diff --git a/.gitattributes b/.gitattributes
index 2d53b50e44..133e2625c1 100644
--- a/.gitattributes
+++ b/.gitattributes
@@ -15,16 +15,13 @@
 # These should also not be modified by git.
 tests/basics/string_cr_conversion.py -text
 tests/basics/string_crlf_conversion.py -text
-stmhal/pybcdc.inf_template -text
-stmhal/usbd_* -text
-stmhal/boards/*/stm32f4xx_hal_conf.h -text
-stmhal/cmsis/** -text
-stmhal/hal/** -text
-stmhal/usbdev/** -text
-stmhal/usbhost/** -text
-cc3200/hal/aes.c -text
-cc3200/hal/aes.h -text
-cc3200/hal/des.c -text
-cc3200/hal/i2s.c -text
-cc3200/hal/i2s.h -text
-cc3200/version.h -text
+ports/stm32/pybcdc.inf_template -text
+ports/stm32/usbd_* -text
+ports/stm32/usbdev/** -text
+ports/stm32/usbhost/** -text
+ports/cc3200/hal/aes.c -text
+ports/cc3200/hal/aes.h -text
+ports/cc3200/hal/des.c -text
+ports/cc3200/hal/i2s.c -text
+ports/cc3200/hal/i2s.h -text
+ports/cc3200/version.h -text
diff --git a/.gitmodules b/.gitmodules
index 0cd28519d8..adf0c871a2 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -11,19 +11,12 @@
 [submodule "lib/berkeley-db-1.xx"]
 	path = lib/berkeley-db-1.xx
 	url = https://github.com/pfalcon/berkeley-db-1.xx
-[submodule "freetouch2"]
-	path = atmel-samd/freetouch
-	url = https://github.com/adafruit/Adafruit_FreeTouch.git
 [submodule "tools/uf2"]
 	path = tools/uf2
 	url = https://github.com/Microsoft/uf2.git
 [submodule "atmel-samd/frozen/Adafruit_CircuitPython_NeoPixel"]
 	path = frozen/Adafruit_CircuitPython_NeoPixel
 	url = https://github.com/adafruit/Adafruit_CircuitPython_NeoPixel
-[submodule "atmel-samd/asf4"]
-	path = atmel-samd/asf4
-	url = https://github.com/adafruit/asf4.git
-	branch = circuitpython
 [submodule "frozen/Adafruit_CircuitPython_Thermistor"]
 	path = frozen/Adafruit_CircuitPython_Thermistor
 	url = https://github.com/adafruit/Adafruit_CircuitPython_Thermistor.git
@@ -33,3 +26,14 @@
 [submodule "frozen/Adafruit_CircuitPython_BusDevice"]
 	path = frozen/Adafruit_CircuitPython_BusDevice
 	url = https://github.com/adafruit/Adafruit_CircuitPython_BusDevice.git
+[submodule "lib/stm32lib"]
+	path = lib/stm32lib
+	url = https://github.com/micropython/stm32lib
+	branch = work-F4-1.13.1+F7-1.5.0+L4-1.3.0
+[submodule "freetouch2"]
+       path = ports/atmel-samd/freetouch
+       url = https://github.com/adafruit/Adafruit_FreeTouch.git
+[submodule "atmel-samd/asf4"]
+       path = ports/atmel-samd/asf4
+       url = https://github.com/adafruit/asf4.git
+       branch = circuitpython
diff --git a/.travis.yml b/.travis.yml
index 93ed835aad..b137a234b1 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -37,41 +37,55 @@ before_script:
   - sudo apt-get install -y --force-yes gcc-arm-embedded
   # For teensy build
   - sudo apt-get install realpath
-  # For coverage testing
-  # cpp-coveralls 0.4 conflicts with urllib3 preinstalled in Travis VM
-  - sudo pip install cpp-coveralls==0.3.12
+  # For coverage testing (upgrade is used to get latest urllib3 version)
+  - sudo pip install --upgrade cpp-coveralls
   - gcc --version
   - arm-none-eabi-gcc --version
   - python3 --version
 
 script:
   # Build mpy-cross first because other builds depend on it.
+  - echo 'Building mpy-cross' && echo -en 'travis_fold:start:mpy-cross\\r'
   - make -C mpy-cross
+  - echo -en 'travis_fold:end:mpy-cross\\r'
+  - echo 'Building Adafruit binaries' && echo -en 'travis_fold:start:adafruit-bins\\r'
   - tools/build_adafruit_bins.sh
-  - make -C minimal CROSS=1 build/firmware.bin
-  - ls -l minimal/build/firmware.bin
-  - mkdir -p ${HOME}/persist
+  - echo -en 'travis_fold:end:adafruit-bins\\r'
+  - make -C ports/minimal CROSS=1 build/firmware.bin
+  - ls -l ports/minimal/build/firmware.bin
+  #- mkdir -p ${HOME}/persist
   # Save new firmware for reference, but only if building a main branch, not a pull request
-  - 'if [ "$TRAVIS_PULL_REQUEST" = "false" ]; then cp minimal/build/firmware.bin ${HOME}/persist/; fi'
-  - make -C unix deplibs
-  - make -C unix
-  - make -C bare-arm
-  - make -C qemu-arm test
+  #- 'if [ "$TRAVIS_PULL_REQUEST" = "false" ]; then cp ports/minimal/build/firmware.bin ${HOME}/persist/; fi'
+  - echo 'Building unix' && echo -en 'travis_fold:start:unix\\r'
+  - make -C ports/unix deplibs
+  - make -C ports/unix
+  - make -C ports/unix coverage
+  - echo -en 'travis_fold:end:unix\\r'
+  - echo 'Building qemu' && echo -en 'travis_fold:start:qemu\\r'
+  - make -C ports/qemu-arm test
+  - echo -en 'travis_fold:end:qemu\\r'
 
   # run tests without coverage info
   #- (cd tests && MICROPY_CPYTHON3=python3.4 ./run-tests)
   #- (cd tests && MICROPY_CPYTHON3=python3.4 ./run-tests --emit native)
 
   # run tests with coverage info
-  - make -C unix coverage
-  - (cd tests && MICROPY_CPYTHON3=python3.4 MICROPY_MICROPYTHON=../unix/micropython_coverage ./run-tests)
-  - (cd tests && MICROPY_CPYTHON3=python3.4 MICROPY_MICROPYTHON=../unix/micropython_coverage ./run-tests -d thread)
-  - (cd tests && MICROPY_CPYTHON3=python3.4 MICROPY_MICROPYTHON=../unix/micropython_coverage ./run-tests --emit native)
-  - (cd tests && MICROPY_CPYTHON3=python3.4 MICROPY_MICROPYTHON=../unix/micropython_coverage ./run-tests --via-mpy -d basics float)
+  - echo 'Test all' && echo -en 'travis_fold:start:test_all\\r'
+  - (cd tests && MICROPY_CPYTHON3=python3.4 MICROPY_MICROPYTHON=../ports/unix/micropython_coverage ./run-tests)
+  - echo -en 'travis_fold:end:test_all\\r'
+  - echo 'Test threads' && echo -en 'travis_fold:start:test_threads\\r'
+  - (cd tests && MICROPY_CPYTHON3=python3.4 MICROPY_MICROPYTHON=../ports/unix/micropython_coverage ./run-tests -d thread)
+  - echo -en 'travis_fold:end:test_threads\\r'
+  - echo 'Testing with native' && echo -en 'travis_fold:start:test_native\\r'
+  - (cd tests && MICROPY_CPYTHON3=python3.4 MICROPY_MICROPYTHON=../ports/unix/micropython_coverage ./run-tests --emit native)
+  - echo -en 'travis_fold:end:test_native\\r'
+  - echo 'Testing with mpy' && echo -en 'travis_fold:start:test_mpy\\r'
+  - (cd tests && MICROPY_CPYTHON3=python3.4 MICROPY_MICROPYTHON=../ports/unix/micropython_coverage ./run-tests --via-mpy -d basics float)
+  - echo -en 'travis_fold:end:test_mpy\\r'
 
   # run coveralls coverage analysis (try to, even if some builds/tests failed)
-  #- (cd unix && coveralls --root .. --build-root . --gcov $(which gcov) --gcov-options '\-o build-coverage/' --include py --include extmod)
+  #- (cd ports/unix && coveralls --root ../.. --build-root . --gcov $(which gcov) --gcov-options '\-o build-coverage/' --include py --include extmod)
 
 after_failure:
   - (cd tests && for exp in *.exp; do testbase=$(basename $exp .exp); echo -e "\nFAILURE $testbase"; diff -u $testbase.exp $testbase.out; done)
-  - (grep "FAIL" qemu-arm/build/console.out)
+  - (grep "FAIL" ports/qemu-arm/build/console.out)
diff --git a/README.md b/README.md
index 571a849d0e..5d3b53b1df 100644
--- a/README.md
+++ b/README.md
@@ -177,24 +177,24 @@ CircuitPython:
 Ports include the code unique to a microcontroller line and also
 variations based on the board.
 
-* `atmel-samd` Support for SAMD21 based boards such as [Arduino Zero][],
+* `ports/atmel-samd` Support for SAMD21 based boards such as [Arduino Zero][],
   [Adafruit Feather M0 Basic][], and [Adafruit Feather M0 Bluefruit LE][].
-* `bare-arm` A bare minimum version of MicroPython for ARM MCUs.
-* `cc3200` Support for boards based [CC3200](http://www.ti.com/product/CC3200)
+* `ports/bare-arm` A bare minimum version of MicroPython for ARM MCUs.
+* `ports/cc3200` Support for boards based [CC3200](http://www.ti.com/product/CC3200)
   from TI such as the [WiPy 1.0](https://www.pycom.io/solutions/py-boards/wipy1/).
-* `esp8266` Support for boards based on ESP8266 WiFi modules such as the
+* `ports/esp8266` Support for boards based on ESP8266 WiFi modules such as the
   [Adafruit Feather HUZZAH][].
-* `minimal` A minimal MicroPython port. Start with this if you want
+* `ports/minimal` A minimal MicroPython port. Start with this if you want
   to port MicroPython to another microcontroller.
-* `pic16bit` Support for 16-bit PIC microcontrollers.
-* `qemu-arm` Support for ARM emulation through [QEMU](https://qemu.org).
-* `stmhal` Support for boards based on STM32 microcontrollers including
+* `ports/pic16bit` Support for 16-bit PIC microcontrollers.
+* `ports/qemu-arm` Support for ARM emulation through [QEMU](https://qemu.org).
+* `ports/stm32` Support for boards based on STM32 microcontrollers including
   the MicroPython flagship [PyBoard](https://store.micropython.org/store/#/products/PYBv1_1).
-* `teensy` Support for the Teensy line of boards such as the
+* `ports/teensy` Support for the Teensy line of boards such as the
   [Teensy 3.1](https://www.pjrc.com/teensy/teensy31.html).
-* `unix` Support for UNIX.
-* `windows` Support for [Windows](https://www.microsoft.com/en-us/windows/).
-* `zephyr` Support for [Zephyr](https://www.zephyrproject.org/), a
+* `ports/unix` Support for UNIX.
+* `ports/windows` Support for [Windows](https://www.microsoft.com/en-us/windows/).
+* `ports/zephyr` Support for [Zephyr](https://www.zephyrproject.org/), a
   real-time operating system by the Linux Foundation.
 
 CircuitPython only maintains the `atmel-samd` and `esp8266` ports. The
diff --git a/atmel-samd/freetouch b/atmel-samd/freetouch
deleted file mode 160000
index 7d8a8f9998..0000000000
--- a/atmel-samd/freetouch
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 7d8a8f99989a4de5b3fbf491df956d1aaca2c172
diff --git a/atmel-samd/tools/bossac.exe b/atmel-samd/tools/bossac.exe
deleted file mode 100644
index 228b9012b0..0000000000
Binary files a/atmel-samd/tools/bossac.exe and /dev/null differ
diff --git a/cc3200/misc/mpexception.c b/cc3200/misc/mpexception.c
deleted file mode 100644
index 72b203fae3..0000000000
--- a/cc3200/misc/mpexception.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * This file is part of the MicroPython project, http://micropython.org/
- *
- * The MIT License (MIT)
- *
- * Copyright (c) 2013, 2014 Damien P. George
- * Copyright (c) 2015 Daniel Campora
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include <stdint.h>
-#include <string.h>
-
-#include "py/mpstate.h"
-#include "mpexception.h"
-
-
-/******************************************************************************
-DECLARE PRIVATE FUNCTIONS
- ******************************************************************************/
-STATIC void mpexception_set_user_interrupt (int chr, void *data);
-
-/******************************************************************************
-DECLARE EXPORTED DATA
- ******************************************************************************/
-const char mpexception_value_invalid_arguments[]    = "invalid argument(s) value";
-const char mpexception_num_type_invalid_arguments[] = "invalid argument(s) num/type";
-const char mpexception_uncaught[]                   = "uncaught exception";
-
-int   user_interrupt_char = -1;
-
-/******************************************************************************
-DECLARE PRIVATE DATA
- ******************************************************************************/
-STATIC void *user_interrupt_data = NULL;
-
-/******************************************************************************
-DEFINE PUBLIC FUNCTIONS
- ******************************************************************************/
-
-void mpexception_init0 (void) {
-    // Create an exception object for interrupting through the stdin uart
-    MP_STATE_PORT(mp_const_user_interrupt) = mp_obj_new_exception(&mp_type_KeyboardInterrupt);
-    mpexception_set_user_interrupt (-1, MP_STATE_PORT(mp_const_user_interrupt));
-}
-
-void mpexception_set_interrupt_char (int c) {
-    if (c != -1) {
-        mp_obj_exception_clear_traceback(MP_STATE_PORT(mp_const_user_interrupt));
-    }
-    mpexception_set_user_interrupt(c, MP_STATE_PORT(mp_const_user_interrupt));
-}
-
-// Call this function to raise a pending exception during an interrupt.
-// It will try to raise the exception "softly" by setting the
-// mp_pending_exception variable hoping that the VM will notice it.
-void mpexception_nlr_jump (void *o) {
-    if (MP_STATE_PORT(mp_pending_exception) == MP_OBJ_NULL) {
-        MP_STATE_PORT(mp_pending_exception) = o;
-    }
-}
-
-void mpexception_keyboard_nlr_jump (void) {
-    mpexception_nlr_jump (user_interrupt_data);
-}
-
-/******************************************************************************
-DEFINE PRIVATE FUNCTIONS
- ******************************************************************************/
-
-STATIC void mpexception_set_user_interrupt (int chr, void *data) {
-    user_interrupt_char = chr;
-    user_interrupt_data = data;
-}
diff --git a/docs/esp8266/tutorial/neopixel.rst b/docs/esp8266/tutorial/neopixel.rst
index 245aed6d46..a1537526f3 100644
--- a/docs/esp8266/tutorial/neopixel.rst
+++ b/docs/esp8266/tutorial/neopixel.rst
@@ -20,6 +20,20 @@ To set the colour of pixels use::
     >>> np[1] = (0, 128, 0) # set to green, half brightness
     >>> np[2] = (0, 0, 64)  # set to blue, quarter brightness
 
+For LEDs with more than 3 colours, such as RGBW pixels or RGBY pixels, the
+NeoPixel class takes a ``bpp`` parameter. To setup a NeoPixel object for an
+RGBW Pixel, do the following::
+
+    >>> import machine, neopixel
+    >>> np = neopixel.NeoPixel(machine.Pin(4), 8, bpp=4)
+
+In a 4-bpp mode, remember to use 4-tuples instead of 3-tuples to set the colour.
+For example to set the first three pixels use::
+
+    >>> np[0] = (255, 0, 0, 128) # Orange in an RGBY Setup
+    >>> np[1] = (0, 255, 0, 128) # Yellow-green in an RGBY Setup
+    >>> np[2] = (0, 0, 255, 128) # Green-blue in an RGBY Setup
+
 Then use the ``write()`` method to output the colours to the LEDs::
 
     >>> np.write()
diff --git a/docs/library/btree.rst b/docs/library/btree.rst
index 9322d32e6a..8fac67e8d4 100644
--- a/docs/library/btree.rst
+++ b/docs/library/btree.rst
@@ -76,20 +76,24 @@ Example::
 Functions
 ---------
 
-.. function:: open(stream, \*, flags=0, cachesize=0, pagesize=0, minkeypage=0)
+.. function:: open(stream, \*, flags=0, pagesize=0, cachesize=0, minkeypage=0)
 
    Open a database from a random-access `stream` (like an open file). All
    other parameters are optional and keyword-only, and allow to tweak advanced
    parameters of the database operation (most users will not need them):
 
    * *flags* - Currently unused.
-   * *cachesize* - Suggested maximum memory cache size in bytes. For a
-     board with enough memory using larger values may improve performance.
-     The value is only a recommendation, the module may use more memory if
-     values set too low.
    * *pagesize* - Page size used for the nodes in BTree. Acceptable range
-     is 512-65536. If 0, underlying I/O block size will be used (the best
-     compromise between memory usage and performance).
+     is 512-65536. If 0, a port-specific default will be used, optimized for
+     port's memory usage and/or performance.
+   * *cachesize* - Suggested memory cache size in bytes. For a
+     board with enough memory using larger values may improve performance.
+     Cache policy is as follows: entire cache is not allocated at once;
+     instead, accessing a new page in database will allocate a memory buffer
+     for it, until value specified by *cachesize* is reached. Then, these
+     buffers will be managed using LRU (least recently used) policy. More
+     buffers may still be allocated if needed (e.g., if a database contains
+     big keys and/or values). Allocated cache buffers aren't reclaimed.
    * *minkeypage* - Minimum number of keys to store per page. Default value
      of 0 equivalent to 2.
 
diff --git a/docs/library/framebuf.rst b/docs/library/framebuf.rst
index b92bd08eff..74c9f85649 100644
--- a/docs/library/framebuf.rst
+++ b/docs/library/framebuf.rst
@@ -38,9 +38,9 @@ Constructors
         - *width* is the width of the FrameBuffer in pixels
         - *height* is the height of the FrameBuffer in pixels
         - *format* specifies the type of pixel used in the FrameBuffer;
-          valid values are ``framebuf.MVLSB``, ``framebuf.RGB565``
-          and ``framebuf.GS4_HMSB``. MVLSB is monochrome 1-bit color,
-          RGB565 is RGB 16-bit color, and GS4_HMSB is grayscale 4-bit color.
+          permissible values are listed under Constants below. These set the
+          number of bits used to encode a color value and the layout of these
+          bits in *buffer*.
           Where a color value c is passed to a method, c is a small integer
           with an encoding that is dependent on the format of the FrameBuffer.
         - *stride* is the number of pixels between each horizontal line
@@ -110,8 +110,9 @@ Other methods
     corresponding color will be considered transparent: all pixels with that
     color value will not be drawn.
 
-    This method works between FrameBuffer's utilising different formats, but the
-    resulting colors may be unexpected due to the mismatch in color formats.
+    This method works between FrameBuffer instances utilising different formats,
+    but the resulting colors may be unexpected due to the mismatch in color
+    formats.
 
 Constants
 ---------
diff --git a/docs/library/machine.Signal.rst b/docs/library/machine.Signal.rst
index 4869086274..a1a29164b2 100644
--- a/docs/library/machine.Signal.rst
+++ b/docs/library/machine.Signal.rst
@@ -4,17 +4,44 @@
 class Signal -- control and sense external I/O devices
 ======================================================
 
-The Signal class is a simple extension of Pin class. Unlike Pin, which
+The Signal class is a simple extension of the `Pin` class. Unlike Pin, which
 can be only in "absolute" 0 and 1 states, a Signal can be in "asserted"
 (on) or "deasserted" (off) states, while being inverted (active-low) or
-not. Summing up, it adds logical inversion support to Pin functionality.
+not. In other words, it adds logical inversion support to Pin functionality.
 While this may seem a simple addition, it is exactly what is needed to
 support wide array of simple digital devices in a way portable across
 different boards, which is one of the major MicroPython goals. Regardless
-whether different users have an active-high or active-low LED, a normally
-open or normally closed relay - you can develop single, nicely looking
+of whether different users have an active-high or active-low LED, a normally
+open or normally closed relay - you can develop a single, nicely looking
 application which works with each of them, and capture hardware
-configuration differences in few lines on the config file of your app.
+configuration differences in few lines in the config file of your app.
+
+Example::
+
+    from machine import Pin, Signal
+
+    # Suppose you have an active-high LED on pin 0
+    led1_pin = Pin(0, Pin.OUT)
+    # ... and active-low LED on pin 1
+    led2_pin = Pin(1, Pin.OUT)
+
+    # Now to light up both of them using Pin class, you'll need to set
+    # them to different values
+    led1_pin.value(1)
+    led2_pin.value(0)
+
+    # Signal class allows to abstract away active-high/active-low
+    # difference
+    led1 = Signal(led1_pin, invert=False)
+    led2 = Signal(led2_pin, invert=True)
+
+    # Now lighting up them looks the same
+    led1.value(1)
+    led2.value(1)
+
+    # Even better:
+    led1.on()
+    led2.on()
 
 Following is the guide when Signal vs Pin should be used:
 
@@ -33,11 +60,11 @@ architecture of MicroPython: Pin offers the lowest overhead, which may
 be important when bit-banging protocols. But Signal adds additional
 flexibility on top of Pin, at the cost of minor overhead (much smaller
 than if you implemented active-high vs active-low device differences in
-Python manually!). Also, Pin is low-level object which needs to be
+Python manually!). Also, Pin is a low-level object which needs to be
 implemented for each support board, while Signal is a high-level object
 which comes for free once Pin is implemented.
 
-If in doubt, give the Signal a try! Once again, it is developed to save
+If in doubt, give the Signal a try! Once again, it is offered to save
 developers from the need to handle unexciting differences like active-low
 vs active-high signals, and allow other users to share and enjoy your
 application, instead of being frustrated by the fact that it doesn't
diff --git a/docs/library/micropython.rst b/docs/library/micropython.rst
index 4ff0b0c159..c13a7391bb 100644
--- a/docs/library/micropython.rst
+++ b/docs/library/micropython.rst
@@ -46,7 +46,7 @@ Functions
 
 .. function:: mem_info([verbose])
 
-   Print information about currently used memory.  If the *verbose`* argument
+   Print information about currently used memory.  If the *verbose* argument
    is given then extra information is printed.
 
    The information that is printed is implementation dependent, but currently
diff --git a/docs/library/network.rst b/docs/library/network.rst
index de93c0e01d..def6bee74e 100644
--- a/docs/library/network.rst
+++ b/docs/library/network.rst
@@ -9,7 +9,7 @@ This module provides network drivers and routing configuration. To use this
 module, a MicroPython variant/build with network capabilities must be installed.
 Network drivers for specific hardware are available within this module and are
 used to configure hardware network interface(s). Network services provided
-by configured interfaces are then available for use via the :mod:`socket`
+by configured interfaces are then available for use via the :mod:`usocket`
 module.
 
 For example::
@@ -39,9 +39,9 @@ Common network adapter interface
 ================================
 
 This section describes an (implied) abstract base class for all network
-interface classes implemented by different ports of MicroPython for
-different hardware. This means that MicroPython does not actually
-provide `AbstractNIC` class, but any actual NIC class, as described
+interface classes implemented by `MicroPython ports <MicroPython port>`
+for different hardware. This means that MicroPython does not actually
+provide ``AbstractNIC`` class, but any actual NIC class, as described
 in the following sections, implements methods as described here.
 
 .. class:: AbstractNIC(id=None, ...)
@@ -411,7 +411,7 @@ parameter should be `id`.
         print(ap.config('channel'))
 
        Following are commonly supported parameters (availability of a specific parameter
-       depends on network technology type, driver, and MicroPython port).
+       depends on network technology type, driver, and `MicroPython port`).
 
        =========  ===========
        Parameter  Description
diff --git a/docs/library/uos.rst b/docs/library/uos.rst
index 7c52c1eead..43bf69cc0a 100644
--- a/docs/library/uos.rst
+++ b/docs/library/uos.rst
@@ -89,8 +89,22 @@ Functions
    Return a bytes object with n random bytes. Whenever possible, it is
    generated by the hardware random number generator.
 
-.. function:: dupterm(stream_object)
+.. function:: dupterm(stream_object, index=0)
 
-   Duplicate or switch MicroPython terminal (the REPL) on the passed stream-like
-   object. The given object must implement the ``readinto()`` and ``write()``
-   methods. If ``None`` is passed, previously set redirection is cancelled.
+   Duplicate or switch the MicroPython terminal (the REPL) on the given stream-like
+   object. The *stream_object* argument must implement the ``readinto()`` and
+   ``write()`` methods.  The stream should be in non-blocking mode and
+   ``readinto()`` should return ``None`` if there is no data available for reading.
+
+   After calling this function all terminal output is repeated on this stream,
+   and any input that is available on the stream is passed on to the terminal input.
+
+   The *index* parameter should be a non-negative integer and specifies which
+   duplication slot is set.  A given port may implement more than one slot (slot 0
+   will always be available) and in that case terminal input and output is
+   duplicated on all the slots that are set.
+
+   If ``None`` is passed as the *stream_object* then duplication is cancelled on
+   the slot given by *index*.
+
+   The function returns the previous stream-like object in the given slot.
diff --git a/docs/library/usocket.rst b/docs/library/usocket.rst
index 65e24e2662..dfdcd68bc9 100644
--- a/docs/library/usocket.rst
+++ b/docs/library/usocket.rst
@@ -117,12 +117,12 @@ Constants
 .. data:: usocket.SOL_*
 
    Socket option levels (an argument to `setsockopt()`). The exact
-   inventory depends on a MicroPython port.
+   inventory depends on a `MicroPython port`.
 
 .. data:: usocket.SO_*
 
    Socket options (an argument to `setsockopt()`). The exact
-   inventory depends on a MicroPython port.
+   inventory depends on a `MicroPython port`.
 
 Constants specific to WiPy:
 
diff --git a/docs/pyboard/tutorial/pass_through.rst b/docs/pyboard/tutorial/pass_through.rst
index a94e7363d2..012a907648 100644
--- a/docs/pyboard/tutorial/pass_through.rst
+++ b/docs/pyboard/tutorial/pass_through.rst
@@ -15,4 +15,4 @@ It's as simple as::
             if uart.any():
                 usb.write(uart.read(256))
 
-    pass_through(pyb.USB_VCP(), pyb.UART(1, 9600))
+    pass_through(pyb.USB_VCP(), pyb.UART(1, 9600, timeout=0))
diff --git a/docs/reference/constrained.rst b/docs/reference/constrained.rst
index 14286aa262..e7de459bc9 100644
--- a/docs/reference/constrained.rst
+++ b/docs/reference/constrained.rst
@@ -279,7 +279,7 @@ After importing the modules, execute:
 
 Then copy and paste all the Q(xxx) lines into a text editor. Check for and
 remove lines which are obviously invalid. Open the file qstrdefsport.h which
-will be found in stmhal (or the equivalent directory for the architecture in
+will be found in ports/stm32 (or the equivalent directory for the architecture in
 use). Copy and paste the corrected lines at the end of the file. Save the file,
 rebuild and flash the firmware. The outcome can be checked by importing the
 modules and again issuing:
diff --git a/docs/reference/glossary.rst b/docs/reference/glossary.rst
index 98979afa92..4cd3d84cc5 100644
--- a/docs/reference/glossary.rst
+++ b/docs/reference/glossary.rst
@@ -56,9 +56,9 @@ Glossary
         which provides implementations for many modules from CPython's
         standard library. However, large subset of these modules require
         POSIX-like environment (Linux, MacOS, Windows may be partially
-        supported), and thus would work or make sense only with MicroPython
-        Unix port. Some subset of modules is however usable for baremetal ports
-        too.
+        supported), and thus would work or make sense only with
+        `MicroPython Unix port`. Some subset of modules is however usable
+        for `baremetal` ports too.
 
         Unlike monolithic :term:`CPython` stdlib, micropython-lib modules
         are intended to be installed individually - either using manual
diff --git a/docs/reference/isr_rules.rst b/docs/reference/isr_rules.rst
index 23dcfd01f4..5009f30f79 100644
--- a/docs/reference/isr_rules.rst
+++ b/docs/reference/isr_rules.rst
@@ -21,6 +21,7 @@ This summarises the points detailed below and lists the principal recommendation
 
 * Keep the code as short and simple as possible.
 * Avoid memory allocation: no appending to lists or insertion into dictionaries, no floating point.
+* Consider using ``micropython.schedule`` to work around the above constraint.
 * Where an ISR returns multiple bytes use a pre-allocated ``bytearray``. If multiple integers are to be
   shared between an ISR and the main program consider an array (``array.array``).
 * Where data is shared between the main program and an ISR, consider disabling interrupts prior to accessing
@@ -158,6 +159,26 @@ On platforms with hardware floating point (such as the Pyboard) the inline ARM T
 round this limitation. This is because the processor stores float values in a machine word; values can be shared
 between the ISR and main program code via an array of floats.
 
+Using micropython.schedule
+~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+This function enables an ISR to schedule a callback for execution "very soon". The callback is queued for
+execution which will take place at a time when the heap is not locked. Hence it can create Python objects
+and use floats. The callback is also guaranteed to run at a time when the main program has completed any
+update of Python objects, so the callback will not encounter partially updated objects.
+
+Typical usage is to handle sensor hardware. The ISR acquires data from the hardware and enables it to
+issue a further interrupt. It then schedules a callback to process the data.
+
+Scheduled callbacks should comply with the principles of interrupt handler design outlined below. This is to
+avoid problems resulting from I/O activity and the modification of shared data which can arise in any code
+which pre-empts the main program loop.
+
+Execution time needs to be considered in relation to the frequency with which interrupts can occur. If an
+interrupt occurs while the previous callback is executing, a further instance of the callback will be queued
+for execution; this will run after the current instance has completed. A sustained high interrupt repetition
+rate therefore carries a risk of unconstrained queue growth and eventual failure with a ``RuntimeError``.
+
 Exceptions
 ----------
 
diff --git a/drivers/cc3000/src/ccspi.c b/drivers/cc3000/src/ccspi.c
index 64900efe46..820be809b3 100644
--- a/drivers/cc3000/src/ccspi.c
+++ b/drivers/cc3000/src/ccspi.c
@@ -34,8 +34,6 @@
 
 #include <string.h>
 
-#include "py/nlr.h"
-#include "py/obj.h"
 #include "py/runtime.h"
 #include "pin.h"
 #include "led.h"
diff --git a/drivers/display/ssd1306.py b/drivers/display/ssd1306.py
index 53bcb0d2de..d65f2d3502 100644
--- a/drivers/display/ssd1306.py
+++ b/drivers/display/ssd1306.py
@@ -32,7 +32,21 @@ class SSD1306:
         self.external_vcc = external_vcc
         self.pages = self.height // 8
         self.buffer = bytearray(self.pages * self.width)
-        self.framebuf = framebuf.FrameBuffer(self.buffer, self.width, self.height, framebuf.MVLSB)
+        fb = framebuf.FrameBuffer(self.buffer, self.width, self.height, framebuf.MONO_VLSB)
+        self.framebuf = fb
+        # Provide methods for accessing FrameBuffer graphics primitives. This is a
+        # workround because inheritance from a native class is currently unsupported.
+        # http://docs.micropython.org/en/latest/pyboard/library/framebuf.html
+        self.fill = fb.fill
+        self.pixel = fb.pixel
+        self.hline = fb.hline
+        self.vline = fb.vline
+        self.line = fb.line
+        self.rect = fb.rect
+        self.fill_rect = fb.fill_rect
+        self.text = fb.text
+        self.scroll = fb.scroll
+        self.blit = fb.blit
         self.poweron()
         self.init_display()
 
@@ -88,18 +102,6 @@ class SSD1306:
         self.write_cmd(self.pages - 1)
         self.write_data(self.buffer)
 
-    def fill(self, col):
-        self.framebuf.fill(col)
-
-    def pixel(self, x, y, col):
-        self.framebuf.pixel(x, y, col)
-
-    def scroll(self, dx, dy):
-        self.framebuf.scroll(dx, dy)
-
-    def text(self, string, x, y, col=1):
-        self.framebuf.text(string, x, y, col)
-
 
 class SSD1306_I2C(SSD1306):
     def __init__(self, width, height, i2c, addr=0x3c, external_vcc=False):
diff --git a/drivers/memory/spiflash.c b/drivers/memory/spiflash.c
index 214610e0a2..08564d0540 100644
--- a/drivers/memory/spiflash.c
+++ b/drivers/memory/spiflash.c
@@ -49,10 +49,8 @@ STATIC uint8_t buf[SECTOR_SIZE];
 void mp_spiflash_init(mp_spiflash_t *self) {
     mp_hal_pin_write(self->cs, 1);
     mp_hal_pin_output(self->cs);
-    mp_hal_pin_write(self->spi.sck, 0);
-    mp_hal_pin_output(self->spi.sck);
-    mp_hal_pin_output(self->spi.mosi);
-    mp_hal_pin_input(self->spi.miso);
+    const mp_machine_spi_p_t *protocol = self->spi->type->protocol;
+    protocol->init(self->spi, 0, NULL, (mp_map_t*)&mp_const_empty_map);
 }
 
 STATIC void mp_spiflash_acquire_bus(mp_spiflash_t *self) {
@@ -66,7 +64,8 @@ STATIC void mp_spiflash_release_bus(mp_spiflash_t *self) {
 }
 
 STATIC void mp_spiflash_transfer(mp_spiflash_t *self, size_t len, const uint8_t *src, uint8_t *dest) {
-    mp_machine_soft_spi_transfer(&self->spi.base, len, src, dest);
+    const mp_machine_spi_p_t *protocol = self->spi->type->protocol;
+    protocol->transfer(self->spi, len, src, dest);
 }
 
 STATIC int mp_spiflash_wait_sr(mp_spiflash_t *self, uint8_t mask, uint8_t val, uint32_t timeout) {
diff --git a/drivers/memory/spiflash.h b/drivers/memory/spiflash.h
index 967352b04e..cd96b16f34 100644
--- a/drivers/memory/spiflash.h
+++ b/drivers/memory/spiflash.h
@@ -30,8 +30,7 @@
 
 typedef struct _mp_spiflash_t {
     mp_hal_pin_obj_t cs;
-    // TODO replace with generic SPI object
-    mp_machine_soft_spi_obj_t spi;
+    mp_obj_base_t *spi; // object must have protocol pointing to mp_machine_spi_p_t struct
 } mp_spiflash_t;
 
 void mp_spiflash_init(mp_spiflash_t *self);
diff --git a/drivers/nrf24l01/nrf24l01test.py b/drivers/nrf24l01/nrf24l01test.py
index a25194d387..5413511c3b 100644
--- a/drivers/nrf24l01/nrf24l01test.py
+++ b/drivers/nrf24l01/nrf24l01test.py
@@ -1,8 +1,8 @@
 """Test for nrf24l01 module."""
 
 import struct
-import pyb
-from pyb import Pin, SPI
+import utime
+from machine import Pin, SPI
 from nrf24l01 import NRF24L01
 
 pipes = (b'\xf0\xf0\xf0\xf0\xe1', b'\xf0\xf0\xf0\xf0\xd2')
@@ -24,7 +24,7 @@ def master():
     while num_successes < num_needed and num_failures < num_needed:
         # stop listening and send packet
         nrf.stop_listening()
-        millis = pyb.millis()
+        millis = utime.ticks_ms()
         led_state = max(1, (led_state << 1) & 0x0f)
         print('sending:', millis, led_state)
         try:
@@ -36,10 +36,10 @@ def master():
         nrf.start_listening()
 
         # wait for response, with 250ms timeout
-        start_time = pyb.millis()
+        start_time = utime.ticks_ms()
         timeout = False
         while not nrf.any() and not timeout:
-            if pyb.elapsed_millis(start_time) > 250:
+            if utime.ticks_diff(utime.ticks_ms(), start_time) > 250:
                 timeout = True
 
         if timeout:
@@ -51,11 +51,11 @@ def master():
             got_millis, = struct.unpack('i', nrf.recv())
 
             # print response and round-trip delay
-            print('got response:', got_millis, '(delay', pyb.millis() - got_millis, 'ms)')
+            print('got response:', got_millis, '(delay', utime.ticks_diff(utime.ticks_ms(), got_millis), 'ms)')
             num_successes += 1
 
         # delay then loop
-        pyb.delay(250)
+        utime.sleep_ms(250)
 
     print('master finished sending; successes=%d, failures=%d' % (num_successes, num_failures))
 
@@ -69,18 +69,19 @@ def slave():
     print('NRF24L01 slave mode, waiting for packets... (ctrl-C to stop)')
 
     while True:
-        pyb.wfi()
+        machine.idle()
         if nrf.any():
             while nrf.any():
                 buf = nrf.recv()
                 millis, led_state = struct.unpack('ii', buf)
                 print('received:', millis, led_state)
-                for i in range(4):
-                    if led_state & (1 << i):
-                        pyb.LED(i + 1).on()
+                for led in leds:
+                    if led_state & 1:
+                        led.on()
                     else:
-                        pyb.LED(i + 1).off()
-                pyb.delay(15)
+                        led.off()
+                    led_state >>= 1
+                utime.sleep_ms(15)
 
             nrf.stop_listening()
             try:
@@ -90,6 +91,12 @@ def slave():
             print('sent response')
             nrf.start_listening()
 
+try:
+    import pyb
+    leds = [pyb.LED(i + 1) for i in range(4)]
+except:
+    leds = []
+
 print('NRF24L01 test module loaded')
 print('NRF24L01 pinout for test:')
 print('    CE on Y4')
diff --git a/esp8266/modules/ds18x20.py b/esp8266/modules/ds18x20.py
deleted file mode 120000
index faae59d909..0000000000
--- a/esp8266/modules/ds18x20.py
+++ /dev/null
@@ -1 +0,0 @@
-../../drivers/onewire/ds18x20.py
\ No newline at end of file
diff --git a/esp8266/modules/onewire.py b/esp8266/modules/onewire.py
deleted file mode 120000
index f6ec745e85..0000000000
--- a/esp8266/modules/onewire.py
+++ /dev/null
@@ -1 +0,0 @@
-../../drivers/onewire/onewire.py
\ No newline at end of file
diff --git a/esp8266/modules/upip.py b/esp8266/modules/upip.py
deleted file mode 120000
index 20d52a4ab7..0000000000
--- a/esp8266/modules/upip.py
+++ /dev/null
@@ -1 +0,0 @@
-../../tools/upip.py
\ No newline at end of file
diff --git a/esp8266/modules/upip_utarfile.py b/esp8266/modules/upip_utarfile.py
deleted file mode 120000
index 1498862916..0000000000
--- a/esp8266/modules/upip_utarfile.py
+++ /dev/null
@@ -1 +0,0 @@
-../../tools/upip_utarfile.py
\ No newline at end of file
diff --git a/examples/pins.py b/examples/pins.py
index ab359f6921..aafdb48133 100644
--- a/examples/pins.py
+++ b/examples/pins.py
@@ -1,5 +1,5 @@
 # Print a nice list of pins, their current settings, and available afs.
-# Requires pins_af.py from stmhal/build-PYBV10/ directory.
+# Requires pins_af.py from ports/stm32/build-PYBV10/ directory.
 
 import pyb
 import pins_af
diff --git a/extmod/machine_i2c.c b/extmod/machine_i2c.c
index c0a51a6e7f..5d441b1ba7 100644
--- a/extmod/machine_i2c.c
+++ b/extmod/machine_i2c.c
@@ -269,7 +269,7 @@ int mp_machine_soft_i2c_readfrom(mp_obj_base_t *self_in, uint16_t addr, uint8_t
 /******************************************************************************/
 // MicroPython bindings for I2C
 
-STATIC void machine_i2c_obj_init_helper(machine_i2c_obj_t *self, mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC void machine_i2c_obj_init_helper(machine_i2c_obj_t *self, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     enum { ARG_scl, ARG_sda, ARG_freq, ARG_timeout };
     static const mp_arg_t allowed_args[] = {
         { MP_QSTR_scl, MP_ARG_REQUIRED | MP_ARG_OBJ },
diff --git a/extmod/machine_mem.c b/extmod/machine_mem.c
index af987cb7f7..b9f16507c4 100644
--- a/extmod/machine_mem.c
+++ b/extmod/machine_mem.c
@@ -24,8 +24,8 @@
  * THE SOFTWARE.
  */
 
+#include "py/runtime.h"
 #include "extmod/machine_mem.h"
-#include "py/nlr.h"
 
 #if MICROPY_PY_MACHINE
 
diff --git a/extmod/machine_pinbase.c b/extmod/machine_pinbase.c
index 3c1f094834..070c5cde9d 100644
--- a/extmod/machine_pinbase.c
+++ b/extmod/machine_pinbase.c
@@ -30,6 +30,7 @@
 #include "py/obj.h"
 #include "py/runtime.h"
 #include "extmod/virtpin.h"
+#include "extmod/machine_pinbase.h"
 
 // PinBase class
 
@@ -40,10 +41,8 @@ typedef struct _mp_pinbase_t {
     mp_obj_base_t base;
 } mp_pinbase_t;
 
-STATIC const mp_obj_type_t pinbase_type;
-
-STATIC mp_pinbase_t pinbase_singleton = {
-    .base = { &pinbase_type },
+STATIC const mp_pinbase_t pinbase_singleton = {
+    .base = { &machine_pinbase_type },
 };
 
 STATIC mp_obj_t pinbase_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args) {
diff --git a/extmod/modbtree.c b/extmod/modbtree.c
index 229daaf0f9..5c13115328 100644
--- a/extmod/modbtree.c
+++ b/extmod/modbtree.c
@@ -29,9 +29,7 @@
 #include <errno.h> // for declaration of global errno variable
 #include <fcntl.h>
 
-#include "py/nlr.h"
 #include "py/runtime.h"
-#include "py/runtime0.h"
 #include "py/stream.h"
 
 #if MICROPY_PY_BTREE
@@ -281,7 +279,7 @@ STATIC mp_obj_t btree_subscr(mp_obj_t self_in, mp_obj_t index, mp_obj_t value) {
     }
 }
 
-STATIC mp_obj_t btree_binary_op(mp_uint_t op, mp_obj_t lhs_in, mp_obj_t rhs_in) {
+STATIC mp_obj_t btree_binary_op(mp_binary_op_t op, mp_obj_t lhs_in, mp_obj_t rhs_in) {
     mp_obj_btree_t *self = MP_OBJ_TO_PTR(lhs_in);
     switch (op) {
         case MP_BINARY_OP_IN: {
diff --git a/extmod/modframebuf.c b/extmod/modframebuf.c
index f4e8571297..20e40d5791 100644
--- a/extmod/modframebuf.c
+++ b/extmod/modframebuf.c
@@ -27,13 +27,11 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "py/nlr.h"
-#include "py/obj.h"
 #include "py/runtime.h"
 
 #if MICROPY_PY_FRAMEBUF
 
-#include "stmhal/font_petme128_8x8.h"
+#include "ports/stm32/font_petme128_8x8.h"
 
 typedef struct _mp_obj_framebuf_t {
     mp_obj_base_t base;
diff --git a/extmod/modlwip.c b/extmod/modlwip.c
index cc10523e54..f7e776af91 100644
--- a/extmod/modlwip.c
+++ b/extmod/modlwip.c
@@ -29,7 +29,6 @@
 #include <string.h>
 #include <stdio.h>
 
-#include "py/nlr.h"
 #include "py/objlist.h"
 #include "py/runtime.h"
 #include "py/stream.h"
@@ -1070,7 +1069,7 @@ STATIC mp_obj_t lwip_socket_setblocking(mp_obj_t self_in, mp_obj_t flag_in) {
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_2(lwip_socket_setblocking_obj, lwip_socket_setblocking);
 
-STATIC mp_obj_t lwip_socket_setsockopt(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t lwip_socket_setsockopt(size_t n_args, const mp_obj_t *args) {
     (void)n_args; // always 4
     lwip_socket_obj_t *socket = args[0];
 
@@ -1120,7 +1119,7 @@ STATIC mp_obj_t lwip_socket_setsockopt(mp_uint_t n_args, const mp_obj_t *args) {
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(lwip_socket_setsockopt_obj, 4, 4, lwip_socket_setsockopt);
 
-STATIC mp_obj_t lwip_socket_makefile(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t lwip_socket_makefile(size_t n_args, const mp_obj_t *args) {
     (void)n_args;
     return args[0];
 }
diff --git a/extmod/modubinascii.c b/extmod/modubinascii.c
index 25fc8852ac..8256a50cf2 100644
--- a/extmod/modubinascii.c
+++ b/extmod/modubinascii.c
@@ -28,13 +28,10 @@
 #include <assert.h>
 #include <string.h>
 
-#include "py/nlr.h"
 #include "py/runtime.h"
 #include "py/binary.h"
 #include "extmod/modubinascii.h"
 
-#include "uzlib/tinf.h"
-
 mp_obj_t mod_binascii_hexlify(size_t n_args, const mp_obj_t *args) {
     // Second argument is for an extension to allow a separator to be used
     // between values.
@@ -221,6 +218,8 @@ mp_obj_t mod_binascii_b2a_base64(mp_obj_t data) {
 MP_DEFINE_CONST_FUN_OBJ_1(mod_binascii_b2a_base64_obj, mod_binascii_b2a_base64);
 
 #if MICROPY_PY_UBINASCII_CRC32
+#include "uzlib/tinf.h"
+
 mp_obj_t mod_binascii_crc32(size_t n_args, const mp_obj_t *args) {
     mp_buffer_info_t bufinfo;
     mp_get_buffer_raise(args[0], &bufinfo, MP_BUFFER_READ);
diff --git a/extmod/moductypes.c b/extmod/moductypes.c
index ffa974f636..b0f28331e9 100644
--- a/extmod/moductypes.c
+++ b/extmod/moductypes.c
@@ -28,7 +28,6 @@
 #include <string.h>
 #include <stdint.h>
 
-#include "py/nlr.h"
 #include "py/runtime.h"
 #include "py/objtuple.h"
 #include "py/binary.h"
diff --git a/extmod/moduhashlib.c b/extmod/moduhashlib.c
index f3beb39399..3fad69247e 100644
--- a/extmod/moduhashlib.c
+++ b/extmod/moduhashlib.c
@@ -27,7 +27,6 @@
 #include <assert.h>
 #include <string.h>
 
-#include "py/nlr.h"
 #include "py/runtime.h"
 
 #if MICROPY_PY_UHASHLIB
diff --git a/extmod/moduheapq.c b/extmod/moduheapq.c
index 4a620bad81..71c15368bf 100644
--- a/extmod/moduheapq.c
+++ b/extmod/moduheapq.c
@@ -24,9 +24,7 @@
  * THE SOFTWARE.
  */
 
-#include "py/nlr.h"
 #include "py/objlist.h"
-#include "py/runtime0.h"
 #include "py/runtime.h"
 
 #if MICROPY_PY_UHEAPQ
diff --git a/extmod/modujson.c b/extmod/modujson.c
index 6c4aa1611d..f14682d26f 100644
--- a/extmod/modujson.c
+++ b/extmod/modujson.c
@@ -26,7 +26,6 @@
 
 #include <stdio.h>
 
-#include "py/nlr.h"
 #include "py/objlist.h"
 #include "py/objstringio.h"
 #include "py/parsenum.h"
diff --git a/extmod/modurandom.c b/extmod/modurandom.c
index 4b63dace4d..1512a3fd4a 100644
--- a/extmod/modurandom.c
+++ b/extmod/modurandom.c
@@ -27,7 +27,6 @@
 #include <assert.h>
 #include <string.h>
 
-//#include "py/nlr.h"
 #include "py/runtime.h"
 
 #if MICROPY_PY_URANDOM
diff --git a/extmod/modure.c b/extmod/modure.c
index 2baebdecc6..78de4706d2 100644
--- a/extmod/modure.c
+++ b/extmod/modure.c
@@ -28,13 +28,15 @@
 #include <assert.h>
 #include <string.h>
 
-#include "py/nlr.h"
 #include "py/runtime.h"
 #include "py/binary.h"
 #include "py/objstr.h"
+#include "py/stackctrl.h"
 
 #if MICROPY_PY_URE
 
+#define re1_5_stack_chk() MP_STACK_CHECK()
+
 #include "re1.5/re1.5.h"
 
 #define FLAG_DEBUG 0x1000
diff --git a/extmod/modussl_axtls.c b/extmod/modussl_axtls.c
index b5d2412d26..88a89a23d4 100644
--- a/extmod/modussl_axtls.c
+++ b/extmod/modussl_axtls.c
@@ -27,7 +27,6 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "py/nlr.h"
 #include "py/runtime.h"
 #include "py/stream.h"
 
diff --git a/extmod/modussl_mbedtls.c b/extmod/modussl_mbedtls.c
index 12ec60a756..d7316cb4ae 100644
--- a/extmod/modussl_mbedtls.c
+++ b/extmod/modussl_mbedtls.c
@@ -31,10 +31,8 @@
 #include <string.h>
 #include <errno.h> // needed because mp_is_nonblocking_error uses system error codes
 
-#include "py/nlr.h"
 #include "py/runtime.h"
 #include "py/stream.h"
-#include "py/obj.h"
 
 // mbedtls_time_t
 #include "mbedtls/platform.h"
@@ -67,7 +65,7 @@ struct ssl_args {
 
 STATIC const mp_obj_type_t ussl_socket_type;
 
-static void mbedtls_debug(void *ctx, int level, const char *file, int line, const char *str) {
+void mbedtls_debug(void *ctx, int level, const char *file, int line, const char *str) {
     printf("DBG:%s:%04d: %s\n", file, line, str);
 }
 
@@ -123,8 +121,10 @@ STATIC mp_obj_ssl_socket_t *socket_new(mp_obj_t sock, struct ssl_args *args) {
     mbedtls_x509_crt_init(&o->cert);
     mbedtls_pk_init(&o->pkey);
     mbedtls_ctr_drbg_init(&o->ctr_drbg);
+    #ifdef MBEDTLS_DEBUG_C
     // Debug level (0-4)
     mbedtls_debug_set_threshold(0);
+    #endif
 
     mbedtls_entropy_init(&o->entropy);
     const byte seed[] = "upy";
@@ -144,7 +144,9 @@ STATIC mp_obj_ssl_socket_t *socket_new(mp_obj_t sock, struct ssl_args *args) {
 
     mbedtls_ssl_conf_authmode(&o->conf, MBEDTLS_SSL_VERIFY_NONE);
     mbedtls_ssl_conf_rng(&o->conf, mbedtls_ctr_drbg_random, &o->ctr_drbg);
+    #ifdef MBEDTLS_DEBUG_C
     mbedtls_ssl_conf_dbg(&o->conf, mbedtls_debug, NULL);
+    #endif
 
     ret = mbedtls_ssl_setup(&o->ssl, &o->conf);
     if (ret != 0) {
diff --git a/extmod/modutimeq.c b/extmod/modutimeq.c
index e54415b28f..0a836c7cc8 100644
--- a/extmod/modutimeq.c
+++ b/extmod/modutimeq.c
@@ -27,9 +27,7 @@
 
 #include <string.h>
 
-#include "py/nlr.h"
 #include "py/objlist.h"
-#include "py/runtime0.h"
 #include "py/runtime.h"
 #include "py/smallint.h"
 
@@ -189,7 +187,7 @@ STATIC mp_obj_t mod_utimeq_dump(mp_obj_t heap_in) {
 STATIC MP_DEFINE_CONST_FUN_OBJ_1(mod_utimeq_dump_obj, mod_utimeq_dump);
 #endif
 
-STATIC mp_obj_t utimeq_unary_op(mp_uint_t op, mp_obj_t self_in) {
+STATIC mp_obj_t utimeq_unary_op(mp_unary_op_t op, mp_obj_t self_in) {
     mp_obj_utimeq_t *self = MP_OBJ_TO_PTR(self_in);
     switch (op) {
         case MP_UNARY_OP_BOOL: return mp_obj_new_bool(self->len != 0);
diff --git a/extmod/moduzlib.c b/extmod/moduzlib.c
index b446dba737..e9af07370e 100644
--- a/extmod/moduzlib.c
+++ b/extmod/moduzlib.c
@@ -27,7 +27,6 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "py/nlr.h"
 #include "py/runtime.h"
 #include "py/stream.h"
 #include "py/mperrno.h"
diff --git a/extmod/modwebrepl.c b/extmod/modwebrepl.c
index b0d146c236..c5087ac293 100644
--- a/extmod/modwebrepl.c
+++ b/extmod/modwebrepl.c
@@ -28,8 +28,6 @@
 #include <stdint.h>
 #include <string.h>
 
-#include "py/nlr.h"
-#include "py/obj.h"
 #include "py/runtime.h"
 #include "py/stream.h"
 #include "py/builtin.h"
diff --git a/extmod/modwebsocket.c b/extmod/modwebsocket.c
index 6c6e32c1a2..a651164b2f 100644
--- a/extmod/modwebsocket.c
+++ b/extmod/modwebsocket.c
@@ -28,8 +28,6 @@
 #include <stdint.h>
 #include <string.h>
 
-#include "py/nlr.h"
-#include "py/obj.h"
 #include "py/runtime.h"
 #include "py/stream.h"
 #include "extmod/modwebsocket.h"
diff --git a/extmod/re1.5/compilecode.c b/extmod/re1.5/compilecode.c
index e4635f034a..3267a4190d 100644
--- a/extmod/re1.5/compilecode.c
+++ b/extmod/re1.5/compilecode.c
@@ -55,7 +55,7 @@ static const char *_compilecode(const char *re, ByteProg *prog, int sizecode)
             for (cnt = 0; *re != ']'; re++, cnt++) {
                 if (!*re) return NULL;
                 EMIT(PC++, *re);
-                if (re[1] == '-') {
+                if (re[1] == '-' && re[2] != ']') {
                     re += 2;
                 }
                 EMIT(PC++, *re);
diff --git a/extmod/re1.5/re1.5.h b/extmod/re1.5/re1.5.h
index 815c5d33d1..ba6f97b743 100644
--- a/extmod/re1.5/re1.5.h
+++ b/extmod/re1.5/re1.5.h
@@ -48,6 +48,9 @@ void printre(Regexp*);
 #ifndef re1_5_fatal
 void re1_5_fatal(char*);
 #endif
+#ifndef re1_5_stack_chk
+#define re1_5_stack_chk()
+#endif
 void *mal(int);
 
 struct Prog
diff --git a/extmod/re1.5/recursiveloop.c b/extmod/re1.5/recursiveloop.c
index e8fef03049..bb337decfb 100644
--- a/extmod/re1.5/recursiveloop.c
+++ b/extmod/re1.5/recursiveloop.c
@@ -9,7 +9,9 @@ recursiveloop(char *pc, const char *sp, Subject *input, const char **subp, int n
 {
 	const char *old;
 	int off;
-	
+
+	re1_5_stack_chk();
+
 	for(;;) {
 		if(inst_is_consumer(*pc)) {
 			// If we need to match a character, but there's none left, it's fail
diff --git a/extmod/uos_dupterm.c b/extmod/uos_dupterm.c
index 16d1d54516..54fb23a797 100644
--- a/extmod/uos_dupterm.c
+++ b/extmod/uos_dupterm.c
@@ -27,7 +27,6 @@
 #include <string.h>
 #include "py/mpconfig.h"
 
-#include "py/nlr.h"
 #include "py/runtime.h"
 #include "py/objtuple.h"
 #include "py/objarray.h"
@@ -68,7 +67,7 @@ void mp_uos_dupterm_tx_strn(const char *str, size_t len) {
     }
 }
 
-STATIC mp_obj_t mp_uos_dupterm(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t mp_uos_dupterm(size_t n_args, const mp_obj_t *args) {
     if (n_args == 0) {
         if (MP_STATE_PORT(term_obj) == MP_OBJ_NULL) {
             return mp_const_none;
diff --git a/extmod/vfs.c b/extmod/vfs.c
index 3aa1d7744a..586bb4b01d 100644
--- a/extmod/vfs.c
+++ b/extmod/vfs.c
@@ -27,7 +27,6 @@
 #include <stdint.h>
 #include <string.h>
 
-#include "py/runtime0.h"
 #include "py/runtime.h"
 #include "py/objstr.h"
 #include "py/mperrno.h"
diff --git a/extmod/vfs_fat.c b/extmod/vfs_fat.c
index b270541119..22346bdf1d 100644
--- a/extmod/vfs_fat.c
+++ b/extmod/vfs_fat.c
@@ -33,7 +33,6 @@
 #endif
 
 #include <string.h>
-#include "py/nlr.h"
 #include "py/runtime.h"
 #include "py/mperrno.h"
 #include "lib/oofatfs/ff.h"
diff --git a/extmod/vfs_fat_file.c b/extmod/vfs_fat_file.c
index 3894b2cae7..f580184a7c 100644
--- a/extmod/vfs_fat_file.c
+++ b/extmod/vfs_fat_file.c
@@ -31,7 +31,6 @@
 
 #include <stdio.h>
 
-#include "py/nlr.h"
 #include "py/runtime.h"
 #include "py/stream.h"
 #include "py/mperrno.h"
diff --git a/extmod/vfs_fat_misc.c b/extmod/vfs_fat_misc.c
index 7c16db7e5b..9a26b4a2f9 100644
--- a/extmod/vfs_fat_misc.c
+++ b/extmod/vfs_fat_misc.c
@@ -28,7 +28,6 @@
 #if MICROPY_VFS_FAT
 
 #include <string.h>
-#include "py/nlr.h"
 #include "py/runtime.h"
 #include "lib/oofatfs/ff.h"
 #include "extmod/vfs_fat.h"
diff --git a/lib/berkeley-db-1.xx b/lib/berkeley-db-1.xx
index dab957dacd..35aaec4418 160000
--- a/lib/berkeley-db-1.xx
+++ b/lib/berkeley-db-1.xx
@@ -1 +1 @@
-Subproject commit dab957dacddcbf6cbc85d42df62e189e4877bb72
+Subproject commit 35aaec4418ad78628a3b935885dd189d41ce779b
diff --git a/lib/embed/abort_.c b/lib/embed/abort_.c
index a6df8143c3..2fba0de4ea 100644
--- a/lib/embed/abort_.c
+++ b/lib/embed/abort_.c
@@ -3,5 +3,5 @@
 NORETURN void abort_(void);
 
 NORETURN void abort_(void) {
-    nlr_raise(mp_obj_new_exception_msg(&mp_type_RuntimeError, "abort() called"));
+    mp_raise_msg(&mp_type_RuntimeError, "abort() called");
 }
diff --git a/lib/libm/math.c b/lib/libm/math.c
index a2313fcea8..327a149b13 100644
--- a/lib/libm/math.c
+++ b/lib/libm/math.c
@@ -61,7 +61,12 @@ float log2f(float x) { return logf(x) / (float)_M_LN2; }
 static const float _M_LN10 = 2.30258509299404; // 0x40135d8e
 float log10f(float x) { return logf(x) / (float)_M_LN10; }
 
-float tanhf(float x) { return sinhf(x) / coshf(x); }
+float tanhf(float x) {
+    if (isinf(x)) {
+        return copysignf(1, x);
+    }
+    return sinhf(x) / coshf(x);
+}
 
 /*****************************************************************************/
 /*****************************************************************************/
diff --git a/lib/netutils/netutils.c b/lib/netutils/netutils.c
index 15e70397cb..06c3ff9b08 100644
--- a/lib/netutils/netutils.c
+++ b/lib/netutils/netutils.c
@@ -29,8 +29,6 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "py/obj.h"
-#include "py/nlr.h"
 #include "py/runtime.h"
 #include "lib/netutils/netutils.h"
 
diff --git a/lib/stm32lib b/lib/stm32lib
new file mode 160000
index 0000000000..d2bcfda543
--- /dev/null
+++ b/lib/stm32lib
@@ -0,0 +1 @@
+Subproject commit d2bcfda543d3b99361e44112aca929225bdcc07f
diff --git a/lib/utils/pyexec.c b/lib/utils/pyexec.c
index d95084624c..df93614a10 100644
--- a/lib/utils/pyexec.c
+++ b/lib/utils/pyexec.c
@@ -29,7 +29,6 @@
 #include <stdint.h>
 #include <string.h>
 
-#include "py/nlr.h"
 #include "py/compile.h"
 #include "py/runtime.h"
 #include "py/repl.h"
diff --git a/lib/utils/pyexec.h b/lib/utils/pyexec.h
index 0632d90ae3..d3411f06af 100644
--- a/lib/utils/pyexec.h
+++ b/lib/utils/pyexec.h
@@ -55,6 +55,7 @@ int pyexec_frozen_module(const char *name);
 void pyexec_event_repl_init(void);
 int pyexec_event_repl_process_char(int c);
 extern uint8_t pyexec_repl_active;
+mp_obj_t pyb_set_repl_info(mp_obj_t o_value);
 
 MP_DECLARE_CONST_FUN_OBJ_1(pyb_set_repl_info_obj);
 
diff --git a/mpy-cross/Makefile b/mpy-cross/Makefile
index 5399b5ae77..53ce50c7ff 100644
--- a/mpy-cross/Makefile
+++ b/mpy-cross/Makefile
@@ -65,7 +65,7 @@ SRC_C = \
 # Add fmode when compiling with mingw gcc
 COMPILER_TARGET := $(shell $(CC) -dumpmachine)
 ifneq (,$(findstring mingw,$(COMPILER_TARGET)))
-	SRC_C += windows/fmode.c
+	SRC_C += ports/windows/fmode.c
 endif
 
 OBJ = $(PY_O)
diff --git a/mpy-cross/main.c b/mpy-cross/main.c
index ca8d9633fa..d819f74f12 100644
--- a/mpy-cross/main.c
+++ b/mpy-cross/main.c
@@ -29,14 +29,13 @@
 #include <stdlib.h>
 #include <unistd.h>
 
-#include "py/mpstate.h"
 #include "py/compile.h"
 #include "py/persistentcode.h"
 #include "py/runtime.h"
 #include "py/gc.h"
 #include "py/stackctrl.h"
 #ifdef _WIN32
-#include "windows/fmode.h"
+#include "ports/windows/fmode.h"
 #endif
 
 // Command line options, with their defaults
diff --git a/atmel-samd/.gitattributes b/ports/atmel-samd/.gitattributes
similarity index 100%
rename from atmel-samd/.gitattributes
rename to ports/atmel-samd/.gitattributes
diff --git a/atmel-samd/.gitignore b/ports/atmel-samd/.gitignore
similarity index 100%
rename from atmel-samd/.gitignore
rename to ports/atmel-samd/.gitignore
diff --git a/atmel-samd/Makefile b/ports/atmel-samd/Makefile
similarity index 99%
rename from atmel-samd/Makefile
rename to ports/atmel-samd/Makefile
index 485ac9a0b5..f9751415a1 100644
--- a/atmel-samd/Makefile
+++ b/ports/atmel-samd/Makefile
@@ -9,7 +9,7 @@ endif
 # If the build directory is not given, make it reflect the board name.
 BUILD ?= build-$(BOARD)
 
-include ../py/mkenv.mk
+include ../../py/mkenv.mk
 -include mpconfigport.mk
 include boards/$(BOARD)/mpconfigboard.mk
 
@@ -28,7 +28,7 @@ BOSSAC := tools/bossac_osx
 HAL_DIR=hal/$(MCU_SERIES)
 
 INC += -I. \
-       -I.. \
+       -I../.. \
        -I../lib/mp-readline \
        -I../lib/timeutils \
        -Iasf4/$(CHIP_FAMILY) \
diff --git a/atmel-samd/README.rst b/ports/atmel-samd/README.rst
similarity index 100%
rename from atmel-samd/README.rst
rename to ports/atmel-samd/README.rst
diff --git a/atmel-samd/asf4 b/ports/atmel-samd/asf4
similarity index 100%
rename from atmel-samd/asf4
rename to ports/atmel-samd/asf4
diff --git a/atmel-samd/asf4_conf/samd21/hpl_dmac_config.h b/ports/atmel-samd/asf4_conf/samd21/hpl_dmac_config.h
similarity index 100%
rename from atmel-samd/asf4_conf/samd21/hpl_dmac_config.h
rename to ports/atmel-samd/asf4_conf/samd21/hpl_dmac_config.h
diff --git a/atmel-samd/asf4_conf/samd21/hpl_gclk_config.h b/ports/atmel-samd/asf4_conf/samd21/hpl_gclk_config.h
similarity index 100%
rename from atmel-samd/asf4_conf/samd21/hpl_gclk_config.h
rename to ports/atmel-samd/asf4_conf/samd21/hpl_gclk_config.h
diff --git a/atmel-samd/asf4_conf/samd21/hpl_nvmctrl_config.h b/ports/atmel-samd/asf4_conf/samd21/hpl_nvmctrl_config.h
similarity index 100%
rename from atmel-samd/asf4_conf/samd21/hpl_nvmctrl_config.h
rename to ports/atmel-samd/asf4_conf/samd21/hpl_nvmctrl_config.h
diff --git a/atmel-samd/asf4_conf/samd21/hpl_pm_config.h b/ports/atmel-samd/asf4_conf/samd21/hpl_pm_config.h
similarity index 100%
rename from atmel-samd/asf4_conf/samd21/hpl_pm_config.h
rename to ports/atmel-samd/asf4_conf/samd21/hpl_pm_config.h
diff --git a/atmel-samd/asf4_conf/samd21/hpl_rtc_config.h b/ports/atmel-samd/asf4_conf/samd21/hpl_rtc_config.h
similarity index 100%
rename from atmel-samd/asf4_conf/samd21/hpl_rtc_config.h
rename to ports/atmel-samd/asf4_conf/samd21/hpl_rtc_config.h
diff --git a/atmel-samd/asf4_conf/samd21/hpl_sysctrl_config.h b/ports/atmel-samd/asf4_conf/samd21/hpl_sysctrl_config.h
similarity index 100%
rename from atmel-samd/asf4_conf/samd21/hpl_sysctrl_config.h
rename to ports/atmel-samd/asf4_conf/samd21/hpl_sysctrl_config.h
diff --git a/atmel-samd/asf4_conf/samd21/hpl_systick_config.h b/ports/atmel-samd/asf4_conf/samd21/hpl_systick_config.h
similarity index 100%
rename from atmel-samd/asf4_conf/samd21/hpl_systick_config.h
rename to ports/atmel-samd/asf4_conf/samd21/hpl_systick_config.h
diff --git a/atmel-samd/asf4_conf/samd21/hpl_tc_config.h b/ports/atmel-samd/asf4_conf/samd21/hpl_tc_config.h
similarity index 100%
rename from atmel-samd/asf4_conf/samd21/hpl_tc_config.h
rename to ports/atmel-samd/asf4_conf/samd21/hpl_tc_config.h
diff --git a/atmel-samd/asf4_conf/samd21/hpl_usb_config.h b/ports/atmel-samd/asf4_conf/samd21/hpl_usb_config.h
similarity index 100%
rename from atmel-samd/asf4_conf/samd21/hpl_usb_config.h
rename to ports/atmel-samd/asf4_conf/samd21/hpl_usb_config.h
diff --git a/atmel-samd/asf4_conf/samd21/peripheral_clk_config.h b/ports/atmel-samd/asf4_conf/samd21/peripheral_clk_config.h
similarity index 100%
rename from atmel-samd/asf4_conf/samd21/peripheral_clk_config.h
rename to ports/atmel-samd/asf4_conf/samd21/peripheral_clk_config.h
diff --git a/atmel-samd/asf4_conf/samd51/hpl_dmac_config.h b/ports/atmel-samd/asf4_conf/samd51/hpl_dmac_config.h
similarity index 100%
rename from atmel-samd/asf4_conf/samd51/hpl_dmac_config.h
rename to ports/atmel-samd/asf4_conf/samd51/hpl_dmac_config.h
diff --git a/atmel-samd/asf4_conf/samd51/hpl_gclk_config.h b/ports/atmel-samd/asf4_conf/samd51/hpl_gclk_config.h
similarity index 100%
rename from atmel-samd/asf4_conf/samd51/hpl_gclk_config.h
rename to ports/atmel-samd/asf4_conf/samd51/hpl_gclk_config.h
diff --git a/atmel-samd/asf4_conf/samd51/hpl_mclk_config.h b/ports/atmel-samd/asf4_conf/samd51/hpl_mclk_config.h
similarity index 100%
rename from atmel-samd/asf4_conf/samd51/hpl_mclk_config.h
rename to ports/atmel-samd/asf4_conf/samd51/hpl_mclk_config.h
diff --git a/atmel-samd/asf4_conf/samd51/hpl_nvmctrl_config.h b/ports/atmel-samd/asf4_conf/samd51/hpl_nvmctrl_config.h
similarity index 100%
rename from atmel-samd/asf4_conf/samd51/hpl_nvmctrl_config.h
rename to ports/atmel-samd/asf4_conf/samd51/hpl_nvmctrl_config.h
diff --git a/atmel-samd/asf4_conf/samd51/hpl_osc32kctrl_config.h b/ports/atmel-samd/asf4_conf/samd51/hpl_osc32kctrl_config.h
similarity index 100%
rename from atmel-samd/asf4_conf/samd51/hpl_osc32kctrl_config.h
rename to ports/atmel-samd/asf4_conf/samd51/hpl_osc32kctrl_config.h
diff --git a/atmel-samd/asf4_conf/samd51/hpl_oscctrl_config.h b/ports/atmel-samd/asf4_conf/samd51/hpl_oscctrl_config.h
similarity index 100%
rename from atmel-samd/asf4_conf/samd51/hpl_oscctrl_config.h
rename to ports/atmel-samd/asf4_conf/samd51/hpl_oscctrl_config.h
diff --git a/atmel-samd/asf4_conf/samd51/hpl_rtc_config.h b/ports/atmel-samd/asf4_conf/samd51/hpl_rtc_config.h
similarity index 100%
rename from atmel-samd/asf4_conf/samd51/hpl_rtc_config.h
rename to ports/atmel-samd/asf4_conf/samd51/hpl_rtc_config.h
diff --git a/atmel-samd/asf4_conf/samd51/hpl_systick_config.h b/ports/atmel-samd/asf4_conf/samd51/hpl_systick_config.h
similarity index 100%
rename from atmel-samd/asf4_conf/samd51/hpl_systick_config.h
rename to ports/atmel-samd/asf4_conf/samd51/hpl_systick_config.h
diff --git a/atmel-samd/asf4_conf/samd51/hpl_tc_config.h b/ports/atmel-samd/asf4_conf/samd51/hpl_tc_config.h
similarity index 100%
rename from atmel-samd/asf4_conf/samd51/hpl_tc_config.h
rename to ports/atmel-samd/asf4_conf/samd51/hpl_tc_config.h
diff --git a/atmel-samd/asf4_conf/samd51/hpl_trng_config.h b/ports/atmel-samd/asf4_conf/samd51/hpl_trng_config.h
similarity index 100%
rename from atmel-samd/asf4_conf/samd51/hpl_trng_config.h
rename to ports/atmel-samd/asf4_conf/samd51/hpl_trng_config.h
diff --git a/atmel-samd/asf4_conf/samd51/hpl_usb_config.h b/ports/atmel-samd/asf4_conf/samd51/hpl_usb_config.h
similarity index 100%
rename from atmel-samd/asf4_conf/samd51/hpl_usb_config.h
rename to ports/atmel-samd/asf4_conf/samd51/hpl_usb_config.h
diff --git a/atmel-samd/asf4_conf/samd51/peripheral_clk_config.h b/ports/atmel-samd/asf4_conf/samd51/peripheral_clk_config.h
similarity index 100%
rename from atmel-samd/asf4_conf/samd51/peripheral_clk_config.h
rename to ports/atmel-samd/asf4_conf/samd51/peripheral_clk_config.h
diff --git a/atmel-samd/background.c b/ports/atmel-samd/background.c
similarity index 100%
rename from atmel-samd/background.c
rename to ports/atmel-samd/background.c
diff --git a/atmel-samd/background.h b/ports/atmel-samd/background.h
similarity index 100%
rename from atmel-samd/background.h
rename to ports/atmel-samd/background.h
diff --git a/atmel-samd/bindings/samd/__init__.c b/ports/atmel-samd/bindings/samd/__init__.c
similarity index 100%
rename from atmel-samd/bindings/samd/__init__.c
rename to ports/atmel-samd/bindings/samd/__init__.c
diff --git a/atmel-samd/boards/arduino_zero/board.c b/ports/atmel-samd/boards/arduino_zero/board.c
similarity index 100%
rename from atmel-samd/boards/arduino_zero/board.c
rename to ports/atmel-samd/boards/arduino_zero/board.c
diff --git a/atmel-samd/boards/arduino_zero/mpconfigboard.h b/ports/atmel-samd/boards/arduino_zero/mpconfigboard.h
similarity index 100%
rename from atmel-samd/boards/arduino_zero/mpconfigboard.h
rename to ports/atmel-samd/boards/arduino_zero/mpconfigboard.h
diff --git a/atmel-samd/boards/arduino_zero/mpconfigboard.mk b/ports/atmel-samd/boards/arduino_zero/mpconfigboard.mk
similarity index 100%
rename from atmel-samd/boards/arduino_zero/mpconfigboard.mk
rename to ports/atmel-samd/boards/arduino_zero/mpconfigboard.mk
diff --git a/atmel-samd/boards/arduino_zero/pins.c b/ports/atmel-samd/boards/arduino_zero/pins.c
similarity index 100%
rename from atmel-samd/boards/arduino_zero/pins.c
rename to ports/atmel-samd/boards/arduino_zero/pins.c
diff --git a/atmel-samd/boards/board.h b/ports/atmel-samd/boards/board.h
similarity index 100%
rename from atmel-samd/boards/board.h
rename to ports/atmel-samd/boards/board.h
diff --git a/atmel-samd/boards/circuitplayground_express/board.c b/ports/atmel-samd/boards/circuitplayground_express/board.c
similarity index 100%
rename from atmel-samd/boards/circuitplayground_express/board.c
rename to ports/atmel-samd/boards/circuitplayground_express/board.c
diff --git a/atmel-samd/boards/circuitplayground_express/mpconfigboard.h b/ports/atmel-samd/boards/circuitplayground_express/mpconfigboard.h
similarity index 100%
rename from atmel-samd/boards/circuitplayground_express/mpconfigboard.h
rename to ports/atmel-samd/boards/circuitplayground_express/mpconfigboard.h
diff --git a/atmel-samd/boards/circuitplayground_express/mpconfigboard.mk b/ports/atmel-samd/boards/circuitplayground_express/mpconfigboard.mk
similarity index 100%
rename from atmel-samd/boards/circuitplayground_express/mpconfigboard.mk
rename to ports/atmel-samd/boards/circuitplayground_express/mpconfigboard.mk
diff --git a/atmel-samd/boards/circuitplayground_express/pins.c b/ports/atmel-samd/boards/circuitplayground_express/pins.c
similarity index 100%
rename from atmel-samd/boards/circuitplayground_express/pins.c
rename to ports/atmel-samd/boards/circuitplayground_express/pins.c
diff --git a/atmel-samd/boards/feather_m0_adalogger/board.c b/ports/atmel-samd/boards/feather_m0_adalogger/board.c
similarity index 100%
rename from atmel-samd/boards/feather_m0_adalogger/board.c
rename to ports/atmel-samd/boards/feather_m0_adalogger/board.c
diff --git a/atmel-samd/boards/feather_m0_adalogger/mpconfigboard.h b/ports/atmel-samd/boards/feather_m0_adalogger/mpconfigboard.h
similarity index 100%
rename from atmel-samd/boards/feather_m0_adalogger/mpconfigboard.h
rename to ports/atmel-samd/boards/feather_m0_adalogger/mpconfigboard.h
diff --git a/atmel-samd/boards/feather_m0_adalogger/mpconfigboard.mk b/ports/atmel-samd/boards/feather_m0_adalogger/mpconfigboard.mk
similarity index 100%
rename from atmel-samd/boards/feather_m0_adalogger/mpconfigboard.mk
rename to ports/atmel-samd/boards/feather_m0_adalogger/mpconfigboard.mk
diff --git a/atmel-samd/boards/feather_m0_adalogger/pins.c b/ports/atmel-samd/boards/feather_m0_adalogger/pins.c
similarity index 100%
rename from atmel-samd/boards/feather_m0_adalogger/pins.c
rename to ports/atmel-samd/boards/feather_m0_adalogger/pins.c
diff --git a/atmel-samd/boards/feather_m0_basic/board.c b/ports/atmel-samd/boards/feather_m0_basic/board.c
similarity index 100%
rename from atmel-samd/boards/feather_m0_basic/board.c
rename to ports/atmel-samd/boards/feather_m0_basic/board.c
diff --git a/atmel-samd/boards/feather_m0_basic/mpconfigboard.h b/ports/atmel-samd/boards/feather_m0_basic/mpconfigboard.h
similarity index 100%
rename from atmel-samd/boards/feather_m0_basic/mpconfigboard.h
rename to ports/atmel-samd/boards/feather_m0_basic/mpconfigboard.h
diff --git a/atmel-samd/boards/feather_m0_basic/mpconfigboard.mk b/ports/atmel-samd/boards/feather_m0_basic/mpconfigboard.mk
similarity index 100%
rename from atmel-samd/boards/feather_m0_basic/mpconfigboard.mk
rename to ports/atmel-samd/boards/feather_m0_basic/mpconfigboard.mk
diff --git a/atmel-samd/boards/feather_m0_basic/pins.c b/ports/atmel-samd/boards/feather_m0_basic/pins.c
similarity index 100%
rename from atmel-samd/boards/feather_m0_basic/pins.c
rename to ports/atmel-samd/boards/feather_m0_basic/pins.c
diff --git a/atmel-samd/boards/feather_m0_express/board.c b/ports/atmel-samd/boards/feather_m0_express/board.c
similarity index 100%
rename from atmel-samd/boards/feather_m0_express/board.c
rename to ports/atmel-samd/boards/feather_m0_express/board.c
diff --git a/atmel-samd/boards/feather_m0_express/mpconfigboard.h b/ports/atmel-samd/boards/feather_m0_express/mpconfigboard.h
similarity index 100%
rename from atmel-samd/boards/feather_m0_express/mpconfigboard.h
rename to ports/atmel-samd/boards/feather_m0_express/mpconfigboard.h
diff --git a/atmel-samd/boards/feather_m0_express/mpconfigboard.mk b/ports/atmel-samd/boards/feather_m0_express/mpconfigboard.mk
similarity index 100%
rename from atmel-samd/boards/feather_m0_express/mpconfigboard.mk
rename to ports/atmel-samd/boards/feather_m0_express/mpconfigboard.mk
diff --git a/atmel-samd/boards/feather_m0_express/pins.c b/ports/atmel-samd/boards/feather_m0_express/pins.c
similarity index 100%
rename from atmel-samd/boards/feather_m0_express/pins.c
rename to ports/atmel-samd/boards/feather_m0_express/pins.c
diff --git a/atmel-samd/boards/flash_AT25DF081A.h b/ports/atmel-samd/boards/flash_AT25DF081A.h
similarity index 100%
rename from atmel-samd/boards/flash_AT25DF081A.h
rename to ports/atmel-samd/boards/flash_AT25DF081A.h
diff --git a/atmel-samd/boards/flash_GD25Q16C.h b/ports/atmel-samd/boards/flash_GD25Q16C.h
similarity index 100%
rename from atmel-samd/boards/flash_GD25Q16C.h
rename to ports/atmel-samd/boards/flash_GD25Q16C.h
diff --git a/atmel-samd/boards/flash_S25FL216K.h b/ports/atmel-samd/boards/flash_S25FL216K.h
similarity index 100%
rename from atmel-samd/boards/flash_S25FL216K.h
rename to ports/atmel-samd/boards/flash_S25FL216K.h
diff --git a/atmel-samd/boards/flash_W25Q32BV.h b/ports/atmel-samd/boards/flash_W25Q32BV.h
similarity index 100%
rename from atmel-samd/boards/flash_W25Q32BV.h
rename to ports/atmel-samd/boards/flash_W25Q32BV.h
diff --git a/atmel-samd/boards/gemma_m0/board.c b/ports/atmel-samd/boards/gemma_m0/board.c
similarity index 100%
rename from atmel-samd/boards/gemma_m0/board.c
rename to ports/atmel-samd/boards/gemma_m0/board.c
diff --git a/atmel-samd/boards/gemma_m0/mpconfigboard.h b/ports/atmel-samd/boards/gemma_m0/mpconfigboard.h
similarity index 100%
rename from atmel-samd/boards/gemma_m0/mpconfigboard.h
rename to ports/atmel-samd/boards/gemma_m0/mpconfigboard.h
diff --git a/atmel-samd/boards/gemma_m0/mpconfigboard.mk b/ports/atmel-samd/boards/gemma_m0/mpconfigboard.mk
similarity index 100%
rename from atmel-samd/boards/gemma_m0/mpconfigboard.mk
rename to ports/atmel-samd/boards/gemma_m0/mpconfigboard.mk
diff --git a/atmel-samd/boards/gemma_m0/pins.c b/ports/atmel-samd/boards/gemma_m0/pins.c
similarity index 100%
rename from atmel-samd/boards/gemma_m0/pins.c
rename to ports/atmel-samd/boards/gemma_m0/pins.c
diff --git a/atmel-samd/boards/metro_m0_express/board.c b/ports/atmel-samd/boards/metro_m0_express/board.c
similarity index 100%
rename from atmel-samd/boards/metro_m0_express/board.c
rename to ports/atmel-samd/boards/metro_m0_express/board.c
diff --git a/atmel-samd/boards/metro_m0_express/mpconfigboard.h b/ports/atmel-samd/boards/metro_m0_express/mpconfigboard.h
similarity index 100%
rename from atmel-samd/boards/metro_m0_express/mpconfigboard.h
rename to ports/atmel-samd/boards/metro_m0_express/mpconfigboard.h
diff --git a/atmel-samd/boards/metro_m0_express/mpconfigboard.mk b/ports/atmel-samd/boards/metro_m0_express/mpconfigboard.mk
similarity index 100%
rename from atmel-samd/boards/metro_m0_express/mpconfigboard.mk
rename to ports/atmel-samd/boards/metro_m0_express/mpconfigboard.mk
diff --git a/atmel-samd/boards/metro_m0_express/pins.c b/ports/atmel-samd/boards/metro_m0_express/pins.c
similarity index 100%
rename from atmel-samd/boards/metro_m0_express/pins.c
rename to ports/atmel-samd/boards/metro_m0_express/pins.c
diff --git a/atmel-samd/boards/metro_m4_express/board.c b/ports/atmel-samd/boards/metro_m4_express/board.c
similarity index 100%
rename from atmel-samd/boards/metro_m4_express/board.c
rename to ports/atmel-samd/boards/metro_m4_express/board.c
diff --git a/atmel-samd/boards/metro_m4_express/mpconfigboard.h b/ports/atmel-samd/boards/metro_m4_express/mpconfigboard.h
similarity index 100%
rename from atmel-samd/boards/metro_m4_express/mpconfigboard.h
rename to ports/atmel-samd/boards/metro_m4_express/mpconfigboard.h
diff --git a/atmel-samd/boards/metro_m4_express/mpconfigboard.mk b/ports/atmel-samd/boards/metro_m4_express/mpconfigboard.mk
similarity index 100%
rename from atmel-samd/boards/metro_m4_express/mpconfigboard.mk
rename to ports/atmel-samd/boards/metro_m4_express/mpconfigboard.mk
diff --git a/atmel-samd/boards/metro_m4_express/pins.c b/ports/atmel-samd/boards/metro_m4_express/pins.c
similarity index 100%
rename from atmel-samd/boards/metro_m4_express/pins.c
rename to ports/atmel-samd/boards/metro_m4_express/pins.c
diff --git a/atmel-samd/boards/samd21x18-bootloader-crystalless.ld b/ports/atmel-samd/boards/samd21x18-bootloader-crystalless.ld
similarity index 100%
rename from atmel-samd/boards/samd21x18-bootloader-crystalless.ld
rename to ports/atmel-samd/boards/samd21x18-bootloader-crystalless.ld
diff --git a/atmel-samd/boards/samd21x18-bootloader-external-flash-crystalless.ld b/ports/atmel-samd/boards/samd21x18-bootloader-external-flash-crystalless.ld
similarity index 100%
rename from atmel-samd/boards/samd21x18-bootloader-external-flash-crystalless.ld
rename to ports/atmel-samd/boards/samd21x18-bootloader-external-flash-crystalless.ld
diff --git a/atmel-samd/boards/samd21x18-bootloader-external-flash.ld b/ports/atmel-samd/boards/samd21x18-bootloader-external-flash.ld
similarity index 100%
rename from atmel-samd/boards/samd21x18-bootloader-external-flash.ld
rename to ports/atmel-samd/boards/samd21x18-bootloader-external-flash.ld
diff --git a/atmel-samd/boards/samd21x18-bootloader.ld b/ports/atmel-samd/boards/samd21x18-bootloader.ld
similarity index 100%
rename from atmel-samd/boards/samd21x18-bootloader.ld
rename to ports/atmel-samd/boards/samd21x18-bootloader.ld
diff --git a/atmel-samd/boards/samd21x18-external-flash.ld b/ports/atmel-samd/boards/samd21x18-external-flash.ld
similarity index 100%
rename from atmel-samd/boards/samd21x18-external-flash.ld
rename to ports/atmel-samd/boards/samd21x18-external-flash.ld
diff --git a/atmel-samd/boards/samd21x18.ld b/ports/atmel-samd/boards/samd21x18.ld
similarity index 100%
rename from atmel-samd/boards/samd21x18.ld
rename to ports/atmel-samd/boards/samd21x18.ld
diff --git a/atmel-samd/boards/samd51x18-bootloader-external-flash.ld b/ports/atmel-samd/boards/samd51x18-bootloader-external-flash.ld
similarity index 100%
rename from atmel-samd/boards/samd51x18-bootloader-external-flash.ld
rename to ports/atmel-samd/boards/samd51x18-bootloader-external-flash.ld
diff --git a/atmel-samd/boards/samd51x19-bootloader-external-flash.ld b/ports/atmel-samd/boards/samd51x19-bootloader-external-flash.ld
similarity index 100%
rename from atmel-samd/boards/samd51x19-bootloader-external-flash.ld
rename to ports/atmel-samd/boards/samd51x19-bootloader-external-flash.ld
diff --git a/atmel-samd/boards/samd51x19-bootloader.ld b/ports/atmel-samd/boards/samd51x19-bootloader.ld
similarity index 100%
rename from atmel-samd/boards/samd51x19-bootloader.ld
rename to ports/atmel-samd/boards/samd51x19-bootloader.ld
diff --git a/atmel-samd/boards/samd51x20-bootloader-external-flash.ld b/ports/atmel-samd/boards/samd51x20-bootloader-external-flash.ld
similarity index 100%
rename from atmel-samd/boards/samd51x20-bootloader-external-flash.ld
rename to ports/atmel-samd/boards/samd51x20-bootloader-external-flash.ld
diff --git a/atmel-samd/boards/samd51x20-bootloader.ld b/ports/atmel-samd/boards/samd51x20-bootloader.ld
similarity index 100%
rename from atmel-samd/boards/samd51x20-bootloader.ld
rename to ports/atmel-samd/boards/samd51x20-bootloader.ld
diff --git a/atmel-samd/boards/samd51x20-external-flash.ld b/ports/atmel-samd/boards/samd51x20-external-flash.ld
similarity index 100%
rename from atmel-samd/boards/samd51x20-external-flash.ld
rename to ports/atmel-samd/boards/samd51x20-external-flash.ld
diff --git a/atmel-samd/boards/samd51x20.ld b/ports/atmel-samd/boards/samd51x20.ld
similarity index 100%
rename from atmel-samd/boards/samd51x20.ld
rename to ports/atmel-samd/boards/samd51x20.ld
diff --git a/atmel-samd/boards/trinket_m0/board.c b/ports/atmel-samd/boards/trinket_m0/board.c
similarity index 100%
rename from atmel-samd/boards/trinket_m0/board.c
rename to ports/atmel-samd/boards/trinket_m0/board.c
diff --git a/atmel-samd/boards/trinket_m0/mpconfigboard.h b/ports/atmel-samd/boards/trinket_m0/mpconfigboard.h
similarity index 100%
rename from atmel-samd/boards/trinket_m0/mpconfigboard.h
rename to ports/atmel-samd/boards/trinket_m0/mpconfigboard.h
diff --git a/atmel-samd/boards/trinket_m0/mpconfigboard.mk b/ports/atmel-samd/boards/trinket_m0/mpconfigboard.mk
similarity index 100%
rename from atmel-samd/boards/trinket_m0/mpconfigboard.mk
rename to ports/atmel-samd/boards/trinket_m0/mpconfigboard.mk
diff --git a/atmel-samd/boards/trinket_m0/pins.c b/ports/atmel-samd/boards/trinket_m0/pins.c
similarity index 100%
rename from atmel-samd/boards/trinket_m0/pins.c
rename to ports/atmel-samd/boards/trinket_m0/pins.c
diff --git a/atmel-samd/boards/trinket_m0_haxpress/board.c b/ports/atmel-samd/boards/trinket_m0_haxpress/board.c
similarity index 100%
rename from atmel-samd/boards/trinket_m0_haxpress/board.c
rename to ports/atmel-samd/boards/trinket_m0_haxpress/board.c
diff --git a/atmel-samd/boards/trinket_m0_haxpress/conf_access.h b/ports/atmel-samd/boards/trinket_m0_haxpress/conf_access.h
similarity index 100%
rename from atmel-samd/boards/trinket_m0_haxpress/conf_access.h
rename to ports/atmel-samd/boards/trinket_m0_haxpress/conf_access.h
diff --git a/atmel-samd/boards/trinket_m0_haxpress/conf_board.h b/ports/atmel-samd/boards/trinket_m0_haxpress/conf_board.h
similarity index 100%
rename from atmel-samd/boards/trinket_m0_haxpress/conf_board.h
rename to ports/atmel-samd/boards/trinket_m0_haxpress/conf_board.h
diff --git a/atmel-samd/boards/trinket_m0_haxpress/conf_clocks.h b/ports/atmel-samd/boards/trinket_m0_haxpress/conf_clocks.h
similarity index 100%
rename from atmel-samd/boards/trinket_m0_haxpress/conf_clocks.h
rename to ports/atmel-samd/boards/trinket_m0_haxpress/conf_clocks.h
diff --git a/atmel-samd/boards/trinket_m0_haxpress/conf_usb.h b/ports/atmel-samd/boards/trinket_m0_haxpress/conf_usb.h
similarity index 100%
rename from atmel-samd/boards/trinket_m0_haxpress/conf_usb.h
rename to ports/atmel-samd/boards/trinket_m0_haxpress/conf_usb.h
diff --git a/atmel-samd/boards/trinket_m0_haxpress/mpconfigboard.h b/ports/atmel-samd/boards/trinket_m0_haxpress/mpconfigboard.h
similarity index 100%
rename from atmel-samd/boards/trinket_m0_haxpress/mpconfigboard.h
rename to ports/atmel-samd/boards/trinket_m0_haxpress/mpconfigboard.h
diff --git a/atmel-samd/boards/trinket_m0_haxpress/mpconfigboard.mk b/ports/atmel-samd/boards/trinket_m0_haxpress/mpconfigboard.mk
similarity index 100%
rename from atmel-samd/boards/trinket_m0_haxpress/mpconfigboard.mk
rename to ports/atmel-samd/boards/trinket_m0_haxpress/mpconfigboard.mk
diff --git a/atmel-samd/boards/trinket_m0_haxpress/pins.c b/ports/atmel-samd/boards/trinket_m0_haxpress/pins.c
similarity index 100%
rename from atmel-samd/boards/trinket_m0_haxpress/pins.c
rename to ports/atmel-samd/boards/trinket_m0_haxpress/pins.c
diff --git a/atmel-samd/common-hal/analogio/AnalogIn.c b/ports/atmel-samd/common-hal/analogio/AnalogIn.c
similarity index 100%
rename from atmel-samd/common-hal/analogio/AnalogIn.c
rename to ports/atmel-samd/common-hal/analogio/AnalogIn.c
diff --git a/atmel-samd/common-hal/analogio/AnalogIn.h b/ports/atmel-samd/common-hal/analogio/AnalogIn.h
similarity index 100%
rename from atmel-samd/common-hal/analogio/AnalogIn.h
rename to ports/atmel-samd/common-hal/analogio/AnalogIn.h
diff --git a/atmel-samd/common-hal/analogio/AnalogOut.c b/ports/atmel-samd/common-hal/analogio/AnalogOut.c
similarity index 100%
rename from atmel-samd/common-hal/analogio/AnalogOut.c
rename to ports/atmel-samd/common-hal/analogio/AnalogOut.c
diff --git a/atmel-samd/common-hal/analogio/AnalogOut.h b/ports/atmel-samd/common-hal/analogio/AnalogOut.h
similarity index 100%
rename from atmel-samd/common-hal/analogio/AnalogOut.h
rename to ports/atmel-samd/common-hal/analogio/AnalogOut.h
diff --git a/atmel-samd/common-hal/analogio/__init__.c b/ports/atmel-samd/common-hal/analogio/__init__.c
similarity index 100%
rename from atmel-samd/common-hal/analogio/__init__.c
rename to ports/atmel-samd/common-hal/analogio/__init__.c
diff --git a/atmel-samd/common-hal/audiobusio/PDMIn.c b/ports/atmel-samd/common-hal/audiobusio/PDMIn.c
similarity index 100%
rename from atmel-samd/common-hal/audiobusio/PDMIn.c
rename to ports/atmel-samd/common-hal/audiobusio/PDMIn.c
diff --git a/atmel-samd/common-hal/audiobusio/PDMIn.h b/ports/atmel-samd/common-hal/audiobusio/PDMIn.h
similarity index 100%
rename from atmel-samd/common-hal/audiobusio/PDMIn.h
rename to ports/atmel-samd/common-hal/audiobusio/PDMIn.h
diff --git a/atmel-samd/common-hal/audiobusio/__init__.c b/ports/atmel-samd/common-hal/audiobusio/__init__.c
similarity index 100%
rename from atmel-samd/common-hal/audiobusio/__init__.c
rename to ports/atmel-samd/common-hal/audiobusio/__init__.c
diff --git a/atmel-samd/common-hal/audioio/AudioOut.c b/ports/atmel-samd/common-hal/audioio/AudioOut.c
similarity index 100%
rename from atmel-samd/common-hal/audioio/AudioOut.c
rename to ports/atmel-samd/common-hal/audioio/AudioOut.c
diff --git a/atmel-samd/common-hal/audioio/AudioOut.h b/ports/atmel-samd/common-hal/audioio/AudioOut.h
similarity index 100%
rename from atmel-samd/common-hal/audioio/AudioOut.h
rename to ports/atmel-samd/common-hal/audioio/AudioOut.h
diff --git a/atmel-samd/common-hal/audioio/__init__.c b/ports/atmel-samd/common-hal/audioio/__init__.c
similarity index 100%
rename from atmel-samd/common-hal/audioio/__init__.c
rename to ports/atmel-samd/common-hal/audioio/__init__.c
diff --git a/atmel-samd/common-hal/board/__init__.c b/ports/atmel-samd/common-hal/board/__init__.c
similarity index 100%
rename from atmel-samd/common-hal/board/__init__.c
rename to ports/atmel-samd/common-hal/board/__init__.c
diff --git a/atmel-samd/common-hal/busio/I2C.c b/ports/atmel-samd/common-hal/busio/I2C.c
similarity index 100%
rename from atmel-samd/common-hal/busio/I2C.c
rename to ports/atmel-samd/common-hal/busio/I2C.c
diff --git a/atmel-samd/common-hal/busio/I2C.h b/ports/atmel-samd/common-hal/busio/I2C.h
similarity index 100%
rename from atmel-samd/common-hal/busio/I2C.h
rename to ports/atmel-samd/common-hal/busio/I2C.h
diff --git a/atmel-samd/common-hal/busio/OneWire.h b/ports/atmel-samd/common-hal/busio/OneWire.h
similarity index 100%
rename from atmel-samd/common-hal/busio/OneWire.h
rename to ports/atmel-samd/common-hal/busio/OneWire.h
diff --git a/atmel-samd/common-hal/busio/SPI.c b/ports/atmel-samd/common-hal/busio/SPI.c
similarity index 100%
rename from atmel-samd/common-hal/busio/SPI.c
rename to ports/atmel-samd/common-hal/busio/SPI.c
diff --git a/atmel-samd/common-hal/busio/SPI.h b/ports/atmel-samd/common-hal/busio/SPI.h
similarity index 100%
rename from atmel-samd/common-hal/busio/SPI.h
rename to ports/atmel-samd/common-hal/busio/SPI.h
diff --git a/atmel-samd/common-hal/busio/UART.c b/ports/atmel-samd/common-hal/busio/UART.c
similarity index 100%
rename from atmel-samd/common-hal/busio/UART.c
rename to ports/atmel-samd/common-hal/busio/UART.c
diff --git a/atmel-samd/common-hal/busio/UART.h b/ports/atmel-samd/common-hal/busio/UART.h
similarity index 100%
rename from atmel-samd/common-hal/busio/UART.h
rename to ports/atmel-samd/common-hal/busio/UART.h
diff --git a/atmel-samd/common-hal/busio/__init__.c b/ports/atmel-samd/common-hal/busio/__init__.c
similarity index 100%
rename from atmel-samd/common-hal/busio/__init__.c
rename to ports/atmel-samd/common-hal/busio/__init__.c
diff --git a/atmel-samd/common-hal/digitalio/DigitalInOut.c b/ports/atmel-samd/common-hal/digitalio/DigitalInOut.c
similarity index 100%
rename from atmel-samd/common-hal/digitalio/DigitalInOut.c
rename to ports/atmel-samd/common-hal/digitalio/DigitalInOut.c
diff --git a/atmel-samd/common-hal/digitalio/DigitalInOut.h b/ports/atmel-samd/common-hal/digitalio/DigitalInOut.h
similarity index 100%
rename from atmel-samd/common-hal/digitalio/DigitalInOut.h
rename to ports/atmel-samd/common-hal/digitalio/DigitalInOut.h
diff --git a/atmel-samd/common-hal/digitalio/__init__.c b/ports/atmel-samd/common-hal/digitalio/__init__.c
similarity index 100%
rename from atmel-samd/common-hal/digitalio/__init__.c
rename to ports/atmel-samd/common-hal/digitalio/__init__.c
diff --git a/atmel-samd/common-hal/microcontroller/Pin.c b/ports/atmel-samd/common-hal/microcontroller/Pin.c
similarity index 100%
rename from atmel-samd/common-hal/microcontroller/Pin.c
rename to ports/atmel-samd/common-hal/microcontroller/Pin.c
diff --git a/atmel-samd/common-hal/microcontroller/Pin.h b/ports/atmel-samd/common-hal/microcontroller/Pin.h
similarity index 100%
rename from atmel-samd/common-hal/microcontroller/Pin.h
rename to ports/atmel-samd/common-hal/microcontroller/Pin.h
diff --git a/atmel-samd/common-hal/microcontroller/Processor.c b/ports/atmel-samd/common-hal/microcontroller/Processor.c
similarity index 100%
rename from atmel-samd/common-hal/microcontroller/Processor.c
rename to ports/atmel-samd/common-hal/microcontroller/Processor.c
diff --git a/atmel-samd/common-hal/microcontroller/Processor.h b/ports/atmel-samd/common-hal/microcontroller/Processor.h
similarity index 100%
rename from atmel-samd/common-hal/microcontroller/Processor.h
rename to ports/atmel-samd/common-hal/microcontroller/Processor.h
diff --git a/atmel-samd/common-hal/microcontroller/__init__.c b/ports/atmel-samd/common-hal/microcontroller/__init__.c
similarity index 100%
rename from atmel-samd/common-hal/microcontroller/__init__.c
rename to ports/atmel-samd/common-hal/microcontroller/__init__.c
diff --git a/atmel-samd/common-hal/neopixel_write/__init__.c b/ports/atmel-samd/common-hal/neopixel_write/__init__.c
similarity index 100%
rename from atmel-samd/common-hal/neopixel_write/__init__.c
rename to ports/atmel-samd/common-hal/neopixel_write/__init__.c
diff --git a/atmel-samd/common-hal/nvm/ByteArray.c b/ports/atmel-samd/common-hal/nvm/ByteArray.c
similarity index 100%
rename from atmel-samd/common-hal/nvm/ByteArray.c
rename to ports/atmel-samd/common-hal/nvm/ByteArray.c
diff --git a/atmel-samd/common-hal/nvm/ByteArray.h b/ports/atmel-samd/common-hal/nvm/ByteArray.h
similarity index 100%
rename from atmel-samd/common-hal/nvm/ByteArray.h
rename to ports/atmel-samd/common-hal/nvm/ByteArray.h
diff --git a/atmel-samd/common-hal/nvm/__init__.c b/ports/atmel-samd/common-hal/nvm/__init__.c
similarity index 100%
rename from atmel-samd/common-hal/nvm/__init__.c
rename to ports/atmel-samd/common-hal/nvm/__init__.c
diff --git a/atmel-samd/common-hal/os/__init__.c b/ports/atmel-samd/common-hal/os/__init__.c
similarity index 100%
rename from atmel-samd/common-hal/os/__init__.c
rename to ports/atmel-samd/common-hal/os/__init__.c
diff --git a/atmel-samd/common-hal/pulseio/PWMOut.c b/ports/atmel-samd/common-hal/pulseio/PWMOut.c
similarity index 100%
rename from atmel-samd/common-hal/pulseio/PWMOut.c
rename to ports/atmel-samd/common-hal/pulseio/PWMOut.c
diff --git a/atmel-samd/common-hal/pulseio/PWMOut.h b/ports/atmel-samd/common-hal/pulseio/PWMOut.h
similarity index 100%
rename from atmel-samd/common-hal/pulseio/PWMOut.h
rename to ports/atmel-samd/common-hal/pulseio/PWMOut.h
diff --git a/atmel-samd/common-hal/pulseio/PulseIn.c b/ports/atmel-samd/common-hal/pulseio/PulseIn.c
similarity index 100%
rename from atmel-samd/common-hal/pulseio/PulseIn.c
rename to ports/atmel-samd/common-hal/pulseio/PulseIn.c
diff --git a/atmel-samd/common-hal/pulseio/PulseIn.h b/ports/atmel-samd/common-hal/pulseio/PulseIn.h
similarity index 100%
rename from atmel-samd/common-hal/pulseio/PulseIn.h
rename to ports/atmel-samd/common-hal/pulseio/PulseIn.h
diff --git a/atmel-samd/common-hal/pulseio/PulseOut.c b/ports/atmel-samd/common-hal/pulseio/PulseOut.c
similarity index 100%
rename from atmel-samd/common-hal/pulseio/PulseOut.c
rename to ports/atmel-samd/common-hal/pulseio/PulseOut.c
diff --git a/atmel-samd/common-hal/pulseio/PulseOut.h b/ports/atmel-samd/common-hal/pulseio/PulseOut.h
similarity index 100%
rename from atmel-samd/common-hal/pulseio/PulseOut.h
rename to ports/atmel-samd/common-hal/pulseio/PulseOut.h
diff --git a/atmel-samd/common-hal/pulseio/__init__.c b/ports/atmel-samd/common-hal/pulseio/__init__.c
similarity index 100%
rename from atmel-samd/common-hal/pulseio/__init__.c
rename to ports/atmel-samd/common-hal/pulseio/__init__.c
diff --git a/atmel-samd/common-hal/storage/__init__.c b/ports/atmel-samd/common-hal/storage/__init__.c
similarity index 100%
rename from atmel-samd/common-hal/storage/__init__.c
rename to ports/atmel-samd/common-hal/storage/__init__.c
diff --git a/atmel-samd/common-hal/time/__init__.c b/ports/atmel-samd/common-hal/time/__init__.c
similarity index 100%
rename from atmel-samd/common-hal/time/__init__.c
rename to ports/atmel-samd/common-hal/time/__init__.c
diff --git a/atmel-samd/common-hal/touchio/TouchIn.c b/ports/atmel-samd/common-hal/touchio/TouchIn.c
similarity index 100%
rename from atmel-samd/common-hal/touchio/TouchIn.c
rename to ports/atmel-samd/common-hal/touchio/TouchIn.c
diff --git a/atmel-samd/common-hal/touchio/TouchIn.h b/ports/atmel-samd/common-hal/touchio/TouchIn.h
similarity index 100%
rename from atmel-samd/common-hal/touchio/TouchIn.h
rename to ports/atmel-samd/common-hal/touchio/TouchIn.h
diff --git a/atmel-samd/common-hal/touchio/__init__.c b/ports/atmel-samd/common-hal/touchio/__init__.c
similarity index 100%
rename from atmel-samd/common-hal/touchio/__init__.c
rename to ports/atmel-samd/common-hal/touchio/__init__.c
diff --git a/atmel-samd/common-hal/usb_hid/Device.c b/ports/atmel-samd/common-hal/usb_hid/Device.c
similarity index 100%
rename from atmel-samd/common-hal/usb_hid/Device.c
rename to ports/atmel-samd/common-hal/usb_hid/Device.c
diff --git a/atmel-samd/common-hal/usb_hid/Device.h b/ports/atmel-samd/common-hal/usb_hid/Device.h
similarity index 100%
rename from atmel-samd/common-hal/usb_hid/Device.h
rename to ports/atmel-samd/common-hal/usb_hid/Device.h
diff --git a/atmel-samd/common-hal/usb_hid/__init__.c b/ports/atmel-samd/common-hal/usb_hid/__init__.c
similarity index 100%
rename from atmel-samd/common-hal/usb_hid/__init__.c
rename to ports/atmel-samd/common-hal/usb_hid/__init__.c
diff --git a/atmel-samd/common-hal/usb_hid/__init__.h b/ports/atmel-samd/common-hal/usb_hid/__init__.h
similarity index 100%
rename from atmel-samd/common-hal/usb_hid/__init__.h
rename to ports/atmel-samd/common-hal/usb_hid/__init__.h
diff --git a/atmel-samd/common-hal/usb_hid/types.h b/ports/atmel-samd/common-hal/usb_hid/types.h
similarity index 100%
rename from atmel-samd/common-hal/usb_hid/types.h
rename to ports/atmel-samd/common-hal/usb_hid/types.h
diff --git a/atmel-samd/fatfs_port.c b/ports/atmel-samd/fatfs_port.c
similarity index 100%
rename from atmel-samd/fatfs_port.c
rename to ports/atmel-samd/fatfs_port.c
diff --git a/atmel-samd/flash_api.c b/ports/atmel-samd/flash_api.c
similarity index 100%
rename from atmel-samd/flash_api.c
rename to ports/atmel-samd/flash_api.c
diff --git a/atmel-samd/flash_api.h b/ports/atmel-samd/flash_api.h
similarity index 100%
rename from atmel-samd/flash_api.h
rename to ports/atmel-samd/flash_api.h
diff --git a/ports/atmel-samd/freetouch/Adafruit_FreeTouch.cpp b/ports/atmel-samd/freetouch/Adafruit_FreeTouch.cpp
new file mode 100644
index 0000000000..45cac38674
--- /dev/null
+++ b/ports/atmel-samd/freetouch/Adafruit_FreeTouch.cpp
@@ -0,0 +1,280 @@
+/*
+ * FreeTouch, a QTouch-compatible library - tested on ATSAMD21 only!
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Limor 'ladyada' Fried for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "Adafruit_FreeTouch.h"
+
+#include "adafruit_ptc.h"
+
+Adafruit_FreeTouch::Adafruit_FreeTouch(int p, oversample_t f, series_resistor_t r, freq_mode_t fh) {
+    adafruit_ptc_get_config_default(&config);
+    pin = p;
+    uint8_t port_offset = 0;
+    if (g_APinDescription[pin].ulPort == PORTB) {
+        port_offset += 32;
+    }
+    config.pin = port_offset + g_APinDescription[pin].ulPin;
+    config.yline = getYLine();  // determine the Y0-15 #
+    config.oversample = f;
+    config.seriesres = r;
+    config.freqhop = fh;
+}
+
+bool Adafruit_FreeTouch::begin(void) {
+    if (config.yline == -1) {  // not all pins have Y line
+        return false;
+    }
+
+    /* Setup and enable generic clock source for PTC module.
+       struct system_gclk_chan_config gclk_chan_conf;
+       system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+    */
+    
+    uint8_t channel = PTC_GCLK_ID;
+    uint8_t source_generator = 1;
+    
+    // original line: system_gclk_chan_set_config(PTC_GCLK_ID, &gclk_chan_conf);
+    uint32_t new_clkctrl_config = (channel << GCLK_CLKCTRL_ID_Pos);  // from gclk.c
+    
+    // original line: gclk_chan_conf.source_generator = GCLK_GENERATOR_1;
+    /* Select the desired generic clock generator */
+    new_clkctrl_config |= source_generator << GCLK_CLKCTRL_GEN_Pos;  // from gclk.c
+    
+    /* Disable generic clock channel */
+    // original line: system_gclk_chan_disable(channel);
+    noInterrupts();
+    
+    /* Select the requested generator channel */
+    *((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+    
+    /* Sanity check WRTLOCK */
+    //Assert(!GCLK->CLKCTRL.bit.WRTLOCK);
+    
+    /* Switch to known-working source so that the channel can be disabled */
+    uint32_t prev_gen_id = GCLK->CLKCTRL.bit.GEN;
+    GCLK->CLKCTRL.bit.GEN = 0;
+    
+    /* Disable the generic clock */
+    GCLK->CLKCTRL.reg &= ~GCLK_CLKCTRL_CLKEN;
+    while (GCLK->CLKCTRL.reg & GCLK_CLKCTRL_CLKEN) {
+      /* Wait for clock to become disabled */
+    }
+    
+    /* Restore previous configured clock generator */
+    GCLK->CLKCTRL.bit.GEN = prev_gen_id;
+    
+    //system_interrupt_leave_critical_section();  
+    interrupts();
+    
+    /* Write the new configuration */
+    GCLK->CLKCTRL.reg = new_clkctrl_config;
+    
+    // original line: system_gclk_chan_enable(PTC_GCLK_ID);
+    *((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+    GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_CLKEN;	/* Enable the generic clock */
+    
+    
+    // original line: system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_PTC);
+    PM->APBCMASK.reg |= PM_APBCMASK_PTC;
+    
+    adafruit_ptc_init(PTC, &config);
+
+    return true;
+}
+
+uint16_t Adafruit_FreeTouch::measure(void) {
+  uint16_t m;
+
+  m = measureRaw();
+  if (m == -1) return -1;
+
+  // normalize the signal
+  switch (config.oversample) {
+    case OVERSAMPLE_1:   return m;
+    case OVERSAMPLE_2:   return m/2;
+    case OVERSAMPLE_4:   return m/4;
+    case OVERSAMPLE_8:   return m/8;
+    case OVERSAMPLE_16:  return m/16;
+    case OVERSAMPLE_32:  return m/32;
+    case OVERSAMPLE_64:  return m/64;
+  }
+
+  return -1; // shouldn't reach here but fail if we do!
+}
+
+uint16_t Adafruit_FreeTouch::measureRaw(void) {
+    adafruit_ptc_start_conversion(PTC, &config);
+
+    while (!adafruit_ptc_is_conversion_finished(PTC)) {
+        yield();
+    }
+
+    return adafruit_ptc_get_conversion_result(PTC);
+}
+
+/*********************************** low level config **/
+
+int Adafruit_FreeTouch::getYLine(void) {
+  int p = g_APinDescription[pin].ulPin;
+  if (g_APinDescription[pin].ulPort == PORTA) {
+    if ((p >= 2) && (p <= 7)) {
+      return (p - 2);
+    }
+  }
+  if (g_APinDescription[pin].ulPort == PORTB) {
+    if ((p >= 0) && (p <= 9)) {
+      return (p + 6);
+    }
+  }
+
+  // not valid
+  return -1;
+}
+
+void Adafruit_FreeTouch::setCompCap(uint16_t cc) {
+    config.compcap = cc & 0x3FFF;
+}
+
+void Adafruit_FreeTouch::setIntCap(uint8_t ic) {
+    config.intcap = ic & 0x3F;
+}
+
+void Adafruit_FreeTouch::setOversampling(oversample_t lvl) {
+    config.oversample = lvl; // back it up for later
+}
+
+void Adafruit_FreeTouch::setSeriesResistor(series_resistor_t res) {
+    config.seriesres = res;
+}
+
+void Adafruit_FreeTouch::setFreqHopping(freq_mode_t fh, freq_hop_t hs) {
+    config.freqhop = fh;
+    config.hops = hs;
+}
+
+/**************************** DEBUGGING ASSIST *************************/
+void Adafruit_FreeTouch::snapshotRegsAndPrint(uint32_t base, uint8_t numregs) {
+  volatile uint32_t addr = base;
+  uint8_t datas[255];
+
+  digitalWrite(LED_BUILTIN, HIGH);
+  for (uint8_t i=0; i<numregs; i++) {
+    datas[i] = *(uint8_t *)(addr+i);
+  }
+  digitalWrite(LED_BUILTIN, LOW);
+  printPTCregs(base, datas, numregs);
+
+  for (uint8_t i=0; i<numregs; i++) {
+  //  Serial.print("$"); Serial.print(addr+i, HEX); Serial.print("\t0x");
+  //  printHex(datas[i]); Serial.println();
+  }
+
+}
+
+// Print a hex with leading zero
+void Adafruit_FreeTouch::printHex(uint8_t h, boolean newline) {
+  if (h < 0x10) Serial.print("0");
+  Serial.print(h, HEX);
+  if (newline)  Serial.println();
+}
+
+void Adafruit_FreeTouch::printPTCregs(uint32_t base, uint8_t *regs, uint8_t num) {
+  Serial.println("--------------------------------------------------------");
+  for (uint8_t i=0; i<num; i++) {
+      switch (i + base) {
+        case 0x41004430:  Serial.print("0x"); Serial.print(i+base, HEX);
+          Serial.print(" PMUX0:\t\t0x"); printHex(regs[i], true); break;
+        case 0x41004431:  Serial.print("0x"); Serial.print(i+base, HEX);
+          Serial.print(" PMUX1:\t\t0x"); printHex(regs[i], true); break;
+        case 0x41004432:  Serial.print("0x"); Serial.print(i+base, HEX);
+          Serial.print(" PMUX2:\t\t0x"); printHex(regs[i], true); break;
+        case 0x41004433:  Serial.print("0x"); Serial.print(i+base, HEX);
+          Serial.print(" PMUX3:\t\t0x"); printHex(regs[i], true); break;
+
+        case 0x41004440:  Serial.print("0x"); Serial.print(i+base, HEX);
+          Serial.print(" PCFG0:\t\t0x"); printHex(regs[i], true); break;
+        case 0x41004441:  Serial.print("0x"); Serial.print(i+base, HEX);
+          Serial.print(" PCFG1:\t\t0x"); printHex(regs[i], true); break;
+        case 0x41004442:  Serial.print("0x"); Serial.print(i+base, HEX);
+          Serial.print(" PCFG2:\t\t0x"); printHex(regs[i], true); break;
+        case 0x41004443:  Serial.print("0x"); Serial.print(i+base, HEX);
+          Serial.print(" PCFG3:\t\t0x"); printHex(regs[i], true); break;
+        case 0x41004444:  Serial.print("0x"); Serial.print(i+base, HEX);
+          Serial.print(" PCFG4:\t\t0x"); printHex(regs[i], true); break;
+
+
+        case 0x42004C00: Serial.print("0x"); Serial.print(i+base, HEX);
+          Serial.print(" Control A:\t\t0x"); printHex(regs[i], true); break;
+        case 0x42004C01: Serial.print("0x"); Serial.print(i+base, HEX);
+          Serial.print(" Sync:     \t\t0x"); printHex(regs[i], true); break;
+        case 0x42004C04: Serial.print("0x"); Serial.print(i+base, HEX);
+          Serial.print(" Prescaler:\t\t0x"); printHex(regs[i], true); break;
+        case 0x42004C05: Serial.print("0x"); Serial.print(i+base, HEX);
+          Serial.print(" Init:     \t\t0x"); printHex(regs[i], true); break;
+        case 0x42004C08: Serial.print("0x"); Serial.print(i+base, HEX);
+          Serial.print(" Disable Irq:\t\t0x"); printHex(regs[i], true); break;
+        case 0x42004C09: Serial.print("0x"); Serial.print(i+base, HEX);
+          Serial.print(" Enable Irq:\t\t0x"); printHex(regs[i], true); break;
+        case 0x42004C0A: Serial.print("0x"); Serial.print(i+base, HEX);
+          Serial.print(" Flags:     \t\t0x"); printHex(regs[i], true); break;
+        case 0x42004C0C: Serial.print("0x"); Serial.print(i+base, HEX);
+          Serial.print(" Freq Cntl:\t\t0x"); printHex(regs[i], true); break;
+        case 0x42004C0D: Serial.print("0x"); Serial.print(i+base, HEX);
+          Serial.print(" Conv Cntl:\t\t0x"); printHex(regs[i], true); break;
+        case 0x42004C10: Serial.print("0x"); Serial.print(i+base, HEX);
+          Serial.print(" Y Select1:\t\t0x"); printHex(regs[i], true); break;
+        case 0x42004C11: Serial.print("0x"); Serial.print(i+0x42004C00, HEX);
+          Serial.print(" Y Select2:\t\t0x"); printHex(regs[i], true); break;
+/*
+        case 0x42004C12: Serial.print("0x"); Serial.print(i+0x42004C00, HEX);
+          Serial.print(" X Select1:\t\t0x"); printHex(regs[i], true); break;
+        case 0x42004C13: Serial.print("0x"); Serial.print(i+0x42004C00, HEX);
+          Serial.print(" X Select2:\t\t0x"); printHex(regs[i], true); break;
+*/
+        case 0x42004C14: Serial.print("0x"); Serial.print(i+base, HEX);
+          Serial.print(" Y Enable1:\t\t0x"); printHex(regs[i], true); break;
+        case 0x42004C15: Serial.print("0x"); Serial.print(i+0x42004C00, HEX);
+          Serial.print(" Y Enable2:\t\t0x"); printHex(regs[i], true); break;
+/*
+        case 0x42004C16: Serial.print("0x"); Serial.print(i+0x42004C00, HEX);
+          Serial.print(" X Enable1:\t\t0x"); printHex(regs[i], true); break;
+        case 0x42004C17: Serial.print("0x"); Serial.print(i+0x42004C00, HEX);
+          Serial.print(" X Enable2:\t\t0x"); printHex(regs[i], true); break;
+*/
+        case 0x42004C18: Serial.print("0x"); Serial.print(i+base, HEX);
+          Serial.print(" Compcap L:\t\t0x"); printHex(regs[i], true); break;
+        case 0x42004C19: Serial.print("0x"); Serial.print(i+base, HEX);
+          Serial.print(" Compcap H:\t\t0x"); printHex(regs[i], true); break;
+        case 0x42004C1A: Serial.print("0x"); Serial.print(i+base, HEX);
+          Serial.print(" Intcap:   \t\t0x"); printHex(regs[i], true); break;
+        case 0x42004C1B: Serial.print("0x"); Serial.print(i+base, HEX);
+          Serial.print(" Sense res:\t\t0x"); printHex(regs[i], true); break;
+        case 0x42004C1C: Serial.print("0x"); Serial.print(i+base, HEX);
+          Serial.print(" Result L:\t\t0x"); printHex(regs[i], true); break;
+        case 0x42004C1D: Serial.print("0x"); Serial.print(i+base, HEX);
+          Serial.print(" Result H:\t\t0x"); printHex(regs[i], true); break;
+
+       }
+  }
+}
diff --git a/ports/atmel-samd/freetouch/Adafruit_FreeTouch.h b/ports/atmel-samd/freetouch/Adafruit_FreeTouch.h
new file mode 100644
index 0000000000..85dd089881
--- /dev/null
+++ b/ports/atmel-samd/freetouch/Adafruit_FreeTouch.h
@@ -0,0 +1,37 @@
+#ifndef ADAFRUIT_FREETOUCH_H
+#define ADAFRUIT_FREETOUCH_H
+
+#include <Arduino.h>
+#include "adafruit_ptc.h"
+
+class Adafruit_FreeTouch {
+ public:
+  Adafruit_FreeTouch(int p = 0, oversample_t f = OVERSAMPLE_4, series_resistor_t r = RESISTOR_0, freq_mode_t fh = FREQ_MODE_NONE);
+  bool begin(void);
+
+  uint16_t measure(void);
+  uint16_t measureRaw(void);
+
+ private:
+  void ptcInitSettings(void);
+  void ptcConfigIOpin(void);
+  uint16_t startPtcAcquire(void);
+
+  int  getYLine(void);
+  void selectYLine(void);
+  void setOversampling(oversample_t lvl);
+  void setSeriesResistor(series_resistor_t res);
+  void setFreqHopping(freq_mode_t fh, freq_hop_t hops = FREQ_HOP_1);
+  void setCompCap(uint16_t cc);
+  void setIntCap(uint8_t ic);
+
+  void snapshotRegsAndPrint(uint32_t base, uint8_t numregs);
+  void printHex(uint8_t h, boolean newline);
+  void printPTCregs(uint32_t base, uint8_t *regs, uint8_t num);
+
+ private:
+    int pin;           // arduino pin #
+    struct adafruit_ptc_config config;
+};
+
+#endif
diff --git a/ports/atmel-samd/freetouch/README.md b/ports/atmel-samd/freetouch/README.md
new file mode 100644
index 0000000000..3b179a45c1
--- /dev/null
+++ b/ports/atmel-samd/freetouch/README.md
@@ -0,0 +1,2 @@
+# Adafruit_FreeTouch
+A QTouch-compatible library
diff --git a/ports/atmel-samd/freetouch/adafruit_ptc.c b/ports/atmel-samd/freetouch/adafruit_ptc.c
new file mode 100644
index 0000000000..f4369cf4a5
--- /dev/null
+++ b/ports/atmel-samd/freetouch/adafruit_ptc.c
@@ -0,0 +1,148 @@
+/*
+ * FreeTouch, a QTouch-compatible library - tested on ATSAMD21 only!
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Limor 'ladyada' Fried for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "adafruit_ptc.h"
+#include "pinmux.h"
+
+static void sync_config(Ptc const* module_inst) {
+    while (module_inst->CONTROLB.bit.SYNCFLAG) ;
+}
+
+void adafruit_ptc_get_config_default(struct adafruit_ptc_config *config) {
+    config->pin = 0xff;
+    config->yline = -1;
+    config->oversample = OVERSAMPLE_4;
+    config->seriesres = RESISTOR_0;
+    config->freqhop = FREQ_MODE_NONE;
+    config->compcap = 0x2000;
+    config->intcap = 0x3F;
+}
+
+void adafruit_ptc_init(Ptc* module_inst, struct adafruit_ptc_config const* config) {
+    struct system_pinmux_config pinmux_config;
+    system_pinmux_get_config_defaults(&pinmux_config);
+    pinmux_config.mux_position = 0x1;
+    pinmux_config.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE;
+    system_pinmux_pin_set_config(config->pin, &pinmux_config);
+
+    sync_config(module_inst);
+    module_inst->CONTROLA.bit.ENABLE = 0;
+    sync_config(module_inst);
+
+    module_inst->UNK4C04.reg &= 0xF7; //MEMORY[0x42004C04] &= 0xF7u;
+    module_inst->UNK4C04.reg &= 0xFB; //MEMORY[0x42004C04] &= 0xFBu;
+    module_inst->UNK4C04.reg &= 0xFC; //MEMORY[0x42004C04] &= 0xFCu;
+    sync_config(module_inst);
+    module_inst->FREQCONTROL.reg &= 0x9F;       //MEMORY[0x42004C0C] &= 0x9Fu;
+    sync_config(module_inst);
+    module_inst->FREQCONTROL.reg &= 0xEF;       //MEMORY[0x42004C0C] &= 0xEFu;
+    sync_config(module_inst);
+    module_inst->FREQCONTROL.bit.SAMPLEDELAY = 0; //MEMORY[0x42004C0C] &= 0xF0u;
+    module_inst->CONTROLC.bit.INIT = 1;         //MEMORY[0x42004C05] |= 1u;
+    module_inst->CONTROLA.bit.RUNINSTANDBY = 1; //MEMORY[0x42004C00] |= 4u;
+    sync_config(module_inst);
+    module_inst->INTDISABLE.bit.WCO = 1;
+    sync_config(module_inst);
+    module_inst->INTDISABLE.bit.EOC = 1;
+    sync_config(module_inst);
+
+    // enable the sensor, only done once per line
+    if (config->yline < 8) {
+        sync_config(module_inst);
+        module_inst->YENABLEL.reg |= 1 << config->yline;
+        sync_config(module_inst);
+    } else if (config->yline < 16) {
+        module_inst->YENABLEH.reg |= 1 << (config->yline - 8);
+    }
+
+    sync_config(module_inst);
+    module_inst->CONTROLA.bit.ENABLE = 1;
+    sync_config(module_inst);
+}
+
+void adafruit_ptc_start_conversion(Ptc* module_inst, struct adafruit_ptc_config const* config) {
+    module_inst->CONTROLA.bit.RUNINSTANDBY = 1;
+    sync_config(module_inst);
+    module_inst->CONTROLA.bit.ENABLE = 1;
+    sync_config(module_inst);
+    module_inst->INTDISABLE.bit.WCO = 1;
+    sync_config(module_inst);
+    module_inst->INTFLAGS.bit.WCO = 1;
+    sync_config(module_inst);
+    module_inst->INTFLAGS.bit.EOC = 1;
+    sync_config(module_inst);
+
+    // set up pin!
+    sync_config(module_inst);
+    if (config->yline < 8) {
+        module_inst->YSELECTL.reg = 1 << config->yline;
+    } else {
+        module_inst->YSELECTL.reg = 0;
+    }
+
+    if (config->yline > 7) {
+        module_inst->YSELECTH.reg = 1 << (config->yline - 8);
+    } else {
+        module_inst->YSELECTH.reg = 0;
+    }
+
+    sync_config(module_inst);
+    // set up sense resistor
+    module_inst->SERRES.bit.RESISTOR = config->seriesres;
+    sync_config(module_inst);
+    // set up prescalar
+    module_inst->CONVCONTROL.bit.ADCACCUM = config->oversample;
+    sync_config(module_inst);
+    // set up freq hopping
+    if (config->freqhop == FREQ_MODE_NONE) {
+        module_inst->FREQCONTROL.bit.FREQSPREADEN = 0;
+        module_inst->FREQCONTROL.bit.SAMPLEDELAY = 0;
+    } else {
+        module_inst->FREQCONTROL.bit.FREQSPREADEN = 1;
+        module_inst->FREQCONTROL.bit.SAMPLEDELAY = config->hops;
+    }
+    // set up compensation cap + int (?) cap
+    sync_config(module_inst);
+    module_inst->COMPCAPL.bit.VALUE = config->compcap & 0xFF;
+    module_inst->COMPCAPH.bit.VALUE = (config->compcap>>8) & 0x3F;
+    sync_config(module_inst);
+    module_inst->INTCAP.bit.VALUE = config->intcap & 0x3F;
+    sync_config(module_inst);
+
+    module_inst->BURSTMODE.reg = 0xA4;
+    sync_config(module_inst);
+
+    module_inst->CONVCONTROL.bit.CONVERT = 1;
+    sync_config(module_inst);
+}
+
+bool adafruit_ptc_is_conversion_finished(Ptc* module_inst) {
+    return module_inst->CONVCONTROL.bit.CONVERT == 0;
+}
+
+uint16_t adafruit_ptc_get_conversion_result(Ptc* module_inst) {
+    sync_config(module_inst);
+    return module_inst->RESULT.reg;
+}
diff --git a/ports/atmel-samd/freetouch/adafruit_ptc.h b/ports/atmel-samd/freetouch/adafruit_ptc.h
new file mode 100644
index 0000000000..93bb16ef40
--- /dev/null
+++ b/ports/atmel-samd/freetouch/adafruit_ptc.h
@@ -0,0 +1,109 @@
+/*
+ * FreeTouch, a QTouch-compatible library - tested on ATSAMD21 only!
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Limor 'ladyada' Fried for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+// This is similar to the drivers found in sam0/drivers but for the PTC.
+#ifndef ADAFRUIT_FREETOUCH_ADAFRUIT_PTC_H
+#define ADAFRUIT_FREETOUCH_ADAFRUIT_PTC_H
+
+#include <stdint.h>
+
+#include "samd21_ptc_component.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Touch library oversampling (filter) setting */
+typedef enum tag_oversample_level_t {
+	OVERSAMPLE_1,
+	OVERSAMPLE_2,
+	OVERSAMPLE_4,
+	OVERSAMPLE_8,
+	OVERSAMPLE_16,
+	OVERSAMPLE_32,
+	OVERSAMPLE_64
+}
+oversample_t;
+
+/* Touch library series resistor setting */
+typedef enum tag_series_resistor_t {
+	RESISTOR_0,
+	RESISTOR_20K,
+	RESISTOR_50K,
+	RESISTOR_100K,
+}
+series_resistor_t;
+
+typedef enum tag_freq_mode_t {
+	FREQ_MODE_NONE,
+	FREQ_MODE_HOP,
+	FREQ_MODE_SPREAD,
+	FREQ_MODE_SPREAD_MEDIAN
+}
+freq_mode_t;
+
+typedef enum tag_freq_hop_t {
+	FREQ_HOP_1,
+	FREQ_HOP_2,
+	FREQ_HOP_3,
+	FREQ_HOP_4,
+	FREQ_HOP_5,
+	FREQ_HOP_6,
+	FREQ_HOP_7,
+	FREQ_HOP_8,
+	FREQ_HOP_9,
+	FREQ_HOP_10,
+	FREQ_HOP_11,
+	FREQ_HOP_12,
+	FREQ_HOP_13,
+	FREQ_HOP_14,
+	FREQ_HOP_15,
+	FREQ_HOP_16
+}
+freq_hop_t;
+
+struct adafruit_ptc_config {
+    uint8_t pin;           // ASF pin #
+    int8_t yline;      // the Y select line (see datasheet)
+    oversample_t oversample;
+    series_resistor_t seriesres;
+    freq_mode_t freqhop;
+    freq_hop_t hops;
+    uint16_t compcap;
+    uint8_t  intcap;
+};
+
+void adafruit_ptc_get_config_default(struct adafruit_ptc_config *config);
+void adafruit_ptc_init(Ptc* module_inst, struct adafruit_ptc_config const* config);
+void adafruit_ptc_start_conversion(Ptc* module_inst, struct adafruit_ptc_config const* config);
+
+bool adafruit_ptc_is_conversion_finished(Ptc* module_inst);
+uint16_t adafruit_ptc_get_conversion_result(Ptc* module_inst);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  // ADAFRUIT_FREETOUCH_ADAFRUIT_PTC_H
diff --git a/ports/atmel-samd/freetouch/examples/freetouch/freetouch.ino b/ports/atmel-samd/freetouch/examples/freetouch/freetouch.ino
new file mode 100644
index 0000000000..d89642c2e5
--- /dev/null
+++ b/ports/atmel-samd/freetouch/examples/freetouch/freetouch.ino
@@ -0,0 +1,56 @@
+#include "Adafruit_FreeTouch.h"
+
+Adafruit_FreeTouch qt_1 = Adafruit_FreeTouch(A0, OVERSAMPLE_4, RESISTOR_50K, FREQ_MODE_NONE);
+Adafruit_FreeTouch qt_2 = Adafruit_FreeTouch(A1, OVERSAMPLE_4, RESISTOR_50K, FREQ_MODE_NONE);
+Adafruit_FreeTouch qt_3 = Adafruit_FreeTouch(A2, OVERSAMPLE_4, RESISTOR_50K, FREQ_MODE_NONE);
+Adafruit_FreeTouch qt_4 = Adafruit_FreeTouch(A3, OVERSAMPLE_4, RESISTOR_50K, FREQ_MODE_NONE);
+
+void setup() {
+  Serial.begin(115200);
+  
+  while (!Serial);
+  Serial.println("FreeTouch test");
+  // initialize digital pin LED_BUILTIN as an output.
+  pinMode(LED_BUILTIN, OUTPUT);
+
+  if (! qt_1.begin())  
+    Serial.println("Failed to begin qt on pin A0");
+  if (! qt_2.begin())  
+    Serial.println("Failed to begin qt on pin A1");
+  if (! qt_3.begin())  
+    Serial.println("Failed to begin qt on pin A2");
+  if (! qt_4.begin())  
+    Serial.println("Failed to begin qt on pin A3");
+
+}
+
+
+
+void loop() {
+  int counter, result = 0;
+  
+  // DIY
+  Serial.println("\n*************************************");
+
+  counter = millis();
+  result = qt_1.measure(); 
+  Serial.print("QT 1: "); Serial.print(result);
+  Serial.print(" (");  Serial.print(millis() - counter); Serial.println(" ms)");
+
+  counter = millis();
+  result = qt_2.measure(); 
+  Serial.print("QT 2: "); Serial.print(result);
+  Serial.print(" (");  Serial.print(millis() - counter); Serial.println(" ms)");
+
+  counter = millis();
+  result = qt_3.measure(); 
+  Serial.print("QT 3: "); Serial.print(result);
+  Serial.print(" (");  Serial.print(millis() - counter); Serial.println(" ms)");
+  
+  counter = millis();
+  result = qt_4.measure(); 
+  Serial.print("QT 4: "); Serial.print(result);
+  Serial.print(" (");  Serial.print(millis() - counter); Serial.println(" ms)");
+  
+  delay(200);
+}
\ No newline at end of file
diff --git a/ports/atmel-samd/freetouch/samd21_ptc_component.h b/ports/atmel-samd/freetouch/samd21_ptc_component.h
new file mode 100644
index 0000000000..0af3236d38
--- /dev/null
+++ b/ports/atmel-samd/freetouch/samd21_ptc_component.h
@@ -0,0 +1,350 @@
+/*
+ * FreeTouch, a QTouch-compatible library - tested on ATSAMD21 only!
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Limor 'ladyada' Fried for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+// This is similar to the component definitions found in
+// sam0/utils/cmsis/samd21/include/component but for the PTC.
+#ifndef ADAFRUIT_FREETOUCH_PTC_COMPONENT_H
+#define ADAFRUIT_FREETOUCH_PTC_COMPONENT_H
+
+#include "compiler.h"
+
+#undef ENABLE
+
+/*************** CONTROL A register ***************/
+#define PTC_REG_CONTROLA   0x42004C00
+#define PTC_BIT_ENABLE     0x02
+#define PTC_BIT_RUNINSTBY  0x04
+
+
+typedef union {
+  struct {
+    uint8_t   SWRESET:1;
+    uint8_t   ENABLE:1;
+    uint8_t   RUNINSTANDBY:1;
+    uint8_t   __pad0__:5;
+  } bit;
+  uint8_t reg;
+} PTC_REG_CONTROLA_Type;
+
+/*************** CONTROL B register ***************/
+
+#define PTC_REG_CONTROLB 0x42004C01
+#define PTC_BIT_SYNCFLAG 0x80
+
+typedef union {
+  struct {
+    uint8_t   __pad0__:7;
+    uint8_t   SYNCFLAG:1;
+  } bit;
+  uint8_t reg;
+} PTC_REG_CONTROLB_Type;
+
+/*************** UNK4C04 register ***************/
+
+#define PTC_REG_UNK4C04 0x42004C04
+
+typedef union {
+  uint8_t reg;
+} PTC_REG_UNK4C04_Type;
+
+
+/*************** CONTROL C register ***************/
+
+#define PTC_REG_CONTROLC 0x42004C05
+#define PTC_BIT_INIT 0x01
+
+typedef union {
+  struct {
+    uint8_t   INIT:1;
+    uint8_t   __pad0__:7;
+  } bit;
+  uint8_t reg;
+} PTC_REG_CONTROLC_Type;
+
+
+
+/*************** INT registers ***************/
+
+typedef union {
+  struct {
+    uint8_t   EOC:1;
+    uint8_t   WCO:1;
+    uint8_t   __pad0__:6;
+  } bit;
+  uint8_t reg;
+} PTC_REG_INT_Type;
+
+
+#define PTC_REG_INTDISABLE 0x42004C08
+#define PTC_REG_INTENABLE 0x42004C09
+#define PTC_BIT_EOCINTEN  0x01
+#define PTC_BIT_WCOINTEN  0x02
+
+#define PTC_REG_INTFLAGS 0x42004C0A
+#define PTC_BIT_EOCINTFLAG 0x01
+#define PTC_BIT_WCOINTFLAG 0x02
+
+
+/*************** FREQ CONTROL reg ***************/
+
+typedef union {
+  struct {
+    uint8_t   SAMPLEDELAY:4;
+    uint8_t   FREQSPREADEN:1;
+    uint8_t   __pad0__:3;
+  } bit;
+  uint8_t reg;
+} PTC_REG_FREQCONTROL_Type;
+
+#define PTC_REG_FREQCONTROL 0x42004C0C
+#define PTC_BIT_FREQSPREADEN 0x10
+#define PTC_REG_SAMPLEDELAY_MASK 0x0F
+
+/*************** CONVERT CONTROL reg ***************/
+
+typedef union {
+  struct {
+    uint8_t   ADCACCUM:3;
+    uint8_t   __pad0__:4;
+    uint8_t   CONVERT:1;
+  } bit;
+  uint8_t reg;
+} __attribute__ ((packed)) PTC_REG_CONVCONTROL_Type;
+
+
+#define PTC_REG_CONVCONTROL 0x42004C0D
+#define PTC_BIT_CONVSTARTED 0x80
+#define PTC_REG_ADCACC_MASK 0x07
+
+
+/*************** Y SELECT L+H reg ***************/
+
+typedef union {
+  struct {
+    uint8_t   Y0:1;
+    uint8_t   Y1:1;
+    uint8_t   Y2:1;
+    uint8_t   Y3:1;
+    uint8_t   Y4:1;
+    uint8_t   Y5:1;
+    uint8_t   Y6:1;
+    uint8_t   Y7:1;
+  } bit;
+  uint8_t reg;
+} __attribute__ ((packed)) PTC_REG_YSELECTL_Type;
+
+typedef union {
+  struct {
+    uint8_t   Y8:1;
+    uint8_t   Y9:1;
+    uint8_t   Y10:1;
+    uint8_t   Y11:1;
+    uint8_t   Y12:1;
+    uint8_t   Y13:1;
+    uint8_t   Y14:1;
+    uint8_t   Y15:1;
+  } bit;
+  uint8_t reg;
+} __attribute__ ((packed)) PTC_REG_YSELECTH_Type;
+
+#define PTC_REG_YSELECT_L 0x42004C10
+#define PTC_REG_YSELECT_H 0x42004C11
+
+#define PTC_REG_YENABLE_L 0x42004C14
+#define PTC_REG_YENABLE_H 0x42004C15
+
+
+/*************** X SELECT L+H reg ***************/
+
+typedef union {
+  struct {
+    uint8_t   X0:1;
+    uint8_t   X1:1;
+    uint8_t   X2:1;
+    uint8_t   X3:1;
+    uint8_t   X4:1;
+    uint8_t   X5:1;
+    uint8_t   X6:1;
+    uint8_t   X7:1;
+  } bit;
+  uint8_t reg;
+} __attribute__ ((packed)) PTC_REG_XSELECTL_Type;
+
+typedef union {
+  struct {
+    uint8_t   X8:1;
+    uint8_t   X9:1;
+    uint8_t   X10:1;
+    uint8_t   X11:1;
+    uint8_t   X12:1;
+    uint8_t   X13:1;
+    uint8_t   X14:1;
+    uint8_t   X15:1;
+  } bit;
+  uint8_t reg;
+} __attribute__ ((packed)) PTC_REG_XSELECTH_Type;
+
+
+#define PTC_REG_XSELECT_L 0x42004C12
+#define PTC_REG_XSELECT_H 0x42004C13
+
+#define PTC_REG_XENABLE_L 0x42004C16
+#define PTC_REG_XENABLE_H 0x42004C17
+
+/*************** Compensation Cap reg ***************/
+
+typedef union {
+  struct {
+    uint8_t   VALUE:8;
+  } bit;
+  uint8_t reg;
+} __attribute__ ((packed)) PTC_REG_COMPCAPL_Type;
+
+typedef union {
+  struct {
+    uint8_t   VALUE:6;
+    uint8_t   __pad0__:2;
+  } bit;
+  uint8_t reg;
+} __attribute__ ((packed)) PTC_REG_COMPCAPH_Type;
+
+#define PTC_REG_COMPCAPL    0x42004C18
+#define PTC_REG_COMPCAPH    0x42004C19
+
+/*************** Int Cap reg ***************/
+
+typedef union {
+  struct {
+    uint8_t   VALUE:6;
+    uint8_t   __pad0__:2;
+  } bit;
+  uint8_t reg;
+} __attribute__ ((packed)) PTC_REG_INTCAP_Type;
+
+
+#define PTC_REG_INTCAP    0x42004C1A
+
+/*************** Series resistor reg ***************/
+
+typedef union {
+  struct {
+    uint8_t   RESISTOR:2;
+    uint8_t   __pad0__:6;
+  } bit;
+  uint8_t reg;
+} __attribute__ ((packed)) PTC_REG_SERRES_Type;
+
+#define PTC_REG_SERIESRES    0x42004C1B
+
+/*************** conversion result reg ***************/
+
+typedef union {
+  struct {
+    uint8_t   LOWBYTE;
+    uint8_t   HIGHBYTE;
+  } byte;
+  uint16_t reg;
+} __attribute__ ((packed)) PTC_REG_CONVRESULT_Type;
+
+#define PTC_REG_CONVRESULT_L 0x42004C1C
+#define PTC_REG_CONVRESULT_H 0x42004C1D
+
+/*************** burst mode reg ***************/
+
+typedef union {
+  struct {
+    uint8_t   __pad0__:2;
+    uint8_t   CTSLOWPOWER:1;
+    uint8_t   __pad1__:1;
+    uint8_t   BURSTMODE:4;
+  } bit;
+  uint8_t reg;
+} __attribute__ ((packed)) PTC_REG_BURSTMODE_Type;
+
+
+#define PTC_REG_BURSTMODE     0x42004C20
+#define PTC_REG_BURSTMODE_MASK   0xF0
+#define PTC_BIT_CTSLOWPOWER   0x04
+
+/*************** etc unused reg ***************/
+
+#define PTC_REG_XYENABLE     0x42004C16
+#define PTC_BIT_XYENABLE     0x02
+
+#define PTC_REG_WCO_MODE     0x42004C21
+#define PTC_REG_WCO_MODE_MASK   0x07
+
+#define PTC_SET_WCO_THRESHHOLD_A_L 0x42004C24
+#define PTC_SET_WCO_THRESHHOLD_A_H 0x42004C25
+#define PTC_SET_WCO_THRESHHOLD_B_L 0x42004C26
+#define PTC_SET_WCO_THRESHHOLD_B_H 0x42004C27
+
+typedef struct {
+  __IO PTC_REG_CONTROLA_Type CONTROLA;    // 0x42004C00
+  __IO PTC_REG_CONTROLB_Type CONTROLB;    // 0x42004C01
+  uint8_t   __pad4c02__;                // 0x42004C02 unknown
+  uint8_t   __pad4c03__;                // 0x42004C03 unknown
+  __IO PTC_REG_UNK4C04_Type  UNK4C04;   // 0x42004C04 unknown
+  __IO PTC_REG_CONTROLC_Type CONTROLC;    // 0x42004C05
+  uint8_t   __pad4c06__;                // 0x42004C06 unknown
+  uint8_t   __pad4c07__;                // 0x42004C07 unknown
+  __IO PTC_REG_INT_Type      INTDISABLE;  // 0x42004C08
+  __IO PTC_REG_INT_Type      INTENABLE;   // 0x42004C09
+  __IO PTC_REG_INT_Type      INTFLAGS;    // 0x42004C0A
+  uint8_t   __pad4c0b__;                // 0x42004C0B unknown
+  __IO PTC_REG_FREQCONTROL_Type FREQCONTROL;  //0x42004C0C
+  __IO PTC_REG_CONVCONTROL_Type CONVCONTROL;  // 0x42004C0D
+  uint8_t   __pad4c0e__;                // 0x42004C0E unknown
+  uint8_t   __pad4c0f__;                // 0x42004C0F unknown
+  __IO PTC_REG_YSELECTL_Type YSELECTL;  // 0x42004C10
+  __IO PTC_REG_YSELECTL_Type YSELECTH;  // 0x42004C11
+  __IO PTC_REG_XSELECTL_Type XSELECTL;  // 0x42004C12
+  __IO PTC_REG_XSELECTL_Type XSELECTH;  // 0x42004C13
+  __IO PTC_REG_YSELECTL_Type YENABLEL;  // 0x42004C14
+  __IO PTC_REG_YSELECTL_Type YENABLEH;  // 0x42004C15
+  __IO PTC_REG_XSELECTL_Type XENABLEL;  // 0x42004C16
+  __IO PTC_REG_XSELECTL_Type XENABLEH;  // 0x42004C17
+
+  __IO PTC_REG_COMPCAPL_Type COMPCAPL;  // 0x42004C18
+  __IO PTC_REG_COMPCAPH_Type COMPCAPH;  // 0x42004C19
+  __IO PTC_REG_INTCAP_Type   INTCAP;    // 0x42004C1A
+  __IO PTC_REG_SERRES_Type   SERRES;    // 0x42004C1B
+
+  __IO PTC_REG_CONVRESULT_Type RESULT;  // 0x42004C1C + 0x42004C1D
+  uint8_t   __pad4c1e__;                // 0x42004C1E unknown
+  uint8_t   __pad4c1f__;                // 0x42004C1F unknown
+  __IO PTC_REG_BURSTMODE_Type BURSTMODE; // 0x42004C20
+} Ptc;
+
+#define PTC  (( Ptc *)0x42004C00U)
+
+#define PTC_REG_INTDISABLE 0x42004C08
+#define PTC_REG_INTENABLE 0x42004C09
+#define PTC_BIT_EOCINTEN  0x01
+#define PTC_BIT_WCOINTEN  0x02
+
+#define PTC_REG_INTFLAGS 0x42004C0A
+
+#endif  // ADAFRUIT_FREETOUCH_PTC_COMPONENT_H
diff --git a/atmel-samd/internal_flash.c b/ports/atmel-samd/internal_flash.c
similarity index 100%
rename from atmel-samd/internal_flash.c
rename to ports/atmel-samd/internal_flash.c
diff --git a/atmel-samd/internal_flash.h b/ports/atmel-samd/internal_flash.h
similarity index 100%
rename from atmel-samd/internal_flash.h
rename to ports/atmel-samd/internal_flash.h
diff --git a/atmel-samd/modules/frozentest.py b/ports/atmel-samd/modules/frozentest.py
similarity index 100%
rename from atmel-samd/modules/frozentest.py
rename to ports/atmel-samd/modules/frozentest.py
diff --git a/atmel-samd/mpconfigport.h b/ports/atmel-samd/mpconfigport.h
similarity index 100%
rename from atmel-samd/mpconfigport.h
rename to ports/atmel-samd/mpconfigport.h
diff --git a/atmel-samd/mpconfigport.mk b/ports/atmel-samd/mpconfigport.mk
similarity index 100%
rename from atmel-samd/mpconfigport.mk
rename to ports/atmel-samd/mpconfigport.mk
diff --git a/atmel-samd/mphalport.c b/ports/atmel-samd/mphalport.c
similarity index 100%
rename from atmel-samd/mphalport.c
rename to ports/atmel-samd/mphalport.c
diff --git a/atmel-samd/mphalport.h b/ports/atmel-samd/mphalport.h
similarity index 100%
rename from atmel-samd/mphalport.h
rename to ports/atmel-samd/mphalport.h
diff --git a/atmel-samd/pins.h b/ports/atmel-samd/pins.h
similarity index 100%
rename from atmel-samd/pins.h
rename to ports/atmel-samd/pins.h
diff --git a/atmel-samd/qstrdefsport.h b/ports/atmel-samd/qstrdefsport.h
similarity index 100%
rename from atmel-samd/qstrdefsport.h
rename to ports/atmel-samd/qstrdefsport.h
diff --git a/atmel-samd/reset.c b/ports/atmel-samd/reset.c
similarity index 100%
rename from atmel-samd/reset.c
rename to ports/atmel-samd/reset.c
diff --git a/atmel-samd/reset.h b/ports/atmel-samd/reset.h
similarity index 100%
rename from atmel-samd/reset.h
rename to ports/atmel-samd/reset.h
diff --git a/atmel-samd/samd21_pins.c b/ports/atmel-samd/samd21_pins.c
similarity index 100%
rename from atmel-samd/samd21_pins.c
rename to ports/atmel-samd/samd21_pins.c
diff --git a/atmel-samd/samd21_pins.h b/ports/atmel-samd/samd21_pins.h
similarity index 100%
rename from atmel-samd/samd21_pins.h
rename to ports/atmel-samd/samd21_pins.h
diff --git a/atmel-samd/samd51_pins.c b/ports/atmel-samd/samd51_pins.c
similarity index 100%
rename from atmel-samd/samd51_pins.c
rename to ports/atmel-samd/samd51_pins.c
diff --git a/atmel-samd/samd51_pins.h b/ports/atmel-samd/samd51_pins.h
similarity index 100%
rename from atmel-samd/samd51_pins.h
rename to ports/atmel-samd/samd51_pins.h
diff --git a/atmel-samd/shared_dma.c b/ports/atmel-samd/shared_dma.c
similarity index 100%
rename from atmel-samd/shared_dma.c
rename to ports/atmel-samd/shared_dma.c
diff --git a/atmel-samd/shared_dma.h b/ports/atmel-samd/shared_dma.h
similarity index 100%
rename from atmel-samd/shared_dma.h
rename to ports/atmel-samd/shared_dma.h
diff --git a/atmel-samd/spi_flash.c b/ports/atmel-samd/spi_flash.c
similarity index 100%
rename from atmel-samd/spi_flash.c
rename to ports/atmel-samd/spi_flash.c
diff --git a/atmel-samd/spi_flash.h b/ports/atmel-samd/spi_flash.h
similarity index 100%
rename from atmel-samd/spi_flash.h
rename to ports/atmel-samd/spi_flash.h
diff --git a/atmel-samd/supervisor/filesystem.c b/ports/atmel-samd/supervisor/filesystem.c
similarity index 100%
rename from atmel-samd/supervisor/filesystem.c
rename to ports/atmel-samd/supervisor/filesystem.c
diff --git a/atmel-samd/supervisor/port.c b/ports/atmel-samd/supervisor/port.c
similarity index 100%
rename from atmel-samd/supervisor/port.c
rename to ports/atmel-samd/supervisor/port.c
diff --git a/atmel-samd/supervisor/serial.c b/ports/atmel-samd/supervisor/serial.c
similarity index 100%
rename from atmel-samd/supervisor/serial.c
rename to ports/atmel-samd/supervisor/serial.c
diff --git a/atmel-samd/tick.c b/ports/atmel-samd/tick.c
similarity index 100%
rename from atmel-samd/tick.c
rename to ports/atmel-samd/tick.c
diff --git a/atmel-samd/tick.h b/ports/atmel-samd/tick.h
similarity index 100%
rename from atmel-samd/tick.h
rename to ports/atmel-samd/tick.h
diff --git a/atmel-samd/tools/bossac_linux b/ports/atmel-samd/tools/bossac_linux
similarity index 100%
rename from atmel-samd/tools/bossac_linux
rename to ports/atmel-samd/tools/bossac_linux
diff --git a/atmel-samd/tools/bossac_osx b/ports/atmel-samd/tools/bossac_osx
similarity index 100%
rename from atmel-samd/tools/bossac_osx
rename to ports/atmel-samd/tools/bossac_osx
diff --git a/atmel-samd/tools/gen_pin_name_table.py b/ports/atmel-samd/tools/gen_pin_name_table.py
similarity index 100%
rename from atmel-samd/tools/gen_pin_name_table.py
rename to ports/atmel-samd/tools/gen_pin_name_table.py
diff --git a/atmel-samd/tools/samd21.json b/ports/atmel-samd/tools/samd21.json
similarity index 100%
rename from atmel-samd/tools/samd21.json
rename to ports/atmel-samd/tools/samd21.json
diff --git a/atmel-samd/tools/samd51.json b/ports/atmel-samd/tools/samd51.json
similarity index 100%
rename from atmel-samd/tools/samd51.json
rename to ports/atmel-samd/tools/samd51.json
diff --git a/atmel-samd/tools/update_asf.py b/ports/atmel-samd/tools/update_asf.py
similarity index 100%
rename from atmel-samd/tools/update_asf.py
rename to ports/atmel-samd/tools/update_asf.py
diff --git a/atmel-samd/usb.c b/ports/atmel-samd/usb.c
similarity index 100%
rename from atmel-samd/usb.c
rename to ports/atmel-samd/usb.c
diff --git a/atmel-samd/usb.h b/ports/atmel-samd/usb.h
similarity index 100%
rename from atmel-samd/usb.h
rename to ports/atmel-samd/usb.h
diff --git a/atmel-samd/usb_mass_storage.c b/ports/atmel-samd/usb_mass_storage.c
similarity index 100%
rename from atmel-samd/usb_mass_storage.c
rename to ports/atmel-samd/usb_mass_storage.c
diff --git a/atmel-samd/usb_mass_storage.h b/ports/atmel-samd/usb_mass_storage.h
similarity index 100%
rename from atmel-samd/usb_mass_storage.h
rename to ports/atmel-samd/usb_mass_storage.h
diff --git a/bare-arm/Makefile b/ports/bare-arm/Makefile
similarity index 97%
rename from bare-arm/Makefile
rename to ports/bare-arm/Makefile
index 90c13de11f..0fcd5d0272 100644
--- a/bare-arm/Makefile
+++ b/ports/bare-arm/Makefile
@@ -1,4 +1,4 @@
-include ../py/mkenv.mk
+include ../../py/mkenv.mk
 
 # qstr definitions (must come before including py.mk)
 QSTR_DEFS = qstrdefsport.h
diff --git a/bare-arm/main.c b/ports/bare-arm/main.c
similarity index 99%
rename from bare-arm/main.c
rename to ports/bare-arm/main.c
index 938414dfe8..b96fb47ace 100644
--- a/bare-arm/main.c
+++ b/ports/bare-arm/main.c
@@ -2,7 +2,6 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "py/nlr.h"
 #include "py/compile.h"
 #include "py/runtime.h"
 #include "py/repl.h"
diff --git a/bare-arm/mpconfigport.h b/ports/bare-arm/mpconfigport.h
similarity index 100%
rename from bare-arm/mpconfigport.h
rename to ports/bare-arm/mpconfigport.h
diff --git a/bare-arm/mphalport.h b/ports/bare-arm/mphalport.h
similarity index 100%
rename from bare-arm/mphalport.h
rename to ports/bare-arm/mphalport.h
diff --git a/bare-arm/qstrdefsport.h b/ports/bare-arm/qstrdefsport.h
similarity index 100%
rename from bare-arm/qstrdefsport.h
rename to ports/bare-arm/qstrdefsport.h
diff --git a/bare-arm/stm32f405.ld b/ports/bare-arm/stm32f405.ld
similarity index 100%
rename from bare-arm/stm32f405.ld
rename to ports/bare-arm/stm32f405.ld
diff --git a/cc3200/FreeRTOS/FreeRTOSConfig.h b/ports/cc3200/FreeRTOS/FreeRTOSConfig.h
similarity index 100%
rename from cc3200/FreeRTOS/FreeRTOSConfig.h
rename to ports/cc3200/FreeRTOS/FreeRTOSConfig.h
diff --git a/cc3200/FreeRTOS/License/license.txt b/ports/cc3200/FreeRTOS/License/license.txt
similarity index 100%
rename from cc3200/FreeRTOS/License/license.txt
rename to ports/cc3200/FreeRTOS/License/license.txt
diff --git a/cc3200/FreeRTOS/Source/croutine.c b/ports/cc3200/FreeRTOS/Source/croutine.c
similarity index 100%
rename from cc3200/FreeRTOS/Source/croutine.c
rename to ports/cc3200/FreeRTOS/Source/croutine.c
diff --git a/cc3200/FreeRTOS/Source/event_groups.c b/ports/cc3200/FreeRTOS/Source/event_groups.c
similarity index 100%
rename from cc3200/FreeRTOS/Source/event_groups.c
rename to ports/cc3200/FreeRTOS/Source/event_groups.c
diff --git a/cc3200/FreeRTOS/Source/include/FreeRTOS.h b/ports/cc3200/FreeRTOS/Source/include/FreeRTOS.h
similarity index 100%
rename from cc3200/FreeRTOS/Source/include/FreeRTOS.h
rename to ports/cc3200/FreeRTOS/Source/include/FreeRTOS.h
diff --git a/cc3200/FreeRTOS/Source/include/StackMacros.h b/ports/cc3200/FreeRTOS/Source/include/StackMacros.h
similarity index 100%
rename from cc3200/FreeRTOS/Source/include/StackMacros.h
rename to ports/cc3200/FreeRTOS/Source/include/StackMacros.h
diff --git a/cc3200/FreeRTOS/Source/include/croutine.h b/ports/cc3200/FreeRTOS/Source/include/croutine.h
similarity index 100%
rename from cc3200/FreeRTOS/Source/include/croutine.h
rename to ports/cc3200/FreeRTOS/Source/include/croutine.h
diff --git a/cc3200/FreeRTOS/Source/include/deprecated_definitions.h b/ports/cc3200/FreeRTOS/Source/include/deprecated_definitions.h
similarity index 100%
rename from cc3200/FreeRTOS/Source/include/deprecated_definitions.h
rename to ports/cc3200/FreeRTOS/Source/include/deprecated_definitions.h
diff --git a/cc3200/FreeRTOS/Source/include/event_groups.h b/ports/cc3200/FreeRTOS/Source/include/event_groups.h
similarity index 100%
rename from cc3200/FreeRTOS/Source/include/event_groups.h
rename to ports/cc3200/FreeRTOS/Source/include/event_groups.h
diff --git a/cc3200/FreeRTOS/Source/include/list.h b/ports/cc3200/FreeRTOS/Source/include/list.h
similarity index 100%
rename from cc3200/FreeRTOS/Source/include/list.h
rename to ports/cc3200/FreeRTOS/Source/include/list.h
diff --git a/cc3200/FreeRTOS/Source/include/mpu_prototypes.h b/ports/cc3200/FreeRTOS/Source/include/mpu_prototypes.h
similarity index 100%
rename from cc3200/FreeRTOS/Source/include/mpu_prototypes.h
rename to ports/cc3200/FreeRTOS/Source/include/mpu_prototypes.h
diff --git a/cc3200/FreeRTOS/Source/include/mpu_wrappers.h b/ports/cc3200/FreeRTOS/Source/include/mpu_wrappers.h
similarity index 100%
rename from cc3200/FreeRTOS/Source/include/mpu_wrappers.h
rename to ports/cc3200/FreeRTOS/Source/include/mpu_wrappers.h
diff --git a/cc3200/FreeRTOS/Source/include/portable.h b/ports/cc3200/FreeRTOS/Source/include/portable.h
similarity index 100%
rename from cc3200/FreeRTOS/Source/include/portable.h
rename to ports/cc3200/FreeRTOS/Source/include/portable.h
diff --git a/cc3200/FreeRTOS/Source/include/projdefs.h b/ports/cc3200/FreeRTOS/Source/include/projdefs.h
similarity index 100%
rename from cc3200/FreeRTOS/Source/include/projdefs.h
rename to ports/cc3200/FreeRTOS/Source/include/projdefs.h
diff --git a/cc3200/FreeRTOS/Source/include/queue.h b/ports/cc3200/FreeRTOS/Source/include/queue.h
similarity index 100%
rename from cc3200/FreeRTOS/Source/include/queue.h
rename to ports/cc3200/FreeRTOS/Source/include/queue.h
diff --git a/cc3200/FreeRTOS/Source/include/semphr.h b/ports/cc3200/FreeRTOS/Source/include/semphr.h
similarity index 100%
rename from cc3200/FreeRTOS/Source/include/semphr.h
rename to ports/cc3200/FreeRTOS/Source/include/semphr.h
diff --git a/cc3200/FreeRTOS/Source/include/task.h b/ports/cc3200/FreeRTOS/Source/include/task.h
similarity index 100%
rename from cc3200/FreeRTOS/Source/include/task.h
rename to ports/cc3200/FreeRTOS/Source/include/task.h
diff --git a/cc3200/FreeRTOS/Source/include/timers.h b/ports/cc3200/FreeRTOS/Source/include/timers.h
similarity index 100%
rename from cc3200/FreeRTOS/Source/include/timers.h
rename to ports/cc3200/FreeRTOS/Source/include/timers.h
diff --git a/cc3200/FreeRTOS/Source/list.c b/ports/cc3200/FreeRTOS/Source/list.c
similarity index 100%
rename from cc3200/FreeRTOS/Source/list.c
rename to ports/cc3200/FreeRTOS/Source/list.c
diff --git a/cc3200/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c b/ports/cc3200/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c
similarity index 100%
rename from cc3200/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c
rename to ports/cc3200/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c
diff --git a/cc3200/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h b/ports/cc3200/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h
similarity index 100%
rename from cc3200/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h
rename to ports/cc3200/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h
diff --git a/cc3200/FreeRTOS/Source/portable/MemMang/heap_4.c b/ports/cc3200/FreeRTOS/Source/portable/MemMang/heap_4.c
similarity index 100%
rename from cc3200/FreeRTOS/Source/portable/MemMang/heap_4.c
rename to ports/cc3200/FreeRTOS/Source/portable/MemMang/heap_4.c
diff --git a/cc3200/FreeRTOS/Source/queue.c b/ports/cc3200/FreeRTOS/Source/queue.c
similarity index 100%
rename from cc3200/FreeRTOS/Source/queue.c
rename to ports/cc3200/FreeRTOS/Source/queue.c
diff --git a/cc3200/FreeRTOS/Source/tasks.c b/ports/cc3200/FreeRTOS/Source/tasks.c
similarity index 100%
rename from cc3200/FreeRTOS/Source/tasks.c
rename to ports/cc3200/FreeRTOS/Source/tasks.c
diff --git a/cc3200/FreeRTOS/Source/timers.c b/ports/cc3200/FreeRTOS/Source/timers.c
similarity index 100%
rename from cc3200/FreeRTOS/Source/timers.c
rename to ports/cc3200/FreeRTOS/Source/timers.c
diff --git a/cc3200/Makefile b/ports/cc3200/Makefile
similarity index 98%
rename from cc3200/Makefile
rename to ports/cc3200/Makefile
index 4c8b0b8325..81531b1084 100644
--- a/cc3200/Makefile
+++ b/ports/cc3200/Makefile
@@ -14,7 +14,7 @@ PORT ?= /dev/ttyUSB1
 # If the build directory is not given, make it reflect the board name.
 BUILD ?= build/$(BOARD)/$(BTYPE)
 
-include ../py/mkenv.mk
+include ../../py/mkenv.mk
 -include ../../localconfig.mk
 
 CROSS_COMPILE ?= arm-none-eabi-
diff --git a/cc3200/README.md b/ports/cc3200/README.md
similarity index 100%
rename from cc3200/README.md
rename to ports/cc3200/README.md
diff --git a/cc3200/application.lds b/ports/cc3200/application.lds
similarity index 100%
rename from cc3200/application.lds
rename to ports/cc3200/application.lds
diff --git a/cc3200/application.mk b/ports/cc3200/application.mk
similarity index 98%
rename from cc3200/application.mk
rename to ports/cc3200/application.mk
index 3ac28823a1..19abe66163 100644
--- a/cc3200/application.mk
+++ b/ports/cc3200/application.mk
@@ -18,7 +18,7 @@ APP_INC += -Iutil
 APP_INC += -Ibootmgr
 APP_INC += -I$(BUILD)
 APP_INC += -I$(BUILD)/genhdr
-APP_INC += -I$(TOP)/stmhal
+APP_INC += -I$(TOP)/ports/stm32
 
 APP_CPPDEFINES = -Dgcc -DTARGET_IS_CC3200 -DSL_FULL -DUSE_FREERTOS
 
@@ -147,10 +147,11 @@ APP_LIB_SRC_C = $(addprefix lib/,\
 	netutils/netutils.c \
 	timeutils/timeutils.c \
 	utils/pyexec.c \
+	utils/interrupt_char.c \
 	utils/sys_stdio_mphal.c \
 	)
 	
-APP_STM_SRC_C = $(addprefix stmhal/,\
+APP_STM_SRC_C = $(addprefix ports/stm32/,\
 	bufhelper.c \
 	irq.c \
 	)
diff --git a/cc3200/appsign.sh b/ports/cc3200/appsign.sh
similarity index 100%
rename from cc3200/appsign.sh
rename to ports/cc3200/appsign.sh
diff --git a/cc3200/boards/LAUNCHXL/mpconfigboard.h b/ports/cc3200/boards/LAUNCHXL/mpconfigboard.h
similarity index 100%
rename from cc3200/boards/LAUNCHXL/mpconfigboard.h
rename to ports/cc3200/boards/LAUNCHXL/mpconfigboard.h
diff --git a/cc3200/boards/LAUNCHXL/pins.csv b/ports/cc3200/boards/LAUNCHXL/pins.csv
similarity index 100%
rename from cc3200/boards/LAUNCHXL/pins.csv
rename to ports/cc3200/boards/LAUNCHXL/pins.csv
diff --git a/cc3200/boards/WIPY/mpconfigboard.h b/ports/cc3200/boards/WIPY/mpconfigboard.h
similarity index 100%
rename from cc3200/boards/WIPY/mpconfigboard.h
rename to ports/cc3200/boards/WIPY/mpconfigboard.h
diff --git a/cc3200/boards/WIPY/pins.csv b/ports/cc3200/boards/WIPY/pins.csv
similarity index 100%
rename from cc3200/boards/WIPY/pins.csv
rename to ports/cc3200/boards/WIPY/pins.csv
diff --git a/cc3200/boards/cc3200_af.csv b/ports/cc3200/boards/cc3200_af.csv
similarity index 100%
rename from cc3200/boards/cc3200_af.csv
rename to ports/cc3200/boards/cc3200_af.csv
diff --git a/cc3200/boards/cc3200_prefix.c b/ports/cc3200/boards/cc3200_prefix.c
similarity index 100%
rename from cc3200/boards/cc3200_prefix.c
rename to ports/cc3200/boards/cc3200_prefix.c
diff --git a/cc3200/boards/make-pins.py b/ports/cc3200/boards/make-pins.py
similarity index 100%
rename from cc3200/boards/make-pins.py
rename to ports/cc3200/boards/make-pins.py
diff --git a/cc3200/bootmgr/bootgen.sh b/ports/cc3200/bootmgr/bootgen.sh
similarity index 100%
rename from cc3200/bootmgr/bootgen.sh
rename to ports/cc3200/bootmgr/bootgen.sh
diff --git a/cc3200/bootmgr/bootloader.mk b/ports/cc3200/bootmgr/bootloader.mk
similarity index 98%
rename from cc3200/bootmgr/bootloader.mk
rename to ports/cc3200/bootmgr/bootloader.mk
index b8aa9082c9..44f1b7f42d 100644
--- a/cc3200/bootmgr/bootloader.mk
+++ b/ports/cc3200/bootmgr/bootloader.mk
@@ -98,7 +98,7 @@ $(BUILD)/misc/%.o: CFLAGS += -Os
 $(BUILD)/simplelink/%.o: CFLAGS += -Os
 $(BUILD)/drivers/cc3100/%.o: CFLAGS += -Os
 $(BUILD)/py/%.o: CFLAGS += -Os
-$(BUILD)/stmhal/%.o: CFLAGS += -Os
+$(BUILD)/ports/stm32/%.o: CFLAGS += -Os
 else
 $(error Invalid BTYPE specified)
 endif
diff --git a/cc3200/bootmgr/bootmgr.h b/ports/cc3200/bootmgr/bootmgr.h
similarity index 100%
rename from cc3200/bootmgr/bootmgr.h
rename to ports/cc3200/bootmgr/bootmgr.h
diff --git a/cc3200/bootmgr/bootmgr.lds b/ports/cc3200/bootmgr/bootmgr.lds
similarity index 100%
rename from cc3200/bootmgr/bootmgr.lds
rename to ports/cc3200/bootmgr/bootmgr.lds
diff --git a/cc3200/bootmgr/flc.h b/ports/cc3200/bootmgr/flc.h
similarity index 100%
rename from cc3200/bootmgr/flc.h
rename to ports/cc3200/bootmgr/flc.h
diff --git a/cc3200/bootmgr/main.c b/ports/cc3200/bootmgr/main.c
similarity index 100%
rename from cc3200/bootmgr/main.c
rename to ports/cc3200/bootmgr/main.c
diff --git a/cc3200/bootmgr/relocator/relocator.bin b/ports/cc3200/bootmgr/relocator/relocator.bin
similarity index 100%
rename from cc3200/bootmgr/relocator/relocator.bin
rename to ports/cc3200/bootmgr/relocator/relocator.bin
diff --git a/cc3200/bootmgr/runapp.s b/ports/cc3200/bootmgr/runapp.s
similarity index 100%
rename from cc3200/bootmgr/runapp.s
rename to ports/cc3200/bootmgr/runapp.s
diff --git a/cc3200/bootmgr/sl/user.h b/ports/cc3200/bootmgr/sl/user.h
similarity index 100%
rename from cc3200/bootmgr/sl/user.h
rename to ports/cc3200/bootmgr/sl/user.h
diff --git a/cc3200/fatfs/src/drivers/sd_diskio.c b/ports/cc3200/fatfs/src/drivers/sd_diskio.c
similarity index 100%
rename from cc3200/fatfs/src/drivers/sd_diskio.c
rename to ports/cc3200/fatfs/src/drivers/sd_diskio.c
diff --git a/cc3200/fatfs/src/drivers/sd_diskio.h b/ports/cc3200/fatfs/src/drivers/sd_diskio.h
similarity index 100%
rename from cc3200/fatfs/src/drivers/sd_diskio.h
rename to ports/cc3200/fatfs/src/drivers/sd_diskio.h
diff --git a/cc3200/fatfs/src/drivers/sflash_diskio.c b/ports/cc3200/fatfs/src/drivers/sflash_diskio.c
similarity index 100%
rename from cc3200/fatfs/src/drivers/sflash_diskio.c
rename to ports/cc3200/fatfs/src/drivers/sflash_diskio.c
diff --git a/cc3200/fatfs/src/drivers/sflash_diskio.h b/ports/cc3200/fatfs/src/drivers/sflash_diskio.h
similarity index 100%
rename from cc3200/fatfs/src/drivers/sflash_diskio.h
rename to ports/cc3200/fatfs/src/drivers/sflash_diskio.h
diff --git a/cc3200/fatfs/src/drivers/stdcmd.h b/ports/cc3200/fatfs/src/drivers/stdcmd.h
similarity index 100%
rename from cc3200/fatfs/src/drivers/stdcmd.h
rename to ports/cc3200/fatfs/src/drivers/stdcmd.h
diff --git a/cc3200/fatfs_port.c b/ports/cc3200/fatfs_port.c
similarity index 100%
rename from cc3200/fatfs_port.c
rename to ports/cc3200/fatfs_port.c
diff --git a/cc3200/ftp/ftp.c b/ports/cc3200/ftp/ftp.c
similarity index 99%
rename from cc3200/ftp/ftp.c
rename to ports/cc3200/ftp/ftp.c
index 5461f9180a..ee80e51f52 100644
--- a/cc3200/ftp/ftp.c
+++ b/ports/cc3200/ftp/ftp.c
@@ -27,8 +27,7 @@
 #include <stdint.h>
 #include <stdio.h>
 
-#include "py/mpstate.h"
-#include "py/obj.h"
+#include "py/runtime.h"
 #include "lib/timeutils/timeutils.h"
 #include "lib/oofatfs/ff.h"
 #include "extmod/vfs.h"
diff --git a/cc3200/ftp/ftp.h b/ports/cc3200/ftp/ftp.h
similarity index 100%
rename from cc3200/ftp/ftp.h
rename to ports/cc3200/ftp/ftp.h
diff --git a/cc3200/ftp/updater.c b/ports/cc3200/ftp/updater.c
similarity index 100%
rename from cc3200/ftp/updater.c
rename to ports/cc3200/ftp/updater.c
diff --git a/cc3200/ftp/updater.h b/ports/cc3200/ftp/updater.h
similarity index 100%
rename from cc3200/ftp/updater.h
rename to ports/cc3200/ftp/updater.h
diff --git a/cc3200/hal/adc.c b/ports/cc3200/hal/adc.c
similarity index 100%
rename from cc3200/hal/adc.c
rename to ports/cc3200/hal/adc.c
diff --git a/cc3200/hal/adc.h b/ports/cc3200/hal/adc.h
similarity index 100%
rename from cc3200/hal/adc.h
rename to ports/cc3200/hal/adc.h
diff --git a/cc3200/hal/aes.c b/ports/cc3200/hal/aes.c
similarity index 100%
rename from cc3200/hal/aes.c
rename to ports/cc3200/hal/aes.c
diff --git a/cc3200/hal/aes.h b/ports/cc3200/hal/aes.h
similarity index 100%
rename from cc3200/hal/aes.h
rename to ports/cc3200/hal/aes.h
diff --git a/cc3200/hal/cc3200_asm.h b/ports/cc3200/hal/cc3200_asm.h
similarity index 100%
rename from cc3200/hal/cc3200_asm.h
rename to ports/cc3200/hal/cc3200_asm.h
diff --git a/cc3200/hal/cc3200_hal.c b/ports/cc3200/hal/cc3200_hal.c
similarity index 98%
rename from cc3200/hal/cc3200_hal.c
rename to ports/cc3200/hal/cc3200_hal.c
index b4848e99e8..0285d05856 100644
--- a/cc3200/hal/cc3200_hal.c
+++ b/ports/cc3200/hal/cc3200_hal.c
@@ -33,7 +33,6 @@
 #include <string.h>
 
 
-#include "py/mpstate.h"
 #include "py/mphal.h"
 #include "py/runtime.h"
 #include "py/objstr.h"
@@ -143,10 +142,6 @@ void mp_hal_delay_ms(mp_uint_t delay) {
     }
 }
 
-void mp_hal_set_interrupt_char (int c) {
-    mpexception_set_interrupt_char (c);
-}
-
 void mp_hal_stdout_tx_str(const char *str) {
     mp_hal_stdout_tx_strn(str, strlen(str));
 }
diff --git a/cc3200/hal/cc3200_hal.h b/ports/cc3200/hal/cc3200_hal.h
similarity index 100%
rename from cc3200/hal/cc3200_hal.h
rename to ports/cc3200/hal/cc3200_hal.h
diff --git a/cc3200/hal/cpu.c b/ports/cc3200/hal/cpu.c
similarity index 100%
rename from cc3200/hal/cpu.c
rename to ports/cc3200/hal/cpu.c
diff --git a/cc3200/hal/cpu.h b/ports/cc3200/hal/cpu.h
similarity index 100%
rename from cc3200/hal/cpu.h
rename to ports/cc3200/hal/cpu.h
diff --git a/cc3200/hal/crc.c b/ports/cc3200/hal/crc.c
similarity index 100%
rename from cc3200/hal/crc.c
rename to ports/cc3200/hal/crc.c
diff --git a/cc3200/hal/crc.h b/ports/cc3200/hal/crc.h
similarity index 100%
rename from cc3200/hal/crc.h
rename to ports/cc3200/hal/crc.h
diff --git a/cc3200/hal/debug.h b/ports/cc3200/hal/debug.h
similarity index 100%
rename from cc3200/hal/debug.h
rename to ports/cc3200/hal/debug.h
diff --git a/cc3200/hal/des.c b/ports/cc3200/hal/des.c
similarity index 100%
rename from cc3200/hal/des.c
rename to ports/cc3200/hal/des.c
diff --git a/cc3200/hal/des.h b/ports/cc3200/hal/des.h
similarity index 100%
rename from cc3200/hal/des.h
rename to ports/cc3200/hal/des.h
diff --git a/cc3200/hal/fault_registers.h b/ports/cc3200/hal/fault_registers.h
similarity index 100%
rename from cc3200/hal/fault_registers.h
rename to ports/cc3200/hal/fault_registers.h
diff --git a/cc3200/hal/gpio.c b/ports/cc3200/hal/gpio.c
similarity index 100%
rename from cc3200/hal/gpio.c
rename to ports/cc3200/hal/gpio.c
diff --git a/cc3200/hal/gpio.h b/ports/cc3200/hal/gpio.h
similarity index 100%
rename from cc3200/hal/gpio.h
rename to ports/cc3200/hal/gpio.h
diff --git a/cc3200/hal/i2c.c b/ports/cc3200/hal/i2c.c
similarity index 100%
rename from cc3200/hal/i2c.c
rename to ports/cc3200/hal/i2c.c
diff --git a/cc3200/hal/i2c.h b/ports/cc3200/hal/i2c.h
similarity index 100%
rename from cc3200/hal/i2c.h
rename to ports/cc3200/hal/i2c.h
diff --git a/cc3200/hal/i2s.c b/ports/cc3200/hal/i2s.c
similarity index 100%
rename from cc3200/hal/i2s.c
rename to ports/cc3200/hal/i2s.c
diff --git a/cc3200/hal/i2s.h b/ports/cc3200/hal/i2s.h
similarity index 100%
rename from cc3200/hal/i2s.h
rename to ports/cc3200/hal/i2s.h
diff --git a/cc3200/hal/inc/asmdefs.h b/ports/cc3200/hal/inc/asmdefs.h
similarity index 100%
rename from cc3200/hal/inc/asmdefs.h
rename to ports/cc3200/hal/inc/asmdefs.h
diff --git a/cc3200/hal/inc/hw_adc.h b/ports/cc3200/hal/inc/hw_adc.h
similarity index 100%
rename from cc3200/hal/inc/hw_adc.h
rename to ports/cc3200/hal/inc/hw_adc.h
diff --git a/cc3200/hal/inc/hw_aes.h b/ports/cc3200/hal/inc/hw_aes.h
similarity index 100%
rename from cc3200/hal/inc/hw_aes.h
rename to ports/cc3200/hal/inc/hw_aes.h
diff --git a/cc3200/hal/inc/hw_apps_config.h b/ports/cc3200/hal/inc/hw_apps_config.h
similarity index 100%
rename from cc3200/hal/inc/hw_apps_config.h
rename to ports/cc3200/hal/inc/hw_apps_config.h
diff --git a/cc3200/hal/inc/hw_apps_rcm.h b/ports/cc3200/hal/inc/hw_apps_rcm.h
similarity index 100%
rename from cc3200/hal/inc/hw_apps_rcm.h
rename to ports/cc3200/hal/inc/hw_apps_rcm.h
diff --git a/cc3200/hal/inc/hw_camera.h b/ports/cc3200/hal/inc/hw_camera.h
similarity index 100%
rename from cc3200/hal/inc/hw_camera.h
rename to ports/cc3200/hal/inc/hw_camera.h
diff --git a/cc3200/hal/inc/hw_common_reg.h b/ports/cc3200/hal/inc/hw_common_reg.h
similarity index 100%
rename from cc3200/hal/inc/hw_common_reg.h
rename to ports/cc3200/hal/inc/hw_common_reg.h
diff --git a/cc3200/hal/inc/hw_des.h b/ports/cc3200/hal/inc/hw_des.h
similarity index 100%
rename from cc3200/hal/inc/hw_des.h
rename to ports/cc3200/hal/inc/hw_des.h
diff --git a/cc3200/hal/inc/hw_dthe.h b/ports/cc3200/hal/inc/hw_dthe.h
similarity index 100%
rename from cc3200/hal/inc/hw_dthe.h
rename to ports/cc3200/hal/inc/hw_dthe.h
diff --git a/cc3200/hal/inc/hw_flash_ctrl.h b/ports/cc3200/hal/inc/hw_flash_ctrl.h
similarity index 100%
rename from cc3200/hal/inc/hw_flash_ctrl.h
rename to ports/cc3200/hal/inc/hw_flash_ctrl.h
diff --git a/cc3200/hal/inc/hw_gpio.h b/ports/cc3200/hal/inc/hw_gpio.h
similarity index 100%
rename from cc3200/hal/inc/hw_gpio.h
rename to ports/cc3200/hal/inc/hw_gpio.h
diff --git a/cc3200/hal/inc/hw_gprcm.h b/ports/cc3200/hal/inc/hw_gprcm.h
similarity index 100%
rename from cc3200/hal/inc/hw_gprcm.h
rename to ports/cc3200/hal/inc/hw_gprcm.h
diff --git a/cc3200/hal/inc/hw_hib1p2.h b/ports/cc3200/hal/inc/hw_hib1p2.h
similarity index 100%
rename from cc3200/hal/inc/hw_hib1p2.h
rename to ports/cc3200/hal/inc/hw_hib1p2.h
diff --git a/cc3200/hal/inc/hw_hib3p3.h b/ports/cc3200/hal/inc/hw_hib3p3.h
similarity index 100%
rename from cc3200/hal/inc/hw_hib3p3.h
rename to ports/cc3200/hal/inc/hw_hib3p3.h
diff --git a/cc3200/hal/inc/hw_i2c.h b/ports/cc3200/hal/inc/hw_i2c.h
similarity index 100%
rename from cc3200/hal/inc/hw_i2c.h
rename to ports/cc3200/hal/inc/hw_i2c.h
diff --git a/cc3200/hal/inc/hw_ints.h b/ports/cc3200/hal/inc/hw_ints.h
similarity index 100%
rename from cc3200/hal/inc/hw_ints.h
rename to ports/cc3200/hal/inc/hw_ints.h
diff --git a/cc3200/hal/inc/hw_mcasp.h b/ports/cc3200/hal/inc/hw_mcasp.h
similarity index 100%
rename from cc3200/hal/inc/hw_mcasp.h
rename to ports/cc3200/hal/inc/hw_mcasp.h
diff --git a/cc3200/hal/inc/hw_mcspi.h b/ports/cc3200/hal/inc/hw_mcspi.h
similarity index 100%
rename from cc3200/hal/inc/hw_mcspi.h
rename to ports/cc3200/hal/inc/hw_mcspi.h
diff --git a/cc3200/hal/inc/hw_memmap.h b/ports/cc3200/hal/inc/hw_memmap.h
similarity index 100%
rename from cc3200/hal/inc/hw_memmap.h
rename to ports/cc3200/hal/inc/hw_memmap.h
diff --git a/cc3200/hal/inc/hw_mmchs.h b/ports/cc3200/hal/inc/hw_mmchs.h
similarity index 100%
rename from cc3200/hal/inc/hw_mmchs.h
rename to ports/cc3200/hal/inc/hw_mmchs.h
diff --git a/cc3200/hal/inc/hw_nvic.h b/ports/cc3200/hal/inc/hw_nvic.h
similarity index 100%
rename from cc3200/hal/inc/hw_nvic.h
rename to ports/cc3200/hal/inc/hw_nvic.h
diff --git a/cc3200/hal/inc/hw_ocp_shared.h b/ports/cc3200/hal/inc/hw_ocp_shared.h
similarity index 100%
rename from cc3200/hal/inc/hw_ocp_shared.h
rename to ports/cc3200/hal/inc/hw_ocp_shared.h
diff --git a/cc3200/hal/inc/hw_shamd5.h b/ports/cc3200/hal/inc/hw_shamd5.h
similarity index 100%
rename from cc3200/hal/inc/hw_shamd5.h
rename to ports/cc3200/hal/inc/hw_shamd5.h
diff --git a/cc3200/hal/inc/hw_stack_die_ctrl.h b/ports/cc3200/hal/inc/hw_stack_die_ctrl.h
similarity index 100%
rename from cc3200/hal/inc/hw_stack_die_ctrl.h
rename to ports/cc3200/hal/inc/hw_stack_die_ctrl.h
diff --git a/cc3200/hal/inc/hw_timer.h b/ports/cc3200/hal/inc/hw_timer.h
similarity index 100%
rename from cc3200/hal/inc/hw_timer.h
rename to ports/cc3200/hal/inc/hw_timer.h
diff --git a/cc3200/hal/inc/hw_types.h b/ports/cc3200/hal/inc/hw_types.h
similarity index 100%
rename from cc3200/hal/inc/hw_types.h
rename to ports/cc3200/hal/inc/hw_types.h
diff --git a/cc3200/hal/inc/hw_uart.h b/ports/cc3200/hal/inc/hw_uart.h
similarity index 100%
rename from cc3200/hal/inc/hw_uart.h
rename to ports/cc3200/hal/inc/hw_uart.h
diff --git a/cc3200/hal/inc/hw_udma.h b/ports/cc3200/hal/inc/hw_udma.h
similarity index 100%
rename from cc3200/hal/inc/hw_udma.h
rename to ports/cc3200/hal/inc/hw_udma.h
diff --git a/cc3200/hal/inc/hw_wdt.h b/ports/cc3200/hal/inc/hw_wdt.h
similarity index 100%
rename from cc3200/hal/inc/hw_wdt.h
rename to ports/cc3200/hal/inc/hw_wdt.h
diff --git a/cc3200/hal/interrupt.c b/ports/cc3200/hal/interrupt.c
similarity index 100%
rename from cc3200/hal/interrupt.c
rename to ports/cc3200/hal/interrupt.c
diff --git a/cc3200/hal/interrupt.h b/ports/cc3200/hal/interrupt.h
similarity index 100%
rename from cc3200/hal/interrupt.h
rename to ports/cc3200/hal/interrupt.h
diff --git a/cc3200/hal/pin.c b/ports/cc3200/hal/pin.c
similarity index 100%
rename from cc3200/hal/pin.c
rename to ports/cc3200/hal/pin.c
diff --git a/cc3200/hal/pin.h b/ports/cc3200/hal/pin.h
similarity index 100%
rename from cc3200/hal/pin.h
rename to ports/cc3200/hal/pin.h
diff --git a/cc3200/hal/prcm.c b/ports/cc3200/hal/prcm.c
similarity index 100%
rename from cc3200/hal/prcm.c
rename to ports/cc3200/hal/prcm.c
diff --git a/cc3200/hal/prcm.h b/ports/cc3200/hal/prcm.h
similarity index 100%
rename from cc3200/hal/prcm.h
rename to ports/cc3200/hal/prcm.h
diff --git a/cc3200/hal/rom.h b/ports/cc3200/hal/rom.h
similarity index 100%
rename from cc3200/hal/rom.h
rename to ports/cc3200/hal/rom.h
diff --git a/cc3200/hal/rom_map.h b/ports/cc3200/hal/rom_map.h
similarity index 100%
rename from cc3200/hal/rom_map.h
rename to ports/cc3200/hal/rom_map.h
diff --git a/cc3200/hal/rom_patch.h b/ports/cc3200/hal/rom_patch.h
similarity index 100%
rename from cc3200/hal/rom_patch.h
rename to ports/cc3200/hal/rom_patch.h
diff --git a/cc3200/hal/sdhost.c b/ports/cc3200/hal/sdhost.c
similarity index 100%
rename from cc3200/hal/sdhost.c
rename to ports/cc3200/hal/sdhost.c
diff --git a/cc3200/hal/sdhost.h b/ports/cc3200/hal/sdhost.h
similarity index 100%
rename from cc3200/hal/sdhost.h
rename to ports/cc3200/hal/sdhost.h
diff --git a/cc3200/hal/shamd5.c b/ports/cc3200/hal/shamd5.c
similarity index 100%
rename from cc3200/hal/shamd5.c
rename to ports/cc3200/hal/shamd5.c
diff --git a/cc3200/hal/shamd5.h b/ports/cc3200/hal/shamd5.h
similarity index 100%
rename from cc3200/hal/shamd5.h
rename to ports/cc3200/hal/shamd5.h
diff --git a/cc3200/hal/spi.c b/ports/cc3200/hal/spi.c
similarity index 100%
rename from cc3200/hal/spi.c
rename to ports/cc3200/hal/spi.c
diff --git a/cc3200/hal/spi.h b/ports/cc3200/hal/spi.h
similarity index 100%
rename from cc3200/hal/spi.h
rename to ports/cc3200/hal/spi.h
diff --git a/cc3200/hal/startup_gcc.c b/ports/cc3200/hal/startup_gcc.c
similarity index 100%
rename from cc3200/hal/startup_gcc.c
rename to ports/cc3200/hal/startup_gcc.c
diff --git a/cc3200/hal/systick.c b/ports/cc3200/hal/systick.c
similarity index 100%
rename from cc3200/hal/systick.c
rename to ports/cc3200/hal/systick.c
diff --git a/cc3200/hal/systick.h b/ports/cc3200/hal/systick.h
similarity index 100%
rename from cc3200/hal/systick.h
rename to ports/cc3200/hal/systick.h
diff --git a/cc3200/hal/timer.c b/ports/cc3200/hal/timer.c
similarity index 100%
rename from cc3200/hal/timer.c
rename to ports/cc3200/hal/timer.c
diff --git a/cc3200/hal/timer.h b/ports/cc3200/hal/timer.h
similarity index 100%
rename from cc3200/hal/timer.h
rename to ports/cc3200/hal/timer.h
diff --git a/cc3200/hal/uart.c b/ports/cc3200/hal/uart.c
similarity index 100%
rename from cc3200/hal/uart.c
rename to ports/cc3200/hal/uart.c
diff --git a/cc3200/hal/uart.h b/ports/cc3200/hal/uart.h
similarity index 100%
rename from cc3200/hal/uart.h
rename to ports/cc3200/hal/uart.h
diff --git a/cc3200/hal/utils.c b/ports/cc3200/hal/utils.c
similarity index 100%
rename from cc3200/hal/utils.c
rename to ports/cc3200/hal/utils.c
diff --git a/cc3200/hal/utils.h b/ports/cc3200/hal/utils.h
similarity index 100%
rename from cc3200/hal/utils.h
rename to ports/cc3200/hal/utils.h
diff --git a/cc3200/hal/wdt.c b/ports/cc3200/hal/wdt.c
similarity index 100%
rename from cc3200/hal/wdt.c
rename to ports/cc3200/hal/wdt.c
diff --git a/cc3200/hal/wdt.h b/ports/cc3200/hal/wdt.h
similarity index 100%
rename from cc3200/hal/wdt.h
rename to ports/cc3200/hal/wdt.h
diff --git a/cc3200/main.c b/ports/cc3200/main.c
similarity index 100%
rename from cc3200/main.c
rename to ports/cc3200/main.c
diff --git a/cc3200/misc/FreeRTOSHooks.c b/ports/cc3200/misc/FreeRTOSHooks.c
similarity index 100%
rename from cc3200/misc/FreeRTOSHooks.c
rename to ports/cc3200/misc/FreeRTOSHooks.c
diff --git a/cc3200/misc/antenna.c b/ports/cc3200/misc/antenna.c
similarity index 100%
rename from cc3200/misc/antenna.c
rename to ports/cc3200/misc/antenna.c
diff --git a/cc3200/misc/antenna.h b/ports/cc3200/misc/antenna.h
similarity index 100%
rename from cc3200/misc/antenna.h
rename to ports/cc3200/misc/antenna.h
diff --git a/cc3200/misc/help.c b/ports/cc3200/misc/help.c
similarity index 96%
rename from cc3200/misc/help.c
rename to ports/cc3200/misc/help.c
index 739303e193..ea0c9501db 100644
--- a/cc3200/misc/help.c
+++ b/ports/cc3200/misc/help.c
@@ -27,6 +27,6 @@
 
 #include "py/builtin.h"
 
-const char *cc3200_help_text = "Welcome to MicroPython!\n"
+const char cc3200_help_text[] = "Welcome to MicroPython!\n"
                                 "For online help please visit http://micropython.org/help/.\n"
                                 "For further help on a specific object, type help(obj)\n";
diff --git a/cc3200/misc/mperror.c b/ports/cc3200/misc/mperror.c
similarity index 100%
rename from cc3200/misc/mperror.c
rename to ports/cc3200/misc/mperror.c
diff --git a/cc3200/misc/mperror.h b/ports/cc3200/misc/mperror.h
similarity index 100%
rename from cc3200/misc/mperror.h
rename to ports/cc3200/misc/mperror.h
diff --git a/ports/cc3200/misc/mpexception.c b/ports/cc3200/misc/mpexception.c
new file mode 100644
index 0000000000..72d4a155fa
--- /dev/null
+++ b/ports/cc3200/misc/mpexception.c
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <stdint.h>
+#include <string.h>
+
+#include "mpexception.h"
+
+
+/******************************************************************************
+DECLARE EXPORTED DATA
+ ******************************************************************************/
+const char mpexception_value_invalid_arguments[]    = "invalid argument(s) value";
+const char mpexception_num_type_invalid_arguments[] = "invalid argument(s) num/type";
+const char mpexception_uncaught[]                   = "uncaught exception";
diff --git a/cc3200/misc/mpexception.h b/ports/cc3200/misc/mpexception.h
similarity index 87%
rename from cc3200/misc/mpexception.h
rename to ports/cc3200/misc/mpexception.h
index 88134857c1..e84a1edb21 100644
--- a/cc3200/misc/mpexception.h
+++ b/ports/cc3200/misc/mpexception.h
@@ -31,12 +31,4 @@ extern const char mpexception_value_invalid_arguments[];
 extern const char mpexception_num_type_invalid_arguments[];
 extern const char mpexception_uncaught[];
 
-extern int        user_interrupt_char;
-
-
-extern void mpexception_init0 (void);
-extern void mpexception_set_interrupt_char (int c);
-extern void mpexception_nlr_jump (void *o);
-extern void mpexception_keyboard_nlr_jump (void);
-
 #endif // MICROPY_INCLUDED_CC3200_MISC_MPEXCEPTION_H
diff --git a/cc3200/misc/mpirq.c b/ports/cc3200/misc/mpirq.c
similarity index 98%
rename from cc3200/misc/mpirq.c
rename to ports/cc3200/misc/mpirq.c
index d05f9181b8..d54e7465b1 100644
--- a/cc3200/misc/mpirq.c
+++ b/ports/cc3200/misc/mpirq.c
@@ -145,7 +145,7 @@ void mp_irq_handler (mp_obj_t self_in) {
 /******************************************************************************/
 // MicroPython bindings
 
-STATIC mp_obj_t mp_irq_init (mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t mp_irq_init(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     mp_irq_obj_t *self = pos_args[0];
     // this is a bit of a hack, but it let us reuse the callback_create method from our parent
     ((mp_obj_t *)pos_args)[0] = self->parent;
diff --git a/cc3200/misc/mpirq.h b/ports/cc3200/misc/mpirq.h
similarity index 96%
rename from cc3200/misc/mpirq.h
rename to ports/cc3200/misc/mpirq.h
index 35ce66e2da..223a34cae2 100644
--- a/cc3200/misc/mpirq.h
+++ b/ports/cc3200/misc/mpirq.h
@@ -34,7 +34,7 @@
 /******************************************************************************
  DEFINE TYPES
  ******************************************************************************/
-typedef mp_obj_t (*mp_irq_init_t) (mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args);
+typedef mp_obj_t (*mp_irq_init_t) (size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args);
 typedef void (*mp_irq_void_method_t) (mp_obj_t self);
 typedef int (*mp_irq_int_method_t)  (mp_obj_t self);
 
diff --git a/cc3200/mods/modmachine.c b/ports/cc3200/mods/modmachine.c
similarity index 99%
rename from cc3200/mods/modmachine.c
rename to ports/cc3200/mods/modmachine.c
index fb0fe7f2c7..6051497e30 100644
--- a/cc3200/mods/modmachine.c
+++ b/ports/cc3200/mods/modmachine.c
@@ -27,7 +27,6 @@
 
 #include <stdint.h>
 
-#include "py/mpstate.h"
 #include "py/runtime.h"
 #include "py/mphal.h"
 #include "irq.h"
diff --git a/cc3200/mods/modnetwork.c b/ports/cc3200/mods/modnetwork.c
similarity index 96%
rename from cc3200/mods/modnetwork.c
rename to ports/cc3200/mods/modnetwork.c
index 221b664da1..37dffe731f 100644
--- a/cc3200/mods/modnetwork.c
+++ b/ports/cc3200/mods/modnetwork.c
@@ -25,9 +25,6 @@
  * THE SOFTWARE.
  */
 
-#include "py/mpstate.h"
-#include "py/obj.h"
-#include "py/nlr.h"
 #include "py/runtime.h"
 #include "py/mperrno.h"
 #include "py/mphal.h"
@@ -112,7 +109,7 @@ STATIC mp_obj_t network_server_make_new(const mp_obj_type_t *type, size_t n_args
     return (mp_obj_t)self;
 }
 
-STATIC mp_obj_t network_server_init(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t network_server_init(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     // parse args
     mp_arg_val_t args[MP_ARRAY_SIZE(network_server_args) - 1];
     mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_ARRAY_SIZE(args), &network_server_args[1], args);
@@ -121,7 +118,7 @@ STATIC mp_obj_t network_server_init(mp_uint_t n_args, const mp_obj_t *pos_args,
 STATIC MP_DEFINE_CONST_FUN_OBJ_KW(network_server_init_obj, 1, network_server_init);
 
 // timeout value given in seconds
-STATIC mp_obj_t network_server_timeout(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t network_server_timeout(size_t n_args, const mp_obj_t *args) {
     if (n_args > 1) {
         uint32_t timeout = mp_obj_get_int(args[1]);
         servers_set_timeout(timeout * 1000);
diff --git a/cc3200/mods/modnetwork.h b/ports/cc3200/mods/modnetwork.h
similarity index 100%
rename from cc3200/mods/modnetwork.h
rename to ports/cc3200/mods/modnetwork.h
diff --git a/cc3200/mods/modubinascii.c b/ports/cc3200/mods/modubinascii.c
similarity index 98%
rename from cc3200/mods/modubinascii.c
rename to ports/cc3200/mods/modubinascii.c
index 7f51a8f3d1..6b020ab393 100644
--- a/cc3200/mods/modubinascii.c
+++ b/ports/cc3200/mods/modubinascii.c
@@ -25,8 +25,6 @@
  * THE SOFTWARE.
  */
 
-#include "py/mpconfig.h"
-#include "py/nlr.h"
 #include "py/runtime.h"
 #include "py/binary.h"
 #include "extmod/modubinascii.h"
diff --git a/cc3200/mods/modubinascii.h b/ports/cc3200/mods/modubinascii.h
similarity index 100%
rename from cc3200/mods/modubinascii.h
rename to ports/cc3200/mods/modubinascii.h
diff --git a/cc3200/mods/moduhashlib.c b/ports/cc3200/mods/moduhashlib.c
similarity index 99%
rename from cc3200/mods/moduhashlib.c
rename to ports/cc3200/mods/moduhashlib.c
index bec88d7ca9..96f5149273 100644
--- a/cc3200/mods/moduhashlib.c
+++ b/ports/cc3200/mods/moduhashlib.c
@@ -30,7 +30,6 @@
 
 #include "py/mpconfig.h"
 #include MICROPY_HAL_H
-#include "py/nlr.h"
 #include "py/runtime.h"
 #include "inc/hw_types.h"
 #include "inc/hw_ints.h"
diff --git a/cc3200/mods/moduos.c b/ports/cc3200/mods/moduos.c
similarity index 99%
rename from cc3200/mods/moduos.c
rename to ports/cc3200/mods/moduos.c
index ba8fd86a6b..7d99c8e80d 100644
--- a/cc3200/mods/moduos.c
+++ b/ports/cc3200/mods/moduos.c
@@ -28,8 +28,6 @@
 #include <stdint.h>
 #include <string.h>
 
-#include "py/mpstate.h"
-#include "py/nlr.h"
 #include "py/objtuple.h"
 #include "py/objstr.h"
 #include "py/runtime.h"
diff --git a/cc3200/mods/moduos.h b/ports/cc3200/mods/moduos.h
similarity index 100%
rename from cc3200/mods/moduos.h
rename to ports/cc3200/mods/moduos.h
diff --git a/cc3200/mods/modusocket.c b/ports/cc3200/mods/modusocket.c
similarity index 99%
rename from cc3200/mods/modusocket.c
rename to ports/cc3200/mods/modusocket.c
index 1e3e1eafbf..f587e765ae 100644
--- a/cc3200/mods/modusocket.c
+++ b/ports/cc3200/mods/modusocket.c
@@ -492,7 +492,7 @@ STATIC mp_obj_t socket_bind(mp_obj_t self_in, mp_obj_t addr_in) {
 STATIC MP_DEFINE_CONST_FUN_OBJ_2(socket_bind_obj, socket_bind);
 
 // method socket.listen([backlog])
-STATIC mp_obj_t socket_listen(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t socket_listen(size_t n_args, const mp_obj_t *args) {
     mod_network_socket_obj_t *self = args[0];
 
     int32_t backlog = 0;
@@ -639,7 +639,7 @@ STATIC mp_obj_t socket_recvfrom(mp_obj_t self_in, mp_obj_t len_in) {
 STATIC MP_DEFINE_CONST_FUN_OBJ_2(socket_recvfrom_obj, socket_recvfrom);
 
 // method socket.setsockopt(level, optname, value)
-STATIC mp_obj_t socket_setsockopt(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t socket_setsockopt(size_t n_args, const mp_obj_t *args) {
     mod_network_socket_obj_t *self = args[0];
 
     mp_int_t level = mp_obj_get_int(args[1]);
@@ -697,7 +697,7 @@ STATIC mp_obj_t socket_setblocking(mp_obj_t self_in, mp_obj_t blocking) {
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_2(socket_setblocking_obj, socket_setblocking);
 
-STATIC mp_obj_t socket_makefile(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t socket_makefile(size_t n_args, const mp_obj_t *args) {
     (void)n_args;
     return args[0];
 }
diff --git a/cc3200/mods/modusocket.h b/ports/cc3200/mods/modusocket.h
similarity index 100%
rename from cc3200/mods/modusocket.h
rename to ports/cc3200/mods/modusocket.h
diff --git a/cc3200/mods/modussl.c b/ports/cc3200/mods/modussl.c
similarity index 98%
rename from cc3200/mods/modussl.c
rename to ports/cc3200/mods/modussl.c
index 0c15e120d0..3211570499 100644
--- a/cc3200/mods/modussl.c
+++ b/ports/cc3200/mods/modussl.c
@@ -70,7 +70,7 @@ STATIC const mp_obj_type_t ssl_socket_type = {
     .locals_dict = (mp_obj_t)&socket_locals_dict,
 };
 
-STATIC mp_obj_t mod_ssl_wrap_socket(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t mod_ssl_wrap_socket(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     STATIC const mp_arg_t allowed_args[] = {
         { MP_QSTR_sock,             MP_ARG_REQUIRED | MP_ARG_OBJ,  },
         { MP_QSTR_keyfile,          MP_ARG_KW_ONLY  | MP_ARG_OBJ,  {.u_obj = mp_const_none} },
diff --git a/cc3200/mods/modutime.c b/ports/cc3200/mods/modutime.c
similarity index 98%
rename from cc3200/mods/modutime.c
rename to ports/cc3200/mods/modutime.c
index cd36ef6040..13750f96b5 100644
--- a/cc3200/mods/modutime.c
+++ b/ports/cc3200/mods/modutime.c
@@ -65,7 +65,7 @@
 /// second  is 0-59
 /// weekday is 0-6 for Mon-Sun.
 /// yearday is 1-366
-STATIC mp_obj_t time_localtime(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t time_localtime(size_t n_args, const mp_obj_t *args) {
     if (n_args == 0 || args[0] == mp_const_none) {
         timeutils_struct_time_t tm;
 
diff --git a/cc3200/mods/modwipy.c b/ports/cc3200/mods/modwipy.c
similarity index 92%
rename from cc3200/mods/modwipy.c
rename to ports/cc3200/mods/modwipy.c
index c1b326fa2f..0f16e73018 100644
--- a/cc3200/mods/modwipy.c
+++ b/ports/cc3200/mods/modwipy.c
@@ -7,7 +7,7 @@
 /******************************************************************************/
 // MicroPython bindings
 
-STATIC mp_obj_t mod_wipy_heartbeat (mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t mod_wipy_heartbeat(size_t n_args, const mp_obj_t *args) {
     if (n_args) {
         mperror_enable_heartbeat (mp_obj_is_true(args[0]));
         return mp_const_none;
diff --git a/cc3200/mods/modwlan.c b/ports/cc3200/mods/modwlan.c
similarity index 98%
rename from cc3200/mods/modwlan.c
rename to ports/cc3200/mods/modwlan.c
index ac27dbb166..005334a796 100644
--- a/cc3200/mods/modwlan.c
+++ b/ports/cc3200/mods/modwlan.c
@@ -846,7 +846,7 @@ STATIC mp_obj_t wlan_make_new(const mp_obj_type_t *type, size_t n_args, size_t n
     return (mp_obj_t)self;
 }
 
-STATIC mp_obj_t wlan_init(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t wlan_init(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     // parse args
     mp_arg_val_t args[MP_ARRAY_SIZE(wlan_init_args) - 1];
     mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_ARRAY_SIZE(args), &wlan_init_args[1], args);
@@ -905,7 +905,7 @@ STATIC mp_obj_t wlan_scan(mp_obj_t self_in) {
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_1(wlan_scan_obj, wlan_scan);
 
-STATIC mp_obj_t wlan_connect(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t wlan_connect(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     STATIC const mp_arg_t allowed_args[] = {
         { MP_QSTR_ssid,     MP_ARG_REQUIRED | MP_ARG_OBJ, },
         { MP_QSTR_auth,                       MP_ARG_OBJ, {.u_obj = mp_const_none} },
@@ -982,7 +982,7 @@ STATIC mp_obj_t wlan_isconnected(mp_obj_t self_in) {
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_1(wlan_isconnected_obj, wlan_isconnected);
 
-STATIC mp_obj_t wlan_ifconfig (mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t wlan_ifconfig(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     STATIC const mp_arg_t wlan_ifconfig_args[] = {
         { MP_QSTR_id,               MP_ARG_INT,     {.u_int = 0} },
         { MP_QSTR_config,           MP_ARG_OBJ,     {.u_obj = MP_OBJ_NULL} },
@@ -1059,7 +1059,7 @@ STATIC mp_obj_t wlan_ifconfig (mp_uint_t n_args, const mp_obj_t *pos_args, mp_ma
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_KW(wlan_ifconfig_obj, 1, wlan_ifconfig);
 
-STATIC mp_obj_t wlan_mode (mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t wlan_mode(size_t n_args, const mp_obj_t *args) {
     wlan_obj_t *self = args[0];
     if (n_args == 1) {
         return mp_obj_new_int(self->mode);
@@ -1073,7 +1073,7 @@ STATIC mp_obj_t wlan_mode (mp_uint_t n_args, const mp_obj_t *args) {
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(wlan_mode_obj, 1, 2, wlan_mode);
 
-STATIC mp_obj_t wlan_ssid (mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t wlan_ssid(size_t n_args, const mp_obj_t *args) {
     wlan_obj_t *self = args[0];
     if (n_args == 1) {
         return mp_obj_new_str((const char *)self->ssid, strlen((const char *)self->ssid), false);
@@ -1088,7 +1088,7 @@ STATIC mp_obj_t wlan_ssid (mp_uint_t n_args, const mp_obj_t *args) {
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(wlan_ssid_obj, 1, 2, wlan_ssid);
 
-STATIC mp_obj_t wlan_auth (mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t wlan_auth(size_t n_args, const mp_obj_t *args) {
     wlan_obj_t *self = args[0];
     if (n_args == 1) {
         if (self->auth == SL_SEC_TYPE_OPEN) {
@@ -1118,7 +1118,7 @@ STATIC mp_obj_t wlan_auth (mp_uint_t n_args, const mp_obj_t *args) {
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(wlan_auth_obj, 1, 2, wlan_auth);
 
-STATIC mp_obj_t wlan_channel (mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t wlan_channel(size_t n_args, const mp_obj_t *args) {
     wlan_obj_t *self = args[0];
     if (n_args == 1) {
         return mp_obj_new_int(self->channel);
@@ -1132,7 +1132,7 @@ STATIC mp_obj_t wlan_channel (mp_uint_t n_args, const mp_obj_t *args) {
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(wlan_channel_obj, 1, 2, wlan_channel);
 
-STATIC mp_obj_t wlan_antenna (mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t wlan_antenna(size_t n_args, const mp_obj_t *args) {
     wlan_obj_t *self = args[0];
     if (n_args == 1) {
         return mp_obj_new_int(self->antenna);
@@ -1147,7 +1147,7 @@ STATIC mp_obj_t wlan_antenna (mp_uint_t n_args, const mp_obj_t *args) {
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(wlan_antenna_obj, 1, 2, wlan_antenna);
 
-STATIC mp_obj_t wlan_mac (mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t wlan_mac(size_t n_args, const mp_obj_t *args) {
     wlan_obj_t *self = args[0];
     if (n_args == 1) {
         return mp_obj_new_bytes((const byte *)self->mac, SL_BSSID_LENGTH);
@@ -1165,7 +1165,7 @@ STATIC mp_obj_t wlan_mac (mp_uint_t n_args, const mp_obj_t *args) {
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(wlan_mac_obj, 1, 2, wlan_mac);
 
-STATIC mp_obj_t wlan_irq (mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t wlan_irq(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     mp_arg_val_t args[mp_irq_INIT_NUM_ARGS];
     mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, mp_irq_INIT_NUM_ARGS, mp_irq_init_args, args);
 
diff --git a/cc3200/mods/modwlan.h b/ports/cc3200/mods/modwlan.h
similarity index 100%
rename from cc3200/mods/modwlan.h
rename to ports/cc3200/mods/modwlan.h
diff --git a/cc3200/mods/pybadc.c b/ports/cc3200/mods/pybadc.c
similarity index 98%
rename from cc3200/mods/pybadc.c
rename to ports/cc3200/mods/pybadc.c
index 1fca2da33a..c73b8c149a 100644
--- a/cc3200/mods/pybadc.c
+++ b/ports/cc3200/mods/pybadc.c
@@ -28,8 +28,6 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "py/mpconfig.h"
-#include "py/nlr.h"
 #include "py/runtime.h"
 #include "py/binary.h"
 #include "py/gc.h"
@@ -168,7 +166,7 @@ STATIC mp_obj_t adc_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_
     return self;
 }
 
-STATIC mp_obj_t adc_init(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t adc_init(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     // parse args
     mp_arg_val_t args[MP_ARRAY_SIZE(pyb_adc_init_args) - 1];
     mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_ARRAY_SIZE(args), &pyb_adc_init_args[1], args);
@@ -193,7 +191,7 @@ STATIC mp_obj_t adc_deinit(mp_obj_t self_in) {
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_1(adc_deinit_obj, adc_deinit);
 
-STATIC mp_obj_t adc_channel(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t adc_channel(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     STATIC const mp_arg_t pyb_adc_channel_args[] = {
         { MP_QSTR_id,                          MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
         { MP_QSTR_pin,        MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} },
diff --git a/cc3200/mods/pybadc.h b/ports/cc3200/mods/pybadc.h
similarity index 100%
rename from cc3200/mods/pybadc.h
rename to ports/cc3200/mods/pybadc.h
diff --git a/cc3200/mods/pybflash.c b/ports/cc3200/mods/pybflash.c
similarity index 100%
rename from cc3200/mods/pybflash.c
rename to ports/cc3200/mods/pybflash.c
diff --git a/cc3200/mods/pybflash.h b/ports/cc3200/mods/pybflash.h
similarity index 100%
rename from cc3200/mods/pybflash.h
rename to ports/cc3200/mods/pybflash.h
diff --git a/cc3200/mods/pybi2c.c b/ports/cc3200/mods/pybi2c.c
similarity index 97%
rename from cc3200/mods/pybi2c.c
rename to ports/cc3200/mods/pybi2c.c
index 370806121f..d08627fa49 100644
--- a/cc3200/mods/pybi2c.c
+++ b/ports/cc3200/mods/pybi2c.c
@@ -28,7 +28,6 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "py/mpstate.h"
 #include "py/runtime.h"
 #include "py/mperrno.h"
 #include "py/mphal.h"
@@ -380,7 +379,7 @@ STATIC mp_obj_t pyb_i2c_scan(mp_obj_t self_in) {
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_i2c_scan_obj, pyb_i2c_scan);
 
-STATIC mp_obj_t pyb_i2c_readfrom(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_i2c_readfrom(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     STATIC const mp_arg_t pyb_i2c_readfrom_args[] = {
         { MP_QSTR_addr,    MP_ARG_REQUIRED | MP_ARG_INT, },
         { MP_QSTR_nbytes,  MP_ARG_REQUIRED | MP_ARG_OBJ, },
@@ -398,7 +397,7 @@ STATIC mp_obj_t pyb_i2c_readfrom(mp_uint_t n_args, const mp_obj_t *pos_args, mp_
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_KW(pyb_i2c_readfrom_obj, 3, pyb_i2c_readfrom);
 
-STATIC mp_obj_t pyb_i2c_readfrom_into(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_i2c_readfrom_into(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     STATIC const mp_arg_t pyb_i2c_readfrom_into_args[] = {
         { MP_QSTR_addr,    MP_ARG_REQUIRED | MP_ARG_INT, },
         { MP_QSTR_buf,     MP_ARG_REQUIRED | MP_ARG_OBJ, },
@@ -416,7 +415,7 @@ STATIC mp_obj_t pyb_i2c_readfrom_into(mp_uint_t n_args, const mp_obj_t *pos_args
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_KW(pyb_i2c_readfrom_into_obj, 1, pyb_i2c_readfrom_into);
 
-STATIC mp_obj_t pyb_i2c_writeto(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_i2c_writeto(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     STATIC const mp_arg_t pyb_i2c_writeto_args[] = {
         { MP_QSTR_addr,    MP_ARG_REQUIRED | MP_ARG_INT,  },
         { MP_QSTR_buf,     MP_ARG_REQUIRED | MP_ARG_OBJ,  },
@@ -444,7 +443,7 @@ STATIC mp_obj_t pyb_i2c_writeto(mp_uint_t n_args, const mp_obj_t *pos_args, mp_m
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_KW(pyb_i2c_writeto_obj, 1, pyb_i2c_writeto);
 
-STATIC mp_obj_t pyb_i2c_readfrom_mem(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_i2c_readfrom_mem(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     STATIC const mp_arg_t pyb_i2c_readfrom_mem_args[] = {
         { MP_QSTR_addr,     MP_ARG_REQUIRED  | MP_ARG_INT, },
         { MP_QSTR_memaddr,  MP_ARG_REQUIRED  | MP_ARG_INT, },
@@ -469,7 +468,7 @@ STATIC const mp_arg_t pyb_i2c_readfrom_mem_into_args[] = {
     { MP_QSTR_addrsize, MP_ARG_KW_ONLY   | MP_ARG_INT, {.u_int = 8} },
 };
 
-STATIC mp_obj_t pyb_i2c_readfrom_mem_into(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_i2c_readfrom_mem_into(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     // parse args
     mp_arg_val_t args[MP_ARRAY_SIZE(pyb_i2c_readfrom_mem_into_args)];
     mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_ARRAY_SIZE(args), pyb_i2c_readfrom_mem_into_args, args);
@@ -481,7 +480,7 @@ STATIC mp_obj_t pyb_i2c_readfrom_mem_into(mp_uint_t n_args, const mp_obj_t *pos_
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_KW(pyb_i2c_readfrom_mem_into_obj, 1, pyb_i2c_readfrom_mem_into);
 
-STATIC mp_obj_t pyb_i2c_writeto_mem(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_i2c_writeto_mem(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     // parse args
     mp_arg_val_t args[MP_ARRAY_SIZE(pyb_i2c_readfrom_mem_into_args)];
     mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_ARRAY_SIZE(pyb_i2c_readfrom_mem_into_args), pyb_i2c_readfrom_mem_into_args, args);
diff --git a/cc3200/mods/pybi2c.h b/ports/cc3200/mods/pybi2c.h
similarity index 100%
rename from cc3200/mods/pybi2c.h
rename to ports/cc3200/mods/pybi2c.h
diff --git a/cc3200/mods/pybpin.c b/ports/cc3200/mods/pybpin.c
similarity index 98%
rename from cc3200/mods/pybpin.c
rename to ports/cc3200/mods/pybpin.c
index 43a0306362..c877433e92 100644
--- a/cc3200/mods/pybpin.c
+++ b/ports/cc3200/mods/pybpin.c
@@ -29,11 +29,8 @@
 #include <stdint.h>
 #include <string.h>
 
-#include "py/mpconfig.h"
-#include "py/obj.h"
 #include "py/runtime.h"
 #include "py/gc.h"
-#include "py/mpstate.h"
 #include "inc/hw_types.h"
 #include "inc/hw_gpio.h"
 #include "inc/hw_ints.h"
@@ -530,7 +527,7 @@ STATIC const mp_arg_t pin_init_args[] = {
 };
 #define pin_INIT_NUM_ARGS MP_ARRAY_SIZE(pin_init_args)
 
-STATIC mp_obj_t pin_obj_init_helper(pin_obj_t *self, mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t pin_obj_init_helper(pin_obj_t *self, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     // parse args
     mp_arg_val_t args[pin_INIT_NUM_ARGS];
     mp_arg_parse_all(n_args, pos_args, kw_args, pin_INIT_NUM_ARGS, pin_init_args, args);
@@ -660,12 +657,12 @@ STATIC mp_obj_t pin_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_
     return (mp_obj_t)pin;
 }
 
-STATIC mp_obj_t pin_obj_init(mp_uint_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
+STATIC mp_obj_t pin_obj_init(size_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
     return pin_obj_init_helper(args[0], n_args - 1, args + 1, kw_args);
 }
 MP_DEFINE_CONST_FUN_OBJ_KW(pin_init_obj, 1, pin_obj_init);
 
-STATIC mp_obj_t pin_value(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t pin_value(size_t n_args, const mp_obj_t *args) {
     pin_obj_t *self = args[0];
     if (n_args == 1) {
         // get the value
@@ -690,7 +687,7 @@ STATIC mp_obj_t pin_id(mp_obj_t self_in) {
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_1(pin_id_obj, pin_id);
 
-STATIC mp_obj_t pin_mode(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t pin_mode(size_t n_args, const mp_obj_t *args) {
     pin_obj_t *self = args[0];
     if (n_args == 1) {
         return mp_obj_new_int(self->mode);
@@ -704,7 +701,7 @@ STATIC mp_obj_t pin_mode(mp_uint_t n_args, const mp_obj_t *args) {
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pin_mode_obj, 1, 2, pin_mode);
 
-STATIC mp_obj_t pin_pull(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t pin_pull(size_t n_args, const mp_obj_t *args) {
     pin_obj_t *self = args[0];
     if (n_args == 1) {
         if (self->pull == PIN_TYPE_STD) {
@@ -726,7 +723,7 @@ STATIC mp_obj_t pin_pull(mp_uint_t n_args, const mp_obj_t *args) {
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pin_pull_obj, 1, 2, pin_pull);
 
-STATIC mp_obj_t pin_drive(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t pin_drive(size_t n_args, const mp_obj_t *args) {
     pin_obj_t *self = args[0];
     if (n_args == 1) {
         return mp_obj_new_int(self->strength);
@@ -761,7 +758,7 @@ STATIC mp_obj_t pin_alt_list(mp_obj_t self_in) {
 STATIC MP_DEFINE_CONST_FUN_OBJ_1(pin_alt_list_obj, pin_alt_list);
 
 /// \method irq(trigger, priority, handler, wake)
-STATIC mp_obj_t pin_irq (mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t pin_irq(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     mp_arg_val_t args[mp_irq_INIT_NUM_ARGS];
     mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, mp_irq_INIT_NUM_ARGS, mp_irq_init_args, args);
     pin_obj_t *self = pos_args[0];
diff --git a/cc3200/mods/pybpin.h b/ports/cc3200/mods/pybpin.h
similarity index 100%
rename from cc3200/mods/pybpin.h
rename to ports/cc3200/mods/pybpin.h
diff --git a/cc3200/mods/pybrtc.c b/ports/cc3200/mods/pybrtc.c
similarity index 97%
rename from cc3200/mods/pybrtc.c
rename to ports/cc3200/mods/pybrtc.c
index 8a29c930e2..e7b9cf258f 100644
--- a/cc3200/mods/pybrtc.c
+++ b/ports/cc3200/mods/pybrtc.c
@@ -310,7 +310,7 @@ STATIC mp_obj_t pyb_rtc_make_new(const mp_obj_type_t *type, size_t n_args, size_
     return (mp_obj_t)&pyb_rtc_obj;
 }
 
-STATIC mp_obj_t pyb_rtc_init (mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_rtc_init(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     // parse args
     mp_arg_val_t args[MP_ARRAY_SIZE(pyb_rtc_init_args) - 1];
     mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_ARRAY_SIZE(args), &pyb_rtc_init_args[1], args);
@@ -347,7 +347,7 @@ STATIC mp_obj_t pyb_rtc_deinit (mp_obj_t self_in) {
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_rtc_deinit_obj, pyb_rtc_deinit);
 
-STATIC mp_obj_t pyb_rtc_alarm (mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_rtc_alarm(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     STATIC const mp_arg_t allowed_args[] = {
         { MP_QSTR_id,                            MP_ARG_INT,  {.u_int = 0} },
         { MP_QSTR_time,                          MP_ARG_OBJ,  {.u_obj = mp_const_none} },
@@ -388,7 +388,7 @@ STATIC mp_obj_t pyb_rtc_alarm (mp_uint_t n_args, const mp_obj_t *pos_args, mp_ma
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_KW(pyb_rtc_alarm_obj, 1, pyb_rtc_alarm);
 
-STATIC mp_obj_t pyb_rtc_alarm_left (mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t pyb_rtc_alarm_left(size_t n_args, const mp_obj_t *args) {
     pyb_rtc_obj_t *self = args[0];
     int32_t ms_left;
     uint32_t c_seconds;
@@ -411,7 +411,7 @@ STATIC mp_obj_t pyb_rtc_alarm_left (mp_uint_t n_args, const mp_obj_t *args) {
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_rtc_alarm_left_obj, 1, 2, pyb_rtc_alarm_left);
 
-STATIC mp_obj_t pyb_rtc_alarm_cancel (mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t pyb_rtc_alarm_cancel(size_t n_args, const mp_obj_t *args) {
     // only alarm id 0 is available
     if (n_args > 1 && mp_obj_get_int(args[1]) != 0) {
         mp_raise_OSError(MP_ENODEV);
@@ -423,7 +423,7 @@ STATIC mp_obj_t pyb_rtc_alarm_cancel (mp_uint_t n_args, const mp_obj_t *args) {
 STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_rtc_alarm_cancel_obj, 1, 2, pyb_rtc_alarm_cancel);
 
 /// \method irq(trigger, priority, handler, wake)
-STATIC mp_obj_t pyb_rtc_irq (mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_rtc_irq(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     mp_arg_val_t args[mp_irq_INIT_NUM_ARGS];
     mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, mp_irq_INIT_NUM_ARGS, mp_irq_init_args, args);
     pyb_rtc_obj_t *self = pos_args[0];
diff --git a/cc3200/mods/pybrtc.h b/ports/cc3200/mods/pybrtc.h
similarity index 100%
rename from cc3200/mods/pybrtc.h
rename to ports/cc3200/mods/pybrtc.h
diff --git a/cc3200/mods/pybsd.c b/ports/cc3200/mods/pybsd.c
similarity index 98%
rename from cc3200/mods/pybsd.c
rename to ports/cc3200/mods/pybsd.c
index 34294f88e2..c47d4e9451 100644
--- a/cc3200/mods/pybsd.c
+++ b/ports/cc3200/mods/pybsd.c
@@ -144,7 +144,7 @@ STATIC mp_obj_t pyb_sd_make_new(const mp_obj_type_t *type, size_t n_args, size_t
     return self;
 }
 
-STATIC mp_obj_t pyb_sd_init (mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_sd_init(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     // parse args
     mp_arg_val_t args[MP_ARRAY_SIZE(pyb_sd_init_args) - 1];
     mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_ARRAY_SIZE(args), &pyb_sd_init_args[1], args);
diff --git a/cc3200/mods/pybsd.h b/ports/cc3200/mods/pybsd.h
similarity index 100%
rename from cc3200/mods/pybsd.h
rename to ports/cc3200/mods/pybsd.h
diff --git a/cc3200/mods/pybsleep.c b/ports/cc3200/mods/pybsleep.c
similarity index 99%
rename from cc3200/mods/pybsleep.c
rename to ports/cc3200/mods/pybsleep.c
index a7488c5f14..798c6538be 100644
--- a/cc3200/mods/pybsleep.c
+++ b/ports/cc3200/mods/pybsleep.c
@@ -27,7 +27,6 @@
 #include <stdint.h>
 #include <string.h>
 
-#include "py/mpstate.h"
 #include "py/runtime.h"
 #include "py/mphal.h"
 #include "inc/hw_types.h"
diff --git a/cc3200/mods/pybsleep.h b/ports/cc3200/mods/pybsleep.h
similarity index 100%
rename from cc3200/mods/pybsleep.h
rename to ports/cc3200/mods/pybsleep.h
diff --git a/cc3200/mods/pybspi.c b/ports/cc3200/mods/pybspi.c
similarity index 97%
rename from cc3200/mods/pybspi.c
rename to ports/cc3200/mods/pybspi.c
index acd1e25366..27591e4f4c 100644
--- a/cc3200/mods/pybspi.c
+++ b/ports/cc3200/mods/pybspi.c
@@ -28,7 +28,6 @@
 #include <stdint.h>
 #include <string.h>
 
-#include "py/mpstate.h"
 #include "py/runtime.h"
 #include "py/mperrno.h"
 #include "bufhelper.h"
@@ -248,7 +247,7 @@ STATIC mp_obj_t pyb_spi_make_new(const mp_obj_type_t *type, size_t n_args, size_
     return self;
 }
 
-STATIC mp_obj_t pyb_spi_init(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_spi_init(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     // parse args
     mp_arg_val_t args[MP_ARRAY_SIZE(pyb_spi_init_args) - 1];
     mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_ARRAY_SIZE(args), &pyb_spi_init_args[1], args);
@@ -287,7 +286,7 @@ STATIC mp_obj_t pyb_spi_write (mp_obj_t self_in, mp_obj_t buf) {
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_2(pyb_spi_write_obj, pyb_spi_write);
 
-STATIC mp_obj_t pyb_spi_read(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_spi_read(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     static const mp_arg_t allowed_args[] = {
         { MP_QSTR_nbytes,    MP_ARG_REQUIRED | MP_ARG_OBJ, },
         { MP_QSTR_write,     MP_ARG_INT, {.u_int = 0x00} },
@@ -311,7 +310,7 @@ STATIC mp_obj_t pyb_spi_read(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_KW(pyb_spi_read_obj, 1, pyb_spi_read);
 
-STATIC mp_obj_t pyb_spi_readinto(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_spi_readinto(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     static const mp_arg_t allowed_args[] = {
         { MP_QSTR_buf,       MP_ARG_REQUIRED | MP_ARG_OBJ, },
         { MP_QSTR_write,     MP_ARG_INT, {.u_int = 0x00} },
diff --git a/cc3200/mods/pybspi.h b/ports/cc3200/mods/pybspi.h
similarity index 100%
rename from cc3200/mods/pybspi.h
rename to ports/cc3200/mods/pybspi.h
diff --git a/cc3200/mods/pybtimer.c b/ports/cc3200/mods/pybtimer.c
similarity index 96%
rename from cc3200/mods/pybtimer.c
rename to ports/cc3200/mods/pybtimer.c
index d6ed1b14b1..ea795b8480 100644
--- a/cc3200/mods/pybtimer.c
+++ b/ports/cc3200/mods/pybtimer.c
@@ -29,9 +29,6 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "py/mpconfig.h"
-#include "py/obj.h"
-#include "py/nlr.h"
 #include "py/runtime.h"
 #include "py/gc.h"
 #include "py/mperrno.h"
@@ -111,7 +108,7 @@ STATIC const mp_obj_t pyb_timer_pwm_pin[8] = {&pin_GP24, MP_OBJ_NULL, &pin_GP25,
 /******************************************************************************
  DECLARE PRIVATE FUNCTIONS
  ******************************************************************************/
-STATIC mp_obj_t pyb_timer_channel_irq (mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args);
+STATIC mp_obj_t pyb_timer_channel_irq(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args);
 STATIC void timer_disable (pyb_timer_obj_t *tim);
 STATIC void timer_channel_init (pyb_timer_channel_obj_t *ch);
 STATIC void TIMER0AIntHandler(void);
@@ -285,7 +282,7 @@ STATIC void pyb_timer_print(const mp_print_t *print, mp_obj_t self_in, mp_print_
     mp_printf(print, "Timer(%u, mode=Timer.%q)", tim->id, mode_qst);
 }
 
-STATIC mp_obj_t pyb_timer_init_helper(pyb_timer_obj_t *tim, mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_timer_init_helper(pyb_timer_obj_t *tim, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     static const mp_arg_t allowed_args[] = {
         { MP_QSTR_mode,         MP_ARG_REQUIRED | MP_ARG_INT, },
         { MP_QSTR_width,        MP_ARG_KW_ONLY  | MP_ARG_INT, {.u_int = 16} },
@@ -346,7 +343,7 @@ STATIC mp_obj_t pyb_timer_make_new(const mp_obj_type_t *type, size_t n_args, siz
     return (mp_obj_t)tim;
 }
 
-STATIC mp_obj_t pyb_timer_init(mp_uint_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_timer_init(size_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
     return pyb_timer_init_helper(args[0], n_args - 1, args + 1, kw_args);
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_KW(pyb_timer_init_obj, 1, pyb_timer_init);
@@ -358,7 +355,7 @@ STATIC mp_obj_t pyb_timer_deinit(mp_obj_t self_in) {
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_timer_deinit_obj, pyb_timer_deinit);
 
-STATIC mp_obj_t pyb_timer_channel(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_timer_channel(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     static const mp_arg_t allowed_args[] = {
         { MP_QSTR_freq,                MP_ARG_KW_ONLY  | MP_ARG_INT, {.u_int = 0} },
         { MP_QSTR_period,              MP_ARG_KW_ONLY  | MP_ARG_INT, {.u_int = 0} },
@@ -552,7 +549,7 @@ STATIC void pyb_timer_channel_print(const mp_print_t *print, mp_obj_t self_in, m
     mp_printf(print, ")");
 }
 
-STATIC mp_obj_t pyb_timer_channel_freq(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t pyb_timer_channel_freq(size_t n_args, const mp_obj_t *args) {
     pyb_timer_channel_obj_t *ch = args[0];
     if (n_args == 1) {
         // get
@@ -571,7 +568,7 @@ STATIC mp_obj_t pyb_timer_channel_freq(mp_uint_t n_args, const mp_obj_t *args) {
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_timer_channel_freq_obj, 1, 2, pyb_timer_channel_freq);
 
-STATIC mp_obj_t pyb_timer_channel_period(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t pyb_timer_channel_period(size_t n_args, const mp_obj_t *args) {
     pyb_timer_channel_obj_t *ch = args[0];
     if (n_args == 1) {
         // get
@@ -590,7 +587,7 @@ STATIC mp_obj_t pyb_timer_channel_period(mp_uint_t n_args, const mp_obj_t *args)
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_timer_channel_period_obj, 1, 2, pyb_timer_channel_period);
 
-STATIC mp_obj_t pyb_timer_channel_duty_cycle(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t pyb_timer_channel_duty_cycle(size_t n_args, const mp_obj_t *args) {
     pyb_timer_channel_obj_t *ch = args[0];
     if (n_args == 1) {
         // get
@@ -614,7 +611,7 @@ STATIC mp_obj_t pyb_timer_channel_duty_cycle(mp_uint_t n_args, const mp_obj_t *a
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_timer_channel_duty_cycle_obj, 1, 3, pyb_timer_channel_duty_cycle);
 
-STATIC mp_obj_t pyb_timer_channel_irq (mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_timer_channel_irq(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     mp_arg_val_t args[mp_irq_INIT_NUM_ARGS];
     mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, mp_irq_INIT_NUM_ARGS, mp_irq_init_args, args);
     pyb_timer_channel_obj_t *ch = pos_args[0];
diff --git a/cc3200/mods/pybtimer.h b/ports/cc3200/mods/pybtimer.h
similarity index 100%
rename from cc3200/mods/pybtimer.h
rename to ports/cc3200/mods/pybtimer.h
diff --git a/cc3200/mods/pybuart.c b/ports/cc3200/mods/pybuart.c
similarity index 98%
rename from cc3200/mods/pybuart.c
rename to ports/cc3200/mods/pybuart.c
index 77ebbbf182..35c0de9f95 100644
--- a/cc3200/mods/pybuart.c
+++ b/ports/cc3200/mods/pybuart.c
@@ -29,12 +29,11 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "py/mpconfig.h"
-#include "py/obj.h"
 #include "py/runtime.h"
 #include "py/objlist.h"
 #include "py/stream.h"
 #include "py/mphal.h"
+#include "lib/utils/interrupt_char.h"
 #include "inc/hw_types.h"
 #include "inc/hw_ints.h"
 #include "inc/hw_memmap.h"
@@ -47,7 +46,6 @@
 #include "mpirq.h"
 #include "pybsleep.h"
 #include "mpexception.h"
-#include "py/mpstate.h"
 #include "osi.h"
 #include "utils.h"
 #include "pin.h"
@@ -251,9 +249,9 @@ STATIC void UARTGenericIntHandler(uint32_t uart_id) {
         MAP_UARTIntClear(self->reg, UART_INT_RX | UART_INT_RT);
         while (UARTCharsAvail(self->reg)) {
             int data = MAP_UARTCharGetNonBlocking(self->reg);
-            if (MP_STATE_PORT(os_term_dup_obj) && MP_STATE_PORT(os_term_dup_obj)->stream_o == self && data == user_interrupt_char) {
+            if (MP_STATE_PORT(os_term_dup_obj) && MP_STATE_PORT(os_term_dup_obj)->stream_o == self && data == mp_interrupt_char) {
                 // raise an exception when interrupts are finished
-                mpexception_keyboard_nlr_jump();
+                mp_keyboard_interrupt();
             } else { // there's always a read buffer available
                 uint16_t next_head = (self->read_buf_head + 1) % PYBUART_RX_BUFFER_LEN;
                 if (next_head != self->read_buf_tail) {
@@ -487,7 +485,7 @@ STATIC mp_obj_t pyb_uart_make_new(const mp_obj_type_t *type, size_t n_args, size
     return self;
 }
 
-STATIC mp_obj_t pyb_uart_init(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_uart_init(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     // parse args
     mp_arg_val_t args[MP_ARRAY_SIZE(pyb_uart_init_args) - 1];
     mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_ARRAY_SIZE(args), &pyb_uart_init_args[1], args);
@@ -530,7 +528,7 @@ STATIC mp_obj_t pyb_uart_sendbreak(mp_obj_t self_in) {
 STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_uart_sendbreak_obj, pyb_uart_sendbreak);
 
 /// \method irq(trigger, priority, handler, wake)
-STATIC mp_obj_t pyb_uart_irq (mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_uart_irq(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     mp_arg_val_t args[mp_irq_INIT_NUM_ARGS];
     mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, mp_irq_INIT_NUM_ARGS, mp_irq_init_args, args);
 
diff --git a/cc3200/mods/pybuart.h b/ports/cc3200/mods/pybuart.h
similarity index 100%
rename from cc3200/mods/pybuart.h
rename to ports/cc3200/mods/pybuart.h
diff --git a/cc3200/mods/pybwdt.c b/ports/cc3200/mods/pybwdt.c
similarity index 100%
rename from cc3200/mods/pybwdt.c
rename to ports/cc3200/mods/pybwdt.c
diff --git a/cc3200/mods/pybwdt.h b/ports/cc3200/mods/pybwdt.h
similarity index 100%
rename from cc3200/mods/pybwdt.h
rename to ports/cc3200/mods/pybwdt.h
diff --git a/cc3200/mpconfigport.h b/ports/cc3200/mpconfigport.h
similarity index 99%
rename from cc3200/mpconfigport.h
rename to ports/cc3200/mpconfigport.h
index a5b007daf6..29ae9092b1 100644
--- a/cc3200/mpconfigport.h
+++ b/ports/cc3200/mpconfigport.h
@@ -120,6 +120,7 @@
 
 #define MICROPY_ENABLE_EMERGENCY_EXCEPTION_BUF      (1)
 #define MICROPY_EMERGENCY_EXCEPTION_BUF_SIZE        (0)
+#define MICROPY_KBD_EXCEPTION                       (1)
 
 // We define our own list of errno constants to include in uerrno module
 #define MICROPY_PY_UERRNO_LIST \
diff --git a/cc3200/mptask.c b/ports/cc3200/mptask.c
similarity index 99%
rename from cc3200/mptask.c
rename to ports/cc3200/mptask.c
index 019da49712..81048d1e7e 100644
--- a/cc3200/mptask.c
+++ b/ports/cc3200/mptask.c
@@ -61,7 +61,6 @@
 #include "telnet.h"
 #include "debug.h"
 #include "sflash_diskio.h"
-#include "mpexception.h"
 #include "random.h"
 #include "pybi2c.h"
 #include "pins.h"
@@ -143,7 +142,6 @@ soft_reset:
     mp_obj_list_append(mp_sys_path, MP_OBJ_NEW_QSTR(MP_QSTR_)); // current dir (or base dir of the script)
 
     // execute all basic initializations
-    mpexception_init0();
     mp_irq_init0();
     pyb_sleep_init0();
     pin_init0();
diff --git a/cc3200/mptask.h b/ports/cc3200/mptask.h
similarity index 100%
rename from cc3200/mptask.h
rename to ports/cc3200/mptask.h
diff --git a/cc3200/mpthreadport.c b/ports/cc3200/mpthreadport.c
similarity index 99%
rename from cc3200/mpthreadport.c
rename to ports/cc3200/mpthreadport.c
index e77ac4ae53..9dbc518e06 100644
--- a/cc3200/mpthreadport.c
+++ b/ports/cc3200/mpthreadport.c
@@ -26,8 +26,6 @@
 
 #include <stdio.h>
 
-#include "py/mpconfig.h"
-#include "py/mpstate.h"
 #include "py/runtime.h"
 #include "py/gc.h"
 #include "py/mpthread.h"
diff --git a/cc3200/mpthreadport.h b/ports/cc3200/mpthreadport.h
similarity index 100%
rename from cc3200/mpthreadport.h
rename to ports/cc3200/mpthreadport.h
diff --git a/cc3200/qstrdefsport.h b/ports/cc3200/qstrdefsport.h
similarity index 100%
rename from cc3200/qstrdefsport.h
rename to ports/cc3200/qstrdefsport.h
diff --git a/cc3200/serverstask.c b/ports/cc3200/serverstask.c
similarity index 100%
rename from cc3200/serverstask.c
rename to ports/cc3200/serverstask.c
diff --git a/cc3200/serverstask.h b/ports/cc3200/serverstask.h
similarity index 100%
rename from cc3200/serverstask.h
rename to ports/cc3200/serverstask.h
diff --git a/cc3200/simplelink/cc_pal.c b/ports/cc3200/simplelink/cc_pal.c
similarity index 100%
rename from cc3200/simplelink/cc_pal.c
rename to ports/cc3200/simplelink/cc_pal.c
diff --git a/cc3200/simplelink/cc_pal.h b/ports/cc3200/simplelink/cc_pal.h
similarity index 100%
rename from cc3200/simplelink/cc_pal.h
rename to ports/cc3200/simplelink/cc_pal.h
diff --git a/cc3200/simplelink/oslib/osi.h b/ports/cc3200/simplelink/oslib/osi.h
similarity index 100%
rename from cc3200/simplelink/oslib/osi.h
rename to ports/cc3200/simplelink/oslib/osi.h
diff --git a/cc3200/simplelink/oslib/osi_freertos.c b/ports/cc3200/simplelink/oslib/osi_freertos.c
similarity index 100%
rename from cc3200/simplelink/oslib/osi_freertos.c
rename to ports/cc3200/simplelink/oslib/osi_freertos.c
diff --git a/cc3200/simplelink/user.h b/ports/cc3200/simplelink/user.h
similarity index 100%
rename from cc3200/simplelink/user.h
rename to ports/cc3200/simplelink/user.h
diff --git a/cc3200/telnet/telnet.c b/ports/cc3200/telnet/telnet.c
similarity index 99%
rename from cc3200/telnet/telnet.c
rename to ports/cc3200/telnet/telnet.c
index 2f0818f6ba..dbb77cd6d7 100644
--- a/cc3200/telnet/telnet.c
+++ b/ports/cc3200/telnet/telnet.c
@@ -29,6 +29,7 @@
 #include "py/mpconfig.h"
 #include "py/obj.h"
 #include "py/mphal.h"
+#include "lib/utils/interrupt_char.h"
 #include "telnet.h"
 #include "simplelink.h"
 #include "modnetwork.h"
@@ -445,9 +446,9 @@ static void telnet_parse_input (uint8_t *str, int16_t *len) {
 
     for (uint8_t *_str = b_str; _str < b_str + b_len; ) {
         if (*_str <= 127) {
-            if (telnet_data.state == E_TELNET_STE_LOGGED_IN && *_str == user_interrupt_char) {
+            if (telnet_data.state == E_TELNET_STE_LOGGED_IN && *_str == mp_interrupt_char) {
                 // raise a keyboard exception
-                mpexception_keyboard_nlr_jump();
+                mp_keyboard_interrupt();
                 (*len)--;
                 _str++;
             }
diff --git a/cc3200/telnet/telnet.h b/ports/cc3200/telnet/telnet.h
similarity index 100%
rename from cc3200/telnet/telnet.h
rename to ports/cc3200/telnet/telnet.h
diff --git a/cc3200/tools/smoke.py b/ports/cc3200/tools/smoke.py
similarity index 100%
rename from cc3200/tools/smoke.py
rename to ports/cc3200/tools/smoke.py
diff --git a/cc3200/tools/smoke.py.exp b/ports/cc3200/tools/smoke.py.exp
similarity index 100%
rename from cc3200/tools/smoke.py.exp
rename to ports/cc3200/tools/smoke.py.exp
diff --git a/cc3200/tools/uniflash.py b/ports/cc3200/tools/uniflash.py
similarity index 100%
rename from cc3200/tools/uniflash.py
rename to ports/cc3200/tools/uniflash.py
diff --git a/cc3200/tools/update-wipy.py b/ports/cc3200/tools/update-wipy.py
similarity index 100%
rename from cc3200/tools/update-wipy.py
rename to ports/cc3200/tools/update-wipy.py
diff --git a/cc3200/util/cryptohash.c b/ports/cc3200/util/cryptohash.c
similarity index 100%
rename from cc3200/util/cryptohash.c
rename to ports/cc3200/util/cryptohash.c
diff --git a/cc3200/util/cryptohash.h b/ports/cc3200/util/cryptohash.h
similarity index 100%
rename from cc3200/util/cryptohash.h
rename to ports/cc3200/util/cryptohash.h
diff --git a/cc3200/util/fifo.c b/ports/cc3200/util/fifo.c
similarity index 100%
rename from cc3200/util/fifo.c
rename to ports/cc3200/util/fifo.c
diff --git a/cc3200/util/fifo.h b/ports/cc3200/util/fifo.h
similarity index 100%
rename from cc3200/util/fifo.h
rename to ports/cc3200/util/fifo.h
diff --git a/cc3200/util/gccollect.c b/ports/cc3200/util/gccollect.c
similarity index 97%
rename from cc3200/util/gccollect.c
rename to ports/cc3200/util/gccollect.c
index baee2eeef9..6e2a9081c8 100644
--- a/cc3200/util/gccollect.c
+++ b/ports/cc3200/util/gccollect.c
@@ -28,8 +28,6 @@
 #include <stdio.h>
 #include <stdint.h>
 
-#include "py/mpconfig.h"
-#include "py/mpstate.h"
 #include "py/gc.h"
 #include "py/mpthread.h"
 #include "gccollect.h"
diff --git a/cc3200/util/gccollect.h b/ports/cc3200/util/gccollect.h
similarity index 100%
rename from cc3200/util/gccollect.h
rename to ports/cc3200/util/gccollect.h
diff --git a/cc3200/util/gchelper.h b/ports/cc3200/util/gchelper.h
similarity index 100%
rename from cc3200/util/gchelper.h
rename to ports/cc3200/util/gchelper.h
diff --git a/cc3200/util/gchelper.s b/ports/cc3200/util/gchelper.s
similarity index 100%
rename from cc3200/util/gchelper.s
rename to ports/cc3200/util/gchelper.s
diff --git a/cc3200/util/random.c b/ports/cc3200/util/random.c
similarity index 100%
rename from cc3200/util/random.c
rename to ports/cc3200/util/random.c
diff --git a/cc3200/util/random.h b/ports/cc3200/util/random.h
similarity index 100%
rename from cc3200/util/random.h
rename to ports/cc3200/util/random.h
diff --git a/cc3200/util/sleeprestore.h b/ports/cc3200/util/sleeprestore.h
similarity index 100%
rename from cc3200/util/sleeprestore.h
rename to ports/cc3200/util/sleeprestore.h
diff --git a/cc3200/util/sleeprestore.s b/ports/cc3200/util/sleeprestore.s
similarity index 100%
rename from cc3200/util/sleeprestore.s
rename to ports/cc3200/util/sleeprestore.s
diff --git a/cc3200/util/socketfifo.c b/ports/cc3200/util/socketfifo.c
similarity index 100%
rename from cc3200/util/socketfifo.c
rename to ports/cc3200/util/socketfifo.c
diff --git a/cc3200/util/socketfifo.h b/ports/cc3200/util/socketfifo.h
similarity index 100%
rename from cc3200/util/socketfifo.h
rename to ports/cc3200/util/socketfifo.h
diff --git a/cc3200/version.h b/ports/cc3200/version.h
similarity index 100%
rename from cc3200/version.h
rename to ports/cc3200/version.h
diff --git a/esp8266/Makefile b/ports/esp8266/Makefile
similarity index 98%
rename from esp8266/Makefile
rename to ports/esp8266/Makefile
index 78916c3f73..ebb8981ef5 100644
--- a/esp8266/Makefile
+++ b/ports/esp8266/Makefile
@@ -8,7 +8,7 @@ endif
 # If the build directory is not given, make it reflect the board name.
 BUILD ?= build
 
-include ../py/mkenv.mk
+include ../../py/mkenv.mk
 
 # qstr definitions (must come before including py.mk)
 QSTR_DEFS = qstrdefsport.h #$(BUILD)/pins_qstr.h
@@ -17,6 +17,7 @@ MICROPY_PY_USSL = 1
 MICROPY_SSL_AXTLS = 1
 MICROPY_FATFS = 1
 MICROPY_PY_BTREE = 1
+BTREE_DEFS_EXTRA = -DDEFPSIZE=1024 -DMINCACHE=3
 
 FROZEN_DIR ?= scripts
 FROZEN_MPY_DIR ?= modules
@@ -93,7 +94,7 @@ SRC_C = \
 	modnetwork.c \
 	ets_alt_task.c \
 	fatfs_port.c \
-	axtls_helpers.c \
+	posix_helpers.c \
 	hspi.c \
 	boards/$(BOARD)/pins.c \
 	$(SRC_MOD)
diff --git a/esp8266/README.md b/ports/esp8266/README.md
similarity index 100%
rename from esp8266/README.md
rename to ports/esp8266/README.md
diff --git a/esp8266/boards/feather_huzzah/pins.c b/ports/esp8266/boards/feather_huzzah/pins.c
similarity index 100%
rename from esp8266/boards/feather_huzzah/pins.c
rename to ports/esp8266/boards/feather_huzzah/pins.c
diff --git a/esp8266/common-hal/analogio/AnalogIn.c b/ports/esp8266/common-hal/analogio/AnalogIn.c
similarity index 100%
rename from esp8266/common-hal/analogio/AnalogIn.c
rename to ports/esp8266/common-hal/analogio/AnalogIn.c
diff --git a/esp8266/common-hal/analogio/AnalogIn.h b/ports/esp8266/common-hal/analogio/AnalogIn.h
similarity index 100%
rename from esp8266/common-hal/analogio/AnalogIn.h
rename to ports/esp8266/common-hal/analogio/AnalogIn.h
diff --git a/esp8266/common-hal/analogio/AnalogOut.c b/ports/esp8266/common-hal/analogio/AnalogOut.c
similarity index 100%
rename from esp8266/common-hal/analogio/AnalogOut.c
rename to ports/esp8266/common-hal/analogio/AnalogOut.c
diff --git a/esp8266/common-hal/analogio/AnalogOut.h b/ports/esp8266/common-hal/analogio/AnalogOut.h
similarity index 100%
rename from esp8266/common-hal/analogio/AnalogOut.h
rename to ports/esp8266/common-hal/analogio/AnalogOut.h
diff --git a/esp8266/common-hal/analogio/__init__.c b/ports/esp8266/common-hal/analogio/__init__.c
similarity index 100%
rename from esp8266/common-hal/analogio/__init__.c
rename to ports/esp8266/common-hal/analogio/__init__.c
diff --git a/esp8266/common-hal/board/__init__.c b/ports/esp8266/common-hal/board/__init__.c
similarity index 100%
rename from esp8266/common-hal/board/__init__.c
rename to ports/esp8266/common-hal/board/__init__.c
diff --git a/esp8266/common-hal/busio/I2C.h b/ports/esp8266/common-hal/busio/I2C.h
similarity index 100%
rename from esp8266/common-hal/busio/I2C.h
rename to ports/esp8266/common-hal/busio/I2C.h
diff --git a/esp8266/common-hal/busio/OneWire.h b/ports/esp8266/common-hal/busio/OneWire.h
similarity index 100%
rename from esp8266/common-hal/busio/OneWire.h
rename to ports/esp8266/common-hal/busio/OneWire.h
diff --git a/esp8266/common-hal/busio/SPI.c b/ports/esp8266/common-hal/busio/SPI.c
similarity index 99%
rename from esp8266/common-hal/busio/SPI.c
rename to ports/esp8266/common-hal/busio/SPI.c
index fc8dd348f1..50ad03460e 100644
--- a/esp8266/common-hal/busio/SPI.c
+++ b/ports/esp8266/common-hal/busio/SPI.c
@@ -24,15 +24,15 @@
  * THE SOFTWARE.
  */
 
-#include "esp8266/ets_alt_task.h"
-#include "esp8266/hspi.h"
 #include "shared-bindings/microcontroller/__init__.h"
 #include "common-hal/busio/SPI.h"
 #include "py/nlr.h"
 
 #include "eagle_soc.h"
+#include "ets_alt_task.h"
 #include "c_types.h"
 #include "gpio.h"
+#include "hspi.h"
 
 extern const mcu_pin_obj_t pin_MTMS;
 extern const mcu_pin_obj_t pin_MTCK;
diff --git a/esp8266/common-hal/busio/SPI.h b/ports/esp8266/common-hal/busio/SPI.h
similarity index 100%
rename from esp8266/common-hal/busio/SPI.h
rename to ports/esp8266/common-hal/busio/SPI.h
diff --git a/esp8266/common-hal/busio/UART.c b/ports/esp8266/common-hal/busio/UART.c
similarity index 100%
rename from esp8266/common-hal/busio/UART.c
rename to ports/esp8266/common-hal/busio/UART.c
diff --git a/esp8266/common-hal/busio/UART.h b/ports/esp8266/common-hal/busio/UART.h
similarity index 100%
rename from esp8266/common-hal/busio/UART.h
rename to ports/esp8266/common-hal/busio/UART.h
diff --git a/esp8266/common-hal/busio/__init__.c b/ports/esp8266/common-hal/busio/__init__.c
similarity index 100%
rename from esp8266/common-hal/busio/__init__.c
rename to ports/esp8266/common-hal/busio/__init__.c
diff --git a/esp8266/common-hal/digitalio/DigitalInOut.c b/ports/esp8266/common-hal/digitalio/DigitalInOut.c
similarity index 100%
rename from esp8266/common-hal/digitalio/DigitalInOut.c
rename to ports/esp8266/common-hal/digitalio/DigitalInOut.c
diff --git a/esp8266/common-hal/digitalio/DigitalInOut.h b/ports/esp8266/common-hal/digitalio/DigitalInOut.h
similarity index 100%
rename from esp8266/common-hal/digitalio/DigitalInOut.h
rename to ports/esp8266/common-hal/digitalio/DigitalInOut.h
diff --git a/esp8266/common-hal/digitalio/__init__.c b/ports/esp8266/common-hal/digitalio/__init__.c
similarity index 100%
rename from esp8266/common-hal/digitalio/__init__.c
rename to ports/esp8266/common-hal/digitalio/__init__.c
diff --git a/esp8266/common-hal/microcontroller/Pin.c b/ports/esp8266/common-hal/microcontroller/Pin.c
similarity index 100%
rename from esp8266/common-hal/microcontroller/Pin.c
rename to ports/esp8266/common-hal/microcontroller/Pin.c
diff --git a/esp8266/common-hal/microcontroller/Pin.h b/ports/esp8266/common-hal/microcontroller/Pin.h
similarity index 100%
rename from esp8266/common-hal/microcontroller/Pin.h
rename to ports/esp8266/common-hal/microcontroller/Pin.h
diff --git a/esp8266/common-hal/microcontroller/Processor.c b/ports/esp8266/common-hal/microcontroller/Processor.c
similarity index 100%
rename from esp8266/common-hal/microcontroller/Processor.c
rename to ports/esp8266/common-hal/microcontroller/Processor.c
diff --git a/esp8266/common-hal/microcontroller/Processor.h b/ports/esp8266/common-hal/microcontroller/Processor.h
similarity index 100%
rename from esp8266/common-hal/microcontroller/Processor.h
rename to ports/esp8266/common-hal/microcontroller/Processor.h
diff --git a/esp8266/common-hal/microcontroller/__init__.c b/ports/esp8266/common-hal/microcontroller/__init__.c
similarity index 100%
rename from esp8266/common-hal/microcontroller/__init__.c
rename to ports/esp8266/common-hal/microcontroller/__init__.c
diff --git a/esp8266/common-hal/microcontroller/__init__.h b/ports/esp8266/common-hal/microcontroller/__init__.h
similarity index 100%
rename from esp8266/common-hal/microcontroller/__init__.h
rename to ports/esp8266/common-hal/microcontroller/__init__.h
diff --git a/esp8266/common-hal/multiterminal/__init__.c b/ports/esp8266/common-hal/multiterminal/__init__.c
similarity index 100%
rename from esp8266/common-hal/multiterminal/__init__.c
rename to ports/esp8266/common-hal/multiterminal/__init__.c
diff --git a/esp8266/common-hal/neopixel_write/__init__.c b/ports/esp8266/common-hal/neopixel_write/__init__.c
similarity index 100%
rename from esp8266/common-hal/neopixel_write/__init__.c
rename to ports/esp8266/common-hal/neopixel_write/__init__.c
diff --git a/esp8266/common-hal/os/__init__.c b/ports/esp8266/common-hal/os/__init__.c
similarity index 100%
rename from esp8266/common-hal/os/__init__.c
rename to ports/esp8266/common-hal/os/__init__.c
diff --git a/esp8266/common-hal/pulseio/PWMOut.c b/ports/esp8266/common-hal/pulseio/PWMOut.c
similarity index 100%
rename from esp8266/common-hal/pulseio/PWMOut.c
rename to ports/esp8266/common-hal/pulseio/PWMOut.c
diff --git a/esp8266/common-hal/pulseio/PWMOut.h b/ports/esp8266/common-hal/pulseio/PWMOut.h
similarity index 100%
rename from esp8266/common-hal/pulseio/PWMOut.h
rename to ports/esp8266/common-hal/pulseio/PWMOut.h
diff --git a/esp8266/common-hal/pulseio/PulseIn.c b/ports/esp8266/common-hal/pulseio/PulseIn.c
similarity index 100%
rename from esp8266/common-hal/pulseio/PulseIn.c
rename to ports/esp8266/common-hal/pulseio/PulseIn.c
diff --git a/esp8266/common-hal/pulseio/PulseIn.h b/ports/esp8266/common-hal/pulseio/PulseIn.h
similarity index 100%
rename from esp8266/common-hal/pulseio/PulseIn.h
rename to ports/esp8266/common-hal/pulseio/PulseIn.h
diff --git a/esp8266/common-hal/pulseio/PulseOut.c b/ports/esp8266/common-hal/pulseio/PulseOut.c
similarity index 100%
rename from esp8266/common-hal/pulseio/PulseOut.c
rename to ports/esp8266/common-hal/pulseio/PulseOut.c
diff --git a/esp8266/common-hal/pulseio/PulseOut.h b/ports/esp8266/common-hal/pulseio/PulseOut.h
similarity index 100%
rename from esp8266/common-hal/pulseio/PulseOut.h
rename to ports/esp8266/common-hal/pulseio/PulseOut.h
diff --git a/esp8266/common-hal/pulseio/__init__.c b/ports/esp8266/common-hal/pulseio/__init__.c
similarity index 100%
rename from esp8266/common-hal/pulseio/__init__.c
rename to ports/esp8266/common-hal/pulseio/__init__.c
diff --git a/esp8266/common-hal/storage/__init__.c b/ports/esp8266/common-hal/storage/__init__.c
similarity index 100%
rename from esp8266/common-hal/storage/__init__.c
rename to ports/esp8266/common-hal/storage/__init__.c
diff --git a/esp8266/common-hal/time/__init__.c b/ports/esp8266/common-hal/time/__init__.c
similarity index 100%
rename from esp8266/common-hal/time/__init__.c
rename to ports/esp8266/common-hal/time/__init__.c
diff --git a/esp8266/eagle.rom.addr.v6.ld b/ports/esp8266/eagle.rom.addr.v6.ld
similarity index 100%
rename from esp8266/eagle.rom.addr.v6.ld
rename to ports/esp8266/eagle.rom.addr.v6.ld
diff --git a/esp8266/esp8266.ld b/ports/esp8266/esp8266.ld
similarity index 100%
rename from esp8266/esp8266.ld
rename to ports/esp8266/esp8266.ld
diff --git a/esp8266/esp8266_512k.ld b/ports/esp8266/esp8266_512k.ld
similarity index 100%
rename from esp8266/esp8266_512k.ld
rename to ports/esp8266/esp8266_512k.ld
diff --git a/esp8266/esp8266_common.ld b/ports/esp8266/esp8266_common.ld
similarity index 100%
rename from esp8266/esp8266_common.ld
rename to ports/esp8266/esp8266_common.ld
diff --git a/esp8266/esp8266_ota.ld b/ports/esp8266/esp8266_ota.ld
similarity index 100%
rename from esp8266/esp8266_ota.ld
rename to ports/esp8266/esp8266_ota.ld
diff --git a/esp8266/esp_init_data.c b/ports/esp8266/esp_init_data.c
similarity index 100%
rename from esp8266/esp_init_data.c
rename to ports/esp8266/esp_init_data.c
diff --git a/esp8266/esp_mphal.c b/ports/esp8266/esp_mphal.c
similarity index 90%
rename from esp8266/esp_mphal.c
rename to ports/esp8266/esp_mphal.c
index 748c90292f..4f3ca58365 100644
--- a/esp8266/esp_mphal.c
+++ b/ports/esp8266/esp_mphal.c
@@ -31,8 +31,6 @@
 #include "esp_mphal.h"
 #include "user_interface.h"
 #include "ets_alt_task.h"
-#include "py/obj.h"
-#include "py/mpstate.h"
 #include "py/runtime.h"
 #include "extmod/misc.h"
 #include "lib/utils/pyexec.h"
@@ -76,11 +74,6 @@ int mp_hal_stdin_rx_chr(void) {
     }
 }
 
-void mp_hal_stdout_tx_char(char c) {
-    uart_tx_one_char(UART0, c);
-    mp_uos_dupterm_tx_strn(&c, 1);
-}
-
 #if 0
 void mp_hal_debug_str(const char *str) {
     while (*str) {
@@ -91,23 +84,39 @@ void mp_hal_debug_str(const char *str) {
 #endif
 
 void mp_hal_stdout_tx_str(const char *str) {
+    const char *last = str;
     while (*str) {
-        mp_hal_stdout_tx_char(*str++);
+        uart_tx_one_char(UART0, *str++);
     }
+    mp_uos_dupterm_tx_strn(last, str - last);
 }
 
 void mp_hal_stdout_tx_strn(const char *str, uint32_t len) {
+    const char *last = str;
     while (len--) {
-        mp_hal_stdout_tx_char(*str++);
+        uart_tx_one_char(UART0, *str++);
     }
+    mp_uos_dupterm_tx_strn(last, str - last);
 }
 
 void mp_hal_stdout_tx_strn_cooked(const char *str, uint32_t len) {
+    const char *last = str;
     while (len--) {
         if (*str == '\n') {
-            mp_hal_stdout_tx_char('\r');
+            if (str > last) {
+                mp_uos_dupterm_tx_strn(last, str - last);
+            }
+            uart_tx_one_char(UART0, '\r');
+            uart_tx_one_char(UART0, '\n');
+            mp_uos_dupterm_tx_strn("\r\n", 2);
+            ++str;
+            last = str;
+        } else {
+            uart_tx_one_char(UART0, *str++);
         }
-        mp_hal_stdout_tx_char(*str++);
+    }
+    if (str > last) {
+        mp_uos_dupterm_tx_strn(last, str - last);
     }
 }
 
diff --git a/esp8266/esp_mphal.h b/ports/esp8266/esp_mphal.h
similarity index 99%
rename from esp8266/esp_mphal.h
rename to ports/esp8266/esp_mphal.h
index 913bd70dc9..194e56f649 100644
--- a/esp8266/esp_mphal.h
+++ b/ports/esp8266/esp_mphal.h
@@ -72,7 +72,7 @@ void ets_event_poll(void);
 // C-level pin HAL
 #include "etshal.h"
 #include "gpio.h"
-#include "esp8266/modmachine.h"
+#include "modmachine.h"
 #define MP_HAL_PIN_FMT "%u"
 #define mp_hal_pin_obj_t uint32_t
 #define mp_hal_get_pin_obj(o) mp_obj_get_pin(o)
diff --git a/esp8266/espapa102.c b/ports/esp8266/espapa102.c
similarity index 100%
rename from esp8266/espapa102.c
rename to ports/esp8266/espapa102.c
diff --git a/esp8266/espapa102.h b/ports/esp8266/espapa102.h
similarity index 100%
rename from esp8266/espapa102.h
rename to ports/esp8266/espapa102.h
diff --git a/esp8266/espneopixel.c b/ports/esp8266/espneopixel.c
similarity index 100%
rename from esp8266/espneopixel.c
rename to ports/esp8266/espneopixel.c
diff --git a/esp8266/espneopixel.h b/ports/esp8266/espneopixel.h
similarity index 100%
rename from esp8266/espneopixel.h
rename to ports/esp8266/espneopixel.h
diff --git a/esp8266/esppwm.c b/ports/esp8266/esppwm.c
similarity index 100%
rename from esp8266/esppwm.c
rename to ports/esp8266/esppwm.c
diff --git a/esp8266/esppwm.h b/ports/esp8266/esppwm.h
similarity index 100%
rename from esp8266/esppwm.h
rename to ports/esp8266/esppwm.h
diff --git a/esp8266/espuart.c b/ports/esp8266/espuart.c
similarity index 100%
rename from esp8266/espuart.c
rename to ports/esp8266/espuart.c
diff --git a/esp8266/espuart.h b/ports/esp8266/espuart.h
similarity index 100%
rename from esp8266/espuart.h
rename to ports/esp8266/espuart.h
diff --git a/esp8266/ets_alt_task.c b/ports/esp8266/ets_alt_task.c
similarity index 100%
rename from esp8266/ets_alt_task.c
rename to ports/esp8266/ets_alt_task.c
diff --git a/esp8266/ets_alt_task.h b/ports/esp8266/ets_alt_task.h
similarity index 100%
rename from esp8266/ets_alt_task.h
rename to ports/esp8266/ets_alt_task.h
diff --git a/esp8266/etshal.h b/ports/esp8266/etshal.h
similarity index 100%
rename from esp8266/etshal.h
rename to ports/esp8266/etshal.h
diff --git a/esp8266/fatfs_port.c b/ports/esp8266/fatfs_port.c
similarity index 100%
rename from esp8266/fatfs_port.c
rename to ports/esp8266/fatfs_port.c
diff --git a/esp8266/gccollect.c b/ports/esp8266/gccollect.c
similarity index 100%
rename from esp8266/gccollect.c
rename to ports/esp8266/gccollect.c
diff --git a/esp8266/gccollect.h b/ports/esp8266/gccollect.h
similarity index 100%
rename from esp8266/gccollect.h
rename to ports/esp8266/gccollect.h
diff --git a/esp8266/gchelper.s b/ports/esp8266/gchelper.s
similarity index 100%
rename from esp8266/gchelper.s
rename to ports/esp8266/gchelper.s
diff --git a/esp8266/help.c b/ports/esp8266/help.c
similarity index 98%
rename from esp8266/help.c
rename to ports/esp8266/help.c
index 2035cdd6cb..0a851f4c48 100644
--- a/esp8266/help.c
+++ b/ports/esp8266/help.c
@@ -26,7 +26,7 @@
 
 #include "py/builtin.h"
 
-const char *esp_help_text =
+const char esp_help_text[] =
 "Welcome to MicroPython!\n"
 "\n"
 "For online docs please visit http://docs.micropython.org/en/latest/esp8266/ .\n"
diff --git a/esp8266/hspi.c b/ports/esp8266/hspi.c
similarity index 100%
rename from esp8266/hspi.c
rename to ports/esp8266/hspi.c
diff --git a/esp8266/hspi.h b/ports/esp8266/hspi.h
similarity index 100%
rename from esp8266/hspi.h
rename to ports/esp8266/hspi.h
diff --git a/esp8266/hspi_register.h b/ports/esp8266/hspi_register.h
similarity index 100%
rename from esp8266/hspi_register.h
rename to ports/esp8266/hspi_register.h
diff --git a/esp8266/intr.c b/ports/esp8266/intr.c
similarity index 100%
rename from esp8266/intr.c
rename to ports/esp8266/intr.c
diff --git a/esp8266/lexerstr32.c b/ports/esp8266/lexerstr32.c
similarity index 100%
rename from esp8266/lexerstr32.c
rename to ports/esp8266/lexerstr32.c
diff --git a/esp8266/machine_adc.c b/ports/esp8266/machine_adc.c
similarity index 98%
rename from esp8266/machine_adc.c
rename to ports/esp8266/machine_adc.c
index c8c08695bd..b422f0f9ec 100644
--- a/esp8266/machine_adc.c
+++ b/ports/esp8266/machine_adc.c
@@ -27,8 +27,6 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "py/nlr.h"
-#include "py/obj.h"
 #include "py/runtime.h"
 #include "user_interface.h"
 
diff --git a/esp8266/machine_hspi.c b/ports/esp8266/machine_hspi.c
similarity index 100%
rename from esp8266/machine_hspi.c
rename to ports/esp8266/machine_hspi.c
diff --git a/esp8266/machine_pin.c b/ports/esp8266/machine_pin.c
similarity index 98%
rename from esp8266/machine_pin.c
rename to ports/esp8266/machine_pin.c
index 673082065b..14505c8f02 100644
--- a/esp8266/machine_pin.c
+++ b/ports/esp8266/machine_pin.c
@@ -33,7 +33,6 @@
 #include "user_interface.h"
 #include "gpio.h"
 
-#include "py/nlr.h"
 #include "py/runtime.h"
 #include "py/gc.h"
 #include "py/mphal.h"
@@ -243,7 +242,7 @@ STATIC void pyb_pin_print(const mp_print_t *print, mp_obj_t self_in, mp_print_ki
 }
 
 // pin.init(mode, pull=None, *, value)
-STATIC mp_obj_t pyb_pin_obj_init_helper(pyb_pin_obj_t *self, mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_pin_obj_init_helper(pyb_pin_obj_t *self, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     enum { ARG_mode, ARG_pull, ARG_value };
     static const mp_arg_t allowed_args[] = {
         { MP_QSTR_mode, MP_ARG_REQUIRED | MP_ARG_INT },
@@ -347,13 +346,13 @@ STATIC mp_obj_t pyb_pin_call(mp_obj_t self_in, size_t n_args, size_t n_kw, const
 }
 
 // pin.init(mode, pull)
-STATIC mp_obj_t pyb_pin_obj_init(mp_uint_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_pin_obj_init(size_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
     return pyb_pin_obj_init_helper(args[0], n_args - 1, args + 1, kw_args);
 }
 MP_DEFINE_CONST_FUN_OBJ_KW(pyb_pin_init_obj, 1, pyb_pin_obj_init);
 
 // pin.value([value])
-STATIC mp_obj_t pyb_pin_value(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t pyb_pin_value(size_t n_args, const mp_obj_t *args) {
     return pyb_pin_call(args[0], n_args - 1, 0, args + 1);
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_pin_value_obj, 1, 2, pyb_pin_value);
diff --git a/esp8266/machine_pwm.c b/ports/esp8266/machine_pwm.c
similarity index 99%
rename from esp8266/machine_pwm.c
rename to ports/esp8266/machine_pwm.c
index 0f6e90983e..961b8e5474 100644
--- a/esp8266/machine_pwm.c
+++ b/ports/esp8266/machine_pwm.c
@@ -29,7 +29,6 @@
 
 #include "esppwm.h"
 
-#include "py/nlr.h"
 #include "py/runtime.h"
 #include "modmachine.h"
 
diff --git a/esp8266/machine_rtc.c b/ports/esp8266/machine_rtc.c
similarity index 98%
rename from esp8266/machine_rtc.c
rename to ports/esp8266/machine_rtc.c
index c5d04e0cfa..bbfc172cd8 100644
--- a/esp8266/machine_rtc.c
+++ b/ports/esp8266/machine_rtc.c
@@ -27,8 +27,6 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "py/nlr.h"
-#include "py/obj.h"
 #include "py/runtime.h"
 #include "lib/timeutils/timeutils.h"
 #include "user_interface.h"
@@ -126,7 +124,7 @@ void rtc_prepare_deepsleep(uint64_t sleep_us) {
     system_rtc_mem_write(MEM_DELTA_ADDR, &delta, sizeof(delta));
 }
 
-STATIC mp_obj_t pyb_rtc_datetime(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t pyb_rtc_datetime(size_t n_args, const mp_obj_t *args) {
     if (n_args == 1) {
         // Get time
         uint64_t msecs = pyb_rtc_get_us_since_2000() / 1000;
@@ -165,7 +163,7 @@ STATIC mp_obj_t pyb_rtc_datetime(mp_uint_t n_args, const mp_obj_t *args) {
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_rtc_datetime_obj, 1, 2, pyb_rtc_datetime);
 
-STATIC mp_obj_t pyb_rtc_memory(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t pyb_rtc_memory(size_t n_args, const mp_obj_t *args) {
     uint8_t rtcram[MEM_USER_MAXLEN];
     uint32_t len;
 
diff --git a/esp8266/machine_uart.c b/ports/esp8266/machine_uart.c
similarity index 100%
rename from esp8266/machine_uart.c
rename to ports/esp8266/machine_uart.c
diff --git a/esp8266/machine_wdt.c b/ports/esp8266/machine_wdt.c
similarity index 98%
rename from esp8266/machine_wdt.c
rename to ports/esp8266/machine_wdt.c
index 5e23ff7826..04b42782e5 100644
--- a/esp8266/machine_wdt.c
+++ b/ports/esp8266/machine_wdt.c
@@ -27,8 +27,6 @@
 //#include <stdio.h>
 #include <string.h>
 
-#include "py/nlr.h"
-#include "py/obj.h"
 #include "py/runtime.h"
 #include "user_interface.h"
 #include "etshal.h"
diff --git a/esp8266/main.c b/ports/esp8266/main.c
similarity index 99%
rename from esp8266/main.c
rename to ports/esp8266/main.c
index 49c454e723..04ea827617 100644
--- a/esp8266/main.c
+++ b/ports/esp8266/main.c
@@ -27,10 +27,8 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "py/nlr.h"
 #include "py/compile.h"
 #include "py/frozenmod.h"
-#include "py/runtime0.h"
 #include "py/runtime.h"
 #include "py/stackctrl.h"
 #include "py/mperrno.h"
diff --git a/esp8266/makeimg.py b/ports/esp8266/makeimg.py
similarity index 100%
rename from esp8266/makeimg.py
rename to ports/esp8266/makeimg.py
diff --git a/esp8266/modesp.c b/ports/esp8266/modesp.c
similarity index 99%
rename from esp8266/modesp.c
rename to ports/esp8266/modesp.c
index cecedeb03f..b57f7de586 100644
--- a/esp8266/modesp.c
+++ b/ports/esp8266/modesp.c
@@ -56,7 +56,7 @@ STATIC mp_obj_t esp_osdebug(mp_obj_t val) {
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_1(esp_osdebug_obj, esp_osdebug);
 
-STATIC mp_obj_t esp_sleep_type(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t esp_sleep_type(size_t n_args, const mp_obj_t *args) {
     if (n_args == 0) {
         return mp_obj_new_int(wifi_get_sleep_type());
     } else {
@@ -66,7 +66,7 @@ STATIC mp_obj_t esp_sleep_type(mp_uint_t n_args, const mp_obj_t *args) {
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(esp_sleep_type_obj, 0, 1, esp_sleep_type);
 
-STATIC mp_obj_t esp_deepsleep(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t esp_deepsleep(size_t n_args, const mp_obj_t *args) {
     uint32_t sleep_us = n_args > 0 ? mp_obj_get_int(args[0]) : 0;
     // prepare for RTC reset at wake up
     rtc_prepare_deepsleep(sleep_us);
diff --git a/esp8266/modmachine.c b/ports/esp8266/modmachine.c
similarity index 97%
rename from esp8266/modmachine.c
rename to ports/esp8266/modmachine.c
index 98bc495586..99286848e2 100644
--- a/esp8266/modmachine.c
+++ b/ports/esp8266/modmachine.c
@@ -51,7 +51,7 @@
 
 extern const mp_obj_type_t esp_wdt_type;
 
-STATIC mp_obj_t machine_freq(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t machine_freq(size_t n_args, const mp_obj_t *args) {
     if (n_args == 0) {
         // get
         return mp_obj_new_int(system_get_cpu_freq() * 1000000);
@@ -159,7 +159,7 @@ STATIC void esp_timer_cb(void *arg) {
     mp_sched_schedule(self->callback, self);
 }
 
-STATIC mp_obj_t esp_timer_init_helper(esp_timer_obj_t *self, mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t esp_timer_init_helper(esp_timer_obj_t *self, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     static const mp_arg_t allowed_args[] = {
 //        { MP_QSTR_freq,         MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} },
         { MP_QSTR_period,       MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0xffffffff} },
@@ -180,7 +180,7 @@ STATIC mp_obj_t esp_timer_init_helper(esp_timer_obj_t *self, mp_uint_t n_args, c
     return mp_const_none;
 }
 
-STATIC mp_obj_t esp_timer_init(mp_uint_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
+STATIC mp_obj_t esp_timer_init(size_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
     return esp_timer_init_helper(args[0], n_args - 1, args + 1, kw_args);
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_KW(esp_timer_init_obj, 1, esp_timer_init);
diff --git a/esp8266/modmachine.h b/ports/esp8266/modmachine.h
similarity index 100%
rename from esp8266/modmachine.h
rename to ports/esp8266/modmachine.h
diff --git a/esp8266/modnetwork.c b/ports/esp8266/modnetwork.c
similarity index 98%
rename from esp8266/modnetwork.c
rename to ports/esp8266/modnetwork.c
index b893209c65..2c61e5dcdb 100644
--- a/esp8266/modnetwork.c
+++ b/ports/esp8266/modnetwork.c
@@ -28,7 +28,6 @@
 #include <stdint.h>
 #include <string.h>
 
-#include "py/nlr.h"
 #include "py/objlist.h"
 #include "py/runtime.h"
 #include "py/mphal.h"
@@ -62,7 +61,7 @@ STATIC void require_if(mp_obj_t wlan_if, int if_no) {
     }
 }
 
-STATIC mp_obj_t get_wlan(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t get_wlan(size_t n_args, const mp_obj_t *args) {
     int idx = 0;
     if (n_args > 0) {
         idx = mp_obj_get_int(args[0]);
@@ -71,7 +70,7 @@ STATIC mp_obj_t get_wlan(mp_uint_t n_args, const mp_obj_t *args) {
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(get_wlan_obj, 0, 1, get_wlan);
 
-STATIC mp_obj_t esp_active(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t esp_active(size_t n_args, const mp_obj_t *args) {
     wlan_if_obj_t *self = MP_OBJ_TO_PTR(args[0]);
     uint32_t mode = wifi_get_opmode();
     if (n_args > 1) {
@@ -94,7 +93,7 @@ STATIC mp_obj_t esp_active(mp_uint_t n_args, const mp_obj_t *args) {
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(esp_active_obj, 1, 2, esp_active);
 
-STATIC mp_obj_t esp_connect(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t esp_connect(size_t n_args, const mp_obj_t *args) {
     require_if(args[0], STATION_IF);
     struct station_config config = {{0}};
     size_t len;
@@ -442,7 +441,7 @@ const mp_obj_type_t wlan_if_type = {
     .locals_dict = (mp_obj_dict_t*)&wlan_if_locals_dict,
 };
 
-STATIC mp_obj_t esp_phy_mode(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t esp_phy_mode(size_t n_args, const mp_obj_t *args) {
     if (n_args == 0) {
         return mp_obj_new_int(wifi_get_phy_mode());
     } else {
diff --git a/esp8266/modpyb.c b/ports/esp8266/modpyb.c
similarity index 97%
rename from esp8266/modpyb.c
rename to ports/esp8266/modpyb.c
index e977191ee6..0a23f6f9da 100644
--- a/esp8266/modpyb.c
+++ b/ports/esp8266/modpyb.c
@@ -35,7 +35,7 @@
 // only remaining function is pyb.info() which has been moved to the
 // esp module, pending deletion/renaming/moving elsewhere.
 
-STATIC mp_obj_t pyb_info(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t pyb_info(size_t n_args, const mp_obj_t *args) {
     // print info about memory
     {
         printf("_text_start=%p\n", &_text_start);
diff --git a/esp8266/modules/_boot.py b/ports/esp8266/modules/_boot.py
similarity index 100%
rename from esp8266/modules/_boot.py
rename to ports/esp8266/modules/_boot.py
diff --git a/esp8266/modules/apa102.py b/ports/esp8266/modules/apa102.py
similarity index 100%
rename from esp8266/modules/apa102.py
rename to ports/esp8266/modules/apa102.py
diff --git a/esp8266/modules/dht.py b/ports/esp8266/modules/dht.py
similarity index 100%
rename from esp8266/modules/dht.py
rename to ports/esp8266/modules/dht.py
diff --git a/ports/esp8266/modules/ds18x20.py b/ports/esp8266/modules/ds18x20.py
new file mode 120000
index 0000000000..1ec92d1c99
--- /dev/null
+++ b/ports/esp8266/modules/ds18x20.py
@@ -0,0 +1 @@
+../../../drivers/onewire/ds18x20.py
\ No newline at end of file
diff --git a/esp8266/modules/flashbdev.py b/ports/esp8266/modules/flashbdev.py
similarity index 100%
rename from esp8266/modules/flashbdev.py
rename to ports/esp8266/modules/flashbdev.py
diff --git a/esp8266/modules/inisetup.py b/ports/esp8266/modules/inisetup.py
similarity index 100%
rename from esp8266/modules/inisetup.py
rename to ports/esp8266/modules/inisetup.py
diff --git a/esp8266/modules/ntptime.py b/ports/esp8266/modules/ntptime.py
similarity index 100%
rename from esp8266/modules/ntptime.py
rename to ports/esp8266/modules/ntptime.py
diff --git a/ports/esp8266/modules/onewire.py b/ports/esp8266/modules/onewire.py
new file mode 120000
index 0000000000..33f30e84f1
--- /dev/null
+++ b/ports/esp8266/modules/onewire.py
@@ -0,0 +1 @@
+../../../drivers/onewire/onewire.py
\ No newline at end of file
diff --git a/esp8266/modules/port_diag.py b/ports/esp8266/modules/port_diag.py
similarity index 100%
rename from esp8266/modules/port_diag.py
rename to ports/esp8266/modules/port_diag.py
diff --git a/ports/esp8266/modules/upip.py b/ports/esp8266/modules/upip.py
new file mode 120000
index 0000000000..130eb69016
--- /dev/null
+++ b/ports/esp8266/modules/upip.py
@@ -0,0 +1 @@
+../../../tools/upip.py
\ No newline at end of file
diff --git a/ports/esp8266/modules/upip_utarfile.py b/ports/esp8266/modules/upip_utarfile.py
new file mode 120000
index 0000000000..d9653d6a60
--- /dev/null
+++ b/ports/esp8266/modules/upip_utarfile.py
@@ -0,0 +1 @@
+../../../tools/upip_utarfile.py
\ No newline at end of file
diff --git a/esp8266/modules/webrepl.py b/ports/esp8266/modules/webrepl.py
similarity index 100%
rename from esp8266/modules/webrepl.py
rename to ports/esp8266/modules/webrepl.py
diff --git a/esp8266/modules/webrepl_setup.py b/ports/esp8266/modules/webrepl_setup.py
similarity index 100%
rename from esp8266/modules/webrepl_setup.py
rename to ports/esp8266/modules/webrepl_setup.py
diff --git a/esp8266/modules/websocket_helper.py b/ports/esp8266/modules/websocket_helper.py
similarity index 100%
rename from esp8266/modules/websocket_helper.py
rename to ports/esp8266/modules/websocket_helper.py
diff --git a/esp8266/modutime.c b/ports/esp8266/modutime.c
similarity index 97%
rename from esp8266/modutime.c
rename to ports/esp8266/modutime.c
index afb14dfd6a..ab9cb7dc23 100644
--- a/esp8266/modutime.c
+++ b/ports/esp8266/modutime.c
@@ -28,8 +28,6 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "py/nlr.h"
-#include "py/obj.h"
 #include "py/gc.h"
 #include "py/runtime.h"
 #include "py/mphal.h"
@@ -56,7 +54,7 @@
 /// second  is 0-59
 /// weekday is 0-6 for Mon-Sun.
 /// yearday is 1-366
-STATIC mp_obj_t time_localtime(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t time_localtime(size_t n_args, const mp_obj_t *args) {
     timeutils_struct_time_t tm;
     mp_int_t seconds;
     if (n_args == 0 || args[0] == mp_const_none) {
diff --git a/esp8266/mpconfigport.h b/ports/esp8266/mpconfigport.h
similarity index 100%
rename from esp8266/mpconfigport.h
rename to ports/esp8266/mpconfigport.h
diff --git a/esp8266/mpconfigport_512k.h b/ports/esp8266/mpconfigport_512k.h
similarity index 100%
rename from esp8266/mpconfigport_512k.h
rename to ports/esp8266/mpconfigport_512k.h
diff --git a/esp8266/axtls_helpers.c b/ports/esp8266/posix_helpers.c
similarity index 81%
rename from esp8266/axtls_helpers.c
rename to ports/esp8266/posix_helpers.c
index 6d508fdeb1..1fc677c5c5 100644
--- a/esp8266/axtls_helpers.c
+++ b/ports/esp8266/posix_helpers.c
@@ -26,22 +26,33 @@
 
 #include <stdint.h>
 #include <stdio.h>
+#include <errno.h>
 #include "py/mphal.h"
 #include "py/gc.h"
 
-// Functions for axTLS
+// Functions for external libs like axTLS, BerkeleyDB, etc.
 
 void *malloc(size_t size) {
-    return gc_alloc(size, false);
+    void *p = gc_alloc(size, false);
+    if (p == NULL) {
+        // POSIX requires ENOMEM to be set in case of error
+        errno = ENOMEM;
+    }
+    return p;
 }
 void free(void *ptr) {
     gc_free(ptr);
 }
 void *calloc(size_t nmemb, size_t size) {
-    return m_malloc0(nmemb * size);
+    return malloc(nmemb * size);
 }
 void *realloc(void *ptr, size_t size) {
-    return gc_realloc(ptr, size, true);
+    void *p = gc_realloc(ptr, size, true);
+    if (p == NULL) {
+        // POSIX requires ENOMEM to be set in case of error
+        errno = ENOMEM;
+    }
+    return p;
 }
 
 #define PLATFORM_HTONL(_n) ((uint32_t)( (((_n) & 0xff) << 24) | (((_n) & 0xff00) << 8) | (((_n) >> 8)  & 0xff00) | (((_n) >> 24) & 0xff) ))
diff --git a/esp8266/qstrdefsport.h b/ports/esp8266/qstrdefsport.h
similarity index 100%
rename from esp8266/qstrdefsport.h
rename to ports/esp8266/qstrdefsport.h
diff --git a/esp8266/strtoll.c b/ports/esp8266/strtoll.c
similarity index 100%
rename from esp8266/strtoll.c
rename to ports/esp8266/strtoll.c
diff --git a/esp8266/uart_register.h b/ports/esp8266/uart_register.h
similarity index 100%
rename from esp8266/uart_register.h
rename to ports/esp8266/uart_register.h
diff --git a/esp8266/user_config.h b/ports/esp8266/user_config.h
similarity index 100%
rename from esp8266/user_config.h
rename to ports/esp8266/user_config.h
diff --git a/esp8266/xtirq.h b/ports/esp8266/xtirq.h
similarity index 100%
rename from esp8266/xtirq.h
rename to ports/esp8266/xtirq.h
diff --git a/minimal/Makefile b/ports/minimal/Makefile
similarity index 98%
rename from minimal/Makefile
rename to ports/minimal/Makefile
index c95d639aff..ae295d655e 100644
--- a/minimal/Makefile
+++ b/ports/minimal/Makefile
@@ -1,4 +1,4 @@
-include ../py/mkenv.mk
+include ../../py/mkenv.mk
 
 CROSS = 0
 
diff --git a/minimal/README.md b/ports/minimal/README.md
similarity index 100%
rename from minimal/README.md
rename to ports/minimal/README.md
diff --git a/minimal/frozentest.mpy b/ports/minimal/frozentest.mpy
similarity index 100%
rename from minimal/frozentest.mpy
rename to ports/minimal/frozentest.mpy
diff --git a/minimal/frozentest.py b/ports/minimal/frozentest.py
similarity index 100%
rename from minimal/frozentest.py
rename to ports/minimal/frozentest.py
diff --git a/minimal/main.c b/ports/minimal/main.c
similarity index 99%
rename from minimal/main.c
rename to ports/minimal/main.c
index e28cfe45eb..9d43a9cf97 100644
--- a/minimal/main.c
+++ b/ports/minimal/main.c
@@ -2,7 +2,6 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "py/nlr.h"
 #include "py/compile.h"
 #include "py/runtime.h"
 #include "py/repl.h"
diff --git a/minimal/mpconfigport.h b/ports/minimal/mpconfigport.h
similarity index 100%
rename from minimal/mpconfigport.h
rename to ports/minimal/mpconfigport.h
diff --git a/minimal/mphalport.h b/ports/minimal/mphalport.h
similarity index 100%
rename from minimal/mphalport.h
rename to ports/minimal/mphalport.h
diff --git a/minimal/qstrdefsport.h b/ports/minimal/qstrdefsport.h
similarity index 100%
rename from minimal/qstrdefsport.h
rename to ports/minimal/qstrdefsport.h
diff --git a/minimal/stm32f405.ld b/ports/minimal/stm32f405.ld
similarity index 100%
rename from minimal/stm32f405.ld
rename to ports/minimal/stm32f405.ld
diff --git a/minimal/uart_core.c b/ports/minimal/uart_core.c
similarity index 100%
rename from minimal/uart_core.c
rename to ports/minimal/uart_core.c
diff --git a/ports/nrf/.gitignore b/ports/nrf/.gitignore
new file mode 100644
index 0000000000..ace93515a2
--- /dev/null
+++ b/ports/nrf/.gitignore
@@ -0,0 +1,8 @@
+# Nordic files
+#####################
+drivers/bluetooth/s1*/
+
+# Build files
+#####################
+build-*/
+
diff --git a/ports/nrf/Makefile b/ports/nrf/Makefile
new file mode 100644
index 0000000000..ca22e093c3
--- /dev/null
+++ b/ports/nrf/Makefile
@@ -0,0 +1,294 @@
+# Select the board to build for: if not given on the command line,
+# then default to pca10040.
+BOARD ?= pca10040
+ifeq ($(wildcard boards/$(BOARD)/.),)
+$(error Invalid BOARD specified)
+endif
+
+# If SoftDevice is selected, try to use that one.
+SD ?=
+SD_LOWER = $(shell echo $(SD) | tr '[:upper:]' '[:lower:]')
+
+# TODO: Verify that it is a valid target.
+
+
+ifeq ($(SD), )
+	# If the build directory is not given, make it reflect the board name.
+	BUILD ?= build-$(BOARD)
+	include ../../py/mkenv.mk
+	include boards/$(BOARD)/mpconfigboard.mk
+else
+	# If the build directory is not given, make it reflect the board name.
+	BUILD ?= build-$(BOARD)-$(SD_LOWER)
+	include ../../py/mkenv.mk
+	include boards/$(BOARD)/mpconfigboard_$(SD_LOWER).mk
+
+	include drivers/bluetooth/bluetooth_common.mk
+endif
+
+# qstr definitions (must come before including py.mk)
+QSTR_DEFS = qstrdefsport.h $(BUILD)/pins_qstr.h
+
+FROZEN_MPY_DIR = freeze
+
+# include py core make definitions
+include ../../py/py.mk
+
+
+FATFS_DIR = lib/oofatfs
+MPY_CROSS = ../../mpy-cross/mpy-cross
+MPY_TOOL = ../../tools/mpy-tool.py
+
+CROSS_COMPILE = arm-none-eabi-
+
+MCU_VARIANT_UPPER = $(shell echo $(MCU_VARIANT) | tr '[:lower:]' '[:upper:]')
+
+INC += -I.
+INC += -I../..
+INC += -I$(BUILD)
+INC += -I./../../lib/cmsis/inc
+INC += -I./device
+INC += -I./device/$(MCU_VARIANT)
+INC += -I./hal
+INC += -I./hal/$(MCU_VARIANT)
+INC += -I./modules/machine
+INC += -I./modules/ubluepy
+INC += -I./modules/music
+INC += -I./modules/random
+INC += -I./modules/ble
+INC += -I../../lib/mp-readline
+INC += -I./drivers/bluetooth
+INC += -I./drivers
+
+NRF_DEFINES += -D$(MCU_VARIANT_UPPER)
+NRF_DEFINES += -DCONFIG_GPIO_AS_PINRESET
+
+CFLAGS_CORTEX_M = -mthumb -mabi=aapcs -fsingle-precision-constant -Wdouble-promotion
+
+CFLAGS_MCU_m4 = $(CFLAGS_CORTEX_M) -mtune=cortex-m4 -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard
+
+CFLAGS_MCU_m0 = $(CFLAGS_CORTEX_M) --short-enums -mtune=cortex-m0 -mcpu=cortex-m0 -mfloat-abi=soft -fno-builtin
+
+
+CFLAGS += $(CFLAGS_MCU_$(MCU_SERIES)) 
+CFLAGS += $(INC) -Wall -Werror -ansi -std=gnu99 -nostdlib $(COPT) $(NRF_DEFINES) $(CFLAGS_MOD)
+CFLAGS += -fno-strict-aliasing
+CFLAGS += -fstack-usage
+CFLAGS += -fdata-sections -ffunction-sections
+CFLAGS += -Iboards/$(BOARD)
+CFLAGS += -DNRF5_HAL_H='<$(MCU_VARIANT)_hal.h>'
+
+LDFLAGS = $(CFLAGS)
+LDFLAGS += -Xlinker -Map=$(@:.elf=.map)
+LDFLAGS += -mthumb -mabi=aapcs -T $(LD_FILE) -L boards/
+LDFLAGS += -Wl,--gc-sections
+
+#Debugging/Optimization
+ifeq ($(DEBUG), 1)
+#ASMFLAGS += -g -gtabs+
+CFLAGS += -O0 -ggdb
+LDFLAGS += -O0
+else
+CFLAGS += -Os -DNDEBUG
+LDFLAGS += -Os
+endif
+
+LIBS = \
+
+ifeq ($(MCU_VARIANT), nrf52)
+LIBM_FILE_NAME   = $(shell $(CC) $(CFLAGS) -print-file-name=libm.a)
+LIBC_FILE_NAME   = $(shell $(CC) $(CFLAGS) -print-file-name=libc.a)
+LIBGCC_FILE_NAME = $(shell $(CC) $(CFLAGS) -print-libgcc-file-name)
+
+LIBS += -L $(dir $(LIBM_FILE_NAME)) -lm
+LIBS += -L $(dir $(LIBC_FILE_NAME)) -lc
+LIBS += -L $(dir $(LIBGCC_FILE_NAME)) -lgcc
+endif
+
+SRC_LIB = $(addprefix lib/,\
+	libc/string0.c \
+	mp-readline/readline.c \
+	utils/pyexec.c \
+	timeutils/timeutils.c \
+	oofatfs/ff.c \
+	oofatfs/option/unicode.c \
+	)
+
+SRC_HAL = $(addprefix hal/,\
+	hal_uart.c \
+	hal_uarte.c \
+	hal_spi.c \
+	hal_spie.c \
+	hal_time.c \
+	hal_rtc.c \
+	hal_timer.c \
+	hal_twi.c \
+	hal_adc.c \
+	hal_adce.c \
+	hal_temp.c \
+	hal_gpio.c \
+	hal_rng.c \
+	)
+
+ifeq ($(MCU_VARIANT), nrf52)
+SRC_HAL += $(addprefix hal/,\
+	hal_pwm.c \
+	)
+endif
+
+SRC_C += \
+	main.c \
+	mphalport.c \
+	help.c \
+	gccollect.c \
+	pin_named_pins.c \
+	fatfs_port.c \
+	drivers/softpwm.c \
+	drivers/ticker.c \
+	drivers/bluetooth/ble_drv.c \
+	drivers/bluetooth/ble_uart.c \
+
+DRIVERS_SRC_C += $(addprefix modules/,\
+	machine/modmachine.c \
+	machine/uart.c \
+	machine/spi.c \
+	machine/i2c.c \
+	machine/adc.c \
+	machine/pin.c \
+	machine/timer.c \
+	machine/rtc.c \
+	machine/pwm.c \
+	machine/led.c \
+	machine/temp.c \
+	uos/moduos.c \
+	utime/modutime.c \
+	pyb/modpyb.c \
+	ubluepy/modubluepy.c \
+	ubluepy/ubluepy_peripheral.c \
+	ubluepy/ubluepy_service.c \
+	ubluepy/ubluepy_characteristic.c \
+	ubluepy/ubluepy_uuid.c \
+	ubluepy/ubluepy_delegate.c \
+	ubluepy/ubluepy_constants.c \
+	ubluepy/ubluepy_descriptor.c \
+	ubluepy/ubluepy_scanner.c \
+	ubluepy/ubluepy_scan_entry.c \
+	music/modmusic.c \
+	music/musictunes.c \
+	ble/modble.c \
+	random/modrandom.c \
+	)
+
+SRC_C += \
+	device/$(MCU_VARIANT)/system_$(MCU_SUB_VARIANT).c \
+	device/$(MCU_VARIANT)/startup_$(MCU_SUB_VARIANT).c \
+
+FROZEN_MPY_PY_FILES := $(shell find -L $(FROZEN_MPY_DIR) -type f -name '*.py')
+FROZEN_MPY_MPY_FILES := $(addprefix $(BUILD)/,$(FROZEN_MPY_PY_FILES:.py=.mpy))
+
+OBJ += $(PY_O) $(addprefix $(BUILD)/, $(SRC_C:.c=.o))
+OBJ += $(addprefix $(BUILD)/, $(SRC_LIB:.c=.o))
+OBJ += $(addprefix $(BUILD)/, $(SRC_HAL:.c=.o))
+OBJ += $(addprefix $(BUILD)/, $(DRIVERS_SRC_C:.c=.o))
+OBJ += $(BUILD)/pins_gen.o
+
+$(BUILD)/$(FATFS_DIR)/ff.o: COPT += -Os
+$(filter $(PY_BUILD)/../extmod/vfs_fat_%.o, $(PY_O)): COPT += -Os
+
+.phony: all flash sd binary hex
+
+all: binary hex
+
+OUTPUT_FILENAME = firmware
+
+## Create binary .bin file from the .out file
+binary: $(BUILD)/$(OUTPUT_FILENAME).bin
+
+$(BUILD)/$(OUTPUT_FILENAME).bin: $(BUILD)/$(OUTPUT_FILENAME).elf
+	$(OBJCOPY) -O binary $< $@
+
+## Create binary .hex file from the .out file
+hex: $(BUILD)/$(OUTPUT_FILENAME).hex
+
+$(BUILD)/$(OUTPUT_FILENAME).hex: $(BUILD)/$(OUTPUT_FILENAME).elf
+	$(OBJCOPY) -O ihex $< $@
+
+FLASHER ?=
+
+ifeq ($(FLASHER),)
+
+flash: $(BUILD)/$(OUTPUT_FILENAME).hex
+	nrfjprog --program $< --sectorerase -f $(MCU_VARIANT)
+	nrfjprog --reset -f $(MCU_VARIANT)
+
+sd: $(BUILD)/$(OUTPUT_FILENAME).hex
+	nrfjprog --eraseall -f $(MCU_VARIANT)
+	nrfjprog --program $(SOFTDEV_HEX) -f $(MCU_VARIANT)
+	nrfjprog --program $< --sectorerase -f $(MCU_VARIANT)
+	nrfjprog --reset -f $(MCU_VARIANT)
+
+else ifeq ($(FLASHER), pyocd)
+
+flash: $(BUILD)/$(OUTPUT_FILENAME).hex
+	pyocd-flashtool -t $(MCU_VARIANT) $<
+
+sd: $(BUILD)/$(OUTPUT_FILENAME).hex
+	pyocd-flashtool -t $(MCU_VARIANT) --chip_erase
+	pyocd-flashtool -t $(MCU_VARIANT) $(SOFTDEV_HEX)
+	pyocd-flashtool -t $(MCU_VARIANT) $<
+
+endif
+
+$(BUILD)/$(OUTPUT_FILENAME).elf: $(OBJ)
+	$(ECHO) "LINK $@"
+	$(Q)$(CC) $(LDFLAGS) -o $@ $(OBJ) $(LIBS)
+	$(Q)$(SIZE) $@
+
+# List of sources for qstr extraction
+SRC_QSTR += $(SRC_C) $(SRC_MOD) $(SRC_LIB) $(DRIVERS_SRC_C)
+
+# Append any auto-generated sources that are needed by sources listed in
+# SRC_QSTR
+SRC_QSTR_AUTO_DEPS +=
+
+# Making OBJ use an order-only depenedency on the generated pins.h file
+# has the side effect of making the pins.h file before we actually compile
+# any of the objects. The normal dependency generation will deal with the
+# case when pins.h is modified. But when it doesn't exist, we don't know
+# which source files might need it.
+$(OBJ): | $(HEADER_BUILD)/pins.h
+
+# Use a pattern rule here so that make will only call make-pins.py once to make
+# both pins_$(BOARD).c and pins.h
+$(BUILD)/%_$(BOARD).c $(HEADER_BUILD)/%.h $(HEADER_BUILD)/%_af_const.h $(BUILD)/%_qstr.h: boards/$(BOARD)/%.csv $(MAKE_PINS) $(AF_FILE) $(PREFIX_FILE) | $(HEADER_BUILD)
+	$(ECHO) "Create $@"
+	$(Q)$(PYTHON) $(MAKE_PINS) --board $(BOARD_PINS) --af $(AF_FILE) --prefix $(PREFIX_FILE) --hdr $(GEN_PINS_HDR) --qstr $(GEN_PINS_QSTR) --af-const $(GEN_PINS_AF_CONST) --af-py $(GEN_PINS_AF_PY) > $(GEN_PINS_SRC)
+
+$(BUILD)/pins_gen.o: $(BUILD)/pins_gen.c
+	$(call compile_c)
+
+MAKE_PINS = boards/make-pins.py
+BOARD_PINS = boards/$(BOARD)/pins.csv
+AF_FILE = $(MCU_VARIANT)_af.csv
+PREFIX_FILE = boards/$(MCU_VARIANT)_prefix.c
+GEN_PINS_SRC = $(BUILD)/pins_gen.c
+GEN_PINS_HDR = $(HEADER_BUILD)/pins.h
+GEN_PINS_QSTR = $(BUILD)/pins_qstr.h
+GEN_PINS_AF_CONST = $(HEADER_BUILD)/pins_af_const.h
+GEN_PINS_AF_PY = $(BUILD)/pins_af.py
+
+ifneq ($(FROZEN_DIR),)
+# To use frozen source modules, put your .py files in a subdirectory (eg scripts/)
+# and then invoke make with FROZEN_DIR=scripts (be sure to build from scratch).
+CFLAGS += -DMICROPY_MODULE_FROZEN_STR
+endif
+
+ifneq ($(FROZEN_MPY_DIR),)
+# To use frozen bytecode, put your .py files in a subdirectory (eg frozen/) and
+# then invoke make with FROZEN_MPY_DIR=frozen (be sure to build from scratch).
+CFLAGS += -DMICROPY_QSTR_EXTRA_POOL=mp_qstr_frozen_const_pool
+CFLAGS += -DMICROPY_MODULE_FROZEN_MPY
+endif
+
+include ../../py/mkrules.mk
+
diff --git a/ports/nrf/README.md b/ports/nrf/README.md
new file mode 100644
index 0000000000..d1c292e7d0
--- /dev/null
+++ b/ports/nrf/README.md
@@ -0,0 +1,144 @@
+# MicroPython Port To The Nordic Semiconductor nRF Series
+
+This is a port of MicroPython to the Nordic Semiconductor nRF series of chips.
+
+## Supported Features
+
+* UART
+* SPI
+* LEDs
+* Pins
+* ADC
+* I2C
+* PWM (nRF52 only)
+* Temperature
+* RTC (Real Time Counter. Low-Power counter)
+* BLE support including:
+  * Peripheral role on nrf51 targets
+  * Central role and Peripheral role on nrf52 targets
+  * _REPL over Bluetooth LE_ (optionally using WebBluetooth)
+  * ubluepy: Bluetooth LE module for MicroPython
+  * 1 non-connectable advertiser while in connection
+
+## Tested Hardware
+
+* nRF51
+  * [micro:bit](http://microbit.org/)
+  * PCA10000 (dongle)
+  * PCA10001
+  * PCA10028
+  * PCA10031 (dongle)
+  * [WT51822-S4AT](http://www.wireless-tag.com/wireless_module/BLE/WT51822-S4AT.html)
+* nRF52832
+  * [PCA10040](http://infocenter.nordicsemi.com/index.jsp?topic=%2Fcom.nordic.infocenter.nrf52%2Fdita%2Fnrf52%2Fdevelopment%2Fnrf52_dev_kit.html) 
+  * [Adafruit Feather nRF52](https://www.adafruit.com/product/3406)
+  * [Thingy:52](http://www.nordicsemi.com/eng/Products/Nordic-Thingy-52)
+  * [Arduino Primo](http://www.arduino.org/products/boards/arduino-primo)
+* nRF52840
+  * [PCA10056](http://www.nordicsemi.com/eng/Products/nRF52840-Preview-DK)
+
+## Compile and Flash
+
+Prerequisite steps for building the nrf port:
+
+    git clone <URL>.git micropython
+    cd micropython
+    git submodule update --init
+    make -C mpy-cross
+
+By default, the PCA10040 (nrf52832) is used as compile target. To build and flash issue the following command inside the ports/nrf/ folder:
+
+    make
+    make flash
+
+Alternatively the target board could be defined:
+
+     make BOARD=pca10040
+     make flash
+     
+## Compile and Flash with Bluetooth Stack
+
+First prepare the bluetooth folder by downloading Bluetooth LE stacks and headers:
+
+     ./drivers/bluetooth/download_ble_stack.sh
+
+If the Bluetooth stacks has been downloaded, compile the target with the following command:
+
+    make BOARD=pca10040 SD=s132
+
+The **make sd** will trigger a flash of the bluetooth stack before that application is flashed. Note that **make sd** will perform a full erase of the chip, which could cause 3rd party bootloaders to also be wiped.
+
+    make BOARD=pca10040 SD=s132 sd
+
+Note: further tuning of features to include in bluetooth or even setting up the device to use REPL over Bluetooth can be configured in the `bluetooth_conf.h`.
+
+## Target Boards and Make Flags
+
+Target Board (BOARD) | Bluetooth Stack (SD)    | Bluetooth Support      | Flash Util
+---------------------|-------------------------|------------------------|-------------------------------
+microbit             | s110                    | Peripheral             | [PyOCD](#pyocdopenocd-targets)
+pca10000             | s110                    | Peripheral             | [Segger](#segger-targets)
+pca10001             | s110                    | Peripheral             | [Segger](#segger-targets)
+pca10028             | s110                    | Peripheral             | [Segger](#segger-targets)
+pca10031             | s110                    | Peripheral             | [Segger](#segger-targets)
+wt51822_s4at         | s110                    | Peripheral             | Manual, see [datasheet](https://4tronix.co.uk/picobot2/WT51822-S4AT.pdf) for pinout
+pca10040             | s132                    | Peripheral and Central | [Segger](#segger-targets)
+feather52            | s132                    | Peripheral and Central | [UART DFU](#dfu-targets)
+arduino_primo        | s132                    | Peripheral and Central | [PyOCD](#pyocdopenocd-targets)
+pca10056             |                         |                        | [Segger](#segger-targets)
+
+## Segger Targets
+
+Install the necessary tools to flash and debug using Segger:
+
+[JLink Download](https://www.segger.com/downloads/jlink#)
+
+[nrfjprog linux-32bit Download](https://www.nordicsemi.com/eng/nordic/download_resource/52615/16/95882111/97746)
+
+[nrfjprog linux-64bit Download](https://www.nordicsemi.com/eng/nordic/download_resource/51386/21/77886419/94917)
+
+[nrfjprog osx Download](https://www.nordicsemi.com/eng/nordic/download_resource/53402/12/97293750/99977)
+
+[nrfjprog win32 Download](https://www.nordicsemi.com/eng/nordic/download_resource/33444/40/22191727/53210)
+
+note: On Linux it might be required to link SEGGER's `libjlinkarm.so` inside nrfjprog's folder.
+
+## PyOCD/OpenOCD Targets
+
+Install the necessary tools to flash and debug using OpenOCD:
+
+    sudo apt-get install openocd
+    sudo pip install pyOCD
+
+## DFU Targets
+
+    sudo apt-get install build-essential libffi-dev pkg-config gcc-arm-none-eabi git python python-pip
+    git clone https://github.com/adafruit/Adafruit_nRF52_Arduino.git
+    cd Adafruit_nRF52_Arduino/tools/nrfutil-0.5.2/
+    sudo pip install -r requirements.txt
+    sudo python setup.py install
+  
+**make flash** and **make sd** will not work with DFU targets. Hence, **dfu-gen** and **dfu-flash** must be used instead.
+* dfu-gen: Generates a Firmware zip to be used by the DFU flash application.
+* dfu-flash: Triggers the DFU flash application to upload the firmware from the generated Firmware zip file. 
+
+Example on how to generate and flash feather52 target:
+
+    make BOARD=feather52 SD=s132
+    make BOARD=feather52 SD=s132 dfu-gen
+    make BOARD=feather52 SD=s132 dfu-flash
+    
+## Bluetooth LE REPL
+
+The port also implements a BLE REPL driver. This feature is disabled by default, as it will deactivate the UART REPL when activated. As some of the nRF devices only have one UART, using the BLE REPL free's the UART instance such that it can be used as a general UART peripheral not bound to REPL.
+
+The configuration can be enabled by editing the `bluetooth_conf.h` and set `MICROPY_PY_BLE_NUS` to 1.
+
+When enabled you have different options to test it:
+* [NUS Console for Linux](https://github.com/tralamazza/nus_console) (recommended)
+* [WebBluetooth REPL](https://glennrub.github.io/webbluetooth/micropython/repl/) (experimental)
+
+Other:
+* nRF UART application for IPhone/Android
+
+WebBluetooth mode can also be configured by editing `bluetooth_conf.h` and set `BLUETOOTH_WEBBLUETOOTH_REPL` to 1. This will alternate advertisement between Eddystone URL and regular connectable advertisement. The Eddystone URL will point the phone or PC to download [WebBluetooth REPL](https://glennrub.github.io/webbluetooth/micropython/repl/) (experimental), which subsequently can be used to connect to the Bluetooth REPL from the PC or Phone browser.
diff --git a/ports/nrf/bluetooth_conf.h b/ports/nrf/bluetooth_conf.h
new file mode 100644
index 0000000000..6a3cbdc83e
--- /dev/null
+++ b/ports/nrf/bluetooth_conf.h
@@ -0,0 +1,37 @@
+#ifndef BLUETOOTH_CONF_H__
+#define BLUETOOTH_CONF_H__
+
+// SD specific configurations.
+
+#if (BLUETOOTH_SD == 110)
+
+#define MICROPY_PY_BLE                  (1)
+#define MICROPY_PY_BLE_NUS              (0)
+#define BLUETOOTH_WEBBLUETOOTH_REPL     (0)
+#define MICROPY_PY_UBLUEPY              (1)
+#define MICROPY_PY_UBLUEPY_PERIPHERAL   (1)
+
+#elif (BLUETOOTH_SD == 132)
+
+#define MICROPY_PY_BLE                  (1)
+#define MICROPY_PY_BLE_NUS              (0)
+#define BLUETOOTH_WEBBLUETOOTH_REPL     (0)
+#define MICROPY_PY_UBLUEPY              (1)
+#define MICROPY_PY_UBLUEPY_PERIPHERAL   (1)
+#define MICROPY_PY_UBLUEPY_CENTRAL      (1)
+
+#else
+#error "SD not supported"
+#endif
+
+// Default defines.
+
+#ifndef MICROPY_PY_BLE
+#define MICROPY_PY_BLE                  (0)
+#endif
+
+#ifndef MICROPY_PY_BLE_NUS
+#define MICROPY_PY_BLE_NUS              (0)
+#endif
+
+#endif
diff --git a/ports/nrf/boards/arduino_primo/mpconfigboard.h b/ports/nrf/boards/arduino_primo/mpconfigboard.h
new file mode 100644
index 0000000000..eec2ba3f78
--- /dev/null
+++ b/ports/nrf/boards/arduino_primo/mpconfigboard.h
@@ -0,0 +1,79 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#define MICROPY_HW_BOARD_NAME       "Arduino Primo"
+#define MICROPY_HW_MCU_NAME         "NRF52832"
+#define MICROPY_PY_SYS_PLATFORM     "nrf52"
+
+#define MICROPY_PY_MACHINE_SOFT_PWM (1)
+#define MICROPY_PY_MUSIC            (1)
+
+#define MICROPY_PY_MACHINE_HW_PWM   (1)
+#define MICROPY_PY_MACHINE_HW_SPI   (1)
+#define MICROPY_PY_MACHINE_TIMER    (1)
+#define MICROPY_PY_MACHINE_RTC      (1)
+#define MICROPY_PY_MACHINE_I2C      (1)
+#define MICROPY_PY_MACHINE_ADC      (1)
+#define MICROPY_PY_MACHINE_TEMP     (1)
+
+#define MICROPY_HW_HAS_LED          (1)
+#define MICROPY_HW_HAS_SWITCH       (0)
+#define MICROPY_HW_HAS_FLASH        (0)
+#define MICROPY_HW_HAS_SDCARD       (0)
+#define MICROPY_HW_HAS_MMA7660      (0)
+#define MICROPY_HW_HAS_LIS3DSH      (0)
+#define MICROPY_HW_HAS_LCD          (0)
+#define MICROPY_HW_ENABLE_RNG       (0)
+#define MICROPY_HW_ENABLE_RTC       (0)
+#define MICROPY_HW_ENABLE_TIMER     (0)
+#define MICROPY_HW_ENABLE_SERVO     (0)
+#define MICROPY_HW_ENABLE_DAC       (0)
+#define MICROPY_HW_ENABLE_CAN       (0)
+
+#define MICROPY_HW_LED_COUNT        (1)
+#define MICROPY_HW_LED_PULLUP       (0)
+
+#define MICROPY_HW_LED1             (20) // LED1
+
+// UART config
+#define MICROPY_HW_UART1_RX         (pin_A11)
+#define MICROPY_HW_UART1_TX         (pin_A12)
+#define MICROPY_HW_UART1_HWFC       (0)
+
+// SPI0 config
+#define MICROPY_HW_SPI0_NAME        "SPI0"
+#define MICROPY_HW_SPI0_SCK         (pin_A25) // (Arduino D13)
+#define MICROPY_HW_SPI0_MOSI        (pin_A23) // (Arduino D11)
+#define MICROPY_HW_SPI0_MISO        (pin_A24) // (Arduino D12)
+
+#define MICROPY_HW_PWM0_NAME        "PWM0"
+#define MICROPY_HW_PWM1_NAME        "PWM1"
+#define MICROPY_HW_PWM2_NAME        "PWM2"
+
+// buzzer pin
+#define MICROPY_HW_MUSIC_PIN        (pin_A8)
+
+#define HELP_TEXT_BOARD_LED         "1"
diff --git a/ports/nrf/boards/arduino_primo/mpconfigboard.mk b/ports/nrf/boards/arduino_primo/mpconfigboard.mk
new file mode 100644
index 0000000000..0be6b3f953
--- /dev/null
+++ b/ports/nrf/boards/arduino_primo/mpconfigboard.mk
@@ -0,0 +1,7 @@
+MCU_SERIES = m4
+MCU_VARIANT = nrf52
+MCU_SUB_VARIANT = nrf52832
+LD_FILE = boards/nrf52832_512k_64k.ld
+FLASHER = pyocd
+
+NRF_DEFINES += -DNRF52832_XXAA
diff --git a/ports/nrf/boards/arduino_primo/mpconfigboard_s132.mk b/ports/nrf/boards/arduino_primo/mpconfigboard_s132.mk
new file mode 100644
index 0000000000..cbbafebfa1
--- /dev/null
+++ b/ports/nrf/boards/arduino_primo/mpconfigboard_s132.mk
@@ -0,0 +1,9 @@
+MCU_SERIES = m4
+MCU_VARIANT = nrf52
+MCU_SUB_VARIANT = nrf52832
+SOFTDEV_VERSION = 3.0.0
+FLASHER=pyocd
+
+LD_FILE = boards/nrf52832_512k_64k_s132_$(SOFTDEV_VERSION).ld
+
+NRF_DEFINES += -DNRF52832_XXAA
diff --git a/ports/nrf/boards/arduino_primo/nrf52_hal_conf.h b/ports/nrf/boards/arduino_primo/nrf52_hal_conf.h
new file mode 100644
index 0000000000..585506b8d6
--- /dev/null
+++ b/ports/nrf/boards/arduino_primo/nrf52_hal_conf.h
@@ -0,0 +1,17 @@
+#ifndef NRF52_HAL_CONF_H__
+#define NRF52_HAL_CONF_H__
+
+#define HAL_UART_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIME_MODULE_ENABLED
+#define HAL_PWM_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_TIMER_MODULE_ENABLED
+#define HAL_TWI_MODULE_ENABLED
+#define HAL_ADCE_MODULE_ENABLED
+#define HAL_TEMP_MODULE_ENABLED
+// #define HAL_UARTE_MODULE_ENABLED
+// #define HAL_SPIE_MODULE_ENABLED
+// #define HAL_TWIE_MODULE_ENABLED
+
+#endif // NRF52_HAL_CONF_H__
diff --git a/ports/nrf/boards/arduino_primo/pins.csv b/ports/nrf/boards/arduino_primo/pins.csv
new file mode 100644
index 0000000000..c177133983
--- /dev/null
+++ b/ports/nrf/boards/arduino_primo/pins.csv
@@ -0,0 +1,30 @@
+PA2,PA2
+PA3,PA3
+PA4,PA4
+PA5,PA5
+PA6,PA6
+PA7,PA7
+PA8,PA8
+PA9,PA9
+PA10,PA10
+PA11,PA11
+PA12,PA12
+PA13,PA13
+PA14,PA14
+PA15,PA15
+PA16,PA16
+PA17,PA17
+PA18,PA18
+PA19,PA19
+PA20,PA20
+PA21,PA21
+PA22,PA22
+PA23,PA23
+PA24,PA24
+PA25,PA25
+PA26,PA26
+PA27,PA27
+PA28,PA28
+PA29,PA29
+PA30,PA30
+PA31,PA31
\ No newline at end of file
diff --git a/ports/nrf/boards/common.ld b/ports/nrf/boards/common.ld
new file mode 100644
index 0000000000..c6e4952b45
--- /dev/null
+++ b/ports/nrf/boards/common.ld
@@ -0,0 +1,103 @@
+/* define output sections */
+SECTIONS
+{
+    /* The startup code goes first into FLASH */
+    .isr_vector :
+    {
+        . = ALIGN(4);
+        KEEP(*(.isr_vector)) /* Startup code */
+
+        . = ALIGN(4);
+    } >FLASH_ISR
+   
+    /* The program code and other data goes into FLASH */
+    .text :
+    {
+        . = ALIGN(4);
+        *(.text)           /* .text sections (code) */
+        *(.text*)          /* .text* sections (code) */
+        *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+        *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    /*  *(.glue_7)   */    /* glue arm to thumb code */
+    /*  *(.glue_7t)  */    /* glue thumb to arm code */
+
+        . = ALIGN(4);
+        _etext = .;        /* define a global symbol at end of code */
+    } >FLASH_TEXT
+     
+    /*
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } >FLASH
+
+    .ARM :
+    {
+        __exidx_start = .;
+        *(.ARM.exidx*)
+        __exidx_end = .;
+    } >FLASH
+    */
+        
+    /* used by the startup to initialize data */
+    _sidata = .;
+        
+    /* This is the initialized data section
+    The program executes knowing that the data is in the RAM
+    but the loader puts the initial values in the FLASH (inidata).
+    It is one task of the startup to copy the initial values from FLASH to RAM. */
+    .data : AT (_sidata)
+    {
+        . = ALIGN(4);
+        _sdata = .;        /* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM */
+        _ram_start = .;    /* create a global symbol at ram start for garbage collector */
+        *(.data)           /* .data sections */
+        *(.data*)          /* .data* sections */
+
+        . = ALIGN(4);
+        _edata = .;        /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */
+    } >RAM 
+            
+    /* Uninitialized data section */
+    .bss :
+    {
+        . = ALIGN(4);
+        _sbss = .;         /* define a global symbol at bss start; used by startup code */
+        *(.bss)
+        *(.bss*)
+        *(COMMON)
+
+        . = ALIGN(4);
+        _ebss = .;         /* define a global symbol at bss end; used by startup code and GC */
+    } >RAM
+
+    /* this is to define the start of the heap, and make sure we have a minimum size */
+    .heap :
+    {
+        . = ALIGN(4);
+	PROVIDE ( end = . );
+	PROVIDE ( _end = . );
+        _heap_start = .;    /* define a global symbol at heap start */
+        . = . + _minimum_heap_size;
+    } >RAM
+
+    /* this just checks there is enough RAM for the stack */
+    .stack :
+    {
+        . = ALIGN(4);
+        . = . + _minimum_stack_size;
+        . = ALIGN(4);
+    } >RAM
+
+    /* Remove information from the standard libraries */
+    /*
+    /DISCARD/ :
+    {
+        libc.a ( * )
+        libm.a ( * )
+        libgcc.a ( * )
+    }
+    */
+
+    .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/ports/nrf/boards/dvk_bl652/mpconfigboard.h b/ports/nrf/boards/dvk_bl652/mpconfigboard.h
new file mode 100644
index 0000000000..1eb9fe5c9a
--- /dev/null
+++ b/ports/nrf/boards/dvk_bl652/mpconfigboard.h
@@ -0,0 +1,78 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#define DVK_BL652
+
+#define MICROPY_HW_BOARD_NAME       "DVK-BL652"
+#define MICROPY_HW_MCU_NAME         "NRF52832"
+#define MICROPY_PY_SYS_PLATFORM     "bl652"
+
+#define MICROPY_PY_MACHINE_PWM      (1)
+#define MICROPY_PY_MACHINE_HW_SPI   (1)
+#define MICROPY_PY_MACHINE_TIMER    (1)
+#define MICROPY_PY_MACHINE_RTC      (1)
+#define MICROPY_PY_MACHINE_I2C      (1)
+#define MICROPY_PY_MACHINE_ADC      (1)
+#define MICROPY_PY_MACHINE_TEMP     (1)
+
+#define MICROPY_HW_HAS_LED          (1)
+#define MICROPY_HW_HAS_SWITCH       (0)
+#define MICROPY_HW_HAS_FLASH        (0)
+#define MICROPY_HW_HAS_SDCARD       (0)
+#define MICROPY_HW_HAS_MMA7660      (0)
+#define MICROPY_HW_HAS_LIS3DSH      (0)
+#define MICROPY_HW_HAS_LCD          (0)
+#define MICROPY_HW_ENABLE_RNG       (0)
+#define MICROPY_HW_ENABLE_RTC       (0)
+#define MICROPY_HW_ENABLE_TIMER     (0)
+#define MICROPY_HW_ENABLE_SERVO     (0)
+#define MICROPY_HW_ENABLE_DAC       (0)
+#define MICROPY_HW_ENABLE_CAN       (0)
+
+#define MICROPY_HW_LED_COUNT        (2)
+#define MICROPY_HW_LED_PULLUP       (0)
+
+#define MICROPY_HW_LED1             (17) // LED1
+#define MICROPY_HW_LED2             (19) // LED2
+
+// UART config
+#define MICROPY_HW_UART1_RX         (pin_A8)
+#define MICROPY_HW_UART1_TX         (pin_A6)
+#define MICROPY_HW_UART1_CTS        (pin_A7)
+#define MICROPY_HW_UART1_RTS        (pin_A5)
+#define MICROPY_HW_UART1_HWFC       (1)
+
+// SPI0 config
+#define MICROPY_HW_SPI0_NAME        "SPI0"
+#define MICROPY_HW_SPI0_SCK         (pin_A25)
+#define MICROPY_HW_SPI0_MOSI        (pin_A23)
+#define MICROPY_HW_SPI0_MISO        (pin_A24)
+
+#define MICROPY_HW_PWM0_NAME        "PWM0"
+#define MICROPY_HW_PWM1_NAME        "PWM1"
+#define MICROPY_HW_PWM2_NAME        "PWM2"
+
+#define HELP_TEXT_BOARD_LED         "1,2"
diff --git a/ports/nrf/boards/dvk_bl652/mpconfigboard.mk b/ports/nrf/boards/dvk_bl652/mpconfigboard.mk
new file mode 100644
index 0000000000..83dbb5ab42
--- /dev/null
+++ b/ports/nrf/boards/dvk_bl652/mpconfigboard.mk
@@ -0,0 +1,6 @@
+MCU_SERIES = m4
+MCU_VARIANT = nrf52
+MCU_SUB_VARIANT = nrf52832
+LD_FILE = boards/nrf52832_512k_64k.ld
+
+NRF_DEFINES += -DNRF52832_XXAA
diff --git a/ports/nrf/boards/dvk_bl652/mpconfigboard_s132.mk b/ports/nrf/boards/dvk_bl652/mpconfigboard_s132.mk
new file mode 100644
index 0000000000..62e3b0f334
--- /dev/null
+++ b/ports/nrf/boards/dvk_bl652/mpconfigboard_s132.mk
@@ -0,0 +1,10 @@
+MCU_SERIES = m4
+MCU_VARIANT = nrf52
+MCU_SUB_VARIANT = nrf52832
+SOFTDEV_VERSION = 3.0.0
+
+LD_FILE = boards/nrf52832_512k_64k_s132_$(SOFTDEV_VERSION).ld
+
+NRF_DEFINES += -DNRF52832_XXAA
+CFLAGS += -DBLUETOOTH_LFCLK_RC
+
diff --git a/ports/nrf/boards/dvk_bl652/nrf52_hal_conf.h b/ports/nrf/boards/dvk_bl652/nrf52_hal_conf.h
new file mode 100644
index 0000000000..fd6073a187
--- /dev/null
+++ b/ports/nrf/boards/dvk_bl652/nrf52_hal_conf.h
@@ -0,0 +1,18 @@
+#ifndef NRF52_HAL_CONF_H__
+#define NRF52_HAL_CONF_H__
+
+#define HAL_UART_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIME_MODULE_ENABLED
+#define HAL_PWM_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_TIMER_MODULE_ENABLED
+#define HAL_TWI_MODULE_ENABLED
+#define HAL_ADCE_MODULE_ENABLED
+#define HAL_TEMP_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+// #define HAL_UARTE_MODULE_ENABLED
+// #define HAL_SPIE_MODULE_ENABLED
+// #define HAL_TWIE_MODULE_ENABLED
+
+#endif // NRF52_HAL_CONF_H__
diff --git a/ports/nrf/boards/dvk_bl652/pins.csv b/ports/nrf/boards/dvk_bl652/pins.csv
new file mode 100644
index 0000000000..126fa5b2f0
--- /dev/null
+++ b/ports/nrf/boards/dvk_bl652/pins.csv
@@ -0,0 +1,31 @@
+PA2,PA2
+PA3,PA3
+PA4,PA4
+UART_RTS,PA5
+UART_TX,PA6
+UART_CTS,PA7
+UART_RX,PA8
+PA9,PA9
+PA10,PA10
+PA11,PA11
+PA12,PA12
+PA13,PA13
+PA14,PA14
+PA15,PA15
+PA16,PA16
+PA17,PA17
+PA18,PA18
+PA19,PA19
+PA20,PA20
+PA21,PA21
+PA22,PA22
+PA23,PA23
+PA24,PA24
+PA25,PA25
+PA26,PA26
+PA27,PA27
+PA28,PA28
+PA29,PA29
+PA30,PA30
+PA31,PA31
+
diff --git a/ports/nrf/boards/feather52/custom_nrf52832_dfu_app.ld b/ports/nrf/boards/feather52/custom_nrf52832_dfu_app.ld
new file mode 100644
index 0000000000..de737e1584
--- /dev/null
+++ b/ports/nrf/boards/feather52/custom_nrf52832_dfu_app.ld
@@ -0,0 +1,27 @@
+/*
+    GNU linker script for NRF52 w/ s132 2.0.1 SoftDevice
+*/
+
+/* Specify the memory areas */
+MEMORY
+{
+    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = 0x080000 /* entire flash, 512 KiB */
+    FLASH_ISR (rx)  : ORIGIN = 0x0001c000, LENGTH = 0x001000 /* sector 0, 4 KiB */
+    FLASH_TEXT (rx) : ORIGIN = 0x0001c400, LENGTH = 0x026c00 /* 152 KiB - APP - ISR */
+    RAM (xrw)       : ORIGIN = 0x200039c0, LENGTH = 0x0c640  /* 49.5 KiB, give 8KiB headroom for softdevice */
+}
+ 
+/* produce a link error if there is not this amount of RAM for these sections */
+_minimum_stack_size = 2K;
+_minimum_heap_size = 16K;
+ 
+/* top end of the stack */
+
+/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*/
+_estack = ORIGIN(RAM) + LENGTH(RAM);
+
+/* RAM extents for the garbage collector */
+_ram_end = ORIGIN(RAM) + LENGTH(RAM);
+_heap_end = 0x20007000; /* tunable */
+
+INCLUDE "boards/common.ld"
diff --git a/ports/nrf/boards/feather52/mpconfigboard.h b/ports/nrf/boards/feather52/mpconfigboard.h
new file mode 100644
index 0000000000..fca9274b79
--- /dev/null
+++ b/ports/nrf/boards/feather52/mpconfigboard.h
@@ -0,0 +1,76 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#define PCA10040
+
+#define MICROPY_HW_BOARD_NAME       "Bluefruit nRF52 Feather"
+#define MICROPY_HW_MCU_NAME         "NRF52832"
+#define MICROPY_PY_SYS_PLATFORM     "nrf52"
+
+#define MICROPY_PY_MACHINE_HW_PWM   (1)
+#define MICROPY_PY_MACHINE_HW_SPI   (1)
+#define MICROPY_PY_MACHINE_TIMER    (1)
+#define MICROPY_PY_MACHINE_RTC      (1)
+#define MICROPY_PY_MACHINE_I2C      (1)
+#define MICROPY_PY_MACHINE_ADC      (1)
+#define MICROPY_PY_MACHINE_TEMP     (1)
+
+#define MICROPY_HW_HAS_LED          (1)
+#define MICROPY_HW_HAS_SWITCH       (0)
+#define MICROPY_HW_HAS_FLASH        (0)
+#define MICROPY_HW_HAS_SDCARD       (0)
+#define MICROPY_HW_HAS_MMA7660      (0)
+#define MICROPY_HW_HAS_LIS3DSH      (0)
+#define MICROPY_HW_HAS_LCD          (0)
+#define MICROPY_HW_ENABLE_RNG       (0)
+#define MICROPY_HW_ENABLE_RTC       (0)
+#define MICROPY_HW_ENABLE_TIMER     (0)
+#define MICROPY_HW_ENABLE_SERVO     (0)
+#define MICROPY_HW_ENABLE_DAC       (0)
+#define MICROPY_HW_ENABLE_CAN       (0)
+
+#define MICROPY_HW_LED_COUNT        (2)
+#define MICROPY_HW_LED_PULLUP       (0)
+
+#define MICROPY_HW_LED1             (17) // LED1
+#define MICROPY_HW_LED2             (19) // LED2
+
+// UART config
+#define MICROPY_HW_UART1_RX         (pin_A8)
+#define MICROPY_HW_UART1_TX         (pin_A6)
+#define MICROPY_HW_UART1_HWFC       (0)
+
+// SPI0 config
+#define MICROPY_HW_SPI0_NAME        "SPI0"
+#define MICROPY_HW_SPI0_SCK         (pin_A12) // (Arduino D13)
+#define MICROPY_HW_SPI0_MOSI        (pin_A13) // (Arduino D11)
+#define MICROPY_HW_SPI0_MISO        (pin_A14) // (Arduino D12)
+
+#define MICROPY_HW_PWM0_NAME        "PWM0"
+#define MICROPY_HW_PWM1_NAME        "PWM1"
+#define MICROPY_HW_PWM2_NAME        "PWM2"
+
+#define HELP_TEXT_BOARD_LED         "1,2"
diff --git a/ports/nrf/boards/feather52/mpconfigboard.mk b/ports/nrf/boards/feather52/mpconfigboard.mk
new file mode 100644
index 0000000000..ce8dcde30d
--- /dev/null
+++ b/ports/nrf/boards/feather52/mpconfigboard.mk
@@ -0,0 +1,25 @@
+MCU_SERIES = m4
+MCU_VARIANT = nrf52
+MCU_SUB_VARIANT = nrf52832
+SOFTDEV_VERSION = 2.0.1
+
+LD_FILE = boards/feather52/custom_nrf52832_dfu_app.ld
+
+NRF_DEFINES += -DNRF52832_XXAA
+
+
+check_defined = \
+    $(strip $(foreach 1,$1, \
+    $(call __check_defined,$1,$(strip $(value 2)))))
+__check_defined = \
+    $(if $(value $1),, \
+    $(error Undefined make flag: $1$(if $2, ($2))))
+
+.PHONY: dfu-gen dfu-flash
+
+dfu-gen:
+	nrfutil dfu genpkg --dev-type 0x0052 --application $(BUILD)/$(OUTPUT_FILENAME).hex $(BUILD)/dfu-package.zip
+
+dfu-flash:
+	@:$(call check_defined, SERIAL, example: SERIAL=/dev/ttyUSB0)
+	sudo nrfutil dfu serial --package $(BUILD)/dfu-package.zip -p $(SERIAL)
diff --git a/ports/nrf/boards/feather52/mpconfigboard_s132.mk b/ports/nrf/boards/feather52/mpconfigboard_s132.mk
new file mode 100644
index 0000000000..ce8dcde30d
--- /dev/null
+++ b/ports/nrf/boards/feather52/mpconfigboard_s132.mk
@@ -0,0 +1,25 @@
+MCU_SERIES = m4
+MCU_VARIANT = nrf52
+MCU_SUB_VARIANT = nrf52832
+SOFTDEV_VERSION = 2.0.1
+
+LD_FILE = boards/feather52/custom_nrf52832_dfu_app.ld
+
+NRF_DEFINES += -DNRF52832_XXAA
+
+
+check_defined = \
+    $(strip $(foreach 1,$1, \
+    $(call __check_defined,$1,$(strip $(value 2)))))
+__check_defined = \
+    $(if $(value $1),, \
+    $(error Undefined make flag: $1$(if $2, ($2))))
+
+.PHONY: dfu-gen dfu-flash
+
+dfu-gen:
+	nrfutil dfu genpkg --dev-type 0x0052 --application $(BUILD)/$(OUTPUT_FILENAME).hex $(BUILD)/dfu-package.zip
+
+dfu-flash:
+	@:$(call check_defined, SERIAL, example: SERIAL=/dev/ttyUSB0)
+	sudo nrfutil dfu serial --package $(BUILD)/dfu-package.zip -p $(SERIAL)
diff --git a/ports/nrf/boards/feather52/nrf52_hal_conf.h b/ports/nrf/boards/feather52/nrf52_hal_conf.h
new file mode 100644
index 0000000000..fd6073a187
--- /dev/null
+++ b/ports/nrf/boards/feather52/nrf52_hal_conf.h
@@ -0,0 +1,18 @@
+#ifndef NRF52_HAL_CONF_H__
+#define NRF52_HAL_CONF_H__
+
+#define HAL_UART_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIME_MODULE_ENABLED
+#define HAL_PWM_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_TIMER_MODULE_ENABLED
+#define HAL_TWI_MODULE_ENABLED
+#define HAL_ADCE_MODULE_ENABLED
+#define HAL_TEMP_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+// #define HAL_UARTE_MODULE_ENABLED
+// #define HAL_SPIE_MODULE_ENABLED
+// #define HAL_TWIE_MODULE_ENABLED
+
+#endif // NRF52_HAL_CONF_H__
diff --git a/ports/nrf/boards/feather52/pins.csv b/ports/nrf/boards/feather52/pins.csv
new file mode 100644
index 0000000000..b7017602a7
--- /dev/null
+++ b/ports/nrf/boards/feather52/pins.csv
@@ -0,0 +1,25 @@
+PA2,PA2,ADC0_IN0
+PA3,PA3,ADC0_IN1
+PA4,PA4,ADC0_IN2
+PA5,PA5,ADC0_IN3
+UART_TX,PA6
+PA7,PA7
+UART_RX,PA8
+NFC1,PA9
+NFC2,PA10
+PA11,PA11
+SPI_SCK,PA12
+SPI_MOSI,PA13
+SPI_MISO,PA14
+PA15,PA15
+PA16,PA16
+LED1,PA17
+LED2,PA19
+PA20,PA20
+I2C_SDA,PA25
+I2C_SCL,PA26
+PA27,PA27
+PA28,PA28,ADC0_IN4
+PA29,PA29,ADC0_IN5
+PA30,PA30,ADC0_IN6
+PA31,PA31,ADC0_IN7
diff --git a/ports/nrf/boards/make-pins.py b/ports/nrf/boards/make-pins.py
new file mode 100644
index 0000000000..733bd8c33c
--- /dev/null
+++ b/ports/nrf/boards/make-pins.py
@@ -0,0 +1,399 @@
+#!/usr/bin/env python
+"""Creates the pin file for the nRF5."""
+
+from __future__ import print_function
+
+import argparse
+import sys
+import csv
+
+SUPPORTED_FN = {
+    'UART'  : ['RX', 'TX', 'CTS', 'RTS']
+}
+
+def parse_port_pin(name_str):
+    """Parses a string and returns a (port-num, pin-num) tuple."""
+    if len(name_str) < 3:
+        raise ValueError("Expecting pin name to be at least 4 charcters.")
+    if name_str[0] != 'P':
+        raise ValueError("Expecting pin name to start with P")
+    if name_str[1] not in ('A', 'B'):
+        raise ValueError("Expecting pin port to be in A or B")
+    port = ord(name_str[1]) - ord('A')
+    pin_str = name_str[2:].split('/')[0]
+    if not pin_str.isdigit():
+        raise ValueError("Expecting numeric pin number.")
+    return (port, int(pin_str))
+
+def split_name_num(name_num):
+    num = None
+    for num_idx in range(len(name_num) - 1, -1, -1):
+        if not name_num[num_idx].isdigit():
+            name = name_num[0:num_idx + 1]
+            num_str = name_num[num_idx + 1:]
+            if len(num_str) > 0:
+                num = int(num_str)
+            break
+    return name, num
+
+
+class AlternateFunction(object):
+    """Holds the information associated with a pins alternate function."""
+
+    def __init__(self, idx, af_str):
+        self.idx = idx
+        self.af_str = af_str
+
+        self.func = ''
+        self.fn_num = None
+        self.pin_type = ''
+        self.supported = False
+
+        af_words = af_str.split('_', 1)
+        self.func, self.fn_num = split_name_num(af_words[0])
+        if len(af_words) > 1:
+            self.pin_type = af_words[1]
+        if self.func in SUPPORTED_FN:
+            pin_types = SUPPORTED_FN[self.func]
+            if self.pin_type in pin_types:
+                self.supported = True
+
+    def is_supported(self):
+        return self.supported
+
+    def ptr(self):
+        """Returns the numbered function (i.e. USART6) for this AF."""
+        if self.fn_num is None:
+            return self.func
+        return '{:s}{:d}'.format(self.func, self.fn_num)
+
+    def mux_name(self):
+        return 'AF{:d}_{:s}'.format(self.idx, self.ptr())
+
+    def print(self):
+        """Prints the C representation of this AF."""
+        if self.supported:
+            print('  AF',  end='')
+        else:
+            print('  //', end='')
+        fn_num = self.fn_num
+        if fn_num is None:
+            fn_num = 0
+        print('({:2d}, {:8s}, {:2d}, {:10s}, {:8s}), // {:s}'.format(self.idx,
+              self.func, fn_num, self.pin_type, self.ptr(), self.af_str))
+
+    def qstr_list(self):
+        return [self.mux_name()]
+
+
+class Pin(object):
+    """Holds the information associated with a pin."""
+
+    def __init__(self, port, pin):
+        self.port = port
+        self.pin = pin
+        self.alt_fn = []
+        self.alt_fn_count = 0
+        self.adc_num = 0
+        self.adc_channel = 0
+        self.board_pin = False
+
+    def port_letter(self):
+        return chr(self.port + ord('A'))
+
+    def cpu_pin_name(self):
+        return '{:s}{:d}'.format(self.port_letter(), self.pin)
+
+    def is_board_pin(self):
+        return self.board_pin
+
+    def set_is_board_pin(self):
+        self.board_pin = True
+
+    def parse_adc(self, adc_str):
+        if (adc_str[:3] != 'ADC'):
+            return
+        (adc,channel) = adc_str.split('_')
+        for idx in range(3, len(adc)):
+            self.adc_num = int(adc[idx])
+        self.adc_channel = int(channel[2:])
+
+    def parse_af(self, af_idx, af_strs_in):
+        if len(af_strs_in) == 0:
+            return
+        # If there is a slash, then the slash separates 2 aliases for the
+        # same alternate function.
+        af_strs = af_strs_in.split('/')
+        for af_str in af_strs:
+            alt_fn = AlternateFunction(af_idx, af_str)
+            self.alt_fn.append(alt_fn)
+            if alt_fn.is_supported():
+                self.alt_fn_count += 1
+
+    def alt_fn_name(self, null_if_0=False):
+        if null_if_0 and self.alt_fn_count == 0:
+            return 'NULL'
+        return 'pin_{:s}_af'.format(self.cpu_pin_name())
+
+    def adc_num_str(self):
+        str = ''
+        for adc_num in range(1,4):
+            if self.adc_num & (1 << (adc_num - 1)):
+                if len(str) > 0:
+                    str += ' | '
+                str += 'PIN_ADC'
+                str += chr(ord('0') + adc_num)
+        if len(str) == 0:
+            str = '0'
+        return str
+
+    def print(self):
+        if self.alt_fn_count == 0:
+            print("// ",  end='')
+        print('const pin_af_obj_t {:s}[] = {{'.format(self.alt_fn_name()))
+        for alt_fn in self.alt_fn:
+            alt_fn.print()
+        if self.alt_fn_count == 0:
+            print("// ",  end='')
+        print('};')
+        print('')
+        print('const pin_obj_t pin_{:s} = PIN({:s}, {:d}, {:s}, {:s}, {:d});'.format(
+            self.cpu_pin_name(), self.port_letter(), self.pin,
+            self.alt_fn_name(null_if_0=True),
+            self.adc_num_str(), self.adc_channel))
+        print('')
+
+    def print_header(self, hdr_file):
+        hdr_file.write('extern const pin_obj_t pin_{:s};\n'.
+                       format(self.cpu_pin_name()))
+        if self.alt_fn_count > 0:
+            hdr_file.write('extern const pin_af_obj_t pin_{:s}_af[];\n'.
+                           format(self.cpu_pin_name()))
+
+    def qstr_list(self):
+        result = []
+        for alt_fn in self.alt_fn:
+            if alt_fn.is_supported():
+                result += alt_fn.qstr_list()
+        return result
+
+
+class NamedPin(object):
+
+    def __init__(self, name, pin):
+        self._name = name
+        self._pin = pin
+
+    def pin(self):
+        return self._pin
+
+    def name(self):
+        return self._name
+
+
+class Pins(object):
+
+    def __init__(self):
+        self.cpu_pins = []   # list of NamedPin objects
+        self.board_pins = [] # list of NamedPin objects
+
+    def find_pin(self, port_num, pin_num):
+        for named_pin in self.cpu_pins:
+            pin = named_pin.pin()
+            if pin.port == port_num and pin.pin == pin_num:
+                return pin
+
+    def parse_af_file(self, filename, pinname_col, af_col, af_col_end):
+        with open(filename, 'r') as csvfile:
+            rows = csv.reader(csvfile)
+            for row in rows:
+                try:
+                    (port_num, pin_num) = parse_port_pin(row[pinname_col])
+                except:
+                    continue
+                pin = Pin(port_num, pin_num)
+                for af_idx in range(af_col, len(row)):
+                    if af_idx < af_col_end:
+                        pin.parse_af(af_idx - af_col, row[af_idx])
+                    elif af_idx == af_col_end:
+                        pin.parse_adc(row[af_idx])
+                self.cpu_pins.append(NamedPin(pin.cpu_pin_name(), pin))
+
+    def parse_board_file(self, filename):
+        with open(filename, 'r') as csvfile:
+            rows = csv.reader(csvfile)
+            for row in rows:
+                try:
+                    (port_num, pin_num) = parse_port_pin(row[1])
+                except:
+                    continue
+                pin = self.find_pin(port_num, pin_num)
+                if pin:
+                    pin.set_is_board_pin()
+                    self.board_pins.append(NamedPin(row[0], pin))
+
+    def print_named(self, label, named_pins):
+        print('STATIC const mp_rom_map_elem_t pin_{:s}_pins_locals_dict_table[] = {{'.format(label))
+        for named_pin in named_pins:
+            pin = named_pin.pin()
+            if pin.is_board_pin():
+                print('  {{ MP_ROM_QSTR(MP_QSTR_{:s}), MP_ROM_PTR(&pin_{:s}) }},'.format(named_pin.name(),  pin.cpu_pin_name()))
+        print('};')
+        print('MP_DEFINE_CONST_DICT(pin_{:s}_pins_locals_dict, pin_{:s}_pins_locals_dict_table);'.format(label, label));
+
+    def print(self):
+        for named_pin in self.cpu_pins:
+            pin = named_pin.pin()
+            if pin.is_board_pin():
+                pin.print()
+        self.print_named('cpu', self.cpu_pins)
+        print('')
+        self.print_named('board', self.board_pins)
+
+    def print_adc(self, adc_num):
+        print('');
+        print('const pin_obj_t * const pin_adc{:d}[] = {{'.format(adc_num))
+        for channel in range(16):
+            adc_found = False
+            for named_pin in self.cpu_pins:
+                pin = named_pin.pin()
+                if (pin.is_board_pin() and
+                    (pin.adc_num & (1 << (adc_num - 1))) and (pin.adc_channel == channel)):
+                    print('  &pin_{:s}, // {:d}'.format(pin.cpu_pin_name(), channel))
+                    adc_found = True
+                    break
+            if not adc_found:
+                print('  NULL,    // {:d}'.format(channel))
+        print('};')
+
+
+    def print_header(self, hdr_filename):
+        with open(hdr_filename, 'wt') as hdr_file:
+            for named_pin in self.cpu_pins:
+                pin = named_pin.pin()
+                if pin.is_board_pin():
+                    pin.print_header(hdr_file)
+            hdr_file.write('extern const pin_obj_t * const pin_adc1[];\n')
+            hdr_file.write('extern const pin_obj_t * const pin_adc2[];\n')
+            hdr_file.write('extern const pin_obj_t * const pin_adc3[];\n')
+
+    def print_qstr(self, qstr_filename):
+        with open(qstr_filename, 'wt') as qstr_file:
+            qstr_set = set([])
+            for named_pin in self.cpu_pins:
+                pin = named_pin.pin()
+                if pin.is_board_pin():
+                    qstr_set |= set(pin.qstr_list())
+                    qstr_set |= set([named_pin.name()])
+            for named_pin in self.board_pins:
+                qstr_set |= set([named_pin.name()])
+            for qstr in sorted(qstr_set):
+                print('Q({})'.format(qstr), file=qstr_file)
+
+
+    def print_af_hdr(self, af_const_filename):
+        with open(af_const_filename,  'wt') as af_const_file:
+            af_hdr_set = set([])
+            mux_name_width = 0
+            for named_pin in self.cpu_pins:
+                pin = named_pin.pin()
+                if pin.is_board_pin():
+                    for af in pin.alt_fn:
+                        if af.is_supported():
+                            mux_name = af.mux_name()
+                            af_hdr_set |= set([mux_name])
+                            if len(mux_name) > mux_name_width:
+                                mux_name_width = len(mux_name)
+            for mux_name in sorted(af_hdr_set):
+                key = 'MP_ROM_QSTR(MP_QSTR_{}),'.format(mux_name)
+                val = 'MP_ROM_INT(GPIO_{})'.format(mux_name)
+                print('    { %-*s %s },' % (mux_name_width + 26, key, val),
+                      file=af_const_file)
+
+    def print_af_py(self, af_py_filename):
+        with open(af_py_filename,  'wt') as af_py_file:
+            print('PINS_AF = (', file=af_py_file);
+            for named_pin in self.board_pins:
+                print("  ('%s', " % named_pin.name(), end='', file=af_py_file)
+                for af in named_pin.pin().alt_fn:
+                    if af.is_supported():
+                        print("(%d, '%s'), " % (af.idx, af.af_str), end='', file=af_py_file)
+                print('),', file=af_py_file)
+            print(')',  file=af_py_file)
+
+
+def main():
+    parser = argparse.ArgumentParser(
+        prog="make-pins.py",
+        usage="%(prog)s [options] [command]",
+        description="Generate board specific pin file"
+    )
+    parser.add_argument(
+        "-a", "--af",
+        dest="af_filename",
+        help="Specifies the alternate function file for the chip",
+        default="nrf.csv"
+    )
+    parser.add_argument(
+        "--af-const",
+        dest="af_const_filename",
+        help="Specifies header file for alternate function constants.",
+        default="build/pins_af_const.h"
+    )
+    parser.add_argument(
+        "--af-py",
+        dest="af_py_filename",
+        help="Specifies the filename for the python alternate function mappings.",
+        default="build/pins_af.py"
+    )
+    parser.add_argument(
+        "-b", "--board",
+        dest="board_filename",
+        help="Specifies the board file",
+    )
+    parser.add_argument(
+        "-p", "--prefix",
+        dest="prefix_filename",
+        help="Specifies beginning portion of generated pins file",
+        default="nrf52_prefix.c"
+    )
+    parser.add_argument(
+        "-q", "--qstr",
+        dest="qstr_filename",
+        help="Specifies name of generated qstr header file",
+        default="build/pins_qstr.h"
+    )
+    parser.add_argument(
+        "-r", "--hdr",
+        dest="hdr_filename",
+        help="Specifies name of generated pin header file",
+        default="build/pins.h"
+    )
+    args = parser.parse_args(sys.argv[1:])
+
+    pins = Pins()
+
+    print('// This file was automatically generated by make-pins.py')
+    print('//')
+    if args.af_filename:
+        print('// --af {:s}'.format(args.af_filename))
+        pins.parse_af_file(args.af_filename, 1, 2, 2)
+
+    if args.board_filename:
+        print('// --board {:s}'.format(args.board_filename))
+        pins.parse_board_file(args.board_filename)
+
+    if args.prefix_filename:
+        print('// --prefix {:s}'.format(args.prefix_filename))
+        print('')
+        with open(args.prefix_filename, 'r') as prefix_file:
+            print(prefix_file.read())
+    pins.print()
+    pins.print_header(args.hdr_filename)
+    pins.print_qstr(args.qstr_filename)
+    pins.print_af_hdr(args.af_const_filename)
+    pins.print_af_py(args.af_py_filename)
+
+
+if __name__ == "__main__":
+    main()
diff --git a/ports/nrf/boards/microbit/mpconfigboard.h b/ports/nrf/boards/microbit/mpconfigboard.h
new file mode 100644
index 0000000000..6dc8b0597f
--- /dev/null
+++ b/ports/nrf/boards/microbit/mpconfigboard.h
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#define PCA10028
+
+#define MICROPY_HW_BOARD_NAME       "micro:bit"
+#define MICROPY_HW_MCU_NAME         "NRF51822"
+#define MICROPY_PY_SYS_PLATFORM     "nrf51"
+
+#define MICROPY_PY_MUSIC            (0)
+#define MICROPY_PY_MACHINE_SOFT_PWM (0)
+#define MICROPY_PY_MACHINE_HW_SPI   (1)
+#define MICROPY_PY_MACHINE_TIMER    (1)
+#define MICROPY_PY_MACHINE_RTC      (1)
+#define MICROPY_PY_MACHINE_I2C      (1)
+#define MICROPY_PY_MACHINE_ADC      (1)
+#define MICROPY_PY_MACHINE_TEMP     (1)
+
+#define MICROPY_HW_HAS_LED          (0)
+#define MICROPY_HW_HAS_SWITCH       (0)
+#define MICROPY_HW_HAS_FLASH        (0)
+#define MICROPY_HW_HAS_SDCARD       (0)
+#define MICROPY_HW_HAS_MMA7660      (0)
+#define MICROPY_HW_HAS_LIS3DSH      (0)
+#define MICROPY_HW_HAS_LCD          (0)
+#define MICROPY_HW_ENABLE_RNG       (0)
+#define MICROPY_HW_ENABLE_RTC       (0)
+#define MICROPY_HW_ENABLE_TIMER     (0)
+#define MICROPY_HW_ENABLE_SERVO     (0)
+#define MICROPY_HW_ENABLE_DAC       (0)
+#define MICROPY_HW_ENABLE_CAN       (0)
+
+// UART config
+#define MICROPY_HW_UART1_RX         (pin_A25)
+#define MICROPY_HW_UART1_TX         (pin_A24)
+#define MICROPY_HW_UART1_HWFC       (0)
+
+// SPI0 config
+#define MICROPY_HW_SPI0_NAME        "SPI0"
+#define MICROPY_HW_SPI0_SCK         (pin_A23)
+#define MICROPY_HW_SPI0_MOSI        (pin_A21)
+#define MICROPY_HW_SPI0_MISO        (pin_A22)
+
+// micro:bit music pin
+#define MICROPY_HW_MUSIC_PIN        (pin_A3)
diff --git a/ports/nrf/boards/microbit/mpconfigboard.mk b/ports/nrf/boards/microbit/mpconfigboard.mk
new file mode 100644
index 0000000000..dd63e22e5d
--- /dev/null
+++ b/ports/nrf/boards/microbit/mpconfigboard.mk
@@ -0,0 +1,5 @@
+MCU_SERIES = m0
+MCU_VARIANT = nrf51
+MCU_SUB_VARIANT = nrf51822
+LD_FILE = boards/nrf51x22_256k_16k.ld
+FLASHER = pyocd
diff --git a/ports/nrf/boards/microbit/mpconfigboard_s110.mk b/ports/nrf/boards/microbit/mpconfigboard_s110.mk
new file mode 100644
index 0000000000..d638b06095
--- /dev/null
+++ b/ports/nrf/boards/microbit/mpconfigboard_s110.mk
@@ -0,0 +1,8 @@
+MCU_SERIES = m0
+MCU_VARIANT = nrf51
+MCU_SUB_VARIANT = nrf51822
+SOFTDEV_VERSION = 8.0.0
+LD_FILE = boards/nrf51x22_256k_16k_s110_$(SOFTDEV_VERSION).ld
+FLASHER = pyocd
+
+CFLAGS += -DBLUETOOTH_LFCLK_RC
diff --git a/ports/nrf/boards/microbit/nrf51_hal_conf.h b/ports/nrf/boards/microbit/nrf51_hal_conf.h
new file mode 100644
index 0000000000..79af193468
--- /dev/null
+++ b/ports/nrf/boards/microbit/nrf51_hal_conf.h
@@ -0,0 +1,14 @@
+#ifndef NRF51_HAL_CONF_H__
+#define NRF51_HAL_CONF_H__
+
+#define HAL_UART_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIME_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_TIMER_MODULE_ENABLED
+#define HAL_TWI_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_TEMP_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+
+#endif // NRF51_HAL_CONF_H__
diff --git a/ports/nrf/boards/microbit/pins.csv b/ports/nrf/boards/microbit/pins.csv
new file mode 100644
index 0000000000..bb118c30a8
--- /dev/null
+++ b/ports/nrf/boards/microbit/pins.csv
@@ -0,0 +1,32 @@
+I2C_SCL,PA0
+PA1,PA1
+PA2,PA2
+PA3,PA3
+PA4,PA4
+PA5,PA5
+PA6,PA6
+PA7,PA7
+UART_RTS,PA8
+UART_TX,PA9
+UART_CTS,PA10
+UART_RX,PA11
+PA12,PA12
+PA13,PA13
+PA14,PA14
+PA15,PA15
+PA16,PA16
+PA17,PA17
+PA18,PA18
+PA19,PA19
+PA20,PA20
+SPI_MOSI,PA21
+SPI_MISO,PA22
+SPI_SCK,PA23
+PA24,PA24
+PA25,PA25
+PA26,PA26
+PA27,PA27
+PA28,PA28
+PA29,PA29
+I2C_SDA,PA30
+PA31,PA31
diff --git a/ports/nrf/boards/nrf51_prefix.c b/ports/nrf/boards/nrf51_prefix.c
new file mode 100644
index 0000000000..a2413fe6bd
--- /dev/null
+++ b/ports/nrf/boards/nrf51_prefix.c
@@ -0,0 +1,31 @@
+// nrf51_prefix.c becomes the initial portion of the generated pins file.
+
+#include <stdio.h>
+
+#include "py/obj.h"
+#include "py/mphal.h"
+#include "pin.h"
+
+#define AF(af_idx, af_fn, af_unit, af_type, af_ptr) \
+{ \
+    { &pin_af_type }, \
+    .name = MP_QSTR_AF ## af_idx ## _ ## af_fn ## af_unit, \
+    .idx = (af_idx), \
+    .fn = AF_FN_ ## af_fn, \
+    .unit = (af_unit), \
+    .type = AF_PIN_TYPE_ ## af_fn ## _ ## af_type, \
+    .af_fn = (af_ptr) \
+}
+
+#define PIN(p_port, p_pin, p_af, p_adc_num, p_adc_channel) \
+{ \
+    { &pin_type }, \
+    .name = MP_QSTR_ ## p_port ## p_pin, \
+    .port = PORT_ ## p_port, \
+    .pin = (p_pin), \
+    .num_af = (sizeof(p_af) / sizeof(pin_af_obj_t)), \
+    .pin_mask = (1 << p_pin), \
+    .af = p_af, \
+    .adc_num = p_adc_num, \
+    .adc_channel = p_adc_channel, \
+}
diff --git a/ports/nrf/boards/nrf51x22_256k_16k.ld b/ports/nrf/boards/nrf51x22_256k_16k.ld
new file mode 100644
index 0000000000..e25ae3b874
--- /dev/null
+++ b/ports/nrf/boards/nrf51x22_256k_16k.ld
@@ -0,0 +1,28 @@
+/*
+    GNU linker script for NRF52 blank w/ no SoftDevice
+*/
+/* Specify the memory areas */
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lnosys)
+MEMORY
+{
+    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = 0x040000 /* entire flash, 256 KiB */
+    FLASH_ISR (rx)  : ORIGIN = 0x00000000, LENGTH = 0x000400 /* sector 0, 1 KiB */
+    FLASH_TEXT (rx) : ORIGIN = 0x00000400, LENGTH = 0x03FC00 /* 255 KiB */
+    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 0x004000 /* 16 KiB */
+}
+ 
+/* produce a link error if there is not this amount of RAM for these sections */
+_minimum_stack_size = 4K;
+_minimum_heap_size = 8K;
+ 
+/* top end of the stack */
+
+/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*/
+_estack = ORIGIN(RAM) + LENGTH(RAM);
+
+/* RAM extents for the garbage collector */
+_ram_end = ORIGIN(RAM) + LENGTH(RAM);
+_heap_end = 0x20002000; /* tunable */
+
+INCLUDE "boards/common.ld"
diff --git a/ports/nrf/boards/nrf51x22_256k_16k_s110_8.0.0.ld b/ports/nrf/boards/nrf51x22_256k_16k_s110_8.0.0.ld
new file mode 100644
index 0000000000..aa5ff3f838
--- /dev/null
+++ b/ports/nrf/boards/nrf51x22_256k_16k_s110_8.0.0.ld
@@ -0,0 +1,28 @@
+/*
+    GNU linker script for NRF51822 AA w/ S110 8.0.0 SoftDevice
+*/
+/* Specify the memory areas */
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lnosys)
+MEMORY
+{
+    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = 0x040000 /* entire flash, 256 KiB */
+    FLASH_ISR (rx)  : ORIGIN = 0x00018000, LENGTH = 0x000400 /* sector 0, 1 KiB */
+    FLASH_TEXT (rx) : ORIGIN = 0x00018400, LENGTH = 0x027c00 /* 159 KiB */
+    RAM (xrw)       : ORIGIN = 0x20002000, LENGTH = 0x002000 /* 8 KiB */
+}
+
+/* produce a link error if there is not this amount of RAM for these sections */
+_minimum_stack_size = 2K;
+_minimum_heap_size = 1K;
+
+/* top end of the stack */
+
+/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*/
+_estack = ORIGIN(RAM) + LENGTH(RAM);
+
+/* RAM extents for the garbage collector */
+_ram_end = ORIGIN(RAM) + LENGTH(RAM);
+_heap_end = 0x20003c00; /* tunable */
+
+INCLUDE "boards/common.ld"
diff --git a/ports/nrf/boards/nrf51x22_256k_32k.ld b/ports/nrf/boards/nrf51x22_256k_32k.ld
new file mode 100644
index 0000000000..28f8068420
--- /dev/null
+++ b/ports/nrf/boards/nrf51x22_256k_32k.ld
@@ -0,0 +1,28 @@
+/*
+    GNU linker script for NRF52 blank w/ no SoftDevice
+*/
+/* Specify the memory areas */
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lnosys)
+MEMORY
+{
+    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = 0x040000 /* entire flash, 256 KiB */
+    FLASH_ISR (rx)  : ORIGIN = 0x00000000, LENGTH = 0x000400 /* sector 0, 1 KiB */
+    FLASH_TEXT (rx) : ORIGIN = 0x00000400, LENGTH = 0x03F000 /* 255 KiB */
+    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 0x008000 /* 32 KiB */
+}
+ 
+/* produce a link error if there is not this amount of RAM for these sections */
+_minimum_stack_size = 4K;
+_minimum_heap_size = 24K;
+ 
+/* top end of the stack */
+
+/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*/
+_estack = ORIGIN(RAM) + LENGTH(RAM);
+
+/* RAM extents for the garbage collector */
+_ram_end = ORIGIN(RAM) + LENGTH(RAM);
+_heap_end = 0x20006000; /* tunable */
+
+INCLUDE "boards/common.ld"
diff --git a/ports/nrf/boards/nrf51x22_256k_32k_s110_8.0.0.ld b/ports/nrf/boards/nrf51x22_256k_32k_s110_8.0.0.ld
new file mode 100644
index 0000000000..adee5b4bc9
--- /dev/null
+++ b/ports/nrf/boards/nrf51x22_256k_32k_s110_8.0.0.ld
@@ -0,0 +1,28 @@
+/*
+    GNU linker script for NRF51822 AC w/ S110 8.0.0 SoftDevice
+*/
+/* Specify the memory areas */
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lnosys)
+MEMORY
+{
+    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = 0x040000 /* entire flash, 256 KiB */
+    FLASH_ISR (rx)  : ORIGIN = 0x00018000, LENGTH = 0x000400 /* sector 0, 1 KiB */
+    FLASH_TEXT (rx) : ORIGIN = 0x00018400, LENGTH = 0x027c00 /* 159 KiB */
+    RAM (xrw)       : ORIGIN = 0x20002000, LENGTH = 0x006000 /* 24 KiB */
+}
+ 
+/* produce a link error if there is not this amount of RAM for these sections */
+_minimum_stack_size = 2K;
+_minimum_heap_size = 1K;
+ 
+/* top end of the stack */
+
+/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*/
+_estack = ORIGIN(RAM) + LENGTH(RAM);
+
+/* RAM extents for the garbage collector */
+_ram_end = ORIGIN(RAM) + LENGTH(RAM);
+_heap_end = 0x20005000; /* tunable */
+
+INCLUDE "boards/common.ld"
diff --git a/ports/nrf/boards/nrf51x22_256k_32k_s120_2.1.0.ld b/ports/nrf/boards/nrf51x22_256k_32k_s120_2.1.0.ld
new file mode 100644
index 0000000000..3de7083fd7
--- /dev/null
+++ b/ports/nrf/boards/nrf51x22_256k_32k_s120_2.1.0.ld
@@ -0,0 +1,28 @@
+/*
+    GNU linker script for NRF51822 AC w/ S120 2.1.0 SoftDevice
+*/
+/* Specify the memory areas */
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lnosys)
+MEMORY
+{
+    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = 0x040000 /* entire flash, 256 KiB */
+    FLASH_ISR (rx)  : ORIGIN = 0x0001D000, LENGTH = 0x000400 /* sector 0, 1 KiB */
+    FLASH_TEXT (rx) : ORIGIN = 0x0001D400, LENGTH = 0x022c00 /* 139 KiB */
+    RAM (xrw)       : ORIGIN = 0x20002800, LENGTH = 0x005800 /* 22 KiB */
+}
+ 
+/* produce a link error if there is not this amount of RAM for these sections */
+_minimum_stack_size = 2K;
+_minimum_heap_size = 4K;
+ 
+/* top end of the stack */
+
+/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*/
+_estack = ORIGIN(RAM) + LENGTH(RAM);
+
+/* RAM extents for the garbage collector */
+_ram_end = ORIGIN(RAM) + LENGTH(RAM);
+_heap_end = 0x20003000; /* tunable */
+
+INCLUDE "boards/common.ld"
diff --git a/ports/nrf/boards/nrf51x22_256k_32k_s130_2.0.1.ld b/ports/nrf/boards/nrf51x22_256k_32k_s130_2.0.1.ld
new file mode 100644
index 0000000000..1845f973ff
--- /dev/null
+++ b/ports/nrf/boards/nrf51x22_256k_32k_s130_2.0.1.ld
@@ -0,0 +1,28 @@
+/*
+    GNU linker script for NRF51822 AC w/ S130 2.0.1 SoftDevice
+*/
+/* Specify the memory areas */
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lnosys)
+MEMORY
+{
+    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = 0x040000 /* entire flash, 256 KiB */
+    FLASH_ISR (rx)  : ORIGIN = 0x0001b000, LENGTH = 0x000400 /* sector 0, 1 KiB */
+    FLASH_TEXT (rx) : ORIGIN = 0x0001b400, LENGTH = 0x024c00 /* 147 KiB */
+    RAM (xrw)       : ORIGIN = 0x200013c8, LENGTH = 0x006c38 /* 27 KiB */
+}
+ 
+/* produce a link error if there is not this amount of RAM for these sections */
+_minimum_stack_size = 2K;
+_minimum_heap_size = 6K;
+ 
+/* top end of the stack */
+
+/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*/
+_estack = ORIGIN(RAM) + LENGTH(RAM);
+
+/* RAM extents for the garbage collector */
+_ram_end = ORIGIN(RAM) + LENGTH(RAM);
+_heap_end = 0x20002000; /* tunable */
+
+INCLUDE "boards/common.ld"
diff --git a/ports/nrf/boards/nrf52832_512k_64k.ld b/ports/nrf/boards/nrf52832_512k_64k.ld
new file mode 100644
index 0000000000..afd7d359f8
--- /dev/null
+++ b/ports/nrf/boards/nrf52832_512k_64k.ld
@@ -0,0 +1,27 @@
+/*
+    GNU linker script for NRF52832 blank w/ no SoftDevice
+*/
+
+/* Specify the memory areas */
+MEMORY
+{
+    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = 0x080000 /* entire flash, 512 KiB */
+    FLASH_ISR (rx)  : ORIGIN = 0x00000000, LENGTH = 0x001000 /* sector 0, 4 KiB */
+    FLASH_TEXT (rx) : ORIGIN = 0x00001000, LENGTH = 0x07F000 /* 508 KiB */
+    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 0x010000 /* 64 KiB */
+}
+ 
+/* produce a link error if there is not this amount of RAM for these sections */
+_minimum_stack_size = 2K;
+_minimum_heap_size = 32K;
+ 
+/* top end of the stack */
+
+/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*/
+_estack = ORIGIN(RAM) + LENGTH(RAM);
+
+/* RAM extents for the garbage collector */
+_ram_end = ORIGIN(RAM) + LENGTH(RAM);
+_heap_end = 0x20008000; /* tunable */
+
+INCLUDE "boards/common.ld"
diff --git a/ports/nrf/boards/nrf52832_512k_64k_s132_2.0.1.ld b/ports/nrf/boards/nrf52832_512k_64k_s132_2.0.1.ld
new file mode 100644
index 0000000000..05e1daa896
--- /dev/null
+++ b/ports/nrf/boards/nrf52832_512k_64k_s132_2.0.1.ld
@@ -0,0 +1,27 @@
+/*
+    GNU linker script for NRF52 w/ s132 2.0.1 SoftDevice
+*/
+
+/* Specify the memory areas */
+MEMORY
+{
+    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = 0x080000 /* entire flash, 512 KiB */
+    FLASH_ISR (rx)  : ORIGIN = 0x0001c000, LENGTH = 0x001000 /* sector 0, 4 KiB */
+    FLASH_TEXT (rx) : ORIGIN = 0x0001d000, LENGTH = 0x060000 /* 396 KiB */
+    RAM (xrw)       : ORIGIN = 0x200039c0, LENGTH = 0x0c640  /* 49.5 KiB, give 8KiB headroom for softdevice */
+}
+ 
+/* produce a link error if there is not this amount of RAM for these sections */
+_minimum_stack_size = 2K;
+_minimum_heap_size = 16K;
+ 
+/* top end of the stack */
+
+/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*/
+_estack = ORIGIN(RAM) + LENGTH(RAM);
+
+/* RAM extents for the garbage collector */
+_ram_end = ORIGIN(RAM) + LENGTH(RAM);
+_heap_end = 0x20007000; /* tunable */
+
+INCLUDE "boards/common.ld"
diff --git a/ports/nrf/boards/nrf52832_512k_64k_s132_3.0.0.ld b/ports/nrf/boards/nrf52832_512k_64k_s132_3.0.0.ld
new file mode 100644
index 0000000000..159c159b2c
--- /dev/null
+++ b/ports/nrf/boards/nrf52832_512k_64k_s132_3.0.0.ld
@@ -0,0 +1,27 @@
+/*
+    GNU linker script for NRF52 w/ s132 3.0.0 SoftDevice
+*/
+
+/* Specify the memory areas */
+MEMORY
+{
+    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = 0x080000 /* entire flash, 512 KiB */
+    FLASH_ISR (rx)  : ORIGIN = 0x0001f000, LENGTH = 0x001000 /* sector 0, 4 KiB */
+    FLASH_TEXT (rx) : ORIGIN = 0x00020000, LENGTH = 0x060000 /* 396 KiB */
+    RAM (xrw)       : ORIGIN = 0x200039c0, LENGTH = 0x0c640  /* 49.5 KiB, give 8KiB headroom for softdevice */
+}
+ 
+/* produce a link error if there is not this amount of RAM for these sections */
+_minimum_stack_size = 2K;
+_minimum_heap_size = 16K;
+ 
+/* top end of the stack */
+
+/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*/
+_estack = ORIGIN(RAM) + LENGTH(RAM);
+
+/* RAM extents for the garbage collector */
+_ram_end = ORIGIN(RAM) + LENGTH(RAM);
+_heap_end = 0x20007000; /* tunable */
+
+INCLUDE "boards/common.ld"
diff --git a/ports/nrf/boards/nrf52840_1M_256k.ld b/ports/nrf/boards/nrf52840_1M_256k.ld
new file mode 100644
index 0000000000..43b4458315
--- /dev/null
+++ b/ports/nrf/boards/nrf52840_1M_256k.ld
@@ -0,0 +1,27 @@
+/*
+    GNU linker script for NRF52840 blank w/ no SoftDevice
+*/
+
+/* Specify the memory areas */
+MEMORY
+{
+    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = 0x100000 /* entire flash, 1 MiB */
+    FLASH_ISR (rx)  : ORIGIN = 0x00000000, LENGTH = 0x001000 /* sector 0, 4 KiB */
+    FLASH_TEXT (rx) : ORIGIN = 0x00001000, LENGTH = 0x0FF000 /* 1020 KiB */
+    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 0x040000 /* 256 KiB */
+}
+
+/* produce a link error if there is not this amount of RAM for these sections */
+_minimum_stack_size = 40K;
+_minimum_heap_size = 128K;
+ 
+/* top end of the stack */
+
+/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*/
+_estack = ORIGIN(RAM) + LENGTH(RAM);
+
+/* RAM extents for the garbage collector */
+_ram_end = ORIGIN(RAM) + LENGTH(RAM);
+_heap_end = 0x20020000; /* tunable */
+
+INCLUDE "boards/common.ld"
diff --git a/ports/nrf/boards/nrf52_prefix.c b/ports/nrf/boards/nrf52_prefix.c
new file mode 100644
index 0000000000..89e5df5b10
--- /dev/null
+++ b/ports/nrf/boards/nrf52_prefix.c
@@ -0,0 +1,31 @@
+// nrf52_prefix.c becomes the initial portion of the generated pins file.
+
+#include <stdio.h>
+
+#include "py/obj.h"
+#include "py/mphal.h"
+#include "pin.h"
+
+#define AF(af_idx, af_fn, af_unit, af_type, af_ptr) \
+{ \
+    { &pin_af_type }, \
+    .name = MP_QSTR_AF ## af_idx ## _ ## af_fn ## af_unit, \
+    .idx = (af_idx), \
+    .fn = AF_FN_ ## af_fn, \
+    .unit = (af_unit), \
+    .type = AF_PIN_TYPE_ ## af_fn ## _ ## af_type, \
+    .af_fn = (af_ptr) \
+}
+
+#define PIN(p_port, p_pin, p_af, p_adc_num, p_adc_channel) \
+{ \
+    { &pin_type }, \
+    .name = MP_QSTR_ ## p_port ## p_pin, \
+    .port = PORT_ ## p_port, \
+    .pin = (p_pin), \
+    .num_af = (sizeof(p_af) / sizeof(pin_af_obj_t)), \
+    .pin_mask = (1 << p_pin), \
+    .af = p_af, \
+    .adc_num = p_adc_num, \
+    .adc_channel = p_adc_channel, \
+}
diff --git a/ports/nrf/boards/pca10000/mpconfigboard.h b/ports/nrf/boards/pca10000/mpconfigboard.h
new file mode 100644
index 0000000000..75932a4937
--- /dev/null
+++ b/ports/nrf/boards/pca10000/mpconfigboard.h
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#define PCA10000
+
+#define MICROPY_HW_BOARD_NAME       "PCA10000"
+#define MICROPY_HW_MCU_NAME         "NRF51822"
+#define MICROPY_PY_SYS_PLATFORM     "nrf51-dongle"
+
+#define MICROPY_PY_MACHINE_HW_SPI   (0)
+#define MICROPY_PY_MACHINE_TIMER    (1)
+#define MICROPY_PY_MACHINE_RTC      (1)
+#define MICROPY_PY_MACHINE_I2C      (0)
+#define MICROPY_PY_MACHINE_ADC      (0)
+#define MICROPY_PY_MACHINE_TEMP     (1)
+
+#define MICROPY_HW_HAS_LED          (1)
+#define MICROPY_HW_HAS_SWITCH       (0)
+#define MICROPY_HW_HAS_FLASH        (0)
+#define MICROPY_HW_HAS_SDCARD       (0)
+#define MICROPY_HW_HAS_MMA7660      (0)
+#define MICROPY_HW_HAS_LIS3DSH      (0)
+#define MICROPY_HW_HAS_LCD          (0)
+#define MICROPY_HW_ENABLE_RNG       (0)
+#define MICROPY_HW_ENABLE_RTC       (0)
+#define MICROPY_HW_ENABLE_TIMER     (0)
+#define MICROPY_HW_ENABLE_SERVO     (0)
+#define MICROPY_HW_ENABLE_DAC       (0)
+#define MICROPY_HW_ENABLE_CAN       (0)
+
+#define MICROPY_HW_LED_TRICOLOR     (1)
+#define MICROPY_HW_LED_PULLUP       (1)
+
+#define MICROPY_HW_LED_RED          (21) // RED
+#define MICROPY_HW_LED_GREEN        (22) // GREEN
+#define MICROPY_HW_LED_BLUE         (23) // BLUE
+
+// UART config
+#define MICROPY_HW_UART1_RX         (pin_A11)
+#define MICROPY_HW_UART1_TX         (pin_A9)
+#define MICROPY_HW_UART1_HWFC       (0)
+
+#define HELP_TEXT_BOARD_LED         "1,2,3"
diff --git a/ports/nrf/boards/pca10000/mpconfigboard.mk b/ports/nrf/boards/pca10000/mpconfigboard.mk
new file mode 100644
index 0000000000..12087d6828
--- /dev/null
+++ b/ports/nrf/boards/pca10000/mpconfigboard.mk
@@ -0,0 +1,4 @@
+MCU_SERIES = m0
+MCU_VARIANT = nrf51
+MCU_SUB_VARIANT = nrf51822
+LD_FILE = boards/nrf51x22_256k_16k.ld
diff --git a/ports/nrf/boards/pca10000/mpconfigboard_s110.mk b/ports/nrf/boards/pca10000/mpconfigboard_s110.mk
new file mode 100644
index 0000000000..5cd9966f9c
--- /dev/null
+++ b/ports/nrf/boards/pca10000/mpconfigboard_s110.mk
@@ -0,0 +1,5 @@
+MCU_SERIES = m0
+MCU_VARIANT = nrf51
+MCU_SUB_VARIANT = nrf51822
+SOFTDEV_VERSION = 8.0.0
+LD_FILE = boards/nrf51x22_256k_16k_s110_$(SOFTDEV_VERSION).ld
diff --git a/ports/nrf/boards/pca10000/nrf51_hal_conf.h b/ports/nrf/boards/pca10000/nrf51_hal_conf.h
new file mode 100644
index 0000000000..64d48b14eb
--- /dev/null
+++ b/ports/nrf/boards/pca10000/nrf51_hal_conf.h
@@ -0,0 +1,11 @@
+#ifndef NRF51_HAL_CONF_H__
+#define NRF51_HAL_CONF_H__
+
+#define HAL_UART_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_TIMER_MODULE_ENABLED
+#define HAL_TIME_MODULE_ENABLED
+#define HAL_TEMP_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+
+#endif // NRF51_HAL_CONF_H__
diff --git a/ports/nrf/boards/pca10000/pins.csv b/ports/nrf/boards/pca10000/pins.csv
new file mode 100644
index 0000000000..cc3f62db1a
--- /dev/null
+++ b/ports/nrf/boards/pca10000/pins.csv
@@ -0,0 +1,7 @@
+UART_RTS,PA8
+UART_TX,PA9
+UART_CTS,PA10
+UART_RX,PA11
+LED_RED,PA21
+LED_GREEN,PA22
+LED_BLUE,PA23
\ No newline at end of file
diff --git a/ports/nrf/boards/pca10001/mpconfigboard.h b/ports/nrf/boards/pca10001/mpconfigboard.h
new file mode 100644
index 0000000000..e2320752ae
--- /dev/null
+++ b/ports/nrf/boards/pca10001/mpconfigboard.h
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#define PCA10001
+
+#define MICROPY_HW_BOARD_NAME       "PCA10001"
+#define MICROPY_HW_MCU_NAME         "NRF51822"
+#define MICROPY_PY_SYS_PLATFORM     "nrf51-DK"
+
+#define MICROPY_PY_MACHINE_HW_SPI   (0)
+#define MICROPY_PY_MACHINE_TIMER    (1)
+#define MICROPY_PY_MACHINE_RTC      (1)
+#define MICROPY_PY_MACHINE_I2C      (1)
+#define MICROPY_PY_MACHINE_ADC      (1)
+#define MICROPY_PY_MACHINE_TEMP     (1)
+
+#define MICROPY_HW_HAS_LED          (1)
+#define MICROPY_HW_HAS_SWITCH       (0)
+#define MICROPY_HW_HAS_FLASH        (0)
+#define MICROPY_HW_HAS_SDCARD       (0)
+#define MICROPY_HW_HAS_MMA7660      (0)
+#define MICROPY_HW_HAS_LIS3DSH      (0)
+#define MICROPY_HW_HAS_LCD          (0)
+#define MICROPY_HW_ENABLE_RNG       (0)
+#define MICROPY_HW_ENABLE_RTC       (0)
+#define MICROPY_HW_ENABLE_TIMER     (0)
+#define MICROPY_HW_ENABLE_SERVO     (0)
+#define MICROPY_HW_ENABLE_DAC       (0)
+#define MICROPY_HW_ENABLE_CAN       (0)
+
+
+#define MICROPY_HW_LED_COUNT        (2)
+#define MICROPY_HW_LED_PULLUP       (0)
+
+#define MICROPY_HW_LED1             (18) // LED1
+#define MICROPY_HW_LED2             (19) // LED2
+
+// UART config
+#define MICROPY_HW_UART1_RX         (pin_A11)
+#define MICROPY_HW_UART1_TX         (pin_A9)
+#define MICROPY_HW_UART1_CTS        (pin_A10)
+#define MICROPY_HW_UART1_RTS        (pin_A8)
+#define MICROPY_HW_UART1_HWFC       (0)
+
+#define HELP_TEXT_BOARD_LED         "1,2"
diff --git a/ports/nrf/boards/pca10001/mpconfigboard.mk b/ports/nrf/boards/pca10001/mpconfigboard.mk
new file mode 100644
index 0000000000..12087d6828
--- /dev/null
+++ b/ports/nrf/boards/pca10001/mpconfigboard.mk
@@ -0,0 +1,4 @@
+MCU_SERIES = m0
+MCU_VARIANT = nrf51
+MCU_SUB_VARIANT = nrf51822
+LD_FILE = boards/nrf51x22_256k_16k.ld
diff --git a/ports/nrf/boards/pca10001/mpconfigboard_s110.mk b/ports/nrf/boards/pca10001/mpconfigboard_s110.mk
new file mode 100644
index 0000000000..5cd9966f9c
--- /dev/null
+++ b/ports/nrf/boards/pca10001/mpconfigboard_s110.mk
@@ -0,0 +1,5 @@
+MCU_SERIES = m0
+MCU_VARIANT = nrf51
+MCU_SUB_VARIANT = nrf51822
+SOFTDEV_VERSION = 8.0.0
+LD_FILE = boards/nrf51x22_256k_16k_s110_$(SOFTDEV_VERSION).ld
diff --git a/ports/nrf/boards/pca10001/nrf51_hal_conf.h b/ports/nrf/boards/pca10001/nrf51_hal_conf.h
new file mode 100644
index 0000000000..79af193468
--- /dev/null
+++ b/ports/nrf/boards/pca10001/nrf51_hal_conf.h
@@ -0,0 +1,14 @@
+#ifndef NRF51_HAL_CONF_H__
+#define NRF51_HAL_CONF_H__
+
+#define HAL_UART_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIME_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_TIMER_MODULE_ENABLED
+#define HAL_TWI_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_TEMP_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+
+#endif // NRF51_HAL_CONF_H__
diff --git a/ports/nrf/boards/pca10001/pins.csv b/ports/nrf/boards/pca10001/pins.csv
new file mode 100644
index 0000000000..2b16969869
--- /dev/null
+++ b/ports/nrf/boards/pca10001/pins.csv
@@ -0,0 +1,32 @@
+PA0,PA0
+PA1,PA1
+PA2,PA2
+PA3,PA3
+PA4,PA4
+PA5,PA5
+PA6,PA6
+PA7,PA7
+UART_RTS,PA8
+UART_TX,PA9
+UART_CTS,PA10
+UART_RX,PA11
+PA12,PA12
+PA13,PA13
+PA14,PA14
+PA15,PA15
+PA16,PA16
+PA17,PA17
+PA18,PA18
+PA19,PA19
+PA20,PA20
+PA21,PA21
+PA22,PA22
+PA23,PA23
+PA24,PA24
+PA25,PA25
+PA26,PA26
+PA27,PA27
+PA28,PA28
+PA29,PA29
+PA30,PA30
+PA31,PA31
\ No newline at end of file
diff --git a/ports/nrf/boards/pca10028/mpconfigboard.h b/ports/nrf/boards/pca10028/mpconfigboard.h
new file mode 100644
index 0000000000..3c557bdb49
--- /dev/null
+++ b/ports/nrf/boards/pca10028/mpconfigboard.h
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#define PCA10028
+
+#define MICROPY_HW_BOARD_NAME       "PCA10028"
+#define MICROPY_HW_MCU_NAME         "NRF51822"
+#define MICROPY_PY_SYS_PLATFORM     "nrf51-DK"
+
+#define MICROPY_PY_MACHINE_HW_SPI   (1)
+#define MICROPY_PY_MACHINE_TIMER    (1)
+#define MICROPY_PY_MACHINE_RTC      (1)
+#define MICROPY_PY_MACHINE_I2C      (1)
+#define MICROPY_PY_MACHINE_ADC      (1)
+#define MICROPY_PY_MACHINE_TEMP     (1)
+
+#define MICROPY_HW_HAS_LED          (1)
+#define MICROPY_HW_HAS_SWITCH       (0)
+#define MICROPY_HW_HAS_FLASH        (0)
+#define MICROPY_HW_HAS_SDCARD       (0)
+#define MICROPY_HW_HAS_MMA7660      (0)
+#define MICROPY_HW_HAS_LIS3DSH      (0)
+#define MICROPY_HW_HAS_LCD          (0)
+#define MICROPY_HW_ENABLE_RNG       (0)
+#define MICROPY_HW_ENABLE_RTC       (0)
+#define MICROPY_HW_ENABLE_TIMER     (0)
+#define MICROPY_HW_ENABLE_SERVO     (0)
+#define MICROPY_HW_ENABLE_DAC       (0)
+#define MICROPY_HW_ENABLE_CAN       (0)
+
+#define MICROPY_HW_LED_COUNT        (4)
+#define MICROPY_HW_LED_PULLUP       (1)
+
+#define MICROPY_HW_LED1             (21) // LED1
+#define MICROPY_HW_LED2             (22) // LED2
+#define MICROPY_HW_LED3             (23) // LED3
+#define MICROPY_HW_LED4             (24) // LED4
+
+// UART config
+#define MICROPY_HW_UART1_RX         (pin_A11)
+#define MICROPY_HW_UART1_TX         (pin_A9)
+#define MICROPY_HW_UART1_CTS        (pin_A10)
+#define MICROPY_HW_UART1_RTS        (pin_A8)
+#define MICROPY_HW_UART1_HWFC       (1)
+
+// SPI0 config
+#define MICROPY_HW_SPI0_NAME        "SPI0"
+#define MICROPY_HW_SPI0_SCK         (pin_A29)
+#define MICROPY_HW_SPI0_MOSI        (pin_A25)
+#define MICROPY_HW_SPI0_MISO        (pin_A28)
+
+#define HELP_TEXT_BOARD_LED         "1,2,3,4"
diff --git a/ports/nrf/boards/pca10028/mpconfigboard.mk b/ports/nrf/boards/pca10028/mpconfigboard.mk
new file mode 100644
index 0000000000..29e76d94a9
--- /dev/null
+++ b/ports/nrf/boards/pca10028/mpconfigboard.mk
@@ -0,0 +1,4 @@
+MCU_SERIES = m0
+MCU_VARIANT = nrf51
+MCU_SUB_VARIANT = nrf51822
+LD_FILE = boards/nrf51x22_256k_32k.ld
diff --git a/ports/nrf/boards/pca10028/mpconfigboard_s110.mk b/ports/nrf/boards/pca10028/mpconfigboard_s110.mk
new file mode 100644
index 0000000000..6afc1466f4
--- /dev/null
+++ b/ports/nrf/boards/pca10028/mpconfigboard_s110.mk
@@ -0,0 +1,5 @@
+MCU_SERIES = m0
+MCU_VARIANT = nrf51
+MCU_SUB_VARIANT = nrf51822
+SOFTDEV_VERSION = 8.0.0
+LD_FILE = boards/nrf51x22_256k_32k_s110_$(SOFTDEV_VERSION).ld
diff --git a/ports/nrf/boards/pca10028/mpconfigboard_s120.mk b/ports/nrf/boards/pca10028/mpconfigboard_s120.mk
new file mode 100644
index 0000000000..97843f8f71
--- /dev/null
+++ b/ports/nrf/boards/pca10028/mpconfigboard_s120.mk
@@ -0,0 +1,5 @@
+MCU_SERIES = m0
+MCU_VARIANT = nrf51
+MCU_SUB_VARIANT = nrf51822
+SOFTDEV_VERSION = 2.1.0
+LD_FILE = boards/nrf51x22_256k_32k_s120_$(SOFTDEV_VERSION).ld
diff --git a/ports/nrf/boards/pca10028/mpconfigboard_s130.mk b/ports/nrf/boards/pca10028/mpconfigboard_s130.mk
new file mode 100644
index 0000000000..908549afdc
--- /dev/null
+++ b/ports/nrf/boards/pca10028/mpconfigboard_s130.mk
@@ -0,0 +1,5 @@
+MCU_SERIES = m0
+MCU_VARIANT = nrf51
+MCU_SUB_VARIANT = nrf51822
+SOFTDEV_VERSION = 2.0.1
+LD_FILE = boards/nrf51x22_256k_32k_s130_$(SOFTDEV_VERSION).ld
diff --git a/ports/nrf/boards/pca10028/nrf51_hal_conf.h b/ports/nrf/boards/pca10028/nrf51_hal_conf.h
new file mode 100644
index 0000000000..79af193468
--- /dev/null
+++ b/ports/nrf/boards/pca10028/nrf51_hal_conf.h
@@ -0,0 +1,14 @@
+#ifndef NRF51_HAL_CONF_H__
+#define NRF51_HAL_CONF_H__
+
+#define HAL_UART_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIME_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_TIMER_MODULE_ENABLED
+#define HAL_TWI_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_TEMP_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+
+#endif // NRF51_HAL_CONF_H__
diff --git a/ports/nrf/boards/pca10028/pins.csv b/ports/nrf/boards/pca10028/pins.csv
new file mode 100644
index 0000000000..c239ba4903
--- /dev/null
+++ b/ports/nrf/boards/pca10028/pins.csv
@@ -0,0 +1,32 @@
+PA0,PA0
+PA1,PA1,ADC0_IN2
+PA2,PA2,ADC0_IN3
+PA3,PA3,ADC0_IN4
+PA4,PA4,ADC0_IN5
+PA5,PA5,ADC0_IN6
+PA6,PA6,ADC0_IN7
+PA7,PA7
+UART_RTS,PA8
+UART_TX,PA9
+UART_CTS,PA10
+UART_RX,PA11
+PA12,PA12
+PA13,PA13
+PA14,PA14
+PA15,PA15
+PA16,PA16
+PA17,PA17
+PA18,PA18
+PA19,PA19
+PA20,PA20
+PA21,PA21
+PA22,PA22
+PA23,PA23
+PA24,PA24
+PA25,PA25
+PA26,PA26
+PA27,PA27
+PA28,PA28
+PA29,PA29
+PA30,PA30
+PA31,PA31
\ No newline at end of file
diff --git a/ports/nrf/boards/pca10031/mpconfigboard.h b/ports/nrf/boards/pca10031/mpconfigboard.h
new file mode 100644
index 0000000000..78d66e4b3d
--- /dev/null
+++ b/ports/nrf/boards/pca10031/mpconfigboard.h
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#define PCA10031
+
+#define MICROPY_HW_BOARD_NAME       "PCA10031"
+#define MICROPY_HW_MCU_NAME         "NRF51822"
+#define MICROPY_PY_SYS_PLATFORM     "nrf51-dongle"
+
+#define MICROPY_PY_MACHINE_HW_SPI   (1)
+#define MICROPY_PY_MACHINE_TIMER    (1)
+#define MICROPY_PY_MACHINE_RTC      (1)
+#define MICROPY_PY_MACHINE_I2C      (1)
+#define MICROPY_PY_MACHINE_ADC      (1)
+#define MICROPY_PY_MACHINE_TEMP     (1)
+
+#define MICROPY_HW_HAS_LED          (1)
+#define MICROPY_HW_HAS_SWITCH       (0)
+#define MICROPY_HW_HAS_FLASH        (0)
+#define MICROPY_HW_HAS_SDCARD       (0)
+#define MICROPY_HW_HAS_MMA7660      (0)
+#define MICROPY_HW_HAS_LIS3DSH      (0)
+#define MICROPY_HW_HAS_LCD          (0)
+#define MICROPY_HW_ENABLE_RNG       (0)
+#define MICROPY_HW_ENABLE_RTC       (0)
+#define MICROPY_HW_ENABLE_TIMER     (0)
+#define MICROPY_HW_ENABLE_SERVO     (0)
+#define MICROPY_HW_ENABLE_DAC       (0)
+#define MICROPY_HW_ENABLE_CAN       (0)
+
+#define MICROPY_HW_LED_TRICOLOR     (1)
+#define MICROPY_HW_LED_PULLUP       (1)
+
+#define MICROPY_HW_LED_RED          (21) // RED
+#define MICROPY_HW_LED_GREEN        (22) // GREEN
+#define MICROPY_HW_LED_BLUE         (23) // BLUE
+
+// UART config
+#define MICROPY_HW_UART1_RX         (pin_A11)
+#define MICROPY_HW_UART1_TX         (pin_A9)
+#define MICROPY_HW_UART1_CTS        (pin_A10)
+#define MICROPY_HW_UART1_RTS        (pin_A8)
+#define MICROPY_HW_UART1_HWFC       (0)
+
+// SPI0 config
+#define MICROPY_HW_SPI0_NAME        "SPI0"
+#define MICROPY_HW_SPI0_SCK         (pin_A15)
+#define MICROPY_HW_SPI0_MOSI        (pin_A16)
+#define MICROPY_HW_SPI0_MISO        (pin_A17)
+
+#define HELP_TEXT_BOARD_LED         "1,2,3"
diff --git a/ports/nrf/boards/pca10031/mpconfigboard.mk b/ports/nrf/boards/pca10031/mpconfigboard.mk
new file mode 100644
index 0000000000..29e76d94a9
--- /dev/null
+++ b/ports/nrf/boards/pca10031/mpconfigboard.mk
@@ -0,0 +1,4 @@
+MCU_SERIES = m0
+MCU_VARIANT = nrf51
+MCU_SUB_VARIANT = nrf51822
+LD_FILE = boards/nrf51x22_256k_32k.ld
diff --git a/ports/nrf/boards/pca10031/mpconfigboard_s110.mk b/ports/nrf/boards/pca10031/mpconfigboard_s110.mk
new file mode 100644
index 0000000000..6afc1466f4
--- /dev/null
+++ b/ports/nrf/boards/pca10031/mpconfigboard_s110.mk
@@ -0,0 +1,5 @@
+MCU_SERIES = m0
+MCU_VARIANT = nrf51
+MCU_SUB_VARIANT = nrf51822
+SOFTDEV_VERSION = 8.0.0
+LD_FILE = boards/nrf51x22_256k_32k_s110_$(SOFTDEV_VERSION).ld
diff --git a/ports/nrf/boards/pca10031/mpconfigboard_s120.mk b/ports/nrf/boards/pca10031/mpconfigboard_s120.mk
new file mode 100644
index 0000000000..97843f8f71
--- /dev/null
+++ b/ports/nrf/boards/pca10031/mpconfigboard_s120.mk
@@ -0,0 +1,5 @@
+MCU_SERIES = m0
+MCU_VARIANT = nrf51
+MCU_SUB_VARIANT = nrf51822
+SOFTDEV_VERSION = 2.1.0
+LD_FILE = boards/nrf51x22_256k_32k_s120_$(SOFTDEV_VERSION).ld
diff --git a/ports/nrf/boards/pca10031/mpconfigboard_s130.mk b/ports/nrf/boards/pca10031/mpconfigboard_s130.mk
new file mode 100644
index 0000000000..908549afdc
--- /dev/null
+++ b/ports/nrf/boards/pca10031/mpconfigboard_s130.mk
@@ -0,0 +1,5 @@
+MCU_SERIES = m0
+MCU_VARIANT = nrf51
+MCU_SUB_VARIANT = nrf51822
+SOFTDEV_VERSION = 2.0.1
+LD_FILE = boards/nrf51x22_256k_32k_s130_$(SOFTDEV_VERSION).ld
diff --git a/ports/nrf/boards/pca10031/nrf51_hal_conf.h b/ports/nrf/boards/pca10031/nrf51_hal_conf.h
new file mode 100644
index 0000000000..79af193468
--- /dev/null
+++ b/ports/nrf/boards/pca10031/nrf51_hal_conf.h
@@ -0,0 +1,14 @@
+#ifndef NRF51_HAL_CONF_H__
+#define NRF51_HAL_CONF_H__
+
+#define HAL_UART_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIME_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_TIMER_MODULE_ENABLED
+#define HAL_TWI_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_TEMP_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+
+#endif // NRF51_HAL_CONF_H__
diff --git a/ports/nrf/boards/pca10031/pins.csv b/ports/nrf/boards/pca10031/pins.csv
new file mode 100644
index 0000000000..b27a12b91a
--- /dev/null
+++ b/ports/nrf/boards/pca10031/pins.csv
@@ -0,0 +1,13 @@
+UART_RTS,PA8
+UART_TX,PA9
+UART_CTS,PA10
+UART_RX,PA11
+LED_RED,PA21
+LED_GREEN,PA22
+LED_BLUE,PA23
+PA15,PA15
+PA16,PA16
+PA17,PA17
+PA18,PA18
+PA19,PA19
+PA20,PA20
\ No newline at end of file
diff --git a/ports/nrf/boards/pca10040/mpconfigboard.h b/ports/nrf/boards/pca10040/mpconfigboard.h
new file mode 100644
index 0000000000..7c46aa381d
--- /dev/null
+++ b/ports/nrf/boards/pca10040/mpconfigboard.h
@@ -0,0 +1,80 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#define PCA10040
+
+#define MICROPY_HW_BOARD_NAME       "PCA10040"
+#define MICROPY_HW_MCU_NAME         "NRF52832"
+#define MICROPY_PY_SYS_PLATFORM     "nrf52-DK"
+
+#define MICROPY_PY_MACHINE_HW_PWM   (1)
+#define MICROPY_PY_MACHINE_HW_SPI   (1)
+#define MICROPY_PY_MACHINE_TIMER    (1)
+#define MICROPY_PY_MACHINE_RTC      (1)
+#define MICROPY_PY_MACHINE_I2C      (1)
+#define MICROPY_PY_MACHINE_ADC      (1)
+#define MICROPY_PY_MACHINE_TEMP     (1)
+
+#define MICROPY_HW_HAS_LED          (1)
+#define MICROPY_HW_HAS_SWITCH       (0)
+#define MICROPY_HW_HAS_FLASH        (0)
+#define MICROPY_HW_HAS_SDCARD       (0)
+#define MICROPY_HW_HAS_MMA7660      (0)
+#define MICROPY_HW_HAS_LIS3DSH      (0)
+#define MICROPY_HW_HAS_LCD          (0)
+#define MICROPY_HW_ENABLE_RNG       (0)
+#define MICROPY_HW_ENABLE_RTC       (0)
+#define MICROPY_HW_ENABLE_TIMER     (0)
+#define MICROPY_HW_ENABLE_SERVO     (0)
+#define MICROPY_HW_ENABLE_DAC       (0)
+#define MICROPY_HW_ENABLE_CAN       (0)
+
+#define MICROPY_HW_LED_COUNT        (4)
+#define MICROPY_HW_LED_PULLUP       (1)
+
+#define MICROPY_HW_LED1             (17) // LED1
+#define MICROPY_HW_LED2             (18) // LED2
+#define MICROPY_HW_LED3             (19) // LED3
+#define MICROPY_HW_LED4             (20) // LED4
+
+// UART config
+#define MICROPY_HW_UART1_RX         (pin_A8)
+#define MICROPY_HW_UART1_TX         (pin_A6)
+#define MICROPY_HW_UART1_CTS        (pin_A7)
+#define MICROPY_HW_UART1_RTS        (pin_A5)
+#define MICROPY_HW_UART1_HWFC       (1)
+
+// SPI0 config
+#define MICROPY_HW_SPI0_NAME        "SPI0"
+#define MICROPY_HW_SPI0_SCK         (pin_A25) // (Arduino D13)
+#define MICROPY_HW_SPI0_MOSI        (pin_A23) // (Arduino D11)
+#define MICROPY_HW_SPI0_MISO        (pin_A24) // (Arduino D12)
+
+#define MICROPY_HW_PWM0_NAME        "PWM0"
+#define MICROPY_HW_PWM1_NAME        "PWM1"
+#define MICROPY_HW_PWM2_NAME        "PWM2"
+
+#define HELP_TEXT_BOARD_LED         "1,2,3,4"
diff --git a/ports/nrf/boards/pca10040/mpconfigboard.mk b/ports/nrf/boards/pca10040/mpconfigboard.mk
new file mode 100644
index 0000000000..83dbb5ab42
--- /dev/null
+++ b/ports/nrf/boards/pca10040/mpconfigboard.mk
@@ -0,0 +1,6 @@
+MCU_SERIES = m4
+MCU_VARIANT = nrf52
+MCU_SUB_VARIANT = nrf52832
+LD_FILE = boards/nrf52832_512k_64k.ld
+
+NRF_DEFINES += -DNRF52832_XXAA
diff --git a/ports/nrf/boards/pca10040/mpconfigboard_s132.mk b/ports/nrf/boards/pca10040/mpconfigboard_s132.mk
new file mode 100644
index 0000000000..42d37d38d4
--- /dev/null
+++ b/ports/nrf/boards/pca10040/mpconfigboard_s132.mk
@@ -0,0 +1,8 @@
+MCU_SERIES = m4
+MCU_VARIANT = nrf52
+MCU_SUB_VARIANT = nrf52832
+SOFTDEV_VERSION = 3.0.0
+
+LD_FILE = boards/nrf52832_512k_64k_s132_$(SOFTDEV_VERSION).ld
+
+NRF_DEFINES += -DNRF52832_XXAA
diff --git a/ports/nrf/boards/pca10040/nrf52_hal_conf.h b/ports/nrf/boards/pca10040/nrf52_hal_conf.h
new file mode 100644
index 0000000000..fd6073a187
--- /dev/null
+++ b/ports/nrf/boards/pca10040/nrf52_hal_conf.h
@@ -0,0 +1,18 @@
+#ifndef NRF52_HAL_CONF_H__
+#define NRF52_HAL_CONF_H__
+
+#define HAL_UART_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIME_MODULE_ENABLED
+#define HAL_PWM_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_TIMER_MODULE_ENABLED
+#define HAL_TWI_MODULE_ENABLED
+#define HAL_ADCE_MODULE_ENABLED
+#define HAL_TEMP_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+// #define HAL_UARTE_MODULE_ENABLED
+// #define HAL_SPIE_MODULE_ENABLED
+// #define HAL_TWIE_MODULE_ENABLED
+
+#endif // NRF52_HAL_CONF_H__
diff --git a/ports/nrf/boards/pca10040/pins.csv b/ports/nrf/boards/pca10040/pins.csv
new file mode 100644
index 0000000000..c177133983
--- /dev/null
+++ b/ports/nrf/boards/pca10040/pins.csv
@@ -0,0 +1,30 @@
+PA2,PA2
+PA3,PA3
+PA4,PA4
+PA5,PA5
+PA6,PA6
+PA7,PA7
+PA8,PA8
+PA9,PA9
+PA10,PA10
+PA11,PA11
+PA12,PA12
+PA13,PA13
+PA14,PA14
+PA15,PA15
+PA16,PA16
+PA17,PA17
+PA18,PA18
+PA19,PA19
+PA20,PA20
+PA21,PA21
+PA22,PA22
+PA23,PA23
+PA24,PA24
+PA25,PA25
+PA26,PA26
+PA27,PA27
+PA28,PA28
+PA29,PA29
+PA30,PA30
+PA31,PA31
\ No newline at end of file
diff --git a/ports/nrf/boards/pca10056/mpconfigboard.h b/ports/nrf/boards/pca10056/mpconfigboard.h
new file mode 100644
index 0000000000..dc16f65674
--- /dev/null
+++ b/ports/nrf/boards/pca10056/mpconfigboard.h
@@ -0,0 +1,84 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#define PCA10056
+
+#define MICROPY_HW_BOARD_NAME       "PCA10056"
+#define MICROPY_HW_MCU_NAME         "NRF52840"
+#define MICROPY_PY_SYS_PLATFORM     "nrf52840-PDK"
+
+#define MICROPY_PY_MACHINE_HW_PWM   (1)
+#define MICROPY_PY_MACHINE_HW_SPI   (1)
+#define MICROPY_PY_MACHINE_TIMER    (1)
+#define MICROPY_PY_MACHINE_RTC      (1)
+#define MICROPY_PY_MACHINE_I2C      (1)
+#define MICROPY_PY_MACHINE_ADC      (1)
+#define MICROPY_PY_MACHINE_TEMP     (1)
+
+#define MICROPY_HW_HAS_LED          (1)
+#define MICROPY_HW_HAS_SWITCH       (0)
+#define MICROPY_HW_HAS_FLASH        (0)
+#define MICROPY_HW_HAS_SDCARD       (0)
+#define MICROPY_HW_HAS_MMA7660      (0)
+#define MICROPY_HW_HAS_LIS3DSH      (0)
+#define MICROPY_HW_HAS_LCD          (0)
+#define MICROPY_HW_ENABLE_RNG       (0)
+#define MICROPY_HW_ENABLE_RTC       (0)
+#define MICROPY_HW_ENABLE_TIMER     (0)
+#define MICROPY_HW_ENABLE_SERVO     (0)
+#define MICROPY_HW_ENABLE_DAC       (0)
+#define MICROPY_HW_ENABLE_CAN       (0)
+
+#define MICROPY_HW_LED_COUNT        (4)
+#define MICROPY_HW_LED_PULLUP       (1)
+
+#define MICROPY_HW_LED1             (13) // LED1
+#define MICROPY_HW_LED2             (14) // LED2
+#define MICROPY_HW_LED3             (15) // LED3
+#define MICROPY_HW_LED4             (16) // LED4
+
+// UART config
+#define MICROPY_HW_UART1_RX         (pin_A8)
+#define MICROPY_HW_UART1_TX         (pin_A6)
+#define MICROPY_HW_UART1_CTS        (pin_A7)
+#define MICROPY_HW_UART1_RTS        (pin_A5)
+#define MICROPY_HW_UART1_HWFC       (1)
+
+// SPI0 config
+#define MICROPY_HW_SPI0_NAME        "SPI0"
+
+#define MICROPY_HW_SPI0_SCK         (pin_B15)
+#define MICROPY_HW_SPI0_MOSI        (pin_B13)
+#define MICROPY_HW_SPI0_MISO        (pin_B14)
+
+#define MICROPY_HW_PWM0_NAME        "PWM0"
+#define MICROPY_HW_PWM1_NAME        "PWM1"
+#define MICROPY_HW_PWM2_NAME        "PWM2"
+#if 0
+#define MICROPY_HW_PWM3_NAME        "PWM3"
+#endif
+
+#define HELP_TEXT_BOARD_LED         "1,2,3,4"
diff --git a/ports/nrf/boards/pca10056/mpconfigboard.mk b/ports/nrf/boards/pca10056/mpconfigboard.mk
new file mode 100644
index 0000000000..76661243a6
--- /dev/null
+++ b/ports/nrf/boards/pca10056/mpconfigboard.mk
@@ -0,0 +1,6 @@
+MCU_SERIES = m4
+MCU_VARIANT = nrf52
+MCU_SUB_VARIANT = nrf52840
+LD_FILE = boards/nrf52840_1M_256k.ld
+
+NRF_DEFINES += -DNRF52840_XXAA
diff --git a/ports/nrf/boards/pca10056/nrf52_hal_conf.h b/ports/nrf/boards/pca10056/nrf52_hal_conf.h
new file mode 100644
index 0000000000..0f42e8975b
--- /dev/null
+++ b/ports/nrf/boards/pca10056/nrf52_hal_conf.h
@@ -0,0 +1,18 @@
+#ifndef NRF52_HAL_CONF_H__
+#define NRF52_HAL_CONF_H__
+
+// #define HAL_UART_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIME_MODULE_ENABLED
+#define HAL_PWM_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_TIMER_MODULE_ENABLED
+#define HAL_TWI_MODULE_ENABLED
+#define HAL_ADCE_MODULE_ENABLED
+#define HAL_TEMP_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+#define HAL_UARTE_MODULE_ENABLED
+// #define HAL_SPIE_MODULE_ENABLED
+// #define HAL_TWIE_MODULE_ENABLED
+
+#endif // NRF52_HAL_CONF_H__
diff --git a/ports/nrf/boards/pca10056/pins.csv b/ports/nrf/boards/pca10056/pins.csv
new file mode 100644
index 0000000000..f2f7f19672
--- /dev/null
+++ b/ports/nrf/boards/pca10056/pins.csv
@@ -0,0 +1,48 @@
+PA0,PA0
+PA1,PA1
+PA2,PA2,ADC0_IN0
+PA3,PA3,ADC0_IN1
+PA4,PA4,ADC0_IN2
+PA5,PA5,ADC0_IN3
+PA6,PA6
+PA7,PA7
+PA8,PA8
+PA9,PA9
+PA10,PA10
+PA11,PA11
+PA12,PA12
+PA13,PA13
+PA14,PA14
+PA15,PA15
+PA16,PA16
+PA17,PA17
+PA18,PA18
+PA19,PA19
+PA20,PA20
+PA21,PA21
+PA22,PA22
+PA23,PA23
+PA24,PA24
+PA25,PA25
+PA26,PA26
+PA27,PA27
+PA28,PA28,ADC0_IN4
+PA29,PA29,ADC0_IN5
+PA30,PA30,ADC0_IN6
+PA31,PA31,ADC0_IN7
+PB0,PB0
+PB1,PB1
+PB2,PB2
+PB3,PB3
+PB4,PB4
+PB5,PB5
+PB6,PB6
+PB7,PB7
+PB8,PB8
+PB9,PB9
+PB10,PB10
+PB11,PB11
+PB12,PB12
+PB13,PB13
+PB14,PB14
+PB15,PB15
diff --git a/ports/nrf/boards/wt51822_s4at/mpconfigboard.h b/ports/nrf/boards/wt51822_s4at/mpconfigboard.h
new file mode 100644
index 0000000000..f8b2405885
--- /dev/null
+++ b/ports/nrf/boards/wt51822_s4at/mpconfigboard.h
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Ayke van Laethem
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#define WT51822_S4AT
+
+// Datasheet for board:
+// https://4tronix.co.uk/picobot2/WT51822-S4AT.pdf
+#define MICROPY_HW_BOARD_NAME       "WT51822-S4AT"
+#define MICROPY_HW_MCU_NAME         "NRF51822"
+#define MICROPY_PY_SYS_PLATFORM     "nrf51"
+
+#define MICROPY_PY_MACHINE_HW_SPI   (1)
+#define MICROPY_PY_MACHINE_TIMER    (1)
+#define MICROPY_PY_MACHINE_RTC      (1)
+#define MICROPY_PY_MACHINE_I2C      (1)
+#define MICROPY_PY_MACHINE_ADC      (1)
+#define MICROPY_PY_MACHINE_TEMP     (1)
+
+#define MICROPY_HW_HAS_LED          (0)
+#define MICROPY_HW_HAS_SWITCH       (0)
+#define MICROPY_HW_HAS_FLASH        (0)
+#define MICROPY_HW_HAS_SDCARD       (0)
+#define MICROPY_HW_HAS_MMA7660      (0)
+#define MICROPY_HW_HAS_LIS3DSH      (0)
+#define MICROPY_HW_HAS_LCD          (0)
+#define MICROPY_HW_ENABLE_RNG       (0)
+#define MICROPY_HW_ENABLE_RTC       (0)
+#define MICROPY_HW_ENABLE_TIMER     (0)
+#define MICROPY_HW_ENABLE_SERVO     (0)
+#define MICROPY_HW_ENABLE_DAC       (0)
+#define MICROPY_HW_ENABLE_CAN       (0)
+
+// UART config
+#define MICROPY_HW_UART1_RX         (pin_A1)
+#define MICROPY_HW_UART1_TX         (pin_A2)
+#define MICROPY_HW_UART1_HWFC       (0)
+
+// SPI0 config
+#define MICROPY_HW_SPI0_NAME        "SPI0"
+#define MICROPY_HW_SPI0_SCK         (pin_A9)
+#define MICROPY_HW_SPI0_MOSI        (pin_A10)
+#define MICROPY_HW_SPI0_MISO        (pin_A13)
diff --git a/ports/nrf/boards/wt51822_s4at/mpconfigboard.mk b/ports/nrf/boards/wt51822_s4at/mpconfigboard.mk
new file mode 100644
index 0000000000..12087d6828
--- /dev/null
+++ b/ports/nrf/boards/wt51822_s4at/mpconfigboard.mk
@@ -0,0 +1,4 @@
+MCU_SERIES = m0
+MCU_VARIANT = nrf51
+MCU_SUB_VARIANT = nrf51822
+LD_FILE = boards/nrf51x22_256k_16k.ld
diff --git a/ports/nrf/boards/wt51822_s4at/mpconfigboard_s110.mk b/ports/nrf/boards/wt51822_s4at/mpconfigboard_s110.mk
new file mode 100644
index 0000000000..8f5433b47c
--- /dev/null
+++ b/ports/nrf/boards/wt51822_s4at/mpconfigboard_s110.mk
@@ -0,0 +1,7 @@
+MCU_SERIES = m0
+MCU_VARIANT = nrf51
+MCU_SUB_VARIANT = nrf51822
+SOFTDEV_VERSION = 8.0.0
+LD_FILE = boards/nrf51x22_256k_16k_s110_$(SOFTDEV_VERSION).ld
+
+CFLAGS += -DBLUETOOTH_LFCLK_RC
diff --git a/ports/nrf/boards/wt51822_s4at/nrf51_hal_conf.h b/ports/nrf/boards/wt51822_s4at/nrf51_hal_conf.h
new file mode 100644
index 0000000000..79af193468
--- /dev/null
+++ b/ports/nrf/boards/wt51822_s4at/nrf51_hal_conf.h
@@ -0,0 +1,14 @@
+#ifndef NRF51_HAL_CONF_H__
+#define NRF51_HAL_CONF_H__
+
+#define HAL_UART_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIME_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_TIMER_MODULE_ENABLED
+#define HAL_TWI_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_TEMP_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+
+#endif // NRF51_HAL_CONF_H__
diff --git a/ports/nrf/boards/wt51822_s4at/pins.csv b/ports/nrf/boards/wt51822_s4at/pins.csv
new file mode 100644
index 0000000000..01f5e8fcef
--- /dev/null
+++ b/ports/nrf/boards/wt51822_s4at/pins.csv
@@ -0,0 +1,7 @@
+PA1,PA1
+PA2,PA2
+PA3,PA3
+PA4,PA4
+PA9,PA9
+PA10,PA10
+PA13,PA13
diff --git a/ports/nrf/device/compiler_abstraction.h b/ports/nrf/device/compiler_abstraction.h
new file mode 100644
index 0000000000..df9f3dbdee
--- /dev/null
+++ b/ports/nrf/device/compiler_abstraction.h
@@ -0,0 +1,144 @@
+/* Copyright (c) 2016, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *   * Redistributions of source code must retain the above copyright notice, this
+ *     list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *
+ *   * Neither the name of Nordic Semiconductor ASA nor the names of its
+ *     contributors may be used to endorse or promote products derived from
+ *     this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+ 
+#ifndef _COMPILER_ABSTRACTION_H
+#define _COMPILER_ABSTRACTION_H
+
+/*lint ++flb "Enter library region" */
+
+#if defined ( __CC_ARM )
+
+    #ifndef __ASM
+        #define __ASM               __asm
+    #endif
+
+    #ifndef __INLINE
+        #define __INLINE            __inline
+    #endif
+
+    #ifndef __WEAK
+        #define __WEAK              __weak
+    #endif
+
+    #ifndef __ALIGN
+        #define __ALIGN(n)          __align(n)
+    #endif
+
+    #ifndef __PACKED
+        #define __PACKED            __packed
+    #endif
+
+    #define GET_SP()                __current_sp()
+
+#elif defined ( __ICCARM__ )
+
+    #ifndef __ASM
+        #define __ASM               __asm
+    #endif
+
+    #ifndef __INLINE
+        #define __INLINE            inline
+    #endif
+
+    #ifndef __WEAK
+        #define __WEAK              __weak
+    #endif
+
+    #ifndef __ALIGN
+        #define STRING_PRAGMA(x) _Pragma(#x)
+        #define __ALIGN(n) STRING_PRAGMA(data_alignment = n)
+    #endif
+
+    #ifndef __PACKED
+        #define __PACKED            __packed
+    #endif
+    
+    #define GET_SP()                __get_SP()
+
+#elif defined   ( __GNUC__ )
+
+    #ifndef __ASM
+        #define __ASM               __asm
+    #endif
+
+    #ifndef __INLINE
+        #define __INLINE            inline
+    #endif
+
+    #ifndef __WEAK
+        #define __WEAK              __attribute__((weak))
+    #endif
+
+    #ifndef __ALIGN
+        #define __ALIGN(n)          __attribute__((aligned(n)))
+    #endif
+
+    #ifndef __PACKED
+        #define __PACKED           __attribute__((packed)) 
+    #endif
+
+    #define GET_SP()                gcc_current_sp()
+
+    static inline unsigned int gcc_current_sp(void)
+    {
+        register unsigned sp __ASM("sp");
+        return sp;
+    }
+
+#elif defined   ( __TASKING__ )
+
+    #ifndef __ASM
+        #define __ASM               __asm
+    #endif
+
+    #ifndef __INLINE
+        #define __INLINE            inline
+    #endif
+
+    #ifndef __WEAK
+        #define __WEAK              __attribute__((weak))
+    #endif
+
+    #ifndef __ALIGN
+        #define __ALIGN(n)          __align(n)
+    #endif
+    
+    /* Not defined for TASKING. */
+    #ifndef __PACKED
+        #define __PACKED
+    #endif
+
+    #define GET_SP()                __get_MSP()
+
+#endif
+
+/*lint --flb "Leave library region" */
+
+#endif
diff --git a/ports/nrf/device/nrf.h b/ports/nrf/device/nrf.h
new file mode 100644
index 0000000000..b74af23e6e
--- /dev/null
+++ b/ports/nrf/device/nrf.h
@@ -0,0 +1,77 @@
+/* Copyright (c) 2016, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *   * Redistributions of source code must retain the above copyright notice, this
+ *     list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *
+ *   * Neither the name of Nordic Semiconductor ASA nor the names of its
+ *     contributors may be used to endorse or promote products derived from
+ *     this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+ 
+#ifndef NRF_H
+#define NRF_H
+
+/* MDK version */
+#define MDK_MAJOR_VERSION   8
+#define MDK_MINOR_VERSION   11
+#define MDK_MICRO_VERSION   1
+
+/* Define NRF52_SERIES for common use in nRF52 series devices. */
+#if defined (NRF52832_XXAA) || defined (NRF52840_XXAA)
+    #define NRF52_SERIES
+#endif
+
+
+#if defined(_WIN32)
+    /* Do not include nrf specific files when building for PC host */
+#elif defined(__unix)
+    /* Do not include nrf specific files when building for PC host */
+#elif defined(__APPLE__)
+    /* Do not include nrf specific files when building for PC host */
+#else
+
+    /* Device selection for device includes. */
+    #if defined (NRF51)
+        #include "nrf51.h"
+        #include "nrf51_bitfields.h"
+        #include "nrf51_deprecated.h"
+    #elif defined (NRF52840_XXAA)
+        #include "nrf52840.h"
+        #include "nrf52840_bitfields.h"
+        #include "nrf51_to_nrf52840.h"
+        #include "nrf52_to_nrf52840.h"
+    #elif defined (NRF52832_XXAA)
+        #include "nrf52.h"
+        #include "nrf52_bitfields.h"
+        #include "nrf51_to_nrf52.h"
+        #include "nrf52_name_change.h"
+    #else
+        #error "Device must be defined. See nrf.h."
+    #endif /* NRF51, NRF52832_XXAA, NRF52840_XXAA */
+
+    #include "compiler_abstraction.h"
+
+#endif /* _WIN32 || __unix || __APPLE__ */
+
+#endif /* NRF_H */
+
diff --git a/ports/nrf/device/nrf51/nrf51.h b/ports/nrf/device/nrf51/nrf51.h
new file mode 100644
index 0000000000..ae60a5613d
--- /dev/null
+++ b/ports/nrf/device/nrf51/nrf51.h
@@ -0,0 +1,1193 @@
+
+/****************************************************************************************************//**
+ * @file     nrf51.h
+ *
+ * @brief    CMSIS Cortex-M0 Peripheral Access Layer Header File for
+ *           nrf51 from Nordic Semiconductor.
+ *
+ * @version  V522
+ * @date     18. November 2016
+ *
+ * @note     Generated with SVDConv V2.81d 
+ *           from CMSIS SVD File 'nrf51.svd' Version 522,
+ *
+ * @par      Copyright (c) 2016, Nordic Semiconductor ASA
+ *           All rights reserved.
+ *           
+ *           Redistribution and use in source and binary forms, with or without
+ *           modification, are permitted provided that the following conditions are met:
+ *           
+ *           * Redistributions of source code must retain the above copyright notice, this
+ *           list of conditions and the following disclaimer.
+ *           
+ *           * Redistributions in binary form must reproduce the above copyright notice,
+ *           this list of conditions and the following disclaimer in the documentation
+ *           and/or other materials provided with the distribution.
+ *           
+ *           * Neither the name of Nordic Semiconductor ASA nor the names of its
+ *           contributors may be used to endorse or promote products derived from
+ *           this software without specific prior written permission.
+ *           
+ *           THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *           AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *           IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *           DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ *           FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *           DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ *           SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ *           CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ *           OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *           OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *           
+ *
+ *******************************************************************************************************/
+
+
+
+/** @addtogroup Nordic Semiconductor
+  * @{
+  */
+
+/** @addtogroup nrf51
+  * @{
+  */
+
+#ifndef NRF51_H
+#define NRF51_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* -------------------------  Interrupt Number Definition  ------------------------ */
+
+typedef enum {
+/* -------------------  Cortex-M0 Processor Exceptions Numbers  ------------------- */
+  Reset_IRQn                    = -15,              /*!<   1  Reset Vector, invoked on Power up and warm reset                 */
+  NonMaskableInt_IRQn           = -14,              /*!<   2  Non maskable Interrupt, cannot be stopped or preempted           */
+  HardFault_IRQn                = -13,              /*!<   3  Hard Fault, all classes of Fault                                 */
+  SVCall_IRQn                   =  -5,              /*!<  11  System Service Call via SVC instruction                          */
+  DebugMonitor_IRQn             =  -4,              /*!<  12  Debug Monitor                                                    */
+  PendSV_IRQn                   =  -2,              /*!<  14  Pendable request for system service                              */
+  SysTick_IRQn                  =  -1,              /*!<  15  System Tick Timer                                                */
+/* ----------------------  nrf51 Specific Interrupt Numbers  ---------------------- */
+  POWER_CLOCK_IRQn              =   0,              /*!<   0  POWER_CLOCK                                                      */
+  RADIO_IRQn                    =   1,              /*!<   1  RADIO                                                            */
+  UART0_IRQn                    =   2,              /*!<   2  UART0                                                            */
+  SPI0_TWI0_IRQn                =   3,              /*!<   3  SPI0_TWI0                                                        */
+  SPI1_TWI1_IRQn                =   4,              /*!<   4  SPI1_TWI1                                                        */
+  GPIOTE_IRQn                   =   6,              /*!<   6  GPIOTE                                                           */
+  ADC_IRQn                      =   7,              /*!<   7  ADC                                                              */
+  TIMER0_IRQn                   =   8,              /*!<   8  TIMER0                                                           */
+  TIMER1_IRQn                   =   9,              /*!<   9  TIMER1                                                           */
+  TIMER2_IRQn                   =  10,              /*!<  10  TIMER2                                                           */
+  RTC0_IRQn                     =  11,              /*!<  11  RTC0                                                             */
+  TEMP_IRQn                     =  12,              /*!<  12  TEMP                                                             */
+  RNG_IRQn                      =  13,              /*!<  13  RNG                                                              */
+  ECB_IRQn                      =  14,              /*!<  14  ECB                                                              */
+  CCM_AAR_IRQn                  =  15,              /*!<  15  CCM_AAR                                                          */
+  WDT_IRQn                      =  16,              /*!<  16  WDT                                                              */
+  RTC1_IRQn                     =  17,              /*!<  17  RTC1                                                             */
+  QDEC_IRQn                     =  18,              /*!<  18  QDEC                                                             */
+  LPCOMP_IRQn                   =  19,              /*!<  19  LPCOMP                                                           */
+  SWI0_IRQn                     =  20,              /*!<  20  SWI0                                                             */
+  SWI1_IRQn                     =  21,              /*!<  21  SWI1                                                             */
+  SWI2_IRQn                     =  22,              /*!<  22  SWI2                                                             */
+  SWI3_IRQn                     =  23,              /*!<  23  SWI3                                                             */
+  SWI4_IRQn                     =  24,              /*!<  24  SWI4                                                             */
+  SWI5_IRQn                     =  25               /*!<  25  SWI5                                                             */
+} IRQn_Type;
+
+
+/** @addtogroup Configuration_of_CMSIS
+  * @{
+  */
+
+
+/* ================================================================================ */
+/* ================      Processor and Core Peripheral Section     ================ */
+/* ================================================================================ */
+
+/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
+#define __CM0_REV                 0x0301            /*!< Cortex-M0 Core Revision                                               */
+#define __MPU_PRESENT                  0            /*!< MPU present or not                                                    */
+#define __NVIC_PRIO_BITS               2            /*!< Number of Bits used for Priority Levels                               */
+#define __Vendor_SysTickConfig         0            /*!< Set to 1 if different SysTick Config is used                          */
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include "core_cm0.h"                               /*!< Cortex-M0 processor and core peripherals                              */
+#include "system_nrf51.h"                           /*!< nrf51 System                                                          */
+
+
+/* ================================================================================ */
+/* ================       Device Specific Peripheral Section       ================ */
+/* ================================================================================ */
+
+
+/** @addtogroup Device_Peripheral_Registers
+  * @{
+  */
+
+
+/* -------------------  Start of section using anonymous unions  ------------------ */
+#if defined(__CC_ARM)
+  #pragma push
+  #pragma anon_unions
+#elif defined(__ICCARM__)
+  #pragma language=extended
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+/* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+  #pragma warning 586
+#else
+  #warning Not supported compiler type
+#endif
+
+
+typedef struct {
+  __O  uint32_t  EN;                                /*!< Enable channel group.                                                 */
+  __O  uint32_t  DIS;                               /*!< Disable channel group.                                                */
+} PPI_TASKS_CHG_Type;
+
+typedef struct {
+  __IO uint32_t  EEP;                               /*!< Channel event end-point.                                              */
+  __IO uint32_t  TEP;                               /*!< Channel task end-point.                                               */
+} PPI_CH_Type;
+
+
+/* ================================================================================ */
+/* ================                      POWER                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Power Control. (POWER)
+  */
+
+typedef struct {                                    /*!< POWER Structure                                                       */
+  __I  uint32_t  RESERVED0[30];
+  __O  uint32_t  TASKS_CONSTLAT;                    /*!< Enable constant latency mode.                                         */
+  __O  uint32_t  TASKS_LOWPWR;                      /*!< Enable low power mode (variable latency).                             */
+  __I  uint32_t  RESERVED1[34];
+  __IO uint32_t  EVENTS_POFWARN;                    /*!< Power failure warning.                                                */
+  __I  uint32_t  RESERVED2[126];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED3[61];
+  __IO uint32_t  RESETREAS;                         /*!< Reset reason.                                                         */
+  __I  uint32_t  RESERVED4[9];
+  __I  uint32_t  RAMSTATUS;                         /*!< Ram status register.                                                  */
+  __I  uint32_t  RESERVED5[53];
+  __O  uint32_t  SYSTEMOFF;                         /*!< System off register.                                                  */
+  __I  uint32_t  RESERVED6[3];
+  __IO uint32_t  POFCON;                            /*!< Power failure configuration.                                          */
+  __I  uint32_t  RESERVED7[2];
+  __IO uint32_t  GPREGRET;                          /*!< General purpose retention register. This register is a retained
+                                                         register.                                                             */
+  __I  uint32_t  RESERVED8;
+  __IO uint32_t  RAMON;                             /*!< Ram on/off.                                                           */
+  __I  uint32_t  RESERVED9[7];
+  __IO uint32_t  RESET;                             /*!< Pin reset functionality configuration register. This register
+                                                         is a retained register.                                               */
+  __I  uint32_t  RESERVED10[3];
+  __IO uint32_t  RAMONB;                            /*!< Ram on/off.                                                           */
+  __I  uint32_t  RESERVED11[8];
+  __IO uint32_t  DCDCEN;                            /*!< DCDC converter enable configuration register.                         */
+  __I  uint32_t  RESERVED12[291];
+  __IO uint32_t  DCDCFORCE;                         /*!< DCDC power-up force register.                                         */
+} NRF_POWER_Type;
+
+
+/* ================================================================================ */
+/* ================                      CLOCK                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Clock control. (CLOCK)
+  */
+
+typedef struct {                                    /*!< CLOCK Structure                                                       */
+  __O  uint32_t  TASKS_HFCLKSTART;                  /*!< Start HFCLK clock source.                                             */
+  __O  uint32_t  TASKS_HFCLKSTOP;                   /*!< Stop HFCLK clock source.                                              */
+  __O  uint32_t  TASKS_LFCLKSTART;                  /*!< Start LFCLK clock source.                                             */
+  __O  uint32_t  TASKS_LFCLKSTOP;                   /*!< Stop LFCLK clock source.                                              */
+  __O  uint32_t  TASKS_CAL;                         /*!< Start calibration of LFCLK RC oscillator.                             */
+  __O  uint32_t  TASKS_CTSTART;                     /*!< Start calibration timer.                                              */
+  __O  uint32_t  TASKS_CTSTOP;                      /*!< Stop calibration timer.                                               */
+  __I  uint32_t  RESERVED0[57];
+  __IO uint32_t  EVENTS_HFCLKSTARTED;               /*!< HFCLK oscillator started.                                             */
+  __IO uint32_t  EVENTS_LFCLKSTARTED;               /*!< LFCLK oscillator started.                                             */
+  __I  uint32_t  RESERVED1;
+  __IO uint32_t  EVENTS_DONE;                       /*!< Calibration of LFCLK RC oscillator completed.                         */
+  __IO uint32_t  EVENTS_CTTO;                       /*!< Calibration timer timeout.                                            */
+  __I  uint32_t  RESERVED2[124];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED3[63];
+  __I  uint32_t  HFCLKRUN;                          /*!< Task HFCLKSTART trigger status.                                       */
+  __I  uint32_t  HFCLKSTAT;                         /*!< High frequency clock status.                                          */
+  __I  uint32_t  RESERVED4;
+  __I  uint32_t  LFCLKRUN;                          /*!< Task LFCLKSTART triggered status.                                     */
+  __I  uint32_t  LFCLKSTAT;                         /*!< Low frequency clock status.                                           */
+  __I  uint32_t  LFCLKSRCCOPY;                      /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is
+                                                         triggered.                                                            */
+  __I  uint32_t  RESERVED5[62];
+  __IO uint32_t  LFCLKSRC;                          /*!< Clock source for the LFCLK clock.                                     */
+  __I  uint32_t  RESERVED6[7];
+  __IO uint32_t  CTIV;                              /*!< Calibration timer interval.                                           */
+  __I  uint32_t  RESERVED7[5];
+  __IO uint32_t  XTALFREQ;                          /*!< Crystal frequency.                                                    */
+} NRF_CLOCK_Type;
+
+
+/* ================================================================================ */
+/* ================                       MPU                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Memory Protection Unit. (MPU)
+  */
+
+typedef struct {                                    /*!< MPU Structure                                                         */
+  __I  uint32_t  RESERVED0[330];
+  __IO uint32_t  PERR0;                             /*!< Configuration of peripherals in mpu regions.                          */
+  __IO uint32_t  RLENR0;                            /*!< Length of RAM region 0.                                               */
+  __I  uint32_t  RESERVED1[52];
+  __IO uint32_t  PROTENSET0;                        /*!< Erase and write protection bit enable set register.                   */
+  __IO uint32_t  PROTENSET1;                        /*!< Erase and write protection bit enable set register.                   */
+  __IO uint32_t  DISABLEINDEBUG;                    /*!< Disable erase and write protection mechanism in debug mode.           */
+  __IO uint32_t  PROTBLOCKSIZE;                     /*!< Erase and write protection block size.                                */
+} NRF_MPU_Type;
+
+
+/* ================================================================================ */
+/* ================                      RADIO                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief The radio. (RADIO)
+  */
+
+typedef struct {                                    /*!< RADIO Structure                                                       */
+  __O  uint32_t  TASKS_TXEN;                        /*!< Enable radio in TX mode.                                              */
+  __O  uint32_t  TASKS_RXEN;                        /*!< Enable radio in RX mode.                                              */
+  __O  uint32_t  TASKS_START;                       /*!< Start radio.                                                          */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop radio.                                                           */
+  __O  uint32_t  TASKS_DISABLE;                     /*!< Disable radio.                                                        */
+  __O  uint32_t  TASKS_RSSISTART;                   /*!< Start the RSSI and take one sample of the receive signal strength.    */
+  __O  uint32_t  TASKS_RSSISTOP;                    /*!< Stop the RSSI measurement.                                            */
+  __O  uint32_t  TASKS_BCSTART;                     /*!< Start the bit counter.                                                */
+  __O  uint32_t  TASKS_BCSTOP;                      /*!< Stop the bit counter.                                                 */
+  __I  uint32_t  RESERVED0[55];
+  __IO uint32_t  EVENTS_READY;                      /*!< Ready event.                                                          */
+  __IO uint32_t  EVENTS_ADDRESS;                    /*!< Address event.                                                        */
+  __IO uint32_t  EVENTS_PAYLOAD;                    /*!< Payload event.                                                        */
+  __IO uint32_t  EVENTS_END;                        /*!< End event.                                                            */
+  __IO uint32_t  EVENTS_DISABLED;                   /*!< Disable event.                                                        */
+  __IO uint32_t  EVENTS_DEVMATCH;                   /*!< A device address match occurred on the last received packet.          */
+  __IO uint32_t  EVENTS_DEVMISS;                    /*!< No device address match occurred on the last received packet.         */
+  __IO uint32_t  EVENTS_RSSIEND;                    /*!< Sampling of the receive signal strength complete. A new RSSI
+                                                         sample is ready for readout at the RSSISAMPLE register.               */
+  __I  uint32_t  RESERVED1[2];
+  __IO uint32_t  EVENTS_BCMATCH;                    /*!< Bit counter reached bit count value specified in BCC register.        */
+  __I  uint32_t  RESERVED2[53];
+  __IO uint32_t  SHORTS;                            /*!< Shortcuts for the radio.                                              */
+  __I  uint32_t  RESERVED3[64];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED4[61];
+  __I  uint32_t  CRCSTATUS;                         /*!< CRC status of received packet.                                        */
+  __I  uint32_t  RESERVED5;
+  __I  uint32_t  RXMATCH;                           /*!< Received address.                                                     */
+  __I  uint32_t  RXCRC;                             /*!< Received CRC.                                                         */
+  __I  uint32_t  DAI;                               /*!< Device address match index.                                           */
+  __I  uint32_t  RESERVED6[60];
+  __IO uint32_t  PACKETPTR;                         /*!< Packet pointer. Decision point: START task.                           */
+  __IO uint32_t  FREQUENCY;                         /*!< Frequency.                                                            */
+  __IO uint32_t  TXPOWER;                           /*!< Output power.                                                         */
+  __IO uint32_t  MODE;                              /*!< Data rate and modulation.                                             */
+  __IO uint32_t  PCNF0;                             /*!< Packet configuration 0.                                               */
+  __IO uint32_t  PCNF1;                             /*!< Packet configuration 1.                                               */
+  __IO uint32_t  BASE0;                             /*!< Radio base address 0. Decision point: START task.                     */
+  __IO uint32_t  BASE1;                             /*!< Radio base address 1. Decision point: START task.                     */
+  __IO uint32_t  PREFIX0;                           /*!< Prefixes bytes for logical addresses 0 to 3.                          */
+  __IO uint32_t  PREFIX1;                           /*!< Prefixes bytes for logical addresses 4 to 7.                          */
+  __IO uint32_t  TXADDRESS;                         /*!< Transmit address select.                                              */
+  __IO uint32_t  RXADDRESSES;                       /*!< Receive address select.                                               */
+  __IO uint32_t  CRCCNF;                            /*!< CRC configuration.                                                    */
+  __IO uint32_t  CRCPOLY;                           /*!< CRC polynomial.                                                       */
+  __IO uint32_t  CRCINIT;                           /*!< CRC initial value.                                                    */
+  __IO uint32_t  TEST;                              /*!< Test features enable register.                                        */
+  __IO uint32_t  TIFS;                              /*!< Inter Frame Spacing in microseconds.                                  */
+  __I  uint32_t  RSSISAMPLE;                        /*!< RSSI sample.                                                          */
+  __I  uint32_t  RESERVED7;
+  __I  uint32_t  STATE;                             /*!< Current radio state.                                                  */
+  __IO uint32_t  DATAWHITEIV;                       /*!< Data whitening initial value.                                         */
+  __I  uint32_t  RESERVED8[2];
+  __IO uint32_t  BCC;                               /*!< Bit counter compare.                                                  */
+  __I  uint32_t  RESERVED9[39];
+  __IO uint32_t  DAB[8];                            /*!< Device address base segment.                                          */
+  __IO uint32_t  DAP[8];                            /*!< Device address prefix.                                                */
+  __IO uint32_t  DACNF;                             /*!< Device address match configuration.                                   */
+  __I  uint32_t  RESERVED10[56];
+  __IO uint32_t  OVERRIDE0;                         /*!< Trim value override register 0.                                       */
+  __IO uint32_t  OVERRIDE1;                         /*!< Trim value override register 1.                                       */
+  __IO uint32_t  OVERRIDE2;                         /*!< Trim value override register 2.                                       */
+  __IO uint32_t  OVERRIDE3;                         /*!< Trim value override register 3.                                       */
+  __IO uint32_t  OVERRIDE4;                         /*!< Trim value override register 4.                                       */
+  __I  uint32_t  RESERVED11[561];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_RADIO_Type;
+
+
+/* ================================================================================ */
+/* ================                      UART                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Universal Asynchronous Receiver/Transmitter. (UART)
+  */
+
+typedef struct {                                    /*!< UART Structure                                                        */
+  __O  uint32_t  TASKS_STARTRX;                     /*!< Start UART receiver.                                                  */
+  __O  uint32_t  TASKS_STOPRX;                      /*!< Stop UART receiver.                                                   */
+  __O  uint32_t  TASKS_STARTTX;                     /*!< Start UART transmitter.                                               */
+  __O  uint32_t  TASKS_STOPTX;                      /*!< Stop UART transmitter.                                                */
+  __I  uint32_t  RESERVED0[3];
+  __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend UART.                                                         */
+  __I  uint32_t  RESERVED1[56];
+  __IO uint32_t  EVENTS_CTS;                        /*!< CTS activated.                                                        */
+  __IO uint32_t  EVENTS_NCTS;                       /*!< CTS deactivated.                                                      */
+  __IO uint32_t  EVENTS_RXDRDY;                     /*!< Data received in RXD.                                                 */
+  __I  uint32_t  RESERVED2[4];
+  __IO uint32_t  EVENTS_TXDRDY;                     /*!< Data sent from TXD.                                                   */
+  __I  uint32_t  RESERVED3;
+  __IO uint32_t  EVENTS_ERROR;                      /*!< Error detected.                                                       */
+  __I  uint32_t  RESERVED4[7];
+  __IO uint32_t  EVENTS_RXTO;                       /*!< Receiver timeout.                                                     */
+  __I  uint32_t  RESERVED5[46];
+  __IO uint32_t  SHORTS;                            /*!< Shortcuts for UART.                                                   */
+  __I  uint32_t  RESERVED6[64];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED7[93];
+  __IO uint32_t  ERRORSRC;                          /*!< Error source. Write error field to 1 to clear error.                  */
+  __I  uint32_t  RESERVED8[31];
+  __IO uint32_t  ENABLE;                            /*!< Enable UART and acquire IOs.                                          */
+  __I  uint32_t  RESERVED9;
+  __IO uint32_t  PSELRTS;                           /*!< Pin select for RTS.                                                   */
+  __IO uint32_t  PSELTXD;                           /*!< Pin select for TXD.                                                   */
+  __IO uint32_t  PSELCTS;                           /*!< Pin select for CTS.                                                   */
+  __IO uint32_t  PSELRXD;                           /*!< Pin select for RXD.                                                   */
+  __I  uint32_t  RXD;                               /*!< RXD register. On read action the buffer pointer is displaced.
+                                                         Once read the character is consumed. If read when no character
+                                                          available, the UART will stop working.                               */
+  __O  uint32_t  TXD;                               /*!< TXD register.                                                         */
+  __I  uint32_t  RESERVED10;
+  __IO uint32_t  BAUDRATE;                          /*!< UART Baudrate.                                                        */
+  __I  uint32_t  RESERVED11[17];
+  __IO uint32_t  CONFIG;                            /*!< Configuration of parity and hardware flow control register.           */
+  __I  uint32_t  RESERVED12[675];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_UART_Type;
+
+
+/* ================================================================================ */
+/* ================                       SPI                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief SPI master 0. (SPI)
+  */
+
+typedef struct {                                    /*!< SPI Structure                                                         */
+  __I  uint32_t  RESERVED0[66];
+  __IO uint32_t  EVENTS_READY;                      /*!< TXD byte sent and RXD byte received.                                  */
+  __I  uint32_t  RESERVED1[126];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED2[125];
+  __IO uint32_t  ENABLE;                            /*!< Enable SPI.                                                           */
+  __I  uint32_t  RESERVED3;
+  __IO uint32_t  PSELSCK;                           /*!< Pin select for SCK.                                                   */
+  __IO uint32_t  PSELMOSI;                          /*!< Pin select for MOSI.                                                  */
+  __IO uint32_t  PSELMISO;                          /*!< Pin select for MISO.                                                  */
+  __I  uint32_t  RESERVED4;
+  __I  uint32_t  RXD;                               /*!< RX data.                                                              */
+  __IO uint32_t  TXD;                               /*!< TX data.                                                              */
+  __I  uint32_t  RESERVED5;
+  __IO uint32_t  FREQUENCY;                         /*!< SPI frequency                                                         */
+  __I  uint32_t  RESERVED6[11];
+  __IO uint32_t  CONFIG;                            /*!< Configuration register.                                               */
+  __I  uint32_t  RESERVED7[681];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_SPI_Type;
+
+
+/* ================================================================================ */
+/* ================                       TWI                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Two-wire interface master 0. (TWI)
+  */
+
+typedef struct {                                    /*!< TWI Structure                                                         */
+  __O  uint32_t  TASKS_STARTRX;                     /*!< Start 2-Wire master receive sequence.                                 */
+  __I  uint32_t  RESERVED0;
+  __O  uint32_t  TASKS_STARTTX;                     /*!< Start 2-Wire master transmit sequence.                                */
+  __I  uint32_t  RESERVED1[2];
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop 2-Wire transaction.                                              */
+  __I  uint32_t  RESERVED2;
+  __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend 2-Wire transaction.                                           */
+  __O  uint32_t  TASKS_RESUME;                      /*!< Resume 2-Wire transaction.                                            */
+  __I  uint32_t  RESERVED3[56];
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< Two-wire stopped.                                                     */
+  __IO uint32_t  EVENTS_RXDREADY;                   /*!< Two-wire ready to deliver new RXD byte received.                      */
+  __I  uint32_t  RESERVED4[4];
+  __IO uint32_t  EVENTS_TXDSENT;                    /*!< Two-wire finished sending last TXD byte.                              */
+  __I  uint32_t  RESERVED5;
+  __IO uint32_t  EVENTS_ERROR;                      /*!< Two-wire error detected.                                              */
+  __I  uint32_t  RESERVED6[4];
+  __IO uint32_t  EVENTS_BB;                         /*!< Two-wire byte boundary.                                               */
+  __I  uint32_t  RESERVED7[3];
+  __IO uint32_t  EVENTS_SUSPENDED;                  /*!< Two-wire suspended.                                                   */
+  __I  uint32_t  RESERVED8[45];
+  __IO uint32_t  SHORTS;                            /*!< Shortcuts for TWI.                                                    */
+  __I  uint32_t  RESERVED9[64];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED10[110];
+  __IO uint32_t  ERRORSRC;                          /*!< Two-wire error source. Write error field to 1 to clear error.         */
+  __I  uint32_t  RESERVED11[14];
+  __IO uint32_t  ENABLE;                            /*!< Enable two-wire master.                                               */
+  __I  uint32_t  RESERVED12;
+  __IO uint32_t  PSELSCL;                           /*!< Pin select for SCL.                                                   */
+  __IO uint32_t  PSELSDA;                           /*!< Pin select for SDA.                                                   */
+  __I  uint32_t  RESERVED13[2];
+  __I  uint32_t  RXD;                               /*!< RX data register.                                                     */
+  __IO uint32_t  TXD;                               /*!< TX data register.                                                     */
+  __I  uint32_t  RESERVED14;
+  __IO uint32_t  FREQUENCY;                         /*!< Two-wire frequency.                                                   */
+  __I  uint32_t  RESERVED15[24];
+  __IO uint32_t  ADDRESS;                           /*!< Address used in the two-wire transfer.                                */
+  __I  uint32_t  RESERVED16[668];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_TWI_Type;
+
+
+/* ================================================================================ */
+/* ================                      SPIS                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief SPI slave 1. (SPIS)
+  */
+
+typedef struct {                                    /*!< SPIS Structure                                                        */
+  __I  uint32_t  RESERVED0[9];
+  __O  uint32_t  TASKS_ACQUIRE;                     /*!< Acquire SPI semaphore.                                                */
+  __O  uint32_t  TASKS_RELEASE;                     /*!< Release SPI semaphore.                                                */
+  __I  uint32_t  RESERVED1[54];
+  __IO uint32_t  EVENTS_END;                        /*!< Granted transaction completed.                                        */
+  __I  uint32_t  RESERVED2[2];
+  __IO uint32_t  EVENTS_ENDRX;                      /*!< End of RXD buffer reached                                             */
+  __I  uint32_t  RESERVED3[5];
+  __IO uint32_t  EVENTS_ACQUIRED;                   /*!< Semaphore acquired.                                                   */
+  __I  uint32_t  RESERVED4[53];
+  __IO uint32_t  SHORTS;                            /*!< Shortcuts for SPIS.                                                   */
+  __I  uint32_t  RESERVED5[64];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED6[61];
+  __I  uint32_t  SEMSTAT;                           /*!< Semaphore status.                                                     */
+  __I  uint32_t  RESERVED7[15];
+  __IO uint32_t  STATUS;                            /*!< Status from last transaction.                                         */
+  __I  uint32_t  RESERVED8[47];
+  __IO uint32_t  ENABLE;                            /*!< Enable SPIS.                                                          */
+  __I  uint32_t  RESERVED9;
+  __IO uint32_t  PSELSCK;                           /*!< Pin select for SCK.                                                   */
+  __IO uint32_t  PSELMISO;                          /*!< Pin select for MISO.                                                  */
+  __IO uint32_t  PSELMOSI;                          /*!< Pin select for MOSI.                                                  */
+  __IO uint32_t  PSELCSN;                           /*!< Pin select for CSN.                                                   */
+  __I  uint32_t  RESERVED10[7];
+  __IO uint32_t  RXDPTR;                            /*!< RX data pointer.                                                      */
+  __IO uint32_t  MAXRX;                             /*!< Maximum number of bytes in the receive buffer.                        */
+  __I  uint32_t  AMOUNTRX;                          /*!< Number of bytes received in last granted transaction.                 */
+  __I  uint32_t  RESERVED11;
+  __IO uint32_t  TXDPTR;                            /*!< TX data pointer.                                                      */
+  __IO uint32_t  MAXTX;                             /*!< Maximum number of bytes in the transmit buffer.                       */
+  __I  uint32_t  AMOUNTTX;                          /*!< Number of bytes transmitted in last granted transaction.              */
+  __I  uint32_t  RESERVED12;
+  __IO uint32_t  CONFIG;                            /*!< Configuration register.                                               */
+  __I  uint32_t  RESERVED13;
+  __IO uint32_t  DEF;                               /*!< Default character.                                                    */
+  __I  uint32_t  RESERVED14[24];
+  __IO uint32_t  ORC;                               /*!< Over-read character.                                                  */
+  __I  uint32_t  RESERVED15[654];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_SPIS_Type;
+
+
+/* ================================================================================ */
+/* ================                     GPIOTE                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief GPIO tasks and events. (GPIOTE)
+  */
+
+typedef struct {                                    /*!< GPIOTE Structure                                                      */
+  __O  uint32_t  TASKS_OUT[4];                      /*!< Tasks asssociated with GPIOTE channels.                               */
+  __I  uint32_t  RESERVED0[60];
+  __IO uint32_t  EVENTS_IN[4];                      /*!< Tasks asssociated with GPIOTE channels.                               */
+  __I  uint32_t  RESERVED1[27];
+  __IO uint32_t  EVENTS_PORT;                       /*!< Event generated from multiple pins.                                   */
+  __I  uint32_t  RESERVED2[97];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED3[129];
+  __IO uint32_t  CONFIG[4];                         /*!< Channel configuration registers.                                      */
+  __I  uint32_t  RESERVED4[695];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_GPIOTE_Type;
+
+
+/* ================================================================================ */
+/* ================                       ADC                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Analog to digital converter. (ADC)
+  */
+
+typedef struct {                                    /*!< ADC Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Start an ADC conversion.                                              */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop ADC.                                                             */
+  __I  uint32_t  RESERVED0[62];
+  __IO uint32_t  EVENTS_END;                        /*!< ADC conversion complete.                                              */
+  __I  uint32_t  RESERVED1[128];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED2[61];
+  __I  uint32_t  BUSY;                              /*!< ADC busy register.                                                    */
+  __I  uint32_t  RESERVED3[63];
+  __IO uint32_t  ENABLE;                            /*!< ADC enable.                                                           */
+  __IO uint32_t  CONFIG;                            /*!< ADC configuration register.                                           */
+  __I  uint32_t  RESULT;                            /*!< Result of ADC conversion.                                             */
+  __I  uint32_t  RESERVED4[700];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_ADC_Type;
+
+
+/* ================================================================================ */
+/* ================                      TIMER                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Timer 0. (TIMER)
+  */
+
+typedef struct {                                    /*!< TIMER Structure                                                       */
+  __O  uint32_t  TASKS_START;                       /*!< Start Timer.                                                          */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop Timer.                                                           */
+  __O  uint32_t  TASKS_COUNT;                       /*!< Increment Timer (In counter mode).                                    */
+  __O  uint32_t  TASKS_CLEAR;                       /*!< Clear timer.                                                          */
+  __O  uint32_t  TASKS_SHUTDOWN;                    /*!< Shutdown timer.                                                       */
+  __I  uint32_t  RESERVED0[11];
+  __O  uint32_t  TASKS_CAPTURE[4];                  /*!< Capture Timer value to CC[n] registers.                               */
+  __I  uint32_t  RESERVED1[60];
+  __IO uint32_t  EVENTS_COMPARE[4];                 /*!< Compare event on CC[n] match.                                         */
+  __I  uint32_t  RESERVED2[44];
+  __IO uint32_t  SHORTS;                            /*!< Shortcuts for Timer.                                                  */
+  __I  uint32_t  RESERVED3[64];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED4[126];
+  __IO uint32_t  MODE;                              /*!< Timer Mode selection.                                                 */
+  __IO uint32_t  BITMODE;                           /*!< Sets timer behaviour.                                                 */
+  __I  uint32_t  RESERVED5;
+  __IO uint32_t  PRESCALER;                         /*!< 4-bit prescaler to source clock frequency (max value 9). Source
+                                                         clock frequency is divided by 2^SCALE.                                */
+  __I  uint32_t  RESERVED6[11];
+  __IO uint32_t  CC[4];                             /*!< Capture/compare registers.                                            */
+  __I  uint32_t  RESERVED7[683];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_TIMER_Type;
+
+
+/* ================================================================================ */
+/* ================                       RTC                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Real time counter 0. (RTC)
+  */
+
+typedef struct {                                    /*!< RTC Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Start RTC Counter.                                                    */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop RTC Counter.                                                     */
+  __O  uint32_t  TASKS_CLEAR;                       /*!< Clear RTC Counter.                                                    */
+  __O  uint32_t  TASKS_TRIGOVRFLW;                  /*!< Set COUNTER to 0xFFFFFFF0.                                            */
+  __I  uint32_t  RESERVED0[60];
+  __IO uint32_t  EVENTS_TICK;                       /*!< Event on COUNTER increment.                                           */
+  __IO uint32_t  EVENTS_OVRFLW;                     /*!< Event on COUNTER overflow.                                            */
+  __I  uint32_t  RESERVED1[14];
+  __IO uint32_t  EVENTS_COMPARE[4];                 /*!< Compare event on CC[n] match.                                         */
+  __I  uint32_t  RESERVED2[109];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED3[13];
+  __IO uint32_t  EVTEN;                             /*!< Configures event enable routing to PPI for each RTC event.            */
+  __IO uint32_t  EVTENSET;                          /*!< Enable events routing to PPI. The reading of this register gives
+                                                         the value of EVTEN.                                                   */
+  __IO uint32_t  EVTENCLR;                          /*!< Disable events routing to PPI. The reading of this register
+                                                         gives the value of EVTEN.                                             */
+  __I  uint32_t  RESERVED4[110];
+  __I  uint32_t  COUNTER;                           /*!< Current COUNTER value.                                                */
+  __IO uint32_t  PRESCALER;                         /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
+                                                         Must be written when RTC is STOPed.                                   */
+  __I  uint32_t  RESERVED5[13];
+  __IO uint32_t  CC[4];                             /*!< Capture/compare registers.                                            */
+  __I  uint32_t  RESERVED6[683];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_RTC_Type;
+
+
+/* ================================================================================ */
+/* ================                      TEMP                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Temperature Sensor. (TEMP)
+  */
+
+typedef struct {                                    /*!< TEMP Structure                                                        */
+  __O  uint32_t  TASKS_START;                       /*!< Start temperature measurement.                                        */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop temperature measurement.                                         */
+  __I  uint32_t  RESERVED0[62];
+  __IO uint32_t  EVENTS_DATARDY;                    /*!< Temperature measurement complete, data ready event.                   */
+  __I  uint32_t  RESERVED1[128];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED2[127];
+  __I  int32_t   TEMP;                              /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision.   */
+  __I  uint32_t  RESERVED3[700];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_TEMP_Type;
+
+
+/* ================================================================================ */
+/* ================                       RNG                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Random Number Generator. (RNG)
+  */
+
+typedef struct {                                    /*!< RNG Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Start the random number generator.                                    */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop the random number generator.                                     */
+  __I  uint32_t  RESERVED0[62];
+  __IO uint32_t  EVENTS_VALRDY;                     /*!< New random number generated and written to VALUE register.            */
+  __I  uint32_t  RESERVED1[63];
+  __IO uint32_t  SHORTS;                            /*!< Shortcuts for the RNG.                                                */
+  __I  uint32_t  RESERVED2[64];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register                                         */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register                                       */
+  __I  uint32_t  RESERVED3[126];
+  __IO uint32_t  CONFIG;                            /*!< Configuration register.                                               */
+  __I  uint32_t  VALUE;                             /*!< RNG random number.                                                    */
+  __I  uint32_t  RESERVED4[700];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_RNG_Type;
+
+
+/* ================================================================================ */
+/* ================                       ECB                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief AES ECB Mode Encryption. (ECB)
+  */
+
+typedef struct {                                    /*!< ECB Structure                                                         */
+  __O  uint32_t  TASKS_STARTECB;                    /*!< Start ECB block encrypt. If a crypto operation is running, this
+                                                         will not initiate a new encryption and the ERRORECB event will
+                                                          be triggered.                                                        */
+  __O  uint32_t  TASKS_STOPECB;                     /*!< Stop current ECB encryption. If a crypto operation is running,
+                                                         this will will trigger the ERRORECB event.                            */
+  __I  uint32_t  RESERVED0[62];
+  __IO uint32_t  EVENTS_ENDECB;                     /*!< ECB block encrypt complete.                                           */
+  __IO uint32_t  EVENTS_ERRORECB;                   /*!< ECB block encrypt aborted due to a STOPECB task or due to an
+                                                         error.                                                                */
+  __I  uint32_t  RESERVED1[127];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED2[126];
+  __IO uint32_t  ECBDATAPTR;                        /*!< ECB block encrypt memory pointer.                                     */
+  __I  uint32_t  RESERVED3[701];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_ECB_Type;
+
+
+/* ================================================================================ */
+/* ================                       AAR                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Accelerated Address Resolver. (AAR)
+  */
+
+typedef struct {                                    /*!< AAR Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Start resolving addresses based on IRKs specified in the IRK
+                                                         data structure.                                                       */
+  __I  uint32_t  RESERVED0;
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop resolving addresses.                                             */
+  __I  uint32_t  RESERVED1[61];
+  __IO uint32_t  EVENTS_END;                        /*!< Address resolution procedure completed.                               */
+  __IO uint32_t  EVENTS_RESOLVED;                   /*!< Address resolved.                                                     */
+  __IO uint32_t  EVENTS_NOTRESOLVED;                /*!< Address not resolved.                                                 */
+  __I  uint32_t  RESERVED2[126];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED3[61];
+  __I  uint32_t  STATUS;                            /*!< Resolution status.                                                    */
+  __I  uint32_t  RESERVED4[63];
+  __IO uint32_t  ENABLE;                            /*!< Enable AAR.                                                           */
+  __IO uint32_t  NIRK;                              /*!< Number of Identity root Keys in the IRK data structure.               */
+  __IO uint32_t  IRKPTR;                            /*!< Pointer to the IRK data structure.                                    */
+  __I  uint32_t  RESERVED5;
+  __IO uint32_t  ADDRPTR;                           /*!< Pointer to the resolvable address (6 bytes).                          */
+  __IO uint32_t  SCRATCHPTR;                        /*!< Pointer to a scratch data area used for temporary storage during
+                                                         resolution. A minimum of 3 bytes must be reserved.                    */
+  __I  uint32_t  RESERVED6[697];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_AAR_Type;
+
+
+/* ================================================================================ */
+/* ================                       CCM                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief AES CCM Mode Encryption. (CCM)
+  */
+
+typedef struct {                                    /*!< CCM Structure                                                         */
+  __O  uint32_t  TASKS_KSGEN;                       /*!< Start generation of key-stream. This operation will stop by
+                                                         itself when completed.                                                */
+  __O  uint32_t  TASKS_CRYPT;                       /*!< Start encrypt/decrypt. This operation will stop by itself when
+                                                         completed.                                                            */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop encrypt/decrypt.                                                 */
+  __I  uint32_t  RESERVED0[61];
+  __IO uint32_t  EVENTS_ENDKSGEN;                   /*!< Keystream generation completed.                                       */
+  __IO uint32_t  EVENTS_ENDCRYPT;                   /*!< Encrypt/decrypt completed.                                            */
+  __IO uint32_t  EVENTS_ERROR;                      /*!< Error happened.                                                       */
+  __I  uint32_t  RESERVED1[61];
+  __IO uint32_t  SHORTS;                            /*!< Shortcuts for the CCM.                                                */
+  __I  uint32_t  RESERVED2[64];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED3[61];
+  __I  uint32_t  MICSTATUS;                         /*!< CCM RX MIC check result.                                              */
+  __I  uint32_t  RESERVED4[63];
+  __IO uint32_t  ENABLE;                            /*!< CCM enable.                                                           */
+  __IO uint32_t  MODE;                              /*!< Operation mode.                                                       */
+  __IO uint32_t  CNFPTR;                            /*!< Pointer to a data structure holding AES key and NONCE vector.         */
+  __IO uint32_t  INPTR;                             /*!< Pointer to the input packet.                                          */
+  __IO uint32_t  OUTPTR;                            /*!< Pointer to the output packet.                                         */
+  __IO uint32_t  SCRATCHPTR;                        /*!< Pointer to a scratch data area used for temporary storage during
+                                                         resolution. A minimum of 43 bytes must be reserved.                   */
+  __I  uint32_t  RESERVED5[697];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_CCM_Type;
+
+
+/* ================================================================================ */
+/* ================                       WDT                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Watchdog Timer. (WDT)
+  */
+
+typedef struct {                                    /*!< WDT Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Start the watchdog.                                                   */
+  __I  uint32_t  RESERVED0[63];
+  __IO uint32_t  EVENTS_TIMEOUT;                    /*!< Watchdog timeout.                                                     */
+  __I  uint32_t  RESERVED1[128];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED2[61];
+  __I  uint32_t  RUNSTATUS;                         /*!< Watchdog running status.                                              */
+  __I  uint32_t  REQSTATUS;                         /*!< Request status.                                                       */
+  __I  uint32_t  RESERVED3[63];
+  __IO uint32_t  CRV;                               /*!< Counter reload value in number of 32kiHz clock cycles.                */
+  __IO uint32_t  RREN;                              /*!< Reload request enable.                                                */
+  __IO uint32_t  CONFIG;                            /*!< Configuration register.                                               */
+  __I  uint32_t  RESERVED4[60];
+  __O  uint32_t  RR[8];                             /*!< Reload requests registers.                                            */
+  __I  uint32_t  RESERVED5[631];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_WDT_Type;
+
+
+/* ================================================================================ */
+/* ================                      QDEC                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Rotary decoder. (QDEC)
+  */
+
+typedef struct {                                    /*!< QDEC Structure                                                        */
+  __O  uint32_t  TASKS_START;                       /*!< Start the quadrature decoder.                                         */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop the quadrature decoder.                                          */
+  __O  uint32_t  TASKS_READCLRACC;                  /*!< Transfers the content from ACC registers to ACCREAD registers,
+                                                         and clears the ACC registers.                                         */
+  __I  uint32_t  RESERVED0[61];
+  __IO uint32_t  EVENTS_SAMPLERDY;                  /*!< A new sample is written to the sample register.                       */
+  __IO uint32_t  EVENTS_REPORTRDY;                  /*!< REPORTPER number of samples accumulated in ACC register, and
+                                                         ACC register different than zero.                                     */
+  __IO uint32_t  EVENTS_ACCOF;                      /*!< ACC or ACCDBL register overflow.                                      */
+  __I  uint32_t  RESERVED1[61];
+  __IO uint32_t  SHORTS;                            /*!< Shortcuts for the QDEC.                                               */
+  __I  uint32_t  RESERVED2[64];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED3[125];
+  __IO uint32_t  ENABLE;                            /*!< Enable the QDEC.                                                      */
+  __IO uint32_t  LEDPOL;                            /*!< LED output pin polarity.                                              */
+  __IO uint32_t  SAMPLEPER;                         /*!< Sample period.                                                        */
+  __I  int32_t   SAMPLE;                            /*!< Motion sample value.                                                  */
+  __IO uint32_t  REPORTPER;                         /*!< Number of samples to generate an EVENT_REPORTRDY.                     */
+  __I  int32_t   ACC;                               /*!< Accumulated valid transitions register.                               */
+  __I  int32_t   ACCREAD;                           /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
+                                                         task.                                                                 */
+  __IO uint32_t  PSELLED;                           /*!< Pin select for LED output.                                            */
+  __IO uint32_t  PSELA;                             /*!< Pin select for phase A input.                                         */
+  __IO uint32_t  PSELB;                             /*!< Pin select for phase B input.                                         */
+  __IO uint32_t  DBFEN;                             /*!< Enable debouncer input filters.                                       */
+  __I  uint32_t  RESERVED4[5];
+  __IO uint32_t  LEDPRE;                            /*!< Time LED is switched ON before the sample.                            */
+  __I  uint32_t  ACCDBL;                            /*!< Accumulated double (error) transitions register.                      */
+  __I  uint32_t  ACCDBLREAD;                        /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
+                                                         task.                                                                 */
+  __I  uint32_t  RESERVED5[684];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_QDEC_Type;
+
+
+/* ================================================================================ */
+/* ================                     LPCOMP                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Low power comparator. (LPCOMP)
+  */
+
+typedef struct {                                    /*!< LPCOMP Structure                                                      */
+  __O  uint32_t  TASKS_START;                       /*!< Start the comparator.                                                 */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop the comparator.                                                  */
+  __O  uint32_t  TASKS_SAMPLE;                      /*!< Sample comparator value.                                              */
+  __I  uint32_t  RESERVED0[61];
+  __IO uint32_t  EVENTS_READY;                      /*!< LPCOMP is ready and output is valid.                                  */
+  __IO uint32_t  EVENTS_DOWN;                       /*!< Input voltage crossed the threshold going down.                       */
+  __IO uint32_t  EVENTS_UP;                         /*!< Input voltage crossed the threshold going up.                         */
+  __IO uint32_t  EVENTS_CROSS;                      /*!< Input voltage crossed the threshold in any direction.                 */
+  __I  uint32_t  RESERVED1[60];
+  __IO uint32_t  SHORTS;                            /*!< Shortcuts for the LPCOMP.                                             */
+  __I  uint32_t  RESERVED2[64];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED3[61];
+  __I  uint32_t  RESULT;                            /*!< Result of last compare.                                               */
+  __I  uint32_t  RESERVED4[63];
+  __IO uint32_t  ENABLE;                            /*!< Enable the LPCOMP.                                                    */
+  __IO uint32_t  PSEL;                              /*!< Input pin select.                                                     */
+  __IO uint32_t  REFSEL;                            /*!< Reference select.                                                     */
+  __IO uint32_t  EXTREFSEL;                         /*!< External reference select.                                            */
+  __I  uint32_t  RESERVED5[4];
+  __IO uint32_t  ANADETECT;                         /*!< Analog detect configuration.                                          */
+  __I  uint32_t  RESERVED6[694];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_LPCOMP_Type;
+
+
+/* ================================================================================ */
+/* ================                       SWI                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief SW Interrupts. (SWI)
+  */
+
+typedef struct {                                    /*!< SWI Structure                                                         */
+  __I  uint32_t  UNUSED;                            /*!< Unused.                                                               */
+} NRF_SWI_Type;
+
+
+/* ================================================================================ */
+/* ================                      NVMC                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Non Volatile Memory Controller. (NVMC)
+  */
+
+typedef struct {                                    /*!< NVMC Structure                                                        */
+  __I  uint32_t  RESERVED0[256];
+  __I  uint32_t  READY;                             /*!< Ready flag.                                                           */
+  __I  uint32_t  RESERVED1[64];
+  __IO uint32_t  CONFIG;                            /*!< Configuration register.                                               */
+  
+  union {
+    __IO uint32_t  ERASEPCR1;                       /*!< Register for erasing a non-protected non-volatile memory page.        */
+    __IO uint32_t  ERASEPAGE;                       /*!< Register for erasing a non-protected non-volatile memory page.        */
+  };
+  __IO uint32_t  ERASEALL;                          /*!< Register for erasing all non-volatile user memory.                    */
+  __IO uint32_t  ERASEPCR0;                         /*!< Register for erasing a protected non-volatile memory page.            */
+  __IO uint32_t  ERASEUICR;                         /*!< Register for start erasing User Information Congfiguration Registers. */
+} NRF_NVMC_Type;
+
+
+/* ================================================================================ */
+/* ================                       PPI                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief PPI controller. (PPI)
+  */
+
+typedef struct {                                    /*!< PPI Structure                                                         */
+  PPI_TASKS_CHG_Type TASKS_CHG[4];                  /*!< Channel group tasks.                                                  */
+  __I  uint32_t  RESERVED0[312];
+  __IO uint32_t  CHEN;                              /*!< Channel enable.                                                       */
+  __IO uint32_t  CHENSET;                           /*!< Channel enable set.                                                   */
+  __IO uint32_t  CHENCLR;                           /*!< Channel enable clear.                                                 */
+  __I  uint32_t  RESERVED1;
+  PPI_CH_Type CH[16];                               /*!< PPI Channel.                                                          */
+  __I  uint32_t  RESERVED2[156];
+  __IO uint32_t  CHG[4];                            /*!< Channel group configuration.                                          */
+} NRF_PPI_Type;
+
+
+/* ================================================================================ */
+/* ================                      FICR                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Factory Information Configuration. (FICR)
+  */
+
+typedef struct {                                    /*!< FICR Structure                                                        */
+  __I  uint32_t  RESERVED0[4];
+  __I  uint32_t  CODEPAGESIZE;                      /*!< Code memory page size in bytes.                                       */
+  __I  uint32_t  CODESIZE;                          /*!< Code memory size in pages.                                            */
+  __I  uint32_t  RESERVED1[4];
+  __I  uint32_t  CLENR0;                            /*!< Length of code region 0 in bytes.                                     */
+  __I  uint32_t  PPFC;                              /*!< Pre-programmed factory code present.                                  */
+  __I  uint32_t  RESERVED2;
+  __I  uint32_t  NUMRAMBLOCK;                       /*!< Number of individualy controllable RAM blocks.                        */
+  
+  union {
+    __I  uint32_t  SIZERAMBLOCK[4];                 /*!< Deprecated array of size of RAM block in bytes. This name is
+                                                         kept for backward compatinility purposes. Use SIZERAMBLOCKS
+                                                          instead.                                                             */
+    __I  uint32_t  SIZERAMBLOCKS;                   /*!< Size of RAM blocks in bytes.                                          */
+  };
+  __I  uint32_t  RESERVED3[5];
+  __I  uint32_t  CONFIGID;                          /*!< Configuration identifier.                                             */
+  __I  uint32_t  DEVICEID[2];                       /*!< Device identifier.                                                    */
+  __I  uint32_t  RESERVED4[6];
+  __I  uint32_t  ER[4];                             /*!< Encryption root.                                                      */
+  __I  uint32_t  IR[4];                             /*!< Identity root.                                                        */
+  __I  uint32_t  DEVICEADDRTYPE;                    /*!< Device address type.                                                  */
+  __I  uint32_t  DEVICEADDR[2];                     /*!< Device address.                                                       */
+  __I  uint32_t  OVERRIDEEN;                        /*!< Radio calibration override enable.                                    */
+  __I  uint32_t  NRF_1MBIT[5];                      /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit
+                                                         mode.                                                                 */
+  __I  uint32_t  RESERVED5[10];
+  __I  uint32_t  BLE_1MBIT[5];                      /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
+                                                         mode.                                                                 */
+} NRF_FICR_Type;
+
+
+/* ================================================================================ */
+/* ================                      UICR                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief User Information Configuration. (UICR)
+  */
+
+typedef struct {                                    /*!< UICR Structure                                                        */
+  __IO uint32_t  CLENR0;                            /*!< Length of code region 0.                                              */
+  __IO uint32_t  RBPCONF;                           /*!< Readback protection configuration.                                    */
+  __IO uint32_t  XTALFREQ;                          /*!< Reset value for CLOCK XTALFREQ register.                              */
+  __I  uint32_t  RESERVED0;
+  __I  uint32_t  FWID;                              /*!< Firmware ID.                                                          */
+  
+  union {
+    __IO uint32_t  NRFFW[15];                       /*!< Reserved for Nordic firmware design.                                  */
+    __IO uint32_t  BOOTLOADERADDR;                  /*!< Bootloader start address.                                             */
+  };
+  __IO uint32_t  NRFHW[12];                         /*!< Reserved for Nordic hardware design.                                  */
+  __IO uint32_t  CUSTOMER[32];                      /*!< Reserved for customer.                                                */
+} NRF_UICR_Type;
+
+
+/* ================================================================================ */
+/* ================                      GPIO                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief General purpose input and output. (GPIO)
+  */
+
+typedef struct {                                    /*!< GPIO Structure                                                        */
+  __I  uint32_t  RESERVED0[321];
+  __IO uint32_t  OUT;                               /*!< Write GPIO port.                                                      */
+  __IO uint32_t  OUTSET;                            /*!< Set individual bits in GPIO port.                                     */
+  __IO uint32_t  OUTCLR;                            /*!< Clear individual bits in GPIO port.                                   */
+  __I  uint32_t  IN;                                /*!< Read GPIO port.                                                       */
+  __IO uint32_t  DIR;                               /*!< Direction of GPIO pins.                                               */
+  __IO uint32_t  DIRSET;                            /*!< DIR set register.                                                     */
+  __IO uint32_t  DIRCLR;                            /*!< DIR clear register.                                                   */
+  __I  uint32_t  RESERVED1[120];
+  __IO uint32_t  PIN_CNF[32];                       /*!< Configuration of GPIO pins.                                           */
+} NRF_GPIO_Type;
+
+
+/* --------------------  End of section using anonymous unions  ------------------- */
+#if defined(__CC_ARM)
+  #pragma pop
+#elif defined(__ICCARM__)
+  /* leave anonymous unions enabled */
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+  /* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+  #pragma warning restore
+#else
+  #warning Not supported compiler type
+#endif
+
+
+
+
+/* ================================================================================ */
+/* ================              Peripheral memory map             ================ */
+/* ================================================================================ */
+
+#define NRF_POWER_BASE                  0x40000000UL
+#define NRF_CLOCK_BASE                  0x40000000UL
+#define NRF_MPU_BASE                    0x40000000UL
+#define NRF_RADIO_BASE                  0x40001000UL
+#define NRF_UART0_BASE                  0x40002000UL
+#define NRF_SPI0_BASE                   0x40003000UL
+#define NRF_TWI0_BASE                   0x40003000UL
+#define NRF_SPI1_BASE                   0x40004000UL
+#define NRF_TWI1_BASE                   0x40004000UL
+#define NRF_SPIS1_BASE                  0x40004000UL
+#define NRF_GPIOTE_BASE                 0x40006000UL
+#define NRF_ADC_BASE                    0x40007000UL
+#define NRF_TIMER0_BASE                 0x40008000UL
+#define NRF_TIMER1_BASE                 0x40009000UL
+#define NRF_TIMER2_BASE                 0x4000A000UL
+#define NRF_RTC0_BASE                   0x4000B000UL
+#define NRF_TEMP_BASE                   0x4000C000UL
+#define NRF_RNG_BASE                    0x4000D000UL
+#define NRF_ECB_BASE                    0x4000E000UL
+#define NRF_AAR_BASE                    0x4000F000UL
+#define NRF_CCM_BASE                    0x4000F000UL
+#define NRF_WDT_BASE                    0x40010000UL
+#define NRF_RTC1_BASE                   0x40011000UL
+#define NRF_QDEC_BASE                   0x40012000UL
+#define NRF_LPCOMP_BASE                 0x40013000UL
+#define NRF_SWI_BASE                    0x40014000UL
+#define NRF_NVMC_BASE                   0x4001E000UL
+#define NRF_PPI_BASE                    0x4001F000UL
+#define NRF_FICR_BASE                   0x10000000UL
+#define NRF_UICR_BASE                   0x10001000UL
+#define NRF_GPIO_BASE                   0x50000000UL
+
+
+/* ================================================================================ */
+/* ================             Peripheral declaration             ================ */
+/* ================================================================================ */
+
+#define NRF_POWER                       ((NRF_POWER_Type          *) NRF_POWER_BASE)
+#define NRF_CLOCK                       ((NRF_CLOCK_Type          *) NRF_CLOCK_BASE)
+#define NRF_MPU                         ((NRF_MPU_Type            *) NRF_MPU_BASE)
+#define NRF_RADIO                       ((NRF_RADIO_Type          *) NRF_RADIO_BASE)
+#define NRF_UART0                       ((NRF_UART_Type           *) NRF_UART0_BASE)
+#define NRF_SPI0                        ((NRF_SPI_Type            *) NRF_SPI0_BASE)
+#define NRF_TWI0                        ((NRF_TWI_Type            *) NRF_TWI0_BASE)
+#define NRF_SPI1                        ((NRF_SPI_Type            *) NRF_SPI1_BASE)
+#define NRF_TWI1                        ((NRF_TWI_Type            *) NRF_TWI1_BASE)
+#define NRF_SPIS1                       ((NRF_SPIS_Type           *) NRF_SPIS1_BASE)
+#define NRF_GPIOTE                      ((NRF_GPIOTE_Type         *) NRF_GPIOTE_BASE)
+#define NRF_ADC                         ((NRF_ADC_Type            *) NRF_ADC_BASE)
+#define NRF_TIMER0                      ((NRF_TIMER_Type          *) NRF_TIMER0_BASE)
+#define NRF_TIMER1                      ((NRF_TIMER_Type          *) NRF_TIMER1_BASE)
+#define NRF_TIMER2                      ((NRF_TIMER_Type          *) NRF_TIMER2_BASE)
+#define NRF_RTC0                        ((NRF_RTC_Type            *) NRF_RTC0_BASE)
+#define NRF_TEMP                        ((NRF_TEMP_Type           *) NRF_TEMP_BASE)
+#define NRF_RNG                         ((NRF_RNG_Type            *) NRF_RNG_BASE)
+#define NRF_ECB                         ((NRF_ECB_Type            *) NRF_ECB_BASE)
+#define NRF_AAR                         ((NRF_AAR_Type            *) NRF_AAR_BASE)
+#define NRF_CCM                         ((NRF_CCM_Type            *) NRF_CCM_BASE)
+#define NRF_WDT                         ((NRF_WDT_Type            *) NRF_WDT_BASE)
+#define NRF_RTC1                        ((NRF_RTC_Type            *) NRF_RTC1_BASE)
+#define NRF_QDEC                        ((NRF_QDEC_Type           *) NRF_QDEC_BASE)
+#define NRF_LPCOMP                      ((NRF_LPCOMP_Type         *) NRF_LPCOMP_BASE)
+#define NRF_SWI                         ((NRF_SWI_Type            *) NRF_SWI_BASE)
+#define NRF_NVMC                        ((NRF_NVMC_Type           *) NRF_NVMC_BASE)
+#define NRF_PPI                         ((NRF_PPI_Type            *) NRF_PPI_BASE)
+#define NRF_FICR                        ((NRF_FICR_Type           *) NRF_FICR_BASE)
+#define NRF_UICR                        ((NRF_UICR_Type           *) NRF_UICR_BASE)
+#define NRF_GPIO                        ((NRF_GPIO_Type           *) NRF_GPIO_BASE)
+
+
+/** @} */ /* End of group Device_Peripheral_Registers */
+/** @} */ /* End of group nrf51 */
+/** @} */ /* End of group Nordic Semiconductor */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif  /* nrf51_H */
+
diff --git a/ports/nrf/device/nrf51/nrf51_bitfields.h b/ports/nrf/device/nrf51/nrf51_bitfields.h
new file mode 100644
index 0000000000..22c2c21e55
--- /dev/null
+++ b/ports/nrf/device/nrf51/nrf51_bitfields.h
@@ -0,0 +1,6129 @@
+/* Copyright (c) 2016, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *   * Redistributions of source code must retain the above copyright notice, this
+ *     list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *
+ *   * Neither the name of Nordic Semiconductor ASA nor the names of its
+ *     contributors may be used to endorse or promote products derived from
+ *     this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+ 
+#ifndef __NRF51_BITS_H
+#define __NRF51_BITS_H
+
+/*lint ++flb "Enter library region" */
+
+/* Peripheral: AAR */
+/* Description: Accelerated Address Resolver. */
+
+/* Register: AAR_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 2 : Enable interrupt on NOTRESOLVED event. */
+#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
+#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
+#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
+#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
+#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on RESOLVED event. */
+#define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
+#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
+#define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
+#define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
+#define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 0 : Enable interrupt on END event. */
+#define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
+#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define AAR_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
+#define AAR_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
+#define AAR_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: AAR_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 2 : Disable interrupt on NOTRESOLVED event. */
+#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
+#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
+#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
+#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
+#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on RESOLVED event. */
+#define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
+#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
+#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
+#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
+#define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 0 : Disable interrupt on ENDKSGEN event. */
+#define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
+#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define AAR_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
+#define AAR_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
+#define AAR_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: AAR_STATUS */
+/* Description: Resolution status. */
+
+/* Bits 3..0 : The IRK used last time an address was resolved. */
+#define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
+
+/* Register: AAR_ENABLE */
+/* Description: Enable AAR. */
+
+/* Bits 1..0 : Enable AAR. */
+#define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define AAR_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled AAR. */
+#define AAR_ENABLE_ENABLE_Enabled (0x03UL) /*!< Enable AAR. */
+
+/* Register: AAR_NIRK */
+/* Description: Number of Identity root Keys in the IRK data structure. */
+
+/* Bits 4..0 : Number of Identity root Keys in the IRK data structure. */
+#define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
+#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
+
+/* Register: AAR_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define AAR_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define AAR_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define AAR_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: ADC */
+/* Description: Analog to digital converter. */
+
+/* Register: ADC_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 0 : Enable interrupt on END event. */
+#define ADC_INTENSET_END_Pos (0UL) /*!< Position of END field. */
+#define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define ADC_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
+#define ADC_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
+#define ADC_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: ADC_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 0 : Disable interrupt on END event. */
+#define ADC_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
+#define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define ADC_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
+#define ADC_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
+#define ADC_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: ADC_BUSY */
+/* Description: ADC busy register. */
+
+/* Bit 0 : ADC busy register. */
+#define ADC_BUSY_BUSY_Pos (0UL) /*!< Position of BUSY field. */
+#define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos) /*!< Bit mask of BUSY field. */
+#define ADC_BUSY_BUSY_Ready (0UL) /*!< No ongoing ADC conversion is taking place. ADC is ready. */
+#define ADC_BUSY_BUSY_Busy (1UL) /*!< An ADC conversion is taking place. ADC is busy. */
+
+/* Register: ADC_ENABLE */
+/* Description: ADC enable. */
+
+/* Bits 1..0 : ADC enable. */
+#define ADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define ADC_ENABLE_ENABLE_Disabled (0x00UL) /*!< ADC is disabled. */
+#define ADC_ENABLE_ENABLE_Enabled (0x01UL) /*!< ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. */
+
+/* Register: ADC_CONFIG */
+/* Description: ADC configuration register. */
+
+/* Bits 17..16 : ADC external reference pin selection. */
+#define ADC_CONFIG_EXTREFSEL_Pos (16UL) /*!< Position of EXTREFSEL field. */
+#define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
+#define ADC_CONFIG_EXTREFSEL_None (0UL) /*!< Analog external reference inputs disabled. */
+#define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL) /*!< Use analog reference 0 as reference. */
+#define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /*!< Use analog reference 1 as reference. */
+
+/* Bits 15..8 : ADC analog pin selection. */
+#define ADC_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
+#define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
+#define ADC_CONFIG_PSEL_Disabled (0UL) /*!< Analog input pins disabled. */
+#define ADC_CONFIG_PSEL_AnalogInput0 (1UL) /*!< Use analog input 0 as analog input. */
+#define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /*!< Use analog input 1 as analog input. */
+#define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /*!< Use analog input 2 as analog input. */
+#define ADC_CONFIG_PSEL_AnalogInput3 (8UL) /*!< Use analog input 3 as analog input. */
+#define ADC_CONFIG_PSEL_AnalogInput4 (16UL) /*!< Use analog input 4 as analog input. */
+#define ADC_CONFIG_PSEL_AnalogInput5 (32UL) /*!< Use analog input 5 as analog input. */
+#define ADC_CONFIG_PSEL_AnalogInput6 (64UL) /*!< Use analog input 6 as analog input. */
+#define ADC_CONFIG_PSEL_AnalogInput7 (128UL) /*!< Use analog input 7 as analog input. */
+
+/* Bits 6..5 : ADC reference selection. */
+#define ADC_CONFIG_REFSEL_Pos (5UL) /*!< Position of REFSEL field. */
+#define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
+#define ADC_CONFIG_REFSEL_VBG (0x00UL) /*!< Use internal 1.2V bandgap voltage as reference for conversion. */
+#define ADC_CONFIG_REFSEL_External (0x01UL) /*!< Use external source configured by EXTREFSEL as reference for conversion. */
+#define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /*!< Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. */
+#define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL) /*!< Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. */
+
+/* Bits 4..2 : ADC input selection. */
+#define ADC_CONFIG_INPSEL_Pos (2UL) /*!< Position of INPSEL field. */
+#define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos) /*!< Bit mask of INPSEL field. */
+#define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL) /*!< Analog input specified by PSEL with no prescaling used as input for the conversion. */
+#define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL) /*!< Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. */
+#define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL) /*!< Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. */
+#define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /*!< Supply voltage with 2/3 prescaling used as input for the conversion. */
+#define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL) /*!< Supply voltage with 1/3 prescaling used as input for the conversion. */
+
+/* Bits 1..0 : ADC resolution. */
+#define ADC_CONFIG_RES_Pos (0UL) /*!< Position of RES field. */
+#define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos) /*!< Bit mask of RES field. */
+#define ADC_CONFIG_RES_8bit (0x00UL) /*!< 8bit ADC resolution. */
+#define ADC_CONFIG_RES_9bit (0x01UL) /*!< 9bit ADC resolution. */
+#define ADC_CONFIG_RES_10bit (0x02UL) /*!< 10bit ADC resolution. */
+
+/* Register: ADC_RESULT */
+/* Description: Result of ADC conversion. */
+
+/* Bits 9..0 : Result of ADC conversion. */
+#define ADC_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
+#define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
+
+/* Register: ADC_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define ADC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define ADC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define ADC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: CCM */
+/* Description: AES CCM Mode Encryption. */
+
+/* Register: CCM_SHORTS */
+/* Description: Shortcuts for the CCM. */
+
+/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task. */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Shortcut disabled. */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Register: CCM_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 2 : Enable interrupt on ERROR event. */
+#define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
+#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
+#define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
+#define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on ENDCRYPT event. */
+#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
+#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
+#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */
+#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */
+#define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 0 : Enable interrupt on ENDKSGEN event. */
+#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
+#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
+#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */
+#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */
+#define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: CCM_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 2 : Disable interrupt on ERROR event. */
+#define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
+#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
+#define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
+#define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on ENDCRYPT event. */
+#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
+#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
+#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */
+#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */
+#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 0 : Disable interrupt on ENDKSGEN event. */
+#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
+#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
+#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */
+#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */
+#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: CCM_MICSTATUS */
+/* Description: CCM RX MIC check result. */
+
+/* Bit 0 : Result of the MIC check performed during the previous CCM RX STARTCRYPT */
+#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
+#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
+#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed. */
+#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed. */
+
+/* Register: CCM_ENABLE */
+/* Description: CCM enable. */
+
+/* Bits 1..0 : CCM enable. */
+#define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define CCM_ENABLE_ENABLE_Disabled (0x00UL) /*!< CCM is disabled. */
+#define CCM_ENABLE_ENABLE_Enabled (0x02UL) /*!< CCM is enabled. */
+
+/* Register: CCM_MODE */
+/* Description: Operation mode. */
+
+/* Bit 0 : CCM mode operation. */
+#define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define CCM_MODE_MODE_Encryption (0UL) /*!< CCM mode TX */
+#define CCM_MODE_MODE_Decryption (1UL) /*!< CCM mode TX */
+
+/* Register: CCM_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define CCM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define CCM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define CCM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: CLOCK */
+/* Description: Clock control. */
+
+/* Register: CLOCK_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 4 : Enable interrupt on CTTO event. */
+#define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
+#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
+#define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Interrupt disabled. */
+#define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Interrupt enabled. */
+#define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 3 : Enable interrupt on DONE event. */
+#define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */
+#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
+#define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Interrupt disabled. */
+#define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Interrupt enabled. */
+#define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on LFCLKSTARTED event. */
+#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
+#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
+#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
+#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
+#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 0 : Enable interrupt on HFCLKSTARTED event. */
+#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
+#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
+#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
+#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
+#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: CLOCK_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 4 : Disable interrupt on CTTO event. */
+#define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
+#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
+#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Interrupt disabled. */
+#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Interrupt enabled. */
+#define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 3 : Disable interrupt on DONE event. */
+#define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */
+#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
+#define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Interrupt disabled. */
+#define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Interrupt enabled. */
+#define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on LFCLKSTARTED event. */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 0 : Disable interrupt on HFCLKSTARTED event. */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: CLOCK_HFCLKRUN */
+/* Description: Task HFCLKSTART trigger status. */
+
+/* Bit 0 : Task HFCLKSTART trigger status. */
+#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
+#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task HFCLKSTART has not been triggered. */
+#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task HFCLKSTART has been triggered. */
+
+/* Register: CLOCK_HFCLKSTAT */
+/* Description: High frequency clock status. */
+
+/* Bit 16 : State for the HFCLK. */
+#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
+#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
+#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK clock not running. */
+#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK clock running. */
+
+/* Bit 0 : Active clock source for the HF clock. */
+#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< Internal 16MHz RC oscillator running and generating the HFCLK clock. */
+#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. */
+
+/* Register: CLOCK_LFCLKRUN */
+/* Description: Task LFCLKSTART triggered status. */
+
+/* Bit 0 : Task LFCLKSTART triggered status. */
+#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
+#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task LFCLKSTART has not been triggered. */
+#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task LFCLKSTART has been triggered. */
+
+/* Register: CLOCK_LFCLKSTAT */
+/* Description: Low frequency clock status. */
+
+/* Bit 16 : State for the LF clock. */
+#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
+#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
+#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK clock not running. */
+#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK clock running. */
+
+/* Bits 1..0 : Active clock source for the LF clock. */
+#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator running and generating the LFCLK clock. */
+#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< External 32KiHz crystal oscillator running and generating the LFCLK clock. */
+#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. */
+
+/* Register: CLOCK_LFCLKSRCCOPY */
+/* Description: Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
+
+/* Bits 1..0 : Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
+#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */
+#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */
+#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */
+
+/* Register: CLOCK_LFCLKSRC */
+/* Description: Clock source for the LFCLK clock. */
+
+/* Bits 1..0 : Clock source. */
+#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */
+#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */
+#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */
+
+/* Register: CLOCK_CTIV */
+/* Description: Calibration timer interval. */
+
+/* Bits 6..0 : Calibration timer interval in 0.25s resolution. */
+#define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */
+#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */
+
+/* Register: CLOCK_XTALFREQ */
+/* Description: Crystal frequency. */
+
+/* Bits 7..0 : External Xtal frequency selection. */
+#define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */
+#define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */
+#define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz xtal is used as source for the HFCLK oscillator. */
+#define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz xtal is used as source for the HFCLK oscillator. */
+
+
+/* Peripheral: ECB */
+/* Description: AES ECB Mode Encryption. */
+
+/* Register: ECB_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 1 : Enable interrupt on ERRORECB event. */
+#define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
+#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
+#define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */
+#define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */
+#define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 0 : Enable interrupt on ENDECB event. */
+#define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
+#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
+#define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */
+#define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */
+#define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: ECB_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 1 : Disable interrupt on ERRORECB event. */
+#define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
+#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
+#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */
+#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */
+#define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 0 : Disable interrupt on ENDECB event. */
+#define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
+#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
+#define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */
+#define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */
+#define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: ECB_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define ECB_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define ECB_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define ECB_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: FICR */
+/* Description: Factory Information Configuration. */
+
+/* Register: FICR_PPFC */
+/* Description: Pre-programmed factory code present. */
+
+/* Bits 7..0 : Pre-programmed factory code present. */
+#define FICR_PPFC_PPFC_Pos (0UL) /*!< Position of PPFC field. */
+#define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /*!< Bit mask of PPFC field. */
+#define FICR_PPFC_PPFC_Present (0x00UL) /*!< Present. */
+#define FICR_PPFC_PPFC_NotPresent (0xFFUL) /*!< Not present. */
+
+/* Register: FICR_CONFIGID */
+/* Description: Configuration identifier. */
+
+/* Bits 31..16 : Firmware Identification Number pre-loaded into the flash. */
+#define FICR_CONFIGID_FWID_Pos (16UL) /*!< Position of FWID field. */
+#define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /*!< Bit mask of FWID field. */
+
+/* Bits 15..0 : Hardware Identification Number. */
+#define FICR_CONFIGID_HWID_Pos (0UL) /*!< Position of HWID field. */
+#define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /*!< Bit mask of HWID field. */
+
+/* Register: FICR_DEVICEADDRTYPE */
+/* Description: Device address type. */
+
+/* Bit 0 : Device address type. */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address. */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address. */
+
+/* Register: FICR_OVERRIDEEN */
+/* Description: Radio calibration override enable. */
+
+/* Bit 3 : Override default values for BLE_1Mbit mode. */
+#define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL) /*!< Position of BLE_1MBIT field. */
+#define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos) /*!< Bit mask of BLE_1MBIT field. */
+#define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /*!< Override the default values for BLE_1Mbit mode. */
+#define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /*!< Do not override the default values for BLE_1Mbit mode. */
+
+/* Bit 0 : Override default values for NRF_1Mbit mode. */
+#define FICR_OVERRIDEEN_NRF_1MBIT_Pos (0UL) /*!< Position of NRF_1MBIT field. */
+#define FICR_OVERRIDEEN_NRF_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_NRF_1MBIT_Pos) /*!< Bit mask of NRF_1MBIT field. */
+#define FICR_OVERRIDEEN_NRF_1MBIT_Override (0UL) /*!< Override the default values for NRF_1Mbit mode. */
+#define FICR_OVERRIDEEN_NRF_1MBIT_NotOverride (1UL) /*!< Do not override the default values for NRF_1Mbit mode. */
+
+
+/* Peripheral: GPIO */
+/* Description: General purpose input and output. */
+
+/* Register: GPIO_OUT */
+/* Description: Write GPIO port. */
+
+/* Bit 31 : Pin 31. */
+#define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 30 : Pin 30. */
+#define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 29 : Pin 29. */
+#define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 28 : Pin 28. */
+#define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 27 : Pin 27. */
+#define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 26 : Pin 26. */
+#define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 25 : Pin 25. */
+#define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 24 : Pin 24. */
+#define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 23 : Pin 23. */
+#define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 22 : Pin 22. */
+#define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 21 : Pin 21. */
+#define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 20 : Pin 20. */
+#define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 19 : Pin 19. */
+#define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 18 : Pin 18. */
+#define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 17 : Pin 17. */
+#define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 16 : Pin 16. */
+#define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 15 : Pin 15. */
+#define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 14 : Pin 14. */
+#define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 13 : Pin 13. */
+#define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 12 : Pin 12. */
+#define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 11 : Pin 11. */
+#define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 10 : Pin 10. */
+#define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 9 : Pin 9. */
+#define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 8 : Pin 8. */
+#define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 7 : Pin 7. */
+#define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 6 : Pin 6. */
+#define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 5 : Pin 5. */
+#define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 4 : Pin 4. */
+#define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 3 : Pin 3. */
+#define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 2 : Pin 2. */
+#define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 1 : Pin 1. */
+#define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 0 : Pin 0. */
+#define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high. */
+
+/* Register: GPIO_OUTSET */
+/* Description: Set individual bits in GPIO port. */
+
+/* Bit 31 : Pin 31. */
+#define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_OUTSET_PIN31_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN31_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 30 : Pin 30. */
+#define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_OUTSET_PIN30_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN30_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 29 : Pin 29. */
+#define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_OUTSET_PIN29_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN29_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 28 : Pin 28. */
+#define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_OUTSET_PIN28_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN28_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 27 : Pin 27. */
+#define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_OUTSET_PIN27_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN27_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 26 : Pin 26. */
+#define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_OUTSET_PIN26_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN26_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 25 : Pin 25. */
+#define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_OUTSET_PIN25_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN25_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 24 : Pin 24. */
+#define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_OUTSET_PIN24_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN24_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 23 : Pin 23. */
+#define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_OUTSET_PIN23_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN23_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 22 : Pin 22. */
+#define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_OUTSET_PIN22_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN22_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 21 : Pin 21. */
+#define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_OUTSET_PIN21_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN21_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 20 : Pin 20. */
+#define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_OUTSET_PIN20_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN20_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 19 : Pin 19. */
+#define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_OUTSET_PIN19_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN19_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 18 : Pin 18. */
+#define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_OUTSET_PIN18_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN18_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 17 : Pin 17. */
+#define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_OUTSET_PIN17_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN17_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 16 : Pin 16. */
+#define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_OUTSET_PIN16_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN16_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 15 : Pin 15. */
+#define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_OUTSET_PIN15_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN15_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 14 : Pin 14. */
+#define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_OUTSET_PIN14_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN14_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 13 : Pin 13. */
+#define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_OUTSET_PIN13_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN13_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 12 : Pin 12. */
+#define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_OUTSET_PIN12_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN12_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 11 : Pin 11. */
+#define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_OUTSET_PIN11_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN11_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 10 : Pin 10. */
+#define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_OUTSET_PIN10_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN10_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 9 : Pin 9. */
+#define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_OUTSET_PIN9_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN9_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 8 : Pin 8. */
+#define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_OUTSET_PIN8_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN8_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 7 : Pin 7. */
+#define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_OUTSET_PIN7_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN7_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 6 : Pin 6. */
+#define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_OUTSET_PIN6_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN6_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 5 : Pin 5. */
+#define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_OUTSET_PIN5_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN5_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 4 : Pin 4. */
+#define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_OUTSET_PIN4_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN4_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 3 : Pin 3. */
+#define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_OUTSET_PIN3_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN3_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 2 : Pin 2. */
+#define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_OUTSET_PIN2_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN2_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 1 : Pin 1. */
+#define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_OUTSET_PIN1_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN1_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 0 : Pin 0. */
+#define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_OUTSET_PIN0_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN0_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Set pin driver high. */
+
+/* Register: GPIO_OUTCLR */
+/* Description: Clear individual bits in GPIO port. */
+
+/* Bit 31 : Pin 31. */
+#define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN31_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 30 : Pin 30. */
+#define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN30_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 29 : Pin 29. */
+#define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN29_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 28 : Pin 28. */
+#define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN28_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 27 : Pin 27. */
+#define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN27_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 26 : Pin 26. */
+#define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN26_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 25 : Pin 25. */
+#define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN25_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 24 : Pin 24. */
+#define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN24_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 23 : Pin 23. */
+#define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN23_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 22 : Pin 22. */
+#define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN22_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 21 : Pin 21. */
+#define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN21_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 20 : Pin 20. */
+#define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN20_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 19 : Pin 19. */
+#define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN19_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 18 : Pin 18. */
+#define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN18_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 17 : Pin 17. */
+#define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN17_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 16 : Pin 16. */
+#define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN16_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 15 : Pin 15. */
+#define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN15_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 14 : Pin 14. */
+#define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN14_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 13 : Pin 13. */
+#define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN13_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 12 : Pin 12. */
+#define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN12_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 11 : Pin 11. */
+#define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN11_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 10 : Pin 10. */
+#define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN10_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 9 : Pin 9. */
+#define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN9_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 8 : Pin 8. */
+#define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN8_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 7 : Pin 7. */
+#define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN7_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 6 : Pin 6. */
+#define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN6_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 5 : Pin 5. */
+#define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN5_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 4 : Pin 4. */
+#define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN4_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 3 : Pin 3. */
+#define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN3_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 2 : Pin 2. */
+#define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN2_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 1 : Pin 1. */
+#define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN1_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 0 : Pin 0. */
+#define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN0_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Set pin driver low. */
+
+/* Register: GPIO_IN */
+/* Description: Read GPIO port. */
+
+/* Bit 31 : Pin 31. */
+#define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high. */
+
+/* Bit 30 : Pin 30. */
+#define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high. */
+
+/* Bit 29 : Pin 29. */
+#define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high. */
+
+/* Bit 28 : Pin 28. */
+#define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high. */
+
+/* Bit 27 : Pin 27. */
+#define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high. */
+
+/* Bit 26 : Pin 26. */
+#define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high. */
+
+/* Bit 25 : Pin 25. */
+#define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high. */
+
+/* Bit 24 : Pin 24. */
+#define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high. */
+
+/* Bit 23 : Pin 23. */
+#define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high. */
+
+/* Bit 22 : Pin 22. */
+#define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high. */
+
+/* Bit 21 : Pin 21. */
+#define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high. */
+
+/* Bit 20 : Pin 20. */
+#define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high. */
+
+/* Bit 19 : Pin 19. */
+#define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high. */
+
+/* Bit 18 : Pin 18. */
+#define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high. */
+
+/* Bit 17 : Pin 17. */
+#define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high. */
+
+/* Bit 16 : Pin 16. */
+#define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high. */
+
+/* Bit 15 : Pin 15. */
+#define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high. */
+
+/* Bit 14 : Pin 14. */
+#define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high. */
+
+/* Bit 13 : Pin 13. */
+#define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high. */
+
+/* Bit 12 : Pin 12. */
+#define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high. */
+
+/* Bit 11 : Pin 11. */
+#define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high. */
+
+/* Bit 10 : Pin 10. */
+#define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high. */
+
+/* Bit 9 : Pin 9. */
+#define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high. */
+
+/* Bit 8 : Pin 8. */
+#define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high. */
+
+/* Bit 7 : Pin 7. */
+#define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high. */
+
+/* Bit 6 : Pin 6. */
+#define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high. */
+
+/* Bit 5 : Pin 5. */
+#define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high. */
+
+/* Bit 4 : Pin 4. */
+#define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high. */
+
+/* Bit 3 : Pin 3. */
+#define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high. */
+
+/* Bit 2 : Pin 2. */
+#define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high. */
+
+/* Bit 1 : Pin 1. */
+#define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high. */
+
+/* Bit 0 : Pin 0. */
+#define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high. */
+
+/* Register: GPIO_DIR */
+/* Description: Direction of GPIO pins. */
+
+/* Bit 31 : Pin 31. */
+#define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 30 : Pin 30. */
+#define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 29 : Pin 29. */
+#define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 28 : Pin 28. */
+#define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 27 : Pin 27. */
+#define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 26 : Pin 26. */
+#define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 25 : Pin 25. */
+#define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 24 : Pin 24. */
+#define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 23 : Pin 23. */
+#define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 22 : Pin 22. */
+#define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 21 : Pin 21. */
+#define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 20 : Pin 20. */
+#define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 19 : Pin 19. */
+#define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 18 : Pin 18. */
+#define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 17 : Pin 17. */
+#define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 16 : Pin 16. */
+#define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 15 : Pin 15. */
+#define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 14 : Pin 14. */
+#define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 13 : Pin 13. */
+#define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 12 : Pin 12. */
+#define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 11 : Pin 11. */
+#define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 10 : Pin 10. */
+#define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 9 : Pin 9. */
+#define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 8 : Pin 8. */
+#define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 7 : Pin 7. */
+#define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 6 : Pin 6. */
+#define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 5 : Pin 5. */
+#define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 4 : Pin 4. */
+#define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 3 : Pin 3. */
+#define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 2 : Pin 2. */
+#define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 1 : Pin 1. */
+#define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 0 : Pin 0. */
+#define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output. */
+
+/* Register: GPIO_DIRSET */
+/* Description: DIR set register. */
+
+/* Bit 31 : Set as output pin 31. */
+#define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_DIRSET_PIN31_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN31_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 30 : Set as output pin 30. */
+#define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_DIRSET_PIN30_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN30_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 29 : Set as output pin 29. */
+#define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_DIRSET_PIN29_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN29_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 28 : Set as output pin 28. */
+#define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_DIRSET_PIN28_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN28_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 27 : Set as output pin 27. */
+#define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_DIRSET_PIN27_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN27_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 26 : Set as output pin 26. */
+#define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_DIRSET_PIN26_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN26_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 25 : Set as output pin 25. */
+#define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_DIRSET_PIN25_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN25_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 24 : Set as output pin 24. */
+#define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_DIRSET_PIN24_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN24_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 23 : Set as output pin 23. */
+#define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_DIRSET_PIN23_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN23_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 22 : Set as output pin 22. */
+#define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_DIRSET_PIN22_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN22_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 21 : Set as output pin 21. */
+#define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_DIRSET_PIN21_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN21_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 20 : Set as output pin 20. */
+#define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_DIRSET_PIN20_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN20_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 19 : Set as output pin 19. */
+#define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_DIRSET_PIN19_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN19_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 18 : Set as output pin 18. */
+#define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_DIRSET_PIN18_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN18_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 17 : Set as output pin 17. */
+#define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_DIRSET_PIN17_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN17_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 16 : Set as output pin 16. */
+#define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_DIRSET_PIN16_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN16_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 15 : Set as output pin 15. */
+#define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_DIRSET_PIN15_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN15_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 14 : Set as output pin 14. */
+#define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_DIRSET_PIN14_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN14_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 13 : Set as output pin 13. */
+#define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_DIRSET_PIN13_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN13_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 12 : Set as output pin 12. */
+#define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_DIRSET_PIN12_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN12_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 11 : Set as output pin 11. */
+#define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_DIRSET_PIN11_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN11_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 10 : Set as output pin 10. */
+#define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_DIRSET_PIN10_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN10_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 9 : Set as output pin 9. */
+#define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_DIRSET_PIN9_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN9_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 8 : Set as output pin 8. */
+#define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_DIRSET_PIN8_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN8_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 7 : Set as output pin 7. */
+#define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_DIRSET_PIN7_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN7_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 6 : Set as output pin 6. */
+#define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_DIRSET_PIN6_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN6_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 5 : Set as output pin 5. */
+#define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_DIRSET_PIN5_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN5_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 4 : Set as output pin 4. */
+#define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_DIRSET_PIN4_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN4_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 3 : Set as output pin 3. */
+#define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_DIRSET_PIN3_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN3_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 2 : Set as output pin 2. */
+#define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_DIRSET_PIN2_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN2_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 1 : Set as output pin 1. */
+#define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_DIRSET_PIN1_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN1_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 0 : Set as output pin 0. */
+#define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_DIRSET_PIN0_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN0_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Set pin as output. */
+
+/* Register: GPIO_DIRCLR */
+/* Description: DIR clear register. */
+
+/* Bit 31 : Set as input pin 31. */
+#define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 30 : Set as input pin 30. */
+#define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 29 : Set as input pin 29. */
+#define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 28 : Set as input pin 28. */
+#define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 27 : Set as input pin 27. */
+#define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 26 : Set as input pin 26. */
+#define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 25 : Set as input pin 25. */
+#define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 24 : Set as input pin 24. */
+#define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 23 : Set as input pin 23. */
+#define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 22 : Set as input pin 22. */
+#define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 21 : Set as input pin 21. */
+#define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 20 : Set as input pin 20. */
+#define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 19 : Set as input pin 19. */
+#define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 18 : Set as input pin 18. */
+#define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 17 : Set as input pin 17. */
+#define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 16 : Set as input pin 16. */
+#define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 15 : Set as input pin 15. */
+#define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 14 : Set as input pin 14. */
+#define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 13 : Set as input pin 13. */
+#define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 12 : Set as input pin 12. */
+#define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 11 : Set as input pin 11. */
+#define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 10 : Set as input pin 10. */
+#define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 9 : Set as input pin 9. */
+#define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 8 : Set as input pin 8. */
+#define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 7 : Set as input pin 7. */
+#define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 6 : Set as input pin 6. */
+#define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 5 : Set as input pin 5. */
+#define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 4 : Set as input pin 4. */
+#define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 3 : Set as input pin 3. */
+#define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 2 : Set as input pin 2. */
+#define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 1 : Set as input pin 1. */
+#define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 0 : Set as input pin 0. */
+#define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Set pin as input. */
+
+/* Register: GPIO_PIN_CNF */
+/* Description: Configuration of GPIO pins. */
+
+/* Bits 17..16 : Pin sensing mechanism. */
+#define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
+#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
+#define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /*!< Disabled. */
+#define GPIO_PIN_CNF_SENSE_High (0x02UL) /*!< Wakeup on high level. */
+#define GPIO_PIN_CNF_SENSE_Low (0x03UL) /*!< Wakeup on low level. */
+
+/* Bits 10..8 : Drive configuration. */
+#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
+#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
+#define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL) /*!< Standard '0', Standard '1'. */
+#define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL) /*!< High '0', Standard '1'. */
+#define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL) /*!< Standard '0', High '1'. */
+#define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL) /*!< High '0', High '1'. */
+#define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL) /*!< Disconnected '0', Standard '1'. */
+#define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL) /*!< Disconnected '0', High '1'. */
+#define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL) /*!< Standard '0', Disconnected '1'. */
+#define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL) /*!< High '0', Disconnected '1'. */
+
+/* Bits 3..2 : Pull-up or -down configuration. */
+#define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
+#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
+#define GPIO_PIN_CNF_PULL_Disabled (0x00UL) /*!< No pull. */
+#define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /*!< Pulldown on pin. */
+#define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /*!< Pullup on pin. */
+
+/* Bit 1 : Connect or disconnect input path. */
+#define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
+#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
+#define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input pin. */
+#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input pin. */
+
+/* Bit 0 : Pin direction. */
+#define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
+#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
+#define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin. */
+#define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin. */
+
+
+/* Peripheral: GPIOTE */
+/* Description: GPIO tasks and events. */
+
+/* Register: GPIOTE_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 31 : Enable interrupt on PORT event. */
+#define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
+#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
+#define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Interrupt disabled. */
+#define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Interrupt enabled. */
+#define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 3 : Enable interrupt on IN[3] event. */
+#define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
+#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
+#define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Interrupt disabled. */
+#define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Interrupt enabled. */
+#define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 2 : Enable interrupt on IN[2] event. */
+#define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
+#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
+#define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Interrupt disabled. */
+#define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Interrupt enabled. */
+#define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on IN[1] event. */
+#define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
+#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
+#define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Interrupt disabled. */
+#define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Interrupt enabled. */
+#define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 0 : Enable interrupt on IN[0] event. */
+#define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
+#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
+#define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Interrupt disabled. */
+#define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Interrupt enabled. */
+#define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: GPIOTE_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 31 : Disable interrupt on PORT event. */
+#define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
+#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
+#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Interrupt disabled. */
+#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Interrupt enabled. */
+#define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 3 : Disable interrupt on IN[3] event. */
+#define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
+#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
+#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Interrupt disabled. */
+#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Interrupt enabled. */
+#define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 2 : Disable interrupt on IN[2] event. */
+#define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
+#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
+#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Interrupt disabled. */
+#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Interrupt enabled. */
+#define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on IN[1] event. */
+#define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
+#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
+#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Interrupt disabled. */
+#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Interrupt enabled. */
+#define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 0 : Disable interrupt on IN[0] event. */
+#define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
+#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
+#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Interrupt disabled. */
+#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Interrupt enabled. */
+#define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: GPIOTE_CONFIG */
+/* Description: Channel configuration registers. */
+
+/* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */
+#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
+#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
+#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Initial low output when in task mode. */
+#define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Initial high output when in task mode. */
+
+/* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */
+#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
+#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
+#define GPIOTE_CONFIG_POLARITY_None (0x00UL) /*!< No task or event. */
+#define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /*!< Low to high. */
+#define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /*!< High to low. */
+#define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /*!< Toggle. */
+
+/* Bits 12..8 : Pin select. */
+#define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
+#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
+
+/* Bits 1..0 : Mode */
+#define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
+#define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /*!< Disabled. */
+#define GPIOTE_CONFIG_MODE_Event (0x01UL) /*!< Channel configure in event mode. */
+#define GPIOTE_CONFIG_MODE_Task (0x03UL) /*!< Channel configure in task mode. */
+
+/* Register: GPIOTE_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define GPIOTE_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define GPIOTE_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define GPIOTE_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: LPCOMP */
+/* Description: Low power comparator. */
+
+/* Register: LPCOMP_SHORTS */
+/* Description: Shortcuts for the LPCOMP. */
+
+/* Bit 4 : Shortcut between CROSS event and STOP task. */
+#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
+#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
+#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 3 : Shortcut between UP event and STOP task. */
+#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
+#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
+#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 2 : Shortcut between DOWN event and STOP task. */
+#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
+#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
+#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 1 : Shortcut between RADY event and STOP task. */
+#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
+#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
+#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 0 : Shortcut between READY event and SAMPLE task. */
+#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
+#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
+#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Shortcut disabled. */
+#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Register: LPCOMP_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 3 : Enable interrupt on CROSS event. */
+#define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
+#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
+#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
+#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
+#define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 2 : Enable interrupt on UP event. */
+#define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
+#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
+#define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Interrupt disabled. */
+#define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Interrupt enabled. */
+#define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on DOWN event. */
+#define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
+#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
+#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
+#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
+#define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 0 : Enable interrupt on READY event. */
+#define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
+#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
+#define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
+#define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: LPCOMP_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 3 : Disable interrupt on CROSS event. */
+#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
+#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
+#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
+#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
+#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 2 : Disable interrupt on UP event. */
+#define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
+#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
+#define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Interrupt disabled. */
+#define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Interrupt enabled. */
+#define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on DOWN event. */
+#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
+#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
+#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
+#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
+#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 0 : Disable interrupt on READY event. */
+#define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
+#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
+#define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
+#define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: LPCOMP_RESULT */
+/* Description: Result of last compare. */
+
+/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
+#define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
+#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
+#define LPCOMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is bellow the reference threshold. */
+#define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold. */
+
+/* Register: LPCOMP_ENABLE */
+/* Description: Enable the LPCOMP. */
+
+/* Bits 1..0 : Enable or disable LPCOMP. */
+#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled LPCOMP. */
+#define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable LPCOMP. */
+
+/* Register: LPCOMP_PSEL */
+/* Description: Input pin select. */
+
+/* Bits 2..0 : Analog input pin select. */
+#define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
+#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
+#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< Use analog input 0 as analog input. */
+#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< Use analog input 1 as analog input. */
+#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< Use analog input 2 as analog input. */
+#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< Use analog input 3 as analog input. */
+#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< Use analog input 4 as analog input. */
+#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< Use analog input 5 as analog input. */
+#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< Use analog input 6 as analog input. */
+#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< Use analog input 7 as analog input. */
+
+/* Register: LPCOMP_REFSEL */
+/* Description: Reference select. */
+
+/* Bits 2..0 : Reference select. */
+#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
+#define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
+#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /*!< Use supply with a 1/8 prescaler as reference. */
+#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /*!< Use supply with a 2/8 prescaler as reference. */
+#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /*!< Use supply with a 3/8 prescaler as reference. */
+#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /*!< Use supply with a 4/8 prescaler as reference. */
+#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /*!< Use supply with a 5/8 prescaler as reference. */
+#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /*!< Use supply with a 6/8 prescaler as reference. */
+#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /*!< Use supply with a 7/8 prescaler as reference. */
+#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< Use external analog reference as reference. */
+
+/* Register: LPCOMP_EXTREFSEL */
+/* Description: External reference select. */
+
+/* Bit 0 : External analog reference pin selection. */
+#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
+#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
+#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use analog reference 0 as reference. */
+#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use analog reference 1 as reference. */
+
+/* Register: LPCOMP_ANADETECT */
+/* Description: Analog detect configuration. */
+
+/* Bits 1..0 : Analog detect configuration. */
+#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */
+#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */
+#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETEC on crossing, both upwards and downwards crossing. */
+#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETEC on upwards crossing only. */
+#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETEC on downwards crossing only. */
+
+/* Register: LPCOMP_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define LPCOMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define LPCOMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define LPCOMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: MPU */
+/* Description: Memory Protection Unit. */
+
+/* Register: MPU_PERR0 */
+/* Description: Configuration of peripherals in mpu regions. */
+
+/* Bit 31 : PPI region configuration. */
+#define MPU_PERR0_PPI_Pos (31UL) /*!< Position of PPI field. */
+#define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /*!< Bit mask of PPI field. */
+#define MPU_PERR0_PPI_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_PPI_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 30 : NVMC region configuration. */
+#define MPU_PERR0_NVMC_Pos (30UL) /*!< Position of NVMC field. */
+#define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos) /*!< Bit mask of NVMC field. */
+#define MPU_PERR0_NVMC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_NVMC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 19 : LPCOMP region configuration. */
+#define MPU_PERR0_LPCOMP_Pos (19UL) /*!< Position of LPCOMP field. */
+#define MPU_PERR0_LPCOMP_Msk (0x1UL << MPU_PERR0_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
+#define MPU_PERR0_LPCOMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_LPCOMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 18 : QDEC region configuration. */
+#define MPU_PERR0_QDEC_Pos (18UL) /*!< Position of QDEC field. */
+#define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos) /*!< Bit mask of QDEC field. */
+#define MPU_PERR0_QDEC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_QDEC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 17 : RTC1 region configuration. */
+#define MPU_PERR0_RTC1_Pos (17UL) /*!< Position of RTC1 field. */
+#define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos) /*!< Bit mask of RTC1 field. */
+#define MPU_PERR0_RTC1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_RTC1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 16 : WDT region configuration. */
+#define MPU_PERR0_WDT_Pos (16UL) /*!< Position of WDT field. */
+#define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos) /*!< Bit mask of WDT field. */
+#define MPU_PERR0_WDT_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_WDT_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 15 : CCM and AAR region configuration. */
+#define MPU_PERR0_CCM_AAR_Pos (15UL) /*!< Position of CCM_AAR field. */
+#define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos) /*!< Bit mask of CCM_AAR field. */
+#define MPU_PERR0_CCM_AAR_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_CCM_AAR_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 14 : ECB region configuration. */
+#define MPU_PERR0_ECB_Pos (14UL) /*!< Position of ECB field. */
+#define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos) /*!< Bit mask of ECB field. */
+#define MPU_PERR0_ECB_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_ECB_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 13 : RNG region configuration. */
+#define MPU_PERR0_RNG_Pos (13UL) /*!< Position of RNG field. */
+#define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos) /*!< Bit mask of RNG field. */
+#define MPU_PERR0_RNG_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_RNG_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 12 : TEMP region configuration. */
+#define MPU_PERR0_TEMP_Pos (12UL) /*!< Position of TEMP field. */
+#define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos) /*!< Bit mask of TEMP field. */
+#define MPU_PERR0_TEMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_TEMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 11 : RTC0 region configuration. */
+#define MPU_PERR0_RTC0_Pos (11UL) /*!< Position of RTC0 field. */
+#define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos) /*!< Bit mask of RTC0 field. */
+#define MPU_PERR0_RTC0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_RTC0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 10 : TIMER2 region configuration. */
+#define MPU_PERR0_TIMER2_Pos (10UL) /*!< Position of TIMER2 field. */
+#define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos) /*!< Bit mask of TIMER2 field. */
+#define MPU_PERR0_TIMER2_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_TIMER2_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 9 : TIMER1 region configuration. */
+#define MPU_PERR0_TIMER1_Pos (9UL) /*!< Position of TIMER1 field. */
+#define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos) /*!< Bit mask of TIMER1 field. */
+#define MPU_PERR0_TIMER1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_TIMER1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 8 : TIMER0 region configuration. */
+#define MPU_PERR0_TIMER0_Pos (8UL) /*!< Position of TIMER0 field. */
+#define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos) /*!< Bit mask of TIMER0 field. */
+#define MPU_PERR0_TIMER0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_TIMER0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 7 : ADC region configuration. */
+#define MPU_PERR0_ADC_Pos (7UL) /*!< Position of ADC field. */
+#define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos) /*!< Bit mask of ADC field. */
+#define MPU_PERR0_ADC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_ADC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 6 : GPIOTE region configuration. */
+#define MPU_PERR0_GPIOTE_Pos (6UL) /*!< Position of GPIOTE field. */
+#define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos) /*!< Bit mask of GPIOTE field. */
+#define MPU_PERR0_GPIOTE_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_GPIOTE_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 4 : SPI1 and TWI1 region configuration. */
+#define MPU_PERR0_SPI1_TWI1_Pos (4UL) /*!< Position of SPI1_TWI1 field. */
+#define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos) /*!< Bit mask of SPI1_TWI1 field. */
+#define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 3 : SPI0 and TWI0 region configuration. */
+#define MPU_PERR0_SPI0_TWI0_Pos (3UL) /*!< Position of SPI0_TWI0 field. */
+#define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos) /*!< Bit mask of SPI0_TWI0 field. */
+#define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 2 : UART0 region configuration. */
+#define MPU_PERR0_UART0_Pos (2UL) /*!< Position of UART0 field. */
+#define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos) /*!< Bit mask of UART0 field. */
+#define MPU_PERR0_UART0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_UART0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 1 : RADIO region configuration. */
+#define MPU_PERR0_RADIO_Pos (1UL) /*!< Position of RADIO field. */
+#define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos) /*!< Bit mask of RADIO field. */
+#define MPU_PERR0_RADIO_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_RADIO_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 0 : POWER_CLOCK region configuration. */
+#define MPU_PERR0_POWER_CLOCK_Pos (0UL) /*!< Position of POWER_CLOCK field. */
+#define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos) /*!< Bit mask of POWER_CLOCK field. */
+#define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Register: MPU_PROTENSET0 */
+/* Description: Erase and write protection bit enable set register. */
+
+/* Bit 31 : Protection enable for region 31. */
+#define MPU_PROTENSET0_PROTREG31_Pos (31UL) /*!< Position of PROTREG31 field. */
+#define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos) /*!< Bit mask of PROTREG31 field. */
+#define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG31_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 30 : Protection enable for region 30. */
+#define MPU_PROTENSET0_PROTREG30_Pos (30UL) /*!< Position of PROTREG30 field. */
+#define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos) /*!< Bit mask of PROTREG30 field. */
+#define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG30_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 29 : Protection enable for region 29. */
+#define MPU_PROTENSET0_PROTREG29_Pos (29UL) /*!< Position of PROTREG29 field. */
+#define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos) /*!< Bit mask of PROTREG29 field. */
+#define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG29_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 28 : Protection enable for region 28. */
+#define MPU_PROTENSET0_PROTREG28_Pos (28UL) /*!< Position of PROTREG28 field. */
+#define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos) /*!< Bit mask of PROTREG28 field. */
+#define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG28_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 27 : Protection enable for region 27. */
+#define MPU_PROTENSET0_PROTREG27_Pos (27UL) /*!< Position of PROTREG27 field. */
+#define MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos) /*!< Bit mask of PROTREG27 field. */
+#define MPU_PROTENSET0_PROTREG27_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG27_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG27_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 26 : Protection enable for region 26. */
+#define MPU_PROTENSET0_PROTREG26_Pos (26UL) /*!< Position of PROTREG26 field. */
+#define MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos) /*!< Bit mask of PROTREG26 field. */
+#define MPU_PROTENSET0_PROTREG26_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG26_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG26_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 25 : Protection enable for region 25. */
+#define MPU_PROTENSET0_PROTREG25_Pos (25UL) /*!< Position of PROTREG25 field. */
+#define MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos) /*!< Bit mask of PROTREG25 field. */
+#define MPU_PROTENSET0_PROTREG25_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG25_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG25_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 24 : Protection enable for region 24. */
+#define MPU_PROTENSET0_PROTREG24_Pos (24UL) /*!< Position of PROTREG24 field. */
+#define MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos) /*!< Bit mask of PROTREG24 field. */
+#define MPU_PROTENSET0_PROTREG24_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG24_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG24_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 23 : Protection enable for region 23. */
+#define MPU_PROTENSET0_PROTREG23_Pos (23UL) /*!< Position of PROTREG23 field. */
+#define MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos) /*!< Bit mask of PROTREG23 field. */
+#define MPU_PROTENSET0_PROTREG23_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG23_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG23_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 22 : Protection enable for region 22. */
+#define MPU_PROTENSET0_PROTREG22_Pos (22UL) /*!< Position of PROTREG22 field. */
+#define MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos) /*!< Bit mask of PROTREG22 field. */
+#define MPU_PROTENSET0_PROTREG22_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG22_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG22_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 21 : Protection enable for region 21. */
+#define MPU_PROTENSET0_PROTREG21_Pos (21UL) /*!< Position of PROTREG21 field. */
+#define MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos) /*!< Bit mask of PROTREG21 field. */
+#define MPU_PROTENSET0_PROTREG21_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG21_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG21_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 20 : Protection enable for region 20. */
+#define MPU_PROTENSET0_PROTREG20_Pos (20UL) /*!< Position of PROTREG20 field. */
+#define MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos) /*!< Bit mask of PROTREG20 field. */
+#define MPU_PROTENSET0_PROTREG20_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG20_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG20_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 19 : Protection enable for region 19. */
+#define MPU_PROTENSET0_PROTREG19_Pos (19UL) /*!< Position of PROTREG19 field. */
+#define MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos) /*!< Bit mask of PROTREG19 field. */
+#define MPU_PROTENSET0_PROTREG19_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG19_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG19_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 18 : Protection enable for region 18. */
+#define MPU_PROTENSET0_PROTREG18_Pos (18UL) /*!< Position of PROTREG18 field. */
+#define MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos) /*!< Bit mask of PROTREG18 field. */
+#define MPU_PROTENSET0_PROTREG18_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG18_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG18_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 17 : Protection enable for region 17. */
+#define MPU_PROTENSET0_PROTREG17_Pos (17UL) /*!< Position of PROTREG17 field. */
+#define MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos) /*!< Bit mask of PROTREG17 field. */
+#define MPU_PROTENSET0_PROTREG17_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG17_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG17_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 16 : Protection enable for region 16. */
+#define MPU_PROTENSET0_PROTREG16_Pos (16UL) /*!< Position of PROTREG16 field. */
+#define MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos) /*!< Bit mask of PROTREG16 field. */
+#define MPU_PROTENSET0_PROTREG16_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG16_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG16_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 15 : Protection enable for region 15. */
+#define MPU_PROTENSET0_PROTREG15_Pos (15UL) /*!< Position of PROTREG15 field. */
+#define MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos) /*!< Bit mask of PROTREG15 field. */
+#define MPU_PROTENSET0_PROTREG15_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG15_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG15_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 14 : Protection enable for region 14. */
+#define MPU_PROTENSET0_PROTREG14_Pos (14UL) /*!< Position of PROTREG14 field. */
+#define MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos) /*!< Bit mask of PROTREG14 field. */
+#define MPU_PROTENSET0_PROTREG14_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG14_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG14_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 13 : Protection enable for region 13. */
+#define MPU_PROTENSET0_PROTREG13_Pos (13UL) /*!< Position of PROTREG13 field. */
+#define MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos) /*!< Bit mask of PROTREG13 field. */
+#define MPU_PROTENSET0_PROTREG13_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG13_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG13_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 12 : Protection enable for region 12. */
+#define MPU_PROTENSET0_PROTREG12_Pos (12UL) /*!< Position of PROTREG12 field. */
+#define MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos) /*!< Bit mask of PROTREG12 field. */
+#define MPU_PROTENSET0_PROTREG12_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG12_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG12_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 11 : Protection enable for region 11. */
+#define MPU_PROTENSET0_PROTREG11_Pos (11UL) /*!< Position of PROTREG11 field. */
+#define MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos) /*!< Bit mask of PROTREG11 field. */
+#define MPU_PROTENSET0_PROTREG11_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG11_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG11_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 10 : Protection enable for region 10. */
+#define MPU_PROTENSET0_PROTREG10_Pos (10UL) /*!< Position of PROTREG10 field. */
+#define MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos) /*!< Bit mask of PROTREG10 field. */
+#define MPU_PROTENSET0_PROTREG10_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG10_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG10_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 9 : Protection enable for region 9. */
+#define MPU_PROTENSET0_PROTREG9_Pos (9UL) /*!< Position of PROTREG9 field. */
+#define MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos) /*!< Bit mask of PROTREG9 field. */
+#define MPU_PROTENSET0_PROTREG9_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG9_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG9_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 8 : Protection enable for region 8. */
+#define MPU_PROTENSET0_PROTREG8_Pos (8UL) /*!< Position of PROTREG8 field. */
+#define MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos) /*!< Bit mask of PROTREG8 field. */
+#define MPU_PROTENSET0_PROTREG8_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG8_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG8_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 7 : Protection enable for region 7. */
+#define MPU_PROTENSET0_PROTREG7_Pos (7UL) /*!< Position of PROTREG7 field. */
+#define MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos) /*!< Bit mask of PROTREG7 field. */
+#define MPU_PROTENSET0_PROTREG7_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG7_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG7_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 6 : Protection enable for region 6. */
+#define MPU_PROTENSET0_PROTREG6_Pos (6UL) /*!< Position of PROTREG6 field. */
+#define MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos) /*!< Bit mask of PROTREG6 field. */
+#define MPU_PROTENSET0_PROTREG6_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG6_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG6_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 5 : Protection enable for region 5. */
+#define MPU_PROTENSET0_PROTREG5_Pos (5UL) /*!< Position of PROTREG5 field. */
+#define MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos) /*!< Bit mask of PROTREG5 field. */
+#define MPU_PROTENSET0_PROTREG5_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG5_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG5_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 4 : Protection enable for region 4. */
+#define MPU_PROTENSET0_PROTREG4_Pos (4UL) /*!< Position of PROTREG4 field. */
+#define MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos) /*!< Bit mask of PROTREG4 field. */
+#define MPU_PROTENSET0_PROTREG4_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG4_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG4_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 3 : Protection enable for region 3. */
+#define MPU_PROTENSET0_PROTREG3_Pos (3UL) /*!< Position of PROTREG3 field. */
+#define MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos) /*!< Bit mask of PROTREG3 field. */
+#define MPU_PROTENSET0_PROTREG3_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG3_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG3_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 2 : Protection enable for region 2. */
+#define MPU_PROTENSET0_PROTREG2_Pos (2UL) /*!< Position of PROTREG2 field. */
+#define MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos) /*!< Bit mask of PROTREG2 field. */
+#define MPU_PROTENSET0_PROTREG2_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG2_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG2_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 1 : Protection enable for region 1. */
+#define MPU_PROTENSET0_PROTREG1_Pos (1UL) /*!< Position of PROTREG1 field. */
+#define MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos) /*!< Bit mask of PROTREG1 field. */
+#define MPU_PROTENSET0_PROTREG1_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG1_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG1_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 0 : Protection enable for region 0. */
+#define MPU_PROTENSET0_PROTREG0_Pos (0UL) /*!< Position of PROTREG0 field. */
+#define MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos) /*!< Bit mask of PROTREG0 field. */
+#define MPU_PROTENSET0_PROTREG0_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG0_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG0_Set (1UL) /*!< Enable protection on write. */
+
+/* Register: MPU_PROTENSET1 */
+/* Description: Erase and write protection bit enable set register. */
+
+/* Bit 31 : Protection enable for region 63. */
+#define MPU_PROTENSET1_PROTREG63_Pos (31UL) /*!< Position of PROTREG63 field. */
+#define MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos) /*!< Bit mask of PROTREG63 field. */
+#define MPU_PROTENSET1_PROTREG63_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG63_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG63_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 30 : Protection enable for region 62. */
+#define MPU_PROTENSET1_PROTREG62_Pos (30UL) /*!< Position of PROTREG62 field. */
+#define MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos) /*!< Bit mask of PROTREG62 field. */
+#define MPU_PROTENSET1_PROTREG62_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG62_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG62_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 29 : Protection enable for region 61. */
+#define MPU_PROTENSET1_PROTREG61_Pos (29UL) /*!< Position of PROTREG61 field. */
+#define MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos) /*!< Bit mask of PROTREG61 field. */
+#define MPU_PROTENSET1_PROTREG61_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG61_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG61_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 28 : Protection enable for region 60. */
+#define MPU_PROTENSET1_PROTREG60_Pos (28UL) /*!< Position of PROTREG60 field. */
+#define MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos) /*!< Bit mask of PROTREG60 field. */
+#define MPU_PROTENSET1_PROTREG60_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG60_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG60_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 27 : Protection enable for region 59. */
+#define MPU_PROTENSET1_PROTREG59_Pos (27UL) /*!< Position of PROTREG59 field. */
+#define MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos) /*!< Bit mask of PROTREG59 field. */
+#define MPU_PROTENSET1_PROTREG59_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG59_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG59_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 26 : Protection enable for region 58. */
+#define MPU_PROTENSET1_PROTREG58_Pos (26UL) /*!< Position of PROTREG58 field. */
+#define MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos) /*!< Bit mask of PROTREG58 field. */
+#define MPU_PROTENSET1_PROTREG58_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG58_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG58_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 25 : Protection enable for region 57. */
+#define MPU_PROTENSET1_PROTREG57_Pos (25UL) /*!< Position of PROTREG57 field. */
+#define MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos) /*!< Bit mask of PROTREG57 field. */
+#define MPU_PROTENSET1_PROTREG57_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG57_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG57_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 24 : Protection enable for region 56. */
+#define MPU_PROTENSET1_PROTREG56_Pos (24UL) /*!< Position of PROTREG56 field. */
+#define MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos) /*!< Bit mask of PROTREG56 field. */
+#define MPU_PROTENSET1_PROTREG56_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG56_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG56_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 23 : Protection enable for region 55. */
+#define MPU_PROTENSET1_PROTREG55_Pos (23UL) /*!< Position of PROTREG55 field. */
+#define MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos) /*!< Bit mask of PROTREG55 field. */
+#define MPU_PROTENSET1_PROTREG55_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG55_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG55_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 22 : Protection enable for region 54. */
+#define MPU_PROTENSET1_PROTREG54_Pos (22UL) /*!< Position of PROTREG54 field. */
+#define MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos) /*!< Bit mask of PROTREG54 field. */
+#define MPU_PROTENSET1_PROTREG54_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG54_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG54_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 21 : Protection enable for region 53. */
+#define MPU_PROTENSET1_PROTREG53_Pos (21UL) /*!< Position of PROTREG53 field. */
+#define MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos) /*!< Bit mask of PROTREG53 field. */
+#define MPU_PROTENSET1_PROTREG53_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG53_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG53_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 20 : Protection enable for region 52. */
+#define MPU_PROTENSET1_PROTREG52_Pos (20UL) /*!< Position of PROTREG52 field. */
+#define MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos) /*!< Bit mask of PROTREG52 field. */
+#define MPU_PROTENSET1_PROTREG52_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG52_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG52_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 19 : Protection enable for region 51. */
+#define MPU_PROTENSET1_PROTREG51_Pos (19UL) /*!< Position of PROTREG51 field. */
+#define MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos) /*!< Bit mask of PROTREG51 field. */
+#define MPU_PROTENSET1_PROTREG51_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG51_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG51_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 18 : Protection enable for region 50. */
+#define MPU_PROTENSET1_PROTREG50_Pos (18UL) /*!< Position of PROTREG50 field. */
+#define MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos) /*!< Bit mask of PROTREG50 field. */
+#define MPU_PROTENSET1_PROTREG50_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG50_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG50_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 17 : Protection enable for region 49. */
+#define MPU_PROTENSET1_PROTREG49_Pos (17UL) /*!< Position of PROTREG49 field. */
+#define MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos) /*!< Bit mask of PROTREG49 field. */
+#define MPU_PROTENSET1_PROTREG49_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG49_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG49_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 16 : Protection enable for region 48. */
+#define MPU_PROTENSET1_PROTREG48_Pos (16UL) /*!< Position of PROTREG48 field. */
+#define MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos) /*!< Bit mask of PROTREG48 field. */
+#define MPU_PROTENSET1_PROTREG48_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG48_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG48_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 15 : Protection enable for region 47. */
+#define MPU_PROTENSET1_PROTREG47_Pos (15UL) /*!< Position of PROTREG47 field. */
+#define MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos) /*!< Bit mask of PROTREG47 field. */
+#define MPU_PROTENSET1_PROTREG47_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG47_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG47_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 14 : Protection enable for region 46. */
+#define MPU_PROTENSET1_PROTREG46_Pos (14UL) /*!< Position of PROTREG46 field. */
+#define MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos) /*!< Bit mask of PROTREG46 field. */
+#define MPU_PROTENSET1_PROTREG46_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG46_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG46_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 13 : Protection enable for region 45. */
+#define MPU_PROTENSET1_PROTREG45_Pos (13UL) /*!< Position of PROTREG45 field. */
+#define MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos) /*!< Bit mask of PROTREG45 field. */
+#define MPU_PROTENSET1_PROTREG45_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG45_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG45_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 12 : Protection enable for region 44. */
+#define MPU_PROTENSET1_PROTREG44_Pos (12UL) /*!< Position of PROTREG44 field. */
+#define MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos) /*!< Bit mask of PROTREG44 field. */
+#define MPU_PROTENSET1_PROTREG44_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG44_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG44_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 11 : Protection enable for region 43. */
+#define MPU_PROTENSET1_PROTREG43_Pos (11UL) /*!< Position of PROTREG43 field. */
+#define MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos) /*!< Bit mask of PROTREG43 field. */
+#define MPU_PROTENSET1_PROTREG43_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG43_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG43_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 10 : Protection enable for region 42. */
+#define MPU_PROTENSET1_PROTREG42_Pos (10UL) /*!< Position of PROTREG42 field. */
+#define MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos) /*!< Bit mask of PROTREG42 field. */
+#define MPU_PROTENSET1_PROTREG42_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG42_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG42_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 9 : Protection enable for region 41. */
+#define MPU_PROTENSET1_PROTREG41_Pos (9UL) /*!< Position of PROTREG41 field. */
+#define MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos) /*!< Bit mask of PROTREG41 field. */
+#define MPU_PROTENSET1_PROTREG41_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG41_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG41_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 8 : Protection enable for region 40. */
+#define MPU_PROTENSET1_PROTREG40_Pos (8UL) /*!< Position of PROTREG40 field. */
+#define MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos) /*!< Bit mask of PROTREG40 field. */
+#define MPU_PROTENSET1_PROTREG40_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG40_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG40_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 7 : Protection enable for region 39. */
+#define MPU_PROTENSET1_PROTREG39_Pos (7UL) /*!< Position of PROTREG39 field. */
+#define MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos) /*!< Bit mask of PROTREG39 field. */
+#define MPU_PROTENSET1_PROTREG39_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG39_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG39_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 6 : Protection enable for region 38. */
+#define MPU_PROTENSET1_PROTREG38_Pos (6UL) /*!< Position of PROTREG38 field. */
+#define MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos) /*!< Bit mask of PROTREG38 field. */
+#define MPU_PROTENSET1_PROTREG38_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG38_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG38_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 5 : Protection enable for region 37. */
+#define MPU_PROTENSET1_PROTREG37_Pos (5UL) /*!< Position of PROTREG37 field. */
+#define MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos) /*!< Bit mask of PROTREG37 field. */
+#define MPU_PROTENSET1_PROTREG37_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG37_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG37_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 4 : Protection enable for region 36. */
+#define MPU_PROTENSET1_PROTREG36_Pos (4UL) /*!< Position of PROTREG36 field. */
+#define MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos) /*!< Bit mask of PROTREG36 field. */
+#define MPU_PROTENSET1_PROTREG36_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG36_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG36_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 3 : Protection enable for region 35. */
+#define MPU_PROTENSET1_PROTREG35_Pos (3UL) /*!< Position of PROTREG35 field. */
+#define MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos) /*!< Bit mask of PROTREG35 field. */
+#define MPU_PROTENSET1_PROTREG35_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG35_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG35_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 2 : Protection enable for region 34. */
+#define MPU_PROTENSET1_PROTREG34_Pos (2UL) /*!< Position of PROTREG34 field. */
+#define MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos) /*!< Bit mask of PROTREG34 field. */
+#define MPU_PROTENSET1_PROTREG34_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG34_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG34_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 1 : Protection enable for region 33. */
+#define MPU_PROTENSET1_PROTREG33_Pos (1UL) /*!< Position of PROTREG33 field. */
+#define MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos) /*!< Bit mask of PROTREG33 field. */
+#define MPU_PROTENSET1_PROTREG33_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG33_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG33_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 0 : Protection enable for region 32. */
+#define MPU_PROTENSET1_PROTREG32_Pos (0UL) /*!< Position of PROTREG32 field. */
+#define MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos) /*!< Bit mask of PROTREG32 field. */
+#define MPU_PROTENSET1_PROTREG32_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG32_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG32_Set (1UL) /*!< Enable protection on write. */
+
+/* Register: MPU_DISABLEINDEBUG */
+/* Description: Disable erase and write protection mechanism in debug mode. */
+
+/* Bit 0 : Disable protection mechanism in debug mode. */
+#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */
+#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */
+#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Protection enabled. */
+#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Protection disabled. */
+
+/* Register: MPU_PROTBLOCKSIZE */
+/* Description: Erase and write protection block size. */
+
+/* Bits 1..0 : Erase and write protection block size. */
+#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos (0UL) /*!< Position of PROTBLOCKSIZE field. */
+#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Msk (0x3UL << MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos) /*!< Bit mask of PROTBLOCKSIZE field. */
+#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_4k (0UL) /*!< Erase and write protection block size is 4k. */
+
+
+/* Peripheral: NVMC */
+/* Description: Non Volatile Memory Controller. */
+
+/* Register: NVMC_READY */
+/* Description: Ready flag. */
+
+/* Bit 0 : NVMC ready. */
+#define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
+#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
+#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation). */
+#define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready. */
+
+/* Register: NVMC_CONFIG */
+/* Description: Configuration register. */
+
+/* Bits 1..0 : Program write enable. */
+#define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
+#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
+#define NVMC_CONFIG_WEN_Ren (0x00UL) /*!< Read only access. */
+#define NVMC_CONFIG_WEN_Wen (0x01UL) /*!< Write enabled. */
+#define NVMC_CONFIG_WEN_Een (0x02UL) /*!< Erase enabled. */
+
+/* Register: NVMC_ERASEALL */
+/* Description: Register for erasing all non-volatile user memory. */
+
+/* Bit 0 : Starts the erasing of all user NVM (code region 0/1 and UICR registers). */
+#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
+#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
+#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation. */
+#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase. */
+
+/* Register: NVMC_ERASEUICR */
+/* Description: Register for start erasing User Information Congfiguration Registers. */
+
+/* Bit 0 : It can only be used when all contents of code region 1 are erased. */
+#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */
+#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */
+#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation. */
+#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start UICR erase. */
+
+
+/* Peripheral: POWER */
+/* Description: Power Control. */
+
+/* Register: POWER_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 2 : Enable interrupt on POFWARN event. */
+#define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
+#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
+#define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */
+#define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */
+#define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: POWER_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 2 : Disable interrupt on POFWARN event. */
+#define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
+#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
+#define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */
+#define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */
+#define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: POWER_RESETREAS */
+/* Description: Reset reason. */
+
+/* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */
+#define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */
+#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
+#define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Reset not detected. */
+#define POWER_RESETREAS_DIF_Detected (1UL) /*!< Reset detected. */
+
+/* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */
+#define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */
+#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
+#define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Reset not detected. */
+#define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Reset detected. */
+
+/* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */
+#define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */
+#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
+#define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Reset not detected. */
+#define POWER_RESETREAS_OFF_Detected (1UL) /*!< Reset detected. */
+
+/* Bit 3 : Reset from CPU lock-up detected. */
+#define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */
+#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
+#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Reset not detected. */
+#define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Reset detected. */
+
+/* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */
+#define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
+#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
+#define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Reset not detected. */
+#define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Reset detected. */
+
+/* Bit 1 : Reset from watchdog detected. */
+#define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
+#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
+#define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Reset not detected. */
+#define POWER_RESETREAS_DOG_Detected (1UL) /*!< Reset detected. */
+
+/* Bit 0 : Reset from pin-reset detected. */
+#define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
+#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
+#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Reset not detected. */
+#define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Reset detected. */
+
+/* Register: POWER_RAMSTATUS */
+/* Description: Ram status register. */
+
+/* Bit 3 : RAM block 3 status. */
+#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */
+#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */
+#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< RAM block 3 is off or powering up. */
+#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< RAM block 3 is on. */
+
+/* Bit 2 : RAM block 2 status. */
+#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */
+#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */
+#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< RAM block 2 is off or powering up. */
+#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< RAM block 2 is on. */
+
+/* Bit 1 : RAM block 1 status. */
+#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */
+#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */
+#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< RAM block 1 is off or powering up. */
+#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< RAM block 1 is on. */
+
+/* Bit 0 : RAM block 0 status. */
+#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */
+#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */
+#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< RAM block 0 is off or powering up. */
+#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< RAM block 0 is on. */
+
+/* Register: POWER_SYSTEMOFF */
+/* Description: System off register. */
+
+/* Bit 0 : Enter system off mode. */
+#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
+#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
+#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enter system off mode. */
+
+/* Register: POWER_POFCON */
+/* Description: Power failure configuration. */
+
+/* Bits 2..1 : Set threshold level. */
+#define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
+#define POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
+#define POWER_POFCON_THRESHOLD_V21 (0x00UL) /*!< Set threshold to 2.1Volts. */
+#define POWER_POFCON_THRESHOLD_V23 (0x01UL) /*!< Set threshold to 2.3Volts. */
+#define POWER_POFCON_THRESHOLD_V25 (0x02UL) /*!< Set threshold to 2.5Volts. */
+#define POWER_POFCON_THRESHOLD_V27 (0x03UL) /*!< Set threshold to 2.7Volts. */
+
+/* Bit 0 : Power failure comparator enable. */
+#define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
+#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */
+#define POWER_POFCON_POF_Disabled (0UL) /*!< Disabled. */
+#define POWER_POFCON_POF_Enabled (1UL) /*!< Enabled. */
+
+/* Register: POWER_GPREGRET */
+/* Description: General purpose retention register. This register is a retained register. */
+
+/* Bits 7..0 : General purpose retention register. */
+#define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
+#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
+
+/* Register: POWER_RAMON */
+/* Description: Ram on/off. */
+
+/* Bit 17 : RAM block 1 behaviour in OFF mode. */
+#define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */
+#define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */
+#define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in OFF mode. */
+#define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< RAM block 1 ON in OFF mode. */
+
+/* Bit 16 : RAM block 0 behaviour in OFF mode. */
+#define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */
+#define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */
+#define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in OFF mode. */
+#define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< RAM block 0 ON in OFF mode. */
+
+/* Bit 1 : RAM block 1 behaviour in ON mode. */
+#define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */
+#define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */
+#define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in ON mode. */
+#define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< RAM block 1 ON in ON mode. */
+
+/* Bit 0 : RAM block 0 behaviour in ON mode. */
+#define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */
+#define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */
+#define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in ON mode. */
+#define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< RAM block 0 ON in ON mode. */
+
+/* Register: POWER_RESET */
+/* Description: Pin reset functionality configuration register. This register is a retained register. */
+
+/* Bit 0 : Enable or disable pin reset in debug interface mode. */
+#define POWER_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
+#define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
+#define POWER_RESET_RESET_Disabled (0UL) /*!< Pin reset in debug interface mode disabled. */
+#define POWER_RESET_RESET_Enabled (1UL) /*!< Pin reset in debug interface mode enabled. */
+
+/* Register: POWER_RAMONB */
+/* Description: Ram on/off. */
+
+/* Bit 17 : RAM block 3 behaviour in OFF mode. */
+#define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */
+#define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */
+#define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< RAM block 3 OFF in OFF mode. */
+#define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< RAM block 3 ON in OFF mode. */
+
+/* Bit 16 : RAM block 2 behaviour in OFF mode. */
+#define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */
+#define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */
+#define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in OFF mode. */
+#define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< RAM block 2 ON in OFF mode. */
+
+/* Bit 1 : RAM block 3 behaviour in ON mode. */
+#define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */
+#define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */
+#define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< RAM block 33 OFF in ON mode. */
+#define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< RAM block 3 ON in ON mode. */
+
+/* Bit 0 : RAM block 2 behaviour in ON mode. */
+#define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */
+#define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */
+#define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in ON mode. */
+#define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< RAM block 2 ON in ON mode. */
+
+/* Register: POWER_DCDCEN */
+/* Description: DCDC converter enable configuration register. */
+
+/* Bit 0 : Enable DCDC converter. */
+#define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
+#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
+#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< DCDC converter disabled. */
+#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< DCDC converter enabled. */
+
+/* Register: POWER_DCDCFORCE */
+/* Description: DCDC power-up force register. */
+
+/* Bit 1 : DCDC power-up force on. */
+#define POWER_DCDCFORCE_FORCEON_Pos (1UL) /*!< Position of FORCEON field. */
+#define POWER_DCDCFORCE_FORCEON_Msk (0x1UL << POWER_DCDCFORCE_FORCEON_Pos) /*!< Bit mask of FORCEON field. */
+#define POWER_DCDCFORCE_FORCEON_NoForce (0UL) /*!< No force. */
+#define POWER_DCDCFORCE_FORCEON_Force (1UL) /*!< Force. */
+
+/* Bit 0 : DCDC power-up force off. */
+#define POWER_DCDCFORCE_FORCEOFF_Pos (0UL) /*!< Position of FORCEOFF field. */
+#define POWER_DCDCFORCE_FORCEOFF_Msk (0x1UL << POWER_DCDCFORCE_FORCEOFF_Pos) /*!< Bit mask of FORCEOFF field. */
+#define POWER_DCDCFORCE_FORCEOFF_NoForce (0UL) /*!< No force. */
+#define POWER_DCDCFORCE_FORCEOFF_Force (1UL) /*!< Force. */
+
+
+/* Peripheral: PPI */
+/* Description: PPI controller. */
+
+/* Register: PPI_CHEN */
+/* Description: Channel enable. */
+
+/* Bit 31 : Enable PPI channel 31. */
+#define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHEN_CH31_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH31_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 30 : Enable PPI channel 30. */
+#define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHEN_CH30_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH30_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 29 : Enable PPI channel 29. */
+#define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHEN_CH29_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH29_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 28 : Enable PPI channel 28. */
+#define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHEN_CH28_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH28_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 27 : Enable PPI channel 27. */
+#define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHEN_CH27_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH27_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 26 : Enable PPI channel 26. */
+#define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHEN_CH26_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH26_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 25 : Enable PPI channel 25. */
+#define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHEN_CH25_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH25_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 24 : Enable PPI channel 24. */
+#define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHEN_CH24_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH24_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 23 : Enable PPI channel 23. */
+#define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHEN_CH23_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH23_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 22 : Enable PPI channel 22. */
+#define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHEN_CH22_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH22_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 21 : Enable PPI channel 21. */
+#define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHEN_CH21_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH21_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 20 : Enable PPI channel 20. */
+#define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHEN_CH20_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH20_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 15 : Enable PPI channel 15. */
+#define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHEN_CH15_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH15_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 14 : Enable PPI channel 14. */
+#define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHEN_CH14_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH14_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 13 : Enable PPI channel 13. */
+#define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHEN_CH13_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH13_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 12 : Enable PPI channel 12. */
+#define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHEN_CH12_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH12_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 11 : Enable PPI channel 11. */
+#define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHEN_CH11_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH11_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 10 : Enable PPI channel 10. */
+#define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHEN_CH10_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH10_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 9 : Enable PPI channel 9. */
+#define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHEN_CH9_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH9_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 8 : Enable PPI channel 8. */
+#define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHEN_CH8_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH8_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 7 : Enable PPI channel 7. */
+#define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHEN_CH7_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH7_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 6 : Enable PPI channel 6. */
+#define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHEN_CH6_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH6_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 5 : Enable PPI channel 5. */
+#define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHEN_CH5_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH5_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 4 : Enable PPI channel 4. */
+#define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHEN_CH4_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH4_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 3 : Enable PPI channel 3. */
+#define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHEN_CH3_Disabled (0UL) /*!< Channel disabled */
+#define PPI_CHEN_CH3_Enabled (1UL) /*!< Channel enabled */
+
+/* Bit 2 : Enable PPI channel 2. */
+#define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHEN_CH2_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH2_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 1 : Enable PPI channel 1. */
+#define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHEN_CH1_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH1_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 0 : Enable PPI channel 0. */
+#define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHEN_CH0_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH0_Enabled (1UL) /*!< Channel enabled. */
+
+/* Register: PPI_CHENSET */
+/* Description: Channel enable set. */
+
+/* Bit 31 : Enable PPI channel 31. */
+#define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHENSET_CH31_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH31_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH31_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 30 : Enable PPI channel 30. */
+#define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHENSET_CH30_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH30_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH30_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 29 : Enable PPI channel 29. */
+#define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHENSET_CH29_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH29_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH29_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 28 : Enable PPI channel 28. */
+#define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHENSET_CH28_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH28_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH28_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 27 : Enable PPI channel 27. */
+#define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHENSET_CH27_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH27_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH27_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 26 : Enable PPI channel 26. */
+#define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHENSET_CH26_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH26_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH26_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 25 : Enable PPI channel 25. */
+#define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHENSET_CH25_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH25_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH25_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 24 : Enable PPI channel 24. */
+#define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHENSET_CH24_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH24_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH24_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 23 : Enable PPI channel 23. */
+#define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHENSET_CH23_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH23_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH23_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 22 : Enable PPI channel 22. */
+#define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHENSET_CH22_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH22_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH22_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 21 : Enable PPI channel 21. */
+#define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHENSET_CH21_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH21_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH21_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 20 : Enable PPI channel 20. */
+#define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHENSET_CH20_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH20_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH20_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 15 : Enable PPI channel 15. */
+#define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHENSET_CH15_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH15_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH15_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 14 : Enable PPI channel 14. */
+#define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHENSET_CH14_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH14_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH14_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 13 : Enable PPI channel 13. */
+#define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHENSET_CH13_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH13_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH13_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 12 : Enable PPI channel 12. */
+#define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHENSET_CH12_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH12_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH12_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 11 : Enable PPI channel 11. */
+#define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHENSET_CH11_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH11_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH11_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 10 : Enable PPI channel 10. */
+#define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHENSET_CH10_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH10_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH10_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 9 : Enable PPI channel 9. */
+#define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHENSET_CH9_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH9_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH9_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 8 : Enable PPI channel 8. */
+#define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHENSET_CH8_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH8_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH8_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 7 : Enable PPI channel 7. */
+#define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHENSET_CH7_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH7_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH7_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 6 : Enable PPI channel 6. */
+#define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHENSET_CH6_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH6_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH6_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 5 : Enable PPI channel 5. */
+#define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHENSET_CH5_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH5_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH5_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 4 : Enable PPI channel 4. */
+#define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHENSET_CH4_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH4_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH4_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 3 : Enable PPI channel 3. */
+#define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHENSET_CH3_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH3_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH3_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 2 : Enable PPI channel 2. */
+#define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHENSET_CH2_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH2_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH2_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 1 : Enable PPI channel 1. */
+#define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHENSET_CH1_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH1_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH1_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 0 : Enable PPI channel 0. */
+#define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHENSET_CH0_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH0_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH0_Set (1UL) /*!< Enable channel on write. */
+
+/* Register: PPI_CHENCLR */
+/* Description: Channel enable clear. */
+
+/* Bit 31 : Disable PPI channel 31. */
+#define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH31_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 30 : Disable PPI channel 30. */
+#define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH30_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 29 : Disable PPI channel 29. */
+#define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH29_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 28 : Disable PPI channel 28. */
+#define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH28_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 27 : Disable PPI channel 27. */
+#define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH27_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 26 : Disable PPI channel 26. */
+#define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH26_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 25 : Disable PPI channel 25. */
+#define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH25_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 24 : Disable PPI channel 24. */
+#define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH24_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 23 : Disable PPI channel 23. */
+#define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH23_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 22 : Disable PPI channel 22. */
+#define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH22_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 21 : Disable PPI channel 21. */
+#define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH21_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 20 : Disable PPI channel 20. */
+#define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH20_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 15 : Disable PPI channel 15. */
+#define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH15_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 14 : Disable PPI channel 14. */
+#define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH14_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 13 : Disable PPI channel 13. */
+#define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH13_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 12 : Disable PPI channel 12. */
+#define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH12_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 11 : Disable PPI channel 11. */
+#define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH11_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 10 : Disable PPI channel 10. */
+#define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH10_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 9 : Disable PPI channel 9. */
+#define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH9_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 8 : Disable PPI channel 8. */
+#define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH8_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 7 : Disable PPI channel 7. */
+#define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH7_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 6 : Disable PPI channel 6. */
+#define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH6_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 5 : Disable PPI channel 5. */
+#define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH5_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 4 : Disable PPI channel 4. */
+#define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH4_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 3 : Disable PPI channel 3. */
+#define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH3_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 2 : Disable PPI channel 2. */
+#define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH2_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 1 : Disable PPI channel 1. */
+#define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH1_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 0 : Disable PPI channel 0. */
+#define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH0_Clear (1UL) /*!< Disable channel on write. */
+
+/* Register: PPI_CHG */
+/* Description: Channel group configuration. */
+
+/* Bit 31 : Include CH31 in channel group. */
+#define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHG_CH31_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH31_Included (1UL) /*!< Channel included. */
+
+/* Bit 30 : Include CH30 in channel group. */
+#define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHG_CH30_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH30_Included (1UL) /*!< Channel included. */
+
+/* Bit 29 : Include CH29 in channel group. */
+#define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHG_CH29_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH29_Included (1UL) /*!< Channel included. */
+
+/* Bit 28 : Include CH28 in channel group. */
+#define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHG_CH28_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH28_Included (1UL) /*!< Channel included. */
+
+/* Bit 27 : Include CH27 in channel group. */
+#define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHG_CH27_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH27_Included (1UL) /*!< Channel included. */
+
+/* Bit 26 : Include CH26 in channel group. */
+#define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHG_CH26_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH26_Included (1UL) /*!< Channel included. */
+
+/* Bit 25 : Include CH25 in channel group. */
+#define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHG_CH25_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH25_Included (1UL) /*!< Channel included. */
+
+/* Bit 24 : Include CH24 in channel group. */
+#define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHG_CH24_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH24_Included (1UL) /*!< Channel included. */
+
+/* Bit 23 : Include CH23 in channel group. */
+#define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHG_CH23_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH23_Included (1UL) /*!< Channel included. */
+
+/* Bit 22 : Include CH22 in channel group. */
+#define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHG_CH22_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH22_Included (1UL) /*!< Channel included. */
+
+/* Bit 21 : Include CH21 in channel group. */
+#define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHG_CH21_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH21_Included (1UL) /*!< Channel included. */
+
+/* Bit 20 : Include CH20 in channel group. */
+#define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHG_CH20_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH20_Included (1UL) /*!< Channel included. */
+
+/* Bit 15 : Include CH15 in channel group. */
+#define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHG_CH15_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH15_Included (1UL) /*!< Channel included. */
+
+/* Bit 14 : Include CH14 in channel group. */
+#define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHG_CH14_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH14_Included (1UL) /*!< Channel included. */
+
+/* Bit 13 : Include CH13 in channel group. */
+#define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHG_CH13_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH13_Included (1UL) /*!< Channel included. */
+
+/* Bit 12 : Include CH12 in channel group. */
+#define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHG_CH12_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH12_Included (1UL) /*!< Channel included. */
+
+/* Bit 11 : Include CH11 in channel group. */
+#define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHG_CH11_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH11_Included (1UL) /*!< Channel included. */
+
+/* Bit 10 : Include CH10 in channel group. */
+#define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHG_CH10_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH10_Included (1UL) /*!< Channel included. */
+
+/* Bit 9 : Include CH9 in channel group. */
+#define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHG_CH9_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH9_Included (1UL) /*!< Channel included. */
+
+/* Bit 8 : Include CH8 in channel group. */
+#define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHG_CH8_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH8_Included (1UL) /*!< Channel included. */
+
+/* Bit 7 : Include CH7 in channel group. */
+#define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHG_CH7_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH7_Included (1UL) /*!< Channel included. */
+
+/* Bit 6 : Include CH6 in channel group. */
+#define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHG_CH6_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH6_Included (1UL) /*!< Channel included. */
+
+/* Bit 5 : Include CH5 in channel group. */
+#define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHG_CH5_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH5_Included (1UL) /*!< Channel included. */
+
+/* Bit 4 : Include CH4 in channel group. */
+#define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHG_CH4_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH4_Included (1UL) /*!< Channel included. */
+
+/* Bit 3 : Include CH3 in channel group. */
+#define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHG_CH3_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH3_Included (1UL) /*!< Channel included. */
+
+/* Bit 2 : Include CH2 in channel group. */
+#define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHG_CH2_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH2_Included (1UL) /*!< Channel included. */
+
+/* Bit 1 : Include CH1 in channel group. */
+#define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHG_CH1_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH1_Included (1UL) /*!< Channel included. */
+
+/* Bit 0 : Include CH0 in channel group. */
+#define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHG_CH0_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH0_Included (1UL) /*!< Channel included. */
+
+
+/* Peripheral: QDEC */
+/* Description: Rotary decoder. */
+
+/* Register: QDEC_SHORTS */
+/* Description: Shortcuts for the QDEC. */
+
+/* Bit 1 : Shortcut between SAMPLERDY event and STOP task. */
+#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */
+#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */
+#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task. */
+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */
+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */
+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Shortcut disabled. */
+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Register: QDEC_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 2 : Enable interrupt on ACCOF event. */
+#define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
+#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
+#define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */
+#define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */
+#define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on REPORTRDY event. */
+#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
+#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
+#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 0 : Enable interrupt on SAMPLERDY event. */
+#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
+#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
+#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: QDEC_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 2 : Disable interrupt on ACCOF event. */
+#define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
+#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
+#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */
+#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */
+#define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on REPORTRDY event. */
+#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
+#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
+#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 0 : Disable interrupt on SAMPLERDY event. */
+#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
+#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
+#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: QDEC_ENABLE */
+/* Description: Enable the QDEC. */
+
+/* Bit 0 : Enable or disable QDEC. */
+#define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled QDEC. */
+#define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable QDEC. */
+
+/* Register: QDEC_LEDPOL */
+/* Description: LED output pin polarity. */
+
+/* Bit 0 : LED output pin polarity. */
+#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */
+#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */
+#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< LED output is active low. */
+#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< LED output is active high. */
+
+/* Register: QDEC_SAMPLEPER */
+/* Description: Sample period. */
+
+/* Bits 2..0 : Sample period. */
+#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */
+#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */
+#define QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL) /*!< 128us sample period. */
+#define QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL) /*!< 256us sample period. */
+#define QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL) /*!< 512us sample period. */
+#define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL) /*!< 1024us sample period. */
+#define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL) /*!< 2048us sample period. */
+#define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL) /*!< 4096us sample period. */
+#define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL) /*!< 8192us sample period. */
+#define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL) /*!< 16384us sample period. */
+
+/* Register: QDEC_SAMPLE */
+/* Description: Motion sample value. */
+
+/* Bits 31..0 : Last sample taken in compliment to 2. */
+#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */
+#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */
+
+/* Register: QDEC_REPORTPER */
+/* Description: Number of samples to generate an EVENT_REPORTRDY. */
+
+/* Bits 2..0 : Number of samples to generate an EVENT_REPORTRDY. */
+#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */
+#define QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */
+#define QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL) /*!< 10 samples per report. */
+#define QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL) /*!< 40 samples per report. */
+#define QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL) /*!< 80 samples per report. */
+#define QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL) /*!< 120 samples per report. */
+#define QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL) /*!< 160 samples per report. */
+#define QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL) /*!< 200 samples per report. */
+#define QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL) /*!< 240 samples per report. */
+#define QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL) /*!< 280 samples per report. */
+
+/* Register: QDEC_DBFEN */
+/* Description: Enable debouncer input filters. */
+
+/* Bit 0 : Enable debounce input filters. */
+#define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */
+#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */
+#define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled. */
+#define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled. */
+
+/* Register: QDEC_LEDPRE */
+/* Description: Time LED is switched ON before the sample. */
+
+/* Bits 8..0 : Period in us the LED in switched on prior to sampling. */
+#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */
+#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */
+
+/* Register: QDEC_ACCDBL */
+/* Description: Accumulated double (error) transitions register. */
+
+/* Bits 3..0 : Accumulated double (error) transitions. */
+#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */
+#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */
+
+/* Register: QDEC_ACCDBLREAD */
+/* Description: Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC task. */
+
+/* Bits 3..0 : Snapshot of accumulated double (error) transitions. */
+#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */
+#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */
+
+/* Register: QDEC_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define QDEC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define QDEC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define QDEC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: RADIO */
+/* Description: The radio. */
+
+/* Register: RADIO_SHORTS */
+/* Description: Shortcuts for the radio. */
+
+/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 6 : Shortcut between ADDRESS event and BCSTART task. */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Shortcut disabled. */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 5 : Shortcut between END event and START task. */
+#define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */
+#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
+#define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */
+#define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task. */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Shortcut disabled. */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 3 : Shortcut between DISABLED event and RXEN task. */
+#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */
+#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */
+#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Shortcut disabled. */
+#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 2 : Shortcut between DISABLED event and TXEN task.  */
+#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
+#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */
+#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Shortcut disabled. */
+#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 1 : Shortcut between END event and DISABLE task. */
+#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */
+#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */
+#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Shortcut disabled. */
+#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 0 : Shortcut between READY event and START task. */
+#define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */
+#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */
+#define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Shortcut disabled. */
+#define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Register: RADIO_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 10 : Enable interrupt on BCMATCH event. */
+#define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
+#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
+#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 7 : Enable interrupt on RSSIEND event. */
+#define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
+#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
+#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 6 : Enable interrupt on DEVMISS event. */
+#define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
+#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
+#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 5 : Enable interrupt on DEVMATCH event. */
+#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
+#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
+#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 4 : Enable interrupt on DISABLED event. */
+#define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
+#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
+#define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 3 : Enable interrupt on END event. */
+#define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */
+#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define RADIO_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 2 : Enable interrupt on PAYLOAD event. */
+#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
+#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
+#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on ADDRESS event. */
+#define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
+#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 0 : Enable interrupt on READY event. */
+#define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
+#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define RADIO_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: RADIO_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 10 : Disable interrupt on BCMATCH event. */
+#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
+#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
+#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 7 : Disable interrupt on RSSIEND event. */
+#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
+#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
+#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 6 : Disable interrupt on DEVMISS event. */
+#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
+#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
+#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 5 : Disable interrupt on DEVMATCH event. */
+#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
+#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
+#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 4 : Disable interrupt on DISABLED event. */
+#define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
+#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
+#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 3 : Disable interrupt on END event. */
+#define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */
+#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define RADIO_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 2 : Disable interrupt on PAYLOAD event. */
+#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
+#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
+#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on ADDRESS event. */
+#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
+#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 0 : Disable interrupt on READY event. */
+#define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
+#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: RADIO_CRCSTATUS */
+/* Description: CRC status of received packet. */
+
+/* Bit 0 : CRC status of received packet. */
+#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */
+#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */
+#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error. */
+#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok. */
+
+/* Register: RADIO_RXMATCH */
+/* Description: Received address. */
+
+/* Bits 2..0 : Logical address in which previous packet was received. */
+#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */
+#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */
+
+/* Register: RADIO_RXCRC */
+/* Description: Received CRC. */
+
+/* Bits 23..0 : CRC field of previously received packet. */
+#define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */
+#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */
+
+/* Register: RADIO_DAI */
+/* Description: Device address match index. */
+
+/* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that obtained an address match. */
+#define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */
+#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */
+
+/* Register: RADIO_FREQUENCY */
+/* Description: Frequency. */
+
+/* Bits 6..0 : Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task.  */
+#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+
+/* Register: RADIO_TXPOWER */
+/* Description: Output power. */
+
+/* Bits 7..0 : Radio output power. Decision point: TXEN task. */
+#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */
+#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */
+#define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0dBm. */
+#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4dBm. */
+#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< -30dBm. */
+#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20dBm. */
+#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16dBm. */
+#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12dBm. */
+#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8dBm. */
+#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4dBm. */
+
+/* Register: RADIO_MODE */
+/* Description: Data rate and modulation. */
+
+/* Bits 1..0 : Radio data rate and modulation setting. Decision point: TXEN or RXEN task. */
+#define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define RADIO_MODE_MODE_Nrf_1Mbit (0x00UL) /*!< 1Mbit/s Nordic propietary radio mode. */
+#define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL) /*!< 2Mbit/s Nordic propietary radio mode. */
+#define RADIO_MODE_MODE_Nrf_250Kbit (0x02UL) /*!< 250kbit/s Nordic propietary radio mode. */
+#define RADIO_MODE_MODE_Ble_1Mbit (0x03UL) /*!< 1Mbit/s Bluetooth Low Energy */
+
+/* Register: RADIO_PCNF0 */
+/* Description: Packet configuration 0. */
+
+/* Bits 19..16 : Length of S1 field in number of bits. Decision point: START task. */
+#define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */
+#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */
+
+/* Bit 8 : Length of S0 field in number of bytes. Decision point: START task. */
+#define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */
+#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */
+
+/* Bits 3..0 : Length of length field in number of bits. Decision point: START task. */
+#define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */
+#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */
+
+/* Register: RADIO_PCNF1 */
+/* Description: Packet configuration 1. */
+
+/* Bit 25 : Packet whitening enable. */
+#define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */
+#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */
+#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Whitening disabled. */
+#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Whitening enabled. */
+
+/* Bit 24 : On air endianness of packet length field. Decision point: START task. */
+#define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */
+#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
+#define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */
+#define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */
+
+/* Bits 18..16 : Base address length in number of bytes. Decision point: START task. */
+#define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */
+#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */
+
+/* Bits 15..8 : Static length in number of bytes. Decision point: START task. */
+#define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */
+#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */
+
+/* Bits 7..0 : Maximum length of packet payload in number of bytes. */
+#define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
+#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
+
+/* Register: RADIO_PREFIX0 */
+/* Description: Prefixes bytes for logical addresses 0 to 3. */
+
+/* Bits 31..24 : Address prefix 3. Decision point: START task. */
+#define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */
+#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */
+
+/* Bits 23..16 : Address prefix 2. Decision point: START task. */
+#define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */
+#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */
+
+/* Bits 15..8 : Address prefix 1. Decision point: START task. */
+#define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */
+#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */
+
+/* Bits 7..0 : Address prefix 0. Decision point: START task. */
+#define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */
+#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */
+
+/* Register: RADIO_PREFIX1 */
+/* Description: Prefixes bytes for logical addresses 4 to 7. */
+
+/* Bits 31..24 : Address prefix 7. Decision point: START task. */
+#define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */
+#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */
+
+/* Bits 23..16 : Address prefix 6. Decision point: START task. */
+#define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */
+#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */
+
+/* Bits 15..8 : Address prefix 5. Decision point: START task. */
+#define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */
+#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */
+
+/* Bits 7..0 : Address prefix 4. Decision point: START task. */
+#define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */
+#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */
+
+/* Register: RADIO_TXADDRESS */
+/* Description: Transmit address select. */
+
+/* Bits 2..0 : Logical address to be used when transmitting a packet. Decision point: START task. */
+#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */
+#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */
+
+/* Register: RADIO_RXADDRESSES */
+/* Description: Receive address select. */
+
+/* Bit 7 : Enable reception on logical address 7. Decision point: START task. */
+#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */
+#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */
+#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Reception disabled. */
+#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Reception enabled. */
+
+/* Bit 6 : Enable reception on logical address 6. Decision point: START task. */
+#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */
+#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */
+#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Reception disabled. */
+#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Reception enabled. */
+
+/* Bit 5 : Enable reception on logical address 5. Decision point: START task. */
+#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */
+#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */
+#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Reception disabled. */
+#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Reception enabled. */
+
+/* Bit 4 : Enable reception on logical address 4. Decision point: START task. */
+#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */
+#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */
+#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Reception disabled. */
+#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Reception enabled. */
+
+/* Bit 3 : Enable reception on logical address 3. Decision point: START task. */
+#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */
+#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */
+#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Reception disabled. */
+#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Reception enabled. */
+
+/* Bit 2 : Enable reception on logical address 2. Decision point: START task. */
+#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
+#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */
+#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Reception disabled. */
+#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Reception enabled. */
+
+/* Bit 1 : Enable reception on logical address 1. Decision point: START task. */
+#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */
+#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */
+#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Reception disabled. */
+#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Reception enabled. */
+
+/* Bit 0 : Enable reception on logical address 0. Decision point: START task. */
+#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */
+#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */
+#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Reception disabled. */
+#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Reception enabled. */
+
+/* Register: RADIO_CRCCNF */
+/* Description: CRC configuration. */
+
+/* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */
+#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */
+#define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */
+#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< Include packet address in CRC calculation. */
+#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. */
+
+/* Bits 1..0 : CRC length. Decision point: START task. */
+#define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */
+#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */
+#define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC calculation disabled. */
+#define RADIO_CRCCNF_LEN_One (1UL) /*!< One byte long CRC. */
+#define RADIO_CRCCNF_LEN_Two (2UL) /*!< Two bytes long CRC. */
+#define RADIO_CRCCNF_LEN_Three (3UL) /*!< Three bytes long CRC. */
+
+/* Register: RADIO_CRCPOLY */
+/* Description: CRC polynomial. */
+
+/* Bits 23..0 : CRC polynomial. Decision point: START task. */
+#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */
+#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */
+
+/* Register: RADIO_CRCINIT */
+/* Description: CRC initial value. */
+
+/* Bits 23..0 : Initial value for CRC calculation. Decision point: START task. */
+#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */
+#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */
+
+/* Register: RADIO_TEST */
+/* Description: Test features enable register. */
+
+/* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */
+#define RADIO_TEST_PLLLOCK_Pos (1UL) /*!< Position of PLLLOCK field. */
+#define RADIO_TEST_PLLLOCK_Msk (0x1UL << RADIO_TEST_PLLLOCK_Pos) /*!< Bit mask of PLLLOCK field. */
+#define RADIO_TEST_PLLLOCK_Disabled (0UL) /*!< PLL lock disabled. */
+#define RADIO_TEST_PLLLOCK_Enabled (1UL) /*!< PLL lock enabled. */
+
+/* Bit 0 : Constant carrier. Decision point: TXEN task. */
+#define RADIO_TEST_CONSTCARRIER_Pos (0UL) /*!< Position of CONSTCARRIER field. */
+#define RADIO_TEST_CONSTCARRIER_Msk (0x1UL << RADIO_TEST_CONSTCARRIER_Pos) /*!< Bit mask of CONSTCARRIER field. */
+#define RADIO_TEST_CONSTCARRIER_Disabled (0UL) /*!< Constant carrier disabled. */
+#define RADIO_TEST_CONSTCARRIER_Enabled (1UL) /*!< Constant carrier enabled. */
+
+/* Register: RADIO_TIFS */
+/* Description: Inter Frame Spacing in microseconds. */
+
+/* Bits 7..0 : Inter frame spacing in microseconds. Decision point: START rask */
+#define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */
+#define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */
+
+/* Register: RADIO_RSSISAMPLE */
+/* Description: RSSI sample. */
+
+/* Bits 6..0 : RSSI sample result. The result is read as a positive value so that ReceivedSignalStrength = -RSSISAMPLE dBm */
+#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */
+#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */
+
+/* Register: RADIO_STATE */
+/* Description: Current radio state. */
+
+/* Bits 3..0 : Current radio state. */
+#define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */
+#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */
+#define RADIO_STATE_STATE_Disabled (0x00UL) /*!< Radio is in the Disabled state. */
+#define RADIO_STATE_STATE_RxRu (0x01UL) /*!< Radio is in the Rx Ramp Up state. */
+#define RADIO_STATE_STATE_RxIdle (0x02UL) /*!< Radio is in the Rx Idle state. */
+#define RADIO_STATE_STATE_Rx (0x03UL) /*!< Radio is in the Rx state. */
+#define RADIO_STATE_STATE_RxDisable (0x04UL) /*!< Radio is in the Rx Disable state. */
+#define RADIO_STATE_STATE_TxRu (0x09UL) /*!< Radio is in the Tx Ramp Up state. */
+#define RADIO_STATE_STATE_TxIdle (0x0AUL) /*!< Radio is in the Tx Idle state. */
+#define RADIO_STATE_STATE_Tx (0x0BUL) /*!< Radio is in the Tx state. */
+#define RADIO_STATE_STATE_TxDisable (0x0CUL) /*!< Radio is in the Tx Disable state. */
+
+/* Register: RADIO_DATAWHITEIV */
+/* Description: Data whitening initial value. */
+
+/* Bits 6..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */
+#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */
+#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */
+
+/* Register: RADIO_DAP */
+/* Description: Device address prefix. */
+
+/* Bits 15..0 : Device address prefix. */
+#define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */
+#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */
+
+/* Register: RADIO_DACNF */
+/* Description: Device address match configuration. */
+
+/* Bit 15 : TxAdd for device address 7. */
+#define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */
+#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */
+
+/* Bit 14 : TxAdd for device address 6. */
+#define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */
+#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */
+
+/* Bit 13 : TxAdd for device address 5. */
+#define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */
+#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */
+
+/* Bit 12 : TxAdd for device address 4. */
+#define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */
+#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */
+
+/* Bit 11 : TxAdd for device address 3. */
+#define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */
+#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */
+
+/* Bit 10 : TxAdd for device address 2. */
+#define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */
+#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */
+
+/* Bit 9 : TxAdd for device address 1. */
+#define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */
+#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */
+
+/* Bit 8 : TxAdd for device address 0. */
+#define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */
+#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */
+
+/* Bit 7 : Enable or disable device address matching using device address 7. */
+#define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */
+#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */
+#define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled. */
+#define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled. */
+
+/* Bit 6 : Enable or disable device address matching using device address 6. */
+#define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */
+#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */
+#define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled. */
+#define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled. */
+
+/* Bit 5 : Enable or disable device address matching using device address 5. */
+#define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */
+#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */
+#define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled. */
+#define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled. */
+
+/* Bit 4 : Enable or disable device address matching using device address 4. */
+#define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */
+#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */
+#define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled. */
+#define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled. */
+
+/* Bit 3 : Enable or disable device address matching using device address 3. */
+#define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */
+#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */
+#define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled. */
+#define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled. */
+
+/* Bit 2 : Enable or disable device address matching using device address 2. */
+#define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
+#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */
+#define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled. */
+#define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled. */
+
+/* Bit 1 : Enable or disable device address matching using device address 1. */
+#define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */
+#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */
+#define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled. */
+#define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled. */
+
+/* Bit 0 : Enable or disable device address matching using device address 0. */
+#define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */
+#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */
+#define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled. */
+#define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled. */
+
+/* Register: RADIO_OVERRIDE0 */
+/* Description: Trim value override register 0. */
+
+/* Bits 31..0 : Trim value override 0. */
+#define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /*!< Position of OVERRIDE0 field. */
+#define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /*!< Bit mask of OVERRIDE0 field. */
+
+/* Register: RADIO_OVERRIDE1 */
+/* Description: Trim value override register 1. */
+
+/* Bits 31..0 : Trim value override 1. */
+#define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /*!< Position of OVERRIDE1 field. */
+#define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /*!< Bit mask of OVERRIDE1 field. */
+
+/* Register: RADIO_OVERRIDE2 */
+/* Description: Trim value override register 2. */
+
+/* Bits 31..0 : Trim value override 2. */
+#define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /*!< Position of OVERRIDE2 field. */
+#define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /*!< Bit mask of OVERRIDE2 field. */
+
+/* Register: RADIO_OVERRIDE3 */
+/* Description: Trim value override register 3. */
+
+/* Bits 31..0 : Trim value override 3. */
+#define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /*!< Position of OVERRIDE3 field. */
+#define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /*!< Bit mask of OVERRIDE3 field. */
+
+/* Register: RADIO_OVERRIDE4 */
+/* Description: Trim value override register 4. */
+
+/* Bit 31 : Enable or disable override of default trim values. */
+#define RADIO_OVERRIDE4_ENABLE_Pos (31UL) /*!< Position of ENABLE field. */
+#define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /*!< Override trim values disabled. */
+#define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /*!< Override trim values enabled. */
+
+/* Bits 27..0 : Trim value override 4. */
+#define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /*!< Position of OVERRIDE4 field. */
+#define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /*!< Bit mask of OVERRIDE4 field. */
+
+/* Register: RADIO_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define RADIO_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define RADIO_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: RNG */
+/* Description: Random Number Generator. */
+
+/* Register: RNG_SHORTS */
+/* Description: Shortcuts for the RNG. */
+
+/* Bit 0 : Shortcut between VALRDY event and STOP task. */
+#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */
+#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */
+#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Register: RNG_INTENSET */
+/* Description: Interrupt enable set register */
+
+/* Bit 0 : Enable interrupt on VALRDY event. */
+#define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
+#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
+#define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: RNG_INTENCLR */
+/* Description: Interrupt enable clear register */
+
+/* Bit 0 : Disable interrupt on VALRDY event. */
+#define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
+#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
+#define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: RNG_CONFIG */
+/* Description: Configuration register. */
+
+/* Bit 0 : Digital error correction enable. */
+#define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */
+#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */
+#define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Digital error correction disabled. */
+#define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Digital error correction enabled. */
+
+/* Register: RNG_VALUE */
+/* Description: RNG random number. */
+
+/* Bits 7..0 : Generated random number. */
+#define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
+#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
+
+/* Register: RNG_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define RNG_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define RNG_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define RNG_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: RTC */
+/* Description: Real time counter 0. */
+
+/* Register: RTC_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 19 : Enable interrupt on COMPARE[3] event. */
+#define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 18 : Enable interrupt on COMPARE[2] event. */
+#define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 17 : Enable interrupt on COMPARE[1] event. */
+#define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 16 : Enable interrupt on COMPARE[0] event. */
+#define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on OVRFLW event. */
+#define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 0 : Enable interrupt on TICK event. */
+#define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_INTENSET_TICK_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENSET_TICK_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENSET_TICK_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: RTC_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 19 : Disable interrupt on COMPARE[3] event. */
+#define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 18 : Disable interrupt on COMPARE[2] event. */
+#define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 17 : Disable interrupt on COMPARE[1] event. */
+#define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 16 : Disable interrupt on COMPARE[0] event. */
+#define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on OVRFLW event. */
+#define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 0 : Disable interrupt on TICK event. */
+#define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: RTC_EVTEN */
+/* Description: Configures event enable routing to PPI for each RTC event. */
+
+/* Bit 19 : COMPARE[3] event enable. */
+#define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Event enabled. */
+
+/* Bit 18 : COMPARE[2] event enable. */
+#define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Event enabled. */
+
+/* Bit 17 : COMPARE[1] event enable. */
+#define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Event enabled. */
+
+/* Bit 16 : COMPARE[0] event enable. */
+#define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Event enabled. */
+
+/* Bit 1 : OVRFLW event enable. */
+#define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Event enabled. */
+
+/* Bit 0 : TICK event enable. */
+#define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_EVTEN_TICK_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Event enabled. */
+
+/* Register: RTC_EVTENSET */
+/* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN. */
+
+/* Bit 19 : Enable routing to PPI of COMPARE[3] event. */
+#define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable event on write. */
+
+/* Bit 18 : Enable routing to PPI of COMPARE[2] event. */
+#define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable event on write. */
+
+/* Bit 17 : Enable routing to PPI of COMPARE[1] event. */
+#define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable event on write. */
+
+/* Bit 16 : Enable routing to PPI of COMPARE[0] event. */
+#define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable event on write. */
+
+/* Bit 1 : Enable routing to PPI of OVRFLW event. */
+#define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable event on write. */
+
+/* Bit 0 : Enable routing to PPI of TICK event. */
+#define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable event on write. */
+
+/* Register: RTC_EVTENCLR */
+/* Description: Disable events routing to PPI. The reading of this register gives the value of EVTEN. */
+
+/* Bit 19 : Disable routing to PPI of COMPARE[3] event. */
+#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable event on write. */
+
+/* Bit 18 : Disable routing to PPI of COMPARE[2] event. */
+#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable event on write. */
+
+/* Bit 17 : Disable routing to PPI of COMPARE[1] event. */
+#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable event on write. */
+
+/* Bit 16 : Disable routing to PPI of COMPARE[0] event. */
+#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable event on write. */
+
+/* Bit 1 : Disable routing to PPI of OVRFLW event. */
+#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable event on write. */
+
+/* Bit 0 : Disable routing to PPI of TICK event. */
+#define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable event on write. */
+
+/* Register: RTC_COUNTER */
+/* Description: Current COUNTER value. */
+
+/* Bits 23..0 : Counter value. */
+#define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
+#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
+
+/* Register: RTC_PRESCALER */
+/* Description: 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */
+
+/* Bits 11..0 : RTC PRESCALER value. */
+#define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
+#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
+
+/* Register: RTC_CC */
+/* Description: Capture/compare registers. */
+
+/* Bits 23..0 : Compare value. */
+#define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
+#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
+
+/* Register: RTC_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define RTC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define RTC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define RTC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: SPI */
+/* Description: SPI master 0. */
+
+/* Register: SPI_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 2 : Enable interrupt on READY event. */
+#define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */
+#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define SPI_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPI_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPI_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: SPI_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 2 : Disable interrupt on READY event. */
+#define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */
+#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define SPI_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPI_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: SPI_ENABLE */
+/* Description: Enable SPI. */
+
+/* Bits 2..0 : Enable or disable SPI. */
+#define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define SPI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPI. */
+#define SPI_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable SPI. */
+
+/* Register: SPI_RXD */
+/* Description: RX data. */
+
+/* Bits 7..0 : RX data from last transfer. */
+#define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
+#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
+
+/* Register: SPI_TXD */
+/* Description: TX data. */
+
+/* Bits 7..0 : TX data for next transfer. */
+#define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
+#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
+
+/* Register: SPI_FREQUENCY */
+/* Description: SPI frequency */
+
+/* Bits 31..0 : SPI data rate. */
+#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125kbps. */
+#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250kbps. */
+#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500kbps. */
+#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1Mbps. */
+#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2Mbps. */
+#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4Mbps. */
+#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8Mbps. */
+
+/* Register: SPI_CONFIG */
+/* Description: Configuration register. */
+
+/* Bit 2 : Serial clock (SCK) polarity. */
+#define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
+#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
+#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
+#define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
+
+/* Bit 1 : Serial clock (SCK) phase. */
+#define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
+#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
+#define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
+#define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
+
+/* Bit 0 : Bit order. */
+#define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
+#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
+#define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
+#define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
+
+/* Register: SPI_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define SPI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define SPI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define SPI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: SPIS */
+/* Description: SPI slave 1. */
+
+/* Register: SPIS_SHORTS */
+/* Description: Shortcuts for SPIS. */
+
+/* Bit 2 : Shortcut between END event and the ACQUIRE task. */
+#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
+#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
+#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Shortcut disabled. */
+#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Register: SPIS_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 10 : Enable interrupt on ACQUIRED event. */
+#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
+#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
+#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 4 : enable interrupt on ENDRX event. */
+#define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on END event. */
+#define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
+#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define SPIS_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPIS_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPIS_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: SPIS_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 10 : Disable interrupt on ACQUIRED event. */
+#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
+#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
+#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 4 : Disable interrupt on ENDRX event. */
+#define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on END event. */
+#define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
+#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define SPIS_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPIS_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: SPIS_SEMSTAT */
+/* Description: Semaphore status. */
+
+/* Bits 1..0 : Semaphore status. */
+#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
+#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
+#define SPIS_SEMSTAT_SEMSTAT_Free (0x00UL) /*!< Semaphore is free. */
+#define SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL) /*!< Semaphore is assigned to the CPU. */
+#define SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL) /*!< Semaphore is assigned to the SPIS. */
+#define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL) /*!< Semaphore is assigned to the SPIS, but a handover to the CPU is pending. */
+
+/* Register: SPIS_STATUS */
+/* Description: Status from last transaction. */
+
+/* Bit 1 : RX buffer overflow detected, and prevented. */
+#define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
+#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
+#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Error not present. */
+#define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Error present. */
+#define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Clear on write. */
+
+/* Bit 0 : TX buffer overread detected, and prevented. */
+#define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
+#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
+#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Error not present. */
+#define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Error present. */
+#define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Clear on write. */
+
+/* Register: SPIS_ENABLE */
+/* Description: Enable SPIS. */
+
+/* Bits 2..0 : Enable or disable SPIS. */
+#define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define SPIS_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIS. */
+#define SPIS_ENABLE_ENABLE_Enabled (0x02UL) /*!< Enable SPIS. */
+
+/* Register: SPIS_MAXRX */
+/* Description: Maximum number of bytes in the receive buffer. */
+
+/* Bits 7..0 : Maximum number of bytes in the receive buffer. */
+#define SPIS_MAXRX_MAXRX_Pos (0UL) /*!< Position of MAXRX field. */
+#define SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos) /*!< Bit mask of MAXRX field. */
+
+/* Register: SPIS_AMOUNTRX */
+/* Description: Number of bytes received in last granted transaction. */
+
+/* Bits 7..0 : Number of bytes received in last granted transaction. */
+#define SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL) /*!< Position of AMOUNTRX field. */
+#define SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos) /*!< Bit mask of AMOUNTRX field. */
+
+/* Register: SPIS_MAXTX */
+/* Description: Maximum number of bytes in the transmit buffer. */
+
+/* Bits 7..0 : Maximum number of bytes in the transmit buffer. */
+#define SPIS_MAXTX_MAXTX_Pos (0UL) /*!< Position of MAXTX field. */
+#define SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos) /*!< Bit mask of MAXTX field. */
+
+/* Register: SPIS_AMOUNTTX */
+/* Description: Number of bytes transmitted in last granted transaction. */
+
+/* Bits 7..0 : Number of bytes transmitted in last granted transaction. */
+#define SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL) /*!< Position of AMOUNTTX field. */
+#define SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos) /*!< Bit mask of AMOUNTTX field. */
+
+/* Register: SPIS_CONFIG */
+/* Description: Configuration register. */
+
+/* Bit 2 : Serial clock (SCK) polarity. */
+#define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
+#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
+#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
+#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
+
+/* Bit 1 : Serial clock (SCK) phase. */
+#define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
+#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
+#define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
+#define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
+
+/* Bit 0 : Bit order. */
+#define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
+#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
+#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
+#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
+
+/* Register: SPIS_DEF */
+/* Description: Default character. */
+
+/* Bits 7..0 : Default character. */
+#define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
+#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
+
+/* Register: SPIS_ORC */
+/* Description: Over-read character. */
+
+/* Bits 7..0 : Over-read character. */
+#define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
+#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
+
+/* Register: SPIS_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define SPIS_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define SPIS_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define SPIS_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: TEMP */
+/* Description: Temperature Sensor. */
+
+/* Register: TEMP_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 0 : Enable interrupt on DATARDY event. */
+#define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
+#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
+#define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: TEMP_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 0 : Disable interrupt on DATARDY event. */
+#define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
+#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
+#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: TEMP_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define TEMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define TEMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define TEMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: TIMER */
+/* Description: Timer 0. */
+
+/* Register: TIMER_SHORTS */
+/* Description: Shortcuts for Timer. */
+
+/* Bit 11 : Shortcut between CC[3] event and the STOP task. */
+#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
+#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
+#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 10 : Shortcut between CC[2] event and the STOP task. */
+#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
+#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
+#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 9 : Shortcut between CC[1] event and the STOP task. */
+#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
+#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
+#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 8 : Shortcut between CC[0] event and the STOP task. */
+#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
+#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
+#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 3 : Shortcut between CC[3] event and the CLEAR task. */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 2 : Shortcut between CC[2] event and the CLEAR task. */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 1 : Shortcut between CC[1] event and the CLEAR task. */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 0 : Shortcut between CC[0] event and the CLEAR task. */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Register: TIMER_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 19 : Enable interrupt on COMPARE[3] */
+#define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
+#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
+#define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 18 : Enable interrupt on COMPARE[2] */
+#define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
+#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
+#define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 17 : Enable interrupt on COMPARE[1] */
+#define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
+#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
+#define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 16 : Enable interrupt on COMPARE[0] */
+#define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
+#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
+#define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: TIMER_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 19 : Disable interrupt on COMPARE[3] */
+#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
+#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
+#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 18 : Disable interrupt on COMPARE[2] */
+#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
+#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
+#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 17 : Disable interrupt on COMPARE[1] */
+#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
+#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
+#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 16 : Disable interrupt on COMPARE[0] */
+#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
+#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
+#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: TIMER_MODE */
+/* Description: Timer Mode selection. */
+
+/* Bit 0 : Select Normal or Counter mode. */
+#define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define TIMER_MODE_MODE_Timer (0UL) /*!< Timer in Normal mode. */
+#define TIMER_MODE_MODE_Counter (1UL) /*!< Timer in Counter mode. */
+
+/* Register: TIMER_BITMODE */
+/* Description: Sets timer behaviour. */
+
+/* Bits 1..0 : Sets timer behaviour ro be like the implementation of a timer with width as indicated. */
+#define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
+#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
+#define TIMER_BITMODE_BITMODE_16Bit (0x00UL) /*!< 16-bit timer behaviour. */
+#define TIMER_BITMODE_BITMODE_08Bit (0x01UL) /*!< 8-bit timer behaviour. */
+#define TIMER_BITMODE_BITMODE_24Bit (0x02UL) /*!< 24-bit timer behaviour. */
+#define TIMER_BITMODE_BITMODE_32Bit (0x03UL) /*!< 32-bit timer behaviour. */
+
+/* Register: TIMER_PRESCALER */
+/* Description: 4-bit prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. */
+
+/* Bits 3..0 : Timer PRESCALER value. Max value is 9. */
+#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
+#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
+
+/* Register: TIMER_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define TIMER_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define TIMER_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define TIMER_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: TWI */
+/* Description: Two-wire interface master 0. */
+
+/* Register: TWI_SHORTS */
+/* Description: Shortcuts for TWI. */
+
+/* Bit 1 : Shortcut between BB event and the STOP task. */
+#define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */
+#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */
+#define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 0 : Shortcut between BB event and the SUSPEND task. */
+#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */
+#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */
+#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Shortcut disabled. */
+#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Register: TWI_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 18 : Enable interrupt on SUSPENDED event. */
+#define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 14 : Enable interrupt on BB event. */
+#define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */
+#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */
+#define TWI_INTENSET_BB_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENSET_BB_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENSET_BB_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 9 : Enable interrupt on ERROR event. */
+#define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 7 : Enable interrupt on TXDSENT event. */
+#define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
+#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
+#define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 2 : Enable interrupt on READY event. */
+#define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
+#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
+#define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on STOPPED event. */
+#define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: TWI_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 18 : Disable interrupt on SUSPENDED event. */
+#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 14 : Disable interrupt on BB event. */
+#define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */
+#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */
+#define TWI_INTENCLR_BB_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENCLR_BB_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 9 : Disable interrupt on ERROR event. */
+#define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 7 : Disable interrupt on TXDSENT event. */
+#define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
+#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
+#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 2 : Disable interrupt on RXDREADY event. */
+#define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
+#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
+#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on STOPPED event. */
+#define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: TWI_ERRORSRC */
+/* Description: Two-wire error source. Write error field to 1 to clear error. */
+
+/* Bit 2 : NACK received after sending a data byte. */
+#define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
+#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
+#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Error not present. */
+#define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Error present. */
+#define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Clear error on write. */
+
+/* Bit 1 : NACK received after sending the address. */
+#define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
+#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
+#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Error not present. */
+#define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Error present. */
+#define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Clear error on write. */
+
+/* Bit 0 : Byte received in RXD register before read of the last received byte (data loss). */
+#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
+#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
+#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Error not present. */
+#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Error present. */
+#define TWI_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */
+
+/* Register: TWI_ENABLE */
+/* Description: Enable two-wire master. */
+
+/* Bits 2..0 : Enable or disable W2M */
+#define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define TWI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled. */
+#define TWI_ENABLE_ENABLE_Enabled (0x05UL) /*!< Enabled. */
+
+/* Register: TWI_RXD */
+/* Description: RX data register. */
+
+/* Bits 7..0 : RX data from last transfer. */
+#define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
+#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
+
+/* Register: TWI_TXD */
+/* Description: TX data register. */
+
+/* Bits 7..0 : TX data for next transfer. */
+#define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
+#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
+
+/* Register: TWI_FREQUENCY */
+/* Description: Two-wire frequency. */
+
+/* Bits 31..0 : Two-wire master clock frequency. */
+#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps. */
+#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */
+#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps (actual rate 410.256 kbps). */
+
+/* Register: TWI_ADDRESS */
+/* Description: Address used in the two-wire transfer. */
+
+/* Bits 6..0 : Two-wire address. */
+#define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
+#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+
+/* Register: TWI_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define TWI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define TWI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define TWI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: UART */
+/* Description: Universal Asynchronous Receiver/Transmitter. */
+
+/* Register: UART_SHORTS */
+/* Description: Shortcuts for UART. */
+
+/* Bit 4 : Shortcut between NCTS event and STOPRX task. */
+#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */
+#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */
+#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Shortcut disabled. */
+#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 3 : Shortcut between CTS event and STARTRX task. */
+#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */
+#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */
+#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Shortcut disabled. */
+#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Register: UART_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 17 : Enable interrupt on RXTO event. */
+#define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UART_INTENSET_RXTO_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENSET_RXTO_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENSET_RXTO_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 9 : Enable interrupt on ERROR event. */
+#define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UART_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 7 : Enable interrupt on TXRDY event. */
+#define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 2 : Enable interrupt on RXRDY event. */
+#define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on NCTS event. */
+#define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UART_INTENSET_NCTS_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENSET_NCTS_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENSET_NCTS_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 0 : Enable interrupt on CTS event. */
+#define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UART_INTENSET_CTS_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENSET_CTS_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENSET_CTS_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: UART_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 17 : Disable interrupt on RXTO event. */
+#define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 9 : Disable interrupt on ERROR event. */
+#define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 7 : Disable interrupt on TXRDY event. */
+#define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 2 : Disable interrupt on RXRDY event. */
+#define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on NCTS event. */
+#define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 0 : Disable interrupt on CTS event. */
+#define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UART_INTENCLR_CTS_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENCLR_CTS_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: UART_ERRORSRC */
+/* Description: Error source. Write error field to 1 to clear error. */
+
+/* Bit 3 : The serial data input is '0' for longer than the length of a data frame. */
+#define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
+#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
+#define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Error not present. */
+#define UART_ERRORSRC_BREAK_Present (1UL) /*!< Error present. */
+#define UART_ERRORSRC_BREAK_Clear (1UL) /*!< Clear error on write. */
+
+/* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character have been received. */
+#define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
+#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
+#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Error not present. */
+#define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Error present. */
+#define UART_ERRORSRC_FRAMING_Clear (1UL) /*!< Clear error on write. */
+
+/* Bit 1 : A character with bad parity is received. Only checked if HW parity control is enabled. */
+#define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
+#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Error not present. */
+#define UART_ERRORSRC_PARITY_Present (1UL) /*!< Error present. */
+#define UART_ERRORSRC_PARITY_Clear (1UL) /*!< Clear error on write. */
+
+/* Bit 0 : A start bit is received while the previous data still lies in RXD. (Data loss). */
+#define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
+#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
+#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Error not present. */
+#define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Error present. */
+#define UART_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */
+
+/* Register: UART_ENABLE */
+/* Description: Enable UART and acquire IOs. */
+
+/* Bits 2..0 : Enable or disable UART and acquire IOs. */
+#define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define UART_ENABLE_ENABLE_Disabled (0x00UL) /*!< UART disabled. */
+#define UART_ENABLE_ENABLE_Enabled (0x04UL) /*!< UART enabled. */
+
+/* Register: UART_RXD */
+/* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consumed. If read when no character available, the UART will stop working. */
+
+/* Bits 7..0 : RX data from previous transfer. Double buffered. */
+#define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
+#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
+
+/* Register: UART_TXD */
+/* Description: TXD register. */
+
+/* Bits 7..0 : TX data for transfer. */
+#define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
+#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
+
+/* Register: UART_BAUDRATE */
+/* Description: UART Baudrate. */
+
+/* Bits 31..0 : UART baudrate. */
+#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
+#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
+#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1M baud. */
+
+/* Register: UART_CONFIG */
+/* Description: Configuration of parity and hardware flow control register. */
+
+/* Bits 3..1 : Include parity bit. */
+#define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
+#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define UART_CONFIG_PARITY_Excluded (0UL) /*!< Parity bit excluded. */
+#define UART_CONFIG_PARITY_Included (7UL) /*!< Parity bit included. */
+
+/* Bit 0 : Hardware flow control. */
+#define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
+#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
+#define UART_CONFIG_HWFC_Disabled (0UL) /*!< Hardware flow control disabled. */
+#define UART_CONFIG_HWFC_Enabled (1UL) /*!< Hardware flow control enabled. */
+
+/* Register: UART_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define UART_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define UART_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define UART_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: UICR */
+/* Description: User Information Configuration. */
+
+/* Register: UICR_RBPCONF */
+/* Description: Readback protection configuration. */
+
+/* Bits 15..8 : Readback protect all code in the device. */
+#define UICR_RBPCONF_PALL_Pos (8UL) /*!< Position of PALL field. */
+#define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /*!< Bit mask of PALL field. */
+#define UICR_RBPCONF_PALL_Enabled (0x00UL) /*!< Enabled. */
+#define UICR_RBPCONF_PALL_Disabled (0xFFUL) /*!< Disabled. */
+
+/* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */
+#define UICR_RBPCONF_PR0_Pos (0UL) /*!< Position of PR0 field. */
+#define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /*!< Bit mask of PR0 field. */
+#define UICR_RBPCONF_PR0_Enabled (0x00UL) /*!< Enabled. */
+#define UICR_RBPCONF_PR0_Disabled (0xFFUL) /*!< Disabled. */
+
+/* Register: UICR_XTALFREQ */
+/* Description: Reset value for CLOCK XTALFREQ register. */
+
+/* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */
+#define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */
+#define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */
+#define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz Xtal is used. */
+#define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz Xtal is used. */
+
+/* Register: UICR_FWID */
+/* Description: Firmware ID. */
+
+/* Bits 15..0 : Identification number for the firmware loaded into the chip. */
+#define UICR_FWID_FWID_Pos (0UL) /*!< Position of FWID field. */
+#define UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos) /*!< Bit mask of FWID field. */
+
+
+/* Peripheral: WDT */
+/* Description: Watchdog Timer. */
+
+/* Register: WDT_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 0 : Enable interrupt on TIMEOUT event. */
+#define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
+#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
+#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */
+#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */
+#define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: WDT_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 0 : Disable interrupt on TIMEOUT event. */
+#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
+#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
+#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */
+#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */
+#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: WDT_RUNSTATUS */
+/* Description: Watchdog running status. */
+
+/* Bit 0 : Watchdog running status. */
+#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */
+#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */
+#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog timer is not running. */
+#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog timer is running. */
+
+/* Register: WDT_REQSTATUS */
+/* Description: Request status. */
+
+/* Bit 7 : Request status for RR[7]. */
+#define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
+#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
+#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled or has already requested reload. */
+#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled and has not jet requested. */
+
+/* Bit 6 : Request status for RR[6]. */
+#define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
+#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
+#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled or has already requested reload. */
+#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled and has not jet requested. */
+
+/* Bit 5 : Request status for RR[5]. */
+#define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
+#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
+#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled or has already requested reload. */
+#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled and has not jet requested. */
+
+/* Bit 4 : Request status for RR[4]. */
+#define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
+#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
+#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled or has already requested reload. */
+#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled and has not jet requested. */
+
+/* Bit 3 : Request status for RR[3]. */
+#define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
+#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
+#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled or has already requested reload. */
+#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled and has not jet requested. */
+
+/* Bit 2 : Request status for RR[2]. */
+#define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
+#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
+#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled or has already requested reload. */
+#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled and has not jet requested. */
+
+/* Bit 1 : Request status for RR[1]. */
+#define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
+#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
+#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled or has already requested reload. */
+#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled and has not jet requested. */
+
+/* Bit 0 : Request status for RR[0]. */
+#define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
+#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
+#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled or has already requested reload. */
+#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled and has not jet requested. */
+
+/* Register: WDT_RREN */
+/* Description: Reload request enable. */
+
+/* Bit 7 : Enable or disable RR[7] register. */
+#define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
+#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
+#define WDT_RREN_RR7_Disabled (0UL) /*!< RR[7] register is disabled. */
+#define WDT_RREN_RR7_Enabled (1UL) /*!< RR[7] register is enabled. */
+
+/* Bit 6 : Enable or disable RR[6] register. */
+#define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
+#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
+#define WDT_RREN_RR6_Disabled (0UL) /*!< RR[6] register is disabled. */
+#define WDT_RREN_RR6_Enabled (1UL) /*!< RR[6] register is enabled. */
+
+/* Bit 5 : Enable or disable RR[5] register. */
+#define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
+#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
+#define WDT_RREN_RR5_Disabled (0UL) /*!< RR[5] register is disabled. */
+#define WDT_RREN_RR5_Enabled (1UL) /*!< RR[5] register is enabled. */
+
+/* Bit 4 : Enable or disable RR[4] register. */
+#define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
+#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
+#define WDT_RREN_RR4_Disabled (0UL) /*!< RR[4] register is disabled. */
+#define WDT_RREN_RR4_Enabled (1UL) /*!< RR[4] register is enabled. */
+
+/* Bit 3 : Enable or disable RR[3] register. */
+#define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
+#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
+#define WDT_RREN_RR3_Disabled (0UL) /*!< RR[3] register is disabled. */
+#define WDT_RREN_RR3_Enabled (1UL) /*!< RR[3] register is enabled. */
+
+/* Bit 2 : Enable or disable RR[2] register. */
+#define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
+#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
+#define WDT_RREN_RR2_Disabled (0UL) /*!< RR[2] register is disabled. */
+#define WDT_RREN_RR2_Enabled (1UL) /*!< RR[2] register is enabled. */
+
+/* Bit 1 : Enable or disable RR[1] register. */
+#define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
+#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
+#define WDT_RREN_RR1_Disabled (0UL) /*!< RR[1] register is disabled. */
+#define WDT_RREN_RR1_Enabled (1UL) /*!< RR[1] register is enabled. */
+
+/* Bit 0 : Enable or disable RR[0] register. */
+#define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
+#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
+#define WDT_RREN_RR0_Disabled (0UL) /*!< RR[0] register is disabled. */
+#define WDT_RREN_RR0_Enabled (1UL) /*!< RR[0] register is enabled. */
+
+/* Register: WDT_CONFIG */
+/* Description: Configuration register. */
+
+/* Bit 3 : Configure the watchdog to pause or not while the CPU is halted by the debugger. */
+#define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
+#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
+#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger. */
+#define WDT_CONFIG_HALT_Run (1UL) /*!< Do not pause watchdog while the CPU is halted by the debugger. */
+
+/* Bit 0 : Configure the watchdog to pause or not while the CPU is sleeping. */
+#define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
+#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
+#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is asleep. */
+#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Do not pause watchdog while the CPU is asleep. */
+
+/* Register: WDT_RR */
+/* Description: Reload requests registers. */
+
+/* Bits 31..0 : Reload register. */
+#define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
+#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
+#define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer. */
+
+/* Register: WDT_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define WDT_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define WDT_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define WDT_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/*lint --flb "Leave library region" */
+#endif
diff --git a/ports/nrf/device/nrf51/nrf51_deprecated.h b/ports/nrf/device/nrf51/nrf51_deprecated.h
new file mode 100644
index 0000000000..1a7860f693
--- /dev/null
+++ b/ports/nrf/device/nrf51/nrf51_deprecated.h
@@ -0,0 +1,440 @@
+/* Copyright (c) 2016, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *   * Redistributions of source code must retain the above copyright notice, this
+ *     list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *
+ *   * Neither the name of Nordic Semiconductor ASA nor the names of its
+ *     contributors may be used to endorse or promote products derived from
+ *     this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+ 
+#ifndef NRF51_DEPRECATED_H
+#define NRF51_DEPRECATED_H
+
+/*lint ++flb "Enter library region */
+
+/* This file is given to prevent your SW from not compiling with the updates made to nrf51.h and 
+ * nrf51_bitfields.h. The macros defined in this file were available previously. Do not use these
+ * macros on purpose. Use the ones defined in nrf51.h and nrf51_bitfields.h instead.
+ */
+
+/* NVMC */
+/* The register ERASEPROTECTEDPAGE is called ERASEPCR0 in the documentation. */
+#define ERASEPROTECTEDPAGE   ERASEPCR0
+
+ 
+/* LPCOMP */
+/* The interrupt ISR was renamed. Adding old name to the macros. */
+#define LPCOMP_COMP_IRQHandler          LPCOMP_IRQHandler
+#define LPCOMP_COMP_IRQn                LPCOMP_IRQn
+/* Corrected typo in RESULT register. */
+#define LPCOMP_RESULT_RESULT_Bellow     LPCOMP_RESULT_RESULT_Below
+ 
+ 
+/* MPU */
+/* The field MPU.PERR0.LPCOMP_COMP was renamed. Added into deprecated in case somebody was using the macros defined for it. */
+#define MPU_PERR0_LPCOMP_COMP_Pos           MPU_PERR0_LPCOMP_Pos
+#define MPU_PERR0_LPCOMP_COMP_Msk           MPU_PERR0_LPCOMP_Msk
+#define MPU_PERR0_LPCOMP_COMP_InRegion1     MPU_PERR0_LPCOMP_InRegion1
+#define MPU_PERR0_LPCOMP_COMP_InRegion0     MPU_PERR0_LPCOMP_InRegion0
+ 
+ 
+/* POWER */
+/* The field POWER.RAMON.OFFRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
+#define POWER_RAMON_OFFRAM3_Pos         (19UL)                                  
+#define POWER_RAMON_OFFRAM3_Msk         (0x1UL << POWER_RAMON_OFFRAM3_Pos)      
+#define POWER_RAMON_OFFRAM3_RAM3Off     (0UL)                                   
+#define POWER_RAMON_OFFRAM3_RAM3On      (1UL)                                   
+/* The field POWER.RAMON.OFFRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
+#define POWER_RAMON_OFFRAM2_Pos         (18UL)                                  
+#define POWER_RAMON_OFFRAM2_Msk         (0x1UL << POWER_RAMON_OFFRAM2_Pos)      
+#define POWER_RAMON_OFFRAM2_RAM2Off     (0UL)                                   
+#define POWER_RAMON_OFFRAM2_RAM2On      (1UL)                                  
+/* The field POWER.RAMON.ONRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
+#define POWER_RAMON_ONRAM3_Pos          (3UL)                                  
+#define POWER_RAMON_ONRAM3_Msk          (0x1UL << POWER_RAMON_ONRAM3_Pos)      
+#define POWER_RAMON_ONRAM3_RAM3Off      (0UL)                                  
+#define POWER_RAMON_ONRAM3_RAM3On       (1UL)                                  
+/* The field POWER.RAMON.ONRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
+#define POWER_RAMON_ONRAM2_Pos          (2UL)                                  
+#define POWER_RAMON_ONRAM2_Msk          (0x1UL << POWER_RAMON_ONRAM2_Pos)       
+#define POWER_RAMON_ONRAM2_RAM2Off      (0UL)                                  
+#define POWER_RAMON_ONRAM2_RAM2On       (1UL)                                 
+
+ 
+/* RADIO */
+/* The enumerated value RADIO.TXPOWER.TXPOWER.Neg40dBm was renamed. Added into deprecated with the new macro name. */
+#define RADIO_TXPOWER_TXPOWER_Neg40dBm  RADIO_TXPOWER_TXPOWER_Neg30dBm      
+/* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */
+#define RADIO_CRCCNF_SKIP_ADDR_Pos      RADIO_CRCCNF_SKIPADDR_Pos 
+#define RADIO_CRCCNF_SKIP_ADDR_Msk      RADIO_CRCCNF_SKIPADDR_Msk 
+#define RADIO_CRCCNF_SKIP_ADDR_Include  RADIO_CRCCNF_SKIPADDR_Include 
+#define RADIO_CRCCNF_SKIP_ADDR_Skip     RADIO_CRCCNF_SKIPADDR_Skip 
+/* The name of the field PLLLOCK was corrected. Old macros added for compatibility. */
+#define RADIO_TEST_PLL_LOCK_Pos         RADIO_TEST_PLLLOCK_Pos 
+#define RADIO_TEST_PLL_LOCK_Msk         RADIO_TEST_PLLLOCK_Msk 
+#define RADIO_TEST_PLL_LOCK_Disabled    RADIO_TEST_PLLLOCK_Disabled 
+#define RADIO_TEST_PLL_LOCK_Enabled     RADIO_TEST_PLLLOCK_Enabled 
+/* The name of the field CONSTCARRIER was corrected. Old macros added for compatibility. */
+#define RADIO_TEST_CONST_CARRIER_Pos        RADIO_TEST_CONSTCARRIER_Pos 
+#define RADIO_TEST_CONST_CARRIER_Msk        RADIO_TEST_CONSTCARRIER_Msk 
+#define RADIO_TEST_CONST_CARRIER_Disabled   RADIO_TEST_CONSTCARRIER_Disabled 
+#define RADIO_TEST_CONST_CARRIER_Enabled    RADIO_TEST_CONSTCARRIER_Enabled 
+
+
+/* FICR */
+/* The registers FICR.SIZERAMBLOCK0, FICR.SIZERAMBLOCK1, FICR.SIZERAMBLOCK2 and FICR.SIZERAMBLOCK3 were renamed into an array. */
+#define SIZERAMBLOCK0   SIZERAMBLOCKS                   
+#define SIZERAMBLOCK1   SIZERAMBLOCKS                   
+#define SIZERAMBLOCK2   SIZERAMBLOCK[2]                 /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */
+#define SIZERAMBLOCK3   SIZERAMBLOCK[3]                 /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */
+/* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */
+#define DEVICEID0       DEVICEID[0]                     
+#define DEVICEID1       DEVICEID[1]                     
+/* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */
+#define ER0             ER[0]                           
+#define ER1             ER[1]                          
+#define ER2             ER[2]                       
+#define ER3             ER[3]                      
+/* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */
+#define IR0             IR[0]                         
+#define IR1             IR[1]                         
+#define IR2             IR[2]                         
+#define IR3             IR[3]                          
+/* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */
+#define DEVICEADDR0     DEVICEADDR[0]                  
+#define DEVICEADDR1     DEVICEADDR[1]                  
+
+
+/* PPI */
+/* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */
+#define TASKS_CHG0EN     TASKS_CHG[0].EN                    
+#define TASKS_CHG0DIS    TASKS_CHG[0].DIS                  
+#define TASKS_CHG1EN     TASKS_CHG[1].EN                    
+#define TASKS_CHG1DIS    TASKS_CHG[1].DIS                  
+#define TASKS_CHG2EN     TASKS_CHG[2].EN                   
+#define TASKS_CHG2DIS    TASKS_CHG[2].DIS                  
+#define TASKS_CHG3EN     TASKS_CHG[3].EN                    
+#define TASKS_CHG3DIS    TASKS_CHG[3].DIS                  
+/* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */
+#define CH0_EEP          CH[0].EEP                          
+#define CH0_TEP          CH[0].TEP                          
+#define CH1_EEP          CH[1].EEP                         
+#define CH1_TEP          CH[1].TEP                         
+#define CH2_EEP          CH[2].EEP                          
+#define CH2_TEP          CH[2].TEP                         
+#define CH3_EEP          CH[3].EEP                          
+#define CH3_TEP          CH[3].TEP                         
+#define CH4_EEP          CH[4].EEP                         
+#define CH4_TEP          CH[4].TEP                         
+#define CH5_EEP          CH[5].EEP                          
+#define CH5_TEP          CH[5].TEP                          
+#define CH6_EEP          CH[6].EEP                          
+#define CH6_TEP          CH[6].TEP                         
+#define CH7_EEP          CH[7].EEP                          
+#define CH7_TEP          CH[7].TEP                          
+#define CH8_EEP          CH[8].EEP                         
+#define CH8_TEP          CH[8].TEP                          
+#define CH9_EEP          CH[9].EEP                          
+#define CH9_TEP          CH[9].TEP                          
+#define CH10_EEP         CH[10].EEP                         
+#define CH10_TEP         CH[10].TEP                         
+#define CH11_EEP         CH[11].EEP                         
+#define CH11_TEP         CH[11].TEP                         
+#define CH12_EEP         CH[12].EEP                         
+#define CH12_TEP         CH[12].TEP                         
+#define CH13_EEP         CH[13].EEP                         
+#define CH13_TEP         CH[13].TEP                         
+#define CH14_EEP         CH[14].EEP                         
+#define CH14_TEP         CH[14].TEP                         
+#define CH15_EEP         CH[15].EEP                         
+#define CH15_TEP         CH[15].TEP                        
+/* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */
+#define CHG0             CHG[0]                            
+#define CHG1             CHG[1]                            
+#define CHG2             CHG[2]                             
+#define CHG3             CHG[3]                           
+/* All bitfield macros for the CHGx registers therefore changed name. */
+#define PPI_CHG0_CH15_Pos       PPI_CHG_CH15_Pos            
+#define PPI_CHG0_CH15_Msk       PPI_CHG_CH15_Msk            
+#define PPI_CHG0_CH15_Excluded  PPI_CHG_CH15_Excluded       
+#define PPI_CHG0_CH15_Included  PPI_CHG_CH15_Included       
+#define PPI_CHG0_CH14_Pos       PPI_CHG_CH14_Pos            
+#define PPI_CHG0_CH14_Msk       PPI_CHG_CH14_Msk           
+#define PPI_CHG0_CH14_Excluded  PPI_CHG_CH14_Excluded       
+#define PPI_CHG0_CH14_Included  PPI_CHG_CH14_Included       
+#define PPI_CHG0_CH13_Pos       PPI_CHG_CH13_Pos            
+#define PPI_CHG0_CH13_Msk       PPI_CHG_CH13_Msk            
+#define PPI_CHG0_CH13_Excluded  PPI_CHG_CH13_Excluded      
+#define PPI_CHG0_CH13_Included  PPI_CHG_CH13_Included       
+#define PPI_CHG0_CH12_Pos       PPI_CHG_CH12_Pos            
+#define PPI_CHG0_CH12_Msk       PPI_CHG_CH12_Msk            
+#define PPI_CHG0_CH12_Excluded  PPI_CHG_CH12_Excluded       
+#define PPI_CHG0_CH12_Included  PPI_CHG_CH12_Included       
+#define PPI_CHG0_CH11_Pos       PPI_CHG_CH11_Pos            
+#define PPI_CHG0_CH11_Msk       PPI_CHG_CH11_Msk            
+#define PPI_CHG0_CH11_Excluded  PPI_CHG_CH11_Excluded       
+#define PPI_CHG0_CH11_Included  PPI_CHG_CH11_Included       
+#define PPI_CHG0_CH10_Pos       PPI_CHG_CH10_Pos            
+#define PPI_CHG0_CH10_Msk       PPI_CHG_CH10_Msk            
+#define PPI_CHG0_CH10_Excluded  PPI_CHG_CH10_Excluded       
+#define PPI_CHG0_CH10_Included  PPI_CHG_CH10_Included       
+#define PPI_CHG0_CH9_Pos        PPI_CHG_CH9_Pos             
+#define PPI_CHG0_CH9_Msk        PPI_CHG_CH9_Msk             
+#define PPI_CHG0_CH9_Excluded   PPI_CHG_CH9_Excluded        
+#define PPI_CHG0_CH9_Included   PPI_CHG_CH9_Included        
+#define PPI_CHG0_CH8_Pos        PPI_CHG_CH8_Pos             
+#define PPI_CHG0_CH8_Msk        PPI_CHG_CH8_Msk             
+#define PPI_CHG0_CH8_Excluded   PPI_CHG_CH8_Excluded        
+#define PPI_CHG0_CH8_Included   PPI_CHG_CH8_Included        
+#define PPI_CHG0_CH7_Pos        PPI_CHG_CH7_Pos             
+#define PPI_CHG0_CH7_Msk        PPI_CHG_CH7_Msk             
+#define PPI_CHG0_CH7_Excluded   PPI_CHG_CH7_Excluded        
+#define PPI_CHG0_CH7_Included   PPI_CHG_CH7_Included        
+#define PPI_CHG0_CH6_Pos        PPI_CHG_CH6_Pos             
+#define PPI_CHG0_CH6_Msk        PPI_CHG_CH6_Msk             
+#define PPI_CHG0_CH6_Excluded   PPI_CHG_CH6_Excluded        
+#define PPI_CHG0_CH6_Included   PPI_CHG_CH6_Included        
+#define PPI_CHG0_CH5_Pos        PPI_CHG_CH5_Pos             
+#define PPI_CHG0_CH5_Msk        PPI_CHG_CH5_Msk             
+#define PPI_CHG0_CH5_Excluded   PPI_CHG_CH5_Excluded       
+#define PPI_CHG0_CH5_Included   PPI_CHG_CH5_Included        
+#define PPI_CHG0_CH4_Pos        PPI_CHG_CH4_Pos             
+#define PPI_CHG0_CH4_Msk        PPI_CHG_CH4_Msk             
+#define PPI_CHG0_CH4_Excluded   PPI_CHG_CH4_Excluded       
+#define PPI_CHG0_CH4_Included   PPI_CHG_CH4_Included       
+#define PPI_CHG0_CH3_Pos        PPI_CHG_CH3_Pos             
+#define PPI_CHG0_CH3_Msk        PPI_CHG_CH3_Msk            
+#define PPI_CHG0_CH3_Excluded   PPI_CHG_CH3_Excluded        
+#define PPI_CHG0_CH3_Included   PPI_CHG_CH3_Included       
+#define PPI_CHG0_CH2_Pos        PPI_CHG_CH2_Pos            
+#define PPI_CHG0_CH2_Msk        PPI_CHG_CH2_Msk             
+#define PPI_CHG0_CH2_Excluded   PPI_CHG_CH2_Excluded       
+#define PPI_CHG0_CH2_Included   PPI_CHG_CH2_Included       
+#define PPI_CHG0_CH1_Pos        PPI_CHG_CH1_Pos            
+#define PPI_CHG0_CH1_Msk        PPI_CHG_CH1_Msk            
+#define PPI_CHG0_CH1_Excluded   PPI_CHG_CH1_Excluded        
+#define PPI_CHG0_CH1_Included   PPI_CHG_CH1_Included       
+#define PPI_CHG0_CH0_Pos        PPI_CHG_CH0_Pos            
+#define PPI_CHG0_CH0_Msk        PPI_CHG_CH0_Msk            
+#define PPI_CHG0_CH0_Excluded   PPI_CHG_CH0_Excluded        
+#define PPI_CHG0_CH0_Included   PPI_CHG_CH0_Included       
+#define PPI_CHG1_CH15_Pos       PPI_CHG_CH15_Pos           
+#define PPI_CHG1_CH15_Msk       PPI_CHG_CH15_Msk           
+#define PPI_CHG1_CH15_Excluded  PPI_CHG_CH15_Excluded       
+#define PPI_CHG1_CH15_Included  PPI_CHG_CH15_Included      
+#define PPI_CHG1_CH14_Pos       PPI_CHG_CH14_Pos           
+#define PPI_CHG1_CH14_Msk       PPI_CHG_CH14_Msk            
+#define PPI_CHG1_CH14_Excluded  PPI_CHG_CH14_Excluded      
+#define PPI_CHG1_CH14_Included  PPI_CHG_CH14_Included       
+#define PPI_CHG1_CH13_Pos       PPI_CHG_CH13_Pos           
+#define PPI_CHG1_CH13_Msk       PPI_CHG_CH13_Msk            
+#define PPI_CHG1_CH13_Excluded  PPI_CHG_CH13_Excluded      
+#define PPI_CHG1_CH13_Included  PPI_CHG_CH13_Included      
+#define PPI_CHG1_CH12_Pos       PPI_CHG_CH12_Pos            
+#define PPI_CHG1_CH12_Msk       PPI_CHG_CH12_Msk           
+#define PPI_CHG1_CH12_Excluded  PPI_CHG_CH12_Excluded      
+#define PPI_CHG1_CH12_Included  PPI_CHG_CH12_Included      
+#define PPI_CHG1_CH11_Pos       PPI_CHG_CH11_Pos            
+#define PPI_CHG1_CH11_Msk       PPI_CHG_CH11_Msk           
+#define PPI_CHG1_CH11_Excluded  PPI_CHG_CH11_Excluded      
+#define PPI_CHG1_CH11_Included  PPI_CHG_CH11_Included      
+#define PPI_CHG1_CH10_Pos       PPI_CHG_CH10_Pos           
+#define PPI_CHG1_CH10_Msk       PPI_CHG_CH10_Msk            
+#define PPI_CHG1_CH10_Excluded  PPI_CHG_CH10_Excluded      
+#define PPI_CHG1_CH10_Included  PPI_CHG_CH10_Included      
+#define PPI_CHG1_CH9_Pos        PPI_CHG_CH9_Pos            
+#define PPI_CHG1_CH9_Msk        PPI_CHG_CH9_Msk            
+#define PPI_CHG1_CH9_Excluded   PPI_CHG_CH9_Excluded       
+#define PPI_CHG1_CH9_Included   PPI_CHG_CH9_Included       
+#define PPI_CHG1_CH8_Pos        PPI_CHG_CH8_Pos            
+#define PPI_CHG1_CH8_Msk        PPI_CHG_CH8_Msk            
+#define PPI_CHG1_CH8_Excluded   PPI_CHG_CH8_Excluded       
+#define PPI_CHG1_CH8_Included   PPI_CHG_CH8_Included       
+#define PPI_CHG1_CH7_Pos        PPI_CHG_CH7_Pos             
+#define PPI_CHG1_CH7_Msk        PPI_CHG_CH7_Msk            
+#define PPI_CHG1_CH7_Excluded   PPI_CHG_CH7_Excluded        
+#define PPI_CHG1_CH7_Included   PPI_CHG_CH7_Included       
+#define PPI_CHG1_CH6_Pos        PPI_CHG_CH6_Pos             
+#define PPI_CHG1_CH6_Msk        PPI_CHG_CH6_Msk            
+#define PPI_CHG1_CH6_Excluded   PPI_CHG_CH6_Excluded       
+#define PPI_CHG1_CH6_Included   PPI_CHG_CH6_Included       
+#define PPI_CHG1_CH5_Pos        PPI_CHG_CH5_Pos             
+#define PPI_CHG1_CH5_Msk        PPI_CHG_CH5_Msk             
+#define PPI_CHG1_CH5_Excluded   PPI_CHG_CH5_Excluded       
+#define PPI_CHG1_CH5_Included   PPI_CHG_CH5_Included        
+#define PPI_CHG1_CH4_Pos        PPI_CHG_CH4_Pos             
+#define PPI_CHG1_CH4_Msk        PPI_CHG_CH4_Msk             
+#define PPI_CHG1_CH4_Excluded   PPI_CHG_CH4_Excluded        
+#define PPI_CHG1_CH4_Included   PPI_CHG_CH4_Included        
+#define PPI_CHG1_CH3_Pos        PPI_CHG_CH3_Pos            
+#define PPI_CHG1_CH3_Msk        PPI_CHG_CH3_Msk             
+#define PPI_CHG1_CH3_Excluded   PPI_CHG_CH3_Excluded        
+#define PPI_CHG1_CH3_Included   PPI_CHG_CH3_Included       
+#define PPI_CHG1_CH2_Pos        PPI_CHG_CH2_Pos            
+#define PPI_CHG1_CH2_Msk        PPI_CHG_CH2_Msk             
+#define PPI_CHG1_CH2_Excluded   PPI_CHG_CH2_Excluded        
+#define PPI_CHG1_CH2_Included   PPI_CHG_CH2_Included        
+#define PPI_CHG1_CH1_Pos        PPI_CHG_CH1_Pos             
+#define PPI_CHG1_CH1_Msk        PPI_CHG_CH1_Msk            
+#define PPI_CHG1_CH1_Excluded   PPI_CHG_CH1_Excluded        
+#define PPI_CHG1_CH1_Included   PPI_CHG_CH1_Included       
+#define PPI_CHG1_CH0_Pos        PPI_CHG_CH0_Pos             
+#define PPI_CHG1_CH0_Msk        PPI_CHG_CH0_Msk            
+#define PPI_CHG1_CH0_Excluded   PPI_CHG_CH0_Excluded       
+#define PPI_CHG1_CH0_Included   PPI_CHG_CH0_Included       
+#define PPI_CHG2_CH15_Pos       PPI_CHG_CH15_Pos           
+#define PPI_CHG2_CH15_Msk       PPI_CHG_CH15_Msk            
+#define PPI_CHG2_CH15_Excluded  PPI_CHG_CH15_Excluded      
+#define PPI_CHG2_CH15_Included  PPI_CHG_CH15_Included      
+#define PPI_CHG2_CH14_Pos       PPI_CHG_CH14_Pos           
+#define PPI_CHG2_CH14_Msk       PPI_CHG_CH14_Msk           
+#define PPI_CHG2_CH14_Excluded  PPI_CHG_CH14_Excluded       
+#define PPI_CHG2_CH14_Included  PPI_CHG_CH14_Included      
+#define PPI_CHG2_CH13_Pos       PPI_CHG_CH13_Pos           
+#define PPI_CHG2_CH13_Msk       PPI_CHG_CH13_Msk            
+#define PPI_CHG2_CH13_Excluded  PPI_CHG_CH13_Excluded       
+#define PPI_CHG2_CH13_Included  PPI_CHG_CH13_Included      
+#define PPI_CHG2_CH12_Pos       PPI_CHG_CH12_Pos            
+#define PPI_CHG2_CH12_Msk       PPI_CHG_CH12_Msk            
+#define PPI_CHG2_CH12_Excluded  PPI_CHG_CH12_Excluded      
+#define PPI_CHG2_CH12_Included  PPI_CHG_CH12_Included       
+#define PPI_CHG2_CH11_Pos       PPI_CHG_CH11_Pos           
+#define PPI_CHG2_CH11_Msk       PPI_CHG_CH11_Msk           
+#define PPI_CHG2_CH11_Excluded  PPI_CHG_CH11_Excluded       
+#define PPI_CHG2_CH11_Included  PPI_CHG_CH11_Included       
+#define PPI_CHG2_CH10_Pos       PPI_CHG_CH10_Pos            
+#define PPI_CHG2_CH10_Msk       PPI_CHG_CH10_Msk            
+#define PPI_CHG2_CH10_Excluded  PPI_CHG_CH10_Excluded      
+#define PPI_CHG2_CH10_Included  PPI_CHG_CH10_Included      
+#define PPI_CHG2_CH9_Pos        PPI_CHG_CH9_Pos            
+#define PPI_CHG2_CH9_Msk        PPI_CHG_CH9_Msk            
+#define PPI_CHG2_CH9_Excluded   PPI_CHG_CH9_Excluded        
+#define PPI_CHG2_CH9_Included   PPI_CHG_CH9_Included       
+#define PPI_CHG2_CH8_Pos        PPI_CHG_CH8_Pos            
+#define PPI_CHG2_CH8_Msk        PPI_CHG_CH8_Msk            
+#define PPI_CHG2_CH8_Excluded   PPI_CHG_CH8_Excluded       
+#define PPI_CHG2_CH8_Included   PPI_CHG_CH8_Included        
+#define PPI_CHG2_CH7_Pos        PPI_CHG_CH7_Pos            
+#define PPI_CHG2_CH7_Msk        PPI_CHG_CH7_Msk            
+#define PPI_CHG2_CH7_Excluded   PPI_CHG_CH7_Excluded       
+#define PPI_CHG2_CH7_Included   PPI_CHG_CH7_Included       
+#define PPI_CHG2_CH6_Pos        PPI_CHG_CH6_Pos            
+#define PPI_CHG2_CH6_Msk        PPI_CHG_CH6_Msk            
+#define PPI_CHG2_CH6_Excluded   PPI_CHG_CH6_Excluded       
+#define PPI_CHG2_CH6_Included   PPI_CHG_CH6_Included       
+#define PPI_CHG2_CH5_Pos        PPI_CHG_CH5_Pos            
+#define PPI_CHG2_CH5_Msk        PPI_CHG_CH5_Msk            
+#define PPI_CHG2_CH5_Excluded   PPI_CHG_CH5_Excluded       
+#define PPI_CHG2_CH5_Included   PPI_CHG_CH5_Included        
+#define PPI_CHG2_CH4_Pos        PPI_CHG_CH4_Pos             
+#define PPI_CHG2_CH4_Msk        PPI_CHG_CH4_Msk             
+#define PPI_CHG2_CH4_Excluded   PPI_CHG_CH4_Excluded        
+#define PPI_CHG2_CH4_Included   PPI_CHG_CH4_Included       
+#define PPI_CHG2_CH3_Pos        PPI_CHG_CH3_Pos            
+#define PPI_CHG2_CH3_Msk        PPI_CHG_CH3_Msk            
+#define PPI_CHG2_CH3_Excluded   PPI_CHG_CH3_Excluded       
+#define PPI_CHG2_CH3_Included   PPI_CHG_CH3_Included       
+#define PPI_CHG2_CH2_Pos        PPI_CHG_CH2_Pos            
+#define PPI_CHG2_CH2_Msk        PPI_CHG_CH2_Msk           
+#define PPI_CHG2_CH2_Excluded   PPI_CHG_CH2_Excluded       
+#define PPI_CHG2_CH2_Included   PPI_CHG_CH2_Included       
+#define PPI_CHG2_CH1_Pos        PPI_CHG_CH1_Pos             
+#define PPI_CHG2_CH1_Msk        PPI_CHG_CH1_Msk             
+#define PPI_CHG2_CH1_Excluded   PPI_CHG_CH1_Excluded       
+#define PPI_CHG2_CH1_Included   PPI_CHG_CH1_Included       
+#define PPI_CHG2_CH0_Pos        PPI_CHG_CH0_Pos            
+#define PPI_CHG2_CH0_Msk        PPI_CHG_CH0_Msk            
+#define PPI_CHG2_CH0_Excluded   PPI_CHG_CH0_Excluded       
+#define PPI_CHG2_CH0_Included   PPI_CHG_CH0_Included        
+#define PPI_CHG3_CH15_Pos       PPI_CHG_CH15_Pos           
+#define PPI_CHG3_CH15_Msk       PPI_CHG_CH15_Msk           
+#define PPI_CHG3_CH15_Excluded  PPI_CHG_CH15_Excluded     
+#define PPI_CHG3_CH15_Included  PPI_CHG_CH15_Included      
+#define PPI_CHG3_CH14_Pos       PPI_CHG_CH14_Pos          
+#define PPI_CHG3_CH14_Msk       PPI_CHG_CH14_Msk           
+#define PPI_CHG3_CH14_Excluded  PPI_CHG_CH14_Excluded      
+#define PPI_CHG3_CH14_Included  PPI_CHG_CH14_Included       
+#define PPI_CHG3_CH13_Pos       PPI_CHG_CH13_Pos           
+#define PPI_CHG3_CH13_Msk       PPI_CHG_CH13_Msk            
+#define PPI_CHG3_CH13_Excluded  PPI_CHG_CH13_Excluded      
+#define PPI_CHG3_CH13_Included  PPI_CHG_CH13_Included      
+#define PPI_CHG3_CH12_Pos       PPI_CHG_CH12_Pos            
+#define PPI_CHG3_CH12_Msk       PPI_CHG_CH12_Msk            
+#define PPI_CHG3_CH12_Excluded  PPI_CHG_CH12_Excluded       
+#define PPI_CHG3_CH12_Included  PPI_CHG_CH12_Included       
+#define PPI_CHG3_CH11_Pos       PPI_CHG_CH11_Pos            
+#define PPI_CHG3_CH11_Msk       PPI_CHG_CH11_Msk            
+#define PPI_CHG3_CH11_Excluded  PPI_CHG_CH11_Excluded      
+#define PPI_CHG3_CH11_Included  PPI_CHG_CH11_Included       
+#define PPI_CHG3_CH10_Pos       PPI_CHG_CH10_Pos            
+#define PPI_CHG3_CH10_Msk       PPI_CHG_CH10_Msk            
+#define PPI_CHG3_CH10_Excluded  PPI_CHG_CH10_Excluded      
+#define PPI_CHG3_CH10_Included  PPI_CHG_CH10_Included      
+#define PPI_CHG3_CH9_Pos        PPI_CHG_CH9_Pos            
+#define PPI_CHG3_CH9_Msk        PPI_CHG_CH9_Msk            
+#define PPI_CHG3_CH9_Excluded   PPI_CHG_CH9_Excluded       
+#define PPI_CHG3_CH9_Included   PPI_CHG_CH9_Included       
+#define PPI_CHG3_CH8_Pos        PPI_CHG_CH8_Pos            
+#define PPI_CHG3_CH8_Msk        PPI_CHG_CH8_Msk             
+#define PPI_CHG3_CH8_Excluded   PPI_CHG_CH8_Excluded       
+#define PPI_CHG3_CH8_Included   PPI_CHG_CH8_Included       
+#define PPI_CHG3_CH7_Pos        PPI_CHG_CH7_Pos             
+#define PPI_CHG3_CH7_Msk        PPI_CHG_CH7_Msk            
+#define PPI_CHG3_CH7_Excluded   PPI_CHG_CH7_Excluded        
+#define PPI_CHG3_CH7_Included   PPI_CHG_CH7_Included       
+#define PPI_CHG3_CH6_Pos        PPI_CHG_CH6_Pos             
+#define PPI_CHG3_CH6_Msk        PPI_CHG_CH6_Msk             
+#define PPI_CHG3_CH6_Excluded   PPI_CHG_CH6_Excluded       
+#define PPI_CHG3_CH6_Included   PPI_CHG_CH6_Included        
+#define PPI_CHG3_CH5_Pos        PPI_CHG_CH5_Pos             
+#define PPI_CHG3_CH5_Msk        PPI_CHG_CH5_Msk             
+#define PPI_CHG3_CH5_Excluded   PPI_CHG_CH5_Excluded        
+#define PPI_CHG3_CH5_Included   PPI_CHG_CH5_Included       
+#define PPI_CHG3_CH4_Pos        PPI_CHG_CH4_Pos             
+#define PPI_CHG3_CH4_Msk        PPI_CHG_CH4_Msk            
+#define PPI_CHG3_CH4_Excluded   PPI_CHG_CH4_Excluded        
+#define PPI_CHG3_CH4_Included   PPI_CHG_CH4_Included        
+#define PPI_CHG3_CH3_Pos        PPI_CHG_CH3_Pos             
+#define PPI_CHG3_CH3_Msk        PPI_CHG_CH3_Msk            
+#define PPI_CHG3_CH3_Excluded   PPI_CHG_CH3_Excluded        
+#define PPI_CHG3_CH3_Included   PPI_CHG_CH3_Included        
+#define PPI_CHG3_CH2_Pos        PPI_CHG_CH2_Pos             
+#define PPI_CHG3_CH2_Msk        PPI_CHG_CH2_Msk             
+#define PPI_CHG3_CH2_Excluded   PPI_CHG_CH2_Excluded        
+#define PPI_CHG3_CH2_Included   PPI_CHG_CH2_Included       
+#define PPI_CHG3_CH1_Pos        PPI_CHG_CH1_Pos             
+#define PPI_CHG3_CH1_Msk        PPI_CHG_CH1_Msk             
+#define PPI_CHG3_CH1_Excluded   PPI_CHG_CH1_Excluded        
+#define PPI_CHG3_CH1_Included   PPI_CHG_CH1_Included        
+#define PPI_CHG3_CH0_Pos        PPI_CHG_CH0_Pos             
+#define PPI_CHG3_CH0_Msk        PPI_CHG_CH0_Msk             
+#define PPI_CHG3_CH0_Excluded   PPI_CHG_CH0_Excluded        
+#define PPI_CHG3_CH0_Included   PPI_CHG_CH0_Included        
+
+
+
+/*lint --flb "Leave library region" */
+
+#endif /* NRF51_DEPRECATED_H */
+
diff --git a/ports/nrf/device/nrf51/startup_nrf51822.c b/ports/nrf/device/nrf51/startup_nrf51822.c
new file mode 100644
index 0000000000..add8218e6c
--- /dev/null
+++ b/ports/nrf/device/nrf51/startup_nrf51822.c
@@ -0,0 +1,151 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <stdint.h>
+
+extern uint32_t _estack;
+extern uint32_t _sidata;
+extern uint32_t _sdata;
+extern uint32_t _edata;
+extern uint32_t _sbss;
+extern uint32_t _ebss;
+
+typedef void (*func)(void);
+
+extern void  _start(void) __attribute__((noreturn));
+extern void SystemInit(void);
+
+void Default_Handler(void) {
+    while (1);
+}
+
+void Reset_Handler(void) {
+    uint32_t * ram_on_addr   = (uint32_t *)0x40000524;
+    uint32_t * ram_on_b_addr = (uint32_t *)0x40000554;
+    // RAM on in on-mode
+    *ram_on_addr   = 3; // block 0 and 1
+    *ram_on_b_addr = 3; // block 2 and 3
+#if 0 
+    // RAM on in off-mode 
+    ram_on_addr   = 1 << 16;
+    ram_on_b_addr = 1 << 17;
+#endif
+
+    uint32_t * p_src  = &_sidata;
+    uint32_t * p_dest = &_sdata;
+
+    while (p_dest < &_edata) {
+      *p_dest++ = *p_src++;
+    }
+
+    uint32_t * p_bss     = &_sbss;
+    uint32_t * p_bss_end = &_ebss;
+    while (p_bss < p_bss_end) {
+        *p_bss++ = 0ul;
+    }
+
+    SystemInit();
+    _start();
+}
+
+void NMI_Handler            (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler            (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler        (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void POWER_CLOCK_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void RADIO_IRQHandler       (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART0_IRQHandler       (void) __attribute__ ((weak, alias("Default_Handler")));
+void SPI0_TWI0_IRQHandler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void SPI1_TWI1_IRQHandler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void GPIOTE_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void ADC_IRQHandler         (void) __attribute__ ((weak, alias("Default_Handler")));
+void TIMER0_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void TIMER1_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void TIMER2_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void RTC0_IRQHandler        (void) __attribute__ ((weak, alias("Default_Handler")));
+void TEMP_IRQHandler        (void) __attribute__ ((weak, alias("Default_Handler")));
+void RNG_IRQHandler         (void) __attribute__ ((weak, alias("Default_Handler")));
+void ECB_IRQHandler         (void) __attribute__ ((weak, alias("Default_Handler")));
+void CCM_AAR_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void WDT_IRQHandler         (void) __attribute__ ((weak, alias("Default_Handler")));
+void RTC1_IRQHandler        (void) __attribute__ ((weak, alias("Default_Handler")));
+void QDEC_IRQHandler        (void) __attribute__ ((weak, alias("Default_Handler")));
+void LPCOMP_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void SWI0_IRQHandler        (void) __attribute__ ((weak, alias("Default_Handler")));
+void SWI1_IRQHandler        (void) __attribute__ ((weak, alias("Default_Handler")));
+void SWI2_IRQHandler        (void) __attribute__ ((weak, alias("Default_Handler")));
+void SWI3_IRQHandler        (void) __attribute__ ((weak, alias("Default_Handler")));
+void SWI4_IRQHandler        (void) __attribute__ ((weak, alias("Default_Handler")));
+void SWI5_IRQHandler        (void) __attribute__ ((weak, alias("Default_Handler")));
+
+const func __Vectors[] __attribute__ ((section(".isr_vector"))) = {
+    (func)&_estack,
+    Reset_Handler,
+    NMI_Handler,
+    HardFault_Handler,
+    0,
+    0,
+    0,
+    0,
+    0,
+    0,
+    0,
+    SVC_Handler,
+    0,
+    0,
+    PendSV_Handler,
+    SysTick_Handler,
+
+    /* External Interrupts */
+    POWER_CLOCK_IRQHandler,
+    RADIO_IRQHandler,
+    UART0_IRQHandler,
+    SPI0_TWI0_IRQHandler,
+    SPI1_TWI1_IRQHandler,
+    0,
+    GPIOTE_IRQHandler,
+    ADC_IRQHandler,
+    TIMER0_IRQHandler,
+    TIMER1_IRQHandler,
+    TIMER2_IRQHandler,
+    RTC0_IRQHandler,
+    TEMP_IRQHandler,
+    RNG_IRQHandler,
+    ECB_IRQHandler,
+    CCM_AAR_IRQHandler,
+    WDT_IRQHandler,
+    RTC1_IRQHandler,
+    QDEC_IRQHandler,
+    LPCOMP_IRQHandler,
+    SWI0_IRQHandler,
+    SWI1_IRQHandler,
+    SWI2_IRQHandler,
+    SWI3_IRQHandler,
+    SWI4_IRQHandler,
+    SWI5_IRQHandler
+};
diff --git a/ports/nrf/device/nrf51/system_nrf51.h b/ports/nrf/device/nrf51/system_nrf51.h
new file mode 100644
index 0000000000..71c403962e
--- /dev/null
+++ b/ports/nrf/device/nrf51/system_nrf51.h
@@ -0,0 +1,69 @@
+/* Copyright (c) 2012 ARM LIMITED
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *   * Redistributions of source code must retain the above copyright notice, this
+ *     list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *
+ *   * Neither the name of ARM nor the names of its contributors may be used to
+ *     endorse or promote products derived from this software without specific
+ *     prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+ 
+#ifndef SYSTEM_NRF51_H
+#define SYSTEM_NRF51_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+
+extern uint32_t SystemCoreClock;    /*!< System Clock Frequency (Core Clock)  */
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock 
+ *         retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_NRF51_H */
diff --git a/ports/nrf/device/nrf51/system_nrf51822.c b/ports/nrf/device/nrf51/system_nrf51822.c
new file mode 100644
index 0000000000..0ad09d5ff7
--- /dev/null
+++ b/ports/nrf/device/nrf51/system_nrf51822.c
@@ -0,0 +1,151 @@
+/* Copyright (c) 2012 ARM LIMITED
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *   * Redistributions of source code must retain the above copyright notice, this
+ *     list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *
+ *   * Neither the name of ARM nor the names of its contributors may be used to
+ *     endorse or promote products derived from this software without specific
+ *     prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+ 
+/* NOTE: Template files (including this one) are application specific and therefore expected to
+   be copied into the application project folder prior to its use! */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "nrf.h"
+#include "system_nrf51.h"
+
+/*lint ++flb "Enter library region" */
+
+
+#define __SYSTEM_CLOCK      (16000000UL)     /*!< nRF51 devices use a fixed System Clock Frequency of 16MHz */
+
+static bool is_manual_peripheral_setup_needed(void);
+static bool is_disabled_in_debug_needed(void);
+static bool is_peripheral_domain_setup_needed(void);
+
+
+#if defined ( __CC_ARM )
+    uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK;
+#elif defined ( __ICCARM__ )
+    __root uint32_t SystemCoreClock = __SYSTEM_CLOCK;
+#elif defined   ( __GNUC__ )
+    uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK;
+#endif
+
+void SystemCoreClockUpdate(void)
+{
+    SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+void SystemInit(void)
+{
+    /* If desired, switch off the unused RAM to lower consumption by the use of RAMON register.
+       It can also be done in the application main() function. */
+
+    /* Prepare the peripherals for use as indicated by the PAN 26 "System: Manual setup is required
+       to enable the use of peripherals" found at Product Anomaly document for your device found at
+       https://www.nordicsemi.com/. The side effect of executing these instructions in the devices
+       that do not need it is that the new peripherals in the second generation devices (LPCOMP for
+       example) will not be available. */
+    if (is_manual_peripheral_setup_needed())
+    {
+        *(uint32_t volatile *)0x40000504 = 0xC007FFDF;
+        *(uint32_t volatile *)0x40006C18 = 0x00008000;
+    }
+
+    /* Disable PROTENSET registers under debug, as indicated by PAN 59 "MPU: Reset value of DISABLEINDEBUG
+       register is incorrect" found at Product Anomaly document for your device found at
+       https://www.nordicsemi.com/. There is no side effect of using these instruction if not needed. */
+    if (is_disabled_in_debug_needed())
+    {
+        NRF_MPU->DISABLEINDEBUG = MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos;
+    }
+
+    /* Execute the following code to eliminate excessive current in sleep mode with RAM retention in nRF51802 devices,
+       as indicated by PAN 76 "System: Excessive current in sleep mode with retention" found at Product Anomaly document
+       for your device found at https://www.nordicsemi.com/. */
+    if (is_peripheral_domain_setup_needed()){
+        if (*(uint32_t volatile *)0x4006EC00 != 1){
+            *(uint32_t volatile *)0x4006EC00 = 0x9375;
+            while (*(uint32_t volatile *)0x4006EC00 != 1){
+            }
+        }
+        *(uint32_t volatile *)0x4006EC14 = 0xC0;
+    }
+}
+
+
+static bool is_manual_peripheral_setup_needed(void)
+{
+    if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
+    {
+        if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x00) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
+        {
+            return true;
+        }
+        if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x10) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
+        {
+            return true;
+        }
+        if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
+        {
+            return true;
+        }
+    }
+
+    return false;
+}
+
+static bool is_disabled_in_debug_needed(void)
+{
+    if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
+    {
+        if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
+        {
+            return true;
+        }
+    }
+
+    return false;
+}
+
+static bool is_peripheral_domain_setup_needed(void)
+{
+    if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
+    {
+        if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0xA0) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
+        {
+            return true;
+        }
+        if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0xD0) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
+        {
+            return true;
+        }
+    }
+
+    return false;
+}
+
+/*lint --flb "Leave library region" */
diff --git a/ports/nrf/device/nrf52/nrf51_to_nrf52.h b/ports/nrf/device/nrf52/nrf51_to_nrf52.h
new file mode 100644
index 0000000000..72dfd91fc0
--- /dev/null
+++ b/ports/nrf/device/nrf52/nrf51_to_nrf52.h
@@ -0,0 +1,952 @@
+/* Copyright (c) 2016, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *   * Redistributions of source code must retain the above copyright notice, this
+ *     list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *
+ *   * Neither the name of Nordic Semiconductor ASA nor the names of its
+ *     contributors may be used to endorse or promote products derived from
+ *     this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+ 
+#ifndef NRF51_TO_NRF52_H
+#define NRF51_TO_NRF52_H
+
+/*lint ++flb "Enter library region */
+
+/* This file is given to prevent your SW from not compiling with the name changes between nRF51 and nRF52 devices.
+ * It redefines the old nRF51 names into the new ones as long as the functionality is still supported. If the
+ * functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros
+ * from the nrf51_deprecated.h file. */
+
+
+/* IRQ */
+/* Several peripherals have been added to several indexes. Names of IRQ handlers and IRQ numbers have changed. */
+#define UART0_IRQHandler        UARTE0_UART0_IRQHandler
+#define SPI0_TWI0_IRQHandler    SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+#define SPI1_TWI1_IRQHandler    SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+#define ADC_IRQHandler          SAADC_IRQHandler
+#define LPCOMP_IRQHandler       COMP_LPCOMP_IRQHandler
+#define SWI0_IRQHandler         SWI0_EGU0_IRQHandler
+#define SWI1_IRQHandler         SWI1_EGU1_IRQHandler
+#define SWI2_IRQHandler         SWI2_EGU2_IRQHandler
+#define SWI3_IRQHandler         SWI3_EGU3_IRQHandler
+#define SWI4_IRQHandler         SWI4_EGU4_IRQHandler
+#define SWI5_IRQHandler         SWI5_EGU5_IRQHandler
+
+#define UART0_IRQn              UARTE0_UART0_IRQn
+#define SPI0_TWI0_IRQn          SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn
+#define SPI1_TWI1_IRQn          SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn
+#define ADC_IRQn                SAADC_IRQn
+#define LPCOMP_IRQn             COMP_LPCOMP_IRQn
+#define SWI0_IRQn               SWI0_EGU0_IRQn
+#define SWI1_IRQn               SWI1_EGU1_IRQn
+#define SWI2_IRQn               SWI2_EGU2_IRQn
+#define SWI3_IRQn               SWI3_EGU3_IRQn
+#define SWI4_IRQn               SWI4_EGU4_IRQn
+#define SWI5_IRQn               SWI5_EGU5_IRQn
+
+
+/* UICR */
+/* Register RBPCONF was renamed to APPROTECT. */
+#define RBPCONF     APPROTECT
+
+#define UICR_RBPCONF_PALL_Pos           UICR_APPROTECT_PALL_Pos
+#define UICR_RBPCONF_PALL_Msk           UICR_APPROTECT_PALL_Msk
+#define UICR_RBPCONF_PALL_Enabled       UICR_APPROTECT_PALL_Enabled
+#define UICR_RBPCONF_PALL_Disabled      UICR_APPROTECT_PALL_Disabled
+
+
+/* GPIO */
+/* GPIO port was renamed to P0. */
+#define NRF_GPIO        NRF_P0
+#define NRF_GPIO_BASE   NRF_P0_BASE
+
+
+/* QDEC */
+/* The registers PSELA, PSELB and PSELLED were restructured into a struct. */
+#define PSELLED     PSEL.LED
+#define PSELA       PSEL.A
+#define PSELB       PSEL.B
+
+
+/* SPIS */
+/* The registers PSELSCK, PSELMISO, PSELMOSI, PSELCSN were restructured into a struct. */
+#define PSELSCK       PSEL.SCK
+#define PSELMISO      PSEL.MISO
+#define PSELMOSI      PSEL.MOSI
+#define PSELCSN       PSEL.CSN
+
+/* The registers RXDPTR, MAXRX, AMOUNTRX were restructured into a struct */
+#define RXDPTR        RXD.PTR
+#define MAXRX         RXD.MAXCNT
+#define AMOUNTRX      RXD.AMOUNT
+
+#define SPIS_MAXRX_MAXRX_Pos        SPIS_RXD_MAXCNT_MAXCNT_Pos
+#define SPIS_MAXRX_MAXRX_Msk        SPIS_RXD_MAXCNT_MAXCNT_Msk
+
+#define SPIS_AMOUNTRX_AMOUNTRX_Pos  SPIS_RXD_AMOUNT_AMOUNT_Pos
+#define SPIS_AMOUNTRX_AMOUNTRX_Msk  SPIS_RXD_AMOUNT_AMOUNT_Msk
+
+/* The registers TXDPTR, MAXTX, AMOUNTTX were restructured into a struct */
+#define TXDPTR        TXD.PTR
+#define MAXTX         TXD.MAXCNT
+#define AMOUNTTX      TXD.AMOUNT
+
+#define SPIS_MAXTX_MAXTX_Pos        SPIS_TXD_MAXCNT_MAXCNT_Pos
+#define SPIS_MAXTX_MAXTX_Msk        SPIS_TXD_MAXCNT_MAXCNT_Msk
+
+#define SPIS_AMOUNTTX_AMOUNTTX_Pos  SPIS_TXD_AMOUNT_AMOUNT_Pos
+#define SPIS_AMOUNTTX_AMOUNTTX_Msk  SPIS_TXD_AMOUNT_AMOUNT_Msk
+
+
+/* MPU */
+/* Part of MPU module was renamed BPROT, while the rest was eliminated. */
+#define NRF_MPU     NRF_BPROT
+
+/* Register DISABLEINDEBUG macros were affected. */
+#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos       BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos
+#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk       BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk
+#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled   BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled
+#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled  BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled
+
+/* Registers PROTENSET0 and PROTENSET1 were affected and renamed as CONFIG0 and CONFIG1. */
+#define PROTENSET0  CONFIG0
+#define PROTENSET1  CONFIG1
+
+#define MPU_PROTENSET1_PROTREG63_Pos        BPROT_CONFIG1_REGION63_Pos
+#define MPU_PROTENSET1_PROTREG63_Msk        BPROT_CONFIG1_REGION63_Msk
+#define MPU_PROTENSET1_PROTREG63_Disabled   BPROT_CONFIG1_REGION63_Disabled
+#define MPU_PROTENSET1_PROTREG63_Enabled    BPROT_CONFIG1_REGION63_Enabled
+#define MPU_PROTENSET1_PROTREG63_Set        BPROT_CONFIG1_REGION63_Enabled
+
+#define MPU_PROTENSET1_PROTREG62_Pos        BPROT_CONFIG1_REGION62_Pos
+#define MPU_PROTENSET1_PROTREG62_Msk        BPROT_CONFIG1_REGION62_Msk
+#define MPU_PROTENSET1_PROTREG62_Disabled   BPROT_CONFIG1_REGION62_Disabled
+#define MPU_PROTENSET1_PROTREG62_Enabled    BPROT_CONFIG1_REGION62_Enabled
+#define MPU_PROTENSET1_PROTREG62_Set        BPROT_CONFIG1_REGION62_Enabled
+
+#define MPU_PROTENSET1_PROTREG61_Pos        BPROT_CONFIG1_REGION61_Pos
+#define MPU_PROTENSET1_PROTREG61_Msk        BPROT_CONFIG1_REGION61_Msk
+#define MPU_PROTENSET1_PROTREG61_Disabled   BPROT_CONFIG1_REGION61_Disabled
+#define MPU_PROTENSET1_PROTREG61_Enabled    BPROT_CONFIG1_REGION61_Enabled
+#define MPU_PROTENSET1_PROTREG61_Set        BPROT_CONFIG1_REGION61_Enabled
+
+#define MPU_PROTENSET1_PROTREG60_Pos        BPROT_CONFIG1_REGION60_Pos
+#define MPU_PROTENSET1_PROTREG60_Msk        BPROT_CONFIG1_REGION60_Msk
+#define MPU_PROTENSET1_PROTREG60_Disabled   BPROT_CONFIG1_REGION60_Disabled
+#define MPU_PROTENSET1_PROTREG60_Enabled    BPROT_CONFIG1_REGION60_Enabled
+#define MPU_PROTENSET1_PROTREG60_Set        BPROT_CONFIG1_REGION60_Enabled
+
+#define MPU_PROTENSET1_PROTREG59_Pos        BPROT_CONFIG1_REGION59_Pos
+#define MPU_PROTENSET1_PROTREG59_Msk        BPROT_CONFIG1_REGION59_Msk
+#define MPU_PROTENSET1_PROTREG59_Disabled   BPROT_CONFIG1_REGION59_Disabled
+#define MPU_PROTENSET1_PROTREG59_Enabled    BPROT_CONFIG1_REGION59_Enabled
+#define MPU_PROTENSET1_PROTREG59_Set        BPROT_CONFIG1_REGION59_Enabled
+
+#define MPU_PROTENSET1_PROTREG58_Pos        BPROT_CONFIG1_REGION58_Pos
+#define MPU_PROTENSET1_PROTREG58_Msk        BPROT_CONFIG1_REGION58_Msk
+#define MPU_PROTENSET1_PROTREG58_Disabled   BPROT_CONFIG1_REGION58_Disabled
+#define MPU_PROTENSET1_PROTREG58_Enabled    BPROT_CONFIG1_REGION58_Enabled
+#define MPU_PROTENSET1_PROTREG58_Set        BPROT_CONFIG1_REGION58_Enabled
+
+#define MPU_PROTENSET1_PROTREG57_Pos        BPROT_CONFIG1_REGION57_Pos
+#define MPU_PROTENSET1_PROTREG57_Msk        BPROT_CONFIG1_REGION57_Msk
+#define MPU_PROTENSET1_PROTREG57_Disabled   BPROT_CONFIG1_REGION57_Disabled
+#define MPU_PROTENSET1_PROTREG57_Enabled    BPROT_CONFIG1_REGION57_Enabled
+#define MPU_PROTENSET1_PROTREG57_Set        BPROT_CONFIG1_REGION57_Enabled
+
+#define MPU_PROTENSET1_PROTREG56_Pos        BPROT_CONFIG1_REGION56_Pos
+#define MPU_PROTENSET1_PROTREG56_Msk        BPROT_CONFIG1_REGION56_Msk
+#define MPU_PROTENSET1_PROTREG56_Disabled   BPROT_CONFIG1_REGION56_Disabled
+#define MPU_PROTENSET1_PROTREG56_Enabled    BPROT_CONFIG1_REGION56_Enabled
+#define MPU_PROTENSET1_PROTREG56_Set        BPROT_CONFIG1_REGION56_Enabled
+
+#define MPU_PROTENSET1_PROTREG55_Pos        BPROT_CONFIG1_REGION55_Pos
+#define MPU_PROTENSET1_PROTREG55_Msk        BPROT_CONFIG1_REGION55_Msk
+#define MPU_PROTENSET1_PROTREG55_Disabled   BPROT_CONFIG1_REGION55_Disabled
+#define MPU_PROTENSET1_PROTREG55_Enabled    BPROT_CONFIG1_REGION55_Enabled
+#define MPU_PROTENSET1_PROTREG55_Set        BPROT_CONFIG1_REGION55_Enabled
+
+#define MPU_PROTENSET1_PROTREG54_Pos        BPROT_CONFIG1_REGION54_Pos
+#define MPU_PROTENSET1_PROTREG54_Msk        BPROT_CONFIG1_REGION54_Msk
+#define MPU_PROTENSET1_PROTREG54_Disabled   BPROT_CONFIG1_REGION54_Disabled
+#define MPU_PROTENSET1_PROTREG54_Enabled    BPROT_CONFIG1_REGION54_Enabled
+#define MPU_PROTENSET1_PROTREG54_Set        BPROT_CONFIG1_REGION54_Enabled
+
+#define MPU_PROTENSET1_PROTREG53_Pos        BPROT_CONFIG1_REGION53_Pos
+#define MPU_PROTENSET1_PROTREG53_Msk        BPROT_CONFIG1_REGION53_Msk
+#define MPU_PROTENSET1_PROTREG53_Disabled   BPROT_CONFIG1_REGION53_Disabled
+#define MPU_PROTENSET1_PROTREG53_Enabled    BPROT_CONFIG1_REGION53_Enabled
+#define MPU_PROTENSET1_PROTREG53_Set        BPROT_CONFIG1_REGION53_Enabled
+
+#define MPU_PROTENSET1_PROTREG52_Pos        BPROT_CONFIG1_REGION52_Pos
+#define MPU_PROTENSET1_PROTREG52_Msk        BPROT_CONFIG1_REGION52_Msk
+#define MPU_PROTENSET1_PROTREG52_Disabled   BPROT_CONFIG1_REGION52_Disabled
+#define MPU_PROTENSET1_PROTREG52_Enabled    BPROT_CONFIG1_REGION52_Enabled
+#define MPU_PROTENSET1_PROTREG52_Set        BPROT_CONFIG1_REGION52_Enabled
+
+#define MPU_PROTENSET1_PROTREG51_Pos        BPROT_CONFIG1_REGION51_Pos
+#define MPU_PROTENSET1_PROTREG51_Msk        BPROT_CONFIG1_REGION51_Msk
+#define MPU_PROTENSET1_PROTREG51_Disabled   BPROT_CONFIG1_REGION51_Disabled
+#define MPU_PROTENSET1_PROTREG51_Enabled    BPROT_CONFIG1_REGION51_Enabled
+#define MPU_PROTENSET1_PROTREG51_Set        BPROT_CONFIG1_REGION51_Enabled
+
+#define MPU_PROTENSET1_PROTREG50_Pos        BPROT_CONFIG1_REGION50_Pos
+#define MPU_PROTENSET1_PROTREG50_Msk        BPROT_CONFIG1_REGION50_Msk
+#define MPU_PROTENSET1_PROTREG50_Disabled   BPROT_CONFIG1_REGION50_Disabled
+#define MPU_PROTENSET1_PROTREG50_Enabled    BPROT_CONFIG1_REGION50_Enabled
+#define MPU_PROTENSET1_PROTREG50_Set        BPROT_CONFIG1_REGION50_Enabled
+
+#define MPU_PROTENSET1_PROTREG49_Pos        BPROT_CONFIG1_REGION49_Pos
+#define MPU_PROTENSET1_PROTREG49_Msk        BPROT_CONFIG1_REGION49_Msk
+#define MPU_PROTENSET1_PROTREG49_Disabled   BPROT_CONFIG1_REGION49_Disabled
+#define MPU_PROTENSET1_PROTREG49_Enabled    BPROT_CONFIG1_REGION49_Enabled
+#define MPU_PROTENSET1_PROTREG49_Set        BPROT_CONFIG1_REGION49_Enabled
+
+#define MPU_PROTENSET1_PROTREG48_Pos        BPROT_CONFIG1_REGION48_Pos
+#define MPU_PROTENSET1_PROTREG48_Msk        BPROT_CONFIG1_REGION48_Msk
+#define MPU_PROTENSET1_PROTREG48_Disabled   BPROT_CONFIG1_REGION48_Disabled
+#define MPU_PROTENSET1_PROTREG48_Enabled    BPROT_CONFIG1_REGION48_Enabled
+#define MPU_PROTENSET1_PROTREG48_Set        BPROT_CONFIG1_REGION48_Enabled
+
+#define MPU_PROTENSET1_PROTREG47_Pos        BPROT_CONFIG1_REGION47_Pos
+#define MPU_PROTENSET1_PROTREG47_Msk        BPROT_CONFIG1_REGION47_Msk
+#define MPU_PROTENSET1_PROTREG47_Disabled   BPROT_CONFIG1_REGION47_Disabled
+#define MPU_PROTENSET1_PROTREG47_Enabled    BPROT_CONFIG1_REGION47_Enabled
+#define MPU_PROTENSET1_PROTREG47_Set        BPROT_CONFIG1_REGION47_Enabled
+
+#define MPU_PROTENSET1_PROTREG46_Pos        BPROT_CONFIG1_REGION46_Pos
+#define MPU_PROTENSET1_PROTREG46_Msk        BPROT_CONFIG1_REGION46_Msk
+#define MPU_PROTENSET1_PROTREG46_Disabled   BPROT_CONFIG1_REGION46_Disabled
+#define MPU_PROTENSET1_PROTREG46_Enabled    BPROT_CONFIG1_REGION46_Enabled
+#define MPU_PROTENSET1_PROTREG46_Set        BPROT_CONFIG1_REGION46_Enabled
+
+#define MPU_PROTENSET1_PROTREG45_Pos        BPROT_CONFIG1_REGION45_Pos
+#define MPU_PROTENSET1_PROTREG45_Msk        BPROT_CONFIG1_REGION45_Msk
+#define MPU_PROTENSET1_PROTREG45_Disabled   BPROT_CONFIG1_REGION45_Disabled
+#define MPU_PROTENSET1_PROTREG45_Enabled    BPROT_CONFIG1_REGION45_Enabled
+#define MPU_PROTENSET1_PROTREG45_Set        BPROT_CONFIG1_REGION45_Enabled
+
+#define MPU_PROTENSET1_PROTREG44_Pos        BPROT_CONFIG1_REGION44_Pos
+#define MPU_PROTENSET1_PROTREG44_Msk        BPROT_CONFIG1_REGION44_Msk
+#define MPU_PROTENSET1_PROTREG44_Disabled   BPROT_CONFIG1_REGION44_Disabled
+#define MPU_PROTENSET1_PROTREG44_Enabled    BPROT_CONFIG1_REGION44_Enabled
+#define MPU_PROTENSET1_PROTREG44_Set        BPROT_CONFIG1_REGION44_Enabled
+
+#define MPU_PROTENSET1_PROTREG43_Pos        BPROT_CONFIG1_REGION43_Pos
+#define MPU_PROTENSET1_PROTREG43_Msk        BPROT_CONFIG1_REGION43_Msk
+#define MPU_PROTENSET1_PROTREG43_Disabled   BPROT_CONFIG1_REGION43_Disabled
+#define MPU_PROTENSET1_PROTREG43_Enabled    BPROT_CONFIG1_REGION43_Enabled
+#define MPU_PROTENSET1_PROTREG43_Set        BPROT_CONFIG1_REGION43_Enabled
+
+#define MPU_PROTENSET1_PROTREG42_Pos        BPROT_CONFIG1_REGION42_Pos
+#define MPU_PROTENSET1_PROTREG42_Msk        BPROT_CONFIG1_REGION42_Msk
+#define MPU_PROTENSET1_PROTREG42_Disabled   BPROT_CONFIG1_REGION42_Disabled
+#define MPU_PROTENSET1_PROTREG42_Enabled    BPROT_CONFIG1_REGION42_Enabled
+#define MPU_PROTENSET1_PROTREG42_Set        BPROT_CONFIG1_REGION42_Enabled
+
+#define MPU_PROTENSET1_PROTREG41_Pos        BPROT_CONFIG1_REGION41_Pos
+#define MPU_PROTENSET1_PROTREG41_Msk        BPROT_CONFIG1_REGION41_Msk
+#define MPU_PROTENSET1_PROTREG41_Disabled   BPROT_CONFIG1_REGION41_Disabled
+#define MPU_PROTENSET1_PROTREG41_Enabled    BPROT_CONFIG1_REGION41_Enabled
+#define MPU_PROTENSET1_PROTREG41_Set        BPROT_CONFIG1_REGION41_Enabled
+
+#define MPU_PROTENSET1_PROTREG40_Pos        BPROT_CONFIG1_REGION40_Pos
+#define MPU_PROTENSET1_PROTREG40_Msk        BPROT_CONFIG1_REGION40_Msk
+#define MPU_PROTENSET1_PROTREG40_Disabled   BPROT_CONFIG1_REGION40_Disabled
+#define MPU_PROTENSET1_PROTREG40_Enabled    BPROT_CONFIG1_REGION40_Enabled
+#define MPU_PROTENSET1_PROTREG40_Set        BPROT_CONFIG1_REGION40_Enabled
+
+#define MPU_PROTENSET1_PROTREG39_Pos        BPROT_CONFIG1_REGION39_Pos
+#define MPU_PROTENSET1_PROTREG39_Msk        BPROT_CONFIG1_REGION39_Msk
+#define MPU_PROTENSET1_PROTREG39_Disabled   BPROT_CONFIG1_REGION39_Disabled
+#define MPU_PROTENSET1_PROTREG39_Enabled    BPROT_CONFIG1_REGION39_Enabled
+#define MPU_PROTENSET1_PROTREG39_Set        BPROT_CONFIG1_REGION39_Enabled
+
+#define MPU_PROTENSET1_PROTREG38_Pos        BPROT_CONFIG1_REGION38_Pos
+#define MPU_PROTENSET1_PROTREG38_Msk        BPROT_CONFIG1_REGION38_Msk
+#define MPU_PROTENSET1_PROTREG38_Disabled   BPROT_CONFIG1_REGION38_Disabled
+#define MPU_PROTENSET1_PROTREG38_Enabled    BPROT_CONFIG1_REGION38_Enabled
+#define MPU_PROTENSET1_PROTREG38_Set        BPROT_CONFIG1_REGION38_Enabled
+
+#define MPU_PROTENSET1_PROTREG37_Pos        BPROT_CONFIG1_REGION37_Pos
+#define MPU_PROTENSET1_PROTREG37_Msk        BPROT_CONFIG1_REGION37_Msk
+#define MPU_PROTENSET1_PROTREG37_Disabled   BPROT_CONFIG1_REGION37_Disabled
+#define MPU_PROTENSET1_PROTREG37_Enabled    BPROT_CONFIG1_REGION37_Enabled
+#define MPU_PROTENSET1_PROTREG37_Set        BPROT_CONFIG1_REGION37_Enabled
+
+#define MPU_PROTENSET1_PROTREG36_Pos        BPROT_CONFIG1_REGION36_Pos
+#define MPU_PROTENSET1_PROTREG36_Msk        BPROT_CONFIG1_REGION36_Msk
+#define MPU_PROTENSET1_PROTREG36_Disabled   BPROT_CONFIG1_REGION36_Disabled
+#define MPU_PROTENSET1_PROTREG36_Enabled    BPROT_CONFIG1_REGION36_Enabled
+#define MPU_PROTENSET1_PROTREG36_Set        BPROT_CONFIG1_REGION36_Enabled
+
+#define MPU_PROTENSET1_PROTREG35_Pos        BPROT_CONFIG1_REGION35_Pos
+#define MPU_PROTENSET1_PROTREG35_Msk        BPROT_CONFIG1_REGION35_Msk
+#define MPU_PROTENSET1_PROTREG35_Disabled   BPROT_CONFIG1_REGION35_Disabled
+#define MPU_PROTENSET1_PROTREG35_Enabled    BPROT_CONFIG1_REGION35_Enabled
+#define MPU_PROTENSET1_PROTREG35_Set        BPROT_CONFIG1_REGION35_Enabled
+
+#define MPU_PROTENSET1_PROTREG34_Pos        BPROT_CONFIG1_REGION34_Pos
+#define MPU_PROTENSET1_PROTREG34_Msk        BPROT_CONFIG1_REGION34_Msk
+#define MPU_PROTENSET1_PROTREG34_Disabled   BPROT_CONFIG1_REGION34_Disabled
+#define MPU_PROTENSET1_PROTREG34_Enabled    BPROT_CONFIG1_REGION34_Enabled
+#define MPU_PROTENSET1_PROTREG34_Set        BPROT_CONFIG1_REGION34_Enabled
+
+#define MPU_PROTENSET1_PROTREG33_Pos        BPROT_CONFIG1_REGION33_Pos
+#define MPU_PROTENSET1_PROTREG33_Msk        BPROT_CONFIG1_REGION33_Msk
+#define MPU_PROTENSET1_PROTREG33_Disabled   BPROT_CONFIG1_REGION33_Disabled
+#define MPU_PROTENSET1_PROTREG33_Enabled    BPROT_CONFIG1_REGION33_Enabled
+#define MPU_PROTENSET1_PROTREG33_Set        BPROT_CONFIG1_REGION33_Enabled
+
+#define MPU_PROTENSET1_PROTREG32_Pos        BPROT_CONFIG1_REGION32_Pos
+#define MPU_PROTENSET1_PROTREG32_Msk        BPROT_CONFIG1_REGION32_Msk
+#define MPU_PROTENSET1_PROTREG32_Disabled   BPROT_CONFIG1_REGION32_Disabled
+#define MPU_PROTENSET1_PROTREG32_Enabled    BPROT_CONFIG1_REGION32_Enabled
+#define MPU_PROTENSET1_PROTREG32_Set        BPROT_CONFIG1_REGION32_Enabled
+
+#define MPU_PROTENSET0_PROTREG31_Pos        BPROT_CONFIG0_REGION31_Pos
+#define MPU_PROTENSET0_PROTREG31_Msk        BPROT_CONFIG0_REGION31_Msk
+#define MPU_PROTENSET0_PROTREG31_Disabled   BPROT_CONFIG0_REGION31_Disabled
+#define MPU_PROTENSET0_PROTREG31_Enabled    BPROT_CONFIG0_REGION31_Enabled
+#define MPU_PROTENSET0_PROTREG31_Set        BPROT_CONFIG0_REGION31_Enabled
+
+#define MPU_PROTENSET0_PROTREG30_Pos        BPROT_CONFIG0_REGION30_Pos
+#define MPU_PROTENSET0_PROTREG30_Msk        BPROT_CONFIG0_REGION30_Msk
+#define MPU_PROTENSET0_PROTREG30_Disabled   BPROT_CONFIG0_REGION30_Disabled
+#define MPU_PROTENSET0_PROTREG30_Enabled    BPROT_CONFIG0_REGION30_Enabled
+#define MPU_PROTENSET0_PROTREG30_Set        BPROT_CONFIG0_REGION30_Enabled
+
+#define MPU_PROTENSET0_PROTREG29_Pos        BPROT_CONFIG0_REGION29_Pos
+#define MPU_PROTENSET0_PROTREG29_Msk        BPROT_CONFIG0_REGION29_Msk
+#define MPU_PROTENSET0_PROTREG29_Disabled   BPROT_CONFIG0_REGION29_Disabled
+#define MPU_PROTENSET0_PROTREG29_Enabled    BPROT_CONFIG0_REGION29_Enabled
+#define MPU_PROTENSET0_PROTREG29_Set        BPROT_CONFIG0_REGION29_Enabled
+
+#define MPU_PROTENSET0_PROTREG28_Pos        BPROT_CONFIG0_REGION28_Pos
+#define MPU_PROTENSET0_PROTREG28_Msk        BPROT_CONFIG0_REGION28_Msk
+#define MPU_PROTENSET0_PROTREG28_Disabled   BPROT_CONFIG0_REGION28_Disabled
+#define MPU_PROTENSET0_PROTREG28_Enabled    BPROT_CONFIG0_REGION28_Enabled
+#define MPU_PROTENSET0_PROTREG28_Set        BPROT_CONFIG0_REGION28_Enabled
+
+#define MPU_PROTENSET0_PROTREG27_Pos        BPROT_CONFIG0_REGION27_Pos
+#define MPU_PROTENSET0_PROTREG27_Msk        BPROT_CONFIG0_REGION27_Msk
+#define MPU_PROTENSET0_PROTREG27_Disabled   BPROT_CONFIG0_REGION27_Disabled
+#define MPU_PROTENSET0_PROTREG27_Enabled    BPROT_CONFIG0_REGION27_Enabled
+#define MPU_PROTENSET0_PROTREG27_Set        BPROT_CONFIG0_REGION27_Enabled
+
+#define MPU_PROTENSET0_PROTREG26_Pos        BPROT_CONFIG0_REGION26_Pos
+#define MPU_PROTENSET0_PROTREG26_Msk        BPROT_CONFIG0_REGION26_Msk
+#define MPU_PROTENSET0_PROTREG26_Disabled   BPROT_CONFIG0_REGION26_Disabled
+#define MPU_PROTENSET0_PROTREG26_Enabled    BPROT_CONFIG0_REGION26_Enabled
+#define MPU_PROTENSET0_PROTREG26_Set        BPROT_CONFIG0_REGION26_Enabled
+
+#define MPU_PROTENSET0_PROTREG25_Pos        BPROT_CONFIG0_REGION25_Pos
+#define MPU_PROTENSET0_PROTREG25_Msk        BPROT_CONFIG0_REGION25_Msk
+#define MPU_PROTENSET0_PROTREG25_Disabled   BPROT_CONFIG0_REGION25_Disabled
+#define MPU_PROTENSET0_PROTREG25_Enabled    BPROT_CONFIG0_REGION25_Enabled
+#define MPU_PROTENSET0_PROTREG25_Set        BPROT_CONFIG0_REGION25_Enabled
+
+#define MPU_PROTENSET0_PROTREG24_Pos        BPROT_CONFIG0_REGION24_Pos
+#define MPU_PROTENSET0_PROTREG24_Msk        BPROT_CONFIG0_REGION24_Msk
+#define MPU_PROTENSET0_PROTREG24_Disabled   BPROT_CONFIG0_REGION24_Disabled
+#define MPU_PROTENSET0_PROTREG24_Enabled    BPROT_CONFIG0_REGION24_Enabled
+#define MPU_PROTENSET0_PROTREG24_Set        BPROT_CONFIG0_REGION24_Enabled
+
+#define MPU_PROTENSET0_PROTREG23_Pos        BPROT_CONFIG0_REGION23_Pos
+#define MPU_PROTENSET0_PROTREG23_Msk        BPROT_CONFIG0_REGION23_Msk
+#define MPU_PROTENSET0_PROTREG23_Disabled   BPROT_CONFIG0_REGION23_Disabled
+#define MPU_PROTENSET0_PROTREG23_Enabled    BPROT_CONFIG0_REGION23_Enabled
+#define MPU_PROTENSET0_PROTREG23_Set        BPROT_CONFIG0_REGION23_Enabled
+
+#define MPU_PROTENSET0_PROTREG22_Pos        BPROT_CONFIG0_REGION22_Pos
+#define MPU_PROTENSET0_PROTREG22_Msk        BPROT_CONFIG0_REGION22_Msk
+#define MPU_PROTENSET0_PROTREG22_Disabled   BPROT_CONFIG0_REGION22_Disabled
+#define MPU_PROTENSET0_PROTREG22_Enabled    BPROT_CONFIG0_REGION22_Enabled
+#define MPU_PROTENSET0_PROTREG22_Set        BPROT_CONFIG0_REGION22_Enabled
+
+#define MPU_PROTENSET0_PROTREG21_Pos        BPROT_CONFIG0_REGION21_Pos
+#define MPU_PROTENSET0_PROTREG21_Msk        BPROT_CONFIG0_REGION21_Msk
+#define MPU_PROTENSET0_PROTREG21_Disabled   BPROT_CONFIG0_REGION21_Disabled
+#define MPU_PROTENSET0_PROTREG21_Enabled    BPROT_CONFIG0_REGION21_Enabled
+#define MPU_PROTENSET0_PROTREG21_Set        BPROT_CONFIG0_REGION21_Enabled
+
+#define MPU_PROTENSET0_PROTREG20_Pos        BPROT_CONFIG0_REGION20_Pos
+#define MPU_PROTENSET0_PROTREG20_Msk        BPROT_CONFIG0_REGION20_Msk
+#define MPU_PROTENSET0_PROTREG20_Disabled   BPROT_CONFIG0_REGION20_Disabled
+#define MPU_PROTENSET0_PROTREG20_Enabled    BPROT_CONFIG0_REGION20_Enabled
+#define MPU_PROTENSET0_PROTREG20_Set        BPROT_CONFIG0_REGION20_Enabled
+
+#define MPU_PROTENSET0_PROTREG19_Pos        BPROT_CONFIG0_REGION19_Pos
+#define MPU_PROTENSET0_PROTREG19_Msk        BPROT_CONFIG0_REGION19_Msk
+#define MPU_PROTENSET0_PROTREG19_Disabled   BPROT_CONFIG0_REGION19_Disabled
+#define MPU_PROTENSET0_PROTREG19_Enabled    BPROT_CONFIG0_REGION19_Enabled
+#define MPU_PROTENSET0_PROTREG19_Set        BPROT_CONFIG0_REGION19_Enabled
+
+#define MPU_PROTENSET0_PROTREG18_Pos        BPROT_CONFIG0_REGION18_Pos
+#define MPU_PROTENSET0_PROTREG18_Msk        BPROT_CONFIG0_REGION18_Msk
+#define MPU_PROTENSET0_PROTREG18_Disabled   BPROT_CONFIG0_REGION18_Disabled
+#define MPU_PROTENSET0_PROTREG18_Enabled    BPROT_CONFIG0_REGION18_Enabled
+#define MPU_PROTENSET0_PROTREG18_Set        BPROT_CONFIG0_REGION18_Enabled
+
+#define MPU_PROTENSET0_PROTREG17_Pos        BPROT_CONFIG0_REGION17_Pos
+#define MPU_PROTENSET0_PROTREG17_Msk        BPROT_CONFIG0_REGION17_Msk
+#define MPU_PROTENSET0_PROTREG17_Disabled   BPROT_CONFIG0_REGION17_Disabled
+#define MPU_PROTENSET0_PROTREG17_Enabled    BPROT_CONFIG0_REGION17_Enabled
+#define MPU_PROTENSET0_PROTREG17_Set        BPROT_CONFIG0_REGION17_Enabled
+
+#define MPU_PROTENSET0_PROTREG16_Pos        BPROT_CONFIG0_REGION16_Pos
+#define MPU_PROTENSET0_PROTREG16_Msk        BPROT_CONFIG0_REGION16_Msk
+#define MPU_PROTENSET0_PROTREG16_Disabled   BPROT_CONFIG0_REGION16_Disabled
+#define MPU_PROTENSET0_PROTREG16_Enabled    BPROT_CONFIG0_REGION16_Enabled
+#define MPU_PROTENSET0_PROTREG16_Set        BPROT_CONFIG0_REGION16_Enabled
+
+#define MPU_PROTENSET0_PROTREG15_Pos        BPROT_CONFIG0_REGION15_Pos
+#define MPU_PROTENSET0_PROTREG15_Msk        BPROT_CONFIG0_REGION15_Msk
+#define MPU_PROTENSET0_PROTREG15_Disabled   BPROT_CONFIG0_REGION15_Disabled
+#define MPU_PROTENSET0_PROTREG15_Enabled    BPROT_CONFIG0_REGION15_Enabled
+#define MPU_PROTENSET0_PROTREG15_Set        BPROT_CONFIG0_REGION15_Enabled
+
+#define MPU_PROTENSET0_PROTREG14_Pos        BPROT_CONFIG0_REGION14_Pos
+#define MPU_PROTENSET0_PROTREG14_Msk        BPROT_CONFIG0_REGION14_Msk
+#define MPU_PROTENSET0_PROTREG14_Disabled   BPROT_CONFIG0_REGION14_Disabled
+#define MPU_PROTENSET0_PROTREG14_Enabled    BPROT_CONFIG0_REGION14_Enabled
+#define MPU_PROTENSET0_PROTREG14_Set        BPROT_CONFIG0_REGION14_Enabled
+
+#define MPU_PROTENSET0_PROTREG13_Pos        BPROT_CONFIG0_REGION13_Pos
+#define MPU_PROTENSET0_PROTREG13_Msk        BPROT_CONFIG0_REGION13_Msk
+#define MPU_PROTENSET0_PROTREG13_Disabled   BPROT_CONFIG0_REGION13_Disabled
+#define MPU_PROTENSET0_PROTREG13_Enabled    BPROT_CONFIG0_REGION13_Enabled
+#define MPU_PROTENSET0_PROTREG13_Set        BPROT_CONFIG0_REGION13_Enabled
+
+#define MPU_PROTENSET0_PROTREG12_Pos        BPROT_CONFIG0_REGION12_Pos
+#define MPU_PROTENSET0_PROTREG12_Msk        BPROT_CONFIG0_REGION12_Msk
+#define MPU_PROTENSET0_PROTREG12_Disabled   BPROT_CONFIG0_REGION12_Disabled
+#define MPU_PROTENSET0_PROTREG12_Enabled    BPROT_CONFIG0_REGION12_Enabled
+#define MPU_PROTENSET0_PROTREG12_Set        BPROT_CONFIG0_REGION12_Enabled
+
+#define MPU_PROTENSET0_PROTREG11_Pos        BPROT_CONFIG0_REGION11_Pos
+#define MPU_PROTENSET0_PROTREG11_Msk        BPROT_CONFIG0_REGION11_Msk
+#define MPU_PROTENSET0_PROTREG11_Disabled   BPROT_CONFIG0_REGION11_Disabled
+#define MPU_PROTENSET0_PROTREG11_Enabled    BPROT_CONFIG0_REGION11_Enabled
+#define MPU_PROTENSET0_PROTREG11_Set        BPROT_CONFIG0_REGION11_Enabled
+
+#define MPU_PROTENSET0_PROTREG10_Pos        BPROT_CONFIG0_REGION10_Pos
+#define MPU_PROTENSET0_PROTREG10_Msk        BPROT_CONFIG0_REGION10_Msk
+#define MPU_PROTENSET0_PROTREG10_Disabled   BPROT_CONFIG0_REGION10_Disabled
+#define MPU_PROTENSET0_PROTREG10_Enabled    BPROT_CONFIG0_REGION10_Enabled
+#define MPU_PROTENSET0_PROTREG10_Set        BPROT_CONFIG0_REGION10_Enabled
+
+#define MPU_PROTENSET0_PROTREG9_Pos        BPROT_CONFIG0_REGION9_Pos
+#define MPU_PROTENSET0_PROTREG9_Msk        BPROT_CONFIG0_REGION9_Msk
+#define MPU_PROTENSET0_PROTREG9_Disabled   BPROT_CONFIG0_REGION9_Disabled
+#define MPU_PROTENSET0_PROTREG9_Enabled    BPROT_CONFIG0_REGION9_Enabled
+#define MPU_PROTENSET0_PROTREG9_Set        BPROT_CONFIG0_REGION9_Enabled
+
+#define MPU_PROTENSET0_PROTREG8_Pos        BPROT_CONFIG0_REGION8_Pos
+#define MPU_PROTENSET0_PROTREG8_Msk        BPROT_CONFIG0_REGION8_Msk
+#define MPU_PROTENSET0_PROTREG8_Disabled   BPROT_CONFIG0_REGION8_Disabled
+#define MPU_PROTENSET0_PROTREG8_Enabled    BPROT_CONFIG0_REGION8_Enabled
+#define MPU_PROTENSET0_PROTREG8_Set        BPROT_CONFIG0_REGION8_Enabled
+
+#define MPU_PROTENSET0_PROTREG7_Pos        BPROT_CONFIG0_REGION7_Pos
+#define MPU_PROTENSET0_PROTREG7_Msk        BPROT_CONFIG0_REGION7_Msk
+#define MPU_PROTENSET0_PROTREG7_Disabled   BPROT_CONFIG0_REGION7_Disabled
+#define MPU_PROTENSET0_PROTREG7_Enabled    BPROT_CONFIG0_REGION7_Enabled
+#define MPU_PROTENSET0_PROTREG7_Set        BPROT_CONFIG0_REGION7_Enabled
+
+#define MPU_PROTENSET0_PROTREG6_Pos        BPROT_CONFIG0_REGION6_Pos
+#define MPU_PROTENSET0_PROTREG6_Msk        BPROT_CONFIG0_REGION6_Msk
+#define MPU_PROTENSET0_PROTREG6_Disabled   BPROT_CONFIG0_REGION6_Disabled
+#define MPU_PROTENSET0_PROTREG6_Enabled    BPROT_CONFIG0_REGION6_Enabled
+#define MPU_PROTENSET0_PROTREG6_Set        BPROT_CONFIG0_REGION6_Enabled
+
+#define MPU_PROTENSET0_PROTREG5_Pos        BPROT_CONFIG0_REGION5_Pos
+#define MPU_PROTENSET0_PROTREG5_Msk        BPROT_CONFIG0_REGION5_Msk
+#define MPU_PROTENSET0_PROTREG5_Disabled   BPROT_CONFIG0_REGION5_Disabled
+#define MPU_PROTENSET0_PROTREG5_Enabled    BPROT_CONFIG0_REGION5_Enabled
+#define MPU_PROTENSET0_PROTREG5_Set        BPROT_CONFIG0_REGION5_Enabled
+
+#define MPU_PROTENSET0_PROTREG4_Pos        BPROT_CONFIG0_REGION4_Pos
+#define MPU_PROTENSET0_PROTREG4_Msk        BPROT_CONFIG0_REGION4_Msk
+#define MPU_PROTENSET0_PROTREG4_Disabled   BPROT_CONFIG0_REGION4_Disabled
+#define MPU_PROTENSET0_PROTREG4_Enabled    BPROT_CONFIG0_REGION4_Enabled
+#define MPU_PROTENSET0_PROTREG4_Set        BPROT_CONFIG0_REGION4_Enabled
+
+#define MPU_PROTENSET0_PROTREG3_Pos        BPROT_CONFIG0_REGION3_Pos
+#define MPU_PROTENSET0_PROTREG3_Msk        BPROT_CONFIG0_REGION3_Msk
+#define MPU_PROTENSET0_PROTREG3_Disabled   BPROT_CONFIG0_REGION3_Disabled
+#define MPU_PROTENSET0_PROTREG3_Enabled    BPROT_CONFIG0_REGION3_Enabled
+#define MPU_PROTENSET0_PROTREG3_Set        BPROT_CONFIG0_REGION3_Enabled
+
+#define MPU_PROTENSET0_PROTREG2_Pos        BPROT_CONFIG0_REGION2_Pos
+#define MPU_PROTENSET0_PROTREG2_Msk        BPROT_CONFIG0_REGION2_Msk
+#define MPU_PROTENSET0_PROTREG2_Disabled   BPROT_CONFIG0_REGION2_Disabled
+#define MPU_PROTENSET0_PROTREG2_Enabled    BPROT_CONFIG0_REGION2_Enabled
+#define MPU_PROTENSET0_PROTREG2_Set        BPROT_CONFIG0_REGION2_Enabled
+
+#define MPU_PROTENSET0_PROTREG1_Pos        BPROT_CONFIG0_REGION1_Pos
+#define MPU_PROTENSET0_PROTREG1_Msk        BPROT_CONFIG0_REGION1_Msk
+#define MPU_PROTENSET0_PROTREG1_Disabled   BPROT_CONFIG0_REGION1_Disabled
+#define MPU_PROTENSET0_PROTREG1_Enabled    BPROT_CONFIG0_REGION1_Enabled
+#define MPU_PROTENSET0_PROTREG1_Set        BPROT_CONFIG0_REGION1_Enabled
+
+#define MPU_PROTENSET0_PROTREG0_Pos        BPROT_CONFIG0_REGION0_Pos
+#define MPU_PROTENSET0_PROTREG0_Msk        BPROT_CONFIG0_REGION0_Msk
+#define MPU_PROTENSET0_PROTREG0_Disabled   BPROT_CONFIG0_REGION0_Disabled
+#define MPU_PROTENSET0_PROTREG0_Enabled    BPROT_CONFIG0_REGION0_Enabled
+#define MPU_PROTENSET0_PROTREG0_Set        BPROT_CONFIG0_REGION0_Enabled
+
+
+/* From nrf51_deprecated.h */
+
+/* NVMC */
+/* The register ERASEPROTECTEDPAGE changed name to ERASEPCR0 in the documentation. */
+#define ERASEPROTECTEDPAGE      ERASEPCR0
+
+
+/* IRQ */
+/* COMP module was eliminated. Adapted to nrf52 headers. */
+#define LPCOMP_COMP_IRQHandler  COMP_LPCOMP_IRQHandler
+#define LPCOMP_COMP_IRQn        COMP_LPCOMP_IRQn
+
+
+/* REFSEL register redefined enumerated values and added some more. */
+#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling          LPCOMP_REFSEL_REFSEL_Ref1_8Vdd
+#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling         LPCOMP_REFSEL_REFSEL_Ref2_8Vdd
+#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling       LPCOMP_REFSEL_REFSEL_Ref3_8Vdd
+#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling        LPCOMP_REFSEL_REFSEL_Ref4_8Vdd
+#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling        LPCOMP_REFSEL_REFSEL_Ref5_8Vdd
+#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling         LPCOMP_REFSEL_REFSEL_Ref6_8Vdd
+#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling       LPCOMP_REFSEL_REFSEL_Ref7_8Vdd
+
+
+/* RADIO */
+/* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */
+#define RADIO_CRCCNF_SKIP_ADDR_Pos      RADIO_CRCCNF_SKIPADDR_Pos
+#define RADIO_CRCCNF_SKIP_ADDR_Msk      RADIO_CRCCNF_SKIPADDR_Msk
+#define RADIO_CRCCNF_SKIP_ADDR_Include  RADIO_CRCCNF_SKIPADDR_Include
+#define RADIO_CRCCNF_SKIP_ADDR_Skip     RADIO_CRCCNF_SKIPADDR_Skip
+
+
+/* FICR */
+/* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */
+#define DEVICEID0       DEVICEID[0]
+#define DEVICEID1       DEVICEID[1]
+
+/* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */
+#define ER0             ER[0]
+#define ER1             ER[1]
+#define ER2             ER[2]
+#define ER3             ER[3]
+
+/* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */
+#define IR0             IR[0]
+#define IR1             IR[1]
+#define IR2             IR[2]
+#define IR3             IR[3]
+
+/* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */
+#define DEVICEADDR0     DEVICEADDR[0]
+#define DEVICEADDR1     DEVICEADDR[1]
+
+
+/* PPI */
+/* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */
+#define TASKS_CHG0EN     TASKS_CHG[0].EN
+#define TASKS_CHG0DIS    TASKS_CHG[0].DIS
+#define TASKS_CHG1EN     TASKS_CHG[1].EN
+#define TASKS_CHG1DIS    TASKS_CHG[1].DIS
+#define TASKS_CHG2EN     TASKS_CHG[2].EN
+#define TASKS_CHG2DIS    TASKS_CHG[2].DIS
+#define TASKS_CHG3EN     TASKS_CHG[3].EN
+#define TASKS_CHG3DIS    TASKS_CHG[3].DIS
+
+/* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */
+#define CH0_EEP          CH[0].EEP
+#define CH0_TEP          CH[0].TEP
+#define CH1_EEP          CH[1].EEP
+#define CH1_TEP          CH[1].TEP
+#define CH2_EEP          CH[2].EEP
+#define CH2_TEP          CH[2].TEP
+#define CH3_EEP          CH[3].EEP
+#define CH3_TEP          CH[3].TEP
+#define CH4_EEP          CH[4].EEP
+#define CH4_TEP          CH[4].TEP
+#define CH5_EEP          CH[5].EEP
+#define CH5_TEP          CH[5].TEP
+#define CH6_EEP          CH[6].EEP
+#define CH6_TEP          CH[6].TEP
+#define CH7_EEP          CH[7].EEP
+#define CH7_TEP          CH[7].TEP
+#define CH8_EEP          CH[8].EEP
+#define CH8_TEP          CH[8].TEP
+#define CH9_EEP          CH[9].EEP
+#define CH9_TEP          CH[9].TEP
+#define CH10_EEP         CH[10].EEP
+#define CH10_TEP         CH[10].TEP
+#define CH11_EEP         CH[11].EEP
+#define CH11_TEP         CH[11].TEP
+#define CH12_EEP         CH[12].EEP
+#define CH12_TEP         CH[12].TEP
+#define CH13_EEP         CH[13].EEP
+#define CH13_TEP         CH[13].TEP
+#define CH14_EEP         CH[14].EEP
+#define CH14_TEP         CH[14].TEP
+#define CH15_EEP         CH[15].EEP
+#define CH15_TEP         CH[15].TEP
+
+/* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */
+#define CHG0             CHG[0]
+#define CHG1             CHG[1]
+#define CHG2             CHG[2]
+#define CHG3             CHG[3]
+
+/* All bitfield macros for the CHGx registers therefore changed name. */
+#define PPI_CHG0_CH15_Pos       PPI_CHG_CH15_Pos
+#define PPI_CHG0_CH15_Msk       PPI_CHG_CH15_Msk
+#define PPI_CHG0_CH15_Excluded  PPI_CHG_CH15_Excluded
+#define PPI_CHG0_CH15_Included  PPI_CHG_CH15_Included
+
+#define PPI_CHG0_CH14_Pos       PPI_CHG_CH14_Pos
+#define PPI_CHG0_CH14_Msk       PPI_CHG_CH14_Msk
+#define PPI_CHG0_CH14_Excluded  PPI_CHG_CH14_Excluded
+#define PPI_CHG0_CH14_Included  PPI_CHG_CH14_Included
+
+#define PPI_CHG0_CH13_Pos       PPI_CHG_CH13_Pos
+#define PPI_CHG0_CH13_Msk       PPI_CHG_CH13_Msk
+#define PPI_CHG0_CH13_Excluded  PPI_CHG_CH13_Excluded
+#define PPI_CHG0_CH13_Included  PPI_CHG_CH13_Included
+
+#define PPI_CHG0_CH12_Pos       PPI_CHG_CH12_Pos
+#define PPI_CHG0_CH12_Msk       PPI_CHG_CH12_Msk
+#define PPI_CHG0_CH12_Excluded  PPI_CHG_CH12_Excluded
+#define PPI_CHG0_CH12_Included  PPI_CHG_CH12_Included
+
+#define PPI_CHG0_CH11_Pos       PPI_CHG_CH11_Pos
+#define PPI_CHG0_CH11_Msk       PPI_CHG_CH11_Msk
+#define PPI_CHG0_CH11_Excluded  PPI_CHG_CH11_Excluded
+#define PPI_CHG0_CH11_Included  PPI_CHG_CH11_Included
+
+#define PPI_CHG0_CH10_Pos       PPI_CHG_CH10_Pos
+#define PPI_CHG0_CH10_Msk       PPI_CHG_CH10_Msk
+#define PPI_CHG0_CH10_Excluded  PPI_CHG_CH10_Excluded
+#define PPI_CHG0_CH10_Included  PPI_CHG_CH10_Included
+
+#define PPI_CHG0_CH9_Pos        PPI_CHG_CH9_Pos
+#define PPI_CHG0_CH9_Msk        PPI_CHG_CH9_Msk
+#define PPI_CHG0_CH9_Excluded   PPI_CHG_CH9_Excluded
+#define PPI_CHG0_CH9_Included   PPI_CHG_CH9_Included
+
+#define PPI_CHG0_CH8_Pos        PPI_CHG_CH8_Pos
+#define PPI_CHG0_CH8_Msk        PPI_CHG_CH8_Msk
+#define PPI_CHG0_CH8_Excluded   PPI_CHG_CH8_Excluded
+#define PPI_CHG0_CH8_Included   PPI_CHG_CH8_Included
+
+#define PPI_CHG0_CH7_Pos        PPI_CHG_CH7_Pos
+#define PPI_CHG0_CH7_Msk        PPI_CHG_CH7_Msk
+#define PPI_CHG0_CH7_Excluded   PPI_CHG_CH7_Excluded
+#define PPI_CHG0_CH7_Included   PPI_CHG_CH7_Included
+
+#define PPI_CHG0_CH6_Pos        PPI_CHG_CH6_Pos
+#define PPI_CHG0_CH6_Msk        PPI_CHG_CH6_Msk
+#define PPI_CHG0_CH6_Excluded   PPI_CHG_CH6_Excluded
+#define PPI_CHG0_CH6_Included   PPI_CHG_CH6_Included
+
+#define PPI_CHG0_CH5_Pos        PPI_CHG_CH5_Pos
+#define PPI_CHG0_CH5_Msk        PPI_CHG_CH5_Msk
+#define PPI_CHG0_CH5_Excluded   PPI_CHG_CH5_Excluded
+#define PPI_CHG0_CH5_Included   PPI_CHG_CH5_Included
+
+#define PPI_CHG0_CH4_Pos        PPI_CHG_CH4_Pos
+#define PPI_CHG0_CH4_Msk        PPI_CHG_CH4_Msk
+#define PPI_CHG0_CH4_Excluded   PPI_CHG_CH4_Excluded
+#define PPI_CHG0_CH4_Included   PPI_CHG_CH4_Included
+
+#define PPI_CHG0_CH3_Pos        PPI_CHG_CH3_Pos
+#define PPI_CHG0_CH3_Msk        PPI_CHG_CH3_Msk
+#define PPI_CHG0_CH3_Excluded   PPI_CHG_CH3_Excluded
+#define PPI_CHG0_CH3_Included   PPI_CHG_CH3_Included
+
+#define PPI_CHG0_CH2_Pos        PPI_CHG_CH2_Pos
+#define PPI_CHG0_CH2_Msk        PPI_CHG_CH2_Msk
+#define PPI_CHG0_CH2_Excluded   PPI_CHG_CH2_Excluded
+#define PPI_CHG0_CH2_Included   PPI_CHG_CH2_Included
+
+#define PPI_CHG0_CH1_Pos        PPI_CHG_CH1_Pos
+#define PPI_CHG0_CH1_Msk        PPI_CHG_CH1_Msk
+#define PPI_CHG0_CH1_Excluded   PPI_CHG_CH1_Excluded
+#define PPI_CHG0_CH1_Included   PPI_CHG_CH1_Included
+
+#define PPI_CHG0_CH0_Pos        PPI_CHG_CH0_Pos
+#define PPI_CHG0_CH0_Msk        PPI_CHG_CH0_Msk
+#define PPI_CHG0_CH0_Excluded   PPI_CHG_CH0_Excluded
+#define PPI_CHG0_CH0_Included   PPI_CHG_CH0_Included
+
+#define PPI_CHG1_CH15_Pos       PPI_CHG_CH15_Pos
+#define PPI_CHG1_CH15_Msk       PPI_CHG_CH15_Msk
+#define PPI_CHG1_CH15_Excluded  PPI_CHG_CH15_Excluded
+#define PPI_CHG1_CH15_Included  PPI_CHG_CH15_Included
+
+#define PPI_CHG1_CH14_Pos       PPI_CHG_CH14_Pos
+#define PPI_CHG1_CH14_Msk       PPI_CHG_CH14_Msk
+#define PPI_CHG1_CH14_Excluded  PPI_CHG_CH14_Excluded
+#define PPI_CHG1_CH14_Included  PPI_CHG_CH14_Included
+
+#define PPI_CHG1_CH13_Pos       PPI_CHG_CH13_Pos
+#define PPI_CHG1_CH13_Msk       PPI_CHG_CH13_Msk
+#define PPI_CHG1_CH13_Excluded  PPI_CHG_CH13_Excluded
+#define PPI_CHG1_CH13_Included  PPI_CHG_CH13_Included
+
+#define PPI_CHG1_CH12_Pos       PPI_CHG_CH12_Pos
+#define PPI_CHG1_CH12_Msk       PPI_CHG_CH12_Msk
+#define PPI_CHG1_CH12_Excluded  PPI_CHG_CH12_Excluded
+#define PPI_CHG1_CH12_Included  PPI_CHG_CH12_Included
+
+#define PPI_CHG1_CH11_Pos       PPI_CHG_CH11_Pos
+#define PPI_CHG1_CH11_Msk       PPI_CHG_CH11_Msk
+#define PPI_CHG1_CH11_Excluded  PPI_CHG_CH11_Excluded
+#define PPI_CHG1_CH11_Included  PPI_CHG_CH11_Included
+
+#define PPI_CHG1_CH10_Pos       PPI_CHG_CH10_Pos
+#define PPI_CHG1_CH10_Msk       PPI_CHG_CH10_Msk
+#define PPI_CHG1_CH10_Excluded  PPI_CHG_CH10_Excluded
+#define PPI_CHG1_CH10_Included  PPI_CHG_CH10_Included
+
+#define PPI_CHG1_CH9_Pos        PPI_CHG_CH9_Pos
+#define PPI_CHG1_CH9_Msk        PPI_CHG_CH9_Msk
+#define PPI_CHG1_CH9_Excluded   PPI_CHG_CH9_Excluded
+#define PPI_CHG1_CH9_Included   PPI_CHG_CH9_Included
+
+#define PPI_CHG1_CH8_Pos        PPI_CHG_CH8_Pos
+#define PPI_CHG1_CH8_Msk        PPI_CHG_CH8_Msk
+#define PPI_CHG1_CH8_Excluded   PPI_CHG_CH8_Excluded
+#define PPI_CHG1_CH8_Included   PPI_CHG_CH8_Included
+
+#define PPI_CHG1_CH7_Pos        PPI_CHG_CH7_Pos
+#define PPI_CHG1_CH7_Msk        PPI_CHG_CH7_Msk
+#define PPI_CHG1_CH7_Excluded   PPI_CHG_CH7_Excluded
+#define PPI_CHG1_CH7_Included   PPI_CHG_CH7_Included
+
+#define PPI_CHG1_CH6_Pos        PPI_CHG_CH6_Pos
+#define PPI_CHG1_CH6_Msk        PPI_CHG_CH6_Msk
+#define PPI_CHG1_CH6_Excluded   PPI_CHG_CH6_Excluded
+#define PPI_CHG1_CH6_Included   PPI_CHG_CH6_Included
+
+#define PPI_CHG1_CH5_Pos        PPI_CHG_CH5_Pos
+#define PPI_CHG1_CH5_Msk        PPI_CHG_CH5_Msk
+#define PPI_CHG1_CH5_Excluded   PPI_CHG_CH5_Excluded
+#define PPI_CHG1_CH5_Included   PPI_CHG_CH5_Included
+
+#define PPI_CHG1_CH4_Pos        PPI_CHG_CH4_Pos
+#define PPI_CHG1_CH4_Msk        PPI_CHG_CH4_Msk
+#define PPI_CHG1_CH4_Excluded   PPI_CHG_CH4_Excluded
+#define PPI_CHG1_CH4_Included   PPI_CHG_CH4_Included
+
+#define PPI_CHG1_CH3_Pos        PPI_CHG_CH3_Pos
+#define PPI_CHG1_CH3_Msk        PPI_CHG_CH3_Msk
+#define PPI_CHG1_CH3_Excluded   PPI_CHG_CH3_Excluded
+#define PPI_CHG1_CH3_Included   PPI_CHG_CH3_Included
+
+#define PPI_CHG1_CH2_Pos        PPI_CHG_CH2_Pos
+#define PPI_CHG1_CH2_Msk        PPI_CHG_CH2_Msk
+#define PPI_CHG1_CH2_Excluded   PPI_CHG_CH2_Excluded
+#define PPI_CHG1_CH2_Included   PPI_CHG_CH2_Included
+
+#define PPI_CHG1_CH1_Pos        PPI_CHG_CH1_Pos
+#define PPI_CHG1_CH1_Msk        PPI_CHG_CH1_Msk
+#define PPI_CHG1_CH1_Excluded   PPI_CHG_CH1_Excluded
+#define PPI_CHG1_CH1_Included   PPI_CHG_CH1_Included
+
+#define PPI_CHG1_CH0_Pos        PPI_CHG_CH0_Pos
+#define PPI_CHG1_CH0_Msk        PPI_CHG_CH0_Msk
+#define PPI_CHG1_CH0_Excluded   PPI_CHG_CH0_Excluded
+#define PPI_CHG1_CH0_Included   PPI_CHG_CH0_Included
+
+#define PPI_CHG2_CH15_Pos       PPI_CHG_CH15_Pos
+#define PPI_CHG2_CH15_Msk       PPI_CHG_CH15_Msk
+#define PPI_CHG2_CH15_Excluded  PPI_CHG_CH15_Excluded
+#define PPI_CHG2_CH15_Included  PPI_CHG_CH15_Included
+
+#define PPI_CHG2_CH14_Pos       PPI_CHG_CH14_Pos
+#define PPI_CHG2_CH14_Msk       PPI_CHG_CH14_Msk
+#define PPI_CHG2_CH14_Excluded  PPI_CHG_CH14_Excluded
+#define PPI_CHG2_CH14_Included  PPI_CHG_CH14_Included
+
+#define PPI_CHG2_CH13_Pos       PPI_CHG_CH13_Pos
+#define PPI_CHG2_CH13_Msk       PPI_CHG_CH13_Msk
+#define PPI_CHG2_CH13_Excluded  PPI_CHG_CH13_Excluded
+#define PPI_CHG2_CH13_Included  PPI_CHG_CH13_Included
+
+#define PPI_CHG2_CH12_Pos       PPI_CHG_CH12_Pos
+#define PPI_CHG2_CH12_Msk       PPI_CHG_CH12_Msk
+#define PPI_CHG2_CH12_Excluded  PPI_CHG_CH12_Excluded
+#define PPI_CHG2_CH12_Included  PPI_CHG_CH12_Included
+
+#define PPI_CHG2_CH11_Pos       PPI_CHG_CH11_Pos
+#define PPI_CHG2_CH11_Msk       PPI_CHG_CH11_Msk
+#define PPI_CHG2_CH11_Excluded  PPI_CHG_CH11_Excluded
+#define PPI_CHG2_CH11_Included  PPI_CHG_CH11_Included
+
+#define PPI_CHG2_CH10_Pos       PPI_CHG_CH10_Pos
+#define PPI_CHG2_CH10_Msk       PPI_CHG_CH10_Msk
+#define PPI_CHG2_CH10_Excluded  PPI_CHG_CH10_Excluded
+#define PPI_CHG2_CH10_Included  PPI_CHG_CH10_Included
+
+#define PPI_CHG2_CH9_Pos        PPI_CHG_CH9_Pos
+#define PPI_CHG2_CH9_Msk        PPI_CHG_CH9_Msk
+#define PPI_CHG2_CH9_Excluded   PPI_CHG_CH9_Excluded
+#define PPI_CHG2_CH9_Included   PPI_CHG_CH9_Included
+
+#define PPI_CHG2_CH8_Pos        PPI_CHG_CH8_Pos
+#define PPI_CHG2_CH8_Msk        PPI_CHG_CH8_Msk
+#define PPI_CHG2_CH8_Excluded   PPI_CHG_CH8_Excluded
+#define PPI_CHG2_CH8_Included   PPI_CHG_CH8_Included
+
+#define PPI_CHG2_CH7_Pos        PPI_CHG_CH7_Pos
+#define PPI_CHG2_CH7_Msk        PPI_CHG_CH7_Msk
+#define PPI_CHG2_CH7_Excluded   PPI_CHG_CH7_Excluded
+#define PPI_CHG2_CH7_Included   PPI_CHG_CH7_Included
+
+#define PPI_CHG2_CH6_Pos        PPI_CHG_CH6_Pos
+#define PPI_CHG2_CH6_Msk        PPI_CHG_CH6_Msk
+#define PPI_CHG2_CH6_Excluded   PPI_CHG_CH6_Excluded
+#define PPI_CHG2_CH6_Included   PPI_CHG_CH6_Included
+
+#define PPI_CHG2_CH5_Pos        PPI_CHG_CH5_Pos
+#define PPI_CHG2_CH5_Msk        PPI_CHG_CH5_Msk
+#define PPI_CHG2_CH5_Excluded   PPI_CHG_CH5_Excluded
+#define PPI_CHG2_CH5_Included   PPI_CHG_CH5_Included
+
+#define PPI_CHG2_CH4_Pos        PPI_CHG_CH4_Pos
+#define PPI_CHG2_CH4_Msk        PPI_CHG_CH4_Msk
+#define PPI_CHG2_CH4_Excluded   PPI_CHG_CH4_Excluded
+#define PPI_CHG2_CH4_Included   PPI_CHG_CH4_Included
+
+#define PPI_CHG2_CH3_Pos        PPI_CHG_CH3_Pos
+#define PPI_CHG2_CH3_Msk        PPI_CHG_CH3_Msk
+#define PPI_CHG2_CH3_Excluded   PPI_CHG_CH3_Excluded
+#define PPI_CHG2_CH3_Included   PPI_CHG_CH3_Included
+
+#define PPI_CHG2_CH2_Pos        PPI_CHG_CH2_Pos
+#define PPI_CHG2_CH2_Msk        PPI_CHG_CH2_Msk
+#define PPI_CHG2_CH2_Excluded   PPI_CHG_CH2_Excluded
+#define PPI_CHG2_CH2_Included   PPI_CHG_CH2_Included
+
+#define PPI_CHG2_CH1_Pos        PPI_CHG_CH1_Pos
+#define PPI_CHG2_CH1_Msk        PPI_CHG_CH1_Msk
+#define PPI_CHG2_CH1_Excluded   PPI_CHG_CH1_Excluded
+#define PPI_CHG2_CH1_Included   PPI_CHG_CH1_Included
+
+#define PPI_CHG2_CH0_Pos        PPI_CHG_CH0_Pos
+#define PPI_CHG2_CH0_Msk        PPI_CHG_CH0_Msk
+#define PPI_CHG2_CH0_Excluded   PPI_CHG_CH0_Excluded
+#define PPI_CHG2_CH0_Included   PPI_CHG_CH0_Included
+
+#define PPI_CHG3_CH15_Pos       PPI_CHG_CH15_Pos
+#define PPI_CHG3_CH15_Msk       PPI_CHG_CH15_Msk
+#define PPI_CHG3_CH15_Excluded  PPI_CHG_CH15_Excluded
+#define PPI_CHG3_CH15_Included  PPI_CHG_CH15_Included
+
+#define PPI_CHG3_CH14_Pos       PPI_CHG_CH14_Pos
+#define PPI_CHG3_CH14_Msk       PPI_CHG_CH14_Msk
+#define PPI_CHG3_CH14_Excluded  PPI_CHG_CH14_Excluded
+#define PPI_CHG3_CH14_Included  PPI_CHG_CH14_Included
+
+#define PPI_CHG3_CH13_Pos       PPI_CHG_CH13_Pos
+#define PPI_CHG3_CH13_Msk       PPI_CHG_CH13_Msk
+#define PPI_CHG3_CH13_Excluded  PPI_CHG_CH13_Excluded
+#define PPI_CHG3_CH13_Included  PPI_CHG_CH13_Included
+
+#define PPI_CHG3_CH12_Pos       PPI_CHG_CH12_Pos
+#define PPI_CHG3_CH12_Msk       PPI_CHG_CH12_Msk
+#define PPI_CHG3_CH12_Excluded  PPI_CHG_CH12_Excluded
+#define PPI_CHG3_CH12_Included  PPI_CHG_CH12_Included
+
+#define PPI_CHG3_CH11_Pos       PPI_CHG_CH11_Pos
+#define PPI_CHG3_CH11_Msk       PPI_CHG_CH11_Msk
+#define PPI_CHG3_CH11_Excluded  PPI_CHG_CH11_Excluded
+#define PPI_CHG3_CH11_Included  PPI_CHG_CH11_Included
+
+#define PPI_CHG3_CH10_Pos       PPI_CHG_CH10_Pos
+#define PPI_CHG3_CH10_Msk       PPI_CHG_CH10_Msk
+#define PPI_CHG3_CH10_Excluded  PPI_CHG_CH10_Excluded
+#define PPI_CHG3_CH10_Included  PPI_CHG_CH10_Included
+
+#define PPI_CHG3_CH9_Pos        PPI_CHG_CH9_Pos
+#define PPI_CHG3_CH9_Msk        PPI_CHG_CH9_Msk
+#define PPI_CHG3_CH9_Excluded   PPI_CHG_CH9_Excluded
+#define PPI_CHG3_CH9_Included   PPI_CHG_CH9_Included
+
+#define PPI_CHG3_CH8_Pos        PPI_CHG_CH8_Pos
+#define PPI_CHG3_CH8_Msk        PPI_CHG_CH8_Msk
+#define PPI_CHG3_CH8_Excluded   PPI_CHG_CH8_Excluded
+#define PPI_CHG3_CH8_Included   PPI_CHG_CH8_Included
+
+#define PPI_CHG3_CH7_Pos        PPI_CHG_CH7_Pos
+#define PPI_CHG3_CH7_Msk        PPI_CHG_CH7_Msk
+#define PPI_CHG3_CH7_Excluded   PPI_CHG_CH7_Excluded
+#define PPI_CHG3_CH7_Included   PPI_CHG_CH7_Included
+
+#define PPI_CHG3_CH6_Pos        PPI_CHG_CH6_Pos
+#define PPI_CHG3_CH6_Msk        PPI_CHG_CH6_Msk
+#define PPI_CHG3_CH6_Excluded   PPI_CHG_CH6_Excluded
+#define PPI_CHG3_CH6_Included   PPI_CHG_CH6_Included
+
+#define PPI_CHG3_CH5_Pos        PPI_CHG_CH5_Pos
+#define PPI_CHG3_CH5_Msk        PPI_CHG_CH5_Msk
+#define PPI_CHG3_CH5_Excluded   PPI_CHG_CH5_Excluded
+#define PPI_CHG3_CH5_Included   PPI_CHG_CH5_Included
+
+#define PPI_CHG3_CH4_Pos        PPI_CHG_CH4_Pos
+#define PPI_CHG3_CH4_Msk        PPI_CHG_CH4_Msk
+#define PPI_CHG3_CH4_Excluded   PPI_CHG_CH4_Excluded
+#define PPI_CHG3_CH4_Included   PPI_CHG_CH4_Included
+
+#define PPI_CHG3_CH3_Pos        PPI_CHG_CH3_Pos
+#define PPI_CHG3_CH3_Msk        PPI_CHG_CH3_Msk
+#define PPI_CHG3_CH3_Excluded   PPI_CHG_CH3_Excluded
+#define PPI_CHG3_CH3_Included   PPI_CHG_CH3_Included
+
+#define PPI_CHG3_CH2_Pos        PPI_CHG_CH2_Pos
+#define PPI_CHG3_CH2_Msk        PPI_CHG_CH2_Msk
+#define PPI_CHG3_CH2_Excluded   PPI_CHG_CH2_Excluded
+#define PPI_CHG3_CH2_Included   PPI_CHG_CH2_Included
+
+#define PPI_CHG3_CH1_Pos        PPI_CHG_CH1_Pos
+#define PPI_CHG3_CH1_Msk        PPI_CHG_CH1_Msk
+#define PPI_CHG3_CH1_Excluded   PPI_CHG_CH1_Excluded
+#define PPI_CHG3_CH1_Included   PPI_CHG_CH1_Included
+
+#define PPI_CHG3_CH0_Pos        PPI_CHG_CH0_Pos
+#define PPI_CHG3_CH0_Msk        PPI_CHG_CH0_Msk
+#define PPI_CHG3_CH0_Excluded   PPI_CHG_CH0_Excluded
+#define PPI_CHG3_CH0_Included   PPI_CHG_CH0_Included
+
+
+
+
+/*lint --flb "Leave library region" */
+
+#endif /* NRF51_TO_NRF52_H */
+
diff --git a/ports/nrf/device/nrf52/nrf51_to_nrf52840.h b/ports/nrf/device/nrf52/nrf51_to_nrf52840.h
new file mode 100644
index 0000000000..2ee36e7558
--- /dev/null
+++ b/ports/nrf/device/nrf52/nrf51_to_nrf52840.h
@@ -0,0 +1,567 @@
+/* Copyright (c) 2016, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *   * Redistributions of source code must retain the above copyright notice, this
+ *     list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *
+ *   * Neither the name of Nordic Semiconductor ASA nor the names of its
+ *     contributors may be used to endorse or promote products derived from
+ *     this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+ 
+#ifndef NRF51_TO_NRF52840_H
+#define NRF51_TO_NRF52840_H
+
+/*lint ++flb "Enter library region */
+
+/* This file is given to prevent your SW from not compiling with the name changes between nRF51 and nRF52840 devices.
+ * It redefines the old nRF51 names into the new ones as long as the functionality is still supported. If the
+ * functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros
+ * from the nrf51_deprecated.h file. */
+
+
+/* IRQ */
+/* Several peripherals have been added to several indexes. Names of IRQ handlers and IRQ numbers have changed. */
+#define UART0_IRQHandler        UARTE0_UART0_IRQHandler
+#define SPI0_TWI0_IRQHandler    SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+#define SPI1_TWI1_IRQHandler    SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+#define ADC_IRQHandler          SAADC_IRQHandler
+#define LPCOMP_IRQHandler       COMP_LPCOMP_IRQHandler
+#define SWI0_IRQHandler         SWI0_EGU0_IRQHandler
+#define SWI1_IRQHandler         SWI1_EGU1_IRQHandler
+#define SWI2_IRQHandler         SWI2_EGU2_IRQHandler
+#define SWI3_IRQHandler         SWI3_EGU3_IRQHandler
+#define SWI4_IRQHandler         SWI4_EGU4_IRQHandler
+#define SWI5_IRQHandler         SWI5_EGU5_IRQHandler
+
+#define UART0_IRQn              UARTE0_UART0_IRQn
+#define SPI0_TWI0_IRQn          SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn
+#define SPI1_TWI1_IRQn          SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn
+#define ADC_IRQn                SAADC_IRQn
+#define LPCOMP_IRQn             COMP_LPCOMP_IRQn
+#define SWI0_IRQn               SWI0_EGU0_IRQn
+#define SWI1_IRQn               SWI1_EGU1_IRQn
+#define SWI2_IRQn               SWI2_EGU2_IRQn
+#define SWI3_IRQn               SWI3_EGU3_IRQn
+#define SWI4_IRQn               SWI4_EGU4_IRQn
+#define SWI5_IRQn               SWI5_EGU5_IRQn
+
+
+/* UICR */
+/* Register RBPCONF was renamed to APPROTECT. */
+#define RBPCONF     APPROTECT
+
+#define UICR_RBPCONF_PALL_Pos           UICR_APPROTECT_PALL_Pos
+#define UICR_RBPCONF_PALL_Msk           UICR_APPROTECT_PALL_Msk
+#define UICR_RBPCONF_PALL_Enabled       UICR_APPROTECT_PALL_Enabled
+#define UICR_RBPCONF_PALL_Disabled      UICR_APPROTECT_PALL_Disabled
+
+
+/* GPIO */
+/* GPIO port was renamed to P0. */
+#define NRF_GPIO        NRF_P0
+#define NRF_GPIO_BASE   NRF_P0_BASE
+
+
+/* QDEC */
+/* The registers PSELA, PSELB and PSELLED were restructured into a struct. */
+#define PSELLED     PSEL.LED
+#define PSELA       PSEL.A
+#define PSELB       PSEL.B
+
+
+/* SPIS */
+/* The registers PSELSCK, PSELMISO, PSELMOSI, PSELCSN were restructured into a struct. */
+#define PSELSCK       PSEL.SCK
+#define PSELMISO      PSEL.MISO
+#define PSELMOSI      PSEL.MOSI
+#define PSELCSN       PSEL.CSN
+
+/* The registers RXDPTR, MAXRX, AMOUNTRX were restructured into a struct */
+#define RXDPTR        RXD.PTR
+#define MAXRX         RXD.MAXCNT
+#define AMOUNTRX      RXD.AMOUNT
+
+#define SPIS_MAXRX_MAXRX_Pos        SPIS_RXD_MAXCNT_MAXCNT_Pos
+#define SPIS_MAXRX_MAXRX_Msk        SPIS_RXD_MAXCNT_MAXCNT_Msk
+
+#define SPIS_AMOUNTRX_AMOUNTRX_Pos  SPIS_RXD_AMOUNT_AMOUNT_Pos
+#define SPIS_AMOUNTRX_AMOUNTRX_Msk  SPIS_RXD_AMOUNT_AMOUNT_Msk
+
+/* The registers TXDPTR, MAXTX, AMOUNTTX were restructured into a struct */
+#define TXDPTR        TXD.PTR
+#define MAXTX         TXD.MAXCNT
+#define AMOUNTTX      TXD.AMOUNT
+
+#define SPIS_MAXTX_MAXTX_Pos        SPIS_TXD_MAXCNT_MAXCNT_Pos
+#define SPIS_MAXTX_MAXTX_Msk        SPIS_TXD_MAXCNT_MAXCNT_Msk
+
+#define SPIS_AMOUNTTX_AMOUNTTX_Pos  SPIS_TXD_AMOUNT_AMOUNT_Pos
+#define SPIS_AMOUNTTX_AMOUNTTX_Msk  SPIS_TXD_AMOUNT_AMOUNT_Msk
+
+
+/* UART */
+/* The registers PSELRTS, PSELTXD, PSELCTS, PSELRXD were restructured into a struct. */
+#define PSELRTS       PSEL.RTS
+#define PSELTXD       PSEL.TXD
+#define PSELCTS       PSEL.CTS
+#define PSELRXD       PSEL.RXD
+
+/* TWI */
+/* The registers PSELSCL, PSELSDA were restructured into a struct. */
+#define PSELSCL       PSEL.SCL
+#define PSELSDA       PSEL.SDA
+
+
+
+/* From nrf51_deprecated.h */
+
+/* NVMC */
+/* The register ERASEPROTECTEDPAGE changed name to ERASEPCR0 in the documentation. */
+#define ERASEPROTECTEDPAGE      ERASEPCR0
+
+
+/* IRQ */
+/* COMP module was eliminated. Adapted to nrf52840 headers. */
+#define LPCOMP_COMP_IRQHandler  COMP_LPCOMP_IRQHandler
+#define LPCOMP_COMP_IRQn        COMP_LPCOMP_IRQn
+
+
+/* REFSEL register redefined enumerated values and added some more. */
+#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling          LPCOMP_REFSEL_REFSEL_Ref1_8Vdd
+#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling         LPCOMP_REFSEL_REFSEL_Ref2_8Vdd
+#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling       LPCOMP_REFSEL_REFSEL_Ref3_8Vdd
+#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling        LPCOMP_REFSEL_REFSEL_Ref4_8Vdd
+#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling        LPCOMP_REFSEL_REFSEL_Ref5_8Vdd
+#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling         LPCOMP_REFSEL_REFSEL_Ref6_8Vdd
+#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling       LPCOMP_REFSEL_REFSEL_Ref7_8Vdd
+
+
+/* RADIO */
+/* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */
+#define RADIO_CRCCNF_SKIP_ADDR_Pos      RADIO_CRCCNF_SKIPADDR_Pos
+#define RADIO_CRCCNF_SKIP_ADDR_Msk      RADIO_CRCCNF_SKIPADDR_Msk
+#define RADIO_CRCCNF_SKIP_ADDR_Include  RADIO_CRCCNF_SKIPADDR_Include
+#define RADIO_CRCCNF_SKIP_ADDR_Skip     RADIO_CRCCNF_SKIPADDR_Skip
+
+
+/* FICR */
+/* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */
+#define DEVICEID0       DEVICEID[0]
+#define DEVICEID1       DEVICEID[1]
+
+/* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */
+#define ER0             ER[0]
+#define ER1             ER[1]
+#define ER2             ER[2]
+#define ER3             ER[3]
+
+/* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */
+#define IR0             IR[0]
+#define IR1             IR[1]
+#define IR2             IR[2]
+#define IR3             IR[3]
+
+/* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */
+#define DEVICEADDR0     DEVICEADDR[0]
+#define DEVICEADDR1     DEVICEADDR[1]
+
+
+/* PPI */
+/* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */
+#define TASKS_CHG0EN     TASKS_CHG[0].EN
+#define TASKS_CHG0DIS    TASKS_CHG[0].DIS
+#define TASKS_CHG1EN     TASKS_CHG[1].EN
+#define TASKS_CHG1DIS    TASKS_CHG[1].DIS
+#define TASKS_CHG2EN     TASKS_CHG[2].EN
+#define TASKS_CHG2DIS    TASKS_CHG[2].DIS
+#define TASKS_CHG3EN     TASKS_CHG[3].EN
+#define TASKS_CHG3DIS    TASKS_CHG[3].DIS
+
+/* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */
+#define CH0_EEP          CH[0].EEP
+#define CH0_TEP          CH[0].TEP
+#define CH1_EEP          CH[1].EEP
+#define CH1_TEP          CH[1].TEP
+#define CH2_EEP          CH[2].EEP
+#define CH2_TEP          CH[2].TEP
+#define CH3_EEP          CH[3].EEP
+#define CH3_TEP          CH[3].TEP
+#define CH4_EEP          CH[4].EEP
+#define CH4_TEP          CH[4].TEP
+#define CH5_EEP          CH[5].EEP
+#define CH5_TEP          CH[5].TEP
+#define CH6_EEP          CH[6].EEP
+#define CH6_TEP          CH[6].TEP
+#define CH7_EEP          CH[7].EEP
+#define CH7_TEP          CH[7].TEP
+#define CH8_EEP          CH[8].EEP
+#define CH8_TEP          CH[8].TEP
+#define CH9_EEP          CH[9].EEP
+#define CH9_TEP          CH[9].TEP
+#define CH10_EEP         CH[10].EEP
+#define CH10_TEP         CH[10].TEP
+#define CH11_EEP         CH[11].EEP
+#define CH11_TEP         CH[11].TEP
+#define CH12_EEP         CH[12].EEP
+#define CH12_TEP         CH[12].TEP
+#define CH13_EEP         CH[13].EEP
+#define CH13_TEP         CH[13].TEP
+#define CH14_EEP         CH[14].EEP
+#define CH14_TEP         CH[14].TEP
+#define CH15_EEP         CH[15].EEP
+#define CH15_TEP         CH[15].TEP
+
+/* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */
+#define CHG0             CHG[0]
+#define CHG1             CHG[1]
+#define CHG2             CHG[2]
+#define CHG3             CHG[3]
+
+/* All bitfield macros for the CHGx registers therefore changed name. */
+#define PPI_CHG0_CH15_Pos       PPI_CHG_CH15_Pos
+#define PPI_CHG0_CH15_Msk       PPI_CHG_CH15_Msk
+#define PPI_CHG0_CH15_Excluded  PPI_CHG_CH15_Excluded
+#define PPI_CHG0_CH15_Included  PPI_CHG_CH15_Included
+
+#define PPI_CHG0_CH14_Pos       PPI_CHG_CH14_Pos
+#define PPI_CHG0_CH14_Msk       PPI_CHG_CH14_Msk
+#define PPI_CHG0_CH14_Excluded  PPI_CHG_CH14_Excluded
+#define PPI_CHG0_CH14_Included  PPI_CHG_CH14_Included
+
+#define PPI_CHG0_CH13_Pos       PPI_CHG_CH13_Pos
+#define PPI_CHG0_CH13_Msk       PPI_CHG_CH13_Msk
+#define PPI_CHG0_CH13_Excluded  PPI_CHG_CH13_Excluded
+#define PPI_CHG0_CH13_Included  PPI_CHG_CH13_Included
+
+#define PPI_CHG0_CH12_Pos       PPI_CHG_CH12_Pos
+#define PPI_CHG0_CH12_Msk       PPI_CHG_CH12_Msk
+#define PPI_CHG0_CH12_Excluded  PPI_CHG_CH12_Excluded
+#define PPI_CHG0_CH12_Included  PPI_CHG_CH12_Included
+
+#define PPI_CHG0_CH11_Pos       PPI_CHG_CH11_Pos
+#define PPI_CHG0_CH11_Msk       PPI_CHG_CH11_Msk
+#define PPI_CHG0_CH11_Excluded  PPI_CHG_CH11_Excluded
+#define PPI_CHG0_CH11_Included  PPI_CHG_CH11_Included
+
+#define PPI_CHG0_CH10_Pos       PPI_CHG_CH10_Pos
+#define PPI_CHG0_CH10_Msk       PPI_CHG_CH10_Msk
+#define PPI_CHG0_CH10_Excluded  PPI_CHG_CH10_Excluded
+#define PPI_CHG0_CH10_Included  PPI_CHG_CH10_Included
+
+#define PPI_CHG0_CH9_Pos        PPI_CHG_CH9_Pos
+#define PPI_CHG0_CH9_Msk        PPI_CHG_CH9_Msk
+#define PPI_CHG0_CH9_Excluded   PPI_CHG_CH9_Excluded
+#define PPI_CHG0_CH9_Included   PPI_CHG_CH9_Included
+
+#define PPI_CHG0_CH8_Pos        PPI_CHG_CH8_Pos
+#define PPI_CHG0_CH8_Msk        PPI_CHG_CH8_Msk
+#define PPI_CHG0_CH8_Excluded   PPI_CHG_CH8_Excluded
+#define PPI_CHG0_CH8_Included   PPI_CHG_CH8_Included
+
+#define PPI_CHG0_CH7_Pos        PPI_CHG_CH7_Pos
+#define PPI_CHG0_CH7_Msk        PPI_CHG_CH7_Msk
+#define PPI_CHG0_CH7_Excluded   PPI_CHG_CH7_Excluded
+#define PPI_CHG0_CH7_Included   PPI_CHG_CH7_Included
+
+#define PPI_CHG0_CH6_Pos        PPI_CHG_CH6_Pos
+#define PPI_CHG0_CH6_Msk        PPI_CHG_CH6_Msk
+#define PPI_CHG0_CH6_Excluded   PPI_CHG_CH6_Excluded
+#define PPI_CHG0_CH6_Included   PPI_CHG_CH6_Included
+
+#define PPI_CHG0_CH5_Pos        PPI_CHG_CH5_Pos
+#define PPI_CHG0_CH5_Msk        PPI_CHG_CH5_Msk
+#define PPI_CHG0_CH5_Excluded   PPI_CHG_CH5_Excluded
+#define PPI_CHG0_CH5_Included   PPI_CHG_CH5_Included
+
+#define PPI_CHG0_CH4_Pos        PPI_CHG_CH4_Pos
+#define PPI_CHG0_CH4_Msk        PPI_CHG_CH4_Msk
+#define PPI_CHG0_CH4_Excluded   PPI_CHG_CH4_Excluded
+#define PPI_CHG0_CH4_Included   PPI_CHG_CH4_Included
+
+#define PPI_CHG0_CH3_Pos        PPI_CHG_CH3_Pos
+#define PPI_CHG0_CH3_Msk        PPI_CHG_CH3_Msk
+#define PPI_CHG0_CH3_Excluded   PPI_CHG_CH3_Excluded
+#define PPI_CHG0_CH3_Included   PPI_CHG_CH3_Included
+
+#define PPI_CHG0_CH2_Pos        PPI_CHG_CH2_Pos
+#define PPI_CHG0_CH2_Msk        PPI_CHG_CH2_Msk
+#define PPI_CHG0_CH2_Excluded   PPI_CHG_CH2_Excluded
+#define PPI_CHG0_CH2_Included   PPI_CHG_CH2_Included
+
+#define PPI_CHG0_CH1_Pos        PPI_CHG_CH1_Pos
+#define PPI_CHG0_CH1_Msk        PPI_CHG_CH1_Msk
+#define PPI_CHG0_CH1_Excluded   PPI_CHG_CH1_Excluded
+#define PPI_CHG0_CH1_Included   PPI_CHG_CH1_Included
+
+#define PPI_CHG0_CH0_Pos        PPI_CHG_CH0_Pos
+#define PPI_CHG0_CH0_Msk        PPI_CHG_CH0_Msk
+#define PPI_CHG0_CH0_Excluded   PPI_CHG_CH0_Excluded
+#define PPI_CHG0_CH0_Included   PPI_CHG_CH0_Included
+
+#define PPI_CHG1_CH15_Pos       PPI_CHG_CH15_Pos
+#define PPI_CHG1_CH15_Msk       PPI_CHG_CH15_Msk
+#define PPI_CHG1_CH15_Excluded  PPI_CHG_CH15_Excluded
+#define PPI_CHG1_CH15_Included  PPI_CHG_CH15_Included
+
+#define PPI_CHG1_CH14_Pos       PPI_CHG_CH14_Pos
+#define PPI_CHG1_CH14_Msk       PPI_CHG_CH14_Msk
+#define PPI_CHG1_CH14_Excluded  PPI_CHG_CH14_Excluded
+#define PPI_CHG1_CH14_Included  PPI_CHG_CH14_Included
+
+#define PPI_CHG1_CH13_Pos       PPI_CHG_CH13_Pos
+#define PPI_CHG1_CH13_Msk       PPI_CHG_CH13_Msk
+#define PPI_CHG1_CH13_Excluded  PPI_CHG_CH13_Excluded
+#define PPI_CHG1_CH13_Included  PPI_CHG_CH13_Included
+
+#define PPI_CHG1_CH12_Pos       PPI_CHG_CH12_Pos
+#define PPI_CHG1_CH12_Msk       PPI_CHG_CH12_Msk
+#define PPI_CHG1_CH12_Excluded  PPI_CHG_CH12_Excluded
+#define PPI_CHG1_CH12_Included  PPI_CHG_CH12_Included
+
+#define PPI_CHG1_CH11_Pos       PPI_CHG_CH11_Pos
+#define PPI_CHG1_CH11_Msk       PPI_CHG_CH11_Msk
+#define PPI_CHG1_CH11_Excluded  PPI_CHG_CH11_Excluded
+#define PPI_CHG1_CH11_Included  PPI_CHG_CH11_Included
+
+#define PPI_CHG1_CH10_Pos       PPI_CHG_CH10_Pos
+#define PPI_CHG1_CH10_Msk       PPI_CHG_CH10_Msk
+#define PPI_CHG1_CH10_Excluded  PPI_CHG_CH10_Excluded
+#define PPI_CHG1_CH10_Included  PPI_CHG_CH10_Included
+
+#define PPI_CHG1_CH9_Pos        PPI_CHG_CH9_Pos
+#define PPI_CHG1_CH9_Msk        PPI_CHG_CH9_Msk
+#define PPI_CHG1_CH9_Excluded   PPI_CHG_CH9_Excluded
+#define PPI_CHG1_CH9_Included   PPI_CHG_CH9_Included
+
+#define PPI_CHG1_CH8_Pos        PPI_CHG_CH8_Pos
+#define PPI_CHG1_CH8_Msk        PPI_CHG_CH8_Msk
+#define PPI_CHG1_CH8_Excluded   PPI_CHG_CH8_Excluded
+#define PPI_CHG1_CH8_Included   PPI_CHG_CH8_Included
+
+#define PPI_CHG1_CH7_Pos        PPI_CHG_CH7_Pos
+#define PPI_CHG1_CH7_Msk        PPI_CHG_CH7_Msk
+#define PPI_CHG1_CH7_Excluded   PPI_CHG_CH7_Excluded
+#define PPI_CHG1_CH7_Included   PPI_CHG_CH7_Included
+
+#define PPI_CHG1_CH6_Pos        PPI_CHG_CH6_Pos
+#define PPI_CHG1_CH6_Msk        PPI_CHG_CH6_Msk
+#define PPI_CHG1_CH6_Excluded   PPI_CHG_CH6_Excluded
+#define PPI_CHG1_CH6_Included   PPI_CHG_CH6_Included
+
+#define PPI_CHG1_CH5_Pos        PPI_CHG_CH5_Pos
+#define PPI_CHG1_CH5_Msk        PPI_CHG_CH5_Msk
+#define PPI_CHG1_CH5_Excluded   PPI_CHG_CH5_Excluded
+#define PPI_CHG1_CH5_Included   PPI_CHG_CH5_Included
+
+#define PPI_CHG1_CH4_Pos        PPI_CHG_CH4_Pos
+#define PPI_CHG1_CH4_Msk        PPI_CHG_CH4_Msk
+#define PPI_CHG1_CH4_Excluded   PPI_CHG_CH4_Excluded
+#define PPI_CHG1_CH4_Included   PPI_CHG_CH4_Included
+
+#define PPI_CHG1_CH3_Pos        PPI_CHG_CH3_Pos
+#define PPI_CHG1_CH3_Msk        PPI_CHG_CH3_Msk
+#define PPI_CHG1_CH3_Excluded   PPI_CHG_CH3_Excluded
+#define PPI_CHG1_CH3_Included   PPI_CHG_CH3_Included
+
+#define PPI_CHG1_CH2_Pos        PPI_CHG_CH2_Pos
+#define PPI_CHG1_CH2_Msk        PPI_CHG_CH2_Msk
+#define PPI_CHG1_CH2_Excluded   PPI_CHG_CH2_Excluded
+#define PPI_CHG1_CH2_Included   PPI_CHG_CH2_Included
+
+#define PPI_CHG1_CH1_Pos        PPI_CHG_CH1_Pos
+#define PPI_CHG1_CH1_Msk        PPI_CHG_CH1_Msk
+#define PPI_CHG1_CH1_Excluded   PPI_CHG_CH1_Excluded
+#define PPI_CHG1_CH1_Included   PPI_CHG_CH1_Included
+
+#define PPI_CHG1_CH0_Pos        PPI_CHG_CH0_Pos
+#define PPI_CHG1_CH0_Msk        PPI_CHG_CH0_Msk
+#define PPI_CHG1_CH0_Excluded   PPI_CHG_CH0_Excluded
+#define PPI_CHG1_CH0_Included   PPI_CHG_CH0_Included
+
+#define PPI_CHG2_CH15_Pos       PPI_CHG_CH15_Pos
+#define PPI_CHG2_CH15_Msk       PPI_CHG_CH15_Msk
+#define PPI_CHG2_CH15_Excluded  PPI_CHG_CH15_Excluded
+#define PPI_CHG2_CH15_Included  PPI_CHG_CH15_Included
+
+#define PPI_CHG2_CH14_Pos       PPI_CHG_CH14_Pos
+#define PPI_CHG2_CH14_Msk       PPI_CHG_CH14_Msk
+#define PPI_CHG2_CH14_Excluded  PPI_CHG_CH14_Excluded
+#define PPI_CHG2_CH14_Included  PPI_CHG_CH14_Included
+
+#define PPI_CHG2_CH13_Pos       PPI_CHG_CH13_Pos
+#define PPI_CHG2_CH13_Msk       PPI_CHG_CH13_Msk
+#define PPI_CHG2_CH13_Excluded  PPI_CHG_CH13_Excluded
+#define PPI_CHG2_CH13_Included  PPI_CHG_CH13_Included
+
+#define PPI_CHG2_CH12_Pos       PPI_CHG_CH12_Pos
+#define PPI_CHG2_CH12_Msk       PPI_CHG_CH12_Msk
+#define PPI_CHG2_CH12_Excluded  PPI_CHG_CH12_Excluded
+#define PPI_CHG2_CH12_Included  PPI_CHG_CH12_Included
+
+#define PPI_CHG2_CH11_Pos       PPI_CHG_CH11_Pos
+#define PPI_CHG2_CH11_Msk       PPI_CHG_CH11_Msk
+#define PPI_CHG2_CH11_Excluded  PPI_CHG_CH11_Excluded
+#define PPI_CHG2_CH11_Included  PPI_CHG_CH11_Included
+
+#define PPI_CHG2_CH10_Pos       PPI_CHG_CH10_Pos
+#define PPI_CHG2_CH10_Msk       PPI_CHG_CH10_Msk
+#define PPI_CHG2_CH10_Excluded  PPI_CHG_CH10_Excluded
+#define PPI_CHG2_CH10_Included  PPI_CHG_CH10_Included
+
+#define PPI_CHG2_CH9_Pos        PPI_CHG_CH9_Pos
+#define PPI_CHG2_CH9_Msk        PPI_CHG_CH9_Msk
+#define PPI_CHG2_CH9_Excluded   PPI_CHG_CH9_Excluded
+#define PPI_CHG2_CH9_Included   PPI_CHG_CH9_Included
+
+#define PPI_CHG2_CH8_Pos        PPI_CHG_CH8_Pos
+#define PPI_CHG2_CH8_Msk        PPI_CHG_CH8_Msk
+#define PPI_CHG2_CH8_Excluded   PPI_CHG_CH8_Excluded
+#define PPI_CHG2_CH8_Included   PPI_CHG_CH8_Included
+
+#define PPI_CHG2_CH7_Pos        PPI_CHG_CH7_Pos
+#define PPI_CHG2_CH7_Msk        PPI_CHG_CH7_Msk
+#define PPI_CHG2_CH7_Excluded   PPI_CHG_CH7_Excluded
+#define PPI_CHG2_CH7_Included   PPI_CHG_CH7_Included
+
+#define PPI_CHG2_CH6_Pos        PPI_CHG_CH6_Pos
+#define PPI_CHG2_CH6_Msk        PPI_CHG_CH6_Msk
+#define PPI_CHG2_CH6_Excluded   PPI_CHG_CH6_Excluded
+#define PPI_CHG2_CH6_Included   PPI_CHG_CH6_Included
+
+#define PPI_CHG2_CH5_Pos        PPI_CHG_CH5_Pos
+#define PPI_CHG2_CH5_Msk        PPI_CHG_CH5_Msk
+#define PPI_CHG2_CH5_Excluded   PPI_CHG_CH5_Excluded
+#define PPI_CHG2_CH5_Included   PPI_CHG_CH5_Included
+
+#define PPI_CHG2_CH4_Pos        PPI_CHG_CH4_Pos
+#define PPI_CHG2_CH4_Msk        PPI_CHG_CH4_Msk
+#define PPI_CHG2_CH4_Excluded   PPI_CHG_CH4_Excluded
+#define PPI_CHG2_CH4_Included   PPI_CHG_CH4_Included
+
+#define PPI_CHG2_CH3_Pos        PPI_CHG_CH3_Pos
+#define PPI_CHG2_CH3_Msk        PPI_CHG_CH3_Msk
+#define PPI_CHG2_CH3_Excluded   PPI_CHG_CH3_Excluded
+#define PPI_CHG2_CH3_Included   PPI_CHG_CH3_Included
+
+#define PPI_CHG2_CH2_Pos        PPI_CHG_CH2_Pos
+#define PPI_CHG2_CH2_Msk        PPI_CHG_CH2_Msk
+#define PPI_CHG2_CH2_Excluded   PPI_CHG_CH2_Excluded
+#define PPI_CHG2_CH2_Included   PPI_CHG_CH2_Included
+
+#define PPI_CHG2_CH1_Pos        PPI_CHG_CH1_Pos
+#define PPI_CHG2_CH1_Msk        PPI_CHG_CH1_Msk
+#define PPI_CHG2_CH1_Excluded   PPI_CHG_CH1_Excluded
+#define PPI_CHG2_CH1_Included   PPI_CHG_CH1_Included
+
+#define PPI_CHG2_CH0_Pos        PPI_CHG_CH0_Pos
+#define PPI_CHG2_CH0_Msk        PPI_CHG_CH0_Msk
+#define PPI_CHG2_CH0_Excluded   PPI_CHG_CH0_Excluded
+#define PPI_CHG2_CH0_Included   PPI_CHG_CH0_Included
+
+#define PPI_CHG3_CH15_Pos       PPI_CHG_CH15_Pos
+#define PPI_CHG3_CH15_Msk       PPI_CHG_CH15_Msk
+#define PPI_CHG3_CH15_Excluded  PPI_CHG_CH15_Excluded
+#define PPI_CHG3_CH15_Included  PPI_CHG_CH15_Included
+
+#define PPI_CHG3_CH14_Pos       PPI_CHG_CH14_Pos
+#define PPI_CHG3_CH14_Msk       PPI_CHG_CH14_Msk
+#define PPI_CHG3_CH14_Excluded  PPI_CHG_CH14_Excluded
+#define PPI_CHG3_CH14_Included  PPI_CHG_CH14_Included
+
+#define PPI_CHG3_CH13_Pos       PPI_CHG_CH13_Pos
+#define PPI_CHG3_CH13_Msk       PPI_CHG_CH13_Msk
+#define PPI_CHG3_CH13_Excluded  PPI_CHG_CH13_Excluded
+#define PPI_CHG3_CH13_Included  PPI_CHG_CH13_Included
+
+#define PPI_CHG3_CH12_Pos       PPI_CHG_CH12_Pos
+#define PPI_CHG3_CH12_Msk       PPI_CHG_CH12_Msk
+#define PPI_CHG3_CH12_Excluded  PPI_CHG_CH12_Excluded
+#define PPI_CHG3_CH12_Included  PPI_CHG_CH12_Included
+
+#define PPI_CHG3_CH11_Pos       PPI_CHG_CH11_Pos
+#define PPI_CHG3_CH11_Msk       PPI_CHG_CH11_Msk
+#define PPI_CHG3_CH11_Excluded  PPI_CHG_CH11_Excluded
+#define PPI_CHG3_CH11_Included  PPI_CHG_CH11_Included
+
+#define PPI_CHG3_CH10_Pos       PPI_CHG_CH10_Pos
+#define PPI_CHG3_CH10_Msk       PPI_CHG_CH10_Msk
+#define PPI_CHG3_CH10_Excluded  PPI_CHG_CH10_Excluded
+#define PPI_CHG3_CH10_Included  PPI_CHG_CH10_Included
+
+#define PPI_CHG3_CH9_Pos        PPI_CHG_CH9_Pos
+#define PPI_CHG3_CH9_Msk        PPI_CHG_CH9_Msk
+#define PPI_CHG3_CH9_Excluded   PPI_CHG_CH9_Excluded
+#define PPI_CHG3_CH9_Included   PPI_CHG_CH9_Included
+
+#define PPI_CHG3_CH8_Pos        PPI_CHG_CH8_Pos
+#define PPI_CHG3_CH8_Msk        PPI_CHG_CH8_Msk
+#define PPI_CHG3_CH8_Excluded   PPI_CHG_CH8_Excluded
+#define PPI_CHG3_CH8_Included   PPI_CHG_CH8_Included
+
+#define PPI_CHG3_CH7_Pos        PPI_CHG_CH7_Pos
+#define PPI_CHG3_CH7_Msk        PPI_CHG_CH7_Msk
+#define PPI_CHG3_CH7_Excluded   PPI_CHG_CH7_Excluded
+#define PPI_CHG3_CH7_Included   PPI_CHG_CH7_Included
+
+#define PPI_CHG3_CH6_Pos        PPI_CHG_CH6_Pos
+#define PPI_CHG3_CH6_Msk        PPI_CHG_CH6_Msk
+#define PPI_CHG3_CH6_Excluded   PPI_CHG_CH6_Excluded
+#define PPI_CHG3_CH6_Included   PPI_CHG_CH6_Included
+
+#define PPI_CHG3_CH5_Pos        PPI_CHG_CH5_Pos
+#define PPI_CHG3_CH5_Msk        PPI_CHG_CH5_Msk
+#define PPI_CHG3_CH5_Excluded   PPI_CHG_CH5_Excluded
+#define PPI_CHG3_CH5_Included   PPI_CHG_CH5_Included
+
+#define PPI_CHG3_CH4_Pos        PPI_CHG_CH4_Pos
+#define PPI_CHG3_CH4_Msk        PPI_CHG_CH4_Msk
+#define PPI_CHG3_CH4_Excluded   PPI_CHG_CH4_Excluded
+#define PPI_CHG3_CH4_Included   PPI_CHG_CH4_Included
+
+#define PPI_CHG3_CH3_Pos        PPI_CHG_CH3_Pos
+#define PPI_CHG3_CH3_Msk        PPI_CHG_CH3_Msk
+#define PPI_CHG3_CH3_Excluded   PPI_CHG_CH3_Excluded
+#define PPI_CHG3_CH3_Included   PPI_CHG_CH3_Included
+
+#define PPI_CHG3_CH2_Pos        PPI_CHG_CH2_Pos
+#define PPI_CHG3_CH2_Msk        PPI_CHG_CH2_Msk
+#define PPI_CHG3_CH2_Excluded   PPI_CHG_CH2_Excluded
+#define PPI_CHG3_CH2_Included   PPI_CHG_CH2_Included
+
+#define PPI_CHG3_CH1_Pos        PPI_CHG_CH1_Pos
+#define PPI_CHG3_CH1_Msk        PPI_CHG_CH1_Msk
+#define PPI_CHG3_CH1_Excluded   PPI_CHG_CH1_Excluded
+#define PPI_CHG3_CH1_Included   PPI_CHG_CH1_Included
+
+#define PPI_CHG3_CH0_Pos        PPI_CHG_CH0_Pos
+#define PPI_CHG3_CH0_Msk        PPI_CHG_CH0_Msk
+#define PPI_CHG3_CH0_Excluded   PPI_CHG_CH0_Excluded
+#define PPI_CHG3_CH0_Included   PPI_CHG_CH0_Included
+
+
+
+
+/*lint --flb "Leave library region" */
+
+#endif /* NRF51_TO_NRF52840_H */
+
diff --git a/ports/nrf/device/nrf52/nrf52.h b/ports/nrf/device/nrf52/nrf52.h
new file mode 100644
index 0000000000..8e0ff0c0b5
--- /dev/null
+++ b/ports/nrf/device/nrf52/nrf52.h
@@ -0,0 +1,2091 @@
+
+/****************************************************************************************************//**
+ * @file     nrf52.h
+ *
+ * @brief    CMSIS Cortex-M4 Peripheral Access Layer Header File for
+ *           nrf52 from Nordic Semiconductor.
+ *
+ * @version  V1
+ * @date     18. November 2016
+ *
+ * @note     Generated with SVDConv V2.81d 
+ *           from CMSIS SVD File 'nrf52.svd' Version 1,
+ *
+ * @par      Copyright (c) 2016, Nordic Semiconductor ASA
+ *           All rights reserved.
+ *           
+ *           Redistribution and use in source and binary forms, with or without
+ *           modification, are permitted provided that the following conditions are met:
+ *           
+ *           * Redistributions of source code must retain the above copyright notice, this
+ *           list of conditions and the following disclaimer.
+ *           
+ *           * Redistributions in binary form must reproduce the above copyright notice,
+ *           this list of conditions and the following disclaimer in the documentation
+ *           and/or other materials provided with the distribution.
+ *           
+ *           * Neither the name of Nordic Semiconductor ASA nor the names of its
+ *           contributors may be used to endorse or promote products derived from
+ *           this software without specific prior written permission.
+ *           
+ *           THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *           AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *           IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *           DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ *           FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *           DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ *           SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ *           CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ *           OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *           OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *           
+ *
+ *******************************************************************************************************/
+
+
+
+/** @addtogroup Nordic Semiconductor
+  * @{
+  */
+
+/** @addtogroup nrf52
+  * @{
+  */
+
+#ifndef NRF52_H
+#define NRF52_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* -------------------------  Interrupt Number Definition  ------------------------ */
+
+typedef enum {
+/* -------------------  Cortex-M4 Processor Exceptions Numbers  ------------------- */
+  Reset_IRQn                    = -15,              /*!<   1  Reset Vector, invoked on Power up and warm reset                 */
+  NonMaskableInt_IRQn           = -14,              /*!<   2  Non maskable Interrupt, cannot be stopped or preempted           */
+  HardFault_IRQn                = -13,              /*!<   3  Hard Fault, all classes of Fault                                 */
+  MemoryManagement_IRQn         = -12,              /*!<   4  Memory Management, MPU mismatch, including Access Violation
+                                                         and No Match                                                          */
+  BusFault_IRQn                 = -11,              /*!<   5  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
+                                                         related Fault                                                         */
+  UsageFault_IRQn               = -10,              /*!<   6  Usage Fault, i.e. Undef Instruction, Illegal State Transition    */
+  SVCall_IRQn                   =  -5,              /*!<  11  System Service Call via SVC instruction                          */
+  DebugMonitor_IRQn             =  -4,              /*!<  12  Debug Monitor                                                    */
+  PendSV_IRQn                   =  -2,              /*!<  14  Pendable request for system service                              */
+  SysTick_IRQn                  =  -1,              /*!<  15  System Tick Timer                                                */
+/* ----------------------  nrf52 Specific Interrupt Numbers  ---------------------- */
+  POWER_CLOCK_IRQn              =   0,              /*!<   0  POWER_CLOCK                                                      */
+  RADIO_IRQn                    =   1,              /*!<   1  RADIO                                                            */
+  UARTE0_UART0_IRQn             =   2,              /*!<   2  UARTE0_UART0                                                     */
+  SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn=   3,      /*!<   3  SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0                                */
+  SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn=   4,      /*!<   4  SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1                                */
+  NFCT_IRQn                     =   5,              /*!<   5  NFCT                                                             */
+  GPIOTE_IRQn                   =   6,              /*!<   6  GPIOTE                                                           */
+  SAADC_IRQn                    =   7,              /*!<   7  SAADC                                                            */
+  TIMER0_IRQn                   =   8,              /*!<   8  TIMER0                                                           */
+  TIMER1_IRQn                   =   9,              /*!<   9  TIMER1                                                           */
+  TIMER2_IRQn                   =  10,              /*!<  10  TIMER2                                                           */
+  RTC0_IRQn                     =  11,              /*!<  11  RTC0                                                             */
+  TEMP_IRQn                     =  12,              /*!<  12  TEMP                                                             */
+  RNG_IRQn                      =  13,              /*!<  13  RNG                                                              */
+  ECB_IRQn                      =  14,              /*!<  14  ECB                                                              */
+  CCM_AAR_IRQn                  =  15,              /*!<  15  CCM_AAR                                                          */
+  WDT_IRQn                      =  16,              /*!<  16  WDT                                                              */
+  RTC1_IRQn                     =  17,              /*!<  17  RTC1                                                             */
+  QDEC_IRQn                     =  18,              /*!<  18  QDEC                                                             */
+  COMP_LPCOMP_IRQn              =  19,              /*!<  19  COMP_LPCOMP                                                      */
+  SWI0_EGU0_IRQn                =  20,              /*!<  20  SWI0_EGU0                                                        */
+  SWI1_EGU1_IRQn                =  21,              /*!<  21  SWI1_EGU1                                                        */
+  SWI2_EGU2_IRQn                =  22,              /*!<  22  SWI2_EGU2                                                        */
+  SWI3_EGU3_IRQn                =  23,              /*!<  23  SWI3_EGU3                                                        */
+  SWI4_EGU4_IRQn                =  24,              /*!<  24  SWI4_EGU4                                                        */
+  SWI5_EGU5_IRQn                =  25,              /*!<  25  SWI5_EGU5                                                        */
+  TIMER3_IRQn                   =  26,              /*!<  26  TIMER3                                                           */
+  TIMER4_IRQn                   =  27,              /*!<  27  TIMER4                                                           */
+  PWM0_IRQn                     =  28,              /*!<  28  PWM0                                                             */
+  PDM_IRQn                      =  29,              /*!<  29  PDM                                                              */
+  MWU_IRQn                      =  32,              /*!<  32  MWU                                                              */
+  PWM1_IRQn                     =  33,              /*!<  33  PWM1                                                             */
+  PWM2_IRQn                     =  34,              /*!<  34  PWM2                                                             */
+  SPIM2_SPIS2_SPI2_IRQn         =  35,              /*!<  35  SPIM2_SPIS2_SPI2                                                 */
+  RTC2_IRQn                     =  36,              /*!<  36  RTC2                                                             */
+  I2S_IRQn                      =  37,              /*!<  37  I2S                                                              */
+  FPU_IRQn                      =  38               /*!<  38  FPU                                                              */
+} IRQn_Type;
+
+
+/** @addtogroup Configuration_of_CMSIS
+  * @{
+  */
+
+
+/* ================================================================================ */
+/* ================      Processor and Core Peripheral Section     ================ */
+/* ================================================================================ */
+
+/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */
+#define __CM4_REV                 0x0001            /*!< Cortex-M4 Core Revision                                               */
+#define __MPU_PRESENT                  1            /*!< MPU present or not                                                    */
+#define __NVIC_PRIO_BITS               3            /*!< Number of Bits used for Priority Levels                               */
+#define __Vendor_SysTickConfig         0            /*!< Set to 1 if different SysTick Config is used                          */
+#define __FPU_PRESENT                  1            /*!< FPU present or not                                                    */
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include "core_cm4.h"                               /*!< Cortex-M4 processor and core peripherals                              */
+#include "system_nrf52.h"                           /*!< nrf52 System                                                          */
+
+
+/* ================================================================================ */
+/* ================       Device Specific Peripheral Section       ================ */
+/* ================================================================================ */
+
+
+/** @addtogroup Device_Peripheral_Registers
+  * @{
+  */
+
+
+/* -------------------  Start of section using anonymous unions  ------------------ */
+#if defined(__CC_ARM)
+  #pragma push
+  #pragma anon_unions
+#elif defined(__ICCARM__)
+  #pragma language=extended
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+/* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+  #pragma warning 586
+#else
+  #warning Not supported compiler type
+#endif
+
+
+typedef struct {
+  __I  uint32_t  PART;                              /*!< Part code                                                             */
+  __I  uint32_t  VARIANT;                           /*!< Part Variant, Hardware version and Production configuration           */
+  __I  uint32_t  PACKAGE;                           /*!< Package option                                                        */
+  __I  uint32_t  RAM;                               /*!< RAM variant                                                           */
+  __I  uint32_t  FLASH;                             /*!< Flash variant                                                         */
+  __IO uint32_t  UNUSED0[3];                        /*!< Description collection[0]: Unspecified                                */
+} FICR_INFO_Type;
+
+typedef struct {
+  __I  uint32_t  A0;                                /*!< Slope definition A0.                                                  */
+  __I  uint32_t  A1;                                /*!< Slope definition A1.                                                  */
+  __I  uint32_t  A2;                                /*!< Slope definition A2.                                                  */
+  __I  uint32_t  A3;                                /*!< Slope definition A3.                                                  */
+  __I  uint32_t  A4;                                /*!< Slope definition A4.                                                  */
+  __I  uint32_t  A5;                                /*!< Slope definition A5.                                                  */
+  __I  uint32_t  B0;                                /*!< y-intercept B0.                                                       */
+  __I  uint32_t  B1;                                /*!< y-intercept B1.                                                       */
+  __I  uint32_t  B2;                                /*!< y-intercept B2.                                                       */
+  __I  uint32_t  B3;                                /*!< y-intercept B3.                                                       */
+  __I  uint32_t  B4;                                /*!< y-intercept B4.                                                       */
+  __I  uint32_t  B5;                                /*!< y-intercept B5.                                                       */
+  __I  uint32_t  T0;                                /*!< Segment end T0.                                                       */
+  __I  uint32_t  T1;                                /*!< Segment end T1.                                                       */
+  __I  uint32_t  T2;                                /*!< Segment end T2.                                                       */
+  __I  uint32_t  T3;                                /*!< Segment end T3.                                                       */
+  __I  uint32_t  T4;                                /*!< Segment end T4.                                                       */
+} FICR_TEMP_Type;
+
+typedef struct {
+  __I  uint32_t  TAGHEADER0;                        /*!< Default header for NFC Tag. Software can read these values to
+                                                         populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.            */
+  __I  uint32_t  TAGHEADER1;                        /*!< Default header for NFC Tag. Software can read these values to
+                                                         populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.            */
+  __I  uint32_t  TAGHEADER2;                        /*!< Default header for NFC Tag. Software can read these values to
+                                                         populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.            */
+  __I  uint32_t  TAGHEADER3;                        /*!< Default header for NFC Tag. Software can read these values to
+                                                         populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.            */
+} FICR_NFC_Type;
+
+typedef struct {
+  __IO uint32_t  POWER;                             /*!< Description cluster[0]: RAM0 power control register                   */
+  __O  uint32_t  POWERSET;                          /*!< Description cluster[0]: RAM0 power control set register               */
+  __O  uint32_t  POWERCLR;                          /*!< Description cluster[0]: RAM0 power control clear register             */
+  __I  uint32_t  RESERVED0;
+} POWER_RAM_Type;
+
+typedef struct {
+  __IO uint32_t  RTS;                               /*!< Pin select for RTS signal                                             */
+  __IO uint32_t  TXD;                               /*!< Pin select for TXD signal                                             */
+  __IO uint32_t  CTS;                               /*!< Pin select for CTS signal                                             */
+  __IO uint32_t  RXD;                               /*!< Pin select for RXD signal                                             */
+} UARTE_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in receive buffer                             */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */
+} UARTE_RXD_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in transmit buffer                            */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */
+} UARTE_TXD_Type;
+
+typedef struct {
+  __IO uint32_t  SCK;                               /*!< Pin select for SCK                                                    */
+  __IO uint32_t  MOSI;                              /*!< Pin select for MOSI signal                                            */
+  __IO uint32_t  MISO;                              /*!< Pin select for MISO signal                                            */
+} SPIM_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in receive buffer                             */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */
+  __IO uint32_t  LIST;                              /*!< EasyDMA list type                                                     */
+} SPIM_RXD_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in transmit buffer                            */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */
+  __IO uint32_t  LIST;                              /*!< EasyDMA list type                                                     */
+} SPIM_TXD_Type;
+
+typedef struct {
+  __IO uint32_t  SCK;                               /*!< Pin select for SCK                                                    */
+  __IO uint32_t  MISO;                              /*!< Pin select for MISO signal                                            */
+  __IO uint32_t  MOSI;                              /*!< Pin select for MOSI signal                                            */
+  __IO uint32_t  CSN;                               /*!< Pin select for CSN signal                                             */
+} SPIS_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< RXD data pointer                                                      */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in receive buffer                             */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes received in last granted transaction                  */
+} SPIS_RXD_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< TXD data pointer                                                      */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in transmit buffer                            */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transmitted in last granted transaction               */
+} SPIS_TXD_Type;
+
+typedef struct {
+  __IO uint32_t  SCL;                               /*!< Pin select for SCL signal                                             */
+  __IO uint32_t  SDA;                               /*!< Pin select for SDA signal                                             */
+} TWIM_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in receive buffer                             */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */
+  __IO uint32_t  LIST;                              /*!< EasyDMA list type                                                     */
+} TWIM_RXD_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in transmit buffer                            */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */
+  __IO uint32_t  LIST;                              /*!< EasyDMA list type                                                     */
+} TWIM_TXD_Type;
+
+typedef struct {
+  __IO uint32_t  SCL;                               /*!< Pin select for SCL signal                                             */
+  __IO uint32_t  SDA;                               /*!< Pin select for SDA signal                                             */
+} TWIS_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< RXD Data pointer                                                      */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in RXD buffer                                 */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last RXD transaction               */
+} TWIS_RXD_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< TXD Data pointer                                                      */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in TXD buffer                                 */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last TXD transaction               */
+} TWIS_TXD_Type;
+
+typedef struct {
+  __IO uint32_t  SCK;                               /*!< Pin select for SCK                                                    */
+  __IO uint32_t  MOSI;                              /*!< Pin select for MOSI                                                   */
+  __IO uint32_t  MISO;                              /*!< Pin select for MISO                                                   */
+} SPI_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  RX;                                /*!< Result of last incoming frames                                        */
+} NFCT_FRAMESTATUS_Type;
+
+typedef struct {
+  __IO uint32_t  FRAMECONFIG;                       /*!< Configuration of outgoing frames                                      */
+  __IO uint32_t  AMOUNT;                            /*!< Size of outgoing frame                                                */
+} NFCT_TXD_Type;
+
+typedef struct {
+  __IO uint32_t  FRAMECONFIG;                       /*!< Configuration of incoming frames                                      */
+  __I  uint32_t  AMOUNT;                            /*!< Size of last incoming frame                                           */
+} NFCT_RXD_Type;
+
+typedef struct {
+  __IO uint32_t  LIMITH;                            /*!< Description cluster[0]: Last results is equal or above CH[0].LIMIT.HIGH */
+  __IO uint32_t  LIMITL;                            /*!< Description cluster[0]: Last results is equal or below CH[0].LIMIT.LOW */
+} SAADC_EVENTS_CH_Type;
+
+typedef struct {
+  __IO uint32_t  PSELP;                             /*!< Description cluster[0]: Input positive pin selection for CH[0]        */
+  __IO uint32_t  PSELN;                             /*!< Description cluster[0]: Input negative pin selection for CH[0]        */
+  __IO uint32_t  CONFIG;                            /*!< Description cluster[0]: Input configuration for CH[0]                 */
+  __IO uint32_t  LIMIT;                             /*!< Description cluster[0]: High/low limits for event monitoring
+                                                         a channel                                                             */
+} SAADC_CH_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of buffer words to transfer                            */
+  __I  uint32_t  AMOUNT;                            /*!< Number of buffer words transferred since last START                   */
+} SAADC_RESULT_Type;
+
+typedef struct {
+  __IO uint32_t  LED;                               /*!< Pin select for LED signal                                             */
+  __IO uint32_t  A;                                 /*!< Pin select for A signal                                               */
+  __IO uint32_t  B;                                 /*!< Pin select for B signal                                               */
+} QDEC_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Description cluster[0]: Beginning address in Data RAM of this
+                                                         sequence                                                              */
+  __IO uint32_t  CNT;                               /*!< Description cluster[0]: Amount of values (duty cycles) in this
+                                                         sequence                                                              */
+  __IO uint32_t  REFRESH;                           /*!< Description cluster[0]: Amount of additional PWM periods between
+                                                         samples loaded into compare register                                  */
+  __IO uint32_t  ENDDELAY;                          /*!< Description cluster[0]: Time added after the sequence                 */
+  __I  uint32_t  RESERVED1[4];
+} PWM_SEQ_Type;
+
+typedef struct {
+  __IO uint32_t  OUT[4];                            /*!< Description collection[0]: Output pin select for PWM channel
+                                                         0                                                                     */
+} PWM_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  CLK;                               /*!< Pin number configuration for PDM CLK signal                           */
+  __IO uint32_t  DIN;                               /*!< Pin number configuration for PDM DIN signal                           */
+} PDM_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< RAM address pointer to write samples to with EasyDMA                  */
+  __IO uint32_t  MAXCNT;                            /*!< Number of samples to allocate memory for in EasyDMA mode              */
+} PDM_SAMPLE_Type;
+
+typedef struct {
+  __O  uint32_t  EN;                                /*!< Description cluster[0]: Enable channel group 0                        */
+  __O  uint32_t  DIS;                               /*!< Description cluster[0]: Disable channel group 0                       */
+} PPI_TASKS_CHG_Type;
+
+typedef struct {
+  __IO uint32_t  EEP;                               /*!< Description cluster[0]: Channel 0 event end-point                     */
+  __IO uint32_t  TEP;                               /*!< Description cluster[0]: Channel 0 task end-point                      */
+} PPI_CH_Type;
+
+typedef struct {
+  __IO uint32_t  TEP;                               /*!< Description cluster[0]: Channel 0 task end-point                      */
+} PPI_FORK_Type;
+
+typedef struct {
+  __IO uint32_t  WA;                                /*!< Description cluster[0]: Write access to region 0 detected             */
+  __IO uint32_t  RA;                                /*!< Description cluster[0]: Read access to region 0 detected              */
+} MWU_EVENTS_REGION_Type;
+
+typedef struct {
+  __IO uint32_t  WA;                                /*!< Description cluster[0]: Write access to peripheral region 0
+                                                         detected                                                              */
+  __IO uint32_t  RA;                                /*!< Description cluster[0]: Read access to peripheral region 0 detected   */
+} MWU_EVENTS_PREGION_Type;
+
+typedef struct {
+  __IO uint32_t  SUBSTATWA;                         /*!< Description cluster[0]: Source of event/interrupt in region
+                                                         0, write access detected while corresponding subregion was enabled
+                                                          for watching                                                         */
+  __IO uint32_t  SUBSTATRA;                         /*!< Description cluster[0]: Source of event/interrupt in region
+                                                         0, read access detected while corresponding subregion was enabled
+                                                          for watching                                                         */
+} MWU_PERREGION_Type;
+
+typedef struct {
+  __IO uint32_t  START;                             /*!< Description cluster[0]: Start address for region 0                    */
+  __IO uint32_t  END;                               /*!< Description cluster[0]: End address of region 0                       */
+  __I  uint32_t  RESERVED2[2];
+} MWU_REGION_Type;
+
+typedef struct {
+  __I  uint32_t  START;                             /*!< Description cluster[0]: Reserved for future use                       */
+  __I  uint32_t  END;                               /*!< Description cluster[0]: Reserved for future use                       */
+  __IO uint32_t  SUBS;                              /*!< Description cluster[0]: Subregions of region 0                        */
+  __I  uint32_t  RESERVED3;
+} MWU_PREGION_Type;
+
+typedef struct {
+  __IO uint32_t  MODE;                              /*!< I2S mode.                                                             */
+  __IO uint32_t  RXEN;                              /*!< Reception (RX) enable.                                                */
+  __IO uint32_t  TXEN;                              /*!< Transmission (TX) enable.                                             */
+  __IO uint32_t  MCKEN;                             /*!< Master clock generator enable.                                        */
+  __IO uint32_t  MCKFREQ;                           /*!< Master clock generator frequency.                                     */
+  __IO uint32_t  RATIO;                             /*!< MCK / LRCK ratio.                                                     */
+  __IO uint32_t  SWIDTH;                            /*!< Sample width.                                                         */
+  __IO uint32_t  ALIGN;                             /*!< Alignment of sample within a frame.                                   */
+  __IO uint32_t  FORMAT;                            /*!< Frame format.                                                         */
+  __IO uint32_t  CHANNELS;                          /*!< Enable channels.                                                      */
+} I2S_CONFIG_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Receive buffer RAM start address.                                     */
+} I2S_RXD_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Transmit buffer RAM start address.                                    */
+} I2S_TXD_Type;
+
+typedef struct {
+  __IO uint32_t  MAXCNT;                            /*!< Size of RXD and TXD buffers.                                          */
+} I2S_RXTXD_Type;
+
+typedef struct {
+  __IO uint32_t  MCK;                               /*!< Pin select for MCK signal.                                            */
+  __IO uint32_t  SCK;                               /*!< Pin select for SCK signal.                                            */
+  __IO uint32_t  LRCK;                              /*!< Pin select for LRCK signal.                                           */
+  __IO uint32_t  SDIN;                              /*!< Pin select for SDIN signal.                                           */
+  __IO uint32_t  SDOUT;                             /*!< Pin select for SDOUT signal.                                          */
+} I2S_PSEL_Type;
+
+
+/* ================================================================================ */
+/* ================                      FICR                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Factory Information Configuration Registers (FICR)
+  */
+
+typedef struct {                                    /*!< FICR Structure                                                        */
+  __I  uint32_t  RESERVED0[4];
+  __I  uint32_t  CODEPAGESIZE;                      /*!< Code memory page size                                                 */
+  __I  uint32_t  CODESIZE;                          /*!< Code memory size                                                      */
+  __I  uint32_t  RESERVED1[18];
+  __I  uint32_t  DEVICEID[2];                       /*!< Description collection[0]: Device identifier                          */
+  __I  uint32_t  RESERVED2[6];
+  __I  uint32_t  ER[4];                             /*!< Description collection[0]: Encryption Root, word 0                    */
+  __I  uint32_t  IR[4];                             /*!< Description collection[0]: Identity Root, word 0                      */
+  __I  uint32_t  DEVICEADDRTYPE;                    /*!< Device address type                                                   */
+  __I  uint32_t  DEVICEADDR[2];                     /*!< Description collection[0]: Device address 0                           */
+  __I  uint32_t  RESERVED3[21];
+  FICR_INFO_Type INFO;                              /*!< Device info                                                           */
+  __I  uint32_t  RESERVED4[185];
+  FICR_TEMP_Type TEMP;                              /*!< Registers storing factory TEMP module linearization coefficients      */
+  __I  uint32_t  RESERVED5[2];
+  FICR_NFC_Type NFC;                                /*!< Unspecified                                                           */
+} NRF_FICR_Type;
+
+
+/* ================================================================================ */
+/* ================                      UICR                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief User Information Configuration Registers (UICR)
+  */
+
+typedef struct {                                    /*!< UICR Structure                                                        */
+  __IO uint32_t  UNUSED0;                           /*!< Unspecified                                                           */
+  __IO uint32_t  UNUSED1;                           /*!< Unspecified                                                           */
+  __IO uint32_t  UNUSED2;                           /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED0;
+  __IO uint32_t  UNUSED3;                           /*!< Unspecified                                                           */
+  __IO uint32_t  NRFFW[15];                         /*!< Description collection[0]: Reserved for Nordic firmware design        */
+  __IO uint32_t  NRFHW[12];                         /*!< Description collection[0]: Reserved for Nordic hardware design        */
+  __IO uint32_t  CUSTOMER[32];                      /*!< Description collection[0]: Reserved for customer                      */
+  __I  uint32_t  RESERVED1[64];
+  __IO uint32_t  PSELRESET[2];                      /*!< Description collection[0]: Mapping of the nRESET function (see
+                                                         POWER chapter for details)                                            */
+  __IO uint32_t  APPROTECT;                         /*!< Access Port protection                                                */
+  __IO uint32_t  NFCPINS;                           /*!< Setting of pins dedicated to NFC functionality: NFC antenna
+                                                         or GPIO                                                               */
+} NRF_UICR_Type;
+
+
+/* ================================================================================ */
+/* ================                      BPROT                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Block Protect (BPROT)
+  */
+
+typedef struct {                                    /*!< BPROT Structure                                                       */
+  __I  uint32_t  RESERVED0[384];
+  __IO uint32_t  CONFIG0;                           /*!< Block protect configuration register 0                                */
+  __IO uint32_t  CONFIG1;                           /*!< Block protect configuration register 1                                */
+  __IO uint32_t  DISABLEINDEBUG;                    /*!< Disable protection mechanism in debug interface mode                  */
+  __IO uint32_t  UNUSED0;                           /*!< Unspecified                                                           */
+  __IO uint32_t  CONFIG2;                           /*!< Block protect configuration register 2                                */
+  __IO uint32_t  CONFIG3;                           /*!< Block protect configuration register 3                                */
+} NRF_BPROT_Type;
+
+
+/* ================================================================================ */
+/* ================                      POWER                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Power control (POWER)
+  */
+
+typedef struct {                                    /*!< POWER Structure                                                       */
+  __I  uint32_t  RESERVED0[30];
+  __O  uint32_t  TASKS_CONSTLAT;                    /*!< Enable constant latency mode                                          */
+  __O  uint32_t  TASKS_LOWPWR;                      /*!< Enable low power mode (variable latency)                              */
+  __I  uint32_t  RESERVED1[34];
+  __IO uint32_t  EVENTS_POFWARN;                    /*!< Power failure warning                                                 */
+  __I  uint32_t  RESERVED2[2];
+  __IO uint32_t  EVENTS_SLEEPENTER;                 /*!< CPU entered WFI/WFE sleep                                             */
+  __IO uint32_t  EVENTS_SLEEPEXIT;                  /*!< CPU exited WFI/WFE sleep                                              */
+  __I  uint32_t  RESERVED3[122];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED4[61];
+  __IO uint32_t  RESETREAS;                         /*!< Reset reason                                                          */
+  __I  uint32_t  RESERVED5[9];
+  __I  uint32_t  RAMSTATUS;                         /*!< Deprecated register - RAM status register                             */
+  __I  uint32_t  RESERVED6[53];
+  __O  uint32_t  SYSTEMOFF;                         /*!< System OFF register                                                   */
+  __I  uint32_t  RESERVED7[3];
+  __IO uint32_t  POFCON;                            /*!< Power failure comparator configuration                                */
+  __I  uint32_t  RESERVED8[2];
+  __IO uint32_t  GPREGRET;                          /*!< General purpose retention register                                    */
+  __IO uint32_t  GPREGRET2;                         /*!< General purpose retention register                                    */
+  __IO uint32_t  RAMON;                             /*!< Deprecated register - RAM on/off register (this register is
+                                                         retained)                                                             */
+  __I  uint32_t  RESERVED9[11];
+  __IO uint32_t  RAMONB;                            /*!< Deprecated register - RAM on/off register (this register is
+                                                         retained)                                                             */
+  __I  uint32_t  RESERVED10[8];
+  __IO uint32_t  DCDCEN;                            /*!< DC/DC enable register                                                 */
+  __I  uint32_t  RESERVED11[225];
+  POWER_RAM_Type RAM[8];                            /*!< Unspecified                                                           */
+} NRF_POWER_Type;
+
+
+/* ================================================================================ */
+/* ================                      CLOCK                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Clock control (CLOCK)
+  */
+
+typedef struct {                                    /*!< CLOCK Structure                                                       */
+  __O  uint32_t  TASKS_HFCLKSTART;                  /*!< Start HFCLK crystal oscillator                                        */
+  __O  uint32_t  TASKS_HFCLKSTOP;                   /*!< Stop HFCLK crystal oscillator                                         */
+  __O  uint32_t  TASKS_LFCLKSTART;                  /*!< Start LFCLK source                                                    */
+  __O  uint32_t  TASKS_LFCLKSTOP;                   /*!< Stop LFCLK source                                                     */
+  __O  uint32_t  TASKS_CAL;                         /*!< Start calibration of LFRC oscillator                                  */
+  __O  uint32_t  TASKS_CTSTART;                     /*!< Start calibration timer                                               */
+  __O  uint32_t  TASKS_CTSTOP;                      /*!< Stop calibration timer                                                */
+  __I  uint32_t  RESERVED0[57];
+  __IO uint32_t  EVENTS_HFCLKSTARTED;               /*!< HFCLK oscillator started                                              */
+  __IO uint32_t  EVENTS_LFCLKSTARTED;               /*!< LFCLK started                                                         */
+  __I  uint32_t  RESERVED1;
+  __IO uint32_t  EVENTS_DONE;                       /*!< Calibration of LFCLK RC oscillator complete event                     */
+  __IO uint32_t  EVENTS_CTTO;                       /*!< Calibration timer timeout                                             */
+  __I  uint32_t  RESERVED2[124];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[63];
+  __I  uint32_t  HFCLKRUN;                          /*!< Status indicating that HFCLKSTART task has been triggered             */
+  __I  uint32_t  HFCLKSTAT;                         /*!< HFCLK status                                                          */
+  __I  uint32_t  RESERVED4;
+  __I  uint32_t  LFCLKRUN;                          /*!< Status indicating that LFCLKSTART task has been triggered             */
+  __I  uint32_t  LFCLKSTAT;                         /*!< LFCLK status                                                          */
+  __I  uint32_t  LFCLKSRCCOPY;                      /*!< Copy of LFCLKSRC register, set when LFCLKSTART task was triggered     */
+  __I  uint32_t  RESERVED5[62];
+  __IO uint32_t  LFCLKSRC;                          /*!< Clock source for the LFCLK                                            */
+  __I  uint32_t  RESERVED6[7];
+  __IO uint32_t  CTIV;                              /*!< Calibration timer interval                                            */
+  __I  uint32_t  RESERVED7[8];
+  __IO uint32_t  TRACECONFIG;                       /*!< Clocking options for the Trace Port debug interface                   */
+} NRF_CLOCK_Type;
+
+
+/* ================================================================================ */
+/* ================                      RADIO                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief 2.4 GHz Radio (RADIO)
+  */
+
+typedef struct {                                    /*!< RADIO Structure                                                       */
+  __O  uint32_t  TASKS_TXEN;                        /*!< Enable RADIO in TX mode                                               */
+  __O  uint32_t  TASKS_RXEN;                        /*!< Enable RADIO in RX mode                                               */
+  __O  uint32_t  TASKS_START;                       /*!< Start RADIO                                                           */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop RADIO                                                            */
+  __O  uint32_t  TASKS_DISABLE;                     /*!< Disable RADIO                                                         */
+  __O  uint32_t  TASKS_RSSISTART;                   /*!< Start the RSSI and take one single sample of the receive signal
+                                                         strength.                                                             */
+  __O  uint32_t  TASKS_RSSISTOP;                    /*!< Stop the RSSI measurement                                             */
+  __O  uint32_t  TASKS_BCSTART;                     /*!< Start the bit counter                                                 */
+  __O  uint32_t  TASKS_BCSTOP;                      /*!< Stop the bit counter                                                  */
+  __I  uint32_t  RESERVED0[55];
+  __IO uint32_t  EVENTS_READY;                      /*!< RADIO has ramped up and is ready to be started                        */
+  __IO uint32_t  EVENTS_ADDRESS;                    /*!< Address sent or received                                              */
+  __IO uint32_t  EVENTS_PAYLOAD;                    /*!< Packet payload sent or received                                       */
+  __IO uint32_t  EVENTS_END;                        /*!< Packet sent or received                                               */
+  __IO uint32_t  EVENTS_DISABLED;                   /*!< RADIO has been disabled                                               */
+  __IO uint32_t  EVENTS_DEVMATCH;                   /*!< A device address match occurred on the last received packet           */
+  __IO uint32_t  EVENTS_DEVMISS;                    /*!< No device address match occurred on the last received packet          */
+  __IO uint32_t  EVENTS_RSSIEND;                    /*!< Sampling of receive signal strength complete.                         */
+  __I  uint32_t  RESERVED1[2];
+  __IO uint32_t  EVENTS_BCMATCH;                    /*!< Bit counter reached bit count value.                                  */
+  __I  uint32_t  RESERVED2;
+  __IO uint32_t  EVENTS_CRCOK;                      /*!< Packet received with CRC ok                                           */
+  __IO uint32_t  EVENTS_CRCERROR;                   /*!< Packet received with CRC error                                        */
+  __I  uint32_t  RESERVED3[50];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED4[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED5[61];
+  __I  uint32_t  CRCSTATUS;                         /*!< CRC status                                                            */
+  __I  uint32_t  RESERVED6;
+  __I  uint32_t  RXMATCH;                           /*!< Received address                                                      */
+  __I  uint32_t  RXCRC;                             /*!< CRC field of previously received packet                               */
+  __I  uint32_t  DAI;                               /*!< Device address match index                                            */
+  __I  uint32_t  RESERVED7[60];
+  __IO uint32_t  PACKETPTR;                         /*!< Packet pointer                                                        */
+  __IO uint32_t  FREQUENCY;                         /*!< Frequency                                                             */
+  __IO uint32_t  TXPOWER;                           /*!< Output power                                                          */
+  __IO uint32_t  MODE;                              /*!< Data rate and modulation                                              */
+  __IO uint32_t  PCNF0;                             /*!< Packet configuration register 0                                       */
+  __IO uint32_t  PCNF1;                             /*!< Packet configuration register 1                                       */
+  __IO uint32_t  BASE0;                             /*!< Base address 0                                                        */
+  __IO uint32_t  BASE1;                             /*!< Base address 1                                                        */
+  __IO uint32_t  PREFIX0;                           /*!< Prefixes bytes for logical addresses 0-3                              */
+  __IO uint32_t  PREFIX1;                           /*!< Prefixes bytes for logical addresses 4-7                              */
+  __IO uint32_t  TXADDRESS;                         /*!< Transmit address select                                               */
+  __IO uint32_t  RXADDRESSES;                       /*!< Receive address select                                                */
+  __IO uint32_t  CRCCNF;                            /*!< CRC configuration                                                     */
+  __IO uint32_t  CRCPOLY;                           /*!< CRC polynomial                                                        */
+  __IO uint32_t  CRCINIT;                           /*!< CRC initial value                                                     */
+  __IO uint32_t  UNUSED0;                           /*!< Unspecified                                                           */
+  __IO uint32_t  TIFS;                              /*!< Inter Frame Spacing in us                                             */
+  __I  uint32_t  RSSISAMPLE;                        /*!< RSSI sample                                                           */
+  __I  uint32_t  RESERVED8;
+  __I  uint32_t  STATE;                             /*!< Current radio state                                                   */
+  __IO uint32_t  DATAWHITEIV;                       /*!< Data whitening initial value                                          */
+  __I  uint32_t  RESERVED9[2];
+  __IO uint32_t  BCC;                               /*!< Bit counter compare                                                   */
+  __I  uint32_t  RESERVED10[39];
+  __IO uint32_t  DAB[8];                            /*!< Description collection[0]: Device address base segment 0              */
+  __IO uint32_t  DAP[8];                            /*!< Description collection[0]: Device address prefix 0                    */
+  __IO uint32_t  DACNF;                             /*!< Device address match configuration                                    */
+  __I  uint32_t  RESERVED11[3];
+  __IO uint32_t  MODECNF0;                          /*!< Radio mode configuration register 0                                   */
+  __I  uint32_t  RESERVED12[618];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control                                              */
+} NRF_RADIO_Type;
+
+
+/* ================================================================================ */
+/* ================                      UARTE                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief UART with EasyDMA (UARTE)
+  */
+
+typedef struct {                                    /*!< UARTE Structure                                                       */
+  __O  uint32_t  TASKS_STARTRX;                     /*!< Start UART receiver                                                   */
+  __O  uint32_t  TASKS_STOPRX;                      /*!< Stop UART receiver                                                    */
+  __O  uint32_t  TASKS_STARTTX;                     /*!< Start UART transmitter                                                */
+  __O  uint32_t  TASKS_STOPTX;                      /*!< Stop UART transmitter                                                 */
+  __I  uint32_t  RESERVED0[7];
+  __O  uint32_t  TASKS_FLUSHRX;                     /*!< Flush RX FIFO into RX buffer                                          */
+  __I  uint32_t  RESERVED1[52];
+  __IO uint32_t  EVENTS_CTS;                        /*!< CTS is activated (set low). Clear To Send.                            */
+  __IO uint32_t  EVENTS_NCTS;                       /*!< CTS is deactivated (set high). Not Clear To Send.                     */
+  __IO uint32_t  EVENTS_RXDRDY;                     /*!< Data received in RXD (but potentially not yet transferred to
+                                                         Data RAM)                                                             */
+  __I  uint32_t  RESERVED2;
+  __IO uint32_t  EVENTS_ENDRX;                      /*!< Receive buffer is filled up                                           */
+  __I  uint32_t  RESERVED3[2];
+  __IO uint32_t  EVENTS_TXDRDY;                     /*!< Data sent from TXD                                                    */
+  __IO uint32_t  EVENTS_ENDTX;                      /*!< Last TX byte transmitted                                              */
+  __IO uint32_t  EVENTS_ERROR;                      /*!< Error detected                                                        */
+  __I  uint32_t  RESERVED4[7];
+  __IO uint32_t  EVENTS_RXTO;                       /*!< Receiver timeout                                                      */
+  __I  uint32_t  RESERVED5;
+  __IO uint32_t  EVENTS_RXSTARTED;                  /*!< UART receiver has started                                             */
+  __IO uint32_t  EVENTS_TXSTARTED;                  /*!< UART transmitter has started                                          */
+  __I  uint32_t  RESERVED6;
+  __IO uint32_t  EVENTS_TXSTOPPED;                  /*!< Transmitter stopped                                                   */
+  __I  uint32_t  RESERVED7[41];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED8[63];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED9[93];
+  __IO uint32_t  ERRORSRC;                          /*!< Error source                                                          */
+  __I  uint32_t  RESERVED10[31];
+  __IO uint32_t  ENABLE;                            /*!< Enable UART                                                           */
+  __I  uint32_t  RESERVED11;
+  UARTE_PSEL_Type PSEL;                             /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED12[3];
+  __IO uint32_t  BAUDRATE;                          /*!< Baud rate. Accuracy depends on the HFCLK source selected.             */
+  __I  uint32_t  RESERVED13[3];
+  UARTE_RXD_Type RXD;                               /*!< RXD EasyDMA channel                                                   */
+  __I  uint32_t  RESERVED14;
+  UARTE_TXD_Type TXD;                               /*!< TXD EasyDMA channel                                                   */
+  __I  uint32_t  RESERVED15[7];
+  __IO uint32_t  CONFIG;                            /*!< Configuration of parity and hardware flow control                     */
+} NRF_UARTE_Type;
+
+
+/* ================================================================================ */
+/* ================                      UART                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Universal Asynchronous Receiver/Transmitter (UART)
+  */
+
+typedef struct {                                    /*!< UART Structure                                                        */
+  __O  uint32_t  TASKS_STARTRX;                     /*!< Start UART receiver                                                   */
+  __O  uint32_t  TASKS_STOPRX;                      /*!< Stop UART receiver                                                    */
+  __O  uint32_t  TASKS_STARTTX;                     /*!< Start UART transmitter                                                */
+  __O  uint32_t  TASKS_STOPTX;                      /*!< Stop UART transmitter                                                 */
+  __I  uint32_t  RESERVED0[3];
+  __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend UART                                                          */
+  __I  uint32_t  RESERVED1[56];
+  __IO uint32_t  EVENTS_CTS;                        /*!< CTS is activated (set low). Clear To Send.                            */
+  __IO uint32_t  EVENTS_NCTS;                       /*!< CTS is deactivated (set high). Not Clear To Send.                     */
+  __IO uint32_t  EVENTS_RXDRDY;                     /*!< Data received in RXD                                                  */
+  __I  uint32_t  RESERVED2[4];
+  __IO uint32_t  EVENTS_TXDRDY;                     /*!< Data sent from TXD                                                    */
+  __I  uint32_t  RESERVED3;
+  __IO uint32_t  EVENTS_ERROR;                      /*!< Error detected                                                        */
+  __I  uint32_t  RESERVED4[7];
+  __IO uint32_t  EVENTS_RXTO;                       /*!< Receiver timeout                                                      */
+  __I  uint32_t  RESERVED5[46];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED6[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED7[93];
+  __IO uint32_t  ERRORSRC;                          /*!< Error source                                                          */
+  __I  uint32_t  RESERVED8[31];
+  __IO uint32_t  ENABLE;                            /*!< Enable UART                                                           */
+  __I  uint32_t  RESERVED9;
+  __IO uint32_t  PSELRTS;                           /*!< Pin select for RTS                                                    */
+  __IO uint32_t  PSELTXD;                           /*!< Pin select for TXD                                                    */
+  __IO uint32_t  PSELCTS;                           /*!< Pin select for CTS                                                    */
+  __IO uint32_t  PSELRXD;                           /*!< Pin select for RXD                                                    */
+  __I  uint32_t  RXD;                               /*!< RXD register                                                          */
+  __O  uint32_t  TXD;                               /*!< TXD register                                                          */
+  __I  uint32_t  RESERVED10;
+  __IO uint32_t  BAUDRATE;                          /*!< Baud rate                                                             */
+  __I  uint32_t  RESERVED11[17];
+  __IO uint32_t  CONFIG;                            /*!< Configuration of parity and hardware flow control                     */
+} NRF_UART_Type;
+
+
+/* ================================================================================ */
+/* ================                      SPIM                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM)
+  */
+
+typedef struct {                                    /*!< SPIM Structure                                                        */
+  __I  uint32_t  RESERVED0[4];
+  __O  uint32_t  TASKS_START;                       /*!< Start SPI transaction                                                 */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop SPI transaction                                                  */
+  __I  uint32_t  RESERVED1;
+  __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend SPI transaction                                               */
+  __O  uint32_t  TASKS_RESUME;                      /*!< Resume SPI transaction                                                */
+  __I  uint32_t  RESERVED2[56];
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< SPI transaction has stopped                                           */
+  __I  uint32_t  RESERVED3[2];
+  __IO uint32_t  EVENTS_ENDRX;                      /*!< End of RXD buffer reached                                             */
+  __I  uint32_t  RESERVED4;
+  __IO uint32_t  EVENTS_END;                        /*!< End of RXD buffer and TXD buffer reached                              */
+  __I  uint32_t  RESERVED5;
+  __IO uint32_t  EVENTS_ENDTX;                      /*!< End of TXD buffer reached                                             */
+  __I  uint32_t  RESERVED6[10];
+  __IO uint32_t  EVENTS_STARTED;                    /*!< Transaction started                                                   */
+  __I  uint32_t  RESERVED7[44];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED8[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED9[125];
+  __IO uint32_t  ENABLE;                            /*!< Enable SPIM                                                           */
+  __I  uint32_t  RESERVED10;
+  SPIM_PSEL_Type PSEL;                              /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED11[4];
+  __IO uint32_t  FREQUENCY;                         /*!< SPI frequency                                                         */
+  __I  uint32_t  RESERVED12[3];
+  SPIM_RXD_Type RXD;                                /*!< RXD EasyDMA channel                                                   */
+  SPIM_TXD_Type TXD;                                /*!< TXD EasyDMA channel                                                   */
+  __IO uint32_t  CONFIG;                            /*!< Configuration register                                                */
+  __I  uint32_t  RESERVED13[26];
+  __IO uint32_t  ORC;                               /*!< Over-read character. Character clocked out in case and over-read
+                                                         of the TXD buffer.                                                    */
+} NRF_SPIM_Type;
+
+
+/* ================================================================================ */
+/* ================                      SPIS                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief SPI Slave 0 (SPIS)
+  */
+
+typedef struct {                                    /*!< SPIS Structure                                                        */
+  __I  uint32_t  RESERVED0[9];
+  __O  uint32_t  TASKS_ACQUIRE;                     /*!< Acquire SPI semaphore                                                 */
+  __O  uint32_t  TASKS_RELEASE;                     /*!< Release SPI semaphore, enabling the SPI slave to acquire it           */
+  __I  uint32_t  RESERVED1[54];
+  __IO uint32_t  EVENTS_END;                        /*!< Granted transaction completed                                         */
+  __I  uint32_t  RESERVED2[2];
+  __IO uint32_t  EVENTS_ENDRX;                      /*!< End of RXD buffer reached                                             */
+  __I  uint32_t  RESERVED3[5];
+  __IO uint32_t  EVENTS_ACQUIRED;                   /*!< Semaphore acquired                                                    */
+  __I  uint32_t  RESERVED4[53];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED5[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED6[61];
+  __I  uint32_t  SEMSTAT;                           /*!< Semaphore status register                                             */
+  __I  uint32_t  RESERVED7[15];
+  __IO uint32_t  STATUS;                            /*!< Status from last transaction                                          */
+  __I  uint32_t  RESERVED8[47];
+  __IO uint32_t  ENABLE;                            /*!< Enable SPI slave                                                      */
+  __I  uint32_t  RESERVED9;
+  SPIS_PSEL_Type PSEL;                              /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED10[7];
+  SPIS_RXD_Type RXD;                                /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED11;
+  SPIS_TXD_Type TXD;                                /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED12;
+  __IO uint32_t  CONFIG;                            /*!< Configuration register                                                */
+  __I  uint32_t  RESERVED13;
+  __IO uint32_t  DEF;                               /*!< Default character. Character clocked out in case of an ignored
+                                                         transaction.                                                          */
+  __I  uint32_t  RESERVED14[24];
+  __IO uint32_t  ORC;                               /*!< Over-read character                                                   */
+} NRF_SPIS_Type;
+
+
+/* ================================================================================ */
+/* ================                      TWIM                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM)
+  */
+
+typedef struct {                                    /*!< TWIM Structure                                                        */
+  __O  uint32_t  TASKS_STARTRX;                     /*!< Start TWI receive sequence                                            */
+  __I  uint32_t  RESERVED0;
+  __O  uint32_t  TASKS_STARTTX;                     /*!< Start TWI transmit sequence                                           */
+  __I  uint32_t  RESERVED1[2];
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop TWI transaction. Must be issued while the TWI master is
+                                                         not suspended.                                                        */
+  __I  uint32_t  RESERVED2;
+  __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend TWI transaction                                               */
+  __O  uint32_t  TASKS_RESUME;                      /*!< Resume TWI transaction                                                */
+  __I  uint32_t  RESERVED3[56];
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< TWI stopped                                                           */
+  __I  uint32_t  RESERVED4[7];
+  __IO uint32_t  EVENTS_ERROR;                      /*!< TWI error                                                             */
+  __I  uint32_t  RESERVED5[8];
+  __IO uint32_t  EVENTS_SUSPENDED;                  /*!< Last byte has been sent out after the SUSPEND task has been
+                                                         issued, TWI traffic is now suspended.                                 */
+  __IO uint32_t  EVENTS_RXSTARTED;                  /*!< Receive sequence started                                              */
+  __IO uint32_t  EVENTS_TXSTARTED;                  /*!< Transmit sequence started                                             */
+  __I  uint32_t  RESERVED6[2];
+  __IO uint32_t  EVENTS_LASTRX;                     /*!< Byte boundary, starting to receive the last byte                      */
+  __IO uint32_t  EVENTS_LASTTX;                     /*!< Byte boundary, starting to transmit the last byte                     */
+  __I  uint32_t  RESERVED7[39];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED8[63];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED9[110];
+  __IO uint32_t  ERRORSRC;                          /*!< Error source                                                          */
+  __I  uint32_t  RESERVED10[14];
+  __IO uint32_t  ENABLE;                            /*!< Enable TWIM                                                           */
+  __I  uint32_t  RESERVED11;
+  TWIM_PSEL_Type PSEL;                              /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED12[5];
+  __IO uint32_t  FREQUENCY;                         /*!< TWI frequency                                                         */
+  __I  uint32_t  RESERVED13[3];
+  TWIM_RXD_Type RXD;                                /*!< RXD EasyDMA channel                                                   */
+  TWIM_TXD_Type TXD;                                /*!< TXD EasyDMA channel                                                   */
+  __I  uint32_t  RESERVED14[13];
+  __IO uint32_t  ADDRESS;                           /*!< Address used in the TWI transfer                                      */
+} NRF_TWIM_Type;
+
+
+/* ================================================================================ */
+/* ================                      TWIS                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS)
+  */
+
+typedef struct {                                    /*!< TWIS Structure                                                        */
+  __I  uint32_t  RESERVED0[5];
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop TWI transaction                                                  */
+  __I  uint32_t  RESERVED1;
+  __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend TWI transaction                                               */
+  __O  uint32_t  TASKS_RESUME;                      /*!< Resume TWI transaction                                                */
+  __I  uint32_t  RESERVED2[3];
+  __O  uint32_t  TASKS_PREPARERX;                   /*!< Prepare the TWI slave to respond to a write command                   */
+  __O  uint32_t  TASKS_PREPARETX;                   /*!< Prepare the TWI slave to respond to a read command                    */
+  __I  uint32_t  RESERVED3[51];
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< TWI stopped                                                           */
+  __I  uint32_t  RESERVED4[7];
+  __IO uint32_t  EVENTS_ERROR;                      /*!< TWI error                                                             */
+  __I  uint32_t  RESERVED5[9];
+  __IO uint32_t  EVENTS_RXSTARTED;                  /*!< Receive sequence started                                              */
+  __IO uint32_t  EVENTS_TXSTARTED;                  /*!< Transmit sequence started                                             */
+  __I  uint32_t  RESERVED6[4];
+  __IO uint32_t  EVENTS_WRITE;                      /*!< Write command received                                                */
+  __IO uint32_t  EVENTS_READ;                       /*!< Read command received                                                 */
+  __I  uint32_t  RESERVED7[37];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED8[63];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED9[113];
+  __IO uint32_t  ERRORSRC;                          /*!< Error source                                                          */
+  __I  uint32_t  MATCH;                             /*!< Status register indicating which address had a match                  */
+  __I  uint32_t  RESERVED10[10];
+  __IO uint32_t  ENABLE;                            /*!< Enable TWIS                                                           */
+  __I  uint32_t  RESERVED11;
+  TWIS_PSEL_Type PSEL;                              /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED12[9];
+  TWIS_RXD_Type RXD;                                /*!< RXD EasyDMA channel                                                   */
+  __I  uint32_t  RESERVED13;
+  TWIS_TXD_Type TXD;                                /*!< TXD EasyDMA channel                                                   */
+  __I  uint32_t  RESERVED14[14];
+  __IO uint32_t  ADDRESS[2];                        /*!< Description collection[0]: TWI slave address 0                        */
+  __I  uint32_t  RESERVED15;
+  __IO uint32_t  CONFIG;                            /*!< Configuration register for the address match mechanism                */
+  __I  uint32_t  RESERVED16[10];
+  __IO uint32_t  ORC;                               /*!< Over-read character. Character sent out in case of an over-read
+                                                         of the transmit buffer.                                               */
+} NRF_TWIS_Type;
+
+
+/* ================================================================================ */
+/* ================                       SPI                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Serial Peripheral Interface 0 (SPI)
+  */
+
+typedef struct {                                    /*!< SPI Structure                                                         */
+  __I  uint32_t  RESERVED0[66];
+  __IO uint32_t  EVENTS_READY;                      /*!< TXD byte sent and RXD byte received                                   */
+  __I  uint32_t  RESERVED1[126];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED2[125];
+  __IO uint32_t  ENABLE;                            /*!< Enable SPI                                                            */
+  __I  uint32_t  RESERVED3;
+  SPI_PSEL_Type PSEL;                               /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED4;
+  __I  uint32_t  RXD;                               /*!< RXD register                                                          */
+  __IO uint32_t  TXD;                               /*!< TXD register                                                          */
+  __I  uint32_t  RESERVED5;
+  __IO uint32_t  FREQUENCY;                         /*!< SPI frequency                                                         */
+  __I  uint32_t  RESERVED6[11];
+  __IO uint32_t  CONFIG;                            /*!< Configuration register                                                */
+} NRF_SPI_Type;
+
+
+/* ================================================================================ */
+/* ================                       TWI                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief I2C compatible Two-Wire Interface 0 (TWI)
+  */
+
+typedef struct {                                    /*!< TWI Structure                                                         */
+  __O  uint32_t  TASKS_STARTRX;                     /*!< Start TWI receive sequence                                            */
+  __I  uint32_t  RESERVED0;
+  __O  uint32_t  TASKS_STARTTX;                     /*!< Start TWI transmit sequence                                           */
+  __I  uint32_t  RESERVED1[2];
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop TWI transaction                                                  */
+  __I  uint32_t  RESERVED2;
+  __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend TWI transaction                                               */
+  __O  uint32_t  TASKS_RESUME;                      /*!< Resume TWI transaction                                                */
+  __I  uint32_t  RESERVED3[56];
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< TWI stopped                                                           */
+  __IO uint32_t  EVENTS_RXDREADY;                   /*!< TWI RXD byte received                                                 */
+  __I  uint32_t  RESERVED4[4];
+  __IO uint32_t  EVENTS_TXDSENT;                    /*!< TWI TXD byte sent                                                     */
+  __I  uint32_t  RESERVED5;
+  __IO uint32_t  EVENTS_ERROR;                      /*!< TWI error                                                             */
+  __I  uint32_t  RESERVED6[4];
+  __IO uint32_t  EVENTS_BB;                         /*!< TWI byte boundary, generated before each byte that is sent or
+                                                         received                                                              */
+  __I  uint32_t  RESERVED7[3];
+  __IO uint32_t  EVENTS_SUSPENDED;                  /*!< TWI entered the suspended state                                       */
+  __I  uint32_t  RESERVED8[45];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED9[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED10[110];
+  __IO uint32_t  ERRORSRC;                          /*!< Error source                                                          */
+  __I  uint32_t  RESERVED11[14];
+  __IO uint32_t  ENABLE;                            /*!< Enable TWI                                                            */
+  __I  uint32_t  RESERVED12;
+  __IO uint32_t  PSELSCL;                           /*!< Pin select for SCL                                                    */
+  __IO uint32_t  PSELSDA;                           /*!< Pin select for SDA                                                    */
+  __I  uint32_t  RESERVED13[2];
+  __I  uint32_t  RXD;                               /*!< RXD register                                                          */
+  __IO uint32_t  TXD;                               /*!< TXD register                                                          */
+  __I  uint32_t  RESERVED14;
+  __IO uint32_t  FREQUENCY;                         /*!< TWI frequency                                                         */
+  __I  uint32_t  RESERVED15[24];
+  __IO uint32_t  ADDRESS;                           /*!< Address used in the TWI transfer                                      */
+} NRF_TWI_Type;
+
+
+/* ================================================================================ */
+/* ================                      NFCT                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief NFC-A compatible radio (NFCT)
+  */
+
+typedef struct {                                    /*!< NFCT Structure                                                        */
+  __O  uint32_t  TASKS_ACTIVATE;                    /*!< Activate NFC peripheral for incoming and outgoing frames, change
+                                                         state to activated                                                    */
+  __O  uint32_t  TASKS_DISABLE;                     /*!< Disable NFC peripheral                                                */
+  __O  uint32_t  TASKS_SENSE;                       /*!< Enable NFC sense field mode, change state to sense mode               */
+  __O  uint32_t  TASKS_STARTTX;                     /*!< Start transmission of a outgoing frame, change state to transmit      */
+  __I  uint32_t  RESERVED0[3];
+  __O  uint32_t  TASKS_ENABLERXDATA;                /*!< Initializes the EasyDMA for receive.                                  */
+  __I  uint32_t  RESERVED1;
+  __O  uint32_t  TASKS_GOIDLE;                      /*!< Force state machine to IDLE state                                     */
+  __O  uint32_t  TASKS_GOSLEEP;                     /*!< Force state machine to SLEEP_A state                                  */
+  __I  uint32_t  RESERVED2[53];
+  __IO uint32_t  EVENTS_READY;                      /*!< The NFC peripheral is ready to receive and send frames                */
+  __IO uint32_t  EVENTS_FIELDDETECTED;              /*!< Remote NFC field detected                                             */
+  __IO uint32_t  EVENTS_FIELDLOST;                  /*!< Remote NFC field lost                                                 */
+  __IO uint32_t  EVENTS_TXFRAMESTART;               /*!< Marks the start of the first symbol of a transmitted frame            */
+  __IO uint32_t  EVENTS_TXFRAMEEND;                 /*!< Marks the end of the last transmitted on-air symbol of a frame        */
+  __IO uint32_t  EVENTS_RXFRAMESTART;               /*!< Marks the end of the first symbol of a received frame                 */
+  __IO uint32_t  EVENTS_RXFRAMEEND;                 /*!< Received data have been checked (CRC, parity) and transferred
+                                                         to RAM, and EasyDMA has ended accessing the RX buffer                 */
+  __IO uint32_t  EVENTS_ERROR;                      /*!< NFC error reported. The ERRORSTATUS register contains details
+                                                         on the source of the error.                                           */
+  __I  uint32_t  RESERVED3[2];
+  __IO uint32_t  EVENTS_RXERROR;                    /*!< NFC RX frame error reported. The FRAMESTATUS.RX register contains
+                                                         details on the source of the error.                                   */
+  __IO uint32_t  EVENTS_ENDRX;                      /*!< RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full.      */
+  __IO uint32_t  EVENTS_ENDTX;                      /*!< Transmission of data in RAM has ended, and EasyDMA has ended
+                                                         accessing the TX buffer                                               */
+  __I  uint32_t  RESERVED4;
+  __IO uint32_t  EVENTS_AUTOCOLRESSTARTED;          /*!< Auto collision resolution process has started                         */
+  __I  uint32_t  RESERVED5[3];
+  __IO uint32_t  EVENTS_COLLISION;                  /*!< NFC Auto collision resolution error reported.                         */
+  __IO uint32_t  EVENTS_SELECTED;                   /*!< NFC Auto collision resolution successfully completed                  */
+  __IO uint32_t  EVENTS_STARTED;                    /*!< EasyDMA is ready to receive or send frames.                           */
+  __I  uint32_t  RESERVED6[43];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED7[63];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED8[62];
+  __IO uint32_t  ERRORSTATUS;                       /*!< NFC Error Status register                                             */
+  __I  uint32_t  RESERVED9;
+  NFCT_FRAMESTATUS_Type FRAMESTATUS;                /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED10[8];
+  __I  uint32_t  CURRENTLOADCTRL;                   /*!< Current value driven to the NFC Load Control                          */
+  __I  uint32_t  RESERVED11[2];
+  __I  uint32_t  FIELDPRESENT;                      /*!< Indicates the presence or not of a valid field                        */
+  __I  uint32_t  RESERVED12[49];
+  __IO uint32_t  FRAMEDELAYMIN;                     /*!< Minimum frame delay                                                   */
+  __IO uint32_t  FRAMEDELAYMAX;                     /*!< Maximum frame delay                                                   */
+  __IO uint32_t  FRAMEDELAYMODE;                    /*!< Configuration register for the Frame Delay Timer                      */
+  __IO uint32_t  PACKETPTR;                         /*!< Packet pointer for TXD and RXD data storage in Data RAM               */
+  __IO uint32_t  MAXLEN;                            /*!< Size of allocated for TXD and RXD data storage buffer in Data
+                                                         RAM                                                                   */
+  NFCT_TXD_Type TXD;                                /*!< Unspecified                                                           */
+  NFCT_RXD_Type RXD;                                /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED13[26];
+  __IO uint32_t  NFCID1_LAST;                       /*!< Last NFCID1 part (4, 7 or 10 bytes ID)                                */
+  __IO uint32_t  NFCID1_2ND_LAST;                   /*!< Second last NFCID1 part (7 or 10 bytes ID)                            */
+  __IO uint32_t  NFCID1_3RD_LAST;                   /*!< Third last NFCID1 part (10 bytes ID)                                  */
+  __I  uint32_t  RESERVED14;
+  __IO uint32_t  SENSRES;                           /*!< NFC-A SENS_RES auto-response settings                                 */
+  __IO uint32_t  SELRES;                            /*!< NFC-A SEL_RES auto-response settings                                  */
+} NRF_NFCT_Type;
+
+
+/* ================================================================================ */
+/* ================                     GPIOTE                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief GPIO Tasks and Events (GPIOTE)
+  */
+
+typedef struct {                                    /*!< GPIOTE Structure                                                      */
+  __O  uint32_t  TASKS_OUT[8];                      /*!< Description collection[0]: Task for writing to pin specified
+                                                         in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY. */
+  __I  uint32_t  RESERVED0[4];
+  __O  uint32_t  TASKS_SET[8];                      /*!< Description collection[0]: Task for writing to pin specified
+                                                         in CONFIG[0].PSEL. Action on pin is to set it high.                   */
+  __I  uint32_t  RESERVED1[4];
+  __O  uint32_t  TASKS_CLR[8];                      /*!< Description collection[0]: Task for writing to pin specified
+                                                         in CONFIG[0].PSEL. Action on pin is to set it low.                    */
+  __I  uint32_t  RESERVED2[32];
+  __IO uint32_t  EVENTS_IN[8];                      /*!< Description collection[0]: Event generated from pin specified
+                                                         in CONFIG[0].PSEL                                                     */
+  __I  uint32_t  RESERVED3[23];
+  __IO uint32_t  EVENTS_PORT;                       /*!< Event generated from multiple input GPIO pins with SENSE mechanism
+                                                         enabled                                                               */
+  __I  uint32_t  RESERVED4[97];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED5[129];
+  __IO uint32_t  CONFIG[8];                         /*!< Description collection[0]: Configuration for OUT[n], SET[n]
+                                                         and CLR[n] tasks and IN[n] event                                      */
+} NRF_GPIOTE_Type;
+
+
+/* ================================================================================ */
+/* ================                      SAADC                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Analog to Digital Converter (SAADC)
+  */
+
+typedef struct {                                    /*!< SAADC Structure                                                       */
+  __O  uint32_t  TASKS_START;                       /*!< Start the ADC and prepare the result buffer in RAM                    */
+  __O  uint32_t  TASKS_SAMPLE;                      /*!< Take one ADC sample, if scan is enabled all channels are sampled      */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop the ADC and terminate any on-going conversion                    */
+  __O  uint32_t  TASKS_CALIBRATEOFFSET;             /*!< Starts offset auto-calibration                                        */
+  __I  uint32_t  RESERVED0[60];
+  __IO uint32_t  EVENTS_STARTED;                    /*!< The ADC has started                                                   */
+  __IO uint32_t  EVENTS_END;                        /*!< The ADC has filled up the Result buffer                               */
+  __IO uint32_t  EVENTS_DONE;                       /*!< A conversion task has been completed. Depending on the mode,
+                                                         multiple conversions might be needed for a result to be transferred
+                                                          to RAM.                                                              */
+  __IO uint32_t  EVENTS_RESULTDONE;                 /*!< A result is ready to get transferred to RAM.                          */
+  __IO uint32_t  EVENTS_CALIBRATEDONE;              /*!< Calibration is complete                                               */
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< The ADC has stopped                                                   */
+  SAADC_EVENTS_CH_Type EVENTS_CH[8];                /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED1[106];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED2[61];
+  __I  uint32_t  STATUS;                            /*!< Status                                                                */
+  __I  uint32_t  RESERVED3[63];
+  __IO uint32_t  ENABLE;                            /*!< Enable or disable ADC                                                 */
+  __I  uint32_t  RESERVED4[3];
+  SAADC_CH_Type CH[8];                              /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED5[24];
+  __IO uint32_t  RESOLUTION;                        /*!< Resolution configuration                                              */
+  __IO uint32_t  OVERSAMPLE;                        /*!< Oversampling configuration. OVERSAMPLE should not be combined
+                                                         with SCAN. The RESOLUTION is applied before averaging, thus
+                                                          for high OVERSAMPLE a higher RESOLUTION should be used.              */
+  __IO uint32_t  SAMPLERATE;                        /*!< Controls normal or continuous sample rate                             */
+  __I  uint32_t  RESERVED6[12];
+  SAADC_RESULT_Type RESULT;                         /*!< RESULT EasyDMA channel                                                */
+} NRF_SAADC_Type;
+
+
+/* ================================================================================ */
+/* ================                      TIMER                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Timer/Counter 0 (TIMER)
+  */
+
+typedef struct {                                    /*!< TIMER Structure                                                       */
+  __O  uint32_t  TASKS_START;                       /*!< Start Timer                                                           */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop Timer                                                            */
+  __O  uint32_t  TASKS_COUNT;                       /*!< Increment Timer (Counter mode only)                                   */
+  __O  uint32_t  TASKS_CLEAR;                       /*!< Clear time                                                            */
+  __O  uint32_t  TASKS_SHUTDOWN;                    /*!< Deprecated register - Shut down timer                                 */
+  __I  uint32_t  RESERVED0[11];
+  __O  uint32_t  TASKS_CAPTURE[6];                  /*!< Description collection[0]: Capture Timer value to CC[0] register      */
+  __I  uint32_t  RESERVED1[58];
+  __IO uint32_t  EVENTS_COMPARE[6];                 /*!< Description collection[0]: Compare event on CC[0] match               */
+  __I  uint32_t  RESERVED2[42];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED3[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED4[126];
+  __IO uint32_t  MODE;                              /*!< Timer mode selection                                                  */
+  __IO uint32_t  BITMODE;                           /*!< Configure the number of bits used by the TIMER                        */
+  __I  uint32_t  RESERVED5;
+  __IO uint32_t  PRESCALER;                         /*!< Timer prescaler register                                              */
+  __I  uint32_t  RESERVED6[11];
+  __IO uint32_t  CC[6];                             /*!< Description collection[0]: Capture/Compare register 0                 */
+} NRF_TIMER_Type;
+
+
+/* ================================================================================ */
+/* ================                       RTC                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Real time counter 0 (RTC)
+  */
+
+typedef struct {                                    /*!< RTC Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Start RTC COUNTER                                                     */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop RTC COUNTER                                                      */
+  __O  uint32_t  TASKS_CLEAR;                       /*!< Clear RTC COUNTER                                                     */
+  __O  uint32_t  TASKS_TRIGOVRFLW;                  /*!< Set COUNTER to 0xFFFFF0                                               */
+  __I  uint32_t  RESERVED0[60];
+  __IO uint32_t  EVENTS_TICK;                       /*!< Event on COUNTER increment                                            */
+  __IO uint32_t  EVENTS_OVRFLW;                     /*!< Event on COUNTER overflow                                             */
+  __I  uint32_t  RESERVED1[14];
+  __IO uint32_t  EVENTS_COMPARE[4];                 /*!< Description collection[0]: Compare event on CC[0] match               */
+  __I  uint32_t  RESERVED2[109];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[13];
+  __IO uint32_t  EVTEN;                             /*!< Enable or disable event routing                                       */
+  __IO uint32_t  EVTENSET;                          /*!< Enable event routing                                                  */
+  __IO uint32_t  EVTENCLR;                          /*!< Disable event routing                                                 */
+  __I  uint32_t  RESERVED4[110];
+  __I  uint32_t  COUNTER;                           /*!< Current COUNTER value                                                 */
+  __IO uint32_t  PRESCALER;                         /*!< 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must
+                                                         be written when RTC is stopped                                        */
+  __I  uint32_t  RESERVED5[13];
+  __IO uint32_t  CC[4];                             /*!< Description collection[0]: Compare register 0                         */
+} NRF_RTC_Type;
+
+
+/* ================================================================================ */
+/* ================                      TEMP                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Temperature Sensor (TEMP)
+  */
+
+typedef struct {                                    /*!< TEMP Structure                                                        */
+  __O  uint32_t  TASKS_START;                       /*!< Start temperature measurement                                         */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop temperature measurement                                          */
+  __I  uint32_t  RESERVED0[62];
+  __IO uint32_t  EVENTS_DATARDY;                    /*!< Temperature measurement complete, data ready                          */
+  __I  uint32_t  RESERVED1[128];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED2[127];
+  __I  int32_t   TEMP;                              /*!< Temperature in degC (0.25deg steps)                                   */
+  __I  uint32_t  RESERVED3[5];
+  __IO uint32_t  A0;                                /*!< Slope of 1st piece wise linear function                               */
+  __IO uint32_t  A1;                                /*!< Slope of 2nd piece wise linear function                               */
+  __IO uint32_t  A2;                                /*!< Slope of 3rd piece wise linear function                               */
+  __IO uint32_t  A3;                                /*!< Slope of 4th piece wise linear function                               */
+  __IO uint32_t  A4;                                /*!< Slope of 5th piece wise linear function                               */
+  __IO uint32_t  A5;                                /*!< Slope of 6th piece wise linear function                               */
+  __I  uint32_t  RESERVED4[2];
+  __IO uint32_t  B0;                                /*!< y-intercept of 1st piece wise linear function                         */
+  __IO uint32_t  B1;                                /*!< y-intercept of 2nd piece wise linear function                         */
+  __IO uint32_t  B2;                                /*!< y-intercept of 3rd piece wise linear function                         */
+  __IO uint32_t  B3;                                /*!< y-intercept of 4th piece wise linear function                         */
+  __IO uint32_t  B4;                                /*!< y-intercept of 5th piece wise linear function                         */
+  __IO uint32_t  B5;                                /*!< y-intercept of 6th piece wise linear function                         */
+  __I  uint32_t  RESERVED5[2];
+  __IO uint32_t  T0;                                /*!< End point of 1st piece wise linear function                           */
+  __IO uint32_t  T1;                                /*!< End point of 2nd piece wise linear function                           */
+  __IO uint32_t  T2;                                /*!< End point of 3rd piece wise linear function                           */
+  __IO uint32_t  T3;                                /*!< End point of 4th piece wise linear function                           */
+  __IO uint32_t  T4;                                /*!< End point of 5th piece wise linear function                           */
+} NRF_TEMP_Type;
+
+
+/* ================================================================================ */
+/* ================                       RNG                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Random Number Generator (RNG)
+  */
+
+typedef struct {                                    /*!< RNG Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Task starting the random number generator                             */
+  __O  uint32_t  TASKS_STOP;                        /*!< Task stopping the random number generator                             */
+  __I  uint32_t  RESERVED0[62];
+  __IO uint32_t  EVENTS_VALRDY;                     /*!< Event being generated for every new random number written to
+                                                         the VALUE register                                                    */
+  __I  uint32_t  RESERVED1[63];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED2[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[126];
+  __IO uint32_t  CONFIG;                            /*!< Configuration register                                                */
+  __I  uint32_t  VALUE;                             /*!< Output random number                                                  */
+} NRF_RNG_Type;
+
+
+/* ================================================================================ */
+/* ================                       ECB                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief AES ECB Mode Encryption (ECB)
+  */
+
+typedef struct {                                    /*!< ECB Structure                                                         */
+  __O  uint32_t  TASKS_STARTECB;                    /*!< Start ECB block encrypt                                               */
+  __O  uint32_t  TASKS_STOPECB;                     /*!< Abort a possible executing ECB operation                              */
+  __I  uint32_t  RESERVED0[62];
+  __IO uint32_t  EVENTS_ENDECB;                     /*!< ECB block encrypt complete                                            */
+  __IO uint32_t  EVENTS_ERRORECB;                   /*!< ECB block encrypt aborted because of a STOPECB task or due to
+                                                         an error                                                              */
+  __I  uint32_t  RESERVED1[127];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED2[126];
+  __IO uint32_t  ECBDATAPTR;                        /*!< ECB block encrypt memory pointers                                     */
+} NRF_ECB_Type;
+
+
+/* ================================================================================ */
+/* ================                       CCM                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief AES CCM Mode Encryption (CCM)
+  */
+
+typedef struct {                                    /*!< CCM Structure                                                         */
+  __O  uint32_t  TASKS_KSGEN;                       /*!< Start generation of key-stream. This operation will stop by
+                                                         itself when completed.                                                */
+  __O  uint32_t  TASKS_CRYPT;                       /*!< Start encryption/decryption. This operation will stop by itself
+                                                         when completed.                                                       */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop encryption/decryption                                            */
+  __I  uint32_t  RESERVED0[61];
+  __IO uint32_t  EVENTS_ENDKSGEN;                   /*!< Key-stream generation complete                                        */
+  __IO uint32_t  EVENTS_ENDCRYPT;                   /*!< Encrypt/decrypt complete                                              */
+  __IO uint32_t  EVENTS_ERROR;                      /*!< CCM error event                                                       */
+  __I  uint32_t  RESERVED1[61];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED2[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[61];
+  __I  uint32_t  MICSTATUS;                         /*!< MIC check result                                                      */
+  __I  uint32_t  RESERVED4[63];
+  __IO uint32_t  ENABLE;                            /*!< Enable                                                                */
+  __IO uint32_t  MODE;                              /*!< Operation mode                                                        */
+  __IO uint32_t  CNFPTR;                            /*!< Pointer to data structure holding AES key and NONCE vector            */
+  __IO uint32_t  INPTR;                             /*!< Input pointer                                                         */
+  __IO uint32_t  OUTPTR;                            /*!< Output pointer                                                        */
+  __IO uint32_t  SCRATCHPTR;                        /*!< Pointer to data area used for temporary storage                       */
+} NRF_CCM_Type;
+
+
+/* ================================================================================ */
+/* ================                       AAR                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Accelerated Address Resolver (AAR)
+  */
+
+typedef struct {                                    /*!< AAR Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Start resolving addresses based on IRKs specified in the IRK
+                                                         data structure                                                        */
+  __I  uint32_t  RESERVED0;
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop resolving addresses                                              */
+  __I  uint32_t  RESERVED1[61];
+  __IO uint32_t  EVENTS_END;                        /*!< Address resolution procedure complete                                 */
+  __IO uint32_t  EVENTS_RESOLVED;                   /*!< Address resolved                                                      */
+  __IO uint32_t  EVENTS_NOTRESOLVED;                /*!< Address not resolved                                                  */
+  __I  uint32_t  RESERVED2[126];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[61];
+  __I  uint32_t  STATUS;                            /*!< Resolution status                                                     */
+  __I  uint32_t  RESERVED4[63];
+  __IO uint32_t  ENABLE;                            /*!< Enable AAR                                                            */
+  __IO uint32_t  NIRK;                              /*!< Number of IRKs                                                        */
+  __IO uint32_t  IRKPTR;                            /*!< Pointer to IRK data structure                                         */
+  __I  uint32_t  RESERVED5;
+  __IO uint32_t  ADDRPTR;                           /*!< Pointer to the resolvable address                                     */
+  __IO uint32_t  SCRATCHPTR;                        /*!< Pointer to data area used for temporary storage                       */
+} NRF_AAR_Type;
+
+
+/* ================================================================================ */
+/* ================                       WDT                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Watchdog Timer (WDT)
+  */
+
+typedef struct {                                    /*!< WDT Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Start the watchdog                                                    */
+  __I  uint32_t  RESERVED0[63];
+  __IO uint32_t  EVENTS_TIMEOUT;                    /*!< Watchdog timeout                                                      */
+  __I  uint32_t  RESERVED1[128];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED2[61];
+  __I  uint32_t  RUNSTATUS;                         /*!< Run status                                                            */
+  __I  uint32_t  REQSTATUS;                         /*!< Request status                                                        */
+  __I  uint32_t  RESERVED3[63];
+  __IO uint32_t  CRV;                               /*!< Counter reload value                                                  */
+  __IO uint32_t  RREN;                              /*!< Enable register for reload request registers                          */
+  __IO uint32_t  CONFIG;                            /*!< Configuration register                                                */
+  __I  uint32_t  RESERVED4[60];
+  __O  uint32_t  RR[8];                             /*!< Description collection[0]: Reload request 0                           */
+} NRF_WDT_Type;
+
+
+/* ================================================================================ */
+/* ================                      QDEC                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Quadrature Decoder (QDEC)
+  */
+
+typedef struct {                                    /*!< QDEC Structure                                                        */
+  __O  uint32_t  TASKS_START;                       /*!< Task starting the quadrature decoder                                  */
+  __O  uint32_t  TASKS_STOP;                        /*!< Task stopping the quadrature decoder                                  */
+  __O  uint32_t  TASKS_READCLRACC;                  /*!< Read and clear ACC and ACCDBL                                         */
+  __O  uint32_t  TASKS_RDCLRACC;                    /*!< Read and clear ACC                                                    */
+  __O  uint32_t  TASKS_RDCLRDBL;                    /*!< Read and clear ACCDBL                                                 */
+  __I  uint32_t  RESERVED0[59];
+  __IO uint32_t  EVENTS_SAMPLERDY;                  /*!< Event being generated for every new sample value written to
+                                                         the SAMPLE register                                                   */
+  __IO uint32_t  EVENTS_REPORTRDY;                  /*!< Non-null report ready                                                 */
+  __IO uint32_t  EVENTS_ACCOF;                      /*!< ACC or ACCDBL register overflow                                       */
+  __IO uint32_t  EVENTS_DBLRDY;                     /*!< Double displacement(s) detected                                       */
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< QDEC has been stopped                                                 */
+  __I  uint32_t  RESERVED1[59];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED2[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[125];
+  __IO uint32_t  ENABLE;                            /*!< Enable the quadrature decoder                                         */
+  __IO uint32_t  LEDPOL;                            /*!< LED output pin polarity                                               */
+  __IO uint32_t  SAMPLEPER;                         /*!< Sample period                                                         */
+  __I  int32_t   SAMPLE;                            /*!< Motion sample value                                                   */
+  __IO uint32_t  REPORTPER;                         /*!< Number of samples to be taken before REPORTRDY and DBLRDY events
+                                                         can be generated                                                      */
+  __I  int32_t   ACC;                               /*!< Register accumulating the valid transitions                           */
+  __I  int32_t   ACCREAD;                           /*!< Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC
+                                                         task                                                                  */
+  QDEC_PSEL_Type PSEL;                              /*!< Unspecified                                                           */
+  __IO uint32_t  DBFEN;                             /*!< Enable input debounce filters                                         */
+  __I  uint32_t  RESERVED4[5];
+  __IO uint32_t  LEDPRE;                            /*!< Time period the LED is switched ON prior to sampling                  */
+  __I  uint32_t  ACCDBL;                            /*!< Register accumulating the number of detected double transitions       */
+  __I  uint32_t  ACCDBLREAD;                        /*!< Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL
+                                                         task                                                                  */
+} NRF_QDEC_Type;
+
+
+/* ================================================================================ */
+/* ================                      COMP                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Comparator (COMP)
+  */
+
+typedef struct {                                    /*!< COMP Structure                                                        */
+  __O  uint32_t  TASKS_START;                       /*!< Start comparator                                                      */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop comparator                                                       */
+  __O  uint32_t  TASKS_SAMPLE;                      /*!< Sample comparator value                                               */
+  __I  uint32_t  RESERVED0[61];
+  __IO uint32_t  EVENTS_READY;                      /*!< COMP is ready and output is valid                                     */
+  __IO uint32_t  EVENTS_DOWN;                       /*!< Downward crossing                                                     */
+  __IO uint32_t  EVENTS_UP;                         /*!< Upward crossing                                                       */
+  __IO uint32_t  EVENTS_CROSS;                      /*!< Downward or upward crossing                                           */
+  __I  uint32_t  RESERVED1[60];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED2[63];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[61];
+  __I  uint32_t  RESULT;                            /*!< Compare result                                                        */
+  __I  uint32_t  RESERVED4[63];
+  __IO uint32_t  ENABLE;                            /*!< COMP enable                                                           */
+  __IO uint32_t  PSEL;                              /*!< Pin select                                                            */
+  __IO uint32_t  REFSEL;                            /*!< Reference source select                                               */
+  __IO uint32_t  EXTREFSEL;                         /*!< External reference select                                             */
+  __I  uint32_t  RESERVED5[8];
+  __IO uint32_t  TH;                                /*!< Threshold configuration for hysteresis unit                           */
+  __IO uint32_t  MODE;                              /*!< Mode configuration                                                    */
+  __IO uint32_t  HYST;                              /*!< Comparator hysteresis enable                                          */
+  __IO uint32_t  ISOURCE;                           /*!< Current source select on analog input                                 */
+} NRF_COMP_Type;
+
+
+/* ================================================================================ */
+/* ================                     LPCOMP                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Low Power Comparator (LPCOMP)
+  */
+
+typedef struct {                                    /*!< LPCOMP Structure                                                      */
+  __O  uint32_t  TASKS_START;                       /*!< Start comparator                                                      */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop comparator                                                       */
+  __O  uint32_t  TASKS_SAMPLE;                      /*!< Sample comparator value                                               */
+  __I  uint32_t  RESERVED0[61];
+  __IO uint32_t  EVENTS_READY;                      /*!< LPCOMP is ready and output is valid                                   */
+  __IO uint32_t  EVENTS_DOWN;                       /*!< Downward crossing                                                     */
+  __IO uint32_t  EVENTS_UP;                         /*!< Upward crossing                                                       */
+  __IO uint32_t  EVENTS_CROSS;                      /*!< Downward or upward crossing                                           */
+  __I  uint32_t  RESERVED1[60];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED2[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[61];
+  __I  uint32_t  RESULT;                            /*!< Compare result                                                        */
+  __I  uint32_t  RESERVED4[63];
+  __IO uint32_t  ENABLE;                            /*!< Enable LPCOMP                                                         */
+  __IO uint32_t  PSEL;                              /*!< Input pin select                                                      */
+  __IO uint32_t  REFSEL;                            /*!< Reference select                                                      */
+  __IO uint32_t  EXTREFSEL;                         /*!< External reference select                                             */
+  __I  uint32_t  RESERVED5[4];
+  __IO uint32_t  ANADETECT;                         /*!< Analog detect configuration                                           */
+  __I  uint32_t  RESERVED6[5];
+  __IO uint32_t  HYST;                              /*!< Comparator hysteresis enable                                          */
+} NRF_LPCOMP_Type;
+
+
+/* ================================================================================ */
+/* ================                       SWI                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Software interrupt 0 (SWI)
+  */
+
+typedef struct {                                    /*!< SWI Structure                                                         */
+  __I  uint32_t  UNUSED;                            /*!< Unused.                                                               */
+} NRF_SWI_Type;
+
+
+/* ================================================================================ */
+/* ================                       EGU                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Event Generator Unit 0 (EGU)
+  */
+
+typedef struct {                                    /*!< EGU Structure                                                         */
+  __O  uint32_t  TASKS_TRIGGER[16];                 /*!< Description collection[0]: Trigger 0 for triggering the corresponding
+                                                         TRIGGERED[0] event                                                    */
+  __I  uint32_t  RESERVED0[48];
+  __IO uint32_t  EVENTS_TRIGGERED[16];              /*!< Description collection[0]: Event number 0 generated by triggering
+                                                         the corresponding TRIGGER[0] task                                     */
+  __I  uint32_t  RESERVED1[112];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+} NRF_EGU_Type;
+
+
+/* ================================================================================ */
+/* ================                       PWM                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Pulse Width Modulation Unit 0 (PWM)
+  */
+
+typedef struct {                                    /*!< PWM Structure                                                         */
+  __I  uint32_t  RESERVED0;
+  __O  uint32_t  TASKS_STOP;                        /*!< Stops PWM pulse generation on all channels at the end of current
+                                                         PWM period, and stops sequence playback                               */
+  __O  uint32_t  TASKS_SEQSTART[2];                 /*!< Description collection[0]: Loads the first PWM value on all
+                                                         enabled channels from sequence 0, and starts playing that sequence
+                                                          at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes
+                                                          PWM generation to start it was not running.                          */
+  __O  uint32_t  TASKS_NEXTSTEP;                    /*!< Steps by one value in the current sequence on all enabled channels
+                                                         if DECODER.MODE=NextStep. Does not cause PWM generation to start
+                                                          it was not running.                                                  */
+  __I  uint32_t  RESERVED1[60];
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< Response to STOP task, emitted when PWM pulses are no longer
+                                                         generated                                                             */
+  __IO uint32_t  EVENTS_SEQSTARTED[2];              /*!< Description collection[0]: First PWM period started on sequence
+                                                         0                                                                     */
+  __IO uint32_t  EVENTS_SEQEND[2];                  /*!< Description collection[0]: Emitted at end of every sequence
+                                                         0, when last value from RAM has been applied to wave counter          */
+  __IO uint32_t  EVENTS_PWMPERIODEND;               /*!< Emitted at the end of each PWM period                                 */
+  __IO uint32_t  EVENTS_LOOPSDONE;                  /*!< Concatenated sequences have been played the amount of times
+                                                         defined in LOOP.CNT                                                   */
+  __I  uint32_t  RESERVED2[56];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED3[63];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED4[125];
+  __IO uint32_t  ENABLE;                            /*!< PWM module enable register                                            */
+  __IO uint32_t  MODE;                              /*!< Selects operating mode of the wave counter                            */
+  __IO uint32_t  COUNTERTOP;                        /*!< Value up to which the pulse generator counter counts                  */
+  __IO uint32_t  PRESCALER;                         /*!< Configuration for PWM_CLK                                             */
+  __IO uint32_t  DECODER;                           /*!< Configuration of the decoder                                          */
+  __IO uint32_t  LOOP;                              /*!< Amount of playback of a loop                                          */
+  __I  uint32_t  RESERVED5[2];
+  PWM_SEQ_Type SEQ[2];                              /*!< Unspecified                                                           */
+  PWM_PSEL_Type PSEL;                               /*!< Unspecified                                                           */
+} NRF_PWM_Type;
+
+
+/* ================================================================================ */
+/* ================                       PDM                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Pulse Density Modulation (Digital Microphone) Interface (PDM)
+  */
+
+typedef struct {                                    /*!< PDM Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Starts continuous PDM transfer                                        */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stops PDM transfer                                                    */
+  __I  uint32_t  RESERVED0[62];
+  __IO uint32_t  EVENTS_STARTED;                    /*!< PDM transfer has started                                              */
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< PDM transfer has finished                                             */
+  __IO uint32_t  EVENTS_END;                        /*!< The PDM has written the last sample specified by SAMPLE.MAXCNT
+                                                         (or the last sample after a STOP task has been received) to
+                                                          Data RAM                                                             */
+  __I  uint32_t  RESERVED1[125];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED2[125];
+  __IO uint32_t  ENABLE;                            /*!< PDM module enable register                                            */
+  __IO uint32_t  PDMCLKCTRL;                        /*!< PDM clock generator control                                           */
+  __IO uint32_t  MODE;                              /*!< Defines the routing of the connected PDM microphones' signals         */
+  __I  uint32_t  RESERVED3[3];
+  __IO uint32_t  GAINL;                             /*!< Left output gain adjustment                                           */
+  __IO uint32_t  GAINR;                             /*!< Right output gain adjustment                                          */
+  __I  uint32_t  RESERVED4[8];
+  PDM_PSEL_Type PSEL;                               /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED5[6];
+  PDM_SAMPLE_Type SAMPLE;                           /*!< Unspecified                                                           */
+} NRF_PDM_Type;
+
+
+/* ================================================================================ */
+/* ================                      NVMC                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Non Volatile Memory Controller (NVMC)
+  */
+
+typedef struct {                                    /*!< NVMC Structure                                                        */
+  __I  uint32_t  RESERVED0[256];
+  __I  uint32_t  READY;                             /*!< Ready flag                                                            */
+  __I  uint32_t  RESERVED1[64];
+  __IO uint32_t  CONFIG;                            /*!< Configuration register                                                */
+  
+  union {
+    __IO uint32_t  ERASEPCR1;                       /*!< Deprecated register - Register for erasing a page in Code area.
+                                                         Equivalent to ERASEPAGE.                                              */
+    __IO uint32_t  ERASEPAGE;                       /*!< Register for erasing a page in Code area                              */
+  };
+  __IO uint32_t  ERASEALL;                          /*!< Register for erasing all non-volatile user memory                     */
+  __IO uint32_t  ERASEPCR0;                         /*!< Deprecated register - Register for erasing a page in Code area.
+                                                         Equivalent to ERASEPAGE.                                              */
+  __IO uint32_t  ERASEUICR;                         /*!< Register for erasing User Information Configuration Registers         */
+  __I  uint32_t  RESERVED2[10];
+  __IO uint32_t  ICACHECNF;                         /*!< I-Code cache configuration register.                                  */
+  __I  uint32_t  RESERVED3;
+  __IO uint32_t  IHIT;                              /*!< I-Code cache hit counter.                                             */
+  __IO uint32_t  IMISS;                             /*!< I-Code cache miss counter.                                            */
+} NRF_NVMC_Type;
+
+
+/* ================================================================================ */
+/* ================                       PPI                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Programmable Peripheral Interconnect (PPI)
+  */
+
+typedef struct {                                    /*!< PPI Structure                                                         */
+  PPI_TASKS_CHG_Type TASKS_CHG[6];                  /*!< Channel group tasks                                                   */
+  __I  uint32_t  RESERVED0[308];
+  __IO uint32_t  CHEN;                              /*!< Channel enable register                                               */
+  __IO uint32_t  CHENSET;                           /*!< Channel enable set register                                           */
+  __IO uint32_t  CHENCLR;                           /*!< Channel enable clear register                                         */
+  __I  uint32_t  RESERVED1;
+  PPI_CH_Type CH[20];                               /*!< PPI Channel                                                           */
+  __I  uint32_t  RESERVED2[148];
+  __IO uint32_t  CHG[6];                            /*!< Description collection[0]: Channel group 0                            */
+  __I  uint32_t  RESERVED3[62];
+  PPI_FORK_Type FORK[32];                           /*!< Fork                                                                  */
+} NRF_PPI_Type;
+
+
+/* ================================================================================ */
+/* ================                       MWU                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Memory Watch Unit (MWU)
+  */
+
+typedef struct {                                    /*!< MWU Structure                                                         */
+  __I  uint32_t  RESERVED0[64];
+  MWU_EVENTS_REGION_Type EVENTS_REGION[4];          /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED1[16];
+  MWU_EVENTS_PREGION_Type EVENTS_PREGION[2];        /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED2[100];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[5];
+  __IO uint32_t  NMIEN;                             /*!< Enable or disable non-maskable interrupt                              */
+  __IO uint32_t  NMIENSET;                          /*!< Enable non-maskable interrupt                                         */
+  __IO uint32_t  NMIENCLR;                          /*!< Disable non-maskable interrupt                                        */
+  __I  uint32_t  RESERVED4[53];
+  MWU_PERREGION_Type PERREGION[2];                  /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED5[64];
+  __IO uint32_t  REGIONEN;                          /*!< Enable/disable regions watch                                          */
+  __IO uint32_t  REGIONENSET;                       /*!< Enable regions watch                                                  */
+  __IO uint32_t  REGIONENCLR;                       /*!< Disable regions watch                                                 */
+  __I  uint32_t  RESERVED6[57];
+  MWU_REGION_Type REGION[4];                        /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED7[32];
+  MWU_PREGION_Type PREGION[2];                      /*!< Unspecified                                                           */
+} NRF_MWU_Type;
+
+
+/* ================================================================================ */
+/* ================                       I2S                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Inter-IC Sound (I2S)
+  */
+
+typedef struct {                                    /*!< I2S Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Starts continuous I2S transfer. Also starts MCK generator when
+                                                         this is enabled.                                                      */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stops I2S transfer. Also stops MCK generator. Triggering this
+                                                         task will cause the {event:STOPPED} event to be generated.            */
+  __I  uint32_t  RESERVED0[63];
+  __IO uint32_t  EVENTS_RXPTRUPD;                   /*!< The RXD.PTR register has been copied to internal double-buffers.
+                                                         When the I2S module is started and RX is enabled, this event
+                                                          will be generated for every RXTXD.MAXCNT words that are received
+                                                          on the SDIN pin.                                                     */
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< I2S transfer stopped.                                                 */
+  __I  uint32_t  RESERVED1[2];
+  __IO uint32_t  EVENTS_TXPTRUPD;                   /*!< The TDX.PTR register has been copied to internal double-buffers.
+                                                         When the I2S module is started and TX is enabled, this event
+                                                          will be generated for every RXTXD.MAXCNT words that are sent
+                                                          on the SDOUT pin.                                                    */
+  __I  uint32_t  RESERVED2[122];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[125];
+  __IO uint32_t  ENABLE;                            /*!< Enable I2S module.                                                    */
+  I2S_CONFIG_Type CONFIG;                           /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED4[3];
+  I2S_RXD_Type RXD;                                 /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED5;
+  I2S_TXD_Type TXD;                                 /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED6[3];
+  I2S_RXTXD_Type RXTXD;                             /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED7[3];
+  I2S_PSEL_Type PSEL;                               /*!< Unspecified                                                           */
+} NRF_I2S_Type;
+
+
+/* ================================================================================ */
+/* ================                       FPU                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief FPU (FPU)
+  */
+
+typedef struct {                                    /*!< FPU Structure                                                         */
+  __I  uint32_t  UNUSED;                            /*!< Unused.                                                               */
+} NRF_FPU_Type;
+
+
+/* ================================================================================ */
+/* ================                      GPIO                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief GPIO Port 1 (GPIO)
+  */
+
+typedef struct {                                    /*!< GPIO Structure                                                        */
+  __I  uint32_t  RESERVED0[321];
+  __IO uint32_t  OUT;                               /*!< Write GPIO port                                                       */
+  __IO uint32_t  OUTSET;                            /*!< Set individual bits in GPIO port                                      */
+  __IO uint32_t  OUTCLR;                            /*!< Clear individual bits in GPIO port                                    */
+  __I  uint32_t  IN;                                /*!< Read GPIO port                                                        */
+  __IO uint32_t  DIR;                               /*!< Direction of GPIO pins                                                */
+  __IO uint32_t  DIRSET;                            /*!< DIR set register                                                      */
+  __IO uint32_t  DIRCLR;                            /*!< DIR clear register                                                    */
+  __IO uint32_t  LATCH;                             /*!< Latch register indicating what GPIO pins that have met the criteria
+                                                         set in the PIN_CNF[n].SENSE registers                                 */
+  __IO uint32_t  DETECTMODE;                        /*!< Select between default DETECT signal behaviour and LDETECT mode       */
+  __I  uint32_t  RESERVED1[118];
+  __IO uint32_t  PIN_CNF[32];                       /*!< Description collection[0]: Configuration of GPIO pins                 */
+} NRF_GPIO_Type;
+
+
+/* --------------------  End of section using anonymous unions  ------------------- */
+#if defined(__CC_ARM)
+  #pragma pop
+#elif defined(__ICCARM__)
+  /* leave anonymous unions enabled */
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+  /* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+  #pragma warning restore
+#else
+  #warning Not supported compiler type
+#endif
+
+
+
+
+/* ================================================================================ */
+/* ================              Peripheral memory map             ================ */
+/* ================================================================================ */
+
+#define NRF_FICR_BASE                   0x10000000UL
+#define NRF_UICR_BASE                   0x10001000UL
+#define NRF_BPROT_BASE                  0x40000000UL
+#define NRF_POWER_BASE                  0x40000000UL
+#define NRF_CLOCK_BASE                  0x40000000UL
+#define NRF_RADIO_BASE                  0x40001000UL
+#define NRF_UARTE0_BASE                 0x40002000UL
+#define NRF_UART0_BASE                  0x40002000UL
+#define NRF_SPIM0_BASE                  0x40003000UL
+#define NRF_SPIS0_BASE                  0x40003000UL
+#define NRF_TWIM0_BASE                  0x40003000UL
+#define NRF_TWIS0_BASE                  0x40003000UL
+#define NRF_SPI0_BASE                   0x40003000UL
+#define NRF_TWI0_BASE                   0x40003000UL
+#define NRF_SPIM1_BASE                  0x40004000UL
+#define NRF_SPIS1_BASE                  0x40004000UL
+#define NRF_TWIM1_BASE                  0x40004000UL
+#define NRF_TWIS1_BASE                  0x40004000UL
+#define NRF_SPI1_BASE                   0x40004000UL
+#define NRF_TWI1_BASE                   0x40004000UL
+#define NRF_NFCT_BASE                   0x40005000UL
+#define NRF_GPIOTE_BASE                 0x40006000UL
+#define NRF_SAADC_BASE                  0x40007000UL
+#define NRF_TIMER0_BASE                 0x40008000UL
+#define NRF_TIMER1_BASE                 0x40009000UL
+#define NRF_TIMER2_BASE                 0x4000A000UL
+#define NRF_RTC0_BASE                   0x4000B000UL
+#define NRF_TEMP_BASE                   0x4000C000UL
+#define NRF_RNG_BASE                    0x4000D000UL
+#define NRF_ECB_BASE                    0x4000E000UL
+#define NRF_CCM_BASE                    0x4000F000UL
+#define NRF_AAR_BASE                    0x4000F000UL
+#define NRF_WDT_BASE                    0x40010000UL
+#define NRF_RTC1_BASE                   0x40011000UL
+#define NRF_QDEC_BASE                   0x40012000UL
+#define NRF_COMP_BASE                   0x40013000UL
+#define NRF_LPCOMP_BASE                 0x40013000UL
+#define NRF_SWI0_BASE                   0x40014000UL
+#define NRF_EGU0_BASE                   0x40014000UL
+#define NRF_SWI1_BASE                   0x40015000UL
+#define NRF_EGU1_BASE                   0x40015000UL
+#define NRF_SWI2_BASE                   0x40016000UL
+#define NRF_EGU2_BASE                   0x40016000UL
+#define NRF_SWI3_BASE                   0x40017000UL
+#define NRF_EGU3_BASE                   0x40017000UL
+#define NRF_SWI4_BASE                   0x40018000UL
+#define NRF_EGU4_BASE                   0x40018000UL
+#define NRF_SWI5_BASE                   0x40019000UL
+#define NRF_EGU5_BASE                   0x40019000UL
+#define NRF_TIMER3_BASE                 0x4001A000UL
+#define NRF_TIMER4_BASE                 0x4001B000UL
+#define NRF_PWM0_BASE                   0x4001C000UL
+#define NRF_PDM_BASE                    0x4001D000UL
+#define NRF_NVMC_BASE                   0x4001E000UL
+#define NRF_PPI_BASE                    0x4001F000UL
+#define NRF_MWU_BASE                    0x40020000UL
+#define NRF_PWM1_BASE                   0x40021000UL
+#define NRF_PWM2_BASE                   0x40022000UL
+#define NRF_SPIM2_BASE                  0x40023000UL
+#define NRF_SPIS2_BASE                  0x40023000UL
+#define NRF_SPI2_BASE                   0x40023000UL
+#define NRF_RTC2_BASE                   0x40024000UL
+#define NRF_I2S_BASE                    0x40025000UL
+#define NRF_FPU_BASE                    0x40026000UL
+#define NRF_P0_BASE                     0x50000000UL
+
+
+/* ================================================================================ */
+/* ================             Peripheral declaration             ================ */
+/* ================================================================================ */
+
+#define NRF_FICR                        ((NRF_FICR_Type           *) NRF_FICR_BASE)
+#define NRF_UICR                        ((NRF_UICR_Type           *) NRF_UICR_BASE)
+#define NRF_BPROT                       ((NRF_BPROT_Type          *) NRF_BPROT_BASE)
+#define NRF_POWER                       ((NRF_POWER_Type          *) NRF_POWER_BASE)
+#define NRF_CLOCK                       ((NRF_CLOCK_Type          *) NRF_CLOCK_BASE)
+#define NRF_RADIO                       ((NRF_RADIO_Type          *) NRF_RADIO_BASE)
+#define NRF_UARTE0                      ((NRF_UARTE_Type          *) NRF_UARTE0_BASE)
+#define NRF_UART0                       ((NRF_UART_Type           *) NRF_UART0_BASE)
+#define NRF_SPIM0                       ((NRF_SPIM_Type           *) NRF_SPIM0_BASE)
+#define NRF_SPIS0                       ((NRF_SPIS_Type           *) NRF_SPIS0_BASE)
+#define NRF_TWIM0                       ((NRF_TWIM_Type           *) NRF_TWIM0_BASE)
+#define NRF_TWIS0                       ((NRF_TWIS_Type           *) NRF_TWIS0_BASE)
+#define NRF_SPI0                        ((NRF_SPI_Type            *) NRF_SPI0_BASE)
+#define NRF_TWI0                        ((NRF_TWI_Type            *) NRF_TWI0_BASE)
+#define NRF_SPIM1                       ((NRF_SPIM_Type           *) NRF_SPIM1_BASE)
+#define NRF_SPIS1                       ((NRF_SPIS_Type           *) NRF_SPIS1_BASE)
+#define NRF_TWIM1                       ((NRF_TWIM_Type           *) NRF_TWIM1_BASE)
+#define NRF_TWIS1                       ((NRF_TWIS_Type           *) NRF_TWIS1_BASE)
+#define NRF_SPI1                        ((NRF_SPI_Type            *) NRF_SPI1_BASE)
+#define NRF_TWI1                        ((NRF_TWI_Type            *) NRF_TWI1_BASE)
+#define NRF_NFCT                        ((NRF_NFCT_Type           *) NRF_NFCT_BASE)
+#define NRF_GPIOTE                      ((NRF_GPIOTE_Type         *) NRF_GPIOTE_BASE)
+#define NRF_SAADC                       ((NRF_SAADC_Type          *) NRF_SAADC_BASE)
+#define NRF_TIMER0                      ((NRF_TIMER_Type          *) NRF_TIMER0_BASE)
+#define NRF_TIMER1                      ((NRF_TIMER_Type          *) NRF_TIMER1_BASE)
+#define NRF_TIMER2                      ((NRF_TIMER_Type          *) NRF_TIMER2_BASE)
+#define NRF_RTC0                        ((NRF_RTC_Type            *) NRF_RTC0_BASE)
+#define NRF_TEMP                        ((NRF_TEMP_Type           *) NRF_TEMP_BASE)
+#define NRF_RNG                         ((NRF_RNG_Type            *) NRF_RNG_BASE)
+#define NRF_ECB                         ((NRF_ECB_Type            *) NRF_ECB_BASE)
+#define NRF_CCM                         ((NRF_CCM_Type            *) NRF_CCM_BASE)
+#define NRF_AAR                         ((NRF_AAR_Type            *) NRF_AAR_BASE)
+#define NRF_WDT                         ((NRF_WDT_Type            *) NRF_WDT_BASE)
+#define NRF_RTC1                        ((NRF_RTC_Type            *) NRF_RTC1_BASE)
+#define NRF_QDEC                        ((NRF_QDEC_Type           *) NRF_QDEC_BASE)
+#define NRF_COMP                        ((NRF_COMP_Type           *) NRF_COMP_BASE)
+#define NRF_LPCOMP                      ((NRF_LPCOMP_Type         *) NRF_LPCOMP_BASE)
+#define NRF_SWI0                        ((NRF_SWI_Type            *) NRF_SWI0_BASE)
+#define NRF_EGU0                        ((NRF_EGU_Type            *) NRF_EGU0_BASE)
+#define NRF_SWI1                        ((NRF_SWI_Type            *) NRF_SWI1_BASE)
+#define NRF_EGU1                        ((NRF_EGU_Type            *) NRF_EGU1_BASE)
+#define NRF_SWI2                        ((NRF_SWI_Type            *) NRF_SWI2_BASE)
+#define NRF_EGU2                        ((NRF_EGU_Type            *) NRF_EGU2_BASE)
+#define NRF_SWI3                        ((NRF_SWI_Type            *) NRF_SWI3_BASE)
+#define NRF_EGU3                        ((NRF_EGU_Type            *) NRF_EGU3_BASE)
+#define NRF_SWI4                        ((NRF_SWI_Type            *) NRF_SWI4_BASE)
+#define NRF_EGU4                        ((NRF_EGU_Type            *) NRF_EGU4_BASE)
+#define NRF_SWI5                        ((NRF_SWI_Type            *) NRF_SWI5_BASE)
+#define NRF_EGU5                        ((NRF_EGU_Type            *) NRF_EGU5_BASE)
+#define NRF_TIMER3                      ((NRF_TIMER_Type          *) NRF_TIMER3_BASE)
+#define NRF_TIMER4                      ((NRF_TIMER_Type          *) NRF_TIMER4_BASE)
+#define NRF_PWM0                        ((NRF_PWM_Type            *) NRF_PWM0_BASE)
+#define NRF_PDM                         ((NRF_PDM_Type            *) NRF_PDM_BASE)
+#define NRF_NVMC                        ((NRF_NVMC_Type           *) NRF_NVMC_BASE)
+#define NRF_PPI                         ((NRF_PPI_Type            *) NRF_PPI_BASE)
+#define NRF_MWU                         ((NRF_MWU_Type            *) NRF_MWU_BASE)
+#define NRF_PWM1                        ((NRF_PWM_Type            *) NRF_PWM1_BASE)
+#define NRF_PWM2                        ((NRF_PWM_Type            *) NRF_PWM2_BASE)
+#define NRF_SPIM2                       ((NRF_SPIM_Type           *) NRF_SPIM2_BASE)
+#define NRF_SPIS2                       ((NRF_SPIS_Type           *) NRF_SPIS2_BASE)
+#define NRF_SPI2                        ((NRF_SPI_Type            *) NRF_SPI2_BASE)
+#define NRF_RTC2                        ((NRF_RTC_Type            *) NRF_RTC2_BASE)
+#define NRF_I2S                         ((NRF_I2S_Type            *) NRF_I2S_BASE)
+#define NRF_FPU                         ((NRF_FPU_Type            *) NRF_FPU_BASE)
+#define NRF_P0                          ((NRF_GPIO_Type           *) NRF_P0_BASE)
+
+
+/** @} */ /* End of group Device_Peripheral_Registers */
+/** @} */ /* End of group nrf52 */
+/** @} */ /* End of group Nordic Semiconductor */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif  /* nrf52_H */
+
diff --git a/ports/nrf/device/nrf52/nrf52840.h b/ports/nrf/device/nrf52/nrf52840.h
new file mode 100644
index 0000000000..92a40f4c08
--- /dev/null
+++ b/ports/nrf/device/nrf52/nrf52840.h
@@ -0,0 +1,2417 @@
+
+/****************************************************************************************************//**
+ * @file     nrf52840.h
+ *
+ * @brief    CMSIS Cortex-M4 Peripheral Access Layer Header File for
+ *           nrf52840 from Nordic Semiconductor.
+ *
+ * @version  V1
+ * @date     18. November 2016
+ *
+ * @note     Generated with SVDConv V2.81d 
+ *           from CMSIS SVD File 'nrf52840.svd' Version 1,
+ *
+ * @par      Copyright (c) 2016, Nordic Semiconductor ASA
+ *           All rights reserved.
+ *           
+ *           Redistribution and use in source and binary forms, with or without
+ *           modification, are permitted provided that the following conditions are met:
+ *           
+ *           * Redistributions of source code must retain the above copyright notice, this
+ *           list of conditions and the following disclaimer.
+ *           
+ *           * Redistributions in binary form must reproduce the above copyright notice,
+ *           this list of conditions and the following disclaimer in the documentation
+ *           and/or other materials provided with the distribution.
+ *           
+ *           * Neither the name of Nordic Semiconductor ASA nor the names of its
+ *           contributors may be used to endorse or promote products derived from
+ *           this software without specific prior written permission.
+ *           
+ *           THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *           AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *           IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *           DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ *           FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *           DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ *           SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ *           CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ *           OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *           OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *           
+ *
+ *******************************************************************************************************/
+
+
+
+/** @addtogroup Nordic Semiconductor
+  * @{
+  */
+
+/** @addtogroup nrf52840
+  * @{
+  */
+
+#ifndef NRF52840_H
+#define NRF52840_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* -------------------------  Interrupt Number Definition  ------------------------ */
+
+typedef enum {
+/* -------------------  Cortex-M4 Processor Exceptions Numbers  ------------------- */
+  Reset_IRQn                    = -15,              /*!<   1  Reset Vector, invoked on Power up and warm reset                 */
+  NonMaskableInt_IRQn           = -14,              /*!<   2  Non maskable Interrupt, cannot be stopped or preempted           */
+  HardFault_IRQn                = -13,              /*!<   3  Hard Fault, all classes of Fault                                 */
+  MemoryManagement_IRQn         = -12,              /*!<   4  Memory Management, MPU mismatch, including Access Violation
+                                                         and No Match                                                          */
+  BusFault_IRQn                 = -11,              /*!<   5  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
+                                                         related Fault                                                         */
+  UsageFault_IRQn               = -10,              /*!<   6  Usage Fault, i.e. Undef Instruction, Illegal State Transition    */
+  SVCall_IRQn                   =  -5,              /*!<  11  System Service Call via SVC instruction                          */
+  DebugMonitor_IRQn             =  -4,              /*!<  12  Debug Monitor                                                    */
+  PendSV_IRQn                   =  -2,              /*!<  14  Pendable request for system service                              */
+  SysTick_IRQn                  =  -1,              /*!<  15  System Tick Timer                                                */
+/* ---------------------  nrf52840 Specific Interrupt Numbers  -------------------- */
+  POWER_CLOCK_IRQn              =   0,              /*!<   0  POWER_CLOCK                                                      */
+  RADIO_IRQn                    =   1,              /*!<   1  RADIO                                                            */
+  UARTE0_UART0_IRQn             =   2,              /*!<   2  UARTE0_UART0                                                     */
+  SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn=   3,      /*!<   3  SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0                                */
+  SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn=   4,      /*!<   4  SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1                                */
+  NFCT_IRQn                     =   5,              /*!<   5  NFCT                                                             */
+  GPIOTE_IRQn                   =   6,              /*!<   6  GPIOTE                                                           */
+  SAADC_IRQn                    =   7,              /*!<   7  SAADC                                                            */
+  TIMER0_IRQn                   =   8,              /*!<   8  TIMER0                                                           */
+  TIMER1_IRQn                   =   9,              /*!<   9  TIMER1                                                           */
+  TIMER2_IRQn                   =  10,              /*!<  10  TIMER2                                                           */
+  RTC0_IRQn                     =  11,              /*!<  11  RTC0                                                             */
+  TEMP_IRQn                     =  12,              /*!<  12  TEMP                                                             */
+  RNG_IRQn                      =  13,              /*!<  13  RNG                                                              */
+  ECB_IRQn                      =  14,              /*!<  14  ECB                                                              */
+  CCM_AAR_IRQn                  =  15,              /*!<  15  CCM_AAR                                                          */
+  WDT_IRQn                      =  16,              /*!<  16  WDT                                                              */
+  RTC1_IRQn                     =  17,              /*!<  17  RTC1                                                             */
+  QDEC_IRQn                     =  18,              /*!<  18  QDEC                                                             */
+  COMP_LPCOMP_IRQn              =  19,              /*!<  19  COMP_LPCOMP                                                      */
+  SWI0_EGU0_IRQn                =  20,              /*!<  20  SWI0_EGU0                                                        */
+  SWI1_EGU1_IRQn                =  21,              /*!<  21  SWI1_EGU1                                                        */
+  SWI2_EGU2_IRQn                =  22,              /*!<  22  SWI2_EGU2                                                        */
+  SWI3_EGU3_IRQn                =  23,              /*!<  23  SWI3_EGU3                                                        */
+  SWI4_EGU4_IRQn                =  24,              /*!<  24  SWI4_EGU4                                                        */
+  SWI5_EGU5_IRQn                =  25,              /*!<  25  SWI5_EGU5                                                        */
+  TIMER3_IRQn                   =  26,              /*!<  26  TIMER3                                                           */
+  TIMER4_IRQn                   =  27,              /*!<  27  TIMER4                                                           */
+  PWM0_IRQn                     =  28,              /*!<  28  PWM0                                                             */
+  PDM_IRQn                      =  29,              /*!<  29  PDM                                                              */
+  MWU_IRQn                      =  32,              /*!<  32  MWU                                                              */
+  PWM1_IRQn                     =  33,              /*!<  33  PWM1                                                             */
+  PWM2_IRQn                     =  34,              /*!<  34  PWM2                                                             */
+  SPIM2_SPIS2_SPI2_IRQn         =  35,              /*!<  35  SPIM2_SPIS2_SPI2                                                 */
+  RTC2_IRQn                     =  36,              /*!<  36  RTC2                                                             */
+  I2S_IRQn                      =  37,              /*!<  37  I2S                                                              */
+  FPU_IRQn                      =  38,              /*!<  38  FPU                                                              */
+  USBD_IRQn                     =  39,              /*!<  39  USBD                                                             */
+  UARTE1_IRQn                   =  40,              /*!<  40  UARTE1                                                           */
+  QSPI_IRQn                     =  41,              /*!<  41  QSPI                                                             */
+  CRYPTOCELL_IRQn               =  42,              /*!<  42  CRYPTOCELL                                                       */
+  SPIM3_IRQn                    =  43,              /*!<  43  SPIM3                                                            */
+  PWM3_IRQn                     =  45               /*!<  45  PWM3                                                             */
+} IRQn_Type;
+
+
+/** @addtogroup Configuration_of_CMSIS
+  * @{
+  */
+
+
+/* ================================================================================ */
+/* ================      Processor and Core Peripheral Section     ================ */
+/* ================================================================================ */
+
+/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */
+#define __CM4_REV                 0x0001            /*!< Cortex-M4 Core Revision                                               */
+#define __MPU_PRESENT                  1            /*!< MPU present or not                                                    */
+#define __NVIC_PRIO_BITS               3            /*!< Number of Bits used for Priority Levels                               */
+#define __Vendor_SysTickConfig         0            /*!< Set to 1 if different SysTick Config is used                          */
+#define __FPU_PRESENT                  1            /*!< FPU present or not                                                    */
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include "core_cm4.h"                               /*!< Cortex-M4 processor and core peripherals                              */
+#include "system_nrf52840.h"                        /*!< nrf52840 System                                                       */
+
+
+/* ================================================================================ */
+/* ================       Device Specific Peripheral Section       ================ */
+/* ================================================================================ */
+
+
+/** @addtogroup Device_Peripheral_Registers
+  * @{
+  */
+
+
+/* -------------------  Start of section using anonymous unions  ------------------ */
+#if defined(__CC_ARM)
+  #pragma push
+  #pragma anon_unions
+#elif defined(__ICCARM__)
+  #pragma language=extended
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+/* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+  #pragma warning 586
+#else
+  #warning Not supported compiler type
+#endif
+
+
+typedef struct {
+  __I  uint32_t  PART;                              /*!< Part code                                                             */
+  __I  uint32_t  VARIANT;                           /*!< Part variant (hardware version and production configuration).         */
+  __I  uint32_t  PACKAGE;                           /*!< Package option                                                        */
+  __I  uint32_t  RAM;                               /*!< RAM variant                                                           */
+  __I  uint32_t  FLASH;                             /*!< Flash variant                                                         */
+  __IO uint32_t  UNUSED0[3];                        /*!< Description collection[0]: Unspecified                                */
+} FICR_INFO_Type;
+
+typedef struct {
+  __I  uint32_t  A0;                                /*!< Slope definition A0.                                                  */
+  __I  uint32_t  A1;                                /*!< Slope definition A1.                                                  */
+  __I  uint32_t  A2;                                /*!< Slope definition A2.                                                  */
+  __I  uint32_t  A3;                                /*!< Slope definition A3.                                                  */
+  __I  uint32_t  A4;                                /*!< Slope definition A4.                                                  */
+  __I  uint32_t  A5;                                /*!< Slope definition A5.                                                  */
+  __I  uint32_t  B0;                                /*!< y-intercept B0.                                                       */
+  __I  uint32_t  B1;                                /*!< y-intercept B1.                                                       */
+  __I  uint32_t  B2;                                /*!< y-intercept B2.                                                       */
+  __I  uint32_t  B3;                                /*!< y-intercept B3.                                                       */
+  __I  uint32_t  B4;                                /*!< y-intercept B4.                                                       */
+  __I  uint32_t  B5;                                /*!< y-intercept B5.                                                       */
+  __I  uint32_t  T0;                                /*!< Segment end T0.                                                       */
+  __I  uint32_t  T1;                                /*!< Segment end T1.                                                       */
+  __I  uint32_t  T2;                                /*!< Segment end T2.                                                       */
+  __I  uint32_t  T3;                                /*!< Segment end T3.                                                       */
+  __I  uint32_t  T4;                                /*!< Segment end T4.                                                       */
+} FICR_TEMP_Type;
+
+typedef struct {
+  __I  uint32_t  TAGHEADER0;                        /*!< Default header for NFC Tag. Software can read these values to
+                                                         populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.            */
+  __I  uint32_t  TAGHEADER1;                        /*!< Default header for NFC Tag. Software can read these values to
+                                                         populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.            */
+  __I  uint32_t  TAGHEADER2;                        /*!< Default header for NFC Tag. Software can read these values to
+                                                         populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.            */
+  __I  uint32_t  TAGHEADER3;                        /*!< Default header for NFC Tag. Software can read these values to
+                                                         populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.            */
+} FICR_NFC_Type;
+
+typedef struct {
+  __IO uint32_t  POWER;                             /*!< Description cluster[0]: RAM0 power control register                   */
+  __O  uint32_t  POWERSET;                          /*!< Description cluster[0]: RAM0 power control set register               */
+  __O  uint32_t  POWERCLR;                          /*!< Description cluster[0]: RAM0 power control clear register             */
+  __I  uint32_t  RESERVED0;
+} POWER_RAM_Type;
+
+typedef struct {
+  __IO uint32_t  RTS;                               /*!< Pin select for RTS signal                                             */
+  __IO uint32_t  TXD;                               /*!< Pin select for TXD signal                                             */
+  __IO uint32_t  CTS;                               /*!< Pin select for CTS signal                                             */
+  __IO uint32_t  RXD;                               /*!< Pin select for RXD signal                                             */
+} UARTE_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in receive buffer                             */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */
+} UARTE_RXD_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in transmit buffer                            */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */
+} UARTE_TXD_Type;
+
+typedef struct {
+  __IO uint32_t  RTS;                               /*!< Pin select for RTS                                                    */
+  __IO uint32_t  TXD;                               /*!< Pin select for TXD                                                    */
+  __IO uint32_t  CTS;                               /*!< Pin select for CTS                                                    */
+  __IO uint32_t  RXD;                               /*!< Pin select for RXD                                                    */
+} UART_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  SCK;                               /*!< Pin select for SCK                                                    */
+  __IO uint32_t  MOSI;                              /*!< Pin select for MOSI signal                                            */
+  __IO uint32_t  MISO;                              /*!< Pin select for MISO signal                                            */
+  __IO uint32_t  CSN;                               /*!< Pin select for CSN                                                    */
+} SPIM_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in receive buffer                             */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */
+  __IO uint32_t  LIST;                              /*!< EasyDMA list type                                                     */
+} SPIM_RXD_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
+  __IO uint32_t  MAXCNT;                            /*!< Number of bytes in transmit buffer                                    */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */
+  __IO uint32_t  LIST;                              /*!< EasyDMA list type                                                     */
+} SPIM_TXD_Type;
+
+typedef struct {
+  __IO uint32_t  RXDELAY;                           /*!< Sample delay for input serial data on MISO                            */
+  __IO uint32_t  CSNDUR;                            /*!< Minimum duration between edge of CSN and edge of SCK and minimum
+                                                         duration CSN must stay high between transactions                      */
+} SPIM_IFTIMING_Type;
+
+typedef struct {
+  __IO uint32_t  SCK;                               /*!< Pin select for SCK                                                    */
+  __IO uint32_t  MISO;                              /*!< Pin select for MISO signal                                            */
+  __IO uint32_t  MOSI;                              /*!< Pin select for MOSI signal                                            */
+  __IO uint32_t  CSN;                               /*!< Pin select for CSN signal                                             */
+} SPIS_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< RXD data pointer                                                      */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in receive buffer                             */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes received in last granted transaction                  */
+} SPIS_RXD_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< TXD data pointer                                                      */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in transmit buffer                            */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transmitted in last granted transaction               */
+} SPIS_TXD_Type;
+
+typedef struct {
+  __IO uint32_t  SCL;                               /*!< Pin select for SCL signal                                             */
+  __IO uint32_t  SDA;                               /*!< Pin select for SDA signal                                             */
+} TWIM_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in receive buffer                             */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */
+  __IO uint32_t  LIST;                              /*!< EasyDMA list type                                                     */
+} TWIM_RXD_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in transmit buffer                            */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */
+  __IO uint32_t  LIST;                              /*!< EasyDMA list type                                                     */
+} TWIM_TXD_Type;
+
+typedef struct {
+  __IO uint32_t  SCL;                               /*!< Pin select for SCL signal                                             */
+  __IO uint32_t  SDA;                               /*!< Pin select for SDA signal                                             */
+} TWIS_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< RXD Data pointer                                                      */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in RXD buffer                                 */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last RXD transaction               */
+} TWIS_RXD_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< TXD Data pointer                                                      */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in TXD buffer                                 */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last TXD transaction               */
+} TWIS_TXD_Type;
+
+typedef struct {
+  __IO uint32_t  SCK;                               /*!< Pin select for SCK                                                    */
+  __IO uint32_t  MOSI;                              /*!< Pin select for MOSI signal                                            */
+  __IO uint32_t  MISO;                              /*!< Pin select for MISO signal                                            */
+} SPI_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  SCL;                               /*!< Pin select for SCL                                                    */
+  __IO uint32_t  SDA;                               /*!< Pin select for SDA                                                    */
+} TWI_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  RX;                                /*!< Result of last incoming frame                                         */
+} NFCT_FRAMESTATUS_Type;
+
+typedef struct {
+  __IO uint32_t  FRAMECONFIG;                       /*!< Configuration of outgoing frames                                      */
+  __IO uint32_t  AMOUNT;                            /*!< Size of outgoing frame                                                */
+} NFCT_TXD_Type;
+
+typedef struct {
+  __IO uint32_t  FRAMECONFIG;                       /*!< Configuration of incoming frames                                      */
+  __I  uint32_t  AMOUNT;                            /*!< Size of last incoming frame                                           */
+} NFCT_RXD_Type;
+
+typedef struct {
+  __IO uint32_t  LIMITH;                            /*!< Description cluster[0]: Last results is equal or above CH[0].LIMIT.HIGH */
+  __IO uint32_t  LIMITL;                            /*!< Description cluster[0]: Last results is equal or below CH[0].LIMIT.LOW */
+} SAADC_EVENTS_CH_Type;
+
+typedef struct {
+  __IO uint32_t  PSELP;                             /*!< Description cluster[0]: Input positive pin selection for CH[0]        */
+  __IO uint32_t  PSELN;                             /*!< Description cluster[0]: Input negative pin selection for CH[0]        */
+  __IO uint32_t  CONFIG;                            /*!< Description cluster[0]: Input configuration for CH[0]                 */
+  __IO uint32_t  LIMIT;                             /*!< Description cluster[0]: High/low limits for event monitoring
+                                                         a channel                                                             */
+} SAADC_CH_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of buffer words to transfer                            */
+  __I  uint32_t  AMOUNT;                            /*!< Number of buffer words transferred since last START                   */
+} SAADC_RESULT_Type;
+
+typedef struct {
+  __IO uint32_t  LED;                               /*!< Pin select for LED signal                                             */
+  __IO uint32_t  A;                                 /*!< Pin select for A signal                                               */
+  __IO uint32_t  B;                                 /*!< Pin select for B signal                                               */
+} QDEC_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Description cluster[0]: Beginning address in Data RAM of sequence
+                                                         A                                                                     */
+  __IO uint32_t  CNT;                               /*!< Description cluster[0]: Amount of values (duty cycles) in sequence
+                                                         A                                                                     */
+  __IO uint32_t  REFRESH;                           /*!< Description cluster[0]: Amount of additional PWM periods between
+                                                         samples loaded to compare register (load every CNT+1 PWM periods)     */
+  __IO uint32_t  ENDDELAY;                          /*!< Description cluster[0]: Time added after the sequence                 */
+  __I  uint32_t  RESERVED1[4];
+} PWM_SEQ_Type;
+
+typedef struct {
+  __IO uint32_t  OUT[4];                            /*!< Description collection[0]: Output pin select for PWM channel
+                                                         0                                                                     */
+} PWM_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  CLK;                               /*!< Pin number configuration for PDM CLK signal                           */
+  __IO uint32_t  DIN;                               /*!< Pin number configuration for PDM DIN signal                           */
+} PDM_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< RAM address pointer to write samples to with EasyDMA                  */
+  __IO uint32_t  MAXCNT;                            /*!< Number of samples to allocate memory for in EasyDMA mode              */
+} PDM_SAMPLE_Type;
+
+typedef struct {
+  __IO uint32_t  ADDR;                              /*!< Description cluster[0]: Configure the word-aligned start address
+                                                         of region 0 to protect                                                */
+  __IO uint32_t  SIZE;                              /*!< Description cluster[0]: Size of region to protect counting from
+                                                         address ACL[0].ADDR. Write '0' as no effect.                          */
+  __IO uint32_t  PERM;                              /*!< Description cluster[0]: Access permissions for region 0 as defined
+                                                         by start address ACL[0].ADDR and size ACL[0].SIZE                     */
+  __IO uint32_t  UNUSED0;                           /*!< Unspecified                                                           */
+} ACL_ACL_Type;
+
+typedef struct {
+  __O  uint32_t  EN;                                /*!< Description cluster[0]: Enable channel group 0                        */
+  __O  uint32_t  DIS;                               /*!< Description cluster[0]: Disable channel group 0                       */
+} PPI_TASKS_CHG_Type;
+
+typedef struct {
+  __IO uint32_t  EEP;                               /*!< Description cluster[0]: Channel 0 event end-point                     */
+  __IO uint32_t  TEP;                               /*!< Description cluster[0]: Channel 0 task end-point                      */
+} PPI_CH_Type;
+
+typedef struct {
+  __IO uint32_t  TEP;                               /*!< Description cluster[0]: Channel 0 task end-point                      */
+} PPI_FORK_Type;
+
+typedef struct {
+  __IO uint32_t  WA;                                /*!< Description cluster[0]: Write access to region 0 detected             */
+  __IO uint32_t  RA;                                /*!< Description cluster[0]: Read access to region 0 detected              */
+} MWU_EVENTS_REGION_Type;
+
+typedef struct {
+  __IO uint32_t  WA;                                /*!< Description cluster[0]: Write access to peripheral region 0
+                                                         detected                                                              */
+  __IO uint32_t  RA;                                /*!< Description cluster[0]: Read access to peripheral region 0 detected   */
+} MWU_EVENTS_PREGION_Type;
+
+typedef struct {
+  __IO uint32_t  SUBSTATWA;                         /*!< Description cluster[0]: Source of event/interrupt in region
+                                                         0, write access detected while corresponding subregion was enabled
+                                                          for watching                                                         */
+  __IO uint32_t  SUBSTATRA;                         /*!< Description cluster[0]: Source of event/interrupt in region
+                                                         0, read access detected while corresponding subregion was enabled
+                                                          for watching                                                         */
+} MWU_PERREGION_Type;
+
+typedef struct {
+  __IO uint32_t  START;                             /*!< Description cluster[0]: Start address for region 0                    */
+  __IO uint32_t  END;                               /*!< Description cluster[0]: End address of region 0                       */
+  __I  uint32_t  RESERVED2[2];
+} MWU_REGION_Type;
+
+typedef struct {
+  __I  uint32_t  START;                             /*!< Description cluster[0]: Reserved for future use                       */
+  __I  uint32_t  END;                               /*!< Description cluster[0]: Reserved for future use                       */
+  __IO uint32_t  SUBS;                              /*!< Description cluster[0]: Subregions of region 0                        */
+  __I  uint32_t  RESERVED3;
+} MWU_PREGION_Type;
+
+typedef struct {
+  __IO uint32_t  MODE;                              /*!< I2S mode.                                                             */
+  __IO uint32_t  RXEN;                              /*!< Reception (RX) enable.                                                */
+  __IO uint32_t  TXEN;                              /*!< Transmission (TX) enable.                                             */
+  __IO uint32_t  MCKEN;                             /*!< Master clock generator enable.                                        */
+  __IO uint32_t  MCKFREQ;                           /*!< Master clock generator frequency.                                     */
+  __IO uint32_t  RATIO;                             /*!< MCK / LRCK ratio.                                                     */
+  __IO uint32_t  SWIDTH;                            /*!< Sample width.                                                         */
+  __IO uint32_t  ALIGN;                             /*!< Alignment of sample within a frame.                                   */
+  __IO uint32_t  FORMAT;                            /*!< Frame format.                                                         */
+  __IO uint32_t  CHANNELS;                          /*!< Enable channels.                                                      */
+} I2S_CONFIG_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Receive buffer RAM start address.                                     */
+} I2S_RXD_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Transmit buffer RAM start address.                                    */
+} I2S_TXD_Type;
+
+typedef struct {
+  __IO uint32_t  MAXCNT;                            /*!< Size of RXD and TXD buffers.                                          */
+} I2S_RXTXD_Type;
+
+typedef struct {
+  __IO uint32_t  MCK;                               /*!< Pin select for MCK signal.                                            */
+  __IO uint32_t  SCK;                               /*!< Pin select for SCK signal.                                            */
+  __IO uint32_t  LRCK;                              /*!< Pin select for LRCK signal.                                           */
+  __IO uint32_t  SDIN;                              /*!< Pin select for SDIN signal.                                           */
+  __IO uint32_t  SDOUT;                             /*!< Pin select for SDOUT signal.                                          */
+} I2S_PSEL_Type;
+
+typedef struct {
+  __I  uint32_t  EPIN[8];                           /*!< Description collection[0]: IN endpoint halted status. Can be
+                                                         used as is as response to a GetStatus() request to endpoint.          */
+  __I  uint32_t  RESERVED4;
+  __I  uint32_t  EPOUT[8];                          /*!< Description collection[0]: OUT endpoint halted status. Can be
+                                                         used as is as response to a GetStatus() request to endpoint.          */
+} USBD_HALTED_Type;
+
+typedef struct {
+  __IO uint32_t  EPOUT[8];                          /*!< Description collection[0]: Amount of bytes received last in
+                                                         the data stage of this OUT endpoint                                   */
+  __IO uint32_t  ISOOUT;                            /*!< Amount of bytes received last on this iso OUT data endpoint           */
+} USBD_SIZE_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Description cluster[0]: Data pointer                                  */
+  __IO uint32_t  MAXCNT;                            /*!< Description cluster[0]: Maximum number of bytes to transfer           */
+  __I  uint32_t  AMOUNT;                            /*!< Description cluster[0]: Number of bytes transferred in the last
+                                                         transaction                                                           */
+  __I  uint32_t  RESERVED5[2];
+} USBD_EPIN_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes to transfer                                   */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */
+} USBD_ISOIN_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Description cluster[0]: Data pointer                                  */
+  __IO uint32_t  MAXCNT;                            /*!< Description cluster[0]: Maximum number of bytes to transfer           */
+  __I  uint32_t  AMOUNT;                            /*!< Description cluster[0]: Number of bytes transferred in the last
+                                                         transaction                                                           */
+  __I  uint32_t  RESERVED6[2];
+} USBD_EPOUT_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes to transfer                                   */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */
+} USBD_ISOOUT_Type;
+
+typedef struct {
+  __IO uint32_t  SRC;                               /*!< Flash memory source address                                           */
+  __IO uint32_t  DST;                               /*!< RAM destination address                                               */
+  __IO uint32_t  CNT;                               /*!< Read transfer length                                                  */
+} QSPI_READ_Type;
+
+typedef struct {
+  __IO uint32_t  DST;                               /*!< Flash destination address                                             */
+  __IO uint32_t  SRC;                               /*!< RAM source address                                                    */
+  __IO uint32_t  CNT;                               /*!< Write transfer length                                                 */
+} QSPI_WRITE_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Start address of flash block to be erased                             */
+  __IO uint32_t  LEN;                               /*!< Size of block to be erased.                                           */
+} QSPI_ERASE_Type;
+
+typedef struct {
+  __IO uint32_t  SCK;                               /*!< Pin select for serial clock SCK                                       */
+  __IO uint32_t  CSN;                               /*!< Pin select for chip select signal CSN.                                */
+  __I  uint32_t  RESERVED7;
+  __IO uint32_t  IO0;                               /*!< Pin select for serial data MOSI/IO0.                                  */
+  __IO uint32_t  IO1;                               /*!< Pin select for serial data MISO/IO1.                                  */
+  __IO uint32_t  IO2;                               /*!< Pin select for serial data IO2.                                       */
+  __IO uint32_t  IO3;                               /*!< Pin select for serial data IO3.                                       */
+} QSPI_PSEL_Type;
+
+
+/* ================================================================================ */
+/* ================                      FICR                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Factory Information Configuration Registers (FICR)
+  */
+
+typedef struct {                                    /*!< FICR Structure                                                        */
+  __I  uint32_t  RESERVED0[4];
+  __I  uint32_t  CODEPAGESIZE;                      /*!< Code memory page size                                                 */
+  __I  uint32_t  CODESIZE;                          /*!< Code memory size                                                      */
+  __I  uint32_t  RESERVED1[18];
+  __I  uint32_t  DEVICEID[2];                       /*!< Description collection[0]: Device identifier                          */
+  __I  uint32_t  RESERVED2[6];
+  __I  uint32_t  ER[4];                             /*!< Description collection[0]: Encryption root, word 0                    */
+  __I  uint32_t  IR[4];                             /*!< Description collection[0]: Identity Root, word 0                      */
+  __I  uint32_t  DEVICEADDRTYPE;                    /*!< Device address type                                                   */
+  __I  uint32_t  DEVICEADDR[2];                     /*!< Description collection[0]: Device address 0                           */
+  __I  uint32_t  RESERVED3[21];
+  FICR_INFO_Type INFO;                              /*!< Device info                                                           */
+  __I  uint32_t  RESERVED4[185];
+  FICR_TEMP_Type TEMP;                              /*!< Registers storing factory TEMP module linearization coefficients      */
+  __I  uint32_t  RESERVED5[2];
+  FICR_NFC_Type NFC;                                /*!< Unspecified                                                           */
+} NRF_FICR_Type;
+
+
+/* ================================================================================ */
+/* ================                      UICR                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief User Information Configuration Registers (UICR)
+  */
+
+typedef struct {                                    /*!< UICR Structure                                                        */
+  __IO uint32_t  UNUSED0;                           /*!< Unspecified                                                           */
+  __IO uint32_t  UNUSED1;                           /*!< Unspecified                                                           */
+  __IO uint32_t  UNUSED2;                           /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED0;
+  __IO uint32_t  UNUSED3;                           /*!< Unspecified                                                           */
+  __IO uint32_t  NRFFW[15];                         /*!< Description collection[0]: Reserved for Nordic firmware design        */
+  __IO uint32_t  NRFHW[12];                         /*!< Description collection[0]: Reserved for Nordic hardware design        */
+  __IO uint32_t  CUSTOMER[32];                      /*!< Description collection[0]: Reserved for customer                      */
+  __I  uint32_t  RESERVED1[64];
+  __IO uint32_t  PSELRESET[2];                      /*!< Description collection[0]: Mapping of the nRESET function             */
+  __IO uint32_t  APPROTECT;                         /*!< Access port protection                                                */
+  __IO uint32_t  NFCPINS;                           /*!< Setting of pins dedicated to NFC functionality: NFC antenna
+                                                         or GPIO                                                               */
+  __I  uint32_t  RESERVED2[60];
+  __IO uint32_t  EXTSUPPLY;                         /*!< Enable external circuitry to be supplied from VDD pin. Applicable
+                                                         in 'High voltage mode' only.                                          */
+  __IO uint32_t  REGOUT0;                           /*!< GPIO reference voltage / external output supply voltage in 'High
+                                                         voltage mode'.                                                        */
+} NRF_UICR_Type;
+
+
+/* ================================================================================ */
+/* ================                      POWER                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Power control (POWER)
+  */
+
+typedef struct {                                    /*!< POWER Structure                                                       */
+  __I  uint32_t  RESERVED0[30];
+  __O  uint32_t  TASKS_CONSTLAT;                    /*!< Enable constant latency mode                                          */
+  __O  uint32_t  TASKS_LOWPWR;                      /*!< Enable low power mode (variable latency)                              */
+  __I  uint32_t  RESERVED1[34];
+  __IO uint32_t  EVENTS_POFWARN;                    /*!< Power failure warning                                                 */
+  __I  uint32_t  RESERVED2[2];
+  __IO uint32_t  EVENTS_SLEEPENTER;                 /*!< CPU entered WFI/WFE sleep                                             */
+  __IO uint32_t  EVENTS_SLEEPEXIT;                  /*!< CPU exited WFI/WFE sleep                                              */
+  __IO uint32_t  EVENTS_USBDETECTED;                /*!< Voltage supply detected on VBUS                                       */
+  __IO uint32_t  EVENTS_USBREMOVED;                 /*!< Voltage supply removed from VBUS                                      */
+  __IO uint32_t  EVENTS_USBPWRRDY;                  /*!< USB 3.3 V supply ready                                                */
+  __I  uint32_t  RESERVED3[119];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED4[61];
+  __IO uint32_t  RESETREAS;                         /*!< Reset reason                                                          */
+  __I  uint32_t  RESERVED5[9];
+  __I  uint32_t  RAMSTATUS;                         /*!< Deprecated register - RAM status register                             */
+  __I  uint32_t  RESERVED6[3];
+  __I  uint32_t  USBREGSTATUS;                      /*!< USB supply status                                                     */
+  __I  uint32_t  RESERVED7[49];
+  __O  uint32_t  SYSTEMOFF;                         /*!< System OFF register                                                   */
+  __I  uint32_t  RESERVED8[3];
+  __IO uint32_t  POFCON;                            /*!< Power failure comparator configuration                                */
+  __I  uint32_t  RESERVED9[2];
+  __IO uint32_t  GPREGRET;                          /*!< General purpose retention register                                    */
+  __IO uint32_t  GPREGRET2;                         /*!< General purpose retention register                                    */
+  __I  uint32_t  RESERVED10[21];
+  __IO uint32_t  DCDCEN;                            /*!< Enable DC/DC converter for REG1 stage.                                */
+  __I  uint32_t  RESERVED11;
+  __IO uint32_t  DCDCEN0;                           /*!< Enable DC/DC converter for REG0 stage.                                */
+  __I  uint32_t  RESERVED12[47];
+  __I  uint32_t  MAINREGSTATUS;                     /*!< Main supply status                                                    */
+  __I  uint32_t  RESERVED13[175];
+  POWER_RAM_Type RAM[9];                            /*!< Unspecified                                                           */
+} NRF_POWER_Type;
+
+
+/* ================================================================================ */
+/* ================                      CLOCK                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Clock control (CLOCK)
+  */
+
+typedef struct {                                    /*!< CLOCK Structure                                                       */
+  __O  uint32_t  TASKS_HFCLKSTART;                  /*!< Start HFCLK crystal oscillator                                        */
+  __O  uint32_t  TASKS_HFCLKSTOP;                   /*!< Stop HFCLK crystal oscillator                                         */
+  __O  uint32_t  TASKS_LFCLKSTART;                  /*!< Start LFCLK source                                                    */
+  __O  uint32_t  TASKS_LFCLKSTOP;                   /*!< Stop LFCLK source                                                     */
+  __O  uint32_t  TASKS_CAL;                         /*!< Start calibration of LFRC or LFULP oscillator                         */
+  __O  uint32_t  TASKS_CTSTART;                     /*!< Start calibration timer                                               */
+  __O  uint32_t  TASKS_CTSTOP;                      /*!< Stop calibration timer                                                */
+  __I  uint32_t  RESERVED0[57];
+  __IO uint32_t  EVENTS_HFCLKSTARTED;               /*!< HFCLK oscillator started                                              */
+  __IO uint32_t  EVENTS_LFCLKSTARTED;               /*!< LFCLK started                                                         */
+  __I  uint32_t  RESERVED1;
+  __IO uint32_t  EVENTS_DONE;                       /*!< Calibration of LFCLK RC oscillator complete event                     */
+  __IO uint32_t  EVENTS_CTTO;                       /*!< Calibration timer timeout                                             */
+  __I  uint32_t  RESERVED2[124];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[63];
+  __I  uint32_t  HFCLKRUN;                          /*!< Status indicating that HFCLKSTART task has been triggered             */
+  __I  uint32_t  HFCLKSTAT;                         /*!< HFCLK status                                                          */
+  __I  uint32_t  RESERVED4;
+  __I  uint32_t  LFCLKRUN;                          /*!< Status indicating that LFCLKSTART task has been triggered             */
+  __I  uint32_t  LFCLKSTAT;                         /*!< LFCLK status                                                          */
+  __I  uint32_t  LFCLKSRCCOPY;                      /*!< Copy of LFCLKSRC register, set when LFCLKSTART task was triggered     */
+  __I  uint32_t  RESERVED5[62];
+  __IO uint32_t  LFCLKSRC;                          /*!< Clock source for the LFCLK                                            */
+  __I  uint32_t  RESERVED6[7];
+  __IO uint32_t  CTIV;                              /*!< Calibration timer interval                                            */
+  __I  uint32_t  RESERVED7[8];
+  __IO uint32_t  TRACECONFIG;                       /*!< Clocking options for the Trace Port debug interface                   */
+} NRF_CLOCK_Type;
+
+
+/* ================================================================================ */
+/* ================                      RADIO                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief 2.4 GHz Radio (RADIO)
+  */
+
+typedef struct {                                    /*!< RADIO Structure                                                       */
+  __O  uint32_t  TASKS_TXEN;                        /*!< Enable RADIO in TX mode                                               */
+  __O  uint32_t  TASKS_RXEN;                        /*!< Enable RADIO in RX mode                                               */
+  __O  uint32_t  TASKS_START;                       /*!< Start RADIO                                                           */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop RADIO                                                            */
+  __O  uint32_t  TASKS_DISABLE;                     /*!< Disable RADIO                                                         */
+  __O  uint32_t  TASKS_RSSISTART;                   /*!< Start the RSSI and take one single sample of the receive signal
+                                                         strength.                                                             */
+  __O  uint32_t  TASKS_RSSISTOP;                    /*!< Stop the RSSI measurement                                             */
+  __O  uint32_t  TASKS_BCSTART;                     /*!< Start the bit counter                                                 */
+  __O  uint32_t  TASKS_BCSTOP;                      /*!< Stop the bit counter                                                  */
+  __O  uint32_t  TASKS_EDSTART;                     /*!< Start the Energy Detect measurement used in IEEE 802.15.4 mode        */
+  __O  uint32_t  TASKS_EDSTOP;                      /*!< Stop the Energy Detect measurement                                    */
+  __O  uint32_t  TASKS_CCASTART;                    /*!< Start the Clear Channel Assessment used in IEEE 802.15.4 mode         */
+  __O  uint32_t  TASKS_CCASTOP;                     /*!< Stop the Clear Channel Assessment                                     */
+  __I  uint32_t  RESERVED0[51];
+  __IO uint32_t  EVENTS_READY;                      /*!< RADIO has ramped up and is ready to be started                        */
+  __IO uint32_t  EVENTS_ADDRESS;                    /*!< Address sent or received                                              */
+  __IO uint32_t  EVENTS_PAYLOAD;                    /*!< Packet payload sent or received                                       */
+  __IO uint32_t  EVENTS_END;                        /*!< Packet sent or received                                               */
+  __IO uint32_t  EVENTS_DISABLED;                   /*!< RADIO has been disabled                                               */
+  __IO uint32_t  EVENTS_DEVMATCH;                   /*!< A device address match occurred on the last received packet           */
+  __IO uint32_t  EVENTS_DEVMISS;                    /*!< No device address match occurred on the last received packet          */
+  __IO uint32_t  EVENTS_RSSIEND;                    /*!< Sampling of receive signal strength complete.                         */
+  __I  uint32_t  RESERVED1[2];
+  __IO uint32_t  EVENTS_BCMATCH;                    /*!< Bit counter reached bit count value.                                  */
+  __I  uint32_t  RESERVED2;
+  __IO uint32_t  EVENTS_CRCOK;                      /*!< Packet received with CRC ok                                           */
+  __IO uint32_t  EVENTS_CRCERROR;                   /*!< Packet received with CRC error                                        */
+  __IO uint32_t  EVENTS_FRAMESTART;                 /*!< IEEE 802.15.4 length field received                                   */
+  __IO uint32_t  EVENTS_EDEND;                      /*!< Sampling of Energy Detection complete. A new ED sample is ready
+                                                         for readout from the RADIO.EDSAMPLE register                          */
+  __IO uint32_t  EVENTS_EDSTOPPED;                  /*!< The sampling of Energy Detection has stopped                          */
+  __IO uint32_t  EVENTS_CCAIDLE;                    /*!< Wireless medium in idle - clear to send                               */
+  __IO uint32_t  EVENTS_CCABUSY;                    /*!< Wireless medium busy - do not send                                    */
+  __IO uint32_t  EVENTS_CCASTOPPED;                 /*!< The CCA has stopped                                                   */
+  __IO uint32_t  EVENTS_RATEBOOST;                  /*!< Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit
+                                                         to Ble_LR500Kbit.                                                     */
+  __IO uint32_t  EVENTS_TXREADY;                    /*!< RADIO has ramped up and is ready to be started TX path                */
+  __IO uint32_t  EVENTS_RXREADY;                    /*!< RADIO has ramped up and is ready to be started RX path                */
+  __IO uint32_t  EVENTS_MHRMATCH;                   /*!< MAC Header match found.                                               */
+  __I  uint32_t  RESERVED3[40];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED4[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED5[61];
+  __I  uint32_t  CRCSTATUS;                         /*!< CRC status                                                            */
+  __I  uint32_t  RESERVED6;
+  __I  uint32_t  RXMATCH;                           /*!< Received address                                                      */
+  __I  uint32_t  RXCRC;                             /*!< CRC field of previously received packet                               */
+  __I  uint32_t  DAI;                               /*!< Device address match index                                            */
+  __I  uint32_t  RESERVED7[60];
+  __IO uint32_t  PACKETPTR;                         /*!< Packet pointer                                                        */
+  __IO uint32_t  FREQUENCY;                         /*!< Frequency                                                             */
+  __IO uint32_t  TXPOWER;                           /*!< Output power                                                          */
+  __IO uint32_t  MODE;                              /*!< Data rate and modulation                                              */
+  __IO uint32_t  PCNF0;                             /*!< Packet configuration register 0                                       */
+  __IO uint32_t  PCNF1;                             /*!< Packet configuration register 1                                       */
+  __IO uint32_t  BASE0;                             /*!< Base address 0                                                        */
+  __IO uint32_t  BASE1;                             /*!< Base address 1                                                        */
+  __IO uint32_t  PREFIX0;                           /*!< Prefixes bytes for logical addresses 0-3                              */
+  __IO uint32_t  PREFIX1;                           /*!< Prefixes bytes for logical addresses 4-7                              */
+  __IO uint32_t  TXADDRESS;                         /*!< Transmit address select                                               */
+  __IO uint32_t  RXADDRESSES;                       /*!< Receive address select                                                */
+  __IO uint32_t  CRCCNF;                            /*!< CRC configuration                                                     */
+  __IO uint32_t  CRCPOLY;                           /*!< CRC polynomial                                                        */
+  __IO uint32_t  CRCINIT;                           /*!< CRC initial value                                                     */
+  __I  uint32_t  RESERVED8;
+  __IO uint32_t  TIFS;                              /*!< Inter Frame Spacing in us                                             */
+  __I  uint32_t  RSSISAMPLE;                        /*!< RSSI sample                                                           */
+  __I  uint32_t  RESERVED9;
+  __I  uint32_t  STATE;                             /*!< Current radio state                                                   */
+  __IO uint32_t  DATAWHITEIV;                       /*!< Data whitening initial value                                          */
+  __I  uint32_t  RESERVED10[2];
+  __IO uint32_t  BCC;                               /*!< Bit counter compare                                                   */
+  __I  uint32_t  RESERVED11[39];
+  __IO uint32_t  DAB[8];                            /*!< Description collection[0]: Device address base segment 0              */
+  __IO uint32_t  DAP[8];                            /*!< Description collection[0]: Device address prefix 0                    */
+  __IO uint32_t  DACNF;                             /*!< Device address match configuration                                    */
+  __IO uint32_t  MHRMATCHCONF;                      /*!< Search Pattern Configuration                                          */
+  __IO uint32_t  MHRMATCHMAS;                       /*!< Pattern mask                                                          */
+  __I  uint32_t  RESERVED12;
+  __IO uint32_t  MODECNF0;                          /*!< Radio mode configuration register 0                                   */
+  __I  uint32_t  RESERVED13[3];
+  __IO uint32_t  SFD;                               /*!< IEEE 802.15.4 Start of Frame Delimiter                                */
+  __IO uint32_t  EDCNT;                             /*!< IEEE 802.15.4 Energy Detect Loop Count                                */
+  __IO uint32_t  EDSAMPLE;                          /*!< IEEE 802.15.4 Energy Detect Level                                     */
+  __IO uint32_t  CCACTRL;                           /*!< IEEE 802.15.4 Clear Channel Assessment Control                        */
+  __I  uint32_t  RESERVED14[611];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control                                              */
+} NRF_RADIO_Type;
+
+
+/* ================================================================================ */
+/* ================                      UARTE                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief UART with EasyDMA 0 (UARTE)
+  */
+
+typedef struct {                                    /*!< UARTE Structure                                                       */
+  __O  uint32_t  TASKS_STARTRX;                     /*!< Start UART receiver                                                   */
+  __O  uint32_t  TASKS_STOPRX;                      /*!< Stop UART receiver                                                    */
+  __O  uint32_t  TASKS_STARTTX;                     /*!< Start UART transmitter                                                */
+  __O  uint32_t  TASKS_STOPTX;                      /*!< Stop UART transmitter                                                 */
+  __I  uint32_t  RESERVED0[7];
+  __O  uint32_t  TASKS_FLUSHRX;                     /*!< Flush RX FIFO into RX buffer                                          */
+  __I  uint32_t  RESERVED1[52];
+  __IO uint32_t  EVENTS_CTS;                        /*!< CTS is activated (set low). Clear To Send.                            */
+  __IO uint32_t  EVENTS_NCTS;                       /*!< CTS is deactivated (set high). Not Clear To Send.                     */
+  __IO uint32_t  EVENTS_RXDRDY;                     /*!< Data received in RXD (but potentially not yet transferred to
+                                                         Data RAM)                                                             */
+  __I  uint32_t  RESERVED2;
+  __IO uint32_t  EVENTS_ENDRX;                      /*!< Receive buffer is filled up                                           */
+  __I  uint32_t  RESERVED3[2];
+  __IO uint32_t  EVENTS_TXDRDY;                     /*!< Data sent from TXD                                                    */
+  __IO uint32_t  EVENTS_ENDTX;                      /*!< Last TX byte transmitted                                              */
+  __IO uint32_t  EVENTS_ERROR;                      /*!< Error detected                                                        */
+  __I  uint32_t  RESERVED4[7];
+  __IO uint32_t  EVENTS_RXTO;                       /*!< Receiver timeout                                                      */
+  __I  uint32_t  RESERVED5;
+  __IO uint32_t  EVENTS_RXSTARTED;                  /*!< UART receiver has started                                             */
+  __IO uint32_t  EVENTS_TXSTARTED;                  /*!< UART transmitter has started                                          */
+  __I  uint32_t  RESERVED6;
+  __IO uint32_t  EVENTS_TXSTOPPED;                  /*!< Transmitter stopped                                                   */
+  __I  uint32_t  RESERVED7[41];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED8[63];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED9[93];
+  __IO uint32_t  ERRORSRC;                          /*!< Error source Note : this register is read / write one to clear.       */
+  __I  uint32_t  RESERVED10[31];
+  __IO uint32_t  ENABLE;                            /*!< Enable UART                                                           */
+  __I  uint32_t  RESERVED11;
+  UARTE_PSEL_Type PSEL;                             /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED12[3];
+  __IO uint32_t  BAUDRATE;                          /*!< Baud rate. Accuracy depends on the HFCLK source selected.             */
+  __I  uint32_t  RESERVED13[3];
+  UARTE_RXD_Type RXD;                               /*!< RXD EasyDMA channel                                                   */
+  __I  uint32_t  RESERVED14;
+  UARTE_TXD_Type TXD;                               /*!< TXD EasyDMA channel                                                   */
+  __I  uint32_t  RESERVED15[7];
+  __IO uint32_t  CONFIG;                            /*!< Configuration of parity and hardware flow control                     */
+} NRF_UARTE_Type;
+
+
+/* ================================================================================ */
+/* ================                      UART                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Universal Asynchronous Receiver/Transmitter (UART)
+  */
+
+typedef struct {                                    /*!< UART Structure                                                        */
+  __O  uint32_t  TASKS_STARTRX;                     /*!< Start UART receiver                                                   */
+  __O  uint32_t  TASKS_STOPRX;                      /*!< Stop UART receiver                                                    */
+  __O  uint32_t  TASKS_STARTTX;                     /*!< Start UART transmitter                                                */
+  __O  uint32_t  TASKS_STOPTX;                      /*!< Stop UART transmitter                                                 */
+  __I  uint32_t  RESERVED0[3];
+  __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend UART                                                          */
+  __I  uint32_t  RESERVED1[56];
+  __IO uint32_t  EVENTS_CTS;                        /*!< CTS is activated (set low). Clear To Send.                            */
+  __IO uint32_t  EVENTS_NCTS;                       /*!< CTS is deactivated (set high). Not Clear To Send.                     */
+  __IO uint32_t  EVENTS_RXDRDY;                     /*!< Data received in RXD                                                  */
+  __I  uint32_t  RESERVED2[4];
+  __IO uint32_t  EVENTS_TXDRDY;                     /*!< Data sent from TXD                                                    */
+  __I  uint32_t  RESERVED3;
+  __IO uint32_t  EVENTS_ERROR;                      /*!< Error detected                                                        */
+  __I  uint32_t  RESERVED4[7];
+  __IO uint32_t  EVENTS_RXTO;                       /*!< Receiver timeout                                                      */
+  __I  uint32_t  RESERVED5[46];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED6[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED7[93];
+  __IO uint32_t  ERRORSRC;                          /*!< Error source                                                          */
+  __I  uint32_t  RESERVED8[31];
+  __IO uint32_t  ENABLE;                            /*!< Enable UART                                                           */
+  __I  uint32_t  RESERVED9;
+  UART_PSEL_Type PSEL;                              /*!< Unspecified                                                           */
+  __I  uint32_t  RXD;                               /*!< RXD register                                                          */
+  __O  uint32_t  TXD;                               /*!< TXD register                                                          */
+  __I  uint32_t  RESERVED10;
+  __IO uint32_t  BAUDRATE;                          /*!< Baud rate. Accuracy depends on the HFCLK source selected.             */
+  __I  uint32_t  RESERVED11[17];
+  __IO uint32_t  CONFIG;                            /*!< Configuration of parity and hardware flow control                     */
+} NRF_UART_Type;
+
+
+/* ================================================================================ */
+/* ================                      SPIM                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM)
+  */
+
+typedef struct {                                    /*!< SPIM Structure                                                        */
+  __I  uint32_t  RESERVED0[4];
+  __O  uint32_t  TASKS_START;                       /*!< Start SPI transaction                                                 */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop SPI transaction                                                  */
+  __I  uint32_t  RESERVED1;
+  __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend SPI transaction                                               */
+  __O  uint32_t  TASKS_RESUME;                      /*!< Resume SPI transaction                                                */
+  __I  uint32_t  RESERVED2[56];
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< SPI transaction has stopped                                           */
+  __I  uint32_t  RESERVED3[2];
+  __IO uint32_t  EVENTS_ENDRX;                      /*!< End of RXD buffer reached                                             */
+  __I  uint32_t  RESERVED4;
+  __IO uint32_t  EVENTS_END;                        /*!< End of RXD buffer and TXD buffer reached                              */
+  __I  uint32_t  RESERVED5;
+  __IO uint32_t  EVENTS_ENDTX;                      /*!< End of TXD buffer reached                                             */
+  __I  uint32_t  RESERVED6[10];
+  __IO uint32_t  EVENTS_STARTED;                    /*!< Transaction started                                                   */
+  __I  uint32_t  RESERVED7[44];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED8[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED9[61];
+  __IO uint32_t  STALLSTAT;                         /*!< Stall status for EasyDMA RAM accesses. The fields in this register
+                                                         is set to STALL by hardware whenever a stall occurres and can
+                                                          be cleared (set to NOSTALL) by the CPU.                              */
+  __I  uint32_t  RESERVED10[63];
+  __IO uint32_t  ENABLE;                            /*!< Enable SPIM                                                           */
+  __I  uint32_t  RESERVED11;
+  SPIM_PSEL_Type PSEL;                              /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED12[3];
+  __IO uint32_t  FREQUENCY;                         /*!< SPI frequency. Accuracy depends on the HFCLK source selected.         */
+  __I  uint32_t  RESERVED13[3];
+  SPIM_RXD_Type RXD;                                /*!< RXD EasyDMA channel                                                   */
+  SPIM_TXD_Type TXD;                                /*!< TXD EasyDMA channel                                                   */
+  __IO uint32_t  CONFIG;                            /*!< Configuration register                                                */
+  __I  uint32_t  RESERVED14[2];
+  SPIM_IFTIMING_Type IFTIMING;                      /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED15[22];
+  __IO uint32_t  ORC;                               /*!< Byte transmitted after TXD.MAXCNT bytes have been transmitted
+                                                         in the case when RXD.MAXCNT is greater than TXD.MAXCNT                */
+} NRF_SPIM_Type;
+
+
+/* ================================================================================ */
+/* ================                      SPIS                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief SPI Slave 0 (SPIS)
+  */
+
+typedef struct {                                    /*!< SPIS Structure                                                        */
+  __I  uint32_t  RESERVED0[9];
+  __O  uint32_t  TASKS_ACQUIRE;                     /*!< Acquire SPI semaphore                                                 */
+  __O  uint32_t  TASKS_RELEASE;                     /*!< Release SPI semaphore, enabling the SPI slave to acquire it           */
+  __I  uint32_t  RESERVED1[54];
+  __IO uint32_t  EVENTS_END;                        /*!< Granted transaction completed                                         */
+  __I  uint32_t  RESERVED2[2];
+  __IO uint32_t  EVENTS_ENDRX;                      /*!< End of RXD buffer reached                                             */
+  __I  uint32_t  RESERVED3[5];
+  __IO uint32_t  EVENTS_ACQUIRED;                   /*!< Semaphore acquired                                                    */
+  __I  uint32_t  RESERVED4[53];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED5[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED6[61];
+  __I  uint32_t  SEMSTAT;                           /*!< Semaphore status register                                             */
+  __I  uint32_t  RESERVED7[15];
+  __IO uint32_t  STATUS;                            /*!< Status from last transaction                                          */
+  __I  uint32_t  RESERVED8[47];
+  __IO uint32_t  ENABLE;                            /*!< Enable SPI slave                                                      */
+  __I  uint32_t  RESERVED9;
+  SPIS_PSEL_Type PSEL;                              /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED10[7];
+  SPIS_RXD_Type RXD;                                /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED11;
+  SPIS_TXD_Type TXD;                                /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED12;
+  __IO uint32_t  CONFIG;                            /*!< Configuration register                                                */
+  __I  uint32_t  RESERVED13;
+  __IO uint32_t  DEF;                               /*!< Default character. Character clocked out in case of an ignored
+                                                         transaction.                                                          */
+  __I  uint32_t  RESERVED14[24];
+  __IO uint32_t  ORC;                               /*!< Over-read character                                                   */
+} NRF_SPIS_Type;
+
+
+/* ================================================================================ */
+/* ================                      TWIM                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM)
+  */
+
+typedef struct {                                    /*!< TWIM Structure                                                        */
+  __O  uint32_t  TASKS_STARTRX;                     /*!< Start TWI receive sequence                                            */
+  __I  uint32_t  RESERVED0;
+  __O  uint32_t  TASKS_STARTTX;                     /*!< Start TWI transmit sequence                                           */
+  __I  uint32_t  RESERVED1[2];
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop TWI transaction. Must be issued while the TWI master is
+                                                         not suspended.                                                        */
+  __I  uint32_t  RESERVED2;
+  __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend TWI transaction                                               */
+  __O  uint32_t  TASKS_RESUME;                      /*!< Resume TWI transaction                                                */
+  __I  uint32_t  RESERVED3[56];
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< TWI stopped                                                           */
+  __I  uint32_t  RESERVED4[7];
+  __IO uint32_t  EVENTS_ERROR;                      /*!< TWI error                                                             */
+  __I  uint32_t  RESERVED5[8];
+  __IO uint32_t  EVENTS_SUSPENDED;                  /*!< Last byte has been sent out after the SUSPEND task has been
+                                                         issued, TWI traffic is now suspended.                                 */
+  __IO uint32_t  EVENTS_RXSTARTED;                  /*!< Receive sequence started                                              */
+  __IO uint32_t  EVENTS_TXSTARTED;                  /*!< Transmit sequence started                                             */
+  __I  uint32_t  RESERVED6[2];
+  __IO uint32_t  EVENTS_LASTRX;                     /*!< Byte boundary, starting to receive the last byte                      */
+  __IO uint32_t  EVENTS_LASTTX;                     /*!< Byte boundary, starting to transmit the last byte                     */
+  __I  uint32_t  RESERVED7[39];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED8[63];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED9[110];
+  __IO uint32_t  ERRORSRC;                          /*!< Error source                                                          */
+  __I  uint32_t  RESERVED10[14];
+  __IO uint32_t  ENABLE;                            /*!< Enable TWIM                                                           */
+  __I  uint32_t  RESERVED11;
+  TWIM_PSEL_Type PSEL;                              /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED12[5];
+  __IO uint32_t  FREQUENCY;                         /*!< TWI frequency. Accuracy depends on the HFCLK source selected.         */
+  __I  uint32_t  RESERVED13[3];
+  TWIM_RXD_Type RXD;                                /*!< RXD EasyDMA channel                                                   */
+  TWIM_TXD_Type TXD;                                /*!< TXD EasyDMA channel                                                   */
+  __I  uint32_t  RESERVED14[13];
+  __IO uint32_t  ADDRESS;                           /*!< Address used in the TWI transfer                                      */
+} NRF_TWIM_Type;
+
+
+/* ================================================================================ */
+/* ================                      TWIS                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS)
+  */
+
+typedef struct {                                    /*!< TWIS Structure                                                        */
+  __I  uint32_t  RESERVED0[5];
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop TWI transaction                                                  */
+  __I  uint32_t  RESERVED1;
+  __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend TWI transaction                                               */
+  __O  uint32_t  TASKS_RESUME;                      /*!< Resume TWI transaction                                                */
+  __I  uint32_t  RESERVED2[3];
+  __O  uint32_t  TASKS_PREPARERX;                   /*!< Prepare the TWI slave to respond to a write command                   */
+  __O  uint32_t  TASKS_PREPARETX;                   /*!< Prepare the TWI slave to respond to a read command                    */
+  __I  uint32_t  RESERVED3[51];
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< TWI stopped                                                           */
+  __I  uint32_t  RESERVED4[7];
+  __IO uint32_t  EVENTS_ERROR;                      /*!< TWI error                                                             */
+  __I  uint32_t  RESERVED5[9];
+  __IO uint32_t  EVENTS_RXSTARTED;                  /*!< Receive sequence started                                              */
+  __IO uint32_t  EVENTS_TXSTARTED;                  /*!< Transmit sequence started                                             */
+  __I  uint32_t  RESERVED6[4];
+  __IO uint32_t  EVENTS_WRITE;                      /*!< Write command received                                                */
+  __IO uint32_t  EVENTS_READ;                       /*!< Read command received                                                 */
+  __I  uint32_t  RESERVED7[37];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED8[63];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED9[113];
+  __IO uint32_t  ERRORSRC;                          /*!< Error source                                                          */
+  __I  uint32_t  MATCH;                             /*!< Status register indicating which address had a match                  */
+  __I  uint32_t  RESERVED10[10];
+  __IO uint32_t  ENABLE;                            /*!< Enable TWIS                                                           */
+  __I  uint32_t  RESERVED11;
+  TWIS_PSEL_Type PSEL;                              /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED12[9];
+  TWIS_RXD_Type RXD;                                /*!< RXD EasyDMA channel                                                   */
+  __I  uint32_t  RESERVED13;
+  TWIS_TXD_Type TXD;                                /*!< TXD EasyDMA channel                                                   */
+  __I  uint32_t  RESERVED14[14];
+  __IO uint32_t  ADDRESS[2];                        /*!< Description collection[0]: TWI slave address 0                        */
+  __I  uint32_t  RESERVED15;
+  __IO uint32_t  CONFIG;                            /*!< Configuration register for the address match mechanism                */
+  __I  uint32_t  RESERVED16[10];
+  __IO uint32_t  ORC;                               /*!< Over-read character. Character sent out in case of an over-read
+                                                         of the transmit buffer.                                               */
+} NRF_TWIS_Type;
+
+
+/* ================================================================================ */
+/* ================                       SPI                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Serial Peripheral Interface 0 (SPI)
+  */
+
+typedef struct {                                    /*!< SPI Structure                                                         */
+  __I  uint32_t  RESERVED0[66];
+  __IO uint32_t  EVENTS_READY;                      /*!< TXD byte sent and RXD byte received                                   */
+  __I  uint32_t  RESERVED1[126];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED2[125];
+  __IO uint32_t  ENABLE;                            /*!< Enable SPI                                                            */
+  __I  uint32_t  RESERVED3;
+  SPI_PSEL_Type PSEL;                               /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED4;
+  __I  uint32_t  RXD;                               /*!< RXD register                                                          */
+  __IO uint32_t  TXD;                               /*!< TXD register                                                          */
+  __I  uint32_t  RESERVED5;
+  __IO uint32_t  FREQUENCY;                         /*!< SPI frequency. Accuracy depends on the HFCLK source selected.         */
+  __I  uint32_t  RESERVED6[11];
+  __IO uint32_t  CONFIG;                            /*!< Configuration register                                                */
+} NRF_SPI_Type;
+
+
+/* ================================================================================ */
+/* ================                       TWI                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief I2C compatible Two-Wire Interface 0 (TWI)
+  */
+
+typedef struct {                                    /*!< TWI Structure                                                         */
+  __O  uint32_t  TASKS_STARTRX;                     /*!< Start TWI receive sequence                                            */
+  __I  uint32_t  RESERVED0;
+  __O  uint32_t  TASKS_STARTTX;                     /*!< Start TWI transmit sequence                                           */
+  __I  uint32_t  RESERVED1[2];
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop TWI transaction                                                  */
+  __I  uint32_t  RESERVED2;
+  __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend TWI transaction                                               */
+  __O  uint32_t  TASKS_RESUME;                      /*!< Resume TWI transaction                                                */
+  __I  uint32_t  RESERVED3[56];
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< TWI stopped                                                           */
+  __IO uint32_t  EVENTS_RXDREADY;                   /*!< TWI RXD byte received                                                 */
+  __I  uint32_t  RESERVED4[4];
+  __IO uint32_t  EVENTS_TXDSENT;                    /*!< TWI TXD byte sent                                                     */
+  __I  uint32_t  RESERVED5;
+  __IO uint32_t  EVENTS_ERROR;                      /*!< TWI error                                                             */
+  __I  uint32_t  RESERVED6[4];
+  __IO uint32_t  EVENTS_BB;                         /*!< TWI byte boundary, generated before each byte that is sent or
+                                                         received                                                              */
+  __I  uint32_t  RESERVED7[3];
+  __IO uint32_t  EVENTS_SUSPENDED;                  /*!< TWI entered the suspended state                                       */
+  __I  uint32_t  RESERVED8[45];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED9[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED10[110];
+  __IO uint32_t  ERRORSRC;                          /*!< Error source                                                          */
+  __I  uint32_t  RESERVED11[14];
+  __IO uint32_t  ENABLE;                            /*!< Enable TWI                                                            */
+  __I  uint32_t  RESERVED12;
+  TWI_PSEL_Type PSEL;                               /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED13[2];
+  __I  uint32_t  RXD;                               /*!< RXD register                                                          */
+  __IO uint32_t  TXD;                               /*!< TXD register                                                          */
+  __I  uint32_t  RESERVED14;
+  __IO uint32_t  FREQUENCY;                         /*!< TWI frequency. Accuracy depends on the HFCLK source selected.         */
+  __I  uint32_t  RESERVED15[24];
+  __IO uint32_t  ADDRESS;                           /*!< Address used in the TWI transfer                                      */
+} NRF_TWI_Type;
+
+
+/* ================================================================================ */
+/* ================                      NFCT                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief NFC-A compatible radio (NFCT)
+  */
+
+typedef struct {                                    /*!< NFCT Structure                                                        */
+  __O  uint32_t  TASKS_ACTIVATE;                    /*!< Activate NFCT peripheral for incoming and outgoing frames, change
+                                                         state to activated                                                    */
+  __O  uint32_t  TASKS_DISABLE;                     /*!< Disable NFCT peripheral                                               */
+  __O  uint32_t  TASKS_SENSE;                       /*!< Enable NFC sense field mode, change state to sense mode               */
+  __O  uint32_t  TASKS_STARTTX;                     /*!< Start transmission of an outgoing frame, change state to transmit     */
+  __I  uint32_t  RESERVED0[3];
+  __O  uint32_t  TASKS_ENABLERXDATA;                /*!< Initializes the EasyDMA for receive.                                  */
+  __I  uint32_t  RESERVED1;
+  __O  uint32_t  TASKS_GOIDLE;                      /*!< Force state machine to IDLE state                                     */
+  __O  uint32_t  TASKS_GOSLEEP;                     /*!< Force state machine to SLEEP_A state                                  */
+  __I  uint32_t  RESERVED2[53];
+  __IO uint32_t  EVENTS_READY;                      /*!< The NFCT peripheral is ready to receive and send frames               */
+  __IO uint32_t  EVENTS_FIELDDETECTED;              /*!< Remote NFC field detected                                             */
+  __IO uint32_t  EVENTS_FIELDLOST;                  /*!< Remote NFC field lost                                                 */
+  __IO uint32_t  EVENTS_TXFRAMESTART;               /*!< Marks the start of the first symbol of a transmitted frame            */
+  __IO uint32_t  EVENTS_TXFRAMEEND;                 /*!< Marks the end of the last transmitted on-air symbol of a frame        */
+  __IO uint32_t  EVENTS_RXFRAMESTART;               /*!< Marks the end of the first symbol of a received frame                 */
+  __IO uint32_t  EVENTS_RXFRAMEEND;                 /*!< Received data has been checked (CRC, parity) and transferred
+                                                         to RAM, and EasyDMA has ended accessing the RX buffer                 */
+  __IO uint32_t  EVENTS_ERROR;                      /*!< NFC error reported. The ERRORSTATUS register contains details
+                                                         on the source of the error.                                           */
+  __I  uint32_t  RESERVED3[2];
+  __IO uint32_t  EVENTS_RXERROR;                    /*!< NFC RX frame error reported. The FRAMESTATUS.RX register contains
+                                                         details on the source of the error.                                   */
+  __IO uint32_t  EVENTS_ENDRX;                      /*!< RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full.      */
+  __IO uint32_t  EVENTS_ENDTX;                      /*!< Transmission of data in RAM has ended, and EasyDMA has ended
+                                                         accessing the TX buffer                                               */
+  __I  uint32_t  RESERVED4;
+  __IO uint32_t  EVENTS_AUTOCOLRESSTARTED;          /*!< Auto collision resolution process has started                         */
+  __I  uint32_t  RESERVED5[3];
+  __IO uint32_t  EVENTS_COLLISION;                  /*!< NFC auto collision resolution error reported.                         */
+  __IO uint32_t  EVENTS_SELECTED;                   /*!< NFC auto collision resolution successfully completed                  */
+  __IO uint32_t  EVENTS_STARTED;                    /*!< EasyDMA is ready to receive or send frames.                           */
+  __I  uint32_t  RESERVED6[43];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED7[63];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED8[62];
+  __IO uint32_t  ERRORSTATUS;                       /*!< NFC Error Status register                                             */
+  __I  uint32_t  RESERVED9;
+  NFCT_FRAMESTATUS_Type FRAMESTATUS;                /*!< Unspecified                                                           */
+  __I  uint32_t  NFCTAGSTATE;                       /*!< NfcTag state register                                                 */
+  __I  uint32_t  RESERVED10[10];
+  __I  uint32_t  FIELDPRESENT;                      /*!< Indicates the presence or not of a valid field                        */
+  __I  uint32_t  RESERVED11[49];
+  __IO uint32_t  FRAMEDELAYMIN;                     /*!< Minimum frame delay                                                   */
+  __IO uint32_t  FRAMEDELAYMAX;                     /*!< Maximum frame delay                                                   */
+  __IO uint32_t  FRAMEDELAYMODE;                    /*!< Configuration register for the Frame Delay Timer                      */
+  __IO uint32_t  PACKETPTR;                         /*!< Packet pointer for TXD and RXD data storage in Data RAM               */
+  __IO uint32_t  MAXLEN;                            /*!< Size of the RAM buffer allocated to TXD and RXD data storage
+                                                         each                                                                  */
+  NFCT_TXD_Type TXD;                                /*!< Unspecified                                                           */
+  NFCT_RXD_Type RXD;                                /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED12[26];
+  __IO uint32_t  NFCID1_LAST;                       /*!< Last NFCID1 part (4, 7 or 10 bytes ID)                                */
+  __IO uint32_t  NFCID1_2ND_LAST;                   /*!< Second last NFCID1 part (7 or 10 bytes ID)                            */
+  __IO uint32_t  NFCID1_3RD_LAST;                   /*!< Third last NFCID1 part (10 bytes ID)                                  */
+  __IO uint32_t  AUTOCOLRESCONFIG;                  /*!< Controls the auto collision resolution function. This setting
+                                                         must be done before the NFCT peripheral is enabled.                   */
+  __IO uint32_t  SENSRES;                           /*!< NFC-A SENS_RES auto-response settings                                 */
+  __IO uint32_t  SELRES;                            /*!< NFC-A SEL_RES auto-response settings                                  */
+} NRF_NFCT_Type;
+
+
+/* ================================================================================ */
+/* ================                     GPIOTE                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief GPIO Tasks and Events (GPIOTE)
+  */
+
+typedef struct {                                    /*!< GPIOTE Structure                                                      */
+  __O  uint32_t  TASKS_OUT[8];                      /*!< Description collection[0]: Task for writing to pin specified
+                                                         in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY. */
+  __I  uint32_t  RESERVED0[4];
+  __O  uint32_t  TASKS_SET[8];                      /*!< Description collection[0]: Task for writing to pin specified
+                                                         in CONFIG[0].PSEL. Action on pin is to set it high.                   */
+  __I  uint32_t  RESERVED1[4];
+  __O  uint32_t  TASKS_CLR[8];                      /*!< Description collection[0]: Task for writing to pin specified
+                                                         in CONFIG[0].PSEL. Action on pin is to set it low.                    */
+  __I  uint32_t  RESERVED2[32];
+  __IO uint32_t  EVENTS_IN[8];                      /*!< Description collection[0]: Event generated from pin specified
+                                                         in CONFIG[0].PSEL                                                     */
+  __I  uint32_t  RESERVED3[23];
+  __IO uint32_t  EVENTS_PORT;                       /*!< Event generated from multiple input GPIO pins with SENSE mechanism
+                                                         enabled                                                               */
+  __I  uint32_t  RESERVED4[97];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED5[129];
+  __IO uint32_t  CONFIG[8];                         /*!< Description collection[0]: Configuration for OUT[n], SET[n]
+                                                         and CLR[n] tasks and IN[n] event                                      */
+} NRF_GPIOTE_Type;
+
+
+/* ================================================================================ */
+/* ================                      SAADC                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Analog to Digital Converter (SAADC)
+  */
+
+typedef struct {                                    /*!< SAADC Structure                                                       */
+  __O  uint32_t  TASKS_START;                       /*!< Start the ADC and prepare the result buffer in RAM                    */
+  __O  uint32_t  TASKS_SAMPLE;                      /*!< Take one ADC sample, if scan is enabled all channels are sampled      */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop the ADC and terminate any on-going conversion                    */
+  __O  uint32_t  TASKS_CALIBRATEOFFSET;             /*!< Starts offset auto-calibration                                        */
+  __I  uint32_t  RESERVED0[60];
+  __IO uint32_t  EVENTS_STARTED;                    /*!< The ADC has started                                                   */
+  __IO uint32_t  EVENTS_END;                        /*!< The ADC has filled up the Result buffer                               */
+  __IO uint32_t  EVENTS_DONE;                       /*!< A conversion task has been completed. Depending on the mode,
+                                                         multiple conversions might be needed for a result to be transferred
+                                                          to RAM.                                                              */
+  __IO uint32_t  EVENTS_RESULTDONE;                 /*!< A result is ready to get transferred to RAM.                          */
+  __IO uint32_t  EVENTS_CALIBRATEDONE;              /*!< Calibration is complete                                               */
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< The ADC has stopped                                                   */
+  SAADC_EVENTS_CH_Type EVENTS_CH[8];                /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED1[106];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED2[61];
+  __I  uint32_t  STATUS;                            /*!< Status                                                                */
+  __I  uint32_t  RESERVED3[63];
+  __IO uint32_t  ENABLE;                            /*!< Enable or disable ADC                                                 */
+  __I  uint32_t  RESERVED4[3];
+  SAADC_CH_Type CH[8];                              /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED5[24];
+  __IO uint32_t  RESOLUTION;                        /*!< Resolution configuration                                              */
+  __IO uint32_t  OVERSAMPLE;                        /*!< Oversampling configuration. OVERSAMPLE should not be combined
+                                                         with SCAN. The RESOLUTION is applied before averaging, thus
+                                                          for high OVERSAMPLE a higher RESOLUTION should be used.              */
+  __IO uint32_t  SAMPLERATE;                        /*!< Controls normal or continuous sample rate                             */
+  __I  uint32_t  RESERVED6[12];
+  SAADC_RESULT_Type RESULT;                         /*!< RESULT EasyDMA channel                                                */
+} NRF_SAADC_Type;
+
+
+/* ================================================================================ */
+/* ================                      TIMER                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Timer/Counter 0 (TIMER)
+  */
+
+typedef struct {                                    /*!< TIMER Structure                                                       */
+  __O  uint32_t  TASKS_START;                       /*!< Start Timer                                                           */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop Timer                                                            */
+  __O  uint32_t  TASKS_COUNT;                       /*!< Increment Timer (Counter mode only)                                   */
+  __O  uint32_t  TASKS_CLEAR;                       /*!< Clear time                                                            */
+  __O  uint32_t  TASKS_SHUTDOWN;                    /*!< Deprecated register - Shut down timer                                 */
+  __I  uint32_t  RESERVED0[11];
+  __O  uint32_t  TASKS_CAPTURE[6];                  /*!< Description collection[0]: Capture Timer value to CC[0] register      */
+  __I  uint32_t  RESERVED1[58];
+  __IO uint32_t  EVENTS_COMPARE[6];                 /*!< Description collection[0]: Compare event on CC[0] match               */
+  __I  uint32_t  RESERVED2[42];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED3[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED4[61];
+  __I  uint32_t  STATUS;                            /*!< Timer status                                                          */
+  __I  uint32_t  RESERVED5[64];
+  __IO uint32_t  MODE;                              /*!< Timer mode selection                                                  */
+  __IO uint32_t  BITMODE;                           /*!< Configure the number of bits used by the TIMER                        */
+  __I  uint32_t  RESERVED6;
+  __IO uint32_t  PRESCALER;                         /*!< Timer prescaler register                                              */
+  __I  uint32_t  RESERVED7[11];
+  __IO uint32_t  CC[6];                             /*!< Description collection[0]: Capture/Compare register 0                 */
+} NRF_TIMER_Type;
+
+
+/* ================================================================================ */
+/* ================                       RTC                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Real time counter 0 (RTC)
+  */
+
+typedef struct {                                    /*!< RTC Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Start RTC COUNTER                                                     */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop RTC COUNTER                                                      */
+  __O  uint32_t  TASKS_CLEAR;                       /*!< Clear RTC COUNTER                                                     */
+  __O  uint32_t  TASKS_TRIGOVRFLW;                  /*!< Set COUNTER to 0xFFFFF0                                               */
+  __I  uint32_t  RESERVED0[60];
+  __IO uint32_t  EVENTS_TICK;                       /*!< Event on COUNTER increment                                            */
+  __IO uint32_t  EVENTS_OVRFLW;                     /*!< Event on COUNTER overflow                                             */
+  __I  uint32_t  RESERVED1[14];
+  __IO uint32_t  EVENTS_COMPARE[4];                 /*!< Description collection[0]: Compare event on CC[0] match               */
+  __I  uint32_t  RESERVED2[109];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[13];
+  __IO uint32_t  EVTEN;                             /*!< Enable or disable event routing                                       */
+  __IO uint32_t  EVTENSET;                          /*!< Enable event routing                                                  */
+  __IO uint32_t  EVTENCLR;                          /*!< Disable event routing                                                 */
+  __I  uint32_t  RESERVED4[110];
+  __I  uint32_t  COUNTER;                           /*!< Current COUNTER value                                                 */
+  __IO uint32_t  PRESCALER;                         /*!< 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must
+                                                         be written when RTC is stopped                                        */
+  __I  uint32_t  RESERVED5[13];
+  __IO uint32_t  CC[4];                             /*!< Description collection[0]: Compare register 0                         */
+} NRF_RTC_Type;
+
+
+/* ================================================================================ */
+/* ================                      TEMP                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Temperature Sensor (TEMP)
+  */
+
+typedef struct {                                    /*!< TEMP Structure                                                        */
+  __O  uint32_t  TASKS_START;                       /*!< Start temperature measurement                                         */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop temperature measurement                                          */
+  __I  uint32_t  RESERVED0[62];
+  __IO uint32_t  EVENTS_DATARDY;                    /*!< Temperature measurement complete, data ready                          */
+  __I  uint32_t  RESERVED1[128];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED2[127];
+  __I  int32_t   TEMP;                              /*!< Temperature in degC (0.25deg steps)                                   */
+  __I  uint32_t  RESERVED3[5];
+  __IO uint32_t  A0;                                /*!< Slope of 1st piece wise linear function                               */
+  __IO uint32_t  A1;                                /*!< Slope of 2nd piece wise linear function                               */
+  __IO uint32_t  A2;                                /*!< Slope of 3rd piece wise linear function                               */
+  __IO uint32_t  A3;                                /*!< Slope of 4th piece wise linear function                               */
+  __IO uint32_t  A4;                                /*!< Slope of 5th piece wise linear function                               */
+  __IO uint32_t  A5;                                /*!< Slope of 6th piece wise linear function                               */
+  __I  uint32_t  RESERVED4[2];
+  __IO uint32_t  B0;                                /*!< y-intercept of 1st piece wise linear function                         */
+  __IO uint32_t  B1;                                /*!< y-intercept of 2nd piece wise linear function                         */
+  __IO uint32_t  B2;                                /*!< y-intercept of 3rd piece wise linear function                         */
+  __IO uint32_t  B3;                                /*!< y-intercept of 4th piece wise linear function                         */
+  __IO uint32_t  B4;                                /*!< y-intercept of 5th piece wise linear function                         */
+  __IO uint32_t  B5;                                /*!< y-intercept of 6th piece wise linear function                         */
+  __I  uint32_t  RESERVED5[2];
+  __IO uint32_t  T0;                                /*!< End point of 1st piece wise linear function                           */
+  __IO uint32_t  T1;                                /*!< End point of 2nd piece wise linear function                           */
+  __IO uint32_t  T2;                                /*!< End point of 3rd piece wise linear function                           */
+  __IO uint32_t  T3;                                /*!< End point of 4th piece wise linear function                           */
+  __IO uint32_t  T4;                                /*!< End point of 5th piece wise linear function                           */
+} NRF_TEMP_Type;
+
+
+/* ================================================================================ */
+/* ================                       RNG                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Random Number Generator (RNG)
+  */
+
+typedef struct {                                    /*!< RNG Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Task starting the random number generator                             */
+  __O  uint32_t  TASKS_STOP;                        /*!< Task stopping the random number generator                             */
+  __I  uint32_t  RESERVED0[62];
+  __IO uint32_t  EVENTS_VALRDY;                     /*!< Event being generated for every new random number written to
+                                                         the VALUE register                                                    */
+  __I  uint32_t  RESERVED1[63];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED2[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[126];
+  __IO uint32_t  CONFIG;                            /*!< Configuration register                                                */
+  __I  uint32_t  VALUE;                             /*!< Output random number                                                  */
+} NRF_RNG_Type;
+
+
+/* ================================================================================ */
+/* ================                       ECB                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief AES ECB Mode Encryption (ECB)
+  */
+
+typedef struct {                                    /*!< ECB Structure                                                         */
+  __O  uint32_t  TASKS_STARTECB;                    /*!< Start ECB block encrypt                                               */
+  __O  uint32_t  TASKS_STOPECB;                     /*!< Abort a possible executing ECB operation                              */
+  __I  uint32_t  RESERVED0[62];
+  __IO uint32_t  EVENTS_ENDECB;                     /*!< ECB block encrypt complete                                            */
+  __IO uint32_t  EVENTS_ERRORECB;                   /*!< ECB block encrypt aborted because of a STOPECB task or due to
+                                                         an error                                                              */
+  __I  uint32_t  RESERVED1[127];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED2[126];
+  __IO uint32_t  ECBDATAPTR;                        /*!< ECB block encrypt memory pointers                                     */
+} NRF_ECB_Type;
+
+
+/* ================================================================================ */
+/* ================                       CCM                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief AES CCM Mode Encryption (CCM)
+  */
+
+typedef struct {                                    /*!< CCM Structure                                                         */
+  __O  uint32_t  TASKS_KSGEN;                       /*!< Start generation of key-stream. This operation will stop by
+                                                         itself when completed.                                                */
+  __O  uint32_t  TASKS_CRYPT;                       /*!< Start encryption/decryption. This operation will stop by itself
+                                                         when completed.                                                       */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop encryption/decryption                                            */
+  __O  uint32_t  TASKS_RATEOVERRIDE;                /*!< Override DATARATE setting in MODE register with the contents
+                                                         of the RATEOVERRIDE register for any ongoing encryption/decryption    */
+  __I  uint32_t  RESERVED0[60];
+  __IO uint32_t  EVENTS_ENDKSGEN;                   /*!< Key-stream generation complete                                        */
+  __IO uint32_t  EVENTS_ENDCRYPT;                   /*!< Encrypt/decrypt complete                                              */
+  __IO uint32_t  EVENTS_ERROR;                      /*!< Deprecated register - CCM error event                                 */
+  __I  uint32_t  RESERVED1[61];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED2[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[61];
+  __I  uint32_t  MICSTATUS;                         /*!< MIC check result                                                      */
+  __I  uint32_t  RESERVED4[63];
+  __IO uint32_t  ENABLE;                            /*!< Enable                                                                */
+  __IO uint32_t  MODE;                              /*!< Operation mode                                                        */
+  __IO uint32_t  CNFPTR;                            /*!< Pointer to data structure holding AES key and NONCE vector            */
+  __IO uint32_t  INPTR;                             /*!< Input pointer                                                         */
+  __IO uint32_t  OUTPTR;                            /*!< Output pointer                                                        */
+  __IO uint32_t  SCRATCHPTR;                        /*!< Pointer to data area used for temporary storage                       */
+  __IO uint32_t  MAXPACKETSIZE;                     /*!< Length of key-stream generated when MODE.LENGTH = Extended.           */
+  __IO uint32_t  RATEOVERRIDE;                      /*!< Data rate override setting.                                           */
+} NRF_CCM_Type;
+
+
+/* ================================================================================ */
+/* ================                       AAR                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Accelerated Address Resolver (AAR)
+  */
+
+typedef struct {                                    /*!< AAR Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Start resolving addresses based on IRKs specified in the IRK
+                                                         data structure                                                        */
+  __I  uint32_t  RESERVED0;
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop resolving addresses                                              */
+  __I  uint32_t  RESERVED1[61];
+  __IO uint32_t  EVENTS_END;                        /*!< Address resolution procedure complete                                 */
+  __IO uint32_t  EVENTS_RESOLVED;                   /*!< Address resolved                                                      */
+  __IO uint32_t  EVENTS_NOTRESOLVED;                /*!< Address not resolved                                                  */
+  __I  uint32_t  RESERVED2[126];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[61];
+  __I  uint32_t  STATUS;                            /*!< Resolution status                                                     */
+  __I  uint32_t  RESERVED4[63];
+  __IO uint32_t  ENABLE;                            /*!< Enable AAR                                                            */
+  __IO uint32_t  NIRK;                              /*!< Number of IRKs                                                        */
+  __IO uint32_t  IRKPTR;                            /*!< Pointer to IRK data structure                                         */
+  __I  uint32_t  RESERVED5;
+  __IO uint32_t  ADDRPTR;                           /*!< Pointer to the resolvable address                                     */
+  __IO uint32_t  SCRATCHPTR;                        /*!< Pointer to data area used for temporary storage                       */
+} NRF_AAR_Type;
+
+
+/* ================================================================================ */
+/* ================                       WDT                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Watchdog Timer (WDT)
+  */
+
+typedef struct {                                    /*!< WDT Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Start the watchdog                                                    */
+  __I  uint32_t  RESERVED0[63];
+  __IO uint32_t  EVENTS_TIMEOUT;                    /*!< Watchdog timeout                                                      */
+  __I  uint32_t  RESERVED1[128];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED2[61];
+  __I  uint32_t  RUNSTATUS;                         /*!< Run status                                                            */
+  __I  uint32_t  REQSTATUS;                         /*!< Request status                                                        */
+  __I  uint32_t  RESERVED3[63];
+  __IO uint32_t  CRV;                               /*!< Counter reload value                                                  */
+  __IO uint32_t  RREN;                              /*!< Enable register for reload request registers                          */
+  __IO uint32_t  CONFIG;                            /*!< Configuration register                                                */
+  __I  uint32_t  RESERVED4[60];
+  __O  uint32_t  RR[8];                             /*!< Description collection[0]: Reload request 0                           */
+} NRF_WDT_Type;
+
+
+/* ================================================================================ */
+/* ================                      QDEC                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Quadrature Decoder (QDEC)
+  */
+
+typedef struct {                                    /*!< QDEC Structure                                                        */
+  __O  uint32_t  TASKS_START;                       /*!< Task starting the quadrature decoder                                  */
+  __O  uint32_t  TASKS_STOP;                        /*!< Task stopping the quadrature decoder                                  */
+  __O  uint32_t  TASKS_READCLRACC;                  /*!< Read and clear ACC and ACCDBL                                         */
+  __O  uint32_t  TASKS_RDCLRACC;                    /*!< Read and clear ACC                                                    */
+  __O  uint32_t  TASKS_RDCLRDBL;                    /*!< Read and clear ACCDBL                                                 */
+  __I  uint32_t  RESERVED0[59];
+  __IO uint32_t  EVENTS_SAMPLERDY;                  /*!< Event being generated for every new sample value written to
+                                                         the SAMPLE register                                                   */
+  __IO uint32_t  EVENTS_REPORTRDY;                  /*!< Non-null report ready                                                 */
+  __IO uint32_t  EVENTS_ACCOF;                      /*!< ACC or ACCDBL register overflow                                       */
+  __IO uint32_t  EVENTS_DBLRDY;                     /*!< Double displacement(s) detected                                       */
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< QDEC has been stopped                                                 */
+  __I  uint32_t  RESERVED1[59];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED2[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[125];
+  __IO uint32_t  ENABLE;                            /*!< Enable the quadrature decoder                                         */
+  __IO uint32_t  LEDPOL;                            /*!< LED output pin polarity                                               */
+  __IO uint32_t  SAMPLEPER;                         /*!< Sample period                                                         */
+  __I  int32_t   SAMPLE;                            /*!< Motion sample value                                                   */
+  __IO uint32_t  REPORTPER;                         /*!< Number of samples to be taken before REPORTRDY and DBLRDY events
+                                                         can be generated                                                      */
+  __I  int32_t   ACC;                               /*!< Register accumulating the valid transitions                           */
+  __I  int32_t   ACCREAD;                           /*!< Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC
+                                                         task                                                                  */
+  QDEC_PSEL_Type PSEL;                              /*!< Unspecified                                                           */
+  __IO uint32_t  DBFEN;                             /*!< Enable input debounce filters                                         */
+  __I  uint32_t  RESERVED4[5];
+  __IO uint32_t  LEDPRE;                            /*!< Time period the LED is switched ON prior to sampling                  */
+  __I  uint32_t  ACCDBL;                            /*!< Register accumulating the number of detected double transitions       */
+  __I  uint32_t  ACCDBLREAD;                        /*!< Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL
+                                                         task                                                                  */
+} NRF_QDEC_Type;
+
+
+/* ================================================================================ */
+/* ================                      COMP                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Comparator (COMP)
+  */
+
+typedef struct {                                    /*!< COMP Structure                                                        */
+  __O  uint32_t  TASKS_START;                       /*!< Start comparator                                                      */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop comparator                                                       */
+  __O  uint32_t  TASKS_SAMPLE;                      /*!< Sample comparator value                                               */
+  __I  uint32_t  RESERVED0[61];
+  __IO uint32_t  EVENTS_READY;                      /*!< COMP is ready and output is valid                                     */
+  __IO uint32_t  EVENTS_DOWN;                       /*!< Downward crossing                                                     */
+  __IO uint32_t  EVENTS_UP;                         /*!< Upward crossing                                                       */
+  __IO uint32_t  EVENTS_CROSS;                      /*!< Downward or upward crossing                                           */
+  __I  uint32_t  RESERVED1[60];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED2[63];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[61];
+  __I  uint32_t  RESULT;                            /*!< Compare result                                                        */
+  __I  uint32_t  RESERVED4[63];
+  __IO uint32_t  ENABLE;                            /*!< COMP enable                                                           */
+  __IO uint32_t  PSEL;                              /*!< Pin select                                                            */
+  __IO uint32_t  REFSEL;                            /*!< Reference source select                                               */
+  __IO uint32_t  EXTREFSEL;                         /*!< External reference select                                             */
+  __I  uint32_t  RESERVED5[8];
+  __IO uint32_t  TH;                                /*!< Threshold configuration for hysteresis unit                           */
+  __IO uint32_t  MODE;                              /*!< Mode configuration                                                    */
+  __IO uint32_t  HYST;                              /*!< Comparator hysteresis enable                                          */
+  __IO uint32_t  ISOURCE;                           /*!< Current source select on analog input                                 */
+} NRF_COMP_Type;
+
+
+/* ================================================================================ */
+/* ================                     LPCOMP                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Low Power Comparator (LPCOMP)
+  */
+
+typedef struct {                                    /*!< LPCOMP Structure                                                      */
+  __O  uint32_t  TASKS_START;                       /*!< Start comparator                                                      */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop comparator                                                       */
+  __O  uint32_t  TASKS_SAMPLE;                      /*!< Sample comparator value                                               */
+  __I  uint32_t  RESERVED0[61];
+  __IO uint32_t  EVENTS_READY;                      /*!< LPCOMP is ready and output is valid                                   */
+  __IO uint32_t  EVENTS_DOWN;                       /*!< Downward crossing                                                     */
+  __IO uint32_t  EVENTS_UP;                         /*!< Upward crossing                                                       */
+  __IO uint32_t  EVENTS_CROSS;                      /*!< Downward or upward crossing                                           */
+  __I  uint32_t  RESERVED1[60];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED2[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[61];
+  __I  uint32_t  RESULT;                            /*!< Compare result                                                        */
+  __I  uint32_t  RESERVED4[63];
+  __IO uint32_t  ENABLE;                            /*!< Enable LPCOMP                                                         */
+  __IO uint32_t  PSEL;                              /*!< Input pin select                                                      */
+  __IO uint32_t  REFSEL;                            /*!< Reference select                                                      */
+  __IO uint32_t  EXTREFSEL;                         /*!< External reference select                                             */
+  __I  uint32_t  RESERVED5[4];
+  __IO uint32_t  ANADETECT;                         /*!< Analog detect configuration                                           */
+  __I  uint32_t  RESERVED6[5];
+  __IO uint32_t  HYST;                              /*!< Comparator hysteresis enable                                          */
+} NRF_LPCOMP_Type;
+
+
+/* ================================================================================ */
+/* ================                       SWI                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Software interrupt 0 (SWI)
+  */
+
+typedef struct {                                    /*!< SWI Structure                                                         */
+  __I  uint32_t  UNUSED;                            /*!< Unused.                                                               */
+} NRF_SWI_Type;
+
+
+/* ================================================================================ */
+/* ================                       EGU                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Event Generator Unit 0 (EGU)
+  */
+
+typedef struct {                                    /*!< EGU Structure                                                         */
+  __O  uint32_t  TASKS_TRIGGER[16];                 /*!< Description collection[0]: Trigger 0 for triggering the corresponding
+                                                         TRIGGERED[0] event                                                    */
+  __I  uint32_t  RESERVED0[48];
+  __IO uint32_t  EVENTS_TRIGGERED[16];              /*!< Description collection[0]: Event number 0 generated by triggering
+                                                         the corresponding TRIGGER[0] task                                     */
+  __I  uint32_t  RESERVED1[112];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+} NRF_EGU_Type;
+
+
+/* ================================================================================ */
+/* ================                       PWM                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Pulse Width Modulation Unit 0 (PWM)
+  */
+
+typedef struct {                                    /*!< PWM Structure                                                         */
+  __I  uint32_t  RESERVED0;
+  __O  uint32_t  TASKS_STOP;                        /*!< Stops PWM pulse generation on all channels at the end of current
+                                                         PWM period, and stops sequence playback                               */
+  __O  uint32_t  TASKS_SEQSTART[2];                 /*!< Description collection[0]: Loads the first PWM value on all
+                                                         enabled channels from sequence 0, and starts playing that sequence
+                                                          at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes
+                                                          PWM generation to start it was not running.                          */
+  __O  uint32_t  TASKS_NEXTSTEP;                    /*!< Steps by one value in the current sequence on all enabled channels
+                                                         if DECODER.MODE=NextStep. Does not cause PWM generation to start
+                                                          it was not running.                                                  */
+  __I  uint32_t  RESERVED1[60];
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< Response to STOP task, emitted when PWM pulses are no longer
+                                                         generated                                                             */
+  __IO uint32_t  EVENTS_SEQSTARTED[2];              /*!< Description collection[0]: First PWM period started on sequence
+                                                         0                                                                     */
+  __IO uint32_t  EVENTS_SEQEND[2];                  /*!< Description collection[0]: Emitted at end of every sequence
+                                                         0, when last value from RAM has been applied to wave counter          */
+  __IO uint32_t  EVENTS_PWMPERIODEND;               /*!< Emitted at the end of each PWM period                                 */
+  __IO uint32_t  EVENTS_LOOPSDONE;                  /*!< Concatenated sequences have been played the amount of times
+                                                         defined in LOOP.CNT                                                   */
+  __I  uint32_t  RESERVED2[56];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED3[63];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED4[125];
+  __IO uint32_t  ENABLE;                            /*!< PWM module enable register                                            */
+  __IO uint32_t  MODE;                              /*!< Selects operating mode of the wave counter                            */
+  __IO uint32_t  COUNTERTOP;                        /*!< Value up to which the pulse generator counter counts                  */
+  __IO uint32_t  PRESCALER;                         /*!< Configuration for PWM_CLK                                             */
+  __IO uint32_t  DECODER;                           /*!< Configuration of the decoder                                          */
+  __IO uint32_t  LOOP;                              /*!< Amount of playback of a loop                                          */
+  __I  uint32_t  RESERVED5[2];
+  PWM_SEQ_Type SEQ[2];                              /*!< Unspecified                                                           */
+  PWM_PSEL_Type PSEL;                               /*!< Unspecified                                                           */
+} NRF_PWM_Type;
+
+
+/* ================================================================================ */
+/* ================                       PDM                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Pulse Density Modulation (Digital Microphone) Interface (PDM)
+  */
+
+typedef struct {                                    /*!< PDM Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Starts continuous PDM transfer                                        */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stops PDM transfer                                                    */
+  __I  uint32_t  RESERVED0[62];
+  __IO uint32_t  EVENTS_STARTED;                    /*!< PDM transfer has started                                              */
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< PDM transfer has finished                                             */
+  __IO uint32_t  EVENTS_END;                        /*!< The PDM has written the last sample specified by SAMPLE.MAXCNT
+                                                         (or the last sample after a STOP task has been received) to
+                                                          Data RAM                                                             */
+  __I  uint32_t  RESERVED1[125];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED2[125];
+  __IO uint32_t  ENABLE;                            /*!< PDM module enable register                                            */
+  __IO uint32_t  PDMCLKCTRL;                        /*!< PDM clock generator control                                           */
+  __IO uint32_t  MODE;                              /*!< Defines the routing of the connected PDM microphones' signals         */
+  __I  uint32_t  RESERVED3[3];
+  __IO uint32_t  GAINL;                             /*!< Left output gain adjustment                                           */
+  __IO uint32_t  GAINR;                             /*!< Right output gain adjustment                                          */
+  __IO uint32_t  RATIO;                             /*!< Selects the ratio between PDM_CLK and output sample rate. Change
+                                                         PDMCLKCTRL accordingly.                                               */
+  __I  uint32_t  RESERVED4[7];
+  PDM_PSEL_Type PSEL;                               /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED5[6];
+  PDM_SAMPLE_Type SAMPLE;                           /*!< Unspecified                                                           */
+} NRF_PDM_Type;
+
+
+/* ================================================================================ */
+/* ================                      NVMC                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Non Volatile Memory Controller (NVMC)
+  */
+
+typedef struct {                                    /*!< NVMC Structure                                                        */
+  __I  uint32_t  RESERVED0[256];
+  __I  uint32_t  READY;                             /*!< Ready flag                                                            */
+  __I  uint32_t  RESERVED1[64];
+  __IO uint32_t  CONFIG;                            /*!< Configuration register                                                */
+  
+  union {
+    __IO uint32_t  ERASEPCR1;                       /*!< Deprecated register - Register for erasing a page in Code area.
+                                                         Equivalent to ERASEPAGE.                                              */
+    __IO uint32_t  ERASEPAGE;                       /*!< Register for erasing a page in Code area                              */
+  };
+  __IO uint32_t  ERASEALL;                          /*!< Register for erasing all non-volatile user memory                     */
+  __IO uint32_t  ERASEPCR0;                         /*!< Deprecated register - Register for erasing a page in Code area.
+                                                         Equivalent to ERASEPAGE.                                              */
+  __IO uint32_t  ERASEUICR;                         /*!< Register for erasing User Information Configuration Registers         */
+  __I  uint32_t  RESERVED2[10];
+  __IO uint32_t  ICACHECNF;                         /*!< I-Code cache configuration register.                                  */
+  __I  uint32_t  RESERVED3;
+  __IO uint32_t  IHIT;                              /*!< I-Code cache hit counter.                                             */
+  __IO uint32_t  IMISS;                             /*!< I-Code cache miss counter.                                            */
+} NRF_NVMC_Type;
+
+
+/* ================================================================================ */
+/* ================                       ACL                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Access control lists (ACL)
+  */
+
+typedef struct {                                    /*!< ACL Structure                                                         */
+  __I  uint32_t  RESERVED0[449];
+  __IO uint32_t  DISABLEINDEBUG;                    /*!< Disable all ACL protection mechanisms for regions while in debug
+                                                         mode                                                                  */
+  __I  uint32_t  RESERVED1[62];
+  ACL_ACL_Type ACL[8];                              /*!< Unspecified                                                           */
+} NRF_ACL_Type;
+
+
+/* ================================================================================ */
+/* ================                       PPI                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Programmable Peripheral Interconnect (PPI)
+  */
+
+typedef struct {                                    /*!< PPI Structure                                                         */
+  PPI_TASKS_CHG_Type TASKS_CHG[6];                  /*!< Channel group tasks                                                   */
+  __I  uint32_t  RESERVED0[308];
+  __IO uint32_t  CHEN;                              /*!< Channel enable register                                               */
+  __IO uint32_t  CHENSET;                           /*!< Channel enable set register                                           */
+  __IO uint32_t  CHENCLR;                           /*!< Channel enable clear register                                         */
+  __I  uint32_t  RESERVED1;
+  PPI_CH_Type CH[20];                               /*!< PPI Channel                                                           */
+  __I  uint32_t  RESERVED2[148];
+  __IO uint32_t  CHG[6];                            /*!< Description collection[0]: Channel group 0                            */
+  __I  uint32_t  RESERVED3[62];
+  PPI_FORK_Type FORK[32];                           /*!< Fork                                                                  */
+} NRF_PPI_Type;
+
+
+/* ================================================================================ */
+/* ================                       MWU                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Memory Watch Unit (MWU)
+  */
+
+typedef struct {                                    /*!< MWU Structure                                                         */
+  __I  uint32_t  RESERVED0[64];
+  MWU_EVENTS_REGION_Type EVENTS_REGION[4];          /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED1[16];
+  MWU_EVENTS_PREGION_Type EVENTS_PREGION[2];        /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED2[100];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[5];
+  __IO uint32_t  NMIEN;                             /*!< Enable or disable non-maskable interrupt                              */
+  __IO uint32_t  NMIENSET;                          /*!< Enable non-maskable interrupt                                         */
+  __IO uint32_t  NMIENCLR;                          /*!< Disable non-maskable interrupt                                        */
+  __I  uint32_t  RESERVED4[53];
+  MWU_PERREGION_Type PERREGION[2];                  /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED5[64];
+  __IO uint32_t  REGIONEN;                          /*!< Enable/disable regions watch                                          */
+  __IO uint32_t  REGIONENSET;                       /*!< Enable regions watch                                                  */
+  __IO uint32_t  REGIONENCLR;                       /*!< Disable regions watch                                                 */
+  __I  uint32_t  RESERVED6[57];
+  MWU_REGION_Type REGION[4];                        /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED7[32];
+  MWU_PREGION_Type PREGION[2];                      /*!< Unspecified                                                           */
+} NRF_MWU_Type;
+
+
+/* ================================================================================ */
+/* ================                       I2S                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Inter-IC Sound (I2S)
+  */
+
+typedef struct {                                    /*!< I2S Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Starts continuous I2S transfer. Also starts MCK generator when
+                                                         this is enabled.                                                      */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stops I2S transfer. Also stops MCK generator. Triggering this
+                                                         task will cause the {event:STOPPED} event to be generated.            */
+  __I  uint32_t  RESERVED0[63];
+  __IO uint32_t  EVENTS_RXPTRUPD;                   /*!< The RXD.PTR register has been copied to internal double-buffers.
+                                                         When the I2S module is started and RX is enabled, this event
+                                                          will be generated for every RXTXD.MAXCNT words that are received
+                                                          on the SDIN pin.                                                     */
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< I2S transfer stopped.                                                 */
+  __I  uint32_t  RESERVED1[2];
+  __IO uint32_t  EVENTS_TXPTRUPD;                   /*!< The TDX.PTR register has been copied to internal double-buffers.
+                                                         When the I2S module is started and TX is enabled, this event
+                                                          will be generated for every RXTXD.MAXCNT words that are sent
+                                                          on the SDOUT pin.                                                    */
+  __I  uint32_t  RESERVED2[122];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[125];
+  __IO uint32_t  ENABLE;                            /*!< Enable I2S module.                                                    */
+  I2S_CONFIG_Type CONFIG;                           /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED4[3];
+  I2S_RXD_Type RXD;                                 /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED5;
+  I2S_TXD_Type TXD;                                 /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED6[3];
+  I2S_RXTXD_Type RXTXD;                             /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED7[3];
+  I2S_PSEL_Type PSEL;                               /*!< Unspecified                                                           */
+} NRF_I2S_Type;
+
+
+/* ================================================================================ */
+/* ================                       FPU                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief FPU (FPU)
+  */
+
+typedef struct {                                    /*!< FPU Structure                                                         */
+  __I  uint32_t  UNUSED;                            /*!< Unused.                                                               */
+} NRF_FPU_Type;
+
+
+/* ================================================================================ */
+/* ================                      USBD                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Universal Serial Bus device (USBD)
+  */
+
+typedef struct {                                    /*!< USBD Structure                                                        */
+  __I  uint32_t  RESERVED0;
+  __O  uint32_t  TASKS_STARTEPIN[8];                /*!< Description collection[0]: Captures the EPIN[0].PTR, EPIN[0].MAXCNT
+                                                         and EPIN[0].CONFIG registers values, and enables endpoint IN
+                                                          0 to respond to traffic from host                                    */
+  __O  uint32_t  TASKS_STARTISOIN;                  /*!< Captures the ISOIN.PTR, ISOIN.MAXCNT and ISOIN.CONFIG registers
+                                                         values, and enables sending data on iso endpoint                      */
+  __O  uint32_t  TASKS_STARTEPOUT[8];               /*!< Description collection[0]: Captures the EPOUT[0].PTR, EPOUT[0].MAXCNT
+                                                         and EPOUT[0].CONFIG registers values, and enables endpoint 0
+                                                          to respond to traffic from host                                      */
+  __O  uint32_t  TASKS_STARTISOOUT;                 /*!< Captures the ISOOUT.PTR, ISOOUT.MAXCNT and ISOOUT.CONFIG registers
+                                                         values, and enables receiving of data on iso endpoint                 */
+  __O  uint32_t  TASKS_EP0RCVOUT;                   /*!< Allows OUT data stage on control endpoint 0                           */
+  __O  uint32_t  TASKS_EP0STATUS;                   /*!< Allows status stage on control endpoint 0                             */
+  __O  uint32_t  TASKS_EP0STALL;                    /*!< STALLs data and status stage on control endpoint 0                    */
+  __O  uint32_t  TASKS_DPDMDRIVE;                   /*!< Forces D+ and D-lines to the state defined in the DPDMVALUE
+                                                         register                                                              */
+  __O  uint32_t  TASKS_DPDMNODRIVE;                 /*!< Stops forcing D+ and D- lines to any state (USB engine takes
+                                                         control)                                                              */
+  __I  uint32_t  RESERVED1[40];
+  __IO uint32_t  EVENTS_USBRESET;                   /*!< Signals that a USB reset condition has been detected on the
+                                                         USB lines                                                             */
+  __IO uint32_t  EVENTS_STARTED;                    /*!< Confirms that the EPIN[n].PTR, EPIN[n].MAXCNT, EPIN[n].CONFIG,
+                                                         or EPOUT[n].PTR, EPOUT[n].MAXCNT and EPOUT[n].CONFIG registers
+                                                          have been captured on all endpoints reported in the EPSTATUS
+                                                          register                                                             */
+  __IO uint32_t  EVENTS_ENDEPIN[8];                 /*!< Description collection[0]: The whole EPIN[0] buffer has been
+                                                         consumed. The RAM buffer can be accessed safely by software.          */
+  __IO uint32_t  EVENTS_EP0DATADONE;                /*!< An acknowledged data transfer has taken place on the control
+                                                         endpoint                                                              */
+  __IO uint32_t  EVENTS_ENDISOIN;                   /*!< The whole ISOIN buffer has been consumed. The RAM buffer can
+                                                         be accessed safely by software.                                       */
+  __IO uint32_t  EVENTS_ENDEPOUT[8];                /*!< Description collection[0]: The whole EPOUT[0] buffer has been
+                                                         consumed. The RAM buffer can be accessed safely by software.          */
+  __IO uint32_t  EVENTS_ENDISOOUT;                  /*!< The whole ISOOUT buffer has been consumed. The RAM buffer can
+                                                         be accessed safely by software.                                       */
+  __IO uint32_t  EVENTS_SOF;                        /*!< Signals that a SOF (start of frame) condition has been detected
+                                                         on the USB lines                                                      */
+  __IO uint32_t  EVENTS_USBEVENT;                   /*!< An event or an error not covered by specific events has occurred,
+                                                         check EVENTCAUSE register to find the cause                           */
+  __IO uint32_t  EVENTS_EP0SETUP;                   /*!< A valid SETUP token has been received (and acknowledged) on
+                                                         the control endpoint                                                  */
+  __IO uint32_t  EVENTS_EPDATA;                     /*!< A data transfer has occurred on a data endpoint, indicated by
+                                                         the EPDATASTATUS register                                             */
+  __IO uint32_t  EVENTS_ACCESSFAULT;                /*!< Access to an unavailable USB register has been attempted (software
+                                                         or EasyDMA). This event can get fired even when USBD is not
+                                                          ENABLEd.                                                             */
+  __I  uint32_t  RESERVED2[38];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED3[63];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED4[61];
+  __IO uint32_t  EVENTCAUSE;                        /*!< Details on event that caused the USBEVENT event                       */
+  __I  uint32_t  BUSSTATE;                          /*!< Provides the logic state of the D+ and D- lines                       */
+  __I  uint32_t  RESERVED5[6];
+  USBD_HALTED_Type HALTED;                          /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED6;
+  __IO uint32_t  EPSTATUS;                          /*!< Provides information on which endpoint's EasyDMA registers have
+                                                         been captured                                                         */
+  __IO uint32_t  EPDATASTATUS;                      /*!< Provides information on which endpoint(s) an acknowledged data
+                                                         transfer has occurred (EPDATA event)                                  */
+  __I  uint32_t  USBADDR;                           /*!< Device USB address                                                    */
+  __I  uint32_t  RESERVED7[3];
+  __I  uint32_t  BMREQUESTTYPE;                     /*!< SETUP data, byte 0, bmRequestType                                     */
+  __I  uint32_t  BREQUEST;                          /*!< SETUP data, byte 1, bRequest                                          */
+  __I  uint32_t  WVALUEL;                           /*!< SETUP data, byte 2, LSB of wValue                                     */
+  __I  uint32_t  WVALUEH;                           /*!< SETUP data, byte 3, MSB of wValue                                     */
+  __I  uint32_t  WINDEXL;                           /*!< SETUP data, byte 4, LSB of wIndex                                     */
+  __I  uint32_t  WINDEXH;                           /*!< SETUP data, byte 5, MSB of wIndex                                     */
+  __I  uint32_t  WLENGTHL;                          /*!< SETUP data, byte 6, LSB of wLength                                    */
+  __I  uint32_t  WLENGTHH;                          /*!< SETUP data, byte 7, MSB of wLength                                    */
+  USBD_SIZE_Type SIZE;                              /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED8[15];
+  __IO uint32_t  ENABLE;                            /*!< Enable USB                                                            */
+  __IO uint32_t  USBPULLUP;                         /*!< Control of the USB pull-up                                            */
+  __IO uint32_t  DPDMVALUE;                         /*!< State at which the DPDMDRIVE task will force D+ and D-. The
+                                                         DPDMNODRIVE task reverts the control of the lines to MAC IP
+                                                          (no forcing).                                                        */
+  __IO uint32_t  DTOGGLE;                           /*!< Data toggle control and status.                                       */
+  __IO uint32_t  EPINEN;                            /*!< Endpoint IN enable                                                    */
+  __IO uint32_t  EPOUTEN;                           /*!< Endpoint OUT enable                                                   */
+  __O  uint32_t  EPSTALL;                           /*!< STALL endpoints                                                       */
+  __IO uint32_t  ISOSPLIT;                          /*!< Controls the split of ISO buffers                                     */
+  __I  uint32_t  FRAMECNTR;                         /*!< Returns the current value of the start of frame counter               */
+  __I  uint32_t  RESERVED9[3];
+  __IO uint32_t  ISOINCONFIG;                       /*!< Controls the response of the ISO IN endpoint to an IN token
+                                                         when no data is ready to be sent                                      */
+  __I  uint32_t  RESERVED10[51];
+  USBD_EPIN_Type EPIN[8];                           /*!< Unspecified                                                           */
+  USBD_ISOIN_Type ISOIN;                            /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED11[21];
+  USBD_EPOUT_Type EPOUT[8];                         /*!< Unspecified                                                           */
+  USBD_ISOOUT_Type ISOOUT;                          /*!< Unspecified                                                           */
+} NRF_USBD_Type;
+
+
+/* ================================================================================ */
+/* ================                      QSPI                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief External flash interface (QSPI)
+  */
+
+typedef struct {                                    /*!< QSPI Structure                                                        */
+  __O  uint32_t  TASKS_ACTIVATE;                    /*!< Activate QSPI interface                                               */
+  __O  uint32_t  TASKS_READSTART;                   /*!< Start transfer from external flash memory to internal RAM             */
+  __O  uint32_t  TASKS_WRITESTART;                  /*!< Start transfer from internal RAM to external flash memory             */
+  __O  uint32_t  TASKS_ERASESTART;                  /*!< Start external flash memory erase operation                           */
+  __I  uint32_t  RESERVED0[60];
+  __IO uint32_t  EVENTS_READY;                      /*!< QSPI peripheral is ready. This event will be generated as a
+                                                         response to any QSPI task.                                            */
+  __I  uint32_t  RESERVED1[127];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED2[125];
+  __IO uint32_t  ENABLE;                            /*!< Enable QSPI peripheral and acquire the pins selected in PSELn
+                                                         registers                                                             */
+  QSPI_READ_Type READ;                              /*!< Unspecified                                                           */
+  QSPI_WRITE_Type WRITE;                            /*!< Unspecified                                                           */
+  QSPI_ERASE_Type ERASE;                            /*!< Unspecified                                                           */
+  QSPI_PSEL_Type PSEL;                              /*!< Unspecified                                                           */
+  __IO uint32_t  XIPOFFSET;                         /*!< Address offset into the external memory for Execute in Place
+                                                         operation.                                                            */
+  __IO uint32_t  IFCONFIG0;                         /*!< Interface configuration.                                              */
+  __I  uint32_t  RESERVED3[46];
+  __IO uint32_t  IFCONFIG1;                         /*!< Interface configuration.                                              */
+  __I  uint32_t  STATUS;                            /*!< Status register.                                                      */
+  __I  uint32_t  RESERVED4[3];
+  __IO uint32_t  DPMDUR;                            /*!< Set the duration required to enter/exit deep power-down mode
+                                                         (DPM).                                                                */
+  __I  uint32_t  RESERVED5[3];
+  __IO uint32_t  ADDRCONF;                          /*!< Extended address configuration.                                       */
+  __I  uint32_t  RESERVED6[3];
+  __IO uint32_t  CINSTRCONF;                        /*!< Custom instruction configuration register.                            */
+  __IO uint32_t  CINSTRDAT0;                        /*!< Custom instruction data register 0.                                   */
+  __IO uint32_t  CINSTRDAT1;                        /*!< Custom instruction data register 1.                                   */
+  __IO uint32_t  IFTIMING;                          /*!< SPI interface timing.                                                 */
+} NRF_QSPI_Type;
+
+
+/* ================================================================================ */
+/* ================                      GPIO                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief GPIO Port 1 (GPIO)
+  */
+
+typedef struct {                                    /*!< GPIO Structure                                                        */
+  __I  uint32_t  RESERVED0[321];
+  __IO uint32_t  OUT;                               /*!< Write GPIO port                                                       */
+  __IO uint32_t  OUTSET;                            /*!< Set individual bits in GPIO port                                      */
+  __IO uint32_t  OUTCLR;                            /*!< Clear individual bits in GPIO port                                    */
+  __I  uint32_t  IN;                                /*!< Read GPIO port                                                        */
+  __IO uint32_t  DIR;                               /*!< Direction of GPIO pins                                                */
+  __IO uint32_t  DIRSET;                            /*!< DIR set register                                                      */
+  __IO uint32_t  DIRCLR;                            /*!< DIR clear register                                                    */
+  __IO uint32_t  LATCH;                             /*!< Latch register indicating what GPIO pins that have met the criteria
+                                                         set in the PIN_CNF[n].SENSE registers                                 */
+  __IO uint32_t  DETECTMODE;                        /*!< Select between default DETECT signal behaviour and LDETECT mode       */
+  __I  uint32_t  RESERVED1[118];
+  __IO uint32_t  PIN_CNF[32];                       /*!< Description collection[0]: Configuration of GPIO pins                 */
+} NRF_GPIO_Type;
+
+
+/* ================================================================================ */
+/* ================                   CRYPTOCELL                   ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief ARM CryptoCell register interface (CRYPTOCELL)
+  */
+
+typedef struct {                                    /*!< CRYPTOCELL Structure                                                  */
+  __I  uint32_t  RESERVED0[320];
+  __IO uint32_t  ENABLE;                            /*!< Control power and clock for ARM CryptoCell subsystem                  */
+} NRF_CRYPTOCELL_Type;
+
+
+/* --------------------  End of section using anonymous unions  ------------------- */
+#if defined(__CC_ARM)
+  #pragma pop
+#elif defined(__ICCARM__)
+  /* leave anonymous unions enabled */
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+  /* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+  #pragma warning restore
+#else
+  #warning Not supported compiler type
+#endif
+
+
+
+
+/* ================================================================================ */
+/* ================              Peripheral memory map             ================ */
+/* ================================================================================ */
+
+#define NRF_FICR_BASE                   0x10000000UL
+#define NRF_UICR_BASE                   0x10001000UL
+#define NRF_POWER_BASE                  0x40000000UL
+#define NRF_CLOCK_BASE                  0x40000000UL
+#define NRF_RADIO_BASE                  0x40001000UL
+#define NRF_UARTE0_BASE                 0x40002000UL
+#define NRF_UART0_BASE                  0x40002000UL
+#define NRF_SPIM0_BASE                  0x40003000UL
+#define NRF_SPIS0_BASE                  0x40003000UL
+#define NRF_TWIM0_BASE                  0x40003000UL
+#define NRF_TWIS0_BASE                  0x40003000UL
+#define NRF_SPI0_BASE                   0x40003000UL
+#define NRF_TWI0_BASE                   0x40003000UL
+#define NRF_SPIM1_BASE                  0x40004000UL
+#define NRF_SPIS1_BASE                  0x40004000UL
+#define NRF_TWIM1_BASE                  0x40004000UL
+#define NRF_TWIS1_BASE                  0x40004000UL
+#define NRF_SPI1_BASE                   0x40004000UL
+#define NRF_TWI1_BASE                   0x40004000UL
+#define NRF_NFCT_BASE                   0x40005000UL
+#define NRF_GPIOTE_BASE                 0x40006000UL
+#define NRF_SAADC_BASE                  0x40007000UL
+#define NRF_TIMER0_BASE                 0x40008000UL
+#define NRF_TIMER1_BASE                 0x40009000UL
+#define NRF_TIMER2_BASE                 0x4000A000UL
+#define NRF_RTC0_BASE                   0x4000B000UL
+#define NRF_TEMP_BASE                   0x4000C000UL
+#define NRF_RNG_BASE                    0x4000D000UL
+#define NRF_ECB_BASE                    0x4000E000UL
+#define NRF_CCM_BASE                    0x4000F000UL
+#define NRF_AAR_BASE                    0x4000F000UL
+#define NRF_WDT_BASE                    0x40010000UL
+#define NRF_RTC1_BASE                   0x40011000UL
+#define NRF_QDEC_BASE                   0x40012000UL
+#define NRF_COMP_BASE                   0x40013000UL
+#define NRF_LPCOMP_BASE                 0x40013000UL
+#define NRF_SWI0_BASE                   0x40014000UL
+#define NRF_EGU0_BASE                   0x40014000UL
+#define NRF_SWI1_BASE                   0x40015000UL
+#define NRF_EGU1_BASE                   0x40015000UL
+#define NRF_SWI2_BASE                   0x40016000UL
+#define NRF_EGU2_BASE                   0x40016000UL
+#define NRF_SWI3_BASE                   0x40017000UL
+#define NRF_EGU3_BASE                   0x40017000UL
+#define NRF_SWI4_BASE                   0x40018000UL
+#define NRF_EGU4_BASE                   0x40018000UL
+#define NRF_SWI5_BASE                   0x40019000UL
+#define NRF_EGU5_BASE                   0x40019000UL
+#define NRF_TIMER3_BASE                 0x4001A000UL
+#define NRF_TIMER4_BASE                 0x4001B000UL
+#define NRF_PWM0_BASE                   0x4001C000UL
+#define NRF_PDM_BASE                    0x4001D000UL
+#define NRF_NVMC_BASE                   0x4001E000UL
+#define NRF_ACL_BASE                    0x4001E000UL
+#define NRF_PPI_BASE                    0x4001F000UL
+#define NRF_MWU_BASE                    0x40020000UL
+#define NRF_PWM1_BASE                   0x40021000UL
+#define NRF_PWM2_BASE                   0x40022000UL
+#define NRF_SPIM2_BASE                  0x40023000UL
+#define NRF_SPIS2_BASE                  0x40023000UL
+#define NRF_SPI2_BASE                   0x40023000UL
+#define NRF_RTC2_BASE                   0x40024000UL
+#define NRF_I2S_BASE                    0x40025000UL
+#define NRF_FPU_BASE                    0x40026000UL
+#define NRF_USBD_BASE                   0x40027000UL
+#define NRF_UARTE1_BASE                 0x40028000UL
+#define NRF_QSPI_BASE                   0x40029000UL
+#define NRF_SPIM3_BASE                  0x4002B000UL
+#define NRF_PWM3_BASE                   0x4002D000UL
+#define NRF_P0_BASE                     0x50000000UL
+#define NRF_P1_BASE                     0x50000300UL
+#define NRF_CRYPTOCELL_BASE             0x5002A000UL
+
+
+/* ================================================================================ */
+/* ================             Peripheral declaration             ================ */
+/* ================================================================================ */
+
+#define NRF_FICR                        ((NRF_FICR_Type           *) NRF_FICR_BASE)
+#define NRF_UICR                        ((NRF_UICR_Type           *) NRF_UICR_BASE)
+#define NRF_POWER                       ((NRF_POWER_Type          *) NRF_POWER_BASE)
+#define NRF_CLOCK                       ((NRF_CLOCK_Type          *) NRF_CLOCK_BASE)
+#define NRF_RADIO                       ((NRF_RADIO_Type          *) NRF_RADIO_BASE)
+#define NRF_UARTE0                      ((NRF_UARTE_Type          *) NRF_UARTE0_BASE)
+#define NRF_UART0                       ((NRF_UART_Type           *) NRF_UART0_BASE)
+#define NRF_SPIM0                       ((NRF_SPIM_Type           *) NRF_SPIM0_BASE)
+#define NRF_SPIS0                       ((NRF_SPIS_Type           *) NRF_SPIS0_BASE)
+#define NRF_TWIM0                       ((NRF_TWIM_Type           *) NRF_TWIM0_BASE)
+#define NRF_TWIS0                       ((NRF_TWIS_Type           *) NRF_TWIS0_BASE)
+#define NRF_SPI0                        ((NRF_SPI_Type            *) NRF_SPI0_BASE)
+#define NRF_TWI0                        ((NRF_TWI_Type            *) NRF_TWI0_BASE)
+#define NRF_SPIM1                       ((NRF_SPIM_Type           *) NRF_SPIM1_BASE)
+#define NRF_SPIS1                       ((NRF_SPIS_Type           *) NRF_SPIS1_BASE)
+#define NRF_TWIM1                       ((NRF_TWIM_Type           *) NRF_TWIM1_BASE)
+#define NRF_TWIS1                       ((NRF_TWIS_Type           *) NRF_TWIS1_BASE)
+#define NRF_SPI1                        ((NRF_SPI_Type            *) NRF_SPI1_BASE)
+#define NRF_TWI1                        ((NRF_TWI_Type            *) NRF_TWI1_BASE)
+#define NRF_NFCT                        ((NRF_NFCT_Type           *) NRF_NFCT_BASE)
+#define NRF_GPIOTE                      ((NRF_GPIOTE_Type         *) NRF_GPIOTE_BASE)
+#define NRF_SAADC                       ((NRF_SAADC_Type          *) NRF_SAADC_BASE)
+#define NRF_TIMER0                      ((NRF_TIMER_Type          *) NRF_TIMER0_BASE)
+#define NRF_TIMER1                      ((NRF_TIMER_Type          *) NRF_TIMER1_BASE)
+#define NRF_TIMER2                      ((NRF_TIMER_Type          *) NRF_TIMER2_BASE)
+#define NRF_RTC0                        ((NRF_RTC_Type            *) NRF_RTC0_BASE)
+#define NRF_TEMP                        ((NRF_TEMP_Type           *) NRF_TEMP_BASE)
+#define NRF_RNG                         ((NRF_RNG_Type            *) NRF_RNG_BASE)
+#define NRF_ECB                         ((NRF_ECB_Type            *) NRF_ECB_BASE)
+#define NRF_CCM                         ((NRF_CCM_Type            *) NRF_CCM_BASE)
+#define NRF_AAR                         ((NRF_AAR_Type            *) NRF_AAR_BASE)
+#define NRF_WDT                         ((NRF_WDT_Type            *) NRF_WDT_BASE)
+#define NRF_RTC1                        ((NRF_RTC_Type            *) NRF_RTC1_BASE)
+#define NRF_QDEC                        ((NRF_QDEC_Type           *) NRF_QDEC_BASE)
+#define NRF_COMP                        ((NRF_COMP_Type           *) NRF_COMP_BASE)
+#define NRF_LPCOMP                      ((NRF_LPCOMP_Type         *) NRF_LPCOMP_BASE)
+#define NRF_SWI0                        ((NRF_SWI_Type            *) NRF_SWI0_BASE)
+#define NRF_EGU0                        ((NRF_EGU_Type            *) NRF_EGU0_BASE)
+#define NRF_SWI1                        ((NRF_SWI_Type            *) NRF_SWI1_BASE)
+#define NRF_EGU1                        ((NRF_EGU_Type            *) NRF_EGU1_BASE)
+#define NRF_SWI2                        ((NRF_SWI_Type            *) NRF_SWI2_BASE)
+#define NRF_EGU2                        ((NRF_EGU_Type            *) NRF_EGU2_BASE)
+#define NRF_SWI3                        ((NRF_SWI_Type            *) NRF_SWI3_BASE)
+#define NRF_EGU3                        ((NRF_EGU_Type            *) NRF_EGU3_BASE)
+#define NRF_SWI4                        ((NRF_SWI_Type            *) NRF_SWI4_BASE)
+#define NRF_EGU4                        ((NRF_EGU_Type            *) NRF_EGU4_BASE)
+#define NRF_SWI5                        ((NRF_SWI_Type            *) NRF_SWI5_BASE)
+#define NRF_EGU5                        ((NRF_EGU_Type            *) NRF_EGU5_BASE)
+#define NRF_TIMER3                      ((NRF_TIMER_Type          *) NRF_TIMER3_BASE)
+#define NRF_TIMER4                      ((NRF_TIMER_Type          *) NRF_TIMER4_BASE)
+#define NRF_PWM0                        ((NRF_PWM_Type            *) NRF_PWM0_BASE)
+#define NRF_PDM                         ((NRF_PDM_Type            *) NRF_PDM_BASE)
+#define NRF_NVMC                        ((NRF_NVMC_Type           *) NRF_NVMC_BASE)
+#define NRF_ACL                         ((NRF_ACL_Type            *) NRF_ACL_BASE)
+#define NRF_PPI                         ((NRF_PPI_Type            *) NRF_PPI_BASE)
+#define NRF_MWU                         ((NRF_MWU_Type            *) NRF_MWU_BASE)
+#define NRF_PWM1                        ((NRF_PWM_Type            *) NRF_PWM1_BASE)
+#define NRF_PWM2                        ((NRF_PWM_Type            *) NRF_PWM2_BASE)
+#define NRF_SPIM2                       ((NRF_SPIM_Type           *) NRF_SPIM2_BASE)
+#define NRF_SPIS2                       ((NRF_SPIS_Type           *) NRF_SPIS2_BASE)
+#define NRF_SPI2                        ((NRF_SPI_Type            *) NRF_SPI2_BASE)
+#define NRF_RTC2                        ((NRF_RTC_Type            *) NRF_RTC2_BASE)
+#define NRF_I2S                         ((NRF_I2S_Type            *) NRF_I2S_BASE)
+#define NRF_FPU                         ((NRF_FPU_Type            *) NRF_FPU_BASE)
+#define NRF_USBD                        ((NRF_USBD_Type           *) NRF_USBD_BASE)
+#define NRF_UARTE1                      ((NRF_UARTE_Type          *) NRF_UARTE1_BASE)
+#define NRF_QSPI                        ((NRF_QSPI_Type           *) NRF_QSPI_BASE)
+#define NRF_SPIM3                       ((NRF_SPIM_Type           *) NRF_SPIM3_BASE)
+#define NRF_PWM3                        ((NRF_PWM_Type            *) NRF_PWM3_BASE)
+#define NRF_P0                          ((NRF_GPIO_Type           *) NRF_P0_BASE)
+#define NRF_P1                          ((NRF_GPIO_Type           *) NRF_P1_BASE)
+#define NRF_CRYPTOCELL                  ((NRF_CRYPTOCELL_Type     *) NRF_CRYPTOCELL_BASE)
+
+
+/** @} */ /* End of group Device_Peripheral_Registers */
+/** @} */ /* End of group nrf52840 */
+/** @} */ /* End of group Nordic Semiconductor */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif  /* nrf52840_H */
+
diff --git a/ports/nrf/device/nrf52/nrf52840_bitfields.h b/ports/nrf/device/nrf52/nrf52840_bitfields.h
new file mode 100644
index 0000000000..17f63b4ec2
--- /dev/null
+++ b/ports/nrf/device/nrf52/nrf52840_bitfields.h
@@ -0,0 +1,14633 @@
+/* Copyright (c) 2016, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *   * Redistributions of source code must retain the above copyright notice, this
+ *     list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *
+ *   * Neither the name of Nordic Semiconductor ASA nor the names of its
+ *     contributors may be used to endorse or promote products derived from
+ *     this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+ 
+#ifndef __NRF52840_BITS_H
+#define __NRF52840_BITS_H
+
+/*lint ++flb "Enter library region" */
+
+/* Peripheral: AAR */
+/* Description: Accelerated Address Resolver */
+
+/* Register: AAR_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 2 : Write '1' to Enable interrupt for NOTRESOLVED event */
+#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
+#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
+#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
+#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
+#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for RESOLVED event */
+#define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
+#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
+#define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
+#define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
+#define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for END event */
+#define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
+#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define AAR_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Register: AAR_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 2 : Write '1' to Disable interrupt for NOTRESOLVED event */
+#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
+#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
+#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
+#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
+#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for RESOLVED event */
+#define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
+#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
+#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
+#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
+#define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for END event */
+#define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
+#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Register: AAR_STATUS */
+/* Description: Resolution status */
+
+/* Bits 3..0 : The IRK that was used last time an address was resolved */
+#define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
+
+/* Register: AAR_ENABLE */
+/* Description: Enable AAR */
+
+/* Bits 1..0 : Enable or disable AAR */
+#define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */
+
+/* Register: AAR_NIRK */
+/* Description: Number of IRKs */
+
+/* Bits 4..0 : Number of Identity root keys available in the IRK data structure */
+#define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
+#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
+
+/* Register: AAR_IRKPTR */
+/* Description: Pointer to IRK data structure */
+
+/* Bits 31..0 : Pointer to the IRK data structure */
+#define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */
+#define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */
+
+/* Register: AAR_ADDRPTR */
+/* Description: Pointer to the resolvable address */
+
+/* Bits 31..0 : Pointer to the resolvable address (6-bytes) */
+#define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */
+#define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */
+
+/* Register: AAR_SCRATCHPTR */
+/* Description: Pointer to data area used for temporary storage */
+
+/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. */
+#define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
+#define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
+
+
+/* Peripheral: ACL */
+/* Description: Access control lists */
+
+/* Register: ACL_DISABLEINDEBUG */
+/* Description: Disable all ACL protection mechanisms for regions while in debug mode */
+
+/* Bit 0 : Disable the protection mechanism for regions while in debug mode. */
+#define ACL_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */
+#define ACL_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << ACL_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */
+#define ACL_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< ACL is enabled in debug mode */
+#define ACL_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< ACL is disabled in debug mode */
+
+/* Register: ACL_ACL_ADDR */
+/* Description: Description cluster[0]:  Configure the word-aligned start address of region 0 to protect */
+
+/* Bits 31..0 : Valid word-aligned start address of region 0 to protect. Address must point to a flash page boundary. */
+#define ACL_ACL_ADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */
+#define ACL_ACL_ADDR_ADDR_Msk (0xFFFFFFFFUL << ACL_ACL_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */
+
+/* Register: ACL_ACL_SIZE */
+/* Description: Description cluster[0]:  Size of region to protect counting from address ACL[0].ADDR. Write '0' as no effect. */
+
+/* Bits 31..0 : Size of flash region 0 in bytes. Must be a multiple of the flash page size. */
+#define ACL_ACL_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */
+#define ACL_ACL_SIZE_SIZE_Msk (0xFFFFFFFFUL << ACL_ACL_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */
+
+/* Register: ACL_ACL_PERM */
+/* Description: Description cluster[0]:  Access permissions for region 0 as defined by start address ACL[0].ADDR and size ACL[0].SIZE */
+
+/* Bit 2 : Configure read permissions for region 0. Write '0' has no effect. */
+#define ACL_ACL_PERM_READ_Pos (2UL) /*!< Position of READ field. */
+#define ACL_ACL_PERM_READ_Msk (0x1UL << ACL_ACL_PERM_READ_Pos) /*!< Bit mask of READ field. */
+#define ACL_ACL_PERM_READ_Enable (0UL) /*!< Allow read instructions to region 0 */
+#define ACL_ACL_PERM_READ_Disable (1UL) /*!< Block read instructions to region 0 */
+
+/* Bit 1 : Configure write and erase permissions for region 0. Write '0' has no effect. */
+#define ACL_ACL_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */
+#define ACL_ACL_PERM_WRITE_Msk (0x1UL << ACL_ACL_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */
+#define ACL_ACL_PERM_WRITE_Enable (0UL) /*!< Allow write and erase instructions to region 0 */
+#define ACL_ACL_PERM_WRITE_Disable (1UL) /*!< Block write and erase instructions to region 0 */
+
+
+/* Peripheral: CCM */
+/* Description: AES CCM Mode Encryption */
+
+/* Register: CCM_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: CCM_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 2 : Write '1' to Enable interrupt for ERROR event */
+#define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
+#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for ENDCRYPT event */
+#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
+#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
+#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
+#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
+#define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for ENDKSGEN event */
+#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
+#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
+#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
+#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
+#define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */
+
+/* Register: CCM_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 2 : Write '1' to Disable interrupt for ERROR event */
+#define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
+#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for ENDCRYPT event */
+#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
+#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
+#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
+#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
+#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for ENDKSGEN event */
+#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
+#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
+#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
+#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
+#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */
+
+/* Register: CCM_MICSTATUS */
+/* Description: MIC check result */
+
+/* Bit 0 : The result of the MIC check performed during the previous decryption operation */
+#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
+#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
+#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed */
+#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */
+
+/* Register: CCM_ENABLE */
+/* Description: Enable */
+
+/* Bits 1..0 : Enable or disable CCM */
+#define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
+
+/* Register: CCM_MODE */
+/* Description: Operation mode */
+
+/* Bit 24 : Packet length configuration */
+#define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */
+#define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */
+#define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packets up to 27 bytes will be generated. */
+#define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packets up to MAXPACKETSIZE bytes will be generated. */
+
+/* Bits 17..16 : Radio data rate that the CCM shall run synchronous with */
+#define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */
+#define CCM_MODE_DATARATE_Msk (0x3UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */
+#define CCM_MODE_DATARATE_1Mbit (0UL) /*!< 1 Mbps */
+#define CCM_MODE_DATARATE_2Mbit (1UL) /*!< 2 Mbps */
+#define CCM_MODE_DATARATE_125Kbps (2UL) /*!< 125 Kbps */
+#define CCM_MODE_DATARATE_500Kbps (3UL) /*!< 500 Kbps */
+
+/* Bit 0 : The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered. */
+#define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */
+#define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */
+
+/* Register: CCM_CNFPTR */
+/* Description: Pointer to data structure holding AES key and NONCE vector */
+
+/* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) */
+#define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */
+#define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */
+
+/* Register: CCM_INPTR */
+/* Description: Input pointer */
+
+/* Bits 31..0 : Input pointer */
+#define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */
+#define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */
+
+/* Register: CCM_OUTPTR */
+/* Description: Output pointer */
+
+/* Bits 31..0 : Output pointer */
+#define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */
+#define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */
+
+/* Register: CCM_SCRATCHPTR */
+/* Description: Pointer to data area used for temporary storage */
+
+/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption. */
+#define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
+#define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
+
+/* Register: CCM_MAXPACKETSIZE */
+/* Description: Length of key-stream generated when MODE.LENGTH = Extended. */
+
+/* Bits 7..0 : Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet to be encrypted/decrypted. */
+#define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos (0UL) /*!< Position of MAXPACKETSIZE field. */
+#define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Msk (0xFFUL << CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) /*!< Bit mask of MAXPACKETSIZE field. */
+
+/* Register: CCM_RATEOVERRIDE */
+/* Description: Data rate override setting. */
+
+/* Bits 1..0 : Data rate override setting. */
+#define CCM_RATEOVERRIDE_RATEOVERRIDE_Pos (0UL) /*!< Position of RATEOVERRIDE field. */
+#define CCM_RATEOVERRIDE_RATEOVERRIDE_Msk (0x3UL << CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) /*!< Bit mask of RATEOVERRIDE field. */
+#define CCM_RATEOVERRIDE_RATEOVERRIDE_1Mbit (0UL) /*!< 1 Mbps */
+#define CCM_RATEOVERRIDE_RATEOVERRIDE_2Mbit (1UL) /*!< 2 Mbps */
+#define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbps (2UL) /*!< 125 Kbps */
+#define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbps (3UL) /*!< 500 Kbps */
+
+
+/* Peripheral: CLOCK */
+/* Description: Clock control */
+
+/* Register: CLOCK_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 4 : Write '1' to Enable interrupt for CTTO event */
+#define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
+#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
+#define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for DONE event */
+#define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */
+#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
+#define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for LFCLKSTARTED event */
+#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
+#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
+#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for HFCLKSTARTED event */
+#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
+#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
+#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */
+
+/* Register: CLOCK_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 4 : Write '1' to Disable interrupt for CTTO event */
+#define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
+#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
+#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for DONE event */
+#define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */
+#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
+#define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for LFCLKSTARTED event */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for HFCLKSTARTED event */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */
+
+/* Register: CLOCK_HFCLKRUN */
+/* Description: Status indicating that HFCLKSTART task has been triggered */
+
+/* Bit 0 : HFCLKSTART task triggered or not */
+#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
+#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
+#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
+
+/* Register: CLOCK_HFCLKSTAT */
+/* Description: HFCLK status */
+
+/* Bit 16 : HFCLK state */
+#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
+#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
+#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */
+#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */
+
+/* Bit 0 : Source of HFCLK */
+#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< 64 MHz internal oscillator (HFINT) */
+#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< 64 MHz crystal oscillator (HFXO) */
+
+/* Register: CLOCK_LFCLKRUN */
+/* Description: Status indicating that LFCLKSTART task has been triggered */
+
+/* Bit 0 : LFCLKSTART task triggered or not */
+#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
+#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
+#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
+
+/* Register: CLOCK_LFCLKSTAT */
+/* Description: LFCLK status */
+
+/* Bit 16 : LFCLK state */
+#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
+#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
+#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK not running */
+#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */
+
+/* Bits 1..0 : Source of LFCLK */
+#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
+#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
+#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
+#define CLOCK_LFCLKSTAT_SRC_LFULP (3UL) /*!< 32.768 kHz ultra low power RC oscillator */
+
+/* Register: CLOCK_LFCLKSRCCOPY */
+/* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */
+
+/* Bits 1..0 : Clock source */
+#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
+#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
+#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
+#define CLOCK_LFCLKSRCCOPY_SRC_LFULP (3UL) /*!< 32.768 kHz ultra low power RC oscillator */
+
+/* Register: CLOCK_LFCLKSRC */
+/* Description: Clock source for the LFCLK */
+
+/* Bit 17 : Enable or disable external source for LFCLK */
+#define CLOCK_LFCLKSRC_EXTERNAL_Pos (17UL) /*!< Position of EXTERNAL field. */
+#define CLOCK_LFCLKSRC_EXTERNAL_Msk (0x1UL << CLOCK_LFCLKSRC_EXTERNAL_Pos) /*!< Bit mask of EXTERNAL field. */
+#define CLOCK_LFCLKSRC_EXTERNAL_Disabled (0UL) /*!< Disable external source (use with Xtal) */
+#define CLOCK_LFCLKSRC_EXTERNAL_Enabled (1UL) /*!< Enable use of external source instead of Xtal (SRC needs to be set to Xtal) */
+
+/* Bit 16 : Enable or disable bypass of LFCLK crystal oscillator with external clock source */
+#define CLOCK_LFCLKSRC_BYPASS_Pos (16UL) /*!< Position of BYPASS field. */
+#define CLOCK_LFCLKSRC_BYPASS_Msk (0x1UL << CLOCK_LFCLKSRC_BYPASS_Pos) /*!< Bit mask of BYPASS field. */
+#define CLOCK_LFCLKSRC_BYPASS_Disabled (0UL) /*!< Disable (use with Xtal or low-swing external source) */
+#define CLOCK_LFCLKSRC_BYPASS_Enabled (1UL) /*!< Enable (use with rail-to-rail external source) */
+
+/* Bits 1..0 : Clock source */
+#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
+#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
+#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
+#define CLOCK_LFCLKSRC_SRC_LFULP (3UL) /*!< 32.768 kHz ultra low power RC oscillator */
+
+/* Register: CLOCK_CTIV */
+/* Description: Calibration timer interval */
+
+/* Bits 6..0 : Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. */
+#define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */
+#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */
+
+/* Register: CLOCK_TRACECONFIG */
+/* Description: Clocking options for the Trace Port debug interface */
+
+/* Bits 17..16 : Pin multiplexing of trace signals. */
+#define CLOCK_TRACECONFIG_TRACEMUX_Pos (16UL) /*!< Position of TRACEMUX field. */
+#define CLOCK_TRACECONFIG_TRACEMUX_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEMUX_Pos) /*!< Bit mask of TRACEMUX field. */
+#define CLOCK_TRACECONFIG_TRACEMUX_GPIO (0UL) /*!< GPIOs multiplexed onto all trace-pins */
+#define CLOCK_TRACECONFIG_TRACEMUX_Serial (1UL) /*!< SWO multiplexed onto P0.18, GPIO multiplexed onto other trace pins */
+#define CLOCK_TRACECONFIG_TRACEMUX_Parallel (2UL) /*!< TRACECLK and TRACEDATA multiplexed onto P0.20, P0.18, P0.16, P0.15 and P0.14. */
+
+/* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two. */
+#define CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */
+#define CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */
+#define CLOCK_TRACECONFIG_TRACEPORTSPEED_32MHz (0UL) /*!< 32 MHz Trace Port clock (TRACECLK = 16 MHz) */
+#define CLOCK_TRACECONFIG_TRACEPORTSPEED_16MHz (1UL) /*!< 16 MHz Trace Port clock (TRACECLK = 8 MHz) */
+#define CLOCK_TRACECONFIG_TRACEPORTSPEED_8MHz (2UL) /*!< 8 MHz Trace Port clock (TRACECLK = 4 MHz) */
+#define CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz (3UL) /*!< 4 MHz Trace Port clock (TRACECLK = 2 MHz) */
+
+
+/* Peripheral: COMP */
+/* Description: Comparator */
+
+/* Register: COMP_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 4 : Shortcut between CROSS event and STOP task */
+#define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
+#define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
+#define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between UP event and STOP task */
+#define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
+#define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
+#define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between DOWN event and STOP task */
+#define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
+#define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
+#define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between READY event and STOP task */
+#define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
+#define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
+#define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between READY event and SAMPLE task */
+#define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
+#define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
+#define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
+#define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: COMP_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 3 : Enable or disable interrupt for CROSS event */
+#define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */
+#define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */
+#define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */
+#define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for UP event */
+#define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */
+#define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */
+#define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */
+#define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for DOWN event */
+#define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */
+#define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */
+#define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */
+#define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for READY event */
+#define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
+#define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */
+#define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */
+#define COMP_INTEN_READY_Enabled (1UL) /*!< Enable */
+
+/* Register: COMP_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 3 : Write '1' to Enable interrupt for CROSS event */
+#define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
+#define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
+#define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for UP event */
+#define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
+#define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
+#define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENSET_UP_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for DOWN event */
+#define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
+#define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
+#define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for READY event */
+#define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
+#define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENSET_READY_Set (1UL) /*!< Enable */
+
+/* Register: COMP_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 3 : Write '1' to Disable interrupt for CROSS event */
+#define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
+#define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
+#define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for UP event */
+#define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
+#define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
+#define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for DOWN event */
+#define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
+#define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
+#define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for READY event */
+#define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
+#define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
+
+/* Register: COMP_RESULT */
+/* Description: Compare result */
+
+/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
+#define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
+#define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
+#define COMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the threshold (VIN+ &lt; VIN-) */
+#define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the threshold (VIN+ &gt; VIN-) */
+
+/* Register: COMP_ENABLE */
+/* Description: COMP enable */
+
+/* Bits 1..0 : Enable or disable COMP */
+#define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define COMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define COMP_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
+
+/* Register: COMP_PSEL */
+/* Description: Pin select */
+
+/* Bits 2..0 : Analog pin select */
+#define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
+#define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
+#define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */
+#define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
+#define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
+#define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */
+#define COMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */
+#define COMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */
+#define COMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */
+#define COMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */
+
+/* Register: COMP_REFSEL */
+/* Description: Reference source select */
+
+/* Bits 2..0 : Reference select */
+#define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
+#define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
+#define COMP_REFSEL_REFSEL_Int1V2 (0UL) /*!< VREF = internal 1.2 V reference (VDD &gt;= 1.7 V) */
+#define COMP_REFSEL_REFSEL_Int1V8 (1UL) /*!< VREF = internal 1.8 V reference (VDD &gt;= VREF + 0.2 V) */
+#define COMP_REFSEL_REFSEL_Int2V4 (2UL) /*!< VREF = internal 2.4 V reference (VDD &gt;= VREF + 0.2 V) */
+#define COMP_REFSEL_REFSEL_VDD (4UL) /*!< VREF = VDD */
+#define COMP_REFSEL_REFSEL_ARef (7UL) /*!< VREF = AREF (VDD &gt;= VREF &gt;= AREFMIN) */
+
+/* Register: COMP_EXTREFSEL */
+/* Description: External reference select */
+
+/* Bit 0 : External analog reference select */
+#define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
+#define COMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
+#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */
+#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */
+
+/* Register: COMP_TH */
+/* Description: Threshold configuration for hysteresis unit */
+
+/* Bits 13..8 : VUP = (THUP+1)/64*VREF */
+#define COMP_TH_THUP_Pos (8UL) /*!< Position of THUP field. */
+#define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */
+
+/* Bits 5..0 : VDOWN = (THDOWN+1)/64*VREF */
+#define COMP_TH_THDOWN_Pos (0UL) /*!< Position of THDOWN field. */
+#define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */
+
+/* Register: COMP_MODE */
+/* Description: Mode configuration */
+
+/* Bit 8 : Main operation mode */
+#define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */
+#define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */
+#define COMP_MODE_MAIN_SE (0UL) /*!< Single ended mode */
+#define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode */
+
+/* Bits 1..0 : Speed and power mode */
+#define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */
+#define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */
+#define COMP_MODE_SP_Low (0UL) /*!< Low power mode */
+#define COMP_MODE_SP_Normal (1UL) /*!< Normal mode */
+#define COMP_MODE_SP_High (2UL) /*!< High speed mode */
+
+/* Register: COMP_HYST */
+/* Description: Comparator hysteresis enable */
+
+/* Bit 0 : Comparator hysteresis */
+#define COMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
+#define COMP_HYST_HYST_Msk (0x1UL << COMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
+#define COMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */
+#define COMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis enabled */
+
+/* Register: COMP_ISOURCE */
+/* Description: Current source select on analog input */
+
+/* Bits 1..0 : Comparator hysteresis */
+#define COMP_ISOURCE_ISOURCE_Pos (0UL) /*!< Position of ISOURCE field. */
+#define COMP_ISOURCE_ISOURCE_Msk (0x3UL << COMP_ISOURCE_ISOURCE_Pos) /*!< Bit mask of ISOURCE field. */
+#define COMP_ISOURCE_ISOURCE_Off (0UL) /*!< Current source disabled */
+#define COMP_ISOURCE_ISOURCE_Ien2mA5 (1UL) /*!< Current source enabled (+/- 2.5 uA) */
+#define COMP_ISOURCE_ISOURCE_Ien5mA (2UL) /*!< Current source enabled (+/- 5 uA) */
+#define COMP_ISOURCE_ISOURCE_Ien10mA (3UL) /*!< Current source enabled (+/- 10 uA) */
+
+
+/* Peripheral: CRYPTOCELL */
+/* Description: ARM CryptoCell register interface */
+
+/* Register: CRYPTOCELL_ENABLE */
+/* Description: Control power and clock for ARM CryptoCell subsystem */
+
+/* Bit 0 : Enable or disable the CryptoCell subsystem */
+#define CRYPTOCELL_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define CRYPTOCELL_ENABLE_ENABLE_Msk (0x1UL << CRYPTOCELL_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define CRYPTOCELL_ENABLE_ENABLE_Disabled (0UL) /*!< CryptoCell subsystem disabled */
+#define CRYPTOCELL_ENABLE_ENABLE_Enabled (1UL) /*!< CryptoCell subsystem enabled */
+
+
+/* Peripheral: ECB */
+/* Description: AES ECB Mode Encryption */
+
+/* Register: ECB_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 1 : Write '1' to Enable interrupt for ERRORECB event */
+#define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
+#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
+#define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
+#define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
+#define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for ENDECB event */
+#define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
+#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
+#define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */
+#define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */
+#define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */
+
+/* Register: ECB_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 1 : Write '1' to Disable interrupt for ERRORECB event */
+#define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
+#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
+#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
+#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
+#define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for ENDECB event */
+#define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
+#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
+#define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */
+#define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */
+#define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */
+
+/* Register: ECB_ECBDATAPTR */
+/* Description: ECB block encrypt memory pointers */
+
+/* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */
+#define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL) /*!< Position of ECBDATAPTR field. */
+#define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos) /*!< Bit mask of ECBDATAPTR field. */
+
+
+/* Peripheral: EGU */
+/* Description: Event Generator Unit 0 */
+
+/* Register: EGU_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 15 : Enable or disable interrupt for TRIGGERED[15] event */
+#define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
+#define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
+#define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */
+
+/* Bit 14 : Enable or disable interrupt for TRIGGERED[14] event */
+#define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
+#define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
+#define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */
+
+/* Bit 13 : Enable or disable interrupt for TRIGGERED[13] event */
+#define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
+#define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
+#define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */
+
+/* Bit 12 : Enable or disable interrupt for TRIGGERED[12] event */
+#define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
+#define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
+#define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */
+
+/* Bit 11 : Enable or disable interrupt for TRIGGERED[11] event */
+#define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
+#define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
+#define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */
+
+/* Bit 10 : Enable or disable interrupt for TRIGGERED[10] event */
+#define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
+#define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
+#define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for TRIGGERED[9] event */
+#define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
+#define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
+#define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */
+
+/* Bit 8 : Enable or disable interrupt for TRIGGERED[8] event */
+#define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
+#define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
+#define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable interrupt for TRIGGERED[7] event */
+#define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
+#define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
+#define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable interrupt for TRIGGERED[6] event */
+#define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
+#define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
+#define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable interrupt for TRIGGERED[5] event */
+#define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
+#define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
+#define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for TRIGGERED[4] event */
+#define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
+#define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
+#define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable interrupt for TRIGGERED[3] event */
+#define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
+#define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
+#define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for TRIGGERED[2] event */
+#define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
+#define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
+#define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for TRIGGERED[1] event */
+#define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
+#define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
+#define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for TRIGGERED[0] event */
+#define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
+#define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
+#define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */
+
+/* Register: EGU_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 15 : Write '1' to Enable interrupt for TRIGGERED[15] event */
+#define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
+#define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
+#define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */
+
+/* Bit 14 : Write '1' to Enable interrupt for TRIGGERED[14] event */
+#define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
+#define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
+#define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */
+
+/* Bit 13 : Write '1' to Enable interrupt for TRIGGERED[13] event */
+#define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
+#define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
+#define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */
+
+/* Bit 12 : Write '1' to Enable interrupt for TRIGGERED[12] event */
+#define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
+#define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
+#define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */
+
+/* Bit 11 : Write '1' to Enable interrupt for TRIGGERED[11] event */
+#define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
+#define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
+#define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */
+
+/* Bit 10 : Write '1' to Enable interrupt for TRIGGERED[10] event */
+#define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
+#define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
+#define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to Enable interrupt for TRIGGERED[9] event */
+#define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
+#define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
+#define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */
+
+/* Bit 8 : Write '1' to Enable interrupt for TRIGGERED[8] event */
+#define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
+#define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
+#define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for TRIGGERED[7] event */
+#define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
+#define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
+#define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for TRIGGERED[6] event */
+#define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
+#define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
+#define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable interrupt for TRIGGERED[5] event */
+#define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
+#define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
+#define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for TRIGGERED[4] event */
+#define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
+#define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
+#define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for TRIGGERED[3] event */
+#define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
+#define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
+#define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for TRIGGERED[2] event */
+#define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
+#define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
+#define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for TRIGGERED[1] event */
+#define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
+#define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
+#define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for TRIGGERED[0] event */
+#define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
+#define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
+#define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */
+
+/* Register: EGU_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 15 : Write '1' to Disable interrupt for TRIGGERED[15] event */
+#define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
+#define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
+#define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */
+
+/* Bit 14 : Write '1' to Disable interrupt for TRIGGERED[14] event */
+#define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
+#define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
+#define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */
+
+/* Bit 13 : Write '1' to Disable interrupt for TRIGGERED[13] event */
+#define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
+#define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
+#define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */
+
+/* Bit 12 : Write '1' to Disable interrupt for TRIGGERED[12] event */
+#define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
+#define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
+#define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */
+
+/* Bit 11 : Write '1' to Disable interrupt for TRIGGERED[11] event */
+#define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
+#define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
+#define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */
+
+/* Bit 10 : Write '1' to Disable interrupt for TRIGGERED[10] event */
+#define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
+#define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
+#define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to Disable interrupt for TRIGGERED[9] event */
+#define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
+#define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
+#define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */
+
+/* Bit 8 : Write '1' to Disable interrupt for TRIGGERED[8] event */
+#define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
+#define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
+#define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for TRIGGERED[7] event */
+#define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
+#define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
+#define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for TRIGGERED[6] event */
+#define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
+#define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
+#define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable interrupt for TRIGGERED[5] event */
+#define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
+#define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
+#define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for TRIGGERED[4] event */
+#define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
+#define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
+#define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for TRIGGERED[3] event */
+#define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
+#define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
+#define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for TRIGGERED[2] event */
+#define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
+#define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
+#define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for TRIGGERED[1] event */
+#define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
+#define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
+#define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for TRIGGERED[0] event */
+#define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
+#define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
+#define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */
+
+
+/* Peripheral: FICR */
+/* Description: Factory Information Configuration Registers */
+
+/* Register: FICR_CODEPAGESIZE */
+/* Description: Code memory page size */
+
+/* Bits 31..0 : Code memory page size */
+#define FICR_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */
+#define FICR_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */
+
+/* Register: FICR_CODESIZE */
+/* Description: Code memory size */
+
+/* Bits 31..0 : Code memory size in number of pages */
+#define FICR_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */
+#define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */
+
+/* Register: FICR_DEVICEID */
+/* Description: Description collection[0]:  Device identifier */
+
+/* Bits 31..0 : 64 bit unique device identifier */
+#define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */
+#define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */
+
+/* Register: FICR_ER */
+/* Description: Description collection[0]:  Encryption root, word 0 */
+
+/* Bits 31..0 : Encryption root, word 0 */
+#define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */
+#define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */
+
+/* Register: FICR_IR */
+/* Description: Description collection[0]:  Identity Root, word 0 */
+
+/* Bits 31..0 : Identity Root, word 0 */
+#define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */
+#define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos) /*!< Bit mask of IR field. */
+
+/* Register: FICR_DEVICEADDRTYPE */
+/* Description: Device address type */
+
+/* Bit 0 : Device address type */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */
+
+/* Register: FICR_DEVICEADDR */
+/* Description: Description collection[0]:  Device address 0 */
+
+/* Bits 31..0 : 48 bit device address */
+#define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */
+#define FICR_DEVICEADDR_DEVICEADDR_Msk (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos) /*!< Bit mask of DEVICEADDR field. */
+
+/* Register: FICR_INFO_PART */
+/* Description: Part code */
+
+/* Bits 31..0 : Part code */
+#define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */
+#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */
+#define FICR_INFO_PART_PART_N52840 (0x52840UL) /*!< nRF52840 */
+#define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
+
+/* Register: FICR_INFO_VARIANT */
+/* Description: Part variant (hardware version and production configuration). */
+
+/* Bits 31..0 : Part variant (hardware version and production configuration). Encoded as ASCII. */
+#define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */
+#define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */
+#define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */
+#define FICR_INFO_VARIANT_VARIANT_AAAB (0x41414142UL) /*!< AAAB */
+#define FICR_INFO_VARIANT_VARIANT_AAB0 (0x41414230UL) /*!< AAB0 */
+#define FICR_INFO_VARIANT_VARIANT_AABA (0x41414241UL) /*!< AABA */
+#define FICR_INFO_VARIANT_VARIANT_AABB (0x41414242UL) /*!< AABB */
+#define FICR_INFO_VARIANT_VARIANT_ABBA (0x41424241UL) /*!< ABBA */
+#define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
+
+/* Register: FICR_INFO_PACKAGE */
+/* Description: Package option */
+
+/* Bits 31..0 : Package option */
+#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */
+#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */
+#define FICR_INFO_PACKAGE_PACKAGE_QI (0x2004UL) /*!< QIxx - 73-pin aQFN */
+#define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
+
+/* Register: FICR_INFO_RAM */
+/* Description: RAM variant */
+
+/* Bits 31..0 : RAM variant */
+#define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */
+#define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */
+#define FICR_INFO_RAM_RAM_K16 (0x10UL) /*!< 16 kByte RAM */
+#define FICR_INFO_RAM_RAM_K32 (0x20UL) /*!< 32 kByte RAM */
+#define FICR_INFO_RAM_RAM_K64 (0x40UL) /*!< 64 kByte RAM */
+#define FICR_INFO_RAM_RAM_K128 (0x80UL) /*!< 128 kByte RAM */
+#define FICR_INFO_RAM_RAM_K256 (0x100UL) /*!< 256 kByte RAM */
+#define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
+
+/* Register: FICR_INFO_FLASH */
+/* Description: Flash variant */
+
+/* Bits 31..0 : Flash variant */
+#define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */
+#define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */
+#define FICR_INFO_FLASH_FLASH_K128 (0x80UL) /*!< 128 kByte FLASH */
+#define FICR_INFO_FLASH_FLASH_K256 (0x100UL) /*!< 256 kByte FLASH */
+#define FICR_INFO_FLASH_FLASH_K512 (0x200UL) /*!< 512 kByte FLASH */
+#define FICR_INFO_FLASH_FLASH_K1024 (0x400UL) /*!< 1 MByte FLASH */
+#define FICR_INFO_FLASH_FLASH_K2048 (0x800UL) /*!< 2 MByte FLASH */
+#define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
+
+/* Register: FICR_TEMP_A0 */
+/* Description: Slope definition A0. */
+
+/* Bits 11..0 : A (slope definition) register. */
+#define FICR_TEMP_A0_A_Pos (0UL) /*!< Position of A field. */
+#define FICR_TEMP_A0_A_Msk (0xFFFUL << FICR_TEMP_A0_A_Pos) /*!< Bit mask of A field. */
+
+/* Register: FICR_TEMP_A1 */
+/* Description: Slope definition A1. */
+
+/* Bits 11..0 : A (slope definition) register. */
+#define FICR_TEMP_A1_A_Pos (0UL) /*!< Position of A field. */
+#define FICR_TEMP_A1_A_Msk (0xFFFUL << FICR_TEMP_A1_A_Pos) /*!< Bit mask of A field. */
+
+/* Register: FICR_TEMP_A2 */
+/* Description: Slope definition A2. */
+
+/* Bits 11..0 : A (slope definition) register. */
+#define FICR_TEMP_A2_A_Pos (0UL) /*!< Position of A field. */
+#define FICR_TEMP_A2_A_Msk (0xFFFUL << FICR_TEMP_A2_A_Pos) /*!< Bit mask of A field. */
+
+/* Register: FICR_TEMP_A3 */
+/* Description: Slope definition A3. */
+
+/* Bits 11..0 : A (slope definition) register. */
+#define FICR_TEMP_A3_A_Pos (0UL) /*!< Position of A field. */
+#define FICR_TEMP_A3_A_Msk (0xFFFUL << FICR_TEMP_A3_A_Pos) /*!< Bit mask of A field. */
+
+/* Register: FICR_TEMP_A4 */
+/* Description: Slope definition A4. */
+
+/* Bits 11..0 : A (slope definition) register. */
+#define FICR_TEMP_A4_A_Pos (0UL) /*!< Position of A field. */
+#define FICR_TEMP_A4_A_Msk (0xFFFUL << FICR_TEMP_A4_A_Pos) /*!< Bit mask of A field. */
+
+/* Register: FICR_TEMP_A5 */
+/* Description: Slope definition A5. */
+
+/* Bits 11..0 : A (slope definition) register. */
+#define FICR_TEMP_A5_A_Pos (0UL) /*!< Position of A field. */
+#define FICR_TEMP_A5_A_Msk (0xFFFUL << FICR_TEMP_A5_A_Pos) /*!< Bit mask of A field. */
+
+/* Register: FICR_TEMP_B0 */
+/* Description: y-intercept B0. */
+
+/* Bits 13..0 : B (y-intercept) */
+#define FICR_TEMP_B0_B_Pos (0UL) /*!< Position of B field. */
+#define FICR_TEMP_B0_B_Msk (0x3FFFUL << FICR_TEMP_B0_B_Pos) /*!< Bit mask of B field. */
+
+/* Register: FICR_TEMP_B1 */
+/* Description: y-intercept B1. */
+
+/* Bits 13..0 : B (y-intercept) */
+#define FICR_TEMP_B1_B_Pos (0UL) /*!< Position of B field. */
+#define FICR_TEMP_B1_B_Msk (0x3FFFUL << FICR_TEMP_B1_B_Pos) /*!< Bit mask of B field. */
+
+/* Register: FICR_TEMP_B2 */
+/* Description: y-intercept B2. */
+
+/* Bits 13..0 : B (y-intercept) */
+#define FICR_TEMP_B2_B_Pos (0UL) /*!< Position of B field. */
+#define FICR_TEMP_B2_B_Msk (0x3FFFUL << FICR_TEMP_B2_B_Pos) /*!< Bit mask of B field. */
+
+/* Register: FICR_TEMP_B3 */
+/* Description: y-intercept B3. */
+
+/* Bits 13..0 : B (y-intercept) */
+#define FICR_TEMP_B3_B_Pos (0UL) /*!< Position of B field. */
+#define FICR_TEMP_B3_B_Msk (0x3FFFUL << FICR_TEMP_B3_B_Pos) /*!< Bit mask of B field. */
+
+/* Register: FICR_TEMP_B4 */
+/* Description: y-intercept B4. */
+
+/* Bits 13..0 : B (y-intercept) */
+#define FICR_TEMP_B4_B_Pos (0UL) /*!< Position of B field. */
+#define FICR_TEMP_B4_B_Msk (0x3FFFUL << FICR_TEMP_B4_B_Pos) /*!< Bit mask of B field. */
+
+/* Register: FICR_TEMP_B5 */
+/* Description: y-intercept B5. */
+
+/* Bits 13..0 : B (y-intercept) */
+#define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */
+#define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */
+
+/* Register: FICR_TEMP_T0 */
+/* Description: Segment end T0. */
+
+/* Bits 7..0 : T (segment end)register. */
+#define FICR_TEMP_T0_T_Pos (0UL) /*!< Position of T field. */
+#define FICR_TEMP_T0_T_Msk (0xFFUL << FICR_TEMP_T0_T_Pos) /*!< Bit mask of T field. */
+
+/* Register: FICR_TEMP_T1 */
+/* Description: Segment end T1. */
+
+/* Bits 7..0 : T (segment end)register. */
+#define FICR_TEMP_T1_T_Pos (0UL) /*!< Position of T field. */
+#define FICR_TEMP_T1_T_Msk (0xFFUL << FICR_TEMP_T1_T_Pos) /*!< Bit mask of T field. */
+
+/* Register: FICR_TEMP_T2 */
+/* Description: Segment end T2. */
+
+/* Bits 7..0 : T (segment end)register. */
+#define FICR_TEMP_T2_T_Pos (0UL) /*!< Position of T field. */
+#define FICR_TEMP_T2_T_Msk (0xFFUL << FICR_TEMP_T2_T_Pos) /*!< Bit mask of T field. */
+
+/* Register: FICR_TEMP_T3 */
+/* Description: Segment end T3. */
+
+/* Bits 7..0 : T (segment end)register. */
+#define FICR_TEMP_T3_T_Pos (0UL) /*!< Position of T field. */
+#define FICR_TEMP_T3_T_Msk (0xFFUL << FICR_TEMP_T3_T_Pos) /*!< Bit mask of T field. */
+
+/* Register: FICR_TEMP_T4 */
+/* Description: Segment end T4. */
+
+/* Bits 7..0 : T (segment end)register. */
+#define FICR_TEMP_T4_T_Pos (0UL) /*!< Position of T field. */
+#define FICR_TEMP_T4_T_Msk (0xFFUL << FICR_TEMP_T4_T_Pos) /*!< Bit mask of T field. */
+
+/* Register: FICR_NFC_TAGHEADER0 */
+/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
+
+/* Bits 31..24 : Unique identifier byte 3 */
+#define FICR_NFC_TAGHEADER0_UD3_Pos (24UL) /*!< Position of UD3 field. */
+#define FICR_NFC_TAGHEADER0_UD3_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD3_Pos) /*!< Bit mask of UD3 field. */
+
+/* Bits 23..16 : Unique identifier byte 2 */
+#define FICR_NFC_TAGHEADER0_UD2_Pos (16UL) /*!< Position of UD2 field. */
+#define FICR_NFC_TAGHEADER0_UD2_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD2_Pos) /*!< Bit mask of UD2 field. */
+
+/* Bits 15..8 : Unique identifier byte 1 */
+#define FICR_NFC_TAGHEADER0_UD1_Pos (8UL) /*!< Position of UD1 field. */
+#define FICR_NFC_TAGHEADER0_UD1_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD1_Pos) /*!< Bit mask of UD1 field. */
+
+/* Bits 7..0 : Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F */
+#define FICR_NFC_TAGHEADER0_MFGID_Pos (0UL) /*!< Position of MFGID field. */
+#define FICR_NFC_TAGHEADER0_MFGID_Msk (0xFFUL << FICR_NFC_TAGHEADER0_MFGID_Pos) /*!< Bit mask of MFGID field. */
+
+/* Register: FICR_NFC_TAGHEADER1 */
+/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
+
+/* Bits 31..24 : Unique identifier byte 7 */
+#define FICR_NFC_TAGHEADER1_UD7_Pos (24UL) /*!< Position of UD7 field. */
+#define FICR_NFC_TAGHEADER1_UD7_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD7_Pos) /*!< Bit mask of UD7 field. */
+
+/* Bits 23..16 : Unique identifier byte 6 */
+#define FICR_NFC_TAGHEADER1_UD6_Pos (16UL) /*!< Position of UD6 field. */
+#define FICR_NFC_TAGHEADER1_UD6_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD6_Pos) /*!< Bit mask of UD6 field. */
+
+/* Bits 15..8 : Unique identifier byte 5 */
+#define FICR_NFC_TAGHEADER1_UD5_Pos (8UL) /*!< Position of UD5 field. */
+#define FICR_NFC_TAGHEADER1_UD5_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD5_Pos) /*!< Bit mask of UD5 field. */
+
+/* Bits 7..0 : Unique identifier byte 4 */
+#define FICR_NFC_TAGHEADER1_UD4_Pos (0UL) /*!< Position of UD4 field. */
+#define FICR_NFC_TAGHEADER1_UD4_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD4_Pos) /*!< Bit mask of UD4 field. */
+
+/* Register: FICR_NFC_TAGHEADER2 */
+/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
+
+/* Bits 31..24 : Unique identifier byte 11 */
+#define FICR_NFC_TAGHEADER2_UD11_Pos (24UL) /*!< Position of UD11 field. */
+#define FICR_NFC_TAGHEADER2_UD11_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD11_Pos) /*!< Bit mask of UD11 field. */
+
+/* Bits 23..16 : Unique identifier byte 10 */
+#define FICR_NFC_TAGHEADER2_UD10_Pos (16UL) /*!< Position of UD10 field. */
+#define FICR_NFC_TAGHEADER2_UD10_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD10_Pos) /*!< Bit mask of UD10 field. */
+
+/* Bits 15..8 : Unique identifier byte 9 */
+#define FICR_NFC_TAGHEADER2_UD9_Pos (8UL) /*!< Position of UD9 field. */
+#define FICR_NFC_TAGHEADER2_UD9_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD9_Pos) /*!< Bit mask of UD9 field. */
+
+/* Bits 7..0 : Unique identifier byte 8 */
+#define FICR_NFC_TAGHEADER2_UD8_Pos (0UL) /*!< Position of UD8 field. */
+#define FICR_NFC_TAGHEADER2_UD8_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD8_Pos) /*!< Bit mask of UD8 field. */
+
+/* Register: FICR_NFC_TAGHEADER3 */
+/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
+
+/* Bits 31..24 : Unique identifier byte 15 */
+#define FICR_NFC_TAGHEADER3_UD15_Pos (24UL) /*!< Position of UD15 field. */
+#define FICR_NFC_TAGHEADER3_UD15_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD15_Pos) /*!< Bit mask of UD15 field. */
+
+/* Bits 23..16 : Unique identifier byte 14 */
+#define FICR_NFC_TAGHEADER3_UD14_Pos (16UL) /*!< Position of UD14 field. */
+#define FICR_NFC_TAGHEADER3_UD14_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD14_Pos) /*!< Bit mask of UD14 field. */
+
+/* Bits 15..8 : Unique identifier byte 13 */
+#define FICR_NFC_TAGHEADER3_UD13_Pos (8UL) /*!< Position of UD13 field. */
+#define FICR_NFC_TAGHEADER3_UD13_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD13_Pos) /*!< Bit mask of UD13 field. */
+
+/* Bits 7..0 : Unique identifier byte 12 */
+#define FICR_NFC_TAGHEADER3_UD12_Pos (0UL) /*!< Position of UD12 field. */
+#define FICR_NFC_TAGHEADER3_UD12_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD12_Pos) /*!< Bit mask of UD12 field. */
+
+
+/* Peripheral: GPIOTE */
+/* Description: GPIO Tasks and Events */
+
+/* Register: GPIOTE_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 31 : Write '1' to Enable interrupt for PORT event */
+#define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
+#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
+#define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for IN[7] event */
+#define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */
+#define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */
+#define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for IN[6] event */
+#define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */
+#define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */
+#define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable interrupt for IN[5] event */
+#define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */
+#define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */
+#define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for IN[4] event */
+#define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */
+#define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */
+#define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for IN[3] event */
+#define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
+#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
+#define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for IN[2] event */
+#define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
+#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
+#define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for IN[1] event */
+#define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
+#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
+#define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for IN[0] event */
+#define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
+#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
+#define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */
+
+/* Register: GPIOTE_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 31 : Write '1' to Disable interrupt for PORT event */
+#define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
+#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
+#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for IN[7] event */
+#define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */
+#define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */
+#define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for IN[6] event */
+#define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */
+#define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */
+#define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable interrupt for IN[5] event */
+#define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */
+#define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */
+#define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for IN[4] event */
+#define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */
+#define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */
+#define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for IN[3] event */
+#define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
+#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
+#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for IN[2] event */
+#define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
+#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
+#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for IN[1] event */
+#define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
+#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
+#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for IN[0] event */
+#define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
+#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
+#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */
+
+/* Register: GPIOTE_CONFIG */
+/* Description: Description collection[0]:  Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */
+
+/* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */
+#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
+#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
+#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */
+#define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */
+
+/* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */
+#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
+#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
+#define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */
+#define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */
+#define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */
+#define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */
+
+/* Bits 14..13 : Port number */
+#define GPIOTE_CONFIG_PORT_Pos (13UL) /*!< Position of PORT field. */
+#define GPIOTE_CONFIG_PORT_Msk (0x3UL << GPIOTE_CONFIG_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 12..8 : GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event */
+#define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
+#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
+
+/* Bits 1..0 : Mode */
+#define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
+#define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */
+#define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */
+#define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */
+
+
+/* Peripheral: I2S */
+/* Description: Inter-IC Sound */
+
+/* Register: I2S_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 5 : Enable or disable interrupt for TXPTRUPD event */
+#define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
+#define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
+#define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */
+#define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for STOPPED event */
+#define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
+#define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for RXPTRUPD event */
+#define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
+#define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
+#define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */
+#define I2S_INTEN_RXPTRUPD_Enabled (1UL) /*!< Enable */
+
+/* Register: I2S_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 5 : Write '1' to Enable interrupt for TXPTRUPD event */
+#define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
+#define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
+#define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
+#define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
+#define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for STOPPED event */
+#define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
+#define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for RXPTRUPD event */
+#define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
+#define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
+#define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
+#define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
+#define I2S_INTENSET_RXPTRUPD_Set (1UL) /*!< Enable */
+
+/* Register: I2S_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 5 : Write '1' to Disable interrupt for TXPTRUPD event */
+#define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
+#define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
+#define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
+#define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
+#define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for STOPPED event */
+#define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
+#define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for RXPTRUPD event */
+#define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
+#define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
+#define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
+#define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
+#define I2S_INTENCLR_RXPTRUPD_Clear (1UL) /*!< Disable */
+
+/* Register: I2S_ENABLE */
+/* Description: Enable I2S module. */
+
+/* Bit 0 : Enable I2S module. */
+#define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define I2S_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define I2S_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
+
+/* Register: I2S_CONFIG_MODE */
+/* Description: I2S mode. */
+
+/* Bit 0 : I2S mode. */
+#define I2S_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define I2S_CONFIG_MODE_MODE_Master (0UL) /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. */
+#define I2S_CONFIG_MODE_MODE_Slave (1UL) /*!< Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx */
+
+/* Register: I2S_CONFIG_RXEN */
+/* Description: Reception (RX) enable. */
+
+/* Bit 0 : Reception (RX) enable. */
+#define I2S_CONFIG_RXEN_RXEN_Pos (0UL) /*!< Position of RXEN field. */
+#define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos) /*!< Bit mask of RXEN field. */
+#define I2S_CONFIG_RXEN_RXEN_Disabled (0UL) /*!< Reception disabled and now data will be written to the RXD.PTR address. */
+#define I2S_CONFIG_RXEN_RXEN_Enabled (1UL) /*!< Reception enabled. */
+
+/* Register: I2S_CONFIG_TXEN */
+/* Description: Transmission (TX) enable. */
+
+/* Bit 0 : Transmission (TX) enable. */
+#define I2S_CONFIG_TXEN_TXEN_Pos (0UL) /*!< Position of TXEN field. */
+#define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos) /*!< Bit mask of TXEN field. */
+#define I2S_CONFIG_TXEN_TXEN_Disabled (0UL) /*!< Transmission disabled and now data will be read from the RXD.TXD address. */
+#define I2S_CONFIG_TXEN_TXEN_Enabled (1UL) /*!< Transmission enabled. */
+
+/* Register: I2S_CONFIG_MCKEN */
+/* Description: Master clock generator enable. */
+
+/* Bit 0 : Master clock generator enable. */
+#define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL) /*!< Position of MCKEN field. */
+#define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos) /*!< Bit mask of MCKEN field. */
+#define I2S_CONFIG_MCKEN_MCKEN_Disabled (0UL) /*!< Master clock generator disabled and PSEL.MCK not connected(available as GPIO). */
+#define I2S_CONFIG_MCKEN_MCKEN_Enabled (1UL) /*!< Master clock generator running and MCK output on PSEL.MCK. */
+
+/* Register: I2S_CONFIG_MCKFREQ */
+/* Description: Master clock generator frequency. */
+
+/* Bits 31..0 : Master clock generator frequency. */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL) /*!< Position of MCKFREQ field. */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos) /*!< Bit mask of MCKFREQ field. */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL) /*!< 32 MHz / 125 = 0.256 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL) /*!< 32 MHz / 63 = 0.5079365 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL) /*!< 32 MHz / 42 = 0.7619048 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32 (0x08000000UL) /*!< 32 MHz / 32 = 1.0 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL) /*!< 32 MHz / 31 = 1.0322581 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL) /*!< 32 MHz / 30 = 1.0666667 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL) /*!< 32 MHz / 23 = 1.3913043 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL) /*!< 32 MHz / 16 = 2.0 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL) /*!< 32 MHz / 15 = 2.1333333 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6 (0x28000000UL) /*!< 32 MHz / 6 = 5.3333333 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5 (0x30000000UL) /*!< 32 MHz / 5 = 6.4 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4 (0x40000000UL) /*!< 32 MHz / 4 = 8.0 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3 (0x50000000UL) /*!< 32 MHz / 3 = 10.6666667 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2 (0x80000000UL) /*!< 32 MHz / 2 = 16.0 MHz */
+
+/* Register: I2S_CONFIG_RATIO */
+/* Description: MCK / LRCK ratio. */
+
+/* Bits 3..0 : MCK / LRCK ratio. */
+#define I2S_CONFIG_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */
+#define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */
+#define I2S_CONFIG_RATIO_RATIO_32X (0UL) /*!< LRCK = MCK / 32 */
+#define I2S_CONFIG_RATIO_RATIO_48X (1UL) /*!< LRCK = MCK / 48 */
+#define I2S_CONFIG_RATIO_RATIO_64X (2UL) /*!< LRCK = MCK / 64 */
+#define I2S_CONFIG_RATIO_RATIO_96X (3UL) /*!< LRCK = MCK / 96 */
+#define I2S_CONFIG_RATIO_RATIO_128X (4UL) /*!< LRCK = MCK / 128 */
+#define I2S_CONFIG_RATIO_RATIO_192X (5UL) /*!< LRCK = MCK / 192 */
+#define I2S_CONFIG_RATIO_RATIO_256X (6UL) /*!< LRCK = MCK / 256 */
+#define I2S_CONFIG_RATIO_RATIO_384X (7UL) /*!< LRCK = MCK / 384 */
+#define I2S_CONFIG_RATIO_RATIO_512X (8UL) /*!< LRCK = MCK / 512 */
+
+/* Register: I2S_CONFIG_SWIDTH */
+/* Description: Sample width. */
+
+/* Bits 1..0 : Sample width. */
+#define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL) /*!< Position of SWIDTH field. */
+#define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x3UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field. */
+#define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0UL) /*!< 8 bit. */
+#define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (1UL) /*!< 16 bit. */
+#define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (2UL) /*!< 24 bit. */
+
+/* Register: I2S_CONFIG_ALIGN */
+/* Description: Alignment of sample within a frame. */
+
+/* Bit 0 : Alignment of sample within a frame. */
+#define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL) /*!< Position of ALIGN field. */
+#define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field. */
+#define I2S_CONFIG_ALIGN_ALIGN_Left (0UL) /*!< Left-aligned. */
+#define I2S_CONFIG_ALIGN_ALIGN_Right (1UL) /*!< Right-aligned. */
+
+/* Register: I2S_CONFIG_FORMAT */
+/* Description: Frame format. */
+
+/* Bit 0 : Frame format. */
+#define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL) /*!< Position of FORMAT field. */
+#define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos) /*!< Bit mask of FORMAT field. */
+#define I2S_CONFIG_FORMAT_FORMAT_I2S (0UL) /*!< Original I2S format. */
+#define I2S_CONFIG_FORMAT_FORMAT_Aligned (1UL) /*!< Alternate (left- or right-aligned) format. */
+
+/* Register: I2S_CONFIG_CHANNELS */
+/* Description: Enable channels. */
+
+/* Bits 1..0 : Enable channels. */
+#define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL) /*!< Position of CHANNELS field. */
+#define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos) /*!< Bit mask of CHANNELS field. */
+#define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0UL) /*!< Stereo. */
+#define I2S_CONFIG_CHANNELS_CHANNELS_Left (1UL) /*!< Left only. */
+#define I2S_CONFIG_CHANNELS_CHANNELS_Right (2UL) /*!< Right only. */
+
+/* Register: I2S_RXD_PTR */
+/* Description: Receive buffer RAM start address. */
+
+/* Bits 31..0 : Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. */
+#define I2S_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: I2S_TXD_PTR */
+/* Description: Transmit buffer RAM start address. */
+
+/* Bits 31..0 : Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. */
+#define I2S_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: I2S_RXTXD_MAXCNT */
+/* Description: Size of RXD and TXD buffers. */
+
+/* Bits 13..0 : Size of RXD and TXD buffers in number of 32 bit words. */
+#define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: I2S_PSEL_MCK */
+/* Description: Pin select for MCK signal. */
+
+/* Bit 31 : Connection */
+#define I2S_PSEL_MCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define I2S_PSEL_MCK_CONNECT_Connected (0UL) /*!< Connect */
+#define I2S_PSEL_MCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 9..8 : Port number */
+#define I2S_PSEL_MCK_PORT_Pos (8UL) /*!< Position of PORT field. */
+#define I2S_PSEL_MCK_PORT_Msk (0x3UL << I2S_PSEL_MCK_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define I2S_PSEL_MCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: I2S_PSEL_SCK */
+/* Description: Pin select for SCK signal. */
+
+/* Bit 31 : Connection */
+#define I2S_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define I2S_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
+#define I2S_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 9..8 : Port number */
+#define I2S_PSEL_SCK_PORT_Pos (8UL) /*!< Position of PORT field. */
+#define I2S_PSEL_SCK_PORT_Msk (0x3UL << I2S_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define I2S_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: I2S_PSEL_LRCK */
+/* Description: Pin select for LRCK signal. */
+
+/* Bit 31 : Connection */
+#define I2S_PSEL_LRCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define I2S_PSEL_LRCK_CONNECT_Connected (0UL) /*!< Connect */
+#define I2S_PSEL_LRCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 9..8 : Port number */
+#define I2S_PSEL_LRCK_PORT_Pos (8UL) /*!< Position of PORT field. */
+#define I2S_PSEL_LRCK_PORT_Msk (0x3UL << I2S_PSEL_LRCK_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define I2S_PSEL_LRCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: I2S_PSEL_SDIN */
+/* Description: Pin select for SDIN signal. */
+
+/* Bit 31 : Connection */
+#define I2S_PSEL_SDIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define I2S_PSEL_SDIN_CONNECT_Connected (0UL) /*!< Connect */
+#define I2S_PSEL_SDIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 9..8 : Port number */
+#define I2S_PSEL_SDIN_PORT_Pos (8UL) /*!< Position of PORT field. */
+#define I2S_PSEL_SDIN_PORT_Msk (0x3UL << I2S_PSEL_SDIN_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define I2S_PSEL_SDIN_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: I2S_PSEL_SDOUT */
+/* Description: Pin select for SDOUT signal. */
+
+/* Bit 31 : Connection */
+#define I2S_PSEL_SDOUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define I2S_PSEL_SDOUT_CONNECT_Connected (0UL) /*!< Connect */
+#define I2S_PSEL_SDOUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 9..8 : Port number */
+#define I2S_PSEL_SDOUT_PORT_Pos (8UL) /*!< Position of PORT field. */
+#define I2S_PSEL_SDOUT_PORT_Msk (0x3UL << I2S_PSEL_SDOUT_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define I2S_PSEL_SDOUT_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos) /*!< Bit mask of PIN field. */
+
+
+/* Peripheral: LPCOMP */
+/* Description: Low Power Comparator */
+
+/* Register: LPCOMP_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 4 : Shortcut between CROSS event and STOP task */
+#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
+#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
+#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between UP event and STOP task */
+#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
+#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
+#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between DOWN event and STOP task */
+#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
+#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
+#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between READY event and STOP task */
+#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
+#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
+#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between READY event and SAMPLE task */
+#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
+#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
+#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
+#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: LPCOMP_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 3 : Write '1' to Enable interrupt for CROSS event */
+#define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
+#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
+#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for UP event */
+#define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
+#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
+#define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for DOWN event */
+#define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
+#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
+#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for READY event */
+#define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
+#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable */
+
+/* Register: LPCOMP_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 3 : Write '1' to Disable interrupt for CROSS event */
+#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
+#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
+#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for UP event */
+#define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
+#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
+#define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for DOWN event */
+#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
+#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
+#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for READY event */
+#define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
+#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
+
+/* Register: LPCOMP_RESULT */
+/* Description: Compare result */
+
+/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
+#define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
+#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
+#define LPCOMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the reference threshold (VIN+ &lt; VIN-). */
+#define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold (VIN+ &gt; VIN-). */
+
+/* Register: LPCOMP_ENABLE */
+/* Description: Enable LPCOMP */
+
+/* Bits 1..0 : Enable or disable LPCOMP */
+#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define LPCOMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define LPCOMP_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
+
+/* Register: LPCOMP_PSEL */
+/* Description: Input pin select */
+
+/* Bits 2..0 : Analog pin select */
+#define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
+#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
+#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */
+#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
+#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
+#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */
+#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */
+#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */
+#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */
+#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */
+
+/* Register: LPCOMP_REFSEL */
+/* Description: Reference select */
+
+/* Bits 3..0 : Reference select */
+#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
+#define LPCOMP_REFSEL_REFSEL_Msk (0xFUL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
+#define LPCOMP_REFSEL_REFSEL_Ref1_8Vdd (0UL) /*!< VDD * 1/8 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref2_8Vdd (1UL) /*!< VDD * 2/8 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref3_8Vdd (2UL) /*!< VDD * 3/8 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref4_8Vdd (3UL) /*!< VDD * 4/8 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref5_8Vdd (4UL) /*!< VDD * 5/8 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref6_8Vdd (5UL) /*!< VDD * 6/8 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref7_8Vdd (6UL) /*!< VDD * 7/8 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< External analog reference selected */
+#define LPCOMP_REFSEL_REFSEL_Ref1_16Vdd (8UL) /*!< VDD * 1/16 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref3_16Vdd (9UL) /*!< VDD * 3/16 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref5_16Vdd (10UL) /*!< VDD * 5/16 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref7_16Vdd (11UL) /*!< VDD * 7/16 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref9_16Vdd (12UL) /*!< VDD * 9/16 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref11_16Vdd (13UL) /*!< VDD * 11/16 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref13_16Vdd (14UL) /*!< VDD * 13/16 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref15_16Vdd (15UL) /*!< VDD * 15/16 selected as reference */
+
+/* Register: LPCOMP_EXTREFSEL */
+/* Description: External reference select */
+
+/* Bit 0 : External analog reference select */
+#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
+#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
+#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */
+#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */
+
+/* Register: LPCOMP_ANADETECT */
+/* Description: Analog detect configuration */
+
+/* Bits 1..0 : Analog detect configuration */
+#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */
+#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */
+#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETECT on crossing, both upward crossing and downward crossing */
+#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETECT on upward crossing only */
+#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETECT on downward crossing only */
+
+/* Register: LPCOMP_HYST */
+/* Description: Comparator hysteresis enable */
+
+/* Bit 0 : Comparator hysteresis enable */
+#define LPCOMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
+#define LPCOMP_HYST_HYST_Msk (0x1UL << LPCOMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
+#define LPCOMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */
+#define LPCOMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis disabled (typ. 50 mV) */
+
+
+/* Peripheral: MWU */
+/* Description: Memory Watch Unit */
+
+/* Register: MWU_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 27 : Enable or disable interrupt for PREGION[1].RA event */
+#define MWU_INTEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
+#define MWU_INTEN_PREGION1RA_Msk (0x1UL << MWU_INTEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
+#define MWU_INTEN_PREGION1RA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_PREGION1RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 26 : Enable or disable interrupt for PREGION[1].WA event */
+#define MWU_INTEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
+#define MWU_INTEN_PREGION1WA_Msk (0x1UL << MWU_INTEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
+#define MWU_INTEN_PREGION1WA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_PREGION1WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 25 : Enable or disable interrupt for PREGION[0].RA event */
+#define MWU_INTEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
+#define MWU_INTEN_PREGION0RA_Msk (0x1UL << MWU_INTEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
+#define MWU_INTEN_PREGION0RA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_PREGION0RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 24 : Enable or disable interrupt for PREGION[0].WA event */
+#define MWU_INTEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
+#define MWU_INTEN_PREGION0WA_Msk (0x1UL << MWU_INTEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
+#define MWU_INTEN_PREGION0WA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_PREGION0WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable interrupt for REGION[3].RA event */
+#define MWU_INTEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
+#define MWU_INTEN_REGION3RA_Msk (0x1UL << MWU_INTEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
+#define MWU_INTEN_REGION3RA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION3RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable interrupt for REGION[3].WA event */
+#define MWU_INTEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
+#define MWU_INTEN_REGION3WA_Msk (0x1UL << MWU_INTEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
+#define MWU_INTEN_REGION3WA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION3WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable interrupt for REGION[2].RA event */
+#define MWU_INTEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
+#define MWU_INTEN_REGION2RA_Msk (0x1UL << MWU_INTEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
+#define MWU_INTEN_REGION2RA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION2RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for REGION[2].WA event */
+#define MWU_INTEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
+#define MWU_INTEN_REGION2WA_Msk (0x1UL << MWU_INTEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
+#define MWU_INTEN_REGION2WA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION2WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable interrupt for REGION[1].RA event */
+#define MWU_INTEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
+#define MWU_INTEN_REGION1RA_Msk (0x1UL << MWU_INTEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
+#define MWU_INTEN_REGION1RA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION1RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for REGION[1].WA event */
+#define MWU_INTEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
+#define MWU_INTEN_REGION1WA_Msk (0x1UL << MWU_INTEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
+#define MWU_INTEN_REGION1WA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION1WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for REGION[0].RA event */
+#define MWU_INTEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
+#define MWU_INTEN_REGION0RA_Msk (0x1UL << MWU_INTEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
+#define MWU_INTEN_REGION0RA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION0RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for REGION[0].WA event */
+#define MWU_INTEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
+#define MWU_INTEN_REGION0WA_Msk (0x1UL << MWU_INTEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
+#define MWU_INTEN_REGION0WA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION0WA_Enabled (1UL) /*!< Enable */
+
+/* Register: MWU_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 27 : Write '1' to Enable interrupt for PREGION[1].RA event */
+#define MWU_INTENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
+#define MWU_INTENSET_PREGION1RA_Msk (0x1UL << MWU_INTENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
+#define MWU_INTENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_PREGION1RA_Set (1UL) /*!< Enable */
+
+/* Bit 26 : Write '1' to Enable interrupt for PREGION[1].WA event */
+#define MWU_INTENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
+#define MWU_INTENSET_PREGION1WA_Msk (0x1UL << MWU_INTENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
+#define MWU_INTENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_PREGION1WA_Set (1UL) /*!< Enable */
+
+/* Bit 25 : Write '1' to Enable interrupt for PREGION[0].RA event */
+#define MWU_INTENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
+#define MWU_INTENSET_PREGION0RA_Msk (0x1UL << MWU_INTENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
+#define MWU_INTENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_PREGION0RA_Set (1UL) /*!< Enable */
+
+/* Bit 24 : Write '1' to Enable interrupt for PREGION[0].WA event */
+#define MWU_INTENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
+#define MWU_INTENSET_PREGION0WA_Msk (0x1UL << MWU_INTENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
+#define MWU_INTENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_PREGION0WA_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for REGION[3].RA event */
+#define MWU_INTENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
+#define MWU_INTENSET_REGION3RA_Msk (0x1UL << MWU_INTENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
+#define MWU_INTENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION3RA_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for REGION[3].WA event */
+#define MWU_INTENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
+#define MWU_INTENSET_REGION3WA_Msk (0x1UL << MWU_INTENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
+#define MWU_INTENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION3WA_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable interrupt for REGION[2].RA event */
+#define MWU_INTENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
+#define MWU_INTENSET_REGION2RA_Msk (0x1UL << MWU_INTENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
+#define MWU_INTENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION2RA_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for REGION[2].WA event */
+#define MWU_INTENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
+#define MWU_INTENSET_REGION2WA_Msk (0x1UL << MWU_INTENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
+#define MWU_INTENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION2WA_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for REGION[1].RA event */
+#define MWU_INTENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
+#define MWU_INTENSET_REGION1RA_Msk (0x1UL << MWU_INTENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
+#define MWU_INTENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION1RA_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for REGION[1].WA event */
+#define MWU_INTENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
+#define MWU_INTENSET_REGION1WA_Msk (0x1UL << MWU_INTENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
+#define MWU_INTENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION1WA_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for REGION[0].RA event */
+#define MWU_INTENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
+#define MWU_INTENSET_REGION0RA_Msk (0x1UL << MWU_INTENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
+#define MWU_INTENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION0RA_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for REGION[0].WA event */
+#define MWU_INTENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
+#define MWU_INTENSET_REGION0WA_Msk (0x1UL << MWU_INTENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
+#define MWU_INTENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION0WA_Set (1UL) /*!< Enable */
+
+/* Register: MWU_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 27 : Write '1' to Disable interrupt for PREGION[1].RA event */
+#define MWU_INTENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
+#define MWU_INTENCLR_PREGION1RA_Msk (0x1UL << MWU_INTENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
+#define MWU_INTENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
+
+/* Bit 26 : Write '1' to Disable interrupt for PREGION[1].WA event */
+#define MWU_INTENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
+#define MWU_INTENCLR_PREGION1WA_Msk (0x1UL << MWU_INTENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
+#define MWU_INTENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
+
+/* Bit 25 : Write '1' to Disable interrupt for PREGION[0].RA event */
+#define MWU_INTENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
+#define MWU_INTENCLR_PREGION0RA_Msk (0x1UL << MWU_INTENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
+#define MWU_INTENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
+
+/* Bit 24 : Write '1' to Disable interrupt for PREGION[0].WA event */
+#define MWU_INTENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
+#define MWU_INTENCLR_PREGION0WA_Msk (0x1UL << MWU_INTENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
+#define MWU_INTENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for REGION[3].RA event */
+#define MWU_INTENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
+#define MWU_INTENCLR_REGION3RA_Msk (0x1UL << MWU_INTENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
+#define MWU_INTENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION3RA_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for REGION[3].WA event */
+#define MWU_INTENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
+#define MWU_INTENCLR_REGION3WA_Msk (0x1UL << MWU_INTENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
+#define MWU_INTENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION3WA_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable interrupt for REGION[2].RA event */
+#define MWU_INTENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
+#define MWU_INTENCLR_REGION2RA_Msk (0x1UL << MWU_INTENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
+#define MWU_INTENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION2RA_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for REGION[2].WA event */
+#define MWU_INTENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
+#define MWU_INTENCLR_REGION2WA_Msk (0x1UL << MWU_INTENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
+#define MWU_INTENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION2WA_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for REGION[1].RA event */
+#define MWU_INTENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
+#define MWU_INTENCLR_REGION1RA_Msk (0x1UL << MWU_INTENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
+#define MWU_INTENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION1RA_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for REGION[1].WA event */
+#define MWU_INTENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
+#define MWU_INTENCLR_REGION1WA_Msk (0x1UL << MWU_INTENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
+#define MWU_INTENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION1WA_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for REGION[0].RA event */
+#define MWU_INTENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
+#define MWU_INTENCLR_REGION0RA_Msk (0x1UL << MWU_INTENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
+#define MWU_INTENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION0RA_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for REGION[0].WA event */
+#define MWU_INTENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
+#define MWU_INTENCLR_REGION0WA_Msk (0x1UL << MWU_INTENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
+#define MWU_INTENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION0WA_Clear (1UL) /*!< Disable */
+
+/* Register: MWU_NMIEN */
+/* Description: Enable or disable non-maskable interrupt */
+
+/* Bit 27 : Enable or disable non-maskable interrupt for PREGION[1].RA event */
+#define MWU_NMIEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
+#define MWU_NMIEN_PREGION1RA_Msk (0x1UL << MWU_NMIEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
+#define MWU_NMIEN_PREGION1RA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_PREGION1RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 26 : Enable or disable non-maskable interrupt for PREGION[1].WA event */
+#define MWU_NMIEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
+#define MWU_NMIEN_PREGION1WA_Msk (0x1UL << MWU_NMIEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
+#define MWU_NMIEN_PREGION1WA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_PREGION1WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 25 : Enable or disable non-maskable interrupt for PREGION[0].RA event */
+#define MWU_NMIEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
+#define MWU_NMIEN_PREGION0RA_Msk (0x1UL << MWU_NMIEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
+#define MWU_NMIEN_PREGION0RA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_PREGION0RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 24 : Enable or disable non-maskable interrupt for PREGION[0].WA event */
+#define MWU_NMIEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
+#define MWU_NMIEN_PREGION0WA_Msk (0x1UL << MWU_NMIEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
+#define MWU_NMIEN_PREGION0WA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_PREGION0WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable non-maskable interrupt for REGION[3].RA event */
+#define MWU_NMIEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
+#define MWU_NMIEN_REGION3RA_Msk (0x1UL << MWU_NMIEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
+#define MWU_NMIEN_REGION3RA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION3RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable non-maskable interrupt for REGION[3].WA event */
+#define MWU_NMIEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
+#define MWU_NMIEN_REGION3WA_Msk (0x1UL << MWU_NMIEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
+#define MWU_NMIEN_REGION3WA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION3WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable non-maskable interrupt for REGION[2].RA event */
+#define MWU_NMIEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
+#define MWU_NMIEN_REGION2RA_Msk (0x1UL << MWU_NMIEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
+#define MWU_NMIEN_REGION2RA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION2RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable non-maskable interrupt for REGION[2].WA event */
+#define MWU_NMIEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
+#define MWU_NMIEN_REGION2WA_Msk (0x1UL << MWU_NMIEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
+#define MWU_NMIEN_REGION2WA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION2WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable non-maskable interrupt for REGION[1].RA event */
+#define MWU_NMIEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
+#define MWU_NMIEN_REGION1RA_Msk (0x1UL << MWU_NMIEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
+#define MWU_NMIEN_REGION1RA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION1RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable non-maskable interrupt for REGION[1].WA event */
+#define MWU_NMIEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
+#define MWU_NMIEN_REGION1WA_Msk (0x1UL << MWU_NMIEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
+#define MWU_NMIEN_REGION1WA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION1WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable non-maskable interrupt for REGION[0].RA event */
+#define MWU_NMIEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
+#define MWU_NMIEN_REGION0RA_Msk (0x1UL << MWU_NMIEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
+#define MWU_NMIEN_REGION0RA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION0RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable non-maskable interrupt for REGION[0].WA event */
+#define MWU_NMIEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
+#define MWU_NMIEN_REGION0WA_Msk (0x1UL << MWU_NMIEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
+#define MWU_NMIEN_REGION0WA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION0WA_Enabled (1UL) /*!< Enable */
+
+/* Register: MWU_NMIENSET */
+/* Description: Enable non-maskable interrupt */
+
+/* Bit 27 : Write '1' to Enable non-maskable interrupt for PREGION[1].RA event */
+#define MWU_NMIENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
+#define MWU_NMIENSET_PREGION1RA_Msk (0x1UL << MWU_NMIENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
+#define MWU_NMIENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_PREGION1RA_Set (1UL) /*!< Enable */
+
+/* Bit 26 : Write '1' to Enable non-maskable interrupt for PREGION[1].WA event */
+#define MWU_NMIENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
+#define MWU_NMIENSET_PREGION1WA_Msk (0x1UL << MWU_NMIENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
+#define MWU_NMIENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_PREGION1WA_Set (1UL) /*!< Enable */
+
+/* Bit 25 : Write '1' to Enable non-maskable interrupt for PREGION[0].RA event */
+#define MWU_NMIENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
+#define MWU_NMIENSET_PREGION0RA_Msk (0x1UL << MWU_NMIENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
+#define MWU_NMIENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_PREGION0RA_Set (1UL) /*!< Enable */
+
+/* Bit 24 : Write '1' to Enable non-maskable interrupt for PREGION[0].WA event */
+#define MWU_NMIENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
+#define MWU_NMIENSET_PREGION0WA_Msk (0x1UL << MWU_NMIENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
+#define MWU_NMIENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_PREGION0WA_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable non-maskable interrupt for REGION[3].RA event */
+#define MWU_NMIENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
+#define MWU_NMIENSET_REGION3RA_Msk (0x1UL << MWU_NMIENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
+#define MWU_NMIENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION3RA_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable non-maskable interrupt for REGION[3].WA event */
+#define MWU_NMIENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
+#define MWU_NMIENSET_REGION3WA_Msk (0x1UL << MWU_NMIENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
+#define MWU_NMIENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION3WA_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable non-maskable interrupt for REGION[2].RA event */
+#define MWU_NMIENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
+#define MWU_NMIENSET_REGION2RA_Msk (0x1UL << MWU_NMIENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
+#define MWU_NMIENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION2RA_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable non-maskable interrupt for REGION[2].WA event */
+#define MWU_NMIENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
+#define MWU_NMIENSET_REGION2WA_Msk (0x1UL << MWU_NMIENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
+#define MWU_NMIENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION2WA_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable non-maskable interrupt for REGION[1].RA event */
+#define MWU_NMIENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
+#define MWU_NMIENSET_REGION1RA_Msk (0x1UL << MWU_NMIENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
+#define MWU_NMIENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION1RA_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable non-maskable interrupt for REGION[1].WA event */
+#define MWU_NMIENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
+#define MWU_NMIENSET_REGION1WA_Msk (0x1UL << MWU_NMIENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
+#define MWU_NMIENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION1WA_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable non-maskable interrupt for REGION[0].RA event */
+#define MWU_NMIENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
+#define MWU_NMIENSET_REGION0RA_Msk (0x1UL << MWU_NMIENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
+#define MWU_NMIENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION0RA_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable non-maskable interrupt for REGION[0].WA event */
+#define MWU_NMIENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
+#define MWU_NMIENSET_REGION0WA_Msk (0x1UL << MWU_NMIENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
+#define MWU_NMIENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION0WA_Set (1UL) /*!< Enable */
+
+/* Register: MWU_NMIENCLR */
+/* Description: Disable non-maskable interrupt */
+
+/* Bit 27 : Write '1' to Disable non-maskable interrupt for PREGION[1].RA event */
+#define MWU_NMIENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
+#define MWU_NMIENCLR_PREGION1RA_Msk (0x1UL << MWU_NMIENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
+#define MWU_NMIENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
+
+/* Bit 26 : Write '1' to Disable non-maskable interrupt for PREGION[1].WA event */
+#define MWU_NMIENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
+#define MWU_NMIENCLR_PREGION1WA_Msk (0x1UL << MWU_NMIENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
+#define MWU_NMIENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
+
+/* Bit 25 : Write '1' to Disable non-maskable interrupt for PREGION[0].RA event */
+#define MWU_NMIENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
+#define MWU_NMIENCLR_PREGION0RA_Msk (0x1UL << MWU_NMIENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
+#define MWU_NMIENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
+
+/* Bit 24 : Write '1' to Disable non-maskable interrupt for PREGION[0].WA event */
+#define MWU_NMIENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
+#define MWU_NMIENCLR_PREGION0WA_Msk (0x1UL << MWU_NMIENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
+#define MWU_NMIENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable non-maskable interrupt for REGION[3].RA event */
+#define MWU_NMIENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
+#define MWU_NMIENCLR_REGION3RA_Msk (0x1UL << MWU_NMIENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
+#define MWU_NMIENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION3RA_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable non-maskable interrupt for REGION[3].WA event */
+#define MWU_NMIENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
+#define MWU_NMIENCLR_REGION3WA_Msk (0x1UL << MWU_NMIENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
+#define MWU_NMIENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION3WA_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable non-maskable interrupt for REGION[2].RA event */
+#define MWU_NMIENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
+#define MWU_NMIENCLR_REGION2RA_Msk (0x1UL << MWU_NMIENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
+#define MWU_NMIENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION2RA_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable non-maskable interrupt for REGION[2].WA event */
+#define MWU_NMIENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
+#define MWU_NMIENCLR_REGION2WA_Msk (0x1UL << MWU_NMIENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
+#define MWU_NMIENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION2WA_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable non-maskable interrupt for REGION[1].RA event */
+#define MWU_NMIENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
+#define MWU_NMIENCLR_REGION1RA_Msk (0x1UL << MWU_NMIENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
+#define MWU_NMIENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION1RA_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable non-maskable interrupt for REGION[1].WA event */
+#define MWU_NMIENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
+#define MWU_NMIENCLR_REGION1WA_Msk (0x1UL << MWU_NMIENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
+#define MWU_NMIENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION1WA_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable non-maskable interrupt for REGION[0].RA event */
+#define MWU_NMIENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
+#define MWU_NMIENCLR_REGION0RA_Msk (0x1UL << MWU_NMIENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
+#define MWU_NMIENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION0RA_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable non-maskable interrupt for REGION[0].WA event */
+#define MWU_NMIENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
+#define MWU_NMIENCLR_REGION0WA_Msk (0x1UL << MWU_NMIENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
+#define MWU_NMIENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION0WA_Clear (1UL) /*!< Disable */
+
+/* Register: MWU_PERREGION_SUBSTATWA */
+/* Description: Description cluster[0]:  Source of event/interrupt in region 0, write access detected while corresponding subregion was enabled for watching */
+
+/* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR31_Pos (31UL) /*!< Position of SR31 field. */
+#define MWU_PERREGION_SUBSTATWA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR31_Pos) /*!< Bit mask of SR31 field. */
+#define MWU_PERREGION_SUBSTATWA_SR31_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR31_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR30_Pos (30UL) /*!< Position of SR30 field. */
+#define MWU_PERREGION_SUBSTATWA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR30_Pos) /*!< Bit mask of SR30 field. */
+#define MWU_PERREGION_SUBSTATWA_SR30_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR30_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR29_Pos (29UL) /*!< Position of SR29 field. */
+#define MWU_PERREGION_SUBSTATWA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR29_Pos) /*!< Bit mask of SR29 field. */
+#define MWU_PERREGION_SUBSTATWA_SR29_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR29_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR28_Pos (28UL) /*!< Position of SR28 field. */
+#define MWU_PERREGION_SUBSTATWA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR28_Pos) /*!< Bit mask of SR28 field. */
+#define MWU_PERREGION_SUBSTATWA_SR28_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR28_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR27_Pos (27UL) /*!< Position of SR27 field. */
+#define MWU_PERREGION_SUBSTATWA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR27_Pos) /*!< Bit mask of SR27 field. */
+#define MWU_PERREGION_SUBSTATWA_SR27_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR27_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR26_Pos (26UL) /*!< Position of SR26 field. */
+#define MWU_PERREGION_SUBSTATWA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR26_Pos) /*!< Bit mask of SR26 field. */
+#define MWU_PERREGION_SUBSTATWA_SR26_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR26_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR25_Pos (25UL) /*!< Position of SR25 field. */
+#define MWU_PERREGION_SUBSTATWA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR25_Pos) /*!< Bit mask of SR25 field. */
+#define MWU_PERREGION_SUBSTATWA_SR25_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR25_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR24_Pos (24UL) /*!< Position of SR24 field. */
+#define MWU_PERREGION_SUBSTATWA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR24_Pos) /*!< Bit mask of SR24 field. */
+#define MWU_PERREGION_SUBSTATWA_SR24_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR24_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR23_Pos (23UL) /*!< Position of SR23 field. */
+#define MWU_PERREGION_SUBSTATWA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR23_Pos) /*!< Bit mask of SR23 field. */
+#define MWU_PERREGION_SUBSTATWA_SR23_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR23_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR22_Pos (22UL) /*!< Position of SR22 field. */
+#define MWU_PERREGION_SUBSTATWA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR22_Pos) /*!< Bit mask of SR22 field. */
+#define MWU_PERREGION_SUBSTATWA_SR22_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR22_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR21_Pos (21UL) /*!< Position of SR21 field. */
+#define MWU_PERREGION_SUBSTATWA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR21_Pos) /*!< Bit mask of SR21 field. */
+#define MWU_PERREGION_SUBSTATWA_SR21_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR21_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR20_Pos (20UL) /*!< Position of SR20 field. */
+#define MWU_PERREGION_SUBSTATWA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR20_Pos) /*!< Bit mask of SR20 field. */
+#define MWU_PERREGION_SUBSTATWA_SR20_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR20_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR19_Pos (19UL) /*!< Position of SR19 field. */
+#define MWU_PERREGION_SUBSTATWA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR19_Pos) /*!< Bit mask of SR19 field. */
+#define MWU_PERREGION_SUBSTATWA_SR19_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR19_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR18_Pos (18UL) /*!< Position of SR18 field. */
+#define MWU_PERREGION_SUBSTATWA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR18_Pos) /*!< Bit mask of SR18 field. */
+#define MWU_PERREGION_SUBSTATWA_SR18_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR18_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR17_Pos (17UL) /*!< Position of SR17 field. */
+#define MWU_PERREGION_SUBSTATWA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR17_Pos) /*!< Bit mask of SR17 field. */
+#define MWU_PERREGION_SUBSTATWA_SR17_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR17_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR16_Pos (16UL) /*!< Position of SR16 field. */
+#define MWU_PERREGION_SUBSTATWA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR16_Pos) /*!< Bit mask of SR16 field. */
+#define MWU_PERREGION_SUBSTATWA_SR16_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR16_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR15_Pos (15UL) /*!< Position of SR15 field. */
+#define MWU_PERREGION_SUBSTATWA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR15_Pos) /*!< Bit mask of SR15 field. */
+#define MWU_PERREGION_SUBSTATWA_SR15_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR15_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR14_Pos (14UL) /*!< Position of SR14 field. */
+#define MWU_PERREGION_SUBSTATWA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR14_Pos) /*!< Bit mask of SR14 field. */
+#define MWU_PERREGION_SUBSTATWA_SR14_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR14_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR13_Pos (13UL) /*!< Position of SR13 field. */
+#define MWU_PERREGION_SUBSTATWA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR13_Pos) /*!< Bit mask of SR13 field. */
+#define MWU_PERREGION_SUBSTATWA_SR13_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR13_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR12_Pos (12UL) /*!< Position of SR12 field. */
+#define MWU_PERREGION_SUBSTATWA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR12_Pos) /*!< Bit mask of SR12 field. */
+#define MWU_PERREGION_SUBSTATWA_SR12_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR12_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR11_Pos (11UL) /*!< Position of SR11 field. */
+#define MWU_PERREGION_SUBSTATWA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR11_Pos) /*!< Bit mask of SR11 field. */
+#define MWU_PERREGION_SUBSTATWA_SR11_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR11_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR10_Pos (10UL) /*!< Position of SR10 field. */
+#define MWU_PERREGION_SUBSTATWA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR10_Pos) /*!< Bit mask of SR10 field. */
+#define MWU_PERREGION_SUBSTATWA_SR10_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR10_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR9_Pos (9UL) /*!< Position of SR9 field. */
+#define MWU_PERREGION_SUBSTATWA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR9_Pos) /*!< Bit mask of SR9 field. */
+#define MWU_PERREGION_SUBSTATWA_SR9_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR9_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR8_Pos (8UL) /*!< Position of SR8 field. */
+#define MWU_PERREGION_SUBSTATWA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR8_Pos) /*!< Bit mask of SR8 field. */
+#define MWU_PERREGION_SUBSTATWA_SR8_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR8_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR7_Pos (7UL) /*!< Position of SR7 field. */
+#define MWU_PERREGION_SUBSTATWA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR7_Pos) /*!< Bit mask of SR7 field. */
+#define MWU_PERREGION_SUBSTATWA_SR7_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR7_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR6_Pos (6UL) /*!< Position of SR6 field. */
+#define MWU_PERREGION_SUBSTATWA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR6_Pos) /*!< Bit mask of SR6 field. */
+#define MWU_PERREGION_SUBSTATWA_SR6_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR6_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR5_Pos (5UL) /*!< Position of SR5 field. */
+#define MWU_PERREGION_SUBSTATWA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR5_Pos) /*!< Bit mask of SR5 field. */
+#define MWU_PERREGION_SUBSTATWA_SR5_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR5_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR4_Pos (4UL) /*!< Position of SR4 field. */
+#define MWU_PERREGION_SUBSTATWA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR4_Pos) /*!< Bit mask of SR4 field. */
+#define MWU_PERREGION_SUBSTATWA_SR4_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR4_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR3_Pos (3UL) /*!< Position of SR3 field. */
+#define MWU_PERREGION_SUBSTATWA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR3_Pos) /*!< Bit mask of SR3 field. */
+#define MWU_PERREGION_SUBSTATWA_SR3_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR3_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR2_Pos (2UL) /*!< Position of SR2 field. */
+#define MWU_PERREGION_SUBSTATWA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR2_Pos) /*!< Bit mask of SR2 field. */
+#define MWU_PERREGION_SUBSTATWA_SR2_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR2_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR1_Pos (1UL) /*!< Position of SR1 field. */
+#define MWU_PERREGION_SUBSTATWA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR1_Pos) /*!< Bit mask of SR1 field. */
+#define MWU_PERREGION_SUBSTATWA_SR1_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR1_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR0_Pos (0UL) /*!< Position of SR0 field. */
+#define MWU_PERREGION_SUBSTATWA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR0_Pos) /*!< Bit mask of SR0 field. */
+#define MWU_PERREGION_SUBSTATWA_SR0_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR0_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Register: MWU_PERREGION_SUBSTATRA */
+/* Description: Description cluster[0]:  Source of event/interrupt in region 0, read access detected while corresponding subregion was enabled for watching */
+
+/* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR31_Pos (31UL) /*!< Position of SR31 field. */
+#define MWU_PERREGION_SUBSTATRA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR31_Pos) /*!< Bit mask of SR31 field. */
+#define MWU_PERREGION_SUBSTATRA_SR31_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR31_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR30_Pos (30UL) /*!< Position of SR30 field. */
+#define MWU_PERREGION_SUBSTATRA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR30_Pos) /*!< Bit mask of SR30 field. */
+#define MWU_PERREGION_SUBSTATRA_SR30_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR30_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR29_Pos (29UL) /*!< Position of SR29 field. */
+#define MWU_PERREGION_SUBSTATRA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR29_Pos) /*!< Bit mask of SR29 field. */
+#define MWU_PERREGION_SUBSTATRA_SR29_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR29_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR28_Pos (28UL) /*!< Position of SR28 field. */
+#define MWU_PERREGION_SUBSTATRA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR28_Pos) /*!< Bit mask of SR28 field. */
+#define MWU_PERREGION_SUBSTATRA_SR28_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR28_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR27_Pos (27UL) /*!< Position of SR27 field. */
+#define MWU_PERREGION_SUBSTATRA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR27_Pos) /*!< Bit mask of SR27 field. */
+#define MWU_PERREGION_SUBSTATRA_SR27_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR27_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR26_Pos (26UL) /*!< Position of SR26 field. */
+#define MWU_PERREGION_SUBSTATRA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR26_Pos) /*!< Bit mask of SR26 field. */
+#define MWU_PERREGION_SUBSTATRA_SR26_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR26_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR25_Pos (25UL) /*!< Position of SR25 field. */
+#define MWU_PERREGION_SUBSTATRA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR25_Pos) /*!< Bit mask of SR25 field. */
+#define MWU_PERREGION_SUBSTATRA_SR25_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR25_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR24_Pos (24UL) /*!< Position of SR24 field. */
+#define MWU_PERREGION_SUBSTATRA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR24_Pos) /*!< Bit mask of SR24 field. */
+#define MWU_PERREGION_SUBSTATRA_SR24_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR24_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR23_Pos (23UL) /*!< Position of SR23 field. */
+#define MWU_PERREGION_SUBSTATRA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR23_Pos) /*!< Bit mask of SR23 field. */
+#define MWU_PERREGION_SUBSTATRA_SR23_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR23_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR22_Pos (22UL) /*!< Position of SR22 field. */
+#define MWU_PERREGION_SUBSTATRA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR22_Pos) /*!< Bit mask of SR22 field. */
+#define MWU_PERREGION_SUBSTATRA_SR22_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR22_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR21_Pos (21UL) /*!< Position of SR21 field. */
+#define MWU_PERREGION_SUBSTATRA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR21_Pos) /*!< Bit mask of SR21 field. */
+#define MWU_PERREGION_SUBSTATRA_SR21_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR21_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR20_Pos (20UL) /*!< Position of SR20 field. */
+#define MWU_PERREGION_SUBSTATRA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR20_Pos) /*!< Bit mask of SR20 field. */
+#define MWU_PERREGION_SUBSTATRA_SR20_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR20_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR19_Pos (19UL) /*!< Position of SR19 field. */
+#define MWU_PERREGION_SUBSTATRA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR19_Pos) /*!< Bit mask of SR19 field. */
+#define MWU_PERREGION_SUBSTATRA_SR19_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR19_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR18_Pos (18UL) /*!< Position of SR18 field. */
+#define MWU_PERREGION_SUBSTATRA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR18_Pos) /*!< Bit mask of SR18 field. */
+#define MWU_PERREGION_SUBSTATRA_SR18_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR18_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR17_Pos (17UL) /*!< Position of SR17 field. */
+#define MWU_PERREGION_SUBSTATRA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR17_Pos) /*!< Bit mask of SR17 field. */
+#define MWU_PERREGION_SUBSTATRA_SR17_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR17_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR16_Pos (16UL) /*!< Position of SR16 field. */
+#define MWU_PERREGION_SUBSTATRA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR16_Pos) /*!< Bit mask of SR16 field. */
+#define MWU_PERREGION_SUBSTATRA_SR16_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR16_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR15_Pos (15UL) /*!< Position of SR15 field. */
+#define MWU_PERREGION_SUBSTATRA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR15_Pos) /*!< Bit mask of SR15 field. */
+#define MWU_PERREGION_SUBSTATRA_SR15_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR15_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR14_Pos (14UL) /*!< Position of SR14 field. */
+#define MWU_PERREGION_SUBSTATRA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR14_Pos) /*!< Bit mask of SR14 field. */
+#define MWU_PERREGION_SUBSTATRA_SR14_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR14_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR13_Pos (13UL) /*!< Position of SR13 field. */
+#define MWU_PERREGION_SUBSTATRA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR13_Pos) /*!< Bit mask of SR13 field. */
+#define MWU_PERREGION_SUBSTATRA_SR13_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR13_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR12_Pos (12UL) /*!< Position of SR12 field. */
+#define MWU_PERREGION_SUBSTATRA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR12_Pos) /*!< Bit mask of SR12 field. */
+#define MWU_PERREGION_SUBSTATRA_SR12_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR12_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR11_Pos (11UL) /*!< Position of SR11 field. */
+#define MWU_PERREGION_SUBSTATRA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR11_Pos) /*!< Bit mask of SR11 field. */
+#define MWU_PERREGION_SUBSTATRA_SR11_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR11_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR10_Pos (10UL) /*!< Position of SR10 field. */
+#define MWU_PERREGION_SUBSTATRA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR10_Pos) /*!< Bit mask of SR10 field. */
+#define MWU_PERREGION_SUBSTATRA_SR10_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR10_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR9_Pos (9UL) /*!< Position of SR9 field. */
+#define MWU_PERREGION_SUBSTATRA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR9_Pos) /*!< Bit mask of SR9 field. */
+#define MWU_PERREGION_SUBSTATRA_SR9_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR9_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR8_Pos (8UL) /*!< Position of SR8 field. */
+#define MWU_PERREGION_SUBSTATRA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR8_Pos) /*!< Bit mask of SR8 field. */
+#define MWU_PERREGION_SUBSTATRA_SR8_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR8_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR7_Pos (7UL) /*!< Position of SR7 field. */
+#define MWU_PERREGION_SUBSTATRA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR7_Pos) /*!< Bit mask of SR7 field. */
+#define MWU_PERREGION_SUBSTATRA_SR7_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR7_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR6_Pos (6UL) /*!< Position of SR6 field. */
+#define MWU_PERREGION_SUBSTATRA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR6_Pos) /*!< Bit mask of SR6 field. */
+#define MWU_PERREGION_SUBSTATRA_SR6_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR6_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR5_Pos (5UL) /*!< Position of SR5 field. */
+#define MWU_PERREGION_SUBSTATRA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR5_Pos) /*!< Bit mask of SR5 field. */
+#define MWU_PERREGION_SUBSTATRA_SR5_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR5_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR4_Pos (4UL) /*!< Position of SR4 field. */
+#define MWU_PERREGION_SUBSTATRA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR4_Pos) /*!< Bit mask of SR4 field. */
+#define MWU_PERREGION_SUBSTATRA_SR4_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR4_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR3_Pos (3UL) /*!< Position of SR3 field. */
+#define MWU_PERREGION_SUBSTATRA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR3_Pos) /*!< Bit mask of SR3 field. */
+#define MWU_PERREGION_SUBSTATRA_SR3_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR3_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR2_Pos (2UL) /*!< Position of SR2 field. */
+#define MWU_PERREGION_SUBSTATRA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR2_Pos) /*!< Bit mask of SR2 field. */
+#define MWU_PERREGION_SUBSTATRA_SR2_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR2_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR1_Pos (1UL) /*!< Position of SR1 field. */
+#define MWU_PERREGION_SUBSTATRA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR1_Pos) /*!< Bit mask of SR1 field. */
+#define MWU_PERREGION_SUBSTATRA_SR1_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR1_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR0_Pos (0UL) /*!< Position of SR0 field. */
+#define MWU_PERREGION_SUBSTATRA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR0_Pos) /*!< Bit mask of SR0 field. */
+#define MWU_PERREGION_SUBSTATRA_SR0_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR0_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Register: MWU_REGIONEN */
+/* Description: Enable/disable regions watch */
+
+/* Bit 27 : Enable/disable read access watch in PREGION[1] */
+#define MWU_REGIONEN_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
+#define MWU_REGIONEN_PRGN1RA_Msk (0x1UL << MWU_REGIONEN_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
+#define MWU_REGIONEN_PRGN1RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
+#define MWU_REGIONEN_PRGN1RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
+
+/* Bit 26 : Enable/disable write access watch in PREGION[1] */
+#define MWU_REGIONEN_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
+#define MWU_REGIONEN_PRGN1WA_Msk (0x1UL << MWU_REGIONEN_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
+#define MWU_REGIONEN_PRGN1WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
+#define MWU_REGIONEN_PRGN1WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
+
+/* Bit 25 : Enable/disable read access watch in PREGION[0] */
+#define MWU_REGIONEN_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
+#define MWU_REGIONEN_PRGN0RA_Msk (0x1UL << MWU_REGIONEN_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
+#define MWU_REGIONEN_PRGN0RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
+#define MWU_REGIONEN_PRGN0RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
+
+/* Bit 24 : Enable/disable write access watch in PREGION[0] */
+#define MWU_REGIONEN_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
+#define MWU_REGIONEN_PRGN0WA_Msk (0x1UL << MWU_REGIONEN_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
+#define MWU_REGIONEN_PRGN0WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
+#define MWU_REGIONEN_PRGN0WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
+
+/* Bit 7 : Enable/disable read access watch in region[3] */
+#define MWU_REGIONEN_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
+#define MWU_REGIONEN_RGN3RA_Msk (0x1UL << MWU_REGIONEN_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
+#define MWU_REGIONEN_RGN3RA_Disable (0UL) /*!< Disable read access watch in this region */
+#define MWU_REGIONEN_RGN3RA_Enable (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 6 : Enable/disable write access watch in region[3] */
+#define MWU_REGIONEN_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
+#define MWU_REGIONEN_RGN3WA_Msk (0x1UL << MWU_REGIONEN_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
+#define MWU_REGIONEN_RGN3WA_Disable (0UL) /*!< Disable write access watch in this region */
+#define MWU_REGIONEN_RGN3WA_Enable (1UL) /*!< Enable write access watch in this region */
+
+/* Bit 5 : Enable/disable read access watch in region[2] */
+#define MWU_REGIONEN_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
+#define MWU_REGIONEN_RGN2RA_Msk (0x1UL << MWU_REGIONEN_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
+#define MWU_REGIONEN_RGN2RA_Disable (0UL) /*!< Disable read access watch in this region */
+#define MWU_REGIONEN_RGN2RA_Enable (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 4 : Enable/disable write access watch in region[2] */
+#define MWU_REGIONEN_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
+#define MWU_REGIONEN_RGN2WA_Msk (0x1UL << MWU_REGIONEN_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
+#define MWU_REGIONEN_RGN2WA_Disable (0UL) /*!< Disable write access watch in this region */
+#define MWU_REGIONEN_RGN2WA_Enable (1UL) /*!< Enable write access watch in this region */
+
+/* Bit 3 : Enable/disable read access watch in region[1] */
+#define MWU_REGIONEN_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
+#define MWU_REGIONEN_RGN1RA_Msk (0x1UL << MWU_REGIONEN_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
+#define MWU_REGIONEN_RGN1RA_Disable (0UL) /*!< Disable read access watch in this region */
+#define MWU_REGIONEN_RGN1RA_Enable (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 2 : Enable/disable write access watch in region[1] */
+#define MWU_REGIONEN_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
+#define MWU_REGIONEN_RGN1WA_Msk (0x1UL << MWU_REGIONEN_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
+#define MWU_REGIONEN_RGN1WA_Disable (0UL) /*!< Disable write access watch in this region */
+#define MWU_REGIONEN_RGN1WA_Enable (1UL) /*!< Enable write access watch in this region */
+
+/* Bit 1 : Enable/disable read access watch in region[0] */
+#define MWU_REGIONEN_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
+#define MWU_REGIONEN_RGN0RA_Msk (0x1UL << MWU_REGIONEN_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
+#define MWU_REGIONEN_RGN0RA_Disable (0UL) /*!< Disable read access watch in this region */
+#define MWU_REGIONEN_RGN0RA_Enable (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 0 : Enable/disable write access watch in region[0] */
+#define MWU_REGIONEN_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
+#define MWU_REGIONEN_RGN0WA_Msk (0x1UL << MWU_REGIONEN_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
+#define MWU_REGIONEN_RGN0WA_Disable (0UL) /*!< Disable write access watch in this region */
+#define MWU_REGIONEN_RGN0WA_Enable (1UL) /*!< Enable write access watch in this region */
+
+/* Register: MWU_REGIONENSET */
+/* Description: Enable regions watch */
+
+/* Bit 27 : Enable read access watch in PREGION[1] */
+#define MWU_REGIONENSET_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
+#define MWU_REGIONENSET_PRGN1RA_Msk (0x1UL << MWU_REGIONENSET_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
+#define MWU_REGIONENSET_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
+#define MWU_REGIONENSET_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
+#define MWU_REGIONENSET_PRGN1RA_Set (1UL) /*!< Enable read access watch in this PREGION */
+
+/* Bit 26 : Enable write access watch in PREGION[1] */
+#define MWU_REGIONENSET_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
+#define MWU_REGIONENSET_PRGN1WA_Msk (0x1UL << MWU_REGIONENSET_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
+#define MWU_REGIONENSET_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
+#define MWU_REGIONENSET_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
+#define MWU_REGIONENSET_PRGN1WA_Set (1UL) /*!< Enable write access watch in this PREGION */
+
+/* Bit 25 : Enable read access watch in PREGION[0] */
+#define MWU_REGIONENSET_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
+#define MWU_REGIONENSET_PRGN0RA_Msk (0x1UL << MWU_REGIONENSET_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
+#define MWU_REGIONENSET_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
+#define MWU_REGIONENSET_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
+#define MWU_REGIONENSET_PRGN0RA_Set (1UL) /*!< Enable read access watch in this PREGION */
+
+/* Bit 24 : Enable write access watch in PREGION[0] */
+#define MWU_REGIONENSET_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
+#define MWU_REGIONENSET_PRGN0WA_Msk (0x1UL << MWU_REGIONENSET_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
+#define MWU_REGIONENSET_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
+#define MWU_REGIONENSET_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
+#define MWU_REGIONENSET_PRGN0WA_Set (1UL) /*!< Enable write access watch in this PREGION */
+
+/* Bit 7 : Enable read access watch in region[3] */
+#define MWU_REGIONENSET_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
+#define MWU_REGIONENSET_RGN3RA_Msk (0x1UL << MWU_REGIONENSET_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
+#define MWU_REGIONENSET_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN3RA_Set (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 6 : Enable write access watch in region[3] */
+#define MWU_REGIONENSET_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
+#define MWU_REGIONENSET_RGN3WA_Msk (0x1UL << MWU_REGIONENSET_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
+#define MWU_REGIONENSET_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN3WA_Set (1UL) /*!< Enable write access watch in this region */
+
+/* Bit 5 : Enable read access watch in region[2] */
+#define MWU_REGIONENSET_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
+#define MWU_REGIONENSET_RGN2RA_Msk (0x1UL << MWU_REGIONENSET_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
+#define MWU_REGIONENSET_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN2RA_Set (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 4 : Enable write access watch in region[2] */
+#define MWU_REGIONENSET_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
+#define MWU_REGIONENSET_RGN2WA_Msk (0x1UL << MWU_REGIONENSET_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
+#define MWU_REGIONENSET_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN2WA_Set (1UL) /*!< Enable write access watch in this region */
+
+/* Bit 3 : Enable read access watch in region[1] */
+#define MWU_REGIONENSET_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
+#define MWU_REGIONENSET_RGN1RA_Msk (0x1UL << MWU_REGIONENSET_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
+#define MWU_REGIONENSET_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN1RA_Set (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 2 : Enable write access watch in region[1] */
+#define MWU_REGIONENSET_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
+#define MWU_REGIONENSET_RGN1WA_Msk (0x1UL << MWU_REGIONENSET_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
+#define MWU_REGIONENSET_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN1WA_Set (1UL) /*!< Enable write access watch in this region */
+
+/* Bit 1 : Enable read access watch in region[0] */
+#define MWU_REGIONENSET_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
+#define MWU_REGIONENSET_RGN0RA_Msk (0x1UL << MWU_REGIONENSET_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
+#define MWU_REGIONENSET_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN0RA_Set (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 0 : Enable write access watch in region[0] */
+#define MWU_REGIONENSET_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
+#define MWU_REGIONENSET_RGN0WA_Msk (0x1UL << MWU_REGIONENSET_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
+#define MWU_REGIONENSET_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN0WA_Set (1UL) /*!< Enable write access watch in this region */
+
+/* Register: MWU_REGIONENCLR */
+/* Description: Disable regions watch */
+
+/* Bit 27 : Disable read access watch in PREGION[1] */
+#define MWU_REGIONENCLR_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
+#define MWU_REGIONENCLR_PRGN1RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
+#define MWU_REGIONENCLR_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
+#define MWU_REGIONENCLR_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
+#define MWU_REGIONENCLR_PRGN1RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
+
+/* Bit 26 : Disable write access watch in PREGION[1] */
+#define MWU_REGIONENCLR_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
+#define MWU_REGIONENCLR_PRGN1WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
+#define MWU_REGIONENCLR_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
+#define MWU_REGIONENCLR_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
+#define MWU_REGIONENCLR_PRGN1WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
+
+/* Bit 25 : Disable read access watch in PREGION[0] */
+#define MWU_REGIONENCLR_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
+#define MWU_REGIONENCLR_PRGN0RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
+#define MWU_REGIONENCLR_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
+#define MWU_REGIONENCLR_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
+#define MWU_REGIONENCLR_PRGN0RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
+
+/* Bit 24 : Disable write access watch in PREGION[0] */
+#define MWU_REGIONENCLR_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
+#define MWU_REGIONENCLR_PRGN0WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
+#define MWU_REGIONENCLR_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
+#define MWU_REGIONENCLR_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
+#define MWU_REGIONENCLR_PRGN0WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
+
+/* Bit 7 : Disable read access watch in region[3] */
+#define MWU_REGIONENCLR_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
+#define MWU_REGIONENCLR_RGN3RA_Msk (0x1UL << MWU_REGIONENCLR_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
+#define MWU_REGIONENCLR_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN3RA_Clear (1UL) /*!< Disable read access watch in this region */
+
+/* Bit 6 : Disable write access watch in region[3] */
+#define MWU_REGIONENCLR_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
+#define MWU_REGIONENCLR_RGN3WA_Msk (0x1UL << MWU_REGIONENCLR_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
+#define MWU_REGIONENCLR_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN3WA_Clear (1UL) /*!< Disable write access watch in this region */
+
+/* Bit 5 : Disable read access watch in region[2] */
+#define MWU_REGIONENCLR_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
+#define MWU_REGIONENCLR_RGN2RA_Msk (0x1UL << MWU_REGIONENCLR_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
+#define MWU_REGIONENCLR_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN2RA_Clear (1UL) /*!< Disable read access watch in this region */
+
+/* Bit 4 : Disable write access watch in region[2] */
+#define MWU_REGIONENCLR_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
+#define MWU_REGIONENCLR_RGN2WA_Msk (0x1UL << MWU_REGIONENCLR_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
+#define MWU_REGIONENCLR_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN2WA_Clear (1UL) /*!< Disable write access watch in this region */
+
+/* Bit 3 : Disable read access watch in region[1] */
+#define MWU_REGIONENCLR_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
+#define MWU_REGIONENCLR_RGN1RA_Msk (0x1UL << MWU_REGIONENCLR_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
+#define MWU_REGIONENCLR_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN1RA_Clear (1UL) /*!< Disable read access watch in this region */
+
+/* Bit 2 : Disable write access watch in region[1] */
+#define MWU_REGIONENCLR_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
+#define MWU_REGIONENCLR_RGN1WA_Msk (0x1UL << MWU_REGIONENCLR_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
+#define MWU_REGIONENCLR_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN1WA_Clear (1UL) /*!< Disable write access watch in this region */
+
+/* Bit 1 : Disable read access watch in region[0] */
+#define MWU_REGIONENCLR_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
+#define MWU_REGIONENCLR_RGN0RA_Msk (0x1UL << MWU_REGIONENCLR_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
+#define MWU_REGIONENCLR_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN0RA_Clear (1UL) /*!< Disable read access watch in this region */
+
+/* Bit 0 : Disable write access watch in region[0] */
+#define MWU_REGIONENCLR_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
+#define MWU_REGIONENCLR_RGN0WA_Msk (0x1UL << MWU_REGIONENCLR_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
+#define MWU_REGIONENCLR_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN0WA_Clear (1UL) /*!< Disable write access watch in this region */
+
+/* Register: MWU_REGION_START */
+/* Description: Description cluster[0]:  Start address for region 0 */
+
+/* Bits 31..0 : Start address for region */
+#define MWU_REGION_START_START_Pos (0UL) /*!< Position of START field. */
+#define MWU_REGION_START_START_Msk (0xFFFFFFFFUL << MWU_REGION_START_START_Pos) /*!< Bit mask of START field. */
+
+/* Register: MWU_REGION_END */
+/* Description: Description cluster[0]:  End address of region 0 */
+
+/* Bits 31..0 : End address of region. */
+#define MWU_REGION_END_END_Pos (0UL) /*!< Position of END field. */
+#define MWU_REGION_END_END_Msk (0xFFFFFFFFUL << MWU_REGION_END_END_Pos) /*!< Bit mask of END field. */
+
+/* Register: MWU_PREGION_START */
+/* Description: Description cluster[0]:  Reserved for future use */
+
+/* Bits 31..0 : Reserved for future use */
+#define MWU_PREGION_START_START_Pos (0UL) /*!< Position of START field. */
+#define MWU_PREGION_START_START_Msk (0xFFFFFFFFUL << MWU_PREGION_START_START_Pos) /*!< Bit mask of START field. */
+
+/* Register: MWU_PREGION_END */
+/* Description: Description cluster[0]:  Reserved for future use */
+
+/* Bits 31..0 : Reserved for future use */
+#define MWU_PREGION_END_END_Pos (0UL) /*!< Position of END field. */
+#define MWU_PREGION_END_END_Msk (0xFFFFFFFFUL << MWU_PREGION_END_END_Pos) /*!< Bit mask of END field. */
+
+/* Register: MWU_PREGION_SUBS */
+/* Description: Description cluster[0]:  Subregions of region 0 */
+
+/* Bit 31 : Include or exclude subregion 31 in region */
+#define MWU_PREGION_SUBS_SR31_Pos (31UL) /*!< Position of SR31 field. */
+#define MWU_PREGION_SUBS_SR31_Msk (0x1UL << MWU_PREGION_SUBS_SR31_Pos) /*!< Bit mask of SR31 field. */
+#define MWU_PREGION_SUBS_SR31_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR31_Include (1UL) /*!< Include */
+
+/* Bit 30 : Include or exclude subregion 30 in region */
+#define MWU_PREGION_SUBS_SR30_Pos (30UL) /*!< Position of SR30 field. */
+#define MWU_PREGION_SUBS_SR30_Msk (0x1UL << MWU_PREGION_SUBS_SR30_Pos) /*!< Bit mask of SR30 field. */
+#define MWU_PREGION_SUBS_SR30_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR30_Include (1UL) /*!< Include */
+
+/* Bit 29 : Include or exclude subregion 29 in region */
+#define MWU_PREGION_SUBS_SR29_Pos (29UL) /*!< Position of SR29 field. */
+#define MWU_PREGION_SUBS_SR29_Msk (0x1UL << MWU_PREGION_SUBS_SR29_Pos) /*!< Bit mask of SR29 field. */
+#define MWU_PREGION_SUBS_SR29_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR29_Include (1UL) /*!< Include */
+
+/* Bit 28 : Include or exclude subregion 28 in region */
+#define MWU_PREGION_SUBS_SR28_Pos (28UL) /*!< Position of SR28 field. */
+#define MWU_PREGION_SUBS_SR28_Msk (0x1UL << MWU_PREGION_SUBS_SR28_Pos) /*!< Bit mask of SR28 field. */
+#define MWU_PREGION_SUBS_SR28_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR28_Include (1UL) /*!< Include */
+
+/* Bit 27 : Include or exclude subregion 27 in region */
+#define MWU_PREGION_SUBS_SR27_Pos (27UL) /*!< Position of SR27 field. */
+#define MWU_PREGION_SUBS_SR27_Msk (0x1UL << MWU_PREGION_SUBS_SR27_Pos) /*!< Bit mask of SR27 field. */
+#define MWU_PREGION_SUBS_SR27_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR27_Include (1UL) /*!< Include */
+
+/* Bit 26 : Include or exclude subregion 26 in region */
+#define MWU_PREGION_SUBS_SR26_Pos (26UL) /*!< Position of SR26 field. */
+#define MWU_PREGION_SUBS_SR26_Msk (0x1UL << MWU_PREGION_SUBS_SR26_Pos) /*!< Bit mask of SR26 field. */
+#define MWU_PREGION_SUBS_SR26_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR26_Include (1UL) /*!< Include */
+
+/* Bit 25 : Include or exclude subregion 25 in region */
+#define MWU_PREGION_SUBS_SR25_Pos (25UL) /*!< Position of SR25 field. */
+#define MWU_PREGION_SUBS_SR25_Msk (0x1UL << MWU_PREGION_SUBS_SR25_Pos) /*!< Bit mask of SR25 field. */
+#define MWU_PREGION_SUBS_SR25_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR25_Include (1UL) /*!< Include */
+
+/* Bit 24 : Include or exclude subregion 24 in region */
+#define MWU_PREGION_SUBS_SR24_Pos (24UL) /*!< Position of SR24 field. */
+#define MWU_PREGION_SUBS_SR24_Msk (0x1UL << MWU_PREGION_SUBS_SR24_Pos) /*!< Bit mask of SR24 field. */
+#define MWU_PREGION_SUBS_SR24_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR24_Include (1UL) /*!< Include */
+
+/* Bit 23 : Include or exclude subregion 23 in region */
+#define MWU_PREGION_SUBS_SR23_Pos (23UL) /*!< Position of SR23 field. */
+#define MWU_PREGION_SUBS_SR23_Msk (0x1UL << MWU_PREGION_SUBS_SR23_Pos) /*!< Bit mask of SR23 field. */
+#define MWU_PREGION_SUBS_SR23_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR23_Include (1UL) /*!< Include */
+
+/* Bit 22 : Include or exclude subregion 22 in region */
+#define MWU_PREGION_SUBS_SR22_Pos (22UL) /*!< Position of SR22 field. */
+#define MWU_PREGION_SUBS_SR22_Msk (0x1UL << MWU_PREGION_SUBS_SR22_Pos) /*!< Bit mask of SR22 field. */
+#define MWU_PREGION_SUBS_SR22_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR22_Include (1UL) /*!< Include */
+
+/* Bit 21 : Include or exclude subregion 21 in region */
+#define MWU_PREGION_SUBS_SR21_Pos (21UL) /*!< Position of SR21 field. */
+#define MWU_PREGION_SUBS_SR21_Msk (0x1UL << MWU_PREGION_SUBS_SR21_Pos) /*!< Bit mask of SR21 field. */
+#define MWU_PREGION_SUBS_SR21_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR21_Include (1UL) /*!< Include */
+
+/* Bit 20 : Include or exclude subregion 20 in region */
+#define MWU_PREGION_SUBS_SR20_Pos (20UL) /*!< Position of SR20 field. */
+#define MWU_PREGION_SUBS_SR20_Msk (0x1UL << MWU_PREGION_SUBS_SR20_Pos) /*!< Bit mask of SR20 field. */
+#define MWU_PREGION_SUBS_SR20_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR20_Include (1UL) /*!< Include */
+
+/* Bit 19 : Include or exclude subregion 19 in region */
+#define MWU_PREGION_SUBS_SR19_Pos (19UL) /*!< Position of SR19 field. */
+#define MWU_PREGION_SUBS_SR19_Msk (0x1UL << MWU_PREGION_SUBS_SR19_Pos) /*!< Bit mask of SR19 field. */
+#define MWU_PREGION_SUBS_SR19_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR19_Include (1UL) /*!< Include */
+
+/* Bit 18 : Include or exclude subregion 18 in region */
+#define MWU_PREGION_SUBS_SR18_Pos (18UL) /*!< Position of SR18 field. */
+#define MWU_PREGION_SUBS_SR18_Msk (0x1UL << MWU_PREGION_SUBS_SR18_Pos) /*!< Bit mask of SR18 field. */
+#define MWU_PREGION_SUBS_SR18_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR18_Include (1UL) /*!< Include */
+
+/* Bit 17 : Include or exclude subregion 17 in region */
+#define MWU_PREGION_SUBS_SR17_Pos (17UL) /*!< Position of SR17 field. */
+#define MWU_PREGION_SUBS_SR17_Msk (0x1UL << MWU_PREGION_SUBS_SR17_Pos) /*!< Bit mask of SR17 field. */
+#define MWU_PREGION_SUBS_SR17_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR17_Include (1UL) /*!< Include */
+
+/* Bit 16 : Include or exclude subregion 16 in region */
+#define MWU_PREGION_SUBS_SR16_Pos (16UL) /*!< Position of SR16 field. */
+#define MWU_PREGION_SUBS_SR16_Msk (0x1UL << MWU_PREGION_SUBS_SR16_Pos) /*!< Bit mask of SR16 field. */
+#define MWU_PREGION_SUBS_SR16_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR16_Include (1UL) /*!< Include */
+
+/* Bit 15 : Include or exclude subregion 15 in region */
+#define MWU_PREGION_SUBS_SR15_Pos (15UL) /*!< Position of SR15 field. */
+#define MWU_PREGION_SUBS_SR15_Msk (0x1UL << MWU_PREGION_SUBS_SR15_Pos) /*!< Bit mask of SR15 field. */
+#define MWU_PREGION_SUBS_SR15_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR15_Include (1UL) /*!< Include */
+
+/* Bit 14 : Include or exclude subregion 14 in region */
+#define MWU_PREGION_SUBS_SR14_Pos (14UL) /*!< Position of SR14 field. */
+#define MWU_PREGION_SUBS_SR14_Msk (0x1UL << MWU_PREGION_SUBS_SR14_Pos) /*!< Bit mask of SR14 field. */
+#define MWU_PREGION_SUBS_SR14_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR14_Include (1UL) /*!< Include */
+
+/* Bit 13 : Include or exclude subregion 13 in region */
+#define MWU_PREGION_SUBS_SR13_Pos (13UL) /*!< Position of SR13 field. */
+#define MWU_PREGION_SUBS_SR13_Msk (0x1UL << MWU_PREGION_SUBS_SR13_Pos) /*!< Bit mask of SR13 field. */
+#define MWU_PREGION_SUBS_SR13_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR13_Include (1UL) /*!< Include */
+
+/* Bit 12 : Include or exclude subregion 12 in region */
+#define MWU_PREGION_SUBS_SR12_Pos (12UL) /*!< Position of SR12 field. */
+#define MWU_PREGION_SUBS_SR12_Msk (0x1UL << MWU_PREGION_SUBS_SR12_Pos) /*!< Bit mask of SR12 field. */
+#define MWU_PREGION_SUBS_SR12_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR12_Include (1UL) /*!< Include */
+
+/* Bit 11 : Include or exclude subregion 11 in region */
+#define MWU_PREGION_SUBS_SR11_Pos (11UL) /*!< Position of SR11 field. */
+#define MWU_PREGION_SUBS_SR11_Msk (0x1UL << MWU_PREGION_SUBS_SR11_Pos) /*!< Bit mask of SR11 field. */
+#define MWU_PREGION_SUBS_SR11_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR11_Include (1UL) /*!< Include */
+
+/* Bit 10 : Include or exclude subregion 10 in region */
+#define MWU_PREGION_SUBS_SR10_Pos (10UL) /*!< Position of SR10 field. */
+#define MWU_PREGION_SUBS_SR10_Msk (0x1UL << MWU_PREGION_SUBS_SR10_Pos) /*!< Bit mask of SR10 field. */
+#define MWU_PREGION_SUBS_SR10_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR10_Include (1UL) /*!< Include */
+
+/* Bit 9 : Include or exclude subregion 9 in region */
+#define MWU_PREGION_SUBS_SR9_Pos (9UL) /*!< Position of SR9 field. */
+#define MWU_PREGION_SUBS_SR9_Msk (0x1UL << MWU_PREGION_SUBS_SR9_Pos) /*!< Bit mask of SR9 field. */
+#define MWU_PREGION_SUBS_SR9_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR9_Include (1UL) /*!< Include */
+
+/* Bit 8 : Include or exclude subregion 8 in region */
+#define MWU_PREGION_SUBS_SR8_Pos (8UL) /*!< Position of SR8 field. */
+#define MWU_PREGION_SUBS_SR8_Msk (0x1UL << MWU_PREGION_SUBS_SR8_Pos) /*!< Bit mask of SR8 field. */
+#define MWU_PREGION_SUBS_SR8_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR8_Include (1UL) /*!< Include */
+
+/* Bit 7 : Include or exclude subregion 7 in region */
+#define MWU_PREGION_SUBS_SR7_Pos (7UL) /*!< Position of SR7 field. */
+#define MWU_PREGION_SUBS_SR7_Msk (0x1UL << MWU_PREGION_SUBS_SR7_Pos) /*!< Bit mask of SR7 field. */
+#define MWU_PREGION_SUBS_SR7_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR7_Include (1UL) /*!< Include */
+
+/* Bit 6 : Include or exclude subregion 6 in region */
+#define MWU_PREGION_SUBS_SR6_Pos (6UL) /*!< Position of SR6 field. */
+#define MWU_PREGION_SUBS_SR6_Msk (0x1UL << MWU_PREGION_SUBS_SR6_Pos) /*!< Bit mask of SR6 field. */
+#define MWU_PREGION_SUBS_SR6_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR6_Include (1UL) /*!< Include */
+
+/* Bit 5 : Include or exclude subregion 5 in region */
+#define MWU_PREGION_SUBS_SR5_Pos (5UL) /*!< Position of SR5 field. */
+#define MWU_PREGION_SUBS_SR5_Msk (0x1UL << MWU_PREGION_SUBS_SR5_Pos) /*!< Bit mask of SR5 field. */
+#define MWU_PREGION_SUBS_SR5_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR5_Include (1UL) /*!< Include */
+
+/* Bit 4 : Include or exclude subregion 4 in region */
+#define MWU_PREGION_SUBS_SR4_Pos (4UL) /*!< Position of SR4 field. */
+#define MWU_PREGION_SUBS_SR4_Msk (0x1UL << MWU_PREGION_SUBS_SR4_Pos) /*!< Bit mask of SR4 field. */
+#define MWU_PREGION_SUBS_SR4_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR4_Include (1UL) /*!< Include */
+
+/* Bit 3 : Include or exclude subregion 3 in region */
+#define MWU_PREGION_SUBS_SR3_Pos (3UL) /*!< Position of SR3 field. */
+#define MWU_PREGION_SUBS_SR3_Msk (0x1UL << MWU_PREGION_SUBS_SR3_Pos) /*!< Bit mask of SR3 field. */
+#define MWU_PREGION_SUBS_SR3_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR3_Include (1UL) /*!< Include */
+
+/* Bit 2 : Include or exclude subregion 2 in region */
+#define MWU_PREGION_SUBS_SR2_Pos (2UL) /*!< Position of SR2 field. */
+#define MWU_PREGION_SUBS_SR2_Msk (0x1UL << MWU_PREGION_SUBS_SR2_Pos) /*!< Bit mask of SR2 field. */
+#define MWU_PREGION_SUBS_SR2_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR2_Include (1UL) /*!< Include */
+
+/* Bit 1 : Include or exclude subregion 1 in region */
+#define MWU_PREGION_SUBS_SR1_Pos (1UL) /*!< Position of SR1 field. */
+#define MWU_PREGION_SUBS_SR1_Msk (0x1UL << MWU_PREGION_SUBS_SR1_Pos) /*!< Bit mask of SR1 field. */
+#define MWU_PREGION_SUBS_SR1_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR1_Include (1UL) /*!< Include */
+
+/* Bit 0 : Include or exclude subregion 0 in region */
+#define MWU_PREGION_SUBS_SR0_Pos (0UL) /*!< Position of SR0 field. */
+#define MWU_PREGION_SUBS_SR0_Msk (0x1UL << MWU_PREGION_SUBS_SR0_Pos) /*!< Bit mask of SR0 field. */
+#define MWU_PREGION_SUBS_SR0_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR0_Include (1UL) /*!< Include */
+
+
+/* Peripheral: NFCT */
+/* Description: NFC-A compatible radio */
+
+/* Register: NFCT_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 5 : Shortcut between TXFRAMEEND event and ENABLERXDATA task */
+#define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Pos (5UL) /*!< Position of TXFRAMEEND_ENABLERXDATA field. */
+#define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Msk (0x1UL << NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Pos) /*!< Bit mask of TXFRAMEEND_ENABLERXDATA field. */
+#define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Disabled (0UL) /*!< Disable shortcut */
+#define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between FIELDLOST event and SENSE task */
+#define NFCT_SHORTS_FIELDLOST_SENSE_Pos (1UL) /*!< Position of FIELDLOST_SENSE field. */
+#define NFCT_SHORTS_FIELDLOST_SENSE_Msk (0x1UL << NFCT_SHORTS_FIELDLOST_SENSE_Pos) /*!< Bit mask of FIELDLOST_SENSE field. */
+#define NFCT_SHORTS_FIELDLOST_SENSE_Disabled (0UL) /*!< Disable shortcut */
+#define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between FIELDDETECTED event and ACTIVATE task */
+#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos (0UL) /*!< Position of FIELDDETECTED_ACTIVATE field. */
+#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk (0x1UL << NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos) /*!< Bit mask of FIELDDETECTED_ACTIVATE field. */
+#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled (0UL) /*!< Disable shortcut */
+#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: NFCT_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 20 : Enable or disable interrupt for STARTED event */
+#define NFCT_INTEN_STARTED_Pos (20UL) /*!< Position of STARTED field. */
+#define NFCT_INTEN_STARTED_Msk (0x1UL << NFCT_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define NFCT_INTEN_STARTED_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_STARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 19 : Enable or disable interrupt for SELECTED event */
+#define NFCT_INTEN_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
+#define NFCT_INTEN_SELECTED_Msk (0x1UL << NFCT_INTEN_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
+#define NFCT_INTEN_SELECTED_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_SELECTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 18 : Enable or disable interrupt for COLLISION event */
+#define NFCT_INTEN_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
+#define NFCT_INTEN_COLLISION_Msk (0x1UL << NFCT_INTEN_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
+#define NFCT_INTEN_COLLISION_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_COLLISION_Enabled (1UL) /*!< Enable */
+
+/* Bit 14 : Enable or disable interrupt for AUTOCOLRESSTARTED event */
+#define NFCT_INTEN_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
+#define NFCT_INTEN_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTEN_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
+#define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 12 : Enable or disable interrupt for ENDTX event */
+#define NFCT_INTEN_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
+#define NFCT_INTEN_ENDTX_Msk (0x1UL << NFCT_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define NFCT_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
+
+/* Bit 11 : Enable or disable interrupt for ENDRX event */
+#define NFCT_INTEN_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
+#define NFCT_INTEN_ENDRX_Msk (0x1UL << NFCT_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define NFCT_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
+
+/* Bit 10 : Enable or disable interrupt for RXERROR event */
+#define NFCT_INTEN_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
+#define NFCT_INTEN_RXERROR_Msk (0x1UL << NFCT_INTEN_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
+#define NFCT_INTEN_RXERROR_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_RXERROR_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable interrupt for ERROR event */
+#define NFCT_INTEN_ERROR_Pos (7UL) /*!< Position of ERROR field. */
+#define NFCT_INTEN_ERROR_Msk (0x1UL << NFCT_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define NFCT_INTEN_ERROR_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_ERROR_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable interrupt for RXFRAMEEND event */
+#define NFCT_INTEN_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
+#define NFCT_INTEN_RXFRAMEEND_Msk (0x1UL << NFCT_INTEN_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
+#define NFCT_INTEN_RXFRAMEEND_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_RXFRAMEEND_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable interrupt for RXFRAMESTART event */
+#define NFCT_INTEN_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
+#define NFCT_INTEN_RXFRAMESTART_Msk (0x1UL << NFCT_INTEN_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
+#define NFCT_INTEN_RXFRAMESTART_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_RXFRAMESTART_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for TXFRAMEEND event */
+#define NFCT_INTEN_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
+#define NFCT_INTEN_TXFRAMEEND_Msk (0x1UL << NFCT_INTEN_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
+#define NFCT_INTEN_TXFRAMEEND_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_TXFRAMEEND_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable interrupt for TXFRAMESTART event */
+#define NFCT_INTEN_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
+#define NFCT_INTEN_TXFRAMESTART_Msk (0x1UL << NFCT_INTEN_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
+#define NFCT_INTEN_TXFRAMESTART_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_TXFRAMESTART_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for FIELDLOST event */
+#define NFCT_INTEN_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
+#define NFCT_INTEN_FIELDLOST_Msk (0x1UL << NFCT_INTEN_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
+#define NFCT_INTEN_FIELDLOST_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_FIELDLOST_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for FIELDDETECTED event */
+#define NFCT_INTEN_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
+#define NFCT_INTEN_FIELDDETECTED_Msk (0x1UL << NFCT_INTEN_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
+#define NFCT_INTEN_FIELDDETECTED_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_FIELDDETECTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for READY event */
+#define NFCT_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
+#define NFCT_INTEN_READY_Msk (0x1UL << NFCT_INTEN_READY_Pos) /*!< Bit mask of READY field. */
+#define NFCT_INTEN_READY_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_READY_Enabled (1UL) /*!< Enable */
+
+/* Register: NFCT_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 20 : Write '1' to Enable interrupt for STARTED event */
+#define NFCT_INTENSET_STARTED_Pos (20UL) /*!< Position of STARTED field. */
+#define NFCT_INTENSET_STARTED_Msk (0x1UL << NFCT_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define NFCT_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_STARTED_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to Enable interrupt for SELECTED event */
+#define NFCT_INTENSET_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
+#define NFCT_INTENSET_SELECTED_Msk (0x1UL << NFCT_INTENSET_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
+#define NFCT_INTENSET_SELECTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_SELECTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_SELECTED_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to Enable interrupt for COLLISION event */
+#define NFCT_INTENSET_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
+#define NFCT_INTENSET_COLLISION_Msk (0x1UL << NFCT_INTENSET_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
+#define NFCT_INTENSET_COLLISION_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_COLLISION_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_COLLISION_Set (1UL) /*!< Enable */
+
+/* Bit 14 : Write '1' to Enable interrupt for AUTOCOLRESSTARTED event */
+#define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
+#define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
+#define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 12 : Write '1' to Enable interrupt for ENDTX event */
+#define NFCT_INTENSET_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
+#define NFCT_INTENSET_ENDTX_Msk (0x1UL << NFCT_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define NFCT_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_ENDTX_Set (1UL) /*!< Enable */
+
+/* Bit 11 : Write '1' to Enable interrupt for ENDRX event */
+#define NFCT_INTENSET_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
+#define NFCT_INTENSET_ENDRX_Msk (0x1UL << NFCT_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define NFCT_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_ENDRX_Set (1UL) /*!< Enable */
+
+/* Bit 10 : Write '1' to Enable interrupt for RXERROR event */
+#define NFCT_INTENSET_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
+#define NFCT_INTENSET_RXERROR_Msk (0x1UL << NFCT_INTENSET_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
+#define NFCT_INTENSET_RXERROR_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_RXERROR_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_RXERROR_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for ERROR event */
+#define NFCT_INTENSET_ERROR_Pos (7UL) /*!< Position of ERROR field. */
+#define NFCT_INTENSET_ERROR_Msk (0x1UL << NFCT_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define NFCT_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for RXFRAMEEND event */
+#define NFCT_INTENSET_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
+#define NFCT_INTENSET_RXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
+#define NFCT_INTENSET_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_RXFRAMEEND_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable interrupt for RXFRAMESTART event */
+#define NFCT_INTENSET_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
+#define NFCT_INTENSET_RXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
+#define NFCT_INTENSET_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_RXFRAMESTART_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for TXFRAMEEND event */
+#define NFCT_INTENSET_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
+#define NFCT_INTENSET_TXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
+#define NFCT_INTENSET_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_TXFRAMEEND_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for TXFRAMESTART event */
+#define NFCT_INTENSET_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
+#define NFCT_INTENSET_TXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
+#define NFCT_INTENSET_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_TXFRAMESTART_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for FIELDLOST event */
+#define NFCT_INTENSET_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
+#define NFCT_INTENSET_FIELDLOST_Msk (0x1UL << NFCT_INTENSET_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
+#define NFCT_INTENSET_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_FIELDLOST_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for FIELDDETECTED event */
+#define NFCT_INTENSET_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
+#define NFCT_INTENSET_FIELDDETECTED_Msk (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
+#define NFCT_INTENSET_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_FIELDDETECTED_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for READY event */
+#define NFCT_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
+#define NFCT_INTENSET_READY_Msk (0x1UL << NFCT_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define NFCT_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_READY_Set (1UL) /*!< Enable */
+
+/* Register: NFCT_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 20 : Write '1' to Disable interrupt for STARTED event */
+#define NFCT_INTENCLR_STARTED_Pos (20UL) /*!< Position of STARTED field. */
+#define NFCT_INTENCLR_STARTED_Msk (0x1UL << NFCT_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define NFCT_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to Disable interrupt for SELECTED event */
+#define NFCT_INTENCLR_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
+#define NFCT_INTENCLR_SELECTED_Msk (0x1UL << NFCT_INTENCLR_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
+#define NFCT_INTENCLR_SELECTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_SELECTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_SELECTED_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to Disable interrupt for COLLISION event */
+#define NFCT_INTENCLR_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
+#define NFCT_INTENCLR_COLLISION_Msk (0x1UL << NFCT_INTENCLR_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
+#define NFCT_INTENCLR_COLLISION_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_COLLISION_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_COLLISION_Clear (1UL) /*!< Disable */
+
+/* Bit 14 : Write '1' to Disable interrupt for AUTOCOLRESSTARTED event */
+#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
+#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
+#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 12 : Write '1' to Disable interrupt for ENDTX event */
+#define NFCT_INTENCLR_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
+#define NFCT_INTENCLR_ENDTX_Msk (0x1UL << NFCT_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define NFCT_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
+
+/* Bit 11 : Write '1' to Disable interrupt for ENDRX event */
+#define NFCT_INTENCLR_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
+#define NFCT_INTENCLR_ENDRX_Msk (0x1UL << NFCT_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define NFCT_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
+
+/* Bit 10 : Write '1' to Disable interrupt for RXERROR event */
+#define NFCT_INTENCLR_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
+#define NFCT_INTENCLR_RXERROR_Msk (0x1UL << NFCT_INTENCLR_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
+#define NFCT_INTENCLR_RXERROR_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_RXERROR_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_RXERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for ERROR event */
+#define NFCT_INTENCLR_ERROR_Pos (7UL) /*!< Position of ERROR field. */
+#define NFCT_INTENCLR_ERROR_Msk (0x1UL << NFCT_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define NFCT_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for RXFRAMEEND event */
+#define NFCT_INTENCLR_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
+#define NFCT_INTENCLR_RXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
+#define NFCT_INTENCLR_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_RXFRAMEEND_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable interrupt for RXFRAMESTART event */
+#define NFCT_INTENCLR_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
+#define NFCT_INTENCLR_RXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
+#define NFCT_INTENCLR_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_RXFRAMESTART_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for TXFRAMEEND event */
+#define NFCT_INTENCLR_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
+#define NFCT_INTENCLR_TXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
+#define NFCT_INTENCLR_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_TXFRAMEEND_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for TXFRAMESTART event */
+#define NFCT_INTENCLR_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
+#define NFCT_INTENCLR_TXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
+#define NFCT_INTENCLR_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_TXFRAMESTART_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for FIELDLOST event */
+#define NFCT_INTENCLR_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
+#define NFCT_INTENCLR_FIELDLOST_Msk (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
+#define NFCT_INTENCLR_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_FIELDLOST_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for FIELDDETECTED event */
+#define NFCT_INTENCLR_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
+#define NFCT_INTENCLR_FIELDDETECTED_Msk (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
+#define NFCT_INTENCLR_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_FIELDDETECTED_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for READY event */
+#define NFCT_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
+#define NFCT_INTENCLR_READY_Msk (0x1UL << NFCT_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define NFCT_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_READY_Clear (1UL) /*!< Disable */
+
+/* Register: NFCT_ERRORSTATUS */
+/* Description: NFC Error Status register */
+
+/* Bit 0 : No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX */
+#define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos (0UL) /*!< Position of FRAMEDELAYTIMEOUT field. */
+#define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Msk (0x1UL << NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos) /*!< Bit mask of FRAMEDELAYTIMEOUT field. */
+
+/* Register: NFCT_FRAMESTATUS_RX */
+/* Description: Result of last incoming frame */
+
+/* Bit 3 : Overrun detected */
+#define NFCT_FRAMESTATUS_RX_OVERRUN_Pos (3UL) /*!< Position of OVERRUN field. */
+#define NFCT_FRAMESTATUS_RX_OVERRUN_Msk (0x1UL << NFCT_FRAMESTATUS_RX_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
+#define NFCT_FRAMESTATUS_RX_OVERRUN_NoOverrun (0UL) /*!< No overrun detected */
+#define NFCT_FRAMESTATUS_RX_OVERRUN_Overrun (1UL) /*!< Overrun error */
+
+/* Bit 2 : Parity status of received frame */
+#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos (2UL) /*!< Position of PARITYSTATUS field. */
+#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Msk (0x1UL << NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos) /*!< Bit mask of PARITYSTATUS field. */
+#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityOK (0UL) /*!< Frame received with parity OK */
+#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityError (1UL) /*!< Frame received with parity error */
+
+/* Bit 0 : No valid end of frame (EoF) detected */
+#define NFCT_FRAMESTATUS_RX_CRCERROR_Pos (0UL) /*!< Position of CRCERROR field. */
+#define NFCT_FRAMESTATUS_RX_CRCERROR_Msk (0x1UL << NFCT_FRAMESTATUS_RX_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
+#define NFCT_FRAMESTATUS_RX_CRCERROR_CRCCorrect (0UL) /*!< Valid CRC detected */
+#define NFCT_FRAMESTATUS_RX_CRCERROR_CRCError (1UL) /*!< CRC received does not match local check */
+
+/* Register: NFCT_NFCTAGSTATE */
+/* Description: NfcTag state register */
+
+/* Bits 2..0 : NfcTag state */
+#define NFCT_NFCTAGSTATE_NFCTAGSTATE_Pos (0UL) /*!< Position of NFCTAGSTATE field. */
+#define NFCT_NFCTAGSTATE_NFCTAGSTATE_Msk (0x7UL << NFCT_NFCTAGSTATE_NFCTAGSTATE_Pos) /*!< Bit mask of NFCTAGSTATE field. */
+#define NFCT_NFCTAGSTATE_NFCTAGSTATE_Disabled (0UL) /*!< Disabled or sense */
+#define NFCT_NFCTAGSTATE_NFCTAGSTATE_RampUp (2UL) /*!< RampUp */
+#define NFCT_NFCTAGSTATE_NFCTAGSTATE_Idle (3UL) /*!< Idle */
+#define NFCT_NFCTAGSTATE_NFCTAGSTATE_Receive (4UL) /*!< Receive */
+#define NFCT_NFCTAGSTATE_NFCTAGSTATE_FrameDelay (5UL) /*!< FrameDelay */
+#define NFCT_NFCTAGSTATE_NFCTAGSTATE_Transmit (6UL) /*!< Transmit */
+
+/* Register: NFCT_FIELDPRESENT */
+/* Description: Indicates the presence or not of a valid field */
+
+/* Bit 1 : Indicates if the low level has locked to the field */
+#define NFCT_FIELDPRESENT_LOCKDETECT_Pos (1UL) /*!< Position of LOCKDETECT field. */
+#define NFCT_FIELDPRESENT_LOCKDETECT_Msk (0x1UL << NFCT_FIELDPRESENT_LOCKDETECT_Pos) /*!< Bit mask of LOCKDETECT field. */
+#define NFCT_FIELDPRESENT_LOCKDETECT_NotLocked (0UL) /*!< Not locked to field */
+#define NFCT_FIELDPRESENT_LOCKDETECT_Locked (1UL) /*!< Locked to field */
+
+/* Bit 0 : Indicates if a valid field is present. Available only in the activated state. */
+#define NFCT_FIELDPRESENT_FIELDPRESENT_Pos (0UL) /*!< Position of FIELDPRESENT field. */
+#define NFCT_FIELDPRESENT_FIELDPRESENT_Msk (0x1UL << NFCT_FIELDPRESENT_FIELDPRESENT_Pos) /*!< Bit mask of FIELDPRESENT field. */
+#define NFCT_FIELDPRESENT_FIELDPRESENT_NoField (0UL) /*!< No valid field detected */
+#define NFCT_FIELDPRESENT_FIELDPRESENT_FieldPresent (1UL) /*!< Valid field detected */
+
+/* Register: NFCT_FRAMEDELAYMIN */
+/* Description: Minimum frame delay */
+
+/* Bits 15..0 : Minimum frame delay in number of 13.56 MHz clocks */
+#define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos (0UL) /*!< Position of FRAMEDELAYMIN field. */
+#define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Msk (0xFFFFUL << NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos) /*!< Bit mask of FRAMEDELAYMIN field. */
+
+/* Register: NFCT_FRAMEDELAYMAX */
+/* Description: Maximum frame delay */
+
+/* Bits 15..0 : Maximum frame delay in number of 13.56 MHz clocks */
+#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos (0UL) /*!< Position of FRAMEDELAYMAX field. */
+#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk (0xFFFFUL << NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos) /*!< Bit mask of FRAMEDELAYMAX field. */
+
+/* Register: NFCT_FRAMEDELAYMODE */
+/* Description: Configuration register for the Frame Delay Timer */
+
+/* Bits 1..0 : Configuration register for the Frame Delay Timer */
+#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos (0UL) /*!< Position of FRAMEDELAYMODE field. */
+#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Msk (0x3UL << NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos) /*!< Bit mask of FRAMEDELAYMODE field. */
+#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_FreeRun (0UL) /*!< Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. */
+#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Window (1UL) /*!< Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX */
+#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_ExactVal (2UL) /*!< Frame is transmitted exactly at FRAMEDELAYMAX */
+#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_WindowGrid (3UL) /*!< Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX */
+
+/* Register: NFCT_PACKETPTR */
+/* Description: Packet pointer for TXD and RXD data storage in Data RAM */
+
+/* Bits 31..0 : Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-aligned RAM address. */
+#define NFCT_PACKETPTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define NFCT_PACKETPTR_PTR_Msk (0xFFFFFFFFUL << NFCT_PACKETPTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: NFCT_MAXLEN */
+/* Description: Size of the RAM buffer allocated to TXD and RXD data storage each */
+
+/* Bits 8..0 : Size of the RAM buffer allocated to TXD and RXD data storage each */
+#define NFCT_MAXLEN_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
+#define NFCT_MAXLEN_MAXLEN_Msk (0x1FFUL << NFCT_MAXLEN_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
+
+/* Register: NFCT_TXD_FRAMECONFIG */
+/* Description: Configuration of outgoing frames */
+
+/* Bit 4 : CRC mode for outgoing frames */
+#define NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos (4UL) /*!< Position of CRCMODETX field. */
+#define NFCT_TXD_FRAMECONFIG_CRCMODETX_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos) /*!< Bit mask of CRCMODETX field. */
+#define NFCT_TXD_FRAMECONFIG_CRCMODETX_NoCRCTX (0UL) /*!< CRC is not added to the frame */
+#define NFCT_TXD_FRAMECONFIG_CRCMODETX_CRC16TX (1UL) /*!< 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame */
+
+/* Bit 2 : Adding SoF or not in TX frames */
+#define NFCT_TXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
+#define NFCT_TXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */
+#define NFCT_TXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< SoF symbol not added */
+#define NFCT_TXD_FRAMECONFIG_SOF_SoF (1UL) /*!< SoF symbol added */
+
+/* Bit 1 : Discarding unused bits at start or end of a frame */
+#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos (1UL) /*!< Position of DISCARDMODE field. */
+#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos) /*!< Bit mask of DISCARDMODE field. */
+#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardEnd (0UL) /*!< Unused bits are discarded at end of frame (EoF) */
+#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardStart (1UL) /*!< Unused bits are discarded at start of frame (SoF) */
+
+/* Bit 0 : Indicates if parity is added to the frame */
+#define NFCT_TXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */
+#define NFCT_TXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define NFCT_TXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not added to TX frames */
+#define NFCT_TXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is added to TX frames */
+
+/* Register: NFCT_TXD_AMOUNT */
+/* Description: Size of outgoing frame */
+
+/* Bits 11..3 : Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing */
+#define NFCT_TXD_AMOUNT_TXDATABYTES_Pos (3UL) /*!< Position of TXDATABYTES field. */
+#define NFCT_TXD_AMOUNT_TXDATABYTES_Msk (0x1FFUL << NFCT_TXD_AMOUNT_TXDATABYTES_Pos) /*!< Bit mask of TXDATABYTES field. */
+
+/* Bits 2..0 : Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). */
+#define NFCT_TXD_AMOUNT_TXDATABITS_Pos (0UL) /*!< Position of TXDATABITS field. */
+#define NFCT_TXD_AMOUNT_TXDATABITS_Msk (0x7UL << NFCT_TXD_AMOUNT_TXDATABITS_Pos) /*!< Bit mask of TXDATABITS field. */
+
+/* Register: NFCT_RXD_FRAMECONFIG */
+/* Description: Configuration of incoming frames */
+
+/* Bit 4 : CRC mode for incoming frames */
+#define NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos (4UL) /*!< Position of CRCMODERX field. */
+#define NFCT_RXD_FRAMECONFIG_CRCMODERX_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos) /*!< Bit mask of CRCMODERX field. */
+#define NFCT_RXD_FRAMECONFIG_CRCMODERX_NoCRCRX (0UL) /*!< CRC is not expected in RX frames */
+#define NFCT_RXD_FRAMECONFIG_CRCMODERX_CRC16RX (1UL) /*!< Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated */
+
+/* Bit 2 : SoF expected or not in RX frames */
+#define NFCT_RXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
+#define NFCT_RXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */
+#define NFCT_RXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< SoF symbol is not expected in RX frames */
+#define NFCT_RXD_FRAMECONFIG_SOF_SoF (1UL) /*!< SoF symbol is expected in RX frames */
+
+/* Bit 0 : Indicates if parity expected in RX frame */
+#define NFCT_RXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */
+#define NFCT_RXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define NFCT_RXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not expected in RX frames */
+#define NFCT_RXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is expected in RX frames */
+
+/* Register: NFCT_RXD_AMOUNT */
+/* Description: Size of last incoming frame */
+
+/* Bits 11..3 : Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) */
+#define NFCT_RXD_AMOUNT_RXDATABYTES_Pos (3UL) /*!< Position of RXDATABYTES field. */
+#define NFCT_RXD_AMOUNT_RXDATABYTES_Msk (0x1FFUL << NFCT_RXD_AMOUNT_RXDATABYTES_Pos) /*!< Bit mask of RXDATABYTES field. */
+
+/* Bits 2..0 : Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). */
+#define NFCT_RXD_AMOUNT_RXDATABITS_Pos (0UL) /*!< Position of RXDATABITS field. */
+#define NFCT_RXD_AMOUNT_RXDATABITS_Msk (0x7UL << NFCT_RXD_AMOUNT_RXDATABITS_Pos) /*!< Bit mask of RXDATABITS field. */
+
+/* Register: NFCT_NFCID1_LAST */
+/* Description: Last NFCID1 part (4, 7 or 10 bytes ID) */
+
+/* Bits 31..24 : NFCID1 byte W */
+#define NFCT_NFCID1_LAST_NFCID1_W_Pos (24UL) /*!< Position of NFCID1_W field. */
+#define NFCT_NFCID1_LAST_NFCID1_W_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_W_Pos) /*!< Bit mask of NFCID1_W field. */
+
+/* Bits 23..16 : NFCID1 byte X */
+#define NFCT_NFCID1_LAST_NFCID1_X_Pos (16UL) /*!< Position of NFCID1_X field. */
+#define NFCT_NFCID1_LAST_NFCID1_X_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_X_Pos) /*!< Bit mask of NFCID1_X field. */
+
+/* Bits 15..8 : NFCID1 byte Y */
+#define NFCT_NFCID1_LAST_NFCID1_Y_Pos (8UL) /*!< Position of NFCID1_Y field. */
+#define NFCT_NFCID1_LAST_NFCID1_Y_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Y_Pos) /*!< Bit mask of NFCID1_Y field. */
+
+/* Bits 7..0 : NFCID1 byte Z (very last byte sent) */
+#define NFCT_NFCID1_LAST_NFCID1_Z_Pos (0UL) /*!< Position of NFCID1_Z field. */
+#define NFCT_NFCID1_LAST_NFCID1_Z_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Z_Pos) /*!< Bit mask of NFCID1_Z field. */
+
+/* Register: NFCT_NFCID1_2ND_LAST */
+/* Description: Second last NFCID1 part (7 or 10 bytes ID) */
+
+/* Bits 23..16 : NFCID1 byte T */
+#define NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos (16UL) /*!< Position of NFCID1_T field. */
+#define NFCT_NFCID1_2ND_LAST_NFCID1_T_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos) /*!< Bit mask of NFCID1_T field. */
+
+/* Bits 15..8 : NFCID1 byte U */
+#define NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos (8UL) /*!< Position of NFCID1_U field. */
+#define NFCT_NFCID1_2ND_LAST_NFCID1_U_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos) /*!< Bit mask of NFCID1_U field. */
+
+/* Bits 7..0 : NFCID1 byte V */
+#define NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos (0UL) /*!< Position of NFCID1_V field. */
+#define NFCT_NFCID1_2ND_LAST_NFCID1_V_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos) /*!< Bit mask of NFCID1_V field. */
+
+/* Register: NFCT_NFCID1_3RD_LAST */
+/* Description: Third last NFCID1 part (10 bytes ID) */
+
+/* Bits 23..16 : NFCID1 byte Q */
+#define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos (16UL) /*!< Position of NFCID1_Q field. */
+#define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos) /*!< Bit mask of NFCID1_Q field. */
+
+/* Bits 15..8 : NFCID1 byte R */
+#define NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos (8UL) /*!< Position of NFCID1_R field. */
+#define NFCT_NFCID1_3RD_LAST_NFCID1_R_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos) /*!< Bit mask of NFCID1_R field. */
+
+/* Bits 7..0 : NFCID1 byte S */
+#define NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos (0UL) /*!< Position of NFCID1_S field. */
+#define NFCT_NFCID1_3RD_LAST_NFCID1_S_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos) /*!< Bit mask of NFCID1_S field. */
+
+/* Register: NFCT_AUTOCOLRESCONFIG */
+/* Description: Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is enabled. */
+
+/* Bit 0 : Enables/disables auto collision resolution */
+#define NFCT_AUTOCOLRESCONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define NFCT_AUTOCOLRESCONFIG_MODE_Msk (0x1UL << NFCT_AUTOCOLRESCONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
+#define NFCT_AUTOCOLRESCONFIG_MODE_Enabled (0UL) /*!< Auto collision resolution enabled */
+#define NFCT_AUTOCOLRESCONFIG_MODE_Disabled (1UL) /*!< Auto collision resolution disabled */
+
+/* Register: NFCT_SENSRES */
+/* Description: NFC-A SENS_RES auto-response settings */
+
+/* Bits 15..12 : Reserved for future use. Shall be 0. */
+#define NFCT_SENSRES_RFU74_Pos (12UL) /*!< Position of RFU74 field. */
+#define NFCT_SENSRES_RFU74_Msk (0xFUL << NFCT_SENSRES_RFU74_Pos) /*!< Bit mask of RFU74 field. */
+
+/* Bits 11..8 : Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
+#define NFCT_SENSRES_PLATFCONFIG_Pos (8UL) /*!< Position of PLATFCONFIG field. */
+#define NFCT_SENSRES_PLATFCONFIG_Msk (0xFUL << NFCT_SENSRES_PLATFCONFIG_Pos) /*!< Bit mask of PLATFCONFIG field. */
+
+/* Bits 7..6 : NFCID1 size. This value is used by the auto collision resolution engine. */
+#define NFCT_SENSRES_NFCIDSIZE_Pos (6UL) /*!< Position of NFCIDSIZE field. */
+#define NFCT_SENSRES_NFCIDSIZE_Msk (0x3UL << NFCT_SENSRES_NFCIDSIZE_Pos) /*!< Bit mask of NFCIDSIZE field. */
+#define NFCT_SENSRES_NFCIDSIZE_NFCID1Single (0UL) /*!< NFCID1 size: single (4 bytes) */
+#define NFCT_SENSRES_NFCIDSIZE_NFCID1Double (1UL) /*!< NFCID1 size: double (7 bytes) */
+#define NFCT_SENSRES_NFCIDSIZE_NFCID1Triple (2UL) /*!< NFCID1 size: triple (10 bytes) */
+
+/* Bit 5 : Reserved for future use. Shall be 0. */
+#define NFCT_SENSRES_RFU5_Pos (5UL) /*!< Position of RFU5 field. */
+#define NFCT_SENSRES_RFU5_Msk (0x1UL << NFCT_SENSRES_RFU5_Pos) /*!< Bit mask of RFU5 field. */
+
+/* Bits 4..0 : Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the <i>NFC Forum, NFC Digital Protocol Technical Specification</i> */
+#define NFCT_SENSRES_BITFRAMESDD_Pos (0UL) /*!< Position of BITFRAMESDD field. */
+#define NFCT_SENSRES_BITFRAMESDD_Msk (0x1FUL << NFCT_SENSRES_BITFRAMESDD_Pos) /*!< Bit mask of BITFRAMESDD field. */
+#define NFCT_SENSRES_BITFRAMESDD_SDD00000 (0UL) /*!< SDD pattern 00000 */
+#define NFCT_SENSRES_BITFRAMESDD_SDD00001 (1UL) /*!< SDD pattern 00001 */
+#define NFCT_SENSRES_BITFRAMESDD_SDD00010 (2UL) /*!< SDD pattern 00010 */
+#define NFCT_SENSRES_BITFRAMESDD_SDD00100 (4UL) /*!< SDD pattern 00100 */
+#define NFCT_SENSRES_BITFRAMESDD_SDD01000 (8UL) /*!< SDD pattern 01000 */
+#define NFCT_SENSRES_BITFRAMESDD_SDD10000 (16UL) /*!< SDD pattern 10000 */
+
+/* Register: NFCT_SELRES */
+/* Description: NFC-A SEL_RES auto-response settings */
+
+/* Bit 7 : Reserved for future use. Shall be 0. */
+#define NFCT_SELRES_RFU7_Pos (7UL) /*!< Position of RFU7 field. */
+#define NFCT_SELRES_RFU7_Msk (0x1UL << NFCT_SELRES_RFU7_Pos) /*!< Bit mask of RFU7 field. */
+
+/* Bits 6..5 : Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
+#define NFCT_SELRES_PROTOCOL_Pos (5UL) /*!< Position of PROTOCOL field. */
+#define NFCT_SELRES_PROTOCOL_Msk (0x3UL << NFCT_SELRES_PROTOCOL_Pos) /*!< Bit mask of PROTOCOL field. */
+
+/* Bits 4..3 : Reserved for future use. Shall be 0. */
+#define NFCT_SELRES_RFU43_Pos (3UL) /*!< Position of RFU43 field. */
+#define NFCT_SELRES_RFU43_Msk (0x3UL << NFCT_SELRES_RFU43_Pos) /*!< Bit mask of RFU43 field. */
+
+/* Bit 2 : Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification (controlled by hardware, shall be 0) */
+#define NFCT_SELRES_CASCADE_Pos (2UL) /*!< Position of CASCADE field. */
+#define NFCT_SELRES_CASCADE_Msk (0x1UL << NFCT_SELRES_CASCADE_Pos) /*!< Bit mask of CASCADE field. */
+
+/* Bits 1..0 : Reserved for future use. Shall be 0. */
+#define NFCT_SELRES_RFU10_Pos (0UL) /*!< Position of RFU10 field. */
+#define NFCT_SELRES_RFU10_Msk (0x3UL << NFCT_SELRES_RFU10_Pos) /*!< Bit mask of RFU10 field. */
+
+
+/* Peripheral: NVMC */
+/* Description: Non Volatile Memory Controller */
+
+/* Register: NVMC_READY */
+/* Description: Ready flag */
+
+/* Bit 0 : NVMC is ready or busy */
+#define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
+#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
+#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */
+#define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */
+
+/* Register: NVMC_CONFIG */
+/* Description: Configuration register */
+
+/* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */
+#define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
+#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
+#define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */
+#define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write Enabled */
+#define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */
+
+/* Register: NVMC_ERASEPAGE */
+/* Description: Register for erasing a page in Code area */
+
+/* Bits 31..0 : Register for starting erase of a page in Code area */
+#define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */
+#define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */
+
+/* Register: NVMC_ERASEPCR1 */
+/* Description: Deprecated register -  Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
+
+/* Bits 31..0 : Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
+#define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */
+#define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */
+
+/* Register: NVMC_ERASEALL */
+/* Description: Register for erasing all non-volatile user memory */
+
+/* Bit 0 : Erase all non-volatile memory including UICR registers. Note that the erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. */
+#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
+#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
+#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */
+#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */
+
+/* Register: NVMC_ERASEPCR0 */
+/* Description: Deprecated register -  Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
+
+/* Bits 31..0 : Register for starting erase of a page in Code area. Equivalent to ERASEPAGE. */
+#define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */
+#define NVMC_ERASEPCR0_ERASEPCR0_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos) /*!< Bit mask of ERASEPCR0 field. */
+
+/* Register: NVMC_ERASEUICR */
+/* Description: Register for erasing User Information Configuration Registers */
+
+/* Bit 0 : Register starting erase of all User Information Configuration Registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased. */
+#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */
+#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */
+#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation */
+#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start erase of UICR */
+
+/* Register: NVMC_ICACHECNF */
+/* Description: I-Code cache configuration register. */
+
+/* Bit 8 : Cache profiling enable */
+#define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */
+#define NVMC_ICACHECNF_CACHEPROFEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos) /*!< Bit mask of CACHEPROFEN field. */
+#define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0UL) /*!< Disable cache profiling */
+#define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL) /*!< Enable cache profiling */
+
+/* Bit 0 : Cache enable */
+#define NVMC_ICACHECNF_CACHEEN_Pos (0UL) /*!< Position of CACHEEN field. */
+#define NVMC_ICACHECNF_CACHEEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos) /*!< Bit mask of CACHEEN field. */
+#define NVMC_ICACHECNF_CACHEEN_Disabled (0UL) /*!< Disable cache. Invalidates all cache entries. */
+#define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */
+
+/* Register: NVMC_IHIT */
+/* Description: I-Code cache hit counter. */
+
+/* Bits 31..0 : Number of cache hits */
+#define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */
+#define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */
+
+/* Register: NVMC_IMISS */
+/* Description: I-Code cache miss counter. */
+
+/* Bits 31..0 : Number of cache misses */
+#define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */
+#define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */
+
+
+/* Peripheral: GPIO */
+/* Description: GPIO Port 1 */
+
+/* Register: GPIO_OUT */
+/* Description: Write GPIO port */
+
+/* Bit 31 : Pin 31 */
+#define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */
+
+/* Bit 30 : Pin 30 */
+#define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */
+
+/* Bit 29 : Pin 29 */
+#define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */
+
+/* Bit 28 : Pin 28 */
+#define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */
+
+/* Bit 27 : Pin 27 */
+#define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */
+
+/* Bit 26 : Pin 26 */
+#define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */
+
+/* Bit 25 : Pin 25 */
+#define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */
+
+/* Bit 24 : Pin 24 */
+#define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */
+
+/* Bit 23 : Pin 23 */
+#define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */
+
+/* Bit 22 : Pin 22 */
+#define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */
+
+/* Bit 21 : Pin 21 */
+#define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */
+
+/* Bit 20 : Pin 20 */
+#define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */
+
+/* Bit 19 : Pin 19 */
+#define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */
+
+/* Bit 18 : Pin 18 */
+#define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */
+
+/* Bit 17 : Pin 17 */
+#define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */
+
+/* Bit 16 : Pin 16 */
+#define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */
+
+/* Bit 15 : Pin 15 */
+#define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */
+
+/* Bit 14 : Pin 14 */
+#define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */
+
+/* Bit 13 : Pin 13 */
+#define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */
+
+/* Bit 12 : Pin 12 */
+#define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */
+
+/* Bit 11 : Pin 11 */
+#define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */
+
+/* Bit 10 : Pin 10 */
+#define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */
+
+/* Bit 9 : Pin 9 */
+#define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */
+
+/* Bit 8 : Pin 8 */
+#define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */
+
+/* Bit 7 : Pin 7 */
+#define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */
+
+/* Bit 6 : Pin 6 */
+#define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */
+
+/* Bit 5 : Pin 5 */
+#define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */
+
+/* Bit 4 : Pin 4 */
+#define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */
+
+/* Bit 3 : Pin 3 */
+#define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */
+
+/* Bit 2 : Pin 2 */
+#define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */
+
+/* Bit 1 : Pin 1 */
+#define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */
+
+/* Bit 0 : Pin 0 */
+#define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */
+
+/* Register: GPIO_OUTSET */
+/* Description: Set individual bits in GPIO port */
+
+/* Bit 31 : Pin 31 */
+#define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 30 : Pin 30 */
+#define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 29 : Pin 29 */
+#define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 28 : Pin 28 */
+#define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 27 : Pin 27 */
+#define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 26 : Pin 26 */
+#define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 25 : Pin 25 */
+#define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 24 : Pin 24 */
+#define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 23 : Pin 23 */
+#define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 22 : Pin 22 */
+#define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 21 : Pin 21 */
+#define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 20 : Pin 20 */
+#define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 19 : Pin 19 */
+#define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 18 : Pin 18 */
+#define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 17 : Pin 17 */
+#define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 16 : Pin 16 */
+#define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 15 : Pin 15 */
+#define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 14 : Pin 14 */
+#define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 13 : Pin 13 */
+#define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 12 : Pin 12 */
+#define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 11 : Pin 11 */
+#define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 10 : Pin 10 */
+#define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 9 : Pin 9 */
+#define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 8 : Pin 8 */
+#define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 7 : Pin 7 */
+#define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 6 : Pin 6 */
+#define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 5 : Pin 5 */
+#define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 4 : Pin 4 */
+#define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 3 : Pin 3 */
+#define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 2 : Pin 2 */
+#define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 1 : Pin 1 */
+#define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 0 : Pin 0 */
+#define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Register: GPIO_OUTCLR */
+/* Description: Clear individual bits in GPIO port */
+
+/* Bit 31 : Pin 31 */
+#define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 30 : Pin 30 */
+#define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 29 : Pin 29 */
+#define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 28 : Pin 28 */
+#define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 27 : Pin 27 */
+#define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 26 : Pin 26 */
+#define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 25 : Pin 25 */
+#define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 24 : Pin 24 */
+#define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 23 : Pin 23 */
+#define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 22 : Pin 22 */
+#define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 21 : Pin 21 */
+#define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 20 : Pin 20 */
+#define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 19 : Pin 19 */
+#define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 18 : Pin 18 */
+#define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 17 : Pin 17 */
+#define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 16 : Pin 16 */
+#define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 15 : Pin 15 */
+#define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 14 : Pin 14 */
+#define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 13 : Pin 13 */
+#define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 12 : Pin 12 */
+#define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 11 : Pin 11 */
+#define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 10 : Pin 10 */
+#define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 9 : Pin 9 */
+#define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 8 : Pin 8 */
+#define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 7 : Pin 7 */
+#define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 6 : Pin 6 */
+#define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 5 : Pin 5 */
+#define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 4 : Pin 4 */
+#define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 3 : Pin 3 */
+#define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 2 : Pin 2 */
+#define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 1 : Pin 1 */
+#define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 0 : Pin 0 */
+#define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Register: GPIO_IN */
+/* Description: Read GPIO port */
+
+/* Bit 31 : Pin 31 */
+#define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */
+
+/* Bit 30 : Pin 30 */
+#define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */
+
+/* Bit 29 : Pin 29 */
+#define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */
+
+/* Bit 28 : Pin 28 */
+#define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */
+
+/* Bit 27 : Pin 27 */
+#define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */
+
+/* Bit 26 : Pin 26 */
+#define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */
+
+/* Bit 25 : Pin 25 */
+#define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */
+
+/* Bit 24 : Pin 24 */
+#define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */
+
+/* Bit 23 : Pin 23 */
+#define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */
+
+/* Bit 22 : Pin 22 */
+#define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */
+
+/* Bit 21 : Pin 21 */
+#define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */
+
+/* Bit 20 : Pin 20 */
+#define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */
+
+/* Bit 19 : Pin 19 */
+#define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */
+
+/* Bit 18 : Pin 18 */
+#define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */
+
+/* Bit 17 : Pin 17 */
+#define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */
+
+/* Bit 16 : Pin 16 */
+#define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */
+
+/* Bit 15 : Pin 15 */
+#define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */
+
+/* Bit 14 : Pin 14 */
+#define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */
+
+/* Bit 13 : Pin 13 */
+#define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */
+
+/* Bit 12 : Pin 12 */
+#define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */
+
+/* Bit 11 : Pin 11 */
+#define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */
+
+/* Bit 10 : Pin 10 */
+#define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */
+
+/* Bit 9 : Pin 9 */
+#define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */
+
+/* Bit 8 : Pin 8 */
+#define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */
+
+/* Bit 7 : Pin 7 */
+#define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */
+
+/* Bit 6 : Pin 6 */
+#define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */
+
+/* Bit 5 : Pin 5 */
+#define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */
+
+/* Bit 4 : Pin 4 */
+#define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */
+
+/* Bit 3 : Pin 3 */
+#define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */
+
+/* Bit 2 : Pin 2 */
+#define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */
+
+/* Bit 1 : Pin 1 */
+#define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */
+
+/* Bit 0 : Pin 0 */
+#define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */
+
+/* Register: GPIO_DIR */
+/* Description: Direction of GPIO pins */
+
+/* Bit 31 : Pin 31 */
+#define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */
+
+/* Bit 30 : Pin 30 */
+#define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */
+
+/* Bit 29 : Pin 29 */
+#define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */
+
+/* Bit 28 : Pin 28 */
+#define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */
+
+/* Bit 27 : Pin 27 */
+#define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */
+
+/* Bit 26 : Pin 26 */
+#define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */
+
+/* Bit 25 : Pin 25 */
+#define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */
+
+/* Bit 24 : Pin 24 */
+#define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */
+
+/* Bit 23 : Pin 23 */
+#define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */
+
+/* Bit 22 : Pin 22 */
+#define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */
+
+/* Bit 21 : Pin 21 */
+#define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */
+
+/* Bit 20 : Pin 20 */
+#define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */
+
+/* Bit 19 : Pin 19 */
+#define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */
+
+/* Bit 18 : Pin 18 */
+#define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */
+
+/* Bit 17 : Pin 17 */
+#define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */
+
+/* Bit 16 : Pin 16 */
+#define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */
+
+/* Bit 15 : Pin 15 */
+#define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */
+
+/* Bit 14 : Pin 14 */
+#define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */
+
+/* Bit 13 : Pin 13 */
+#define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */
+
+/* Bit 12 : Pin 12 */
+#define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */
+
+/* Bit 11 : Pin 11 */
+#define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */
+
+/* Bit 10 : Pin 10 */
+#define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */
+
+/* Bit 9 : Pin 9 */
+#define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */
+
+/* Bit 8 : Pin 8 */
+#define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */
+
+/* Bit 7 : Pin 7 */
+#define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */
+
+/* Bit 6 : Pin 6 */
+#define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */
+
+/* Bit 5 : Pin 5 */
+#define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */
+
+/* Bit 4 : Pin 4 */
+#define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */
+
+/* Bit 3 : Pin 3 */
+#define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */
+
+/* Bit 2 : Pin 2 */
+#define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */
+
+/* Bit 1 : Pin 1 */
+#define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */
+
+/* Bit 0 : Pin 0 */
+#define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */
+
+/* Register: GPIO_DIRSET */
+/* Description: DIR set register */
+
+/* Bit 31 : Set as output pin 31 */
+#define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 30 : Set as output pin 30 */
+#define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 29 : Set as output pin 29 */
+#define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 28 : Set as output pin 28 */
+#define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 27 : Set as output pin 27 */
+#define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 26 : Set as output pin 26 */
+#define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 25 : Set as output pin 25 */
+#define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 24 : Set as output pin 24 */
+#define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 23 : Set as output pin 23 */
+#define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 22 : Set as output pin 22 */
+#define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 21 : Set as output pin 21 */
+#define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 20 : Set as output pin 20 */
+#define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 19 : Set as output pin 19 */
+#define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 18 : Set as output pin 18 */
+#define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 17 : Set as output pin 17 */
+#define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 16 : Set as output pin 16 */
+#define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 15 : Set as output pin 15 */
+#define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 14 : Set as output pin 14 */
+#define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 13 : Set as output pin 13 */
+#define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 12 : Set as output pin 12 */
+#define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 11 : Set as output pin 11 */
+#define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 10 : Set as output pin 10 */
+#define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 9 : Set as output pin 9 */
+#define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 8 : Set as output pin 8 */
+#define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 7 : Set as output pin 7 */
+#define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 6 : Set as output pin 6 */
+#define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 5 : Set as output pin 5 */
+#define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 4 : Set as output pin 4 */
+#define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 3 : Set as output pin 3 */
+#define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 2 : Set as output pin 2 */
+#define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 1 : Set as output pin 1 */
+#define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 0 : Set as output pin 0 */
+#define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Register: GPIO_DIRCLR */
+/* Description: DIR clear register */
+
+/* Bit 31 : Set as input pin 31 */
+#define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 30 : Set as input pin 30 */
+#define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 29 : Set as input pin 29 */
+#define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 28 : Set as input pin 28 */
+#define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 27 : Set as input pin 27 */
+#define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 26 : Set as input pin 26 */
+#define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 25 : Set as input pin 25 */
+#define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 24 : Set as input pin 24 */
+#define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 23 : Set as input pin 23 */
+#define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 22 : Set as input pin 22 */
+#define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 21 : Set as input pin 21 */
+#define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 20 : Set as input pin 20 */
+#define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 19 : Set as input pin 19 */
+#define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 18 : Set as input pin 18 */
+#define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 17 : Set as input pin 17 */
+#define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 16 : Set as input pin 16 */
+#define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 15 : Set as input pin 15 */
+#define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 14 : Set as input pin 14 */
+#define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 13 : Set as input pin 13 */
+#define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 12 : Set as input pin 12 */
+#define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 11 : Set as input pin 11 */
+#define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 10 : Set as input pin 10 */
+#define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 9 : Set as input pin 9 */
+#define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 8 : Set as input pin 8 */
+#define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 7 : Set as input pin 7 */
+#define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 6 : Set as input pin 6 */
+#define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 5 : Set as input pin 5 */
+#define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 4 : Set as input pin 4 */
+#define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 3 : Set as input pin 3 */
+#define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 2 : Set as input pin 2 */
+#define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 1 : Set as input pin 1 */
+#define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 0 : Set as input pin 0 */
+#define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Register: GPIO_LATCH */
+/* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */
+
+/* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */
+
+/* Register: GPIO_DETECTMODE */
+/* Description: Select between default DETECT signal behaviour and LDETECT mode */
+
+/* Bit 0 : Select between default DETECT signal behaviour and LDETECT mode */
+#define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */
+#define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */
+#define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */
+#define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */
+
+/* Register: GPIO_PIN_CNF */
+/* Description: Description collection[0]:  Configuration of GPIO pins */
+
+/* Bits 17..16 : Pin sensing mechanism */
+#define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
+#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
+#define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */
+#define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */
+#define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */
+
+/* Bits 10..8 : Drive configuration */
+#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
+#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
+#define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */
+#define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */
+#define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */
+#define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */
+#define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or connections) */
+#define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */
+#define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-and connections) */
+#define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */
+
+/* Bits 3..2 : Pull configuration */
+#define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
+#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
+#define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */
+#define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */
+#define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */
+
+/* Bit 1 : Connect or disconnect input buffer */
+#define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
+#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
+#define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */
+#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */
+
+/* Bit 0 : Pin direction. Same physical register as DIR register */
+#define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
+#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
+#define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */
+#define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */
+
+
+/* Peripheral: PDM */
+/* Description: Pulse Density Modulation (Digital Microphone) Interface */
+
+/* Register: PDM_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 2 : Enable or disable interrupt for END event */
+#define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */
+#define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */
+#define PDM_INTEN_END_Disabled (0UL) /*!< Disable */
+#define PDM_INTEN_END_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for STOPPED event */
+#define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for STARTED event */
+#define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */
+#define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */
+
+/* Register: PDM_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 2 : Write '1' to Enable interrupt for END event */
+#define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */
+#define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define PDM_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
+#define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for STARTED event */
+#define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */
+
+/* Register: PDM_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 2 : Write '1' to Disable interrupt for END event */
+#define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */
+#define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
+#define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for STARTED event */
+#define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
+
+/* Register: PDM_ENABLE */
+/* Description: PDM module enable register */
+
+/* Bit 0 : Enable or disable PDM module */
+#define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
+
+/* Register: PDM_PDMCLKCTRL */
+/* Description: PDM clock generator control */
+
+/* Bits 31..0 : PDM_CLK frequency */
+#define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */
+#define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */
+#define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */
+#define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. */
+#define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz */
+#define PDM_PDMCLKCTRL_FREQ_1231K (0x09800000UL) /*!< PDM_CLK = 32 MHz / 26 = 1.231 MHz */
+#define PDM_PDMCLKCTRL_FREQ_1280K (0x0A000000UL) /*!< PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. */
+#define PDM_PDMCLKCTRL_FREQ_1333K (0x0A800000UL) /*!< PDM_CLK = 32 MHz / 24 = 1.333 MHz */
+
+/* Register: PDM_MODE */
+/* Description: Defines the routing of the connected PDM microphones' signals */
+
+/* Bit 1 : Defines on which PDM_CLK edge Left (or mono) is sampled */
+#define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */
+#define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */
+#define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */
+#define PDM_MODE_EDGE_LeftRising (1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */
+
+/* Bit 0 : Mono or stereo operation */
+#define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */
+#define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */
+#define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] */
+#define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] */
+
+/* Register: PDM_GAINL */
+/* Description: Left output gain adjustment */
+
+/* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00    -20 dB gain adjust 0x01  -19.5 dB gain adjust (...) 0x27   -0.5 dB gain adjust 0x28      0 dB gain adjust 0x29   +0.5 dB gain adjust (...) 0x4F  +19.5 dB gain adjust 0x50    +20 dB gain adjust */
+#define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */
+#define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */
+#define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
+#define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */
+#define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */
+
+/* Register: PDM_GAINR */
+/* Description: Right output gain adjustment */
+
+/* Bits 7..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */
+#define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */
+#define PDM_GAINR_GAINR_Msk (0xFFUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */
+#define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
+#define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */
+#define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */
+
+/* Register: PDM_RATIO */
+/* Description: Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. */
+
+/* Bit 0 : Selects the ratio between PDM_CLK and output sample rate */
+#define PDM_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */
+#define PDM_RATIO_RATIO_Msk (0x1UL << PDM_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */
+#define PDM_RATIO_RATIO_Ratio64 (0UL) /*!< Ratio of 64 */
+#define PDM_RATIO_RATIO_Ratio80 (1UL) /*!< Ratio of 80 */
+
+/* Register: PDM_PSEL_CLK */
+/* Description: Pin number configuration for PDM CLK signal */
+
+/* Bit 31 : Connection */
+#define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define PDM_PSEL_CLK_CONNECT_Connected (0UL) /*!< Connect */
+#define PDM_PSEL_CLK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define PDM_PSEL_CLK_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define PDM_PSEL_CLK_PORT_Msk (0x3UL << PDM_PSEL_CLK_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: PDM_PSEL_DIN */
+/* Description: Pin number configuration for PDM DIN signal */
+
+/* Bit 31 : Connection */
+#define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define PDM_PSEL_DIN_CONNECT_Connected (0UL) /*!< Connect */
+#define PDM_PSEL_DIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define PDM_PSEL_DIN_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define PDM_PSEL_DIN_PORT_Msk (0x3UL << PDM_PSEL_DIN_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: PDM_SAMPLE_PTR */
+/* Description: RAM address pointer to write samples to with EasyDMA */
+
+/* Bits 31..0 : Address to write PDM samples to over DMA */
+#define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */
+#define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */
+
+/* Register: PDM_SAMPLE_MAXCNT */
+/* Description: Number of samples to allocate memory for in EasyDMA mode */
+
+/* Bits 14..0 : Length of DMA RAM allocation in number of samples */
+#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */
+#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */
+
+
+/* Peripheral: POWER */
+/* Description: Power control */
+
+/* Register: POWER_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 9 : Write '1' to Enable interrupt for USBPWRRDY event */
+#define POWER_INTENSET_USBPWRRDY_Pos (9UL) /*!< Position of USBPWRRDY field. */
+#define POWER_INTENSET_USBPWRRDY_Msk (0x1UL << POWER_INTENSET_USBPWRRDY_Pos) /*!< Bit mask of USBPWRRDY field. */
+#define POWER_INTENSET_USBPWRRDY_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENSET_USBPWRRDY_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENSET_USBPWRRDY_Set (1UL) /*!< Enable */
+
+/* Bit 8 : Write '1' to Enable interrupt for USBREMOVED event */
+#define POWER_INTENSET_USBREMOVED_Pos (8UL) /*!< Position of USBREMOVED field. */
+#define POWER_INTENSET_USBREMOVED_Msk (0x1UL << POWER_INTENSET_USBREMOVED_Pos) /*!< Bit mask of USBREMOVED field. */
+#define POWER_INTENSET_USBREMOVED_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENSET_USBREMOVED_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENSET_USBREMOVED_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for USBDETECTED event */
+#define POWER_INTENSET_USBDETECTED_Pos (7UL) /*!< Position of USBDETECTED field. */
+#define POWER_INTENSET_USBDETECTED_Msk (0x1UL << POWER_INTENSET_USBDETECTED_Pos) /*!< Bit mask of USBDETECTED field. */
+#define POWER_INTENSET_USBDETECTED_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENSET_USBDETECTED_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENSET_USBDETECTED_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for SLEEPEXIT event */
+#define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
+#define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
+#define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable interrupt for SLEEPENTER event */
+#define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
+#define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
+#define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for POFWARN event */
+#define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
+#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
+#define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */
+
+/* Register: POWER_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 9 : Write '1' to Disable interrupt for USBPWRRDY event */
+#define POWER_INTENCLR_USBPWRRDY_Pos (9UL) /*!< Position of USBPWRRDY field. */
+#define POWER_INTENCLR_USBPWRRDY_Msk (0x1UL << POWER_INTENCLR_USBPWRRDY_Pos) /*!< Bit mask of USBPWRRDY field. */
+#define POWER_INTENCLR_USBPWRRDY_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENCLR_USBPWRRDY_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENCLR_USBPWRRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 8 : Write '1' to Disable interrupt for USBREMOVED event */
+#define POWER_INTENCLR_USBREMOVED_Pos (8UL) /*!< Position of USBREMOVED field. */
+#define POWER_INTENCLR_USBREMOVED_Msk (0x1UL << POWER_INTENCLR_USBREMOVED_Pos) /*!< Bit mask of USBREMOVED field. */
+#define POWER_INTENCLR_USBREMOVED_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENCLR_USBREMOVED_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENCLR_USBREMOVED_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for USBDETECTED event */
+#define POWER_INTENCLR_USBDETECTED_Pos (7UL) /*!< Position of USBDETECTED field. */
+#define POWER_INTENCLR_USBDETECTED_Msk (0x1UL << POWER_INTENCLR_USBDETECTED_Pos) /*!< Bit mask of USBDETECTED field. */
+#define POWER_INTENCLR_USBDETECTED_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENCLR_USBDETECTED_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENCLR_USBDETECTED_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for SLEEPEXIT event */
+#define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
+#define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
+#define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable interrupt for SLEEPENTER event */
+#define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
+#define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
+#define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for POFWARN event */
+#define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
+#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
+#define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */
+
+/* Register: POWER_RESETREAS */
+/* Description: Reset reason */
+
+/* Bit 20 : Reset due to wake up from System OFF mode by Vbus rising into valid range */
+#define POWER_RESETREAS_VBUS_Pos (20UL) /*!< Position of VBUS field. */
+#define POWER_RESETREAS_VBUS_Msk (0x1UL << POWER_RESETREAS_VBUS_Pos) /*!< Bit mask of VBUS field. */
+#define POWER_RESETREAS_VBUS_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_VBUS_Detected (1UL) /*!< Detected */
+
+/* Bit 19 : Reset due to wake up from System OFF mode by NFC field detect */
+#define POWER_RESETREAS_NFC_Pos (19UL) /*!< Position of NFC field. */
+#define POWER_RESETREAS_NFC_Msk (0x1UL << POWER_RESETREAS_NFC_Pos) /*!< Bit mask of NFC field. */
+#define POWER_RESETREAS_NFC_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_NFC_Detected (1UL) /*!< Detected */
+
+/* Bit 18 : Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode */
+#define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */
+#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
+#define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */
+
+/* Bit 17 : Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP */
+#define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */
+#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
+#define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Detected */
+
+/* Bit 16 : Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO */
+#define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */
+#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
+#define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */
+
+/* Bit 3 : Reset from CPU lock-up detected */
+#define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */
+#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
+#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */
+
+/* Bit 2 : Reset from soft reset detected */
+#define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
+#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
+#define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */
+
+/* Bit 1 : Reset from watchdog detected */
+#define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
+#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
+#define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */
+
+/* Bit 0 : Reset from pin-reset detected */
+#define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
+#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
+#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */
+
+/* Register: POWER_RAMSTATUS */
+/* Description: Deprecated register -  RAM status register */
+
+/* Bit 3 : RAM block 3 is on or off/powering up */
+#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */
+#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */
+#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< Off */
+#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< On */
+
+/* Bit 2 : RAM block 2 is on or off/powering up */
+#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */
+#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */
+#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< Off */
+#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< On */
+
+/* Bit 1 : RAM block 1 is on or off/powering up */
+#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */
+#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */
+#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< Off */
+#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< On */
+
+/* Bit 0 : RAM block 0 is on or off/powering up */
+#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */
+#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */
+#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< Off */
+#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< On */
+
+/* Register: POWER_USBREGSTATUS */
+/* Description: USB supply status */
+
+/* Bit 1 : USB supply output settling time elapsed */
+#define POWER_USBREGSTATUS_OUTPUTRDY_Pos (1UL) /*!< Position of OUTPUTRDY field. */
+#define POWER_USBREGSTATUS_OUTPUTRDY_Msk (0x1UL << POWER_USBREGSTATUS_OUTPUTRDY_Pos) /*!< Bit mask of OUTPUTRDY field. */
+#define POWER_USBREGSTATUS_OUTPUTRDY_NotReady (0UL) /*!< USBREG output settling time not elapsed */
+#define POWER_USBREGSTATUS_OUTPUTRDY_Ready (1UL) /*!< USBREG output settling time elapsed (same information as USBPWRRDY event) */
+
+/* Bit 0 : VBUS input detection status (USBDETECTED and USBREMOVED events are derived from this information) */
+#define POWER_USBREGSTATUS_VBUSDETECT_Pos (0UL) /*!< Position of VBUSDETECT field. */
+#define POWER_USBREGSTATUS_VBUSDETECT_Msk (0x1UL << POWER_USBREGSTATUS_VBUSDETECT_Pos) /*!< Bit mask of VBUSDETECT field. */
+#define POWER_USBREGSTATUS_VBUSDETECT_NoVbus (0UL) /*!< VBUS voltage below valid threshold */
+#define POWER_USBREGSTATUS_VBUSDETECT_VbusPresent (1UL) /*!< VBUS voltage above valid threshold */
+
+/* Register: POWER_SYSTEMOFF */
+/* Description: System OFF register */
+
+/* Bit 0 : Enable System OFF mode */
+#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
+#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
+#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */
+
+/* Register: POWER_POFCON */
+/* Description: Power failure comparator configuration */
+
+/* Bits 11..8 : Power failure comparator threshold setting for voltage supply on VDDH */
+#define POWER_POFCON_THRESHOLDVDDH_Pos (8UL) /*!< Position of THRESHOLDVDDH field. */
+#define POWER_POFCON_THRESHOLDVDDH_Msk (0xFUL << POWER_POFCON_THRESHOLDVDDH_Pos) /*!< Bit mask of THRESHOLDVDDH field. */
+#define POWER_POFCON_THRESHOLDVDDH_V27 (0UL) /*!< Set threshold to 2.7 V */
+#define POWER_POFCON_THRESHOLDVDDH_V28 (1UL) /*!< Set threshold to 2.8 V */
+#define POWER_POFCON_THRESHOLDVDDH_V29 (2UL) /*!< Set threshold to 2.9 V */
+#define POWER_POFCON_THRESHOLDVDDH_V30 (3UL) /*!< Set threshold to 3.0 V */
+#define POWER_POFCON_THRESHOLDVDDH_V31 (4UL) /*!< Set threshold to 3.1 V */
+#define POWER_POFCON_THRESHOLDVDDH_V32 (5UL) /*!< Set threshold to 3.2 V */
+#define POWER_POFCON_THRESHOLDVDDH_V33 (6UL) /*!< Set threshold to 3.3 V */
+#define POWER_POFCON_THRESHOLDVDDH_V34 (7UL) /*!< Set threshold to 3.4 V */
+#define POWER_POFCON_THRESHOLDVDDH_V35 (8UL) /*!< Set threshold to 3.5 V */
+#define POWER_POFCON_THRESHOLDVDDH_V36 (9UL) /*!< Set threshold to 3.6 V */
+#define POWER_POFCON_THRESHOLDVDDH_V37 (10UL) /*!< Set threshold to 3.7 V */
+#define POWER_POFCON_THRESHOLDVDDH_V38 (11UL) /*!< Set threshold to 3.8 V */
+#define POWER_POFCON_THRESHOLDVDDH_V39 (12UL) /*!< Set threshold to 3.9 V */
+#define POWER_POFCON_THRESHOLDVDDH_V40 (13UL) /*!< Set threshold to 4.0 V */
+#define POWER_POFCON_THRESHOLDVDDH_V41 (14UL) /*!< Set threshold to 4.1 V */
+#define POWER_POFCON_THRESHOLDVDDH_V42 (15UL) /*!< Set threshold to 4.2 V */
+
+/* Bits 4..1 : Power failure comparator threshold setting */
+#define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
+#define POWER_POFCON_THRESHOLD_Msk (0xFUL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
+#define POWER_POFCON_THRESHOLD_V17 (4UL) /*!< Set threshold to 1.7 V */
+#define POWER_POFCON_THRESHOLD_V18 (5UL) /*!< Set threshold to 1.8 V */
+#define POWER_POFCON_THRESHOLD_V19 (6UL) /*!< Set threshold to 1.9 V */
+#define POWER_POFCON_THRESHOLD_V20 (7UL) /*!< Set threshold to 2.0 V */
+#define POWER_POFCON_THRESHOLD_V21 (8UL) /*!< Set threshold to 2.1 V */
+#define POWER_POFCON_THRESHOLD_V22 (9UL) /*!< Set threshold to 2.2 V */
+#define POWER_POFCON_THRESHOLD_V23 (10UL) /*!< Set threshold to 2.3 V */
+#define POWER_POFCON_THRESHOLD_V24 (11UL) /*!< Set threshold to 2.4 V */
+#define POWER_POFCON_THRESHOLD_V25 (12UL) /*!< Set threshold to 2.5 V */
+#define POWER_POFCON_THRESHOLD_V26 (13UL) /*!< Set threshold to 2.6 V */
+#define POWER_POFCON_THRESHOLD_V27 (14UL) /*!< Set threshold to 2.7 V */
+#define POWER_POFCON_THRESHOLD_V28 (15UL) /*!< Set threshold to 2.8 V */
+
+/* Bit 0 : Enable or disable power failure comparator */
+#define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
+#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */
+#define POWER_POFCON_POF_Disabled (0UL) /*!< Disable */
+#define POWER_POFCON_POF_Enabled (1UL) /*!< Enable */
+
+/* Register: POWER_GPREGRET */
+/* Description: General purpose retention register */
+
+/* Bits 7..0 : General purpose retention register */
+#define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
+#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
+
+/* Register: POWER_GPREGRET2 */
+/* Description: General purpose retention register */
+
+/* Bits 7..0 : General purpose retention register */
+#define POWER_GPREGRET2_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
+#define POWER_GPREGRET2_GPREGRET_Msk (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
+
+/* Register: POWER_DCDCEN */
+/* Description: Enable DC/DC converter for REG1 stage. */
+
+/* Bit 0 : Enable DC/DC converter for REG1 stage. */
+#define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
+#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
+#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< Disable */
+#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */
+
+/* Register: POWER_DCDCEN0 */
+/* Description: Enable DC/DC converter for REG0 stage. */
+
+/* Bit 0 : Enable DC/DC converter for REG0 stage. */
+#define POWER_DCDCEN0_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
+#define POWER_DCDCEN0_DCDCEN_Msk (0x1UL << POWER_DCDCEN0_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
+#define POWER_DCDCEN0_DCDCEN_Disabled (0UL) /*!< Disable */
+#define POWER_DCDCEN0_DCDCEN_Enabled (1UL) /*!< Enable */
+
+/* Register: POWER_MAINREGSTATUS */
+/* Description: Main supply status */
+
+/* Bit 0 : Main supply status */
+#define POWER_MAINREGSTATUS_MAINREGSTATUS_Pos (0UL) /*!< Position of MAINREGSTATUS field. */
+#define POWER_MAINREGSTATUS_MAINREGSTATUS_Msk (0x1UL << POWER_MAINREGSTATUS_MAINREGSTATUS_Pos) /*!< Bit mask of MAINREGSTATUS field. */
+#define POWER_MAINREGSTATUS_MAINREGSTATUS_Normal (0UL) /*!< Normal voltage mode. Voltage supplied on VDD. */
+#define POWER_MAINREGSTATUS_MAINREGSTATUS_High (1UL) /*!< High voltage mode. Voltage supplied on VDDH. */
+
+/* Register: POWER_RAM_POWER */
+/* Description: Description cluster[0]:  RAM0 power control register */
+
+/* Bit 31 : Keep retention on RAM section S15 when RAM section is in OFF */
+#define POWER_RAM_POWER_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */
+#define POWER_RAM_POWER_S15RETENTION_Msk (0x1UL << POWER_RAM_POWER_S15RETENTION_Pos) /*!< Bit mask of S15RETENTION field. */
+#define POWER_RAM_POWER_S15RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S15RETENTION_On (1UL) /*!< On */
+
+/* Bit 30 : Keep retention on RAM section S14 when RAM section is in OFF */
+#define POWER_RAM_POWER_S14RETENTION_Pos (30UL) /*!< Position of S14RETENTION field. */
+#define POWER_RAM_POWER_S14RETENTION_Msk (0x1UL << POWER_RAM_POWER_S14RETENTION_Pos) /*!< Bit mask of S14RETENTION field. */
+#define POWER_RAM_POWER_S14RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S14RETENTION_On (1UL) /*!< On */
+
+/* Bit 29 : Keep retention on RAM section S13 when RAM section is in OFF */
+#define POWER_RAM_POWER_S13RETENTION_Pos (29UL) /*!< Position of S13RETENTION field. */
+#define POWER_RAM_POWER_S13RETENTION_Msk (0x1UL << POWER_RAM_POWER_S13RETENTION_Pos) /*!< Bit mask of S13RETENTION field. */
+#define POWER_RAM_POWER_S13RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S13RETENTION_On (1UL) /*!< On */
+
+/* Bit 28 : Keep retention on RAM section S12 when RAM section is in OFF */
+#define POWER_RAM_POWER_S12RETENTION_Pos (28UL) /*!< Position of S12RETENTION field. */
+#define POWER_RAM_POWER_S12RETENTION_Msk (0x1UL << POWER_RAM_POWER_S12RETENTION_Pos) /*!< Bit mask of S12RETENTION field. */
+#define POWER_RAM_POWER_S12RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S12RETENTION_On (1UL) /*!< On */
+
+/* Bit 27 : Keep retention on RAM section S11 when RAM section is in OFF */
+#define POWER_RAM_POWER_S11RETENTION_Pos (27UL) /*!< Position of S11RETENTION field. */
+#define POWER_RAM_POWER_S11RETENTION_Msk (0x1UL << POWER_RAM_POWER_S11RETENTION_Pos) /*!< Bit mask of S11RETENTION field. */
+#define POWER_RAM_POWER_S11RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S11RETENTION_On (1UL) /*!< On */
+
+/* Bit 26 : Keep retention on RAM section S10 when RAM section is in OFF */
+#define POWER_RAM_POWER_S10RETENTION_Pos (26UL) /*!< Position of S10RETENTION field. */
+#define POWER_RAM_POWER_S10RETENTION_Msk (0x1UL << POWER_RAM_POWER_S10RETENTION_Pos) /*!< Bit mask of S10RETENTION field. */
+#define POWER_RAM_POWER_S10RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S10RETENTION_On (1UL) /*!< On */
+
+/* Bit 25 : Keep retention on RAM section S9 when RAM section is in OFF */
+#define POWER_RAM_POWER_S9RETENTION_Pos (25UL) /*!< Position of S9RETENTION field. */
+#define POWER_RAM_POWER_S9RETENTION_Msk (0x1UL << POWER_RAM_POWER_S9RETENTION_Pos) /*!< Bit mask of S9RETENTION field. */
+#define POWER_RAM_POWER_S9RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S9RETENTION_On (1UL) /*!< On */
+
+/* Bit 24 : Keep retention on RAM section S8 when RAM section is in OFF */
+#define POWER_RAM_POWER_S8RETENTION_Pos (24UL) /*!< Position of S8RETENTION field. */
+#define POWER_RAM_POWER_S8RETENTION_Msk (0x1UL << POWER_RAM_POWER_S8RETENTION_Pos) /*!< Bit mask of S8RETENTION field. */
+#define POWER_RAM_POWER_S8RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S8RETENTION_On (1UL) /*!< On */
+
+/* Bit 23 : Keep retention on RAM section S7 when RAM section is in OFF */
+#define POWER_RAM_POWER_S7RETENTION_Pos (23UL) /*!< Position of S7RETENTION field. */
+#define POWER_RAM_POWER_S7RETENTION_Msk (0x1UL << POWER_RAM_POWER_S7RETENTION_Pos) /*!< Bit mask of S7RETENTION field. */
+#define POWER_RAM_POWER_S7RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S7RETENTION_On (1UL) /*!< On */
+
+/* Bit 22 : Keep retention on RAM section S6 when RAM section is in OFF */
+#define POWER_RAM_POWER_S6RETENTION_Pos (22UL) /*!< Position of S6RETENTION field. */
+#define POWER_RAM_POWER_S6RETENTION_Msk (0x1UL << POWER_RAM_POWER_S6RETENTION_Pos) /*!< Bit mask of S6RETENTION field. */
+#define POWER_RAM_POWER_S6RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S6RETENTION_On (1UL) /*!< On */
+
+/* Bit 21 : Keep retention on RAM section S5 when RAM section is in OFF */
+#define POWER_RAM_POWER_S5RETENTION_Pos (21UL) /*!< Position of S5RETENTION field. */
+#define POWER_RAM_POWER_S5RETENTION_Msk (0x1UL << POWER_RAM_POWER_S5RETENTION_Pos) /*!< Bit mask of S5RETENTION field. */
+#define POWER_RAM_POWER_S5RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S5RETENTION_On (1UL) /*!< On */
+
+/* Bit 20 : Keep retention on RAM section S4 when RAM section is in OFF */
+#define POWER_RAM_POWER_S4RETENTION_Pos (20UL) /*!< Position of S4RETENTION field. */
+#define POWER_RAM_POWER_S4RETENTION_Msk (0x1UL << POWER_RAM_POWER_S4RETENTION_Pos) /*!< Bit mask of S4RETENTION field. */
+#define POWER_RAM_POWER_S4RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S4RETENTION_On (1UL) /*!< On */
+
+/* Bit 19 : Keep retention on RAM section S3 when RAM section is in OFF */
+#define POWER_RAM_POWER_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */
+#define POWER_RAM_POWER_S3RETENTION_Msk (0x1UL << POWER_RAM_POWER_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */
+#define POWER_RAM_POWER_S3RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S3RETENTION_On (1UL) /*!< On */
+
+/* Bit 18 : Keep retention on RAM section S2 when RAM section is in OFF */
+#define POWER_RAM_POWER_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */
+#define POWER_RAM_POWER_S2RETENTION_Msk (0x1UL << POWER_RAM_POWER_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */
+#define POWER_RAM_POWER_S2RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S2RETENTION_On (1UL) /*!< On */
+
+/* Bit 17 : Keep retention on RAM section S1 when RAM section is in OFF */
+#define POWER_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
+#define POWER_RAM_POWER_S1RETENTION_Msk (0x1UL << POWER_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
+#define POWER_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S1RETENTION_On (1UL) /*!< On */
+
+/* Bit 16 : Keep retention on RAM section S0 when RAM section is in OFF */
+#define POWER_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
+#define POWER_RAM_POWER_S0RETENTION_Msk (0x1UL << POWER_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
+#define POWER_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S0RETENTION_On (1UL) /*!< On */
+
+/* Bit 15 : Keep RAM section S15 ON or OFF in System ON mode. */
+#define POWER_RAM_POWER_S15POWER_Pos (15UL) /*!< Position of S15POWER field. */
+#define POWER_RAM_POWER_S15POWER_Msk (0x1UL << POWER_RAM_POWER_S15POWER_Pos) /*!< Bit mask of S15POWER field. */
+#define POWER_RAM_POWER_S15POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S15POWER_On (1UL) /*!< On */
+
+/* Bit 14 : Keep RAM section S14 ON or OFF in System ON mode. */
+#define POWER_RAM_POWER_S14POWER_Pos (14UL) /*!< Position of S14POWER field. */
+#define POWER_RAM_POWER_S14POWER_Msk (0x1UL << POWER_RAM_POWER_S14POWER_Pos) /*!< Bit mask of S14POWER field. */
+#define POWER_RAM_POWER_S14POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S14POWER_On (1UL) /*!< On */
+
+/* Bit 13 : Keep RAM section S13 ON or OFF in System ON mode. */
+#define POWER_RAM_POWER_S13POWER_Pos (13UL) /*!< Position of S13POWER field. */
+#define POWER_RAM_POWER_S13POWER_Msk (0x1UL << POWER_RAM_POWER_S13POWER_Pos) /*!< Bit mask of S13POWER field. */
+#define POWER_RAM_POWER_S13POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S13POWER_On (1UL) /*!< On */
+
+/* Bit 12 : Keep RAM section S12 ON or OFF in System ON mode. */
+#define POWER_RAM_POWER_S12POWER_Pos (12UL) /*!< Position of S12POWER field. */
+#define POWER_RAM_POWER_S12POWER_Msk (0x1UL << POWER_RAM_POWER_S12POWER_Pos) /*!< Bit mask of S12POWER field. */
+#define POWER_RAM_POWER_S12POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S12POWER_On (1UL) /*!< On */
+
+/* Bit 11 : Keep RAM section S11 ON or OFF in System ON mode. */
+#define POWER_RAM_POWER_S11POWER_Pos (11UL) /*!< Position of S11POWER field. */
+#define POWER_RAM_POWER_S11POWER_Msk (0x1UL << POWER_RAM_POWER_S11POWER_Pos) /*!< Bit mask of S11POWER field. */
+#define POWER_RAM_POWER_S11POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S11POWER_On (1UL) /*!< On */
+
+/* Bit 10 : Keep RAM section S10 ON or OFF in System ON mode. */
+#define POWER_RAM_POWER_S10POWER_Pos (10UL) /*!< Position of S10POWER field. */
+#define POWER_RAM_POWER_S10POWER_Msk (0x1UL << POWER_RAM_POWER_S10POWER_Pos) /*!< Bit mask of S10POWER field. */
+#define POWER_RAM_POWER_S10POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S10POWER_On (1UL) /*!< On */
+
+/* Bit 9 : Keep RAM section S9 ON or OFF in System ON mode. */
+#define POWER_RAM_POWER_S9POWER_Pos (9UL) /*!< Position of S9POWER field. */
+#define POWER_RAM_POWER_S9POWER_Msk (0x1UL << POWER_RAM_POWER_S9POWER_Pos) /*!< Bit mask of S9POWER field. */
+#define POWER_RAM_POWER_S9POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S9POWER_On (1UL) /*!< On */
+
+/* Bit 8 : Keep RAM section S8 ON or OFF in System ON mode. */
+#define POWER_RAM_POWER_S8POWER_Pos (8UL) /*!< Position of S8POWER field. */
+#define POWER_RAM_POWER_S8POWER_Msk (0x1UL << POWER_RAM_POWER_S8POWER_Pos) /*!< Bit mask of S8POWER field. */
+#define POWER_RAM_POWER_S8POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S8POWER_On (1UL) /*!< On */
+
+/* Bit 7 : Keep RAM section S7 ON or OFF in System ON mode. */
+#define POWER_RAM_POWER_S7POWER_Pos (7UL) /*!< Position of S7POWER field. */
+#define POWER_RAM_POWER_S7POWER_Msk (0x1UL << POWER_RAM_POWER_S7POWER_Pos) /*!< Bit mask of S7POWER field. */
+#define POWER_RAM_POWER_S7POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S7POWER_On (1UL) /*!< On */
+
+/* Bit 6 : Keep RAM section S6 ON or OFF in System ON mode. */
+#define POWER_RAM_POWER_S6POWER_Pos (6UL) /*!< Position of S6POWER field. */
+#define POWER_RAM_POWER_S6POWER_Msk (0x1UL << POWER_RAM_POWER_S6POWER_Pos) /*!< Bit mask of S6POWER field. */
+#define POWER_RAM_POWER_S6POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S6POWER_On (1UL) /*!< On */
+
+/* Bit 5 : Keep RAM section S5 ON or OFF in System ON mode. */
+#define POWER_RAM_POWER_S5POWER_Pos (5UL) /*!< Position of S5POWER field. */
+#define POWER_RAM_POWER_S5POWER_Msk (0x1UL << POWER_RAM_POWER_S5POWER_Pos) /*!< Bit mask of S5POWER field. */
+#define POWER_RAM_POWER_S5POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S5POWER_On (1UL) /*!< On */
+
+/* Bit 4 : Keep RAM section S4 ON or OFF in System ON mode. */
+#define POWER_RAM_POWER_S4POWER_Pos (4UL) /*!< Position of S4POWER field. */
+#define POWER_RAM_POWER_S4POWER_Msk (0x1UL << POWER_RAM_POWER_S4POWER_Pos) /*!< Bit mask of S4POWER field. */
+#define POWER_RAM_POWER_S4POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S4POWER_On (1UL) /*!< On */
+
+/* Bit 3 : Keep RAM section S3 ON or OFF in System ON mode. */
+#define POWER_RAM_POWER_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */
+#define POWER_RAM_POWER_S3POWER_Msk (0x1UL << POWER_RAM_POWER_S3POWER_Pos) /*!< Bit mask of S3POWER field. */
+#define POWER_RAM_POWER_S3POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S3POWER_On (1UL) /*!< On */
+
+/* Bit 2 : Keep RAM section S2 ON or OFF in System ON mode. */
+#define POWER_RAM_POWER_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
+#define POWER_RAM_POWER_S2POWER_Msk (0x1UL << POWER_RAM_POWER_S2POWER_Pos) /*!< Bit mask of S2POWER field. */
+#define POWER_RAM_POWER_S2POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S2POWER_On (1UL) /*!< On */
+
+/* Bit 1 : Keep RAM section S1 ON or OFF in System ON mode. */
+#define POWER_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
+#define POWER_RAM_POWER_S1POWER_Msk (0x1UL << POWER_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
+#define POWER_RAM_POWER_S1POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S1POWER_On (1UL) /*!< On */
+
+/* Bit 0 : Keep RAM section S0 ON or OFF in System ON mode. */
+#define POWER_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
+#define POWER_RAM_POWER_S0POWER_Msk (0x1UL << POWER_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
+#define POWER_RAM_POWER_S0POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */
+
+/* Register: POWER_RAM_POWERSET */
+/* Description: Description cluster[0]:  RAM0 power control set register */
+
+/* Bit 31 : Keep retention on RAM section S15 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */
+#define POWER_RAM_POWERSET_S15RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S15RETENTION_Pos) /*!< Bit mask of S15RETENTION field. */
+#define POWER_RAM_POWERSET_S15RETENTION_On (1UL) /*!< On */
+
+/* Bit 30 : Keep retention on RAM section S14 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S14RETENTION_Pos (30UL) /*!< Position of S14RETENTION field. */
+#define POWER_RAM_POWERSET_S14RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S14RETENTION_Pos) /*!< Bit mask of S14RETENTION field. */
+#define POWER_RAM_POWERSET_S14RETENTION_On (1UL) /*!< On */
+
+/* Bit 29 : Keep retention on RAM section S13 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S13RETENTION_Pos (29UL) /*!< Position of S13RETENTION field. */
+#define POWER_RAM_POWERSET_S13RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S13RETENTION_Pos) /*!< Bit mask of S13RETENTION field. */
+#define POWER_RAM_POWERSET_S13RETENTION_On (1UL) /*!< On */
+
+/* Bit 28 : Keep retention on RAM section S12 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S12RETENTION_Pos (28UL) /*!< Position of S12RETENTION field. */
+#define POWER_RAM_POWERSET_S12RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S12RETENTION_Pos) /*!< Bit mask of S12RETENTION field. */
+#define POWER_RAM_POWERSET_S12RETENTION_On (1UL) /*!< On */
+
+/* Bit 27 : Keep retention on RAM section S11 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S11RETENTION_Pos (27UL) /*!< Position of S11RETENTION field. */
+#define POWER_RAM_POWERSET_S11RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S11RETENTION_Pos) /*!< Bit mask of S11RETENTION field. */
+#define POWER_RAM_POWERSET_S11RETENTION_On (1UL) /*!< On */
+
+/* Bit 26 : Keep retention on RAM section S10 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S10RETENTION_Pos (26UL) /*!< Position of S10RETENTION field. */
+#define POWER_RAM_POWERSET_S10RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S10RETENTION_Pos) /*!< Bit mask of S10RETENTION field. */
+#define POWER_RAM_POWERSET_S10RETENTION_On (1UL) /*!< On */
+
+/* Bit 25 : Keep retention on RAM section S9 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S9RETENTION_Pos (25UL) /*!< Position of S9RETENTION field. */
+#define POWER_RAM_POWERSET_S9RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S9RETENTION_Pos) /*!< Bit mask of S9RETENTION field. */
+#define POWER_RAM_POWERSET_S9RETENTION_On (1UL) /*!< On */
+
+/* Bit 24 : Keep retention on RAM section S8 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S8RETENTION_Pos (24UL) /*!< Position of S8RETENTION field. */
+#define POWER_RAM_POWERSET_S8RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S8RETENTION_Pos) /*!< Bit mask of S8RETENTION field. */
+#define POWER_RAM_POWERSET_S8RETENTION_On (1UL) /*!< On */
+
+/* Bit 23 : Keep retention on RAM section S7 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S7RETENTION_Pos (23UL) /*!< Position of S7RETENTION field. */
+#define POWER_RAM_POWERSET_S7RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S7RETENTION_Pos) /*!< Bit mask of S7RETENTION field. */
+#define POWER_RAM_POWERSET_S7RETENTION_On (1UL) /*!< On */
+
+/* Bit 22 : Keep retention on RAM section S6 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S6RETENTION_Pos (22UL) /*!< Position of S6RETENTION field. */
+#define POWER_RAM_POWERSET_S6RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S6RETENTION_Pos) /*!< Bit mask of S6RETENTION field. */
+#define POWER_RAM_POWERSET_S6RETENTION_On (1UL) /*!< On */
+
+/* Bit 21 : Keep retention on RAM section S5 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S5RETENTION_Pos (21UL) /*!< Position of S5RETENTION field. */
+#define POWER_RAM_POWERSET_S5RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S5RETENTION_Pos) /*!< Bit mask of S5RETENTION field. */
+#define POWER_RAM_POWERSET_S5RETENTION_On (1UL) /*!< On */
+
+/* Bit 20 : Keep retention on RAM section S4 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S4RETENTION_Pos (20UL) /*!< Position of S4RETENTION field. */
+#define POWER_RAM_POWERSET_S4RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S4RETENTION_Pos) /*!< Bit mask of S4RETENTION field. */
+#define POWER_RAM_POWERSET_S4RETENTION_On (1UL) /*!< On */
+
+/* Bit 19 : Keep retention on RAM section S3 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */
+#define POWER_RAM_POWERSET_S3RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */
+#define POWER_RAM_POWERSET_S3RETENTION_On (1UL) /*!< On */
+
+/* Bit 18 : Keep retention on RAM section S2 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */
+#define POWER_RAM_POWERSET_S2RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */
+#define POWER_RAM_POWERSET_S2RETENTION_On (1UL) /*!< On */
+
+/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
+#define POWER_RAM_POWERSET_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
+#define POWER_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */
+
+/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
+#define POWER_RAM_POWERSET_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
+#define POWER_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */
+
+/* Bit 15 : Keep RAM section S15 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERSET_S15POWER_Pos (15UL) /*!< Position of S15POWER field. */
+#define POWER_RAM_POWERSET_S15POWER_Msk (0x1UL << POWER_RAM_POWERSET_S15POWER_Pos) /*!< Bit mask of S15POWER field. */
+#define POWER_RAM_POWERSET_S15POWER_On (1UL) /*!< On */
+
+/* Bit 14 : Keep RAM section S14 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERSET_S14POWER_Pos (14UL) /*!< Position of S14POWER field. */
+#define POWER_RAM_POWERSET_S14POWER_Msk (0x1UL << POWER_RAM_POWERSET_S14POWER_Pos) /*!< Bit mask of S14POWER field. */
+#define POWER_RAM_POWERSET_S14POWER_On (1UL) /*!< On */
+
+/* Bit 13 : Keep RAM section S13 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERSET_S13POWER_Pos (13UL) /*!< Position of S13POWER field. */
+#define POWER_RAM_POWERSET_S13POWER_Msk (0x1UL << POWER_RAM_POWERSET_S13POWER_Pos) /*!< Bit mask of S13POWER field. */
+#define POWER_RAM_POWERSET_S13POWER_On (1UL) /*!< On */
+
+/* Bit 12 : Keep RAM section S12 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERSET_S12POWER_Pos (12UL) /*!< Position of S12POWER field. */
+#define POWER_RAM_POWERSET_S12POWER_Msk (0x1UL << POWER_RAM_POWERSET_S12POWER_Pos) /*!< Bit mask of S12POWER field. */
+#define POWER_RAM_POWERSET_S12POWER_On (1UL) /*!< On */
+
+/* Bit 11 : Keep RAM section S11 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERSET_S11POWER_Pos (11UL) /*!< Position of S11POWER field. */
+#define POWER_RAM_POWERSET_S11POWER_Msk (0x1UL << POWER_RAM_POWERSET_S11POWER_Pos) /*!< Bit mask of S11POWER field. */
+#define POWER_RAM_POWERSET_S11POWER_On (1UL) /*!< On */
+
+/* Bit 10 : Keep RAM section S10 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERSET_S10POWER_Pos (10UL) /*!< Position of S10POWER field. */
+#define POWER_RAM_POWERSET_S10POWER_Msk (0x1UL << POWER_RAM_POWERSET_S10POWER_Pos) /*!< Bit mask of S10POWER field. */
+#define POWER_RAM_POWERSET_S10POWER_On (1UL) /*!< On */
+
+/* Bit 9 : Keep RAM section S9 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERSET_S9POWER_Pos (9UL) /*!< Position of S9POWER field. */
+#define POWER_RAM_POWERSET_S9POWER_Msk (0x1UL << POWER_RAM_POWERSET_S9POWER_Pos) /*!< Bit mask of S9POWER field. */
+#define POWER_RAM_POWERSET_S9POWER_On (1UL) /*!< On */
+
+/* Bit 8 : Keep RAM section S8 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERSET_S8POWER_Pos (8UL) /*!< Position of S8POWER field. */
+#define POWER_RAM_POWERSET_S8POWER_Msk (0x1UL << POWER_RAM_POWERSET_S8POWER_Pos) /*!< Bit mask of S8POWER field. */
+#define POWER_RAM_POWERSET_S8POWER_On (1UL) /*!< On */
+
+/* Bit 7 : Keep RAM section S7 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERSET_S7POWER_Pos (7UL) /*!< Position of S7POWER field. */
+#define POWER_RAM_POWERSET_S7POWER_Msk (0x1UL << POWER_RAM_POWERSET_S7POWER_Pos) /*!< Bit mask of S7POWER field. */
+#define POWER_RAM_POWERSET_S7POWER_On (1UL) /*!< On */
+
+/* Bit 6 : Keep RAM section S6 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERSET_S6POWER_Pos (6UL) /*!< Position of S6POWER field. */
+#define POWER_RAM_POWERSET_S6POWER_Msk (0x1UL << POWER_RAM_POWERSET_S6POWER_Pos) /*!< Bit mask of S6POWER field. */
+#define POWER_RAM_POWERSET_S6POWER_On (1UL) /*!< On */
+
+/* Bit 5 : Keep RAM section S5 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERSET_S5POWER_Pos (5UL) /*!< Position of S5POWER field. */
+#define POWER_RAM_POWERSET_S5POWER_Msk (0x1UL << POWER_RAM_POWERSET_S5POWER_Pos) /*!< Bit mask of S5POWER field. */
+#define POWER_RAM_POWERSET_S5POWER_On (1UL) /*!< On */
+
+/* Bit 4 : Keep RAM section S4 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERSET_S4POWER_Pos (4UL) /*!< Position of S4POWER field. */
+#define POWER_RAM_POWERSET_S4POWER_Msk (0x1UL << POWER_RAM_POWERSET_S4POWER_Pos) /*!< Bit mask of S4POWER field. */
+#define POWER_RAM_POWERSET_S4POWER_On (1UL) /*!< On */
+
+/* Bit 3 : Keep RAM section S3 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERSET_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */
+#define POWER_RAM_POWERSET_S3POWER_Msk (0x1UL << POWER_RAM_POWERSET_S3POWER_Pos) /*!< Bit mask of S3POWER field. */
+#define POWER_RAM_POWERSET_S3POWER_On (1UL) /*!< On */
+
+/* Bit 2 : Keep RAM section S2 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERSET_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
+#define POWER_RAM_POWERSET_S2POWER_Msk (0x1UL << POWER_RAM_POWERSET_S2POWER_Pos) /*!< Bit mask of S2POWER field. */
+#define POWER_RAM_POWERSET_S2POWER_On (1UL) /*!< On */
+
+/* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
+#define POWER_RAM_POWERSET_S1POWER_Msk (0x1UL << POWER_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
+#define POWER_RAM_POWERSET_S1POWER_On (1UL) /*!< On */
+
+/* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
+#define POWER_RAM_POWERSET_S0POWER_Msk (0x1UL << POWER_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
+#define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */
+
+/* Register: POWER_RAM_POWERCLR */
+/* Description: Description cluster[0]:  RAM0 power control clear register */
+
+/* Bit 31 : Keep retention on RAM section S15 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */
+#define POWER_RAM_POWERCLR_S15RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S15RETENTION_Pos) /*!< Bit mask of S15RETENTION field. */
+#define POWER_RAM_POWERCLR_S15RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 30 : Keep retention on RAM section S14 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S14RETENTION_Pos (30UL) /*!< Position of S14RETENTION field. */
+#define POWER_RAM_POWERCLR_S14RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S14RETENTION_Pos) /*!< Bit mask of S14RETENTION field. */
+#define POWER_RAM_POWERCLR_S14RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 29 : Keep retention on RAM section S13 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S13RETENTION_Pos (29UL) /*!< Position of S13RETENTION field. */
+#define POWER_RAM_POWERCLR_S13RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S13RETENTION_Pos) /*!< Bit mask of S13RETENTION field. */
+#define POWER_RAM_POWERCLR_S13RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 28 : Keep retention on RAM section S12 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S12RETENTION_Pos (28UL) /*!< Position of S12RETENTION field. */
+#define POWER_RAM_POWERCLR_S12RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S12RETENTION_Pos) /*!< Bit mask of S12RETENTION field. */
+#define POWER_RAM_POWERCLR_S12RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 27 : Keep retention on RAM section S11 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S11RETENTION_Pos (27UL) /*!< Position of S11RETENTION field. */
+#define POWER_RAM_POWERCLR_S11RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S11RETENTION_Pos) /*!< Bit mask of S11RETENTION field. */
+#define POWER_RAM_POWERCLR_S11RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 26 : Keep retention on RAM section S10 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S10RETENTION_Pos (26UL) /*!< Position of S10RETENTION field. */
+#define POWER_RAM_POWERCLR_S10RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S10RETENTION_Pos) /*!< Bit mask of S10RETENTION field. */
+#define POWER_RAM_POWERCLR_S10RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 25 : Keep retention on RAM section S9 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S9RETENTION_Pos (25UL) /*!< Position of S9RETENTION field. */
+#define POWER_RAM_POWERCLR_S9RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S9RETENTION_Pos) /*!< Bit mask of S9RETENTION field. */
+#define POWER_RAM_POWERCLR_S9RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 24 : Keep retention on RAM section S8 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S8RETENTION_Pos (24UL) /*!< Position of S8RETENTION field. */
+#define POWER_RAM_POWERCLR_S8RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S8RETENTION_Pos) /*!< Bit mask of S8RETENTION field. */
+#define POWER_RAM_POWERCLR_S8RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 23 : Keep retention on RAM section S7 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S7RETENTION_Pos (23UL) /*!< Position of S7RETENTION field. */
+#define POWER_RAM_POWERCLR_S7RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S7RETENTION_Pos) /*!< Bit mask of S7RETENTION field. */
+#define POWER_RAM_POWERCLR_S7RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 22 : Keep retention on RAM section S6 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S6RETENTION_Pos (22UL) /*!< Position of S6RETENTION field. */
+#define POWER_RAM_POWERCLR_S6RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S6RETENTION_Pos) /*!< Bit mask of S6RETENTION field. */
+#define POWER_RAM_POWERCLR_S6RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 21 : Keep retention on RAM section S5 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S5RETENTION_Pos (21UL) /*!< Position of S5RETENTION field. */
+#define POWER_RAM_POWERCLR_S5RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S5RETENTION_Pos) /*!< Bit mask of S5RETENTION field. */
+#define POWER_RAM_POWERCLR_S5RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 20 : Keep retention on RAM section S4 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S4RETENTION_Pos (20UL) /*!< Position of S4RETENTION field. */
+#define POWER_RAM_POWERCLR_S4RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S4RETENTION_Pos) /*!< Bit mask of S4RETENTION field. */
+#define POWER_RAM_POWERCLR_S4RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 19 : Keep retention on RAM section S3 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */
+#define POWER_RAM_POWERCLR_S3RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */
+#define POWER_RAM_POWERCLR_S3RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 18 : Keep retention on RAM section S2 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */
+#define POWER_RAM_POWERCLR_S2RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */
+#define POWER_RAM_POWERCLR_S2RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
+#define POWER_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
+#define POWER_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
+#define POWER_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
+#define POWER_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 15 : Keep RAM section S15 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S15POWER_Pos (15UL) /*!< Position of S15POWER field. */
+#define POWER_RAM_POWERCLR_S15POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S15POWER_Pos) /*!< Bit mask of S15POWER field. */
+#define POWER_RAM_POWERCLR_S15POWER_Off (1UL) /*!< Off */
+
+/* Bit 14 : Keep RAM section S14 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S14POWER_Pos (14UL) /*!< Position of S14POWER field. */
+#define POWER_RAM_POWERCLR_S14POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S14POWER_Pos) /*!< Bit mask of S14POWER field. */
+#define POWER_RAM_POWERCLR_S14POWER_Off (1UL) /*!< Off */
+
+/* Bit 13 : Keep RAM section S13 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S13POWER_Pos (13UL) /*!< Position of S13POWER field. */
+#define POWER_RAM_POWERCLR_S13POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S13POWER_Pos) /*!< Bit mask of S13POWER field. */
+#define POWER_RAM_POWERCLR_S13POWER_Off (1UL) /*!< Off */
+
+/* Bit 12 : Keep RAM section S12 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S12POWER_Pos (12UL) /*!< Position of S12POWER field. */
+#define POWER_RAM_POWERCLR_S12POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S12POWER_Pos) /*!< Bit mask of S12POWER field. */
+#define POWER_RAM_POWERCLR_S12POWER_Off (1UL) /*!< Off */
+
+/* Bit 11 : Keep RAM section S11 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S11POWER_Pos (11UL) /*!< Position of S11POWER field. */
+#define POWER_RAM_POWERCLR_S11POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S11POWER_Pos) /*!< Bit mask of S11POWER field. */
+#define POWER_RAM_POWERCLR_S11POWER_Off (1UL) /*!< Off */
+
+/* Bit 10 : Keep RAM section S10 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S10POWER_Pos (10UL) /*!< Position of S10POWER field. */
+#define POWER_RAM_POWERCLR_S10POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S10POWER_Pos) /*!< Bit mask of S10POWER field. */
+#define POWER_RAM_POWERCLR_S10POWER_Off (1UL) /*!< Off */
+
+/* Bit 9 : Keep RAM section S9 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S9POWER_Pos (9UL) /*!< Position of S9POWER field. */
+#define POWER_RAM_POWERCLR_S9POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S9POWER_Pos) /*!< Bit mask of S9POWER field. */
+#define POWER_RAM_POWERCLR_S9POWER_Off (1UL) /*!< Off */
+
+/* Bit 8 : Keep RAM section S8 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S8POWER_Pos (8UL) /*!< Position of S8POWER field. */
+#define POWER_RAM_POWERCLR_S8POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S8POWER_Pos) /*!< Bit mask of S8POWER field. */
+#define POWER_RAM_POWERCLR_S8POWER_Off (1UL) /*!< Off */
+
+/* Bit 7 : Keep RAM section S7 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S7POWER_Pos (7UL) /*!< Position of S7POWER field. */
+#define POWER_RAM_POWERCLR_S7POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S7POWER_Pos) /*!< Bit mask of S7POWER field. */
+#define POWER_RAM_POWERCLR_S7POWER_Off (1UL) /*!< Off */
+
+/* Bit 6 : Keep RAM section S6 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S6POWER_Pos (6UL) /*!< Position of S6POWER field. */
+#define POWER_RAM_POWERCLR_S6POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S6POWER_Pos) /*!< Bit mask of S6POWER field. */
+#define POWER_RAM_POWERCLR_S6POWER_Off (1UL) /*!< Off */
+
+/* Bit 5 : Keep RAM section S5 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S5POWER_Pos (5UL) /*!< Position of S5POWER field. */
+#define POWER_RAM_POWERCLR_S5POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S5POWER_Pos) /*!< Bit mask of S5POWER field. */
+#define POWER_RAM_POWERCLR_S5POWER_Off (1UL) /*!< Off */
+
+/* Bit 4 : Keep RAM section S4 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S4POWER_Pos (4UL) /*!< Position of S4POWER field. */
+#define POWER_RAM_POWERCLR_S4POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S4POWER_Pos) /*!< Bit mask of S4POWER field. */
+#define POWER_RAM_POWERCLR_S4POWER_Off (1UL) /*!< Off */
+
+/* Bit 3 : Keep RAM section S3 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */
+#define POWER_RAM_POWERCLR_S3POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S3POWER_Pos) /*!< Bit mask of S3POWER field. */
+#define POWER_RAM_POWERCLR_S3POWER_Off (1UL) /*!< Off */
+
+/* Bit 2 : Keep RAM section S2 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
+#define POWER_RAM_POWERCLR_S2POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S2POWER_Pos) /*!< Bit mask of S2POWER field. */
+#define POWER_RAM_POWERCLR_S2POWER_Off (1UL) /*!< Off */
+
+/* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
+#define POWER_RAM_POWERCLR_S1POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
+#define POWER_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */
+
+/* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
+#define POWER_RAM_POWERCLR_S0POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
+#define POWER_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */
+
+
+/* Peripheral: PPI */
+/* Description: Programmable Peripheral Interconnect */
+
+/* Register: PPI_CHEN */
+/* Description: Channel enable register */
+
+/* Bit 31 : Enable or disable channel 31 */
+#define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHEN_CH31_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH31_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 30 : Enable or disable channel 30 */
+#define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHEN_CH30_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH30_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 29 : Enable or disable channel 29 */
+#define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHEN_CH29_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH29_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 28 : Enable or disable channel 28 */
+#define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHEN_CH28_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH28_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 27 : Enable or disable channel 27 */
+#define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHEN_CH27_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH27_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 26 : Enable or disable channel 26 */
+#define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHEN_CH26_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH26_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 25 : Enable or disable channel 25 */
+#define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHEN_CH25_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH25_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 24 : Enable or disable channel 24 */
+#define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHEN_CH24_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH24_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 23 : Enable or disable channel 23 */
+#define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHEN_CH23_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH23_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 22 : Enable or disable channel 22 */
+#define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHEN_CH22_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH22_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 21 : Enable or disable channel 21 */
+#define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHEN_CH21_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH21_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 20 : Enable or disable channel 20 */
+#define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHEN_CH20_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH20_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 19 : Enable or disable channel 19 */
+#define PPI_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */
+#define PPI_CHEN_CH19_Msk (0x1UL << PPI_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */
+#define PPI_CHEN_CH19_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH19_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 18 : Enable or disable channel 18 */
+#define PPI_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */
+#define PPI_CHEN_CH18_Msk (0x1UL << PPI_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */
+#define PPI_CHEN_CH18_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH18_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 17 : Enable or disable channel 17 */
+#define PPI_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */
+#define PPI_CHEN_CH17_Msk (0x1UL << PPI_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */
+#define PPI_CHEN_CH17_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH17_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 16 : Enable or disable channel 16 */
+#define PPI_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */
+#define PPI_CHEN_CH16_Msk (0x1UL << PPI_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */
+#define PPI_CHEN_CH16_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH16_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 15 : Enable or disable channel 15 */
+#define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHEN_CH15_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH15_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 14 : Enable or disable channel 14 */
+#define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHEN_CH14_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH14_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 13 : Enable or disable channel 13 */
+#define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHEN_CH13_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH13_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 12 : Enable or disable channel 12 */
+#define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHEN_CH12_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH12_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 11 : Enable or disable channel 11 */
+#define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHEN_CH11_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH11_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 10 : Enable or disable channel 10 */
+#define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHEN_CH10_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH10_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 9 : Enable or disable channel 9 */
+#define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHEN_CH9_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH9_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 8 : Enable or disable channel 8 */
+#define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHEN_CH8_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH8_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 7 : Enable or disable channel 7 */
+#define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHEN_CH7_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH7_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 6 : Enable or disable channel 6 */
+#define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHEN_CH6_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH6_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 5 : Enable or disable channel 5 */
+#define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHEN_CH5_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH5_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 4 : Enable or disable channel 4 */
+#define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHEN_CH4_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH4_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 3 : Enable or disable channel 3 */
+#define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHEN_CH3_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH3_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 2 : Enable or disable channel 2 */
+#define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHEN_CH2_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH2_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 1 : Enable or disable channel 1 */
+#define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHEN_CH1_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH1_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 0 : Enable or disable channel 0 */
+#define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHEN_CH0_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH0_Enabled (1UL) /*!< Enable channel */
+
+/* Register: PPI_CHENSET */
+/* Description: Channel enable set register */
+
+/* Bit 31 : Channel 31 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 30 : Channel 30 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 29 : Channel 29 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 28 : Channel 28 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 27 : Channel 27 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 26 : Channel 26 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 25 : Channel 25 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 24 : Channel 24 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 23 : Channel 23 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 22 : Channel 22 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 21 : Channel 21 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 20 : Channel 20 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 19 : Channel 19 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */
+#define PPI_CHENSET_CH19_Msk (0x1UL << PPI_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */
+#define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 18 : Channel 18 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */
+#define PPI_CHENSET_CH18_Msk (0x1UL << PPI_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */
+#define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 17 : Channel 17 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */
+#define PPI_CHENSET_CH17_Msk (0x1UL << PPI_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */
+#define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 16 : Channel 16 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */
+#define PPI_CHENSET_CH16_Msk (0x1UL << PPI_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */
+#define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 15 : Channel 15 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 14 : Channel 14 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 13 : Channel 13 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 12 : Channel 12 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 11 : Channel 11 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 10 : Channel 10 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 9 : Channel 9 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 8 : Channel 8 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 7 : Channel 7 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 6 : Channel 6 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 5 : Channel 5 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 4 : Channel 4 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 3 : Channel 3 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 2 : Channel 2 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 1 : Channel 1 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 0 : Channel 0 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */
+
+/* Register: PPI_CHENCLR */
+/* Description: Channel enable clear register */
+
+/* Bit 31 : Channel 31 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 30 : Channel 30 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 29 : Channel 29 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 28 : Channel 28 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 27 : Channel 27 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 26 : Channel 26 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 25 : Channel 25 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 24 : Channel 24 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 23 : Channel 23 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 22 : Channel 22 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 21 : Channel 21 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 20 : Channel 20 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 19 : Channel 19 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */
+#define PPI_CHENCLR_CH19_Msk (0x1UL << PPI_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */
+#define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 18 : Channel 18 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */
+#define PPI_CHENCLR_CH18_Msk (0x1UL << PPI_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */
+#define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 17 : Channel 17 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */
+#define PPI_CHENCLR_CH17_Msk (0x1UL << PPI_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */
+#define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 16 : Channel 16 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */
+#define PPI_CHENCLR_CH16_Msk (0x1UL << PPI_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */
+#define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 15 : Channel 15 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 14 : Channel 14 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 13 : Channel 13 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 12 : Channel 12 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 11 : Channel 11 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 10 : Channel 10 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 9 : Channel 9 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 8 : Channel 8 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 7 : Channel 7 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 6 : Channel 6 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 5 : Channel 5 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 4 : Channel 4 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 3 : Channel 3 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 2 : Channel 2 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 1 : Channel 1 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 0 : Channel 0 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */
+
+/* Register: PPI_CH_EEP */
+/* Description: Description cluster[0]:  Channel 0 event end-point */
+
+/* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */
+#define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */
+#define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */
+
+/* Register: PPI_CH_TEP */
+/* Description: Description cluster[0]:  Channel 0 task end-point */
+
+/* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */
+#define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
+#define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
+
+/* Register: PPI_CHG */
+/* Description: Description collection[0]:  Channel group 0 */
+
+/* Bit 31 : Include or exclude channel 31 */
+#define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHG_CH31_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH31_Included (1UL) /*!< Include */
+
+/* Bit 30 : Include or exclude channel 30 */
+#define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHG_CH30_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH30_Included (1UL) /*!< Include */
+
+/* Bit 29 : Include or exclude channel 29 */
+#define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHG_CH29_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH29_Included (1UL) /*!< Include */
+
+/* Bit 28 : Include or exclude channel 28 */
+#define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHG_CH28_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH28_Included (1UL) /*!< Include */
+
+/* Bit 27 : Include or exclude channel 27 */
+#define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHG_CH27_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH27_Included (1UL) /*!< Include */
+
+/* Bit 26 : Include or exclude channel 26 */
+#define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHG_CH26_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH26_Included (1UL) /*!< Include */
+
+/* Bit 25 : Include or exclude channel 25 */
+#define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHG_CH25_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH25_Included (1UL) /*!< Include */
+
+/* Bit 24 : Include or exclude channel 24 */
+#define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHG_CH24_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH24_Included (1UL) /*!< Include */
+
+/* Bit 23 : Include or exclude channel 23 */
+#define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHG_CH23_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH23_Included (1UL) /*!< Include */
+
+/* Bit 22 : Include or exclude channel 22 */
+#define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHG_CH22_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH22_Included (1UL) /*!< Include */
+
+/* Bit 21 : Include or exclude channel 21 */
+#define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHG_CH21_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH21_Included (1UL) /*!< Include */
+
+/* Bit 20 : Include or exclude channel 20 */
+#define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHG_CH20_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH20_Included (1UL) /*!< Include */
+
+/* Bit 19 : Include or exclude channel 19 */
+#define PPI_CHG_CH19_Pos (19UL) /*!< Position of CH19 field. */
+#define PPI_CHG_CH19_Msk (0x1UL << PPI_CHG_CH19_Pos) /*!< Bit mask of CH19 field. */
+#define PPI_CHG_CH19_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH19_Included (1UL) /*!< Include */
+
+/* Bit 18 : Include or exclude channel 18 */
+#define PPI_CHG_CH18_Pos (18UL) /*!< Position of CH18 field. */
+#define PPI_CHG_CH18_Msk (0x1UL << PPI_CHG_CH18_Pos) /*!< Bit mask of CH18 field. */
+#define PPI_CHG_CH18_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH18_Included (1UL) /*!< Include */
+
+/* Bit 17 : Include or exclude channel 17 */
+#define PPI_CHG_CH17_Pos (17UL) /*!< Position of CH17 field. */
+#define PPI_CHG_CH17_Msk (0x1UL << PPI_CHG_CH17_Pos) /*!< Bit mask of CH17 field. */
+#define PPI_CHG_CH17_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH17_Included (1UL) /*!< Include */
+
+/* Bit 16 : Include or exclude channel 16 */
+#define PPI_CHG_CH16_Pos (16UL) /*!< Position of CH16 field. */
+#define PPI_CHG_CH16_Msk (0x1UL << PPI_CHG_CH16_Pos) /*!< Bit mask of CH16 field. */
+#define PPI_CHG_CH16_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH16_Included (1UL) /*!< Include */
+
+/* Bit 15 : Include or exclude channel 15 */
+#define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHG_CH15_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH15_Included (1UL) /*!< Include */
+
+/* Bit 14 : Include or exclude channel 14 */
+#define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHG_CH14_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH14_Included (1UL) /*!< Include */
+
+/* Bit 13 : Include or exclude channel 13 */
+#define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHG_CH13_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH13_Included (1UL) /*!< Include */
+
+/* Bit 12 : Include or exclude channel 12 */
+#define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHG_CH12_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH12_Included (1UL) /*!< Include */
+
+/* Bit 11 : Include or exclude channel 11 */
+#define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHG_CH11_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH11_Included (1UL) /*!< Include */
+
+/* Bit 10 : Include or exclude channel 10 */
+#define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHG_CH10_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH10_Included (1UL) /*!< Include */
+
+/* Bit 9 : Include or exclude channel 9 */
+#define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHG_CH9_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH9_Included (1UL) /*!< Include */
+
+/* Bit 8 : Include or exclude channel 8 */
+#define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHG_CH8_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH8_Included (1UL) /*!< Include */
+
+/* Bit 7 : Include or exclude channel 7 */
+#define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHG_CH7_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH7_Included (1UL) /*!< Include */
+
+/* Bit 6 : Include or exclude channel 6 */
+#define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHG_CH6_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH6_Included (1UL) /*!< Include */
+
+/* Bit 5 : Include or exclude channel 5 */
+#define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHG_CH5_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH5_Included (1UL) /*!< Include */
+
+/* Bit 4 : Include or exclude channel 4 */
+#define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHG_CH4_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH4_Included (1UL) /*!< Include */
+
+/* Bit 3 : Include or exclude channel 3 */
+#define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHG_CH3_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH3_Included (1UL) /*!< Include */
+
+/* Bit 2 : Include or exclude channel 2 */
+#define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHG_CH2_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH2_Included (1UL) /*!< Include */
+
+/* Bit 1 : Include or exclude channel 1 */
+#define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHG_CH1_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH1_Included (1UL) /*!< Include */
+
+/* Bit 0 : Include or exclude channel 0 */
+#define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHG_CH0_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH0_Included (1UL) /*!< Include */
+
+/* Register: PPI_FORK_TEP */
+/* Description: Description cluster[0]:  Channel 0 task end-point */
+
+/* Bits 31..0 : Pointer to task register */
+#define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
+#define PPI_FORK_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_FORK_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
+
+
+/* Peripheral: PWM */
+/* Description: Pulse Width Modulation Unit 0 */
+
+/* Register: PWM_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 4 : Shortcut between LOOPSDONE event and STOP task */
+#define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */
+#define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */
+#define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between LOOPSDONE event and SEQSTART[1] task */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between LOOPSDONE event and SEQSTART[0] task */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between SEQEND[1] event and STOP task */
+#define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */
+#define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */
+#define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between SEQEND[0] event and STOP task */
+#define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */
+#define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */
+#define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: PWM_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 7 : Enable or disable interrupt for LOOPSDONE event */
+#define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
+#define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
+#define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable interrupt for PWMPERIODEND event */
+#define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
+#define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
+#define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable interrupt for SEQEND[1] event */
+#define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
+#define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
+#define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for SEQEND[0] event */
+#define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
+#define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
+#define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable interrupt for SEQSTARTED[1] event */
+#define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
+#define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
+#define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for SEQSTARTED[0] event */
+#define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
+#define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
+#define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for STOPPED event */
+#define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Register: PWM_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 7 : Write '1' to Enable interrupt for LOOPSDONE event */
+#define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
+#define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
+#define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for PWMPERIODEND event */
+#define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
+#define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
+#define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable interrupt for SEQEND[1] event */
+#define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
+#define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
+#define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for SEQEND[0] event */
+#define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
+#define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
+#define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for SEQSTARTED[1] event */
+#define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
+#define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
+#define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for SEQSTARTED[0] event */
+#define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
+#define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
+#define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
+#define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Register: PWM_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 7 : Write '1' to Disable interrupt for LOOPSDONE event */
+#define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
+#define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
+#define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for PWMPERIODEND event */
+#define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
+#define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
+#define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable interrupt for SEQEND[1] event */
+#define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
+#define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
+#define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for SEQEND[0] event */
+#define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
+#define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
+#define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for SEQSTARTED[1] event */
+#define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
+#define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
+#define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for SEQSTARTED[0] event */
+#define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
+#define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
+#define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
+#define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Register: PWM_ENABLE */
+/* Description: PWM module enable register */
+
+/* Bit 0 : Enable or disable PWM module */
+#define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define PWM_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled */
+#define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
+
+/* Register: PWM_MODE */
+/* Description: Selects operating mode of the wave counter */
+
+/* Bit 0 : Selects up or up and down as wave counter mode */
+#define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */
+#define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */
+#define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter - edge aligned PWM duty-cycle */
+#define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter - center aligned PWM duty cycle */
+
+/* Register: PWM_COUNTERTOP */
+/* Description: Value up to which the pulse generator counter counts */
+
+/* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used. */
+#define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */
+#define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */
+
+/* Register: PWM_PRESCALER */
+/* Description: Configuration for PWM_CLK */
+
+/* Bits 2..0 : Pre-scaler of PWM_CLK */
+#define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
+#define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
+#define PWM_PRESCALER_PRESCALER_DIV_1 (0UL) /*!< Divide by   1 (16MHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by   2 ( 8MHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by   4 ( 4MHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by   8 ( 2MHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_16 (4UL) /*!< Divide by  16 ( 1MHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_32 (5UL) /*!< Divide by  32 ( 500kHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_64 (6UL) /*!< Divide by  64 ( 250kHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_128 (7UL) /*!< Divide by 128 ( 125kHz) */
+
+/* Register: PWM_DECODER */
+/* Description: Configuration of the decoder */
+
+/* Bit 8 : Selects source for advancing the active sequence */
+#define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */
+#define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */
+#define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */
+#define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */
+
+/* Bits 2..0 : How a sequence is read from RAM and spread to the compare register */
+#define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */
+#define PWM_DECODER_LOAD_Msk (0x7UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */
+#define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */
+#define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */
+#define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */
+#define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */
+
+/* Register: PWM_LOOP */
+/* Description: Amount of playback of a loop */
+
+/* Bits 15..0 : Amount of playback of pattern cycles */
+#define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */
+#define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */
+#define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */
+
+/* Register: PWM_SEQ_PTR */
+/* Description: Description cluster[0]:  Beginning address in Data RAM of sequence A */
+
+/* Bits 31..0 : Beginning address in Data RAM of sequence A */
+#define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: PWM_SEQ_CNT */
+/* Description: Description cluster[0]:  Amount of values (duty cycles) in sequence A */
+
+/* Bits 14..0 : Amount of values (duty cycles) in sequence A */
+#define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */
+#define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */
+#define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */
+
+/* Register: PWM_SEQ_REFRESH */
+/* Description: Description cluster[0]:  Amount of additional PWM periods between samples loaded to compare register (load every CNT+1 PWM periods) */
+
+/* Bits 23..0 : Amount of additional PWM periods between samples loaded to compare register (load every CNT+1 PWM periods) */
+#define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */
+#define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */
+#define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */
+
+/* Register: PWM_SEQ_ENDDELAY */
+/* Description: Description cluster[0]:  Time added after the sequence */
+
+/* Bits 23..0 : Time added after the sequence in PWM periods */
+#define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */
+#define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */
+
+/* Register: PWM_PSEL_OUT */
+/* Description: Description collection[0]:  Output pin select for PWM channel 0 */
+
+/* Bit 31 : Connection */
+#define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define PWM_PSEL_OUT_CONNECT_Connected (0UL) /*!< Connect */
+#define PWM_PSEL_OUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 9..8 : Port number */
+#define PWM_PSEL_OUT_PORT_Pos (8UL) /*!< Position of PORT field. */
+#define PWM_PSEL_OUT_PORT_Msk (0x3UL << PWM_PSEL_OUT_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */
+
+
+/* Peripheral: QDEC */
+/* Description: Quadrature Decoder */
+
+/* Register: QDEC_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 6 : Shortcut between SAMPLERDY event and READCLRACC task */
+#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */
+#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */
+#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
+#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 5 : Shortcut between DBLRDY event and STOP task */
+#define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */
+#define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */
+#define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 4 : Shortcut between DBLRDY event and RDCLRDBL task */
+#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */
+#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */
+#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */
+#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between REPORTRDY event and STOP task */
+#define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */
+#define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */
+#define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between REPORTRDY event and RDCLRACC task */
+#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */
+#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */
+#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */
+#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between SAMPLERDY event and STOP task */
+#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */
+#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */
+#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task */
+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */
+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */
+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: QDEC_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 4 : Write '1' to Enable interrupt for STOPPED event */
+#define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
+#define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for DBLRDY event */
+#define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
+#define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
+#define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for ACCOF event */
+#define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
+#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
+#define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for REPORTRDY event */
+#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
+#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
+#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for SAMPLERDY event */
+#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
+#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
+#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable */
+
+/* Register: QDEC_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 4 : Write '1' to Disable interrupt for STOPPED event */
+#define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
+#define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for DBLRDY event */
+#define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
+#define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
+#define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for ACCOF event */
+#define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
+#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
+#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for REPORTRDY event */
+#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
+#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
+#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for SAMPLERDY event */
+#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
+#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
+#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable */
+
+/* Register: QDEC_ENABLE */
+/* Description: Enable the quadrature decoder */
+
+/* Bit 0 : Enable or disable the quadrature decoder */
+#define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
+
+/* Register: QDEC_LEDPOL */
+/* Description: LED output pin polarity */
+
+/* Bit 0 : LED output pin polarity */
+#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */
+#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */
+#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< Led active on output pin low */
+#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< Led active on output pin high */
+
+/* Register: QDEC_SAMPLEPER */
+/* Description: Sample period */
+
+/* Bits 3..0 : Sample period. The SAMPLE register will be updated for every new sample */
+#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */
+#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */
+#define QDEC_SAMPLEPER_SAMPLEPER_128us (0UL) /*!< 128 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_256us (1UL) /*!< 256 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_512us (2UL) /*!< 512 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_1024us (3UL) /*!< 1024 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_2048us (4UL) /*!< 2048 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_4096us (5UL) /*!< 4096 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_8192us (6UL) /*!< 8192 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_16384us (7UL) /*!< 16384 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_32ms (8UL) /*!< 32768 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_65ms (9UL) /*!< 65536 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_131ms (10UL) /*!< 131072 us */
+
+/* Register: QDEC_SAMPLE */
+/* Description: Motion sample value */
+
+/* Bits 31..0 : Last motion sample */
+#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */
+#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */
+
+/* Register: QDEC_REPORTPER */
+/* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */
+
+/* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated */
+#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */
+#define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */
+#define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples / report */
+#define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples / report */
+#define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples / report */
+#define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples / report */
+#define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples / report */
+#define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples / report */
+#define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples / report */
+#define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples / report */
+#define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample / report */
+
+/* Register: QDEC_ACC */
+/* Description: Register accumulating the valid transitions */
+
+/* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register */
+#define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */
+#define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */
+
+/* Register: QDEC_ACCREAD */
+/* Description: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */
+
+/* Bits 31..0 : Snapshot of the ACC register. */
+#define QDEC_ACCREAD_ACCREAD_Pos (0UL) /*!< Position of ACCREAD field. */
+#define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos) /*!< Bit mask of ACCREAD field. */
+
+/* Register: QDEC_PSEL_LED */
+/* Description: Pin select for LED signal */
+
+/* Bit 31 : Connection */
+#define QDEC_PSEL_LED_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define QDEC_PSEL_LED_CONNECT_Connected (0UL) /*!< Connect */
+#define QDEC_PSEL_LED_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define QDEC_PSEL_LED_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define QDEC_PSEL_LED_PORT_Msk (0x3UL << QDEC_PSEL_LED_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define QDEC_PSEL_LED_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: QDEC_PSEL_A */
+/* Description: Pin select for A signal */
+
+/* Bit 31 : Connection */
+#define QDEC_PSEL_A_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define QDEC_PSEL_A_CONNECT_Connected (0UL) /*!< Connect */
+#define QDEC_PSEL_A_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define QDEC_PSEL_A_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define QDEC_PSEL_A_PORT_Msk (0x3UL << QDEC_PSEL_A_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define QDEC_PSEL_A_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: QDEC_PSEL_B */
+/* Description: Pin select for B signal */
+
+/* Bit 31 : Connection */
+#define QDEC_PSEL_B_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define QDEC_PSEL_B_CONNECT_Connected (0UL) /*!< Connect */
+#define QDEC_PSEL_B_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define QDEC_PSEL_B_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define QDEC_PSEL_B_PORT_Msk (0x3UL << QDEC_PSEL_B_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define QDEC_PSEL_B_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: QDEC_DBFEN */
+/* Description: Enable input debounce filters */
+
+/* Bit 0 : Enable input debounce filters */
+#define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */
+#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */
+#define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled */
+#define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled */
+
+/* Register: QDEC_LEDPRE */
+/* Description: Time period the LED is switched ON prior to sampling */
+
+/* Bits 8..0 : Period in us the LED is switched on prior to sampling */
+#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */
+#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */
+
+/* Register: QDEC_ACCDBL */
+/* Description: Register accumulating the number of detected double transitions */
+
+/* Bits 3..0 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */
+#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */
+#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */
+
+/* Register: QDEC_ACCDBLREAD */
+/* Description: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */
+
+/* Bits 3..0 : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. */
+#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */
+#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */
+
+
+/* Peripheral: QSPI */
+/* Description: External flash interface */
+
+/* Register: QSPI_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 0 : Enable or disable interrupt for READY event */
+#define QSPI_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
+#define QSPI_INTEN_READY_Msk (0x1UL << QSPI_INTEN_READY_Pos) /*!< Bit mask of READY field. */
+#define QSPI_INTEN_READY_Disabled (0UL) /*!< Disable */
+#define QSPI_INTEN_READY_Enabled (1UL) /*!< Enable */
+
+/* Register: QSPI_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 0 : Write '1' to Enable interrupt for READY event */
+#define QSPI_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
+#define QSPI_INTENSET_READY_Msk (0x1UL << QSPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define QSPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
+#define QSPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
+#define QSPI_INTENSET_READY_Set (1UL) /*!< Enable */
+
+/* Register: QSPI_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 0 : Write '1' to Disable interrupt for READY event */
+#define QSPI_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
+#define QSPI_INTENCLR_READY_Msk (0x1UL << QSPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define QSPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
+#define QSPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
+#define QSPI_INTENCLR_READY_Clear (1UL) /*!< Disable */
+
+/* Register: QSPI_ENABLE */
+/* Description: Enable QSPI peripheral and acquire the pins selected in PSELn registers */
+
+/* Bit 0 : Enable or disable QSPI */
+#define QSPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define QSPI_ENABLE_ENABLE_Msk (0x1UL << QSPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define QSPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable QSPI */
+#define QSPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable QSPI */
+
+/* Register: QSPI_READ_SRC */
+/* Description: Flash memory source address */
+
+/* Bits 31..0 : Word-aligned flash memory source address. */
+#define QSPI_READ_SRC_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define QSPI_READ_SRC_SRC_Msk (0xFFFFFFFFUL << QSPI_READ_SRC_SRC_Pos) /*!< Bit mask of SRC field. */
+
+/* Register: QSPI_READ_DST */
+/* Description: RAM destination address */
+
+/* Bits 31..0 : Word-aligned RAM destination address. */
+#define QSPI_READ_DST_DST_Pos (0UL) /*!< Position of DST field. */
+#define QSPI_READ_DST_DST_Msk (0xFFFFFFFFUL << QSPI_READ_DST_DST_Pos) /*!< Bit mask of DST field. */
+
+/* Register: QSPI_READ_CNT */
+/* Description: Read transfer length */
+
+/* Bits 20..0 : Read transfer length in number of bytes. The length must be a multiple of 4 bytes. */
+#define QSPI_READ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */
+#define QSPI_READ_CNT_CNT_Msk (0x1FFFFFUL << QSPI_READ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */
+
+/* Register: QSPI_WRITE_DST */
+/* Description: Flash destination address */
+
+/* Bits 31..0 : Word-aligned flash destination address. */
+#define QSPI_WRITE_DST_DST_Pos (0UL) /*!< Position of DST field. */
+#define QSPI_WRITE_DST_DST_Msk (0xFFFFFFFFUL << QSPI_WRITE_DST_DST_Pos) /*!< Bit mask of DST field. */
+
+/* Register: QSPI_WRITE_SRC */
+/* Description: RAM source address */
+
+/* Bits 31..0 : Word-aligned RAM source address. */
+#define QSPI_WRITE_SRC_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define QSPI_WRITE_SRC_SRC_Msk (0xFFFFFFFFUL << QSPI_WRITE_SRC_SRC_Pos) /*!< Bit mask of SRC field. */
+
+/* Register: QSPI_WRITE_CNT */
+/* Description: Write transfer length */
+
+/* Bits 20..0 : Write transfer length in number of bytes. The length must be a multiple of 4 bytes. */
+#define QSPI_WRITE_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */
+#define QSPI_WRITE_CNT_CNT_Msk (0x1FFFFFUL << QSPI_WRITE_CNT_CNT_Pos) /*!< Bit mask of CNT field. */
+
+/* Register: QSPI_ERASE_PTR */
+/* Description: Start address of flash block to be erased */
+
+/* Bits 31..0 : Word-aligned start address of block to be erased. */
+#define QSPI_ERASE_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define QSPI_ERASE_PTR_PTR_Msk (0xFFFFFFFFUL << QSPI_ERASE_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: QSPI_ERASE_LEN */
+/* Description: Size of block to be erased. */
+
+/* Bits 1..0 : LEN */
+#define QSPI_ERASE_LEN_LEN_Pos (0UL) /*!< Position of LEN field. */
+#define QSPI_ERASE_LEN_LEN_Msk (0x3UL << QSPI_ERASE_LEN_LEN_Pos) /*!< Bit mask of LEN field. */
+#define QSPI_ERASE_LEN_LEN_4KB (0UL) /*!< Erase 4 kB block (flash command 0x20) */
+#define QSPI_ERASE_LEN_LEN_64KB (1UL) /*!< Erase 64 kB block (flash command 0xD8) */
+#define QSPI_ERASE_LEN_LEN_All (2UL) /*!< Erase all (flash command 0xC7) */
+
+/* Register: QSPI_PSEL_SCK */
+/* Description: Pin select for serial clock SCK */
+
+/* Bit 31 : Connection */
+#define QSPI_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define QSPI_PSEL_SCK_CONNECT_Msk (0x1UL << QSPI_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define QSPI_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
+#define QSPI_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define QSPI_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define QSPI_PSEL_SCK_PORT_Msk (0x3UL << QSPI_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define QSPI_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define QSPI_PSEL_SCK_PIN_Msk (0x1FUL << QSPI_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: QSPI_PSEL_CSN */
+/* Description: Pin select for chip select signal CSN. */
+
+/* Bit 31 : Connection */
+#define QSPI_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define QSPI_PSEL_CSN_CONNECT_Msk (0x1UL << QSPI_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define QSPI_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */
+#define QSPI_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define QSPI_PSEL_CSN_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define QSPI_PSEL_CSN_PORT_Msk (0x3UL << QSPI_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define QSPI_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define QSPI_PSEL_CSN_PIN_Msk (0x1FUL << QSPI_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: QSPI_PSEL_IO0 */
+/* Description: Pin select for serial data MOSI/IO0. */
+
+/* Bit 31 : Connection */
+#define QSPI_PSEL_IO0_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define QSPI_PSEL_IO0_CONNECT_Msk (0x1UL << QSPI_PSEL_IO0_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define QSPI_PSEL_IO0_CONNECT_Connected (0UL) /*!< Connect */
+#define QSPI_PSEL_IO0_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define QSPI_PSEL_IO0_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define QSPI_PSEL_IO0_PORT_Msk (0x3UL << QSPI_PSEL_IO0_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define QSPI_PSEL_IO0_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define QSPI_PSEL_IO0_PIN_Msk (0x1FUL << QSPI_PSEL_IO0_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: QSPI_PSEL_IO1 */
+/* Description: Pin select for serial data MISO/IO1. */
+
+/* Bit 31 : Connection */
+#define QSPI_PSEL_IO1_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define QSPI_PSEL_IO1_CONNECT_Msk (0x1UL << QSPI_PSEL_IO1_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define QSPI_PSEL_IO1_CONNECT_Connected (0UL) /*!< Connect */
+#define QSPI_PSEL_IO1_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define QSPI_PSEL_IO1_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define QSPI_PSEL_IO1_PORT_Msk (0x3UL << QSPI_PSEL_IO1_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define QSPI_PSEL_IO1_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define QSPI_PSEL_IO1_PIN_Msk (0x1FUL << QSPI_PSEL_IO1_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: QSPI_PSEL_IO2 */
+/* Description: Pin select for serial data IO2. */
+
+/* Bit 31 : Connection */
+#define QSPI_PSEL_IO2_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define QSPI_PSEL_IO2_CONNECT_Msk (0x1UL << QSPI_PSEL_IO2_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define QSPI_PSEL_IO2_CONNECT_Connected (0UL) /*!< Connect */
+#define QSPI_PSEL_IO2_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define QSPI_PSEL_IO2_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define QSPI_PSEL_IO2_PORT_Msk (0x3UL << QSPI_PSEL_IO2_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define QSPI_PSEL_IO2_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define QSPI_PSEL_IO2_PIN_Msk (0x1FUL << QSPI_PSEL_IO2_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: QSPI_PSEL_IO3 */
+/* Description: Pin select for serial data IO3. */
+
+/* Bit 31 : Connection */
+#define QSPI_PSEL_IO3_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define QSPI_PSEL_IO3_CONNECT_Msk (0x1UL << QSPI_PSEL_IO3_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define QSPI_PSEL_IO3_CONNECT_Connected (0UL) /*!< Connect */
+#define QSPI_PSEL_IO3_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define QSPI_PSEL_IO3_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define QSPI_PSEL_IO3_PORT_Msk (0x3UL << QSPI_PSEL_IO3_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define QSPI_PSEL_IO3_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define QSPI_PSEL_IO3_PIN_Msk (0x1FUL << QSPI_PSEL_IO3_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: QSPI_XIPOFFSET */
+/* Description: Address offset into the external memory for Execute in Place operation. */
+
+/* Bits 31..0 : Address offset into the external memory for Execute in Place operation. Value must be a multiple of 4. */
+#define QSPI_XIPOFFSET_XIPOFFSET_Pos (0UL) /*!< Position of XIPOFFSET field. */
+#define QSPI_XIPOFFSET_XIPOFFSET_Msk (0xFFFFFFFFUL << QSPI_XIPOFFSET_XIPOFFSET_Pos) /*!< Bit mask of XIPOFFSET field. */
+
+/* Register: QSPI_IFCONFIG0 */
+/* Description: Interface configuration. */
+
+/* Bit 7 : Enable deep power-down mode (DPM) feature. */
+#define QSPI_IFCONFIG0_DPMENABLE_Pos (7UL) /*!< Position of DPMENABLE field. */
+#define QSPI_IFCONFIG0_DPMENABLE_Msk (0x1UL << QSPI_IFCONFIG0_DPMENABLE_Pos) /*!< Bit mask of DPMENABLE field. */
+#define QSPI_IFCONFIG0_DPMENABLE_Disable (0UL) /*!< Disable DPM feature. */
+#define QSPI_IFCONFIG0_DPMENABLE_Enable (1UL) /*!< Enable DPM feature. */
+
+/* Bit 6 : Addressing mode. */
+#define QSPI_IFCONFIG0_ADDRMODE_Pos (6UL) /*!< Position of ADDRMODE field. */
+#define QSPI_IFCONFIG0_ADDRMODE_Msk (0x1UL << QSPI_IFCONFIG0_ADDRMODE_Pos) /*!< Bit mask of ADDRMODE field. */
+#define QSPI_IFCONFIG0_ADDRMODE_24BIT (0UL) /*!< 24-bit addressing. */
+#define QSPI_IFCONFIG0_ADDRMODE_32BIT (1UL) /*!< 32-bit addressing. */
+
+/* Bits 5..3 : Configure number of data lines and opcode used for writing. */
+#define QSPI_IFCONFIG0_WRITEOC_Pos (3UL) /*!< Position of WRITEOC field. */
+#define QSPI_IFCONFIG0_WRITEOC_Msk (0x7UL << QSPI_IFCONFIG0_WRITEOC_Pos) /*!< Bit mask of WRITEOC field. */
+#define QSPI_IFCONFIG0_WRITEOC_PP (0UL) /*!< Single data line SPI. PP (opcode 0x02). */
+#define QSPI_IFCONFIG0_WRITEOC_PP2O (1UL) /*!< Dual data line SPI. PP2O (opcode 0xA2). */
+#define QSPI_IFCONFIG0_WRITEOC_PP4O (2UL) /*!< Quad data line SPI. PP4O (opcode 0x32). */
+#define QSPI_IFCONFIG0_WRITEOC_PP4IO (3UL) /*!< Quad data line SPI. PP4IO (opcode 0x38). */
+
+/* Bits 2..0 : Configure number of data lines and opcode used for reading. */
+#define QSPI_IFCONFIG0_READOC_Pos (0UL) /*!< Position of READOC field. */
+#define QSPI_IFCONFIG0_READOC_Msk (0x7UL << QSPI_IFCONFIG0_READOC_Pos) /*!< Bit mask of READOC field. */
+#define QSPI_IFCONFIG0_READOC_FASTREAD (0UL) /*!< Single data line SPI. FAST_READ (opcode 0x0B). */
+#define QSPI_IFCONFIG0_READOC_READ2O (1UL) /*!< Dual data line SPI. READ2O (opcode 0x3B). */
+#define QSPI_IFCONFIG0_READOC_READ2IO (2UL) /*!< Dual data line SPI. READ2IO (opcode 0xBB). */
+#define QSPI_IFCONFIG0_READOC_READ4O (3UL) /*!< Quad data line SPI. READ4O (opcode 0x6B). */
+#define QSPI_IFCONFIG0_READOC_READ4IO (4UL) /*!< Quad data line SPI. READ4IO (opcode 0xEB). */
+
+/* Register: QSPI_IFCONFIG1 */
+/* Description: Interface configuration. */
+
+/* Bits 31..28 : SCK frequency is given as 32 MHz / (SCKFREQ + 1). */
+#define QSPI_IFCONFIG1_SCKFREQ_Pos (28UL) /*!< Position of SCKFREQ field. */
+#define QSPI_IFCONFIG1_SCKFREQ_Msk (0xFUL << QSPI_IFCONFIG1_SCKFREQ_Pos) /*!< Bit mask of SCKFREQ field. */
+
+/* Bit 25 : Select SPI mode. */
+#define QSPI_IFCONFIG1_SPIMODE_Pos (25UL) /*!< Position of SPIMODE field. */
+#define QSPI_IFCONFIG1_SPIMODE_Msk (0x1UL << QSPI_IFCONFIG1_SPIMODE_Pos) /*!< Bit mask of SPIMODE field. */
+#define QSPI_IFCONFIG1_SPIMODE_MODE0 (0UL) /*!< Mode 0: Data are captured on the clock's rising edge and data is output on a falling edge. Base level of clock is 0 (CPOL=0, CPHA=0). */
+#define QSPI_IFCONFIG1_SPIMODE_MODE3 (1UL) /*!< Mode 3: Data are captured on the clock's falling edge and data is output on a rising edge. Base level of clock is 1 (CPOL=1, CPHA=1). */
+
+/* Bit 24 : Enter/exit deep power-down mode (DPM) for external flash memory. */
+#define QSPI_IFCONFIG1_DPMEN_Pos (24UL) /*!< Position of DPMEN field. */
+#define QSPI_IFCONFIG1_DPMEN_Msk (0x1UL << QSPI_IFCONFIG1_DPMEN_Pos) /*!< Bit mask of DPMEN field. */
+#define QSPI_IFCONFIG1_DPMEN_Exit (0UL) /*!< Exit DPM. */
+#define QSPI_IFCONFIG1_DPMEN_Enter (1UL) /*!< Enter DPM. */
+
+/* Bits 7..0 : Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 16 MHz periods (62.5 ns). */
+#define QSPI_IFCONFIG1_SCKDELAY_Pos (0UL) /*!< Position of SCKDELAY field. */
+#define QSPI_IFCONFIG1_SCKDELAY_Msk (0xFFUL << QSPI_IFCONFIG1_SCKDELAY_Pos) /*!< Bit mask of SCKDELAY field. */
+
+/* Register: QSPI_STATUS */
+/* Description: Status register. */
+
+/* Bits 31..24 : Value of external flash devices Status Register. When the external flash has two bytes status register this field includes the value of the low byte. */
+#define QSPI_STATUS_SREG_Pos (24UL) /*!< Position of SREG field. */
+#define QSPI_STATUS_SREG_Msk (0xFFUL << QSPI_STATUS_SREG_Pos) /*!< Bit mask of SREG field. */
+
+/* Bit 3 : Ready status. */
+#define QSPI_STATUS_READY_Pos (3UL) /*!< Position of READY field. */
+#define QSPI_STATUS_READY_Msk (0x1UL << QSPI_STATUS_READY_Pos) /*!< Bit mask of READY field. */
+#define QSPI_STATUS_READY_BUSY (0UL) /*!< QSPI peripheral is busy. It is not allowed to trigger any new tasks, writing custom instructions or enter/exit DPM. */
+#define QSPI_STATUS_READY_READY (1UL) /*!< QSPI peripheral is ready. It is allowed to trigger new tasks, writing custom instructions or enter/exit DPM. */
+
+/* Bit 2 : Deep power-down mode (DPM) status of external flash. */
+#define QSPI_STATUS_DPM_Pos (2UL) /*!< Position of DPM field. */
+#define QSPI_STATUS_DPM_Msk (0x1UL << QSPI_STATUS_DPM_Pos) /*!< Bit mask of DPM field. */
+#define QSPI_STATUS_DPM_Disabled (0UL) /*!< External flash is not in DPM. */
+#define QSPI_STATUS_DPM_Enabled (1UL) /*!< External flash is in DPM. */
+
+/* Register: QSPI_DPMDUR */
+/* Description: Set the duration required to enter/exit deep power-down mode (DPM). */
+
+/* Bits 31..16 : Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 62.5 ns. */
+#define QSPI_DPMDUR_EXIT_Pos (16UL) /*!< Position of EXIT field. */
+#define QSPI_DPMDUR_EXIT_Msk (0xFFFFUL << QSPI_DPMDUR_EXIT_Pos) /*!< Bit mask of EXIT field. */
+
+/* Bits 15..0 : Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 62.5 ns. */
+#define QSPI_DPMDUR_ENTER_Pos (0UL) /*!< Position of ENTER field. */
+#define QSPI_DPMDUR_ENTER_Msk (0xFFFFUL << QSPI_DPMDUR_ENTER_Pos) /*!< Bit mask of ENTER field. */
+
+/* Register: QSPI_ADDRCONF */
+/* Description: Extended address configuration. */
+
+/* Bit 27 : Send WREN (write enable opcode 0x06) before instruction. */
+#define QSPI_ADDRCONF_WREN_Pos (27UL) /*!< Position of WREN field. */
+#define QSPI_ADDRCONF_WREN_Msk (0x1UL << QSPI_ADDRCONF_WREN_Pos) /*!< Bit mask of WREN field. */
+#define QSPI_ADDRCONF_WREN_Disable (0UL) /*!< Do not send WREN. */
+#define QSPI_ADDRCONF_WREN_Enable (1UL) /*!< Send WREN. */
+
+/* Bit 26 : Wait for write complete before sending command. */
+#define QSPI_ADDRCONF_WIPWAIT_Pos (26UL) /*!< Position of WIPWAIT field. */
+#define QSPI_ADDRCONF_WIPWAIT_Msk (0x1UL << QSPI_ADDRCONF_WIPWAIT_Pos) /*!< Bit mask of WIPWAIT field. */
+#define QSPI_ADDRCONF_WIPWAIT_Disable (0UL) /*!< No wait. */
+#define QSPI_ADDRCONF_WIPWAIT_Enable (1UL) /*!< Wait. */
+
+/* Bits 25..24 : Extended addressing mode. */
+#define QSPI_ADDRCONF_MODE_Pos (24UL) /*!< Position of MODE field. */
+#define QSPI_ADDRCONF_MODE_Msk (0x3UL << QSPI_ADDRCONF_MODE_Pos) /*!< Bit mask of MODE field. */
+#define QSPI_ADDRCONF_MODE_NoInstr (0UL) /*!< Do not send any instruction. */
+#define QSPI_ADDRCONF_MODE_Opcode (1UL) /*!< Send opcode. */
+#define QSPI_ADDRCONF_MODE_OpByte0 (2UL) /*!< Send opcode, byte0. */
+#define QSPI_ADDRCONF_MODE_All (3UL) /*!< Send opcode, byte0, byte1. */
+
+/* Bits 23..16 : Byte 1 following byte 0. */
+#define QSPI_ADDRCONF_BYTE1_Pos (16UL) /*!< Position of BYTE1 field. */
+#define QSPI_ADDRCONF_BYTE1_Msk (0xFFUL << QSPI_ADDRCONF_BYTE1_Pos) /*!< Bit mask of BYTE1 field. */
+
+/* Bits 15..8 : Byte 0 following opcode. */
+#define QSPI_ADDRCONF_BYTE0_Pos (8UL) /*!< Position of BYTE0 field. */
+#define QSPI_ADDRCONF_BYTE0_Msk (0xFFUL << QSPI_ADDRCONF_BYTE0_Pos) /*!< Bit mask of BYTE0 field. */
+
+/* Bits 7..0 : Opcode that enters the 32-bit addressing mode. */
+#define QSPI_ADDRCONF_OPCODE_Pos (0UL) /*!< Position of OPCODE field. */
+#define QSPI_ADDRCONF_OPCODE_Msk (0xFFUL << QSPI_ADDRCONF_OPCODE_Pos) /*!< Bit mask of OPCODE field. */
+
+/* Register: QSPI_CINSTRCONF */
+/* Description: Custom instruction configuration register. */
+
+/* Bit 15 : Send WREN (write enable opcode 0x06) before instruction. */
+#define QSPI_CINSTRCONF_WREN_Pos (15UL) /*!< Position of WREN field. */
+#define QSPI_CINSTRCONF_WREN_Msk (0x1UL << QSPI_CINSTRCONF_WREN_Pos) /*!< Bit mask of WREN field. */
+#define QSPI_CINSTRCONF_WREN_Disable (0UL) /*!< Do not send WREN. */
+#define QSPI_CINSTRCONF_WREN_Enable (1UL) /*!< Send WREN. */
+
+/* Bit 14 : Wait for write complete before sending command. */
+#define QSPI_CINSTRCONF_WIPWAIT_Pos (14UL) /*!< Position of WIPWAIT field. */
+#define QSPI_CINSTRCONF_WIPWAIT_Msk (0x1UL << QSPI_CINSTRCONF_WIPWAIT_Pos) /*!< Bit mask of WIPWAIT field. */
+#define QSPI_CINSTRCONF_WIPWAIT_Disable (0UL) /*!< No wait. */
+#define QSPI_CINSTRCONF_WIPWAIT_Enable (1UL) /*!< Wait. */
+
+/* Bit 13 : Level of the IO3 pin (if connected) during transmission of custom instruction. */
+#define QSPI_CINSTRCONF_LIO3_Pos (13UL) /*!< Position of LIO3 field. */
+#define QSPI_CINSTRCONF_LIO3_Msk (0x1UL << QSPI_CINSTRCONF_LIO3_Pos) /*!< Bit mask of LIO3 field. */
+
+/* Bit 12 : Level of the IO2 pin (if connected) during transmission of custom instruction. */
+#define QSPI_CINSTRCONF_LIO2_Pos (12UL) /*!< Position of LIO2 field. */
+#define QSPI_CINSTRCONF_LIO2_Msk (0x1UL << QSPI_CINSTRCONF_LIO2_Pos) /*!< Bit mask of LIO2 field. */
+
+/* Bits 11..8 : Length of custom instruction in number of bytes. */
+#define QSPI_CINSTRCONF_LENGTH_Pos (8UL) /*!< Position of LENGTH field. */
+#define QSPI_CINSTRCONF_LENGTH_Msk (0xFUL << QSPI_CINSTRCONF_LENGTH_Pos) /*!< Bit mask of LENGTH field. */
+#define QSPI_CINSTRCONF_LENGTH_1B (1UL) /*!< Send opcode only. */
+#define QSPI_CINSTRCONF_LENGTH_2B (2UL) /*!< Send opcode, CINSTRDAT0.BYTE0. */
+#define QSPI_CINSTRCONF_LENGTH_3B (3UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE1. */
+#define QSPI_CINSTRCONF_LENGTH_4B (4UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE2. */
+#define QSPI_CINSTRCONF_LENGTH_5B (5UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE3. */
+#define QSPI_CINSTRCONF_LENGTH_6B (6UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE4. */
+#define QSPI_CINSTRCONF_LENGTH_7B (7UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE5. */
+#define QSPI_CINSTRCONF_LENGTH_8B (8UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE6. */
+#define QSPI_CINSTRCONF_LENGTH_9B (9UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE7. */
+
+/* Bits 7..0 : Opcode of Custom instruction. */
+#define QSPI_CINSTRCONF_OPCODE_Pos (0UL) /*!< Position of OPCODE field. */
+#define QSPI_CINSTRCONF_OPCODE_Msk (0xFFUL << QSPI_CINSTRCONF_OPCODE_Pos) /*!< Bit mask of OPCODE field. */
+
+/* Register: QSPI_CINSTRDAT0 */
+/* Description: Custom instruction data register 0. */
+
+/* Bits 31..24 : Data byte 3 */
+#define QSPI_CINSTRDAT0_BYTE3_Pos (24UL) /*!< Position of BYTE3 field. */
+#define QSPI_CINSTRDAT0_BYTE3_Msk (0xFFUL << QSPI_CINSTRDAT0_BYTE3_Pos) /*!< Bit mask of BYTE3 field. */
+
+/* Bits 23..16 : Data byte 2 */
+#define QSPI_CINSTRDAT0_BYTE2_Pos (16UL) /*!< Position of BYTE2 field. */
+#define QSPI_CINSTRDAT0_BYTE2_Msk (0xFFUL << QSPI_CINSTRDAT0_BYTE2_Pos) /*!< Bit mask of BYTE2 field. */
+
+/* Bits 15..8 : Data byte 1 */
+#define QSPI_CINSTRDAT0_BYTE1_Pos (8UL) /*!< Position of BYTE1 field. */
+#define QSPI_CINSTRDAT0_BYTE1_Msk (0xFFUL << QSPI_CINSTRDAT0_BYTE1_Pos) /*!< Bit mask of BYTE1 field. */
+
+/* Bits 7..0 : Data byte 0 */
+#define QSPI_CINSTRDAT0_BYTE0_Pos (0UL) /*!< Position of BYTE0 field. */
+#define QSPI_CINSTRDAT0_BYTE0_Msk (0xFFUL << QSPI_CINSTRDAT0_BYTE0_Pos) /*!< Bit mask of BYTE0 field. */
+
+/* Register: QSPI_CINSTRDAT1 */
+/* Description: Custom instruction data register 1. */
+
+/* Bits 31..24 : Data byte 7 */
+#define QSPI_CINSTRDAT1_BYTE7_Pos (24UL) /*!< Position of BYTE7 field. */
+#define QSPI_CINSTRDAT1_BYTE7_Msk (0xFFUL << QSPI_CINSTRDAT1_BYTE7_Pos) /*!< Bit mask of BYTE7 field. */
+
+/* Bits 23..16 : Data byte 6 */
+#define QSPI_CINSTRDAT1_BYTE6_Pos (16UL) /*!< Position of BYTE6 field. */
+#define QSPI_CINSTRDAT1_BYTE6_Msk (0xFFUL << QSPI_CINSTRDAT1_BYTE6_Pos) /*!< Bit mask of BYTE6 field. */
+
+/* Bits 15..8 : Data byte 5 */
+#define QSPI_CINSTRDAT1_BYTE5_Pos (8UL) /*!< Position of BYTE5 field. */
+#define QSPI_CINSTRDAT1_BYTE5_Msk (0xFFUL << QSPI_CINSTRDAT1_BYTE5_Pos) /*!< Bit mask of BYTE5 field. */
+
+/* Bits 7..0 : Data byte 4 */
+#define QSPI_CINSTRDAT1_BYTE4_Pos (0UL) /*!< Position of BYTE4 field. */
+#define QSPI_CINSTRDAT1_BYTE4_Msk (0xFFUL << QSPI_CINSTRDAT1_BYTE4_Pos) /*!< Bit mask of BYTE4 field. */
+
+/* Register: QSPI_IFTIMING */
+/* Description: SPI interface timing. */
+
+/* Bits 10..8 : Timing related to sampling of the input serial data. The value of RXDELAY specifies the number of 64 MHz cycles (15.625 ns) delay from the the rising edge of the SPI Clock (SCK) until the input serial data is sampled. As en example, if set to 0 the input serial data is sampled on the rising edge of SCK. */
+#define QSPI_IFTIMING_RXDELAY_Pos (8UL) /*!< Position of RXDELAY field. */
+#define QSPI_IFTIMING_RXDELAY_Msk (0x7UL << QSPI_IFTIMING_RXDELAY_Pos) /*!< Bit mask of RXDELAY field. */
+
+
+/* Peripheral: RADIO */
+/* Description: 2.4 GHz Radio */
+
+/* Register: RADIO_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 19 : Shortcut between RXREADY event and START task */
+#define RADIO_SHORTS_RXREADY_START_Pos (19UL) /*!< Position of RXREADY_START field. */
+#define RADIO_SHORTS_RXREADY_START_Msk (0x1UL << RADIO_SHORTS_RXREADY_START_Pos) /*!< Bit mask of RXREADY_START field. */
+#define RADIO_SHORTS_RXREADY_START_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_RXREADY_START_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 18 : Shortcut between TXREADY event and START task */
+#define RADIO_SHORTS_TXREADY_START_Pos (18UL) /*!< Position of TXREADY_START field. */
+#define RADIO_SHORTS_TXREADY_START_Msk (0x1UL << RADIO_SHORTS_TXREADY_START_Pos) /*!< Bit mask of TXREADY_START field. */
+#define RADIO_SHORTS_TXREADY_START_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_TXREADY_START_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 17 : Shortcut between CCAIDLE event and STOP task */
+#define RADIO_SHORTS_CCAIDLE_STOP_Pos (17UL) /*!< Position of CCAIDLE_STOP field. */
+#define RADIO_SHORTS_CCAIDLE_STOP_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_STOP_Pos) /*!< Bit mask of CCAIDLE_STOP field. */
+#define RADIO_SHORTS_CCAIDLE_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_CCAIDLE_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 16 : Shortcut between EDEND event and DISABLE task */
+#define RADIO_SHORTS_EDEND_DISABLE_Pos (16UL) /*!< Position of EDEND_DISABLE field. */
+#define RADIO_SHORTS_EDEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_EDEND_DISABLE_Pos) /*!< Bit mask of EDEND_DISABLE field. */
+#define RADIO_SHORTS_EDEND_DISABLE_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_EDEND_DISABLE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 15 : Shortcut between READY event and EDSTART task */
+#define RADIO_SHORTS_READY_EDSTART_Pos (15UL) /*!< Position of READY_EDSTART field. */
+#define RADIO_SHORTS_READY_EDSTART_Msk (0x1UL << RADIO_SHORTS_READY_EDSTART_Pos) /*!< Bit mask of READY_EDSTART field. */
+#define RADIO_SHORTS_READY_EDSTART_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_READY_EDSTART_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 14 : Shortcut between FRAMESTART event and BCSTART task */
+#define RADIO_SHORTS_FRAMESTART_BCSTART_Pos (14UL) /*!< Position of FRAMESTART_BCSTART field. */
+#define RADIO_SHORTS_FRAMESTART_BCSTART_Msk (0x1UL << RADIO_SHORTS_FRAMESTART_BCSTART_Pos) /*!< Bit mask of FRAMESTART_BCSTART field. */
+#define RADIO_SHORTS_FRAMESTART_BCSTART_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_FRAMESTART_BCSTART_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 13 : Shortcut between CCABUSY event and DISABLE task */
+#define RADIO_SHORTS_CCABUSY_DISABLE_Pos (13UL) /*!< Position of CCABUSY_DISABLE field. */
+#define RADIO_SHORTS_CCABUSY_DISABLE_Msk (0x1UL << RADIO_SHORTS_CCABUSY_DISABLE_Pos) /*!< Bit mask of CCABUSY_DISABLE field. */
+#define RADIO_SHORTS_CCABUSY_DISABLE_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_CCABUSY_DISABLE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 12 : Shortcut between CCAIDLE event and TXEN task */
+#define RADIO_SHORTS_CCAIDLE_TXEN_Pos (12UL) /*!< Position of CCAIDLE_TXEN field. */
+#define RADIO_SHORTS_CCAIDLE_TXEN_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_TXEN_Pos) /*!< Bit mask of CCAIDLE_TXEN field. */
+#define RADIO_SHORTS_CCAIDLE_TXEN_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_CCAIDLE_TXEN_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 11 : Shortcut between RXREADY event and CCASTART task */
+#define RADIO_SHORTS_RXREADY_CCASTART_Pos (11UL) /*!< Position of RXREADY_CCASTART field. */
+#define RADIO_SHORTS_RXREADY_CCASTART_Msk (0x1UL << RADIO_SHORTS_RXREADY_CCASTART_Pos) /*!< Bit mask of RXREADY_CCASTART field. */
+#define RADIO_SHORTS_RXREADY_CCASTART_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_RXREADY_CCASTART_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 6 : Shortcut between ADDRESS event and BCSTART task */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 5 : Shortcut between END event and START task */
+#define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */
+#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
+#define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between DISABLED event and RXEN task */
+#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */
+#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */
+#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between DISABLED event and TXEN task */
+#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
+#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */
+#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between END event and DISABLE task */
+#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */
+#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */
+#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between READY event and START task */
+#define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */
+#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */
+#define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: RADIO_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 23 : Write '1' to Enable interrupt for MHRMATCH event */
+#define RADIO_INTENSET_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */
+#define RADIO_INTENSET_MHRMATCH_Msk (0x1UL << RADIO_INTENSET_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */
+#define RADIO_INTENSET_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_MHRMATCH_Set (1UL) /*!< Enable */
+
+/* Bit 22 : Write '1' to Enable interrupt for RXREADY event */
+#define RADIO_INTENSET_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */
+#define RADIO_INTENSET_RXREADY_Msk (0x1UL << RADIO_INTENSET_RXREADY_Pos) /*!< Bit mask of RXREADY field. */
+#define RADIO_INTENSET_RXREADY_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_RXREADY_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_RXREADY_Set (1UL) /*!< Enable */
+
+/* Bit 21 : Write '1' to Enable interrupt for TXREADY event */
+#define RADIO_INTENSET_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */
+#define RADIO_INTENSET_TXREADY_Msk (0x1UL << RADIO_INTENSET_TXREADY_Pos) /*!< Bit mask of TXREADY field. */
+#define RADIO_INTENSET_TXREADY_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_TXREADY_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_TXREADY_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to Enable interrupt for RATEBOOST event */
+#define RADIO_INTENSET_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */
+#define RADIO_INTENSET_RATEBOOST_Msk (0x1UL << RADIO_INTENSET_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */
+#define RADIO_INTENSET_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_RATEBOOST_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to Enable interrupt for CCASTOPPED event */
+#define RADIO_INTENSET_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */
+#define RADIO_INTENSET_CCASTOPPED_Msk (0x1UL << RADIO_INTENSET_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */
+#define RADIO_INTENSET_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_CCASTOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to Enable interrupt for CCABUSY event */
+#define RADIO_INTENSET_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */
+#define RADIO_INTENSET_CCABUSY_Msk (0x1UL << RADIO_INTENSET_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */
+#define RADIO_INTENSET_CCABUSY_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_CCABUSY_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_CCABUSY_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to Enable interrupt for CCAIDLE event */
+#define RADIO_INTENSET_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */
+#define RADIO_INTENSET_CCAIDLE_Msk (0x1UL << RADIO_INTENSET_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */
+#define RADIO_INTENSET_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_CCAIDLE_Set (1UL) /*!< Enable */
+
+/* Bit 16 : Write '1' to Enable interrupt for EDSTOPPED event */
+#define RADIO_INTENSET_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */
+#define RADIO_INTENSET_EDSTOPPED_Msk (0x1UL << RADIO_INTENSET_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */
+#define RADIO_INTENSET_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_EDSTOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 15 : Write '1' to Enable interrupt for EDEND event */
+#define RADIO_INTENSET_EDEND_Pos (15UL) /*!< Position of EDEND field. */
+#define RADIO_INTENSET_EDEND_Msk (0x1UL << RADIO_INTENSET_EDEND_Pos) /*!< Bit mask of EDEND field. */
+#define RADIO_INTENSET_EDEND_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_EDEND_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_EDEND_Set (1UL) /*!< Enable */
+
+/* Bit 14 : Write '1' to Enable interrupt for FRAMESTART event */
+#define RADIO_INTENSET_FRAMESTART_Pos (14UL) /*!< Position of FRAMESTART field. */
+#define RADIO_INTENSET_FRAMESTART_Msk (0x1UL << RADIO_INTENSET_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */
+#define RADIO_INTENSET_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_FRAMESTART_Set (1UL) /*!< Enable */
+
+/* Bit 13 : Write '1' to Enable interrupt for CRCERROR event */
+#define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
+#define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
+#define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */
+
+/* Bit 12 : Write '1' to Enable interrupt for CRCOK event */
+#define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
+#define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
+#define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */
+
+/* Bit 10 : Write '1' to Enable interrupt for BCMATCH event */
+#define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
+#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
+#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for RSSIEND event */
+#define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
+#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
+#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for DEVMISS event */
+#define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
+#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
+#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable interrupt for DEVMATCH event */
+#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
+#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
+#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for DISABLED event */
+#define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
+#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
+#define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for END event */
+#define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */
+#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for PAYLOAD event */
+#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
+#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
+#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for ADDRESS event */
+#define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
+#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for READY event */
+#define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
+#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */
+
+/* Register: RADIO_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 23 : Write '1' to Disable interrupt for MHRMATCH event */
+#define RADIO_INTENCLR_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */
+#define RADIO_INTENCLR_MHRMATCH_Msk (0x1UL << RADIO_INTENCLR_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */
+#define RADIO_INTENCLR_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_MHRMATCH_Clear (1UL) /*!< Disable */
+
+/* Bit 22 : Write '1' to Disable interrupt for RXREADY event */
+#define RADIO_INTENCLR_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */
+#define RADIO_INTENCLR_RXREADY_Msk (0x1UL << RADIO_INTENCLR_RXREADY_Pos) /*!< Bit mask of RXREADY field. */
+#define RADIO_INTENCLR_RXREADY_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_RXREADY_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_RXREADY_Clear (1UL) /*!< Disable */
+
+/* Bit 21 : Write '1' to Disable interrupt for TXREADY event */
+#define RADIO_INTENCLR_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */
+#define RADIO_INTENCLR_TXREADY_Msk (0x1UL << RADIO_INTENCLR_TXREADY_Pos) /*!< Bit mask of TXREADY field. */
+#define RADIO_INTENCLR_TXREADY_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_TXREADY_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_TXREADY_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to Disable interrupt for RATEBOOST event */
+#define RADIO_INTENCLR_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */
+#define RADIO_INTENCLR_RATEBOOST_Msk (0x1UL << RADIO_INTENCLR_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */
+#define RADIO_INTENCLR_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_RATEBOOST_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to Disable interrupt for CCASTOPPED event */
+#define RADIO_INTENCLR_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */
+#define RADIO_INTENCLR_CCASTOPPED_Msk (0x1UL << RADIO_INTENCLR_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */
+#define RADIO_INTENCLR_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_CCASTOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to Disable interrupt for CCABUSY event */
+#define RADIO_INTENCLR_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */
+#define RADIO_INTENCLR_CCABUSY_Msk (0x1UL << RADIO_INTENCLR_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */
+#define RADIO_INTENCLR_CCABUSY_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_CCABUSY_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_CCABUSY_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to Disable interrupt for CCAIDLE event */
+#define RADIO_INTENCLR_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */
+#define RADIO_INTENCLR_CCAIDLE_Msk (0x1UL << RADIO_INTENCLR_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */
+#define RADIO_INTENCLR_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_CCAIDLE_Clear (1UL) /*!< Disable */
+
+/* Bit 16 : Write '1' to Disable interrupt for EDSTOPPED event */
+#define RADIO_INTENCLR_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */
+#define RADIO_INTENCLR_EDSTOPPED_Msk (0x1UL << RADIO_INTENCLR_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */
+#define RADIO_INTENCLR_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_EDSTOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 15 : Write '1' to Disable interrupt for EDEND event */
+#define RADIO_INTENCLR_EDEND_Pos (15UL) /*!< Position of EDEND field. */
+#define RADIO_INTENCLR_EDEND_Msk (0x1UL << RADIO_INTENCLR_EDEND_Pos) /*!< Bit mask of EDEND field. */
+#define RADIO_INTENCLR_EDEND_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_EDEND_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_EDEND_Clear (1UL) /*!< Disable */
+
+/* Bit 14 : Write '1' to Disable interrupt for FRAMESTART event */
+#define RADIO_INTENCLR_FRAMESTART_Pos (14UL) /*!< Position of FRAMESTART field. */
+#define RADIO_INTENCLR_FRAMESTART_Msk (0x1UL << RADIO_INTENCLR_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */
+#define RADIO_INTENCLR_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_FRAMESTART_Clear (1UL) /*!< Disable */
+
+/* Bit 13 : Write '1' to Disable interrupt for CRCERROR event */
+#define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
+#define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
+#define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 12 : Write '1' to Disable interrupt for CRCOK event */
+#define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
+#define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
+#define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */
+
+/* Bit 10 : Write '1' to Disable interrupt for BCMATCH event */
+#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
+#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
+#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for RSSIEND event */
+#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
+#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
+#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for DEVMISS event */
+#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
+#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
+#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable interrupt for DEVMATCH event */
+#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
+#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
+#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for DISABLED event */
+#define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
+#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
+#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for END event */
+#define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */
+#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for PAYLOAD event */
+#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
+#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
+#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for ADDRESS event */
+#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
+#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for READY event */
+#define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
+#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */
+
+/* Register: RADIO_CRCSTATUS */
+/* Description: CRC status */
+
+/* Bit 0 : CRC status of packet received */
+#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */
+#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */
+#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error */
+#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok */
+
+/* Register: RADIO_RXMATCH */
+/* Description: Received address */
+
+/* Bits 2..0 : Received address */
+#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */
+#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */
+
+/* Register: RADIO_RXCRC */
+/* Description: CRC field of previously received packet */
+
+/* Bits 23..0 : CRC field of previously received packet */
+#define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */
+#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */
+
+/* Register: RADIO_DAI */
+/* Description: Device address match index */
+
+/* Bits 2..0 : Device address match index */
+#define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */
+#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */
+
+/* Register: RADIO_PACKETPTR */
+/* Description: Packet pointer */
+
+/* Bits 31..0 : Packet pointer */
+#define RADIO_PACKETPTR_PACKETPTR_Pos (0UL) /*!< Position of PACKETPTR field. */
+#define RADIO_PACKETPTR_PACKETPTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos) /*!< Bit mask of PACKETPTR field. */
+
+/* Register: RADIO_FREQUENCY */
+/* Description: Frequency */
+
+/* Bit 8 : Channel map selection. */
+#define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */
+#define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */
+#define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHZ .. 2500 MHz */
+#define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHZ .. 2460 MHz */
+
+/* Bits 6..0 : Radio channel frequency */
+#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+
+/* Register: RADIO_TXPOWER */
+/* Description: Output power */
+
+/* Bits 7..0 : RADIO output power. */
+#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */
+#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */
+#define RADIO_TXPOWER_TXPOWER_0dBm (0x0UL) /*!< 0 dBm */
+#define RADIO_TXPOWER_TXPOWER_Pos2dBm (0x2UL) /*!< +2 dBm */
+#define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x3UL) /*!< +3 dBm */
+#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x4UL) /*!< +4 dBm */
+#define RADIO_TXPOWER_TXPOWER_Pos5dBm (0x5UL) /*!< +5 dBm */
+#define RADIO_TXPOWER_TXPOWER_Pos6dBm (0x6UL) /*!< +6 dBm */
+#define RADIO_TXPOWER_TXPOWER_Pos7dBm (0x7UL) /*!< +7 dBm */
+#define RADIO_TXPOWER_TXPOWER_Pos8dBm (0x8UL) /*!< +8 dBm */
+#define RADIO_TXPOWER_TXPOWER_Pos9dBm (0x9UL) /*!< +9 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< Deprecated enumerator -  -40 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */
+
+/* Register: RADIO_MODE */
+/* Description: Data rate and modulation */
+
+/* Bits 3..0 : Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation. */
+#define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbit/s Nordic proprietary radio mode */
+#define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbit/s Nordic proprietary radio mode */
+#define RADIO_MODE_MODE_Nrf_250Kbit (2UL) /*!< Deprecated enumerator -  250 kbit/s Nordic proprietary radio mode */
+#define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbit/s Bluetooth Low Energy */
+#define RADIO_MODE_MODE_Ble_2Mbit (4UL) /*!< 2 Mbit/s Bluetooth Low Energy */
+#define RADIO_MODE_MODE_Ble_LR125Kbit (5UL) /*!< Long range 125 kbit/s (TX Only - RX supports both) */
+#define RADIO_MODE_MODE_Ble_LR500Kbit (6UL) /*!< Long range 500 kbit/s (TX Only - RX supports both) */
+#define RADIO_MODE_MODE_Ieee802154_250Kbit (15UL) /*!< IEEE 802.15.4-2006 250 kbit/s */
+
+/* Register: RADIO_PCNF0 */
+/* Description: Packet configuration register 0 */
+
+/* Bits 30..29 : Length of TERM field in Long Range operation */
+#define RADIO_PCNF0_TERMLEN_Pos (29UL) /*!< Position of TERMLEN field. */
+#define RADIO_PCNF0_TERMLEN_Msk (0x3UL << RADIO_PCNF0_TERMLEN_Pos) /*!< Bit mask of TERMLEN field. */
+
+/* Bit 26 : Indicates if LENGTH field contains CRC or not */
+#define RADIO_PCNF0_CRCINC_Pos (26UL) /*!< Position of CRCINC field. */
+#define RADIO_PCNF0_CRCINC_Msk (0x1UL << RADIO_PCNF0_CRCINC_Pos) /*!< Bit mask of CRCINC field. */
+#define RADIO_PCNF0_CRCINC_Exclude (0UL) /*!< LENGTH does not contain CRC */
+#define RADIO_PCNF0_CRCINC_Include (1UL) /*!< LENGTH includes CRC */
+
+/* Bits 25..24 : Length of preamble on air. Decision point: TASKS_START task */
+#define RADIO_PCNF0_PLEN_Pos (24UL) /*!< Position of PLEN field. */
+#define RADIO_PCNF0_PLEN_Msk (0x3UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field. */
+#define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */
+#define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */
+#define RADIO_PCNF0_PLEN_32bitZero (2UL) /*!< 32-bit zero preamble - used for IEEE 802.15.4 */
+#define RADIO_PCNF0_PLEN_LongRange (3UL) /*!< Preamble - used for BTLE Long Range */
+
+/* Bits 23..22 : Length of Code Indicator - Long Range */
+#define RADIO_PCNF0_CILEN_Pos (22UL) /*!< Position of CILEN field. */
+#define RADIO_PCNF0_CILEN_Msk (0x3UL << RADIO_PCNF0_CILEN_Pos) /*!< Bit mask of CILEN field. */
+
+/* Bit 20 : Include or exclude S1 field in RAM */
+#define RADIO_PCNF0_S1INCL_Pos (20UL) /*!< Position of S1INCL field. */
+#define RADIO_PCNF0_S1INCL_Msk (0x1UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field. */
+#define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN &gt; 0 */
+#define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */
+
+/* Bits 19..16 : Length on air of S1 field in number of bits. */
+#define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */
+#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */
+
+/* Bit 8 : Length on air of S0 field in number of bytes. */
+#define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */
+#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */
+
+/* Bits 3..0 : Length on air of LENGTH field in number of bits. */
+#define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */
+#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */
+
+/* Register: RADIO_PCNF1 */
+/* Description: Packet configuration register 1 */
+
+/* Bit 25 : Enable or disable packet whitening */
+#define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */
+#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */
+#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */
+#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */
+
+/* Bit 24 : On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. */
+#define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */
+#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
+#define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least Significant bit on air first */
+#define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */
+
+/* Bits 18..16 : Base address length in number of bytes */
+#define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */
+#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */
+
+/* Bits 15..8 : Static length in number of bytes */
+#define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */
+#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */
+
+/* Bits 7..0 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. */
+#define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
+#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
+
+/* Register: RADIO_BASE0 */
+/* Description: Base address 0 */
+
+/* Bits 31..0 : Base address 0 */
+#define RADIO_BASE0_BASE0_Pos (0UL) /*!< Position of BASE0 field. */
+#define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field. */
+
+/* Register: RADIO_BASE1 */
+/* Description: Base address 1 */
+
+/* Bits 31..0 : Base address 1 */
+#define RADIO_BASE1_BASE1_Pos (0UL) /*!< Position of BASE1 field. */
+#define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field. */
+
+/* Register: RADIO_PREFIX0 */
+/* Description: Prefixes bytes for logical addresses 0-3 */
+
+/* Bits 31..24 : Address prefix 3. */
+#define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */
+#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */
+
+/* Bits 23..16 : Address prefix 2. */
+#define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */
+#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */
+
+/* Bits 15..8 : Address prefix 1. */
+#define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */
+#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */
+
+/* Bits 7..0 : Address prefix 0. */
+#define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */
+#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */
+
+/* Register: RADIO_PREFIX1 */
+/* Description: Prefixes bytes for logical addresses 4-7 */
+
+/* Bits 31..24 : Address prefix 7. */
+#define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */
+#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */
+
+/* Bits 23..16 : Address prefix 6. */
+#define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */
+#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */
+
+/* Bits 15..8 : Address prefix 5. */
+#define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */
+#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */
+
+/* Bits 7..0 : Address prefix 4. */
+#define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */
+#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */
+
+/* Register: RADIO_TXADDRESS */
+/* Description: Transmit address select */
+
+/* Bits 2..0 : Transmit address select */
+#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */
+#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */
+
+/* Register: RADIO_RXADDRESSES */
+/* Description: Receive address select */
+
+/* Bit 7 : Enable or disable reception on logical address 7. */
+#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */
+#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */
+#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable reception on logical address 6. */
+#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */
+#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */
+#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable reception on logical address 5. */
+#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */
+#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */
+#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable reception on logical address 4. */
+#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */
+#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */
+#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable reception on logical address 3. */
+#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */
+#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */
+#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable reception on logical address 2. */
+#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
+#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */
+#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable reception on logical address 1. */
+#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */
+#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */
+#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable reception on logical address 0. */
+#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */
+#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */
+#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */
+
+/* Register: RADIO_CRCCNF */
+/* Description: CRC configuration */
+
+/* Bits 9..8 : Include or exclude packet address field out of CRC calculation. */
+#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */
+#define RADIO_CRCCNF_SKIPADDR_Msk (0x3UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */
+#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< CRC calculation includes address field */
+#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */
+#define RADIO_CRCCNF_SKIPADDR_Ieee802154 (2UL) /*!< CRC calculation as per 802.15.4 standard. Starting at first byte after length field. */
+
+/* Bits 1..0 : CRC length in number of bytes. */
+#define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */
+#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */
+#define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */
+#define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */
+#define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */
+#define RADIO_CRCCNF_LEN_Three (3UL) /*!< CRC length is three bytes and CRC calculation is enabled */
+
+/* Register: RADIO_CRCPOLY */
+/* Description: CRC polynomial */
+
+/* Bits 23..0 : CRC polynomial */
+#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */
+#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */
+
+/* Register: RADIO_CRCINIT */
+/* Description: CRC initial value */
+
+/* Bits 23..0 : CRC initial value */
+#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */
+#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */
+
+/* Register: RADIO_TIFS */
+/* Description: Inter Frame Spacing in us */
+
+/* Bits 9..0 : Inter Frame Spacing in us */
+#define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */
+#define RADIO_TIFS_TIFS_Msk (0x3FFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */
+
+/* Register: RADIO_RSSISAMPLE */
+/* Description: RSSI sample */
+
+/* Bits 6..0 : RSSI sample */
+#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */
+#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */
+
+/* Register: RADIO_STATE */
+/* Description: Current radio state */
+
+/* Bits 3..0 : Current radio state */
+#define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */
+#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */
+#define RADIO_STATE_STATE_Disabled (0UL) /*!< RADIO is in the Disabled state */
+#define RADIO_STATE_STATE_RxRu (1UL) /*!< RADIO is in the RXRU state */
+#define RADIO_STATE_STATE_RxIdle (2UL) /*!< RADIO is in the RXIDLE state */
+#define RADIO_STATE_STATE_Rx (3UL) /*!< RADIO is in the RX state */
+#define RADIO_STATE_STATE_RxDisable (4UL) /*!< RADIO is in the RXDISABLED state */
+#define RADIO_STATE_STATE_TxRu (9UL) /*!< RADIO is in the TXRU state */
+#define RADIO_STATE_STATE_TxIdle (10UL) /*!< RADIO is in the TXIDLE state */
+#define RADIO_STATE_STATE_Tx (11UL) /*!< RADIO is in the TX state */
+#define RADIO_STATE_STATE_TxDisable (12UL) /*!< RADIO is in the TXDISABLED state */
+
+/* Register: RADIO_DATAWHITEIV */
+/* Description: Data whitening initial value */
+
+/* Bits 6..0 : Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. */
+#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */
+#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */
+
+/* Register: RADIO_BCC */
+/* Description: Bit counter compare */
+
+/* Bits 31..0 : Bit counter compare */
+#define RADIO_BCC_BCC_Pos (0UL) /*!< Position of BCC field. */
+#define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */
+
+/* Register: RADIO_DAB */
+/* Description: Description collection[0]:  Device address base segment 0 */
+
+/* Bits 31..0 : Device address base segment 0 */
+#define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */
+#define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */
+
+/* Register: RADIO_DAP */
+/* Description: Description collection[0]:  Device address prefix 0 */
+
+/* Bits 15..0 : Device address prefix 0 */
+#define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */
+#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */
+
+/* Register: RADIO_DACNF */
+/* Description: Device address match configuration */
+
+/* Bit 15 : TxAdd for device address 7 */
+#define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */
+#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */
+
+/* Bit 14 : TxAdd for device address 6 */
+#define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */
+#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */
+
+/* Bit 13 : TxAdd for device address 5 */
+#define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */
+#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */
+
+/* Bit 12 : TxAdd for device address 4 */
+#define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */
+#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */
+
+/* Bit 11 : TxAdd for device address 3 */
+#define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */
+#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */
+
+/* Bit 10 : TxAdd for device address 2 */
+#define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */
+#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */
+
+/* Bit 9 : TxAdd for device address 1 */
+#define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */
+#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */
+
+/* Bit 8 : TxAdd for device address 0 */
+#define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */
+#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */
+
+/* Bit 7 : Enable or disable device address matching using device address 7 */
+#define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */
+#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */
+#define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */
+
+/* Bit 6 : Enable or disable device address matching using device address 6 */
+#define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */
+#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */
+#define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */
+
+/* Bit 5 : Enable or disable device address matching using device address 5 */
+#define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */
+#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */
+#define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */
+
+/* Bit 4 : Enable or disable device address matching using device address 4 */
+#define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */
+#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */
+#define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */
+
+/* Bit 3 : Enable or disable device address matching using device address 3 */
+#define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */
+#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */
+#define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */
+
+/* Bit 2 : Enable or disable device address matching using device address 2 */
+#define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
+#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */
+#define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */
+
+/* Bit 1 : Enable or disable device address matching using device address 1 */
+#define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */
+#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */
+#define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */
+
+/* Bit 0 : Enable or disable device address matching using device address 0 */
+#define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */
+#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */
+#define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */
+
+/* Register: RADIO_MODECNF0 */
+/* Description: Radio mode configuration register 0 */
+
+/* Bits 9..8 : Default TX value */
+#define RADIO_MODECNF0_DTX_Pos (8UL) /*!< Position of DTX field. */
+#define RADIO_MODECNF0_DTX_Msk (0x3UL << RADIO_MODECNF0_DTX_Pos) /*!< Bit mask of DTX field. */
+#define RADIO_MODECNF0_DTX_B1 (0UL) /*!< Transmit '1' */
+#define RADIO_MODECNF0_DTX_B0 (1UL) /*!< Transmit '0' */
+#define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */
+
+/* Bit 0 : Radio ramp-up time */
+#define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */
+#define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */
+#define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN), compatible with firmware written for nRF51 */
+#define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST), see electrical specification for more information */
+
+/* Register: RADIO_SFD */
+/* Description: IEEE 802.15.4 Start of Frame Delimiter */
+
+/* Bits 7..0 : IEEE 802.15.4 Start of Frame Delimiter */
+#define RADIO_SFD_SFD_Pos (0UL) /*!< Position of SFD field. */
+#define RADIO_SFD_SFD_Msk (0xFFUL << RADIO_SFD_SFD_Pos) /*!< Bit mask of SFD field. */
+
+/* Register: RADIO_EDCNT */
+/* Description: IEEE 802.15.4 Energy Detect Loop Count */
+
+/* Bits 20..0 : IEEE 802.15.4 Energy Detect Loop Count */
+#define RADIO_EDCNT_EDCNT_Pos (0UL) /*!< Position of EDCNT field. */
+#define RADIO_EDCNT_EDCNT_Msk (0x1FFFFFUL << RADIO_EDCNT_EDCNT_Pos) /*!< Bit mask of EDCNT field. */
+
+/* Register: RADIO_EDSAMPLE */
+/* Description: IEEE 802.15.4 Energy Detect Level */
+
+/* Bits 7..0 : IEEE 802.15.4 Energy Detect Level */
+#define RADIO_EDSAMPLE_EDLVL_Pos (0UL) /*!< Position of EDLVL field. */
+#define RADIO_EDSAMPLE_EDLVL_Msk (0xFFUL << RADIO_EDSAMPLE_EDLVL_Pos) /*!< Bit mask of EDLVL field. */
+
+/* Register: RADIO_CCACTRL */
+/* Description: IEEE 802.15.4 Clear Channel Assessment Control */
+
+/* Bits 31..24 : Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled. */
+#define RADIO_CCACTRL_CCACORRCNT_Pos (24UL) /*!< Position of CCACORRCNT field. */
+#define RADIO_CCACTRL_CCACORRCNT_Msk (0xFFUL << RADIO_CCACTRL_CCACORRCNT_Pos) /*!< Bit mask of CCACORRCNT field. */
+
+/* Bits 23..16 : CCA Correlator Busy Threshold. Only relevant to CarrierMode, CarrierAndEdMode and CarrierOrEdMode. */
+#define RADIO_CCACTRL_CCACORRTHRES_Pos (16UL) /*!< Position of CCACORRTHRES field. */
+#define RADIO_CCACTRL_CCACORRTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCACORRTHRES_Pos) /*!< Bit mask of CCACORRTHRES field. */
+
+/* Bits 15..8 : CCA Energy Busy Threshold. Used in all the CCA modes except CarrierMode. */
+#define RADIO_CCACTRL_CCAEDTHRES_Pos (8UL) /*!< Position of CCAEDTHRES field. */
+#define RADIO_CCACTRL_CCAEDTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCAEDTHRES_Pos) /*!< Bit mask of CCAEDTHRES field. */
+
+/* Bits 2..0 : CCA Mode Of Operation */
+#define RADIO_CCACTRL_CCAMODE_Pos (0UL) /*!< Position of CCAMODE field. */
+#define RADIO_CCACTRL_CCAMODE_Msk (0x7UL << RADIO_CCACTRL_CCAMODE_Pos) /*!< Bit mask of CCAMODE field. */
+#define RADIO_CCACTRL_CCAMODE_EdMode (0UL) /*!< Energy Above Threshold */
+#define RADIO_CCACTRL_CCAMODE_CarrierMode (1UL) /*!< Carrier Seen */
+#define RADIO_CCACTRL_CCAMODE_CarrierAndEdMode (2UL) /*!< Energy Above Threshold AND Carrier Seen */
+#define RADIO_CCACTRL_CCAMODE_CarrierOrEdMode (3UL) /*!< Energy Above Threshold OR Carrier Seen */
+#define RADIO_CCACTRL_CCAMODE_EdModeTest1 (4UL) /*!< Energy Above Threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. */
+
+/* Register: RADIO_POWER */
+/* Description: Peripheral power control */
+
+/* Bit 0 : Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. */
+#define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define RADIO_POWER_POWER_Disabled (0UL) /*!< Peripheral is powered off */
+#define RADIO_POWER_POWER_Enabled (1UL) /*!< Peripheral is powered on */
+
+
+/* Peripheral: RNG */
+/* Description: Random Number Generator */
+
+/* Register: RNG_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 0 : Shortcut between VALRDY event and STOP task */
+#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */
+#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */
+#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: RNG_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 0 : Write '1' to Enable interrupt for VALRDY event */
+#define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
+#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
+#define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */
+#define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */
+#define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */
+
+/* Register: RNG_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 0 : Write '1' to Disable interrupt for VALRDY event */
+#define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
+#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
+#define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */
+#define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */
+#define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */
+
+/* Register: RNG_CONFIG */
+/* Description: Configuration register */
+
+/* Bit 0 : Bias correction */
+#define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */
+#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */
+#define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Disabled */
+#define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */
+
+/* Register: RNG_VALUE */
+/* Description: Output random number */
+
+/* Bits 7..0 : Generated random number */
+#define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
+#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
+
+
+/* Peripheral: RTC */
+/* Description: Real time counter 0 */
+
+/* Register: RTC_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */
+#define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */
+#define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */
+#define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
+
+/* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */
+#define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for OVRFLW event */
+#define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for TICK event */
+#define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */
+
+/* Register: RTC_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */
+#define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */
+#define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */
+#define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
+
+/* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */
+#define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for OVRFLW event */
+#define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for TICK event */
+#define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */
+
+/* Register: RTC_EVTEN */
+/* Description: Enable or disable event routing */
+
+/* Bit 19 : Enable or disable event routing for COMPARE[3] event */
+#define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */
+
+/* Bit 18 : Enable or disable event routing for COMPARE[2] event */
+#define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */
+
+/* Bit 17 : Enable or disable event routing for COMPARE[1] event */
+#define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */
+
+/* Bit 16 : Enable or disable event routing for COMPARE[0] event */
+#define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable event routing for OVRFLW event */
+#define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable event routing for TICK event */
+#define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */
+
+/* Register: RTC_EVTENSET */
+/* Description: Enable event routing */
+
+/* Bit 19 : Write '1' to Enable event routing for COMPARE[3] event */
+#define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to Enable event routing for COMPARE[2] event */
+#define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to Enable event routing for COMPARE[1] event */
+#define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */
+
+/* Bit 16 : Write '1' to Enable event routing for COMPARE[0] event */
+#define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable event routing for OVRFLW event */
+#define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable event routing for TICK event */
+#define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */
+
+/* Register: RTC_EVTENCLR */
+/* Description: Disable event routing */
+
+/* Bit 19 : Write '1' to Disable event routing for COMPARE[3] event */
+#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to Disable event routing for COMPARE[2] event */
+#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to Disable event routing for COMPARE[1] event */
+#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
+
+/* Bit 16 : Write '1' to Disable event routing for COMPARE[0] event */
+#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable event routing for OVRFLW event */
+#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable event routing for TICK event */
+#define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */
+
+/* Register: RTC_COUNTER */
+/* Description: Current COUNTER value */
+
+/* Bits 23..0 : Counter value */
+#define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
+#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
+
+/* Register: RTC_PRESCALER */
+/* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped */
+
+/* Bits 11..0 : Prescaler value */
+#define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
+#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
+
+/* Register: RTC_CC */
+/* Description: Description collection[0]:  Compare register 0 */
+
+/* Bits 23..0 : Compare value */
+#define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
+#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
+
+
+/* Peripheral: SAADC */
+/* Description: Analog to Digital Converter */
+
+/* Register: SAADC_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 21 : Enable or disable interrupt for CH[7].LIMITL event */
+#define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
+#define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
+#define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 20 : Enable or disable interrupt for CH[7].LIMITH event */
+#define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
+#define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
+#define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 19 : Enable or disable interrupt for CH[6].LIMITL event */
+#define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
+#define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
+#define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 18 : Enable or disable interrupt for CH[6].LIMITH event */
+#define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
+#define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
+#define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 17 : Enable or disable interrupt for CH[5].LIMITL event */
+#define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
+#define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
+#define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 16 : Enable or disable interrupt for CH[5].LIMITH event */
+#define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
+#define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
+#define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 15 : Enable or disable interrupt for CH[4].LIMITL event */
+#define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
+#define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
+#define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 14 : Enable or disable interrupt for CH[4].LIMITH event */
+#define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
+#define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
+#define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 13 : Enable or disable interrupt for CH[3].LIMITL event */
+#define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
+#define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
+#define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 12 : Enable or disable interrupt for CH[3].LIMITH event */
+#define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
+#define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
+#define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 11 : Enable or disable interrupt for CH[2].LIMITL event */
+#define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
+#define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
+#define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 10 : Enable or disable interrupt for CH[2].LIMITH event */
+#define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
+#define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
+#define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for CH[1].LIMITL event */
+#define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
+#define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
+#define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 8 : Enable or disable interrupt for CH[1].LIMITH event */
+#define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
+#define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
+#define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable interrupt for CH[0].LIMITL event */
+#define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
+#define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
+#define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable interrupt for CH[0].LIMITH event */
+#define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
+#define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
+#define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable interrupt for STOPPED event */
+#define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
+#define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for CALIBRATEDONE event */
+#define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
+#define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
+#define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable interrupt for RESULTDONE event */
+#define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
+#define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
+#define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for DONE event */
+#define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */
+#define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */
+#define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for END event */
+#define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */
+#define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */
+#define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for STARTED event */
+#define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */
+
+/* Register: SAADC_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 21 : Write '1' to Enable interrupt for CH[7].LIMITL event */
+#define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
+#define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
+#define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to Enable interrupt for CH[7].LIMITH event */
+#define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
+#define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
+#define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to Enable interrupt for CH[6].LIMITL event */
+#define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
+#define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
+#define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to Enable interrupt for CH[6].LIMITH event */
+#define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
+#define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
+#define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to Enable interrupt for CH[5].LIMITL event */
+#define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
+#define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
+#define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 16 : Write '1' to Enable interrupt for CH[5].LIMITH event */
+#define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
+#define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
+#define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 15 : Write '1' to Enable interrupt for CH[4].LIMITL event */
+#define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
+#define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
+#define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 14 : Write '1' to Enable interrupt for CH[4].LIMITH event */
+#define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
+#define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
+#define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 13 : Write '1' to Enable interrupt for CH[3].LIMITL event */
+#define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
+#define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
+#define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 12 : Write '1' to Enable interrupt for CH[3].LIMITH event */
+#define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
+#define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
+#define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 11 : Write '1' to Enable interrupt for CH[2].LIMITL event */
+#define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
+#define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
+#define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 10 : Write '1' to Enable interrupt for CH[2].LIMITH event */
+#define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
+#define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
+#define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to Enable interrupt for CH[1].LIMITL event */
+#define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
+#define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
+#define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 8 : Write '1' to Enable interrupt for CH[1].LIMITH event */
+#define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
+#define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
+#define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for CH[0].LIMITL event */
+#define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
+#define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
+#define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for CH[0].LIMITH event */
+#define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
+#define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
+#define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable interrupt for STOPPED event */
+#define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
+#define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for CALIBRATEDONE event */
+#define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
+#define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
+#define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for RESULTDONE event */
+#define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
+#define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
+#define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for DONE event */
+#define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */
+#define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
+#define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for END event */
+#define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */
+#define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for STARTED event */
+#define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */
+
+/* Register: SAADC_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 21 : Write '1' to Disable interrupt for CH[7].LIMITL event */
+#define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
+#define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
+#define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to Disable interrupt for CH[7].LIMITH event */
+#define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
+#define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
+#define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to Disable interrupt for CH[6].LIMITL event */
+#define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
+#define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
+#define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to Disable interrupt for CH[6].LIMITH event */
+#define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
+#define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
+#define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to Disable interrupt for CH[5].LIMITL event */
+#define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
+#define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
+#define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 16 : Write '1' to Disable interrupt for CH[5].LIMITH event */
+#define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
+#define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
+#define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 15 : Write '1' to Disable interrupt for CH[4].LIMITL event */
+#define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
+#define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
+#define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 14 : Write '1' to Disable interrupt for CH[4].LIMITH event */
+#define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
+#define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
+#define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 13 : Write '1' to Disable interrupt for CH[3].LIMITL event */
+#define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
+#define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
+#define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 12 : Write '1' to Disable interrupt for CH[3].LIMITH event */
+#define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
+#define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
+#define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 11 : Write '1' to Disable interrupt for CH[2].LIMITL event */
+#define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
+#define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
+#define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 10 : Write '1' to Disable interrupt for CH[2].LIMITH event */
+#define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
+#define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
+#define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to Disable interrupt for CH[1].LIMITL event */
+#define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
+#define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
+#define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 8 : Write '1' to Disable interrupt for CH[1].LIMITH event */
+#define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
+#define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
+#define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for CH[0].LIMITL event */
+#define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
+#define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
+#define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for CH[0].LIMITH event */
+#define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
+#define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
+#define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable interrupt for STOPPED event */
+#define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
+#define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for CALIBRATEDONE event */
+#define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
+#define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
+#define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for RESULTDONE event */
+#define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
+#define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
+#define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for DONE event */
+#define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */
+#define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
+#define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for END event */
+#define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
+#define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for STARTED event */
+#define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
+
+/* Register: SAADC_STATUS */
+/* Description: Status */
+
+/* Bit 0 : Status */
+#define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
+#define SAADC_STATUS_STATUS_Ready (0UL) /*!< ADC is ready. No on-going conversion. */
+#define SAADC_STATUS_STATUS_Busy (1UL) /*!< ADC is busy. Conversion in progress. */
+
+/* Register: SAADC_ENABLE */
+/* Description: Enable or disable ADC */
+
+/* Bit 0 : Enable or disable ADC */
+#define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable ADC */
+#define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */
+
+/* Register: SAADC_CH_PSELP */
+/* Description: Description cluster[0]:  Input positive pin selection for CH[0] */
+
+/* Bits 4..0 : Analog positive input channel */
+#define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */
+#define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */
+#define SAADC_CH_PSELP_PSELP_NC (0UL) /*!< Not connected */
+#define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL) /*!< AIN0 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput2 (3UL) /*!< AIN2 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput3 (4UL) /*!< AIN3 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput4 (5UL) /*!< AIN4 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL) /*!< AIN5 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL) /*!< AIN6 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL) /*!< AIN7 */
+#define SAADC_CH_PSELP_PSELP_VDD (9UL) /*!< VDD */
+#define SAADC_CH_PSELP_PSELP_VDDHDIV5 (0x11UL) /*!< VDDH/5 */
+
+/* Register: SAADC_CH_PSELN */
+/* Description: Description cluster[0]:  Input negative pin selection for CH[0] */
+
+/* Bits 4..0 : Analog negative input, enables differential channel */
+#define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */
+#define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */
+#define SAADC_CH_PSELN_PSELN_NC (0UL) /*!< Not connected */
+#define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL) /*!< AIN0 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput2 (3UL) /*!< AIN2 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput3 (4UL) /*!< AIN3 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput4 (5UL) /*!< AIN4 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL) /*!< AIN5 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL) /*!< AIN6 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL) /*!< AIN7 */
+#define SAADC_CH_PSELN_PSELN_VDD (9UL) /*!< VDD */
+#define SAADC_CH_PSELN_PSELN_VDDHDIV5 (0x11UL) /*!< VDDH/5 */
+
+/* Register: SAADC_CH_CONFIG */
+/* Description: Description cluster[0]:  Input configuration for CH[0] */
+
+/* Bit 24 : Enable burst mode */
+#define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */
+#define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */
+#define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */
+#define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */
+
+/* Bit 20 : Enable differential mode */
+#define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */
+#define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
+#define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to GND */
+#define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */
+
+/* Bits 18..16 : Acquisition time, the time the ADC uses to sample the input voltage */
+#define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */
+#define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */
+#define SAADC_CH_CONFIG_TACQ_3us (0UL) /*!< 3 us */
+#define SAADC_CH_CONFIG_TACQ_5us (1UL) /*!< 5 us */
+#define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */
+#define SAADC_CH_CONFIG_TACQ_15us (3UL) /*!< 15 us */
+#define SAADC_CH_CONFIG_TACQ_20us (4UL) /*!< 20 us */
+#define SAADC_CH_CONFIG_TACQ_40us (5UL) /*!< 40 us */
+
+/* Bit 12 : Reference control */
+#define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */
+#define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
+#define SAADC_CH_CONFIG_REFSEL_Internal (0UL) /*!< Internal reference (0.6 V) */
+#define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD/4 as reference */
+
+/* Bits 10..8 : Gain control */
+#define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */
+#define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */
+#define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) /*!< 1/6 */
+#define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL) /*!< 1/5 */
+#define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */
+#define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL) /*!< 1/3 */
+#define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */
+#define SAADC_CH_CONFIG_GAIN_Gain1 (5UL) /*!< 1 */
+#define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */
+#define SAADC_CH_CONFIG_GAIN_Gain4 (7UL) /*!< 4 */
+
+/* Bits 5..4 : Negative channel resistor control */
+#define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */
+#define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */
+#define SAADC_CH_CONFIG_RESN_Bypass (0UL) /*!< Bypass resistor ladder */
+#define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */
+#define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */
+#define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD/2 */
+
+/* Bits 1..0 : Positive channel resistor control */
+#define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */
+#define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */
+#define SAADC_CH_CONFIG_RESP_Bypass (0UL) /*!< Bypass resistor ladder */
+#define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */
+#define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */
+#define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */
+
+/* Register: SAADC_CH_LIMIT */
+/* Description: Description cluster[0]:  High/low limits for event monitoring a channel */
+
+/* Bits 31..16 : High level limit */
+#define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */
+#define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */
+
+/* Bits 15..0 : Low level limit */
+#define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */
+#define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */
+
+/* Register: SAADC_RESOLUTION */
+/* Description: Resolution configuration */
+
+/* Bits 2..0 : Set the resolution */
+#define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */
+#define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */
+#define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bit */
+#define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bit */
+#define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bit */
+#define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bit */
+
+/* Register: SAADC_OVERSAMPLE */
+/* Description: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */
+
+/* Bits 3..0 : Oversample control */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0UL) /*!< Bypass oversampling */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (3UL) /*!< Oversample 8x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (4UL) /*!< Oversample 16x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (5UL) /*!< Oversample 32x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (6UL) /*!< Oversample 64x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (7UL) /*!< Oversample 128x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (8UL) /*!< Oversample 256x */
+
+/* Register: SAADC_SAMPLERATE */
+/* Description: Controls normal or continuous sample rate */
+
+/* Bit 12 : Select mode for sample rate control */
+#define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */
+#define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define SAADC_SAMPLERATE_MODE_Task (0UL) /*!< Rate is controlled from SAMPLE task */
+#define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */
+
+/* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */
+#define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */
+#define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */
+
+/* Register: SAADC_RESULT_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SAADC_RESULT_MAXCNT */
+/* Description: Maximum number of buffer words to transfer */
+
+/* Bits 14..0 : Maximum number of buffer words to transfer */
+#define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SAADC_RESULT_AMOUNT */
+/* Description: Number of buffer words transferred since last START */
+
+/* Bits 14..0 : Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. */
+#define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+
+/* Peripheral: SPI */
+/* Description: Serial Peripheral Interface 0 */
+
+/* Register: SPI_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 2 : Write '1' to Enable interrupt for READY event */
+#define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */
+#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
+#define SPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
+#define SPI_INTENSET_READY_Set (1UL) /*!< Enable */
+
+/* Register: SPI_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 2 : Write '1' to Disable interrupt for READY event */
+#define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */
+#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
+#define SPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
+#define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable */
+
+/* Register: SPI_ENABLE */
+/* Description: Enable SPI */
+
+/* Bits 3..0 : Enable or disable SPI */
+#define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define SPI_ENABLE_ENABLE_Msk (0xFUL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define SPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI */
+#define SPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SPI */
+
+/* Register: SPI_PSEL_SCK */
+/* Description: Pin select for SCK */
+
+/* Bit 31 : Connection */
+#define SPI_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPI_PSEL_SCK_CONNECT_Msk (0x1UL << SPI_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPI_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
+#define SPI_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define SPI_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define SPI_PSEL_SCK_PORT_Msk (0x3UL << SPI_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define SPI_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPI_PSEL_SCK_PIN_Msk (0x1FUL << SPI_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPI_PSEL_MOSI */
+/* Description: Pin select for MOSI signal */
+
+/* Bit 31 : Connection */
+#define SPI_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPI_PSEL_MOSI_CONNECT_Msk (0x1UL << SPI_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPI_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
+#define SPI_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define SPI_PSEL_MOSI_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define SPI_PSEL_MOSI_PORT_Msk (0x3UL << SPI_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define SPI_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPI_PSEL_MOSI_PIN_Msk (0x1FUL << SPI_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPI_PSEL_MISO */
+/* Description: Pin select for MISO signal */
+
+/* Bit 31 : Connection */
+#define SPI_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPI_PSEL_MISO_CONNECT_Msk (0x1UL << SPI_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPI_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
+#define SPI_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define SPI_PSEL_MISO_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define SPI_PSEL_MISO_PORT_Msk (0x3UL << SPI_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define SPI_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPI_PSEL_MISO_PIN_Msk (0x1FUL << SPI_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPI_RXD */
+/* Description: RXD register */
+
+/* Bits 7..0 : RX data received. Double buffered */
+#define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
+#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
+
+/* Register: SPI_TXD */
+/* Description: TXD register */
+
+/* Bits 7..0 : TX data to send. Double buffered */
+#define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
+#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
+
+/* Register: SPI_FREQUENCY */
+/* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */
+
+/* Bits 31..0 : SPI master data rate */
+#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
+#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
+#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
+#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
+#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
+#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
+#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
+
+/* Register: SPI_CONFIG */
+/* Description: Configuration register */
+
+/* Bit 2 : Serial clock (SCK) polarity */
+#define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
+#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
+#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
+#define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
+
+/* Bit 1 : Serial clock (SCK) phase */
+#define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
+#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
+#define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
+#define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
+
+/* Bit 0 : Bit order */
+#define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
+#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
+#define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
+#define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
+
+
+/* Peripheral: SPIM */
+/* Description: Serial Peripheral Interface Master with EasyDMA 0 */
+
+/* Register: SPIM_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 17 : Shortcut between END event and START task */
+#define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */
+#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
+#define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
+#define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: SPIM_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 19 : Write '1' to Enable interrupt for STARTED event */
+#define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */
+#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */
+
+/* Bit 8 : Write '1' to Enable interrupt for ENDTX event */
+#define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for END event */
+#define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */
+#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
+#define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
+#define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Register: SPIM_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 19 : Write '1' to Disable interrupt for STARTED event */
+#define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */
+#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 8 : Write '1' to Disable interrupt for ENDTX event */
+#define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for END event */
+#define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */
+#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
+#define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
+#define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Register: SPIM_STALLSTAT */
+/* Description: Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU. */
+
+/* Bit 1 : Stall status for EasyDMA RAM writes */
+#define SPIM_STALLSTAT_RX_Pos (1UL) /*!< Position of RX field. */
+#define SPIM_STALLSTAT_RX_Msk (0x1UL << SPIM_STALLSTAT_RX_Pos) /*!< Bit mask of RX field. */
+#define SPIM_STALLSTAT_RX_NOSTALL (0UL) /*!< No stall */
+#define SPIM_STALLSTAT_RX_STALL (1UL) /*!< A stall has occurred */
+
+/* Bit 0 : Stall status for EasyDMA RAM reads */
+#define SPIM_STALLSTAT_TX_Pos (0UL) /*!< Position of TX field. */
+#define SPIM_STALLSTAT_TX_Msk (0x1UL << SPIM_STALLSTAT_TX_Pos) /*!< Bit mask of TX field. */
+#define SPIM_STALLSTAT_TX_NOSTALL (0UL) /*!< No stall */
+#define SPIM_STALLSTAT_TX_STALL (1UL) /*!< A stall has occurred */
+
+/* Register: SPIM_ENABLE */
+/* Description: Enable SPIM */
+
+/* Bits 3..0 : Enable or disable SPIM */
+#define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */
+#define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */
+
+/* Register: SPIM_PSEL_SCK */
+/* Description: Pin select for SCK */
+
+/* Bit 31 : Connection */
+#define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define SPIM_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define SPIM_PSEL_SCK_PORT_Msk (0x3UL << SPIM_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIM_PSEL_MOSI */
+/* Description: Pin select for MOSI signal */
+
+/* Bit 31 : Connection */
+#define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define SPIM_PSEL_MOSI_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define SPIM_PSEL_MOSI_PORT_Msk (0x3UL << SPIM_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIM_PSEL_MISO */
+/* Description: Pin select for MISO signal */
+
+/* Bit 31 : Connection */
+#define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define SPIM_PSEL_MISO_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define SPIM_PSEL_MISO_PORT_Msk (0x3UL << SPIM_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIM_PSEL_CSN */
+/* Description: Pin select for CSN */
+
+/* Bit 31 : Connection */
+#define SPIM_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIM_PSEL_CSN_CONNECT_Msk (0x1UL << SPIM_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIM_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIM_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define SPIM_PSEL_CSN_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define SPIM_PSEL_CSN_PORT_Msk (0x3UL << SPIM_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define SPIM_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIM_PSEL_CSN_PIN_Msk (0x1FUL << SPIM_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIM_FREQUENCY */
+/* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */
+
+/* Bits 31..0 : SPI master data rate */
+#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
+#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
+#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
+#define SPIM_FREQUENCY_FREQUENCY_M16 (0x0A000000UL) /*!< 16 Mbps */
+#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
+#define SPIM_FREQUENCY_FREQUENCY_M32 (0x14000000UL) /*!< 32 Mbps */
+#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
+#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
+#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
+
+/* Register: SPIM_RXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SPIM_RXD_MAXCNT */
+/* Description: Maximum number of bytes in receive buffer */
+
+/* Bits 15..0 : Maximum number of bytes in receive buffer */
+#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SPIM_RXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 15..0 : Number of bytes transferred in the last transaction */
+#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: SPIM_RXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 1..0 : List type */
+#define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define SPIM_RXD_LIST_LIST_Msk (0x3UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: SPIM_TXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SPIM_TXD_MAXCNT */
+/* Description: Number of bytes in transmit buffer */
+
+/* Bits 15..0 : Maximum number of bytes in transmit buffer */
+#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SPIM_TXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 15..0 : Number of bytes transferred in the last transaction */
+#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: SPIM_TXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 1..0 : List type */
+#define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define SPIM_TXD_LIST_LIST_Msk (0x3UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: SPIM_CONFIG */
+/* Description: Configuration register */
+
+/* Bit 2 : Serial clock (SCK) polarity */
+#define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
+#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
+#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
+#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
+
+/* Bit 1 : Serial clock (SCK) phase */
+#define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
+#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
+#define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
+#define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
+
+/* Bit 0 : Bit order */
+#define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
+#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
+#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
+#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
+
+/* Register: SPIM_IFTIMING_RXDELAY */
+/* Description: Sample delay for input serial data on MISO */
+
+/* Bits 2..0 : Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK. */
+#define SPIM_IFTIMING_RXDELAY_RXDELAY_Pos (0UL) /*!< Position of RXDELAY field. */
+#define SPIM_IFTIMING_RXDELAY_RXDELAY_Msk (0x7UL << SPIM_IFTIMING_RXDELAY_RXDELAY_Pos) /*!< Bit mask of RXDELAY field. */
+
+/* Register: SPIM_IFTIMING_CSNDUR */
+/* Description: Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions */
+
+/* Bits 7..0 : Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns). */
+#define SPIM_IFTIMING_CSNDUR_CSNDUR_Pos (0UL) /*!< Position of CSNDUR field. */
+#define SPIM_IFTIMING_CSNDUR_CSNDUR_Msk (0xFFUL << SPIM_IFTIMING_CSNDUR_CSNDUR_Pos) /*!< Bit mask of CSNDUR field. */
+
+/* Register: SPIM_ORC */
+/* Description: Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT */
+
+/* Bits 7..0 : Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT. */
+#define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
+#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
+
+
+/* Peripheral: SPIS */
+/* Description: SPI Slave 0 */
+
+/* Register: SPIS_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 2 : Shortcut between END event and ACQUIRE task */
+#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
+#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
+#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */
+#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: SPIS_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 10 : Write '1' to Enable interrupt for ACQUIRED event */
+#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
+#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
+#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
+#define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for END event */
+#define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
+#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Register: SPIS_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 10 : Write '1' to Disable interrupt for ACQUIRED event */
+#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
+#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
+#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
+#define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for END event */
+#define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
+#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Register: SPIS_SEMSTAT */
+/* Description: Semaphore status register */
+
+/* Bits 1..0 : Semaphore status */
+#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
+#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
+#define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */
+#define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */
+#define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */
+#define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */
+
+/* Register: SPIS_STATUS */
+/* Description: Status from last transaction */
+
+/* Bit 1 : RX buffer overflow detected, and prevented */
+#define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
+#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
+#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */
+#define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */
+#define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */
+
+/* Bit 0 : TX buffer over-read detected, and prevented */
+#define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
+#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
+#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */
+#define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */
+#define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */
+
+/* Register: SPIS_ENABLE */
+/* Description: Enable SPI slave */
+
+/* Bits 3..0 : Enable or disable SPI slave */
+#define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */
+#define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */
+
+/* Register: SPIS_PSEL_SCK */
+/* Description: Pin select for SCK */
+
+/* Bit 31 : Connection */
+#define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define SPIS_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define SPIS_PSEL_SCK_PORT_Msk (0x3UL << SPIS_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIS_PSEL_MISO */
+/* Description: Pin select for MISO signal */
+
+/* Bit 31 : Connection */
+#define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define SPIS_PSEL_MISO_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define SPIS_PSEL_MISO_PORT_Msk (0x3UL << SPIS_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIS_PSEL_MOSI */
+/* Description: Pin select for MOSI signal */
+
+/* Bit 31 : Connection */
+#define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define SPIS_PSEL_MOSI_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define SPIS_PSEL_MOSI_PORT_Msk (0x3UL << SPIS_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIS_PSEL_CSN */
+/* Description: Pin select for CSN signal */
+
+/* Bit 31 : Connection */
+#define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define SPIS_PSEL_CSN_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define SPIS_PSEL_CSN_PORT_Msk (0x3UL << SPIS_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIS_RXD_PTR */
+/* Description: RXD data pointer */
+
+/* Bits 31..0 : RXD data pointer */
+#define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SPIS_RXD_MAXCNT */
+/* Description: Maximum number of bytes in receive buffer */
+
+/* Bits 7..0 : Maximum number of bytes in receive buffer */
+#define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SPIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SPIS_RXD_AMOUNT */
+/* Description: Number of bytes received in last granted transaction */
+
+/* Bits 7..0 : Number of bytes received in the last granted transaction */
+#define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SPIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: SPIS_TXD_PTR */
+/* Description: TXD data pointer */
+
+/* Bits 31..0 : TXD data pointer */
+#define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SPIS_TXD_MAXCNT */
+/* Description: Maximum number of bytes in transmit buffer */
+
+/* Bits 7..0 : Maximum number of bytes in transmit buffer */
+#define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SPIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SPIS_TXD_AMOUNT */
+/* Description: Number of bytes transmitted in last granted transaction */
+
+/* Bits 7..0 : Number of bytes transmitted in last granted transaction */
+#define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SPIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: SPIS_CONFIG */
+/* Description: Configuration register */
+
+/* Bit 2 : Serial clock (SCK) polarity */
+#define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
+#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
+#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
+#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
+
+/* Bit 1 : Serial clock (SCK) phase */
+#define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
+#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
+#define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
+#define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
+
+/* Bit 0 : Bit order */
+#define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
+#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
+#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
+#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
+
+/* Register: SPIS_DEF */
+/* Description: Default character. Character clocked out in case of an ignored transaction. */
+
+/* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */
+#define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
+#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
+
+/* Register: SPIS_ORC */
+/* Description: Over-read character */
+
+/* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */
+#define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
+#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
+
+
+/* Peripheral: TEMP */
+/* Description: Temperature Sensor */
+
+/* Register: TEMP_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 0 : Write '1' to Enable interrupt for DATARDY event */
+#define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
+#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
+#define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */
+#define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */
+#define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */
+
+/* Register: TEMP_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 0 : Write '1' to Disable interrupt for DATARDY event */
+#define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
+#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
+#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */
+#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */
+#define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */
+
+/* Register: TEMP_TEMP */
+/* Description: Temperature in degC (0.25deg steps) */
+
+/* Bits 31..0 : Temperature in degC (0.25deg steps) */
+#define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */
+#define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */
+
+/* Register: TEMP_A0 */
+/* Description: Slope of 1st piece wise linear function */
+
+/* Bits 11..0 : Slope of 1st piece wise linear function */
+#define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */
+#define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */
+
+/* Register: TEMP_A1 */
+/* Description: Slope of 2nd piece wise linear function */
+
+/* Bits 11..0 : Slope of 2nd piece wise linear function */
+#define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */
+#define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */
+
+/* Register: TEMP_A2 */
+/* Description: Slope of 3rd piece wise linear function */
+
+/* Bits 11..0 : Slope of 3rd piece wise linear function */
+#define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */
+#define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */
+
+/* Register: TEMP_A3 */
+/* Description: Slope of 4th piece wise linear function */
+
+/* Bits 11..0 : Slope of 4th piece wise linear function */
+#define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */
+#define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */
+
+/* Register: TEMP_A4 */
+/* Description: Slope of 5th piece wise linear function */
+
+/* Bits 11..0 : Slope of 5th piece wise linear function */
+#define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */
+#define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */
+
+/* Register: TEMP_A5 */
+/* Description: Slope of 6th piece wise linear function */
+
+/* Bits 11..0 : Slope of 6th piece wise linear function */
+#define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */
+#define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */
+
+/* Register: TEMP_B0 */
+/* Description: y-intercept of 1st piece wise linear function */
+
+/* Bits 13..0 : y-intercept of 1st piece wise linear function */
+#define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */
+#define TEMP_B0_B0_Msk (0x3FFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */
+
+/* Register: TEMP_B1 */
+/* Description: y-intercept of 2nd piece wise linear function */
+
+/* Bits 13..0 : y-intercept of 2nd piece wise linear function */
+#define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */
+#define TEMP_B1_B1_Msk (0x3FFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */
+
+/* Register: TEMP_B2 */
+/* Description: y-intercept of 3rd piece wise linear function */
+
+/* Bits 13..0 : y-intercept of 3rd piece wise linear function */
+#define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */
+#define TEMP_B2_B2_Msk (0x3FFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */
+
+/* Register: TEMP_B3 */
+/* Description: y-intercept of 4th piece wise linear function */
+
+/* Bits 13..0 : y-intercept of 4th piece wise linear function */
+#define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */
+#define TEMP_B3_B3_Msk (0x3FFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */
+
+/* Register: TEMP_B4 */
+/* Description: y-intercept of 5th piece wise linear function */
+
+/* Bits 13..0 : y-intercept of 5th piece wise linear function */
+#define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */
+#define TEMP_B4_B4_Msk (0x3FFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */
+
+/* Register: TEMP_B5 */
+/* Description: y-intercept of 6th piece wise linear function */
+
+/* Bits 13..0 : y-intercept of 6th piece wise linear function */
+#define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */
+#define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */
+
+/* Register: TEMP_T0 */
+/* Description: End point of 1st piece wise linear function */
+
+/* Bits 7..0 : End point of 1st piece wise linear function */
+#define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */
+#define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */
+
+/* Register: TEMP_T1 */
+/* Description: End point of 2nd piece wise linear function */
+
+/* Bits 7..0 : End point of 2nd piece wise linear function */
+#define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */
+#define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */
+
+/* Register: TEMP_T2 */
+/* Description: End point of 3rd piece wise linear function */
+
+/* Bits 7..0 : End point of 3rd piece wise linear function */
+#define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */
+#define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */
+
+/* Register: TEMP_T3 */
+/* Description: End point of 4th piece wise linear function */
+
+/* Bits 7..0 : End point of 4th piece wise linear function */
+#define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */
+#define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */
+
+/* Register: TEMP_T4 */
+/* Description: End point of 5th piece wise linear function */
+
+/* Bits 7..0 : End point of 5th piece wise linear function */
+#define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */
+#define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */
+
+
+/* Peripheral: TIMER */
+/* Description: Timer/Counter 0 */
+
+/* Register: TIMER_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 13 : Shortcut between COMPARE[5] event and STOP task */
+#define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */
+#define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */
+#define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 12 : Shortcut between COMPARE[4] event and STOP task */
+#define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */
+#define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */
+#define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 11 : Shortcut between COMPARE[3] event and STOP task */
+#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
+#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
+#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 10 : Shortcut between COMPARE[2] event and STOP task */
+#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
+#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
+#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 9 : Shortcut between COMPARE[1] event and STOP task */
+#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
+#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
+#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 8 : Shortcut between COMPARE[0] event and STOP task */
+#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
+#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
+#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 5 : Shortcut between COMPARE[5] event and CLEAR task */
+#define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */
+#define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */
+#define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 4 : Shortcut between COMPARE[4] event and CLEAR task */
+#define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */
+#define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */
+#define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between COMPARE[3] event and CLEAR task */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between COMPARE[2] event and CLEAR task */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between COMPARE[1] event and CLEAR task */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between COMPARE[0] event and CLEAR task */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: TIMER_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 21 : Write '1' to Enable interrupt for COMPARE[5] event */
+#define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
+#define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
+#define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to Enable interrupt for COMPARE[4] event */
+#define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
+#define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
+#define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */
+#define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */
+#define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */
+#define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
+
+/* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */
+#define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
+
+/* Register: TIMER_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 21 : Write '1' to Disable interrupt for COMPARE[5] event */
+#define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
+#define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
+#define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to Disable interrupt for COMPARE[4] event */
+#define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
+#define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
+#define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */
+#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */
+#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */
+#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
+
+/* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */
+#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
+
+/* Register: TIMER_STATUS */
+/* Description: Timer status */
+
+/* Bit 0 : Timer status */
+#define TIMER_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define TIMER_STATUS_STATUS_Msk (0x1UL << TIMER_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
+#define TIMER_STATUS_STATUS_Stopped (0UL) /*!< Timer is stopped */
+#define TIMER_STATUS_STATUS_Started (1UL) /*!< Timer is started */
+
+/* Register: TIMER_MODE */
+/* Description: Timer mode selection */
+
+/* Bits 1..0 : Timer mode */
+#define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */
+#define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator -  Select Counter mode */
+#define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */
+
+/* Register: TIMER_BITMODE */
+/* Description: Configure the number of bits used by the TIMER */
+
+/* Bits 1..0 : Timer bit width */
+#define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
+#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
+#define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */
+#define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */
+#define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */
+#define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */
+
+/* Register: TIMER_PRESCALER */
+/* Description: Timer prescaler register */
+
+/* Bits 3..0 : Prescaler value */
+#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
+#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
+
+/* Register: TIMER_CC */
+/* Description: Description collection[0]:  Capture/Compare register 0 */
+
+/* Bits 31..0 : Capture/Compare value */
+#define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */
+#define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */
+
+
+/* Peripheral: TWI */
+/* Description: I2C compatible Two-Wire Interface 0 */
+
+/* Register: TWI_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 1 : Shortcut between BB event and STOP task */
+#define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */
+#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */
+#define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between BB event and SUSPEND task */
+#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */
+#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */
+#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
+#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: TWI_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */
+#define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
+
+/* Bit 14 : Write '1' to Enable interrupt for BB event */
+#define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */
+#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */
+#define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENSET_BB_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to Enable interrupt for ERROR event */
+#define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for TXDSENT event */
+#define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
+#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
+#define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for RXDREADY event */
+#define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
+#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
+#define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
+#define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Register: TWI_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */
+#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
+
+/* Bit 14 : Write '1' to Disable interrupt for BB event */
+#define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */
+#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */
+#define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to Disable interrupt for ERROR event */
+#define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for TXDSENT event */
+#define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
+#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
+#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for RXDREADY event */
+#define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
+#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
+#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
+#define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Register: TWI_ERRORSRC */
+/* Description: Error source */
+
+/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
+#define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
+#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
+#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Read: error not present */
+#define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Read: error present */
+
+/* Bit 1 : NACK received after sending the address (write '1' to clear) */
+#define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
+#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
+#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Read: error not present */
+#define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Read: error present */
+
+/* Bit 0 : Overrun error */
+#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
+#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
+#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */
+#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */
+
+/* Register: TWI_ENABLE */
+/* Description: Enable TWI */
+
+/* Bits 3..0 : Enable or disable TWI */
+#define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define TWI_ENABLE_ENABLE_Msk (0xFUL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define TWI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWI */
+#define TWI_ENABLE_ENABLE_Enabled (5UL) /*!< Enable TWI */
+
+/* Register: TWI_PSEL_SCL */
+/* Description: Pin select for SCL */
+
+/* Bit 31 : Connection */
+#define TWI_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TWI_PSEL_SCL_CONNECT_Msk (0x1UL << TWI_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TWI_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
+#define TWI_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define TWI_PSEL_SCL_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define TWI_PSEL_SCL_PORT_Msk (0x3UL << TWI_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define TWI_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TWI_PSEL_SCL_PIN_Msk (0x1FUL << TWI_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: TWI_PSEL_SDA */
+/* Description: Pin select for SDA */
+
+/* Bit 31 : Connection */
+#define TWI_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TWI_PSEL_SDA_CONNECT_Msk (0x1UL << TWI_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TWI_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
+#define TWI_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define TWI_PSEL_SDA_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define TWI_PSEL_SDA_PORT_Msk (0x3UL << TWI_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define TWI_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TWI_PSEL_SDA_PIN_Msk (0x1FUL << TWI_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: TWI_RXD */
+/* Description: RXD register */
+
+/* Bits 7..0 : RXD register */
+#define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
+#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
+
+/* Register: TWI_TXD */
+/* Description: TXD register */
+
+/* Bits 7..0 : TXD register */
+#define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
+#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
+
+/* Register: TWI_FREQUENCY */
+/* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */
+
+/* Bits 31..0 : TWI master clock frequency */
+#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
+#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
+#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps (actual rate 410.256 kbps) */
+
+/* Register: TWI_ADDRESS */
+/* Description: Address used in the TWI transfer */
+
+/* Bits 6..0 : Address used in the TWI transfer */
+#define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
+#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+
+
+/* Peripheral: TWIM */
+/* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */
+
+/* Register: TWIM_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 12 : Shortcut between LASTRX event and STOP task */
+#define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */
+#define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */
+#define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 10 : Shortcut between LASTRX event and STARTTX task */
+#define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */
+#define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */
+#define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */
+#define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 9 : Shortcut between LASTTX event and STOP task */
+#define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */
+#define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */
+#define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 8 : Shortcut between LASTTX event and SUSPEND task */
+#define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */
+#define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */
+#define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
+#define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 7 : Shortcut between LASTTX event and STARTRX task */
+#define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */
+#define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */
+#define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
+#define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: TWIM_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 24 : Enable or disable interrupt for LASTTX event */
+#define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
+#define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
+#define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */
+
+/* Bit 23 : Enable or disable interrupt for LASTRX event */
+#define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
+#define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
+#define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */
+
+/* Bit 20 : Enable or disable interrupt for TXSTARTED event */
+#define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 19 : Enable or disable interrupt for RXSTARTED event */
+#define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 18 : Enable or disable interrupt for SUSPENDED event */
+#define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for ERROR event */
+#define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for STOPPED event */
+#define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Register: TWIM_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 24 : Write '1' to Enable interrupt for LASTTX event */
+#define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
+#define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
+#define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */
+
+/* Bit 23 : Write '1' to Enable interrupt for LASTRX event */
+#define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
+#define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
+#define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
+#define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
+#define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */
+#define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to Enable interrupt for ERROR event */
+#define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
+#define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Register: TWIM_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 24 : Write '1' to Disable interrupt for LASTTX event */
+#define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
+#define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
+#define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */
+
+/* Bit 23 : Write '1' to Disable interrupt for LASTRX event */
+#define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
+#define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
+#define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
+#define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
+#define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */
+#define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to Disable interrupt for ERROR event */
+#define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
+#define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Register: TWIM_ERRORSRC */
+/* Description: Error source */
+
+/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
+#define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
+#define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
+#define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
+#define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
+
+/* Bit 1 : NACK received after sending the address (write '1' to clear) */
+#define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
+#define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
+#define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */
+#define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */
+
+/* Bit 0 : Overrun error */
+#define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
+#define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
+#define TWIM_ERRORSRC_OVERRUN_NotReceived (0UL) /*!< Error did not occur */
+#define TWIM_ERRORSRC_OVERRUN_Received (1UL) /*!< Error occurred */
+
+/* Register: TWIM_ENABLE */
+/* Description: Enable TWIM */
+
+/* Bits 3..0 : Enable or disable TWIM */
+#define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */
+#define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */
+
+/* Register: TWIM_PSEL_SCL */
+/* Description: Pin select for SCL signal */
+
+/* Bit 31 : Connection */
+#define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
+#define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define TWIM_PSEL_SCL_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define TWIM_PSEL_SCL_PORT_Msk (0x3UL << TWIM_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: TWIM_PSEL_SDA */
+/* Description: Pin select for SDA signal */
+
+/* Bit 31 : Connection */
+#define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
+#define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define TWIM_PSEL_SDA_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define TWIM_PSEL_SDA_PORT_Msk (0x3UL << TWIM_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: TWIM_FREQUENCY */
+/* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */
+
+/* Bits 31..0 : TWI master clock frequency */
+#define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+#define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
+#define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
+#define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */
+
+/* Register: TWIM_RXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: TWIM_RXD_MAXCNT */
+/* Description: Maximum number of bytes in receive buffer */
+
+/* Bits 7..0 : Maximum number of bytes in receive buffer */
+#define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define TWIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: TWIM_RXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
+#define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define TWIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: TWIM_RXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 2..0 : List type */
+#define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define TWIM_RXD_LIST_LIST_Msk (0x7UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: TWIM_TXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: TWIM_TXD_MAXCNT */
+/* Description: Maximum number of bytes in transmit buffer */
+
+/* Bits 7..0 : Maximum number of bytes in transmit buffer */
+#define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define TWIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: TWIM_TXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
+#define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define TWIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: TWIM_TXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 2..0 : List type */
+#define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define TWIM_TXD_LIST_LIST_Msk (0x7UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: TWIM_ADDRESS */
+/* Description: Address used in the TWI transfer */
+
+/* Bits 6..0 : Address used in the TWI transfer */
+#define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
+#define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+
+
+/* Peripheral: TWIS */
+/* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */
+
+/* Register: TWIS_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 14 : Shortcut between READ event and SUSPEND task */
+#define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */
+#define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */
+#define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
+#define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 13 : Shortcut between WRITE event and SUSPEND task */
+#define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */
+#define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */
+#define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
+#define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: TWIS_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 26 : Enable or disable interrupt for READ event */
+#define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */
+#define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */
+#define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */
+
+/* Bit 25 : Enable or disable interrupt for WRITE event */
+#define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */
+#define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */
+#define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */
+
+/* Bit 20 : Enable or disable interrupt for TXSTARTED event */
+#define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 19 : Enable or disable interrupt for RXSTARTED event */
+#define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for ERROR event */
+#define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for STOPPED event */
+#define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Register: TWIS_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 26 : Write '1' to Enable interrupt for READ event */
+#define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */
+#define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */
+#define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */
+
+/* Bit 25 : Write '1' to Enable interrupt for WRITE event */
+#define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */
+#define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */
+#define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
+#define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
+#define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to Enable interrupt for ERROR event */
+#define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
+#define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Register: TWIS_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 26 : Write '1' to Disable interrupt for READ event */
+#define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */
+#define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */
+#define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */
+
+/* Bit 25 : Write '1' to Disable interrupt for WRITE event */
+#define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */
+#define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */
+#define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
+#define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
+#define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to Disable interrupt for ERROR event */
+#define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
+#define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Register: TWIS_ERRORSRC */
+/* Description: Error source */
+
+/* Bit 3 : TX buffer over-read detected, and prevented */
+#define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */
+#define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
+#define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */
+#define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */
+
+/* Bit 2 : NACK sent after receiving a data byte */
+#define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
+#define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
+#define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
+#define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
+
+/* Bit 0 : RX buffer overflow detected, and prevented */
+#define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */
+#define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
+#define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */
+#define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */
+
+/* Register: TWIS_MATCH */
+/* Description: Status register indicating which address had a match */
+
+/* Bit 0 : Which of the addresses in {ADDRESS} matched the incoming address */
+#define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */
+#define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */
+
+/* Register: TWIS_ENABLE */
+/* Description: Enable TWIS */
+
+/* Bits 3..0 : Enable or disable TWIS */
+#define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */
+#define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */
+
+/* Register: TWIS_PSEL_SCL */
+/* Description: Pin select for SCL signal */
+
+/* Bit 31 : Connection */
+#define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
+#define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define TWIS_PSEL_SCL_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define TWIS_PSEL_SCL_PORT_Msk (0x3UL << TWIS_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: TWIS_PSEL_SDA */
+/* Description: Pin select for SDA signal */
+
+/* Bit 31 : Connection */
+#define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
+#define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define TWIS_PSEL_SDA_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define TWIS_PSEL_SDA_PORT_Msk (0x3UL << TWIS_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: TWIS_RXD_PTR */
+/* Description: RXD Data pointer */
+
+/* Bits 31..0 : RXD Data pointer */
+#define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: TWIS_RXD_MAXCNT */
+/* Description: Maximum number of bytes in RXD buffer */
+
+/* Bits 7..0 : Maximum number of bytes in RXD buffer */
+#define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define TWIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: TWIS_RXD_AMOUNT */
+/* Description: Number of bytes transferred in the last RXD transaction */
+
+/* Bits 7..0 : Number of bytes transferred in the last RXD transaction */
+#define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define TWIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: TWIS_TXD_PTR */
+/* Description: TXD Data pointer */
+
+/* Bits 31..0 : TXD Data pointer */
+#define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: TWIS_TXD_MAXCNT */
+/* Description: Maximum number of bytes in TXD buffer */
+
+/* Bits 7..0 : Maximum number of bytes in TXD buffer */
+#define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define TWIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: TWIS_TXD_AMOUNT */
+/* Description: Number of bytes transferred in the last TXD transaction */
+
+/* Bits 7..0 : Number of bytes transferred in the last TXD transaction */
+#define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define TWIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: TWIS_ADDRESS */
+/* Description: Description collection[0]:  TWI slave address 0 */
+
+/* Bits 6..0 : TWI slave address */
+#define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
+#define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+
+/* Register: TWIS_CONFIG */
+/* Description: Configuration register for the address match mechanism */
+
+/* Bit 1 : Enable or disable address matching on ADDRESS[1] */
+#define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */
+#define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */
+#define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */
+#define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */
+
+/* Bit 0 : Enable or disable address matching on ADDRESS[0] */
+#define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */
+#define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */
+#define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */
+#define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */
+
+/* Register: TWIS_ORC */
+/* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */
+
+/* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */
+#define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
+#define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
+
+
+/* Peripheral: UART */
+/* Description: Universal Asynchronous Receiver/Transmitter */
+
+/* Register: UART_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 4 : Shortcut between NCTS event and STOPRX task */
+#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */
+#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */
+#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */
+#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between CTS event and STARTRX task */
+#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */
+#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */
+#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */
+#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: UART_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 17 : Write '1' to Enable interrupt for RXTO event */
+#define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to Enable interrupt for ERROR event */
+#define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */
+#define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */
+#define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for NCTS event */
+#define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for CTS event */
+#define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENSET_CTS_Set (1UL) /*!< Enable */
+
+/* Register: UART_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 17 : Write '1' to Disable interrupt for RXTO event */
+#define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to Disable interrupt for ERROR event */
+#define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */
+#define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */
+#define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for NCTS event */
+#define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for CTS event */
+#define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable */
+
+/* Register: UART_ERRORSRC */
+/* Description: Error source */
+
+/* Bit 3 : Break condition */
+#define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
+#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
+#define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
+#define UART_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
+
+/* Bit 2 : Framing error occurred */
+#define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
+#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
+#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
+#define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
+
+/* Bit 1 : Parity error */
+#define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
+#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
+#define UART_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
+
+/* Bit 0 : Overrun error */
+#define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
+#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
+#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
+#define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
+
+/* Register: UART_ENABLE */
+/* Description: Enable UART */
+
+/* Bits 3..0 : Enable or disable UART */
+#define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define UART_ENABLE_ENABLE_Msk (0xFUL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define UART_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UART */
+#define UART_ENABLE_ENABLE_Enabled (4UL) /*!< Enable UART */
+
+/* Register: UART_PSEL_RTS */
+/* Description: Pin select for RTS */
+
+/* Bit 31 : Connection */
+#define UART_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UART_PSEL_RTS_CONNECT_Msk (0x1UL << UART_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UART_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */
+#define UART_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define UART_PSEL_RTS_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define UART_PSEL_RTS_PORT_Msk (0x3UL << UART_PSEL_RTS_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define UART_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UART_PSEL_RTS_PIN_Msk (0x1FUL << UART_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UART_PSEL_TXD */
+/* Description: Pin select for TXD */
+
+/* Bit 31 : Connection */
+#define UART_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UART_PSEL_TXD_CONNECT_Msk (0x1UL << UART_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UART_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */
+#define UART_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define UART_PSEL_TXD_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define UART_PSEL_TXD_PORT_Msk (0x3UL << UART_PSEL_TXD_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define UART_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UART_PSEL_TXD_PIN_Msk (0x1FUL << UART_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UART_PSEL_CTS */
+/* Description: Pin select for CTS */
+
+/* Bit 31 : Connection */
+#define UART_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UART_PSEL_CTS_CONNECT_Msk (0x1UL << UART_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UART_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */
+#define UART_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define UART_PSEL_CTS_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define UART_PSEL_CTS_PORT_Msk (0x3UL << UART_PSEL_CTS_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define UART_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UART_PSEL_CTS_PIN_Msk (0x1FUL << UART_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UART_PSEL_RXD */
+/* Description: Pin select for RXD */
+
+/* Bit 31 : Connection */
+#define UART_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UART_PSEL_RXD_CONNECT_Msk (0x1UL << UART_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UART_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */
+#define UART_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define UART_PSEL_RXD_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define UART_PSEL_RXD_PORT_Msk (0x3UL << UART_PSEL_RXD_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define UART_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UART_PSEL_RXD_PIN_Msk (0x1FUL << UART_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UART_RXD */
+/* Description: RXD register */
+
+/* Bits 7..0 : RX data received in previous transfers, double buffered */
+#define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
+#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
+
+/* Register: UART_TXD */
+/* Description: TXD register */
+
+/* Bits 7..0 : TX data to be transferred */
+#define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
+#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
+
+/* Register: UART_BAUDRATE */
+/* Description: Baud rate. Accuracy depends on the HFCLK source selected. */
+
+/* Bits 31..0 : Baud rate */
+#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
+#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
+#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
+#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
+#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
+#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
+#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud (actual rate: 14414) */
+#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
+#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud (actual rate: 28829) */
+#define UART_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */
+#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud (actual rate: 38462) */
+#define UART_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */
+#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud (actual rate: 57762) */
+#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
+#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud (actual rate: 115942) */
+#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud (actual rate: 231884) */
+#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
+#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud (actual rate: 470588) */
+#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud (actual rate: 941176) */
+#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
+
+/* Register: UART_CONFIG */
+/* Description: Configuration of parity and hardware flow control */
+
+/* Bits 3..1 : Parity */
+#define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
+#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define UART_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
+#define UART_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */
+
+/* Bit 0 : Hardware flow control */
+#define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
+#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
+#define UART_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
+#define UART_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
+
+
+/* Peripheral: UARTE */
+/* Description: UART with EasyDMA 0 */
+
+/* Register: UARTE_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 6 : Shortcut between ENDRX event and STOPRX task */
+#define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */
+#define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */
+#define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */
+#define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 5 : Shortcut between ENDRX event and STARTRX task */
+#define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */
+#define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */
+#define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
+#define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: UARTE_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 22 : Enable or disable interrupt for TXSTOPPED event */
+#define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
+#define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
+#define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */
+
+/* Bit 20 : Enable or disable interrupt for TXSTARTED event */
+#define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 19 : Enable or disable interrupt for RXSTARTED event */
+#define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 17 : Enable or disable interrupt for RXTO event */
+#define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for ERROR event */
+#define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */
+
+/* Bit 8 : Enable or disable interrupt for ENDTX event */
+#define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable interrupt for TXDRDY event */
+#define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for ENDRX event */
+#define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for RXDRDY event */
+#define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for NCTS event */
+#define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for CTS event */
+#define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */
+
+/* Register: UARTE_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 22 : Write '1' to Enable interrupt for TXSTOPPED event */
+#define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
+#define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
+#define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
+#define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
+#define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to Enable interrupt for RXTO event */
+#define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to Enable interrupt for ERROR event */
+#define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 8 : Write '1' to Enable interrupt for ENDTX event */
+#define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */
+#define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
+#define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */
+#define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for NCTS event */
+#define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for CTS event */
+#define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */
+
+/* Register: UARTE_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 22 : Write '1' to Disable interrupt for TXSTOPPED event */
+#define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
+#define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
+#define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
+#define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
+#define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to Disable interrupt for RXTO event */
+#define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to Disable interrupt for ERROR event */
+#define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 8 : Write '1' to Disable interrupt for ENDTX event */
+#define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */
+#define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
+#define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */
+#define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for NCTS event */
+#define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for CTS event */
+#define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */
+
+/* Register: UARTE_ERRORSRC */
+/* Description: Error source Note : this register is read / write one to clear. */
+
+/* Bit 3 : Break condition */
+#define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
+#define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
+#define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
+#define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
+
+/* Bit 2 : Framing error occurred */
+#define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
+#define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
+#define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
+#define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
+
+/* Bit 1 : Parity error */
+#define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
+#define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
+#define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
+
+/* Bit 0 : Overrun error */
+#define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
+#define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
+#define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
+#define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
+
+/* Register: UARTE_ENABLE */
+/* Description: Enable UART */
+
+/* Bits 3..0 : Enable or disable UARTE */
+#define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */
+#define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */
+
+/* Register: UARTE_PSEL_RTS */
+/* Description: Pin select for RTS signal */
+
+/* Bit 31 : Connection */
+#define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */
+#define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define UARTE_PSEL_RTS_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define UARTE_PSEL_RTS_PORT_Msk (0x3UL << UARTE_PSEL_RTS_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UARTE_PSEL_TXD */
+/* Description: Pin select for TXD signal */
+
+/* Bit 31 : Connection */
+#define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */
+#define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define UARTE_PSEL_TXD_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define UARTE_PSEL_TXD_PORT_Msk (0x3UL << UARTE_PSEL_TXD_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UARTE_PSEL_CTS */
+/* Description: Pin select for CTS signal */
+
+/* Bit 31 : Connection */
+#define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */
+#define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define UARTE_PSEL_CTS_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define UARTE_PSEL_CTS_PORT_Msk (0x3UL << UARTE_PSEL_CTS_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UARTE_PSEL_RXD */
+/* Description: Pin select for RXD signal */
+
+/* Bit 31 : Connection */
+#define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */
+#define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define UARTE_PSEL_RXD_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define UARTE_PSEL_RXD_PORT_Msk (0x3UL << UARTE_PSEL_RXD_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UARTE_BAUDRATE */
+/* Description: Baud rate. Accuracy depends on the HFCLK source selected. */
+
+/* Bits 31..0 : Baud rate */
+#define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
+#define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
+#define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */
+#define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
+#define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
+
+/* Register: UARTE_RXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: UARTE_RXD_MAXCNT */
+/* Description: Maximum number of bytes in receive buffer */
+
+/* Bits 9..0 : Maximum number of bytes in receive buffer */
+#define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define UARTE_RXD_MAXCNT_MAXCNT_Msk (0x3FFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: UARTE_RXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 9..0 : Number of bytes transferred in the last transaction */
+#define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define UARTE_RXD_AMOUNT_AMOUNT_Msk (0x3FFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: UARTE_TXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: UARTE_TXD_MAXCNT */
+/* Description: Maximum number of bytes in transmit buffer */
+
+/* Bits 9..0 : Maximum number of bytes in transmit buffer */
+#define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define UARTE_TXD_MAXCNT_MAXCNT_Msk (0x3FFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: UARTE_TXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 9..0 : Number of bytes transferred in the last transaction */
+#define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define UARTE_TXD_AMOUNT_AMOUNT_Msk (0x3FFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: UARTE_CONFIG */
+/* Description: Configuration of parity and hardware flow control */
+
+/* Bit 4 : Stop bits */
+#define UARTE_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */
+#define UARTE_CONFIG_STOP_Msk (0x1UL << UARTE_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */
+#define UARTE_CONFIG_STOP_One (0UL) /*!< One stop bit */
+#define UARTE_CONFIG_STOP_Two (1UL) /*!< Two stop bits */
+
+/* Bits 3..1 : Parity */
+#define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
+#define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
+#define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include even parity bit */
+
+/* Bit 0 : Hardware flow control */
+#define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
+#define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
+#define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
+#define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
+
+
+/* Peripheral: UICR */
+/* Description: User Information Configuration Registers */
+
+/* Register: UICR_NRFFW */
+/* Description: Description collection[0]:  Reserved for Nordic firmware design */
+
+/* Bits 31..0 : Reserved for Nordic firmware design */
+#define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */
+#define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */
+
+/* Register: UICR_NRFHW */
+/* Description: Description collection[0]:  Reserved for Nordic hardware design */
+
+/* Bits 31..0 : Reserved for Nordic hardware design */
+#define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */
+#define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */
+
+/* Register: UICR_CUSTOMER */
+/* Description: Description collection[0]:  Reserved for customer */
+
+/* Bits 31..0 : Reserved for customer */
+#define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */
+#define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */
+
+/* Register: UICR_PSELRESET */
+/* Description: Description collection[0]:  Mapping of the nRESET function */
+
+/* Bit 31 : Connection */
+#define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UICR_PSELRESET_CONNECT_Msk (0x1UL << UICR_PSELRESET_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UICR_PSELRESET_CONNECT_Connected (0UL) /*!< Connect */
+#define UICR_PSELRESET_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number onto which nRESET is exposed */
+#define UICR_PSELRESET_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define UICR_PSELRESET_PORT_Msk (0x3UL << UICR_PSELRESET_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number of PORT onto which nRESET is exposed */
+#define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UICR_PSELRESET_PIN_Msk (0x1FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UICR_APPROTECT */
+/* Description: Access port protection */
+
+/* Bits 7..0 : Enable or disable Access Port protection. */
+#define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */
+#define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */
+#define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */
+#define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Disable */
+
+/* Register: UICR_NFCPINS */
+/* Description: Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */
+
+/* Bit 0 : Setting of pins dedicated to NFC functionality */
+#define UICR_NFCPINS_PROTECT_Pos (0UL) /*!< Position of PROTECT field. */
+#define UICR_NFCPINS_PROTECT_Msk (0x1UL << UICR_NFCPINS_PROTECT_Pos) /*!< Bit mask of PROTECT field. */
+#define UICR_NFCPINS_PROTECT_Disabled (0UL) /*!< Operation as GPIO pins. Same protection as normal GPIO pins */
+#define UICR_NFCPINS_PROTECT_NFC (1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation */
+
+/* Register: UICR_EXTSUPPLY */
+/* Description: Enable external circuitry to be supplied from VDD pin. Applicable in 'High voltage mode' only. */
+
+/* Bit 0 : Enable external circuitry to be supplied from VDD pin (output of REG0 stage). */
+#define UICR_EXTSUPPLY_EXTSUPPLY_Pos (0UL) /*!< Position of EXTSUPPLY field. */
+#define UICR_EXTSUPPLY_EXTSUPPLY_Msk (0x1UL << UICR_EXTSUPPLY_EXTSUPPLY_Pos) /*!< Bit mask of EXTSUPPLY field. */
+#define UICR_EXTSUPPLY_EXTSUPPLY_Disabled (0UL) /*!< No current can be drawn from the VDD pin. */
+#define UICR_EXTSUPPLY_EXTSUPPLY_Enabled (1UL) /*!< It is allowed to supply external circuitry from the VDD pin. */
+
+/* Register: UICR_REGOUT0 */
+/* Description: GPIO reference voltage / external output supply voltage in 'High voltage mode'. */
+
+/* Bits 2..0 : Output voltage from of REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VEXDIF. */
+#define UICR_REGOUT0_VOUT_Pos (0UL) /*!< Position of VOUT field. */
+#define UICR_REGOUT0_VOUT_Msk (0x7UL << UICR_REGOUT0_VOUT_Pos) /*!< Bit mask of VOUT field. */
+#define UICR_REGOUT0_VOUT_1V8 (0UL) /*!< 1.8 V */
+#define UICR_REGOUT0_VOUT_2V1 (1UL) /*!< 2.1 V */
+#define UICR_REGOUT0_VOUT_2V4 (2UL) /*!< 2.4 V */
+#define UICR_REGOUT0_VOUT_2V7 (3UL) /*!< 2.7 V */
+#define UICR_REGOUT0_VOUT_3V0 (4UL) /*!< 3.0 V */
+#define UICR_REGOUT0_VOUT_3V3 (5UL) /*!< 3.3 V */
+#define UICR_REGOUT0_VOUT_DEFAULT (7UL) /*!< Default voltage: 1.8 V */
+
+
+/* Peripheral: USBD */
+/* Description: Universal Serial Bus device */
+
+/* Register: USBD_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 4 : Shortcut between ENDEPOUT[0] event and EP0RCVOUT task */
+#define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Pos (4UL) /*!< Position of ENDEPOUT0_EP0RCVOUT field. */
+#define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Msk (0x1UL << USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Pos) /*!< Bit mask of ENDEPOUT0_EP0RCVOUT field. */
+#define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Disabled (0UL) /*!< Disable shortcut */
+#define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between ENDEPOUT[0] event and EP0STATUS task */
+#define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Pos (3UL) /*!< Position of ENDEPOUT0_EP0STATUS field. */
+#define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Msk (0x1UL << USBD_SHORTS_ENDEPOUT0_EP0STATUS_Pos) /*!< Bit mask of ENDEPOUT0_EP0STATUS field. */
+#define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Disabled (0UL) /*!< Disable shortcut */
+#define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between EP0DATADONE event and EP0STATUS task */
+#define USBD_SHORTS_EP0DATADONE_EP0STATUS_Pos (2UL) /*!< Position of EP0DATADONE_EP0STATUS field. */
+#define USBD_SHORTS_EP0DATADONE_EP0STATUS_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_EP0STATUS_Pos) /*!< Bit mask of EP0DATADONE_EP0STATUS field. */
+#define USBD_SHORTS_EP0DATADONE_EP0STATUS_Disabled (0UL) /*!< Disable shortcut */
+#define USBD_SHORTS_EP0DATADONE_EP0STATUS_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between EP0DATADONE event and STARTEPOUT[0] task */
+#define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Pos (1UL) /*!< Position of EP0DATADONE_STARTEPOUT0 field. */
+#define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Pos) /*!< Bit mask of EP0DATADONE_STARTEPOUT0 field. */
+#define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Disabled (0UL) /*!< Disable shortcut */
+#define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between EP0DATADONE event and STARTEPIN[0] task */
+#define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Pos (0UL) /*!< Position of EP0DATADONE_STARTEPIN0 field. */
+#define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_STARTEPIN0_Pos) /*!< Bit mask of EP0DATADONE_STARTEPIN0 field. */
+#define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Disabled (0UL) /*!< Disable shortcut */
+#define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: USBD_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 25 : Enable or disable interrupt for ACCESSFAULT event */
+#define USBD_INTEN_ACCESSFAULT_Pos (25UL) /*!< Position of ACCESSFAULT field. */
+#define USBD_INTEN_ACCESSFAULT_Msk (0x1UL << USBD_INTEN_ACCESSFAULT_Pos) /*!< Bit mask of ACCESSFAULT field. */
+#define USBD_INTEN_ACCESSFAULT_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ACCESSFAULT_Enabled (1UL) /*!< Enable */
+
+/* Bit 24 : Enable or disable interrupt for EPDATA event */
+#define USBD_INTEN_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */
+#define USBD_INTEN_EPDATA_Msk (0x1UL << USBD_INTEN_EPDATA_Pos) /*!< Bit mask of EPDATA field. */
+#define USBD_INTEN_EPDATA_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_EPDATA_Enabled (1UL) /*!< Enable */
+
+/* Bit 23 : Enable or disable interrupt for EP0SETUP event */
+#define USBD_INTEN_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */
+#define USBD_INTEN_EP0SETUP_Msk (0x1UL << USBD_INTEN_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */
+#define USBD_INTEN_EP0SETUP_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_EP0SETUP_Enabled (1UL) /*!< Enable */
+
+/* Bit 22 : Enable or disable interrupt for USBEVENT event */
+#define USBD_INTEN_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */
+#define USBD_INTEN_USBEVENT_Msk (0x1UL << USBD_INTEN_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */
+#define USBD_INTEN_USBEVENT_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_USBEVENT_Enabled (1UL) /*!< Enable */
+
+/* Bit 21 : Enable or disable interrupt for SOF event */
+#define USBD_INTEN_SOF_Pos (21UL) /*!< Position of SOF field. */
+#define USBD_INTEN_SOF_Msk (0x1UL << USBD_INTEN_SOF_Pos) /*!< Bit mask of SOF field. */
+#define USBD_INTEN_SOF_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_SOF_Enabled (1UL) /*!< Enable */
+
+/* Bit 20 : Enable or disable interrupt for ENDISOOUT event */
+#define USBD_INTEN_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */
+#define USBD_INTEN_ENDISOOUT_Msk (0x1UL << USBD_INTEN_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */
+#define USBD_INTEN_ENDISOOUT_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDISOOUT_Enabled (1UL) /*!< Enable */
+
+/* Bit 19 : Enable or disable interrupt for ENDEPOUT[7] event */
+#define USBD_INTEN_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */
+#define USBD_INTEN_ENDEPOUT7_Msk (0x1UL << USBD_INTEN_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */
+#define USBD_INTEN_ENDEPOUT7_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPOUT7_Enabled (1UL) /*!< Enable */
+
+/* Bit 18 : Enable or disable interrupt for ENDEPOUT[6] event */
+#define USBD_INTEN_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */
+#define USBD_INTEN_ENDEPOUT6_Msk (0x1UL << USBD_INTEN_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */
+#define USBD_INTEN_ENDEPOUT6_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPOUT6_Enabled (1UL) /*!< Enable */
+
+/* Bit 17 : Enable or disable interrupt for ENDEPOUT[5] event */
+#define USBD_INTEN_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */
+#define USBD_INTEN_ENDEPOUT5_Msk (0x1UL << USBD_INTEN_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */
+#define USBD_INTEN_ENDEPOUT5_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPOUT5_Enabled (1UL) /*!< Enable */
+
+/* Bit 16 : Enable or disable interrupt for ENDEPOUT[4] event */
+#define USBD_INTEN_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */
+#define USBD_INTEN_ENDEPOUT4_Msk (0x1UL << USBD_INTEN_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */
+#define USBD_INTEN_ENDEPOUT4_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPOUT4_Enabled (1UL) /*!< Enable */
+
+/* Bit 15 : Enable or disable interrupt for ENDEPOUT[3] event */
+#define USBD_INTEN_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */
+#define USBD_INTEN_ENDEPOUT3_Msk (0x1UL << USBD_INTEN_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */
+#define USBD_INTEN_ENDEPOUT3_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPOUT3_Enabled (1UL) /*!< Enable */
+
+/* Bit 14 : Enable or disable interrupt for ENDEPOUT[2] event */
+#define USBD_INTEN_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */
+#define USBD_INTEN_ENDEPOUT2_Msk (0x1UL << USBD_INTEN_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */
+#define USBD_INTEN_ENDEPOUT2_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPOUT2_Enabled (1UL) /*!< Enable */
+
+/* Bit 13 : Enable or disable interrupt for ENDEPOUT[1] event */
+#define USBD_INTEN_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */
+#define USBD_INTEN_ENDEPOUT1_Msk (0x1UL << USBD_INTEN_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */
+#define USBD_INTEN_ENDEPOUT1_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPOUT1_Enabled (1UL) /*!< Enable */
+
+/* Bit 12 : Enable or disable interrupt for ENDEPOUT[0] event */
+#define USBD_INTEN_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */
+#define USBD_INTEN_ENDEPOUT0_Msk (0x1UL << USBD_INTEN_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */
+#define USBD_INTEN_ENDEPOUT0_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPOUT0_Enabled (1UL) /*!< Enable */
+
+/* Bit 11 : Enable or disable interrupt for ENDISOIN event */
+#define USBD_INTEN_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */
+#define USBD_INTEN_ENDISOIN_Msk (0x1UL << USBD_INTEN_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */
+#define USBD_INTEN_ENDISOIN_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDISOIN_Enabled (1UL) /*!< Enable */
+
+/* Bit 10 : Enable or disable interrupt for EP0DATADONE event */
+#define USBD_INTEN_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */
+#define USBD_INTEN_EP0DATADONE_Msk (0x1UL << USBD_INTEN_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */
+#define USBD_INTEN_EP0DATADONE_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_EP0DATADONE_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for ENDEPIN[7] event */
+#define USBD_INTEN_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */
+#define USBD_INTEN_ENDEPIN7_Msk (0x1UL << USBD_INTEN_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */
+#define USBD_INTEN_ENDEPIN7_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPIN7_Enabled (1UL) /*!< Enable */
+
+/* Bit 8 : Enable or disable interrupt for ENDEPIN[6] event */
+#define USBD_INTEN_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */
+#define USBD_INTEN_ENDEPIN6_Msk (0x1UL << USBD_INTEN_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */
+#define USBD_INTEN_ENDEPIN6_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPIN6_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable interrupt for ENDEPIN[5] event */
+#define USBD_INTEN_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */
+#define USBD_INTEN_ENDEPIN5_Msk (0x1UL << USBD_INTEN_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */
+#define USBD_INTEN_ENDEPIN5_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPIN5_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable interrupt for ENDEPIN[4] event */
+#define USBD_INTEN_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */
+#define USBD_INTEN_ENDEPIN4_Msk (0x1UL << USBD_INTEN_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */
+#define USBD_INTEN_ENDEPIN4_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPIN4_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable interrupt for ENDEPIN[3] event */
+#define USBD_INTEN_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */
+#define USBD_INTEN_ENDEPIN3_Msk (0x1UL << USBD_INTEN_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */
+#define USBD_INTEN_ENDEPIN3_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPIN3_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for ENDEPIN[2] event */
+#define USBD_INTEN_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */
+#define USBD_INTEN_ENDEPIN2_Msk (0x1UL << USBD_INTEN_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */
+#define USBD_INTEN_ENDEPIN2_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPIN2_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable interrupt for ENDEPIN[1] event */
+#define USBD_INTEN_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */
+#define USBD_INTEN_ENDEPIN1_Msk (0x1UL << USBD_INTEN_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */
+#define USBD_INTEN_ENDEPIN1_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPIN1_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for ENDEPIN[0] event */
+#define USBD_INTEN_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */
+#define USBD_INTEN_ENDEPIN0_Msk (0x1UL << USBD_INTEN_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */
+#define USBD_INTEN_ENDEPIN0_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPIN0_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for STARTED event */
+#define USBD_INTEN_STARTED_Pos (1UL) /*!< Position of STARTED field. */
+#define USBD_INTEN_STARTED_Msk (0x1UL << USBD_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define USBD_INTEN_STARTED_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_STARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for USBRESET event */
+#define USBD_INTEN_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */
+#define USBD_INTEN_USBRESET_Msk (0x1UL << USBD_INTEN_USBRESET_Pos) /*!< Bit mask of USBRESET field. */
+#define USBD_INTEN_USBRESET_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_USBRESET_Enabled (1UL) /*!< Enable */
+
+/* Register: USBD_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 25 : Write '1' to Enable interrupt for ACCESSFAULT event */
+#define USBD_INTENSET_ACCESSFAULT_Pos (25UL) /*!< Position of ACCESSFAULT field. */
+#define USBD_INTENSET_ACCESSFAULT_Msk (0x1UL << USBD_INTENSET_ACCESSFAULT_Pos) /*!< Bit mask of ACCESSFAULT field. */
+#define USBD_INTENSET_ACCESSFAULT_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ACCESSFAULT_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ACCESSFAULT_Set (1UL) /*!< Enable */
+
+/* Bit 24 : Write '1' to Enable interrupt for EPDATA event */
+#define USBD_INTENSET_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */
+#define USBD_INTENSET_EPDATA_Msk (0x1UL << USBD_INTENSET_EPDATA_Pos) /*!< Bit mask of EPDATA field. */
+#define USBD_INTENSET_EPDATA_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_EPDATA_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_EPDATA_Set (1UL) /*!< Enable */
+
+/* Bit 23 : Write '1' to Enable interrupt for EP0SETUP event */
+#define USBD_INTENSET_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */
+#define USBD_INTENSET_EP0SETUP_Msk (0x1UL << USBD_INTENSET_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */
+#define USBD_INTENSET_EP0SETUP_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_EP0SETUP_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_EP0SETUP_Set (1UL) /*!< Enable */
+
+/* Bit 22 : Write '1' to Enable interrupt for USBEVENT event */
+#define USBD_INTENSET_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */
+#define USBD_INTENSET_USBEVENT_Msk (0x1UL << USBD_INTENSET_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */
+#define USBD_INTENSET_USBEVENT_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_USBEVENT_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_USBEVENT_Set (1UL) /*!< Enable */
+
+/* Bit 21 : Write '1' to Enable interrupt for SOF event */
+#define USBD_INTENSET_SOF_Pos (21UL) /*!< Position of SOF field. */
+#define USBD_INTENSET_SOF_Msk (0x1UL << USBD_INTENSET_SOF_Pos) /*!< Bit mask of SOF field. */
+#define USBD_INTENSET_SOF_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_SOF_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_SOF_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to Enable interrupt for ENDISOOUT event */
+#define USBD_INTENSET_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */
+#define USBD_INTENSET_ENDISOOUT_Msk (0x1UL << USBD_INTENSET_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */
+#define USBD_INTENSET_ENDISOOUT_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDISOOUT_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDISOOUT_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to Enable interrupt for ENDEPOUT[7] event */
+#define USBD_INTENSET_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */
+#define USBD_INTENSET_ENDEPOUT7_Msk (0x1UL << USBD_INTENSET_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */
+#define USBD_INTENSET_ENDEPOUT7_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPOUT7_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPOUT7_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to Enable interrupt for ENDEPOUT[6] event */
+#define USBD_INTENSET_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */
+#define USBD_INTENSET_ENDEPOUT6_Msk (0x1UL << USBD_INTENSET_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */
+#define USBD_INTENSET_ENDEPOUT6_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPOUT6_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPOUT6_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to Enable interrupt for ENDEPOUT[5] event */
+#define USBD_INTENSET_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */
+#define USBD_INTENSET_ENDEPOUT5_Msk (0x1UL << USBD_INTENSET_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */
+#define USBD_INTENSET_ENDEPOUT5_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPOUT5_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPOUT5_Set (1UL) /*!< Enable */
+
+/* Bit 16 : Write '1' to Enable interrupt for ENDEPOUT[4] event */
+#define USBD_INTENSET_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */
+#define USBD_INTENSET_ENDEPOUT4_Msk (0x1UL << USBD_INTENSET_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */
+#define USBD_INTENSET_ENDEPOUT4_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPOUT4_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPOUT4_Set (1UL) /*!< Enable */
+
+/* Bit 15 : Write '1' to Enable interrupt for ENDEPOUT[3] event */
+#define USBD_INTENSET_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */
+#define USBD_INTENSET_ENDEPOUT3_Msk (0x1UL << USBD_INTENSET_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */
+#define USBD_INTENSET_ENDEPOUT3_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPOUT3_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPOUT3_Set (1UL) /*!< Enable */
+
+/* Bit 14 : Write '1' to Enable interrupt for ENDEPOUT[2] event */
+#define USBD_INTENSET_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */
+#define USBD_INTENSET_ENDEPOUT2_Msk (0x1UL << USBD_INTENSET_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */
+#define USBD_INTENSET_ENDEPOUT2_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPOUT2_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPOUT2_Set (1UL) /*!< Enable */
+
+/* Bit 13 : Write '1' to Enable interrupt for ENDEPOUT[1] event */
+#define USBD_INTENSET_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */
+#define USBD_INTENSET_ENDEPOUT1_Msk (0x1UL << USBD_INTENSET_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */
+#define USBD_INTENSET_ENDEPOUT1_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPOUT1_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPOUT1_Set (1UL) /*!< Enable */
+
+/* Bit 12 : Write '1' to Enable interrupt for ENDEPOUT[0] event */
+#define USBD_INTENSET_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */
+#define USBD_INTENSET_ENDEPOUT0_Msk (0x1UL << USBD_INTENSET_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */
+#define USBD_INTENSET_ENDEPOUT0_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPOUT0_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPOUT0_Set (1UL) /*!< Enable */
+
+/* Bit 11 : Write '1' to Enable interrupt for ENDISOIN event */
+#define USBD_INTENSET_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */
+#define USBD_INTENSET_ENDISOIN_Msk (0x1UL << USBD_INTENSET_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */
+#define USBD_INTENSET_ENDISOIN_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDISOIN_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDISOIN_Set (1UL) /*!< Enable */
+
+/* Bit 10 : Write '1' to Enable interrupt for EP0DATADONE event */
+#define USBD_INTENSET_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */
+#define USBD_INTENSET_EP0DATADONE_Msk (0x1UL << USBD_INTENSET_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */
+#define USBD_INTENSET_EP0DATADONE_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_EP0DATADONE_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_EP0DATADONE_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to Enable interrupt for ENDEPIN[7] event */
+#define USBD_INTENSET_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */
+#define USBD_INTENSET_ENDEPIN7_Msk (0x1UL << USBD_INTENSET_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */
+#define USBD_INTENSET_ENDEPIN7_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPIN7_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPIN7_Set (1UL) /*!< Enable */
+
+/* Bit 8 : Write '1' to Enable interrupt for ENDEPIN[6] event */
+#define USBD_INTENSET_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */
+#define USBD_INTENSET_ENDEPIN6_Msk (0x1UL << USBD_INTENSET_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */
+#define USBD_INTENSET_ENDEPIN6_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPIN6_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPIN6_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for ENDEPIN[5] event */
+#define USBD_INTENSET_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */
+#define USBD_INTENSET_ENDEPIN5_Msk (0x1UL << USBD_INTENSET_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */
+#define USBD_INTENSET_ENDEPIN5_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPIN5_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPIN5_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for ENDEPIN[4] event */
+#define USBD_INTENSET_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */
+#define USBD_INTENSET_ENDEPIN4_Msk (0x1UL << USBD_INTENSET_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */
+#define USBD_INTENSET_ENDEPIN4_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPIN4_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPIN4_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable interrupt for ENDEPIN[3] event */
+#define USBD_INTENSET_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */
+#define USBD_INTENSET_ENDEPIN3_Msk (0x1UL << USBD_INTENSET_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */
+#define USBD_INTENSET_ENDEPIN3_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPIN3_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPIN3_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for ENDEPIN[2] event */
+#define USBD_INTENSET_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */
+#define USBD_INTENSET_ENDEPIN2_Msk (0x1UL << USBD_INTENSET_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */
+#define USBD_INTENSET_ENDEPIN2_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPIN2_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPIN2_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for ENDEPIN[1] event */
+#define USBD_INTENSET_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */
+#define USBD_INTENSET_ENDEPIN1_Msk (0x1UL << USBD_INTENSET_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */
+#define USBD_INTENSET_ENDEPIN1_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPIN1_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPIN1_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for ENDEPIN[0] event */
+#define USBD_INTENSET_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */
+#define USBD_INTENSET_ENDEPIN0_Msk (0x1UL << USBD_INTENSET_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */
+#define USBD_INTENSET_ENDEPIN0_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPIN0_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPIN0_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for STARTED event */
+#define USBD_INTENSET_STARTED_Pos (1UL) /*!< Position of STARTED field. */
+#define USBD_INTENSET_STARTED_Msk (0x1UL << USBD_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define USBD_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_STARTED_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for USBRESET event */
+#define USBD_INTENSET_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */
+#define USBD_INTENSET_USBRESET_Msk (0x1UL << USBD_INTENSET_USBRESET_Pos) /*!< Bit mask of USBRESET field. */
+#define USBD_INTENSET_USBRESET_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_USBRESET_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_USBRESET_Set (1UL) /*!< Enable */
+
+/* Register: USBD_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 25 : Write '1' to Disable interrupt for ACCESSFAULT event */
+#define USBD_INTENCLR_ACCESSFAULT_Pos (25UL) /*!< Position of ACCESSFAULT field. */
+#define USBD_INTENCLR_ACCESSFAULT_Msk (0x1UL << USBD_INTENCLR_ACCESSFAULT_Pos) /*!< Bit mask of ACCESSFAULT field. */
+#define USBD_INTENCLR_ACCESSFAULT_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ACCESSFAULT_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ACCESSFAULT_Clear (1UL) /*!< Disable */
+
+/* Bit 24 : Write '1' to Disable interrupt for EPDATA event */
+#define USBD_INTENCLR_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */
+#define USBD_INTENCLR_EPDATA_Msk (0x1UL << USBD_INTENCLR_EPDATA_Pos) /*!< Bit mask of EPDATA field. */
+#define USBD_INTENCLR_EPDATA_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_EPDATA_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_EPDATA_Clear (1UL) /*!< Disable */
+
+/* Bit 23 : Write '1' to Disable interrupt for EP0SETUP event */
+#define USBD_INTENCLR_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */
+#define USBD_INTENCLR_EP0SETUP_Msk (0x1UL << USBD_INTENCLR_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */
+#define USBD_INTENCLR_EP0SETUP_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_EP0SETUP_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_EP0SETUP_Clear (1UL) /*!< Disable */
+
+/* Bit 22 : Write '1' to Disable interrupt for USBEVENT event */
+#define USBD_INTENCLR_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */
+#define USBD_INTENCLR_USBEVENT_Msk (0x1UL << USBD_INTENCLR_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */
+#define USBD_INTENCLR_USBEVENT_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_USBEVENT_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_USBEVENT_Clear (1UL) /*!< Disable */
+
+/* Bit 21 : Write '1' to Disable interrupt for SOF event */
+#define USBD_INTENCLR_SOF_Pos (21UL) /*!< Position of SOF field. */
+#define USBD_INTENCLR_SOF_Msk (0x1UL << USBD_INTENCLR_SOF_Pos) /*!< Bit mask of SOF field. */
+#define USBD_INTENCLR_SOF_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_SOF_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_SOF_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to Disable interrupt for ENDISOOUT event */
+#define USBD_INTENCLR_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */
+#define USBD_INTENCLR_ENDISOOUT_Msk (0x1UL << USBD_INTENCLR_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */
+#define USBD_INTENCLR_ENDISOOUT_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDISOOUT_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDISOOUT_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to Disable interrupt for ENDEPOUT[7] event */
+#define USBD_INTENCLR_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */
+#define USBD_INTENCLR_ENDEPOUT7_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */
+#define USBD_INTENCLR_ENDEPOUT7_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPOUT7_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPOUT7_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to Disable interrupt for ENDEPOUT[6] event */
+#define USBD_INTENCLR_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */
+#define USBD_INTENCLR_ENDEPOUT6_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */
+#define USBD_INTENCLR_ENDEPOUT6_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPOUT6_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPOUT6_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to Disable interrupt for ENDEPOUT[5] event */
+#define USBD_INTENCLR_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */
+#define USBD_INTENCLR_ENDEPOUT5_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */
+#define USBD_INTENCLR_ENDEPOUT5_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPOUT5_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPOUT5_Clear (1UL) /*!< Disable */
+
+/* Bit 16 : Write '1' to Disable interrupt for ENDEPOUT[4] event */
+#define USBD_INTENCLR_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */
+#define USBD_INTENCLR_ENDEPOUT4_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */
+#define USBD_INTENCLR_ENDEPOUT4_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPOUT4_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPOUT4_Clear (1UL) /*!< Disable */
+
+/* Bit 15 : Write '1' to Disable interrupt for ENDEPOUT[3] event */
+#define USBD_INTENCLR_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */
+#define USBD_INTENCLR_ENDEPOUT3_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */
+#define USBD_INTENCLR_ENDEPOUT3_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPOUT3_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPOUT3_Clear (1UL) /*!< Disable */
+
+/* Bit 14 : Write '1' to Disable interrupt for ENDEPOUT[2] event */
+#define USBD_INTENCLR_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */
+#define USBD_INTENCLR_ENDEPOUT2_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */
+#define USBD_INTENCLR_ENDEPOUT2_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPOUT2_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPOUT2_Clear (1UL) /*!< Disable */
+
+/* Bit 13 : Write '1' to Disable interrupt for ENDEPOUT[1] event */
+#define USBD_INTENCLR_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */
+#define USBD_INTENCLR_ENDEPOUT1_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */
+#define USBD_INTENCLR_ENDEPOUT1_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPOUT1_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPOUT1_Clear (1UL) /*!< Disable */
+
+/* Bit 12 : Write '1' to Disable interrupt for ENDEPOUT[0] event */
+#define USBD_INTENCLR_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */
+#define USBD_INTENCLR_ENDEPOUT0_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */
+#define USBD_INTENCLR_ENDEPOUT0_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPOUT0_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPOUT0_Clear (1UL) /*!< Disable */
+
+/* Bit 11 : Write '1' to Disable interrupt for ENDISOIN event */
+#define USBD_INTENCLR_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */
+#define USBD_INTENCLR_ENDISOIN_Msk (0x1UL << USBD_INTENCLR_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */
+#define USBD_INTENCLR_ENDISOIN_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDISOIN_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDISOIN_Clear (1UL) /*!< Disable */
+
+/* Bit 10 : Write '1' to Disable interrupt for EP0DATADONE event */
+#define USBD_INTENCLR_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */
+#define USBD_INTENCLR_EP0DATADONE_Msk (0x1UL << USBD_INTENCLR_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */
+#define USBD_INTENCLR_EP0DATADONE_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_EP0DATADONE_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_EP0DATADONE_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to Disable interrupt for ENDEPIN[7] event */
+#define USBD_INTENCLR_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */
+#define USBD_INTENCLR_ENDEPIN7_Msk (0x1UL << USBD_INTENCLR_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */
+#define USBD_INTENCLR_ENDEPIN7_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPIN7_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPIN7_Clear (1UL) /*!< Disable */
+
+/* Bit 8 : Write '1' to Disable interrupt for ENDEPIN[6] event */
+#define USBD_INTENCLR_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */
+#define USBD_INTENCLR_ENDEPIN6_Msk (0x1UL << USBD_INTENCLR_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */
+#define USBD_INTENCLR_ENDEPIN6_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPIN6_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPIN6_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for ENDEPIN[5] event */
+#define USBD_INTENCLR_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */
+#define USBD_INTENCLR_ENDEPIN5_Msk (0x1UL << USBD_INTENCLR_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */
+#define USBD_INTENCLR_ENDEPIN5_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPIN5_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPIN5_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for ENDEPIN[4] event */
+#define USBD_INTENCLR_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */
+#define USBD_INTENCLR_ENDEPIN4_Msk (0x1UL << USBD_INTENCLR_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */
+#define USBD_INTENCLR_ENDEPIN4_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPIN4_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPIN4_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable interrupt for ENDEPIN[3] event */
+#define USBD_INTENCLR_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */
+#define USBD_INTENCLR_ENDEPIN3_Msk (0x1UL << USBD_INTENCLR_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */
+#define USBD_INTENCLR_ENDEPIN3_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPIN3_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPIN3_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for ENDEPIN[2] event */
+#define USBD_INTENCLR_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */
+#define USBD_INTENCLR_ENDEPIN2_Msk (0x1UL << USBD_INTENCLR_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */
+#define USBD_INTENCLR_ENDEPIN2_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPIN2_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPIN2_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for ENDEPIN[1] event */
+#define USBD_INTENCLR_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */
+#define USBD_INTENCLR_ENDEPIN1_Msk (0x1UL << USBD_INTENCLR_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */
+#define USBD_INTENCLR_ENDEPIN1_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPIN1_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPIN1_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for ENDEPIN[0] event */
+#define USBD_INTENCLR_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */
+#define USBD_INTENCLR_ENDEPIN0_Msk (0x1UL << USBD_INTENCLR_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */
+#define USBD_INTENCLR_ENDEPIN0_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPIN0_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPIN0_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for STARTED event */
+#define USBD_INTENCLR_STARTED_Pos (1UL) /*!< Position of STARTED field. */
+#define USBD_INTENCLR_STARTED_Msk (0x1UL << USBD_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define USBD_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for USBRESET event */
+#define USBD_INTENCLR_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */
+#define USBD_INTENCLR_USBRESET_Msk (0x1UL << USBD_INTENCLR_USBRESET_Pos) /*!< Bit mask of USBRESET field. */
+#define USBD_INTENCLR_USBRESET_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_USBRESET_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_USBRESET_Clear (1UL) /*!< Disable */
+
+/* Register: USBD_EVENTCAUSE */
+/* Description: Details on event that caused the USBEVENT event */
+
+/* Bit 11 : Wrapper has re-initialized SFRs to the proper values. MAC is ready for normal operation. Write '1' to clear. */
+#define USBD_EVENTCAUSE_READY_Pos (11UL) /*!< Position of READY field. */
+#define USBD_EVENTCAUSE_READY_Msk (0x1UL << USBD_EVENTCAUSE_READY_Pos) /*!< Bit mask of READY field. */
+#define USBD_EVENTCAUSE_READY_NotDetected (0UL) /*!< USBEVENT was not issued due to USBD peripheral ready */
+#define USBD_EVENTCAUSE_READY_Ready (1UL) /*!< USBD peripheral is ready */
+
+/* Bit 9 : Signals that a RESUME condition (K state or activity restart) has been detected on the USB lines. Write '1' to clear. */
+#define USBD_EVENTCAUSE_RESUME_Pos (9UL) /*!< Position of RESUME field. */
+#define USBD_EVENTCAUSE_RESUME_Msk (0x1UL << USBD_EVENTCAUSE_RESUME_Pos) /*!< Bit mask of RESUME field. */
+#define USBD_EVENTCAUSE_RESUME_NotDetected (0UL) /*!< Resume not detected */
+#define USBD_EVENTCAUSE_RESUME_Detected (1UL) /*!< Resume detected */
+
+/* Bit 8 : Signals that the USB lines have been seen idle long enough for the device to enter suspend. Write '1' to clear. */
+#define USBD_EVENTCAUSE_SUSPEND_Pos (8UL) /*!< Position of SUSPEND field. */
+#define USBD_EVENTCAUSE_SUSPEND_Msk (0x1UL << USBD_EVENTCAUSE_SUSPEND_Pos) /*!< Bit mask of SUSPEND field. */
+#define USBD_EVENTCAUSE_SUSPEND_NotDetected (0UL) /*!< Suspend not detected */
+#define USBD_EVENTCAUSE_SUSPEND_Detected (1UL) /*!< Suspend detected */
+
+/* Bit 0 : CRC error was detected on isochronous OUT endpoint 8. Write '1' to clear. */
+#define USBD_EVENTCAUSE_ISOOUTCRC_Pos (0UL) /*!< Position of ISOOUTCRC field. */
+#define USBD_EVENTCAUSE_ISOOUTCRC_Msk (0x1UL << USBD_EVENTCAUSE_ISOOUTCRC_Pos) /*!< Bit mask of ISOOUTCRC field. */
+#define USBD_EVENTCAUSE_ISOOUTCRC_NotDetected (0UL) /*!< No error detected */
+#define USBD_EVENTCAUSE_ISOOUTCRC_Detected (1UL) /*!< Error detected */
+
+/* Register: USBD_BUSSTATE */
+/* Description: Provides the logic state of the D+ and D- lines */
+
+/* Bit 1 : State of the D+ line */
+#define USBD_BUSSTATE_DP_Pos (1UL) /*!< Position of DP field. */
+#define USBD_BUSSTATE_DP_Msk (0x1UL << USBD_BUSSTATE_DP_Pos) /*!< Bit mask of DP field. */
+#define USBD_BUSSTATE_DP_Low (0UL) /*!< Low */
+#define USBD_BUSSTATE_DP_High (1UL) /*!< High */
+
+/* Bit 0 : State of the D- line */
+#define USBD_BUSSTATE_DM_Pos (0UL) /*!< Position of DM field. */
+#define USBD_BUSSTATE_DM_Msk (0x1UL << USBD_BUSSTATE_DM_Pos) /*!< Bit mask of DM field. */
+#define USBD_BUSSTATE_DM_Low (0UL) /*!< Low */
+#define USBD_BUSSTATE_DM_High (1UL) /*!< High */
+
+/* Register: USBD_HALTED_EPIN */
+/* Description: Description collection[0]:  IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */
+
+/* Bits 15..0 : IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */
+#define USBD_HALTED_EPIN_GETSTATUS_Pos (0UL) /*!< Position of GETSTATUS field. */
+#define USBD_HALTED_EPIN_GETSTATUS_Msk (0xFFFFUL << USBD_HALTED_EPIN_GETSTATUS_Pos) /*!< Bit mask of GETSTATUS field. */
+#define USBD_HALTED_EPIN_GETSTATUS_NotHalted (0UL) /*!< Endpoint is not halted */
+#define USBD_HALTED_EPIN_GETSTATUS_Halted (1UL) /*!< Endpoint is halted */
+
+/* Register: USBD_HALTED_EPOUT */
+/* Description: Description collection[0]:  OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */
+
+/* Bits 15..0 : OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */
+#define USBD_HALTED_EPOUT_GETSTATUS_Pos (0UL) /*!< Position of GETSTATUS field. */
+#define USBD_HALTED_EPOUT_GETSTATUS_Msk (0xFFFFUL << USBD_HALTED_EPOUT_GETSTATUS_Pos) /*!< Bit mask of GETSTATUS field. */
+#define USBD_HALTED_EPOUT_GETSTATUS_NotHalted (0UL) /*!< Endpoint is not halted */
+#define USBD_HALTED_EPOUT_GETSTATUS_Halted (1UL) /*!< Endpoint is halted */
+
+/* Register: USBD_EPSTATUS */
+/* Description: Provides information on which endpoint's EasyDMA registers have been captured */
+
+/* Bit 24 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */
+#define USBD_EPSTATUS_EPOUT8_Pos (24UL) /*!< Position of EPOUT8 field. */
+#define USBD_EPSTATUS_EPOUT8_Msk (0x1UL << USBD_EPSTATUS_EPOUT8_Pos) /*!< Bit mask of EPOUT8 field. */
+#define USBD_EPSTATUS_EPOUT8_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPOUT8_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 23 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */
+#define USBD_EPSTATUS_EPOUT7_Pos (23UL) /*!< Position of EPOUT7 field. */
+#define USBD_EPSTATUS_EPOUT7_Msk (0x1UL << USBD_EPSTATUS_EPOUT7_Pos) /*!< Bit mask of EPOUT7 field. */
+#define USBD_EPSTATUS_EPOUT7_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPOUT7_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 22 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */
+#define USBD_EPSTATUS_EPOUT6_Pos (22UL) /*!< Position of EPOUT6 field. */
+#define USBD_EPSTATUS_EPOUT6_Msk (0x1UL << USBD_EPSTATUS_EPOUT6_Pos) /*!< Bit mask of EPOUT6 field. */
+#define USBD_EPSTATUS_EPOUT6_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPOUT6_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 21 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */
+#define USBD_EPSTATUS_EPOUT5_Pos (21UL) /*!< Position of EPOUT5 field. */
+#define USBD_EPSTATUS_EPOUT5_Msk (0x1UL << USBD_EPSTATUS_EPOUT5_Pos) /*!< Bit mask of EPOUT5 field. */
+#define USBD_EPSTATUS_EPOUT5_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPOUT5_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 20 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */
+#define USBD_EPSTATUS_EPOUT4_Pos (20UL) /*!< Position of EPOUT4 field. */
+#define USBD_EPSTATUS_EPOUT4_Msk (0x1UL << USBD_EPSTATUS_EPOUT4_Pos) /*!< Bit mask of EPOUT4 field. */
+#define USBD_EPSTATUS_EPOUT4_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPOUT4_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 19 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */
+#define USBD_EPSTATUS_EPOUT3_Pos (19UL) /*!< Position of EPOUT3 field. */
+#define USBD_EPSTATUS_EPOUT3_Msk (0x1UL << USBD_EPSTATUS_EPOUT3_Pos) /*!< Bit mask of EPOUT3 field. */
+#define USBD_EPSTATUS_EPOUT3_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPOUT3_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 18 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */
+#define USBD_EPSTATUS_EPOUT2_Pos (18UL) /*!< Position of EPOUT2 field. */
+#define USBD_EPSTATUS_EPOUT2_Msk (0x1UL << USBD_EPSTATUS_EPOUT2_Pos) /*!< Bit mask of EPOUT2 field. */
+#define USBD_EPSTATUS_EPOUT2_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPOUT2_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 17 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */
+#define USBD_EPSTATUS_EPOUT1_Pos (17UL) /*!< Position of EPOUT1 field. */
+#define USBD_EPSTATUS_EPOUT1_Msk (0x1UL << USBD_EPSTATUS_EPOUT1_Pos) /*!< Bit mask of EPOUT1 field. */
+#define USBD_EPSTATUS_EPOUT1_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPOUT1_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 16 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */
+#define USBD_EPSTATUS_EPOUT0_Pos (16UL) /*!< Position of EPOUT0 field. */
+#define USBD_EPSTATUS_EPOUT0_Msk (0x1UL << USBD_EPSTATUS_EPOUT0_Pos) /*!< Bit mask of EPOUT0 field. */
+#define USBD_EPSTATUS_EPOUT0_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPOUT0_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 8 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */
+#define USBD_EPSTATUS_EPIN8_Pos (8UL) /*!< Position of EPIN8 field. */
+#define USBD_EPSTATUS_EPIN8_Msk (0x1UL << USBD_EPSTATUS_EPIN8_Pos) /*!< Bit mask of EPIN8 field. */
+#define USBD_EPSTATUS_EPIN8_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPIN8_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 7 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */
+#define USBD_EPSTATUS_EPIN7_Pos (7UL) /*!< Position of EPIN7 field. */
+#define USBD_EPSTATUS_EPIN7_Msk (0x1UL << USBD_EPSTATUS_EPIN7_Pos) /*!< Bit mask of EPIN7 field. */
+#define USBD_EPSTATUS_EPIN7_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPIN7_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 6 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */
+#define USBD_EPSTATUS_EPIN6_Pos (6UL) /*!< Position of EPIN6 field. */
+#define USBD_EPSTATUS_EPIN6_Msk (0x1UL << USBD_EPSTATUS_EPIN6_Pos) /*!< Bit mask of EPIN6 field. */
+#define USBD_EPSTATUS_EPIN6_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPIN6_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 5 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */
+#define USBD_EPSTATUS_EPIN5_Pos (5UL) /*!< Position of EPIN5 field. */
+#define USBD_EPSTATUS_EPIN5_Msk (0x1UL << USBD_EPSTATUS_EPIN5_Pos) /*!< Bit mask of EPIN5 field. */
+#define USBD_EPSTATUS_EPIN5_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPIN5_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 4 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */
+#define USBD_EPSTATUS_EPIN4_Pos (4UL) /*!< Position of EPIN4 field. */
+#define USBD_EPSTATUS_EPIN4_Msk (0x1UL << USBD_EPSTATUS_EPIN4_Pos) /*!< Bit mask of EPIN4 field. */
+#define USBD_EPSTATUS_EPIN4_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPIN4_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 3 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */
+#define USBD_EPSTATUS_EPIN3_Pos (3UL) /*!< Position of EPIN3 field. */
+#define USBD_EPSTATUS_EPIN3_Msk (0x1UL << USBD_EPSTATUS_EPIN3_Pos) /*!< Bit mask of EPIN3 field. */
+#define USBD_EPSTATUS_EPIN3_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPIN3_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 2 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */
+#define USBD_EPSTATUS_EPIN2_Pos (2UL) /*!< Position of EPIN2 field. */
+#define USBD_EPSTATUS_EPIN2_Msk (0x1UL << USBD_EPSTATUS_EPIN2_Pos) /*!< Bit mask of EPIN2 field. */
+#define USBD_EPSTATUS_EPIN2_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPIN2_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 1 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */
+#define USBD_EPSTATUS_EPIN1_Pos (1UL) /*!< Position of EPIN1 field. */
+#define USBD_EPSTATUS_EPIN1_Msk (0x1UL << USBD_EPSTATUS_EPIN1_Pos) /*!< Bit mask of EPIN1 field. */
+#define USBD_EPSTATUS_EPIN1_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPIN1_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 0 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */
+#define USBD_EPSTATUS_EPIN0_Pos (0UL) /*!< Position of EPIN0 field. */
+#define USBD_EPSTATUS_EPIN0_Msk (0x1UL << USBD_EPSTATUS_EPIN0_Pos) /*!< Bit mask of EPIN0 field. */
+#define USBD_EPSTATUS_EPIN0_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPIN0_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Register: USBD_EPDATASTATUS */
+/* Description: Provides information on which endpoint(s) an acknowledged data transfer has occurred (EPDATA event) */
+
+/* Bit 23 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
+#define USBD_EPDATASTATUS_EPOUT7_Pos (23UL) /*!< Position of EPOUT7 field. */
+#define USBD_EPDATASTATUS_EPOUT7_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT7_Pos) /*!< Bit mask of EPOUT7 field. */
+#define USBD_EPDATASTATUS_EPOUT7_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
+#define USBD_EPDATASTATUS_EPOUT7_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
+
+/* Bit 22 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
+#define USBD_EPDATASTATUS_EPOUT6_Pos (22UL) /*!< Position of EPOUT6 field. */
+#define USBD_EPDATASTATUS_EPOUT6_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT6_Pos) /*!< Bit mask of EPOUT6 field. */
+#define USBD_EPDATASTATUS_EPOUT6_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
+#define USBD_EPDATASTATUS_EPOUT6_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
+
+/* Bit 21 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
+#define USBD_EPDATASTATUS_EPOUT5_Pos (21UL) /*!< Position of EPOUT5 field. */
+#define USBD_EPDATASTATUS_EPOUT5_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT5_Pos) /*!< Bit mask of EPOUT5 field. */
+#define USBD_EPDATASTATUS_EPOUT5_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
+#define USBD_EPDATASTATUS_EPOUT5_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
+
+/* Bit 20 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
+#define USBD_EPDATASTATUS_EPOUT4_Pos (20UL) /*!< Position of EPOUT4 field. */
+#define USBD_EPDATASTATUS_EPOUT4_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT4_Pos) /*!< Bit mask of EPOUT4 field. */
+#define USBD_EPDATASTATUS_EPOUT4_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
+#define USBD_EPDATASTATUS_EPOUT4_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
+
+/* Bit 19 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
+#define USBD_EPDATASTATUS_EPOUT3_Pos (19UL) /*!< Position of EPOUT3 field. */
+#define USBD_EPDATASTATUS_EPOUT3_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT3_Pos) /*!< Bit mask of EPOUT3 field. */
+#define USBD_EPDATASTATUS_EPOUT3_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
+#define USBD_EPDATASTATUS_EPOUT3_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
+
+/* Bit 18 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
+#define USBD_EPDATASTATUS_EPOUT2_Pos (18UL) /*!< Position of EPOUT2 field. */
+#define USBD_EPDATASTATUS_EPOUT2_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT2_Pos) /*!< Bit mask of EPOUT2 field. */
+#define USBD_EPDATASTATUS_EPOUT2_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
+#define USBD_EPDATASTATUS_EPOUT2_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
+
+/* Bit 17 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
+#define USBD_EPDATASTATUS_EPOUT1_Pos (17UL) /*!< Position of EPOUT1 field. */
+#define USBD_EPDATASTATUS_EPOUT1_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT1_Pos) /*!< Bit mask of EPOUT1 field. */
+#define USBD_EPDATASTATUS_EPOUT1_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
+#define USBD_EPDATASTATUS_EPOUT1_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
+
+/* Bit 7 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
+#define USBD_EPDATASTATUS_EPIN7_Pos (7UL) /*!< Position of EPIN7 field. */
+#define USBD_EPDATASTATUS_EPIN7_Msk (0x1UL << USBD_EPDATASTATUS_EPIN7_Pos) /*!< Bit mask of EPIN7 field. */
+#define USBD_EPDATASTATUS_EPIN7_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
+#define USBD_EPDATASTATUS_EPIN7_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
+
+/* Bit 6 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
+#define USBD_EPDATASTATUS_EPIN6_Pos (6UL) /*!< Position of EPIN6 field. */
+#define USBD_EPDATASTATUS_EPIN6_Msk (0x1UL << USBD_EPDATASTATUS_EPIN6_Pos) /*!< Bit mask of EPIN6 field. */
+#define USBD_EPDATASTATUS_EPIN6_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
+#define USBD_EPDATASTATUS_EPIN6_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
+
+/* Bit 5 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
+#define USBD_EPDATASTATUS_EPIN5_Pos (5UL) /*!< Position of EPIN5 field. */
+#define USBD_EPDATASTATUS_EPIN5_Msk (0x1UL << USBD_EPDATASTATUS_EPIN5_Pos) /*!< Bit mask of EPIN5 field. */
+#define USBD_EPDATASTATUS_EPIN5_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
+#define USBD_EPDATASTATUS_EPIN5_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
+
+/* Bit 4 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
+#define USBD_EPDATASTATUS_EPIN4_Pos (4UL) /*!< Position of EPIN4 field. */
+#define USBD_EPDATASTATUS_EPIN4_Msk (0x1UL << USBD_EPDATASTATUS_EPIN4_Pos) /*!< Bit mask of EPIN4 field. */
+#define USBD_EPDATASTATUS_EPIN4_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
+#define USBD_EPDATASTATUS_EPIN4_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
+
+/* Bit 3 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
+#define USBD_EPDATASTATUS_EPIN3_Pos (3UL) /*!< Position of EPIN3 field. */
+#define USBD_EPDATASTATUS_EPIN3_Msk (0x1UL << USBD_EPDATASTATUS_EPIN3_Pos) /*!< Bit mask of EPIN3 field. */
+#define USBD_EPDATASTATUS_EPIN3_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
+#define USBD_EPDATASTATUS_EPIN3_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
+
+/* Bit 2 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
+#define USBD_EPDATASTATUS_EPIN2_Pos (2UL) /*!< Position of EPIN2 field. */
+#define USBD_EPDATASTATUS_EPIN2_Msk (0x1UL << USBD_EPDATASTATUS_EPIN2_Pos) /*!< Bit mask of EPIN2 field. */
+#define USBD_EPDATASTATUS_EPIN2_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
+#define USBD_EPDATASTATUS_EPIN2_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
+
+/* Bit 1 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
+#define USBD_EPDATASTATUS_EPIN1_Pos (1UL) /*!< Position of EPIN1 field. */
+#define USBD_EPDATASTATUS_EPIN1_Msk (0x1UL << USBD_EPDATASTATUS_EPIN1_Pos) /*!< Bit mask of EPIN1 field. */
+#define USBD_EPDATASTATUS_EPIN1_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
+#define USBD_EPDATASTATUS_EPIN1_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
+
+/* Register: USBD_USBADDR */
+/* Description: Device USB address */
+
+/* Bits 6..0 : Device USB address */
+#define USBD_USBADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */
+#define USBD_USBADDR_ADDR_Msk (0x7FUL << USBD_USBADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */
+
+/* Register: USBD_BMREQUESTTYPE */
+/* Description: SETUP data, byte 0, bmRequestType */
+
+/* Bit 7 : Data transfer direction */
+#define USBD_BMREQUESTTYPE_DIRECTION_Pos (7UL) /*!< Position of DIRECTION field. */
+#define USBD_BMREQUESTTYPE_DIRECTION_Msk (0x1UL << USBD_BMREQUESTTYPE_DIRECTION_Pos) /*!< Bit mask of DIRECTION field. */
+#define USBD_BMREQUESTTYPE_DIRECTION_HostToDevice (0UL) /*!< Host-to-device */
+#define USBD_BMREQUESTTYPE_DIRECTION_DeviceToHost (1UL) /*!< Device-to-host */
+
+/* Bits 6..5 : Data transfer type */
+#define USBD_BMREQUESTTYPE_TYPE_Pos (5UL) /*!< Position of TYPE field. */
+#define USBD_BMREQUESTTYPE_TYPE_Msk (0x3UL << USBD_BMREQUESTTYPE_TYPE_Pos) /*!< Bit mask of TYPE field. */
+#define USBD_BMREQUESTTYPE_TYPE_Standard (0UL) /*!< Standard */
+#define USBD_BMREQUESTTYPE_TYPE_Class (1UL) /*!< Class */
+#define USBD_BMREQUESTTYPE_TYPE_Vendor (2UL) /*!< Vendor */
+
+/* Bits 4..0 : Data transfer type */
+#define USBD_BMREQUESTTYPE_RECIPIENT_Pos (0UL) /*!< Position of RECIPIENT field. */
+#define USBD_BMREQUESTTYPE_RECIPIENT_Msk (0x1FUL << USBD_BMREQUESTTYPE_RECIPIENT_Pos) /*!< Bit mask of RECIPIENT field. */
+#define USBD_BMREQUESTTYPE_RECIPIENT_Device (0UL) /*!< Device */
+#define USBD_BMREQUESTTYPE_RECIPIENT_Interface (1UL) /*!< Interface */
+#define USBD_BMREQUESTTYPE_RECIPIENT_Endpoint (2UL) /*!< Endpoint */
+#define USBD_BMREQUESTTYPE_RECIPIENT_Other (3UL) /*!< Other */
+
+/* Register: USBD_BREQUEST */
+/* Description: SETUP data, byte 1, bRequest */
+
+/* Bits 7..0 : SETUP data, byte 1, bRequest. Values provides for standard requests only, user must implement Class and Vendor values. */
+#define USBD_BREQUEST_BREQUEST_Pos (0UL) /*!< Position of BREQUEST field. */
+#define USBD_BREQUEST_BREQUEST_Msk (0xFFUL << USBD_BREQUEST_BREQUEST_Pos) /*!< Bit mask of BREQUEST field. */
+#define USBD_BREQUEST_BREQUEST_STD_GET_STATUS (0UL) /*!< Standard request GET_STATUS */
+#define USBD_BREQUEST_BREQUEST_STD_CLEAR_FEATURE (1UL) /*!< Standard request CLEAR_FEATURE */
+#define USBD_BREQUEST_BREQUEST_STD_SET_FEATURE (3UL) /*!< Standard request SET_FEATURE */
+#define USBD_BREQUEST_BREQUEST_STD_SET_ADDRESS (5UL) /*!< Standard request SET_ADDRESS */
+#define USBD_BREQUEST_BREQUEST_STD_GET_DESCRIPTOR (6UL) /*!< Standard request GET_DESCRIPTOR */
+#define USBD_BREQUEST_BREQUEST_STD_SET_DESCRIPTOR (7UL) /*!< Standard request SET_DESCRIPTOR */
+#define USBD_BREQUEST_BREQUEST_STD_GET_CONFIGURATION (8UL) /*!< Standard request GET_CONFIGURATION */
+#define USBD_BREQUEST_BREQUEST_STD_SET_CONFIGURATION (9UL) /*!< Standard request SET_CONFIGURATION */
+#define USBD_BREQUEST_BREQUEST_STD_GET_INTERFACE (10UL) /*!< Standard request GET_INTERFACE */
+#define USBD_BREQUEST_BREQUEST_STD_SET_INTERFACE (11UL) /*!< Standard request SET_INTERFACE */
+#define USBD_BREQUEST_BREQUEST_STD_SYNCH_FRAME (12UL) /*!< Standard request SYNCH_FRAME */
+
+/* Register: USBD_WVALUEL */
+/* Description: SETUP data, byte 2, LSB of wValue */
+
+/* Bits 7..0 : SETUP data, byte 2, LSB of wValue */
+#define USBD_WVALUEL_WVALUEL_Pos (0UL) /*!< Position of WVALUEL field. */
+#define USBD_WVALUEL_WVALUEL_Msk (0xFFUL << USBD_WVALUEL_WVALUEL_Pos) /*!< Bit mask of WVALUEL field. */
+
+/* Register: USBD_WVALUEH */
+/* Description: SETUP data, byte 3, MSB of wValue */
+
+/* Bits 7..0 : SETUP data, byte 3, MSB of wValue */
+#define USBD_WVALUEH_WVALUEH_Pos (0UL) /*!< Position of WVALUEH field. */
+#define USBD_WVALUEH_WVALUEH_Msk (0xFFUL << USBD_WVALUEH_WVALUEH_Pos) /*!< Bit mask of WVALUEH field. */
+
+/* Register: USBD_WINDEXL */
+/* Description: SETUP data, byte 4, LSB of wIndex */
+
+/* Bits 7..0 : SETUP data, byte 4, LSB of wIndex */
+#define USBD_WINDEXL_WINDEXL_Pos (0UL) /*!< Position of WINDEXL field. */
+#define USBD_WINDEXL_WINDEXL_Msk (0xFFUL << USBD_WINDEXL_WINDEXL_Pos) /*!< Bit mask of WINDEXL field. */
+
+/* Register: USBD_WINDEXH */
+/* Description: SETUP data, byte 5, MSB of wIndex */
+
+/* Bits 7..0 : SETUP data, byte 5, MSB of wIndex */
+#define USBD_WINDEXH_WINDEXH_Pos (0UL) /*!< Position of WINDEXH field. */
+#define USBD_WINDEXH_WINDEXH_Msk (0xFFUL << USBD_WINDEXH_WINDEXH_Pos) /*!< Bit mask of WINDEXH field. */
+
+/* Register: USBD_WLENGTHL */
+/* Description: SETUP data, byte 6, LSB of wLength */
+
+/* Bits 7..0 : SETUP data, byte 6, LSB of wLength */
+#define USBD_WLENGTHL_WLENGTHL_Pos (0UL) /*!< Position of WLENGTHL field. */
+#define USBD_WLENGTHL_WLENGTHL_Msk (0xFFUL << USBD_WLENGTHL_WLENGTHL_Pos) /*!< Bit mask of WLENGTHL field. */
+
+/* Register: USBD_WLENGTHH */
+/* Description: SETUP data, byte 7, MSB of wLength */
+
+/* Bits 7..0 : SETUP data, byte 7, MSB of wLength */
+#define USBD_WLENGTHH_WLENGTHH_Pos (0UL) /*!< Position of WLENGTHH field. */
+#define USBD_WLENGTHH_WLENGTHH_Msk (0xFFUL << USBD_WLENGTHH_WLENGTHH_Pos) /*!< Bit mask of WLENGTHH field. */
+
+/* Register: USBD_SIZE_EPOUT */
+/* Description: Description collection[0]:  Amount of bytes received last in the data stage of this OUT endpoint */
+
+/* Bits 6..0 : Amount of bytes received last in the data stage of this OUT endpoint */
+#define USBD_SIZE_EPOUT_SIZE_Pos (0UL) /*!< Position of SIZE field. */
+#define USBD_SIZE_EPOUT_SIZE_Msk (0x7FUL << USBD_SIZE_EPOUT_SIZE_Pos) /*!< Bit mask of SIZE field. */
+
+/* Register: USBD_SIZE_ISOOUT */
+/* Description: Amount of bytes received last on this iso OUT data endpoint */
+
+/* Bit 16 : Zero-length data packet received */
+#define USBD_SIZE_ISOOUT_ZERO_Pos (16UL) /*!< Position of ZERO field. */
+#define USBD_SIZE_ISOOUT_ZERO_Msk (0x1UL << USBD_SIZE_ISOOUT_ZERO_Pos) /*!< Bit mask of ZERO field. */
+#define USBD_SIZE_ISOOUT_ZERO_Normal (0UL) /*!< No zero-length data received, use value in SIZE */
+#define USBD_SIZE_ISOOUT_ZERO_ZeroData (1UL) /*!< Zero-length data received, ignore value in SIZE */
+
+/* Bits 9..0 : Amount of bytes received last on this iso OUT data endpoint */
+#define USBD_SIZE_ISOOUT_SIZE_Pos (0UL) /*!< Position of SIZE field. */
+#define USBD_SIZE_ISOOUT_SIZE_Msk (0x3FFUL << USBD_SIZE_ISOOUT_SIZE_Pos) /*!< Bit mask of SIZE field. */
+
+/* Register: USBD_ENABLE */
+/* Description: Enable USB */
+
+/* Bit 0 : Enable USB */
+#define USBD_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define USBD_ENABLE_ENABLE_Msk (0x1UL << USBD_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define USBD_ENABLE_ENABLE_Disabled (0UL) /*!< USB peripheral is disabled */
+#define USBD_ENABLE_ENABLE_Enabled (1UL) /*!< USB peripheral is enabled */
+
+/* Register: USBD_USBPULLUP */
+/* Description: Control of the USB pull-up */
+
+/* Bit 0 : Control of the USB pull-up on the D+ line */
+#define USBD_USBPULLUP_CONNECT_Pos (0UL) /*!< Position of CONNECT field. */
+#define USBD_USBPULLUP_CONNECT_Msk (0x1UL << USBD_USBPULLUP_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define USBD_USBPULLUP_CONNECT_Disabled (0UL) /*!< Pull-up is disconnected */
+#define USBD_USBPULLUP_CONNECT_Enabled (1UL) /*!< Pull-up is connected to D+ */
+
+/* Register: USBD_DPDMVALUE */
+/* Description: State at which the DPDMDRIVE task will force D+ and D-. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing). */
+
+/* Bits 4..0 : State at which the DPDMDRIVE task will force D+ and D- */
+#define USBD_DPDMVALUE_STATE_Pos (0UL) /*!< Position of STATE field. */
+#define USBD_DPDMVALUE_STATE_Msk (0x1FUL << USBD_DPDMVALUE_STATE_Pos) /*!< Bit mask of STATE field. */
+#define USBD_DPDMVALUE_STATE_Resume (1UL) /*!< D+ forced low, D- forced high (K state) for a timing pre-set in hardware (50 us or 5 ms, depending on bus state) */
+#define USBD_DPDMVALUE_STATE_J (2UL) /*!< D+ forced high, D- forced low (J state) */
+#define USBD_DPDMVALUE_STATE_K (4UL) /*!< D+ forced low, D- forced high (K state) */
+
+/* Register: USBD_DTOGGLE */
+/* Description: Data toggle control and status. */
+
+/* Bits 9..8 : Data toggle value */
+#define USBD_DTOGGLE_VALUE_Pos (8UL) /*!< Position of VALUE field. */
+#define USBD_DTOGGLE_VALUE_Msk (0x3UL << USBD_DTOGGLE_VALUE_Pos) /*!< Bit mask of VALUE field. */
+#define USBD_DTOGGLE_VALUE_Nop (0UL) /*!< No action on data toggle when writing the register with this value */
+#define USBD_DTOGGLE_VALUE_Data0 (1UL) /*!< Data toggle is DATA0 on endpoint set by EP and IO */
+#define USBD_DTOGGLE_VALUE_Data1 (2UL) /*!< Data toggle is DATA1 on endpoint set by EP and IO */
+
+/* Bit 7 : Selects IN or OUT endpoint */
+#define USBD_DTOGGLE_IO_Pos (7UL) /*!< Position of IO field. */
+#define USBD_DTOGGLE_IO_Msk (0x1UL << USBD_DTOGGLE_IO_Pos) /*!< Bit mask of IO field. */
+#define USBD_DTOGGLE_IO_Out (0UL) /*!< Selects OUT endpoint */
+#define USBD_DTOGGLE_IO_In (1UL) /*!< Selects IN endpoint */
+
+/* Bits 2..0 : Select bulk endpoint number */
+#define USBD_DTOGGLE_EP_Pos (0UL) /*!< Position of EP field. */
+#define USBD_DTOGGLE_EP_Msk (0x7UL << USBD_DTOGGLE_EP_Pos) /*!< Bit mask of EP field. */
+
+/* Register: USBD_EPINEN */
+/* Description: Endpoint IN enable */
+
+/* Bit 8 : Enable iso IN endpoint */
+#define USBD_EPINEN_ISOIN_Pos (8UL) /*!< Position of ISOIN field. */
+#define USBD_EPINEN_ISOIN_Msk (0x1UL << USBD_EPINEN_ISOIN_Pos) /*!< Bit mask of ISOIN field. */
+#define USBD_EPINEN_ISOIN_Disable (0UL) /*!< Disable iso IN endpoint 8 */
+#define USBD_EPINEN_ISOIN_Enable (1UL) /*!< Enable iso IN endpoint 8 */
+
+/* Bit 7 : Enable IN endpoint 7 */
+#define USBD_EPINEN_IN7_Pos (7UL) /*!< Position of IN7 field. */
+#define USBD_EPINEN_IN7_Msk (0x1UL << USBD_EPINEN_IN7_Pos) /*!< Bit mask of IN7 field. */
+#define USBD_EPINEN_IN7_Disable (0UL) /*!< Disable endpoint IN 7 (no response to IN tokens) */
+#define USBD_EPINEN_IN7_Enable (1UL) /*!< Enable endpoint IN 7 (response to IN tokens) */
+
+/* Bit 6 : Enable IN endpoint 6 */
+#define USBD_EPINEN_IN6_Pos (6UL) /*!< Position of IN6 field. */
+#define USBD_EPINEN_IN6_Msk (0x1UL << USBD_EPINEN_IN6_Pos) /*!< Bit mask of IN6 field. */
+#define USBD_EPINEN_IN6_Disable (0UL) /*!< Disable endpoint IN 6 (no response to IN tokens) */
+#define USBD_EPINEN_IN6_Enable (1UL) /*!< Enable endpoint IN 6 (response to IN tokens) */
+
+/* Bit 5 : Enable IN endpoint 5 */
+#define USBD_EPINEN_IN5_Pos (5UL) /*!< Position of IN5 field. */
+#define USBD_EPINEN_IN5_Msk (0x1UL << USBD_EPINEN_IN5_Pos) /*!< Bit mask of IN5 field. */
+#define USBD_EPINEN_IN5_Disable (0UL) /*!< Disable endpoint IN 5 (no response to IN tokens) */
+#define USBD_EPINEN_IN5_Enable (1UL) /*!< Enable endpoint IN 5 (response to IN tokens) */
+
+/* Bit 4 : Enable IN endpoint 4 */
+#define USBD_EPINEN_IN4_Pos (4UL) /*!< Position of IN4 field. */
+#define USBD_EPINEN_IN4_Msk (0x1UL << USBD_EPINEN_IN4_Pos) /*!< Bit mask of IN4 field. */
+#define USBD_EPINEN_IN4_Disable (0UL) /*!< Disable endpoint IN 4 (no response to IN tokens) */
+#define USBD_EPINEN_IN4_Enable (1UL) /*!< Enable endpoint IN 4 (response to IN tokens) */
+
+/* Bit 3 : Enable IN endpoint 3 */
+#define USBD_EPINEN_IN3_Pos (3UL) /*!< Position of IN3 field. */
+#define USBD_EPINEN_IN3_Msk (0x1UL << USBD_EPINEN_IN3_Pos) /*!< Bit mask of IN3 field. */
+#define USBD_EPINEN_IN3_Disable (0UL) /*!< Disable endpoint IN 3 (no response to IN tokens) */
+#define USBD_EPINEN_IN3_Enable (1UL) /*!< Enable endpoint IN 3 (response to IN tokens) */
+
+/* Bit 2 : Enable IN endpoint 2 */
+#define USBD_EPINEN_IN2_Pos (2UL) /*!< Position of IN2 field. */
+#define USBD_EPINEN_IN2_Msk (0x1UL << USBD_EPINEN_IN2_Pos) /*!< Bit mask of IN2 field. */
+#define USBD_EPINEN_IN2_Disable (0UL) /*!< Disable endpoint IN 2 (no response to IN tokens) */
+#define USBD_EPINEN_IN2_Enable (1UL) /*!< Enable endpoint IN 2 (response to IN tokens) */
+
+/* Bit 1 : Enable IN endpoint 1 */
+#define USBD_EPINEN_IN1_Pos (1UL) /*!< Position of IN1 field. */
+#define USBD_EPINEN_IN1_Msk (0x1UL << USBD_EPINEN_IN1_Pos) /*!< Bit mask of IN1 field. */
+#define USBD_EPINEN_IN1_Disable (0UL) /*!< Disable endpoint IN 1 (no response to IN tokens) */
+#define USBD_EPINEN_IN1_Enable (1UL) /*!< Enable endpoint IN 1 (response to IN tokens) */
+
+/* Bit 0 : Enable IN endpoint 0 */
+#define USBD_EPINEN_IN0_Pos (0UL) /*!< Position of IN0 field. */
+#define USBD_EPINEN_IN0_Msk (0x1UL << USBD_EPINEN_IN0_Pos) /*!< Bit mask of IN0 field. */
+#define USBD_EPINEN_IN0_Disable (0UL) /*!< Disable endpoint IN 0 (no response to IN tokens) */
+#define USBD_EPINEN_IN0_Enable (1UL) /*!< Enable endpoint IN 0 (response to IN tokens) */
+
+/* Register: USBD_EPOUTEN */
+/* Description: Endpoint OUT enable */
+
+/* Bit 8 : Enable iso OUT endpoint 8 */
+#define USBD_EPOUTEN_ISOOUT_Pos (8UL) /*!< Position of ISOOUT field. */
+#define USBD_EPOUTEN_ISOOUT_Msk (0x1UL << USBD_EPOUTEN_ISOOUT_Pos) /*!< Bit mask of ISOOUT field. */
+#define USBD_EPOUTEN_ISOOUT_Disable (0UL) /*!< Disable iso OUT endpoint 8 */
+#define USBD_EPOUTEN_ISOOUT_Enable (1UL) /*!< Enable iso OUT endpoint 8 */
+
+/* Bit 7 : Enable OUT endpoint 7 */
+#define USBD_EPOUTEN_OUT7_Pos (7UL) /*!< Position of OUT7 field. */
+#define USBD_EPOUTEN_OUT7_Msk (0x1UL << USBD_EPOUTEN_OUT7_Pos) /*!< Bit mask of OUT7 field. */
+#define USBD_EPOUTEN_OUT7_Disable (0UL) /*!< Disable endpoint OUT 7 (no response to OUT tokens) */
+#define USBD_EPOUTEN_OUT7_Enable (1UL) /*!< Enable endpoint OUT 7 (response to OUT tokens) */
+
+/* Bit 6 : Enable OUT endpoint 6 */
+#define USBD_EPOUTEN_OUT6_Pos (6UL) /*!< Position of OUT6 field. */
+#define USBD_EPOUTEN_OUT6_Msk (0x1UL << USBD_EPOUTEN_OUT6_Pos) /*!< Bit mask of OUT6 field. */
+#define USBD_EPOUTEN_OUT6_Disable (0UL) /*!< Disable endpoint OUT 6 (no response to OUT tokens) */
+#define USBD_EPOUTEN_OUT6_Enable (1UL) /*!< Enable endpoint OUT 6 (response to OUT tokens) */
+
+/* Bit 5 : Enable OUT endpoint 5 */
+#define USBD_EPOUTEN_OUT5_Pos (5UL) /*!< Position of OUT5 field. */
+#define USBD_EPOUTEN_OUT5_Msk (0x1UL << USBD_EPOUTEN_OUT5_Pos) /*!< Bit mask of OUT5 field. */
+#define USBD_EPOUTEN_OUT5_Disable (0UL) /*!< Disable endpoint OUT 5 (no response to OUT tokens) */
+#define USBD_EPOUTEN_OUT5_Enable (1UL) /*!< Enable endpoint OUT 5 (response to OUT tokens) */
+
+/* Bit 4 : Enable OUT endpoint 4 */
+#define USBD_EPOUTEN_OUT4_Pos (4UL) /*!< Position of OUT4 field. */
+#define USBD_EPOUTEN_OUT4_Msk (0x1UL << USBD_EPOUTEN_OUT4_Pos) /*!< Bit mask of OUT4 field. */
+#define USBD_EPOUTEN_OUT4_Disable (0UL) /*!< Disable endpoint OUT 4 (no response to OUT tokens) */
+#define USBD_EPOUTEN_OUT4_Enable (1UL) /*!< Enable endpoint OUT 4 (response to OUT tokens) */
+
+/* Bit 3 : Enable OUT endpoint 3 */
+#define USBD_EPOUTEN_OUT3_Pos (3UL) /*!< Position of OUT3 field. */
+#define USBD_EPOUTEN_OUT3_Msk (0x1UL << USBD_EPOUTEN_OUT3_Pos) /*!< Bit mask of OUT3 field. */
+#define USBD_EPOUTEN_OUT3_Disable (0UL) /*!< Disable endpoint OUT 3 (no response to OUT tokens) */
+#define USBD_EPOUTEN_OUT3_Enable (1UL) /*!< Enable endpoint OUT 3 (response to OUT tokens) */
+
+/* Bit 2 : Enable OUT endpoint 2 */
+#define USBD_EPOUTEN_OUT2_Pos (2UL) /*!< Position of OUT2 field. */
+#define USBD_EPOUTEN_OUT2_Msk (0x1UL << USBD_EPOUTEN_OUT2_Pos) /*!< Bit mask of OUT2 field. */
+#define USBD_EPOUTEN_OUT2_Disable (0UL) /*!< Disable endpoint OUT 2 (no response to OUT tokens) */
+#define USBD_EPOUTEN_OUT2_Enable (1UL) /*!< Enable endpoint OUT 2 (response to OUT tokens) */
+
+/* Bit 1 : Enable OUT endpoint 1 */
+#define USBD_EPOUTEN_OUT1_Pos (1UL) /*!< Position of OUT1 field. */
+#define USBD_EPOUTEN_OUT1_Msk (0x1UL << USBD_EPOUTEN_OUT1_Pos) /*!< Bit mask of OUT1 field. */
+#define USBD_EPOUTEN_OUT1_Disable (0UL) /*!< Disable endpoint OUT 1 (no response to OUT tokens) */
+#define USBD_EPOUTEN_OUT1_Enable (1UL) /*!< Enable endpoint OUT 1 (response to OUT tokens) */
+
+/* Bit 0 : Enable OUT endpoint 0 */
+#define USBD_EPOUTEN_OUT0_Pos (0UL) /*!< Position of OUT0 field. */
+#define USBD_EPOUTEN_OUT0_Msk (0x1UL << USBD_EPOUTEN_OUT0_Pos) /*!< Bit mask of OUT0 field. */
+#define USBD_EPOUTEN_OUT0_Disable (0UL) /*!< Disable endpoint OUT 0 (no response to OUT tokens) */
+#define USBD_EPOUTEN_OUT0_Enable (1UL) /*!< Enable endpoint OUT 0 (response to OUT tokens) */
+
+/* Register: USBD_EPSTALL */
+/* Description: STALL endpoints */
+
+/* Bit 8 : Stall selected endpoint */
+#define USBD_EPSTALL_STALL_Pos (8UL) /*!< Position of STALL field. */
+#define USBD_EPSTALL_STALL_Msk (0x1UL << USBD_EPSTALL_STALL_Pos) /*!< Bit mask of STALL field. */
+#define USBD_EPSTALL_STALL_UnStall (0UL) /*!< Don't stall selected endpoint */
+#define USBD_EPSTALL_STALL_Stall (1UL) /*!< Stall selected endpoint */
+
+/* Bit 7 : Selects IN or OUT endpoint */
+#define USBD_EPSTALL_IO_Pos (7UL) /*!< Position of IO field. */
+#define USBD_EPSTALL_IO_Msk (0x1UL << USBD_EPSTALL_IO_Pos) /*!< Bit mask of IO field. */
+#define USBD_EPSTALL_IO_Out (0UL) /*!< Selects OUT endpoint */
+#define USBD_EPSTALL_IO_In (1UL) /*!< Selects IN endpoint */
+
+/* Bits 2..0 : Select endpoint number */
+#define USBD_EPSTALL_EP_Pos (0UL) /*!< Position of EP field. */
+#define USBD_EPSTALL_EP_Msk (0x7UL << USBD_EPSTALL_EP_Pos) /*!< Bit mask of EP field. */
+
+/* Register: USBD_ISOSPLIT */
+/* Description: Controls the split of ISO buffers */
+
+/* Bits 15..0 : Controls the split of ISO buffers */
+#define USBD_ISOSPLIT_SPLIT_Pos (0UL) /*!< Position of SPLIT field. */
+#define USBD_ISOSPLIT_SPLIT_Msk (0xFFFFUL << USBD_ISOSPLIT_SPLIT_Pos) /*!< Bit mask of SPLIT field. */
+#define USBD_ISOSPLIT_SPLIT_OneDir (0x0000UL) /*!< Full buffer dedicated to either iso IN or OUT */
+#define USBD_ISOSPLIT_SPLIT_HalfIN (0x0080UL) /*!< Lower half for IN, upper half for OUT */
+
+/* Register: USBD_FRAMECNTR */
+/* Description: Returns the current value of the start of frame counter */
+
+/* Bits 10..0 : Returns the current value of the start of frame counter */
+#define USBD_FRAMECNTR_FRAMECNTR_Pos (0UL) /*!< Position of FRAMECNTR field. */
+#define USBD_FRAMECNTR_FRAMECNTR_Msk (0x7FFUL << USBD_FRAMECNTR_FRAMECNTR_Pos) /*!< Bit mask of FRAMECNTR field. */
+
+/* Register: USBD_ISOINCONFIG */
+/* Description: Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent */
+
+/* Bit 0 : Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent */
+#define USBD_ISOINCONFIG_RESPONSE_Pos (0UL) /*!< Position of RESPONSE field. */
+#define USBD_ISOINCONFIG_RESPONSE_Msk (0x1UL << USBD_ISOINCONFIG_RESPONSE_Pos) /*!< Bit mask of RESPONSE field. */
+#define USBD_ISOINCONFIG_RESPONSE_NoResp (0UL) /*!< Endpoint does not respond in that case */
+#define USBD_ISOINCONFIG_RESPONSE_ZeroData (1UL) /*!< Endpoint responds with a zero-length data packet in that case */
+
+/* Register: USBD_EPIN_PTR */
+/* Description: Description cluster[0]:  Data pointer */
+
+/* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */
+#define USBD_EPIN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define USBD_EPIN_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPIN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: USBD_EPIN_MAXCNT */
+/* Description: Description cluster[0]:  Maximum number of bytes to transfer */
+
+/* Bits 6..0 : Maximum number of bytes to transfer */
+#define USBD_EPIN_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define USBD_EPIN_MAXCNT_MAXCNT_Msk (0x7FUL << USBD_EPIN_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: USBD_EPIN_AMOUNT */
+/* Description: Description cluster[0]:  Number of bytes transferred in the last transaction */
+
+/* Bits 6..0 : Number of bytes transferred in the last transaction */
+#define USBD_EPIN_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define USBD_EPIN_AMOUNT_AMOUNT_Msk (0x7FUL << USBD_EPIN_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: USBD_ISOIN_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */
+#define USBD_ISOIN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define USBD_ISOIN_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_ISOIN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: USBD_ISOIN_MAXCNT */
+/* Description: Maximum number of bytes to transfer */
+
+/* Bits 9..0 : Maximum number of bytes to transfer */
+#define USBD_ISOIN_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define USBD_ISOIN_MAXCNT_MAXCNT_Msk (0x3FFUL << USBD_ISOIN_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: USBD_ISOIN_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 9..0 : Number of bytes transferred in the last transaction */
+#define USBD_ISOIN_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define USBD_ISOIN_AMOUNT_AMOUNT_Msk (0x3FFUL << USBD_ISOIN_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: USBD_EPOUT_PTR */
+/* Description: Description cluster[0]:  Data pointer */
+
+/* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */
+#define USBD_EPOUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define USBD_EPOUT_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPOUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: USBD_EPOUT_MAXCNT */
+/* Description: Description cluster[0]:  Maximum number of bytes to transfer */
+
+/* Bits 6..0 : Maximum number of bytes to transfer */
+#define USBD_EPOUT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define USBD_EPOUT_MAXCNT_MAXCNT_Msk (0x7FUL << USBD_EPOUT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: USBD_EPOUT_AMOUNT */
+/* Description: Description cluster[0]:  Number of bytes transferred in the last transaction */
+
+/* Bits 6..0 : Number of bytes transferred in the last transaction */
+#define USBD_EPOUT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define USBD_EPOUT_AMOUNT_AMOUNT_Msk (0x7FUL << USBD_EPOUT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: USBD_ISOOUT_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */
+#define USBD_ISOOUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define USBD_ISOOUT_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_ISOOUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: USBD_ISOOUT_MAXCNT */
+/* Description: Maximum number of bytes to transfer */
+
+/* Bits 9..0 : Maximum number of bytes to transfer */
+#define USBD_ISOOUT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define USBD_ISOOUT_MAXCNT_MAXCNT_Msk (0x3FFUL << USBD_ISOOUT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: USBD_ISOOUT_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 9..0 : Number of bytes transferred in the last transaction */
+#define USBD_ISOOUT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define USBD_ISOOUT_AMOUNT_AMOUNT_Msk (0x3FFUL << USBD_ISOOUT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+
+/* Peripheral: WDT */
+/* Description: Watchdog Timer */
+
+/* Register: WDT_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 0 : Write '1' to Enable interrupt for TIMEOUT event */
+#define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
+#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
+#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
+#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
+#define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */
+
+/* Register: WDT_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 0 : Write '1' to Disable interrupt for TIMEOUT event */
+#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
+#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
+#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
+#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
+#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */
+
+/* Register: WDT_RUNSTATUS */
+/* Description: Run status */
+
+/* Bit 0 : Indicates whether or not the watchdog is running */
+#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */
+#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */
+#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog not running */
+#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog is running */
+
+/* Register: WDT_REQSTATUS */
+/* Description: Request status */
+
+/* Bit 7 : Request status for RR[7] register */
+#define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
+#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
+#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */
+
+/* Bit 6 : Request status for RR[6] register */
+#define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
+#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
+#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */
+
+/* Bit 5 : Request status for RR[5] register */
+#define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
+#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
+#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */
+
+/* Bit 4 : Request status for RR[4] register */
+#define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
+#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
+#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */
+
+/* Bit 3 : Request status for RR[3] register */
+#define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
+#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
+#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */
+
+/* Bit 2 : Request status for RR[2] register */
+#define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
+#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
+#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */
+
+/* Bit 1 : Request status for RR[1] register */
+#define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
+#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
+#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */
+
+/* Bit 0 : Request status for RR[0] register */
+#define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
+#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
+#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */
+
+/* Register: WDT_CRV */
+/* Description: Counter reload value */
+
+/* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */
+#define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */
+#define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */
+
+/* Register: WDT_RREN */
+/* Description: Enable register for reload request registers */
+
+/* Bit 7 : Enable or disable RR[7] register */
+#define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
+#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
+#define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */
+#define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */
+
+/* Bit 6 : Enable or disable RR[6] register */
+#define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
+#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
+#define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */
+#define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */
+
+/* Bit 5 : Enable or disable RR[5] register */
+#define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
+#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
+#define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */
+#define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */
+
+/* Bit 4 : Enable or disable RR[4] register */
+#define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
+#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
+#define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */
+#define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */
+
+/* Bit 3 : Enable or disable RR[3] register */
+#define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
+#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
+#define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */
+#define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */
+
+/* Bit 2 : Enable or disable RR[2] register */
+#define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
+#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
+#define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */
+#define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */
+
+/* Bit 1 : Enable or disable RR[1] register */
+#define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
+#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
+#define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */
+#define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */
+
+/* Bit 0 : Enable or disable RR[0] register */
+#define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
+#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
+#define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */
+#define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */
+
+/* Register: WDT_CONFIG */
+/* Description: Configuration register */
+
+/* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */
+#define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
+#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
+#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */
+#define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */
+
+/* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */
+#define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
+#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
+#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */
+#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */
+
+/* Register: WDT_RR */
+/* Description: Description collection[0]:  Reload request 0 */
+
+/* Bits 31..0 : Reload request register */
+#define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
+#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
+#define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */
+
+
+/*lint --flb "Leave library region" */
+#endif
diff --git a/ports/nrf/device/nrf52/nrf52_bitfields.h b/ports/nrf/device/nrf52/nrf52_bitfields.h
new file mode 100644
index 0000000000..b695bf8a19
--- /dev/null
+++ b/ports/nrf/device/nrf52/nrf52_bitfields.h
@@ -0,0 +1,12642 @@
+/* Copyright (c) 2016, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *   * Redistributions of source code must retain the above copyright notice, this
+ *     list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *
+ *   * Neither the name of Nordic Semiconductor ASA nor the names of its
+ *     contributors may be used to endorse or promote products derived from
+ *     this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+ 
+#ifndef __NRF52_BITS_H
+#define __NRF52_BITS_H
+
+/*lint ++flb "Enter library region" */
+
+/* Peripheral: AAR */
+/* Description: Accelerated Address Resolver */
+
+/* Register: AAR_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 2 : Write '1' to Enable interrupt for NOTRESOLVED event */
+#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
+#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
+#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
+#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
+#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for RESOLVED event */
+#define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
+#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
+#define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
+#define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
+#define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for END event */
+#define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
+#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define AAR_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Register: AAR_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 2 : Write '1' to Disable interrupt for NOTRESOLVED event */
+#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
+#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
+#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
+#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
+#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for RESOLVED event */
+#define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
+#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
+#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
+#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
+#define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for END event */
+#define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
+#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Register: AAR_STATUS */
+/* Description: Resolution status */
+
+/* Bits 3..0 : The IRK that was used last time an address was resolved */
+#define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
+
+/* Register: AAR_ENABLE */
+/* Description: Enable AAR */
+
+/* Bits 1..0 : Enable or disable AAR */
+#define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */
+
+/* Register: AAR_NIRK */
+/* Description: Number of IRKs */
+
+/* Bits 4..0 : Number of Identity root keys available in the IRK data structure */
+#define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
+#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
+
+/* Register: AAR_IRKPTR */
+/* Description: Pointer to IRK data structure */
+
+/* Bits 31..0 : Pointer to the IRK data structure */
+#define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */
+#define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */
+
+/* Register: AAR_ADDRPTR */
+/* Description: Pointer to the resolvable address */
+
+/* Bits 31..0 : Pointer to the resolvable address (6-bytes) */
+#define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */
+#define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */
+
+/* Register: AAR_SCRATCHPTR */
+/* Description: Pointer to data area used for temporary storage */
+
+/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. */
+#define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
+#define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
+
+
+/* Peripheral: BPROT */
+/* Description: Block Protect */
+
+/* Register: BPROT_CONFIG0 */
+/* Description: Block protect configuration register 0 */
+
+/* Bit 31 : Enable protection for region 31. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION31_Pos (31UL) /*!< Position of REGION31 field. */
+#define BPROT_CONFIG0_REGION31_Msk (0x1UL << BPROT_CONFIG0_REGION31_Pos) /*!< Bit mask of REGION31 field. */
+#define BPROT_CONFIG0_REGION31_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION31_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 30 : Enable protection for region 30. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION30_Pos (30UL) /*!< Position of REGION30 field. */
+#define BPROT_CONFIG0_REGION30_Msk (0x1UL << BPROT_CONFIG0_REGION30_Pos) /*!< Bit mask of REGION30 field. */
+#define BPROT_CONFIG0_REGION30_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION30_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 29 : Enable protection for region 29. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION29_Pos (29UL) /*!< Position of REGION29 field. */
+#define BPROT_CONFIG0_REGION29_Msk (0x1UL << BPROT_CONFIG0_REGION29_Pos) /*!< Bit mask of REGION29 field. */
+#define BPROT_CONFIG0_REGION29_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION29_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 28 : Enable protection for region 28. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION28_Pos (28UL) /*!< Position of REGION28 field. */
+#define BPROT_CONFIG0_REGION28_Msk (0x1UL << BPROT_CONFIG0_REGION28_Pos) /*!< Bit mask of REGION28 field. */
+#define BPROT_CONFIG0_REGION28_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION28_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 27 : Enable protection for region 27. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION27_Pos (27UL) /*!< Position of REGION27 field. */
+#define BPROT_CONFIG0_REGION27_Msk (0x1UL << BPROT_CONFIG0_REGION27_Pos) /*!< Bit mask of REGION27 field. */
+#define BPROT_CONFIG0_REGION27_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION27_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 26 : Enable protection for region 26. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION26_Pos (26UL) /*!< Position of REGION26 field. */
+#define BPROT_CONFIG0_REGION26_Msk (0x1UL << BPROT_CONFIG0_REGION26_Pos) /*!< Bit mask of REGION26 field. */
+#define BPROT_CONFIG0_REGION26_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION26_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 25 : Enable protection for region 25. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION25_Pos (25UL) /*!< Position of REGION25 field. */
+#define BPROT_CONFIG0_REGION25_Msk (0x1UL << BPROT_CONFIG0_REGION25_Pos) /*!< Bit mask of REGION25 field. */
+#define BPROT_CONFIG0_REGION25_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION25_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 24 : Enable protection for region 24. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION24_Pos (24UL) /*!< Position of REGION24 field. */
+#define BPROT_CONFIG0_REGION24_Msk (0x1UL << BPROT_CONFIG0_REGION24_Pos) /*!< Bit mask of REGION24 field. */
+#define BPROT_CONFIG0_REGION24_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION24_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 23 : Enable protection for region 23. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION23_Pos (23UL) /*!< Position of REGION23 field. */
+#define BPROT_CONFIG0_REGION23_Msk (0x1UL << BPROT_CONFIG0_REGION23_Pos) /*!< Bit mask of REGION23 field. */
+#define BPROT_CONFIG0_REGION23_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION23_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 22 : Enable protection for region 22. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION22_Pos (22UL) /*!< Position of REGION22 field. */
+#define BPROT_CONFIG0_REGION22_Msk (0x1UL << BPROT_CONFIG0_REGION22_Pos) /*!< Bit mask of REGION22 field. */
+#define BPROT_CONFIG0_REGION22_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION22_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 21 : Enable protection for region 21. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION21_Pos (21UL) /*!< Position of REGION21 field. */
+#define BPROT_CONFIG0_REGION21_Msk (0x1UL << BPROT_CONFIG0_REGION21_Pos) /*!< Bit mask of REGION21 field. */
+#define BPROT_CONFIG0_REGION21_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION21_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 20 : Enable protection for region 20. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION20_Pos (20UL) /*!< Position of REGION20 field. */
+#define BPROT_CONFIG0_REGION20_Msk (0x1UL << BPROT_CONFIG0_REGION20_Pos) /*!< Bit mask of REGION20 field. */
+#define BPROT_CONFIG0_REGION20_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION20_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 19 : Enable protection for region 19. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION19_Pos (19UL) /*!< Position of REGION19 field. */
+#define BPROT_CONFIG0_REGION19_Msk (0x1UL << BPROT_CONFIG0_REGION19_Pos) /*!< Bit mask of REGION19 field. */
+#define BPROT_CONFIG0_REGION19_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION19_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 18 : Enable protection for region 18. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION18_Pos (18UL) /*!< Position of REGION18 field. */
+#define BPROT_CONFIG0_REGION18_Msk (0x1UL << BPROT_CONFIG0_REGION18_Pos) /*!< Bit mask of REGION18 field. */
+#define BPROT_CONFIG0_REGION18_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION18_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 17 : Enable protection for region 17. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION17_Pos (17UL) /*!< Position of REGION17 field. */
+#define BPROT_CONFIG0_REGION17_Msk (0x1UL << BPROT_CONFIG0_REGION17_Pos) /*!< Bit mask of REGION17 field. */
+#define BPROT_CONFIG0_REGION17_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION17_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 16 : Enable protection for region 16. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION16_Pos (16UL) /*!< Position of REGION16 field. */
+#define BPROT_CONFIG0_REGION16_Msk (0x1UL << BPROT_CONFIG0_REGION16_Pos) /*!< Bit mask of REGION16 field. */
+#define BPROT_CONFIG0_REGION16_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION16_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 15 : Enable protection for region 15. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION15_Pos (15UL) /*!< Position of REGION15 field. */
+#define BPROT_CONFIG0_REGION15_Msk (0x1UL << BPROT_CONFIG0_REGION15_Pos) /*!< Bit mask of REGION15 field. */
+#define BPROT_CONFIG0_REGION15_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION15_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 14 : Enable protection for region 14. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION14_Pos (14UL) /*!< Position of REGION14 field. */
+#define BPROT_CONFIG0_REGION14_Msk (0x1UL << BPROT_CONFIG0_REGION14_Pos) /*!< Bit mask of REGION14 field. */
+#define BPROT_CONFIG0_REGION14_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION14_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 13 : Enable protection for region 13. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION13_Pos (13UL) /*!< Position of REGION13 field. */
+#define BPROT_CONFIG0_REGION13_Msk (0x1UL << BPROT_CONFIG0_REGION13_Pos) /*!< Bit mask of REGION13 field. */
+#define BPROT_CONFIG0_REGION13_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION13_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 12 : Enable protection for region 12. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION12_Pos (12UL) /*!< Position of REGION12 field. */
+#define BPROT_CONFIG0_REGION12_Msk (0x1UL << BPROT_CONFIG0_REGION12_Pos) /*!< Bit mask of REGION12 field. */
+#define BPROT_CONFIG0_REGION12_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION12_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 11 : Enable protection for region 11. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION11_Pos (11UL) /*!< Position of REGION11 field. */
+#define BPROT_CONFIG0_REGION11_Msk (0x1UL << BPROT_CONFIG0_REGION11_Pos) /*!< Bit mask of REGION11 field. */
+#define BPROT_CONFIG0_REGION11_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION11_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 10 : Enable protection for region 10. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION10_Pos (10UL) /*!< Position of REGION10 field. */
+#define BPROT_CONFIG0_REGION10_Msk (0x1UL << BPROT_CONFIG0_REGION10_Pos) /*!< Bit mask of REGION10 field. */
+#define BPROT_CONFIG0_REGION10_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION10_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 9 : Enable protection for region 9. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION9_Pos (9UL) /*!< Position of REGION9 field. */
+#define BPROT_CONFIG0_REGION9_Msk (0x1UL << BPROT_CONFIG0_REGION9_Pos) /*!< Bit mask of REGION9 field. */
+#define BPROT_CONFIG0_REGION9_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION9_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 8 : Enable protection for region 8. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION8_Pos (8UL) /*!< Position of REGION8 field. */
+#define BPROT_CONFIG0_REGION8_Msk (0x1UL << BPROT_CONFIG0_REGION8_Pos) /*!< Bit mask of REGION8 field. */
+#define BPROT_CONFIG0_REGION8_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION8_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 7 : Enable protection for region 7. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION7_Pos (7UL) /*!< Position of REGION7 field. */
+#define BPROT_CONFIG0_REGION7_Msk (0x1UL << BPROT_CONFIG0_REGION7_Pos) /*!< Bit mask of REGION7 field. */
+#define BPROT_CONFIG0_REGION7_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION7_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 6 : Enable protection for region 6. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION6_Pos (6UL) /*!< Position of REGION6 field. */
+#define BPROT_CONFIG0_REGION6_Msk (0x1UL << BPROT_CONFIG0_REGION6_Pos) /*!< Bit mask of REGION6 field. */
+#define BPROT_CONFIG0_REGION6_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION6_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 5 : Enable protection for region 5. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION5_Pos (5UL) /*!< Position of REGION5 field. */
+#define BPROT_CONFIG0_REGION5_Msk (0x1UL << BPROT_CONFIG0_REGION5_Pos) /*!< Bit mask of REGION5 field. */
+#define BPROT_CONFIG0_REGION5_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION5_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 4 : Enable protection for region 4. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION4_Pos (4UL) /*!< Position of REGION4 field. */
+#define BPROT_CONFIG0_REGION4_Msk (0x1UL << BPROT_CONFIG0_REGION4_Pos) /*!< Bit mask of REGION4 field. */
+#define BPROT_CONFIG0_REGION4_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION4_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 3 : Enable protection for region 3. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION3_Pos (3UL) /*!< Position of REGION3 field. */
+#define BPROT_CONFIG0_REGION3_Msk (0x1UL << BPROT_CONFIG0_REGION3_Pos) /*!< Bit mask of REGION3 field. */
+#define BPROT_CONFIG0_REGION3_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION3_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 2 : Enable protection for region 2. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION2_Pos (2UL) /*!< Position of REGION2 field. */
+#define BPROT_CONFIG0_REGION2_Msk (0x1UL << BPROT_CONFIG0_REGION2_Pos) /*!< Bit mask of REGION2 field. */
+#define BPROT_CONFIG0_REGION2_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION2_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 1 : Enable protection for region 1. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION1_Pos (1UL) /*!< Position of REGION1 field. */
+#define BPROT_CONFIG0_REGION1_Msk (0x1UL << BPROT_CONFIG0_REGION1_Pos) /*!< Bit mask of REGION1 field. */
+#define BPROT_CONFIG0_REGION1_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION1_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 0 : Enable protection for region 0. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION0_Pos (0UL) /*!< Position of REGION0 field. */
+#define BPROT_CONFIG0_REGION0_Msk (0x1UL << BPROT_CONFIG0_REGION0_Pos) /*!< Bit mask of REGION0 field. */
+#define BPROT_CONFIG0_REGION0_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION0_Enabled (1UL) /*!< Protection enable */
+
+/* Register: BPROT_CONFIG1 */
+/* Description: Block protect configuration register 1 */
+
+/* Bit 31 : Enable protection for region 63. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION63_Pos (31UL) /*!< Position of REGION63 field. */
+#define BPROT_CONFIG1_REGION63_Msk (0x1UL << BPROT_CONFIG1_REGION63_Pos) /*!< Bit mask of REGION63 field. */
+#define BPROT_CONFIG1_REGION63_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION63_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 30 : Enable protection for region 62. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION62_Pos (30UL) /*!< Position of REGION62 field. */
+#define BPROT_CONFIG1_REGION62_Msk (0x1UL << BPROT_CONFIG1_REGION62_Pos) /*!< Bit mask of REGION62 field. */
+#define BPROT_CONFIG1_REGION62_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION62_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 29 : Enable protection for region 61. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION61_Pos (29UL) /*!< Position of REGION61 field. */
+#define BPROT_CONFIG1_REGION61_Msk (0x1UL << BPROT_CONFIG1_REGION61_Pos) /*!< Bit mask of REGION61 field. */
+#define BPROT_CONFIG1_REGION61_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION61_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 28 : Enable protection for region 60. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION60_Pos (28UL) /*!< Position of REGION60 field. */
+#define BPROT_CONFIG1_REGION60_Msk (0x1UL << BPROT_CONFIG1_REGION60_Pos) /*!< Bit mask of REGION60 field. */
+#define BPROT_CONFIG1_REGION60_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION60_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 27 : Enable protection for region 59. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION59_Pos (27UL) /*!< Position of REGION59 field. */
+#define BPROT_CONFIG1_REGION59_Msk (0x1UL << BPROT_CONFIG1_REGION59_Pos) /*!< Bit mask of REGION59 field. */
+#define BPROT_CONFIG1_REGION59_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION59_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 26 : Enable protection for region 58. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION58_Pos (26UL) /*!< Position of REGION58 field. */
+#define BPROT_CONFIG1_REGION58_Msk (0x1UL << BPROT_CONFIG1_REGION58_Pos) /*!< Bit mask of REGION58 field. */
+#define BPROT_CONFIG1_REGION58_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION58_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 25 : Enable protection for region 57. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION57_Pos (25UL) /*!< Position of REGION57 field. */
+#define BPROT_CONFIG1_REGION57_Msk (0x1UL << BPROT_CONFIG1_REGION57_Pos) /*!< Bit mask of REGION57 field. */
+#define BPROT_CONFIG1_REGION57_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION57_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 24 : Enable protection for region 56. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION56_Pos (24UL) /*!< Position of REGION56 field. */
+#define BPROT_CONFIG1_REGION56_Msk (0x1UL << BPROT_CONFIG1_REGION56_Pos) /*!< Bit mask of REGION56 field. */
+#define BPROT_CONFIG1_REGION56_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION56_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 23 : Enable protection for region 55. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION55_Pos (23UL) /*!< Position of REGION55 field. */
+#define BPROT_CONFIG1_REGION55_Msk (0x1UL << BPROT_CONFIG1_REGION55_Pos) /*!< Bit mask of REGION55 field. */
+#define BPROT_CONFIG1_REGION55_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION55_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 22 : Enable protection for region 54. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION54_Pos (22UL) /*!< Position of REGION54 field. */
+#define BPROT_CONFIG1_REGION54_Msk (0x1UL << BPROT_CONFIG1_REGION54_Pos) /*!< Bit mask of REGION54 field. */
+#define BPROT_CONFIG1_REGION54_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION54_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 21 : Enable protection for region 53. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION53_Pos (21UL) /*!< Position of REGION53 field. */
+#define BPROT_CONFIG1_REGION53_Msk (0x1UL << BPROT_CONFIG1_REGION53_Pos) /*!< Bit mask of REGION53 field. */
+#define BPROT_CONFIG1_REGION53_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION53_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 20 : Enable protection for region 52. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION52_Pos (20UL) /*!< Position of REGION52 field. */
+#define BPROT_CONFIG1_REGION52_Msk (0x1UL << BPROT_CONFIG1_REGION52_Pos) /*!< Bit mask of REGION52 field. */
+#define BPROT_CONFIG1_REGION52_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION52_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 19 : Enable protection for region 51. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION51_Pos (19UL) /*!< Position of REGION51 field. */
+#define BPROT_CONFIG1_REGION51_Msk (0x1UL << BPROT_CONFIG1_REGION51_Pos) /*!< Bit mask of REGION51 field. */
+#define BPROT_CONFIG1_REGION51_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION51_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 18 : Enable protection for region 50. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION50_Pos (18UL) /*!< Position of REGION50 field. */
+#define BPROT_CONFIG1_REGION50_Msk (0x1UL << BPROT_CONFIG1_REGION50_Pos) /*!< Bit mask of REGION50 field. */
+#define BPROT_CONFIG1_REGION50_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION50_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 17 : Enable protection for region 49. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION49_Pos (17UL) /*!< Position of REGION49 field. */
+#define BPROT_CONFIG1_REGION49_Msk (0x1UL << BPROT_CONFIG1_REGION49_Pos) /*!< Bit mask of REGION49 field. */
+#define BPROT_CONFIG1_REGION49_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION49_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 16 : Enable protection for region 48. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION48_Pos (16UL) /*!< Position of REGION48 field. */
+#define BPROT_CONFIG1_REGION48_Msk (0x1UL << BPROT_CONFIG1_REGION48_Pos) /*!< Bit mask of REGION48 field. */
+#define BPROT_CONFIG1_REGION48_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION48_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 15 : Enable protection for region 47. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION47_Pos (15UL) /*!< Position of REGION47 field. */
+#define BPROT_CONFIG1_REGION47_Msk (0x1UL << BPROT_CONFIG1_REGION47_Pos) /*!< Bit mask of REGION47 field. */
+#define BPROT_CONFIG1_REGION47_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION47_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 14 : Enable protection for region 46. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION46_Pos (14UL) /*!< Position of REGION46 field. */
+#define BPROT_CONFIG1_REGION46_Msk (0x1UL << BPROT_CONFIG1_REGION46_Pos) /*!< Bit mask of REGION46 field. */
+#define BPROT_CONFIG1_REGION46_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION46_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 13 : Enable protection for region 45. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION45_Pos (13UL) /*!< Position of REGION45 field. */
+#define BPROT_CONFIG1_REGION45_Msk (0x1UL << BPROT_CONFIG1_REGION45_Pos) /*!< Bit mask of REGION45 field. */
+#define BPROT_CONFIG1_REGION45_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION45_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 12 : Enable protection for region 44. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION44_Pos (12UL) /*!< Position of REGION44 field. */
+#define BPROT_CONFIG1_REGION44_Msk (0x1UL << BPROT_CONFIG1_REGION44_Pos) /*!< Bit mask of REGION44 field. */
+#define BPROT_CONFIG1_REGION44_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION44_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 11 : Enable protection for region 43. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION43_Pos (11UL) /*!< Position of REGION43 field. */
+#define BPROT_CONFIG1_REGION43_Msk (0x1UL << BPROT_CONFIG1_REGION43_Pos) /*!< Bit mask of REGION43 field. */
+#define BPROT_CONFIG1_REGION43_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION43_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 10 : Enable protection for region 42. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION42_Pos (10UL) /*!< Position of REGION42 field. */
+#define BPROT_CONFIG1_REGION42_Msk (0x1UL << BPROT_CONFIG1_REGION42_Pos) /*!< Bit mask of REGION42 field. */
+#define BPROT_CONFIG1_REGION42_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION42_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 9 : Enable protection for region 41. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION41_Pos (9UL) /*!< Position of REGION41 field. */
+#define BPROT_CONFIG1_REGION41_Msk (0x1UL << BPROT_CONFIG1_REGION41_Pos) /*!< Bit mask of REGION41 field. */
+#define BPROT_CONFIG1_REGION41_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION41_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 8 : Enable protection for region 40. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION40_Pos (8UL) /*!< Position of REGION40 field. */
+#define BPROT_CONFIG1_REGION40_Msk (0x1UL << BPROT_CONFIG1_REGION40_Pos) /*!< Bit mask of REGION40 field. */
+#define BPROT_CONFIG1_REGION40_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION40_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 7 : Enable protection for region 39. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION39_Pos (7UL) /*!< Position of REGION39 field. */
+#define BPROT_CONFIG1_REGION39_Msk (0x1UL << BPROT_CONFIG1_REGION39_Pos) /*!< Bit mask of REGION39 field. */
+#define BPROT_CONFIG1_REGION39_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION39_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 6 : Enable protection for region 38. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION38_Pos (6UL) /*!< Position of REGION38 field. */
+#define BPROT_CONFIG1_REGION38_Msk (0x1UL << BPROT_CONFIG1_REGION38_Pos) /*!< Bit mask of REGION38 field. */
+#define BPROT_CONFIG1_REGION38_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION38_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 5 : Enable protection for region 37. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION37_Pos (5UL) /*!< Position of REGION37 field. */
+#define BPROT_CONFIG1_REGION37_Msk (0x1UL << BPROT_CONFIG1_REGION37_Pos) /*!< Bit mask of REGION37 field. */
+#define BPROT_CONFIG1_REGION37_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION37_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 4 : Enable protection for region 36. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION36_Pos (4UL) /*!< Position of REGION36 field. */
+#define BPROT_CONFIG1_REGION36_Msk (0x1UL << BPROT_CONFIG1_REGION36_Pos) /*!< Bit mask of REGION36 field. */
+#define BPROT_CONFIG1_REGION36_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION36_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 3 : Enable protection for region 35. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION35_Pos (3UL) /*!< Position of REGION35 field. */
+#define BPROT_CONFIG1_REGION35_Msk (0x1UL << BPROT_CONFIG1_REGION35_Pos) /*!< Bit mask of REGION35 field. */
+#define BPROT_CONFIG1_REGION35_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION35_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 2 : Enable protection for region 34. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION34_Pos (2UL) /*!< Position of REGION34 field. */
+#define BPROT_CONFIG1_REGION34_Msk (0x1UL << BPROT_CONFIG1_REGION34_Pos) /*!< Bit mask of REGION34 field. */
+#define BPROT_CONFIG1_REGION34_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION34_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 1 : Enable protection for region 33. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION33_Pos (1UL) /*!< Position of REGION33 field. */
+#define BPROT_CONFIG1_REGION33_Msk (0x1UL << BPROT_CONFIG1_REGION33_Pos) /*!< Bit mask of REGION33 field. */
+#define BPROT_CONFIG1_REGION33_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION33_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 0 : Enable protection for region 32. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION32_Pos (0UL) /*!< Position of REGION32 field. */
+#define BPROT_CONFIG1_REGION32_Msk (0x1UL << BPROT_CONFIG1_REGION32_Pos) /*!< Bit mask of REGION32 field. */
+#define BPROT_CONFIG1_REGION32_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION32_Enabled (1UL) /*!< Protection enabled */
+
+/* Register: BPROT_DISABLEINDEBUG */
+/* Description: Disable protection mechanism in debug interface mode */
+
+/* Bit 0 : Disable the protection mechanism for NVM regions while in debug interface mode. This register will only disable the protection mechanism if the device is in debug interface mode. */
+#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */
+#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */
+#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Enable in debug */
+#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Disable in debug */
+
+/* Register: BPROT_CONFIG2 */
+/* Description: Block protect configuration register 2 */
+
+/* Bit 31 : Enable protection for region 95. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION95_Pos (31UL) /*!< Position of REGION95 field. */
+#define BPROT_CONFIG2_REGION95_Msk (0x1UL << BPROT_CONFIG2_REGION95_Pos) /*!< Bit mask of REGION95 field. */
+#define BPROT_CONFIG2_REGION95_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION95_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 30 : Enable protection for region 94. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION94_Pos (30UL) /*!< Position of REGION94 field. */
+#define BPROT_CONFIG2_REGION94_Msk (0x1UL << BPROT_CONFIG2_REGION94_Pos) /*!< Bit mask of REGION94 field. */
+#define BPROT_CONFIG2_REGION94_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION94_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 29 : Enable protection for region 93. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION93_Pos (29UL) /*!< Position of REGION93 field. */
+#define BPROT_CONFIG2_REGION93_Msk (0x1UL << BPROT_CONFIG2_REGION93_Pos) /*!< Bit mask of REGION93 field. */
+#define BPROT_CONFIG2_REGION93_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION93_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 28 : Enable protection for region 92. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION92_Pos (28UL) /*!< Position of REGION92 field. */
+#define BPROT_CONFIG2_REGION92_Msk (0x1UL << BPROT_CONFIG2_REGION92_Pos) /*!< Bit mask of REGION92 field. */
+#define BPROT_CONFIG2_REGION92_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION92_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 27 : Enable protection for region 91. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION91_Pos (27UL) /*!< Position of REGION91 field. */
+#define BPROT_CONFIG2_REGION91_Msk (0x1UL << BPROT_CONFIG2_REGION91_Pos) /*!< Bit mask of REGION91 field. */
+#define BPROT_CONFIG2_REGION91_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION91_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 26 : Enable protection for region 90. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION90_Pos (26UL) /*!< Position of REGION90 field. */
+#define BPROT_CONFIG2_REGION90_Msk (0x1UL << BPROT_CONFIG2_REGION90_Pos) /*!< Bit mask of REGION90 field. */
+#define BPROT_CONFIG2_REGION90_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION90_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 25 : Enable protection for region 89. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION89_Pos (25UL) /*!< Position of REGION89 field. */
+#define BPROT_CONFIG2_REGION89_Msk (0x1UL << BPROT_CONFIG2_REGION89_Pos) /*!< Bit mask of REGION89 field. */
+#define BPROT_CONFIG2_REGION89_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION89_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 24 : Enable protection for region 88. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION88_Pos (24UL) /*!< Position of REGION88 field. */
+#define BPROT_CONFIG2_REGION88_Msk (0x1UL << BPROT_CONFIG2_REGION88_Pos) /*!< Bit mask of REGION88 field. */
+#define BPROT_CONFIG2_REGION88_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION88_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 23 : Enable protection for region 87. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION87_Pos (23UL) /*!< Position of REGION87 field. */
+#define BPROT_CONFIG2_REGION87_Msk (0x1UL << BPROT_CONFIG2_REGION87_Pos) /*!< Bit mask of REGION87 field. */
+#define BPROT_CONFIG2_REGION87_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION87_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 22 : Enable protection for region 86. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION86_Pos (22UL) /*!< Position of REGION86 field. */
+#define BPROT_CONFIG2_REGION86_Msk (0x1UL << BPROT_CONFIG2_REGION86_Pos) /*!< Bit mask of REGION86 field. */
+#define BPROT_CONFIG2_REGION86_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION86_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 21 : Enable protection for region 85. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION85_Pos (21UL) /*!< Position of REGION85 field. */
+#define BPROT_CONFIG2_REGION85_Msk (0x1UL << BPROT_CONFIG2_REGION85_Pos) /*!< Bit mask of REGION85 field. */
+#define BPROT_CONFIG2_REGION85_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION85_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 20 : Enable protection for region 84. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION84_Pos (20UL) /*!< Position of REGION84 field. */
+#define BPROT_CONFIG2_REGION84_Msk (0x1UL << BPROT_CONFIG2_REGION84_Pos) /*!< Bit mask of REGION84 field. */
+#define BPROT_CONFIG2_REGION84_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION84_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 19 : Enable protection for region 83. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION83_Pos (19UL) /*!< Position of REGION83 field. */
+#define BPROT_CONFIG2_REGION83_Msk (0x1UL << BPROT_CONFIG2_REGION83_Pos) /*!< Bit mask of REGION83 field. */
+#define BPROT_CONFIG2_REGION83_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION83_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 18 : Enable protection for region 82. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION82_Pos (18UL) /*!< Position of REGION82 field. */
+#define BPROT_CONFIG2_REGION82_Msk (0x1UL << BPROT_CONFIG2_REGION82_Pos) /*!< Bit mask of REGION82 field. */
+#define BPROT_CONFIG2_REGION82_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION82_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 17 : Enable protection for region 81. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION81_Pos (17UL) /*!< Position of REGION81 field. */
+#define BPROT_CONFIG2_REGION81_Msk (0x1UL << BPROT_CONFIG2_REGION81_Pos) /*!< Bit mask of REGION81 field. */
+#define BPROT_CONFIG2_REGION81_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION81_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 16 : Enable protection for region 80. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION80_Pos (16UL) /*!< Position of REGION80 field. */
+#define BPROT_CONFIG2_REGION80_Msk (0x1UL << BPROT_CONFIG2_REGION80_Pos) /*!< Bit mask of REGION80 field. */
+#define BPROT_CONFIG2_REGION80_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION80_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 15 : Enable protection for region 79. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION79_Pos (15UL) /*!< Position of REGION79 field. */
+#define BPROT_CONFIG2_REGION79_Msk (0x1UL << BPROT_CONFIG2_REGION79_Pos) /*!< Bit mask of REGION79 field. */
+#define BPROT_CONFIG2_REGION79_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION79_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 14 : Enable protection for region 78. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION78_Pos (14UL) /*!< Position of REGION78 field. */
+#define BPROT_CONFIG2_REGION78_Msk (0x1UL << BPROT_CONFIG2_REGION78_Pos) /*!< Bit mask of REGION78 field. */
+#define BPROT_CONFIG2_REGION78_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION78_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 13 : Enable protection for region 77. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION77_Pos (13UL) /*!< Position of REGION77 field. */
+#define BPROT_CONFIG2_REGION77_Msk (0x1UL << BPROT_CONFIG2_REGION77_Pos) /*!< Bit mask of REGION77 field. */
+#define BPROT_CONFIG2_REGION77_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION77_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 12 : Enable protection for region 76. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION76_Pos (12UL) /*!< Position of REGION76 field. */
+#define BPROT_CONFIG2_REGION76_Msk (0x1UL << BPROT_CONFIG2_REGION76_Pos) /*!< Bit mask of REGION76 field. */
+#define BPROT_CONFIG2_REGION76_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION76_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 11 : Enable protection for region 75. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION75_Pos (11UL) /*!< Position of REGION75 field. */
+#define BPROT_CONFIG2_REGION75_Msk (0x1UL << BPROT_CONFIG2_REGION75_Pos) /*!< Bit mask of REGION75 field. */
+#define BPROT_CONFIG2_REGION75_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION75_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 10 : Enable protection for region 74. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION74_Pos (10UL) /*!< Position of REGION74 field. */
+#define BPROT_CONFIG2_REGION74_Msk (0x1UL << BPROT_CONFIG2_REGION74_Pos) /*!< Bit mask of REGION74 field. */
+#define BPROT_CONFIG2_REGION74_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION74_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 9 : Enable protection for region 73. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION73_Pos (9UL) /*!< Position of REGION73 field. */
+#define BPROT_CONFIG2_REGION73_Msk (0x1UL << BPROT_CONFIG2_REGION73_Pos) /*!< Bit mask of REGION73 field. */
+#define BPROT_CONFIG2_REGION73_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION73_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 8 : Enable protection for region 72. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION72_Pos (8UL) /*!< Position of REGION72 field. */
+#define BPROT_CONFIG2_REGION72_Msk (0x1UL << BPROT_CONFIG2_REGION72_Pos) /*!< Bit mask of REGION72 field. */
+#define BPROT_CONFIG2_REGION72_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION72_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 7 : Enable protection for region 71. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION71_Pos (7UL) /*!< Position of REGION71 field. */
+#define BPROT_CONFIG2_REGION71_Msk (0x1UL << BPROT_CONFIG2_REGION71_Pos) /*!< Bit mask of REGION71 field. */
+#define BPROT_CONFIG2_REGION71_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION71_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 6 : Enable protection for region 70. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION70_Pos (6UL) /*!< Position of REGION70 field. */
+#define BPROT_CONFIG2_REGION70_Msk (0x1UL << BPROT_CONFIG2_REGION70_Pos) /*!< Bit mask of REGION70 field. */
+#define BPROT_CONFIG2_REGION70_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION70_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 5 : Enable protection for region 69. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION69_Pos (5UL) /*!< Position of REGION69 field. */
+#define BPROT_CONFIG2_REGION69_Msk (0x1UL << BPROT_CONFIG2_REGION69_Pos) /*!< Bit mask of REGION69 field. */
+#define BPROT_CONFIG2_REGION69_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION69_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 4 : Enable protection for region 68. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION68_Pos (4UL) /*!< Position of REGION68 field. */
+#define BPROT_CONFIG2_REGION68_Msk (0x1UL << BPROT_CONFIG2_REGION68_Pos) /*!< Bit mask of REGION68 field. */
+#define BPROT_CONFIG2_REGION68_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION68_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 3 : Enable protection for region 67. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION67_Pos (3UL) /*!< Position of REGION67 field. */
+#define BPROT_CONFIG2_REGION67_Msk (0x1UL << BPROT_CONFIG2_REGION67_Pos) /*!< Bit mask of REGION67 field. */
+#define BPROT_CONFIG2_REGION67_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION67_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 2 : Enable protection for region 66. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION66_Pos (2UL) /*!< Position of REGION66 field. */
+#define BPROT_CONFIG2_REGION66_Msk (0x1UL << BPROT_CONFIG2_REGION66_Pos) /*!< Bit mask of REGION66 field. */
+#define BPROT_CONFIG2_REGION66_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION66_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 1 : Enable protection for region 65. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION65_Pos (1UL) /*!< Position of REGION65 field. */
+#define BPROT_CONFIG2_REGION65_Msk (0x1UL << BPROT_CONFIG2_REGION65_Pos) /*!< Bit mask of REGION65 field. */
+#define BPROT_CONFIG2_REGION65_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION65_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 0 : Enable protection for region 64. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION64_Pos (0UL) /*!< Position of REGION64 field. */
+#define BPROT_CONFIG2_REGION64_Msk (0x1UL << BPROT_CONFIG2_REGION64_Pos) /*!< Bit mask of REGION64 field. */
+#define BPROT_CONFIG2_REGION64_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION64_Enabled (1UL) /*!< Protection enabled */
+
+/* Register: BPROT_CONFIG3 */
+/* Description: Block protect configuration register 3 */
+
+/* Bit 31 : Enable protection for region 127. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION127_Pos (31UL) /*!< Position of REGION127 field. */
+#define BPROT_CONFIG3_REGION127_Msk (0x1UL << BPROT_CONFIG3_REGION127_Pos) /*!< Bit mask of REGION127 field. */
+#define BPROT_CONFIG3_REGION127_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION127_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 30 : Enable protection for region 126. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION126_Pos (30UL) /*!< Position of REGION126 field. */
+#define BPROT_CONFIG3_REGION126_Msk (0x1UL << BPROT_CONFIG3_REGION126_Pos) /*!< Bit mask of REGION126 field. */
+#define BPROT_CONFIG3_REGION126_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION126_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 29 : Enable protection for region 125. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION125_Pos (29UL) /*!< Position of REGION125 field. */
+#define BPROT_CONFIG3_REGION125_Msk (0x1UL << BPROT_CONFIG3_REGION125_Pos) /*!< Bit mask of REGION125 field. */
+#define BPROT_CONFIG3_REGION125_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION125_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 28 : Enable protection for region 124. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION124_Pos (28UL) /*!< Position of REGION124 field. */
+#define BPROT_CONFIG3_REGION124_Msk (0x1UL << BPROT_CONFIG3_REGION124_Pos) /*!< Bit mask of REGION124 field. */
+#define BPROT_CONFIG3_REGION124_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION124_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 27 : Enable protection for region 123. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION123_Pos (27UL) /*!< Position of REGION123 field. */
+#define BPROT_CONFIG3_REGION123_Msk (0x1UL << BPROT_CONFIG3_REGION123_Pos) /*!< Bit mask of REGION123 field. */
+#define BPROT_CONFIG3_REGION123_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION123_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 26 : Enable protection for region 122. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION122_Pos (26UL) /*!< Position of REGION122 field. */
+#define BPROT_CONFIG3_REGION122_Msk (0x1UL << BPROT_CONFIG3_REGION122_Pos) /*!< Bit mask of REGION122 field. */
+#define BPROT_CONFIG3_REGION122_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION122_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 25 : Enable protection for region 121. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION121_Pos (25UL) /*!< Position of REGION121 field. */
+#define BPROT_CONFIG3_REGION121_Msk (0x1UL << BPROT_CONFIG3_REGION121_Pos) /*!< Bit mask of REGION121 field. */
+#define BPROT_CONFIG3_REGION121_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION121_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 24 : Enable protection for region 120. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION120_Pos (24UL) /*!< Position of REGION120 field. */
+#define BPROT_CONFIG3_REGION120_Msk (0x1UL << BPROT_CONFIG3_REGION120_Pos) /*!< Bit mask of REGION120 field. */
+#define BPROT_CONFIG3_REGION120_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION120_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 23 : Enable protection for region 119. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION119_Pos (23UL) /*!< Position of REGION119 field. */
+#define BPROT_CONFIG3_REGION119_Msk (0x1UL << BPROT_CONFIG3_REGION119_Pos) /*!< Bit mask of REGION119 field. */
+#define BPROT_CONFIG3_REGION119_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION119_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 22 : Enable protection for region 118. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION118_Pos (22UL) /*!< Position of REGION118 field. */
+#define BPROT_CONFIG3_REGION118_Msk (0x1UL << BPROT_CONFIG3_REGION118_Pos) /*!< Bit mask of REGION118 field. */
+#define BPROT_CONFIG3_REGION118_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION118_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 21 : Enable protection for region 117. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION117_Pos (21UL) /*!< Position of REGION117 field. */
+#define BPROT_CONFIG3_REGION117_Msk (0x1UL << BPROT_CONFIG3_REGION117_Pos) /*!< Bit mask of REGION117 field. */
+#define BPROT_CONFIG3_REGION117_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION117_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 20 : Enable protection for region 116. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION116_Pos (20UL) /*!< Position of REGION116 field. */
+#define BPROT_CONFIG3_REGION116_Msk (0x1UL << BPROT_CONFIG3_REGION116_Pos) /*!< Bit mask of REGION116 field. */
+#define BPROT_CONFIG3_REGION116_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION116_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 19 : Enable protection for region 115. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION115_Pos (19UL) /*!< Position of REGION115 field. */
+#define BPROT_CONFIG3_REGION115_Msk (0x1UL << BPROT_CONFIG3_REGION115_Pos) /*!< Bit mask of REGION115 field. */
+#define BPROT_CONFIG3_REGION115_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION115_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 18 : Enable protection for region 114. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION114_Pos (18UL) /*!< Position of REGION114 field. */
+#define BPROT_CONFIG3_REGION114_Msk (0x1UL << BPROT_CONFIG3_REGION114_Pos) /*!< Bit mask of REGION114 field. */
+#define BPROT_CONFIG3_REGION114_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION114_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 17 : Enable protection for region 113. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION113_Pos (17UL) /*!< Position of REGION113 field. */
+#define BPROT_CONFIG3_REGION113_Msk (0x1UL << BPROT_CONFIG3_REGION113_Pos) /*!< Bit mask of REGION113 field. */
+#define BPROT_CONFIG3_REGION113_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION113_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 16 : Enable protection for region 112. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION112_Pos (16UL) /*!< Position of REGION112 field. */
+#define BPROT_CONFIG3_REGION112_Msk (0x1UL << BPROT_CONFIG3_REGION112_Pos) /*!< Bit mask of REGION112 field. */
+#define BPROT_CONFIG3_REGION112_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION112_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 15 : Enable protection for region 111. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION111_Pos (15UL) /*!< Position of REGION111 field. */
+#define BPROT_CONFIG3_REGION111_Msk (0x1UL << BPROT_CONFIG3_REGION111_Pos) /*!< Bit mask of REGION111 field. */
+#define BPROT_CONFIG3_REGION111_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION111_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 14 : Enable protection for region 110. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION110_Pos (14UL) /*!< Position of REGION110 field. */
+#define BPROT_CONFIG3_REGION110_Msk (0x1UL << BPROT_CONFIG3_REGION110_Pos) /*!< Bit mask of REGION110 field. */
+#define BPROT_CONFIG3_REGION110_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION110_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 13 : Enable protection for region 109. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION109_Pos (13UL) /*!< Position of REGION109 field. */
+#define BPROT_CONFIG3_REGION109_Msk (0x1UL << BPROT_CONFIG3_REGION109_Pos) /*!< Bit mask of REGION109 field. */
+#define BPROT_CONFIG3_REGION109_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION109_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 12 : Enable protection for region 108. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION108_Pos (12UL) /*!< Position of REGION108 field. */
+#define BPROT_CONFIG3_REGION108_Msk (0x1UL << BPROT_CONFIG3_REGION108_Pos) /*!< Bit mask of REGION108 field. */
+#define BPROT_CONFIG3_REGION108_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION108_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 11 : Enable protection for region 107. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION107_Pos (11UL) /*!< Position of REGION107 field. */
+#define BPROT_CONFIG3_REGION107_Msk (0x1UL << BPROT_CONFIG3_REGION107_Pos) /*!< Bit mask of REGION107 field. */
+#define BPROT_CONFIG3_REGION107_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION107_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 10 : Enable protection for region 106. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION106_Pos (10UL) /*!< Position of REGION106 field. */
+#define BPROT_CONFIG3_REGION106_Msk (0x1UL << BPROT_CONFIG3_REGION106_Pos) /*!< Bit mask of REGION106 field. */
+#define BPROT_CONFIG3_REGION106_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION106_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 9 : Enable protection for region 105. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION105_Pos (9UL) /*!< Position of REGION105 field. */
+#define BPROT_CONFIG3_REGION105_Msk (0x1UL << BPROT_CONFIG3_REGION105_Pos) /*!< Bit mask of REGION105 field. */
+#define BPROT_CONFIG3_REGION105_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION105_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 8 : Enable protection for region 104. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION104_Pos (8UL) /*!< Position of REGION104 field. */
+#define BPROT_CONFIG3_REGION104_Msk (0x1UL << BPROT_CONFIG3_REGION104_Pos) /*!< Bit mask of REGION104 field. */
+#define BPROT_CONFIG3_REGION104_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION104_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 7 : Enable protection for region 103. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION103_Pos (7UL) /*!< Position of REGION103 field. */
+#define BPROT_CONFIG3_REGION103_Msk (0x1UL << BPROT_CONFIG3_REGION103_Pos) /*!< Bit mask of REGION103 field. */
+#define BPROT_CONFIG3_REGION103_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION103_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 6 : Enable protection for region 102. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION102_Pos (6UL) /*!< Position of REGION102 field. */
+#define BPROT_CONFIG3_REGION102_Msk (0x1UL << BPROT_CONFIG3_REGION102_Pos) /*!< Bit mask of REGION102 field. */
+#define BPROT_CONFIG3_REGION102_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION102_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 5 : Enable protection for region 101. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION101_Pos (5UL) /*!< Position of REGION101 field. */
+#define BPROT_CONFIG3_REGION101_Msk (0x1UL << BPROT_CONFIG3_REGION101_Pos) /*!< Bit mask of REGION101 field. */
+#define BPROT_CONFIG3_REGION101_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION101_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 4 : Enable protection for region 100. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION100_Pos (4UL) /*!< Position of REGION100 field. */
+#define BPROT_CONFIG3_REGION100_Msk (0x1UL << BPROT_CONFIG3_REGION100_Pos) /*!< Bit mask of REGION100 field. */
+#define BPROT_CONFIG3_REGION100_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION100_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 3 : Enable protection for region 99. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION99_Pos (3UL) /*!< Position of REGION99 field. */
+#define BPROT_CONFIG3_REGION99_Msk (0x1UL << BPROT_CONFIG3_REGION99_Pos) /*!< Bit mask of REGION99 field. */
+#define BPROT_CONFIG3_REGION99_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION99_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 2 : Enable protection for region 98. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION98_Pos (2UL) /*!< Position of REGION98 field. */
+#define BPROT_CONFIG3_REGION98_Msk (0x1UL << BPROT_CONFIG3_REGION98_Pos) /*!< Bit mask of REGION98 field. */
+#define BPROT_CONFIG3_REGION98_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION98_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 1 : Enable protection for region 97. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION97_Pos (1UL) /*!< Position of REGION97 field. */
+#define BPROT_CONFIG3_REGION97_Msk (0x1UL << BPROT_CONFIG3_REGION97_Pos) /*!< Bit mask of REGION97 field. */
+#define BPROT_CONFIG3_REGION97_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION97_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 0 : Enable protection for region 96. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION96_Pos (0UL) /*!< Position of REGION96 field. */
+#define BPROT_CONFIG3_REGION96_Msk (0x1UL << BPROT_CONFIG3_REGION96_Pos) /*!< Bit mask of REGION96 field. */
+#define BPROT_CONFIG3_REGION96_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION96_Enabled (1UL) /*!< Protection enabled */
+
+
+/* Peripheral: CCM */
+/* Description: AES CCM Mode Encryption */
+
+/* Register: CCM_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: CCM_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 2 : Write '1' to Enable interrupt for ERROR event */
+#define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
+#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for ENDCRYPT event */
+#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
+#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
+#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
+#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
+#define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for ENDKSGEN event */
+#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
+#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
+#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
+#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
+#define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */
+
+/* Register: CCM_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 2 : Write '1' to Disable interrupt for ERROR event */
+#define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
+#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for ENDCRYPT event */
+#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
+#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
+#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
+#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
+#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for ENDKSGEN event */
+#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
+#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
+#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
+#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
+#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */
+
+/* Register: CCM_MICSTATUS */
+/* Description: MIC check result */
+
+/* Bit 0 : The result of the MIC check performed during the previous decryption operation */
+#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
+#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
+#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed */
+#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */
+
+/* Register: CCM_ENABLE */
+/* Description: Enable */
+
+/* Bits 1..0 : Enable or disable CCM */
+#define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
+
+/* Register: CCM_MODE */
+/* Description: Operation mode */
+
+/* Bit 24 : Packet length configuration */
+#define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */
+#define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */
+#define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field is 5-bit */
+#define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field is 8-bit */
+
+/* Bit 16 : Data rate that the CCM shall run in synch with */
+#define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */
+#define CCM_MODE_DATARATE_Msk (0x1UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */
+#define CCM_MODE_DATARATE_1Mbit (0UL) /*!< In synch with 1 Mbit data rate */
+#define CCM_MODE_DATARATE_2Mbit (1UL) /*!< In synch with 2 Mbit data rate */
+
+/* Bit 0 : The mode of operation to be used */
+#define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */
+#define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */
+
+/* Register: CCM_CNFPTR */
+/* Description: Pointer to data structure holding AES key and NONCE vector */
+
+/* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) */
+#define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */
+#define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */
+
+/* Register: CCM_INPTR */
+/* Description: Input pointer */
+
+/* Bits 31..0 : Input pointer */
+#define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */
+#define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */
+
+/* Register: CCM_OUTPTR */
+/* Description: Output pointer */
+
+/* Bits 31..0 : Output pointer */
+#define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */
+#define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */
+
+/* Register: CCM_SCRATCHPTR */
+/* Description: Pointer to data area used for temporary storage */
+
+/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption. */
+#define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
+#define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
+
+
+/* Peripheral: CLOCK */
+/* Description: Clock control */
+
+/* Register: CLOCK_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 4 : Write '1' to Enable interrupt for CTTO event */
+#define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
+#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
+#define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for DONE event */
+#define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */
+#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
+#define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for LFCLKSTARTED event */
+#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
+#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
+#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for HFCLKSTARTED event */
+#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
+#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
+#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */
+
+/* Register: CLOCK_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 4 : Write '1' to Disable interrupt for CTTO event */
+#define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
+#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
+#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for DONE event */
+#define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */
+#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
+#define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for LFCLKSTARTED event */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for HFCLKSTARTED event */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */
+
+/* Register: CLOCK_HFCLKRUN */
+/* Description: Status indicating that HFCLKSTART task has been triggered */
+
+/* Bit 0 : HFCLKSTART task triggered or not */
+#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
+#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
+#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
+
+/* Register: CLOCK_HFCLKSTAT */
+/* Description: HFCLK status */
+
+/* Bit 16 : HFCLK state */
+#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
+#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
+#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */
+#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */
+
+/* Bit 0 : Source of HFCLK */
+#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< 64 MHz internal oscillator (HFINT) */
+#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< 64 MHz crystal oscillator (HFXO) */
+
+/* Register: CLOCK_LFCLKRUN */
+/* Description: Status indicating that LFCLKSTART task has been triggered */
+
+/* Bit 0 : LFCLKSTART task triggered or not */
+#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
+#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
+#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
+
+/* Register: CLOCK_LFCLKSTAT */
+/* Description: LFCLK status */
+
+/* Bit 16 : LFCLK state */
+#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
+#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
+#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK not running */
+#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */
+
+/* Bits 1..0 : Source of LFCLK */
+#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
+#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
+#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
+
+/* Register: CLOCK_LFCLKSRCCOPY */
+/* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */
+
+/* Bits 1..0 : Clock source */
+#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
+#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
+#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
+
+/* Register: CLOCK_LFCLKSRC */
+/* Description: Clock source for the LFCLK */
+
+/* Bit 17 : Enable or disable external source for LFCLK */
+#define CLOCK_LFCLKSRC_EXTERNAL_Pos (17UL) /*!< Position of EXTERNAL field. */
+#define CLOCK_LFCLKSRC_EXTERNAL_Msk (0x1UL << CLOCK_LFCLKSRC_EXTERNAL_Pos) /*!< Bit mask of EXTERNAL field. */
+#define CLOCK_LFCLKSRC_EXTERNAL_Disabled (0UL) /*!< Disable external source (use with Xtal) */
+#define CLOCK_LFCLKSRC_EXTERNAL_Enabled (1UL) /*!< Enable use of external source instead of Xtal (SRC needs to be set to Xtal) */
+
+/* Bit 16 : Enable or disable bypass of LFCLK crystal oscillator with external clock source */
+#define CLOCK_LFCLKSRC_BYPASS_Pos (16UL) /*!< Position of BYPASS field. */
+#define CLOCK_LFCLKSRC_BYPASS_Msk (0x1UL << CLOCK_LFCLKSRC_BYPASS_Pos) /*!< Bit mask of BYPASS field. */
+#define CLOCK_LFCLKSRC_BYPASS_Disabled (0UL) /*!< Disable (use with Xtal or low-swing external source) */
+#define CLOCK_LFCLKSRC_BYPASS_Enabled (1UL) /*!< Enable (use with rail-to-rail external source) */
+
+/* Bits 1..0 : Clock source */
+#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
+#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
+#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
+
+/* Register: CLOCK_CTIV */
+/* Description: Calibration timer interval */
+
+/* Bits 6..0 : Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. */
+#define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */
+#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */
+
+/* Register: CLOCK_TRACECONFIG */
+/* Description: Clocking options for the Trace Port debug interface */
+
+/* Bits 17..16 : Pin multiplexing of trace signals. */
+#define CLOCK_TRACECONFIG_TRACEMUX_Pos (16UL) /*!< Position of TRACEMUX field. */
+#define CLOCK_TRACECONFIG_TRACEMUX_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEMUX_Pos) /*!< Bit mask of TRACEMUX field. */
+#define CLOCK_TRACECONFIG_TRACEMUX_GPIO (0UL) /*!< GPIOs multiplexed onto all trace-pins */
+#define CLOCK_TRACECONFIG_TRACEMUX_Serial (1UL) /*!< SWO multiplexed onto P0.18, GPIO multiplexed onto other trace pins */
+#define CLOCK_TRACECONFIG_TRACEMUX_Parallel (2UL) /*!< TRACECLK and TRACEDATA multiplexed onto P0.20, P0.18, P0.16, P0.15 and P0.14. */
+
+/* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two. */
+#define CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */
+#define CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */
+#define CLOCK_TRACECONFIG_TRACEPORTSPEED_32MHz (0UL) /*!< 32 MHz Trace Port clock (TRACECLK = 16 MHz) */
+#define CLOCK_TRACECONFIG_TRACEPORTSPEED_16MHz (1UL) /*!< 16 MHz Trace Port clock (TRACECLK = 8 MHz) */
+#define CLOCK_TRACECONFIG_TRACEPORTSPEED_8MHz (2UL) /*!< 8 MHz Trace Port clock (TRACECLK = 4 MHz) */
+#define CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz (3UL) /*!< 4 MHz Trace Port clock (TRACECLK = 2 MHz) */
+
+
+/* Peripheral: COMP */
+/* Description: Comparator */
+
+/* Register: COMP_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 4 : Shortcut between CROSS event and STOP task */
+#define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
+#define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
+#define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between UP event and STOP task */
+#define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
+#define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
+#define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between DOWN event and STOP task */
+#define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
+#define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
+#define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between READY event and STOP task */
+#define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
+#define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
+#define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between READY event and SAMPLE task */
+#define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
+#define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
+#define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
+#define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: COMP_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 3 : Enable or disable interrupt for CROSS event */
+#define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */
+#define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */
+#define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */
+#define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for UP event */
+#define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */
+#define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */
+#define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */
+#define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for DOWN event */
+#define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */
+#define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */
+#define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */
+#define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for READY event */
+#define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
+#define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */
+#define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */
+#define COMP_INTEN_READY_Enabled (1UL) /*!< Enable */
+
+/* Register: COMP_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 3 : Write '1' to Enable interrupt for CROSS event */
+#define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
+#define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
+#define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for UP event */
+#define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
+#define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
+#define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENSET_UP_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for DOWN event */
+#define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
+#define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
+#define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for READY event */
+#define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
+#define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENSET_READY_Set (1UL) /*!< Enable */
+
+/* Register: COMP_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 3 : Write '1' to Disable interrupt for CROSS event */
+#define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
+#define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
+#define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for UP event */
+#define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
+#define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
+#define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for DOWN event */
+#define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
+#define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
+#define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for READY event */
+#define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
+#define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
+
+/* Register: COMP_RESULT */
+/* Description: Compare result */
+
+/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
+#define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
+#define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
+#define COMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the threshold (VIN+ &lt; VIN-) */
+#define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the threshold (VIN+ &gt; VIN-) */
+
+/* Register: COMP_ENABLE */
+/* Description: COMP enable */
+
+/* Bits 1..0 : Enable or disable COMP */
+#define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define COMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define COMP_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
+
+/* Register: COMP_PSEL */
+/* Description: Pin select */
+
+/* Bits 2..0 : Analog pin select */
+#define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
+#define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
+#define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */
+#define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
+#define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
+#define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */
+#define COMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */
+#define COMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */
+#define COMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */
+#define COMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */
+
+/* Register: COMP_REFSEL */
+/* Description: Reference source select */
+
+/* Bits 2..0 : Reference select */
+#define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
+#define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
+#define COMP_REFSEL_REFSEL_Int1V2 (0UL) /*!< VREF = internal 1.2 V reference (VDD &gt;= 1.7 V) */
+#define COMP_REFSEL_REFSEL_Int1V8 (1UL) /*!< VREF = internal 1.8 V reference (VDD &gt;= VREF + 0.2 V) */
+#define COMP_REFSEL_REFSEL_Int2V4 (2UL) /*!< VREF = internal 2.4 V reference (VDD &gt;= VREF + 0.2 V) */
+#define COMP_REFSEL_REFSEL_VDD (4UL) /*!< VREF = VDD */
+#define COMP_REFSEL_REFSEL_ARef (7UL) /*!< VREF = AREF (VDD &gt;= VREF &gt;= AREFMIN) */
+
+/* Register: COMP_EXTREFSEL */
+/* Description: External reference select */
+
+/* Bit 0 : External analog reference select */
+#define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
+#define COMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
+#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */
+#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */
+
+/* Register: COMP_TH */
+/* Description: Threshold configuration for hysteresis unit */
+
+/* Bits 13..8 : VUP = (THUP+1)/64*VREF */
+#define COMP_TH_THUP_Pos (8UL) /*!< Position of THUP field. */
+#define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */
+
+/* Bits 5..0 : VDOWN = (THDOWN+1)/64*VREF */
+#define COMP_TH_THDOWN_Pos (0UL) /*!< Position of THDOWN field. */
+#define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */
+
+/* Register: COMP_MODE */
+/* Description: Mode configuration */
+
+/* Bit 8 : Main operation mode */
+#define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */
+#define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */
+#define COMP_MODE_MAIN_SE (0UL) /*!< Single ended mode */
+#define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode */
+
+/* Bits 1..0 : Speed and power mode */
+#define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */
+#define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */
+#define COMP_MODE_SP_Low (0UL) /*!< Low power mode */
+#define COMP_MODE_SP_Normal (1UL) /*!< Normal mode */
+#define COMP_MODE_SP_High (2UL) /*!< High speed mode */
+
+/* Register: COMP_HYST */
+/* Description: Comparator hysteresis enable */
+
+/* Bit 0 : Comparator hysteresis */
+#define COMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
+#define COMP_HYST_HYST_Msk (0x1UL << COMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
+#define COMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */
+#define COMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis enabled */
+
+/* Register: COMP_ISOURCE */
+/* Description: Current source select on analog input */
+
+/* Bits 1..0 : Comparator hysteresis */
+#define COMP_ISOURCE_ISOURCE_Pos (0UL) /*!< Position of ISOURCE field. */
+#define COMP_ISOURCE_ISOURCE_Msk (0x3UL << COMP_ISOURCE_ISOURCE_Pos) /*!< Bit mask of ISOURCE field. */
+#define COMP_ISOURCE_ISOURCE_Off (0UL) /*!< Current source disabled */
+#define COMP_ISOURCE_ISOURCE_Ien2mA5 (1UL) /*!< Current source enabled (+/- 2.5 uA) */
+#define COMP_ISOURCE_ISOURCE_Ien5mA (2UL) /*!< Current source enabled (+/- 5 uA) */
+#define COMP_ISOURCE_ISOURCE_Ien10mA (3UL) /*!< Current source enabled (+/- 10 uA) */
+
+
+/* Peripheral: ECB */
+/* Description: AES ECB Mode Encryption */
+
+/* Register: ECB_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 1 : Write '1' to Enable interrupt for ERRORECB event */
+#define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
+#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
+#define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
+#define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
+#define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for ENDECB event */
+#define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
+#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
+#define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */
+#define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */
+#define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */
+
+/* Register: ECB_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 1 : Write '1' to Disable interrupt for ERRORECB event */
+#define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
+#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
+#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
+#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
+#define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for ENDECB event */
+#define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
+#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
+#define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */
+#define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */
+#define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */
+
+/* Register: ECB_ECBDATAPTR */
+/* Description: ECB block encrypt memory pointers */
+
+/* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */
+#define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL) /*!< Position of ECBDATAPTR field. */
+#define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos) /*!< Bit mask of ECBDATAPTR field. */
+
+
+/* Peripheral: EGU */
+/* Description: Event Generator Unit 0 */
+
+/* Register: EGU_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 15 : Enable or disable interrupt for TRIGGERED[15] event */
+#define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
+#define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
+#define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */
+
+/* Bit 14 : Enable or disable interrupt for TRIGGERED[14] event */
+#define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
+#define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
+#define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */
+
+/* Bit 13 : Enable or disable interrupt for TRIGGERED[13] event */
+#define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
+#define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
+#define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */
+
+/* Bit 12 : Enable or disable interrupt for TRIGGERED[12] event */
+#define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
+#define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
+#define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */
+
+/* Bit 11 : Enable or disable interrupt for TRIGGERED[11] event */
+#define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
+#define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
+#define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */
+
+/* Bit 10 : Enable or disable interrupt for TRIGGERED[10] event */
+#define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
+#define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
+#define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for TRIGGERED[9] event */
+#define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
+#define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
+#define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */
+
+/* Bit 8 : Enable or disable interrupt for TRIGGERED[8] event */
+#define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
+#define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
+#define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable interrupt for TRIGGERED[7] event */
+#define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
+#define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
+#define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable interrupt for TRIGGERED[6] event */
+#define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
+#define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
+#define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable interrupt for TRIGGERED[5] event */
+#define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
+#define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
+#define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for TRIGGERED[4] event */
+#define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
+#define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
+#define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable interrupt for TRIGGERED[3] event */
+#define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
+#define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
+#define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for TRIGGERED[2] event */
+#define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
+#define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
+#define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for TRIGGERED[1] event */
+#define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
+#define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
+#define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for TRIGGERED[0] event */
+#define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
+#define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
+#define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */
+
+/* Register: EGU_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 15 : Write '1' to Enable interrupt for TRIGGERED[15] event */
+#define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
+#define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
+#define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */
+
+/* Bit 14 : Write '1' to Enable interrupt for TRIGGERED[14] event */
+#define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
+#define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
+#define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */
+
+/* Bit 13 : Write '1' to Enable interrupt for TRIGGERED[13] event */
+#define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
+#define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
+#define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */
+
+/* Bit 12 : Write '1' to Enable interrupt for TRIGGERED[12] event */
+#define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
+#define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
+#define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */
+
+/* Bit 11 : Write '1' to Enable interrupt for TRIGGERED[11] event */
+#define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
+#define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
+#define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */
+
+/* Bit 10 : Write '1' to Enable interrupt for TRIGGERED[10] event */
+#define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
+#define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
+#define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to Enable interrupt for TRIGGERED[9] event */
+#define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
+#define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
+#define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */
+
+/* Bit 8 : Write '1' to Enable interrupt for TRIGGERED[8] event */
+#define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
+#define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
+#define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for TRIGGERED[7] event */
+#define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
+#define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
+#define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for TRIGGERED[6] event */
+#define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
+#define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
+#define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable interrupt for TRIGGERED[5] event */
+#define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
+#define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
+#define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for TRIGGERED[4] event */
+#define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
+#define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
+#define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for TRIGGERED[3] event */
+#define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
+#define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
+#define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for TRIGGERED[2] event */
+#define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
+#define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
+#define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for TRIGGERED[1] event */
+#define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
+#define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
+#define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for TRIGGERED[0] event */
+#define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
+#define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
+#define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */
+
+/* Register: EGU_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 15 : Write '1' to Disable interrupt for TRIGGERED[15] event */
+#define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
+#define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
+#define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */
+
+/* Bit 14 : Write '1' to Disable interrupt for TRIGGERED[14] event */
+#define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
+#define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
+#define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */
+
+/* Bit 13 : Write '1' to Disable interrupt for TRIGGERED[13] event */
+#define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
+#define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
+#define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */
+
+/* Bit 12 : Write '1' to Disable interrupt for TRIGGERED[12] event */
+#define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
+#define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
+#define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */
+
+/* Bit 11 : Write '1' to Disable interrupt for TRIGGERED[11] event */
+#define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
+#define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
+#define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */
+
+/* Bit 10 : Write '1' to Disable interrupt for TRIGGERED[10] event */
+#define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
+#define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
+#define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to Disable interrupt for TRIGGERED[9] event */
+#define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
+#define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
+#define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */
+
+/* Bit 8 : Write '1' to Disable interrupt for TRIGGERED[8] event */
+#define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
+#define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
+#define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for TRIGGERED[7] event */
+#define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
+#define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
+#define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for TRIGGERED[6] event */
+#define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
+#define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
+#define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable interrupt for TRIGGERED[5] event */
+#define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
+#define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
+#define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for TRIGGERED[4] event */
+#define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
+#define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
+#define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for TRIGGERED[3] event */
+#define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
+#define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
+#define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for TRIGGERED[2] event */
+#define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
+#define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
+#define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for TRIGGERED[1] event */
+#define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
+#define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
+#define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for TRIGGERED[0] event */
+#define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
+#define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
+#define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */
+
+
+/* Peripheral: FICR */
+/* Description: Factory Information Configuration Registers */
+
+/* Register: FICR_CODEPAGESIZE */
+/* Description: Code memory page size */
+
+/* Bits 31..0 : Code memory page size */
+#define FICR_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */
+#define FICR_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */
+
+/* Register: FICR_CODESIZE */
+/* Description: Code memory size */
+
+/* Bits 31..0 : Code memory size in number of pages */
+#define FICR_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */
+#define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */
+
+/* Register: FICR_DEVICEID */
+/* Description: Description collection[0]:  Device identifier */
+
+/* Bits 31..0 : 64 bit unique device identifier */
+#define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */
+#define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */
+
+/* Register: FICR_ER */
+/* Description: Description collection[0]:  Encryption Root, word 0 */
+
+/* Bits 31..0 : Encryption Root, word n */
+#define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */
+#define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */
+
+/* Register: FICR_IR */
+/* Description: Description collection[0]:  Identity Root, word 0 */
+
+/* Bits 31..0 : Identity Root, word n */
+#define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */
+#define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos) /*!< Bit mask of IR field. */
+
+/* Register: FICR_DEVICEADDRTYPE */
+/* Description: Device address type */
+
+/* Bit 0 : Device address type */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */
+
+/* Register: FICR_DEVICEADDR */
+/* Description: Description collection[0]:  Device address 0 */
+
+/* Bits 31..0 : 48 bit device address */
+#define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */
+#define FICR_DEVICEADDR_DEVICEADDR_Msk (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos) /*!< Bit mask of DEVICEADDR field. */
+
+/* Register: FICR_INFO_PART */
+/* Description: Part code */
+
+/* Bits 31..0 : Part code */
+#define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */
+#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */
+#define FICR_INFO_PART_PART_N52832 (0x52832UL) /*!< nRF52832 */
+#define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
+
+/* Register: FICR_INFO_VARIANT */
+/* Description: Part Variant, Hardware version and Production configuration */
+
+/* Bits 31..0 : Part Variant, Hardware version and Production configuration, encoded as ASCII */
+#define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */
+#define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */
+#define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */
+#define FICR_INFO_VARIANT_VARIANT_AAAB (0x41414142UL) /*!< AAAB */
+#define FICR_INFO_VARIANT_VARIANT_AABA (0x41414241UL) /*!< AABA */
+#define FICR_INFO_VARIANT_VARIANT_AABB (0x41414242UL) /*!< AABB */
+#define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
+
+/* Register: FICR_INFO_PACKAGE */
+/* Description: Package option */
+
+/* Bits 31..0 : Package option */
+#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */
+#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */
+#define FICR_INFO_PACKAGE_PACKAGE_QF (0x2000UL) /*!< QFxx - 48-pin QFN */
+#define FICR_INFO_PACKAGE_PACKAGE_CH (0x2001UL) /*!< CHxx - 7x8 WLCSP 56 balls */
+#define FICR_INFO_PACKAGE_PACKAGE_CI (0x2002UL) /*!< CIxx - 7x8 WLCSP 56 balls */
+#define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
+
+/* Register: FICR_INFO_RAM */
+/* Description: RAM variant */
+
+/* Bits 31..0 : RAM variant */
+#define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */
+#define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */
+#define FICR_INFO_RAM_RAM_K16 (0x10UL) /*!< 16 kByte RAM */
+#define FICR_INFO_RAM_RAM_K32 (0x20UL) /*!< 32 kByte RAM */
+#define FICR_INFO_RAM_RAM_K64 (0x40UL) /*!< 64 kByte RAM */
+#define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
+
+/* Register: FICR_INFO_FLASH */
+/* Description: Flash variant */
+
+/* Bits 31..0 : Flash variant */
+#define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */
+#define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */
+#define FICR_INFO_FLASH_FLASH_K128 (0x80UL) /*!< 128 kByte FLASH */
+#define FICR_INFO_FLASH_FLASH_K256 (0x100UL) /*!< 256 kByte FLASH */
+#define FICR_INFO_FLASH_FLASH_K512 (0x200UL) /*!< 512 kByte FLASH */
+#define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
+
+/* Register: FICR_TEMP_A0 */
+/* Description: Slope definition A0. */
+
+/* Bits 11..0 : A (slope definition) register. */
+#define FICR_TEMP_A0_A_Pos (0UL) /*!< Position of A field. */
+#define FICR_TEMP_A0_A_Msk (0xFFFUL << FICR_TEMP_A0_A_Pos) /*!< Bit mask of A field. */
+
+/* Register: FICR_TEMP_A1 */
+/* Description: Slope definition A1. */
+
+/* Bits 11..0 : A (slope definition) register. */
+#define FICR_TEMP_A1_A_Pos (0UL) /*!< Position of A field. */
+#define FICR_TEMP_A1_A_Msk (0xFFFUL << FICR_TEMP_A1_A_Pos) /*!< Bit mask of A field. */
+
+/* Register: FICR_TEMP_A2 */
+/* Description: Slope definition A2. */
+
+/* Bits 11..0 : A (slope definition) register. */
+#define FICR_TEMP_A2_A_Pos (0UL) /*!< Position of A field. */
+#define FICR_TEMP_A2_A_Msk (0xFFFUL << FICR_TEMP_A2_A_Pos) /*!< Bit mask of A field. */
+
+/* Register: FICR_TEMP_A3 */
+/* Description: Slope definition A3. */
+
+/* Bits 11..0 : A (slope definition) register. */
+#define FICR_TEMP_A3_A_Pos (0UL) /*!< Position of A field. */
+#define FICR_TEMP_A3_A_Msk (0xFFFUL << FICR_TEMP_A3_A_Pos) /*!< Bit mask of A field. */
+
+/* Register: FICR_TEMP_A4 */
+/* Description: Slope definition A4. */
+
+/* Bits 11..0 : A (slope definition) register. */
+#define FICR_TEMP_A4_A_Pos (0UL) /*!< Position of A field. */
+#define FICR_TEMP_A4_A_Msk (0xFFFUL << FICR_TEMP_A4_A_Pos) /*!< Bit mask of A field. */
+
+/* Register: FICR_TEMP_A5 */
+/* Description: Slope definition A5. */
+
+/* Bits 11..0 : A (slope definition) register. */
+#define FICR_TEMP_A5_A_Pos (0UL) /*!< Position of A field. */
+#define FICR_TEMP_A5_A_Msk (0xFFFUL << FICR_TEMP_A5_A_Pos) /*!< Bit mask of A field. */
+
+/* Register: FICR_TEMP_B0 */
+/* Description: y-intercept B0. */
+
+/* Bits 13..0 : B (y-intercept) */
+#define FICR_TEMP_B0_B_Pos (0UL) /*!< Position of B field. */
+#define FICR_TEMP_B0_B_Msk (0x3FFFUL << FICR_TEMP_B0_B_Pos) /*!< Bit mask of B field. */
+
+/* Register: FICR_TEMP_B1 */
+/* Description: y-intercept B1. */
+
+/* Bits 13..0 : B (y-intercept) */
+#define FICR_TEMP_B1_B_Pos (0UL) /*!< Position of B field. */
+#define FICR_TEMP_B1_B_Msk (0x3FFFUL << FICR_TEMP_B1_B_Pos) /*!< Bit mask of B field. */
+
+/* Register: FICR_TEMP_B2 */
+/* Description: y-intercept B2. */
+
+/* Bits 13..0 : B (y-intercept) */
+#define FICR_TEMP_B2_B_Pos (0UL) /*!< Position of B field. */
+#define FICR_TEMP_B2_B_Msk (0x3FFFUL << FICR_TEMP_B2_B_Pos) /*!< Bit mask of B field. */
+
+/* Register: FICR_TEMP_B3 */
+/* Description: y-intercept B3. */
+
+/* Bits 13..0 : B (y-intercept) */
+#define FICR_TEMP_B3_B_Pos (0UL) /*!< Position of B field. */
+#define FICR_TEMP_B3_B_Msk (0x3FFFUL << FICR_TEMP_B3_B_Pos) /*!< Bit mask of B field. */
+
+/* Register: FICR_TEMP_B4 */
+/* Description: y-intercept B4. */
+
+/* Bits 13..0 : B (y-intercept) */
+#define FICR_TEMP_B4_B_Pos (0UL) /*!< Position of B field. */
+#define FICR_TEMP_B4_B_Msk (0x3FFFUL << FICR_TEMP_B4_B_Pos) /*!< Bit mask of B field. */
+
+/* Register: FICR_TEMP_B5 */
+/* Description: y-intercept B5. */
+
+/* Bits 13..0 : B (y-intercept) */
+#define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */
+#define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */
+
+/* Register: FICR_TEMP_T0 */
+/* Description: Segment end T0. */
+
+/* Bits 7..0 : T (segment end)register. */
+#define FICR_TEMP_T0_T_Pos (0UL) /*!< Position of T field. */
+#define FICR_TEMP_T0_T_Msk (0xFFUL << FICR_TEMP_T0_T_Pos) /*!< Bit mask of T field. */
+
+/* Register: FICR_TEMP_T1 */
+/* Description: Segment end T1. */
+
+/* Bits 7..0 : T (segment end)register. */
+#define FICR_TEMP_T1_T_Pos (0UL) /*!< Position of T field. */
+#define FICR_TEMP_T1_T_Msk (0xFFUL << FICR_TEMP_T1_T_Pos) /*!< Bit mask of T field. */
+
+/* Register: FICR_TEMP_T2 */
+/* Description: Segment end T2. */
+
+/* Bits 7..0 : T (segment end)register. */
+#define FICR_TEMP_T2_T_Pos (0UL) /*!< Position of T field. */
+#define FICR_TEMP_T2_T_Msk (0xFFUL << FICR_TEMP_T2_T_Pos) /*!< Bit mask of T field. */
+
+/* Register: FICR_TEMP_T3 */
+/* Description: Segment end T3. */
+
+/* Bits 7..0 : T (segment end)register. */
+#define FICR_TEMP_T3_T_Pos (0UL) /*!< Position of T field. */
+#define FICR_TEMP_T3_T_Msk (0xFFUL << FICR_TEMP_T3_T_Pos) /*!< Bit mask of T field. */
+
+/* Register: FICR_TEMP_T4 */
+/* Description: Segment end T4. */
+
+/* Bits 7..0 : T (segment end)register. */
+#define FICR_TEMP_T4_T_Pos (0UL) /*!< Position of T field. */
+#define FICR_TEMP_T4_T_Msk (0xFFUL << FICR_TEMP_T4_T_Pos) /*!< Bit mask of T field. */
+
+/* Register: FICR_NFC_TAGHEADER0 */
+/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
+
+/* Bits 31..24 : Unique identifier byte 3 */
+#define FICR_NFC_TAGHEADER0_UD3_Pos (24UL) /*!< Position of UD3 field. */
+#define FICR_NFC_TAGHEADER0_UD3_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD3_Pos) /*!< Bit mask of UD3 field. */
+
+/* Bits 23..16 : Unique identifier byte 2 */
+#define FICR_NFC_TAGHEADER0_UD2_Pos (16UL) /*!< Position of UD2 field. */
+#define FICR_NFC_TAGHEADER0_UD2_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD2_Pos) /*!< Bit mask of UD2 field. */
+
+/* Bits 15..8 : Unique identifier byte 1 */
+#define FICR_NFC_TAGHEADER0_UD1_Pos (8UL) /*!< Position of UD1 field. */
+#define FICR_NFC_TAGHEADER0_UD1_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD1_Pos) /*!< Bit mask of UD1 field. */
+
+/* Bits 7..0 : Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F */
+#define FICR_NFC_TAGHEADER0_MFGID_Pos (0UL) /*!< Position of MFGID field. */
+#define FICR_NFC_TAGHEADER0_MFGID_Msk (0xFFUL << FICR_NFC_TAGHEADER0_MFGID_Pos) /*!< Bit mask of MFGID field. */
+
+/* Register: FICR_NFC_TAGHEADER1 */
+/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
+
+/* Bits 31..24 : Unique identifier byte 7 */
+#define FICR_NFC_TAGHEADER1_UD7_Pos (24UL) /*!< Position of UD7 field. */
+#define FICR_NFC_TAGHEADER1_UD7_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD7_Pos) /*!< Bit mask of UD7 field. */
+
+/* Bits 23..16 : Unique identifier byte 6 */
+#define FICR_NFC_TAGHEADER1_UD6_Pos (16UL) /*!< Position of UD6 field. */
+#define FICR_NFC_TAGHEADER1_UD6_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD6_Pos) /*!< Bit mask of UD6 field. */
+
+/* Bits 15..8 : Unique identifier byte 5 */
+#define FICR_NFC_TAGHEADER1_UD5_Pos (8UL) /*!< Position of UD5 field. */
+#define FICR_NFC_TAGHEADER1_UD5_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD5_Pos) /*!< Bit mask of UD5 field. */
+
+/* Bits 7..0 : Unique identifier byte 4 */
+#define FICR_NFC_TAGHEADER1_UD4_Pos (0UL) /*!< Position of UD4 field. */
+#define FICR_NFC_TAGHEADER1_UD4_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD4_Pos) /*!< Bit mask of UD4 field. */
+
+/* Register: FICR_NFC_TAGHEADER2 */
+/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
+
+/* Bits 31..24 : Unique identifier byte 11 */
+#define FICR_NFC_TAGHEADER2_UD11_Pos (24UL) /*!< Position of UD11 field. */
+#define FICR_NFC_TAGHEADER2_UD11_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD11_Pos) /*!< Bit mask of UD11 field. */
+
+/* Bits 23..16 : Unique identifier byte 10 */
+#define FICR_NFC_TAGHEADER2_UD10_Pos (16UL) /*!< Position of UD10 field. */
+#define FICR_NFC_TAGHEADER2_UD10_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD10_Pos) /*!< Bit mask of UD10 field. */
+
+/* Bits 15..8 : Unique identifier byte 9 */
+#define FICR_NFC_TAGHEADER2_UD9_Pos (8UL) /*!< Position of UD9 field. */
+#define FICR_NFC_TAGHEADER2_UD9_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD9_Pos) /*!< Bit mask of UD9 field. */
+
+/* Bits 7..0 : Unique identifier byte 8 */
+#define FICR_NFC_TAGHEADER2_UD8_Pos (0UL) /*!< Position of UD8 field. */
+#define FICR_NFC_TAGHEADER2_UD8_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD8_Pos) /*!< Bit mask of UD8 field. */
+
+/* Register: FICR_NFC_TAGHEADER3 */
+/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
+
+/* Bits 31..24 : Unique identifier byte 15 */
+#define FICR_NFC_TAGHEADER3_UD15_Pos (24UL) /*!< Position of UD15 field. */
+#define FICR_NFC_TAGHEADER3_UD15_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD15_Pos) /*!< Bit mask of UD15 field. */
+
+/* Bits 23..16 : Unique identifier byte 14 */
+#define FICR_NFC_TAGHEADER3_UD14_Pos (16UL) /*!< Position of UD14 field. */
+#define FICR_NFC_TAGHEADER3_UD14_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD14_Pos) /*!< Bit mask of UD14 field. */
+
+/* Bits 15..8 : Unique identifier byte 13 */
+#define FICR_NFC_TAGHEADER3_UD13_Pos (8UL) /*!< Position of UD13 field. */
+#define FICR_NFC_TAGHEADER3_UD13_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD13_Pos) /*!< Bit mask of UD13 field. */
+
+/* Bits 7..0 : Unique identifier byte 12 */
+#define FICR_NFC_TAGHEADER3_UD12_Pos (0UL) /*!< Position of UD12 field. */
+#define FICR_NFC_TAGHEADER3_UD12_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD12_Pos) /*!< Bit mask of UD12 field. */
+
+
+/* Peripheral: GPIOTE */
+/* Description: GPIO Tasks and Events */
+
+/* Register: GPIOTE_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 31 : Write '1' to Enable interrupt for PORT event */
+#define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
+#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
+#define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for IN[7] event */
+#define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */
+#define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */
+#define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for IN[6] event */
+#define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */
+#define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */
+#define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable interrupt for IN[5] event */
+#define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */
+#define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */
+#define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for IN[4] event */
+#define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */
+#define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */
+#define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for IN[3] event */
+#define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
+#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
+#define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for IN[2] event */
+#define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
+#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
+#define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for IN[1] event */
+#define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
+#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
+#define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for IN[0] event */
+#define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
+#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
+#define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */
+
+/* Register: GPIOTE_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 31 : Write '1' to Disable interrupt for PORT event */
+#define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
+#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
+#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for IN[7] event */
+#define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */
+#define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */
+#define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for IN[6] event */
+#define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */
+#define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */
+#define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable interrupt for IN[5] event */
+#define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */
+#define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */
+#define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for IN[4] event */
+#define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */
+#define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */
+#define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for IN[3] event */
+#define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
+#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
+#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for IN[2] event */
+#define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
+#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
+#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for IN[1] event */
+#define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
+#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
+#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for IN[0] event */
+#define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
+#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
+#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */
+
+/* Register: GPIOTE_CONFIG */
+/* Description: Description collection[0]:  Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */
+
+/* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */
+#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
+#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
+#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */
+#define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */
+
+/* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */
+#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
+#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
+#define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */
+#define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */
+#define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */
+#define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */
+
+/* Bits 12..8 : GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event */
+#define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
+#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
+
+/* Bits 1..0 : Mode */
+#define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
+#define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */
+#define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */
+#define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */
+
+
+/* Peripheral: I2S */
+/* Description: Inter-IC Sound */
+
+/* Register: I2S_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 5 : Enable or disable interrupt for TXPTRUPD event */
+#define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
+#define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
+#define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */
+#define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for STOPPED event */
+#define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
+#define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for RXPTRUPD event */
+#define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
+#define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
+#define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */
+#define I2S_INTEN_RXPTRUPD_Enabled (1UL) /*!< Enable */
+
+/* Register: I2S_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 5 : Write '1' to Enable interrupt for TXPTRUPD event */
+#define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
+#define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
+#define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
+#define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
+#define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for STOPPED event */
+#define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
+#define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for RXPTRUPD event */
+#define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
+#define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
+#define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
+#define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
+#define I2S_INTENSET_RXPTRUPD_Set (1UL) /*!< Enable */
+
+/* Register: I2S_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 5 : Write '1' to Disable interrupt for TXPTRUPD event */
+#define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
+#define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
+#define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
+#define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
+#define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for STOPPED event */
+#define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
+#define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for RXPTRUPD event */
+#define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
+#define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
+#define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
+#define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
+#define I2S_INTENCLR_RXPTRUPD_Clear (1UL) /*!< Disable */
+
+/* Register: I2S_ENABLE */
+/* Description: Enable I2S module. */
+
+/* Bit 0 : Enable I2S module. */
+#define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define I2S_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define I2S_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
+
+/* Register: I2S_CONFIG_MODE */
+/* Description: I2S mode. */
+
+/* Bit 0 : I2S mode. */
+#define I2S_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define I2S_CONFIG_MODE_MODE_Master (0UL) /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. */
+#define I2S_CONFIG_MODE_MODE_Slave (1UL) /*!< Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx */
+
+/* Register: I2S_CONFIG_RXEN */
+/* Description: Reception (RX) enable. */
+
+/* Bit 0 : Reception (RX) enable. */
+#define I2S_CONFIG_RXEN_RXEN_Pos (0UL) /*!< Position of RXEN field. */
+#define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos) /*!< Bit mask of RXEN field. */
+#define I2S_CONFIG_RXEN_RXEN_Disabled (0UL) /*!< Reception disabled and now data will be written to the RXD.PTR address. */
+#define I2S_CONFIG_RXEN_RXEN_Enabled (1UL) /*!< Reception enabled. */
+
+/* Register: I2S_CONFIG_TXEN */
+/* Description: Transmission (TX) enable. */
+
+/* Bit 0 : Transmission (TX) enable. */
+#define I2S_CONFIG_TXEN_TXEN_Pos (0UL) /*!< Position of TXEN field. */
+#define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos) /*!< Bit mask of TXEN field. */
+#define I2S_CONFIG_TXEN_TXEN_Disabled (0UL) /*!< Transmission disabled and now data will be read from the RXD.TXD address. */
+#define I2S_CONFIG_TXEN_TXEN_Enabled (1UL) /*!< Transmission enabled. */
+
+/* Register: I2S_CONFIG_MCKEN */
+/* Description: Master clock generator enable. */
+
+/* Bit 0 : Master clock generator enable. */
+#define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL) /*!< Position of MCKEN field. */
+#define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos) /*!< Bit mask of MCKEN field. */
+#define I2S_CONFIG_MCKEN_MCKEN_Disabled (0UL) /*!< Master clock generator disabled and PSEL.MCK not connected(available as GPIO). */
+#define I2S_CONFIG_MCKEN_MCKEN_Enabled (1UL) /*!< Master clock generator running and MCK output on PSEL.MCK. */
+
+/* Register: I2S_CONFIG_MCKFREQ */
+/* Description: Master clock generator frequency. */
+
+/* Bits 31..0 : Master clock generator frequency. */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL) /*!< Position of MCKFREQ field. */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos) /*!< Bit mask of MCKFREQ field. */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL) /*!< 32 MHz / 125 = 0.256 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL) /*!< 32 MHz / 63 = 0.5079365 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL) /*!< 32 MHz / 42 = 0.7619048 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32 (0x08000000UL) /*!< 32 MHz / 32 = 1.0 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL) /*!< 32 MHz / 31 = 1.0322581 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL) /*!< 32 MHz / 30 = 1.0666667 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL) /*!< 32 MHz / 23 = 1.3913043 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL) /*!< 32 MHz / 16 = 2.0 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL) /*!< 32 MHz / 15 = 2.1333333 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6 (0x28000000UL) /*!< 32 MHz / 6 = 5.3333333 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5 (0x30000000UL) /*!< 32 MHz / 5 = 6.4 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4 (0x40000000UL) /*!< 32 MHz / 4 = 8.0 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3 (0x50000000UL) /*!< 32 MHz / 3 = 10.6666667 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2 (0x80000000UL) /*!< 32 MHz / 2 = 16.0 MHz */
+
+/* Register: I2S_CONFIG_RATIO */
+/* Description: MCK / LRCK ratio. */
+
+/* Bits 3..0 : MCK / LRCK ratio. */
+#define I2S_CONFIG_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */
+#define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */
+#define I2S_CONFIG_RATIO_RATIO_32X (0UL) /*!< LRCK = MCK / 32 */
+#define I2S_CONFIG_RATIO_RATIO_48X (1UL) /*!< LRCK = MCK / 48 */
+#define I2S_CONFIG_RATIO_RATIO_64X (2UL) /*!< LRCK = MCK / 64 */
+#define I2S_CONFIG_RATIO_RATIO_96X (3UL) /*!< LRCK = MCK / 96 */
+#define I2S_CONFIG_RATIO_RATIO_128X (4UL) /*!< LRCK = MCK / 128 */
+#define I2S_CONFIG_RATIO_RATIO_192X (5UL) /*!< LRCK = MCK / 192 */
+#define I2S_CONFIG_RATIO_RATIO_256X (6UL) /*!< LRCK = MCK / 256 */
+#define I2S_CONFIG_RATIO_RATIO_384X (7UL) /*!< LRCK = MCK / 384 */
+#define I2S_CONFIG_RATIO_RATIO_512X (8UL) /*!< LRCK = MCK / 512 */
+
+/* Register: I2S_CONFIG_SWIDTH */
+/* Description: Sample width. */
+
+/* Bits 1..0 : Sample width. */
+#define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL) /*!< Position of SWIDTH field. */
+#define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x3UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field. */
+#define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0UL) /*!< 8 bit. */
+#define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (1UL) /*!< 16 bit. */
+#define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (2UL) /*!< 24 bit. */
+
+/* Register: I2S_CONFIG_ALIGN */
+/* Description: Alignment of sample within a frame. */
+
+/* Bit 0 : Alignment of sample within a frame. */
+#define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL) /*!< Position of ALIGN field. */
+#define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field. */
+#define I2S_CONFIG_ALIGN_ALIGN_Left (0UL) /*!< Left-aligned. */
+#define I2S_CONFIG_ALIGN_ALIGN_Right (1UL) /*!< Right-aligned. */
+
+/* Register: I2S_CONFIG_FORMAT */
+/* Description: Frame format. */
+
+/* Bit 0 : Frame format. */
+#define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL) /*!< Position of FORMAT field. */
+#define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos) /*!< Bit mask of FORMAT field. */
+#define I2S_CONFIG_FORMAT_FORMAT_I2S (0UL) /*!< Original I2S format. */
+#define I2S_CONFIG_FORMAT_FORMAT_Aligned (1UL) /*!< Alternate (left- or right-aligned) format. */
+
+/* Register: I2S_CONFIG_CHANNELS */
+/* Description: Enable channels. */
+
+/* Bits 1..0 : Enable channels. */
+#define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL) /*!< Position of CHANNELS field. */
+#define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos) /*!< Bit mask of CHANNELS field. */
+#define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0UL) /*!< Stereo. */
+#define I2S_CONFIG_CHANNELS_CHANNELS_Left (1UL) /*!< Left only. */
+#define I2S_CONFIG_CHANNELS_CHANNELS_Right (2UL) /*!< Right only. */
+
+/* Register: I2S_RXD_PTR */
+/* Description: Receive buffer RAM start address. */
+
+/* Bits 31..0 : Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. */
+#define I2S_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: I2S_TXD_PTR */
+/* Description: Transmit buffer RAM start address. */
+
+/* Bits 31..0 : Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. */
+#define I2S_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: I2S_RXTXD_MAXCNT */
+/* Description: Size of RXD and TXD buffers. */
+
+/* Bits 13..0 : Size of RXD and TXD buffers in number of 32 bit words. */
+#define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: I2S_PSEL_MCK */
+/* Description: Pin select for MCK signal. */
+
+/* Bit 31 : Connection */
+#define I2S_PSEL_MCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define I2S_PSEL_MCK_CONNECT_Connected (0UL) /*!< Connect */
+#define I2S_PSEL_MCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define I2S_PSEL_MCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: I2S_PSEL_SCK */
+/* Description: Pin select for SCK signal. */
+
+/* Bit 31 : Connection */
+#define I2S_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define I2S_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
+#define I2S_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define I2S_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: I2S_PSEL_LRCK */
+/* Description: Pin select for LRCK signal. */
+
+/* Bit 31 : Connection */
+#define I2S_PSEL_LRCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define I2S_PSEL_LRCK_CONNECT_Connected (0UL) /*!< Connect */
+#define I2S_PSEL_LRCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define I2S_PSEL_LRCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: I2S_PSEL_SDIN */
+/* Description: Pin select for SDIN signal. */
+
+/* Bit 31 : Connection */
+#define I2S_PSEL_SDIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define I2S_PSEL_SDIN_CONNECT_Connected (0UL) /*!< Connect */
+#define I2S_PSEL_SDIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define I2S_PSEL_SDIN_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: I2S_PSEL_SDOUT */
+/* Description: Pin select for SDOUT signal. */
+
+/* Bit 31 : Connection */
+#define I2S_PSEL_SDOUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define I2S_PSEL_SDOUT_CONNECT_Connected (0UL) /*!< Connect */
+#define I2S_PSEL_SDOUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define I2S_PSEL_SDOUT_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos) /*!< Bit mask of PIN field. */
+
+
+/* Peripheral: LPCOMP */
+/* Description: Low Power Comparator */
+
+/* Register: LPCOMP_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 4 : Shortcut between CROSS event and STOP task */
+#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
+#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
+#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between UP event and STOP task */
+#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
+#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
+#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between DOWN event and STOP task */
+#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
+#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
+#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between READY event and STOP task */
+#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
+#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
+#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between READY event and SAMPLE task */
+#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
+#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
+#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
+#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: LPCOMP_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 3 : Write '1' to Enable interrupt for CROSS event */
+#define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
+#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
+#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for UP event */
+#define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
+#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
+#define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for DOWN event */
+#define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
+#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
+#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for READY event */
+#define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
+#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable */
+
+/* Register: LPCOMP_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 3 : Write '1' to Disable interrupt for CROSS event */
+#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
+#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
+#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for UP event */
+#define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
+#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
+#define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for DOWN event */
+#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
+#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
+#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for READY event */
+#define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
+#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
+
+/* Register: LPCOMP_RESULT */
+/* Description: Compare result */
+
+/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
+#define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
+#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
+#define LPCOMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the reference threshold (VIN+ &lt; VIN-). */
+#define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold (VIN+ &gt; VIN-). */
+
+/* Register: LPCOMP_ENABLE */
+/* Description: Enable LPCOMP */
+
+/* Bits 1..0 : Enable or disable LPCOMP */
+#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define LPCOMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define LPCOMP_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
+
+/* Register: LPCOMP_PSEL */
+/* Description: Input pin select */
+
+/* Bits 2..0 : Analog pin select */
+#define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
+#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
+#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */
+#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
+#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
+#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */
+#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */
+#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */
+#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */
+#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */
+
+/* Register: LPCOMP_REFSEL */
+/* Description: Reference select */
+
+/* Bits 3..0 : Reference select */
+#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
+#define LPCOMP_REFSEL_REFSEL_Msk (0xFUL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
+#define LPCOMP_REFSEL_REFSEL_Ref1_8Vdd (0UL) /*!< VDD * 1/8 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref2_8Vdd (1UL) /*!< VDD * 2/8 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref3_8Vdd (2UL) /*!< VDD * 3/8 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref4_8Vdd (3UL) /*!< VDD * 4/8 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref5_8Vdd (4UL) /*!< VDD * 5/8 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref6_8Vdd (5UL) /*!< VDD * 6/8 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref7_8Vdd (6UL) /*!< VDD * 7/8 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< External analog reference selected */
+#define LPCOMP_REFSEL_REFSEL_Ref1_16Vdd (8UL) /*!< VDD * 1/16 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref3_16Vdd (9UL) /*!< VDD * 3/16 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref5_16Vdd (10UL) /*!< VDD * 5/16 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref7_16Vdd (11UL) /*!< VDD * 7/16 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref9_16Vdd (12UL) /*!< VDD * 9/16 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref11_16Vdd (13UL) /*!< VDD * 11/16 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref13_16Vdd (14UL) /*!< VDD * 13/16 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref15_16Vdd (15UL) /*!< VDD * 15/16 selected as reference */
+
+/* Register: LPCOMP_EXTREFSEL */
+/* Description: External reference select */
+
+/* Bit 0 : External analog reference select */
+#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
+#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
+#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */
+#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */
+
+/* Register: LPCOMP_ANADETECT */
+/* Description: Analog detect configuration */
+
+/* Bits 1..0 : Analog detect configuration */
+#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */
+#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */
+#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETECT on crossing, both upward crossing and downward crossing */
+#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETECT on upward crossing only */
+#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETECT on downward crossing only */
+
+/* Register: LPCOMP_HYST */
+/* Description: Comparator hysteresis enable */
+
+/* Bit 0 : Comparator hysteresis enable */
+#define LPCOMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
+#define LPCOMP_HYST_HYST_Msk (0x1UL << LPCOMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
+#define LPCOMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */
+#define LPCOMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis disabled (typ. 50 mV) */
+
+
+/* Peripheral: MWU */
+/* Description: Memory Watch Unit */
+
+/* Register: MWU_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 27 : Enable or disable interrupt for PREGION[1].RA event */
+#define MWU_INTEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
+#define MWU_INTEN_PREGION1RA_Msk (0x1UL << MWU_INTEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
+#define MWU_INTEN_PREGION1RA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_PREGION1RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 26 : Enable or disable interrupt for PREGION[1].WA event */
+#define MWU_INTEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
+#define MWU_INTEN_PREGION1WA_Msk (0x1UL << MWU_INTEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
+#define MWU_INTEN_PREGION1WA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_PREGION1WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 25 : Enable or disable interrupt for PREGION[0].RA event */
+#define MWU_INTEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
+#define MWU_INTEN_PREGION0RA_Msk (0x1UL << MWU_INTEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
+#define MWU_INTEN_PREGION0RA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_PREGION0RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 24 : Enable or disable interrupt for PREGION[0].WA event */
+#define MWU_INTEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
+#define MWU_INTEN_PREGION0WA_Msk (0x1UL << MWU_INTEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
+#define MWU_INTEN_PREGION0WA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_PREGION0WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable interrupt for REGION[3].RA event */
+#define MWU_INTEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
+#define MWU_INTEN_REGION3RA_Msk (0x1UL << MWU_INTEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
+#define MWU_INTEN_REGION3RA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION3RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable interrupt for REGION[3].WA event */
+#define MWU_INTEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
+#define MWU_INTEN_REGION3WA_Msk (0x1UL << MWU_INTEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
+#define MWU_INTEN_REGION3WA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION3WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable interrupt for REGION[2].RA event */
+#define MWU_INTEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
+#define MWU_INTEN_REGION2RA_Msk (0x1UL << MWU_INTEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
+#define MWU_INTEN_REGION2RA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION2RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for REGION[2].WA event */
+#define MWU_INTEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
+#define MWU_INTEN_REGION2WA_Msk (0x1UL << MWU_INTEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
+#define MWU_INTEN_REGION2WA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION2WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable interrupt for REGION[1].RA event */
+#define MWU_INTEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
+#define MWU_INTEN_REGION1RA_Msk (0x1UL << MWU_INTEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
+#define MWU_INTEN_REGION1RA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION1RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for REGION[1].WA event */
+#define MWU_INTEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
+#define MWU_INTEN_REGION1WA_Msk (0x1UL << MWU_INTEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
+#define MWU_INTEN_REGION1WA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION1WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for REGION[0].RA event */
+#define MWU_INTEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
+#define MWU_INTEN_REGION0RA_Msk (0x1UL << MWU_INTEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
+#define MWU_INTEN_REGION0RA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION0RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for REGION[0].WA event */
+#define MWU_INTEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
+#define MWU_INTEN_REGION0WA_Msk (0x1UL << MWU_INTEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
+#define MWU_INTEN_REGION0WA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION0WA_Enabled (1UL) /*!< Enable */
+
+/* Register: MWU_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 27 : Write '1' to Enable interrupt for PREGION[1].RA event */
+#define MWU_INTENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
+#define MWU_INTENSET_PREGION1RA_Msk (0x1UL << MWU_INTENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
+#define MWU_INTENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_PREGION1RA_Set (1UL) /*!< Enable */
+
+/* Bit 26 : Write '1' to Enable interrupt for PREGION[1].WA event */
+#define MWU_INTENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
+#define MWU_INTENSET_PREGION1WA_Msk (0x1UL << MWU_INTENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
+#define MWU_INTENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_PREGION1WA_Set (1UL) /*!< Enable */
+
+/* Bit 25 : Write '1' to Enable interrupt for PREGION[0].RA event */
+#define MWU_INTENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
+#define MWU_INTENSET_PREGION0RA_Msk (0x1UL << MWU_INTENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
+#define MWU_INTENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_PREGION0RA_Set (1UL) /*!< Enable */
+
+/* Bit 24 : Write '1' to Enable interrupt for PREGION[0].WA event */
+#define MWU_INTENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
+#define MWU_INTENSET_PREGION0WA_Msk (0x1UL << MWU_INTENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
+#define MWU_INTENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_PREGION0WA_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for REGION[3].RA event */
+#define MWU_INTENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
+#define MWU_INTENSET_REGION3RA_Msk (0x1UL << MWU_INTENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
+#define MWU_INTENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION3RA_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for REGION[3].WA event */
+#define MWU_INTENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
+#define MWU_INTENSET_REGION3WA_Msk (0x1UL << MWU_INTENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
+#define MWU_INTENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION3WA_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable interrupt for REGION[2].RA event */
+#define MWU_INTENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
+#define MWU_INTENSET_REGION2RA_Msk (0x1UL << MWU_INTENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
+#define MWU_INTENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION2RA_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for REGION[2].WA event */
+#define MWU_INTENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
+#define MWU_INTENSET_REGION2WA_Msk (0x1UL << MWU_INTENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
+#define MWU_INTENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION2WA_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for REGION[1].RA event */
+#define MWU_INTENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
+#define MWU_INTENSET_REGION1RA_Msk (0x1UL << MWU_INTENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
+#define MWU_INTENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION1RA_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for REGION[1].WA event */
+#define MWU_INTENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
+#define MWU_INTENSET_REGION1WA_Msk (0x1UL << MWU_INTENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
+#define MWU_INTENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION1WA_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for REGION[0].RA event */
+#define MWU_INTENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
+#define MWU_INTENSET_REGION0RA_Msk (0x1UL << MWU_INTENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
+#define MWU_INTENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION0RA_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for REGION[0].WA event */
+#define MWU_INTENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
+#define MWU_INTENSET_REGION0WA_Msk (0x1UL << MWU_INTENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
+#define MWU_INTENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION0WA_Set (1UL) /*!< Enable */
+
+/* Register: MWU_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 27 : Write '1' to Disable interrupt for PREGION[1].RA event */
+#define MWU_INTENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
+#define MWU_INTENCLR_PREGION1RA_Msk (0x1UL << MWU_INTENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
+#define MWU_INTENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
+
+/* Bit 26 : Write '1' to Disable interrupt for PREGION[1].WA event */
+#define MWU_INTENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
+#define MWU_INTENCLR_PREGION1WA_Msk (0x1UL << MWU_INTENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
+#define MWU_INTENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
+
+/* Bit 25 : Write '1' to Disable interrupt for PREGION[0].RA event */
+#define MWU_INTENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
+#define MWU_INTENCLR_PREGION0RA_Msk (0x1UL << MWU_INTENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
+#define MWU_INTENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
+
+/* Bit 24 : Write '1' to Disable interrupt for PREGION[0].WA event */
+#define MWU_INTENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
+#define MWU_INTENCLR_PREGION0WA_Msk (0x1UL << MWU_INTENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
+#define MWU_INTENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for REGION[3].RA event */
+#define MWU_INTENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
+#define MWU_INTENCLR_REGION3RA_Msk (0x1UL << MWU_INTENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
+#define MWU_INTENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION3RA_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for REGION[3].WA event */
+#define MWU_INTENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
+#define MWU_INTENCLR_REGION3WA_Msk (0x1UL << MWU_INTENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
+#define MWU_INTENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION3WA_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable interrupt for REGION[2].RA event */
+#define MWU_INTENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
+#define MWU_INTENCLR_REGION2RA_Msk (0x1UL << MWU_INTENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
+#define MWU_INTENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION2RA_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for REGION[2].WA event */
+#define MWU_INTENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
+#define MWU_INTENCLR_REGION2WA_Msk (0x1UL << MWU_INTENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
+#define MWU_INTENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION2WA_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for REGION[1].RA event */
+#define MWU_INTENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
+#define MWU_INTENCLR_REGION1RA_Msk (0x1UL << MWU_INTENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
+#define MWU_INTENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION1RA_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for REGION[1].WA event */
+#define MWU_INTENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
+#define MWU_INTENCLR_REGION1WA_Msk (0x1UL << MWU_INTENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
+#define MWU_INTENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION1WA_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for REGION[0].RA event */
+#define MWU_INTENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
+#define MWU_INTENCLR_REGION0RA_Msk (0x1UL << MWU_INTENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
+#define MWU_INTENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION0RA_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for REGION[0].WA event */
+#define MWU_INTENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
+#define MWU_INTENCLR_REGION0WA_Msk (0x1UL << MWU_INTENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
+#define MWU_INTENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION0WA_Clear (1UL) /*!< Disable */
+
+/* Register: MWU_NMIEN */
+/* Description: Enable or disable non-maskable interrupt */
+
+/* Bit 27 : Enable or disable non-maskable interrupt for PREGION[1].RA event */
+#define MWU_NMIEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
+#define MWU_NMIEN_PREGION1RA_Msk (0x1UL << MWU_NMIEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
+#define MWU_NMIEN_PREGION1RA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_PREGION1RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 26 : Enable or disable non-maskable interrupt for PREGION[1].WA event */
+#define MWU_NMIEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
+#define MWU_NMIEN_PREGION1WA_Msk (0x1UL << MWU_NMIEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
+#define MWU_NMIEN_PREGION1WA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_PREGION1WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 25 : Enable or disable non-maskable interrupt for PREGION[0].RA event */
+#define MWU_NMIEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
+#define MWU_NMIEN_PREGION0RA_Msk (0x1UL << MWU_NMIEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
+#define MWU_NMIEN_PREGION0RA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_PREGION0RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 24 : Enable or disable non-maskable interrupt for PREGION[0].WA event */
+#define MWU_NMIEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
+#define MWU_NMIEN_PREGION0WA_Msk (0x1UL << MWU_NMIEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
+#define MWU_NMIEN_PREGION0WA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_PREGION0WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable non-maskable interrupt for REGION[3].RA event */
+#define MWU_NMIEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
+#define MWU_NMIEN_REGION3RA_Msk (0x1UL << MWU_NMIEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
+#define MWU_NMIEN_REGION3RA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION3RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable non-maskable interrupt for REGION[3].WA event */
+#define MWU_NMIEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
+#define MWU_NMIEN_REGION3WA_Msk (0x1UL << MWU_NMIEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
+#define MWU_NMIEN_REGION3WA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION3WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable non-maskable interrupt for REGION[2].RA event */
+#define MWU_NMIEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
+#define MWU_NMIEN_REGION2RA_Msk (0x1UL << MWU_NMIEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
+#define MWU_NMIEN_REGION2RA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION2RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable non-maskable interrupt for REGION[2].WA event */
+#define MWU_NMIEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
+#define MWU_NMIEN_REGION2WA_Msk (0x1UL << MWU_NMIEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
+#define MWU_NMIEN_REGION2WA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION2WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable non-maskable interrupt for REGION[1].RA event */
+#define MWU_NMIEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
+#define MWU_NMIEN_REGION1RA_Msk (0x1UL << MWU_NMIEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
+#define MWU_NMIEN_REGION1RA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION1RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable non-maskable interrupt for REGION[1].WA event */
+#define MWU_NMIEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
+#define MWU_NMIEN_REGION1WA_Msk (0x1UL << MWU_NMIEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
+#define MWU_NMIEN_REGION1WA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION1WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable non-maskable interrupt for REGION[0].RA event */
+#define MWU_NMIEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
+#define MWU_NMIEN_REGION0RA_Msk (0x1UL << MWU_NMIEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
+#define MWU_NMIEN_REGION0RA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION0RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable non-maskable interrupt for REGION[0].WA event */
+#define MWU_NMIEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
+#define MWU_NMIEN_REGION0WA_Msk (0x1UL << MWU_NMIEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
+#define MWU_NMIEN_REGION0WA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION0WA_Enabled (1UL) /*!< Enable */
+
+/* Register: MWU_NMIENSET */
+/* Description: Enable non-maskable interrupt */
+
+/* Bit 27 : Write '1' to Enable non-maskable interrupt for PREGION[1].RA event */
+#define MWU_NMIENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
+#define MWU_NMIENSET_PREGION1RA_Msk (0x1UL << MWU_NMIENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
+#define MWU_NMIENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_PREGION1RA_Set (1UL) /*!< Enable */
+
+/* Bit 26 : Write '1' to Enable non-maskable interrupt for PREGION[1].WA event */
+#define MWU_NMIENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
+#define MWU_NMIENSET_PREGION1WA_Msk (0x1UL << MWU_NMIENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
+#define MWU_NMIENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_PREGION1WA_Set (1UL) /*!< Enable */
+
+/* Bit 25 : Write '1' to Enable non-maskable interrupt for PREGION[0].RA event */
+#define MWU_NMIENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
+#define MWU_NMIENSET_PREGION0RA_Msk (0x1UL << MWU_NMIENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
+#define MWU_NMIENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_PREGION0RA_Set (1UL) /*!< Enable */
+
+/* Bit 24 : Write '1' to Enable non-maskable interrupt for PREGION[0].WA event */
+#define MWU_NMIENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
+#define MWU_NMIENSET_PREGION0WA_Msk (0x1UL << MWU_NMIENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
+#define MWU_NMIENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_PREGION0WA_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable non-maskable interrupt for REGION[3].RA event */
+#define MWU_NMIENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
+#define MWU_NMIENSET_REGION3RA_Msk (0x1UL << MWU_NMIENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
+#define MWU_NMIENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION3RA_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable non-maskable interrupt for REGION[3].WA event */
+#define MWU_NMIENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
+#define MWU_NMIENSET_REGION3WA_Msk (0x1UL << MWU_NMIENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
+#define MWU_NMIENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION3WA_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable non-maskable interrupt for REGION[2].RA event */
+#define MWU_NMIENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
+#define MWU_NMIENSET_REGION2RA_Msk (0x1UL << MWU_NMIENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
+#define MWU_NMIENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION2RA_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable non-maskable interrupt for REGION[2].WA event */
+#define MWU_NMIENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
+#define MWU_NMIENSET_REGION2WA_Msk (0x1UL << MWU_NMIENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
+#define MWU_NMIENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION2WA_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable non-maskable interrupt for REGION[1].RA event */
+#define MWU_NMIENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
+#define MWU_NMIENSET_REGION1RA_Msk (0x1UL << MWU_NMIENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
+#define MWU_NMIENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION1RA_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable non-maskable interrupt for REGION[1].WA event */
+#define MWU_NMIENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
+#define MWU_NMIENSET_REGION1WA_Msk (0x1UL << MWU_NMIENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
+#define MWU_NMIENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION1WA_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable non-maskable interrupt for REGION[0].RA event */
+#define MWU_NMIENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
+#define MWU_NMIENSET_REGION0RA_Msk (0x1UL << MWU_NMIENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
+#define MWU_NMIENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION0RA_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable non-maskable interrupt for REGION[0].WA event */
+#define MWU_NMIENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
+#define MWU_NMIENSET_REGION0WA_Msk (0x1UL << MWU_NMIENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
+#define MWU_NMIENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION0WA_Set (1UL) /*!< Enable */
+
+/* Register: MWU_NMIENCLR */
+/* Description: Disable non-maskable interrupt */
+
+/* Bit 27 : Write '1' to Disable non-maskable interrupt for PREGION[1].RA event */
+#define MWU_NMIENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
+#define MWU_NMIENCLR_PREGION1RA_Msk (0x1UL << MWU_NMIENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
+#define MWU_NMIENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
+
+/* Bit 26 : Write '1' to Disable non-maskable interrupt for PREGION[1].WA event */
+#define MWU_NMIENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
+#define MWU_NMIENCLR_PREGION1WA_Msk (0x1UL << MWU_NMIENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
+#define MWU_NMIENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
+
+/* Bit 25 : Write '1' to Disable non-maskable interrupt for PREGION[0].RA event */
+#define MWU_NMIENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
+#define MWU_NMIENCLR_PREGION0RA_Msk (0x1UL << MWU_NMIENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
+#define MWU_NMIENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
+
+/* Bit 24 : Write '1' to Disable non-maskable interrupt for PREGION[0].WA event */
+#define MWU_NMIENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
+#define MWU_NMIENCLR_PREGION0WA_Msk (0x1UL << MWU_NMIENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
+#define MWU_NMIENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable non-maskable interrupt for REGION[3].RA event */
+#define MWU_NMIENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
+#define MWU_NMIENCLR_REGION3RA_Msk (0x1UL << MWU_NMIENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
+#define MWU_NMIENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION3RA_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable non-maskable interrupt for REGION[3].WA event */
+#define MWU_NMIENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
+#define MWU_NMIENCLR_REGION3WA_Msk (0x1UL << MWU_NMIENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
+#define MWU_NMIENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION3WA_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable non-maskable interrupt for REGION[2].RA event */
+#define MWU_NMIENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
+#define MWU_NMIENCLR_REGION2RA_Msk (0x1UL << MWU_NMIENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
+#define MWU_NMIENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION2RA_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable non-maskable interrupt for REGION[2].WA event */
+#define MWU_NMIENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
+#define MWU_NMIENCLR_REGION2WA_Msk (0x1UL << MWU_NMIENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
+#define MWU_NMIENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION2WA_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable non-maskable interrupt for REGION[1].RA event */
+#define MWU_NMIENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
+#define MWU_NMIENCLR_REGION1RA_Msk (0x1UL << MWU_NMIENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
+#define MWU_NMIENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION1RA_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable non-maskable interrupt for REGION[1].WA event */
+#define MWU_NMIENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
+#define MWU_NMIENCLR_REGION1WA_Msk (0x1UL << MWU_NMIENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
+#define MWU_NMIENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION1WA_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable non-maskable interrupt for REGION[0].RA event */
+#define MWU_NMIENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
+#define MWU_NMIENCLR_REGION0RA_Msk (0x1UL << MWU_NMIENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
+#define MWU_NMIENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION0RA_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable non-maskable interrupt for REGION[0].WA event */
+#define MWU_NMIENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
+#define MWU_NMIENCLR_REGION0WA_Msk (0x1UL << MWU_NMIENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
+#define MWU_NMIENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION0WA_Clear (1UL) /*!< Disable */
+
+/* Register: MWU_PERREGION_SUBSTATWA */
+/* Description: Description cluster[0]:  Source of event/interrupt in region 0, write access detected while corresponding subregion was enabled for watching */
+
+/* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR31_Pos (31UL) /*!< Position of SR31 field. */
+#define MWU_PERREGION_SUBSTATWA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR31_Pos) /*!< Bit mask of SR31 field. */
+#define MWU_PERREGION_SUBSTATWA_SR31_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR31_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR30_Pos (30UL) /*!< Position of SR30 field. */
+#define MWU_PERREGION_SUBSTATWA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR30_Pos) /*!< Bit mask of SR30 field. */
+#define MWU_PERREGION_SUBSTATWA_SR30_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR30_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR29_Pos (29UL) /*!< Position of SR29 field. */
+#define MWU_PERREGION_SUBSTATWA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR29_Pos) /*!< Bit mask of SR29 field. */
+#define MWU_PERREGION_SUBSTATWA_SR29_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR29_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR28_Pos (28UL) /*!< Position of SR28 field. */
+#define MWU_PERREGION_SUBSTATWA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR28_Pos) /*!< Bit mask of SR28 field. */
+#define MWU_PERREGION_SUBSTATWA_SR28_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR28_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR27_Pos (27UL) /*!< Position of SR27 field. */
+#define MWU_PERREGION_SUBSTATWA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR27_Pos) /*!< Bit mask of SR27 field. */
+#define MWU_PERREGION_SUBSTATWA_SR27_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR27_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR26_Pos (26UL) /*!< Position of SR26 field. */
+#define MWU_PERREGION_SUBSTATWA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR26_Pos) /*!< Bit mask of SR26 field. */
+#define MWU_PERREGION_SUBSTATWA_SR26_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR26_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR25_Pos (25UL) /*!< Position of SR25 field. */
+#define MWU_PERREGION_SUBSTATWA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR25_Pos) /*!< Bit mask of SR25 field. */
+#define MWU_PERREGION_SUBSTATWA_SR25_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR25_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR24_Pos (24UL) /*!< Position of SR24 field. */
+#define MWU_PERREGION_SUBSTATWA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR24_Pos) /*!< Bit mask of SR24 field. */
+#define MWU_PERREGION_SUBSTATWA_SR24_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR24_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR23_Pos (23UL) /*!< Position of SR23 field. */
+#define MWU_PERREGION_SUBSTATWA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR23_Pos) /*!< Bit mask of SR23 field. */
+#define MWU_PERREGION_SUBSTATWA_SR23_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR23_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR22_Pos (22UL) /*!< Position of SR22 field. */
+#define MWU_PERREGION_SUBSTATWA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR22_Pos) /*!< Bit mask of SR22 field. */
+#define MWU_PERREGION_SUBSTATWA_SR22_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR22_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR21_Pos (21UL) /*!< Position of SR21 field. */
+#define MWU_PERREGION_SUBSTATWA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR21_Pos) /*!< Bit mask of SR21 field. */
+#define MWU_PERREGION_SUBSTATWA_SR21_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR21_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR20_Pos (20UL) /*!< Position of SR20 field. */
+#define MWU_PERREGION_SUBSTATWA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR20_Pos) /*!< Bit mask of SR20 field. */
+#define MWU_PERREGION_SUBSTATWA_SR20_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR20_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR19_Pos (19UL) /*!< Position of SR19 field. */
+#define MWU_PERREGION_SUBSTATWA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR19_Pos) /*!< Bit mask of SR19 field. */
+#define MWU_PERREGION_SUBSTATWA_SR19_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR19_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR18_Pos (18UL) /*!< Position of SR18 field. */
+#define MWU_PERREGION_SUBSTATWA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR18_Pos) /*!< Bit mask of SR18 field. */
+#define MWU_PERREGION_SUBSTATWA_SR18_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR18_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR17_Pos (17UL) /*!< Position of SR17 field. */
+#define MWU_PERREGION_SUBSTATWA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR17_Pos) /*!< Bit mask of SR17 field. */
+#define MWU_PERREGION_SUBSTATWA_SR17_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR17_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR16_Pos (16UL) /*!< Position of SR16 field. */
+#define MWU_PERREGION_SUBSTATWA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR16_Pos) /*!< Bit mask of SR16 field. */
+#define MWU_PERREGION_SUBSTATWA_SR16_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR16_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR15_Pos (15UL) /*!< Position of SR15 field. */
+#define MWU_PERREGION_SUBSTATWA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR15_Pos) /*!< Bit mask of SR15 field. */
+#define MWU_PERREGION_SUBSTATWA_SR15_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR15_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR14_Pos (14UL) /*!< Position of SR14 field. */
+#define MWU_PERREGION_SUBSTATWA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR14_Pos) /*!< Bit mask of SR14 field. */
+#define MWU_PERREGION_SUBSTATWA_SR14_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR14_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR13_Pos (13UL) /*!< Position of SR13 field. */
+#define MWU_PERREGION_SUBSTATWA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR13_Pos) /*!< Bit mask of SR13 field. */
+#define MWU_PERREGION_SUBSTATWA_SR13_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR13_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR12_Pos (12UL) /*!< Position of SR12 field. */
+#define MWU_PERREGION_SUBSTATWA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR12_Pos) /*!< Bit mask of SR12 field. */
+#define MWU_PERREGION_SUBSTATWA_SR12_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR12_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR11_Pos (11UL) /*!< Position of SR11 field. */
+#define MWU_PERREGION_SUBSTATWA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR11_Pos) /*!< Bit mask of SR11 field. */
+#define MWU_PERREGION_SUBSTATWA_SR11_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR11_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR10_Pos (10UL) /*!< Position of SR10 field. */
+#define MWU_PERREGION_SUBSTATWA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR10_Pos) /*!< Bit mask of SR10 field. */
+#define MWU_PERREGION_SUBSTATWA_SR10_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR10_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR9_Pos (9UL) /*!< Position of SR9 field. */
+#define MWU_PERREGION_SUBSTATWA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR9_Pos) /*!< Bit mask of SR9 field. */
+#define MWU_PERREGION_SUBSTATWA_SR9_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR9_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR8_Pos (8UL) /*!< Position of SR8 field. */
+#define MWU_PERREGION_SUBSTATWA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR8_Pos) /*!< Bit mask of SR8 field. */
+#define MWU_PERREGION_SUBSTATWA_SR8_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR8_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR7_Pos (7UL) /*!< Position of SR7 field. */
+#define MWU_PERREGION_SUBSTATWA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR7_Pos) /*!< Bit mask of SR7 field. */
+#define MWU_PERREGION_SUBSTATWA_SR7_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR7_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR6_Pos (6UL) /*!< Position of SR6 field. */
+#define MWU_PERREGION_SUBSTATWA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR6_Pos) /*!< Bit mask of SR6 field. */
+#define MWU_PERREGION_SUBSTATWA_SR6_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR6_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR5_Pos (5UL) /*!< Position of SR5 field. */
+#define MWU_PERREGION_SUBSTATWA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR5_Pos) /*!< Bit mask of SR5 field. */
+#define MWU_PERREGION_SUBSTATWA_SR5_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR5_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR4_Pos (4UL) /*!< Position of SR4 field. */
+#define MWU_PERREGION_SUBSTATWA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR4_Pos) /*!< Bit mask of SR4 field. */
+#define MWU_PERREGION_SUBSTATWA_SR4_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR4_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR3_Pos (3UL) /*!< Position of SR3 field. */
+#define MWU_PERREGION_SUBSTATWA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR3_Pos) /*!< Bit mask of SR3 field. */
+#define MWU_PERREGION_SUBSTATWA_SR3_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR3_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR2_Pos (2UL) /*!< Position of SR2 field. */
+#define MWU_PERREGION_SUBSTATWA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR2_Pos) /*!< Bit mask of SR2 field. */
+#define MWU_PERREGION_SUBSTATWA_SR2_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR2_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR1_Pos (1UL) /*!< Position of SR1 field. */
+#define MWU_PERREGION_SUBSTATWA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR1_Pos) /*!< Bit mask of SR1 field. */
+#define MWU_PERREGION_SUBSTATWA_SR1_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR1_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR0_Pos (0UL) /*!< Position of SR0 field. */
+#define MWU_PERREGION_SUBSTATWA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR0_Pos) /*!< Bit mask of SR0 field. */
+#define MWU_PERREGION_SUBSTATWA_SR0_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR0_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Register: MWU_PERREGION_SUBSTATRA */
+/* Description: Description cluster[0]:  Source of event/interrupt in region 0, read access detected while corresponding subregion was enabled for watching */
+
+/* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR31_Pos (31UL) /*!< Position of SR31 field. */
+#define MWU_PERREGION_SUBSTATRA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR31_Pos) /*!< Bit mask of SR31 field. */
+#define MWU_PERREGION_SUBSTATRA_SR31_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR31_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR30_Pos (30UL) /*!< Position of SR30 field. */
+#define MWU_PERREGION_SUBSTATRA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR30_Pos) /*!< Bit mask of SR30 field. */
+#define MWU_PERREGION_SUBSTATRA_SR30_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR30_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR29_Pos (29UL) /*!< Position of SR29 field. */
+#define MWU_PERREGION_SUBSTATRA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR29_Pos) /*!< Bit mask of SR29 field. */
+#define MWU_PERREGION_SUBSTATRA_SR29_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR29_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR28_Pos (28UL) /*!< Position of SR28 field. */
+#define MWU_PERREGION_SUBSTATRA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR28_Pos) /*!< Bit mask of SR28 field. */
+#define MWU_PERREGION_SUBSTATRA_SR28_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR28_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR27_Pos (27UL) /*!< Position of SR27 field. */
+#define MWU_PERREGION_SUBSTATRA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR27_Pos) /*!< Bit mask of SR27 field. */
+#define MWU_PERREGION_SUBSTATRA_SR27_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR27_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR26_Pos (26UL) /*!< Position of SR26 field. */
+#define MWU_PERREGION_SUBSTATRA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR26_Pos) /*!< Bit mask of SR26 field. */
+#define MWU_PERREGION_SUBSTATRA_SR26_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR26_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR25_Pos (25UL) /*!< Position of SR25 field. */
+#define MWU_PERREGION_SUBSTATRA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR25_Pos) /*!< Bit mask of SR25 field. */
+#define MWU_PERREGION_SUBSTATRA_SR25_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR25_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR24_Pos (24UL) /*!< Position of SR24 field. */
+#define MWU_PERREGION_SUBSTATRA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR24_Pos) /*!< Bit mask of SR24 field. */
+#define MWU_PERREGION_SUBSTATRA_SR24_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR24_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR23_Pos (23UL) /*!< Position of SR23 field. */
+#define MWU_PERREGION_SUBSTATRA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR23_Pos) /*!< Bit mask of SR23 field. */
+#define MWU_PERREGION_SUBSTATRA_SR23_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR23_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR22_Pos (22UL) /*!< Position of SR22 field. */
+#define MWU_PERREGION_SUBSTATRA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR22_Pos) /*!< Bit mask of SR22 field. */
+#define MWU_PERREGION_SUBSTATRA_SR22_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR22_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR21_Pos (21UL) /*!< Position of SR21 field. */
+#define MWU_PERREGION_SUBSTATRA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR21_Pos) /*!< Bit mask of SR21 field. */
+#define MWU_PERREGION_SUBSTATRA_SR21_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR21_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR20_Pos (20UL) /*!< Position of SR20 field. */
+#define MWU_PERREGION_SUBSTATRA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR20_Pos) /*!< Bit mask of SR20 field. */
+#define MWU_PERREGION_SUBSTATRA_SR20_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR20_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR19_Pos (19UL) /*!< Position of SR19 field. */
+#define MWU_PERREGION_SUBSTATRA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR19_Pos) /*!< Bit mask of SR19 field. */
+#define MWU_PERREGION_SUBSTATRA_SR19_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR19_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR18_Pos (18UL) /*!< Position of SR18 field. */
+#define MWU_PERREGION_SUBSTATRA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR18_Pos) /*!< Bit mask of SR18 field. */
+#define MWU_PERREGION_SUBSTATRA_SR18_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR18_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR17_Pos (17UL) /*!< Position of SR17 field. */
+#define MWU_PERREGION_SUBSTATRA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR17_Pos) /*!< Bit mask of SR17 field. */
+#define MWU_PERREGION_SUBSTATRA_SR17_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR17_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR16_Pos (16UL) /*!< Position of SR16 field. */
+#define MWU_PERREGION_SUBSTATRA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR16_Pos) /*!< Bit mask of SR16 field. */
+#define MWU_PERREGION_SUBSTATRA_SR16_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR16_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR15_Pos (15UL) /*!< Position of SR15 field. */
+#define MWU_PERREGION_SUBSTATRA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR15_Pos) /*!< Bit mask of SR15 field. */
+#define MWU_PERREGION_SUBSTATRA_SR15_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR15_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR14_Pos (14UL) /*!< Position of SR14 field. */
+#define MWU_PERREGION_SUBSTATRA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR14_Pos) /*!< Bit mask of SR14 field. */
+#define MWU_PERREGION_SUBSTATRA_SR14_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR14_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR13_Pos (13UL) /*!< Position of SR13 field. */
+#define MWU_PERREGION_SUBSTATRA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR13_Pos) /*!< Bit mask of SR13 field. */
+#define MWU_PERREGION_SUBSTATRA_SR13_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR13_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR12_Pos (12UL) /*!< Position of SR12 field. */
+#define MWU_PERREGION_SUBSTATRA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR12_Pos) /*!< Bit mask of SR12 field. */
+#define MWU_PERREGION_SUBSTATRA_SR12_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR12_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR11_Pos (11UL) /*!< Position of SR11 field. */
+#define MWU_PERREGION_SUBSTATRA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR11_Pos) /*!< Bit mask of SR11 field. */
+#define MWU_PERREGION_SUBSTATRA_SR11_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR11_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR10_Pos (10UL) /*!< Position of SR10 field. */
+#define MWU_PERREGION_SUBSTATRA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR10_Pos) /*!< Bit mask of SR10 field. */
+#define MWU_PERREGION_SUBSTATRA_SR10_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR10_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR9_Pos (9UL) /*!< Position of SR9 field. */
+#define MWU_PERREGION_SUBSTATRA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR9_Pos) /*!< Bit mask of SR9 field. */
+#define MWU_PERREGION_SUBSTATRA_SR9_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR9_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR8_Pos (8UL) /*!< Position of SR8 field. */
+#define MWU_PERREGION_SUBSTATRA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR8_Pos) /*!< Bit mask of SR8 field. */
+#define MWU_PERREGION_SUBSTATRA_SR8_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR8_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR7_Pos (7UL) /*!< Position of SR7 field. */
+#define MWU_PERREGION_SUBSTATRA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR7_Pos) /*!< Bit mask of SR7 field. */
+#define MWU_PERREGION_SUBSTATRA_SR7_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR7_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR6_Pos (6UL) /*!< Position of SR6 field. */
+#define MWU_PERREGION_SUBSTATRA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR6_Pos) /*!< Bit mask of SR6 field. */
+#define MWU_PERREGION_SUBSTATRA_SR6_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR6_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR5_Pos (5UL) /*!< Position of SR5 field. */
+#define MWU_PERREGION_SUBSTATRA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR5_Pos) /*!< Bit mask of SR5 field. */
+#define MWU_PERREGION_SUBSTATRA_SR5_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR5_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR4_Pos (4UL) /*!< Position of SR4 field. */
+#define MWU_PERREGION_SUBSTATRA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR4_Pos) /*!< Bit mask of SR4 field. */
+#define MWU_PERREGION_SUBSTATRA_SR4_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR4_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR3_Pos (3UL) /*!< Position of SR3 field. */
+#define MWU_PERREGION_SUBSTATRA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR3_Pos) /*!< Bit mask of SR3 field. */
+#define MWU_PERREGION_SUBSTATRA_SR3_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR3_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR2_Pos (2UL) /*!< Position of SR2 field. */
+#define MWU_PERREGION_SUBSTATRA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR2_Pos) /*!< Bit mask of SR2 field. */
+#define MWU_PERREGION_SUBSTATRA_SR2_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR2_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR1_Pos (1UL) /*!< Position of SR1 field. */
+#define MWU_PERREGION_SUBSTATRA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR1_Pos) /*!< Bit mask of SR1 field. */
+#define MWU_PERREGION_SUBSTATRA_SR1_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR1_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR0_Pos (0UL) /*!< Position of SR0 field. */
+#define MWU_PERREGION_SUBSTATRA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR0_Pos) /*!< Bit mask of SR0 field. */
+#define MWU_PERREGION_SUBSTATRA_SR0_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR0_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Register: MWU_REGIONEN */
+/* Description: Enable/disable regions watch */
+
+/* Bit 27 : Enable/disable read access watch in PREGION[1] */
+#define MWU_REGIONEN_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
+#define MWU_REGIONEN_PRGN1RA_Msk (0x1UL << MWU_REGIONEN_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
+#define MWU_REGIONEN_PRGN1RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
+#define MWU_REGIONEN_PRGN1RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
+
+/* Bit 26 : Enable/disable write access watch in PREGION[1] */
+#define MWU_REGIONEN_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
+#define MWU_REGIONEN_PRGN1WA_Msk (0x1UL << MWU_REGIONEN_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
+#define MWU_REGIONEN_PRGN1WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
+#define MWU_REGIONEN_PRGN1WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
+
+/* Bit 25 : Enable/disable read access watch in PREGION[0] */
+#define MWU_REGIONEN_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
+#define MWU_REGIONEN_PRGN0RA_Msk (0x1UL << MWU_REGIONEN_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
+#define MWU_REGIONEN_PRGN0RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
+#define MWU_REGIONEN_PRGN0RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
+
+/* Bit 24 : Enable/disable write access watch in PREGION[0] */
+#define MWU_REGIONEN_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
+#define MWU_REGIONEN_PRGN0WA_Msk (0x1UL << MWU_REGIONEN_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
+#define MWU_REGIONEN_PRGN0WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
+#define MWU_REGIONEN_PRGN0WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
+
+/* Bit 7 : Enable/disable read access watch in region[3] */
+#define MWU_REGIONEN_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
+#define MWU_REGIONEN_RGN3RA_Msk (0x1UL << MWU_REGIONEN_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
+#define MWU_REGIONEN_RGN3RA_Disable (0UL) /*!< Disable read access watch in this region */
+#define MWU_REGIONEN_RGN3RA_Enable (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 6 : Enable/disable write access watch in region[3] */
+#define MWU_REGIONEN_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
+#define MWU_REGIONEN_RGN3WA_Msk (0x1UL << MWU_REGIONEN_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
+#define MWU_REGIONEN_RGN3WA_Disable (0UL) /*!< Disable write access watch in this region */
+#define MWU_REGIONEN_RGN3WA_Enable (1UL) /*!< Enable write access watch in this region */
+
+/* Bit 5 : Enable/disable read access watch in region[2] */
+#define MWU_REGIONEN_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
+#define MWU_REGIONEN_RGN2RA_Msk (0x1UL << MWU_REGIONEN_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
+#define MWU_REGIONEN_RGN2RA_Disable (0UL) /*!< Disable read access watch in this region */
+#define MWU_REGIONEN_RGN2RA_Enable (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 4 : Enable/disable write access watch in region[2] */
+#define MWU_REGIONEN_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
+#define MWU_REGIONEN_RGN2WA_Msk (0x1UL << MWU_REGIONEN_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
+#define MWU_REGIONEN_RGN2WA_Disable (0UL) /*!< Disable write access watch in this region */
+#define MWU_REGIONEN_RGN2WA_Enable (1UL) /*!< Enable write access watch in this region */
+
+/* Bit 3 : Enable/disable read access watch in region[1] */
+#define MWU_REGIONEN_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
+#define MWU_REGIONEN_RGN1RA_Msk (0x1UL << MWU_REGIONEN_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
+#define MWU_REGIONEN_RGN1RA_Disable (0UL) /*!< Disable read access watch in this region */
+#define MWU_REGIONEN_RGN1RA_Enable (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 2 : Enable/disable write access watch in region[1] */
+#define MWU_REGIONEN_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
+#define MWU_REGIONEN_RGN1WA_Msk (0x1UL << MWU_REGIONEN_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
+#define MWU_REGIONEN_RGN1WA_Disable (0UL) /*!< Disable write access watch in this region */
+#define MWU_REGIONEN_RGN1WA_Enable (1UL) /*!< Enable write access watch in this region */
+
+/* Bit 1 : Enable/disable read access watch in region[0] */
+#define MWU_REGIONEN_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
+#define MWU_REGIONEN_RGN0RA_Msk (0x1UL << MWU_REGIONEN_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
+#define MWU_REGIONEN_RGN0RA_Disable (0UL) /*!< Disable read access watch in this region */
+#define MWU_REGIONEN_RGN0RA_Enable (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 0 : Enable/disable write access watch in region[0] */
+#define MWU_REGIONEN_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
+#define MWU_REGIONEN_RGN0WA_Msk (0x1UL << MWU_REGIONEN_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
+#define MWU_REGIONEN_RGN0WA_Disable (0UL) /*!< Disable write access watch in this region */
+#define MWU_REGIONEN_RGN0WA_Enable (1UL) /*!< Enable write access watch in this region */
+
+/* Register: MWU_REGIONENSET */
+/* Description: Enable regions watch */
+
+/* Bit 27 : Enable read access watch in PREGION[1] */
+#define MWU_REGIONENSET_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
+#define MWU_REGIONENSET_PRGN1RA_Msk (0x1UL << MWU_REGIONENSET_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
+#define MWU_REGIONENSET_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
+#define MWU_REGIONENSET_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
+#define MWU_REGIONENSET_PRGN1RA_Set (1UL) /*!< Enable read access watch in this PREGION */
+
+/* Bit 26 : Enable write access watch in PREGION[1] */
+#define MWU_REGIONENSET_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
+#define MWU_REGIONENSET_PRGN1WA_Msk (0x1UL << MWU_REGIONENSET_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
+#define MWU_REGIONENSET_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
+#define MWU_REGIONENSET_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
+#define MWU_REGIONENSET_PRGN1WA_Set (1UL) /*!< Enable write access watch in this PREGION */
+
+/* Bit 25 : Enable read access watch in PREGION[0] */
+#define MWU_REGIONENSET_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
+#define MWU_REGIONENSET_PRGN0RA_Msk (0x1UL << MWU_REGIONENSET_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
+#define MWU_REGIONENSET_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
+#define MWU_REGIONENSET_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
+#define MWU_REGIONENSET_PRGN0RA_Set (1UL) /*!< Enable read access watch in this PREGION */
+
+/* Bit 24 : Enable write access watch in PREGION[0] */
+#define MWU_REGIONENSET_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
+#define MWU_REGIONENSET_PRGN0WA_Msk (0x1UL << MWU_REGIONENSET_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
+#define MWU_REGIONENSET_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
+#define MWU_REGIONENSET_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
+#define MWU_REGIONENSET_PRGN0WA_Set (1UL) /*!< Enable write access watch in this PREGION */
+
+/* Bit 7 : Enable read access watch in region[3] */
+#define MWU_REGIONENSET_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
+#define MWU_REGIONENSET_RGN3RA_Msk (0x1UL << MWU_REGIONENSET_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
+#define MWU_REGIONENSET_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN3RA_Set (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 6 : Enable write access watch in region[3] */
+#define MWU_REGIONENSET_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
+#define MWU_REGIONENSET_RGN3WA_Msk (0x1UL << MWU_REGIONENSET_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
+#define MWU_REGIONENSET_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN3WA_Set (1UL) /*!< Enable write access watch in this region */
+
+/* Bit 5 : Enable read access watch in region[2] */
+#define MWU_REGIONENSET_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
+#define MWU_REGIONENSET_RGN2RA_Msk (0x1UL << MWU_REGIONENSET_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
+#define MWU_REGIONENSET_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN2RA_Set (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 4 : Enable write access watch in region[2] */
+#define MWU_REGIONENSET_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
+#define MWU_REGIONENSET_RGN2WA_Msk (0x1UL << MWU_REGIONENSET_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
+#define MWU_REGIONENSET_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN2WA_Set (1UL) /*!< Enable write access watch in this region */
+
+/* Bit 3 : Enable read access watch in region[1] */
+#define MWU_REGIONENSET_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
+#define MWU_REGIONENSET_RGN1RA_Msk (0x1UL << MWU_REGIONENSET_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
+#define MWU_REGIONENSET_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN1RA_Set (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 2 : Enable write access watch in region[1] */
+#define MWU_REGIONENSET_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
+#define MWU_REGIONENSET_RGN1WA_Msk (0x1UL << MWU_REGIONENSET_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
+#define MWU_REGIONENSET_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN1WA_Set (1UL) /*!< Enable write access watch in this region */
+
+/* Bit 1 : Enable read access watch in region[0] */
+#define MWU_REGIONENSET_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
+#define MWU_REGIONENSET_RGN0RA_Msk (0x1UL << MWU_REGIONENSET_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
+#define MWU_REGIONENSET_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN0RA_Set (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 0 : Enable write access watch in region[0] */
+#define MWU_REGIONENSET_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
+#define MWU_REGIONENSET_RGN0WA_Msk (0x1UL << MWU_REGIONENSET_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
+#define MWU_REGIONENSET_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN0WA_Set (1UL) /*!< Enable write access watch in this region */
+
+/* Register: MWU_REGIONENCLR */
+/* Description: Disable regions watch */
+
+/* Bit 27 : Disable read access watch in PREGION[1] */
+#define MWU_REGIONENCLR_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
+#define MWU_REGIONENCLR_PRGN1RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
+#define MWU_REGIONENCLR_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
+#define MWU_REGIONENCLR_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
+#define MWU_REGIONENCLR_PRGN1RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
+
+/* Bit 26 : Disable write access watch in PREGION[1] */
+#define MWU_REGIONENCLR_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
+#define MWU_REGIONENCLR_PRGN1WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
+#define MWU_REGIONENCLR_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
+#define MWU_REGIONENCLR_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
+#define MWU_REGIONENCLR_PRGN1WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
+
+/* Bit 25 : Disable read access watch in PREGION[0] */
+#define MWU_REGIONENCLR_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
+#define MWU_REGIONENCLR_PRGN0RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
+#define MWU_REGIONENCLR_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
+#define MWU_REGIONENCLR_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
+#define MWU_REGIONENCLR_PRGN0RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
+
+/* Bit 24 : Disable write access watch in PREGION[0] */
+#define MWU_REGIONENCLR_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
+#define MWU_REGIONENCLR_PRGN0WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
+#define MWU_REGIONENCLR_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
+#define MWU_REGIONENCLR_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
+#define MWU_REGIONENCLR_PRGN0WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
+
+/* Bit 7 : Disable read access watch in region[3] */
+#define MWU_REGIONENCLR_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
+#define MWU_REGIONENCLR_RGN3RA_Msk (0x1UL << MWU_REGIONENCLR_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
+#define MWU_REGIONENCLR_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN3RA_Clear (1UL) /*!< Disable read access watch in this region */
+
+/* Bit 6 : Disable write access watch in region[3] */
+#define MWU_REGIONENCLR_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
+#define MWU_REGIONENCLR_RGN3WA_Msk (0x1UL << MWU_REGIONENCLR_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
+#define MWU_REGIONENCLR_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN3WA_Clear (1UL) /*!< Disable write access watch in this region */
+
+/* Bit 5 : Disable read access watch in region[2] */
+#define MWU_REGIONENCLR_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
+#define MWU_REGIONENCLR_RGN2RA_Msk (0x1UL << MWU_REGIONENCLR_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
+#define MWU_REGIONENCLR_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN2RA_Clear (1UL) /*!< Disable read access watch in this region */
+
+/* Bit 4 : Disable write access watch in region[2] */
+#define MWU_REGIONENCLR_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
+#define MWU_REGIONENCLR_RGN2WA_Msk (0x1UL << MWU_REGIONENCLR_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
+#define MWU_REGIONENCLR_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN2WA_Clear (1UL) /*!< Disable write access watch in this region */
+
+/* Bit 3 : Disable read access watch in region[1] */
+#define MWU_REGIONENCLR_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
+#define MWU_REGIONENCLR_RGN1RA_Msk (0x1UL << MWU_REGIONENCLR_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
+#define MWU_REGIONENCLR_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN1RA_Clear (1UL) /*!< Disable read access watch in this region */
+
+/* Bit 2 : Disable write access watch in region[1] */
+#define MWU_REGIONENCLR_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
+#define MWU_REGIONENCLR_RGN1WA_Msk (0x1UL << MWU_REGIONENCLR_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
+#define MWU_REGIONENCLR_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN1WA_Clear (1UL) /*!< Disable write access watch in this region */
+
+/* Bit 1 : Disable read access watch in region[0] */
+#define MWU_REGIONENCLR_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
+#define MWU_REGIONENCLR_RGN0RA_Msk (0x1UL << MWU_REGIONENCLR_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
+#define MWU_REGIONENCLR_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN0RA_Clear (1UL) /*!< Disable read access watch in this region */
+
+/* Bit 0 : Disable write access watch in region[0] */
+#define MWU_REGIONENCLR_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
+#define MWU_REGIONENCLR_RGN0WA_Msk (0x1UL << MWU_REGIONENCLR_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
+#define MWU_REGIONENCLR_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN0WA_Clear (1UL) /*!< Disable write access watch in this region */
+
+/* Register: MWU_REGION_START */
+/* Description: Description cluster[0]:  Start address for region 0 */
+
+/* Bits 31..0 : Start address for region */
+#define MWU_REGION_START_START_Pos (0UL) /*!< Position of START field. */
+#define MWU_REGION_START_START_Msk (0xFFFFFFFFUL << MWU_REGION_START_START_Pos) /*!< Bit mask of START field. */
+
+/* Register: MWU_REGION_END */
+/* Description: Description cluster[0]:  End address of region 0 */
+
+/* Bits 31..0 : End address of region. */
+#define MWU_REGION_END_END_Pos (0UL) /*!< Position of END field. */
+#define MWU_REGION_END_END_Msk (0xFFFFFFFFUL << MWU_REGION_END_END_Pos) /*!< Bit mask of END field. */
+
+/* Register: MWU_PREGION_START */
+/* Description: Description cluster[0]:  Reserved for future use */
+
+/* Bits 31..0 : Reserved for future use */
+#define MWU_PREGION_START_START_Pos (0UL) /*!< Position of START field. */
+#define MWU_PREGION_START_START_Msk (0xFFFFFFFFUL << MWU_PREGION_START_START_Pos) /*!< Bit mask of START field. */
+
+/* Register: MWU_PREGION_END */
+/* Description: Description cluster[0]:  Reserved for future use */
+
+/* Bits 31..0 : Reserved for future use */
+#define MWU_PREGION_END_END_Pos (0UL) /*!< Position of END field. */
+#define MWU_PREGION_END_END_Msk (0xFFFFFFFFUL << MWU_PREGION_END_END_Pos) /*!< Bit mask of END field. */
+
+/* Register: MWU_PREGION_SUBS */
+/* Description: Description cluster[0]:  Subregions of region 0 */
+
+/* Bit 31 : Include or exclude subregion 31 in region */
+#define MWU_PREGION_SUBS_SR31_Pos (31UL) /*!< Position of SR31 field. */
+#define MWU_PREGION_SUBS_SR31_Msk (0x1UL << MWU_PREGION_SUBS_SR31_Pos) /*!< Bit mask of SR31 field. */
+#define MWU_PREGION_SUBS_SR31_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR31_Include (1UL) /*!< Include */
+
+/* Bit 30 : Include or exclude subregion 30 in region */
+#define MWU_PREGION_SUBS_SR30_Pos (30UL) /*!< Position of SR30 field. */
+#define MWU_PREGION_SUBS_SR30_Msk (0x1UL << MWU_PREGION_SUBS_SR30_Pos) /*!< Bit mask of SR30 field. */
+#define MWU_PREGION_SUBS_SR30_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR30_Include (1UL) /*!< Include */
+
+/* Bit 29 : Include or exclude subregion 29 in region */
+#define MWU_PREGION_SUBS_SR29_Pos (29UL) /*!< Position of SR29 field. */
+#define MWU_PREGION_SUBS_SR29_Msk (0x1UL << MWU_PREGION_SUBS_SR29_Pos) /*!< Bit mask of SR29 field. */
+#define MWU_PREGION_SUBS_SR29_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR29_Include (1UL) /*!< Include */
+
+/* Bit 28 : Include or exclude subregion 28 in region */
+#define MWU_PREGION_SUBS_SR28_Pos (28UL) /*!< Position of SR28 field. */
+#define MWU_PREGION_SUBS_SR28_Msk (0x1UL << MWU_PREGION_SUBS_SR28_Pos) /*!< Bit mask of SR28 field. */
+#define MWU_PREGION_SUBS_SR28_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR28_Include (1UL) /*!< Include */
+
+/* Bit 27 : Include or exclude subregion 27 in region */
+#define MWU_PREGION_SUBS_SR27_Pos (27UL) /*!< Position of SR27 field. */
+#define MWU_PREGION_SUBS_SR27_Msk (0x1UL << MWU_PREGION_SUBS_SR27_Pos) /*!< Bit mask of SR27 field. */
+#define MWU_PREGION_SUBS_SR27_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR27_Include (1UL) /*!< Include */
+
+/* Bit 26 : Include or exclude subregion 26 in region */
+#define MWU_PREGION_SUBS_SR26_Pos (26UL) /*!< Position of SR26 field. */
+#define MWU_PREGION_SUBS_SR26_Msk (0x1UL << MWU_PREGION_SUBS_SR26_Pos) /*!< Bit mask of SR26 field. */
+#define MWU_PREGION_SUBS_SR26_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR26_Include (1UL) /*!< Include */
+
+/* Bit 25 : Include or exclude subregion 25 in region */
+#define MWU_PREGION_SUBS_SR25_Pos (25UL) /*!< Position of SR25 field. */
+#define MWU_PREGION_SUBS_SR25_Msk (0x1UL << MWU_PREGION_SUBS_SR25_Pos) /*!< Bit mask of SR25 field. */
+#define MWU_PREGION_SUBS_SR25_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR25_Include (1UL) /*!< Include */
+
+/* Bit 24 : Include or exclude subregion 24 in region */
+#define MWU_PREGION_SUBS_SR24_Pos (24UL) /*!< Position of SR24 field. */
+#define MWU_PREGION_SUBS_SR24_Msk (0x1UL << MWU_PREGION_SUBS_SR24_Pos) /*!< Bit mask of SR24 field. */
+#define MWU_PREGION_SUBS_SR24_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR24_Include (1UL) /*!< Include */
+
+/* Bit 23 : Include or exclude subregion 23 in region */
+#define MWU_PREGION_SUBS_SR23_Pos (23UL) /*!< Position of SR23 field. */
+#define MWU_PREGION_SUBS_SR23_Msk (0x1UL << MWU_PREGION_SUBS_SR23_Pos) /*!< Bit mask of SR23 field. */
+#define MWU_PREGION_SUBS_SR23_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR23_Include (1UL) /*!< Include */
+
+/* Bit 22 : Include or exclude subregion 22 in region */
+#define MWU_PREGION_SUBS_SR22_Pos (22UL) /*!< Position of SR22 field. */
+#define MWU_PREGION_SUBS_SR22_Msk (0x1UL << MWU_PREGION_SUBS_SR22_Pos) /*!< Bit mask of SR22 field. */
+#define MWU_PREGION_SUBS_SR22_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR22_Include (1UL) /*!< Include */
+
+/* Bit 21 : Include or exclude subregion 21 in region */
+#define MWU_PREGION_SUBS_SR21_Pos (21UL) /*!< Position of SR21 field. */
+#define MWU_PREGION_SUBS_SR21_Msk (0x1UL << MWU_PREGION_SUBS_SR21_Pos) /*!< Bit mask of SR21 field. */
+#define MWU_PREGION_SUBS_SR21_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR21_Include (1UL) /*!< Include */
+
+/* Bit 20 : Include or exclude subregion 20 in region */
+#define MWU_PREGION_SUBS_SR20_Pos (20UL) /*!< Position of SR20 field. */
+#define MWU_PREGION_SUBS_SR20_Msk (0x1UL << MWU_PREGION_SUBS_SR20_Pos) /*!< Bit mask of SR20 field. */
+#define MWU_PREGION_SUBS_SR20_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR20_Include (1UL) /*!< Include */
+
+/* Bit 19 : Include or exclude subregion 19 in region */
+#define MWU_PREGION_SUBS_SR19_Pos (19UL) /*!< Position of SR19 field. */
+#define MWU_PREGION_SUBS_SR19_Msk (0x1UL << MWU_PREGION_SUBS_SR19_Pos) /*!< Bit mask of SR19 field. */
+#define MWU_PREGION_SUBS_SR19_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR19_Include (1UL) /*!< Include */
+
+/* Bit 18 : Include or exclude subregion 18 in region */
+#define MWU_PREGION_SUBS_SR18_Pos (18UL) /*!< Position of SR18 field. */
+#define MWU_PREGION_SUBS_SR18_Msk (0x1UL << MWU_PREGION_SUBS_SR18_Pos) /*!< Bit mask of SR18 field. */
+#define MWU_PREGION_SUBS_SR18_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR18_Include (1UL) /*!< Include */
+
+/* Bit 17 : Include or exclude subregion 17 in region */
+#define MWU_PREGION_SUBS_SR17_Pos (17UL) /*!< Position of SR17 field. */
+#define MWU_PREGION_SUBS_SR17_Msk (0x1UL << MWU_PREGION_SUBS_SR17_Pos) /*!< Bit mask of SR17 field. */
+#define MWU_PREGION_SUBS_SR17_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR17_Include (1UL) /*!< Include */
+
+/* Bit 16 : Include or exclude subregion 16 in region */
+#define MWU_PREGION_SUBS_SR16_Pos (16UL) /*!< Position of SR16 field. */
+#define MWU_PREGION_SUBS_SR16_Msk (0x1UL << MWU_PREGION_SUBS_SR16_Pos) /*!< Bit mask of SR16 field. */
+#define MWU_PREGION_SUBS_SR16_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR16_Include (1UL) /*!< Include */
+
+/* Bit 15 : Include or exclude subregion 15 in region */
+#define MWU_PREGION_SUBS_SR15_Pos (15UL) /*!< Position of SR15 field. */
+#define MWU_PREGION_SUBS_SR15_Msk (0x1UL << MWU_PREGION_SUBS_SR15_Pos) /*!< Bit mask of SR15 field. */
+#define MWU_PREGION_SUBS_SR15_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR15_Include (1UL) /*!< Include */
+
+/* Bit 14 : Include or exclude subregion 14 in region */
+#define MWU_PREGION_SUBS_SR14_Pos (14UL) /*!< Position of SR14 field. */
+#define MWU_PREGION_SUBS_SR14_Msk (0x1UL << MWU_PREGION_SUBS_SR14_Pos) /*!< Bit mask of SR14 field. */
+#define MWU_PREGION_SUBS_SR14_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR14_Include (1UL) /*!< Include */
+
+/* Bit 13 : Include or exclude subregion 13 in region */
+#define MWU_PREGION_SUBS_SR13_Pos (13UL) /*!< Position of SR13 field. */
+#define MWU_PREGION_SUBS_SR13_Msk (0x1UL << MWU_PREGION_SUBS_SR13_Pos) /*!< Bit mask of SR13 field. */
+#define MWU_PREGION_SUBS_SR13_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR13_Include (1UL) /*!< Include */
+
+/* Bit 12 : Include or exclude subregion 12 in region */
+#define MWU_PREGION_SUBS_SR12_Pos (12UL) /*!< Position of SR12 field. */
+#define MWU_PREGION_SUBS_SR12_Msk (0x1UL << MWU_PREGION_SUBS_SR12_Pos) /*!< Bit mask of SR12 field. */
+#define MWU_PREGION_SUBS_SR12_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR12_Include (1UL) /*!< Include */
+
+/* Bit 11 : Include or exclude subregion 11 in region */
+#define MWU_PREGION_SUBS_SR11_Pos (11UL) /*!< Position of SR11 field. */
+#define MWU_PREGION_SUBS_SR11_Msk (0x1UL << MWU_PREGION_SUBS_SR11_Pos) /*!< Bit mask of SR11 field. */
+#define MWU_PREGION_SUBS_SR11_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR11_Include (1UL) /*!< Include */
+
+/* Bit 10 : Include or exclude subregion 10 in region */
+#define MWU_PREGION_SUBS_SR10_Pos (10UL) /*!< Position of SR10 field. */
+#define MWU_PREGION_SUBS_SR10_Msk (0x1UL << MWU_PREGION_SUBS_SR10_Pos) /*!< Bit mask of SR10 field. */
+#define MWU_PREGION_SUBS_SR10_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR10_Include (1UL) /*!< Include */
+
+/* Bit 9 : Include or exclude subregion 9 in region */
+#define MWU_PREGION_SUBS_SR9_Pos (9UL) /*!< Position of SR9 field. */
+#define MWU_PREGION_SUBS_SR9_Msk (0x1UL << MWU_PREGION_SUBS_SR9_Pos) /*!< Bit mask of SR9 field. */
+#define MWU_PREGION_SUBS_SR9_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR9_Include (1UL) /*!< Include */
+
+/* Bit 8 : Include or exclude subregion 8 in region */
+#define MWU_PREGION_SUBS_SR8_Pos (8UL) /*!< Position of SR8 field. */
+#define MWU_PREGION_SUBS_SR8_Msk (0x1UL << MWU_PREGION_SUBS_SR8_Pos) /*!< Bit mask of SR8 field. */
+#define MWU_PREGION_SUBS_SR8_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR8_Include (1UL) /*!< Include */
+
+/* Bit 7 : Include or exclude subregion 7 in region */
+#define MWU_PREGION_SUBS_SR7_Pos (7UL) /*!< Position of SR7 field. */
+#define MWU_PREGION_SUBS_SR7_Msk (0x1UL << MWU_PREGION_SUBS_SR7_Pos) /*!< Bit mask of SR7 field. */
+#define MWU_PREGION_SUBS_SR7_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR7_Include (1UL) /*!< Include */
+
+/* Bit 6 : Include or exclude subregion 6 in region */
+#define MWU_PREGION_SUBS_SR6_Pos (6UL) /*!< Position of SR6 field. */
+#define MWU_PREGION_SUBS_SR6_Msk (0x1UL << MWU_PREGION_SUBS_SR6_Pos) /*!< Bit mask of SR6 field. */
+#define MWU_PREGION_SUBS_SR6_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR6_Include (1UL) /*!< Include */
+
+/* Bit 5 : Include or exclude subregion 5 in region */
+#define MWU_PREGION_SUBS_SR5_Pos (5UL) /*!< Position of SR5 field. */
+#define MWU_PREGION_SUBS_SR5_Msk (0x1UL << MWU_PREGION_SUBS_SR5_Pos) /*!< Bit mask of SR5 field. */
+#define MWU_PREGION_SUBS_SR5_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR5_Include (1UL) /*!< Include */
+
+/* Bit 4 : Include or exclude subregion 4 in region */
+#define MWU_PREGION_SUBS_SR4_Pos (4UL) /*!< Position of SR4 field. */
+#define MWU_PREGION_SUBS_SR4_Msk (0x1UL << MWU_PREGION_SUBS_SR4_Pos) /*!< Bit mask of SR4 field. */
+#define MWU_PREGION_SUBS_SR4_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR4_Include (1UL) /*!< Include */
+
+/* Bit 3 : Include or exclude subregion 3 in region */
+#define MWU_PREGION_SUBS_SR3_Pos (3UL) /*!< Position of SR3 field. */
+#define MWU_PREGION_SUBS_SR3_Msk (0x1UL << MWU_PREGION_SUBS_SR3_Pos) /*!< Bit mask of SR3 field. */
+#define MWU_PREGION_SUBS_SR3_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR3_Include (1UL) /*!< Include */
+
+/* Bit 2 : Include or exclude subregion 2 in region */
+#define MWU_PREGION_SUBS_SR2_Pos (2UL) /*!< Position of SR2 field. */
+#define MWU_PREGION_SUBS_SR2_Msk (0x1UL << MWU_PREGION_SUBS_SR2_Pos) /*!< Bit mask of SR2 field. */
+#define MWU_PREGION_SUBS_SR2_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR2_Include (1UL) /*!< Include */
+
+/* Bit 1 : Include or exclude subregion 1 in region */
+#define MWU_PREGION_SUBS_SR1_Pos (1UL) /*!< Position of SR1 field. */
+#define MWU_PREGION_SUBS_SR1_Msk (0x1UL << MWU_PREGION_SUBS_SR1_Pos) /*!< Bit mask of SR1 field. */
+#define MWU_PREGION_SUBS_SR1_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR1_Include (1UL) /*!< Include */
+
+/* Bit 0 : Include or exclude subregion 0 in region */
+#define MWU_PREGION_SUBS_SR0_Pos (0UL) /*!< Position of SR0 field. */
+#define MWU_PREGION_SUBS_SR0_Msk (0x1UL << MWU_PREGION_SUBS_SR0_Pos) /*!< Bit mask of SR0 field. */
+#define MWU_PREGION_SUBS_SR0_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR0_Include (1UL) /*!< Include */
+
+
+/* Peripheral: NFCT */
+/* Description: NFC-A compatible radio */
+
+/* Register: NFCT_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 1 : Shortcut between FIELDLOST event and SENSE task */
+#define NFCT_SHORTS_FIELDLOST_SENSE_Pos (1UL) /*!< Position of FIELDLOST_SENSE field. */
+#define NFCT_SHORTS_FIELDLOST_SENSE_Msk (0x1UL << NFCT_SHORTS_FIELDLOST_SENSE_Pos) /*!< Bit mask of FIELDLOST_SENSE field. */
+#define NFCT_SHORTS_FIELDLOST_SENSE_Disabled (0UL) /*!< Disable shortcut */
+#define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between FIELDDETECTED event and ACTIVATE task */
+#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos (0UL) /*!< Position of FIELDDETECTED_ACTIVATE field. */
+#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk (0x1UL << NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos) /*!< Bit mask of FIELDDETECTED_ACTIVATE field. */
+#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled (0UL) /*!< Disable shortcut */
+#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: NFCT_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 20 : Enable or disable interrupt for STARTED event */
+#define NFCT_INTEN_STARTED_Pos (20UL) /*!< Position of STARTED field. */
+#define NFCT_INTEN_STARTED_Msk (0x1UL << NFCT_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define NFCT_INTEN_STARTED_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_STARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 19 : Enable or disable interrupt for SELECTED event */
+#define NFCT_INTEN_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
+#define NFCT_INTEN_SELECTED_Msk (0x1UL << NFCT_INTEN_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
+#define NFCT_INTEN_SELECTED_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_SELECTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 18 : Enable or disable interrupt for COLLISION event */
+#define NFCT_INTEN_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
+#define NFCT_INTEN_COLLISION_Msk (0x1UL << NFCT_INTEN_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
+#define NFCT_INTEN_COLLISION_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_COLLISION_Enabled (1UL) /*!< Enable */
+
+/* Bit 14 : Enable or disable interrupt for AUTOCOLRESSTARTED event */
+#define NFCT_INTEN_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
+#define NFCT_INTEN_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTEN_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
+#define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 12 : Enable or disable interrupt for ENDTX event */
+#define NFCT_INTEN_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
+#define NFCT_INTEN_ENDTX_Msk (0x1UL << NFCT_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define NFCT_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
+
+/* Bit 11 : Enable or disable interrupt for ENDRX event */
+#define NFCT_INTEN_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
+#define NFCT_INTEN_ENDRX_Msk (0x1UL << NFCT_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define NFCT_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
+
+/* Bit 10 : Enable or disable interrupt for RXERROR event */
+#define NFCT_INTEN_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
+#define NFCT_INTEN_RXERROR_Msk (0x1UL << NFCT_INTEN_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
+#define NFCT_INTEN_RXERROR_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_RXERROR_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable interrupt for ERROR event */
+#define NFCT_INTEN_ERROR_Pos (7UL) /*!< Position of ERROR field. */
+#define NFCT_INTEN_ERROR_Msk (0x1UL << NFCT_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define NFCT_INTEN_ERROR_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_ERROR_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable interrupt for RXFRAMEEND event */
+#define NFCT_INTEN_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
+#define NFCT_INTEN_RXFRAMEEND_Msk (0x1UL << NFCT_INTEN_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
+#define NFCT_INTEN_RXFRAMEEND_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_RXFRAMEEND_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable interrupt for RXFRAMESTART event */
+#define NFCT_INTEN_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
+#define NFCT_INTEN_RXFRAMESTART_Msk (0x1UL << NFCT_INTEN_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
+#define NFCT_INTEN_RXFRAMESTART_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_RXFRAMESTART_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for TXFRAMEEND event */
+#define NFCT_INTEN_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
+#define NFCT_INTEN_TXFRAMEEND_Msk (0x1UL << NFCT_INTEN_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
+#define NFCT_INTEN_TXFRAMEEND_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_TXFRAMEEND_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable interrupt for TXFRAMESTART event */
+#define NFCT_INTEN_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
+#define NFCT_INTEN_TXFRAMESTART_Msk (0x1UL << NFCT_INTEN_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
+#define NFCT_INTEN_TXFRAMESTART_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_TXFRAMESTART_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for FIELDLOST event */
+#define NFCT_INTEN_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
+#define NFCT_INTEN_FIELDLOST_Msk (0x1UL << NFCT_INTEN_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
+#define NFCT_INTEN_FIELDLOST_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_FIELDLOST_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for FIELDDETECTED event */
+#define NFCT_INTEN_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
+#define NFCT_INTEN_FIELDDETECTED_Msk (0x1UL << NFCT_INTEN_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
+#define NFCT_INTEN_FIELDDETECTED_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_FIELDDETECTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for READY event */
+#define NFCT_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
+#define NFCT_INTEN_READY_Msk (0x1UL << NFCT_INTEN_READY_Pos) /*!< Bit mask of READY field. */
+#define NFCT_INTEN_READY_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_READY_Enabled (1UL) /*!< Enable */
+
+/* Register: NFCT_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 20 : Write '1' to Enable interrupt for STARTED event */
+#define NFCT_INTENSET_STARTED_Pos (20UL) /*!< Position of STARTED field. */
+#define NFCT_INTENSET_STARTED_Msk (0x1UL << NFCT_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define NFCT_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_STARTED_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to Enable interrupt for SELECTED event */
+#define NFCT_INTENSET_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
+#define NFCT_INTENSET_SELECTED_Msk (0x1UL << NFCT_INTENSET_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
+#define NFCT_INTENSET_SELECTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_SELECTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_SELECTED_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to Enable interrupt for COLLISION event */
+#define NFCT_INTENSET_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
+#define NFCT_INTENSET_COLLISION_Msk (0x1UL << NFCT_INTENSET_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
+#define NFCT_INTENSET_COLLISION_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_COLLISION_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_COLLISION_Set (1UL) /*!< Enable */
+
+/* Bit 14 : Write '1' to Enable interrupt for AUTOCOLRESSTARTED event */
+#define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
+#define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
+#define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 12 : Write '1' to Enable interrupt for ENDTX event */
+#define NFCT_INTENSET_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
+#define NFCT_INTENSET_ENDTX_Msk (0x1UL << NFCT_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define NFCT_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_ENDTX_Set (1UL) /*!< Enable */
+
+/* Bit 11 : Write '1' to Enable interrupt for ENDRX event */
+#define NFCT_INTENSET_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
+#define NFCT_INTENSET_ENDRX_Msk (0x1UL << NFCT_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define NFCT_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_ENDRX_Set (1UL) /*!< Enable */
+
+/* Bit 10 : Write '1' to Enable interrupt for RXERROR event */
+#define NFCT_INTENSET_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
+#define NFCT_INTENSET_RXERROR_Msk (0x1UL << NFCT_INTENSET_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
+#define NFCT_INTENSET_RXERROR_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_RXERROR_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_RXERROR_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for ERROR event */
+#define NFCT_INTENSET_ERROR_Pos (7UL) /*!< Position of ERROR field. */
+#define NFCT_INTENSET_ERROR_Msk (0x1UL << NFCT_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define NFCT_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for RXFRAMEEND event */
+#define NFCT_INTENSET_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
+#define NFCT_INTENSET_RXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
+#define NFCT_INTENSET_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_RXFRAMEEND_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable interrupt for RXFRAMESTART event */
+#define NFCT_INTENSET_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
+#define NFCT_INTENSET_RXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
+#define NFCT_INTENSET_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_RXFRAMESTART_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for TXFRAMEEND event */
+#define NFCT_INTENSET_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
+#define NFCT_INTENSET_TXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
+#define NFCT_INTENSET_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_TXFRAMEEND_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for TXFRAMESTART event */
+#define NFCT_INTENSET_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
+#define NFCT_INTENSET_TXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
+#define NFCT_INTENSET_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_TXFRAMESTART_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for FIELDLOST event */
+#define NFCT_INTENSET_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
+#define NFCT_INTENSET_FIELDLOST_Msk (0x1UL << NFCT_INTENSET_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
+#define NFCT_INTENSET_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_FIELDLOST_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for FIELDDETECTED event */
+#define NFCT_INTENSET_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
+#define NFCT_INTENSET_FIELDDETECTED_Msk (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
+#define NFCT_INTENSET_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_FIELDDETECTED_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for READY event */
+#define NFCT_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
+#define NFCT_INTENSET_READY_Msk (0x1UL << NFCT_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define NFCT_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_READY_Set (1UL) /*!< Enable */
+
+/* Register: NFCT_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 20 : Write '1' to Disable interrupt for STARTED event */
+#define NFCT_INTENCLR_STARTED_Pos (20UL) /*!< Position of STARTED field. */
+#define NFCT_INTENCLR_STARTED_Msk (0x1UL << NFCT_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define NFCT_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to Disable interrupt for SELECTED event */
+#define NFCT_INTENCLR_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
+#define NFCT_INTENCLR_SELECTED_Msk (0x1UL << NFCT_INTENCLR_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
+#define NFCT_INTENCLR_SELECTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_SELECTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_SELECTED_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to Disable interrupt for COLLISION event */
+#define NFCT_INTENCLR_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
+#define NFCT_INTENCLR_COLLISION_Msk (0x1UL << NFCT_INTENCLR_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
+#define NFCT_INTENCLR_COLLISION_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_COLLISION_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_COLLISION_Clear (1UL) /*!< Disable */
+
+/* Bit 14 : Write '1' to Disable interrupt for AUTOCOLRESSTARTED event */
+#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
+#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
+#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 12 : Write '1' to Disable interrupt for ENDTX event */
+#define NFCT_INTENCLR_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
+#define NFCT_INTENCLR_ENDTX_Msk (0x1UL << NFCT_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define NFCT_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
+
+/* Bit 11 : Write '1' to Disable interrupt for ENDRX event */
+#define NFCT_INTENCLR_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
+#define NFCT_INTENCLR_ENDRX_Msk (0x1UL << NFCT_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define NFCT_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
+
+/* Bit 10 : Write '1' to Disable interrupt for RXERROR event */
+#define NFCT_INTENCLR_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
+#define NFCT_INTENCLR_RXERROR_Msk (0x1UL << NFCT_INTENCLR_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
+#define NFCT_INTENCLR_RXERROR_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_RXERROR_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_RXERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for ERROR event */
+#define NFCT_INTENCLR_ERROR_Pos (7UL) /*!< Position of ERROR field. */
+#define NFCT_INTENCLR_ERROR_Msk (0x1UL << NFCT_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define NFCT_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for RXFRAMEEND event */
+#define NFCT_INTENCLR_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
+#define NFCT_INTENCLR_RXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
+#define NFCT_INTENCLR_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_RXFRAMEEND_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable interrupt for RXFRAMESTART event */
+#define NFCT_INTENCLR_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
+#define NFCT_INTENCLR_RXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
+#define NFCT_INTENCLR_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_RXFRAMESTART_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for TXFRAMEEND event */
+#define NFCT_INTENCLR_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
+#define NFCT_INTENCLR_TXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
+#define NFCT_INTENCLR_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_TXFRAMEEND_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for TXFRAMESTART event */
+#define NFCT_INTENCLR_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
+#define NFCT_INTENCLR_TXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
+#define NFCT_INTENCLR_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_TXFRAMESTART_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for FIELDLOST event */
+#define NFCT_INTENCLR_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
+#define NFCT_INTENCLR_FIELDLOST_Msk (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
+#define NFCT_INTENCLR_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_FIELDLOST_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for FIELDDETECTED event */
+#define NFCT_INTENCLR_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
+#define NFCT_INTENCLR_FIELDDETECTED_Msk (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
+#define NFCT_INTENCLR_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_FIELDDETECTED_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for READY event */
+#define NFCT_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
+#define NFCT_INTENCLR_READY_Msk (0x1UL << NFCT_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define NFCT_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_READY_Clear (1UL) /*!< Disable */
+
+/* Register: NFCT_ERRORSTATUS */
+/* Description: NFC Error Status register */
+
+/* Bit 3 : Field level is too low at min load resistance */
+#define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos (3UL) /*!< Position of NFCFIELDTOOWEAK field. */
+#define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Msk (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos) /*!< Bit mask of NFCFIELDTOOWEAK field. */
+
+/* Bit 2 : Field level is too high at max load resistance */
+#define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos (2UL) /*!< Position of NFCFIELDTOOSTRONG field. */
+#define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Msk (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos) /*!< Bit mask of NFCFIELDTOOSTRONG field. */
+
+/* Bit 0 : No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX */
+#define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos (0UL) /*!< Position of FRAMEDELAYTIMEOUT field. */
+#define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Msk (0x1UL << NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos) /*!< Bit mask of FRAMEDELAYTIMEOUT field. */
+
+/* Register: NFCT_FRAMESTATUS_RX */
+/* Description: Result of last incoming frames */
+
+/* Bit 3 : Overrun detected */
+#define NFCT_FRAMESTATUS_RX_OVERRUN_Pos (3UL) /*!< Position of OVERRUN field. */
+#define NFCT_FRAMESTATUS_RX_OVERRUN_Msk (0x1UL << NFCT_FRAMESTATUS_RX_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
+#define NFCT_FRAMESTATUS_RX_OVERRUN_NoOverrun (0UL) /*!< No overrun detected */
+#define NFCT_FRAMESTATUS_RX_OVERRUN_Overrun (1UL) /*!< Overrun error */
+
+/* Bit 2 : Parity status of received frame */
+#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos (2UL) /*!< Position of PARITYSTATUS field. */
+#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Msk (0x1UL << NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos) /*!< Bit mask of PARITYSTATUS field. */
+#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityOK (0UL) /*!< Frame received with parity OK */
+#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityError (1UL) /*!< Frame received with parity error */
+
+/* Bit 0 : No valid End of Frame detected */
+#define NFCT_FRAMESTATUS_RX_CRCERROR_Pos (0UL) /*!< Position of CRCERROR field. */
+#define NFCT_FRAMESTATUS_RX_CRCERROR_Msk (0x1UL << NFCT_FRAMESTATUS_RX_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
+#define NFCT_FRAMESTATUS_RX_CRCERROR_CRCCorrect (0UL) /*!< Valid CRC detected */
+#define NFCT_FRAMESTATUS_RX_CRCERROR_CRCError (1UL) /*!< CRC received does not match local check */
+
+/* Register: NFCT_CURRENTLOADCTRL */
+/* Description: Current value driven to the NFC Load Control */
+
+/* Bits 5..0 : Current value driven to the NFC Load Control */
+#define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos (0UL) /*!< Position of CURRENTLOADCTRL field. */
+#define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Msk (0x3FUL << NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos) /*!< Bit mask of CURRENTLOADCTRL field. */
+
+/* Register: NFCT_FIELDPRESENT */
+/* Description: Indicates the presence or not of a valid field */
+
+/* Bit 1 : Indicates if the low level has locked to the field */
+#define NFCT_FIELDPRESENT_LOCKDETECT_Pos (1UL) /*!< Position of LOCKDETECT field. */
+#define NFCT_FIELDPRESENT_LOCKDETECT_Msk (0x1UL << NFCT_FIELDPRESENT_LOCKDETECT_Pos) /*!< Bit mask of LOCKDETECT field. */
+#define NFCT_FIELDPRESENT_LOCKDETECT_NotLocked (0UL) /*!< Not locked to field */
+#define NFCT_FIELDPRESENT_LOCKDETECT_Locked (1UL) /*!< Locked to field */
+
+/* Bit 0 : Indicates the presence or not of a valid field. Available only in the activated state. */
+#define NFCT_FIELDPRESENT_FIELDPRESENT_Pos (0UL) /*!< Position of FIELDPRESENT field. */
+#define NFCT_FIELDPRESENT_FIELDPRESENT_Msk (0x1UL << NFCT_FIELDPRESENT_FIELDPRESENT_Pos) /*!< Bit mask of FIELDPRESENT field. */
+#define NFCT_FIELDPRESENT_FIELDPRESENT_NoField (0UL) /*!< No valid field detected */
+#define NFCT_FIELDPRESENT_FIELDPRESENT_FieldPresent (1UL) /*!< Valid field detected */
+
+/* Register: NFCT_FRAMEDELAYMIN */
+/* Description: Minimum frame delay */
+
+/* Bits 15..0 : Minimum frame delay in number of 13.56 MHz clocks */
+#define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos (0UL) /*!< Position of FRAMEDELAYMIN field. */
+#define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Msk (0xFFFFUL << NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos) /*!< Bit mask of FRAMEDELAYMIN field. */
+
+/* Register: NFCT_FRAMEDELAYMAX */
+/* Description: Maximum frame delay */
+
+/* Bits 15..0 : Maximum frame delay in number of 13.56 MHz clocks */
+#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos (0UL) /*!< Position of FRAMEDELAYMAX field. */
+#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk (0xFFFFUL << NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos) /*!< Bit mask of FRAMEDELAYMAX field. */
+
+/* Register: NFCT_FRAMEDELAYMODE */
+/* Description: Configuration register for the Frame Delay Timer */
+
+/* Bits 1..0 : Configuration register for the Frame Delay Timer */
+#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos (0UL) /*!< Position of FRAMEDELAYMODE field. */
+#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Msk (0x3UL << NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos) /*!< Bit mask of FRAMEDELAYMODE field. */
+#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_FreeRun (0UL) /*!< Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. */
+#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Window (1UL) /*!< Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX */
+#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_ExactVal (2UL) /*!< Frame is transmitted exactly at FRAMEDELAYMAX */
+#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_WindowGrid (3UL) /*!< Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX */
+
+/* Register: NFCT_PACKETPTR */
+/* Description: Packet pointer for TXD and RXD data storage in Data RAM */
+
+/* Bits 31..0 : Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte aligned RAM address. */
+#define NFCT_PACKETPTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define NFCT_PACKETPTR_PTR_Msk (0xFFFFFFFFUL << NFCT_PACKETPTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: NFCT_MAXLEN */
+/* Description: Size of allocated for TXD and RXD data storage buffer in Data RAM */
+
+/* Bits 8..0 : Size of allocated for TXD and RXD data storage buffer in Data RAM */
+#define NFCT_MAXLEN_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
+#define NFCT_MAXLEN_MAXLEN_Msk (0x1FFUL << NFCT_MAXLEN_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
+
+/* Register: NFCT_TXD_FRAMECONFIG */
+/* Description: Configuration of outgoing frames */
+
+/* Bit 4 : CRC mode for outgoing frames */
+#define NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos (4UL) /*!< Position of CRCMODETX field. */
+#define NFCT_TXD_FRAMECONFIG_CRCMODETX_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos) /*!< Bit mask of CRCMODETX field. */
+#define NFCT_TXD_FRAMECONFIG_CRCMODETX_NoCRCTX (0UL) /*!< CRC is not added to the frame */
+#define NFCT_TXD_FRAMECONFIG_CRCMODETX_CRC16TX (1UL) /*!< 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame */
+
+/* Bit 2 : Adding SoF or not in TX frames */
+#define NFCT_TXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
+#define NFCT_TXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */
+#define NFCT_TXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< Start of Frame symbol not added */
+#define NFCT_TXD_FRAMECONFIG_SOF_SoF (1UL) /*!< Start of Frame symbol added */
+
+/* Bit 1 : Discarding unused bits in start or at end of a Frame */
+#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos (1UL) /*!< Position of DISCARDMODE field. */
+#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos) /*!< Bit mask of DISCARDMODE field. */
+#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardEnd (0UL) /*!< Unused bits is discarded at end of frame */
+#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardStart (1UL) /*!< Unused bits is discarded at start of frame */
+
+/* Bit 0 : Adding parity or not in the frame */
+#define NFCT_TXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */
+#define NFCT_TXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define NFCT_TXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not added in TX frames */
+#define NFCT_TXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is added TX frames */
+
+/* Register: NFCT_TXD_AMOUNT */
+/* Description: Size of outgoing frame */
+
+/* Bits 11..3 : Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing */
+#define NFCT_TXD_AMOUNT_TXDATABYTES_Pos (3UL) /*!< Position of TXDATABYTES field. */
+#define NFCT_TXD_AMOUNT_TXDATABYTES_Msk (0x1FFUL << NFCT_TXD_AMOUNT_TXDATABYTES_Pos) /*!< Bit mask of TXDATABYTES field. */
+
+/* Bits 2..0 : Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). */
+#define NFCT_TXD_AMOUNT_TXDATABITS_Pos (0UL) /*!< Position of TXDATABITS field. */
+#define NFCT_TXD_AMOUNT_TXDATABITS_Msk (0x7UL << NFCT_TXD_AMOUNT_TXDATABITS_Pos) /*!< Bit mask of TXDATABITS field. */
+
+/* Register: NFCT_RXD_FRAMECONFIG */
+/* Description: Configuration of incoming frames */
+
+/* Bit 4 : CRC mode for incoming frames */
+#define NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos (4UL) /*!< Position of CRCMODERX field. */
+#define NFCT_RXD_FRAMECONFIG_CRCMODERX_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos) /*!< Bit mask of CRCMODERX field. */
+#define NFCT_RXD_FRAMECONFIG_CRCMODERX_NoCRCRX (0UL) /*!< CRC is not expected in RX frames */
+#define NFCT_RXD_FRAMECONFIG_CRCMODERX_CRC16RX (1UL) /*!< Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated */
+
+/* Bit 2 : SoF expected or not in RX frames */
+#define NFCT_RXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
+#define NFCT_RXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */
+#define NFCT_RXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< Start of Frame symbol is not expected in RX frames */
+#define NFCT_RXD_FRAMECONFIG_SOF_SoF (1UL) /*!< Start of Frame symbol is expected in RX frames */
+
+/* Bit 0 : Parity expected or not in RX frame */
+#define NFCT_RXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */
+#define NFCT_RXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define NFCT_RXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not expected in RX frames */
+#define NFCT_RXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is expected in RX frames */
+
+/* Register: NFCT_RXD_AMOUNT */
+/* Description: Size of last incoming frame */
+
+/* Bits 11..3 : Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) */
+#define NFCT_RXD_AMOUNT_RXDATABYTES_Pos (3UL) /*!< Position of RXDATABYTES field. */
+#define NFCT_RXD_AMOUNT_RXDATABYTES_Msk (0x1FFUL << NFCT_RXD_AMOUNT_RXDATABYTES_Pos) /*!< Bit mask of RXDATABYTES field. */
+
+/* Bits 2..0 : Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). */
+#define NFCT_RXD_AMOUNT_RXDATABITS_Pos (0UL) /*!< Position of RXDATABITS field. */
+#define NFCT_RXD_AMOUNT_RXDATABITS_Msk (0x7UL << NFCT_RXD_AMOUNT_RXDATABITS_Pos) /*!< Bit mask of RXDATABITS field. */
+
+/* Register: NFCT_NFCID1_LAST */
+/* Description: Last NFCID1 part (4, 7 or 10 bytes ID) */
+
+/* Bits 31..24 : NFCID1 byte W */
+#define NFCT_NFCID1_LAST_NFCID1_W_Pos (24UL) /*!< Position of NFCID1_W field. */
+#define NFCT_NFCID1_LAST_NFCID1_W_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_W_Pos) /*!< Bit mask of NFCID1_W field. */
+
+/* Bits 23..16 : NFCID1 byte X */
+#define NFCT_NFCID1_LAST_NFCID1_X_Pos (16UL) /*!< Position of NFCID1_X field. */
+#define NFCT_NFCID1_LAST_NFCID1_X_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_X_Pos) /*!< Bit mask of NFCID1_X field. */
+
+/* Bits 15..8 : NFCID1 byte Y */
+#define NFCT_NFCID1_LAST_NFCID1_Y_Pos (8UL) /*!< Position of NFCID1_Y field. */
+#define NFCT_NFCID1_LAST_NFCID1_Y_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Y_Pos) /*!< Bit mask of NFCID1_Y field. */
+
+/* Bits 7..0 : NFCID1 byte Z (very last byte sent) */
+#define NFCT_NFCID1_LAST_NFCID1_Z_Pos (0UL) /*!< Position of NFCID1_Z field. */
+#define NFCT_NFCID1_LAST_NFCID1_Z_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Z_Pos) /*!< Bit mask of NFCID1_Z field. */
+
+/* Register: NFCT_NFCID1_2ND_LAST */
+/* Description: Second last NFCID1 part (7 or 10 bytes ID) */
+
+/* Bits 23..16 : NFCID1 byte T */
+#define NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos (16UL) /*!< Position of NFCID1_T field. */
+#define NFCT_NFCID1_2ND_LAST_NFCID1_T_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos) /*!< Bit mask of NFCID1_T field. */
+
+/* Bits 15..8 : NFCID1 byte U */
+#define NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos (8UL) /*!< Position of NFCID1_U field. */
+#define NFCT_NFCID1_2ND_LAST_NFCID1_U_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos) /*!< Bit mask of NFCID1_U field. */
+
+/* Bits 7..0 : NFCID1 byte V */
+#define NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos (0UL) /*!< Position of NFCID1_V field. */
+#define NFCT_NFCID1_2ND_LAST_NFCID1_V_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos) /*!< Bit mask of NFCID1_V field. */
+
+/* Register: NFCT_NFCID1_3RD_LAST */
+/* Description: Third last NFCID1 part (10 bytes ID) */
+
+/* Bits 23..16 : NFCID1 byte Q */
+#define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos (16UL) /*!< Position of NFCID1_Q field. */
+#define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos) /*!< Bit mask of NFCID1_Q field. */
+
+/* Bits 15..8 : NFCID1 byte R */
+#define NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos (8UL) /*!< Position of NFCID1_R field. */
+#define NFCT_NFCID1_3RD_LAST_NFCID1_R_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos) /*!< Bit mask of NFCID1_R field. */
+
+/* Bits 7..0 : NFCID1 byte S */
+#define NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos (0UL) /*!< Position of NFCID1_S field. */
+#define NFCT_NFCID1_3RD_LAST_NFCID1_S_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos) /*!< Bit mask of NFCID1_S field. */
+
+/* Register: NFCT_SENSRES */
+/* Description: NFC-A SENS_RES auto-response settings */
+
+/* Bits 15..12 : Reserved for future use. Shall be 0. */
+#define NFCT_SENSRES_RFU74_Pos (12UL) /*!< Position of RFU74 field. */
+#define NFCT_SENSRES_RFU74_Msk (0xFUL << NFCT_SENSRES_RFU74_Pos) /*!< Bit mask of RFU74 field. */
+
+/* Bits 11..8 : Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
+#define NFCT_SENSRES_PLATFCONFIG_Pos (8UL) /*!< Position of PLATFCONFIG field. */
+#define NFCT_SENSRES_PLATFCONFIG_Msk (0xFUL << NFCT_SENSRES_PLATFCONFIG_Pos) /*!< Bit mask of PLATFCONFIG field. */
+
+/* Bits 7..6 : NFCID1 size. This value is used by the Auto collision resolution engine. */
+#define NFCT_SENSRES_NFCIDSIZE_Pos (6UL) /*!< Position of NFCIDSIZE field. */
+#define NFCT_SENSRES_NFCIDSIZE_Msk (0x3UL << NFCT_SENSRES_NFCIDSIZE_Pos) /*!< Bit mask of NFCIDSIZE field. */
+#define NFCT_SENSRES_NFCIDSIZE_NFCID1Single (0UL) /*!< NFCID1 size: single (4 bytes) */
+#define NFCT_SENSRES_NFCIDSIZE_NFCID1Double (1UL) /*!< NFCID1 size: double (7 bytes) */
+#define NFCT_SENSRES_NFCIDSIZE_NFCID1Triple (2UL) /*!< NFCID1 size: triple (10 bytes) */
+
+/* Bit 5 : Reserved for future use. Shall be 0. */
+#define NFCT_SENSRES_RFU5_Pos (5UL) /*!< Position of RFU5 field. */
+#define NFCT_SENSRES_RFU5_Msk (0x1UL << NFCT_SENSRES_RFU5_Pos) /*!< Bit mask of RFU5 field. */
+
+/* Bits 4..0 : Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
+#define NFCT_SENSRES_BITFRAMESDD_Pos (0UL) /*!< Position of BITFRAMESDD field. */
+#define NFCT_SENSRES_BITFRAMESDD_Msk (0x1FUL << NFCT_SENSRES_BITFRAMESDD_Pos) /*!< Bit mask of BITFRAMESDD field. */
+#define NFCT_SENSRES_BITFRAMESDD_SDD00000 (0UL) /*!< SDD pattern 00000 */
+#define NFCT_SENSRES_BITFRAMESDD_SDD00001 (1UL) /*!< SDD pattern 00001 */
+#define NFCT_SENSRES_BITFRAMESDD_SDD00010 (2UL) /*!< SDD pattern 00010 */
+#define NFCT_SENSRES_BITFRAMESDD_SDD00100 (4UL) /*!< SDD pattern 00100 */
+#define NFCT_SENSRES_BITFRAMESDD_SDD01000 (8UL) /*!< SDD pattern 01000 */
+#define NFCT_SENSRES_BITFRAMESDD_SDD10000 (16UL) /*!< SDD pattern 10000 */
+
+/* Register: NFCT_SELRES */
+/* Description: NFC-A SEL_RES auto-response settings */
+
+/* Bit 7 : Reserved for future use. Shall be 0. */
+#define NFCT_SELRES_RFU7_Pos (7UL) /*!< Position of RFU7 field. */
+#define NFCT_SELRES_RFU7_Msk (0x1UL << NFCT_SELRES_RFU7_Pos) /*!< Bit mask of RFU7 field. */
+
+/* Bits 6..5 : Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
+#define NFCT_SELRES_PROTOCOL_Pos (5UL) /*!< Position of PROTOCOL field. */
+#define NFCT_SELRES_PROTOCOL_Msk (0x3UL << NFCT_SELRES_PROTOCOL_Pos) /*!< Bit mask of PROTOCOL field. */
+
+/* Bits 4..3 : Reserved for future use. Shall be 0. */
+#define NFCT_SELRES_RFU43_Pos (3UL) /*!< Position of RFU43 field. */
+#define NFCT_SELRES_RFU43_Msk (0x3UL << NFCT_SELRES_RFU43_Pos) /*!< Bit mask of RFU43 field. */
+
+/* Bit 2 : Cascade bit (controlled by hardware, write has no effect) */
+#define NFCT_SELRES_CASCADE_Pos (2UL) /*!< Position of CASCADE field. */
+#define NFCT_SELRES_CASCADE_Msk (0x1UL << NFCT_SELRES_CASCADE_Pos) /*!< Bit mask of CASCADE field. */
+#define NFCT_SELRES_CASCADE_Complete (0UL) /*!< NFCID1 complete */
+#define NFCT_SELRES_CASCADE_NotComplete (1UL) /*!< NFCID1 not complete */
+
+/* Bits 1..0 : Reserved for future use. Shall be 0. */
+#define NFCT_SELRES_RFU10_Pos (0UL) /*!< Position of RFU10 field. */
+#define NFCT_SELRES_RFU10_Msk (0x3UL << NFCT_SELRES_RFU10_Pos) /*!< Bit mask of RFU10 field. */
+
+
+/* Peripheral: NVMC */
+/* Description: Non Volatile Memory Controller */
+
+/* Register: NVMC_READY */
+/* Description: Ready flag */
+
+/* Bit 0 : NVMC is ready or busy */
+#define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
+#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
+#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */
+#define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */
+
+/* Register: NVMC_CONFIG */
+/* Description: Configuration register */
+
+/* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */
+#define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
+#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
+#define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */
+#define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write Enabled */
+#define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */
+
+/* Register: NVMC_ERASEPAGE */
+/* Description: Register for erasing a page in Code area */
+
+/* Bits 31..0 : Register for starting erase of a page in Code area */
+#define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */
+#define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */
+
+/* Register: NVMC_ERASEPCR1 */
+/* Description: Deprecated register -  Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
+
+/* Bits 31..0 : Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
+#define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */
+#define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */
+
+/* Register: NVMC_ERASEALL */
+/* Description: Register for erasing all non-volatile user memory */
+
+/* Bit 0 : Erase all non-volatile memory including UICR registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. */
+#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
+#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
+#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */
+#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */
+
+/* Register: NVMC_ERASEPCR0 */
+/* Description: Deprecated register -  Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
+
+/* Bits 31..0 : Register for starting erase of a page in Code area. Equivalent to ERASEPAGE. */
+#define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */
+#define NVMC_ERASEPCR0_ERASEPCR0_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos) /*!< Bit mask of ERASEPCR0 field. */
+
+/* Register: NVMC_ERASEUICR */
+/* Description: Register for erasing User Information Configuration Registers */
+
+/* Bit 0 : Register starting erase of all User Information Configuration Registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. */
+#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */
+#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */
+#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation */
+#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start erase of UICR */
+
+/* Register: NVMC_ICACHECNF */
+/* Description: I-Code cache configuration register. */
+
+/* Bit 8 : Cache profiling enable */
+#define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */
+#define NVMC_ICACHECNF_CACHEPROFEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos) /*!< Bit mask of CACHEPROFEN field. */
+#define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0UL) /*!< Disable cache profiling */
+#define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL) /*!< Enable cache profiling */
+
+/* Bit 0 : Cache enable */
+#define NVMC_ICACHECNF_CACHEEN_Pos (0UL) /*!< Position of CACHEEN field. */
+#define NVMC_ICACHECNF_CACHEEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos) /*!< Bit mask of CACHEEN field. */
+#define NVMC_ICACHECNF_CACHEEN_Disabled (0UL) /*!< Disable cache. Invalidates all cache entries. */
+#define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */
+
+/* Register: NVMC_IHIT */
+/* Description: I-Code cache hit counter. */
+
+/* Bits 31..0 : Number of cache hits */
+#define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */
+#define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */
+
+/* Register: NVMC_IMISS */
+/* Description: I-Code cache miss counter. */
+
+/* Bits 31..0 : Number of cache misses */
+#define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */
+#define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */
+
+
+/* Peripheral: GPIO */
+/* Description: GPIO Port 1 */
+
+/* Register: GPIO_OUT */
+/* Description: Write GPIO port */
+
+/* Bit 31 : Pin 31 */
+#define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */
+
+/* Bit 30 : Pin 30 */
+#define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */
+
+/* Bit 29 : Pin 29 */
+#define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */
+
+/* Bit 28 : Pin 28 */
+#define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */
+
+/* Bit 27 : Pin 27 */
+#define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */
+
+/* Bit 26 : Pin 26 */
+#define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */
+
+/* Bit 25 : Pin 25 */
+#define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */
+
+/* Bit 24 : Pin 24 */
+#define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */
+
+/* Bit 23 : Pin 23 */
+#define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */
+
+/* Bit 22 : Pin 22 */
+#define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */
+
+/* Bit 21 : Pin 21 */
+#define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */
+
+/* Bit 20 : Pin 20 */
+#define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */
+
+/* Bit 19 : Pin 19 */
+#define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */
+
+/* Bit 18 : Pin 18 */
+#define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */
+
+/* Bit 17 : Pin 17 */
+#define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */
+
+/* Bit 16 : Pin 16 */
+#define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */
+
+/* Bit 15 : Pin 15 */
+#define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */
+
+/* Bit 14 : Pin 14 */
+#define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */
+
+/* Bit 13 : Pin 13 */
+#define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */
+
+/* Bit 12 : Pin 12 */
+#define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */
+
+/* Bit 11 : Pin 11 */
+#define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */
+
+/* Bit 10 : Pin 10 */
+#define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */
+
+/* Bit 9 : Pin 9 */
+#define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */
+
+/* Bit 8 : Pin 8 */
+#define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */
+
+/* Bit 7 : Pin 7 */
+#define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */
+
+/* Bit 6 : Pin 6 */
+#define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */
+
+/* Bit 5 : Pin 5 */
+#define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */
+
+/* Bit 4 : Pin 4 */
+#define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */
+
+/* Bit 3 : Pin 3 */
+#define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */
+
+/* Bit 2 : Pin 2 */
+#define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */
+
+/* Bit 1 : Pin 1 */
+#define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */
+
+/* Bit 0 : Pin 0 */
+#define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */
+
+/* Register: GPIO_OUTSET */
+/* Description: Set individual bits in GPIO port */
+
+/* Bit 31 : Pin 31 */
+#define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 30 : Pin 30 */
+#define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 29 : Pin 29 */
+#define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 28 : Pin 28 */
+#define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 27 : Pin 27 */
+#define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 26 : Pin 26 */
+#define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 25 : Pin 25 */
+#define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 24 : Pin 24 */
+#define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 23 : Pin 23 */
+#define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 22 : Pin 22 */
+#define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 21 : Pin 21 */
+#define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 20 : Pin 20 */
+#define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 19 : Pin 19 */
+#define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 18 : Pin 18 */
+#define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 17 : Pin 17 */
+#define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 16 : Pin 16 */
+#define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 15 : Pin 15 */
+#define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 14 : Pin 14 */
+#define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 13 : Pin 13 */
+#define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 12 : Pin 12 */
+#define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 11 : Pin 11 */
+#define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 10 : Pin 10 */
+#define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 9 : Pin 9 */
+#define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 8 : Pin 8 */
+#define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 7 : Pin 7 */
+#define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 6 : Pin 6 */
+#define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 5 : Pin 5 */
+#define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 4 : Pin 4 */
+#define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 3 : Pin 3 */
+#define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 2 : Pin 2 */
+#define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 1 : Pin 1 */
+#define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 0 : Pin 0 */
+#define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Register: GPIO_OUTCLR */
+/* Description: Clear individual bits in GPIO port */
+
+/* Bit 31 : Pin 31 */
+#define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 30 : Pin 30 */
+#define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 29 : Pin 29 */
+#define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 28 : Pin 28 */
+#define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 27 : Pin 27 */
+#define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 26 : Pin 26 */
+#define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 25 : Pin 25 */
+#define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 24 : Pin 24 */
+#define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 23 : Pin 23 */
+#define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 22 : Pin 22 */
+#define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 21 : Pin 21 */
+#define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 20 : Pin 20 */
+#define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 19 : Pin 19 */
+#define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 18 : Pin 18 */
+#define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 17 : Pin 17 */
+#define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 16 : Pin 16 */
+#define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 15 : Pin 15 */
+#define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 14 : Pin 14 */
+#define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 13 : Pin 13 */
+#define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 12 : Pin 12 */
+#define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 11 : Pin 11 */
+#define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 10 : Pin 10 */
+#define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 9 : Pin 9 */
+#define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 8 : Pin 8 */
+#define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 7 : Pin 7 */
+#define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 6 : Pin 6 */
+#define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 5 : Pin 5 */
+#define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 4 : Pin 4 */
+#define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 3 : Pin 3 */
+#define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 2 : Pin 2 */
+#define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 1 : Pin 1 */
+#define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 0 : Pin 0 */
+#define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Register: GPIO_IN */
+/* Description: Read GPIO port */
+
+/* Bit 31 : Pin 31 */
+#define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */
+
+/* Bit 30 : Pin 30 */
+#define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */
+
+/* Bit 29 : Pin 29 */
+#define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */
+
+/* Bit 28 : Pin 28 */
+#define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */
+
+/* Bit 27 : Pin 27 */
+#define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */
+
+/* Bit 26 : Pin 26 */
+#define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */
+
+/* Bit 25 : Pin 25 */
+#define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */
+
+/* Bit 24 : Pin 24 */
+#define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */
+
+/* Bit 23 : Pin 23 */
+#define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */
+
+/* Bit 22 : Pin 22 */
+#define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */
+
+/* Bit 21 : Pin 21 */
+#define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */
+
+/* Bit 20 : Pin 20 */
+#define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */
+
+/* Bit 19 : Pin 19 */
+#define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */
+
+/* Bit 18 : Pin 18 */
+#define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */
+
+/* Bit 17 : Pin 17 */
+#define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */
+
+/* Bit 16 : Pin 16 */
+#define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */
+
+/* Bit 15 : Pin 15 */
+#define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */
+
+/* Bit 14 : Pin 14 */
+#define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */
+
+/* Bit 13 : Pin 13 */
+#define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */
+
+/* Bit 12 : Pin 12 */
+#define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */
+
+/* Bit 11 : Pin 11 */
+#define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */
+
+/* Bit 10 : Pin 10 */
+#define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */
+
+/* Bit 9 : Pin 9 */
+#define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */
+
+/* Bit 8 : Pin 8 */
+#define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */
+
+/* Bit 7 : Pin 7 */
+#define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */
+
+/* Bit 6 : Pin 6 */
+#define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */
+
+/* Bit 5 : Pin 5 */
+#define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */
+
+/* Bit 4 : Pin 4 */
+#define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */
+
+/* Bit 3 : Pin 3 */
+#define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */
+
+/* Bit 2 : Pin 2 */
+#define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */
+
+/* Bit 1 : Pin 1 */
+#define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */
+
+/* Bit 0 : Pin 0 */
+#define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */
+
+/* Register: GPIO_DIR */
+/* Description: Direction of GPIO pins */
+
+/* Bit 31 : Pin 31 */
+#define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */
+
+/* Bit 30 : Pin 30 */
+#define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */
+
+/* Bit 29 : Pin 29 */
+#define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */
+
+/* Bit 28 : Pin 28 */
+#define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */
+
+/* Bit 27 : Pin 27 */
+#define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */
+
+/* Bit 26 : Pin 26 */
+#define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */
+
+/* Bit 25 : Pin 25 */
+#define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */
+
+/* Bit 24 : Pin 24 */
+#define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */
+
+/* Bit 23 : Pin 23 */
+#define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */
+
+/* Bit 22 : Pin 22 */
+#define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */
+
+/* Bit 21 : Pin 21 */
+#define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */
+
+/* Bit 20 : Pin 20 */
+#define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */
+
+/* Bit 19 : Pin 19 */
+#define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */
+
+/* Bit 18 : Pin 18 */
+#define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */
+
+/* Bit 17 : Pin 17 */
+#define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */
+
+/* Bit 16 : Pin 16 */
+#define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */
+
+/* Bit 15 : Pin 15 */
+#define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */
+
+/* Bit 14 : Pin 14 */
+#define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */
+
+/* Bit 13 : Pin 13 */
+#define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */
+
+/* Bit 12 : Pin 12 */
+#define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */
+
+/* Bit 11 : Pin 11 */
+#define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */
+
+/* Bit 10 : Pin 10 */
+#define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */
+
+/* Bit 9 : Pin 9 */
+#define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */
+
+/* Bit 8 : Pin 8 */
+#define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */
+
+/* Bit 7 : Pin 7 */
+#define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */
+
+/* Bit 6 : Pin 6 */
+#define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */
+
+/* Bit 5 : Pin 5 */
+#define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */
+
+/* Bit 4 : Pin 4 */
+#define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */
+
+/* Bit 3 : Pin 3 */
+#define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */
+
+/* Bit 2 : Pin 2 */
+#define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */
+
+/* Bit 1 : Pin 1 */
+#define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */
+
+/* Bit 0 : Pin 0 */
+#define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */
+
+/* Register: GPIO_DIRSET */
+/* Description: DIR set register */
+
+/* Bit 31 : Set as output pin 31 */
+#define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 30 : Set as output pin 30 */
+#define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 29 : Set as output pin 29 */
+#define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 28 : Set as output pin 28 */
+#define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 27 : Set as output pin 27 */
+#define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 26 : Set as output pin 26 */
+#define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 25 : Set as output pin 25 */
+#define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 24 : Set as output pin 24 */
+#define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 23 : Set as output pin 23 */
+#define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 22 : Set as output pin 22 */
+#define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 21 : Set as output pin 21 */
+#define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 20 : Set as output pin 20 */
+#define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 19 : Set as output pin 19 */
+#define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 18 : Set as output pin 18 */
+#define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 17 : Set as output pin 17 */
+#define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 16 : Set as output pin 16 */
+#define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 15 : Set as output pin 15 */
+#define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 14 : Set as output pin 14 */
+#define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 13 : Set as output pin 13 */
+#define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 12 : Set as output pin 12 */
+#define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 11 : Set as output pin 11 */
+#define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 10 : Set as output pin 10 */
+#define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 9 : Set as output pin 9 */
+#define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 8 : Set as output pin 8 */
+#define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 7 : Set as output pin 7 */
+#define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 6 : Set as output pin 6 */
+#define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 5 : Set as output pin 5 */
+#define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 4 : Set as output pin 4 */
+#define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 3 : Set as output pin 3 */
+#define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 2 : Set as output pin 2 */
+#define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 1 : Set as output pin 1 */
+#define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 0 : Set as output pin 0 */
+#define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Register: GPIO_DIRCLR */
+/* Description: DIR clear register */
+
+/* Bit 31 : Set as input pin 31 */
+#define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 30 : Set as input pin 30 */
+#define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 29 : Set as input pin 29 */
+#define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 28 : Set as input pin 28 */
+#define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 27 : Set as input pin 27 */
+#define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 26 : Set as input pin 26 */
+#define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 25 : Set as input pin 25 */
+#define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 24 : Set as input pin 24 */
+#define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 23 : Set as input pin 23 */
+#define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 22 : Set as input pin 22 */
+#define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 21 : Set as input pin 21 */
+#define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 20 : Set as input pin 20 */
+#define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 19 : Set as input pin 19 */
+#define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 18 : Set as input pin 18 */
+#define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 17 : Set as input pin 17 */
+#define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 16 : Set as input pin 16 */
+#define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 15 : Set as input pin 15 */
+#define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 14 : Set as input pin 14 */
+#define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 13 : Set as input pin 13 */
+#define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 12 : Set as input pin 12 */
+#define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 11 : Set as input pin 11 */
+#define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 10 : Set as input pin 10 */
+#define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 9 : Set as input pin 9 */
+#define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 8 : Set as input pin 8 */
+#define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 7 : Set as input pin 7 */
+#define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 6 : Set as input pin 6 */
+#define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 5 : Set as input pin 5 */
+#define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 4 : Set as input pin 4 */
+#define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 3 : Set as input pin 3 */
+#define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 2 : Set as input pin 2 */
+#define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 1 : Set as input pin 1 */
+#define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 0 : Set as input pin 0 */
+#define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Register: GPIO_LATCH */
+/* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */
+
+/* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */
+
+/* Register: GPIO_DETECTMODE */
+/* Description: Select between default DETECT signal behaviour and LDETECT mode */
+
+/* Bit 0 : Select between default DETECT signal behaviour and LDETECT mode */
+#define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */
+#define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */
+#define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */
+#define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */
+
+/* Register: GPIO_PIN_CNF */
+/* Description: Description collection[0]:  Configuration of GPIO pins */
+
+/* Bits 17..16 : Pin sensing mechanism */
+#define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
+#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
+#define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */
+#define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */
+#define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */
+
+/* Bits 10..8 : Drive configuration */
+#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
+#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
+#define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */
+#define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */
+#define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */
+#define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */
+#define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or connections) */
+#define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */
+#define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-and connections) */
+#define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */
+
+/* Bits 3..2 : Pull configuration */
+#define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
+#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
+#define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */
+#define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */
+#define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */
+
+/* Bit 1 : Connect or disconnect input buffer */
+#define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
+#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
+#define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */
+#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */
+
+/* Bit 0 : Pin direction. Same physical register as DIR register */
+#define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
+#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
+#define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */
+#define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */
+
+
+/* Peripheral: PDM */
+/* Description: Pulse Density Modulation (Digital Microphone) Interface */
+
+/* Register: PDM_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 2 : Enable or disable interrupt for END event */
+#define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */
+#define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */
+#define PDM_INTEN_END_Disabled (0UL) /*!< Disable */
+#define PDM_INTEN_END_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for STOPPED event */
+#define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for STARTED event */
+#define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */
+#define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */
+
+/* Register: PDM_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 2 : Write '1' to Enable interrupt for END event */
+#define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */
+#define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define PDM_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
+#define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for STARTED event */
+#define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */
+
+/* Register: PDM_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 2 : Write '1' to Disable interrupt for END event */
+#define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */
+#define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
+#define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for STARTED event */
+#define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
+
+/* Register: PDM_ENABLE */
+/* Description: PDM module enable register */
+
+/* Bit 0 : Enable or disable PDM module */
+#define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
+
+/* Register: PDM_PDMCLKCTRL */
+/* Description: PDM clock generator control */
+
+/* Bits 31..0 : PDM_CLK frequency */
+#define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */
+#define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */
+#define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */
+#define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz */
+#define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz */
+
+/* Register: PDM_MODE */
+/* Description: Defines the routing of the connected PDM microphones' signals */
+
+/* Bit 1 : Defines on which PDM_CLK edge Left (or mono) is sampled */
+#define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */
+#define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */
+#define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */
+#define PDM_MODE_EDGE_LeftRising (1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */
+
+/* Bit 0 : Mono or stereo operation */
+#define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */
+#define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */
+#define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] */
+#define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] */
+
+/* Register: PDM_GAINL */
+/* Description: Left output gain adjustment */
+
+/* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00    -20 dB gain adjust 0x01  -19.5 dB gain adjust (...) 0x27   -0.5 dB gain adjust 0x28      0 dB gain adjust 0x29   +0.5 dB gain adjust (...) 0x4F  +19.5 dB gain adjust 0x50    +20 dB gain adjust */
+#define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */
+#define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */
+#define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
+#define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */
+#define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */
+
+/* Register: PDM_GAINR */
+/* Description: Right output gain adjustment */
+
+/* Bits 7..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */
+#define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */
+#define PDM_GAINR_GAINR_Msk (0xFFUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */
+#define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
+#define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */
+#define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */
+
+/* Register: PDM_PSEL_CLK */
+/* Description: Pin number configuration for PDM CLK signal */
+
+/* Bit 31 : Connection */
+#define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define PDM_PSEL_CLK_CONNECT_Connected (0UL) /*!< Connect */
+#define PDM_PSEL_CLK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: PDM_PSEL_DIN */
+/* Description: Pin number configuration for PDM DIN signal */
+
+/* Bit 31 : Connection */
+#define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define PDM_PSEL_DIN_CONNECT_Connected (0UL) /*!< Connect */
+#define PDM_PSEL_DIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: PDM_SAMPLE_PTR */
+/* Description: RAM address pointer to write samples to with EasyDMA */
+
+/* Bits 31..0 : Address to write PDM samples to over DMA */
+#define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */
+#define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */
+
+/* Register: PDM_SAMPLE_MAXCNT */
+/* Description: Number of samples to allocate memory for in EasyDMA mode */
+
+/* Bits 14..0 : Length of DMA RAM allocation in number of samples */
+#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */
+#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */
+
+
+/* Peripheral: POWER */
+/* Description: Power control */
+
+/* Register: POWER_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 6 : Write '1' to Enable interrupt for SLEEPEXIT event */
+#define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
+#define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
+#define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable interrupt for SLEEPENTER event */
+#define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
+#define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
+#define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for POFWARN event */
+#define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
+#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
+#define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */
+
+/* Register: POWER_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 6 : Write '1' to Disable interrupt for SLEEPEXIT event */
+#define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
+#define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
+#define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable interrupt for SLEEPENTER event */
+#define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
+#define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
+#define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for POFWARN event */
+#define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
+#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
+#define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */
+
+/* Register: POWER_RESETREAS */
+/* Description: Reset reason */
+
+/* Bit 19 : Reset due to wake up from System OFF mode by NFC field detect */
+#define POWER_RESETREAS_NFC_Pos (19UL) /*!< Position of NFC field. */
+#define POWER_RESETREAS_NFC_Msk (0x1UL << POWER_RESETREAS_NFC_Pos) /*!< Bit mask of NFC field. */
+#define POWER_RESETREAS_NFC_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_NFC_Detected (1UL) /*!< Detected */
+
+/* Bit 18 : Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode */
+#define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */
+#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
+#define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */
+
+/* Bit 17 : Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP */
+#define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */
+#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
+#define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Detected */
+
+/* Bit 16 : Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO */
+#define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */
+#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
+#define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */
+
+/* Bit 3 : Reset from CPU lock-up detected */
+#define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */
+#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
+#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */
+
+/* Bit 2 : Reset from soft reset detected */
+#define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
+#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
+#define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */
+
+/* Bit 1 : Reset from watchdog detected */
+#define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
+#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
+#define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */
+
+/* Bit 0 : Reset from pin-reset detected */
+#define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
+#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
+#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */
+
+/* Register: POWER_RAMSTATUS */
+/* Description: Deprecated register -  RAM status register */
+
+/* Bit 3 : RAM block 3 is on or off/powering up */
+#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */
+#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */
+#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< Off */
+#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< On */
+
+/* Bit 2 : RAM block 2 is on or off/powering up */
+#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */
+#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */
+#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< Off */
+#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< On */
+
+/* Bit 1 : RAM block 1 is on or off/powering up */
+#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */
+#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */
+#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< Off */
+#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< On */
+
+/* Bit 0 : RAM block 0 is on or off/powering up */
+#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */
+#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */
+#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< Off */
+#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< On */
+
+/* Register: POWER_SYSTEMOFF */
+/* Description: System OFF register */
+
+/* Bit 0 : Enable System OFF mode */
+#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
+#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
+#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */
+
+/* Register: POWER_POFCON */
+/* Description: Power failure comparator configuration */
+
+/* Bits 4..1 : Power failure comparator threshold setting */
+#define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
+#define POWER_POFCON_THRESHOLD_Msk (0xFUL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
+#define POWER_POFCON_THRESHOLD_V17 (4UL) /*!< Set threshold to 1.7 V */
+#define POWER_POFCON_THRESHOLD_V18 (5UL) /*!< Set threshold to 1.8 V */
+#define POWER_POFCON_THRESHOLD_V19 (6UL) /*!< Set threshold to 1.9 V */
+#define POWER_POFCON_THRESHOLD_V20 (7UL) /*!< Set threshold to 2.0 V */
+#define POWER_POFCON_THRESHOLD_V21 (8UL) /*!< Set threshold to 2.1 V */
+#define POWER_POFCON_THRESHOLD_V22 (9UL) /*!< Set threshold to 2.2 V */
+#define POWER_POFCON_THRESHOLD_V23 (10UL) /*!< Set threshold to 2.3 V */
+#define POWER_POFCON_THRESHOLD_V24 (11UL) /*!< Set threshold to 2.4 V */
+#define POWER_POFCON_THRESHOLD_V25 (12UL) /*!< Set threshold to 2.5 V */
+#define POWER_POFCON_THRESHOLD_V26 (13UL) /*!< Set threshold to 2.6 V */
+#define POWER_POFCON_THRESHOLD_V27 (14UL) /*!< Set threshold to 2.7 V */
+#define POWER_POFCON_THRESHOLD_V28 (15UL) /*!< Set threshold to 2.8 V */
+
+/* Bit 0 : Enable or disable power failure comparator */
+#define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
+#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */
+#define POWER_POFCON_POF_Disabled (0UL) /*!< Disable */
+#define POWER_POFCON_POF_Enabled (1UL) /*!< Enable */
+
+/* Register: POWER_GPREGRET */
+/* Description: General purpose retention register */
+
+/* Bits 7..0 : General purpose retention register */
+#define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
+#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
+
+/* Register: POWER_GPREGRET2 */
+/* Description: General purpose retention register */
+
+/* Bits 7..0 : General purpose retention register */
+#define POWER_GPREGRET2_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
+#define POWER_GPREGRET2_GPREGRET_Msk (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
+
+/* Register: POWER_RAMON */
+/* Description: Deprecated register -  RAM on/off register (this register is retained) */
+
+/* Bit 17 : Keep retention on RAM block 1 when RAM block is switched off */
+#define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */
+#define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */
+#define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< Off */
+#define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< On */
+
+/* Bit 16 : Keep retention on RAM block 0 when RAM block is switched off */
+#define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */
+#define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */
+#define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< Off */
+#define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< On */
+
+/* Bit 1 : Keep RAM block 1 on or off in system ON Mode */
+#define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */
+#define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */
+#define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< Off */
+#define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< On */
+
+/* Bit 0 : Keep RAM block 0 on or off in system ON Mode */
+#define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */
+#define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */
+#define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< Off */
+#define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< On */
+
+/* Register: POWER_RAMONB */
+/* Description: Deprecated register -  RAM on/off register (this register is retained) */
+
+/* Bit 17 : Keep retention on RAM block 3 when RAM block is switched off */
+#define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */
+#define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */
+#define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< Off */
+#define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< On */
+
+/* Bit 16 : Keep retention on RAM block 2 when RAM block is switched off */
+#define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */
+#define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */
+#define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< Off */
+#define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< On */
+
+/* Bit 1 : Keep RAM block 3 on or off in system ON Mode */
+#define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */
+#define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */
+#define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< Off */
+#define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< On */
+
+/* Bit 0 : Keep RAM block 2 on or off in system ON Mode */
+#define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */
+#define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */
+#define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< Off */
+#define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< On */
+
+/* Register: POWER_DCDCEN */
+/* Description: DC/DC enable register */
+
+/* Bit 0 : Enable or disable DC/DC converter */
+#define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
+#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
+#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< Disable */
+#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */
+
+/* Register: POWER_RAM_POWER */
+/* Description: Description cluster[0]:  RAM0 power control register */
+
+/* Bit 17 : Keep retention on RAM section S1 when RAM section is in OFF */
+#define POWER_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
+#define POWER_RAM_POWER_S1RETENTION_Msk (0x1UL << POWER_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
+#define POWER_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S1RETENTION_On (1UL) /*!< On */
+
+/* Bit 16 : Keep retention on RAM section S0 when RAM section is in OFF */
+#define POWER_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
+#define POWER_RAM_POWER_S0RETENTION_Msk (0x1UL << POWER_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
+#define POWER_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S0RETENTION_On (1UL) /*!< On */
+
+/* Bit 1 : Keep RAM section S1 ON or OFF in System ON mode. */
+#define POWER_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
+#define POWER_RAM_POWER_S1POWER_Msk (0x1UL << POWER_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
+#define POWER_RAM_POWER_S1POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S1POWER_On (1UL) /*!< On */
+
+/* Bit 0 : Keep RAM section S0 ON or OFF in System ON mode. */
+#define POWER_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
+#define POWER_RAM_POWER_S0POWER_Msk (0x1UL << POWER_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
+#define POWER_RAM_POWER_S0POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */
+
+/* Register: POWER_RAM_POWERSET */
+/* Description: Description cluster[0]:  RAM0 power control set register */
+
+/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
+#define POWER_RAM_POWERSET_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
+#define POWER_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */
+
+/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
+#define POWER_RAM_POWERSET_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
+#define POWER_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */
+
+/* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
+#define POWER_RAM_POWERSET_S1POWER_Msk (0x1UL << POWER_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
+#define POWER_RAM_POWERSET_S1POWER_On (1UL) /*!< On */
+
+/* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
+#define POWER_RAM_POWERSET_S0POWER_Msk (0x1UL << POWER_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
+#define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */
+
+/* Register: POWER_RAM_POWERCLR */
+/* Description: Description cluster[0]:  RAM0 power control clear register */
+
+/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
+#define POWER_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
+#define POWER_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
+#define POWER_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
+#define POWER_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
+#define POWER_RAM_POWERCLR_S1POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
+#define POWER_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */
+
+/* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
+#define POWER_RAM_POWERCLR_S0POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
+#define POWER_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */
+
+
+/* Peripheral: PPI */
+/* Description: Programmable Peripheral Interconnect */
+
+/* Register: PPI_CHEN */
+/* Description: Channel enable register */
+
+/* Bit 31 : Enable or disable channel 31 */
+#define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHEN_CH31_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH31_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 30 : Enable or disable channel 30 */
+#define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHEN_CH30_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH30_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 29 : Enable or disable channel 29 */
+#define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHEN_CH29_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH29_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 28 : Enable or disable channel 28 */
+#define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHEN_CH28_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH28_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 27 : Enable or disable channel 27 */
+#define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHEN_CH27_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH27_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 26 : Enable or disable channel 26 */
+#define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHEN_CH26_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH26_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 25 : Enable or disable channel 25 */
+#define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHEN_CH25_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH25_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 24 : Enable or disable channel 24 */
+#define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHEN_CH24_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH24_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 23 : Enable or disable channel 23 */
+#define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHEN_CH23_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH23_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 22 : Enable or disable channel 22 */
+#define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHEN_CH22_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH22_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 21 : Enable or disable channel 21 */
+#define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHEN_CH21_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH21_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 20 : Enable or disable channel 20 */
+#define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHEN_CH20_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH20_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 19 : Enable or disable channel 19 */
+#define PPI_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */
+#define PPI_CHEN_CH19_Msk (0x1UL << PPI_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */
+#define PPI_CHEN_CH19_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH19_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 18 : Enable or disable channel 18 */
+#define PPI_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */
+#define PPI_CHEN_CH18_Msk (0x1UL << PPI_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */
+#define PPI_CHEN_CH18_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH18_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 17 : Enable or disable channel 17 */
+#define PPI_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */
+#define PPI_CHEN_CH17_Msk (0x1UL << PPI_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */
+#define PPI_CHEN_CH17_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH17_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 16 : Enable or disable channel 16 */
+#define PPI_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */
+#define PPI_CHEN_CH16_Msk (0x1UL << PPI_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */
+#define PPI_CHEN_CH16_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH16_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 15 : Enable or disable channel 15 */
+#define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHEN_CH15_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH15_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 14 : Enable or disable channel 14 */
+#define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHEN_CH14_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH14_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 13 : Enable or disable channel 13 */
+#define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHEN_CH13_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH13_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 12 : Enable or disable channel 12 */
+#define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHEN_CH12_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH12_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 11 : Enable or disable channel 11 */
+#define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHEN_CH11_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH11_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 10 : Enable or disable channel 10 */
+#define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHEN_CH10_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH10_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 9 : Enable or disable channel 9 */
+#define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHEN_CH9_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH9_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 8 : Enable or disable channel 8 */
+#define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHEN_CH8_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH8_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 7 : Enable or disable channel 7 */
+#define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHEN_CH7_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH7_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 6 : Enable or disable channel 6 */
+#define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHEN_CH6_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH6_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 5 : Enable or disable channel 5 */
+#define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHEN_CH5_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH5_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 4 : Enable or disable channel 4 */
+#define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHEN_CH4_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH4_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 3 : Enable or disable channel 3 */
+#define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHEN_CH3_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH3_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 2 : Enable or disable channel 2 */
+#define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHEN_CH2_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH2_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 1 : Enable or disable channel 1 */
+#define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHEN_CH1_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH1_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 0 : Enable or disable channel 0 */
+#define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHEN_CH0_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH0_Enabled (1UL) /*!< Enable channel */
+
+/* Register: PPI_CHENSET */
+/* Description: Channel enable set register */
+
+/* Bit 31 : Channel 31 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 30 : Channel 30 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 29 : Channel 29 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 28 : Channel 28 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 27 : Channel 27 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 26 : Channel 26 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 25 : Channel 25 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 24 : Channel 24 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 23 : Channel 23 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 22 : Channel 22 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 21 : Channel 21 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 20 : Channel 20 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 19 : Channel 19 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */
+#define PPI_CHENSET_CH19_Msk (0x1UL << PPI_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */
+#define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 18 : Channel 18 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */
+#define PPI_CHENSET_CH18_Msk (0x1UL << PPI_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */
+#define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 17 : Channel 17 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */
+#define PPI_CHENSET_CH17_Msk (0x1UL << PPI_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */
+#define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 16 : Channel 16 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */
+#define PPI_CHENSET_CH16_Msk (0x1UL << PPI_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */
+#define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 15 : Channel 15 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 14 : Channel 14 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 13 : Channel 13 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 12 : Channel 12 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 11 : Channel 11 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 10 : Channel 10 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 9 : Channel 9 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 8 : Channel 8 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 7 : Channel 7 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 6 : Channel 6 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 5 : Channel 5 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 4 : Channel 4 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 3 : Channel 3 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 2 : Channel 2 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 1 : Channel 1 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 0 : Channel 0 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */
+
+/* Register: PPI_CHENCLR */
+/* Description: Channel enable clear register */
+
+/* Bit 31 : Channel 31 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 30 : Channel 30 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 29 : Channel 29 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 28 : Channel 28 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 27 : Channel 27 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 26 : Channel 26 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 25 : Channel 25 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 24 : Channel 24 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 23 : Channel 23 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 22 : Channel 22 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 21 : Channel 21 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 20 : Channel 20 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 19 : Channel 19 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */
+#define PPI_CHENCLR_CH19_Msk (0x1UL << PPI_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */
+#define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 18 : Channel 18 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */
+#define PPI_CHENCLR_CH18_Msk (0x1UL << PPI_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */
+#define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 17 : Channel 17 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */
+#define PPI_CHENCLR_CH17_Msk (0x1UL << PPI_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */
+#define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 16 : Channel 16 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */
+#define PPI_CHENCLR_CH16_Msk (0x1UL << PPI_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */
+#define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 15 : Channel 15 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 14 : Channel 14 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 13 : Channel 13 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 12 : Channel 12 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 11 : Channel 11 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 10 : Channel 10 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 9 : Channel 9 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 8 : Channel 8 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 7 : Channel 7 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 6 : Channel 6 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 5 : Channel 5 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 4 : Channel 4 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 3 : Channel 3 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 2 : Channel 2 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 1 : Channel 1 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 0 : Channel 0 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */
+
+/* Register: PPI_CH_EEP */
+/* Description: Description cluster[0]:  Channel 0 event end-point */
+
+/* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */
+#define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */
+#define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */
+
+/* Register: PPI_CH_TEP */
+/* Description: Description cluster[0]:  Channel 0 task end-point */
+
+/* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */
+#define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
+#define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
+
+/* Register: PPI_CHG */
+/* Description: Description collection[0]:  Channel group 0 */
+
+/* Bit 31 : Include or exclude channel 31 */
+#define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHG_CH31_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH31_Included (1UL) /*!< Include */
+
+/* Bit 30 : Include or exclude channel 30 */
+#define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHG_CH30_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH30_Included (1UL) /*!< Include */
+
+/* Bit 29 : Include or exclude channel 29 */
+#define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHG_CH29_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH29_Included (1UL) /*!< Include */
+
+/* Bit 28 : Include or exclude channel 28 */
+#define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHG_CH28_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH28_Included (1UL) /*!< Include */
+
+/* Bit 27 : Include or exclude channel 27 */
+#define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHG_CH27_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH27_Included (1UL) /*!< Include */
+
+/* Bit 26 : Include or exclude channel 26 */
+#define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHG_CH26_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH26_Included (1UL) /*!< Include */
+
+/* Bit 25 : Include or exclude channel 25 */
+#define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHG_CH25_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH25_Included (1UL) /*!< Include */
+
+/* Bit 24 : Include or exclude channel 24 */
+#define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHG_CH24_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH24_Included (1UL) /*!< Include */
+
+/* Bit 23 : Include or exclude channel 23 */
+#define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHG_CH23_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH23_Included (1UL) /*!< Include */
+
+/* Bit 22 : Include or exclude channel 22 */
+#define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHG_CH22_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH22_Included (1UL) /*!< Include */
+
+/* Bit 21 : Include or exclude channel 21 */
+#define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHG_CH21_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH21_Included (1UL) /*!< Include */
+
+/* Bit 20 : Include or exclude channel 20 */
+#define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHG_CH20_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH20_Included (1UL) /*!< Include */
+
+/* Bit 19 : Include or exclude channel 19 */
+#define PPI_CHG_CH19_Pos (19UL) /*!< Position of CH19 field. */
+#define PPI_CHG_CH19_Msk (0x1UL << PPI_CHG_CH19_Pos) /*!< Bit mask of CH19 field. */
+#define PPI_CHG_CH19_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH19_Included (1UL) /*!< Include */
+
+/* Bit 18 : Include or exclude channel 18 */
+#define PPI_CHG_CH18_Pos (18UL) /*!< Position of CH18 field. */
+#define PPI_CHG_CH18_Msk (0x1UL << PPI_CHG_CH18_Pos) /*!< Bit mask of CH18 field. */
+#define PPI_CHG_CH18_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH18_Included (1UL) /*!< Include */
+
+/* Bit 17 : Include or exclude channel 17 */
+#define PPI_CHG_CH17_Pos (17UL) /*!< Position of CH17 field. */
+#define PPI_CHG_CH17_Msk (0x1UL << PPI_CHG_CH17_Pos) /*!< Bit mask of CH17 field. */
+#define PPI_CHG_CH17_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH17_Included (1UL) /*!< Include */
+
+/* Bit 16 : Include or exclude channel 16 */
+#define PPI_CHG_CH16_Pos (16UL) /*!< Position of CH16 field. */
+#define PPI_CHG_CH16_Msk (0x1UL << PPI_CHG_CH16_Pos) /*!< Bit mask of CH16 field. */
+#define PPI_CHG_CH16_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH16_Included (1UL) /*!< Include */
+
+/* Bit 15 : Include or exclude channel 15 */
+#define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHG_CH15_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH15_Included (1UL) /*!< Include */
+
+/* Bit 14 : Include or exclude channel 14 */
+#define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHG_CH14_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH14_Included (1UL) /*!< Include */
+
+/* Bit 13 : Include or exclude channel 13 */
+#define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHG_CH13_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH13_Included (1UL) /*!< Include */
+
+/* Bit 12 : Include or exclude channel 12 */
+#define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHG_CH12_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH12_Included (1UL) /*!< Include */
+
+/* Bit 11 : Include or exclude channel 11 */
+#define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHG_CH11_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH11_Included (1UL) /*!< Include */
+
+/* Bit 10 : Include or exclude channel 10 */
+#define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHG_CH10_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH10_Included (1UL) /*!< Include */
+
+/* Bit 9 : Include or exclude channel 9 */
+#define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHG_CH9_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH9_Included (1UL) /*!< Include */
+
+/* Bit 8 : Include or exclude channel 8 */
+#define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHG_CH8_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH8_Included (1UL) /*!< Include */
+
+/* Bit 7 : Include or exclude channel 7 */
+#define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHG_CH7_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH7_Included (1UL) /*!< Include */
+
+/* Bit 6 : Include or exclude channel 6 */
+#define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHG_CH6_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH6_Included (1UL) /*!< Include */
+
+/* Bit 5 : Include or exclude channel 5 */
+#define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHG_CH5_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH5_Included (1UL) /*!< Include */
+
+/* Bit 4 : Include or exclude channel 4 */
+#define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHG_CH4_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH4_Included (1UL) /*!< Include */
+
+/* Bit 3 : Include or exclude channel 3 */
+#define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHG_CH3_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH3_Included (1UL) /*!< Include */
+
+/* Bit 2 : Include or exclude channel 2 */
+#define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHG_CH2_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH2_Included (1UL) /*!< Include */
+
+/* Bit 1 : Include or exclude channel 1 */
+#define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHG_CH1_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH1_Included (1UL) /*!< Include */
+
+/* Bit 0 : Include or exclude channel 0 */
+#define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHG_CH0_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH0_Included (1UL) /*!< Include */
+
+/* Register: PPI_FORK_TEP */
+/* Description: Description cluster[0]:  Channel 0 task end-point */
+
+/* Bits 31..0 : Pointer to task register */
+#define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
+#define PPI_FORK_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_FORK_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
+
+
+/* Peripheral: PWM */
+/* Description: Pulse Width Modulation Unit 0 */
+
+/* Register: PWM_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 4 : Shortcut between LOOPSDONE event and STOP task */
+#define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */
+#define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */
+#define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between LOOPSDONE event and SEQSTART[1] task */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between LOOPSDONE event and SEQSTART[0] task */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between SEQEND[1] event and STOP task */
+#define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */
+#define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */
+#define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between SEQEND[0] event and STOP task */
+#define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */
+#define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */
+#define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: PWM_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 7 : Enable or disable interrupt for LOOPSDONE event */
+#define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
+#define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
+#define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable interrupt for PWMPERIODEND event */
+#define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
+#define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
+#define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable interrupt for SEQEND[1] event */
+#define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
+#define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
+#define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for SEQEND[0] event */
+#define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
+#define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
+#define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable interrupt for SEQSTARTED[1] event */
+#define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
+#define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
+#define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for SEQSTARTED[0] event */
+#define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
+#define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
+#define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for STOPPED event */
+#define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Register: PWM_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 7 : Write '1' to Enable interrupt for LOOPSDONE event */
+#define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
+#define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
+#define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for PWMPERIODEND event */
+#define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
+#define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
+#define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable interrupt for SEQEND[1] event */
+#define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
+#define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
+#define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for SEQEND[0] event */
+#define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
+#define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
+#define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for SEQSTARTED[1] event */
+#define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
+#define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
+#define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for SEQSTARTED[0] event */
+#define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
+#define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
+#define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
+#define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Register: PWM_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 7 : Write '1' to Disable interrupt for LOOPSDONE event */
+#define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
+#define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
+#define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for PWMPERIODEND event */
+#define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
+#define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
+#define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable interrupt for SEQEND[1] event */
+#define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
+#define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
+#define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for SEQEND[0] event */
+#define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
+#define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
+#define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for SEQSTARTED[1] event */
+#define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
+#define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
+#define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for SEQSTARTED[0] event */
+#define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
+#define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
+#define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
+#define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Register: PWM_ENABLE */
+/* Description: PWM module enable register */
+
+/* Bit 0 : Enable or disable PWM module */
+#define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define PWM_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled */
+#define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
+
+/* Register: PWM_MODE */
+/* Description: Selects operating mode of the wave counter */
+
+/* Bit 0 : Selects up or up and down as wave counter mode */
+#define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */
+#define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */
+#define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter - edge aligned PWM duty-cycle */
+#define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter - center aligned PWM duty cycle */
+
+/* Register: PWM_COUNTERTOP */
+/* Description: Value up to which the pulse generator counter counts */
+
+/* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used. */
+#define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */
+#define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */
+
+/* Register: PWM_PRESCALER */
+/* Description: Configuration for PWM_CLK */
+
+/* Bits 2..0 : Pre-scaler of PWM_CLK */
+#define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
+#define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
+#define PWM_PRESCALER_PRESCALER_DIV_1 (0UL) /*!< Divide by   1 (16MHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by   2 ( 8MHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by   4 ( 4MHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by   8 ( 2MHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_16 (4UL) /*!< Divide by  16 ( 1MHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_32 (5UL) /*!< Divide by  32 ( 500kHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_64 (6UL) /*!< Divide by  64 ( 250kHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_128 (7UL) /*!< Divide by 128 ( 125kHz) */
+
+/* Register: PWM_DECODER */
+/* Description: Configuration of the decoder */
+
+/* Bit 8 : Selects source for advancing the active sequence */
+#define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */
+#define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */
+#define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */
+#define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */
+
+/* Bits 2..0 : How a sequence is read from RAM and spread to the compare register */
+#define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */
+#define PWM_DECODER_LOAD_Msk (0x7UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */
+#define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */
+#define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */
+#define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */
+#define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */
+
+/* Register: PWM_LOOP */
+/* Description: Amount of playback of a loop */
+
+/* Bits 15..0 : Amount of playback of pattern cycles */
+#define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */
+#define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */
+#define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */
+
+/* Register: PWM_SEQ_PTR */
+/* Description: Description cluster[0]:  Beginning address in Data RAM of this sequence */
+
+/* Bits 31..0 : Beginning address in Data RAM of this sequence */
+#define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: PWM_SEQ_CNT */
+/* Description: Description cluster[0]:  Amount of values (duty cycles) in this sequence */
+
+/* Bits 14..0 : Amount of values (duty cycles) in this sequence */
+#define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */
+#define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */
+#define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */
+
+/* Register: PWM_SEQ_REFRESH */
+/* Description: Description cluster[0]:  Amount of additional PWM periods between samples loaded into compare register */
+
+/* Bits 23..0 : Amount of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) */
+#define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */
+#define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */
+#define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */
+
+/* Register: PWM_SEQ_ENDDELAY */
+/* Description: Description cluster[0]:  Time added after the sequence */
+
+/* Bits 23..0 : Time added after the sequence in PWM periods */
+#define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */
+#define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */
+
+/* Register: PWM_PSEL_OUT */
+/* Description: Description collection[0]:  Output pin select for PWM channel 0 */
+
+/* Bit 31 : Connection */
+#define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define PWM_PSEL_OUT_CONNECT_Connected (0UL) /*!< Connect */
+#define PWM_PSEL_OUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */
+
+
+/* Peripheral: QDEC */
+/* Description: Quadrature Decoder */
+
+/* Register: QDEC_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 6 : Shortcut between SAMPLERDY event and READCLRACC task */
+#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */
+#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */
+#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
+#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 5 : Shortcut between DBLRDY event and STOP task */
+#define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */
+#define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */
+#define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 4 : Shortcut between DBLRDY event and RDCLRDBL task */
+#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */
+#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */
+#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */
+#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between REPORTRDY event and STOP task */
+#define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */
+#define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */
+#define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between REPORTRDY event and RDCLRACC task */
+#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */
+#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */
+#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */
+#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between SAMPLERDY event and STOP task */
+#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */
+#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */
+#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task */
+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */
+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */
+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: QDEC_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 4 : Write '1' to Enable interrupt for STOPPED event */
+#define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
+#define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for DBLRDY event */
+#define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
+#define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
+#define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for ACCOF event */
+#define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
+#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
+#define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for REPORTRDY event */
+#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
+#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
+#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for SAMPLERDY event */
+#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
+#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
+#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable */
+
+/* Register: QDEC_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 4 : Write '1' to Disable interrupt for STOPPED event */
+#define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
+#define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for DBLRDY event */
+#define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
+#define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
+#define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for ACCOF event */
+#define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
+#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
+#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for REPORTRDY event */
+#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
+#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
+#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for SAMPLERDY event */
+#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
+#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
+#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable */
+
+/* Register: QDEC_ENABLE */
+/* Description: Enable the quadrature decoder */
+
+/* Bit 0 : Enable or disable the quadrature decoder */
+#define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
+
+/* Register: QDEC_LEDPOL */
+/* Description: LED output pin polarity */
+
+/* Bit 0 : LED output pin polarity */
+#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */
+#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */
+#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< Led active on output pin low */
+#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< Led active on output pin high */
+
+/* Register: QDEC_SAMPLEPER */
+/* Description: Sample period */
+
+/* Bits 3..0 : Sample period. The SAMPLE register will be updated for every new sample */
+#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */
+#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */
+#define QDEC_SAMPLEPER_SAMPLEPER_128us (0UL) /*!< 128 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_256us (1UL) /*!< 256 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_512us (2UL) /*!< 512 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_1024us (3UL) /*!< 1024 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_2048us (4UL) /*!< 2048 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_4096us (5UL) /*!< 4096 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_8192us (6UL) /*!< 8192 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_16384us (7UL) /*!< 16384 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_32ms (8UL) /*!< 32768 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_65ms (9UL) /*!< 65536 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_131ms (10UL) /*!< 131072 us */
+
+/* Register: QDEC_SAMPLE */
+/* Description: Motion sample value */
+
+/* Bits 31..0 : Last motion sample */
+#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */
+#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */
+
+/* Register: QDEC_REPORTPER */
+/* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */
+
+/* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated */
+#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */
+#define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */
+#define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples / report */
+#define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples / report */
+#define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples / report */
+#define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples / report */
+#define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples / report */
+#define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples / report */
+#define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples / report */
+#define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples / report */
+#define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample / report */
+
+/* Register: QDEC_ACC */
+/* Description: Register accumulating the valid transitions */
+
+/* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register */
+#define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */
+#define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */
+
+/* Register: QDEC_ACCREAD */
+/* Description: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */
+
+/* Bits 31..0 : Snapshot of the ACC register. */
+#define QDEC_ACCREAD_ACCREAD_Pos (0UL) /*!< Position of ACCREAD field. */
+#define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos) /*!< Bit mask of ACCREAD field. */
+
+/* Register: QDEC_PSEL_LED */
+/* Description: Pin select for LED signal */
+
+/* Bit 31 : Connection */
+#define QDEC_PSEL_LED_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define QDEC_PSEL_LED_CONNECT_Connected (0UL) /*!< Connect */
+#define QDEC_PSEL_LED_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define QDEC_PSEL_LED_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: QDEC_PSEL_A */
+/* Description: Pin select for A signal */
+
+/* Bit 31 : Connection */
+#define QDEC_PSEL_A_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define QDEC_PSEL_A_CONNECT_Connected (0UL) /*!< Connect */
+#define QDEC_PSEL_A_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define QDEC_PSEL_A_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: QDEC_PSEL_B */
+/* Description: Pin select for B signal */
+
+/* Bit 31 : Connection */
+#define QDEC_PSEL_B_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define QDEC_PSEL_B_CONNECT_Connected (0UL) /*!< Connect */
+#define QDEC_PSEL_B_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define QDEC_PSEL_B_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: QDEC_DBFEN */
+/* Description: Enable input debounce filters */
+
+/* Bit 0 : Enable input debounce filters */
+#define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */
+#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */
+#define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled */
+#define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled */
+
+/* Register: QDEC_LEDPRE */
+/* Description: Time period the LED is switched ON prior to sampling */
+
+/* Bits 8..0 : Period in us the LED is switched on prior to sampling */
+#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */
+#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */
+
+/* Register: QDEC_ACCDBL */
+/* Description: Register accumulating the number of detected double transitions */
+
+/* Bits 3..0 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */
+#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */
+#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */
+
+/* Register: QDEC_ACCDBLREAD */
+/* Description: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */
+
+/* Bits 3..0 : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. */
+#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */
+#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */
+
+
+/* Peripheral: RADIO */
+/* Description: 2.4 GHz Radio */
+
+/* Register: RADIO_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 6 : Shortcut between ADDRESS event and BCSTART task */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 5 : Shortcut between END event and START task */
+#define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */
+#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
+#define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between DISABLED event and RXEN task */
+#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */
+#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */
+#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between DISABLED event and TXEN task */
+#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
+#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */
+#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between END event and DISABLE task */
+#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */
+#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */
+#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between READY event and START task */
+#define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */
+#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */
+#define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: RADIO_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 13 : Write '1' to Enable interrupt for CRCERROR event */
+#define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
+#define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
+#define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */
+
+/* Bit 12 : Write '1' to Enable interrupt for CRCOK event */
+#define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
+#define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
+#define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */
+
+/* Bit 10 : Write '1' to Enable interrupt for BCMATCH event */
+#define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
+#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
+#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for RSSIEND event */
+#define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
+#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
+#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for DEVMISS event */
+#define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
+#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
+#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable interrupt for DEVMATCH event */
+#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
+#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
+#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for DISABLED event */
+#define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
+#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
+#define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for END event */
+#define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */
+#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for PAYLOAD event */
+#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
+#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
+#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for ADDRESS event */
+#define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
+#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for READY event */
+#define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
+#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */
+
+/* Register: RADIO_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 13 : Write '1' to Disable interrupt for CRCERROR event */
+#define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
+#define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
+#define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 12 : Write '1' to Disable interrupt for CRCOK event */
+#define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
+#define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
+#define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */
+
+/* Bit 10 : Write '1' to Disable interrupt for BCMATCH event */
+#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
+#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
+#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for RSSIEND event */
+#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
+#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
+#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for DEVMISS event */
+#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
+#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
+#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable interrupt for DEVMATCH event */
+#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
+#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
+#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for DISABLED event */
+#define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
+#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
+#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for END event */
+#define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */
+#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for PAYLOAD event */
+#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
+#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
+#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for ADDRESS event */
+#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
+#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for READY event */
+#define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
+#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */
+
+/* Register: RADIO_CRCSTATUS */
+/* Description: CRC status */
+
+/* Bit 0 : CRC status of packet received */
+#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */
+#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */
+#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error */
+#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok */
+
+/* Register: RADIO_RXMATCH */
+/* Description: Received address */
+
+/* Bits 2..0 : Received address */
+#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */
+#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */
+
+/* Register: RADIO_RXCRC */
+/* Description: CRC field of previously received packet */
+
+/* Bits 23..0 : CRC field of previously received packet */
+#define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */
+#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */
+
+/* Register: RADIO_DAI */
+/* Description: Device address match index */
+
+/* Bits 2..0 : Device address match index */
+#define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */
+#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */
+
+/* Register: RADIO_PACKETPTR */
+/* Description: Packet pointer */
+
+/* Bits 31..0 : Packet pointer */
+#define RADIO_PACKETPTR_PACKETPTR_Pos (0UL) /*!< Position of PACKETPTR field. */
+#define RADIO_PACKETPTR_PACKETPTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos) /*!< Bit mask of PACKETPTR field. */
+
+/* Register: RADIO_FREQUENCY */
+/* Description: Frequency */
+
+/* Bit 8 : Channel map selection. */
+#define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */
+#define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */
+#define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHZ .. 2500 MHz */
+#define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHZ .. 2460 MHz */
+
+/* Bits 6..0 : Radio channel frequency */
+#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+
+/* Register: RADIO_TXPOWER */
+/* Description: Output power */
+
+/* Bits 7..0 : RADIO output power. */
+#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */
+#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */
+#define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0 dBm */
+#define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x03UL) /*!< +3 dBm */
+#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< Deprecated enumerator -  -40 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */
+
+/* Register: RADIO_MODE */
+/* Description: Data rate and modulation */
+
+/* Bits 3..0 : Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation. */
+#define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbit/s Nordic proprietary radio mode */
+#define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbit/s Nordic proprietary radio mode */
+#define RADIO_MODE_MODE_Nrf_250Kbit (2UL) /*!< Deprecated enumerator -  250 kbit/s Nordic proprietary radio mode */
+#define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbit/s Bluetooth Low Energy */
+
+/* Register: RADIO_PCNF0 */
+/* Description: Packet configuration register 0 */
+
+/* Bit 24 : Length of preamble on air. Decision point: TASKS_START task */
+#define RADIO_PCNF0_PLEN_Pos (24UL) /*!< Position of PLEN field. */
+#define RADIO_PCNF0_PLEN_Msk (0x1UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field. */
+#define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */
+#define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */
+
+/* Bit 20 : Include or exclude S1 field in RAM */
+#define RADIO_PCNF0_S1INCL_Pos (20UL) /*!< Position of S1INCL field. */
+#define RADIO_PCNF0_S1INCL_Msk (0x1UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field. */
+#define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN &gt; 0 */
+#define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */
+
+/* Bits 19..16 : Length on air of S1 field in number of bits. */
+#define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */
+#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */
+
+/* Bit 8 : Length on air of S0 field in number of bytes. */
+#define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */
+#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */
+
+/* Bits 3..0 : Length on air of LENGTH field in number of bits. */
+#define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */
+#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */
+
+/* Register: RADIO_PCNF1 */
+/* Description: Packet configuration register 1 */
+
+/* Bit 25 : Enable or disable packet whitening */
+#define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */
+#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */
+#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */
+#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */
+
+/* Bit 24 : On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. */
+#define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */
+#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
+#define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least Significant bit on air first */
+#define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */
+
+/* Bits 18..16 : Base address length in number of bytes */
+#define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */
+#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */
+
+/* Bits 15..8 : Static length in number of bytes */
+#define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */
+#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */
+
+/* Bits 7..0 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. */
+#define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
+#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
+
+/* Register: RADIO_BASE0 */
+/* Description: Base address 0 */
+
+/* Bits 31..0 : Base address 0 */
+#define RADIO_BASE0_BASE0_Pos (0UL) /*!< Position of BASE0 field. */
+#define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field. */
+
+/* Register: RADIO_BASE1 */
+/* Description: Base address 1 */
+
+/* Bits 31..0 : Base address 1 */
+#define RADIO_BASE1_BASE1_Pos (0UL) /*!< Position of BASE1 field. */
+#define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field. */
+
+/* Register: RADIO_PREFIX0 */
+/* Description: Prefixes bytes for logical addresses 0-3 */
+
+/* Bits 31..24 : Address prefix 3. */
+#define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */
+#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */
+
+/* Bits 23..16 : Address prefix 2. */
+#define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */
+#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */
+
+/* Bits 15..8 : Address prefix 1. */
+#define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */
+#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */
+
+/* Bits 7..0 : Address prefix 0. */
+#define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */
+#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */
+
+/* Register: RADIO_PREFIX1 */
+/* Description: Prefixes bytes for logical addresses 4-7 */
+
+/* Bits 31..24 : Address prefix 7. */
+#define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */
+#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */
+
+/* Bits 23..16 : Address prefix 6. */
+#define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */
+#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */
+
+/* Bits 15..8 : Address prefix 5. */
+#define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */
+#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */
+
+/* Bits 7..0 : Address prefix 4. */
+#define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */
+#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */
+
+/* Register: RADIO_TXADDRESS */
+/* Description: Transmit address select */
+
+/* Bits 2..0 : Transmit address select */
+#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */
+#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */
+
+/* Register: RADIO_RXADDRESSES */
+/* Description: Receive address select */
+
+/* Bit 7 : Enable or disable reception on logical address 7. */
+#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */
+#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */
+#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable reception on logical address 6. */
+#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */
+#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */
+#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable reception on logical address 5. */
+#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */
+#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */
+#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable reception on logical address 4. */
+#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */
+#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */
+#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable reception on logical address 3. */
+#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */
+#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */
+#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable reception on logical address 2. */
+#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
+#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */
+#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable reception on logical address 1. */
+#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */
+#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */
+#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable reception on logical address 0. */
+#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */
+#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */
+#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */
+
+/* Register: RADIO_CRCCNF */
+/* Description: CRC configuration */
+
+/* Bit 8 : Include or exclude packet address field out of CRC calculation. */
+#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */
+#define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */
+#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< CRC calculation includes address field */
+#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */
+
+/* Bits 1..0 : CRC length in number of bytes. */
+#define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */
+#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */
+#define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */
+#define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */
+#define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */
+#define RADIO_CRCCNF_LEN_Three (3UL) /*!< CRC length is three bytes and CRC calculation is enabled */
+
+/* Register: RADIO_CRCPOLY */
+/* Description: CRC polynomial */
+
+/* Bits 23..0 : CRC polynomial */
+#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */
+#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */
+
+/* Register: RADIO_CRCINIT */
+/* Description: CRC initial value */
+
+/* Bits 23..0 : CRC initial value */
+#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */
+#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */
+
+/* Register: RADIO_TIFS */
+/* Description: Inter Frame Spacing in us */
+
+/* Bits 7..0 : Inter Frame Spacing in us */
+#define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */
+#define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */
+
+/* Register: RADIO_RSSISAMPLE */
+/* Description: RSSI sample */
+
+/* Bits 6..0 : RSSI sample */
+#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */
+#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */
+
+/* Register: RADIO_STATE */
+/* Description: Current radio state */
+
+/* Bits 3..0 : Current radio state */
+#define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */
+#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */
+#define RADIO_STATE_STATE_Disabled (0UL) /*!< RADIO is in the Disabled state */
+#define RADIO_STATE_STATE_RxRu (1UL) /*!< RADIO is in the RXRU state */
+#define RADIO_STATE_STATE_RxIdle (2UL) /*!< RADIO is in the RXIDLE state */
+#define RADIO_STATE_STATE_Rx (3UL) /*!< RADIO is in the RX state */
+#define RADIO_STATE_STATE_RxDisable (4UL) /*!< RADIO is in the RXDISABLED state */
+#define RADIO_STATE_STATE_TxRu (9UL) /*!< RADIO is in the TXRU state */
+#define RADIO_STATE_STATE_TxIdle (10UL) /*!< RADIO is in the TXIDLE state */
+#define RADIO_STATE_STATE_Tx (11UL) /*!< RADIO is in the TX state */
+#define RADIO_STATE_STATE_TxDisable (12UL) /*!< RADIO is in the TXDISABLED state */
+
+/* Register: RADIO_DATAWHITEIV */
+/* Description: Data whitening initial value */
+
+/* Bits 6..0 : Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. */
+#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */
+#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */
+
+/* Register: RADIO_BCC */
+/* Description: Bit counter compare */
+
+/* Bits 31..0 : Bit counter compare */
+#define RADIO_BCC_BCC_Pos (0UL) /*!< Position of BCC field. */
+#define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */
+
+/* Register: RADIO_DAB */
+/* Description: Description collection[0]:  Device address base segment 0 */
+
+/* Bits 31..0 : Device address base segment 0 */
+#define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */
+#define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */
+
+/* Register: RADIO_DAP */
+/* Description: Description collection[0]:  Device address prefix 0 */
+
+/* Bits 15..0 : Device address prefix 0 */
+#define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */
+#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */
+
+/* Register: RADIO_DACNF */
+/* Description: Device address match configuration */
+
+/* Bit 15 : TxAdd for device address 7 */
+#define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */
+#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */
+
+/* Bit 14 : TxAdd for device address 6 */
+#define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */
+#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */
+
+/* Bit 13 : TxAdd for device address 5 */
+#define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */
+#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */
+
+/* Bit 12 : TxAdd for device address 4 */
+#define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */
+#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */
+
+/* Bit 11 : TxAdd for device address 3 */
+#define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */
+#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */
+
+/* Bit 10 : TxAdd for device address 2 */
+#define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */
+#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */
+
+/* Bit 9 : TxAdd for device address 1 */
+#define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */
+#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */
+
+/* Bit 8 : TxAdd for device address 0 */
+#define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */
+#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */
+
+/* Bit 7 : Enable or disable device address matching using device address 7 */
+#define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */
+#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */
+#define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */
+
+/* Bit 6 : Enable or disable device address matching using device address 6 */
+#define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */
+#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */
+#define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */
+
+/* Bit 5 : Enable or disable device address matching using device address 5 */
+#define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */
+#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */
+#define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */
+
+/* Bit 4 : Enable or disable device address matching using device address 4 */
+#define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */
+#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */
+#define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */
+
+/* Bit 3 : Enable or disable device address matching using device address 3 */
+#define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */
+#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */
+#define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */
+
+/* Bit 2 : Enable or disable device address matching using device address 2 */
+#define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
+#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */
+#define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */
+
+/* Bit 1 : Enable or disable device address matching using device address 1 */
+#define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */
+#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */
+#define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */
+
+/* Bit 0 : Enable or disable device address matching using device address 0 */
+#define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */
+#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */
+#define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */
+
+/* Register: RADIO_MODECNF0 */
+/* Description: Radio mode configuration register 0 */
+
+/* Bits 9..8 : Default TX value */
+#define RADIO_MODECNF0_DTX_Pos (8UL) /*!< Position of DTX field. */
+#define RADIO_MODECNF0_DTX_Msk (0x3UL << RADIO_MODECNF0_DTX_Pos) /*!< Bit mask of DTX field. */
+#define RADIO_MODECNF0_DTX_B1 (0UL) /*!< Transmit '1' */
+#define RADIO_MODECNF0_DTX_B0 (1UL) /*!< Transmit '0' */
+#define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */
+
+/* Bit 0 : Radio ramp-up time */
+#define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */
+#define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */
+#define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN), compatible with firmware written for nRF51 */
+#define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST), see electrical specification for more information */
+
+/* Register: RADIO_POWER */
+/* Description: Peripheral power control */
+
+/* Bit 0 : Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. */
+#define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define RADIO_POWER_POWER_Disabled (0UL) /*!< Peripheral is powered off */
+#define RADIO_POWER_POWER_Enabled (1UL) /*!< Peripheral is powered on */
+
+
+/* Peripheral: RNG */
+/* Description: Random Number Generator */
+
+/* Register: RNG_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 0 : Shortcut between VALRDY event and STOP task */
+#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */
+#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */
+#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: RNG_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 0 : Write '1' to Enable interrupt for VALRDY event */
+#define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
+#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
+#define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */
+#define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */
+#define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */
+
+/* Register: RNG_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 0 : Write '1' to Disable interrupt for VALRDY event */
+#define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
+#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
+#define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */
+#define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */
+#define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */
+
+/* Register: RNG_CONFIG */
+/* Description: Configuration register */
+
+/* Bit 0 : Bias correction */
+#define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */
+#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */
+#define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Disabled */
+#define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */
+
+/* Register: RNG_VALUE */
+/* Description: Output random number */
+
+/* Bits 7..0 : Generated random number */
+#define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
+#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
+
+
+/* Peripheral: RTC */
+/* Description: Real time counter 0 */
+
+/* Register: RTC_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */
+#define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */
+#define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */
+#define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
+
+/* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */
+#define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for OVRFLW event */
+#define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for TICK event */
+#define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */
+
+/* Register: RTC_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */
+#define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */
+#define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */
+#define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
+
+/* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */
+#define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for OVRFLW event */
+#define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for TICK event */
+#define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */
+
+/* Register: RTC_EVTEN */
+/* Description: Enable or disable event routing */
+
+/* Bit 19 : Enable or disable event routing for COMPARE[3] event */
+#define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */
+
+/* Bit 18 : Enable or disable event routing for COMPARE[2] event */
+#define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */
+
+/* Bit 17 : Enable or disable event routing for COMPARE[1] event */
+#define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */
+
+/* Bit 16 : Enable or disable event routing for COMPARE[0] event */
+#define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable event routing for OVRFLW event */
+#define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable event routing for TICK event */
+#define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */
+
+/* Register: RTC_EVTENSET */
+/* Description: Enable event routing */
+
+/* Bit 19 : Write '1' to Enable event routing for COMPARE[3] event */
+#define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to Enable event routing for COMPARE[2] event */
+#define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to Enable event routing for COMPARE[1] event */
+#define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */
+
+/* Bit 16 : Write '1' to Enable event routing for COMPARE[0] event */
+#define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable event routing for OVRFLW event */
+#define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable event routing for TICK event */
+#define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */
+
+/* Register: RTC_EVTENCLR */
+/* Description: Disable event routing */
+
+/* Bit 19 : Write '1' to Disable event routing for COMPARE[3] event */
+#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to Disable event routing for COMPARE[2] event */
+#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to Disable event routing for COMPARE[1] event */
+#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
+
+/* Bit 16 : Write '1' to Disable event routing for COMPARE[0] event */
+#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable event routing for OVRFLW event */
+#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable event routing for TICK event */
+#define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */
+
+/* Register: RTC_COUNTER */
+/* Description: Current COUNTER value */
+
+/* Bits 23..0 : Counter value */
+#define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
+#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
+
+/* Register: RTC_PRESCALER */
+/* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped */
+
+/* Bits 11..0 : Prescaler value */
+#define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
+#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
+
+/* Register: RTC_CC */
+/* Description: Description collection[0]:  Compare register 0 */
+
+/* Bits 23..0 : Compare value */
+#define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
+#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
+
+
+/* Peripheral: SAADC */
+/* Description: Analog to Digital Converter */
+
+/* Register: SAADC_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 21 : Enable or disable interrupt for CH[7].LIMITL event */
+#define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
+#define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
+#define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 20 : Enable or disable interrupt for CH[7].LIMITH event */
+#define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
+#define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
+#define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 19 : Enable or disable interrupt for CH[6].LIMITL event */
+#define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
+#define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
+#define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 18 : Enable or disable interrupt for CH[6].LIMITH event */
+#define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
+#define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
+#define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 17 : Enable or disable interrupt for CH[5].LIMITL event */
+#define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
+#define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
+#define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 16 : Enable or disable interrupt for CH[5].LIMITH event */
+#define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
+#define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
+#define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 15 : Enable or disable interrupt for CH[4].LIMITL event */
+#define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
+#define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
+#define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 14 : Enable or disable interrupt for CH[4].LIMITH event */
+#define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
+#define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
+#define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 13 : Enable or disable interrupt for CH[3].LIMITL event */
+#define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
+#define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
+#define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 12 : Enable or disable interrupt for CH[3].LIMITH event */
+#define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
+#define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
+#define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 11 : Enable or disable interrupt for CH[2].LIMITL event */
+#define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
+#define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
+#define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 10 : Enable or disable interrupt for CH[2].LIMITH event */
+#define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
+#define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
+#define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for CH[1].LIMITL event */
+#define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
+#define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
+#define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 8 : Enable or disable interrupt for CH[1].LIMITH event */
+#define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
+#define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
+#define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable interrupt for CH[0].LIMITL event */
+#define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
+#define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
+#define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable interrupt for CH[0].LIMITH event */
+#define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
+#define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
+#define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable interrupt for STOPPED event */
+#define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
+#define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for CALIBRATEDONE event */
+#define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
+#define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
+#define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable interrupt for RESULTDONE event */
+#define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
+#define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
+#define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for DONE event */
+#define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */
+#define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */
+#define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for END event */
+#define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */
+#define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */
+#define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for STARTED event */
+#define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */
+
+/* Register: SAADC_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 21 : Write '1' to Enable interrupt for CH[7].LIMITL event */
+#define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
+#define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
+#define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to Enable interrupt for CH[7].LIMITH event */
+#define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
+#define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
+#define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to Enable interrupt for CH[6].LIMITL event */
+#define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
+#define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
+#define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to Enable interrupt for CH[6].LIMITH event */
+#define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
+#define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
+#define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to Enable interrupt for CH[5].LIMITL event */
+#define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
+#define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
+#define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 16 : Write '1' to Enable interrupt for CH[5].LIMITH event */
+#define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
+#define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
+#define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 15 : Write '1' to Enable interrupt for CH[4].LIMITL event */
+#define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
+#define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
+#define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 14 : Write '1' to Enable interrupt for CH[4].LIMITH event */
+#define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
+#define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
+#define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 13 : Write '1' to Enable interrupt for CH[3].LIMITL event */
+#define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
+#define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
+#define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 12 : Write '1' to Enable interrupt for CH[3].LIMITH event */
+#define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
+#define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
+#define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 11 : Write '1' to Enable interrupt for CH[2].LIMITL event */
+#define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
+#define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
+#define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 10 : Write '1' to Enable interrupt for CH[2].LIMITH event */
+#define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
+#define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
+#define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to Enable interrupt for CH[1].LIMITL event */
+#define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
+#define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
+#define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 8 : Write '1' to Enable interrupt for CH[1].LIMITH event */
+#define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
+#define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
+#define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for CH[0].LIMITL event */
+#define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
+#define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
+#define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for CH[0].LIMITH event */
+#define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
+#define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
+#define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable interrupt for STOPPED event */
+#define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
+#define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for CALIBRATEDONE event */
+#define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
+#define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
+#define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for RESULTDONE event */
+#define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
+#define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
+#define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for DONE event */
+#define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */
+#define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
+#define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for END event */
+#define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */
+#define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for STARTED event */
+#define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */
+
+/* Register: SAADC_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 21 : Write '1' to Disable interrupt for CH[7].LIMITL event */
+#define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
+#define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
+#define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to Disable interrupt for CH[7].LIMITH event */
+#define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
+#define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
+#define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to Disable interrupt for CH[6].LIMITL event */
+#define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
+#define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
+#define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to Disable interrupt for CH[6].LIMITH event */
+#define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
+#define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
+#define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to Disable interrupt for CH[5].LIMITL event */
+#define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
+#define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
+#define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 16 : Write '1' to Disable interrupt for CH[5].LIMITH event */
+#define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
+#define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
+#define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 15 : Write '1' to Disable interrupt for CH[4].LIMITL event */
+#define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
+#define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
+#define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 14 : Write '1' to Disable interrupt for CH[4].LIMITH event */
+#define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
+#define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
+#define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 13 : Write '1' to Disable interrupt for CH[3].LIMITL event */
+#define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
+#define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
+#define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 12 : Write '1' to Disable interrupt for CH[3].LIMITH event */
+#define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
+#define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
+#define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 11 : Write '1' to Disable interrupt for CH[2].LIMITL event */
+#define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
+#define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
+#define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 10 : Write '1' to Disable interrupt for CH[2].LIMITH event */
+#define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
+#define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
+#define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to Disable interrupt for CH[1].LIMITL event */
+#define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
+#define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
+#define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 8 : Write '1' to Disable interrupt for CH[1].LIMITH event */
+#define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
+#define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
+#define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for CH[0].LIMITL event */
+#define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
+#define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
+#define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for CH[0].LIMITH event */
+#define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
+#define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
+#define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable interrupt for STOPPED event */
+#define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
+#define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for CALIBRATEDONE event */
+#define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
+#define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
+#define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for RESULTDONE event */
+#define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
+#define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
+#define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for DONE event */
+#define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */
+#define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
+#define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for END event */
+#define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
+#define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for STARTED event */
+#define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
+
+/* Register: SAADC_STATUS */
+/* Description: Status */
+
+/* Bit 0 : Status */
+#define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
+#define SAADC_STATUS_STATUS_Ready (0UL) /*!< ADC is ready. No on-going conversion. */
+#define SAADC_STATUS_STATUS_Busy (1UL) /*!< ADC is busy. Conversion in progress. */
+
+/* Register: SAADC_ENABLE */
+/* Description: Enable or disable ADC */
+
+/* Bit 0 : Enable or disable ADC */
+#define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable ADC */
+#define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */
+
+/* Register: SAADC_CH_PSELP */
+/* Description: Description cluster[0]:  Input positive pin selection for CH[0] */
+
+/* Bits 4..0 : Analog positive input channel */
+#define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */
+#define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */
+#define SAADC_CH_PSELP_PSELP_NC (0UL) /*!< Not connected */
+#define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL) /*!< AIN0 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput2 (3UL) /*!< AIN2 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput3 (4UL) /*!< AIN3 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput4 (5UL) /*!< AIN4 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL) /*!< AIN5 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL) /*!< AIN6 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL) /*!< AIN7 */
+#define SAADC_CH_PSELP_PSELP_VDD (9UL) /*!< VDD */
+
+/* Register: SAADC_CH_PSELN */
+/* Description: Description cluster[0]:  Input negative pin selection for CH[0] */
+
+/* Bits 4..0 : Analog negative input, enables differential channel */
+#define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */
+#define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */
+#define SAADC_CH_PSELN_PSELN_NC (0UL) /*!< Not connected */
+#define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL) /*!< AIN0 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput2 (3UL) /*!< AIN2 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput3 (4UL) /*!< AIN3 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput4 (5UL) /*!< AIN4 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL) /*!< AIN5 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL) /*!< AIN6 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL) /*!< AIN7 */
+#define SAADC_CH_PSELN_PSELN_VDD (9UL) /*!< VDD */
+
+/* Register: SAADC_CH_CONFIG */
+/* Description: Description cluster[0]:  Input configuration for CH[0] */
+
+/* Bit 24 : Enable burst mode */
+#define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */
+#define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */
+#define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */
+#define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */
+
+/* Bit 20 : Enable differential mode */
+#define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */
+#define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
+#define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to GND */
+#define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */
+
+/* Bits 18..16 : Acquisition time, the time the ADC uses to sample the input voltage */
+#define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */
+#define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */
+#define SAADC_CH_CONFIG_TACQ_3us (0UL) /*!< 3 us */
+#define SAADC_CH_CONFIG_TACQ_5us (1UL) /*!< 5 us */
+#define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */
+#define SAADC_CH_CONFIG_TACQ_15us (3UL) /*!< 15 us */
+#define SAADC_CH_CONFIG_TACQ_20us (4UL) /*!< 20 us */
+#define SAADC_CH_CONFIG_TACQ_40us (5UL) /*!< 40 us */
+
+/* Bit 12 : Reference control */
+#define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */
+#define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
+#define SAADC_CH_CONFIG_REFSEL_Internal (0UL) /*!< Internal reference (0.6 V) */
+#define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD/4 as reference */
+
+/* Bits 10..8 : Gain control */
+#define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */
+#define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */
+#define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) /*!< 1/6 */
+#define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL) /*!< 1/5 */
+#define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */
+#define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL) /*!< 1/3 */
+#define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */
+#define SAADC_CH_CONFIG_GAIN_Gain1 (5UL) /*!< 1 */
+#define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */
+#define SAADC_CH_CONFIG_GAIN_Gain4 (7UL) /*!< 4 */
+
+/* Bits 5..4 : Negative channel resistor control */
+#define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */
+#define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */
+#define SAADC_CH_CONFIG_RESN_Bypass (0UL) /*!< Bypass resistor ladder */
+#define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */
+#define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */
+#define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD/2 */
+
+/* Bits 1..0 : Positive channel resistor control */
+#define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */
+#define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */
+#define SAADC_CH_CONFIG_RESP_Bypass (0UL) /*!< Bypass resistor ladder */
+#define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */
+#define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */
+#define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */
+
+/* Register: SAADC_CH_LIMIT */
+/* Description: Description cluster[0]:  High/low limits for event monitoring a channel */
+
+/* Bits 31..16 : High level limit */
+#define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */
+#define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */
+
+/* Bits 15..0 : Low level limit */
+#define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */
+#define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */
+
+/* Register: SAADC_RESOLUTION */
+/* Description: Resolution configuration */
+
+/* Bits 2..0 : Set the resolution */
+#define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */
+#define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */
+#define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bit */
+#define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bit */
+#define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bit */
+#define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bit */
+
+/* Register: SAADC_OVERSAMPLE */
+/* Description: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */
+
+/* Bits 3..0 : Oversample control */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0UL) /*!< Bypass oversampling */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (3UL) /*!< Oversample 8x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (4UL) /*!< Oversample 16x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (5UL) /*!< Oversample 32x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (6UL) /*!< Oversample 64x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (7UL) /*!< Oversample 128x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (8UL) /*!< Oversample 256x */
+
+/* Register: SAADC_SAMPLERATE */
+/* Description: Controls normal or continuous sample rate */
+
+/* Bit 12 : Select mode for sample rate control */
+#define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */
+#define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define SAADC_SAMPLERATE_MODE_Task (0UL) /*!< Rate is controlled from SAMPLE task */
+#define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */
+
+/* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */
+#define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */
+#define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */
+
+/* Register: SAADC_RESULT_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SAADC_RESULT_MAXCNT */
+/* Description: Maximum number of buffer words to transfer */
+
+/* Bits 14..0 : Maximum number of buffer words to transfer */
+#define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SAADC_RESULT_AMOUNT */
+/* Description: Number of buffer words transferred since last START */
+
+/* Bits 14..0 : Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. */
+#define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+
+/* Peripheral: SPI */
+/* Description: Serial Peripheral Interface 0 */
+
+/* Register: SPI_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 2 : Write '1' to Enable interrupt for READY event */
+#define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */
+#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
+#define SPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
+#define SPI_INTENSET_READY_Set (1UL) /*!< Enable */
+
+/* Register: SPI_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 2 : Write '1' to Disable interrupt for READY event */
+#define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */
+#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
+#define SPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
+#define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable */
+
+/* Register: SPI_ENABLE */
+/* Description: Enable SPI */
+
+/* Bits 3..0 : Enable or disable SPI */
+#define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define SPI_ENABLE_ENABLE_Msk (0xFUL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define SPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI */
+#define SPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SPI */
+
+/* Register: SPI_PSEL_SCK */
+/* Description: Pin select for SCK */
+
+/* Bits 31..0 : Pin number configuration for SPI SCK signal */
+#define SPI_PSEL_SCK_PSELSCK_Pos (0UL) /*!< Position of PSELSCK field. */
+#define SPI_PSEL_SCK_PSELSCK_Msk (0xFFFFFFFFUL << SPI_PSEL_SCK_PSELSCK_Pos) /*!< Bit mask of PSELSCK field. */
+#define SPI_PSEL_SCK_PSELSCK_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
+
+/* Register: SPI_PSEL_MOSI */
+/* Description: Pin select for MOSI */
+
+/* Bits 31..0 : Pin number configuration for SPI MOSI signal */
+#define SPI_PSEL_MOSI_PSELMOSI_Pos (0UL) /*!< Position of PSELMOSI field. */
+#define SPI_PSEL_MOSI_PSELMOSI_Msk (0xFFFFFFFFUL << SPI_PSEL_MOSI_PSELMOSI_Pos) /*!< Bit mask of PSELMOSI field. */
+#define SPI_PSEL_MOSI_PSELMOSI_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
+
+/* Register: SPI_PSEL_MISO */
+/* Description: Pin select for MISO */
+
+/* Bits 31..0 : Pin number configuration for SPI MISO signal */
+#define SPI_PSEL_MISO_PSELMISO_Pos (0UL) /*!< Position of PSELMISO field. */
+#define SPI_PSEL_MISO_PSELMISO_Msk (0xFFFFFFFFUL << SPI_PSEL_MISO_PSELMISO_Pos) /*!< Bit mask of PSELMISO field. */
+#define SPI_PSEL_MISO_PSELMISO_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
+
+/* Register: SPI_RXD */
+/* Description: RXD register */
+
+/* Bits 7..0 : RX data received. Double buffered */
+#define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
+#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
+
+/* Register: SPI_TXD */
+/* Description: TXD register */
+
+/* Bits 7..0 : TX data to send. Double buffered */
+#define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
+#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
+
+/* Register: SPI_FREQUENCY */
+/* Description: SPI frequency */
+
+/* Bits 31..0 : SPI master data rate */
+#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
+#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
+#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
+#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
+#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
+#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
+#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
+
+/* Register: SPI_CONFIG */
+/* Description: Configuration register */
+
+/* Bit 2 : Serial clock (SCK) polarity */
+#define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
+#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
+#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
+#define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
+
+/* Bit 1 : Serial clock (SCK) phase */
+#define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
+#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
+#define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
+#define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
+
+/* Bit 0 : Bit order */
+#define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
+#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
+#define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
+#define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
+
+
+/* Peripheral: SPIM */
+/* Description: Serial Peripheral Interface Master with EasyDMA 0 */
+
+/* Register: SPIM_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 17 : Shortcut between END event and START task */
+#define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */
+#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
+#define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
+#define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: SPIM_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 19 : Write '1' to Enable interrupt for STARTED event */
+#define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */
+#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */
+
+/* Bit 8 : Write '1' to Enable interrupt for ENDTX event */
+#define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for END event */
+#define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */
+#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
+#define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
+#define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Register: SPIM_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 19 : Write '1' to Disable interrupt for STARTED event */
+#define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */
+#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 8 : Write '1' to Disable interrupt for ENDTX event */
+#define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for END event */
+#define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */
+#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
+#define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
+#define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Register: SPIM_ENABLE */
+/* Description: Enable SPIM */
+
+/* Bits 3..0 : Enable or disable SPIM */
+#define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */
+#define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */
+
+/* Register: SPIM_PSEL_SCK */
+/* Description: Pin select for SCK */
+
+/* Bit 31 : Connection */
+#define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIM_PSEL_MOSI */
+/* Description: Pin select for MOSI signal */
+
+/* Bit 31 : Connection */
+#define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIM_PSEL_MISO */
+/* Description: Pin select for MISO signal */
+
+/* Bit 31 : Connection */
+#define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIM_FREQUENCY */
+/* Description: SPI frequency */
+
+/* Bits 31..0 : SPI master data rate */
+#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
+#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
+#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
+#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
+#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
+#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
+#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
+
+/* Register: SPIM_RXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SPIM_RXD_MAXCNT */
+/* Description: Maximum number of bytes in receive buffer */
+
+/* Bits 7..0 : Maximum number of bytes in receive buffer */
+#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SPIM_RXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 7..0 : Number of bytes transferred in the last transaction */
+#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: SPIM_RXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 2..0 : List type */
+#define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define SPIM_RXD_LIST_LIST_Msk (0x7UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: SPIM_TXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SPIM_TXD_MAXCNT */
+/* Description: Maximum number of bytes in transmit buffer */
+
+/* Bits 7..0 : Maximum number of bytes in transmit buffer */
+#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SPIM_TXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 7..0 : Number of bytes transferred in the last transaction */
+#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: SPIM_TXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 2..0 : List type */
+#define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define SPIM_TXD_LIST_LIST_Msk (0x7UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: SPIM_CONFIG */
+/* Description: Configuration register */
+
+/* Bit 2 : Serial clock (SCK) polarity */
+#define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
+#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
+#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
+#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
+
+/* Bit 1 : Serial clock (SCK) phase */
+#define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
+#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
+#define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
+#define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
+
+/* Bit 0 : Bit order */
+#define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
+#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
+#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
+#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
+
+/* Register: SPIM_ORC */
+/* Description: Over-read character. Character clocked out in case and over-read of the TXD buffer. */
+
+/* Bits 7..0 : Over-read character. Character clocked out in case and over-read of the TXD buffer. */
+#define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
+#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
+
+
+/* Peripheral: SPIS */
+/* Description: SPI Slave 0 */
+
+/* Register: SPIS_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 2 : Shortcut between END event and ACQUIRE task */
+#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
+#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
+#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */
+#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: SPIS_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 10 : Write '1' to Enable interrupt for ACQUIRED event */
+#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
+#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
+#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
+#define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for END event */
+#define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
+#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Register: SPIS_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 10 : Write '1' to Disable interrupt for ACQUIRED event */
+#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
+#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
+#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
+#define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for END event */
+#define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
+#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Register: SPIS_SEMSTAT */
+/* Description: Semaphore status register */
+
+/* Bits 1..0 : Semaphore status */
+#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
+#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
+#define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */
+#define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */
+#define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */
+#define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */
+
+/* Register: SPIS_STATUS */
+/* Description: Status from last transaction */
+
+/* Bit 1 : RX buffer overflow detected, and prevented */
+#define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
+#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
+#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */
+#define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */
+#define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */
+
+/* Bit 0 : TX buffer over-read detected, and prevented */
+#define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
+#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
+#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */
+#define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */
+#define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */
+
+/* Register: SPIS_ENABLE */
+/* Description: Enable SPI slave */
+
+/* Bits 3..0 : Enable or disable SPI slave */
+#define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */
+#define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */
+
+/* Register: SPIS_PSEL_SCK */
+/* Description: Pin select for SCK */
+
+/* Bit 31 : Connection */
+#define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIS_PSEL_MISO */
+/* Description: Pin select for MISO signal */
+
+/* Bit 31 : Connection */
+#define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIS_PSEL_MOSI */
+/* Description: Pin select for MOSI signal */
+
+/* Bit 31 : Connection */
+#define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIS_PSEL_CSN */
+/* Description: Pin select for CSN signal */
+
+/* Bit 31 : Connection */
+#define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIS_RXD_PTR */
+/* Description: RXD data pointer */
+
+/* Bits 31..0 : RXD data pointer */
+#define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SPIS_RXD_MAXCNT */
+/* Description: Maximum number of bytes in receive buffer */
+
+/* Bits 7..0 : Maximum number of bytes in receive buffer */
+#define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SPIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SPIS_RXD_AMOUNT */
+/* Description: Number of bytes received in last granted transaction */
+
+/* Bits 7..0 : Number of bytes received in the last granted transaction */
+#define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SPIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: SPIS_TXD_PTR */
+/* Description: TXD data pointer */
+
+/* Bits 31..0 : TXD data pointer */
+#define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SPIS_TXD_MAXCNT */
+/* Description: Maximum number of bytes in transmit buffer */
+
+/* Bits 7..0 : Maximum number of bytes in transmit buffer */
+#define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SPIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SPIS_TXD_AMOUNT */
+/* Description: Number of bytes transmitted in last granted transaction */
+
+/* Bits 7..0 : Number of bytes transmitted in last granted transaction */
+#define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SPIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: SPIS_CONFIG */
+/* Description: Configuration register */
+
+/* Bit 2 : Serial clock (SCK) polarity */
+#define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
+#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
+#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
+#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
+
+/* Bit 1 : Serial clock (SCK) phase */
+#define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
+#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
+#define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
+#define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
+
+/* Bit 0 : Bit order */
+#define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
+#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
+#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
+#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
+
+/* Register: SPIS_DEF */
+/* Description: Default character. Character clocked out in case of an ignored transaction. */
+
+/* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */
+#define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
+#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
+
+/* Register: SPIS_ORC */
+/* Description: Over-read character */
+
+/* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */
+#define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
+#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
+
+
+/* Peripheral: TEMP */
+/* Description: Temperature Sensor */
+
+/* Register: TEMP_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 0 : Write '1' to Enable interrupt for DATARDY event */
+#define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
+#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
+#define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */
+#define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */
+#define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */
+
+/* Register: TEMP_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 0 : Write '1' to Disable interrupt for DATARDY event */
+#define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
+#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
+#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */
+#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */
+#define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */
+
+/* Register: TEMP_TEMP */
+/* Description: Temperature in degC (0.25deg steps) */
+
+/* Bits 31..0 : Temperature in degC (0.25deg steps) */
+#define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */
+#define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */
+
+/* Register: TEMP_A0 */
+/* Description: Slope of 1st piece wise linear function */
+
+/* Bits 11..0 : Slope of 1st piece wise linear function */
+#define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */
+#define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */
+
+/* Register: TEMP_A1 */
+/* Description: Slope of 2nd piece wise linear function */
+
+/* Bits 11..0 : Slope of 2nd piece wise linear function */
+#define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */
+#define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */
+
+/* Register: TEMP_A2 */
+/* Description: Slope of 3rd piece wise linear function */
+
+/* Bits 11..0 : Slope of 3rd piece wise linear function */
+#define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */
+#define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */
+
+/* Register: TEMP_A3 */
+/* Description: Slope of 4th piece wise linear function */
+
+/* Bits 11..0 : Slope of 4th piece wise linear function */
+#define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */
+#define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */
+
+/* Register: TEMP_A4 */
+/* Description: Slope of 5th piece wise linear function */
+
+/* Bits 11..0 : Slope of 5th piece wise linear function */
+#define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */
+#define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */
+
+/* Register: TEMP_A5 */
+/* Description: Slope of 6th piece wise linear function */
+
+/* Bits 11..0 : Slope of 6th piece wise linear function */
+#define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */
+#define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */
+
+/* Register: TEMP_B0 */
+/* Description: y-intercept of 1st piece wise linear function */
+
+/* Bits 13..0 : y-intercept of 1st piece wise linear function */
+#define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */
+#define TEMP_B0_B0_Msk (0x3FFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */
+
+/* Register: TEMP_B1 */
+/* Description: y-intercept of 2nd piece wise linear function */
+
+/* Bits 13..0 : y-intercept of 2nd piece wise linear function */
+#define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */
+#define TEMP_B1_B1_Msk (0x3FFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */
+
+/* Register: TEMP_B2 */
+/* Description: y-intercept of 3rd piece wise linear function */
+
+/* Bits 13..0 : y-intercept of 3rd piece wise linear function */
+#define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */
+#define TEMP_B2_B2_Msk (0x3FFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */
+
+/* Register: TEMP_B3 */
+/* Description: y-intercept of 4th piece wise linear function */
+
+/* Bits 13..0 : y-intercept of 4th piece wise linear function */
+#define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */
+#define TEMP_B3_B3_Msk (0x3FFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */
+
+/* Register: TEMP_B4 */
+/* Description: y-intercept of 5th piece wise linear function */
+
+/* Bits 13..0 : y-intercept of 5th piece wise linear function */
+#define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */
+#define TEMP_B4_B4_Msk (0x3FFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */
+
+/* Register: TEMP_B5 */
+/* Description: y-intercept of 6th piece wise linear function */
+
+/* Bits 13..0 : y-intercept of 6th piece wise linear function */
+#define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */
+#define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */
+
+/* Register: TEMP_T0 */
+/* Description: End point of 1st piece wise linear function */
+
+/* Bits 7..0 : End point of 1st piece wise linear function */
+#define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */
+#define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */
+
+/* Register: TEMP_T1 */
+/* Description: End point of 2nd piece wise linear function */
+
+/* Bits 7..0 : End point of 2nd piece wise linear function */
+#define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */
+#define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */
+
+/* Register: TEMP_T2 */
+/* Description: End point of 3rd piece wise linear function */
+
+/* Bits 7..0 : End point of 3rd piece wise linear function */
+#define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */
+#define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */
+
+/* Register: TEMP_T3 */
+/* Description: End point of 4th piece wise linear function */
+
+/* Bits 7..0 : End point of 4th piece wise linear function */
+#define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */
+#define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */
+
+/* Register: TEMP_T4 */
+/* Description: End point of 5th piece wise linear function */
+
+/* Bits 7..0 : End point of 5th piece wise linear function */
+#define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */
+#define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */
+
+
+/* Peripheral: TIMER */
+/* Description: Timer/Counter 0 */
+
+/* Register: TIMER_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 13 : Shortcut between COMPARE[5] event and STOP task */
+#define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */
+#define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */
+#define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 12 : Shortcut between COMPARE[4] event and STOP task */
+#define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */
+#define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */
+#define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 11 : Shortcut between COMPARE[3] event and STOP task */
+#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
+#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
+#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 10 : Shortcut between COMPARE[2] event and STOP task */
+#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
+#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
+#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 9 : Shortcut between COMPARE[1] event and STOP task */
+#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
+#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
+#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 8 : Shortcut between COMPARE[0] event and STOP task */
+#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
+#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
+#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 5 : Shortcut between COMPARE[5] event and CLEAR task */
+#define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */
+#define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */
+#define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 4 : Shortcut between COMPARE[4] event and CLEAR task */
+#define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */
+#define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */
+#define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between COMPARE[3] event and CLEAR task */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between COMPARE[2] event and CLEAR task */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between COMPARE[1] event and CLEAR task */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between COMPARE[0] event and CLEAR task */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: TIMER_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 21 : Write '1' to Enable interrupt for COMPARE[5] event */
+#define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
+#define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
+#define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to Enable interrupt for COMPARE[4] event */
+#define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
+#define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
+#define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */
+#define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */
+#define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */
+#define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
+
+/* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */
+#define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
+
+/* Register: TIMER_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 21 : Write '1' to Disable interrupt for COMPARE[5] event */
+#define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
+#define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
+#define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to Disable interrupt for COMPARE[4] event */
+#define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
+#define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
+#define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */
+#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */
+#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */
+#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
+
+/* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */
+#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
+
+/* Register: TIMER_MODE */
+/* Description: Timer mode selection */
+
+/* Bits 1..0 : Timer mode */
+#define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */
+#define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator -  Select Counter mode */
+#define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */
+
+/* Register: TIMER_BITMODE */
+/* Description: Configure the number of bits used by the TIMER */
+
+/* Bits 1..0 : Timer bit width */
+#define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
+#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
+#define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */
+#define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */
+#define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */
+#define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */
+
+/* Register: TIMER_PRESCALER */
+/* Description: Timer prescaler register */
+
+/* Bits 3..0 : Prescaler value */
+#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
+#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
+
+/* Register: TIMER_CC */
+/* Description: Description collection[0]:  Capture/Compare register 0 */
+
+/* Bits 31..0 : Capture/Compare value */
+#define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */
+#define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */
+
+
+/* Peripheral: TWI */
+/* Description: I2C compatible Two-Wire Interface 0 */
+
+/* Register: TWI_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 1 : Shortcut between BB event and STOP task */
+#define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */
+#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */
+#define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between BB event and SUSPEND task */
+#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */
+#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */
+#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
+#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: TWI_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */
+#define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
+
+/* Bit 14 : Write '1' to Enable interrupt for BB event */
+#define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */
+#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */
+#define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENSET_BB_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to Enable interrupt for ERROR event */
+#define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for TXDSENT event */
+#define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
+#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
+#define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for RXDREADY event */
+#define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
+#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
+#define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
+#define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Register: TWI_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */
+#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
+
+/* Bit 14 : Write '1' to Disable interrupt for BB event */
+#define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */
+#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */
+#define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to Disable interrupt for ERROR event */
+#define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for TXDSENT event */
+#define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
+#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
+#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for RXDREADY event */
+#define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
+#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
+#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
+#define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Register: TWI_ERRORSRC */
+/* Description: Error source */
+
+/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
+#define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
+#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
+#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Read: error not present */
+#define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Read: error present */
+#define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Write: clear error on writing '1' */
+
+/* Bit 1 : NACK received after sending the address (write '1' to clear) */
+#define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
+#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
+#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Read: error not present */
+#define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Read: error present */
+#define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Write: clear error on writing '1' */
+
+/* Bit 0 : Overrun error */
+#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
+#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
+#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */
+#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */
+#define TWI_ERRORSRC_OVERRUN_Clear (1UL) /*!< Write: clear error on writing '1' */
+
+/* Register: TWI_ENABLE */
+/* Description: Enable TWI */
+
+/* Bits 3..0 : Enable or disable TWI */
+#define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define TWI_ENABLE_ENABLE_Msk (0xFUL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define TWI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWI */
+#define TWI_ENABLE_ENABLE_Enabled (5UL) /*!< Enable TWI */
+
+/* Register: TWI_PSELSCL */
+/* Description: Pin select for SCL */
+
+/* Bits 31..0 : Pin number configuration for TWI SCL signal */
+#define TWI_PSELSCL_PSELSCL_Pos (0UL) /*!< Position of PSELSCL field. */
+#define TWI_PSELSCL_PSELSCL_Msk (0xFFFFFFFFUL << TWI_PSELSCL_PSELSCL_Pos) /*!< Bit mask of PSELSCL field. */
+#define TWI_PSELSCL_PSELSCL_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
+
+/* Register: TWI_PSELSDA */
+/* Description: Pin select for SDA */
+
+/* Bits 31..0 : Pin number configuration for TWI SDA signal */
+#define TWI_PSELSDA_PSELSDA_Pos (0UL) /*!< Position of PSELSDA field. */
+#define TWI_PSELSDA_PSELSDA_Msk (0xFFFFFFFFUL << TWI_PSELSDA_PSELSDA_Pos) /*!< Bit mask of PSELSDA field. */
+#define TWI_PSELSDA_PSELSDA_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
+
+/* Register: TWI_RXD */
+/* Description: RXD register */
+
+/* Bits 7..0 : RXD register */
+#define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
+#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
+
+/* Register: TWI_TXD */
+/* Description: TXD register */
+
+/* Bits 7..0 : TXD register */
+#define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
+#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
+
+/* Register: TWI_FREQUENCY */
+/* Description: TWI frequency */
+
+/* Bits 31..0 : TWI master clock frequency */
+#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
+#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
+#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps (actual rate 410.256 kbps) */
+
+/* Register: TWI_ADDRESS */
+/* Description: Address used in the TWI transfer */
+
+/* Bits 6..0 : Address used in the TWI transfer */
+#define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
+#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+
+
+/* Peripheral: TWIM */
+/* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */
+
+/* Register: TWIM_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 12 : Shortcut between LASTRX event and STOP task */
+#define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */
+#define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */
+#define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 10 : Shortcut between LASTRX event and STARTTX task */
+#define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */
+#define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */
+#define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */
+#define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 9 : Shortcut between LASTTX event and STOP task */
+#define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */
+#define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */
+#define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 8 : Shortcut between LASTTX event and SUSPEND task */
+#define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */
+#define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */
+#define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
+#define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 7 : Shortcut between LASTTX event and STARTRX task */
+#define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */
+#define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */
+#define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
+#define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: TWIM_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 24 : Enable or disable interrupt for LASTTX event */
+#define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
+#define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
+#define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */
+
+/* Bit 23 : Enable or disable interrupt for LASTRX event */
+#define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
+#define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
+#define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */
+
+/* Bit 20 : Enable or disable interrupt for TXSTARTED event */
+#define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 19 : Enable or disable interrupt for RXSTARTED event */
+#define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 18 : Enable or disable interrupt for SUSPENDED event */
+#define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for ERROR event */
+#define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for STOPPED event */
+#define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Register: TWIM_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 24 : Write '1' to Enable interrupt for LASTTX event */
+#define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
+#define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
+#define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */
+
+/* Bit 23 : Write '1' to Enable interrupt for LASTRX event */
+#define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
+#define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
+#define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
+#define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
+#define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */
+#define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to Enable interrupt for ERROR event */
+#define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
+#define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Register: TWIM_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 24 : Write '1' to Disable interrupt for LASTTX event */
+#define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
+#define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
+#define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */
+
+/* Bit 23 : Write '1' to Disable interrupt for LASTRX event */
+#define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
+#define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
+#define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
+#define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
+#define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */
+#define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to Disable interrupt for ERROR event */
+#define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
+#define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Register: TWIM_ERRORSRC */
+/* Description: Error source */
+
+/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
+#define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
+#define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
+#define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
+#define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
+
+/* Bit 1 : NACK received after sending the address (write '1' to clear) */
+#define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
+#define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
+#define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */
+#define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */
+
+/* Bit 0 : Overrun error */
+#define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
+#define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
+#define TWIM_ERRORSRC_OVERRUN_NotReceived (0UL) /*!< Error did not occur */
+#define TWIM_ERRORSRC_OVERRUN_Received (1UL) /*!< Error occurred */
+
+/* Register: TWIM_ENABLE */
+/* Description: Enable TWIM */
+
+/* Bits 3..0 : Enable or disable TWIM */
+#define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */
+#define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */
+
+/* Register: TWIM_PSEL_SCL */
+/* Description: Pin select for SCL signal */
+
+/* Bit 31 : Connection */
+#define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
+#define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: TWIM_PSEL_SDA */
+/* Description: Pin select for SDA signal */
+
+/* Bit 31 : Connection */
+#define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
+#define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: TWIM_FREQUENCY */
+/* Description: TWI frequency */
+
+/* Bits 31..0 : TWI master clock frequency */
+#define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+#define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
+#define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
+#define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */
+
+/* Register: TWIM_RXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: TWIM_RXD_MAXCNT */
+/* Description: Maximum number of bytes in receive buffer */
+
+/* Bits 7..0 : Maximum number of bytes in receive buffer */
+#define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define TWIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: TWIM_RXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
+#define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define TWIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: TWIM_RXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 2..0 : List type */
+#define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define TWIM_RXD_LIST_LIST_Msk (0x7UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: TWIM_TXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: TWIM_TXD_MAXCNT */
+/* Description: Maximum number of bytes in transmit buffer */
+
+/* Bits 7..0 : Maximum number of bytes in transmit buffer */
+#define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define TWIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: TWIM_TXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
+#define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define TWIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: TWIM_TXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 2..0 : List type */
+#define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define TWIM_TXD_LIST_LIST_Msk (0x7UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: TWIM_ADDRESS */
+/* Description: Address used in the TWI transfer */
+
+/* Bits 6..0 : Address used in the TWI transfer */
+#define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
+#define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+
+
+/* Peripheral: TWIS */
+/* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */
+
+/* Register: TWIS_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 14 : Shortcut between READ event and SUSPEND task */
+#define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */
+#define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */
+#define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
+#define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 13 : Shortcut between WRITE event and SUSPEND task */
+#define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */
+#define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */
+#define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
+#define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: TWIS_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 26 : Enable or disable interrupt for READ event */
+#define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */
+#define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */
+#define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */
+
+/* Bit 25 : Enable or disable interrupt for WRITE event */
+#define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */
+#define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */
+#define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */
+
+/* Bit 20 : Enable or disable interrupt for TXSTARTED event */
+#define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 19 : Enable or disable interrupt for RXSTARTED event */
+#define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for ERROR event */
+#define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for STOPPED event */
+#define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Register: TWIS_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 26 : Write '1' to Enable interrupt for READ event */
+#define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */
+#define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */
+#define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */
+
+/* Bit 25 : Write '1' to Enable interrupt for WRITE event */
+#define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */
+#define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */
+#define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
+#define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
+#define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to Enable interrupt for ERROR event */
+#define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
+#define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Register: TWIS_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 26 : Write '1' to Disable interrupt for READ event */
+#define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */
+#define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */
+#define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */
+
+/* Bit 25 : Write '1' to Disable interrupt for WRITE event */
+#define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */
+#define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */
+#define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
+#define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
+#define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to Disable interrupt for ERROR event */
+#define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
+#define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Register: TWIS_ERRORSRC */
+/* Description: Error source */
+
+/* Bit 3 : TX buffer over-read detected, and prevented */
+#define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */
+#define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
+#define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */
+#define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */
+
+/* Bit 2 : NACK sent after receiving a data byte */
+#define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
+#define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
+#define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
+#define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
+
+/* Bit 0 : RX buffer overflow detected, and prevented */
+#define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */
+#define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
+#define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */
+#define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */
+
+/* Register: TWIS_MATCH */
+/* Description: Status register indicating which address had a match */
+
+/* Bit 0 : Which of the addresses in {ADDRESS} matched the incoming address */
+#define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */
+#define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */
+
+/* Register: TWIS_ENABLE */
+/* Description: Enable TWIS */
+
+/* Bits 3..0 : Enable or disable TWIS */
+#define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */
+#define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */
+
+/* Register: TWIS_PSEL_SCL */
+/* Description: Pin select for SCL signal */
+
+/* Bit 31 : Connection */
+#define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
+#define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: TWIS_PSEL_SDA */
+/* Description: Pin select for SDA signal */
+
+/* Bit 31 : Connection */
+#define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
+#define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: TWIS_RXD_PTR */
+/* Description: RXD Data pointer */
+
+/* Bits 31..0 : RXD Data pointer */
+#define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: TWIS_RXD_MAXCNT */
+/* Description: Maximum number of bytes in RXD buffer */
+
+/* Bits 7..0 : Maximum number of bytes in RXD buffer */
+#define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define TWIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: TWIS_RXD_AMOUNT */
+/* Description: Number of bytes transferred in the last RXD transaction */
+
+/* Bits 7..0 : Number of bytes transferred in the last RXD transaction */
+#define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define TWIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: TWIS_TXD_PTR */
+/* Description: TXD Data pointer */
+
+/* Bits 31..0 : TXD Data pointer */
+#define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: TWIS_TXD_MAXCNT */
+/* Description: Maximum number of bytes in TXD buffer */
+
+/* Bits 7..0 : Maximum number of bytes in TXD buffer */
+#define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define TWIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: TWIS_TXD_AMOUNT */
+/* Description: Number of bytes transferred in the last TXD transaction */
+
+/* Bits 7..0 : Number of bytes transferred in the last TXD transaction */
+#define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define TWIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: TWIS_ADDRESS */
+/* Description: Description collection[0]:  TWI slave address 0 */
+
+/* Bits 6..0 : TWI slave address */
+#define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
+#define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+
+/* Register: TWIS_CONFIG */
+/* Description: Configuration register for the address match mechanism */
+
+/* Bit 1 : Enable or disable address matching on ADDRESS[1] */
+#define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */
+#define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */
+#define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */
+#define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */
+
+/* Bit 0 : Enable or disable address matching on ADDRESS[0] */
+#define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */
+#define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */
+#define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */
+#define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */
+
+/* Register: TWIS_ORC */
+/* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */
+
+/* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */
+#define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
+#define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
+
+
+/* Peripheral: UART */
+/* Description: Universal Asynchronous Receiver/Transmitter */
+
+/* Register: UART_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 4 : Shortcut between NCTS event and STOPRX task */
+#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */
+#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */
+#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */
+#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between CTS event and STARTRX task */
+#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */
+#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */
+#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */
+#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: UART_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 17 : Write '1' to Enable interrupt for RXTO event */
+#define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to Enable interrupt for ERROR event */
+#define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */
+#define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */
+#define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for NCTS event */
+#define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for CTS event */
+#define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENSET_CTS_Set (1UL) /*!< Enable */
+
+/* Register: UART_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 17 : Write '1' to Disable interrupt for RXTO event */
+#define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to Disable interrupt for ERROR event */
+#define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */
+#define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */
+#define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for NCTS event */
+#define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for CTS event */
+#define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable */
+
+/* Register: UART_ERRORSRC */
+/* Description: Error source */
+
+/* Bit 3 : Break condition */
+#define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
+#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
+#define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
+#define UART_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
+
+/* Bit 2 : Framing error occurred */
+#define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
+#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
+#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
+#define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
+
+/* Bit 1 : Parity error */
+#define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
+#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
+#define UART_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
+
+/* Bit 0 : Overrun error */
+#define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
+#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
+#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
+#define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
+
+/* Register: UART_ENABLE */
+/* Description: Enable UART */
+
+/* Bits 3..0 : Enable or disable UART */
+#define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define UART_ENABLE_ENABLE_Msk (0xFUL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define UART_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UART */
+#define UART_ENABLE_ENABLE_Enabled (4UL) /*!< Enable UART */
+
+/* Register: UART_PSELRTS */
+/* Description: Pin select for RTS */
+
+/* Bits 31..0 : Pin number configuration for UART RTS signal */
+#define UART_PSELRTS_PSELRTS_Pos (0UL) /*!< Position of PSELRTS field. */
+#define UART_PSELRTS_PSELRTS_Msk (0xFFFFFFFFUL << UART_PSELRTS_PSELRTS_Pos) /*!< Bit mask of PSELRTS field. */
+#define UART_PSELRTS_PSELRTS_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
+
+/* Register: UART_PSELTXD */
+/* Description: Pin select for TXD */
+
+/* Bits 31..0 : Pin number configuration for UART TXD signal */
+#define UART_PSELTXD_PSELTXD_Pos (0UL) /*!< Position of PSELTXD field. */
+#define UART_PSELTXD_PSELTXD_Msk (0xFFFFFFFFUL << UART_PSELTXD_PSELTXD_Pos) /*!< Bit mask of PSELTXD field. */
+#define UART_PSELTXD_PSELTXD_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
+
+/* Register: UART_PSELCTS */
+/* Description: Pin select for CTS */
+
+/* Bits 31..0 : Pin number configuration for UART CTS signal */
+#define UART_PSELCTS_PSELCTS_Pos (0UL) /*!< Position of PSELCTS field. */
+#define UART_PSELCTS_PSELCTS_Msk (0xFFFFFFFFUL << UART_PSELCTS_PSELCTS_Pos) /*!< Bit mask of PSELCTS field. */
+#define UART_PSELCTS_PSELCTS_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
+
+/* Register: UART_PSELRXD */
+/* Description: Pin select for RXD */
+
+/* Bits 31..0 : Pin number configuration for UART RXD signal */
+#define UART_PSELRXD_PSELRXD_Pos (0UL) /*!< Position of PSELRXD field. */
+#define UART_PSELRXD_PSELRXD_Msk (0xFFFFFFFFUL << UART_PSELRXD_PSELRXD_Pos) /*!< Bit mask of PSELRXD field. */
+#define UART_PSELRXD_PSELRXD_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
+
+/* Register: UART_RXD */
+/* Description: RXD register */
+
+/* Bits 7..0 : RX data received in previous transfers, double buffered */
+#define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
+#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
+
+/* Register: UART_TXD */
+/* Description: TXD register */
+
+/* Bits 7..0 : TX data to be transferred */
+#define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
+#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
+
+/* Register: UART_BAUDRATE */
+/* Description: Baud rate */
+
+/* Bits 31..0 : Baud rate */
+#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
+#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
+#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
+#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
+#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
+#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
+#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud (actual rate: 14414) */
+#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
+#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud (actual rate: 28829) */
+#define UART_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */
+#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud (actual rate: 38462) */
+#define UART_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */
+#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud (actual rate: 57762) */
+#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
+#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud (actual rate: 115942) */
+#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud (actual rate: 231884) */
+#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
+#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud (actual rate: 470588) */
+#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud (actual rate: 941176) */
+#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
+
+/* Register: UART_CONFIG */
+/* Description: Configuration of parity and hardware flow control */
+
+/* Bits 3..1 : Parity */
+#define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
+#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define UART_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
+#define UART_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */
+
+/* Bit 0 : Hardware flow control */
+#define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
+#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
+#define UART_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
+#define UART_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
+
+
+/* Peripheral: UARTE */
+/* Description: UART with EasyDMA */
+
+/* Register: UARTE_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 6 : Shortcut between ENDRX event and STOPRX task */
+#define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */
+#define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */
+#define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */
+#define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 5 : Shortcut between ENDRX event and STARTRX task */
+#define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */
+#define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */
+#define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
+#define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: UARTE_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 22 : Enable or disable interrupt for TXSTOPPED event */
+#define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
+#define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
+#define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */
+
+/* Bit 20 : Enable or disable interrupt for TXSTARTED event */
+#define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 19 : Enable or disable interrupt for RXSTARTED event */
+#define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 17 : Enable or disable interrupt for RXTO event */
+#define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for ERROR event */
+#define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */
+
+/* Bit 8 : Enable or disable interrupt for ENDTX event */
+#define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable interrupt for TXDRDY event */
+#define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for ENDRX event */
+#define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for RXDRDY event */
+#define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for NCTS event */
+#define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for CTS event */
+#define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */
+
+/* Register: UARTE_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 22 : Write '1' to Enable interrupt for TXSTOPPED event */
+#define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
+#define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
+#define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
+#define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
+#define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to Enable interrupt for RXTO event */
+#define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to Enable interrupt for ERROR event */
+#define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 8 : Write '1' to Enable interrupt for ENDTX event */
+#define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */
+#define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
+#define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */
+#define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for NCTS event */
+#define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for CTS event */
+#define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */
+
+/* Register: UARTE_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 22 : Write '1' to Disable interrupt for TXSTOPPED event */
+#define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
+#define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
+#define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
+#define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
+#define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to Disable interrupt for RXTO event */
+#define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to Disable interrupt for ERROR event */
+#define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 8 : Write '1' to Disable interrupt for ENDTX event */
+#define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */
+#define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
+#define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */
+#define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for NCTS event */
+#define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for CTS event */
+#define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */
+
+/* Register: UARTE_ERRORSRC */
+/* Description: Error source */
+
+/* Bit 3 : Break condition */
+#define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
+#define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
+#define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
+#define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
+
+/* Bit 2 : Framing error occurred */
+#define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
+#define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
+#define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
+#define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
+
+/* Bit 1 : Parity error */
+#define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
+#define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
+#define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
+
+/* Bit 0 : Overrun error */
+#define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
+#define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
+#define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
+#define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
+
+/* Register: UARTE_ENABLE */
+/* Description: Enable UART */
+
+/* Bits 3..0 : Enable or disable UARTE */
+#define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */
+#define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */
+
+/* Register: UARTE_PSEL_RTS */
+/* Description: Pin select for RTS signal */
+
+/* Bit 31 : Connection */
+#define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */
+#define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UARTE_PSEL_TXD */
+/* Description: Pin select for TXD signal */
+
+/* Bit 31 : Connection */
+#define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */
+#define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UARTE_PSEL_CTS */
+/* Description: Pin select for CTS signal */
+
+/* Bit 31 : Connection */
+#define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */
+#define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UARTE_PSEL_RXD */
+/* Description: Pin select for RXD signal */
+
+/* Bit 31 : Connection */
+#define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */
+#define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UARTE_BAUDRATE */
+/* Description: Baud rate. Accuracy depends on the HFCLK source selected. */
+
+/* Bits 31..0 : Baud rate */
+#define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
+#define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
+#define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */
+#define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
+#define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
+
+/* Register: UARTE_RXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: UARTE_RXD_MAXCNT */
+/* Description: Maximum number of bytes in receive buffer */
+
+/* Bits 7..0 : Maximum number of bytes in receive buffer */
+#define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define UARTE_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: UARTE_RXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 7..0 : Number of bytes transferred in the last transaction */
+#define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define UARTE_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: UARTE_TXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: UARTE_TXD_MAXCNT */
+/* Description: Maximum number of bytes in transmit buffer */
+
+/* Bits 7..0 : Maximum number of bytes in transmit buffer */
+#define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define UARTE_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: UARTE_TXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 7..0 : Number of bytes transferred in the last transaction */
+#define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define UARTE_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: UARTE_CONFIG */
+/* Description: Configuration of parity and hardware flow control */
+
+/* Bits 3..1 : Parity */
+#define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
+#define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
+#define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */
+
+/* Bit 0 : Hardware flow control */
+#define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
+#define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
+#define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
+#define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
+
+
+/* Peripheral: UICR */
+/* Description: User Information Configuration Registers */
+
+/* Register: UICR_NRFFW */
+/* Description: Description collection[0]:  Reserved for Nordic firmware design */
+
+/* Bits 31..0 : Reserved for Nordic firmware design */
+#define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */
+#define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */
+
+/* Register: UICR_NRFHW */
+/* Description: Description collection[0]:  Reserved for Nordic hardware design */
+
+/* Bits 31..0 : Reserved for Nordic hardware design */
+#define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */
+#define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */
+
+/* Register: UICR_CUSTOMER */
+/* Description: Description collection[0]:  Reserved for customer */
+
+/* Bits 31..0 : Reserved for customer */
+#define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */
+#define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */
+
+/* Register: UICR_PSELRESET */
+/* Description: Description collection[0]:  Mapping of the nRESET function (see POWER chapter for details) */
+
+/* Bit 31 : Connection */
+#define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UICR_PSELRESET_CONNECT_Msk (0x1UL << UICR_PSELRESET_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UICR_PSELRESET_CONNECT_Connected (0UL) /*!< Connect */
+#define UICR_PSELRESET_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : GPIO number P0.n onto which Reset is exposed */
+#define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UICR_PSELRESET_PIN_Msk (0x1FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UICR_APPROTECT */
+/* Description: Access Port protection */
+
+/* Bits 7..0 : Enable or disable Access Port protection. Any other value than 0xFF being written to this field will enable protection. */
+#define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */
+#define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */
+#define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */
+#define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Disable */
+
+/* Register: UICR_NFCPINS */
+/* Description: Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */
+
+/* Bit 0 : Setting of pins dedicated to NFC functionality */
+#define UICR_NFCPINS_PROTECT_Pos (0UL) /*!< Position of PROTECT field. */
+#define UICR_NFCPINS_PROTECT_Msk (0x1UL << UICR_NFCPINS_PROTECT_Pos) /*!< Bit mask of PROTECT field. */
+#define UICR_NFCPINS_PROTECT_Disabled (0UL) /*!< Operation as GPIO pins. Same protection as normal GPIO pins */
+#define UICR_NFCPINS_PROTECT_NFC (1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation */
+
+
+/* Peripheral: WDT */
+/* Description: Watchdog Timer */
+
+/* Register: WDT_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 0 : Write '1' to Enable interrupt for TIMEOUT event */
+#define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
+#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
+#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
+#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
+#define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */
+
+/* Register: WDT_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 0 : Write '1' to Disable interrupt for TIMEOUT event */
+#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
+#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
+#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
+#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
+#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */
+
+/* Register: WDT_RUNSTATUS */
+/* Description: Run status */
+
+/* Bit 0 : Indicates whether or not the watchdog is running */
+#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */
+#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */
+#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog not running */
+#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog is running */
+
+/* Register: WDT_REQSTATUS */
+/* Description: Request status */
+
+/* Bit 7 : Request status for RR[7] register */
+#define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
+#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
+#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */
+
+/* Bit 6 : Request status for RR[6] register */
+#define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
+#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
+#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */
+
+/* Bit 5 : Request status for RR[5] register */
+#define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
+#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
+#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */
+
+/* Bit 4 : Request status for RR[4] register */
+#define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
+#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
+#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */
+
+/* Bit 3 : Request status for RR[3] register */
+#define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
+#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
+#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */
+
+/* Bit 2 : Request status for RR[2] register */
+#define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
+#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
+#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */
+
+/* Bit 1 : Request status for RR[1] register */
+#define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
+#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
+#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */
+
+/* Bit 0 : Request status for RR[0] register */
+#define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
+#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
+#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */
+
+/* Register: WDT_CRV */
+/* Description: Counter reload value */
+
+/* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */
+#define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */
+#define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */
+
+/* Register: WDT_RREN */
+/* Description: Enable register for reload request registers */
+
+/* Bit 7 : Enable or disable RR[7] register */
+#define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
+#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
+#define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */
+#define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */
+
+/* Bit 6 : Enable or disable RR[6] register */
+#define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
+#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
+#define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */
+#define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */
+
+/* Bit 5 : Enable or disable RR[5] register */
+#define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
+#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
+#define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */
+#define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */
+
+/* Bit 4 : Enable or disable RR[4] register */
+#define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
+#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
+#define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */
+#define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */
+
+/* Bit 3 : Enable or disable RR[3] register */
+#define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
+#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
+#define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */
+#define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */
+
+/* Bit 2 : Enable or disable RR[2] register */
+#define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
+#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
+#define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */
+#define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */
+
+/* Bit 1 : Enable or disable RR[1] register */
+#define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
+#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
+#define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */
+#define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */
+
+/* Bit 0 : Enable or disable RR[0] register */
+#define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
+#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
+#define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */
+#define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */
+
+/* Register: WDT_CONFIG */
+/* Description: Configuration register */
+
+/* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */
+#define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
+#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
+#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */
+#define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */
+
+/* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */
+#define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
+#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
+#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */
+#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */
+
+/* Register: WDT_RR */
+/* Description: Description collection[0]:  Reload request 0 */
+
+/* Bits 31..0 : Reload request register */
+#define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
+#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
+#define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */
+
+
+/*lint --flb "Leave library region" */
+#endif
diff --git a/ports/nrf/device/nrf52/nrf52_name_change.h b/ports/nrf/device/nrf52/nrf52_name_change.h
new file mode 100644
index 0000000000..61f90adb0c
--- /dev/null
+++ b/ports/nrf/device/nrf52/nrf52_name_change.h
@@ -0,0 +1,70 @@
+/* Copyright (c) 2016, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *   * Redistributions of source code must retain the above copyright notice, this
+ *     list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *
+ *   * Neither the name of Nordic Semiconductor ASA nor the names of its
+ *     contributors may be used to endorse or promote products derived from
+ *     this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+ 
+#ifndef NRF52_NAME_CHANGE_H
+#define NRF52_NAME_CHANGE_H
+
+/*lint ++flb "Enter library region */
+
+/* This file is given to prevent your SW from not compiling with the updates made to nrf52.h and 
+ * nrf52_bitfields.h. The macros defined in this file were available previously. Do not use these
+ * macros on purpose. Use the ones defined in nrf52.h and nrf52_bitfields.h instead.
+ */
+
+/* I2S */
+/* Several enumerations changed case. Adding old macros to keep compilation compatibility. */
+#define I2S_ENABLE_ENABLE_DISABLE           I2S_ENABLE_ENABLE_Disabled
+#define I2S_ENABLE_ENABLE_ENABLE            I2S_ENABLE_ENABLE_Enabled
+#define I2S_CONFIG_MODE_MODE_MASTER         I2S_CONFIG_MODE_MODE_Master
+#define I2S_CONFIG_MODE_MODE_SLAVE          I2S_CONFIG_MODE_MODE_Slave
+#define I2S_CONFIG_RXEN_RXEN_DISABLE        I2S_CONFIG_RXEN_RXEN_Disabled
+#define I2S_CONFIG_RXEN_RXEN_ENABLE         I2S_CONFIG_RXEN_RXEN_Enabled
+#define I2S_CONFIG_TXEN_TXEN_DISABLE        I2S_CONFIG_TXEN_TXEN_Disabled
+#define I2S_CONFIG_TXEN_TXEN_ENABLE         I2S_CONFIG_TXEN_TXEN_Enabled
+#define I2S_CONFIG_MCKEN_MCKEN_DISABLE      I2S_CONFIG_MCKEN_MCKEN_Disabled
+#define I2S_CONFIG_MCKEN_MCKEN_ENABLE       I2S_CONFIG_MCKEN_MCKEN_Enabled
+#define I2S_CONFIG_SWIDTH_SWIDTH_8BIT       I2S_CONFIG_SWIDTH_SWIDTH_8Bit
+#define I2S_CONFIG_SWIDTH_SWIDTH_16BIT      I2S_CONFIG_SWIDTH_SWIDTH_16Bit
+#define I2S_CONFIG_SWIDTH_SWIDTH_24BIT      I2S_CONFIG_SWIDTH_SWIDTH_24Bit
+#define I2S_CONFIG_ALIGN_ALIGN_LEFT         I2S_CONFIG_ALIGN_ALIGN_Left
+#define I2S_CONFIG_ALIGN_ALIGN_RIGHT        I2S_CONFIG_ALIGN_ALIGN_Right
+#define I2S_CONFIG_FORMAT_FORMAT_ALIGNED    I2S_CONFIG_FORMAT_FORMAT_Aligned
+#define I2S_CONFIG_CHANNELS_CHANNELS_STEREO I2S_CONFIG_CHANNELS_CHANNELS_Stereo
+#define I2S_CONFIG_CHANNELS_CHANNELS_LEFT   I2S_CONFIG_CHANNELS_CHANNELS_Left
+#define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT  I2S_CONFIG_CHANNELS_CHANNELS_Right
+
+/* LPCOMP */
+/* Corrected typo in RESULT register. */
+#define LPCOMP_RESULT_RESULT_Bellow         LPCOMP_RESULT_RESULT_Below
+
+/*lint --flb "Leave library region" */
+
+#endif /* NRF52_NAME_CHANGE_H */
+
diff --git a/ports/nrf/device/nrf52/nrf52_to_nrf52840.h b/ports/nrf/device/nrf52/nrf52_to_nrf52840.h
new file mode 100644
index 0000000000..3067dcc005
--- /dev/null
+++ b/ports/nrf/device/nrf52/nrf52_to_nrf52840.h
@@ -0,0 +1,88 @@
+/* Copyright (c) 2016, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *   * Redistributions of source code must retain the above copyright notice, this
+ *     list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *
+ *   * Neither the name of Nordic Semiconductor ASA nor the names of its
+ *     contributors may be used to endorse or promote products derived from
+ *     this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+ 
+#ifndef NRF52_TO_NRF52840_H
+#define NRF52_TO_NRF52840_H
+
+/*lint ++flb "Enter library region */
+
+/* This file is given to prevent your SW from not compiling with the name changes between nRF51 or nRF52832 and nRF52840 devices.
+ * It redefines the old nRF51 or nRF52832 names into the new ones as long as the functionality is still supported. If the
+ * functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros
+ * from the nrf52_namechange.h file. */
+ 
+/* Differences between latest nRF52 headers and nRF52840 headers. */
+
+/* UART */
+/* The registers PSELRTS, PSELTXD, PSELCTS, PSELRXD were restructured into a struct. */
+#define PSELRTS       PSEL.RTS
+#define PSELTXD       PSEL.TXD
+#define PSELCTS       PSEL.CTS
+#define PSELRXD       PSEL.RXD
+
+/* TWI */
+/* The registers PSELSCL, PSELSDA were restructured into a struct. */
+#define PSELSCL       PSEL.SCL
+#define PSELSDA       PSEL.SDA
+
+
+/* From nrf52_name_change.h. Several macros changed in different versions of nRF52 headers. By defining the following, any code written for any version of nRF52 headers will still compile. */
+
+/* I2S */
+/* Several enumerations changed case. Adding old macros to keep compilation compatibility. */
+#define I2S_ENABLE_ENABLE_DISABLE           I2S_ENABLE_ENABLE_Disabled
+#define I2S_ENABLE_ENABLE_ENABLE            I2S_ENABLE_ENABLE_Enabled
+#define I2S_CONFIG_MODE_MODE_MASTER         I2S_CONFIG_MODE_MODE_Master
+#define I2S_CONFIG_MODE_MODE_SLAVE          I2S_CONFIG_MODE_MODE_Slave
+#define I2S_CONFIG_RXEN_RXEN_DISABLE        I2S_CONFIG_RXEN_RXEN_Disabled
+#define I2S_CONFIG_RXEN_RXEN_ENABLE         I2S_CONFIG_RXEN_RXEN_Enabled
+#define I2S_CONFIG_TXEN_TXEN_DISABLE        I2S_CONFIG_TXEN_TXEN_Disabled
+#define I2S_CONFIG_TXEN_TXEN_ENABLE         I2S_CONFIG_TXEN_TXEN_Enabled
+#define I2S_CONFIG_MCKEN_MCKEN_DISABLE      I2S_CONFIG_MCKEN_MCKEN_Disabled
+#define I2S_CONFIG_MCKEN_MCKEN_ENABLE       I2S_CONFIG_MCKEN_MCKEN_Enabled
+#define I2S_CONFIG_SWIDTH_SWIDTH_8BIT       I2S_CONFIG_SWIDTH_SWIDTH_8Bit
+#define I2S_CONFIG_SWIDTH_SWIDTH_16BIT      I2S_CONFIG_SWIDTH_SWIDTH_16Bit
+#define I2S_CONFIG_SWIDTH_SWIDTH_24BIT      I2S_CONFIG_SWIDTH_SWIDTH_24Bit
+#define I2S_CONFIG_ALIGN_ALIGN_LEFT         I2S_CONFIG_ALIGN_ALIGN_Left
+#define I2S_CONFIG_ALIGN_ALIGN_RIGHT        I2S_CONFIG_ALIGN_ALIGN_Right
+#define I2S_CONFIG_FORMAT_FORMAT_ALIGNED    I2S_CONFIG_FORMAT_FORMAT_Aligned
+#define I2S_CONFIG_CHANNELS_CHANNELS_STEREO I2S_CONFIG_CHANNELS_CHANNELS_Stereo
+#define I2S_CONFIG_CHANNELS_CHANNELS_LEFT   I2S_CONFIG_CHANNELS_CHANNELS_Left
+#define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT  I2S_CONFIG_CHANNELS_CHANNELS_Right
+
+/* LPCOMP */
+/* Corrected typo in RESULT register. */
+#define LPCOMP_RESULT_RESULT_Bellow         LPCOMP_RESULT_RESULT_Below
+
+
+/*lint --flb "Leave library region" */
+
+#endif /* NRF51_TO_NRF52840_H */
+
diff --git a/ports/nrf/device/nrf52/startup_nrf52832.c b/ports/nrf/device/nrf52/startup_nrf52832.c
new file mode 100644
index 0000000000..b36ac0d971
--- /dev/null
+++ b/ports/nrf/device/nrf52/startup_nrf52832.c
@@ -0,0 +1,167 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <stdint.h>
+
+extern uint32_t _estack;
+extern uint32_t _sidata;
+extern uint32_t _sdata;
+extern uint32_t _edata;
+extern uint32_t _sbss;
+extern uint32_t _ebss;
+
+typedef void (*func)(void);
+
+extern void  _start(void) __attribute__((noreturn));
+extern void SystemInit(void);
+
+void Default_Handler(void) {
+    while (1);
+}
+
+void Reset_Handler(void) {
+    uint32_t * p_src  = &_sidata;
+    uint32_t * p_dest = &_sdata;
+
+    while (p_dest < &_edata) {
+      *p_dest++ = *p_src++;
+    }
+
+    uint32_t * p_bss     = &_sbss;
+    uint32_t * p_bss_end = &_ebss;
+    while (p_bss < p_bss_end) {
+        *p_bss++ = 0ul;
+    }
+
+    SystemInit();
+    _start();
+}
+
+void NMI_Handler              (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler        (void) __attribute__ ((weak, alias("Default_Handler")));
+void MemoryManagement_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler       (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler              (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler           (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler          (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void POWER_CLOCK_IRQHandler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void RADIO_IRQHandler         (void) __attribute__ ((weak, alias("Default_Handler")));
+void UARTE0_UART0_IRQHandler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void NFCT_IRQHandler          (void) __attribute__ ((weak, alias("Default_Handler")));
+void GPIOTE_IRQHandler        (void) __attribute__ ((weak, alias("Default_Handler")));
+void SAADC_IRQHandler         (void) __attribute__ ((weak, alias("Default_Handler")));
+void TIMER0_IRQHandler        (void) __attribute__ ((weak, alias("Default_Handler")));
+void TIMER1_IRQHandler        (void) __attribute__ ((weak, alias("Default_Handler")));
+void TIMER2_IRQHandler        (void) __attribute__ ((weak, alias("Default_Handler")));
+void RTC0_IRQHandler          (void) __attribute__ ((weak, alias("Default_Handler")));
+void TEMP_IRQHandler          (void) __attribute__ ((weak, alias("Default_Handler")));
+void RNG_IRQHandler           (void) __attribute__ ((weak, alias("Default_Handler")));
+void ECB_IRQHandler           (void) __attribute__ ((weak, alias("Default_Handler")));
+void CCM_AAR_IRQHandler       (void) __attribute__ ((weak, alias("Default_Handler")));
+void WDT_IRQHandler           (void) __attribute__ ((weak, alias("Default_Handler")));
+void RTC1_IRQHandler          (void) __attribute__ ((weak, alias("Default_Handler")));
+void QDEC_IRQHandler          (void) __attribute__ ((weak, alias("Default_Handler")));
+void COMP_LPCOMP_IRQHandler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void SWI0_EGU0_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void SWI1_EGU1_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void SWI2_EGU2_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void SWI3_EGU3_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void SWI4_EGU4_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void SWI5_EGU5_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void TIMER3_IRQHandler        (void) __attribute__ ((weak, alias("Default_Handler")));
+void TIMER4_IRQHandler        (void) __attribute__ ((weak, alias("Default_Handler")));
+void PWM0_IRQHandler          (void) __attribute__ ((weak, alias("Default_Handler")));
+void PDM_IRQHandler           (void) __attribute__ ((weak, alias("Default_Handler")));
+void MWU_IRQHandler           (void) __attribute__ ((weak, alias("Default_Handler")));
+void PWM1_IRQHandler          (void) __attribute__ ((weak, alias("Default_Handler")));
+void PWM2_IRQHandler          (void) __attribute__ ((weak, alias("Default_Handler")));
+void SPIM2_SPIS2_SPI2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void RTC2_IRQHandler          (void) __attribute__ ((weak, alias("Default_Handler")));
+void I2S_IRQHandler           (void) __attribute__ ((weak, alias("Default_Handler")));
+
+const func __Vectors[] __attribute__ ((section(".isr_vector"))) = {
+    (func)&_estack,
+    Reset_Handler,
+    NMI_Handler,
+    HardFault_Handler,
+    MemoryManagement_Handler,
+    BusFault_Handler,
+    UsageFault_Handler,
+    0,
+    0,
+    0,
+    0,
+    SVC_Handler,
+    DebugMon_Handler,
+    0,
+    PendSV_Handler,
+    SysTick_Handler,
+
+    /* External Interrupts */
+    POWER_CLOCK_IRQHandler,
+    RADIO_IRQHandler,
+    UARTE0_UART0_IRQHandler,
+    SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler,
+    SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler,
+    NFCT_IRQHandler,
+    GPIOTE_IRQHandler,
+    SAADC_IRQHandler,
+    TIMER0_IRQHandler,
+    TIMER1_IRQHandler,
+    TIMER2_IRQHandler,
+    RTC0_IRQHandler,
+    TEMP_IRQHandler,
+    RNG_IRQHandler,
+    ECB_IRQHandler,
+    CCM_AAR_IRQHandler,
+    WDT_IRQHandler,
+    RTC1_IRQHandler,
+    QDEC_IRQHandler,
+    COMP_LPCOMP_IRQHandler,
+    SWI0_EGU0_IRQHandler,
+    SWI1_EGU1_IRQHandler,
+    SWI2_EGU2_IRQHandler,
+    SWI3_EGU3_IRQHandler,
+    SWI4_EGU4_IRQHandler,
+    SWI5_EGU5_IRQHandler,
+    TIMER3_IRQHandler,
+    TIMER4_IRQHandler,
+    PWM0_IRQHandler,
+    PDM_IRQHandler,
+    0,
+    0,
+    MWU_IRQHandler,
+    PWM1_IRQHandler,
+    PWM2_IRQHandler,
+    SPIM2_SPIS2_SPI2_IRQHandler,
+    RTC2_IRQHandler,
+    I2S_IRQHandler
+};
diff --git a/ports/nrf/device/nrf52/startup_nrf52840.c b/ports/nrf/device/nrf52/startup_nrf52840.c
new file mode 100644
index 0000000000..998696c08e
--- /dev/null
+++ b/ports/nrf/device/nrf52/startup_nrf52840.c
@@ -0,0 +1,182 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <stdint.h>
+
+extern uint32_t _estack;
+extern uint32_t _sidata;
+extern uint32_t _sdata;
+extern uint32_t _edata;
+extern uint32_t _sbss;
+extern uint32_t _ebss;
+
+typedef void (*func)(void);
+
+extern void  _start(void) __attribute__((noreturn));
+extern void SystemInit(void);
+
+void Default_Handler(void) {
+    while (1);
+}
+
+void Reset_Handler(void) {
+    uint32_t * p_src  = &_sidata;
+    uint32_t * p_dest = &_sdata;
+
+    while (p_dest < &_edata) {
+      *p_dest++ = *p_src++;
+    }
+
+    uint32_t * p_bss     = &_sbss;
+    uint32_t * p_bss_end = &_ebss;
+    while (p_bss < p_bss_end) {
+        *p_bss++ = 0ul;
+    }
+
+    SystemInit();
+    _start();
+}
+
+void NMI_Handler                 (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler           (void) __attribute__ ((weak, alias("Default_Handler")));
+void MemoryManagement_Handler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler            (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler          (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler                 (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler            (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler              (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler             (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void POWER_CLOCK_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void RADIO_IRQHandler            (void) __attribute__ ((weak, alias("Default_Handler")));
+void UARTE0_UART0_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void NFCT_IRQHandler             (void) __attribute__ ((weak, alias("Default_Handler")));
+void GPIOTE_IRQHandler           (void) __attribute__ ((weak, alias("Default_Handler")));
+void SAADC_IRQHandler            (void) __attribute__ ((weak, alias("Default_Handler")));
+void TIMER0_IRQHandler           (void) __attribute__ ((weak, alias("Default_Handler")));
+void TIMER1_IRQHandler           (void) __attribute__ ((weak, alias("Default_Handler")));
+void TIMER2_IRQHandler           (void) __attribute__ ((weak, alias("Default_Handler")));
+void RTC0_IRQHandler             (void) __attribute__ ((weak, alias("Default_Handler")));
+void TEMP_IRQHandler             (void) __attribute__ ((weak, alias("Default_Handler")));
+void RNG_IRQHandler              (void) __attribute__ ((weak, alias("Default_Handler")));
+void ECB_IRQHandler              (void) __attribute__ ((weak, alias("Default_Handler")));
+void CCM_AAR_IRQHandler          (void) __attribute__ ((weak, alias("Default_Handler")));
+void WDT_IRQHandler              (void) __attribute__ ((weak, alias("Default_Handler")));
+void RTC1_IRQHandler             (void) __attribute__ ((weak, alias("Default_Handler")));
+void QDEC_IRQHandler             (void) __attribute__ ((weak, alias("Default_Handler")));
+void COMP_LPCOMP_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void SWI0_EGU0_IRQHandler        (void) __attribute__ ((weak, alias("Default_Handler")));
+void SWI1_EGU1_IRQHandler        (void) __attribute__ ((weak, alias("Default_Handler")));
+void SWI2_EGU2_IRQHandler        (void) __attribute__ ((weak, alias("Default_Handler")));
+void SWI3_EGU3_IRQHandler        (void) __attribute__ ((weak, alias("Default_Handler")));
+void SWI4_EGU4_IRQHandler        (void) __attribute__ ((weak, alias("Default_Handler")));
+void SWI5_EGU5_IRQHandler        (void) __attribute__ ((weak, alias("Default_Handler")));
+void TIMER3_IRQHandler           (void) __attribute__ ((weak, alias("Default_Handler")));
+void TIMER4_IRQHandler           (void) __attribute__ ((weak, alias("Default_Handler")));
+void PWM0_IRQHandler             (void) __attribute__ ((weak, alias("Default_Handler")));
+void PDM_IRQHandler              (void) __attribute__ ((weak, alias("Default_Handler")));
+void MWU_IRQHandler              (void) __attribute__ ((weak, alias("Default_Handler")));
+void PWM1_IRQHandler             (void) __attribute__ ((weak, alias("Default_Handler")));
+void PWM2_IRQHandler             (void) __attribute__ ((weak, alias("Default_Handler")));
+void SPIM2_SPIS2_SPI2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void RTC2_IRQHandler             (void) __attribute__ ((weak, alias("Default_Handler")));
+void I2S_IRQHandler              (void) __attribute__ ((weak, alias("Default_Handler")));
+void FPU_IRQHandler              (void) __attribute__ ((weak, alias("Default_Handler")));
+void USBD_IRQHandler             (void) __attribute__ ((weak, alias("Default_Handler")));
+void UARTE1_IRQHandler           (void) __attribute__ ((weak, alias("Default_Handler")));
+void QSPI_IRQHandler             (void) __attribute__ ((weak, alias("Default_Handler")));
+void CRYPTOCELL_IRQHandler       (void) __attribute__ ((weak, alias("Default_Handler")));
+void SPIM3_IRQHandler            (void) __attribute__ ((weak, alias("Default_Handler")));
+void PWM3_IRQHandler             (void) __attribute__ ((weak, alias("Default_Handler")));
+
+const func __Vectors[] __attribute__ ((section(".isr_vector"))) = {
+    (func)&_estack,
+    Reset_Handler,
+    NMI_Handler,
+    HardFault_Handler,
+    MemoryManagement_Handler,
+    BusFault_Handler,
+    UsageFault_Handler,
+    0,
+    0,
+    0,
+    0,
+    SVC_Handler,
+    DebugMon_Handler,
+    0,
+    PendSV_Handler,
+    SysTick_Handler,
+
+    /* External Interrupts */
+    POWER_CLOCK_IRQHandler,
+    RADIO_IRQHandler,
+    UARTE0_UART0_IRQHandler,
+    SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler,
+    SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler,
+    NFCT_IRQHandler,
+    GPIOTE_IRQHandler,
+    SAADC_IRQHandler,
+    TIMER0_IRQHandler,
+    TIMER1_IRQHandler,
+    TIMER2_IRQHandler,
+    RTC0_IRQHandler,
+    TEMP_IRQHandler,
+    RNG_IRQHandler,
+    ECB_IRQHandler,
+    CCM_AAR_IRQHandler,
+    WDT_IRQHandler,
+    RTC1_IRQHandler,
+    QDEC_IRQHandler,
+    COMP_LPCOMP_IRQHandler,
+    SWI0_EGU0_IRQHandler,
+    SWI1_EGU1_IRQHandler,
+    SWI2_EGU2_IRQHandler,
+    SWI3_EGU3_IRQHandler,
+    SWI4_EGU4_IRQHandler,
+    SWI5_EGU5_IRQHandler,
+    TIMER3_IRQHandler,
+    TIMER4_IRQHandler,
+    PWM0_IRQHandler,
+    PDM_IRQHandler,
+    0,
+    0,
+    MWU_IRQHandler,
+    PWM1_IRQHandler,
+    PWM2_IRQHandler,
+    SPIM2_SPIS2_SPI2_IRQHandler,
+    RTC2_IRQHandler,
+    I2S_IRQHandler,
+    FPU_IRQHandler,
+    USBD_IRQHandler,
+    UARTE1_IRQHandler,
+    QSPI_IRQHandler,
+    CRYPTOCELL_IRQHandler,
+    SPIM3_IRQHandler,
+    0,
+    PWM3_IRQHandler,
+};
diff --git a/ports/nrf/device/nrf52/system_nrf52.h b/ports/nrf/device/nrf52/system_nrf52.h
new file mode 100644
index 0000000000..9201e7926b
--- /dev/null
+++ b/ports/nrf/device/nrf52/system_nrf52.h
@@ -0,0 +1,69 @@
+/* Copyright (c) 2012 ARM LIMITED
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *   * Redistributions of source code must retain the above copyright notice, this
+ *     list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *
+ *   * Neither the name of ARM nor the names of its contributors may be used to
+ *     endorse or promote products derived from this software without specific
+ *     prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+ 
+#ifndef SYSTEM_NRF52_H
+#define SYSTEM_NRF52_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+
+extern uint32_t SystemCoreClock;    /*!< System Clock Frequency (Core Clock)  */
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock 
+ *         retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_NRF52_H */
diff --git a/ports/nrf/device/nrf52/system_nrf52832.c b/ports/nrf/device/nrf52/system_nrf52832.c
new file mode 100644
index 0000000000..b96b41717c
--- /dev/null
+++ b/ports/nrf/device/nrf52/system_nrf52832.c
@@ -0,0 +1,308 @@
+/* Copyright (c) 2012 ARM LIMITED
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *   * Redistributions of source code must retain the above copyright notice, this
+ *     list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *
+ *   * Neither the name of ARM nor the names of its contributors may be used to
+ *     endorse or promote products derived from this software without specific
+ *     prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+ 
+#include <stdint.h>
+#include <stdbool.h>
+#include "nrf.h"
+#include "system_nrf52.h"
+
+/*lint ++flb "Enter library region" */
+
+#define __SYSTEM_CLOCK_64M      (64000000UL)
+
+static bool errata_16(void);
+static bool errata_31(void);
+static bool errata_32(void);
+static bool errata_36(void);
+static bool errata_37(void);
+static bool errata_57(void);
+static bool errata_66(void);
+static bool errata_108(void);
+
+
+#if defined ( __CC_ARM )
+    uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
+#elif defined ( __ICCARM__ )
+    __root uint32_t SystemCoreClock = __SYSTEM_CLOCK_64M;
+#elif defined ( __GNUC__ )
+    uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
+#endif
+
+void SystemCoreClockUpdate(void)
+{
+    SystemCoreClock = __SYSTEM_CLOCK_64M;
+}
+
+void SystemInit(void)
+{
+    /* Workaround for Errata 16 "System: RAM may be corrupt on wakeup from CPU IDLE" found at the Errata document
+       for your device located at https://infocenter.nordicsemi.com/ */
+    if (errata_16()){
+        *(volatile uint32_t *)0x4007C074 = 3131961357ul;
+    }
+
+    /* Workaround for Errata 31 "CLOCK: Calibration values are not correctly loaded from FICR at reset" found at the Errata document
+       for your device located at https://infocenter.nordicsemi.com/ */
+    if (errata_31()){
+        *(volatile uint32_t *)0x4000053C = ((*(volatile uint32_t *)0x10000244) & 0x0000E000) >> 13;
+    }
+
+    /* Workaround for Errata 32 "DIF: Debug session automatically enables TracePort pins" found at the Errata document
+       for your device located at https://infocenter.nordicsemi.com/ */
+    if (errata_32()){
+        CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk;
+    }
+
+    /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
+       for your device located at https://infocenter.nordicsemi.com/  */
+    if (errata_36()){
+        NRF_CLOCK->EVENTS_DONE = 0;
+        NRF_CLOCK->EVENTS_CTTO = 0;
+        NRF_CLOCK->CTIV = 0;
+    }
+
+    /* Workaround for Errata 37 "RADIO: Encryption engine is slow by default" found at the Errata document
+       for your device located at https://infocenter.nordicsemi.com/  */
+    if (errata_37()){
+        *(volatile uint32_t *)0x400005A0 = 0x3;
+    }
+
+    /* Workaround for Errata 57 "NFCT: NFC Modulation amplitude" found at the Errata document
+       for your device located at https://infocenter.nordicsemi.com/  */
+    if (errata_57()){
+        *(volatile uint32_t *)0x40005610 = 0x00000005;
+        *(volatile uint32_t *)0x40005688 = 0x00000001;
+        *(volatile uint32_t *)0x40005618 = 0x00000000;
+        *(volatile uint32_t *)0x40005614 = 0x0000003F;
+    }
+
+    /* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document
+       for your device located at https://infocenter.nordicsemi.com/  */
+    if (errata_66()){
+        NRF_TEMP->A0 = NRF_FICR->TEMP.A0;
+        NRF_TEMP->A1 = NRF_FICR->TEMP.A1;
+        NRF_TEMP->A2 = NRF_FICR->TEMP.A2;
+        NRF_TEMP->A3 = NRF_FICR->TEMP.A3;
+        NRF_TEMP->A4 = NRF_FICR->TEMP.A4;
+        NRF_TEMP->A5 = NRF_FICR->TEMP.A5;
+        NRF_TEMP->B0 = NRF_FICR->TEMP.B0;
+        NRF_TEMP->B1 = NRF_FICR->TEMP.B1;
+        NRF_TEMP->B2 = NRF_FICR->TEMP.B2;
+        NRF_TEMP->B3 = NRF_FICR->TEMP.B3;
+        NRF_TEMP->B4 = NRF_FICR->TEMP.B4;
+        NRF_TEMP->B5 = NRF_FICR->TEMP.B5;
+        NRF_TEMP->T0 = NRF_FICR->TEMP.T0;
+        NRF_TEMP->T1 = NRF_FICR->TEMP.T1;
+        NRF_TEMP->T2 = NRF_FICR->TEMP.T2;
+        NRF_TEMP->T3 = NRF_FICR->TEMP.T3;
+        NRF_TEMP->T4 = NRF_FICR->TEMP.T4;
+    }
+
+    /* Workaround for Errata 108 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
+       for your device located at https://infocenter.nordicsemi.com/  */
+    if (errata_108()){
+        *(volatile uint32_t *)0x40000EE4 = *(volatile uint32_t *)0x10000258 & 0x0000004F;
+    }
+    
+    /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
+     * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
+     * operations are not used in your code. */
+    #if (__FPU_USED == 1)
+        SCB->CPACR |= (3UL << 20) | (3UL << 22);
+        __DSB();
+        __ISB();
+    #endif
+
+    /* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined,
+       two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as
+       normal GPIOs. */
+    #if defined (CONFIG_NFCT_PINS_AS_GPIOS)
+        if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){
+            NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
+            while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+            NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk;
+            while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+            NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
+            while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+            NVIC_SystemReset();
+        }
+    #endif
+
+    /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
+      defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
+      reserved for PinReset and not available as normal GPIO. */
+    #if defined (CONFIG_GPIO_AS_PINRESET)
+        if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
+            ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
+            NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
+            while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+            NRF_UICR->PSELRESET[0] = 21;
+            while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+            NRF_UICR->PSELRESET[1] = 21;
+            while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+            NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
+            while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+            NVIC_SystemReset();
+        }
+    #endif
+
+    /* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product
+       Specification to see which one). */
+    #if defined (ENABLE_SWO)
+        CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+        NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
+        NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+    #endif
+
+    /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product
+       Specification to see which ones). */
+    #if defined (ENABLE_TRACE)
+        CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+        NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos;
+        NRF_P0->PIN_CNF[14] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+        NRF_P0->PIN_CNF[15] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+        NRF_P0->PIN_CNF[16] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+        NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+        NRF_P0->PIN_CNF[20] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+    #endif
+
+    SystemCoreClockUpdate();
+}
+
+
+static bool errata_16(void)
+{
+    if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
+        if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){
+            return true;
+        }
+    }
+
+    return false;
+}
+
+static bool errata_31(void)
+{
+    if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
+        if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){
+            return true;
+        }
+        if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40){
+            return true;
+        }
+        if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){
+            return true;
+        }
+    }
+
+    return false;
+}
+
+static bool errata_32(void)
+{
+    if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
+        if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){
+            return true;
+        }
+    }
+
+    return false;
+}
+
+static bool errata_36(void)
+{
+    if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
+        if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){
+            return true;
+        }
+        if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40){
+            return true;
+        }
+        if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){
+            return true;
+        }
+    }
+
+    return false;
+}
+
+static bool errata_37(void)
+{
+    if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
+        if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){
+            return true;
+        }
+    }
+
+    return false;
+}
+
+static bool errata_57(void)
+{
+    if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
+        if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){
+            return true;
+        }
+    }
+
+    return false;
+}
+
+static bool errata_66(void)
+{
+    if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
+        if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){
+            return true;
+        }
+    }
+
+    return false;
+}
+
+
+static bool errata_108(void)
+{
+    if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
+        if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){
+            return true;
+        }
+        if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40){
+            return true;
+        }
+        if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){
+            return true;
+        }
+    }
+
+    return false;
+}
+
+
+/*lint --flb "Leave library region" */
diff --git a/ports/nrf/device/nrf52/system_nrf52840.c b/ports/nrf/device/nrf52/system_nrf52840.c
new file mode 100644
index 0000000000..4a94218cc3
--- /dev/null
+++ b/ports/nrf/device/nrf52/system_nrf52840.c
@@ -0,0 +1,209 @@
+/* Copyright (c) 2012 ARM LIMITED
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *   * Redistributions of source code must retain the above copyright notice, this
+ *     list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *
+ *   * Neither the name of ARM nor the names of its contributors may be used to
+ *     endorse or promote products derived from this software without specific
+ *     prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "nrf.h"
+#include "system_nrf52840.h"
+
+/*lint ++flb "Enter library region" */
+
+#define __SYSTEM_CLOCK_64M      (64000000UL)
+
+static bool errata_36(void);
+static bool errata_98(void);
+static bool errata_103(void);
+static bool errata_115(void);
+static bool errata_120(void);
+
+
+#if defined ( __CC_ARM )
+    uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
+#elif defined ( __ICCARM__ )
+    __root uint32_t SystemCoreClock = __SYSTEM_CLOCK_64M;
+#elif defined ( __GNUC__ )
+    uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
+#endif
+
+void SystemCoreClockUpdate(void)
+{
+    SystemCoreClock = __SYSTEM_CLOCK_64M;
+}
+
+void SystemInit(void)
+{
+    /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
+       for your device located at https://infocenter.nordicsemi.com/  */
+    if (errata_36()){
+        NRF_CLOCK->EVENTS_DONE = 0;
+        NRF_CLOCK->EVENTS_CTTO = 0;
+        NRF_CLOCK->CTIV = 0;
+    }
+
+    /* Workaround for Errata 98 "NFCT: Not able to communicate with the peer" found at the Errata document
+       for your device located at https://infocenter.nordicsemi.com/  */
+    if (errata_98()){
+        *(volatile uint32_t *)0x4000568Cul = 0x00038148ul;
+    }
+
+    /* Workaround for Errata 103 "CCM: Wrong reset value of CCM MAXPACKETSIZE" found at the Errata document
+       for your device located at https://infocenter.nordicsemi.com/  */
+    if (errata_103()){
+        NRF_CCM->MAXPACKETSIZE = 0xFBul;
+    }
+
+    /* Workaround for Errata 115 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
+       for your device located at https://infocenter.nordicsemi.com/  */
+    if (errata_115()){
+        *(volatile uint32_t *)0x40000EE4 = (*(volatile uint32_t *)0x40000EE4 & 0xFFFFFFF0) | (*(uint32_t *)0x10000258 & 0x0000000F);
+    }
+
+    /* Workaround for Errata 120 "QSPI: Data read or written is corrupted" found at the Errata document
+       for your device located at https://infocenter.nordicsemi.com/  */
+    if (errata_120()){
+        *(volatile uint32_t *)0x40029640ul = 0x200ul;
+    }
+
+    /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
+     * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
+     * operations are not used in your code. */
+    #if (__FPU_USED == 1)
+        SCB->CPACR |= (3UL << 20) | (3UL << 22);
+        __DSB();
+        __ISB();
+    #endif
+
+    /* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined,
+       two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as
+       normal GPIOs. */
+    #if defined (CONFIG_NFCT_PINS_AS_GPIOS)
+        if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){
+            NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
+            while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+            NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk;
+            while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+            NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
+            while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+            NVIC_SystemReset();
+        }
+    #endif
+
+    /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
+      defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
+      reserved for PinReset and not available as normal GPIO. */
+    #if defined (CONFIG_GPIO_AS_PINRESET)
+        if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
+            ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
+            NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
+            while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+            NRF_UICR->PSELRESET[0] = 18;
+            while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+            NRF_UICR->PSELRESET[1] = 18;
+            while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+            NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
+            while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+            NVIC_SystemReset();
+        }
+    #endif
+
+    /* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product
+       Specification to see which one). */
+    #if defined (ENABLE_SWO)
+        CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+        NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
+        NRF_P1->PIN_CNF[0] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+    #endif
+
+    /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product
+       Specification to see which ones). */
+    #if defined (ENABLE_TRACE)
+        CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+        NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos;
+        NRF_P0->PIN_CNF[7]  = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+        NRF_P1->PIN_CNF[0]  = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+        NRF_P0->PIN_CNF[12] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+        NRF_P0->PIN_CNF[11] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+        NRF_P1->PIN_CNF[9]  = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+    #endif
+
+    SystemCoreClockUpdate();
+}
+
+
+static bool errata_36(void)
+{
+    if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
+        return true;
+    }
+
+    return false;
+}
+
+
+static bool errata_98(void)
+{
+    if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
+        return true;
+    }
+
+    return false;
+}
+
+
+static bool errata_103(void)
+{
+    if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
+        return true;
+    }
+
+    return false;
+}
+
+
+static bool errata_115(void)
+{
+    if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
+        return true;
+    }
+
+    return false;
+}
+
+
+static bool errata_120(void)
+{
+    if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
+        return true;
+    }
+
+    return false;
+}
+
+/*lint --flb "Leave library region" */
diff --git a/ports/nrf/device/nrf52/system_nrf52840.h b/ports/nrf/device/nrf52/system_nrf52840.h
new file mode 100644
index 0000000000..9201e7926b
--- /dev/null
+++ b/ports/nrf/device/nrf52/system_nrf52840.h
@@ -0,0 +1,69 @@
+/* Copyright (c) 2012 ARM LIMITED
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *   * Redistributions of source code must retain the above copyright notice, this
+ *     list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *
+ *   * Neither the name of ARM nor the names of its contributors may be used to
+ *     endorse or promote products derived from this software without specific
+ *     prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+ 
+#ifndef SYSTEM_NRF52_H
+#define SYSTEM_NRF52_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+
+extern uint32_t SystemCoreClock;    /*!< System Clock Frequency (Core Clock)  */
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock 
+ *         retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_NRF52_H */
diff --git a/ports/nrf/drivers/bluetooth/ble_drv.c b/ports/nrf/drivers/bluetooth/ble_drv.c
new file mode 100644
index 0000000000..2bb6fac2d2
--- /dev/null
+++ b/ports/nrf/drivers/bluetooth/ble_drv.c
@@ -0,0 +1,1065 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#if BLUETOOTH_SD
+
+#include <stdio.h>
+#include <string.h>
+#include <stdbool.h>
+
+#include "py/runtime.h"
+#include "ble_drv.h"
+#include "mpconfigport.h"
+#include "nrf_sdm.h"
+#include "ble_gap.h"
+#include "ble.h" // sd_ble_uuid_encode
+
+
+#define BLE_DRIVER_VERBOSE 0
+#if BLE_DRIVER_VERBOSE
+#define BLE_DRIVER_LOG printf
+#else
+#define BLE_DRIVER_LOG(...)
+#endif
+
+#define BLE_ADV_LENGTH_FIELD_SIZE   1
+#define BLE_ADV_AD_TYPE_FIELD_SIZE  1
+#define BLE_AD_TYPE_FLAGS_DATA_SIZE 1
+
+#define MSEC_TO_UNITS(TIME, RESOLUTION) (((TIME) * 1000) / (RESOLUTION))
+#define UNIT_0_625_MS (625)
+#define UNIT_10_MS    (10000)
+#define APP_CFG_NON_CONN_ADV_TIMEOUT 0 // Disable timeout.
+#define NON_CONNECTABLE_ADV_INTERVAL MSEC_TO_UNITS(100, UNIT_0_625_MS)
+
+#define BLE_MIN_CONN_INTERVAL        MSEC_TO_UNITS(12, UNIT_0_625_MS)
+#define BLE_MAX_CONN_INTERVAL        MSEC_TO_UNITS(12, UNIT_0_625_MS)
+#define BLE_SLAVE_LATENCY            0
+#define BLE_CONN_SUP_TIMEOUT         MSEC_TO_UNITS(4000, UNIT_10_MS)
+
+#define SD_TEST_OR_ENABLE() \
+if (ble_drv_stack_enabled() == 0) { \
+    (void)ble_drv_stack_enable(); \
+}
+
+static volatile bool m_adv_in_progress;
+static volatile bool m_tx_in_progress;
+
+static ble_drv_gap_evt_callback_t          gap_event_handler;
+static ble_drv_gatts_evt_callback_t        gatts_event_handler;
+
+static mp_obj_t mp_gap_observer;
+static mp_obj_t mp_gatts_observer;
+
+#if (BLUETOOTH_SD == 130) || (BLUETOOTH_SD == 132)
+static volatile bool m_primary_service_found;
+static volatile bool m_characteristic_found;
+static volatile bool m_write_done;
+
+static volatile ble_drv_adv_evt_callback_t          adv_event_handler;
+static volatile ble_drv_gattc_evt_callback_t        gattc_event_handler;
+static volatile ble_drv_disc_add_service_callback_t disc_add_service_handler;
+static volatile ble_drv_disc_add_char_callback_t    disc_add_char_handler;
+static volatile ble_drv_gattc_char_data_callback_t  gattc_char_data_handle;
+
+static mp_obj_t mp_adv_observer;
+static mp_obj_t mp_gattc_observer;
+static mp_obj_t mp_gattc_disc_service_observer;
+static mp_obj_t mp_gattc_disc_char_observer;
+static mp_obj_t mp_gattc_char_data_observer;
+#endif
+
+#if (BLUETOOTH_SD != 100) && (BLUETOOTH_SD != 110)
+#include "nrf_nvic.h"
+
+#ifdef NRF52
+nrf_nvic_state_t nrf_nvic_state = {0};
+#endif // NRF52
+
+#endif // (BLUETOOTH_SD != 100)
+
+#if (BLUETOOTH_SD == 100 ) || (BLUETOOTH_SD == 110)
+void softdevice_assert_handler(uint32_t pc, uint16_t line_number, const uint8_t * p_file_name) {
+    BLE_DRIVER_LOG("ERROR: SoftDevice assert!!!");
+}
+#else
+void softdevice_assert_handler(uint32_t id, uint32_t pc, uint32_t info) {
+    BLE_DRIVER_LOG("ERROR: SoftDevice assert!!!");
+}
+#endif
+uint32_t ble_drv_stack_enable(void) {
+    m_adv_in_progress = false;
+    m_tx_in_progress  = false;
+
+#if (BLUETOOTH_SD == 100) || (BLUETOOTH_SD == 110)
+#if BLUETOOTH_LFCLK_RC
+    uint32_t err_code = sd_softdevice_enable(NRF_CLOCK_LFCLKSRC_RC_250_PPM_250MS_CALIBRATION,
+                                             softdevice_assert_handler);
+#else
+    uint32_t err_code = sd_softdevice_enable(NRF_CLOCK_LFCLKSRC_XTAL_20_PPM,
+                                             softdevice_assert_handler);
+#endif // BLUETOOTH_LFCLK_RC
+#else
+#if BLUETOOTH_LFCLK_RC
+    nrf_clock_lf_cfg_t clock_config = {
+        .source = NRF_CLOCK_LF_SRC_RC,
+        .rc_ctiv = 16,
+        .rc_temp_ctiv = 2,
+        .xtal_accuracy = 0
+    };
+#else
+    nrf_clock_lf_cfg_t clock_config = {
+        .source = NRF_CLOCK_LF_SRC_XTAL,
+        .rc_ctiv = 0,
+        .rc_temp_ctiv = 0,
+        .xtal_accuracy = NRF_CLOCK_LF_XTAL_ACCURACY_20_PPM
+    };
+#endif
+    uint32_t err_code = sd_softdevice_enable(&clock_config,
+                                             softdevice_assert_handler);
+#endif
+
+    BLE_DRIVER_LOG("SoftDevice enable status: " UINT_FMT "\n", (uint16_t)err_code);
+
+#if NRF51
+    err_code = sd_nvic_EnableIRQ(SWI2_IRQn);
+#else
+    err_code = sd_nvic_EnableIRQ(SWI2_EGU2_IRQn);
+#endif
+
+    BLE_DRIVER_LOG("IRQ enable status: " UINT_FMT "\n", (uint16_t)err_code);
+    
+    // Enable BLE stack.
+    ble_enable_params_t ble_enable_params;
+    memset(&ble_enable_params, 0x00, sizeof(ble_enable_params));
+    ble_enable_params.gatts_enable_params.attr_tab_size = BLE_GATTS_ATTR_TAB_SIZE_DEFAULT;
+    ble_enable_params.gatts_enable_params.service_changed  = 0;
+#if (BLUETOOTH_SD == 132)
+    ble_enable_params.gap_enable_params.periph_conn_count  = 1;
+    ble_enable_params.gap_enable_params.central_conn_count = 1;
+#endif
+
+
+#if (BLUETOOTH_SD == 100) || (BLUETOOTH_SD == 110)
+    err_code = sd_ble_enable(&ble_enable_params);
+#else
+
+#if (BLUETOOTH_SD == 132)
+    uint32_t app_ram_start = 0x200039c0;
+    err_code = sd_ble_enable(&ble_enable_params, &app_ram_start); // 8K SD headroom from linker script.
+    BLE_DRIVER_LOG("BLE ram size: " UINT_FMT "\n", (uint16_t)app_ram_start);
+#else
+    err_code = sd_ble_enable(&ble_enable_params, (uint32_t *)0x20001870);
+#endif
+
+#endif
+
+    BLE_DRIVER_LOG("BLE enable status: " UINT_FMT "\n", (uint16_t)err_code);
+
+    // set up security mode
+    ble_gap_conn_params_t   gap_conn_params;
+    ble_gap_conn_sec_mode_t sec_mode;
+
+    BLE_GAP_CONN_SEC_MODE_SET_OPEN(&sec_mode);
+
+    const char device_name[] = "micr";
+
+    if ((err_code = sd_ble_gap_device_name_set(&sec_mode,
+                                               (const uint8_t *)device_name,
+                                                strlen(device_name))) != 0) {
+        nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError,
+                  "Cannot apply GAP parameters."));
+    }
+
+    // set connection parameters
+    memset(&gap_conn_params, 0, sizeof(gap_conn_params));
+
+    gap_conn_params.min_conn_interval = BLE_MIN_CONN_INTERVAL;
+    gap_conn_params.max_conn_interval = BLE_MAX_CONN_INTERVAL;
+    gap_conn_params.slave_latency     = BLE_SLAVE_LATENCY;
+    gap_conn_params.conn_sup_timeout  = BLE_CONN_SUP_TIMEOUT;
+
+    if (sd_ble_gap_ppcp_set(&gap_conn_params) != 0) {
+
+    nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError,
+              "Cannot set PPCP parameters."));
+    }
+
+    return err_code;
+}
+
+void ble_drv_stack_disable(void) {
+    sd_softdevice_disable();
+}
+
+uint8_t ble_drv_stack_enabled(void) {
+    uint8_t is_enabled;
+    uint32_t err_code = sd_softdevice_is_enabled(&is_enabled);
+    (void)err_code;
+
+    BLE_DRIVER_LOG("Is enabled status: " UINT_FMT "\n", (uint16_t)err_code);
+
+    return is_enabled;
+}
+
+void ble_drv_address_get(ble_drv_addr_t * p_addr) {
+    SD_TEST_OR_ENABLE();
+
+    ble_gap_addr_t local_ble_addr;
+#if (BLUETOOTH_SD == 132 && BLE_API_VERSION == 3)
+    uint32_t err_code = sd_ble_gap_addr_get(&local_ble_addr);
+#else
+    uint32_t err_code = sd_ble_gap_address_get(&local_ble_addr);
+#endif
+
+    if (err_code != 0) {
+        nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError,
+                  "Can not query for the device address."));
+    }
+
+    BLE_DRIVER_LOG("ble address, type: " HEX2_FMT ", " \
+                   "address: " HEX2_FMT ":" HEX2_FMT ":" HEX2_FMT ":" \
+                               HEX2_FMT ":" HEX2_FMT ":" HEX2_FMT "\n", \
+                   local_ble_addr.addr_type, \
+                   local_ble_addr.addr[5], local_ble_addr.addr[4], local_ble_addr.addr[3], \
+                   local_ble_addr.addr[2], local_ble_addr.addr[1], local_ble_addr.addr[0]);
+
+    p_addr->addr_type = local_ble_addr.addr_type;
+    memcpy(p_addr->addr, local_ble_addr.addr, 6);
+}
+
+bool ble_drv_uuid_add_vs(uint8_t * p_uuid, uint8_t * idx) {
+    SD_TEST_OR_ENABLE();
+
+    if (sd_ble_uuid_vs_add((ble_uuid128_t const *)p_uuid, idx) != 0) {
+        nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError,
+                  "Can not add Vendor Specific 128-bit UUID."));
+    }
+
+    return true;
+}
+
+bool ble_drv_service_add(ubluepy_service_obj_t * p_service_obj) {
+    SD_TEST_OR_ENABLE();
+
+    if (p_service_obj->p_uuid->type > BLE_UUID_TYPE_BLE) {
+
+        ble_uuid_t uuid;
+        uuid.type  = p_service_obj->p_uuid->uuid_vs_idx;
+        uuid.uuid  = p_service_obj->p_uuid->value[0];
+        uuid.uuid += p_service_obj->p_uuid->value[1] << 8;
+
+        if (sd_ble_gatts_service_add(p_service_obj->type,
+                                     &uuid,
+                                     &p_service_obj->handle) != 0) {
+            nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError,
+                      "Can not add Service."));
+        }
+    } else if (p_service_obj->p_uuid->type == BLE_UUID_TYPE_BLE) {
+        BLE_DRIVER_LOG("adding service\n");
+
+        ble_uuid_t uuid;
+        uuid.type  = p_service_obj->p_uuid->type;
+        uuid.uuid  = p_service_obj->p_uuid->value[0];
+        uuid.uuid += p_service_obj->p_uuid->value[1] << 8;
+
+        if (sd_ble_gatts_service_add(p_service_obj->type,
+                                     &uuid,
+                                     &p_service_obj->handle) != 0) {
+            nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError,
+                      "Can not add Service."));
+        }
+    }
+    return true;
+}
+
+bool ble_drv_characteristic_add(ubluepy_characteristic_obj_t * p_char_obj) {
+    ble_gatts_char_md_t char_md;
+    ble_gatts_attr_md_t cccd_md;
+    ble_gatts_attr_t    attr_char_value;
+    ble_uuid_t          uuid;
+    ble_gatts_attr_md_t attr_md;
+
+    memset(&char_md, 0, sizeof(char_md));
+
+    char_md.char_props.broadcast      = (p_char_obj->props & UBLUEPY_PROP_BROADCAST) ? 1 : 0;
+    char_md.char_props.read           = (p_char_obj->props & UBLUEPY_PROP_READ) ? 1 : 0;
+    char_md.char_props.write_wo_resp  = (p_char_obj->props & UBLUEPY_PROP_WRITE_WO_RESP) ? 1 : 0;
+    char_md.char_props.write          = (p_char_obj->props & UBLUEPY_PROP_WRITE) ? 1 : 0;
+    char_md.char_props.notify         = (p_char_obj->props & UBLUEPY_PROP_NOTIFY) ? 1 : 0;
+    char_md.char_props.indicate       = (p_char_obj->props & UBLUEPY_PROP_INDICATE) ? 1 : 0;
+#if 0
+    char_md.char_props.auth_signed_wr = (p_char_obj->props & UBLUEPY_PROP_NOTIFY) ? 1 : 0;
+#endif
+
+
+    char_md.p_char_user_desc  = NULL;
+    char_md.p_char_pf         = NULL;
+    char_md.p_user_desc_md    = NULL;
+    char_md.p_sccd_md         = NULL;
+
+    // if cccd
+    if (p_char_obj->attrs & UBLUEPY_ATTR_CCCD) {
+        memset(&cccd_md, 0, sizeof(cccd_md));
+        BLE_GAP_CONN_SEC_MODE_SET_OPEN(&cccd_md.read_perm);
+        BLE_GAP_CONN_SEC_MODE_SET_OPEN(&cccd_md.write_perm);
+        cccd_md.vloc = BLE_GATTS_VLOC_STACK;
+        char_md.p_cccd_md = &cccd_md;
+    } else {
+        char_md.p_cccd_md = NULL;
+    }
+
+    uuid.type  = p_char_obj->p_uuid->type;
+    uuid.uuid  = p_char_obj->p_uuid->value[0];
+    uuid.uuid += p_char_obj->p_uuid->value[1] << 8;
+
+    memset(&attr_md, 0, sizeof(attr_md));
+
+    BLE_GAP_CONN_SEC_MODE_SET_OPEN(&attr_md.read_perm);
+    BLE_GAP_CONN_SEC_MODE_SET_OPEN(&attr_md.write_perm);
+
+    attr_md.vloc    = BLE_GATTS_VLOC_STACK;
+    attr_md.rd_auth = 0;
+    attr_md.wr_auth = 0;
+    attr_md.vlen    = 1;
+
+    memset(&attr_char_value, 0, sizeof(attr_char_value));
+
+    attr_char_value.p_uuid    = &uuid;
+    attr_char_value.p_attr_md = &attr_md;
+    attr_char_value.init_len  = sizeof(uint8_t);
+    attr_char_value.init_offs = 0;
+    attr_char_value.max_len   = (GATT_MTU_SIZE_DEFAULT - 3);
+
+    ble_gatts_char_handles_t handles;
+
+    if (sd_ble_gatts_characteristic_add(p_char_obj->service_handle,
+                                        &char_md,
+                                        &attr_char_value,
+                                        &handles) != 0) {
+        nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError,
+                  "Can not add Characteristic."));
+    }
+
+    // apply handles to object instance
+    p_char_obj->handle           = handles.value_handle;
+    p_char_obj->user_desc_handle = handles.user_desc_handle;
+    p_char_obj->cccd_handle      = handles.cccd_handle;
+    p_char_obj->sccd_handle      = handles.sccd_handle;
+
+    return true;
+}
+
+bool ble_drv_advertise_data(ubluepy_advertise_data_t * p_adv_params) {
+    SD_TEST_OR_ENABLE();
+
+    uint8_t byte_pos = 0;
+
+    uint8_t adv_data[BLE_GAP_ADV_MAX_SIZE];
+
+    if (p_adv_params->device_name_len > 0) {
+        ble_gap_conn_sec_mode_t sec_mode;
+
+        BLE_GAP_CONN_SEC_MODE_SET_OPEN(&sec_mode);
+
+        if (sd_ble_gap_device_name_set(&sec_mode,
+                                       p_adv_params->p_device_name,
+                                       p_adv_params->device_name_len) != 0) {
+            nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError,
+	              "Can not apply device name in the stack."));
+        }
+
+        BLE_DRIVER_LOG("Device name applied\n");
+
+        adv_data[byte_pos] = (BLE_ADV_AD_TYPE_FIELD_SIZE + p_adv_params->device_name_len);
+        byte_pos += BLE_ADV_LENGTH_FIELD_SIZE;
+        adv_data[byte_pos] = BLE_GAP_AD_TYPE_COMPLETE_LOCAL_NAME;
+        byte_pos += BLE_ADV_AD_TYPE_FIELD_SIZE;
+        memcpy(&adv_data[byte_pos], p_adv_params->p_device_name, p_adv_params->device_name_len);
+        // increment position counter to see if it fits, and in case more content should
+        // follow in this adv packet.
+        byte_pos += p_adv_params->device_name_len;
+    }
+
+    // Add FLAGS only if manually controlled data has not been used.
+    if (p_adv_params->data_len == 0) {
+        // set flags, default to disc mode
+        adv_data[byte_pos] = (BLE_ADV_AD_TYPE_FIELD_SIZE + BLE_AD_TYPE_FLAGS_DATA_SIZE);
+        byte_pos += BLE_ADV_LENGTH_FIELD_SIZE;
+        adv_data[byte_pos] = BLE_GAP_AD_TYPE_FLAGS;
+        byte_pos += BLE_AD_TYPE_FLAGS_DATA_SIZE;
+        adv_data[byte_pos] = BLE_GAP_ADV_FLAGS_LE_ONLY_GENERAL_DISC_MODE;
+        byte_pos += 1;
+    }
+
+    if (p_adv_params->num_of_services > 0) {
+
+        bool type_16bit_present  = false;
+        bool type_128bit_present = false;
+
+        for (uint8_t i = 0; i < p_adv_params->num_of_services; i++) {
+            ubluepy_service_obj_t * p_service = (ubluepy_service_obj_t *)p_adv_params->p_services[i];
+            if (p_service->p_uuid->type == UBLUEPY_UUID_16_BIT) {
+                type_16bit_present = true;
+            }
+
+            if (p_service->p_uuid->type == UBLUEPY_UUID_128_BIT) {
+                type_128bit_present = true;
+            }
+        }
+
+        if (type_16bit_present) {
+            uint8_t size_byte_pos = byte_pos;
+
+            // skip length byte for now, apply total length post calculation
+            byte_pos += BLE_ADV_LENGTH_FIELD_SIZE;
+
+            adv_data[byte_pos] = BLE_GAP_AD_TYPE_16BIT_SERVICE_UUID_COMPLETE;
+            byte_pos += BLE_ADV_AD_TYPE_FIELD_SIZE;
+
+            uint8_t uuid_total_size = 0;
+            uint8_t encoded_size    = 0;
+
+            for (uint8_t i = 0; i < p_adv_params->num_of_services; i++) {
+                ubluepy_service_obj_t * p_service = (ubluepy_service_obj_t *)p_adv_params->p_services[i];
+
+                ble_uuid_t uuid;
+                uuid.type  = p_service->p_uuid->type;
+                uuid.uuid  = p_service->p_uuid->value[0];
+                uuid.uuid += p_service->p_uuid->value[1] << 8;
+                // calculate total size of uuids
+                if (sd_ble_uuid_encode(&uuid, &encoded_size, NULL) != 0) {
+                    nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError,
+                              "Can not encode UUID, to check length."));
+                }
+
+                // do encoding into the adv buffer
+                if (sd_ble_uuid_encode(&uuid, &encoded_size, &adv_data[byte_pos]) != 0) {
+                    nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError,
+                              "Can encode UUID into the advertisment packet."));
+                }
+
+                BLE_DRIVER_LOG("encoded uuid for service %u: ", 0);
+                for (uint8_t j = 0; j < encoded_size; j++) {
+                    BLE_DRIVER_LOG(HEX2_FMT " ", adv_data[byte_pos + j]);
+                }
+                BLE_DRIVER_LOG("\n");
+
+                uuid_total_size += encoded_size; // size of entry
+                byte_pos        += encoded_size; // relative to adv data packet
+                BLE_DRIVER_LOG("ADV: uuid size: %u, type: %u, uuid: %x%x, vs_idx: %u\n",
+                       encoded_size, p_service->p_uuid->type,
+                       p_service->p_uuid->value[1],
+                       p_service->p_uuid->value[0],
+                       p_service->p_uuid->uuid_vs_idx);
+            }
+
+            adv_data[size_byte_pos] = (BLE_ADV_AD_TYPE_FIELD_SIZE + uuid_total_size);
+        }
+
+        if (type_128bit_present) {
+            uint8_t size_byte_pos = byte_pos;
+
+            // skip length byte for now, apply total length post calculation
+            byte_pos += BLE_ADV_LENGTH_FIELD_SIZE;
+
+            adv_data[byte_pos] = BLE_GAP_AD_TYPE_128BIT_SERVICE_UUID_COMPLETE;
+            byte_pos += BLE_ADV_AD_TYPE_FIELD_SIZE;
+
+            uint8_t uuid_total_size = 0;
+            uint8_t encoded_size    = 0;
+
+            for (uint8_t i = 0; i < p_adv_params->num_of_services; i++) {
+                ubluepy_service_obj_t * p_service = (ubluepy_service_obj_t *)p_adv_params->p_services[i];
+
+                ble_uuid_t uuid;
+                uuid.type  = p_service->p_uuid->uuid_vs_idx;
+                uuid.uuid  = p_service->p_uuid->value[0];
+                uuid.uuid += p_service->p_uuid->value[1] << 8;
+
+                // calculate total size of uuids
+                if (sd_ble_uuid_encode(&uuid, &encoded_size, NULL) != 0) {
+                    nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError,
+                              "Can not encode UUID, to check length."));
+                }
+
+                // do encoding into the adv buffer
+                if (sd_ble_uuid_encode(&uuid, &encoded_size, &adv_data[byte_pos]) != 0) {
+                    nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError,
+                              "Can encode UUID into the advertisment packet."));
+                }
+
+                BLE_DRIVER_LOG("encoded uuid for service %u: ", 0);
+                for (uint8_t j = 0; j < encoded_size; j++) {
+                    BLE_DRIVER_LOG(HEX2_FMT " ", adv_data[byte_pos + j]);
+                }
+                BLE_DRIVER_LOG("\n");
+
+                uuid_total_size += encoded_size; // size of entry
+                byte_pos        += encoded_size; // relative to adv data packet
+                BLE_DRIVER_LOG("ADV: uuid size: %u, type: %x%x, uuid: %u, vs_idx: %u\n",
+                       encoded_size, p_service->p_uuid->type,
+                       p_service->p_uuid->value[1],
+                       p_service->p_uuid->value[0],
+                       p_service->p_uuid->uuid_vs_idx);
+            }
+
+            adv_data[size_byte_pos] = (BLE_ADV_AD_TYPE_FIELD_SIZE + uuid_total_size);
+        }
+    }
+
+    if ((p_adv_params->data_len > 0) && (p_adv_params->p_data != NULL)) {
+        if (p_adv_params->data_len + byte_pos > BLE_GAP_ADV_MAX_SIZE) {
+            nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError,
+                      "Can not fit data into the advertisment packet."));
+        }
+
+        memcpy(adv_data, p_adv_params->p_data, p_adv_params->data_len);
+        byte_pos += p_adv_params->data_len;
+    }
+
+    // scan response data not set
+    uint32_t err_code;
+    if ((err_code = sd_ble_gap_adv_data_set(adv_data, byte_pos, NULL, 0)) != 0) {
+        nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError,
+                  "Can not apply advertisment data. status: 0x" HEX2_FMT, (uint16_t)err_code));
+    }
+    BLE_DRIVER_LOG("Set Adv data size: " UINT_FMT "\n", byte_pos);
+
+    static ble_gap_adv_params_t m_adv_params;
+
+    // initialize advertising params
+    memset(&m_adv_params, 0, sizeof(m_adv_params));
+    if (p_adv_params->connectable) {
+        m_adv_params.type        = BLE_GAP_ADV_TYPE_ADV_IND;
+    } else {
+        m_adv_params.type        = BLE_GAP_ADV_TYPE_ADV_NONCONN_IND;
+    }
+
+    m_adv_params.p_peer_addr = NULL;                                // undirected advertisement
+    m_adv_params.fp          = BLE_GAP_ADV_FP_ANY;
+    m_adv_params.interval    = MSEC_TO_UNITS(100, UNIT_0_625_MS);   // approx 8 ms
+    m_adv_params.timeout     = 0;                                   // infinite advertisment
+
+    ble_drv_advertise_stop();
+
+    err_code = sd_ble_gap_adv_start(&m_adv_params);
+    if (err_code != 0) {
+        nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError,
+                  "Can not start advertisment. status: 0x" HEX2_FMT, (uint16_t)err_code));
+    }
+
+    m_adv_in_progress = true;
+
+    return true;
+}
+
+void ble_drv_advertise_stop(void) {
+    if (m_adv_in_progress == true) {
+        uint32_t err_code;
+        if ((err_code = sd_ble_gap_adv_stop()) != 0) {
+            nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError,
+                      "Can not stop advertisment. status: 0x" HEX2_FMT, (uint16_t)err_code));
+        }
+    }
+    m_adv_in_progress = false;
+}
+
+void ble_drv_attr_s_read(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data) {
+    ble_gatts_value_t gatts_value;
+    memset(&gatts_value, 0, sizeof(gatts_value));
+
+    gatts_value.len     = len;
+    gatts_value.offset  = 0;
+    gatts_value.p_value = p_data;
+
+    uint32_t err_code = sd_ble_gatts_value_get(conn_handle,
+                                               handle,
+                                               &gatts_value);
+    if (err_code != 0) {
+        nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError,
+                  "Can not read attribute value. status: 0x" HEX2_FMT, (uint16_t)err_code));
+    }
+
+}
+
+void ble_drv_attr_s_write(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data) {
+    ble_gatts_value_t gatts_value;
+    memset(&gatts_value, 0, sizeof(gatts_value));
+
+    gatts_value.len     = len;
+    gatts_value.offset  = 0;
+    gatts_value.p_value = p_data;
+
+    uint32_t err_code = sd_ble_gatts_value_set(conn_handle, handle, &gatts_value);
+
+    if (err_code != 0) {
+        nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError,
+                  "Can not write attribute value. status: 0x" HEX2_FMT, (uint16_t)err_code));
+    }
+}
+
+void ble_drv_attr_s_notify(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data) {
+    uint16_t               hvx_len = len;
+    ble_gatts_hvx_params_t hvx_params;
+
+    memset(&hvx_params, 0, sizeof(hvx_params));
+
+    hvx_params.handle = handle;
+    hvx_params.type   = BLE_GATT_HVX_NOTIFICATION;
+    hvx_params.offset = 0;
+    hvx_params.p_len  = &hvx_len;
+    hvx_params.p_data = p_data;
+
+    while (m_tx_in_progress) {
+        ;
+    }
+
+    m_tx_in_progress = true;
+    uint32_t err_code;
+    if ((err_code = sd_ble_gatts_hvx(conn_handle, &hvx_params)) != 0) {
+        nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError,
+                  "Can not notify attribute value. status: 0x" HEX2_FMT, (uint16_t)err_code));
+    }
+}
+
+void ble_drv_gap_event_handler_set(mp_obj_t obj, ble_drv_gap_evt_callback_t evt_handler) {
+    mp_gap_observer = obj;
+    gap_event_handler = evt_handler;
+}
+
+void ble_drv_gatts_event_handler_set(mp_obj_t obj, ble_drv_gatts_evt_callback_t evt_handler) {
+    mp_gatts_observer = obj;
+    gatts_event_handler = evt_handler;
+}
+
+#if (BLUETOOTH_SD == 130) || (BLUETOOTH_SD == 132)
+
+void ble_drv_gattc_event_handler_set(mp_obj_t obj, ble_drv_gattc_evt_callback_t evt_handler) {
+    mp_gattc_observer = obj;
+    gattc_event_handler = evt_handler;
+}
+
+void ble_drv_adv_report_handler_set(mp_obj_t obj, ble_drv_adv_evt_callback_t evt_handler) {
+    mp_adv_observer = obj;
+    adv_event_handler = evt_handler;
+}
+
+
+void ble_drv_attr_c_read(uint16_t conn_handle, uint16_t handle, mp_obj_t obj, ble_drv_gattc_char_data_callback_t cb) {
+
+    mp_gattc_char_data_observer = obj;
+    gattc_char_data_handle = cb;
+
+    uint32_t err_code = sd_ble_gattc_read(conn_handle,
+                                          handle,
+                                          0);
+    if (err_code != 0) {
+        nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError,
+                  "Can not read attribute value. status: 0x" HEX2_FMT, (uint16_t)err_code));
+    }
+
+    while (gattc_char_data_handle != NULL) {
+        ;
+    }
+}
+
+void ble_drv_attr_c_write(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data, bool w_response) {
+
+    ble_gattc_write_params_t write_params;
+
+    if (w_response) {
+            write_params.write_op = BLE_GATT_OP_WRITE_REQ;
+    } else {
+        write_params.write_op = BLE_GATT_OP_WRITE_CMD;
+    }
+
+    write_params.flags    = BLE_GATT_EXEC_WRITE_FLAG_PREPARED_CANCEL;
+    write_params.handle   = handle;
+    write_params.offset   = 0;
+    write_params.len      = len;
+    write_params.p_value  = p_data;
+
+    m_write_done = !w_response;
+
+    uint32_t err_code = sd_ble_gattc_write(conn_handle, &write_params);
+
+    if (err_code != 0) {
+        nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError,
+            "Can not write attribute value. status: 0x" HEX2_FMT, (uint16_t)err_code));
+    }
+
+    while (m_write_done != true) {
+        ;
+    }
+}
+
+void ble_drv_scan_start(void) {
+    SD_TEST_OR_ENABLE();
+
+    ble_gap_scan_params_t scan_params;
+    scan_params.active   = 1;
+    scan_params.interval = MSEC_TO_UNITS(100, UNIT_0_625_MS);
+    scan_params.window   = MSEC_TO_UNITS(100, UNIT_0_625_MS);
+    scan_params.timeout  = 0; // Infinite
+
+#if (BLUETOOTH_SD == 130)
+    scan_params.selective   = 0;
+    scan_params.p_whitelist = NULL;
+#elif (BLUETOOTH_SD == 132 && BLE_API_VERSION == 3)
+    scan_params.use_whitelist = 0;
+#endif
+
+    uint32_t err_code;
+    if ((err_code = sd_ble_gap_scan_start(&scan_params)) != 0) {
+        nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError,
+                  "Can not start scanning. status: 0x" HEX2_FMT, (uint16_t)err_code));
+    }
+}
+
+void ble_drv_scan_stop(void) {
+    sd_ble_gap_scan_stop();
+}
+
+void ble_drv_connect(uint8_t * p_addr, uint8_t addr_type) {
+    SD_TEST_OR_ENABLE();
+
+    ble_gap_scan_params_t scan_params;
+    scan_params.active   = 1;
+    scan_params.interval = MSEC_TO_UNITS(100, UNIT_0_625_MS);
+    scan_params.window   = MSEC_TO_UNITS(100, UNIT_0_625_MS);
+    scan_params.timeout  = 0; // infinite
+
+#if (BLUETOOTH_SD == 130)
+    scan_params.selective   = 0;
+    scan_params.p_whitelist = NULL;
+#elif (BLUETOOTH_SD == 132 && BLE_API_VERSION == 3)
+    scan_params.use_whitelist = 0;
+#endif
+
+    ble_gap_addr_t addr;
+    memset(&addr, 0, sizeof(addr));
+
+    addr.addr_type = addr_type;
+    memcpy(addr.addr, p_addr, 6);
+
+    BLE_DRIVER_LOG("GAP CONNECTING: "HEX2_FMT":"HEX2_FMT":"HEX2_FMT":"HEX2_FMT":"HEX2_FMT":"HEX2_FMT", type: %d\n",
+                   addr.addr[0], addr.addr[1], addr.addr[2], addr.addr[3], addr.addr[4], addr.addr[5], addr.addr_type);
+
+    ble_gap_conn_params_t conn_params;
+
+//  (void)sd_ble_gap_ppcp_get(&conn_params);
+
+    // set connection parameters
+    memset(&conn_params, 0, sizeof(conn_params));
+
+    conn_params.min_conn_interval = BLE_MIN_CONN_INTERVAL;
+    conn_params.max_conn_interval = BLE_MAX_CONN_INTERVAL;
+    conn_params.slave_latency     = BLE_SLAVE_LATENCY;
+    conn_params.conn_sup_timeout  = BLE_CONN_SUP_TIMEOUT;
+
+    uint32_t err_code;
+    if ((err_code = sd_ble_gap_connect(&addr, &scan_params, &conn_params)) != 0) {
+        nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError,
+                  "Can not connect. status: 0x" HEX2_FMT, (uint16_t)err_code));
+    }
+}
+
+bool ble_drv_discover_services(mp_obj_t obj, uint16_t conn_handle, uint16_t start_handle, ble_drv_disc_add_service_callback_t cb) {
+    BLE_DRIVER_LOG("Discover primary services. Conn handle: 0x" HEX2_FMT "\n",
+                   conn_handle);
+
+    mp_gattc_disc_service_observer = obj;
+    disc_add_service_handler = cb;
+
+    m_primary_service_found = false;
+
+    uint32_t err_code;
+    err_code = sd_ble_gattc_primary_services_discover(conn_handle,
+                                                      start_handle,
+                                                      NULL);
+    if (err_code != 0) {
+        return false;
+    }
+
+    // busy loop until last service has been iterated
+    while (disc_add_service_handler != NULL) {
+        ;
+    }
+
+    if (m_primary_service_found) {
+        return true;
+    } else {
+        return false;
+    }
+}
+
+bool ble_drv_discover_characteristic(mp_obj_t obj,
+                                     uint16_t conn_handle,
+                                     uint16_t start_handle,
+                                     uint16_t end_handle,
+                                     ble_drv_disc_add_char_callback_t cb) {
+    BLE_DRIVER_LOG("Discover characteristicts. Conn handle: 0x" HEX2_FMT "\n",
+                   conn_handle);
+
+    mp_gattc_disc_char_observer = obj;
+    disc_add_char_handler = cb;
+
+    ble_gattc_handle_range_t handle_range;
+    handle_range.start_handle = start_handle;
+    handle_range.end_handle   = end_handle;
+
+    m_characteristic_found = false;
+
+    uint32_t err_code;
+    err_code = sd_ble_gattc_characteristics_discover(conn_handle, &handle_range);
+    if (err_code != 0) {
+        return false;
+    }
+
+    // busy loop until last service has been iterated
+    while (disc_add_char_handler != NULL) {
+        ;
+    }
+
+    if (m_characteristic_found) {
+        return true;
+    } else {
+        return false;
+    }
+}
+
+void ble_drv_discover_descriptors(void) {
+
+}
+
+#endif
+
+static void ble_evt_handler(ble_evt_t * p_ble_evt) {
+// S132 event ranges.
+// Common 0x01 -> 0x0F
+// GAP    0x10 -> 0x2F
+// GATTC  0x30 -> 0x4F
+// GATTS  0x50 -> 0x6F
+// L2CAP  0x70 -> 0x8F
+    switch (p_ble_evt->header.evt_id) {
+        case BLE_GAP_EVT_CONNECTED:
+            BLE_DRIVER_LOG("GAP CONNECT\n");
+            m_adv_in_progress = false;
+            gap_event_handler(mp_gap_observer, p_ble_evt->header.evt_id, p_ble_evt->evt.gap_evt.conn_handle, p_ble_evt->header.evt_len - (2 * sizeof(uint16_t)), NULL);
+
+            ble_gap_conn_params_t conn_params;
+            (void)sd_ble_gap_ppcp_get(&conn_params);
+            (void)sd_ble_gap_conn_param_update(p_ble_evt->evt.gap_evt.conn_handle, &conn_params);
+            break;
+
+        case BLE_GAP_EVT_DISCONNECTED:
+            BLE_DRIVER_LOG("GAP DISCONNECT\n");
+            gap_event_handler(mp_gap_observer, p_ble_evt->header.evt_id, p_ble_evt->evt.gap_evt.conn_handle, p_ble_evt->header.evt_len - (2 * sizeof(uint16_t)), NULL);
+            break;
+
+        case BLE_GATTS_EVT_HVC:
+            gatts_event_handler(mp_gatts_observer, p_ble_evt->header.evt_id, p_ble_evt->evt.gatts_evt.params.hvc.handle, p_ble_evt->header.evt_len - (2 * sizeof(uint16_t)), NULL);
+            break;
+
+        case BLE_GATTS_EVT_WRITE:
+            BLE_DRIVER_LOG("GATTS write\n");
+
+            uint16_t  handle   = p_ble_evt->evt.gatts_evt.params.write.handle;
+            uint16_t  data_len = p_ble_evt->evt.gatts_evt.params.write.len;
+            uint8_t * p_data   = &p_ble_evt->evt.gatts_evt.params.write.data[0];
+
+            gatts_event_handler(mp_gatts_observer, p_ble_evt->header.evt_id, handle, data_len, p_data);
+            break;
+
+        case BLE_GAP_EVT_CONN_PARAM_UPDATE:
+            BLE_DRIVER_LOG("GAP CONN PARAM UPDATE\n");
+            break;
+
+        case BLE_GATTS_EVT_SYS_ATTR_MISSING:
+            // No system attributes have been stored.
+            (void)sd_ble_gatts_sys_attr_set(p_ble_evt->evt.gatts_evt.conn_handle, NULL, 0, 0);
+            break;
+
+#if (BLUETOOTH_SD == 132 && BLE_API_VERSION == 3)
+        case BLE_GATTS_EVT_EXCHANGE_MTU_REQUEST:
+            BLE_DRIVER_LOG("GATTS EVT EXCHANGE MTU REQUEST\n");
+            (void)sd_ble_gatts_exchange_mtu_reply(p_ble_evt->evt.gatts_evt.conn_handle, 23); // MAX MTU size
+            break;
+#endif
+
+        case BLE_EVT_TX_COMPLETE:
+            BLE_DRIVER_LOG("BLE EVT TX COMPLETE\n");
+            m_tx_in_progress = false;
+            break;
+
+        case BLE_GAP_EVT_SEC_PARAMS_REQUEST:
+            BLE_DRIVER_LOG("BLE EVT SEC PARAMS REQUEST\n");
+            // pairing not supported
+            (void)sd_ble_gap_sec_params_reply(p_ble_evt->evt.gatts_evt.conn_handle,
+                                              BLE_GAP_SEC_STATUS_PAIRING_NOT_SUPP,
+                                              NULL, NULL);
+            break;
+
+#if (BLUETOOTH_SD == 130) || (BLUETOOTH_SD == 132)
+        case BLE_GAP_EVT_ADV_REPORT:
+            BLE_DRIVER_LOG("BLE EVT ADV REPORT\n");
+            ble_drv_adv_data_t adv_data = {
+                .p_peer_addr  = p_ble_evt->evt.gap_evt.params.adv_report.peer_addr.addr,
+                .addr_type    = p_ble_evt->evt.gap_evt.params.adv_report.peer_addr.addr_type,
+                .is_scan_resp = p_ble_evt->evt.gap_evt.params.adv_report.scan_rsp,
+                .rssi         = p_ble_evt->evt.gap_evt.params.adv_report.rssi,
+                .data_len     = p_ble_evt->evt.gap_evt.params.adv_report.dlen,
+                .p_data       = p_ble_evt->evt.gap_evt.params.adv_report.data,
+                .adv_type     = p_ble_evt->evt.gap_evt.params.adv_report.type
+            };
+
+            // TODO: Fix unsafe callback to possible undefined callback...
+            adv_event_handler(mp_adv_observer,
+                              p_ble_evt->header.evt_id,
+                              &adv_data);
+            break;
+
+        case BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST:
+            BLE_DRIVER_LOG("BLE EVT CONN PARAM UPDATE REQUEST\n");
+
+            (void)sd_ble_gap_conn_param_update(p_ble_evt->evt.gap_evt.conn_handle,
+                                               &p_ble_evt->evt.gap_evt.params.conn_param_update_request.conn_params);
+            break;
+
+        case BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP:
+            BLE_DRIVER_LOG("BLE EVT PRIMARY SERVICE DISCOVERY RESPONSE\n");
+            BLE_DRIVER_LOG(">>> service count: %d\n", p_ble_evt->evt.gattc_evt.params.prim_srvc_disc_rsp.count);
+
+            for (uint16_t i = 0; i < p_ble_evt->evt.gattc_evt.params.prim_srvc_disc_rsp.count; i++) {
+                ble_gattc_service_t * p_service = &p_ble_evt->evt.gattc_evt.params.prim_srvc_disc_rsp.services[i];
+
+                ble_drv_service_data_t service;
+                service.uuid_type    = p_service->uuid.type;
+                service.uuid         = p_service->uuid.uuid;
+                service.start_handle = p_service->handle_range.start_handle;
+                service.end_handle   = p_service->handle_range.end_handle;
+
+                disc_add_service_handler(mp_gattc_disc_service_observer, &service);
+            }
+
+            if (p_ble_evt->evt.gattc_evt.params.prim_srvc_disc_rsp.count > 0) {
+                m_primary_service_found = true;
+            }
+
+            // mark end of service discovery
+            disc_add_service_handler = NULL;
+
+            break;
+
+        case BLE_GATTC_EVT_CHAR_DISC_RSP:
+            BLE_DRIVER_LOG("BLE EVT CHAR DISCOVERY RESPONSE\n");
+            BLE_DRIVER_LOG(">>> characteristic count: %d\n", p_ble_evt->evt.gattc_evt.params.char_disc_rsp.count);
+
+            for (uint16_t i = 0; i < p_ble_evt->evt.gattc_evt.params.char_disc_rsp.count; i++) {
+                ble_gattc_char_t * p_char = &p_ble_evt->evt.gattc_evt.params.char_disc_rsp.chars[i];
+
+                ble_drv_char_data_t char_data;
+                char_data.uuid_type    = p_char->uuid.type;
+                char_data.uuid         = p_char->uuid.uuid;
+                char_data.decl_handle  = p_char->handle_decl;
+                char_data.value_handle = p_char->handle_value;
+
+                char_data.props |= (p_char->char_props.broadcast) ? UBLUEPY_PROP_BROADCAST : 0;
+                char_data.props |= (p_char->char_props.read) ? UBLUEPY_PROP_READ : 0;
+                char_data.props |= (p_char->char_props.write_wo_resp) ? UBLUEPY_PROP_WRITE_WO_RESP : 0;
+                char_data.props |= (p_char->char_props.write) ? UBLUEPY_PROP_WRITE : 0;
+                char_data.props |= (p_char->char_props.notify) ? UBLUEPY_PROP_NOTIFY : 0;
+                char_data.props |= (p_char->char_props.indicate) ? UBLUEPY_PROP_INDICATE : 0;
+            #if 0
+                char_data.props |= (p_char->char_props.auth_signed_wr) ? UBLUEPY_PROP_NOTIFY : 0;
+            #endif
+
+                disc_add_char_handler(mp_gattc_disc_char_observer, &char_data);
+            }
+
+            if (p_ble_evt->evt.gattc_evt.params.char_disc_rsp.count > 0) {
+                m_characteristic_found = true;
+            }
+
+            // mark end of characteristic discovery
+            disc_add_char_handler = NULL;
+
+            break;
+
+        case BLE_GATTC_EVT_READ_RSP:
+            BLE_DRIVER_LOG("BLE EVT READ RESPONSE, offset: 0x"HEX2_FMT", length: 0x"HEX2_FMT"\n",
+                           p_ble_evt->evt.gattc_evt.params.read_rsp.offset,
+                           p_ble_evt->evt.gattc_evt.params.read_rsp.len);
+
+            gattc_char_data_handle(mp_gattc_char_data_observer,
+                                   p_ble_evt->evt.gattc_evt.params.read_rsp.len,
+                                   p_ble_evt->evt.gattc_evt.params.read_rsp.data);
+
+            // mark end of read
+            gattc_char_data_handle = NULL;
+
+            break;
+
+        case BLE_GATTC_EVT_WRITE_RSP:
+            BLE_DRIVER_LOG("BLE EVT WRITE RESPONSE\n");
+            m_write_done = true;
+            break;
+
+        case BLE_GATTC_EVT_HVX:
+            BLE_DRIVER_LOG("BLE EVT HVX RESPONSE\n");
+            break;
+#endif
+
+        default:
+            BLE_DRIVER_LOG(">>> unhandled evt: 0x" HEX2_FMT "\n", p_ble_evt->header.evt_id);
+            break;
+    }
+}
+
+static uint8_t m_ble_evt_buf[sizeof(ble_evt_t) + (GATT_MTU_SIZE_DEFAULT)] __attribute__ ((aligned (4)));
+
+#ifdef NRF51
+void SWI2_IRQHandler(void) {
+#else
+void SWI2_EGU2_IRQHandler(void) {
+#endif
+
+    uint32_t evt_id;
+    uint32_t err_code;
+    do {
+        err_code = sd_evt_get(&evt_id);
+        // TODO: handle non ble events
+    } while (err_code != NRF_ERROR_NOT_FOUND && err_code != NRF_SUCCESS);
+
+    uint16_t evt_len = sizeof(m_ble_evt_buf);
+    do {
+        err_code = sd_ble_evt_get(m_ble_evt_buf, &evt_len);
+        ble_evt_handler((ble_evt_t *)m_ble_evt_buf);
+    } while (err_code != NRF_ERROR_NOT_FOUND && err_code != NRF_SUCCESS);
+}
+
+#endif // BLUETOOTH_SD
diff --git a/ports/nrf/drivers/bluetooth/ble_drv.h b/ports/nrf/drivers/bluetooth/ble_drv.h
new file mode 100644
index 0000000000..d8b7154671
--- /dev/null
+++ b/ports/nrf/drivers/bluetooth/ble_drv.h
@@ -0,0 +1,129 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef BLUETOOTH_LE_DRIVER_H__
+#define BLUETOOTH_LE_DRIVER_H__
+
+#if BLUETOOTH_SD
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "modubluepy.h"
+
+typedef struct {
+    uint8_t   addr[6];
+    uint8_t   addr_type;
+} ble_drv_addr_t;
+
+typedef struct {
+    uint8_t * p_peer_addr;
+    uint8_t   addr_type;
+    bool      is_scan_resp;
+    int8_t    rssi;
+    uint8_t   data_len;
+    uint8_t * p_data;
+    uint8_t   adv_type;
+} ble_drv_adv_data_t;
+
+typedef struct {
+    uint16_t uuid;
+    uint8_t  uuid_type;
+    uint16_t start_handle;
+    uint16_t end_handle;
+} ble_drv_service_data_t;
+
+typedef struct {
+    uint16_t uuid;
+    uint8_t  uuid_type;
+    uint8_t  props;
+    uint16_t decl_handle;
+    uint16_t value_handle;
+} ble_drv_char_data_t;
+
+typedef void (*ble_drv_gap_evt_callback_t)(mp_obj_t self, uint16_t event_id, uint16_t conn_handle, uint16_t length, uint8_t * data);
+typedef void (*ble_drv_gatts_evt_callback_t)(mp_obj_t self, uint16_t event_id, uint16_t attr_handle, uint16_t length, uint8_t * data);
+typedef void (*ble_drv_gattc_evt_callback_t)(mp_obj_t self, uint16_t event_id, uint16_t attr_handle, uint16_t length, uint8_t * data);
+typedef void (*ble_drv_adv_evt_callback_t)(mp_obj_t self, uint16_t event_id, ble_drv_adv_data_t * data);
+typedef void (*ble_drv_disc_add_service_callback_t)(mp_obj_t self, ble_drv_service_data_t * p_service_data);
+typedef void (*ble_drv_disc_add_char_callback_t)(mp_obj_t self, ble_drv_char_data_t * p_desc_data);
+typedef void (*ble_drv_gattc_char_data_callback_t)(mp_obj_t self, uint16_t length, uint8_t * p_data);
+
+uint32_t ble_drv_stack_enable(void);
+
+void ble_drv_stack_disable(void);
+
+uint8_t ble_drv_stack_enabled(void);
+
+void ble_drv_address_get(ble_drv_addr_t * p_addr);
+
+bool ble_drv_uuid_add_vs(uint8_t * p_uuid, uint8_t * idx);
+
+bool ble_drv_service_add(ubluepy_service_obj_t * p_service_obj);
+
+bool ble_drv_characteristic_add(ubluepy_characteristic_obj_t * p_char_obj);
+
+bool ble_drv_advertise_data(ubluepy_advertise_data_t * p_adv_params);
+
+void ble_drv_advertise_stop(void);
+
+void ble_drv_gap_event_handler_set(mp_obj_t obs, ble_drv_gap_evt_callback_t evt_handler);
+
+void ble_drv_gatts_event_handler_set(mp_obj_t obj, ble_drv_gatts_evt_callback_t evt_handler);
+
+void ble_drv_gattc_event_handler_set(mp_obj_t obj, ble_drv_gattc_evt_callback_t evt_handler);
+
+void ble_drv_attr_s_read(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data);
+
+void ble_drv_attr_c_read(uint16_t conn_handle, uint16_t handle, mp_obj_t obj, ble_drv_gattc_char_data_callback_t cb);
+
+void ble_drv_attr_s_write(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data);
+
+void ble_drv_attr_s_notify(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data);
+
+void ble_drv_attr_c_write(uint16_t conn_handle, uint16_t handle, uint16_t len, uint8_t * p_data, bool w_response);
+
+void ble_drv_scan_start(void);
+
+void ble_drv_scan_stop(void);
+
+void ble_drv_adv_report_handler_set(mp_obj_t obj, ble_drv_adv_evt_callback_t evt_handler);
+
+void ble_drv_connect(uint8_t * p_addr, uint8_t addr_type);
+
+bool ble_drv_discover_services(mp_obj_t obj, uint16_t conn_handle, uint16_t start_handle, ble_drv_disc_add_service_callback_t cb);
+
+bool ble_drv_discover_characteristic(mp_obj_t obj,
+                                     uint16_t conn_handle,
+                                     uint16_t start_handle,
+                                     uint16_t end_handle,
+                                     ble_drv_disc_add_char_callback_t cb);
+
+void ble_drv_discover_descriptors(void);
+
+#endif // BLUETOOTH_SD
+
+#endif // BLUETOOTH_LE_DRIVER_H__
diff --git a/ports/nrf/drivers/bluetooth/ble_uart.c b/ports/nrf/drivers/bluetooth/ble_uart.c
new file mode 100644
index 0000000000..cc829750cd
--- /dev/null
+++ b/ports/nrf/drivers/bluetooth/ble_uart.c
@@ -0,0 +1,266 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#if BLUETOOTH_SD
+
+#include <string.h>
+#include "ble_uart.h"
+#include "ringbuffer.h"
+#include "hal/hal_time.h"
+
+#if MICROPY_PY_BLE_NUS
+
+#if BLUETOOTH_WEBBLUETOOTH_REPL
+#include "hal_time.h"
+#endif // BLUETOOTH_WEBBLUETOOTH_REPL
+
+static ubluepy_uuid_obj_t uuid_obj_service = {
+    .base.type = &ubluepy_uuid_type,
+    .type = UBLUEPY_UUID_128_BIT,
+    .value = {0x01, 0x00}
+};
+
+static ubluepy_uuid_obj_t uuid_obj_char_tx = {
+    .base.type = &ubluepy_uuid_type,
+    .type = UBLUEPY_UUID_128_BIT,
+    .value = {0x03, 0x00}
+};
+
+static ubluepy_uuid_obj_t uuid_obj_char_rx = {
+    .base.type = &ubluepy_uuid_type,
+    .type = UBLUEPY_UUID_128_BIT,
+    .value = {0x02, 0x00}
+};
+
+static ubluepy_service_obj_t ble_uart_service = {
+    .base.type = &ubluepy_service_type,
+    .p_uuid = &uuid_obj_service,
+    .type = UBLUEPY_SERVICE_PRIMARY
+};
+
+static ubluepy_characteristic_obj_t ble_uart_char_rx = {
+    .base.type = &ubluepy_characteristic_type,
+    .p_uuid = &uuid_obj_char_rx,
+    .props = UBLUEPY_PROP_WRITE | UBLUEPY_PROP_WRITE_WO_RESP,
+    .attrs = 0,
+};
+
+static ubluepy_characteristic_obj_t ble_uart_char_tx = {
+    .base.type = &ubluepy_characteristic_type,
+    .p_uuid = &uuid_obj_char_tx,
+    .props = UBLUEPY_PROP_NOTIFY,
+    .attrs = UBLUEPY_ATTR_CCCD,
+};
+
+static ubluepy_peripheral_obj_t ble_uart_peripheral = {
+    .base.type = &ubluepy_peripheral_type,
+    .conn_handle = 0xFFFF,
+};
+
+static volatile bool m_cccd_enabled;
+static volatile bool m_connected;
+
+ringBuffer_typedef(uint8_t, ringbuffer_t);
+
+static ringbuffer_t   m_rx_ring_buffer;
+static ringbuffer_t * mp_rx_ring_buffer = &m_rx_ring_buffer;
+static uint8_t        m_rx_ring_buffer_data[128];
+
+static ubluepy_advertise_data_t m_adv_data_uart_service;
+
+#if BLUETOOTH_WEBBLUETOOTH_REPL
+static ubluepy_advertise_data_t m_adv_data_eddystone_url;
+#endif // BLUETOOTH_WEBBLUETOOTH_REPL
+
+int mp_hal_stdin_rx_chr(void) {
+    while (isBufferEmpty(mp_rx_ring_buffer)) {
+        ;
+    }
+
+    uint8_t byte;
+    bufferRead(mp_rx_ring_buffer, byte);
+    return (int)byte;
+}
+
+void mp_hal_stdout_tx_strn(const char *str, size_t len) {
+    uint8_t *buf = (uint8_t *)str;
+    size_t send_len;
+
+    while (len > 0) {
+        if (len >= 20) {
+            send_len = 20; // (GATT_MTU_SIZE_DEFAULT - 3)
+        } else {
+            send_len = len;
+        }
+
+        ubluepy_characteristic_obj_t * p_char = &ble_uart_char_tx;
+
+        ble_drv_attr_s_notify(p_char->p_service->p_periph->conn_handle,
+                              p_char->handle,
+                              send_len,
+                              buf);
+
+        len -= send_len;
+        buf += send_len;
+    }
+}
+
+void mp_hal_stdout_tx_strn_cooked(const char *str, mp_uint_t len) {
+    mp_hal_stdout_tx_strn(str, len);
+}
+
+STATIC void gap_event_handler(mp_obj_t self_in, uint16_t event_id, uint16_t conn_handle, uint16_t length, uint8_t * data) {
+    ubluepy_peripheral_obj_t * self = MP_OBJ_TO_PTR(self_in);
+
+    if (event_id == 16) {                // connect event
+        self->conn_handle = conn_handle;
+        m_connected = true;
+    } else if (event_id == 17) {         // disconnect event
+        self->conn_handle = 0xFFFF;      // invalid connection handle
+        m_connected = false;
+    }
+}
+
+STATIC void gatts_event_handler(mp_obj_t self_in, uint16_t event_id, uint16_t attr_handle, uint16_t length, uint8_t * data) {
+    ubluepy_peripheral_obj_t * self = MP_OBJ_TO_PTR(self_in);
+    (void)self;
+
+    if (event_id == 80) { // gatts write
+        if (ble_uart_char_tx.cccd_handle == attr_handle) {
+            m_cccd_enabled = true;
+        } else if (ble_uart_char_rx.handle == attr_handle) {
+            for (uint16_t i = 0; i < length; i++) {
+                bufferWrite(mp_rx_ring_buffer, data[i]);
+            }
+        }
+    }
+}
+
+void ble_uart_init0(void) {
+    uint8_t base_uuid[] = {0x9E, 0xCA, 0xDC, 0x24, 0x0E, 0xE5, 0xA9, 0xE0, 0x93, 0xF3, 0xA3, 0xB5, 0x00, 0x00, 0x40, 0x6E};
+    uint8_t uuid_vs_idx;
+
+    (void)ble_drv_uuid_add_vs(base_uuid, &uuid_vs_idx);
+
+    uuid_obj_service.uuid_vs_idx = uuid_vs_idx;
+    uuid_obj_char_tx.uuid_vs_idx = uuid_vs_idx;
+    uuid_obj_char_rx.uuid_vs_idx = uuid_vs_idx;
+
+    (void)ble_drv_service_add(&ble_uart_service);
+    ble_uart_service.char_list = mp_obj_new_list(0, NULL);
+
+    // add TX characteristic
+    ble_uart_char_tx.service_handle = ble_uart_service.handle;
+    bool retval = ble_drv_characteristic_add(&ble_uart_char_tx);
+    if (retval) {
+    	ble_uart_char_tx.p_service = &ble_uart_service;
+    }
+    mp_obj_list_append(ble_uart_service.char_list, MP_OBJ_FROM_PTR(&ble_uart_char_tx));
+
+    // add RX characteristic
+    ble_uart_char_rx.service_handle = ble_uart_service.handle;
+    retval = ble_drv_characteristic_add(&ble_uart_char_rx);
+    if (retval) {
+    	ble_uart_char_rx.p_service = &ble_uart_service;
+    }
+    mp_obj_list_append(ble_uart_service.char_list, MP_OBJ_FROM_PTR(&ble_uart_char_rx));
+
+    // setup the peripheral
+    ble_uart_peripheral.service_list = mp_obj_new_list(0, NULL);
+    mp_obj_list_append(ble_uart_peripheral.service_list, MP_OBJ_FROM_PTR(&ble_uart_service));
+    ble_uart_service.p_periph = &ble_uart_peripheral;
+
+    ble_drv_gap_event_handler_set(MP_OBJ_FROM_PTR(&ble_uart_peripheral), gap_event_handler);
+    ble_drv_gatts_event_handler_set(MP_OBJ_FROM_PTR(&ble_uart_peripheral), gatts_event_handler);
+
+    ble_uart_peripheral.conn_handle = 0xFFFF;
+
+    char device_name[] = "mpus";
+
+    mp_obj_t service_list = mp_obj_new_list(0, NULL);
+    mp_obj_list_append(service_list, MP_OBJ_FROM_PTR(&ble_uart_service));
+
+    mp_obj_t * services = NULL;
+    mp_uint_t  num_services;
+    mp_obj_get_array(service_list, &num_services, &services);
+
+    m_adv_data_uart_service.p_services      = services;
+    m_adv_data_uart_service.num_of_services = num_services;
+    m_adv_data_uart_service.p_device_name   = (uint8_t *)device_name;
+    m_adv_data_uart_service.device_name_len = strlen(device_name);
+    m_adv_data_uart_service.connectable     = true;
+    m_adv_data_uart_service.p_data          = NULL;
+
+#if BLUETOOTH_WEBBLUETOOTH_REPL
+    // for now point eddystone URL to https://goo.gl/x46FES => https://glennrub.github.io/webbluetooth/micropython/repl/
+    static uint8_t eddystone_url_data[27] = {0x2, 0x1, 0x6,
+                                             0x3, 0x3, 0xaa, 0xfe,
+                                             19, 0x16, 0xaa, 0xfe, 0x10, 0xee, 0x3, 'g', 'o', 'o', '.', 'g', 'l', '/', 'x', '4', '6', 'F', 'E', 'S'};
+    // eddystone url adv data
+    m_adv_data_eddystone_url.p_data      = eddystone_url_data;
+    m_adv_data_eddystone_url.data_len    = sizeof(eddystone_url_data);
+    m_adv_data_eddystone_url.connectable = false;
+#endif
+
+    m_cccd_enabled = false;
+
+    // initialize ring buffer
+    m_rx_ring_buffer.size = sizeof(m_rx_ring_buffer_data) + 1;
+    m_rx_ring_buffer.start = 0;
+    m_rx_ring_buffer.end = 0;
+    m_rx_ring_buffer.elems = m_rx_ring_buffer_data;
+
+    m_connected = false;
+
+    ble_uart_advertise();
+}
+
+void ble_uart_advertise(void) {
+#if BLUETOOTH_WEBBLUETOOTH_REPL
+    while (!m_connected) {
+        (void)ble_drv_advertise_data(&m_adv_data_uart_service);
+        mp_hal_delay_ms(500);
+        (void)ble_drv_advertise_data(&m_adv_data_eddystone_url);
+        mp_hal_delay_ms(500);
+    }
+
+    ble_drv_advertise_stop();
+#else
+    (void)ble_drv_advertise_data(&m_adv_data_uart_service);
+#endif // BLUETOOTH_WEBBLUETOOTH_REPL
+}
+
+bool ble_uart_connected(void) {
+    return (m_connected);
+}
+
+bool ble_uart_enabled(void) {
+    return (m_cccd_enabled);
+}
+
+#endif // MICROPY_PY_BLE_NUS
+
+#endif // BLUETOOTH_SD
diff --git a/ports/nrf/drivers/bluetooth/ble_uart.h b/ports/nrf/drivers/bluetooth/ble_uart.h
new file mode 100644
index 0000000000..e67176a26f
--- /dev/null
+++ b/ports/nrf/drivers/bluetooth/ble_uart.h
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef BLUETOOTH_LE_UART_H__
+#define BLUETOOTH_LE_UART_H__
+
+#if BLUETOOTH_SD
+
+#include "modubluepy.h"
+#include "ble_drv.h"
+
+void ble_uart_init0(void);
+void ble_uart_advertise(void);
+bool ble_uart_connected(void);
+bool ble_uart_enabled(void);
+
+#endif // BLUETOOTH_SD
+
+#endif // BLUETOOTH_LE_UART_H__
diff --git a/ports/nrf/drivers/bluetooth/bluetooth_common.mk b/ports/nrf/drivers/bluetooth/bluetooth_common.mk
new file mode 100644
index 0000000000..38c604e04c
--- /dev/null
+++ b/ports/nrf/drivers/bluetooth/bluetooth_common.mk
@@ -0,0 +1,55 @@
+
+SOFTDEV_HEX_NAME ?=
+SOFTDEV_HEX_PATH ?=
+
+ifeq ($(SD), s110)
+	INC += -Idrivers/bluetooth/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)_API/include
+	CFLAGS += -DBLUETOOTH_SD_DEBUG=1
+	CFLAGS += -DBLUETOOTH_SD=110
+	SOFTDEV_HEX_NAME = $(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)_softdevice.hex
+	SOFTDEV_HEX_PATH = drivers/bluetooth/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)
+
+else ifeq ($(SD), s120)
+	$(error No BLE wrapper available yet)
+else ifeq ($(SD), s130)
+	$(error No BLE wrapper available yet)
+else ifeq ($(SD), s132)
+	INC += -Idrivers/bluetooth/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)_API/include
+	INC += -Idrivers/bluetooth/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)_API/include/$(MCU_VARIANT)
+	CFLAGS += -DBLUETOOTH_SD_DEBUG=1
+	CFLAGS += -DBLUETOOTH_SD=132
+
+ifeq ($(SOFTDEV_VERSION), 2.0.1)
+	CFLAGS += -DBLE_API_VERSION=2
+else ifeq ($(SOFTDEV_VERSION), 3.0.0)
+	CFLAGS += -DBLE_API_VERSION=3
+endif
+
+	SOFTDEV_HEX_NAME = $(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)_softdevice.hex
+	SOFTDEV_HEX_PATH = drivers/bluetooth/$(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION)
+else
+	$(error Incorrect softdevice set flag)
+endif
+
+define STACK_MISSING_ERROR
+
+
+###### ERROR: Bluetooth LE Stack not found ############
+#                                                     #
+# The build target requires a Bluetooth LE stack.     #
+# $(SD)_$(MCU_VARIANT)_$(SOFTDEV_VERSION) Bluetooth LE stack not found.      #
+#                                                     #
+# Please run the download script:                     #
+#                                                     #
+#      drivers/bluetooth/download_ble_stack.sh        #
+#                                                     #
+#######################################################
+
+endef
+
+
+SOFTDEV_HEX = $(SOFTDEV_HEX_PATH)/$(SOFTDEV_HEX_NAME)
+
+ifeq ($(shell test ! -e $(SOFTDEV_HEX) && echo -n no),no)
+    $(error $(STACK_MISSING_ERROR))
+endif
diff --git a/ports/nrf/drivers/bluetooth/download_ble_stack.sh b/ports/nrf/drivers/bluetooth/download_ble_stack.sh
new file mode 100755
index 0000000000..537742605b
--- /dev/null
+++ b/ports/nrf/drivers/bluetooth/download_ble_stack.sh
@@ -0,0 +1,74 @@
+#!/bin/bash
+
+function download_s110_nrf51_8_0_0
+{
+    echo ""
+    echo "####################################"
+    echo "### Downloading s110_nrf51_8.0.0 ###"
+    echo "####################################"
+    echo ""
+
+    mkdir -p $1/s110_nrf51_8.0.0
+    cd $1/s110_nrf51_8.0.0
+    wget https://www.nordicsemi.com/eng/nordic/download_resource/45846/3/78153065/80234
+    mv 80234 temp.zip
+    unzip -u temp.zip
+    rm temp.zip
+    cd -
+}
+
+function download_s132_nrf52_2_0_1
+{
+    echo ""
+    echo "####################################"
+    echo "### Downloading s132_nrf52_2.0.1 ###"
+    echo "####################################"
+    echo ""
+
+    mkdir -p $1/s132_nrf52_2.0.1
+    cd $1/s132_nrf52_2.0.1
+    wget https://www.nordicsemi.com/eng/nordic/download_resource/51479/6/84640562/95151
+    mv 95151 temp.zip
+    unzip -u temp.zip
+    rm temp.zip
+    cd -
+}
+
+function download_s132_nrf52_3_0_0
+{
+    echo ""
+    echo "####################################"
+    echo "### Downloading s132_nrf52_3.0.0 ###"
+    echo "####################################"
+    echo ""
+
+    mkdir -p $1/s132_nrf52_3.0.0
+    cd $1/s132_nrf52_3.0.0
+
+    wget https://www.nordicsemi.com/eng/nordic/download_resource/56261/6/26298825/108144
+    mv 108144 temp.zip
+    unzip -u temp.zip
+    rm temp.zip
+    cd -
+}
+
+
+SCRIPT_DIR="$(cd -P "$(dirname "${BASH_SOURCE[0]}")" && pwd)"
+
+if [ $# -eq 0 ]; then 
+    echo "No Bluetooth LE stack defined, downloading all."
+    download_s110_nrf51_8_0_0 ${SCRIPT_DIR}
+    download_s132_nrf52_2_0_1 ${SCRIPT_DIR}
+    download_s132_nrf52_3_0_0 ${SCRIPT_DIR}
+else 
+    case $1 in
+        "s110_nrf51" )
+            download_s110_nrf51_8_0_0 ${SCRIPT_DIR} ;;
+        "s132_nrf52_2_0_1" )
+            download_s132_nrf52_2_0_1 ${SCRIPT_DIR} ;;
+        "s132_nrf52_3_0_0" )
+            download_s132_nrf52_3_0_0 ${SCRIPT_DIR} ;;
+    esac
+fi
+
+exit 0
diff --git a/ports/nrf/drivers/bluetooth/ringbuffer.h b/ports/nrf/drivers/bluetooth/ringbuffer.h
new file mode 100644
index 0000000000..3438b5c9b5
--- /dev/null
+++ b/ports/nrf/drivers/bluetooth/ringbuffer.h
@@ -0,0 +1,99 @@
+/* The MIT License (MIT)
+ *
+ * Copyright (c) 2013 Philip Thrasher
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ * Philip Thrasher's Crazy Awesome Ring Buffer Macros!
+ *
+ * Below you will find some naughty macros for easy owning and manipulating
+ * generic ring buffers. Yes, they are slightly evil in readability, but they
+ * are really fast, and they work great.
+ *
+ * Example usage:
+ *
+ * #include <stdio.h>
+ *
+ * // So we can use this in any method, this gives us a typedef
+ * // named 'intBuffer'.
+ * ringBuffer_typedef(int, intBuffer);
+ *
+ * int main() {
+ *   // Declare vars.
+ *   intBuffer myBuffer;
+ *
+ *   bufferInit(myBuffer,1024,int);
+ *
+ *   // We must have the pointer. All of the macros deal with the pointer.
+ *   // (except for init.)
+ *   intBuffer* myBuffer_ptr;
+ *   myBuffer_ptr = &myBuffer;
+ *
+ *   // Write two values.
+ *   bufferWrite(myBuffer_ptr,37);
+ *   bufferWrite(myBuffer_ptr,72);
+ *
+ *   // Read a value into a local variable.
+ *   int first;
+ *   bufferRead(myBuffer_ptr,first);
+ *   assert(first == 37); // true
+ *
+ *   int second;
+ *   bufferRead(myBuffer_ptr,second);
+ *   assert(second == 72); // true
+ *
+ *   return 0;
+ * }
+ *
+ */
+
+#ifndef _ringbuffer_h
+#define _ringbuffer_h
+
+#define ringBuffer_typedef(T, NAME) \
+  typedef struct { \
+    int size; \
+    volatile int start; \
+    volatile int end; \
+    T* elems; \
+  } NAME
+
+#define bufferInit(BUF, S, T) \
+  BUF.size = S+1; \
+  BUF.start = 0; \
+  BUF.end = 0; \
+  BUF.elems = (T*)calloc(BUF.size, sizeof(T))
+
+
+#define bufferDestroy(BUF) free(BUF->elems)
+#define nextStartIndex(BUF) ((BUF->start + 1) % BUF->size)
+#define nextEndIndex(BUF) ((BUF->end + 1) % BUF->size)
+#define isBufferEmpty(BUF) (BUF->end == BUF->start)
+#define isBufferFull(BUF) (nextEndIndex(BUF) == BUF->start)
+
+#define bufferWrite(BUF, ELEM) \
+  BUF->elems[BUF->end] = ELEM; \
+  BUF->end = (BUF->end + 1) % BUF->size; \
+  if (isBufferEmpty(BUF)) { \
+    BUF->start = nextStartIndex(BUF); \
+  }
+
+#define bufferRead(BUF, ELEM) \
+    ELEM = BUF->elems[BUF->start]; \
+    BUF->start = nextStartIndex(BUF);
+
+#endif
diff --git a/ports/nrf/drivers/softpwm.c b/ports/nrf/drivers/softpwm.c
new file mode 100644
index 0000000000..22564f7d0a
--- /dev/null
+++ b/ports/nrf/drivers/softpwm.c
@@ -0,0 +1,257 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2016 Mark Shannon
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "py/mphal.h"
+
+#if MICROPY_PY_MACHINE_SOFT_PWM
+
+#include "stddef.h"
+#include "py/runtime.h"
+#include "py/gc.h"
+#include "hal_timer.h"
+#include "hal_gpio.h"
+#include "pin.h"
+
+#include "ticker.h"
+
+#define CYCLES_PER_MICROSECONDS 16
+
+#define MICROSECONDS_PER_TICK 16
+#define CYCLES_PER_TICK (CYCLES_PER_MICROSECONDS*MICROSECONDS_PER_TICK)
+// This must be an integer multiple of MICROSECONDS_PER_TICK
+#define MICROSECONDS_PER_MACRO_TICK 6000
+#define MILLISECONDS_PER_MACRO_TICK 6
+
+#define PWM_TICKER_INDEX 2
+
+// Default period of 20ms
+#define DEFAULT_PERIOD ((20*1000)/MICROSECONDS_PER_TICK)
+
+typedef struct _pwm_event {
+    uint16_t time;
+    uint8_t pin;
+    uint8_t turn_on;
+} pwm_event;
+
+typedef struct _pwm_events {
+    uint8_t count;
+    uint16_t period;
+    uint32_t all_pins;
+    pwm_event events[1];
+} pwm_events;
+
+static const pwm_events OFF_EVENTS = {
+    .count = 1,
+    .period = DEFAULT_PERIOD,
+    .all_pins = 0,
+    .events = {
+        {
+            .time = 1024,
+            .pin = 31,
+            .turn_on = 0
+        }
+    }
+};
+
+#define active_events MP_STATE_PORT(pwm_active_events)
+#define pending_events MP_STATE_PORT(pwm_pending_events)
+
+void softpwm_init(void) {
+    active_events = &OFF_EVENTS;
+    pending_events = NULL;
+}
+
+static uint8_t next_event = 0;
+
+static inline int32_t pwm_get_period_ticks(void) {
+    const pwm_events *tmp = pending_events;
+    if (tmp == NULL)
+        tmp = active_events;
+    return tmp->period;
+}
+
+#if 0
+void pwm_dump_events(const pwm_events *events) {
+    printf("Count %d, period %d, all pins %d\r\n", events->count, events->period, events->all_pins);
+    for (uint32_t i = 0; i < events->count; i++) {
+        const pwm_event *event = &events->events[i];
+        printf("Event. pin: %d, duty cycle: %d, turn_on: %d\r\n",
+               event->pin, event->time, event->turn_on);
+    }
+}
+
+void pwm_dump_state(void) {
+    while(pending_events);
+    pwm_dump_events(active_events);
+}
+#endif
+
+static const pwm_events *swap_pending(const pwm_events *in) {
+    __disable_irq();
+    const pwm_events *result = pending_events;
+    pending_events = in;
+    __enable_irq();
+    return result;
+}
+
+static pwm_events *copy_events(const pwm_events *orig, uint32_t count) {
+    pwm_events *events = m_malloc(sizeof(pwm_events) + (count-1)*sizeof(pwm_event));
+    events->count = count;
+    uint32_t copy = count > orig->count ? orig->count : count;
+    for (uint32_t i = 0; i < copy; i++) {
+        events->events[i] = orig->events[i];
+    }
+    return events;
+}
+
+static int find_pin_in_events(const pwm_events *events, uint32_t pin) {
+    for (int i = 0; i < events->count; i++) {
+        if (events->events[i].pin == pin)
+            return i;
+    }
+    return -1;
+}
+
+static void sort_events(pwm_events *events) {
+    // Insertion sort
+    for (int32_t i = 1; i < events->count; i++) {
+        pwm_event x = events->events[i];
+        int32_t j;
+        for (j = i - 1; j >= 0 && events->events[j].time > x.time; j--) {
+            events->events[j+1] = events->events[j];
+        }
+        events->events[j+1] = x;
+    }
+}
+
+int32_t pwm_callback(void) {
+    int32_t tdiff;
+    const pwm_events *events = active_events;
+    const pwm_event *event = &events->events[next_event];
+    int32_t tnow = (event->time*events->period)>>10;
+    do {
+        if (event->turn_on) {
+            hal_gpio_pin_set(0, event->pin);
+            next_event++;
+        } else {
+            hal_gpio_out_clear(0, events->all_pins);
+            next_event = 0;
+            tnow = 0;
+            if (pending_events) {
+                events = pending_events;
+                active_events = events;
+                pending_events = NULL;
+            }
+        }
+        event = &events->events[next_event];
+        tdiff = ((event->time*events->period)>>10) - tnow;
+    } while (tdiff == 0);
+    return tdiff;
+}
+
+void pwm_start(void) {
+    set_ticker_callback(PWM_TICKER_INDEX, pwm_callback, 120);
+}
+
+void pwm_stop(void) {
+    clear_ticker_callback(PWM_TICKER_INDEX);
+}
+
+static void pwm_set_period_ticks(int32_t ticks) {
+    const pwm_events *old_events = swap_pending(NULL);
+    if (old_events == NULL) {
+        old_events = active_events;
+    }
+    pwm_events *events = copy_events(old_events, old_events->count);
+    events->all_pins = old_events->all_pins;
+    events->period = ticks;
+    pending_events = events;
+}
+
+int pwm_set_period_us(int32_t us) {
+    if ((us < 256) ||
+        (us > 1000000)) {
+        return -1;
+    }
+    pwm_set_period_ticks(us/MICROSECONDS_PER_TICK);
+    return 0;
+}
+
+int32_t pwm_get_period_us(void) {
+    return pwm_get_period_ticks()*MICROSECONDS_PER_TICK;
+}
+
+void pwm_set_duty_cycle(int32_t pin, uint32_t value) {
+    if (value >= (1<<10)) {
+        value = (1<<10)-1;
+    }
+    uint32_t turn_on_time = 1024-value;
+    const pwm_events *old_events = swap_pending(NULL);
+    if (old_events == NULL) {
+        old_events = active_events;
+    }
+    if (((1<<pin)&old_events->all_pins) == 0) {
+        hal_gpio_cfg_pin(0, pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED);
+    }
+    int ev = find_pin_in_events(old_events, pin);
+    pwm_events *events;
+    if (ev < 0 && value == 0) {
+        return;
+    } else if (ev < 0) {
+        events = copy_events(old_events, old_events->count+1);
+        events->all_pins = old_events->all_pins | (1<<pin);
+        events->events[old_events->count].time = turn_on_time;
+        events->events[old_events->count].pin = pin;
+        events->events[old_events->count].turn_on = 1;
+    } else if (value == 0) {
+        events = copy_events(old_events, old_events->count-1);
+        events->all_pins = old_events->all_pins & ~(1<<pin);
+        if (ev < old_events->count-1) {
+            events->events[ev] = old_events->events[old_events->count-1];
+        }
+    } else {
+        events = copy_events(old_events, old_events->count);
+        events->all_pins = old_events->all_pins;
+        events->events[ev].time = turn_on_time;
+    }
+    events->period = old_events->period;
+    sort_events(events);
+    pending_events = events;
+    return;
+}
+
+void pwm_release(int32_t pin) {
+    pwm_set_duty_cycle(pin, 0);
+    const pwm_events *ev = active_events;
+    int i = find_pin_in_events(ev, pin);
+    if (i < 0)
+        return;
+    // If i >= 0 it means that `ev` is in RAM, so it safe to discard the const qualifier
+    ((pwm_events *)ev)->events[i].pin = 31;
+    hal_gpio_pin_clear(0, pin);
+}
+
+#endif // MICROPY_PY_MACHINE_SOFT_PWM
diff --git a/ports/nrf/drivers/softpwm.h b/ports/nrf/drivers/softpwm.h
new file mode 100644
index 0000000000..a73c15cd85
--- /dev/null
+++ b/ports/nrf/drivers/softpwm.h
@@ -0,0 +1,13 @@
+#ifndef __MICROPY_INCLUDED_LIB_PWM_H__
+#define __MICROPY_INCLUDED_LIB_PWM_H__
+
+void softpwm_init(void);
+void pwm_start(void);
+void pwm_stop(void);
+
+int pwm_set_period_us(int32_t us);
+int32_t pwm_get_period_us(void);
+void pwm_set_duty_cycle(int32_t pin, int32_t value);
+void pwm_release(int32_t pin);
+
+#endif // __MICROPY_INCLUDED_LIB_PWM_H__
diff --git a/ports/nrf/drivers/ticker.c b/ports/nrf/drivers/ticker.c
new file mode 100644
index 0000000000..aa730d643d
--- /dev/null
+++ b/ports/nrf/drivers/ticker.c
@@ -0,0 +1,162 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2016 Mark Shannon
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "py/mphal.h"
+
+#if MICROPY_PY_MACHINE_SOFT_PWM
+
+#include "ticker.h"
+#include "hal_irq.h"
+
+#define FastTicker NRF_TIMER1
+#define FastTicker_IRQn TIMER1_IRQn
+#define FastTicker_IRQHandler TIMER1_IRQHandler
+
+#define SlowTicker_IRQn SWI0_IRQn
+#define SlowTicker_IRQHandler SWI0_IRQHandler
+
+// Ticker callback function called every MACRO_TICK
+static volatile callback_ptr slow_ticker;
+
+void ticker_init(callback_ptr slow_ticker_callback) {
+    slow_ticker = slow_ticker_callback;
+
+    NRF_TIMER_Type *ticker = FastTicker;
+#ifdef NRF51
+    ticker->POWER = 1;
+#endif
+    __NOP();
+    ticker_stop();
+    ticker->TASKS_CLEAR = 1;
+    ticker->CC[3] = MICROSECONDS_PER_MACRO_TICK;
+    ticker->MODE = TIMER_MODE_MODE_Timer;
+    ticker->BITMODE = TIMER_BITMODE_BITMODE_24Bit << TIMER_BITMODE_BITMODE_Pos;
+    ticker->PRESCALER = 4; // 1 tick == 1 microsecond
+    ticker->INTENSET = TIMER_INTENSET_COMPARE3_Msk;
+    ticker->SHORTS = 0;
+
+#ifdef NRF51
+    hal_irq_priority(FastTicker_IRQn, 1);
+#else
+    hal_irq_priority(FastTicker_IRQn, 2);
+#endif
+
+    hal_irq_priority(SlowTicker_IRQn, 3);
+    hal_irq_priority(SlowTicker_IRQn, 3);
+
+    hal_irq_enable(SlowTicker_IRQn);
+}
+
+/* Start and stop timer 1 including workarounds for Anomaly 73 for Timer
+* http://www.nordicsemi.com/eng/content/download/29490/494569/file/nRF51822-PAN%20v3.0.pdf
+*/
+void ticker_start(void) {
+    hal_irq_enable(FastTicker_IRQn);
+#ifdef NRF51
+    *(uint32_t *)0x40009C0C = 1; // for Timer 1
+#endif
+    FastTicker->TASKS_START = 1;
+}
+
+void ticker_stop(void) {
+    hal_irq_disable(FastTicker_IRQn);
+    FastTicker->TASKS_STOP = 1;
+#ifdef NRF51
+    *(uint32_t *)0x40009C0C = 0; // for Timer 1
+#endif
+}
+
+int32_t noop(void) {
+    return -1;
+}
+
+volatile uint32_t ticks;
+
+static ticker_callback_ptr callbacks[3] = { noop, noop, noop };
+
+void FastTicker_IRQHandler(void) {
+    NRF_TIMER_Type *ticker = FastTicker;
+    ticker_callback_ptr *call = callbacks;
+    if (ticker->EVENTS_COMPARE[0]) {
+        ticker->EVENTS_COMPARE[0] = 0;
+        ticker->CC[0] += call[0]()*MICROSECONDS_PER_TICK;
+    }
+    if (ticker->EVENTS_COMPARE[1]) {
+        ticker->EVENTS_COMPARE[1] = 0;
+        ticker->CC[1] += call[1]()*MICROSECONDS_PER_TICK;
+    }
+    if (ticker->EVENTS_COMPARE[2]) {
+        ticker->EVENTS_COMPARE[2] = 0;
+        ticker->CC[2] += call[2]()*MICROSECONDS_PER_TICK;
+    }
+    if (ticker->EVENTS_COMPARE[3]) {
+        ticker->EVENTS_COMPARE[3] = 0;
+        ticker->CC[3] += MICROSECONDS_PER_MACRO_TICK;
+        ticks += MILLISECONDS_PER_MACRO_TICK;
+        hal_irq_pending(SlowTicker_IRQn);
+    }
+}
+
+
+static const uint32_t masks[3] = {
+    TIMER_INTENCLR_COMPARE0_Msk,
+    TIMER_INTENCLR_COMPARE1_Msk,
+    TIMER_INTENCLR_COMPARE2_Msk,
+};
+
+int set_ticker_callback(uint32_t index, ticker_callback_ptr func, int32_t initial_delay_us) {
+    if (index > 3)
+        return -1;
+    NRF_TIMER_Type *ticker = FastTicker;
+    callbacks[index] = noop;
+    ticker->INTENCLR = masks[index];
+    ticker->TASKS_CAPTURE[index] = 1;
+    uint32_t t = FastTicker->CC[index];
+    // Need to make sure that set tick is aligned to lastest tick
+    // Use CC[3] as a reference, as that is always up-to-date.
+    int32_t cc3 = FastTicker->CC[3];
+    int32_t delta = t+initial_delay_us-cc3;
+    delta = (delta/MICROSECONDS_PER_TICK+1)*MICROSECONDS_PER_TICK;
+    callbacks[index] = func;
+    ticker->INTENSET = masks[index];
+    FastTicker->CC[index] = cc3 + delta;
+    return 0;
+}
+
+int clear_ticker_callback(uint32_t index) {
+    if (index > 3)
+        return -1;
+    FastTicker->INTENCLR = masks[index];
+    callbacks[index] = noop;
+    return 0;
+}
+
+void SlowTicker_IRQHandler(void)
+{
+    slow_ticker();
+}
+
+#endif // MICROPY_PY_MACHINE_SOFT_PWM
diff --git a/ports/nrf/drivers/ticker.h b/ports/nrf/drivers/ticker.h
new file mode 100644
index 0000000000..6ac87cd503
--- /dev/null
+++ b/ports/nrf/drivers/ticker.h
@@ -0,0 +1,30 @@
+#ifndef __MICROPY_INCLUDED_LIB_TICKER_H__
+#define __MICROPY_INCLUDED_LIB_TICKER_H__
+
+/*************************************
+ * 62.5kHz (16µs cycle time) ticker.
+ ************************************/
+
+#include "nrf.h"
+
+typedef void (*callback_ptr)(void);
+typedef int32_t (*ticker_callback_ptr)(void);
+
+void ticker_init(callback_ptr slow_ticker_callback);
+void ticker_start(void);
+void ticker_stop(void);
+
+int clear_ticker_callback(uint32_t index);
+int set_ticker_callback(uint32_t index, ticker_callback_ptr func, int32_t initial_delay_us);
+
+int set_low_priority_callback(callback_ptr callback, int id);
+
+#define CYCLES_PER_MICROSECONDS 16
+
+#define MICROSECONDS_PER_TICK 16
+#define CYCLES_PER_TICK (CYCLES_PER_MICROSECONDS*MICROSECONDS_PER_TICK)
+// This must be an integer multiple of MICROSECONDS_PER_TICK
+#define MICROSECONDS_PER_MACRO_TICK 6000
+#define MILLISECONDS_PER_MACRO_TICK 6
+
+#endif // __MICROPY_INCLUDED_LIB_TICKER_H__
\ No newline at end of file
diff --git a/ports/nrf/examples/mountsd.py b/ports/nrf/examples/mountsd.py
new file mode 100644
index 0000000000..1577221a62
--- /dev/null
+++ b/ports/nrf/examples/mountsd.py
@@ -0,0 +1,35 @@
+"""
+
+Example for pca10040 / nrf52832 to show how mount
+and list a sdcard connected over SPI.
+
+
+Direct wireing on SD card (SPI):
+   ______________________________
+  |                              \
+  |             9.    | NC    |   \
+  |             1.      | ~CS   | |
+  |             2.      | MOSI  | |
+  |             3.      | GND   | |
+  |             4.      | VCC3.3| |
+  |             5.      | SCK   | |
+  |             6.      | GND   | |
+  |             7.      | MISO  | |
+  |             8.      | NC    | |
+  |                               |
+  ---------------------------------
+"""
+
+import os
+from machine import SPI, Pin
+from sdcard import SDCard
+
+def mnt():
+    cs = Pin("A22", mode=Pin.OUT)
+    sd = SDCard(SPI(0), cs)
+    os.mount(sd, '/')
+
+def list():
+    files = os.listdir()
+    print(files)
+
diff --git a/ports/nrf/examples/musictest.py b/ports/nrf/examples/musictest.py
new file mode 100644
index 0000000000..d958543ec3
--- /dev/null
+++ b/ports/nrf/examples/musictest.py
@@ -0,0 +1,13 @@
+# 
+# Example usage where "A3" is the Buzzer pin.
+#
+#  from musictest import play
+#  play("A3")
+#
+
+from machine import Pin
+import music
+
+def play(pin_str):
+    p = Pin(pin_str, mode=Pin.OUT)
+    music.play(music.PRELUDE, pin=p)
diff --git a/ports/nrf/examples/nrf52_pwm.py b/ports/nrf/examples/nrf52_pwm.py
new file mode 100644
index 0000000000..2ea1e7be7e
--- /dev/null
+++ b/ports/nrf/examples/nrf52_pwm.py
@@ -0,0 +1,15 @@
+import time
+from machine import PWM, Pin
+
+def pulse():
+    for i in range(0, 101):
+        p = PWM(0, Pin("A17", mode=Pin.OUT), freq=PWM.FREQ_16MHZ, duty=i, period=16000)
+        p.init()
+        time.sleep_ms(10)
+        p.deinit()
+
+    for i in range(0, 101):
+        p = PWM(0, Pin("A17", mode=Pin.OUT), freq=PWM.FREQ_16MHZ, duty=100-i, period=16000)
+        p.init()
+        time.sleep_ms(10)
+        p.deinit()
diff --git a/ports/nrf/examples/nrf52_servo.py b/ports/nrf/examples/nrf52_servo.py
new file mode 100644
index 0000000000..e9c594af3e
--- /dev/null
+++ b/ports/nrf/examples/nrf52_servo.py
@@ -0,0 +1,50 @@
+# This file is part of the MicroPython project, http://micropython.org/
+#
+# The MIT License (MIT)
+#
+# Copyright (c) 2017 Glenn Ruben Bakke
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+# THE SOFTWARE
+
+import time
+from machine import PWM, Pin
+
+class Servo():
+    def __init__(self, pin_name=""):
+        if pin_name:
+            self.pin = Pin(pin_name, mode=Pin.OUT, pull=Pin.PULL_DOWN)
+        else:
+            self.pin = Pin("A22", mode=Pin.OUT, pull=Pin.PULL_DOWN)
+    def left(self):
+        p = PWM(0, self.pin, freq=PWM.FREQ_125KHZ, pulse_width=105, period=2500, mode=PWM.MODE_HIGH_LOW)
+        p.init()
+        time.sleep_ms(200)
+        p.deinit()
+        
+    def center(self):
+        p = PWM(0, self.pin, freq=PWM.FREQ_125KHZ, pulse_width=188, period=2500, mode=PWM.MODE_HIGH_LOW)
+        p.init()
+        time.sleep_ms(200)
+        p.deinit()
+        
+    def right(self):
+        p = PWM(0, self.pin, freq=PWM.FREQ_125KHZ, pulse_width=275, period=2500, mode=PWM.MODE_HIGH_LOW)
+        p.init()
+        time.sleep_ms(200)
+        p.deinit()
diff --git a/ports/nrf/examples/powerup.py b/ports/nrf/examples/powerup.py
new file mode 100644
index 0000000000..fd7dd83439
--- /dev/null
+++ b/ports/nrf/examples/powerup.py
@@ -0,0 +1,213 @@
+# This file is part of the MicroPython project, http://micropython.org/
+#
+# The MIT License (MIT)
+#
+# Copyright (c) 2017 Glenn Ruben Bakke
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+# THE SOFTWARE
+
+# MicroPython controller for PowerUp 3.0 paper airplane
+# https://www.poweruptoys.com/products/powerup-v3
+#
+# Examples is written for nrf52832, pca10040 using s132 bluetooth stack.
+#
+# Joystick shield pin mapping:
+#  - analog stick x-direction - ADC0 - P0.02/"A02"
+#  - buttons P0.13 - P0.16 / "A13", "A14", "A15", "A16"
+#
+# Example usage:
+#
+#     from powerup import PowerUp3
+#     p = PowerUp3()
+
+import time
+from machine import ADC
+from machine import Pin
+from ubluepy import Peripheral, Scanner, constants
+
+def bytes_to_str(bytes):
+    string = ""
+    for b in bytes:
+        string += chr(b)
+    return string
+
+def get_device_names(scan_entries):
+    dev_names = []
+    for e in scan_entries:
+        scan = e.getScanData()
+        if scan:
+            for s in scan:
+               if s[0] == constants.ad_types.AD_TYPE_COMPLETE_LOCAL_NAME:
+                   dev_names.append((e, bytes_to_str(s[2])))
+    return dev_names
+
+def find_device_by_name(name):
+    s = Scanner()
+    scan_res = s.scan(500)
+
+    device_names = get_device_names(scan_res)
+    for dev in device_names:
+        if name == dev[1]:
+            return dev[0]
+
+class PowerUp3:
+    def __init__(self):
+        self.x_adc = ADC(1)
+
+        self.btn_speed_up = Pin("A13", mode=Pin.IN, pull=Pin.PULL_UP)
+        self.btn_speed_down = Pin("A15", mode=Pin.IN, pull=Pin.PULL_UP)
+        self.btn_speed_full = Pin("A14", mode=Pin.IN, pull=Pin.PULL_UP)
+        self.btn_speed_off = Pin("A16", mode=Pin.IN, pull=Pin.PULL_UP)
+
+        self.x_mid = 0
+        
+        self.calibrate()
+        self.connect()
+        self.loop()
+        
+    def read_stick_x(self):
+        return self.x_adc.value()
+        
+    def button_speed_up(self):
+        return not bool(self.btn_speed_up.value())
+
+    def button_speed_down(self):
+        return not bool(self.btn_speed_down.value())
+
+    def button_speed_full(self):
+        return not bool(self.btn_speed_full.value())
+
+    def button_speed_off(self):
+        return not bool(self.btn_speed_off.value())
+
+    def calibrate(self):
+        self.x_mid = self.read_stick_x()
+
+    def __str__(self):
+        return "calibration x: %i, y: %i" % (self.x_mid)
+
+    def map_chars(self):
+        s = self.p.getServices()
+
+        service_batt = s[3]
+        service_control = s[4]
+
+        self.char_batt_lvl = service_batt.getCharacteristics()[0]
+        self.char_control_speed = service_control.getCharacteristics()[0]
+        self.char_control_angle = service_control.getCharacteristics()[2]
+
+    def battery_level(self):
+        return int(self.char_batt_lvl.read()[0])
+
+    def speed(self, new_speed=None):
+        if new_speed == None:
+            return int(self.char_control_speed.read()[0])
+        else:
+            self.char_control_speed.write(bytearray([new_speed]))
+
+    def angle(self, new_angle=None):
+        if new_angle == None:
+            return int(self.char_control_angle.read()[0])
+        else:
+            self.char_control_angle.write(bytearray([new_angle]))
+
+    def connect(self):
+        dev = None
+
+        # connect to the airplane
+        while not dev:
+            dev = find_device_by_name("TailorToys PowerUp")
+            if dev:
+                self.p = Peripheral()
+                self.p.connect(dev.addr())
+
+        # locate interesting characteristics
+        self.map_chars()
+
+    def rudder_center(self):
+        if self.old_angle != 0:
+            self.old_angle = 0
+            self.angle(0)
+
+    def rudder_left(self, angle):
+        steps = (angle // self.interval_size_left)
+        new_angle = 60 - steps
+
+        if self.old_angle != new_angle:
+            self.angle(new_angle)
+            self.old_angle = new_angle
+
+    def rudder_right(self, angle):
+        steps = (angle // self.interval_size_right)
+        new_angle = -steps
+
+        if self.old_angle != new_angle:
+            self.angle(new_angle)
+            self.old_angle = new_angle
+
+    def throttle(self, speed):
+        if (speed > 200):
+            speed = 200
+        elif (speed < 0):
+            speed = 0
+
+        if self.old_speed != speed:
+            self.speed(speed)
+            self.old_speed = speed
+
+    def loop(self):
+        adc_threshold = 10
+        right_threshold = self.x_mid + adc_threshold
+        left_threshold = self.x_mid - adc_threshold
+
+        self.interval_size_left = self.x_mid // 60
+        self.interval_size_right = (255 - self.x_mid) // 60
+
+        self.old_angle = 0
+        self.old_speed = 0
+
+        while True:
+
+            time.sleep_ms(100)
+
+            # read out new angle
+            new_angle = self.read_stick_x()
+            if (new_angle < 256):
+                if (new_angle > right_threshold):
+                    self.rudder_right(new_angle - self.x_mid)
+                elif (new_angle < left_threshold):
+                    self.rudder_left(new_angle)
+                else:
+                    self.rudder_center()
+
+            # read out new speed
+            new_speed = self.old_speed
+
+            if self.button_speed_up():
+                new_speed += 25
+            elif self.button_speed_down():
+                new_speed -= 25
+            elif self.button_speed_full():
+                new_speed = 200
+            elif self.button_speed_off():
+                new_speed = 0
+            else:
+                pass
+
+            self.throttle(new_speed)
diff --git a/ports/nrf/examples/seeed_tft.py b/ports/nrf/examples/seeed_tft.py
new file mode 100644
index 0000000000..f751bbb0f2
--- /dev/null
+++ b/ports/nrf/examples/seeed_tft.py
@@ -0,0 +1,210 @@
+# This file is part of the MicroPython project, http://micropython.org/
+#
+# The MIT License (MIT)
+#
+# Copyright (c) 2016 Glenn Ruben Bakke
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+# THE SOFTWARE.
+
+"""
+MicroPython Seeedstudio TFT Shield V2 driver, SPI interfaces, Analog GPIO
+Contains SD-card reader, LCD and Touch sensor
+
+The pca10040 pin layout is used as reference.
+
+Example usage of LCD:
+
+    from seeedstudio_tft_shield_v2 import ILI9341
+
+    lcd = ILI9341(240, 320)
+    lcd.text("Hello World!, 32, 32)
+    lcd.show()
+
+Example usage of SD card reader:
+
+    import os
+    from seeedstudio_tft_shield_v2 import mount_tf
+
+    tf = mount_tf()
+    os.listdir()
+"""
+import os
+import time
+import framebuf
+
+from machine import SPI, Pin
+from sdcard import SDCard
+
+def mount_tf(self, mount_point="/"):
+    sd = SDCard(SPI(0), Pin("A15", mode=Pin.OUT))
+    os.mount(sd, mount_point)
+
+class ILI9341:
+    def __init__(self, width, height):
+        self.width = width
+        self.height = height
+        self.pages = self.height // 8
+        self.buffer = bytearray(self.pages * self.width)
+        self.framebuf = framebuf.FrameBuffer(self.buffer, self.width, self.height, framebuf.MONO_VLSB)
+
+        self.spi = SPI(0)
+        # chip select
+        self.cs = Pin("A16", mode=Pin.OUT, pull=Pin.PULL_UP)
+        # command
+        self.dc = Pin("A17", mode=Pin.OUT, pull=Pin.PULL_UP)
+        
+        # initialize all pins high
+        self.cs.high()
+        self.dc.high()
+
+        self.spi.init(baudrate=8000000, phase=0, polarity=0)
+
+        self.init_display()
+        
+
+    def init_display(self):
+        time.sleep_ms(500)
+        
+        self.write_cmd(0x01)
+        
+        time.sleep_ms(200)
+    
+        self.write_cmd(0xCF)
+        self.write_data(bytearray([0x00, 0x8B, 0x30]))
+    
+        self.write_cmd(0xED)
+        self.write_data(bytearray([0x67, 0x03, 0x12, 0x81]))
+
+        self.write_cmd(0xE8)
+        self.write_data(bytearray([0x85, 0x10, 0x7A]))
+    
+        self.write_cmd(0xCB)
+        self.write_data(bytearray([0x39, 0x2C, 0x00, 0x34, 0x02]))
+    
+        self.write_cmd(0xF7)
+        self.write_data(bytearray([0x20]))
+
+        self.write_cmd(0xEA)
+        self.write_data(bytearray([0x00, 0x00]))
+
+        # Power control
+        self.write_cmd(0xC0)
+        # VRH[5:0]
+        self.write_data(bytearray([0x1B]))
+        
+        # Power control
+        self.write_cmd(0xC1)
+        # SAP[2:0];BT[3:0]
+        self.write_data(bytearray([0x10]))
+        
+        # VCM control
+        self.write_cmd(0xC5)
+        self.write_data(bytearray([0x3F, 0x3C]))
+    
+        # VCM control2
+        self.write_cmd(0xC7)
+        self.write_data(bytearray([0xB7]))
+    
+        # Memory Access Control
+        self.write_cmd(0x36)
+        self.write_data(bytearray([0x08]))
+    
+        self.write_cmd(0x3A)
+        self.write_data(bytearray([0x55]))
+    
+        self.write_cmd(0xB1)
+        self.write_data(bytearray([0x00, 0x1B]))
+        
+        # Display Function Control
+        self.write_cmd(0xB6)
+        self.write_data(bytearray([0x0A, 0xA2]))
+    
+        # 3Gamma Function Disable
+        self.write_cmd(0xF2)
+        self.write_data(bytearray([0x00]))
+        
+        # Gamma curve selected
+        self.write_cmd(0x26)
+        self.write_data(bytearray([0x01]))
+    
+        # Set Gamma
+        self.write_cmd(0xE0)
+        self.write_data(bytearray([0x0F, 0x2A, 0x28, 0x08, 0x0E, 0x08, 0x54, 0XA9, 0x43, 0x0A, 0x0F, 0x00, 0x00, 0x00, 0x00]))
+    
+        # Set Gamma
+        self.write_cmd(0XE1)
+        self.write_data(bytearray([0x00, 0x15, 0x17, 0x07, 0x11, 0x06, 0x2B, 0x56, 0x3C, 0x05, 0x10, 0x0F, 0x3F, 0x3F, 0x0F]))
+        
+        # Exit Sleep
+        self.write_cmd(0x11)
+        time.sleep_ms(120)
+        
+        # Display on
+        self.write_cmd(0x29)
+        time.sleep_ms(500)
+        self.fill(0)
+
+    def show(self):
+        # set col
+        self.write_cmd(0x2A)
+        self.write_data(bytearray([0x00, 0x00]))
+        self.write_data(bytearray([0x00, 0xef]))
+        
+        # set page 
+        self.write_cmd(0x2B)
+        self.write_data(bytearray([0x00, 0x00]))
+        self.write_data(bytearray([0x01, 0x3f]))
+
+        self.write_cmd(0x2c);
+
+        num_of_pixels = self.height * self.width
+
+        for row in range(0, self.pages):
+            for pixel_pos in range(0, 8):
+                for col in range(0, self.width):
+                    compressed_pixel = self.buffer[row * 240 + col]
+                    if ((compressed_pixel >> pixel_pos) & 0x1) == 0:
+                        self.write_data(bytearray([0x00, 0x00]))
+                    else:
+                        self.write_data(bytearray([0xFF, 0xFF]))
+
+    def fill(self, col):
+        self.framebuf.fill(col)
+
+    def pixel(self, x, y, col):
+        self.framebuf.pixel(x, y, col)
+
+    def scroll(self, dx, dy):
+        self.framebuf.scroll(dx, dy)
+
+    def text(self, string, x, y, col=1):
+        self.framebuf.text(string, x, y, col)
+
+    def write_cmd(self, cmd):
+        self.dc.low()
+        self.cs.low()
+        self.spi.write(bytearray([cmd]))
+        self.cs.high()
+        
+    def write_data(self, buf):
+        self.dc.high()
+        self.cs.low()
+        self.spi.write(buf)
+        self.cs.high()
+
diff --git a/ports/nrf/examples/ssd1306_mod.py b/ports/nrf/examples/ssd1306_mod.py
new file mode 100644
index 0000000000..0cee2c2a67
--- /dev/null
+++ b/ports/nrf/examples/ssd1306_mod.py
@@ -0,0 +1,27 @@
+# NOTE: Modified version to align with implemented I2C API in nrf port.
+#
+# Examples usage of SSD1306_SPI on pca10040
+#
+# from machine import Pin, SPI
+# from ssd1306 import SSD1306_SPI
+# spi = SPI(0, baudrate=40000000)
+# dc = Pin.board.PA11
+# res = Pin.board.PA12
+# cs = Pin.board.PA13
+# disp = SSD1306_SPI(128, 64, spi, dc, res, cs)
+#
+#
+# Example usage of SSD1306_I2C on pca10040
+#
+# from machine import Pin, I2C
+# from ssd1306_mod import SSD1306_I2C_Mod
+# i2c = I2C(0, Pin.board.PA3, Pin.board.PA4)
+# disp = SSD1306_I2C_Mod(128, 64, i2c)
+
+from ssd1306 import SSD1306_I2C
+
+class SSD1306_I2C_Mod(SSD1306_I2C):
+
+    def write_data(self, buf):
+        buffer = bytearray([0x40]) + buf # Co=0, D/C#=1
+        self.i2c.writeto(self.addr, buffer)
diff --git a/ports/nrf/examples/ubluepy_eddystone.py b/ports/nrf/examples/ubluepy_eddystone.py
new file mode 100644
index 0000000000..c8abd5aea6
--- /dev/null
+++ b/ports/nrf/examples/ubluepy_eddystone.py
@@ -0,0 +1,58 @@
+from ubluepy import Peripheral, constants
+
+BLE_GAP_ADV_FLAG_LE_GENERAL_DISC_MODE       = const(0x02)
+BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED       = const(0x04)
+
+BLE_GAP_ADV_FLAGS_LE_ONLY_GENERAL_DISC_MODE = const(BLE_GAP_ADV_FLAG_LE_GENERAL_DISC_MODE | BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED)
+
+EDDYSTONE_FRAME_TYPE_URL                    = const(0x10)
+EDDYSTONE_URL_PREFIX_HTTP_WWW               = const(0x00) # "http://www".
+EDDYSTONE_URL_SUFFIX_DOT_COM                = const(0x01) # ".com"
+
+def string_to_binarray(text):
+    b = bytearray([])
+    for c in text:
+        b.append(ord(c))
+    return b
+
+def gen_ad_type_content(ad_type, data):
+    b = bytearray(1)
+    b.append(ad_type)
+    b.extend(data)
+    b[0] = len(b) - 1
+    return b
+
+def generate_eddystone_adv_packet(url):
+    # flags
+    disc_mode = bytearray([BLE_GAP_ADV_FLAGS_LE_ONLY_GENERAL_DISC_MODE])
+    packet_flags = gen_ad_type_content(constants.ad_types.AD_TYPE_FLAGS, disc_mode)
+
+    # 16-bit uuid
+    uuid = bytearray([0xAA, 0xFE])
+    packet_uuid16 = gen_ad_type_content(constants.ad_types.AD_TYPE_16BIT_SERVICE_UUID_COMPLETE, uuid)
+
+    # eddystone data
+    rssi = 0xEE # -18 dB, approx signal strength at 0m.
+    eddystone_data = bytearray([])
+    eddystone_data.append(EDDYSTONE_FRAME_TYPE_URL)
+    eddystone_data.append(rssi)
+    eddystone_data.append(EDDYSTONE_URL_PREFIX_HTTP_WWW)
+    eddystone_data.extend(string_to_binarray(url))
+    eddystone_data.append(EDDYSTONE_URL_SUFFIX_DOT_COM)
+
+    # service data
+    service_data = uuid + eddystone_data
+    packet_service_data = gen_ad_type_content(constants.ad_types.AD_TYPE_SERVICE_DATA, service_data)
+
+    # generate advertisment packet
+    packet = bytearray([])
+    packet.extend(packet_flags)
+    packet.extend(packet_uuid16)
+    packet.extend(packet_service_data)
+
+    return packet
+
+def start():
+    adv_packet = generate_eddystone_adv_packet("micropython")  
+    p = Peripheral()
+    p.advertise(data=adv_packet, connectable=False)
\ No newline at end of file
diff --git a/ports/nrf/examples/ubluepy_scan.py b/ports/nrf/examples/ubluepy_scan.py
new file mode 100644
index 0000000000..ab11661cca
--- /dev/null
+++ b/ports/nrf/examples/ubluepy_scan.py
@@ -0,0 +1,38 @@
+from ubluepy import Scanner, constants
+
+def bytes_to_str(bytes):
+    string = ""
+    for b in bytes:
+        string += chr(b)
+    return string
+
+def get_device_names(scan_entries):
+    dev_names = []
+    for e in scan_entries:
+        scan = e.getScanData()
+        if scan:
+            for s in scan:
+               if s[0] == constants.ad_types.AD_TYPE_COMPLETE_LOCAL_NAME:
+                   dev_names.append((e, bytes_to_str(s[2])))
+    return dev_names
+
+def find_device_by_name(name):
+    s = Scanner()
+    scan_res = s.scan(100)
+    
+    device_names = get_device_names(scan_res)
+    for dev in device_names:
+        if name == dev[1]:
+            return dev[0]
+
+# >>> res = find_device_by_name("micr")
+# >>> if res:
+# ...     print("address:", res.addr())
+# ...     print("address type:", res.addr_type())
+# ...     print("rssi:", res.rssi())
+# ...     
+# ...     
+# ... 
+# address: c2:73:61:89:24:45
+# address type: 1
+# rssi: -26
diff --git a/ports/nrf/examples/ubluepy_temp.py b/ports/nrf/examples/ubluepy_temp.py
new file mode 100644
index 0000000000..fac091bc17
--- /dev/null
+++ b/ports/nrf/examples/ubluepy_temp.py
@@ -0,0 +1,92 @@
+# This file is part of the MicroPython project, http://micropython.org/
+#
+# The MIT License (MIT)
+#
+# Copyright (c) 2017 Glenn Ruben Bakke
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+# THE SOFTWARE
+
+from pyb import LED
+from machine import RTC, Temp
+from ubluepy import Service, Characteristic, UUID, Peripheral, constants
+
+def event_handler(id, handle, data):
+    global rtc
+    global periph
+    global serv_env_sense
+    global notif_enabled
+ 
+    if id == constants.EVT_GAP_CONNECTED:
+        # indicated 'connected'
+        LED(1).on()
+
+    elif id == constants.EVT_GAP_DISCONNECTED:
+        # stop low power timer
+        rtc.stop()
+        # indicate 'disconnected'
+        LED(1).off()
+        # restart advertisment
+        periph.advertise(device_name="micr_temp", services=[serv_env_sense])
+
+    elif id == constants.EVT_GATTS_WRITE:
+        # write to this Characteristic is to CCCD
+        if int(data[0]) == 1:
+            notif_enabled = True
+            # start low power timer
+            rtc.start()
+        else: 
+            notif_enabled = False
+            # stop low power timer
+            rtc.stop()
+
+def send_temp(timer_id):
+    global notif_enabled
+    global char_temp
+
+    if notif_enabled:
+        # measure chip temperature
+        temp = Temp.read()
+        temp =  temp * 100
+        char_temp.write(bytearray([temp & 0xFF, temp >> 8]))
+
+# start off with LED(1) off
+LED(1).off()
+
+# use RTC1 as RTC0 is used by bluetooth stack 
+# set up RTC callback every 5 second
+rtc = RTC(1, period=5, mode=RTC.PERIODIC, callback=send_temp)
+
+notif_enabled = False
+
+uuid_env_sense = UUID("0x181A") # Environmental Sensing service
+uuid_temp = UUID("0x2A6E") # Temperature characteristic
+ 
+serv_env_sense = Service(uuid_env_sense)
+
+temp_props = Characteristic.PROP_NOTIFY | Characteristic.PROP_READ
+temp_attrs = Characteristic.ATTR_CCCD
+char_temp = Characteristic(uuid_temp, props = temp_props, attrs = temp_attrs)
+
+serv_env_sense.addCharacteristic(char_temp)
+
+periph = Peripheral()
+periph.addService(serv_env_sense)
+periph.setConnectionHandler(event_handler)
+periph.advertise(device_name="micr_temp", services=[serv_env_sense])
+
diff --git a/ports/nrf/fatfs_port.c b/ports/nrf/fatfs_port.c
new file mode 100644
index 0000000000..13ac21fb1b
--- /dev/null
+++ b/ports/nrf/fatfs_port.c
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "py/runtime.h"
+#include "lib/oofatfs/ff.h"
+
+DWORD get_fattime(void) {
+	// TODO: Implement this function. For now, fake it.
+    return ((2016 - 1980) << 25) | ((12) << 21) | ((4) << 16) | ((00) << 11) | ((18) << 5) | (23 / 2);
+}
diff --git a/ports/nrf/freeze/test.py b/ports/nrf/freeze/test.py
new file mode 100644
index 0000000000..e64bbc9f52
--- /dev/null
+++ b/ports/nrf/freeze/test.py
@@ -0,0 +1,4 @@
+import sys
+
+def hello():
+    print("Hello %s!" % sys.platform)
diff --git a/ports/nrf/gccollect.c b/ports/nrf/gccollect.c
new file mode 100644
index 0000000000..b7aa57a55a
--- /dev/null
+++ b/ports/nrf/gccollect.c
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <stdio.h>
+#include <stdint.h>
+
+#include "py/obj.h"
+#include "py/gc.h"
+#include "gccollect.h"
+
+static inline uint32_t get_msp(void)
+{
+	register uint32_t result;
+	__asm volatile ("MRS %0, msp\n" : "=r" (result) );
+	return(result);
+}
+
+void gc_collect(void) {
+    // start the GC
+    gc_collect_start();
+
+    mp_uint_t sp = get_msp(); // Get stack pointer
+    
+    // trace the stack, including the registers (since they live on the stack in this function)
+    gc_collect_root((void**)sp, ((uint32_t)&_ram_end - sp) / sizeof(uint32_t));
+
+    // end the GC
+    gc_collect_end();
+}
diff --git a/ports/nrf/gccollect.h b/ports/nrf/gccollect.h
new file mode 100644
index 0000000000..6a285b017a
--- /dev/null
+++ b/ports/nrf/gccollect.h
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef GC_COLLECT_H__
+#define GC_COLLECT_H__
+
+extern uint32_t _etext;
+extern uint32_t _sidata;
+extern uint32_t _ram_start;
+extern uint32_t _sdata;
+extern uint32_t _edata;
+extern uint32_t _sbss;
+extern uint32_t _ebss;
+extern uint32_t _heap_start;
+extern uint32_t _heap_end;
+extern uint32_t _estack;
+extern uint32_t _ram_end;
+
+void gc_collect(void);
+
+#endif
diff --git a/ports/nrf/hal/hal_adc.c b/ports/nrf/hal/hal_adc.c
new file mode 100644
index 0000000000..a6cf453914
--- /dev/null
+++ b/ports/nrf/hal/hal_adc.c
@@ -0,0 +1,129 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <stdio.h>
+#include "mphalport.h"
+#include "hal_adc.h"
+
+#ifdef HAL_ADC_MODULE_ENABLED
+
+#define ADC_REF_VOLTAGE_IN_MILLIVOLTS  (1200) // Reference voltage (in milli volts) used by ADC while doing conversion.
+#define ADC_PRE_SCALING_COMPENSATION   (3)    // The ADC is configured to use VDD with 1/3 prescaling as input. And hence the result of conversion is to be multiplied by 3 to get the actual value of the battery voltage.
+#define DIODE_FWD_VOLT_DROP_MILLIVOLTS (270)  // Typical forward voltage drop of the diode (Part no: SD103ATW-7-F) that is connected in series with the voltage supply. This is the voltage drop when the forward current is 1mA. Source: Data sheet of 'SURFACE MOUNT SCHOTTKY BARRIER DIODE ARRAY' available at www.diodes.com.
+
+#define ADC_RESULT_IN_MILLI_VOLTS(ADC_VALUE)\
+        ((((ADC_VALUE) * ADC_REF_VOLTAGE_IN_MILLIVOLTS) / 255) * ADC_PRE_SCALING_COMPENSATION)
+
+static const uint32_t hal_adc_input_lookup[] = {
+    ADC_CONFIG_PSEL_AnalogInput0 << ADC_CONFIG_PSEL_Pos,
+    ADC_CONFIG_PSEL_AnalogInput1 << ADC_CONFIG_PSEL_Pos,
+    ADC_CONFIG_PSEL_AnalogInput2 << ADC_CONFIG_PSEL_Pos,
+    ADC_CONFIG_PSEL_AnalogInput3 << ADC_CONFIG_PSEL_Pos,
+    ADC_CONFIG_PSEL_AnalogInput4 << ADC_CONFIG_PSEL_Pos,
+    ADC_CONFIG_PSEL_AnalogInput5 << ADC_CONFIG_PSEL_Pos,
+    ADC_CONFIG_PSEL_AnalogInput6 << ADC_CONFIG_PSEL_Pos,
+    ADC_CONFIG_PSEL_AnalogInput7 << ADC_CONFIG_PSEL_Pos
+};
+
+
+static uint8_t battery_level_in_percent(const uint16_t mvolts)
+{
+    uint8_t battery_level;
+
+    if (mvolts >= 3000) {
+        battery_level = 100;
+    } else if (mvolts > 2900) {
+        battery_level = 100 - ((3000 - mvolts) * 58) / 100;
+    } else if (mvolts > 2740) {
+        battery_level = 42 - ((2900 - mvolts) * 24) / 160;
+    } else if (mvolts > 2440) {
+        battery_level = 18 - ((2740 - mvolts) * 12) / 300;
+    } else if (mvolts > 2100) {
+        battery_level = 6 - ((2440 - mvolts) * 6) / 340;
+    } else {
+        battery_level = 0;
+    }
+
+    return battery_level;
+}
+
+uint16_t hal_adc_channel_value(hal_adc_config_t const * p_adc_conf) {
+    ADC_BASE->INTENSET   = ADC_INTENSET_END_Msk;
+    ADC_BASE->CONFIG     = (ADC_CONFIG_RES_8bit                        << ADC_CONFIG_RES_Pos)
+                           | (ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling << ADC_CONFIG_INPSEL_Pos)
+                           | (ADC_CONFIG_REFSEL_VBG                      << ADC_CONFIG_REFSEL_Pos)
+                           | (hal_adc_input_lookup[p_adc_conf->channel])
+                           | (ADC_CONFIG_EXTREFSEL_None                  << ADC_CONFIG_EXTREFSEL_Pos);
+
+    ADC_BASE->EVENTS_END  = 0;
+    ADC_BASE->ENABLE      = ADC_ENABLE_ENABLE_Enabled;
+
+    ADC_BASE->EVENTS_END  = 0;
+    ADC_BASE->TASKS_START = 1;
+
+    while (!ADC_BASE->EVENTS_END) {
+        ;
+    }
+
+    uint8_t  adc_result;
+
+    ADC_BASE->EVENTS_END = 0;
+    adc_result           = ADC_BASE->RESULT;
+    ADC_BASE->TASKS_STOP = 1;
+
+    return adc_result;
+}
+
+uint16_t hal_adc_battery_level(void) {
+    ADC_BASE->INTENSET   = ADC_INTENSET_END_Msk;
+    ADC_BASE->CONFIG     = (ADC_CONFIG_RES_8bit                        << ADC_CONFIG_RES_Pos)
+                           | (ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling << ADC_CONFIG_INPSEL_Pos)
+                           | (ADC_CONFIG_REFSEL_VBG                      << ADC_CONFIG_REFSEL_Pos)
+                           | (ADC_CONFIG_PSEL_Disabled                   << ADC_CONFIG_PSEL_Pos)
+                           | (ADC_CONFIG_EXTREFSEL_None                  << ADC_CONFIG_EXTREFSEL_Pos);
+
+    ADC_BASE->EVENTS_END  = 0;
+    ADC_BASE->ENABLE      = ADC_ENABLE_ENABLE_Enabled;
+
+    ADC_BASE->EVENTS_END  = 0;
+    ADC_BASE->TASKS_START = 1;
+
+    while (!ADC_BASE->EVENTS_END) {
+        ;
+    }
+
+    uint8_t  adc_result;
+    uint16_t batt_lvl_in_milli_volts;
+
+    ADC_BASE->EVENTS_END = 0;
+    adc_result           = ADC_BASE->RESULT;
+    ADC_BASE->TASKS_STOP = 1;
+
+    batt_lvl_in_milli_volts = ADC_RESULT_IN_MILLI_VOLTS(adc_result) + DIODE_FWD_VOLT_DROP_MILLIVOLTS;
+    return battery_level_in_percent(batt_lvl_in_milli_volts);
+}
+
+#endif // HAL_ADC_MODULE_ENABLED
diff --git a/ports/nrf/hal/hal_adc.h b/ports/nrf/hal/hal_adc.h
new file mode 100644
index 0000000000..76ed7e6618
--- /dev/null
+++ b/ports/nrf/hal/hal_adc.h
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HAL_ADC_H__
+#define HAL_ADC_H__
+
+#include <stdint.h>
+
+#include "nrf.h"
+
+#if NRF51
+
+#define ADC_IRQ_NUM ADC_IRQn
+#define ADC_BASE ((NRF_ADC_Type *)NRF_ADC_BASE)
+#define HAL_ADC_Type NRF_ADC_Type
+
+#else
+
+#define ADC_IRQ_NUM SAADC_IRQn
+#define ADC_BASE ((NRF_SAADC_Type *)NRF_SAADC_BASE)
+#define HAL_ADC_Type NRF_SAADC_Type
+
+#endif
+
+typedef enum {
+    HAL_ADC_CHANNEL_2 = 2,
+    HAL_ADC_CHANNEL_3,
+    HAL_ADC_CHANNEL_4,
+    HAL_ADC_CHANNEL_5,
+    HAL_ADC_CHANNEL_6,
+    HAL_ADC_CHANNEL_7,
+} hal_adc_channel_t;
+
+/**
+  * @brief  ADC Configuration Structure definition
+  */
+typedef struct {
+    hal_adc_channel_t channel;
+} hal_adc_config_t;
+
+/**
+  * @brief  ADC handle Structure definition
+  */
+typedef struct __ADC_HandleTypeDef {
+    hal_adc_config_t config;         /* ADC config parameters */
+} ADC_HandleTypeDef;
+
+uint16_t hal_adc_channel_value(hal_adc_config_t const * p_adc_conf);
+
+uint16_t hal_adc_battery_level(void);
+
+#endif // HAL_ADC_H__
diff --git a/ports/nrf/hal/hal_adce.c b/ports/nrf/hal/hal_adce.c
new file mode 100644
index 0000000000..0abdf07c37
--- /dev/null
+++ b/ports/nrf/hal/hal_adce.c
@@ -0,0 +1,118 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "mphalport.h"
+#include "hal_adc.h"
+
+#ifdef HAL_ADCE_MODULE_ENABLED
+
+static const uint32_t hal_adc_input_lookup_pos[] = {
+    SAADC_CH_PSELP_PSELP_AnalogInput0 << SAADC_CH_PSELP_PSELP_Pos,
+    SAADC_CH_PSELP_PSELP_AnalogInput1 << SAADC_CH_PSELP_PSELP_Pos,
+    SAADC_CH_PSELP_PSELP_AnalogInput2 << SAADC_CH_PSELP_PSELP_Pos,
+    SAADC_CH_PSELP_PSELP_AnalogInput3 << SAADC_CH_PSELP_PSELP_Pos,
+    SAADC_CH_PSELP_PSELP_AnalogInput4 << SAADC_CH_PSELP_PSELP_Pos,
+    SAADC_CH_PSELP_PSELP_AnalogInput5 << SAADC_CH_PSELP_PSELP_Pos,
+    SAADC_CH_PSELP_PSELP_AnalogInput6 << SAADC_CH_PSELP_PSELP_Pos,
+    SAADC_CH_PSELP_PSELP_AnalogInput7 << SAADC_CH_PSELP_PSELP_Pos
+};
+
+#define HAL_ADCE_PSELP_NOT_CONNECTED (SAADC_CH_PSELP_PSELP_NC << SAADC_CH_PSELP_PSELP_Pos)
+#define HAL_ADCE_PSELP_VDD           (SAADC_CH_PSELP_PSELP_VDD << SAADC_CH_PSELP_PSELP_Pos)
+
+/*static const uint32_t hal_adc_input_lookup_neg[] = {
+    SAADC_CH_PSELN_PSELN_AnalogInput0 << SAADC_CH_PSELN_PSELN_Pos,
+    SAADC_CH_PSELN_PSELN_AnalogInput1 << SAADC_CH_PSELN_PSELN_Pos,
+    SAADC_CH_PSELN_PSELN_AnalogInput2 << SAADC_CH_PSELN_PSELN_Pos,
+    SAADC_CH_PSELN_PSELN_AnalogInput3 << SAADC_CH_PSELN_PSELN_Pos,
+    SAADC_CH_PSELN_PSELN_AnalogInput4 << SAADC_CH_PSELN_PSELN_Pos,
+    SAADC_CH_PSELN_PSELN_AnalogInput5 << SAADC_CH_PSELN_PSELN_Pos,
+    SAADC_CH_PSELN_PSELN_AnalogInput6 << SAADC_CH_PSELN_PSELN_Pos,
+    SAADC_CH_PSELN_PSELN_AnalogInput7 << SAADC_CH_PSELN_PSELN_Pos
+};*/
+
+#define HAL_ADCE_PSELN_NOT_CONNECTED (SAADC_CH_PSELN_PSELN_NC << SAADC_CH_PSELN_PSELN_Pos)
+#define HAL_ADCE_PSELN_VDD           (SAADC_CH_PSELN_PSELN_VDD << SAADC_CH_PSELN_PSELN_Pos)
+
+uint16_t hal_adc_channel_value(hal_adc_config_t const * p_adc_conf) {
+    int16_t result = 0;
+
+    // configure to use VDD/4 and gain 1/4
+    ADC_BASE->CH[0].CONFIG = (SAADC_CH_CONFIG_GAIN_Gain1_4  << SAADC_CH_CONFIG_GAIN_Pos)
+                           | (SAADC_CH_CONFIG_MODE_SE       << SAADC_CH_CONFIG_MODE_Pos)
+                           | (SAADC_CH_CONFIG_REFSEL_VDD1_4 << SAADC_CH_CONFIG_REFSEL_Pos)
+                           | (SAADC_CH_CONFIG_RESN_Bypass   << SAADC_CH_CONFIG_RESN_Pos)
+                           | (SAADC_CH_CONFIG_RESP_Bypass   << SAADC_CH_CONFIG_RESP_Pos)
+                           | (SAADC_CH_CONFIG_TACQ_3us      << SAADC_CH_CONFIG_TACQ_Pos);
+
+    // positive input
+    ADC_BASE->CH[0].PSELP = hal_adc_input_lookup_pos[p_adc_conf->channel]; // HAL_ADCE_PSELP_VDD;
+    ADC_BASE->CH[0].PSELN = HAL_ADCE_PSELN_NOT_CONNECTED;
+
+    ADC_BASE->RESOLUTION    = SAADC_RESOLUTION_VAL_8bit << SAADC_RESOLUTION_VAL_Pos;
+    ADC_BASE->RESULT.MAXCNT = 1;
+    ADC_BASE->RESULT.PTR    = (uint32_t)&result;
+    ADC_BASE->SAMPLERATE    = SAADC_SAMPLERATE_MODE_Task << SAADC_SAMPLERATE_MODE_Pos;
+    ADC_BASE->ENABLE        = SAADC_ENABLE_ENABLE_Enabled << SAADC_ENABLE_ENABLE_Pos;
+
+    // calibrate ADC
+    ADC_BASE->TASKS_CALIBRATEOFFSET = 1;
+    while (ADC_BASE->EVENTS_CALIBRATEDONE == 0) {
+        ;
+    }
+    ADC_BASE->EVENTS_CALIBRATEDONE = 0;
+    while (ADC_BASE->STATUS == (SAADC_STATUS_STATUS_Busy << SAADC_STATUS_STATUS_Pos)) {
+        ;
+    }
+
+    // start the ADC
+    ADC_BASE->TASKS_START = 1;
+    while (ADC_BASE->EVENTS_STARTED == 0) {
+        ;
+    }
+    ADC_BASE->EVENTS_STARTED = 0;
+
+    // sample ADC
+    ADC_BASE->TASKS_SAMPLE = 1;
+    while (ADC_BASE->EVENTS_END == 0) {
+        ;
+    }
+    ADC_BASE->EVENTS_END = 0;
+
+    ADC_BASE->TASKS_STOP = 1;
+    while (ADC_BASE->EVENTS_STOPPED == 0) {
+        ;
+    }
+    ADC_BASE->EVENTS_STOPPED = 0;
+
+    return result;
+}
+
+uint16_t hal_adc_battery_level(void) {
+    return 0;
+}
+
+#endif // HAL_ADCE_MODULE_ENABLED
diff --git a/ports/nrf/hal/hal_gpio.c b/ports/nrf/hal/hal_gpio.c
new file mode 100644
index 0000000000..7cc57af2b9
--- /dev/null
+++ b/ports/nrf/hal/hal_gpio.c
@@ -0,0 +1,117 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "hal_gpio.h"
+#include "mphalport.h"
+#include "hal_irq.h"
+
+#define GPIOTE_IRQ_NUM GPIOTE_IRQn
+#define GPIOTE_BASE ((NRF_GPIOTE_Type *)NRF_GPIOTE_BASE)
+#define HAL_GPIOTE_Type NRF_GPIOTE_Type
+
+static hal_gpio_event_callback_t m_callback;
+
+void hal_gpio_register_callback(hal_gpio_event_callback_t cb) {
+    m_callback = cb;
+
+#if 0
+    hal_gpio_event_config_t config;
+    config.channel    = HAL_GPIO_EVENT_CHANNEL_0;
+    config.event      = HAL_GPIO_POLARITY_EVENT_HIGH_TO_LOW;
+    config.init_level = 1;
+    config.pin        = 13;
+    config.port       = 0;
+
+    // start LFCLK if not already started
+    if (NRF_CLOCK->LFCLKSTAT == 0) {
+        NRF_CLOCK->TASKS_LFCLKSTART = 1;
+        while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0);
+        NRF_CLOCK->EVENTS_LFCLKSTARTED = 0;
+    }
+
+	hal_irq_enable(GPIOTE_IRQ_NUM);
+    hal_irq_priority(GPIOTE_IRQ_NUM, 3);
+
+    hal_gpio_event_config(&config);
+#endif
+}
+
+void hal_gpio_event_config(hal_gpio_event_config_t const * p_config) {
+#if 0
+    hal_gpio_cfg_pin(p_config->port, p_config->pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_UP);
+
+    uint8_t channel = (uint8_t)p_config->channel;
+    GPIOTE_BASE->CONFIG[channel] = \
+          GPIOTE_CONFIG_MODE_Event << GPIOTE_CONFIG_MODE_Pos \
+        | p_config->pin << GPIOTE_CONFIG_PSEL_Pos \
+        | p_config->event \
+        | p_config->init_level << GPIOTE_CONFIG_OUTINIT_Pos;
+
+    GPIOTE_BASE->INTENSET = 1 << channel;
+    GPIOTE_BASE->EVENTS_IN[channel] = 0;
+#endif
+}
+
+#if 0
+
+void GPIOTE_IRQHandler(void) {
+    if (GPIOTE_BASE->EVENTS_IN[0]) {
+        GPIOTE_BASE->EVENTS_IN[0] = 0;
+        m_callback(HAL_GPIO_EVENT_CHANNEL_0);
+    }
+    if (GPIOTE_BASE->EVENTS_IN[1]) {
+        GPIOTE_BASE->EVENTS_IN[1] = 0;
+        m_callback(HAL_GPIO_EVENT_CHANNEL_1);
+    }
+    if (GPIOTE_BASE->EVENTS_IN[2]) {
+        GPIOTE_BASE->EVENTS_IN[2] = 0;
+        m_callback(HAL_GPIO_EVENT_CHANNEL_2);
+    }
+    if (GPIOTE_BASE->EVENTS_IN[3]) {
+        GPIOTE_BASE->EVENTS_IN[3] = 0;
+        m_callback(HAL_GPIO_EVENT_CHANNEL_3);
+    }
+#if NRF52
+    if (GPIOTE_BASE->EVENTS_IN[4]) {
+        GPIOTE_BASE->EVENTS_IN[4] = 0;
+        m_callback(HAL_GPIO_EVENT_CHANNEL_4);
+    }
+    if (GPIOTE_BASE->EVENTS_IN[5]) {
+        GPIOTE_BASE->EVENTS_IN[5] = 0;
+        m_callback(HAL_GPIO_EVENT_CHANNEL_5);
+    }
+    if (GPIOTE_BASE->EVENTS_IN[6]) {
+        GPIOTE_BASE->EVENTS_IN[6] = 0;
+        m_callback(HAL_GPIO_EVENT_CHANNEL_6);
+    }
+    if (GPIOTE_BASE->EVENTS_IN[7]) {
+        GPIOTE_BASE->EVENTS_IN[7] = 0;
+        m_callback(HAL_GPIO_EVENT_CHANNEL_7);
+    }
+#endif
+}
+
+#endif // if 0
diff --git a/ports/nrf/hal/hal_gpio.h b/ports/nrf/hal/hal_gpio.h
new file mode 100644
index 0000000000..afd03d0dce
--- /dev/null
+++ b/ports/nrf/hal/hal_gpio.h
@@ -0,0 +1,128 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HAL_GPIO_H__
+#define HAL_GPIO_H__
+
+#include "nrf.h"
+
+#if NRF51
+  #define POINTERS (const uint32_t[]){NRF_GPIO_BASE}
+#endif
+
+#if NRF52
+  #ifdef NRF52832_XXAA
+    #define POINTERS (const uint32_t[]){NRF_P0_BASE}
+  #endif
+
+  #ifdef NRF52840_XXAA
+    #define POINTERS (const uint32_t[]){NRF_P0_BASE, NRF_P1_BASE}
+  #endif
+#endif
+
+#define GPIO_BASE(x) ((NRF_GPIO_Type *)POINTERS[x])
+
+#define hal_gpio_pin_high(p) (((NRF_GPIO_Type *)(GPIO_BASE((p)->port)))->OUTSET = (p)->pin_mask)
+#define hal_gpio_pin_low(p)  (((NRF_GPIO_Type *)(GPIO_BASE((p)->port)))->OUTCLR = (p)->pin_mask)
+#define hal_gpio_pin_read(p) (((NRF_GPIO_Type *)(GPIO_BASE((p)->port)))->IN >> ((p)->pin) & 1)
+
+typedef enum {
+    HAL_GPIO_POLARITY_EVENT_LOW_TO_HIGH = GPIOTE_CONFIG_POLARITY_LoToHi << GPIOTE_CONFIG_POLARITY_Pos,
+    HAL_GPIO_POLARITY_EVENT_HIGH_TO_LOW = GPIOTE_CONFIG_POLARITY_HiToLo << GPIOTE_CONFIG_POLARITY_Pos,
+    HAL_GPIO_POLARITY_EVENT_TOGGLE      = GPIOTE_CONFIG_POLARITY_Toggle << GPIOTE_CONFIG_POLARITY_Pos
+} hal_gpio_polarity_event_t;
+
+typedef enum {
+    HAL_GPIO_PULL_DISABLED = (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos),
+    HAL_GPIO_PULL_DOWN     = (GPIO_PIN_CNF_PULL_Pulldown << GPIO_PIN_CNF_PULL_Pos),
+    HAL_GPIO_PULL_UP       = (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos)
+} hal_gpio_pull_t;
+
+typedef enum {
+    HAL_GPIO_MODE_OUTPUT = (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos),
+    HAL_GPIO_MODE_INPUT  = (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos),
+} hal_gpio_mode_t;
+
+static inline void hal_gpio_cfg_pin(uint8_t port, uint32_t pin_number, hal_gpio_mode_t mode, hal_gpio_pull_t pull) {
+    GPIO_BASE(port)->PIN_CNF[pin_number] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
+                                         | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
+                                         | pull
+                                         | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
+                                         | mode;
+}
+
+static inline void hal_gpio_out_set(uint8_t port, uint32_t pin_mask) {
+    GPIO_BASE(port)->OUTSET = pin_mask;
+}
+
+static inline void hal_gpio_out_clear(uint8_t port, uint32_t pin_mask) {
+    GPIO_BASE(port)->OUTCLR = pin_mask;
+}
+
+static inline void hal_gpio_pin_set(uint8_t port, uint32_t pin) {
+    GPIO_BASE(port)->OUTSET = (1 << pin);
+}
+
+static inline void hal_gpio_pin_clear(uint8_t port, uint32_t pin) {
+    GPIO_BASE(port)->OUTCLR = (1 << pin);
+}
+
+static inline void hal_gpio_pin_toggle(uint8_t port, uint32_t pin) {
+    uint32_t pin_mask   = (1 << pin);
+    uint32_t pins_state = NRF_GPIO->OUT;
+
+    GPIO_BASE(port)->OUTSET = (~pins_state) & pin_mask;
+    GPIO_BASE(port)->OUTCLR = pins_state & pin_mask;
+}
+
+typedef enum {
+    HAL_GPIO_EVENT_CHANNEL_0 = 0,
+    HAL_GPIO_EVENT_CHANNEL_1,
+    HAL_GPIO_EVENT_CHANNEL_2,
+    HAL_GPIO_EVENT_CHANNEL_3,
+#if NRF52
+    HAL_GPIO_EVENT_CHANNEL_4,
+    HAL_GPIO_EVENT_CHANNEL_5,
+    HAL_GPIO_EVENT_CHANNEL_6,
+    HAL_GPIO_EVENT_CHANNEL_7
+#endif
+} hal_gpio_event_channel_t;
+
+typedef struct {
+    hal_gpio_event_channel_t  channel;
+    hal_gpio_polarity_event_t event;
+    uint32_t                  pin;
+    uint8_t                   port;
+    uint8_t                   init_level;
+} hal_gpio_event_config_t;
+
+typedef void (*hal_gpio_event_callback_t)(hal_gpio_event_channel_t channel);
+
+void hal_gpio_register_callback(hal_gpio_event_callback_t cb);
+
+void hal_gpio_event_config(hal_gpio_event_config_t const * p_config);
+
+#endif // HAL_GPIO_H__
diff --git a/ports/nrf/hal/hal_irq.h b/ports/nrf/hal/hal_irq.h
new file mode 100644
index 0000000000..d8e4ddba42
--- /dev/null
+++ b/ports/nrf/hal/hal_irq.h
@@ -0,0 +1,119 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HAL_IRQ_H__
+#define HAL_IRQ_H__
+
+#include <stdint.h>
+
+#include "nrf.h"
+
+#if BLUETOOTH_SD
+#include "py/nlr.h"
+#include "ble_drv.h"
+
+#define BLUETOOTH_STACK_ENABLED() (ble_drv_stack_enabled())
+
+#ifdef NRF51
+  #include "nrf_soc.h"
+#elif defined(NRF52)
+  #include "nrf_nvic.h"
+#endif
+#endif // BLUETOOTH_SD
+
+static inline void hal_irq_clear(uint32_t irq_num) {
+#if BLUETOOTH_SD
+    if (BLUETOOTH_STACK_ENABLED() == 1) {
+        if (sd_nvic_ClearPendingIRQ(irq_num) != 0) {
+            nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
+                      "IRQ (%d) clear error", irq_num));
+        }
+    } else
+#endif // BLUETOOTH_SD
+    {
+        NVIC_ClearPendingIRQ(irq_num);
+    }
+}
+
+static inline void hal_irq_enable(uint32_t irq_num) {
+    hal_irq_clear(irq_num);
+
+#if BLUETOOTH_SD
+    if (BLUETOOTH_STACK_ENABLED() == 1) {
+        if (sd_nvic_EnableIRQ(irq_num) != 0) {
+            nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
+                      "IRQ (%d) enable error", irq_num));
+        }
+    } else
+#endif // BLUETOOTH_SD
+    {
+        NVIC_EnableIRQ(irq_num);
+    }
+}
+
+static inline void hal_irq_disable(uint32_t irq_num) {
+#if BLUETOOTH_SD
+    if (BLUETOOTH_STACK_ENABLED() == 1) {
+        if (sd_nvic_DisableIRQ(irq_num) != 0) {
+            nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
+                      "IRQ (%d) disable error", irq_num));
+        }
+    } else
+#endif // BLUETOOTH_SD
+    {
+        NVIC_DisableIRQ(irq_num);
+    }
+}
+
+static inline void hal_irq_priority(uint32_t irq_num, uint8_t priority) {
+#if BLUETOOTH_SD
+    if (BLUETOOTH_STACK_ENABLED() == 1) {
+        if (sd_nvic_SetPriority(irq_num, priority) != 0) {
+            nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
+                      "IRQ (%d) priority error", irq_num, priority));
+        }
+    } else
+#endif // BLUETOOTH_SD
+    {
+        NVIC_SetPriority(irq_num, priority);
+    }
+}
+
+static inline void hal_irq_pending(uint32_t irq_num) {
+#if BLUETOOTH_SD
+    if (BLUETOOTH_STACK_ENABLED() == 1) {
+        if (sd_nvic_SetPendingIRQ(irq_num) != 0) {
+            nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
+                      "IRQ (%d) pending error", irq_num));
+        }
+    } else
+#endif // BLUETOOTH_SD
+    {
+        NVIC_SetPendingIRQ(irq_num);
+    }
+}
+
+#endif // HAL_IRQ_H__
diff --git a/ports/nrf/hal/hal_pwm.c b/ports/nrf/hal/hal_pwm.c
new file mode 100644
index 0000000000..c7ae31a996
--- /dev/null
+++ b/ports/nrf/hal/hal_pwm.c
@@ -0,0 +1,118 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <stdint.h>
+#include <stdio.h>
+
+#include "mphalport.h"
+#include "hal_pwm.h"
+
+#ifdef HAL_PWM_MODULE_ENABLED
+
+#define PWM_COUNTER_TOP 16000 // 16MHz divided by 16000-> 1ms
+
+volatile uint16_t g_pwm_seq[4];
+volatile uint16_t g_pwm_period;
+
+static const uint32_t hal_pwm_frequency_lookup[] = {
+    PWM_PRESCALER_PRESCALER_DIV_1, // 16MHz
+    PWM_PRESCALER_PRESCALER_DIV_2, // 8MHz
+    PWM_PRESCALER_PRESCALER_DIV_4, // 4MHz
+    PWM_PRESCALER_PRESCALER_DIV_8, // 2MHz
+    PWM_PRESCALER_PRESCALER_DIV_16, // 1MHz
+    PWM_PRESCALER_PRESCALER_DIV_32, // 500kHz
+    PWM_PRESCALER_PRESCALER_DIV_64, // 250kHz
+    PWM_PRESCALER_PRESCALER_DIV_128 // 125kHz
+};
+
+void hal_pwm_init(NRF_PWM_Type * p_instance, hal_pwm_init_t const * p_pwm_init) {
+    g_pwm_period = p_pwm_init->period;
+    uint16_t pulse_width = ((g_pwm_period * p_pwm_init->duty)/100);
+
+    if (p_pwm_init->pulse_width > 0) {
+        pulse_width = p_pwm_init->pulse_width;
+    }
+
+    if (p_pwm_init->mode == HAL_PWM_MODE_HIGH_LOW) {
+        g_pwm_seq[0] = g_pwm_period - pulse_width;
+        g_pwm_seq[1] = g_pwm_period - pulse_width;
+    } else {
+        g_pwm_seq[0] = pulse_width;
+        g_pwm_seq[1] = pulse_width;
+    }
+
+    g_pwm_seq[2] = 0;
+    g_pwm_seq[3] = 0;
+
+    p_instance->PSEL.OUT[0] = (p_pwm_init->pwm_pin << PWM_PSEL_OUT_PIN_Pos)
+    		                | (PWM_PSEL_OUT_CONNECT_Connected << PWM_PSEL_OUT_CONNECT_Pos);
+
+    p_instance->ENABLE      = (PWM_ENABLE_ENABLE_Enabled << PWM_ENABLE_ENABLE_Pos);
+    p_instance->MODE        = (PWM_MODE_UPDOWN_Up << PWM_MODE_UPDOWN_Pos);
+    p_instance->PRESCALER   = (hal_pwm_frequency_lookup[p_pwm_init->freq] << PWM_PRESCALER_PRESCALER_Pos);
+    p_instance->COUNTERTOP  = (p_pwm_init->period << PWM_COUNTERTOP_COUNTERTOP_Pos);
+    p_instance->LOOP        = (PWM_LOOP_CNT_Disabled << PWM_LOOP_CNT_Pos);
+    p_instance->DECODER     = (PWM_DECODER_LOAD_Individual << PWM_DECODER_LOAD_Pos)
+                            | (PWM_DECODER_MODE_RefreshCount << PWM_DECODER_MODE_Pos);
+    p_instance->SEQ[0].PTR  = ((uint32_t)(g_pwm_seq) << PWM_SEQ_PTR_PTR_Pos);
+    p_instance->SEQ[0].CNT  = ((sizeof(g_pwm_seq) / sizeof(uint16_t)) << PWM_SEQ_CNT_CNT_Pos);
+
+    p_instance->SEQ[0].REFRESH    = 0;
+    p_instance->SEQ[0].ENDDELAY   = 0;
+}
+
+void hal_pwm_start(NRF_PWM_Type * p_instance) {
+    p_instance->TASKS_SEQSTART[0] = 1;
+}
+
+void hal_pwm_stop(NRF_PWM_Type * p_instance) {
+    p_instance->TASKS_SEQSTART[0] = 0;
+    p_instance->ENABLE            = (PWM_ENABLE_ENABLE_Disabled << PWM_ENABLE_ENABLE_Pos);
+}
+
+void hal_pwm_freq_set(NRF_PWM_Type * p_instance, uint16_t freq) {
+#if 0
+    p_instance->PRESCALER = (hal_pwm_frequency_lookup[freq] << PWM_PRESCALER_PRESCALER_Pos);
+#endif
+}
+
+void hal_pwm_period_set(NRF_PWM_Type * p_instance, uint16_t period) {
+#if 0
+    g_pwm_period = period;
+    p_instance->COUNTERTOP = (g_pwm_period << PWM_COUNTERTOP_COUNTERTOP_Pos);
+#endif
+}
+
+void hal_pwm_duty_set(NRF_PWM_Type * p_instance, uint8_t duty) {
+#if 0
+    uint16_t duty_cycle = ((g_pwm_period * duty)/100);
+
+    g_pwm_seq[0] = duty_cycle;
+    g_pwm_seq[1] = duty_cycle;
+#endif
+}
+
+#endif // HAL_PWM_MODULE_ENABLED
diff --git a/ports/nrf/hal/hal_pwm.h b/ports/nrf/hal/hal_pwm.h
new file mode 100644
index 0000000000..49214ed200
--- /dev/null
+++ b/ports/nrf/hal/hal_pwm.h
@@ -0,0 +1,108 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HAL_PWM_H__
+#define HAL_PWM_H__
+
+#include <stdint.h>
+
+#include "nrf.h"
+
+// TODO: nrf51 series need Soft PWM. Not part of HAL.
+
+#if NRF52
+
+#define PWM0  ((NRF_PWM_Type *)NRF_PWM0_BASE)
+#define PWM0_IRQ_NUM PWM1_IRQn
+#define PWM1  ((NRF_PWM_Type *)NRF_PWM1_BASE)
+#define PWM1_IRQ_NUM PWM1_IRQn
+#define PWM2  ((NRF_PWM_Type *)NRF_PWM2_BASE)
+#define PWM2_IRQ_NUM PWM2_IRQn
+
+#if 0 // TODO: nrf52840
+#define PWM3  ((NRF_PWM_Type *)NRF_PWM3_BASE)
+#define PWM3_IRQ_NUM PWM3_IRQn
+#endif
+
+#else
+#error "Device not supported."
+#endif
+
+/**
+  * @brief  PWM frequency type definition
+  */
+typedef enum {
+    HAL_PWM_FREQ_16Mhz = 0,
+    HAL_PWM_FREQ_8Mhz,
+    HAL_PWM_FREQ_4Mhz,
+    HAL_PWM_FREQ_2Mhz,
+    HAL_PWM_FREQ_1Mhz,
+    HAL_PWM_FREQ_500khz,
+    HAL_PWM_FREQ_250khz,
+    HAL_PWM_FREQ_125khz
+} hal_pwm_freq_t;
+
+/**
+  * @brief  PWM mode type definition
+  */
+typedef enum {
+    HAL_PWM_MODE_LOW_HIGH = 0,
+    HAL_PWM_MODE_HIGH_LOW
+} hal_pwm_mode_t;
+
+
+typedef struct {
+    uint8_t pwm_pin;
+    hal_pwm_freq_t freq;
+    uint8_t duty;
+    uint16_t pulse_width;
+    uint16_t period;
+    hal_pwm_mode_t mode;
+} hal_pwm_init_t;
+
+/**
+  * @brief  PWM handle Structure definition
+  */
+typedef struct __PWM_HandleTypeDef
+{
+    NRF_PWM_Type               *instance;    /* PWM registers base address */
+    hal_pwm_init_t             init;         /* PWM initialization parameters */
+} PWM_HandleTypeDef;
+
+
+void hal_pwm_init(NRF_PWM_Type * p_instance, hal_pwm_init_t const * p_pwm_init);
+
+void hal_pwm_freq_set(NRF_PWM_Type * p_instance, uint16_t freq);
+
+void hal_pwm_period_set(NRF_PWM_Type * p_instance, uint16_t period);
+
+void hal_pwm_duty_set(NRF_PWM_Type * p_instance, uint8_t duty);
+
+void hal_pwm_start(NRF_PWM_Type * p_instance);
+
+void hal_pwm_stop(NRF_PWM_Type * p_instance);
+
+#endif // HAL_PWM_H__
diff --git a/ports/nrf/hal/hal_qspie.c b/ports/nrf/hal/hal_qspie.c
new file mode 100644
index 0000000000..90863b6203
--- /dev/null
+++ b/ports/nrf/hal/hal_qspie.c
@@ -0,0 +1,122 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "mphalport.h"
+#include "hal_qspie.h"
+
+#ifdef HAL_QSPIE_MODULE_ENABLED
+
+#define QSPI_IRQ_NUM QSPI_IRQn
+#define QSPI_BASE ((NRF_QSPI_Type *)NRF_QSPI_BASE)
+
+// frequency, 32 MHz / (SCKFREQ + 1)
+static const uint32_t hal_qspi_frequency_lookup[] = {
+    (15 << QSPI_IFCONFIG1_SCKFREQ_Pos), // 2 Mbps
+    (7  << QSPI_IFCONFIG1_SCKFREQ_Pos), // 4 Mbps
+    (3  << QSPI_IFCONFIG1_SCKFREQ_Pos), // 8 Mbps
+    (1  << QSPI_IFCONFIG1_SCKFREQ_Pos), // 16 Mbps
+    (0  << QSPI_IFCONFIG1_SCKFREQ_Pos), // 32 Mbps
+};
+
+void hal_qspi_master_init(NRF_QSPI_Type * p_instance, hal_qspi_init_t const * p_qspi_init)
+{
+	// configure SCK
+    p_instance->PSEL.SCK = (p_qspi_init->clk_pin << QSPI_PSEL_SCK_PIN_Pos)
+                         | (p_qspi_init->clk_pin_port << QSPI_PSEL_SCK_PORT_Pos)
+                         | (QSPI_PSEL_SCK_CONNECT_Connected << QSPI_PSEL_SCK_CONNECT_Pos);
+
+    // configure CS
+    if (p_qspi_init->use_csn) {
+        p_instance->PSEL.CSN = (p_qspi_init->clk_pin << QSPI_PSEL_CSN_PIN_Pos)
+                             | (p_qspi_init->clk_pin_port << QSPI_PSEL_CSN_PORT_Pos)
+                             | (QSPI_PSEL_CSN_CONNECT_Connected << QSPI_PSEL_CSN_CONNECT_Pos);
+    } else {
+        p_instance->PSEL.CSN = (QSPI_PSEL_CSN_CONNECT_Disconnected << QSPI_PSEL_CSN_CONNECT_Pos);
+    }
+
+    // configure MOSI/IO0, valid for all configurations
+    p_instance->PSEL.IO0 = (p_qspi_init->d0_mosi_pin << QSPI_PSEL_IO0_PIN_Pos)
+                        | (p_qspi_init->d0_mosi_pin_port << QSPI_PSEL_IO0_PORT_Pos)
+                        | (QSPI_PSEL_IO0_CONNECT_Connected << QSPI_PSEL_IO0_CONNECT_Pos);
+
+    if (p_qspi_init->data_line != HAL_QSPI_DATA_LINE_SINGLE) {
+        // configure MISO/IO1
+        p_instance->PSEL.IO1 = (p_qspi_init->d1_miso_pin << QSPI_PSEL_IO1_PIN_Pos)
+                            | (p_qspi_init->d1_miso_pin_port << QSPI_PSEL_IO1_PORT_Pos)
+                            | (QSPI_PSEL_IO1_CONNECT_Connected << QSPI_PSEL_IO1_CONNECT_Pos);
+
+        if (p_qspi_init->data_line == HAL_QSPI_DATA_LINE_QUAD) {
+            // configure IO2
+            p_instance->PSEL.IO2 = (p_qspi_init->d2_pin << QSPI_PSEL_IO2_PIN_Pos)
+                                | (p_qspi_init->d2_pin_port << QSPI_PSEL_IO2_PORT_Pos)
+                                | (QSPI_PSEL_IO2_CONNECT_Connected << QSPI_PSEL_IO2_CONNECT_Pos);
+
+            // configure IO3
+            p_instance->PSEL.IO3 = (p_qspi_init->d3_pin << QSPI_PSEL_IO3_PIN_Pos)
+                                | (p_qspi_init->d3_pin_port << QSPI_PSEL_IO3_PORT_Pos)
+                                | (QSPI_PSEL_IO3_CONNECT_Connected << QSPI_PSEL_IO3_CONNECT_Pos);
+        }
+    }
+
+    uint32_t mode;
+    switch (p_qspi_init->mode) {
+        case HAL_SPI_MODE_CPOL0_CPHA0:
+            mode = (QSPI_IFCONFIG1_SPIMODE_MODE0 << QSPI_IFCONFIG1_SPIMODE_Pos);
+            break;
+        case HAL_SPI_MODE_CPOL1_CPHA1:
+            mode = (QSPI_IFCONFIG1_SPIMODE_MODE3 << QSPI_IFCONFIG1_SPIMODE_Pos);
+            break;
+        default:
+            mode = 0;
+            break;
+    }
+
+    // interface config1
+    p_instance->IFCONFIG1 = hal_qspi_frequency_lookup[p_qspi_init->freq]
+                          | mode
+                          | (1 << QSPI_IFCONFIG1_SCKDELAY_Pos); // number of 16 MHz periods (62.5 ns)
+
+    p_instance->ENABLE = 1;
+}
+
+void hal_qspi_master_tx_rx(NRF_QSPI_Type  * p_instance,
+                           uint16_t         transfer_size,
+                           const uint8_t  * tx_data,
+                           uint8_t        * rx_data)
+{
+	p_instance->READ.DST = (uint32_t)rx_data;
+	p_instance->READ.CNT = transfer_size;
+	p_instance->READ.SRC = (uint32_t)tx_data;
+	p_instance->READ.CNT = transfer_size;
+	p_instance->TASKS_ACTIVATE = 1;
+	while (p_instance->EVENTS_READY == 0) {
+		;
+	}
+
+	p_instance->TASKS_ACTIVATE = 0;
+}
+
+#endif // HAL_QSPIE_MODULE_ENABLED
diff --git a/ports/nrf/hal/hal_qspie.h b/ports/nrf/hal/hal_qspie.h
new file mode 100644
index 0000000000..c964ff4387
--- /dev/null
+++ b/ports/nrf/hal/hal_qspie.h
@@ -0,0 +1,110 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HAL_QSPIE_H__
+#define HAL_QSPIE_H__
+
+#ifdef HAL_QSPIE_MODULE_ENABLED
+
+#if NRF52840_XXAA
+
+#include <nrf.h>
+
+#else
+#error "Device not supported."
+#endif
+
+/**
+  * @brief  Quad SPI clock frequency type definition
+  */
+typedef enum {
+    HAL_FREQ_2_Mbps,
+    HAL_FREQ_4_Mbps,
+    HAL_FREQ_8_Mbps,
+    HAL_FREQ_16_Mbps,
+    HAL_FREQ_32_Mbps
+} hal_qspi_clk_freq_t;
+
+/**
+  * @brief  Quad SPI mode type definition
+  */
+typedef enum {
+    HAL_SPI_MODE_CPOL0_CPHA0 = 0, // CPOL = 0, CPHA = 0 (data on leading edge)
+    HAL_SPI_MODE_CPOL1_CPHA1 = 3  // CPOL = 1, CPHA = 1 (data on trailing edge)
+} hal_qspi_mode_t;
+
+/**
+  * @brief  Quad SPI data line configuration type definition
+  */
+typedef enum {
+    HAL_QSPI_DATA_LINE_SINGLE,
+    HAL_QSPI_DATA_LINE_DUAL,
+    HAL_QSPI_DATA_LINE_QUAD
+} hal_qspi_data_line_t;
+
+
+
+/**
+  * @brief  Quad SPI Configuration Structure definition
+  */
+typedef struct {
+    uint8_t d0_mosi_pin;
+    uint8_t d1_miso_pin;
+    uint8_t d2_pin;
+    uint8_t d3_pin;
+    uint8_t clk_pin;
+    uint8_t csn_pin;
+    uint8_t d0_mosi_pin_port;
+    uint8_t d1_miso_pin_port;
+    uint8_t d2_pin_port;
+    uint8_t d3_pin_port;
+    uint8_t clk_pin_port;
+    uint8_t csn_pin_port;
+    bool use_csn;
+    hal_qspi_mode_t mode;
+    hal_qspi_data_line_t data_line;
+    hal_qspi_clk_freq_t freq;
+} hal_qspi_init_t;
+
+/**
+  * @brief  Quad SPI handle Structure definition
+  */
+typedef struct __QSPI_HandleTypeDef
+{
+    NRF_QSPI_Type     *instance;    /* QSPI registers base address */
+    hal_qspi_init_t   init;         /* QSPI initialization parameters */
+} QSPI_HandleTypeDef;
+
+void hal_qspi_master_init(NRF_QSPI_Type * p_instance, hal_qspi_init_t const * p_qspi_init);
+
+void hal_qspi_master_tx_rx(NRF_QSPI_Type  * p_instance,
+                           uint16_t         transfer_size,
+                           const uint8_t  * tx_data,
+                           uint8_t        * rx_data);
+
+#endif // HAL_QSPIE_MODULE_ENABLED
+
+#endif // HAL_QSPIE_H__
diff --git a/ports/nrf/hal/hal_rng.c b/ports/nrf/hal/hal_rng.c
new file mode 100644
index 0000000000..39b6f57896
--- /dev/null
+++ b/ports/nrf/hal/hal_rng.c
@@ -0,0 +1,76 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "mphalport.h"
+#include "hal_rng.h"
+
+#ifdef HAL_RNG_MODULE_ENABLED
+
+#if BLUETOOTH_SD
+#include "py/nlr.h"
+#include "ble_drv.h"
+#include "nrf_soc.h"
+
+#define BLUETOOTH_STACK_ENABLED() (ble_drv_stack_enabled())
+
+#endif // BLUETOOTH_SD
+
+uint32_t hal_rng_generate(void) {
+
+    uint32_t retval = 0;
+
+#if BLUETOOTH_SD
+
+    if (BLUETOOTH_STACK_ENABLED() == 1) {
+        uint32_t status;
+        do {
+            status = sd_rand_application_vector_get((uint8_t *)&retval, 4); // Extract 4 bytes
+        } while (status != 0);
+    } else {
+#endif
+        uint8_t * p_retval = (uint8_t *)&retval;
+
+        NRF_RNG->EVENTS_VALRDY = 0;
+        NRF_RNG->TASKS_START   = 1;
+
+        for (uint16_t i = 0; i < 4; i++) {
+            while (NRF_RNG->EVENTS_VALRDY == 0) {
+                ;
+            }
+            NRF_RNG->EVENTS_VALRDY = 0;
+            p_retval[i] = NRF_RNG->VALUE;
+        }
+
+        NRF_RNG->TASKS_STOP = 1;
+#if BLUETOOTH_SD
+    }
+#endif
+
+    return retval;
+}
+
+#endif // HAL_RNG_MODULE_ENABLED
+
diff --git a/ports/nrf/hal/hal_rng.h b/ports/nrf/hal/hal_rng.h
new file mode 100644
index 0000000000..d09a26eb9e
--- /dev/null
+++ b/ports/nrf/hal/hal_rng.h
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HAL_RNG_H__
+#define HAL_RNG_H__
+
+#include "nrf.h"
+
+uint32_t hal_rng_generate(void);
+
+#endif // HAL_RNG_H__
diff --git a/ports/nrf/hal/hal_rtc.c b/ports/nrf/hal/hal_rtc.c
new file mode 100644
index 0000000000..ba968f90c0
--- /dev/null
+++ b/ports/nrf/hal/hal_rtc.c
@@ -0,0 +1,123 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "mphalport.h"
+#include "hal_rtc.h"
+#include "hal_irq.h"
+
+#ifdef HAL_RTC_MODULE_ENABLED
+
+#define HAL_LFCLK_FREQ (32768UL)
+#define HAL_RTC_FREQ (10UL)
+#define HAL_RTC_COUNTER_PRESCALER ((HAL_LFCLK_FREQ/HAL_RTC_FREQ)-1)
+
+static hal_rtc_app_callback m_callback;
+
+static uint32_t m_period[sizeof(RTC_BASE_POINTERS) / sizeof(uint32_t)];
+
+void hal_rtc_callback_set(hal_rtc_app_callback callback) {
+    m_callback = callback;
+}
+
+void hal_rtc_init(hal_rtc_conf_t const * p_rtc_conf) {
+    NRF_RTC_Type * p_rtc = RTC_BASE(p_rtc_conf->id);
+
+    // start LFCLK if not already started
+    if (NRF_CLOCK->LFCLKSTAT == 0) {
+        NRF_CLOCK->TASKS_LFCLKSTART = 1;
+        while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0);
+        NRF_CLOCK->EVENTS_LFCLKSTARTED = 0;
+    }
+
+    m_period[p_rtc_conf->id] = p_rtc_conf->period;
+
+    p_rtc->PRESCALER = HAL_RTC_COUNTER_PRESCALER;
+    hal_irq_priority(RTC_IRQ_NUM(p_rtc_conf->id), p_rtc_conf->irq_priority);
+}
+
+void hal_rtc_start(uint8_t id) {
+    NRF_RTC_Type * p_rtc = RTC_BASE(id);
+
+    uint32_t period  = HAL_RTC_FREQ * m_period[id];
+    uint32_t counter = p_rtc->COUNTER;
+
+    p_rtc->CC[0] = counter + period;
+
+    p_rtc->EVTENSET = RTC_EVTEN_COMPARE0_Msk;
+    p_rtc->INTENSET = RTC_INTENSET_COMPARE0_Msk;
+
+    hal_irq_clear(RTC_IRQ_NUM(id));
+    hal_irq_enable(RTC_IRQ_NUM(id));
+
+    p_rtc->TASKS_START = 1;
+}
+
+void hal_rtc_stop(uint8_t id) {
+    NRF_RTC_Type * p_rtc = RTC_BASE(id);
+
+    p_rtc->EVTENCLR = RTC_EVTEN_COMPARE0_Msk;
+    p_rtc->INTENCLR = RTC_INTENSET_COMPARE0_Msk;
+
+    hal_irq_disable(RTC_IRQ_NUM(id));
+
+    p_rtc->TASKS_STOP = 1;
+}
+
+static void common_irq_handler(uint8_t id) {
+    NRF_RTC_Type * p_rtc = RTC_BASE(id);
+
+    // clear all events
+    p_rtc->EVENTS_COMPARE[0] = 0;
+    p_rtc->EVENTS_COMPARE[1] = 0;
+    p_rtc->EVENTS_COMPARE[2] = 0;
+    p_rtc->EVENTS_COMPARE[3] = 0;
+    p_rtc->EVENTS_TICK       = 0;
+    p_rtc->EVENTS_OVRFLW     = 0;
+
+    m_callback(id);
+}
+
+void RTC0_IRQHandler(void)
+{
+    common_irq_handler(0);
+}
+
+void RTC1_IRQHandler(void)
+{
+    common_irq_handler(1);
+}
+
+#if NRF52
+
+void RTC2_IRQHandler(void)
+{
+    common_irq_handler(2);
+}
+
+#endif // NRF52
+
+#endif // HAL_RTC_MODULE_ENABLED
+
diff --git a/ports/nrf/hal/hal_rtc.h b/ports/nrf/hal/hal_rtc.h
new file mode 100644
index 0000000000..62bc028b05
--- /dev/null
+++ b/ports/nrf/hal/hal_rtc.h
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HAL_RTC_H__
+#define HAL_RTC_H__
+
+#include "nrf.h"
+
+#if NRF51
+  #define RTC_BASE_POINTERS (const uint32_t[]){NRF_RTC0_BASE, \
+                                               NRF_RTC1_BASE}
+  #define RTC_IRQ_VALUES (const uint32_t[]){RTC0_IRQn, \
+                                            RTC1_IRQn}
+#endif
+
+#if NRF52
+  #define RTC_BASE_POINTERS (const uint32_t[]){NRF_RTC0_BASE, \
+                                               NRF_RTC1_BASE, \
+                                               NRF_RTC2_BASE}
+  #define RTC_IRQ_VALUES (const uint32_t[]){RTC0_IRQn, \
+                                            RTC1_IRQn, \
+                                            RTC2_IRQn}
+#endif
+
+#define RTC_BASE(x) ((NRF_RTC_Type *)RTC_BASE_POINTERS[x])
+#define RTC_IRQ_NUM(x) (RTC_IRQ_VALUES[x])
+
+typedef void (*hal_rtc_app_callback)(uint8_t id);
+
+/**
+  * @brief  RTC Configuration Structure definition
+  */
+typedef struct {
+    uint8_t  id;           /* RTC instance id */
+    uint32_t period;       /* RTC period in ms */
+    uint32_t irq_priority; /* RTC IRQ priority */
+} hal_rtc_conf_t;
+
+void hal_rtc_callback_set(hal_rtc_app_callback callback);
+
+void hal_rtc_init(hal_rtc_conf_t const * p_rtc_config);
+
+void hal_rtc_start(uint8_t id);
+
+void hal_rtc_stop(uint8_t id);
+
+#endif // HAL_RTC_H__
diff --git a/ports/nrf/hal/hal_spi.c b/ports/nrf/hal/hal_spi.c
new file mode 100644
index 0000000000..2de203d237
--- /dev/null
+++ b/ports/nrf/hal/hal_spi.c
@@ -0,0 +1,127 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <stdint.h>
+#include <stdio.h>
+
+#include "mphalport.h"
+#include "hal_spi.h"
+
+#ifdef HAL_SPI_MODULE_ENABLED
+
+static const uint32_t hal_spi_frequency_lookup[] = {
+    SPI_FREQUENCY_FREQUENCY_K125, // 125 kbps
+    SPI_FREQUENCY_FREQUENCY_K250, // 250 kbps
+    SPI_FREQUENCY_FREQUENCY_K500, // 500 kbps
+    SPI_FREQUENCY_FREQUENCY_M1, // 1 Mbps
+    SPI_FREQUENCY_FREQUENCY_M2, // 2 Mbps
+    SPI_FREQUENCY_FREQUENCY_M4, // 4 Mbps
+    SPI_FREQUENCY_FREQUENCY_M8 // 8 Mbps
+};
+
+void hal_spi_master_init(NRF_SPI_Type * p_instance, hal_spi_init_t const * p_spi_init) {
+    hal_gpio_cfg_pin(p_spi_init->clk_pin->port, p_spi_init->clk_pin->pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED);
+    hal_gpio_cfg_pin(p_spi_init->mosi_pin->port, p_spi_init->mosi_pin->pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED);
+    hal_gpio_cfg_pin(p_spi_init->miso_pin->port, p_spi_init->miso_pin->pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED);
+
+#if NRF51
+    p_instance->PSELSCK  = p_spi_init->clk_pin->pin;
+    p_instance->PSELMOSI = p_spi_init->mosi_pin->pin;
+    p_instance->PSELMISO = p_spi_init->miso_pin->pin;
+#else
+    p_instance->PSEL.SCK  = p_spi_init->clk_pin->pin;
+    p_instance->PSEL.MOSI = p_spi_init->mosi_pin->pin;
+    p_instance->PSEL.MISO = p_spi_init->miso_pin->pin;
+
+#if NRF52840_XXAA
+    p_instance->PSEL.SCK  |= (p_spi_init->clk_pin->port << SPI_PSEL_SCK_PORT_Pos);
+    p_instance->PSEL.MOSI |= (p_spi_init->mosi_pin->port << SPI_PSEL_MOSI_PORT_Pos);
+    p_instance->PSEL.MISO |= (p_spi_init->miso_pin->port << SPI_PSEL_MISO_PORT_Pos);
+#endif
+
+#endif
+
+    p_instance->FREQUENCY = hal_spi_frequency_lookup[p_spi_init->freq];
+
+    uint32_t mode;
+    switch (p_spi_init->mode) {
+        case HAL_SPI_MODE_CPOL0_CPHA0:
+            mode = (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos);
+            break;
+        case HAL_SPI_MODE_CPOL0_CPHA1:
+            mode = (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos);
+            break;
+        case HAL_SPI_MODE_CPOL1_CPHA0:
+            mode = (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos);
+            break;
+        case HAL_SPI_MODE_CPOL1_CPHA1:
+            mode = (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos);
+            break;
+        default:
+            mode = 0;
+            break;
+    }
+
+    if (p_spi_init->firstbit == HAL_SPI_LSB_FIRST) {
+        p_instance->CONFIG = (mode | (SPI_CONFIG_ORDER_LsbFirst << SPI_CONFIG_ORDER_Pos));
+    } else {
+        p_instance->CONFIG = (mode | (SPI_CONFIG_ORDER_MsbFirst << SPI_CONFIG_ORDER_Pos));
+    }
+
+    p_instance->EVENTS_READY = 0U;
+    p_instance->ENABLE = (SPI_ENABLE_ENABLE_Enabled << SPI_ENABLE_ENABLE_Pos);
+}
+
+void hal_spi_master_tx_rx(NRF_SPI_Type  * p_instance,
+                          uint16_t        transfer_size,
+                          const uint8_t * tx_data,
+                          uint8_t       * rx_data) {
+
+    uint16_t number_of_txd_bytes = 0;
+
+    p_instance->EVENTS_READY = 0;
+
+    while (number_of_txd_bytes < transfer_size) {
+        p_instance->TXD = (uint32_t)(tx_data[number_of_txd_bytes]);
+
+        // wait for the transaction complete or timeout (about 10ms - 20 ms)
+        while (p_instance->EVENTS_READY == 0) {
+            ;
+        }
+
+        p_instance->EVENTS_READY = 0;
+
+        uint8_t in_byte = (uint8_t)p_instance->RXD;
+
+        if (rx_data != NULL) {
+            rx_data[number_of_txd_bytes] = in_byte;
+        }
+
+        number_of_txd_bytes++;
+    };
+}
+
+#endif // HAL_SPI_MODULE_ENABLED
diff --git a/ports/nrf/hal/hal_spi.h b/ports/nrf/hal/hal_spi.h
new file mode 100644
index 0000000000..cb01284689
--- /dev/null
+++ b/ports/nrf/hal/hal_spi.h
@@ -0,0 +1,127 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HAL_SPI_H__
+#define HAL_SPI_H__
+
+#include <stdbool.h>
+#include "nrf.h"
+
+#if NRF51
+  #define SPI_BASE_POINTERS (const uint32_t[]){NRF_SPI0_BASE, NRF_SPI1_BASE}
+  #define SPI_IRQ_VALUES (const uint32_t[]){SPI0_TWI0_IRQn, SPI1_TWI1_IRQn}
+#endif
+
+#if NRF52
+  #ifdef NRF52832_XXAA
+    #define SPI_BASE_POINTERS (const uint32_t[]){NRF_SPI0_BASE, \
+                                                 NRF_SPI1_BASE, \
+                                                 NRF_SPI2_BASE}
+    #define SPI_IRQ_VALUES (const uint32_t[]){SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn, \
+                                              SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn, \
+                                              SPIM2_SPIS2_SPI2_IRQn}
+  #endif
+
+  #ifdef NRF52840_XXAA
+    #define SPI_BASE_POINTERS (const uint32_t[]){NRF_SPI0_BASE, \
+                                                 NRF_SPI1_BASE, \
+                                                 NRF_SPI2_BASE, \
+                                                 NRF_SPIM3_BASE}
+    #define SPI_IRQ_VALUES (const uint32_t[]){SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn, \
+                                              SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn, \
+                                              SPIM2_SPIS2_SPI2_IRQn, \
+                                              SPIM3_IRQn}
+  #endif
+#endif
+
+#define SPI_BASE(x) ((NRF_SPI_Type *)SPI_BASE_POINTERS[x])
+#define SPI_IRQ_NUM(x) (SPI_IRQ_VALUES[x])
+
+/**
+  * @brief  SPI clock frequency type definition
+  */
+typedef enum {
+    HAL_SPI_FREQ_125_Kbps = 0,
+    HAL_SPI_FREQ_250_Kbps,
+    HAL_SPI_FREQ_500_Kbps,
+    HAL_SPI_FREQ_1_Mbps,
+    HAL_SPI_FREQ_2_Mbps,
+    HAL_SPI_FREQ_4_Mbps,
+    HAL_SPI_FREQ_8_Mbps,
+#if NRF52840_XXAA
+    HAL_SPI_FREQ_16_Mbps,
+    HAL_SPI_FREQ_32_Mbps
+#endif
+} hal_spi_clk_freq_t;
+
+/**
+  * @brief  SPI mode type definition
+  */
+typedef enum {
+    HAL_SPI_MODE_CPOL0_CPHA0 = 0, // CPOL = 0, CPHA = 0 (data on leading edge)
+    HAL_SPI_MODE_CPOL0_CPHA1,     // CPOL = 0, CPHA = 1 (data on trailing edge)
+    HAL_SPI_MODE_CPOL1_CPHA0,     // CPOL = 1, CPHA = 0 (data on leading edge)
+    HAL_SPI_MODE_CPOL1_CPHA1      // CPOL = 1, CPHA = 1 (data on trailing edge)
+} hal_spi_mode_t;
+
+/**
+ * @brief  SPI firstbit mode definition
+ */
+typedef enum {
+    HAL_SPI_MSB_FIRST = 0,
+    HAL_SPI_LSB_FIRST
+} hal_spi_firstbit_t;
+
+/**
+  * @brief  SPI Configuration Structure definition
+  */
+typedef struct {
+    const pin_obj_t * mosi_pin;
+    const pin_obj_t * miso_pin;
+    const pin_obj_t * clk_pin;
+    hal_spi_firstbit_t firstbit;
+    hal_spi_mode_t mode;
+    uint32_t irq_priority;
+    hal_spi_clk_freq_t freq;
+} hal_spi_init_t;
+
+/**
+  * @brief  SPI handle Structure definition
+  */
+typedef struct __SPI_HandleTypeDef
+{
+    NRF_SPI_Type      *instance;    /* SPI registers base address */
+    hal_spi_init_t    init;         /* SPI initialization parameters */
+} SPI_HandleTypeDef;
+
+void hal_spi_master_init(NRF_SPI_Type * p_instance, hal_spi_init_t const * p_spi_init);
+
+void hal_spi_master_tx_rx(NRF_SPI_Type  * p_instance,
+                          uint16_t        transfer_size,
+                          const uint8_t * tx_data,
+                          uint8_t       * rx_data);
+
+#endif // HAL_SPI_H__
diff --git a/ports/nrf/hal/hal_spie.c b/ports/nrf/hal/hal_spie.c
new file mode 100644
index 0000000000..e2639e4560
--- /dev/null
+++ b/ports/nrf/hal/hal_spie.c
@@ -0,0 +1,123 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <stdint.h>
+#include <stdio.h>
+
+#include "mphalport.h"
+#include "hal_spi.h"
+
+#ifdef HAL_SPIE_MODULE_ENABLED
+
+static const uint32_t hal_spi_frequency_lookup[] = {
+    SPIM_FREQUENCY_FREQUENCY_K125, // 125 kbps
+    SPIM_FREQUENCY_FREQUENCY_K250, // 250 kbps
+    SPIM_FREQUENCY_FREQUENCY_K500, // 500 kbps
+    SPIM_FREQUENCY_FREQUENCY_M1, // 1 Mbps
+    SPIM_FREQUENCY_FREQUENCY_M2, // 2 Mbps
+    SPIM_FREQUENCY_FREQUENCY_M4, // 4 Mbps
+    SPIM_FREQUENCY_FREQUENCY_M8, // 8 Mbps
+#if NRF52840_XXAA
+    SPIM_FREQUENCY_FREQUENCY_M16, // 16 Mbps
+    SPIM_FREQUENCY_FREQUENCY_M32, // 32 Mbps
+#endif
+};
+
+void hal_spi_master_init(NRF_SPI_Type * p_instance, hal_spi_init_t const * p_spi_init) {
+    // cast to master type
+    NRF_SPIM_Type * spim_instance = (NRF_SPIM_Type *)p_instance;
+
+    hal_gpio_cfg_pin(p_spi_init->clk_pin->port, p_spi_init->clk_pin->pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED);
+    hal_gpio_cfg_pin(p_spi_init->mosi_pin->port, p_spi_init->mosi_pin->pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED);
+    hal_gpio_cfg_pin(p_spi_init->miso_pin->port, p_spi_init->miso_pin->pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED);
+
+    spim_instance->PSEL.SCK  = p_spi_init->clk_pin->pin;
+    spim_instance->PSEL.MOSI = p_spi_init->mosi_pin->pin;
+    spim_instance->PSEL.MISO = p_spi_init->miso_pin->pin;
+
+#if NRF52840_XXAA
+    spim_instance->PSEL.SCK  |= (p_spi_init->clk_pin->port << SPIM_PSEL_SCK_PORT_Pos);
+    spim_instance->PSEL.MOSI |= (p_spi_init->mosi_pin->port << SPIM_PSEL_MOSI_PORT_Pos);
+    spim_instance->PSEL.MISO |= (p_spi_init->miso_pin->port << SPIM_PSEL_MISO_PORT_Pos);
+#endif
+
+    spim_instance->FREQUENCY = hal_spi_frequency_lookup[p_spi_init->freq];
+
+    uint32_t mode;
+    switch (p_spi_init->mode) {
+        case HAL_SPI_MODE_CPOL0_CPHA0:
+            mode = (SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos) | (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos);
+            break;
+        case HAL_SPI_MODE_CPOL0_CPHA1:
+            mode = (SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos) | (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos);
+            break;
+        case HAL_SPI_MODE_CPOL1_CPHA0:
+            mode = (SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos) | (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos);
+            break;
+        case HAL_SPI_MODE_CPOL1_CPHA1:
+            mode = (SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos) | (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos);
+            break;
+        default:
+            mode = 0;
+            break;
+    }
+
+    if (p_spi_init->firstbit == HAL_SPI_LSB_FIRST) {
+    	spim_instance->CONFIG = (mode | (SPIM_CONFIG_ORDER_LsbFirst << SPIM_CONFIG_ORDER_Pos));
+    } else {
+    	spim_instance->CONFIG = (mode | (SPIM_CONFIG_ORDER_MsbFirst << SPIM_CONFIG_ORDER_Pos));
+    }
+
+    spim_instance->EVENTS_END = 0;
+    spim_instance->ENABLE = (SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos);
+}
+
+void hal_spi_master_tx_rx(NRF_SPI_Type * p_instance, uint16_t transfer_size, const uint8_t * tx_data, uint8_t * rx_data) {
+
+    // cast to master type
+    NRF_SPIM_Type * spim_instance = (NRF_SPIM_Type *)p_instance;
+
+    if (tx_data != NULL) {
+        spim_instance->TXD.PTR = (uint32_t)(tx_data);
+        spim_instance->TXD.MAXCNT = transfer_size;
+    }
+
+    if (rx_data != NULL) {
+        spim_instance->RXD.PTR = (uint32_t)(rx_data);
+        spim_instance->RXD.MAXCNT = transfer_size;
+    }
+
+    spim_instance->TASKS_START = 1;
+
+    while(spim_instance->EVENTS_END != 1) {
+        ;
+    }
+
+    spim_instance->EVENTS_END = 0;
+    spim_instance->TASKS_STOP  = 1;
+}
+
+#endif // HAL_SPIE_MODULE_ENABLED
diff --git a/ports/nrf/hal/hal_temp.c b/ports/nrf/hal/hal_temp.c
new file mode 100644
index 0000000000..c88814dd1b
--- /dev/null
+++ b/ports/nrf/hal/hal_temp.c
@@ -0,0 +1,76 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Bander F. Ajba
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <stdio.h>
+#include <stdint.h>
+#include "mphalport.h"
+#include "hal_temp.h"
+
+#if BLUETOOTH_SD
+#include "py/nlr.h"
+#include "ble_drv.h"
+#include "nrf_soc.h"
+#define BLUETOOTH_STACK_ENABLED() (ble_drv_stack_enabled())
+#endif // BLUETOOTH_SD
+
+#ifdef HAL_TEMP_MODULE_ENABLED
+
+void hal_temp_init(void) {
+    // @note Workaround for PAN_028 rev2.0A anomaly 31 - TEMP: Temperature offset value has to be manually loaded to the TEMP module
+    *(uint32_t *) 0x4000C504 = 0;
+}
+
+
+
+int32_t hal_temp_read(void) {
+#if BLUETOOTH_SD
+    if (BLUETOOTH_STACK_ENABLED() == 1) {
+        int32_t temp;
+        (void)sd_temp_get(&temp);
+        return temp / 4; // resolution of 0.25 degree celsius
+    }
+#endif // BLUETOOTH_SD
+
+    int32_t volatile temp;
+    hal_temp_init();
+
+    NRF_TEMP->TASKS_START = 1; // Start the temperature measurement.
+
+    while (NRF_TEMP->EVENTS_DATARDY == 0) {
+        // Do nothing.
+    }
+
+    NRF_TEMP->EVENTS_DATARDY = 0;
+
+    // @note Workaround for PAN_028 rev2.0A anomaly 29 - TEMP: Stop task clears the TEMP register. 
+    temp = (((NRF_TEMP->TEMP & MASK_SIGN) != 0) ? (NRF_TEMP->TEMP | MASK_SIGN_EXTENSION) : (NRF_TEMP->TEMP) / 4);
+
+    // @note Workaround for PAN_028 rev2.0A anomaly 30 - TEMP: Temp module analog front end does not power down when DATARDY event occurs.
+    NRF_TEMP->TASKS_STOP = 1; // Stop the temperature measurement. 
+    return temp;
+}
+
+#endif // HAL_TEMP_MODULE_ENABLED
diff --git a/ports/nrf/hal/hal_temp.h b/ports/nrf/hal/hal_temp.h
new file mode 100644
index 0000000000..b203c944dd
--- /dev/null
+++ b/ports/nrf/hal/hal_temp.h
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Bander F. Ajba
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HAL_TEMP_H__
+#define HAL_TEMP_H__
+
+#include "nrf.h"
+
+#define MASK_SIGN           (0x00000200UL)
+#define MASK_SIGN_EXTENSION (0xFFFFFC00UL)
+
+void hal_temp_init(void);
+
+int32_t hal_temp_read(void);
+
+#endif
\ No newline at end of file
diff --git a/ports/nrf/hal/hal_time.c b/ports/nrf/hal/hal_time.c
new file mode 100644
index 0000000000..706bd3a175
--- /dev/null
+++ b/ports/nrf/hal/hal_time.c
@@ -0,0 +1,116 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "mphalport.h"
+#include "hal_time.h"
+
+#ifdef HAL_TIME_MODULE_ENABLED
+
+void mp_hal_delay_us(mp_uint_t us)
+{
+    register uint32_t delay __ASM ("r0") = us;
+    __ASM volatile (
+#ifdef NRF51
+            ".syntax unified\n"
+#endif
+        "1:\n"
+        " SUBS %0, %0, #1\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+#ifdef NRF52
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+        " NOP\n"
+#endif
+        " BNE 1b\n"
+#ifdef NRF51
+        ".syntax divided\n"
+#endif
+        : "+r" (delay));
+}
+
+void mp_hal_delay_ms(mp_uint_t ms)
+{
+    for (mp_uint_t i = 0; i < ms; i++)
+    {
+        mp_hal_delay_us(999);
+    }
+}
+
+#endif // HAL_TIME_MODULE_ENABLED
diff --git a/ports/nrf/hal/hal_time.h b/ports/nrf/hal/hal_time.h
new file mode 100644
index 0000000000..20393f918b
--- /dev/null
+++ b/ports/nrf/hal/hal_time.h
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HAL_TIME_H__
+#define HAL_TIME_H__
+
+void mp_hal_delay_ms(mp_uint_t ms);
+
+void mp_hal_delay_us(mp_uint_t us);
+
+#endif // HAL_TIME_H__
diff --git a/ports/nrf/hal/hal_timer.c b/ports/nrf/hal/hal_timer.c
new file mode 100644
index 0000000000..458353c8ca
--- /dev/null
+++ b/ports/nrf/hal/hal_timer.c
@@ -0,0 +1,103 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "mphalport.h"
+#include "hal_timer.h"
+#include "hal_irq.h"
+
+#ifdef HAL_TIMER_MODULE_ENABLED
+
+static hal_timer_app_callback m_callback;
+
+void hal_timer_callback_set(hal_timer_app_callback callback) {
+    m_callback = callback;
+}
+
+void hal_timer_init(hal_timer_conf_t const * p_timer_conf) {
+    NRF_TIMER_Type * p_timer = TIMER_BASE(p_timer_conf->id);
+
+    p_timer->CC[0]       = 1000 * p_timer_conf->period;
+    p_timer->MODE        = TIMER_MODE_MODE_Timer;
+    p_timer->BITMODE     = TIMER_BITMODE_BITMODE_24Bit << TIMER_BITMODE_BITMODE_Pos;
+    p_timer->PRESCALER   = 4; // 1 us
+    p_timer->INTENSET    = TIMER_INTENSET_COMPARE0_Msk;
+    p_timer->SHORTS      = (TIMER_SHORTS_COMPARE0_CLEAR_Enabled << TIMER_SHORTS_COMPARE0_CLEAR_Pos);
+    p_timer->TASKS_CLEAR = 1;
+
+    hal_irq_priority(TIMER_IRQ_NUM(p_timer_conf->id), p_timer_conf->irq_priority);
+}
+
+void hal_timer_start(uint8_t id) {
+    NRF_TIMER_Type * p_timer = TIMER_BASE(id);
+
+    p_timer->TASKS_CLEAR = 1;
+    hal_irq_enable(TIMER_IRQ_NUM(id));
+    p_timer->TASKS_START = 1;
+}
+
+void hal_timer_stop(uint8_t id) {
+    NRF_TIMER_Type * p_timer = TIMER_BASE(id);
+
+    hal_irq_disable(TIMER_IRQ_NUM(id));
+    p_timer->TASKS_STOP = 1;
+}
+
+static void common_irq_handler(uint8_t id) {
+    NRF_TIMER_Type * p_timer = TIMER_BASE(id);
+
+    if (p_timer->EVENTS_COMPARE[0]) {
+        p_timer->EVENTS_COMPARE[0] = 0;
+            m_callback(id);
+    }
+}
+
+void TIMER0_IRQHandler(void) {
+    common_irq_handler(0);
+}
+
+#if (MICROPY_PY_MACHINE_SOFT_PWM != 1)
+void TIMER1_IRQHandler(void) {
+    common_irq_handler(1);
+}
+#endif
+
+void TIMER2_IRQHandler(void) {
+    common_irq_handler(2);
+}
+
+#if NRF52
+
+void TIMER3_IRQHandler(void) {
+    common_irq_handler(3);
+}
+
+void TIMER4_IRQHandler(void) {
+    common_irq_handler(4);
+}
+
+#endif
+
+#endif // HAL_TIMER_MODULE_ENABLED
diff --git a/ports/nrf/hal/hal_timer.h b/ports/nrf/hal/hal_timer.h
new file mode 100644
index 0000000000..7d109c6d11
--- /dev/null
+++ b/ports/nrf/hal/hal_timer.h
@@ -0,0 +1,76 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HAL_TIMER_H__
+#define HAL_TIMER_H__
+
+#include "nrf.h"
+
+#if NRF51
+  #define TIMER_BASE_POINTERS (const uint32_t[]){NRF_TIMER0_BASE, \
+                                                 NRF_TIMER1_BASE, \
+                                                 NRF_TIMER2_BASE}
+  #define TIMER_IRQ_VALUES (const uint32_t[]){TIMER0_IRQn, \
+                                              TIMER1_IRQn, \
+                                              TIMER2_IRQn}
+#endif
+
+#if NRF52
+  #define TIMER_BASE_POINTERS (const uint32_t[]){NRF_TIMER0_BASE, \
+                                                 NRF_TIMER1_BASE, \
+                                                 NRF_TIMER1_BASE, \
+                                                 NRF_TIMER1_BASE, \
+                                                 NRF_TIMER2_BASE}
+  #define TIMER_IRQ_VALUES (const uint32_t[]){TIMER0_IRQn, \
+                                              TIMER1_IRQn, \
+                                              TIMER2_IRQn, \
+                                              TIMER3_IRQn, \
+                                              TIMER4_IRQn}
+#endif
+
+#define TIMER_BASE(x) ((NRF_TIMER_Type *)TIMER_BASE_POINTERS[x])
+#define TIMER_IRQ_NUM(x) (TIMER_IRQ_VALUES[x])
+
+typedef void (*hal_timer_app_callback)(uint8_t id);
+
+/**
+  * @brief  Timer Configuration Structure definition
+  */
+typedef struct {
+    uint8_t  id;
+    uint32_t period;
+    uint8_t  irq_priority;
+} hal_timer_conf_t;
+
+void hal_timer_callback_set(hal_timer_app_callback callback);
+
+void hal_timer_init(hal_timer_conf_t const * p_timer_config);
+
+void hal_timer_start(uint8_t id);
+
+void hal_timer_stop(uint8_t id);
+
+#endif // HAL_TIMER_H__
diff --git a/ports/nrf/hal/hal_twi.c b/ports/nrf/hal/hal_twi.c
new file mode 100644
index 0000000000..65d729c94b
--- /dev/null
+++ b/ports/nrf/hal/hal_twi.c
@@ -0,0 +1,133 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "mphalport.h"
+#include "hal_twi.h"
+
+#ifdef HAL_TWI_MODULE_ENABLED
+
+static const uint32_t hal_twi_frequency_lookup[] = {
+    TWI_FREQUENCY_FREQUENCY_K100, // 100 kbps
+    TWI_FREQUENCY_FREQUENCY_K250, // 250 kbps
+    TWI_FREQUENCY_FREQUENCY_K400, // 400 kbps
+};
+
+void hal_twi_master_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi_init) {
+
+#if NRF52840_XXAA
+    p_instance->PSEL.SCL  = p_twi_init->scl_pin->pin;
+    p_instance->PSEL.SDA  = p_twi_init->sda_pin->pin;
+    p_instance->PSEL.SCL |= (p_twi_init->scl_pin->port << TWI_PSEL_SCL_PORT_Pos);
+    p_instance->PSEL.SDA |= (p_twi_init->sda_pin->port << TWI_PSEL_SDA_PORT_Pos);
+#else
+    p_instance->PSELSCL  = p_twi_init->scl_pin->pin;
+    p_instance->PSELSDA  = p_twi_init->sda_pin->pin;
+#endif
+
+    p_instance->FREQUENCY = hal_twi_frequency_lookup[p_twi_init->freq];
+    p_instance->ENABLE    = (TWI_ENABLE_ENABLE_Enabled << TWI_ENABLE_ENABLE_Pos);
+}
+#include <stdio.h>
+void hal_twi_master_tx(NRF_TWI_Type  * p_instance,
+                       uint8_t         addr,
+                       uint16_t        transfer_size,
+                       const uint8_t * tx_data,
+                       bool            stop) {
+
+    uint16_t number_of_txd_bytes = 0;
+
+    p_instance->ADDRESS = addr;
+
+    p_instance->EVENTS_TXDSENT = 0;
+
+    p_instance->TXD            = tx_data[number_of_txd_bytes];
+    p_instance->TASKS_STARTTX  = 1;
+
+    while (number_of_txd_bytes < transfer_size) {
+        // wait for the transaction complete
+        while (p_instance->EVENTS_TXDSENT == 0) {
+            ;
+        }
+
+        number_of_txd_bytes++;
+
+        // TODO: This could go one byte out of bound.
+        p_instance->TXD            = tx_data[number_of_txd_bytes];
+        p_instance->EVENTS_TXDSENT = 0;
+    }
+
+
+    if (stop) {
+        p_instance->EVENTS_STOPPED   = 0;
+        p_instance->TASKS_STOP       = 1;
+
+        while (p_instance->EVENTS_STOPPED == 0) {
+            ;
+        }
+    }
+}
+
+void hal_twi_master_rx(NRF_TWI_Type  * p_instance,
+                       uint8_t         addr,
+                       uint16_t        transfer_size,
+                       uint8_t       * rx_data,
+                       bool            stop) {
+
+    uint16_t number_of_rxd_bytes = 0;
+
+    p_instance->ADDRESS = addr;
+
+    p_instance->EVENTS_RXDREADY = 0;
+
+    p_instance->TASKS_STARTRX  = 1;
+
+    while (number_of_rxd_bytes < transfer_size) {
+        // wait for the transaction complete
+        while (p_instance->EVENTS_RXDREADY == 0) {
+            ;
+        }
+
+        rx_data[number_of_rxd_bytes] = p_instance->RXD;
+        p_instance->EVENTS_RXDREADY = 0;
+
+        number_of_rxd_bytes++;
+    }
+
+    if (stop) {
+        p_instance->EVENTS_STOPPED   = 0;
+        p_instance->TASKS_STOP       = 1;
+
+        while (p_instance->EVENTS_STOPPED == 0) {
+            ;
+        }
+    }
+}
+
+void hal_twi_slave_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi_init) {
+}
+
+#endif // HAL_TWI_MODULE_ENABLED
+
diff --git a/ports/nrf/hal/hal_twi.h b/ports/nrf/hal/hal_twi.h
new file mode 100644
index 0000000000..834c512a08
--- /dev/null
+++ b/ports/nrf/hal/hal_twi.h
@@ -0,0 +1,118 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HAL_TWI_H__
+#define HAL_TWI_H__
+
+#include <stdbool.h>
+#include "nrf.h"
+
+#define TWI_BASE_POINTERS (const uint32_t[]){NRF_TWI0_BASE, NRF_TWI1_BASE}
+#define TWI_BASE(x) ((NRF_TWI_Type *)TWI_BASE_POINTERS[x])
+
+#if NRF51
+
+#define TWI_IRQ_VALUES (const uint32_t[]){SPI0_TWI0_IRQn, SPI1_TWI1_IRQn}
+
+#elif NRF52
+
+#define TWI_IRQ_VALUES (const uint32_t[]){SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn, \
+                                          SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn}
+
+#endif
+
+#if NRF52
+
+/**
+  * @brief  TWIM Configuration Structure definition
+  */
+typedef struct {
+} hal_twim_init_t;
+
+/**
+  * @brief  TWIS Configuration Structure definition
+  */
+typedef struct {
+} hal_twis_init_t;
+
+#endif
+
+/**
+  * @brief  TWI clock frequency type definition
+  */
+typedef enum {
+    HAL_TWI_FREQ_100_Kbps = 0,
+    HAL_TWI_FREQ_250_Kbps,
+    HAL_TWI_FREQ_400_Kbps
+} hal_twi_clk_freq_t;
+
+/**
+  * @brief  TWI role type definition
+  */
+typedef enum {
+    HAL_TWI_MASTER,
+    HAL_TWI_SLAVE
+} hal_twi_role_t;
+
+/**
+  * @brief  TWI Configuration Structure definition
+  */
+typedef struct {
+    uint8_t             id;           /* TWI instance id */
+    const pin_obj_t *   scl_pin;      /* TWI SCL pin */
+    const pin_obj_t *   sda_pin;      /* TWI SDA pin */
+    hal_twi_role_t      role;         /* TWI master/slave */
+    hal_twi_clk_freq_t  freq;         /* TWI frequency */
+} hal_twi_init_t;
+
+/**
+  * @brief  TWI handle Structure definition
+  */
+typedef struct __TWI_HandleTypeDef
+{
+    NRF_TWI_Type        *instance;    /* TWI register base address */
+    hal_twi_init_t      init;         /* TWI initialization parameters */
+} TWI_HandleTypeDef;
+
+void hal_twi_master_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi_init);
+
+void hal_twi_master_tx(NRF_TWI_Type  * p_instance,
+                       uint8_t         addr,
+                       uint16_t        transfer_size,
+                       const uint8_t * tx_data,
+                       bool            stop);
+
+void hal_twi_master_rx(NRF_TWI_Type  * p_instance,
+                       uint8_t         addr,
+                       uint16_t        transfer_size,
+                       uint8_t       * rx_data,
+                       bool            stop);
+
+
+void hal_twi_slave_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi_init);
+
+
+#endif // HAL_TWI_H__
diff --git a/ports/nrf/hal/hal_twie.c b/ports/nrf/hal/hal_twie.c
new file mode 100644
index 0000000000..cfa930f1d9
--- /dev/null
+++ b/ports/nrf/hal/hal_twie.c
@@ -0,0 +1,115 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "mphalport.h"
+#include "hal_twi.h"
+
+#ifdef HAL_TWIE_MODULE_ENABLED
+
+// EasyDMA variants
+#define TWI_MASTER_BASE(x) ((NRF_TWIM_Type *)TWI_BASE_POINTERS[x])
+#define TWI_SLAVE_BASE(x) ((NRF_TWIS_Type *)TWI_BASE_POINTERS[x])
+
+static const uint32_t hal_twi_frequency_lookup[] = {
+    TWIM_FREQUENCY_FREQUENCY_K100, // 100 kbps
+    TWIM_FREQUENCY_FREQUENCY_K250, // 250 kbps
+    TWIM_FREQUENCY_FREQUENCY_K400, // 400 kbps
+};
+
+void hal_twi_master_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi_init) {
+    // cast to master type
+    NRF_TWIM_Type * twim_instance = (NRF_TWIM_Type *)p_instance;
+
+    twim_instance->PSEL.SCL  = p_twi_init->scl_pin->pin;
+    twim_instance->PSEL.SDA  = p_twi_init->sda_pin->pin;
+
+#if NRF52840_XXAA
+    twim_instance->PSEL.SCL |= (p_twi_init->scl_pin->port << TWIM_PSEL_SCL_PORT_Pos);
+    twim_instance->PSEL.SDA |= (p_twi_init->sda_pin->port << TWIM_PSEL_SDA_PORT_Pos);
+#endif
+    twim_instance->FREQUENCY = hal_twi_frequency_lookup[p_twi_init->freq];
+    twim_instance->ENABLE    = (TWIM_ENABLE_ENABLE_Enabled << TWIM_ENABLE_ENABLE_Pos);
+}
+
+#include <stdio.h>
+
+void hal_twi_master_tx(NRF_TWI_Type  * p_instance,
+                       uint8_t         addr,
+                       uint16_t        transfer_size,
+                       const uint8_t * tx_data,
+                       bool            stop) {
+    // cast to master type
+    NRF_TWIM_Type * twim_instance = (NRF_TWIM_Type *)p_instance;
+
+    twim_instance->ADDRESS = addr;
+
+    printf("Hal I2C transfer size: %u, addr: %x, stop: %u\n", transfer_size, addr, stop);
+    twim_instance->TXD.MAXCNT     = transfer_size;
+    twim_instance->TXD.PTR        = (uint32_t)tx_data;
+
+    if (stop) {
+        twim_instance->SHORTS = TWIM_SHORTS_LASTTX_STOP_Msk;
+    } else {
+        twim_instance->SHORTS = TWIM_SHORTS_LASTTX_SUSPEND_Msk;
+    }
+
+    if (twim_instance->EVENTS_SUSPENDED == 1) {
+        printf("Resuming\n");
+        twim_instance->EVENTS_SUSPENDED = 0;
+        twim_instance->EVENTS_STOPPED   = 0;
+        twim_instance->TASKS_RESUME     = 1; // in case of resume
+    } else {
+        printf("Starting\n");
+        twim_instance->EVENTS_SUSPENDED = 0;
+        twim_instance->EVENTS_STOPPED   = 0;
+        twim_instance->TASKS_STARTTX    = 1;
+    }
+
+    printf("Going into loop\n");
+    while (twim_instance->EVENTS_STOPPED == 0 && twim_instance->EVENTS_SUSPENDED == 0) {
+        ;
+    }
+}
+
+void hal_twi_master_rx(NRF_TWI_Type  * p_instance,
+                       uint8_t         addr,
+                       uint16_t        transfer_size,
+                       const uint8_t * rx_data) {
+    // cast to master type
+    NRF_TWIM_Type * twim_instance = (NRF_TWIM_Type *)p_instance;
+
+    twim_instance->ADDRESS = addr;
+
+}
+
+void hal_twi_slave_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi_init) {
+    // cast to slave type
+    NRF_TWIS_Type * twis_instance = (NRF_TWIS_Type *)p_instance;
+    (void)twis_instance;
+}
+
+#endif // HAL_TWIE_MODULE_ENABLED
+
diff --git a/ports/nrf/hal/hal_uart.c b/ports/nrf/hal/hal_uart.c
new file mode 100644
index 0000000000..39590272b5
--- /dev/null
+++ b/ports/nrf/hal/hal_uart.c
@@ -0,0 +1,146 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <stdint.h>
+#include <stdio.h>
+
+#include "nrf.h"
+#include "mphalport.h"
+#include "hal_uart.h"
+
+#ifdef HAL_UART_MODULE_ENABLED
+
+uint32_t hal_uart_baudrate_lookup[] = {
+    UART_BAUDRATE_BAUDRATE_Baud1200,   ///< 1200 baud.
+    UART_BAUDRATE_BAUDRATE_Baud2400,   ///< 2400 baud.
+    UART_BAUDRATE_BAUDRATE_Baud4800,   ///< 4800 baud.
+    UART_BAUDRATE_BAUDRATE_Baud9600,   ///< 9600 baud.
+    UART_BAUDRATE_BAUDRATE_Baud14400,  ///< 14400 baud.
+    UART_BAUDRATE_BAUDRATE_Baud19200,  ///< 19200 baud.
+    UART_BAUDRATE_BAUDRATE_Baud28800,  ///< 28800 baud.
+    UART_BAUDRATE_BAUDRATE_Baud38400,  ///< 38400 baud.
+    UART_BAUDRATE_BAUDRATE_Baud57600,  ///< 57600 baud.
+    UART_BAUDRATE_BAUDRATE_Baud76800,  ///< 76800 baud.
+    UART_BAUDRATE_BAUDRATE_Baud115200, ///< 115200 baud.
+    UART_BAUDRATE_BAUDRATE_Baud230400, ///< 230400 baud.
+    UART_BAUDRATE_BAUDRATE_Baud250000, ///< 250000 baud.
+    UART_BAUDRATE_BAUDRATE_Baud460800, ///< 460800 baud.
+    UART_BAUDRATE_BAUDRATE_Baud921600, ///< 921600 baud.
+    UART_BAUDRATE_BAUDRATE_Baud1M,     ///< 1000000 baud.
+};
+
+hal_uart_error_t hal_uart_char_write(NRF_UART_Type * p_instance, uint8_t ch) {
+    p_instance->ERRORSRC = 0;
+    p_instance->TXD   = (uint8_t)ch;
+    while (p_instance->EVENTS_TXDRDY != 1) {
+        // Blocking wait.
+    }
+
+    // Clear the TX flag.
+    p_instance->EVENTS_TXDRDY = 0;
+
+    return p_instance->ERRORSRC;
+}
+
+hal_uart_error_t hal_uart_char_read(NRF_UART_Type * p_instance, uint8_t * ch) {
+    p_instance->ERRORSRC = 0;
+    while (p_instance->EVENTS_RXDRDY != 1) {
+        // Wait for RXD data.
+    }
+
+    p_instance->EVENTS_RXDRDY = 0;
+    *ch = p_instance->RXD;
+
+    return p_instance->ERRORSRC;
+}
+
+hal_uart_error_t hal_uart_buffer_write(NRF_UART_Type * p_instance, uint8_t * p_buffer, uint32_t num_of_bytes, uart_complete_cb cb) {
+    int i = 0;
+    hal_uart_error_t err = 0;
+    uint8_t ch = p_buffer[i++];
+    while (i < num_of_bytes) {
+        err = hal_uart_char_write(p_instance, ch);
+        if (err) {
+            return err;
+        }
+        ch = p_buffer[i++];
+    }
+    cb();
+    return err;
+}
+
+hal_uart_error_t hal_uart_buffer_read(NRF_UART_Type * p_instance, uint8_t * p_buffer, uint32_t num_of_bytes, uart_complete_cb cb) {
+    int i = 0;
+    hal_uart_error_t err = 0;
+    while (i < num_of_bytes) {
+        hal_uart_error_t err = hal_uart_char_read(p_instance, &p_buffer[i]);
+        if (err) {
+            return err;
+        }
+        i++;
+    }
+    cb();
+    return err;
+}
+
+void hal_uart_init(NRF_UART_Type * p_instance, hal_uart_init_t const * p_uart_init) {
+    hal_gpio_cfg_pin(p_uart_init->tx_pin->port, p_uart_init->tx_pin->pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED);
+    hal_gpio_cfg_pin(p_uart_init->tx_pin->port, p_uart_init->rx_pin->pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED);
+
+    hal_gpio_pin_clear(p_uart_init->tx_pin->port, p_uart_init->tx_pin->pin);
+
+    p_instance->PSELTXD = p_uart_init->tx_pin->pin;
+    p_instance->PSELRXD = p_uart_init->rx_pin->pin;
+
+#if NRF52840_XXAA
+    p_instance->PSELTXD |= (p_uart_init->tx_pin->port << UARTE_PSEL_TXD_PORT_Pos);
+    p_instance->PSELRXD |= (p_uart_init->rx_pin->port << UARTE_PSEL_RXD_PORT_Pos);
+#endif
+
+    if (p_uart_init->flow_control) {
+        hal_gpio_cfg_pin(p_uart_init->rts_pin->port, p_uart_init->rts_pin->pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED);
+        hal_gpio_cfg_pin(p_uart_init->cts_pin->port, p_uart_init->cts_pin->pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED);
+
+        p_instance->PSELCTS = p_uart_init->cts_pin->pin;
+        p_instance->PSELRTS = p_uart_init->rts_pin->pin;
+
+#if NRF52840_XXAA
+        p_instance->PSELCTS |= (p_uart_init->cts_pin->port << UARTE_PSEL_CTS_PORT_Pos);
+        p_instance->PSELRTS |= (p_uart_init->rts_pin->port << UARTE_PSEL_RTS_PORT_Pos);
+#endif
+
+        p_instance->CONFIG  = (UART_CONFIG_HWFC_Enabled << UART_CONFIG_HWFC_Pos);
+    }
+
+    p_instance->BAUDRATE      = (hal_uart_baudrate_lookup[p_uart_init->baud_rate]);
+    p_instance->ENABLE        = (UART_ENABLE_ENABLE_Enabled << UART_ENABLE_ENABLE_Pos);
+    p_instance->EVENTS_TXDRDY = 0;
+    p_instance->EVENTS_RXDRDY = 0;
+    p_instance->TASKS_STARTTX = 1;
+    p_instance->TASKS_STARTRX = 1;
+}
+
+#endif // HAL_UART_MODULE_ENABLED
diff --git a/ports/nrf/hal/hal_uart.h b/ports/nrf/hal/hal_uart.h
new file mode 100644
index 0000000000..ca0110c3e4
--- /dev/null
+++ b/ports/nrf/hal/hal_uart.h
@@ -0,0 +1,125 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HAL_UART_H__
+#define HAL_UART_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "nrf.h"
+
+#if NRF51
+  #define UART_HWCONTROL_NONE                  ((uint32_t)UART_CONFIG_HWFC_Disabled << UART_CONFIG_HWFC_Pos)
+  #define UART_HWCONTROL_RTS_CTS               ((uint32_t)(UART_CONFIG_HWFC_Enabled << UART_CONFIG_HWFC_Pos)
+  #define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
+                              (((CONTROL) == UART_HWCONTROL_NONE) || \
+                               ((CONTROL) == UART_HWCONTROL_RTS_CTS))
+  #define UART_BASE_POINTERS (const uint32_t[]){NRF_UART0_BASE}
+  #define UART_IRQ_VALUES (const uint32_t[]){UART0_IRQn}
+
+#elif NRF52
+  #define UART_HWCONTROL_NONE                  ((uint32_t)UARTE_CONFIG_HWFC_Disabled << UARTE_CONFIG_HWFC_Pos)
+  #define UART_HWCONTROL_RTS_CTS               ((uint32_t)(UARTE_CONFIG_HWFC_Enabled << UARTE_CONFIG_HWFC_Pos)
+  #define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
+                              (((CONTROL) == UART_HWCONTROL_NONE) || \
+                               ((CONTROL) == UART_HWCONTROL_RTS_CTS))
+  #ifdef HAL_UART_MODULE_ENABLED
+    #define UART_BASE_POINTERS (const uint32_t[]){NRF_UART0_BASE}
+    #define UART_IRQ_VALUES (const uint32_t[]){UARTE0_UART0_IRQn}
+  #else // HAL_UARTE_MODULE_ENABLED
+    #ifdef NRF52832_XXAA
+      #define UART_BASE_POINTERS (const uint32_t[]){NRF_UARTE0_BASE}
+      #define UART_IRQ_VALUES (const uint32_t[]){UARTE0_UART0_IRQn}
+    #elif NRF52840_XXAA
+      #define UART_BASE_POINTERS (const uint32_t[]){NRF_UARTE0_BASE, \
+                                                    NRF_UARTE1_BASE}
+      #define UART_IRQ_VALUES (const uint32_t[]){UARTE0_UART0_IRQn, \
+                                                 UARTE1_IRQn}
+    #endif // HAL_UARTE_MODULE_ENABLED
+  #endif
+#else
+#error "Device not supported."
+#endif
+
+#define UART_BASE(x) ((NRF_UART_Type *)UART_BASE_POINTERS[x])
+#define UART_IRQ_NUM(x) (UART_IRQ_VALUES[x])
+
+typedef enum
+{
+    HAL_UART_ERROR_NONE      = 0x00,    /*!< No error */
+    HAL_UART_ERROR_ORE       = 0x01,    /*!< Overrun error. A start bit is received while the previous data still lies in RXD. (Previous data is lost.) */
+    HAL_UART_ERROR_PE        = 0x02,    /*!< Parity error. A character with bad parity is received, if HW parity check is enabled. */
+    HAL_UART_ERROR_FE        = 0x04,    /*!< Frame error. A valid stop bit is not detected on the serial data input after all bits in a character have been received. */
+    HAL_UART_ERROR_BE        = 0x08,    /*!< Break error. The serial data input is '0' for longer than the length of a data frame. (The data frame length is 10 bits without parity bit, and 11 bits with parity bit.). */
+} hal_uart_error_t;
+
+typedef enum {
+    HAL_UART_BAUD_1K2 = 0,        /**< 1200 baud */
+    HAL_UART_BAUD_2K4,            /**< 2400 baud */
+    HAL_UART_BAUD_4K8,            /**< 4800 baud */
+    HAL_UART_BAUD_9K6,            /**< 9600 baud */
+    HAL_UART_BAUD_14K4,           /**< 14.4 kbaud */
+    HAL_UART_BAUD_19K2,           /**< 19.2 kbaud */
+    HAL_UART_BAUD_28K8,           /**< 28.8 kbaud */
+    HAL_UART_BAUD_38K4,           /**< 38.4 kbaud */
+    HAL_UART_BAUD_57K6,           /**< 57.6 kbaud */
+    HAL_UART_BAUD_76K8,           /**< 76.8 kbaud */
+    HAL_UART_BAUD_115K2,          /**< 115.2 kbaud */
+    HAL_UART_BAUD_230K4,          /**< 230.4 kbaud */
+    HAL_UART_BAUD_250K0,          /**< 250.0 kbaud */
+    HAL_UART_BAUD_500K0,          /**< 500.0 kbaud */
+    HAL_UART_BAUD_1M0             /**< 1 mbaud */
+} hal_uart_baudrate_t;
+
+typedef struct {
+    uint8_t           id;           /* UART instance id */
+    const pin_obj_t * rx_pin;       /* RX pin. */
+    const pin_obj_t * tx_pin;       /* TX pin. */
+    const pin_obj_t * rts_pin;      /* RTS pin, only used if flow control is enabled. */
+    const pin_obj_t * cts_pin;      /* CTS pin, only used if flow control is enabled. */
+    bool              flow_control; /* Flow control setting, if flow control is used, the system will use low power UART mode, based on CTS signal. */
+    bool              use_parity;   /* Even parity if TRUE, no parity if FALSE. */
+    uint32_t          baud_rate;    /* Baud rate configuration. */
+    uint32_t          irq_priority; /* UARTE IRQ priority. */
+    uint32_t          irq_num;
+} hal_uart_init_t;
+
+typedef struct
+{
+    NRF_UART_Type     * p_instance; /* UART registers base address   */
+    hal_uart_init_t     init;       /* UART communication parameters */
+} UART_HandleTypeDef;
+
+typedef void (*uart_complete_cb)(void);
+
+void hal_uart_init(NRF_UART_Type * p_instance, hal_uart_init_t const * p_uart_init);
+
+hal_uart_error_t hal_uart_char_write(NRF_UART_Type * p_instance, uint8_t ch);
+
+hal_uart_error_t hal_uart_char_read(NRF_UART_Type * p_instance, uint8_t * ch);
+
+#endif // HAL_UART_H__
diff --git a/ports/nrf/hal/hal_uarte.c b/ports/nrf/hal/hal_uarte.c
new file mode 100644
index 0000000000..d3e899b91d
--- /dev/null
+++ b/ports/nrf/hal/hal_uarte.c
@@ -0,0 +1,180 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <stdint.h>
+#include <stdio.h>
+#include "mphalport.h"
+
+#include "hal_uart.h"
+#include "hal_irq.h"
+
+#ifdef HAL_UARTE_MODULE_ENABLED
+
+#include "nrf.h"
+
+#ifndef NRF52
+#error "Device not supported."
+#endif
+
+#define UART_BASE(x) ((NRF_UART_Type *)UART_BASE_POINTERS[x])
+#define UART_IRQ_NUM(x) (UART_IRQ_VALUES[x])
+
+#define TX_BUF_SIZE 1
+#define RX_BUF_SIZE 1
+
+static const uint32_t hal_uart_baudrate_lookup[] = {
+    UARTE_BAUDRATE_BAUDRATE_Baud1200,   ///< 1200 baud.
+    UARTE_BAUDRATE_BAUDRATE_Baud2400,   ///< 2400 baud.
+    UARTE_BAUDRATE_BAUDRATE_Baud4800,   ///< 4800 baud.
+    UARTE_BAUDRATE_BAUDRATE_Baud9600,   ///< 9600 baud.
+    UARTE_BAUDRATE_BAUDRATE_Baud14400,  ///< 14400 baud.
+    UARTE_BAUDRATE_BAUDRATE_Baud19200,  ///< 19200 baud.
+    UARTE_BAUDRATE_BAUDRATE_Baud28800,  ///< 28800 baud.
+    UARTE_BAUDRATE_BAUDRATE_Baud38400,  ///< 38400 baud.
+    UARTE_BAUDRATE_BAUDRATE_Baud57600,  ///< 57600 baud.
+    UARTE_BAUDRATE_BAUDRATE_Baud76800,  ///< 76800 baud.
+    UARTE_BAUDRATE_BAUDRATE_Baud115200, ///< 115200 baud.
+    UARTE_BAUDRATE_BAUDRATE_Baud230400, ///< 230400 baud.
+    UARTE_BAUDRATE_BAUDRATE_Baud250000, ///< 250000 baud.
+    UARTE_BAUDRATE_BAUDRATE_Baud460800, ///< 460800 baud.
+    UARTE_BAUDRATE_BAUDRATE_Baud921600, ///< 921600 baud.
+    UARTE_BAUDRATE_BAUDRATE_Baud1M,     ///< 1000000 baud.
+};
+
+void nrf_sendchar(NRF_UART_Type * p_instance, int ch) {
+    hal_uart_char_write(p_instance, ch);
+}
+
+void hal_uart_init(NRF_UART_Type * p_instance, hal_uart_init_t const * p_uart_init) {
+
+    NRF_UARTE_Type * uarte_instance = (NRF_UARTE_Type *)p_instance;
+
+    hal_gpio_cfg_pin(p_uart_init->tx_pin->port, p_uart_init->tx_pin->pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED);
+    hal_gpio_pin_set(p_uart_init->tx_pin->port, p_uart_init->tx_pin->pin);
+    hal_gpio_cfg_pin(p_uart_init->tx_pin->port, p_uart_init->rx_pin->pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED);
+
+    uarte_instance->BAUDRATE = (hal_uart_baudrate_lookup[p_uart_init->baud_rate]);
+
+    uint32_t hwfc   = (p_uart_init->flow_control) 
+                      ? (UARTE_CONFIG_HWFC_Enabled << UARTE_CONFIG_HWFC_Pos)
+                      : (UARTE_CONFIG_HWFC_Disabled << UARTE_CONFIG_HWFC_Pos);
+
+    uint32_t parity = (p_uart_init->use_parity)
+                      ? (UARTE_CONFIG_PARITY_Included << UARTE_CONFIG_PARITY_Pos)
+                      : (UARTE_CONFIG_PARITY_Excluded << UARTE_CONFIG_PARITY_Pos);
+
+    uarte_instance->CONFIG = (uint32_t)hwfc | (uint32_t)parity;
+
+    uarte_instance->PSEL.RXD = p_uart_init->rx_pin->pin;
+    uarte_instance->PSEL.TXD = p_uart_init->tx_pin->pin;
+
+#if NRF52840_XXAA
+    uarte_instance->PSEL.RXD |= (p_uart_init->rx_pin->port << UARTE_PSEL_RXD_PORT_Pos);
+    uarte_instance->PSEL.TXD |= (p_uart_init->tx_pin->port << UARTE_PSEL_TXD_PORT_Pos);
+#endif
+
+    if (hwfc) {
+        hal_gpio_cfg_pin(p_uart_init->cts_pin->port, p_uart_init->cts_pin->pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED);
+        hal_gpio_cfg_pin(p_uart_init->rts_pin->port, p_uart_init->rts_pin->pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED);
+        hal_gpio_pin_set(p_uart_init->rts_pin->port, p_uart_init->rts_pin->pin);
+
+        uarte_instance->PSEL.RTS = p_uart_init->rts_pin->pin;
+        uarte_instance->PSEL.CTS = p_uart_init->cts_pin->pin;
+
+#if NRF52840_XXAA
+        uarte_instance->PSEL.RTS |= (p_uart_init->rx_pin->port << UARTE_PSEL_RTS_PORT_Pos);
+        uarte_instance->PSEL.CTS |= (p_uart_init->rx_pin->port << UARTE_PSEL_CTS_PORT_Pos);
+#endif
+    }
+
+    hal_irq_priority(p_uart_init->irq_num, p_uart_init->irq_priority);
+    hal_irq_enable(p_uart_init->irq_num);
+
+    uarte_instance->INTENSET = (UARTE_INTENSET_ENDRX_Set << UARTE_INTENSET_ENDRX_Pos);
+    uarte_instance->INTENSET = (UARTE_INTENSET_ENDTX_Set << UARTE_INTENSET_ENDTX_Pos);
+
+    uarte_instance->ENABLE = (UARTE_ENABLE_ENABLE_Enabled << UARTE_ENABLE_ENABLE_Pos);
+
+    uarte_instance->EVENTS_ENDTX  = 0;
+    uarte_instance->EVENTS_ENDRX  = 0;
+}
+
+hal_uart_error_t hal_uart_char_write(NRF_UART_Type * p_instance, uint8_t ch) {
+
+    NRF_UARTE_Type * uarte_instance = (NRF_UARTE_Type *)p_instance;
+
+    uarte_instance->ERRORSRC = 0;
+
+
+    static volatile uint8_t m_tx_buf[TX_BUF_SIZE];
+    (void)m_tx_buf;
+
+    uarte_instance->INTENCLR = (UARTE_INTENSET_ENDTX_Set << UARTE_INTENSET_ENDTX_Pos);
+
+    m_tx_buf[0] = ch;
+
+    uarte_instance->TXD.PTR = (uint32_t)((uint8_t *)m_tx_buf);
+    uarte_instance->TXD.MAXCNT = (uint32_t)sizeof(m_tx_buf);
+
+    uarte_instance->TASKS_STARTTX = 1;
+
+    while((0 == uarte_instance->EVENTS_ENDTX));
+
+    uarte_instance->EVENTS_ENDTX  = 0;
+    uarte_instance->TASKS_STOPTX  = 1;
+
+    uarte_instance->INTENSET = (UARTE_INTENSET_ENDTX_Set << UARTE_INTENSET_ENDTX_Pos);
+
+    return uarte_instance->ERRORSRC;
+}
+
+hal_uart_error_t hal_uart_char_read(NRF_UART_Type * p_instance, uint8_t * ch) {
+
+    NRF_UARTE_Type * uarte_instance = (NRF_UARTE_Type *)p_instance;
+
+    uarte_instance->ERRORSRC = 0;
+
+    static volatile uint8_t m_rx_buf[RX_BUF_SIZE];
+
+    uarte_instance->INTENCLR = (UARTE_INTENSET_ENDRX_Set << UARTE_INTENSET_ENDRX_Pos);
+
+    uarte_instance->RXD.PTR = (uint32_t)((uint8_t *)m_rx_buf);
+    uarte_instance->RXD.MAXCNT = (uint32_t)sizeof(m_rx_buf);
+
+    uarte_instance->TASKS_STARTRX = 1;
+
+    while ((0 == uarte_instance->EVENTS_ENDRX));
+
+    uarte_instance->EVENTS_ENDRX  = 0;
+    uarte_instance->TASKS_STOPRX  = 1;
+
+    uarte_instance->INTENSET = (UARTE_INTENSET_ENDRX_Set << UARTE_INTENSET_ENDRX_Pos);
+    *ch = (uint8_t)m_rx_buf[0];
+
+    return uarte_instance->ERRORSRC;
+}
+
+#endif // HAL_UARTE_MODULE_ENABLED
diff --git a/ports/nrf/hal/nrf51_hal.h b/ports/nrf/hal/nrf51_hal.h
new file mode 100644
index 0000000000..68b3c1ae0d
--- /dev/null
+++ b/ports/nrf/hal/nrf51_hal.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <nrf.h>
+
+// include config from board
+#include "nrf51_hal_conf.h"
diff --git a/ports/nrf/hal/nrf52_hal.h b/ports/nrf/hal/nrf52_hal.h
new file mode 100644
index 0000000000..daa05e9101
--- /dev/null
+++ b/ports/nrf/hal/nrf52_hal.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <nrf.h>
+
+// include config from board
+#include "nrf52_hal_conf.h"
diff --git a/ports/nrf/help.c b/ports/nrf/help.c
new file mode 100644
index 0000000000..5cbb0fc911
--- /dev/null
+++ b/ports/nrf/help.c
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "py/builtin.h"
+
+#if BLUETOOTH_SD
+#include "help_sd.h"
+#endif
+
+const char nrf5_help_text[] =
+"Welcome to MicroPython!\n"
+"\n"
+"For online help please visit http://micropython.org/help/.\n"
+"\n"
+"Quick overview of commands for the board:\n"
+#if MICROPY_HW_HAS_LED
+"  pyb.LED(n)    -- create an LED object for LED n (n=" HELP_TEXT_BOARD_LED ")\n"
+"\n"
+#endif
+#if BLUETOOTH_SD
+HELP_TEXT_SD
+#endif
+"Control commands:\n"
+"  CTRL-A        -- on a blank line, enter raw REPL mode\n"
+"  CTRL-B        -- on a blank line, enter normal REPL mode\n"
+"  CTRL-D        -- on a blank line, do a soft reset of the board\n"
+"  CTRL-E        -- on a blank line, enter paste mode\n"
+"\n"
+"For further help on a specific object, type help(obj)\n"
+;
diff --git a/ports/nrf/main.c b/ports/nrf/main.c
new file mode 100644
index 0000000000..92f578cda1
--- /dev/null
+++ b/ports/nrf/main.c
@@ -0,0 +1,265 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+
+#include "py/nlr.h"
+#include "py/mperrno.h"
+#include "py/lexer.h"
+#include "py/parse.h"
+#include "py/obj.h"
+#include "py/runtime.h"
+#include "py/stackctrl.h"
+#include "py/gc.h"
+#include "py/compile.h"
+#include "lib/utils/pyexec.h"
+#include "readline.h"
+#include "gccollect.h"
+#include "modmachine.h"
+#include "modmusic.h"
+#include "led.h"
+#include "uart.h"
+#include "nrf.h"
+#include "pin.h"
+#include "spi.h"
+#include "i2c.h"
+#include "rtc.h"
+#if MICROPY_PY_MACHINE_HW_PWM
+#include "pwm.h"
+#endif
+#include "timer.h"
+
+#if (MICROPY_PY_BLE_NUS)
+#include "ble_uart.h"
+#endif
+
+void do_str(const char *src, mp_parse_input_kind_t input_kind) {
+    mp_lexer_t *lex = mp_lexer_new_from_str_len(MP_QSTR__lt_stdin_gt_, src, strlen(src), 0);
+    if (lex == NULL) {
+        printf("MemoryError: lexer could not allocate memory\n");
+        return;
+    }
+
+    nlr_buf_t nlr;
+    if (nlr_push(&nlr) == 0) {
+        qstr source_name = lex->source_name;
+        mp_parse_tree_t pn = mp_parse(lex, input_kind);
+        mp_obj_t module_fun = mp_compile(&pn, source_name, MP_EMIT_OPT_NONE, true);
+        mp_call_function_0(module_fun);
+        nlr_pop();
+    } else {
+        // uncaught exception
+        mp_obj_print_exception(&mp_plat_print, (mp_obj_t)nlr.ret_val);
+    }
+}
+
+extern uint32_t _heap_start;
+extern uint32_t _heap_end;
+
+int main(int argc, char **argv) {
+    
+soft_reset:
+    mp_stack_set_top(&_ram_end);
+
+    // Stack limit should be less than real stack size, so we have a chance
+    // to recover from limit hit.  (Limit is measured in bytes.)
+    mp_stack_set_limit((char*)&_ram_end - (char*)&_heap_end - 400);
+
+    machine_init();
+
+    gc_init(&_heap_start, &_heap_end);
+
+    mp_init();
+    mp_obj_list_init(mp_sys_path, 0);
+    mp_obj_list_append(mp_sys_path, MP_OBJ_NEW_QSTR(MP_QSTR_)); // current dir (or base dir of the script)
+    mp_obj_list_init(mp_sys_argv, 0);
+
+    pyb_set_repl_info(MP_OBJ_NEW_SMALL_INT(0));
+
+    readline_init0();
+
+#if MICROPY_PY_MACHINE_HW_SPI
+    spi_init0();
+#endif
+
+#if MICROPY_PY_MACHINE_I2C
+    i2c_init0();
+#endif
+
+#if MICROPY_PY_MACHINE_HW_PWM
+    pwm_init0();
+#endif
+
+#if MICROPY_PY_MACHINE_RTC
+    rtc_init0();
+#endif
+
+#if MICROPY_PY_MACHINE_TIMER
+    timer_init0();
+#endif
+
+    uart_init0();
+
+#if (MICROPY_PY_BLE_NUS == 0)
+    {
+        mp_obj_t args[2] = {
+            MP_OBJ_NEW_SMALL_INT(0),
+            MP_OBJ_NEW_SMALL_INT(115200),
+        };
+        MP_STATE_PORT(pyb_stdio_uart) = machine_hard_uart_type.make_new((mp_obj_t)&machine_hard_uart_type, MP_ARRAY_SIZE(args), 0, args);
+    }
+#endif
+
+pin_init0();
+
+#if MICROPY_HW_HAS_SDCARD
+    // if an SD card is present then mount it on /sd/
+    if (sdcard_is_present()) {
+        // create vfs object
+        fs_user_mount_t *vfs = m_new_obj_maybe(fs_user_mount_t);
+        if (vfs == NULL) {
+            goto no_mem_for_sd;
+        }
+        vfs->str = "/sd";
+        vfs->len = 3;
+        vfs->flags = FSUSER_FREE_OBJ;
+        sdcard_init_vfs(vfs);
+
+        // put the sd device in slot 1 (it will be unused at this point)
+        MP_STATE_PORT(fs_user_mount)[1] = vfs;
+
+        FRESULT res = f_mount(&vfs->fatfs, vfs->str, 1);
+        if (res != FR_OK) {
+            printf("PYB: can't mount SD card\n");
+            MP_STATE_PORT(fs_user_mount)[1] = NULL;
+            m_del_obj(fs_user_mount_t, vfs);
+        } else {
+            // TODO these should go before the /flash entries in the path
+            mp_obj_list_append(mp_sys_path, MP_OBJ_NEW_QSTR(MP_QSTR__slash_sd));
+            mp_obj_list_append(mp_sys_path, MP_OBJ_NEW_QSTR(MP_QSTR__slash_sd_slash_lib));
+
+			// use SD card as current directory
+			f_chdrive("/sd");
+        }
+        no_mem_for_sd:;
+    }
+#endif
+
+#if (MICROPY_HW_HAS_LED)
+    led_init();
+
+    do_str("import pyb\r\n" \
+           "pyb.LED(1).on()",
+           MP_PARSE_FILE_INPUT);
+#endif
+
+    // Main script is finished, so now go into REPL mode.
+    // The REPL mode can change, or it can request a soft reset.
+    int ret_code = 0;
+
+#if MICROPY_PY_BLE_NUS
+    ble_uart_init0();
+    while (!ble_uart_enabled()) {
+        ;
+    }
+#endif
+
+    for (;;) {
+        if (pyexec_mode_kind == PYEXEC_MODE_RAW_REPL) {
+            if (pyexec_raw_repl() != 0) {
+                break;
+            }
+        } else {
+            ret_code = pyexec_friendly_repl();
+            if (ret_code != 0) {
+                break;
+            }
+        }
+    }
+
+    mp_deinit();
+
+    if (ret_code == PYEXEC_FORCED_EXIT) {
+        NVIC_SystemReset();
+    } else {
+        goto soft_reset;
+    }
+
+    return 0;
+}
+
+#if !MICROPY_VFS
+mp_lexer_t *mp_lexer_new_from_file(const char *filename) {
+    mp_raise_OSError(MP_ENOENT);
+}
+
+mp_import_stat_t mp_import_stat(const char *path) {
+    return MP_IMPORT_STAT_NO_EXIST;
+}
+
+STATIC mp_obj_t mp_builtin_open(size_t n_args, const mp_obj_t *args, mp_map_t *kwargs) {
+    mp_raise_OSError(MP_EPERM);
+}
+MP_DEFINE_CONST_FUN_OBJ_KW(mp_builtin_open_obj, 1, mp_builtin_open);
+#endif
+
+void HardFault_Handler(void)
+{
+#if NRF52
+	static volatile uint32_t reg;
+	static volatile uint32_t reg2;
+	static volatile uint32_t bfar;
+	reg = SCB->HFSR;
+	reg2 = SCB->CFSR;
+	bfar = SCB->BFAR;
+	for (int i = 0; i < 0; i++)
+	{
+		(void)reg;
+		(void)reg2;
+		(void)bfar;
+	}
+#endif
+}
+
+void NORETURN __fatal_error(const char *msg) {
+    while (1);
+}
+
+void nlr_jump_fail(void *val) {
+    printf("FATAL: uncaught exception %p\n", val);
+    mp_obj_print_exception(&mp_plat_print, (mp_obj_t)val);
+    __fatal_error("");
+}
+
+void MP_WEAK __assert_func(const char *file, int line, const char *func, const char *expr) {
+    printf("Assertion '%s' failed, at file %s:%d\n", expr, file, line);
+    __fatal_error("Assertion failed");
+}
+
+void _start(void) {main(0, NULL);}
diff --git a/ports/nrf/modules/ble/help_sd.h b/ports/nrf/modules/ble/help_sd.h
new file mode 100644
index 0000000000..027bbdd513
--- /dev/null
+++ b/ports/nrf/modules/ble/help_sd.h
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HELP_SD_H__
+#define HELP_SD_H__
+
+#include "bluetooth_conf.h"
+
+#if MICROPY_PY_BLE
+
+#define HELP_TEXT_SD \
+"If compiled with SD=<softdevice> the additional commands are\n" \
+"available:\n" \
+"  ble.enable()    -- enable bluetooth stack\n" \
+"  ble.disable()   -- disable bluetooth stack\n" \
+"  ble.enabled()   -- check whether bluetooth stack is enabled\n" \
+"  ble.address()   -- return device address as text string\n" \
+"\n"
+ 
+#else
+#define HELP_TEXT_SD
+#endif // MICROPY_PY_BLE
+
+#endif
diff --git a/ports/nrf/modules/ble/modble.c b/ports/nrf/modules/ble/modble.c
new file mode 100644
index 0000000000..e025006b17
--- /dev/null
+++ b/ports/nrf/modules/ble/modble.c
@@ -0,0 +1,105 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <stdio.h>
+#include <stdint.h>
+#include "py/runtime.h"
+
+#if MICROPY_PY_BLE
+
+#include "led.h"
+#include "mpconfigboard.h"
+#include "ble_drv.h"
+
+/// \method enable()
+/// Enable BLE softdevice.
+mp_obj_t ble_obj_enable(void) {
+    printf("SoftDevice enabled\n");
+    uint32_t err_code = ble_drv_stack_enable();
+    if (err_code < 0) {
+        // TODO: raise exception.
+    }
+    return mp_const_none;
+}
+
+/// \method disable()
+/// Disable BLE softdevice.
+mp_obj_t ble_obj_disable(void) {
+    ble_drv_stack_disable();
+    return mp_const_none;
+}
+
+/// \method enabled()
+/// Get state of whether the softdevice is enabled or not.
+mp_obj_t ble_obj_enabled(void) {
+    uint8_t is_enabled = ble_drv_stack_enabled();
+    mp_int_t enabled = is_enabled;
+    return MP_OBJ_NEW_SMALL_INT(enabled);
+}
+
+/// \method address()
+/// Return device address as text string.
+mp_obj_t ble_obj_address(void) {
+    ble_drv_addr_t local_addr;
+    ble_drv_address_get(&local_addr);
+
+    vstr_t vstr;
+    vstr_init(&vstr, 17);
+
+    vstr_printf(&vstr, ""HEX2_FMT":"HEX2_FMT":"HEX2_FMT":" \
+                         HEX2_FMT":"HEX2_FMT":"HEX2_FMT"",
+                local_addr.addr[5], local_addr.addr[4], local_addr.addr[3],
+                local_addr.addr[2], local_addr.addr[1], local_addr.addr[0]);
+
+    mp_obj_t mac_str = mp_obj_new_str(vstr.buf, vstr.len, false);
+
+    vstr_clear(&vstr);
+
+    return mac_str;
+}
+
+STATIC MP_DEFINE_CONST_FUN_OBJ_0(ble_obj_enable_obj, ble_obj_enable);
+STATIC MP_DEFINE_CONST_FUN_OBJ_0(ble_obj_disable_obj, ble_obj_disable);
+STATIC MP_DEFINE_CONST_FUN_OBJ_0(ble_obj_enabled_obj, ble_obj_enabled);
+STATIC MP_DEFINE_CONST_FUN_OBJ_0(ble_obj_address_obj, ble_obj_address);
+
+STATIC const mp_rom_map_elem_t ble_module_globals_table[] = {
+    { MP_ROM_QSTR(MP_QSTR___name__), MP_ROM_QSTR(MP_QSTR_ble) },
+    { MP_ROM_QSTR(MP_QSTR_enable),   MP_ROM_PTR(&ble_obj_enable_obj) },
+    { MP_ROM_QSTR(MP_QSTR_disable),  MP_ROM_PTR(&ble_obj_disable_obj) },
+    { MP_ROM_QSTR(MP_QSTR_enabled),  MP_ROM_PTR(&ble_obj_enabled_obj) },
+    { MP_ROM_QSTR(MP_QSTR_address),  MP_ROM_PTR(&ble_obj_address_obj) },
+};
+
+
+STATIC MP_DEFINE_CONST_DICT(ble_module_globals, ble_module_globals_table);
+
+const mp_obj_module_t ble_module = {
+    .base = { &mp_type_module },
+    .globals = (mp_obj_dict_t*)&ble_module_globals,
+};
+
+#endif // MICROPY_PY_BLE
diff --git a/ports/nrf/modules/machine/adc.c b/ports/nrf/modules/machine/adc.c
new file mode 100644
index 0000000000..61cb6f7b49
--- /dev/null
+++ b/ports/nrf/modules/machine/adc.c
@@ -0,0 +1,144 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <stdio.h>
+#include <string.h>
+
+#include "py/nlr.h"
+#include "py/runtime.h"
+#include "py/mphal.h"
+#include "adc.h"
+#include "hal_adc.h"
+
+#if MICROPY_PY_MACHINE_ADC
+
+typedef struct _machine_adc_obj_t {
+    mp_obj_base_t base;
+    ADC_HandleTypeDef *adc;
+} machine_adc_obj_t;
+
+ADC_HandleTypeDef ADCHandle0 = {.config.channel = 0};
+ADC_HandleTypeDef ADCHandle1 = {.config.channel = 1};
+ADC_HandleTypeDef ADCHandle2 = {.config.channel = 2};
+ADC_HandleTypeDef ADCHandle3 = {.config.channel = 3};
+ADC_HandleTypeDef ADCHandle4 = {.config.channel = 4};
+ADC_HandleTypeDef ADCHandle5 = {.config.channel = 5};
+ADC_HandleTypeDef ADCHandle6 = {.config.channel = 6};
+ADC_HandleTypeDef ADCHandle7 = {.config.channel = 7};
+
+STATIC const machine_adc_obj_t machine_adc_obj[] = {
+    {{&machine_adc_type}, &ADCHandle0},
+    {{&machine_adc_type}, &ADCHandle1},
+    {{&machine_adc_type}, &ADCHandle2},
+    {{&machine_adc_type}, &ADCHandle3},
+    {{&machine_adc_type}, &ADCHandle4},
+    {{&machine_adc_type}, &ADCHandle5},
+    {{&machine_adc_type}, &ADCHandle6},
+    {{&machine_adc_type}, &ADCHandle7},
+};
+
+STATIC int adc_find(mp_obj_t id) {
+    // given an integer id
+    int adc_id = mp_obj_get_int(id);
+
+    int adc_idx = adc_id;
+
+    if (adc_idx >= 0 && adc_idx <= MP_ARRAY_SIZE(machine_adc_obj)
+        && machine_adc_obj[adc_idx].adc != NULL) {
+        return adc_idx;
+    }
+    nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
+        "ADC(%d) does not exist", adc_id));
+}
+
+
+/// \method __str__()
+/// Return a string describing the ADC object.
+STATIC void machine_adc_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) {
+    machine_adc_obj_t *self = o;
+
+    (void)self;
+
+    mp_printf(print, "ADC()");
+}
+
+/******************************************************************************/
+/* MicroPython bindings for machine API                                       */
+
+// for make_new
+enum {
+    ARG_NEW_PIN,
+};
+
+STATIC mp_obj_t machine_adc_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) {
+    static const mp_arg_t allowed_args[] = {
+        { ARG_NEW_PIN,  MP_ARG_OBJ, {.u_obj = MP_OBJ_NEW_SMALL_INT(-1) } },
+    };
+
+    // parse args
+    mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
+    mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
+
+    int adc_id = adc_find(args[ARG_NEW_PIN].u_obj);
+    const machine_adc_obj_t *self = &machine_adc_obj[adc_id];
+
+    return MP_OBJ_FROM_PTR(self);
+}
+
+/// \method value()
+/// Read adc level.
+mp_obj_t machine_adc_value(mp_obj_t self_in) {
+    machine_adc_obj_t *self = self_in;
+    return MP_OBJ_NEW_SMALL_INT(hal_adc_channel_value(&self->adc->config));
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(mp_machine_adc_value_obj, machine_adc_value);
+
+/// \method battery_level()
+/// Get battery level in percentage.
+mp_obj_t machine_adc_battery_level(void) {
+    return MP_OBJ_NEW_SMALL_INT(hal_adc_battery_level());
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_0(mp_machine_adc_battery_level_obj, machine_adc_battery_level);
+
+STATIC const mp_rom_map_elem_t machine_adc_locals_dict_table[] = {
+    // instance methods
+    { MP_ROM_QSTR(MP_QSTR_value), MP_ROM_PTR(&mp_machine_adc_value_obj) },
+
+    // class methods
+    { MP_ROM_QSTR(MP_QSTR_battery_level), MP_ROM_PTR(&mp_machine_adc_battery_level_obj) },
+};
+
+STATIC MP_DEFINE_CONST_DICT(machine_adc_locals_dict, machine_adc_locals_dict_table);
+
+const mp_obj_type_t machine_adc_type = {
+    { &mp_type_type },
+    .name = MP_QSTR_ADC,
+    .make_new = machine_adc_make_new,
+    .locals_dict = (mp_obj_dict_t*)&machine_adc_locals_dict,
+    .print = machine_adc_print,
+};
+
+#endif // MICROPY_PY_MACHINE_ADC
diff --git a/ports/nrf/modules/machine/adc.h b/ports/nrf/modules/machine/adc.h
new file mode 100644
index 0000000000..a8ff56fbba
--- /dev/null
+++ b/ports/nrf/modules/machine/adc.h
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef ADC_H__
+#define ADC_H__
+
+#include "hal_adc.h"
+
+extern const mp_obj_type_t machine_adc_type;
+
+#endif // ADC_H__
diff --git a/ports/nrf/modules/machine/i2c.c b/ports/nrf/modules/machine/i2c.c
new file mode 100644
index 0000000000..943599816e
--- /dev/null
+++ b/ports/nrf/modules/machine/i2c.c
@@ -0,0 +1,163 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <stdio.h>
+#include <string.h>
+
+#include "py/nlr.h"
+#include "py/runtime.h"
+#include "py/mphal.h"
+#include "extmod/machine_i2c.h"
+#include "i2c.h"
+#include "hal_twi.h"
+
+#if MICROPY_PY_MACHINE_I2C
+
+STATIC const mp_obj_type_t machine_hard_i2c_type;
+
+typedef struct _machine_hard_i2c_obj_t {
+    mp_obj_base_t base;
+    TWI_HandleTypeDef *i2c;
+} machine_hard_i2c_obj_t;
+
+TWI_HandleTypeDef I2CHandle0 = {.instance = NULL, .init.id = 0};
+TWI_HandleTypeDef I2CHandle1 = {.instance = NULL, .init.id = 1};
+
+STATIC const machine_hard_i2c_obj_t machine_hard_i2c_obj[] = {
+    {{&machine_hard_i2c_type}, &I2CHandle0},
+    {{&machine_hard_i2c_type}, &I2CHandle1},
+};
+
+void i2c_init0(void) {
+    // reset the I2C handles
+    memset(&I2CHandle0, 0, sizeof(TWI_HandleTypeDef));
+    I2CHandle0.instance = TWI_BASE(0);
+    memset(&I2CHandle1, 0, sizeof(TWI_HandleTypeDef));
+    I2CHandle0.instance = TWI_BASE(1);
+}
+
+STATIC int i2c_find(mp_obj_t id) {
+    // given an integer id
+    int i2c_id = mp_obj_get_int(id);
+    if (i2c_id >= 0 && i2c_id <= MP_ARRAY_SIZE(machine_hard_i2c_obj)
+        && machine_hard_i2c_obj[i2c_id].i2c != NULL) {
+        return i2c_id;
+    }
+    nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
+        "I2C(%d) does not exist", i2c_id));
+}
+
+STATIC void machine_hard_i2c_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) {
+    machine_hard_i2c_obj_t *self = o;
+    mp_printf(print, "I2C(%u, scl=(port=%u, pin=%u), sda=(port=%u, pin=%u))",
+              self->i2c->init.id,
+              self->i2c->init.scl_pin->port,
+              self->i2c->init.scl_pin->pin,
+              self->i2c->init.sda_pin->port,
+              self->i2c->init.sda_pin->pin);
+}
+
+/******************************************************************************/
+/* MicroPython bindings for machine API                                       */
+
+// for make_new
+enum {
+    ARG_NEW_id,
+    ARG_NEW_scl,
+    ARG_NEW_sda,
+    ARG_NEW_freq,
+    ARG_NEW_timeout,
+};
+
+mp_obj_t machine_hard_i2c_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) {
+    static const mp_arg_t allowed_args[] = {
+        { ARG_NEW_id,       MP_ARG_REQUIRED | MP_ARG_OBJ },
+        { ARG_NEW_scl,      MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
+        { ARG_NEW_sda,      MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
+    };
+
+    // parse args
+    mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
+    mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
+
+    // get static peripheral object
+    int i2c_id = i2c_find(args[ARG_NEW_id].u_obj);
+    const machine_hard_i2c_obj_t *self = &machine_hard_i2c_obj[i2c_id];
+
+    if (args[ARG_NEW_scl].u_obj != MP_OBJ_NULL) {
+        self->i2c->init.scl_pin = args[ARG_NEW_scl].u_obj;
+    } else {
+        nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
+                  "I2C SCL Pin not set"));
+    }
+
+    if (args[ARG_NEW_sda].u_obj != MP_OBJ_NULL) {
+        self->i2c->init.sda_pin = args[ARG_NEW_sda].u_obj;
+    } else {
+        nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
+                  "I2C SDA Pin not set"));
+    }
+
+    self->i2c->init.freq = HAL_TWI_FREQ_100_Kbps;
+
+    hal_twi_master_init(self->i2c->instance, &self->i2c->init);
+
+    return MP_OBJ_FROM_PTR(self);
+}
+
+#include <stdio.h>
+
+int machine_hard_i2c_readfrom(mp_obj_base_t *self_in, uint16_t addr, uint8_t *dest, size_t len, bool stop) {
+    machine_hard_i2c_obj_t *self = (machine_hard_i2c_obj_t *)self_in;
+
+    hal_twi_master_rx(self->i2c->instance, addr, len, dest, stop);
+
+    return 0;
+}
+
+int machine_hard_i2c_writeto(mp_obj_base_t *self_in, uint16_t addr, const uint8_t *src, size_t len, bool stop) {
+    machine_hard_i2c_obj_t *self = (machine_hard_i2c_obj_t *)self_in;
+
+    hal_twi_master_tx(self->i2c->instance, addr, len, src, stop);
+
+    return 0;
+}
+
+STATIC const mp_machine_i2c_p_t machine_hard_i2c_p = {
+    .readfrom = machine_hard_i2c_readfrom,
+    .writeto = machine_hard_i2c_writeto,
+};
+
+STATIC const mp_obj_type_t machine_hard_i2c_type = {
+    { &mp_type_type },
+    .name = MP_QSTR_I2C,
+    .print = machine_hard_i2c_print,
+    .make_new = machine_hard_i2c_make_new,
+    .protocol = &machine_hard_i2c_p,
+    .locals_dict = (mp_obj_dict_t*)&mp_machine_soft_i2c_locals_dict,
+};
+
+#endif // MICROPY_PY_MACHINE_I2C
diff --git a/ports/nrf/modules/machine/i2c.h b/ports/nrf/modules/machine/i2c.h
new file mode 100644
index 0000000000..cd8d4507c3
--- /dev/null
+++ b/ports/nrf/modules/machine/i2c.h
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef I2C_H__
+#define I2C_H__
+
+#include "hal_twi.h"
+
+extern const mp_obj_type_t machine_i2c_type;
+
+void i2c_init0(void);
+
+#endif // I2C_H__
diff --git a/ports/nrf/modules/machine/led.c b/ports/nrf/modules/machine/led.c
new file mode 100644
index 0000000000..3eec949e9e
--- /dev/null
+++ b/ports/nrf/modules/machine/led.c
@@ -0,0 +1,159 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013-2016 Damien P. George
+ * Copyright (c) 2015 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "py/runtime.h"
+
+#include "mphalport.h"
+#include "led.h"
+#include "mpconfigboard.h"
+
+#if MICROPY_HW_HAS_LED
+
+#define LED_OFF(led) {(MICROPY_HW_LED_PULLUP) ? hal_gpio_pin_set(0, led) : hal_gpio_pin_clear(0, led); }
+#define LED_ON(led) {(MICROPY_HW_LED_PULLUP) ? hal_gpio_pin_clear(0, led) : hal_gpio_pin_set(0, led); }
+
+typedef struct _pyb_led_obj_t {
+    mp_obj_base_t base;
+    mp_uint_t led_id;
+    mp_uint_t hw_pin;
+    uint8_t hw_pin_port;
+} pyb_led_obj_t;
+
+STATIC const pyb_led_obj_t pyb_led_obj[] = {
+#if MICROPY_HW_LED_TRICOLOR
+    {{&pyb_led_type}, PYB_LED_RED, MICROPY_HW_LED_RED},
+    {{&pyb_led_type}, PYB_LED_GREEN, MICROPY_HW_LED_GREEN},
+    {{&pyb_led_type}, PYB_LED_BLUE, MICROPY_HW_LED_BLUE},
+#elif (MICROPY_HW_LED_COUNT == 1)
+    {{&pyb_led_type}, PYB_LED1, MICROPY_HW_LED1},
+#elif (MICROPY_HW_LED_COUNT == 2)
+    {{&pyb_led_type}, PYB_LED1, MICROPY_HW_LED1},
+    {{&pyb_led_type}, PYB_LED2, MICROPY_HW_LED2},
+#else
+    {{&pyb_led_type}, PYB_LED1, MICROPY_HW_LED1},
+    {{&pyb_led_type}, PYB_LED2, MICROPY_HW_LED2},
+    {{&pyb_led_type}, PYB_LED3, MICROPY_HW_LED3},
+    {{&pyb_led_type}, PYB_LED4, MICROPY_HW_LED4},
+#endif
+};
+
+#define NUM_LEDS MP_ARRAY_SIZE(pyb_led_obj)
+
+void led_init(void) {
+    for (uint8_t i = 0; i < NUM_LEDS; i++) {
+        LED_OFF(pyb_led_obj[i].hw_pin);
+        hal_gpio_cfg_pin(0, pyb_led_obj[i].hw_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED);
+    }
+}
+
+void led_state(pyb_led_obj_t * led_obj, int state) {
+    if (state == 1) {
+        LED_ON(led_obj->hw_pin);
+    } else {
+        LED_OFF(led_obj->hw_pin);
+    }
+}
+
+void led_toggle(pyb_led_obj_t * led_obj) {
+    hal_gpio_pin_toggle(0, led_obj->hw_pin);
+}
+
+
+
+/******************************************************************************/
+/* MicroPython bindings                                                      */
+
+void led_obj_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) {
+    pyb_led_obj_t *self = self_in;
+    mp_printf(print, "LED(%lu)", self->led_id);
+}
+
+/// \classmethod \constructor(id)
+/// Create an LED object associated with the given LED:
+///
+///   - `id` is the LED number, 1-4.
+STATIC mp_obj_t led_obj_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args) {
+    // check arguments
+    mp_arg_check_num(n_args, n_kw, 1, 1, false);
+
+    // get led number
+    mp_int_t led_id = mp_obj_get_int(args[0]);
+
+    // check led number
+    if (!(1 <= led_id && led_id <= NUM_LEDS)) {
+        nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "LED(%d) does not exist", led_id));
+    }
+
+    // return static led object
+    return (mp_obj_t)&pyb_led_obj[led_id - 1];
+}
+
+/// \method on()
+/// Turn the LED on.
+mp_obj_t led_obj_on(mp_obj_t self_in) {
+    pyb_led_obj_t *self = self_in;
+    led_state(self, 1);
+    return mp_const_none;
+}
+
+/// \method off()
+/// Turn the LED off.
+mp_obj_t led_obj_off(mp_obj_t self_in) {
+    pyb_led_obj_t *self = self_in;
+    led_state(self, 0);
+    return mp_const_none;
+}
+
+/// \method toggle()
+/// Toggle the LED between on and off.
+mp_obj_t led_obj_toggle(mp_obj_t self_in) {
+    pyb_led_obj_t *self = self_in;
+    led_toggle(self);
+    return mp_const_none;
+}
+
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(led_obj_on_obj, led_obj_on);
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(led_obj_off_obj, led_obj_off);
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(led_obj_toggle_obj, led_obj_toggle);
+
+STATIC const mp_rom_map_elem_t led_locals_dict_table[] = {
+    { MP_ROM_QSTR(MP_QSTR_on), MP_ROM_PTR(&led_obj_on_obj) },
+    { MP_ROM_QSTR(MP_QSTR_off), MP_ROM_PTR(&led_obj_off_obj) },
+    { MP_ROM_QSTR(MP_QSTR_toggle), MP_ROM_PTR(&led_obj_toggle_obj) },
+};
+
+STATIC MP_DEFINE_CONST_DICT(led_locals_dict, led_locals_dict_table);
+
+const mp_obj_type_t pyb_led_type = {
+    { &mp_type_type },
+    .name = MP_QSTR_LED,
+    .print = led_obj_print,
+    .make_new = led_obj_make_new,
+    .locals_dict = (mp_obj_dict_t*)&led_locals_dict,
+};
+
+#endif // MICROPY_HW_HAS_LED
diff --git a/ports/nrf/modules/machine/led.h b/ports/nrf/modules/machine/led.h
new file mode 100644
index 0000000000..c9e20ce4c8
--- /dev/null
+++ b/ports/nrf/modules/machine/led.h
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef LED_H
+#define LED_H
+
+typedef enum {
+#if MICROPY_HW_LED_TRICOLOR
+    PYB_LED_RED = 1,
+    PYB_LED_GREEN = 2,
+    PYB_LED_BLUE = 3
+#elif (MICROPY_HW_LED_COUNT == 1)
+    PYB_LED1 = 1,
+#elif (MICROPY_HW_LED_COUNT == 2)
+    PYB_LED1 = 1,
+    PYB_LED2 = 2,
+#else
+    PYB_LED1 = 1,
+    PYB_LED2 = 2,
+    PYB_LED3 = 3,
+    PYB_LED4 = 4
+#endif
+} pyb_led_t;
+
+void led_init(void);
+
+extern const mp_obj_type_t pyb_led_type;
+
+#endif // LED_H
diff --git a/ports/nrf/modules/machine/modmachine.c b/ports/nrf/modules/machine/modmachine.c
new file mode 100644
index 0000000000..ad536a37db
--- /dev/null
+++ b/ports/nrf/modules/machine/modmachine.c
@@ -0,0 +1,244 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013-2015 Damien P. George
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#include <stdio.h>
+
+#include "modmachine.h"
+#include "py/gc.h"
+#include "py/runtime.h"
+#include "py/mphal.h"
+#include "extmod/machine_mem.h"
+#include "extmod/machine_pulse.h"
+#include "extmod/machine_i2c.h"
+#include "lib/utils/pyexec.h"
+#include "lib/oofatfs/ff.h"
+#include "lib/oofatfs/diskio.h"
+#include "gccollect.h"
+#include "pin.h"
+#include "uart.h"
+#include "spi.h"
+#include "i2c.h"
+#include "timer.h"
+#if MICROPY_PY_MACHINE_HW_PWM
+#include "pwm.h"
+#endif
+#if MICROPY_PY_MACHINE_ADC
+#include "adc.h"
+#endif
+#if MICROPY_PY_MACHINE_TEMP
+#include "temp.h"
+#endif
+#if MICROPY_PY_MACHINE_RTC
+#include "rtc.h"
+#endif
+
+#define PYB_RESET_HARD      (0)
+#define PYB_RESET_WDT       (1)
+#define PYB_RESET_SOFT      (2)
+#define PYB_RESET_LOCKUP    (3)
+#define PYB_RESET_POWER_ON  (16)
+#define PYB_RESET_LPCOMP    (17)
+#define PYB_RESET_DIF       (18)
+#define PYB_RESET_NFC       (19)
+
+STATIC uint32_t reset_cause;
+
+void machine_init(void) {
+    uint32_t state = NRF_POWER->RESETREAS;
+    if (state & POWER_RESETREAS_RESETPIN_Msk) {
+        reset_cause = PYB_RESET_HARD;
+    } else if (state & POWER_RESETREAS_DOG_Msk) {
+        reset_cause = PYB_RESET_WDT;
+    } else if (state & POWER_RESETREAS_SREQ_Msk) {
+        reset_cause = PYB_RESET_SOFT;
+    } else if (state & POWER_RESETREAS_LOCKUP_Msk) {
+        reset_cause = PYB_RESET_LOCKUP;
+    } else if (state & POWER_RESETREAS_OFF_Msk) {
+        reset_cause = PYB_RESET_POWER_ON;
+    } else if (state & POWER_RESETREAS_LPCOMP_Msk) {
+        reset_cause = PYB_RESET_LPCOMP;
+    } else if (state & POWER_RESETREAS_DIF_Msk) {
+        reset_cause = PYB_RESET_DIF;
+#if NRF52
+    } else if (state & POWER_RESETREAS_NFC_Msk) {
+        reset_cause = PYB_RESET_NFC;
+#endif
+    }
+
+    // clear reset reason
+    NRF_POWER->RESETREAS = (1 << reset_cause);
+}
+
+// machine.info([dump_alloc_table])
+// Print out lots of information about the board.
+STATIC mp_obj_t machine_info(mp_uint_t n_args, const mp_obj_t *args) {
+    // to print info about memory
+    {
+        printf("_etext=%p\n", &_etext);
+        printf("_sidata=%p\n", &_sidata);
+        printf("_sdata=%p\n", &_sdata);
+        printf("_edata=%p\n", &_edata);
+        printf("_sbss=%p\n", &_sbss);
+        printf("_ebss=%p\n", &_ebss);
+        printf("_estack=%p\n", &_estack);
+        printf("_ram_start=%p\n", &_ram_start);
+        printf("_heap_start=%p\n", &_heap_start);
+        printf("_heap_end=%p\n", &_heap_end);
+        printf("_ram_end=%p\n", &_ram_end);
+    }
+
+    // qstr info
+    {
+        mp_uint_t n_pool, n_qstr, n_str_data_bytes, n_total_bytes;
+        qstr_pool_info(&n_pool, &n_qstr, &n_str_data_bytes, &n_total_bytes);
+        printf("qstr:\n  n_pool=" UINT_FMT "\n  n_qstr=" UINT_FMT "\n  n_str_data_bytes=" UINT_FMT "\n  n_total_bytes=" UINT_FMT "\n", n_pool, n_qstr, n_str_data_bytes, n_total_bytes);
+    }
+
+    // GC info
+    {
+        gc_info_t info;
+        gc_info(&info);
+        printf("GC:\n");
+        printf("  " UINT_FMT " total\n", info.total);
+        printf("  " UINT_FMT " : " UINT_FMT "\n", info.used, info.free);
+        printf("  1=" UINT_FMT " 2=" UINT_FMT " m=" UINT_FMT "\n", info.num_1block, info.num_2block, info.max_block);
+    }
+
+    if (n_args == 1) {
+        // arg given means dump gc allocation table
+        gc_dump_alloc_table();
+    }
+
+    return mp_const_none;
+}
+MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(machine_info_obj, 0, 1, machine_info);
+
+// Resets the pyboard in a manner similar to pushing the external RESET button.
+STATIC mp_obj_t machine_reset(void) {
+    NVIC_SystemReset();
+    return mp_const_none;
+}
+MP_DEFINE_CONST_FUN_OBJ_0(machine_reset_obj, machine_reset);
+
+STATIC mp_obj_t machine_soft_reset(void) {
+    pyexec_system_exit = PYEXEC_FORCED_EXIT;
+    nlr_raise(mp_obj_new_exception(&mp_type_SystemExit));
+}
+MP_DEFINE_CONST_FUN_OBJ_0(machine_soft_reset_obj, machine_soft_reset);
+
+STATIC mp_obj_t machine_sleep(void) {
+    __WFE();
+    return mp_const_none;
+}
+MP_DEFINE_CONST_FUN_OBJ_0(machine_sleep_obj, machine_sleep);
+
+STATIC mp_obj_t machine_deepsleep(void) {
+    __WFI();
+    return mp_const_none;
+}
+MP_DEFINE_CONST_FUN_OBJ_0(machine_deepsleep_obj, machine_deepsleep);
+
+STATIC mp_obj_t machine_reset_cause(void) {
+    return MP_OBJ_NEW_SMALL_INT(reset_cause);
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_0(machine_reset_cause_obj, machine_reset_cause);
+
+STATIC mp_obj_t machine_enable_irq(void) {
+#ifndef BLUETOOTH_SD
+    __enable_irq();
+#else
+
+#endif
+    return mp_const_none;
+}
+MP_DEFINE_CONST_FUN_OBJ_0(machine_enable_irq_obj, machine_enable_irq);
+
+// Resets the pyboard in a manner similar to pushing the external RESET button.
+STATIC mp_obj_t machine_disable_irq(void) {
+#ifndef BLUETOOTH_SD
+    __disable_irq();
+#else
+
+#endif
+    return mp_const_none;
+}
+MP_DEFINE_CONST_FUN_OBJ_0(machine_disable_irq_obj, machine_disable_irq);
+
+STATIC const mp_rom_map_elem_t machine_module_globals_table[] = {
+    { MP_ROM_QSTR(MP_QSTR___name__),           MP_ROM_QSTR(MP_QSTR_umachine) },
+    { MP_ROM_QSTR(MP_QSTR_info),               MP_ROM_PTR(&machine_info_obj) },
+    { MP_ROM_QSTR(MP_QSTR_reset),              MP_ROM_PTR(&machine_reset_obj) },
+    { MP_ROM_QSTR(MP_QSTR_soft_reset),         MP_ROM_PTR(&machine_soft_reset_obj) },
+    { MP_ROM_QSTR(MP_QSTR_enable_irq),         MP_ROM_PTR(&machine_enable_irq_obj) },
+    { MP_ROM_QSTR(MP_QSTR_disable_irq),        MP_ROM_PTR(&machine_disable_irq_obj) },
+#if MICROPY_HW_ENABLE_RNG
+    { MP_ROM_QSTR(MP_QSTR_rng),                MP_ROM_PTR(&pyb_rng_get_obj) },
+#endif
+    { MP_ROM_QSTR(MP_QSTR_sleep),              MP_ROM_PTR(&machine_sleep_obj) },
+    { MP_ROM_QSTR(MP_QSTR_deepsleep),          MP_ROM_PTR(&machine_deepsleep_obj) },
+    { MP_ROM_QSTR(MP_QSTR_reset_cause),        MP_ROM_PTR(&machine_reset_cause_obj) },
+    { MP_ROM_QSTR(MP_QSTR_Pin),                MP_ROM_PTR(&pin_type) },
+    { MP_ROM_QSTR(MP_QSTR_UART),               MP_ROM_PTR(&machine_hard_uart_type) },
+#if MICROPY_PY_MACHINE_HW_SPI
+    { MP_ROM_QSTR(MP_QSTR_SPI),                MP_ROM_PTR(&machine_hard_spi_type) },
+#endif
+#if MICROPY_PY_MACHINE_I2C
+    { MP_ROM_QSTR(MP_QSTR_I2C),                MP_ROM_PTR(&machine_i2c_type) },
+#endif
+#if MICROPY_PY_MACHINE_ADC
+    { MP_ROM_QSTR(MP_QSTR_ADC),                MP_ROM_PTR(&machine_adc_type) },
+#endif
+#if MICROPY_PY_MACHINE_RTC
+    { MP_ROM_QSTR(MP_QSTR_RTC),                MP_ROM_PTR(&machine_rtc_type) },
+#endif
+#if MICROPY_PY_MACHINE_TIMER
+    { MP_ROM_QSTR(MP_QSTR_Timer),              MP_ROM_PTR(&machine_timer_type) },
+#endif
+#if MICROPY_PY_MACHINE_HW_PWM
+    { MP_ROM_QSTR(MP_QSTR_PWM),                MP_ROM_PTR(&machine_hard_pwm_type) },
+#endif
+#if MICROPY_PY_MACHINE_TEMP
+    { MP_ROM_QSTR(MP_QSTR_Temp),               MP_ROM_PTR(&machine_temp_type) },
+#endif
+    { MP_ROM_QSTR(MP_QSTR_HARD_RESET),         MP_ROM_INT(PYB_RESET_HARD) },
+    { MP_ROM_QSTR(MP_QSTR_WDT_RESET),          MP_ROM_INT(PYB_RESET_WDT) },
+    { MP_ROM_QSTR(MP_QSTR_SOFT_RESET),         MP_ROM_INT(PYB_RESET_SOFT) },
+    { MP_ROM_QSTR(MP_QSTR_LOCKUP_RESET),       MP_ROM_INT(PYB_RESET_LOCKUP) },
+    { MP_ROM_QSTR(MP_QSTR_PWRON_RESET),        MP_ROM_INT(PYB_RESET_POWER_ON) },
+    { MP_ROM_QSTR(MP_QSTR_LPCOMP_RESET),       MP_ROM_INT(PYB_RESET_LPCOMP) },
+    { MP_ROM_QSTR(MP_QSTR_DEBUG_IF_RESET),     MP_ROM_INT(PYB_RESET_DIF) },
+#if NRF52
+    { MP_ROM_QSTR(MP_QSTR_NFC_RESET),          MP_ROM_INT(PYB_RESET_NFC) },
+#endif
+};
+
+STATIC MP_DEFINE_CONST_DICT(machine_module_globals, machine_module_globals_table);
+
+const mp_obj_module_t machine_module = {
+    .base = { &mp_type_module },
+    .globals = (mp_obj_dict_t*)&machine_module_globals,
+};
+
diff --git a/ports/nrf/modules/machine/modmachine.h b/ports/nrf/modules/machine/modmachine.h
new file mode 100644
index 0000000000..76b4ad7242
--- /dev/null
+++ b/ports/nrf/modules/machine/modmachine.h
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013-2015 Damien P. George
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef __MICROPY_INCLUDED_NRF5_MODMACHINE_H__
+#define __MICROPY_INCLUDED_NRF5_MODMACHINE_H__
+
+#include "py/mpstate.h"
+#include "py/nlr.h"
+#include "py/obj.h"
+
+void machine_init(void);
+
+MP_DECLARE_CONST_FUN_OBJ_VAR_BETWEEN(machine_info_obj);
+MP_DECLARE_CONST_FUN_OBJ_0(machine_reset_obj);
+MP_DECLARE_CONST_FUN_OBJ_0(machine_sleep_obj);
+MP_DECLARE_CONST_FUN_OBJ_0(machine_deepsleep_obj);
+
+#endif // __MICROPY_INCLUDED_NRF5_MODMACHINE_H__
diff --git a/ports/nrf/modules/machine/pin.c b/ports/nrf/modules/machine/pin.c
new file mode 100644
index 0000000000..62160d785f
--- /dev/null
+++ b/ports/nrf/modules/machine/pin.c
@@ -0,0 +1,695 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+
+#include <stdio.h>
+#include <stdint.h>
+#include <string.h>
+
+#include "py/nlr.h"
+#include "py/runtime.h"
+#include "py/mphal.h"
+#include "pin.h"
+
+/// \moduleref pyb
+/// \class Pin - control I/O pins
+///
+/// A pin is the basic object to control I/O pins.  It has methods to set
+/// the mode of the pin (input, output, etc) and methods to get and set the
+/// digital logic level.  For analog control of a pin, see the ADC class.
+///
+/// Usage Model:
+///
+/// All Board Pins are predefined as pyb.Pin.board.Name
+///
+///     x1_pin = pyb.Pin.board.X1
+///
+///     g = pyb.Pin(pyb.Pin.board.X1, pyb.Pin.IN)
+///
+/// CPU pins which correspond to the board pins are available
+/// as `pyb.cpu.Name`. For the CPU pins, the names are the port letter
+/// followed by the pin number. On the PYBv1.0, `pyb.Pin.board.X1` and
+/// `pyb.Pin.cpu.B6` are the same pin.
+///
+/// You can also use strings:
+///
+///     g = pyb.Pin('X1', pyb.Pin.OUT_PP)
+///
+/// Users can add their own names:
+///
+///     MyMapperDict = { 'LeftMotorDir' : pyb.Pin.cpu.C12 }
+///     pyb.Pin.dict(MyMapperDict)
+///     g = pyb.Pin("LeftMotorDir", pyb.Pin.OUT_OD)
+///
+/// and can query mappings
+///
+///     pin = pyb.Pin("LeftMotorDir")
+///
+/// Users can also add their own mapping function:
+///
+///     def MyMapper(pin_name):
+///        if pin_name == "LeftMotorDir":
+///            return pyb.Pin.cpu.A0
+///
+///     pyb.Pin.mapper(MyMapper)
+///
+/// So, if you were to call: `pyb.Pin("LeftMotorDir", pyb.Pin.OUT_PP)`
+/// then `"LeftMotorDir"` is passed directly to the mapper function.
+///
+/// To summarise, the following order determines how things get mapped into
+/// an ordinal pin number:
+///
+/// 1. Directly specify a pin object
+/// 2. User supplied mapping function
+/// 3. User supplied mapping (object must be usable as a dictionary key)
+/// 4. Supply a string which matches a board pin
+/// 5. Supply a string which matches a CPU port/pin
+///
+/// You can set `pyb.Pin.debug(True)` to get some debug information about
+/// how a particular object gets mapped to a pin.
+
+// Pin class variables
+STATIC bool pin_class_debug;
+
+// Forward declare function
+void gpio_irq_event_callback(hal_gpio_event_channel_t channel);
+
+void pin_init0(void) {
+    MP_STATE_PORT(pin_class_mapper) = mp_const_none;
+    MP_STATE_PORT(pin_class_map_dict) = mp_const_none;
+    pin_class_debug = false;
+
+    hal_gpio_register_callback(gpio_irq_event_callback);
+}
+
+// C API used to convert a user-supplied pin name into an ordinal pin number.
+const pin_obj_t *pin_find(mp_obj_t user_obj) {
+    const pin_obj_t *pin_obj;
+
+    // If a pin was provided, then use it
+    if (MP_OBJ_IS_TYPE(user_obj, &pin_type)) {
+        pin_obj = user_obj;
+        if (pin_class_debug) {
+            printf("Pin map passed pin ");
+            mp_obj_print((mp_obj_t)pin_obj, PRINT_STR);
+            printf("\n");
+        }
+        return pin_obj;
+    }
+
+    if (MP_STATE_PORT(pin_class_mapper) != mp_const_none) {
+        pin_obj = mp_call_function_1(MP_STATE_PORT(pin_class_mapper), user_obj);
+        if (pin_obj != mp_const_none) {
+            if (!MP_OBJ_IS_TYPE(pin_obj, &pin_type)) {
+                mp_raise_ValueError("Pin.mapper didn't return a Pin object");
+            }
+            if (pin_class_debug) {
+                printf("Pin.mapper maps ");
+                mp_obj_print(user_obj, PRINT_REPR);
+                printf(" to ");
+                mp_obj_print((mp_obj_t)pin_obj, PRINT_STR);
+                printf("\n");
+            }
+            return pin_obj;
+        }
+        // The pin mapping function returned mp_const_none, fall through to
+        // other lookup methods.
+    }
+
+    if (MP_STATE_PORT(pin_class_map_dict) != mp_const_none) {
+        mp_map_t *pin_map_map = mp_obj_dict_get_map(MP_STATE_PORT(pin_class_map_dict));
+        mp_map_elem_t *elem = mp_map_lookup(pin_map_map, user_obj, MP_MAP_LOOKUP);
+        if (elem != NULL && elem->value != NULL) {
+            pin_obj = elem->value;
+            if (pin_class_debug) {
+                printf("Pin.map_dict maps ");
+                mp_obj_print(user_obj, PRINT_REPR);
+                printf(" to ");
+                mp_obj_print((mp_obj_t)pin_obj, PRINT_STR);
+                printf("\n");
+            }
+            return pin_obj;
+        }
+    }
+
+    // See if the pin name matches a board pin
+    pin_obj = pin_find_named_pin(&pin_board_pins_locals_dict, user_obj);
+    if (pin_obj) {
+        if (pin_class_debug) {
+            printf("Pin.board maps ");
+            mp_obj_print(user_obj, PRINT_REPR);
+            printf(" to ");
+            mp_obj_print((mp_obj_t)pin_obj, PRINT_STR);
+            printf("\n");
+        }
+        return pin_obj;
+    }
+
+    // See if the pin name matches a cpu pin
+    pin_obj = pin_find_named_pin(&pin_cpu_pins_locals_dict, user_obj);
+    if (pin_obj) {
+        if (pin_class_debug) {
+            printf("Pin.cpu maps ");
+            mp_obj_print(user_obj, PRINT_REPR);
+            printf(" to ");
+            mp_obj_print((mp_obj_t)pin_obj, PRINT_STR);
+            printf("\n");
+        }
+        return pin_obj;
+    }
+
+    nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "pin '%s' not a valid pin identifier", mp_obj_str_get_str(user_obj)));
+}
+
+/// \method __str__()
+/// Return a string describing the pin object.
+STATIC void pin_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) {
+    pin_obj_t *self = self_in;
+
+    // pin name
+    mp_printf(print, "Pin(Pin.cpu.%q, mode=Pin.", self->name);
+    mp_printf(print, "port=0x%x, ", self->port);
+    mp_printf(print, "pin=0x%x, ", self->pin);
+    mp_printf(print, "pin_mask=0x%x,", self->pin_mask);
+/*
+    uint32_t mode = pin_get_mode(self);
+
+    if (mode == GPIO_MODE_ANALOG) {
+        // analog
+        mp_print_str(print, "ANALOG)");
+
+    } else {
+        // IO mode
+        bool af = false;
+        qstr mode_qst;
+        if (mode == GPIO_MODE_INPUT) {
+            mode_qst = MP_QSTR_IN;
+        } else if (mode == GPIO_MODE_OUTPUT_PP) {
+            mode_qst = MP_QSTR_OUT;
+        } else if (mode == GPIO_MODE_OUTPUT_OD) {
+            mode_qst = MP_QSTR_OPEN_DRAIN;
+        } else {
+            af = true;
+            if (mode == GPIO_MODE_AF_PP) {
+                mode_qst = MP_QSTR_ALT;
+            } else {
+                mode_qst = MP_QSTR_ALT_OPEN_DRAIN;
+            }
+        }
+        mp_print_str(print, qstr_str(mode_qst));
+        // pull mode
+        qstr pull_qst = MP_QSTR_NULL;
+        uint32_t pull = pin_get_pull(self);
+        if (pull == GPIO_PULLUP) {
+            pull_qst = MP_QSTR_PULL_UP;
+        } else if (pull == GPIO_PULLDOWN) {
+            pull_qst = MP_QSTR_PULL_DOWN;
+        }
+        if (pull_qst != MP_QSTR_NULL) {
+            mp_printf(print, ", pull=Pin.%q", pull_qst);
+        }
+        // AF mode
+        if (af) {
+            mp_uint_t af_idx = pin_get_af(self);
+            const pin_af_obj_t *af_obj = pin_find_af_by_index(self, af_idx);
+            if (af_obj == NULL) {
+                mp_printf(print, ", af=%d)", af_idx);
+            } else {
+                mp_printf(print, ", af=Pin.%q)", af_obj->name);
+            }
+        } else {
+*/
+            mp_print_str(print, ")");
+   /*     }
+    }*/
+
+}
+
+STATIC mp_obj_t pin_obj_init_helper(const pin_obj_t *pin, mp_uint_t n_args, const mp_obj_t *args, mp_map_t *kw_args);
+
+/// \classmethod \constructor(id, ...)
+/// Create a new Pin object associated with the id.  If additional arguments are given,
+/// they are used to initialise the pin.  See `init`.
+STATIC mp_obj_t pin_make_new(const mp_obj_type_t *type, mp_uint_t n_args, mp_uint_t n_kw, const mp_obj_t *args) {
+    mp_arg_check_num(n_args, n_kw, 1, MP_OBJ_FUN_ARGS_MAX, true);
+
+    // Run an argument through the mapper and return the result.
+    const pin_obj_t *pin = pin_find(args[0]);
+
+    if (n_args > 1 || n_kw > 0) {
+        // pin mode given, so configure this GPIO
+        mp_map_t kw_args;
+        mp_map_init_fixed_table(&kw_args, n_kw, args + n_args);
+        pin_obj_init_helper(pin, n_args - 1, args + 1, &kw_args);
+    }
+
+    return (mp_obj_t)pin;
+}
+
+// fast method for getting/setting pin value
+STATIC mp_obj_t pin_call(mp_obj_t self_in, mp_uint_t n_args, mp_uint_t n_kw, const mp_obj_t *args) {
+    mp_arg_check_num(n_args, n_kw, 0, 1, false);
+    pin_obj_t *self = self_in;
+    if (n_args == 0) {
+        // get pin
+        return MP_OBJ_NEW_SMALL_INT(mp_hal_pin_read(self));
+    } else {
+        // set pin
+        mp_hal_pin_write(self, mp_obj_is_true(args[0]));
+        return mp_const_none;
+    }
+}
+
+STATIC mp_obj_t pin_off(mp_obj_t self_in) {
+    pin_obj_t *self = self_in;
+    mp_hal_pin_low(self);
+    return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(pin_off_obj, pin_off);
+
+STATIC mp_obj_t pin_on(mp_obj_t self_in) {
+    pin_obj_t *self = self_in;
+    mp_hal_pin_high(self);
+    return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(pin_on_obj, pin_on);
+
+/// \classmethod mapper([fun])
+/// Get or set the pin mapper function.
+STATIC mp_obj_t pin_mapper(mp_uint_t n_args, const mp_obj_t *args) {
+    if (n_args > 1) {
+        MP_STATE_PORT(pin_class_mapper) = args[1];
+        return mp_const_none;
+    }
+    return MP_STATE_PORT(pin_class_mapper);
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pin_mapper_fun_obj, 1, 2, pin_mapper);
+STATIC MP_DEFINE_CONST_CLASSMETHOD_OBJ(pin_mapper_obj, (mp_obj_t)&pin_mapper_fun_obj);
+
+/// \classmethod dict([dict])
+/// Get or set the pin mapper dictionary.
+STATIC mp_obj_t pin_map_dict(mp_uint_t n_args, const mp_obj_t *args) {
+    if (n_args > 1) {
+        MP_STATE_PORT(pin_class_map_dict) = args[1];
+        return mp_const_none;
+    }
+    return MP_STATE_PORT(pin_class_map_dict);
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pin_map_dict_fun_obj, 1, 2, pin_map_dict);
+STATIC MP_DEFINE_CONST_CLASSMETHOD_OBJ(pin_map_dict_obj, (mp_obj_t)&pin_map_dict_fun_obj);
+
+/// \classmethod af_list()
+/// Returns an array of alternate functions available for this pin.
+STATIC mp_obj_t pin_af_list(mp_obj_t self_in) {
+    pin_obj_t *self = self_in;
+    mp_obj_t result = mp_obj_new_list(0, NULL);
+
+    const pin_af_obj_t *af = self->af;
+    for (mp_uint_t i = 0; i < self->num_af; i++, af++) {
+        mp_obj_list_append(result, (mp_obj_t)af);
+    }
+    return result;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(pin_af_list_obj, pin_af_list);
+
+/// \classmethod debug([state])
+/// Get or set the debugging state (`True` or `False` for on or off).
+STATIC mp_obj_t pin_debug(mp_uint_t n_args, const mp_obj_t *args) {
+    if (n_args > 1) {
+        pin_class_debug = mp_obj_is_true(args[1]);
+        return mp_const_none;
+    }
+    return mp_obj_new_bool(pin_class_debug);
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pin_debug_fun_obj, 1, 2, pin_debug);
+STATIC MP_DEFINE_CONST_CLASSMETHOD_OBJ(pin_debug_obj, (mp_obj_t)&pin_debug_fun_obj);
+
+// init(mode, pull=None, af=-1, *, value, alt)
+STATIC mp_obj_t pin_obj_init_helper(const pin_obj_t *self, mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+    static const mp_arg_t allowed_args[] = {
+        { MP_QSTR_mode, MP_ARG_REQUIRED | MP_ARG_INT },
+        { MP_QSTR_pull, MP_ARG_OBJ, {.u_obj = mp_const_none}},
+        { MP_QSTR_af, MP_ARG_INT, {.u_int = -1}}, // legacy
+        { MP_QSTR_value, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL}},
+        { MP_QSTR_alt, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1}},
+    };
+
+    // parse args
+    mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
+    mp_arg_parse_all(n_args, pos_args, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
+
+    // get pull mode
+    uint pull = HAL_GPIO_PULL_DISABLED;
+    if (args[1].u_obj != mp_const_none) {
+        pull = mp_obj_get_int(args[1].u_obj);
+    }
+
+    // if given, set the pin value before initialising to prevent glitches
+    if (args[3].u_obj != MP_OBJ_NULL) {
+        mp_hal_pin_write(self, mp_obj_is_true(args[3].u_obj));
+    }
+
+    // get io mode
+    uint mode = args[0].u_int;
+    if (mode == HAL_GPIO_MODE_OUTPUT || mode == HAL_GPIO_MODE_INPUT) {
+        hal_gpio_cfg_pin(self->port, self->pin, mode, pull);
+    } else {
+        nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "invalid pin mode: %d", mode));
+    }
+
+    return mp_const_none;
+}
+
+STATIC mp_obj_t pin_obj_init(mp_uint_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
+    return pin_obj_init_helper(args[0], n_args - 1, args + 1, kw_args);
+}
+MP_DEFINE_CONST_FUN_OBJ_KW(pin_init_obj, 1, pin_obj_init);
+
+/// \method value([value])
+/// Get or set the digital logic level of the pin:
+///
+///   - With no argument, return 0 or 1 depending on the logic level of the pin.
+///   - With `value` given, set the logic level of the pin.  `value` can be
+///   anything that converts to a boolean.  If it converts to `True`, the pin
+///   is set high, otherwise it is set low.
+STATIC mp_obj_t pin_value(mp_uint_t n_args, const mp_obj_t *args) {
+    return pin_call(args[0], n_args - 1, 0, args + 1);
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pin_value_obj, 1, 2, pin_value);
+
+/// \method low()
+/// Set the pin to a low logic level.
+STATIC mp_obj_t pin_low(mp_obj_t self_in) {
+    pin_obj_t *self = self_in;
+    mp_hal_pin_low(self);
+    return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(pin_low_obj, pin_low);
+
+/// \method high()
+/// Set the pin to a high logic level.
+STATIC mp_obj_t pin_high(mp_obj_t self_in) {
+    pin_obj_t *self = self_in;
+    mp_hal_pin_high(self);
+    return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(pin_high_obj, pin_high);
+
+/// \method name()
+/// Get the pin name.
+STATIC mp_obj_t pin_name(mp_obj_t self_in) {
+    pin_obj_t *self = self_in;
+    return MP_OBJ_NEW_QSTR(self->name);
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(pin_name_obj, pin_name);
+
+/// \method names()
+/// Returns the cpu and board names for this pin.
+STATIC mp_obj_t pin_names(mp_obj_t self_in) {
+    pin_obj_t *self = self_in;
+    mp_obj_t result = mp_obj_new_list(0, NULL);
+    mp_obj_list_append(result, MP_OBJ_NEW_QSTR(self->name));
+
+    mp_map_t *map = mp_obj_dict_get_map((mp_obj_t)&pin_board_pins_locals_dict);
+    mp_map_elem_t *elem = map->table;
+
+    for (mp_uint_t i = 0; i < map->used; i++, elem++) {
+        if (elem->value == self) {
+            mp_obj_list_append(result, elem->key);
+        }
+    }
+    return result;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(pin_names_obj, pin_names);
+
+/// \method port()
+/// Get the pin port.
+STATIC mp_obj_t pin_port(mp_obj_t self_in) {
+    pin_obj_t *self = self_in;
+    return MP_OBJ_NEW_SMALL_INT(self->port);
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(pin_port_obj, pin_port);
+
+/// \method pin()
+/// Get the pin number.
+STATIC mp_obj_t pin_pin(mp_obj_t self_in) {
+    pin_obj_t *self = self_in;
+    return MP_OBJ_NEW_SMALL_INT(self->pin);
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(pin_pin_obj, pin_pin);
+
+/// \method gpio()
+/// Returns the base address of the GPIO block associated with this pin.
+STATIC mp_obj_t pin_gpio(mp_obj_t self_in) {
+    pin_obj_t *self = self_in;
+    return MP_OBJ_NEW_SMALL_INT((mp_int_t)self->gpio);
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(pin_gpio_obj, pin_gpio);
+
+/// \method mode()
+/// Returns the currently configured mode of the pin. The integer returned
+/// will match one of the allowed constants for the mode argument to the init
+/// function.
+STATIC mp_obj_t pin_mode(mp_obj_t self_in) {
+    return mp_const_none; // TODO: MP_OBJ_NEW_SMALL_INT(pin_get_mode(self_in));
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(pin_mode_obj, pin_mode);
+
+/// \method pull()
+/// Returns the currently configured pull of the pin. The integer returned
+/// will match one of the allowed constants for the pull argument to the init
+/// function.
+STATIC mp_obj_t pin_pull(mp_obj_t self_in) {
+    return mp_const_none; // TODO: MP_OBJ_NEW_SMALL_INT(pin_get_pull(self_in));
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(pin_pull_obj, pin_pull);
+
+/// \method af()
+/// Returns the currently configured alternate-function of the pin. The
+/// integer returned will match one of the allowed constants for the af
+/// argument to the init function.
+STATIC mp_obj_t pin_af(mp_obj_t self_in) {
+    return mp_const_none; // TODO: MP_OBJ_NEW_SMALL_INT(pin_get_af(self_in));
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(pin_af_obj, pin_af);
+
+STATIC mp_obj_t pin_irq(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+    static const mp_arg_t allowed_args[] = {
+        { MP_QSTR_handler, MP_ARG_OBJ,  {.u_obj = mp_const_none} },
+        { MP_QSTR_trigger, MP_ARG_INT,  {.u_int = HAL_GPIO_POLARITY_EVENT_TOGGLE} },
+        { MP_QSTR_wake,    MP_ARG_BOOL, {.u_bool = false} },
+    };
+    pin_obj_t *self = MP_OBJ_TO_PTR(pos_args[0]);
+    mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
+    mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
+
+    (void)self;
+
+    // return the irq object
+    return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_KW(pin_irq_obj, 1, pin_irq);
+
+
+STATIC const mp_rom_map_elem_t pin_locals_dict_table[] = {
+    // instance methods
+    { MP_ROM_QSTR(MP_QSTR_init),    MP_ROM_PTR(&pin_init_obj) },
+    { MP_ROM_QSTR(MP_QSTR_value),   MP_ROM_PTR(&pin_value_obj) },
+    { MP_ROM_QSTR(MP_QSTR_off),     MP_ROM_PTR(&pin_off_obj) },
+    { MP_ROM_QSTR(MP_QSTR_on),      MP_ROM_PTR(&pin_on_obj) },
+    { MP_ROM_QSTR(MP_QSTR_low),     MP_ROM_PTR(&pin_low_obj) },
+    { MP_ROM_QSTR(MP_QSTR_high),    MP_ROM_PTR(&pin_high_obj) },
+    { MP_ROM_QSTR(MP_QSTR_name),    MP_ROM_PTR(&pin_name_obj) },
+    { MP_ROM_QSTR(MP_QSTR_names),   MP_ROM_PTR(&pin_names_obj) },
+    { MP_ROM_QSTR(MP_QSTR_af_list), MP_ROM_PTR(&pin_af_list_obj) },
+    { MP_ROM_QSTR(MP_QSTR_port),    MP_ROM_PTR(&pin_port_obj) },
+    { MP_ROM_QSTR(MP_QSTR_pin),     MP_ROM_PTR(&pin_pin_obj) },
+    { MP_ROM_QSTR(MP_QSTR_gpio),    MP_ROM_PTR(&pin_gpio_obj) },
+    { MP_ROM_QSTR(MP_QSTR_mode),    MP_ROM_PTR(&pin_mode_obj) },
+    { MP_ROM_QSTR(MP_QSTR_pull),    MP_ROM_PTR(&pin_pull_obj) },
+    { MP_ROM_QSTR(MP_QSTR_af),      MP_ROM_PTR(&pin_af_obj) },
+    { MP_ROM_QSTR(MP_QSTR_irq),     MP_ROM_PTR(&pin_irq_obj) },
+
+    // class methods
+    { MP_ROM_QSTR(MP_QSTR_mapper),  MP_ROM_PTR(&pin_mapper_obj) },
+    { MP_ROM_QSTR(MP_QSTR_dict),    MP_ROM_PTR(&pin_map_dict_obj) },
+    { MP_ROM_QSTR(MP_QSTR_debug),   MP_ROM_PTR(&pin_debug_obj) },
+
+    // class attributes
+    { MP_ROM_QSTR(MP_QSTR_board),   MP_ROM_PTR(&pin_board_pins_obj_type) },
+    { MP_ROM_QSTR(MP_QSTR_cpu),     MP_ROM_PTR(&pin_cpu_pins_obj_type) },
+
+    // class constants
+    { MP_ROM_QSTR(MP_QSTR_IN),        MP_ROM_INT(HAL_GPIO_MODE_INPUT) },
+    { MP_ROM_QSTR(MP_QSTR_OUT),       MP_ROM_INT(HAL_GPIO_MODE_OUTPUT) },
+/*
+    { MP_ROM_QSTR(MP_QSTR_OPEN_DRAIN),     MP_ROM_INT(GPIO_MODE_OUTPUT_OD) },
+    { MP_ROM_QSTR(MP_QSTR_ALT),            MP_ROM_INT(GPIO_MODE_AF_PP) },
+    { MP_ROM_QSTR(MP_QSTR_ALT_OPEN_DRAIN), MP_ROM_INT(GPIO_MODE_AF_OD) },
+    { MP_ROM_QSTR(MP_QSTR_ANALOG),         MP_ROM_INT(GPIO_MODE_ANALOG) },
+*/
+    { MP_ROM_QSTR(MP_QSTR_PULL_DISABLED), MP_ROM_INT(HAL_GPIO_PULL_DISABLED) },
+    { MP_ROM_QSTR(MP_QSTR_PULL_UP),       MP_ROM_INT(HAL_GPIO_PULL_UP) },
+    { MP_ROM_QSTR(MP_QSTR_PULL_DOWN),     MP_ROM_INT(HAL_GPIO_PULL_DOWN) },
+
+    // IRQ triggers, can be or'd together
+    { MP_ROM_QSTR(MP_QSTR_IRQ_RISING),    MP_ROM_INT(HAL_GPIO_POLARITY_EVENT_LOW_TO_HIGH) },
+    { MP_ROM_QSTR(MP_QSTR_IRQ_FALLING),   MP_ROM_INT(HAL_GPIO_POLARITY_EVENT_HIGH_TO_LOW) },
+/*
+    // legacy class constants
+    { MP_ROM_QSTR(MP_QSTR_OUT_PP),    MP_ROM_INT(GPIO_MODE_OUTPUT_PP) },
+    { MP_ROM_QSTR(MP_QSTR_OUT_OD),    MP_ROM_INT(GPIO_MODE_OUTPUT_OD) },
+    { MP_ROM_QSTR(MP_QSTR_AF_PP),     MP_ROM_INT(GPIO_MODE_AF_PP) },
+    { MP_ROM_QSTR(MP_QSTR_AF_OD),     MP_ROM_INT(GPIO_MODE_AF_OD) },
+    { MP_ROM_QSTR(MP_QSTR_PULL_NONE), MP_ROM_INT(GPIO_NOPULL) },
+*/
+#include "genhdr/pins_af_const.h"
+};
+
+STATIC MP_DEFINE_CONST_DICT(pin_locals_dict, pin_locals_dict_table);
+
+const mp_obj_type_t pin_type = {
+    { &mp_type_type },
+    .name = MP_QSTR_Pin,
+    .print = pin_print,
+    .make_new = pin_make_new,
+    .call = pin_call,
+    .locals_dict = (mp_obj_dict_t*)&pin_locals_dict,
+};
+
+/// \moduleref pyb
+/// \class PinAF - Pin Alternate Functions
+///
+/// A Pin represents a physical pin on the microcprocessor. Each pin
+/// can have a variety of functions (GPIO, I2C SDA, etc). Each PinAF
+/// object represents a particular function for a pin.
+///
+/// Usage Model:
+///
+///     x3 = pyb.Pin.board.X3
+///     x3_af = x3.af_list()
+///
+/// x3_af will now contain an array of PinAF objects which are availble on
+/// pin X3.
+///
+/// For the pyboard, x3_af would contain:
+///     [Pin.AF1_TIM2, Pin.AF2_TIM5, Pin.AF3_TIM9, Pin.AF7_USART2]
+///
+/// Normally, each peripheral would configure the af automatically, but sometimes
+/// the same function is available on multiple pins, and having more control
+/// is desired.
+///
+/// To configure X3 to expose TIM2_CH3, you could use:
+///    pin = pyb.Pin(pyb.Pin.board.X3, mode=pyb.Pin.AF_PP, af=pyb.Pin.AF1_TIM2)
+/// or:
+///    pin = pyb.Pin(pyb.Pin.board.X3, mode=pyb.Pin.AF_PP, af=1)
+
+/// \method __str__()
+/// Return a string describing the alternate function.
+STATIC void pin_af_obj_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) {
+    pin_af_obj_t *self = self_in;
+    mp_printf(print, "Pin.%q", self->name);
+}
+
+/// \method index()
+/// Return the alternate function index.
+STATIC mp_obj_t pin_af_index(mp_obj_t self_in) {
+    pin_af_obj_t *af = self_in;
+    return MP_OBJ_NEW_SMALL_INT(af->idx);
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(pin_af_index_obj, pin_af_index);
+
+/// \method name()
+/// Return the name of the alternate function.
+STATIC mp_obj_t pin_af_name(mp_obj_t self_in) {
+    pin_af_obj_t *af = self_in;
+    return MP_OBJ_NEW_QSTR(af->name);
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(pin_af_name_obj, pin_af_name);
+
+/// \method reg()
+/// Return the base register associated with the peripheral assigned to this
+/// alternate function.
+STATIC mp_obj_t pin_af_reg(mp_obj_t self_in) {
+    pin_af_obj_t *af = self_in;
+    return MP_OBJ_NEW_SMALL_INT((mp_uint_t)af->reg);
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(pin_af_reg_obj, pin_af_reg);
+
+STATIC const mp_rom_map_elem_t pin_af_locals_dict_table[] = {
+    { MP_ROM_QSTR(MP_QSTR_index),   MP_ROM_PTR(&pin_af_index_obj) },
+    { MP_ROM_QSTR(MP_QSTR_name),    MP_ROM_PTR(&pin_af_name_obj) },
+    { MP_ROM_QSTR(MP_QSTR_reg),     MP_ROM_PTR(&pin_af_reg_obj) },
+};
+STATIC MP_DEFINE_CONST_DICT(pin_af_locals_dict, pin_af_locals_dict_table);
+
+const mp_obj_type_t pin_af_type = {
+    { &mp_type_type },
+    .name = MP_QSTR_PinAF,
+    .print = pin_af_obj_print,
+    .locals_dict = (mp_obj_dict_t*)&pin_af_locals_dict,
+};
+
+/******************************************************************************/
+// Pin IRQ object
+
+void gpio_irq_event_callback(hal_gpio_event_channel_t channel) {
+    // printf("### gpio irq received on channel %d\n", (uint16_t)channel);
+}
+
+typedef struct _pin_irq_obj_t {
+    mp_obj_base_t base;
+    pin_obj_t pin;
+} pin_irq_obj_t;
+
+// STATIC const mp_obj_type_t pin_irq_type;
+
+/*STATIC mp_obj_t pin_irq_call(mp_obj_t self_in, size_t n_args, size_t n_kw, const mp_obj_t *args) {
+    pin_irq_obj_t *self = self_in;
+    (void)self;
+    return mp_const_none;
+}*/
+
+/*STATIC mp_obj_t pin_irq_trigger(size_t n_args, const mp_obj_t *args) {
+    pin_irq_obj_t *self = args[0];
+    (void)self;
+    return mp_const_none;
+}*/
+// STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pin_irq_trigger_obj, 1, 2, pin_irq_trigger);
+
+// STATIC const mp_rom_map_elem_t pin_irq_locals_dict_table[] = {
+//     { MP_ROM_QSTR(MP_QSTR_trigger),  MP_ROM_PTR(&pin_irq_trigger_obj) },
+// };
+
+// STATIC MP_DEFINE_CONST_DICT(pin_irq_locals_dict, pin_irq_locals_dict_table);
+
+/*STATIC const mp_obj_type_t pin_irq_type = {
+    { &mp_type_type },
+    .name = MP_QSTR_IRQ,
+    .call = pin_irq_call,
+    .locals_dict = (mp_obj_dict_t*)&pin_irq_locals_dict,
+};*/
diff --git a/ports/nrf/modules/machine/pin.h b/ports/nrf/modules/machine/pin.h
new file mode 100644
index 0000000000..1935a0d263
--- /dev/null
+++ b/ports/nrf/modules/machine/pin.h
@@ -0,0 +1,102 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef __MICROPY_INCLUDED_NRF5_PIN_H__
+#define __MICROPY_INCLUDED_NRF5_PIN_H__
+
+// This file requires pin_defs_xxx.h (which has port specific enums and
+// defines, so we include it here. It should never be included directly
+
+#include MICROPY_PIN_DEFS_PORT_H
+#include "py/obj.h"
+
+typedef struct {
+  mp_obj_base_t base;
+  qstr name;
+  uint8_t idx;
+  uint8_t fn;
+  uint8_t unit;
+  uint8_t type;
+
+  union {
+    void          *reg;
+
+    PIN_DEFS_PORT_AF_UNION
+  };
+} pin_af_obj_t;
+
+typedef struct {
+  mp_obj_base_t base;
+  qstr name;
+  uint32_t port   : 4;
+  uint32_t pin    : 5;      // Some ARM processors use 32 bits/PORT
+  uint32_t num_af : 4;
+  uint32_t adc_channel : 5; // Some ARM processors use 32 bits/PORT
+  uint32_t adc_num  : 3;    // 1 bit per ADC
+  uint32_t pin_mask;
+  pin_gpio_t *gpio;
+  const pin_af_obj_t *af;
+  uint32_t pull;
+} pin_obj_t;
+
+extern const mp_obj_type_t pin_type;
+extern const mp_obj_type_t pin_af_type;
+
+typedef struct {
+  const char *name;
+  const pin_obj_t *pin;
+} pin_named_pin_t;
+
+extern const pin_named_pin_t pin_board_pins[];
+extern const pin_named_pin_t pin_cpu_pins[];
+
+//extern pin_map_obj_t pin_map_obj;
+
+typedef struct {
+    mp_obj_base_t base;
+    qstr name;
+    const pin_named_pin_t *named_pins;
+} pin_named_pins_obj_t;
+
+extern const mp_obj_type_t pin_board_pins_obj_type;
+extern const mp_obj_type_t pin_cpu_pins_obj_type;
+
+extern const mp_obj_dict_t pin_cpu_pins_locals_dict;
+extern const mp_obj_dict_t pin_board_pins_locals_dict;
+
+MP_DECLARE_CONST_FUN_OBJ_KW(pin_init_obj);
+
+void pin_init0(void);
+uint32_t pin_get_mode(const pin_obj_t *pin);
+uint32_t pin_get_pull(const pin_obj_t *pin);
+uint32_t pin_get_af(const pin_obj_t *pin);
+const pin_obj_t *pin_find(mp_obj_t user_obj);
+const pin_obj_t *pin_find_named_pin(const mp_obj_dict_t *named_pins, mp_obj_t name);
+const pin_af_obj_t *pin_find_af(const pin_obj_t *pin, uint8_t fn, uint8_t unit);
+const pin_af_obj_t *pin_find_af_by_index(const pin_obj_t *pin, mp_uint_t af_idx);
+const pin_af_obj_t *pin_find_af_by_name(const pin_obj_t *pin, const char *name);
+
+#endif // __MICROPY_INCLUDED_NRF5_PIN_H__
diff --git a/ports/nrf/modules/machine/pwm.c b/ports/nrf/modules/machine/pwm.c
new file mode 100644
index 0000000000..eaba96606f
--- /dev/null
+++ b/ports/nrf/modules/machine/pwm.c
@@ -0,0 +1,332 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <stdio.h>
+#include <string.h>
+
+#include "py/nlr.h"
+#include "py/runtime.h"
+#include "py/mphal.h"
+
+#if MICROPY_PY_MACHINE_HW_PWM
+
+#include "pin.h"
+#include "genhdr/pins.h"
+#include "pwm.h"
+
+#if NRF52
+// Use PWM hardware.
+#include "hal_pwm.h"
+#endif
+
+#ifdef MICROPY_HW_PWM0_NAME
+PWM_HandleTypeDef PWMHandle0 = {.instance = NULL};
+#endif
+
+STATIC const pyb_pwm_obj_t machine_pwm_obj[] = {
+    #ifdef MICROPY_HW_PWM0_NAME
+    {{&machine_hard_pwm_type}, &PWMHandle0},
+    #else
+    {{&machine_hard_pwm_type}, NULL},
+    #endif
+};
+
+void pwm_init0(void) {
+    // reset the PWM handles
+    #ifdef MICROPY_HW_PWM0_NAME
+    memset(&PWMHandle0, 0, sizeof(PWM_HandleTypeDef));
+    PWMHandle0.instance = PWM0;
+    #endif
+}
+
+STATIC int pwm_find(mp_obj_t id) {
+    if (MP_OBJ_IS_STR(id)) {
+        // given a string id
+        const char *port = mp_obj_str_get_str(id);
+        if (0) {
+        #ifdef MICROPY_HW_PWM0_NAME
+        } else if (strcmp(port, MICROPY_HW_PWM0_NAME) == 0) {
+            return 1;
+        #endif
+        }
+        nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
+            "PWM(%s) does not exist", port));
+    } else {
+        // given an integer id
+        int pwm_id = mp_obj_get_int(id);
+        if (pwm_id >= 0 && pwm_id <= MP_ARRAY_SIZE(machine_pwm_obj)
+            && machine_pwm_obj[pwm_id].pwm != NULL) {
+            return pwm_id;
+        }
+        nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
+            "PWM(%d) does not exist", pwm_id));
+    }
+}
+
+void pwm_init(PWM_HandleTypeDef *pwm) {
+	// start pwm
+	hal_pwm_start(pwm->instance);
+}
+
+void pwm_deinit(PWM_HandleTypeDef *pwm) {
+	// stop pwm
+	hal_pwm_stop(pwm->instance);
+}
+
+STATIC void pwm_print(const mp_print_t *print, PWM_HandleTypeDef *pwm, bool legacy) {
+    uint pwm_num = 0; // default to PWM0
+    mp_printf(print, "PWM(%u)", pwm_num);
+}
+
+/******************************************************************************/
+/* MicroPython bindings for machine API                                       */
+
+// for make_new
+enum {
+    ARG_NEW_id,
+    ARG_NEW_pin,
+    ARG_NEW_freq,
+    ARG_NEW_period,
+    ARG_NEW_duty,
+    ARG_NEW_pulse_width,
+    ARG_NEW_mode
+};
+
+// for init
+enum {
+    ARG_INIT_pin
+};
+
+// for freq
+enum {
+    ARG_FREQ_freq
+};
+
+STATIC mp_obj_t machine_hard_pwm_make_new(mp_arg_val_t *args);
+STATIC void machine_hard_pwm_init(mp_obj_t self, mp_arg_val_t *args);
+STATIC void machine_hard_pwm_deinit(mp_obj_t self);
+STATIC mp_obj_t machine_hard_pwm_freq(mp_obj_t self, mp_arg_val_t *args);
+
+/* common code for both soft and hard implementations *************************/
+
+STATIC mp_obj_t machine_pwm_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) {
+    static const mp_arg_t allowed_args[] = {
+        { MP_QSTR_id,       MP_ARG_OBJ, {.u_obj = MP_OBJ_NEW_SMALL_INT(-1)} },
+        { MP_QSTR_pin,      MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
+        { MP_QSTR_freq,     MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
+        { MP_QSTR_period,   MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
+        { MP_QSTR_duty,     MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
+        { MP_QSTR_pulse_width, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
+        { MP_QSTR_mode,     MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
+    };
+
+    // parse args
+    mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
+    mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
+
+    if (args[ARG_NEW_id].u_obj == MP_OBJ_NEW_SMALL_INT(-1)) {
+        // TODO: implement soft PWM
+        // return machine_soft_pwm_make_new(args);
+        return mp_const_none;
+    } else {
+        // hardware peripheral id given
+        return machine_hard_pwm_make_new(args);
+    }
+}
+
+STATIC mp_obj_t machine_pwm_init(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+    static const mp_arg_t allowed_args[] = {
+        { MP_QSTR_pin, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }
+    };
+
+    // parse args
+    mp_obj_t self = pos_args[0];
+    mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
+    mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
+
+    // dispatch to specific implementation
+    if (mp_obj_get_type(self) == &machine_hard_pwm_type) {
+        machine_hard_pwm_init(self, args);
+    }
+
+    return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_KW(machine_pwm_init_obj, 1, machine_pwm_init);
+
+STATIC mp_obj_t machine_pwm_deinit(mp_obj_t self) {
+    // dispatch to specific implementation
+    if (mp_obj_get_type(self) == &machine_hard_pwm_type) {
+        machine_hard_pwm_deinit(self);
+    }
+    return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_pwm_deinit_obj, machine_pwm_deinit);
+
+STATIC mp_obj_t machine_pwm_freq(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+    static const mp_arg_t allowed_args[] = {
+        { MP_QSTR_freq, MP_ARG_INT, {.u_int = -1} },
+    };
+
+    mp_obj_t self = pos_args[0];
+    mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
+    mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
+
+    if (mp_obj_get_type(self) == &machine_hard_pwm_type) {
+        machine_hard_pwm_freq(self, args);
+    } else {
+        // soft pwm
+    }
+
+    return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_KW(mp_machine_pwm_freq_obj, 1, machine_pwm_freq);
+
+STATIC mp_obj_t machine_pwm_period(size_t n_args, const mp_obj_t *args) {
+    return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(mp_machine_pwm_period_obj, 1, 2, machine_pwm_period);
+
+STATIC mp_obj_t machine_pwm_duty(size_t n_args, const mp_obj_t *args) {
+    return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(mp_machine_pwm_duty_obj, 1, 2, machine_pwm_duty);
+
+STATIC const mp_rom_map_elem_t machine_pwm_locals_dict_table[] = {
+    { MP_ROM_QSTR(MP_QSTR_init),   MP_ROM_PTR(&machine_pwm_init_obj) },
+    { MP_ROM_QSTR(MP_QSTR_deinit), MP_ROM_PTR(&machine_pwm_deinit_obj) },
+
+    { MP_ROM_QSTR(MP_QSTR_freq),   MP_ROM_PTR(&mp_machine_pwm_freq_obj) },
+    { MP_ROM_QSTR(MP_QSTR_period), MP_ROM_PTR(&mp_machine_pwm_period_obj) },
+    { MP_ROM_QSTR(MP_QSTR_duty),   MP_ROM_PTR(&mp_machine_pwm_duty_obj) },
+
+    { MP_ROM_QSTR(MP_QSTR_FREQ_16MHZ),    MP_ROM_INT(HAL_PWM_FREQ_16Mhz) },
+    { MP_ROM_QSTR(MP_QSTR_FREQ_8MHZ),     MP_ROM_INT(HAL_PWM_FREQ_8Mhz) },
+    { MP_ROM_QSTR(MP_QSTR_FREQ_4MHZ),     MP_ROM_INT(HAL_PWM_FREQ_4Mhz) },
+    { MP_ROM_QSTR(MP_QSTR_FREQ_2MHZ),     MP_ROM_INT(HAL_PWM_FREQ_2Mhz) },
+    { MP_ROM_QSTR(MP_QSTR_FREQ_1MHZ),     MP_ROM_INT(HAL_PWM_FREQ_1Mhz) },
+    { MP_ROM_QSTR(MP_QSTR_FREQ_500KHZ),   MP_ROM_INT(HAL_PWM_FREQ_500khz) },
+    { MP_ROM_QSTR(MP_QSTR_FREQ_250KHZ),   MP_ROM_INT(HAL_PWM_FREQ_250khz) },
+    { MP_ROM_QSTR(MP_QSTR_FREQ_125KHZ),   MP_ROM_INT(HAL_PWM_FREQ_125khz) },
+
+    { MP_ROM_QSTR(MP_QSTR_MODE_LOW_HIGH), MP_ROM_INT(HAL_PWM_MODE_LOW_HIGH) },
+    { MP_ROM_QSTR(MP_QSTR_MODE_HIGH_LOW), MP_ROM_INT(HAL_PWM_MODE_HIGH_LOW) },
+};
+
+STATIC MP_DEFINE_CONST_DICT(machine_pwm_locals_dict, machine_pwm_locals_dict_table);
+
+/* code for hard implementation ***********************************************/
+
+STATIC const machine_hard_pwm_obj_t machine_hard_pwm_obj[] = {
+    {{&machine_hard_pwm_type}, &machine_pwm_obj[0]},
+};
+
+STATIC void machine_hard_pwm_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) {
+    machine_hard_pwm_obj_t *self = self_in;
+    pwm_print(print, self->pyb->pwm, false);
+}
+
+STATIC mp_obj_t machine_hard_pwm_make_new(mp_arg_val_t *args) {
+    // get static peripheral object
+    int pwm_id = pwm_find(args[ARG_NEW_id].u_obj);
+    const machine_hard_pwm_obj_t *self = &machine_hard_pwm_obj[pwm_id];
+
+    // check if PWM pin is set
+    if (args[ARG_NEW_pin].u_obj != MP_OBJ_NULL) {
+        pin_obj_t *pin_obj = args[ARG_NEW_pin].u_obj;
+        self->pyb->pwm->init.pwm_pin = pin_obj->pin;
+    } else {
+        // TODO: raise exception.
+    }
+
+    if (args[ARG_NEW_freq].u_obj != MP_OBJ_NULL) {
+        self->pyb->pwm->init.freq = mp_obj_get_int(args[ARG_NEW_freq].u_obj);
+    } else {
+        self->pyb->pwm->init.freq = 50; // 50 Hz by default.
+    }
+
+    if (args[ARG_NEW_period].u_obj != MP_OBJ_NULL) {
+        self->pyb->pwm->init.period = mp_obj_get_int(args[ARG_NEW_period].u_obj);
+    } else {
+	    nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
+                  "PWM period has to be within 16000 frequence cycles", self->pyb->pwm->init.period));
+    }
+
+    if (args[ARG_NEW_duty].u_obj != MP_OBJ_NULL) {
+        self->pyb->pwm->init.duty = mp_obj_get_int(args[ARG_NEW_duty].u_obj);
+    } else {
+        self->pyb->pwm->init.duty = 50; // 50% by default.
+    }
+
+    if (args[ARG_NEW_pulse_width].u_obj != MP_OBJ_NULL) {
+        self->pyb->pwm->init.pulse_width = mp_obj_get_int(args[ARG_NEW_pulse_width].u_obj);
+    } else {
+        self->pyb->pwm->init.pulse_width = 0;
+    }
+
+    if (args[ARG_NEW_mode].u_obj != MP_OBJ_NULL) {
+        self->pyb->pwm->init.mode = mp_obj_get_int(args[ARG_NEW_mode].u_obj);
+    } else {
+        self->pyb->pwm->init.mode = HAL_PWM_MODE_HIGH_LOW;
+    }
+
+    hal_pwm_init(self->pyb->pwm->instance, &self->pyb->pwm->init);
+
+    return MP_OBJ_FROM_PTR(self);
+}
+
+STATIC void machine_hard_pwm_init(mp_obj_t self_in, mp_arg_val_t *args) {
+	machine_hard_pwm_obj_t *self = self_in;
+	pwm_init(self->pyb->pwm);
+}
+
+STATIC void machine_hard_pwm_deinit(mp_obj_t self_in) {
+    machine_hard_pwm_obj_t *self = self_in;
+    pwm_deinit(self->pyb->pwm);
+}
+
+STATIC mp_obj_t machine_hard_pwm_freq(mp_obj_t self_in, mp_arg_val_t *args) {
+    machine_hard_pwm_obj_t *self = self_in;
+
+    if (args[ARG_FREQ_freq].u_int != -1) {
+	    self->pyb->pwm->init.freq = args[ARG_FREQ_freq].u_int;
+        hal_pwm_init(self->pyb->pwm->instance, &self->pyb->pwm->init);
+	} else {
+        return MP_OBJ_NEW_SMALL_INT(self->pyb->pwm->init.freq);
+    }
+
+    return mp_const_none;
+}
+
+
+const mp_obj_type_t machine_hard_pwm_type = {
+    { &mp_type_type },
+    .name = MP_QSTR_PWM,
+    .print = machine_hard_pwm_print,
+    .make_new = machine_pwm_make_new,
+    .locals_dict = (mp_obj_dict_t*)&machine_pwm_locals_dict,
+};
+
+#endif // MICROPY_PY_MACHINE_HW_PWM
diff --git a/ports/nrf/modules/machine/pwm.h b/ports/nrf/modules/machine/pwm.h
new file mode 100644
index 0000000000..85184bae01
--- /dev/null
+++ b/ports/nrf/modules/machine/pwm.h
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "hal_pwm.h"
+
+typedef struct _pyb_pwm_obj_t {
+    mp_obj_base_t base;
+    PWM_HandleTypeDef *pwm;
+} pyb_pwm_obj_t;
+
+typedef struct _machine_hard_pwm_obj_t {
+    mp_obj_base_t base;
+    const pyb_pwm_obj_t *pyb;
+} machine_hard_pwm_obj_t;
+
+void pwm_init0(void);
+
+extern const mp_obj_type_t machine_hard_pwm_type;
diff --git a/ports/nrf/modules/machine/rtc.c b/ports/nrf/modules/machine/rtc.c
new file mode 100644
index 0000000000..cbf9e62114
--- /dev/null
+++ b/ports/nrf/modules/machine/rtc.c
@@ -0,0 +1,178 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <stdio.h>
+#include <string.h>
+
+#include "py/nlr.h"
+#include "py/runtime.h"
+#include "py/mphal.h"
+#include "rtc.h"
+#include "hal_rtc.h"
+
+#if MICROPY_PY_MACHINE_RTC
+
+typedef struct _machine_rtc_obj_t {
+    mp_obj_base_t    base;
+    hal_rtc_conf_t * p_config;
+    mp_obj_t callback;
+    mp_int_t period;
+    mp_int_t mode;
+} machine_rtc_obj_t;
+
+static hal_rtc_conf_t rtc_config0 = {.id = 0};
+static hal_rtc_conf_t rtc_config1 = {.id = 1};
+#if NRF52
+static hal_rtc_conf_t rtc_config2 = {.id = 2};
+#endif
+
+STATIC machine_rtc_obj_t machine_rtc_obj[] = {
+    {{&machine_rtc_type}, &rtc_config0},
+    {{&machine_rtc_type}, &rtc_config1},
+#if NRF52
+    {{&machine_rtc_type}, &rtc_config2},
+#endif
+};
+
+STATIC void hal_interrupt_handle(uint8_t id) {
+    machine_rtc_obj_t * self = &machine_rtc_obj[id];;
+
+    mp_call_function_1(self->callback, self);
+
+    if (self != NULL) {
+        hal_rtc_stop(id);
+        if (self->mode == 1) {
+            hal_rtc_start(id);
+        }
+    }
+}
+
+void rtc_init0(void) {
+    hal_rtc_callback_set(hal_interrupt_handle);
+}
+
+STATIC int rtc_find(mp_obj_t id) {
+    // given an integer id
+    int rtc_id = mp_obj_get_int(id);
+    if (rtc_id >= 0 && rtc_id <= MP_ARRAY_SIZE(machine_rtc_obj)
+        && machine_rtc_obj[rtc_id].p_config != NULL) {
+        return rtc_id;
+    }
+    nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
+        "RTC(%d) does not exist", rtc_id));
+}
+
+STATIC void rtc_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) {
+    machine_rtc_obj_t *self = o;
+    mp_printf(print, "RTC(%u)", self->p_config->id);
+}
+
+/******************************************************************************/
+/* MicroPython bindings for machine API                                       */
+
+STATIC mp_obj_t machine_rtc_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) {
+    static const mp_arg_t allowed_args[] = {
+        { MP_QSTR_id,       MP_ARG_OBJ, {.u_obj = MP_OBJ_NEW_SMALL_INT(-1)} },
+        { MP_QSTR_period,   MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 1000} },
+        { MP_QSTR_mode,     MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 1} },
+        { MP_QSTR_callback, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} },
+    };
+
+    // parse args
+    mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
+    mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
+
+    // get static peripheral object
+    int rtc_id = rtc_find(args[0].u_obj);
+
+    // unconst machine object in order to set a callback.
+    machine_rtc_obj_t * self = (machine_rtc_obj_t *)&machine_rtc_obj[rtc_id];
+
+    self->p_config->period = args[1].u_int;
+
+    self->mode = args[2].u_int;
+
+    if (args[3].u_obj != mp_const_none) {
+        self->callback = args[3].u_obj;
+    }
+
+#ifdef NRF51
+    self->p_config->irq_priority = 3;
+#else
+    self->p_config->irq_priority = 6;
+#endif
+
+    hal_rtc_init(self->p_config);
+
+    return MP_OBJ_FROM_PTR(self);
+}
+
+/// \method start(period)
+/// Start the RTC timer. Timeout occurs after number of periods
+/// in the configured frequency has been reached.
+///
+STATIC mp_obj_t machine_rtc_start(mp_obj_t self_in) {
+    machine_rtc_obj_t * self = MP_OBJ_TO_PTR(self_in);
+
+    hal_rtc_start(self->p_config->id);
+
+    return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_rtc_start_obj, machine_rtc_start);
+
+/// \method stop()
+/// Stop the RTC timer.
+///
+STATIC mp_obj_t machine_rtc_stop(mp_obj_t self_in) {
+    machine_rtc_obj_t * self = MP_OBJ_TO_PTR(self_in);
+
+    hal_rtc_stop(self->p_config->id);
+
+    return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_rtc_stop_obj, machine_rtc_stop);
+
+
+STATIC const mp_rom_map_elem_t machine_rtc_locals_dict_table[] = {
+    { MP_ROM_QSTR(MP_QSTR_start), MP_ROM_PTR(&machine_rtc_start_obj) },
+    { MP_ROM_QSTR(MP_QSTR_stop),  MP_ROM_PTR(&machine_rtc_stop_obj) },
+
+    // constants
+    { MP_ROM_QSTR(MP_QSTR_ONESHOT),  MP_ROM_INT(0) },
+    { MP_ROM_QSTR(MP_QSTR_PERIODIC), MP_ROM_INT(1) },
+};
+
+STATIC MP_DEFINE_CONST_DICT(machine_rtc_locals_dict, machine_rtc_locals_dict_table);
+
+const mp_obj_type_t machine_rtc_type = {
+    { &mp_type_type },
+    .name = MP_QSTR_RTC,
+    .print = rtc_print,
+    .make_new = machine_rtc_make_new,
+    .locals_dict = (mp_obj_dict_t*)&machine_rtc_locals_dict
+};
+
+#endif // MICROPY_PY_MACHINE_RTC
diff --git a/ports/nrf/modules/machine/rtc.h b/ports/nrf/modules/machine/rtc.h
new file mode 100644
index 0000000000..6bf6efa6ad
--- /dev/null
+++ b/ports/nrf/modules/machine/rtc.h
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef RTC_H__
+#define RTC_H__
+
+#include "hal_rtc.h"
+
+extern const mp_obj_type_t machine_rtc_type;
+
+void rtc_init0(void);
+
+#endif // RTC_H__
diff --git a/ports/nrf/modules/machine/spi.c b/ports/nrf/modules/machine/spi.c
new file mode 100644
index 0000000000..0a82f1db52
--- /dev/null
+++ b/ports/nrf/modules/machine/spi.c
@@ -0,0 +1,377 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <stdio.h>
+#include <string.h>
+
+#include "py/nlr.h"
+#include "py/runtime.h"
+#include "py/mphal.h"
+#include "extmod/machine_spi.h"
+#include "pin.h"
+#include "genhdr/pins.h"
+#include "spi.h"
+#include "hal_spi.h"
+
+#if MICROPY_PY_MACHINE_HW_SPI
+
+/// \moduleref pyb
+/// \class SPI - a master-driven serial protocol
+///
+/// SPI is a serial protocol that is driven by a master.  At the physical level
+/// there are 3 lines: SCK, MOSI, MISO.
+///
+/// See usage model of I2C; SPI is very similar.  Main difference is
+/// parameters to init the SPI bus:
+///
+///     from pyb import SPI
+///     spi = SPI(1, SPI.MASTER, baudrate=600000, polarity=1, phase=0, crc=0x7)
+///
+/// Only required parameter is mode, SPI.MASTER or SPI.SLAVE.  Polarity can be
+/// 0 or 1, and is the level the idle clock line sits at.  Phase can be 0 or 1
+/// to sample data on the first or second clock edge respectively.  Crc can be
+/// None for no CRC, or a polynomial specifier.
+///
+/// Additional method for SPI:
+///
+///     data = spi.send_recv(b'1234')        # send 4 bytes and receive 4 bytes
+///     buf = bytearray(4)
+///     spi.send_recv(b'1234', buf)          # send 4 bytes and receive 4 into buf
+///     spi.send_recv(buf, buf)              # send/recv 4 bytes from/to buf
+
+SPI_HandleTypeDef SPIHandle0 = {.instance = NULL};
+SPI_HandleTypeDef SPIHandle1 = {.instance = NULL};
+#if NRF52
+SPI_HandleTypeDef SPIHandle2 = {.instance = NULL};
+#if NRF52840_XXAA
+SPI_HandleTypeDef SPIHandle3 = {.instance = NULL}; // 32 Mbs master only
+#endif // NRF52840_XXAA
+#endif // NRF52
+
+STATIC const machine_hard_spi_obj_t machine_hard_spi_obj[] = {
+    {{&machine_hard_spi_type}, &SPIHandle0},
+    {{&machine_hard_spi_type}, &SPIHandle1},
+#if NRF52
+    {{&machine_hard_spi_type}, &SPIHandle2},
+#if NRF52840_XXAA
+    {{&machine_hard_spi_type}, &SPIHandle3},
+#endif // NRF52840_XXAA
+#endif // NRF52
+
+};
+
+void spi_init0(void) {
+    // reset the SPI handles
+    memset(&SPIHandle0, 0, sizeof(SPI_HandleTypeDef));
+    SPIHandle0.instance = SPI_BASE(0);
+    memset(&SPIHandle1, 0, sizeof(SPI_HandleTypeDef));
+    SPIHandle1.instance = SPI_BASE(1);
+#if NRF52
+    memset(&SPIHandle2, 0, sizeof(SPI_HandleTypeDef));
+    SPIHandle2.instance = SPI_BASE(2);
+#if NRF52840_XXAA
+    memset(&SPIHandle3, 0, sizeof(SPI_HandleTypeDef));
+    SPIHandle3.instance = SPI_BASE(3);
+#endif // NRF52840_XXAA
+#endif // NRF52
+}
+
+STATIC int spi_find(mp_obj_t id) {
+    if (MP_OBJ_IS_STR(id)) {
+        // given a string id
+        const char *port = mp_obj_str_get_str(id);
+        if (0) {
+        #ifdef MICROPY_HW_SPI0_NAME
+        } else if (strcmp(port, MICROPY_HW_SPI0_NAME) == 0) {
+            return 1;
+        #endif
+        }
+        nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
+            "SPI(%s) does not exist", port));
+    } else {
+        // given an integer id
+        int spi_id = mp_obj_get_int(id);
+        if (spi_id >= 0 && spi_id <= MP_ARRAY_SIZE(machine_hard_spi_obj)
+            && machine_hard_spi_obj[spi_id].spi != NULL) {
+            return spi_id;
+        }
+        nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
+            "SPI(%d) does not exist", spi_id));
+    }
+}
+
+void spi_init(SPI_HandleTypeDef *spi, bool enable_nss_pin) {
+}
+
+void spi_deinit(SPI_HandleTypeDef *spi) {
+}
+
+STATIC void spi_transfer(const machine_hard_spi_obj_t * self, size_t len, const void * src, void * dest) {
+    hal_spi_master_tx_rx(self->spi->instance, len, src, dest);
+}
+
+STATIC void spi_print(const mp_print_t *print, SPI_HandleTypeDef *spi, bool legacy) {
+    uint spi_num = 0; // default to SPI1
+    mp_printf(print, "SPI(%u)", spi_num);
+}
+
+/******************************************************************************/
+/* MicroPython bindings for machine API                                       */
+
+// for make_new
+enum {
+    ARG_NEW_id,
+    ARG_NEW_baudrate,
+    ARG_NEW_polarity,
+    ARG_NEW_phase,
+    ARG_NEW_bits,
+    ARG_NEW_firstbit,
+    ARG_NEW_sck,
+    ARG_NEW_mosi,
+    ARG_NEW_miso
+};
+
+// for init
+enum {
+    ARG_INIT_baudrate,
+    ARG_INIT_polarity,
+    ARG_INIT_phase,
+    ARG_INIT_bits,
+    ARG_INIT_firstbit
+};
+
+STATIC mp_obj_t machine_hard_spi_make_new(mp_arg_val_t *args);
+STATIC void machine_hard_spi_init(mp_obj_t self, mp_arg_val_t *args);
+STATIC void machine_hard_spi_deinit(mp_obj_t self);
+
+/* common code for both soft and hard implementations *************************/
+
+STATIC mp_obj_t machine_spi_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) {
+    static const mp_arg_t allowed_args[] = {
+        { MP_QSTR_id,       MP_ARG_OBJ, {.u_obj = MP_OBJ_NEW_SMALL_INT(-1)} },
+        { MP_QSTR_baudrate, MP_ARG_INT, {.u_int = 500000} },
+        { MP_QSTR_polarity, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} },
+        { MP_QSTR_phase,    MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} },
+        { MP_QSTR_bits,     MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 8} },
+        { MP_QSTR_firstbit, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0 /* SPI_FIRSTBIT_MSB */} },
+        { MP_QSTR_sck,      MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
+        { MP_QSTR_mosi,     MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
+        { MP_QSTR_miso,     MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
+    };
+
+    // parse args
+    mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
+    mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
+
+    if (args[ARG_NEW_id].u_obj == MP_OBJ_NEW_SMALL_INT(-1)) {
+        // TODO: implement soft SPI
+        // return machine_soft_spi_make_new(args);
+        return mp_const_none;
+    } else {
+        // hardware peripheral id given
+        return machine_hard_spi_make_new(args);
+    }
+}
+
+STATIC mp_obj_t machine_spi_init(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+    static const mp_arg_t allowed_args[] = {
+        { MP_QSTR_baudrate, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} },
+        { MP_QSTR_polarity, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} },
+        { MP_QSTR_phase,    MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} },
+        { MP_QSTR_bits,     MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} },
+        { MP_QSTR_firstbit, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} },
+    };
+
+    // parse args
+    mp_obj_t self = pos_args[0];
+    mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
+    mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
+
+    // dispatch to specific implementation
+    if (mp_obj_get_type(self) == &machine_hard_spi_type) {
+        machine_hard_spi_init(self, args);
+    }
+
+    return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_KW(machine_spi_init_obj, 1, machine_spi_init);
+
+STATIC mp_obj_t machine_spi_deinit(mp_obj_t self) {
+    // dispatch to specific implementation
+    if (mp_obj_get_type(self) == &machine_hard_spi_type) {
+        machine_hard_spi_deinit(self);
+    }
+    return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_spi_deinit_obj, machine_spi_deinit);
+
+STATIC const mp_rom_map_elem_t machine_spi_locals_dict_table[] = {
+    { MP_ROM_QSTR(MP_QSTR_init), MP_ROM_PTR(&machine_spi_init_obj) },
+    { MP_ROM_QSTR(MP_QSTR_deinit), MP_ROM_PTR(&machine_spi_deinit_obj) },
+
+    { MP_ROM_QSTR(MP_QSTR_read), MP_ROM_PTR(&mp_machine_spi_read_obj) },
+    { MP_ROM_QSTR(MP_QSTR_readinto), MP_ROM_PTR(&mp_machine_spi_readinto_obj) },
+    { MP_ROM_QSTR(MP_QSTR_write), MP_ROM_PTR(&mp_machine_spi_write_obj) },
+    { MP_ROM_QSTR(MP_QSTR_write_readinto), MP_ROM_PTR(&mp_machine_spi_write_readinto_obj) },
+
+    { MP_ROM_QSTR(MP_QSTR_MSB), MP_ROM_INT(HAL_SPI_MSB_FIRST) }, // SPI_FIRSTBIT_MSB
+    { MP_ROM_QSTR(MP_QSTR_LSB), MP_ROM_INT(HAL_SPI_LSB_FIRST) }, // SPI_FIRSTBIT_LSB
+};
+
+STATIC MP_DEFINE_CONST_DICT(machine_spi_locals_dict, machine_spi_locals_dict_table);
+
+/* code for hard implementation ***********************************************/
+
+STATIC void machine_hard_spi_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) {
+    machine_hard_spi_obj_t *self = self_in;
+    spi_print(print, self->spi, false);
+}
+
+STATIC mp_obj_t machine_hard_spi_make_new(mp_arg_val_t *args) {
+    // get static peripheral object
+    int spi_id = spi_find(args[ARG_NEW_id].u_obj);
+    const machine_hard_spi_obj_t *self = &machine_hard_spi_obj[spi_id];
+
+    // here we would check the sck/mosi/miso pins and configure them
+    if (args[ARG_NEW_sck].u_obj != MP_OBJ_NULL
+        && args[ARG_NEW_mosi].u_obj != MP_OBJ_NULL
+        && args[ARG_NEW_miso].u_obj != MP_OBJ_NULL) {
+
+        self->spi->init.clk_pin = args[ARG_NEW_sck].u_obj;
+        self->spi->init.mosi_pin = args[ARG_NEW_mosi].u_obj;
+        self->spi->init.miso_pin = args[ARG_NEW_miso].u_obj;
+    } else {
+        self->spi->init.clk_pin = &MICROPY_HW_SPI0_SCK;
+        self->spi->init.mosi_pin = &MICROPY_HW_SPI0_MOSI;
+        self->spi->init.miso_pin = &MICROPY_HW_SPI0_MISO;
+    }
+
+    int baudrate = args[ARG_NEW_baudrate].u_int;
+
+    if (baudrate <= 125000) {
+        self->spi->init.freq = HAL_SPI_FREQ_125_Kbps;
+    } else if (baudrate <= 250000) {
+        self->spi->init.freq = HAL_SPI_FREQ_250_Kbps;
+    } else if (baudrate <= 500000) {
+        self->spi->init.freq = HAL_SPI_FREQ_500_Kbps;
+    } else if (baudrate <= 1000000) {
+        self->spi->init.freq = HAL_SPI_FREQ_1_Mbps;
+    } else if (baudrate <= 2000000) {
+        self->spi->init.freq = HAL_SPI_FREQ_2_Mbps;
+    } else if (baudrate <= 4000000) {
+        self->spi->init.freq = HAL_SPI_FREQ_4_Mbps;
+    } else if (baudrate <= 8000000) {
+        self->spi->init.freq = HAL_SPI_FREQ_8_Mbps;
+#if NRF52840_XXAA
+    } else if (baudrate <= 16000000) {
+        self->spi->init.freq = HAL_SPI_FREQ_16_Mbps;
+    } else if (baudrate <= 32000000) {
+        self->spi->init.freq = HAL_SPI_FREQ_32_Mbps;
+#endif
+    } else { // Default
+        self->spi->init.freq = HAL_SPI_FREQ_1_Mbps;
+    }
+#ifdef NRF51
+    self->spi->init.irq_priority = 3;
+#else
+    self->spi->init.irq_priority = 6;
+#endif
+    self->spi->init.mode = HAL_SPI_MODE_CPOL0_CPHA0;
+    self->spi->init.firstbit = (args[ARG_NEW_firstbit].u_int == 0) ? HAL_SPI_MSB_FIRST : HAL_SPI_LSB_FIRST;;
+    hal_spi_master_init(self->spi->instance, &self->spi->init);
+
+    return MP_OBJ_FROM_PTR(self);
+}
+
+STATIC void machine_hard_spi_init(mp_obj_t self_in, mp_arg_val_t *args) {
+}
+
+STATIC void machine_hard_spi_deinit(mp_obj_t self_in) {
+    machine_hard_spi_obj_t *self = self_in;
+    spi_deinit(self->spi);
+}
+
+STATIC void machine_hard_spi_transfer(mp_obj_base_t *self_in, size_t len, const uint8_t *src, uint8_t *dest) {
+    machine_hard_spi_obj_t *self = (machine_hard_spi_obj_t*)self_in;
+    spi_transfer(self, len, src, dest);
+}
+
+
+STATIC mp_obj_t mp_machine_spi_read(size_t n_args, const mp_obj_t *args) {
+    vstr_t vstr;
+    vstr_init_len(&vstr, mp_obj_get_int(args[1]));
+    memset(vstr.buf, n_args == 3 ? mp_obj_get_int(args[2]) : 0, vstr.len);
+    spi_transfer(args[0], vstr.len, vstr.buf, vstr.buf);
+    return mp_obj_new_str_from_vstr(&mp_type_bytes, &vstr);
+}
+MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(mp_machine_spi_read_obj, 2, 3, mp_machine_spi_read);
+
+STATIC mp_obj_t mp_machine_spi_readinto(size_t n_args, const mp_obj_t *args) {
+    mp_buffer_info_t bufinfo;
+    mp_get_buffer_raise(args[1], &bufinfo, MP_BUFFER_WRITE);
+    memset(bufinfo.buf, n_args == 3 ? mp_obj_get_int(args[2]) : 0, bufinfo.len);
+    spi_transfer(args[0], bufinfo.len, bufinfo.buf, bufinfo.buf);
+    return mp_const_none;
+}
+MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(mp_machine_spi_readinto_obj, 2, 3, mp_machine_spi_readinto);
+
+STATIC mp_obj_t mp_machine_spi_write(mp_obj_t self, mp_obj_t wr_buf) {
+    mp_buffer_info_t src;
+    mp_get_buffer_raise(wr_buf, &src, MP_BUFFER_READ);
+    spi_transfer(self, src.len, (const uint8_t*)src.buf, NULL);
+    return mp_const_none;
+}
+MP_DEFINE_CONST_FUN_OBJ_2(mp_machine_spi_write_obj, mp_machine_spi_write);
+
+STATIC mp_obj_t mp_machine_spi_write_readinto(mp_obj_t self, mp_obj_t wr_buf, mp_obj_t rd_buf) {
+    mp_buffer_info_t src;
+    mp_get_buffer_raise(wr_buf, &src, MP_BUFFER_READ);
+    mp_buffer_info_t dest;
+    mp_get_buffer_raise(rd_buf, &dest, MP_BUFFER_WRITE);
+    if (src.len != dest.len) {
+        mp_raise_ValueError("buffers must be the same length");
+    }
+    spi_transfer(self, src.len, src.buf, dest.buf);
+    return mp_const_none;
+}
+MP_DEFINE_CONST_FUN_OBJ_3(mp_machine_spi_write_readinto_obj, mp_machine_spi_write_readinto);
+
+
+STATIC const mp_machine_spi_p_t machine_hard_spi_p = {
+    .transfer = machine_hard_spi_transfer,
+};
+
+const mp_obj_type_t machine_hard_spi_type = {
+    { &mp_type_type },
+    .name = MP_QSTR_SPI,
+    .print = machine_hard_spi_print,
+    .make_new = machine_spi_make_new,
+    .protocol = &machine_hard_spi_p,
+    .locals_dict = (mp_obj_dict_t*)&machine_spi_locals_dict,
+};
+
+#endif // MICROPY_PY_MACHINE_HW_SPI
diff --git a/ports/nrf/modules/machine/spi.h b/ports/nrf/modules/machine/spi.h
new file mode 100644
index 0000000000..71053fc276
--- /dev/null
+++ b/ports/nrf/modules/machine/spi.h
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#include "py/obj.h"
+
+#include "hal_spi.h"
+
+typedef struct _machine_hard_spi_obj_t {
+    mp_obj_base_t base;
+    SPI_HandleTypeDef *spi;
+} machine_hard_spi_obj_t;
+
+extern const mp_obj_type_t machine_hard_spi_type;
+
+void spi_init0(void);
diff --git a/ports/nrf/modules/machine/temp.c b/ports/nrf/modules/machine/temp.c
new file mode 100644
index 0000000000..9f1840c6ef
--- /dev/null
+++ b/ports/nrf/modules/machine/temp.c
@@ -0,0 +1,96 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Bander F. Ajba
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <stdio.h>
+#include <string.h>
+
+#include "py/nlr.h"
+#include "py/runtime.h"
+#include "py/mphal.h"
+#include "temp.h"
+#include "hal_temp.h"
+
+#if MICROPY_PY_MACHINE_TEMP
+
+typedef struct _machine_temp_obj_t {
+    mp_obj_base_t base;
+} machine_temp_obj_t;
+
+/// \method __str__()
+/// Return a string describing the Temp object.
+STATIC void machine_temp_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) {
+    machine_temp_obj_t *self = o;
+
+    (void)self;
+
+    mp_printf(print, "Temp");
+}
+
+/******************************************************************************/
+/* MicroPython bindings for machine API                                       */
+
+STATIC mp_obj_t machine_temp_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) {
+    static const mp_arg_t allowed_args[] = {
+        { },
+    };
+
+    // parse args
+    mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
+    mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
+    
+    machine_temp_obj_t *self = m_new_obj(machine_temp_obj_t);
+    
+    self->base.type = &machine_temp_type;
+
+    return MP_OBJ_FROM_PTR(self);
+}
+
+/// \method read()
+/// Get temperature.
+STATIC mp_obj_t machine_temp_read(mp_uint_t n_args, const mp_obj_t *args) {
+
+    return MP_OBJ_NEW_SMALL_INT(hal_temp_read());
+}
+
+STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(mp_machine_temp_read_obj, 0, 1, machine_temp_read);
+
+STATIC const mp_rom_map_elem_t machine_temp_locals_dict_table[] = {
+    // instance methods
+    // class methods
+    { MP_ROM_QSTR(MP_QSTR_read), MP_ROM_PTR(&mp_machine_temp_read_obj) },
+};
+
+STATIC MP_DEFINE_CONST_DICT(machine_temp_locals_dict, machine_temp_locals_dict_table);
+
+const mp_obj_type_t machine_temp_type = {
+    { &mp_type_type },
+    .name = MP_QSTR_Temp,
+    .make_new = machine_temp_make_new,
+    .locals_dict = (mp_obj_dict_t*)&machine_temp_locals_dict,
+    .print = machine_temp_print,
+};
+
+#endif // MICROPY_PY_MACHINE_TEMP
diff --git a/ports/nrf/modules/machine/temp.h b/ports/nrf/modules/machine/temp.h
new file mode 100644
index 0000000000..e8f751bdfa
--- /dev/null
+++ b/ports/nrf/modules/machine/temp.h
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Bander F. Ajba
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef TEMP_H__
+#define TEMP_H__
+
+extern const mp_obj_type_t machine_temp_type;
+
+int32_t temp_read(void);
+
+#endif // TEMP_H__
diff --git a/ports/nrf/modules/machine/timer.c b/ports/nrf/modules/machine/timer.c
new file mode 100644
index 0000000000..c8eb2ef30b
--- /dev/null
+++ b/ports/nrf/modules/machine/timer.c
@@ -0,0 +1,194 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <stdio.h>
+#include <string.h>
+
+#include "py/nlr.h"
+#include "py/runtime.h"
+#include "py/mphal.h"
+#include "timer.h"
+#include "hal_timer.h"
+
+#if MICROPY_PY_MACHINE_TIMER
+
+typedef struct _machine_timer_obj_t {
+    mp_obj_base_t      base;
+    hal_timer_conf_t * p_config;
+    mp_obj_t callback;
+    mp_int_t period;
+    mp_int_t mode;
+} machine_timer_obj_t;
+
+static hal_timer_conf_t timer_config0 = {.id = 0};
+static hal_timer_conf_t timer_config1 = {.id = 1};
+static hal_timer_conf_t timer_config2 = {.id = 2};
+
+#if NRF52
+static hal_timer_conf_t timer_config3 = {.id = 3};
+static hal_timer_conf_t timer_config4 = {.id = 4};
+#endif
+
+STATIC machine_timer_obj_t machine_timer_obj[] = {
+    {{&machine_timer_type}, &timer_config0},
+    {{&machine_timer_type}, &timer_config1},
+    {{&machine_timer_type}, &timer_config2},
+#if NRF52
+    {{&machine_timer_type}, &timer_config3},
+    {{&machine_timer_type}, &timer_config4},
+#endif
+};
+
+STATIC void hal_interrupt_handle(uint8_t id) {
+    machine_timer_obj_t * self = &machine_timer_obj[id];
+
+    mp_call_function_1(self->callback, self);
+
+    if (self != NULL) {
+        hal_timer_stop(id);
+        if (self->mode == 1) {
+            hal_timer_start(id);
+        }
+    }
+}
+
+void timer_init0(void) {
+    hal_timer_callback_set(hal_interrupt_handle);
+}
+
+STATIC int timer_find(mp_obj_t id) {
+    // given an integer id
+    int timer_id = mp_obj_get_int(id);
+    if (timer_id >= 0 && timer_id < MP_ARRAY_SIZE(machine_timer_obj)
+        && machine_timer_obj[timer_id].p_config != NULL) {
+        return timer_id;
+    }
+    nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
+        "Timer(%d) does not exist", timer_id));
+}
+
+STATIC void timer_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) {
+    machine_timer_obj_t *self = o;
+    mp_printf(print, "Timer(%u)", self->p_config->id);
+}
+
+/******************************************************************************/
+/* MicroPython bindings for machine API                                       */
+
+STATIC mp_obj_t machine_timer_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) {
+    static const mp_arg_t allowed_args[] = {
+        { MP_QSTR_id,       MP_ARG_OBJ, {.u_obj = MP_OBJ_NEW_SMALL_INT(-1)} },
+        { MP_QSTR_period,   MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 1000} },
+        { MP_QSTR_mode,     MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 1} },
+        { MP_QSTR_callback, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} },
+    };
+
+    // parse args
+    mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
+    mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
+
+    // get static peripheral object
+    int timer_id = timer_find(args[0].u_obj);
+
+#if BLUETOOTH_SD
+    if (timer_id == 0) {
+        nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
+                  "Timer(%d) reserved by Bluetooth LE stack.", timer_id));
+    }
+#endif
+
+#if MICROPY_PY_MACHINE_SOFT_PWM
+    if (timer_id == 1) {
+        nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
+                  "Timer(%d) reserved by ticker driver.", timer_id));
+    }
+#endif
+
+    machine_timer_obj_t *self = &machine_timer_obj[timer_id];
+
+    self->p_config->period = args[1].u_int;
+
+    self->mode = args[2].u_int;
+
+    if (args[3].u_obj != mp_const_none) {
+        self->callback = args[3].u_obj;
+    }
+
+#ifdef NRF51
+    self->p_config->irq_priority = 3;
+#else
+    self->p_config->irq_priority = 6;
+#endif
+
+    hal_timer_init(self->p_config);
+
+    return MP_OBJ_FROM_PTR(self);
+}
+
+/// \method start(period)
+/// Start the timer.
+///
+STATIC mp_obj_t machine_timer_start(mp_obj_t self_in) {
+    machine_timer_obj_t * self = MP_OBJ_TO_PTR(self_in);
+
+    hal_timer_start(self->p_config->id);
+
+    return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_timer_start_obj, machine_timer_start);
+
+/// \method stop()
+/// Stop the timer.
+///
+STATIC mp_obj_t machine_timer_stop(mp_obj_t self_in) {
+    machine_timer_obj_t * self = MP_OBJ_TO_PTR(self_in);
+
+    hal_timer_stop(self->p_config->id);
+
+    return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_timer_stop_obj, machine_timer_stop);
+
+STATIC const mp_rom_map_elem_t machine_timer_locals_dict_table[] = {
+    { MP_ROM_QSTR(MP_QSTR_start), MP_ROM_PTR(&machine_timer_start_obj) },
+    { MP_ROM_QSTR(MP_QSTR_stop),  MP_ROM_PTR(&machine_timer_stop_obj) },
+
+    // constants
+    { MP_ROM_QSTR(MP_QSTR_ONESHOT),  MP_ROM_INT(0) },
+    { MP_ROM_QSTR(MP_QSTR_PERIODIC), MP_ROM_INT(1) },
+};
+
+STATIC MP_DEFINE_CONST_DICT(machine_timer_locals_dict, machine_timer_locals_dict_table);
+
+const mp_obj_type_t machine_timer_type = {
+    { &mp_type_type },
+    .name = MP_QSTR_Timer,
+    .print = timer_print,
+    .make_new = machine_timer_make_new,
+    .locals_dict = (mp_obj_dict_t*)&machine_timer_locals_dict
+};
+
+#endif // MICROPY_PY_MACHINE_TIMER
diff --git a/ports/nrf/modules/machine/timer.h b/ports/nrf/modules/machine/timer.h
new file mode 100644
index 0000000000..2989dc69be
--- /dev/null
+++ b/ports/nrf/modules/machine/timer.h
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef TIMER_H__
+#define TIMER_H__
+
+#include "hal_timer.h"
+
+extern const mp_obj_type_t machine_timer_type;
+
+void timer_init0(void);
+
+#endif // TIMER_H__
diff --git a/ports/nrf/modules/machine/uart.c b/ports/nrf/modules/machine/uart.c
new file mode 100644
index 0000000000..b99afef622
--- /dev/null
+++ b/ports/nrf/modules/machine/uart.c
@@ -0,0 +1,382 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <stdbool.h>
+#include <string.h>
+#include <stdarg.h>
+
+#include "py/nlr.h"
+#include "py/runtime.h"
+#include "py/stream.h"
+#include "py/mperrno.h"
+#include "py/mphal.h"
+#include "pin.h"
+#include "genhdr/pins.h"
+
+#include "uart.h"
+#include "mpconfigboard.h"
+#include "nrf.h"
+#include "mphalport.h"
+#include "hal_uart.h"
+
+typedef struct _machine_hard_uart_obj_t {
+    mp_obj_base_t base;
+    UART_HandleTypeDef * uart;
+    byte char_width;                    // 0 for 7,8 bit chars, 1 for 9 bit chars
+} machine_hard_uart_obj_t;
+
+UART_HandleTypeDef UARTHandle0 = {.p_instance = NULL, .init.id = 0};
+#if NRF52840_XXAA
+UART_HandleTypeDef UARTHandle1 = {.p_instance = NULL, .init.id = 1};
+#endif
+
+STATIC machine_hard_uart_obj_t machine_hard_uart_obj[] = {
+    {{&machine_hard_uart_type}, &UARTHandle0},
+#if NRF52840_XXAA
+    {{&machine_hard_uart_type}, &UARTHandle1},
+#endif
+};
+
+void uart_init0(void) {
+    // reset the UART handles
+    memset(&UARTHandle0, 0, sizeof(UART_HandleTypeDef));
+    UARTHandle0.p_instance = UART_BASE(0);
+#if NRF52840_XXAA
+    memset(&UARTHandle1, 0, sizeof(UART_HandleTypeDef));
+    UARTHandle0.p_instance = UART_BASE(1);
+#endif
+}
+
+STATIC int uart_find(mp_obj_t id) {
+    // given an integer id
+    int uart_id = mp_obj_get_int(id);
+    if (uart_id >= 0 && uart_id <= MP_ARRAY_SIZE(machine_hard_uart_obj)
+        && machine_hard_uart_obj[uart_id].uart != NULL) {
+        return uart_id;
+    }
+    nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
+              "UART(%d) does not exist", uart_id));
+}
+
+void uart_irq_handler(mp_uint_t uart_id) {
+
+}
+
+bool uart_rx_any(machine_hard_uart_obj_t *uart_obj) {
+    // TODO: uart will block for now.
+    return true;
+}
+
+int uart_rx_char(machine_hard_uart_obj_t * self) {
+    uint8_t ch;
+    hal_uart_char_read(self->uart->p_instance, &ch);
+    return (int)ch;
+}
+
+STATIC hal_uart_error_t uart_tx_char(machine_hard_uart_obj_t * self, int c) {
+    return hal_uart_char_write(self->uart->p_instance, (char)c);
+}
+
+
+void uart_tx_strn(machine_hard_uart_obj_t *uart_obj, const char *str, uint len) {
+    for (const char *top = str + len; str < top; str++) {
+        uart_tx_char(uart_obj, *str);
+    }
+}
+
+void uart_tx_strn_cooked(machine_hard_uart_obj_t *uart_obj, const char *str, uint len) {
+    for (const char *top = str + len; str < top; str++) {
+        if (*str == '\n') {
+            uart_tx_char(uart_obj, '\r');
+        }
+        uart_tx_char(uart_obj, *str);
+    }
+}
+
+/******************************************************************************/
+/* MicroPython bindings                                                      */
+
+STATIC void machine_hard_uart_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) {
+}
+
+
+
+/// \method init(baudrate, bits=8, parity=None, stop=1, *, timeout=1000, timeout_char=0, read_buf_len=64)
+///
+/// Initialise the UART bus with the given parameters:
+///   - `id`is bus id.
+///   - `baudrate` is the clock rate.
+///   - `bits` is the number of bits per byte, 7, 8 or 9.
+///   - `parity` is the parity, `None`, 0 (even) or 1 (odd).
+///   - `stop` is the number of stop bits, 1 or 2.
+///   - `timeout` is the timeout in milliseconds to wait for the first character.
+///   - `timeout_char` is the timeout in milliseconds to wait between characters.
+///   - `read_buf_len` is the character length of the read buffer (0 to disable).
+STATIC mp_obj_t machine_hard_uart_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) {
+    static const mp_arg_t allowed_args[] = {
+        { MP_QSTR_id,       MP_ARG_REQUIRED | MP_ARG_OBJ },
+        { MP_QSTR_baudrate, MP_ARG_REQUIRED | MP_ARG_INT, {.u_int = 9600} },
+        { MP_QSTR_bits, MP_ARG_INT, {.u_int = 8} },
+        { MP_QSTR_parity, MP_ARG_OBJ, {.u_obj = mp_const_none} },
+        { MP_QSTR_stop, MP_ARG_INT, {.u_int = 1} },
+        { MP_QSTR_flow, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} },
+        { MP_QSTR_timeout, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 1000} },
+        { MP_QSTR_timeout_char, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} },
+        { MP_QSTR_read_buf_len, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 64} },
+    };
+
+    // parse args
+    mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
+    mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
+
+    // get static peripheral object
+    int uart_id = uart_find(args[0].u_obj);
+    machine_hard_uart_obj_t * self = &machine_hard_uart_obj[uart_id];
+
+    hal_uart_init_t * init = &self->uart->init;
+
+    // flow control
+    init->flow_control = args[5].u_int;
+
+#if MICROPY_HW_UART1_HWFC
+    init->flow_control = true;
+#else
+	init->flow_control = false;
+#endif
+	init->use_parity   = false;
+#if (BLUETOOTH_SD == 100)
+	init->irq_priority = 3;
+#else
+	init->irq_priority = 6;
+#endif
+
+    switch (args[1].u_int) {
+        case 1200:
+            init->baud_rate = HAL_UART_BAUD_1K2;
+            break;
+        case 2400:
+            init->baud_rate = HAL_UART_BAUD_2K4;
+            break;
+        case 4800:
+            init->baud_rate = HAL_UART_BAUD_4K8;
+            break;
+        case 9600:
+            init->baud_rate = HAL_UART_BAUD_9K6;
+            break;
+        case 14400:
+            init->baud_rate = HAL_UART_BAUD_14K4;
+            break;
+        case 19200:
+            init->baud_rate = HAL_UART_BAUD_19K2;
+            break;
+        case 28800:
+            init->baud_rate = HAL_UART_BAUD_28K8;
+            break;
+        case 38400:
+            init->baud_rate = HAL_UART_BAUD_38K4;
+            break;
+        case 57600:
+            init->baud_rate = HAL_UART_BAUD_57K6;
+            break;
+        case 76800:
+            init->baud_rate = HAL_UART_BAUD_76K8;
+            break;
+        case 115200:
+            init->baud_rate = HAL_UART_BAUD_115K2;
+            break;
+        case 230400:
+            init->baud_rate = HAL_UART_BAUD_230K4;
+            break;
+        case 250000:
+            init->baud_rate = HAL_UART_BAUD_250K0;
+            break;
+        case 500000:
+            init->baud_rate = HAL_UART_BAUD_500K0;
+            break;
+        case 1000000:
+            init->baud_rate = HAL_UART_BAUD_1M0;
+            break;
+        default:
+            nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
+                      "UART baudrate not supported, %ul", init->baud_rate));
+            break;
+    }
+
+    init->rx_pin = &MICROPY_HW_UART1_RX;
+    init->tx_pin = &MICROPY_HW_UART1_TX;
+
+#if MICROPY_HW_UART1_HWFC
+    init->rts_pin = &MICROPY_HW_UART1_RTS;
+    init->cts_pin = &MICROPY_HW_UART1_CTS;
+#endif
+
+    hal_uart_init(self->uart->p_instance, init);
+
+    return MP_OBJ_FROM_PTR(self);
+}
+
+/// \method writechar(char)
+/// Write a single character on the bus.  `char` is an integer to write.
+/// Return value: `None`.
+STATIC mp_obj_t machine_hard_uart_writechar(mp_obj_t self_in, mp_obj_t char_in) {
+    machine_hard_uart_obj_t *self = self_in;
+
+    // get the character to write (might be 9 bits)
+    uint16_t data = mp_obj_get_int(char_in);
+
+    hal_uart_error_t err = 0;
+    for (int i = 0; i < 2; i++) {
+        err = uart_tx_char(self, (int)(&data)[i]);
+    }
+
+    HAL_StatusTypeDef status = self->uart->p_instance->EVENTS_ERROR;
+
+    if (err != HAL_UART_ERROR_NONE) {
+        mp_hal_raise(status);
+    }
+
+    return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_2(machine_hard_uart_writechar_obj, machine_hard_uart_writechar);
+
+/// \method readchar()
+/// Receive a single character on the bus.
+/// Return value: The character read, as an integer.  Returns -1 on timeout.
+STATIC mp_obj_t machine_hard_uart_readchar(mp_obj_t self_in) {
+    machine_hard_uart_obj_t *self = self_in;
+    return MP_OBJ_NEW_SMALL_INT(uart_rx_char(self));
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_hard_uart_readchar_obj, machine_hard_uart_readchar);
+
+// uart.sendbreak()
+STATIC mp_obj_t machine_hard_uart_sendbreak(mp_obj_t self_in) {
+    return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_hard_uart_sendbreak_obj, machine_hard_uart_sendbreak);
+
+STATIC const mp_rom_map_elem_t machine_hard_uart_locals_dict_table[] = {
+    // instance methods
+    /// \method read([nbytes])
+    { MP_ROM_QSTR(MP_QSTR_read), MP_ROM_PTR(&mp_stream_read_obj) },
+    /// \method readline()
+    { MP_ROM_QSTR(MP_QSTR_readline), MP_ROM_PTR(&mp_stream_unbuffered_readline_obj) },
+    /// \method readinto(buf[, nbytes])
+    { MP_ROM_QSTR(MP_QSTR_readinto), MP_ROM_PTR(&mp_stream_readinto_obj) },
+    /// \method writechar(buf)
+    { MP_ROM_QSTR(MP_QSTR_writechar), MP_ROM_PTR(&machine_hard_uart_writechar_obj) },
+    { MP_ROM_QSTR(MP_QSTR_readchar), MP_ROM_PTR(&machine_hard_uart_readchar_obj) },
+    { MP_ROM_QSTR(MP_QSTR_sendbreak), MP_ROM_PTR(&machine_hard_uart_sendbreak_obj) },
+
+    // class constants
+/*
+    { MP_ROM_QSTR(MP_QSTR_RTS), MP_ROM_INT(UART_HWCONTROL_RTS) },
+    { MP_ROM_QSTR(MP_QSTR_CTS), MP_ROM_INT(UART_HWCONTROL_CTS) },
+*/
+};
+
+STATIC MP_DEFINE_CONST_DICT(machine_hard_uart_locals_dict, machine_hard_uart_locals_dict_table);
+
+STATIC mp_uint_t machine_hard_uart_read(mp_obj_t self_in, void *buf_in, mp_uint_t size, int *errcode) {
+    machine_hard_uart_obj_t *self = self_in;
+    byte *buf = buf_in;
+
+    // check that size is a multiple of character width
+    if (size & self->char_width) {
+        *errcode = MP_EIO;
+        return MP_STREAM_ERROR;
+    }
+
+    // convert byte size to char size
+    size >>= self->char_width;
+
+    // make sure we want at least 1 char
+    if (size == 0) {
+        return 0;
+    }
+
+    // read the data
+    byte * orig_buf = buf;
+    for (;;) {
+        int data = uart_rx_char(self);
+
+        *buf++ = data;
+
+        if (--size == 0) {
+            // return number of bytes read
+            return buf - orig_buf;
+        }
+    }
+}
+
+STATIC mp_uint_t machine_hard_uart_write(mp_obj_t self_in, const void *buf_in, mp_uint_t size, int *errcode) {
+    machine_hard_uart_obj_t *self = self_in;
+    const byte *buf = buf_in;
+
+    // check that size is a multiple of character width
+    if (size & self->char_width) {
+        *errcode = MP_EIO;
+        return MP_STREAM_ERROR;
+    }
+
+    hal_uart_error_t err = 0;
+    for (int i = 0; i < size; i++) {
+        err = uart_tx_char(self, (int)((uint8_t *)buf)[i]);
+    }
+
+    if (err == HAL_UART_ERROR_NONE) {
+        // return number of bytes written
+        return size;
+    } else {
+        *errcode = mp_hal_status_to_errno_table[err];
+        return MP_STREAM_ERROR;
+    }
+}
+
+STATIC mp_uint_t machine_hard_uart_ioctl(mp_obj_t self_in, mp_uint_t request, uintptr_t arg, int *errcode) {
+    machine_hard_uart_obj_t *self = self_in;
+    (void)self;
+    return MP_STREAM_ERROR;
+}
+
+STATIC const mp_stream_p_t uart_stream_p = {
+    .read = machine_hard_uart_read,
+    .write = machine_hard_uart_write,
+    .ioctl = machine_hard_uart_ioctl,
+    .is_text = false,
+};
+
+const mp_obj_type_t machine_hard_uart_type = {
+    { &mp_type_type },
+    .name = MP_QSTR_UART,
+    .print = machine_hard_uart_print,
+    .make_new = machine_hard_uart_make_new,
+    .getiter = mp_identity_getiter,
+    .iternext = mp_stream_unbuffered_iter,
+    .protocol = &uart_stream_p,
+    .locals_dict = (mp_obj_dict_t*)&machine_hard_uart_locals_dict,
+};
+
diff --git a/ports/nrf/modules/machine/uart.h b/ports/nrf/modules/machine/uart.h
new file mode 100644
index 0000000000..a4453eadff
--- /dev/null
+++ b/ports/nrf/modules/machine/uart.h
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef UART_H__
+#define UART_H__
+
+typedef enum {
+    PYB_UART_NONE = 0,
+    PYB_UART_1 = 1,
+} pyb_uart_t;
+
+typedef struct _machine_hard_uart_obj_t machine_hard_uart_obj_t;
+extern const mp_obj_type_t machine_hard_uart_type;
+
+void uart_init0(void);
+void uart_deinit(void);
+void uart_irq_handler(mp_uint_t uart_id);
+
+bool uart_rx_any(machine_hard_uart_obj_t * uart_obj);
+int uart_rx_char(machine_hard_uart_obj_t * uart_obj);
+void uart_tx_strn(machine_hard_uart_obj_t * uart_obj, const char *str, uint len);
+void uart_tx_strn_cooked(machine_hard_uart_obj_t *uart_obj, const char *str, uint len);
+
+#endif
diff --git a/ports/nrf/modules/music/modmusic.c b/ports/nrf/modules/music/modmusic.c
new file mode 100644
index 0000000000..c2afc341cb
--- /dev/null
+++ b/ports/nrf/modules/music/modmusic.c
@@ -0,0 +1,517 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2015 Damien P. George
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "py/mphal.h"
+
+#if MICROPY_PY_MUSIC
+
+// #include "microbitobj.h"
+// #include "microbitmusic.h"
+#include "py/obj.h"
+#include "py/runtime.h"
+#include "py/objstr.h"
+#include "modmusic.h"
+#include "musictunes.h"
+#include "softpwm.h"
+#include "ticker.h"
+#include "pin.h"
+#include "genhdr/pins.h"
+
+#define DEFAULT_BPM      120
+#define DEFAULT_TICKS    4 // i.e. 4 ticks per beat
+#define DEFAULT_OCTAVE   4 // C4 is middle C
+#define DEFAULT_DURATION 4 // Crotchet
+#define ARTICULATION_MS  10 // articulation between notes in milliseconds
+
+typedef struct _music_data_t {
+    uint16_t bpm;
+    uint16_t ticks;
+
+    // store these to simplify the writing process
+    uint8_t last_octave;
+    uint8_t last_duration;
+
+    // Asynchronous parts.
+    volatile uint8_t async_state;
+    bool async_loop;
+    uint32_t async_wait_ticks;
+    uint16_t async_notes_len;
+    uint16_t async_notes_index;
+    const pin_obj_t *async_pin;
+    mp_obj_t async_note;
+} music_data_t;
+
+enum {
+    ASYNC_MUSIC_STATE_IDLE,
+    ASYNC_MUSIC_STATE_NEXT_NOTE,
+    ASYNC_MUSIC_STATE_ARTICULATE,
+};
+
+#define music_data MP_STATE_PORT(music_data)
+
+extern volatile uint32_t ticks;
+
+STATIC uint32_t start_note(const char *note_str, size_t note_len, const pin_obj_t *pin);
+
+void microbit_music_init0(void) {
+    softpwm_init();
+    ticker_init(microbit_music_tick);
+    ticker_start();
+    pwm_start();
+}
+
+void microbit_music_tick(void) {
+    if (music_data == NULL) {
+        // music module not yet imported
+        return;
+    }
+
+    if (music_data->async_state == ASYNC_MUSIC_STATE_IDLE) {
+        // nothing to do
+        return;
+    }
+
+    if (ticks < music_data->async_wait_ticks) {
+        // need to wait for timeout to expire
+        return;
+    }
+
+    if (music_data->async_state == ASYNC_MUSIC_STATE_ARTICULATE) {
+        // turn off output and rest
+        pwm_set_duty_cycle(music_data->async_pin->pin, 0); // TODO: remove pin setting.
+        music_data->async_wait_ticks = ticks + ARTICULATION_MS;
+        music_data->async_state = ASYNC_MUSIC_STATE_NEXT_NOTE;
+    } else if (music_data->async_state == ASYNC_MUSIC_STATE_NEXT_NOTE) {
+        // play next note
+        if (music_data->async_notes_index >= music_data->async_notes_len) {
+            if (music_data->async_loop) {
+                music_data->async_notes_index = 0;
+            } else {
+                music_data->async_state = ASYNC_MUSIC_STATE_IDLE;
+// TODO:        microbit_obj_pin_free(music_data->async_pin);
+                music_data->async_pin = NULL;
+                return;
+            }
+        }
+        mp_obj_t note;
+        if (music_data->async_notes_len == 1) {
+            note = music_data->async_note;
+        } else {
+            note = ((mp_obj_t*)music_data->async_note)[music_data->async_notes_index];
+        }
+        if (note == mp_const_none) {
+            // a rest (is this even used anymore?)
+            pwm_set_duty_cycle(music_data->async_pin->pin, 0); // TODO: remove pin setting.
+            music_data->async_wait_ticks = 60000 / music_data->bpm;
+            music_data->async_state = ASYNC_MUSIC_STATE_NEXT_NOTE;
+        } else {
+            // a note
+            mp_uint_t note_len;
+            const char *note_str = mp_obj_str_get_data(note, &note_len);
+            uint32_t delay_on = start_note(note_str, note_len, music_data->async_pin);
+            music_data->async_wait_ticks = ticks + delay_on;
+            music_data->async_notes_index += 1;
+            music_data->async_state = ASYNC_MUSIC_STATE_ARTICULATE;
+        }
+    }
+}
+
+STATIC void wait_async_music_idle(void) {
+    // wait for the async music state to become idle
+    while (music_data->async_state != ASYNC_MUSIC_STATE_IDLE) {
+        // allow CTRL-C to stop the music
+        if (MP_STATE_VM(mp_pending_exception) != MP_OBJ_NULL) {
+            music_data->async_state = ASYNC_MUSIC_STATE_IDLE;
+            pwm_set_duty_cycle(music_data->async_pin->pin, 0); // TODO: remove pin setting.
+            break;
+        }
+    }
+}
+
+STATIC uint32_t start_note(const char *note_str, size_t note_len, const pin_obj_t *pin) {
+    pwm_set_duty_cycle(pin->pin, 128); // TODO: remove pin setting.
+
+    // [NOTE](#|b)(octave)(:length)
+    // technically, c4 is middle c, so we'll go with that...
+    // if we define A as 0 and G as 7, then we can use the following
+    // array of us periods
+
+    // these are the periods of note4 (the octave ascending from middle c) from A->B then C->G
+    STATIC uint16_t periods_us[] = {2273, 2025, 3822, 3405, 3034, 2863, 2551};
+    // A#, -, C#, D#, -, F#, G#
+    STATIC uint16_t periods_sharps_us[] = {2145, 0, 3608, 3214, 0, 2703, 2408};
+
+    // we'll represent the note as an integer (A=0, G=6)
+    // TODO: validate the note
+    uint8_t note_index = (note_str[0] & 0x1f) - 1;
+
+    // TODO: the duration and bpm should be persistent between notes
+    uint32_t ms_per_tick = (60000 / music_data->bpm) / music_data->ticks;
+
+    int8_t octave = 0;
+    bool sharp = false;
+
+    size_t current_position = 1;
+
+    // parse sharp or flat
+    if (current_position < note_len && (note_str[current_position] == '#' || note_str[current_position] == 'b')) {
+        if (note_str[current_position] == 'b') {
+            // make sure we handle wrapping round gracefully
+            if (note_index == 0) {
+                note_index = 6;
+            } else {
+                note_index--;
+            }
+
+            // handle the unusual edge case of Cb
+            if (note_index == 1) {
+                octave--;
+            }
+        }
+
+        sharp = true;
+        current_position++;
+    }
+
+    // parse the octave
+    if (current_position < note_len && note_str[current_position] != ':') {
+        // currently this will only work with a one digit number
+        // use +=, since the sharp/flat code changes octave to compensate.
+        music_data->last_octave = (note_str[current_position] & 0xf);
+        current_position++;
+    }
+
+    octave += music_data->last_octave;
+
+    // parse the duration
+    if (current_position < note_len && note_str[current_position] == ':') {
+        // I'll make this handle up to two digits for the time being.
+        current_position++;
+
+        if (current_position < note_len) {
+            music_data->last_duration = note_str[current_position] & 0xf;
+
+            current_position++;
+            if (current_position < note_len) {
+                music_data->last_duration *= 10;
+                music_data->last_duration += note_str[current_position] & 0xf;
+            }
+        } else {
+            // technically, this should be a syntax error, since this means
+            // that no duration has been specified. For the time being,
+            // we'll let you off :D
+        }
+    }
+    // play the note!
+
+    // make the octave relative to octave 4
+    octave -= 4;
+
+    // 18 is 'r' or 'R'
+    if (note_index < 10) {
+        uint32_t period;
+        if (sharp) {
+            if (octave >= 0) {
+                period = periods_sharps_us[note_index] >> octave;
+            }
+            else {
+                period = periods_sharps_us[note_index] << -octave;
+            }
+        } else {
+            if (octave >= 0) {
+                period = periods_us[note_index] >> octave;
+            }
+            else {
+                period = periods_us[note_index] << -octave;
+            }
+        }
+        pwm_set_period_us(period);
+    } else {
+        pwm_set_duty_cycle(pin->pin, 0); // TODO: remove pin setting.
+    }
+
+    // Cut off a short time from end of note so we hear articulation.
+    mp_int_t gap_ms = (ms_per_tick * music_data->last_duration) - ARTICULATION_MS;
+    if (gap_ms < ARTICULATION_MS) {
+        gap_ms = ARTICULATION_MS;
+    }
+    return gap_ms;
+}
+
+STATIC mp_obj_t microbit_music_reset(void) {
+    music_data->bpm = DEFAULT_BPM;
+    music_data->ticks = DEFAULT_TICKS;
+    music_data->last_octave = DEFAULT_OCTAVE;
+    music_data->last_duration = DEFAULT_DURATION;
+
+    return mp_const_none;
+}
+MP_DEFINE_CONST_FUN_OBJ_0(microbit_music_reset_obj, microbit_music_reset);
+
+STATIC mp_obj_t microbit_music_get_tempo(void) {
+    mp_obj_t tempo_tuple[2];
+
+    tempo_tuple[0] = mp_obj_new_int(music_data->bpm);
+    tempo_tuple[1] = mp_obj_new_int(music_data->ticks);
+
+    return mp_obj_new_tuple(2, tempo_tuple);
+}
+MP_DEFINE_CONST_FUN_OBJ_0(microbit_music_get_tempo_obj, microbit_music_get_tempo);
+
+STATIC mp_obj_t microbit_music_stop(mp_uint_t n_args, const mp_obj_t *args) {
+    const pin_obj_t *pin;
+    if (n_args == 0) {
+#ifdef MICROPY_HW_MUSIC_PIN
+        pin = &MICROPY_HW_MUSIC_PIN;
+#else
+        mp_raise_ValueError("pin parameter not given");
+#endif
+    } else {
+        pin = (pin_obj_t *)args[0];
+    }
+    (void)pin;
+    // Raise exception if the pin we are trying to stop is not in a compatible mode.
+// TODO: microbit_obj_pin_acquire(pin, microbit_pin_mode_music);
+    pwm_set_duty_cycle(pin->pin, 0); // TODO: remove pin setting.
+// TODO: microbit_obj_pin_free(pin);
+    music_data->async_pin = NULL;
+    music_data->async_state = ASYNC_MUSIC_STATE_IDLE;
+
+    return mp_const_none;
+}
+MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(microbit_music_stop_obj, 0, 1, microbit_music_stop);
+
+STATIC mp_obj_t microbit_music_play(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+    static const mp_arg_t allowed_args[] = {
+        { MP_QSTR_music, MP_ARG_REQUIRED | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
+        { MP_QSTR_pin,   MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
+        { MP_QSTR_wait,  MP_ARG_BOOL, {.u_bool = true} },
+        { MP_QSTR_loop,  MP_ARG_BOOL, {.u_bool = false} },
+    };
+
+    // parse args
+    mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
+    mp_arg_parse_all(n_args, pos_args, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
+
+    // reset octave and duration so tunes always play the same
+    music_data->last_octave = DEFAULT_OCTAVE;
+    music_data->last_duration = DEFAULT_DURATION;
+
+    // get either a single note or a list of notes
+    mp_uint_t len;
+    mp_obj_t *items;
+    if (MP_OBJ_IS_STR_OR_BYTES(args[0].u_obj)) {
+        len = 1;
+        items = &args[0].u_obj;
+    } else {
+        mp_obj_get_array(args[0].u_obj, &len, &items);
+    }
+
+    // Release the previous pin
+// TODO: microbit_obj_pin_free(music_data->async_pin);
+    music_data->async_pin = NULL;
+
+    // get the pin to play on
+    const pin_obj_t *pin;
+    if (args[1].u_obj == MP_OBJ_NULL) {
+#ifdef MICROPY_HW_MUSIC_PIN
+        pin = &MICROPY_HW_MUSIC_PIN;
+#else
+        mp_raise_ValueError("pin parameter not given");
+#endif
+    } else {
+        pin = (pin_obj_t *)args[1].u_obj;
+    }
+    // TODO: microbit_obj_pin_acquire(pin, microbit_pin_mode_music);
+
+    // start the tune running in the background
+    music_data->async_state = ASYNC_MUSIC_STATE_IDLE;
+    music_data->async_wait_ticks = ticks;
+    music_data->async_loop = args[3].u_bool;
+    music_data->async_notes_len = len;
+    music_data->async_notes_index = 0;
+    if (len == 1) {
+        // If a string was passed as a single note then we can't store a pointer
+        // to args[0].u_obj, so instead store the single string directly (also
+        // works if a tuple/list of one element was passed).
+        music_data->async_note = items[0];
+    } else {
+        music_data->async_note = items;
+    }
+    music_data->async_pin = pin;
+    music_data->async_state = ASYNC_MUSIC_STATE_NEXT_NOTE;
+
+    if (args[2].u_bool) {
+        // wait for tune to finish
+        wait_async_music_idle();
+    }
+
+    return mp_const_none;
+}
+MP_DEFINE_CONST_FUN_OBJ_KW(microbit_music_play_obj, 0, microbit_music_play);
+
+STATIC mp_obj_t microbit_music_pitch(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+    static const mp_arg_t allowed_args[] = {
+        { MP_QSTR_frequency, MP_ARG_REQUIRED | MP_ARG_INT, {.u_int = 0} },
+        { MP_QSTR_duration, MP_ARG_INT, {.u_int = -1} },
+        { MP_QSTR_pin,    MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
+        { MP_QSTR_wait,   MP_ARG_BOOL, {.u_bool = true} },
+    };
+
+    // parse args
+    mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
+    mp_arg_parse_all(n_args, pos_args, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
+
+    // get the parameters
+    mp_uint_t frequency = args[0].u_int;
+    mp_int_t duration = args[1].u_int;
+
+    // get the pin to play on
+    const pin_obj_t *pin;
+    if (args[2].u_obj == MP_OBJ_NULL) {
+#ifdef MICROPY_HW_MUSIC_PIN
+        pin = &MICROPY_HW_MUSIC_PIN;
+#else
+        mp_raise_ValueError("pin parameter not given");
+#endif
+    } else {
+        pin = (pin_obj_t *)args[2].u_obj;
+    }
+
+    // Update pin modes
+//TODO: microbit_obj_pin_free(music_data->async_pin);
+    music_data->async_pin = NULL;
+//TODO: microbit_obj_pin_acquire(pin, microbit_pin_mode_music);
+    bool wait = args[3].u_bool;
+    pwm_set_duty_cycle(pin->pin, 128); // TODO: remove pin setting.
+    if (frequency == 0) {
+//TODO: pwm_release(pin->name);
+    } else if (pwm_set_period_us(1000000/frequency)) {
+        pwm_release(pin->pin); // TODO: remove pin setting.
+        mp_raise_ValueError("invalid pitch");
+    }
+    if (duration >= 0) {
+        // use async machinery to stop the pitch after the duration
+        music_data->async_state = ASYNC_MUSIC_STATE_IDLE;
+        music_data->async_wait_ticks = ticks + duration;
+        music_data->async_loop = false;
+        music_data->async_notes_len = 0;
+        music_data->async_notes_index = 0;
+        music_data->async_note = NULL;
+        music_data->async_pin = pin;
+        music_data->async_state = ASYNC_MUSIC_STATE_ARTICULATE;
+
+        if (wait) {
+            // wait for the pitch to finish
+            wait_async_music_idle();
+        }
+    } else {
+        // don't block here, since there's no reason to leave a pitch forever in a blocking C function
+    }
+
+    return mp_const_none;
+}
+MP_DEFINE_CONST_FUN_OBJ_KW(microbit_music_pitch_obj, 0, microbit_music_pitch);
+
+STATIC mp_obj_t microbit_music_set_tempo(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+    static const mp_arg_t allowed_args[] = {
+        { MP_QSTR_ticks, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} },
+        { MP_QSTR_bpm,   MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} },
+    };
+
+    mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
+    mp_arg_parse_all(n_args, pos_args, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
+
+    if (args[0].u_int != 0) {
+        // set ticks
+        music_data->ticks = args[0].u_int;
+    }
+
+    if (args[1].u_int != 0) {
+        music_data->bpm = args[1].u_int;
+    }
+
+    return mp_const_none;
+}
+MP_DEFINE_CONST_FUN_OBJ_KW(microbit_music_set_tempo_obj, 0, microbit_music_set_tempo);
+
+
+static mp_obj_t music_init(void) {
+    microbit_music_init0();
+
+    music_data = m_new_obj(music_data_t);
+    music_data->bpm = DEFAULT_BPM;
+    music_data->ticks = DEFAULT_TICKS;
+    music_data->last_octave = DEFAULT_OCTAVE;
+    music_data->last_duration = DEFAULT_DURATION;
+    music_data->async_state = ASYNC_MUSIC_STATE_IDLE;
+    music_data->async_pin = NULL;
+    music_data->async_note = NULL;
+    return mp_const_none;
+}
+MP_DEFINE_CONST_FUN_OBJ_0(music___init___obj, music_init);
+
+STATIC const mp_rom_map_elem_t microbit_music_locals_dict_table[] = {
+    { MP_ROM_QSTR(MP_QSTR___init__), MP_ROM_PTR(&music___init___obj) },
+
+    { MP_ROM_QSTR(MP_QSTR_reset), MP_ROM_PTR(&microbit_music_reset_obj) },
+    { MP_ROM_QSTR(MP_QSTR_set_tempo), MP_ROM_PTR(&microbit_music_set_tempo_obj) },
+    { MP_ROM_QSTR(MP_QSTR_get_tempo), MP_ROM_PTR(&microbit_music_get_tempo_obj) },
+    { MP_ROM_QSTR(MP_QSTR_play), MP_ROM_PTR(&microbit_music_play_obj) },
+    { MP_ROM_QSTR(MP_QSTR_pitch), MP_ROM_PTR(&microbit_music_pitch_obj) },
+    { MP_ROM_QSTR(MP_QSTR_stop), MP_ROM_PTR(&microbit_music_stop_obj) },
+
+    { MP_ROM_QSTR(MP_QSTR_DADADADUM), MP_ROM_PTR(&microbit_music_tune_dadadadum_obj) },
+    { MP_ROM_QSTR(MP_QSTR_ENTERTAINER), MP_ROM_PTR(&microbit_music_tune_entertainer_obj) },
+    { MP_ROM_QSTR(MP_QSTR_PRELUDE), MP_ROM_PTR(&microbit_music_tune_prelude_obj) },
+    { MP_ROM_QSTR(MP_QSTR_ODE), MP_ROM_PTR(&microbit_music_tune_ode_obj) },
+    { MP_ROM_QSTR(MP_QSTR_NYAN), MP_ROM_PTR(&microbit_music_tune_nyan_obj) },
+    { MP_ROM_QSTR(MP_QSTR_RINGTONE), MP_ROM_PTR(&microbit_music_tune_ringtone_obj) },
+    { MP_ROM_QSTR(MP_QSTR_FUNK), MP_ROM_PTR(&microbit_music_tune_funk_obj) },
+    { MP_ROM_QSTR(MP_QSTR_BLUES), MP_ROM_PTR(&microbit_music_tune_blues_obj) },
+    { MP_ROM_QSTR(MP_QSTR_BIRTHDAY), MP_ROM_PTR(&microbit_music_tune_birthday_obj) },
+    { MP_ROM_QSTR(MP_QSTR_WEDDING), MP_ROM_PTR(&microbit_music_tune_wedding_obj) },
+    { MP_ROM_QSTR(MP_QSTR_FUNERAL), MP_ROM_PTR(&microbit_music_tune_funeral_obj) },
+    { MP_ROM_QSTR(MP_QSTR_PUNCHLINE), MP_ROM_PTR(&microbit_music_tune_punchline_obj) },
+    { MP_ROM_QSTR(MP_QSTR_PYTHON), MP_ROM_PTR(&microbit_music_tune_python_obj) },
+    { MP_ROM_QSTR(MP_QSTR_BADDY), MP_ROM_PTR(&microbit_music_tune_baddy_obj) },
+    { MP_ROM_QSTR(MP_QSTR_CHASE), MP_ROM_PTR(&microbit_music_tune_chase_obj) },
+    { MP_ROM_QSTR(MP_QSTR_BA_DING), MP_ROM_PTR(&microbit_music_tune_ba_ding_obj) },
+    { MP_ROM_QSTR(MP_QSTR_WAWAWAWAA), MP_ROM_PTR(&microbit_music_tune_wawawawaa_obj) },
+    { MP_ROM_QSTR(MP_QSTR_JUMP_UP), MP_ROM_PTR(&microbit_music_tune_jump_up_obj) },
+    { MP_ROM_QSTR(MP_QSTR_JUMP_DOWN), MP_ROM_PTR(&microbit_music_tune_jump_down_obj) },
+    { MP_ROM_QSTR(MP_QSTR_POWER_UP), MP_ROM_PTR(&microbit_music_tune_power_up_obj) },
+    { MP_ROM_QSTR(MP_QSTR_POWER_DOWN), MP_ROM_PTR(&microbit_music_tune_power_down_obj) },
+};
+
+STATIC MP_DEFINE_CONST_DICT(microbit_music_locals_dict, microbit_music_locals_dict_table);
+
+const mp_obj_module_t music_module = {
+    .base = { &mp_type_module },
+    .globals = (mp_obj_dict_t*)&microbit_music_locals_dict,
+};
+
+#endif // MICROPY_PY_MUSIC
diff --git a/ports/nrf/modules/music/modmusic.h b/ports/nrf/modules/music/modmusic.h
new file mode 100644
index 0000000000..8e64f02198
--- /dev/null
+++ b/ports/nrf/modules/music/modmusic.h
@@ -0,0 +1,7 @@
+#ifndef __MICROPY_INCLUDED_MICROBIT_MUSIC_H__
+#define __MICROPY_INCLUDED_MICROBIT_MUSIC_H__
+
+void microbit_music_init0(void);
+void microbit_music_tick(void);
+
+#endif // __MICROPY_INCLUDED_MICROBIT_MUSIC_H__
diff --git a/ports/nrf/modules/music/musictunes.c b/ports/nrf/modules/music/musictunes.c
new file mode 100644
index 0000000000..f5e7f4a519
--- /dev/null
+++ b/ports/nrf/modules/music/musictunes.c
@@ -0,0 +1,164 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The music encoded herein is either in the public domain, composed by
+ * Nicholas H.Tollervey or the composer is untraceable and covered by fair
+ * (educational) use.
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2015 Damien P. George
+ * Copyright (c) 2015 Nicholas H. Tollervey
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "py/mphal.h"
+#include "py/objtuple.h"
+
+#if MICROPY_PY_MUSIC
+
+#define N(q) MP_ROM_QSTR(MP_QSTR_ ## q)
+#define T(name, ...) const mp_obj_tuple_t microbit_music_tune_ ## name ## _obj = {{&mp_type_tuple}, .len = (sizeof((mp_obj_t[]){__VA_ARGS__})/sizeof(mp_obj_t)), .items = {__VA_ARGS__}};
+
+
+T(dadadadum,
+    N(r4_colon_2), N(g), N(g), N(g), N(eb_colon_8), N(r_colon_2), N(f), N(f),
+    N(f), N(d_colon_8));
+
+T(entertainer,
+    N(d4_colon_1), N(d_hash_), N(e), N(c5_colon_2), N(e4_colon_1),
+    N(c5_colon_2), N(e4_colon_1), N(c5_colon_3), N(c_colon_1), N(d),
+    N(d_hash_), N(e), N(c), N(d), N(e_colon_2), N(b4_colon_1), N(d5_colon_2),
+    N(c_colon_4));
+
+T(prelude,
+    N(c4_colon_1), N(e), N(g), N(c5), N(e), N(g4), N(c5), N(e), N(c4), N(e),
+    N(g), N(c5), N(e), N(g4), N(c5), N(e), N(c4), N(d), N(g), N(d5), N(f),
+    N(g4), N(d5), N(f), N(c4), N(d), N(g), N(d5), N(f), N(g4), N(d5), N(f),
+    N(b3), N(d4), N(g), N(d5), N(f), N(g4), N(d5), N(f), N(b3), N(d4), N(g),
+    N(d5), N(f), N(g4), N(d5), N(f), N(c4), N(e), N(g), N(c5), N(e), N(g4),
+    N(c5), N(e), N(c4), N(e), N(g), N(c5), N(e), N(g4), N(c5), N(e));
+
+T(ode,
+    N(e4), N(e), N(f), N(g), N(g), N(f), N(e), N(d), N(c), N(c), N(d), N(e),
+    N(e_colon_6), N(d_colon_2), N(d_colon_8), N(e_colon_4), N(e), N(f), N(g),
+    N(g), N(f), N(e), N(d), N(c), N(c), N(d), N(e), N(d_colon_6),
+    N(c_colon_2), N(c_colon_8));
+
+T(nyan,
+    N(f_hash_5_colon_2), N(g_hash_), N(c_hash__colon_1), N(d_hash__colon_2),
+    N(b4_colon_1), N(d5_colon_1), N(c_hash_), N(b4_colon_2), N(b),
+    N(c_hash_5), N(d), N(d_colon_1), N(c_hash_), N(b4_colon_1),
+    N(c_hash_5_colon_1), N(d_hash_), N(f_hash_), N(g_hash_), N(d_hash_),
+    N(f_hash_), N(c_hash_), N(d), N(b4), N(c_hash_5), N(b4),
+    N(d_hash_5_colon_2), N(f_hash_), N(g_hash__colon_1), N(d_hash_),
+    N(f_hash_), N(c_hash_), N(d_hash_), N(b4), N(d5), N(d_hash_), N(d),
+    N(c_hash_), N(b4), N(c_hash_5), N(d_colon_2), N(b4_colon_1), N(c_hash_5),
+    N(d_hash_), N(f_hash_), N(c_hash_), N(d), N(c_hash_), N(b4),
+    N(c_hash_5_colon_2), N(b4), N(c_hash_5), N(b4), N(f_hash__colon_1),
+    N(g_hash_), N(b_colon_2), N(f_hash__colon_1), N(g_hash_), N(b),
+    N(c_hash_5), N(d_hash_), N(b4), N(e5), N(d_hash_), N(e), N(f_hash_),
+    N(b4_colon_2), N(b), N(f_hash__colon_1), N(g_hash_), N(b), N(f_hash_),
+    N(e5), N(d_hash_), N(c_hash_), N(b4), N(f_hash_), N(d_hash_), N(e),
+    N(f_hash_), N(b_colon_2), N(f_hash__colon_1), N(g_hash_), N(b_colon_2),
+    N(f_hash__colon_1), N(g_hash_), N(b), N(b), N(c_hash_5), N(d_hash_),
+    N(b4), N(f_hash_), N(g_hash_), N(f_hash_), N(b_colon_2), N(b_colon_1),
+    N(a_hash_), N(b), N(f_hash_), N(g_hash_), N(b), N(e5), N(d_hash_), N(e),
+    N(f_hash_), N(b4_colon_2), N(c_hash_5));
+
+T(ringtone,
+    N(c4_colon_1), N(d), N(e_colon_2), N(g), N(d_colon_1), N(e), N(f_colon_2),
+    N(a), N(e_colon_1), N(f), N(g_colon_2), N(b), N(c5_colon_4));
+
+T(funk,
+    N(c2_colon_2), N(c), N(d_hash_), N(c_colon_1), N(f_colon_2), N(c_colon_1),
+    N(f_colon_2), N(f_hash_), N(g), N(c), N(c), N(g), N(c_colon_1),
+    N(f_hash__colon_2), N(c_colon_1), N(f_hash__colon_2), N(f), N(d_hash_));
+
+T(blues,
+    N(c2_colon_2), N(e), N(g), N(a), N(a_hash_), N(a), N(g), N(e),
+    N(c2_colon_2), N(e), N(g), N(a), N(a_hash_), N(a), N(g), N(e), N(f), N(a),
+    N(c3), N(d), N(d_hash_), N(d), N(c), N(a2), N(c2_colon_2), N(e), N(g),
+    N(a), N(a_hash_), N(a), N(g), N(e), N(g), N(b), N(d3), N(f), N(f2), N(a),
+    N(c3), N(d_hash_), N(c2_colon_2), N(e), N(g), N(e), N(g), N(f), N(e),
+    N(d));
+
+T(birthday,
+    N(c4_colon_3), N(c_colon_1), N(d_colon_4), N(c_colon_4), N(f),
+    N(e_colon_8), N(c_colon_3), N(c_colon_1), N(d_colon_4), N(c_colon_4),
+    N(g), N(f_colon_8), N(c_colon_3), N(c_colon_1), N(c5_colon_4), N(a4),
+    N(f), N(e), N(d), N(a_hash__colon_3), N(a_hash__colon_1), N(a_colon_4),
+    N(f), N(g), N(f_colon_8));
+
+T(wedding,
+    N(c4_colon_4), N(f_colon_3), N(f_colon_1), N(f_colon_8), N(c_colon_4),
+    N(g_colon_3), N(e_colon_1), N(f_colon_8), N(c_colon_4), N(f_colon_3),
+    N(a_colon_1), N(c5_colon_4), N(a4_colon_3), N(f_colon_1), N(f_colon_4),
+    N(e_colon_3), N(f_colon_1), N(g_colon_8));
+
+T(funeral,
+    N(c3_colon_4), N(c_colon_3), N(c_colon_1), N(c_colon_4),
+    N(d_hash__colon_3), N(d_colon_1), N(d_colon_3), N(c_colon_1),
+    N(c_colon_3), N(b2_colon_1), N(c3_colon_4));
+
+T(punchline,
+    N(c4_colon_3), N(g3_colon_1), N(f_hash_), N(g), N(g_hash__colon_3), N(g),
+    N(r), N(b), N(c4));
+
+T(python,
+    N(d5_colon_1), N(b4), N(r), N(b), N(b), N(a_hash_), N(b), N(g5), N(r),
+    N(d), N(d), N(r), N(b4), N(c5), N(r), N(c), N(c), N(r), N(d),
+    N(e_colon_5), N(c_colon_1), N(a4), N(r), N(a), N(a), N(g_hash_), N(a),
+    N(f_hash_5), N(r), N(e), N(e), N(r), N(c), N(b4), N(r), N(b), N(b), N(r),
+    N(c5), N(d_colon_5), N(d_colon_1), N(b4), N(r), N(b), N(b), N(a_hash_),
+    N(b), N(b5), N(r), N(g), N(g), N(r), N(d), N(c_hash_), N(r), N(a), N(a),
+    N(r), N(a), N(a_colon_5), N(g_colon_1), N(f_hash__colon_2), N(a_colon_1),
+    N(a), N(g_hash_), N(a), N(e_colon_2), N(a_colon_1), N(a), N(g_hash_),
+    N(a), N(d), N(r), N(c_hash_), N(d), N(r), N(c_hash_), N(d_colon_2),
+    N(r_colon_3));
+
+T(baddy,
+    N(c3_colon_3), N(r), N(d_colon_2), N(d_hash_), N(r), N(c), N(r), N(f_hash__colon_8), );
+
+T(chase,
+    N(a4_colon_1), N(b), N(c5), N(b4), N(a_colon_2), N(r), N(a_colon_1), N(b), N(c5), N(b4), N(a_colon_2), N(r), N(a_colon_2), N(e5), N(d_hash_), N(e), N(f), N(e), N(d_hash_), N(e), N(b4_colon_1), N(c5), N(d), N(c), N(b4_colon_2), N(r), N(b_colon_1), N(c5), N(d), N(c), N(b4_colon_2), N(r), N(b_colon_2), N(e5), N(d_hash_), N(e), N(f), N(e), N(d_hash_), N(e), );
+
+T(ba_ding,
+    N(b5_colon_1), N(e6_colon_3), );
+
+T(wawawawaa,
+    N(e3_colon_3), N(r_colon_1), N(d_hash__colon_3), N(r_colon_1), N(d_colon_4), N(r_colon_1), N(c_hash__colon_8), );
+
+T(jump_up,
+    N(c5_colon_1), N(d), N(e), N(f), N(g), );
+
+T(jump_down,
+    N(g5_colon_1), N(f), N(e), N(d), N(c), );
+
+T(power_up,
+    N(g4_colon_1), N(c5), N(e), N(g_colon_2), N(e_colon_1), N(g_colon_3), );
+
+T(power_down,
+    N(g5_colon_1), N(d_hash_), N(c), N(g4_colon_2), N(b_colon_1), N(c5_colon_3), );
+
+#undef N
+#undef T
+
+#endif // MICROPY_PY_MUSIC
diff --git a/ports/nrf/modules/music/musictunes.h b/ports/nrf/modules/music/musictunes.h
new file mode 100644
index 0000000000..82dda5cc7a
--- /dev/null
+++ b/ports/nrf/modules/music/musictunes.h
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef MUSIC_TUNES_H__
+#define MUSIC_TUNES_H__
+
+extern const struct _mp_obj_tuple_t microbit_music_tune_dadadadum_obj;
+extern const struct _mp_obj_tuple_t microbit_music_tune_entertainer_obj;
+extern const struct _mp_obj_tuple_t microbit_music_tune_prelude_obj;
+extern const struct _mp_obj_tuple_t microbit_music_tune_ode_obj;
+extern const struct _mp_obj_tuple_t microbit_music_tune_nyan_obj;
+extern const struct _mp_obj_tuple_t microbit_music_tune_ringtone_obj;
+extern const struct _mp_obj_tuple_t microbit_music_tune_funk_obj;
+extern const struct _mp_obj_tuple_t microbit_music_tune_blues_obj;
+extern const struct _mp_obj_tuple_t microbit_music_tune_birthday_obj;
+extern const struct _mp_obj_tuple_t microbit_music_tune_wedding_obj;
+extern const struct _mp_obj_tuple_t microbit_music_tune_funeral_obj;
+extern const struct _mp_obj_tuple_t microbit_music_tune_punchline_obj;
+extern const struct _mp_obj_tuple_t microbit_music_tune_python_obj;
+extern const struct _mp_obj_tuple_t microbit_music_tune_baddy_obj;
+extern const struct _mp_obj_tuple_t microbit_music_tune_chase_obj;
+extern const struct _mp_obj_tuple_t microbit_music_tune_ba_ding_obj;
+extern const struct _mp_obj_tuple_t microbit_music_tune_wawawawaa_obj;
+extern const struct _mp_obj_tuple_t microbit_music_tune_jump_up_obj;
+extern const struct _mp_obj_tuple_t microbit_music_tune_jump_down_obj;
+extern const struct _mp_obj_tuple_t microbit_music_tune_power_up_obj;
+extern const struct _mp_obj_tuple_t microbit_music_tune_power_down_obj;
+
+#endif // MUSIC_TUNES_H__
diff --git a/ports/nrf/modules/pyb/modpyb.c b/ports/nrf/modules/pyb/modpyb.c
new file mode 100644
index 0000000000..dc2f0ae517
--- /dev/null
+++ b/ports/nrf/modules/pyb/modpyb.c
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2015 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "py/builtin.h"
+#include "lib/utils/pyexec.h"
+#include "py/runtime.h"
+#include "py/obj.h"
+#include "led.h"
+#include "nrf.h" // TODO: figure out where to put this import
+#include "pin.h"
+
+#if MICROPY_HW_HAS_LED
+#define PYB_LED_MODULE { MP_ROM_QSTR(MP_QSTR_LED), MP_ROM_PTR(&pyb_led_type) },
+#else
+#define PYB_LED_MODULE
+#endif
+
+STATIC const mp_rom_map_elem_t pyb_module_globals_table[] = {
+    { MP_ROM_QSTR(MP_QSTR___name__), MP_ROM_QSTR(MP_QSTR_pyb) },
+    { MP_ROM_QSTR(MP_QSTR_repl_info), MP_ROM_PTR(&pyb_set_repl_info_obj) },
+    { MP_ROM_QSTR(MP_QSTR_Pin), MP_ROM_PTR(&pin_type) },
+    PYB_LED_MODULE
+/*    { MP_ROM_QSTR(MP_QSTR_main), MP_ROM_PTR(&pyb_main_obj) }*/
+};
+
+
+STATIC MP_DEFINE_CONST_DICT(pyb_module_globals, pyb_module_globals_table);
+
+const mp_obj_module_t pyb_module = {
+    .base = { &mp_type_module },
+    .globals = (mp_obj_dict_t*)&pyb_module_globals,
+};
diff --git a/ports/nrf/modules/random/modrandom.c b/ports/nrf/modules/random/modrandom.c
new file mode 100644
index 0000000000..0e140750da
--- /dev/null
+++ b/ports/nrf/modules/random/modrandom.c
@@ -0,0 +1,177 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2016 Paul Sokolovsky
+ * Copyright (c) 2016 Damien P. George
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <assert.h>
+#include <string.h>
+
+#include "py/runtime.h"
+#include "hal_rng.h"
+
+#if MICROPY_PY_HW_RNG
+
+static inline int rand30() {
+    uint32_t val = hal_rng_generate();
+    return (val & 0x3fffffff); // binary mask b00111111111111111111111111111111
+}
+
+static inline int randbelow(int n) {
+    return rand30() % n;
+}
+
+STATIC mp_obj_t mod_random_getrandbits(mp_obj_t num_in) {
+    int n = mp_obj_get_int(num_in);
+    if (n > 30 || n == 0) {
+        nlr_raise(mp_obj_new_exception(&mp_type_ValueError));
+    }
+    uint32_t mask = ~0;
+    // Beware of C undefined behavior when shifting by >= than bit size
+    mask >>= (32 - n);
+    return mp_obj_new_int_from_uint(rand30() & mask);
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(mod_random_getrandbits_obj, mod_random_getrandbits);
+
+STATIC mp_obj_t mod_random_randrange(size_t n_args, const mp_obj_t *args) {
+    mp_int_t start = mp_obj_get_int(args[0]);
+    if (n_args == 1) {
+        // range(stop)
+        if (start > 0) {
+            return mp_obj_new_int(randbelow(start));
+        } else {
+            nlr_raise(mp_obj_new_exception(&mp_type_ValueError));
+        }
+    } else {
+        mp_int_t stop = mp_obj_get_int(args[1]);
+        if (n_args == 2) {
+            // range(start, stop)
+            if (start < stop) {
+                return mp_obj_new_int(start + randbelow(stop - start));
+            } else {
+                nlr_raise(mp_obj_new_exception(&mp_type_ValueError));
+            }
+        } else {
+            // range(start, stop, step)
+            mp_int_t step = mp_obj_get_int(args[2]);
+            mp_int_t n;
+            if (step > 0) {
+                n = (stop - start + step - 1) / step;
+            } else if (step < 0) {
+                n = (stop - start + step + 1) / step;
+            } else {
+                nlr_raise(mp_obj_new_exception(&mp_type_ValueError));
+            }
+            if (n > 0) {
+                return mp_obj_new_int(start + step * randbelow(n));
+            } else {
+                nlr_raise(mp_obj_new_exception(&mp_type_ValueError));
+            }
+        }
+    }
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(mod_random_randrange_obj, 1, 3, mod_random_randrange);
+
+STATIC mp_obj_t mod_random_randint(mp_obj_t a_in, mp_obj_t b_in) {
+    mp_int_t a = mp_obj_get_int(a_in);
+    mp_int_t b = mp_obj_get_int(b_in);
+    if (a <= b) {
+        return mp_obj_new_int(a + randbelow(b - a + 1));
+    } else {
+        nlr_raise(mp_obj_new_exception(&mp_type_ValueError));
+    }
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_2(mod_random_randint_obj, mod_random_randint);
+
+STATIC mp_obj_t mod_random_choice(mp_obj_t seq) {
+    mp_int_t len = mp_obj_get_int(mp_obj_len(seq));
+    if (len > 0) {
+        return mp_obj_subscr(seq, mp_obj_new_int(randbelow(len)), MP_OBJ_SENTINEL);
+    } else {
+        nlr_raise(mp_obj_new_exception(&mp_type_IndexError));
+    }
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(mod_random_choice_obj, mod_random_choice);
+
+#if MICROPY_PY_BUILTINS_FLOAT
+
+// returns a number in the range [0..1) using RNG to fill in the fraction bits
+STATIC mp_float_t randfloat(void) {
+    #if MICROPY_FLOAT_IMPL == MICROPY_FLOAT_IMPL_DOUBLE
+    typedef uint64_t mp_float_int_t;
+    #elif MICROPY_FLOAT_IMPL == MICROPY_FLOAT_IMPL_FLOAT
+    typedef uint32_t mp_float_int_t;
+    #endif
+    union {
+        mp_float_t f;
+        #if MP_ENDIANNESS_LITTLE
+        struct { mp_float_int_t frc:MP_FLOAT_FRAC_BITS, exp:MP_FLOAT_EXP_BITS, sgn:1; } p;
+        #else
+        struct { mp_float_int_t sgn:1, exp:MP_FLOAT_EXP_BITS, frc:MP_FLOAT_FRAC_BITS; } p;
+        #endif
+    } u;
+    u.p.sgn = 0;
+    u.p.exp = (1 << (MP_FLOAT_EXP_BITS - 1)) - 1;
+    if (MP_FLOAT_FRAC_BITS <= 30) {
+        u.p.frc = rand30();
+    } else {
+        u.p.frc = ((uint64_t)rand30() << 30) | (uint64_t)rand30();
+    }
+    return u.f - 1;
+}
+
+STATIC mp_obj_t mod_random_random(void) {
+    return mp_obj_new_float(randfloat());
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_0(mod_random_random_obj, mod_random_random);
+
+STATIC mp_obj_t mod_random_uniform(mp_obj_t a_in, mp_obj_t b_in) {
+    mp_float_t a = mp_obj_get_float(a_in);
+    mp_float_t b = mp_obj_get_float(b_in);
+    return mp_obj_new_float(a + (b - a) * randfloat());
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_2(mod_random_uniform_obj, mod_random_uniform);
+
+#endif
+
+STATIC const mp_rom_map_elem_t mp_module_random_globals_table[] = {
+    { MP_ROM_QSTR(MP_QSTR___name__), MP_ROM_QSTR(MP_QSTR_random) },
+    { MP_ROM_QSTR(MP_QSTR_getrandbits), MP_ROM_PTR(&mod_random_getrandbits_obj) },
+    { MP_ROM_QSTR(MP_QSTR_randrange), MP_ROM_PTR(&mod_random_randrange_obj) },
+    { MP_ROM_QSTR(MP_QSTR_randint), MP_ROM_PTR(&mod_random_randint_obj) },
+    { MP_ROM_QSTR(MP_QSTR_choice), MP_ROM_PTR(&mod_random_choice_obj) },
+#if MICROPY_PY_BUILTINS_FLOAT
+    { MP_ROM_QSTR(MP_QSTR_random), MP_ROM_PTR(&mod_random_random_obj) },
+    { MP_ROM_QSTR(MP_QSTR_uniform), MP_ROM_PTR(&mod_random_uniform_obj) },
+#endif
+};
+
+STATIC MP_DEFINE_CONST_DICT(mp_module_random_globals, mp_module_random_globals_table);
+
+const mp_obj_module_t random_module = {
+    .base = { &mp_type_module },
+    .globals = (mp_obj_dict_t*)&mp_module_random_globals,
+};
+
+#endif // MICROPY_PY_HW_RNG
diff --git a/ports/nrf/modules/ubluepy/modubluepy.c b/ports/nrf/modules/ubluepy/modubluepy.c
new file mode 100644
index 0000000000..b306c065b2
--- /dev/null
+++ b/ports/nrf/modules/ubluepy/modubluepy.c
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "py/obj.h"
+
+#if MICROPY_PY_UBLUEPY
+
+extern const mp_obj_type_t ubluepy_peripheral_type;
+extern const mp_obj_type_t ubluepy_service_type;
+extern const mp_obj_type_t ubluepy_uuid_type;
+extern const mp_obj_type_t ubluepy_characteristic_type;
+extern const mp_obj_type_t ubluepy_delegate_type;
+extern const mp_obj_type_t ubluepy_constants_type;
+extern const mp_obj_type_t ubluepy_scanner_type;
+extern const mp_obj_type_t ubluepy_scan_entry_type;
+
+STATIC const mp_rom_map_elem_t mp_module_ubluepy_globals_table[] = {
+    { MP_ROM_QSTR(MP_QSTR___name__),        MP_ROM_QSTR(MP_QSTR_ubluepy) },
+#if MICROPY_PY_UBLUEPY_PERIPHERAL
+    { MP_ROM_QSTR(MP_QSTR_Peripheral),      MP_ROM_PTR(&ubluepy_peripheral_type) },
+#endif
+#if 0 // MICROPY_PY_UBLUEPY_CENTRAL
+    { MP_ROM_QSTR(MP_QSTR_Central),         MP_ROM_PTR(&ubluepy_central_type) },
+#endif
+#if MICROPY_PY_UBLUEPY_CENTRAL
+    { MP_ROM_QSTR(MP_QSTR_Scanner),         MP_ROM_PTR(&ubluepy_scanner_type) },
+    { MP_ROM_QSTR(MP_QSTR_ScanEntry),       MP_ROM_PTR(&ubluepy_scan_entry_type) },
+#endif
+    { MP_ROM_QSTR(MP_QSTR_DefaultDelegate), MP_ROM_PTR(&ubluepy_delegate_type) },
+    { MP_ROM_QSTR(MP_QSTR_UUID),            MP_ROM_PTR(&ubluepy_uuid_type) },
+    { MP_ROM_QSTR(MP_QSTR_Service),         MP_ROM_PTR(&ubluepy_service_type) },
+    { MP_ROM_QSTR(MP_QSTR_Characteristic),  MP_ROM_PTR(&ubluepy_characteristic_type) },
+    { MP_ROM_QSTR(MP_QSTR_constants),       MP_ROM_PTR(&ubluepy_constants_type) },
+#if MICROPY_PY_UBLUEPY_DESCRIPTOR
+    { MP_ROM_QSTR(MP_QSTR_Descriptor),      MP_ROM_PTR(&ubluepy_descriptor_type) },
+#endif
+};
+
+
+STATIC MP_DEFINE_CONST_DICT(mp_module_ubluepy_globals, mp_module_ubluepy_globals_table);
+
+const mp_obj_module_t mp_module_ubluepy = {
+    .base = { &mp_type_module },
+    .globals = (mp_obj_dict_t*)&mp_module_ubluepy_globals,
+};
+
+#endif // MICROPY_PY_UBLUEPY
diff --git a/ports/nrf/modules/ubluepy/modubluepy.h b/ports/nrf/modules/ubluepy/modubluepy.h
new file mode 100644
index 0000000000..83d86c5dfd
--- /dev/null
+++ b/ports/nrf/modules/ubluepy/modubluepy.h
@@ -0,0 +1,200 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef UBLUEPY_H__
+#define UBLUEPY_H__
+
+/* Examples:
+
+Advertisment:
+
+from ubluepy import Peripheral
+p = Peripheral()
+p.advertise(device_name="MicroPython")
+
+DB setup:
+
+from ubluepy import Service, Characteristic, UUID, Peripheral, constants
+from pyb import LED
+
+def event_handler(id, handle, data):
+    print("BLE event:", id, "handle:", handle)
+    print(data)
+
+    if id == constants.EVT_GAP_CONNECTED:
+        # connected
+        LED(2).on()
+    elif id == constants.EVT_GAP_DISCONNECTED:
+        # disconnect
+        LED(2).off()
+    elif id == 80:
+        print("id 80, data:", data)
+
+# u0 = UUID("0x180D") # HRM service
+# u1 = UUID("0x2A37") # HRM measurement
+
+u0 = UUID("6e400001-b5a3-f393-e0a9-e50e24dcca9e")
+u1 = UUID("6e400002-b5a3-f393-e0a9-e50e24dcca9e")
+u2 = UUID("6e400003-b5a3-f393-e0a9-e50e24dcca9e")
+s = Service(u0)
+c0 = Characteristic(u1, props = Characteristic.PROP_WRITE | Characteristic.PROP_WRITE_WO_RESP)
+c1 = Characteristic(u2, props = Characteristic.PROP_NOTIFY, attrs = Characteristic.ATTR_CCCD)
+s.addCharacteristic(c0)
+s.addCharacteristic(c1)
+p = Peripheral()
+p.addService(s)
+p.setConnectionHandler(event_handler)
+p.advertise(device_name="micr", services=[s])
+
+*/
+
+#include "py/obj.h"
+
+extern const mp_obj_type_t ubluepy_uuid_type;
+extern const mp_obj_type_t ubluepy_service_type;
+extern const mp_obj_type_t ubluepy_characteristic_type;
+extern const mp_obj_type_t ubluepy_peripheral_type;
+extern const mp_obj_type_t ubluepy_scanner_type;
+extern const mp_obj_type_t ubluepy_scan_entry_type;
+extern const mp_obj_type_t ubluepy_constants_type;
+extern const mp_obj_type_t ubluepy_constants_ad_types_type;
+
+typedef enum {
+    UBLUEPY_UUID_16_BIT = 1,
+    UBLUEPY_UUID_128_BIT
+} ubluepy_uuid_type_t;
+
+typedef enum {
+    UBLUEPY_SERVICE_PRIMARY = 1,
+    UBLUEPY_SERVICE_SECONDARY = 2
+} ubluepy_service_type_t;
+
+typedef enum {
+    UBLUEPY_ADDR_TYPE_PUBLIC = 0,
+    UBLUEPY_ADDR_TYPE_RANDOM_STATIC = 1,
+#if 0
+    UBLUEPY_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE = 2,
+    UBLUEPY_ADDR_TYPE_RANDOM_PRIVATE_NON_RESOLVABLE = 3,
+#endif
+} ubluepy_addr_type_t;
+
+typedef enum {
+    UBLUEPY_ROLE_PERIPHERAL,
+    UBLUEPY_ROLE_CENTRAL
+} ubluepy_role_type_t;
+
+typedef struct _ubluepy_uuid_obj_t {
+    mp_obj_base_t       base;
+    ubluepy_uuid_type_t type;
+    uint8_t             value[2];
+    uint8_t             uuid_vs_idx;
+} ubluepy_uuid_obj_t;
+
+typedef struct _ubluepy_peripheral_obj_t {
+    mp_obj_base_t       base;
+    ubluepy_role_type_t role;
+    volatile uint16_t   conn_handle;
+    mp_obj_t            delegate;
+    mp_obj_t            notif_handler;
+    mp_obj_t            conn_handler;
+    mp_obj_t            service_list;
+} ubluepy_peripheral_obj_t;
+
+typedef struct _ubluepy_service_obj_t {
+    mp_obj_base_t              base;
+    uint16_t                   handle;
+    uint8_t                    type;
+    ubluepy_uuid_obj_t       * p_uuid;
+    ubluepy_peripheral_obj_t * p_periph;
+    mp_obj_t                   char_list;
+    uint16_t                   start_handle;
+    uint16_t                   end_handle;
+} ubluepy_service_obj_t;
+
+typedef struct _ubluepy_characteristic_obj_t {
+    mp_obj_base_t           base;
+    uint16_t                handle;
+    ubluepy_uuid_obj_t    * p_uuid;
+    uint16_t                service_handle;
+    uint16_t                user_desc_handle;
+    uint16_t                cccd_handle;
+    uint16_t                sccd_handle;
+    uint8_t                 props;
+    uint8_t                 attrs;
+    ubluepy_service_obj_t * p_service;
+    mp_obj_t                value_data;
+} ubluepy_characteristic_obj_t;
+
+typedef struct _ubluepy_descriptor_obj_t {
+    mp_obj_base_t           base;
+    uint16_t                handle;
+    ubluepy_uuid_obj_t    * p_uuid;
+} ubluepy_descriptor_obj_t;
+
+typedef struct _ubluepy_delegate_obj_t {
+    mp_obj_base_t        base;
+} ubluepy_delegate_obj_t;
+
+typedef struct _ubluepy_advertise_data_t {
+    uint8_t *  p_device_name;
+    uint8_t    device_name_len;
+    mp_obj_t * p_services;
+    uint8_t    num_of_services;
+    uint8_t *  p_data;
+    uint8_t    data_len;
+    bool       connectable;
+} ubluepy_advertise_data_t;
+
+typedef struct _ubluepy_scanner_obj_t {
+    mp_obj_base_t base;
+    mp_obj_t      adv_reports;
+} ubluepy_scanner_obj_t;
+
+typedef struct _ubluepy_scan_entry_obj_t {
+    mp_obj_base_t base;
+    mp_obj_t      addr;
+    uint8_t       addr_type;
+    bool          connectable;
+    int8_t        rssi;
+    mp_obj_t      data;
+} ubluepy_scan_entry_obj_t;
+
+typedef enum _ubluepy_prop_t {
+    UBLUEPY_PROP_BROADCAST      = 0x01,
+    UBLUEPY_PROP_READ           = 0x02,
+    UBLUEPY_PROP_WRITE_WO_RESP  = 0x04,
+    UBLUEPY_PROP_WRITE          = 0x08,
+    UBLUEPY_PROP_NOTIFY         = 0x10,
+    UBLUEPY_PROP_INDICATE       = 0x20,
+    UBLUEPY_PROP_AUTH_SIGNED_WR = 0x40,
+} ubluepy_prop_t;
+
+typedef enum _ubluepy_attr_t {
+    UBLUEPY_ATTR_CCCD           = 0x01,
+    UBLUEPY_ATTR_SCCD           = 0x02,
+} ubluepy_attr_t;
+
+#endif // UBLUEPY_H__
diff --git a/ports/nrf/modules/ubluepy/ubluepy_characteristic.c b/ports/nrf/modules/ubluepy/ubluepy_characteristic.c
new file mode 100644
index 0000000000..8e1d0eb1e4
--- /dev/null
+++ b/ports/nrf/modules/ubluepy/ubluepy_characteristic.c
@@ -0,0 +1,222 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "py/obj.h"
+#include "py/runtime.h"
+
+#if MICROPY_PY_UBLUEPY_PERIPHERAL || MICROPY_PY_UBLUEPY_CENTRAL
+
+#include "modubluepy.h"
+#include "ble_drv.h"
+
+STATIC void ubluepy_characteristic_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) {
+    ubluepy_characteristic_obj_t * self = (ubluepy_characteristic_obj_t *)o;
+
+    mp_printf(print, "Characteristic(handle: 0x" HEX2_FMT ", conn_handle: " HEX2_FMT ")",
+              self->handle, self->p_service->p_periph->conn_handle);
+}
+
+STATIC mp_obj_t ubluepy_characteristic_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) {
+    static const mp_arg_t allowed_args[] = {
+        { MP_QSTR_uuid,  MP_ARG_REQUIRED| MP_ARG_OBJ, {.u_obj = mp_const_none} },
+        { MP_QSTR_props, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = UBLUEPY_PROP_READ | UBLUEPY_PROP_WRITE} },
+        { MP_QSTR_attrs, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} },
+    };
+
+    // parse args
+    mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
+    mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
+
+    ubluepy_characteristic_obj_t *s = m_new_obj(ubluepy_characteristic_obj_t);
+    s->base.type = type;
+
+    mp_obj_t uuid_obj = args[0].u_obj;
+
+    if (uuid_obj == mp_const_none) {
+        return MP_OBJ_FROM_PTR(s);
+    }
+
+    if (MP_OBJ_IS_TYPE(uuid_obj, &ubluepy_uuid_type)) {
+        s->p_uuid = MP_OBJ_TO_PTR(uuid_obj);
+        // (void)sd_characterstic_add(s);
+    } else {
+        nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
+                  "Invalid UUID parameter"));
+    }
+
+    if (args[1].u_int > 0) {
+        s->props = (uint8_t)args[1].u_int;
+    }
+
+    if (args[2].u_int > 0) {
+        s->attrs = (uint8_t)args[2].u_int;
+    }
+
+    // clear pointer to service
+    s->p_service = NULL;
+
+    // clear pointer to char value data
+    s->value_data = NULL;
+
+    return MP_OBJ_FROM_PTR(s);
+}
+
+void char_data_callback(mp_obj_t self_in, uint16_t length, uint8_t * p_data) {
+    ubluepy_characteristic_obj_t * self = MP_OBJ_TO_PTR(self_in);
+    self->value_data = mp_obj_new_bytearray(length, p_data);
+}
+
+/// \method read()
+/// Read Characteristic value.
+///
+STATIC mp_obj_t char_read(mp_obj_t self_in) {
+    ubluepy_characteristic_obj_t * self = MP_OBJ_TO_PTR(self_in);
+
+#if MICROPY_PY_UBLUEPY_CENTRAL
+    // TODO: free any previous allocation of value_data
+
+    ble_drv_attr_c_read(self->p_service->p_periph->conn_handle,
+                        self->handle,
+                        self_in,
+                        char_data_callback);
+
+    return self->value_data;
+#else
+    (void)self;
+    return mp_const_none;
+#endif
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_characteristic_read_obj, char_read);
+
+/// \method write(data, [with_response=False])
+/// Write Characteristic value.
+///
+STATIC mp_obj_t char_write(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+    ubluepy_characteristic_obj_t *self = MP_OBJ_TO_PTR(pos_args[0]);
+    mp_obj_t data                      = pos_args[1];
+
+    static const mp_arg_t allowed_args[] = {
+        { MP_QSTR_with_response, MP_ARG_KW_ONLY | MP_ARG_BOOL, {.u_bool = false } },
+    };
+
+    // parse args
+    mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
+    mp_arg_parse_all(n_args - 2, pos_args + 2, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
+
+    mp_buffer_info_t bufinfo;
+    mp_get_buffer_raise(data, &bufinfo, MP_BUFFER_READ);
+
+    // figure out mode of the Peripheral
+    ubluepy_role_type_t role = self->p_service->p_periph->role;
+
+    if (role == UBLUEPY_ROLE_PERIPHERAL) {
+        if (self->props & UBLUEPY_PROP_NOTIFY) {
+            ble_drv_attr_s_notify(self->p_service->p_periph->conn_handle,
+                                  self->handle,
+                                  bufinfo.len,
+                                  bufinfo.buf);
+        } else {
+            ble_drv_attr_s_write(self->p_service->p_periph->conn_handle,
+                                 self->handle,
+                                 bufinfo.len,
+                                 bufinfo.buf);
+        }
+    } else {
+#if MICROPY_PY_UBLUEPY_CENTRAL
+        bool with_response = args[0].u_bool;
+
+        ble_drv_attr_c_write(self->p_service->p_periph->conn_handle,
+                             self->handle,
+                             bufinfo.len,
+                             bufinfo.buf,
+                             with_response);
+#endif
+    }
+    return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_KW(ubluepy_characteristic_write_obj, 2, char_write);
+
+/// \method properties()
+/// Read Characteristic value properties.
+///
+STATIC mp_obj_t char_properties(mp_obj_t self_in) {
+    ubluepy_characteristic_obj_t * self = MP_OBJ_TO_PTR(self_in);
+    return MP_OBJ_NEW_SMALL_INT(self->props);
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_characteristic_get_properties_obj, char_properties);
+
+/// \method uuid()
+/// Get UUID instance of the characteristic.
+///
+STATIC mp_obj_t char_uuid(mp_obj_t self_in) {
+    ubluepy_characteristic_obj_t * self = MP_OBJ_TO_PTR(self_in);
+    return MP_OBJ_FROM_PTR(self->p_uuid);
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_characteristic_get_uuid_obj, char_uuid);
+
+
+STATIC const mp_rom_map_elem_t ubluepy_characteristic_locals_dict_table[] = {
+    { MP_ROM_QSTR(MP_QSTR_read),                MP_ROM_PTR(&ubluepy_characteristic_read_obj) },
+    { MP_ROM_QSTR(MP_QSTR_write),               MP_ROM_PTR(&ubluepy_characteristic_write_obj) },
+#if 0
+    { MP_ROM_QSTR(MP_QSTR_supportsRead),        MP_ROM_PTR(&ubluepy_characteristic_supports_read_obj) },
+    { MP_ROM_QSTR(MP_QSTR_propertiesToString),  MP_ROM_PTR(&ubluepy_characteristic_properties_to_str_obj) },
+    { MP_ROM_QSTR(MP_QSTR_getHandle),           MP_ROM_PTR(&ubluepy_characteristic_get_handle_obj) },
+
+    // Properties
+    { MP_ROM_QSTR(MP_QSTR_peripheral),          MP_ROM_PTR(&ubluepy_characteristic_get_peripheral_obj) },
+#endif
+    { MP_ROM_QSTR(MP_QSTR_uuid),                MP_ROM_PTR(&ubluepy_characteristic_get_uuid_obj) },
+    { MP_ROM_QSTR(MP_QSTR_properties),          MP_ROM_PTR(&ubluepy_characteristic_get_properties_obj) },
+
+    { MP_ROM_QSTR(MP_QSTR_PROP_BROADCAST),      MP_ROM_INT(UBLUEPY_PROP_BROADCAST) },
+    { MP_ROM_QSTR(MP_QSTR_PROP_READ),           MP_ROM_INT(UBLUEPY_PROP_READ) },
+    { MP_ROM_QSTR(MP_QSTR_PROP_WRITE_WO_RESP),  MP_ROM_INT(UBLUEPY_PROP_WRITE_WO_RESP) },
+    { MP_ROM_QSTR(MP_QSTR_PROP_WRITE),          MP_ROM_INT(UBLUEPY_PROP_WRITE) },
+    { MP_ROM_QSTR(MP_QSTR_PROP_NOTIFY),         MP_ROM_INT(UBLUEPY_PROP_NOTIFY) },
+    { MP_ROM_QSTR(MP_QSTR_PROP_INDICATE),       MP_ROM_INT(UBLUEPY_PROP_INDICATE) },
+    { MP_ROM_QSTR(MP_QSTR_PROP_AUTH_SIGNED_WR), MP_ROM_INT(UBLUEPY_PROP_AUTH_SIGNED_WR) },
+
+#if MICROPY_PY_UBLUEPY_PERIPHERAL
+    { MP_ROM_QSTR(MP_QSTR_ATTR_CCCD),           MP_ROM_INT(UBLUEPY_ATTR_CCCD) },
+#endif
+
+#if MICROPY_PY_UBLUEPY_CENTRAL
+    { MP_ROM_QSTR(MP_QSTR_PROP_AUTH_SIGNED_WR), MP_ROM_INT(UBLUEPY_ATTR_SCCD) },
+#endif
+};
+
+STATIC MP_DEFINE_CONST_DICT(ubluepy_characteristic_locals_dict, ubluepy_characteristic_locals_dict_table);
+
+const mp_obj_type_t ubluepy_characteristic_type = {
+    { &mp_type_type },
+    .name = MP_QSTR_Characteristic,
+    .print = ubluepy_characteristic_print,
+    .make_new = ubluepy_characteristic_make_new,
+    .locals_dict = (mp_obj_dict_t*)&ubluepy_characteristic_locals_dict
+};
+
+#endif // MICROPY_PY_UBLUEPY_PERIPHERAL || MICROPY_PY_UBLUEPY_CENTRAL
diff --git a/ports/nrf/modules/ubluepy/ubluepy_constants.c b/ports/nrf/modules/ubluepy/ubluepy_constants.c
new file mode 100644
index 0000000000..14e433e6eb
--- /dev/null
+++ b/ports/nrf/modules/ubluepy/ubluepy_constants.c
@@ -0,0 +1,99 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "py/obj.h"
+#include "py/runtime.h"
+
+#if MICROPY_PY_UBLUEPY
+
+#include "modubluepy.h"
+
+STATIC const mp_rom_map_elem_t ubluepy_constants_ad_types_locals_dict_table[] = {
+    // GAP AD Types
+    { MP_ROM_QSTR(MP_QSTR_AD_TYPE_FLAGS),                              MP_ROM_INT(0x01) },
+    { MP_ROM_QSTR(MP_QSTR_AD_TYPE_16BIT_SERVICE_UUID_MORE_AVAILABLE),  MP_ROM_INT(0x02) },
+    { MP_ROM_QSTR(MP_QSTR_AD_TYPE_16BIT_SERVICE_UUID_COMPLETE),        MP_ROM_INT(0x03) },
+    { MP_ROM_QSTR(MP_QSTR_AD_TYPE_32BIT_SERVICE_UUID_MORE_AVAILABLE),  MP_ROM_INT(0x04) },
+    { MP_ROM_QSTR(MP_QSTR_AD_TYPE_32BIT_SERVICE_UUID_COMPLETE),        MP_ROM_INT(0x05) },
+    { MP_ROM_QSTR(MP_QSTR_AD_TYPE_128BIT_SERVICE_UUID_MORE_AVAILABLE), MP_ROM_INT(0x06) },
+    { MP_ROM_QSTR(MP_QSTR_AD_TYPE_128BIT_SERVICE_UUID_COMPLETE),       MP_ROM_INT(0x07) },
+    { MP_ROM_QSTR(MP_QSTR_AD_TYPE_SHORT_LOCAL_NAME),                   MP_ROM_INT(0x08) },
+    { MP_ROM_QSTR(MP_QSTR_AD_TYPE_COMPLETE_LOCAL_NAME),                MP_ROM_INT(0x09) },
+    { MP_ROM_QSTR(MP_QSTR_AD_TYPE_TX_POWER_LEVEL),                     MP_ROM_INT(0x0A) },
+    { MP_ROM_QSTR(MP_QSTR_AD_TYPE_CLASS_OF_DEVICE),                    MP_ROM_INT(0x0D) },
+    { MP_ROM_QSTR(MP_QSTR_AD_TYPE_SIMPLE_PAIRING_HASH_C),              MP_ROM_INT(0x0E) },
+    { MP_ROM_QSTR(MP_QSTR_AD_TYPE_SIMPLE_PAIRING_RANDOMIZER_R),        MP_ROM_INT(0x0F) },
+    { MP_ROM_QSTR(MP_QSTR_AD_TYPE_SECURITY_MANAGER_TK_VALUE),          MP_ROM_INT(0x10) },
+    { MP_ROM_QSTR(MP_QSTR_AD_TYPE_SECURITY_MANAGER_OOB_FLAGS),         MP_ROM_INT(0x11) },
+    { MP_ROM_QSTR(MP_QSTR_AD_TYPE_SLAVE_CONNECTION_INTERVAL_RANGE),    MP_ROM_INT(0x12) },
+    { MP_ROM_QSTR(MP_QSTR_AD_TYPE_SOLICITED_SERVICE_UUIDS_16BIT),      MP_ROM_INT(0x14) },
+    { MP_ROM_QSTR(MP_QSTR_AD_TYPE_SOLICITED_SERVICE_UUIDS_128BIT),     MP_ROM_INT(0x15) },
+    { MP_ROM_QSTR(MP_QSTR_AD_TYPE_SERVICE_DATA),                       MP_ROM_INT(0x16) },
+    { MP_ROM_QSTR(MP_QSTR_AD_TYPE_PUBLIC_TARGET_ADDRESS),              MP_ROM_INT(0x17) },
+    { MP_ROM_QSTR(MP_QSTR_AD_TYPE_RANDOM_TARGET_ADDRESS),              MP_ROM_INT(0x18) },
+    { MP_ROM_QSTR(MP_QSTR_AD_TYPE_APPEARANCE),                         MP_ROM_INT(0x19) },
+    { MP_ROM_QSTR(MP_QSTR_AD_TYPE_ADVERTISING_INTERVAL),               MP_ROM_INT(0x1A) },
+    { MP_ROM_QSTR(MP_QSTR_AD_TYPE_LE_BLUETOOTH_DEVICE_ADDRESS),        MP_ROM_INT(0x1B) },
+    { MP_ROM_QSTR(MP_QSTR_AD_TYPE_LE_ROLE),                            MP_ROM_INT(0x1C) },
+    { MP_ROM_QSTR(MP_QSTR_AD_TYPE_SIMPLE_PAIRING_HASH_C256),           MP_ROM_INT(0x1D) },
+    { MP_ROM_QSTR(MP_QSTR_AD_TYPE_SIMPLE_PAIRING_RANDOMIZER_R256),     MP_ROM_INT(0x1E) },
+    { MP_ROM_QSTR(MP_QSTR_AD_TYPE_SERVICE_DATA_32BIT_UUID),            MP_ROM_INT(0x20) },
+    { MP_ROM_QSTR(MP_QSTR_AD_TYPE_SERVICE_DATA_128BIT_UUID),           MP_ROM_INT(0x21) },
+    { MP_ROM_QSTR(MP_QSTR_AD_TYPE_URI),                                MP_ROM_INT(0x24) },
+    { MP_ROM_QSTR(MP_QSTR_AD_TYPE_3D_INFORMATION_DATA),                MP_ROM_INT(0x3D) },
+    { MP_ROM_QSTR(MP_QSTR_AD_TYPE_MANUFACTURER_SPECIFIC_DATA),         MP_ROM_INT(0xFF) },
+};
+
+STATIC MP_DEFINE_CONST_DICT(ubluepy_constants_ad_types_locals_dict, ubluepy_constants_ad_types_locals_dict_table);
+
+const mp_obj_type_t ubluepy_constants_ad_types_type = {
+    { &mp_type_type },
+    .name = MP_QSTR_ad_types,
+    .locals_dict = (mp_obj_dict_t*)&ubluepy_constants_ad_types_locals_dict
+};
+
+STATIC const mp_rom_map_elem_t ubluepy_constants_locals_dict_table[] = {
+    // GAP events
+    { MP_ROM_QSTR(MP_QSTR_EVT_GAP_CONNECTED),       MP_ROM_INT(16) },
+    { MP_ROM_QSTR(MP_QSTR_EVT_GAP_DISCONNECTED),    MP_ROM_INT(17) },
+    { MP_ROM_QSTR(MP_QSTR_EVT_GATTS_WRITE),         MP_ROM_INT(80) },
+    { MP_ROM_QSTR(MP_QSTR_UUID_CCCD),               MP_ROM_INT(0x2902) },
+
+    { MP_ROM_QSTR(MP_QSTR_ADDR_TYPE_PUBLIC),        MP_ROM_INT(UBLUEPY_ADDR_TYPE_PUBLIC) },
+    { MP_ROM_QSTR(MP_QSTR_ADDR_TYPE_RANDOM_STATIC), MP_ROM_INT(UBLUEPY_ADDR_TYPE_RANDOM_STATIC) },
+
+    { MP_ROM_QSTR(MP_QSTR_ad_types),                MP_ROM_PTR(&ubluepy_constants_ad_types_type) },
+};
+
+STATIC MP_DEFINE_CONST_DICT(ubluepy_constants_locals_dict, ubluepy_constants_locals_dict_table);
+
+const mp_obj_type_t ubluepy_constants_type = {
+    { &mp_type_type },
+    .name = MP_QSTR_constants,
+    .locals_dict = (mp_obj_dict_t*)&ubluepy_constants_locals_dict
+};
+
+#endif // MICROPY_PY_UBLUEPY
diff --git a/ports/nrf/modules/ubluepy/ubluepy_delegate.c b/ports/nrf/modules/ubluepy/ubluepy_delegate.c
new file mode 100644
index 0000000000..07bb7f4928
--- /dev/null
+++ b/ports/nrf/modules/ubluepy/ubluepy_delegate.c
@@ -0,0 +1,89 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "py/obj.h"
+#include "py/runtime.h"
+
+#if MICROPY_PY_UBLUEPY_PERIPHERAL || MICROPY_PY_UBLUEPY_CENTRAL
+
+#include "modubluepy.h"
+
+STATIC void ubluepy_delegate_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) {
+    ubluepy_delegate_obj_t * self = (ubluepy_delegate_obj_t *)o;
+    (void)self;
+    mp_printf(print, "DefaultDelegate()");
+}
+
+STATIC mp_obj_t ubluepy_delegate_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) {
+    ubluepy_delegate_obj_t *s = m_new_obj(ubluepy_delegate_obj_t);
+    s->base.type = type;
+
+    return MP_OBJ_FROM_PTR(s);
+}
+
+/// \method handleConnection()
+/// Handle connection events.
+///
+STATIC mp_obj_t delegate_handle_conn(mp_obj_t self_in) {
+    ubluepy_delegate_obj_t *self = MP_OBJ_TO_PTR(self_in);
+
+    (void)self;
+
+    return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_delegate_handle_conn_obj, delegate_handle_conn);
+
+/// \method handleNotification()
+/// Handle notification events.
+///
+STATIC mp_obj_t delegate_handle_notif(mp_obj_t self_in) {
+    ubluepy_delegate_obj_t *self = MP_OBJ_TO_PTR(self_in);
+
+    (void)self;
+
+    return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_delegate_handle_notif_obj, delegate_handle_notif);
+
+STATIC const mp_rom_map_elem_t ubluepy_delegate_locals_dict_table[] = {
+    { MP_ROM_QSTR(MP_QSTR_handleConnection),   MP_ROM_PTR(&ubluepy_delegate_handle_conn_obj) },
+    { MP_ROM_QSTR(MP_QSTR_handleNotification), MP_ROM_PTR(&ubluepy_delegate_handle_notif_obj) },
+#if 0
+	{ MP_ROM_QSTR(MP_QSTR_handleDiscovery),    MP_ROM_PTR(&ubluepy_delegate_handle_disc_obj) },
+#endif
+};
+
+STATIC MP_DEFINE_CONST_DICT(ubluepy_delegate_locals_dict, ubluepy_delegate_locals_dict_table);
+
+const mp_obj_type_t ubluepy_delegate_type = {
+    { &mp_type_type },
+    .name = MP_QSTR_DefaultDelegate,
+    .print = ubluepy_delegate_print,
+    .make_new = ubluepy_delegate_make_new,
+    .locals_dict = (mp_obj_dict_t*)&ubluepy_delegate_locals_dict
+};
+
+#endif // MICROPY_PY_UBLUEPY_PERIPHERAL || MICROPY_PY_UBLUEPY_CENTRAL
diff --git a/ports/nrf/modules/ubluepy/ubluepy_descriptor.c b/ports/nrf/modules/ubluepy/ubluepy_descriptor.c
new file mode 100644
index 0000000000..b15301954d
--- /dev/null
+++ b/ports/nrf/modules/ubluepy/ubluepy_descriptor.c
@@ -0,0 +1,82 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "py/obj.h"
+#include "py/runtime.h"
+#include "py/objstr.h"
+#include "py/misc.h"
+
+#if MICROPY_PY_UBLUEPY
+
+#include "modubluepy.h"
+#include "ble_drv.h"
+
+STATIC void ubluepy_descriptor_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) {
+    ubluepy_descriptor_obj_t * self = (ubluepy_descriptor_obj_t *)o;
+
+    mp_printf(print, "Descriptor(uuid: 0x" HEX2_FMT HEX2_FMT ")",
+              self->p_uuid->value[1], self->p_uuid->value[0]);
+}
+
+STATIC mp_obj_t ubluepy_descriptor_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) {
+
+    enum { ARG_NEW_UUID };
+
+    static const mp_arg_t allowed_args[] = {
+        { ARG_NEW_UUID, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
+    };
+
+    // parse args
+    mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
+    mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
+
+    ubluepy_descriptor_obj_t * s = m_new_obj(ubluepy_descriptor_obj_t);
+    s->base.type = type;
+
+    mp_obj_t uuid_obj = args[ARG_NEW_UUID].u_obj;
+
+    (void)uuid_obj;
+
+    return MP_OBJ_FROM_PTR(s);
+}
+
+STATIC const mp_rom_map_elem_t ubluepy_descriptor_locals_dict_table[] = {
+#if 0
+    { MP_ROM_QSTR(MP_QSTR_binVal), MP_ROM_PTR(&ubluepy_descriptor_bin_val_obj) },
+#endif
+};
+
+STATIC MP_DEFINE_CONST_DICT(ubluepy_descriptor_locals_dict, ubluepy_descriptor_locals_dict_table);
+
+const mp_obj_type_t ubluepy_descriptor_type = {
+    { &mp_type_type },
+    .name = MP_QSTR_Descriptor,
+    .print = ubluepy_descriptor_print,
+    .make_new = ubluepy_descriptor_make_new,
+    .locals_dict = (mp_obj_dict_t*)&ubluepy_descriptor_locals_dict
+};
+
+#endif // MICROPY_PY_UBLUEPY
diff --git a/ports/nrf/modules/ubluepy/ubluepy_peripheral.c b/ports/nrf/modules/ubluepy/ubluepy_peripheral.c
new file mode 100644
index 0000000000..48e4673748
--- /dev/null
+++ b/ports/nrf/modules/ubluepy/ubluepy_peripheral.c
@@ -0,0 +1,498 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <string.h>
+#include "py/obj.h"
+#include "py/runtime.h"
+#include "py/objstr.h"
+#include "py/objlist.h"
+
+#if MICROPY_PY_UBLUEPY
+
+#include "ble_drv.h"
+
+STATIC void ubluepy_peripheral_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) {
+    ubluepy_peripheral_obj_t * self = (ubluepy_peripheral_obj_t *)o;
+    (void)self;
+    mp_printf(print, "Peripheral(conn_handle: " HEX2_FMT ")",
+              self->conn_handle);
+}
+
+STATIC void gap_event_handler(mp_obj_t self_in, uint16_t event_id, uint16_t conn_handle, uint16_t length, uint8_t * data) {
+    ubluepy_peripheral_obj_t *self = MP_OBJ_TO_PTR(self_in);
+
+    if (event_id == 16) {                // connect event
+        self->conn_handle = conn_handle;
+    } else if (event_id == 17) {         // disconnect event
+        self->conn_handle = 0xFFFF;      // invalid connection handle
+    }
+
+    if (self->conn_handler != mp_const_none) {
+        mp_obj_t args[3];
+        mp_uint_t num_of_args = 3;
+        args[0] = MP_OBJ_NEW_SMALL_INT(event_id);
+        args[1] = MP_OBJ_NEW_SMALL_INT(conn_handle);
+        if (data != NULL) {
+            args[2] = mp_obj_new_bytearray_by_ref(length, data);
+        } else {
+            args[2] = mp_const_none;
+        }
+
+        // for now hard-code all events to conn_handler
+        mp_call_function_n_kw(self->conn_handler, num_of_args, 0, args);
+    }
+
+    (void)self;
+}
+
+STATIC void gatts_event_handler(mp_obj_t self_in, uint16_t event_id, uint16_t attr_handle, uint16_t length, uint8_t * data) {
+    ubluepy_peripheral_obj_t *self = MP_OBJ_TO_PTR(self_in);
+
+    if (self->conn_handler != mp_const_none) {
+        mp_obj_t args[3];
+        mp_uint_t num_of_args = 3;
+        args[0] = MP_OBJ_NEW_SMALL_INT(event_id);
+        args[1] = MP_OBJ_NEW_SMALL_INT(attr_handle);
+        if (data != NULL) {
+            args[2] = mp_obj_new_bytearray_by_ref(length, data);
+        } else {
+            args[2] = mp_const_none;
+        }
+
+        // for now hard-code all events to conn_handler
+        mp_call_function_n_kw(self->conn_handler, num_of_args, 0, args);
+    }
+
+}
+
+#if MICROPY_PY_UBLUEPY_CENTRAL
+
+static volatile bool m_disc_evt_received;
+
+STATIC void gattc_event_handler(mp_obj_t self_in, uint16_t event_id, uint16_t attr_handle, uint16_t length, uint8_t * data) {
+    ubluepy_peripheral_obj_t *self = MP_OBJ_TO_PTR(self_in);
+    (void)self;
+    m_disc_evt_received = true;
+}
+#endif
+
+STATIC mp_obj_t ubluepy_peripheral_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) {
+    enum {
+        ARG_NEW_DEVICE_ADDR,
+        ARG_NEW_ADDR_TYPE
+    };
+
+    static const mp_arg_t allowed_args[] = {
+        { ARG_NEW_DEVICE_ADDR, MP_ARG_OBJ, {.u_obj = mp_const_none} },
+        { ARG_NEW_ADDR_TYPE,   MP_ARG_OBJ, {.u_obj = mp_const_none} },
+    };
+
+    // parse args
+    mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
+    mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
+
+    ubluepy_peripheral_obj_t *s = m_new_obj(ubluepy_peripheral_obj_t);
+    s->base.type = type;
+
+    s->delegate      = mp_const_none;
+    s->conn_handler  = mp_const_none;
+    s->notif_handler = mp_const_none;
+    s->conn_handle   = 0xFFFF;
+
+    s->service_list = mp_obj_new_list(0, NULL);
+
+    return MP_OBJ_FROM_PTR(s);
+}
+
+/// \method withDelegate(DefaultDelegate)
+/// Set delegate instance for handling Bluetooth LE events.
+///
+STATIC mp_obj_t peripheral_with_delegate(mp_obj_t self_in, mp_obj_t delegate) {
+    ubluepy_peripheral_obj_t *self = MP_OBJ_TO_PTR(self_in);
+
+    self->delegate = delegate;
+
+    return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_2(ubluepy_peripheral_with_delegate_obj, peripheral_with_delegate);
+
+/// \method setNotificationHandler(func)
+/// Set handler for Bluetooth LE notification events.
+///
+STATIC mp_obj_t peripheral_set_notif_handler(mp_obj_t self_in, mp_obj_t func) {
+    ubluepy_peripheral_obj_t *self = MP_OBJ_TO_PTR(self_in);
+
+    self->notif_handler = func;
+
+    return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_2(ubluepy_peripheral_set_notif_handler_obj, peripheral_set_notif_handler);
+
+/// \method setConnectionHandler(func)
+/// Set handler for Bluetooth LE connection events.
+///
+STATIC mp_obj_t peripheral_set_conn_handler(mp_obj_t self_in, mp_obj_t func) {
+    ubluepy_peripheral_obj_t *self = MP_OBJ_TO_PTR(self_in);
+
+    self->conn_handler = func;
+
+    return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_2(ubluepy_peripheral_set_conn_handler_obj, peripheral_set_conn_handler);
+
+#if MICROPY_PY_UBLUEPY_PERIPHERAL
+
+/// \method advertise(device_name, [service=[service1, service2, ...]], [data=bytearray], [connectable=True])
+/// Start advertising. Connectable advertisment type by default.
+///
+STATIC mp_obj_t peripheral_advertise(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+    static const mp_arg_t allowed_args[] = {
+        { MP_QSTR_device_name, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} },
+        { MP_QSTR_services,    MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} },
+        { MP_QSTR_data,        MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} },
+        { MP_QSTR_connectable, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} },
+    };
+
+    ubluepy_peripheral_obj_t *self = MP_OBJ_TO_PTR(pos_args[0]);
+
+    self->role = UBLUEPY_ROLE_PERIPHERAL;
+
+    // parse args
+    mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
+    mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
+
+    // ubluepy_peripheral_obj_t *self = MP_OBJ_TO_PTR(pos_args[0]);
+    mp_obj_t device_name_obj = args[0].u_obj;
+    mp_obj_t service_obj     = args[1].u_obj;
+    mp_obj_t data_obj        = args[2].u_obj;
+    mp_obj_t connectable_obj = args[3].u_obj;
+
+    ubluepy_advertise_data_t adv_data;
+    memset(&adv_data, 0, sizeof(ubluepy_advertise_data_t));
+
+    if (device_name_obj != mp_const_none && MP_OBJ_IS_STR(device_name_obj)) {
+        GET_STR_DATA_LEN(device_name_obj, str_data, str_len);
+
+        adv_data.p_device_name = (uint8_t *)str_data;
+        adv_data.device_name_len = str_len;
+    }
+
+    if (service_obj != mp_const_none) {
+        mp_obj_t * services = NULL;
+        mp_uint_t  num_services;
+        mp_obj_get_array(service_obj, &num_services, &services);
+
+        if (num_services > 0) {
+            adv_data.p_services      = services;
+            adv_data.num_of_services = num_services;
+        }
+    }
+
+    if (data_obj != mp_const_none) {
+        mp_buffer_info_t bufinfo;
+        mp_get_buffer_raise(data_obj, &bufinfo, MP_BUFFER_READ);
+
+        if (bufinfo.len > 0) {
+            adv_data.p_data   = bufinfo.buf;
+            adv_data.data_len = bufinfo.len;
+        }
+    }
+
+    adv_data.connectable = true;
+    if (connectable_obj != mp_const_none && !(mp_obj_is_true(connectable_obj))) {
+        adv_data.connectable = false;
+    } else {
+        ble_drv_gap_event_handler_set(MP_OBJ_FROM_PTR(self), gap_event_handler);
+        ble_drv_gatts_event_handler_set(MP_OBJ_FROM_PTR(self), gatts_event_handler);
+    }
+
+    (void)ble_drv_advertise_data(&adv_data);
+
+    return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_KW(ubluepy_peripheral_advertise_obj, 0, peripheral_advertise);
+
+/// \method advertise_stop()
+/// Stop advertisment if any onging advertisment.
+///
+STATIC mp_obj_t peripheral_advertise_stop(mp_obj_t self_in) {
+    ubluepy_peripheral_obj_t *self = MP_OBJ_TO_PTR(self_in);
+
+    (void)self;
+
+    ble_drv_advertise_stop();
+
+    return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_peripheral_advertise_stop_obj, peripheral_advertise_stop);
+
+#endif // MICROPY_PY_UBLUEPY_PERIPHERAL
+
+/// \method disconnect()
+/// disconnect connection.
+///
+STATIC mp_obj_t peripheral_disconnect(mp_obj_t self_in) {
+    ubluepy_peripheral_obj_t *self = MP_OBJ_TO_PTR(self_in);
+
+    (void)self;
+
+    return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_peripheral_disconnect_obj, peripheral_disconnect);
+
+/// \method addService(Service)
+/// Add service to the Peripheral.
+///
+STATIC mp_obj_t peripheral_add_service(mp_obj_t self_in, mp_obj_t service) {
+    ubluepy_peripheral_obj_t * self = MP_OBJ_TO_PTR(self_in);
+    ubluepy_service_obj_t    * p_service = MP_OBJ_TO_PTR(service);
+
+    p_service->p_periph = self;
+
+    mp_obj_list_append(self->service_list, service);
+
+    return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_2(ubluepy_peripheral_add_service_obj, peripheral_add_service);
+
+/// \method getServices()
+/// Return list with all service registered in the Peripheral.
+///
+STATIC mp_obj_t peripheral_get_services(mp_obj_t self_in) {
+    ubluepy_peripheral_obj_t * self = MP_OBJ_TO_PTR(self_in);
+
+    return self->service_list;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_peripheral_get_services_obj, peripheral_get_services);
+
+#if MICROPY_PY_UBLUEPY_CENTRAL
+
+void static disc_add_service(mp_obj_t self, ble_drv_service_data_t * p_service_data) {
+    ubluepy_service_obj_t * p_service = m_new_obj(ubluepy_service_obj_t);
+    p_service->base.type = &ubluepy_service_type;
+
+    ubluepy_uuid_obj_t * p_uuid = m_new_obj(ubluepy_uuid_obj_t);
+    p_uuid->base.type = &ubluepy_uuid_type;
+
+    p_service->p_uuid = p_uuid;
+
+    p_uuid->type = p_service_data->uuid_type;
+    p_uuid->value[0] = p_service_data->uuid & 0xFF;
+    p_uuid->value[1] = p_service_data->uuid >> 8;
+
+    p_service->handle       = p_service_data->start_handle;
+    p_service->start_handle = p_service_data->start_handle;
+    p_service->end_handle   = p_service_data->end_handle;
+
+    p_service->char_list = mp_obj_new_list(0, NULL);
+
+    peripheral_add_service(self, MP_OBJ_FROM_PTR(p_service));
+}
+
+void static disc_add_char(mp_obj_t service_in, ble_drv_char_data_t * p_desc_data) {
+    ubluepy_service_obj_t        * p_service   = MP_OBJ_TO_PTR(service_in);
+    ubluepy_characteristic_obj_t * p_char = m_new_obj(ubluepy_characteristic_obj_t);
+    p_char->base.type = &ubluepy_characteristic_type;
+
+    ubluepy_uuid_obj_t * p_uuid = m_new_obj(ubluepy_uuid_obj_t);
+    p_uuid->base.type = &ubluepy_uuid_type;
+
+    p_char->p_uuid = p_uuid;
+
+    p_uuid->type = p_desc_data->uuid_type;
+    p_uuid->value[0] = p_desc_data->uuid & 0xFF;
+    p_uuid->value[1] = p_desc_data->uuid >> 8;
+
+    // add characteristic specific data from discovery
+    p_char->props  = p_desc_data->props;
+    p_char->handle = p_desc_data->value_handle;
+
+    // equivalent to ubluepy_service.c - service_add_characteristic()
+    // except the registration of the characteristic towards the bluetooth stack
+    p_char->service_handle = p_service->handle;
+    p_char->p_service      = p_service;
+
+    mp_obj_list_append(p_service->char_list, MP_OBJ_FROM_PTR(p_char));
+}
+
+/// \method connect(device_address [, addr_type=ADDR_TYPE_PUBLIC])
+/// Connect to device peripheral with the given device address.
+/// addr_type can be either ADDR_TYPE_PUBLIC (default) or
+/// ADDR_TYPE_RANDOM_STATIC.
+///
+STATIC mp_obj_t peripheral_connect(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+    ubluepy_peripheral_obj_t *self = MP_OBJ_TO_PTR(pos_args[0]);
+    mp_obj_t dev_addr              = pos_args[1];
+
+    self->role = UBLUEPY_ROLE_CENTRAL;
+
+    static const mp_arg_t allowed_args[] = {
+        { MP_QSTR_addr_type, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = UBLUEPY_ADDR_TYPE_PUBLIC } },
+    };
+
+    // parse args
+    mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
+    mp_arg_parse_all(n_args - 2, pos_args + 2, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
+
+    uint8_t addr_type = args[0].u_int;
+
+    ble_drv_gap_event_handler_set(MP_OBJ_FROM_PTR(self), gap_event_handler);
+
+    if (MP_OBJ_IS_STR(dev_addr)) {
+        GET_STR_DATA_LEN(dev_addr, str_data, str_len);
+        if (str_len == 17) { // Example "11:22:33:aa:bb:cc"
+
+            uint8_t * p_addr = m_new(uint8_t, 6);
+
+            p_addr[0]  = unichar_xdigit_value(str_data[16]);
+            p_addr[0] += unichar_xdigit_value(str_data[15]) << 4;
+            p_addr[1]  = unichar_xdigit_value(str_data[13]);
+            p_addr[1] += unichar_xdigit_value(str_data[12]) << 4;
+            p_addr[2]  = unichar_xdigit_value(str_data[10]);
+            p_addr[2] += unichar_xdigit_value(str_data[9]) << 4;
+            p_addr[3]  = unichar_xdigit_value(str_data[7]);
+            p_addr[3] += unichar_xdigit_value(str_data[6]) << 4;
+            p_addr[4]  = unichar_xdigit_value(str_data[4]);
+            p_addr[4] += unichar_xdigit_value(str_data[3]) << 4;
+            p_addr[5]  = unichar_xdigit_value(str_data[1]);
+            p_addr[5] += unichar_xdigit_value(str_data[0]) << 4;
+
+            ble_drv_connect(p_addr, addr_type);
+
+            m_del(uint8_t, p_addr, 6);
+        }
+    }
+
+    // block until connected
+    while (self->conn_handle == 0xFFFF) {
+        ;
+    }
+
+    ble_drv_gattc_event_handler_set(MP_OBJ_FROM_PTR(self), gattc_event_handler);
+
+    bool service_disc_retval = ble_drv_discover_services(self, self->conn_handle, 0x0001, disc_add_service);
+
+    // continue discovery of primary services ...
+    while (service_disc_retval) {
+        // locate the last added service
+        mp_obj_t * services = NULL;
+        mp_uint_t  num_services;
+        mp_obj_get_array(self->service_list, &num_services, &services);
+
+        ubluepy_service_obj_t * p_service = (ubluepy_service_obj_t *)services[num_services - 1];
+
+        service_disc_retval = ble_drv_discover_services(self,
+                                                        self->conn_handle,
+                                                        p_service->end_handle + 1,
+                                                        disc_add_service);
+    }
+
+    // For each service perform a characteristic discovery
+    mp_obj_t * services = NULL;
+    mp_uint_t  num_services;
+    mp_obj_get_array(self->service_list, &num_services, &services);
+
+    for (uint16_t s = 0; s < num_services; s++) {
+        ubluepy_service_obj_t * p_service = (ubluepy_service_obj_t *)services[s];
+        bool char_disc_retval = ble_drv_discover_characteristic(p_service,
+                                                                self->conn_handle,
+                                                                p_service->start_handle,
+                                                                p_service->end_handle,
+                                                                disc_add_char);
+        // continue discovery of characteristics ...
+        while (char_disc_retval) {
+            mp_obj_t * characteristics = NULL;
+            mp_uint_t  num_chars;
+            mp_obj_get_array(p_service->char_list, &num_chars, &characteristics);
+
+            ubluepy_characteristic_obj_t * p_char = (ubluepy_characteristic_obj_t *)characteristics[num_chars - 1];
+            uint16_t next_handle = p_char->handle + 1;
+            if ((next_handle) < p_service->end_handle) {
+                char_disc_retval = ble_drv_discover_characteristic(p_service,
+                                                                   self->conn_handle,
+                                                                   next_handle,
+                                                                   p_service->end_handle,
+                                                                   disc_add_char);
+            } else {
+                break;
+            }
+        }
+    }
+
+    return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_KW(ubluepy_peripheral_connect_obj, 2, peripheral_connect);
+
+#endif
+
+STATIC const mp_rom_map_elem_t ubluepy_peripheral_locals_dict_table[] = {
+    { MP_ROM_QSTR(MP_QSTR_withDelegate),           MP_ROM_PTR(&ubluepy_peripheral_with_delegate_obj) },
+    { MP_ROM_QSTR(MP_QSTR_setNotificationHandler), MP_ROM_PTR(&ubluepy_peripheral_set_notif_handler_obj) },
+    { MP_ROM_QSTR(MP_QSTR_setConnectionHandler),   MP_ROM_PTR(&ubluepy_peripheral_set_conn_handler_obj) },
+    { MP_ROM_QSTR(MP_QSTR_getServices),            MP_ROM_PTR(&ubluepy_peripheral_get_services_obj) },
+#if MICROPY_PY_UBLUEPY_CENTRAL
+    { MP_ROM_QSTR(MP_QSTR_connect),                MP_ROM_PTR(&ubluepy_peripheral_connect_obj) },
+#if 0
+    { MP_ROM_QSTR(MP_QSTR_disconnect),             MP_ROM_PTR(&ubluepy_peripheral_disconnect_obj) },
+    { MP_ROM_QSTR(MP_QSTR_getServiceByUUID),       MP_ROM_PTR(&ubluepy_peripheral_get_service_by_uuid_obj) },
+    { MP_ROM_QSTR(MP_QSTR_getCharacteristics),     MP_ROM_PTR(&ubluepy_peripheral_get_chars_obj) },
+    { MP_ROM_QSTR(MP_QSTR_getDescriptors),         MP_ROM_PTR(&ubluepy_peripheral_get_descs_obj) },
+    { MP_ROM_QSTR(MP_QSTR_waitForNotifications),   MP_ROM_PTR(&ubluepy_peripheral_wait_for_notif_obj) },
+    { MP_ROM_QSTR(MP_QSTR_writeCharacteristic),    MP_ROM_PTR(&ubluepy_peripheral_write_char_obj) },
+    { MP_ROM_QSTR(MP_QSTR_readCharacteristic),     MP_ROM_PTR(&ubluepy_peripheral_read_char_obj) },
+#endif // 0
+#endif // MICROPY_PY_UBLUEPY_CENTRAL
+#if MICROPY_PY_UBLUEPY_PERIPHERAL
+    { MP_ROM_QSTR(MP_QSTR_advertise),              MP_ROM_PTR(&ubluepy_peripheral_advertise_obj) },
+    { MP_ROM_QSTR(MP_QSTR_advertise_stop),         MP_ROM_PTR(&ubluepy_peripheral_advertise_stop_obj) },
+    { MP_ROM_QSTR(MP_QSTR_disconnect),             MP_ROM_PTR(&ubluepy_peripheral_disconnect_obj) },
+    { MP_ROM_QSTR(MP_QSTR_addService),             MP_ROM_PTR(&ubluepy_peripheral_add_service_obj) },
+#if 0
+    { MP_ROM_QSTR(MP_QSTR_addCharacteristic),      MP_ROM_PTR(&ubluepy_peripheral_add_char_obj) },
+    { MP_ROM_QSTR(MP_QSTR_addDescriptor),          MP_ROM_PTR(&ubluepy_peripheral_add_desc_obj) },
+    { MP_ROM_QSTR(MP_QSTR_writeCharacteristic),    MP_ROM_PTR(&ubluepy_peripheral_write_char_obj) },
+    { MP_ROM_QSTR(MP_QSTR_readCharacteristic),     MP_ROM_PTR(&ubluepy_peripheral_read_char_obj) },
+#endif
+#endif
+#if MICROPY_PY_UBLUEPY_BROADCASTER
+    { MP_ROM_QSTR(MP_QSTR_advertise),              MP_ROM_PTR(&ubluepy_peripheral_advertise_obj) },
+#endif
+#if MICROPY_PY_UBLUEPY_OBSERVER
+	// Nothing yet.
+#endif
+};
+
+STATIC MP_DEFINE_CONST_DICT(ubluepy_peripheral_locals_dict, ubluepy_peripheral_locals_dict_table);
+
+const mp_obj_type_t ubluepy_peripheral_type = {
+    { &mp_type_type },
+    .name = MP_QSTR_Peripheral,
+    .print = ubluepy_peripheral_print,
+    .make_new = ubluepy_peripheral_make_new,
+    .locals_dict = (mp_obj_dict_t*)&ubluepy_peripheral_locals_dict
+};
+
+#endif // MICROPY_PY_UBLUEPY
diff --git a/ports/nrf/modules/ubluepy/ubluepy_scan_entry.c b/ports/nrf/modules/ubluepy/ubluepy_scan_entry.c
new file mode 100644
index 0000000000..8a936d5928
--- /dev/null
+++ b/ports/nrf/modules/ubluepy/ubluepy_scan_entry.c
@@ -0,0 +1,146 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <string.h>
+#include "py/obj.h"
+#include "py/runtime.h"
+#include "py/objstr.h"
+#include "py/objlist.h"
+#include "py/objarray.h"
+#include "py/objtuple.h"
+#include "py/qstr.h"
+
+#if MICROPY_PY_UBLUEPY_CENTRAL
+
+#include "ble_drv.h"
+
+STATIC void ubluepy_scan_entry_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) {
+    ubluepy_scan_entry_obj_t * self = (ubluepy_scan_entry_obj_t *)o;
+    (void)self;
+    mp_printf(print, "ScanEntry");
+}
+
+/// \method addr()
+/// Return address as text string.
+///
+STATIC mp_obj_t scan_entry_get_addr(mp_obj_t self_in) {
+    ubluepy_scan_entry_obj_t *self = MP_OBJ_TO_PTR(self_in);
+    return self->addr;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(bluepy_scan_entry_get_addr_obj, scan_entry_get_addr);
+
+/// \method addr_type()
+/// Return address type value.
+///
+STATIC mp_obj_t scan_entry_get_addr_type(mp_obj_t self_in) {
+    ubluepy_scan_entry_obj_t *self = MP_OBJ_TO_PTR(self_in);
+    return mp_obj_new_int(self->addr_type);
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(bluepy_scan_entry_get_addr_type_obj, scan_entry_get_addr_type);
+
+/// \method rssi()
+/// Return RSSI value.
+///
+STATIC mp_obj_t scan_entry_get_rssi(mp_obj_t self_in) {
+    ubluepy_scan_entry_obj_t *self = MP_OBJ_TO_PTR(self_in);
+    return mp_obj_new_int(self->rssi);
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(bluepy_scan_entry_get_rssi_obj, scan_entry_get_rssi);
+
+/// \method getScanData()
+/// Return list of the scan data tupples (ad_type, description, value)
+///
+STATIC mp_obj_t scan_entry_get_scan_data(mp_obj_t self_in) {
+    ubluepy_scan_entry_obj_t * self = MP_OBJ_TO_PTR(self_in);
+
+    mp_obj_t retval_list = mp_obj_new_list(0, NULL);
+
+    // TODO: check if self->data is set
+    mp_obj_array_t * data = MP_OBJ_TO_PTR(self->data);
+
+    uint16_t byte_index = 0;
+
+    while (byte_index < data->len) {
+        mp_obj_tuple_t *t = MP_OBJ_TO_PTR(mp_obj_new_tuple(3, NULL));
+
+        uint8_t adv_item_len  = ((uint8_t * )data->items)[byte_index];
+        uint8_t adv_item_type = ((uint8_t * )data->items)[byte_index + 1];
+
+        mp_obj_t description = mp_const_none;
+
+        mp_map_t *constant_map = mp_obj_dict_get_map(ubluepy_constants_ad_types_type.locals_dict);
+        mp_map_elem_t *ad_types_table = MP_OBJ_TO_PTR(constant_map->table);
+
+        uint16_t num_of_elements = constant_map->used;
+
+        for (uint16_t i = 0; i < num_of_elements; i++) {
+            mp_map_elem_t element = (mp_map_elem_t)*ad_types_table;
+            ad_types_table++;
+            uint16_t element_value = mp_obj_get_int(element.value);
+
+            if (adv_item_type == element_value) {
+                qstr key_qstr = MP_OBJ_QSTR_VALUE(element.key);
+                const char * text = qstr_str(key_qstr);
+                size_t len = qstr_len(key_qstr);
+
+                vstr_t vstr;
+                vstr_init(&vstr, len);
+                vstr_printf(&vstr, "%s", text);
+                description = mp_obj_new_str(vstr.buf, vstr.len, false);
+                vstr_clear(&vstr);
+            }
+        }
+
+        t->items[0] = MP_OBJ_NEW_SMALL_INT(adv_item_type);
+        t->items[1] = description;
+        t->items[2] = mp_obj_new_bytearray(adv_item_len - 1,
+                                           &((uint8_t * )data->items)[byte_index + 2]);
+        mp_obj_list_append(retval_list, MP_OBJ_FROM_PTR(t));
+
+        byte_index += adv_item_len + 1;
+    }
+
+    return retval_list;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_scan_entry_get_scan_data_obj, scan_entry_get_scan_data);
+
+STATIC const mp_rom_map_elem_t ubluepy_scan_entry_locals_dict_table[] = {
+    { MP_ROM_QSTR(MP_QSTR_addr),        MP_ROM_PTR(&bluepy_scan_entry_get_addr_obj) },
+    { MP_ROM_QSTR(MP_QSTR_addr_type),   MP_ROM_PTR(&bluepy_scan_entry_get_addr_type_obj) },
+    { MP_ROM_QSTR(MP_QSTR_rssi),        MP_ROM_PTR(&bluepy_scan_entry_get_rssi_obj) },
+    { MP_ROM_QSTR(MP_QSTR_getScanData), MP_ROM_PTR(&ubluepy_scan_entry_get_scan_data_obj) },
+};
+
+STATIC MP_DEFINE_CONST_DICT(ubluepy_scan_entry_locals_dict, ubluepy_scan_entry_locals_dict_table);
+
+const mp_obj_type_t ubluepy_scan_entry_type = {
+    { &mp_type_type },
+    .name = MP_QSTR_ScanEntry,
+    .print = ubluepy_scan_entry_print,
+    .locals_dict = (mp_obj_dict_t*)&ubluepy_scan_entry_locals_dict
+};
+
+#endif // MICROPY_PY_UBLUEPY_CENTRAL
diff --git a/ports/nrf/modules/ubluepy/ubluepy_scanner.c b/ports/nrf/modules/ubluepy/ubluepy_scanner.c
new file mode 100644
index 0000000000..b9c442ac59
--- /dev/null
+++ b/ports/nrf/modules/ubluepy/ubluepy_scanner.c
@@ -0,0 +1,124 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <string.h>
+#include "py/obj.h"
+#include "py/runtime.h"
+#include "py/objstr.h"
+#include "py/objlist.h"
+
+#if MICROPY_PY_UBLUEPY_CENTRAL
+
+#include "ble_drv.h"
+#include "hal_time.h"
+
+STATIC void adv_event_handler(mp_obj_t self_in, uint16_t event_id, ble_drv_adv_data_t * data) {
+    ubluepy_scanner_obj_t *self = MP_OBJ_TO_PTR(self_in);
+
+    ubluepy_scan_entry_obj_t * item = m_new_obj(ubluepy_scan_entry_obj_t);
+    item->base.type = &ubluepy_scan_entry_type;
+
+    vstr_t vstr;
+    vstr_init(&vstr, 17);
+
+    vstr_printf(&vstr, ""HEX2_FMT":"HEX2_FMT":"HEX2_FMT":" \
+                         HEX2_FMT":"HEX2_FMT":"HEX2_FMT"",
+                data->p_peer_addr[5], data->p_peer_addr[4], data->p_peer_addr[3],
+                data->p_peer_addr[2], data->p_peer_addr[1], data->p_peer_addr[0]);
+
+    item->addr = mp_obj_new_str(vstr.buf, vstr.len, false);
+
+    vstr_clear(&vstr);
+
+    item->addr_type = data->addr_type;
+    item->rssi      = data->rssi;
+    item->data      = mp_obj_new_bytearray(data->data_len, data->p_data);
+
+    mp_obj_list_append(self->adv_reports, item);
+}
+
+STATIC void ubluepy_scanner_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) {
+    ubluepy_scanner_obj_t * self = (ubluepy_scanner_obj_t *)o;
+    (void)self;
+    mp_printf(print, "Scanner");
+}
+
+STATIC mp_obj_t ubluepy_scanner_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) {
+    static const mp_arg_t allowed_args[] = {
+
+    };
+
+    // parse args
+    mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
+    mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
+
+    ubluepy_scanner_obj_t * s = m_new_obj(ubluepy_scanner_obj_t);
+    s->base.type = type;
+
+    return MP_OBJ_FROM_PTR(s);
+}
+
+/// \method scan(timeout)
+/// Scan for devices. Timeout is in milliseconds and will set the duration
+/// of the scanning.
+///
+STATIC mp_obj_t scanner_scan(mp_obj_t self_in, mp_obj_t timeout_in) {
+    ubluepy_scanner_obj_t * self = MP_OBJ_TO_PTR(self_in);
+    mp_int_t timeout = mp_obj_get_int(timeout_in);
+
+    self->adv_reports = mp_obj_new_list(0, NULL);
+
+    ble_drv_adv_report_handler_set(MP_OBJ_FROM_PTR(self), adv_event_handler);
+
+    // start
+    ble_drv_scan_start();
+
+    // sleep
+    mp_hal_delay_ms(timeout);
+
+    // stop
+    ble_drv_scan_stop();
+
+    return self->adv_reports;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_2(ubluepy_scanner_scan_obj, scanner_scan);
+
+STATIC const mp_rom_map_elem_t ubluepy_scanner_locals_dict_table[] = {
+    { MP_ROM_QSTR(MP_QSTR_scan), MP_ROM_PTR(&ubluepy_scanner_scan_obj) },
+};
+
+STATIC MP_DEFINE_CONST_DICT(ubluepy_scanner_locals_dict, ubluepy_scanner_locals_dict_table);
+
+
+const mp_obj_type_t ubluepy_scanner_type = {
+    { &mp_type_type },
+    .name = MP_QSTR_Scanner,
+    .print = ubluepy_scanner_print,
+    .make_new = ubluepy_scanner_make_new,
+    .locals_dict = (mp_obj_dict_t*)&ubluepy_scanner_locals_dict
+};
+
+#endif // MICROPY_PY_UBLUEPY_CENTRAL
diff --git a/ports/nrf/modules/ubluepy/ubluepy_service.c b/ports/nrf/modules/ubluepy/ubluepy_service.c
new file mode 100644
index 0000000000..68d905743f
--- /dev/null
+++ b/ports/nrf/modules/ubluepy/ubluepy_service.c
@@ -0,0 +1,186 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "py/obj.h"
+#include "py/runtime.h"
+#include "py/objlist.h"
+
+#if MICROPY_PY_UBLUEPY_PERIPHERAL || MICROPY_PY_UBLUEPY_CENTRAL
+
+#include "modubluepy.h"
+#include "ble_drv.h"
+
+STATIC void ubluepy_service_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) {
+    ubluepy_service_obj_t * self = (ubluepy_service_obj_t *)o;
+
+    mp_printf(print, "Service(handle: 0x" HEX2_FMT ")", self->handle);
+}
+
+STATIC mp_obj_t ubluepy_service_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) {
+
+    enum { ARG_NEW_UUID, ARG_NEW_TYPE };
+
+    static const mp_arg_t allowed_args[] = {
+        { ARG_NEW_UUID, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
+        { ARG_NEW_TYPE, MP_ARG_INT, {.u_int = UBLUEPY_SERVICE_PRIMARY} },
+    };
+
+    // parse args
+    mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
+    mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
+
+    ubluepy_service_obj_t *s = m_new_obj(ubluepy_service_obj_t);
+    s->base.type = type;
+
+    mp_obj_t uuid_obj = args[ARG_NEW_UUID].u_obj;
+
+    if (uuid_obj == MP_OBJ_NULL) {
+        return MP_OBJ_FROM_PTR(s);
+    }
+
+    if (MP_OBJ_IS_TYPE(uuid_obj, &ubluepy_uuid_type)) {
+        s->p_uuid = MP_OBJ_TO_PTR(uuid_obj);
+
+        uint8_t type = args[ARG_NEW_TYPE].u_int;
+        if (type > 0 &&  type <= UBLUEPY_SERVICE_PRIMARY) {
+            s->type = type;
+        } else {
+            nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
+                      "Invalid Service type"));
+        }
+
+        (void)ble_drv_service_add(s);
+
+    } else {
+        nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
+                  "Invalid UUID parameter"));
+    }
+
+    // clear reference to peripheral
+    s->p_periph = NULL;
+    s->char_list = mp_obj_new_list(0, NULL);
+
+    return MP_OBJ_FROM_PTR(s);
+}
+
+/// \method addCharacteristic(Characteristic)
+/// Add Characteristic to the Service.
+///
+STATIC mp_obj_t service_add_characteristic(mp_obj_t self_in, mp_obj_t characteristic) {
+    ubluepy_service_obj_t        * self   = MP_OBJ_TO_PTR(self_in);
+    ubluepy_characteristic_obj_t * p_char = MP_OBJ_TO_PTR(characteristic);
+
+    p_char->service_handle = self->handle;
+
+    bool retval = ble_drv_characteristic_add(p_char);
+
+    if (retval) {
+        p_char->p_service = self;
+    }
+
+    mp_obj_list_append(self->char_list, characteristic);
+
+    // return mp_obj_new_bool(retval);
+    return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_2(ubluepy_service_add_char_obj, service_add_characteristic);
+
+/// \method getCharacteristics()
+/// Return list with all characteristics registered in the Service.
+///
+STATIC mp_obj_t service_get_chars(mp_obj_t self_in) {
+    ubluepy_service_obj_t * self = MP_OBJ_TO_PTR(self_in);
+
+    return self->char_list;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_service_get_chars_obj, service_get_chars);
+
+/// \method getCharacteristic(UUID)
+/// Return Characteristic with the given UUID.
+///
+STATIC mp_obj_t service_get_characteristic(mp_obj_t self_in, mp_obj_t uuid) {
+    ubluepy_service_obj_t * self   = MP_OBJ_TO_PTR(self_in);
+    ubluepy_uuid_obj_t    * p_uuid = MP_OBJ_TO_PTR(uuid);
+
+    // validate that there is an UUID object passed in as parameter
+    if (!(MP_OBJ_IS_TYPE(uuid, &ubluepy_uuid_type))) {
+        nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
+                  "Invalid UUID parameter"));
+    }
+
+    mp_obj_t * chars     = NULL;
+    mp_uint_t  num_chars = 0;
+    mp_obj_get_array(self->char_list, &num_chars, &chars);
+
+    for (uint8_t i = 0; i < num_chars; i++) {
+        ubluepy_characteristic_obj_t * p_char = (ubluepy_characteristic_obj_t *)chars[i];
+
+        bool type_match = p_char->p_uuid->type == p_uuid->type;
+        bool uuid_match = ((uint16_t)(*(uint16_t *)&p_char->p_uuid->value[0]) ==
+                           (uint16_t)(*(uint16_t *)&p_uuid->value[0]));
+
+        if (type_match && uuid_match) {
+            return MP_OBJ_FROM_PTR(p_char);
+        }
+    }
+
+    return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_2(ubluepy_service_get_char_obj, service_get_characteristic);
+
+/// \method uuid()
+/// Get UUID instance of the Service.
+///
+STATIC mp_obj_t service_uuid(mp_obj_t self_in) {
+    ubluepy_service_obj_t * self = MP_OBJ_TO_PTR(self_in);
+    return MP_OBJ_FROM_PTR(self->p_uuid);
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_service_get_uuid_obj, service_uuid);
+
+STATIC const mp_rom_map_elem_t ubluepy_service_locals_dict_table[] = {
+    { MP_ROM_QSTR(MP_QSTR_getCharacteristic),  MP_ROM_PTR(&ubluepy_service_get_char_obj) },
+    { MP_ROM_QSTR(MP_QSTR_addCharacteristic),  MP_ROM_PTR(&ubluepy_service_add_char_obj) },
+    { MP_ROM_QSTR(MP_QSTR_getCharacteristics), MP_ROM_PTR(&ubluepy_service_get_chars_obj) },
+#if 0
+	// Properties
+    { MP_ROM_QSTR(MP_QSTR_peripheral), MP_ROM_PTR(&ubluepy_service_get_peripheral_obj) },
+#endif
+    { MP_ROM_QSTR(MP_QSTR_uuid),       MP_ROM_PTR(&ubluepy_service_get_uuid_obj) },
+    { MP_ROM_QSTR(MP_QSTR_PRIMARY),    MP_ROM_INT(UBLUEPY_SERVICE_PRIMARY) },
+    { MP_ROM_QSTR(MP_QSTR_SECONDARY),  MP_ROM_INT(UBLUEPY_SERVICE_SECONDARY) },
+};
+
+STATIC MP_DEFINE_CONST_DICT(ubluepy_service_locals_dict, ubluepy_service_locals_dict_table);
+
+const mp_obj_type_t ubluepy_service_type = {
+    { &mp_type_type },
+    .name = MP_QSTR_Service,
+    .print = ubluepy_service_print,
+    .make_new = ubluepy_service_make_new,
+    .locals_dict = (mp_obj_dict_t*)&ubluepy_service_locals_dict
+};
+
+#endif // MICROPY_PY_UBLUEPY_PERIPHERAL || MICROPY_PY_UBLUEPY_CENTRAL
diff --git a/ports/nrf/modules/ubluepy/ubluepy_uuid.c b/ports/nrf/modules/ubluepy/ubluepy_uuid.c
new file mode 100644
index 0000000000..380d2e4046
--- /dev/null
+++ b/ports/nrf/modules/ubluepy/ubluepy_uuid.c
@@ -0,0 +1,173 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "py/obj.h"
+#include "py/runtime.h"
+#include "py/objstr.h"
+#include "py/misc.h"
+
+#if MICROPY_PY_UBLUEPY
+
+#include "modubluepy.h"
+#include "ble_drv.h"
+
+STATIC void ubluepy_uuid_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) {
+    ubluepy_uuid_obj_t * self = (ubluepy_uuid_obj_t *)o;
+    if (self->type == UBLUEPY_UUID_16_BIT) {
+        mp_printf(print, "UUID(uuid: 0x" HEX2_FMT HEX2_FMT ")",
+                  self->value[1], self->value[0]);
+    } else {
+        mp_printf(print, "UUID(uuid: 0x" HEX2_FMT HEX2_FMT ", VS idx: " HEX2_FMT ")",
+                  self->value[1], self->value[0], self->uuid_vs_idx);
+    }
+}
+
+STATIC mp_obj_t ubluepy_uuid_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) {
+
+    enum { ARG_NEW_UUID };
+
+    static const mp_arg_t allowed_args[] = {
+        { ARG_NEW_UUID, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
+    };
+
+    // parse args
+    mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
+    mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
+
+    ubluepy_uuid_obj_t *s = m_new_obj(ubluepy_uuid_obj_t);
+    s->base.type = type;
+
+    mp_obj_t uuid_obj = args[ARG_NEW_UUID].u_obj;
+
+    if (uuid_obj == MP_OBJ_NULL) {
+        return MP_OBJ_FROM_PTR(s);
+    }
+
+    if (MP_OBJ_IS_INT(uuid_obj)) {
+        s->type = UBLUEPY_UUID_16_BIT;
+        s->value[1] = (((uint16_t)mp_obj_get_int(uuid_obj)) >> 8) & 0xFF;
+        s->value[0] = ((uint8_t)mp_obj_get_int(uuid_obj)) & 0xFF;
+    } else if (MP_OBJ_IS_STR(uuid_obj)) {
+        GET_STR_DATA_LEN(uuid_obj, str_data, str_len);
+        if (str_len == 6) { // Assume hex digit prefixed with 0x
+            s->type = UBLUEPY_UUID_16_BIT;
+            s->value[0]  = unichar_xdigit_value(str_data[5]);
+            s->value[0] += unichar_xdigit_value(str_data[4]) << 4;
+            s->value[1]  = unichar_xdigit_value(str_data[3]);
+            s->value[1] += unichar_xdigit_value(str_data[2]) << 4;
+        } else if (str_len == 36) {
+            s->type = UBLUEPY_UUID_128_BIT;
+            uint8_t buffer[16];
+            buffer[0]  = unichar_xdigit_value(str_data[35]);
+            buffer[0] += unichar_xdigit_value(str_data[34]) << 4;
+            buffer[1]  = unichar_xdigit_value(str_data[33]);
+            buffer[1] += unichar_xdigit_value(str_data[32]) << 4;
+            buffer[2]  = unichar_xdigit_value(str_data[31]);
+            buffer[2] += unichar_xdigit_value(str_data[30]) << 4;
+            buffer[3]  = unichar_xdigit_value(str_data[29]);
+            buffer[3] += unichar_xdigit_value(str_data[28]) << 4;
+            buffer[4]  = unichar_xdigit_value(str_data[27]);
+            buffer[4] += unichar_xdigit_value(str_data[26]) << 4;
+            buffer[5]  = unichar_xdigit_value(str_data[25]);
+            buffer[5] += unichar_xdigit_value(str_data[24]) << 4;
+            // 23 '-'
+            buffer[6]  = unichar_xdigit_value(str_data[22]);
+            buffer[6] += unichar_xdigit_value(str_data[21]) << 4;
+            buffer[7]  = unichar_xdigit_value(str_data[20]);
+            buffer[7] += unichar_xdigit_value(str_data[19]) << 4;
+            // 18 '-'
+            buffer[8]  = unichar_xdigit_value(str_data[17]);
+            buffer[8] += unichar_xdigit_value(str_data[16]) << 4;
+            buffer[9]  = unichar_xdigit_value(str_data[15]);
+            buffer[9] += unichar_xdigit_value(str_data[14]) << 4;
+            // 13 '-'
+            buffer[10]  = unichar_xdigit_value(str_data[12]);
+            buffer[10] += unichar_xdigit_value(str_data[11]) << 4;
+            buffer[11]  = unichar_xdigit_value(str_data[10]);
+            buffer[11] += unichar_xdigit_value(str_data[9]) << 4;
+            // 8 '-'
+            // 16-bit field
+            s->value[0]  = unichar_xdigit_value(str_data[7]);
+            s->value[0] += unichar_xdigit_value(str_data[6]) << 4;
+            s->value[1]  = unichar_xdigit_value(str_data[5]);
+            s->value[1] += unichar_xdigit_value(str_data[4]) << 4;
+
+            buffer[14]  = unichar_xdigit_value(str_data[3]);
+            buffer[14] += unichar_xdigit_value(str_data[2]) << 4;
+            buffer[15]  = unichar_xdigit_value(str_data[1]);
+            buffer[15] += unichar_xdigit_value(str_data[0]) << 4;
+
+            ble_drv_uuid_add_vs(buffer, &s->uuid_vs_idx);
+        } else {
+            nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
+                      "Invalid UUID string length"));
+        }
+    } else if (MP_OBJ_IS_TYPE(uuid_obj, &ubluepy_uuid_type)) {
+        // deep copy instance
+        ubluepy_uuid_obj_t * p_old = MP_OBJ_TO_PTR(uuid_obj);
+        s->type     = p_old->type;
+        s->value[0] = p_old->value[0];
+        s->value[1] = p_old->value[1];
+    } else {
+        nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
+                  "Invalid UUID parameter"));
+    }
+
+    return MP_OBJ_FROM_PTR(s);
+}
+
+/// \method binVal()
+/// Get binary value of the 16 or 128 bit UUID. Returned as bytearray type.
+///
+STATIC mp_obj_t uuid_bin_val(mp_obj_t self_in) {
+    ubluepy_uuid_obj_t * self = MP_OBJ_TO_PTR(self_in);
+
+    // TODO: Extend the uint16 byte value to 16 byte if 128-bit,
+    //       also encapsulate it in a bytearray. For now, return
+    //       the uint16_t field of the UUID.
+    return MP_OBJ_NEW_SMALL_INT(self->value[0] | self->value[1] << 8);
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(ubluepy_uuid_bin_val_obj, uuid_bin_val);
+
+STATIC const mp_rom_map_elem_t ubluepy_uuid_locals_dict_table[] = {
+#if 0
+    { MP_ROM_QSTR(MP_QSTR_getCommonName), MP_ROM_PTR(&ubluepy_uuid_get_common_name_obj) },
+#endif
+    // Properties
+    { MP_ROM_QSTR(MP_QSTR_binVal), MP_ROM_PTR(&ubluepy_uuid_bin_val_obj) },
+};
+
+STATIC MP_DEFINE_CONST_DICT(ubluepy_uuid_locals_dict, ubluepy_uuid_locals_dict_table);
+
+const mp_obj_type_t ubluepy_uuid_type = {
+    { &mp_type_type },
+    .name = MP_QSTR_UUID,
+    .print = ubluepy_uuid_print,
+    .make_new = ubluepy_uuid_make_new,
+    .locals_dict = (mp_obj_dict_t*)&ubluepy_uuid_locals_dict
+};
+
+#endif // MICROPY_PY_UBLUEPY
diff --git a/ports/nrf/modules/uos/moduos.c b/ports/nrf/modules/uos/moduos.c
new file mode 100644
index 0000000000..21ea2cde67
--- /dev/null
+++ b/ports/nrf/modules/uos/moduos.c
@@ -0,0 +1,174 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <stdint.h>
+#include <string.h>
+
+#include "py/mpstate.h"
+#include "py/runtime.h"
+#include "py/objtuple.h"
+#include "py/objstr.h"
+#include "lib/oofatfs/ff.h"
+#include "lib/oofatfs/diskio.h"
+#include "extmod/vfs.h"
+#include "extmod/vfs_fat.h"
+#include "genhdr/mpversion.h"
+//#include "timeutils.h"
+//#include "rng.h"
+#include "uart.h"
+//#include "portmodules.h"
+
+/// \module os - basic "operating system" services
+///
+/// The `os` module contains functions for filesystem access and `urandom`.
+///
+/// The filesystem has `/` as the root directory, and the available physical
+/// drives are accessible from here.  They are currently:
+///
+///     /flash      -- the internal flash filesystem
+///     /sd         -- the SD card (if it exists)
+///
+/// On boot up, the current directory is `/flash` if no SD card is inserted,
+/// otherwise it is `/sd`.
+
+STATIC const qstr os_uname_info_fields[] = {
+    MP_QSTR_sysname, MP_QSTR_nodename,
+    MP_QSTR_release, MP_QSTR_version, MP_QSTR_machine
+};
+STATIC const MP_DEFINE_STR_OBJ(os_uname_info_sysname_obj, "pyboard");
+STATIC const MP_DEFINE_STR_OBJ(os_uname_info_nodename_obj, "pyboard");
+STATIC const MP_DEFINE_STR_OBJ(os_uname_info_release_obj, MICROPY_VERSION_STRING);
+STATIC const MP_DEFINE_STR_OBJ(os_uname_info_version_obj, MICROPY_GIT_TAG " on " MICROPY_BUILD_DATE);
+STATIC const MP_DEFINE_STR_OBJ(os_uname_info_machine_obj, MICROPY_HW_BOARD_NAME " with " MICROPY_HW_MCU_NAME);
+STATIC MP_DEFINE_ATTRTUPLE(
+    os_uname_info_obj,
+    os_uname_info_fields,
+    5,
+    (mp_obj_t)&os_uname_info_sysname_obj,
+    (mp_obj_t)&os_uname_info_nodename_obj,
+    (mp_obj_t)&os_uname_info_release_obj,
+    (mp_obj_t)&os_uname_info_version_obj,
+    (mp_obj_t)&os_uname_info_machine_obj
+);
+
+STATIC mp_obj_t os_uname(void) {
+    return (mp_obj_t)&os_uname_info_obj;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_0(os_uname_obj, os_uname);
+
+#if MICROPY_VFS
+/// \function sync()
+/// Sync all filesystems.
+STATIC mp_obj_t os_sync(void) {
+    for (mp_vfs_mount_t *vfs = MP_STATE_VM(vfs_mount_table); vfs != NULL; vfs = vfs->next) {
+        // this assumes that vfs->obj is fs_user_mount_t with block device functions
+        disk_ioctl(MP_OBJ_TO_PTR(vfs->obj), CTRL_SYNC, NULL);
+    }
+    return mp_const_none;
+}
+MP_DEFINE_CONST_FUN_OBJ_0(mod_os_sync_obj, os_sync);
+#endif
+
+#if MICROPY_HW_ENABLE_RNG
+/// \function urandom(n)
+/// Return a bytes object with n random bytes, generated by the hardware
+/// random number generator.
+STATIC mp_obj_t os_urandom(mp_obj_t num) {
+    mp_int_t n = mp_obj_get_int(num);
+    vstr_t vstr;
+    vstr_init_len(&vstr, n);
+    for (int i = 0; i < n; i++) {
+        vstr.buf[i] = rng_get();
+    }
+    return mp_obj_new_str_from_vstr(&mp_type_bytes, &vstr);
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(os_urandom_obj, os_urandom);
+#endif
+
+// Get or set the UART object that the REPL is repeated on.
+// TODO should accept any object with read/write methods.
+STATIC mp_obj_t os_dupterm(mp_uint_t n_args, const mp_obj_t *args) {
+    if (n_args == 0) {
+        if (MP_STATE_PORT(pyb_stdio_uart) == NULL) {
+            return mp_const_none;
+        } else {
+            return MP_STATE_PORT(pyb_stdio_uart);
+        }
+    } else {
+        if (args[0] == mp_const_none) {
+            MP_STATE_PORT(pyb_stdio_uart) = NULL;
+        } else if (mp_obj_get_type(args[0]) == &machine_hard_uart_type) {
+            MP_STATE_PORT(pyb_stdio_uart) = args[0];
+        } else {
+            mp_raise_ValueError("need a UART object");
+        }
+        return mp_const_none;
+    }
+}
+MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(mod_os_dupterm_obj, 0, 1, os_dupterm);
+
+STATIC const mp_rom_map_elem_t os_module_globals_table[] = {
+    { MP_ROM_QSTR(MP_QSTR___name__), MP_ROM_QSTR(MP_QSTR_uos) },
+
+    { MP_ROM_QSTR(MP_QSTR_uname), MP_ROM_PTR(&os_uname_obj) },
+
+#if MICROPY_VFS
+    { MP_ROM_QSTR(MP_QSTR_chdir), MP_ROM_PTR(&mp_vfs_chdir_obj) },
+    { MP_ROM_QSTR(MP_QSTR_getcwd), MP_ROM_PTR(&mp_vfs_getcwd_obj) },
+    { MP_ROM_QSTR(MP_QSTR_listdir), MP_ROM_PTR(&mp_vfs_listdir_obj) },
+    { MP_ROM_QSTR(MP_QSTR_mkdir), MP_ROM_PTR(&mp_vfs_mkdir_obj) },
+    { MP_ROM_QSTR(MP_QSTR_remove), MP_ROM_PTR(&mp_vfs_remove_obj) },
+    { MP_ROM_QSTR(MP_QSTR_rename), MP_ROM_PTR(&mp_vfs_rename_obj) },
+    { MP_ROM_QSTR(MP_QSTR_rmdir), MP_ROM_PTR(&mp_vfs_rmdir_obj) },
+    { MP_ROM_QSTR(MP_QSTR_stat), MP_ROM_PTR(&mp_vfs_stat_obj) },
+    { MP_ROM_QSTR(MP_QSTR_statvfs), MP_ROM_PTR(&mp_vfs_statvfs_obj) },
+    { MP_ROM_QSTR(MP_QSTR_unlink), MP_ROM_PTR(&mp_vfs_remove_obj) }, // unlink aliases to remove
+
+    { MP_ROM_QSTR(MP_QSTR_sync), MP_ROM_PTR(&mod_os_sync_obj) },
+#endif
+
+    /// \constant sep - separation character used in paths
+    { MP_ROM_QSTR(MP_QSTR_sep), MP_ROM_QSTR(MP_QSTR__slash_) },
+
+#if MICROPY_HW_ENABLE_RNG
+    { MP_ROM_QSTR(MP_QSTR_urandom), MP_ROM_PTR(&os_urandom_obj) },
+#endif
+
+    // these are MicroPython extensions
+    { MP_ROM_QSTR(MP_QSTR_dupterm), MP_ROM_PTR(&mod_os_dupterm_obj) },
+#if MICROPY_VFS
+    { MP_ROM_QSTR(MP_QSTR_mount), MP_ROM_PTR(&mp_vfs_mount_obj) },
+    { MP_ROM_QSTR(MP_QSTR_umount), MP_ROM_PTR(&mp_vfs_umount_obj) },
+    { MP_ROM_QSTR(MP_QSTR_VfsFat), MP_ROM_PTR(&mp_fat_vfs_type) },
+#endif
+};
+
+STATIC MP_DEFINE_CONST_DICT(os_module_globals, os_module_globals_table);
+
+const mp_obj_module_t mp_module_uos = {
+    .base = { &mp_type_module },
+    .globals = (mp_obj_dict_t*)&os_module_globals,
+};
diff --git a/ports/nrf/modules/utime/modutime.c b/ports/nrf/modules/utime/modutime.c
new file mode 100644
index 0000000000..8e9c05c1ee
--- /dev/null
+++ b/ports/nrf/modules/utime/modutime.c
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include NRF5_HAL_H
+
+#include "py/nlr.h"
+#include "py/smallint.h"
+#include "py/obj.h"
+#include "extmod/utime_mphal.h"
+
+/// \module time - time related functions
+///
+/// The `time` module provides functions for getting the current time and date,
+/// and for sleeping.
+
+STATIC const mp_rom_map_elem_t time_module_globals_table[] = {
+    { MP_ROM_QSTR(MP_QSTR___name__), MP_ROM_QSTR(MP_QSTR_utime) },
+
+    { MP_ROM_QSTR(MP_QSTR_sleep_ms), MP_ROM_PTR(&mp_utime_sleep_ms_obj) },
+    { MP_ROM_QSTR(MP_QSTR_sleep_us), MP_ROM_PTR(&mp_utime_sleep_us_obj) },
+};
+
+STATIC MP_DEFINE_CONST_DICT(time_module_globals, time_module_globals_table);
+
+const mp_obj_module_t mp_module_utime = {
+    .base = { &mp_type_module },
+    .globals = (mp_obj_dict_t*)&time_module_globals,
+};
diff --git a/ports/nrf/mpconfigport.h b/ports/nrf/mpconfigport.h
new file mode 100644
index 0000000000..46ad669119
--- /dev/null
+++ b/ports/nrf/mpconfigport.h
@@ -0,0 +1,312 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2015 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef NRF5_MPCONFIGPORT_H__
+#define NRF5_MPCONFIGPORT_H__
+
+#include <mpconfigboard.h>
+
+// options to control how MicroPython is built
+#ifndef MICROPY_VFS
+#define MICROPY_VFS                 (1)
+#endif
+#define MICROPY_VFS_FAT             (MICROPY_VFS)
+#define MICROPY_ALLOC_PATH_MAX      (512)
+#define MICROPY_PERSISTENT_CODE_LOAD (0)
+#define MICROPY_EMIT_THUMB          (0)
+#define MICROPY_EMIT_INLINE_THUMB   (0)
+#define MICROPY_COMP_MODULE_CONST   (0)
+#define MICROPY_COMP_TRIPLE_TUPLE_ASSIGN (0)
+#define MICROPY_READER_VFS          (MICROPY_VFS)
+#define MICROPY_ENABLE_GC           (1)
+#define MICROPY_ENABLE_FINALISER    (1)
+#define MICROPY_STACK_CHECK         (0)
+#define MICROPY_HELPER_REPL         (1)
+#define MICROPY_REPL_EMACS_KEYS     (0)
+#define MICROPY_REPL_AUTO_INDENT    (1)
+#define MICROPY_ENABLE_SOURCE_LINE  (0)
+#define MICROPY_LONGINT_IMPL        (MICROPY_LONGINT_IMPL_MPZ)
+#if NRF51
+#define MICROPY_FLOAT_IMPL          (MICROPY_FLOAT_IMPL_NONE)
+#else
+#define MICROPY_FLOAT_IMPL          (MICROPY_FLOAT_IMPL_FLOAT)
+#endif
+
+#define MICROPY_OPT_COMPUTED_GOTO   (0)
+#define MICROPY_OPT_CACHE_MAP_LOOKUP_IN_BYTECODE (0)
+#define MICROPY_OPT_MPZ_BITWISE     (0)
+
+// fatfs configuration used in ffconf.h
+#define MICROPY_FATFS_ENABLE_LFN       (1)
+#define MICROPY_FATFS_LFN_CODE_PAGE    (437) /* 1=SFN/ANSI 437=LFN/U.S.(OEM) */
+#define MICROPY_FATFS_USE_LABEL        (1)
+#define MICROPY_FATFS_RPATH            (2)
+#define MICROPY_FATFS_MULTI_PARTITION  (1)
+
+// TODO these should be generic, not bound to fatfs
+#define mp_type_fileio fatfs_type_fileio
+#define mp_type_textio fatfs_type_textio
+
+// use vfs's functions for import stat and builtin open
+#if MICROPY_VFS
+#define mp_import_stat mp_vfs_import_stat
+#define mp_builtin_open mp_vfs_open
+#define mp_builtin_open_obj mp_vfs_open_obj
+#endif
+
+#define MICROPY_STREAMS_NON_BLOCK   (1)
+#define MICROPY_MODULE_WEAK_LINKS   (1)
+#define MICROPY_CAN_OVERRIDE_BUILTINS (1)
+#define MICROPY_USE_INTERNAL_ERRNO  (1)
+#define MICROPY_PY_FUNCTION_ATTRS   (1)
+#define MICROPY_PY_BUILTINS_STR_UNICODE (0)
+#define MICROPY_PY_BUILTINS_STR_CENTER (0)
+#define MICROPY_PY_BUILTINS_STR_PARTITION (0)
+#define MICROPY_PY_BUILTINS_STR_SPLITLINES (0)
+#define MICROPY_PY_BUILTINS_MEMORYVIEW (1)
+#define MICROPY_PY_BUILTINS_FROZENSET (1)
+#define MICROPY_PY_BUILTINS_EXECFILE (0)
+#define MICROPY_PY_BUILTINS_COMPILE (1)
+#define MICROPY_PY_BUILTINS_HELP    (1)
+#define MICROPY_PY_BUILTINS_HELP_TEXT nrf5_help_text
+#define MICROPY_PY_BUILTINS_HELP_MODULES (1)
+#define MICROPY_MODULE_BUILTIN_INIT (1)
+#define MICROPY_PY_ALL_SPECIAL_METHODS (0)
+#define MICROPY_PY_MICROPYTHON_MEM_INFO (1)
+#define MICROPY_PY_ARRAY_SLICE_ASSIGN (0)
+#define MICROPY_PY_BUILTINS_SLICE_ATTRS (0)
+#define MICROPY_PY_SYS_EXIT         (1)
+#define MICROPY_PY_SYS_MAXSIZE      (1)
+#define MICROPY_PY_SYS_STDFILES     (0)
+#define MICROPY_PY_SYS_STDIO_BUFFER (0)
+#define MICROPY_PY_COLLECTIONS_ORDEREDDICT (0)
+#define MICROPY_PY_MATH_SPECIAL_FUNCTIONS (0)
+#define MICROPY_PY_CMATH            (0)
+#define MICROPY_PY_IO               (0)
+#define MICROPY_PY_IO_FILEIO        (0)
+#define MICROPY_PY_UERRNO           (0)
+#define MICROPY_PY_UBINASCII        (0)
+#define MICROPY_PY_URANDOM          (0)
+#define MICROPY_PY_URANDOM_EXTRA_FUNCS (0)
+#define MICROPY_PY_UCTYPES          (0)
+#define MICROPY_PY_UZLIB            (0)
+#define MICROPY_PY_UJSON            (0)
+#define MICROPY_PY_URE              (0)
+#define MICROPY_PY_UHEAPQ           (0)
+#define MICROPY_PY_UHASHLIB         (0)
+#define MICROPY_PY_UTIME_MP_HAL     (1)
+#define MICROPY_PY_MACHINE          (1)
+#define MICROPY_PY_MACHINE_PULSE    (0)
+#define MICROPY_PY_MACHINE_I2C_MAKE_NEW machine_hard_i2c_make_new
+#define MICROPY_PY_MACHINE_SPI      (0)
+#define MICROPY_PY_MACHINE_SPI_MIN_DELAY (0)
+#define MICROPY_PY_FRAMEBUF         (0)
+
+#ifndef MICROPY_HW_LED_COUNT
+#define MICROPY_HW_LED_COUNT        (0)
+#endif
+
+#ifndef MICROPY_HW_LED_PULLUP
+#define MICROPY_HW_LED_PULLUP       (0)
+#endif
+
+#ifndef MICROPY_PY_MUSIC
+#define MICROPY_PY_MUSIC            (0)
+#endif
+
+#ifndef MICROPY_PY_MACHINE_ADC
+#define MICROPY_PY_MACHINE_ADC      (0)
+#endif
+
+#ifndef MICROPY_PY_MACHINE_I2C
+#define MICROPY_PY_MACHINE_I2C      (0)
+#endif
+
+#ifndef MICROPY_PY_MACHINE_HW_SPI
+#define MICROPY_PY_MACHINE_HW_SPI   (1)
+#endif
+
+#ifndef MICROPY_PY_MACHINE_HW_PWM
+#define MICROPY_PY_MACHINE_HW_PWM   (0)
+#endif
+
+#ifndef MICROPY_PY_MACHINE_SOFT_PWM
+#define MICROPY_PY_MACHINE_SOFT_PWM (0)
+#endif
+
+#ifndef MICROPY_PY_MACHINE_TIMER
+#define MICROPY_PY_MACHINE_TIMER    (0)
+#endif
+
+#ifndef MICROPY_PY_MACHINE_RTC
+#define MICROPY_PY_MACHINE_RTC      (0)
+#endif
+
+#ifndef MICROPY_PY_HW_RNG
+#define MICROPY_PY_HW_RNG           (1)
+#endif
+
+
+#define MICROPY_ENABLE_EMERGENCY_EXCEPTION_BUF   (1)
+#define MICROPY_EMERGENCY_EXCEPTION_BUF_SIZE  (0)
+
+// if sdk is in use, import configuration
+#if BLUETOOTH_SD
+#include "bluetooth_conf.h"
+#endif
+
+#ifndef MICROPY_PY_UBLUEPY
+#define MICROPY_PY_UBLUEPY                       (0)
+#endif
+
+#ifndef MICROPY_PY_BLE_NUS
+#define MICROPY_PY_BLE_NUS                       (0)
+#endif
+
+// type definitions for the specific machine
+
+#define BYTES_PER_WORD (4)
+
+#define MICROPY_MAKE_POINTER_CALLABLE(p) ((void*)((mp_uint_t)(p) | 1))
+
+#define MP_SSIZE_MAX (0x7fffffff)
+
+#define UINT_FMT "%u"
+#define INT_FMT "%d"
+#define HEX2_FMT "%02x"
+
+typedef int mp_int_t; // must be pointer size
+typedef unsigned int mp_uint_t; // must be pointer size
+typedef long mp_off_t;
+
+// extra built in modules to add to the list of known ones
+extern const struct _mp_obj_module_t pyb_module;
+extern const struct _mp_obj_module_t machine_module;
+extern const struct _mp_obj_module_t mp_module_utime;
+extern const struct _mp_obj_module_t mp_module_uos;
+extern const struct _mp_obj_module_t mp_module_ubluepy;
+extern const struct _mp_obj_module_t music_module;
+extern const struct _mp_obj_module_t random_module;
+
+#if MICROPY_PY_UBLUEPY
+#define UBLUEPY_MODULE                      { MP_ROM_QSTR(MP_QSTR_ubluepy), MP_ROM_PTR(&mp_module_ubluepy) },
+#else
+#define UBLUEPY_MODULE
+#endif
+
+#if MICROPY_PY_MUSIC
+#define MUSIC_MODULE                        { MP_ROM_QSTR(MP_QSTR_music), MP_ROM_PTR(&music_module) },
+#else
+#define MUSIC_MODULE
+#endif
+
+#if MICROPY_PY_HW_RNG
+#define RANDOM_MODULE                        { MP_ROM_QSTR(MP_QSTR_random), MP_ROM_PTR(&random_module) },
+#else
+#define RANDOM_MODULE
+#endif
+
+#if BLUETOOTH_SD
+
+#if MICROPY_PY_BLE
+extern const struct _mp_obj_module_t ble_module;
+#define BLE_MODULE                        { MP_ROM_QSTR(MP_QSTR_ble), MP_ROM_PTR(&ble_module) },
+#else
+#define BLE_MODULE
+#endif
+
+#define MICROPY_PORT_BUILTIN_MODULES \
+    { MP_ROM_QSTR(MP_QSTR_pyb), MP_ROM_PTR(&pyb_module) }, \
+    { MP_ROM_QSTR(MP_QSTR_machine), MP_ROM_PTR(&machine_module) }, \
+    { MP_ROM_QSTR(MP_QSTR_utime), MP_ROM_PTR(&mp_module_utime) }, \
+    { MP_ROM_QSTR(MP_QSTR_time), MP_ROM_PTR(&mp_module_utime) }, \
+    { MP_ROM_QSTR(MP_QSTR_uos), MP_ROM_PTR(&mp_module_uos) }, \
+    BLE_MODULE \
+    MUSIC_MODULE \
+    UBLUEPY_MODULE \
+    RANDOM_MODULE \
+
+
+#else
+extern const struct _mp_obj_module_t ble_module;
+#define MICROPY_PORT_BUILTIN_MODULES \
+    { MP_ROM_QSTR(MP_QSTR_pyb), MP_ROM_PTR(&pyb_module) }, \
+    { MP_ROM_QSTR(MP_QSTR_machine), MP_ROM_PTR(&machine_module) }, \
+    { MP_ROM_QSTR(MP_QSTR_utime), MP_ROM_PTR(&mp_module_utime) }, \
+    { MP_ROM_QSTR(MP_QSTR_uos), MP_ROM_PTR(&mp_module_uos) }, \
+    MUSIC_MODULE \
+    RANDOM_MODULE \
+
+
+#endif // BLUETOOTH_SD
+
+#define MICROPY_PORT_BUILTIN_MODULE_WEAK_LINKS \
+    { MP_ROM_QSTR(MP_QSTR_os), MP_ROM_PTR(&mp_module_uos) }, \
+    { MP_ROM_QSTR(MP_QSTR_time), MP_ROM_PTR(&mp_module_utime) }, \
+
+// extra built in names to add to the global namespace
+#define MICROPY_PORT_BUILTINS \
+    { MP_ROM_QSTR(MP_QSTR_help), MP_ROM_PTR(&mp_builtin_help_obj) }, \
+    { MP_ROM_QSTR(MP_QSTR_open), MP_ROM_PTR(&mp_builtin_open_obj) }, \
+
+// extra constants
+#define MICROPY_PORT_CONSTANTS \
+    { MP_ROM_QSTR(MP_QSTR_pyb), MP_ROM_PTR(&pyb_module) }, \
+    { MP_ROM_QSTR(MP_QSTR_machine), MP_ROM_PTR(&machine_module) }, \
+    BLE_MODULE \
+
+#define MP_STATE_PORT MP_STATE_VM
+
+#define MICROPY_PORT_ROOT_POINTERS \
+    const char *readline_hist[8]; \
+    mp_obj_t pyb_config_main; \
+    mp_obj_t pin_class_mapper; \
+    mp_obj_t pin_class_map_dict; \
+    /* Used to do callbacks to Python code on interrupt */ \
+    struct _pyb_timer_obj_t *pyb_timer_obj_all[14]; \
+    \
+    /* stdio is repeated on this UART object if it's not null */ \
+    struct _machine_hard_uart_obj_t *pyb_stdio_uart; \
+    \
+    /* pointers to all UART objects (if they have been created) */ \
+    struct _machine_hard_uart_obj_t *pyb_uart_obj_all[1]; \
+    \
+    /* list of registered NICs */ \
+    mp_obj_list_t mod_network_nic_list; \
+    \
+    /* microbit modules */ \
+    struct _music_data_t *music_data; \
+    const struct _pwm_events *pwm_active_events; \
+    const struct _pwm_events *pwm_pending_events; \
+
+#define MP_PLAT_PRINT_STRN(str, len) mp_hal_stdout_tx_strn_cooked(str, len)
+
+// We need to provide a declaration/definition of alloca()
+#include <alloca.h>
+
+#define MICROPY_PIN_DEFS_PORT_H "pin_defs_nrf5.h"
+
+#endif
diff --git a/ports/nrf/mphalport.c b/ports/nrf/mphalport.c
new file mode 100644
index 0000000000..1abd4b186a
--- /dev/null
+++ b/ports/nrf/mphalport.c
@@ -0,0 +1,77 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2015 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <errno.h>
+#include <string.h>
+
+#include "py/mpstate.h"
+#include "py/mphal.h"
+#include "py/mperrno.h"
+#include "uart.h"
+
+// this table converts from HAL_StatusTypeDef to POSIX errno
+const byte mp_hal_status_to_errno_table[4] = {
+    [HAL_OK] = 0,
+    [HAL_ERROR] = MP_EIO,
+    [HAL_BUSY] = MP_EBUSY,
+    [HAL_TIMEOUT] = MP_ETIMEDOUT,
+};
+
+NORETURN void mp_hal_raise(HAL_StatusTypeDef status) {
+    nlr_raise(mp_obj_new_exception_arg1(&mp_type_OSError, MP_OBJ_NEW_SMALL_INT(mp_hal_status_to_errno_table[status])));
+}
+
+void mp_hal_set_interrupt_char(int c) {
+
+}
+
+#if (MICROPY_PY_BLE_NUS == 0)
+int mp_hal_stdin_rx_chr(void) {
+    for (;;) {
+        if (MP_STATE_PORT(pyb_stdio_uart) != NULL && uart_rx_any(MP_STATE_PORT(pyb_stdio_uart))) {
+            return uart_rx_char(MP_STATE_PORT(pyb_stdio_uart));
+        }
+    }
+
+    return 0;
+}
+
+void mp_hal_stdout_tx_strn(const char *str, mp_uint_t len) {
+    if (MP_STATE_PORT(pyb_stdio_uart) != NULL) {
+        uart_tx_strn(MP_STATE_PORT(pyb_stdio_uart), str, len);
+    }
+}
+
+void mp_hal_stdout_tx_strn_cooked(const char *str, mp_uint_t len) {
+    if (MP_STATE_PORT(pyb_stdio_uart) != NULL) {
+        uart_tx_strn_cooked(MP_STATE_PORT(pyb_stdio_uart), str, len);
+    }
+}
+#endif
+
+void mp_hal_stdout_tx_str(const char *str) {
+    mp_hal_stdout_tx_strn(str, strlen(str));
+}
diff --git a/ports/nrf/mphalport.h b/ports/nrf/mphalport.h
new file mode 100644
index 0000000000..4e4e117033
--- /dev/null
+++ b/ports/nrf/mphalport.h
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2015 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef __NRF52_HAL
+#define __NRF52_HAL
+
+#include "py/mpconfig.h"
+#include NRF5_HAL_H
+#include "pin.h"
+#include "hal_gpio.h"
+
+typedef enum
+{
+  HAL_OK       = 0x00,
+  HAL_ERROR    = 0x01,
+  HAL_BUSY     = 0x02,
+  HAL_TIMEOUT  = 0x03
+} HAL_StatusTypeDef;
+
+static inline uint32_t hal_tick_fake(void) {
+	return 0;
+}
+
+#define mp_hal_ticks_ms hal_tick_fake // TODO: implement. Right now, return 0 always
+
+extern const unsigned char mp_hal_status_to_errno_table[4];
+
+NORETURN void mp_hal_raise(HAL_StatusTypeDef status);
+void mp_hal_set_interrupt_char(int c); // -1 to disable
+
+int mp_hal_stdin_rx_chr(void);
+void mp_hal_stdout_tx_str(const char *str);
+
+#define mp_hal_pin_obj_t const pin_obj_t*
+#define mp_hal_get_pin_obj(o)    pin_find(o)
+#define mp_hal_pin_high(p)       hal_gpio_pin_high(p)
+#define mp_hal_pin_low(p)        hal_gpio_pin_low(p)
+#define mp_hal_pin_read(p)       hal_gpio_pin_read(p)
+#define mp_hal_pin_write(p, v)   do { if (v) { mp_hal_pin_high(p); } else { mp_hal_pin_low(p); } } while (0)
+#define mp_hal_pin_od_low(p)     mp_hal_pin_low(p)
+#define mp_hal_pin_od_high(p)    mp_hal_pin_high(p)
+#define mp_hal_pin_open_drain(p) hal_gpio_cfg_pin(p->port, p->pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED)
+
+
+// TODO: empty implementation for now. Used by machine_spi.c:69
+#define mp_hal_delay_us_fast(p)
+#define mp_hal_ticks_us() (0)
+#define mp_hal_ticks_cpu() (0)
+
+#endif
+
diff --git a/ports/nrf/nrf51_af.csv b/ports/nrf/nrf51_af.csv
new file mode 100644
index 0000000000..2fc34a06a0
--- /dev/null
+++ b/ports/nrf/nrf51_af.csv
@@ -0,0 +1,32 @@
+PA0,PA0
+PA1,PA1,ADC0_IN2
+PA2,PA2,ADC0_IN3
+PA3,PA3,ADC0_IN4
+PA4,PA4,ADC0_IN5
+PA5,PA5,ADC0_IN6
+PA6,PA6,ADC0_IN7
+PA7,PA7
+PA8,PA8
+PA9,PA9
+PA10,PA10
+PA11,PA11
+PA12,PA12
+PA13,PA13
+PA14,PA14
+PA15,PA15
+PA16,PA16
+PA17,PA17
+PA18,PA18
+PA19,PA19
+PA20,PA20
+PA21,PA21
+PA22,PA22
+PA23,PA23
+PA24,PA24
+PA25,PA25
+PA26,PA26
+PA27,PA27
+PA28,PA28
+PA29,PA29
+PA30,PA30
+PA31,PA31
\ No newline at end of file
diff --git a/ports/nrf/nrf52_af.csv b/ports/nrf/nrf52_af.csv
new file mode 100644
index 0000000000..44a7d8144f
--- /dev/null
+++ b/ports/nrf/nrf52_af.csv
@@ -0,0 +1,48 @@
+PA0,PA0
+PA1,PA1
+PA2,PA2
+PA3,PA3
+PA4,PA4
+PA5,PA5
+PA6,PA6
+PA7,PA7
+PA8,PA8
+PA9,PA9
+PA10,PA10
+PA11,PA11
+PA12,PA12
+PA13,PA13
+PA14,PA14
+PA15,PA15
+PA16,PA16
+PA17,PA17
+PA18,PA18
+PA19,PA19
+PA20,PA20
+PA21,PA21
+PA22,PA22
+PA23,PA23
+PA24,PA24
+PA25,PA25
+PA26,PA26
+PA27,PA27
+PA28,PA28
+PA29,PA29
+PA30,PA30
+PA31,PA31
+PB0,PB0
+PB1,PB1
+PB2,PB2
+PB3,PB3
+PB4,PB4
+PB5,PB5
+PB6,PB6
+PB7,PB7
+PB8,PB8
+PB9,PB9
+PB10,PB10
+PB11,PB11
+PB12,PB12
+PB13,PB13
+PB14,PB14
+PB15,PB15
\ No newline at end of file
diff --git a/ports/nrf/pin_defs_nrf5.h b/ports/nrf/pin_defs_nrf5.h
new file mode 100644
index 0000000000..94f8f3c9c1
--- /dev/null
+++ b/ports/nrf/pin_defs_nrf5.h
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2016 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+// This file contains pin definitions that are specific to the nrf port.
+// This file should only ever be #included by pin.h and not directly.
+
+enum {
+  PORT_A,
+  PORT_B,
+};
+
+enum {
+  AF_FN_UART,
+  AF_FN_SPI,
+};
+
+enum {
+  AF_PIN_TYPE_UART_TX = 0,
+  AF_PIN_TYPE_UART_RX,
+  AF_PIN_TYPE_UART_CTS,
+  AF_PIN_TYPE_UART_RTS,
+
+  AF_PIN_TYPE_SPI_MOSI = 0,
+  AF_PIN_TYPE_SPI_MISO,
+  AF_PIN_TYPE_SPI_SCK,
+  AF_PIN_TYPE_SPI_NSS,
+};
+
+#define PIN_DEFS_PORT_AF_UNION \
+		NRF_UART_Type  *UART;
+//		NRF_SPI_Type  *SPIM;
+//		NRF_SPIS_Type *SPIS;
+
+
+typedef NRF_GPIO_Type pin_gpio_t;
diff --git a/ports/nrf/pin_named_pins.c b/ports/nrf/pin_named_pins.c
new file mode 100644
index 0000000000..e1d8736b9c
--- /dev/null
+++ b/ports/nrf/pin_named_pins.c
@@ -0,0 +1,92 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <stdio.h>
+#include <string.h>
+
+#include "py/runtime.h"
+#include "py/mphal.h"
+#include "pin.h"
+
+STATIC void pin_named_pins_obj_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) {
+    pin_named_pins_obj_t *self = self_in;
+    mp_printf(print, "<Pin.%q>", self->name);
+}
+
+const mp_obj_type_t pin_cpu_pins_obj_type = {
+    { &mp_type_type },
+    .name = MP_QSTR_cpu,
+    .print = pin_named_pins_obj_print,
+    .locals_dict = (mp_obj_t)&pin_cpu_pins_locals_dict,
+};
+
+const mp_obj_type_t pin_board_pins_obj_type = {
+    { &mp_type_type },
+    .name = MP_QSTR_board,
+    .print = pin_named_pins_obj_print,
+    .locals_dict = (mp_obj_t)&pin_board_pins_locals_dict,
+};
+
+const pin_obj_t *pin_find_named_pin(const mp_obj_dict_t *named_pins, mp_obj_t name) {
+    mp_map_t *named_map = mp_obj_dict_get_map((mp_obj_t)named_pins);
+    mp_map_elem_t *named_elem = mp_map_lookup(named_map, name, MP_MAP_LOOKUP);
+    if (named_elem != NULL && named_elem->value != NULL) {
+        return named_elem->value;
+    }
+    return NULL;
+}
+
+const pin_af_obj_t *pin_find_af(const pin_obj_t *pin, uint8_t fn, uint8_t unit) {
+    const pin_af_obj_t *af = pin->af;
+    for (mp_uint_t i = 0; i < pin->num_af; i++, af++) {
+        if (af->fn == fn && af->unit == unit) {
+            return af;
+        }
+    }
+    return NULL;
+}
+
+const pin_af_obj_t *pin_find_af_by_index(const pin_obj_t *pin, mp_uint_t af_idx) {
+    const pin_af_obj_t *af = pin->af;
+    for (mp_uint_t i = 0; i < pin->num_af; i++, af++) {
+        if (af->idx == af_idx) {
+            return af;
+        }
+    }
+    return NULL;
+}
+
+/* unused
+const pin_af_obj_t *pin_find_af_by_name(const pin_obj_t *pin, const char *name) {
+    const pin_af_obj_t *af = pin->af;
+    for (mp_uint_t i = 0; i < pin->num_af; i++, af++) {
+        if (strcmp(name, qstr_str(af->name)) == 0) {
+            return af;
+        }
+    }
+    return NULL;
+}
+*/
diff --git a/ports/nrf/qstrdefsport.h b/ports/nrf/qstrdefsport.h
new file mode 100644
index 0000000000..ef398a4c0a
--- /dev/null
+++ b/ports/nrf/qstrdefsport.h
@@ -0,0 +1,139 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2015 Glenn Ruben Bakke
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+// qstrs specific to this port
+Q(a)
+Q(a#)
+Q(a#:1)
+Q(a#:3)
+Q(a2)
+Q(a4)
+Q(a4:1)
+Q(a4:3)
+Q(a:1)
+Q(a:2)
+Q(a:4)
+Q(a:5)
+Q(b)
+Q(b2:1)
+Q(b3)
+Q(b4)
+Q(b4:1)
+Q(b4:2)
+Q(b5)
+Q(b5:1)
+Q(b:1)
+Q(b:2)
+Q(c)
+Q(c#)
+Q(c#5)
+Q(c#5:1)
+Q(c#5:2)
+Q(c#:1)
+Q(c#:8)
+Q(c2:2)
+Q(c3)
+Q(c3:3)
+Q(c3:4)
+Q(c4)
+Q(c4:1)
+Q(c4:3)
+Q(c4:4)
+Q(c5)
+Q(c5:1)
+Q(c5:2)
+Q(c5:3)
+Q(c5:4)
+Q(c:1)
+Q(c:2)
+Q(c:3)
+Q(c:4)
+Q(c:8)
+Q(d)
+Q(d#)
+Q(d#5:2)
+Q(d#:2)
+Q(d#:3)
+Q(d3)
+Q(d4)
+Q(d4:1)
+Q(d5)
+Q(d5:1)
+Q(d5:2)
+Q(d:1)
+Q(d:2)
+Q(d:3)
+Q(d:4)
+Q(d:5)
+Q(d:6)
+Q(d:8)
+Q(e)
+Q(e3:3)
+Q(e4)
+Q(e4:1)
+Q(e5)
+Q(e6:3)
+Q(e:1)
+Q(e:2)
+Q(e:3)
+Q(e:4)
+Q(e:5)
+Q(e:6)
+Q(e:8)
+Q(eb:8)
+Q(f)
+Q(f#)
+Q(f#5)
+Q(f#5:2)
+Q(f#:1)
+Q(f#:2)
+Q(f#:8)
+Q(f2)
+Q(f:1)
+Q(f:2)
+Q(f:3)
+Q(f:4)
+Q(f:8)
+Q(g)
+Q(g#)
+Q(g#:1)
+Q(g#:3)
+Q(g3:1)
+Q(g4)
+Q(g4:1)
+Q(g4:2)
+Q(g5)
+Q(g5:1)
+Q(g:1)
+Q(g:2)
+Q(g:3)
+Q(g:8)
+Q(r)
+Q(r4:2)
+Q(r:1)
+Q(r:2)
+Q(r:3)
+
diff --git a/pic16bit/Makefile b/ports/pic16bit/Makefile
similarity index 98%
rename from pic16bit/Makefile
rename to ports/pic16bit/Makefile
index ebf4fc2e80..970e75d1fb 100644
--- a/pic16bit/Makefile
+++ b/ports/pic16bit/Makefile
@@ -1,4 +1,4 @@
-include ../py/mkenv.mk
+include ../../py/mkenv.mk
 
 # qstr definitions (must come before including py.mk)
 QSTR_DEFS = qstrdefsport.h
diff --git a/pic16bit/board.c b/ports/pic16bit/board.c
similarity index 100%
rename from pic16bit/board.c
rename to ports/pic16bit/board.c
diff --git a/pic16bit/board.h b/ports/pic16bit/board.h
similarity index 100%
rename from pic16bit/board.h
rename to ports/pic16bit/board.h
diff --git a/pic16bit/main.c b/ports/pic16bit/main.c
similarity index 100%
rename from pic16bit/main.c
rename to ports/pic16bit/main.c
diff --git a/pic16bit/modpyb.c b/ports/pic16bit/modpyb.c
similarity index 100%
rename from pic16bit/modpyb.c
rename to ports/pic16bit/modpyb.c
diff --git a/pic16bit/modpyb.h b/ports/pic16bit/modpyb.h
similarity index 100%
rename from pic16bit/modpyb.h
rename to ports/pic16bit/modpyb.h
diff --git a/pic16bit/modpybled.c b/ports/pic16bit/modpybled.c
similarity index 100%
rename from pic16bit/modpybled.c
rename to ports/pic16bit/modpybled.c
diff --git a/pic16bit/modpybswitch.c b/ports/pic16bit/modpybswitch.c
similarity index 100%
rename from pic16bit/modpybswitch.c
rename to ports/pic16bit/modpybswitch.c
diff --git a/pic16bit/mpconfigport.h b/ports/pic16bit/mpconfigport.h
similarity index 100%
rename from pic16bit/mpconfigport.h
rename to ports/pic16bit/mpconfigport.h
diff --git a/pic16bit/pic16bit_mphal.c b/ports/pic16bit/pic16bit_mphal.c
similarity index 100%
rename from pic16bit/pic16bit_mphal.c
rename to ports/pic16bit/pic16bit_mphal.c
diff --git a/pic16bit/pic16bit_mphal.h b/ports/pic16bit/pic16bit_mphal.h
similarity index 100%
rename from pic16bit/pic16bit_mphal.h
rename to ports/pic16bit/pic16bit_mphal.h
diff --git a/pic16bit/qstrdefsport.h b/ports/pic16bit/qstrdefsport.h
similarity index 100%
rename from pic16bit/qstrdefsport.h
rename to ports/pic16bit/qstrdefsport.h
diff --git a/pic16bit/unistd.h b/ports/pic16bit/unistd.h
similarity index 92%
rename from pic16bit/unistd.h
rename to ports/pic16bit/unistd.h
index 5b60c8a626..23c5e54c75 100644
--- a/pic16bit/unistd.h
+++ b/ports/pic16bit/unistd.h
@@ -3,6 +3,7 @@
 
 // XC16 compiler doesn't seem to have unistd.h file
 
+#define SEEK_SET 0
 #define SEEK_CUR 1
 
 typedef int ssize_t;
diff --git a/qemu-arm/Makefile b/ports/qemu-arm/Makefile
similarity index 99%
rename from qemu-arm/Makefile
rename to ports/qemu-arm/Makefile
index 71403cb5e7..39e13853f4 100644
--- a/qemu-arm/Makefile
+++ b/ports/qemu-arm/Makefile
@@ -1,4 +1,4 @@
-include ../py/mkenv.mk
+include ../../py/mkenv.mk
 -include mpconfigport.mk
 
 # qstr definitions (must come before including py.mk)
diff --git a/qemu-arm/README.md b/ports/qemu-arm/README.md
similarity index 100%
rename from qemu-arm/README.md
rename to ports/qemu-arm/README.md
diff --git a/qemu-arm/main.c b/ports/qemu-arm/main.c
similarity index 97%
rename from qemu-arm/main.c
rename to ports/qemu-arm/main.c
index d5fbcd84bc..d23ef576f9 100644
--- a/qemu-arm/main.c
+++ b/ports/qemu-arm/main.c
@@ -4,10 +4,8 @@
 #include <string.h>
 #include <malloc.h>
 
-#include "py/nlr.h"
 #include "py/obj.h"
 #include "py/compile.h"
-#include "py/runtime0.h"
 #include "py/runtime.h"
 #include "py/stackctrl.h"
 #include "py/gc.h"
diff --git a/qemu-arm/modmachine.c b/ports/qemu-arm/modmachine.c
similarity index 100%
rename from qemu-arm/modmachine.c
rename to ports/qemu-arm/modmachine.c
diff --git a/qemu-arm/moduos.c b/ports/qemu-arm/moduos.c
similarity index 100%
rename from qemu-arm/moduos.c
rename to ports/qemu-arm/moduos.c
diff --git a/qemu-arm/mpconfigport.h b/ports/qemu-arm/mpconfigport.h
similarity index 98%
rename from qemu-arm/mpconfigport.h
rename to ports/qemu-arm/mpconfigport.h
index 317064b7f1..1998837846 100644
--- a/qemu-arm/mpconfigport.h
+++ b/ports/qemu-arm/mpconfigport.h
@@ -18,6 +18,7 @@
 #define MICROPY_FLOAT_IMPL          (MICROPY_FLOAT_IMPL_FLOAT)
 #define MICROPY_CAN_OVERRIDE_BUILTINS (1)
 #define MICROPY_PY_ALL_SPECIAL_METHODS (1)
+#define MICROPY_PY_REVERSE_SPECIAL_METHODS (1)
 #define MICROPY_PY_ARRAY_SLICE_ASSIGN (1)
 #define MICROPY_PY_BUILTINS_FROZENSET (1)
 #define MICROPY_PY_BUILTINS_MEMORYVIEW (1)
diff --git a/qemu-arm/mphalport.h b/ports/qemu-arm/mphalport.h
similarity index 100%
rename from qemu-arm/mphalport.h
rename to ports/qemu-arm/mphalport.h
diff --git a/qemu-arm/qstrdefsport.h b/ports/qemu-arm/qstrdefsport.h
similarity index 100%
rename from qemu-arm/qstrdefsport.h
rename to ports/qemu-arm/qstrdefsport.h
diff --git a/qemu-arm/test_main.c b/ports/qemu-arm/test_main.c
similarity index 98%
rename from qemu-arm/test_main.c
rename to ports/qemu-arm/test_main.c
index 5c07d16076..c018ae4285 100644
--- a/qemu-arm/test_main.c
+++ b/ports/qemu-arm/test_main.c
@@ -4,10 +4,8 @@
 #include <string.h>
 #include <malloc.h>
 
-#include "py/nlr.h"
 #include "py/obj.h"
 #include "py/compile.h"
-#include "py/runtime0.h"
 #include "py/runtime.h"
 #include "py/stackctrl.h"
 #include "py/gc.h"
diff --git a/stmhal/.gitignore b/ports/stm32/.gitignore
similarity index 100%
rename from stmhal/.gitignore
rename to ports/stm32/.gitignore
diff --git a/stmhal/Makefile b/ports/stm32/Makefile
similarity index 91%
rename from stmhal/Makefile
rename to ports/stm32/Makefile
index a0c2ba2aab..e3cb1b217d 100644
--- a/stmhal/Makefile
+++ b/ports/stm32/Makefile
@@ -8,7 +8,7 @@ endif
 # If the build directory is not given, make it reflect the board name.
 BUILD ?= build-$(BOARD)
 
-include ../py/mkenv.mk
+include ../../py/mkenv.mk
 -include mpconfigport.mk
 include boards/$(BOARD)/mpconfigboard.mk
 
@@ -22,8 +22,9 @@ FROZEN_MPY_DIR ?= modules
 include $(TOP)/py/py.mk
 
 LD_DIR=boards
-CMSIS_DIR=cmsis
-HAL_DIR=hal/$(MCU_SERIES)
+CMSIS_DIR=$(TOP)/lib/stm32lib/CMSIS/STM32$(MCU_SERIES_UPPER)xx/Include
+MCU_SERIES_UPPER = $(shell echo $(MCU_SERIES) | tr '[:lower:]' '[:upper:]')
+HAL_DIR=lib/stm32lib/STM32$(MCU_SERIES_UPPER)xx_HAL_Driver
 USBDEV_DIR=usbdev
 #USBHOST_DIR=usbhost
 FATFS_DIR=lib/oofatfs
@@ -44,7 +45,7 @@ INC += -I$(TOP)
 INC += -I$(BUILD)
 INC += -I$(TOP)/lib/cmsis/inc
 INC += -I$(CMSIS_DIR)/
-INC += -I$(HAL_DIR)/inc
+INC += -I$(TOP)/$(HAL_DIR)/Inc
 INC += -I$(USBDEV_DIR)/core/inc -I$(USBDEV_DIR)/class/inc
 #INC += -I$(USBHOST_DIR)
 
@@ -206,7 +207,7 @@ SRC_C = \
 	timer.c \
 	led.c \
 	pin.c \
-	pin_defs_stmhal.c \
+	pin_defs_stm32.c \
 	pin_named_pins.c \
 	bufhelper.c \
 	dma.c \
@@ -245,7 +246,7 @@ SRC_O = \
 	startup_stm32.o \
 	gchelper.o \
 
-SRC_HAL = $(addprefix $(HAL_DIR)/src/stm32$(MCU_SERIES)xx_,\
+SRC_HAL = $(addprefix $(HAL_DIR)/Src/stm32$(MCU_SERIES)xx_,\
 	hal.c \
 	hal_adc.c \
 	hal_adc_ex.c \
@@ -345,7 +346,12 @@ $(PY_BUILD)/formatfloat.o: COPT += -Os
 $(PY_BUILD)/parsenum.o: COPT += -Os
 $(PY_BUILD)/mpprint.o: COPT += -Os
 
-all: $(BUILD)/firmware.dfu $(BUILD)/firmware.hex
+all: $(TOP)/lib/stm32lib/README.md $(BUILD)/firmware.dfu $(BUILD)/firmware.hex
+
+# For convenience, automatically fetch required submodules if they don't exist
+$(TOP)/lib/stm32lib/README.md:
+	$(ECHO) "stm32lib submodule not found, fetching it now..."
+	(cd $(TOP) && git submodule update --init lib/stm32lib)
 
 ifneq ($(FROZEN_DIR),)
 # To use frozen source modules, put your .py files in a subdirectory (eg scripts/)
@@ -398,6 +404,7 @@ $(BUILD)/firmware.elf: $(OBJ)
 	$(Q)$(LD) $(LDFLAGS) -o $@ $^ $(LIBS)
 	$(Q)$(SIZE) $@
 
+PLLVALUES = boards/pllvalues.py
 MAKE_PINS = boards/make-pins.py
 BOARD_PINS = boards/$(BOARD)/pins.csv
 PREFIX_FILE = boards/stm32f4xx_prefix.c
@@ -426,7 +433,7 @@ SRC_QSTR_AUTO_DEPS += $(GEN_CDCINF_HEADER)
 # any of the objects. The normal dependency generation will deal with the
 # case when pins.h is modified. But when it doesn't exist, we don't know
 # which source files might need it.
-$(OBJ): | $(HEADER_BUILD)/pins.h
+$(OBJ): | $(GEN_PINS_HDR)
 
 # With conditional pins, we may need to regenerate qstrdefs.h when config
 # options change.
@@ -444,11 +451,17 @@ $(BUILD)/%_$(BOARD).c $(HEADER_BUILD)/%.h $(HEADER_BUILD)/%_af_const.h $(BUILD)/
 $(BUILD)/pins_$(BOARD).o: $(BUILD)/pins_$(BOARD).c
 	$(call compile_c)
 
+GEN_PLLFREQTABLE_HDR = $(HEADER_BUILD)/pllfreqtable.h
 GEN_STMCONST_HDR = $(HEADER_BUILD)/modstm_const.h
 GEN_STMCONST_QSTR = $(BUILD)/modstm_qstr.h
 GEN_STMCONST_MPZ = $(HEADER_BUILD)/modstm_mpz.h
 CMSIS_MCU_LOWER = $(shell echo $(CMSIS_MCU) | tr '[:upper:]' '[:lower:]')
-CMSIS_MCU_HDR = cmsis/$(CMSIS_MCU_LOWER).h
+CMSIS_MCU_HDR = $(CMSIS_DIR)/$(CMSIS_MCU_LOWER).h
+
+modmachine.c: $(GEN_PLLFREQTABLE_HDR)
+$(GEN_PLLFREQTABLE_HDR): $(PLLVALUES) | $(HEADER_BUILD)
+	$(ECHO) "Create $@"
+	$(Q)$(PYTHON) $(PLLVALUES) -c file:boards/$(BOARD)/stm32$(MCU_SERIES)xx_hal_conf.h > $@
 
 $(BUILD)/modstm.o: $(GEN_STMCONST_HDR)
 # Use a pattern rule here so that make will only call make-stmconst.py once to
diff --git a/stmhal/README.md b/ports/stm32/README.md
similarity index 95%
rename from stmhal/README.md
rename to ports/stm32/README.md
index 32b6d41766..bb184e8db6 100644
--- a/stmhal/README.md
+++ b/ports/stm32/README.md
@@ -24,7 +24,7 @@ bytecode.  The cross-compiler is built and run on the host machine, using:
 $ make -C mpy-cross
 ```
 This command should be executed from the root directory of this repository.
-All other commands below should be executed from the stmhal/ directory.
+All other commands below should be executed from the ports/stm32/ directory.
 
 An ARM compiler is required for the build, along with the associated binary
 utilities.  The default compiler is `arm-none-eabi-gcc`, which is available for
@@ -71,7 +71,7 @@ Or using `dfu-util` directly:
 
 ST Discovery or Nucleo boards have a builtin programmer called ST-LINK. With
 these boards and using Linux or OS X, you have the option to upload the
-`stmhal` firmware using the `st-flash` utility from the
+`stm32` firmware using the `st-flash` utility from the
 [stlink](https://github.com/texane/stlink) project. To do so, connect the board
 with a mini USB cable to its ST-LINK USB port and then use the make target
 `deploy-stlink`. For example, if you have the STM32F4DISCOVERY board, you can
@@ -101,7 +101,7 @@ a mini USB cable to its ST-LINK USB port and then use the make target
     $ make BOARD=STM32F4DISC deploy-openocd
 
 The `openocd` program, which writes the firmware to the target board's flash,
-is configured via the file `stmhal/boards/openocd_stm32f4.cfg`. This
+is configured via the file `ports/stm32/boards/openocd_stm32f4.cfg`. This
 configuration should work for all boards based on a STM32F4xx MCU with a
 ST-LINKv2 interface. You can override the path to this configuration by setting
 `OPENOCD_CONFIG` in your Makefile or on the command line.
diff --git a/stmhal/accel.c b/ports/stm32/accel.c
similarity index 99%
rename from stmhal/accel.c
rename to ports/stm32/accel.c
index 512a6e313a..7b36e20823 100644
--- a/stmhal/accel.c
+++ b/ports/stm32/accel.c
@@ -28,7 +28,6 @@
 #include <string.h>
 
 #include "py/mphal.h"
-#include "py/nlr.h"
 #include "py/runtime.h"
 #include "pin.h"
 #include "genhdr/pins.h"
diff --git a/stmhal/accel.h b/ports/stm32/accel.h
similarity index 100%
rename from stmhal/accel.h
rename to ports/stm32/accel.h
diff --git a/stmhal/adc.c b/ports/stm32/adc.c
similarity index 99%
rename from stmhal/adc.c
rename to ports/stm32/adc.c
index dd59e29c88..9a0dc56a37 100644
--- a/stmhal/adc.c
+++ b/ports/stm32/adc.c
@@ -27,7 +27,6 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "py/nlr.h"
 #include "py/runtime.h"
 #include "py/binary.h"
 #include "py/mphal.h"
@@ -95,7 +94,7 @@
       defined(STM32F746xx) || defined(STM32F767xx) || \
       defined(STM32F769xx) || defined(STM32F446xx)
 #define VBAT_DIV (4)
-#elif defined(STM32L476xx)
+#elif defined(STM32L475xx) || defined(STM32L476xx)
 #define VBAT_DIV (3)
 #else
 #error Unsupported processor
diff --git a/stmhal/adc.h b/ports/stm32/adc.h
similarity index 100%
rename from stmhal/adc.h
rename to ports/stm32/adc.h
diff --git a/stmhal/autoflash b/ports/stm32/autoflash
similarity index 100%
rename from stmhal/autoflash
rename to ports/stm32/autoflash
diff --git a/ports/stm32/boards/B_L475E_IOT01A/mpconfigboard.h b/ports/stm32/boards/B_L475E_IOT01A/mpconfigboard.h
new file mode 100644
index 0000000000..77f029c006
--- /dev/null
+++ b/ports/stm32/boards/B_L475E_IOT01A/mpconfigboard.h
@@ -0,0 +1,76 @@
+#define MICROPY_HW_BOARD_NAME       "B-L475E-IOT01A"
+#define MICROPY_HW_MCU_NAME         "STM32L475"
+
+#define MICROPY_HW_HAS_SWITCH       (1)
+#define MICROPY_HW_HAS_FLASH        (0)
+#define MICROPY_HW_HAS_SDCARD       (0)
+#define MICROPY_HW_HAS_MMA7660      (0)
+#define MICROPY_HW_HAS_LIS3DSH      (0)
+#define MICROPY_HW_HAS_LCD          (0)
+#define MICROPY_HW_ENABLE_RNG       (1)
+#define MICROPY_HW_ENABLE_RTC       (1)
+#define MICROPY_HW_ENABLE_TIMER     (1)
+#define MICROPY_HW_ENABLE_SERVO     (0)
+#define MICROPY_HW_ENABLE_DAC       (0)
+#define MICROPY_HW_ENABLE_CAN       (0)
+
+// MSI is used and is 4MHz
+#define MICROPY_HW_CLK_PLLM (1)
+#define MICROPY_HW_CLK_PLLN (40)
+#define MICROPY_HW_CLK_PLLP (RCC_PLLP_DIV7)
+#define MICROPY_HW_CLK_PLLR (RCC_PLLR_DIV2)
+#define MICROPY_HW_CLK_PLLQ (RCC_PLLQ_DIV4)
+
+#define MICROPY_HW_FLASH_LATENCY    FLASH_LATENCY_4
+
+// USART1 config connected to ST-Link
+#define MICROPY_HW_UART1_TX     (pin_B6)
+#define MICROPY_HW_UART1_RX     (pin_B7)
+// USART2 config connected to PMOD: Flow control is defined and therfore used
+#define MICROPY_HW_UART2_CTS    (pin_D3)
+#define MICROPY_HW_UART2_RTS    (pin_D4)
+#define MICROPY_HW_UART2_TX     (pin_D5)
+#define MICROPY_HW_UART2_RX     (pin_D6)
+// USART3 config for internal use
+#define MICROPY_HW_UART3_TX     (pin_D8)
+#define MICROPY_HW_UART3_RX     (pin_D9)
+// USART4 config 
+#define MICROPY_HW_UART4_TX     (pin_A0)
+#define MICROPY_HW_UART4_RX     (pin_A1)
+// USART 1 is connected to the virtual com port on the ST-LINK
+#define MICROPY_HW_UART_REPL        PYB_UART_1
+#define MICROPY_HW_UART_REPL_BAUD   115200
+
+// I2C busses
+#define MICROPY_HW_I2C1_SCL (pin_B8)
+#define MICROPY_HW_I2C1_SDA (pin_B9)
+#define MICROPY_HW_I2C2_SCL (pin_B10)
+#define MICROPY_HW_I2C2_SDA (pin_B11)
+
+// SPI busses
+#define MICROPY_HW_SPI1_NSS     (pin_A4)
+#define MICROPY_HW_SPI1_SCK     (pin_A5)
+#define MICROPY_HW_SPI1_MISO    (pin_A6)
+#define MICROPY_HW_SPI1_MOSI    (pin_A7)
+
+#define MICROPY_HW_SPI2_NSS     (pin_D0)
+#define MICROPY_HW_SPI2_SCK     (pin_D1)
+#define MICROPY_HW_SPI2_MISO    (pin_D3)
+#define MICROPY_HW_SPI2_MOSI    (pin_D4)
+
+#define MICROPY_HW_SPI3_NSS     (pin_A15)
+#define MICROPY_HW_SPI3_SCK     (pin_C10)
+#define MICROPY_HW_SPI3_MISO    (pin_C11)
+#define MICROPY_HW_SPI3_MOSI    (pin_C12)
+
+// User and wake-up switch. Pressing the button makes the input go low.
+#define MICROPY_HW_USRSW_PIN        (pin_C13)
+#define MICROPY_HW_USRSW_PULL       (GPIO_NOPULL)
+#define MICROPY_HW_USRSW_EXTI_MODE  (GPIO_MODE_IT_FALLING)
+#define MICROPY_HW_USRSW_PRESSED    (0)
+
+// LEDs
+#define MICROPY_HW_LED1             (pin_A5) // green
+#define MICROPY_HW_LED2             (pin_B14) // green
+#define MICROPY_HW_LED_ON(pin)      (mp_hal_pin_high(pin))
+#define MICROPY_HW_LED_OFF(pin)     (mp_hal_pin_low(pin))
diff --git a/ports/stm32/boards/B_L475E_IOT01A/mpconfigboard.mk b/ports/stm32/boards/B_L475E_IOT01A/mpconfigboard.mk
new file mode 100644
index 0000000000..1ba61a3274
--- /dev/null
+++ b/ports/stm32/boards/B_L475E_IOT01A/mpconfigboard.mk
@@ -0,0 +1,8 @@
+MCU_SERIES = l4
+CMSIS_MCU = STM32L475xx
+# The stm32l475 does not have a LDC controller which is
+# the only diffrence to the stm32l476 - so reuse some files.
+AF_FILE = boards/stm32l476_af.csv
+LD_FILE = boards/stm32l476xg.ld
+TEXT_ADDR = 0x08004000
+OPENOCD_CONFIG = boards/openocd_stm32l4.cfg
diff --git a/ports/stm32/boards/B_L475E_IOT01A/pins.csv b/ports/stm32/boards/B_L475E_IOT01A/pins.csv
new file mode 100644
index 0000000000..afe87b71c4
--- /dev/null
+++ b/ports/stm32/boards/B_L475E_IOT01A/pins.csv
@@ -0,0 +1,82 @@
+PA0,PA0
+PA1,PA1
+PA2,PA2
+PA3,PA3
+PA4,PA4
+PA5,PA5
+PA6,PA6
+PA7,PA7
+PA8,PA8
+PA9,PA9
+PA10,PA10
+PA11,PA11
+PA12,PA12
+PA13,PA13
+PA14,PA14
+PA15,PA15
+PB0,PB0
+PB1,PB1
+PB2,PB2
+PB3,PB3
+PB4,PB4
+PB5,PB5
+PB6,PB6
+PB7,PB7
+PB8,PB8
+PB9,PB9
+PB10,PB10
+PB11,PB11
+PB12,PB12
+PB13,PB13
+PB14,PB14
+PB15,PB15
+PC0,PC0
+PC1,PC1
+PC2,PC2
+PC3,PC3
+PC4,PC4
+PC5,PC5
+PC6,PC6
+PC7,PC7
+PC8,PC8
+PC9,PC9
+PC10,PC10
+PC11,PC11
+PC12,PC12
+PC13,PC13
+PC14,PC14
+PC15,PC15
+PD0,PD0
+PD1,PD1
+PD2,PD2
+PD3,PD3
+PD4,PD4
+PD5,PD5
+PD6,PD6
+PD7,PD7
+PD8,PD8
+PD9,PD9
+PD10,PD10
+PD11,PD11
+PD12,PD12
+PD13,PD13
+PD14,PD14
+PD15,PD15
+PE0,PE0
+PE1,PE1
+PE2,PE2
+PE3,PE3
+PE4,PE4
+PE5,PE5
+PE6,PE6
+PE7,PE7
+PE8,PE8
+PE9,PE9
+PE10,PE10
+PE11,PE11
+PE12,PE12
+PE13,PE13
+PE14,PE14
+PE15,PE15
+PH0,PH0
+PH1,PH1
diff --git a/stmhal/boards/LIMIFROG/stm32l4xx_hal_conf.h b/ports/stm32/boards/B_L475E_IOT01A/stm32l4xx_hal_conf.h
similarity index 100%
rename from stmhal/boards/LIMIFROG/stm32l4xx_hal_conf.h
rename to ports/stm32/boards/B_L475E_IOT01A/stm32l4xx_hal_conf.h
diff --git a/stmhal/boards/CERB40/mpconfigboard.h b/ports/stm32/boards/CERB40/mpconfigboard.h
similarity index 100%
rename from stmhal/boards/CERB40/mpconfigboard.h
rename to ports/stm32/boards/CERB40/mpconfigboard.h
diff --git a/stmhal/boards/CERB40/mpconfigboard.mk b/ports/stm32/boards/CERB40/mpconfigboard.mk
similarity index 100%
rename from stmhal/boards/CERB40/mpconfigboard.mk
rename to ports/stm32/boards/CERB40/mpconfigboard.mk
diff --git a/stmhal/boards/CERB40/pins.csv b/ports/stm32/boards/CERB40/pins.csv
similarity index 100%
rename from stmhal/boards/CERB40/pins.csv
rename to ports/stm32/boards/CERB40/pins.csv
diff --git a/stmhal/boards/CERB40/stm32f4xx_hal_conf.h b/ports/stm32/boards/CERB40/stm32f4xx_hal_conf.h
similarity index 100%
rename from stmhal/boards/CERB40/stm32f4xx_hal_conf.h
rename to ports/stm32/boards/CERB40/stm32f4xx_hal_conf.h
diff --git a/stmhal/boards/ESPRUINO_PICO/mpconfigboard.h b/ports/stm32/boards/ESPRUINO_PICO/mpconfigboard.h
similarity index 100%
rename from stmhal/boards/ESPRUINO_PICO/mpconfigboard.h
rename to ports/stm32/boards/ESPRUINO_PICO/mpconfigboard.h
diff --git a/stmhal/boards/ESPRUINO_PICO/mpconfigboard.mk b/ports/stm32/boards/ESPRUINO_PICO/mpconfigboard.mk
similarity index 100%
rename from stmhal/boards/ESPRUINO_PICO/mpconfigboard.mk
rename to ports/stm32/boards/ESPRUINO_PICO/mpconfigboard.mk
diff --git a/stmhal/boards/ESPRUINO_PICO/pins.csv b/ports/stm32/boards/ESPRUINO_PICO/pins.csv
similarity index 100%
rename from stmhal/boards/ESPRUINO_PICO/pins.csv
rename to ports/stm32/boards/ESPRUINO_PICO/pins.csv
diff --git a/stmhal/boards/ESPRUINO_PICO/stm32f4xx_hal_conf.h b/ports/stm32/boards/ESPRUINO_PICO/stm32f4xx_hal_conf.h
similarity index 100%
rename from stmhal/boards/ESPRUINO_PICO/stm32f4xx_hal_conf.h
rename to ports/stm32/boards/ESPRUINO_PICO/stm32f4xx_hal_conf.h
diff --git a/stmhal/boards/HYDRABUS/mpconfigboard.h b/ports/stm32/boards/HYDRABUS/mpconfigboard.h
similarity index 100%
rename from stmhal/boards/HYDRABUS/mpconfigboard.h
rename to ports/stm32/boards/HYDRABUS/mpconfigboard.h
diff --git a/stmhal/boards/HYDRABUS/mpconfigboard.mk b/ports/stm32/boards/HYDRABUS/mpconfigboard.mk
similarity index 100%
rename from stmhal/boards/HYDRABUS/mpconfigboard.mk
rename to ports/stm32/boards/HYDRABUS/mpconfigboard.mk
diff --git a/stmhal/boards/HYDRABUS/pins.csv b/ports/stm32/boards/HYDRABUS/pins.csv
similarity index 100%
rename from stmhal/boards/HYDRABUS/pins.csv
rename to ports/stm32/boards/HYDRABUS/pins.csv
diff --git a/stmhal/boards/HYDRABUS/stm32f4xx_hal_conf.h b/ports/stm32/boards/HYDRABUS/stm32f4xx_hal_conf.h
similarity index 94%
rename from stmhal/boards/HYDRABUS/stm32f4xx_hal_conf.h
rename to ports/stm32/boards/HYDRABUS/stm32f4xx_hal_conf.h
index 8941e8290f..d3df51c101 100644
--- a/stmhal/boards/HYDRABUS/stm32f4xx_hal_conf.h
+++ b/ports/stm32/boards/HYDRABUS/stm32f4xx_hal_conf.h
@@ -1,411 +1,411 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_conf.h
-  * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    19-June-2014
-  * @brief   HAL configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_CONF_H
-#define __STM32F4xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-#define USE_USB_FS
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver 
-  */
-#define HAL_MODULE_ENABLED
-#define HAL_ADC_MODULE_ENABLED
-#define HAL_CAN_MODULE_ENABLED
-/* #define HAL_CRC_MODULE_ENABLED */
-/* #define HAL_CRYP_MODULE_ENABLED */
-#define HAL_DAC_MODULE_ENABLED
-/* #define HAL_DCMI_MODULE_ENABLED */
-#define HAL_DMA_MODULE_ENABLED
-/* #define HAL_DMA2D_MODULE_ENABLED */
-/* #define HAL_ETH_MODULE_ENABLED */
-#define HAL_FLASH_MODULE_ENABLED
-/* #define HAL_NAND_MODULE_ENABLED */
-/* #define HAL_NOR_MODULE_ENABLED */
-/* #define HAL_PCCARD_MODULE_ENABLED */
-/* #define HAL_SRAM_MODULE_ENABLED */
-/* #define HAL_SDRAM_MODULE_ENABLED */
-/* #define HAL_HASH_MODULE_ENABLED */
-#define HAL_GPIO_MODULE_ENABLED
-#define HAL_I2C_MODULE_ENABLED
-/* #define HAL_I2S_MODULE_ENABLED */
-/* #define HAL_IWDG_MODULE_ENABLED */
-/* #define HAL_LTDC_MODULE_ENABLED */
-#define HAL_PWR_MODULE_ENABLED
-#define HAL_RCC_MODULE_ENABLED
-#define HAL_RNG_MODULE_ENABLED
-#define HAL_RTC_MODULE_ENABLED
-/* #define HAL_SAI_MODULE_ENABLED */
-#define HAL_SD_MODULE_ENABLED
-#define HAL_SPI_MODULE_ENABLED
-#define HAL_TIM_MODULE_ENABLED
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED */
-/* #define HAL_IRDA_MODULE_ENABLED */
-/* #define HAL_SMARTCARD_MODULE_ENABLED */
-/* #define HAL_WWDG_MODULE_ENABLED */
-#define HAL_CORTEX_MODULE_ENABLED
-#define HAL_PCD_MODULE_ENABLED
-/* #define HAL_HCD_MODULE_ENABLED */
-
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  ((uint32_t)40000)    
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source 
-  *        frequency, this source is inserted directly through I2S_CKIN pad. 
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */     
-#define  VDD_VALUE                    ((uint32_t)3300) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            ((uint32_t)0x00) /*!< tick interrupt priority */
-#define  USE_RTOS                     0
-#define  PREFETCH_ENABLE              1
-#define  INSTRUCTION_CACHE_ENABLE     1
-#define  DATA_CACHE_ENABLE            1
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1 */
-
-/* ################## Ethernet peripheral configuration ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2
-#define MAC_ADDR1   0
-#define MAC_ADDR2   0
-#define MAC_ADDR3   0
-#define MAC_ADDR4   0
-#define MAC_ADDR5   0
-
-/* Definition of the Ethernet driver buffers size and count */   
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    ((uint32_t)4)       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    ((uint32_t)4)       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-
-/* DP83848 PHY Address*/ 
-#define DP83848_PHY_ADDRESS             0x01
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
-#define PHY_RESET_DELAY                 ((uint32_t)0x000000FF)
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
-
-#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
-#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
- 
-#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-  
-/* Section 4: Extended PHY Registers */
-
-#define PHY_SR                          ((uint16_t)0x10)    /*!< PHY status register Offset                      */
-#define PHY_MICR                        ((uint16_t)0x11)    /*!< MII Interrupt Control Register                  */
-#define PHY_MISR                        ((uint16_t)0x12)    /*!< MII Interrupt Status and Misc. Control Register */
- 
-#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
-#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
-
-#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
-#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
-
-#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
-#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file 
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32f4xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32f4xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-   
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32f4xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32f4xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32f4xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32f4xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f4xx_hal_cryp.h" 
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32f4xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32f4xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f4xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32f4xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
- 
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f4xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f4xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_PCCARD_MODULE_ENABLED
-  #include "stm32f4xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */ 
-  
-#ifdef HAL_SDRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */      
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f4xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f4xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f4xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f4xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f4xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f4xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f4xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f4xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f4xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f4xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f4xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f4xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f4xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f4xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f4xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f4xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f4xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-   
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_CONF_H */
- 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_conf.h
+  * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    19-June-2014
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CONF_H
+#define __STM32F4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+#define USE_USB_FS
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_CAN_MODULE_ENABLED
+/* #define HAL_CRC_MODULE_ENABLED */
+/* #define HAL_CRYP_MODULE_ENABLED */
+#define HAL_DAC_MODULE_ENABLED
+/* #define HAL_DCMI_MODULE_ENABLED */
+#define HAL_DMA_MODULE_ENABLED
+/* #define HAL_DMA2D_MODULE_ENABLED */
+/* #define HAL_ETH_MODULE_ENABLED */
+#define HAL_FLASH_MODULE_ENABLED
+/* #define HAL_NAND_MODULE_ENABLED */
+/* #define HAL_NOR_MODULE_ENABLED */
+/* #define HAL_PCCARD_MODULE_ENABLED */
+/* #define HAL_SRAM_MODULE_ENABLED */
+/* #define HAL_SDRAM_MODULE_ENABLED */
+/* #define HAL_HASH_MODULE_ENABLED */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+/* #define HAL_I2S_MODULE_ENABLED */
+/* #define HAL_IWDG_MODULE_ENABLED */
+/* #define HAL_LTDC_MODULE_ENABLED */
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+/* #define HAL_SAI_MODULE_ENABLED */
+#define HAL_SD_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+/* #define HAL_USART_MODULE_ENABLED */
+/* #define HAL_IRDA_MODULE_ENABLED */
+/* #define HAL_SMARTCARD_MODULE_ENABLED */
+/* #define HAL_WWDG_MODULE_ENABLED */
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+/* #define HAL_HCD_MODULE_ENABLED */
+
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE)
+ #define LSI_VALUE  ((uint32_t)40000)
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  */
+#if !defined  (LSE_VALUE)
+ #define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for I2S peripheral
+  *        This value is used by the I2S HAL module to compute the I2S clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
+  */
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */
+#define  VDD_VALUE                    ((uint32_t)3300) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            ((uint32_t)0x00) /*!< tick interrupt priority */
+#define  USE_RTOS                     0
+#define  PREFETCH_ENABLE              1
+#define  INSTRUCTION_CACHE_ENABLE     1
+#define  DATA_CACHE_ENABLE            1
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1 */
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0   2
+#define MAC_ADDR1   0
+#define MAC_ADDR2   0
+#define MAC_ADDR3   0
+#define MAC_ADDR4   0
+#define MAC_ADDR5   0
+
+/* Definition of the Ethernet driver buffers size and count */
+#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
+#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
+#define ETH_RXBUFNB                    ((uint32_t)4)       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
+#define ETH_TXBUFNB                    ((uint32_t)4)       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848 PHY Address*/
+#define DP83848_PHY_ADDRESS             0x01
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
+#define PHY_RESET_DELAY                 ((uint32_t)0x000000FF)
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
+
+#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
+#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
+#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
+
+#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
+#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
+#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
+#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
+#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
+#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
+#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
+
+#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
+#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
+#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
+
+/* Section 4: Extended PHY Registers */
+
+#define PHY_SR                          ((uint16_t)0x10)    /*!< PHY status register Offset                      */
+#define PHY_MICR                        ((uint16_t)0x11)    /*!< MII Interrupt Control Register                  */
+#define PHY_MISR                        ((uint16_t)0x12)    /*!< MII Interrupt Status and Misc. Control Register */
+
+#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
+#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
+#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
+
+#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
+#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
+
+#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
+#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32f4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32f4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32f4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32f4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32f4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+  #include "stm32f4xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32f4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32f4xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+  #include "stm32f4xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+  #include "stm32f4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+  #include "stm32f4xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+  #include "stm32f4xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32f4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+  #include "stm32f4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+  #include "stm32f4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+  #include "stm32f4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+  #include "stm32f4xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+  #include "stm32f4xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+ #include "stm32f4xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32f4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32f4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f4xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/boards/LIMIFROG/board_init.c b/ports/stm32/boards/LIMIFROG/board_init.c
similarity index 100%
rename from stmhal/boards/LIMIFROG/board_init.c
rename to ports/stm32/boards/LIMIFROG/board_init.c
diff --git a/stmhal/boards/LIMIFROG/mpconfigboard.h b/ports/stm32/boards/LIMIFROG/mpconfigboard.h
similarity index 100%
rename from stmhal/boards/LIMIFROG/mpconfigboard.h
rename to ports/stm32/boards/LIMIFROG/mpconfigboard.h
diff --git a/stmhal/boards/LIMIFROG/mpconfigboard.mk b/ports/stm32/boards/LIMIFROG/mpconfigboard.mk
similarity index 100%
rename from stmhal/boards/LIMIFROG/mpconfigboard.mk
rename to ports/stm32/boards/LIMIFROG/mpconfigboard.mk
diff --git a/stmhal/boards/LIMIFROG/pins.csv b/ports/stm32/boards/LIMIFROG/pins.csv
similarity index 100%
rename from stmhal/boards/LIMIFROG/pins.csv
rename to ports/stm32/boards/LIMIFROG/pins.csv
diff --git a/stmhal/boards/NUCLEO_L476RG/stm32l4xx_hal_conf.h b/ports/stm32/boards/LIMIFROG/stm32l4xx_hal_conf.h
old mode 100755
new mode 100644
similarity index 100%
rename from stmhal/boards/NUCLEO_L476RG/stm32l4xx_hal_conf.h
rename to ports/stm32/boards/LIMIFROG/stm32l4xx_hal_conf.h
diff --git a/stmhal/boards/NETDUINO_PLUS_2/board_init.c b/ports/stm32/boards/NETDUINO_PLUS_2/board_init.c
similarity index 100%
rename from stmhal/boards/NETDUINO_PLUS_2/board_init.c
rename to ports/stm32/boards/NETDUINO_PLUS_2/board_init.c
diff --git a/stmhal/boards/NETDUINO_PLUS_2/mpconfigboard.h b/ports/stm32/boards/NETDUINO_PLUS_2/mpconfigboard.h
similarity index 100%
rename from stmhal/boards/NETDUINO_PLUS_2/mpconfigboard.h
rename to ports/stm32/boards/NETDUINO_PLUS_2/mpconfigboard.h
diff --git a/stmhal/boards/NETDUINO_PLUS_2/mpconfigboard.mk b/ports/stm32/boards/NETDUINO_PLUS_2/mpconfigboard.mk
similarity index 100%
rename from stmhal/boards/NETDUINO_PLUS_2/mpconfigboard.mk
rename to ports/stm32/boards/NETDUINO_PLUS_2/mpconfigboard.mk
diff --git a/stmhal/boards/NETDUINO_PLUS_2/pins.csv b/ports/stm32/boards/NETDUINO_PLUS_2/pins.csv
similarity index 100%
rename from stmhal/boards/NETDUINO_PLUS_2/pins.csv
rename to ports/stm32/boards/NETDUINO_PLUS_2/pins.csv
diff --git a/stmhal/boards/NETDUINO_PLUS_2/stm32f4xx_hal_conf.h b/ports/stm32/boards/NETDUINO_PLUS_2/stm32f4xx_hal_conf.h
similarity index 94%
rename from stmhal/boards/NETDUINO_PLUS_2/stm32f4xx_hal_conf.h
rename to ports/stm32/boards/NETDUINO_PLUS_2/stm32f4xx_hal_conf.h
index 8b04c2845f..42c2c4e9be 100644
--- a/stmhal/boards/NETDUINO_PLUS_2/stm32f4xx_hal_conf.h
+++ b/ports/stm32/boards/NETDUINO_PLUS_2/stm32f4xx_hal_conf.h
@@ -1,411 +1,411 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_conf.h
-  * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    19-June-2014
-  * @brief   HAL configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_CONF_H
-#define __STM32F4xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-#define USE_USB_FS
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver 
-  */
-#define HAL_MODULE_ENABLED
-#define HAL_ADC_MODULE_ENABLED
-#define HAL_CAN_MODULE_ENABLED
-/* #define HAL_CRC_MODULE_ENABLED */
-/* #define HAL_CRYP_MODULE_ENABLED */
-#define HAL_DAC_MODULE_ENABLED
-/* #define HAL_DCMI_MODULE_ENABLED */
-#define HAL_DMA_MODULE_ENABLED
-/* #define HAL_DMA2D_MODULE_ENABLED */
-/* #define HAL_ETH_MODULE_ENABLED */
-#define HAL_FLASH_MODULE_ENABLED
-/* #define HAL_NAND_MODULE_ENABLED */
-/* #define HAL_NOR_MODULE_ENABLED */
-/* #define HAL_PCCARD_MODULE_ENABLED */
-/* #define HAL_SRAM_MODULE_ENABLED */
-/* #define HAL_SDRAM_MODULE_ENABLED */
-/* #define HAL_HASH_MODULE_ENABLED */
-#define HAL_GPIO_MODULE_ENABLED
-#define HAL_I2C_MODULE_ENABLED
-/* #define HAL_I2S_MODULE_ENABLED */
-/* #define HAL_IWDG_MODULE_ENABLED */
-/* #define HAL_LTDC_MODULE_ENABLED */
-#define HAL_PWR_MODULE_ENABLED
-#define HAL_RCC_MODULE_ENABLED
-#define HAL_RNG_MODULE_ENABLED
-#define HAL_RTC_MODULE_ENABLED
-/* #define HAL_SAI_MODULE_ENABLED */
-#define HAL_SD_MODULE_ENABLED
-#define HAL_SPI_MODULE_ENABLED
-#define HAL_TIM_MODULE_ENABLED
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED */
-/* #define HAL_IRDA_MODULE_ENABLED */
-/* #define HAL_SMARTCARD_MODULE_ENABLED */
-/* #define HAL_WWDG_MODULE_ENABLED */
-#define HAL_CORTEX_MODULE_ENABLED
-#define HAL_PCD_MODULE_ENABLED
-/* #define HAL_HCD_MODULE_ENABLED */
-
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  ((uint32_t)40000)    
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source 
-  *        frequency, this source is inserted directly through I2S_CKIN pad. 
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */     
-#define  VDD_VALUE                    ((uint32_t)3300) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            ((uint32_t)0x00) /*!< tick interrupt priority */
-#define  USE_RTOS                     0
-#define  PREFETCH_ENABLE              1
-#define  INSTRUCTION_CACHE_ENABLE     1
-#define  DATA_CACHE_ENABLE            1
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1 */
-
-/* ################## Ethernet peripheral configuration ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2
-#define MAC_ADDR1   0
-#define MAC_ADDR2   0
-#define MAC_ADDR3   0
-#define MAC_ADDR4   0
-#define MAC_ADDR5   0
-
-/* Definition of the Ethernet driver buffers size and count */   
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    ((uint32_t)4)       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    ((uint32_t)4)       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-
-/* DP83848 PHY Address*/ 
-#define DP83848_PHY_ADDRESS             0x01
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
-#define PHY_RESET_DELAY                 ((uint32_t)0x000000FF)
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
-
-#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
-#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
- 
-#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-  
-/* Section 4: Extended PHY Registers */
-
-#define PHY_SR                          ((uint16_t)0x10)    /*!< PHY status register Offset                      */
-#define PHY_MICR                        ((uint16_t)0x11)    /*!< MII Interrupt Control Register                  */
-#define PHY_MISR                        ((uint16_t)0x12)    /*!< MII Interrupt Status and Misc. Control Register */
- 
-#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
-#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
-
-#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
-#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
-
-#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
-#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file 
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32f4xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32f4xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-   
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32f4xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32f4xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32f4xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32f4xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f4xx_hal_cryp.h" 
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32f4xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32f4xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f4xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32f4xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
- 
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f4xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f4xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_PCCARD_MODULE_ENABLED
-  #include "stm32f4xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */ 
-  
-#ifdef HAL_SDRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */      
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f4xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f4xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f4xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f4xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f4xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f4xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f4xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f4xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f4xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f4xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f4xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f4xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f4xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f4xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f4xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f4xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f4xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-   
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_CONF_H */
- 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_conf.h
+  * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    19-June-2014
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CONF_H
+#define __STM32F4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+#define USE_USB_FS
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_CAN_MODULE_ENABLED
+/* #define HAL_CRC_MODULE_ENABLED */
+/* #define HAL_CRYP_MODULE_ENABLED */
+#define HAL_DAC_MODULE_ENABLED
+/* #define HAL_DCMI_MODULE_ENABLED */
+#define HAL_DMA_MODULE_ENABLED
+/* #define HAL_DMA2D_MODULE_ENABLED */
+/* #define HAL_ETH_MODULE_ENABLED */
+#define HAL_FLASH_MODULE_ENABLED
+/* #define HAL_NAND_MODULE_ENABLED */
+/* #define HAL_NOR_MODULE_ENABLED */
+/* #define HAL_PCCARD_MODULE_ENABLED */
+/* #define HAL_SRAM_MODULE_ENABLED */
+/* #define HAL_SDRAM_MODULE_ENABLED */
+/* #define HAL_HASH_MODULE_ENABLED */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+/* #define HAL_I2S_MODULE_ENABLED */
+/* #define HAL_IWDG_MODULE_ENABLED */
+/* #define HAL_LTDC_MODULE_ENABLED */
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+/* #define HAL_SAI_MODULE_ENABLED */
+#define HAL_SD_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+/* #define HAL_USART_MODULE_ENABLED */
+/* #define HAL_IRDA_MODULE_ENABLED */
+/* #define HAL_SMARTCARD_MODULE_ENABLED */
+/* #define HAL_WWDG_MODULE_ENABLED */
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+/* #define HAL_HCD_MODULE_ENABLED */
+
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE)
+ #define LSI_VALUE  ((uint32_t)40000)
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  */
+#if !defined  (LSE_VALUE)
+ #define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for I2S peripheral
+  *        This value is used by the I2S HAL module to compute the I2S clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
+  */
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */
+#define  VDD_VALUE                    ((uint32_t)3300) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            ((uint32_t)0x00) /*!< tick interrupt priority */
+#define  USE_RTOS                     0
+#define  PREFETCH_ENABLE              1
+#define  INSTRUCTION_CACHE_ENABLE     1
+#define  DATA_CACHE_ENABLE            1
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1 */
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0   2
+#define MAC_ADDR1   0
+#define MAC_ADDR2   0
+#define MAC_ADDR3   0
+#define MAC_ADDR4   0
+#define MAC_ADDR5   0
+
+/* Definition of the Ethernet driver buffers size and count */
+#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
+#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
+#define ETH_RXBUFNB                    ((uint32_t)4)       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
+#define ETH_TXBUFNB                    ((uint32_t)4)       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848 PHY Address*/
+#define DP83848_PHY_ADDRESS             0x01
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
+#define PHY_RESET_DELAY                 ((uint32_t)0x000000FF)
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
+
+#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
+#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
+#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
+
+#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
+#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
+#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
+#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
+#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
+#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
+#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
+
+#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
+#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
+#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
+
+/* Section 4: Extended PHY Registers */
+
+#define PHY_SR                          ((uint16_t)0x10)    /*!< PHY status register Offset                      */
+#define PHY_MICR                        ((uint16_t)0x11)    /*!< MII Interrupt Control Register                  */
+#define PHY_MISR                        ((uint16_t)0x12)    /*!< MII Interrupt Status and Misc. Control Register */
+
+#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
+#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
+#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
+
+#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
+#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
+
+#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
+#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32f4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32f4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32f4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32f4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32f4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+  #include "stm32f4xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32f4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32f4xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+  #include "stm32f4xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+  #include "stm32f4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+  #include "stm32f4xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+  #include "stm32f4xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32f4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+  #include "stm32f4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+  #include "stm32f4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+  #include "stm32f4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+  #include "stm32f4xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+  #include "stm32f4xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+ #include "stm32f4xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32f4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32f4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f4xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/boards/NUCLEO_F401RE/mpconfigboard.h b/ports/stm32/boards/NUCLEO_F401RE/mpconfigboard.h
similarity index 94%
rename from stmhal/boards/NUCLEO_F401RE/mpconfigboard.h
rename to ports/stm32/boards/NUCLEO_F401RE/mpconfigboard.h
index c12d52756c..a843d3c35f 100644
--- a/stmhal/boards/NUCLEO_F401RE/mpconfigboard.h
+++ b/ports/stm32/boards/NUCLEO_F401RE/mpconfigboard.h
@@ -22,8 +22,8 @@
 #define MICROPY_HW_UART_REPL_BAUD   115200
 
 // I2C busses
-#define MICROPY_HW_I2C1_SCL (pin_B6)        // Arduino D10, pin 17 on CN10
-#define MICROPY_HW_I2C1_SDA (pin_B7)        //              pin 21 on CN7
+#define MICROPY_HW_I2C1_SCL (pin_B8)        // Arduino D15, pin 3 on CN10
+#define MICROPY_HW_I2C1_SDA (pin_B9)        //         D14, pin 5 on CN10
 #define MICROPY_HW_I2C2_SCL (pin_B10)       // Arduino D6,  pin 25 on CN10
 #define MICROPY_HW_I2C2_SDA (pin_B3)        // Arduino D3,  pin 31 on CN10
 #define MICROPY_HW_I2C3_SCL (pin_A8)        // Arduino D7,  pin 23 on CN10
diff --git a/stmhal/boards/NUCLEO_F401RE/mpconfigboard.mk b/ports/stm32/boards/NUCLEO_F401RE/mpconfigboard.mk
similarity index 100%
rename from stmhal/boards/NUCLEO_F401RE/mpconfigboard.mk
rename to ports/stm32/boards/NUCLEO_F401RE/mpconfigboard.mk
diff --git a/stmhal/boards/NUCLEO_F401RE/pins.csv b/ports/stm32/boards/NUCLEO_F401RE/pins.csv
similarity index 100%
rename from stmhal/boards/NUCLEO_F401RE/pins.csv
rename to ports/stm32/boards/NUCLEO_F401RE/pins.csv
diff --git a/stmhal/boards/PYBV3/stm32f4xx_hal_conf.h b/ports/stm32/boards/NUCLEO_F401RE/stm32f4xx_hal_conf.h
similarity index 94%
rename from stmhal/boards/PYBV3/stm32f4xx_hal_conf.h
rename to ports/stm32/boards/NUCLEO_F401RE/stm32f4xx_hal_conf.h
index 8941e8290f..f4db4cb631 100644
--- a/stmhal/boards/PYBV3/stm32f4xx_hal_conf.h
+++ b/ports/stm32/boards/NUCLEO_F401RE/stm32f4xx_hal_conf.h
@@ -1,411 +1,413 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_conf.h
-  * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    19-June-2014
-  * @brief   HAL configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_CONF_H
-#define __STM32F4xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-#define USE_USB_FS
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver 
-  */
-#define HAL_MODULE_ENABLED
-#define HAL_ADC_MODULE_ENABLED
-#define HAL_CAN_MODULE_ENABLED
-/* #define HAL_CRC_MODULE_ENABLED */
-/* #define HAL_CRYP_MODULE_ENABLED */
-#define HAL_DAC_MODULE_ENABLED
-/* #define HAL_DCMI_MODULE_ENABLED */
-#define HAL_DMA_MODULE_ENABLED
-/* #define HAL_DMA2D_MODULE_ENABLED */
-/* #define HAL_ETH_MODULE_ENABLED */
-#define HAL_FLASH_MODULE_ENABLED
-/* #define HAL_NAND_MODULE_ENABLED */
-/* #define HAL_NOR_MODULE_ENABLED */
-/* #define HAL_PCCARD_MODULE_ENABLED */
-/* #define HAL_SRAM_MODULE_ENABLED */
-/* #define HAL_SDRAM_MODULE_ENABLED */
-/* #define HAL_HASH_MODULE_ENABLED */
-#define HAL_GPIO_MODULE_ENABLED
-#define HAL_I2C_MODULE_ENABLED
-/* #define HAL_I2S_MODULE_ENABLED */
-/* #define HAL_IWDG_MODULE_ENABLED */
-/* #define HAL_LTDC_MODULE_ENABLED */
-#define HAL_PWR_MODULE_ENABLED
-#define HAL_RCC_MODULE_ENABLED
-#define HAL_RNG_MODULE_ENABLED
-#define HAL_RTC_MODULE_ENABLED
-/* #define HAL_SAI_MODULE_ENABLED */
-#define HAL_SD_MODULE_ENABLED
-#define HAL_SPI_MODULE_ENABLED
-#define HAL_TIM_MODULE_ENABLED
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED */
-/* #define HAL_IRDA_MODULE_ENABLED */
-/* #define HAL_SMARTCARD_MODULE_ENABLED */
-/* #define HAL_WWDG_MODULE_ENABLED */
-#define HAL_CORTEX_MODULE_ENABLED
-#define HAL_PCD_MODULE_ENABLED
-/* #define HAL_HCD_MODULE_ENABLED */
-
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  ((uint32_t)40000)    
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source 
-  *        frequency, this source is inserted directly through I2S_CKIN pad. 
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */     
-#define  VDD_VALUE                    ((uint32_t)3300) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            ((uint32_t)0x00) /*!< tick interrupt priority */
-#define  USE_RTOS                     0
-#define  PREFETCH_ENABLE              1
-#define  INSTRUCTION_CACHE_ENABLE     1
-#define  DATA_CACHE_ENABLE            1
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1 */
-
-/* ################## Ethernet peripheral configuration ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2
-#define MAC_ADDR1   0
-#define MAC_ADDR2   0
-#define MAC_ADDR3   0
-#define MAC_ADDR4   0
-#define MAC_ADDR5   0
-
-/* Definition of the Ethernet driver buffers size and count */   
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    ((uint32_t)4)       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    ((uint32_t)4)       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-
-/* DP83848 PHY Address*/ 
-#define DP83848_PHY_ADDRESS             0x01
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
-#define PHY_RESET_DELAY                 ((uint32_t)0x000000FF)
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
-
-#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
-#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
- 
-#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-  
-/* Section 4: Extended PHY Registers */
-
-#define PHY_SR                          ((uint16_t)0x10)    /*!< PHY status register Offset                      */
-#define PHY_MICR                        ((uint16_t)0x11)    /*!< MII Interrupt Control Register                  */
-#define PHY_MISR                        ((uint16_t)0x12)    /*!< MII Interrupt Status and Misc. Control Register */
- 
-#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
-#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
-
-#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
-#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
-
-#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
-#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file 
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32f4xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32f4xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-   
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32f4xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32f4xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32f4xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32f4xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f4xx_hal_cryp.h" 
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32f4xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32f4xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f4xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32f4xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
- 
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f4xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f4xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_PCCARD_MODULE_ENABLED
-  #include "stm32f4xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */ 
-  
-#ifdef HAL_SDRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */      
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f4xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f4xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f4xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f4xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f4xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f4xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f4xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f4xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f4xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f4xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f4xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f4xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f4xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f4xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f4xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f4xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f4xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-   
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_CONF_H */
- 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_conf.h
+  * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    19-June-2014
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CONF_H
+#define __STM32F4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+// This board doesn't really have USB, but the stm32 codebase doesn't build
+// without some USB defined, so we leave this on for now.
+#define USE_USB_FS
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_CAN_MODULE_ENABLED
+/* #define HAL_CRC_MODULE_ENABLED */
+/* #define HAL_CRYP_MODULE_ENABLED */
+#define HAL_DAC_MODULE_ENABLED
+/* #define HAL_DCMI_MODULE_ENABLED */
+#define HAL_DMA_MODULE_ENABLED
+/* #define HAL_DMA2D_MODULE_ENABLED */
+/* #define HAL_ETH_MODULE_ENABLED */
+#define HAL_FLASH_MODULE_ENABLED
+/* #define HAL_NAND_MODULE_ENABLED */
+/* #define HAL_NOR_MODULE_ENABLED */
+/* #define HAL_PCCARD_MODULE_ENABLED */
+/* #define HAL_SRAM_MODULE_ENABLED */
+/* #define HAL_SDRAM_MODULE_ENABLED */
+/* #define HAL_HASH_MODULE_ENABLED */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+/* #define HAL_I2S_MODULE_ENABLED */
+/* #define HAL_IWDG_MODULE_ENABLED */
+/* #define HAL_LTDC_MODULE_ENABLED */
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+/* #define HAL_SAI_MODULE_ENABLED */
+#define HAL_SD_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+/* #define HAL_USART_MODULE_ENABLED */
+/* #define HAL_IRDA_MODULE_ENABLED */
+/* #define HAL_SMARTCARD_MODULE_ENABLED */
+/* #define HAL_WWDG_MODULE_ENABLED */
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+/* #define HAL_HCD_MODULE_ENABLED */
+
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE)
+ #define LSI_VALUE  ((uint32_t)40000)
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  */
+#if !defined  (LSE_VALUE)
+ #define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for I2S peripheral
+  *        This value is used by the I2S HAL module to compute the I2S clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
+  */
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */
+#define  VDD_VALUE                    ((uint32_t)3300) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            ((uint32_t)0x00) /*!< tick interrupt priority */
+#define  USE_RTOS                     0
+#define  PREFETCH_ENABLE              1
+#define  INSTRUCTION_CACHE_ENABLE     1
+#define  DATA_CACHE_ENABLE            1
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1 */
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0   2
+#define MAC_ADDR1   0
+#define MAC_ADDR2   0
+#define MAC_ADDR3   0
+#define MAC_ADDR4   0
+#define MAC_ADDR5   0
+
+/* Definition of the Ethernet driver buffers size and count */
+#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
+#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
+#define ETH_RXBUFNB                    ((uint32_t)4)       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
+#define ETH_TXBUFNB                    ((uint32_t)4)       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848 PHY Address*/
+#define DP83848_PHY_ADDRESS             0x01
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
+#define PHY_RESET_DELAY                 ((uint32_t)0x000000FF)
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
+
+#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
+#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
+#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
+
+#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
+#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
+#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
+#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
+#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
+#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
+#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
+
+#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
+#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
+#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
+
+/* Section 4: Extended PHY Registers */
+
+#define PHY_SR                          ((uint16_t)0x10)    /*!< PHY status register Offset                      */
+#define PHY_MICR                        ((uint16_t)0x11)    /*!< MII Interrupt Control Register                  */
+#define PHY_MISR                        ((uint16_t)0x12)    /*!< MII Interrupt Status and Misc. Control Register */
+
+#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
+#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
+#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
+
+#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
+#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
+
+#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
+#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32f4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32f4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32f4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32f4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32f4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+  #include "stm32f4xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32f4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32f4xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+  #include "stm32f4xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+  #include "stm32f4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+  #include "stm32f4xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+  #include "stm32f4xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32f4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+  #include "stm32f4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+  #include "stm32f4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+  #include "stm32f4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+  #include "stm32f4xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+  #include "stm32f4xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+ #include "stm32f4xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32f4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32f4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f4xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/boards/NUCLEO_F411RE/mpconfigboard.h b/ports/stm32/boards/NUCLEO_F411RE/mpconfigboard.h
similarity index 95%
rename from stmhal/boards/NUCLEO_F411RE/mpconfigboard.h
rename to ports/stm32/boards/NUCLEO_F411RE/mpconfigboard.h
index 1f7f0a23b7..26b1e0b619 100644
--- a/stmhal/boards/NUCLEO_F411RE/mpconfigboard.h
+++ b/ports/stm32/boards/NUCLEO_F411RE/mpconfigboard.h
@@ -22,8 +22,8 @@
 #define MICROPY_HW_UART_REPL_BAUD   115200
 
 // I2C busses
-#define MICROPY_HW_I2C1_SCL (pin_B6)        // Arduino D10, pin 17 on CN10
-#define MICROPY_HW_I2C1_SDA (pin_B7)        //              pin 21 on CN7
+#define MICROPY_HW_I2C1_SCL (pin_B8)        // Arduino D15, pin 3 on CN10
+#define MICROPY_HW_I2C1_SDA (pin_B9)        //         D14, pin 5 on CN10
 #define MICROPY_HW_I2C2_SCL (pin_B10)       // Arduino D6,  pin 25 on CN10
 #define MICROPY_HW_I2C2_SDA (pin_B3)        // Arduino D3,  pin 31 on CN10
 #define MICROPY_HW_I2C3_SCL (pin_A8)        // Arduino D7,  pin 23 on CN10
diff --git a/stmhal/boards/NUCLEO_F411RE/mpconfigboard.mk b/ports/stm32/boards/NUCLEO_F411RE/mpconfigboard.mk
similarity index 100%
rename from stmhal/boards/NUCLEO_F411RE/mpconfigboard.mk
rename to ports/stm32/boards/NUCLEO_F411RE/mpconfigboard.mk
diff --git a/stmhal/boards/NUCLEO_F411RE/pins.csv b/ports/stm32/boards/NUCLEO_F411RE/pins.csv
similarity index 100%
rename from stmhal/boards/NUCLEO_F411RE/pins.csv
rename to ports/stm32/boards/NUCLEO_F411RE/pins.csv
diff --git a/stmhal/boards/NUCLEO_F411RE/stm32f4xx_hal_conf.h b/ports/stm32/boards/NUCLEO_F411RE/stm32f4xx_hal_conf.h
similarity index 99%
rename from stmhal/boards/NUCLEO_F411RE/stm32f4xx_hal_conf.h
rename to ports/stm32/boards/NUCLEO_F411RE/stm32f4xx_hal_conf.h
index e16fba155c..0c424888f8 100644
--- a/stmhal/boards/NUCLEO_F411RE/stm32f4xx_hal_conf.h
+++ b/ports/stm32/boards/NUCLEO_F411RE/stm32f4xx_hal_conf.h
@@ -46,7 +46,7 @@
 /* Exported types ------------------------------------------------------------*/
 /* Exported constants --------------------------------------------------------*/
 
-// This board doesn't really have USB, but the stmhal codebase doesn't build
+// This board doesn't really have USB, but the stm32 codebase doesn't build
 // without some USB defined, so we leave this on for now.
 #define USE_USB_FS
 
diff --git a/stmhal/boards/NUCLEO_F429ZI/mpconfigboard.h b/ports/stm32/boards/NUCLEO_F429ZI/mpconfigboard.h
similarity index 100%
rename from stmhal/boards/NUCLEO_F429ZI/mpconfigboard.h
rename to ports/stm32/boards/NUCLEO_F429ZI/mpconfigboard.h
diff --git a/stmhal/boards/NUCLEO_F429ZI/mpconfigboard.mk b/ports/stm32/boards/NUCLEO_F429ZI/mpconfigboard.mk
similarity index 100%
rename from stmhal/boards/NUCLEO_F429ZI/mpconfigboard.mk
rename to ports/stm32/boards/NUCLEO_F429ZI/mpconfigboard.mk
diff --git a/stmhal/boards/NUCLEO_F429ZI/pins.csv b/ports/stm32/boards/NUCLEO_F429ZI/pins.csv
similarity index 100%
rename from stmhal/boards/NUCLEO_F429ZI/pins.csv
rename to ports/stm32/boards/NUCLEO_F429ZI/pins.csv
diff --git a/stmhal/boards/NUCLEO_F429ZI/stm32f4xx_hal_conf.h b/ports/stm32/boards/NUCLEO_F429ZI/stm32f4xx_hal_conf.h
similarity index 100%
rename from stmhal/boards/NUCLEO_F429ZI/stm32f4xx_hal_conf.h
rename to ports/stm32/boards/NUCLEO_F429ZI/stm32f4xx_hal_conf.h
diff --git a/stmhal/boards/NUCLEO_F446RE/mpconfigboard.h b/ports/stm32/boards/NUCLEO_F446RE/mpconfigboard.h
similarity index 100%
rename from stmhal/boards/NUCLEO_F446RE/mpconfigboard.h
rename to ports/stm32/boards/NUCLEO_F446RE/mpconfigboard.h
diff --git a/stmhal/boards/NUCLEO_F446RE/mpconfigboard.mk b/ports/stm32/boards/NUCLEO_F446RE/mpconfigboard.mk
similarity index 100%
rename from stmhal/boards/NUCLEO_F446RE/mpconfigboard.mk
rename to ports/stm32/boards/NUCLEO_F446RE/mpconfigboard.mk
diff --git a/stmhal/boards/NUCLEO_F446RE/pins.csv b/ports/stm32/boards/NUCLEO_F446RE/pins.csv
similarity index 100%
rename from stmhal/boards/NUCLEO_F446RE/pins.csv
rename to ports/stm32/boards/NUCLEO_F446RE/pins.csv
diff --git a/stmhal/boards/NUCLEO_F446RE/stm32f4xx_hal_conf.h b/ports/stm32/boards/NUCLEO_F446RE/stm32f4xx_hal_conf.h
similarity index 99%
rename from stmhal/boards/NUCLEO_F446RE/stm32f4xx_hal_conf.h
rename to ports/stm32/boards/NUCLEO_F446RE/stm32f4xx_hal_conf.h
index 3d0ce926b5..487ca009f2 100644
--- a/stmhal/boards/NUCLEO_F446RE/stm32f4xx_hal_conf.h
+++ b/ports/stm32/boards/NUCLEO_F446RE/stm32f4xx_hal_conf.h
@@ -46,7 +46,7 @@
 /* Exported types ------------------------------------------------------------*/
 /* Exported constants --------------------------------------------------------*/
 
-// This board doesn't really have USB, but the stmhal codebase doesn't build
+// This board doesn't really have USB, but the stm32 codebase doesn't build
 // without some USB defined, so we leave this on for now.
 #define USE_USB_FS
 
diff --git a/stmhal/boards/NUCLEO_F767ZI/mpconfigboard.h b/ports/stm32/boards/NUCLEO_F767ZI/mpconfigboard.h
similarity index 100%
rename from stmhal/boards/NUCLEO_F767ZI/mpconfigboard.h
rename to ports/stm32/boards/NUCLEO_F767ZI/mpconfigboard.h
diff --git a/stmhal/boards/NUCLEO_F767ZI/mpconfigboard.mk b/ports/stm32/boards/NUCLEO_F767ZI/mpconfigboard.mk
similarity index 100%
rename from stmhal/boards/NUCLEO_F767ZI/mpconfigboard.mk
rename to ports/stm32/boards/NUCLEO_F767ZI/mpconfigboard.mk
diff --git a/stmhal/boards/NUCLEO_F767ZI/pins.csv b/ports/stm32/boards/NUCLEO_F767ZI/pins.csv
similarity index 100%
rename from stmhal/boards/NUCLEO_F767ZI/pins.csv
rename to ports/stm32/boards/NUCLEO_F767ZI/pins.csv
diff --git a/stmhal/boards/NUCLEO_F767ZI/stm32f7xx_hal_conf.h b/ports/stm32/boards/NUCLEO_F767ZI/stm32f7xx_hal_conf.h
similarity index 100%
rename from stmhal/boards/NUCLEO_F767ZI/stm32f7xx_hal_conf.h
rename to ports/stm32/boards/NUCLEO_F767ZI/stm32f7xx_hal_conf.h
diff --git a/stmhal/boards/NUCLEO_L476RG/mpconfigboard.h b/ports/stm32/boards/NUCLEO_L476RG/mpconfigboard.h
similarity index 100%
rename from stmhal/boards/NUCLEO_L476RG/mpconfigboard.h
rename to ports/stm32/boards/NUCLEO_L476RG/mpconfigboard.h
diff --git a/stmhal/boards/NUCLEO_L476RG/mpconfigboard.mk b/ports/stm32/boards/NUCLEO_L476RG/mpconfigboard.mk
similarity index 100%
rename from stmhal/boards/NUCLEO_L476RG/mpconfigboard.mk
rename to ports/stm32/boards/NUCLEO_L476RG/mpconfigboard.mk
diff --git a/stmhal/boards/NUCLEO_L476RG/pins.csv b/ports/stm32/boards/NUCLEO_L476RG/pins.csv
similarity index 100%
rename from stmhal/boards/NUCLEO_L476RG/pins.csv
rename to ports/stm32/boards/NUCLEO_L476RG/pins.csv
diff --git a/stmhal/boards/STM32L476DISC/stm32l4xx_hal_conf.h b/ports/stm32/boards/NUCLEO_L476RG/stm32l4xx_hal_conf.h
old mode 100644
new mode 100755
similarity index 100%
rename from stmhal/boards/STM32L476DISC/stm32l4xx_hal_conf.h
rename to ports/stm32/boards/NUCLEO_L476RG/stm32l4xx_hal_conf.h
diff --git a/stmhal/boards/OLIMEX_E407/mpconfigboard.h b/ports/stm32/boards/OLIMEX_E407/mpconfigboard.h
similarity index 100%
rename from stmhal/boards/OLIMEX_E407/mpconfigboard.h
rename to ports/stm32/boards/OLIMEX_E407/mpconfigboard.h
diff --git a/stmhal/boards/OLIMEX_E407/mpconfigboard.mk b/ports/stm32/boards/OLIMEX_E407/mpconfigboard.mk
similarity index 100%
rename from stmhal/boards/OLIMEX_E407/mpconfigboard.mk
rename to ports/stm32/boards/OLIMEX_E407/mpconfigboard.mk
diff --git a/stmhal/boards/OLIMEX_E407/pins.csv b/ports/stm32/boards/OLIMEX_E407/pins.csv
similarity index 100%
rename from stmhal/boards/OLIMEX_E407/pins.csv
rename to ports/stm32/boards/OLIMEX_E407/pins.csv
diff --git a/stmhal/boards/OLIMEX_E407/stm32f4xx_hal_conf.h b/ports/stm32/boards/OLIMEX_E407/stm32f4xx_hal_conf.h
similarity index 100%
rename from stmhal/boards/OLIMEX_E407/stm32f4xx_hal_conf.h
rename to ports/stm32/boards/OLIMEX_E407/stm32f4xx_hal_conf.h
diff --git a/stmhal/boards/PYBLITEV10/mpconfigboard.h b/ports/stm32/boards/PYBLITEV10/mpconfigboard.h
similarity index 100%
rename from stmhal/boards/PYBLITEV10/mpconfigboard.h
rename to ports/stm32/boards/PYBLITEV10/mpconfigboard.h
diff --git a/stmhal/boards/PYBLITEV10/mpconfigboard.mk b/ports/stm32/boards/PYBLITEV10/mpconfigboard.mk
similarity index 100%
rename from stmhal/boards/PYBLITEV10/mpconfigboard.mk
rename to ports/stm32/boards/PYBLITEV10/mpconfigboard.mk
diff --git a/stmhal/boards/PYBLITEV10/pins.csv b/ports/stm32/boards/PYBLITEV10/pins.csv
similarity index 100%
rename from stmhal/boards/PYBLITEV10/pins.csv
rename to ports/stm32/boards/PYBLITEV10/pins.csv
diff --git a/stmhal/boards/PYBLITEV10/stm32f4xx_hal_conf.h b/ports/stm32/boards/PYBLITEV10/stm32f4xx_hal_conf.h
similarity index 100%
rename from stmhal/boards/PYBLITEV10/stm32f4xx_hal_conf.h
rename to ports/stm32/boards/PYBLITEV10/stm32f4xx_hal_conf.h
diff --git a/stmhal/boards/PYBV10/mpconfigboard.h b/ports/stm32/boards/PYBV10/mpconfigboard.h
similarity index 100%
rename from stmhal/boards/PYBV10/mpconfigboard.h
rename to ports/stm32/boards/PYBV10/mpconfigboard.h
diff --git a/stmhal/boards/PYBV10/mpconfigboard.mk b/ports/stm32/boards/PYBV10/mpconfigboard.mk
similarity index 100%
rename from stmhal/boards/PYBV10/mpconfigboard.mk
rename to ports/stm32/boards/PYBV10/mpconfigboard.mk
diff --git a/stmhal/boards/PYBV10/pins.csv b/ports/stm32/boards/PYBV10/pins.csv
similarity index 100%
rename from stmhal/boards/PYBV10/pins.csv
rename to ports/stm32/boards/PYBV10/pins.csv
diff --git a/stmhal/boards/PYBV10/stm32f4xx_hal_conf.h b/ports/stm32/boards/PYBV10/stm32f4xx_hal_conf.h
similarity index 94%
rename from stmhal/boards/PYBV10/stm32f4xx_hal_conf.h
rename to ports/stm32/boards/PYBV10/stm32f4xx_hal_conf.h
index 52518e196b..3d92522644 100644
--- a/stmhal/boards/PYBV10/stm32f4xx_hal_conf.h
+++ b/ports/stm32/boards/PYBV10/stm32f4xx_hal_conf.h
@@ -1,411 +1,411 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_conf.h
-  * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    19-June-2014
-  * @brief   HAL configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_CONF_H
-#define __STM32F4xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-#define USE_USB_FS
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver 
-  */
-#define HAL_MODULE_ENABLED
-#define HAL_ADC_MODULE_ENABLED
-#define HAL_CAN_MODULE_ENABLED
-/* #define HAL_CRC_MODULE_ENABLED */
-/* #define HAL_CRYP_MODULE_ENABLED */
-#define HAL_DAC_MODULE_ENABLED
-/* #define HAL_DCMI_MODULE_ENABLED */
-#define HAL_DMA_MODULE_ENABLED
-/* #define HAL_DMA2D_MODULE_ENABLED */
-/* #define HAL_ETH_MODULE_ENABLED */
-#define HAL_FLASH_MODULE_ENABLED
-/* #define HAL_NAND_MODULE_ENABLED */
-/* #define HAL_NOR_MODULE_ENABLED */
-/* #define HAL_PCCARD_MODULE_ENABLED */
-/* #define HAL_SRAM_MODULE_ENABLED */
-/* #define HAL_SDRAM_MODULE_ENABLED */
-/* #define HAL_HASH_MODULE_ENABLED */
-#define HAL_GPIO_MODULE_ENABLED
-#define HAL_I2C_MODULE_ENABLED
-#define HAL_I2S_MODULE_ENABLED
-/* #define HAL_IWDG_MODULE_ENABLED */
-/* #define HAL_LTDC_MODULE_ENABLED */
-#define HAL_PWR_MODULE_ENABLED
-#define HAL_RCC_MODULE_ENABLED
-#define HAL_RNG_MODULE_ENABLED
-#define HAL_RTC_MODULE_ENABLED
-/* #define HAL_SAI_MODULE_ENABLED */
-#define HAL_SD_MODULE_ENABLED
-#define HAL_SPI_MODULE_ENABLED
-#define HAL_TIM_MODULE_ENABLED
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED */
-/* #define HAL_IRDA_MODULE_ENABLED */
-/* #define HAL_SMARTCARD_MODULE_ENABLED */
-/* #define HAL_WWDG_MODULE_ENABLED */
-#define HAL_CORTEX_MODULE_ENABLED
-#define HAL_PCD_MODULE_ENABLED
-/* #define HAL_HCD_MODULE_ENABLED */
-
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  ((uint32_t)40000)    
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source 
-  *        frequency, this source is inserted directly through I2S_CKIN pad. 
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */     
-#define  VDD_VALUE                    ((uint32_t)3300) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            ((uint32_t)0x00) /*!< tick interrupt priority */
-#define  USE_RTOS                     0
-#define  PREFETCH_ENABLE              1
-#define  INSTRUCTION_CACHE_ENABLE     1
-#define  DATA_CACHE_ENABLE            1
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1 */
-
-/* ################## Ethernet peripheral configuration ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2
-#define MAC_ADDR1   0
-#define MAC_ADDR2   0
-#define MAC_ADDR3   0
-#define MAC_ADDR4   0
-#define MAC_ADDR5   0
-
-/* Definition of the Ethernet driver buffers size and count */   
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    ((uint32_t)4)       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    ((uint32_t)4)       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-
-/* DP83848 PHY Address*/ 
-#define DP83848_PHY_ADDRESS             0x01
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
-#define PHY_RESET_DELAY                 ((uint32_t)0x000000FF)
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
-
-#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
-#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
- 
-#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-  
-/* Section 4: Extended PHY Registers */
-
-#define PHY_SR                          ((uint16_t)0x10)    /*!< PHY status register Offset                      */
-#define PHY_MICR                        ((uint16_t)0x11)    /*!< MII Interrupt Control Register                  */
-#define PHY_MISR                        ((uint16_t)0x12)    /*!< MII Interrupt Status and Misc. Control Register */
- 
-#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
-#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
-
-#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
-#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
-
-#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
-#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file 
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32f4xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32f4xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-   
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32f4xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32f4xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32f4xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32f4xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f4xx_hal_cryp.h" 
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32f4xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32f4xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f4xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32f4xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
- 
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f4xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f4xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_PCCARD_MODULE_ENABLED
-  #include "stm32f4xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */ 
-  
-#ifdef HAL_SDRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */      
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f4xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f4xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f4xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f4xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f4xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f4xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f4xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f4xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f4xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f4xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f4xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f4xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f4xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f4xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f4xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f4xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f4xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-   
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_CONF_H */
- 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_conf.h
+  * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    19-June-2014
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CONF_H
+#define __STM32F4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+#define USE_USB_FS
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_CAN_MODULE_ENABLED
+/* #define HAL_CRC_MODULE_ENABLED */
+/* #define HAL_CRYP_MODULE_ENABLED */
+#define HAL_DAC_MODULE_ENABLED
+/* #define HAL_DCMI_MODULE_ENABLED */
+#define HAL_DMA_MODULE_ENABLED
+/* #define HAL_DMA2D_MODULE_ENABLED */
+/* #define HAL_ETH_MODULE_ENABLED */
+#define HAL_FLASH_MODULE_ENABLED
+/* #define HAL_NAND_MODULE_ENABLED */
+/* #define HAL_NOR_MODULE_ENABLED */
+/* #define HAL_PCCARD_MODULE_ENABLED */
+/* #define HAL_SRAM_MODULE_ENABLED */
+/* #define HAL_SDRAM_MODULE_ENABLED */
+/* #define HAL_HASH_MODULE_ENABLED */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED
+/* #define HAL_IWDG_MODULE_ENABLED */
+/* #define HAL_LTDC_MODULE_ENABLED */
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+/* #define HAL_SAI_MODULE_ENABLED */
+#define HAL_SD_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+/* #define HAL_USART_MODULE_ENABLED */
+/* #define HAL_IRDA_MODULE_ENABLED */
+/* #define HAL_SMARTCARD_MODULE_ENABLED */
+/* #define HAL_WWDG_MODULE_ENABLED */
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+/* #define HAL_HCD_MODULE_ENABLED */
+
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE)
+ #define LSI_VALUE  ((uint32_t)40000)
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  */
+#if !defined  (LSE_VALUE)
+ #define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for I2S peripheral
+  *        This value is used by the I2S HAL module to compute the I2S clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
+  */
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */
+#define  VDD_VALUE                    ((uint32_t)3300) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            ((uint32_t)0x00) /*!< tick interrupt priority */
+#define  USE_RTOS                     0
+#define  PREFETCH_ENABLE              1
+#define  INSTRUCTION_CACHE_ENABLE     1
+#define  DATA_CACHE_ENABLE            1
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1 */
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0   2
+#define MAC_ADDR1   0
+#define MAC_ADDR2   0
+#define MAC_ADDR3   0
+#define MAC_ADDR4   0
+#define MAC_ADDR5   0
+
+/* Definition of the Ethernet driver buffers size and count */
+#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
+#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
+#define ETH_RXBUFNB                    ((uint32_t)4)       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
+#define ETH_TXBUFNB                    ((uint32_t)4)       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848 PHY Address*/
+#define DP83848_PHY_ADDRESS             0x01
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
+#define PHY_RESET_DELAY                 ((uint32_t)0x000000FF)
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
+
+#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
+#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
+#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
+
+#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
+#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
+#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
+#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
+#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
+#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
+#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
+
+#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
+#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
+#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
+
+/* Section 4: Extended PHY Registers */
+
+#define PHY_SR                          ((uint16_t)0x10)    /*!< PHY status register Offset                      */
+#define PHY_MICR                        ((uint16_t)0x11)    /*!< MII Interrupt Control Register                  */
+#define PHY_MISR                        ((uint16_t)0x12)    /*!< MII Interrupt Status and Misc. Control Register */
+
+#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
+#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
+#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
+
+#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
+#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
+
+#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
+#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32f4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32f4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32f4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32f4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32f4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+  #include "stm32f4xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32f4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32f4xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+  #include "stm32f4xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+  #include "stm32f4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+  #include "stm32f4xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+  #include "stm32f4xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32f4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+  #include "stm32f4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+  #include "stm32f4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+  #include "stm32f4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+  #include "stm32f4xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+  #include "stm32f4xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+ #include "stm32f4xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32f4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32f4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f4xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/boards/PYBV11/mpconfigboard.h b/ports/stm32/boards/PYBV11/mpconfigboard.h
similarity index 100%
rename from stmhal/boards/PYBV11/mpconfigboard.h
rename to ports/stm32/boards/PYBV11/mpconfigboard.h
diff --git a/stmhal/boards/PYBV11/mpconfigboard.mk b/ports/stm32/boards/PYBV11/mpconfigboard.mk
similarity index 100%
rename from stmhal/boards/PYBV11/mpconfigboard.mk
rename to ports/stm32/boards/PYBV11/mpconfigboard.mk
diff --git a/stmhal/boards/PYBV11/pins.csv b/ports/stm32/boards/PYBV11/pins.csv
similarity index 100%
rename from stmhal/boards/PYBV11/pins.csv
rename to ports/stm32/boards/PYBV11/pins.csv
diff --git a/stmhal/boards/PYBV11/stm32f4xx_hal_conf.h b/ports/stm32/boards/PYBV11/stm32f4xx_hal_conf.h
similarity index 100%
rename from stmhal/boards/PYBV11/stm32f4xx_hal_conf.h
rename to ports/stm32/boards/PYBV11/stm32f4xx_hal_conf.h
diff --git a/stmhal/boards/PYBV3/mpconfigboard.h b/ports/stm32/boards/PYBV3/mpconfigboard.h
similarity index 100%
rename from stmhal/boards/PYBV3/mpconfigboard.h
rename to ports/stm32/boards/PYBV3/mpconfigboard.h
diff --git a/stmhal/boards/PYBV3/mpconfigboard.mk b/ports/stm32/boards/PYBV3/mpconfigboard.mk
similarity index 100%
rename from stmhal/boards/PYBV3/mpconfigboard.mk
rename to ports/stm32/boards/PYBV3/mpconfigboard.mk
diff --git a/stmhal/boards/PYBV3/pins.csv b/ports/stm32/boards/PYBV3/pins.csv
similarity index 100%
rename from stmhal/boards/PYBV3/pins.csv
rename to ports/stm32/boards/PYBV3/pins.csv
diff --git a/ports/stm32/boards/PYBV3/stm32f4xx_hal_conf.h b/ports/stm32/boards/PYBV3/stm32f4xx_hal_conf.h
new file mode 100644
index 0000000000..d3df51c101
--- /dev/null
+++ b/ports/stm32/boards/PYBV3/stm32f4xx_hal_conf.h
@@ -0,0 +1,411 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_conf.h
+  * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    19-June-2014
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CONF_H
+#define __STM32F4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+#define USE_USB_FS
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_CAN_MODULE_ENABLED
+/* #define HAL_CRC_MODULE_ENABLED */
+/* #define HAL_CRYP_MODULE_ENABLED */
+#define HAL_DAC_MODULE_ENABLED
+/* #define HAL_DCMI_MODULE_ENABLED */
+#define HAL_DMA_MODULE_ENABLED
+/* #define HAL_DMA2D_MODULE_ENABLED */
+/* #define HAL_ETH_MODULE_ENABLED */
+#define HAL_FLASH_MODULE_ENABLED
+/* #define HAL_NAND_MODULE_ENABLED */
+/* #define HAL_NOR_MODULE_ENABLED */
+/* #define HAL_PCCARD_MODULE_ENABLED */
+/* #define HAL_SRAM_MODULE_ENABLED */
+/* #define HAL_SDRAM_MODULE_ENABLED */
+/* #define HAL_HASH_MODULE_ENABLED */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+/* #define HAL_I2S_MODULE_ENABLED */
+/* #define HAL_IWDG_MODULE_ENABLED */
+/* #define HAL_LTDC_MODULE_ENABLED */
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+/* #define HAL_SAI_MODULE_ENABLED */
+#define HAL_SD_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+/* #define HAL_USART_MODULE_ENABLED */
+/* #define HAL_IRDA_MODULE_ENABLED */
+/* #define HAL_SMARTCARD_MODULE_ENABLED */
+/* #define HAL_WWDG_MODULE_ENABLED */
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+/* #define HAL_HCD_MODULE_ENABLED */
+
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE)
+ #define LSI_VALUE  ((uint32_t)40000)
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  */
+#if !defined  (LSE_VALUE)
+ #define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for I2S peripheral
+  *        This value is used by the I2S HAL module to compute the I2S clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
+  */
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */
+#define  VDD_VALUE                    ((uint32_t)3300) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            ((uint32_t)0x00) /*!< tick interrupt priority */
+#define  USE_RTOS                     0
+#define  PREFETCH_ENABLE              1
+#define  INSTRUCTION_CACHE_ENABLE     1
+#define  DATA_CACHE_ENABLE            1
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1 */
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0   2
+#define MAC_ADDR1   0
+#define MAC_ADDR2   0
+#define MAC_ADDR3   0
+#define MAC_ADDR4   0
+#define MAC_ADDR5   0
+
+/* Definition of the Ethernet driver buffers size and count */
+#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
+#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
+#define ETH_RXBUFNB                    ((uint32_t)4)       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
+#define ETH_TXBUFNB                    ((uint32_t)4)       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848 PHY Address*/
+#define DP83848_PHY_ADDRESS             0x01
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
+#define PHY_RESET_DELAY                 ((uint32_t)0x000000FF)
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
+
+#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
+#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
+#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
+
+#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
+#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
+#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
+#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
+#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
+#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
+#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
+
+#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
+#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
+#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
+
+/* Section 4: Extended PHY Registers */
+
+#define PHY_SR                          ((uint16_t)0x10)    /*!< PHY status register Offset                      */
+#define PHY_MICR                        ((uint16_t)0x11)    /*!< MII Interrupt Control Register                  */
+#define PHY_MISR                        ((uint16_t)0x12)    /*!< MII Interrupt Status and Misc. Control Register */
+
+#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
+#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
+#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
+
+#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
+#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
+
+#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
+#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32f4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32f4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32f4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32f4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32f4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+  #include "stm32f4xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32f4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32f4xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+  #include "stm32f4xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+  #include "stm32f4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+  #include "stm32f4xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+  #include "stm32f4xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32f4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+  #include "stm32f4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+  #include "stm32f4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+  #include "stm32f4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+  #include "stm32f4xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+  #include "stm32f4xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+ #include "stm32f4xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32f4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32f4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f4xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/boards/PYBV4/mpconfigboard.h b/ports/stm32/boards/PYBV4/mpconfigboard.h
similarity index 100%
rename from stmhal/boards/PYBV4/mpconfigboard.h
rename to ports/stm32/boards/PYBV4/mpconfigboard.h
diff --git a/stmhal/boards/PYBV4/mpconfigboard.mk b/ports/stm32/boards/PYBV4/mpconfigboard.mk
similarity index 100%
rename from stmhal/boards/PYBV4/mpconfigboard.mk
rename to ports/stm32/boards/PYBV4/mpconfigboard.mk
diff --git a/stmhal/boards/PYBV4/pins.csv b/ports/stm32/boards/PYBV4/pins.csv
similarity index 100%
rename from stmhal/boards/PYBV4/pins.csv
rename to ports/stm32/boards/PYBV4/pins.csv
diff --git a/ports/stm32/boards/PYBV4/stm32f4xx_hal_conf.h b/ports/stm32/boards/PYBV4/stm32f4xx_hal_conf.h
new file mode 100644
index 0000000000..d3df51c101
--- /dev/null
+++ b/ports/stm32/boards/PYBV4/stm32f4xx_hal_conf.h
@@ -0,0 +1,411 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_conf.h
+  * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    19-June-2014
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CONF_H
+#define __STM32F4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+#define USE_USB_FS
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_CAN_MODULE_ENABLED
+/* #define HAL_CRC_MODULE_ENABLED */
+/* #define HAL_CRYP_MODULE_ENABLED */
+#define HAL_DAC_MODULE_ENABLED
+/* #define HAL_DCMI_MODULE_ENABLED */
+#define HAL_DMA_MODULE_ENABLED
+/* #define HAL_DMA2D_MODULE_ENABLED */
+/* #define HAL_ETH_MODULE_ENABLED */
+#define HAL_FLASH_MODULE_ENABLED
+/* #define HAL_NAND_MODULE_ENABLED */
+/* #define HAL_NOR_MODULE_ENABLED */
+/* #define HAL_PCCARD_MODULE_ENABLED */
+/* #define HAL_SRAM_MODULE_ENABLED */
+/* #define HAL_SDRAM_MODULE_ENABLED */
+/* #define HAL_HASH_MODULE_ENABLED */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+/* #define HAL_I2S_MODULE_ENABLED */
+/* #define HAL_IWDG_MODULE_ENABLED */
+/* #define HAL_LTDC_MODULE_ENABLED */
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+/* #define HAL_SAI_MODULE_ENABLED */
+#define HAL_SD_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+/* #define HAL_USART_MODULE_ENABLED */
+/* #define HAL_IRDA_MODULE_ENABLED */
+/* #define HAL_SMARTCARD_MODULE_ENABLED */
+/* #define HAL_WWDG_MODULE_ENABLED */
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+/* #define HAL_HCD_MODULE_ENABLED */
+
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE)
+ #define LSI_VALUE  ((uint32_t)40000)
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  */
+#if !defined  (LSE_VALUE)
+ #define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for I2S peripheral
+  *        This value is used by the I2S HAL module to compute the I2S clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
+  */
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */
+#define  VDD_VALUE                    ((uint32_t)3300) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            ((uint32_t)0x00) /*!< tick interrupt priority */
+#define  USE_RTOS                     0
+#define  PREFETCH_ENABLE              1
+#define  INSTRUCTION_CACHE_ENABLE     1
+#define  DATA_CACHE_ENABLE            1
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1 */
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0   2
+#define MAC_ADDR1   0
+#define MAC_ADDR2   0
+#define MAC_ADDR3   0
+#define MAC_ADDR4   0
+#define MAC_ADDR5   0
+
+/* Definition of the Ethernet driver buffers size and count */
+#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
+#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
+#define ETH_RXBUFNB                    ((uint32_t)4)       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
+#define ETH_TXBUFNB                    ((uint32_t)4)       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848 PHY Address*/
+#define DP83848_PHY_ADDRESS             0x01
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
+#define PHY_RESET_DELAY                 ((uint32_t)0x000000FF)
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
+
+#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
+#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
+#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
+
+#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
+#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
+#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
+#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
+#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
+#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
+#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
+
+#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
+#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
+#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
+
+/* Section 4: Extended PHY Registers */
+
+#define PHY_SR                          ((uint16_t)0x10)    /*!< PHY status register Offset                      */
+#define PHY_MICR                        ((uint16_t)0x11)    /*!< MII Interrupt Control Register                  */
+#define PHY_MISR                        ((uint16_t)0x12)    /*!< MII Interrupt Status and Misc. Control Register */
+
+#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
+#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
+#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
+
+#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
+#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
+
+#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
+#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32f4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32f4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32f4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32f4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32f4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+  #include "stm32f4xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32f4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32f4xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+  #include "stm32f4xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+  #include "stm32f4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+  #include "stm32f4xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+  #include "stm32f4xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32f4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+  #include "stm32f4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+  #include "stm32f4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+  #include "stm32f4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+  #include "stm32f4xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+  #include "stm32f4xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+ #include "stm32f4xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32f4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32f4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f4xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/boards/STM32F411DISC/mpconfigboard.h b/ports/stm32/boards/STM32F411DISC/mpconfigboard.h
similarity index 100%
rename from stmhal/boards/STM32F411DISC/mpconfigboard.h
rename to ports/stm32/boards/STM32F411DISC/mpconfigboard.h
diff --git a/stmhal/boards/STM32F411DISC/mpconfigboard.mk b/ports/stm32/boards/STM32F411DISC/mpconfigboard.mk
similarity index 100%
rename from stmhal/boards/STM32F411DISC/mpconfigboard.mk
rename to ports/stm32/boards/STM32F411DISC/mpconfigboard.mk
diff --git a/stmhal/boards/STM32F411DISC/pins.csv b/ports/stm32/boards/STM32F411DISC/pins.csv
similarity index 100%
rename from stmhal/boards/STM32F411DISC/pins.csv
rename to ports/stm32/boards/STM32F411DISC/pins.csv
diff --git a/stmhal/boards/STM32F411DISC/stm32f4xx_hal_conf.h b/ports/stm32/boards/STM32F411DISC/stm32f4xx_hal_conf.h
similarity index 100%
rename from stmhal/boards/STM32F411DISC/stm32f4xx_hal_conf.h
rename to ports/stm32/boards/STM32F411DISC/stm32f4xx_hal_conf.h
diff --git a/stmhal/boards/STM32F429DISC/mpconfigboard.h b/ports/stm32/boards/STM32F429DISC/mpconfigboard.h
similarity index 100%
rename from stmhal/boards/STM32F429DISC/mpconfigboard.h
rename to ports/stm32/boards/STM32F429DISC/mpconfigboard.h
diff --git a/stmhal/boards/STM32F429DISC/mpconfigboard.mk b/ports/stm32/boards/STM32F429DISC/mpconfigboard.mk
similarity index 100%
rename from stmhal/boards/STM32F429DISC/mpconfigboard.mk
rename to ports/stm32/boards/STM32F429DISC/mpconfigboard.mk
diff --git a/stmhal/boards/STM32F429DISC/pins.csv b/ports/stm32/boards/STM32F429DISC/pins.csv
similarity index 100%
rename from stmhal/boards/STM32F429DISC/pins.csv
rename to ports/stm32/boards/STM32F429DISC/pins.csv
diff --git a/stmhal/boards/STM32F429DISC/stm32f4xx_hal_conf.h b/ports/stm32/boards/STM32F429DISC/stm32f4xx_hal_conf.h
similarity index 100%
rename from stmhal/boards/STM32F429DISC/stm32f4xx_hal_conf.h
rename to ports/stm32/boards/STM32F429DISC/stm32f4xx_hal_conf.h
diff --git a/stmhal/boards/STM32F439/mpconfigboard.h b/ports/stm32/boards/STM32F439/mpconfigboard.h
similarity index 100%
rename from stmhal/boards/STM32F439/mpconfigboard.h
rename to ports/stm32/boards/STM32F439/mpconfigboard.h
diff --git a/stmhal/boards/STM32F439/mpconfigboard.mk b/ports/stm32/boards/STM32F439/mpconfigboard.mk
similarity index 100%
rename from stmhal/boards/STM32F439/mpconfigboard.mk
rename to ports/stm32/boards/STM32F439/mpconfigboard.mk
diff --git a/stmhal/boards/STM32F439/pins.csv b/ports/stm32/boards/STM32F439/pins.csv
similarity index 100%
rename from stmhal/boards/STM32F439/pins.csv
rename to ports/stm32/boards/STM32F439/pins.csv
diff --git a/stmhal/boards/STM32F439/stm32f4xx_hal_conf.h b/ports/stm32/boards/STM32F439/stm32f4xx_hal_conf.h
similarity index 100%
rename from stmhal/boards/STM32F439/stm32f4xx_hal_conf.h
rename to ports/stm32/boards/STM32F439/stm32f4xx_hal_conf.h
diff --git a/stmhal/boards/STM32F4DISC/mpconfigboard.h b/ports/stm32/boards/STM32F4DISC/mpconfigboard.h
similarity index 100%
rename from stmhal/boards/STM32F4DISC/mpconfigboard.h
rename to ports/stm32/boards/STM32F4DISC/mpconfigboard.h
diff --git a/stmhal/boards/STM32F4DISC/mpconfigboard.mk b/ports/stm32/boards/STM32F4DISC/mpconfigboard.mk
similarity index 100%
rename from stmhal/boards/STM32F4DISC/mpconfigboard.mk
rename to ports/stm32/boards/STM32F4DISC/mpconfigboard.mk
diff --git a/stmhal/boards/STM32F4DISC/pins.csv b/ports/stm32/boards/STM32F4DISC/pins.csv
similarity index 100%
rename from stmhal/boards/STM32F4DISC/pins.csv
rename to ports/stm32/boards/STM32F4DISC/pins.csv
diff --git a/stmhal/boards/STM32F4DISC/staccel.py b/ports/stm32/boards/STM32F4DISC/staccel.py
similarity index 100%
rename from stmhal/boards/STM32F4DISC/staccel.py
rename to ports/stm32/boards/STM32F4DISC/staccel.py
diff --git a/ports/stm32/boards/STM32F4DISC/stm32f4xx_hal_conf.h b/ports/stm32/boards/STM32F4DISC/stm32f4xx_hal_conf.h
new file mode 100644
index 0000000000..d3df51c101
--- /dev/null
+++ b/ports/stm32/boards/STM32F4DISC/stm32f4xx_hal_conf.h
@@ -0,0 +1,411 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_conf.h
+  * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    19-June-2014
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CONF_H
+#define __STM32F4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+#define USE_USB_FS
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_CAN_MODULE_ENABLED
+/* #define HAL_CRC_MODULE_ENABLED */
+/* #define HAL_CRYP_MODULE_ENABLED */
+#define HAL_DAC_MODULE_ENABLED
+/* #define HAL_DCMI_MODULE_ENABLED */
+#define HAL_DMA_MODULE_ENABLED
+/* #define HAL_DMA2D_MODULE_ENABLED */
+/* #define HAL_ETH_MODULE_ENABLED */
+#define HAL_FLASH_MODULE_ENABLED
+/* #define HAL_NAND_MODULE_ENABLED */
+/* #define HAL_NOR_MODULE_ENABLED */
+/* #define HAL_PCCARD_MODULE_ENABLED */
+/* #define HAL_SRAM_MODULE_ENABLED */
+/* #define HAL_SDRAM_MODULE_ENABLED */
+/* #define HAL_HASH_MODULE_ENABLED */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+/* #define HAL_I2S_MODULE_ENABLED */
+/* #define HAL_IWDG_MODULE_ENABLED */
+/* #define HAL_LTDC_MODULE_ENABLED */
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+/* #define HAL_SAI_MODULE_ENABLED */
+#define HAL_SD_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+/* #define HAL_USART_MODULE_ENABLED */
+/* #define HAL_IRDA_MODULE_ENABLED */
+/* #define HAL_SMARTCARD_MODULE_ENABLED */
+/* #define HAL_WWDG_MODULE_ENABLED */
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+/* #define HAL_HCD_MODULE_ENABLED */
+
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE)
+ #define LSI_VALUE  ((uint32_t)40000)
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  */
+#if !defined  (LSE_VALUE)
+ #define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for I2S peripheral
+  *        This value is used by the I2S HAL module to compute the I2S clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
+  */
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */
+#define  VDD_VALUE                    ((uint32_t)3300) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            ((uint32_t)0x00) /*!< tick interrupt priority */
+#define  USE_RTOS                     0
+#define  PREFETCH_ENABLE              1
+#define  INSTRUCTION_CACHE_ENABLE     1
+#define  DATA_CACHE_ENABLE            1
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1 */
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0   2
+#define MAC_ADDR1   0
+#define MAC_ADDR2   0
+#define MAC_ADDR3   0
+#define MAC_ADDR4   0
+#define MAC_ADDR5   0
+
+/* Definition of the Ethernet driver buffers size and count */
+#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
+#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
+#define ETH_RXBUFNB                    ((uint32_t)4)       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
+#define ETH_TXBUFNB                    ((uint32_t)4)       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848 PHY Address*/
+#define DP83848_PHY_ADDRESS             0x01
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
+#define PHY_RESET_DELAY                 ((uint32_t)0x000000FF)
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
+
+#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
+#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
+#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
+
+#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
+#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
+#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
+#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
+#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
+#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
+#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
+
+#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
+#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
+#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
+
+/* Section 4: Extended PHY Registers */
+
+#define PHY_SR                          ((uint16_t)0x10)    /*!< PHY status register Offset                      */
+#define PHY_MICR                        ((uint16_t)0x11)    /*!< MII Interrupt Control Register                  */
+#define PHY_MISR                        ((uint16_t)0x12)    /*!< MII Interrupt Status and Misc. Control Register */
+
+#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
+#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
+#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
+
+#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
+#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
+
+#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
+#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32f4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32f4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32f4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32f4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32f4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+  #include "stm32f4xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32f4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32f4xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+  #include "stm32f4xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+  #include "stm32f4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+  #include "stm32f4xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+  #include "stm32f4xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32f4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+  #include "stm32f4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+  #include "stm32f4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+  #include "stm32f4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+  #include "stm32f4xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+  #include "stm32f4xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+ #include "stm32f4xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32f4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32f4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f4xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/boards/STM32F769DISC/mpconfigboard.h b/ports/stm32/boards/STM32F769DISC/mpconfigboard.h
similarity index 100%
rename from stmhal/boards/STM32F769DISC/mpconfigboard.h
rename to ports/stm32/boards/STM32F769DISC/mpconfigboard.h
diff --git a/stmhal/boards/STM32F769DISC/mpconfigboard.mk b/ports/stm32/boards/STM32F769DISC/mpconfigboard.mk
similarity index 100%
rename from stmhal/boards/STM32F769DISC/mpconfigboard.mk
rename to ports/stm32/boards/STM32F769DISC/mpconfigboard.mk
diff --git a/stmhal/boards/STM32F769DISC/pins.csv b/ports/stm32/boards/STM32F769DISC/pins.csv
similarity index 100%
rename from stmhal/boards/STM32F769DISC/pins.csv
rename to ports/stm32/boards/STM32F769DISC/pins.csv
diff --git a/stmhal/boards/STM32F769DISC/stm32f7xx_hal_conf.h b/ports/stm32/boards/STM32F769DISC/stm32f7xx_hal_conf.h
similarity index 100%
rename from stmhal/boards/STM32F769DISC/stm32f7xx_hal_conf.h
rename to ports/stm32/boards/STM32F769DISC/stm32f7xx_hal_conf.h
diff --git a/stmhal/boards/STM32F7DISC/board_init.c b/ports/stm32/boards/STM32F7DISC/board_init.c
similarity index 100%
rename from stmhal/boards/STM32F7DISC/board_init.c
rename to ports/stm32/boards/STM32F7DISC/board_init.c
diff --git a/stmhal/boards/STM32F7DISC/mpconfigboard.h b/ports/stm32/boards/STM32F7DISC/mpconfigboard.h
similarity index 100%
rename from stmhal/boards/STM32F7DISC/mpconfigboard.h
rename to ports/stm32/boards/STM32F7DISC/mpconfigboard.h
diff --git a/stmhal/boards/STM32F7DISC/mpconfigboard.mk b/ports/stm32/boards/STM32F7DISC/mpconfigboard.mk
similarity index 100%
rename from stmhal/boards/STM32F7DISC/mpconfigboard.mk
rename to ports/stm32/boards/STM32F7DISC/mpconfigboard.mk
diff --git a/stmhal/boards/STM32F7DISC/pins.csv b/ports/stm32/boards/STM32F7DISC/pins.csv
similarity index 100%
rename from stmhal/boards/STM32F7DISC/pins.csv
rename to ports/stm32/boards/STM32F7DISC/pins.csv
diff --git a/stmhal/boards/STM32F7DISC/stm32f7xx_hal_conf.h b/ports/stm32/boards/STM32F7DISC/stm32f7xx_hal_conf.h
similarity index 100%
rename from stmhal/boards/STM32F7DISC/stm32f7xx_hal_conf.h
rename to ports/stm32/boards/STM32F7DISC/stm32f7xx_hal_conf.h
diff --git a/stmhal/boards/STM32L476DISC/board_init.c b/ports/stm32/boards/STM32L476DISC/board_init.c
similarity index 100%
rename from stmhal/boards/STM32L476DISC/board_init.c
rename to ports/stm32/boards/STM32L476DISC/board_init.c
diff --git a/stmhal/boards/STM32L476DISC/mpconfigboard.h b/ports/stm32/boards/STM32L476DISC/mpconfigboard.h
similarity index 100%
rename from stmhal/boards/STM32L476DISC/mpconfigboard.h
rename to ports/stm32/boards/STM32L476DISC/mpconfigboard.h
diff --git a/stmhal/boards/STM32L476DISC/mpconfigboard.mk b/ports/stm32/boards/STM32L476DISC/mpconfigboard.mk
similarity index 100%
rename from stmhal/boards/STM32L476DISC/mpconfigboard.mk
rename to ports/stm32/boards/STM32L476DISC/mpconfigboard.mk
diff --git a/stmhal/boards/STM32L476DISC/pins.csv b/ports/stm32/boards/STM32L476DISC/pins.csv
similarity index 100%
rename from stmhal/boards/STM32L476DISC/pins.csv
rename to ports/stm32/boards/STM32L476DISC/pins.csv
diff --git a/ports/stm32/boards/STM32L476DISC/stm32l4xx_hal_conf.h b/ports/stm32/boards/STM32L476DISC/stm32l4xx_hal_conf.h
new file mode 100644
index 0000000000..9348e06790
--- /dev/null
+++ b/ports/stm32/boards/STM32L476DISC/stm32l4xx_hal_conf.h
@@ -0,0 +1,373 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_conf.h
+  * @author  MCD Application Team
+  * @version V1.2.0
+  * @date    25-November-2015
+  * @brief   HAL configuration template file.
+  *          This file should be copied to the application folder and renamed
+  *          to stm32l4xx_hal_conf.h.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_CONF_H
+#define __STM32L4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define USE_USB_FS
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_CAN_MODULE_ENABLED
+/* #define HAL_COMP_MODULE_ENABLED */
+#define HAL_CORTEX_MODULE_ENABLED
+/* #define HAL_CRC_MODULE_ENABLED */
+/* #define HAL_CRYP_MODULE_ENABLED */
+#define HAL_DAC_MODULE_ENABLED
+/* #define HAL_DFSDM_MODULE_ENABLED */
+#define HAL_DMA_MODULE_ENABLED
+/* #define HAL_FIREWALL_MODULE_ENABLED */
+#define HAL_FLASH_MODULE_ENABLED
+/* #define HAL_HCD_MODULE_ENABLED */
+/* #define HAL_NAND_MODULE_ENABLED */
+/* #define HAL_NOR_MODULE_ENABLED */
+/* #define HAL_SRAM_MODULE_ENABLED */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+/* #define HAL_IRDA_MODULE_ENABLED */
+/* #define HAL_IWDG_MODULE_ENABLED */
+/* #define HAL_LCD_MODULE_ENABLED */
+/* #define HAL_LPTIM_MODULE_ENABLED */
+/* #define HAL_OPAMP_MODULE_ENABLED */
+#define HAL_PCD_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+/* #define HAL_QSPI_MODULE_ENABLED */
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+/* #define HAL_SAI_MODULE_ENABLED */
+#define HAL_SD_MODULE_ENABLED
+/* #define HAL_SMARTCARD_MODULE_ENABLED */
+/* #define HAL_SMBUS_MODULE_ENABLED */
+#define HAL_SPI_MODULE_ENABLED
+/* #define HAL_SWPMI_MODULE_ENABLED */
+#define HAL_TIM_MODULE_ENABLED
+/* #define HAL_TSC_MODULE_ENABLED */
+#define HAL_UART_MODULE_ENABLED
+/* #define HAL_USART_MODULE_ENABLED */
+/* #define HAL_WWDG_MODULE_ENABLED */
+
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).  
+  */
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL). 
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  ((uint32_t)32000)       /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000)   /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined  (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/**
+  * @brief External clock source for SAI2 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined  (EXTERNAL_SAI2_CLOCK_VALUE)
+  #define EXTERNAL_SAI2_CLOCK_VALUE    ((uint32_t)48000) /*!< Value of the SAI2 External clock source in Hz*/
+#endif /* EXTERNAL_SAI2_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */
+#define  VDD_VALUE                    ((uint32_t)3300) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            ((uint32_t)0x00) /*!< tick interrupt priority */
+#define  USE_RTOS                     0
+#define  PREFETCH_ENABLE              1
+#define  INSTRUCTION_CACHE_ENABLE     1
+#define  DATA_CACHE_ENABLE            1
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32l4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32l4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32l4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_DFSDM_MODULE_ENABLED
+  #include "stm32l4xx_hal_dfsdm.h"
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32l4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32l4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+  #include "stm32l4xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32l4xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32l4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32l4xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+  #include "stm32l4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_FIREWALL_MODULE_ENABLED
+  #include "stm32l4xx_hal_firewall.h"
+#endif /* HAL_FIREWALL_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32l4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+  #include "stm32l4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+  #include "stm32l4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+  #include "stm32l4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32l4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32l4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32l4xx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#include "stm32l4xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_OPAMP_MODULE_ENABLED
+#include "stm32l4xx_hal_opamp.h"
+#endif /* HAL_OPAMP_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32l4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32l4xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32l4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32l4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32l4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32l4xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32l4xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32l4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_SWPMI_MODULE_ENABLED
+ #include "stm32l4xx_hal_swpmi.h"
+#endif /* HAL_SWPMI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32l4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+ #include "stm32l4xx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32l4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32l4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32l4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32l4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32l4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32l4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32l4xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/boards/common.ld b/ports/stm32/boards/common.ld
similarity index 100%
rename from stmhal/boards/common.ld
rename to ports/stm32/boards/common.ld
diff --git a/stmhal/boards/make-pins.py b/ports/stm32/boards/make-pins.py
similarity index 100%
rename from stmhal/boards/make-pins.py
rename to ports/stm32/boards/make-pins.py
diff --git a/stmhal/boards/openocd_stm32f4.cfg b/ports/stm32/boards/openocd_stm32f4.cfg
similarity index 100%
rename from stmhal/boards/openocd_stm32f4.cfg
rename to ports/stm32/boards/openocd_stm32f4.cfg
diff --git a/stmhal/boards/openocd_stm32f7.cfg b/ports/stm32/boards/openocd_stm32f7.cfg
similarity index 100%
rename from stmhal/boards/openocd_stm32f7.cfg
rename to ports/stm32/boards/openocd_stm32f7.cfg
diff --git a/stmhal/boards/openocd_stm32l4.cfg b/ports/stm32/boards/openocd_stm32l4.cfg
similarity index 100%
rename from stmhal/boards/openocd_stm32l4.cfg
rename to ports/stm32/boards/openocd_stm32l4.cfg
diff --git a/stmhal/boards/pllvalues.py b/ports/stm32/boards/pllvalues.py
similarity index 56%
rename from stmhal/boards/pllvalues.py
rename to ports/stm32/boards/pllvalues.py
index 183313f304..befd6cfa0d 100644
--- a/stmhal/boards/pllvalues.py
+++ b/ports/stm32/boards/pllvalues.py
@@ -4,6 +4,8 @@ the CPU frequency to a given value.  The algorithm here appears as C code
 for the machine.freq() function.
 """
 
+from __future__ import print_function
+
 def close_int(x):
     return abs(x - round(x)) < 0.01
 
@@ -38,7 +40,10 @@ def compute_pll(hse, sys):
 
 # improved version that doesn't require N/M to be an integer
 def compute_pll2(hse, sys):
-    for P in (2, 4, 6, 8): # allowed values of P
+    # Loop over the allowed values of P, looking for a valid PLL configuration
+    # that gives the desired "sys" frequency.  We use floats for P to force
+    # floating point arithmetic on Python 2.
+    for P in (2.0, 4.0, 6.0, 8.0):
         Q = sys * P / 48
         # Q must be an integer in a set range
         if not (close_int(Q) and 2 <= Q <= 15):
@@ -67,14 +72,17 @@ def compute_pll2(hse, sys):
     # no valid values found
     return None
 
-def verify_and_print_pll(hse, sys, pll):
+def compute_derived(hse, pll):
     M, N, P, Q = pll
-
-    # compute derived quantities
     vco_in = hse / M
     vco_out = hse * N / M
     pllck = hse / M * N / P
     pll48ck = hse / M * N / Q
+    return (vco_in, vco_out, pllck, pll48ck)
+
+def verify_pll(hse, pll):
+    M, N, P, Q = pll
+    vco_in, vco_out, pllck, pll48ck = compute_derived(hse, pll)
 
     # verify ints
     assert close_int(M)
@@ -90,26 +98,68 @@ def verify_and_print_pll(hse, sys, pll):
     assert 1 <= vco_in <= 2
     assert 192 <= vco_out <= 432
 
-    # print out values
-    print(out_format % (sys, M, N, P, Q, vco_in, vco_out, pllck, pll48ck))
+def generate_c_table(hse, valid_plls):
+    valid_plls = valid_plls + [(16, (0, 0, 2, 0))]
+    if hse < 16:
+        valid_plls.append((hse, (1, 0, 2, 0)))
+    valid_plls.sort()
+    print("// (M, P/2-1, SYS) values for %u MHz HSE" % hse)
+    print("static const uint16_t pll_freq_table[%u] = {" % len(valid_plls))
+    for sys, (M, N, P, Q) in valid_plls:
+        print("    (%u << 10) | (%u << 8) | %u," % (M, P // 2 - 1, sys))
+    print("};")
+
+def print_table(hse, valid_plls):
+    print("HSE =", hse, "MHz")
+    print("sys :  M      N     P     Q : VCO_IN VCO_OUT   PLLCK PLL48CK")
+    out_format = "%3u : %2u  %.1f  %.2f  %.2f :  %5.2f  %6.2f  %6.2f  %6.2f"
+    for sys, pll in valid_plls:
+        print(out_format % ((sys,) + pll + compute_derived(hse, pll)))
+    print("found %u valid configurations" % len(valid_plls))
 
 def main():
     global out_format
+
+    # parse input args
     import sys
-    if len(sys.argv) != 2:
-        print("usage: pllvalues.py <hse in MHz>")
+    argv = sys.argv[1:]
+
+    c_table = False
+    if argv[0] == '-c':
+        c_table = True
+        argv.pop(0)
+
+    if len(argv) != 1:
+        print("usage: pllvalues.py [-c] <hse in MHz>")
         sys.exit(1)
-    hse_value = int(sys.argv[1])
-    print("HSE =", hse_value, "MHz")
-    print("sys :  M      N     P     Q : VCO_IN VCO_OUT   PLLCK PLL48CK")
-    out_format = "%3u : %2u  %.1f  %.2f  %.2f :  %5.2f  %6.2f  %6.2f  %6.2f"
-    n_valid = 0
+
+    if argv[0].startswith("file:"):
+        # extract HSE_VALUE from header file
+        with open(argv[0][5:]) as f:
+            for line in f:
+                line = line.strip()
+                if line.startswith("#define") and line.find("HSE_VALUE") != -1:
+                    idx_start = line.find("((uint32_t)") + 11
+                    idx_end = line.find(")", idx_start)
+                    hse = int(line[idx_start:idx_end]) // 1000000
+                    break
+            else:
+                raise ValueError("%s does not contain a definition of HSE_VALUE" % argv[0])
+    else:
+        # HSE given directly as an integer
+        hse = int(argv[0])
+
+    valid_plls = []
     for sysclk in range(1, 217):
-        pll = compute_pll2(hse_value, sysclk)
+        pll = compute_pll2(hse, sysclk)
         if pll is not None:
-            n_valid += 1
-            verify_and_print_pll(hse_value, sysclk, pll)
-    print("found %u valid configurations" % n_valid)
+            verify_pll(hse, pll)
+            valid_plls.append((sysclk, pll))
+
+    if c_table:
+        generate_c_table(hse, valid_plls)
+    else:
+        print_table(hse, valid_plls)
 
 if __name__ == "__main__":
     main()
diff --git a/stmhal/boards/stm32f401_af.csv b/ports/stm32/boards/stm32f401_af.csv
similarity index 100%
rename from stmhal/boards/stm32f401_af.csv
rename to ports/stm32/boards/stm32f401_af.csv
diff --git a/stmhal/boards/stm32f401xd.ld b/ports/stm32/boards/stm32f401xd.ld
similarity index 62%
rename from stmhal/boards/stm32f401xd.ld
rename to ports/stm32/boards/stm32f401xd.ld
index 415c258496..89f6056096 100644
--- a/stmhal/boards/stm32f401xd.ld
+++ b/ports/stm32/boards/stm32f401xd.ld
@@ -5,11 +5,11 @@
 /* Specify the memory areas */
 MEMORY
 {
-    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 0x060000 /* entire flash, 384 KiB */
-    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 0x004000 /* sector 0, 16 KiB */
-    FLASH_FS (rx)   : ORIGIN = 0x08004000, LENGTH = 0x01C000 /* sectors 1,2,3 are 16K, 4 is 64K */
-    FLASH_TEXT (rx) : ORIGIN = 0x08020000, LENGTH = 0x040000 /* sectors 5,6 2*128KiB = 256 KiB */
-    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 0x018000 /* 96 KiB */
+    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 384K /* entire flash */
+    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 16K /* sector 0 */
+    FLASH_FS (rx)   : ORIGIN = 0x08004000, LENGTH = 112K /* sectors 1,2,3 are 16K, 4 is 64K */
+    FLASH_TEXT (rx) : ORIGIN = 0x08020000, LENGTH = 256K /* sectors 5,6 are 128K */
+    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 96K
 }
 
 /* produce a link error if there is not this amount of RAM for these sections */
diff --git a/stmhal/boards/stm32f401xe.ld b/ports/stm32/boards/stm32f401xe.ld
similarity index 61%
rename from stmhal/boards/stm32f401xe.ld
rename to ports/stm32/boards/stm32f401xe.ld
index a2e693b491..ae2f899048 100644
--- a/stmhal/boards/stm32f401xe.ld
+++ b/ports/stm32/boards/stm32f401xe.ld
@@ -5,11 +5,11 @@
 /* Specify the memory areas */
 MEMORY
 {
-    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 0x080000 /* entire flash, 512 KiB */
-    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 0x004000 /* sector 0, 16 KiB */
-    FLASH_FS (rx)   : ORIGIN = 0x08004000, LENGTH = 0x01C000 /* sectors 1,2,3 are 16K, 4 is 64K */
-    FLASH_TEXT (rx) : ORIGIN = 0x08020000, LENGTH = 0x060000 /* sectors 5,6,7 3*128KiB = 384 KiB */
-    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 0x018000 /* 96 KiB */
+    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 512K /* entire flash */
+    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 16K /* sector 0 */
+    FLASH_FS (rx)   : ORIGIN = 0x08004000, LENGTH = 112K /* sectors 1,2,3 are 16K, 4 is 64K */
+    FLASH_TEXT (rx) : ORIGIN = 0x08020000, LENGTH = 384K /* sectors 5,6,7 are 128K */
+    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 96K
 }
 
 /* produce a link error if there is not this amount of RAM for these sections */
diff --git a/stmhal/boards/stm32f405.ld b/ports/stm32/boards/stm32f405.ld
similarity index 100%
rename from stmhal/boards/stm32f405.ld
rename to ports/stm32/boards/stm32f405.ld
diff --git a/stmhal/boards/stm32f405_af.csv b/ports/stm32/boards/stm32f405_af.csv
similarity index 100%
rename from stmhal/boards/stm32f405_af.csv
rename to ports/stm32/boards/stm32f405_af.csv
diff --git a/stmhal/boards/stm32f411.ld b/ports/stm32/boards/stm32f411.ld
similarity index 60%
rename from stmhal/boards/stm32f411.ld
rename to ports/stm32/boards/stm32f411.ld
index d156e852a0..7adfa35c95 100644
--- a/stmhal/boards/stm32f411.ld
+++ b/ports/stm32/boards/stm32f411.ld
@@ -5,11 +5,11 @@
 /* Specify the memory areas */
 MEMORY
 {
-    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 0x080000 /* entire flash, 512 KiB */
-    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 0x004000 /* sector 0, 16 KiB */
-                                                             /* sectors 1,2,3 are 16K, 4 is 64K (for filesystem) */
-    FLASH_TEXT (rx) : ORIGIN = 0x08020000, LENGTH = 0x060000 /* sectors 5,6,7 3*128KiB = 384 KiB */
-    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 0x020000 /* 128 KiB */
+    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 512K /* entire flash */
+    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 16K /* sector 0 */
+    FLASH_FS (rx)   : ORIGIN = 0x08004000, LENGTH = 112K /* sectors 1,2,3 are 16K, 4 is 64K */
+    FLASH_TEXT (rx) : ORIGIN = 0x08020000, LENGTH = 384K /* sectors 5,6,7 are 128K */
+    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 128K
 }
 
 /* produce a link error if there is not this amount of RAM for these sections */
diff --git a/stmhal/boards/stm32f411_af.csv b/ports/stm32/boards/stm32f411_af.csv
similarity index 100%
rename from stmhal/boards/stm32f411_af.csv
rename to ports/stm32/boards/stm32f411_af.csv
diff --git a/stmhal/boards/stm32f429.ld b/ports/stm32/boards/stm32f429.ld
similarity index 62%
rename from stmhal/boards/stm32f429.ld
rename to ports/stm32/boards/stm32f429.ld
index f358233a60..a0931684d2 100644
--- a/stmhal/boards/stm32f429.ld
+++ b/ports/stm32/boards/stm32f429.ld
@@ -5,11 +5,12 @@
 /* Specify the memory areas */
 MEMORY
 {
-    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 0x0200000 /* entire flash, 2048 KiB */
-    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 0x0004000 /* sector 0, 16 KiB */
-    FLASH_TEXT (rx) : ORIGIN = 0x08020000, LENGTH = 0x0088000 /* sectors 5,6,7,8, 4*128KiB = 512 KiB (could increase it more) */
-    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 0x0030000 /* 192 KiB */
-    SDRAM(xrw)      : ORIGIN = 0xC0000000, LENGTH = 0x0800000 /* 8 MByte */
+    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 2048K /* entire flash */
+    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 16K /* sector 0, 16 KiB */
+    FLASH_FS (rx)   : ORIGIN = 0x08004000, LENGTH = 112K /* sectors 1-4: 3*16K+64K */
+    FLASH_TEXT (rx) : ORIGIN = 0x08020000, LENGTH = 896K /* sectors 5-11 are 128K */
+    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 192K
+    SDRAM(xrw)      : ORIGIN = 0xC0000000, LENGTH = 8192K
 }
 
 /* produce a link error if there is not this amount of RAM for these sections */
diff --git a/stmhal/boards/stm32f429_af.csv b/ports/stm32/boards/stm32f429_af.csv
similarity index 100%
rename from stmhal/boards/stm32f429_af.csv
rename to ports/stm32/boards/stm32f429_af.csv
diff --git a/stmhal/boards/stm32f439.ld b/ports/stm32/boards/stm32f439.ld
similarity index 52%
rename from stmhal/boards/stm32f439.ld
rename to ports/stm32/boards/stm32f439.ld
index 0da185e89e..a76a0ebc79 100644
--- a/stmhal/boards/stm32f439.ld
+++ b/ports/stm32/boards/stm32f439.ld
@@ -5,11 +5,13 @@
 /* Specify the memory areas */
 MEMORY
 {
-    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 0x200000 /* entire flash, 2048 KiB */
-    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 0x004000 /* sector 0, 16 KiB */
-    FLASH_TEXT (rx) : ORIGIN = 0x08020000, LENGTH = 0x080000 /* sectors 5,6,7,8, 4*128KiB = 512 KiB (could increase it more) */
-    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 0x030000 /* 192 KiB */
-    CCMRAM (xrw)    : ORIGIN = 0x10000000, LENGTH = 0x010000 /* 64 KiB */
+    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 2048K /* entire flash */
+    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 16K /* sector 0 */
+    FLASH_TEXT (rx) : ORIGIN = 0x08020000, LENGTH = 896K /* sectors 5-11 are 128K */
+    FLASH_FS (rx)   : ORIGIN = 0x08100000, LENGTH = 256K /* sectors 12-17 are 4*16K+64K+128K */
+    FLASH_FS2 (rx)  : ORIGIN = 0x08140000, LENGTH = 128K /* sector 18 */
+    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 192K
+    CCMRAM (xrw)    : ORIGIN = 0x10000000, LENGTH = 64K
 }
 
 /* produce a link error if there is not this amount of RAM for these sections */
diff --git a/stmhal/boards/stm32f439_af.csv b/ports/stm32/boards/stm32f439_af.csv
similarity index 100%
rename from stmhal/boards/stm32f439_af.csv
rename to ports/stm32/boards/stm32f439_af.csv
diff --git a/stmhal/boards/stm32f4xx_prefix.c b/ports/stm32/boards/stm32f4xx_prefix.c
similarity index 100%
rename from stmhal/boards/stm32f4xx_prefix.c
rename to ports/stm32/boards/stm32f4xx_prefix.c
diff --git a/stmhal/boards/stm32f746.ld b/ports/stm32/boards/stm32f746.ld
similarity index 100%
rename from stmhal/boards/stm32f746.ld
rename to ports/stm32/boards/stm32f746.ld
diff --git a/stmhal/boards/stm32f746_af.csv b/ports/stm32/boards/stm32f746_af.csv
similarity index 100%
rename from stmhal/boards/stm32f746_af.csv
rename to ports/stm32/boards/stm32f746_af.csv
diff --git a/stmhal/boards/stm32f767.ld b/ports/stm32/boards/stm32f767.ld
similarity index 100%
rename from stmhal/boards/stm32f767.ld
rename to ports/stm32/boards/stm32f767.ld
diff --git a/stmhal/boards/stm32f767_af.csv b/ports/stm32/boards/stm32f767_af.csv
similarity index 100%
rename from stmhal/boards/stm32f767_af.csv
rename to ports/stm32/boards/stm32f767_af.csv
diff --git a/stmhal/boards/stm32f769.ld b/ports/stm32/boards/stm32f769.ld
similarity index 100%
rename from stmhal/boards/stm32f769.ld
rename to ports/stm32/boards/stm32f769.ld
diff --git a/stmhal/boards/stm32l476_af.csv b/ports/stm32/boards/stm32l476_af.csv
similarity index 100%
rename from stmhal/boards/stm32l476_af.csv
rename to ports/stm32/boards/stm32l476_af.csv
diff --git a/stmhal/boards/stm32l476xe.ld b/ports/stm32/boards/stm32l476xe.ld
similarity index 78%
rename from stmhal/boards/stm32l476xe.ld
rename to ports/stm32/boards/stm32l476xe.ld
index bb9895d2a7..11b2972ade 100644
--- a/stmhal/boards/stm32l476xe.ld
+++ b/ports/stm32/boards/stm32l476xe.ld
@@ -6,9 +6,9 @@
 MEMORY
 {
     FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 512K
-    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 0x0004000 /* sectors 0-7, 16 KiB */
-    FLASH_TEXT (rx) : ORIGIN = 0x08004000, LENGTH = 0x005C000 /* sectors 8-191, 368 KiB */
-    FLASH_FS (r)    : ORIGIN = 0x08060000, LENGTH = 0x0020000 /* sectors 192-255, 128 KiB */
+    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 16K /* sectors 0-7 */
+    FLASH_TEXT (rx) : ORIGIN = 0x08004000, LENGTH = 368K /* sectors 8-191 */
+    FLASH_FS (r)    : ORIGIN = 0x08060000, LENGTH = 128K /* sectors 192-255 */
     RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 96K
     SRAM2 (xrw)     : ORIGIN = 0x10000000, LENGTH = 32K
 }
diff --git a/stmhal/boards/stm32l476xg.ld b/ports/stm32/boards/stm32l476xg.ld
similarity index 78%
rename from stmhal/boards/stm32l476xg.ld
rename to ports/stm32/boards/stm32l476xg.ld
index 684078c430..a94fa27504 100644
--- a/stmhal/boards/stm32l476xg.ld
+++ b/ports/stm32/boards/stm32l476xg.ld
@@ -6,9 +6,9 @@
 MEMORY
 {
     FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 1024K
-    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 0x0004000 /* sectors 0-7, 16 KiB */
-    FLASH_TEXT (rx) : ORIGIN = 0x08004000, LENGTH = 0x007C000 /* sectors 8-255, 496 KiB */
-    FLASH_FS (r)    : ORIGIN = 0x08080000, LENGTH = 0x0080000 /* sectors 256-511 512 KiB */
+    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 16K /* sectors 0-7 */
+    FLASH_TEXT (rx) : ORIGIN = 0x08004000, LENGTH = 496K /* sectors 8-255 */
+    FLASH_FS (r)    : ORIGIN = 0x08080000, LENGTH = 512K /* sectors 256-511 */
     RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 96K
     SRAM2 (xrw)     : ORIGIN = 0x10000000, LENGTH = 32K
 }
diff --git a/stmhal/bufhelper.c b/ports/stm32/bufhelper.c
similarity index 100%
rename from stmhal/bufhelper.c
rename to ports/stm32/bufhelper.c
diff --git a/stmhal/bufhelper.h b/ports/stm32/bufhelper.h
similarity index 100%
rename from stmhal/bufhelper.h
rename to ports/stm32/bufhelper.h
diff --git a/stmhal/can.c b/ports/stm32/can.c
similarity index 98%
rename from stmhal/can.c
rename to ports/stm32/can.c
index d5d80d3263..25a608ce9b 100644
--- a/stmhal/can.c
+++ b/ports/stm32/can.c
@@ -28,8 +28,6 @@
 #include <string.h>
 #include <stdarg.h>
 
-#include "py/ioctl.h"
-#include "py/nlr.h"
 #include "py/objtuple.h"
 #include "py/runtime.h"
 #include "py/gc.h"
@@ -289,7 +287,7 @@ STATIC void pyb_can_print(const mp_print_t *print, mp_obj_t self_in, mp_print_ki
 }
 
 // init(mode, extframe=False, prescaler=100, *, sjw=1, bs1=6, bs2=8)
-STATIC mp_obj_t pyb_can_init_helper(pyb_can_obj_t *self, mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_can_init_helper(pyb_can_obj_t *self, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     static const mp_arg_t allowed_args[] = {
         { MP_QSTR_mode,         MP_ARG_REQUIRED | MP_ARG_INT,   {.u_int  = CAN_MODE_NORMAL} },
         { MP_QSTR_extframe,     MP_ARG_BOOL,                    {.u_bool = false} },
@@ -401,7 +399,7 @@ STATIC mp_obj_t pyb_can_make_new(const mp_obj_type_t *type, size_t n_args, size_
     return self;
 }
 
-STATIC mp_obj_t pyb_can_init(mp_uint_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_can_init(size_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
     return pyb_can_init_helper(args[0], n_args - 1, args + 1, kw_args);
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_KW(pyb_can_init_obj, 1, pyb_can_init);
@@ -455,7 +453,7 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_2(pyb_can_any_obj, pyb_can_any);
 ///   - `timeout` is the timeout in milliseconds to wait for the send.
 ///
 /// Return value: `None`.
-STATIC mp_obj_t pyb_can_send(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_can_send(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     static const mp_arg_t allowed_args[] = {
         { MP_QSTR_data,    MP_ARG_REQUIRED | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
         { MP_QSTR_id,      MP_ARG_REQUIRED | MP_ARG_INT, {.u_int = 0} },
@@ -515,7 +513,7 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_KW(pyb_can_send_obj, 1, pyb_can_send);
 ///   - `timeout` is the timeout in milliseconds to wait for the receive.
 ///
 /// Return value: buffer of data bytes.
-STATIC mp_obj_t pyb_can_recv(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_can_recv(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     static const mp_arg_t allowed_args[] = {
         { MP_QSTR_fifo,    MP_ARG_REQUIRED | MP_ARG_INT, {.u_int = 0} },
         { MP_QSTR_timeout, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 5000} },
@@ -528,7 +526,7 @@ STATIC mp_obj_t pyb_can_recv(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_
 
     // receive the data
     CanRxMsgTypeDef rx_msg;
-    self->can.pRxMsg = &rx_msg;
+    self->can.pRxMsg = self->can.pRx1Msg = &rx_msg;
     HAL_StatusTypeDef status = HAL_CAN_Receive(&self->can, args[0].u_int, args[1].u_int);
 
     if (status != HAL_OK) {
@@ -618,7 +616,7 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_2(pyb_can_clearfilter_obj, pyb_can_clearfilter);
 /// Configures a filterbank
 /// Return value: `None`.
 #define EXTENDED_ID_TO_16BIT_FILTER(id) (((id & 0xC00000) >> 13) | ((id & 0x38000) >> 15)) | 8
-STATIC mp_obj_t pyb_can_setfilter(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_can_setfilter(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     static const mp_arg_t allowed_args[] = {
         { MP_QSTR_bank,     MP_ARG_REQUIRED | MP_ARG_INT, {.u_int = 0} },
         { MP_QSTR_mode,     MP_ARG_REQUIRED | MP_ARG_INT, {.u_int = 0} },
diff --git a/stmhal/can.h b/ports/stm32/can.h
similarity index 100%
rename from stmhal/can.h
rename to ports/stm32/can.h
diff --git a/stmhal/dac.c b/ports/stm32/dac.c
similarity index 98%
rename from stmhal/dac.c
rename to ports/stm32/dac.c
index 14bd59b41a..268b1bcfb6 100644
--- a/stmhal/dac.c
+++ b/ports/stm32/dac.c
@@ -142,7 +142,7 @@ typedef struct _pyb_dac_obj_t {
     uint8_t state;
 } pyb_dac_obj_t;
 
-STATIC mp_obj_t pyb_dac_init_helper(pyb_dac_obj_t *self, mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_dac_init_helper(pyb_dac_obj_t *self, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     static const mp_arg_t allowed_args[] = {
         { MP_QSTR_bits, MP_ARG_INT, {.u_int = 8} },
     };
@@ -246,7 +246,7 @@ STATIC mp_obj_t pyb_dac_make_new(const mp_obj_type_t *type, size_t n_args, size_
     return dac;
 }
 
-STATIC mp_obj_t pyb_dac_init(mp_uint_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_dac_init(size_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
     return pyb_dac_init_helper(args[0], n_args - 1, args + 1, kw_args);
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_KW(pyb_dac_init_obj, 1, pyb_dac_init);
@@ -369,7 +369,7 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_2(pyb_dac_write_obj, pyb_dac_write);
 // and we can reuse the same timer for both DACs (and maybe also ADC) without
 // setting the freq twice.
 // Can still do 1-liner: dac.write_trig(buf, trig=Timer(6, freq=100), loop=True)
-mp_obj_t pyb_dac_write_timed(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+mp_obj_t pyb_dac_write_timed(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     static const mp_arg_t allowed_args[] = {
         { MP_QSTR_data, MP_ARG_REQUIRED | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
         { MP_QSTR_freq, MP_ARG_REQUIRED | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
diff --git a/stmhal/dac.h b/ports/stm32/dac.h
similarity index 100%
rename from stmhal/dac.h
rename to ports/stm32/dac.h
diff --git a/stmhal/dma.c b/ports/stm32/dma.c
similarity index 100%
rename from stmhal/dma.c
rename to ports/stm32/dma.c
diff --git a/stmhal/dma.h b/ports/stm32/dma.h
similarity index 100%
rename from stmhal/dma.h
rename to ports/stm32/dma.h
diff --git a/stmhal/extint.c b/ports/stm32/extint.c
similarity index 99%
rename from stmhal/extint.c
rename to ports/stm32/extint.c
index 24a68c2a22..41943f1cdb 100644
--- a/stmhal/extint.c
+++ b/ports/stm32/extint.c
@@ -83,7 +83,7 @@
 
 // TODO Add python method to change callback object.
 
-#define EXTI_OFFSET	(EXTI_BASE - PERIPH_BASE)
+#define EXTI_OFFSET (EXTI_BASE - PERIPH_BASE)
 
 // Macro used to set/clear the bit corresponding to the line in the IMR/EMR
 // register in an atomic fashion by using bitband addressing.
diff --git a/stmhal/extint.h b/ports/stm32/extint.h
similarity index 100%
rename from stmhal/extint.h
rename to ports/stm32/extint.h
diff --git a/stmhal/fatfs_port.c b/ports/stm32/fatfs_port.c
similarity index 100%
rename from stmhal/fatfs_port.c
rename to ports/stm32/fatfs_port.c
diff --git a/stmhal/flash.c b/ports/stm32/flash.c
similarity index 100%
rename from stmhal/flash.c
rename to ports/stm32/flash.c
diff --git a/stmhal/flash.h b/ports/stm32/flash.h
similarity index 100%
rename from stmhal/flash.h
rename to ports/stm32/flash.h
diff --git a/stmhal/font_petme128_8x8.h b/ports/stm32/font_petme128_8x8.h
similarity index 100%
rename from stmhal/font_petme128_8x8.h
rename to ports/stm32/font_petme128_8x8.h
diff --git a/stmhal/gccollect.c b/ports/stm32/gccollect.c
similarity index 99%
rename from stmhal/gccollect.c
rename to ports/stm32/gccollect.c
index 937fb6f36e..cdec2a136c 100644
--- a/stmhal/gccollect.c
+++ b/ports/stm32/gccollect.c
@@ -27,7 +27,6 @@
 #include <stdio.h>
 #include <stdint.h>
 
-#include "py/mpstate.h"
 #include "py/obj.h"
 #include "py/gc.h"
 #include "py/mpthread.h"
diff --git a/stmhal/gccollect.h b/ports/stm32/gccollect.h
similarity index 100%
rename from stmhal/gccollect.h
rename to ports/stm32/gccollect.h
diff --git a/stmhal/gchelper.s b/ports/stm32/gchelper.s
similarity index 100%
rename from stmhal/gchelper.s
rename to ports/stm32/gchelper.s
diff --git a/stmhal/help.c b/ports/stm32/help.c
similarity index 99%
rename from stmhal/help.c
rename to ports/stm32/help.c
index 87b2af526e..f9d97b70d6 100644
--- a/stmhal/help.c
+++ b/ports/stm32/help.c
@@ -26,7 +26,7 @@
 
 #include "py/builtin.h"
 
-const char *stmhal_help_text =
+const char stm32_help_text[] =
 "Welcome to MicroPython!\n"
 "\n"
 "For online help please visit http://micropython.org/help/.\n"
diff --git a/stmhal/i2c.c b/ports/stm32/i2c.c
similarity index 97%
rename from stmhal/i2c.c
rename to ports/stm32/i2c.c
index 48a1e49af8..b22787cab5 100644
--- a/stmhal/i2c.c
+++ b/ports/stm32/i2c.c
@@ -27,7 +27,6 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "py/nlr.h"
 #include "py/runtime.h"
 #include "py/mphal.h"
 #include "irq.h"
@@ -552,7 +551,7 @@ STATIC void pyb_i2c_print(const mp_print_t *print, mp_obj_t self_in, mp_print_ki
 ///   - `addr` is the 7-bit address (only sensible for a slave)
 ///   - `baudrate` is the SCL clock rate (only sensible for a master)
 ///   - `gencall` is whether to support general call mode
-STATIC mp_obj_t pyb_i2c_init_helper(const pyb_i2c_obj_t *self, mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_i2c_init_helper(const pyb_i2c_obj_t *self, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     static const mp_arg_t allowed_args[] = {
         { MP_QSTR_mode,     MP_ARG_INT, {.u_int = PYB_I2C_MASTER} },
         { MP_QSTR_addr,     MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0x12} },
@@ -650,7 +649,7 @@ STATIC mp_obj_t pyb_i2c_make_new(const mp_obj_type_t *type, size_t n_args, size_
     return (mp_obj_t)i2c_obj;
 }
 
-STATIC mp_obj_t pyb_i2c_init(mp_uint_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_i2c_init(size_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
     return pyb_i2c_init_helper(args[0], n_args - 1, args + 1, kw_args);
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_KW(pyb_i2c_init_obj, 1, pyb_i2c_init);
@@ -699,12 +698,9 @@ STATIC mp_obj_t pyb_i2c_scan(mp_obj_t self_in) {
     mp_obj_t list = mp_obj_new_list(0, NULL);
 
     for (uint addr = 0x08; addr <= 0x77; addr++) {
-        for (int i = 0; i < 10; i++) {
-            HAL_StatusTypeDef status = HAL_I2C_IsDeviceReady(self->i2c, addr << 1, 10, 200);
-            if (status == HAL_OK) {
-                mp_obj_list_append(list, mp_obj_new_int(addr));
-                break;
-            }
+        HAL_StatusTypeDef status = HAL_I2C_IsDeviceReady(self->i2c, addr << 1, 1, 200);
+        if (status == HAL_OK) {
+            mp_obj_list_append(list, MP_OBJ_NEW_SMALL_INT(addr));
         }
     }
 
@@ -720,7 +716,7 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_i2c_scan_obj, pyb_i2c_scan);
 ///   - `timeout` is the timeout in milliseconds to wait for the send
 ///
 /// Return value: `None`.
-STATIC mp_obj_t pyb_i2c_send(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_i2c_send(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     static const mp_arg_t allowed_args[] = {
         { MP_QSTR_send,    MP_ARG_REQUIRED | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
         { MP_QSTR_addr,    MP_ARG_INT, {.u_int = PYB_I2C_MASTER_ADDRESS} },
@@ -800,7 +796,7 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_KW(pyb_i2c_send_obj, 1, pyb_i2c_send);
 ///
 /// Return value: if `recv` is an integer then a new buffer of the bytes received,
 /// otherwise the same buffer that was passed in to `recv`.
-STATIC mp_obj_t pyb_i2c_recv(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_i2c_recv(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     static const mp_arg_t allowed_args[] = {
         { MP_QSTR_recv,    MP_ARG_REQUIRED | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
         { MP_QSTR_addr,    MP_ARG_INT, {.u_int = PYB_I2C_MASTER_ADDRESS} },
@@ -890,7 +886,7 @@ STATIC const mp_arg_t pyb_i2c_mem_read_allowed_args[] = {
     { MP_QSTR_addr_size, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 8} },
 };
 
-STATIC mp_obj_t pyb_i2c_mem_read(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_i2c_mem_read(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     // parse args
     pyb_i2c_obj_t *self = pos_args[0];
     mp_arg_val_t args[MP_ARRAY_SIZE(pyb_i2c_mem_read_allowed_args)];
@@ -958,7 +954,7 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_KW(pyb_i2c_mem_read_obj, 1, pyb_i2c_mem_read);
 ///
 /// Returns `None`.
 /// This is only valid in master mode.
-STATIC mp_obj_t pyb_i2c_mem_write(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_i2c_mem_write(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     // parse args (same as mem_read)
     pyb_i2c_obj_t *self = pos_args[0];
     mp_arg_val_t args[MP_ARRAY_SIZE(pyb_i2c_mem_read_allowed_args)];
diff --git a/stmhal/i2c.h b/ports/stm32/i2c.h
similarity index 100%
rename from stmhal/i2c.h
rename to ports/stm32/i2c.h
diff --git a/stmhal/irq.c b/ports/stm32/irq.c
similarity index 99%
rename from stmhal/irq.c
rename to ports/stm32/irq.c
index d6db8e83d8..7298a4b504 100644
--- a/stmhal/irq.c
+++ b/ports/stm32/irq.c
@@ -24,7 +24,6 @@
  * THE SOFTWARE.
  */
 
-#include "py/nlr.h"
 #include "py/obj.h"
 #include "py/mphal.h"
 #include "irq.h"
diff --git a/stmhal/irq.h b/ports/stm32/irq.h
similarity index 100%
rename from stmhal/irq.h
rename to ports/stm32/irq.h
diff --git a/stmhal/lcd.c b/ports/stm32/lcd.c
similarity index 99%
rename from stmhal/lcd.c
rename to ports/stm32/lcd.c
index 7368193cf8..488df1699c 100644
--- a/stmhal/lcd.c
+++ b/ports/stm32/lcd.c
@@ -28,7 +28,6 @@
 #include <string.h>
 
 #include "py/mphal.h"
-#include "py/nlr.h"
 #include "py/runtime.h"
 
 #if MICROPY_HW_HAS_LCD
@@ -421,7 +420,7 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_3(pyb_lcd_get_obj, pyb_lcd_get);
 /// Set the pixel at `(x, y)` to the given colour (0 or 1).
 ///
 /// This method writes to the hidden buffer.  Use `show()` to show the buffer.
-STATIC mp_obj_t pyb_lcd_pixel(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t pyb_lcd_pixel(size_t n_args, const mp_obj_t *args) {
     pyb_lcd_obj_t *self = args[0];
     int x = mp_obj_get_int(args[1]);
     int y = mp_obj_get_int(args[2]);
@@ -442,7 +441,7 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_lcd_pixel_obj, 4, 4, pyb_lcd_pixe
 /// Draw the given text to the position `(x, y)` using the given colour (0 or 1).
 ///
 /// This method writes to the hidden buffer.  Use `show()` to show the buffer.
-STATIC mp_obj_t pyb_lcd_text(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t pyb_lcd_text(size_t n_args, const mp_obj_t *args) {
     // extract arguments
     pyb_lcd_obj_t *self = args[0];
     size_t len;
diff --git a/stmhal/lcd.h b/ports/stm32/lcd.h
similarity index 100%
rename from stmhal/lcd.h
rename to ports/stm32/lcd.h
diff --git a/stmhal/led.c b/ports/stm32/led.c
similarity index 99%
rename from stmhal/led.c
rename to ports/stm32/led.c
index 030a814dd6..9bbcaa6b30 100644
--- a/stmhal/led.c
+++ b/ports/stm32/led.c
@@ -26,7 +26,6 @@
 
 #include <stdio.h>
 
-#include "py/nlr.h"
 #include "py/runtime.h"
 #include "py/mphal.h"
 #include "timer.h"
@@ -334,7 +333,7 @@ mp_obj_t led_obj_toggle(mp_obj_t self_in) {
 /// Get or set the LED intensity.  Intensity ranges between 0 (off) and 255 (full on).
 /// If no argument is given, return the LED intensity.
 /// If an argument is given, set the LED intensity and return `None`.
-mp_obj_t led_obj_intensity(mp_uint_t n_args, const mp_obj_t *args) {
+mp_obj_t led_obj_intensity(size_t n_args, const mp_obj_t *args) {
     pyb_led_obj_t *self = args[0];
     if (n_args == 1) {
         return mp_obj_new_int(led_get_intensity(self->led_id));
diff --git a/stmhal/led.h b/ports/stm32/led.h
similarity index 100%
rename from stmhal/led.h
rename to ports/stm32/led.h
diff --git a/stmhal/machine_i2c.c b/ports/stm32/machine_i2c.c
similarity index 100%
rename from stmhal/machine_i2c.c
rename to ports/stm32/machine_i2c.c
diff --git a/stmhal/main.c b/ports/stm32/main.c
similarity index 99%
rename from stmhal/main.c
rename to ports/stm32/main.c
index 056c590cda..16279d073d 100644
--- a/stmhal/main.c
+++ b/ports/stm32/main.c
@@ -112,7 +112,7 @@ void MP_WEAK __assert_func(const char *file, int line, const char *func, const c
 }
 #endif
 
-STATIC mp_obj_t pyb_main(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_main(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     static const mp_arg_t allowed_args[] = {
         { MP_QSTR_opt, MP_ARG_INT, {.u_int = 0} }
     };
diff --git a/stmhal/make-stmconst.py b/ports/stm32/make-stmconst.py
similarity index 96%
rename from stmhal/make-stmconst.py
rename to ports/stm32/make-stmconst.py
index 0b5666b9cc..3a8e22b386 100644
--- a/stmhal/make-stmconst.py
+++ b/ports/stm32/make-stmconst.py
@@ -1,10 +1,7 @@
 """
-Read in the cmsis/devinc/stm32f405xx.h header, extract relevant constants,
-and create modstmconst.c.
-
-This is not part of the automatic build process because stm32f405xx.h isn't
-expected to change.  After generating the file, some manual intervention is
-needed to copy the new qstr definitions to qstrdefsport.h.
+This script reads in the given CMSIS device include file (eg stm32f405xx.h),
+extracts relevant peripheral constants, and creates qstrs, mpz's and constants
+for the stm module.
 """
 
 from __future__ import print_function
@@ -254,7 +251,7 @@ def main():
         for mpz in sorted(needed_mpzs):
             assert 0 <= mpz <= 0xffffffff
             print('STATIC const mp_obj_int_t mpz_%08x = {{&mp_type_int}, '
-                '{.neg=0, .fixed_dig=1, .alloc=2, .len=2, ' '.dig=(uint16_t[]){%#x, %#x}}};'
+                '{.neg=0, .fixed_dig=1, .alloc=2, .len=2, ' '.dig=(uint16_t*)(const uint16_t[]){%#x, %#x}}};'
                 % (mpz, mpz & 0xffff, (mpz >> 16) & 0xffff), file=mpz_file)
 
 if __name__ == "__main__":
diff --git a/stmhal/modmachine.c b/ports/stm32/modmachine.c
similarity index 88%
rename from stmhal/modmachine.c
rename to ports/stm32/modmachine.c
index cb7957681d..8c59758fa3 100644
--- a/stmhal/modmachine.c
+++ b/ports/stm32/modmachine.c
@@ -52,12 +52,9 @@
 #include "spi.h"
 #include "uart.h"
 #include "wdt.h"
+#include "genhdr/pllfreqtable.h"
 
-#if defined(MCU_SERIES_F4)
-// the HAL does not define these constants
-#define RCC_CSR_IWDGRSTF (0x20000000)
-#define RCC_CSR_PINRSTF (0x04000000)
-#elif defined(MCU_SERIES_L4)
+#if defined(MCU_SERIES_L4)
 // L4 does not have a POR, so use BOR instead
 #define RCC_CSR_PORRSTF RCC_CSR_BORRSTF
 #endif
@@ -77,6 +74,12 @@ void machine_init(void) {
         reset_cause = PYB_RESET_DEEPSLEEP;
         PWR->CR |= PWR_CR_CSBF;
     } else
+    #elif defined(MCU_SERIES_F7)
+    if (PWR->CSR1 & PWR_CSR1_SBF) {
+        // came out of standby
+        reset_cause = PYB_RESET_DEEPSLEEP;
+        PWR->CR1 |= PWR_CR1_CSBF;
+    } else
     #endif
     {
         // get reset cause from RCC flags
@@ -98,7 +101,7 @@ void machine_init(void) {
 
 // machine.info([dump_alloc_table])
 // Print out lots of information about the board.
-STATIC mp_obj_t machine_info(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t machine_info(size_t n_args, const mp_obj_t *args) {
     // get and print unique id; 96 bits
     {
         byte *id = (byte*)MP_HAL_UNIQUE_ID_ADDRESS;
@@ -202,6 +205,11 @@ STATIC NORETURN mp_obj_t machine_bootloader(void) {
     HAL_RCC_DeInit();
     HAL_DeInit();
 
+    #if (__MPU_PRESENT == 1)
+    // MPU must be disabled for bootloader to function correctly
+    HAL_MPU_Disable();
+    #endif
+
 #if defined(MCU_SERIES_F7)
     // arm-none-eabi-gcc 4.9.0 does not correctly inline this
     // MSP function, so we write it out explicitly here.
@@ -243,7 +251,7 @@ STATIC mp_uint_t machine_freq_calc_apb_div(mp_uint_t wanted_div) {
     else if (wanted_div <= 8) { return RCC_HCLK_DIV8; }
     else { return RCC_SYSCLK_DIV16; }
 }
-STATIC mp_obj_t machine_freq(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t machine_freq(size_t n_args, const mp_obj_t *args) {
     if (n_args == 0) {
         // get
         mp_obj_t tuple[4] = {
@@ -265,61 +273,31 @@ STATIC mp_obj_t machine_freq(mp_uint_t n_args, const mp_obj_t *args) {
         uint32_t m = HSE_VALUE / 1000000, n = 336, p = 2, q = 7;
         uint32_t sysclk_source;
 
-        // the following logic assumes HSE < HSI
-        if (HSE_VALUE / 1000000 <= wanted_sysclk && wanted_sysclk < HSI_VALUE / 1000000) {
-            // use HSE as SYSCLK
-            sysclk_source = RCC_SYSCLKSOURCE_HSE;
-        } else if (HSI_VALUE / 1000000 <= wanted_sysclk && wanted_sysclk < 24) {
-            // use HSI as SYSCLK
-            sysclk_source = RCC_SYSCLKSOURCE_HSI;
-        } else {
-            // search for a valid PLL configuration that keeps USB at 48MHz
-            for (; wanted_sysclk > 0; wanted_sysclk--) {
-                for (p = 2; p <= 8; p += 2) {
-                    // compute VCO_OUT
-                    mp_uint_t vco_out = wanted_sysclk * p;
-                    // make sure VCO_OUT is between 192MHz and 432MHz
-                    if (vco_out < 192 || vco_out > 432) {
-                        continue;
-                    }
-                    // make sure Q is an integer
-                    if (vco_out % 48 != 0) {
-                        continue;
-                    }
-                    // solve for Q to get PLL48CK at 48MHz
-                    q = vco_out / 48;
-                    // make sure Q is in range
-                    if (q < 2 || q > 15) {
-                        continue;
-                    }
-                    // make sure N/M is an integer
-                    if (vco_out % (HSE_VALUE / 1000000) != 0) {
-                        continue;
-                    }
-                    // solve for N/M
-                    mp_uint_t n_by_m = vco_out / (HSE_VALUE / 1000000);
-                    // solve for M, making sure VCO_IN (=HSE/M) is between 1MHz and 2MHz
-                    m = 192 / n_by_m;
-                    while (m < (HSE_VALUE / 2000000) || n_by_m * m < 192) {
-                        m += 1;
-                    }
-                    if (m > (HSE_VALUE / 1000000)) {
-                        continue;
-                    }
-                    // solve for N
-                    n = n_by_m * m;
-                    // make sure N is in range
-                    if (n < 192 || n > 432) {
-                        continue;
-                    }
-
-                    // found values!
+        // search for a valid PLL configuration that keeps USB at 48MHz
+        for (const uint16_t *pll = &pll_freq_table[MP_ARRAY_SIZE(pll_freq_table) - 1]; pll >= &pll_freq_table[0]; --pll) {
+            uint32_t sys = *pll & 0xff;
+            if (sys <= wanted_sysclk) {
+                m = (*pll >> 10) & 0x3f;
+                p = ((*pll >> 7) & 0x6) + 2;
+                if (m == 0) {
+                    // special entry for using HSI directly
+                    sysclk_source = RCC_SYSCLKSOURCE_HSI;
+                    goto set_clk;
+                } else if (m == 1) {
+                    // special entry for using HSE directly
+                    sysclk_source = RCC_SYSCLKSOURCE_HSE;
+                    goto set_clk;
+                } else {
+                    // use PLL
                     sysclk_source = RCC_SYSCLKSOURCE_PLLCLK;
+                    uint32_t vco_out = sys * p;
+                    n = vco_out * m / (HSE_VALUE / 1000000);
+                    q = vco_out / 48;
                     goto set_clk;
                 }
             }
-            mp_raise_ValueError("can't make valid freq");
         }
+        mp_raise_ValueError("can't make valid freq");
 
     set_clk:
         //printf("%lu %lu %lu %lu %lu\n", sysclk_source, m, n, p, q);
@@ -381,6 +359,21 @@ STATIC mp_obj_t machine_freq(mp_uint_t n_args, const mp_obj_t *args) {
 
         // set PLL as system clock source if wanted
         if (sysclk_source == RCC_SYSCLKSOURCE_PLLCLK) {
+            #if defined(MCU_SERIES_F7)
+            // if possible, scale down the internal voltage regulator to save power
+            uint32_t volt_scale;
+            if (wanted_sysclk <= 151000000) {
+                volt_scale = PWR_REGULATOR_VOLTAGE_SCALE3;
+            } else if (wanted_sysclk <= 180000000) {
+                volt_scale = PWR_REGULATOR_VOLTAGE_SCALE2;
+            } else {
+                volt_scale = PWR_REGULATOR_VOLTAGE_SCALE1;
+            }
+            if (HAL_PWREx_ControlVoltageScaling(volt_scale) != HAL_OK) {
+                goto fail;
+            }
+            #endif
+
             #if !defined(MICROPY_HW_FLASH_LATENCY)
             #define MICROPY_HW_FLASH_LATENCY FLASH_LATENCY_5
             #endif
@@ -450,7 +443,11 @@ STATIC mp_obj_t machine_sleep(void) {
     // takes longer to wake but reduces stop current
     HAL_PWREx_EnableFlashPowerDown();
 
+    # if defined(MCU_SERIES_F7)
+    HAL_PWR_EnterSTOPMode((PWR_CR1_LPDS | PWR_CR1_LPUDS | PWR_CR1_FPDS | PWR_CR1_UDEN), PWR_STOPENTRY_WFI);
+    # else
     HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
+    #endif
 
     // reconfigure the system clock after waking up
 
@@ -478,7 +475,7 @@ MP_DEFINE_CONST_FUN_OBJ_0(machine_sleep_obj, machine_sleep);
 STATIC mp_obj_t machine_deepsleep(void) {
     rtc_init_finalise();
 
-#if defined(MCU_SERIES_F7) || defined(MCU_SERIES_L4)
+#if defined(MCU_SERIES_L4)
     printf("machine.deepsleep not supported yet\n");
 #else
     // We need to clear the PWR wake-up-flag before entering standby, since
@@ -500,8 +497,15 @@ STATIC mp_obj_t machine_deepsleep(void) {
     // clear RTC wake-up flags
     RTC->ISR &= ~(RTC_ISR_ALRAF | RTC_ISR_ALRBF | RTC_ISR_WUTF | RTC_ISR_TSF);
 
+    #if defined(MCU_SERIES_F7)
+    // disable wake-up flags
+    PWR->CSR2 &= ~(PWR_CSR2_EWUP6 | PWR_CSR2_EWUP5 | PWR_CSR2_EWUP4 | PWR_CSR2_EWUP3 | PWR_CSR2_EWUP2 | PWR_CSR2_EWUP1);
+    // clear global wake-up flag
+    PWR->CR2 |= PWR_CR2_CWUPF6 | PWR_CR2_CWUPF5 | PWR_CR2_CWUPF4 | PWR_CR2_CWUPF3 | PWR_CR2_CWUPF2 | PWR_CR2_CWUPF1;
+    #else
     // clear global wake-up flag
     PWR->CR |= PWR_CR_CWUF;
+    #endif
 
     // enable previously-enabled RTC interrupts
     RTC->CR |= save_irq_bits;
diff --git a/stmhal/modmachine.h b/ports/stm32/modmachine.h
similarity index 97%
rename from stmhal/modmachine.h
rename to ports/stm32/modmachine.h
index ac39f854ed..77668695fc 100644
--- a/stmhal/modmachine.h
+++ b/ports/stm32/modmachine.h
@@ -26,8 +26,6 @@
 #ifndef MICROPY_INCLUDED_STMHAL_MODMACHINE_H
 #define MICROPY_INCLUDED_STMHAL_MODMACHINE_H
 
-#include "py/mpstate.h"
-#include "py/nlr.h"
 #include "py/obj.h"
 
 void machine_init(void);
diff --git a/stmhal/modnetwork.c b/ports/stm32/modnetwork.c
similarity index 99%
rename from stmhal/modnetwork.c
rename to ports/stm32/modnetwork.c
index 6b4949a0de..6421745325 100644
--- a/stmhal/modnetwork.c
+++ b/ports/stm32/modnetwork.c
@@ -28,7 +28,6 @@
 #include <stdint.h>
 #include <string.h>
 
-#include "py/nlr.h"
 #include "py/objlist.h"
 #include "py/runtime.h"
 #include "modnetwork.h"
diff --git a/stmhal/modnetwork.h b/ports/stm32/modnetwork.h
similarity index 100%
rename from stmhal/modnetwork.h
rename to ports/stm32/modnetwork.h
diff --git a/stmhal/modnwcc3k.c b/ports/stm32/modnwcc3k.c
similarity index 99%
rename from stmhal/modnwcc3k.c
rename to ports/stm32/modnwcc3k.c
index d893a231dd..551206da8e 100644
--- a/stmhal/modnwcc3k.c
+++ b/ports/stm32/modnwcc3k.c
@@ -30,8 +30,6 @@
 // CC3000 defines its own ENOBUFS (different to standard one!)
 #undef ENOBUFS
 
-#include "py/ioctl.h"
-#include "py/nlr.h"
 #include "py/objtuple.h"
 #include "py/objlist.h"
 #include "py/stream.h"
@@ -465,7 +463,7 @@ STATIC mp_obj_t cc3k_make_new(const mp_obj_type_t *type, size_t n_args, size_t n
 }
 
 // method connect(ssid, key=None, *, security=WPA2, bssid=None)
-STATIC mp_obj_t cc3k_connect(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t cc3k_connect(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     static const mp_arg_t allowed_args[] = {
         { MP_QSTR_ssid, MP_ARG_REQUIRED | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
         { MP_QSTR_key, MP_ARG_OBJ, {.u_obj = mp_const_none} },
diff --git a/stmhal/modnwwiznet5k.c b/ports/stm32/modnwwiznet5k.c
similarity index 97%
rename from stmhal/modnwwiznet5k.c
rename to ports/stm32/modnwwiznet5k.c
index eb7eb84438..21e4dbbbf4 100644
--- a/stmhal/modnwwiznet5k.c
+++ b/ports/stm32/modnwwiznet5k.c
@@ -28,7 +28,6 @@
 #include <stdint.h>
 #include <string.h>
 
-#include "py/nlr.h"
 #include "py/objlist.h"
 #include "py/runtime.h"
 #include "py/mperrno.h"
@@ -213,7 +212,10 @@ STATIC int wiznet5k_socket_connect(mod_network_socket_obj_t *socket, byte *ip, m
     }
 
     // now connect
+    MP_THREAD_GIL_EXIT();
     mp_int_t ret = WIZCHIP_EXPORT(connect)(socket->u_param.fileno, ip, port);
+    MP_THREAD_GIL_ENTER();
+
     if (ret < 0) {
         wiznet5k_socket_close(socket);
         *_errno = -ret;
@@ -225,7 +227,10 @@ STATIC int wiznet5k_socket_connect(mod_network_socket_obj_t *socket, byte *ip, m
 }
 
 STATIC mp_uint_t wiznet5k_socket_send(mod_network_socket_obj_t *socket, const byte *buf, mp_uint_t len, int *_errno) {
+    MP_THREAD_GIL_EXIT();
     mp_int_t ret = WIZCHIP_EXPORT(send)(socket->u_param.fileno, (byte*)buf, len);
+    MP_THREAD_GIL_ENTER();
+
     // TODO convert Wiz errno's to POSIX ones
     if (ret < 0) {
         wiznet5k_socket_close(socket);
@@ -236,7 +241,10 @@ STATIC mp_uint_t wiznet5k_socket_send(mod_network_socket_obj_t *socket, const by
 }
 
 STATIC mp_uint_t wiznet5k_socket_recv(mod_network_socket_obj_t *socket, byte *buf, mp_uint_t len, int *_errno) {
+    MP_THREAD_GIL_EXIT();
     mp_int_t ret = WIZCHIP_EXPORT(recv)(socket->u_param.fileno, buf, len);
+    MP_THREAD_GIL_ENTER();
+
     // TODO convert Wiz errno's to POSIX ones
     if (ret < 0) {
         wiznet5k_socket_close(socket);
@@ -254,7 +262,10 @@ STATIC mp_uint_t wiznet5k_socket_sendto(mod_network_socket_obj_t *socket, const
         }
     }
 
+    MP_THREAD_GIL_EXIT();
     mp_int_t ret = WIZCHIP_EXPORT(sendto)(socket->u_param.fileno, (byte*)buf, len, ip, port);
+    MP_THREAD_GIL_ENTER();
+
     if (ret < 0) {
         wiznet5k_socket_close(socket);
         *_errno = -ret;
@@ -265,7 +276,9 @@ STATIC mp_uint_t wiznet5k_socket_sendto(mod_network_socket_obj_t *socket, const
 
 STATIC mp_uint_t wiznet5k_socket_recvfrom(mod_network_socket_obj_t *socket, byte *buf, mp_uint_t len, byte *ip, mp_uint_t *port, int *_errno) {
     uint16_t port2;
+    MP_THREAD_GIL_EXIT();
     mp_int_t ret = WIZCHIP_EXPORT(recvfrom)(socket->u_param.fileno, buf, len, ip, &port2);
+    MP_THREAD_GIL_ENTER();
     *port = port2;
     if (ret < 0) {
         wiznet5k_socket_close(socket);
@@ -407,7 +420,7 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_1(wiznet5k_regs_obj, wiznet5k_regs);
 
 /// \method ifconfig([(ip, subnet, gateway, dns)])
 /// Get/set IP address, subnet mask, gateway and DNS.
-STATIC mp_obj_t wiznet5k_ifconfig(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t wiznet5k_ifconfig(size_t n_args, const mp_obj_t *args) {
     wiz_NetInfo netinfo;
     ctlnetwork(CN_GET_NETINFO, &netinfo);
     if (n_args == 1) {
diff --git a/stmhal/modpyb.c b/ports/stm32/modpyb.c
similarity index 99%
rename from stmhal/modpyb.c
rename to ports/stm32/modpyb.c
index 5dc28e1325..176fc84663 100644
--- a/stmhal/modpyb.c
+++ b/ports/stm32/modpyb.c
@@ -27,8 +27,6 @@
 #include <stdint.h>
 #include <stdio.h>
 
-#include "py/mpstate.h"
-#include "py/nlr.h"
 #include "py/obj.h"
 #include "py/gc.h"
 #include "py/builtin.h"
diff --git a/stmhal/modstm.c b/ports/stm32/modstm.c
similarity index 100%
rename from stmhal/modstm.c
rename to ports/stm32/modstm.c
diff --git a/ports/stm32/modules/lcd160cr.py b/ports/stm32/modules/lcd160cr.py
new file mode 120000
index 0000000000..9e63f1d23f
--- /dev/null
+++ b/ports/stm32/modules/lcd160cr.py
@@ -0,0 +1 @@
+../../../drivers/display/lcd160cr.py
\ No newline at end of file
diff --git a/ports/stm32/modules/lcd160cr_test.py b/ports/stm32/modules/lcd160cr_test.py
new file mode 120000
index 0000000000..5f5bcc1281
--- /dev/null
+++ b/ports/stm32/modules/lcd160cr_test.py
@@ -0,0 +1 @@
+../../../drivers/display/lcd160cr_test.py
\ No newline at end of file
diff --git a/ports/stm32/modules/onewire.py b/ports/stm32/modules/onewire.py
new file mode 120000
index 0000000000..33f30e84f1
--- /dev/null
+++ b/ports/stm32/modules/onewire.py
@@ -0,0 +1 @@
+../../../drivers/onewire/onewire.py
\ No newline at end of file
diff --git a/stmhal/moduos.c b/ports/stm32/moduos.c
similarity index 98%
rename from stmhal/moduos.c
rename to ports/stm32/moduos.c
index e02f6aefa8..f661b3b5e0 100644
--- a/stmhal/moduos.c
+++ b/ports/stm32/moduos.c
@@ -27,7 +27,6 @@
 #include <stdint.h>
 #include <string.h>
 
-#include "py/mpstate.h"
 #include "py/runtime.h"
 #include "py/objtuple.h"
 #include "py/objstr.h"
@@ -108,7 +107,7 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_1(os_urandom_obj, os_urandom);
 
 // Get or set the UART object that the REPL is repeated on.
 // TODO should accept any object with read/write methods.
-STATIC mp_obj_t os_dupterm(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t os_dupterm(size_t n_args, const mp_obj_t *args) {
     if (n_args == 0) {
         if (MP_STATE_PORT(pyb_stdio_uart) == NULL) {
             return mp_const_none;
diff --git a/stmhal/modusocket.c b/ports/stm32/modusocket.c
similarity index 99%
rename from stmhal/modusocket.c
rename to ports/stm32/modusocket.c
index e1da53a4b3..c5ab3b6d79 100644
--- a/stmhal/modusocket.c
+++ b/ports/stm32/modusocket.c
@@ -27,7 +27,6 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "py/nlr.h"
 #include "py/objtuple.h"
 #include "py/objlist.h"
 #include "py/runtime.h"
@@ -280,7 +279,7 @@ STATIC mp_obj_t socket_recvfrom(mp_obj_t self_in, mp_obj_t len_in) {
 STATIC MP_DEFINE_CONST_FUN_OBJ_2(socket_recvfrom_obj, socket_recvfrom);
 
 // method socket.setsockopt(level, optname, value)
-STATIC mp_obj_t socket_setsockopt(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t socket_setsockopt(size_t n_args, const mp_obj_t *args) {
     mod_network_socket_obj_t *self = args[0];
 
     mp_int_t level = mp_obj_get_int(args[1]);
diff --git a/stmhal/modutime.c b/ports/stm32/modutime.c
similarity index 98%
rename from stmhal/modutime.c
rename to ports/stm32/modutime.c
index fe13f80c06..54045f4c5c 100644
--- a/stmhal/modutime.c
+++ b/ports/stm32/modutime.c
@@ -53,7 +53,7 @@
 /// second  is 0-59
 /// weekday is 0-6 for Mon-Sun.
 /// yearday is 1-366
-STATIC mp_obj_t time_localtime(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t time_localtime(size_t n_args, const mp_obj_t *args) {
     if (n_args == 0 || args[0] == mp_const_none) {
         // get current date and time
         // note: need to call get time then get date to correctly access the registers
diff --git a/stmhal/mpconfigport.h b/ports/stm32/mpconfigport.h
similarity index 96%
rename from stmhal/mpconfigport.h
rename to ports/stm32/mpconfigport.h
index 326aa2c20a..7888b5355d 100644
--- a/stmhal/mpconfigport.h
+++ b/ports/stm32/mpconfigport.h
@@ -92,7 +92,7 @@
 #define MICROPY_PY_BUILTINS_INPUT   (1)
 #define MICROPY_PY_BUILTINS_POW3    (1)
 #define MICROPY_PY_BUILTINS_HELP    (1)
-#define MICROPY_PY_BUILTINS_HELP_TEXT stmhal_help_text
+#define MICROPY_PY_BUILTINS_HELP_TEXT stm32_help_text
 #define MICROPY_PY_BUILTINS_HELP_MODULES (1)
 #define MICROPY_PY_MICROPYTHON_MEM_INFO (1)
 #define MICROPY_PY_ARRAY_SLICE_ASSIGN (1)
@@ -232,9 +232,15 @@ extern const struct _mp_obj_module_t mp_module_onewire;
 
 #if defined(MCU_SERIES_F7)
 #define PYB_EXTI_NUM_VECTORS (24)
+#define MICROPY_HW_MAX_TIMER (17)
 #define MICROPY_HW_MAX_UART (8)
+#elif defined(MCU_SERIES_L4)
+#define PYB_EXTI_NUM_VECTORS (23)
+#define MICROPY_HW_MAX_TIMER (17)
+#define MICROPY_HW_MAX_UART (6)
 #else
 #define PYB_EXTI_NUM_VECTORS (23)
+#define MICROPY_HW_MAX_TIMER (14)
 #define MICROPY_HW_MAX_UART (6)
 #endif
 
@@ -254,8 +260,8 @@ extern const struct _mp_obj_module_t mp_module_onewire;
     \
     mp_obj_t pyb_extint_callback[PYB_EXTI_NUM_VECTORS]; \
     \
-    /* Used to do callbacks to Python code on interrupt */ \
-    struct _pyb_timer_obj_t *pyb_timer_obj_all[14]; \
+    /* pointers to all Timer objects (if they have been created) */ \
+    struct _pyb_timer_obj_t *pyb_timer_obj_all[MICROPY_HW_MAX_TIMER]; \
     \
     /* stdio is repeated on this UART object if it's not null */ \
     struct _pyb_uart_obj_t *pyb_stdio_uart; \
@@ -345,4 +351,4 @@ static inline mp_uint_t disable_irq(void) {
 // We need to provide a declaration/definition of alloca()
 #include <alloca.h>
 
-#define MICROPY_PIN_DEFS_PORT_H "pin_defs_stmhal.h"
+#define MICROPY_PIN_DEFS_PORT_H "pin_defs_stm32.h"
diff --git a/stmhal/mpconfigport.mk b/ports/stm32/mpconfigport.mk
similarity index 100%
rename from stmhal/mpconfigport.mk
rename to ports/stm32/mpconfigport.mk
diff --git a/stmhal/mphalport.c b/ports/stm32/mphalport.c
similarity index 99%
rename from stmhal/mphalport.c
rename to ports/stm32/mphalport.c
index dff781ff29..ab3dc227a6 100644
--- a/stmhal/mphalport.c
+++ b/ports/stm32/mphalport.c
@@ -1,6 +1,5 @@
 #include <string.h>
 
-#include "py/mpstate.h"
 #include "py/runtime.h"
 #include "py/mperrno.h"
 #include "py/mphal.h"
diff --git a/stmhal/mphalport.h b/ports/stm32/mphalport.h
similarity index 98%
rename from stmhal/mphalport.h
rename to ports/stm32/mphalport.h
index 8dd95c470c..939df0b3d2 100644
--- a/stmhal/mphalport.h
+++ b/ports/stm32/mphalport.h
@@ -27,7 +27,7 @@ void mp_hal_set_interrupt_char(int c); // -1 to disable
 
 // timing functions
 
-#include "stmhal/irq.h"
+#include "irq.h"
 
 #define mp_hal_quiet_timing_enter() raise_irq_pri(1)
 #define mp_hal_quiet_timing_exit(irq_state) restore_irq_pri(irq_state)
@@ -44,7 +44,7 @@ static inline mp_uint_t mp_hal_ticks_cpu(void) {
 
 // C-level pin HAL
 
-#include "stmhal/pin.h"
+#include "pin.h"
 
 #define MP_HAL_PIN_FMT                  "%q"
 #define MP_HAL_PIN_MODE_INPUT           (0)
diff --git a/stmhal/mpthreadport.c b/ports/stm32/mpthreadport.c
similarity index 98%
rename from stmhal/mpthreadport.c
rename to ports/stm32/mpthreadport.c
index d7c5b569bb..11653b24cf 100644
--- a/stmhal/mpthreadport.c
+++ b/ports/stm32/mpthreadport.c
@@ -26,8 +26,6 @@
 
 #include <stdio.h>
 
-#include "py/mpconfig.h"
-#include "py/mpstate.h"
 #include "py/gc.h"
 #include "py/mpthread.h"
 #include "gccollect.h"
diff --git a/stmhal/mpthreadport.h b/ports/stm32/mpthreadport.h
similarity index 100%
rename from stmhal/mpthreadport.h
rename to ports/stm32/mpthreadport.h
diff --git a/stmhal/pendsv.c b/ports/stm32/pendsv.c
similarity index 99%
rename from stmhal/pendsv.c
rename to ports/stm32/pendsv.c
index 00ea12f460..0aeb1a6dcf 100644
--- a/stmhal/pendsv.c
+++ b/ports/stm32/pendsv.c
@@ -26,7 +26,6 @@
 
 #include <stdlib.h>
 
-#include "py/mpstate.h"
 #include "py/runtime.h"
 #include "lib/utils/interrupt_char.h"
 #include "pendsv.h"
diff --git a/stmhal/pendsv.h b/ports/stm32/pendsv.h
similarity index 100%
rename from stmhal/pendsv.h
rename to ports/stm32/pendsv.h
diff --git a/stmhal/pin.c b/ports/stm32/pin.c
similarity index 97%
rename from stmhal/pin.c
rename to ports/stm32/pin.c
index 8d4e800223..ee2d846469 100644
--- a/stmhal/pin.c
+++ b/ports/stm32/pin.c
@@ -28,7 +28,6 @@
 #include <stdint.h>
 #include <string.h>
 
-#include "py/nlr.h"
 #include "py/runtime.h"
 #include "py/mphal.h"
 #include "extmod/virtpin.h"
@@ -241,7 +240,7 @@ STATIC void pin_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t
     }
 }
 
-STATIC mp_obj_t pin_obj_init_helper(const pin_obj_t *pin, mp_uint_t n_args, const mp_obj_t *args, mp_map_t *kw_args);
+STATIC mp_obj_t pin_obj_init_helper(const pin_obj_t *pin, size_t n_args, const mp_obj_t *args, mp_map_t *kw_args);
 
 /// \classmethod \constructor(id, ...)
 /// Create a new Pin object associated with the id.  If additional arguments are given,
@@ -278,7 +277,7 @@ STATIC mp_obj_t pin_call(mp_obj_t self_in, size_t n_args, size_t n_kw, const mp_
 
 /// \classmethod mapper([fun])
 /// Get or set the pin mapper function.
-STATIC mp_obj_t pin_mapper(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t pin_mapper(size_t n_args, const mp_obj_t *args) {
     if (n_args > 1) {
         MP_STATE_PORT(pin_class_mapper) = args[1];
         return mp_const_none;
@@ -290,7 +289,7 @@ STATIC MP_DEFINE_CONST_CLASSMETHOD_OBJ(pin_mapper_obj, (mp_obj_t)&pin_mapper_fun
 
 /// \classmethod dict([dict])
 /// Get or set the pin mapper dictionary.
-STATIC mp_obj_t pin_map_dict(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t pin_map_dict(size_t n_args, const mp_obj_t *args) {
     if (n_args > 1) {
         MP_STATE_PORT(pin_class_map_dict) = args[1];
         return mp_const_none;
@@ -316,7 +315,7 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_1(pin_af_list_obj, pin_af_list);
 
 /// \classmethod debug([state])
 /// Get or set the debugging state (`True` or `False` for on or off).
-STATIC mp_obj_t pin_debug(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t pin_debug(size_t n_args, const mp_obj_t *args) {
     if (n_args > 1) {
         pin_class_debug = mp_obj_is_true(args[1]);
         return mp_const_none;
@@ -327,7 +326,7 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pin_debug_fun_obj, 1, 2, pin_debug);
 STATIC MP_DEFINE_CONST_CLASSMETHOD_OBJ(pin_debug_obj, (mp_obj_t)&pin_debug_fun_obj);
 
 // init(mode, pull=None, af=-1, *, value, alt)
-STATIC mp_obj_t pin_obj_init_helper(const pin_obj_t *self, mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t pin_obj_init_helper(const pin_obj_t *self, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     static const mp_arg_t allowed_args[] = {
         { MP_QSTR_mode, MP_ARG_REQUIRED | MP_ARG_INT },
         { MP_QSTR_pull, MP_ARG_OBJ, {.u_obj = mp_const_none}},
@@ -384,7 +383,7 @@ STATIC mp_obj_t pin_obj_init_helper(const pin_obj_t *self, mp_uint_t n_args, con
     return mp_const_none;
 }
 
-STATIC mp_obj_t pin_obj_init(mp_uint_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
+STATIC mp_obj_t pin_obj_init(size_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
     return pin_obj_init_helper(args[0], n_args - 1, args + 1, kw_args);
 }
 MP_DEFINE_CONST_FUN_OBJ_KW(pin_init_obj, 1, pin_obj_init);
@@ -396,7 +395,7 @@ MP_DEFINE_CONST_FUN_OBJ_KW(pin_init_obj, 1, pin_obj_init);
 ///   - With `value` given, set the logic level of the pin.  `value` can be
 ///   anything that converts to a boolean.  If it converts to `True`, the pin
 ///   is set high, otherwise it is set low.
-STATIC mp_obj_t pin_value(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t pin_value(size_t n_args, const mp_obj_t *args) {
     return pin_call(args[0], n_args - 1, 0, args + 1);
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pin_value_obj, 1, 2, pin_value);
diff --git a/stmhal/pin.h b/ports/stm32/pin.h
similarity index 100%
rename from stmhal/pin.h
rename to ports/stm32/pin.h
diff --git a/stmhal/pin_defs_stmhal.c b/ports/stm32/pin_defs_stm32.c
similarity index 100%
rename from stmhal/pin_defs_stmhal.c
rename to ports/stm32/pin_defs_stm32.c
diff --git a/stmhal/pin_defs_stmhal.h b/ports/stm32/pin_defs_stm32.h
similarity index 99%
rename from stmhal/pin_defs_stmhal.h
rename to ports/stm32/pin_defs_stm32.h
index 6cf3b1b832..c5b2862835 100644
--- a/stmhal/pin_defs_stmhal.h
+++ b/ports/stm32/pin_defs_stm32.h
@@ -24,7 +24,7 @@
  * THE SOFTWARE.
  */
 
-// This file contains pin definitions that are specific to the stmhal port.
+// This file contains pin definitions that are specific to the stm32 port.
 // This file should only ever be #included by pin.h and not directly.
 
 enum {
diff --git a/stmhal/pin_named_pins.c b/ports/stm32/pin_named_pins.c
similarity index 100%
rename from stmhal/pin_named_pins.c
rename to ports/stm32/pin_named_pins.c
diff --git a/stmhal/portmodules.h b/ports/stm32/portmodules.h
similarity index 100%
rename from stmhal/portmodules.h
rename to ports/stm32/portmodules.h
diff --git a/stmhal/pybcdc.inf_template b/ports/stm32/pybcdc.inf_template
similarity index 100%
rename from stmhal/pybcdc.inf_template
rename to ports/stm32/pybcdc.inf_template
diff --git a/stmhal/pybthread.c b/ports/stm32/pybthread.c
similarity index 100%
rename from stmhal/pybthread.c
rename to ports/stm32/pybthread.c
diff --git a/stmhal/pybthread.h b/ports/stm32/pybthread.h
similarity index 100%
rename from stmhal/pybthread.h
rename to ports/stm32/pybthread.h
diff --git a/stmhal/qstrdefsport.h b/ports/stm32/qstrdefsport.h
similarity index 100%
rename from stmhal/qstrdefsport.h
rename to ports/stm32/qstrdefsport.h
diff --git a/stmhal/rng.c b/ports/stm32/rng.c
similarity index 100%
rename from stmhal/rng.c
rename to ports/stm32/rng.c
diff --git a/stmhal/rng.h b/ports/stm32/rng.h
similarity index 100%
rename from stmhal/rng.h
rename to ports/stm32/rng.h
diff --git a/stmhal/rtc.c b/ports/stm32/rtc.c
similarity index 99%
rename from stmhal/rtc.c
rename to ports/stm32/rtc.c
index 6cb6ef047e..73272d3631 100644
--- a/stmhal/rtc.c
+++ b/ports/stm32/rtc.c
@@ -481,7 +481,7 @@ uint32_t rtc_us_to_subsec(uint32_t us) {
 #define rtc_subsec_to_us
 #endif
 
-mp_obj_t pyb_rtc_datetime(mp_uint_t n_args, const mp_obj_t *args) {
+mp_obj_t pyb_rtc_datetime(size_t n_args, const mp_obj_t *args) {
     rtc_init_finalise();
     if (n_args == 1) {
         // get date and time
@@ -531,7 +531,7 @@ MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_rtc_datetime_obj, 1, 2, pyb_rtc_datetime
 // wakeup(None)
 // wakeup(ms, callback=None)
 // wakeup(wucksel, wut, callback)
-mp_obj_t pyb_rtc_wakeup(mp_uint_t n_args, const mp_obj_t *args) {
+mp_obj_t pyb_rtc_wakeup(size_t n_args, const mp_obj_t *args) {
     // wut is wakeup counter start value, wucksel is clock source
     // counter is decremented at wucksel rate, and wakes the MCU when it gets to 0
     // wucksel=0b000 is RTC/16 (RTC runs at 32768Hz)
@@ -666,7 +666,7 @@ MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_rtc_wakeup_obj, 2, 4, pyb_rtc_wakeup);
 // calibration(cal)
 // When an integer argument is provided, check that it falls in the range [-511 to 512]
 // and set the calibration value; otherwise return calibration value
-mp_obj_t pyb_rtc_calibration(mp_uint_t n_args, const mp_obj_t *args) {
+mp_obj_t pyb_rtc_calibration(size_t n_args, const mp_obj_t *args) {
     rtc_init_finalise();
     mp_int_t cal;
     if (n_args == 2) {
diff --git a/stmhal/rtc.h b/ports/stm32/rtc.h
similarity index 100%
rename from stmhal/rtc.h
rename to ports/stm32/rtc.h
diff --git a/stmhal/sdcard.c b/ports/stm32/sdcard.c
similarity index 88%
rename from stmhal/sdcard.c
rename to ports/stm32/sdcard.c
index dfa7158a4c..484426b846 100644
--- a/stmhal/sdcard.c
+++ b/ports/stm32/sdcard.c
@@ -26,7 +26,6 @@
 
 #include <string.h>
 
-#include "py/nlr.h"
 #include "py/runtime.h"
 #include "py/mphal.h"
 #include "lib/oofatfs/ff.h"
@@ -191,8 +190,7 @@ bool sdcard_power_on(void) {
     sd_handle.Init.ClockDiv            = SDIO_TRANSFER_CLK_DIV;
 
     // init the SD interface, with retry if it's not ready yet
-    HAL_SD_CardInfoTypedef cardinfo;
-    for (int retry = 10; HAL_SD_Init(&sd_handle, &cardinfo) != SD_OK; retry--) {
+    for (int retry = 10; HAL_SD_Init(&sd_handle) != HAL_OK; retry--) {
         if (retry == 0) {
             goto error;
         }
@@ -200,7 +198,7 @@ bool sdcard_power_on(void) {
     }
 
     // configure the SD bus width for wide operation
-    if (HAL_SD_WideBusOperation_Config(&sd_handle, SDIO_BUS_WIDE_4B) != SD_OK) {
+    if (HAL_SD_ConfigWideBusOperation(&sd_handle, SDIO_BUS_WIDE_4B) != HAL_OK) {
         HAL_SD_DeInit(&sd_handle);
         goto error;
     }
@@ -224,9 +222,9 @@ uint64_t sdcard_get_capacity_in_bytes(void) {
     if (sd_handle.Instance == NULL) {
         return 0;
     }
-    HAL_SD_CardInfoTypedef cardinfo;
-    HAL_SD_Get_CardInfo(&sd_handle, &cardinfo);
-    return cardinfo.CardCapacity;
+    HAL_SD_CardInfoTypeDef cardinfo;
+    HAL_SD_GetCardInfo(&sd_handle, &cardinfo);
+    return (uint64_t)cardinfo.LogBlockNbr * (uint64_t)cardinfo.LogBlockSize;
 }
 
 void SDIO_IRQHandler(void) {
@@ -243,13 +241,37 @@ void SDMMC2_IRQHandler(void) {
 }
 #endif
 
+STATIC HAL_StatusTypeDef sdcard_wait_finished(SD_HandleTypeDef *sd, uint32_t timeout) {
+    // Wait for HAL driver to be ready (eg for DMA to finish)
+    uint32_t start = HAL_GetTick();
+    while (sd->State == HAL_SD_STATE_BUSY) {
+        if (HAL_GetTick() - start >= timeout) {
+            return HAL_TIMEOUT;
+        }
+    }
+    // Wait for SD card to complete the operation
+    for (;;) {
+        HAL_SD_CardStateTypeDef state = HAL_SD_GetCardState(sd);
+        if (state == HAL_SD_CARD_TRANSFER) {
+            return HAL_OK;
+        }
+        if (!(state == HAL_SD_CARD_SENDING || state == HAL_SD_CARD_RECEIVING || state == HAL_SD_CARD_PROGRAMMING)) {
+            return HAL_ERROR;
+        }
+        if (HAL_GetTick() - start >= timeout) {
+            return HAL_TIMEOUT;
+        }
+    }
+    return HAL_OK;
+}
+
 mp_uint_t sdcard_read_blocks(uint8_t *dest, uint32_t block_num, uint32_t num_blocks) {
     // check that SD card is initialised
     if (sd_handle.Instance == NULL) {
-        return SD_ERROR;
+        return HAL_ERROR;
     }
 
-    HAL_SD_ErrorTypedef err = SD_OK;
+    HAL_StatusTypeDef err = HAL_OK;
 
     // check that dest pointer is aligned on a 4-byte boundary
     uint8_t *orig_dest = NULL;
@@ -280,10 +302,9 @@ mp_uint_t sdcard_read_blocks(uint8_t *dest, uint32_t block_num, uint32_t num_blo
         // from reading the peripheral the CPU then reads the new data
         MP_HAL_CLEANINVALIDATE_DCACHE(dest, num_blocks * SDCARD_BLOCK_SIZE);
 
-        err = HAL_SD_ReadBlocks_BlockNumber_DMA(&sd_handle, (uint32_t*)dest, block_num, SDCARD_BLOCK_SIZE, num_blocks);
-        if (err == SD_OK) {
-            // wait for DMA transfer to finish, with a large timeout
-            err = HAL_SD_CheckReadOperation(&sd_handle, 100000000);
+        err = HAL_SD_ReadBlocks_DMA(&sd_handle, dest, block_num, num_blocks);
+        if (err == HAL_OK) {
+            err = sdcard_wait_finished(&sd_handle, 60000);
         }
 
         dma_deinit(&SDMMC_RX_DMA);
@@ -291,7 +312,10 @@ mp_uint_t sdcard_read_blocks(uint8_t *dest, uint32_t block_num, uint32_t num_blo
 
         restore_irq_pri(basepri);
     } else {
-        err = HAL_SD_ReadBlocks_BlockNumber(&sd_handle, (uint32_t*)dest, block_num, SDCARD_BLOCK_SIZE, num_blocks);
+        err = HAL_SD_ReadBlocks(&sd_handle, dest, block_num, num_blocks, 60000);
+        if (err == HAL_OK) {
+            err = sdcard_wait_finished(&sd_handle, 60000);
+        }
     }
 
     if (orig_dest != NULL) {
@@ -306,22 +330,22 @@ mp_uint_t sdcard_read_blocks(uint8_t *dest, uint32_t block_num, uint32_t num_blo
 mp_uint_t sdcard_write_blocks(const uint8_t *src, uint32_t block_num, uint32_t num_blocks) {
     // check that SD card is initialised
     if (sd_handle.Instance == NULL) {
-        return SD_ERROR;
+        return HAL_ERROR;
     }
 
-    HAL_SD_ErrorTypedef err = SD_OK;
+    HAL_StatusTypeDef err = HAL_OK;
 
     // check that src pointer is aligned on a 4-byte boundary
     if (((uint32_t)src & 3) != 0) {
         // pointer is not aligned, so allocate a temporary block to do the write
         uint8_t *src_aligned = m_new_maybe(uint8_t, SDCARD_BLOCK_SIZE);
         if (src_aligned == NULL) {
-            return SD_ERROR;
+            return HAL_ERROR;
         }
         for (size_t i = 0; i < num_blocks; ++i) {
             memcpy(src_aligned, src + i * SDCARD_BLOCK_SIZE, SDCARD_BLOCK_SIZE);
             err = sdcard_write_blocks(src_aligned, block_num + i, 1);
-            if (err != SD_OK) {
+            if (err != HAL_OK) {
                 break;
             }
         }
@@ -339,17 +363,19 @@ mp_uint_t sdcard_write_blocks(const uint8_t *src, uint32_t block_num, uint32_t n
         // make sure cache is flushed to RAM so the DMA can read the correct data
         MP_HAL_CLEAN_DCACHE(src, num_blocks * SDCARD_BLOCK_SIZE);
 
-        err = HAL_SD_WriteBlocks_BlockNumber_DMA(&sd_handle, (uint32_t*)src, block_num, SDCARD_BLOCK_SIZE, num_blocks);
-        if (err == SD_OK) {
-            // wait for DMA transfer to finish, with a large timeout
-            err = HAL_SD_CheckWriteOperation(&sd_handle, 100000000);
+        err = HAL_SD_WriteBlocks_DMA(&sd_handle, (uint8_t*)src, block_num, num_blocks);
+        if (err == HAL_OK) {
+            err = sdcard_wait_finished(&sd_handle, 60000);
         }
         dma_deinit(&SDMMC_TX_DMA);
         sd_handle.hdmatx = NULL;
 
         restore_irq_pri(basepri);
     } else {
-        err = HAL_SD_WriteBlocks_BlockNumber(&sd_handle, (uint32_t*)src, block_num, SDCARD_BLOCK_SIZE, num_blocks);
+        err = HAL_SD_WriteBlocks(&sd_handle, (uint8_t*)src, block_num, num_blocks, 60000);
+        if (err == HAL_OK) {
+            err = sdcard_wait_finished(&sd_handle, 60000);
+        }
     }
 
     return err;
@@ -392,12 +418,12 @@ STATIC mp_obj_t sd_info(mp_obj_t self) {
     if (sd_handle.Instance == NULL) {
         return mp_const_none;
     }
-    HAL_SD_CardInfoTypedef cardinfo;
-    HAL_SD_Get_CardInfo(&sd_handle, &cardinfo);
+    HAL_SD_CardInfoTypeDef cardinfo;
+    HAL_SD_GetCardInfo(&sd_handle, &cardinfo);
     // cardinfo.SD_csd and cardinfo.SD_cid have lots of info but we don't use them
     mp_obj_t tuple[3] = {
-        mp_obj_new_int_from_ull(cardinfo.CardCapacity),
-        mp_obj_new_int_from_uint(cardinfo.CardBlockSize),
+        mp_obj_new_int_from_ull((uint64_t)cardinfo.LogBlockNbr * (uint64_t)cardinfo.LogBlockSize),
+        mp_obj_new_int_from_uint(cardinfo.LogBlockSize),
         mp_obj_new_int(cardinfo.CardType),
     };
     return mp_obj_new_tuple(3, tuple);
diff --git a/stmhal/sdcard.h b/ports/stm32/sdcard.h
similarity index 100%
rename from stmhal/sdcard.h
rename to ports/stm32/sdcard.h
diff --git a/stmhal/servo.c b/ports/stm32/servo.c
similarity index 97%
rename from stmhal/servo.c
rename to ports/stm32/servo.c
index fa39587a8e..0e54b4d0af 100644
--- a/stmhal/servo.c
+++ b/ports/stm32/servo.c
@@ -205,7 +205,7 @@ STATIC mp_obj_t pyb_servo_make_new(const mp_obj_type_t *type, size_t n_args, siz
 
 /// \method pulse_width([value])
 /// Get or set the pulse width in milliseconds.
-STATIC mp_obj_t pyb_servo_pulse_width(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t pyb_servo_pulse_width(size_t n_args, const mp_obj_t *args) {
     pyb_servo_obj_t *self = args[0];
     if (n_args == 1) {
         // get pulse width, in us
@@ -223,7 +223,7 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_servo_pulse_width_obj, 1, 2, pyb_
 /// \method calibration([pulse_min, pulse_max, pulse_centre, [pulse_angle_90, pulse_speed_100]])
 /// Get or set the calibration of the servo timing.
 // TODO should accept 1 arg, a 5-tuple of values to set
-STATIC mp_obj_t pyb_servo_calibration(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t pyb_servo_calibration(size_t n_args, const mp_obj_t *args) {
     pyb_servo_obj_t *self = args[0];
     if (n_args == 1) {
         // get calibration values
@@ -258,7 +258,7 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_servo_calibration_obj, 1, 6, pyb_
 ///
 ///   - `angle` is the angle to move to in degrees.
 ///   - `time` is the number of milliseconds to take to get to the specified angle.
-STATIC mp_obj_t pyb_servo_angle(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t pyb_servo_angle(size_t n_args, const mp_obj_t *args) {
     pyb_servo_obj_t *self = args[0];
     if (n_args == 1) {
         // get angle
@@ -288,7 +288,7 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_servo_angle_obj, 1, 3, pyb_servo_
 ///
 ///   - `speed` is the speed to move to change to, between -100 and 100.
 ///   - `time` is the number of milliseconds to take to get to the specified speed.
-STATIC mp_obj_t pyb_servo_speed(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t pyb_servo_speed(size_t n_args, const mp_obj_t *args) {
     pyb_servo_obj_t *self = args[0];
     if (n_args == 1) {
         // get speed
diff --git a/stmhal/servo.h b/ports/stm32/servo.h
similarity index 100%
rename from stmhal/servo.h
rename to ports/stm32/servo.h
diff --git a/stmhal/spi.c b/ports/stm32/spi.c
similarity index 98%
rename from stmhal/spi.c
rename to ports/stm32/spi.c
index d25e13f986..cfd9c2667f 100644
--- a/stmhal/spi.c
+++ b/ports/stm32/spi.c
@@ -27,7 +27,6 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "py/nlr.h"
 #include "py/runtime.h"
 #include "py/mphal.h"
 #include "extmod/machine_spi.h"
@@ -550,7 +549,7 @@ STATIC void pyb_spi_print(const mp_print_t *print, mp_obj_t self_in, mp_print_ki
 ///
 ///   - `mode` must be either `SPI.MASTER` or `SPI.SLAVE`.
 ///   - `baudrate` is the SCK clock rate (only sensible for a master).
-STATIC mp_obj_t pyb_spi_init_helper(const pyb_spi_obj_t *self, mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_spi_init_helper(const pyb_spi_obj_t *self, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     static const mp_arg_t allowed_args[] = {
         { MP_QSTR_mode,     MP_ARG_REQUIRED | MP_ARG_INT, {.u_int = 0} },
         { MP_QSTR_baudrate, MP_ARG_INT, {.u_int = 328125} },
@@ -628,7 +627,7 @@ STATIC mp_obj_t pyb_spi_make_new(const mp_obj_type_t *type, size_t n_args, size_
     return (mp_obj_t)spi_obj;
 }
 
-STATIC mp_obj_t pyb_spi_init(mp_uint_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_spi_init(size_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
     return pyb_spi_init_helper(args[0], n_args - 1, args + 1, kw_args);
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_KW(pyb_spi_init_obj, 1, pyb_spi_init);
@@ -649,7 +648,7 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_spi_deinit_obj, pyb_spi_deinit);
 ///   - `timeout` is the timeout in milliseconds to wait for the send.
 ///
 /// Return value: `None`.
-STATIC mp_obj_t pyb_spi_send(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_spi_send(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     // TODO assumes transmission size is 8-bits wide
 
     static const mp_arg_t allowed_args[] = {
@@ -684,7 +683,7 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_KW(pyb_spi_send_obj, 1, pyb_spi_send);
 ///
 /// Return value: if `recv` is an integer then a new buffer of the bytes received,
 /// otherwise the same buffer that was passed in to `recv`.
-STATIC mp_obj_t pyb_spi_recv(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_spi_recv(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     // TODO assumes transmission size is 8-bits wide
 
     static const mp_arg_t allowed_args[] = {
@@ -724,7 +723,7 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_KW(pyb_spi_recv_obj, 1, pyb_spi_recv);
 ///   - `timeout` is the timeout in milliseconds to wait for the receive.
 ///
 /// Return value: the buffer with the received bytes.
-STATIC mp_obj_t pyb_spi_send_recv(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_spi_send_recv(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     // TODO assumes transmission size is 8-bits wide
 
     static const mp_arg_t allowed_args[] = {
diff --git a/stmhal/spi.h b/ports/stm32/spi.h
similarity index 100%
rename from stmhal/spi.h
rename to ports/stm32/spi.h
diff --git a/stmhal/startup_stm32.S b/ports/stm32/startup_stm32.S
similarity index 100%
rename from stmhal/startup_stm32.S
rename to ports/stm32/startup_stm32.S
diff --git a/stmhal/stm32_it.c b/ports/stm32/stm32_it.c
similarity index 99%
rename from stmhal/stm32_it.c
rename to ports/stm32/stm32_it.c
index 2111da1ae1..f1ac9b6b85 100644
--- a/stmhal/stm32_it.c
+++ b/ports/stm32/stm32_it.c
@@ -67,7 +67,6 @@
 
 #include <stdio.h>
 
-#include "py/mpstate.h"
 #include "py/obj.h"
 #include "py/mphal.h"
 #include "stm32_it.h"
diff --git a/stmhal/stm32_it.h b/ports/stm32/stm32_it.h
similarity index 100%
rename from stmhal/stm32_it.h
rename to ports/stm32/stm32_it.h
diff --git a/stmhal/storage.c b/ports/stm32/storage.c
similarity index 97%
rename from stmhal/storage.c
rename to ports/stm32/storage.c
index 6da1ba95c6..4b329c2dbb 100644
--- a/stmhal/storage.c
+++ b/ports/stm32/storage.c
@@ -92,12 +92,12 @@ STATIC byte flash_cache_mem[0x4000] __attribute__((aligned(4))); // 16k
 #define FLASH_MEM_SEG1_START_ADDR (0x08008000) // sector 1
 #define FLASH_MEM_SEG1_NUM_BLOCKS (192) // sectors 1,2,3: 32k+32k+32=96k
 
-#elif defined(STM32L476xx)
+#elif defined(STM32L475xx) || defined(STM32L476xx)
 
 extern uint8_t _flash_fs_start;
 extern uint8_t _flash_fs_end;
 
-// The STM32L476 doesn't have CCRAM, so we use the 32K SRAM2 for this.
+// The STM32L475/6 doesn't have CCRAM, so we use the 32K SRAM2 for this.
 #define CACHE_MEM_START_ADDR (0x10000000)       // SRAM2 data RAM, 32k
 #define FLASH_SECTOR_SIZE_MAX (0x00800)         // 2k max
 #define FLASH_MEM_SEG1_START_ADDR ((long)&_flash_fs_start)
@@ -176,17 +176,19 @@ static uint8_t *flash_cache_get_addr_for_read(uint32_t flash_addr) {
 
 static bool flash_is_initialised = false;
 
+STATIC const mp_machine_soft_spi_obj_t spiflash_spi_bus = {
+    .base = {&mp_machine_soft_spi_type},
+    .delay_half = MICROPY_PY_MACHINE_SPI_MIN_DELAY,
+    .polarity = 0,
+    .phase = 0,
+    .sck = &MICROPY_HW_SPIFLASH_SCK,
+    .mosi = &MICROPY_HW_SPIFLASH_MOSI,
+    .miso = &MICROPY_HW_SPIFLASH_MISO,
+};
+
 STATIC const mp_spiflash_t spiflash = {
     .cs = &MICROPY_HW_SPIFLASH_CS,
-    .spi = {
-        .base = {&mp_machine_soft_spi_type},
-        .delay_half = MICROPY_PY_MACHINE_SPI_MIN_DELAY,
-        .polarity = 0,
-        .phase = 0,
-        .sck = &MICROPY_HW_SPIFLASH_SCK,
-        .mosi = &MICROPY_HW_SPIFLASH_MOSI,
-        .miso = &MICROPY_HW_SPIFLASH_MISO,
-    },
+    .spi = (mp_obj_base_t*)&spiflash_spi_bus.base,
 };
 
 #endif
diff --git a/stmhal/storage.h b/ports/stm32/storage.h
similarity index 100%
rename from stmhal/storage.h
rename to ports/stm32/storage.h
diff --git a/stmhal/system_stm32.c b/ports/stm32/system_stm32.c
similarity index 97%
rename from stmhal/system_stm32.c
rename to ports/stm32/system_stm32.c
index 7fc16b1483..b71a03181a 100644
--- a/stmhal/system_stm32.c
+++ b/ports/stm32/system_stm32.c
@@ -113,7 +113,10 @@ void __fatal_error(const char *msg);
 #define CONFIG_RCC_CR_2ND (RCC_CR_HSEON || RCC_CR_CSSON || RCC_CR_PLLON)
 #define CONFIG_RCC_PLLCFGR (0x24003010)
 
-#if defined(MCU_SERIES_F7)
+#if defined(MCU_SERIES_F4)
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
+#elif defined(MCU_SERIES_F7)
 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
 #endif
@@ -328,12 +331,8 @@ void SystemClock_Config(void)
      regarding system frequency refer to product datasheet.  */
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
     #elif defined(MCU_SERIES_L4)
-    /* Enable the LSE Oscillator */
-    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
-    RCC_OscInitStruct.LSEState = RCC_LSE_ON;
-    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
-        __fatal_error("HAL_RCC_OscConfig");
-    }
+    // Configure LSE Drive Capability
+    __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
     #endif
 
     /* Enable HSE Oscillator and activate PLL with HSE as source */
@@ -461,6 +460,8 @@ void SystemClock_Config(void)
     PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
     PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
     PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_PLLSAI1;
+    PeriphClkInitStruct.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_MSI;
+    PeriphClkInitStruct.PLLSAI1.PLLSAI1M = 1;
     PeriphClkInitStruct.PLLSAI1.PLLSAI1N = 24;
     PeriphClkInitStruct.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
     PeriphClkInitStruct.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
diff --git a/stmhal/systick.c b/ports/stm32/systick.c
similarity index 100%
rename from stmhal/systick.c
rename to ports/stm32/systick.c
diff --git a/stmhal/systick.h b/ports/stm32/systick.h
similarity index 100%
rename from stmhal/systick.h
rename to ports/stm32/systick.h
diff --git a/stmhal/timer.c b/ports/stm32/timer.c
similarity index 92%
rename from stmhal/timer.c
rename to ports/stm32/timer.c
index 938e965971..96a6baa02d 100644
--- a/stmhal/timer.c
+++ b/ports/stm32/timer.c
@@ -28,9 +28,6 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "usbd_cdc_msc_hid.h"
-#include "usbd_cdc_interface.h"
-
 #include "py/runtime.h"
 #include "py/gc.h"
 #include "timer.h"
@@ -515,7 +512,7 @@ STATIC void pyb_timer_print(const mp_print_t *print, mp_obj_t self_in, mp_print_
 ///       `deadtime` is only available on timers 1 and 8.
 ///
 ///  You must either specify freq or both of period and prescaler.
-STATIC mp_obj_t pyb_timer_init_helper(pyb_timer_obj_t *self, mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_timer_init_helper(pyb_timer_obj_t *self, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     static const mp_arg_t allowed_args[] = {
         { MP_QSTR_freq,         MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} },
         { MP_QSTR_prescaler,    MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0xffffffff} },
@@ -623,6 +620,12 @@ STATIC mp_obj_t pyb_timer_init_helper(pyb_timer_obj_t *self, mp_uint_t n_args, c
     #endif
         config_deadtime(self, args[6].u_int);
     }
+
+    // Enable ARPE so that the auto-reload register is buffered.
+    // This allows to smoothly change the frequency of the timer.
+    self->tim.Instance->CR1 |= TIM_CR1_ARPE;
+
+    // Start the timer running
     if (args[5].u_obj == mp_const_none) {
         HAL_TIM_Base_Start(&self->tim);
     } else {
@@ -632,6 +635,62 @@ STATIC mp_obj_t pyb_timer_init_helper(pyb_timer_obj_t *self, mp_uint_t n_args, c
     return mp_const_none;
 }
 
+// This table encodes the timer instance and irq number.
+// It assumes that timer instance pointer has the lower 8 bits cleared.
+#define TIM_ENTRY(id, irq) [id - 1] = (uint32_t)TIM##id | irq
+STATIC const uint32_t tim_instance_table[MICROPY_HW_MAX_TIMER] = {
+    #if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
+    TIM_ENTRY(1, TIM1_UP_TIM10_IRQn),
+    #elif defined(MCU_SERIES_L4)
+    TIM_ENTRY(1, TIM1_UP_TIM16_IRQn),
+    #endif
+    TIM_ENTRY(2, TIM2_IRQn),
+    TIM_ENTRY(3, TIM3_IRQn),
+    TIM_ENTRY(4, TIM4_IRQn),
+    TIM_ENTRY(5, TIM5_IRQn),
+    #if defined(TIM6)
+    TIM_ENTRY(6, TIM6_DAC_IRQn),
+    #endif
+    #if defined(TIM7)
+    TIM_ENTRY(7, TIM7_IRQn),
+    #endif
+    #if defined(TIM8)
+    #if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
+    TIM_ENTRY(8, TIM8_UP_TIM13_IRQn),
+    #elif defined(MCU_SERIES_L4)
+    TIM_ENTRY(8, TIM8_UP_IRQn),
+    #endif
+    #endif
+    #if defined(TIM9)
+    TIM_ENTRY(9, TIM1_BRK_TIM9_IRQn),
+    #endif
+    #if defined(TIM10)
+    TIM_ENTRY(10, TIM1_UP_TIM10_IRQn),
+    #endif
+    #if defined(TIM11)
+    TIM_ENTRY(11, TIM1_TRG_COM_TIM11_IRQn),
+    #endif
+    #if defined(TIM12)
+    TIM_ENTRY(12, TIM8_BRK_TIM12_IRQn),
+    #endif
+    #if defined(TIM13)
+    TIM_ENTRY(13, TIM8_UP_TIM13_IRQn),
+    #endif
+    #if defined(TIM14)
+    TIM_ENTRY(14, TIM8_TRG_COM_TIM14_IRQn),
+    #endif
+    #if defined(TIM15)
+    TIM_ENTRY(15, TIM1_BRK_TIM15_IRQn),
+    #endif
+    #if defined(TIM16)
+    TIM_ENTRY(16, TIM1_UP_TIM16_IRQn),
+    #endif
+    #if defined(TIM17)
+    TIM_ENTRY(17, TIM1_TRG_COM_TIM17_IRQn),
+    #endif
+};
+#undef TIM_ENTRY
+
 /// \classmethod \constructor(id, ...)
 /// Construct a new timer object of the given id.  If additional
 /// arguments are given, then the timer is initialised by `init(...)`.
@@ -640,74 +699,30 @@ STATIC mp_obj_t pyb_timer_make_new(const mp_obj_type_t *type, size_t n_args, siz
     // check arguments
     mp_arg_check_num(n_args, n_kw, 1, MP_OBJ_FUN_ARGS_MAX, true);
 
-    // create new Timer object
-    pyb_timer_obj_t *tim = m_new_obj(pyb_timer_obj_t);
-    memset(tim, 0, sizeof(*tim));
+    // get the timer id
+    mp_int_t tim_id = mp_obj_get_int(args[0]);
 
-    tim->base.type = &pyb_timer_type;
-    tim->callback = mp_const_none;
-    tim->channel = NULL;
-
-    // get TIM number
-    tim->tim_id = mp_obj_get_int(args[0]);
-    tim->is_32bit = false;
-
-    switch (tim->tim_id) {
-        #if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
-        case 1: tim->tim.Instance = TIM1; tim->irqn = TIM1_UP_TIM10_IRQn; break;
-        #elif defined(MCU_SERIES_L4)
-        case 1: tim->tim.Instance = TIM1; tim->irqn = TIM1_UP_TIM16_IRQn; break;
-        #endif
-        case 2: tim->tim.Instance = TIM2; tim->irqn = TIM2_IRQn; tim->is_32bit = true; break;
-        case 3: tim->tim.Instance = TIM3; tim->irqn = TIM3_IRQn; break;
-        case 4: tim->tim.Instance = TIM4; tim->irqn = TIM4_IRQn; break;
-        case 5: tim->tim.Instance = TIM5; tim->irqn = TIM5_IRQn; tim->is_32bit = true; break;
-        #if defined(TIM6)
-        case 6: tim->tim.Instance = TIM6; tim->irqn = TIM6_DAC_IRQn; break;
-        #endif
-        #if defined(TIM7)
-        case 7: tim->tim.Instance = TIM7; tim->irqn = TIM7_IRQn; break;
-        #endif
-        #if defined(TIM8)
-        #if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
-        case 8: tim->tim.Instance = TIM8; tim->irqn = TIM8_UP_TIM13_IRQn; break;
-        #elif defined(MCU_SERIES_L4)
-        case 8: tim->tim.Instance = TIM8; tim->irqn = TIM8_UP_IRQn; break;
-        #endif
-        #endif
-        #if defined(TIM9)
-        case 9: tim->tim.Instance = TIM9; tim->irqn = TIM1_BRK_TIM9_IRQn; break;
-        #endif
-        #if defined(TIM10)
-        case 10: tim->tim.Instance = TIM10; tim->irqn = TIM1_UP_TIM10_IRQn; break;
-        #endif
-        #if defined(TIM11)
-        case 11: tim->tim.Instance = TIM11; tim->irqn = TIM1_TRG_COM_TIM11_IRQn; break;
-        #endif
-        #if defined(TIM12)
-        case 12: tim->tim.Instance = TIM12; tim->irqn = TIM8_BRK_TIM12_IRQn; break;
-        #endif
-        #if defined(TIM13)
-        case 13: tim->tim.Instance = TIM13; tim->irqn = TIM8_UP_TIM13_IRQn; break;
-        #endif
-        #if defined(TIM14)
-        case 14: tim->tim.Instance = TIM14; tim->irqn = TIM8_TRG_COM_TIM14_IRQn; break;
-        #endif
-        #if defined(TIM15)
-        case 15: tim->tim.Instance = TIM15; tim->irqn = TIM1_BRK_TIM15_IRQn; break;
-        #endif
-        #if defined(TIM16)
-        case 16: tim->tim.Instance = TIM16; tim->irqn = TIM1_UP_TIM16_IRQn; break;
-        #endif
-        #if defined(TIM17)
-        case 17: tim->tim.Instance = TIM17; tim->irqn = TIM1_TRG_COM_TIM17_IRQn; break;
-        #endif
-        default: nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "Timer(%d) doesn't exist", tim->tim_id));
+    // check if the timer exists
+    if (tim_id <= 0 || tim_id > MICROPY_HW_MAX_TIMER || tim_instance_table[tim_id - 1] == 0) {
+        nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "Timer(%d) doesn't exist", tim_id));
     }
 
-    // set the global variable for interrupt callbacks
-    if (tim->tim_id - 1 < PYB_TIMER_OBJ_ALL_NUM) {
-        MP_STATE_PORT(pyb_timer_obj_all)[tim->tim_id - 1] = tim;
+    pyb_timer_obj_t *tim;
+    if (MP_STATE_PORT(pyb_timer_obj_all)[tim_id - 1] == NULL) {
+        // create new Timer object
+        tim = m_new_obj(pyb_timer_obj_t);
+        memset(tim, 0, sizeof(*tim));
+        tim->base.type = &pyb_timer_type;
+        tim->tim_id = tim_id;
+        tim->is_32bit = tim_id == 2 || tim_id == 5;
+        tim->callback = mp_const_none;
+        uint32_t ti = tim_instance_table[tim_id - 1];
+        tim->tim.Instance = (TIM_TypeDef*)(ti & 0xffffff00);
+        tim->irqn = ti & 0xff;
+        MP_STATE_PORT(pyb_timer_obj_all)[tim_id - 1] = tim;
+    } else {
+        // reference existing Timer object
+        tim = MP_STATE_PORT(pyb_timer_obj_all)[tim_id - 1];
     }
 
     if (n_args > 1 || n_kw > 0) {
@@ -720,7 +735,7 @@ STATIC mp_obj_t pyb_timer_make_new(const mp_obj_type_t *type, size_t n_args, siz
     return (mp_obj_t)tim;
 }
 
-STATIC mp_obj_t pyb_timer_init(mp_uint_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_timer_init(size_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
     return pyb_timer_init_helper(args[0], n_args - 1, args + 1, kw_args);
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_KW(pyb_timer_init_obj, 1, pyb_timer_init);
@@ -823,7 +838,7 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_timer_deinit_obj, pyb_timer_deinit);
 ///     timer = pyb.Timer(2, freq=1000)
 ///     ch2 = timer.channel(2, pyb.Timer.PWM, pin=pyb.Pin.board.X2, pulse_width=210000)
 ///     ch3 = timer.channel(3, pyb.Timer.PWM, pin=pyb.Pin.board.X3, pulse_width=420000)
-STATIC mp_obj_t pyb_timer_channel(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_timer_channel(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     static const mp_arg_t allowed_args[] = {
         { MP_QSTR_mode,                MP_ARG_REQUIRED | MP_ARG_INT, {.u_int = 0} },
         { MP_QSTR_callback,            MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} },
@@ -1066,7 +1081,7 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_KW(pyb_timer_channel_obj, 2, pyb_timer_channel);
 
 /// \method counter([value])
 /// Get or set the timer counter.
-STATIC mp_obj_t pyb_timer_counter(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t pyb_timer_counter(size_t n_args, const mp_obj_t *args) {
     pyb_timer_obj_t *self = args[0];
     if (n_args == 1) {
         // get
@@ -1090,7 +1105,7 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_timer_source_freq_obj, pyb_timer_source_fre
 
 /// \method freq([value])
 /// Get or set the frequency for the timer (changes prescaler and period if set).
-STATIC mp_obj_t pyb_timer_freq(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t pyb_timer_freq(size_t n_args, const mp_obj_t *args) {
     pyb_timer_obj_t *self = args[0];
     if (n_args == 1) {
         // get
@@ -1112,10 +1127,6 @@ STATIC mp_obj_t pyb_timer_freq(mp_uint_t n_args, const mp_obj_t *args) {
         uint32_t prescaler = compute_prescaler_period_from_freq(self, args[1], &period);
         self->tim.Instance->PSC = prescaler;
         __HAL_TIM_SetAutoreload(&self->tim, period);
-        // Reset the counter to zero. Otherwise, if counter >= period it will
-        // continue counting until it wraps (at either 16 or 32 bits depending
-        // on the timer).
-        __HAL_TIM_SetCounter(&self->tim, 0);
         return mp_const_none;
     }
 }
@@ -1123,7 +1134,7 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_timer_freq_obj, 1, 2, pyb_timer_f
 
 /// \method prescaler([value])
 /// Get or set the prescaler for the timer.
-STATIC mp_obj_t pyb_timer_prescaler(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t pyb_timer_prescaler(size_t n_args, const mp_obj_t *args) {
     pyb_timer_obj_t *self = args[0];
     if (n_args == 1) {
         // get
@@ -1138,7 +1149,7 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_timer_prescaler_obj, 1, 2, pyb_ti
 
 /// \method period([value])
 /// Get or set the period of the timer.
-STATIC mp_obj_t pyb_timer_period(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t pyb_timer_period(size_t n_args, const mp_obj_t *args) {
     pyb_timer_obj_t *self = args[0];
     if (n_args == 1) {
         // get
@@ -1146,10 +1157,6 @@ STATIC mp_obj_t pyb_timer_period(mp_uint_t n_args, const mp_obj_t *args) {
     } else {
         // set
         __HAL_TIM_SetAutoreload(&self->tim, mp_obj_get_int(args[1]) & TIMER_CNT_MASK(self));
-        // Reset the counter to zero. Otherwise, if counter >= period it will
-        // continue counting until it wraps (at either 16 or 32 bits depending
-        // on the timer).
-        __HAL_TIM_SetCounter(&self->tim, 0);
         return mp_const_none;
     }
 }
@@ -1254,7 +1261,7 @@ STATIC void pyb_timer_channel_print(const mp_print_t *print, mp_obj_t self_in, m
 ///
 /// In edge aligned mode, a pulse_width of `period + 1` corresponds to a duty cycle of 100%
 /// In center aligned mode, a pulse width of `period` corresponds to a duty cycle of 100%
-STATIC mp_obj_t pyb_timer_channel_capture_compare(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t pyb_timer_channel_capture_compare(size_t n_args, const mp_obj_t *args) {
     pyb_timer_channel_obj_t *self = args[0];
     if (n_args == 1) {
         // get
@@ -1273,7 +1280,7 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_timer_channel_capture_compare_obj
 /// for which the pulse is active.  The value can be an integer or
 /// floating-point number for more accuracy.  For example, a value of 25 gives
 /// a duty cycle of 25%.
-STATIC mp_obj_t pyb_timer_channel_pulse_width_percent(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t pyb_timer_channel_pulse_width_percent(size_t n_args, const mp_obj_t *args) {
     pyb_timer_channel_obj_t *self = args[0];
     uint32_t period = compute_period(self->timer);
     if (n_args == 1) {
diff --git a/stmhal/timer.h b/ports/stm32/timer.h
similarity index 100%
rename from stmhal/timer.h
rename to ports/stm32/timer.h
diff --git a/stmhal/uart.c b/ports/stm32/uart.c
similarity index 99%
rename from stmhal/uart.c
rename to ports/stm32/uart.c
index 0f4d36bf1a..a8913a055a 100644
--- a/stmhal/uart.c
+++ b/ports/stm32/uart.c
@@ -28,8 +28,8 @@
 #include <string.h>
 #include <stdarg.h>
 
-#include "py/ioctl.h"
-#include "py/nlr.h"
+//#include "py/ioctl.h"
+//#include "py/nlr.h"
 #include "py/runtime.h"
 #include "py/stream.h"
 #include "py/mperrno.h"
@@ -556,7 +556,7 @@ STATIC void pyb_uart_print(const mp_print_t *print, mp_obj_t self_in, mp_print_k
 ///   - `timeout_char` is the timeout in milliseconds to wait between characters.
 ///   - `flow` is RTS | CTS where RTS == 256, CTS == 512
 ///   - `read_buf_len` is the character length of the read buffer (0 to disable).
-STATIC mp_obj_t pyb_uart_init_helper(pyb_uart_obj_t *self, mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_uart_init_helper(pyb_uart_obj_t *self, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     static const mp_arg_t allowed_args[] = {
         { MP_QSTR_baudrate, MP_ARG_REQUIRED | MP_ARG_INT, {.u_int = 9600} },
         { MP_QSTR_bits, MP_ARG_INT, {.u_int = 8} },
@@ -783,7 +783,7 @@ STATIC mp_obj_t pyb_uart_make_new(const mp_obj_type_t *type, size_t n_args, size
     return self;
 }
 
-STATIC mp_obj_t pyb_uart_init(mp_uint_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_uart_init(size_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
     return pyb_uart_init_helper(args[0], n_args - 1, args + 1, kw_args);
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_KW(pyb_uart_init_obj, 1, pyb_uart_init);
diff --git a/stmhal/uart.h b/ports/stm32/uart.h
similarity index 100%
rename from stmhal/uart.h
rename to ports/stm32/uart.h
diff --git a/stmhal/usb.c b/ports/stm32/usb.c
similarity index 83%
rename from stmhal/usb.c
rename to ports/stm32/usb.c
index 9a0f1d8c1a..906eb19895 100644
--- a/stmhal/usb.c
+++ b/ports/stm32/usb.c
@@ -54,8 +54,16 @@
 // this will be persistent across a soft-reset
 mp_uint_t pyb_usb_flags = 0;
 
+typedef struct _usb_device_t {
+    uint32_t enabled;
+    USBD_HandleTypeDef hUSBDDevice;
+    usbd_cdc_msc_hid_state_t usbd_cdc_msc_hid_state;
+    usbd_cdc_itf_t usbd_cdc_itf;
+    usbd_hid_itf_t usbd_hid_itf;
+} usb_device_t;
+
 #ifdef USE_DEVICE_MODE
-STATIC USBD_HandleTypeDef hUSBDDevice;
+usb_device_t usb_device;
 pyb_usb_storage_medium_t pyb_usb_storage_medium = PYB_USB_STORAGE_MEDIUM_NONE;
 #endif
 
@@ -104,65 +112,80 @@ void pyb_usb_init0(void) {
 
 bool pyb_usb_dev_init(uint16_t vid, uint16_t pid, usb_device_mode_t mode, USBD_HID_ModeInfoTypeDef *hid_info) {
 #ifdef USE_DEVICE_MODE
-    if (!(pyb_usb_flags & PYB_USB_FLAG_DEV_ENABLED)) {
+    usb_device_t *usb_dev = &usb_device;
+    if (!usb_dev->enabled) {
         // only init USB once in the device's power-lifetime
-        USBD_SetVIDPIDRelease(vid, pid, 0x0200, mode == USBD_MODE_CDC);
-        if (USBD_SelectMode(mode, hid_info) != 0) {
+
+        // configure the VID, PID and the USBD mode (interfaces it will expose)
+        USBD_SetVIDPIDRelease(&usb_dev->usbd_cdc_msc_hid_state, vid, pid, 0x0200, mode == USBD_MODE_CDC);
+        if (USBD_SelectMode(&usb_dev->usbd_cdc_msc_hid_state, mode, hid_info) != 0) {
             return false;
         }
-        USBD_Init(&hUSBDDevice, (USBD_DescriptorsTypeDef*)&USBD_Descriptors, USB_PHY_ID);
-        USBD_RegisterClass(&hUSBDDevice, &USBD_CDC_MSC_HID);
-        USBD_CDC_RegisterInterface(&hUSBDDevice, (USBD_CDC_ItfTypeDef*)&USBD_CDC_fops);
+
+        // set up the USBD state
+        USBD_HandleTypeDef *usbd = &usb_dev->hUSBDDevice;
+        usbd->id = USB_PHY_ID;
+        usbd->dev_state  = USBD_STATE_DEFAULT;
+        usbd->pDesc = (USBD_DescriptorsTypeDef*)&USBD_Descriptors;
+        usbd->pClass = &USBD_CDC_MSC_HID;
+        usb_dev->usbd_cdc_msc_hid_state.pdev = usbd;
+        usb_dev->usbd_cdc_msc_hid_state.cdc = &usb_dev->usbd_cdc_itf;
+        usb_dev->usbd_cdc_msc_hid_state.hid = &usb_dev->usbd_hid_itf;
+        usbd->pClassData = &usb_dev->usbd_cdc_msc_hid_state;
+
         switch (pyb_usb_storage_medium) {
 #if MICROPY_HW_HAS_SDCARD
             case PYB_USB_STORAGE_MEDIUM_SDCARD:
-                USBD_MSC_RegisterStorage(&hUSBDDevice, (USBD_StorageTypeDef*)&USBD_SDCARD_STORAGE_fops);
+                USBD_MSC_RegisterStorage(&usb_dev->usbd_cdc_msc_hid_state, (USBD_StorageTypeDef*)&USBD_SDCARD_STORAGE_fops);
                 break;
 #endif
             default:
-                USBD_MSC_RegisterStorage(&hUSBDDevice, (USBD_StorageTypeDef*)&USBD_FLASH_STORAGE_fops);
+                USBD_MSC_RegisterStorage(&usb_dev->usbd_cdc_msc_hid_state, (USBD_StorageTypeDef*)&USBD_FLASH_STORAGE_fops);
                 break;
         }
-        USBD_HID_RegisterInterface(&hUSBDDevice, (USBD_HID_ItfTypeDef*)&USBD_HID_fops);
-        USBD_Start(&hUSBDDevice);
+
+        // start the USB device
+        USBD_LL_Init(usbd);
+        USBD_LL_Start(usbd);
+        usb_dev->enabled = true;
     }
-    pyb_usb_flags |= PYB_USB_FLAG_DEV_ENABLED;
 #endif
 
     return true;
 }
 
 void pyb_usb_dev_deinit(void) {
-    if (pyb_usb_flags & PYB_USB_FLAG_DEV_ENABLED) {
-        USBD_Stop(&hUSBDDevice);
-        pyb_usb_flags &= ~PYB_USB_FLAG_DEV_ENABLED;
+    usb_device_t *usb_dev = &usb_device;
+    if (usb_dev->enabled) {
+        USBD_Stop(&usb_dev->hUSBDDevice);
+        usb_dev->enabled = false;
     }
 }
 
 bool usb_vcp_is_enabled(void) {
-    return (pyb_usb_flags & PYB_USB_FLAG_DEV_ENABLED) != 0;
+    return usb_device.enabled;
 }
 
 int usb_vcp_recv_byte(uint8_t *c) {
-    return USBD_CDC_Rx(c, 1, 0);
+    return usbd_cdc_rx(&usb_device.usbd_cdc_itf, c, 1, 0);
 }
 
 void usb_vcp_send_strn(const char *str, int len) {
 #ifdef USE_DEVICE_MODE
-    if (pyb_usb_flags & PYB_USB_FLAG_DEV_ENABLED) {
-        USBD_CDC_TxAlways((const uint8_t*)str, len);
+    if (usb_device.enabled) {
+        usbd_cdc_tx_always(&usb_device.usbd_cdc_itf, (const uint8_t*)str, len);
     }
 #endif
 }
 
 void usb_vcp_send_strn_cooked(const char *str, int len) {
 #ifdef USE_DEVICE_MODE
-    if (pyb_usb_flags & PYB_USB_FLAG_DEV_ENABLED) {
+    if (usb_device.enabled) {
         for (const char *top = str + len; str < top; str++) {
             if (*str == '\n') {
-                USBD_CDC_TxAlways((const uint8_t*)"\r\n", 2);
+                usbd_cdc_tx_always(&usb_device.usbd_cdc_itf, (const uint8_t*)"\r\n", 2);
             } else {
-                USBD_CDC_TxAlways((const uint8_t*)str, 1);
+                usbd_cdc_tx_always(&usb_device.usbd_cdc_itf, (const uint8_t*)str, 1);
             }
         }
     }
@@ -198,7 +221,7 @@ void usb_vcp_send_strn_cooked(const char *str, int len) {
     pyb.usb_mode(..., port=2) # for second USB port
 */
 
-STATIC mp_obj_t pyb_usb_mode(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_usb_mode(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     static const mp_arg_t allowed_args[] = {
         { MP_QSTR_mode, MP_ARG_REQUIRED | MP_ARG_OBJ, {.u_obj = mp_const_none} },
         { MP_QSTR_vid, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = USBD_VID} },
@@ -211,7 +234,7 @@ STATIC mp_obj_t pyb_usb_mode(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_
     #if defined(USE_HOST_MODE)
         return MP_OBJ_NEW_QSTR(MP_QSTR_host);
     #elif defined(USE_DEVICE_MODE)
-        uint8_t mode = USBD_GetMode();
+        uint8_t mode = USBD_GetMode(&usb_device.usbd_cdc_msc_hid_state);
         switch (mode) {
             case USBD_MODE_CDC:
                 return MP_OBJ_NEW_QSTR(MP_QSTR_VCP);
@@ -336,9 +359,10 @@ MP_DEFINE_CONST_FUN_OBJ_KW(pyb_usb_mode_obj, 0, pyb_usb_mode);
 
 typedef struct _pyb_usb_vcp_obj_t {
     mp_obj_base_t base;
+    usb_device_t *usb_dev;
 } pyb_usb_vcp_obj_t;
 
-STATIC const pyb_usb_vcp_obj_t pyb_usb_vcp_obj = {{&pyb_usb_vcp_type}};
+STATIC const pyb_usb_vcp_obj_t pyb_usb_vcp_obj = {{&pyb_usb_vcp_type}, &usb_device};
 
 STATIC void pyb_usb_vcp_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) {
     mp_print_str(print, "USB_VCP()");
@@ -363,7 +387,8 @@ STATIC mp_obj_t pyb_usb_vcp_setinterrupt(mp_obj_t self_in, mp_obj_t int_chr_in)
 STATIC MP_DEFINE_CONST_FUN_OBJ_2(pyb_usb_vcp_setinterrupt_obj, pyb_usb_vcp_setinterrupt);
 
 STATIC mp_obj_t pyb_usb_vcp_isconnected(mp_obj_t self_in) {
-    return mp_obj_new_bool(USBD_CDC_IsConnected());
+    pyb_usb_vcp_obj_t *self = MP_OBJ_TO_PTR(self_in);
+    return mp_obj_new_bool(usbd_cdc_is_connected(&self->usb_dev->usbd_cdc_itf));
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_usb_vcp_isconnected_obj, pyb_usb_vcp_isconnected);
 
@@ -376,7 +401,8 @@ MP_DEFINE_CONST_FUN_OBJ_0(pyb_have_cdc_obj, pyb_have_cdc);
 /// \method any()
 /// Return `True` if any characters waiting, else `False`.
 STATIC mp_obj_t pyb_usb_vcp_any(mp_obj_t self_in) {
-    if (USBD_CDC_RxNum() > 0) {
+    pyb_usb_vcp_obj_t *self = MP_OBJ_TO_PTR(self_in);
+    if (usbd_cdc_rx_num(&self->usb_dev->usbd_cdc_itf) > 0) {
         return mp_const_true;
     } else {
         return mp_const_false;
@@ -397,8 +423,9 @@ STATIC const mp_arg_t pyb_usb_vcp_send_args[] = {
 };
 #define PYB_USB_VCP_SEND_NUM_ARGS MP_ARRAY_SIZE(pyb_usb_vcp_send_args)
 
-STATIC mp_obj_t pyb_usb_vcp_send(mp_uint_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_usb_vcp_send(size_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
     // parse args
+    pyb_usb_vcp_obj_t *self = MP_OBJ_TO_PTR(args[0]);
     mp_arg_val_t vals[PYB_USB_VCP_SEND_NUM_ARGS];
     mp_arg_parse_all(n_args - 1, args + 1, kw_args, PYB_USB_VCP_SEND_NUM_ARGS, pyb_usb_vcp_send_args, vals);
 
@@ -408,7 +435,7 @@ STATIC mp_obj_t pyb_usb_vcp_send(mp_uint_t n_args, const mp_obj_t *args, mp_map_
     pyb_buf_get_for_send(vals[0].u_obj, &bufinfo, data);
 
     // send the data
-    int ret = USBD_CDC_Tx(bufinfo.buf, bufinfo.len, vals[1].u_int);
+    int ret = usbd_cdc_tx(&self->usb_dev->usbd_cdc_itf, bufinfo.buf, bufinfo.len, vals[1].u_int);
 
     return mp_obj_new_int(ret);
 }
@@ -424,8 +451,9 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_KW(pyb_usb_vcp_send_obj, 1, pyb_usb_vcp_send);
 ///
 /// Return value: if `data` is an integer then a new buffer of the bytes received,
 /// otherwise the number of bytes read into `data` is returned.
-STATIC mp_obj_t pyb_usb_vcp_recv(mp_uint_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_usb_vcp_recv(size_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
     // parse args
+    pyb_usb_vcp_obj_t *self = MP_OBJ_TO_PTR(args[0]);
     mp_arg_val_t vals[PYB_USB_VCP_SEND_NUM_ARGS];
     mp_arg_parse_all(n_args - 1, args + 1, kw_args, PYB_USB_VCP_SEND_NUM_ARGS, pyb_usb_vcp_send_args, vals);
 
@@ -434,7 +462,7 @@ STATIC mp_obj_t pyb_usb_vcp_recv(mp_uint_t n_args, const mp_obj_t *args, mp_map_
     mp_obj_t o_ret = pyb_buf_get_for_recv(vals[0].u_obj, &vstr);
 
     // receive the data
-    int ret = USBD_CDC_Rx((uint8_t*)vstr.buf, vstr.len, vals[1].u_int);
+    int ret = usbd_cdc_rx(&self->usb_dev->usbd_cdc_itf, (uint8_t*)vstr.buf, vstr.len, vals[1].u_int);
 
     // return the received data
     if (o_ret != MP_OBJ_NULL) {
@@ -446,7 +474,7 @@ STATIC mp_obj_t pyb_usb_vcp_recv(mp_uint_t n_args, const mp_obj_t *args, mp_map_
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_KW(pyb_usb_vcp_recv_obj, 1, pyb_usb_vcp_recv);
 
-mp_obj_t pyb_usb_vcp___exit__(mp_uint_t n_args, const mp_obj_t *args) {
+mp_obj_t pyb_usb_vcp___exit__(size_t n_args, const mp_obj_t *args) {
     return mp_const_none;
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_usb_vcp___exit___obj, 4, 4, pyb_usb_vcp___exit__);
@@ -471,7 +499,8 @@ STATIC const mp_rom_map_elem_t pyb_usb_vcp_locals_dict_table[] = {
 STATIC MP_DEFINE_CONST_DICT(pyb_usb_vcp_locals_dict, pyb_usb_vcp_locals_dict_table);
 
 STATIC mp_uint_t pyb_usb_vcp_read(mp_obj_t self_in, void *buf, mp_uint_t size, int *errcode) {
-    int ret = USBD_CDC_Rx((byte*)buf, size, 0);
+    pyb_usb_vcp_obj_t *self = MP_OBJ_TO_PTR(self_in);
+    int ret = usbd_cdc_rx(&self->usb_dev->usbd_cdc_itf, (byte*)buf, size, 0);
     if (ret == 0) {
         // return EAGAIN error to indicate non-blocking
         *errcode = MP_EAGAIN;
@@ -481,7 +510,8 @@ STATIC mp_uint_t pyb_usb_vcp_read(mp_obj_t self_in, void *buf, mp_uint_t size, i
 }
 
 STATIC mp_uint_t pyb_usb_vcp_write(mp_obj_t self_in, const void *buf, mp_uint_t size, int *errcode) {
-    int ret = USBD_CDC_Tx((const byte*)buf, size, 0);
+    pyb_usb_vcp_obj_t *self = MP_OBJ_TO_PTR(self_in);
+    int ret = usbd_cdc_tx(&self->usb_dev->usbd_cdc_itf, (const byte*)buf, size, 0);
     if (ret == 0) {
         // return EAGAIN error to indicate non-blocking
         *errcode = MP_EAGAIN;
@@ -492,13 +522,14 @@ STATIC mp_uint_t pyb_usb_vcp_write(mp_obj_t self_in, const void *buf, mp_uint_t
 
 STATIC mp_uint_t pyb_usb_vcp_ioctl(mp_obj_t self_in, mp_uint_t request, mp_uint_t arg, int *errcode) {
     mp_uint_t ret;
+    pyb_usb_vcp_obj_t *self = MP_OBJ_TO_PTR(self_in);
     if (request == MP_STREAM_POLL) {
         mp_uint_t flags = arg;
         ret = 0;
-        if ((flags & MP_STREAM_POLL_RD) && USBD_CDC_RxNum() > 0) {
+        if ((flags & MP_STREAM_POLL_RD) && usbd_cdc_rx_num(&self->usb_dev->usbd_cdc_itf) > 0) {
             ret |= MP_STREAM_POLL_RD;
         }
-        if ((flags & MP_STREAM_POLL_WR) && USBD_CDC_TxHalfEmpty()) {
+        if ((flags & MP_STREAM_POLL_WR) && usbd_cdc_tx_half_empty(&self->usb_dev->usbd_cdc_itf)) {
             ret |= MP_STREAM_POLL_WR;
         }
     } else {
@@ -530,9 +561,10 @@ const mp_obj_type_t pyb_usb_vcp_type = {
 
 typedef struct _pyb_usb_hid_obj_t {
     mp_obj_base_t base;
+    usb_device_t *usb_dev;
 } pyb_usb_hid_obj_t;
 
-STATIC const pyb_usb_hid_obj_t pyb_usb_hid_obj = {{&pyb_usb_hid_type}};
+STATIC const pyb_usb_hid_obj_t pyb_usb_hid_obj = {{&pyb_usb_hid_type}, &usb_device};
 
 STATIC mp_obj_t pyb_usb_hid_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args) {
     // check arguments
@@ -554,13 +586,14 @@ STATIC mp_obj_t pyb_usb_hid_make_new(const mp_obj_type_t *type, size_t n_args, s
 ///
 /// Return value: if `data` is an integer then a new buffer of the bytes received,
 /// otherwise the number of bytes read into `data` is returned.
-STATIC mp_obj_t pyb_usb_hid_recv(mp_uint_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_usb_hid_recv(size_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
     static const mp_arg_t allowed_args[] = {
         { MP_QSTR_data,    MP_ARG_REQUIRED | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
         { MP_QSTR_timeout, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 5000} },
     };
 
     // parse args
+    pyb_usb_vcp_obj_t *self = MP_OBJ_TO_PTR(args[0]);
     mp_arg_val_t vals[MP_ARRAY_SIZE(allowed_args)];
     mp_arg_parse_all(n_args - 1, args + 1, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, vals);
 
@@ -569,7 +602,7 @@ STATIC mp_obj_t pyb_usb_hid_recv(mp_uint_t n_args, const mp_obj_t *args, mp_map_
     mp_obj_t o_ret = pyb_buf_get_for_recv(vals[0].u_obj, &vstr);
 
     // receive the data
-    int ret = USBD_HID_Rx(&hUSBDDevice, (uint8_t*)vstr.buf, vstr.len, vals[1].u_int);
+    int ret = usbd_hid_rx(&self->usb_dev->usbd_hid_itf, vstr.len, (uint8_t*)vstr.buf, vals[1].u_int);
 
     // return the received data
     if (o_ret != MP_OBJ_NULL) {
@@ -583,6 +616,7 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_KW(pyb_usb_hid_recv_obj, 1, pyb_usb_hid_recv);
 
 STATIC mp_obj_t pyb_usb_hid_send(mp_obj_t self_in, mp_obj_t report_in) {
 #ifdef USE_DEVICE_MODE
+    pyb_usb_vcp_obj_t *self = MP_OBJ_TO_PTR(self_in);
     mp_buffer_info_t bufinfo;
     byte temp_buf[8];
     // get the buffer to send from
@@ -600,7 +634,7 @@ STATIC mp_obj_t pyb_usb_hid_send(mp_obj_t self_in, mp_obj_t report_in) {
     }
 
     // send the data
-    if (USBD_OK == USBD_HID_SendReport(&hUSBDDevice, bufinfo.buf, bufinfo.len)) {
+    if (USBD_OK == USBD_HID_SendReport(&self->usb_dev->usbd_cdc_msc_hid_state, bufinfo.buf, bufinfo.len)) {
         return mp_obj_new_int(bufinfo.len);
     } else {
         return mp_obj_new_int(0);
@@ -613,7 +647,7 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_2(pyb_usb_hid_send_obj, pyb_usb_hid_send);
 
 // deprecated in favour of USB_HID.send
 STATIC mp_obj_t pyb_hid_send_report(mp_obj_t arg) {
-    return pyb_usb_hid_send(MP_OBJ_NULL, arg);
+    return pyb_usb_hid_send(MP_OBJ_FROM_PTR(&pyb_usb_hid_obj), arg);
 }
 MP_DEFINE_CONST_FUN_OBJ_1(pyb_hid_send_report_obj, pyb_hid_send_report);
 
@@ -625,14 +659,15 @@ STATIC const mp_rom_map_elem_t pyb_usb_hid_locals_dict_table[] = {
 STATIC MP_DEFINE_CONST_DICT(pyb_usb_hid_locals_dict, pyb_usb_hid_locals_dict_table);
 
 STATIC mp_uint_t pyb_usb_hid_ioctl(mp_obj_t self_in, mp_uint_t request, mp_uint_t arg, int *errcode) {
+    pyb_usb_vcp_obj_t *self = MP_OBJ_TO_PTR(self_in);
     mp_uint_t ret;
     if (request == MP_STREAM_POLL) {
         mp_uint_t flags = arg;
         ret = 0;
-        if ((flags & MP_STREAM_POLL_RD) && USBD_HID_RxNum() > 0) {
+        if ((flags & MP_STREAM_POLL_RD) && usbd_hid_rx_num(&self->usb_dev->usbd_hid_itf) > 0) {
             ret |= MP_STREAM_POLL_RD;
         }
-        if ((flags & MP_STREAM_POLL_WR) && USBD_HID_CanSendReport(&hUSBDDevice)) {
+        if ((flags & MP_STREAM_POLL_WR) && USBD_HID_CanSendReport(&self->usb_dev->usbd_cdc_msc_hid_state)) {
             ret |= MP_STREAM_POLL_WR;
         }
     } else {
diff --git a/stmhal/usb.h b/ports/stm32/usb.h
similarity index 96%
rename from stmhal/usb.h
rename to ports/stm32/usb.h
index d39f49a6cc..f60ea80336 100644
--- a/stmhal/usb.h
+++ b/ports/stm32/usb.h
@@ -28,7 +28,6 @@
 
 #include "usbd_cdc_msc_hid0.h"
 
-#define PYB_USB_FLAG_DEV_ENABLED        (0x0001)
 #define PYB_USB_FLAG_USB_MODE_CALLED    (0x0002)
 
 // Windows needs a different PID to distinguish different device configurations
@@ -44,8 +43,8 @@ typedef enum {
 } pyb_usb_storage_medium_t;
 
 typedef enum {
-	USB_PHY_FS_ID = 0,
-	USB_PHY_HS_ID = 1,
+    USB_PHY_FS_ID = 0,
+    USB_PHY_HS_ID = 1,
 } USB_PHY_ID;
 
 extern mp_uint_t pyb_usb_flags;
diff --git a/stmhal/usbd_cdc_interface.c b/ports/stm32/usbd_cdc_interface.c
similarity index 59%
rename from stmhal/usbd_cdc_interface.c
rename to ports/stm32/usbd_cdc_interface.c
index 3e107d418e..4c49c9321f 100644
--- a/stmhal/usbd_cdc_interface.c
+++ b/ports/stm32/usbd_cdc_interface.c
@@ -41,12 +41,9 @@
 #include "usbd_cdc_interface.h"
 #include "pendsv.h"
 
-#include "py/mpstate.h"
 #include "py/obj.h"
 #include "lib/utils/interrupt_char.h"
 #include "irq.h"
-#include "timer.h"
-#include "usb.h"
 
 // CDC control commands
 #define CDC_SEND_ENCAPSULATED_COMMAND               0x00
@@ -59,78 +56,27 @@
 #define CDC_SET_CONTROL_LINE_STATE                  0x22
 #define CDC_SEND_BREAK                              0x23
 
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define APP_RX_DATA_SIZE  1024 // this must be 2 or greater, and a power of 2
-#define APP_TX_DATA_SIZE  1024 // I think this can be any value (was 2048)
+uint8_t *usbd_cdc_init(usbd_cdc_itf_t *cdc, usbd_cdc_msc_hid_state_t *usbd) {
+    cdc->usbd = usbd;
+    cdc->rx_buf_put = 0;
+    cdc->rx_buf_get = 0;
+    cdc->tx_buf_ptr_in = 0;
+    cdc->tx_buf_ptr_out = 0;
+    cdc->tx_buf_ptr_out_shadow = 0;
+    cdc->tx_buf_ptr_wait_count = 0;
+    cdc->tx_need_empty_packet = 0;
+    cdc->dev_is_connected = 0;
 
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-static __IO uint8_t dev_is_connected = 0; // indicates if we are connected
-
-static uint8_t cdc_rx_packet_buf[CDC_DATA_FS_MAX_PACKET_SIZE]; // received data from USB OUT endpoint is stored in this buffer
-static uint8_t cdc_rx_user_buf[APP_RX_DATA_SIZE]; // received data is buffered here until the user reads it
-static volatile uint16_t cdc_rx_buf_put = 0; // circular buffer index
-static uint16_t cdc_rx_buf_get = 0; // circular buffer index
-
-static uint8_t UserTxBuffer[APP_TX_DATA_SIZE]; // data for USB IN endpoind is stored in this buffer
-static uint16_t UserTxBufPtrIn = 0; // increment this pointer modulo APP_TX_DATA_SIZE when new data is available
-static __IO uint16_t UserTxBufPtrOut = 0; // increment this pointer modulo APP_TX_DATA_SIZE when data is drained
-static uint16_t UserTxBufPtrOutShadow = 0; // shadow of above
-static uint8_t UserTxBufPtrWaitCount = 0; // used to implement a timeout waiting for low-level USB driver
-static uint8_t UserTxNeedEmptyPacket = 0; // used to flush the USB IN endpoint if the last packet was exactly the endpoint packet size
-
-/* Private function prototypes -----------------------------------------------*/
-static int8_t CDC_Itf_Init     (USBD_HandleTypeDef *pdev);
-static int8_t CDC_Itf_DeInit   (void);
-static int8_t CDC_Itf_Control  (uint8_t cmd, uint8_t* pbuf, uint16_t length);
-static int8_t CDC_Itf_Receive  (USBD_HandleTypeDef *pdev, uint8_t* pbuf, uint32_t *Len);
-
-const USBD_CDC_ItfTypeDef USBD_CDC_fops = {
-    CDC_Itf_Init,
-    CDC_Itf_DeInit,
-    CDC_Itf_Control,
-    CDC_Itf_Receive
-};
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  CDC_Itf_Init
-  *         Initializes the CDC media low layer
-  * @param  None
-  * @retval Result of the opeartion: USBD_OK if all operations are OK else USBD_FAIL
-  */
-static int8_t CDC_Itf_Init(USBD_HandleTypeDef *pdev) {
-    USBD_CDC_SetTxBuffer(pdev, UserTxBuffer, 0);
-    USBD_CDC_SetRxBuffer(pdev, cdc_rx_packet_buf);
-
-    cdc_rx_buf_put = 0;
-    cdc_rx_buf_get = 0;
-
-    return USBD_OK;
+    // Return the buffer to place the first USB OUT packet
+    return cdc->rx_packet_buf;
 }
 
-/**
-  * @brief  CDC_Itf_DeInit
-  *         DeInitializes the CDC media low layer
-  * @param  None
-  * @retval Result of the opeartion: USBD_OK if all operations are OK else USBD_FAIL
-  */
-static int8_t CDC_Itf_DeInit(void) {
-    return USBD_OK;
-}
-
-/**
-  * @brief  CDC_Itf_Control
-  *         Manage the CDC class requests
-  * @param  Cmd: Command code
-  * @param  Buf: Buffer containing command data (request parameters)
-  * @param  Len: Number of data to be sent (in bytes)
-  * @retval Result of the opeartion: USBD_OK if all operations are OK else USBD_FAIL
-  */
-static int8_t CDC_Itf_Control(uint8_t cmd, uint8_t* pbuf, uint16_t length) {
+// Manage the CDC class requests
+// cmd: command code
+// pbuf: buffer containing command data (request parameters)
+// length: number of data to be sent (in bytes)
+// Returns USBD_OK if all operations are OK else USBD_FAIL
+int8_t usbd_cdc_control(usbd_cdc_itf_t *cdc, uint8_t cmd, uint8_t* pbuf, uint16_t length) {
     switch (cmd) {
         case CDC_SEND_ENCAPSULATED_COMMAND:
             /* Add your code here */
@@ -175,7 +121,7 @@ static int8_t CDC_Itf_Control(uint8_t cmd, uint8_t* pbuf, uint16_t length) {
             break;
 
         case CDC_SET_CONTROL_LINE_STATE:
-            dev_is_connected = length & 1; // wValue is passed in Len (bit of a hack)
+            cdc->dev_is_connected = length & 1; // wValue is passed in Len (bit of a hack)
             break;
 
         case CDC_SEND_BREAK:
@@ -193,53 +139,54 @@ static int8_t CDC_Itf_Control(uint8_t cmd, uint8_t* pbuf, uint16_t length) {
 // SOF (start of frame) callback so that it is called exactly at the time it is
 // needed (reducing latency), and often enough (increasing bandwidth).
 void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) {
-    if (!dev_is_connected) {
+    usbd_cdc_msc_hid_state_t *usbd = ((USBD_HandleTypeDef*)hpcd->pData)->pClassData;
+    usbd_cdc_itf_t *cdc = usbd->cdc;
+
+    if (cdc == NULL || !cdc->dev_is_connected) {
         // CDC device is not connected to a host, so we are unable to send any data
         return;
     }
 
-    if (UserTxBufPtrOut == UserTxBufPtrIn && !UserTxNeedEmptyPacket) {
+    if (cdc->tx_buf_ptr_out == cdc->tx_buf_ptr_in && !cdc->tx_need_empty_packet) {
         // No outstanding data to send
         return;
     }
 
-    if (UserTxBufPtrOut != UserTxBufPtrOutShadow) {
+    if (cdc->tx_buf_ptr_out != cdc->tx_buf_ptr_out_shadow) {
         // We have sent data and are waiting for the low-level USB driver to
         // finish sending it over the USB in-endpoint.
         // SOF occurs every 1ms, so we have a 500 * 1ms = 500ms timeout
         // We have a relatively large timeout because the USB host may be busy
         // doing other things and we must give it a chance to read our data.
-        if (UserTxBufPtrWaitCount < 500) {
+        if (cdc->tx_buf_ptr_wait_count < 500) {
             USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
             if (USBx_INEP(CDC_IN_EP & 0x7f)->DIEPTSIZ & USB_OTG_DIEPTSIZ_XFRSIZ) {
                 // USB in-endpoint is still reading the data
-                UserTxBufPtrWaitCount++;
+                cdc->tx_buf_ptr_wait_count++;
                 return;
             }
         }
-        UserTxBufPtrOut = UserTxBufPtrOutShadow;
+        cdc->tx_buf_ptr_out = cdc->tx_buf_ptr_out_shadow;
     }
 
-    if (UserTxBufPtrOutShadow != UserTxBufPtrIn || UserTxNeedEmptyPacket) {
+    if (cdc->tx_buf_ptr_out_shadow != cdc->tx_buf_ptr_in || cdc->tx_need_empty_packet) {
         uint32_t buffptr;
         uint32_t buffsize;
 
-        if (UserTxBufPtrOutShadow > UserTxBufPtrIn) { // rollback
-            buffsize = APP_TX_DATA_SIZE - UserTxBufPtrOutShadow;
+        if (cdc->tx_buf_ptr_out_shadow > cdc->tx_buf_ptr_in) { // rollback
+            buffsize = USBD_CDC_TX_DATA_SIZE - cdc->tx_buf_ptr_out_shadow;
         } else {
-            buffsize = UserTxBufPtrIn - UserTxBufPtrOutShadow;
+            buffsize = cdc->tx_buf_ptr_in - cdc->tx_buf_ptr_out_shadow;
         }
 
-        buffptr = UserTxBufPtrOutShadow;
+        buffptr = cdc->tx_buf_ptr_out_shadow;
 
-        USBD_CDC_SetTxBuffer(hpcd->pData, (uint8_t*)&UserTxBuffer[buffptr], buffsize);
-
-        if (USBD_CDC_TransmitPacket(hpcd->pData) == USBD_OK) {
-            UserTxBufPtrOutShadow += buffsize;
-            if (UserTxBufPtrOutShadow == APP_TX_DATA_SIZE) {
-                UserTxBufPtrOutShadow = 0;
+        if (USBD_CDC_TransmitPacket(cdc->usbd, buffsize, &cdc->tx_buf[buffptr]) == USBD_OK) {
+            cdc->tx_buf_ptr_out_shadow += buffsize;
+            if (cdc->tx_buf_ptr_out_shadow == USBD_CDC_TX_DATA_SIZE) {
+                cdc->tx_buf_ptr_out_shadow = 0;
             }
-            UserTxBufPtrWaitCount = 0;
+            cdc->tx_buf_ptr_wait_count = 0;
 
             // According to the USB specification, a packet size of 64 bytes (CDC_DATA_FS_MAX_PACKET_SIZE)
             // gets held at the USB host until the next packet is sent.  This is because a
@@ -247,62 +194,51 @@ void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) {
             // the host waits for all data to arrive (ie, waits for a packet < max packet size).
             // To flush a packet of exactly max packet size, we need to send a zero-size packet.
             // See eg http://www.cypress.com/?id=4&rID=92719
-            UserTxNeedEmptyPacket = (buffsize > 0 && buffsize % CDC_DATA_FS_MAX_PACKET_SIZE == 0 && UserTxBufPtrOutShadow == UserTxBufPtrIn);
+            cdc->tx_need_empty_packet = (buffsize > 0 && buffsize % CDC_DATA_FS_MAX_PACKET_SIZE == 0 && cdc->tx_buf_ptr_out_shadow == cdc->tx_buf_ptr_in);
         }
     }
 }
 
-/**
-  * @brief  CDC_Itf_DataRx
-  *         Data received over USB OUT endpoint is processed here.
-  * @param  Buf: Buffer of data received
-  * @param  Len: Number of data received (in bytes)
-  * @retval Result of the opeartion: USBD_OK if all operations are OK else USBD_FAIL
-  * @note   The buffer we are passed here is just cdc_rx_packet_buf, so we are
-  *         free to modify it.
-  */
-static int8_t CDC_Itf_Receive(USBD_HandleTypeDef *pdev, uint8_t* Buf, uint32_t *Len) {
+// Data received over USB OUT endpoint is processed here.
+// len: number of bytes received into the buffer we passed to USBD_CDC_ReceivePacket
+// Returns USBD_OK if all operations are OK else USBD_FAIL
+int8_t usbd_cdc_receive(usbd_cdc_itf_t *cdc, size_t len) {
     // copy the incoming data into the circular buffer
-    for (uint8_t *src = Buf, *top = Buf + *Len; src < top; ++src) {
+    for (const uint8_t *src = cdc->rx_packet_buf, *top = cdc->rx_packet_buf + len; src < top; ++src) {
         if (mp_interrupt_char != -1 && *src == mp_interrupt_char) {
             pendsv_kbd_intr();
         } else {
-            uint16_t next_put = (cdc_rx_buf_put + 1) & (APP_RX_DATA_SIZE - 1);
-            if (next_put == cdc_rx_buf_get) {
+            uint16_t next_put = (cdc->rx_buf_put + 1) & (USBD_CDC_RX_DATA_SIZE - 1);
+            if (next_put == cdc->rx_buf_get) {
                 // overflow, we just discard the rest of the chars
                 break;
             }
-            cdc_rx_user_buf[cdc_rx_buf_put] = *src;
-            cdc_rx_buf_put = next_put;
+            cdc->rx_user_buf[cdc->rx_buf_put] = *src;
+            cdc->rx_buf_put = next_put;
         }
     }
 
     // initiate next USB packet transfer
-    USBD_CDC_SetRxBuffer(pdev, cdc_rx_packet_buf);
-    USBD_CDC_ReceivePacket(pdev);
+    USBD_CDC_ReceivePacket(cdc->usbd, cdc->rx_packet_buf);
 
     return USBD_OK;
 }
 
-int USBD_CDC_IsConnected(void) {
-    return dev_is_connected;
-}
-
-int USBD_CDC_TxHalfEmpty(void) {
-    int32_t tx_waiting = (int32_t)UserTxBufPtrIn - (int32_t)UserTxBufPtrOut;
+int usbd_cdc_tx_half_empty(usbd_cdc_itf_t *cdc) {
+    int32_t tx_waiting = (int32_t)cdc->tx_buf_ptr_in - (int32_t)cdc->tx_buf_ptr_out;
     if (tx_waiting < 0) {
-        tx_waiting += APP_TX_DATA_SIZE;
+        tx_waiting += USBD_CDC_TX_DATA_SIZE;
     }
-    return tx_waiting <= APP_TX_DATA_SIZE / 2;
+    return tx_waiting <= USBD_CDC_TX_DATA_SIZE / 2;
 }
 
 // timout in milliseconds.
 // Returns number of bytes written to the device.
-int USBD_CDC_Tx(const uint8_t *buf, uint32_t len, uint32_t timeout) {
+int usbd_cdc_tx(usbd_cdc_itf_t *cdc, const uint8_t *buf, uint32_t len, uint32_t timeout) {
     for (uint32_t i = 0; i < len; i++) {
         // Wait until the device is connected and the buffer has space, with a given timeout
         uint32_t start = HAL_GetTick();
-        while (!dev_is_connected || ((UserTxBufPtrIn + 1) & (APP_TX_DATA_SIZE - 1)) == UserTxBufPtrOut) {
+        while (!cdc->dev_is_connected || ((cdc->tx_buf_ptr_in + 1) & (USBD_CDC_TX_DATA_SIZE - 1)) == cdc->tx_buf_ptr_out) {
             // Wraparound of tick is taken care of by 2's complement arithmetic.
             if (HAL_GetTick() - start >= timeout) {
                 // timeout
@@ -316,8 +252,8 @@ int USBD_CDC_Tx(const uint8_t *buf, uint32_t len, uint32_t timeout) {
         }
 
         // Write data to device buffer
-        UserTxBuffer[UserTxBufPtrIn] = buf[i];
-        UserTxBufPtrIn = (UserTxBufPtrIn + 1) & (APP_TX_DATA_SIZE - 1);
+        cdc->tx_buf[cdc->tx_buf_ptr_in] = buf[i];
+        cdc->tx_buf_ptr_in = (cdc->tx_buf_ptr_in + 1) & (USBD_CDC_TX_DATA_SIZE - 1);
     }
 
     // Success, return number of bytes read
@@ -327,18 +263,18 @@ int USBD_CDC_Tx(const uint8_t *buf, uint32_t len, uint32_t timeout) {
 // Always write all of the data to the device tx buffer, even if the
 // device is not connected, or if the buffer is full.  Has a small timeout
 // to wait for the buffer to be drained, in the case the device is connected.
-void USBD_CDC_TxAlways(const uint8_t *buf, uint32_t len) {
+void usbd_cdc_tx_always(usbd_cdc_itf_t *cdc, const uint8_t *buf, uint32_t len) {
     for (int i = 0; i < len; i++) {
         // If the CDC device is not connected to the host then we don't have anyone to receive our data.
         // The device may become connected in the future, so we should at least try to fill the buffer
         // and hope that it doesn't overflow by the time the device connects.
         // If the device is not connected then we should go ahead and fill the buffer straight away,
         // ignoring overflow.  Otherwise, we should make sure that we have enough room in the buffer.
-        if (dev_is_connected) {
+        if (cdc->dev_is_connected) {
             // If the buffer is full, wait until it gets drained, with a timeout of 500ms
             // (wraparound of tick is taken care of by 2's complement arithmetic).
             uint32_t start = HAL_GetTick();
-            while (((UserTxBufPtrIn + 1) & (APP_TX_DATA_SIZE - 1)) == UserTxBufPtrOut && HAL_GetTick() - start <= 500) {
+            while (((cdc->tx_buf_ptr_in + 1) & (USBD_CDC_TX_DATA_SIZE - 1)) == cdc->tx_buf_ptr_out && HAL_GetTick() - start <= 500) {
                 if (query_irq() == IRQ_STATE_DISABLED) {
                     // IRQs disabled so buffer will never be drained; exit loop
                     break;
@@ -365,28 +301,28 @@ void USBD_CDC_TxAlways(const uint8_t *buf, uint32_t len) {
             */
         }
 
-        UserTxBuffer[UserTxBufPtrIn] = buf[i];
-        UserTxBufPtrIn = (UserTxBufPtrIn + 1) & (APP_TX_DATA_SIZE - 1);
+        cdc->tx_buf[cdc->tx_buf_ptr_in] = buf[i];
+        cdc->tx_buf_ptr_in = (cdc->tx_buf_ptr_in + 1) & (USBD_CDC_TX_DATA_SIZE - 1);
     }
 }
 
 // Returns number of bytes in the rx buffer.
-int USBD_CDC_RxNum(void) {
-    int32_t rx_waiting = (int32_t)cdc_rx_buf_put - (int32_t)cdc_rx_buf_get;
+int usbd_cdc_rx_num(usbd_cdc_itf_t *cdc) {
+    int32_t rx_waiting = (int32_t)cdc->rx_buf_put - (int32_t)cdc->rx_buf_get;
     if (rx_waiting < 0) {
-        rx_waiting += APP_RX_DATA_SIZE;
+        rx_waiting += USBD_CDC_RX_DATA_SIZE;
     }
     return rx_waiting;
 }
 
 // timout in milliseconds.
 // Returns number of bytes read from the device.
-int USBD_CDC_Rx(uint8_t *buf, uint32_t len, uint32_t timeout) {
+int usbd_cdc_rx(usbd_cdc_itf_t *cdc, uint8_t *buf, uint32_t len, uint32_t timeout) {
     // loop to read bytes
     for (uint32_t i = 0; i < len; i++) {
         // Wait until we have at least 1 byte to read
         uint32_t start = HAL_GetTick();
-        while (cdc_rx_buf_put == cdc_rx_buf_get) {
+        while (cdc->rx_buf_put == cdc->rx_buf_get) {
             // Wraparound of tick is taken care of by 2's complement arithmetic.
             if (HAL_GetTick() - start >= timeout) {
                 // timeout
@@ -400,8 +336,8 @@ int USBD_CDC_Rx(uint8_t *buf, uint32_t len, uint32_t timeout) {
         }
 
         // Copy byte from device to user buffer
-        buf[i] = cdc_rx_user_buf[cdc_rx_buf_get];
-        cdc_rx_buf_get = (cdc_rx_buf_get + 1) & (APP_RX_DATA_SIZE - 1);
+        buf[i] = cdc->rx_user_buf[cdc->rx_buf_get];
+        cdc->rx_buf_get = (cdc->rx_buf_get + 1) & (USBD_CDC_RX_DATA_SIZE - 1);
     }
 
     // Success, return number of bytes read
diff --git a/ports/stm32/usbd_cdc_interface.h b/ports/stm32/usbd_cdc_interface.h
new file mode 100644
index 0000000000..6dcab7d479
--- /dev/null
+++ b/ports/stm32/usbd_cdc_interface.h
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ */
+#ifndef MICROPY_INCLUDED_STMHAL_USBD_CDC_INTERFACE_H
+#define MICROPY_INCLUDED_STMHAL_USBD_CDC_INTERFACE_H
+
+/**
+  ******************************************************************************
+  * @file    USB_Device/CDC_Standalone/Inc/usbd_cdc_interface.h
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    26-February-2014
+  * @brief   Header for usbd_cdc_interface.c file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an "AS IS" BASIS,
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+#define USBD_CDC_RX_DATA_SIZE (1024) // this must be 2 or greater, and a power of 2
+#define USBD_CDC_TX_DATA_SIZE (1024) // I think this can be any value (was 2048)
+
+typedef struct _usbd_cdc_itf_t {
+    usbd_cdc_msc_hid_state_t *usbd; // the parent USB device
+
+    uint8_t rx_packet_buf[CDC_DATA_FS_MAX_PACKET_SIZE]; // received data from USB OUT endpoint is stored in this buffer
+    uint8_t rx_user_buf[USBD_CDC_RX_DATA_SIZE]; // received data is buffered here until the user reads it
+    volatile uint16_t rx_buf_put; // circular buffer index
+    uint16_t rx_buf_get; // circular buffer index
+
+    uint8_t tx_buf[USBD_CDC_TX_DATA_SIZE]; // data for USB IN endpoind is stored in this buffer
+    uint16_t tx_buf_ptr_in; // increment this pointer modulo APP_TX_DATA_SIZE when new data is available
+    volatile uint16_t tx_buf_ptr_out; // increment this pointer modulo APP_TX_DATA_SIZE when data is drained
+    uint16_t tx_buf_ptr_out_shadow; // shadow of above
+    uint8_t tx_buf_ptr_wait_count; // used to implement a timeout waiting for low-level USB driver
+    uint8_t tx_need_empty_packet; // used to flush the USB IN endpoint if the last packet was exactly the endpoint packet size
+
+    volatile uint8_t dev_is_connected; // indicates if we are connected
+} usbd_cdc_itf_t;
+
+static inline int usbd_cdc_is_connected(usbd_cdc_itf_t *cdc) {
+    return cdc->dev_is_connected;
+}
+
+int usbd_cdc_tx_half_empty(usbd_cdc_itf_t *cdc);
+int usbd_cdc_tx(usbd_cdc_itf_t *cdc, const uint8_t *buf, uint32_t len, uint32_t timeout);
+void usbd_cdc_tx_always(usbd_cdc_itf_t *cdc, const uint8_t *buf, uint32_t len);
+
+int usbd_cdc_rx_num(usbd_cdc_itf_t *cdc);
+int usbd_cdc_rx(usbd_cdc_itf_t *cdc, uint8_t *buf, uint32_t len, uint32_t timeout);
+
+#endif // MICROPY_INCLUDED_STMHAL_USBD_CDC_INTERFACE_H
diff --git a/stmhal/usbd_conf.c b/ports/stm32/usbd_conf.c
similarity index 100%
rename from stmhal/usbd_conf.c
rename to ports/stm32/usbd_conf.c
diff --git a/stmhal/usbd_conf.h b/ports/stm32/usbd_conf.h
similarity index 100%
rename from stmhal/usbd_conf.h
rename to ports/stm32/usbd_conf.h
diff --git a/stmhal/usbd_desc.c b/ports/stm32/usbd_desc.c
similarity index 61%
rename from stmhal/usbd_desc.c
rename to ports/stm32/usbd_desc.c
index 09e1608c84..1de75aee0f 100644
--- a/stmhal/usbd_desc.c
+++ b/ports/stm32/usbd_desc.c
@@ -50,59 +50,45 @@
 #define USBD_CONFIGURATION_FS_STRING  "Pyboard Config"
 #define USBD_INTERFACE_FS_STRING      "Pyboard Interface"
 
-// USB Standard Device Descriptor
-// needs to be in RAM because we modify the VID and PID
-__ALIGN_BEGIN static uint8_t hUSBDDeviceDesc[USB_LEN_DEV_DESC] __ALIGN_END = {
-    0x12,                       // bLength
-    USB_DESC_TYPE_DEVICE,       // bDescriptorType
-    0x00,                       // bcdUSB
-    0x02,
-    0xef,                       // bDeviceClass: Miscellaneous Device Class
-    0x02,                       // bDeviceSubClass: Common Class
-    0x01,                       // bDeviceProtocol: Interface Association Descriptor
-    USB_MAX_EP0_SIZE,           // bMaxPacketSize
-    LOBYTE(USBD_VID),           // idVendor
-    HIBYTE(USBD_VID),           // idVendor
-    LOBYTE(USBD_PID),           // idVendor
-    HIBYTE(USBD_PID),           // idVendor
-    0x00,                       // bcdDevice rel. 2.00
-    0x02,
-    USBD_IDX_MFC_STR,           // Index of manufacturer string
-    USBD_IDX_PRODUCT_STR,       // Index of product string
-    USBD_IDX_SERIAL_STR,        // Index of serial number string
-    USBD_MAX_NUM_CONFIGURATION  // bNumConfigurations
-};
-
-__ALIGN_BEGIN static uint8_t USBD_LangIDDesc[USB_LEN_LANGID_STR_DESC] __ALIGN_END = {
+__ALIGN_BEGIN static const uint8_t USBD_LangIDDesc[USB_LEN_LANGID_STR_DESC] __ALIGN_END = {
     USB_LEN_LANGID_STR_DESC,
     USB_DESC_TYPE_STRING,
     LOBYTE(USBD_LANGID_STRING),
     HIBYTE(USBD_LANGID_STRING),
 };
 
-__ALIGN_BEGIN static uint8_t USBD_StrDesc[USBD_MAX_STR_DESC_SIZ] __ALIGN_END;
-
 // set the VID, PID and device release number
-void USBD_SetVIDPIDRelease(uint16_t vid, uint16_t pid, uint16_t device_release_num, int cdc_only) {
+void USBD_SetVIDPIDRelease(usbd_cdc_msc_hid_state_t *usbd, uint16_t vid, uint16_t pid, uint16_t device_release_num, int cdc_only) {
+    uint8_t *dev_desc = &usbd->usbd_device_desc[0];
+
+    dev_desc[0] = USB_LEN_DEV_DESC; // bLength
+    dev_desc[1] = USB_DESC_TYPE_DEVICE; // bDescriptorType
+    dev_desc[2] = 0x00; // bcdUSB
+    dev_desc[3] = 0x02; // bcdUSB
     if (cdc_only) {
         // Make it look like a Communications device if we're only
         // using CDC. Otherwise, windows gets confused when we tell it that
         // its a composite device with only a cdc serial interface.
-        hUSBDDeviceDesc[4] = 0x02;
-        hUSBDDeviceDesc[5] = 0x00;
-        hUSBDDeviceDesc[6] = 0x00;
+        dev_desc[4] = 0x02; // bDeviceClass
+        dev_desc[5] = 0x00; // bDeviceSubClass
+        dev_desc[6] = 0x00; // bDeviceProtocol
     } else {
         // For the other modes, we make this look like a composite device.
-        hUSBDDeviceDesc[4] = 0xef;
-        hUSBDDeviceDesc[5] = 0x02;
-        hUSBDDeviceDesc[6] = 0x01;
+        dev_desc[4] = 0xef; // bDeviceClass: Miscellaneous Device Class
+        dev_desc[5] = 0x02; // bDeviceSubClass: Common Class
+        dev_desc[6] = 0x01; // bDeviceProtocol: Interface Association Descriptor
     }
-    hUSBDDeviceDesc[8] = LOBYTE(vid);
-    hUSBDDeviceDesc[9] = HIBYTE(vid);
-    hUSBDDeviceDesc[10] = LOBYTE(pid);
-    hUSBDDeviceDesc[11] = HIBYTE(pid);
-    hUSBDDeviceDesc[12] = LOBYTE(device_release_num);
-    hUSBDDeviceDesc[13] = HIBYTE(device_release_num);
+    dev_desc[7] = USB_MAX_EP0_SIZE; // bMaxPacketSize
+    dev_desc[8] = LOBYTE(vid); // idVendor
+    dev_desc[9] = HIBYTE(vid); // idVendor
+    dev_desc[10] = LOBYTE(pid); // idVendor
+    dev_desc[11] = HIBYTE(pid); // idVendor
+    dev_desc[12] = LOBYTE(device_release_num); // bcdDevice
+    dev_desc[13] = HIBYTE(device_release_num); // bcdDevice
+    dev_desc[14] = USBD_IDX_MFC_STR; // Index of manufacturer string
+    dev_desc[15] = USBD_IDX_PRODUCT_STR; // Index of product string
+    dev_desc[16] = USBD_IDX_SERIAL_STR; // Index of serial number string
+    dev_desc[17] = USBD_MAX_NUM_CONFIGURATION; // bNumConfigurations
 }
 
 /**
@@ -111,9 +97,10 @@ void USBD_SetVIDPIDRelease(uint16_t vid, uint16_t pid, uint16_t device_release_n
   * @param  length: Pointer to data length variable
   * @retval Pointer to descriptor buffer
   */
-STATIC uint8_t *USBD_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) {
-    *length = sizeof(hUSBDDeviceDesc);
-    return hUSBDDeviceDesc;
+STATIC uint8_t *USBD_DeviceDescriptor(USBD_HandleTypeDef *pdev, uint16_t *length) {
+    uint8_t *dev_desc = ((usbd_cdc_msc_hid_state_t*)pdev->pClassData)->usbd_device_desc;
+    *length = USB_LEN_DEV_DESC;
+    return dev_desc;
 }
 
 /**
@@ -122,9 +109,9 @@ STATIC uint8_t *USBD_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
   * @param  length: Pointer to data length variable
   * @retval Pointer to descriptor buffer
   */
-STATIC uint8_t *USBD_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) {
+STATIC uint8_t *USBD_LangIDStrDescriptor(USBD_HandleTypeDef *pdev, uint16_t *length) {
     *length = sizeof(USBD_LangIDDesc);
-    return USBD_LangIDDesc;
+    return (uint8_t*)USBD_LangIDDesc; // the data should only be read from this buf
 }
 
 /**
@@ -133,13 +120,14 @@ STATIC uint8_t *USBD_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *leng
   * @param  length: Pointer to data length variable
   * @retval Pointer to descriptor buffer
   */
-STATIC uint8_t *USBD_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) {
-    if(speed == 0) {
-        USBD_GetString((uint8_t *)USBD_PRODUCT_HS_STRING, USBD_StrDesc, length);
+STATIC uint8_t *USBD_ProductStrDescriptor(USBD_HandleTypeDef *pdev, uint16_t *length) {
+    uint8_t *str_desc = ((usbd_cdc_msc_hid_state_t*)pdev->pClassData)->usbd_str_desc;
+    if (pdev->dev_speed == USBD_SPEED_HIGH) {
+        USBD_GetString((uint8_t *)USBD_PRODUCT_HS_STRING, str_desc, length);
     } else {
-        USBD_GetString((uint8_t *)USBD_PRODUCT_FS_STRING, USBD_StrDesc, length);
+        USBD_GetString((uint8_t *)USBD_PRODUCT_FS_STRING, str_desc, length);
     }
-    return USBD_StrDesc;
+    return str_desc;
 }
 
 /**
@@ -148,9 +136,10 @@ STATIC uint8_t *USBD_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *len
   * @param  length: Pointer to data length variable
   * @retval Pointer to descriptor buffer
   */
-STATIC uint8_t *USBD_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) {
-    USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length);
-    return USBD_StrDesc;
+STATIC uint8_t *USBD_ManufacturerStrDescriptor(USBD_HandleTypeDef *pdev, uint16_t *length) {
+    uint8_t *str_desc = ((usbd_cdc_msc_hid_state_t*)pdev->pClassData)->usbd_str_desc;
+    USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, str_desc, length);
+    return str_desc;
 }
 
 /**
@@ -159,7 +148,7 @@ STATIC uint8_t *USBD_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t
   * @param  length: Pointer to data length variable
   * @retval Pointer to descriptor buffer
   */
-STATIC uint8_t *USBD_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) {
+STATIC uint8_t *USBD_SerialStrDescriptor(USBD_HandleTypeDef *pdev, uint16_t *length) {
     // This document: http://www.usb.org/developers/docs/devclass_docs/usbmassbulk_10.pdf
     // says that the serial number has to be at least 12 digits long and that
     // the last 12 digits need to be unique. It also stipulates that the valid
@@ -179,8 +168,9 @@ STATIC uint8_t *USBD_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *leng
         "%02X%02X%02X%02X%02X%02X",
         id[11], id[10] + id[2], id[9], id[8] + id[0], id[7], id[6]);
 
-    USBD_GetString((uint8_t *)serial_buf, USBD_StrDesc, length);
-    return USBD_StrDesc;
+    uint8_t *str_desc = ((usbd_cdc_msc_hid_state_t*)pdev->pClassData)->usbd_str_desc;
+    USBD_GetString((uint8_t *)serial_buf, str_desc, length);
+    return str_desc;
 }
 
 /**
@@ -189,13 +179,14 @@ STATIC uint8_t *USBD_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *leng
   * @param  length: Pointer to data length variable
   * @retval Pointer to descriptor buffer
   */
-STATIC uint8_t *USBD_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) {
-    if(speed == USBD_SPEED_HIGH) {
-        USBD_GetString((uint8_t *)USBD_CONFIGURATION_HS_STRING, USBD_StrDesc, length);
+STATIC uint8_t *USBD_ConfigStrDescriptor(USBD_HandleTypeDef *pdev, uint16_t *length) {
+    uint8_t *str_desc = ((usbd_cdc_msc_hid_state_t*)pdev->pClassData)->usbd_str_desc;
+    if (pdev->dev_speed == USBD_SPEED_HIGH) {
+        USBD_GetString((uint8_t *)USBD_CONFIGURATION_HS_STRING, str_desc, length);
     } else {
-        USBD_GetString((uint8_t *)USBD_CONFIGURATION_FS_STRING, USBD_StrDesc, length);
+        USBD_GetString((uint8_t *)USBD_CONFIGURATION_FS_STRING, str_desc, length);
     }
-    return USBD_StrDesc;
+    return str_desc;
 }
 
 /**
@@ -204,13 +195,14 @@ STATIC uint8_t *USBD_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *leng
   * @param  length: Pointer to data length variable
   * @retval Pointer to descriptor buffer
   */
-STATIC uint8_t *USBD_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) {
-    if(speed == 0) {
-        USBD_GetString((uint8_t *)USBD_INTERFACE_HS_STRING, USBD_StrDesc, length);
+STATIC uint8_t *USBD_InterfaceStrDescriptor(USBD_HandleTypeDef *pdev, uint16_t *length) {
+    uint8_t *str_desc = ((usbd_cdc_msc_hid_state_t*)pdev->pClassData)->usbd_str_desc;
+    if (pdev->dev_speed == USBD_SPEED_HIGH) {
+        USBD_GetString((uint8_t *)USBD_INTERFACE_HS_STRING, str_desc, length);
     } else {
-        USBD_GetString((uint8_t *)USBD_INTERFACE_FS_STRING, USBD_StrDesc, length);
+        USBD_GetString((uint8_t *)USBD_INTERFACE_FS_STRING, str_desc, length);
     }
-    return USBD_StrDesc;
+    return str_desc;
 }
 
 const USBD_DescriptorsTypeDef USBD_Descriptors = {
diff --git a/stmhal/usbd_desc.h b/ports/stm32/usbd_desc.h
similarity index 89%
rename from stmhal/usbd_desc.h
rename to ports/stm32/usbd_desc.h
index 05cbbe5b17..a4de6c6819 100644
--- a/stmhal/usbd_desc.h
+++ b/ports/stm32/usbd_desc.h
@@ -26,8 +26,10 @@
 #ifndef MICROPY_INCLUDED_STMHAL_USBD_DESC_H
 #define MICROPY_INCLUDED_STMHAL_USBD_DESC_H
 
+#include "usbd_cdc_msc_hid.h"
+
 extern const USBD_DescriptorsTypeDef USBD_Descriptors;
 
-void USBD_SetVIDPIDRelease(uint16_t vid, uint16_t pid, uint16_t device_release_num, int cdc_only);
+void USBD_SetVIDPIDRelease(usbd_cdc_msc_hid_state_t *usbd, uint16_t vid, uint16_t pid, uint16_t device_release_num, int cdc_only);
 
 #endif // MICROPY_INCLUDED_STMHAL_USBD_DESC_H
diff --git a/stmhal/usbd_hid_interface.c b/ports/stm32/usbd_hid_interface.c
similarity index 52%
rename from stmhal/usbd_hid_interface.c
rename to ports/stm32/usbd_hid_interface.c
index 11b3a3acdc..4ee533c21c 100644
--- a/stmhal/usbd_hid_interface.c
+++ b/ports/stm32/usbd_hid_interface.c
@@ -36,75 +36,46 @@
 
 #include <stdint.h>
 
-#include "usbd_cdc_msc_hid.h"
 #include "usbd_hid_interface.h"
 
 #include "py/obj.h"
 #include "irq.h"
 #include "usb.h"
 
-/* Private variables ---------------------------------------------------------*/
+uint8_t *usbd_hid_init(usbd_hid_itf_t *hid, usbd_cdc_msc_hid_state_t *usbd) {
+    hid->usbd = usbd;
+    hid->current_read_buffer = 0;
+    hid->last_read_len = 0;
+    hid->current_write_buffer = 0;
 
-static uint8_t buffer[2][HID_DATA_FS_MAX_PACKET_SIZE]; // pair of buffers to read individual packets into
-static int8_t current_read_buffer = 0; // which buffer to read from
-static uint32_t last_read_len = 0; // length of last read
-static int8_t current_write_buffer = 0; // which buffer to write to
-
-/* Private function prototypes -----------------------------------------------*/
-static int8_t HID_Itf_Init     (USBD_HandleTypeDef *pdev);
-static int8_t HID_Itf_Receive  (USBD_HandleTypeDef *pdev, uint8_t* pbuf, uint32_t Len);
-
-const USBD_HID_ItfTypeDef USBD_HID_fops = {
-    HID_Itf_Init,
-    HID_Itf_Receive
-};
-
-/**
-  * @brief  HID_Itf_Init
-  *         Initializes the HID media low layer
-  * @param  None
-  * @retval Result of the opeartion: USBD_OK if all operations are OK else USBD_FAIL
-  */
-static int8_t HID_Itf_Init(USBD_HandleTypeDef *pdev)
-{
-    current_read_buffer = 0;
-    last_read_len = 0;
-    current_write_buffer = 0;
-    USBD_HID_SetRxBuffer(pdev, buffer[current_write_buffer]);
-    return USBD_OK;
+    // Return the buffer to place the first USB OUT packet
+    return hid->buffer[hid->current_write_buffer];
 }
 
-/**
-  * @brief  HID_Itf_Receive
-  *         Data received over USB OUT endpoint is processed here.
-  * @param  Buf: Buffer of data received
-  * @param  Len: Number of data received (in bytes)
-  * @retval Result of the opeartion: USBD_OK if all operations are OK else USBD_FAIL
-  * @note   The buffer we are passed here is just UserRxBuffer, so we are
-  *         free to modify it.
-  */
-static int8_t HID_Itf_Receive(USBD_HandleTypeDef *pdev, uint8_t* Buf, uint32_t Len) {
-    current_write_buffer = !current_write_buffer;
-    last_read_len = Len;
+// Data received over USB OUT endpoint is processed here.
+// len: number of bytes received into the buffer we passed to USBD_HID_ReceivePacket
+// Returns USBD_OK if all operations are OK else USBD_FAIL
+int8_t usbd_hid_receive(usbd_hid_itf_t *hid, size_t len) {
+    hid->current_write_buffer = !hid->current_write_buffer;
+    hid->last_read_len = len;
     // initiate next USB packet transfer, to append to existing data in buffer
-    USBD_HID_SetRxBuffer(pdev, buffer[current_write_buffer]);
-    USBD_HID_ReceivePacket(pdev);
+    USBD_HID_ReceivePacket(hid->usbd, hid->buffer[hid->current_write_buffer]);
     // Set NAK to indicate we need to process read buffer
-    USBD_HID_SetNAK(pdev);
+    USBD_HID_SetNAK(hid->usbd);
     return USBD_OK;
 }
 
 // Returns number of ready rx buffers.
-int USBD_HID_RxNum(void) {
-    return (current_read_buffer != current_write_buffer);
+int usbd_hid_rx_num(usbd_hid_itf_t *hid) {
+    return hid->current_read_buffer != hid->current_write_buffer;
 }
 
 // timout in milliseconds.
 // Returns number of bytes read from the device.
-int USBD_HID_Rx(USBD_HandleTypeDef *pdev, uint8_t *buf, uint32_t len, uint32_t timeout) {
+int usbd_hid_rx(usbd_hid_itf_t *hid, size_t len, uint8_t *buf, uint32_t timeout) {
     // Wait until we have buffer to read
     uint32_t start = HAL_GetTick();
-    while (current_read_buffer == current_write_buffer) {
+    while (hid->current_read_buffer == hid->current_write_buffer) {
         // Wraparound of tick is taken care of by 2's complement arithmetic.
         if (HAL_GetTick() - start >= timeout) {
             // timeout
@@ -118,17 +89,17 @@ int USBD_HID_Rx(USBD_HandleTypeDef *pdev, uint8_t *buf, uint32_t len, uint32_t t
     }
 
     // There is not enough space in buffer
-    if (len < last_read_len) {
+    if (len < hid->last_read_len) {
         return 0;
     }
 
     // Copy bytes from device to user buffer
-    memcpy(buf, buffer[current_read_buffer], last_read_len);
-    current_read_buffer = !current_read_buffer;
+    memcpy(buf, hid->buffer[hid->current_read_buffer], hid->last_read_len);
+    hid->current_read_buffer = !hid->current_read_buffer;
 
     // Clear NAK to indicate we are ready to read more data
-    USBD_HID_ClearNAK(pdev);
+    USBD_HID_ClearNAK(hid->usbd);
 
     // Success, return number of bytes read
-    return last_read_len;
+    return hid->last_read_len;
 }
diff --git a/ports/stm32/usbd_hid_interface.h b/ports/stm32/usbd_hid_interface.h
new file mode 100644
index 0000000000..79040b57e9
--- /dev/null
+++ b/ports/stm32/usbd_hid_interface.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ */
+#ifndef MICROPY_INCLUDED_STMHAL_USBD_HID_INTERFACE_H
+#define MICROPY_INCLUDED_STMHAL_USBD_HID_INTERFACE_H
+
+#include "usbd_cdc_msc_hid.h"
+
+typedef struct _usbd_hid_itf_t {
+    usbd_cdc_msc_hid_state_t *usbd; // the parent USB device
+
+    uint8_t buffer[2][HID_DATA_FS_MAX_PACKET_SIZE]; // pair of buffers to read individual packets into
+    int8_t current_read_buffer; // which buffer to read from
+    uint32_t last_read_len; // length of last read
+    int8_t current_write_buffer; // which buffer to write to
+} usbd_hid_itf_t;
+
+int usbd_hid_rx_num(usbd_hid_itf_t *hid);
+int usbd_hid_rx(usbd_hid_itf_t *hid, size_t len, uint8_t *buf, uint32_t timeout);
+
+#endif // MICROPY_INCLUDED_STMHAL_USBD_HID_INTERFACE_H
diff --git a/stmhal/usbd_msc_storage.c b/ports/stm32/usbd_msc_storage.c
similarity index 100%
rename from stmhal/usbd_msc_storage.c
rename to ports/stm32/usbd_msc_storage.c
diff --git a/stmhal/usbd_msc_storage.h b/ports/stm32/usbd_msc_storage.h
similarity index 100%
rename from stmhal/usbd_msc_storage.h
rename to ports/stm32/usbd_msc_storage.h
diff --git a/stmhal/usbdev/Release_Notes.html b/ports/stm32/usbdev/Release_Notes.html
similarity index 100%
rename from stmhal/usbdev/Release_Notes.html
rename to ports/stm32/usbdev/Release_Notes.html
diff --git a/stmhal/usbdev/class/inc/usbd_cdc_msc_hid.h b/ports/stm32/usbdev/class/inc/usbd_cdc_msc_hid.h
similarity index 51%
rename from stmhal/usbdev/class/inc/usbd_cdc_msc_hid.h
rename to ports/stm32/usbdev/class/inc/usbd_cdc_msc_hid.h
index 96617b1077..a26b1df0dc 100644
--- a/stmhal/usbdev/class/inc/usbd_cdc_msc_hid.h
+++ b/ports/stm32/usbdev/class/inc/usbd_cdc_msc_hid.h
@@ -6,6 +6,10 @@
 #include  "usbd_msc_scsi.h"
 #include  "usbd_ioreq.h"
 
+// Needed for the CDC+MSC+HID state and should be maximum of all template
+// config descriptors defined in usbd_cdc_msc_hid.c
+#define MAX_TEMPLATE_CONFIG_DESC_SIZE (107)
+
 // CDC, MSC and HID packet sizes
 #define CDC_DATA_FS_MAX_PACKET_SIZE (64) // endpoint IN & OUT packet size
 #define MSC_MEDIA_PACKET            (2048) // was 8192; how low can it go whilst still working?
@@ -27,31 +31,15 @@ typedef struct {
   uint8_t  datatype;
 } USBD_CDC_LineCodingTypeDef;
 
-typedef struct _USBD_CDC_Itf {
-  int8_t (* Init)          (USBD_HandleTypeDef *pdev);
-  int8_t (* DeInit)        (void);
-  int8_t (* Control)       (uint8_t, uint8_t * , uint16_t);   
-  int8_t (* Receive)       (USBD_HandleTypeDef *pdev, uint8_t *, uint32_t *);
-} USBD_CDC_ItfTypeDef;
-
 typedef struct {
   uint32_t data[CDC_DATA_FS_MAX_PACKET_SIZE/4];      /* Force 32bits alignment */
   uint8_t  CmdOpCode;
   uint8_t  CmdLength;    
-  uint8_t  *RxBuffer;  
-  uint8_t  *TxBuffer;   
-  uint32_t RxLength;
-  uint32_t TxLength;    
   
   __IO uint32_t TxState;     
   __IO uint32_t RxState;    
 } USBD_CDC_HandleTypeDef;
 
-typedef struct _USBD_HID_Itf {
-  int8_t (* Init)   (USBD_HandleTypeDef *pdev);
-  int8_t (* Receive)(USBD_HandleTypeDef *pdev, uint8_t *, uint32_t);
-} USBD_HID_ItfTypeDef;
-
 typedef struct _USBD_STORAGE {
   int8_t (* Init) (uint8_t lun);
   int8_t (* GetCapacity) (uint8_t lun, uint32_t *block_num, uint16_t *block_size);
@@ -84,8 +72,48 @@ typedef struct {
   
   uint32_t                 scsi_blk_addr_in_blks;
   uint32_t                 scsi_blk_len;
+
+  // operations of the underlying block device
+  USBD_StorageTypeDef *bdev_ops;
 } USBD_MSC_BOT_HandleTypeDef;
 
+typedef enum {
+    HID_IDLE = 0,
+    HID_BUSY,
+} HID_StateTypeDef;
+
+typedef struct {
+    uint32_t             Protocol;
+    uint32_t             IdleState;
+    uint32_t             AltSetting;
+    HID_StateTypeDef     state;
+} USBD_HID_HandleTypeDef;
+
+typedef struct _usbd_cdc_msc_hid_state_t {
+    USBD_HandleTypeDef *pdev;
+
+    uint8_t usbd_mode;
+    uint8_t cdc_iface_num;
+    uint8_t hid_in_ep;
+    uint8_t hid_out_ep;
+    uint8_t hid_iface_num;
+    uint8_t usbd_config_desc_size;
+    uint8_t *hid_desc;
+    const uint8_t *hid_report_desc;
+
+    USBD_CDC_HandleTypeDef CDC_ClassData;
+    USBD_MSC_BOT_HandleTypeDef MSC_BOT_ClassData;
+    USBD_HID_HandleTypeDef HID_ClassData;
+
+    // RAM to hold the current descriptors, which we configure on the fly
+    __ALIGN_BEGIN uint8_t usbd_device_desc[USB_LEN_DEV_DESC] __ALIGN_END;
+    __ALIGN_BEGIN uint8_t usbd_str_desc[USBD_MAX_STR_DESC_SIZ] __ALIGN_END;
+    __ALIGN_BEGIN uint8_t usbd_config_desc[MAX_TEMPLATE_CONFIG_DESC_SIZE] __ALIGN_END;
+
+    void *cdc;
+    void *hid;
+} usbd_cdc_msc_hid_state_t;
+
 #define USBD_HID_MOUSE_MAX_PACKET          (4)
 #define USBD_HID_MOUSE_REPORT_DESC_SIZE    (74)
 
@@ -96,27 +124,35 @@ extern const uint8_t USBD_HID_MOUSE_ReportDesc[USBD_HID_MOUSE_REPORT_DESC_SIZE];
 
 extern const uint8_t USBD_HID_KEYBOARD_ReportDesc[USBD_HID_KEYBOARD_REPORT_DESC_SIZE];
 
-extern USBD_ClassTypeDef USBD_CDC_MSC_HID;
+extern const USBD_ClassTypeDef USBD_CDC_MSC_HID;
 
 // returns 0 on success, -1 on failure
-int USBD_SelectMode(uint32_t mode, USBD_HID_ModeInfoTypeDef *hid_info);
+int USBD_SelectMode(usbd_cdc_msc_hid_state_t *usbd, uint32_t mode, USBD_HID_ModeInfoTypeDef *hid_info);
 // returns the current usb mode
-uint8_t USBD_GetMode();
+uint8_t USBD_GetMode(usbd_cdc_msc_hid_state_t *usbd);
 
-uint8_t USBD_CDC_RegisterInterface  (USBD_HandleTypeDef   *pdev, USBD_CDC_ItfTypeDef *fops);
-uint8_t USBD_CDC_SetTxBuffer  (USBD_HandleTypeDef   *pdev, uint8_t  *pbuff, uint16_t length);
-uint8_t USBD_CDC_SetRxBuffer        (USBD_HandleTypeDef   *pdev, uint8_t  *pbuff);
-uint8_t USBD_CDC_ReceivePacket  (USBD_HandleTypeDef *pdev);
-uint8_t USBD_CDC_TransmitPacket  (USBD_HandleTypeDef *pdev);
+uint8_t USBD_CDC_ReceivePacket(usbd_cdc_msc_hid_state_t *usbd, uint8_t *buf);
+uint8_t USBD_CDC_TransmitPacket(usbd_cdc_msc_hid_state_t *usbd, size_t len, const uint8_t *buf);
 
-uint8_t USBD_MSC_RegisterStorage(USBD_HandleTypeDef *pdev, USBD_StorageTypeDef *fops);
+static inline void USBD_MSC_RegisterStorage(usbd_cdc_msc_hid_state_t *usbd, USBD_StorageTypeDef *fops) {
+    usbd->MSC_BOT_ClassData.bdev_ops = fops;
+}
 
-uint8_t USBD_HID_RegisterInterface(USBD_HandleTypeDef *pdev, USBD_HID_ItfTypeDef *fops);
-uint8_t USBD_HID_SetRxBuffer(USBD_HandleTypeDef *pdev, uint8_t *pbuff);
-uint8_t USBD_HID_ReceivePacket(USBD_HandleTypeDef *pdev);
-int USBD_HID_CanSendReport(USBD_HandleTypeDef *pdev);
-uint8_t USBD_HID_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len);
-uint8_t USBD_HID_SetNAK(USBD_HandleTypeDef *pdev);
-uint8_t USBD_HID_ClearNAK(USBD_HandleTypeDef *pdev);
+uint8_t USBD_HID_ReceivePacket(usbd_cdc_msc_hid_state_t *usbd, uint8_t *buf);
+int USBD_HID_CanSendReport(usbd_cdc_msc_hid_state_t *usbd);
+uint8_t USBD_HID_SendReport(usbd_cdc_msc_hid_state_t *usbd, uint8_t *report, uint16_t len);
+uint8_t USBD_HID_SetNAK(usbd_cdc_msc_hid_state_t *usbd);
+uint8_t USBD_HID_ClearNAK(usbd_cdc_msc_hid_state_t *usbd);
+
+// These are provided externally to implement the CDC interface
+struct _usbd_cdc_itf_t;
+uint8_t *usbd_cdc_init(struct _usbd_cdc_itf_t *cdc, usbd_cdc_msc_hid_state_t *usbd);
+int8_t usbd_cdc_control(struct _usbd_cdc_itf_t *cdc, uint8_t cmd, uint8_t* pbuf, uint16_t length);
+int8_t usbd_cdc_receive(struct _usbd_cdc_itf_t *cdc, size_t len);
+
+// These are provided externally to implement the HID interface
+struct _usbd_hid_itf_t;
+uint8_t *usbd_hid_init(struct _usbd_hid_itf_t *hid, usbd_cdc_msc_hid_state_t *usbd);
+int8_t usbd_hid_receive(struct _usbd_hid_itf_t *hid, size_t len);
 
 #endif // _USB_CDC_MSC_CORE_H_
diff --git a/stmhal/usbdev/class/inc/usbd_cdc_msc_hid0.h b/ports/stm32/usbdev/class/inc/usbd_cdc_msc_hid0.h
similarity index 100%
rename from stmhal/usbdev/class/inc/usbd_cdc_msc_hid0.h
rename to ports/stm32/usbdev/class/inc/usbd_cdc_msc_hid0.h
diff --git a/stmhal/usbdev/class/inc/usbd_msc_bot.h b/ports/stm32/usbdev/class/inc/usbd_msc_bot.h
similarity index 100%
rename from stmhal/usbdev/class/inc/usbd_msc_bot.h
rename to ports/stm32/usbdev/class/inc/usbd_msc_bot.h
diff --git a/stmhal/usbdev/class/inc/usbd_msc_data.h b/ports/stm32/usbdev/class/inc/usbd_msc_data.h
similarity index 100%
rename from stmhal/usbdev/class/inc/usbd_msc_data.h
rename to ports/stm32/usbdev/class/inc/usbd_msc_data.h
diff --git a/stmhal/usbdev/class/inc/usbd_msc_scsi.h b/ports/stm32/usbdev/class/inc/usbd_msc_scsi.h
similarity index 100%
rename from stmhal/usbdev/class/inc/usbd_msc_scsi.h
rename to ports/stm32/usbdev/class/inc/usbd_msc_scsi.h
diff --git a/stmhal/usbdev/class/src/usbd_cdc_msc_hid.c b/ports/stm32/usbdev/class/src/usbd_cdc_msc_hid.c
similarity index 79%
rename from stmhal/usbdev/class/src/usbd_cdc_msc_hid.c
rename to ports/stm32/usbdev/class/src/usbd_cdc_msc_hid.c
index d61073f4d5..379a8f32ce 100644
--- a/stmhal/usbdev/class/src/usbd_cdc_msc_hid.c
+++ b/ports/stm32/usbdev/class/src/usbd_cdc_msc_hid.c
@@ -27,7 +27,6 @@
 #include "usbd_ioreq.h"
 #include "usbd_cdc_msc_hid.h"
 
-#define MAX_TEMPLATE_CONFIG_DESC_SIZE (107) // should be maximum of all template config desc's
 #define CDC_TEMPLATE_CONFIG_DESC_SIZE (67)
 #define CDC_MSC_TEMPLATE_CONFIG_DESC_SIZE (98)
 #define CDC_HID_TEMPLATE_CONFIG_DESC_SIZE (107)
@@ -72,40 +71,6 @@
 #define HID_REQ_SET_IDLE        (0x0a)
 #define HID_REQ_GET_IDLE        (0x02)
 
-typedef enum {
-    HID_IDLE = 0,
-    HID_BUSY,
-} HID_StateTypeDef;
-
-typedef struct {
-    uint32_t             Protocol;
-    uint32_t             IdleState;
-    uint32_t             AltSetting;
-    HID_StateTypeDef     state;
-    uint8_t              *RxBuffer;
-    uint32_t             RxLength;
-} USBD_HID_HandleTypeDef;
-
-static uint8_t usbd_mode;
-static uint8_t cdc_iface_num;
-static uint8_t hid_in_ep;
-static uint8_t hid_out_ep;
-static uint8_t hid_iface_num;
-static uint8_t usbd_config_desc_size;
-static uint8_t *hid_desc;
-static const uint8_t *hid_report_desc;
-
-static USBD_CDC_ItfTypeDef *CDC_fops;
-static USBD_StorageTypeDef *MSC_fops;
-static USBD_HID_ItfTypeDef *HID_fops;
-
-static USBD_CDC_HandleTypeDef CDC_ClassData;
-static USBD_MSC_BOT_HandleTypeDef MSC_BOT_ClassData;
-static USBD_HID_HandleTypeDef HID_ClassData;
-
-// RAM to hold the current configuration descriptor, which we configure on the fly
-__ALIGN_BEGIN static uint8_t usbd_config_desc[MAX_TEMPLATE_CONFIG_DESC_SIZE] __ALIGN_END;
-
 /*
 // this is used only in high-speed mode, which we don't support
 // USB Standard Device Descriptor
@@ -578,36 +543,36 @@ __ALIGN_BEGIN const uint8_t USBD_HID_KEYBOARD_ReportDesc[USBD_HID_KEYBOARD_REPOR
 };
 
 // return the saved usb mode
-uint8_t USBD_GetMode() {
-    return usbd_mode;
+uint8_t USBD_GetMode(usbd_cdc_msc_hid_state_t *usbd) {
+    return usbd->usbd_mode;
 }
 
-int USBD_SelectMode(uint32_t mode, USBD_HID_ModeInfoTypeDef *hid_info) {
+int USBD_SelectMode(usbd_cdc_msc_hid_state_t *usbd, uint32_t mode, USBD_HID_ModeInfoTypeDef *hid_info) {
     // save mode
-    usbd_mode = mode;
+    usbd->usbd_mode = mode;
 
     // construct config desc
-    switch (usbd_mode) {
+    switch (usbd->usbd_mode) {
         case USBD_MODE_CDC_MSC:
-            usbd_config_desc_size = sizeof(cdc_msc_template_config_desc);
-            memcpy(usbd_config_desc, cdc_msc_template_config_desc, sizeof(cdc_msc_template_config_desc));
-            cdc_iface_num = CDC_IFACE_NUM_WITH_MSC;
+            usbd->usbd_config_desc_size = sizeof(cdc_msc_template_config_desc);
+            memcpy(usbd->usbd_config_desc, cdc_msc_template_config_desc, sizeof(cdc_msc_template_config_desc));
+            usbd->cdc_iface_num = CDC_IFACE_NUM_WITH_MSC;
             break;
 
         case USBD_MODE_CDC_HID:
-            usbd_config_desc_size = sizeof(cdc_hid_template_config_desc);
-            memcpy(usbd_config_desc, cdc_hid_template_config_desc, sizeof(cdc_hid_template_config_desc));
-            cdc_iface_num = CDC_IFACE_NUM_WITH_HID;
-            hid_in_ep = HID_IN_EP_WITH_CDC;
-            hid_out_ep = HID_OUT_EP_WITH_CDC;
-            hid_iface_num = HID_IFACE_NUM_WITH_CDC;
-            hid_desc = usbd_config_desc + CDC_HID_TEMPLATE_HID_DESC_OFFSET;
+            usbd->usbd_config_desc_size = sizeof(cdc_hid_template_config_desc);
+            memcpy(usbd->usbd_config_desc, cdc_hid_template_config_desc, sizeof(cdc_hid_template_config_desc));
+            usbd->cdc_iface_num = CDC_IFACE_NUM_WITH_HID;
+            usbd->hid_in_ep = HID_IN_EP_WITH_CDC;
+            usbd->hid_out_ep = HID_OUT_EP_WITH_CDC;
+            usbd->hid_iface_num = HID_IFACE_NUM_WITH_CDC;
+            usbd->hid_desc = usbd->usbd_config_desc + CDC_HID_TEMPLATE_HID_DESC_OFFSET;
             break;
 
         case USBD_MODE_CDC:
-            usbd_config_desc_size = sizeof(cdc_template_config_desc);
-            memcpy(usbd_config_desc, cdc_template_config_desc, sizeof(cdc_template_config_desc));
-            cdc_iface_num = CDC_IFACE_NUM_ALONE;
+            usbd->usbd_config_desc_size = sizeof(cdc_template_config_desc);
+            memcpy(usbd->usbd_config_desc, cdc_template_config_desc, sizeof(cdc_template_config_desc));
+            usbd->cdc_iface_num = CDC_IFACE_NUM_ALONE;
             break;
 
             /*
@@ -625,7 +590,8 @@ int USBD_SelectMode(uint32_t mode, USBD_HID_ModeInfoTypeDef *hid_info) {
     }
 
     // configure the HID descriptor, if needed
-    if (usbd_mode & USBD_MODE_HID) {
+    if (usbd->usbd_mode & USBD_MODE_HID) {
+        uint8_t *hid_desc = usbd->hid_desc;
         hid_desc[HID_DESC_OFFSET_SUBCLASS] = hid_info->subclass;
         hid_desc[HID_DESC_OFFSET_PROTOCOL] = hid_info->protocol;
         hid_desc[HID_DESC_OFFSET_REPORT_DESC_LEN] = hid_info->report_desc_len;
@@ -635,7 +601,7 @@ int USBD_SelectMode(uint32_t mode, USBD_HID_ModeInfoTypeDef *hid_info) {
         hid_desc[HID_DESC_OFFSET_MAX_PACKET_OUT_LO] = hid_info->max_packet_len;
         hid_desc[HID_DESC_OFFSET_MAX_PACKET_OUT_HI] = 0;
         hid_desc[HID_DESC_OFFSET_POLLING_INTERVAL_OUT] = hid_info->polling_interval;
-        hid_report_desc = hid_info->report_desc;
+        usbd->hid_report_desc = hid_info->report_desc;
     }
 
     return 0;
@@ -647,7 +613,9 @@ static uint8_t USBD_CDC_MSC_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) {
         return 1;
     }
 
-    if (usbd_mode & USBD_MODE_CDC) {
+    usbd_cdc_msc_hid_state_t *usbd = pdev->pClassData;
+
+    if (usbd->usbd_mode & USBD_MODE_CDC) {
         // CDC VCP component
 
         // Open EP IN
@@ -669,17 +637,17 @@ static uint8_t USBD_CDC_MSC_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) {
                        CDC_CMD_PACKET_SIZE);
 
         // Init physical Interface components
-        CDC_fops->Init(pdev);
+        uint8_t *buf = usbd_cdc_init(usbd->cdc, usbd);
 
         // Init Xfer states
-        CDC_ClassData.TxState =0;
-        CDC_ClassData.RxState =0;
+        usbd->CDC_ClassData.TxState = 0;
+        usbd->CDC_ClassData.RxState = 0;
 
         // Prepare Out endpoint to receive next packet
-        USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, CDC_ClassData.RxBuffer, CDC_DATA_OUT_PACKET_SIZE);
+        USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, buf, CDC_DATA_OUT_PACKET_SIZE);
     }
 
-    if (usbd_mode & USBD_MODE_MSC) {
+    if (usbd->usbd_mode & USBD_MODE_MSC) {
         // MSC component
 
         // Open EP OUT
@@ -694,61 +662,57 @@ static uint8_t USBD_CDC_MSC_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) {
                        USBD_EP_TYPE_BULK,
                        MSC_MAX_PACKET);
 
-        // MSC uses the pClassData pointer because SCSI and BOT reference it
-        pdev->pClassData = &MSC_BOT_ClassData;
-
         // Init the BOT layer
         MSC_BOT_Init(pdev);
     }
 
-    if (usbd_mode & USBD_MODE_HID) {
+    if (usbd->usbd_mode & USBD_MODE_HID) {
         // HID component
 
         // get max packet lengths from descriptor
         uint16_t mps_in =
-            hid_desc[HID_DESC_OFFSET_MAX_PACKET_LO]
-            | (hid_desc[HID_DESC_OFFSET_MAX_PACKET_HI] << 8);
+            usbd->hid_desc[HID_DESC_OFFSET_MAX_PACKET_LO]
+            | (usbd->hid_desc[HID_DESC_OFFSET_MAX_PACKET_HI] << 8);
         uint16_t mps_out =
-            hid_desc[HID_DESC_OFFSET_MAX_PACKET_OUT_LO]
-            | (hid_desc[HID_DESC_OFFSET_MAX_PACKET_OUT_HI] << 8);
+            usbd->hid_desc[HID_DESC_OFFSET_MAX_PACKET_OUT_LO]
+            | (usbd->hid_desc[HID_DESC_OFFSET_MAX_PACKET_OUT_HI] << 8);
 
         // Open EP IN
         USBD_LL_OpenEP(pdev,
-                       hid_in_ep,
+                       usbd->hid_in_ep,
                        USBD_EP_TYPE_INTR,
                        mps_in);
 
         // Open EP OUT
         USBD_LL_OpenEP(pdev,
-                       hid_out_ep,
+                       usbd->hid_out_ep,
                        USBD_EP_TYPE_INTR,
                        mps_out);
 
-        HID_fops->Init(pdev);
+        uint8_t *buf = usbd_hid_init(usbd->hid, usbd);
 
         // Prepare Out endpoint to receive next packet
-        USBD_LL_PrepareReceive(pdev, hid_out_ep, HID_ClassData.RxBuffer, mps_out);
+        USBD_LL_PrepareReceive(pdev, usbd->hid_out_ep, buf, mps_out);
 
-        HID_ClassData.state = HID_IDLE;
+        usbd->HID_ClassData.state = HID_IDLE;
     }
 
     return 0;
 }
 
 static uint8_t USBD_CDC_MSC_HID_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx) {
-    if (usbd_mode & USBD_MODE_CDC) {
+    usbd_cdc_msc_hid_state_t *usbd = pdev->pClassData;
+
+    if ((usbd->usbd_mode & USBD_MODE_CDC) && usbd->cdc) {
         // CDC VCP component
 
         // close endpoints
         USBD_LL_CloseEP(pdev, CDC_IN_EP);
         USBD_LL_CloseEP(pdev, CDC_OUT_EP);
         USBD_LL_CloseEP(pdev, CDC_CMD_EP);
-
-        // DeInit physical Interface components
-        CDC_fops->DeInit();
     }
 
-    if (usbd_mode & USBD_MODE_MSC) {
+    if (usbd->usbd_mode & USBD_MODE_MSC) {
         // MSC component
 
         // close endpoints
@@ -757,17 +721,14 @@ static uint8_t USBD_CDC_MSC_HID_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
 
         // DeInit the BOT layer
         MSC_BOT_DeInit(pdev);
-
-        // clear the pointer
-        pdev->pClassData = NULL;
     }
 
-    if (usbd_mode & USBD_MODE_HID) {
+    if (usbd->usbd_mode & USBD_MODE_HID) {
         // HID component
 
         // close endpoints
-        USBD_LL_CloseEP(pdev, hid_in_ep);
-        USBD_LL_CloseEP(pdev, hid_out_ep);
+        USBD_LL_CloseEP(pdev, usbd->hid_in_ep);
+        USBD_LL_CloseEP(pdev, usbd->hid_out_ep);
     }
 
     return 0;
@@ -791,36 +752,38 @@ static uint8_t USBD_CDC_MSC_HID_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTyp
         SU: 21 20 0 1
     */
 
+    usbd_cdc_msc_hid_state_t *usbd = pdev->pClassData;
+
     switch (req->bmRequest & USB_REQ_TYPE_MASK) {
 
         // Class request
         case USB_REQ_TYPE_CLASS:
             // req->wIndex is the recipient interface number
-            if ((usbd_mode & USBD_MODE_CDC) && req->wIndex == cdc_iface_num) {
+            if ((usbd->usbd_mode & USBD_MODE_CDC) && req->wIndex == usbd->cdc_iface_num) {
                 // CDC component
                 if (req->wLength) {
                     if (req->bmRequest & 0x80) {
                         // device-to-host request
-                        CDC_fops->Control(req->bRequest, (uint8_t*)CDC_ClassData.data, req->wLength);
-                        USBD_CtlSendData(pdev, (uint8_t*)CDC_ClassData.data, req->wLength);
+                        usbd_cdc_control(usbd->cdc, req->bRequest, (uint8_t*)usbd->CDC_ClassData.data, req->wLength);
+                        USBD_CtlSendData(pdev, (uint8_t*)usbd->CDC_ClassData.data, req->wLength);
                     } else {
                         // host-to-device request
-                        CDC_ClassData.CmdOpCode = req->bRequest;
-                        CDC_ClassData.CmdLength = req->wLength;
-                        USBD_CtlPrepareRx(pdev, (uint8_t*)CDC_ClassData.data, req->wLength);
+                        usbd->CDC_ClassData.CmdOpCode = req->bRequest;
+                        usbd->CDC_ClassData.CmdLength = req->wLength;
+                        USBD_CtlPrepareRx(pdev, (uint8_t*)usbd->CDC_ClassData.data, req->wLength);
                     }
                 } else {
                     // Not a Data request
                     // Transfer the command to the interface layer
-                    return CDC_fops->Control(req->bRequest, NULL, req->wValue);
+                    return usbd_cdc_control(usbd->cdc, req->bRequest, NULL, req->wValue);
                 }
-            } else if ((usbd_mode & USBD_MODE_MSC) && req->wIndex == MSC_IFACE_NUM_WITH_CDC) {
+            } else if ((usbd->usbd_mode & USBD_MODE_MSC) && req->wIndex == MSC_IFACE_NUM_WITH_CDC) {
                 // MSC component
                 switch (req->bRequest) {
                     case BOT_GET_MAX_LUN:
                         if ((req->wValue  == 0) && (req->wLength == 1) && ((req->bmRequest & 0x80) == 0x80)) {
-                            MSC_BOT_ClassData.max_lun = MSC_fops->GetMaxLun();
-                            USBD_CtlSendData(pdev, (uint8_t *)&MSC_BOT_ClassData.max_lun, 1);
+                            usbd->MSC_BOT_ClassData.max_lun = usbd->MSC_BOT_ClassData.bdev_ops->GetMaxLun();
+                            USBD_CtlSendData(pdev, (uint8_t *)&usbd->MSC_BOT_ClassData.max_lun, 1);
                         } else {
                             USBD_CtlError(pdev, req);
                             return USBD_FAIL;
@@ -840,22 +803,22 @@ static uint8_t USBD_CDC_MSC_HID_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTyp
                         USBD_CtlError(pdev, req);
                         return USBD_FAIL;
                 }
-            } else if ((usbd_mode & USBD_MODE_HID) && req->wIndex == hid_iface_num) {
+            } else if ((usbd->usbd_mode & USBD_MODE_HID) && req->wIndex == usbd->hid_iface_num) {
                 switch (req->bRequest) {
                     case HID_REQ_SET_PROTOCOL:
-                        HID_ClassData.Protocol = (uint8_t)(req->wValue);
+                        usbd->HID_ClassData.Protocol = (uint8_t)(req->wValue);
                         break;
 
                     case HID_REQ_GET_PROTOCOL:
-                        USBD_CtlSendData (pdev, (uint8_t *)&HID_ClassData.Protocol, 1);
+                        USBD_CtlSendData(pdev, (uint8_t *)&usbd->HID_ClassData.Protocol, 1);
                         break;
 
                     case HID_REQ_SET_IDLE:
-                        HID_ClassData.IdleState = (uint8_t)(req->wValue >> 8);
+                        usbd->HID_ClassData.IdleState = (uint8_t)(req->wValue >> 8);
                         break;
 
                     case HID_REQ_GET_IDLE:
-                        USBD_CtlSendData (pdev, (uint8_t *)&HID_ClassData.IdleState, 1);
+                        USBD_CtlSendData(pdev, (uint8_t *)&usbd->HID_ClassData.IdleState, 1);
                         break;
 
                     default:
@@ -867,14 +830,14 @@ static uint8_t USBD_CDC_MSC_HID_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTyp
 
         // Interface & Endpoint request
         case USB_REQ_TYPE_STANDARD:
-            if ((usbd_mode & USBD_MODE_MSC) && req->wIndex == MSC_IFACE_NUM_WITH_CDC) {
+            if ((usbd->usbd_mode & USBD_MODE_MSC) && req->wIndex == MSC_IFACE_NUM_WITH_CDC) {
                 switch (req->bRequest) {
                     case USB_REQ_GET_INTERFACE :
-                        USBD_CtlSendData(pdev, (uint8_t *)&MSC_BOT_ClassData.interface, 1);
+                        USBD_CtlSendData(pdev, (uint8_t *)&usbd->MSC_BOT_ClassData.interface, 1);
                         break;
 
                     case USB_REQ_SET_INTERFACE :
-                        MSC_BOT_ClassData.interface = (uint8_t)(req->wValue);
+                        usbd->MSC_BOT_ClassData.interface = (uint8_t)(req->wValue);
                         break;
 
                     case USB_REQ_CLEAR_FEATURE:
@@ -894,29 +857,29 @@ static uint8_t USBD_CDC_MSC_HID_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTyp
                         MSC_BOT_CplClrFeature(pdev, (uint8_t)req->wIndex);
                         break;
                 }
-            } else if ((usbd_mode & USBD_MODE_HID) && req->wIndex == hid_iface_num) {
+            } else if ((usbd->usbd_mode & USBD_MODE_HID) && req->wIndex == usbd->hid_iface_num) {
                 switch (req->bRequest) {
                     case USB_REQ_GET_DESCRIPTOR: {
                         uint16_t len = 0;
                         const uint8_t *pbuf = NULL;
                         if (req->wValue >> 8 == HID_REPORT_DESC) {
-                            len = hid_desc[HID_DESC_OFFSET_REPORT_DESC_LEN];
+                            len = usbd->hid_desc[HID_DESC_OFFSET_REPORT_DESC_LEN];
                             len = MIN(len, req->wLength);
-                            pbuf = hid_report_desc;
+                            pbuf = usbd->hid_report_desc;
                         } else if (req->wValue >> 8 == HID_DESCRIPTOR_TYPE) {
                             len = MIN(HID_SUBDESC_LEN, req->wLength);
-                            pbuf = hid_desc + HID_DESC_OFFSET_SUBDESC;
+                            pbuf = usbd->hid_desc + HID_DESC_OFFSET_SUBDESC;
                         }
                         USBD_CtlSendData(pdev, (uint8_t*)pbuf, len);
                         break;
                     }
 
                     case USB_REQ_GET_INTERFACE:
-                        USBD_CtlSendData (pdev, (uint8_t *)&HID_ClassData.AltSetting, 1);
+                        USBD_CtlSendData(pdev, (uint8_t *)&usbd->HID_ClassData.AltSetting, 1);
                         break;
 
                     case USB_REQ_SET_INTERFACE:
-                        HID_ClassData.AltSetting = (uint8_t)(req->wValue);
+                        usbd->HID_ClassData.AltSetting = (uint8_t)(req->wValue);
                         break;
                 }
             }
@@ -931,25 +894,27 @@ static uint8_t EP0_TxSent(USBD_HandleTypeDef *pdev) {
 */
 
 static uint8_t USBD_CDC_MSC_HID_EP0_RxReady(USBD_HandleTypeDef *pdev) {
-    if ((CDC_fops != NULL) && (CDC_ClassData.CmdOpCode != 0xff)) {
-        CDC_fops->Control(CDC_ClassData.CmdOpCode, (uint8_t*)CDC_ClassData.data, CDC_ClassData.CmdLength);
-        CDC_ClassData.CmdOpCode = 0xff;
+    usbd_cdc_msc_hid_state_t *usbd = pdev->pClassData;
+    if (usbd->cdc != NULL && usbd->CDC_ClassData.CmdOpCode != 0xff) {
+        usbd_cdc_control(usbd->cdc, usbd->CDC_ClassData.CmdOpCode, (uint8_t*)usbd->CDC_ClassData.data, usbd->CDC_ClassData.CmdLength);
+        usbd->CDC_ClassData.CmdOpCode = 0xff;
     }
 
     return USBD_OK;
 }
 
 static uint8_t USBD_CDC_MSC_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum) {
-    if ((usbd_mode & USBD_MODE_CDC) && (epnum == (CDC_IN_EP & 0x7f) || epnum == (CDC_CMD_EP & 0x7f))) {
-        CDC_ClassData.TxState = 0;
+    usbd_cdc_msc_hid_state_t *usbd = pdev->pClassData;
+    if ((usbd->usbd_mode & USBD_MODE_CDC) && (epnum == (CDC_IN_EP & 0x7f) || epnum == (CDC_CMD_EP & 0x7f))) {
+        usbd->CDC_ClassData.TxState = 0;
         return USBD_OK;
-    } else if ((usbd_mode & USBD_MODE_MSC) && epnum == (MSC_IN_EP & 0x7f)) {
+    } else if ((usbd->usbd_mode & USBD_MODE_MSC) && epnum == (MSC_IN_EP & 0x7f)) {
         MSC_BOT_DataIn(pdev, epnum);
         return USBD_OK;
-    } else if ((usbd_mode & USBD_MODE_HID) && epnum == (hid_in_ep & 0x7f)) {
+    } else if ((usbd->usbd_mode & USBD_MODE_HID) && epnum == (usbd->hid_in_ep & 0x7f)) {
         /* Ensure that the FIFO is empty before a new transfer, this condition could
         be caused by  a new transfer before the end of the previous transfer */
-        HID_ClassData.state = HID_IDLE;
+        usbd->HID_ClassData.state = HID_IDLE;
         return USBD_OK;
     }
 
@@ -957,33 +922,35 @@ static uint8_t USBD_CDC_MSC_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum)
 }
 
 static uint8_t USBD_CDC_MSC_HID_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum) {
-    if ((usbd_mode & USBD_MODE_CDC) && epnum == (CDC_OUT_EP & 0x7f)) {
+    usbd_cdc_msc_hid_state_t *usbd = pdev->pClassData;
+    if ((usbd->usbd_mode & USBD_MODE_CDC) && epnum == (CDC_OUT_EP & 0x7f)) {
         /* Get the received data length */
-        CDC_ClassData.RxLength = USBD_LL_GetRxDataSize (pdev, epnum);
+        size_t len = USBD_LL_GetRxDataSize (pdev, epnum);
 
         /* USB data will be immediately processed, this allow next USB traffic being
         NAKed till the end of the application Xfer */
-        CDC_fops->Receive(pdev, CDC_ClassData.RxBuffer, &CDC_ClassData.RxLength);
+        usbd_cdc_receive(usbd->cdc, len);
 
         return USBD_OK;
-    } else if ((usbd_mode & USBD_MODE_MSC) && epnum == (MSC_OUT_EP & 0x7f)) {
+    } else if ((usbd->usbd_mode & USBD_MODE_MSC) && epnum == (MSC_OUT_EP & 0x7f)) {
         MSC_BOT_DataOut(pdev, epnum);
         return USBD_OK;
-    } else if ((usbd_mode & USBD_MODE_HID) && epnum == (hid_out_ep & 0x7f)) {
-        HID_ClassData.RxLength = USBD_LL_GetRxDataSize(pdev, epnum);
-        HID_fops->Receive(pdev, HID_ClassData.RxBuffer, HID_ClassData.RxLength);
+    } else if ((usbd->usbd_mode & USBD_MODE_HID) && epnum == (usbd->hid_out_ep & 0x7f)) {
+        size_t len = USBD_LL_GetRxDataSize(pdev, epnum);
+        usbd_hid_receive(usbd->hid, len);
     }
 
     return USBD_OK;
 }
 
-static uint8_t *USBD_CDC_MSC_HID_GetCfgDesc(uint16_t *length) {
-    *length = usbd_config_desc_size;
-    return usbd_config_desc;
+static uint8_t *USBD_CDC_MSC_HID_GetCfgDesc(USBD_HandleTypeDef *pdev, uint16_t *length) {
+    usbd_cdc_msc_hid_state_t *usbd = pdev->pClassData;
+    *length = usbd->usbd_config_desc_size;
+    return usbd->usbd_config_desc;
 }
 
 // this is used only in high-speed mode, which we don't support
-uint8_t *USBD_CDC_MSC_HID_GetDeviceQualifierDescriptor (uint16_t *length) {
+uint8_t *USBD_CDC_MSC_HID_GetDeviceQualifierDescriptor(USBD_HandleTypeDef *pdev, uint16_t *length) {
     /*
     *length = sizeof(USBD_CDC_MSC_HID_DeviceQualifierDesc);
     return USBD_CDC_MSC_HID_DeviceQualifierDesc;
@@ -992,34 +959,14 @@ uint8_t *USBD_CDC_MSC_HID_GetDeviceQualifierDescriptor (uint16_t *length) {
     return NULL;
 }
 
-uint8_t USBD_CDC_RegisterInterface(USBD_HandleTypeDef *pdev, USBD_CDC_ItfTypeDef *fops) {
-    if (fops == NULL) {
-        return USBD_FAIL;
-    } else {
-        CDC_fops = fops;
-        return USBD_OK;
-    }
-}
-
-uint8_t USBD_CDC_SetTxBuffer(USBD_HandleTypeDef *pdev, uint8_t *pbuff, uint16_t length) {
-    CDC_ClassData.TxBuffer = pbuff;
-    CDC_ClassData.TxLength = length;
-    return USBD_OK;
-}
-
-uint8_t USBD_CDC_SetRxBuffer(USBD_HandleTypeDef *pdev, uint8_t *pbuff) {
-    CDC_ClassData.RxBuffer = pbuff;
-    return USBD_OK;
-}
-
 // data received on non-control OUT endpoint
-uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev) {
-    if (CDC_ClassData.TxState == 0) {
+uint8_t USBD_CDC_TransmitPacket(usbd_cdc_msc_hid_state_t *usbd, size_t len, const uint8_t *buf) {
+    if (usbd->CDC_ClassData.TxState == 0) {
         // transmit next packet
-        USBD_LL_Transmit(pdev, CDC_IN_EP, CDC_ClassData.TxBuffer, CDC_ClassData.TxLength);
+        USBD_LL_Transmit(usbd->pdev, CDC_IN_EP, (uint8_t*)buf, len);
 
         // Tx transfer in progress
-        CDC_ClassData.TxState = 1;
+        usbd->CDC_ClassData.TxState = 1;
         return USBD_OK;
     } else {
         return USBD_BUSY;
@@ -1027,84 +974,60 @@ uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev) {
 }
 
 // prepare OUT endpoint for reception
-uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev) {
+uint8_t USBD_CDC_ReceivePacket(usbd_cdc_msc_hid_state_t *usbd, uint8_t *buf) {
     // Suspend or Resume USB Out process
-    if (pdev->dev_speed == USBD_SPEED_HIGH) {
+    if (usbd->pdev->dev_speed == USBD_SPEED_HIGH) {
         return USBD_FAIL;
     }
 
     // Prepare Out endpoint to receive next packet
-    USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, CDC_ClassData.RxBuffer, CDC_DATA_OUT_PACKET_SIZE);
+    USBD_LL_PrepareReceive(usbd->pdev, CDC_OUT_EP, buf, CDC_DATA_OUT_PACKET_SIZE);
 
     return USBD_OK;
 }
 
-uint8_t USBD_MSC_RegisterStorage(USBD_HandleTypeDef *pdev, USBD_StorageTypeDef *fops) {
-    if (fops == NULL) {
-        return USBD_FAIL;
-    } else {
-        MSC_fops = fops;
-        pdev->pUserData = fops; // MSC uses pUserData because SCSI and BOT reference it
-        return USBD_OK;
-    }
-}
-
-uint8_t USBD_HID_RegisterInterface(USBD_HandleTypeDef *pdev, USBD_HID_ItfTypeDef *fops) {
-    if (fops == NULL) {
-        return USBD_FAIL;
-    } else {
-        HID_fops = fops;
-        return USBD_OK;
-    }
-}
-
-uint8_t USBD_HID_SetRxBuffer(USBD_HandleTypeDef *pdev, uint8_t *pbuff) {
-    HID_ClassData.RxBuffer = pbuff;
-    return USBD_OK;
-}
-
 // prepare OUT endpoint for reception
-uint8_t USBD_HID_ReceivePacket(USBD_HandleTypeDef *pdev) {
+uint8_t USBD_HID_ReceivePacket(usbd_cdc_msc_hid_state_t *usbd, uint8_t *buf) {
     // Suspend or Resume USB Out process
-    if (pdev->dev_speed == USBD_SPEED_HIGH) {
+    if (usbd->pdev->dev_speed == USBD_SPEED_HIGH) {
         return USBD_FAIL;
     }
 
     // Prepare Out endpoint to receive next packet
     uint16_t mps_out =
-        hid_desc[HID_DESC_OFFSET_MAX_PACKET_OUT_LO]
-        | (hid_desc[HID_DESC_OFFSET_MAX_PACKET_OUT_HI] << 8);
-    USBD_LL_PrepareReceive(pdev, hid_out_ep, HID_ClassData.RxBuffer, mps_out);
+        usbd->hid_desc[HID_DESC_OFFSET_MAX_PACKET_OUT_LO]
+        | (usbd->hid_desc[HID_DESC_OFFSET_MAX_PACKET_OUT_HI] << 8);
+    USBD_LL_PrepareReceive(usbd->pdev, usbd->hid_out_ep, buf, mps_out);
 
     return USBD_OK;
 }
 
-int USBD_HID_CanSendReport(USBD_HandleTypeDef *pdev) {
-    return pdev->dev_state == USBD_STATE_CONFIGURED && HID_ClassData.state == HID_IDLE;
+int USBD_HID_CanSendReport(usbd_cdc_msc_hid_state_t *usbd) {
+    return usbd->pdev->dev_state == USBD_STATE_CONFIGURED && usbd->HID_ClassData.state == HID_IDLE;
 }
 
-uint8_t USBD_HID_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len) {
-    if (pdev->dev_state == USBD_STATE_CONFIGURED) {
-        if (HID_ClassData.state == HID_IDLE) {
-            HID_ClassData.state = HID_BUSY;
-            USBD_LL_Transmit(pdev, hid_in_ep, report, len);
+uint8_t USBD_HID_SendReport(usbd_cdc_msc_hid_state_t *usbd, uint8_t *report, uint16_t len) {
+    if (usbd->pdev->dev_state == USBD_STATE_CONFIGURED) {
+        if (usbd->HID_ClassData.state == HID_IDLE) {
+            usbd->HID_ClassData.state = HID_BUSY;
+            USBD_LL_Transmit(usbd->pdev, usbd->hid_in_ep, report, len);
         }
     }
     return USBD_OK;
 }
 
-uint8_t USBD_HID_SetNAK(USBD_HandleTypeDef *pdev) {
+uint8_t USBD_HID_SetNAK(usbd_cdc_msc_hid_state_t *usbd) {
     // get USBx object from pdev (needed for USBx_OUTEP macro below)
-    PCD_HandleTypeDef *hpcd = pdev->pData;
+    PCD_HandleTypeDef *hpcd = usbd->pdev->pData;
     USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
     // set NAK on HID OUT endpoint
     USBx_OUTEP(HID_OUT_EP_WITH_CDC)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
     return USBD_OK;
 }
 
-uint8_t USBD_HID_ClearNAK(USBD_HandleTypeDef *pdev) {
+uint8_t USBD_HID_ClearNAK(usbd_cdc_msc_hid_state_t *usbd) {
     // get USBx object from pdev (needed for USBx_OUTEP macro below)
-    PCD_HandleTypeDef *hpcd = pdev->pData;
+    PCD_HandleTypeDef *hpcd = usbd->pdev->pData;
     USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
     // clear NAK on HID OUT endpoint
     USBx_OUTEP(HID_OUT_EP_WITH_CDC)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK;
@@ -1112,7 +1035,7 @@ uint8_t USBD_HID_ClearNAK(USBD_HandleTypeDef *pdev) {
 }
 
 // CDC/MSC/HID interface class callback structure
-USBD_ClassTypeDef USBD_CDC_MSC_HID = {
+const USBD_ClassTypeDef USBD_CDC_MSC_HID = {
     USBD_CDC_MSC_HID_Init,
     USBD_CDC_MSC_HID_DeInit,
     USBD_CDC_MSC_HID_Setup,
diff --git a/stmhal/usbdev/class/src/usbd_msc_bot.c b/ports/stm32/usbdev/class/src/usbd_msc_bot.c
similarity index 85%
rename from stmhal/usbdev/class/src/usbd_msc_bot.c
rename to ports/stm32/usbdev/class/src/usbd_msc_bot.c
index 3c06f3cf68..2fccd9e082 100644
--- a/stmhal/usbdev/class/src/usbd_msc_bot.c
+++ b/ports/stm32/usbdev/class/src/usbd_msc_bot.c
@@ -104,7 +104,7 @@ static void MSC_BOT_Abort(USBD_HandleTypeDef  *pdev);
 */
 void MSC_BOT_Init (USBD_HandleTypeDef  *pdev)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = pdev->pClassData;
+  USBD_MSC_BOT_HandleTypeDef *hmsc = &((usbd_cdc_msc_hid_state_t*)pdev->pClassData)->MSC_BOT_ClassData;
     
   hmsc->bot_state  = USBD_BOT_IDLE;
   hmsc->bot_status = USBD_BOT_STATUS_NORMAL;
@@ -112,7 +112,7 @@ void MSC_BOT_Init (USBD_HandleTypeDef  *pdev)
   hmsc->scsi_sense_tail = 0;
   hmsc->scsi_sense_head = 0;
   
-  ((USBD_StorageTypeDef *)pdev->pUserData)->Init(0);
+  hmsc->bdev_ops->Init(0);
   
   USBD_LL_FlushEP(pdev, MSC_OUT_EP);
   USBD_LL_FlushEP(pdev, MSC_IN_EP);
@@ -132,7 +132,7 @@ void MSC_BOT_Init (USBD_HandleTypeDef  *pdev)
 */
 void MSC_BOT_Reset (USBD_HandleTypeDef  *pdev)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = pdev->pClassData;
+  USBD_MSC_BOT_HandleTypeDef *hmsc = &((usbd_cdc_msc_hid_state_t*)pdev->pClassData)->MSC_BOT_ClassData;
     
   hmsc->bot_state  = USBD_BOT_IDLE;
   hmsc->bot_status = USBD_BOT_STATUS_RECOVERY;  
@@ -152,7 +152,7 @@ void MSC_BOT_Reset (USBD_HandleTypeDef  *pdev)
 */
 void MSC_BOT_DeInit (USBD_HandleTypeDef  *pdev)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = pdev->pClassData;  
+  USBD_MSC_BOT_HandleTypeDef *hmsc = &((usbd_cdc_msc_hid_state_t*)pdev->pClassData)->MSC_BOT_ClassData;
   hmsc->bot_state  = USBD_BOT_IDLE;
 }
 
@@ -166,7 +166,7 @@ void MSC_BOT_DeInit (USBD_HandleTypeDef  *pdev)
 void MSC_BOT_DataIn (USBD_HandleTypeDef  *pdev, 
                      uint8_t epnum)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = pdev->pClassData;  
+  USBD_MSC_BOT_HandleTypeDef *hmsc = &((usbd_cdc_msc_hid_state_t*)pdev->pClassData)->MSC_BOT_ClassData;
   
   switch (hmsc->bot_state)
   {
@@ -199,7 +199,7 @@ void MSC_BOT_DataIn (USBD_HandleTypeDef  *pdev,
 void MSC_BOT_DataOut (USBD_HandleTypeDef  *pdev, 
                       uint8_t epnum)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = pdev->pClassData;
+  USBD_MSC_BOT_HandleTypeDef *hmsc = &((usbd_cdc_msc_hid_state_t*)pdev->pClassData)->MSC_BOT_ClassData;
   
   switch (hmsc->bot_state)
   {
@@ -231,7 +231,7 @@ void MSC_BOT_DataOut (USBD_HandleTypeDef  *pdev,
 */
 static void  MSC_BOT_CBW_Decode (USBD_HandleTypeDef  *pdev)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = pdev->pClassData;  
+  USBD_MSC_BOT_HandleTypeDef *hmsc = &((usbd_cdc_msc_hid_state_t*)pdev->pClassData)->MSC_BOT_ClassData;
   
   hmsc->csw.dTag = hmsc->cbw.dTag;
   hmsc->csw.dDataResidue = hmsc->cbw.dDataLength;
@@ -300,7 +300,7 @@ static void  MSC_BOT_SendData(USBD_HandleTypeDef  *pdev,
                               uint8_t* buf, 
                               uint16_t len)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = pdev->pClassData; 
+  USBD_MSC_BOT_HandleTypeDef *hmsc = &((usbd_cdc_msc_hid_state_t*)pdev->pClassData)->MSC_BOT_ClassData;
   
   len = MIN (hmsc->cbw.dDataLength, len);
   hmsc->csw.dDataResidue -= len;
@@ -320,7 +320,7 @@ static void  MSC_BOT_SendData(USBD_HandleTypeDef  *pdev,
 void  MSC_BOT_SendCSW (USBD_HandleTypeDef  *pdev,
                               uint8_t CSW_Status)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = pdev->pClassData; 
+  USBD_MSC_BOT_HandleTypeDef *hmsc = &((usbd_cdc_msc_hid_state_t*)pdev->pClassData)->MSC_BOT_ClassData;
   
   hmsc->csw.dSignature = USBD_BOT_CSW_SIGNATURE;
   hmsc->csw.bStatus = CSW_Status;
@@ -348,7 +348,7 @@ void  MSC_BOT_SendCSW (USBD_HandleTypeDef  *pdev,
 
 static void  MSC_BOT_Abort (USBD_HandleTypeDef  *pdev)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = pdev->pClassData; 
+  USBD_MSC_BOT_HandleTypeDef *hmsc = &((usbd_cdc_msc_hid_state_t*)pdev->pClassData)->MSC_BOT_ClassData;
   
   if ((hmsc->cbw.bmFlags == 0) && 
       (hmsc->cbw.dDataLength != 0) &&
@@ -377,7 +377,7 @@ static void  MSC_BOT_Abort (USBD_HandleTypeDef  *pdev)
 
 void  MSC_BOT_CplClrFeature (USBD_HandleTypeDef  *pdev, uint8_t epnum)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = pdev->pClassData; 
+  USBD_MSC_BOT_HandleTypeDef *hmsc = &((usbd_cdc_msc_hid_state_t*)pdev->pClassData)->MSC_BOT_ClassData;
   
   if(hmsc->bot_status == USBD_BOT_STATUS_ERROR )/* Bad CBW Signature */
   {
diff --git a/stmhal/usbdev/class/src/usbd_msc_data.c b/ports/stm32/usbdev/class/src/usbd_msc_data.c
similarity index 100%
rename from stmhal/usbdev/class/src/usbd_msc_data.c
rename to ports/stm32/usbdev/class/src/usbd_msc_data.c
diff --git a/stmhal/usbdev/class/src/usbd_msc_scsi.c b/ports/stm32/usbdev/class/src/usbd_msc_scsi.c
similarity index 85%
rename from stmhal/usbdev/class/src/usbd_msc_scsi.c
rename to ports/stm32/usbdev/class/src/usbd_msc_scsi.c
index b2931b7452..50cd5b9715 100644
--- a/stmhal/usbdev/class/src/usbd_msc_scsi.c
+++ b/ports/stm32/usbdev/class/src/usbd_msc_scsi.c
@@ -190,7 +190,7 @@ int8_t SCSI_ProcessCmd(USBD_HandleTypeDef  *pdev,
 */
 static int8_t SCSI_TestUnitReady(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = pdev->pClassData;  
+  USBD_MSC_BOT_HandleTypeDef *hmsc = &((usbd_cdc_msc_hid_state_t*)pdev->pClassData)->MSC_BOT_ClassData;
     
   /* case 9 : Hi > D0 */
   if (hmsc->cbw.dDataLength != 0)
@@ -202,7 +202,7 @@ static int8_t SCSI_TestUnitReady(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t
     return -1;
   }  
   
-  if(((USBD_StorageTypeDef *)pdev->pUserData)->IsReady(lun) !=0 )
+  if(hmsc->bdev_ops->IsReady(lun) !=0 )
   {
     SCSI_SenseCode(pdev,
                    lun,
@@ -227,7 +227,7 @@ static int8_t  SCSI_Inquiry(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *par
 {
   uint8_t* pPage;
   uint16_t len;
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = pdev->pClassData; 
+  USBD_MSC_BOT_HandleTypeDef *hmsc = &((usbd_cdc_msc_hid_state_t*)pdev->pClassData)->MSC_BOT_ClassData;
   
   if (params[1] & 0x01)/*Evpd is set*/
   {
@@ -237,7 +237,7 @@ static int8_t  SCSI_Inquiry(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *par
   else
   {
     
-    pPage = (uint8_t *)&((USBD_StorageTypeDef *)pdev->pUserData)->pInquiry[lun * STANDARD_INQUIRY_DATA_LEN];
+    pPage = (uint8_t *)&hmsc->bdev_ops->pInquiry[lun * STANDARD_INQUIRY_DATA_LEN];
     len = pPage[4] + 5;
     
     if (params[4] <= len)
@@ -264,9 +264,9 @@ static int8_t  SCSI_Inquiry(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *par
 */
 static int8_t SCSI_ReadCapacity10(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = pdev->pClassData; 
+  USBD_MSC_BOT_HandleTypeDef *hmsc = &((usbd_cdc_msc_hid_state_t*)pdev->pClassData)->MSC_BOT_ClassData;
   
-  if(((USBD_StorageTypeDef *)pdev->pUserData)->GetCapacity(lun, &hmsc->scsi_blk_nbr, &hmsc->scsi_blk_size) != 0)
+  if(hmsc->bdev_ops->GetCapacity(lun, &hmsc->scsi_blk_nbr, &hmsc->scsi_blk_size) != 0)
   {
     SCSI_SenseCode(pdev,
                    lun,
@@ -300,7 +300,7 @@ static int8_t SCSI_ReadCapacity10(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_
 */
 static int8_t SCSI_ReadFormatCapacity(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = pdev->pClassData; 
+  USBD_MSC_BOT_HandleTypeDef *hmsc = &((usbd_cdc_msc_hid_state_t*)pdev->pClassData)->MSC_BOT_ClassData;
   
   uint16_t blk_size;
   uint32_t blk_nbr;
@@ -311,7 +311,7 @@ static int8_t SCSI_ReadFormatCapacity(USBD_HandleTypeDef  *pdev, uint8_t lun, ui
     hmsc->bot_data[i] = 0;
   }
   
-  if(((USBD_StorageTypeDef *)pdev->pUserData)->GetCapacity(lun, &blk_nbr, &blk_size) != 0)
+  if(hmsc->bdev_ops->GetCapacity(lun, &blk_nbr, &blk_size) != 0)
   {
     SCSI_SenseCode(pdev,
                    lun,
@@ -345,7 +345,7 @@ static int8_t SCSI_ReadFormatCapacity(USBD_HandleTypeDef  *pdev, uint8_t lun, ui
 */
 static int8_t SCSI_ModeSense6 (USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = pdev->pClassData; 
+  USBD_MSC_BOT_HandleTypeDef *hmsc = &((usbd_cdc_msc_hid_state_t*)pdev->pClassData)->MSC_BOT_ClassData;
   uint16_t len = 8 ;
   hmsc->bot_data_length = len;
   
@@ -367,7 +367,7 @@ static int8_t SCSI_ModeSense6 (USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *
 static int8_t SCSI_ModeSense10 (USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params)
 {
   uint16_t len = 8;
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = pdev->pClassData; 
+  USBD_MSC_BOT_HandleTypeDef *hmsc = &((usbd_cdc_msc_hid_state_t*)pdev->pClassData)->MSC_BOT_ClassData;
   
   hmsc->bot_data_length = len;
 
@@ -381,7 +381,7 @@ static int8_t SCSI_ModeSense10 (USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t
 
 static int8_t SCSI_SynchronizeCache(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params) {
     // nothing to synchronize, so just return "success"
-    USBD_MSC_BOT_HandleTypeDef *hmsc = pdev->pClassData;
+  USBD_MSC_BOT_HandleTypeDef *hmsc = &((usbd_cdc_msc_hid_state_t*)pdev->pClassData)->MSC_BOT_ClassData;
     hmsc->bot_data_length = 0;
     return 0;
 }
@@ -397,7 +397,7 @@ static int8_t SCSI_SynchronizeCache(USBD_HandleTypeDef  *pdev, uint8_t lun, uint
 static int8_t SCSI_RequestSense (USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params)
 {
   uint8_t i;
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = pdev->pClassData; 
+  USBD_MSC_BOT_HandleTypeDef *hmsc = &((usbd_cdc_msc_hid_state_t*)pdev->pClassData)->MSC_BOT_ClassData;
   
   for(i=0 ; i < REQUEST_SENSE_DATA_LEN ; i++) 
   {
@@ -439,7 +439,7 @@ static int8_t SCSI_RequestSense (USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t
 */
 void SCSI_SenseCode(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t sKey, uint8_t ASC)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = pdev->pClassData; 
+  USBD_MSC_BOT_HandleTypeDef *hmsc = &((usbd_cdc_msc_hid_state_t*)pdev->pClassData)->MSC_BOT_ClassData;
   
   hmsc->scsi_sense[hmsc->scsi_sense_tail].Skey  = sKey;
   hmsc->scsi_sense[hmsc->scsi_sense_tail].w.ASC = ASC << 8;
@@ -458,14 +458,14 @@ void SCSI_SenseCode(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t sKey, uint8_
 */
 static int8_t SCSI_StartStopUnit(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = pdev->pClassData;   
+  USBD_MSC_BOT_HandleTypeDef *hmsc = &((usbd_cdc_msc_hid_state_t*)pdev->pClassData)->MSC_BOT_ClassData;
   hmsc->bot_data_length = 0;
 
   // On Mac OS X, when the device is ejected a SCSI_START_STOP_UNIT command is sent.
   // Bit 0 of params[4] is the START bit.
   // If we get a stop, we must really stop the device so that the Mac does not
   // automatically remount it.
-  ((USBD_StorageTypeDef *)pdev->pUserData)->StartStopUnit(lun, params[4] & 1);
+  hmsc->bdev_ops->StartStopUnit(lun, params[4] & 1);
 
   return 0;
 }
@@ -479,9 +479,9 @@ static int8_t SCSI_StartStopUnit(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t
 */
 static int8_t SCSI_AllowMediumRemoval(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = pdev->pClassData;   
+  USBD_MSC_BOT_HandleTypeDef *hmsc = &((usbd_cdc_msc_hid_state_t*)pdev->pClassData)->MSC_BOT_ClassData;
   hmsc->bot_data_length = 0;
-  ((USBD_StorageTypeDef *)pdev->pUserData)->PreventAllowMediumRemoval(lun, params[0]);
+  hmsc->bdev_ops->PreventAllowMediumRemoval(lun, params[0]);
   return 0;
 }
 
@@ -494,7 +494,7 @@ static int8_t SCSI_AllowMediumRemoval(USBD_HandleTypeDef  *pdev, uint8_t lun, ui
 */
 static int8_t SCSI_Read10(USBD_HandleTypeDef  *pdev, uint8_t lun , uint8_t *params)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = pdev->pClassData; 
+  USBD_MSC_BOT_HandleTypeDef *hmsc = &((usbd_cdc_msc_hid_state_t*)pdev->pClassData)->MSC_BOT_ClassData;
   
   if(hmsc->bot_state == USBD_BOT_IDLE)  /* Idle */
   {
@@ -510,7 +510,7 @@ static int8_t SCSI_Read10(USBD_HandleTypeDef  *pdev, uint8_t lun , uint8_t *para
       return -1;
     }    
     
-    if(((USBD_StorageTypeDef *)pdev->pUserData)->IsReady(lun) !=0 )
+    if(hmsc->bdev_ops->IsReady(lun) !=0 )
     {
       SCSI_SenseCode(pdev,
                      lun,
@@ -562,7 +562,7 @@ static int8_t SCSI_Read10(USBD_HandleTypeDef  *pdev, uint8_t lun , uint8_t *para
 
 static int8_t SCSI_Write10 (USBD_HandleTypeDef  *pdev, uint8_t lun , uint8_t *params)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = pdev->pClassData; 
+  USBD_MSC_BOT_HandleTypeDef *hmsc = &((usbd_cdc_msc_hid_state_t*)pdev->pClassData)->MSC_BOT_ClassData;
   
   if (hmsc->bot_state == USBD_BOT_IDLE) /* Idle */
   {
@@ -579,7 +579,7 @@ static int8_t SCSI_Write10 (USBD_HandleTypeDef  *pdev, uint8_t lun , uint8_t *pa
     }
     
     /* Check whether Media is ready */
-    if(((USBD_StorageTypeDef *)pdev->pUserData)->IsReady(lun) !=0 )
+    if(hmsc->bdev_ops->IsReady(lun) !=0 )
     {
       SCSI_SenseCode(pdev,
                      lun,
@@ -589,7 +589,7 @@ static int8_t SCSI_Write10 (USBD_HandleTypeDef  *pdev, uint8_t lun , uint8_t *pa
     } 
     
     /* Check If media is write-protected */
-    if(((USBD_StorageTypeDef *)pdev->pUserData)->IsWriteProtected(lun) !=0 )
+    if(hmsc->bdev_ops->IsWriteProtected(lun) !=0 )
     {
       SCSI_SenseCode(pdev,
                      lun,
@@ -652,7 +652,7 @@ static int8_t SCSI_Write10 (USBD_HandleTypeDef  *pdev, uint8_t lun , uint8_t *pa
 
 static int8_t SCSI_Verify10(USBD_HandleTypeDef  *pdev, uint8_t lun , uint8_t *params)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = pdev->pClassData; 
+  USBD_MSC_BOT_HandleTypeDef *hmsc = &((usbd_cdc_msc_hid_state_t*)pdev->pClassData)->MSC_BOT_ClassData;
   
   if ((params[1]& 0x02) == 0x02) 
   {
@@ -687,7 +687,7 @@ static int8_t SCSI_Verify10(USBD_HandleTypeDef  *pdev, uint8_t lun , uint8_t *pa
 */
 static int8_t SCSI_CheckAddressRange (USBD_HandleTypeDef  *pdev, uint8_t lun , uint32_t blk_offset , uint16_t blk_nbr)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = pdev->pClassData; 
+  USBD_MSC_BOT_HandleTypeDef *hmsc = &((usbd_cdc_msc_hid_state_t*)pdev->pClassData)->MSC_BOT_ClassData;
   
   if ((blk_offset + blk_nbr) > hmsc->scsi_blk_nbr )
   {
@@ -708,12 +708,12 @@ static int8_t SCSI_CheckAddressRange (USBD_HandleTypeDef  *pdev, uint8_t lun , u
 */
 static int8_t SCSI_ProcessRead (USBD_HandleTypeDef  *pdev, uint8_t lun)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = pdev->pClassData;   
+  USBD_MSC_BOT_HandleTypeDef *hmsc = &((usbd_cdc_msc_hid_state_t*)pdev->pClassData)->MSC_BOT_ClassData;
   uint32_t len;
   
   len = MIN(hmsc->scsi_blk_len , MSC_MEDIA_PACKET); 
   
-  if( ((USBD_StorageTypeDef *)pdev->pUserData)->Read(lun ,
+  if( hmsc->bdev_ops->Read(lun ,
                               hmsc->bot_data, 
                               hmsc->scsi_blk_addr_in_blks,
                               len / hmsc->scsi_blk_size) < 0)
@@ -756,11 +756,11 @@ static int8_t SCSI_ProcessRead (USBD_HandleTypeDef  *pdev, uint8_t lun)
 static int8_t SCSI_ProcessWrite (USBD_HandleTypeDef  *pdev, uint8_t lun)
 {
   uint32_t len;
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = pdev->pClassData; 
+  USBD_MSC_BOT_HandleTypeDef *hmsc = &((usbd_cdc_msc_hid_state_t*)pdev->pClassData)->MSC_BOT_ClassData;
   
   len = MIN(hmsc->scsi_blk_len , MSC_MEDIA_PACKET); 
   
-  if(((USBD_StorageTypeDef *)pdev->pUserData)->Write(lun ,
+  if(hmsc->bdev_ops->Write(lun ,
                               hmsc->bot_data, 
                               hmsc->scsi_blk_addr_in_blks,
                               len / hmsc->scsi_blk_size) < 0)
diff --git a/stmhal/usbdev/core/inc/usbd_core.h b/ports/stm32/usbdev/core/inc/usbd_core.h
similarity index 96%
rename from stmhal/usbdev/core/inc/usbd_core.h
rename to ports/stm32/usbdev/core/inc/usbd_core.h
index 5360680b92..3178d4a4ba 100644
--- a/stmhal/usbdev/core/inc/usbd_core.h
+++ b/ports/stm32/usbdev/core/inc/usbd_core.h
@@ -88,7 +88,7 @@ USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *
 USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev);
 USBD_StatusTypeDef USBD_Start  (USBD_HandleTypeDef *pdev);
 USBD_StatusTypeDef USBD_Stop   (USBD_HandleTypeDef *pdev);
-USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass);
+USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, const USBD_ClassTypeDef *pclass);
 
 USBD_StatusTypeDef USBD_RunTestMode (USBD_HandleTypeDef  *pdev); 
 USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef  *pdev, uint8_t cfgidx);
diff --git a/stmhal/usbdev/core/inc/usbd_ctlreq.h b/ports/stm32/usbdev/core/inc/usbd_ctlreq.h
similarity index 100%
rename from stmhal/usbdev/core/inc/usbd_ctlreq.h
rename to ports/stm32/usbdev/core/inc/usbd_ctlreq.h
diff --git a/stmhal/usbdev/core/inc/usbd_def.h b/ports/stm32/usbdev/core/inc/usbd_def.h
similarity index 87%
rename from stmhal/usbdev/core/inc/usbd_def.h
rename to ports/stm32/usbdev/core/inc/usbd_def.h
index 5c0506a145..888d426ef3 100644
--- a/stmhal/usbdev/core/inc/usbd_def.h
+++ b/ports/stm32/usbdev/core/inc/usbd_def.h
@@ -168,10 +168,10 @@ typedef struct _Device_cb
   uint8_t  (*IsoINIncomplete)  (struct _USBD_HandleTypeDef *pdev , uint8_t epnum); 
   uint8_t  (*IsoOUTIncomplete) (struct _USBD_HandleTypeDef *pdev , uint8_t epnum);   
 
-  uint8_t  *(*GetHSConfigDescriptor)(uint16_t *length); 
-  uint8_t  *(*GetFSConfigDescriptor)(uint16_t *length);   
-  uint8_t  *(*GetOtherSpeedConfigDescriptor)(uint16_t *length);
-  uint8_t  *(*GetDeviceQualifierDescriptor)(uint16_t *length);
+  uint8_t  *(*GetHSConfigDescriptor)(struct _USBD_HandleTypeDef *pdev, uint16_t *length); 
+  uint8_t  *(*GetFSConfigDescriptor)(struct _USBD_HandleTypeDef *pdev, uint16_t *length);   
+  uint8_t  *(*GetOtherSpeedConfigDescriptor)(struct _USBD_HandleTypeDef *pdev, uint16_t *length);
+  uint8_t  *(*GetDeviceQualifierDescriptor)(struct _USBD_HandleTypeDef *pdev, uint16_t *length);
 #if (USBD_SUPPORT_USER_STRING == 1)
   uint8_t  *(*GetUsrStrDescriptor)(struct _USBD_HandleTypeDef *pdev ,uint8_t index,  uint16_t *length);   
 #endif  
@@ -193,16 +193,18 @@ typedef enum {
   USBD_FAIL,
 }USBD_StatusTypeDef;
 
+struct _USBD_HandleTypeDef;
+
 /* USB Device descriptors structure */
 typedef struct
 {
-  uint8_t  *(*GetDeviceDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length);  
-  uint8_t  *(*GetLangIDStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); 
-  uint8_t  *(*GetManufacturerStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length);  
-  uint8_t  *(*GetProductStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length);  
-  uint8_t  *(*GetSerialStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length);  
-  uint8_t  *(*GetConfigurationStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length);  
-  uint8_t  *(*GetInterfaceStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length);   
+  uint8_t *(*GetDeviceDescriptor)(struct _USBD_HandleTypeDef *pdev, uint16_t *length);
+  uint8_t *(*GetLangIDStrDescriptor)(struct _USBD_HandleTypeDef *pdev, uint16_t *length);
+  uint8_t *(*GetManufacturerStrDescriptor)(struct _USBD_HandleTypeDef *pdev, uint16_t *length);
+  uint8_t *(*GetProductStrDescriptor)(struct _USBD_HandleTypeDef *pdev, uint16_t *length);
+  uint8_t *(*GetSerialStrDescriptor)(struct _USBD_HandleTypeDef *pdev, uint16_t *length);
+  uint8_t *(*GetConfigurationStrDescriptor)(struct _USBD_HandleTypeDef *pdev, uint16_t *length);
+  uint8_t *(*GetInterfaceStrDescriptor)(struct _USBD_HandleTypeDef *pdev, uint16_t *length);
 } USBD_DescriptorsTypeDef;
 
 /* USB Device handle structure */
@@ -235,7 +237,7 @@ typedef struct _USBD_HandleTypeDef
 
   USBD_SetupReqTypedef    request;
   USBD_DescriptorsTypeDef *pDesc;
-  USBD_ClassTypeDef       *pClass;
+  const USBD_ClassTypeDef *pClass;
   void                    *pClassData;  
   void                    *pUserData;    
   void                    *pData;    
diff --git a/stmhal/usbdev/core/inc/usbd_ioreq.h b/ports/stm32/usbdev/core/inc/usbd_ioreq.h
similarity index 100%
rename from stmhal/usbdev/core/inc/usbd_ioreq.h
rename to ports/stm32/usbdev/core/inc/usbd_ioreq.h
diff --git a/stmhal/usbdev/core/src/usbd_core.c b/ports/stm32/usbdev/core/src/usbd_core.c
similarity index 95%
rename from stmhal/usbdev/core/src/usbd_core.c
rename to ports/stm32/usbdev/core/src/usbd_core.c
index bb44513d7b..ae5b99626f 100644
--- a/stmhal/usbdev/core/src/usbd_core.c
+++ b/ports/stm32/usbdev/core/src/usbd_core.c
@@ -155,7 +155,7 @@ USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev)
   * @param  pclass: Class handle
   * @retval USBD Status
   */
-USBD_StatusTypeDef  USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass)
+USBD_StatusTypeDef  USBD_RegisterClass(USBD_HandleTypeDef *pdev, const USBD_ClassTypeDef *pclass)
 {
   USBD_StatusTypeDef   status = USBD_OK;
   if(pclass != 0)
diff --git a/stmhal/usbdev/core/src/usbd_ctlreq.c b/ports/stm32/usbdev/core/src/usbd_ctlreq.c
similarity index 91%
rename from stmhal/usbdev/core/src/usbd_ctlreq.c
rename to ports/stm32/usbdev/core/src/usbd_ctlreq.c
index 80b1da8ea5..5fba322fa6 100644
--- a/stmhal/usbdev/core/src/usbd_ctlreq.c
+++ b/ports/stm32/usbdev/core/src/usbd_ctlreq.c
@@ -330,18 +330,18 @@ static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev ,
   switch (req->wValue >> 8)
   {
   case USB_DESC_TYPE_DEVICE:
-    pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len);
+    pbuf = pdev->pDesc->GetDeviceDescriptor(pdev, &len);
     break;
     
   case USB_DESC_TYPE_CONFIGURATION:     
     if(pdev->dev_speed == USBD_SPEED_HIGH )   
     {
-      pbuf   = (uint8_t *)pdev->pClass->GetHSConfigDescriptor(&len);
+      pbuf   = (uint8_t *)pdev->pClass->GetHSConfigDescriptor(pdev, &len);
       pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
     }
     else
     {
-      pbuf   = (uint8_t *)pdev->pClass->GetFSConfigDescriptor(&len);
+      pbuf   = (uint8_t *)pdev->pClass->GetFSConfigDescriptor(pdev, &len);
       pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
     }
     break;
@@ -350,27 +350,27 @@ static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev ,
     switch ((uint8_t)(req->wValue))
     {
     case USBD_IDX_LANGID_STR:
-     pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len);        
+     pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev, &len);        
       break;
       
     case USBD_IDX_MFC_STR:
-      pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len);
+      pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev, &len);
       break;
       
     case USBD_IDX_PRODUCT_STR:
-      pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len);
+      pbuf = pdev->pDesc->GetProductStrDescriptor(pdev, &len);
       break;
       
     case USBD_IDX_SERIAL_STR:
-      pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len);
+      pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev, &len);
       break;
       
     case USBD_IDX_CONFIG_STR:
-      pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len);
+      pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev, &len);
       break;
       
     case USBD_IDX_INTERFACE_STR:
-      pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len);
+      pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev, &len);
       break;
       
     default:
@@ -387,7 +387,7 @@ static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev ,
 
     if(pdev->dev_speed == USBD_SPEED_HIGH  )   
     {
-      pbuf   = (uint8_t *)pdev->pClass->GetDeviceQualifierDescriptor(&len);
+      pbuf   = (uint8_t *)pdev->pClass->GetDeviceQualifierDescriptor(pdev, &len);
       break;
     }
     else
@@ -399,7 +399,7 @@ static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev ,
   case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION:
     if(pdev->dev_speed == USBD_SPEED_HIGH  )   
     {
-      pbuf   = (uint8_t *)pdev->pClass->GetOtherSpeedConfigDescriptor(&len);
+      pbuf   = (uint8_t *)pdev->pClass->GetOtherSpeedConfigDescriptor(pdev, &len);
       pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION;
       break; 
     }
@@ -479,7 +479,7 @@ static void USBD_SetConfig(USBD_HandleTypeDef *pdev ,
                            USBD_SetupReqTypedef *req)
 {
   
-  static uint8_t  cfgidx;
+  uint8_t cfgidx;
   
   cfgidx = (uint8_t)(req->wValue);                 
   
diff --git a/stmhal/usbdev/core/src/usbd_ioreq.c b/ports/stm32/usbdev/core/src/usbd_ioreq.c
similarity index 100%
rename from stmhal/usbdev/core/src/usbd_ioreq.c
rename to ports/stm32/usbdev/core/src/usbd_ioreq.c
diff --git a/stmhal/usbhost/Class/AUDIO/Inc/usbh_audio.h b/ports/stm32/usbhost/Class/AUDIO/Inc/usbh_audio.h
similarity index 100%
rename from stmhal/usbhost/Class/AUDIO/Inc/usbh_audio.h
rename to ports/stm32/usbhost/Class/AUDIO/Inc/usbh_audio.h
diff --git a/stmhal/usbhost/Class/AUDIO/Src/usbh_audio.c b/ports/stm32/usbhost/Class/AUDIO/Src/usbh_audio.c
similarity index 100%
rename from stmhal/usbhost/Class/AUDIO/Src/usbh_audio.c
rename to ports/stm32/usbhost/Class/AUDIO/Src/usbh_audio.c
diff --git a/stmhal/usbhost/Class/CDC/Inc/usbh_cdc.h b/ports/stm32/usbhost/Class/CDC/Inc/usbh_cdc.h
similarity index 100%
rename from stmhal/usbhost/Class/CDC/Inc/usbh_cdc.h
rename to ports/stm32/usbhost/Class/CDC/Inc/usbh_cdc.h
diff --git a/stmhal/usbhost/Class/CDC/Src/usbh_cdc.c b/ports/stm32/usbhost/Class/CDC/Src/usbh_cdc.c
similarity index 100%
rename from stmhal/usbhost/Class/CDC/Src/usbh_cdc.c
rename to ports/stm32/usbhost/Class/CDC/Src/usbh_cdc.c
diff --git a/stmhal/usbhost/Class/HID/Inc/usbh_hid.h b/ports/stm32/usbhost/Class/HID/Inc/usbh_hid.h
similarity index 100%
rename from stmhal/usbhost/Class/HID/Inc/usbh_hid.h
rename to ports/stm32/usbhost/Class/HID/Inc/usbh_hid.h
diff --git a/stmhal/usbhost/Class/HID/Inc/usbh_hid_keybd.h b/ports/stm32/usbhost/Class/HID/Inc/usbh_hid_keybd.h
similarity index 100%
rename from stmhal/usbhost/Class/HID/Inc/usbh_hid_keybd.h
rename to ports/stm32/usbhost/Class/HID/Inc/usbh_hid_keybd.h
diff --git a/stmhal/usbhost/Class/HID/Inc/usbh_hid_mouse.h b/ports/stm32/usbhost/Class/HID/Inc/usbh_hid_mouse.h
similarity index 100%
rename from stmhal/usbhost/Class/HID/Inc/usbh_hid_mouse.h
rename to ports/stm32/usbhost/Class/HID/Inc/usbh_hid_mouse.h
diff --git a/stmhal/usbhost/Class/HID/Inc/usbh_hid_parser.h b/ports/stm32/usbhost/Class/HID/Inc/usbh_hid_parser.h
similarity index 100%
rename from stmhal/usbhost/Class/HID/Inc/usbh_hid_parser.h
rename to ports/stm32/usbhost/Class/HID/Inc/usbh_hid_parser.h
diff --git a/stmhal/usbhost/Class/HID/Inc/usbh_hid_usage.h b/ports/stm32/usbhost/Class/HID/Inc/usbh_hid_usage.h
similarity index 100%
rename from stmhal/usbhost/Class/HID/Inc/usbh_hid_usage.h
rename to ports/stm32/usbhost/Class/HID/Inc/usbh_hid_usage.h
diff --git a/stmhal/usbhost/Class/HID/Src/usbh_hid.c b/ports/stm32/usbhost/Class/HID/Src/usbh_hid.c
similarity index 100%
rename from stmhal/usbhost/Class/HID/Src/usbh_hid.c
rename to ports/stm32/usbhost/Class/HID/Src/usbh_hid.c
diff --git a/stmhal/usbhost/Class/HID/Src/usbh_hid_keybd.c b/ports/stm32/usbhost/Class/HID/Src/usbh_hid_keybd.c
similarity index 100%
rename from stmhal/usbhost/Class/HID/Src/usbh_hid_keybd.c
rename to ports/stm32/usbhost/Class/HID/Src/usbh_hid_keybd.c
diff --git a/stmhal/usbhost/Class/HID/Src/usbh_hid_mouse.c b/ports/stm32/usbhost/Class/HID/Src/usbh_hid_mouse.c
similarity index 100%
rename from stmhal/usbhost/Class/HID/Src/usbh_hid_mouse.c
rename to ports/stm32/usbhost/Class/HID/Src/usbh_hid_mouse.c
diff --git a/stmhal/usbhost/Class/HID/Src/usbh_hid_parser.c b/ports/stm32/usbhost/Class/HID/Src/usbh_hid_parser.c
similarity index 100%
rename from stmhal/usbhost/Class/HID/Src/usbh_hid_parser.c
rename to ports/stm32/usbhost/Class/HID/Src/usbh_hid_parser.c
diff --git a/stmhal/usbhost/Class/MSC/Inc/usbh_msc.h b/ports/stm32/usbhost/Class/MSC/Inc/usbh_msc.h
similarity index 100%
rename from stmhal/usbhost/Class/MSC/Inc/usbh_msc.h
rename to ports/stm32/usbhost/Class/MSC/Inc/usbh_msc.h
diff --git a/stmhal/usbhost/Class/MSC/Inc/usbh_msc_bot.h b/ports/stm32/usbhost/Class/MSC/Inc/usbh_msc_bot.h
similarity index 100%
rename from stmhal/usbhost/Class/MSC/Inc/usbh_msc_bot.h
rename to ports/stm32/usbhost/Class/MSC/Inc/usbh_msc_bot.h
diff --git a/stmhal/usbhost/Class/MSC/Inc/usbh_msc_scsi.h b/ports/stm32/usbhost/Class/MSC/Inc/usbh_msc_scsi.h
similarity index 100%
rename from stmhal/usbhost/Class/MSC/Inc/usbh_msc_scsi.h
rename to ports/stm32/usbhost/Class/MSC/Inc/usbh_msc_scsi.h
diff --git a/stmhal/usbhost/Class/MSC/Src/usbh_msc.c b/ports/stm32/usbhost/Class/MSC/Src/usbh_msc.c
similarity index 100%
rename from stmhal/usbhost/Class/MSC/Src/usbh_msc.c
rename to ports/stm32/usbhost/Class/MSC/Src/usbh_msc.c
diff --git a/stmhal/usbhost/Class/MSC/Src/usbh_msc_bot.c b/ports/stm32/usbhost/Class/MSC/Src/usbh_msc_bot.c
similarity index 100%
rename from stmhal/usbhost/Class/MSC/Src/usbh_msc_bot.c
rename to ports/stm32/usbhost/Class/MSC/Src/usbh_msc_bot.c
diff --git a/stmhal/usbhost/Class/MSC/Src/usbh_msc_scsi.c b/ports/stm32/usbhost/Class/MSC/Src/usbh_msc_scsi.c
similarity index 100%
rename from stmhal/usbhost/Class/MSC/Src/usbh_msc_scsi.c
rename to ports/stm32/usbhost/Class/MSC/Src/usbh_msc_scsi.c
diff --git a/stmhal/usbhost/Class/MTP/Inc/usbh_mtp.h b/ports/stm32/usbhost/Class/MTP/Inc/usbh_mtp.h
similarity index 100%
rename from stmhal/usbhost/Class/MTP/Inc/usbh_mtp.h
rename to ports/stm32/usbhost/Class/MTP/Inc/usbh_mtp.h
diff --git a/stmhal/usbhost/Class/MTP/Inc/usbh_mtp_ptp.h b/ports/stm32/usbhost/Class/MTP/Inc/usbh_mtp_ptp.h
similarity index 100%
rename from stmhal/usbhost/Class/MTP/Inc/usbh_mtp_ptp.h
rename to ports/stm32/usbhost/Class/MTP/Inc/usbh_mtp_ptp.h
diff --git a/stmhal/usbhost/Class/MTP/Src/usbh_mtp.c b/ports/stm32/usbhost/Class/MTP/Src/usbh_mtp.c
similarity index 100%
rename from stmhal/usbhost/Class/MTP/Src/usbh_mtp.c
rename to ports/stm32/usbhost/Class/MTP/Src/usbh_mtp.c
diff --git a/stmhal/usbhost/Class/MTP/Src/usbh_mtp_ptp.c b/ports/stm32/usbhost/Class/MTP/Src/usbh_mtp_ptp.c
similarity index 100%
rename from stmhal/usbhost/Class/MTP/Src/usbh_mtp_ptp.c
rename to ports/stm32/usbhost/Class/MTP/Src/usbh_mtp_ptp.c
diff --git a/stmhal/usbhost/Class/Template/Inc/usbh_template.h b/ports/stm32/usbhost/Class/Template/Inc/usbh_template.h
similarity index 100%
rename from stmhal/usbhost/Class/Template/Inc/usbh_template.h
rename to ports/stm32/usbhost/Class/Template/Inc/usbh_template.h
diff --git a/stmhal/usbhost/Class/Template/Src/usbh_template.c b/ports/stm32/usbhost/Class/Template/Src/usbh_template.c
similarity index 100%
rename from stmhal/usbhost/Class/Template/Src/usbh_template.c
rename to ports/stm32/usbhost/Class/Template/Src/usbh_template.c
diff --git a/stmhal/usbhost/Core/Inc/usbh_conf_template.h b/ports/stm32/usbhost/Core/Inc/usbh_conf_template.h
similarity index 100%
rename from stmhal/usbhost/Core/Inc/usbh_conf_template.h
rename to ports/stm32/usbhost/Core/Inc/usbh_conf_template.h
diff --git a/stmhal/usbhost/Core/Inc/usbh_core.h b/ports/stm32/usbhost/Core/Inc/usbh_core.h
similarity index 100%
rename from stmhal/usbhost/Core/Inc/usbh_core.h
rename to ports/stm32/usbhost/Core/Inc/usbh_core.h
diff --git a/stmhal/usbhost/Core/Inc/usbh_ctlreq.h b/ports/stm32/usbhost/Core/Inc/usbh_ctlreq.h
similarity index 100%
rename from stmhal/usbhost/Core/Inc/usbh_ctlreq.h
rename to ports/stm32/usbhost/Core/Inc/usbh_ctlreq.h
diff --git a/stmhal/usbhost/Core/Inc/usbh_def.h b/ports/stm32/usbhost/Core/Inc/usbh_def.h
similarity index 100%
rename from stmhal/usbhost/Core/Inc/usbh_def.h
rename to ports/stm32/usbhost/Core/Inc/usbh_def.h
diff --git a/stmhal/usbhost/Core/Inc/usbh_ioreq.h b/ports/stm32/usbhost/Core/Inc/usbh_ioreq.h
similarity index 100%
rename from stmhal/usbhost/Core/Inc/usbh_ioreq.h
rename to ports/stm32/usbhost/Core/Inc/usbh_ioreq.h
diff --git a/stmhal/usbhost/Core/Inc/usbh_pipes.h b/ports/stm32/usbhost/Core/Inc/usbh_pipes.h
similarity index 100%
rename from stmhal/usbhost/Core/Inc/usbh_pipes.h
rename to ports/stm32/usbhost/Core/Inc/usbh_pipes.h
diff --git a/stmhal/usbhost/Core/Src/usbh_conf_template.c b/ports/stm32/usbhost/Core/Src/usbh_conf_template.c
similarity index 100%
rename from stmhal/usbhost/Core/Src/usbh_conf_template.c
rename to ports/stm32/usbhost/Core/Src/usbh_conf_template.c
diff --git a/stmhal/usbhost/Core/Src/usbh_core.c b/ports/stm32/usbhost/Core/Src/usbh_core.c
similarity index 100%
rename from stmhal/usbhost/Core/Src/usbh_core.c
rename to ports/stm32/usbhost/Core/Src/usbh_core.c
diff --git a/stmhal/usbhost/Core/Src/usbh_ctlreq.c b/ports/stm32/usbhost/Core/Src/usbh_ctlreq.c
similarity index 100%
rename from stmhal/usbhost/Core/Src/usbh_ctlreq.c
rename to ports/stm32/usbhost/Core/Src/usbh_ctlreq.c
diff --git a/stmhal/usbhost/Core/Src/usbh_ioreq.c b/ports/stm32/usbhost/Core/Src/usbh_ioreq.c
similarity index 100%
rename from stmhal/usbhost/Core/Src/usbh_ioreq.c
rename to ports/stm32/usbhost/Core/Src/usbh_ioreq.c
diff --git a/stmhal/usbhost/Core/Src/usbh_pipes.c b/ports/stm32/usbhost/Core/Src/usbh_pipes.c
similarity index 100%
rename from stmhal/usbhost/Core/Src/usbh_pipes.c
rename to ports/stm32/usbhost/Core/Src/usbh_pipes.c
diff --git a/stmhal/usbhost/Release_Notes.html b/ports/stm32/usbhost/Release_Notes.html
similarity index 100%
rename from stmhal/usbhost/Release_Notes.html
rename to ports/stm32/usbhost/Release_Notes.html
diff --git a/stmhal/usrsw.c b/ports/stm32/usrsw.c
similarity index 100%
rename from stmhal/usrsw.c
rename to ports/stm32/usrsw.c
diff --git a/stmhal/usrsw.h b/ports/stm32/usrsw.h
similarity index 100%
rename from stmhal/usrsw.h
rename to ports/stm32/usrsw.h
diff --git a/stmhal/wdt.c b/ports/stm32/wdt.c
similarity index 100%
rename from stmhal/wdt.c
rename to ports/stm32/wdt.c
diff --git a/stmhal/wdt.h b/ports/stm32/wdt.h
similarity index 100%
rename from stmhal/wdt.h
rename to ports/stm32/wdt.h
diff --git a/teensy/Makefile b/ports/teensy/Makefile
similarity index 97%
rename from teensy/Makefile
rename to ports/teensy/Makefile
index 9990e4cc47..e6d848b65a 100644
--- a/teensy/Makefile
+++ b/ports/teensy/Makefile
@@ -1,4 +1,4 @@
-include ../py/mkenv.mk
+include ../../py/mkenv.mk
 
 # qstr definitions (must come before including py.mk)
 QSTR_DEFS = qstrdefsport.h $(BUILD)/pins_qstr.h
@@ -31,7 +31,7 @@ CFLAGS_CORTEX_M4 = -mthumb -mtune=cortex-m4 -mcpu=cortex-m4 -msoft-float -mfloat
 
 INC += -I.
 INC += -I$(TOP)
-INC += -I$(TOP)/stmhal
+INC += -I$(TOP)/ports/stm32
 INC += -I$(BUILD)
 INC += -Icore
 
@@ -91,14 +91,14 @@ SRC_C = \
 	uart.c \
 	usb.c \
 
-STM_SRC_C = $(addprefix stmhal/,\
+STM_SRC_C = $(addprefix ports/stm32/,\
 	gccollect.c \
 	irq.c \
 	pin.c \
 	pin_named_pins.c \
 	)
 
-STM_SRC_S = $(addprefix stmhal/,\
+STM_SRC_S = $(addprefix ports/stm32/,\
 	gchelper.s \
 	)
 
diff --git a/teensy/README.md b/ports/teensy/README.md
similarity index 100%
rename from teensy/README.md
rename to ports/teensy/README.md
diff --git a/teensy/add-memzip.sh b/ports/teensy/add-memzip.sh
similarity index 100%
rename from teensy/add-memzip.sh
rename to ports/teensy/add-memzip.sh
diff --git a/teensy/core/Arduino.h b/ports/teensy/core/Arduino.h
similarity index 100%
rename from teensy/core/Arduino.h
rename to ports/teensy/core/Arduino.h
diff --git a/teensy/core/HardwareSerial.h b/ports/teensy/core/HardwareSerial.h
similarity index 100%
rename from teensy/core/HardwareSerial.h
rename to ports/teensy/core/HardwareSerial.h
diff --git a/teensy/core/analog.c b/ports/teensy/core/analog.c
similarity index 100%
rename from teensy/core/analog.c
rename to ports/teensy/core/analog.c
diff --git a/teensy/core/avr_functions.h b/ports/teensy/core/avr_functions.h
similarity index 100%
rename from teensy/core/avr_functions.h
rename to ports/teensy/core/avr_functions.h
diff --git a/teensy/core/core_pins.h b/ports/teensy/core/core_pins.h
similarity index 100%
rename from teensy/core/core_pins.h
rename to ports/teensy/core/core_pins.h
diff --git a/teensy/core/mk20dx128.c b/ports/teensy/core/mk20dx128.c
similarity index 100%
rename from teensy/core/mk20dx128.c
rename to ports/teensy/core/mk20dx128.c
diff --git a/teensy/core/mk20dx128.h b/ports/teensy/core/mk20dx128.h
similarity index 100%
rename from teensy/core/mk20dx128.h
rename to ports/teensy/core/mk20dx128.h
diff --git a/teensy/core/pins_arduino.h b/ports/teensy/core/pins_arduino.h
similarity index 100%
rename from teensy/core/pins_arduino.h
rename to ports/teensy/core/pins_arduino.h
diff --git a/teensy/core/pins_teensy.c b/ports/teensy/core/pins_teensy.c
similarity index 100%
rename from teensy/core/pins_teensy.c
rename to ports/teensy/core/pins_teensy.c
diff --git a/teensy/core/usb_desc.c b/ports/teensy/core/usb_desc.c
similarity index 100%
rename from teensy/core/usb_desc.c
rename to ports/teensy/core/usb_desc.c
diff --git a/teensy/core/usb_desc.h b/ports/teensy/core/usb_desc.h
similarity index 100%
rename from teensy/core/usb_desc.h
rename to ports/teensy/core/usb_desc.h
diff --git a/teensy/core/usb_dev.c b/ports/teensy/core/usb_dev.c
similarity index 100%
rename from teensy/core/usb_dev.c
rename to ports/teensy/core/usb_dev.c
diff --git a/teensy/core/usb_dev.h b/ports/teensy/core/usb_dev.h
similarity index 100%
rename from teensy/core/usb_dev.h
rename to ports/teensy/core/usb_dev.h
diff --git a/teensy/core/usb_mem.c b/ports/teensy/core/usb_mem.c
similarity index 100%
rename from teensy/core/usb_mem.c
rename to ports/teensy/core/usb_mem.c
diff --git a/teensy/core/usb_mem.h b/ports/teensy/core/usb_mem.h
similarity index 100%
rename from teensy/core/usb_mem.h
rename to ports/teensy/core/usb_mem.h
diff --git a/teensy/core/usb_names.h b/ports/teensy/core/usb_names.h
similarity index 100%
rename from teensy/core/usb_names.h
rename to ports/teensy/core/usb_names.h
diff --git a/teensy/core/usb_serial.c b/ports/teensy/core/usb_serial.c
similarity index 100%
rename from teensy/core/usb_serial.c
rename to ports/teensy/core/usb_serial.c
diff --git a/teensy/core/usb_serial.h b/ports/teensy/core/usb_serial.h
similarity index 100%
rename from teensy/core/usb_serial.h
rename to ports/teensy/core/usb_serial.h
diff --git a/teensy/core/yield.c b/ports/teensy/core/yield.c
similarity index 100%
rename from teensy/core/yield.c
rename to ports/teensy/core/yield.c
diff --git a/teensy/hal_ftm.c b/ports/teensy/hal_ftm.c
similarity index 100%
rename from teensy/hal_ftm.c
rename to ports/teensy/hal_ftm.c
diff --git a/teensy/hal_ftm.h b/ports/teensy/hal_ftm.h
similarity index 100%
rename from teensy/hal_ftm.h
rename to ports/teensy/hal_ftm.h
diff --git a/teensy/hal_gpio.c b/ports/teensy/hal_gpio.c
similarity index 100%
rename from teensy/hal_gpio.c
rename to ports/teensy/hal_gpio.c
diff --git a/teensy/help.c b/ports/teensy/help.c
similarity index 99%
rename from teensy/help.c
rename to ports/teensy/help.c
index ebe4bed6bf..a2370c04d2 100644
--- a/teensy/help.c
+++ b/ports/teensy/help.c
@@ -26,7 +26,7 @@
 
 #include "py/builtin.h"
 
-const char *teensy_help_text =
+const char teensy_help_text[] =
 "Welcome to MicroPython!\n"
 "\n"
 "For online help please visit http://micropython.org/help/.\n"
diff --git a/teensy/lcd.c b/ports/teensy/lcd.c
similarity index 87%
rename from teensy/lcd.c
rename to ports/teensy/lcd.c
index e79b7d5acb..e5d6115d75 100644
--- a/teensy/lcd.c
+++ b/ports/teensy/lcd.c
@@ -1,5 +1,5 @@
 #include "py/obj.h"
-#include "../stmhal/lcd.h"
+#include "../stm32/lcd.h"
 
 void lcd_init(void) {
 }
diff --git a/teensy/led.c b/ports/teensy/led.c
similarity index 99%
rename from teensy/led.c
rename to ports/teensy/led.c
index 9159c75cef..add052fad2 100644
--- a/teensy/led.c
+++ b/ports/teensy/led.c
@@ -2,7 +2,6 @@
 
 #include "Arduino.h"
 
-#include "py/nlr.h"
 #include "py/runtime.h"
 #include "py/mphal.h"
 #include "led.h"
diff --git a/teensy/led.h b/ports/teensy/led.h
similarity index 100%
rename from teensy/led.h
rename to ports/teensy/led.h
diff --git a/teensy/lexerfrozen.c b/ports/teensy/lexerfrozen.c
similarity index 100%
rename from teensy/lexerfrozen.c
rename to ports/teensy/lexerfrozen.c
diff --git a/teensy/lexermemzip.h b/ports/teensy/lexermemzip.h
similarity index 100%
rename from teensy/lexermemzip.h
rename to ports/teensy/lexermemzip.h
diff --git a/teensy/main.c b/ports/teensy/main.c
similarity index 100%
rename from teensy/main.c
rename to ports/teensy/main.c
diff --git a/teensy/make-pins.py b/ports/teensy/make-pins.py
similarity index 100%
rename from teensy/make-pins.py
rename to ports/teensy/make-pins.py
diff --git a/teensy/memzip_files/boot.py b/ports/teensy/memzip_files/boot.py
similarity index 100%
rename from teensy/memzip_files/boot.py
rename to ports/teensy/memzip_files/boot.py
diff --git a/teensy/memzip_files/main.py b/ports/teensy/memzip_files/main.py
similarity index 100%
rename from teensy/memzip_files/main.py
rename to ports/teensy/memzip_files/main.py
diff --git a/teensy/mk20dx256.ld b/ports/teensy/mk20dx256.ld
similarity index 100%
rename from teensy/mk20dx256.ld
rename to ports/teensy/mk20dx256.ld
diff --git a/teensy/mk20dx256_af.csv b/ports/teensy/mk20dx256_af.csv
similarity index 100%
rename from teensy/mk20dx256_af.csv
rename to ports/teensy/mk20dx256_af.csv
diff --git a/teensy/mk20dx256_prefix.c b/ports/teensy/mk20dx256_prefix.c
similarity index 100%
rename from teensy/mk20dx256_prefix.c
rename to ports/teensy/mk20dx256_prefix.c
diff --git a/teensy/modpyb.c b/ports/teensy/modpyb.c
similarity index 100%
rename from teensy/modpyb.c
rename to ports/teensy/modpyb.c
diff --git a/teensy/mpconfigport.h b/ports/teensy/mpconfigport.h
similarity index 100%
rename from teensy/mpconfigport.h
rename to ports/teensy/mpconfigport.h
diff --git a/teensy/pin_defs_teensy.c b/ports/teensy/pin_defs_teensy.c
similarity index 100%
rename from teensy/pin_defs_teensy.c
rename to ports/teensy/pin_defs_teensy.c
diff --git a/teensy/pin_defs_teensy.h b/ports/teensy/pin_defs_teensy.h
similarity index 100%
rename from teensy/pin_defs_teensy.h
rename to ports/teensy/pin_defs_teensy.h
diff --git a/teensy/qstrdefsport.h b/ports/teensy/qstrdefsport.h
similarity index 100%
rename from teensy/qstrdefsport.h
rename to ports/teensy/qstrdefsport.h
diff --git a/teensy/reg.c b/ports/teensy/reg.c
similarity index 100%
rename from teensy/reg.c
rename to ports/teensy/reg.c
diff --git a/teensy/reg.h b/ports/teensy/reg.h
similarity index 100%
rename from teensy/reg.h
rename to ports/teensy/reg.h
diff --git a/teensy/servo.c b/ports/teensy/servo.c
similarity index 100%
rename from teensy/servo.c
rename to ports/teensy/servo.c
diff --git a/teensy/servo.h b/ports/teensy/servo.h
similarity index 100%
rename from teensy/servo.h
rename to ports/teensy/servo.h
diff --git a/teensy/std.h b/ports/teensy/std.h
similarity index 100%
rename from teensy/std.h
rename to ports/teensy/std.h
diff --git a/teensy/teensy_hal.c b/ports/teensy/teensy_hal.c
similarity index 98%
rename from teensy/teensy_hal.c
rename to ports/teensy/teensy_hal.c
index 439e3380d9..84d68cff89 100644
--- a/teensy/teensy_hal.c
+++ b/ports/teensy/teensy_hal.c
@@ -1,7 +1,6 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "py/mpstate.h"
 #include "py/runtime.h"
 #include "py/mphal.h"
 #include "usb.h"
diff --git a/teensy/teensy_hal.h b/ports/teensy/teensy_hal.h
similarity index 100%
rename from teensy/teensy_hal.h
rename to ports/teensy/teensy_hal.h
diff --git a/teensy/teensy_pins.csv b/ports/teensy/teensy_pins.csv
similarity index 100%
rename from teensy/teensy_pins.csv
rename to ports/teensy/teensy_pins.csv
diff --git a/teensy/timer.c b/ports/teensy/timer.c
similarity index 98%
rename from teensy/timer.c
rename to ports/teensy/timer.c
index 5c6026a8a9..b823e6c3b9 100644
--- a/teensy/timer.c
+++ b/ports/teensy/timer.c
@@ -29,7 +29,6 @@
 #include <string.h>
 #include <stddef.h>
 
-#include "py/nlr.h"
 #include "py/runtime.h"
 #include "py/gc.h"
 #include "py/mphal.h"
@@ -341,7 +340,7 @@ STATIC mp_obj_t pyb_timer_make_new(const mp_obj_type_t *type, size_t n_args, siz
     return (mp_obj_t)tim;
 }
 
-STATIC mp_obj_t pyb_timer_init(mp_uint_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_timer_init(size_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
     return pyb_timer_init_helper(args[0], n_args - 1, args + 1, kw_args);
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_KW(pyb_timer_init_obj, 1, pyb_timer_init);
@@ -440,7 +439,7 @@ STATIC const mp_arg_t pyb_timer_channel_args[] = {
 };
 #define PYB_TIMER_CHANNEL_NUM_ARGS MP_ARRAY_SIZE(pyb_timer_channel_args)
 
-STATIC mp_obj_t pyb_timer_channel(mp_uint_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
+STATIC mp_obj_t pyb_timer_channel(size_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
     pyb_timer_obj_t *self = args[0];
     mp_int_t channel = mp_obj_get_int(args[1]);
 
@@ -601,7 +600,7 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_KW(pyb_timer_channel_obj, 2, pyb_timer_channel);
 
 /// \method counter([value])
 /// Get or set the timer counter.
-STATIC mp_obj_t pyb_timer_counter(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t pyb_timer_counter(size_t n_args, const mp_obj_t *args) {
     pyb_timer_obj_t *self = args[0];
     if (n_args == 1) {
         // get
@@ -616,7 +615,7 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_timer_counter_obj, 1, 2, pyb_time
 
 /// \method prescaler([value])
 /// Get or set the prescaler for the timer.
-STATIC mp_obj_t pyb_timer_prescaler(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t pyb_timer_prescaler(size_t n_args, const mp_obj_t *args) {
     pyb_timer_obj_t *self = args[0];
     if (n_args == 1) {
         // get
@@ -637,7 +636,7 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_timer_prescaler_obj, 1, 2, pyb_ti
 
 /// \method period([value])
 /// Get or set the period of the timer.
-STATIC mp_obj_t pyb_timer_period(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t pyb_timer_period(size_t n_args, const mp_obj_t *args) {
     pyb_timer_obj_t *self = args[0];
     if (n_args == 1) {
         // get
@@ -777,7 +776,7 @@ STATIC void pyb_timer_channel_print(const mp_print_t *print, mp_obj_t self_in, m
 /// 
 /// In edge aligned mode, a pulse_width of `period + 1` corresponds to a duty cycle of 100%
 /// In center aligned mode, a pulse width of `period` corresponds to a duty cycle of 100%
-STATIC mp_obj_t pyb_timer_channel_capture_compare(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t pyb_timer_channel_capture_compare(size_t n_args, const mp_obj_t *args) {
     pyb_timer_channel_obj_t *self = args[0];
     FTM_TypeDef *FTMx = self->timer->ftm.Instance;
     if (n_args == 1) {
@@ -799,7 +798,7 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_timer_channel_capture_compare_obj
 /// for which the pulse is active.  The value can be an integer or
 /// floating-point number for more accuracy.  For example, a value of 25 gives
 /// a duty cycle of 25%.
-STATIC mp_obj_t pyb_timer_channel_pulse_width_percent(mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t pyb_timer_channel_pulse_width_percent(size_t n_args, const mp_obj_t *args) {
     pyb_timer_channel_obj_t *self = args[0];
     FTM_TypeDef *FTMx = self->timer->ftm.Instance;
     uint32_t period = compute_period(self->timer);
diff --git a/teensy/timer.h b/ports/teensy/timer.h
similarity index 100%
rename from teensy/timer.h
rename to ports/teensy/timer.h
diff --git a/teensy/uart.c b/ports/teensy/uart.c
similarity index 99%
rename from teensy/uart.c
rename to ports/teensy/uart.c
index 768572aff5..3d5111217b 100644
--- a/teensy/uart.c
+++ b/ports/teensy/uart.c
@@ -27,7 +27,6 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "py/nlr.h"
 #include "py/runtime.h"
 #include "bufhelper.h"
 #include "uart.h"
diff --git a/teensy/usb.c b/ports/teensy/usb.c
similarity index 100%
rename from teensy/usb.c
rename to ports/teensy/usb.c
diff --git a/teensy/usb.h b/ports/teensy/usb.h
similarity index 100%
rename from teensy/usb.h
rename to ports/teensy/usb.h
diff --git a/unix/.gitignore b/ports/unix/.gitignore
similarity index 100%
rename from unix/.gitignore
rename to ports/unix/.gitignore
diff --git a/unix/Makefile b/ports/unix/Makefile
similarity index 98%
rename from unix/Makefile
rename to ports/unix/Makefile
index 818f482370..dbe3e592ef 100644
--- a/unix/Makefile
+++ b/ports/unix/Makefile
@@ -1,5 +1,5 @@
 -include mpconfigport.mk
-include ../py/mkenv.mk
+include ../../py/mkenv.mk
 
 FROZEN_DIR = scripts
 FROZEN_MPY_DIR = modules
@@ -188,7 +188,7 @@ include $(TOP)/py/mkrules.mk
 .PHONY: test
 
 test: $(PROG) $(TOP)/tests/run-tests
-	$(eval DIRNAME=$(notdir $(CURDIR)))
+	$(eval DIRNAME=ports/$(notdir $(CURDIR)))
 	cd $(TOP)/tests && MICROPY_MICROPYTHON=../$(DIRNAME)/$(PROG) ./run-tests
 
 # install micropython in /usr/local/bin
@@ -253,7 +253,7 @@ coverage:
 	    BUILD=build-coverage PROG=micropython_coverage
 
 coverage_test: coverage
-	$(eval DIRNAME=$(notdir $(CURDIR)))
+	$(eval DIRNAME=ports/$(notdir $(CURDIR)))
 	cd $(TOP)/tests && MICROPY_MICROPYTHON=../$(DIRNAME)/micropython_coverage ./run-tests
 	cd $(TOP)/tests && MICROPY_MICROPYTHON=../$(DIRNAME)/micropython_coverage ./run-tests -d thread
 	cd $(TOP)/tests && MICROPY_MICROPYTHON=../$(DIRNAME)/micropython_coverage ./run-tests --emit native
diff --git a/unix/alloc.c b/ports/unix/alloc.c
similarity index 100%
rename from unix/alloc.c
rename to ports/unix/alloc.c
diff --git a/unix/coverage-frzmpy/frzmpy1.py b/ports/unix/coverage-frzmpy/frzmpy1.py
similarity index 100%
rename from unix/coverage-frzmpy/frzmpy1.py
rename to ports/unix/coverage-frzmpy/frzmpy1.py
diff --git a/unix/coverage-frzmpy/frzmpy2.py b/ports/unix/coverage-frzmpy/frzmpy2.py
similarity index 100%
rename from unix/coverage-frzmpy/frzmpy2.py
rename to ports/unix/coverage-frzmpy/frzmpy2.py
diff --git a/unix/coverage-frzmpy/frzmpy_pkg1/__init__.py b/ports/unix/coverage-frzmpy/frzmpy_pkg1/__init__.py
similarity index 100%
rename from unix/coverage-frzmpy/frzmpy_pkg1/__init__.py
rename to ports/unix/coverage-frzmpy/frzmpy_pkg1/__init__.py
diff --git a/unix/coverage-frzmpy/frzmpy_pkg2/mod.py b/ports/unix/coverage-frzmpy/frzmpy_pkg2/mod.py
similarity index 100%
rename from unix/coverage-frzmpy/frzmpy_pkg2/mod.py
rename to ports/unix/coverage-frzmpy/frzmpy_pkg2/mod.py
diff --git a/unix/coverage-frzstr/frzstr1.py b/ports/unix/coverage-frzstr/frzstr1.py
similarity index 100%
rename from unix/coverage-frzstr/frzstr1.py
rename to ports/unix/coverage-frzstr/frzstr1.py
diff --git a/unix/coverage-frzstr/frzstr_pkg1/__init__.py b/ports/unix/coverage-frzstr/frzstr_pkg1/__init__.py
similarity index 100%
rename from unix/coverage-frzstr/frzstr_pkg1/__init__.py
rename to ports/unix/coverage-frzstr/frzstr_pkg1/__init__.py
diff --git a/unix/coverage-frzstr/frzstr_pkg2/mod.py b/ports/unix/coverage-frzstr/frzstr_pkg2/mod.py
similarity index 100%
rename from unix/coverage-frzstr/frzstr_pkg2/mod.py
rename to ports/unix/coverage-frzstr/frzstr_pkg2/mod.py
diff --git a/unix/coverage.c b/ports/unix/coverage.c
similarity index 96%
rename from unix/coverage.c
rename to ports/unix/coverage.c
index 4a9ab194bb..651db0a943 100644
--- a/unix/coverage.c
+++ b/ports/unix/coverage.c
@@ -181,8 +181,21 @@ STATIC mp_obj_t extra_coverage(void) {
         mp_printf(&mp_plat_print, "%.*s\n", (int)vstr->len, vstr->buf);
 
         VSTR_FIXED(fix, 4);
-        vstr_add_str(&fix, "large");
-        mp_printf(&mp_plat_print, "%.*s\n", (int)fix.len, fix.buf);
+        nlr_buf_t nlr;
+        if (nlr_push(&nlr) == 0) {
+            vstr_add_str(&fix, "large");
+            nlr_pop();
+        } else {
+            mp_obj_print_exception(&mp_plat_print, MP_OBJ_FROM_PTR(nlr.ret_val));
+        }
+
+        fix.len = fix.alloc;
+        if (nlr_push(&nlr) == 0) {
+            vstr_null_terminated_str(&fix);
+            nlr_pop();
+        } else {
+            mp_obj_print_exception(&mp_plat_print, MP_OBJ_FROM_PTR(nlr.ret_val));
+        }
     }
 
     // repl autocomplete
diff --git a/unix/fatfs_port.c b/ports/unix/fatfs_port.c
similarity index 100%
rename from unix/fatfs_port.c
rename to ports/unix/fatfs_port.c
diff --git a/unix/fdfile.h b/ports/unix/fdfile.h
similarity index 100%
rename from unix/fdfile.h
rename to ports/unix/fdfile.h
diff --git a/unix/file.c b/ports/unix/file.c
similarity index 99%
rename from unix/file.c
rename to ports/unix/file.c
index 0d65f9ca0d..84e9180821 100644
--- a/unix/file.c
+++ b/ports/unix/file.c
@@ -31,7 +31,6 @@
 #include <sys/stat.h>
 #include <sys/types.h>
 
-#include "py/nlr.h"
 #include "py/runtime.h"
 #include "py/stream.h"
 #include "py/builtin.h"
diff --git a/unix/gccollect.c b/ports/unix/gccollect.c
similarity index 100%
rename from unix/gccollect.c
rename to ports/unix/gccollect.c
diff --git a/unix/input.c b/ports/unix/input.c
similarity index 100%
rename from unix/input.c
rename to ports/unix/input.c
diff --git a/unix/input.h b/ports/unix/input.h
similarity index 100%
rename from unix/input.h
rename to ports/unix/input.h
diff --git a/unix/main.c b/ports/unix/main.c
similarity index 99%
rename from unix/main.c
rename to ports/unix/main.c
index a7219211c7..629e36b8b3 100644
--- a/unix/main.c
+++ b/ports/unix/main.c
@@ -37,8 +37,6 @@
 #include <errno.h>
 #include <signal.h>
 
-#include "py/mpstate.h"
-#include "py/nlr.h"
 #include "py/compile.h"
 #include "py/frozenmod.h"
 #include "py/runtime.h"
diff --git a/unix/modffi.c b/ports/unix/modffi.c
similarity index 99%
rename from unix/modffi.c
rename to ports/unix/modffi.c
index f37f1ebeff..1c04c4deff 100644
--- a/unix/modffi.c
+++ b/ports/unix/modffi.c
@@ -32,7 +32,6 @@
 #include <ffi.h>
 #include <stdint.h>
 
-#include "py/nlr.h"
 #include "py/runtime.h"
 #include "py/binary.h"
 #include "py/mperrno.h"
diff --git a/unix/modjni.c b/ports/unix/modjni.c
similarity index 98%
rename from unix/modjni.c
rename to ports/unix/modjni.c
index df9cd9d67a..15b6d9cd78 100644
--- a/unix/modjni.c
+++ b/ports/unix/modjni.c
@@ -30,8 +30,6 @@
 #include <dlfcn.h>
 #include <ctype.h>
 
-#include "py/nlr.h"
-#include "py/runtime0.h"
 #include "py/runtime.h"
 #include "py/binary.h"
 
@@ -64,7 +62,7 @@ STATIC const mp_obj_type_t jmethod_type;
 
 STATIC mp_obj_t new_jobject(jobject jo);
 STATIC mp_obj_t new_jclass(jclass jc);
-STATIC mp_obj_t call_method(jobject obj, const char *name, jarray methods, bool is_constr, mp_uint_t n_args, const mp_obj_t *args);
+STATIC mp_obj_t call_method(jobject obj, const char *name, jarray methods, bool is_constr, size_t n_args, const mp_obj_t *args);
 STATIC bool py2jvalue(const char **jtypesig, mp_obj_t arg, jvalue *out);
 
 typedef struct _mp_obj_jclass_t {
@@ -293,7 +291,7 @@ STATIC mp_obj_t jobject_subscr(mp_obj_t self_in, mp_obj_t index, mp_obj_t value)
 return MP_OBJ_NULL;
 }
 
-STATIC mp_obj_t jobject_unary_op(mp_uint_t op, mp_obj_t self_in) {
+STATIC mp_obj_t jobject_unary_op(mp_unary_op_t op, mp_obj_t self_in) {
     mp_obj_jobject_t *self = self_in;
     switch (op) {
         case MP_UNARY_OP_BOOL:
@@ -463,7 +461,7 @@ STATIC mp_obj_t jvalue2py(const char *jtypesig, jobject arg) {
 }
 #endif
 
-STATIC mp_obj_t call_method(jobject obj, const char *name, jarray methods, bool is_constr, mp_uint_t n_args, const mp_obj_t *args) {
+STATIC mp_obj_t call_method(jobject obj, const char *name, jarray methods, bool is_constr, size_t n_args, const mp_obj_t *args) {
     jvalue jargs[n_args];
 //    printf("methods=%p\n", methods);
     jsize num_methods = JJ(GetArrayLength, methods);
diff --git a/unix/modmachine.c b/ports/unix/modmachine.c
similarity index 100%
rename from unix/modmachine.c
rename to ports/unix/modmachine.c
diff --git a/unix/modos.c b/ports/unix/modos.c
similarity index 99%
rename from unix/modos.c
rename to ports/unix/modos.c
index 5030fbb65b..327116a0a6 100644
--- a/unix/modos.c
+++ b/ports/unix/modos.c
@@ -34,7 +34,6 @@
 #include <dirent.h>
 #include "py/mpconfig.h"
 
-#include "py/nlr.h"
 #include "py/runtime.h"
 #include "py/objtuple.h"
 #include "py/mphal.h"
diff --git a/unix/modsocket.c b/ports/unix/modsocket.c
similarity index 99%
rename from unix/modsocket.c
rename to ports/unix/modsocket.c
index c612f870d9..7e82554c7b 100644
--- a/unix/modsocket.c
+++ b/ports/unix/modsocket.c
@@ -38,7 +38,6 @@
 #include <netdb.h>
 #include <errno.h>
 
-#include "py/nlr.h"
 #include "py/objtuple.h"
 #include "py/objstr.h"
 #include "py/runtime.h"
diff --git a/unix/modtermios.c b/ports/unix/modtermios.c
similarity index 100%
rename from unix/modtermios.c
rename to ports/unix/modtermios.c
diff --git a/unix/modtime.c b/ports/unix/modtime.c
similarity index 100%
rename from unix/modtime.c
rename to ports/unix/modtime.c
diff --git a/ports/unix/modules/upip.py b/ports/unix/modules/upip.py
new file mode 120000
index 0000000000..130eb69016
--- /dev/null
+++ b/ports/unix/modules/upip.py
@@ -0,0 +1 @@
+../../../tools/upip.py
\ No newline at end of file
diff --git a/ports/unix/modules/upip_utarfile.py b/ports/unix/modules/upip_utarfile.py
new file mode 120000
index 0000000000..d9653d6a60
--- /dev/null
+++ b/ports/unix/modules/upip_utarfile.py
@@ -0,0 +1 @@
+../../../tools/upip_utarfile.py
\ No newline at end of file
diff --git a/unix/moduos_vfs.c b/ports/unix/moduos_vfs.c
similarity index 100%
rename from unix/moduos_vfs.c
rename to ports/unix/moduos_vfs.c
diff --git a/unix/moduselect.c b/ports/unix/moduselect.c
similarity index 100%
rename from unix/moduselect.c
rename to ports/unix/moduselect.c
diff --git a/unix/mpconfigport.h b/ports/unix/mpconfigport.h
similarity index 99%
rename from unix/mpconfigport.h
rename to ports/unix/mpconfigport.h
index b557f3d448..50b979279a 100644
--- a/unix/mpconfigport.h
+++ b/ports/unix/mpconfigport.h
@@ -145,8 +145,11 @@
 // names in exception messages (may require more RAM).
 #define MICROPY_ERROR_REPORTING     (MICROPY_ERROR_REPORTING_DETAILED)
 #define MICROPY_WARNINGS            (1)
+#define MICROPY_ERROR_PRINTER       (&mp_stderr_print)
 #define MICROPY_PY_STR_BYTES_CMP_WARN (1)
 
+extern const struct _mp_print_t mp_stderr_print;
+
 // Define to 1 to use undertested inefficient GC helper implementation
 // (if more efficient arch-specific one is not available).
 #ifndef MICROPY_GCREGS_SETJMP
diff --git a/unix/mpconfigport.mk b/ports/unix/mpconfigport.mk
similarity index 100%
rename from unix/mpconfigport.mk
rename to ports/unix/mpconfigport.mk
diff --git a/unix/mpconfigport_coverage.h b/ports/unix/mpconfigport_coverage.h
similarity index 97%
rename from unix/mpconfigport_coverage.h
rename to ports/unix/mpconfigport_coverage.h
index a9e0a38fa0..367b4853af 100644
--- a/unix/mpconfigport_coverage.h
+++ b/ports/unix/mpconfigport_coverage.h
@@ -35,6 +35,7 @@
 #define MICROPY_FLOAT_HIGH_QUALITY_HASH (1)
 #define MICROPY_ENABLE_SCHEDULER       (1)
 #define MICROPY_PY_DELATTR_SETATTR     (1)
+#define MICROPY_PY_REVERSE_SPECIAL_METHODS (1)
 #define MICROPY_PY_BUILTINS_HELP       (1)
 #define MICROPY_PY_BUILTINS_HELP_MODULES (1)
 #define MICROPY_PY_SYS_GETSIZEOF       (1)
diff --git a/unix/mpconfigport_fast.h b/ports/unix/mpconfigport_fast.h
similarity index 100%
rename from unix/mpconfigport_fast.h
rename to ports/unix/mpconfigport_fast.h
diff --git a/unix/mpconfigport_freedos.h b/ports/unix/mpconfigport_freedos.h
similarity index 100%
rename from unix/mpconfigport_freedos.h
rename to ports/unix/mpconfigport_freedos.h
diff --git a/unix/mpconfigport_minimal.h b/ports/unix/mpconfigport_minimal.h
similarity index 100%
rename from unix/mpconfigport_minimal.h
rename to ports/unix/mpconfigport_minimal.h
diff --git a/unix/mpconfigport_nanbox.h b/ports/unix/mpconfigport_nanbox.h
similarity index 100%
rename from unix/mpconfigport_nanbox.h
rename to ports/unix/mpconfigport_nanbox.h
diff --git a/unix/mphalport.h b/ports/unix/mphalport.h
similarity index 100%
rename from unix/mphalport.h
rename to ports/unix/mphalport.h
diff --git a/unix/mpthreadport.c b/ports/unix/mpthreadport.c
similarity index 99%
rename from unix/mpthreadport.c
rename to ports/unix/mpthreadport.c
index 09f5702e38..8c636a4457 100644
--- a/unix/mpthreadport.c
+++ b/ports/unix/mpthreadport.c
@@ -28,7 +28,6 @@
 #include <stdlib.h>
 #include <errno.h>
 
-#include "py/mpstate.h"
 #include "py/runtime.h"
 #include "py/mpthread.h"
 #include "py/gc.h"
diff --git a/unix/mpthreadport.h b/ports/unix/mpthreadport.h
similarity index 100%
rename from unix/mpthreadport.h
rename to ports/unix/mpthreadport.h
diff --git a/unix/qstrdefsport.h b/ports/unix/qstrdefsport.h
similarity index 100%
rename from unix/qstrdefsport.h
rename to ports/unix/qstrdefsport.h
diff --git a/unix/unix_mphal.c b/ports/unix/unix_mphal.c
similarity index 99%
rename from unix/unix_mphal.c
rename to ports/unix/unix_mphal.c
index 02cdbea11f..2b273d8341 100644
--- a/unix/unix_mphal.c
+++ b/ports/unix/unix_mphal.c
@@ -29,7 +29,6 @@
 #include <string.h>
 #include <sys/time.h>
 
-#include "py/mpstate.h"
 #include "py/mphal.h"
 #include "py/runtime.h"
 #include "extmod/misc.h"
diff --git a/windows/.appveyor.yml b/ports/windows/.appveyor.yml
similarity index 90%
rename from windows/.appveyor.yml
rename to ports/windows/.appveyor.yml
index 84060a1162..a82cf5adc9 100644
--- a/windows/.appveyor.yml
+++ b/ports/windows/.appveyor.yml
@@ -15,7 +15,7 @@ platform:
 - x64
 
 build:
-  project: windows/micropython.vcxproj
+  project: ports/windows/micropython.vcxproj
   verbosity: normal
 
 test_script:
diff --git a/windows/.gitignore b/ports/windows/.gitignore
similarity index 100%
rename from windows/.gitignore
rename to ports/windows/.gitignore
diff --git a/windows/Makefile b/ports/windows/Makefile
similarity index 86%
rename from windows/Makefile
rename to ports/windows/Makefile
index a39d348266..b6433300fe 100644
--- a/windows/Makefile
+++ b/ports/windows/Makefile
@@ -1,4 +1,4 @@
-include ../py/mkenv.mk
+include ../../py/mkenv.mk
 -include mpconfigport.mk
 
 # define main target
@@ -28,13 +28,13 @@ endif
 
 # source files
 SRC_C = \
-	unix/main.c \
-	unix/file.c \
-	unix/input.c \
-	unix/modos.c \
-	unix/modmachine.c \
-	unix/modtime.c \
-	unix/gccollect.c \
+	ports/unix/main.c \
+	ports/unix/file.c \
+	ports/unix/input.c \
+	ports/unix/modos.c \
+	ports/unix/modmachine.c \
+	ports/unix/modtime.c \
+	ports/unix/gccollect.c \
 	windows_mphal.c \
 	realpath.c \
 	init.c \
diff --git a/windows/README.md b/ports/windows/README.md
similarity index 96%
rename from windows/README.md
rename to ports/windows/README.md
index 6d32499032..f1bd405513 100644
--- a/windows/README.md
+++ b/ports/windows/README.md
@@ -50,8 +50,8 @@ __Stack usage__
 The msvc compiler is quite stack-hungry which might result in a "maximum recursion depth exceeded"
 RuntimeError for code with lots of nested function calls.
 There are several ways to deal with this:
-- increase the threshold used for detection by altering the argument to `mp_stack_set_limit` in `unix/main.c`
-- disable detection all together by setting `MICROPY_STACK_CHECK` to "0" in `windows/mpconfigport.h`
+- increase the threshold used for detection by altering the argument to `mp_stack_set_limit` in `ports/unix/main.c`
+- disable detection all together by setting `MICROPY_STACK_CHECK` to "0" in `ports/windows/mpconfigport.h`
 - disable the /GL compiler flag by setting `WholeProgramOptimization` to "false"
 
 See [issue 2927](https://github.com/micropython/micropython/issues/2927) for more information.
diff --git a/windows/fmode.c b/ports/windows/fmode.c
similarity index 100%
rename from windows/fmode.c
rename to ports/windows/fmode.c
diff --git a/windows/fmode.h b/ports/windows/fmode.h
similarity index 100%
rename from windows/fmode.h
rename to ports/windows/fmode.h
diff --git a/windows/init.c b/ports/windows/init.c
similarity index 100%
rename from windows/init.c
rename to ports/windows/init.c
diff --git a/windows/init.h b/ports/windows/init.h
similarity index 100%
rename from windows/init.h
rename to ports/windows/init.h
diff --git a/windows/micropython.vcxproj b/ports/windows/micropython.vcxproj
similarity index 100%
rename from windows/micropython.vcxproj
rename to ports/windows/micropython.vcxproj
diff --git a/windows/mpconfigport.h b/ports/windows/mpconfigport.h
similarity index 100%
rename from windows/mpconfigport.h
rename to ports/windows/mpconfigport.h
diff --git a/windows/mpconfigport.mk b/ports/windows/mpconfigport.mk
similarity index 100%
rename from windows/mpconfigport.mk
rename to ports/windows/mpconfigport.mk
diff --git a/windows/msvc/common.props b/ports/windows/msvc/common.props
similarity index 100%
rename from windows/msvc/common.props
rename to ports/windows/msvc/common.props
diff --git a/windows/msvc/debug.props b/ports/windows/msvc/debug.props
similarity index 100%
rename from windows/msvc/debug.props
rename to ports/windows/msvc/debug.props
diff --git a/windows/msvc/dirent.c b/ports/windows/msvc/dirent.c
similarity index 100%
rename from windows/msvc/dirent.c
rename to ports/windows/msvc/dirent.c
diff --git a/windows/msvc/dirent.h b/ports/windows/msvc/dirent.h
similarity index 100%
rename from windows/msvc/dirent.h
rename to ports/windows/msvc/dirent.h
diff --git a/windows/msvc/genhdr.targets b/ports/windows/msvc/genhdr.targets
similarity index 99%
rename from windows/msvc/genhdr.targets
rename to ports/windows/msvc/genhdr.targets
index cac3e3ddc4..ee030c9063 100644
--- a/windows/msvc/genhdr.targets
+++ b/ports/windows/msvc/genhdr.targets
@@ -10,7 +10,7 @@
   <PropertyGroup>
     <DestDir>$(PyBuildDir)genhdr\</DestDir>
     <PySrcDir>$(PyBaseDir)py\</PySrcDir>
-    <QstrDefs>$(PyBaseDir)unix\qstrdefsport.h</QstrDefs>
+    <QstrDefs>$(PyBaseDir)ports\unix\qstrdefsport.h</QstrDefs>
     <PyQstrDefs>$(PySrcDir)qstrdefs.h</PyQstrDefs>
     <QstrDefsCollected>$(DestDir)qstrdefscollected.h</QstrDefsCollected>
     <QstrGen>$(DestDir)qstrdefs.generated.h</QstrGen>
diff --git a/windows/msvc/gettimeofday.c b/ports/windows/msvc/gettimeofday.c
similarity index 100%
rename from windows/msvc/gettimeofday.c
rename to ports/windows/msvc/gettimeofday.c
diff --git a/windows/msvc/paths.props b/ports/windows/msvc/paths.props
similarity index 74%
rename from windows/msvc/paths.props
rename to ports/windows/msvc/paths.props
index 7166982434..db3af4c0fa 100644
--- a/windows/msvc/paths.props
+++ b/ports/windows/msvc/paths.props
@@ -3,28 +3,28 @@
   <PropertyGroup>
     <PyPathsIncluded>True</PyPathsIncluded>
 
-    <!-- The properties below specify the output directory structure.
+    <!-- The properties below specify the directory structure.
          This defaults to, for example for Configuration = Debug and Platform = x64:
 
          micropython [PyBaseDir]
           |- ...
-          |- windows [PyWinDir]
-              |- ...
-              |- micropython.exe
-              |- build [PyBuildDir]
-                  |- Debugx64 [PyOutDir]
-                  |   |- ...
-                  |   |- micropython.exe
-                  |   |- micropython.map
-                  |   |- obj [PyIntDir]
-                  |- genhdr
+          |- ports/windows [PyWinDir]
+                    |- ...
+                    |- micropython.exe
+                    |- build [PyBuildDir]
+                        |- Debugx64 [PyOutDir]
+                        |   |- ...
+                        |   |- micropython.exe
+                        |   |- micropython.map
+                        |   |- obj [PyIntDir]
+                        |- genhdr
 
          Note that the micropython executable will be copied from PyOutDir
          to PyWinDir after each build. -->
 
     <!-- Start from project root -->
-    <PyBaseDir>$([System.IO.Path]::GetFullPath(`$(MSBuildThisFileDirectory)..\..`))\</PyBaseDir>
-    <PyWinDir>$(PyBaseDir)windows\</PyWinDir>
+    <PyBaseDir>$([System.IO.Path]::GetFullPath(`$(MSBuildThisFileDirectory)..\..\..`))\</PyBaseDir>
+    <PyWinDir>$(PyBaseDir)ports\windows\</PyWinDir>
     <PyBuildDir Condition="'$(PyBuildDir)' == ''">$(PyWinDir)build\</PyBuildDir>
 
     <!-- All include directories needed for uPy -->
diff --git a/windows/msvc/release.props b/ports/windows/msvc/release.props
similarity index 100%
rename from windows/msvc/release.props
rename to ports/windows/msvc/release.props
diff --git a/windows/msvc/sources.props b/ports/windows/msvc/sources.props
similarity index 67%
rename from windows/msvc/sources.props
rename to ports/windows/msvc/sources.props
index a97686cdc4..b85295ebc0 100644
--- a/windows/msvc/sources.props
+++ b/ports/windows/msvc/sources.props
@@ -3,16 +3,16 @@
   <Import Project="paths.props" Condition="'$(PyPathsIncluded)' != 'True'"/>
   <ItemGroup>
     <ClCompile Include="$(PyBaseDir)py\*.c" />
-    <ClCompile Include="$(PyBaseDir)windows\*.c" />
-    <ClCompile Include="$(PyBaseDir)windows\msvc\*.c" />
+    <ClCompile Include="$(PyBaseDir)ports\windows\*.c" />
+    <ClCompile Include="$(PyBaseDir)ports\windows\msvc\*.c" />
     <ClCompile Include="$(PyBaseDir)lib\mp-readline\*.c" />
-    <ClCompile Include="$(PyBaseDir)unix\file.c"/>
-    <ClCompile Include="$(PyBaseDir)unix\gccollect.c"/>
-    <ClCompile Include="$(PyBaseDir)unix\input.c"/>
-    <ClCompile Include="$(PyBaseDir)unix\main.c"/>
-    <ClCompile Include="$(PyBaseDir)unix\modos.c"/>
-    <ClCompile Include="$(PyBaseDir)unix\modtime.c"/>
-    <ClCompile Include="$(PyBaseDir)unix\modmachine.c" />
+    <ClCompile Include="$(PyBaseDir)ports\unix\file.c"/>
+    <ClCompile Include="$(PyBaseDir)ports\unix\gccollect.c"/>
+    <ClCompile Include="$(PyBaseDir)ports\unix\input.c"/>
+    <ClCompile Include="$(PyBaseDir)ports\unix\main.c"/>
+    <ClCompile Include="$(PyBaseDir)ports\unix\modos.c"/>
+    <ClCompile Include="$(PyBaseDir)ports\unix\modtime.c"/>
+    <ClCompile Include="$(PyBaseDir)ports\unix\modmachine.c" />
     <ClCompile Include="$(PyBaseDir)extmod\machine_mem.c" />
     <ClCompile Include="$(PyBaseDir)extmod\machine_pinbase.c" />
     <ClCompile Include="$(PyBaseDir)extmod\machine_pulse.c" />
@@ -31,7 +31,7 @@
   </ItemGroup>
   <ItemGroup>
     <ClInclude Include="$(PyBaseDir)py\*.h" />
-    <ClInclude Include="$(PyBaseDir)windows\*.h" />
-    <ClInclude Include="$(PyBaseDir)windows\msvc\*.h" />
+    <ClInclude Include="$(PyBaseDir)ports\windows\*.h" />
+    <ClInclude Include="$(PyBaseDir)ports\windows\msvc\*.h" />
   </ItemGroup>
 </Project>
diff --git a/windows/msvc/sys/time.h b/ports/windows/msvc/sys/time.h
similarity index 100%
rename from windows/msvc/sys/time.h
rename to ports/windows/msvc/sys/time.h
diff --git a/windows/msvc/unistd.h b/ports/windows/msvc/unistd.h
similarity index 100%
rename from windows/msvc/unistd.h
rename to ports/windows/msvc/unistd.h
diff --git a/windows/realpath.c b/ports/windows/realpath.c
similarity index 100%
rename from windows/realpath.c
rename to ports/windows/realpath.c
diff --git a/windows/realpath.h b/ports/windows/realpath.h
similarity index 100%
rename from windows/realpath.h
rename to ports/windows/realpath.h
diff --git a/windows/sleep.c b/ports/windows/sleep.c
similarity index 100%
rename from windows/sleep.c
rename to ports/windows/sleep.c
diff --git a/windows/sleep.h b/ports/windows/sleep.h
similarity index 100%
rename from windows/sleep.h
rename to ports/windows/sleep.h
diff --git a/windows/windows_mphal.c b/ports/windows/windows_mphal.c
similarity index 100%
rename from windows/windows_mphal.c
rename to ports/windows/windows_mphal.c
diff --git a/windows/windows_mphal.h b/ports/windows/windows_mphal.h
similarity index 97%
rename from windows/windows_mphal.h
rename to ports/windows/windows_mphal.h
index 5a93d4e184..2b7aab44a0 100644
--- a/windows/windows_mphal.h
+++ b/ports/windows/windows_mphal.h
@@ -25,7 +25,7 @@
  */
 
 #include "sleep.h"
-#include "unix/mphalport.h"
+#include "ports/unix/mphalport.h"
 
 #define MICROPY_HAL_HAS_VT100 (0)
 
diff --git a/zephyr/.gitignore b/ports/zephyr/.gitignore
similarity index 100%
rename from zephyr/.gitignore
rename to ports/zephyr/.gitignore
diff --git a/zephyr/Kbuild b/ports/zephyr/Kbuild
similarity index 100%
rename from zephyr/Kbuild
rename to ports/zephyr/Kbuild
diff --git a/zephyr/Makefile b/ports/zephyr/Makefile
similarity index 97%
rename from zephyr/Makefile
rename to ports/zephyr/Makefile
index 5840cc47ec..2e6cb41b98 100644
--- a/zephyr/Makefile
+++ b/ports/zephyr/Makefile
@@ -26,7 +26,7 @@ ifneq ($(MAKECMDGOALS), clean)
 include $(Z_EXPORTS)
 endif
 
-include ../py/mkenv.mk
+include ../../py/mkenv.mk
 include $(TOP)/py/py.mk
 
 INC += -I.
@@ -102,4 +102,4 @@ prj_$(BOARD)_merged.conf: prj_base.conf prj_$(BOARD).conf
 	$(PYTHON) makeprj.py prj_base.conf prj_$(BOARD).conf $@
 
 test:
-	cd $(TOP)/tests && ./run-tests --target minimal --device "execpty:make -C ../zephyr run BOARD=$(BOARD) QEMU_PTY=1"
+	cd $(TOP)/tests && ./run-tests --target minimal --device "execpty:make -C ../ports/zephyr run BOARD=$(BOARD) QEMU_PTY=1"
diff --git a/zephyr/Makefile.zephyr b/ports/zephyr/Makefile.zephyr
similarity index 100%
rename from zephyr/Makefile.zephyr
rename to ports/zephyr/Makefile.zephyr
diff --git a/zephyr/README.md b/ports/zephyr/README.md
similarity index 100%
rename from zephyr/README.md
rename to ports/zephyr/README.md
diff --git a/zephyr/help.c b/ports/zephyr/help.c
similarity index 98%
rename from zephyr/help.c
rename to ports/zephyr/help.c
index 0c7f279406..becc203f6f 100644
--- a/zephyr/help.c
+++ b/ports/zephyr/help.c
@@ -26,7 +26,7 @@
 
 #include "py/builtin.h"
 
-const char *zephyr_help_text =
+const char zephyr_help_text[] =
 "Welcome to MicroPython!\n"
 "\n"
 "Control commands:\n"
diff --git a/zephyr/machine_pin.c b/ports/zephyr/machine_pin.c
similarity index 98%
rename from zephyr/machine_pin.c
rename to ports/zephyr/machine_pin.c
index 0e2efcd950..4dcd956cf8 100644
--- a/zephyr/machine_pin.c
+++ b/ports/zephyr/machine_pin.c
@@ -32,7 +32,6 @@
 #include <zephyr.h>
 #include <gpio.h>
 
-#include "py/nlr.h"
 #include "py/runtime.h"
 #include "py/gc.h"
 #include "py/mphal.h"
@@ -46,7 +45,7 @@ STATIC void machine_pin_print(const mp_print_t *print, mp_obj_t self_in, mp_prin
 }
 
 // pin.init(mode, pull=None, *, value)
-STATIC mp_obj_t machine_pin_obj_init_helper(machine_pin_obj_t *self, mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+STATIC mp_obj_t machine_pin_obj_init_helper(machine_pin_obj_t *self, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
     enum { ARG_mode, ARG_pull, ARG_value };
     static const mp_arg_t allowed_args[] = {
         { MP_QSTR_mode, MP_ARG_REQUIRED | MP_ARG_INT },
diff --git a/zephyr/main.c b/ports/zephyr/main.c
similarity index 99%
rename from zephyr/main.c
rename to ports/zephyr/main.c
index a4301629f4..7255d981f1 100644
--- a/zephyr/main.c
+++ b/ports/zephyr/main.c
@@ -33,7 +33,6 @@
 #include <net/net_context.h>
 #endif
 
-#include "py/nlr.h"
 #include "py/compile.h"
 #include "py/runtime.h"
 #include "py/repl.h"
diff --git a/zephyr/make-minimal b/ports/zephyr/make-minimal
similarity index 100%
rename from zephyr/make-minimal
rename to ports/zephyr/make-minimal
diff --git a/zephyr/makeprj.py b/ports/zephyr/makeprj.py
similarity index 100%
rename from zephyr/makeprj.py
rename to ports/zephyr/makeprj.py
diff --git a/zephyr/modmachine.c b/ports/zephyr/modmachine.c
similarity index 100%
rename from zephyr/modmachine.c
rename to ports/zephyr/modmachine.c
diff --git a/zephyr/modmachine.h b/ports/zephyr/modmachine.h
similarity index 100%
rename from zephyr/modmachine.h
rename to ports/zephyr/modmachine.h
diff --git a/zephyr/modusocket.c b/ports/zephyr/modusocket.c
similarity index 100%
rename from zephyr/modusocket.c
rename to ports/zephyr/modusocket.c
diff --git a/zephyr/modutime.c b/ports/zephyr/modutime.c
similarity index 100%
rename from zephyr/modutime.c
rename to ports/zephyr/modutime.c
diff --git a/zephyr/modzephyr.c b/ports/zephyr/modzephyr.c
similarity index 100%
rename from zephyr/modzephyr.c
rename to ports/zephyr/modzephyr.c
diff --git a/zephyr/mpconfigport.h b/ports/zephyr/mpconfigport.h
similarity index 100%
rename from zephyr/mpconfigport.h
rename to ports/zephyr/mpconfigport.h
diff --git a/zephyr/mpconfigport_minimal.h b/ports/zephyr/mpconfigport_minimal.h
similarity index 100%
rename from zephyr/mpconfigport_minimal.h
rename to ports/zephyr/mpconfigport_minimal.h
diff --git a/zephyr/mphalport.h b/ports/zephyr/mphalport.h
similarity index 100%
rename from zephyr/mphalport.h
rename to ports/zephyr/mphalport.h
diff --git a/zephyr/prj_96b_carbon.conf b/ports/zephyr/prj_96b_carbon.conf
similarity index 100%
rename from zephyr/prj_96b_carbon.conf
rename to ports/zephyr/prj_96b_carbon.conf
diff --git a/zephyr/prj_base.conf b/ports/zephyr/prj_base.conf
similarity index 100%
rename from zephyr/prj_base.conf
rename to ports/zephyr/prj_base.conf
diff --git a/zephyr/prj_frdm_k64f.conf b/ports/zephyr/prj_frdm_k64f.conf
similarity index 100%
rename from zephyr/prj_frdm_k64f.conf
rename to ports/zephyr/prj_frdm_k64f.conf
diff --git a/zephyr/prj_minimal.conf b/ports/zephyr/prj_minimal.conf
similarity index 100%
rename from zephyr/prj_minimal.conf
rename to ports/zephyr/prj_minimal.conf
diff --git a/zephyr/prj_qemu_cortex_m3.conf b/ports/zephyr/prj_qemu_cortex_m3.conf
similarity index 100%
rename from zephyr/prj_qemu_cortex_m3.conf
rename to ports/zephyr/prj_qemu_cortex_m3.conf
diff --git a/zephyr/prj_qemu_x86.conf b/ports/zephyr/prj_qemu_x86.conf
similarity index 100%
rename from zephyr/prj_qemu_x86.conf
rename to ports/zephyr/prj_qemu_x86.conf
diff --git a/zephyr/src/Makefile b/ports/zephyr/src/Makefile
similarity index 100%
rename from zephyr/src/Makefile
rename to ports/zephyr/src/Makefile
diff --git a/zephyr/src/zephyr_getchar.c b/ports/zephyr/src/zephyr_getchar.c
similarity index 100%
rename from zephyr/src/zephyr_getchar.c
rename to ports/zephyr/src/zephyr_getchar.c
diff --git a/zephyr/src/zephyr_getchar.h b/ports/zephyr/src/zephyr_getchar.h
similarity index 100%
rename from zephyr/src/zephyr_getchar.h
rename to ports/zephyr/src/zephyr_getchar.h
diff --git a/zephyr/src/zephyr_start.c b/ports/zephyr/src/zephyr_start.c
similarity index 100%
rename from zephyr/src/zephyr_start.c
rename to ports/zephyr/src/zephyr_start.c
diff --git a/zephyr/uart_core.c b/ports/zephyr/uart_core.c
similarity index 100%
rename from zephyr/uart_core.c
rename to ports/zephyr/uart_core.c
diff --git a/zephyr/z_config.mk b/ports/zephyr/z_config.mk
similarity index 100%
rename from zephyr/z_config.mk
rename to ports/zephyr/z_config.mk
diff --git a/py/argcheck.c b/py/argcheck.c
index a5ddc2e340..46be126ac8 100644
--- a/py/argcheck.c
+++ b/py/argcheck.c
@@ -27,7 +27,6 @@
 #include <stdlib.h>
 #include <assert.h>
 
-#include "py/nlr.h"
 #include "py/runtime.h"
 
 void mp_arg_check_num(size_t n_args, size_t n_kw, size_t n_args_min, size_t n_args_max, bool takes_kw) {
diff --git a/py/bc.c b/py/bc.c
index e1cb6a580d..1f68192952 100644
--- a/py/bc.c
+++ b/py/bc.c
@@ -29,9 +29,7 @@
 #include <string.h>
 #include <assert.h>
 
-#include "py/nlr.h"
-#include "py/objfun.h"
-#include "py/runtime0.h"
+#include "py/runtime.h"
 #include "py/bc0.h"
 #include "py/bc.h"
 
diff --git a/py/bc.h b/py/bc.h
index 69e213e422..ebfdeaac1d 100644
--- a/py/bc.h
+++ b/py/bc.h
@@ -27,7 +27,6 @@
 #define MICROPY_INCLUDED_PY_BC_H
 
 #include "py/runtime.h"
-#include "py/obj.h"
 #include "py/objfun.h"
 
 // bytecode layout:
diff --git a/py/bc0.h b/py/bc0.h
index f671c5b5a7..38e23c0fde 100644
--- a/py/bc0.h
+++ b/py/bc0.h
@@ -113,7 +113,7 @@
 #define MP_BC_LOAD_CONST_SMALL_INT_MULTI (0x70) // + N(64)
 #define MP_BC_LOAD_FAST_MULTI            (0xb0) // + N(16)
 #define MP_BC_STORE_FAST_MULTI           (0xc0) // + N(16)
-#define MP_BC_UNARY_OP_MULTI             (0xd0) // + op(7)
+#define MP_BC_UNARY_OP_MULTI             (0xd0) // + op(<MP_UNARY_OP_NON_BYTECODE)
 #define MP_BC_BINARY_OP_MULTI            (0xd7) // + op(36)
 
 #endif // MICROPY_INCLUDED_PY_BC0_H
diff --git a/py/builtin.h b/py/builtin.h
index a637b6e222..84b99a8a4f 100644
--- a/py/builtin.h
+++ b/py/builtin.h
@@ -118,6 +118,6 @@ extern const mp_obj_module_t mp_module_webrepl;
 extern const mp_obj_module_t mp_module_framebuf;
 extern const mp_obj_module_t mp_module_btree;
 
-extern const char *MICROPY_PY_BUILTINS_HELP_TEXT;
+extern const char MICROPY_PY_BUILTINS_HELP_TEXT[];
 
 #endif // MICROPY_INCLUDED_PY_BUILTIN_H
diff --git a/py/builtinevex.c b/py/builtinevex.c
index ba8048f702..846603f46b 100644
--- a/py/builtinevex.c
+++ b/py/builtinevex.c
@@ -26,7 +26,6 @@
 
 #include <stdint.h>
 
-#include "py/nlr.h"
 #include "py/objfun.h"
 #include "py/compile.h"
 #include "py/runtime.h"
diff --git a/py/builtinhelp.c b/py/builtinhelp.c
index 9903f26906..1cea8caac2 100644
--- a/py/builtinhelp.c
+++ b/py/builtinhelp.c
@@ -33,7 +33,7 @@
 
 #if MICROPY_PY_BUILTINS_HELP
 
-const char *mp_help_default_text =
+const char mp_help_default_text[] =
 "Welcome to MicroPython!\n"
 "\n"
 "For online docs please visit http://docs.micropython.org/\n"
@@ -145,20 +145,19 @@ STATIC void mp_help_print_obj(const mp_obj_t obj) {
     }
     #endif
 
+    mp_obj_type_t *type = mp_obj_get_type(obj);
+
     // try to print something sensible about the given object
     mp_print_str(MP_PYTHON_PRINTER, "object ");
     mp_obj_print(obj, PRINT_STR);
-    mp_printf(MP_PYTHON_PRINTER, " is of type %s\n", mp_obj_get_type_str(obj));
+    mp_printf(MP_PYTHON_PRINTER, " is of type %q\n", type->name);
 
     mp_map_t *map = NULL;
-    if (MP_OBJ_IS_TYPE(obj, &mp_type_module)) {
+    if (type == &mp_type_module) {
         map = mp_obj_dict_get_map(mp_obj_module_get_globals(obj));
     } else {
-        mp_obj_type_t *type;
-        if (MP_OBJ_IS_TYPE(obj, &mp_type_type)) {
-            type = obj;
-        } else {
-            type = mp_obj_get_type(obj);
+        if (type == &mp_type_type) {
+            type = MP_OBJ_TO_PTR(obj);
         }
         if (type->locals_dict != MP_OBJ_NULL && MP_OBJ_IS_TYPE(type->locals_dict, &mp_type_dict)) {
             map = mp_obj_dict_get_map(type->locals_dict);
diff --git a/py/builtinimport.c b/py/builtinimport.c
index 5894309ffe..b76ea00bd8 100644
--- a/py/builtinimport.c
+++ b/py/builtinimport.c
@@ -29,7 +29,6 @@
 #include <string.h>
 #include <assert.h>
 
-#include "py/nlr.h"
 #include "py/compile.h"
 #include "py/objmodule.h"
 #include "py/persistentcode.h"
diff --git a/py/emit.h b/py/emit.h
index 2b2c904f60..270a40633c 100644
--- a/py/emit.h
+++ b/py/emit.h
@@ -28,7 +28,6 @@
 
 #include "py/lexer.h"
 #include "py/scope.h"
-#include "py/runtime0.h"
 
 /* Notes on passes:
  * We don't know exactly the opcodes in pass 1 because they depend on the
diff --git a/py/emitbc.c b/py/emitbc.c
index 6770209257..3f4dfc1786 100644
--- a/py/emitbc.c
+++ b/py/emitbc.c
@@ -550,7 +550,7 @@ void mp_emit_bc_load_const_obj(emit_t *emit, mp_obj_t obj) {
 void mp_emit_bc_load_null(emit_t *emit) {
     emit_bc_pre(emit, 1);
     emit_write_bytecode_byte(emit, MP_BC_LOAD_NULL);
-};
+}
 
 void mp_emit_bc_load_fast(emit_t *emit, qstr qst, mp_uint_t local_num) {
     (void)qst;
diff --git a/py/emitnative.c b/py/emitnative.c
index 4608cd1e0c..b2c9a73668 100644
--- a/py/emitnative.c
+++ b/py/emitnative.c
@@ -46,7 +46,6 @@
 #include <string.h>
 #include <assert.h>
 
-#include "py/nlr.h"
 #include "py/emit.h"
 #include "py/bc.h"
 
diff --git a/py/gc.c b/py/gc.c
index 3f88c626ef..16b6e01927 100644
--- a/py/gc.c
+++ b/py/gc.c
@@ -28,9 +28,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "py/mpstate.h"
 #include "py/gc.h"
-#include "py/obj.h"
 #include "py/runtime.h"
 
 #if MICROPY_ENABLE_GC
diff --git a/py/lexer.c b/py/lexer.c
index 074d6f3561..6017d69d6d 100644
--- a/py/lexer.c
+++ b/py/lexer.c
@@ -28,7 +28,6 @@
 #include <string.h>
 #include <assert.h>
 
-#include "py/mpstate.h"
 #include "py/reader.h"
 #include "py/lexer.h"
 #include "py/runtime.h"
diff --git a/py/malloc.c b/py/malloc.c
index af4ccf2e81..ea1d4c4b9e 100644
--- a/py/malloc.c
+++ b/py/malloc.c
@@ -74,7 +74,7 @@ STATIC void *realloc_ext(void *ptr, size_t n_bytes, bool allow_move) {
 void *m_malloc(size_t num_bytes) {
     void *ptr = malloc(num_bytes);
     if (ptr == NULL && num_bytes != 0) {
-        return m_malloc_fail(num_bytes);
+        m_malloc_fail(num_bytes);
     }
 #if MICROPY_MEM_STATS
     MP_STATE_MEM(total_bytes_allocated) += num_bytes;
@@ -100,7 +100,7 @@ void *m_malloc_maybe(size_t num_bytes) {
 void *m_malloc_with_finaliser(size_t num_bytes) {
     void *ptr = malloc_with_finaliser(num_bytes);
     if (ptr == NULL && num_bytes != 0) {
-        return m_malloc_fail(num_bytes);
+        m_malloc_fail(num_bytes);
     }
 #if MICROPY_MEM_STATS
     MP_STATE_MEM(total_bytes_allocated) += num_bytes;
@@ -115,7 +115,7 @@ void *m_malloc_with_finaliser(size_t num_bytes) {
 void *m_malloc0(size_t num_bytes) {
     void *ptr = m_malloc(num_bytes);
     if (ptr == NULL && num_bytes != 0) {
-        return m_malloc_fail(num_bytes);
+        m_malloc_fail(num_bytes);
     }
     // If this config is set then the GC clears all memory, so we don't need to.
     #if !MICROPY_GC_CONSERVATIVE_CLEAR
@@ -131,7 +131,7 @@ void *m_realloc(void *ptr, size_t new_num_bytes) {
 #endif
     void *new_ptr = realloc(ptr, new_num_bytes);
     if (new_ptr == NULL && new_num_bytes != 0) {
-        return m_malloc_fail(new_num_bytes);
+        m_malloc_fail(new_num_bytes);
     }
 #if MICROPY_MEM_STATS
     // At first thought, "Total bytes allocated" should only grow,
diff --git a/py/map.c b/py/map.c
index 7f3c900590..4f76b9b16c 100644
--- a/py/map.c
+++ b/py/map.c
@@ -31,7 +31,6 @@
 
 #include "py/mpconfig.h"
 #include "py/misc.h"
-#include "py/runtime0.h"
 #include "py/runtime.h"
 
 // Fixed empty map. Useful when need to call kw-receiving functions
@@ -93,12 +92,6 @@ void mp_map_init_fixed_table(mp_map_t *map, size_t n, const mp_obj_t *table) {
     map->table = (mp_map_elem_t*)table;
 }
 
-mp_map_t *mp_map_new(size_t n) {
-    mp_map_t *map = m_new(mp_map_t, 1);
-    mp_map_init(map, n);
-    return map;
-}
-
 // Differentiate from mp_map_clear() - semantics is different
 void mp_map_deinit(mp_map_t *map) {
     if (!map->is_fixed) {
@@ -107,11 +100,6 @@ void mp_map_deinit(mp_map_t *map) {
     map->used = map->alloc = 0;
 }
 
-void mp_map_free(mp_map_t *map) {
-    mp_map_deinit(map);
-    m_del_obj(mp_map_t, map);
-}
-
 void mp_map_clear(mp_map_t *map) {
     if (!map->is_fixed) {
         m_del(mp_map_elem_t, map->table, map->alloc);
@@ -148,11 +136,8 @@ STATIC void mp_map_rehash(mp_map_t *map) {
 // MP_MAP_LOOKUP_REMOVE_IF_FOUND behaviour:
 //  - returns NULL if not found, else the slot if was found in with key null and value non-null
 mp_map_elem_t *mp_map_lookup(mp_map_t *map, mp_obj_t index, mp_map_lookup_kind_t lookup_kind) {
-
-    if (map->is_fixed && lookup_kind != MP_MAP_LOOKUP) {
-        // can't add/remove from a fixed array
-        return NULL;
-    }
+    // If the map is a fixed array then we must only be called for a lookup
+    assert(!map->is_fixed || lookup_kind == MP_MAP_LOOKUP);
 
     // Work out if we can compare just pointers
     bool compare_only_ptrs = map->all_keys_are_qstrs;
diff --git a/py/misc.h b/py/misc.h
index 4cd58b960d..995e4549cd 100644
--- a/py/misc.h
+++ b/py/misc.h
@@ -94,7 +94,7 @@ void *m_realloc(void *ptr, size_t new_num_bytes);
 void *m_realloc_maybe(void *ptr, size_t new_num_bytes, bool allow_move);
 void m_free(void *ptr);
 #endif
-NORETURN void *m_malloc_fail(size_t num_bytes);
+NORETURN void m_malloc_fail(size_t num_bytes);
 
 #if MICROPY_MEM_STATS
 size_t m_get_total_bytes_allocated(void);
diff --git a/py/mkenv.mk b/py/mkenv.mk
index 5a118854aa..507fa6eabf 100644
--- a/py/mkenv.mk
+++ b/py/mkenv.mk
@@ -68,7 +68,13 @@ LD += -m32
 endif
 
 MAKE_FROZEN = $(TOP)/tools/make-frozen.py
+# allow mpy-cross (for WSL) and mpy-cross.exe (for cygwin) to coexist
+ifeq ($(OS),Windows_NT)
+MPY_CROSS = $(TOP)/mpy-cross/mpy-cross.exe
+PROG_EXT = .exe
+else
 MPY_CROSS = $(TOP)/mpy-cross/mpy-cross
+endif
 MPY_TOOL = $(TOP)/tools/mpy-tool.py
 
 all:
diff --git a/py/mkrules.mk b/py/mkrules.mk
index 656ffd03cb..e26b949392 100644
--- a/py/mkrules.mk
+++ b/py/mkrules.mk
@@ -110,7 +110,7 @@ endif
 ifneq ($(FROZEN_MPY_DIRS),)
 # to build the MicroPython cross compiler
 # Currently not used, because the wrong mpy-cross may be left over from a previous build. Build by hand to make sure.
-$(MPY_CROSS): $(TOP)/py/*.[ch] $(TOP)/mpy-cross/*.[ch] $(TOP)/windows/fmode.c
+$(MPY_CROSS): $(TOP)/py/*.[ch] $(TOP)/mpy-cross/*.[ch] $(TOP)/ports/windows/fmode.c
 	$(Q)$(MAKE) -C $(TOP)/mpy-cross
 
 # Copy all the modules and single python files to freeze to a common area, omitting top-level dirs (the repo names).
@@ -144,13 +144,13 @@ $(PROG): $(OBJ)
 # we may want to compile using Thumb, but link with non-Thumb libc.
 	$(Q)$(CC) -o $@ $^ $(LIB) $(LDFLAGS)
 ifndef DEBUG
-	$(Q)$(STRIP) $(STRIPFLAGS_EXTRA) $(PROG)
+	$(Q)$(STRIP) $(STRIPFLAGS_EXTRA) $(PROG)$(PROG_EXT)
 endif
-	$(Q)$(SIZE) $$(find $(BUILD) -path "$(BUILD)/build/frozen*.o") $(PROG)
+	$(Q)$(SIZE) $$(find $(BUILD) -path "$(BUILD)/build/frozen*.o") $(PROG)$(PROG_EXT)
 
 clean: clean-prog
 clean-prog:
-	$(RM) -f $(PROG)
+	$(RM) -f $(PROG)$(PROG_EXT)
 	$(RM) -f $(PROG).map
 
 .PHONY: clean-prog
diff --git a/py/modbuiltins.c b/py/modbuiltins.c
index 68dd33ef23..991feda8c9 100644
--- a/py/modbuiltins.c
+++ b/py/modbuiltins.c
@@ -27,12 +27,10 @@
 #include <stdio.h>
 #include <assert.h>
 
-#include "py/nlr.h"
 #include "py/smallint.h"
 #include "py/objint.h"
 #include "py/objstr.h"
 #include "py/objtype.h"
-#include "py/runtime0.h"
 #include "py/runtime.h"
 #include "py/builtin.h"
 #include "py/stream.h"
@@ -91,26 +89,7 @@ STATIC mp_obj_t mp_builtin___build_class__(size_t n_args, const mp_obj_t *args)
 MP_DEFINE_CONST_FUN_OBJ_VAR(mp_builtin___build_class___obj, 2, mp_builtin___build_class__);
 
 STATIC mp_obj_t mp_builtin_abs(mp_obj_t o_in) {
-    #if MICROPY_PY_BUILTINS_FLOAT
-    if (mp_obj_is_float(o_in)) {
-        mp_float_t value = mp_obj_float_get(o_in);
-        // TODO check for NaN etc
-        if (value < 0) {
-            return mp_obj_new_float(-value);
-        } else {
-            return o_in;
-        }
-    #if MICROPY_PY_BUILTINS_COMPLEX
-    } else if (MP_OBJ_IS_TYPE(o_in, &mp_type_complex)) {
-        mp_float_t real, imag;
-        mp_obj_complex_get(o_in, &real, &imag);
-        return mp_obj_new_float(MICROPY_FLOAT_C_FUN(sqrt)(real*real + imag*imag));
-    #endif
-    }
-    #endif
-
-    // this will raise a TypeError if the argument is not integral
-    return mp_obj_int_abs(o_in);
+    return mp_unary_op(MP_UNARY_OP_ABS, o_in);
 }
 MP_DEFINE_CONST_FUN_OBJ_1(mp_builtin_abs_obj, mp_builtin_abs);
 
diff --git a/py/modcmath.c b/py/modcmath.c
index 627a2cbadb..70fd542af9 100644
--- a/py/modcmath.c
+++ b/py/modcmath.c
@@ -30,13 +30,7 @@
 
 #include <math.h>
 
-/// \module cmath - mathematical functions for complex numbers
-///
-/// The `cmath` module provides some basic mathematical funtions for
-/// working with complex numbers.
-
-/// \function phase(z)
-/// Returns the phase of the number `z`, in the range (-pi, +pi].
+// phase(z): returns the phase of the number z in the range (-pi, +pi]
 STATIC mp_obj_t mp_cmath_phase(mp_obj_t z_obj) {
     mp_float_t real, imag;
     mp_obj_get_complex(z_obj, &real, &imag);
@@ -44,8 +38,7 @@ STATIC mp_obj_t mp_cmath_phase(mp_obj_t z_obj) {
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_1(mp_cmath_phase_obj, mp_cmath_phase);
 
-/// \function polar(z)
-/// Returns, as a tuple, the polar form of `z`.
+// polar(z): returns the polar form of z as a tuple
 STATIC mp_obj_t mp_cmath_polar(mp_obj_t z_obj) {
     mp_float_t real, imag;
     mp_obj_get_complex(z_obj, &real, &imag);
@@ -57,8 +50,7 @@ STATIC mp_obj_t mp_cmath_polar(mp_obj_t z_obj) {
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_1(mp_cmath_polar_obj, mp_cmath_polar);
 
-/// \function rect(r, phi)
-/// Returns the complex number with modulus `r` and phase `phi`.
+// rect(r, phi): returns the complex number with modulus r and phase phi
 STATIC mp_obj_t mp_cmath_rect(mp_obj_t r_obj, mp_obj_t phi_obj) {
     mp_float_t r = mp_obj_get_float(r_obj);
     mp_float_t phi = mp_obj_get_float(phi_obj);
@@ -66,8 +58,7 @@ STATIC mp_obj_t mp_cmath_rect(mp_obj_t r_obj, mp_obj_t phi_obj) {
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_2(mp_cmath_rect_obj, mp_cmath_rect);
 
-/// \function exp(z)
-/// Return the exponential of `z`.
+// exp(z): return the exponential of z
 STATIC mp_obj_t mp_cmath_exp(mp_obj_t z_obj) {
     mp_float_t real, imag;
     mp_obj_get_complex(z_obj, &real, &imag);
@@ -76,8 +67,7 @@ STATIC mp_obj_t mp_cmath_exp(mp_obj_t z_obj) {
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_1(mp_cmath_exp_obj, mp_cmath_exp);
 
-/// \function log(z)
-/// Return the natural logarithm of `z`.  The branch cut is along the negative real axis.
+// log(z): return the natural logarithm of z, with branch cut along the negative real axis
 // TODO can take second argument, being the base
 STATIC mp_obj_t mp_cmath_log(mp_obj_t z_obj) {
     mp_float_t real, imag;
@@ -87,8 +77,7 @@ STATIC mp_obj_t mp_cmath_log(mp_obj_t z_obj) {
 STATIC MP_DEFINE_CONST_FUN_OBJ_1(mp_cmath_log_obj, mp_cmath_log);
 
 #if MICROPY_PY_MATH_SPECIAL_FUNCTIONS
-/// \function log10(z)
-/// Return the base-10 logarithm of `z`.  The branch cut is along the negative real axis.
+// log10(z): return the base-10 logarithm of z, with branch cut along the negative real axis
 STATIC mp_obj_t mp_cmath_log10(mp_obj_t z_obj) {
     mp_float_t real, imag;
     mp_obj_get_complex(z_obj, &real, &imag);
@@ -97,8 +86,7 @@ STATIC mp_obj_t mp_cmath_log10(mp_obj_t z_obj) {
 STATIC MP_DEFINE_CONST_FUN_OBJ_1(mp_cmath_log10_obj, mp_cmath_log10);
 #endif
 
-/// \function sqrt(z)
-/// Return the square-root of `z`.
+// sqrt(z): return the square-root of z
 STATIC mp_obj_t mp_cmath_sqrt(mp_obj_t z_obj) {
     mp_float_t real, imag;
     mp_obj_get_complex(z_obj, &real, &imag);
@@ -108,8 +96,7 @@ STATIC mp_obj_t mp_cmath_sqrt(mp_obj_t z_obj) {
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_1(mp_cmath_sqrt_obj, mp_cmath_sqrt);
 
-/// \function cos(z)
-/// Return the cosine of `z`.
+// cos(z): return the cosine of z
 STATIC mp_obj_t mp_cmath_cos(mp_obj_t z_obj) {
     mp_float_t real, imag;
     mp_obj_get_complex(z_obj, &real, &imag);
@@ -117,8 +104,7 @@ STATIC mp_obj_t mp_cmath_cos(mp_obj_t z_obj) {
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_1(mp_cmath_cos_obj, mp_cmath_cos);
 
-/// \function sin(z)
-/// Return the sine of `z`.
+// sin(z): return the sine of z
 STATIC mp_obj_t mp_cmath_sin(mp_obj_t z_obj) {
     mp_float_t real, imag;
     mp_obj_get_complex(z_obj, &real, &imag);
diff --git a/py/modgc.c b/py/modgc.c
index d45e007ebe..55e73defce 100644
--- a/py/modgc.c
+++ b/py/modgc.c
@@ -30,10 +30,7 @@
 
 #if MICROPY_PY_GC && MICROPY_ENABLE_GC
 
-/// \module gc - control the garbage collector
-
-/// \function collect()
-/// Run a garbage collection.
+// collect(): run a garbage collection
 STATIC mp_obj_t py_gc_collect(void) {
     gc_collect();
 #if MICROPY_PY_GC_COLLECT_RETVAL
@@ -44,16 +41,14 @@ STATIC mp_obj_t py_gc_collect(void) {
 }
 MP_DEFINE_CONST_FUN_OBJ_0(gc_collect_obj, py_gc_collect);
 
-/// \function disable()
-/// Disable the garbage collector.
+// disable(): disable the garbage collector
 STATIC mp_obj_t gc_disable(void) {
     MP_STATE_MEM(gc_auto_collect_enabled) = 0;
     return mp_const_none;
 }
 MP_DEFINE_CONST_FUN_OBJ_0(gc_disable_obj, gc_disable);
 
-/// \function enable()
-/// Enable the garbage collector.
+// enable(): enable the garbage collector
 STATIC mp_obj_t gc_enable(void) {
     MP_STATE_MEM(gc_auto_collect_enabled) = 1;
     return mp_const_none;
@@ -65,8 +60,7 @@ STATIC mp_obj_t gc_isenabled(void) {
 }
 MP_DEFINE_CONST_FUN_OBJ_0(gc_isenabled_obj, gc_isenabled);
 
-/// \function mem_free()
-/// Return the number of bytes of available heap RAM.
+// mem_free(): return the number of bytes of available heap RAM
 STATIC mp_obj_t gc_mem_free(void) {
     gc_info_t info;
     gc_info(&info);
@@ -74,8 +68,7 @@ STATIC mp_obj_t gc_mem_free(void) {
 }
 MP_DEFINE_CONST_FUN_OBJ_0(gc_mem_free_obj, gc_mem_free);
 
-/// \function mem_alloc()
-/// Return the number of bytes of heap RAM that are allocated.
+// mem_alloc(): return the number of bytes of heap RAM that are allocated
 STATIC mp_obj_t gc_mem_alloc(void) {
     gc_info_t info;
     gc_info(&info);
diff --git a/py/modmath.c b/py/modmath.c
index ab276786d5..9097805967 100644
--- a/py/modmath.c
+++ b/py/modmath.c
@@ -36,11 +36,6 @@
 // And by defining our own we can ensure it uses the correct const format.
 #define MP_PI MICROPY_FLOAT_CONST(3.14159265358979323846)
 
-/// \module math - mathematical functions
-///
-/// The `math` module provides some basic mathematical funtions for
-/// working with floating-point numbers.
-
 STATIC NORETURN void math_error(void) {
     mp_raise_ValueError("math domain error");
 }
@@ -76,80 +71,74 @@ STATIC NORETURN void math_error(void) {
 #define log2(x) (log(x) * 1.442695040888963407354163704)
 #endif
 
-/// \function sqrt(x)
-/// Returns the square root of `x`.
+// sqrt(x): returns the square root of x
 MATH_FUN_1_ERRCOND(sqrt, sqrt, (x < (mp_float_t)0.0))
-/// \function pow(x, y)
-/// Returns `x` to the power of `y`.
+// pow(x, y): returns x to the power of y
 MATH_FUN_2(pow, pow)
-/// \function exp(x)
+// exp(x)
 MATH_FUN_1(exp, exp)
 #if MICROPY_PY_MATH_SPECIAL_FUNCTIONS
-/// \function expm1(x)
+// expm1(x)
 MATH_FUN_1(expm1, expm1)
-/// \function log2(x)
+// log2(x)
 MATH_FUN_1_ERRCOND(log2, log2, (x <= (mp_float_t)0.0))
-/// \function log10(x)
+// log10(x)
 MATH_FUN_1_ERRCOND(log10, log10, (x <= (mp_float_t)0.0))
-/// \function cosh(x)
+// cosh(x)
 MATH_FUN_1(cosh, cosh)
-/// \function sinh(x)
+// sinh(x)
 MATH_FUN_1(sinh, sinh)
-/// \function tanh(x)
+// tanh(x)
 MATH_FUN_1(tanh, tanh)
-/// \function acosh(x)
+// acosh(x)
 MATH_FUN_1(acosh, acosh)
-/// \function asinh(x)
+// asinh(x)
 MATH_FUN_1(asinh, asinh)
-/// \function atanh(x)
+// atanh(x)
 MATH_FUN_1(atanh, atanh)
 #endif
-/// \function cos(x)
+// cos(x)
 MATH_FUN_1(cos, cos)
-/// \function sin(x)
+// sin(x)
 MATH_FUN_1(sin, sin)
-/// \function tan(x)
+// tan(x)
 MATH_FUN_1(tan, tan)
-/// \function acos(x)
+// acos(x)
 MATH_FUN_1(acos, acos)
-/// \function asin(x)
+// asin(x)
 MATH_FUN_1(asin, asin)
-/// \function atan(x)
+// atan(x)
 MATH_FUN_1(atan, atan)
-/// \function atan2(y, x)
+// atan2(y, x)
 MATH_FUN_2(atan2, atan2)
-/// \function ceil(x)
+// ceil(x)
 MATH_FUN_1_TO_INT(ceil, ceil)
-/// \function copysign(x, y)
+// copysign(x, y)
 MATH_FUN_2(copysign, copysign)
-/// \function fabs(x)
+// fabs(x)
 MATH_FUN_1(fabs, fabs)
-/// \function floor(x)
+// floor(x)
 MATH_FUN_1_TO_INT(floor, floor) //TODO: delegate to x.__floor__() if x is not a float
-/// \function fmod(x, y)
+// fmod(x, y)
 MATH_FUN_2(fmod, fmod)
-/// \function isfinite(x)
+// isfinite(x)
 MATH_FUN_1_TO_BOOL(isfinite, isfinite)
-/// \function isinf(x)
+// isinf(x)
 MATH_FUN_1_TO_BOOL(isinf, isinf)
-/// \function isnan(x)
+// isnan(x)
 MATH_FUN_1_TO_BOOL(isnan, isnan)
-/// \function trunc(x)
+// trunc(x)
 MATH_FUN_1_TO_INT(trunc, trunc)
-/// \function ldexp(x, exp)
+// ldexp(x, exp)
 MATH_FUN_2(ldexp, ldexp)
 #if MICROPY_PY_MATH_SPECIAL_FUNCTIONS
-/// \function erf(x)
-/// Return the error function of `x`.
+// erf(x): return the error function of x
 MATH_FUN_1(erf, erf)
-/// \function erfc(x)
-/// Return the complementary error function of `x`.
+// erfc(x): return the complementary error function of x
 MATH_FUN_1(erfc, erfc)
-/// \function gamma(x)
-/// Return the gamma function of `x`.
+// gamma(x): return the gamma function of x
 MATH_FUN_1(gamma, tgamma)
-/// \function lgamma(x)
-/// return the natural logarithm of the gamma function of `x`.
+// lgamma(x): return the natural logarithm of the gamma function of x
 MATH_FUN_1(lgamma, lgamma)
 #endif
 //TODO: factorial, fsum
@@ -183,8 +172,7 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(mp_math_log_obj, 1, 2, mp_math_log);
 
 // Functions that return a tuple
 
-/// \function frexp(x)
-/// Converts a floating-point number to fractional and integral components.
+// frexp(x): converts a floating-point number to fractional and integral components
 STATIC mp_obj_t mp_math_frexp(mp_obj_t x_obj) {
     int int_exponent = 0;
     mp_float_t significand = MICROPY_FLOAT_C_FUN(frexp)(mp_obj_get_float(x_obj), &int_exponent);
@@ -195,7 +183,7 @@ STATIC mp_obj_t mp_math_frexp(mp_obj_t x_obj) {
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_1(mp_math_frexp_obj, mp_math_frexp);
 
-/// \function modf(x)
+// modf(x)
 STATIC mp_obj_t mp_math_modf(mp_obj_t x_obj) {
     mp_float_t int_part = 0.0;
     mp_float_t fractional_part = MICROPY_FLOAT_C_FUN(modf)(mp_obj_get_float(x_obj), &int_part);
@@ -208,13 +196,13 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_1(mp_math_modf_obj, mp_math_modf);
 
 // Angular conversions
 
-/// \function radians(x)
+// radians(x)
 STATIC mp_obj_t mp_math_radians(mp_obj_t x_obj) {
     return mp_obj_new_float(mp_obj_get_float(x_obj) * (MP_PI / MICROPY_FLOAT_CONST(180.0)));
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_1(mp_math_radians_obj, mp_math_radians);
 
-/// \function degrees(x)
+// degrees(x)
 STATIC mp_obj_t mp_math_degrees(mp_obj_t x_obj) {
     return mp_obj_new_float(mp_obj_get_float(x_obj) * (MICROPY_FLOAT_CONST(180.0) / MP_PI));
 }
diff --git a/py/modmicropython.c b/py/modmicropython.c
index 6fa3f9ad28..2aac53adc7 100644
--- a/py/modmicropython.c
+++ b/py/modmicropython.c
@@ -26,7 +26,6 @@
 
 #include <stdio.h>
 
-#include "py/mpstate.h"
 #include "py/builtin.h"
 #include "py/stackctrl.h"
 #include "py/runtime.h"
diff --git a/py/modstruct.c b/py/modstruct.c
index 1daa333388..8617a8e0d3 100644
--- a/py/modstruct.c
+++ b/py/modstruct.c
@@ -82,26 +82,10 @@ STATIC mp_uint_t get_fmt_num(const char **p) {
     return val;
 }
 
-STATIC uint calcsize_items(const char *fmt) {
-    uint cnt = 0;
-    while (*fmt) {
-        int num = 1;
-        if (unichar_isdigit(*fmt)) {
-            num = get_fmt_num(&fmt);
-            if (*fmt == 's') {
-                num = 1;
-            }
-        }
-        cnt += num;
-        fmt++;
-    }
-    return cnt;
-}
-
-STATIC mp_obj_t struct_calcsize(mp_obj_t fmt_in) {
-    const char *fmt = mp_obj_str_get_str(fmt_in);
+STATIC size_t calc_size_items(const char *fmt, size_t *total_sz) {
     char fmt_type = get_fmt_type(&fmt);
-    mp_uint_t size;
+    size_t total_cnt = 0;
+    size_t size;
     for (size = 0; *fmt; fmt++) {
         mp_uint_t cnt = 1;
         if (unichar_isdigit(*fmt)) {
@@ -109,8 +93,10 @@ STATIC mp_obj_t struct_calcsize(mp_obj_t fmt_in) {
         }
 
         if (*fmt == 's') {
+            total_cnt += 1;
             size += cnt;
         } else {
+            total_cnt += cnt;
             mp_uint_t align;
             size_t sz = mp_binary_get_size(fmt_type, *fmt, &align);
             while (cnt--) {
@@ -120,6 +106,14 @@ STATIC mp_obj_t struct_calcsize(mp_obj_t fmt_in) {
             }
         }
     }
+    *total_sz = size;
+    return total_cnt;
+}
+
+STATIC mp_obj_t struct_calcsize(mp_obj_t fmt_in) {
+    const char *fmt = mp_obj_str_get_str(fmt_in);
+    size_t size;
+    calc_size_items(fmt, &size);
     return MP_OBJ_NEW_SMALL_INT(size);
 }
 MP_DEFINE_CONST_FUN_OBJ_1(struct_calcsize_obj, struct_calcsize);
@@ -130,8 +124,9 @@ STATIC mp_obj_t struct_unpack_from(size_t n_args, const mp_obj_t *args) {
     // Since we implement unpack and unpack_from using the same function
     // we relax the "exact" requirement, and only implement "big enough".
     const char *fmt = mp_obj_str_get_str(args[0]);
+    size_t total_sz;
+    size_t num_items = calc_size_items(fmt, &total_sz);
     char fmt_type = get_fmt_type(&fmt);
-    uint num_items = calcsize_items(fmt);
     mp_obj_tuple_t *res = MP_OBJ_TO_PTR(mp_obj_new_tuple(num_items, NULL));
     mp_buffer_info_t bufinfo;
     mp_get_buffer_raise(args[1], &bufinfo, MP_BUFFER_READ);
@@ -152,21 +147,23 @@ STATIC mp_obj_t struct_unpack_from(size_t n_args, const mp_obj_t *args) {
         p += offset;
     }
 
-    for (uint i = 0; i < num_items;) {
-        mp_uint_t sz = 1;
+    // Check that the input buffer is big enough to unpack all the values
+    if (p + total_sz > end_p) {
+        mp_raise_ValueError("buffer too small");
+    }
+
+    for (size_t i = 0; i < num_items;) {
+        mp_uint_t cnt = 1;
         if (unichar_isdigit(*fmt)) {
-            sz = get_fmt_num(&fmt);
-        }
-        if (p + sz > end_p) {
-            mp_raise_ValueError("buffer too small");
+            cnt = get_fmt_num(&fmt);
         }
         mp_obj_t item;
         if (*fmt == 's') {
-            item = mp_obj_new_bytes(p, sz);
-            p += sz;
+            item = mp_obj_new_bytes(p, cnt);
+            p += cnt;
             res->items[i++] = item;
         } else {
-            while (sz--) {
+            while (cnt--) {
                 item = mp_binary_get_val(fmt_type, *fmt, &p);
                 res->items[i++] = item;
             }
@@ -177,36 +174,35 @@ STATIC mp_obj_t struct_unpack_from(size_t n_args, const mp_obj_t *args) {
 }
 MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(struct_unpack_from_obj, 2, 3, struct_unpack_from);
 
-STATIC void struct_pack_into_internal(mp_obj_t fmt_in, byte *p, byte* end_p, size_t n_args, const mp_obj_t *args) {
+// This function assumes there is enough room in p to store all the values
+STATIC void struct_pack_into_internal(mp_obj_t fmt_in, byte *p, size_t n_args, const mp_obj_t *args) {
     const char *fmt = mp_obj_str_get_str(fmt_in);
     char fmt_type = get_fmt_type(&fmt);
 
     size_t i;
     for (i = 0; i < n_args;) {
-        mp_uint_t sz = 1;
+        mp_uint_t cnt = 1;
         if (*fmt == '\0') {
             // more arguments given than used by format string; CPython raises struct.error here
             break;
         }
         if (unichar_isdigit(*fmt)) {
-            sz = get_fmt_num(&fmt);
-        }
-        if (p + sz > end_p) {
-            mp_raise_ValueError("buffer too small");
+            cnt = get_fmt_num(&fmt);
         }
 
         if (*fmt == 's') {
             mp_buffer_info_t bufinfo;
             mp_get_buffer_raise(args[i++], &bufinfo, MP_BUFFER_READ);
-            mp_uint_t to_copy = sz;
+            mp_uint_t to_copy = cnt;
             if (bufinfo.len < to_copy) {
                 to_copy = bufinfo.len;
             }
             memcpy(p, bufinfo.buf, to_copy);
-            memset(p + to_copy, 0, sz - to_copy);
-            p += sz;
+            memset(p + to_copy, 0, cnt - to_copy);
+            p += cnt;
         } else {
-            while (sz--) {
+            // If we run out of args then we just finish; CPython would raise struct.error
+            while (cnt-- && i < n_args) {
                 mp_binary_set_val(fmt_type, *fmt, args[i++], &p);
             }
         }
@@ -221,8 +217,7 @@ STATIC mp_obj_t struct_pack(size_t n_args, const mp_obj_t *args) {
     vstr_init_len(&vstr, size);
     byte *p = (byte*)vstr.buf;
     memset(p, 0, size);
-    byte *end_p = &p[size];
-    struct_pack_into_internal(args[0], p, end_p, n_args - 1, &args[1]);
+    struct_pack_into_internal(args[0], p, n_args - 1, &args[1]);
     return mp_obj_new_str_from_vstr(&mp_type_bytes, &vstr);
 }
 MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(struct_pack_obj, 1, MP_OBJ_FUN_ARGS_MAX, struct_pack);
@@ -242,7 +237,13 @@ STATIC mp_obj_t struct_pack_into(size_t n_args, const mp_obj_t *args) {
     byte *end_p = &p[bufinfo.len];
     p += offset;
 
-    struct_pack_into_internal(args[0], p, end_p, n_args - 3, &args[3]);
+    // Check that the output buffer is big enough to hold all the values
+    mp_int_t sz = MP_OBJ_SMALL_INT_VALUE(struct_calcsize(args[0]));
+    if (p + sz > end_p) {
+        mp_raise_ValueError("buffer too small");
+    }
+
+    struct_pack_into_internal(args[0], p, n_args - 3, &args[3]);
     return mp_const_none;
 }
 MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(struct_pack_into_obj, 3, MP_OBJ_FUN_ARGS_MAX, struct_pack_into);
diff --git a/py/modsys.c b/py/modsys.c
index ffa7dff111..de3cb7e1ff 100644
--- a/py/modsys.c
+++ b/py/modsys.c
@@ -25,8 +25,6 @@
  * THE SOFTWARE.
  */
 
-#include "py/mpstate.h"
-#include "py/nlr.h"
 #include "py/builtin.h"
 #include "py/objlist.h"
 #include "py/objtuple.h"
@@ -35,15 +33,12 @@
 #include "py/objtype.h"
 #include "py/stream.h"
 #include "py/smallint.h"
-#include "py/runtime0.h"
 #include "py/runtime.h"
 
 #if MICROPY_PY_SYS
 
 #include "genhdr/mpversion.h"
 
-/// \module sys - system specific functions
-
 // defined per port; type of these is irrelevant, just need pointer
 extern struct _mp_dummy_t mp_sys_stdin_obj;
 extern struct _mp_dummy_t mp_sys_stdout_obj;
@@ -53,10 +48,10 @@ extern struct _mp_dummy_t mp_sys_stderr_obj;
 const mp_print_t mp_sys_stdout_print = {&mp_sys_stdout_obj, mp_stream_write_adaptor};
 #endif
 
-/// \constant version - Python language version that this implementation conforms to, as a string
+// version - Python language version that this implementation conforms to, as a string
 STATIC const MP_DEFINE_STR_OBJ(version_obj, "3.4.0");
 
-/// \constant version_info - Python language version that this implementation conforms to, as a tuple of ints
+// version_info - Python language version that this implementation conforms to, as a tuple of ints
 #define I(n) MP_OBJ_NEW_SMALL_INT(n)
 // TODO: CPython is now at 5-element array, but save 2 els so far...
 STATIC const mp_obj_tuple_t mp_sys_version_info_obj = {{&mp_type_tuple}, 3, {I(3), I(4), I(0)}};
@@ -91,13 +86,11 @@ STATIC const mp_rom_obj_tuple_t mp_sys_implementation_obj = {
 #undef I
 
 #ifdef MICROPY_PY_SYS_PLATFORM
-/// \constant platform - the platform that MicroPython is running on
+// platform - the platform that MicroPython is running on
 STATIC const MP_DEFINE_STR_OBJ(platform_obj, MICROPY_PY_SYS_PLATFORM);
 #endif
 
-/// \function exit([retval])
-/// Raise a `SystemExit` exception.  If an argument is given, it is the
-/// value given to `SystemExit`.
+// exit([retval]): raise SystemExit, with optional argument given to the exception
 STATIC mp_obj_t mp_sys_exit(size_t n_args, const mp_obj_t *args) {
     mp_obj_t exc;
     if (n_args == 0) {
@@ -163,7 +156,6 @@ STATIC const mp_rom_map_elem_t mp_module_sys_globals_table[] = {
     #ifdef MICROPY_PY_SYS_PLATFORM
     { MP_ROM_QSTR(MP_QSTR_platform), MP_ROM_PTR(&platform_obj) },
     #endif
-    /// \constant byteorder - the byte order of the system ("little" or "big")
     #if MP_ENDIANNESS_LITTLE
     { MP_ROM_QSTR(MP_QSTR_byteorder), MP_ROM_QSTR(MP_QSTR_little) },
     #else
@@ -184,12 +176,10 @@ STATIC const mp_rom_map_elem_t mp_module_sys_globals_table[] = {
     #endif
 
     #if MICROPY_PY_SYS_EXIT
-    // documented per-port
     { MP_ROM_QSTR(MP_QSTR_exit), MP_ROM_PTR(&mp_sys_exit_obj) },
     #endif
 
     #if MICROPY_PY_SYS_STDFILES
-    // documented per-port
     { MP_ROM_QSTR(MP_QSTR_stdin), MP_ROM_PTR(&mp_sys_stdin_obj) },
     { MP_ROM_QSTR(MP_QSTR_stdout), MP_ROM_PTR(&mp_sys_stdout_obj) },
     { MP_ROM_QSTR(MP_QSTR_stderr), MP_ROM_PTR(&mp_sys_stderr_obj) },
diff --git a/py/modthread.c b/py/modthread.c
index bf74128e81..cb071d0f86 100644
--- a/py/modthread.c
+++ b/py/modthread.c
@@ -192,10 +192,10 @@ STATIC void *thread_entry(void *args_in) {
             // swallow exception silently
         } else {
             // print exception out
-            mp_printf(&mp_plat_print, "Unhandled exception in thread started by ");
-            mp_obj_print_helper(&mp_plat_print, args->fun, PRINT_REPR);
-            mp_printf(&mp_plat_print, "\n");
-            mp_obj_print_exception(&mp_plat_print, MP_OBJ_FROM_PTR(exc));
+            mp_printf(MICROPY_ERROR_PRINTER, "Unhandled exception in thread started by ");
+            mp_obj_print_helper(MICROPY_ERROR_PRINTER, args->fun, PRINT_REPR);
+            mp_printf(MICROPY_ERROR_PRINTER, "\n");
+            mp_obj_print_exception(MICROPY_ERROR_PRINTER, MP_OBJ_FROM_PTR(exc));
         }
     }
 
diff --git a/py/mpconfig.h b/py/mpconfig.h
index 93089e37d0..cec9fb748d 100644
--- a/py/mpconfig.h
+++ b/py/mpconfig.h
@@ -383,6 +383,8 @@
 
 // Whether to use computed gotos in the VM, or a switch
 // Computed gotos are roughly 10% faster, and increase VM code size by a little
+// Note: enabling this will use the gcc-specific extensions of ranged designated
+// initialisers and addresses of labels, which are not part of the C99 standard.
 #ifndef MICROPY_OPT_COMPUTED_GOTO
 #define MICROPY_OPT_COMPUTED_GOTO (0)
 #endif
@@ -541,6 +543,11 @@ typedef long long mp_longint_impl_t;
 #define MICROPY_WARNINGS (0)
 #endif
 
+// This macro is used when printing runtime warnings and errors
+#ifndef MICROPY_ERROR_PRINTER
+#define MICROPY_ERROR_PRINTER (&mp_plat_print)
+#endif
+
 // Float and complex implementation
 #define MICROPY_FLOAT_IMPL_NONE (0)
 #define MICROPY_FLOAT_IMPL_FLOAT (1)
@@ -701,6 +708,11 @@ typedef double mp_float_t;
 #define MICROPY_PY_BUILTINS_STR_UNICODE (0)
 #endif
 
+// Whether to check for valid UTF-8 when converting bytes to str
+#ifndef MICROPY_PY_BUILTINS_STR_UNICODE_CHECK
+#define MICROPY_PY_BUILTINS_STR_UNICODE_CHECK (MICROPY_PY_BUILTINS_STR_UNICODE)
+#endif
+
 // Whether str.center() method provided
 #ifndef MICROPY_PY_BUILTINS_STR_CENTER
 #define MICROPY_PY_BUILTINS_STR_CENTER (0)
@@ -764,11 +776,19 @@ typedef double mp_float_t;
 #endif
 
 // Whether to support complete set of special methods
-// for user classes, otherwise only the most used
+// for user classes, or only the most used ones. "Reverse"
+// methods are controlled by MICROPY_PY_REVERSE_SPECIAL_METHODS
+// below.
 #ifndef MICROPY_PY_ALL_SPECIAL_METHODS
 #define MICROPY_PY_ALL_SPECIAL_METHODS (0)
 #endif
 
+// Whether to support reverse arithmetic operarions methods
+// (__radd__, etc.)
+#ifndef MICROPY_PY_REVERSE_SPECIAL_METHODS
+#define MICROPY_PY_REVERSE_SPECIAL_METHODS (0)
+#endif
+
 // Whether to support compile function
 #ifndef MICROPY_PY_BUILTINS_COMPILE
 #define MICROPY_PY_BUILTINS_COMPILE (0)
diff --git a/py/mpprint.c b/py/mpprint.c
index 6c02d7cefb..a569ef7931 100644
--- a/py/mpprint.c
+++ b/py/mpprint.c
@@ -485,14 +485,17 @@ int mp_vprintf(const mp_print_t *print, const char *fmt, va_list args) {
             case 's':
             {
                 const char *str = va_arg(args, const char*);
-                if (str) {
-                    if (prec < 0) {
-                        prec = strlen(str);
-                    }
-                    chrs += mp_print_strn(print, str, prec, flags, fill, width);
-                } else {
+                #ifndef NDEBUG
+                // With debugging enabled, catch printing of null string pointers
+                if (prec != 0 && str == NULL) {
                     chrs += mp_print_strn(print, "(null)", 6, flags, fill, width);
+                    break;
                 }
+                #endif
+                if (prec < 0) {
+                    prec = strlen(str);
+                }
+                chrs += mp_print_strn(print, str, prec, flags, fill, width);
                 break;
             }
             case 'u':
diff --git a/py/nativeglue.c b/py/nativeglue.c
index e954234c27..61b624ec71 100644
--- a/py/nativeglue.c
+++ b/py/nativeglue.c
@@ -28,8 +28,6 @@
 #include <string.h>
 #include <assert.h>
 
-#include "py/nlr.h"
-#include "py/runtime0.h"
 #include "py/runtime.h"
 #include "py/emitglue.h"
 #include "py/bc.h"
diff --git a/py/nlrthumb.c b/py/nlrthumb.c
index 08a71ac7d6..6e7d717667 100644
--- a/py/nlrthumb.c
+++ b/py/nlrthumb.c
@@ -25,7 +25,6 @@
  */
 
 #include "py/mpstate.h"
-#include "py/nlr.h"
 
 #if (!defined(MICROPY_NLR_SETJMP) || !MICROPY_NLR_SETJMP) && (defined(__thumb2__) || defined(__thumb__) || defined(__arm__))
 
@@ -67,7 +66,14 @@ __attribute__((naked)) unsigned int nlr_push(nlr_buf_t *nlr) {
     "str    lr, [r0, #8]        \n" // store lr into nlr_buf
 #endif
 
+#if defined(__ARM_ARCH_6M__)
+    "ldr    r1, nlr_push_tail_var \n"
+    "bx     r1                  \n" // do the rest in C
+    ".align 2                   \n"
+    "nlr_push_tail_var: .word nlr_push_tail \n"
+#else
     "b      nlr_push_tail       \n" // do the rest in C
+#endif
     );
 
     return 0; // needed to silence compiler warning
diff --git a/py/nlrx64.c b/py/nlrx64.c
index c23fd8fc6a..847d10398e 100644
--- a/py/nlrx64.c
+++ b/py/nlrx64.c
@@ -25,7 +25,6 @@
  */
 
 #include "py/mpstate.h"
-#include "py/nlr.h"
 
 #if !MICROPY_NLR_SETJMP && defined(__x86_64__)
 
@@ -34,7 +33,11 @@
 // x86-64 callee-save registers are:
 //  rbx, rbp, rsp, r12, r13, r14, r15
 
-#define NLR_OS_WINDOWS (defined(_WIN32) || defined(__CYGWIN__))
+#if defined(_WIN32) || defined(__CYGWIN__)
+#define NLR_OS_WINDOWS 1
+#else
+#define NLR_OS_WINDOWS 0
+#endif
 
 __attribute__((used)) unsigned int nlr_push_tail(nlr_buf_t *nlr);
 
diff --git a/py/nlrx86.c b/py/nlrx86.c
index 58aaa1a571..094dea3cc8 100644
--- a/py/nlrx86.c
+++ b/py/nlrx86.c
@@ -24,9 +24,7 @@
  * THE SOFTWARE.
  */
 
-#include "py/mpconfig.h"
 #include "py/mpstate.h"
-#include "py/nlr.h"
 
 #if !MICROPY_NLR_SETJMP && defined(__i386__)
 
@@ -35,7 +33,11 @@
 // For reference, x86 callee save regs are:
 //  ebx, esi, edi, ebp, esp, eip
 
-#define NLR_OS_WINDOWS (defined(_WIN32) || defined(__CYGWIN__))
+#if defined(_WIN32) || defined(__CYGWIN__)
+#define NLR_OS_WINDOWS 1
+#else
+#define NLR_OS_WINDOWS 0
+#endif
 
 #if NLR_OS_WINDOWS
 unsigned int nlr_push_tail(nlr_buf_t *nlr) asm("nlr_push_tail");
@@ -51,7 +53,7 @@ unsigned int nlr_push(nlr_buf_t *nlr) {
     // by default.
     // TODE: Better support for various x86 calling conventions
     // (unfortunately, __attribute__((naked)) is not supported on x86).
-    #ifndef __ZEPHYR__
+    #if !(defined(__ZEPHYR__) || defined(__ANDROID__))
     "pop    %ebp                \n" // undo function's prelude
     #endif
     "mov    4(%esp), %edx       \n" // load nlr_buf
diff --git a/py/nlrxtensa.c b/py/nlrxtensa.c
index ccac3597b1..4520e7e7ac 100644
--- a/py/nlrxtensa.c
+++ b/py/nlrxtensa.c
@@ -25,7 +25,6 @@
  */
 
 #include "py/mpstate.h"
-#include "py/nlr.h"
 
 #if !MICROPY_NLR_SETJMP && defined(__xtensa__)
 
diff --git a/py/obj.c b/py/obj.c
index 7384143cf6..4eb1716266 100644
--- a/py/obj.c
+++ b/py/obj.c
@@ -29,12 +29,10 @@
 #include <stdarg.h>
 #include <assert.h>
 
-#include "py/nlr.h"
 #include "py/obj.h"
 #include "py/objtype.h"
 #include "py/objint.h"
 #include "py/objstr.h"
-#include "py/runtime0.h"
 #include "py/runtime.h"
 #include "py/stackctrl.h"
 #include "py/stream.h" // for mp_obj_print
@@ -162,7 +160,16 @@ bool mp_obj_is_callable(mp_obj_t o_in) {
 // comparison returns NotImplemented, == and != are decided by comparing the object
 // pointer."
 bool mp_obj_equal(mp_obj_t o1, mp_obj_t o2) {
-    if (o1 == o2) {
+    // Float (and complex) NaN is never equal to anything, not even itself,
+    // so we must have a special check here to cover those cases.
+    if (o1 == o2
+        #if MICROPY_PY_BUILTINS_FLOAT
+        && !mp_obj_is_float(o1)
+        #endif
+        #if MICROPY_PY_BUILTINS_COMPLEX
+        && !MP_OBJ_IS_TYPE(o1, &mp_type_complex)
+        #endif
+        ) {
         return true;
     }
     if (o1 == mp_const_none || o2 == mp_const_none) {
@@ -264,20 +271,33 @@ bool mp_obj_get_int_maybe(mp_const_obj_t arg, mp_int_t *value) {
 }
 
 #if MICROPY_PY_BUILTINS_FLOAT
-mp_float_t mp_obj_get_float(mp_obj_t arg) {
+bool mp_obj_get_float_maybe(mp_obj_t arg, mp_float_t *value) {
+    mp_float_t val;
+
     if (arg == mp_const_false) {
-        return 0;
+        val = 0;
     } else if (arg == mp_const_true) {
-        return 1;
+        val = 1;
     } else if (MP_OBJ_IS_SMALL_INT(arg)) {
-        return MP_OBJ_SMALL_INT_VALUE(arg);
+        val = MP_OBJ_SMALL_INT_VALUE(arg);
     #if MICROPY_LONGINT_IMPL != MICROPY_LONGINT_IMPL_NONE
     } else if (MP_OBJ_IS_TYPE(arg, &mp_type_int)) {
-        return mp_obj_int_as_float_impl(arg);
+        val = mp_obj_int_as_float_impl(arg);
     #endif
     } else if (mp_obj_is_float(arg)) {
-        return mp_obj_float_get(arg);
+        val = mp_obj_float_get(arg);
     } else {
+        return false;
+    }
+
+    *value = val;
+    return true;
+}
+
+mp_float_t mp_obj_get_float(mp_obj_t arg) {
+    mp_float_t val;
+
+    if (!mp_obj_get_float_maybe(arg, &val)) {
         if (MICROPY_ERROR_REPORTING == MICROPY_ERROR_REPORTING_TERSE) {
             mp_raise_TypeError("can't convert to float");
         } else {
@@ -285,6 +305,8 @@ mp_float_t mp_obj_get_float(mp_obj_t arg) {
                 "can't convert %s to float", mp_obj_get_type_str(arg));
         }
     }
+
+    return val;
 }
 
 #if MICROPY_PY_BUILTINS_COMPLEX
@@ -505,7 +527,7 @@ void mp_get_buffer_raise(mp_obj_t obj, mp_buffer_info_t *bufinfo, mp_uint_t flag
     }
 }
 
-mp_obj_t mp_generic_unary_op(mp_uint_t op, mp_obj_t o_in) {
+mp_obj_t mp_generic_unary_op(mp_unary_op_t op, mp_obj_t o_in) {
     switch (op) {
         case MP_UNARY_OP_HASH: return MP_OBJ_NEW_SMALL_INT((mp_uint_t)o_in);
         default: return MP_OBJ_NULL; // op not supported
diff --git a/py/obj.h b/py/obj.h
index 2384b1602f..3f784dafcc 100644
--- a/py/obj.h
+++ b/py/obj.h
@@ -32,6 +32,7 @@
 #include "py/misc.h"
 #include "py/qstr.h"
 #include "py/mpprint.h"
+#include "py/runtime0.h"
 
 // This is the definition of the opaque MicroPython object type.
 // All concrete objects have an encoding within this type and the
@@ -431,8 +432,8 @@ typedef struct _mp_obj_iter_buf_t {
 typedef void (*mp_print_fun_t)(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind);
 typedef mp_obj_t (*mp_make_new_fun_t)(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args);
 typedef mp_obj_t (*mp_call_fun_t)(mp_obj_t fun, size_t n_args, size_t n_kw, const mp_obj_t *args);
-typedef mp_obj_t (*mp_unary_op_fun_t)(mp_uint_t op, mp_obj_t);
-typedef mp_obj_t (*mp_binary_op_fun_t)(mp_uint_t op, mp_obj_t, mp_obj_t);
+typedef mp_obj_t (*mp_unary_op_fun_t)(mp_unary_op_t op, mp_obj_t);
+typedef mp_obj_t (*mp_binary_op_fun_t)(mp_binary_op_t op, mp_obj_t, mp_obj_t);
 typedef void (*mp_attr_fun_t)(mp_obj_t self_in, qstr attr, mp_obj_t *dest);
 typedef mp_obj_t (*mp_subscr_fun_t)(mp_obj_t self_in, mp_obj_t index, mp_obj_t value);
 typedef mp_obj_t (*mp_getiter_fun_t)(mp_obj_t self_in, mp_obj_iter_buf_t *iter_buf);
@@ -615,6 +616,7 @@ extern const mp_obj_type_t mp_type_ZeroDivisionError;
 #define mp_const_true (MP_OBJ_FROM_PTR(&mp_const_true_obj))
 #define mp_const_empty_bytes (MP_OBJ_FROM_PTR(&mp_const_empty_bytes_obj))
 #define mp_const_empty_tuple (MP_OBJ_FROM_PTR(&mp_const_empty_tuple_obj))
+#define mp_const_notimplemented (MP_OBJ_FROM_PTR(&mp_const_notimplemented_obj))
 extern const struct _mp_obj_none_t mp_const_none_obj;
 extern const struct _mp_obj_bool_t mp_const_false_obj;
 extern const struct _mp_obj_bool_t mp_const_true_obj;
@@ -628,7 +630,6 @@ extern const struct _mp_obj_exception_t mp_const_GeneratorExit_obj;
 // General API for objects
 
 mp_obj_t mp_obj_new_type(qstr name, mp_obj_t bases_tuple, mp_obj_t locals_dict);
-mp_obj_t mp_obj_new_none(void);
 static inline mp_obj_t mp_obj_new_bool(mp_int_t x) { return x ? mp_const_true : mp_const_false; }
 mp_obj_t mp_obj_new_cell(mp_obj_t obj);
 mp_obj_t mp_obj_new_int(mp_int_t value);
@@ -685,6 +686,7 @@ mp_int_t mp_obj_get_int_truncated(mp_const_obj_t arg);
 bool mp_obj_get_int_maybe(mp_const_obj_t arg, mp_int_t *value);
 #if MICROPY_PY_BUILTINS_FLOAT
 mp_float_t mp_obj_get_float(mp_obj_t self_in);
+bool mp_obj_get_float_maybe(mp_obj_t arg, mp_float_t *value);
 void mp_obj_get_complex(mp_obj_t self_in, mp_float_t *real, mp_float_t *imag);
 #endif
 //qstr mp_obj_get_qstr(mp_obj_t arg);
@@ -695,7 +697,7 @@ mp_obj_t mp_obj_id(mp_obj_t o_in);
 mp_obj_t mp_obj_len(mp_obj_t o_in);
 mp_obj_t mp_obj_len_maybe(mp_obj_t o_in); // may return MP_OBJ_NULL
 mp_obj_t mp_obj_subscr(mp_obj_t base, mp_obj_t index, mp_obj_t val);
-mp_obj_t mp_generic_unary_op(mp_uint_t op, mp_obj_t o_in);
+mp_obj_t mp_generic_unary_op(mp_unary_op_t op, mp_obj_t o_in);
 
 // cell
 mp_obj_t mp_obj_cell_get(mp_obj_t self_in);
@@ -735,11 +737,11 @@ mp_int_t mp_float_hash(mp_float_t val);
 #else
 static inline mp_int_t mp_float_hash(mp_float_t val) { return (mp_int_t)val; }
 #endif
-mp_obj_t mp_obj_float_binary_op(mp_uint_t op, mp_float_t lhs_val, mp_obj_t rhs); // can return MP_OBJ_NULL if op not supported
+mp_obj_t mp_obj_float_binary_op(mp_binary_op_t op, mp_float_t lhs_val, mp_obj_t rhs); // can return MP_OBJ_NULL if op not supported
 
 // complex
 void mp_obj_complex_get(mp_obj_t self_in, mp_float_t *real, mp_float_t *imag);
-mp_obj_t mp_obj_complex_binary_op(mp_uint_t op, mp_float_t lhs_real, mp_float_t lhs_imag, mp_obj_t rhs_in); // can return MP_OBJ_NULL if op not supported
+mp_obj_t mp_obj_complex_binary_op(mp_binary_op_t op, mp_float_t lhs_real, mp_float_t lhs_imag, mp_obj_t rhs_in); // can return MP_OBJ_NULL if op not supported
 #else
 #define mp_obj_is_float(o) (false)
 #endif
diff --git a/py/objarray.c b/py/objarray.c
index 789a29fef7..b8dca32f71 100644
--- a/py/objarray.c
+++ b/py/objarray.c
@@ -29,8 +29,6 @@
 #include <assert.h>
 #include <stdint.h>
 
-#include "py/nlr.h"
-#include "py/runtime0.h"
 #include "py/runtime.h"
 #include "py/binary.h"
 #include "py/objstr.h"
@@ -231,7 +229,7 @@ STATIC mp_obj_t memoryview_make_new(const mp_obj_type_t *type_in, size_t n_args,
 }
 #endif
 
-STATIC mp_obj_t array_unary_op(mp_uint_t op, mp_obj_t o_in) {
+STATIC mp_obj_t array_unary_op(mp_unary_op_t op, mp_obj_t o_in) {
     mp_obj_array_t *o = MP_OBJ_TO_PTR(o_in);
     switch (op) {
         case MP_UNARY_OP_BOOL: return mp_obj_new_bool(o->len != 0);
@@ -240,7 +238,7 @@ STATIC mp_obj_t array_unary_op(mp_uint_t op, mp_obj_t o_in) {
     }
 }
 
-STATIC mp_obj_t array_binary_op(mp_uint_t op, mp_obj_t lhs_in, mp_obj_t rhs_in) {
+STATIC mp_obj_t array_binary_op(mp_binary_op_t op, mp_obj_t lhs_in, mp_obj_t rhs_in) {
     mp_obj_array_t *lhs = MP_OBJ_TO_PTR(lhs_in);
     switch (op) {
         case MP_BINARY_OP_ADD: {
diff --git a/py/objbool.c b/py/objbool.c
index e5bc3c2287..5755b188e9 100644
--- a/py/objbool.c
+++ b/py/objbool.c
@@ -26,8 +26,6 @@
 
 #include <stdlib.h>
 
-#include "py/obj.h"
-#include "py/runtime0.h"
 #include "py/runtime.h"
 
 typedef struct _mp_obj_bool_t {
@@ -63,7 +61,7 @@ STATIC mp_obj_t bool_make_new(const mp_obj_type_t *type_in, size_t n_args, size_
     }
 }
 
-STATIC mp_obj_t bool_unary_op(mp_uint_t op, mp_obj_t o_in) {
+STATIC mp_obj_t bool_unary_op(mp_unary_op_t op, mp_obj_t o_in) {
     if (op == MP_UNARY_OP_LEN) {
         return MP_OBJ_NULL;
     }
@@ -71,7 +69,7 @@ STATIC mp_obj_t bool_unary_op(mp_uint_t op, mp_obj_t o_in) {
     return mp_unary_op(op, MP_OBJ_NEW_SMALL_INT(self->value));
 }
 
-STATIC mp_obj_t bool_binary_op(mp_uint_t op, mp_obj_t lhs_in, mp_obj_t rhs_in) {
+STATIC mp_obj_t bool_binary_op(mp_binary_op_t op, mp_obj_t lhs_in, mp_obj_t rhs_in) {
     mp_obj_bool_t *self = MP_OBJ_TO_PTR(lhs_in);
     return mp_binary_op(op, MP_OBJ_NEW_SMALL_INT(self->value), rhs_in);
 }
diff --git a/py/objcomplex.c b/py/objcomplex.c
index 98dcf7e312..261c2b1f0f 100644
--- a/py/objcomplex.c
+++ b/py/objcomplex.c
@@ -28,10 +28,7 @@
 #include <stdio.h>
 #include <assert.h>
 
-#include "py/nlr.h"
-#include "py/obj.h"
 #include "py/parsenum.h"
-#include "py/runtime0.h"
 #include "py/runtime.h"
 
 #if MICROPY_PY_BUILTINS_COMPLEX
@@ -120,18 +117,20 @@ STATIC mp_obj_t complex_make_new(const mp_obj_type_t *type_in, size_t n_args, si
     }
 }
 
-STATIC mp_obj_t complex_unary_op(mp_uint_t op, mp_obj_t o_in) {
+STATIC mp_obj_t complex_unary_op(mp_unary_op_t op, mp_obj_t o_in) {
     mp_obj_complex_t *o = MP_OBJ_TO_PTR(o_in);
     switch (op) {
         case MP_UNARY_OP_BOOL: return mp_obj_new_bool(o->real != 0 || o->imag != 0);
         case MP_UNARY_OP_HASH: return MP_OBJ_NEW_SMALL_INT(mp_float_hash(o->real) ^ mp_float_hash(o->imag));
         case MP_UNARY_OP_POSITIVE: return o_in;
         case MP_UNARY_OP_NEGATIVE: return mp_obj_new_complex(-o->real, -o->imag);
+        case MP_UNARY_OP_ABS:
+            return mp_obj_new_float(MICROPY_FLOAT_C_FUN(sqrt)(o->real*o->real + o->imag*o->imag));
         default: return MP_OBJ_NULL; // op not supported
     }
 }
 
-STATIC mp_obj_t complex_binary_op(mp_uint_t op, mp_obj_t lhs_in, mp_obj_t rhs_in) {
+STATIC mp_obj_t complex_binary_op(mp_binary_op_t op, mp_obj_t lhs_in, mp_obj_t rhs_in) {
     mp_obj_complex_t *lhs = MP_OBJ_TO_PTR(lhs_in);
     return mp_obj_complex_binary_op(op, lhs->real, lhs->imag, rhs_in);
 }
@@ -174,7 +173,7 @@ void mp_obj_complex_get(mp_obj_t self_in, mp_float_t *real, mp_float_t *imag) {
     *imag = self->imag;
 }
 
-mp_obj_t mp_obj_complex_binary_op(mp_uint_t op, mp_float_t lhs_real, mp_float_t lhs_imag, mp_obj_t rhs_in) {
+mp_obj_t mp_obj_complex_binary_op(mp_binary_op_t op, mp_float_t lhs_real, mp_float_t lhs_imag, mp_obj_t rhs_in) {
     mp_float_t rhs_real, rhs_imag;
     mp_obj_get_complex(rhs_in, &rhs_real, &rhs_imag); // can be any type, this function will convert to float (if possible)
     switch (op) {
diff --git a/py/objdict.c b/py/objdict.c
index f6357a905b..1553a83b46 100644
--- a/py/objdict.c
+++ b/py/objdict.c
@@ -27,9 +27,6 @@
 #include <string.h>
 #include <assert.h>
 
-#include "py/nlr.h"
-#include "py/obj.h"
-#include "py/runtime0.h"
 #include "py/runtime.h"
 #include "py/builtin.h"
 #include "py/objtype.h"
@@ -100,7 +97,7 @@ STATIC mp_obj_t dict_make_new(const mp_obj_type_t *type, size_t n_args, size_t n
     return dict_out;
 }
 
-STATIC mp_obj_t dict_unary_op(mp_uint_t op, mp_obj_t self_in) {
+STATIC mp_obj_t dict_unary_op(mp_unary_op_t op, mp_obj_t self_in) {
     mp_obj_dict_t *self = MP_OBJ_TO_PTR(self_in);
     switch (op) {
         case MP_UNARY_OP_BOOL: return mp_obj_new_bool(self->map.used != 0);
@@ -115,7 +112,7 @@ STATIC mp_obj_t dict_unary_op(mp_uint_t op, mp_obj_t self_in) {
     }
 }
 
-STATIC mp_obj_t dict_binary_op(mp_uint_t op, mp_obj_t lhs_in, mp_obj_t rhs_in) {
+STATIC mp_obj_t dict_binary_op(mp_binary_op_t op, mp_obj_t lhs_in, mp_obj_t rhs_in) {
     mp_obj_dict_t *o = MP_OBJ_TO_PTR(lhs_in);
     switch (op) {
         case MP_BINARY_OP_IN: {
@@ -482,7 +479,7 @@ STATIC void dict_view_print(const mp_print_t *print, mp_obj_t self_in, mp_print_
     mp_print_str(print, "])");
 }
 
-STATIC mp_obj_t dict_view_binary_op(mp_uint_t op, mp_obj_t lhs_in, mp_obj_t rhs_in) {
+STATIC mp_obj_t dict_view_binary_op(mp_binary_op_t op, mp_obj_t lhs_in, mp_obj_t rhs_in) {
     // only supported for the 'keys' kind until sets and dicts are refactored
     mp_obj_dict_view_t *o = MP_OBJ_TO_PTR(lhs_in);
     if (o->kind != MP_DICT_VIEW_KEYS) {
diff --git a/py/objexcept.c b/py/objexcept.c
index 58ae583199..4844c7f92d 100644
--- a/py/objexcept.c
+++ b/py/objexcept.c
@@ -29,7 +29,6 @@
 #include <assert.h>
 #include <stdio.h>
 
-#include "py/mpstate.h"
 #include "py/objlist.h"
 #include "py/objstr.h"
 #include "py/objtuple.h"
@@ -38,6 +37,12 @@
 #include "py/gc.h"
 #include "py/mperrno.h"
 
+// Number of items per traceback entry (file, line, block)
+#define TRACEBACK_ENTRY_LEN (3)
+
+// Number of traceback entries to reserve in the emergency exception buffer
+#define EMG_TRACEBACK_ALLOC (2 * TRACEBACK_ENTRY_LEN)
+
 // Instance of MemoryError exception - needed by mp_malloc_fail
 const mp_obj_exception_t mp_const_MemoryError_obj = {{&mp_type_MemoryError}, 0, 0, NULL, (mp_obj_tuple_t*)&mp_const_empty_tuple_obj};
 
@@ -127,18 +132,51 @@ STATIC void mp_obj_exception_print(const mp_print_t *print, mp_obj_t o_in, mp_pr
 
 mp_obj_t mp_obj_exception_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args) {
     mp_arg_check_num(n_args, n_kw, 0, MP_OBJ_FUN_ARGS_MAX, false);
-    mp_obj_exception_t *o = m_new_obj_var_maybe(mp_obj_exception_t, mp_obj_t, 0);
-    if (o == NULL) {
-        // Couldn't allocate heap memory; use local data instead.
-        o = &MP_STATE_VM(mp_emergency_exception_obj);
-        // We can't store any args.
-        o->args = (mp_obj_tuple_t*)&mp_const_empty_tuple_obj;
-    } else {
-        o->args = MP_OBJ_TO_PTR(mp_obj_new_tuple(n_args, args));
+
+    // Try to allocate memory for the exception, with fallback to emergency exception object
+    mp_obj_exception_t *o_exc = m_new_obj_maybe(mp_obj_exception_t);
+    if (o_exc == NULL) {
+        o_exc = &MP_STATE_VM(mp_emergency_exception_obj);
     }
-    o->base.type = type;
-    o->traceback_data = NULL;
-    return MP_OBJ_FROM_PTR(o);
+
+    // Populate the exception object
+    o_exc->base.type = type;
+    o_exc->traceback_data = NULL;
+
+    mp_obj_tuple_t *o_tuple;
+    if (n_args == 0) {
+        // No args, can use the empty tuple straightaway
+        o_tuple = (mp_obj_tuple_t*)&mp_const_empty_tuple_obj;
+    } else {
+        // Try to allocate memory for the tuple containing the args
+        o_tuple = m_new_obj_var_maybe(mp_obj_tuple_t, mp_obj_t, n_args);
+
+        #if MICROPY_ENABLE_EMERGENCY_EXCEPTION_BUF
+        // If we are called by mp_obj_new_exception_msg_varg then it will have
+        // reserved room (after the traceback data) for a tuple with 1 element.
+        // Otherwise we are free to use the whole buffer after the traceback data.
+        if (o_tuple == NULL && mp_emergency_exception_buf_size >=
+            EMG_TRACEBACK_ALLOC * sizeof(size_t) + sizeof(mp_obj_tuple_t) + n_args * sizeof(mp_obj_t)) {
+            o_tuple = (mp_obj_tuple_t*)
+                ((uint8_t*)MP_STATE_VM(mp_emergency_exception_buf) + EMG_TRACEBACK_ALLOC * sizeof(size_t));
+        }
+        #endif
+
+        if (o_tuple == NULL) {
+            // No memory for a tuple, fallback to an empty tuple
+            o_tuple = (mp_obj_tuple_t*)&mp_const_empty_tuple_obj;
+        } else {
+            // Have memory for a tuple so populate it
+            o_tuple->base.type = &mp_type_tuple;
+            o_tuple->len = n_args;
+            memcpy(o_tuple->items, args, n_args * sizeof(mp_obj_t));
+        }
+    }
+
+    // Store the tuple of args in the exception object
+    o_exc->args = o_tuple;
+
+    return MP_OBJ_FROM_PTR(o_exc);
 }
 
 // Get exception "value" - that is, first argument, or None
@@ -306,6 +344,40 @@ mp_obj_t mp_obj_new_exception_msg(const mp_obj_type_t *exc_type, const char *msg
     return mp_obj_new_exception_msg_varg(exc_type, msg);
 }
 
+// The following struct and function implement a simple printer that conservatively
+// allocates memory and truncates the output data if no more memory can be obtained.
+// It leaves room for a null byte at the end of the buffer.
+
+struct _exc_printer_t {
+    bool allow_realloc;
+    size_t alloc;
+    size_t len;
+    byte *buf;
+};
+
+STATIC void exc_add_strn(void *data, const char *str, size_t len) {
+    struct _exc_printer_t *pr = data;
+    if (pr->len + len >= pr->alloc) {
+        // Not enough room for data plus a null byte so try to grow the buffer
+        if (pr->allow_realloc) {
+            size_t new_alloc = pr->alloc + len + 16;
+            byte *new_buf = m_renew_maybe(byte, pr->buf, pr->alloc, new_alloc, true);
+            if (new_buf == NULL) {
+                pr->allow_realloc = false;
+                len = pr->alloc - pr->len - 1;
+            } else {
+                pr->alloc = new_alloc;
+                pr->buf = new_buf;
+            }
+        } else {
+            len = pr->alloc - pr->len - 1;
+        }
+    }
+    memcpy(pr->buf + pr->len, str, len);
+    pr->len += len;
+}
+
+
 mp_obj_t mp_obj_new_exception_msg_varg(const mp_obj_type_t *exc_type, const char *fmt, ...) {
     va_list ap;
     va_start(ap, fmt);
@@ -315,80 +387,58 @@ mp_obj_t mp_obj_new_exception_msg_varg(const mp_obj_type_t *exc_type, const char
 }
 
 mp_obj_t mp_obj_new_exception_msg_vlist(const mp_obj_type_t *exc_type, const char *fmt, va_list ap) {
-    // check that the given type is an exception type
+    assert(fmt != NULL);
+
+    // Check that the given type is an exception type
     assert(exc_type->make_new == mp_obj_exception_make_new);
 
-    // make exception object
-    mp_obj_exception_t *o = m_new_obj_var_maybe(mp_obj_exception_t, mp_obj_t, 0);
-    if (o == NULL) {
-        // Couldn't allocate heap memory; use local data instead.
-        // Unfortunately, we won't be able to format the string...
-        o = &MP_STATE_VM(mp_emergency_exception_obj);
-        o->base.type = exc_type;
-        o->traceback_data = NULL;
-        o->args = (mp_obj_tuple_t*)&mp_const_empty_tuple_obj;
+    // Try to allocate memory for the message
+    mp_obj_str_t *o_str = m_new_obj_maybe(mp_obj_str_t);
+    size_t o_str_alloc = strlen(fmt) + 1;
+    byte *o_str_buf = m_new_maybe(byte, o_str_alloc);
 
-#if MICROPY_ENABLE_EMERGENCY_EXCEPTION_BUF
-        // If the user has provided a buffer, then we try to create a tuple
-        // of length 1, which has a string object and the string data.
+    bool used_emg_buf = false;
+    #if MICROPY_ENABLE_EMERGENCY_EXCEPTION_BUF
+    // If memory allocation failed and there is an emergency buffer then try to use
+    // that buffer to store the string object and its data (at least 16 bytes for
+    // the string data), reserving room at the start for the traceback and 1-tuple.
+    if ((o_str == NULL || o_str_buf == NULL)
+        && mp_emergency_exception_buf_size >= EMG_TRACEBACK_ALLOC * sizeof(size_t)
+            + sizeof(mp_obj_tuple_t) + sizeof(mp_obj_t) + sizeof(mp_obj_str_t) + 16) {
+        used_emg_buf = true;
+        o_str = (mp_obj_str_t*)((uint8_t*)MP_STATE_VM(mp_emergency_exception_buf)
+            + EMG_TRACEBACK_ALLOC * sizeof(size_t) + sizeof(mp_obj_tuple_t) + sizeof(mp_obj_t));
+        o_str_buf = (byte*)&o_str[1];
+        o_str_alloc = (uint8_t*)MP_STATE_VM(mp_emergency_exception_buf)
+            + mp_emergency_exception_buf_size - o_str_buf;
+    }
+    #endif
 
-        if (mp_emergency_exception_buf_size > (sizeof(mp_obj_tuple_t) + sizeof(mp_obj_str_t) + sizeof(mp_obj_t))) {
-            mp_obj_tuple_t *tuple = (mp_obj_tuple_t *)MP_STATE_VM(mp_emergency_exception_buf);
-            mp_obj_str_t *str = (mp_obj_str_t *)&tuple->items[1];
-
-            tuple->base.type = &mp_type_tuple;
-            tuple->len = 1;
-            tuple->items[0] = MP_OBJ_FROM_PTR(str);
-
-            byte *str_data = (byte *)&str[1];
-            size_t max_len = (byte*)MP_STATE_VM(mp_emergency_exception_buf) + mp_emergency_exception_buf_size
-                         - str_data;
-
-            vstr_t vstr;
-            vstr_init_fixed_buf(&vstr, max_len, (char *)str_data);
-
-            vstr_vprintf(&vstr, fmt, ap);
-
-            str->base.type = &mp_type_str;
-            str->hash = qstr_compute_hash(str_data, str->len);
-            str->len = vstr.len;
-            str->data = str_data;
-
-            o->args = tuple;
-
-            size_t offset = &str_data[str->len] - (byte*)MP_STATE_VM(mp_emergency_exception_buf);
-            offset += sizeof(void *) - 1;
-            offset &= ~(sizeof(void *) - 1);
-
-            if ((mp_emergency_exception_buf_size - offset) > (sizeof(o->traceback_data[0]) * 3)) {
-                // We have room to store some traceback.
-                o->traceback_data = (size_t*)((byte *)MP_STATE_VM(mp_emergency_exception_buf) + offset);
-                o->traceback_alloc = ((byte*)MP_STATE_VM(mp_emergency_exception_buf) + mp_emergency_exception_buf_size - (byte *)o->traceback_data) / sizeof(o->traceback_data[0]);
-                o->traceback_len = 0;
-            }
-        }
-#endif // MICROPY_ENABLE_EMERGENCY_EXCEPTION_BUF
-    } else {
-        o->base.type = exc_type;
-        o->traceback_data = NULL;
-        o->args = MP_OBJ_TO_PTR(mp_obj_new_tuple(1, NULL));
-
-        assert(fmt != NULL);
-        {
-            if (strchr(fmt, '%') == NULL) {
-                // no formatting substitutions, avoid allocating vstr.
-                o->args->items[0] = mp_obj_new_str(fmt, strlen(fmt), false);
-            } else {
-                // render exception message and store as .args[0]
-                vstr_t vstr;
-                vstr_init(&vstr, 16);
-                vstr_vprintf(&vstr, fmt, ap);
-                o->args->items[0] = mp_obj_new_str_from_vstr(&mp_type_str, &vstr);
-            }
-        }
+    if (o_str == NULL) {
+        // No memory for the string object so create the exception with no args
+        return mp_obj_exception_make_new(exc_type, 0, 0, NULL);
     }
 
-    return MP_OBJ_FROM_PTR(o);
+    if (o_str_buf == NULL) {
+        // No memory for the string buffer: assume that the fmt string is in ROM
+        // and use that data as the data of the string
+        o_str->len = o_str_alloc - 1; // will be equal to strlen(fmt)
+        o_str->data = (const byte*)fmt;
+    } else {
+        // We have some memory to format the string
+        struct _exc_printer_t exc_pr = {!used_emg_buf, o_str_alloc, 0, o_str_buf};
+        mp_print_t print = {&exc_pr, exc_add_strn};
+        mp_vprintf(&print, fmt, ap);
+        exc_pr.buf[exc_pr.len] = '\0';
+        o_str->len = exc_pr.len;
+        o_str->data = exc_pr.buf;
+    }
+
+    // Create the string object and call mp_obj_exception_make_new to create the exception
+    o_str->base.type = &mp_type_str;
+    o_str->hash = qstr_compute_hash(o_str->data, o_str->len);
+    mp_obj_t arg = MP_OBJ_FROM_PTR(o_str);
+    return mp_obj_exception_make_new(exc_type, 1, 0, &arg);
 }
 
 // return true if the given object is an exception type
@@ -445,24 +495,46 @@ void mp_obj_exception_add_traceback(mp_obj_t self_in, qstr file, size_t line, qs
     // if memory allocation fails (eg because gc is locked), just return
 
     if (self->traceback_data == NULL) {
-        self->traceback_data = m_new_maybe(size_t, 3);
+        self->traceback_data = m_new_maybe(size_t, TRACEBACK_ENTRY_LEN);
         if (self->traceback_data == NULL) {
+            #if MICROPY_ENABLE_EMERGENCY_EXCEPTION_BUF
+            if (mp_emergency_exception_buf_size >= EMG_TRACEBACK_ALLOC * sizeof(size_t)) {
+                // There is room in the emergency buffer for traceback data
+                size_t *tb = (size_t*)MP_STATE_VM(mp_emergency_exception_buf);
+                self->traceback_data = tb;
+                self->traceback_alloc = EMG_TRACEBACK_ALLOC;
+            } else {
+                // Can't allocate and no room in emergency buffer
+                return;
+            }
+            #else
+            // Can't allocate
+            return;
+            #endif
+        } else {
+            // Allocated the traceback data on the heap
+            self->traceback_alloc = TRACEBACK_ENTRY_LEN;
+        }
+        self->traceback_len = 0;
+    } else if (self->traceback_len + TRACEBACK_ENTRY_LEN > self->traceback_alloc) {
+        #if MICROPY_ENABLE_EMERGENCY_EXCEPTION_BUF
+        if (self->traceback_data == (size_t*)MP_STATE_VM(mp_emergency_exception_buf)) {
+            // Can't resize the emergency buffer
             return;
         }
-        self->traceback_alloc = 3;
-        self->traceback_len = 0;
-    } else if (self->traceback_len + 3 > self->traceback_alloc) {
+        #endif
         // be conservative with growing traceback data
-        size_t *tb_data = m_renew_maybe(size_t, self->traceback_data, self->traceback_alloc, self->traceback_alloc + 3, true);
+        size_t *tb_data = m_renew_maybe(size_t, self->traceback_data, self->traceback_alloc,
+            self->traceback_alloc + TRACEBACK_ENTRY_LEN, true);
         if (tb_data == NULL) {
             return;
         }
         self->traceback_data = tb_data;
-        self->traceback_alloc += 3;
+        self->traceback_alloc += TRACEBACK_ENTRY_LEN;
     }
 
     size_t *tb_data = &self->traceback_data[self->traceback_len];
-    self->traceback_len += 3;
+    self->traceback_len += TRACEBACK_ENTRY_LEN;
     tb_data[0] = file;
     tb_data[1] = line;
     tb_data[2] = block;
diff --git a/py/objfloat.c b/py/objfloat.c
index 668e7536f4..fde2224ad4 100644
--- a/py/objfloat.c
+++ b/py/objfloat.c
@@ -29,9 +29,7 @@
 #include <string.h>
 #include <assert.h>
 
-#include "py/nlr.h"
 #include "py/parsenum.h"
-#include "py/runtime0.h"
 #include "py/runtime.h"
 
 #if MICROPY_PY_BUILTINS_FLOAT
@@ -158,18 +156,26 @@ STATIC mp_obj_t float_make_new(const mp_obj_type_t *type_in, size_t n_args, size
     }
 }
 
-STATIC mp_obj_t float_unary_op(mp_uint_t op, mp_obj_t o_in) {
+STATIC mp_obj_t float_unary_op(mp_unary_op_t op, mp_obj_t o_in) {
     mp_float_t val = mp_obj_float_get(o_in);
     switch (op) {
         case MP_UNARY_OP_BOOL: return mp_obj_new_bool(val != 0);
         case MP_UNARY_OP_HASH: return MP_OBJ_NEW_SMALL_INT(mp_float_hash(val));
         case MP_UNARY_OP_POSITIVE: return o_in;
         case MP_UNARY_OP_NEGATIVE: return mp_obj_new_float(-val);
+        case MP_UNARY_OP_ABS: {
+            // TODO check for NaN etc
+            if (val < 0) {
+                return mp_obj_new_float(-val);
+            } else {
+                return o_in;
+            }
+        }
         default: return MP_OBJ_NULL; // op not supported
     }
 }
 
-STATIC mp_obj_t float_binary_op(mp_uint_t op, mp_obj_t lhs_in, mp_obj_t rhs_in) {
+STATIC mp_obj_t float_binary_op(mp_binary_op_t op, mp_obj_t lhs_in, mp_obj_t rhs_in) {
     mp_float_t lhs_val = mp_obj_float_get(lhs_in);
 #if MICROPY_PY_BUILTINS_COMPLEX
     if (MP_OBJ_IS_TYPE(rhs_in, &mp_type_complex)) {
@@ -242,8 +248,12 @@ STATIC void mp_obj_float_divmod(mp_float_t *x, mp_float_t *y) {
     *y = mod;
 }
 
-mp_obj_t mp_obj_float_binary_op(mp_uint_t op, mp_float_t lhs_val, mp_obj_t rhs_in) {
-    mp_float_t rhs_val = mp_obj_get_float(rhs_in); // can be any type, this function will convert to float (if possible)
+mp_obj_t mp_obj_float_binary_op(mp_binary_op_t op, mp_float_t lhs_val, mp_obj_t rhs_in) {
+    mp_float_t rhs_val;
+    if (!mp_obj_get_float_maybe(rhs_in, &rhs_val)) {
+        return MP_OBJ_NULL; // op not supported
+    }
+
     switch (op) {
         case MP_BINARY_OP_ADD:
         case MP_BINARY_OP_INPLACE_ADD: lhs_val += rhs_val; break;
@@ -289,6 +299,13 @@ mp_obj_t mp_obj_float_binary_op(mp_uint_t op, mp_float_t lhs_val, mp_obj_t rhs_i
             if (lhs_val == 0 && rhs_val < 0) {
                 goto zero_division_error;
             }
+            if (lhs_val < 0 && rhs_val != MICROPY_FLOAT_C_FUN(floor)(rhs_val)) {
+                #if MICROPY_PY_BUILTINS_COMPLEX
+                return mp_obj_complex_binary_op(MP_BINARY_OP_POWER, lhs_val, 0, rhs_in);
+                #else
+                mp_raise_ValueError("complex values not supported");
+                #endif
+            }
             lhs_val = MICROPY_FLOAT_C_FUN(pow)(lhs_val, rhs_val);
             break;
         case MP_BINARY_OP_DIVMOD: {
diff --git a/py/objfun.c b/py/objfun.c
index 5606511d8a..030b3f7cb0 100644
--- a/py/objfun.c
+++ b/py/objfun.c
@@ -28,10 +28,8 @@
 #include <string.h>
 #include <assert.h>
 
-#include "py/nlr.h"
 #include "py/objtuple.h"
 #include "py/objfun.h"
-#include "py/runtime0.h"
 #include "py/runtime.h"
 #include "py/bc.h"
 #include "py/stackctrl.h"
diff --git a/py/objgenerator.c b/py/objgenerator.c
index f777224512..1394524421 100644
--- a/py/objgenerator.c
+++ b/py/objgenerator.c
@@ -28,8 +28,6 @@
 #include <stdlib.h>
 #include <assert.h>
 
-#include "py/nlr.h"
-#include "py/obj.h"
 #include "py/runtime.h"
 #include "py/bc.h"
 #include "py/objgenerator.h"
diff --git a/py/objgetitemiter.c b/py/objgetitemiter.c
index afd6fb22b0..ec41c2c5b1 100644
--- a/py/objgetitemiter.c
+++ b/py/objgetitemiter.c
@@ -26,7 +26,6 @@
 
 #include <stdlib.h>
 
-#include "py/nlr.h"
 #include "py/runtime.h"
 
 // this is a wrapper object that turns something that has a __getitem__ method into an iterator
diff --git a/py/objint.c b/py/objint.c
index 29d889629f..4f2e610a50 100644
--- a/py/objint.c
+++ b/py/objint.c
@@ -28,12 +28,10 @@
 #include <assert.h>
 #include <string.h>
 
-#include "py/nlr.h"
 #include "py/parsenum.h"
 #include "py/smallint.h"
 #include "py/objint.h"
 #include "py/objstr.h"
-#include "py/runtime0.h"
 #include "py/runtime.h"
 #include "py/binary.h"
 
@@ -314,23 +312,13 @@ int mp_obj_int_sign(mp_obj_t self_in) {
     }
 }
 
-// This must handle int and bool types, and must raise a
-// TypeError if the argument is not integral
-mp_obj_t mp_obj_int_abs(mp_obj_t self_in) {
-    mp_int_t val = mp_obj_get_int(self_in);
-    if (val < 0) {
-        val = -val;
-    }
-    return MP_OBJ_NEW_SMALL_INT(val);
-}
-
 // This is called for operations on SMALL_INT that are not handled by mp_unary_op
-mp_obj_t mp_obj_int_unary_op(mp_uint_t op, mp_obj_t o_in) {
+mp_obj_t mp_obj_int_unary_op(mp_unary_op_t op, mp_obj_t o_in) {
     return MP_OBJ_NULL; // op not supported
 }
 
 // This is called for operations on SMALL_INT that are not handled by mp_binary_op
-mp_obj_t mp_obj_int_binary_op(mp_uint_t op, mp_obj_t lhs_in, mp_obj_t rhs_in) {
+mp_obj_t mp_obj_int_binary_op(mp_binary_op_t op, mp_obj_t lhs_in, mp_obj_t rhs_in) {
     return mp_obj_int_binary_op_extra_cases(op, lhs_in, rhs_in);
 }
 
@@ -382,7 +370,7 @@ mp_int_t mp_obj_int_get_checked(mp_const_obj_t self_in) {
 
 // This dispatcher function is expected to be independent of the implementation of long int
 // It handles the extra cases for integer-like arithmetic
-mp_obj_t mp_obj_int_binary_op_extra_cases(mp_uint_t op, mp_obj_t lhs_in, mp_obj_t rhs_in) {
+mp_obj_t mp_obj_int_binary_op_extra_cases(mp_binary_op_t op, mp_obj_t lhs_in, mp_obj_t rhs_in) {
     if (rhs_in == mp_const_false) {
         // false acts as 0
         return mp_binary_op(op, lhs_in, MP_OBJ_NEW_SMALL_INT(0));
diff --git a/py/objint.h b/py/objint.h
index 394c23714b..4b95acde9f 100644
--- a/py/objint.h
+++ b/py/objint.h
@@ -57,10 +57,9 @@ mp_int_t mp_obj_int_hash(mp_obj_t self_in);
 mp_obj_t mp_obj_int_from_bytes_impl(bool big_endian, size_t len, const byte *buf);
 void mp_obj_int_to_bytes_impl(mp_obj_t self_in, bool big_endian, size_t len, byte *buf);
 int mp_obj_int_sign(mp_obj_t self_in);
-mp_obj_t mp_obj_int_abs(mp_obj_t self_in);
-mp_obj_t mp_obj_int_unary_op(mp_uint_t op, mp_obj_t o_in);
-mp_obj_t mp_obj_int_binary_op(mp_uint_t op, mp_obj_t lhs_in, mp_obj_t rhs_in);
-mp_obj_t mp_obj_int_binary_op_extra_cases(mp_uint_t op, mp_obj_t lhs_in, mp_obj_t rhs_in);
+mp_obj_t mp_obj_int_unary_op(mp_unary_op_t op, mp_obj_t o_in);
+mp_obj_t mp_obj_int_binary_op(mp_binary_op_t op, mp_obj_t lhs_in, mp_obj_t rhs_in);
+mp_obj_t mp_obj_int_binary_op_extra_cases(mp_binary_op_t op, mp_obj_t lhs_in, mp_obj_t rhs_in);
 mp_obj_t mp_obj_int_pow3(mp_obj_t base, mp_obj_t exponent,  mp_obj_t modulus);
 
 #endif // MICROPY_INCLUDED_PY_OBJINT_H
diff --git a/py/objint_longlong.c b/py/objint_longlong.c
index 02c005d2fd..2e567c5721 100644
--- a/py/objint_longlong.c
+++ b/py/objint_longlong.c
@@ -28,10 +28,8 @@
 #include <stdlib.h>
 #include <string.h>
 
-#include "py/nlr.h"
 #include "py/smallint.h"
 #include "py/objint.h"
-#include "py/runtime0.h"
 #include "py/runtime.h"
 
 #if MICROPY_PY_BUILTINS_FLOAT
@@ -94,31 +92,7 @@ int mp_obj_int_sign(mp_obj_t self_in) {
     }
 }
 
-// This must handle int and bool types, and must raise a
-// TypeError if the argument is not integral
-mp_obj_t mp_obj_int_abs(mp_obj_t self_in) {
-    if (MP_OBJ_IS_TYPE(self_in, &mp_type_int)) {
-        mp_obj_int_t *self = self_in;
-        self = mp_obj_new_int_from_ll(self->val);
-        if (self->val < 0) {
-            // TODO could overflow long long
-            self->val = -self->val;
-        }
-        return self;
-    } else {
-        mp_int_t val = mp_obj_get_int(self_in);
-        if (val == MP_SMALL_INT_MIN) {
-            return mp_obj_new_int_from_ll(-val);
-        } else {
-            if (val < 0) {
-                val = -val;
-            }
-            return MP_OBJ_NEW_SMALL_INT(val);
-        }
-    }
-}
-
-mp_obj_t mp_obj_int_unary_op(mp_uint_t op, mp_obj_t o_in) {
+mp_obj_t mp_obj_int_unary_op(mp_unary_op_t op, mp_obj_t o_in) {
     mp_obj_int_t *o = o_in;
     switch (op) {
         case MP_UNARY_OP_BOOL: return mp_obj_new_bool(o->val != 0);
@@ -130,11 +104,21 @@ mp_obj_t mp_obj_int_unary_op(mp_uint_t op, mp_obj_t o_in) {
         case MP_UNARY_OP_POSITIVE: return o_in;
         case MP_UNARY_OP_NEGATIVE: return mp_obj_new_int_from_ll(-o->val);
         case MP_UNARY_OP_INVERT: return mp_obj_new_int_from_ll(~o->val);
+        case MP_UNARY_OP_ABS: {
+            mp_obj_int_t *self = MP_OBJ_TO_PTR(o_in);
+            if (self->val >= 0) {
+                return o_in;
+            }
+            self = mp_obj_new_int_from_ll(self->val);
+            // TODO could overflow long long
+            self->val = -self->val;
+            return MP_OBJ_FROM_PTR(self);
+        }
         default: return MP_OBJ_NULL; // op not supported
     }
 }
 
-mp_obj_t mp_obj_int_binary_op(mp_uint_t op, mp_obj_t lhs_in, mp_obj_t rhs_in) {
+mp_obj_t mp_obj_int_binary_op(mp_binary_op_t op, mp_obj_t lhs_in, mp_obj_t rhs_in) {
     long long lhs_val;
     long long rhs_val;
 
diff --git a/py/objint_mpz.c b/py/objint_mpz.c
index 0791a8af2c..7b5cb0b9d4 100644
--- a/py/objint_mpz.c
+++ b/py/objint_mpz.c
@@ -28,11 +28,9 @@
 #include <stdio.h>
 #include <assert.h>
 
-#include "py/nlr.h"
 #include "py/parsenumbase.h"
 #include "py/smallint.h"
 #include "py/objint.h"
-#include "py/runtime0.h"
 #include "py/runtime.h"
 
 #if MICROPY_PY_BUILTINS_FLOAT
@@ -141,28 +139,7 @@ int mp_obj_int_sign(mp_obj_t self_in) {
     }
 }
 
-// This must handle int and bool types, and must raise a
-// TypeError if the argument is not integral
-mp_obj_t mp_obj_int_abs(mp_obj_t self_in) {
-    if (MP_OBJ_IS_TYPE(self_in, &mp_type_int)) {
-        mp_obj_int_t *self = MP_OBJ_TO_PTR(self_in);
-        mp_obj_int_t *self2 = mp_obj_int_new_mpz();
-        mpz_abs_inpl(&self2->mpz, &self->mpz);
-        return MP_OBJ_FROM_PTR(self2);
-    } else {
-        mp_int_t val = mp_obj_get_int(self_in);
-        if (val == MP_SMALL_INT_MIN) {
-            return mp_obj_new_int_from_ll(-val);
-        } else {
-            if (val < 0) {
-                val = -val;
-            }
-            return MP_OBJ_NEW_SMALL_INT(val);
-        }
-    }
-}
-
-mp_obj_t mp_obj_int_unary_op(mp_uint_t op, mp_obj_t o_in) {
+mp_obj_t mp_obj_int_unary_op(mp_unary_op_t op, mp_obj_t o_in) {
     mp_obj_int_t *o = MP_OBJ_TO_PTR(o_in);
     switch (op) {
         case MP_UNARY_OP_BOOL: return mp_obj_new_bool(!mpz_is_zero(&o->mpz));
@@ -170,11 +147,20 @@ mp_obj_t mp_obj_int_unary_op(mp_uint_t op, mp_obj_t o_in) {
         case MP_UNARY_OP_POSITIVE: return o_in;
         case MP_UNARY_OP_NEGATIVE: { mp_obj_int_t *o2 = mp_obj_int_new_mpz(); mpz_neg_inpl(&o2->mpz, &o->mpz); return MP_OBJ_FROM_PTR(o2); }
         case MP_UNARY_OP_INVERT: { mp_obj_int_t *o2 = mp_obj_int_new_mpz(); mpz_not_inpl(&o2->mpz, &o->mpz); return MP_OBJ_FROM_PTR(o2); }
+        case MP_UNARY_OP_ABS: {
+            mp_obj_int_t *self = MP_OBJ_TO_PTR(o_in);
+            if (self->mpz.neg == 0) {
+                return o_in;
+            }
+            mp_obj_int_t *self2 = mp_obj_int_new_mpz();
+            mpz_abs_inpl(&self2->mpz, &self->mpz);
+            return MP_OBJ_FROM_PTR(self2);
+        }
         default: return MP_OBJ_NULL; // op not supported
     }
 }
 
-mp_obj_t mp_obj_int_binary_op(mp_uint_t op, mp_obj_t lhs_in, mp_obj_t rhs_in) {
+mp_obj_t mp_obj_int_binary_op(mp_binary_op_t op, mp_obj_t lhs_in, mp_obj_t rhs_in) {
     const mpz_t *zlhs;
     const mpz_t *zrhs;
     mpz_t z_int;
@@ -221,7 +207,7 @@ mp_obj_t mp_obj_int_binary_op(mp_uint_t op, mp_obj_t lhs_in, mp_obj_t rhs_in) {
         return mp_obj_new_float(flhs / frhs);
 #endif
 
-    } else if (op <= MP_BINARY_OP_INPLACE_POWER) {
+    } else if (op >= MP_BINARY_OP_INPLACE_OR) {
         mp_obj_int_t *res = mp_obj_int_new_mpz();
 
         switch (op) {
diff --git a/py/objlist.c b/py/objlist.c
index 212240c768..c6e85f2c87 100644
--- a/py/objlist.c
+++ b/py/objlist.c
@@ -27,9 +27,7 @@
 #include <string.h>
 #include <assert.h>
 
-#include "py/nlr.h"
 #include "py/objlist.h"
-#include "py/runtime0.h"
 #include "py/runtime.h"
 #include "py/stackctrl.h"
 
@@ -87,19 +85,7 @@ STATIC mp_obj_t list_make_new(const mp_obj_type_t *type_in, size_t n_args, size_
     }
 }
 
-// Don't pass MP_BINARY_OP_NOT_EQUAL here
-STATIC bool list_cmp_helper(mp_uint_t op, mp_obj_t self_in, mp_obj_t another_in) {
-    mp_check_self(MP_OBJ_IS_TYPE(self_in, &mp_type_list));
-    if (!MP_OBJ_IS_TYPE(another_in, &mp_type_list)) {
-        return false;
-    }
-    mp_obj_list_t *self = MP_OBJ_TO_PTR(self_in);
-    mp_obj_list_t *another = MP_OBJ_TO_PTR(another_in);
-
-    return mp_seq_cmp_objs(op, self->items, self->len, another->items, another->len);
-}
-
-STATIC mp_obj_t list_unary_op(mp_uint_t op, mp_obj_t self_in) {
+STATIC mp_obj_t list_unary_op(mp_unary_op_t op, mp_obj_t self_in) {
     mp_obj_list_t *self = MP_OBJ_TO_PTR(self_in);
     switch (op) {
         case MP_UNARY_OP_BOOL: return mp_obj_new_bool(self->len != 0);
@@ -114,7 +100,7 @@ STATIC mp_obj_t list_unary_op(mp_uint_t op, mp_obj_t self_in) {
     }
 }
 
-STATIC mp_obj_t list_binary_op(mp_uint_t op, mp_obj_t lhs, mp_obj_t rhs) {
+STATIC mp_obj_t list_binary_op(mp_binary_op_t op, mp_obj_t lhs, mp_obj_t rhs) {
     mp_obj_list_t *o = MP_OBJ_TO_PTR(lhs);
     switch (op) {
         case MP_BINARY_OP_ADD: {
@@ -146,8 +132,18 @@ STATIC mp_obj_t list_binary_op(mp_uint_t op, mp_obj_t lhs, mp_obj_t rhs) {
         case MP_BINARY_OP_LESS:
         case MP_BINARY_OP_LESS_EQUAL:
         case MP_BINARY_OP_MORE:
-        case MP_BINARY_OP_MORE_EQUAL:
-            return mp_obj_new_bool(list_cmp_helper(op, lhs, rhs));
+        case MP_BINARY_OP_MORE_EQUAL: {
+            if (!MP_OBJ_IS_TYPE(rhs, &mp_type_list)) {
+                if (op == MP_BINARY_OP_EQUAL) {
+                    return mp_const_false;
+                }
+                return MP_OBJ_NULL; // op not supported
+            }
+
+            mp_obj_list_t *another = MP_OBJ_TO_PTR(rhs);
+            bool res = mp_seq_cmp_objs(op, o->items, o->len, another->items, another->len);
+            return mp_obj_new_bool(res);
+        }
 
         default:
             return MP_OBJ_NULL; // op not supported
diff --git a/py/objmodule.c b/py/objmodule.c
index 212973b195..52c6520b9d 100644
--- a/py/objmodule.c
+++ b/py/objmodule.c
@@ -27,8 +27,6 @@
 #include <stdlib.h>
 #include <assert.h>
 
-#include "py/mpstate.h"
-#include "py/nlr.h"
 #include "py/objmodule.h"
 #include "py/runtime.h"
 #include "py/builtin.h"
diff --git a/py/objnone.c b/py/objnone.c
index cd7319bec8..da1031835c 100644
--- a/py/objnone.c
+++ b/py/objnone.c
@@ -26,9 +26,7 @@
 
 #include <stdlib.h>
 
-#include "py/nlr.h"
 #include "py/obj.h"
-#include "py/runtime0.h"
 
 typedef struct _mp_obj_none_t {
     mp_obj_base_t base;
diff --git a/py/objpolyiter.c b/py/objpolyiter.c
index 61bd1e0ac2..01880bff9c 100644
--- a/py/objpolyiter.c
+++ b/py/objpolyiter.c
@@ -26,7 +26,6 @@
 
 #include <stdlib.h>
 
-#include "py/nlr.h"
 #include "py/runtime.h"
 
 // This is universal iterator type which calls "iternext" method stored in
diff --git a/py/objrange.c b/py/objrange.c
index 33b07a9d44..3874adb11c 100644
--- a/py/objrange.c
+++ b/py/objrange.c
@@ -26,8 +26,6 @@
 
 #include <stdlib.h>
 
-#include "py/nlr.h"
-#include "py/runtime0.h"
 #include "py/runtime.h"
 
 /******************************************************************************/
@@ -130,7 +128,7 @@ STATIC mp_int_t range_len(mp_obj_range_t *self) {
     return len;
 }
 
-STATIC mp_obj_t range_unary_op(mp_uint_t op, mp_obj_t self_in) {
+STATIC mp_obj_t range_unary_op(mp_unary_op_t op, mp_obj_t self_in) {
     mp_obj_range_t *self = MP_OBJ_TO_PTR(self_in);
     mp_int_t len = range_len(self);
     switch (op) {
diff --git a/py/objreversed.c b/py/objreversed.c
index a596a2fde3..e498b553de 100644
--- a/py/objreversed.c
+++ b/py/objreversed.c
@@ -27,7 +27,6 @@
 #include <stdlib.h>
 #include <assert.h>
 
-#include "py/nlr.h"
 #include "py/runtime.h"
 
 #if MICROPY_PY_BUILTINS_REVERSED
diff --git a/py/objset.c b/py/objset.c
index 29bdb69def..6ed15c7914 100644
--- a/py/objset.c
+++ b/py/objset.c
@@ -3,7 +3,7 @@
  *
  * The MIT License (MIT)
  *
- * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2013-2017 Damien P. George
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -28,9 +28,7 @@
 #include <string.h>
 #include <assert.h>
 
-#include "py/nlr.h"
 #include "py/runtime.h"
-#include "py/runtime0.h"
 #include "py/builtin.h"
 
 #if MICROPY_PY_BUILTINS_SET
@@ -57,23 +55,13 @@ STATIC bool is_set_or_frozenset(mp_obj_t o) {
     ;
 }
 
+// This macro is shorthand for mp_check_self to verify the argument is a set.
+#define check_set(o) mp_check_self(MP_OBJ_IS_TYPE(o, &mp_type_set))
+
 // This macro is shorthand for mp_check_self to verify the argument is a
 // set or frozenset for methods that operate on both of these types.
 #define check_set_or_frozenset(o) mp_check_self(is_set_or_frozenset(o))
 
-// This function is used to verify the argument for methods that modify
-// the set object, and raises an exception if the arg is a frozenset.
-STATIC void check_set(mp_obj_t o) {
-    #if MICROPY_PY_BUILTINS_FROZENSET
-    if (MP_OBJ_IS_TYPE(o, &mp_type_frozenset)) {
-        // Mutable method called on frozenset; emulate CPython behavior, eg:
-        // AttributeError: 'frozenset' object has no attribute 'add'
-        mp_raise_AttributeError("'frozenset' has no such attribute");
-    }
-    #endif
-    mp_check_self(MP_OBJ_IS_TYPE(o, &mp_type_set));
-}
-
 STATIC void set_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) {
     (void)kind;
     mp_obj_set_t *self = MP_OBJ_TO_PTR(self_in);
@@ -188,26 +176,16 @@ STATIC mp_obj_t set_clear(mp_obj_t self_in) {
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_1(set_clear_obj, set_clear);
 
-STATIC mp_obj_t set_copy_as_mutable(mp_obj_t self_in) {
+STATIC mp_obj_t set_copy(mp_obj_t self_in) {
+    check_set_or_frozenset(self_in);
     mp_obj_set_t *self = MP_OBJ_TO_PTR(self_in);
-
     mp_obj_set_t *other = m_new_obj(mp_obj_set_t);
-    other->base.type = &mp_type_set;
+    other->base.type = self->base.type;
     mp_set_init(&other->set, self->set.alloc);
     other->set.used = self->set.used;
     memcpy(other->set.table, self->set.table, self->set.alloc * sizeof(mp_obj_t));
-
     return MP_OBJ_FROM_PTR(other);
 }
-
-STATIC mp_obj_t set_copy(mp_obj_t self_in) {
-    check_set_or_frozenset(self_in);
-
-    mp_obj_t other = set_copy_as_mutable(self_in);
-    ((mp_obj_base_t*)MP_OBJ_TO_PTR(other))->type = ((mp_obj_base_t*)MP_OBJ_TO_PTR(self_in))->type;
-
-    return other;
-}
 STATIC MP_DEFINE_CONST_FUN_OBJ_1(set_copy_obj, set_copy);
 
 STATIC mp_obj_t set_discard(mp_obj_t self_in, mp_obj_t item) {
@@ -224,25 +202,23 @@ STATIC mp_obj_t set_diff_int(size_t n_args, const mp_obj_t *args, bool update) {
         check_set(args[0]);
         self = args[0];
     } else {
-        check_set_or_frozenset(args[0]);
-        self = set_copy_as_mutable(args[0]);
+        self = set_copy(args[0]);
     }
 
-
     for (size_t i = 1; i < n_args; i++) {
         mp_obj_t other = args[i];
         if (self == other) {
             set_clear(self);
         } else {
+            mp_set_t *self_set = &((mp_obj_set_t*)MP_OBJ_TO_PTR(self))->set;
             mp_obj_t iter = mp_getiter(other, NULL);
             mp_obj_t next;
             while ((next = mp_iternext(iter)) != MP_OBJ_STOP_ITERATION) {
-                set_discard(self, next);
+                mp_set_lookup(self_set, next, MP_MAP_LOOKUP_REMOVE_IF_FOUND);
             }
         }
     }
 
-    ((mp_obj_base_t*)MP_OBJ_TO_PTR(self))->type = ((mp_obj_base_t*)MP_OBJ_TO_PTR(args[0]))->type;
     return self;
 }
 
@@ -333,16 +309,16 @@ STATIC mp_obj_t set_issubset_internal(mp_obj_t self_in, mp_obj_t other_in, bool
         other = MP_OBJ_TO_PTR(set_make_new(&mp_type_set, 1, 0, &other_in));
         cleanup_other = true;
     }
-    bool out = true;
+    mp_obj_t out = mp_const_true;
     if (proper && self->set.used == other->set.used) {
-        out = false;
+        out = mp_const_false;
     } else {
         mp_obj_iter_buf_t iter_buf;
         mp_obj_t iter = set_getiter(MP_OBJ_FROM_PTR(self), &iter_buf);
         mp_obj_t next;
         while ((next = set_it_iternext(iter)) != MP_OBJ_STOP_ITERATION) {
             if (!mp_set_lookup(&other->set, next, MP_MAP_LOOKUP)) {
-                out = false;
+                out = mp_const_false;
                 break;
             }
         }
@@ -354,7 +330,7 @@ STATIC mp_obj_t set_issubset_internal(mp_obj_t self_in, mp_obj_t other_in, bool
     if (cleanup_other) {
         set_clear(MP_OBJ_FROM_PTR(other));
     }
-    return mp_obj_new_bool(out);
+    return out;
 }
 STATIC mp_obj_t set_issubset(mp_obj_t self_in, mp_obj_t other_in) {
     return set_issubset_internal(self_in, other_in, false);
@@ -402,14 +378,14 @@ STATIC mp_obj_t set_remove(mp_obj_t self_in, mp_obj_t item) {
     check_set(self_in);
     mp_obj_set_t *self = MP_OBJ_TO_PTR(self_in);
     if (mp_set_lookup(&self->set, item, MP_MAP_LOOKUP_REMOVE_IF_FOUND) == MP_OBJ_NULL) {
-        nlr_raise(mp_obj_new_exception(&mp_type_KeyError));
+        nlr_raise(mp_obj_new_exception_arg1(&mp_type_KeyError, item));
     }
     return mp_const_none;
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_2(set_remove_obj, set_remove);
 
 STATIC mp_obj_t set_symmetric_difference_update(mp_obj_t self_in, mp_obj_t other_in) {
-    check_set(self_in);
+    check_set_or_frozenset(self_in); // can be frozenset due to call from set_symmetric_difference
     mp_obj_set_t *self = MP_OBJ_TO_PTR(self_in);
     mp_obj_t iter = mp_getiter(other_in, NULL);
     mp_obj_t next;
@@ -421,10 +397,8 @@ STATIC mp_obj_t set_symmetric_difference_update(mp_obj_t self_in, mp_obj_t other
 STATIC MP_DEFINE_CONST_FUN_OBJ_2(set_symmetric_difference_update_obj, set_symmetric_difference_update);
 
 STATIC mp_obj_t set_symmetric_difference(mp_obj_t self_in, mp_obj_t other_in) {
-    check_set_or_frozenset(self_in);
-    mp_obj_t self_out = set_copy_as_mutable(self_in);
+    mp_obj_t self_out = set_copy(self_in);
     set_symmetric_difference_update(self_out, other_in);
-    ((mp_obj_base_t*)MP_OBJ_TO_PTR(self_out))->type = ((mp_obj_base_t*)MP_OBJ_TO_PTR(self_in))->type;
     return self_out;
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_2(set_symmetric_difference_obj, set_symmetric_difference);
@@ -455,7 +429,7 @@ STATIC mp_obj_t set_union(mp_obj_t self_in, mp_obj_t other_in) {
 }
 STATIC MP_DEFINE_CONST_FUN_OBJ_2(set_union_obj, set_union);
 
-STATIC mp_obj_t set_unary_op(mp_uint_t op, mp_obj_t self_in) {
+STATIC mp_obj_t set_unary_op(mp_unary_op_t op, mp_obj_t self_in) {
     mp_obj_set_t *self = MP_OBJ_TO_PTR(self_in);
     switch (op) {
         case MP_UNARY_OP_BOOL: return mp_obj_new_bool(self->set.used != 0);
@@ -480,13 +454,17 @@ STATIC mp_obj_t set_unary_op(mp_uint_t op, mp_obj_t self_in) {
     }
 }
 
-STATIC mp_obj_t set_binary_op(mp_uint_t op, mp_obj_t lhs, mp_obj_t rhs) {
+STATIC mp_obj_t set_binary_op(mp_binary_op_t op, mp_obj_t lhs, mp_obj_t rhs) {
     mp_obj_t args[] = {lhs, rhs};
     #if MICROPY_PY_BUILTINS_FROZENSET
     bool update = MP_OBJ_IS_TYPE(lhs, &mp_type_set);
     #else
     bool update = true;
     #endif
+    if (op != MP_BINARY_OP_IN && !is_set_or_frozenset(rhs)) {
+        // For all ops except containment the RHS must be a set/frozenset
+        return MP_OBJ_NULL;
+    }
     switch (op) {
         case MP_BINARY_OP_OR:
             return set_union(lhs, rhs);
@@ -578,6 +556,19 @@ const mp_obj_type_t mp_type_set = {
 };
 
 #if MICROPY_PY_BUILTINS_FROZENSET
+STATIC const mp_rom_map_elem_t frozenset_locals_dict_table[] = {
+    { MP_ROM_QSTR(MP_QSTR_copy), MP_ROM_PTR(&set_copy_obj) },
+    { MP_ROM_QSTR(MP_QSTR_difference), MP_ROM_PTR(&set_diff_obj) },
+    { MP_ROM_QSTR(MP_QSTR_intersection), MP_ROM_PTR(&set_intersect_obj) },
+    { MP_ROM_QSTR(MP_QSTR_isdisjoint), MP_ROM_PTR(&set_isdisjoint_obj) },
+    { MP_ROM_QSTR(MP_QSTR_issubset), MP_ROM_PTR(&set_issubset_obj) },
+    { MP_ROM_QSTR(MP_QSTR_issuperset), MP_ROM_PTR(&set_issuperset_obj) },
+    { MP_ROM_QSTR(MP_QSTR_symmetric_difference), MP_ROM_PTR(&set_symmetric_difference_obj) },
+    { MP_ROM_QSTR(MP_QSTR_union), MP_ROM_PTR(&set_union_obj) },
+    { MP_ROM_QSTR(MP_QSTR___contains__), MP_ROM_PTR(&mp_op_contains_obj) },
+};
+STATIC MP_DEFINE_CONST_DICT(frozenset_locals_dict, frozenset_locals_dict_table);
+
 const mp_obj_type_t mp_type_frozenset = {
     { &mp_type_type },
     .name = MP_QSTR_frozenset,
@@ -586,7 +577,7 @@ const mp_obj_type_t mp_type_frozenset = {
     .unary_op = set_unary_op,
     .binary_op = set_binary_op,
     .getiter = set_getiter,
-    .locals_dict = (mp_obj_dict_t*)&set_locals_dict,
+    .locals_dict = (mp_obj_dict_t*)&frozenset_locals_dict,
 };
 #endif
 
diff --git a/py/objsingleton.c b/py/objsingleton.c
index ea72ae38cc..67535391ea 100644
--- a/py/objsingleton.c
+++ b/py/objsingleton.c
@@ -27,9 +27,7 @@
 #include <stdlib.h>
 #include <assert.h>
 
-#include "py/nlr.h"
 #include "py/obj.h"
-#include "py/runtime0.h"
 
 /******************************************************************************/
 /* singleton objects defined by Python                                        */
diff --git a/py/objslice.c b/py/objslice.c
index cbdbe6ef98..dc8d72a6a0 100644
--- a/py/objslice.c
+++ b/py/objslice.c
@@ -27,7 +27,6 @@
 #include <stdlib.h>
 #include <assert.h>
 
-#include "py/nlr.h"
 #include "py/obj.h"
 #include "py/runtime.h"
 #include "py/runtime0.h"
diff --git a/py/objstr.c b/py/objstr.c
index 71ad38b9e7..64306f54f8 100644
--- a/py/objstr.c
+++ b/py/objstr.c
@@ -28,11 +28,9 @@
 #include <string.h>
 #include <assert.h>
 
-#include "py/nlr.h"
 #include "py/unicode.h"
 #include "py/objstr.h"
 #include "py/objlist.h"
-#include "py/runtime0.h"
 #include "py/runtime.h"
 #include "py/stackctrl.h"
 
@@ -161,6 +159,11 @@ mp_obj_t mp_obj_str_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_
                 if (str_hash == 0) {
                     str_hash = qstr_compute_hash(str_data, str_len);
                 }
+                #if MICROPY_PY_BUILTINS_STR_UNICODE_CHECK
+                if (!utf8_check(str_data, str_len)) {
+                    mp_raise_msg(&mp_type_UnicodeError, NULL);
+                }
+                #endif
                 mp_obj_str_t *o = MP_OBJ_TO_PTR(mp_obj_new_str_of_type(type, NULL, str_len));
                 o->data = str_data;
                 o->hash = str_hash;
@@ -168,6 +171,11 @@ mp_obj_t mp_obj_str_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_
             } else {
                 mp_buffer_info_t bufinfo;
                 mp_get_buffer_raise(args[0], &bufinfo, MP_BUFFER_READ);
+                #if MICROPY_PY_BUILTINS_STR_UNICODE_CHECK
+                if (!utf8_check(bufinfo.buf, bufinfo.len)) {
+                    mp_raise_msg(&mp_type_UnicodeError, NULL);
+                }
+                #endif
                 return mp_obj_new_str(bufinfo.buf, bufinfo.len, false);
             }
     }
@@ -280,7 +288,7 @@ const byte *find_subbytes(const byte *haystack, size_t hlen, const byte *needle,
 // Note: this function is used to check if an object is a str or bytes, which
 // works because both those types use it as their binary_op method.  Revisit
 // MP_OBJ_IS_STR_OR_BYTES if this fact changes.
-mp_obj_t mp_obj_str_binary_op(mp_uint_t op, mp_obj_t lhs_in, mp_obj_t rhs_in) {
+mp_obj_t mp_obj_str_binary_op(mp_binary_op_t op, mp_obj_t lhs_in, mp_obj_t rhs_in) {
     // check for modulo
     if (op == MP_BINARY_OP_MODULO) {
         mp_obj_t *args = &rhs_in;
@@ -380,9 +388,10 @@ mp_obj_t mp_obj_str_binary_op(mp_uint_t op, mp_obj_t lhs_in, mp_obj_t rhs_in) {
         case MP_BINARY_OP_MORE:
         case MP_BINARY_OP_MORE_EQUAL:
             return mp_obj_new_bool(mp_seq_cmp_bytes(op, lhs_data, lhs_len, rhs_data, rhs_len));
-    }
 
-    return MP_OBJ_NULL; // op not supported
+        default:
+            return MP_OBJ_NULL; // op not supported
+    }
 }
 
 #if !MICROPY_PY_BUILTINS_STR_UNICODE
@@ -726,7 +735,8 @@ MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(str_rindex_obj, 2, 4, str_rindex);
 STATIC mp_obj_t str_startswith(size_t n_args, const mp_obj_t *args) {
     const mp_obj_type_t *self_type = mp_obj_get_type(args[0]);
     GET_STR_DATA_LEN(args[0], str, str_len);
-    GET_STR_DATA_LEN(args[1], prefix, prefix_len);
+    size_t prefix_len;
+    const char *prefix = mp_obj_str_get_data(args[1], &prefix_len);
     const byte *start = str;
     if (n_args > 2) {
         start = str_index_to_ptr(self_type, str, str_len, args[2], true);
@@ -740,7 +750,8 @@ MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(str_startswith_obj, 2, 3, str_startswith);
 
 STATIC mp_obj_t str_endswith(size_t n_args, const mp_obj_t *args) {
     GET_STR_DATA_LEN(args[0], str, str_len);
-    GET_STR_DATA_LEN(args[1], suffix, suffix_len);
+    size_t suffix_len;
+    const char *suffix = mp_obj_str_get_data(args[1], &suffix_len);
     if (n_args > 2) {
         mp_raise_NotImplementedError("start/end indices");
     }
@@ -764,7 +775,7 @@ STATIC mp_obj_t str_uni_strip(int type, size_t n_args, const mp_obj_t *args) {
 
     if (n_args == 1) {
         chars_to_del = whitespace;
-        chars_to_del_len = sizeof(whitespace);
+        chars_to_del_len = sizeof(whitespace) - 1;
     } else {
         if (mp_obj_get_type(args[1]) != self_type) {
             bad_implicit_conversion(args[1]);
@@ -1961,8 +1972,8 @@ const mp_obj_type_t mp_type_bytes = {
     .locals_dict = (mp_obj_dict_t*)&str8_locals_dict,
 };
 
-// the zero-length bytes
-const mp_obj_str_t mp_const_empty_bytes_obj = {{&mp_type_bytes}, 0, 0, NULL};
+// The zero-length bytes object, with data that includes a null-terminating byte
+const mp_obj_str_t mp_const_empty_bytes_obj = {{&mp_type_bytes}, 0, 0, (const byte*)""};
 
 // Create a str/bytes object using the given data.  New memory is allocated and
 // the data is copied across.
diff --git a/py/objstr.h b/py/objstr.h
index 3aef8c68e2..82501a763e 100644
--- a/py/objstr.h
+++ b/py/objstr.h
@@ -67,7 +67,7 @@ mp_obj_t mp_obj_str_format(size_t n_args, const mp_obj_t *args, mp_map_t *kwargs
 mp_obj_t mp_obj_str_split(size_t n_args, const mp_obj_t *args);
 mp_obj_t mp_obj_new_str_of_type(const mp_obj_type_t *type, const byte* data, size_t len);
 
-mp_obj_t mp_obj_str_binary_op(mp_uint_t op, mp_obj_t lhs_in, mp_obj_t rhs_in);
+mp_obj_t mp_obj_str_binary_op(mp_binary_op_t op, mp_obj_t lhs_in, mp_obj_t rhs_in);
 mp_int_t mp_obj_str_get_buffer(mp_obj_t self_in, mp_buffer_info_t *bufinfo, mp_uint_t flags);
 
 const byte *str_index_to_ptr(const mp_obj_type_t *type, const byte *self_data, size_t self_len,
diff --git a/py/objstringio.c b/py/objstringio.c
index 61da0203e1..5c50aa3174 100644
--- a/py/objstringio.c
+++ b/py/objstringio.c
@@ -28,7 +28,6 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "py/nlr.h"
 #include "py/objstr.h"
 #include "py/objstringio.h"
 #include "py/runtime.h"
diff --git a/py/objstrunicode.c b/py/objstrunicode.c
index bdcf10d4dc..a243022a72 100644
--- a/py/objstrunicode.c
+++ b/py/objstrunicode.c
@@ -28,10 +28,8 @@
 #include <string.h>
 #include <assert.h>
 
-#include "py/nlr.h"
 #include "py/objstr.h"
 #include "py/objlist.h"
-#include "py/runtime0.h"
 #include "py/runtime.h"
 
 #if MICROPY_PY_BUILTINS_STR_UNICODE
@@ -100,7 +98,7 @@ STATIC void uni_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t
     }
 }
 
-STATIC mp_obj_t uni_unary_op(mp_uint_t op, mp_obj_t self_in) {
+STATIC mp_obj_t uni_unary_op(mp_unary_op_t op, mp_obj_t self_in) {
     GET_STR_DATA_LEN(self_in, str_data, str_len);
     switch (op) {
         case MP_UNARY_OP_BOOL:
diff --git a/py/objtuple.c b/py/objtuple.c
index 765edb907c..34b7664ebb 100644
--- a/py/objtuple.c
+++ b/py/objtuple.c
@@ -27,9 +27,7 @@
 #include <string.h>
 #include <assert.h>
 
-#include "py/nlr.h"
 #include "py/objtuple.h"
-#include "py/runtime0.h"
 #include "py/runtime.h"
 
 /******************************************************************************/
@@ -101,7 +99,7 @@ STATIC mp_obj_t mp_obj_tuple_make_new(const mp_obj_type_t *type_in, size_t n_arg
 }
 
 // Don't pass MP_BINARY_OP_NOT_EQUAL here
-STATIC bool tuple_cmp_helper(mp_uint_t op, mp_obj_t self_in, mp_obj_t another_in) {
+STATIC mp_obj_t tuple_cmp_helper(mp_uint_t op, mp_obj_t self_in, mp_obj_t another_in) {
     // type check is done on getiter method to allow tuple, namedtuple, attrtuple
     mp_check_self(mp_obj_get_type(self_in)->getiter == mp_obj_tuple_getiter);
     mp_obj_type_t *another_type = mp_obj_get_type(another_in);
@@ -110,15 +108,18 @@ STATIC bool tuple_cmp_helper(mp_uint_t op, mp_obj_t self_in, mp_obj_t another_in
         // Slow path for user subclasses
         another_in = mp_instance_cast_to_native_base(another_in, MP_OBJ_FROM_PTR(&mp_type_tuple));
         if (another_in == MP_OBJ_NULL) {
-            return false;
+            if (op == MP_BINARY_OP_EQUAL) {
+                return mp_const_false;
+            }
+            return MP_OBJ_NULL;
         }
     }
     mp_obj_tuple_t *another = MP_OBJ_TO_PTR(another_in);
 
-    return mp_seq_cmp_objs(op, self->items, self->len, another->items, another->len);
+    return mp_obj_new_bool(mp_seq_cmp_objs(op, self->items, self->len, another->items, another->len));
 }
 
-mp_obj_t mp_obj_tuple_unary_op(mp_uint_t op, mp_obj_t self_in) {
+mp_obj_t mp_obj_tuple_unary_op(mp_unary_op_t op, mp_obj_t self_in) {
     mp_obj_tuple_t *self = MP_OBJ_TO_PTR(self_in);
     switch (op) {
         case MP_UNARY_OP_BOOL: return mp_obj_new_bool(self->len != 0);
@@ -135,7 +136,7 @@ mp_obj_t mp_obj_tuple_unary_op(mp_uint_t op, mp_obj_t self_in) {
     }
 }
 
-mp_obj_t mp_obj_tuple_binary_op(mp_uint_t op, mp_obj_t lhs, mp_obj_t rhs) {
+mp_obj_t mp_obj_tuple_binary_op(mp_binary_op_t op, mp_obj_t lhs, mp_obj_t rhs) {
     mp_obj_tuple_t *o = MP_OBJ_TO_PTR(lhs);
     switch (op) {
         case MP_BINARY_OP_ADD:
@@ -166,7 +167,7 @@ mp_obj_t mp_obj_tuple_binary_op(mp_uint_t op, mp_obj_t lhs, mp_obj_t rhs) {
         case MP_BINARY_OP_LESS_EQUAL:
         case MP_BINARY_OP_MORE:
         case MP_BINARY_OP_MORE_EQUAL:
-            return mp_obj_new_bool(tuple_cmp_helper(op, lhs, rhs));
+            return tuple_cmp_helper(op, lhs, rhs);
 
         default:
             return MP_OBJ_NULL; // op not supported
diff --git a/py/objtuple.h b/py/objtuple.h
index 41e4d3c1b5..bcf0c9ed4f 100644
--- a/py/objtuple.h
+++ b/py/objtuple.h
@@ -50,8 +50,8 @@ typedef struct _mp_rom_obj_tuple_t {
 extern const mp_obj_type_t mp_type_tuple;
 
 void mp_obj_tuple_print(const mp_print_t *print, mp_obj_t o_in, mp_print_kind_t kind);
-mp_obj_t mp_obj_tuple_unary_op(mp_uint_t op, mp_obj_t self_in);
-mp_obj_t mp_obj_tuple_binary_op(mp_uint_t op, mp_obj_t lhs, mp_obj_t rhs);
+mp_obj_t mp_obj_tuple_unary_op(mp_unary_op_t op, mp_obj_t self_in);
+mp_obj_t mp_obj_tuple_binary_op(mp_binary_op_t op, mp_obj_t lhs, mp_obj_t rhs);
 mp_obj_t mp_obj_tuple_subscr(mp_obj_t base, mp_obj_t index, mp_obj_t value);
 mp_obj_t mp_obj_tuple_getiter(mp_obj_t o_in, mp_obj_iter_buf_t *iter_buf);
 
diff --git a/py/objtype.c b/py/objtype.c
index aada226592..d57cec7034 100644
--- a/py/objtype.c
+++ b/py/objtype.c
@@ -30,9 +30,7 @@
 #include <string.h>
 #include <assert.h>
 
-#include "py/nlr.h"
 #include "py/objtype.h"
-#include "py/runtime0.h"
 #include "py/runtime.h"
 
 #if MICROPY_DEBUG_VERBOSE // print debugging info
@@ -113,6 +111,7 @@ STATIC void mp_obj_class_lookup(struct class_lookup_data  *lookup, const mp_obj_
     assert(lookup->dest[0] == MP_OBJ_NULL);
     assert(lookup->dest[1] == MP_OBJ_NULL);
     for (;;) {
+        DEBUG_printf("mp_obj_class_lookup: Looking up %s in %s\n", qstr_str(lookup->attr), qstr_str(type->name));
         // Optimize special method lookup for native types
         // This avoids extra method_name => slot lookup. On the other hand,
         // this should not be applied to class types, as will result in extra
@@ -122,7 +121,8 @@ STATIC void mp_obj_class_lookup(struct class_lookup_data  *lookup, const mp_obj_
 #pragma GCC diagnostic ignored "-Wcast-align"
             if (*(void**)((char*)type + lookup->meth_offset) != NULL) {
 #pragma GCC diagnostic pop
-                DEBUG_printf("mp_obj_class_lookup: matched special meth slot for %s\n", qstr_str(lookup->attr));
+                DEBUG_printf("mp_obj_class_lookup: Matched special meth slot (off=%d) for %s\n",
+                    lookup->meth_offset, qstr_str(lookup->attr));
                 lookup->dest[0] = MP_OBJ_SENTINEL;
                 return;
             }
@@ -153,7 +153,8 @@ STATIC void mp_obj_class_lookup(struct class_lookup_data  *lookup, const mp_obj_
 #if DEBUG_PRINT
                 printf("mp_obj_class_lookup: Returning: ");
                 mp_obj_print(lookup->dest[0], PRINT_REPR); printf(" ");
-                mp_obj_print(lookup->dest[1], PRINT_REPR); printf("\n");
+                // Don't try to repr() lookup->dest[1], as we can be called recursively
+                printf("<%s @%p>\n", mp_obj_get_type_str(lookup->dest[1]), lookup->dest[1]);
 #endif
                 return;
             }
@@ -172,6 +173,7 @@ STATIC void mp_obj_class_lookup(struct class_lookup_data  *lookup, const mp_obj_
         // attribute not found, keep searching base classes
 
         if (type->parent == NULL) {
+            DEBUG_printf("mp_obj_class_lookup: No more parents\n");
             return;
         } else if (((mp_obj_base_t*)type->parent)->type == &mp_type_tuple) {
             const mp_obj_tuple_t *parent_tuple = type->parent;
@@ -254,9 +256,9 @@ mp_obj_t mp_obj_instance_make_new(const mp_obj_type_t *self, size_t n_args, size
 
     mp_obj_instance_t *o = MP_OBJ_TO_PTR(mp_obj_new_instance(self, num_native_bases));
 
-    // This executes only "__new__" part of obejection creation.
-    // TODO: This won't work will for classes with native bases.
-    // TODO: This is hack, should be resolved along the lines of
+    // This executes only "__new__" part of instance creation.
+    // TODO: This won't work well for classes with native bases.
+    // TODO: This is a hack, should be resolved along the lines of
     // https://github.com/micropython/micropython/issues/606#issuecomment-43685883
     if (n_args == 1 && *args == MP_OBJ_SENTINEL) {
         return MP_OBJ_FROM_PTR(o);
@@ -333,7 +335,7 @@ mp_obj_t mp_obj_instance_make_new(const mp_obj_type_t *self, size_t n_args, size
     return MP_OBJ_FROM_PTR(o);
 }
 
-const qstr mp_unary_op_method_name[] = {
+const uint16_t mp_unary_op_method_name[] = {
     [MP_UNARY_OP_BOOL] = MP_QSTR___bool__,
     [MP_UNARY_OP_LEN] = MP_QSTR___len__,
     [MP_UNARY_OP_HASH] = MP_QSTR___hash__,
@@ -348,7 +350,7 @@ const qstr mp_unary_op_method_name[] = {
     [MP_UNARY_OP_NOT] = MP_QSTR_, // don't need to implement this, used to make sure array has full size
 };
 
-STATIC mp_obj_t instance_unary_op(mp_uint_t op, mp_obj_t self_in) {
+STATIC mp_obj_t instance_unary_op(mp_unary_op_t op, mp_obj_t self_in) {
     mp_obj_instance_t *self = MP_OBJ_TO_PTR(self_in);
 
     #if MICROPY_PY_SYS_GETSIZEOF
@@ -407,7 +409,7 @@ STATIC mp_obj_t instance_unary_op(mp_uint_t op, mp_obj_t self_in) {
     }
 }
 
-const qstr mp_binary_op_method_name[] = {
+const uint16_t mp_binary_op_method_name[] = {
     /*
     MP_BINARY_OP_OR,
     MP_BINARY_OP_XOR,
@@ -440,6 +442,13 @@ const qstr mp_binary_op_method_name[] = {
     MP_BINARY_OP_INPLACE_TRUE_DIVIDE,
     MP_BINARY_OP_INPLACE_MODULO,
     MP_BINARY_OP_INPLACE_POWER,*/
+
+    #if MICROPY_PY_REVERSE_SPECIAL_METHODS
+    [MP_BINARY_OP_REVERSE_ADD] = MP_QSTR___radd__,
+    [MP_BINARY_OP_REVERSE_SUBTRACT] = MP_QSTR___rsub__,
+    [MP_BINARY_OP_REVERSE_MULTIPLY] = MP_QSTR___rmul__,
+    #endif
+
     [MP_BINARY_OP_LESS] = MP_QSTR___lt__,
     [MP_BINARY_OP_MORE] = MP_QSTR___gt__,
     [MP_BINARY_OP_EQUAL] = MP_QSTR___eq__,
@@ -452,13 +461,14 @@ const qstr mp_binary_op_method_name[] = {
     /*
     MP_BINARY_OP_IS,
     */
-    [MP_BINARY_OP_EXCEPTION_MATCH] = MP_QSTR_, // not implemented, used to make sure array has full size
+    [MP_BINARY_OP_LAST] = 0, // used to make sure array has full size, TODO: FIXME
 };
 
-STATIC mp_obj_t instance_binary_op(mp_uint_t op, mp_obj_t lhs_in, mp_obj_t rhs_in) {
+STATIC mp_obj_t instance_binary_op(mp_binary_op_t op, mp_obj_t lhs_in, mp_obj_t rhs_in) {
     // Note: For ducktyping, CPython does not look in the instance members or use
     // __getattr__ or __getattribute__.  It only looks in the class dictionary.
     mp_obj_instance_t *lhs = MP_OBJ_TO_PTR(lhs_in);
+retry:;
     qstr op_name = mp_binary_op_method_name[op];
     /* Still try to lookup native slot
     if (op_name == 0) {
@@ -474,14 +484,36 @@ STATIC mp_obj_t instance_binary_op(mp_uint_t op, mp_obj_t lhs_in, mp_obj_t rhs_i
         .is_type = false,
     };
     mp_obj_class_lookup(&lookup, lhs->base.type);
+
+    mp_obj_t res;
     if (dest[0] == MP_OBJ_SENTINEL) {
-        return mp_binary_op(op, lhs->subobj[0], rhs_in);
+        res = mp_binary_op(op, lhs->subobj[0], rhs_in);
     } else if (dest[0] != MP_OBJ_NULL) {
         dest[2] = rhs_in;
-        return mp_call_method_n_kw(1, 0, dest);
+        res = mp_call_method_n_kw(1, 0, dest);
     } else {
+        // If this was an inplace method, fallback to normal method
+        // https://docs.python.org/3/reference/datamodel.html#object.__iadd__ :
+        // "If a specific method is not defined, the augmented assignment
+        // falls back to the normal methods."
+        if (op >= MP_BINARY_OP_INPLACE_OR && op <= MP_BINARY_OP_INPLACE_POWER) {
+            op -= MP_BINARY_OP_INPLACE_OR - MP_BINARY_OP_OR;
+            goto retry;
+        }
         return MP_OBJ_NULL; // op not supported
     }
+
+    #if MICROPY_PY_BUILTINS_NOTIMPLEMENTED
+    // NotImplemented means "try other fallbacks (like calling __rop__
+    // instead of __op__) and if nothing works, raise TypeError". As
+    // MicroPython doesn't implement any fallbacks, signal to raise
+    // TypeError right away.
+    if (res == mp_const_notimplemented) {
+        return MP_OBJ_NULL; // op not supported
+    }
+    #endif
+
+    return res;
 }
 
 STATIC void mp_obj_instance_load_attr(mp_obj_t self_in, qstr attr, mp_obj_t *dest) {
diff --git a/py/parse.c b/py/parse.c
index 897ecd89d6..3a108964b7 100644
--- a/py/parse.c
+++ b/py/parse.c
@@ -31,11 +31,9 @@
 #include <assert.h>
 #include <string.h>
 
-#include "py/nlr.h"
 #include "py/lexer.h"
 #include "py/parse.h"
 #include "py/parsenum.h"
-#include "py/runtime0.h"
 #include "py/runtime.h"
 #include "py/objint.h"
 #include "py/objstr.h"
diff --git a/py/persistentcode.c b/py/persistentcode.c
index fac512fb43..42efcbfbb5 100644
--- a/py/persistentcode.c
+++ b/py/persistentcode.c
@@ -99,7 +99,6 @@ STATIC void extract_prelude(const byte **ip, const byte **ip2, bytecode_prelude_
 #if MICROPY_PERSISTENT_CODE_LOAD
 
 #include "py/parsenum.h"
-#include "py/bc0.h"
 
 STATIC int read_byte(mp_reader_t *reader) {
     return reader->readbyte(reader->data);
@@ -376,7 +375,7 @@ void mp_raw_code_save(mp_raw_code_t *rc, mp_print_t *print) {
 // here we define mp_raw_code_save_file depending on the port
 // TODO abstract this away properly
 
-#if defined(__i386__) || defined(__x86_64__) || (defined(__arm__) && (defined(__unix__)))
+#if defined(__i386__) || defined(__x86_64__) || defined(__unix__)
 
 #include <unistd.h>
 #include <sys/stat.h>
diff --git a/py/py.mk b/py/py.mk
index f48baf659d..9021192df8 100644
--- a/py/py.mk
+++ b/py/py.mk
@@ -74,7 +74,7 @@ endif
 
 ifeq ($(MICROPY_PY_BTREE),1)
 BTREE_DIR = lib/berkeley-db-1.xx
-BTREE_DEFS = -D__DBINTERFACE_PRIVATE=1 -Dmpool_error=printf -Dabort=abort_ -Dvirt_fd_t=mp_obj_t "-DVIRT_FD_T_HEADER=<py/obj.h>"
+BTREE_DEFS = -D__DBINTERFACE_PRIVATE=1 -Dmpool_error=printf -Dabort=abort_ -Dvirt_fd_t=mp_obj_t "-DVIRT_FD_T_HEADER=<py/obj.h>" $(BTREE_DEFS_EXTRA)
 INC += -I$(TOP)/$(BTREE_DIR)/PORT/include
 SRC_MOD += extmod/modbtree.c
 SRC_MOD += $(addprefix $(BTREE_DIR)/,\
diff --git a/py/qstrdefs.h b/py/qstrdefs.h
index 9375b9101a..4ded5be084 100644
--- a/py/qstrdefs.h
+++ b/py/qstrdefs.h
@@ -51,11 +51,3 @@ Q(<genexpr>)
 Q(<string>)
 Q(<stdin>)
 Q(utf-8)
-
-// The following qstrings not referenced from anywhere in the sources
-Q(__locals__)
-Q(BufferError)
-Q(FileExistsError)
-Q(FileNotFoundError)
-Q(FloatingPointError)
-Q(UnboundLocalError)
diff --git a/py/runtime.c b/py/runtime.c
index 2d24f3f756..4af17dd092 100644
--- a/py/runtime.c
+++ b/py/runtime.c
@@ -31,8 +31,8 @@
 
 #include "extmod/vfs.h"
 
-#include "py/mpstate.h"
-#include "py/nlr.h"
+// #include "py/mpstate.h"
+// #include "py/nlr.h"
 #include "py/parsenum.h"
 #include "py/compile.h"
 #include "py/objstr.h"
@@ -42,7 +42,6 @@
 #include "py/objmodule.h"
 #include "py/objgenerator.h"
 #include "py/smallint.h"
-#include "py/runtime0.h"
 #include "py/runtime.h"
 #include "py/builtin.h"
 #include "py/stackctrl.h"
@@ -233,7 +232,7 @@ void mp_delete_global(qstr qst) {
     mp_obj_dict_delete(MP_OBJ_FROM_PTR(mp_globals_get()), MP_OBJ_NEW_QSTR(qst));
 }
 
-mp_obj_t mp_unary_op(mp_uint_t op, mp_obj_t arg) {
+mp_obj_t mp_unary_op(mp_unary_op_t op, mp_obj_t arg) {
     DEBUG_OP_printf("unary " UINT_FMT " %p\n", op, arg);
 
     if (op == MP_UNARY_OP_NOT) {
@@ -255,6 +254,15 @@ mp_obj_t mp_unary_op(mp_uint_t op, mp_obj_t arg) {
                 } else {
                     return MP_OBJ_NEW_SMALL_INT(-val);
                 }
+            case MP_UNARY_OP_ABS:
+                if (val >= 0) {
+                    return arg;
+                } else if (val == MP_SMALL_INT_MIN) {
+                    // check for overflow
+                    return mp_obj_new_int(-val);
+                } else {
+                    return MP_OBJ_NEW_SMALL_INT(-val);
+                }
             default:
                 assert(op == MP_UNARY_OP_INVERT);
                 return MP_OBJ_NEW_SMALL_INT(~val);
@@ -285,7 +293,7 @@ mp_obj_t mp_unary_op(mp_uint_t op, mp_obj_t arg) {
     }
 }
 
-mp_obj_t mp_binary_op(mp_uint_t op, mp_obj_t lhs, mp_obj_t rhs) {
+mp_obj_t mp_binary_op(mp_binary_op_t op, mp_obj_t lhs, mp_obj_t rhs) {
     DEBUG_OP_printf("binary " UINT_FMT " %p %p\n", op, lhs, rhs);
 
     // TODO correctly distinguish inplace operators for mutable objects
@@ -579,7 +587,20 @@ generic_binary_op:
         }
     }
 
-    // TODO implement dispatch for reverse binary ops
+#if MICROPY_PY_REVERSE_SPECIAL_METHODS
+    if (op >= MP_BINARY_OP_OR && op <= MP_BINARY_OP_REVERSE_POWER) {
+        mp_obj_t t = rhs;
+        rhs = lhs;
+        lhs = t;
+        if (op <= MP_BINARY_OP_POWER) {
+            op += MP_BINARY_OP_REVERSE_OR - MP_BINARY_OP_OR;
+            goto generic_binary_op;
+        }
+
+        // Convert __rop__ back to __op__ for error message
+        op -= MP_BINARY_OP_REVERSE_OR - MP_BINARY_OP_OR;
+    }
+#endif
 
 unsupported_op:
     if (MICROPY_ERROR_REPORTING == MICROPY_ERROR_REPORTING_TERSE) {
@@ -1476,7 +1497,7 @@ mp_obj_t mp_parse_compile_execute(mp_lexer_t *lex, mp_parse_input_kind_t parse_i
 
 #endif // MICROPY_ENABLE_COMPILER
 
-NORETURN void *m_malloc_fail(size_t num_bytes) {
+NORETURN void m_malloc_fail(size_t num_bytes) {
     DEBUG_printf("memory allocation failed, allocating %u bytes\n", (uint)num_bytes);
     #if MICROPY_ENABLE_GC
     if (gc_is_locked()) {
diff --git a/py/runtime.h b/py/runtime.h
index 5f8ed5171f..79f5cbc921 100644
--- a/py/runtime.h
+++ b/py/runtime.h
@@ -27,7 +27,6 @@
 #define MICROPY_INCLUDED_PY_RUNTIME_H
 
 #include "py/mpstate.h"
-#include "py/obj.h"
 
 typedef enum {
     MP_VM_RETURN_NORMAL,
@@ -57,9 +56,9 @@ typedef struct _mp_arg_t {
     mp_arg_val_t defval;
 } mp_arg_t;
 
-// defined in objtype.c
-extern const qstr mp_unary_op_method_name[];
-extern const qstr mp_binary_op_method_name[];
+// Tables mapping operator enums to qstrs, defined in objtype.c
+extern const uint16_t mp_unary_op_method_name[];
+extern const uint16_t mp_binary_op_method_name[];
 
 void mp_init(void);
 void mp_deinit(void);
@@ -96,8 +95,8 @@ void mp_store_global(qstr qst, mp_obj_t obj);
 void mp_delete_name(qstr qst);
 void mp_delete_global(qstr qst);
 
-mp_obj_t mp_unary_op(mp_uint_t op, mp_obj_t arg);
-mp_obj_t mp_binary_op(mp_uint_t op, mp_obj_t lhs, mp_obj_t rhs);
+mp_obj_t mp_unary_op(mp_unary_op_t op, mp_obj_t arg);
+mp_obj_t mp_binary_op(mp_binary_op_t op, mp_obj_t lhs, mp_obj_t rhs);
 
 mp_obj_t mp_call_function_0(mp_obj_t fun);
 mp_obj_t mp_call_function_1(mp_obj_t fun, mp_obj_t arg);
@@ -181,7 +180,7 @@ void mp_native_raise(mp_obj_t o);
 #if MICROPY_WARNINGS
 void mp_warning(const char *msg, ...);
 #else
-#define mp_warning(msg, ...)
+#define mp_warning(...)
 #endif
 
 #endif // MICROPY_INCLUDED_PY_RUNTIME_H
diff --git a/py/runtime0.h b/py/runtime0.h
index 0ede55a77c..8e95b68cf5 100644
--- a/py/runtime0.h
+++ b/py/runtime0.h
@@ -45,61 +45,93 @@
 #define MP_NATIVE_TYPE_PTR32 (0x07)
 
 typedef enum {
-    MP_UNARY_OP_BOOL, // __bool__
-    MP_UNARY_OP_LEN, // __len__
-    MP_UNARY_OP_HASH, // __hash__; must return a small int
+    // These ops may appear in the bytecode. Changing this group
+    // in any way requires changing the bytecode version.
     MP_UNARY_OP_POSITIVE,
     MP_UNARY_OP_NEGATIVE,
     MP_UNARY_OP_INVERT,
     MP_UNARY_OP_NOT,
+
+    // Following ops cannot appear in the bytecode
+    MP_UNARY_OP_NON_BYTECODE,
+
+    MP_UNARY_OP_BOOL = MP_UNARY_OP_NON_BYTECODE, // __bool__
+    MP_UNARY_OP_LEN, // __len__
+    MP_UNARY_OP_HASH, // __hash__; must return a small int
+    MP_UNARY_OP_ABS, // __abs__
     MP_UNARY_OP_SIZEOF, // for sys.getsizeof()
 } mp_unary_op_t;
 
+// Note: the first 35 of these are used in bytecode and changing
+// them requires changing the bytecode version.
 typedef enum {
-    MP_BINARY_OP_OR,
-    MP_BINARY_OP_XOR,
-    MP_BINARY_OP_AND,
-    MP_BINARY_OP_LSHIFT,
-    MP_BINARY_OP_RSHIFT,
-
-    MP_BINARY_OP_ADD,
-    MP_BINARY_OP_SUBTRACT,
-    MP_BINARY_OP_MULTIPLY,
-    MP_BINARY_OP_FLOOR_DIVIDE,
-    MP_BINARY_OP_TRUE_DIVIDE,
-
-    MP_BINARY_OP_MODULO,
-    MP_BINARY_OP_POWER,
-    MP_BINARY_OP_DIVMOD, // not emitted by the compiler but supported by the runtime
-    MP_BINARY_OP_INPLACE_OR,
-    MP_BINARY_OP_INPLACE_XOR,
-
-    MP_BINARY_OP_INPLACE_AND,
-    MP_BINARY_OP_INPLACE_LSHIFT,
-    MP_BINARY_OP_INPLACE_RSHIFT,
-    MP_BINARY_OP_INPLACE_ADD,
-    MP_BINARY_OP_INPLACE_SUBTRACT,
-
-    MP_BINARY_OP_INPLACE_MULTIPLY,
-    MP_BINARY_OP_INPLACE_FLOOR_DIVIDE,
-    MP_BINARY_OP_INPLACE_TRUE_DIVIDE,
-    MP_BINARY_OP_INPLACE_MODULO,
-    MP_BINARY_OP_INPLACE_POWER,
-
-    // these should return a bool
+    // Relational operations, should return a bool
     MP_BINARY_OP_LESS,
     MP_BINARY_OP_MORE,
     MP_BINARY_OP_EQUAL,
     MP_BINARY_OP_LESS_EQUAL,
     MP_BINARY_OP_MORE_EQUAL,
-
     MP_BINARY_OP_NOT_EQUAL,
+
     MP_BINARY_OP_IN,
     MP_BINARY_OP_IS,
     MP_BINARY_OP_EXCEPTION_MATCH,
     // these are not supported by the runtime and must be synthesised by the emitter
     MP_BINARY_OP_NOT_IN,
     MP_BINARY_OP_IS_NOT,
+
+    // Arithmetic operations
+    MP_BINARY_OP_INPLACE_OR,
+    MP_BINARY_OP_INPLACE_XOR,
+    MP_BINARY_OP_INPLACE_AND,
+    MP_BINARY_OP_INPLACE_LSHIFT,
+    MP_BINARY_OP_INPLACE_RSHIFT,
+    MP_BINARY_OP_INPLACE_ADD,
+
+    MP_BINARY_OP_INPLACE_SUBTRACT,
+    MP_BINARY_OP_INPLACE_MULTIPLY,
+    MP_BINARY_OP_INPLACE_FLOOR_DIVIDE,
+    MP_BINARY_OP_INPLACE_TRUE_DIVIDE,
+    MP_BINARY_OP_INPLACE_MODULO,
+    MP_BINARY_OP_INPLACE_POWER,
+
+    MP_BINARY_OP_OR,
+    MP_BINARY_OP_XOR,
+    MP_BINARY_OP_AND,
+    MP_BINARY_OP_LSHIFT,
+    MP_BINARY_OP_RSHIFT,
+    MP_BINARY_OP_ADD,
+
+    MP_BINARY_OP_SUBTRACT,
+    MP_BINARY_OP_MULTIPLY,
+    MP_BINARY_OP_FLOOR_DIVIDE,
+    MP_BINARY_OP_TRUE_DIVIDE,
+    MP_BINARY_OP_MODULO,
+    MP_BINARY_OP_POWER,
+
+    // Operations below this line don't appear in bytecode, they
+    // just identify special methods.
+
+    // MP_BINARY_OP_REVERSE_* must follow immediately after MP_BINARY_OP_*
+#if MICROPY_PY_REVERSE_SPECIAL_METHODS
+    MP_BINARY_OP_REVERSE_OR,
+    MP_BINARY_OP_REVERSE_XOR,
+    MP_BINARY_OP_REVERSE_AND,
+    MP_BINARY_OP_REVERSE_LSHIFT,
+    MP_BINARY_OP_REVERSE_RSHIFT,
+    MP_BINARY_OP_REVERSE_ADD,
+
+    MP_BINARY_OP_REVERSE_SUBTRACT,
+    MP_BINARY_OP_REVERSE_MULTIPLY,
+    MP_BINARY_OP_REVERSE_FLOOR_DIVIDE,
+    MP_BINARY_OP_REVERSE_TRUE_DIVIDE,
+    MP_BINARY_OP_REVERSE_MODULO,
+    MP_BINARY_OP_REVERSE_POWER,
+#endif
+
+    MP_BINARY_OP_DIVMOD, // not emitted by the compiler but supported by the runtime
+
+    MP_BINARY_OP_LAST,
 } mp_binary_op_t;
 
 typedef enum {
diff --git a/py/runtime_utils.c b/py/runtime_utils.c
index 56a9180645..a5c5403baf 100644
--- a/py/runtime_utils.c
+++ b/py/runtime_utils.c
@@ -26,8 +26,6 @@
  */
 
 #include "py/runtime.h"
-#include "py/obj.h"
-#include "py/nlr.h"
 
 void mp_call_function_1_protected(mp_obj_t fun, mp_obj_t arg) {
     nlr_buf_t nlr;
diff --git a/py/sequence.c b/py/sequence.c
index 0752ee1098..c66fde98f6 100644
--- a/py/sequence.c
+++ b/py/sequence.c
@@ -27,9 +27,6 @@
 
 #include <string.h>
 
-#include "py/nlr.h"
-#include "py/obj.h"
-#include "py/runtime0.h"
 #include "py/runtime.h"
 
 // Helpers for sequence types
diff --git a/py/showbc.c b/py/showbc.c
index bb2b084ed7..728d8d9837 100644
--- a/py/showbc.c
+++ b/py/showbc.c
@@ -539,7 +539,7 @@ const byte *mp_bytecode_print_str(const byte *ip) {
                 printf("LOAD_FAST " UINT_FMT, (mp_uint_t)ip[-1] - MP_BC_LOAD_FAST_MULTI);
             } else if (ip[-1] < MP_BC_STORE_FAST_MULTI + 16) {
                 printf("STORE_FAST " UINT_FMT, (mp_uint_t)ip[-1] - MP_BC_STORE_FAST_MULTI);
-            } else if (ip[-1] < MP_BC_UNARY_OP_MULTI + 7) {
+            } else if (ip[-1] < MP_BC_UNARY_OP_MULTI + MP_UNARY_OP_NON_BYTECODE) {
                 printf("UNARY_OP " UINT_FMT, (mp_uint_t)ip[-1] - MP_BC_UNARY_OP_MULTI);
             } else if (ip[-1] < MP_BC_BINARY_OP_MULTI + 36) {
                 mp_uint_t op = ip[-1] - MP_BC_BINARY_OP_MULTI;
diff --git a/py/stackctrl.c b/py/stackctrl.c
index 00669121d3..b4ec15b0da 100644
--- a/py/stackctrl.c
+++ b/py/stackctrl.c
@@ -24,9 +24,6 @@
  * THE SOFTWARE.
  */
 
-#include "py/mpstate.h"
-#include "py/nlr.h"
-#include "py/obj.h"
 #include "py/runtime.h"
 #include "py/stackctrl.h"
 
diff --git a/py/stream.c b/py/stream.c
index 0029a59a75..453dee769f 100644
--- a/py/stream.c
+++ b/py/stream.c
@@ -28,7 +28,6 @@
 #include <string.h>
 #include <unistd.h>
 
-#include "py/nlr.h"
 #include "py/objstr.h"
 #include "py/stream.h"
 #include "py/runtime.h"
@@ -141,9 +140,6 @@ STATIC mp_obj_t stream_read_generic(size_t n_args, const mp_obj_t *args, byte fl
         mp_uint_t last_buf_offset = 0;
         while (more_bytes > 0) {
             char *p = vstr_add_len(&vstr, more_bytes);
-            if (p == NULL) {
-                mp_raise_msg(&mp_type_MemoryError, "out of memory");
-            }
             int error;
             mp_uint_t out_sz = mp_stream_read_exactly(args[0], p, more_bytes, &error);
             if (error != 0) {
@@ -380,10 +376,6 @@ STATIC mp_obj_t stream_unbuffered_readline(size_t n_args, const mp_obj_t *args)
 
     while (max_size == -1 || max_size-- != 0) {
         char *p = vstr_add_len(&vstr, 1);
-        if (p == NULL) {
-            mp_raise_msg(&mp_type_MemoryError, "out of memory");
-        }
-
         int error;
         mp_uint_t out_sz = stream_p->read(args[0], p, 1, &error);
         if (out_sz == MP_STREAM_ERROR) {
diff --git a/py/unicode.c b/py/unicode.c
index eddb007d5e..140b7ba712 100644
--- a/py/unicode.c
+++ b/py/unicode.c
@@ -182,3 +182,31 @@ mp_uint_t unichar_xdigit_value(unichar c) {
     }
     return n;
 }
+
+bool utf8_check(const byte *p, size_t len) {
+    uint8_t need = 0;
+    const byte *end = p + len;
+    for (; p < end; p++) {
+        byte c = *p;
+        if (need) {
+            if (c >= 0x80) {
+                need--;
+            } else {
+                // mismatch
+                return 0;
+            }
+        } else {
+            if (c >= 0xc0) {
+                if (c >= 0xf8) {
+                    // mismatch
+                    return 0;
+                }
+                need = (0xe5 >> ((c >> 3) & 0x6)) & 3;
+            } else if (c >= 0x80) {
+                // mismatch
+                return 0;
+            }
+        }
+    }
+    return need == 0; // no pending fragments allowed
+}
diff --git a/py/unicode.h b/py/unicode.h
index 19487a65ae..c1fb517894 100644
--- a/py/unicode.h
+++ b/py/unicode.h
@@ -30,5 +30,6 @@
 #include "py/misc.h"
 
 mp_uint_t utf8_ptr_to_index(const byte *s, const byte *ptr);
+bool utf8_check(const byte *p, size_t len);
 
 #endif // MICROPY_INCLUDED_PY_UNICODE_H
diff --git a/py/vm.c b/py/vm.c
index c7fc83d048..564200037a 100644
--- a/py/vm.c
+++ b/py/vm.c
@@ -29,8 +29,6 @@
 #include <string.h>
 #include <assert.h>
 
-#include "py/mpstate.h"
-#include "py/nlr.h"
 #include "py/emitglue.h"
 #include "py/objtype.h"
 #include "py/runtime.h"
@@ -1124,7 +1122,7 @@ unwind_return:
                             }
                         }
                         if (obj == MP_OBJ_NULL) {
-                            obj = mp_obj_new_exception_msg(&mp_type_RuntimeError, "No active exception to reraise");
+                            obj = mp_obj_new_exception_msg(&mp_type_RuntimeError, "no active exception to reraise");
                             RAISE(obj);
                         }
                     } else {
diff --git a/py/vmentrytable.h b/py/vmentrytable.h
index 352a6dc315..e634e2b417 100644
--- a/py/vmentrytable.h
+++ b/py/vmentrytable.h
@@ -109,7 +109,7 @@ static const void *const entry_table[256] = {
     [MP_BC_LOAD_CONST_SMALL_INT_MULTI ... MP_BC_LOAD_CONST_SMALL_INT_MULTI + 63] = &&entry_MP_BC_LOAD_CONST_SMALL_INT_MULTI,
     [MP_BC_LOAD_FAST_MULTI ... MP_BC_LOAD_FAST_MULTI + 15] = &&entry_MP_BC_LOAD_FAST_MULTI,
     [MP_BC_STORE_FAST_MULTI ... MP_BC_STORE_FAST_MULTI + 15] = &&entry_MP_BC_STORE_FAST_MULTI,
-    [MP_BC_UNARY_OP_MULTI ... MP_BC_UNARY_OP_MULTI + 6] = &&entry_MP_BC_UNARY_OP_MULTI,
+    [MP_BC_UNARY_OP_MULTI ... MP_BC_UNARY_OP_MULTI + MP_UNARY_OP_NON_BYTECODE - 1] = &&entry_MP_BC_UNARY_OP_MULTI,
     [MP_BC_BINARY_OP_MULTI ... MP_BC_BINARY_OP_MULTI + 35] = &&entry_MP_BC_BINARY_OP_MULTI,
 };
 
diff --git a/py/vstr.c b/py/vstr.c
index 8a00f6c6f7..869b278057 100644
--- a/py/vstr.c
+++ b/py/vstr.c
@@ -30,7 +30,7 @@
 #include <assert.h>
 
 #include "py/mpconfig.h"
-#include "py/misc.h"
+#include "py/runtime.h"
 #include "py/mpprint.h"
 
 // returned value is always at least 1 greater than argument
@@ -92,7 +92,9 @@ void vstr_free(vstr_t *vstr) {
 // Extend vstr strictly by requested size, return pointer to newly added chunk.
 char *vstr_extend(vstr_t *vstr, size_t size) {
     if (vstr->fixed_buf) {
-        return NULL;
+        // We can't reallocate, and the caller is expecting the space to
+        // be there, so the only safe option is to raise an exception.
+        mp_raise_msg(&mp_type_RuntimeError, NULL);
     }
     char *new_buf = m_renew(char, vstr->buf, vstr->alloc, vstr->alloc + size);
     char *p = new_buf + vstr->alloc;
@@ -101,17 +103,18 @@ char *vstr_extend(vstr_t *vstr, size_t size) {
     return p;
 }
 
-STATIC bool vstr_ensure_extra(vstr_t *vstr, size_t size) {
+STATIC void vstr_ensure_extra(vstr_t *vstr, size_t size) {
     if (vstr->len + size > vstr->alloc) {
         if (vstr->fixed_buf) {
-            return false;
+            // We can't reallocate, and the caller is expecting the space to
+            // be there, so the only safe option is to raise an exception.
+            mp_raise_msg(&mp_type_RuntimeError, NULL);
         }
         size_t new_alloc = ROUND_ALLOC((vstr->len + size) + 16);
         char *new_buf = m_renew(char, vstr->buf, vstr->alloc, new_alloc);
         vstr->alloc = new_alloc;
         vstr->buf = new_buf;
     }
-    return true;
 }
 
 void vstr_hint_size(vstr_t *vstr, size_t size) {
@@ -119,9 +122,7 @@ void vstr_hint_size(vstr_t *vstr, size_t size) {
 }
 
 char *vstr_add_len(vstr_t *vstr, size_t len) {
-    if (!vstr_ensure_extra(vstr, len)) {
-        return NULL;
-    }
+    vstr_ensure_extra(vstr, len);
     char *buf = vstr->buf + vstr->len;
     vstr->len += len;
     return buf;
@@ -131,9 +132,7 @@ char *vstr_add_len(vstr_t *vstr, size_t len) {
 char *vstr_null_terminated_str(vstr_t *vstr) {
     // If there's no more room, add single byte
     if (vstr->alloc == vstr->len) {
-        if (vstr_extend(vstr, 1) == NULL) {
-            return NULL;
-        }
+        vstr_extend(vstr, 1);
     }
     vstr->buf[vstr->len] = '\0';
     return vstr->buf;
@@ -141,9 +140,6 @@ char *vstr_null_terminated_str(vstr_t *vstr) {
 
 void vstr_add_byte(vstr_t *vstr, byte b) {
     byte *buf = (byte*)vstr_add_len(vstr, 1);
-    if (buf == NULL) {
-        return;
-    }
     buf[0] = b;
 }
 
@@ -153,31 +149,19 @@ void vstr_add_char(vstr_t *vstr, unichar c) {
     // Is it worth just calling vstr_add_len(vstr, 4)?
     if (c < 0x80) {
         byte *buf = (byte*)vstr_add_len(vstr, 1);
-        if (buf == NULL) {
-            return;
-        }
         *buf = (byte)c;
     } else if (c < 0x800) {
         byte *buf = (byte*)vstr_add_len(vstr, 2);
-        if (buf == NULL) {
-            return;
-        }
         buf[0] = (c >> 6) | 0xC0;
         buf[1] = (c & 0x3F) | 0x80;
     } else if (c < 0x10000) {
         byte *buf = (byte*)vstr_add_len(vstr, 3);
-        if (buf == NULL) {
-            return;
-        }
         buf[0] = (c >> 12) | 0xE0;
         buf[1] = ((c >> 6) & 0x3F) | 0x80;
         buf[2] = (c & 0x3F) | 0x80;
     } else {
         assert(c < 0x110000);
         byte *buf = (byte*)vstr_add_len(vstr, 4);
-        if (buf == NULL) {
-            return;
-        }
         buf[0] = (c >> 18) | 0xF0;
         buf[1] = ((c >> 12) & 0x3F) | 0x80;
         buf[2] = ((c >> 6) & 0x3F) | 0x80;
@@ -193,16 +177,7 @@ void vstr_add_str(vstr_t *vstr, const char *str) {
 }
 
 void vstr_add_strn(vstr_t *vstr, const char *str, size_t len) {
-    if (!vstr_ensure_extra(vstr, len)) {
-        // if buf is fixed, we got here because there isn't enough room left
-        // so just try to copy as much as we can, with room for a possible null byte
-        if (vstr->fixed_buf && vstr->len < vstr->alloc) {
-            len = vstr->alloc - vstr->len;
-            goto copy;
-        }
-        return;
-    }
-copy:
+    vstr_ensure_extra(vstr, len);
     memmove(vstr->buf + vstr->len, str, len);
     vstr->len += len;
 }
@@ -214,9 +189,7 @@ STATIC char *vstr_ins_blank_bytes(vstr_t *vstr, size_t byte_pos, size_t byte_len
     }
     if (byte_len > 0) {
         // ensure room for the new bytes
-        if (!vstr_ensure_extra(vstr, byte_len)) {
-            return NULL;
-        }
+        vstr_ensure_extra(vstr, byte_len);
         // copy up the string to make room for the new bytes
         memmove(vstr->buf + byte_pos + byte_len, vstr->buf + byte_pos, l - byte_pos);
         // increase the length
@@ -227,17 +200,13 @@ STATIC char *vstr_ins_blank_bytes(vstr_t *vstr, size_t byte_pos, size_t byte_len
 
 void vstr_ins_byte(vstr_t *vstr, size_t byte_pos, byte b) {
     char *s = vstr_ins_blank_bytes(vstr, byte_pos, 1);
-    if (s != NULL) {
-        *s = b;
-    }
+    *s = b;
 }
 
 void vstr_ins_char(vstr_t *vstr, size_t char_pos, unichar chr) {
     // TODO UNICODE
     char *s = vstr_ins_blank_bytes(vstr, char_pos, 1);
-    if (s != NULL) {
-        *s = chr;
-    }
+    *s = chr;
 }
 
 void vstr_cut_head_bytes(vstr_t *vstr, size_t bytes_to_cut) {
diff --git a/py/warning.c b/py/warning.c
index 46b31ecca7..12d0f9c99b 100644
--- a/py/warning.c
+++ b/py/warning.c
@@ -35,9 +35,9 @@
 void mp_warning(const char *msg, ...) {
     va_list args;
     va_start(args, msg);
-    mp_print_str(&mp_plat_print, "Warning: ");
-    mp_vprintf(&mp_plat_print, msg, args);
-    mp_print_str(&mp_plat_print, "\n");
+    mp_print_str(MICROPY_ERROR_PRINTER, "Warning: ");
+    mp_vprintf(MICROPY_ERROR_PRINTER, msg, args);
+    mp_print_str(MICROPY_ERROR_PRINTER, "\n");
     va_end(args);
 }
 
diff --git a/shared-bindings/nvm/ByteArray.c b/shared-bindings/nvm/ByteArray.c
index 361d03c55d..f4e0463781 100644
--- a/shared-bindings/nvm/ByteArray.c
+++ b/shared-bindings/nvm/ByteArray.c
@@ -53,7 +53,7 @@
 //|
 //|     Return the length. This is used by (`len`)
 //|
-STATIC mp_obj_t nvm_bytearray_unary_op(mp_uint_t op, mp_obj_t self_in) {
+STATIC mp_obj_t nvm_bytearray_unary_op(mp_unary_op_t op, mp_obj_t self_in) {
     nvm_bytearray_obj_t *self = MP_OBJ_TO_PTR(self_in);
     uint16_t len = common_hal_nvm_bytearray_get_length(self);
     switch (op) {
diff --git a/shared-bindings/pulseio/PulseIn.c b/shared-bindings/pulseio/PulseIn.c
index da9e6ac2c5..8be62f4bfc 100644
--- a/shared-bindings/pulseio/PulseIn.c
+++ b/shared-bindings/pulseio/PulseIn.c
@@ -228,7 +228,7 @@ const mp_obj_property_t pulseio_pulsein_maxlen_obj = {
 //|       pulses = pulseio.PulseIn(pin)
 //|       print(len(pulses))
 //|
-STATIC mp_obj_t pulsein_unary_op(mp_uint_t op, mp_obj_t self_in) {
+STATIC mp_obj_t pulsein_unary_op(mp_unary_op_t op, mp_obj_t self_in) {
     pulseio_pulsein_obj_t *self = MP_OBJ_TO_PTR(self_in);
     raise_error_if_deinited(common_hal_pulseio_pulsein_deinited(self));
     uint16_t len = common_hal_pulseio_pulsein_get_len(self);
diff --git a/stmhal/boards/NUCLEO_F401RE/stm32f4xx_hal_conf.h b/stmhal/boards/NUCLEO_F401RE/stm32f4xx_hal_conf.h
deleted file mode 100644
index c20421f0ff..0000000000
--- a/stmhal/boards/NUCLEO_F401RE/stm32f4xx_hal_conf.h
+++ /dev/null
@@ -1,413 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_conf.h
-  * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    19-June-2014
-  * @brief   HAL configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_CONF_H
-#define __STM32F4xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-// This board doesn't really have USB, but the stmhal codebase doesn't build
-// without some USB defined, so we leave this on for now.
-#define USE_USB_FS
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver 
-  */
-#define HAL_MODULE_ENABLED
-#define HAL_ADC_MODULE_ENABLED
-#define HAL_CAN_MODULE_ENABLED
-/* #define HAL_CRC_MODULE_ENABLED */
-/* #define HAL_CRYP_MODULE_ENABLED */
-#define HAL_DAC_MODULE_ENABLED
-/* #define HAL_DCMI_MODULE_ENABLED */
-#define HAL_DMA_MODULE_ENABLED
-/* #define HAL_DMA2D_MODULE_ENABLED */
-/* #define HAL_ETH_MODULE_ENABLED */
-#define HAL_FLASH_MODULE_ENABLED
-/* #define HAL_NAND_MODULE_ENABLED */
-/* #define HAL_NOR_MODULE_ENABLED */
-/* #define HAL_PCCARD_MODULE_ENABLED */
-/* #define HAL_SRAM_MODULE_ENABLED */
-/* #define HAL_SDRAM_MODULE_ENABLED */
-/* #define HAL_HASH_MODULE_ENABLED */
-#define HAL_GPIO_MODULE_ENABLED
-#define HAL_I2C_MODULE_ENABLED
-/* #define HAL_I2S_MODULE_ENABLED */
-/* #define HAL_IWDG_MODULE_ENABLED */
-/* #define HAL_LTDC_MODULE_ENABLED */
-#define HAL_PWR_MODULE_ENABLED
-#define HAL_RCC_MODULE_ENABLED
-#define HAL_RNG_MODULE_ENABLED
-#define HAL_RTC_MODULE_ENABLED
-/* #define HAL_SAI_MODULE_ENABLED */
-#define HAL_SD_MODULE_ENABLED
-#define HAL_SPI_MODULE_ENABLED
-#define HAL_TIM_MODULE_ENABLED
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED */
-/* #define HAL_IRDA_MODULE_ENABLED */
-/* #define HAL_SMARTCARD_MODULE_ENABLED */
-/* #define HAL_WWDG_MODULE_ENABLED */
-#define HAL_CORTEX_MODULE_ENABLED
-#define HAL_PCD_MODULE_ENABLED
-/* #define HAL_HCD_MODULE_ENABLED */
-
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  ((uint32_t)40000)    
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source 
-  *        frequency, this source is inserted directly through I2S_CKIN pad. 
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */     
-#define  VDD_VALUE                    ((uint32_t)3300) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            ((uint32_t)0x00) /*!< tick interrupt priority */
-#define  USE_RTOS                     0
-#define  PREFETCH_ENABLE              1
-#define  INSTRUCTION_CACHE_ENABLE     1
-#define  DATA_CACHE_ENABLE            1
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1 */
-
-/* ################## Ethernet peripheral configuration ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2
-#define MAC_ADDR1   0
-#define MAC_ADDR2   0
-#define MAC_ADDR3   0
-#define MAC_ADDR4   0
-#define MAC_ADDR5   0
-
-/* Definition of the Ethernet driver buffers size and count */   
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    ((uint32_t)4)       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    ((uint32_t)4)       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-
-/* DP83848 PHY Address*/ 
-#define DP83848_PHY_ADDRESS             0x01
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
-#define PHY_RESET_DELAY                 ((uint32_t)0x000000FF)
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
-
-#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
-#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
- 
-#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-  
-/* Section 4: Extended PHY Registers */
-
-#define PHY_SR                          ((uint16_t)0x10)    /*!< PHY status register Offset                      */
-#define PHY_MICR                        ((uint16_t)0x11)    /*!< MII Interrupt Control Register                  */
-#define PHY_MISR                        ((uint16_t)0x12)    /*!< MII Interrupt Status and Misc. Control Register */
- 
-#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
-#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
-
-#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
-#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
-
-#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
-#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file 
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32f4xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32f4xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-   
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32f4xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32f4xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32f4xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32f4xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f4xx_hal_cryp.h" 
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32f4xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32f4xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f4xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32f4xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
- 
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f4xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f4xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_PCCARD_MODULE_ENABLED
-  #include "stm32f4xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */ 
-  
-#ifdef HAL_SDRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */      
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f4xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f4xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f4xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f4xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f4xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f4xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f4xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f4xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f4xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f4xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f4xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f4xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f4xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f4xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f4xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f4xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f4xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-   
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_CONF_H */
- 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/boards/PYBV4/stm32f4xx_hal_conf.h b/stmhal/boards/PYBV4/stm32f4xx_hal_conf.h
deleted file mode 100644
index 8941e8290f..0000000000
--- a/stmhal/boards/PYBV4/stm32f4xx_hal_conf.h
+++ /dev/null
@@ -1,411 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_conf.h
-  * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    19-June-2014
-  * @brief   HAL configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_CONF_H
-#define __STM32F4xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-#define USE_USB_FS
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver 
-  */
-#define HAL_MODULE_ENABLED
-#define HAL_ADC_MODULE_ENABLED
-#define HAL_CAN_MODULE_ENABLED
-/* #define HAL_CRC_MODULE_ENABLED */
-/* #define HAL_CRYP_MODULE_ENABLED */
-#define HAL_DAC_MODULE_ENABLED
-/* #define HAL_DCMI_MODULE_ENABLED */
-#define HAL_DMA_MODULE_ENABLED
-/* #define HAL_DMA2D_MODULE_ENABLED */
-/* #define HAL_ETH_MODULE_ENABLED */
-#define HAL_FLASH_MODULE_ENABLED
-/* #define HAL_NAND_MODULE_ENABLED */
-/* #define HAL_NOR_MODULE_ENABLED */
-/* #define HAL_PCCARD_MODULE_ENABLED */
-/* #define HAL_SRAM_MODULE_ENABLED */
-/* #define HAL_SDRAM_MODULE_ENABLED */
-/* #define HAL_HASH_MODULE_ENABLED */
-#define HAL_GPIO_MODULE_ENABLED
-#define HAL_I2C_MODULE_ENABLED
-/* #define HAL_I2S_MODULE_ENABLED */
-/* #define HAL_IWDG_MODULE_ENABLED */
-/* #define HAL_LTDC_MODULE_ENABLED */
-#define HAL_PWR_MODULE_ENABLED
-#define HAL_RCC_MODULE_ENABLED
-#define HAL_RNG_MODULE_ENABLED
-#define HAL_RTC_MODULE_ENABLED
-/* #define HAL_SAI_MODULE_ENABLED */
-#define HAL_SD_MODULE_ENABLED
-#define HAL_SPI_MODULE_ENABLED
-#define HAL_TIM_MODULE_ENABLED
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED */
-/* #define HAL_IRDA_MODULE_ENABLED */
-/* #define HAL_SMARTCARD_MODULE_ENABLED */
-/* #define HAL_WWDG_MODULE_ENABLED */
-#define HAL_CORTEX_MODULE_ENABLED
-#define HAL_PCD_MODULE_ENABLED
-/* #define HAL_HCD_MODULE_ENABLED */
-
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  ((uint32_t)40000)    
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source 
-  *        frequency, this source is inserted directly through I2S_CKIN pad. 
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */     
-#define  VDD_VALUE                    ((uint32_t)3300) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            ((uint32_t)0x00) /*!< tick interrupt priority */
-#define  USE_RTOS                     0
-#define  PREFETCH_ENABLE              1
-#define  INSTRUCTION_CACHE_ENABLE     1
-#define  DATA_CACHE_ENABLE            1
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1 */
-
-/* ################## Ethernet peripheral configuration ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2
-#define MAC_ADDR1   0
-#define MAC_ADDR2   0
-#define MAC_ADDR3   0
-#define MAC_ADDR4   0
-#define MAC_ADDR5   0
-
-/* Definition of the Ethernet driver buffers size and count */   
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    ((uint32_t)4)       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    ((uint32_t)4)       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-
-/* DP83848 PHY Address*/ 
-#define DP83848_PHY_ADDRESS             0x01
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
-#define PHY_RESET_DELAY                 ((uint32_t)0x000000FF)
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
-
-#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
-#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
- 
-#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-  
-/* Section 4: Extended PHY Registers */
-
-#define PHY_SR                          ((uint16_t)0x10)    /*!< PHY status register Offset                      */
-#define PHY_MICR                        ((uint16_t)0x11)    /*!< MII Interrupt Control Register                  */
-#define PHY_MISR                        ((uint16_t)0x12)    /*!< MII Interrupt Status and Misc. Control Register */
- 
-#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
-#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
-
-#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
-#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
-
-#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
-#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file 
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32f4xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32f4xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-   
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32f4xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32f4xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32f4xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32f4xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f4xx_hal_cryp.h" 
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32f4xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32f4xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f4xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32f4xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
- 
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f4xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f4xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_PCCARD_MODULE_ENABLED
-  #include "stm32f4xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */ 
-  
-#ifdef HAL_SDRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */      
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f4xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f4xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f4xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f4xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f4xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f4xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f4xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f4xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f4xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f4xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f4xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f4xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f4xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f4xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f4xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f4xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f4xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-   
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_CONF_H */
- 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/boards/STM32F4DISC/stm32f4xx_hal_conf.h b/stmhal/boards/STM32F4DISC/stm32f4xx_hal_conf.h
deleted file mode 100644
index 8941e8290f..0000000000
--- a/stmhal/boards/STM32F4DISC/stm32f4xx_hal_conf.h
+++ /dev/null
@@ -1,411 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_conf.h
-  * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    19-June-2014
-  * @brief   HAL configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_CONF_H
-#define __STM32F4xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-#define USE_USB_FS
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver 
-  */
-#define HAL_MODULE_ENABLED
-#define HAL_ADC_MODULE_ENABLED
-#define HAL_CAN_MODULE_ENABLED
-/* #define HAL_CRC_MODULE_ENABLED */
-/* #define HAL_CRYP_MODULE_ENABLED */
-#define HAL_DAC_MODULE_ENABLED
-/* #define HAL_DCMI_MODULE_ENABLED */
-#define HAL_DMA_MODULE_ENABLED
-/* #define HAL_DMA2D_MODULE_ENABLED */
-/* #define HAL_ETH_MODULE_ENABLED */
-#define HAL_FLASH_MODULE_ENABLED
-/* #define HAL_NAND_MODULE_ENABLED */
-/* #define HAL_NOR_MODULE_ENABLED */
-/* #define HAL_PCCARD_MODULE_ENABLED */
-/* #define HAL_SRAM_MODULE_ENABLED */
-/* #define HAL_SDRAM_MODULE_ENABLED */
-/* #define HAL_HASH_MODULE_ENABLED */
-#define HAL_GPIO_MODULE_ENABLED
-#define HAL_I2C_MODULE_ENABLED
-/* #define HAL_I2S_MODULE_ENABLED */
-/* #define HAL_IWDG_MODULE_ENABLED */
-/* #define HAL_LTDC_MODULE_ENABLED */
-#define HAL_PWR_MODULE_ENABLED
-#define HAL_RCC_MODULE_ENABLED
-#define HAL_RNG_MODULE_ENABLED
-#define HAL_RTC_MODULE_ENABLED
-/* #define HAL_SAI_MODULE_ENABLED */
-#define HAL_SD_MODULE_ENABLED
-#define HAL_SPI_MODULE_ENABLED
-#define HAL_TIM_MODULE_ENABLED
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED */
-/* #define HAL_IRDA_MODULE_ENABLED */
-/* #define HAL_SMARTCARD_MODULE_ENABLED */
-/* #define HAL_WWDG_MODULE_ENABLED */
-#define HAL_CORTEX_MODULE_ENABLED
-#define HAL_PCD_MODULE_ENABLED
-/* #define HAL_HCD_MODULE_ENABLED */
-
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  ((uint32_t)40000)    
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source 
-  *        frequency, this source is inserted directly through I2S_CKIN pad. 
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */     
-#define  VDD_VALUE                    ((uint32_t)3300) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            ((uint32_t)0x00) /*!< tick interrupt priority */
-#define  USE_RTOS                     0
-#define  PREFETCH_ENABLE              1
-#define  INSTRUCTION_CACHE_ENABLE     1
-#define  DATA_CACHE_ENABLE            1
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1 */
-
-/* ################## Ethernet peripheral configuration ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2
-#define MAC_ADDR1   0
-#define MAC_ADDR2   0
-#define MAC_ADDR3   0
-#define MAC_ADDR4   0
-#define MAC_ADDR5   0
-
-/* Definition of the Ethernet driver buffers size and count */   
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    ((uint32_t)4)       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    ((uint32_t)4)       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-
-/* DP83848 PHY Address*/ 
-#define DP83848_PHY_ADDRESS             0x01
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
-#define PHY_RESET_DELAY                 ((uint32_t)0x000000FF)
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
-
-#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
-#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
- 
-#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-  
-/* Section 4: Extended PHY Registers */
-
-#define PHY_SR                          ((uint16_t)0x10)    /*!< PHY status register Offset                      */
-#define PHY_MICR                        ((uint16_t)0x11)    /*!< MII Interrupt Control Register                  */
-#define PHY_MISR                        ((uint16_t)0x12)    /*!< MII Interrupt Status and Misc. Control Register */
- 
-#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
-#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
-
-#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
-#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
-
-#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
-#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file 
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32f4xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32f4xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-   
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32f4xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32f4xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32f4xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32f4xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f4xx_hal_cryp.h" 
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32f4xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32f4xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f4xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32f4xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
- 
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f4xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f4xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_PCCARD_MODULE_ENABLED
-  #include "stm32f4xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */ 
-  
-#ifdef HAL_SDRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */      
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f4xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f4xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f4xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f4xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f4xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f4xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f4xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f4xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f4xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f4xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f4xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f4xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f4xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f4xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f4xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f4xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f4xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-   
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_CONF_H */
- 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/cmsis/stm32f401xc.h b/stmhal/cmsis/stm32f401xc.h
deleted file mode 100644
index 1179eca4c9..0000000000
--- a/stmhal/cmsis/stm32f401xc.h
+++ /dev/null
@@ -1,4805 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f401xc.h
-  * @author  MCD Application Team
-  * @version V2.5.1
-  * @date    28-June-2016
-  * @brief   CMSIS STM32F401xCxx Device Peripheral Access Layer Header File.
-  *
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - peripherals registers declarations and bits definition
-  *           - Macros to access peripheral’s registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f401xc
-  * @{
-  */
-    
-#ifndef __STM32F401xC_H
-#define __STM32F401xC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-  
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-
-/**
-  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
-  */
-#define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */
-#define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */
-#define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1U       /*!< FPU present                                   */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32F4XX Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-typedef enum
-{
-/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
-  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
-/******  STM32 specific Interrupt Numbers **********************************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
-  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
-  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
-  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
-  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
-  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
-  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
-  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
-  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
-  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
-  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
-  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
-  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
-  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */  
-  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
-  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
-  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
-  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
-  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
-  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
-  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
-  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
-  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
-  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
-  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
-  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
-  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
-  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
-  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
-  FPU_IRQn                    = 81,      /*!< FPU global interrupt                                             */
-  SPI4_IRQn                   = 84       /*!< SPI4 global Interrupt                                            */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
-#include "system_stm32f4xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */      
-  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
-  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
-  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
-  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
-  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
-  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
-  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
-  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
-  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
-  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
-  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
-  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
-  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
-  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
-  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
-                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief CRC calculation unit 
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
-  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */
-  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
-  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
-  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
-} CRC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
-  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
-  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
-  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
-  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
-  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
-  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
-  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
-  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
-} DMA_Stream_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
-  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
-  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
-  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
-} DMA_TypeDef;
-
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
-  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
-  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
-  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
-  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
-  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-
-typedef struct
-{
-  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */
-  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */
-  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */
-  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */
-  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */
-  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief General Purpose I/O
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
-  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
-  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
-  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
-  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
-  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
-  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
-  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/** 
-  * @brief System configuration controller
-  */
-  
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */ 
-  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */
-  __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */
-  __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */
-  __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */
-  __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */
-  __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
-  __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
-  __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
-  __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
-  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
-  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
-  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
-  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
-  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
-  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
-  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
-  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
-  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
-  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
-  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
-  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
-  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
-  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
-  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
-  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
-  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
-  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
-  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
-  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
-  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
-  uint32_t      RESERVED7[1];  /*!< Reserved, 0x88                                                                    */
-  __IO uint32_t DCKCFGR;       /*!< RCC DCKCFGR configuration register,                          Address offset: 0x8C */
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-
-typedef struct
-{
-  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
-  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
-  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
-  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
-  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
-  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
-  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */
-  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
-  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */
-  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
-  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */
-  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */
-  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */
-  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */
-  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
-  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */
-  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
-  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
-  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
-  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
-  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
-  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
-  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
-  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
-  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
-  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
-  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
-  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
-  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
-  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
-  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
-  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
-  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
-  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
-  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
-  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
-  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
-} RTC_TypeDef;
-
-
-/** 
-  * @brief SD host Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t POWER;          /*!< SDIO power control register,    Address offset: 0x00 */
-  __IO uint32_t CLKCR;          /*!< SDI clock control register,     Address offset: 0x04 */
-  __IO uint32_t ARG;            /*!< SDIO argument register,         Address offset: 0x08 */
-  __IO uint32_t CMD;            /*!< SDIO command register,          Address offset: 0x0C */
-  __I uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */
-  __I uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */
-  __I uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */
-  __I uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */
-  __I uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */
-  __IO uint32_t DTIMER;         /*!< SDIO data timer register,       Address offset: 0x24 */
-  __IO uint32_t DLEN;           /*!< SDIO data length register,      Address offset: 0x28 */
-  __IO uint32_t DCTRL;          /*!< SDIO data control register,     Address offset: 0x2C */
-  __I uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */
-  __I uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */
-  __IO uint32_t ICR;            /*!< SDIO interrupt clear register,  Address offset: 0x38 */
-  __IO uint32_t MASK;           /*!< SDIO mask register,             Address offset: 0x3C */
-  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
-  __I uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */
-  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
-  __IO uint32_t FIFO;           /*!< SDIO data FIFO register,        Address offset: 0x80 */
-} SDIO_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
-  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
-  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
-  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
- 
-/** 
-  * @brief __USB_OTG_Core_register
-  */
-typedef struct
-{
-  __IO uint32_t GOTGCTL;              /*!<  USB_OTG Control and Status Register    Address offset : 0x00      */
-  __IO uint32_t GOTGINT;              /*!<  USB_OTG Interrupt Register             Address offset : 0x04      */
-  __IO uint32_t GAHBCFG;              /*!<  Core AHB Configuration Register        Address offset : 0x08      */
-  __IO uint32_t GUSBCFG;              /*!<  Core USB Configuration Register        Address offset : 0x0C      */
-  __IO uint32_t GRSTCTL;              /*!<  Core Reset Register                    Address offset : 0x10      */
-  __IO uint32_t GINTSTS;              /*!<  Core Interrupt Register                Address offset : 0x14      */
-  __IO uint32_t GINTMSK;              /*!<  Core Interrupt Mask Register           Address offset : 0x18      */
-  __IO uint32_t GRXSTSR;              /*!<  Receive Sts Q Read Register            Address offset : 0x1C      */
-  __IO uint32_t GRXSTSP;              /*!<  Receive Sts Q Read & POP Register      Address offset : 0x20      */
-  __IO uint32_t GRXFSIZ;              /* Receive FIFO Size Register                Address offset : 0x24      */
-  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!<  EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28    */
-  __IO uint32_t HNPTXSTS;             /*!<  Non Periodic Tx FIFO/Queue Sts reg     Address offset : 0x2C      */
-  uint32_t Reserved30[2];             /* Reserved                                  Address offset : 0x30      */
-  __IO uint32_t GCCFG;                /*!<  General Purpose IO Register            Address offset : 0x38      */
-  __IO uint32_t CID;                  /*!< User ID Register                          Address offset : 0x3C      */
-  uint32_t  Reserved40[48];           /*!< Reserved                                  Address offset : 0x40-0xFF */
-  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg            Address offset : 0x100 */
-  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */
-}
-USB_OTG_GlobalTypeDef;
-
-
-
-/** 
-  * @brief __device_Registers
-  */
-typedef struct 
-{
-  __IO uint32_t DCFG;         /*!< dev Configuration Register   Address offset : 0x800 */
-  __IO uint32_t DCTL;         /*!< dev Control Register         Address offset : 0x804 */
-  __IO uint32_t DSTS;         /*!< dev Status Register (RO)     Address offset : 0x808 */
-  uint32_t Reserved0C;        /*!< Reserved                     Address offset : 0x80C */
-  __IO uint32_t DIEPMSK;      /* !< dev IN Endpoint Mask        Address offset : 0x810 */
-  __IO uint32_t DOEPMSK;      /*!< dev OUT Endpoint Mask        Address offset : 0x814 */
-  __IO uint32_t DAINT;        /*!< dev All Endpoints Itr Reg    Address offset : 0x818 */
-  __IO uint32_t DAINTMSK;     /*!< dev All Endpoints Itr Mask   Address offset : 0x81C */
-  uint32_t  Reserved20;       /*!< Reserved                     Address offset : 0x820 */
-  uint32_t Reserved9;         /*!< Reserved                     Address offset : 0x824 */
-  __IO uint32_t DVBUSDIS;     /*!< dev VBUS discharge Register  Address offset : 0x828 */
-  __IO uint32_t DVBUSPULSE;   /*!< dev VBUS Pulse Register      Address offset : 0x82C */
-  __IO uint32_t DTHRCTL;      /*!< dev thr                      Address offset : 0x830 */
-  __IO uint32_t DIEPEMPMSK;   /*!< dev empty msk                Address offset : 0x834 */
-  __IO uint32_t DEACHINT;     /*!< dedicated EP interrupt       Address offset : 0x838 */
-  __IO uint32_t DEACHMSK;     /*!< dedicated EP msk             Address offset : 0x83C */  
-  uint32_t Reserved40;        /*!< dedicated EP mask            Address offset : 0x840 */
-  __IO uint32_t DINEP1MSK;    /*!< dedicated EP mask            Address offset : 0x844 */
-  uint32_t  Reserved44[15];   /*!< Reserved                     Address offset : 0x844-0x87C */
-  __IO uint32_t DOUTEP1MSK;   /*!< dedicated EP msk             Address offset : 0x884 */   
-}
-USB_OTG_DeviceTypeDef;
-
-
-/** 
-  * @brief __IN_Endpoint-Specific_Register
-  */
-typedef struct 
-{
-  __IO uint32_t DIEPCTL;        /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h     */
-  uint32_t Reserved04;          /* Reserved                       900h + (ep_num * 20h) + 04h  */
-  __IO uint32_t DIEPINT;        /* dev IN Endpoint Itr Reg     900h + (ep_num * 20h) + 08h     */
-  uint32_t Reserved0C;          /* Reserved                       900h + (ep_num * 20h) + 0Ch  */
-  __IO uint32_t DIEPTSIZ;       /* IN Endpoint Txfer Size   900h + (ep_num * 20h) + 10h        */
-  __IO uint32_t DIEPDMA;        /* IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h  */
-  __IO uint32_t DTXFSTS;        /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h   */
-  uint32_t Reserved18;           /* Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
-}
-USB_OTG_INEndpointTypeDef;
-
-
-/** 
-  * @brief __OUT_Endpoint-Specific_Registers
-  */
-typedef struct 
-{
-  __IO uint32_t DOEPCTL;       /* dev OUT Endpoint Control Reg  B00h + (ep_num * 20h) + 00h*/
-  uint32_t Reserved04;         /* Reserved                      B00h + (ep_num * 20h) + 04h*/
-  __IO uint32_t DOEPINT;       /* dev OUT Endpoint Itr Reg      B00h + (ep_num * 20h) + 08h*/
-  uint32_t Reserved0C;         /* Reserved                      B00h + (ep_num * 20h) + 0Ch*/
-  __IO uint32_t DOEPTSIZ;      /* dev OUT Endpoint Txfer Size   B00h + (ep_num * 20h) + 10h*/
-  __IO uint32_t DOEPDMA;       /* dev OUT Endpoint DMA Address  B00h + (ep_num * 20h) + 14h*/
-  uint32_t Reserved18[2];      /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
-}
-USB_OTG_OUTEndpointTypeDef;
-
-
-/** 
-  * @brief __Host_Mode_Register_Structures
-  */
-typedef struct 
-{
-  __IO uint32_t HCFG;             /* Host Configuration Register    400h*/
-  __IO uint32_t HFIR;             /* Host Frame Interval Register   404h*/
-  __IO uint32_t HFNUM;            /* Host Frame Nbr/Frame Remaining 408h*/
-  uint32_t Reserved40C;           /* Reserved                       40Ch*/
-  __IO uint32_t HPTXSTS;          /* Host Periodic Tx FIFO/ Queue Status 410h*/
-  __IO uint32_t HAINT;            /* Host All Channels Interrupt Register 414h*/
-  __IO uint32_t HAINTMSK;         /* Host All Channels Interrupt Mask 418h*/
-}
-USB_OTG_HostTypeDef;
-
-
-/** 
-  * @brief __Host_Channel_Specific_Registers
-  */
-typedef struct
-{
-  __IO uint32_t HCCHAR;
-  __IO uint32_t HCSPLT;
-  __IO uint32_t HCINT;
-  __IO uint32_t HCINTMSK;
-  __IO uint32_t HCTSIZ;
-  __IO uint32_t HCDMA;
-  uint32_t Reserved[2];
-}
-USB_OTG_HostChannelTypeDef;
-
-    
-/** 
-  * @brief Peripheral_memory_map
-  */
-#define FLASH_BASE            0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region                        */
-#define SRAM1_BASE            0x20000000U /*!< SRAM1(64 KB) base address in the alias region                             */
-#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region                               */
-#define BKPSRAM_BASE          0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region                        */
-#define SRAM1_BB_BASE         0x22000000U /*!< SRAM1(64 KB) base address in the bit-band region                          */
-#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region                            */
-#define BKPSRAM_BB_BASE       0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region                     */
-#define FLASH_END             0x0803FFFFU /*!< FLASH end address */
-
-/* Legacy defines */
-#define SRAM_BASE             SRAM1_BASE
-#define SRAM_BB_BASE          SRAM1_BB_BASE
-
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000U)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)
-#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400U)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)
-#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000U)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)
-#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)
-
-/*!< APB2 peripherals */
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000U)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x1000U)
-#define USART6_BASE           (APB2PERIPH_BASE + 0x1400U)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000U)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x2300U)
-#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00U)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)
-#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400U)
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800U)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00U)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000U)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400U)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800U)
-
-/*!< AHB1 peripherals */
-#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000U)
-#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400U)
-#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800U)
-#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00U)
-#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000U)
-#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00U)
-#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)
-#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800U)
-#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00U)
-#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000U)
-#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010U)
-#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028U)
-#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040U)
-#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058U)
-#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070U)
-#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088U)
-#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0U)
-#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8U)
-#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400U)
-#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010U)
-#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028U)
-#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040U)
-#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058U)
-#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070U)
-#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088U)
-#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0U)
-#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)
-
-/* Debug MCU registers base address */
-#define DBGMCU_BASE           0xE0042000U
-
-/*!< USB registers base address */
-#define USB_OTG_FS_PERIPH_BASE               0x50000000U
-
-#define USB_OTG_GLOBAL_BASE                  0x000U
-#define USB_OTG_DEVICE_BASE                  0x800U
-#define USB_OTG_IN_ENDPOINT_BASE             0x900U
-#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U
-#define USB_OTG_EP_REG_SIZE                  0x20U
-#define USB_OTG_HOST_BASE                    0x400U
-#define USB_OTG_HOST_PORT_BASE               0x440U
-#define USB_OTG_HOST_CHANNEL_BASE            0x500U
-#define USB_OTG_HOST_CHANNEL_SIZE            0x20U
-#define USB_OTG_PCGCCTL_BASE                 0xE00U
-#define USB_OTG_FIFO_BASE                    0x1000U
-#define USB_OTG_FIFO_SIZE                    0x1000U
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define USART6              ((USART_TypeDef *) USART6_BASE)
-#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define SPI4                ((SPI_TypeDef *) SPI4_BASE) 
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
-#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
-#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
-#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
-#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
-#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
-#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
-#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
-#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
-#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
-#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
-#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
-#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
-#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
-#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
-
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers_Bits_Definition               */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Analog to Digital Converter                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          0x00000001U       /*!<Analog watchdog flag */
-#define  ADC_SR_EOC                          0x00000002U       /*!<End of conversion */
-#define  ADC_SR_JEOC                         0x00000004U       /*!<Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        0x00000008U       /*!<Injected channel Start flag */
-#define  ADC_SR_STRT                         0x00000010U       /*!<Regular channel Start flag */
-#define  ADC_SR_OVR                          0x00000020U       /*!<Overrun flag */
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
-#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels */
-#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels */
-#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution) */
-#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
-  
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion */
-#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode */
-#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC) */
-#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection */
-#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment */
-#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      0xFFFFU            /*!<Injected data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag */
-#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion */
-#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag */
-#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag */
-#define  ADC_CSR_OVR1                        0x00000020U        /*!<ADC1 DMA overrun  flag */
-#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag */
-#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion */
-#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag */
-#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag */
-#define  ADC_CSR_OVR2                        0x00002000U        /*!<ADC2 DMA overrun  flag */
-#define  ADC_CSR_AWD3                        0x00010000U        /*!<ADC3 Analog watchdog flag */
-#define  ADC_CSR_EOC3                        0x00020000U        /*!<ADC3 End of conversion */
-#define  ADC_CSR_JEOC3                       0x00040000U        /*!<ADC3 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT3                      0x00080000U        /*!<ADC3 Injected channel Start flag */
-#define  ADC_CSR_STRT3                       0x00100000U        /*!<ADC3 Regular channel Start flag */
-#define  ADC_CSR_OVR3                        0x00200000U        /*!<ADC3 DMA overrun  flag */
-
-/* Legacy defines */
-#define  ADC_CSR_DOVR1                        ADC_CSR_OVR1
-#define  ADC_CSR_DOVR2                        ADC_CSR_OVR2
-#define  ADC_CSR_DOVR3                        ADC_CSR_OVR3
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
-#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
-#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
-#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
-#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
-
-/*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                      0x0000FFFFU         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                      0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRC calculation unit                              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           0xFFFFFFFFU /*!< Data register bits */
-
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         0xFFU        /*!< General-purpose 8-bit data register bits */
-
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        0x01U        /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 Debug MCU                                  */
-/*                                                                            */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                             DMA Controller                                 */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DMA_SxCR register  *****************/
-#define DMA_SxCR_CHSEL                       0x0E000000U
-#define DMA_SxCR_CHSEL_0                     0x02000000U
-#define DMA_SxCR_CHSEL_1                     0x04000000U
-#define DMA_SxCR_CHSEL_2                     0x08000000U
-#define DMA_SxCR_MBURST                      0x01800000U
-#define DMA_SxCR_MBURST_0                    0x00800000U
-#define DMA_SxCR_MBURST_1                    0x01000000U
-#define DMA_SxCR_PBURST                      0x00600000U
-#define DMA_SxCR_PBURST_0                    0x00200000U
-#define DMA_SxCR_PBURST_1                    0x00400000U
-#define DMA_SxCR_CT                          0x00080000U
-#define DMA_SxCR_DBM                         0x00040000U
-#define DMA_SxCR_PL                          0x00030000U
-#define DMA_SxCR_PL_0                        0x00010000U
-#define DMA_SxCR_PL_1                        0x00020000U
-#define DMA_SxCR_PINCOS                      0x00008000U
-#define DMA_SxCR_MSIZE                       0x00006000U
-#define DMA_SxCR_MSIZE_0                     0x00002000U
-#define DMA_SxCR_MSIZE_1                     0x00004000U
-#define DMA_SxCR_PSIZE                       0x00001800U
-#define DMA_SxCR_PSIZE_0                     0x00000800U
-#define DMA_SxCR_PSIZE_1                     0x00001000U
-#define DMA_SxCR_MINC                        0x00000400U
-#define DMA_SxCR_PINC                        0x00000200U
-#define DMA_SxCR_CIRC                        0x00000100U
-#define DMA_SxCR_DIR                         0x000000C0U
-#define DMA_SxCR_DIR_0                       0x00000040U
-#define DMA_SxCR_DIR_1                       0x00000080U
-#define DMA_SxCR_PFCTRL                      0x00000020U
-#define DMA_SxCR_TCIE                        0x00000010U
-#define DMA_SxCR_HTIE                        0x00000008U
-#define DMA_SxCR_TEIE                        0x00000004U
-#define DMA_SxCR_DMEIE                       0x00000002U
-#define DMA_SxCR_EN                          0x00000001U
-
-/* Legacy defines */
-#define DMA_SxCR_ACK                         0x00100000U
-
-/********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            0x0000FFFFU
-#define DMA_SxNDT_0                          0x00000001U
-#define DMA_SxNDT_1                          0x00000002U
-#define DMA_SxNDT_2                          0x00000004U
-#define DMA_SxNDT_3                          0x00000008U
-#define DMA_SxNDT_4                          0x00000010U
-#define DMA_SxNDT_5                          0x00000020U
-#define DMA_SxNDT_6                          0x00000040U
-#define DMA_SxNDT_7                          0x00000080U
-#define DMA_SxNDT_8                          0x00000100U
-#define DMA_SxNDT_9                          0x00000200U
-#define DMA_SxNDT_10                         0x00000400U
-#define DMA_SxNDT_11                         0x00000800U
-#define DMA_SxNDT_12                         0x00001000U
-#define DMA_SxNDT_13                         0x00002000U
-#define DMA_SxNDT_14                         0x00004000U
-#define DMA_SxNDT_15                         0x00008000U
-
-/********************  Bits definition for DMA_SxFCR register  ****************/ 
-#define DMA_SxFCR_FEIE                       0x00000080U
-#define DMA_SxFCR_FS                         0x00000038U
-#define DMA_SxFCR_FS_0                       0x00000008U
-#define DMA_SxFCR_FS_1                       0x00000010U
-#define DMA_SxFCR_FS_2                       0x00000020U
-#define DMA_SxFCR_DMDIS                      0x00000004U
-#define DMA_SxFCR_FTH                        0x00000003U
-#define DMA_SxFCR_FTH_0                      0x00000001U
-#define DMA_SxFCR_FTH_1                      0x00000002U
-
-/********************  Bits definition for DMA_LISR register  *****************/ 
-#define DMA_LISR_TCIF3                       0x08000000U
-#define DMA_LISR_HTIF3                       0x04000000U
-#define DMA_LISR_TEIF3                       0x02000000U
-#define DMA_LISR_DMEIF3                      0x01000000U
-#define DMA_LISR_FEIF3                       0x00400000U
-#define DMA_LISR_TCIF2                       0x00200000U
-#define DMA_LISR_HTIF2                       0x00100000U
-#define DMA_LISR_TEIF2                       0x00080000U
-#define DMA_LISR_DMEIF2                      0x00040000U
-#define DMA_LISR_FEIF2                       0x00010000U
-#define DMA_LISR_TCIF1                       0x00000800U
-#define DMA_LISR_HTIF1                       0x00000400U
-#define DMA_LISR_TEIF1                       0x00000200U
-#define DMA_LISR_DMEIF1                      0x00000100U
-#define DMA_LISR_FEIF1                       0x00000040U
-#define DMA_LISR_TCIF0                       0x00000020U
-#define DMA_LISR_HTIF0                       0x00000010U
-#define DMA_LISR_TEIF0                       0x00000008U
-#define DMA_LISR_DMEIF0                      0x00000004U
-#define DMA_LISR_FEIF0                       0x00000001U
-
-/********************  Bits definition for DMA_HISR register  *****************/ 
-#define DMA_HISR_TCIF7                       0x08000000U
-#define DMA_HISR_HTIF7                       0x04000000U
-#define DMA_HISR_TEIF7                       0x02000000U
-#define DMA_HISR_DMEIF7                      0x01000000U
-#define DMA_HISR_FEIF7                       0x00400000U
-#define DMA_HISR_TCIF6                       0x00200000U
-#define DMA_HISR_HTIF6                       0x00100000U
-#define DMA_HISR_TEIF6                       0x00080000U
-#define DMA_HISR_DMEIF6                      0x00040000U
-#define DMA_HISR_FEIF6                       0x00010000U
-#define DMA_HISR_TCIF5                       0x00000800U
-#define DMA_HISR_HTIF5                       0x00000400U
-#define DMA_HISR_TEIF5                       0x00000200U
-#define DMA_HISR_DMEIF5                      0x00000100U
-#define DMA_HISR_FEIF5                       0x00000040U
-#define DMA_HISR_TCIF4                       0x00000020U
-#define DMA_HISR_HTIF4                       0x00000010U
-#define DMA_HISR_TEIF4                       0x00000008U
-#define DMA_HISR_DMEIF4                      0x00000004U
-#define DMA_HISR_FEIF4                       0x00000001U
-
-/********************  Bits definition for DMA_LIFCR register  ****************/ 
-#define DMA_LIFCR_CTCIF3                     0x08000000U
-#define DMA_LIFCR_CHTIF3                     0x04000000U
-#define DMA_LIFCR_CTEIF3                     0x02000000U
-#define DMA_LIFCR_CDMEIF3                    0x01000000U
-#define DMA_LIFCR_CFEIF3                     0x00400000U
-#define DMA_LIFCR_CTCIF2                     0x00200000U
-#define DMA_LIFCR_CHTIF2                     0x00100000U
-#define DMA_LIFCR_CTEIF2                     0x00080000U
-#define DMA_LIFCR_CDMEIF2                    0x00040000U
-#define DMA_LIFCR_CFEIF2                     0x00010000U
-#define DMA_LIFCR_CTCIF1                     0x00000800U
-#define DMA_LIFCR_CHTIF1                     0x00000400U
-#define DMA_LIFCR_CTEIF1                     0x00000200U
-#define DMA_LIFCR_CDMEIF1                    0x00000100U
-#define DMA_LIFCR_CFEIF1                     0x00000040U
-#define DMA_LIFCR_CTCIF0                     0x00000020U
-#define DMA_LIFCR_CHTIF0                     0x00000010U
-#define DMA_LIFCR_CTEIF0                     0x00000008U
-#define DMA_LIFCR_CDMEIF0                    0x00000004U
-#define DMA_LIFCR_CFEIF0                     0x00000001U
-
-/********************  Bits definition for DMA_HIFCR  register  ****************/ 
-#define DMA_HIFCR_CTCIF7                     0x08000000U
-#define DMA_HIFCR_CHTIF7                     0x04000000U
-#define DMA_HIFCR_CTEIF7                     0x02000000U
-#define DMA_HIFCR_CDMEIF7                    0x01000000U
-#define DMA_HIFCR_CFEIF7                     0x00400000U
-#define DMA_HIFCR_CTCIF6                     0x00200000U
-#define DMA_HIFCR_CHTIF6                     0x00100000U
-#define DMA_HIFCR_CTEIF6                     0x00080000U
-#define DMA_HIFCR_CDMEIF6                    0x00040000U
-#define DMA_HIFCR_CFEIF6                     0x00010000U
-#define DMA_HIFCR_CTCIF5                     0x00000800U
-#define DMA_HIFCR_CHTIF5                     0x00000400U
-#define DMA_HIFCR_CTEIF5                     0x00000200U
-#define DMA_HIFCR_CDMEIF5                    0x00000100U
-#define DMA_HIFCR_CFEIF5                     0x00000040U
-#define DMA_HIFCR_CTCIF4                     0x00000020U
-#define DMA_HIFCR_CHTIF4                     0x00000010U
-#define DMA_HIFCR_CTEIF4                     0x00000008U
-#define DMA_HIFCR_CDMEIF4                    0x00000004U
-#define DMA_HIFCR_CFEIF4                     0x00000001U
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                    External Interrupt/Event Controller                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    FLASH                                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    0x0000000FU
-#define FLASH_ACR_LATENCY_0WS                0x00000000U
-#define FLASH_ACR_LATENCY_1WS                0x00000001U
-#define FLASH_ACR_LATENCY_2WS                0x00000002U
-#define FLASH_ACR_LATENCY_3WS                0x00000003U
-#define FLASH_ACR_LATENCY_4WS                0x00000004U
-#define FLASH_ACR_LATENCY_5WS                0x00000005U
-#define FLASH_ACR_LATENCY_6WS                0x00000006U
-#define FLASH_ACR_LATENCY_7WS                0x00000007U
-
-#define FLASH_ACR_PRFTEN                     0x00000100U
-#define FLASH_ACR_ICEN                       0x00000200U
-#define FLASH_ACR_DCEN                       0x00000400U
-#define FLASH_ACR_ICRST                      0x00000800U
-#define FLASH_ACR_DCRST                      0x00001000U
-#define FLASH_ACR_BYTE0_ADDRESS              0x40023C00U
-#define FLASH_ACR_BYTE2_ADDRESS              0x40023C03U
-
-/*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         0x00000001U
-#define FLASH_SR_SOP                         0x00000002U
-#define FLASH_SR_WRPERR                      0x00000010U
-#define FLASH_SR_PGAERR                      0x00000020U
-#define FLASH_SR_PGPERR                      0x00000040U
-#define FLASH_SR_PGSERR                      0x00000080U
-#define FLASH_SR_BSY                         0x00010000U
-
-/*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          0x00000001U
-#define FLASH_CR_SER                         0x00000002U
-#define FLASH_CR_MER                         0x00000004U
-#define FLASH_CR_SNB                         0x000000F8U
-#define FLASH_CR_SNB_0                       0x00000008U
-#define FLASH_CR_SNB_1                       0x00000010U
-#define FLASH_CR_SNB_2                       0x00000020U
-#define FLASH_CR_SNB_3                       0x00000040U
-#define FLASH_CR_SNB_4                       0x00000080U
-#define FLASH_CR_PSIZE                       0x00000300U
-#define FLASH_CR_PSIZE_0                     0x00000100U
-#define FLASH_CR_PSIZE_1                     0x00000200U
-#define FLASH_CR_STRT                        0x00010000U
-#define FLASH_CR_EOPIE                       0x01000000U
-#define FLASH_CR_LOCK                        0x80000000U
-
-/*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                 0x00000001U
-#define FLASH_OPTCR_OPTSTRT                 0x00000002U
-#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
-#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
-#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
-
-#define FLASH_OPTCR_WDG_SW                  0x00000020U
-#define FLASH_OPTCR_nRST_STOP               0x00000040U
-#define FLASH_OPTCR_nRST_STDBY              0x00000080U
-#define FLASH_OPTCR_RDP                     0x0000FF00U
-#define FLASH_OPTCR_RDP_0                   0x00000100U
-#define FLASH_OPTCR_RDP_1                   0x00000200U
-#define FLASH_OPTCR_RDP_2                   0x00000400U
-#define FLASH_OPTCR_RDP_3                   0x00000800U
-#define FLASH_OPTCR_RDP_4                   0x00001000U
-#define FLASH_OPTCR_RDP_5                   0x00002000U
-#define FLASH_OPTCR_RDP_6                   0x00004000U
-#define FLASH_OPTCR_RDP_7                   0x00008000U
-#define FLASH_OPTCR_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR_nWRP_0                  0x00010000U
-#define FLASH_OPTCR_nWRP_1                  0x00020000U
-#define FLASH_OPTCR_nWRP_2                  0x00040000U
-#define FLASH_OPTCR_nWRP_3                  0x00080000U
-#define FLASH_OPTCR_nWRP_4                  0x00100000U
-#define FLASH_OPTCR_nWRP_5                  0x00200000U
-#define FLASH_OPTCR_nWRP_6                  0x00400000U
-#define FLASH_OPTCR_nWRP_7                  0x00800000U
-#define FLASH_OPTCR_nWRP_8                  0x01000000U
-#define FLASH_OPTCR_nWRP_9                  0x02000000U
-#define FLASH_OPTCR_nWRP_10                 0x04000000U
-#define FLASH_OPTCR_nWRP_11                 0x08000000U
-                                             
-/******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR1_nWRP_0                  0x00010000U
-#define FLASH_OPTCR1_nWRP_1                  0x00020000U
-#define FLASH_OPTCR1_nWRP_2                  0x00040000U
-#define FLASH_OPTCR1_nWRP_3                  0x00080000U
-#define FLASH_OPTCR1_nWRP_4                  0x00100000U
-#define FLASH_OPTCR1_nWRP_5                  0x00200000U
-#define FLASH_OPTCR1_nWRP_6                  0x00400000U
-#define FLASH_OPTCR1_nWRP_7                  0x00800000U
-#define FLASH_OPTCR1_nWRP_8                  0x01000000U
-#define FLASH_OPTCR1_nWRP_9                  0x02000000U
-#define FLASH_OPTCR1_nWRP_10                 0x04000000U
-#define FLASH_OPTCR1_nWRP_11                 0x08000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    0x00000003U
-#define GPIO_MODER_MODER0_0                  0x00000001U
-#define GPIO_MODER_MODER0_1                  0x00000002U
-
-#define GPIO_MODER_MODER1                    0x0000000CU
-#define GPIO_MODER_MODER1_0                  0x00000004U
-#define GPIO_MODER_MODER1_1                  0x00000008U
-
-#define GPIO_MODER_MODER2                    0x00000030U
-#define GPIO_MODER_MODER2_0                  0x00000010U
-#define GPIO_MODER_MODER2_1                  0x00000020U
-
-#define GPIO_MODER_MODER3                    0x000000C0U
-#define GPIO_MODER_MODER3_0                  0x00000040U
-#define GPIO_MODER_MODER3_1                  0x00000080U
-
-#define GPIO_MODER_MODER4                    0x00000300U
-#define GPIO_MODER_MODER4_0                  0x00000100U
-#define GPIO_MODER_MODER4_1                  0x00000200U
-
-#define GPIO_MODER_MODER5                    0x00000C00U
-#define GPIO_MODER_MODER5_0                  0x00000400U
-#define GPIO_MODER_MODER5_1                  0x00000800U
-
-#define GPIO_MODER_MODER6                    0x00003000U
-#define GPIO_MODER_MODER6_0                  0x00001000U
-#define GPIO_MODER_MODER6_1                  0x00002000U
-
-#define GPIO_MODER_MODER7                    0x0000C000U
-#define GPIO_MODER_MODER7_0                  0x00004000U
-#define GPIO_MODER_MODER7_1                  0x00008000U
-
-#define GPIO_MODER_MODER8                    0x00030000U
-#define GPIO_MODER_MODER8_0                  0x00010000U
-#define GPIO_MODER_MODER8_1                  0x00020000U
-
-#define GPIO_MODER_MODER9                    0x000C0000U
-#define GPIO_MODER_MODER9_0                  0x00040000U
-#define GPIO_MODER_MODER9_1                  0x00080000U
-
-#define GPIO_MODER_MODER10                   0x00300000U
-#define GPIO_MODER_MODER10_0                 0x00100000U
-#define GPIO_MODER_MODER10_1                 0x00200000U
-
-#define GPIO_MODER_MODER11                   0x00C00000U
-#define GPIO_MODER_MODER11_0                 0x00400000U
-#define GPIO_MODER_MODER11_1                 0x00800000U
-
-#define GPIO_MODER_MODER12                   0x03000000U
-#define GPIO_MODER_MODER12_0                 0x01000000U
-#define GPIO_MODER_MODER12_1                 0x02000000U
-
-#define GPIO_MODER_MODER13                   0x0C000000U
-#define GPIO_MODER_MODER13_0                 0x04000000U
-#define GPIO_MODER_MODER13_1                 0x08000000U
-
-#define GPIO_MODER_MODER14                   0x30000000U
-#define GPIO_MODER_MODER14_0                 0x10000000U
-#define GPIO_MODER_MODER14_1                 0x20000000U
-
-#define GPIO_MODER_MODER15                   0xC0000000U
-#define GPIO_MODER_MODER15_0                 0x40000000U
-#define GPIO_MODER_MODER15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     0x00000001U
-#define GPIO_OTYPER_OT_1                     0x00000002U
-#define GPIO_OTYPER_OT_2                     0x00000004U
-#define GPIO_OTYPER_OT_3                     0x00000008U
-#define GPIO_OTYPER_OT_4                     0x00000010U
-#define GPIO_OTYPER_OT_5                     0x00000020U
-#define GPIO_OTYPER_OT_6                     0x00000040U
-#define GPIO_OTYPER_OT_7                     0x00000080U
-#define GPIO_OTYPER_OT_8                     0x00000100U
-#define GPIO_OTYPER_OT_9                     0x00000200U
-#define GPIO_OTYPER_OT_10                    0x00000400U
-#define GPIO_OTYPER_OT_11                    0x00000800U
-#define GPIO_OTYPER_OT_12                    0x00001000U
-#define GPIO_OTYPER_OT_13                    0x00002000U
-#define GPIO_OTYPER_OT_14                    0x00004000U
-#define GPIO_OTYPER_OT_15                    0x00008000U
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
-#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
-#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
-
-#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
-#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
-#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
-
-#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
-#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
-#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
-
-#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
-#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
-#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
-
-#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
-#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
-#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
-
-#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
-#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
-#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
-
-#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
-#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
-#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
-
-#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
-#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
-#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
-
-#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
-#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
-#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
-
-#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
-#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
-#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
-
-#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
-#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
-#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
-
-#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
-#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
-#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
-
-#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
-#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
-#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
-
-#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
-#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
-#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
-
-#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
-#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
-#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
-
-#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
-#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
-#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    0x00000003U
-#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
-#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
-
-#define GPIO_PUPDR_PUPDR1                    0x0000000CU
-#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
-#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
-
-#define GPIO_PUPDR_PUPDR2                    0x00000030U
-#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
-#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
-
-#define GPIO_PUPDR_PUPDR3                    0x000000C0U
-#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
-#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
-
-#define GPIO_PUPDR_PUPDR4                    0x00000300U
-#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
-#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
-
-#define GPIO_PUPDR_PUPDR5                    0x00000C00U
-#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
-#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
-
-#define GPIO_PUPDR_PUPDR6                    0x00003000U
-#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
-#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
-
-#define GPIO_PUPDR_PUPDR7                    0x0000C000U
-#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
-#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
-
-#define GPIO_PUPDR_PUPDR8                    0x00030000U
-#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
-#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
-
-#define GPIO_PUPDR_PUPDR9                    0x000C0000U
-#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
-#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
-
-#define GPIO_PUPDR_PUPDR10                   0x00300000U
-#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
-#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
-
-#define GPIO_PUPDR_PUPDR11                   0x00C00000U
-#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
-#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
-
-#define GPIO_PUPDR_PUPDR12                   0x03000000U
-#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
-#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
-
-#define GPIO_PUPDR_PUPDR13                   0x0C000000U
-#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
-#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
-
-#define GPIO_PUPDR_PUPDR14                   0x30000000U
-#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
-#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
-
-#define GPIO_PUPDR_PUPDR15                   0xC0000000U
-#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
-#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       0x00000001U
-#define GPIO_IDR_IDR_1                       0x00000002U
-#define GPIO_IDR_IDR_2                       0x00000004U
-#define GPIO_IDR_IDR_3                       0x00000008U
-#define GPIO_IDR_IDR_4                       0x00000010U
-#define GPIO_IDR_IDR_5                       0x00000020U
-#define GPIO_IDR_IDR_6                       0x00000040U
-#define GPIO_IDR_IDR_7                       0x00000080U
-#define GPIO_IDR_IDR_8                       0x00000100U
-#define GPIO_IDR_IDR_9                       0x00000200U
-#define GPIO_IDR_IDR_10                      0x00000400U
-#define GPIO_IDR_IDR_11                      0x00000800U
-#define GPIO_IDR_IDR_12                      0x00001000U
-#define GPIO_IDR_IDR_13                      0x00002000U
-#define GPIO_IDR_IDR_14                      0x00004000U
-#define GPIO_IDR_IDR_15                      0x00008000U
-/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
-#define GPIO_OTYPER_IDR_0                    GPIO_IDR_IDR_0
-#define GPIO_OTYPER_IDR_1                    GPIO_IDR_IDR_1
-#define GPIO_OTYPER_IDR_2                    GPIO_IDR_IDR_2
-#define GPIO_OTYPER_IDR_3                    GPIO_IDR_IDR_3
-#define GPIO_OTYPER_IDR_4                    GPIO_IDR_IDR_4
-#define GPIO_OTYPER_IDR_5                    GPIO_IDR_IDR_5
-#define GPIO_OTYPER_IDR_6                    GPIO_IDR_IDR_6
-#define GPIO_OTYPER_IDR_7                    GPIO_IDR_IDR_7
-#define GPIO_OTYPER_IDR_8                    GPIO_IDR_IDR_8
-#define GPIO_OTYPER_IDR_9                    GPIO_IDR_IDR_9
-#define GPIO_OTYPER_IDR_10                   GPIO_IDR_IDR_10
-#define GPIO_OTYPER_IDR_11                   GPIO_IDR_IDR_11
-#define GPIO_OTYPER_IDR_12                   GPIO_IDR_IDR_12
-#define GPIO_OTYPER_IDR_13                   GPIO_IDR_IDR_13
-#define GPIO_OTYPER_IDR_14                   GPIO_IDR_IDR_14
-#define GPIO_OTYPER_IDR_15                   GPIO_IDR_IDR_15
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       0x00000001U
-#define GPIO_ODR_ODR_1                       0x00000002U
-#define GPIO_ODR_ODR_2                       0x00000004U
-#define GPIO_ODR_ODR_3                       0x00000008U
-#define GPIO_ODR_ODR_4                       0x00000010U
-#define GPIO_ODR_ODR_5                       0x00000020U
-#define GPIO_ODR_ODR_6                       0x00000040U
-#define GPIO_ODR_ODR_7                       0x00000080U
-#define GPIO_ODR_ODR_8                       0x00000100U
-#define GPIO_ODR_ODR_9                       0x00000200U
-#define GPIO_ODR_ODR_10                      0x00000400U
-#define GPIO_ODR_ODR_11                      0x00000800U
-#define GPIO_ODR_ODR_12                      0x00001000U
-#define GPIO_ODR_ODR_13                      0x00002000U
-#define GPIO_ODR_ODR_14                      0x00004000U
-#define GPIO_ODR_ODR_15                      0x00008000U
-/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
-#define GPIO_OTYPER_ODR_0                    GPIO_ODR_ODR_0
-#define GPIO_OTYPER_ODR_1                    GPIO_ODR_ODR_1
-#define GPIO_OTYPER_ODR_2                    GPIO_ODR_ODR_2
-#define GPIO_OTYPER_ODR_3                    GPIO_ODR_ODR_3
-#define GPIO_OTYPER_ODR_4                    GPIO_ODR_ODR_4
-#define GPIO_OTYPER_ODR_5                    GPIO_ODR_ODR_5
-#define GPIO_OTYPER_ODR_6                    GPIO_ODR_ODR_6
-#define GPIO_OTYPER_ODR_7                    GPIO_ODR_ODR_7
-#define GPIO_OTYPER_ODR_8                    GPIO_ODR_ODR_8
-#define GPIO_OTYPER_ODR_9                    GPIO_ODR_ODR_9
-#define GPIO_OTYPER_ODR_10                   GPIO_ODR_ODR_10
-#define GPIO_OTYPER_ODR_11                   GPIO_ODR_ODR_11
-#define GPIO_OTYPER_ODR_12                   GPIO_ODR_ODR_12
-#define GPIO_OTYPER_ODR_13                   GPIO_ODR_ODR_13
-#define GPIO_OTYPER_ODR_14                   GPIO_ODR_ODR_14
-#define GPIO_OTYPER_ODR_15                   GPIO_ODR_ODR_15
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       0x00000001U
-#define GPIO_BSRR_BS_1                       0x00000002U
-#define GPIO_BSRR_BS_2                       0x00000004U
-#define GPIO_BSRR_BS_3                       0x00000008U
-#define GPIO_BSRR_BS_4                       0x00000010U
-#define GPIO_BSRR_BS_5                       0x00000020U
-#define GPIO_BSRR_BS_6                       0x00000040U
-#define GPIO_BSRR_BS_7                       0x00000080U
-#define GPIO_BSRR_BS_8                       0x00000100U
-#define GPIO_BSRR_BS_9                       0x00000200U
-#define GPIO_BSRR_BS_10                      0x00000400U
-#define GPIO_BSRR_BS_11                      0x00000800U
-#define GPIO_BSRR_BS_12                      0x00001000U
-#define GPIO_BSRR_BS_13                      0x00002000U
-#define GPIO_BSRR_BS_14                      0x00004000U
-#define GPIO_BSRR_BS_15                      0x00008000U
-#define GPIO_BSRR_BR_0                       0x00010000U
-#define GPIO_BSRR_BR_1                       0x00020000U
-#define GPIO_BSRR_BR_2                       0x00040000U
-#define GPIO_BSRR_BR_3                       0x00080000U
-#define GPIO_BSRR_BR_4                       0x00100000U
-#define GPIO_BSRR_BR_5                       0x00200000U
-#define GPIO_BSRR_BR_6                       0x00400000U
-#define GPIO_BSRR_BR_7                       0x00800000U
-#define GPIO_BSRR_BR_8                       0x01000000U
-#define GPIO_BSRR_BR_9                       0x02000000U
-#define GPIO_BSRR_BR_10                      0x04000000U
-#define GPIO_BSRR_BR_11                      0x08000000U
-#define GPIO_BSRR_BR_12                      0x10000000U
-#define GPIO_BSRR_BR_13                      0x20000000U
-#define GPIO_BSRR_BR_14                      0x40000000U
-#define GPIO_BSRR_BR_15                      0x80000000U
-
-/****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0                       0x00000001U
-#define GPIO_LCKR_LCK1                       0x00000002U
-#define GPIO_LCKR_LCK2                       0x00000004U
-#define GPIO_LCKR_LCK3                       0x00000008U
-#define GPIO_LCKR_LCK4                       0x00000010U
-#define GPIO_LCKR_LCK5                       0x00000020U
-#define GPIO_LCKR_LCK6                       0x00000040U
-#define GPIO_LCKR_LCK7                       0x00000080U
-#define GPIO_LCKR_LCK8                       0x00000100U
-#define GPIO_LCKR_LCK9                       0x00000200U
-#define GPIO_LCKR_LCK10                      0x00000400U
-#define GPIO_LCKR_LCK11                      0x00000800U
-#define GPIO_LCKR_LCK12                      0x00001000U
-#define GPIO_LCKR_LCK13                      0x00002000U
-#define GPIO_LCKR_LCK14                      0x00004000U
-#define GPIO_LCKR_LCK15                      0x00008000U
-#define GPIO_LCKR_LCKK                       0x00010000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Inter-integrated Circuit Interface                    */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          0x00000001U     /*!<Peripheral Enable                             */
-#define  I2C_CR1_SMBUS                       0x00000002U     /*!<SMBus Mode                                    */
-#define  I2C_CR1_SMBTYPE                     0x00000008U     /*!<SMBus Type                                    */
-#define  I2C_CR1_ENARP                       0x00000010U     /*!<ARP Enable                                    */
-#define  I2C_CR1_ENPEC                       0x00000020U     /*!<PEC Enable                                    */
-#define  I2C_CR1_ENGC                        0x00000040U     /*!<General Call Enable                           */
-#define  I2C_CR1_NOSTRETCH                   0x00000080U     /*!<Clock Stretching Disable (Slave mode)  */
-#define  I2C_CR1_START                       0x00000100U     /*!<Start Generation                              */
-#define  I2C_CR1_STOP                        0x00000200U     /*!<Stop Generation                               */
-#define  I2C_CR1_ACK                         0x00000400U     /*!<Acknowledge Enable                            */
-#define  I2C_CR1_POS                         0x00000800U     /*!<Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         0x00001000U     /*!<Packet Error Checking                         */
-#define  I2C_CR1_ALERT                       0x00002000U     /*!<SMBus Alert                                   */
-#define  I2C_CR1_SWRST                       0x00008000U     /*!<Software Reset                                */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        0x0000003FU     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
-#define  I2C_CR2_FREQ_0                      0x00000001U     /*!<Bit 0 */
-#define  I2C_CR2_FREQ_1                      0x00000002U     /*!<Bit 1 */
-#define  I2C_CR2_FREQ_2                      0x00000004U     /*!<Bit 2 */
-#define  I2C_CR2_FREQ_3                      0x00000008U     /*!<Bit 3 */
-#define  I2C_CR2_FREQ_4                      0x00000010U     /*!<Bit 4 */
-#define  I2C_CR2_FREQ_5                      0x00000020U     /*!<Bit 5 */
-
-#define  I2C_CR2_ITERREN                     0x00000100U     /*!<Error Interrupt Enable  */
-#define  I2C_CR2_ITEVTEN                     0x00000200U     /*!<Event Interrupt Enable  */
-#define  I2C_CR2_ITBUFEN                     0x00000400U     /*!<Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       0x00000800U     /*!<DMA Requests Enable     */
-#define  I2C_CR2_LAST                        0x00001000U     /*!<DMA Last Transfer       */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     0x000000FEU     /*!<Interface Address */
-#define  I2C_OAR1_ADD8_9                     0x00000300U     /*!<Interface Address */
-
-#define  I2C_OAR1_ADD0                       0x00000001U     /*!<Bit 0 */
-#define  I2C_OAR1_ADD1                       0x00000002U     /*!<Bit 1 */
-#define  I2C_OAR1_ADD2                       0x00000004U     /*!<Bit 2 */
-#define  I2C_OAR1_ADD3                       0x00000008U     /*!<Bit 3 */
-#define  I2C_OAR1_ADD4                       0x00000010U     /*!<Bit 4 */
-#define  I2C_OAR1_ADD5                       0x00000020U     /*!<Bit 5 */
-#define  I2C_OAR1_ADD6                       0x00000040U     /*!<Bit 6 */
-#define  I2C_OAR1_ADD7                       0x00000080U     /*!<Bit 7 */
-#define  I2C_OAR1_ADD8                       0x00000100U     /*!<Bit 8 */
-#define  I2C_OAR1_ADD9                       0x00000200U     /*!<Bit 9 */
-
-#define  I2C_OAR1_ADDMODE                    0x00008000U     /*!<Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     0x00000001U        /*!<Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       0x000000FEU        /*!<Interface address           */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           0x000000FFU        /*!<8-bit Data Register         */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          0x00000001U     /*!<Start Bit (Master mode)                  */
-#define  I2C_SR1_ADDR                        0x00000002U     /*!<Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         0x00000004U     /*!<Byte Transfer Finished                          */
-#define  I2C_SR1_ADD10                       0x00000008U     /*!<10-bit header sent (Master mode)         */
-#define  I2C_SR1_STOPF                       0x00000010U     /*!<Stop detection (Slave mode)              */
-#define  I2C_SR1_RXNE                        0x00000040U     /*!<Data Register not Empty (receivers)      */
-#define  I2C_SR1_TXE                         0x00000080U     /*!<Data Register Empty (transmitters)       */
-#define  I2C_SR1_BERR                        0x00000100U     /*!<Bus Error                                       */
-#define  I2C_SR1_ARLO                        0x00000200U     /*!<Arbitration Lost (master mode)           */
-#define  I2C_SR1_AF                          0x00000400U     /*!<Acknowledge Failure                             */
-#define  I2C_SR1_OVR                         0x00000800U     /*!<Overrun/Underrun                                */
-#define  I2C_SR1_PECERR                      0x00001000U     /*!<PEC Error in reception                          */
-#define  I2C_SR1_TIMEOUT                     0x00004000U     /*!<Timeout or Tlow Error                           */
-#define  I2C_SR1_SMBALERT                    0x00008000U     /*!<SMBus Alert                                     */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         0x00000001U     /*!<Master/Slave                              */
-#define  I2C_SR2_BUSY                        0x00000002U     /*!<Bus Busy                                  */
-#define  I2C_SR2_TRA                         0x00000004U     /*!<Transmitter/Receiver                      */
-#define  I2C_SR2_GENCALL                     0x00000010U     /*!<General Call Address (Slave mode)  */
-#define  I2C_SR2_SMBDEFAULT                  0x00000020U     /*!<SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     0x00000040U     /*!<SMBus Host Header (Slave mode)     */
-#define  I2C_SR2_DUALF                       0x00000080U     /*!<Dual Flag (Slave mode)             */
-#define  I2C_SR2_PEC                         0x0000FF00U     /*!<Packet Error Checking Register            */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         0x00000FFFU     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        0x00004000U     /*!<Fast Mode Duty Cycle                                       */
-#define  I2C_CCR_FS                          0x00008000U     /*!<I2C Master Mode Selection                                  */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     0x0000003FU     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************  Bit definition for I2C_FLTR register  *******************/
-#define  I2C_FLTR_DNF                        0x0000000FU     /*!<Digital Noise Filter */
-#define  I2C_FLTR_ANOFF                      0x00000010U     /*!<Analog Noise Filter OFF */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Independent WATCHDOG                             */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         0x01U               /*!<Watchdog prescaler value update      */
-#define  IWDG_SR_RVU                         0x02U               /*!<Watchdog counter reload value update */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                             Power Control                                  */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
-#define  PWR_CR_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
-#define  PWR_CR_CWUF                         0x00000004U     /*!< Clear Wakeup Flag                   */
-#define  PWR_CR_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
-#define  PWR_CR_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
-
-#define  PWR_CR_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        0x00000020U     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        0x00000040U     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        0x00000080U     /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
-
-#define  PWR_CR_DBP                          0x00000100U     /*!< Disable Backup Domain write protection                     */
-#define  PWR_CR_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                              */
-#define  PWR_CR_LPLVDS                       0x00000400U     /*!< Low Power Regulator Low Voltage in Deep Sleep mode         */
-#define  PWR_CR_MRLVDS                       0x00000800U     /*!< Main Regulator Low Voltage in Deep Sleep mode              */
-#define  PWR_CR_ADCDC1                       0x00002000U     /*!< Refer to AN4073 on how to use this bit                     */
-#define  PWR_CR_VOS                          0x0000C000U     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
-#define  PWR_CR_VOS_0                        0x00004000U     /*!< Bit 0 */
-#define  PWR_CR_VOS_1                        0x00008000U     /*!< Bit 1 */
-
-/* Legacy define */
-#define  PWR_CR_PMODE                        PWR_CR_VOS
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         0x00000001U     /*!< Wakeup Flag                                      */
-#define  PWR_CSR_SBF                         0x00000002U     /*!< Standby Flag                                     */
-#define  PWR_CSR_PVDO                        0x00000004U     /*!< PVD Output                                       */
-#define  PWR_CSR_BRR                         0x00000008U     /*!< Backup regulator ready                           */
-#define  PWR_CSR_EWUP                        0x00000100U     /*!< Enable WKUP pin                                  */
-#define  PWR_CSR_BRE                         0x00000200U     /*!< Backup regulator enable                          */
-#define  PWR_CSR_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
-
-/* Legacy define */
-#define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        0x00000001U
-#define  RCC_CR_HSIRDY                       0x00000002U
-
-#define  RCC_CR_HSITRIM                      0x000000F8U
-#define  RCC_CR_HSITRIM_0                    0x00000008U/*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    0x00000010U/*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    0x00000020U/*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    0x00000040U/*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    0x00000080U/*!<Bit 4 */
-
-#define  RCC_CR_HSICAL                       0x0000FF00U
-#define  RCC_CR_HSICAL_0                     0x00000100U/*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     0x00000200U/*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     0x00000400U/*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     0x00000800U/*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     0x00001000U/*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     0x00002000U/*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     0x00004000U/*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     0x00008000U/*!<Bit 7 */
-
-#define  RCC_CR_HSEON                        0x00010000U
-#define  RCC_CR_HSERDY                       0x00020000U
-#define  RCC_CR_HSEBYP                       0x00040000U
-#define  RCC_CR_CSSON                        0x00080000U
-#define  RCC_CR_PLLON                        0x01000000U
-#define  RCC_CR_PLLRDY                       0x02000000U
-#define  RCC_CR_PLLI2SON                     0x04000000U
-#define  RCC_CR_PLLI2SRDY                    0x08000000U
-
-/********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    0x0000003FU
-#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
-#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
-#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
-#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
-#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
-#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
-
-#define  RCC_PLLCFGR_PLLN                     0x00007FC0U
-#define  RCC_PLLCFGR_PLLN_0                   0x00000040U
-#define  RCC_PLLCFGR_PLLN_1                   0x00000080U
-#define  RCC_PLLCFGR_PLLN_2                   0x00000100U
-#define  RCC_PLLCFGR_PLLN_3                   0x00000200U
-#define  RCC_PLLCFGR_PLLN_4                   0x00000400U
-#define  RCC_PLLCFGR_PLLN_5                   0x00000800U
-#define  RCC_PLLCFGR_PLLN_6                   0x00001000U
-#define  RCC_PLLCFGR_PLLN_7                   0x00002000U
-#define  RCC_PLLCFGR_PLLN_8                   0x00004000U
-
-#define  RCC_PLLCFGR_PLLP                    0x00030000U
-#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
-#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
-
-#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
-
-#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
-#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
-#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
-#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
-#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-/*!< SW configuration */
-#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
-
-#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
-
-#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
-
-#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
-
-/*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     0x001F0000U
-#define  RCC_CFGR_RTCPRE_0                   0x00010000U
-#define  RCC_CFGR_RTCPRE_1                   0x00020000U
-#define  RCC_CFGR_RTCPRE_2                   0x00040000U
-#define  RCC_CFGR_RTCPRE_3                   0x00080000U
-#define  RCC_CFGR_RTCPRE_4                   0x00100000U
-
-/*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       0x00600000U
-#define  RCC_CFGR_MCO1_0                     0x00200000U
-#define  RCC_CFGR_MCO1_1                     0x00400000U
-
-#define  RCC_CFGR_I2SSRC                     0x00800000U
-
-#define  RCC_CFGR_MCO1PRE                    0x07000000U
-#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
-#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
-#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
-
-#define  RCC_CFGR_MCO2PRE                    0x38000000U
-#define  RCC_CFGR_MCO2PRE_0                  0x08000000U
-#define  RCC_CFGR_MCO2PRE_1                  0x10000000U
-#define  RCC_CFGR_MCO2PRE_2                  0x20000000U
-
-#define  RCC_CFGR_MCO2                       0xC0000000U
-#define  RCC_CFGR_MCO2_0                     0x40000000U
-#define  RCC_CFGR_MCO2_1                     0x80000000U
-
-/********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     0x00000001U
-#define  RCC_CIR_LSERDYF                     0x00000002U
-#define  RCC_CIR_HSIRDYF                     0x00000004U
-#define  RCC_CIR_HSERDYF                     0x00000008U
-#define  RCC_CIR_PLLRDYF                     0x00000010U
-#define  RCC_CIR_PLLI2SRDYF                  0x00000020U
-
-#define  RCC_CIR_CSSF                        0x00000080U
-#define  RCC_CIR_LSIRDYIE                    0x00000100U
-#define  RCC_CIR_LSERDYIE                    0x00000200U
-#define  RCC_CIR_HSIRDYIE                    0x00000400U
-#define  RCC_CIR_HSERDYIE                    0x00000800U
-#define  RCC_CIR_PLLRDYIE                    0x00001000U
-#define  RCC_CIR_PLLI2SRDYIE                 0x00002000U
-
-#define  RCC_CIR_LSIRDYC                     0x00010000U
-#define  RCC_CIR_LSERDYC                     0x00020000U
-#define  RCC_CIR_HSIRDYC                     0x00040000U
-#define  RCC_CIR_HSERDYC                     0x00080000U
-#define  RCC_CIR_PLLRDYC                     0x00100000U
-#define  RCC_CIR_PLLI2SRDYC                  0x00200000U
-
-#define  RCC_CIR_CSSC                        0x00800000U
-
-/********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
-#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
-#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
-#define  RCC_AHB1RSTR_GPIODRST               0x00000008U
-#define  RCC_AHB1RSTR_GPIOERST               0x00000010U
-#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
-#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
-#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
-#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
-
-/********************  Bit definition for RCC_AHB2RSTR register  **************/
-#define  RCC_AHB2RSTR_OTGFSRST               0x00000080U
-
-/********************  Bit definition for RCC_AHB3RSTR register  **************/
-
-/********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM2RST                0x00000001U
-#define  RCC_APB1RSTR_TIM3RST                0x00000002U
-#define  RCC_APB1RSTR_TIM4RST                0x00000004U
-#define  RCC_APB1RSTR_TIM5RST                0x00000008U
-#define  RCC_APB1RSTR_WWDGRST                0x00000800U
-#define  RCC_APB1RSTR_SPI2RST                0x00004000U
-#define  RCC_APB1RSTR_SPI3RST                0x00008000U
-#define  RCC_APB1RSTR_USART2RST              0x00020000U
-#define  RCC_APB1RSTR_I2C1RST                0x00200000U
-#define  RCC_APB1RSTR_I2C2RST                0x00400000U
-#define  RCC_APB1RSTR_I2C3RST                0x00800000U
-#define  RCC_APB1RSTR_PWRRST                 0x10000000U
-
-/********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                0x00000001U
-#define  RCC_APB2RSTR_USART1RST              0x00000010U
-#define  RCC_APB2RSTR_USART6RST              0x00000020U
-#define  RCC_APB2RSTR_ADCRST                 0x00000100U
-#define  RCC_APB2RSTR_SDIORST                0x00000800U
-#define  RCC_APB2RSTR_SPI1RST                0x00001000U
-#define  RCC_APB2RSTR_SPI4RST                0x00002000U
-#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
-#define  RCC_APB2RSTR_TIM9RST                0x00010000U
-#define  RCC_APB2RSTR_TIM10RST               0x00020000U
-#define  RCC_APB2RSTR_TIM11RST               0x00040000U
-
-/* Old SPI1RST bit definition, maintained for legacy purpose */
-#define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
-
-/********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
-#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
-#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
-#define  RCC_AHB1ENR_GPIODEN                 0x00000008U
-#define  RCC_AHB1ENR_GPIOEEN                 0x00000010U
-#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
-#define  RCC_AHB1ENR_CRCEN                   0x00001000U
-#define  RCC_AHB1ENR_BKPSRAMEN               0x00040000U
-#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
-#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
-
-/********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define  RCC_AHB2ENR_OTGFSEN                 0x00000080U
-
-/********************  Bit definition for RCC_AHB3ENR register  ***************/
-
-/********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM2EN                  0x00000001U
-#define  RCC_APB1ENR_TIM3EN                  0x00000002U
-#define  RCC_APB1ENR_TIM4EN                  0x00000004U
-#define  RCC_APB1ENR_TIM5EN                  0x00000008U
-#define  RCC_APB1ENR_WWDGEN                  0x00000800U
-#define  RCC_APB1ENR_SPI2EN                  0x00004000U
-#define  RCC_APB1ENR_SPI3EN                  0x00008000U
-#define  RCC_APB1ENR_USART2EN                0x00020000U
-#define  RCC_APB1ENR_I2C1EN                  0x00200000U
-#define  RCC_APB1ENR_I2C2EN                  0x00400000U
-#define  RCC_APB1ENR_I2C3EN                  0x00800000U
-#define  RCC_APB1ENR_PWREN                   0x10000000U
-
-/********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  0x00000001U
-#define  RCC_APB2ENR_USART1EN                0x00000010U
-#define  RCC_APB2ENR_USART6EN                0x00000020U
-#define  RCC_APB2ENR_ADC1EN                  0x00000100U
-#define  RCC_APB2ENR_SDIOEN                  0x00000800U
-#define  RCC_APB2ENR_SPI1EN                  0x00001000U
-#define  RCC_APB2ENR_SPI4EN                  0x00002000U
-#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
-#define  RCC_APB2ENR_TIM9EN                  0x00010000U
-#define  RCC_APB2ENR_TIM10EN                 0x00020000U
-#define  RCC_APB2ENR_TIM11EN                 0x00040000U
-
-/********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
-#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
-#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
-#define  RCC_AHB1LPENR_GPIODLPEN             0x00000008U
-#define  RCC_AHB1LPENR_GPIOELPEN             0x00000010U
-#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
-#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
-#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
-#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
-#define  RCC_AHB1LPENR_SRAM2LPEN             0x00020000U
-#define  RCC_AHB1LPENR_BKPSRAMLPEN           0x00040000U
-#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
-#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
-
-/********************  Bit definition for RCC_AHB2LPENR register  *************/
-#define  RCC_AHB2LPENR_OTGFSLPEN             0x00000080U
-
-/********************  Bit definition for RCC_AHB3LPENR register  *************/
-
-/********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM2LPEN              0x00000001U
-#define  RCC_APB1LPENR_TIM3LPEN              0x00000002U
-#define  RCC_APB1LPENR_TIM4LPEN              0x00000004U
-#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
-#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
-#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U
-#define  RCC_APB1LPENR_SPI3LPEN              0x00008000U
-#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
-#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
-#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
-#define  RCC_APB1LPENR_I2C3LPEN              0x00800000U
-#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
-#define  RCC_APB1LPENR_DACLPEN               0x20000000U
-
-/********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
-#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
-#define  RCC_APB2LPENR_USART6LPEN            0x00000020U
-#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
-#define  RCC_APB2LPENR_SDIOLPEN              0x00000800U
-#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
-#define  RCC_APB2LPENR_SPI4LPEN              0x00002000U
-#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
-#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
-#define  RCC_APB2LPENR_TIM10LPEN             0x00020000U
-#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
-
-/********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      0x00000001U
-#define  RCC_BDCR_LSERDY                     0x00000002U
-#define  RCC_BDCR_LSEBYP                     0x00000004U
-
-#define  RCC_BDCR_RTCSEL                    0x00000300U
-#define  RCC_BDCR_RTCSEL_0                  0x00000100U
-#define  RCC_BDCR_RTCSEL_1                  0x00000200U
-
-#define  RCC_BDCR_RTCEN                      0x00008000U
-#define  RCC_BDCR_BDRST                      0x00010000U
-
-/********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       0x00000001U
-#define  RCC_CSR_LSIRDY                      0x00000002U
-#define  RCC_CSR_RMVF                        0x01000000U
-#define  RCC_CSR_BORRSTF                     0x02000000U
-#define  RCC_CSR_PADRSTF                     0x04000000U
-#define  RCC_CSR_PORRSTF                     0x08000000U
-#define  RCC_CSR_SFTRSTF                     0x10000000U
-#define  RCC_CSR_WDGRSTF                     0x20000000U
-#define  RCC_CSR_WWDGRSTF                    0x40000000U
-#define  RCC_CSR_LPWRRSTF                    0x80000000U
-
-/********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    0x00001FFFU
-#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
-#define  RCC_SSCGR_SPREADSEL                 0x40000000U
-#define  RCC_SSCGR_SSCGEN                    0x80000000U
-
-/********************  Bit definition for RCC_PLLI2SCFGR register  ************/
-#define  RCC_PLLI2SCFGR_PLLI2SN              0x00007FC0U
-#define  RCC_PLLI2SCFGR_PLLI2SN_0            0x00000040U
-#define  RCC_PLLI2SCFGR_PLLI2SN_1            0x00000080U
-#define  RCC_PLLI2SCFGR_PLLI2SN_2            0x00000100U
-#define  RCC_PLLI2SCFGR_PLLI2SN_3            0x00000200U
-#define  RCC_PLLI2SCFGR_PLLI2SN_4            0x00000400U
-#define  RCC_PLLI2SCFGR_PLLI2SN_5            0x00000800U
-#define  RCC_PLLI2SCFGR_PLLI2SN_6            0x00001000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_7            0x00002000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_8            0x00004000U
-
-#define  RCC_PLLI2SCFGR_PLLI2SR              0x70000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_0            0x10000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_1            0x20000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_2            0x40000000U
-
-/********************  Bit definition for RCC_DCKCFGR register  ***************/
-#define  RCC_DCKCFGR_TIMPRE                  0x01000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            0x00400000U
-#define RTC_TR_HT                            0x00300000U
-#define RTC_TR_HT_0                          0x00100000U
-#define RTC_TR_HT_1                          0x00200000U
-#define RTC_TR_HU                            0x000F0000U
-#define RTC_TR_HU_0                          0x00010000U
-#define RTC_TR_HU_1                          0x00020000U
-#define RTC_TR_HU_2                          0x00040000U
-#define RTC_TR_HU_3                          0x00080000U
-#define RTC_TR_MNT                           0x00007000U
-#define RTC_TR_MNT_0                         0x00001000U
-#define RTC_TR_MNT_1                         0x00002000U
-#define RTC_TR_MNT_2                         0x00004000U
-#define RTC_TR_MNU                           0x00000F00U
-#define RTC_TR_MNU_0                         0x00000100U
-#define RTC_TR_MNU_1                         0x00000200U
-#define RTC_TR_MNU_2                         0x00000400U
-#define RTC_TR_MNU_3                         0x00000800U
-#define RTC_TR_ST                            0x00000070U
-#define RTC_TR_ST_0                          0x00000010U
-#define RTC_TR_ST_1                          0x00000020U
-#define RTC_TR_ST_2                          0x00000040U
-#define RTC_TR_SU                            0x0000000FU
-#define RTC_TR_SU_0                          0x00000001U
-#define RTC_TR_SU_1                          0x00000002U
-#define RTC_TR_SU_2                          0x00000004U
-#define RTC_TR_SU_3                          0x00000008U
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            0x00F00000U
-#define RTC_DR_YT_0                          0x00100000U
-#define RTC_DR_YT_1                          0x00200000U
-#define RTC_DR_YT_2                          0x00400000U
-#define RTC_DR_YT_3                          0x00800000U
-#define RTC_DR_YU                            0x000F0000U
-#define RTC_DR_YU_0                          0x00010000U
-#define RTC_DR_YU_1                          0x00020000U
-#define RTC_DR_YU_2                          0x00040000U
-#define RTC_DR_YU_3                          0x00080000U
-#define RTC_DR_WDU                           0x0000E000U
-#define RTC_DR_WDU_0                         0x00002000U
-#define RTC_DR_WDU_1                         0x00004000U
-#define RTC_DR_WDU_2                         0x00008000U
-#define RTC_DR_MT                            0x00001000U
-#define RTC_DR_MU                            0x00000F00U
-#define RTC_DR_MU_0                          0x00000100U
-#define RTC_DR_MU_1                          0x00000200U
-#define RTC_DR_MU_2                          0x00000400U
-#define RTC_DR_MU_3                          0x00000800U
-#define RTC_DR_DT                            0x00000030U
-#define RTC_DR_DT_0                          0x00000010U
-#define RTC_DR_DT_1                          0x00000020U
-#define RTC_DR_DU                            0x0000000FU
-#define RTC_DR_DU_0                          0x00000001U
-#define RTC_DR_DU_1                          0x00000002U
-#define RTC_DR_DU_2                          0x00000004U
-#define RTC_DR_DU_3                          0x00000008U
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           0x00800000U
-#define RTC_CR_OSEL                          0x00600000U
-#define RTC_CR_OSEL_0                        0x00200000U
-#define RTC_CR_OSEL_1                        0x00400000U
-#define RTC_CR_POL                           0x00100000U
-#define RTC_CR_COSEL                         0x00080000U
-#define RTC_CR_BCK                           0x00040000U
-#define RTC_CR_SUB1H                         0x00020000U
-#define RTC_CR_ADD1H                         0x00010000U
-#define RTC_CR_TSIE                          0x00008000U
-#define RTC_CR_WUTIE                         0x00004000U
-#define RTC_CR_ALRBIE                        0x00002000U
-#define RTC_CR_ALRAIE                        0x00001000U
-#define RTC_CR_TSE                           0x00000800U
-#define RTC_CR_WUTE                          0x00000400U
-#define RTC_CR_ALRBE                         0x00000200U
-#define RTC_CR_ALRAE                         0x00000100U
-#define RTC_CR_DCE                           0x00000080U
-#define RTC_CR_FMT                           0x00000040U
-#define RTC_CR_BYPSHAD                       0x00000020U
-#define RTC_CR_REFCKON                       0x00000010U
-#define RTC_CR_TSEDGE                        0x00000008U
-#define RTC_CR_WUCKSEL                       0x00000007U
-#define RTC_CR_WUCKSEL_0                     0x00000001U
-#define RTC_CR_WUCKSEL_1                     0x00000002U
-#define RTC_CR_WUCKSEL_2                     0x00000004U
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      0x00010000U
-#define RTC_ISR_TAMP1F                       0x00002000U
-#define RTC_ISR_TAMP2F                       0x00004000U
-#define RTC_ISR_TSOVF                        0x00001000U
-#define RTC_ISR_TSF                          0x00000800U
-#define RTC_ISR_WUTF                         0x00000400U
-#define RTC_ISR_ALRBF                        0x00000200U
-#define RTC_ISR_ALRAF                        0x00000100U
-#define RTC_ISR_INIT                         0x00000080U
-#define RTC_ISR_INITF                        0x00000040U
-#define RTC_ISR_RSF                          0x00000020U
-#define RTC_ISR_INITS                        0x00000010U
-#define RTC_ISR_SHPF                         0x00000008U
-#define RTC_ISR_WUTWF                        0x00000004U
-#define RTC_ISR_ALRBWF                       0x00000002U
-#define RTC_ISR_ALRAWF                       0x00000001U
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    0x007F0000U
-#define RTC_PRER_PREDIV_S                    0x00007FFFU
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS                       0x00000080U
-#define RTC_CALIBR_DC                        0x0000001FU
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      0x80000000U
-#define RTC_ALRMAR_WDSEL                     0x40000000U
-#define RTC_ALRMAR_DT                        0x30000000U
-#define RTC_ALRMAR_DT_0                      0x10000000U
-#define RTC_ALRMAR_DT_1                      0x20000000U
-#define RTC_ALRMAR_DU                        0x0F000000U
-#define RTC_ALRMAR_DU_0                      0x01000000U
-#define RTC_ALRMAR_DU_1                      0x02000000U
-#define RTC_ALRMAR_DU_2                      0x04000000U
-#define RTC_ALRMAR_DU_3                      0x08000000U
-#define RTC_ALRMAR_MSK3                      0x00800000U
-#define RTC_ALRMAR_PM                        0x00400000U
-#define RTC_ALRMAR_HT                        0x00300000U
-#define RTC_ALRMAR_HT_0                      0x00100000U
-#define RTC_ALRMAR_HT_1                      0x00200000U
-#define RTC_ALRMAR_HU                        0x000F0000U
-#define RTC_ALRMAR_HU_0                      0x00010000U
-#define RTC_ALRMAR_HU_1                      0x00020000U
-#define RTC_ALRMAR_HU_2                      0x00040000U
-#define RTC_ALRMAR_HU_3                      0x00080000U
-#define RTC_ALRMAR_MSK2                      0x00008000U
-#define RTC_ALRMAR_MNT                       0x00007000U
-#define RTC_ALRMAR_MNT_0                     0x00001000U
-#define RTC_ALRMAR_MNT_1                     0x00002000U
-#define RTC_ALRMAR_MNT_2                     0x00004000U
-#define RTC_ALRMAR_MNU                       0x00000F00U
-#define RTC_ALRMAR_MNU_0                     0x00000100U
-#define RTC_ALRMAR_MNU_1                     0x00000200U
-#define RTC_ALRMAR_MNU_2                     0x00000400U
-#define RTC_ALRMAR_MNU_3                     0x00000800U
-#define RTC_ALRMAR_MSK1                      0x00000080U
-#define RTC_ALRMAR_ST                        0x00000070U
-#define RTC_ALRMAR_ST_0                      0x00000010U
-#define RTC_ALRMAR_ST_1                      0x00000020U
-#define RTC_ALRMAR_ST_2                      0x00000040U
-#define RTC_ALRMAR_SU                        0x0000000FU
-#define RTC_ALRMAR_SU_0                      0x00000001U
-#define RTC_ALRMAR_SU_1                      0x00000002U
-#define RTC_ALRMAR_SU_2                      0x00000004U
-#define RTC_ALRMAR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      0x80000000U
-#define RTC_ALRMBR_WDSEL                     0x40000000U
-#define RTC_ALRMBR_DT                        0x30000000U
-#define RTC_ALRMBR_DT_0                      0x10000000U
-#define RTC_ALRMBR_DT_1                      0x20000000U
-#define RTC_ALRMBR_DU                        0x0F000000U
-#define RTC_ALRMBR_DU_0                      0x01000000U
-#define RTC_ALRMBR_DU_1                      0x02000000U
-#define RTC_ALRMBR_DU_2                      0x04000000U
-#define RTC_ALRMBR_DU_3                      0x08000000U
-#define RTC_ALRMBR_MSK3                      0x00800000U
-#define RTC_ALRMBR_PM                        0x00400000U
-#define RTC_ALRMBR_HT                        0x00300000U
-#define RTC_ALRMBR_HT_0                      0x00100000U
-#define RTC_ALRMBR_HT_1                      0x00200000U
-#define RTC_ALRMBR_HU                        0x000F0000U
-#define RTC_ALRMBR_HU_0                      0x00010000U
-#define RTC_ALRMBR_HU_1                      0x00020000U
-#define RTC_ALRMBR_HU_2                      0x00040000U
-#define RTC_ALRMBR_HU_3                      0x00080000U
-#define RTC_ALRMBR_MSK2                      0x00008000U
-#define RTC_ALRMBR_MNT                       0x00007000U
-#define RTC_ALRMBR_MNT_0                     0x00001000U
-#define RTC_ALRMBR_MNT_1                     0x00002000U
-#define RTC_ALRMBR_MNT_2                     0x00004000U
-#define RTC_ALRMBR_MNU                       0x00000F00U
-#define RTC_ALRMBR_MNU_0                     0x00000100U
-#define RTC_ALRMBR_MNU_1                     0x00000200U
-#define RTC_ALRMBR_MNU_2                     0x00000400U
-#define RTC_ALRMBR_MNU_3                     0x00000800U
-#define RTC_ALRMBR_MSK1                      0x00000080U
-#define RTC_ALRMBR_ST                        0x00000070U
-#define RTC_ALRMBR_ST_0                      0x00000010U
-#define RTC_ALRMBR_ST_1                      0x00000020U
-#define RTC_ALRMBR_ST_2                      0x00000040U
-#define RTC_ALRMBR_SU                        0x0000000FU
-#define RTC_ALRMBR_SU_0                      0x00000001U
-#define RTC_ALRMBR_SU_1                      0x00000002U
-#define RTC_ALRMBR_SU_2                      0x00000004U
-#define RTC_ALRMBR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          0x000000FFU
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           0x0000FFFFU
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     0x00007FFFU
-#define RTC_SHIFTR_ADD1S                     0x80000000U
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          0x00400000U
-#define RTC_TSTR_HT                          0x00300000U
-#define RTC_TSTR_HT_0                        0x00100000U
-#define RTC_TSTR_HT_1                        0x00200000U
-#define RTC_TSTR_HU                          0x000F0000U
-#define RTC_TSTR_HU_0                        0x00010000U
-#define RTC_TSTR_HU_1                        0x00020000U
-#define RTC_TSTR_HU_2                        0x00040000U
-#define RTC_TSTR_HU_3                        0x00080000U
-#define RTC_TSTR_MNT                         0x00007000U
-#define RTC_TSTR_MNT_0                       0x00001000U
-#define RTC_TSTR_MNT_1                       0x00002000U
-#define RTC_TSTR_MNT_2                       0x00004000U
-#define RTC_TSTR_MNU                         0x00000F00U
-#define RTC_TSTR_MNU_0                       0x00000100U
-#define RTC_TSTR_MNU_1                       0x00000200U
-#define RTC_TSTR_MNU_2                       0x00000400U
-#define RTC_TSTR_MNU_3                       0x00000800U
-#define RTC_TSTR_ST                          0x00000070U
-#define RTC_TSTR_ST_0                        0x00000010U
-#define RTC_TSTR_ST_1                        0x00000020U
-#define RTC_TSTR_ST_2                        0x00000040U
-#define RTC_TSTR_SU                          0x0000000FU
-#define RTC_TSTR_SU_0                        0x00000001U
-#define RTC_TSTR_SU_1                        0x00000002U
-#define RTC_TSTR_SU_2                        0x00000004U
-#define RTC_TSTR_SU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         0x0000E000U
-#define RTC_TSDR_WDU_0                       0x00002000U
-#define RTC_TSDR_WDU_1                       0x00004000U
-#define RTC_TSDR_WDU_2                       0x00008000U
-#define RTC_TSDR_MT                          0x00001000U
-#define RTC_TSDR_MU                          0x00000F00U
-#define RTC_TSDR_MU_0                        0x00000100U
-#define RTC_TSDR_MU_1                        0x00000200U
-#define RTC_TSDR_MU_2                        0x00000400U
-#define RTC_TSDR_MU_3                        0x00000800U
-#define RTC_TSDR_DT                          0x00000030U
-#define RTC_TSDR_DT_0                        0x00000010U
-#define RTC_TSDR_DT_1                        0x00000020U
-#define RTC_TSDR_DU                          0x0000000FU
-#define RTC_TSDR_DU_0                        0x00000001U
-#define RTC_TSDR_DU_1                        0x00000002U
-#define RTC_TSDR_DU_2                        0x00000004U
-#define RTC_TSDR_DU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        0x00008000U
-#define RTC_CALR_CALW8                       0x00004000U
-#define RTC_CALR_CALW16                      0x00002000U
-#define RTC_CALR_CALM                        0x000001FFU
-#define RTC_CALR_CALM_0                      0x00000001U
-#define RTC_CALR_CALM_1                      0x00000002U
-#define RTC_CALR_CALM_2                      0x00000004U
-#define RTC_CALR_CALM_3                      0x00000008U
-#define RTC_CALR_CALM_4                      0x00000010U
-#define RTC_CALR_CALM_5                      0x00000020U
-#define RTC_CALR_CALM_6                      0x00000040U
-#define RTC_CALR_CALM_7                      0x00000080U
-#define RTC_CALR_CALM_8                      0x00000100U
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               0x00040000U
-#define RTC_TAFCR_TSINSEL                    0x00020000U
-#define RTC_TAFCR_TAMPINSEL                  0x00010000U
-#define RTC_TAFCR_TAMPPUDIS                  0x00008000U
-#define RTC_TAFCR_TAMPPRCH                   0x00006000U
-#define RTC_TAFCR_TAMPPRCH_0                 0x00002000U
-#define RTC_TAFCR_TAMPPRCH_1                 0x00004000U
-#define RTC_TAFCR_TAMPFLT                    0x00001800U
-#define RTC_TAFCR_TAMPFLT_0                  0x00000800U
-#define RTC_TAFCR_TAMPFLT_1                  0x00001000U
-#define RTC_TAFCR_TAMPFREQ                   0x00000700U
-#define RTC_TAFCR_TAMPFREQ_0                 0x00000100U
-#define RTC_TAFCR_TAMPFREQ_1                 0x00000200U
-#define RTC_TAFCR_TAMPFREQ_2                 0x00000400U
-#define RTC_TAFCR_TAMPTS                     0x00000080U
-#define RTC_TAFCR_TAMP2TRG                   0x00000010U
-#define RTC_TAFCR_TAMP2E                     0x00000008U
-#define RTC_TAFCR_TAMPIE                     0x00000004U
-#define RTC_TAFCR_TAMP1TRG                   0x00000002U
-#define RTC_TAFCR_TAMP1E                     0x00000001U
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  0x0F000000U
-#define RTC_ALRMASSR_MASKSS_0                0x01000000U
-#define RTC_ALRMASSR_MASKSS_1                0x02000000U
-#define RTC_ALRMASSR_MASKSS_2                0x04000000U
-#define RTC_ALRMASSR_MASKSS_3                0x08000000U
-#define RTC_ALRMASSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
-#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
-#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
-#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
-#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
-#define RTC_ALRMBSSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           0xFFFFFFFFU
-
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          SD host Interface                                 */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SDIO_POWER register  ******************/
-#define  SDIO_POWER_PWRCTRL                  0x03U               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDIO_POWER_PWRCTRL_0                0x01U               /*!<Bit 0 */
-#define  SDIO_POWER_PWRCTRL_1                0x02U               /*!<Bit 1 */
-
-/******************  Bit definition for SDIO_CLKCR register  ******************/
-#define  SDIO_CLKCR_CLKDIV                   0x00FFU            /*!<Clock divide factor             */
-#define  SDIO_CLKCR_CLKEN                    0x0100U            /*!<Clock enable bit                */
-#define  SDIO_CLKCR_PWRSAV                   0x0200U            /*!<Power saving configuration bit  */
-#define  SDIO_CLKCR_BYPASS                   0x0400U            /*!<Clock divider bypass enable bit */
-
-#define  SDIO_CLKCR_WIDBUS                   0x1800U            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDIO_CLKCR_WIDBUS_0                 0x0800U            /*!<Bit 0 */
-#define  SDIO_CLKCR_WIDBUS_1                 0x1000U            /*!<Bit 1 */
-
-#define  SDIO_CLKCR_NEGEDGE                  0x2000U            /*!<SDIO_CK dephasing selection bit */
-#define  SDIO_CLKCR_HWFC_EN                  0x4000U            /*!<HW Flow Control enable          */
-
-/*******************  Bit definition for SDIO_ARG register  *******************/
-#define  SDIO_ARG_CMDARG                     0xFFFFFFFFU            /*!<Command argument */
-
-/*******************  Bit definition for SDIO_CMD register  *******************/
-#define  SDIO_CMD_CMDINDEX                   0x003FU            /*!<Command Index                               */
-
-#define  SDIO_CMD_WAITRESP                   0x00C0U            /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDIO_CMD_WAITRESP_0                 0x0040U            /*!< Bit 0 */
-#define  SDIO_CMD_WAITRESP_1                 0x0080U            /*!< Bit 1 */
-
-#define  SDIO_CMD_WAITINT                    0x0100U            /*!<CPSM Waits for Interrupt Request                               */
-#define  SDIO_CMD_WAITPEND                   0x0200U            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDIO_CMD_CPSMEN                     0x0400U            /*!<Command path state machine (CPSM) Enable bit                   */
-#define  SDIO_CMD_SDIOSUSPEND                0x0800U            /*!<SD I/O suspend command                                         */
-#define  SDIO_CMD_ENCMDCOMPL                 0x1000U            /*!<Enable CMD completion                                          */
-#define  SDIO_CMD_NIEN                       0x2000U            /*!<Not Interrupt Enable */
-#define  SDIO_CMD_CEATACMD                   0x4000U            /*!<CE-ATA command       */
-
-/*****************  Bit definition for SDIO_RESPCMD register  *****************/
-#define  SDIO_RESPCMD_RESPCMD                0x3FU               /*!<Response command index */
-
-/******************  Bit definition for SDIO_RESP0 register  ******************/
-#define  SDIO_RESP0_CARDSTATUS0              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP1 register  ******************/
-#define  SDIO_RESP1_CARDSTATUS1              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP2 register  ******************/
-#define  SDIO_RESP2_CARDSTATUS2              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP3 register  ******************/
-#define  SDIO_RESP3_CARDSTATUS3              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP4 register  ******************/
-#define  SDIO_RESP4_CARDSTATUS4              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_DTIMER register  *****************/
-#define  SDIO_DTIMER_DATATIME                0xFFFFFFFFU        /*!<Data timeout period. */
-
-/******************  Bit definition for SDIO_DLEN register  *******************/
-#define  SDIO_DLEN_DATALENGTH                0x01FFFFFFU        /*!<Data length value    */
-
-/******************  Bit definition for SDIO_DCTRL register  ******************/
-#define  SDIO_DCTRL_DTEN                     0x0001U            /*!<Data transfer enabled bit         */
-#define  SDIO_DCTRL_DTDIR                    0x0002U            /*!<Data transfer direction selection */
-#define  SDIO_DCTRL_DTMODE                   0x0004U            /*!<Data transfer mode selection      */
-#define  SDIO_DCTRL_DMAEN                    0x0008U            /*!<DMA enabled bit                   */
-
-#define  SDIO_DCTRL_DBLOCKSIZE               0x00F0U            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDIO_DCTRL_DBLOCKSIZE_0             0x0010U            /*!<Bit 0 */
-#define  SDIO_DCTRL_DBLOCKSIZE_1             0x0020U            /*!<Bit 1 */
-#define  SDIO_DCTRL_DBLOCKSIZE_2             0x0040U            /*!<Bit 2 */
-#define  SDIO_DCTRL_DBLOCKSIZE_3             0x0080U            /*!<Bit 3 */
-
-#define  SDIO_DCTRL_RWSTART                  0x0100U            /*!<Read wait start         */
-#define  SDIO_DCTRL_RWSTOP                   0x0200U            /*!<Read wait stop          */
-#define  SDIO_DCTRL_RWMOD                    0x0400U            /*!<Read wait mode          */
-#define  SDIO_DCTRL_SDIOEN                   0x0800U            /*!<SD I/O enable functions */
-
-/******************  Bit definition for SDIO_DCOUNT register  *****************/
-#define  SDIO_DCOUNT_DATACOUNT               0x01FFFFFFU        /*!<Data count value */
-
-/******************  Bit definition for SDIO_STA register  ********************/
-#define  SDIO_STA_CCRCFAIL                   0x00000001U        /*!<Command response received (CRC check failed)  */
-#define  SDIO_STA_DCRCFAIL                   0x00000002U        /*!<Data block sent/received (CRC check failed)   */
-#define  SDIO_STA_CTIMEOUT                   0x00000004U        /*!<Command response timeout                      */
-#define  SDIO_STA_DTIMEOUT                   0x00000008U        /*!<Data timeout                                  */
-#define  SDIO_STA_TXUNDERR                   0x00000010U        /*!<Transmit FIFO underrun error                  */
-#define  SDIO_STA_RXOVERR                    0x00000020U        /*!<Received FIFO overrun error                   */
-#define  SDIO_STA_CMDREND                    0x00000040U        /*!<Command response received (CRC check passed)  */
-#define  SDIO_STA_CMDSENT                    0x00000080U        /*!<Command sent (no response required)           */
-#define  SDIO_STA_DATAEND                    0x00000100U        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
-#define  SDIO_STA_STBITERR                   0x00000200U        /*!<Start bit not detected on all data signals in wide bus mode */
-#define  SDIO_STA_DBCKEND                    0x00000400U        /*!<Data block sent/received (CRC check passed)   */
-#define  SDIO_STA_CMDACT                     0x00000800U        /*!<Command transfer in progress                  */
-#define  SDIO_STA_TXACT                      0x00001000U        /*!<Data transmit in progress                     */
-#define  SDIO_STA_RXACT                      0x00002000U        /*!<Data receive in progress                      */
-#define  SDIO_STA_TXFIFOHE                   0x00004000U        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDIO_STA_RXFIFOHF                   0x00008000U        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDIO_STA_TXFIFOF                    0x00010000U        /*!<Transmit FIFO full                            */
-#define  SDIO_STA_RXFIFOF                    0x00020000U        /*!<Receive FIFO full                             */
-#define  SDIO_STA_TXFIFOE                    0x00040000U        /*!<Transmit FIFO empty                           */
-#define  SDIO_STA_RXFIFOE                    0x00080000U        /*!<Receive FIFO empty                            */
-#define  SDIO_STA_TXDAVL                     0x00100000U        /*!<Data available in transmit FIFO               */
-#define  SDIO_STA_RXDAVL                     0x00200000U        /*!<Data available in receive FIFO                */
-#define  SDIO_STA_SDIOIT                     0x00400000U        /*!<SDIO interrupt received                       */
-#define  SDIO_STA_CEATAEND                   0x00800000U        /*!<CE-ATA command completion signal received for CMD61 */
-
-/*******************  Bit definition for SDIO_ICR register  *******************/
-#define  SDIO_ICR_CCRCFAILC                  0x00000001U        /*!<CCRCFAIL flag clear bit */
-#define  SDIO_ICR_DCRCFAILC                  0x00000002U        /*!<DCRCFAIL flag clear bit */
-#define  SDIO_ICR_CTIMEOUTC                  0x00000004U        /*!<CTIMEOUT flag clear bit */
-#define  SDIO_ICR_DTIMEOUTC                  0x00000008U        /*!<DTIMEOUT flag clear bit */
-#define  SDIO_ICR_TXUNDERRC                  0x00000010U        /*!<TXUNDERR flag clear bit */
-#define  SDIO_ICR_RXOVERRC                   0x00000020U        /*!<RXOVERR flag clear bit  */
-#define  SDIO_ICR_CMDRENDC                   0x00000040U        /*!<CMDREND flag clear bit  */
-#define  SDIO_ICR_CMDSENTC                   0x00000080U        /*!<CMDSENT flag clear bit  */
-#define  SDIO_ICR_DATAENDC                   0x00000100U        /*!<DATAEND flag clear bit  */
-#define  SDIO_ICR_STBITERRC                  0x00000200U        /*!<STBITERR flag clear bit */
-#define  SDIO_ICR_DBCKENDC                   0x00000400U        /*!<DBCKEND flag clear bit  */
-#define  SDIO_ICR_SDIOITC                    0x00400000U        /*!<SDIOIT flag clear bit   */
-#define  SDIO_ICR_CEATAENDC                  0x00800000U        /*!<CEATAEND flag clear bit */
-
-/******************  Bit definition for SDIO_MASK register  *******************/
-#define  SDIO_MASK_CCRCFAILIE                0x00000001U        /*!<Command CRC Fail Interrupt Enable          */
-#define  SDIO_MASK_DCRCFAILIE                0x00000002U        /*!<Data CRC Fail Interrupt Enable             */
-#define  SDIO_MASK_CTIMEOUTIE                0x00000004U        /*!<Command TimeOut Interrupt Enable           */
-#define  SDIO_MASK_DTIMEOUTIE                0x00000008U        /*!<Data TimeOut Interrupt Enable              */
-#define  SDIO_MASK_TXUNDERRIE                0x00000010U        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
-#define  SDIO_MASK_RXOVERRIE                 0x00000020U        /*!<Rx FIFO OverRun Error Interrupt Enable     */
-#define  SDIO_MASK_CMDRENDIE                 0x00000040U        /*!<Command Response Received Interrupt Enable */
-#define  SDIO_MASK_CMDSENTIE                 0x00000080U        /*!<Command Sent Interrupt Enable              */
-#define  SDIO_MASK_DATAENDIE                 0x00000100U        /*!<Data End Interrupt Enable                  */
-#define  SDIO_MASK_STBITERRIE                0x00000200U        /*!<Start Bit Error Interrupt Enable           */
-#define  SDIO_MASK_DBCKENDIE                 0x00000400U        /*!<Data Block End Interrupt Enable            */
-#define  SDIO_MASK_CMDACTIE                  0x00000800U        /*!<CCommand Acting Interrupt Enable           */
-#define  SDIO_MASK_TXACTIE                   0x00001000U        /*!<Data Transmit Acting Interrupt Enable      */
-#define  SDIO_MASK_RXACTIE                   0x00002000U        /*!<Data receive acting interrupt enabled      */
-#define  SDIO_MASK_TXFIFOHEIE                0x00004000U        /*!<Tx FIFO Half Empty interrupt Enable        */
-#define  SDIO_MASK_RXFIFOHFIE                0x00008000U        /*!<Rx FIFO Half Full interrupt Enable         */
-#define  SDIO_MASK_TXFIFOFIE                 0x00010000U        /*!<Tx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_RXFIFOFIE                 0x00020000U        /*!<Rx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_TXFIFOEIE                 0x00040000U        /*!<Tx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_RXFIFOEIE                 0x00080000U        /*!<Rx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_TXDAVLIE                  0x00100000U        /*!<Data available in Tx FIFO interrupt Enable */
-#define  SDIO_MASK_RXDAVLIE                  0x00200000U        /*!<Data available in Rx FIFO interrupt Enable */
-#define  SDIO_MASK_SDIOITIE                  0x00400000U        /*!<SDIO Mode Interrupt Received interrupt Enable */
-#define  SDIO_MASK_CEATAENDIE                0x00800000U        /*!<CE-ATA command completion signal received Interrupt Enable */
-
-/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
-#define  SDIO_FIFOCNT_FIFOCOUNT              0x00FFFFFFU        /*!<Remaining number of words to be written to or read from the FIFO */
-
-/******************  Bit definition for SDIO_FIFO register  *******************/
-#define  SDIO_FIFO_FIFODATA                  0xFFFFFFFFU        /*!<Receive and transmit FIFO data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        0x00000001U            /*!<Clock Phase      */
-#define  SPI_CR1_CPOL                        0x00000002U            /*!<Clock Polarity   */
-#define  SPI_CR1_MSTR                        0x00000004U            /*!<Master Selection */
-
-#define  SPI_CR1_BR                          0x00000038U            /*!<BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        0x00000008U            /*!<Bit 0 */
-#define  SPI_CR1_BR_1                        0x00000010U            /*!<Bit 1 */
-#define  SPI_CR1_BR_2                        0x00000020U            /*!<Bit 2 */
-
-#define  SPI_CR1_SPE                         0x00000040U            /*!<SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    0x00000080U            /*!<Frame Format                        */
-#define  SPI_CR1_SSI                         0x00000100U            /*!<Internal slave select               */
-#define  SPI_CR1_SSM                         0x00000200U            /*!<Software slave management           */
-#define  SPI_CR1_RXONLY                      0x00000400U            /*!<Receive only                        */
-#define  SPI_CR1_DFF                         0x00000800U            /*!<Data Frame Format                   */
-#define  SPI_CR1_CRCNEXT                     0x00001000U            /*!<Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       0x00002000U            /*!<Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      0x00004000U            /*!<Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    0x00008000U            /*!<Bidirectional data mode enable      */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     0x00000001U               /*!<Rx Buffer DMA Enable                 */
-#define  SPI_CR2_TXDMAEN                     0x00000002U               /*!<Tx Buffer DMA Enable                 */
-#define  SPI_CR2_SSOE                        0x00000004U               /*!<SS Output Enable                     */
-#define  SPI_CR2_FRF                         0x00000010U               /*!<Frame Format                         */
-#define  SPI_CR2_ERRIE                       0x00000020U               /*!<Error Interrupt Enable               */
-#define  SPI_CR2_RXNEIE                      0x00000040U               /*!<RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       0x00000080U               /*!<Tx buffer Empty Interrupt Enable     */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         0x00000001U               /*!<Receive buffer Not Empty */
-#define  SPI_SR_TXE                          0x00000002U               /*!<Transmit buffer Empty    */
-#define  SPI_SR_CHSIDE                       0x00000004U               /*!<Channel side             */
-#define  SPI_SR_UDR                          0x00000008U               /*!<Underrun flag            */
-#define  SPI_SR_CRCERR                       0x00000010U               /*!<CRC Error flag           */
-#define  SPI_SR_MODF                         0x00000020U               /*!<Mode fault               */
-#define  SPI_SR_OVR                          0x00000040U               /*!<Overrun flag             */
-#define  SPI_SR_BSY                          0x00000080U               /*!<Busy flag                */
-#define  SPI_SR_FRE                          0x00000100U               /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           0x0000FFFFU            /*!<Data Register           */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   0x0000FFFFU            /*!<CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    0x0000FFFFU            /*!<Rx CRC Register         */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    0x0000FFFFU            /*!<Tx CRC Register         */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   0x00000001U            /*!<Channel length (number of bits per audio channel) */
-
-#define  SPI_I2SCFGR_DATLEN                  0x00000006U            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define  SPI_I2SCFGR_DATLEN_0                0x00000002U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                0x00000004U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_CKPOL                   0x00000008U            /*!<steady state clock polarity               */
-
-#define  SPI_I2SCFGR_I2SSTD                  0x00000030U            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U            /*!<PCM frame synchronization                 */
-
-#define  SPI_I2SCFGR_I2SCFG                  0x00000300U            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_I2SE                    0x00000400U            /*!<I2S Enable         */
-#define  SPI_I2SCFGR_I2SMOD                  0x00000800U            /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    0x000000FFU            /*!<I2S Linear prescaler         */
-#define  SPI_I2SPR_ODD                       0x00000100U            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     0x00000200U            /*!<Master Clock Output Enable   */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 SYSCFG                                     */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
-#define SYSCFG_MEMRMP_MEM_MODE          0x00000007U /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        0x00000001U
-#define SYSCFG_MEMRMP_MEM_MODE_1        0x00000002U
-#define SYSCFG_MEMRMP_MEM_MODE_2        0x00000004U
-
-/******************  Bit definition for SYSCFG_PMC register  ******************/
-#define SYSCFG_PMC_ADC1DC2              0x00010000U /*!< Refer to AN4073 on how to use this bit  */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
-/** 
-  * @brief   EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         0x0003U /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         0x0004U /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
-
-/** 
-  * @brief   EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         0x0030U /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         0x0040U /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
-
-/** 
-  * @brief   EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         0x0300U /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         0x0400U /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
-
-/** 
-  * @brief   EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         0x3000U /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         0x4000U /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
-/** 
-  * @brief   EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         0x0003U /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         0x0004U /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
-
-/** 
-  * @brief   EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         0x0030U /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         0x0040U /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
-
-/** 
-  * @brief   EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         0x0300U /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         0x0400U /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
-
-/** 
-  * @brief   EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         0x3000U /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         0x4000U /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
-
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
-           
-/** 
-  * @brief   EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         0x0003U /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         0x0004U /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
-
-/** 
-  * @brief   EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         0x0030U /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         0x0040U /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
-
-/** 
-  * @brief   EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        0x0300U /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        0x0400U /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
-
-/** 
-  * @brief   EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        0x3000U /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        0x4000U /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
-/** 
-  * @brief   EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        0x0003U /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        0x0004U /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
-
-/** 
-  * @brief   EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        0x0030U /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        0x0040U /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
-
-/** 
-  * @brief   EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        0x0300U /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        0x0400U /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
-
-/** 
-  * @brief   EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        0x3000U /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        0x4000U /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
-
-/******************  Bit definition for SYSCFG_CMPCR register  ****************/  
-#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell ready flag */
-#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell power-down */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    TIM                                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
-#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
-#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
-#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
-#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
-
-#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
-
-#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
-
-#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        0x0001U            /*!<Capture/Compare Preloaded Control        */
-#define  TIM_CR2_CCUS                        0x0004U            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        0x0008U            /*!<Capture/Compare DMA Selection            */
-
-#define  TIM_CR2_MMS                         0x0070U            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
-#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
-#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
-#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        0x0007U            /*!<SMS[2:0] bits (Slave mode selection)    */
-#define  TIM_SMCR_SMS_0                      0x0001U            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      0x0002U            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      0x0004U            /*!<Bit 2 */
-
-#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
-#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
-
-#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
-
-#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
-
-#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
-#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
-#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
-#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
-#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
-#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
-#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
-#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
-#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
-#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
-#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
-#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
-#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
-#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
-#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
-#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
-#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
-#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
-#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          0x01U               /*!<Update Generation                         */
-#define  TIM_EGR_CC1G                        0x02U               /*!<Capture/Compare 1 Generation              */
-#define  TIM_EGR_CC2G                        0x04U               /*!<Capture/Compare 2 Generation              */
-#define  TIM_EGR_CC3G                        0x08U               /*!<Capture/Compare 3 Generation              */
-#define  TIM_EGR_CC4G                        0x10U               /*!<Capture/Compare 4 Generation              */
-#define  TIM_EGR_COMG                        0x20U               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          0x40U               /*!<Trigger Generation                        */
-#define  TIM_EGR_BG                          0x80U               /*!<Break Generation                          */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      0x0003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    0x0001U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    0x0002U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC1FE                     0x0004U            /*!<Output Compare 1 Fast enable                 */
-#define  TIM_CCMR1_OC1PE                     0x0008U            /*!<Output Compare 1 Preload enable              */
-
-#define  TIM_CCMR1_OC1M                      0x0070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define  TIM_CCMR1_OC1M_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    0x0040U            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC1CE                     0x0080U            /*!<Output Compare 1Clear Enable                 */
-
-#define  TIM_CCMR1_CC2S                      0x0300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    0x0100U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    0x0200U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC2FE                     0x0400U            /*!<Output Compare 2 Fast enable                 */
-#define  TIM_CCMR1_OC2PE                     0x0800U            /*!<Output Compare 2 Preload enable              */
-
-#define  TIM_CCMR1_OC2M                      0x7000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define  TIM_CCMR1_OC2M_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    0x4000U            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC2CE                     0x8000U            /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      0x0003U            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define  TIM_CCMR2_CC3S_0                    0x0001U            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    0x0002U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC3FE                     0x0004U            /*!<Output Compare 3 Fast enable           */
-#define  TIM_CCMR2_OC3PE                     0x0008U            /*!<Output Compare 3 Preload enable        */
-
-#define  TIM_CCMR2_OC3M                      0x0070U            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    0x0040U            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC3CE                     0x0080U            /*!<Output Compare 3 Clear Enable */
-
-#define  TIM_CCMR2_CC4S                      0x0300U            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    0x0100U            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    0x0200U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC4FE                     0x0400U            /*!<Output Compare 4 Fast enable    */
-#define  TIM_CCMR2_OC4PE                     0x0800U            /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR2_OC4M                      0x7000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    0x4000U            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       0x0001U            /*!<Capture/Compare 1 output enable                 */
-#define  TIM_CCER_CC1P                       0x0002U            /*!<Capture/Compare 1 output Polarity               */
-#define  TIM_CCER_CC1NE                      0x0004U            /*!<Capture/Compare 1 Complementary output enable   */
-#define  TIM_CCER_CC1NP                      0x0008U            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       0x0010U            /*!<Capture/Compare 2 output enable                 */
-#define  TIM_CCER_CC2P                       0x0020U            /*!<Capture/Compare 2 output Polarity               */
-#define  TIM_CCER_CC2NE                      0x0040U            /*!<Capture/Compare 2 Complementary output enable   */
-#define  TIM_CCER_CC2NP                      0x0080U            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       0x0100U            /*!<Capture/Compare 3 output enable                 */
-#define  TIM_CCER_CC3P                       0x0200U            /*!<Capture/Compare 3 output Polarity               */
-#define  TIM_CCER_CC3NE                      0x0400U            /*!<Capture/Compare 3 Complementary output enable   */
-#define  TIM_CCER_CC3NP                      0x0800U            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       0x1000U            /*!<Capture/Compare 4 output enable                 */
-#define  TIM_CCER_CC4P                       0x2000U            /*!<Capture/Compare 4 output Polarity               */
-#define  TIM_CCER_CC4NP                      0x8000U            /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         0xFFU               /*!<Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
-
-/*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        0x00FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      0x0001U            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      0x0002U            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      0x0004U            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      0x0008U            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      0x0010U            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      0x0020U            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      0x0040U            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      0x0080U            /*!<Bit 7 */
-
-#define  TIM_BDTR_LOCK                       0x0300U            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     0x0100U            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     0x0200U            /*!<Bit 1 */
-
-#define  TIM_BDTR_OSSI                       0x0400U            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       0x0800U            /*!<Off-State Selection for Run mode  */
-#define  TIM_BDTR_BKE                        0x1000U            /*!<Break enable                      */
-#define  TIM_BDTR_BKP                        0x2000U            /*!<Break Polarity                    */
-#define  TIM_BDTR_AOE                        0x4000U            /*!<Automatic Output enable           */
-#define  TIM_BDTR_MOE                        0x8000U            /*!<Main Output enable                */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
-
-#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
-#define TIM_OR_ITR1_RMP                      0x0C00U            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
-#define TIM_OR_ITR1_RMP_0                    0x0400U            /*!<Bit 0 */
-#define TIM_OR_ITR1_RMP_1                    0x0800U            /*!<Bit 1 */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*         Universal Synchronous Asynchronous Receiver Transmitter            */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         0x0001U            /*!<Parity Error                 */
-#define  USART_SR_FE                         0x0002U            /*!<Framing Error                */
-#define  USART_SR_NE                         0x0004U            /*!<Noise Error Flag             */
-#define  USART_SR_ORE                        0x0008U            /*!<OverRun Error                */
-#define  USART_SR_IDLE                       0x0010U            /*!<IDLE line detected           */
-#define  USART_SR_RXNE                       0x0020U            /*!<Read Data Register Not Empty */
-#define  USART_SR_TC                         0x0040U            /*!<Transmission Complete        */
-#define  USART_SR_TXE                        0x0080U            /*!<Transmit Data Register Empty */
-#define  USART_SR_LBD                        0x0100U            /*!<LIN Break Detection Flag     */
-#define  USART_SR_CTS                        0x0200U            /*!<CTS Flag                     */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         0x01FFU            /*!<Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_Fraction              0x000FU            /*!<Fraction of USARTDIV */
-#define  USART_BRR_DIV_Mantissa              0xFFF0U            /*!<Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       0x0001U            /*!<Send Break                             */
-#define  USART_CR1_RWU                       0x0002U            /*!<Receiver wakeup                        */
-#define  USART_CR1_RE                        0x0004U            /*!<Receiver Enable                        */
-#define  USART_CR1_TE                        0x0008U            /*!<Transmitter Enable                     */
-#define  USART_CR1_IDLEIE                    0x0010U            /*!<IDLE Interrupt Enable                  */
-#define  USART_CR1_RXNEIE                    0x0020U            /*!<RXNE Interrupt Enable                  */
-#define  USART_CR1_TCIE                      0x0040U            /*!<Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     0x0080U            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PEIE                      0x0100U            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PS                        0x0200U            /*!<Parity Selection                       */
-#define  USART_CR1_PCE                       0x0400U            /*!<Parity Control Enable                  */
-#define  USART_CR1_WAKE                      0x0800U            /*!<Wakeup method                          */
-#define  USART_CR1_M                         0x1000U            /*!<Word length                            */
-#define  USART_CR1_UE                        0x2000U            /*!<USART Enable                           */
-#define  USART_CR1_OVER8                     0x8000U            /*!<USART Oversampling by 8 enable         */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       0x000FU            /*!<Address of the USART node            */
-#define  USART_CR2_LBDL                      0x0020U            /*!<LIN Break Detection Length           */
-#define  USART_CR2_LBDIE                     0x0040U            /*!<LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      0x0100U            /*!<Last Bit Clock pulse                 */
-#define  USART_CR2_CPHA                      0x0200U            /*!<Clock Phase                          */
-#define  USART_CR2_CPOL                      0x0400U            /*!<Clock Polarity                       */
-#define  USART_CR2_CLKEN                     0x0800U            /*!<Clock Enable                         */
-
-#define  USART_CR2_STOP                      0x3000U            /*!<STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    0x1000U            /*!<Bit 0 */
-#define  USART_CR2_STOP_1                    0x2000U            /*!<Bit 1 */
-
-#define  USART_CR2_LINEN                     0x4000U            /*!<LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       0x0001U            /*!<Error Interrupt Enable      */
-#define  USART_CR3_IREN                      0x0002U            /*!<IrDA mode Enable            */
-#define  USART_CR3_IRLP                      0x0004U            /*!<IrDA Low-Power              */
-#define  USART_CR3_HDSEL                     0x0008U            /*!<Half-Duplex Selection       */
-#define  USART_CR3_NACK                      0x0010U            /*!<Smartcard NACK enable       */
-#define  USART_CR3_SCEN                      0x0020U            /*!<Smartcard mode enable       */
-#define  USART_CR3_DMAR                      0x0040U            /*!<DMA Enable Receiver         */
-#define  USART_CR3_DMAT                      0x0080U            /*!<DMA Enable Transmitter      */
-#define  USART_CR3_RTSE                      0x0100U            /*!<RTS Enable                  */
-#define  USART_CR3_CTSE                      0x0200U            /*!<CTS Enable                  */
-#define  USART_CR3_CTSIE                     0x0400U            /*!<CTS Interrupt Enable        */
-#define  USART_CR3_ONEBIT                    0x0800U            /*!<USART One bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      0x00FFU            /*!<PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    0x0001U            /*!<Bit 0 */
-#define  USART_GTPR_PSC_1                    0x0002U            /*!<Bit 1 */
-#define  USART_GTPR_PSC_2                    0x0004U            /*!<Bit 2 */
-#define  USART_GTPR_PSC_3                    0x0008U            /*!<Bit 3 */
-#define  USART_GTPR_PSC_4                    0x0010U            /*!<Bit 4 */
-#define  USART_GTPR_PSC_5                    0x0020U            /*!<Bit 5 */
-#define  USART_GTPR_PSC_6                    0x0040U            /*!<Bit 6 */
-#define  USART_GTPR_PSC_7                    0x0080U            /*!<Bit 7 */
-
-#define  USART_GTPR_GT                       0xFF00U            /*!<Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Window WATCHDOG                                 */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           0x7FU               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T_0                         0x01U               /*!<Bit 0 */
-#define  WWDG_CR_T_1                         0x02U               /*!<Bit 1 */
-#define  WWDG_CR_T_2                         0x04U               /*!<Bit 2 */
-#define  WWDG_CR_T_3                         0x08U               /*!<Bit 3 */
-#define  WWDG_CR_T_4                         0x10U               /*!<Bit 4 */
-#define  WWDG_CR_T_5                         0x20U               /*!<Bit 5 */
-#define  WWDG_CR_T_6                         0x40U               /*!<Bit 6 */
-/* Legacy defines */
-#define  WWDG_CR_T0                          WWDG_CR_T_0
-#define  WWDG_CR_T1                          WWDG_CR_T_1
-#define  WWDG_CR_T2                          WWDG_CR_T_2
-#define  WWDG_CR_T3                          WWDG_CR_T_3
-#define  WWDG_CR_T4                          WWDG_CR_T_4
-#define  WWDG_CR_T5                          WWDG_CR_T_5
-#define  WWDG_CR_T6                          WWDG_CR_T_6
-
-#define  WWDG_CR_WDGA                        0x80U               /*!<Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          0x007FU            /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W_0                        0x0001U            /*!<Bit 0 */
-#define  WWDG_CFR_W_1                        0x0002U            /*!<Bit 1 */
-#define  WWDG_CFR_W_2                        0x0004U            /*!<Bit 2 */
-#define  WWDG_CFR_W_3                        0x0008U            /*!<Bit 3 */
-#define  WWDG_CFR_W_4                        0x0010U            /*!<Bit 4 */
-#define  WWDG_CFR_W_5                        0x0020U            /*!<Bit 5 */
-#define  WWDG_CFR_W_6                        0x0040U            /*!<Bit 6 */
-/* Legacy defines */
-#define  WWDG_CFR_W0                         WWDG_CFR_W_0
-#define  WWDG_CFR_W1                         WWDG_CFR_W_1
-#define  WWDG_CFR_W2                         WWDG_CFR_W_2
-#define  WWDG_CFR_W3                         WWDG_CFR_W_3
-#define  WWDG_CFR_W4                         WWDG_CFR_W_4
-#define  WWDG_CFR_W5                         WWDG_CFR_W_5
-#define  WWDG_CFR_W6                         WWDG_CFR_W_6
-
-#define  WWDG_CFR_WDGTB                      0x0180U            /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB_0                    0x0080U            /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB_1                    0x0100U            /*!<Bit 1 */
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
-
-#define  WWDG_CFR_EWI                        0x0200U            /*!<Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        0x01U               /*!<Early Wakeup Interrupt Flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                DBG                                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
-#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
-
-/********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
-#define  DBGMCU_CR_DBG_STOP                  0x00000002U
-#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
-#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
-
-#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
-#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U/*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U/*!<Bit 1 */
-
-/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            0x00000001U
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            0x00000002U
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            0x00000004U
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            0x00000020U
-#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           0x00000040U
-#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           0x00000080U
-#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           0x00000100U
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
-#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
-/* Old IWDGSTOP bit definition, maintained for legacy purpose */
-#define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
-
-/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        0x00000001U
-#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        0x00000002U
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        0x00010000U
-#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       0x00020000U
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       0x00040000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                                       USB_OTG			                        */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/
-#define USB_OTG_GOTGCTL_SRQSCS                  0x00000001U            /*!< Session request success */
-#define USB_OTG_GOTGCTL_SRQ                     0x00000002U            /*!< Session request */
-#define USB_OTG_GOTGCTL_HNGSCS                  0x00000100U            /*!< Host negotiation success */
-#define USB_OTG_GOTGCTL_HNPRQ                   0x00000200U            /*!< HNP request */
-#define USB_OTG_GOTGCTL_HSHNPEN                 0x00000400U            /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_DHNPEN                  0x00000800U            /*!< Device HNP enabled */
-#define USB_OTG_GOTGCTL_CIDSTS                  0x00010000U            /*!< Connector ID status */
-#define USB_OTG_GOTGCTL_DBCT                    0x00020000U            /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD                   0x00040000U            /*!< A-session valid */
-#define USB_OTG_GOTGCTL_BSVLD                   0x00080000U            /*!< B-session valid */
-
-/********************  Bit definition forUSB_OTG_HCFG register  ********************/
-
-#define USB_OTG_HCFG_FSLSPCS                 0x00000003U            /*!< FS/LS PHY clock select */
-#define USB_OTG_HCFG_FSLSPCS_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCFG_FSLSPCS_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCFG_FSLSS                   0x00000004U            /*!< FS- and LS-only support */
-
-/********************  Bit definition forUSB_OTG_DCFG register  ********************/
-
-#define USB_OTG_DCFG_DSPD                    0x00000003U            /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                  0x00000001U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DSPD_1                  0x00000002U            /*!<Bit 1 */
-#define USB_OTG_DCFG_NZLSOHSK                0x00000004U            /*!< Nonzero-length status OUT handshake */
-
-#define USB_OTG_DCFG_DAD                     0x000007F0U            /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                   0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DAD_1                   0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCFG_DAD_2                   0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCFG_DAD_3                   0x00000080U            /*!<Bit 3 */
-#define USB_OTG_DCFG_DAD_4                   0x00000100U            /*!<Bit 4 */
-#define USB_OTG_DCFG_DAD_5                   0x00000200U            /*!<Bit 5 */
-#define USB_OTG_DCFG_DAD_6                   0x00000400U            /*!<Bit 6 */
-
-#define USB_OTG_DCFG_PFIVL                   0x00001800U            /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PFIVL_1                 0x00001000U            /*!<Bit 1 */
-
-#define USB_OTG_DCFG_PERSCHIVL               0x03000000U            /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0             0x01000000U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PERSCHIVL_1             0x02000000U            /*!<Bit 1 */
-
-/********************  Bit definition forUSB_OTG_PCGCR register  ********************/
-#define USB_OTG_PCGCR_STPPCLK                 0x00000001U            /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK                0x00000002U            /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP                 0x00000010U            /*!< PHY suspended */
-
-/********************  Bit definition forUSB_OTG_GOTGINT register  ********************/
-#define USB_OTG_GOTGINT_SEDET                   0x00000004U            /*!< Session end detected */
-#define USB_OTG_GOTGINT_SRSSCHG                 0x00000100U            /*!< Session request success status change */
-#define USB_OTG_GOTGINT_HNSSCHG                 0x00000200U            /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET                  0x00020000U            /*!< Host negotiation detected */
-#define USB_OTG_GOTGINT_ADTOCHG                 0x00040000U            /*!< A-device timeout change */
-#define USB_OTG_GOTGINT_DBCDNE                  0x00080000U            /*!< Debounce done */
-
-/********************  Bit definition forUSB_OTG_DCTL register  ********************/
-#define USB_OTG_DCTL_RWUSIG                  0x00000001U            /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS                    0x00000002U            /*!< Soft disconnect */
-#define USB_OTG_DCTL_GINSTS                  0x00000004U            /*!< Global IN NAK status */
-#define USB_OTG_DCTL_GONSTS                  0x00000008U            /*!< Global OUT NAK status */
-
-#define USB_OTG_DCTL_TCTL                    0x00000070U            /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                  0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCTL_TCTL_1                  0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCTL_TCTL_2                  0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCTL_SGINAK                  0x00000080U            /*!< Set global IN NAK */
-#define USB_OTG_DCTL_CGINAK                  0x00000100U            /*!< Clear global IN NAK */
-#define USB_OTG_DCTL_SGONAK                  0x00000200U            /*!< Set global OUT NAK */
-#define USB_OTG_DCTL_CGONAK                  0x00000400U            /*!< Clear global OUT NAK */
-#define USB_OTG_DCTL_POPRGDNE                0x00000800U            /*!< Power-on programming done */
-
-/********************  Bit definition forUSB_OTG_HFIR register  ********************/
-#define USB_OTG_HFIR_FRIVL                   0x0000FFFFU            /*!< Frame interval */
-
-/********************  Bit definition forUSB_OTG_HFNUM register  ********************/
-#define USB_OTG_HFNUM_FRNUM                   0x0000FFFFU            /*!< Frame number */
-#define USB_OTG_HFNUM_FTREM                   0xFFFF0000U            /*!< Frame time remaining */
-
-/********************  Bit definition forUSB_OTG_DSTS register  ********************/
-#define USB_OTG_DSTS_SUSPSTS                 0x00000001U            /*!< Suspend status */
-
-#define USB_OTG_DSTS_ENUMSPD                 0x00000006U            /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_DSTS_ENUMSPD_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_DSTS_EERR                    0x00000008U            /*!< Erratic error */
-#define USB_OTG_DSTS_FNSOF                   0x003FFF00U            /*!< Frame number of the received SOF */
-
-/********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/
-#define USB_OTG_GAHBCFG_GINT                    0x00000001U            /*!< Global interrupt mask */
-
-#define USB_OTG_GAHBCFG_HBSTLEN                 0x0000001EU            /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_GAHBCFG_HBSTLEN_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_GAHBCFG_HBSTLEN_2               0x00000008U            /*!<Bit 2 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3               0x00000010U            /*!<Bit 3 */
-#define USB_OTG_GAHBCFG_DMAEN                   0x00000020U            /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL                 0x00000080U            /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL                0x00000100U            /*!< Periodic TxFIFO empty level */
-
-/********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/
-
-#define USB_OTG_GUSBCFG_TOCAL                   0x00000007U            /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TOCAL_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TOCAL_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_PHYSEL                  0x00000040U            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP                  0x00000100U            /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP                  0x00000200U            /*!< HNP-capable */
-
-#define USB_OTG_GUSBCFG_TRDT                    0x00003C00U            /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                  0x00000400U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TRDT_1                  0x00000800U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TRDT_2                  0x00001000U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_TRDT_3                  0x00002000U            /*!<Bit 3 */
-#define USB_OTG_GUSBCFG_PHYLPCS                 0x00008000U            /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS                0x00020000U            /*!< ULPI FS/LS select */
-#define USB_OTG_GUSBCFG_ULPIAR                  0x00040000U            /*!< ULPI Auto-resume */
-#define USB_OTG_GUSBCFG_ULPICSM                 0x00080000U            /*!< ULPI Clock SuspendM */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD              0x00100000U            /*!< ULPI External VBUS Drive */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI              0x00200000U            /*!< ULPI external VBUS indicator */
-#define USB_OTG_GUSBCFG_TSDPS                   0x00400000U            /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI                    0x00800000U            /*!< Indicator complement */
-#define USB_OTG_GUSBCFG_PTCI                    0x01000000U            /*!< Indicator pass through */
-#define USB_OTG_GUSBCFG_ULPIIPD                 0x02000000U            /*!< ULPI interface protect disable */
-#define USB_OTG_GUSBCFG_FHMOD                   0x20000000U            /*!< Forced host mode */
-#define USB_OTG_GUSBCFG_FDMOD                   0x40000000U            /*!< Forced peripheral mode */
-#define USB_OTG_GUSBCFG_CTXPKT                  0x80000000U            /*!< Corrupt Tx packet */
-
-/********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
-#define USB_OTG_GRSTCTL_CSRST                   0x00000001U            /*!< Core soft reset */
-#define USB_OTG_GRSTCTL_HSRST                   0x00000002U            /*!< HCLK soft reset */
-#define USB_OTG_GRSTCTL_FCRST                   0x00000004U            /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH                 0x00000010U            /*!< RxFIFO flush */
-#define USB_OTG_GRSTCTL_TXFFLSH                 0x00000020U            /*!< TxFIFO flush */
-
-#define USB_OTG_GRSTCTL_TXFNUM                  0x000007C0U            /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                0x00000040U            /*!<Bit 0 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                0x00000080U            /*!<Bit 1 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                0x00000100U            /*!<Bit 2 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                0x00000200U            /*!<Bit 3 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                0x00000400U            /*!<Bit 4 */
-#define USB_OTG_GRSTCTL_DMAREQ                  0x40000000U            /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL                  0x80000000U            /*!< AHB master idle */
-
-/********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/
-#define USB_OTG_DIEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPMSK_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPMSK_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPMSK_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPMSK_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPMSK_BIM                     0x00000200U            /*!< BNA interrupt mask */
-
-/********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/
-#define USB_OTG_HPTXSTS_PTXFSAVL                0x0000FFFFU            /*!< Periodic transmit data FIFO space available */
-
-#define USB_OTG_HPTXSTS_PTXQSAV                 0x00FF0000U            /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0               0x00010000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1               0x00020000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2               0x00040000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3               0x00080000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4               0x00100000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5               0x00200000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6               0x00400000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7               0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_HPTXSTS_PTXQTOP                 0xFF000000U            /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0               0x01000000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1               0x02000000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2               0x04000000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3               0x08000000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4               0x10000000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5               0x20000000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6               0x40000000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7               0x80000000U            /*!<Bit 7 */
-
-/********************  Bit definition forUSB_OTG_HAINT register  ********************/
-#define USB_OTG_HAINT_HAINT                   0x0000FFFFU            /*!< Channel interrupts */
-
-/********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/
-#define USB_OTG_DOEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPMSK_STUPM                   0x00000008U            /*!< SETUP phase done mask */
-#define USB_OTG_DOEPMSK_OTEPDM                  0x00000010U            /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received mask */
-#define USB_OTG_DOEPMSK_OPEM                    0x00000100U            /*!< OUT packet error mask */
-#define USB_OTG_DOEPMSK_BOIM                    0x00000200U            /*!< BNA interrupt mask */
-
-/********************  Bit definition forUSB_OTG_GINTSTS register  ********************/
-#define USB_OTG_GINTSTS_CMOD                    0x00000001U            /*!< Current mode of operation */
-#define USB_OTG_GINTSTS_MMIS                    0x00000002U            /*!< Mode mismatch interrupt */
-#define USB_OTG_GINTSTS_OTGINT                  0x00000004U            /*!< OTG interrupt */
-#define USB_OTG_GINTSTS_SOF                     0x00000008U            /*!< Start of frame */
-#define USB_OTG_GINTSTS_RXFLVL                  0x00000010U            /*!< RxFIFO nonempty */
-#define USB_OTG_GINTSTS_NPTXFE                  0x00000020U            /*!< Nonperiodic TxFIFO empty */
-#define USB_OTG_GINTSTS_GINAKEFF                0x00000040U            /*!< Global IN nonperiodic NAK effective */
-#define USB_OTG_GINTSTS_BOUTNAKEFF              0x00000080U            /*!< Global OUT NAK effective */
-#define USB_OTG_GINTSTS_ESUSP                   0x00000400U            /*!< Early suspend */
-#define USB_OTG_GINTSTS_USBSUSP                 0x00000800U            /*!< USB suspend */
-#define USB_OTG_GINTSTS_USBRST                  0x00001000U            /*!< USB reset */
-#define USB_OTG_GINTSTS_ENUMDNE                 0x00002000U            /*!< Enumeration done */
-#define USB_OTG_GINTSTS_ISOODRP                 0x00004000U            /*!< Isochronous OUT packet dropped interrupt */
-#define USB_OTG_GINTSTS_EOPF                    0x00008000U            /*!< End of periodic frame interrupt */
-#define USB_OTG_GINTSTS_IEPINT                  0x00040000U            /*!< IN endpoint interrupt */
-#define USB_OTG_GINTSTS_OEPINT                  0x00080000U            /*!< OUT endpoint interrupt */
-#define USB_OTG_GINTSTS_IISOIXFR                0x00100000U            /*!< Incomplete isochronous IN transfer */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       0x00200000U            /*!< Incomplete periodic transfer */
-#define USB_OTG_GINTSTS_DATAFSUSP               0x00400000U            /*!< Data fetch suspended */
-#define USB_OTG_GINTSTS_HPRTINT                 0x01000000U            /*!< Host port interrupt */
-#define USB_OTG_GINTSTS_HCINT                   0x02000000U            /*!< Host channels interrupt */
-#define USB_OTG_GINTSTS_PTXFE                   0x04000000U            /*!< Periodic TxFIFO empty */
-#define USB_OTG_GINTSTS_CIDSCHG                 0x10000000U            /*!< Connector ID status change */
-#define USB_OTG_GINTSTS_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt */
-#define USB_OTG_GINTSTS_SRQINT                  0x40000000U            /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT                  0x80000000U            /*!< Resume/remote wakeup detected interrupt */
-
-/********************  Bit definition forUSB_OTG_GINTMSK register  ********************/
-#define USB_OTG_GINTMSK_MMISM                   0x00000002U            /*!< Mode mismatch interrupt mask */
-#define USB_OTG_GINTMSK_OTGINT                  0x00000004U            /*!< OTG interrupt mask */
-#define USB_OTG_GINTMSK_SOFM                    0x00000008U            /*!< Start of frame mask */
-#define USB_OTG_GINTMSK_RXFLVLM                 0x00000010U            /*!< Receive FIFO nonempty mask */
-#define USB_OTG_GINTMSK_NPTXFEM                 0x00000020U            /*!< Nonperiodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_GINAKEFFM               0x00000040U            /*!< Global nonperiodic IN NAK effective mask */
-#define USB_OTG_GINTMSK_GONAKEFFM               0x00000080U            /*!< Global OUT NAK effective mask */
-#define USB_OTG_GINTMSK_ESUSPM                  0x00000400U            /*!< Early suspend mask */
-#define USB_OTG_GINTMSK_USBSUSPM                0x00000800U            /*!< USB suspend mask */
-#define USB_OTG_GINTMSK_USBRST                  0x00001000U            /*!< USB reset mask */
-#define USB_OTG_GINTMSK_ENUMDNEM                0x00002000U            /*!< Enumeration done mask */
-#define USB_OTG_GINTMSK_ISOODRPM                0x00004000U            /*!< Isochronous OUT packet dropped interrupt mask */
-#define USB_OTG_GINTMSK_EOPFM                   0x00008000U            /*!< End of periodic frame interrupt mask */
-#define USB_OTG_GINTMSK_EPMISM                  0x00020000U            /*!< Endpoint mismatch interrupt mask */
-#define USB_OTG_GINTMSK_IEPINT                  0x00040000U            /*!< IN endpoints interrupt mask */
-#define USB_OTG_GINTMSK_OEPINT                  0x00080000U            /*!< OUT endpoints interrupt mask */
-#define USB_OTG_GINTMSK_IISOIXFRM               0x00100000U            /*!< Incomplete isochronous IN transfer mask */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         0x00200000U            /*!< Incomplete periodic transfer mask */
-#define USB_OTG_GINTMSK_FSUSPM                  0x00400000U            /*!< Data fetch suspended mask */
-#define USB_OTG_GINTMSK_PRTIM                   0x01000000U            /*!< Host port interrupt mask */
-#define USB_OTG_GINTMSK_HCIM                    0x02000000U            /*!< Host channels interrupt mask */
-#define USB_OTG_GINTMSK_PTXFEM                  0x04000000U            /*!< Periodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_CIDSCHGM                0x10000000U            /*!< Connector ID status change mask */
-#define USB_OTG_GINTMSK_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt mask */
-#define USB_OTG_GINTMSK_SRQIM                   0x40000000U            /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM                    0x80000000U            /*!< Resume/remote wakeup detected interrupt mask */
-
-/********************  Bit definition forUSB_OTG_DAINT register  ********************/
-#define USB_OTG_DAINT_IEPINT                  0x0000FFFFU            /*!< IN endpoint interrupt bits */
-#define USB_OTG_DAINT_OEPINT                  0xFFFF0000U            /*!< OUT endpoint interrupt bits */
-
-/********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/
-#define USB_OTG_HAINTMSK_HAINTM                  0x0000FFFFU            /*!< Channel interrupt mask */
-
-/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
-#define USB_OTG_GRXSTSP_EPNUM                    0x0000000FU            /*!< IN EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_BCNT                     0x00007FF0U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID                     0x00018000U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS                   0x001E0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/
-#define USB_OTG_DAINTMSK_IEPM                    0x0000FFFFU            /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM                    0xFFFF0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for OTG register  ********************/
-
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition for OTG register  ********************/
-
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/
-#define USB_OTG_GRXFSIZ_RXFD                    0x0000FFFFU            /*!< RxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/
-#define USB_OTG_DVBUSDIS_VBUSDT                  0x0000FFFFU            /*!< Device VBUS discharge time */
-
-/********************  Bit definition for OTG register  ********************/
-#define USB_OTG_NPTXFSA                 0x0000FFFFU            /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD                  0xFFFF0000U            /*!< Nonperiodic TxFIFO depth */
-#define USB_OTG_TX0FSA                  0x0000FFFFU            /*!< Endpoint 0 transmit RAM start address */
-#define USB_OTG_TX0FD                   0xFFFF0000U            /*!< Endpoint 0 TxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
-#define USB_OTG_DVBUSPULSE_DVBUSP                  0x00000FFFU            /*!< Device VBUS pulsing time */
-
-/********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/
-#define USB_OTG_GNPTXSTS_NPTXFSAV                0x0000FFFFU            /*!< Nonperiodic TxFIFO space available */
-
-#define USB_OTG_GNPTXSTS_NPTQXSAV                0x00FF0000U            /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0              0x00010000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1              0x00020000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2              0x00040000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3              0x00080000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4              0x00100000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5              0x00200000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6              0x00400000U            /*!<Bit 6 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7              0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_GNPTXSTS_NPTXQTOP                0x7F000000U            /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0              0x01000000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1              0x02000000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2              0x04000000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3              0x08000000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4              0x10000000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5              0x20000000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6              0x40000000U            /*!<Bit 6 */
-
-/********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/
-#define USB_OTG_DTHRCTL_NONISOTHREN             0x00000001U            /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN                0x00000002U            /*!< ISO IN endpoint threshold enable */
-
-#define USB_OTG_DTHRCTL_TXTHRLEN                0x000007FCU            /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0              0x00000004U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1              0x00000008U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2              0x00000010U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3              0x00000020U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4              0x00000040U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5              0x00000080U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6              0x00000100U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7              0x00000200U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8              0x00000400U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_RXTHREN                 0x00010000U            /*!< Receive threshold enable */
-
-#define USB_OTG_DTHRCTL_RXTHRLEN                0x03FE0000U            /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0              0x00020000U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1              0x00040000U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2              0x00080000U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3              0x00100000U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4              0x00200000U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5              0x00400000U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6              0x00800000U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7              0x01000000U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8              0x02000000U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_ARPEN                   0x08000000U            /*!< Arbiter parking enable */
-
-/********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM               0x0000FFFFU            /*!< IN EP Tx FIFO empty interrupt mask bits */
-
-/********************  Bit definition forUSB_OTG_DEACHINT register  ********************/
-#define USB_OTG_DEACHINT_IEP1INT                 0x00000002U            /*!< IN endpoint 1interrupt bit */
-#define USB_OTG_DEACHINT_OEP1INT                 0x00020000U            /*!< OUT endpoint 1 interrupt bit */
-
-/********************  Bit definition forUSB_OTG_GCCFG register  ********************/
-#define USB_OTG_GCCFG_PWRDWN                  0x00010000U            /*!< Power down */
-#define USB_OTG_GCCFG_I2CPADEN                0x00020000U            /*!< Enable I2C bus connection for the external I2C PHY interface */
-#define USB_OTG_GCCFG_VBUSASEN                0x00040000U            /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_VBUSBSEN                0x00080000U            /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_SOFOUTEN                0x00100000U            /*!< SOF output enable */
-#define USB_OTG_GCCFG_NOVBUSSENS              0x00200000U            /*!< VBUS sensing disable option */
-
-/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
-#define USB_OTG_DEACHINTMSK_IEP1INTM                0x00000002U            /*!< IN Endpoint 1 interrupt mask bit */
-#define USB_OTG_DEACHINTMSK_OEP1INTM                0x00020000U            /*!< OUT Endpoint 1 interrupt mask bit */
-
-/********************  Bit definition forUSB_OTG_CID register  ********************/
-#define USB_OTG_CID_PRODUCT_ID              0xFFFFFFFFU            /*!< Product ID field */
-
-/********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/
-#define USB_OTG_DIEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPEACHMSK1_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
-
-/********************  Bit definition forUSB_OTG_HPRT register  ********************/
-#define USB_OTG_HPRT_PCSTS                   0x00000001U            /*!< Port connect status */
-#define USB_OTG_HPRT_PCDET                   0x00000002U            /*!< Port connect detected */
-#define USB_OTG_HPRT_PENA                    0x00000004U            /*!< Port enable */
-#define USB_OTG_HPRT_PENCHNG                 0x00000008U            /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA                    0x00000010U            /*!< Port overcurrent active */
-#define USB_OTG_HPRT_POCCHNG                 0x00000020U            /*!< Port overcurrent change */
-#define USB_OTG_HPRT_PRES                    0x00000040U            /*!< Port resume */
-#define USB_OTG_HPRT_PSUSP                   0x00000080U            /*!< Port suspend */
-#define USB_OTG_HPRT_PRST                    0x00000100U            /*!< Port reset */
-
-#define USB_OTG_HPRT_PLSTS                   0x00000C00U            /*!< Port line status */
-#define USB_OTG_HPRT_PLSTS_0                 0x00000400U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PLSTS_1                 0x00000800U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PPWR                    0x00001000U            /*!< Port power */
-
-#define USB_OTG_HPRT_PTCTL                   0x0001E000U            /*!< Port test control */
-#define USB_OTG_HPRT_PTCTL_0                 0x00002000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PTCTL_1                 0x00004000U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PTCTL_2                 0x00008000U            /*!<Bit 2 */
-#define USB_OTG_HPRT_PTCTL_3                 0x00010000U            /*!<Bit 3 */
-
-#define USB_OTG_HPRT_PSPD                    0x00060000U            /*!< Port speed */
-#define USB_OTG_HPRT_PSPD_0                  0x00020000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PSPD_1                  0x00040000U            /*!<Bit 1 */
-
-/********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/
-#define USB_OTG_DOEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DOEPEACHMSK1_TXFURM                  0x00000100U            /*!< OUT packet error mask */
-#define USB_OTG_DOEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_BERRM                   0x00001000U            /*!< Bubble error interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NYETM                   0x00004000U            /*!< NYET interrupt mask */
-
-/********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/
-#define USB_OTG_HPTXFSIZ_PTXSA                   0x0000FFFFU            /*!< Host periodic TxFIFO start address */
-#define USB_OTG_HPTXFSIZ_PTXFD                   0xFFFF0000U            /*!< Host periodic TxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/
-#define USB_OTG_DIEPCTL_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
-#define USB_OTG_DIEPCTL_USBAEP                  0x00008000U            /*!< USB active endpoint */
-#define USB_OTG_DIEPCTL_EONUM_DPID              0x00010000U            /*!< Even/odd frame */
-#define USB_OTG_DIEPCTL_NAKSTS                  0x00020000U            /*!< NAK status */
-
-#define USB_OTG_DIEPCTL_EPTYP                   0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_DIEPCTL_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_STALL                   0x00200000U            /*!< STALL handshake */
-
-#define USB_OTG_DIEPCTL_TXFNUM                  0x03C00000U            /*!< TxFIFO number */
-#define USB_OTG_DIEPCTL_TXFNUM_0                0x00400000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                0x00800000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                0x01000000U            /*!<Bit 2 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                0x02000000U            /*!<Bit 3 */
-#define USB_OTG_DIEPCTL_CNAK                    0x04000000U            /*!< Clear NAK */
-#define USB_OTG_DIEPCTL_SNAK                    0x08000000U            /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          0x10000000U            /*!< Set DATA0 PID */
-#define USB_OTG_DIEPCTL_SODDFRM                 0x20000000U            /*!< Set odd frame */
-#define USB_OTG_DIEPCTL_EPDIS                   0x40000000U            /*!< Endpoint disable */
-#define USB_OTG_DIEPCTL_EPENA                   0x80000000U            /*!< Endpoint enable */
-
-/********************  Bit definition forUSB_OTG_HCCHAR register  ********************/
-#define USB_OTG_HCCHAR_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
-
-#define USB_OTG_HCCHAR_EPNUM                   0x00007800U            /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPNUM_1                 0x00001000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_EPNUM_2                 0x00002000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_EPNUM_3                 0x00004000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_EPDIR                   0x00008000U            /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV                   0x00020000U            /*!< Low-speed device */
-
-#define USB_OTG_HCCHAR_EPTYP                   0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_MC                      0x00300000U            /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                    0x00100000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_MC_1                    0x00200000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_DAD                     0x1FC00000U            /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                   0x00400000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_DAD_1                   0x00800000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_DAD_2                   0x01000000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_DAD_3                   0x02000000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_DAD_4                   0x04000000U            /*!<Bit 4 */
-#define USB_OTG_HCCHAR_DAD_5                   0x08000000U            /*!<Bit 5 */
-#define USB_OTG_HCCHAR_DAD_6                   0x10000000U            /*!<Bit 6 */
-#define USB_OTG_HCCHAR_ODDFRM                  0x20000000U            /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS                   0x40000000U            /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA                   0x80000000U            /*!< Channel enable */
-
-/********************  Bit definition forUSB_OTG_HCSPLT register  ********************/
-
-#define USB_OTG_HCSPLT_PRTADDR                 0x0000007FU            /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_PRTADDR_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_PRTADDR_2               0x00000004U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_PRTADDR_3               0x00000008U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_PRTADDR_4               0x00000010U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_PRTADDR_5               0x00000020U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_PRTADDR_6               0x00000040U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_HUBADDR                 0x00003F80U            /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0               0x00000080U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_HUBADDR_1               0x00000100U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_HUBADDR_2               0x00000200U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_HUBADDR_3               0x00000400U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_HUBADDR_4               0x00000800U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_HUBADDR_5               0x00001000U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_HUBADDR_6               0x00002000U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_XACTPOS                 0x0000C000U            /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0               0x00004000U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_XACTPOS_1               0x00008000U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_COMPLSPLT               0x00010000U            /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN                 0x80000000U            /*!< Split enable */
-
-/********************  Bit definition forUSB_OTG_HCINT register  ********************/
-#define USB_OTG_HCINT_XFRC                    0x00000001U            /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH                     0x00000002U            /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINT_STALL                   0x00000008U            /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK                     0x00000010U            /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK                     0x00000020U            /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET                    0x00000040U            /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR                   0x00000080U            /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR                   0x00000100U            /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR                   0x00000200U            /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR                   0x00000400U            /*!< Data toggle error */
-
-/********************  Bit definition forUSB_OTG_DIEPINT register  ********************/
-#define USB_OTG_DIEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_TOC                     0x00000008U            /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE                  0x00000010U            /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNE                  0x00000040U            /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE                    0x00000080U            /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN              0x00000100U            /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA                     0x00000200U            /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS               0x00000800U            /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR                    0x00001000U            /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK                     0x00002000U            /*!< NAK interrupt */
-
-/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
-#define USB_OTG_HCINTMSK_XFRCM                   0x00000001U            /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM                    0x00000002U            /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM                  0x00000008U            /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM                    0x00000010U            /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM                    0x00000020U            /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET                    0x00000040U            /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM                  0x00000080U            /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM                  0x00000100U            /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM                  0x00000200U            /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM                  0x00000400U            /*!< Data toggle error mask */
-
-/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
-
-#define USB_OTG_DIEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT                  0x60000000U            /*!< Packet count */
-/********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/
-#define USB_OTG_HCTSIZ_XFRSIZ                    0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT                    0x1FF80000U            /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING                    0x80000000U            /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID                      0x60000000U            /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                    0x20000000U            /*!<Bit 0 */
-#define USB_OTG_HCTSIZ_DPID_1                    0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/
-#define USB_OTG_DIEPDMA_DMAADDR                  0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition forUSB_OTG_HCDMA register  ********************/
-#define USB_OTG_HCDMA_DMAADDR                    0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/
-#define USB_OTG_DTXFSTS_INEPTFSAV                0x0000FFFFU            /*!< IN endpoint TxFIFO space avail */
-
-/********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/
-#define USB_OTG_DIEPTXF_INEPTXSA                 0x0000FFFFU            /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD                 0xFFFF0000U            /*!< IN endpoint TxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/
-
-#define USB_OTG_DOEPCTL_MPSIZ                     0x000007FFU            /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP                    0x00008000U            /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS                    0x00020000U            /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            0x10000000U            /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM                   0x20000000U            /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP                     0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                   0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DOEPCTL_EPTYP_1                   0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_SNPM                      0x00100000U            /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL                     0x00200000U            /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK                      0x04000000U            /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK                      0x08000000U            /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS                     0x40000000U            /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA                     0x80000000U            /*!< Endpoint enable */
-
-/********************  Bit definition forUSB_OTG_DOEPINT register  ********************/
-#define USB_OTG_DOEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_STUP                    0x00000008U            /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS                 0x00000010U            /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_NYET                    0x00004000U            /*!< NYET interrupt */
-
-/********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/
-
-#define USB_OTG_DOEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-
-#define USB_OTG_DOEPTSIZ_STUPCNT                 0x60000000U            /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0               0x20000000U            /*!<Bit 0 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1               0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition for PCGCCTL register  ********************/
-#define USB_OTG_PCGCCTL_STOPCLK                 0x00000001U            /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK                 0x00000002U            /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP                 0x00000010U            /*!<Bit 1 */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
- 
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
- 
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************** DMA Instances *******************************/
-#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
-                                              ((INSTANCE) == DMA1_Stream1) || \
-                                              ((INSTANCE) == DMA1_Stream2) || \
-                                              ((INSTANCE) == DMA1_Stream3) || \
-                                              ((INSTANCE) == DMA1_Stream4) || \
-                                              ((INSTANCE) == DMA1_Stream5) || \
-                                              ((INSTANCE) == DMA1_Stream6) || \
-                                              ((INSTANCE) == DMA1_Stream7) || \
-                                              ((INSTANCE) == DMA2_Stream0) || \
-                                              ((INSTANCE) == DMA2_Stream1) || \
-                                              ((INSTANCE) == DMA2_Stream2) || \
-                                              ((INSTANCE) == DMA2_Stream3) || \
-                                              ((INSTANCE) == DMA2_Stream4) || \
-                                              ((INSTANCE) == DMA2_Stream5) || \
-                                              ((INSTANCE) == DMA2_Stream6) || \
-                                              ((INSTANCE) == DMA2_Stream7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOH))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2) || \
-                                       ((INSTANCE) == I2C3))
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI2) || \
-                                    ((INSTANCE) == SPI3))
-
-/*************************** I2S Extended Instances ***************************/
-#define IS_I2S_ALL_INSTANCE_EXT(PERIPH)  (((INSTANCE) == SPI2)    || \
-                                          ((INSTANCE) == SPI3)    || \
-                                          ((INSTANCE) == I2S2ext) || \
-                                          ((INSTANCE) == I2S3ext))
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3) || \
-                                       ((INSTANCE) == SPI4))
-
-/*************************** SPI Extended Instances ***************************/
-#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1)    || \
-                                           ((INSTANCE) == SPI2)    || \
-                                           ((INSTANCE) == SPI3)    || \
-                                           ((INSTANCE) == I2S2ext) || \
-                                           ((INSTANCE) == I2S3ext))
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
-                                   ((INSTANCE) == TIM2)   || \
-                                   ((INSTANCE) == TIM3)   || \
-                                   ((INSTANCE) == TIM4)   || \
-                                   ((INSTANCE) == TIM5)   || \
-                                   ((INSTANCE) == TIM9)   || \
-                                   ((INSTANCE) == TIM10)  || \
-                                   ((INSTANCE) == TIM11))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
-                                         ((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM9)  || \
-                                         ((INSTANCE) == TIM10) || \
-                                         ((INSTANCE) == TIM11))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM9))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5))
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5))
-
-/******************** TIM Instances : Advanced-control timers *****************/
-#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5))
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5))
-
-/************ TIM Instances : DMA requests generation (COMDE) *****************/
-#define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5)) 
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                             ((INSTANCE) == TIM2) || \
-                                             ((INSTANCE) == TIM3) || \
-                                             ((INSTANCE) == TIM4) || \
-                                             ((INSTANCE) == TIM5))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM9))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM9))
-
-/********************** TIM Instances : 32 bit Counter ************************/
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
-                                              ((INSTANCE) == TIM5))
-
-/***************** TIM Instances : external trigger input availabe ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                        ((INSTANCE) == TIM2) || \
-                                        ((INSTANCE) == TIM3) || \
-                                        ((INSTANCE) == TIM4) || \
-                                        ((INSTANCE) == TIM5))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM11))
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM1) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM5) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-/************ TIM Instances : complementary output(s) available ***************/
-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
-   ((((INSTANCE) == TIM1) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3))))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART6))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART6))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART6))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART6))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART6))     
-
-/*********************** PCD Instances ****************************************/
-#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
-
-/*********************** HCD Instances ****************************************/
-#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/****************************** SDIO Instances ********************************/
-#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
-
-/****************************** USB Exported Constants ************************/
-#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                8U
-#define USB_OTG_FS_MAX_IN_ENDPOINTS                    4U    /* Including EP0 */
-#define USB_OTG_FS_MAX_OUT_ENDPOINTS                   4U    /* Including EP0 */
-#define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32F401xC_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/cmsis/stm32f401xe.h b/stmhal/cmsis/stm32f401xe.h
deleted file mode 100644
index 2e09eb71c0..0000000000
--- a/stmhal/cmsis/stm32f401xe.h
+++ /dev/null
@@ -1,4805 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f401xe.h
-  * @author  MCD Application Team
-  * @version V2.5.1
-  * @date    28-June-2016
-  * @brief   CMSIS STM32F401xExx Device Peripheral Access Layer Header File. 
-  *
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - peripherals registers declarations and bits definition
-  *           - Macros to access peripheral’s registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f401xe
-  * @{
-  */
-    
-#ifndef __STM32F401xE_H
-#define __STM32F401xE_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-  
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-
-/**
-  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
-  */
-#define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */
-#define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */
-#define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1U       /*!< FPU present                                   */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32F4XX Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-typedef enum
-{
-/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
-  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
-/******  STM32 specific Interrupt Numbers **********************************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
-  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
-  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
-  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
-  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
-  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
-  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
-  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
-  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
-  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
-  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
-  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
-  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
-  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */  
-  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
-  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
-  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
-  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
-  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
-  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
-  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
-  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
-  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
-  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
-  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
-  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
-  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
-  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
-  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
-  FPU_IRQn                    = 81,      /*!< FPU global interrupt                                             */
-  SPI4_IRQn                   = 84       /*!< SPI4 global Interrupt                                            */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
-#include "system_stm32f4xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */      
-  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
-  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
-  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
-  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
-  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
-  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
-  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
-  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
-  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
-  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
-  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
-  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
-  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
-  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
-  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
-                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief CRC calculation unit 
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
-  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */
-  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
-  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
-  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
-} CRC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
-  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
-  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
-  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
-  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
-  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
-  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
-  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
-  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
-} DMA_Stream_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
-  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
-  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
-  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
-} DMA_TypeDef;
-
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
-  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
-  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
-  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
-  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
-  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-
-typedef struct
-{
-  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */
-  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */
-  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */
-  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */
-  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */
-  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief General Purpose I/O
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
-  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
-  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
-  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
-  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
-  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
-  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
-  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/** 
-  * @brief System configuration controller
-  */
-  
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */ 
-  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */
-  __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */
-  __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */
-  __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */
-  __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */
-  __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
-  __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
-  __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
-  __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
-  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
-  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
-  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
-  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
-  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
-  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
-  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
-  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
-  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
-  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
-  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
-  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
-  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
-  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
-  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
-  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
-  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
-  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
-  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
-  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
-  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
-  uint32_t      RESERVED7[1];  /*!< Reserved, 0x88                                                                    */
-  __IO uint32_t DCKCFGR;       /*!< RCC DCKCFGR configuration register,                          Address offset: 0x8C */
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-
-typedef struct
-{
-  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
-  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
-  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
-  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
-  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
-  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
-  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */
-  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
-  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */
-  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
-  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */
-  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */
-  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */
-  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */
-  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
-  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */
-  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
-  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
-  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
-  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
-  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
-  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
-  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
-  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
-  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
-  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
-  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
-  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
-  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
-  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
-  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
-  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
-  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
-  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
-  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
-  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
-  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
-} RTC_TypeDef;
-
-
-/** 
-  * @brief SD host Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t POWER;          /*!< SDIO power control register,    Address offset: 0x00 */
-  __IO uint32_t CLKCR;          /*!< SDI clock control register,     Address offset: 0x04 */
-  __IO uint32_t ARG;            /*!< SDIO argument register,         Address offset: 0x08 */
-  __IO uint32_t CMD;            /*!< SDIO command register,          Address offset: 0x0C */
-  __I uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */
-  __I uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */
-  __I uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */
-  __I uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */
-  __I uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */
-  __IO uint32_t DTIMER;         /*!< SDIO data timer register,       Address offset: 0x24 */
-  __IO uint32_t DLEN;           /*!< SDIO data length register,      Address offset: 0x28 */
-  __IO uint32_t DCTRL;          /*!< SDIO data control register,     Address offset: 0x2C */
-  __I uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */
-  __I uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */
-  __IO uint32_t ICR;            /*!< SDIO interrupt clear register,  Address offset: 0x38 */
-  __IO uint32_t MASK;           /*!< SDIO mask register,             Address offset: 0x3C */
-  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
-  __I uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */
-  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
-  __IO uint32_t FIFO;           /*!< SDIO data FIFO register,        Address offset: 0x80 */
-} SDIO_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
-  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
-  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
-  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief __USB_OTG_Core_register
-  */
-typedef struct
-{
-  __IO uint32_t GOTGCTL;              /*!<  USB_OTG Control and Status Register    Address offset : 0x00      */
-  __IO uint32_t GOTGINT;              /*!<  USB_OTG Interrupt Register             Address offset : 0x04      */
-  __IO uint32_t GAHBCFG;              /*!<  Core AHB Configuration Register        Address offset : 0x08      */
-  __IO uint32_t GUSBCFG;              /*!<  Core USB Configuration Register        Address offset : 0x0C      */
-  __IO uint32_t GRSTCTL;              /*!<  Core Reset Register                    Address offset : 0x10      */
-  __IO uint32_t GINTSTS;              /*!<  Core Interrupt Register                Address offset : 0x14      */
-  __IO uint32_t GINTMSK;              /*!<  Core Interrupt Mask Register           Address offset : 0x18      */
-  __IO uint32_t GRXSTSR;              /*!<  Receive Sts Q Read Register            Address offset : 0x1C      */
-  __IO uint32_t GRXSTSP;              /*!<  Receive Sts Q Read & POP Register      Address offset : 0x20      */
-  __IO uint32_t GRXFSIZ;              /* Receive FIFO Size Register                Address offset : 0x24      */
-  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!<  EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28    */
-  __IO uint32_t HNPTXSTS;             /*!<  Non Periodic Tx FIFO/Queue Sts reg     Address offset : 0x2C      */
-  uint32_t Reserved30[2];             /* Reserved                                  Address offset : 0x30      */
-  __IO uint32_t GCCFG;                /*!<  General Purpose IO Register            Address offset : 0x38      */
-  __IO uint32_t CID;                  /*!< User ID Register                          Address offset : 0x3C      */
-  uint32_t  Reserved40[48];           /*!< Reserved                                  Address offset : 0x40-0xFF */
-  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg            Address offset : 0x100 */
-  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */
-}
-USB_OTG_GlobalTypeDef;
-
-
-
-/** 
-  * @brief __device_Registers
-  */
-typedef struct 
-{
-  __IO uint32_t DCFG;         /*!< dev Configuration Register   Address offset : 0x800 */
-  __IO uint32_t DCTL;         /*!< dev Control Register         Address offset : 0x804 */
-  __IO uint32_t DSTS;         /*!< dev Status Register (RO)     Address offset : 0x808 */
-  uint32_t Reserved0C;        /*!< Reserved                     Address offset : 0x80C */
-  __IO uint32_t DIEPMSK;      /* !< dev IN Endpoint Mask        Address offset : 0x810 */
-  __IO uint32_t DOEPMSK;      /*!< dev OUT Endpoint Mask        Address offset : 0x814 */
-  __IO uint32_t DAINT;        /*!< dev All Endpoints Itr Reg    Address offset : 0x818 */
-  __IO uint32_t DAINTMSK;     /*!< dev All Endpoints Itr Mask   Address offset : 0x81C */
-  uint32_t  Reserved20;       /*!< Reserved                     Address offset : 0x820 */
-  uint32_t Reserved9;         /*!< Reserved                     Address offset : 0x824 */
-  __IO uint32_t DVBUSDIS;     /*!< dev VBUS discharge Register  Address offset : 0x828 */
-  __IO uint32_t DVBUSPULSE;   /*!< dev VBUS Pulse Register      Address offset : 0x82C */
-  __IO uint32_t DTHRCTL;      /*!< dev thr                      Address offset : 0x830 */
-  __IO uint32_t DIEPEMPMSK;   /*!< dev empty msk                Address offset : 0x834 */
-  __IO uint32_t DEACHINT;     /*!< dedicated EP interrupt       Address offset : 0x838 */
-  __IO uint32_t DEACHMSK;     /*!< dedicated EP msk             Address offset : 0x83C */  
-  uint32_t Reserved40;        /*!< dedicated EP mask            Address offset : 0x840 */
-  __IO uint32_t DINEP1MSK;    /*!< dedicated EP mask            Address offset : 0x844 */
-  uint32_t  Reserved44[15];   /*!< Reserved                     Address offset : 0x844-0x87C */
-  __IO uint32_t DOUTEP1MSK;   /*!< dedicated EP msk             Address offset : 0x884 */   
-}
-USB_OTG_DeviceTypeDef;
-
-
-/** 
-  * @brief __IN_Endpoint-Specific_Register
-  */
-typedef struct 
-{
-  __IO uint32_t DIEPCTL;        /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h     */
-  uint32_t Reserved04;          /* Reserved                       900h + (ep_num * 20h) + 04h  */
-  __IO uint32_t DIEPINT;        /* dev IN Endpoint Itr Reg     900h + (ep_num * 20h) + 08h     */
-  uint32_t Reserved0C;          /* Reserved                       900h + (ep_num * 20h) + 0Ch  */
-  __IO uint32_t DIEPTSIZ;       /* IN Endpoint Txfer Size   900h + (ep_num * 20h) + 10h        */
-  __IO uint32_t DIEPDMA;        /* IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h  */
-  __IO uint32_t DTXFSTS;        /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h   */
-  uint32_t Reserved18;           /* Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
-}
-USB_OTG_INEndpointTypeDef;
-
-
-/** 
-  * @brief __OUT_Endpoint-Specific_Registers
-  */
-typedef struct 
-{
-  __IO uint32_t DOEPCTL;       /* dev OUT Endpoint Control Reg  B00h + (ep_num * 20h) + 00h*/
-  uint32_t Reserved04;         /* Reserved                      B00h + (ep_num * 20h) + 04h*/
-  __IO uint32_t DOEPINT;       /* dev OUT Endpoint Itr Reg      B00h + (ep_num * 20h) + 08h*/
-  uint32_t Reserved0C;         /* Reserved                      B00h + (ep_num * 20h) + 0Ch*/
-  __IO uint32_t DOEPTSIZ;      /* dev OUT Endpoint Txfer Size   B00h + (ep_num * 20h) + 10h*/
-  __IO uint32_t DOEPDMA;       /* dev OUT Endpoint DMA Address  B00h + (ep_num * 20h) + 14h*/
-  uint32_t Reserved18[2];      /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
-}
-USB_OTG_OUTEndpointTypeDef;
-
-
-/** 
-  * @brief __Host_Mode_Register_Structures
-  */
-typedef struct 
-{
-  __IO uint32_t HCFG;             /* Host Configuration Register    400h*/
-  __IO uint32_t HFIR;             /* Host Frame Interval Register   404h*/
-  __IO uint32_t HFNUM;            /* Host Frame Nbr/Frame Remaining 408h*/
-  uint32_t Reserved40C;           /* Reserved                       40Ch*/
-  __IO uint32_t HPTXSTS;          /* Host Periodic Tx FIFO/ Queue Status 410h*/
-  __IO uint32_t HAINT;            /* Host All Channels Interrupt Register 414h*/
-  __IO uint32_t HAINTMSK;         /* Host All Channels Interrupt Mask 418h*/
-}
-USB_OTG_HostTypeDef;
-
-
-/** 
-  * @brief __Host_Channel_Specific_Registers
-  */
-typedef struct
-{
-  __IO uint32_t HCCHAR;
-  __IO uint32_t HCSPLT;
-  __IO uint32_t HCINT;
-  __IO uint32_t HCINTMSK;
-  __IO uint32_t HCTSIZ;
-  __IO uint32_t HCDMA;
-  uint32_t Reserved[2];
-}
-USB_OTG_HostChannelTypeDef;
-
-/** 
-  * @brief Peripheral_memory_map
-  */
-#define FLASH_BASE            0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region                         */
-#define SRAM1_BASE            0x20000000U /*!< SRAM1(96 KB) base address in the alias region                             */
-#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region                                */
-#define BKPSRAM_BASE          0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region                         */
-#define SRAM1_BB_BASE         0x22000000U /*!< SRAM1(96 KB) base address in the bit-band region                          */
-#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region                             */
-#define BKPSRAM_BB_BASE       0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region                      */
-#define FLASH_END             0x0807FFFFU /*!< FLASH end address */
-
-/* Legacy defines */
-#define SRAM_BASE             SRAM1_BASE
-#define SRAM_BB_BASE          SRAM1_BB_BASE
-
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000U)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)
-#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400U)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)
-#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000U)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)
-#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)
-
-/*!< APB2 peripherals */
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000U)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x1000U)
-#define USART6_BASE           (APB2PERIPH_BASE + 0x1400U)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000U)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x2300U)
-#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00U)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)
-#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400U)
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800U)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00U)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000U)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400U)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800U)
-
-/*!< AHB1 peripherals */
-#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000U)
-#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400U)
-#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800U)
-#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00U)
-#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000U)
-#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00U)
-#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)
-#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800U)
-#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00U)
-#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000U)
-#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010U)
-#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028U)
-#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040U)
-#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058U)
-#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070U)
-#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088U)
-#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0U)
-#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8U)
-#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400U)
-#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010U)
-#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028U)
-#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040U)
-#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058U)
-#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070U)
-#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088U)
-#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0U)
-#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)
-
-/* Debug MCU registers base address */
-#define DBGMCU_BASE           0xE0042000U
-
-/*!< USB registers base address */
-#define USB_OTG_FS_PERIPH_BASE               0x50000000U
-
-#define USB_OTG_GLOBAL_BASE                  0x000U
-#define USB_OTG_DEVICE_BASE                  0x800U
-#define USB_OTG_IN_ENDPOINT_BASE             0x900U
-#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U
-#define USB_OTG_EP_REG_SIZE                  0x20U
-#define USB_OTG_HOST_BASE                    0x400U
-#define USB_OTG_HOST_PORT_BASE               0x440U
-#define USB_OTG_HOST_CHANNEL_BASE            0x500U
-#define USB_OTG_HOST_CHANNEL_SIZE            0x20U
-#define USB_OTG_PCGCCTL_BASE                 0xE00U
-#define USB_OTG_FIFO_BASE                    0x1000U
-#define USB_OTG_FIFO_SIZE                    0x1000U
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define USART6              ((USART_TypeDef *) USART6_BASE)
-#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define SPI4                ((SPI_TypeDef *) SPI4_BASE) 
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
-#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
-#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
-#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
-#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
-#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
-#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
-#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
-#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
-#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
-#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
-#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
-#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
-#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
-#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
-
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers_Bits_Definition               */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Analog to Digital Converter                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          0x00000001U       /*!<Analog watchdog flag */
-#define  ADC_SR_EOC                          0x00000002U       /*!<End of conversion */
-#define  ADC_SR_JEOC                         0x00000004U       /*!<Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        0x00000008U       /*!<Injected channel Start flag */
-#define  ADC_SR_STRT                         0x00000010U       /*!<Regular channel Start flag */
-#define  ADC_SR_OVR                          0x00000020U       /*!<Overrun flag */
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
-#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels */
-#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels */
-#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution) */
-#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
-  
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion */
-#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode */
-#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC) */
-#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection */
-#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment */
-#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      0xFFFFU            /*!<Injected data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag */
-#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion */
-#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag */
-#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag */
-#define  ADC_CSR_OVR1                        0x00000020U        /*!<ADC1 DMA overrun  flag */
-#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag */
-#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion */
-#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag */
-#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag */
-#define  ADC_CSR_OVR2                        0x00002000U        /*!<ADC2 DMA overrun  flag */
-#define  ADC_CSR_AWD3                        0x00010000U        /*!<ADC3 Analog watchdog flag */
-#define  ADC_CSR_EOC3                        0x00020000U        /*!<ADC3 End of conversion */
-#define  ADC_CSR_JEOC3                       0x00040000U        /*!<ADC3 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT3                      0x00080000U        /*!<ADC3 Injected channel Start flag */
-#define  ADC_CSR_STRT3                       0x00100000U        /*!<ADC3 Regular channel Start flag */
-#define  ADC_CSR_OVR3                        0x00200000U        /*!<ADC3 DMA overrun  flag */
-
-/* Legacy defines */
-#define  ADC_CSR_DOVR1                        ADC_CSR_OVR1
-#define  ADC_CSR_DOVR2                        ADC_CSR_OVR2
-#define  ADC_CSR_DOVR3                        ADC_CSR_OVR3
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
-#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
-#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
-#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
-#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
-
-/*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                      0x0000FFFFU         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                      0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRC calculation unit                              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           0xFFFFFFFFU /*!< Data register bits */
-
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         0xFFU        /*!< General-purpose 8-bit data register bits */
-
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        0x01U        /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 Debug MCU                                  */
-/*                                                                            */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                             DMA Controller                                 */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DMA_SxCR register  *****************/
-#define DMA_SxCR_CHSEL                       0x0E000000U
-#define DMA_SxCR_CHSEL_0                     0x02000000U
-#define DMA_SxCR_CHSEL_1                     0x04000000U
-#define DMA_SxCR_CHSEL_2                     0x08000000U
-#define DMA_SxCR_MBURST                      0x01800000U
-#define DMA_SxCR_MBURST_0                    0x00800000U
-#define DMA_SxCR_MBURST_1                    0x01000000U
-#define DMA_SxCR_PBURST                      0x00600000U
-#define DMA_SxCR_PBURST_0                    0x00200000U
-#define DMA_SxCR_PBURST_1                    0x00400000U
-#define DMA_SxCR_CT                          0x00080000U
-#define DMA_SxCR_DBM                         0x00040000U
-#define DMA_SxCR_PL                          0x00030000U
-#define DMA_SxCR_PL_0                        0x00010000U
-#define DMA_SxCR_PL_1                        0x00020000U
-#define DMA_SxCR_PINCOS                      0x00008000U
-#define DMA_SxCR_MSIZE                       0x00006000U
-#define DMA_SxCR_MSIZE_0                     0x00002000U
-#define DMA_SxCR_MSIZE_1                     0x00004000U
-#define DMA_SxCR_PSIZE                       0x00001800U
-#define DMA_SxCR_PSIZE_0                     0x00000800U
-#define DMA_SxCR_PSIZE_1                     0x00001000U
-#define DMA_SxCR_MINC                        0x00000400U
-#define DMA_SxCR_PINC                        0x00000200U
-#define DMA_SxCR_CIRC                        0x00000100U
-#define DMA_SxCR_DIR                         0x000000C0U
-#define DMA_SxCR_DIR_0                       0x00000040U
-#define DMA_SxCR_DIR_1                       0x00000080U
-#define DMA_SxCR_PFCTRL                      0x00000020U
-#define DMA_SxCR_TCIE                        0x00000010U
-#define DMA_SxCR_HTIE                        0x00000008U
-#define DMA_SxCR_TEIE                        0x00000004U
-#define DMA_SxCR_DMEIE                       0x00000002U
-#define DMA_SxCR_EN                          0x00000001U
-
-/* Legacy defines */
-#define DMA_SxCR_ACK                         0x00100000U
-
-/********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            0x0000FFFFU
-#define DMA_SxNDT_0                          0x00000001U
-#define DMA_SxNDT_1                          0x00000002U
-#define DMA_SxNDT_2                          0x00000004U
-#define DMA_SxNDT_3                          0x00000008U
-#define DMA_SxNDT_4                          0x00000010U
-#define DMA_SxNDT_5                          0x00000020U
-#define DMA_SxNDT_6                          0x00000040U
-#define DMA_SxNDT_7                          0x00000080U
-#define DMA_SxNDT_8                          0x00000100U
-#define DMA_SxNDT_9                          0x00000200U
-#define DMA_SxNDT_10                         0x00000400U
-#define DMA_SxNDT_11                         0x00000800U
-#define DMA_SxNDT_12                         0x00001000U
-#define DMA_SxNDT_13                         0x00002000U
-#define DMA_SxNDT_14                         0x00004000U
-#define DMA_SxNDT_15                         0x00008000U
-
-/********************  Bits definition for DMA_SxFCR register  ****************/ 
-#define DMA_SxFCR_FEIE                       0x00000080U
-#define DMA_SxFCR_FS                         0x00000038U
-#define DMA_SxFCR_FS_0                       0x00000008U
-#define DMA_SxFCR_FS_1                       0x00000010U
-#define DMA_SxFCR_FS_2                       0x00000020U
-#define DMA_SxFCR_DMDIS                      0x00000004U
-#define DMA_SxFCR_FTH                        0x00000003U
-#define DMA_SxFCR_FTH_0                      0x00000001U
-#define DMA_SxFCR_FTH_1                      0x00000002U
-
-/********************  Bits definition for DMA_LISR register  *****************/ 
-#define DMA_LISR_TCIF3                       0x08000000U
-#define DMA_LISR_HTIF3                       0x04000000U
-#define DMA_LISR_TEIF3                       0x02000000U
-#define DMA_LISR_DMEIF3                      0x01000000U
-#define DMA_LISR_FEIF3                       0x00400000U
-#define DMA_LISR_TCIF2                       0x00200000U
-#define DMA_LISR_HTIF2                       0x00100000U
-#define DMA_LISR_TEIF2                       0x00080000U
-#define DMA_LISR_DMEIF2                      0x00040000U
-#define DMA_LISR_FEIF2                       0x00010000U
-#define DMA_LISR_TCIF1                       0x00000800U
-#define DMA_LISR_HTIF1                       0x00000400U
-#define DMA_LISR_TEIF1                       0x00000200U
-#define DMA_LISR_DMEIF1                      0x00000100U
-#define DMA_LISR_FEIF1                       0x00000040U
-#define DMA_LISR_TCIF0                       0x00000020U
-#define DMA_LISR_HTIF0                       0x00000010U
-#define DMA_LISR_TEIF0                       0x00000008U
-#define DMA_LISR_DMEIF0                      0x00000004U
-#define DMA_LISR_FEIF0                       0x00000001U
-
-/********************  Bits definition for DMA_HISR register  *****************/ 
-#define DMA_HISR_TCIF7                       0x08000000U
-#define DMA_HISR_HTIF7                       0x04000000U
-#define DMA_HISR_TEIF7                       0x02000000U
-#define DMA_HISR_DMEIF7                      0x01000000U
-#define DMA_HISR_FEIF7                       0x00400000U
-#define DMA_HISR_TCIF6                       0x00200000U
-#define DMA_HISR_HTIF6                       0x00100000U
-#define DMA_HISR_TEIF6                       0x00080000U
-#define DMA_HISR_DMEIF6                      0x00040000U
-#define DMA_HISR_FEIF6                       0x00010000U
-#define DMA_HISR_TCIF5                       0x00000800U
-#define DMA_HISR_HTIF5                       0x00000400U
-#define DMA_HISR_TEIF5                       0x00000200U
-#define DMA_HISR_DMEIF5                      0x00000100U
-#define DMA_HISR_FEIF5                       0x00000040U
-#define DMA_HISR_TCIF4                       0x00000020U
-#define DMA_HISR_HTIF4                       0x00000010U
-#define DMA_HISR_TEIF4                       0x00000008U
-#define DMA_HISR_DMEIF4                      0x00000004U
-#define DMA_HISR_FEIF4                       0x00000001U
-
-/********************  Bits definition for DMA_LIFCR register  ****************/ 
-#define DMA_LIFCR_CTCIF3                     0x08000000U
-#define DMA_LIFCR_CHTIF3                     0x04000000U
-#define DMA_LIFCR_CTEIF3                     0x02000000U
-#define DMA_LIFCR_CDMEIF3                    0x01000000U
-#define DMA_LIFCR_CFEIF3                     0x00400000U
-#define DMA_LIFCR_CTCIF2                     0x00200000U
-#define DMA_LIFCR_CHTIF2                     0x00100000U
-#define DMA_LIFCR_CTEIF2                     0x00080000U
-#define DMA_LIFCR_CDMEIF2                    0x00040000U
-#define DMA_LIFCR_CFEIF2                     0x00010000U
-#define DMA_LIFCR_CTCIF1                     0x00000800U
-#define DMA_LIFCR_CHTIF1                     0x00000400U
-#define DMA_LIFCR_CTEIF1                     0x00000200U
-#define DMA_LIFCR_CDMEIF1                    0x00000100U
-#define DMA_LIFCR_CFEIF1                     0x00000040U
-#define DMA_LIFCR_CTCIF0                     0x00000020U
-#define DMA_LIFCR_CHTIF0                     0x00000010U
-#define DMA_LIFCR_CTEIF0                     0x00000008U
-#define DMA_LIFCR_CDMEIF0                    0x00000004U
-#define DMA_LIFCR_CFEIF0                     0x00000001U
-
-/********************  Bits definition for DMA_HIFCR  register  ****************/ 
-#define DMA_HIFCR_CTCIF7                     0x08000000U
-#define DMA_HIFCR_CHTIF7                     0x04000000U
-#define DMA_HIFCR_CTEIF7                     0x02000000U
-#define DMA_HIFCR_CDMEIF7                    0x01000000U
-#define DMA_HIFCR_CFEIF7                     0x00400000U
-#define DMA_HIFCR_CTCIF6                     0x00200000U
-#define DMA_HIFCR_CHTIF6                     0x00100000U
-#define DMA_HIFCR_CTEIF6                     0x00080000U
-#define DMA_HIFCR_CDMEIF6                    0x00040000U
-#define DMA_HIFCR_CFEIF6                     0x00010000U
-#define DMA_HIFCR_CTCIF5                     0x00000800U
-#define DMA_HIFCR_CHTIF5                     0x00000400U
-#define DMA_HIFCR_CTEIF5                     0x00000200U
-#define DMA_HIFCR_CDMEIF5                    0x00000100U
-#define DMA_HIFCR_CFEIF5                     0x00000040U
-#define DMA_HIFCR_CTCIF4                     0x00000020U
-#define DMA_HIFCR_CHTIF4                     0x00000010U
-#define DMA_HIFCR_CTEIF4                     0x00000008U
-#define DMA_HIFCR_CDMEIF4                    0x00000004U
-#define DMA_HIFCR_CFEIF4                     0x00000001U
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                    External Interrupt/Event Controller                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    FLASH                                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    0x0000000FU
-#define FLASH_ACR_LATENCY_0WS                0x00000000U
-#define FLASH_ACR_LATENCY_1WS                0x00000001U
-#define FLASH_ACR_LATENCY_2WS                0x00000002U
-#define FLASH_ACR_LATENCY_3WS                0x00000003U
-#define FLASH_ACR_LATENCY_4WS                0x00000004U
-#define FLASH_ACR_LATENCY_5WS                0x00000005U
-#define FLASH_ACR_LATENCY_6WS                0x00000006U
-#define FLASH_ACR_LATENCY_7WS                0x00000007U
-
-#define FLASH_ACR_PRFTEN                     0x00000100U
-#define FLASH_ACR_ICEN                       0x00000200U
-#define FLASH_ACR_DCEN                       0x00000400U
-#define FLASH_ACR_ICRST                      0x00000800U
-#define FLASH_ACR_DCRST                      0x00001000U
-#define FLASH_ACR_BYTE0_ADDRESS              0x40023C00U
-#define FLASH_ACR_BYTE2_ADDRESS              0x40023C03U
-
-/*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         0x00000001U
-#define FLASH_SR_SOP                         0x00000002U
-#define FLASH_SR_WRPERR                      0x00000010U
-#define FLASH_SR_PGAERR                      0x00000020U
-#define FLASH_SR_PGPERR                      0x00000040U
-#define FLASH_SR_PGSERR                      0x00000080U
-#define FLASH_SR_BSY                         0x00010000U
-
-/*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          0x00000001U
-#define FLASH_CR_SER                         0x00000002U
-#define FLASH_CR_MER                         0x00000004U
-#define FLASH_CR_SNB                         0x000000F8U
-#define FLASH_CR_SNB_0                       0x00000008U
-#define FLASH_CR_SNB_1                       0x00000010U
-#define FLASH_CR_SNB_2                       0x00000020U
-#define FLASH_CR_SNB_3                       0x00000040U
-#define FLASH_CR_SNB_4                       0x00000080U
-#define FLASH_CR_PSIZE                       0x00000300U
-#define FLASH_CR_PSIZE_0                     0x00000100U
-#define FLASH_CR_PSIZE_1                     0x00000200U
-#define FLASH_CR_STRT                        0x00010000U
-#define FLASH_CR_EOPIE                       0x01000000U
-#define FLASH_CR_LOCK                        0x80000000U
-
-/*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                 0x00000001U
-#define FLASH_OPTCR_OPTSTRT                 0x00000002U
-#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
-#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
-#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
-
-#define FLASH_OPTCR_WDG_SW                  0x00000020U
-#define FLASH_OPTCR_nRST_STOP               0x00000040U
-#define FLASH_OPTCR_nRST_STDBY              0x00000080U
-#define FLASH_OPTCR_RDP                     0x0000FF00U
-#define FLASH_OPTCR_RDP_0                   0x00000100U
-#define FLASH_OPTCR_RDP_1                   0x00000200U
-#define FLASH_OPTCR_RDP_2                   0x00000400U
-#define FLASH_OPTCR_RDP_3                   0x00000800U
-#define FLASH_OPTCR_RDP_4                   0x00001000U
-#define FLASH_OPTCR_RDP_5                   0x00002000U
-#define FLASH_OPTCR_RDP_6                   0x00004000U
-#define FLASH_OPTCR_RDP_7                   0x00008000U
-#define FLASH_OPTCR_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR_nWRP_0                  0x00010000U
-#define FLASH_OPTCR_nWRP_1                  0x00020000U
-#define FLASH_OPTCR_nWRP_2                  0x00040000U
-#define FLASH_OPTCR_nWRP_3                  0x00080000U
-#define FLASH_OPTCR_nWRP_4                  0x00100000U
-#define FLASH_OPTCR_nWRP_5                  0x00200000U
-#define FLASH_OPTCR_nWRP_6                  0x00400000U
-#define FLASH_OPTCR_nWRP_7                  0x00800000U
-#define FLASH_OPTCR_nWRP_8                  0x01000000U
-#define FLASH_OPTCR_nWRP_9                  0x02000000U
-#define FLASH_OPTCR_nWRP_10                 0x04000000U
-#define FLASH_OPTCR_nWRP_11                 0x08000000U
-                                             
-/******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR1_nWRP_0                  0x00010000U
-#define FLASH_OPTCR1_nWRP_1                  0x00020000U
-#define FLASH_OPTCR1_nWRP_2                  0x00040000U
-#define FLASH_OPTCR1_nWRP_3                  0x00080000U
-#define FLASH_OPTCR1_nWRP_4                  0x00100000U
-#define FLASH_OPTCR1_nWRP_5                  0x00200000U
-#define FLASH_OPTCR1_nWRP_6                  0x00400000U
-#define FLASH_OPTCR1_nWRP_7                  0x00800000U
-#define FLASH_OPTCR1_nWRP_8                  0x01000000U
-#define FLASH_OPTCR1_nWRP_9                  0x02000000U
-#define FLASH_OPTCR1_nWRP_10                 0x04000000U
-#define FLASH_OPTCR1_nWRP_11                 0x08000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    0x00000003U
-#define GPIO_MODER_MODER0_0                  0x00000001U
-#define GPIO_MODER_MODER0_1                  0x00000002U
-
-#define GPIO_MODER_MODER1                    0x0000000CU
-#define GPIO_MODER_MODER1_0                  0x00000004U
-#define GPIO_MODER_MODER1_1                  0x00000008U
-
-#define GPIO_MODER_MODER2                    0x00000030U
-#define GPIO_MODER_MODER2_0                  0x00000010U
-#define GPIO_MODER_MODER2_1                  0x00000020U
-
-#define GPIO_MODER_MODER3                    0x000000C0U
-#define GPIO_MODER_MODER3_0                  0x00000040U
-#define GPIO_MODER_MODER3_1                  0x00000080U
-
-#define GPIO_MODER_MODER4                    0x00000300U
-#define GPIO_MODER_MODER4_0                  0x00000100U
-#define GPIO_MODER_MODER4_1                  0x00000200U
-
-#define GPIO_MODER_MODER5                    0x00000C00U
-#define GPIO_MODER_MODER5_0                  0x00000400U
-#define GPIO_MODER_MODER5_1                  0x00000800U
-
-#define GPIO_MODER_MODER6                    0x00003000U
-#define GPIO_MODER_MODER6_0                  0x00001000U
-#define GPIO_MODER_MODER6_1                  0x00002000U
-
-#define GPIO_MODER_MODER7                    0x0000C000U
-#define GPIO_MODER_MODER7_0                  0x00004000U
-#define GPIO_MODER_MODER7_1                  0x00008000U
-
-#define GPIO_MODER_MODER8                    0x00030000U
-#define GPIO_MODER_MODER8_0                  0x00010000U
-#define GPIO_MODER_MODER8_1                  0x00020000U
-
-#define GPIO_MODER_MODER9                    0x000C0000U
-#define GPIO_MODER_MODER9_0                  0x00040000U
-#define GPIO_MODER_MODER9_1                  0x00080000U
-
-#define GPIO_MODER_MODER10                   0x00300000U
-#define GPIO_MODER_MODER10_0                 0x00100000U
-#define GPIO_MODER_MODER10_1                 0x00200000U
-
-#define GPIO_MODER_MODER11                   0x00C00000U
-#define GPIO_MODER_MODER11_0                 0x00400000U
-#define GPIO_MODER_MODER11_1                 0x00800000U
-
-#define GPIO_MODER_MODER12                   0x03000000U
-#define GPIO_MODER_MODER12_0                 0x01000000U
-#define GPIO_MODER_MODER12_1                 0x02000000U
-
-#define GPIO_MODER_MODER13                   0x0C000000U
-#define GPIO_MODER_MODER13_0                 0x04000000U
-#define GPIO_MODER_MODER13_1                 0x08000000U
-
-#define GPIO_MODER_MODER14                   0x30000000U
-#define GPIO_MODER_MODER14_0                 0x10000000U
-#define GPIO_MODER_MODER14_1                 0x20000000U
-
-#define GPIO_MODER_MODER15                   0xC0000000U
-#define GPIO_MODER_MODER15_0                 0x40000000U
-#define GPIO_MODER_MODER15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     0x00000001U
-#define GPIO_OTYPER_OT_1                     0x00000002U
-#define GPIO_OTYPER_OT_2                     0x00000004U
-#define GPIO_OTYPER_OT_3                     0x00000008U
-#define GPIO_OTYPER_OT_4                     0x00000010U
-#define GPIO_OTYPER_OT_5                     0x00000020U
-#define GPIO_OTYPER_OT_6                     0x00000040U
-#define GPIO_OTYPER_OT_7                     0x00000080U
-#define GPIO_OTYPER_OT_8                     0x00000100U
-#define GPIO_OTYPER_OT_9                     0x00000200U
-#define GPIO_OTYPER_OT_10                    0x00000400U
-#define GPIO_OTYPER_OT_11                    0x00000800U
-#define GPIO_OTYPER_OT_12                    0x00001000U
-#define GPIO_OTYPER_OT_13                    0x00002000U
-#define GPIO_OTYPER_OT_14                    0x00004000U
-#define GPIO_OTYPER_OT_15                    0x00008000U
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
-#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
-#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
-
-#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
-#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
-#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
-
-#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
-#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
-#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
-
-#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
-#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
-#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
-
-#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
-#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
-#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
-
-#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
-#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
-#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
-
-#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
-#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
-#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
-
-#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
-#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
-#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
-
-#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
-#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
-#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
-
-#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
-#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
-#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
-
-#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
-#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
-#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
-
-#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
-#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
-#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
-
-#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
-#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
-#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
-
-#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
-#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
-#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
-
-#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
-#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
-#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
-
-#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
-#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
-#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    0x00000003U
-#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
-#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
-
-#define GPIO_PUPDR_PUPDR1                    0x0000000CU
-#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
-#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
-
-#define GPIO_PUPDR_PUPDR2                    0x00000030U
-#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
-#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
-
-#define GPIO_PUPDR_PUPDR3                    0x000000C0U
-#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
-#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
-
-#define GPIO_PUPDR_PUPDR4                    0x00000300U
-#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
-#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
-
-#define GPIO_PUPDR_PUPDR5                    0x00000C00U
-#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
-#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
-
-#define GPIO_PUPDR_PUPDR6                    0x00003000U
-#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
-#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
-
-#define GPIO_PUPDR_PUPDR7                    0x0000C000U
-#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
-#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
-
-#define GPIO_PUPDR_PUPDR8                    0x00030000U
-#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
-#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
-
-#define GPIO_PUPDR_PUPDR9                    0x000C0000U
-#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
-#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
-
-#define GPIO_PUPDR_PUPDR10                   0x00300000U
-#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
-#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
-
-#define GPIO_PUPDR_PUPDR11                   0x00C00000U
-#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
-#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
-
-#define GPIO_PUPDR_PUPDR12                   0x03000000U
-#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
-#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
-
-#define GPIO_PUPDR_PUPDR13                   0x0C000000U
-#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
-#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
-
-#define GPIO_PUPDR_PUPDR14                   0x30000000U
-#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
-#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
-
-#define GPIO_PUPDR_PUPDR15                   0xC0000000U
-#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
-#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       0x00000001U
-#define GPIO_IDR_IDR_1                       0x00000002U
-#define GPIO_IDR_IDR_2                       0x00000004U
-#define GPIO_IDR_IDR_3                       0x00000008U
-#define GPIO_IDR_IDR_4                       0x00000010U
-#define GPIO_IDR_IDR_5                       0x00000020U
-#define GPIO_IDR_IDR_6                       0x00000040U
-#define GPIO_IDR_IDR_7                       0x00000080U
-#define GPIO_IDR_IDR_8                       0x00000100U
-#define GPIO_IDR_IDR_9                       0x00000200U
-#define GPIO_IDR_IDR_10                      0x00000400U
-#define GPIO_IDR_IDR_11                      0x00000800U
-#define GPIO_IDR_IDR_12                      0x00001000U
-#define GPIO_IDR_IDR_13                      0x00002000U
-#define GPIO_IDR_IDR_14                      0x00004000U
-#define GPIO_IDR_IDR_15                      0x00008000U
-/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
-#define GPIO_OTYPER_IDR_0                    GPIO_IDR_IDR_0
-#define GPIO_OTYPER_IDR_1                    GPIO_IDR_IDR_1
-#define GPIO_OTYPER_IDR_2                    GPIO_IDR_IDR_2
-#define GPIO_OTYPER_IDR_3                    GPIO_IDR_IDR_3
-#define GPIO_OTYPER_IDR_4                    GPIO_IDR_IDR_4
-#define GPIO_OTYPER_IDR_5                    GPIO_IDR_IDR_5
-#define GPIO_OTYPER_IDR_6                    GPIO_IDR_IDR_6
-#define GPIO_OTYPER_IDR_7                    GPIO_IDR_IDR_7
-#define GPIO_OTYPER_IDR_8                    GPIO_IDR_IDR_8
-#define GPIO_OTYPER_IDR_9                    GPIO_IDR_IDR_9
-#define GPIO_OTYPER_IDR_10                   GPIO_IDR_IDR_10
-#define GPIO_OTYPER_IDR_11                   GPIO_IDR_IDR_11
-#define GPIO_OTYPER_IDR_12                   GPIO_IDR_IDR_12
-#define GPIO_OTYPER_IDR_13                   GPIO_IDR_IDR_13
-#define GPIO_OTYPER_IDR_14                   GPIO_IDR_IDR_14
-#define GPIO_OTYPER_IDR_15                   GPIO_IDR_IDR_15
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       0x00000001U
-#define GPIO_ODR_ODR_1                       0x00000002U
-#define GPIO_ODR_ODR_2                       0x00000004U
-#define GPIO_ODR_ODR_3                       0x00000008U
-#define GPIO_ODR_ODR_4                       0x00000010U
-#define GPIO_ODR_ODR_5                       0x00000020U
-#define GPIO_ODR_ODR_6                       0x00000040U
-#define GPIO_ODR_ODR_7                       0x00000080U
-#define GPIO_ODR_ODR_8                       0x00000100U
-#define GPIO_ODR_ODR_9                       0x00000200U
-#define GPIO_ODR_ODR_10                      0x00000400U
-#define GPIO_ODR_ODR_11                      0x00000800U
-#define GPIO_ODR_ODR_12                      0x00001000U
-#define GPIO_ODR_ODR_13                      0x00002000U
-#define GPIO_ODR_ODR_14                      0x00004000U
-#define GPIO_ODR_ODR_15                      0x00008000U
-/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
-#define GPIO_OTYPER_ODR_0                    GPIO_ODR_ODR_0
-#define GPIO_OTYPER_ODR_1                    GPIO_ODR_ODR_1
-#define GPIO_OTYPER_ODR_2                    GPIO_ODR_ODR_2
-#define GPIO_OTYPER_ODR_3                    GPIO_ODR_ODR_3
-#define GPIO_OTYPER_ODR_4                    GPIO_ODR_ODR_4
-#define GPIO_OTYPER_ODR_5                    GPIO_ODR_ODR_5
-#define GPIO_OTYPER_ODR_6                    GPIO_ODR_ODR_6
-#define GPIO_OTYPER_ODR_7                    GPIO_ODR_ODR_7
-#define GPIO_OTYPER_ODR_8                    GPIO_ODR_ODR_8
-#define GPIO_OTYPER_ODR_9                    GPIO_ODR_ODR_9
-#define GPIO_OTYPER_ODR_10                   GPIO_ODR_ODR_10
-#define GPIO_OTYPER_ODR_11                   GPIO_ODR_ODR_11
-#define GPIO_OTYPER_ODR_12                   GPIO_ODR_ODR_12
-#define GPIO_OTYPER_ODR_13                   GPIO_ODR_ODR_13
-#define GPIO_OTYPER_ODR_14                   GPIO_ODR_ODR_14
-#define GPIO_OTYPER_ODR_15                   GPIO_ODR_ODR_15
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       0x00000001U
-#define GPIO_BSRR_BS_1                       0x00000002U
-#define GPIO_BSRR_BS_2                       0x00000004U
-#define GPIO_BSRR_BS_3                       0x00000008U
-#define GPIO_BSRR_BS_4                       0x00000010U
-#define GPIO_BSRR_BS_5                       0x00000020U
-#define GPIO_BSRR_BS_6                       0x00000040U
-#define GPIO_BSRR_BS_7                       0x00000080U
-#define GPIO_BSRR_BS_8                       0x00000100U
-#define GPIO_BSRR_BS_9                       0x00000200U
-#define GPIO_BSRR_BS_10                      0x00000400U
-#define GPIO_BSRR_BS_11                      0x00000800U
-#define GPIO_BSRR_BS_12                      0x00001000U
-#define GPIO_BSRR_BS_13                      0x00002000U
-#define GPIO_BSRR_BS_14                      0x00004000U
-#define GPIO_BSRR_BS_15                      0x00008000U
-#define GPIO_BSRR_BR_0                       0x00010000U
-#define GPIO_BSRR_BR_1                       0x00020000U
-#define GPIO_BSRR_BR_2                       0x00040000U
-#define GPIO_BSRR_BR_3                       0x00080000U
-#define GPIO_BSRR_BR_4                       0x00100000U
-#define GPIO_BSRR_BR_5                       0x00200000U
-#define GPIO_BSRR_BR_6                       0x00400000U
-#define GPIO_BSRR_BR_7                       0x00800000U
-#define GPIO_BSRR_BR_8                       0x01000000U
-#define GPIO_BSRR_BR_9                       0x02000000U
-#define GPIO_BSRR_BR_10                      0x04000000U
-#define GPIO_BSRR_BR_11                      0x08000000U
-#define GPIO_BSRR_BR_12                      0x10000000U
-#define GPIO_BSRR_BR_13                      0x20000000U
-#define GPIO_BSRR_BR_14                      0x40000000U
-#define GPIO_BSRR_BR_15                      0x80000000U
-
-/****************** Bit definition for GPIO_LCKR register ********************/
-#define GPIO_LCKR_LCK0                       0x00000001U
-#define GPIO_LCKR_LCK1                       0x00000002U
-#define GPIO_LCKR_LCK2                       0x00000004U
-#define GPIO_LCKR_LCK3                       0x00000008U
-#define GPIO_LCKR_LCK4                       0x00000010U
-#define GPIO_LCKR_LCK5                       0x00000020U
-#define GPIO_LCKR_LCK6                       0x00000040U
-#define GPIO_LCKR_LCK7                       0x00000080U
-#define GPIO_LCKR_LCK8                       0x00000100U
-#define GPIO_LCKR_LCK9                       0x00000200U
-#define GPIO_LCKR_LCK10                      0x00000400U
-#define GPIO_LCKR_LCK11                      0x00000800U
-#define GPIO_LCKR_LCK12                      0x00001000U
-#define GPIO_LCKR_LCK13                      0x00002000U
-#define GPIO_LCKR_LCK14                      0x00004000U
-#define GPIO_LCKR_LCK15                      0x00008000U
-#define GPIO_LCKR_LCKK                       0x00010000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Inter-integrated Circuit Interface                    */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          0x00000001U     /*!<Peripheral Enable                             */
-#define  I2C_CR1_SMBUS                       0x00000002U     /*!<SMBus Mode                                    */
-#define  I2C_CR1_SMBTYPE                     0x00000008U     /*!<SMBus Type                                    */
-#define  I2C_CR1_ENARP                       0x00000010U     /*!<ARP Enable                                    */
-#define  I2C_CR1_ENPEC                       0x00000020U     /*!<PEC Enable                                    */
-#define  I2C_CR1_ENGC                        0x00000040U     /*!<General Call Enable                           */
-#define  I2C_CR1_NOSTRETCH                   0x00000080U     /*!<Clock Stretching Disable (Slave mode)  */
-#define  I2C_CR1_START                       0x00000100U     /*!<Start Generation                              */
-#define  I2C_CR1_STOP                        0x00000200U     /*!<Stop Generation                               */
-#define  I2C_CR1_ACK                         0x00000400U     /*!<Acknowledge Enable                            */
-#define  I2C_CR1_POS                         0x00000800U     /*!<Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         0x00001000U     /*!<Packet Error Checking                         */
-#define  I2C_CR1_ALERT                       0x00002000U     /*!<SMBus Alert                                   */
-#define  I2C_CR1_SWRST                       0x00008000U     /*!<Software Reset                                */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        0x0000003FU     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
-#define  I2C_CR2_FREQ_0                      0x00000001U     /*!<Bit 0 */
-#define  I2C_CR2_FREQ_1                      0x00000002U     /*!<Bit 1 */
-#define  I2C_CR2_FREQ_2                      0x00000004U     /*!<Bit 2 */
-#define  I2C_CR2_FREQ_3                      0x00000008U     /*!<Bit 3 */
-#define  I2C_CR2_FREQ_4                      0x00000010U     /*!<Bit 4 */
-#define  I2C_CR2_FREQ_5                      0x00000020U     /*!<Bit 5 */
-
-#define  I2C_CR2_ITERREN                     0x00000100U     /*!<Error Interrupt Enable  */
-#define  I2C_CR2_ITEVTEN                     0x00000200U     /*!<Event Interrupt Enable  */
-#define  I2C_CR2_ITBUFEN                     0x00000400U     /*!<Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       0x00000800U     /*!<DMA Requests Enable     */
-#define  I2C_CR2_LAST                        0x00001000U     /*!<DMA Last Transfer       */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     0x000000FEU     /*!<Interface Address */
-#define  I2C_OAR1_ADD8_9                     0x00000300U     /*!<Interface Address */
-
-#define  I2C_OAR1_ADD0                       0x00000001U     /*!<Bit 0 */
-#define  I2C_OAR1_ADD1                       0x00000002U     /*!<Bit 1 */
-#define  I2C_OAR1_ADD2                       0x00000004U     /*!<Bit 2 */
-#define  I2C_OAR1_ADD3                       0x00000008U     /*!<Bit 3 */
-#define  I2C_OAR1_ADD4                       0x00000010U     /*!<Bit 4 */
-#define  I2C_OAR1_ADD5                       0x00000020U     /*!<Bit 5 */
-#define  I2C_OAR1_ADD6                       0x00000040U     /*!<Bit 6 */
-#define  I2C_OAR1_ADD7                       0x00000080U     /*!<Bit 7 */
-#define  I2C_OAR1_ADD8                       0x00000100U     /*!<Bit 8 */
-#define  I2C_OAR1_ADD9                       0x00000200U     /*!<Bit 9 */
-
-#define  I2C_OAR1_ADDMODE                    0x00008000U     /*!<Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     0x00000001U        /*!<Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       0x000000FEU        /*!<Interface address           */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           0x000000FFU        /*!<8-bit Data Register         */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          0x00000001U     /*!<Start Bit (Master mode)                  */
-#define  I2C_SR1_ADDR                        0x00000002U     /*!<Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         0x00000004U     /*!<Byte Transfer Finished                          */
-#define  I2C_SR1_ADD10                       0x00000008U     /*!<10-bit header sent (Master mode)         */
-#define  I2C_SR1_STOPF                       0x00000010U     /*!<Stop detection (Slave mode)              */
-#define  I2C_SR1_RXNE                        0x00000040U     /*!<Data Register not Empty (receivers)      */
-#define  I2C_SR1_TXE                         0x00000080U     /*!<Data Register Empty (transmitters)       */
-#define  I2C_SR1_BERR                        0x00000100U     /*!<Bus Error                                       */
-#define  I2C_SR1_ARLO                        0x00000200U     /*!<Arbitration Lost (master mode)           */
-#define  I2C_SR1_AF                          0x00000400U     /*!<Acknowledge Failure                             */
-#define  I2C_SR1_OVR                         0x00000800U     /*!<Overrun/Underrun                                */
-#define  I2C_SR1_PECERR                      0x00001000U     /*!<PEC Error in reception                          */
-#define  I2C_SR1_TIMEOUT                     0x00004000U     /*!<Timeout or Tlow Error                           */
-#define  I2C_SR1_SMBALERT                    0x00008000U     /*!<SMBus Alert                                     */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         0x00000001U     /*!<Master/Slave                              */
-#define  I2C_SR2_BUSY                        0x00000002U     /*!<Bus Busy                                  */
-#define  I2C_SR2_TRA                         0x00000004U     /*!<Transmitter/Receiver                      */
-#define  I2C_SR2_GENCALL                     0x00000010U     /*!<General Call Address (Slave mode)  */
-#define  I2C_SR2_SMBDEFAULT                  0x00000020U     /*!<SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     0x00000040U     /*!<SMBus Host Header (Slave mode)     */
-#define  I2C_SR2_DUALF                       0x00000080U     /*!<Dual Flag (Slave mode)             */
-#define  I2C_SR2_PEC                         0x0000FF00U     /*!<Packet Error Checking Register            */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         0x00000FFFU     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        0x00004000U     /*!<Fast Mode Duty Cycle                                       */
-#define  I2C_CCR_FS                          0x00008000U     /*!<I2C Master Mode Selection                                  */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     0x0000003FU     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************  Bit definition for I2C_FLTR register  *******************/
-#define  I2C_FLTR_DNF                        0x0000000FU     /*!<Digital Noise Filter */
-#define  I2C_FLTR_ANOFF                      0x00000010U     /*!<Analog Noise Filter OFF */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Independent WATCHDOG                             */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         0x01U               /*!<Watchdog prescaler value update      */
-#define  IWDG_SR_RVU                         0x02U               /*!<Watchdog counter reload value update */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                             Power Control                                  */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
-#define  PWR_CR_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
-#define  PWR_CR_CWUF                         0x00000004U     /*!< Clear Wakeup Flag                   */
-#define  PWR_CR_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
-#define  PWR_CR_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
-
-#define  PWR_CR_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        0x00000020U     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        0x00000040U     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        0x00000080U     /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
-
-#define  PWR_CR_DBP                          0x00000100U     /*!< Disable Backup Domain write protection                     */
-#define  PWR_CR_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                              */
-#define  PWR_CR_LPLVDS                       0x00000400U     /*!< Low Power Regulator Low Voltage in Deep Sleep mode         */
-#define  PWR_CR_MRLVDS                       0x00000800U     /*!< Main Regulator Low Voltage in Deep Sleep mode              */
-#define  PWR_CR_ADCDC1                       0x00002000U     /*!< Refer to AN4073 on how to use this bit                     */
-#define  PWR_CR_VOS                          0x0000C000U     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */ 
-#define  PWR_CR_VOS_0                        0x00004000U     /*!< Bit 0 */
-#define  PWR_CR_VOS_1                        0x00008000U     /*!< Bit 1 */
-
-/* Legacy define */
-#define  PWR_CR_PMODE                        PWR_CR_VOS
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         0x00000001U     /*!< Wakeup Flag                                      */
-#define  PWR_CSR_SBF                         0x00000002U     /*!< Standby Flag                                     */
-#define  PWR_CSR_PVDO                        0x00000004U     /*!< PVD Output                                       */
-#define  PWR_CSR_BRR                         0x00000008U     /*!< Backup regulator ready                           */
-#define  PWR_CSR_EWUP                        0x00000100U     /*!< Enable WKUP pin                                  */
-#define  PWR_CSR_BRE                         0x00000200U     /*!< Backup regulator enable                          */
-#define  PWR_CSR_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
-
-/* Legacy define */
-#define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        0x00000001U
-#define  RCC_CR_HSIRDY                       0x00000002U
-
-#define  RCC_CR_HSITRIM                      0x000000F8U
-#define  RCC_CR_HSITRIM_0                    0x00000008U/*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    0x00000010U/*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    0x00000020U/*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    0x00000040U/*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    0x00000080U/*!<Bit 4 */
-
-#define  RCC_CR_HSICAL                       0x0000FF00U
-#define  RCC_CR_HSICAL_0                     0x00000100U/*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     0x00000200U/*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     0x00000400U/*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     0x00000800U/*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     0x00001000U/*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     0x00002000U/*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     0x00004000U/*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     0x00008000U/*!<Bit 7 */
-
-#define  RCC_CR_HSEON                        0x00010000U
-#define  RCC_CR_HSERDY                       0x00020000U
-#define  RCC_CR_HSEBYP                       0x00040000U
-#define  RCC_CR_CSSON                        0x00080000U
-#define  RCC_CR_PLLON                        0x01000000U
-#define  RCC_CR_PLLRDY                       0x02000000U
-#define  RCC_CR_PLLI2SON                     0x04000000U
-#define  RCC_CR_PLLI2SRDY                    0x08000000U
-
-/********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    0x0000003FU
-#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
-#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
-#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
-#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
-#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
-#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
-
-#define  RCC_PLLCFGR_PLLN                     0x00007FC0U
-#define  RCC_PLLCFGR_PLLN_0                   0x00000040U
-#define  RCC_PLLCFGR_PLLN_1                   0x00000080U
-#define  RCC_PLLCFGR_PLLN_2                   0x00000100U
-#define  RCC_PLLCFGR_PLLN_3                   0x00000200U
-#define  RCC_PLLCFGR_PLLN_4                   0x00000400U
-#define  RCC_PLLCFGR_PLLN_5                   0x00000800U
-#define  RCC_PLLCFGR_PLLN_6                   0x00001000U
-#define  RCC_PLLCFGR_PLLN_7                   0x00002000U
-#define  RCC_PLLCFGR_PLLN_8                   0x00004000U
-
-#define  RCC_PLLCFGR_PLLP                    0x00030000U
-#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
-#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
-
-#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
-
-#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
-#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
-#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
-#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
-#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-/*!< SW configuration */
-#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
-
-#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
-
-#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
-
-#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
-
-/*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     0x001F0000U
-#define  RCC_CFGR_RTCPRE_0                   0x00010000U
-#define  RCC_CFGR_RTCPRE_1                   0x00020000U
-#define  RCC_CFGR_RTCPRE_2                   0x00040000U
-#define  RCC_CFGR_RTCPRE_3                   0x00080000U
-#define  RCC_CFGR_RTCPRE_4                   0x00100000U
-
-/*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       0x00600000U
-#define  RCC_CFGR_MCO1_0                     0x00200000U
-#define  RCC_CFGR_MCO1_1                     0x00400000U
-
-#define  RCC_CFGR_I2SSRC                     0x00800000U
-
-#define  RCC_CFGR_MCO1PRE                    0x07000000U
-#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
-#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
-#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
-
-#define  RCC_CFGR_MCO2PRE                    0x38000000U
-#define  RCC_CFGR_MCO2PRE_0                  0x08000000U
-#define  RCC_CFGR_MCO2PRE_1                  0x10000000U
-#define  RCC_CFGR_MCO2PRE_2                  0x20000000U
-
-#define  RCC_CFGR_MCO2                       0xC0000000U
-#define  RCC_CFGR_MCO2_0                     0x40000000U
-#define  RCC_CFGR_MCO2_1                     0x80000000U
-
-/********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     0x00000001U
-#define  RCC_CIR_LSERDYF                     0x00000002U
-#define  RCC_CIR_HSIRDYF                     0x00000004U
-#define  RCC_CIR_HSERDYF                     0x00000008U
-#define  RCC_CIR_PLLRDYF                     0x00000010U
-#define  RCC_CIR_PLLI2SRDYF                  0x00000020U
-
-#define  RCC_CIR_CSSF                        0x00000080U
-#define  RCC_CIR_LSIRDYIE                    0x00000100U
-#define  RCC_CIR_LSERDYIE                    0x00000200U
-#define  RCC_CIR_HSIRDYIE                    0x00000400U
-#define  RCC_CIR_HSERDYIE                    0x00000800U
-#define  RCC_CIR_PLLRDYIE                    0x00001000U
-#define  RCC_CIR_PLLI2SRDYIE                 0x00002000U
-
-#define  RCC_CIR_LSIRDYC                     0x00010000U
-#define  RCC_CIR_LSERDYC                     0x00020000U
-#define  RCC_CIR_HSIRDYC                     0x00040000U
-#define  RCC_CIR_HSERDYC                     0x00080000U
-#define  RCC_CIR_PLLRDYC                     0x00100000U
-#define  RCC_CIR_PLLI2SRDYC                  0x00200000U
-
-#define  RCC_CIR_CSSC                        0x00800000U
-
-/********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
-#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
-#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
-#define  RCC_AHB1RSTR_GPIODRST               0x00000008U
-#define  RCC_AHB1RSTR_GPIOERST               0x00000010U
-#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
-#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
-#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
-#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
-
-/********************  Bit definition for RCC_AHB2RSTR register  **************/
-#define  RCC_AHB2RSTR_OTGFSRST               0x00000080U
-
-/********************  Bit definition for RCC_AHB3RSTR register  **************/
-
-/********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM2RST                0x00000001U
-#define  RCC_APB1RSTR_TIM3RST                0x00000002U
-#define  RCC_APB1RSTR_TIM4RST                0x00000004U
-#define  RCC_APB1RSTR_TIM5RST                0x00000008U
-#define  RCC_APB1RSTR_WWDGRST                0x00000800U
-#define  RCC_APB1RSTR_SPI2RST                0x00004000U
-#define  RCC_APB1RSTR_SPI3RST                0x00008000U
-#define  RCC_APB1RSTR_USART2RST              0x00020000U
-#define  RCC_APB1RSTR_I2C1RST                0x00200000U
-#define  RCC_APB1RSTR_I2C2RST                0x00400000U
-#define  RCC_APB1RSTR_I2C3RST                0x00800000U
-#define  RCC_APB1RSTR_PWRRST                 0x10000000U
-
-/********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                0x00000001U
-#define  RCC_APB2RSTR_USART1RST              0x00000010U
-#define  RCC_APB2RSTR_USART6RST              0x00000020U
-#define  RCC_APB2RSTR_ADCRST                 0x00000100U
-#define  RCC_APB2RSTR_SDIORST                0x00000800U
-#define  RCC_APB2RSTR_SPI1RST                0x00001000U
-#define  RCC_APB2RSTR_SPI4RST                0x00002000U
-#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
-#define  RCC_APB2RSTR_TIM9RST                0x00010000U
-#define  RCC_APB2RSTR_TIM10RST               0x00020000U
-#define  RCC_APB2RSTR_TIM11RST               0x00040000U
-
-/* Old SPI1RST bit definition, maintained for legacy purpose */
-#define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
-
-/********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
-#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
-#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
-#define  RCC_AHB1ENR_GPIODEN                 0x00000008U
-#define  RCC_AHB1ENR_GPIOEEN                 0x00000010U
-#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
-#define  RCC_AHB1ENR_CRCEN                   0x00001000U
-#define  RCC_AHB1ENR_BKPSRAMEN               0x00040000U
-#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
-#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
-
-/********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define  RCC_AHB2ENR_OTGFSEN                 0x00000080U
-
-/********************  Bit definition for RCC_AHB3ENR register  ***************/
-
-/********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM2EN                  0x00000001U
-#define  RCC_APB1ENR_TIM3EN                  0x00000002U
-#define  RCC_APB1ENR_TIM4EN                  0x00000004U
-#define  RCC_APB1ENR_TIM5EN                  0x00000008U
-#define  RCC_APB1ENR_WWDGEN                  0x00000800U
-#define  RCC_APB1ENR_SPI2EN                  0x00004000U
-#define  RCC_APB1ENR_SPI3EN                  0x00008000U
-#define  RCC_APB1ENR_USART2EN                0x00020000U
-#define  RCC_APB1ENR_I2C1EN                  0x00200000U
-#define  RCC_APB1ENR_I2C2EN                  0x00400000U
-#define  RCC_APB1ENR_I2C3EN                  0x00800000U
-#define  RCC_APB1ENR_PWREN                   0x10000000U
-
-/********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  0x00000001U
-#define  RCC_APB2ENR_USART1EN                0x00000010U
-#define  RCC_APB2ENR_USART6EN                0x00000020U
-#define  RCC_APB2ENR_ADC1EN                  0x00000100U
-#define  RCC_APB2ENR_SDIOEN                  0x00000800U
-#define  RCC_APB2ENR_SPI1EN                  0x00001000U
-#define  RCC_APB2ENR_SPI4EN                  0x00002000U
-#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
-#define  RCC_APB2ENR_TIM9EN                  0x00010000U
-#define  RCC_APB2ENR_TIM10EN                 0x00020000U
-#define  RCC_APB2ENR_TIM11EN                 0x00040000U
-
-/********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
-#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
-#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
-#define  RCC_AHB1LPENR_GPIODLPEN             0x00000008U
-#define  RCC_AHB1LPENR_GPIOELPEN             0x00000010U
-#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
-#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
-#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
-#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
-#define  RCC_AHB1LPENR_SRAM2LPEN             0x00020000U
-#define  RCC_AHB1LPENR_BKPSRAMLPEN           0x00040000U
-#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
-#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
-
-/********************  Bit definition for RCC_AHB2LPENR register  *************/
-#define  RCC_AHB2LPENR_OTGFSLPEN             0x00000080U
-
-/********************  Bit definition for RCC_AHB3LPENR register  *************/
-
-/********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM2LPEN              0x00000001U
-#define  RCC_APB1LPENR_TIM3LPEN              0x00000002U
-#define  RCC_APB1LPENR_TIM4LPEN              0x00000004U
-#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
-#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
-#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U
-#define  RCC_APB1LPENR_SPI3LPEN              0x00008000U
-#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
-#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
-#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
-#define  RCC_APB1LPENR_I2C3LPEN              0x00800000U
-#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
-#define  RCC_APB1LPENR_DACLPEN               0x20000000U
-
-/********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
-#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
-#define  RCC_APB2LPENR_USART6LPEN            0x00000020U
-#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
-#define  RCC_APB2LPENR_SDIOLPEN              0x00000800U
-#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
-#define  RCC_APB2LPENR_SPI4LPEN              0x00002000U
-#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
-#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
-#define  RCC_APB2LPENR_TIM10LPEN             0x00020000U
-#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
-
-/********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      0x00000001U
-#define  RCC_BDCR_LSERDY                     0x00000002U
-#define  RCC_BDCR_LSEBYP                     0x00000004U
-
-#define  RCC_BDCR_RTCSEL                    0x00000300U
-#define  RCC_BDCR_RTCSEL_0                  0x00000100U
-#define  RCC_BDCR_RTCSEL_1                  0x00000200U
-
-#define  RCC_BDCR_RTCEN                      0x00008000U
-#define  RCC_BDCR_BDRST                      0x00010000U
-
-/********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       0x00000001U
-#define  RCC_CSR_LSIRDY                      0x00000002U
-#define  RCC_CSR_RMVF                        0x01000000U
-#define  RCC_CSR_BORRSTF                     0x02000000U
-#define  RCC_CSR_PADRSTF                     0x04000000U
-#define  RCC_CSR_PORRSTF                     0x08000000U
-#define  RCC_CSR_SFTRSTF                     0x10000000U
-#define  RCC_CSR_WDGRSTF                     0x20000000U
-#define  RCC_CSR_WWDGRSTF                    0x40000000U
-#define  RCC_CSR_LPWRRSTF                    0x80000000U
-
-/********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    0x00001FFFU
-#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
-#define  RCC_SSCGR_SPREADSEL                 0x40000000U
-#define  RCC_SSCGR_SSCGEN                    0x80000000U
-
-/********************  Bit definition for RCC_PLLI2SCFGR register  ************/
-#define  RCC_PLLI2SCFGR_PLLI2SN              0x00007FC0U
-#define  RCC_PLLI2SCFGR_PLLI2SN_0            0x00000040U
-#define  RCC_PLLI2SCFGR_PLLI2SN_1            0x00000080U
-#define  RCC_PLLI2SCFGR_PLLI2SN_2            0x00000100U
-#define  RCC_PLLI2SCFGR_PLLI2SN_3            0x00000200U
-#define  RCC_PLLI2SCFGR_PLLI2SN_4            0x00000400U
-#define  RCC_PLLI2SCFGR_PLLI2SN_5            0x00000800U
-#define  RCC_PLLI2SCFGR_PLLI2SN_6            0x00001000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_7            0x00002000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_8            0x00004000U
-
-#define  RCC_PLLI2SCFGR_PLLI2SR              0x70000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_0            0x10000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_1            0x20000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_2            0x40000000U
-
-/********************  Bit definition for RCC_DCKCFGR register  ***************/
-#define  RCC_DCKCFGR_TIMPRE                  0x01000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            0x00400000U
-#define RTC_TR_HT                            0x00300000U
-#define RTC_TR_HT_0                          0x00100000U
-#define RTC_TR_HT_1                          0x00200000U
-#define RTC_TR_HU                            0x000F0000U
-#define RTC_TR_HU_0                          0x00010000U
-#define RTC_TR_HU_1                          0x00020000U
-#define RTC_TR_HU_2                          0x00040000U
-#define RTC_TR_HU_3                          0x00080000U
-#define RTC_TR_MNT                           0x00007000U
-#define RTC_TR_MNT_0                         0x00001000U
-#define RTC_TR_MNT_1                         0x00002000U
-#define RTC_TR_MNT_2                         0x00004000U
-#define RTC_TR_MNU                           0x00000F00U
-#define RTC_TR_MNU_0                         0x00000100U
-#define RTC_TR_MNU_1                         0x00000200U
-#define RTC_TR_MNU_2                         0x00000400U
-#define RTC_TR_MNU_3                         0x00000800U
-#define RTC_TR_ST                            0x00000070U
-#define RTC_TR_ST_0                          0x00000010U
-#define RTC_TR_ST_1                          0x00000020U
-#define RTC_TR_ST_2                          0x00000040U
-#define RTC_TR_SU                            0x0000000FU
-#define RTC_TR_SU_0                          0x00000001U
-#define RTC_TR_SU_1                          0x00000002U
-#define RTC_TR_SU_2                          0x00000004U
-#define RTC_TR_SU_3                          0x00000008U
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            0x00F00000U
-#define RTC_DR_YT_0                          0x00100000U
-#define RTC_DR_YT_1                          0x00200000U
-#define RTC_DR_YT_2                          0x00400000U
-#define RTC_DR_YT_3                          0x00800000U
-#define RTC_DR_YU                            0x000F0000U
-#define RTC_DR_YU_0                          0x00010000U
-#define RTC_DR_YU_1                          0x00020000U
-#define RTC_DR_YU_2                          0x00040000U
-#define RTC_DR_YU_3                          0x00080000U
-#define RTC_DR_WDU                           0x0000E000U
-#define RTC_DR_WDU_0                         0x00002000U
-#define RTC_DR_WDU_1                         0x00004000U
-#define RTC_DR_WDU_2                         0x00008000U
-#define RTC_DR_MT                            0x00001000U
-#define RTC_DR_MU                            0x00000F00U
-#define RTC_DR_MU_0                          0x00000100U
-#define RTC_DR_MU_1                          0x00000200U
-#define RTC_DR_MU_2                          0x00000400U
-#define RTC_DR_MU_3                          0x00000800U
-#define RTC_DR_DT                            0x00000030U
-#define RTC_DR_DT_0                          0x00000010U
-#define RTC_DR_DT_1                          0x00000020U
-#define RTC_DR_DU                            0x0000000FU
-#define RTC_DR_DU_0                          0x00000001U
-#define RTC_DR_DU_1                          0x00000002U
-#define RTC_DR_DU_2                          0x00000004U
-#define RTC_DR_DU_3                          0x00000008U
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           0x00800000U
-#define RTC_CR_OSEL                          0x00600000U
-#define RTC_CR_OSEL_0                        0x00200000U
-#define RTC_CR_OSEL_1                        0x00400000U
-#define RTC_CR_POL                           0x00100000U
-#define RTC_CR_COSEL                         0x00080000U
-#define RTC_CR_BCK                           0x00040000U
-#define RTC_CR_SUB1H                         0x00020000U
-#define RTC_CR_ADD1H                         0x00010000U
-#define RTC_CR_TSIE                          0x00008000U
-#define RTC_CR_WUTIE                         0x00004000U
-#define RTC_CR_ALRBIE                        0x00002000U
-#define RTC_CR_ALRAIE                        0x00001000U
-#define RTC_CR_TSE                           0x00000800U
-#define RTC_CR_WUTE                          0x00000400U
-#define RTC_CR_ALRBE                         0x00000200U
-#define RTC_CR_ALRAE                         0x00000100U
-#define RTC_CR_DCE                           0x00000080U
-#define RTC_CR_FMT                           0x00000040U
-#define RTC_CR_BYPSHAD                       0x00000020U
-#define RTC_CR_REFCKON                       0x00000010U
-#define RTC_CR_TSEDGE                        0x00000008U
-#define RTC_CR_WUCKSEL                       0x00000007U
-#define RTC_CR_WUCKSEL_0                     0x00000001U
-#define RTC_CR_WUCKSEL_1                     0x00000002U
-#define RTC_CR_WUCKSEL_2                     0x00000004U
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      0x00010000U
-#define RTC_ISR_TAMP1F                       0x00002000U
-#define RTC_ISR_TAMP2F                       0x00004000U
-#define RTC_ISR_TSOVF                        0x00001000U
-#define RTC_ISR_TSF                          0x00000800U
-#define RTC_ISR_WUTF                         0x00000400U
-#define RTC_ISR_ALRBF                        0x00000200U
-#define RTC_ISR_ALRAF                        0x00000100U
-#define RTC_ISR_INIT                         0x00000080U
-#define RTC_ISR_INITF                        0x00000040U
-#define RTC_ISR_RSF                          0x00000020U
-#define RTC_ISR_INITS                        0x00000010U
-#define RTC_ISR_SHPF                         0x00000008U
-#define RTC_ISR_WUTWF                        0x00000004U
-#define RTC_ISR_ALRBWF                       0x00000002U
-#define RTC_ISR_ALRAWF                       0x00000001U
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    0x007F0000U
-#define RTC_PRER_PREDIV_S                    0x00007FFFU
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS                       0x00000080U
-#define RTC_CALIBR_DC                        0x0000001FU
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      0x80000000U
-#define RTC_ALRMAR_WDSEL                     0x40000000U
-#define RTC_ALRMAR_DT                        0x30000000U
-#define RTC_ALRMAR_DT_0                      0x10000000U
-#define RTC_ALRMAR_DT_1                      0x20000000U
-#define RTC_ALRMAR_DU                        0x0F000000U
-#define RTC_ALRMAR_DU_0                      0x01000000U
-#define RTC_ALRMAR_DU_1                      0x02000000U
-#define RTC_ALRMAR_DU_2                      0x04000000U
-#define RTC_ALRMAR_DU_3                      0x08000000U
-#define RTC_ALRMAR_MSK3                      0x00800000U
-#define RTC_ALRMAR_PM                        0x00400000U
-#define RTC_ALRMAR_HT                        0x00300000U
-#define RTC_ALRMAR_HT_0                      0x00100000U
-#define RTC_ALRMAR_HT_1                      0x00200000U
-#define RTC_ALRMAR_HU                        0x000F0000U
-#define RTC_ALRMAR_HU_0                      0x00010000U
-#define RTC_ALRMAR_HU_1                      0x00020000U
-#define RTC_ALRMAR_HU_2                      0x00040000U
-#define RTC_ALRMAR_HU_3                      0x00080000U
-#define RTC_ALRMAR_MSK2                      0x00008000U
-#define RTC_ALRMAR_MNT                       0x00007000U
-#define RTC_ALRMAR_MNT_0                     0x00001000U
-#define RTC_ALRMAR_MNT_1                     0x00002000U
-#define RTC_ALRMAR_MNT_2                     0x00004000U
-#define RTC_ALRMAR_MNU                       0x00000F00U
-#define RTC_ALRMAR_MNU_0                     0x00000100U
-#define RTC_ALRMAR_MNU_1                     0x00000200U
-#define RTC_ALRMAR_MNU_2                     0x00000400U
-#define RTC_ALRMAR_MNU_3                     0x00000800U
-#define RTC_ALRMAR_MSK1                      0x00000080U
-#define RTC_ALRMAR_ST                        0x00000070U
-#define RTC_ALRMAR_ST_0                      0x00000010U
-#define RTC_ALRMAR_ST_1                      0x00000020U
-#define RTC_ALRMAR_ST_2                      0x00000040U
-#define RTC_ALRMAR_SU                        0x0000000FU
-#define RTC_ALRMAR_SU_0                      0x00000001U
-#define RTC_ALRMAR_SU_1                      0x00000002U
-#define RTC_ALRMAR_SU_2                      0x00000004U
-#define RTC_ALRMAR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      0x80000000U
-#define RTC_ALRMBR_WDSEL                     0x40000000U
-#define RTC_ALRMBR_DT                        0x30000000U
-#define RTC_ALRMBR_DT_0                      0x10000000U
-#define RTC_ALRMBR_DT_1                      0x20000000U
-#define RTC_ALRMBR_DU                        0x0F000000U
-#define RTC_ALRMBR_DU_0                      0x01000000U
-#define RTC_ALRMBR_DU_1                      0x02000000U
-#define RTC_ALRMBR_DU_2                      0x04000000U
-#define RTC_ALRMBR_DU_3                      0x08000000U
-#define RTC_ALRMBR_MSK3                      0x00800000U
-#define RTC_ALRMBR_PM                        0x00400000U
-#define RTC_ALRMBR_HT                        0x00300000U
-#define RTC_ALRMBR_HT_0                      0x00100000U
-#define RTC_ALRMBR_HT_1                      0x00200000U
-#define RTC_ALRMBR_HU                        0x000F0000U
-#define RTC_ALRMBR_HU_0                      0x00010000U
-#define RTC_ALRMBR_HU_1                      0x00020000U
-#define RTC_ALRMBR_HU_2                      0x00040000U
-#define RTC_ALRMBR_HU_3                      0x00080000U
-#define RTC_ALRMBR_MSK2                      0x00008000U
-#define RTC_ALRMBR_MNT                       0x00007000U
-#define RTC_ALRMBR_MNT_0                     0x00001000U
-#define RTC_ALRMBR_MNT_1                     0x00002000U
-#define RTC_ALRMBR_MNT_2                     0x00004000U
-#define RTC_ALRMBR_MNU                       0x00000F00U
-#define RTC_ALRMBR_MNU_0                     0x00000100U
-#define RTC_ALRMBR_MNU_1                     0x00000200U
-#define RTC_ALRMBR_MNU_2                     0x00000400U
-#define RTC_ALRMBR_MNU_3                     0x00000800U
-#define RTC_ALRMBR_MSK1                      0x00000080U
-#define RTC_ALRMBR_ST                        0x00000070U
-#define RTC_ALRMBR_ST_0                      0x00000010U
-#define RTC_ALRMBR_ST_1                      0x00000020U
-#define RTC_ALRMBR_ST_2                      0x00000040U
-#define RTC_ALRMBR_SU                        0x0000000FU
-#define RTC_ALRMBR_SU_0                      0x00000001U
-#define RTC_ALRMBR_SU_1                      0x00000002U
-#define RTC_ALRMBR_SU_2                      0x00000004U
-#define RTC_ALRMBR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          0x000000FFU
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           0x0000FFFFU
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     0x00007FFFU
-#define RTC_SHIFTR_ADD1S                     0x80000000U
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          0x00400000U
-#define RTC_TSTR_HT                          0x00300000U
-#define RTC_TSTR_HT_0                        0x00100000U
-#define RTC_TSTR_HT_1                        0x00200000U
-#define RTC_TSTR_HU                          0x000F0000U
-#define RTC_TSTR_HU_0                        0x00010000U
-#define RTC_TSTR_HU_1                        0x00020000U
-#define RTC_TSTR_HU_2                        0x00040000U
-#define RTC_TSTR_HU_3                        0x00080000U
-#define RTC_TSTR_MNT                         0x00007000U
-#define RTC_TSTR_MNT_0                       0x00001000U
-#define RTC_TSTR_MNT_1                       0x00002000U
-#define RTC_TSTR_MNT_2                       0x00004000U
-#define RTC_TSTR_MNU                         0x00000F00U
-#define RTC_TSTR_MNU_0                       0x00000100U
-#define RTC_TSTR_MNU_1                       0x00000200U
-#define RTC_TSTR_MNU_2                       0x00000400U
-#define RTC_TSTR_MNU_3                       0x00000800U
-#define RTC_TSTR_ST                          0x00000070U
-#define RTC_TSTR_ST_0                        0x00000010U
-#define RTC_TSTR_ST_1                        0x00000020U
-#define RTC_TSTR_ST_2                        0x00000040U
-#define RTC_TSTR_SU                          0x0000000FU
-#define RTC_TSTR_SU_0                        0x00000001U
-#define RTC_TSTR_SU_1                        0x00000002U
-#define RTC_TSTR_SU_2                        0x00000004U
-#define RTC_TSTR_SU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         0x0000E000U
-#define RTC_TSDR_WDU_0                       0x00002000U
-#define RTC_TSDR_WDU_1                       0x00004000U
-#define RTC_TSDR_WDU_2                       0x00008000U
-#define RTC_TSDR_MT                          0x00001000U
-#define RTC_TSDR_MU                          0x00000F00U
-#define RTC_TSDR_MU_0                        0x00000100U
-#define RTC_TSDR_MU_1                        0x00000200U
-#define RTC_TSDR_MU_2                        0x00000400U
-#define RTC_TSDR_MU_3                        0x00000800U
-#define RTC_TSDR_DT                          0x00000030U
-#define RTC_TSDR_DT_0                        0x00000010U
-#define RTC_TSDR_DT_1                        0x00000020U
-#define RTC_TSDR_DU                          0x0000000FU
-#define RTC_TSDR_DU_0                        0x00000001U
-#define RTC_TSDR_DU_1                        0x00000002U
-#define RTC_TSDR_DU_2                        0x00000004U
-#define RTC_TSDR_DU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        0x00008000U
-#define RTC_CALR_CALW8                       0x00004000U
-#define RTC_CALR_CALW16                      0x00002000U
-#define RTC_CALR_CALM                        0x000001FFU
-#define RTC_CALR_CALM_0                      0x00000001U
-#define RTC_CALR_CALM_1                      0x00000002U
-#define RTC_CALR_CALM_2                      0x00000004U
-#define RTC_CALR_CALM_3                      0x00000008U
-#define RTC_CALR_CALM_4                      0x00000010U
-#define RTC_CALR_CALM_5                      0x00000020U
-#define RTC_CALR_CALM_6                      0x00000040U
-#define RTC_CALR_CALM_7                      0x00000080U
-#define RTC_CALR_CALM_8                      0x00000100U
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               0x00040000U
-#define RTC_TAFCR_TSINSEL                    0x00020000U
-#define RTC_TAFCR_TAMPINSEL                  0x00010000U
-#define RTC_TAFCR_TAMPPUDIS                  0x00008000U
-#define RTC_TAFCR_TAMPPRCH                   0x00006000U
-#define RTC_TAFCR_TAMPPRCH_0                 0x00002000U
-#define RTC_TAFCR_TAMPPRCH_1                 0x00004000U
-#define RTC_TAFCR_TAMPFLT                    0x00001800U
-#define RTC_TAFCR_TAMPFLT_0                  0x00000800U
-#define RTC_TAFCR_TAMPFLT_1                  0x00001000U
-#define RTC_TAFCR_TAMPFREQ                   0x00000700U
-#define RTC_TAFCR_TAMPFREQ_0                 0x00000100U
-#define RTC_TAFCR_TAMPFREQ_1                 0x00000200U
-#define RTC_TAFCR_TAMPFREQ_2                 0x00000400U
-#define RTC_TAFCR_TAMPTS                     0x00000080U
-#define RTC_TAFCR_TAMP2TRG                   0x00000010U
-#define RTC_TAFCR_TAMP2E                     0x00000008U
-#define RTC_TAFCR_TAMPIE                     0x00000004U
-#define RTC_TAFCR_TAMP1TRG                   0x00000002U
-#define RTC_TAFCR_TAMP1E                     0x00000001U
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  0x0F000000U
-#define RTC_ALRMASSR_MASKSS_0                0x01000000U
-#define RTC_ALRMASSR_MASKSS_1                0x02000000U
-#define RTC_ALRMASSR_MASKSS_2                0x04000000U
-#define RTC_ALRMASSR_MASKSS_3                0x08000000U
-#define RTC_ALRMASSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
-#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
-#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
-#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
-#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
-#define RTC_ALRMBSSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           0xFFFFFFFFU
-
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          SD host Interface                                 */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SDIO_POWER register  ******************/
-#define  SDIO_POWER_PWRCTRL                  0x03U               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDIO_POWER_PWRCTRL_0                0x01U               /*!<Bit 0 */
-#define  SDIO_POWER_PWRCTRL_1                0x02U               /*!<Bit 1 */
-
-/******************  Bit definition for SDIO_CLKCR register  ******************/
-#define  SDIO_CLKCR_CLKDIV                   0x00FFU            /*!<Clock divide factor             */
-#define  SDIO_CLKCR_CLKEN                    0x0100U            /*!<Clock enable bit                */
-#define  SDIO_CLKCR_PWRSAV                   0x0200U            /*!<Power saving configuration bit  */
-#define  SDIO_CLKCR_BYPASS                   0x0400U            /*!<Clock divider bypass enable bit */
-
-#define  SDIO_CLKCR_WIDBUS                   0x1800U            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDIO_CLKCR_WIDBUS_0                 0x0800U            /*!<Bit 0 */
-#define  SDIO_CLKCR_WIDBUS_1                 0x1000U            /*!<Bit 1 */
-
-#define  SDIO_CLKCR_NEGEDGE                  0x2000U            /*!<SDIO_CK dephasing selection bit */
-#define  SDIO_CLKCR_HWFC_EN                  0x4000U            /*!<HW Flow Control enable          */
-
-/*******************  Bit definition for SDIO_ARG register  *******************/
-#define  SDIO_ARG_CMDARG                     0xFFFFFFFFU            /*!<Command argument */
-
-/*******************  Bit definition for SDIO_CMD register  *******************/
-#define  SDIO_CMD_CMDINDEX                   0x003FU            /*!<Command Index                               */
-
-#define  SDIO_CMD_WAITRESP                   0x00C0U            /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDIO_CMD_WAITRESP_0                 0x0040U            /*!< Bit 0 */
-#define  SDIO_CMD_WAITRESP_1                 0x0080U            /*!< Bit 1 */
-
-#define  SDIO_CMD_WAITINT                    0x0100U            /*!<CPSM Waits for Interrupt Request                               */
-#define  SDIO_CMD_WAITPEND                   0x0200U            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDIO_CMD_CPSMEN                     0x0400U            /*!<Command path state machine (CPSM) Enable bit                   */
-#define  SDIO_CMD_SDIOSUSPEND                0x0800U            /*!<SD I/O suspend command                                         */
-#define  SDIO_CMD_ENCMDCOMPL                 0x1000U            /*!<Enable CMD completion                                          */
-#define  SDIO_CMD_NIEN                       0x2000U            /*!<Not Interrupt Enable */
-#define  SDIO_CMD_CEATACMD                   0x4000U            /*!<CE-ATA command       */
-
-/*****************  Bit definition for SDIO_RESPCMD register  *****************/
-#define  SDIO_RESPCMD_RESPCMD                0x3FU               /*!<Response command index */
-
-/******************  Bit definition for SDIO_RESP0 register  ******************/
-#define  SDIO_RESP0_CARDSTATUS0              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP1 register  ******************/
-#define  SDIO_RESP1_CARDSTATUS1              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP2 register  ******************/
-#define  SDIO_RESP2_CARDSTATUS2              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP3 register  ******************/
-#define  SDIO_RESP3_CARDSTATUS3              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP4 register  ******************/
-#define  SDIO_RESP4_CARDSTATUS4              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_DTIMER register  *****************/
-#define  SDIO_DTIMER_DATATIME                0xFFFFFFFFU        /*!<Data timeout period. */
-
-/******************  Bit definition for SDIO_DLEN register  *******************/
-#define  SDIO_DLEN_DATALENGTH                0x01FFFFFFU        /*!<Data length value    */
-
-/******************  Bit definition for SDIO_DCTRL register  ******************/
-#define  SDIO_DCTRL_DTEN                     0x0001U            /*!<Data transfer enabled bit         */
-#define  SDIO_DCTRL_DTDIR                    0x0002U            /*!<Data transfer direction selection */
-#define  SDIO_DCTRL_DTMODE                   0x0004U            /*!<Data transfer mode selection      */
-#define  SDIO_DCTRL_DMAEN                    0x0008U            /*!<DMA enabled bit                   */
-
-#define  SDIO_DCTRL_DBLOCKSIZE               0x00F0U            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDIO_DCTRL_DBLOCKSIZE_0             0x0010U            /*!<Bit 0 */
-#define  SDIO_DCTRL_DBLOCKSIZE_1             0x0020U            /*!<Bit 1 */
-#define  SDIO_DCTRL_DBLOCKSIZE_2             0x0040U            /*!<Bit 2 */
-#define  SDIO_DCTRL_DBLOCKSIZE_3             0x0080U            /*!<Bit 3 */
-
-#define  SDIO_DCTRL_RWSTART                  0x0100U            /*!<Read wait start         */
-#define  SDIO_DCTRL_RWSTOP                   0x0200U            /*!<Read wait stop          */
-#define  SDIO_DCTRL_RWMOD                    0x0400U            /*!<Read wait mode          */
-#define  SDIO_DCTRL_SDIOEN                   0x0800U            /*!<SD I/O enable functions */
-
-/******************  Bit definition for SDIO_DCOUNT register  *****************/
-#define  SDIO_DCOUNT_DATACOUNT               0x01FFFFFFU        /*!<Data count value */
-
-/******************  Bit definition for SDIO_STA register  ********************/
-#define  SDIO_STA_CCRCFAIL                   0x00000001U        /*!<Command response received (CRC check failed)  */
-#define  SDIO_STA_DCRCFAIL                   0x00000002U        /*!<Data block sent/received (CRC check failed)   */
-#define  SDIO_STA_CTIMEOUT                   0x00000004U        /*!<Command response timeout                      */
-#define  SDIO_STA_DTIMEOUT                   0x00000008U        /*!<Data timeout                                  */
-#define  SDIO_STA_TXUNDERR                   0x00000010U        /*!<Transmit FIFO underrun error                  */
-#define  SDIO_STA_RXOVERR                    0x00000020U        /*!<Received FIFO overrun error                   */
-#define  SDIO_STA_CMDREND                    0x00000040U        /*!<Command response received (CRC check passed)  */
-#define  SDIO_STA_CMDSENT                    0x00000080U        /*!<Command sent (no response required)           */
-#define  SDIO_STA_DATAEND                    0x00000100U        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
-#define  SDIO_STA_STBITERR                   0x00000200U        /*!<Start bit not detected on all data signals in wide bus mode */
-#define  SDIO_STA_DBCKEND                    0x00000400U        /*!<Data block sent/received (CRC check passed)   */
-#define  SDIO_STA_CMDACT                     0x00000800U        /*!<Command transfer in progress                  */
-#define  SDIO_STA_TXACT                      0x00001000U        /*!<Data transmit in progress                     */
-#define  SDIO_STA_RXACT                      0x00002000U        /*!<Data receive in progress                      */
-#define  SDIO_STA_TXFIFOHE                   0x00004000U        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDIO_STA_RXFIFOHF                   0x00008000U        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDIO_STA_TXFIFOF                    0x00010000U        /*!<Transmit FIFO full                            */
-#define  SDIO_STA_RXFIFOF                    0x00020000U        /*!<Receive FIFO full                             */
-#define  SDIO_STA_TXFIFOE                    0x00040000U        /*!<Transmit FIFO empty                           */
-#define  SDIO_STA_RXFIFOE                    0x00080000U        /*!<Receive FIFO empty                            */
-#define  SDIO_STA_TXDAVL                     0x00100000U        /*!<Data available in transmit FIFO               */
-#define  SDIO_STA_RXDAVL                     0x00200000U        /*!<Data available in receive FIFO                */
-#define  SDIO_STA_SDIOIT                     0x00400000U        /*!<SDIO interrupt received                       */
-#define  SDIO_STA_CEATAEND                   0x00800000U        /*!<CE-ATA command completion signal received for CMD61 */
-
-/*******************  Bit definition for SDIO_ICR register  *******************/
-#define  SDIO_ICR_CCRCFAILC                  0x00000001U        /*!<CCRCFAIL flag clear bit */
-#define  SDIO_ICR_DCRCFAILC                  0x00000002U        /*!<DCRCFAIL flag clear bit */
-#define  SDIO_ICR_CTIMEOUTC                  0x00000004U        /*!<CTIMEOUT flag clear bit */
-#define  SDIO_ICR_DTIMEOUTC                  0x00000008U        /*!<DTIMEOUT flag clear bit */
-#define  SDIO_ICR_TXUNDERRC                  0x00000010U        /*!<TXUNDERR flag clear bit */
-#define  SDIO_ICR_RXOVERRC                   0x00000020U        /*!<RXOVERR flag clear bit  */
-#define  SDIO_ICR_CMDRENDC                   0x00000040U        /*!<CMDREND flag clear bit  */
-#define  SDIO_ICR_CMDSENTC                   0x00000080U        /*!<CMDSENT flag clear bit  */
-#define  SDIO_ICR_DATAENDC                   0x00000100U        /*!<DATAEND flag clear bit  */
-#define  SDIO_ICR_STBITERRC                  0x00000200U        /*!<STBITERR flag clear bit */
-#define  SDIO_ICR_DBCKENDC                   0x00000400U        /*!<DBCKEND flag clear bit  */
-#define  SDIO_ICR_SDIOITC                    0x00400000U        /*!<SDIOIT flag clear bit   */
-#define  SDIO_ICR_CEATAENDC                  0x00800000U        /*!<CEATAEND flag clear bit */
-
-/******************  Bit definition for SDIO_MASK register  *******************/
-#define  SDIO_MASK_CCRCFAILIE                0x00000001U        /*!<Command CRC Fail Interrupt Enable          */
-#define  SDIO_MASK_DCRCFAILIE                0x00000002U        /*!<Data CRC Fail Interrupt Enable             */
-#define  SDIO_MASK_CTIMEOUTIE                0x00000004U        /*!<Command TimeOut Interrupt Enable           */
-#define  SDIO_MASK_DTIMEOUTIE                0x00000008U        /*!<Data TimeOut Interrupt Enable              */
-#define  SDIO_MASK_TXUNDERRIE                0x00000010U        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
-#define  SDIO_MASK_RXOVERRIE                 0x00000020U        /*!<Rx FIFO OverRun Error Interrupt Enable     */
-#define  SDIO_MASK_CMDRENDIE                 0x00000040U        /*!<Command Response Received Interrupt Enable */
-#define  SDIO_MASK_CMDSENTIE                 0x00000080U        /*!<Command Sent Interrupt Enable              */
-#define  SDIO_MASK_DATAENDIE                 0x00000100U        /*!<Data End Interrupt Enable                  */
-#define  SDIO_MASK_STBITERRIE                0x00000200U        /*!<Start Bit Error Interrupt Enable           */
-#define  SDIO_MASK_DBCKENDIE                 0x00000400U        /*!<Data Block End Interrupt Enable            */
-#define  SDIO_MASK_CMDACTIE                  0x00000800U        /*!<CCommand Acting Interrupt Enable           */
-#define  SDIO_MASK_TXACTIE                   0x00001000U        /*!<Data Transmit Acting Interrupt Enable      */
-#define  SDIO_MASK_RXACTIE                   0x00002000U        /*!<Data receive acting interrupt enabled      */
-#define  SDIO_MASK_TXFIFOHEIE                0x00004000U        /*!<Tx FIFO Half Empty interrupt Enable        */
-#define  SDIO_MASK_RXFIFOHFIE                0x00008000U        /*!<Rx FIFO Half Full interrupt Enable         */
-#define  SDIO_MASK_TXFIFOFIE                 0x00010000U        /*!<Tx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_RXFIFOFIE                 0x00020000U        /*!<Rx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_TXFIFOEIE                 0x00040000U        /*!<Tx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_RXFIFOEIE                 0x00080000U        /*!<Rx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_TXDAVLIE                  0x00100000U        /*!<Data available in Tx FIFO interrupt Enable */
-#define  SDIO_MASK_RXDAVLIE                  0x00200000U        /*!<Data available in Rx FIFO interrupt Enable */
-#define  SDIO_MASK_SDIOITIE                  0x00400000U        /*!<SDIO Mode Interrupt Received interrupt Enable */
-#define  SDIO_MASK_CEATAENDIE                0x00800000U        /*!<CE-ATA command completion signal received Interrupt Enable */
-
-/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
-#define  SDIO_FIFOCNT_FIFOCOUNT              0x00FFFFFFU        /*!<Remaining number of words to be written to or read from the FIFO */
-
-/******************  Bit definition for SDIO_FIFO register  *******************/
-#define  SDIO_FIFO_FIFODATA                  0xFFFFFFFFU        /*!<Receive and transmit FIFO data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        0x00000001U            /*!<Clock Phase      */
-#define  SPI_CR1_CPOL                        0x00000002U            /*!<Clock Polarity   */
-#define  SPI_CR1_MSTR                        0x00000004U            /*!<Master Selection */
-
-#define  SPI_CR1_BR                          0x00000038U            /*!<BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        0x00000008U            /*!<Bit 0 */
-#define  SPI_CR1_BR_1                        0x00000010U            /*!<Bit 1 */
-#define  SPI_CR1_BR_2                        0x00000020U            /*!<Bit 2 */
-
-#define  SPI_CR1_SPE                         0x00000040U            /*!<SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    0x00000080U            /*!<Frame Format                        */
-#define  SPI_CR1_SSI                         0x00000100U            /*!<Internal slave select               */
-#define  SPI_CR1_SSM                         0x00000200U            /*!<Software slave management           */
-#define  SPI_CR1_RXONLY                      0x00000400U            /*!<Receive only                        */
-#define  SPI_CR1_DFF                         0x00000800U            /*!<Data Frame Format                   */
-#define  SPI_CR1_CRCNEXT                     0x00001000U            /*!<Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       0x00002000U            /*!<Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      0x00004000U            /*!<Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    0x00008000U            /*!<Bidirectional data mode enable      */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     0x00000001U               /*!<Rx Buffer DMA Enable                 */
-#define  SPI_CR2_TXDMAEN                     0x00000002U               /*!<Tx Buffer DMA Enable                 */
-#define  SPI_CR2_SSOE                        0x00000004U               /*!<SS Output Enable                     */
-#define  SPI_CR2_FRF                         0x00000010U               /*!<Frame Format                         */
-#define  SPI_CR2_ERRIE                       0x00000020U               /*!<Error Interrupt Enable               */
-#define  SPI_CR2_RXNEIE                      0x00000040U               /*!<RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       0x00000080U               /*!<Tx buffer Empty Interrupt Enable     */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         0x00000001U               /*!<Receive buffer Not Empty */
-#define  SPI_SR_TXE                          0x00000002U               /*!<Transmit buffer Empty    */
-#define  SPI_SR_CHSIDE                       0x00000004U               /*!<Channel side             */
-#define  SPI_SR_UDR                          0x00000008U               /*!<Underrun flag            */
-#define  SPI_SR_CRCERR                       0x00000010U               /*!<CRC Error flag           */
-#define  SPI_SR_MODF                         0x00000020U               /*!<Mode fault               */
-#define  SPI_SR_OVR                          0x00000040U               /*!<Overrun flag             */
-#define  SPI_SR_BSY                          0x00000080U               /*!<Busy flag                */
-#define  SPI_SR_FRE                          0x00000100U               /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           0x0000FFFFU            /*!<Data Register           */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   0x0000FFFFU            /*!<CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    0x0000FFFFU            /*!<Rx CRC Register         */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    0x0000FFFFU            /*!<Tx CRC Register         */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   0x00000001U            /*!<Channel length (number of bits per audio channel) */
-
-#define  SPI_I2SCFGR_DATLEN                  0x00000006U            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define  SPI_I2SCFGR_DATLEN_0                0x00000002U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                0x00000004U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_CKPOL                   0x00000008U            /*!<steady state clock polarity               */
-
-#define  SPI_I2SCFGR_I2SSTD                  0x00000030U            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U            /*!<PCM frame synchronization                 */
-
-#define  SPI_I2SCFGR_I2SCFG                  0x00000300U            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_I2SE                    0x00000400U            /*!<I2S Enable         */
-#define  SPI_I2SCFGR_I2SMOD                  0x00000800U            /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    0x000000FFU            /*!<I2S Linear prescaler         */
-#define  SPI_I2SPR_ODD                       0x00000100U            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     0x00000200U            /*!<Master Clock Output Enable   */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 SYSCFG                                     */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
-#define SYSCFG_MEMRMP_MEM_MODE          0x00000007U /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        0x00000001U
-#define SYSCFG_MEMRMP_MEM_MODE_1        0x00000002U
-#define SYSCFG_MEMRMP_MEM_MODE_2        0x00000004U
-
-/******************  Bit definition for SYSCFG_PMC register  ******************/
-#define SYSCFG_PMC_ADC1DC2              0x00010000U /*!< Refer to AN4073 on how to use this bit  */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
-/** 
-  * @brief   EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         0x0003U /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         0x0004U /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
-
-/** 
-  * @brief   EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         0x0030U /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         0x0040U /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
-
-/** 
-  * @brief   EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         0x0300U /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         0x0400U /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
-
-/** 
-  * @brief   EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         0x3000U /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         0x4000U /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
-/** 
-  * @brief   EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         0x0003U /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         0x0004U /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
-
-/** 
-  * @brief   EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         0x0030U /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         0x0040U /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
-
-/** 
-  * @brief   EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         0x0300U /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         0x0400U /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
-
-/** 
-  * @brief   EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         0x3000U /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         0x4000U /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
-
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
-           
-/** 
-  * @brief   EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         0x0003U /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         0x0004U /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
-
-/** 
-  * @brief   EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         0x0030U /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         0x0040U /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
-
-/** 
-  * @brief   EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        0x0300U /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        0x0400U /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
-
-/** 
-  * @brief   EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        0x3000U /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        0x4000U /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
-/** 
-  * @brief   EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        0x0003U /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        0x0004U /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
-
-/** 
-  * @brief   EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        0x0030U /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        0x0040U /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
-
-/** 
-  * @brief   EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        0x0300U /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        0x0400U /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
-
-/** 
-  * @brief   EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        0x3000U /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        0x4000U /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
-
-/******************  Bit definition for SYSCFG_CMPCR register  ****************/  
-#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell ready flag */
-#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell power-down */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    TIM                                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
-#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
-#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
-#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
-#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
-
-#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
-
-#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
-
-#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        0x0001U            /*!<Capture/Compare Preloaded Control        */
-#define  TIM_CR2_CCUS                        0x0004U            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        0x0008U            /*!<Capture/Compare DMA Selection            */
-
-#define  TIM_CR2_MMS                         0x0070U            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
-#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
-#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
-#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        0x0007U            /*!<SMS[2:0] bits (Slave mode selection)    */
-#define  TIM_SMCR_SMS_0                      0x0001U            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      0x0002U            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      0x0004U            /*!<Bit 2 */
-
-#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
-#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
-
-#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
-
-#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
-
-#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
-#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
-#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
-#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
-#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
-#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
-#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
-#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
-#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
-#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
-#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
-#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
-#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
-#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
-#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
-#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
-#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
-#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
-#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          0x01U               /*!<Update Generation                         */
-#define  TIM_EGR_CC1G                        0x02U               /*!<Capture/Compare 1 Generation              */
-#define  TIM_EGR_CC2G                        0x04U               /*!<Capture/Compare 2 Generation              */
-#define  TIM_EGR_CC3G                        0x08U               /*!<Capture/Compare 3 Generation              */
-#define  TIM_EGR_CC4G                        0x10U               /*!<Capture/Compare 4 Generation              */
-#define  TIM_EGR_COMG                        0x20U               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          0x40U               /*!<Trigger Generation                        */
-#define  TIM_EGR_BG                          0x80U               /*!<Break Generation                          */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      0x0003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    0x0001U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    0x0002U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC1FE                     0x0004U            /*!<Output Compare 1 Fast enable                 */
-#define  TIM_CCMR1_OC1PE                     0x0008U            /*!<Output Compare 1 Preload enable              */
-
-#define  TIM_CCMR1_OC1M                      0x0070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define  TIM_CCMR1_OC1M_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    0x0040U            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC1CE                     0x0080U            /*!<Output Compare 1Clear Enable                 */
-
-#define  TIM_CCMR1_CC2S                      0x0300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    0x0100U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    0x0200U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC2FE                     0x0400U            /*!<Output Compare 2 Fast enable                 */
-#define  TIM_CCMR1_OC2PE                     0x0800U            /*!<Output Compare 2 Preload enable              */
-
-#define  TIM_CCMR1_OC2M                      0x7000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define  TIM_CCMR1_OC2M_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    0x4000U            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC2CE                     0x8000U            /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      0x0003U            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define  TIM_CCMR2_CC3S_0                    0x0001U            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    0x0002U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC3FE                     0x0004U            /*!<Output Compare 3 Fast enable           */
-#define  TIM_CCMR2_OC3PE                     0x0008U            /*!<Output Compare 3 Preload enable        */
-
-#define  TIM_CCMR2_OC3M                      0x0070U            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    0x0040U            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC3CE                     0x0080U            /*!<Output Compare 3 Clear Enable */
-
-#define  TIM_CCMR2_CC4S                      0x0300U            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    0x0100U            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    0x0200U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC4FE                     0x0400U            /*!<Output Compare 4 Fast enable    */
-#define  TIM_CCMR2_OC4PE                     0x0800U            /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR2_OC4M                      0x7000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    0x4000U            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       0x0001U            /*!<Capture/Compare 1 output enable                 */
-#define  TIM_CCER_CC1P                       0x0002U            /*!<Capture/Compare 1 output Polarity               */
-#define  TIM_CCER_CC1NE                      0x0004U            /*!<Capture/Compare 1 Complementary output enable   */
-#define  TIM_CCER_CC1NP                      0x0008U            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       0x0010U            /*!<Capture/Compare 2 output enable                 */
-#define  TIM_CCER_CC2P                       0x0020U            /*!<Capture/Compare 2 output Polarity               */
-#define  TIM_CCER_CC2NE                      0x0040U            /*!<Capture/Compare 2 Complementary output enable   */
-#define  TIM_CCER_CC2NP                      0x0080U            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       0x0100U            /*!<Capture/Compare 3 output enable                 */
-#define  TIM_CCER_CC3P                       0x0200U            /*!<Capture/Compare 3 output Polarity               */
-#define  TIM_CCER_CC3NE                      0x0400U            /*!<Capture/Compare 3 Complementary output enable   */
-#define  TIM_CCER_CC3NP                      0x0800U            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       0x1000U            /*!<Capture/Compare 4 output enable                 */
-#define  TIM_CCER_CC4P                       0x2000U            /*!<Capture/Compare 4 output Polarity               */
-#define  TIM_CCER_CC4NP                      0x8000U            /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         0xFFU               /*!<Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
-
-/*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        0x00FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      0x0001U            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      0x0002U            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      0x0004U            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      0x0008U            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      0x0010U            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      0x0020U            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      0x0040U            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      0x0080U            /*!<Bit 7 */
-
-#define  TIM_BDTR_LOCK                       0x0300U            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     0x0100U            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     0x0200U            /*!<Bit 1 */
-
-#define  TIM_BDTR_OSSI                       0x0400U            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       0x0800U            /*!<Off-State Selection for Run mode  */
-#define  TIM_BDTR_BKE                        0x1000U            /*!<Break enable                      */
-#define  TIM_BDTR_BKP                        0x2000U            /*!<Break Polarity                    */
-#define  TIM_BDTR_AOE                        0x4000U            /*!<Automatic Output enable           */
-#define  TIM_BDTR_MOE                        0x8000U            /*!<Main Output enable                */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
-
-#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
-#define TIM_OR_ITR1_RMP                      0x0C00U            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
-#define TIM_OR_ITR1_RMP_0                    0x0400U            /*!<Bit 0 */
-#define TIM_OR_ITR1_RMP_1                    0x0800U            /*!<Bit 1 */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*         Universal Synchronous Asynchronous Receiver Transmitter            */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         0x0001U            /*!<Parity Error                 */
-#define  USART_SR_FE                         0x0002U            /*!<Framing Error                */
-#define  USART_SR_NE                         0x0004U            /*!<Noise Error Flag             */
-#define  USART_SR_ORE                        0x0008U            /*!<OverRun Error                */
-#define  USART_SR_IDLE                       0x0010U            /*!<IDLE line detected           */
-#define  USART_SR_RXNE                       0x0020U            /*!<Read Data Register Not Empty */
-#define  USART_SR_TC                         0x0040U            /*!<Transmission Complete        */
-#define  USART_SR_TXE                        0x0080U            /*!<Transmit Data Register Empty */
-#define  USART_SR_LBD                        0x0100U            /*!<LIN Break Detection Flag     */
-#define  USART_SR_CTS                        0x0200U            /*!<CTS Flag                     */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         0x01FFU            /*!<Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_Fraction              0x000FU            /*!<Fraction of USARTDIV */
-#define  USART_BRR_DIV_Mantissa              0xFFF0U            /*!<Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       0x0001U            /*!<Send Break                             */
-#define  USART_CR1_RWU                       0x0002U            /*!<Receiver wakeup                        */
-#define  USART_CR1_RE                        0x0004U            /*!<Receiver Enable                        */
-#define  USART_CR1_TE                        0x0008U            /*!<Transmitter Enable                     */
-#define  USART_CR1_IDLEIE                    0x0010U            /*!<IDLE Interrupt Enable                  */
-#define  USART_CR1_RXNEIE                    0x0020U            /*!<RXNE Interrupt Enable                  */
-#define  USART_CR1_TCIE                      0x0040U            /*!<Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     0x0080U            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PEIE                      0x0100U            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PS                        0x0200U            /*!<Parity Selection                       */
-#define  USART_CR1_PCE                       0x0400U            /*!<Parity Control Enable                  */
-#define  USART_CR1_WAKE                      0x0800U            /*!<Wakeup method                          */
-#define  USART_CR1_M                         0x1000U            /*!<Word length                            */
-#define  USART_CR1_UE                        0x2000U            /*!<USART Enable                           */
-#define  USART_CR1_OVER8                     0x8000U            /*!<USART Oversampling by 8 enable         */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       0x000FU            /*!<Address of the USART node            */
-#define  USART_CR2_LBDL                      0x0020U            /*!<LIN Break Detection Length           */
-#define  USART_CR2_LBDIE                     0x0040U            /*!<LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      0x0100U            /*!<Last Bit Clock pulse                 */
-#define  USART_CR2_CPHA                      0x0200U            /*!<Clock Phase                          */
-#define  USART_CR2_CPOL                      0x0400U            /*!<Clock Polarity                       */
-#define  USART_CR2_CLKEN                     0x0800U            /*!<Clock Enable                         */
-
-#define  USART_CR2_STOP                      0x3000U            /*!<STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    0x1000U            /*!<Bit 0 */
-#define  USART_CR2_STOP_1                    0x2000U            /*!<Bit 1 */
-
-#define  USART_CR2_LINEN                     0x4000U            /*!<LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       0x0001U            /*!<Error Interrupt Enable      */
-#define  USART_CR3_IREN                      0x0002U            /*!<IrDA mode Enable            */
-#define  USART_CR3_IRLP                      0x0004U            /*!<IrDA Low-Power              */
-#define  USART_CR3_HDSEL                     0x0008U            /*!<Half-Duplex Selection       */
-#define  USART_CR3_NACK                      0x0010U            /*!<Smartcard NACK enable       */
-#define  USART_CR3_SCEN                      0x0020U            /*!<Smartcard mode enable       */
-#define  USART_CR3_DMAR                      0x0040U            /*!<DMA Enable Receiver         */
-#define  USART_CR3_DMAT                      0x0080U            /*!<DMA Enable Transmitter      */
-#define  USART_CR3_RTSE                      0x0100U            /*!<RTS Enable                  */
-#define  USART_CR3_CTSE                      0x0200U            /*!<CTS Enable                  */
-#define  USART_CR3_CTSIE                     0x0400U            /*!<CTS Interrupt Enable        */
-#define  USART_CR3_ONEBIT                    0x0800U            /*!<USART One bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      0x00FFU            /*!<PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    0x0001U            /*!<Bit 0 */
-#define  USART_GTPR_PSC_1                    0x0002U            /*!<Bit 1 */
-#define  USART_GTPR_PSC_2                    0x0004U            /*!<Bit 2 */
-#define  USART_GTPR_PSC_3                    0x0008U            /*!<Bit 3 */
-#define  USART_GTPR_PSC_4                    0x0010U            /*!<Bit 4 */
-#define  USART_GTPR_PSC_5                    0x0020U            /*!<Bit 5 */
-#define  USART_GTPR_PSC_6                    0x0040U            /*!<Bit 6 */
-#define  USART_GTPR_PSC_7                    0x0080U            /*!<Bit 7 */
-
-#define  USART_GTPR_GT                       0xFF00U            /*!<Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Window WATCHDOG                                 */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           0x7FU               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T_0                         0x01U               /*!<Bit 0 */
-#define  WWDG_CR_T_1                         0x02U               /*!<Bit 1 */
-#define  WWDG_CR_T_2                         0x04U               /*!<Bit 2 */
-#define  WWDG_CR_T_3                         0x08U               /*!<Bit 3 */
-#define  WWDG_CR_T_4                         0x10U               /*!<Bit 4 */
-#define  WWDG_CR_T_5                         0x20U               /*!<Bit 5 */
-#define  WWDG_CR_T_6                         0x40U               /*!<Bit 6 */
-/* Legacy defines */
-#define  WWDG_CR_T0                          WWDG_CR_T_0
-#define  WWDG_CR_T1                          WWDG_CR_T_1
-#define  WWDG_CR_T2                          WWDG_CR_T_2
-#define  WWDG_CR_T3                          WWDG_CR_T_3
-#define  WWDG_CR_T4                          WWDG_CR_T_4
-#define  WWDG_CR_T5                          WWDG_CR_T_5
-#define  WWDG_CR_T6                          WWDG_CR_T_6
-
-#define  WWDG_CR_WDGA                        0x80U               /*!<Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          0x007FU            /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W_0                        0x0001U            /*!<Bit 0 */
-#define  WWDG_CFR_W_1                        0x0002U            /*!<Bit 1 */
-#define  WWDG_CFR_W_2                        0x0004U            /*!<Bit 2 */
-#define  WWDG_CFR_W_3                        0x0008U            /*!<Bit 3 */
-#define  WWDG_CFR_W_4                        0x0010U            /*!<Bit 4 */
-#define  WWDG_CFR_W_5                        0x0020U            /*!<Bit 5 */
-#define  WWDG_CFR_W_6                        0x0040U            /*!<Bit 6 */
-/* Legacy defines */
-#define  WWDG_CFR_W0                         WWDG_CFR_W_0
-#define  WWDG_CFR_W1                         WWDG_CFR_W_1
-#define  WWDG_CFR_W2                         WWDG_CFR_W_2
-#define  WWDG_CFR_W3                         WWDG_CFR_W_3
-#define  WWDG_CFR_W4                         WWDG_CFR_W_4
-#define  WWDG_CFR_W5                         WWDG_CFR_W_5
-#define  WWDG_CFR_W6                         WWDG_CFR_W_6
-
-#define  WWDG_CFR_WDGTB                      0x0180U            /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB_0                    0x0080U            /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB_1                    0x0100U            /*!<Bit 1 */
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
-
-#define  WWDG_CFR_EWI                        0x0200U            /*!<Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        0x01U               /*!<Early Wakeup Interrupt Flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                DBG                                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
-#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
-
-/********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
-#define  DBGMCU_CR_DBG_STOP                  0x00000002U
-#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
-#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
-
-#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
-#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U/*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U/*!<Bit 1 */
-
-/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            0x00000001U
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            0x00000002U
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            0x00000004U
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            0x00000020U
-#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           0x00000040U
-#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           0x00000080U
-#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           0x00000100U
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
-#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
-/* Old IWDGSTOP bit definition, maintained for legacy purpose */
-#define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
-
-/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        0x00000001U
-#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        0x00000002U
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        0x00010000U
-#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       0x00020000U
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       0x00040000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                                       USB_OTG			                        */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/
-#define USB_OTG_GOTGCTL_SRQSCS                  0x00000001U            /*!< Session request success */
-#define USB_OTG_GOTGCTL_SRQ                     0x00000002U            /*!< Session request */
-#define USB_OTG_GOTGCTL_HNGSCS                  0x00000100U            /*!< Host negotiation success */
-#define USB_OTG_GOTGCTL_HNPRQ                   0x00000200U            /*!< HNP request */
-#define USB_OTG_GOTGCTL_HSHNPEN                 0x00000400U            /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_DHNPEN                  0x00000800U            /*!< Device HNP enabled */
-#define USB_OTG_GOTGCTL_CIDSTS                  0x00010000U            /*!< Connector ID status */
-#define USB_OTG_GOTGCTL_DBCT                    0x00020000U            /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD                   0x00040000U            /*!< A-session valid */
-#define USB_OTG_GOTGCTL_BSVLD                   0x00080000U            /*!< B-session valid */
-
-/********************  Bit definition forUSB_OTG_HCFG register  ********************/
-
-#define USB_OTG_HCFG_FSLSPCS                 0x00000003U            /*!< FS/LS PHY clock select */
-#define USB_OTG_HCFG_FSLSPCS_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCFG_FSLSPCS_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCFG_FSLSS                   0x00000004U            /*!< FS- and LS-only support */
-
-/********************  Bit definition forUSB_OTG_DCFG register  ********************/
-
-#define USB_OTG_DCFG_DSPD                    0x00000003U            /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                  0x00000001U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DSPD_1                  0x00000002U            /*!<Bit 1 */
-#define USB_OTG_DCFG_NZLSOHSK                0x00000004U            /*!< Nonzero-length status OUT handshake */
-
-#define USB_OTG_DCFG_DAD                     0x000007F0U            /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                   0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DAD_1                   0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCFG_DAD_2                   0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCFG_DAD_3                   0x00000080U            /*!<Bit 3 */
-#define USB_OTG_DCFG_DAD_4                   0x00000100U            /*!<Bit 4 */
-#define USB_OTG_DCFG_DAD_5                   0x00000200U            /*!<Bit 5 */
-#define USB_OTG_DCFG_DAD_6                   0x00000400U            /*!<Bit 6 */
-
-#define USB_OTG_DCFG_PFIVL                   0x00001800U            /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PFIVL_1                 0x00001000U            /*!<Bit 1 */
-
-#define USB_OTG_DCFG_PERSCHIVL               0x03000000U            /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0             0x01000000U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PERSCHIVL_1             0x02000000U            /*!<Bit 1 */
-
-/********************  Bit definition forUSB_OTG_PCGCR register  ********************/
-#define USB_OTG_PCGCR_STPPCLK                 0x00000001U            /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK                0x00000002U            /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP                 0x00000010U            /*!< PHY suspended */
-
-/********************  Bit definition forUSB_OTG_GOTGINT register  ********************/
-#define USB_OTG_GOTGINT_SEDET                   0x00000004U            /*!< Session end detected */
-#define USB_OTG_GOTGINT_SRSSCHG                 0x00000100U            /*!< Session request success status change */
-#define USB_OTG_GOTGINT_HNSSCHG                 0x00000200U            /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET                  0x00020000U            /*!< Host negotiation detected */
-#define USB_OTG_GOTGINT_ADTOCHG                 0x00040000U            /*!< A-device timeout change */
-#define USB_OTG_GOTGINT_DBCDNE                  0x00080000U            /*!< Debounce done */
-
-/********************  Bit definition forUSB_OTG_DCTL register  ********************/
-#define USB_OTG_DCTL_RWUSIG                  0x00000001U            /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS                    0x00000002U            /*!< Soft disconnect */
-#define USB_OTG_DCTL_GINSTS                  0x00000004U            /*!< Global IN NAK status */
-#define USB_OTG_DCTL_GONSTS                  0x00000008U            /*!< Global OUT NAK status */
-
-#define USB_OTG_DCTL_TCTL                    0x00000070U            /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                  0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCTL_TCTL_1                  0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCTL_TCTL_2                  0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCTL_SGINAK                  0x00000080U            /*!< Set global IN NAK */
-#define USB_OTG_DCTL_CGINAK                  0x00000100U            /*!< Clear global IN NAK */
-#define USB_OTG_DCTL_SGONAK                  0x00000200U            /*!< Set global OUT NAK */
-#define USB_OTG_DCTL_CGONAK                  0x00000400U            /*!< Clear global OUT NAK */
-#define USB_OTG_DCTL_POPRGDNE                0x00000800U            /*!< Power-on programming done */
-
-/********************  Bit definition forUSB_OTG_HFIR register  ********************/
-#define USB_OTG_HFIR_FRIVL                   0x0000FFFFU            /*!< Frame interval */
-
-/********************  Bit definition forUSB_OTG_HFNUM register  ********************/
-#define USB_OTG_HFNUM_FRNUM                   0x0000FFFFU            /*!< Frame number */
-#define USB_OTG_HFNUM_FTREM                   0xFFFF0000U            /*!< Frame time remaining */
-
-/********************  Bit definition forUSB_OTG_DSTS register  ********************/
-#define USB_OTG_DSTS_SUSPSTS                 0x00000001U            /*!< Suspend status */
-
-#define USB_OTG_DSTS_ENUMSPD                 0x00000006U            /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_DSTS_ENUMSPD_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_DSTS_EERR                    0x00000008U            /*!< Erratic error */
-#define USB_OTG_DSTS_FNSOF                   0x003FFF00U            /*!< Frame number of the received SOF */
-
-/********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/
-#define USB_OTG_GAHBCFG_GINT                    0x00000001U            /*!< Global interrupt mask */
-
-#define USB_OTG_GAHBCFG_HBSTLEN                 0x0000001EU            /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_GAHBCFG_HBSTLEN_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_GAHBCFG_HBSTLEN_2               0x00000008U            /*!<Bit 2 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3               0x00000010U            /*!<Bit 3 */
-#define USB_OTG_GAHBCFG_DMAEN                   0x00000020U            /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL                 0x00000080U            /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL                0x00000100U            /*!< Periodic TxFIFO empty level */
-
-/********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/
-
-#define USB_OTG_GUSBCFG_TOCAL                   0x00000007U            /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TOCAL_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TOCAL_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_PHYSEL                  0x00000040U            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP                  0x00000100U            /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP                  0x00000200U            /*!< HNP-capable */
-
-#define USB_OTG_GUSBCFG_TRDT                    0x00003C00U            /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                  0x00000400U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TRDT_1                  0x00000800U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TRDT_2                  0x00001000U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_TRDT_3                  0x00002000U            /*!<Bit 3 */
-#define USB_OTG_GUSBCFG_PHYLPCS                 0x00008000U            /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS                0x00020000U            /*!< ULPI FS/LS select */
-#define USB_OTG_GUSBCFG_ULPIAR                  0x00040000U            /*!< ULPI Auto-resume */
-#define USB_OTG_GUSBCFG_ULPICSM                 0x00080000U            /*!< ULPI Clock SuspendM */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD              0x00100000U            /*!< ULPI External VBUS Drive */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI              0x00200000U            /*!< ULPI external VBUS indicator */
-#define USB_OTG_GUSBCFG_TSDPS                   0x00400000U            /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI                    0x00800000U            /*!< Indicator complement */
-#define USB_OTG_GUSBCFG_PTCI                    0x01000000U            /*!< Indicator pass through */
-#define USB_OTG_GUSBCFG_ULPIIPD                 0x02000000U            /*!< ULPI interface protect disable */
-#define USB_OTG_GUSBCFG_FHMOD                   0x20000000U            /*!< Forced host mode */
-#define USB_OTG_GUSBCFG_FDMOD                   0x40000000U            /*!< Forced peripheral mode */
-#define USB_OTG_GUSBCFG_CTXPKT                  0x80000000U            /*!< Corrupt Tx packet */
-
-/********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
-#define USB_OTG_GRSTCTL_CSRST                   0x00000001U            /*!< Core soft reset */
-#define USB_OTG_GRSTCTL_HSRST                   0x00000002U            /*!< HCLK soft reset */
-#define USB_OTG_GRSTCTL_FCRST                   0x00000004U            /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH                 0x00000010U            /*!< RxFIFO flush */
-#define USB_OTG_GRSTCTL_TXFFLSH                 0x00000020U            /*!< TxFIFO flush */
-
-#define USB_OTG_GRSTCTL_TXFNUM                  0x000007C0U            /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                0x00000040U            /*!<Bit 0 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                0x00000080U            /*!<Bit 1 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                0x00000100U            /*!<Bit 2 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                0x00000200U            /*!<Bit 3 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                0x00000400U            /*!<Bit 4 */
-#define USB_OTG_GRSTCTL_DMAREQ                  0x40000000U            /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL                  0x80000000U            /*!< AHB master idle */
-
-/********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/
-#define USB_OTG_DIEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPMSK_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPMSK_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPMSK_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPMSK_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPMSK_BIM                     0x00000200U            /*!< BNA interrupt mask */
-
-/********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/
-#define USB_OTG_HPTXSTS_PTXFSAVL                0x0000FFFFU            /*!< Periodic transmit data FIFO space available */
-
-#define USB_OTG_HPTXSTS_PTXQSAV                 0x00FF0000U            /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0               0x00010000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1               0x00020000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2               0x00040000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3               0x00080000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4               0x00100000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5               0x00200000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6               0x00400000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7               0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_HPTXSTS_PTXQTOP                 0xFF000000U            /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0               0x01000000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1               0x02000000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2               0x04000000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3               0x08000000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4               0x10000000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5               0x20000000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6               0x40000000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7               0x80000000U            /*!<Bit 7 */
-
-/********************  Bit definition forUSB_OTG_HAINT register  ********************/
-#define USB_OTG_HAINT_HAINT                   0x0000FFFFU            /*!< Channel interrupts */
-
-/********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/
-#define USB_OTG_DOEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPMSK_STUPM                   0x00000008U            /*!< SETUP phase done mask */
-#define USB_OTG_DOEPMSK_OTEPDM                  0x00000010U            /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received mask */
-#define USB_OTG_DOEPMSK_OPEM                    0x00000100U            /*!< OUT packet error mask */
-#define USB_OTG_DOEPMSK_BOIM                    0x00000200U            /*!< BNA interrupt mask */
-
-/********************  Bit definition forUSB_OTG_GINTSTS register  ********************/
-#define USB_OTG_GINTSTS_CMOD                    0x00000001U            /*!< Current mode of operation */
-#define USB_OTG_GINTSTS_MMIS                    0x00000002U            /*!< Mode mismatch interrupt */
-#define USB_OTG_GINTSTS_OTGINT                  0x00000004U            /*!< OTG interrupt */
-#define USB_OTG_GINTSTS_SOF                     0x00000008U            /*!< Start of frame */
-#define USB_OTG_GINTSTS_RXFLVL                  0x00000010U            /*!< RxFIFO nonempty */
-#define USB_OTG_GINTSTS_NPTXFE                  0x00000020U            /*!< Nonperiodic TxFIFO empty */
-#define USB_OTG_GINTSTS_GINAKEFF                0x00000040U            /*!< Global IN nonperiodic NAK effective */
-#define USB_OTG_GINTSTS_BOUTNAKEFF              0x00000080U            /*!< Global OUT NAK effective */
-#define USB_OTG_GINTSTS_ESUSP                   0x00000400U            /*!< Early suspend */
-#define USB_OTG_GINTSTS_USBSUSP                 0x00000800U            /*!< USB suspend */
-#define USB_OTG_GINTSTS_USBRST                  0x00001000U            /*!< USB reset */
-#define USB_OTG_GINTSTS_ENUMDNE                 0x00002000U            /*!< Enumeration done */
-#define USB_OTG_GINTSTS_ISOODRP                 0x00004000U            /*!< Isochronous OUT packet dropped interrupt */
-#define USB_OTG_GINTSTS_EOPF                    0x00008000U            /*!< End of periodic frame interrupt */
-#define USB_OTG_GINTSTS_IEPINT                  0x00040000U            /*!< IN endpoint interrupt */
-#define USB_OTG_GINTSTS_OEPINT                  0x00080000U            /*!< OUT endpoint interrupt */
-#define USB_OTG_GINTSTS_IISOIXFR                0x00100000U            /*!< Incomplete isochronous IN transfer */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       0x00200000U            /*!< Incomplete periodic transfer */
-#define USB_OTG_GINTSTS_DATAFSUSP               0x00400000U            /*!< Data fetch suspended */
-#define USB_OTG_GINTSTS_HPRTINT                 0x01000000U            /*!< Host port interrupt */
-#define USB_OTG_GINTSTS_HCINT                   0x02000000U            /*!< Host channels interrupt */
-#define USB_OTG_GINTSTS_PTXFE                   0x04000000U            /*!< Periodic TxFIFO empty */
-#define USB_OTG_GINTSTS_CIDSCHG                 0x10000000U            /*!< Connector ID status change */
-#define USB_OTG_GINTSTS_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt */
-#define USB_OTG_GINTSTS_SRQINT                  0x40000000U            /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT                  0x80000000U            /*!< Resume/remote wakeup detected interrupt */
-
-/********************  Bit definition forUSB_OTG_GINTMSK register  ********************/
-#define USB_OTG_GINTMSK_MMISM                   0x00000002U            /*!< Mode mismatch interrupt mask */
-#define USB_OTG_GINTMSK_OTGINT                  0x00000004U            /*!< OTG interrupt mask */
-#define USB_OTG_GINTMSK_SOFM                    0x00000008U            /*!< Start of frame mask */
-#define USB_OTG_GINTMSK_RXFLVLM                 0x00000010U            /*!< Receive FIFO nonempty mask */
-#define USB_OTG_GINTMSK_NPTXFEM                 0x00000020U            /*!< Nonperiodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_GINAKEFFM               0x00000040U            /*!< Global nonperiodic IN NAK effective mask */
-#define USB_OTG_GINTMSK_GONAKEFFM               0x00000080U            /*!< Global OUT NAK effective mask */
-#define USB_OTG_GINTMSK_ESUSPM                  0x00000400U            /*!< Early suspend mask */
-#define USB_OTG_GINTMSK_USBSUSPM                0x00000800U            /*!< USB suspend mask */
-#define USB_OTG_GINTMSK_USBRST                  0x00001000U            /*!< USB reset mask */
-#define USB_OTG_GINTMSK_ENUMDNEM                0x00002000U            /*!< Enumeration done mask */
-#define USB_OTG_GINTMSK_ISOODRPM                0x00004000U            /*!< Isochronous OUT packet dropped interrupt mask */
-#define USB_OTG_GINTMSK_EOPFM                   0x00008000U            /*!< End of periodic frame interrupt mask */
-#define USB_OTG_GINTMSK_EPMISM                  0x00020000U            /*!< Endpoint mismatch interrupt mask */
-#define USB_OTG_GINTMSK_IEPINT                  0x00040000U            /*!< IN endpoints interrupt mask */
-#define USB_OTG_GINTMSK_OEPINT                  0x00080000U            /*!< OUT endpoints interrupt mask */
-#define USB_OTG_GINTMSK_IISOIXFRM               0x00100000U            /*!< Incomplete isochronous IN transfer mask */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         0x00200000U            /*!< Incomplete periodic transfer mask */
-#define USB_OTG_GINTMSK_FSUSPM                  0x00400000U            /*!< Data fetch suspended mask */
-#define USB_OTG_GINTMSK_PRTIM                   0x01000000U            /*!< Host port interrupt mask */
-#define USB_OTG_GINTMSK_HCIM                    0x02000000U            /*!< Host channels interrupt mask */
-#define USB_OTG_GINTMSK_PTXFEM                  0x04000000U            /*!< Periodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_CIDSCHGM                0x10000000U            /*!< Connector ID status change mask */
-#define USB_OTG_GINTMSK_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt mask */
-#define USB_OTG_GINTMSK_SRQIM                   0x40000000U            /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM                    0x80000000U            /*!< Resume/remote wakeup detected interrupt mask */
-
-/********************  Bit definition forUSB_OTG_DAINT register  ********************/
-#define USB_OTG_DAINT_IEPINT                  0x0000FFFFU            /*!< IN endpoint interrupt bits */
-#define USB_OTG_DAINT_OEPINT                  0xFFFF0000U            /*!< OUT endpoint interrupt bits */
-
-/********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/
-#define USB_OTG_HAINTMSK_HAINTM                  0x0000FFFFU            /*!< Channel interrupt mask */
-
-/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
-#define USB_OTG_GRXSTSP_EPNUM                    0x0000000FU            /*!< IN EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_BCNT                     0x00007FF0U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID                     0x00018000U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS                   0x001E0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/
-#define USB_OTG_DAINTMSK_IEPM                    0x0000FFFFU            /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM                    0xFFFF0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for OTG register  ********************/
-
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition for OTG register  ********************/
-
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/
-#define USB_OTG_GRXFSIZ_RXFD                    0x0000FFFFU            /*!< RxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/
-#define USB_OTG_DVBUSDIS_VBUSDT                  0x0000FFFFU            /*!< Device VBUS discharge time */
-
-/********************  Bit definition for OTG register  ********************/
-#define USB_OTG_NPTXFSA                 0x0000FFFFU            /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD                  0xFFFF0000U            /*!< Nonperiodic TxFIFO depth */
-#define USB_OTG_TX0FSA                  0x0000FFFFU            /*!< Endpoint 0 transmit RAM start address */
-#define USB_OTG_TX0FD                   0xFFFF0000U            /*!< Endpoint 0 TxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
-#define USB_OTG_DVBUSPULSE_DVBUSP                  0x00000FFFU            /*!< Device VBUS pulsing time */
-
-/********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/
-#define USB_OTG_GNPTXSTS_NPTXFSAV                0x0000FFFFU            /*!< Nonperiodic TxFIFO space available */
-
-#define USB_OTG_GNPTXSTS_NPTQXSAV                0x00FF0000U            /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0              0x00010000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1              0x00020000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2              0x00040000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3              0x00080000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4              0x00100000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5              0x00200000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6              0x00400000U            /*!<Bit 6 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7              0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_GNPTXSTS_NPTXQTOP                0x7F000000U            /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0              0x01000000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1              0x02000000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2              0x04000000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3              0x08000000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4              0x10000000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5              0x20000000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6              0x40000000U            /*!<Bit 6 */
-
-/********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/
-#define USB_OTG_DTHRCTL_NONISOTHREN             0x00000001U            /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN                0x00000002U            /*!< ISO IN endpoint threshold enable */
-
-#define USB_OTG_DTHRCTL_TXTHRLEN                0x000007FCU            /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0              0x00000004U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1              0x00000008U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2              0x00000010U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3              0x00000020U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4              0x00000040U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5              0x00000080U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6              0x00000100U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7              0x00000200U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8              0x00000400U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_RXTHREN                 0x00010000U            /*!< Receive threshold enable */
-
-#define USB_OTG_DTHRCTL_RXTHRLEN                0x03FE0000U            /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0              0x00020000U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1              0x00040000U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2              0x00080000U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3              0x00100000U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4              0x00200000U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5              0x00400000U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6              0x00800000U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7              0x01000000U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8              0x02000000U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_ARPEN                   0x08000000U            /*!< Arbiter parking enable */
-
-/********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM               0x0000FFFFU            /*!< IN EP Tx FIFO empty interrupt mask bits */
-
-/********************  Bit definition forUSB_OTG_DEACHINT register  ********************/
-#define USB_OTG_DEACHINT_IEP1INT                 0x00000002U            /*!< IN endpoint 1interrupt bit */
-#define USB_OTG_DEACHINT_OEP1INT                 0x00020000U            /*!< OUT endpoint 1 interrupt bit */
-
-/********************  Bit definition forUSB_OTG_GCCFG register  ********************/
-#define USB_OTG_GCCFG_PWRDWN                  0x00010000U            /*!< Power down */
-#define USB_OTG_GCCFG_I2CPADEN                0x00020000U            /*!< Enable I2C bus connection for the external I2C PHY interface */
-#define USB_OTG_GCCFG_VBUSASEN                0x00040000U            /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_VBUSBSEN                0x00080000U            /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_SOFOUTEN                0x00100000U            /*!< SOF output enable */
-#define USB_OTG_GCCFG_NOVBUSSENS              0x00200000U            /*!< VBUS sensing disable option */
-
-/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
-#define USB_OTG_DEACHINTMSK_IEP1INTM                0x00000002U            /*!< IN Endpoint 1 interrupt mask bit */
-#define USB_OTG_DEACHINTMSK_OEP1INTM                0x00020000U            /*!< OUT Endpoint 1 interrupt mask bit */
-
-/********************  Bit definition forUSB_OTG_CID register  ********************/
-#define USB_OTG_CID_PRODUCT_ID              0xFFFFFFFFU            /*!< Product ID field */
-
-/********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/
-#define USB_OTG_DIEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPEACHMSK1_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
-
-/********************  Bit definition forUSB_OTG_HPRT register  ********************/
-#define USB_OTG_HPRT_PCSTS                   0x00000001U            /*!< Port connect status */
-#define USB_OTG_HPRT_PCDET                   0x00000002U            /*!< Port connect detected */
-#define USB_OTG_HPRT_PENA                    0x00000004U            /*!< Port enable */
-#define USB_OTG_HPRT_PENCHNG                 0x00000008U            /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA                    0x00000010U            /*!< Port overcurrent active */
-#define USB_OTG_HPRT_POCCHNG                 0x00000020U            /*!< Port overcurrent change */
-#define USB_OTG_HPRT_PRES                    0x00000040U            /*!< Port resume */
-#define USB_OTG_HPRT_PSUSP                   0x00000080U            /*!< Port suspend */
-#define USB_OTG_HPRT_PRST                    0x00000100U            /*!< Port reset */
-
-#define USB_OTG_HPRT_PLSTS                   0x00000C00U            /*!< Port line status */
-#define USB_OTG_HPRT_PLSTS_0                 0x00000400U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PLSTS_1                 0x00000800U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PPWR                    0x00001000U            /*!< Port power */
-
-#define USB_OTG_HPRT_PTCTL                   0x0001E000U            /*!< Port test control */
-#define USB_OTG_HPRT_PTCTL_0                 0x00002000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PTCTL_1                 0x00004000U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PTCTL_2                 0x00008000U            /*!<Bit 2 */
-#define USB_OTG_HPRT_PTCTL_3                 0x00010000U            /*!<Bit 3 */
-
-#define USB_OTG_HPRT_PSPD                    0x00060000U            /*!< Port speed */
-#define USB_OTG_HPRT_PSPD_0                  0x00020000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PSPD_1                  0x00040000U            /*!<Bit 1 */
-
-/********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/
-#define USB_OTG_DOEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DOEPEACHMSK1_TXFURM                  0x00000100U            /*!< OUT packet error mask */
-#define USB_OTG_DOEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_BERRM                   0x00001000U            /*!< Bubble error interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NYETM                   0x00004000U            /*!< NYET interrupt mask */
-
-/********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/
-#define USB_OTG_HPTXFSIZ_PTXSA                   0x0000FFFFU            /*!< Host periodic TxFIFO start address */
-#define USB_OTG_HPTXFSIZ_PTXFD                   0xFFFF0000U            /*!< Host periodic TxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/
-#define USB_OTG_DIEPCTL_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
-#define USB_OTG_DIEPCTL_USBAEP                  0x00008000U            /*!< USB active endpoint */
-#define USB_OTG_DIEPCTL_EONUM_DPID              0x00010000U            /*!< Even/odd frame */
-#define USB_OTG_DIEPCTL_NAKSTS                  0x00020000U            /*!< NAK status */
-
-#define USB_OTG_DIEPCTL_EPTYP                   0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_DIEPCTL_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_STALL                   0x00200000U            /*!< STALL handshake */
-
-#define USB_OTG_DIEPCTL_TXFNUM                  0x03C00000U            /*!< TxFIFO number */
-#define USB_OTG_DIEPCTL_TXFNUM_0                0x00400000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                0x00800000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                0x01000000U            /*!<Bit 2 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                0x02000000U            /*!<Bit 3 */
-#define USB_OTG_DIEPCTL_CNAK                    0x04000000U            /*!< Clear NAK */
-#define USB_OTG_DIEPCTL_SNAK                    0x08000000U            /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          0x10000000U            /*!< Set DATA0 PID */
-#define USB_OTG_DIEPCTL_SODDFRM                 0x20000000U            /*!< Set odd frame */
-#define USB_OTG_DIEPCTL_EPDIS                   0x40000000U            /*!< Endpoint disable */
-#define USB_OTG_DIEPCTL_EPENA                   0x80000000U            /*!< Endpoint enable */
-
-/********************  Bit definition forUSB_OTG_HCCHAR register  ********************/
-#define USB_OTG_HCCHAR_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
-
-#define USB_OTG_HCCHAR_EPNUM                   0x00007800U            /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPNUM_1                 0x00001000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_EPNUM_2                 0x00002000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_EPNUM_3                 0x00004000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_EPDIR                   0x00008000U            /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV                   0x00020000U            /*!< Low-speed device */
-
-#define USB_OTG_HCCHAR_EPTYP                   0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_MC                      0x00300000U            /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                    0x00100000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_MC_1                    0x00200000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_DAD                     0x1FC00000U            /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                   0x00400000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_DAD_1                   0x00800000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_DAD_2                   0x01000000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_DAD_3                   0x02000000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_DAD_4                   0x04000000U            /*!<Bit 4 */
-#define USB_OTG_HCCHAR_DAD_5                   0x08000000U            /*!<Bit 5 */
-#define USB_OTG_HCCHAR_DAD_6                   0x10000000U            /*!<Bit 6 */
-#define USB_OTG_HCCHAR_ODDFRM                  0x20000000U            /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS                   0x40000000U            /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA                   0x80000000U            /*!< Channel enable */
-
-/********************  Bit definition forUSB_OTG_HCSPLT register  ********************/
-
-#define USB_OTG_HCSPLT_PRTADDR                 0x0000007FU            /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_PRTADDR_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_PRTADDR_2               0x00000004U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_PRTADDR_3               0x00000008U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_PRTADDR_4               0x00000010U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_PRTADDR_5               0x00000020U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_PRTADDR_6               0x00000040U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_HUBADDR                 0x00003F80U            /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0               0x00000080U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_HUBADDR_1               0x00000100U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_HUBADDR_2               0x00000200U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_HUBADDR_3               0x00000400U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_HUBADDR_4               0x00000800U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_HUBADDR_5               0x00001000U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_HUBADDR_6               0x00002000U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_XACTPOS                 0x0000C000U            /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0               0x00004000U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_XACTPOS_1               0x00008000U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_COMPLSPLT               0x00010000U            /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN                 0x80000000U            /*!< Split enable */
-
-/********************  Bit definition forUSB_OTG_HCINT register  ********************/
-#define USB_OTG_HCINT_XFRC                    0x00000001U            /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH                     0x00000002U            /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINT_STALL                   0x00000008U            /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK                     0x00000010U            /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK                     0x00000020U            /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET                    0x00000040U            /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR                   0x00000080U            /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR                   0x00000100U            /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR                   0x00000200U            /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR                   0x00000400U            /*!< Data toggle error */
-
-/********************  Bit definition forUSB_OTG_DIEPINT register  ********************/
-#define USB_OTG_DIEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_TOC                     0x00000008U            /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE                  0x00000010U            /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNE                  0x00000040U            /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE                    0x00000080U            /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN              0x00000100U            /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA                     0x00000200U            /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS               0x00000800U            /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR                    0x00001000U            /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK                     0x00002000U            /*!< NAK interrupt */
-
-/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
-#define USB_OTG_HCINTMSK_XFRCM                   0x00000001U            /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM                    0x00000002U            /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM                  0x00000008U            /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM                    0x00000010U            /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM                    0x00000020U            /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET                    0x00000040U            /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM                  0x00000080U            /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM                  0x00000100U            /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM                  0x00000200U            /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM                  0x00000400U            /*!< Data toggle error mask */
-
-/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
-
-#define USB_OTG_DIEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT                  0x60000000U            /*!< Packet count */
-/********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/
-#define USB_OTG_HCTSIZ_XFRSIZ                    0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT                    0x1FF80000U            /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING                    0x80000000U            /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID                      0x60000000U            /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                    0x20000000U            /*!<Bit 0 */
-#define USB_OTG_HCTSIZ_DPID_1                    0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/
-#define USB_OTG_DIEPDMA_DMAADDR                  0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition forUSB_OTG_HCDMA register  ********************/
-#define USB_OTG_HCDMA_DMAADDR                    0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/
-#define USB_OTG_DTXFSTS_INEPTFSAV                0x0000FFFFU            /*!< IN endpoint TxFIFO space avail */
-
-/********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/
-#define USB_OTG_DIEPTXF_INEPTXSA                 0x0000FFFFU            /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD                 0xFFFF0000U            /*!< IN endpoint TxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/
-
-#define USB_OTG_DOEPCTL_MPSIZ                     0x000007FFU            /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP                    0x00008000U            /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS                    0x00020000U            /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            0x10000000U            /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM                   0x20000000U            /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP                     0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                   0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DOEPCTL_EPTYP_1                   0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_SNPM                      0x00100000U            /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL                     0x00200000U            /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK                      0x04000000U            /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK                      0x08000000U            /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS                     0x40000000U            /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA                     0x80000000U            /*!< Endpoint enable */
-
-/********************  Bit definition forUSB_OTG_DOEPINT register  ********************/
-#define USB_OTG_DOEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_STUP                    0x00000008U            /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS                 0x00000010U            /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_NYET                    0x00004000U            /*!< NYET interrupt */
-
-/********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/
-
-#define USB_OTG_DOEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-
-#define USB_OTG_DOEPTSIZ_STUPCNT                 0x60000000U            /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0               0x20000000U            /*!<Bit 0 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1               0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition for PCGCCTL register  ********************/
-#define USB_OTG_PCGCCTL_STOPCLK                 0x00000001U            /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK                 0x00000002U            /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP                 0x00000010U            /*!<Bit 1 */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
- 
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
- 
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************** DMA Instances *******************************/
-#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
-                                              ((INSTANCE) == DMA1_Stream1) || \
-                                              ((INSTANCE) == DMA1_Stream2) || \
-                                              ((INSTANCE) == DMA1_Stream3) || \
-                                              ((INSTANCE) == DMA1_Stream4) || \
-                                              ((INSTANCE) == DMA1_Stream5) || \
-                                              ((INSTANCE) == DMA1_Stream6) || \
-                                              ((INSTANCE) == DMA1_Stream7) || \
-                                              ((INSTANCE) == DMA2_Stream0) || \
-                                              ((INSTANCE) == DMA2_Stream1) || \
-                                              ((INSTANCE) == DMA2_Stream2) || \
-                                              ((INSTANCE) == DMA2_Stream3) || \
-                                              ((INSTANCE) == DMA2_Stream4) || \
-                                              ((INSTANCE) == DMA2_Stream5) || \
-                                              ((INSTANCE) == DMA2_Stream6) || \
-                                              ((INSTANCE) == DMA2_Stream7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOH))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2) || \
-                                       ((INSTANCE) == I2C3))
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI2) || \
-                                    ((INSTANCE) == SPI3))
-
-/*************************** I2S Extended Instances ***************************/
-#define IS_I2S_ALL_INSTANCE_EXT(PERIPH)  (((INSTANCE) == SPI2)    || \
-                                          ((INSTANCE) == SPI3)    || \
-                                          ((INSTANCE) == I2S2ext) || \
-                                          ((INSTANCE) == I2S3ext))
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3) || \
-                                       ((INSTANCE) == SPI4))
-
-/*************************** SPI Extended Instances ***************************/
-#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1)    || \
-                                           ((INSTANCE) == SPI2)    || \
-                                           ((INSTANCE) == SPI3)    || \
-                                           ((INSTANCE) == I2S2ext) || \
-                                           ((INSTANCE) == I2S3ext))
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
-                                   ((INSTANCE) == TIM2)   || \
-                                   ((INSTANCE) == TIM3)   || \
-                                   ((INSTANCE) == TIM4)   || \
-                                   ((INSTANCE) == TIM5)   || \
-                                   ((INSTANCE) == TIM9)   || \
-                                   ((INSTANCE) == TIM10)  || \
-                                   ((INSTANCE) == TIM11))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
-                                         ((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM9)  || \
-                                         ((INSTANCE) == TIM10) || \
-                                         ((INSTANCE) == TIM11))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM9))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5))
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5))
-
-/******************** TIM Instances : Advanced-control timers *****************/
-#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5))
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5))
-
-/************ TIM Instances : DMA requests generation (COMDE) *****************/
-#define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5)) 
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                             ((INSTANCE) == TIM2) || \
-                                             ((INSTANCE) == TIM3) || \
-                                             ((INSTANCE) == TIM4) || \
-                                             ((INSTANCE) == TIM5))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM9))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM9))
-
-/********************** TIM Instances : 32 bit Counter ************************/
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
-                                              ((INSTANCE) == TIM5))
-
-/***************** TIM Instances : external trigger input availabe ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                        ((INSTANCE) == TIM2) || \
-                                        ((INSTANCE) == TIM3) || \
-                                        ((INSTANCE) == TIM4) || \
-                                        ((INSTANCE) == TIM5))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM11))
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM1) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM5) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-/************ TIM Instances : complementary output(s) available ***************/
-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
-   ((((INSTANCE) == TIM1) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3))))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART6))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART6))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART6))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART6))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART6))     
-
-
-/*********************** PCD Instances ****************************************/
-#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
-
-/*********************** HCD Instances ****************************************/
-#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/****************************** SDIO Instances ********************************/
-#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
-
-/****************************** USB Exported Constants ************************/
-#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                8U
-#define USB_OTG_FS_MAX_IN_ENDPOINTS                    4U    /* Including EP0 */
-#define USB_OTG_FS_MAX_OUT_ENDPOINTS                   4U    /* Including EP0 */
-#define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32F401xE_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/cmsis/stm32f405xx.h b/stmhal/cmsis/stm32f405xx.h
deleted file mode 100644
index a28184546a..0000000000
--- a/stmhal/cmsis/stm32f405xx.h
+++ /dev/null
@@ -1,7491 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f405xx.h
-  * @author  MCD Application Team
-  * @version V2.5.1
-  * @date    28-June-2016
-  * @brief   CMSIS STM32F405xx Device Peripheral Access Layer Header File.
-  *
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - peripherals registers declarations and bits definition
-  *           - Macros to access peripheral’s registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f405xx
-  * @{
-  */
-    
-#ifndef __STM32F405xx_H
-#define __STM32F405xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-  
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-
-/**
-  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
-  */
-#define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */
-#define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */
-#define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1U       /*!< FPU present                                   */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32F4XX Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-typedef enum
-{
-/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
-  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
-/******  STM32 specific Interrupt Numbers **********************************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
-  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
-  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
-  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
-  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
-  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
-  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
-  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
-  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
-  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
-  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
-  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
-  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
-  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
-  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
-  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
-  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
-  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */    
-  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
-  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
-  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
-  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
-  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
-  FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                             */
-  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
-  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
-  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
-  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
-  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
-  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
-  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
-  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
-  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
-  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
-  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
-  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
-  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
-  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
-  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
-  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
-  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
-  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
-  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
-  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
-  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
-  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
-  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
-  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
-  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
-  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
-  HASH_RNG_IRQn               = 80,     /*!< Hash and RNG global interrupt                                     */
-  FPU_IRQn                    = 81      /*!< FPU global interrupt                                              */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
-#include "system_stm32f4xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */      
-  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
-  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
-  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
-  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
-  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
-  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
-  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
-  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
-  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
-  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
-  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
-  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
-  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
-  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
-  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
-                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
-} ADC_Common_TypeDef;
-
-
-/** 
-  * @brief Controller Area Network TxMailBox 
-  */
-
-typedef struct
-{
-  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
-  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
-  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
-  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
-} CAN_TxMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FIFOMailBox 
-  */
-  
-typedef struct
-{
-  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
-  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
-  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
-  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
-} CAN_FIFOMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FilterRegister 
-  */
-  
-typedef struct
-{
-  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
-  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
-} CAN_FilterRegister_TypeDef;
-
-/** 
-  * @brief Controller Area Network 
-  */
-  
-typedef struct
-{
-  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
-  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
-  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
-  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
-  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
-  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
-  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
-  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
-  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
-  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
-  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
-  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
-  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
-  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
-  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
-  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
-  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
-  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
-  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
-  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
-  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */ 
-  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
-} CAN_TypeDef;
-
-/** 
-  * @brief CRC calculation unit 
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
-  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */
-  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
-  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
-  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
-  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
-  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
-  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
-  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
-  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
-  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
-  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
-  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
-  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
-  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
-  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
-  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
-  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
-  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
-  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
-  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
-  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
-  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
-  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
-  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
-} DMA_Stream_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
-  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
-  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
-  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
-} DMA_TypeDef;
-
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
-  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
-  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
-  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
-  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
-  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-
-typedef struct
-{
-  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */
-  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */
-  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */
-  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */
-  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */
-  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */
-} FLASH_TypeDef;
-
-
-/** 
-  * @brief Flexible Static Memory Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */   
-} FSMC_Bank1_TypeDef; 
-
-/** 
-  * @brief Flexible Static Memory Controller Bank1E
-  */
-  
-typedef struct
-{
-  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
-} FSMC_Bank1E_TypeDef;
-
-/** 
-  * @brief Flexible Static Memory Controller Bank2
-  */
-  
-typedef struct
-{
-  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */
-  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */
-  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */
-  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
-  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */
-  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */
-  uint32_t      RESERVED1;  /*!< Reserved, 0x78                                                            */
-  uint32_t      RESERVED2;  /*!< Reserved, 0x7C                                                            */
-  __IO uint32_t PCR3;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */
-  __IO uint32_t SR3;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */
-  __IO uint32_t PMEM3;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */
-  __IO uint32_t PATT3;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
-  uint32_t      RESERVED3;  /*!< Reserved, 0x90                                                            */
-  __IO uint32_t ECCR3;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */
-} FSMC_Bank2_3_TypeDef;
-
-/** 
-  * @brief Flexible Static Memory Controller Bank4
-  */
-  
-typedef struct
-{
-  __IO uint32_t PCR4;       /*!< PC Card  control register 4,                       Address offset: 0xA0 */
-  __IO uint32_t SR4;        /*!< PC Card  FIFO status and interrupt register 4,     Address offset: 0xA4 */
-  __IO uint32_t PMEM4;      /*!< PC Card  Common memory space timing register 4,    Address offset: 0xA8 */
-  __IO uint32_t PATT4;      /*!< PC Card  Attribute memory space timing register 4, Address offset: 0xAC */
-  __IO uint32_t PIO4;       /*!< PC Card  I/O space timing register 4,              Address offset: 0xB0 */
-} FSMC_Bank4_TypeDef; 
-
-
-/** 
-  * @brief General Purpose I/O
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
-  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
-  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
-  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
-  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
-  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
-  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
-  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/** 
-  * @brief System configuration controller
-  */
-  
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */ 
-  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */
-  __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */
-  __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */
-  __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */
-  __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */
-  __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
-  __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
-  __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
-  __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
-  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
-  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
-  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
-  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
-  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
-  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
-  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
-  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
-  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
-  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
-  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
-  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
-  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
-  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
-  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
-  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
-  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
-  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
-  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
-  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
-  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
-
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-
-typedef struct
-{
-  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
-  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
-  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
-  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
-  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
-  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
-  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */
-  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
-  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */
-  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
-  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */
-  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */
-  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */
-  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */
-  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
-  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */
-  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
-  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
-  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
-  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
-  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
-  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
-  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
-  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
-  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
-  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
-  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
-  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
-  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
-  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
-  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
-  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
-  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
-  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
-  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
-  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
-  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
-} RTC_TypeDef;
-
-
-/** 
-  * @brief SD host Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t POWER;          /*!< SDIO power control register,    Address offset: 0x00 */
-  __IO uint32_t CLKCR;          /*!< SDI clock control register,     Address offset: 0x04 */
-  __IO uint32_t ARG;            /*!< SDIO argument register,         Address offset: 0x08 */
-  __IO uint32_t CMD;            /*!< SDIO command register,          Address offset: 0x0C */
-  __I uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */
-  __I uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */
-  __I uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */
-  __I uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */
-  __I uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */
-  __IO uint32_t DTIMER;         /*!< SDIO data timer register,       Address offset: 0x24 */
-  __IO uint32_t DLEN;           /*!< SDIO data length register,      Address offset: 0x28 */
-  __IO uint32_t DCTRL;          /*!< SDIO data control register,     Address offset: 0x2C */
-  __I uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */
-  __I uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */
-  __IO uint32_t ICR;            /*!< SDIO interrupt clear register,  Address offset: 0x38 */
-  __IO uint32_t MASK;           /*!< SDIO mask register,             Address offset: 0x3C */
-  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
-  __I uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */
-  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
-  __IO uint32_t FIFO;           /*!< SDIO data FIFO register,        Address offset: 0x80 */
-} SDIO_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
-  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
-  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
-  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-
-/** 
-  * @brief RNG
-  */
-  
-typedef struct 
-{
-  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
-  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
-  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
-} RNG_TypeDef;
-
-
- 
-/** 
-  * @brief __USB_OTG_Core_register
-  */
-typedef struct
-{
-  __IO uint32_t GOTGCTL;              /*!<  USB_OTG Control and Status Register    Address offset : 0x00      */
-  __IO uint32_t GOTGINT;              /*!<  USB_OTG Interrupt Register             Address offset : 0x04      */
-  __IO uint32_t GAHBCFG;              /*!<  Core AHB Configuration Register        Address offset : 0x08      */
-  __IO uint32_t GUSBCFG;              /*!<  Core USB Configuration Register        Address offset : 0x0C      */
-  __IO uint32_t GRSTCTL;              /*!<  Core Reset Register                    Address offset : 0x10      */
-  __IO uint32_t GINTSTS;              /*!<  Core Interrupt Register                Address offset : 0x14      */
-  __IO uint32_t GINTMSK;              /*!<  Core Interrupt Mask Register           Address offset : 0x18      */
-  __IO uint32_t GRXSTSR;              /*!<  Receive Sts Q Read Register            Address offset : 0x1C      */
-  __IO uint32_t GRXSTSP;              /*!<  Receive Sts Q Read & POP Register      Address offset : 0x20      */
-  __IO uint32_t GRXFSIZ;              /* Receive FIFO Size Register                Address offset : 0x24      */
-  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!<  EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28    */
-  __IO uint32_t HNPTXSTS;             /*!<  Non Periodic Tx FIFO/Queue Sts reg     Address offset : 0x2C      */
-  uint32_t Reserved30[2];             /* Reserved                                  Address offset : 0x30      */
-  __IO uint32_t GCCFG;                /*!<  General Purpose IO Register            Address offset : 0x38      */
-  __IO uint32_t CID;                  /*!< User ID Register                          Address offset : 0x3C      */
-  uint32_t  Reserved40[48];           /*!< Reserved                                  Address offset : 0x40-0xFF */
-  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg            Address offset : 0x100 */
-  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */
-}
-USB_OTG_GlobalTypeDef;
-
-
-
-/** 
-  * @brief __device_Registers
-  */
-typedef struct 
-{
-  __IO uint32_t DCFG;         /*!< dev Configuration Register   Address offset : 0x800 */
-  __IO uint32_t DCTL;         /*!< dev Control Register         Address offset : 0x804 */
-  __IO uint32_t DSTS;         /*!< dev Status Register (RO)     Address offset : 0x808 */
-  uint32_t Reserved0C;        /*!< Reserved                     Address offset : 0x80C */
-  __IO uint32_t DIEPMSK;      /* !< dev IN Endpoint Mask        Address offset : 0x810 */
-  __IO uint32_t DOEPMSK;      /*!< dev OUT Endpoint Mask        Address offset : 0x814 */
-  __IO uint32_t DAINT;        /*!< dev All Endpoints Itr Reg    Address offset : 0x818 */
-  __IO uint32_t DAINTMSK;     /*!< dev All Endpoints Itr Mask   Address offset : 0x81C */
-  uint32_t  Reserved20;       /*!< Reserved                     Address offset : 0x820 */
-  uint32_t Reserved9;         /*!< Reserved                     Address offset : 0x824 */
-  __IO uint32_t DVBUSDIS;     /*!< dev VBUS discharge Register  Address offset : 0x828 */
-  __IO uint32_t DVBUSPULSE;   /*!< dev VBUS Pulse Register      Address offset : 0x82C */
-  __IO uint32_t DTHRCTL;      /*!< dev thr                      Address offset : 0x830 */
-  __IO uint32_t DIEPEMPMSK;   /*!< dev empty msk                Address offset : 0x834 */
-  __IO uint32_t DEACHINT;     /*!< dedicated EP interrupt       Address offset : 0x838 */
-  __IO uint32_t DEACHMSK;     /*!< dedicated EP msk             Address offset : 0x83C */  
-  uint32_t Reserved40;        /*!< dedicated EP mask            Address offset : 0x840 */
-  __IO uint32_t DINEP1MSK;    /*!< dedicated EP mask            Address offset : 0x844 */
-  uint32_t  Reserved44[15];   /*!< Reserved                     Address offset : 0x844-0x87C */
-  __IO uint32_t DOUTEP1MSK;   /*!< dedicated EP msk             Address offset : 0x884 */   
-}
-USB_OTG_DeviceTypeDef;
-
-
-/** 
-  * @brief __IN_Endpoint-Specific_Register
-  */
-typedef struct 
-{
-  __IO uint32_t DIEPCTL;        /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h     */
-  uint32_t Reserved04;          /* Reserved                       900h + (ep_num * 20h) + 04h  */
-  __IO uint32_t DIEPINT;        /* dev IN Endpoint Itr Reg     900h + (ep_num * 20h) + 08h     */
-  uint32_t Reserved0C;          /* Reserved                       900h + (ep_num * 20h) + 0Ch  */
-  __IO uint32_t DIEPTSIZ;       /* IN Endpoint Txfer Size   900h + (ep_num * 20h) + 10h        */
-  __IO uint32_t DIEPDMA;        /* IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h  */
-  __IO uint32_t DTXFSTS;        /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h   */
-  uint32_t Reserved18;           /* Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
-}
-USB_OTG_INEndpointTypeDef;
-
-
-/** 
-  * @brief __OUT_Endpoint-Specific_Registers
-  */
-typedef struct 
-{
-  __IO uint32_t DOEPCTL;       /* dev OUT Endpoint Control Reg  B00h + (ep_num * 20h) + 00h*/
-  uint32_t Reserved04;         /* Reserved                      B00h + (ep_num * 20h) + 04h*/
-  __IO uint32_t DOEPINT;       /* dev OUT Endpoint Itr Reg      B00h + (ep_num * 20h) + 08h*/
-  uint32_t Reserved0C;         /* Reserved                      B00h + (ep_num * 20h) + 0Ch*/
-  __IO uint32_t DOEPTSIZ;      /* dev OUT Endpoint Txfer Size   B00h + (ep_num * 20h) + 10h*/
-  __IO uint32_t DOEPDMA;       /* dev OUT Endpoint DMA Address  B00h + (ep_num * 20h) + 14h*/
-  uint32_t Reserved18[2];      /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
-}
-USB_OTG_OUTEndpointTypeDef;
-
-
-/** 
-  * @brief __Host_Mode_Register_Structures
-  */
-typedef struct 
-{
-  __IO uint32_t HCFG;             /* Host Configuration Register    400h*/
-  __IO uint32_t HFIR;             /* Host Frame Interval Register   404h*/
-  __IO uint32_t HFNUM;            /* Host Frame Nbr/Frame Remaining 408h*/
-  uint32_t Reserved40C;           /* Reserved                       40Ch*/
-  __IO uint32_t HPTXSTS;          /* Host Periodic Tx FIFO/ Queue Status 410h*/
-  __IO uint32_t HAINT;            /* Host All Channels Interrupt Register 414h*/
-  __IO uint32_t HAINTMSK;         /* Host All Channels Interrupt Mask 418h*/
-}
-USB_OTG_HostTypeDef;
-
-
-/** 
-  * @brief __Host_Channel_Specific_Registers
-  */
-typedef struct
-{
-  __IO uint32_t HCCHAR;
-  __IO uint32_t HCSPLT;
-  __IO uint32_t HCINT;
-  __IO uint32_t HCINTMSK;
-  __IO uint32_t HCTSIZ;
-  __IO uint32_t HCDMA;
-  uint32_t Reserved[2];
-}
-USB_OTG_HostChannelTypeDef;
-
-    
-/** 
-  * @brief Peripheral_memory_map
-  */
-#define FLASH_BASE            0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region                         */
-#define CCMDATARAM_BASE       0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
-#define SRAM1_BASE            0x20000000U /*!< SRAM1(112 KB) base address in the alias region                             */
-#define SRAM2_BASE            0x2001C000U /*!< SRAM2(16 KB) base address in the alias region                              */
-#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region                                */
-#define BKPSRAM_BASE          0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region                         */
-#define FSMC_R_BASE           0xA0000000U /*!< FSMC registers base address                                                */
-#define SRAM1_BB_BASE         0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region                             */
-#define SRAM2_BB_BASE         0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region                              */
-#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region                                */
-#define BKPSRAM_BB_BASE       0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region                         */
-#define FLASH_END             0x080FFFFFU /*!< FLASH end address */
-#define CCMDATARAM_END        0x1000FFFFU /*!< CCM data RAM end address */
-
-/* Legacy defines */
-#define SRAM_BASE             SRAM1_BASE
-#define SRAM_BB_BASE          SRAM1_BB_BASE
-
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000U)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)
-#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800U)
-#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00U)
-#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000U)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)
-#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400U)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)
-#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000U)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800U)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00U)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x5000U)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)
-#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)
-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)
-#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800U)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)
-
-/*!< APB2 peripherals */
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000U)
-#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400U)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x1000U)
-#define USART6_BASE           (APB2PERIPH_BASE + 0x1400U)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000U)
-#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100U)
-#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200U)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x2300U)
-#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00U)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800U)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00U)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000U)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400U)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800U)
-
-/*!< AHB1 peripherals */
-#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000U)
-#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400U)
-#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800U)
-#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00U)
-#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000U)
-#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400U)
-#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800U)
-#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00U)
-#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000U)
-#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)
-#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800U)
-#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00U)
-#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000U)
-#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010U)
-#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028U)
-#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040U)
-#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058U)
-#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070U)
-#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088U)
-#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0U)
-#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8U)
-#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400U)
-#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010U)
-#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028U)
-#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040U)
-#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058U)
-#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070U)
-#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088U)
-#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0U)
-#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)
-
-/*!< AHB2 peripherals */
-#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800U)
-
-/*!< FSMC Bankx registers base address */
-#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000U)
-#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104U)
-#define FSMC_Bank2_3_R_BASE   (FSMC_R_BASE + 0x0060U)
-#define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0U)
-
-/* Debug MCU registers base address */
-#define DBGMCU_BASE           0xE0042000U
-
-/*!< USB registers base address */
-#define USB_OTG_HS_PERIPH_BASE               0x40040000U
-#define USB_OTG_FS_PERIPH_BASE               0x50000000U
-
-#define USB_OTG_GLOBAL_BASE                  0x000U
-#define USB_OTG_DEVICE_BASE                  0x800U
-#define USB_OTG_IN_ENDPOINT_BASE             0x900U
-#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U
-#define USB_OTG_EP_REG_SIZE                  0x20U
-#define USB_OTG_HOST_BASE                    0x400U
-#define USB_OTG_HOST_PORT_BASE               0x440U
-#define USB_OTG_HOST_CHANNEL_BASE            0x500U
-#define USB_OTG_HOST_CHANNEL_SIZE            0x20U
-#define USB_OTG_PCGCCTL_BASE                 0xE00U
-#define USB_OTG_FIFO_BASE                    0x1000U
-#define USB_OTG_FIFO_SIZE                    0x1000U
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
-#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
-#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define UART4               ((USART_TypeDef *) UART4_BASE)
-#define UART5               ((USART_TypeDef *) UART5_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
-#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
-#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
-#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define USART6              ((USART_TypeDef *) USART6_BASE)
-#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
-#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
-#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE) 
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
-#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
-#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
-#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
-#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
-#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
-#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
-#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
-#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
-#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
-#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
-#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
-#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
-#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
-#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)  
-#define RNG                 ((RNG_TypeDef *) RNG_BASE)
-#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
-#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
-#define FSMC_Bank2_3        ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)
-#define FSMC_Bank4          ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
-
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
-#define USB_OTG_HS          ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers_Bits_Definition               */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Analog to Digital Converter                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          0x00000001U       /*!<Analog watchdog flag */
-#define  ADC_SR_EOC                          0x00000002U       /*!<End of conversion */
-#define  ADC_SR_JEOC                         0x00000004U       /*!<Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        0x00000008U       /*!<Injected channel Start flag */
-#define  ADC_SR_STRT                         0x00000010U       /*!<Regular channel Start flag */
-#define  ADC_SR_OVR                          0x00000020U       /*!<Overrun flag */
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
-#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels */
-#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels */
-#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution) */
-#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
-  
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion */
-#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode */
-#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC) */
-#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection */
-#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment */
-#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      0xFFFFU            /*!<Injected data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag */
-#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion */
-#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag */
-#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag */
-#define  ADC_CSR_OVR1                        0x00000020U        /*!<ADC1 DMA overrun  flag */
-#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag */
-#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion */
-#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag */
-#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag */
-#define  ADC_CSR_OVR2                        0x00002000U        /*!<ADC2 DMA overrun  flag */
-#define  ADC_CSR_AWD3                        0x00010000U        /*!<ADC3 Analog watchdog flag */
-#define  ADC_CSR_EOC3                        0x00020000U        /*!<ADC3 End of conversion */
-#define  ADC_CSR_JEOC3                       0x00040000U        /*!<ADC3 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT3                      0x00080000U        /*!<ADC3 Injected channel Start flag */
-#define  ADC_CSR_STRT3                       0x00100000U        /*!<ADC3 Regular channel Start flag */
-#define  ADC_CSR_OVR3                        0x00200000U        /*!<ADC3 DMA overrun  flag */
-
-/* Legacy defines */
-#define  ADC_CSR_DOVR1                        ADC_CSR_OVR1
-#define  ADC_CSR_DOVR2                        ADC_CSR_OVR2
-#define  ADC_CSR_DOVR3                        ADC_CSR_OVR3
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
-#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
-#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
-#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
-#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
-
-/*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                      0x0000FFFFU         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                      0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Controller Area Network                            */
-/*                                                                            */
-/******************************************************************************/
-/*!<CAN control and status registers */
-/*******************  Bit definition for CAN_MCR register  ********************/
-#define  CAN_MCR_INRQ                        0x00000001U        /*!<Initialization Request */
-#define  CAN_MCR_SLEEP                       0x00000002U        /*!<Sleep Mode Request */
-#define  CAN_MCR_TXFP                        0x00000004U        /*!<Transmit FIFO Priority */
-#define  CAN_MCR_RFLM                        0x00000008U        /*!<Receive FIFO Locked Mode */
-#define  CAN_MCR_NART                        0x00000010U        /*!<No Automatic Retransmission */
-#define  CAN_MCR_AWUM                        0x00000020U        /*!<Automatic Wakeup Mode */
-#define  CAN_MCR_ABOM                        0x00000040U        /*!<Automatic Bus-Off Management */
-#define  CAN_MCR_TTCM                        0x00000080U        /*!<Time Triggered Communication Mode */
-#define  CAN_MCR_RESET                       0x00008000U        /*!<bxCAN software master reset */
-#define  CAN_MCR_DBF                         0x00010000U        /*!<bxCAN Debug freeze */
-/*******************  Bit definition for CAN_MSR register  ********************/
-#define  CAN_MSR_INAK                        0x0001U            /*!<Initialization Acknowledge */
-#define  CAN_MSR_SLAK                        0x0002U            /*!<Sleep Acknowledge */
-#define  CAN_MSR_ERRI                        0x0004U            /*!<Error Interrupt */
-#define  CAN_MSR_WKUI                        0x0008U            /*!<Wakeup Interrupt */
-#define  CAN_MSR_SLAKI                       0x0010U            /*!<Sleep Acknowledge Interrupt */
-#define  CAN_MSR_TXM                         0x0100U            /*!<Transmit Mode */
-#define  CAN_MSR_RXM                         0x0200U            /*!<Receive Mode */
-#define  CAN_MSR_SAMP                        0x0400U            /*!<Last Sample Point */
-#define  CAN_MSR_RX                          0x0800U            /*!<CAN Rx Signal */
-
-/*******************  Bit definition for CAN_TSR register  ********************/
-#define  CAN_TSR_RQCP0                       0x00000001U        /*!<Request Completed Mailbox0 */
-#define  CAN_TSR_TXOK0                       0x00000002U        /*!<Transmission OK of Mailbox0 */
-#define  CAN_TSR_ALST0                       0x00000004U        /*!<Arbitration Lost for Mailbox0 */
-#define  CAN_TSR_TERR0                       0x00000008U        /*!<Transmission Error of Mailbox0 */
-#define  CAN_TSR_ABRQ0                       0x00000080U        /*!<Abort Request for Mailbox0 */
-#define  CAN_TSR_RQCP1                       0x00000100U        /*!<Request Completed Mailbox1 */
-#define  CAN_TSR_TXOK1                       0x00000200U        /*!<Transmission OK of Mailbox1 */
-#define  CAN_TSR_ALST1                       0x00000400U        /*!<Arbitration Lost for Mailbox1 */
-#define  CAN_TSR_TERR1                       0x00000800U        /*!<Transmission Error of Mailbox1 */
-#define  CAN_TSR_ABRQ1                       0x00008000U        /*!<Abort Request for Mailbox 1 */
-#define  CAN_TSR_RQCP2                       0x00010000U        /*!<Request Completed Mailbox2 */
-#define  CAN_TSR_TXOK2                       0x00020000U        /*!<Transmission OK of Mailbox 2 */
-#define  CAN_TSR_ALST2                       0x00040000U        /*!<Arbitration Lost for mailbox 2 */
-#define  CAN_TSR_TERR2                       0x00080000U        /*!<Transmission Error of Mailbox 2 */
-#define  CAN_TSR_ABRQ2                       0x00800000U        /*!<Abort Request for Mailbox 2 */
-#define  CAN_TSR_CODE                        0x03000000U        /*!<Mailbox Code */
-
-#define  CAN_TSR_TME                         0x1C000000U        /*!<TME[2:0] bits */
-#define  CAN_TSR_TME0                        0x04000000U        /*!<Transmit Mailbox 0 Empty */
-#define  CAN_TSR_TME1                        0x08000000U        /*!<Transmit Mailbox 1 Empty */
-#define  CAN_TSR_TME2                        0x10000000U        /*!<Transmit Mailbox 2 Empty */
-
-#define  CAN_TSR_LOW                         0xE0000000U        /*!<LOW[2:0] bits */
-#define  CAN_TSR_LOW0                        0x20000000U        /*!<Lowest Priority Flag for Mailbox 0 */
-#define  CAN_TSR_LOW1                        0x40000000U        /*!<Lowest Priority Flag for Mailbox 1 */
-#define  CAN_TSR_LOW2                        0x80000000U        /*!<Lowest Priority Flag for Mailbox 2 */
-
-/*******************  Bit definition for CAN_RF0R register  *******************/
-#define  CAN_RF0R_FMP0                       0x03U               /*!<FIFO 0 Message Pending */
-#define  CAN_RF0R_FULL0                      0x08U               /*!<FIFO 0 Full */
-#define  CAN_RF0R_FOVR0                      0x10U               /*!<FIFO 0 Overrun */
-#define  CAN_RF0R_RFOM0                      0x20U               /*!<Release FIFO 0 Output Mailbox */
-
-/*******************  Bit definition for CAN_RF1R register  *******************/
-#define  CAN_RF1R_FMP1                       0x03U               /*!<FIFO 1 Message Pending */
-#define  CAN_RF1R_FULL1                      0x08U               /*!<FIFO 1 Full */
-#define  CAN_RF1R_FOVR1                      0x10U               /*!<FIFO 1 Overrun */
-#define  CAN_RF1R_RFOM1                      0x20U               /*!<Release FIFO 1 Output Mailbox */
-
-/********************  Bit definition for CAN_IER register  *******************/
-#define  CAN_IER_TMEIE                       0x00000001U        /*!<Transmit Mailbox Empty Interrupt Enable */
-#define  CAN_IER_FMPIE0                      0x00000002U        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE0                       0x00000004U        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE0                      0x00000008U        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_FMPIE1                      0x00000010U        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE1                       0x00000020U        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE1                      0x00000040U        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error Warning Interrupt Enable */
-#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error Passive Interrupt Enable */
-#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-Off Interrupt Enable */
-#define  CAN_IER_LECIE                       0x00000800U        /*!<Last Error Code Interrupt Enable */
-#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error Interrupt Enable */
-#define  CAN_IER_WKUIE                       0x00010000U        /*!<Wakeup Interrupt Enable */
-#define  CAN_IER_SLKIE                       0x00020000U        /*!<Sleep Interrupt Enable */
-#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error warning interrupt enable */
-#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error passive interrupt enable */
-#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-off interrupt enable */
-#define  CAN_IER_LECIE                       0x00000800U        /*!<Last error code interrupt enable */
-#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error interrupt enable */
-
-
-/********************  Bit definition for CAN_ESR register  *******************/
-#define  CAN_ESR_EWGF                        0x00000001U        /*!<Error Warning Flag */
-#define  CAN_ESR_EPVF                        0x00000002U        /*!<Error Passive Flag */
-#define  CAN_ESR_BOFF                        0x00000004U        /*!<Bus-Off Flag */
-
-#define  CAN_ESR_LEC                         0x00000070U        /*!<LEC[2:0] bits (Last Error Code) */
-#define  CAN_ESR_LEC_0                       0x00000010U        /*!<Bit 0 */
-#define  CAN_ESR_LEC_1                       0x00000020U        /*!<Bit 1 */
-#define  CAN_ESR_LEC_2                       0x00000040U        /*!<Bit 2 */
-
-#define  CAN_ESR_TEC                         0x00FF0000U        /*!<Least significant byte of the 9-bit Transmit Error Counter */
-#define  CAN_ESR_REC                         0xFF000000U        /*!<Receive Error Counter */
-
-/*******************  Bit definition for CAN_BTR register  ********************/
-#define  CAN_BTR_BRP                         0x000003FFU        /*!<Baud Rate Prescaler */
-#define  CAN_BTR_TS1                         0x000F0000U        /*!<Time Segment 1 */
-#define  CAN_BTR_TS1_0                       0x00010000U        /*!<Bit 0 */
-#define  CAN_BTR_TS1_1                       0x00020000U        /*!<Bit 1 */
-#define  CAN_BTR_TS1_2                       0x00040000U        /*!<Bit 2 */
-#define  CAN_BTR_TS1_3                       0x00080000U        /*!<Bit 3 */
-#define  CAN_BTR_TS2                         0x00700000U        /*!<Time Segment 2 */
-#define  CAN_BTR_TS2_0                       0x00100000U        /*!<Bit 0 */
-#define  CAN_BTR_TS2_1                       0x00200000U        /*!<Bit 1 */
-#define  CAN_BTR_TS2_2                       0x00400000U        /*!<Bit 2 */
-#define  CAN_BTR_SJW                         0x03000000U        /*!<Resynchronization Jump Width */
-#define  CAN_BTR_SJW_0                       0x01000000U        /*!<Bit 0 */
-#define  CAN_BTR_SJW_1                       0x02000000U        /*!<Bit 1 */
-#define  CAN_BTR_LBKM                        0x40000000U        /*!<Loop Back Mode (Debug) */
-#define  CAN_BTR_SILM                        0x80000000U        /*!<Silent Mode */
-
-
-/*!<Mailbox registers */
-/******************  Bit definition for CAN_TI0R register  ********************/
-#define  CAN_TI0R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI0R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_TI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/******************  Bit definition for CAN_TDT0R register  *******************/
-#define  CAN_TDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT0R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/******************  Bit definition for CAN_TDL0R register  *******************/
-#define  CAN_TDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/******************  Bit definition for CAN_TDH0R register  *******************/
-#define  CAN_TDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI1R register  *******************/
-#define  CAN_TI1R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI1R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI1R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_TI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT1R register  ******************/
-#define  CAN_TDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT1R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL1R register  ******************/
-#define  CAN_TDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH1R register  ******************/
-#define  CAN_TDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI2R register  *******************/
-#define  CAN_TI2R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI2R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI2R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI2R_EXID                       0x001FFFF8U        /*!<Extended identifier */
-#define  CAN_TI2R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT2R register  ******************/  
-#define  CAN_TDT2R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT2R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT2R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL2R register  ******************/
-#define  CAN_TDL2R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL2R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL2R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL2R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH2R register  ******************/
-#define  CAN_TDH2R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH2R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH2R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH2R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI0R register  *******************/
-#define  CAN_RI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_RI0R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_RI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_RI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT0R register  ******************/
-#define  CAN_RDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_RDT0R_FMI                       0x0000FF00U        /*!<Filter Match Index */
-#define  CAN_RDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL0R register  ******************/
-#define  CAN_RDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_RDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_RDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_RDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH0R register  ******************/
-#define  CAN_RDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_RDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_RDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_RDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI1R register  *******************/
-#define  CAN_RI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_RI1R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_RI1R_EXID                       0x001FFFF8U        /*!<Extended identifier */
-#define  CAN_RI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT1R register  ******************/
-#define  CAN_RDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_RDT1R_FMI                       0x0000FF00U        /*!<Filter Match Index */
-#define  CAN_RDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL1R register  ******************/
-#define  CAN_RDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_RDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_RDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_RDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH1R register  ******************/
-#define  CAN_RDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_RDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_RDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_RDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*!<CAN filter registers */
-/*******************  Bit definition for CAN_FMR register  ********************/
-#define  CAN_FMR_FINIT                       0x01U               /*!<Filter Init Mode */
-#define  CAN_FMR_CAN2SB                      0x00003F00U        /*!<CAN2 start bank */
-
-/*******************  Bit definition for CAN_FM1R register  *******************/
-#define  CAN_FM1R_FBM                        0x0FFFFFFFU        /*!<Filter Mode */
-#define  CAN_FM1R_FBM0                       0x00000001U        /*!<Filter Init Mode bit 0 */
-#define  CAN_FM1R_FBM1                       0x00000002U        /*!<Filter Init Mode bit 1 */
-#define  CAN_FM1R_FBM2                       0x00000004U        /*!<Filter Init Mode bit 2 */
-#define  CAN_FM1R_FBM3                       0x00000008U        /*!<Filter Init Mode bit 3 */
-#define  CAN_FM1R_FBM4                       0x00000010U        /*!<Filter Init Mode bit 4 */
-#define  CAN_FM1R_FBM5                       0x00000020U        /*!<Filter Init Mode bit 5 */
-#define  CAN_FM1R_FBM6                       0x00000040U        /*!<Filter Init Mode bit 6 */
-#define  CAN_FM1R_FBM7                       0x00000080U        /*!<Filter Init Mode bit 7 */
-#define  CAN_FM1R_FBM8                       0x00000100U        /*!<Filter Init Mode bit 8 */
-#define  CAN_FM1R_FBM9                       0x00000200U        /*!<Filter Init Mode bit 9 */
-#define  CAN_FM1R_FBM10                      0x00000400U        /*!<Filter Init Mode bit 10 */
-#define  CAN_FM1R_FBM11                      0x00000800U        /*!<Filter Init Mode bit 11 */
-#define  CAN_FM1R_FBM12                      0x00001000U        /*!<Filter Init Mode bit 12 */
-#define  CAN_FM1R_FBM13                      0x00002000U        /*!<Filter Init Mode bit 13 */
-#define  CAN_FM1R_FBM14                      0x00004000U        /*!<Filter Init Mode bit 14 */
-#define  CAN_FM1R_FBM15                      0x00008000U        /*!<Filter Init Mode bit 15 */
-#define  CAN_FM1R_FBM16                      0x00010000U        /*!<Filter Init Mode bit 16 */
-#define  CAN_FM1R_FBM17                      0x00020000U        /*!<Filter Init Mode bit 17 */
-#define  CAN_FM1R_FBM18                      0x00040000U        /*!<Filter Init Mode bit 18 */
-#define  CAN_FM1R_FBM19                      0x00080000U        /*!<Filter Init Mode bit 19 */
-#define  CAN_FM1R_FBM20                      0x00100000U        /*!<Filter Init Mode bit 20 */
-#define  CAN_FM1R_FBM21                      0x00200000U        /*!<Filter Init Mode bit 21 */
-#define  CAN_FM1R_FBM22                      0x00400000U        /*!<Filter Init Mode bit 22 */
-#define  CAN_FM1R_FBM23                      0x00800000U        /*!<Filter Init Mode bit 23 */
-#define  CAN_FM1R_FBM24                      0x01000000U        /*!<Filter Init Mode bit 24 */
-#define  CAN_FM1R_FBM25                      0x02000000U        /*!<Filter Init Mode bit 25 */
-#define  CAN_FM1R_FBM26                      0x04000000U        /*!<Filter Init Mode bit 26 */
-#define  CAN_FM1R_FBM27                      0x08000000U        /*!<Filter Init Mode bit 27 */
-
-/*******************  Bit definition for CAN_FS1R register  *******************/
-#define  CAN_FS1R_FSC                        0x0FFFFFFFU        /*!<Filter Scale Configuration */
-#define  CAN_FS1R_FSC0                       0x00000001U        /*!<Filter Scale Configuration bit 0 */
-#define  CAN_FS1R_FSC1                       0x00000002U        /*!<Filter Scale Configuration bit 1 */
-#define  CAN_FS1R_FSC2                       0x00000004U        /*!<Filter Scale Configuration bit 2 */
-#define  CAN_FS1R_FSC3                       0x00000008U        /*!<Filter Scale Configuration bit 3 */
-#define  CAN_FS1R_FSC4                       0x00000010U        /*!<Filter Scale Configuration bit 4 */
-#define  CAN_FS1R_FSC5                       0x00000020U        /*!<Filter Scale Configuration bit 5 */
-#define  CAN_FS1R_FSC6                       0x00000040U        /*!<Filter Scale Configuration bit 6 */
-#define  CAN_FS1R_FSC7                       0x00000080U        /*!<Filter Scale Configuration bit 7 */
-#define  CAN_FS1R_FSC8                       0x00000100U        /*!<Filter Scale Configuration bit 8 */
-#define  CAN_FS1R_FSC9                       0x00000200U        /*!<Filter Scale Configuration bit 9 */
-#define  CAN_FS1R_FSC10                      0x00000400U        /*!<Filter Scale Configuration bit 10 */
-#define  CAN_FS1R_FSC11                      0x00000800U        /*!<Filter Scale Configuration bit 11 */
-#define  CAN_FS1R_FSC12                      0x00001000U        /*!<Filter Scale Configuration bit 12 */
-#define  CAN_FS1R_FSC13                      0x00002000U        /*!<Filter Scale Configuration bit 13 */
-#define  CAN_FS1R_FSC14                      0x00004000U        /*!<Filter Scale Configuration bit 14 */
-#define  CAN_FS1R_FSC15                      0x00008000U        /*!<Filter Scale Configuration bit 15 */
-#define  CAN_FS1R_FSC16                      0x00010000U        /*!<Filter Scale Configuration bit 16 */
-#define  CAN_FS1R_FSC17                      0x00020000U        /*!<Filter Scale Configuration bit 17 */
-#define  CAN_FS1R_FSC18                      0x00040000U        /*!<Filter Scale Configuration bit 18 */
-#define  CAN_FS1R_FSC19                      0x00080000U        /*!<Filter Scale Configuration bit 19 */
-#define  CAN_FS1R_FSC20                      0x00100000U        /*!<Filter Scale Configuration bit 20 */
-#define  CAN_FS1R_FSC21                      0x00200000U        /*!<Filter Scale Configuration bit 21 */
-#define  CAN_FS1R_FSC22                      0x00400000U        /*!<Filter Scale Configuration bit 22 */
-#define  CAN_FS1R_FSC23                      0x00800000U        /*!<Filter Scale Configuration bit 23 */
-#define  CAN_FS1R_FSC24                      0x01000000U        /*!<Filter Scale Configuration bit 24 */
-#define  CAN_FS1R_FSC25                      0x02000000U        /*!<Filter Scale Configuration bit 25 */
-#define  CAN_FS1R_FSC26                      0x04000000U        /*!<Filter Scale Configuration bit 26 */
-#define  CAN_FS1R_FSC27                      0x08000000U        /*!<Filter Scale Configuration bit 27 */
-
-/******************  Bit definition for CAN_FFA1R register  *******************/
-#define  CAN_FFA1R_FFA                        0x0FFFFFFFU        /*!<Filter FIFO Assignment */
-#define  CAN_FFA1R_FFA0                       0x00000001U        /*!<Filter FIFO Assignment bit 0 */
-#define  CAN_FFA1R_FFA1                       0x00000002U        /*!<Filter FIFO Assignment bit 1 */
-#define  CAN_FFA1R_FFA2                       0x00000004U        /*!<Filter FIFO Assignment bit 2 */
-#define  CAN_FFA1R_FFA3                       0x00000008U        /*!<Filter FIFO Assignment bit 3 */
-#define  CAN_FFA1R_FFA4                       0x00000010U        /*!<Filter FIFO Assignment bit 4 */
-#define  CAN_FFA1R_FFA5                       0x00000020U        /*!<Filter FIFO Assignment bit 5 */
-#define  CAN_FFA1R_FFA6                       0x00000040U        /*!<Filter FIFO Assignment bit 6 */
-#define  CAN_FFA1R_FFA7                       0x00000080U        /*!<Filter FIFO Assignment bit 7 */
-#define  CAN_FFA1R_FFA8                       0x00000100U        /*!<Filter FIFO Assignment bit 8 */
-#define  CAN_FFA1R_FFA9                       0x00000200U        /*!<Filter FIFO Assignment bit 9 */
-#define  CAN_FFA1R_FFA10                      0x00000400U        /*!<Filter FIFO Assignment bit 10 */
-#define  CAN_FFA1R_FFA11                      0x00000800U        /*!<Filter FIFO Assignment bit 11 */
-#define  CAN_FFA1R_FFA12                      0x00001000U        /*!<Filter FIFO Assignment bit 12 */
-#define  CAN_FFA1R_FFA13                      0x00002000U        /*!<Filter FIFO Assignment bit 13 */
-#define  CAN_FFA1R_FFA14                      0x00004000U        /*!<Filter FIFO Assignment bit 14 */
-#define  CAN_FFA1R_FFA15                      0x00008000U        /*!<Filter FIFO Assignment bit 15 */
-#define  CAN_FFA1R_FFA16                      0x00010000U        /*!<Filter FIFO Assignment bit 16 */
-#define  CAN_FFA1R_FFA17                      0x00020000U        /*!<Filter FIFO Assignment bit 17 */
-#define  CAN_FFA1R_FFA18                      0x00040000U        /*!<Filter FIFO Assignment bit 18 */
-#define  CAN_FFA1R_FFA19                      0x00080000U        /*!<Filter FIFO Assignment bit 19 */
-#define  CAN_FFA1R_FFA20                      0x00100000U        /*!<Filter FIFO Assignment bit 20 */
-#define  CAN_FFA1R_FFA21                      0x00200000U        /*!<Filter FIFO Assignment bit 21 */
-#define  CAN_FFA1R_FFA22                      0x00400000U        /*!<Filter FIFO Assignment bit 22 */
-#define  CAN_FFA1R_FFA23                      0x00800000U        /*!<Filter FIFO Assignment bit 23 */
-#define  CAN_FFA1R_FFA24                      0x01000000U        /*!<Filter FIFO Assignment bit 24 */
-#define  CAN_FFA1R_FFA25                      0x02000000U        /*!<Filter FIFO Assignment bit 25 */
-#define  CAN_FFA1R_FFA26                      0x04000000U        /*!<Filter FIFO Assignment bit 26 */
-#define  CAN_FFA1R_FFA27                      0x08000000U        /*!<Filter FIFO Assignment bit 27 */
-
-/*******************  Bit definition for CAN_FA1R register  *******************/
-#define  CAN_FA1R_FACT                        0x0FFFFFFFU        /*!<Filter Active */
-#define  CAN_FA1R_FACT0                       0x00000001U        /*!<Filter Active bit 0 */
-#define  CAN_FA1R_FACT1                       0x00000002U        /*!<Filter Active bit 1 */
-#define  CAN_FA1R_FACT2                       0x00000004U        /*!<Filter Active bit 2 */
-#define  CAN_FA1R_FACT3                       0x00000008U        /*!<Filter Active bit 3 */
-#define  CAN_FA1R_FACT4                       0x00000010U        /*!<Filter Active bit 4 */
-#define  CAN_FA1R_FACT5                       0x00000020U        /*!<Filter Active bit 5 */
-#define  CAN_FA1R_FACT6                       0x00000040U        /*!<Filter Active bit 6 */
-#define  CAN_FA1R_FACT7                       0x00000080U        /*!<Filter Active bit 7 */
-#define  CAN_FA1R_FACT8                       0x00000100U        /*!<Filter Active bit 8 */
-#define  CAN_FA1R_FACT9                       0x00000200U        /*!<Filter Active bit 9 */
-#define  CAN_FA1R_FACT10                      0x00000400U        /*!<Filter Active bit 10 */
-#define  CAN_FA1R_FACT11                      0x00000800U        /*!<Filter Active bit 11 */
-#define  CAN_FA1R_FACT12                      0x00001000U        /*!<Filter Active bit 12 */
-#define  CAN_FA1R_FACT13                      0x00002000U        /*!<Filter Active bit 13 */
-#define  CAN_FA1R_FACT14                      0x00004000U        /*!<Filter Active bit 14 */
-#define  CAN_FA1R_FACT15                      0x00008000U        /*!<Filter Active bit 15 */
-#define  CAN_FA1R_FACT16                      0x00010000U        /*!<Filter Active bit 16 */
-#define  CAN_FA1R_FACT17                      0x00020000U        /*!<Filter Active bit 17 */
-#define  CAN_FA1R_FACT18                      0x00040000U        /*!<Filter Active bit 18 */
-#define  CAN_FA1R_FACT19                      0x00080000U        /*!<Filter Active bit 19 */
-#define  CAN_FA1R_FACT20                      0x00100000U        /*!<Filter Active bit 20 */
-#define  CAN_FA1R_FACT21                      0x00200000U        /*!<Filter Active bit 21 */
-#define  CAN_FA1R_FACT22                      0x00400000U        /*!<Filter Active bit 22 */
-#define  CAN_FA1R_FACT23                      0x00800000U        /*!<Filter Active bit 23 */
-#define  CAN_FA1R_FACT24                      0x01000000U        /*!<Filter Active bit 24 */
-#define  CAN_FA1R_FACT25                      0x02000000U        /*!<Filter Active bit 25 */
-#define  CAN_FA1R_FACT26                      0x04000000U        /*!<Filter Active bit 26 */
-#define  CAN_FA1R_FACT27                      0x08000000U        /*!<Filter Active bit 27 */
-
-/*******************  Bit definition for CAN_F0R1 register  *******************/
-#define  CAN_F0R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F0R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F0R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F0R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F0R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F0R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F0R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F0R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F0R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F0R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F0R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F0R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F0R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F0R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F0R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F0R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F0R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F0R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F0R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F0R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F0R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F0R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F0R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F0R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F0R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F0R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F0R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F0R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F0R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F0R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F0R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F0R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R1 register  *******************/
-#define  CAN_F1R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F1R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F1R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F1R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F1R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F1R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F1R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F1R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F1R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F1R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F1R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F1R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F1R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F1R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F1R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F1R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F1R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F1R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F1R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F1R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F1R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F1R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F1R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F1R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F1R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F1R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F1R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F1R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F1R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F1R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F1R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F1R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R1 register  *******************/
-#define  CAN_F2R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F2R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F2R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F2R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F2R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F2R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F2R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F2R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F2R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F2R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F2R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F2R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F2R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F2R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F2R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F2R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F2R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F2R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F2R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F2R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F2R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F2R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F2R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F2R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F2R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F2R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F2R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F2R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F2R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F2R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F2R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F2R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R1 register  *******************/
-#define  CAN_F3R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F3R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F3R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F3R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F3R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F3R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F3R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F3R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F3R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F3R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F3R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F3R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F3R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F3R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F3R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F3R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F3R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F3R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F3R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F3R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F3R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F3R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F3R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F3R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F3R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F3R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F3R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F3R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F3R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F3R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F3R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F3R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R1 register  *******************/
-#define  CAN_F4R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F4R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F4R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F4R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F4R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F4R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F4R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F4R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F4R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F4R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F4R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F4R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F4R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F4R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F4R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F4R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F4R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F4R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F4R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F4R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F4R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F4R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F4R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F4R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F4R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F4R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F4R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F4R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F4R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F4R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F4R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F4R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R1 register  *******************/
-#define  CAN_F5R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F5R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F5R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F5R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F5R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F5R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F5R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F5R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F5R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F5R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F5R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F5R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F5R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F5R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F5R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F5R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F5R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F5R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F5R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F5R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F5R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F5R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F5R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F5R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F5R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F5R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F5R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F5R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F5R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F5R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F5R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F5R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R1 register  *******************/
-#define  CAN_F6R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F6R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F6R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F6R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F6R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F6R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F6R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F6R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F6R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F6R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F6R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F6R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F6R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F6R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F6R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F6R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F6R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F6R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F6R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F6R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F6R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F6R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F6R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F6R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F6R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F6R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F6R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F6R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F6R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F6R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F6R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F6R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R1 register  *******************/
-#define  CAN_F7R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F7R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F7R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F7R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F7R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F7R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F7R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F7R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F7R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F7R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F7R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F7R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F7R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F7R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F7R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F7R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F7R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F7R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F7R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F7R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F7R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F7R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F7R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F7R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F7R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F7R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F7R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F7R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F7R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F7R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F7R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F7R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R1 register  *******************/
-#define  CAN_F8R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F8R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F8R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F8R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F8R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F8R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F8R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F8R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F8R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F8R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F8R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F8R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F8R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F8R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F8R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F8R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F8R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F8R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F8R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F8R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F8R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F8R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F8R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F8R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F8R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F8R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F8R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F8R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F8R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F8R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F8R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F8R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R1 register  *******************/
-#define  CAN_F9R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F9R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F9R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F9R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F9R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F9R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F9R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F9R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F9R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F9R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F9R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F9R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F9R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F9R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F9R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F9R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F9R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F9R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F9R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F9R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F9R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F9R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F9R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F9R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F9R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F9R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F9R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F9R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F9R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F9R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F9R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F9R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R1 register  ******************/
-#define  CAN_F10R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F10R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F10R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F10R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F10R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F10R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F10R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F10R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F10R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F10R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F10R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F10R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F10R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F10R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F10R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F10R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F10R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F10R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F10R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F10R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F10R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F10R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F10R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F10R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F10R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F10R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F10R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F10R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F10R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F10R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F10R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F10R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R1 register  ******************/
-#define  CAN_F11R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F11R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F11R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F11R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F11R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F11R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F11R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F11R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F11R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F11R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F11R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F11R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F11R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F11R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F11R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F11R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F11R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F11R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F11R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F11R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F11R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F11R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F11R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F11R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F11R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F11R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F11R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F11R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F11R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F11R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F11R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F11R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R1 register  ******************/
-#define  CAN_F12R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F12R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F12R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F12R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F12R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F12R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F12R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F12R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F12R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F12R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F12R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F12R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F12R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F12R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F12R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F12R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F12R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F12R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F12R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F12R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F12R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F12R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F12R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F12R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F12R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F12R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F12R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F12R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F12R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F12R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F12R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F12R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R1 register  ******************/
-#define  CAN_F13R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F13R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F13R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F13R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F13R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F13R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F13R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F13R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F13R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F13R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F13R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F13R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F13R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F13R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F13R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F13R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F13R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F13R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F13R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F13R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F13R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F13R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F13R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F13R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F13R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F13R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F13R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F13R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F13R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F13R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F13R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F13R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F0R2 register  *******************/
-#define  CAN_F0R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F0R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F0R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F0R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F0R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F0R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F0R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F0R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F0R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F0R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F0R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F0R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F0R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F0R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F0R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F0R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F0R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F0R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F0R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F0R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F0R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F0R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F0R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F0R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F0R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F0R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F0R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F0R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F0R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F0R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F0R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F0R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R2 register  *******************/
-#define  CAN_F1R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F1R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F1R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F1R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F1R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F1R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F1R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F1R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F1R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F1R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F1R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F1R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F1R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F1R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F1R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F1R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F1R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F1R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F1R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F1R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F1R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F1R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F1R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F1R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F1R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F1R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F1R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F1R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F1R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F1R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F1R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F1R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R2 register  *******************/
-#define  CAN_F2R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F2R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F2R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F2R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F2R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F2R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F2R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F2R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F2R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F2R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F2R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F2R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F2R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F2R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F2R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F2R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F2R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F2R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F2R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F2R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F2R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F2R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F2R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F2R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F2R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F2R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F2R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F2R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F2R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F2R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F2R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F2R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R2 register  *******************/
-#define  CAN_F3R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F3R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F3R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F3R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F3R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F3R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F3R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F3R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F3R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F3R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F3R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F3R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F3R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F3R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F3R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F3R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F3R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F3R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F3R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F3R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F3R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F3R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F3R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F3R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F3R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F3R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F3R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F3R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F3R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F3R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F3R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F3R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R2 register  *******************/
-#define  CAN_F4R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F4R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F4R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F4R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F4R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F4R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F4R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F4R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F4R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F4R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F4R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F4R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F4R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F4R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F4R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F4R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F4R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F4R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F4R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F4R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F4R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F4R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F4R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F4R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F4R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F4R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F4R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F4R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F4R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F4R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F4R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F4R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R2 register  *******************/
-#define  CAN_F5R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F5R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F5R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F5R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F5R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F5R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F5R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F5R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F5R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F5R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F5R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F5R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F5R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F5R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F5R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F5R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F5R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F5R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F5R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F5R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F5R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F5R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F5R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F5R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F5R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F5R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F5R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F5R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F5R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F5R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F5R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F5R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R2 register  *******************/
-#define  CAN_F6R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F6R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F6R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F6R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F6R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F6R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F6R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F6R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F6R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F6R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F6R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F6R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F6R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F6R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F6R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F6R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F6R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F6R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F6R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F6R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F6R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F6R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F6R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F6R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F6R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F6R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F6R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F6R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F6R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F6R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F6R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F6R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R2 register  *******************/
-#define  CAN_F7R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F7R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F7R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F7R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F7R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F7R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F7R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F7R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F7R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F7R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F7R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F7R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F7R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F7R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F7R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F7R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F7R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F7R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F7R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F7R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F7R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F7R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F7R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F7R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F7R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F7R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F7R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F7R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F7R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F7R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F7R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F7R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R2 register  *******************/
-#define  CAN_F8R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F8R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F8R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F8R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F8R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F8R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F8R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F8R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F8R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F8R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F8R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F8R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F8R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F8R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F8R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F8R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F8R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F8R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F8R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F8R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F8R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F8R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F8R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F8R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F8R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F8R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F8R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F8R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F8R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F8R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F8R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F8R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R2 register  *******************/
-#define  CAN_F9R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F9R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F9R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F9R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F9R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F9R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F9R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F9R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F9R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F9R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F9R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F9R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F9R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F9R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F9R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F9R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F9R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F9R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F9R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F9R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F9R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F9R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F9R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F9R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F9R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F9R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F9R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F9R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F9R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F9R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F9R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F9R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R2 register  ******************/
-#define  CAN_F10R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F10R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F10R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F10R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F10R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F10R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F10R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F10R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F10R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F10R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F10R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F10R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F10R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F10R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F10R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F10R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F10R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F10R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F10R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F10R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F10R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F10R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F10R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F10R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F10R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F10R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F10R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F10R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F10R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F10R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F10R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F10R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R2 register  ******************/
-#define  CAN_F11R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F11R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F11R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F11R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F11R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F11R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F11R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F11R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F11R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F11R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F11R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F11R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F11R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F11R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F11R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F11R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F11R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F11R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F11R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F11R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F11R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F11R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F11R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F11R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F11R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F11R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F11R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F11R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F11R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F11R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F11R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F11R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R2 register  ******************/
-#define  CAN_F12R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F12R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F12R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F12R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F12R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F12R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F12R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F12R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F12R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F12R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F12R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F12R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F12R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F12R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F12R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F12R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F12R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F12R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F12R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F12R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F12R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F12R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F12R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F12R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F12R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F12R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F12R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F12R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F12R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F12R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F12R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F12R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R2 register  ******************/
-#define  CAN_F13R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F13R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F13R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F13R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F13R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F13R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F13R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F13R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F13R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F13R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F13R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F13R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F13R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F13R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F13R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F13R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F13R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F13R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F13R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F13R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F13R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F13R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F13R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F13R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F13R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F13R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F13R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F13R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F13R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F13R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F13R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F13R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRC calculation unit                              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           0xFFFFFFFFU /*!< Data register bits */
-
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         0xFFU        /*!< General-purpose 8-bit data register bits */
-
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        0x01U        /*!< RESET bit */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Digital to Analog Converter                           */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DAC_CR register  ********************/
-#define  DAC_CR_EN1                          0x00000001U        /*!<DAC channel1 enable */
-#define  DAC_CR_BOFF1                        0x00000002U        /*!<DAC channel1 output buffer disable */
-#define  DAC_CR_TEN1                         0x00000004U        /*!<DAC channel1 Trigger enable */
-
-#define  DAC_CR_TSEL1                        0x00000038U        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define  DAC_CR_TSEL1_0                      0x00000008U        /*!<Bit 0 */
-#define  DAC_CR_TSEL1_1                      0x00000010U        /*!<Bit 1 */
-#define  DAC_CR_TSEL1_2                      0x00000020U        /*!<Bit 2 */
-
-#define  DAC_CR_WAVE1                        0x000000C0U        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE1_0                      0x00000040U        /*!<Bit 0 */
-#define  DAC_CR_WAVE1_1                      0x00000080U        /*!<Bit 1 */
-
-#define  DAC_CR_MAMP1                        0x00000F00U        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP1_0                      0x00000100U        /*!<Bit 0 */
-#define  DAC_CR_MAMP1_1                      0x00000200U        /*!<Bit 1 */
-#define  DAC_CR_MAMP1_2                      0x00000400U        /*!<Bit 2 */
-#define  DAC_CR_MAMP1_3                      0x00000800U        /*!<Bit 3 */
-
-#define  DAC_CR_DMAEN1                       0x00001000U        /*!<DAC channel1 DMA enable */
-#define  DAC_CR_DMAUDRIE1                    0x00002000U        /*!<DAC channel1 DMA underrun interrupt enable*/
-#define  DAC_CR_EN2                          0x00010000U        /*!<DAC channel2 enable */
-#define  DAC_CR_BOFF2                        0x00020000U        /*!<DAC channel2 output buffer disable */
-#define  DAC_CR_TEN2                         0x00040000U        /*!<DAC channel2 Trigger enable */
-
-#define  DAC_CR_TSEL2                        0x00380000U        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define  DAC_CR_TSEL2_0                      0x00080000U        /*!<Bit 0 */
-#define  DAC_CR_TSEL2_1                      0x00100000U        /*!<Bit 1 */
-#define  DAC_CR_TSEL2_2                      0x00200000U        /*!<Bit 2 */
-
-#define  DAC_CR_WAVE2                        0x00C00000U        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE2_0                      0x00400000U        /*!<Bit 0 */
-#define  DAC_CR_WAVE2_1                      0x00800000U        /*!<Bit 1 */
-
-#define  DAC_CR_MAMP2                        0x0F000000U        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP2_0                      0x01000000U        /*!<Bit 0 */
-#define  DAC_CR_MAMP2_1                      0x02000000U        /*!<Bit 1 */
-#define  DAC_CR_MAMP2_2                      0x04000000U        /*!<Bit 2 */
-#define  DAC_CR_MAMP2_3                      0x08000000U        /*!<Bit 3 */
-
-#define  DAC_CR_DMAEN2                       0x10000000U        /*!<DAC channel2 DMA enabled */
-#define  DAC_CR_DMAUDRIE2                    0x20000000U        /*!<DAC channel2 DMA underrun interrupt enable*/
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define  DAC_SWTRIGR_SWTRIG1                 0x01U               /*!<DAC channel1 software trigger */
-#define  DAC_SWTRIGR_SWTRIG2                 0x02U               /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define  DAC_DHR12R1_DACC1DHR                0x0FFFU            /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define  DAC_DHR12L1_DACC1DHR                0xFFF0U            /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define  DAC_DHR8R1_DACC1DHR                 0xFFU               /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define  DAC_DHR12R2_DACC2DHR                0x0FFFU            /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define  DAC_DHR12L2_DACC2DHR                0xFFF0U            /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define  DAC_DHR8R2_DACC2DHR                 0xFFU               /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define  DAC_DHR12RD_DACC1DHR                0x00000FFFU        /*!<DAC channel1 12-bit Right aligned data */
-#define  DAC_DHR12RD_DACC2DHR                0x0FFF0000U        /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define  DAC_DHR12LD_DACC1DHR                0x0000FFF0U        /*!<DAC channel1 12-bit Left aligned data */
-#define  DAC_DHR12LD_DACC2DHR                0xFFF00000U        /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define  DAC_DHR8RD_DACC1DHR                 0x00FFU            /*!<DAC channel1 8-bit Right aligned data */
-#define  DAC_DHR8RD_DACC2DHR                 0xFF00U            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define  DAC_DOR1_DACC1DOR                   0x0FFFU            /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define  DAC_DOR2_DACC2DOR                   0x0FFFU            /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define  DAC_SR_DMAUDR1                      0x00002000U        /*!<DAC channel1 DMA underrun flag */
-#define  DAC_SR_DMAUDR2                      0x20000000U        /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 Debug MCU                                  */
-/*                                                                            */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                             DMA Controller                                 */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DMA_SxCR register  *****************/
-#define DMA_SxCR_CHSEL                       0x0E000000U
-#define DMA_SxCR_CHSEL_0                     0x02000000U
-#define DMA_SxCR_CHSEL_1                     0x04000000U
-#define DMA_SxCR_CHSEL_2                     0x08000000U
-#define DMA_SxCR_MBURST                      0x01800000U
-#define DMA_SxCR_MBURST_0                    0x00800000U
-#define DMA_SxCR_MBURST_1                    0x01000000U
-#define DMA_SxCR_PBURST                      0x00600000U
-#define DMA_SxCR_PBURST_0                    0x00200000U
-#define DMA_SxCR_PBURST_1                    0x00400000U
-#define DMA_SxCR_CT                          0x00080000U
-#define DMA_SxCR_DBM                         0x00040000U
-#define DMA_SxCR_PL                          0x00030000U
-#define DMA_SxCR_PL_0                        0x00010000U
-#define DMA_SxCR_PL_1                        0x00020000U
-#define DMA_SxCR_PINCOS                      0x00008000U
-#define DMA_SxCR_MSIZE                       0x00006000U
-#define DMA_SxCR_MSIZE_0                     0x00002000U
-#define DMA_SxCR_MSIZE_1                     0x00004000U
-#define DMA_SxCR_PSIZE                       0x00001800U
-#define DMA_SxCR_PSIZE_0                     0x00000800U
-#define DMA_SxCR_PSIZE_1                     0x00001000U
-#define DMA_SxCR_MINC                        0x00000400U
-#define DMA_SxCR_PINC                        0x00000200U
-#define DMA_SxCR_CIRC                        0x00000100U
-#define DMA_SxCR_DIR                         0x000000C0U
-#define DMA_SxCR_DIR_0                       0x00000040U
-#define DMA_SxCR_DIR_1                       0x00000080U
-#define DMA_SxCR_PFCTRL                      0x00000020U
-#define DMA_SxCR_TCIE                        0x00000010U
-#define DMA_SxCR_HTIE                        0x00000008U
-#define DMA_SxCR_TEIE                        0x00000004U
-#define DMA_SxCR_DMEIE                       0x00000002U
-#define DMA_SxCR_EN                          0x00000001U
-
-/* Legacy defines */
-#define DMA_SxCR_ACK                         0x00100000U
-
-/********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            0x0000FFFFU
-#define DMA_SxNDT_0                          0x00000001U
-#define DMA_SxNDT_1                          0x00000002U
-#define DMA_SxNDT_2                          0x00000004U
-#define DMA_SxNDT_3                          0x00000008U
-#define DMA_SxNDT_4                          0x00000010U
-#define DMA_SxNDT_5                          0x00000020U
-#define DMA_SxNDT_6                          0x00000040U
-#define DMA_SxNDT_7                          0x00000080U
-#define DMA_SxNDT_8                          0x00000100U
-#define DMA_SxNDT_9                          0x00000200U
-#define DMA_SxNDT_10                         0x00000400U
-#define DMA_SxNDT_11                         0x00000800U
-#define DMA_SxNDT_12                         0x00001000U
-#define DMA_SxNDT_13                         0x00002000U
-#define DMA_SxNDT_14                         0x00004000U
-#define DMA_SxNDT_15                         0x00008000U
-
-/********************  Bits definition for DMA_SxFCR register  ****************/ 
-#define DMA_SxFCR_FEIE                       0x00000080U
-#define DMA_SxFCR_FS                         0x00000038U
-#define DMA_SxFCR_FS_0                       0x00000008U
-#define DMA_SxFCR_FS_1                       0x00000010U
-#define DMA_SxFCR_FS_2                       0x00000020U
-#define DMA_SxFCR_DMDIS                      0x00000004U
-#define DMA_SxFCR_FTH                        0x00000003U
-#define DMA_SxFCR_FTH_0                      0x00000001U
-#define DMA_SxFCR_FTH_1                      0x00000002U
-
-/********************  Bits definition for DMA_LISR register  *****************/ 
-#define DMA_LISR_TCIF3                       0x08000000U
-#define DMA_LISR_HTIF3                       0x04000000U
-#define DMA_LISR_TEIF3                       0x02000000U
-#define DMA_LISR_DMEIF3                      0x01000000U
-#define DMA_LISR_FEIF3                       0x00400000U
-#define DMA_LISR_TCIF2                       0x00200000U
-#define DMA_LISR_HTIF2                       0x00100000U
-#define DMA_LISR_TEIF2                       0x00080000U
-#define DMA_LISR_DMEIF2                      0x00040000U
-#define DMA_LISR_FEIF2                       0x00010000U
-#define DMA_LISR_TCIF1                       0x00000800U
-#define DMA_LISR_HTIF1                       0x00000400U
-#define DMA_LISR_TEIF1                       0x00000200U
-#define DMA_LISR_DMEIF1                      0x00000100U
-#define DMA_LISR_FEIF1                       0x00000040U
-#define DMA_LISR_TCIF0                       0x00000020U
-#define DMA_LISR_HTIF0                       0x00000010U
-#define DMA_LISR_TEIF0                       0x00000008U
-#define DMA_LISR_DMEIF0                      0x00000004U
-#define DMA_LISR_FEIF0                       0x00000001U
-
-/********************  Bits definition for DMA_HISR register  *****************/ 
-#define DMA_HISR_TCIF7                       0x08000000U
-#define DMA_HISR_HTIF7                       0x04000000U
-#define DMA_HISR_TEIF7                       0x02000000U
-#define DMA_HISR_DMEIF7                      0x01000000U
-#define DMA_HISR_FEIF7                       0x00400000U
-#define DMA_HISR_TCIF6                       0x00200000U
-#define DMA_HISR_HTIF6                       0x00100000U
-#define DMA_HISR_TEIF6                       0x00080000U
-#define DMA_HISR_DMEIF6                      0x00040000U
-#define DMA_HISR_FEIF6                       0x00010000U
-#define DMA_HISR_TCIF5                       0x00000800U
-#define DMA_HISR_HTIF5                       0x00000400U
-#define DMA_HISR_TEIF5                       0x00000200U
-#define DMA_HISR_DMEIF5                      0x00000100U
-#define DMA_HISR_FEIF5                       0x00000040U
-#define DMA_HISR_TCIF4                       0x00000020U
-#define DMA_HISR_HTIF4                       0x00000010U
-#define DMA_HISR_TEIF4                       0x00000008U
-#define DMA_HISR_DMEIF4                      0x00000004U
-#define DMA_HISR_FEIF4                       0x00000001U
-
-/********************  Bits definition for DMA_LIFCR register  ****************/ 
-#define DMA_LIFCR_CTCIF3                     0x08000000U
-#define DMA_LIFCR_CHTIF3                     0x04000000U
-#define DMA_LIFCR_CTEIF3                     0x02000000U
-#define DMA_LIFCR_CDMEIF3                    0x01000000U
-#define DMA_LIFCR_CFEIF3                     0x00400000U
-#define DMA_LIFCR_CTCIF2                     0x00200000U
-#define DMA_LIFCR_CHTIF2                     0x00100000U
-#define DMA_LIFCR_CTEIF2                     0x00080000U
-#define DMA_LIFCR_CDMEIF2                    0x00040000U
-#define DMA_LIFCR_CFEIF2                     0x00010000U
-#define DMA_LIFCR_CTCIF1                     0x00000800U
-#define DMA_LIFCR_CHTIF1                     0x00000400U
-#define DMA_LIFCR_CTEIF1                     0x00000200U
-#define DMA_LIFCR_CDMEIF1                    0x00000100U
-#define DMA_LIFCR_CFEIF1                     0x00000040U
-#define DMA_LIFCR_CTCIF0                     0x00000020U
-#define DMA_LIFCR_CHTIF0                     0x00000010U
-#define DMA_LIFCR_CTEIF0                     0x00000008U
-#define DMA_LIFCR_CDMEIF0                    0x00000004U
-#define DMA_LIFCR_CFEIF0                     0x00000001U
-
-/********************  Bits definition for DMA_HIFCR  register  ****************/ 
-#define DMA_HIFCR_CTCIF7                     0x08000000U
-#define DMA_HIFCR_CHTIF7                     0x04000000U
-#define DMA_HIFCR_CTEIF7                     0x02000000U
-#define DMA_HIFCR_CDMEIF7                    0x01000000U
-#define DMA_HIFCR_CFEIF7                     0x00400000U
-#define DMA_HIFCR_CTCIF6                     0x00200000U
-#define DMA_HIFCR_CHTIF6                     0x00100000U
-#define DMA_HIFCR_CTEIF6                     0x00080000U
-#define DMA_HIFCR_CDMEIF6                    0x00040000U
-#define DMA_HIFCR_CFEIF6                     0x00010000U
-#define DMA_HIFCR_CTCIF5                     0x00000800U
-#define DMA_HIFCR_CHTIF5                     0x00000400U
-#define DMA_HIFCR_CTEIF5                     0x00000200U
-#define DMA_HIFCR_CDMEIF5                    0x00000100U
-#define DMA_HIFCR_CFEIF5                     0x00000040U
-#define DMA_HIFCR_CTCIF4                     0x00000020U
-#define DMA_HIFCR_CHTIF4                     0x00000010U
-#define DMA_HIFCR_CTEIF4                     0x00000008U
-#define DMA_HIFCR_CDMEIF4                    0x00000004U
-#define DMA_HIFCR_CFEIF4                     0x00000001U
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                    External Interrupt/Event Controller                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    FLASH                                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    0x0000000FU
-#define FLASH_ACR_LATENCY_0WS                0x00000000U
-#define FLASH_ACR_LATENCY_1WS                0x00000001U
-#define FLASH_ACR_LATENCY_2WS                0x00000002U
-#define FLASH_ACR_LATENCY_3WS                0x00000003U
-#define FLASH_ACR_LATENCY_4WS                0x00000004U
-#define FLASH_ACR_LATENCY_5WS                0x00000005U
-#define FLASH_ACR_LATENCY_6WS                0x00000006U
-#define FLASH_ACR_LATENCY_7WS                0x00000007U
-
-#define FLASH_ACR_PRFTEN                     0x00000100U
-#define FLASH_ACR_ICEN                       0x00000200U
-#define FLASH_ACR_DCEN                       0x00000400U
-#define FLASH_ACR_ICRST                      0x00000800U
-#define FLASH_ACR_DCRST                      0x00001000U
-#define FLASH_ACR_BYTE0_ADDRESS              0x40023C00U
-#define FLASH_ACR_BYTE2_ADDRESS              0x40023C03U
-
-/*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         0x00000001U
-#define FLASH_SR_SOP                         0x00000002U
-#define FLASH_SR_WRPERR                      0x00000010U
-#define FLASH_SR_PGAERR                      0x00000020U
-#define FLASH_SR_PGPERR                      0x00000040U
-#define FLASH_SR_PGSERR                      0x00000080U
-#define FLASH_SR_BSY                         0x00010000U
-
-/*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          0x00000001U
-#define FLASH_CR_SER                         0x00000002U
-#define FLASH_CR_MER                         0x00000004U
-#define FLASH_CR_SNB                         0x000000F8U
-#define FLASH_CR_SNB_0                       0x00000008U
-#define FLASH_CR_SNB_1                       0x00000010U
-#define FLASH_CR_SNB_2                       0x00000020U
-#define FLASH_CR_SNB_3                       0x00000040U
-#define FLASH_CR_SNB_4                       0x00000080U
-#define FLASH_CR_PSIZE                       0x00000300U
-#define FLASH_CR_PSIZE_0                     0x00000100U
-#define FLASH_CR_PSIZE_1                     0x00000200U
-#define FLASH_CR_STRT                        0x00010000U
-#define FLASH_CR_EOPIE                       0x01000000U
-#define FLASH_CR_LOCK                        0x80000000U
-
-/*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                 0x00000001U
-#define FLASH_OPTCR_OPTSTRT                 0x00000002U
-#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
-#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
-#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
-
-#define FLASH_OPTCR_WDG_SW                  0x00000020U
-#define FLASH_OPTCR_nRST_STOP               0x00000040U
-#define FLASH_OPTCR_nRST_STDBY              0x00000080U
-#define FLASH_OPTCR_RDP                     0x0000FF00U
-#define FLASH_OPTCR_RDP_0                   0x00000100U
-#define FLASH_OPTCR_RDP_1                   0x00000200U
-#define FLASH_OPTCR_RDP_2                   0x00000400U
-#define FLASH_OPTCR_RDP_3                   0x00000800U
-#define FLASH_OPTCR_RDP_4                   0x00001000U
-#define FLASH_OPTCR_RDP_5                   0x00002000U
-#define FLASH_OPTCR_RDP_6                   0x00004000U
-#define FLASH_OPTCR_RDP_7                   0x00008000U
-#define FLASH_OPTCR_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR_nWRP_0                  0x00010000U
-#define FLASH_OPTCR_nWRP_1                  0x00020000U
-#define FLASH_OPTCR_nWRP_2                  0x00040000U
-#define FLASH_OPTCR_nWRP_3                  0x00080000U
-#define FLASH_OPTCR_nWRP_4                  0x00100000U
-#define FLASH_OPTCR_nWRP_5                  0x00200000U
-#define FLASH_OPTCR_nWRP_6                  0x00400000U
-#define FLASH_OPTCR_nWRP_7                  0x00800000U
-#define FLASH_OPTCR_nWRP_8                  0x01000000U
-#define FLASH_OPTCR_nWRP_9                  0x02000000U
-#define FLASH_OPTCR_nWRP_10                 0x04000000U
-#define FLASH_OPTCR_nWRP_11                 0x08000000U
-                                             
-/******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR1_nWRP_0                  0x00010000U
-#define FLASH_OPTCR1_nWRP_1                  0x00020000U
-#define FLASH_OPTCR1_nWRP_2                  0x00040000U
-#define FLASH_OPTCR1_nWRP_3                  0x00080000U
-#define FLASH_OPTCR1_nWRP_4                  0x00100000U
-#define FLASH_OPTCR1_nWRP_5                  0x00200000U
-#define FLASH_OPTCR1_nWRP_6                  0x00400000U
-#define FLASH_OPTCR1_nWRP_7                  0x00800000U
-#define FLASH_OPTCR1_nWRP_8                  0x01000000U
-#define FLASH_OPTCR1_nWRP_9                  0x02000000U
-#define FLASH_OPTCR1_nWRP_10                 0x04000000U
-#define FLASH_OPTCR1_nWRP_11                 0x08000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Flexible Static Memory Controller                    */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for FSMC_BCR1 register  *******************/
-#define  FSMC_BCR1_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FSMC_BCR1_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FSMC_BCR1_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FSMC_BCR1_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FSMC_BCR1_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FSMC_BCR1_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR1_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FSMC_BCR1_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FSMC_BCR1_FACCEN                    0x00000040U        /*!<Flash access enable                    */
-#define  FSMC_BCR1_BURSTEN                   0x00000100U        /*!<Burst enable bit                       */
-#define  FSMC_BCR1_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit               */
-#define  FSMC_BCR1_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support             */
-#define  FSMC_BCR1_WAITCFG                   0x00000800U        /*!<Wait timing configuration              */
-#define  FSMC_BCR1_WREN                      0x00001000U        /*!<Write enable bit                       */
-#define  FSMC_BCR1_WAITEN                    0x00002000U        /*!<Wait enable bit                        */
-#define  FSMC_BCR1_EXTMOD                    0x00004000U        /*!<Extended mode enable                   */
-#define  FSMC_BCR1_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait                      */
-#define  FSMC_BCR1_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FSMC_BCR1_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FSMC_BCR1_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FSMC_BCR1_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FSMC_BCR1_CBURSTRW                  0x00080000U        /*!<Write burst enable                     */
-
-/******************  Bit definition for FSMC_BCR2 register  *******************/
-#define  FSMC_BCR2_MBKEN                     0x00000001U        /*!<Memory bank enable bit                */
-#define  FSMC_BCR2_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FSMC_BCR2_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FSMC_BCR2_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FSMC_BCR2_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FSMC_BCR2_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR2_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FSMC_BCR2_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FSMC_BCR2_FACCEN                    0x00000040U        /*!<Flash access enable                    */
-#define  FSMC_BCR2_BURSTEN                   0x00000100U        /*!<Burst enable bit                       */
-#define  FSMC_BCR2_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit               */
-#define  FSMC_BCR2_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support             */
-#define  FSMC_BCR2_WAITCFG                   0x00000800U        /*!<Wait timing configuration              */
-#define  FSMC_BCR2_WREN                      0x00001000U        /*!<Write enable bit                       */
-#define  FSMC_BCR2_WAITEN                    0x00002000U        /*!<Wait enable bit                        */
-#define  FSMC_BCR2_EXTMOD                    0x00004000U        /*!<Extended mode enable                   */
-#define  FSMC_BCR2_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait                      */
-#define  FSMC_BCR2_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FSMC_BCR2_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FSMC_BCR2_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FSMC_BCR2_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FSMC_BCR2_CBURSTRW                  0x00080000U        /*!<Write burst enable                     */
-
-/******************  Bit definition for FSMC_BCR3 register  *******************/
-#define  FSMC_BCR3_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FSMC_BCR3_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FSMC_BCR3_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FSMC_BCR3_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FSMC_BCR3_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FSMC_BCR3_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR3_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FSMC_BCR3_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FSMC_BCR3_FACCEN                    0x00000040U        /*!<Flash access enable                    */
-#define  FSMC_BCR3_BURSTEN                   0x00000100U        /*!<Burst enable bit                       */
-#define  FSMC_BCR3_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit               */
-#define  FSMC_BCR3_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support             */
-#define  FSMC_BCR3_WAITCFG                   0x00000800U        /*!<Wait timing configuration              */
-#define  FSMC_BCR3_WREN                      0x00001000U        /*!<Write enable bit                       */
-#define  FSMC_BCR3_WAITEN                    0x00002000U        /*!<Wait enable bit                        */
-#define  FSMC_BCR3_EXTMOD                    0x00004000U        /*!<Extended mode enable                   */
-#define  FSMC_BCR3_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait                      */
-#define  FSMC_BCR3_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FSMC_BCR3_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FSMC_BCR3_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FSMC_BCR3_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FSMC_BCR3_CBURSTRW                  0x00080000U        /*!<Write burst enable                     */
-
-/******************  Bit definition for FSMC_BCR4 register  *******************/
-#define  FSMC_BCR4_MBKEN                     0x00000001U        /*!<Memory bank enable bit */
-#define  FSMC_BCR4_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FSMC_BCR4_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FSMC_BCR4_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FSMC_BCR4_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FSMC_BCR4_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR4_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FSMC_BCR4_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FSMC_BCR4_FACCEN                    0x00000040U        /*!<Flash access enable                    */
-#define  FSMC_BCR4_BURSTEN                   0x00000100U        /*!<Burst enable bit                       */
-#define  FSMC_BCR4_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit               */
-#define  FSMC_BCR4_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support             */
-#define  FSMC_BCR4_WAITCFG                   0x00000800U        /*!<Wait timing configuration              */
-#define  FSMC_BCR4_WREN                      0x00001000U        /*!<Write enable bit                       */
-#define  FSMC_BCR4_WAITEN                    0x00002000U        /*!<Wait enable bit                        */
-#define  FSMC_BCR4_EXTMOD                    0x00004000U        /*!<Extended mode enable                   */
-#define  FSMC_BCR4_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait                      */
-#define  FSMC_BCR4_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FSMC_BCR4_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FSMC_BCR4_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FSMC_BCR4_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FSMC_BCR4_CBURSTRW                  0x00080000U        /*!<Write burst enable                     */
-
-/******************  Bit definition for FSMC_BTR1 register  ******************/
-#define  FSMC_BTR1_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR1_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FSMC_BTR1_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FSMC_BTR1_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FSMC_BTR1_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BTR1_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR1_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FSMC_BTR1_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FSMC_BTR1_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FSMC_BTR1_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BTR1_DATAST                    0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */
-#define  FSMC_BTR1_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FSMC_BTR1_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FSMC_BTR1_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FSMC_BTR1_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FSMC_BTR1_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FSMC_BTR1_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FSMC_BTR1_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FSMC_BTR1_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BTR1_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR1_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FSMC_BTR1_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FSMC_BTR1_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FSMC_BTR1_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BTR1_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR1_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FSMC_BTR1_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FSMC_BTR1_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FSMC_BTR1_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FSMC_BTR1_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR1_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FSMC_BTR1_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FSMC_BTR1_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FSMC_BTR1_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FSMC_BTR1_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR1_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FSMC_BTR1_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BTR2 register  *******************/
-#define  FSMC_BTR2_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR2_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FSMC_BTR2_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FSMC_BTR2_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FSMC_BTR2_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BTR2_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR2_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FSMC_BTR2_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FSMC_BTR2_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FSMC_BTR2_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BTR2_DATAST                    0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */
-#define  FSMC_BTR2_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FSMC_BTR2_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FSMC_BTR2_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FSMC_BTR2_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FSMC_BTR2_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FSMC_BTR2_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FSMC_BTR2_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FSMC_BTR2_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BTR2_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR2_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FSMC_BTR2_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FSMC_BTR2_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FSMC_BTR2_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BTR2_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR2_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FSMC_BTR2_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FSMC_BTR2_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FSMC_BTR2_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FSMC_BTR2_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR2_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FSMC_BTR2_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FSMC_BTR2_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FSMC_BTR2_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FSMC_BTR2_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR2_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FSMC_BTR2_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/*******************  Bit definition for FSMC_BTR3 register  *******************/
-#define  FSMC_BTR3_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR3_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FSMC_BTR3_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FSMC_BTR3_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FSMC_BTR3_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BTR3_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR3_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FSMC_BTR3_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FSMC_BTR3_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FSMC_BTR3_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BTR3_DATAST                    0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */
-#define  FSMC_BTR3_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FSMC_BTR3_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FSMC_BTR3_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FSMC_BTR3_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FSMC_BTR3_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FSMC_BTR3_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FSMC_BTR3_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FSMC_BTR3_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BTR3_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR3_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FSMC_BTR3_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FSMC_BTR3_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FSMC_BTR3_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BTR3_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR3_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FSMC_BTR3_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FSMC_BTR3_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FSMC_BTR3_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FSMC_BTR3_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR3_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FSMC_BTR3_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FSMC_BTR3_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FSMC_BTR3_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FSMC_BTR3_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR3_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FSMC_BTR3_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BTR4 register  *******************/
-#define  FSMC_BTR4_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR4_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FSMC_BTR4_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FSMC_BTR4_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FSMC_BTR4_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BTR4_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR4_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FSMC_BTR4_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FSMC_BTR4_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FSMC_BTR4_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BTR4_DATAST                    0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */
-#define  FSMC_BTR4_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FSMC_BTR4_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FSMC_BTR4_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FSMC_BTR4_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FSMC_BTR4_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FSMC_BTR4_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FSMC_BTR4_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FSMC_BTR4_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BTR4_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR4_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FSMC_BTR4_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FSMC_BTR4_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FSMC_BTR4_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BTR4_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR4_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FSMC_BTR4_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FSMC_BTR4_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FSMC_BTR4_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FSMC_BTR4_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR4_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FSMC_BTR4_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FSMC_BTR4_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FSMC_BTR4_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FSMC_BTR4_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR4_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FSMC_BTR4_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR1 register  ******************/
-#define  FSMC_BWTR1_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR1_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FSMC_BWTR1_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FSMC_BWTR1_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FSMC_BWTR1_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BWTR1_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR1_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FSMC_BWTR1_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FSMC_BWTR1_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FSMC_BWTR1_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BWTR1_DATAST                   0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */
-#define  FSMC_BWTR1_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FSMC_BWTR1_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FSMC_BWTR1_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FSMC_BWTR1_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FSMC_BWTR1_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FSMC_BWTR1_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FSMC_BWTR1_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FSMC_BWTR1_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BWTR1_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FSMC_BWTR1_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FSMC_BWTR1_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FSMC_BWTR1_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FSMC_BWTR1_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BWTR1_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR1_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FSMC_BWTR1_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR2 register  ******************/
-#define  FSMC_BWTR2_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR2_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FSMC_BWTR2_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FSMC_BWTR2_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FSMC_BWTR2_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BWTR2_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR2_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FSMC_BWTR2_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FSMC_BWTR2_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FSMC_BWTR2_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BWTR2_DATAST                   0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */
-#define  FSMC_BWTR2_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FSMC_BWTR2_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FSMC_BWTR2_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FSMC_BWTR2_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FSMC_BWTR2_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FSMC_BWTR2_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FSMC_BWTR2_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FSMC_BWTR2_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BWTR2_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FSMC_BWTR2_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FSMC_BWTR2_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FSMC_BWTR2_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FSMC_BWTR2_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BWTR2_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR2_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FSMC_BWTR2_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR3 register  ******************/
-#define  FSMC_BWTR3_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR3_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FSMC_BWTR3_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FSMC_BWTR3_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FSMC_BWTR3_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BWTR3_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR3_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FSMC_BWTR3_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FSMC_BWTR3_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FSMC_BWTR3_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BWTR3_DATAST                   0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */
-#define  FSMC_BWTR3_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FSMC_BWTR3_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FSMC_BWTR3_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FSMC_BWTR3_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FSMC_BWTR3_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FSMC_BWTR3_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FSMC_BWTR3_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FSMC_BWTR3_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BWTR3_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FSMC_BWTR3_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FSMC_BWTR3_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FSMC_BWTR3_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FSMC_BWTR3_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BWTR3_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR3_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FSMC_BWTR3_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR4 register  ******************/
-#define  FSMC_BWTR4_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR4_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FSMC_BWTR4_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FSMC_BWTR4_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FSMC_BWTR4_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BWTR4_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR4_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FSMC_BWTR4_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FSMC_BWTR4_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FSMC_BWTR4_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BWTR4_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BWTR4_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FSMC_BWTR4_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FSMC_BWTR4_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FSMC_BWTR4_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FSMC_BWTR4_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FSMC_BWTR4_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FSMC_BWTR4_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FSMC_BWTR4_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BWTR4_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FSMC_BWTR4_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FSMC_BWTR4_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FSMC_BWTR4_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FSMC_BWTR4_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BWTR4_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR4_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FSMC_BWTR4_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_PCR2 register  *******************/
-#define  FSMC_PCR2_PWAITEN                   0x00000002U        /*!<Wait feature enable bit */
-#define  FSMC_PCR2_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FSMC_PCR2_PTYP                      0x00000008U        /*!<Memory type */
-
-#define  FSMC_PCR2_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FSMC_PCR2_PWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FSMC_PCR2_PWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FSMC_PCR2_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit */
-
-#define  FSMC_PCR2_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay) */
-#define  FSMC_PCR2_TCLR_0                    0x00000200U        /*!<Bit 0 */
-#define  FSMC_PCR2_TCLR_1                    0x00000400U        /*!<Bit 1 */
-#define  FSMC_PCR2_TCLR_2                    0x00000800U        /*!<Bit 2 */
-#define  FSMC_PCR2_TCLR_3                    0x00001000U        /*!<Bit 3 */
-
-#define  FSMC_PCR2_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay) */
-#define  FSMC_PCR2_TAR_0                     0x00002000U        /*!<Bit 0 */
-#define  FSMC_PCR2_TAR_1                     0x00004000U        /*!<Bit 1 */
-#define  FSMC_PCR2_TAR_2                     0x00008000U        /*!<Bit 2 */
-#define  FSMC_PCR2_TAR_3                     0x00010000U        /*!<Bit 3 */
-
-#define  FSMC_PCR2_ECCPS                     0x000E0000U        /*!<ECCPS[1:0] bits (ECC page size) */
-#define  FSMC_PCR2_ECCPS_0                   0x00020000U        /*!<Bit 0 */
-#define  FSMC_PCR2_ECCPS_1                   0x00040000U        /*!<Bit 1 */
-#define  FSMC_PCR2_ECCPS_2                   0x00080000U        /*!<Bit 2 */
-
-/******************  Bit definition for FSMC_PCR3 register  *******************/
-#define  FSMC_PCR3_PWAITEN                   0x00000002U        /*!<Wait feature enable bit */
-#define  FSMC_PCR3_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FSMC_PCR3_PTYP                      0x00000008U        /*!<Memory type */
-
-#define  FSMC_PCR3_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FSMC_PCR3_PWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FSMC_PCR3_PWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FSMC_PCR3_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit */
-
-#define  FSMC_PCR3_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay) */
-#define  FSMC_PCR3_TCLR_0                    0x00000200U        /*!<Bit 0 */
-#define  FSMC_PCR3_TCLR_1                    0x00000400U        /*!<Bit 1 */
-#define  FSMC_PCR3_TCLR_2                    0x00000800U        /*!<Bit 2 */
-#define  FSMC_PCR3_TCLR_3                    0x00001000U        /*!<Bit 3 */
-
-#define  FSMC_PCR3_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay) */
-#define  FSMC_PCR3_TAR_0                     0x00002000U        /*!<Bit 0 */
-#define  FSMC_PCR3_TAR_1                     0x00004000U        /*!<Bit 1 */
-#define  FSMC_PCR3_TAR_2                     0x00008000U        /*!<Bit 2 */
-#define  FSMC_PCR3_TAR_3                     0x00010000U        /*!<Bit 3 */
-
-#define  FSMC_PCR3_ECCPS                     0x000E0000U        /*!<ECCPS[2:0] bits (ECC page size) */
-#define  FSMC_PCR3_ECCPS_0                   0x00020000U        /*!<Bit 0 */
-#define  FSMC_PCR3_ECCPS_1                   0x00040000U        /*!<Bit 1 */
-#define  FSMC_PCR3_ECCPS_2                   0x00080000U        /*!<Bit 2 */
-
-/******************  Bit definition for FSMC_PCR4 register  *******************/
-#define  FSMC_PCR4_PWAITEN                   0x00000002U        /*!<Wait feature enable bit */
-#define  FSMC_PCR4_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FSMC_PCR4_PTYP                      0x00000008U        /*!<Memory type */
-
-#define  FSMC_PCR4_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FSMC_PCR4_PWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FSMC_PCR4_PWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FSMC_PCR4_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit */
-
-#define  FSMC_PCR4_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay) */
-#define  FSMC_PCR4_TCLR_0                    0x00000200U        /*!<Bit 0 */
-#define  FSMC_PCR4_TCLR_1                    0x00000400U        /*!<Bit 1 */
-#define  FSMC_PCR4_TCLR_2                    0x00000800U        /*!<Bit 2 */
-#define  FSMC_PCR4_TCLR_3                    0x00001000U        /*!<Bit 3 */
-
-#define  FSMC_PCR4_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay) */
-#define  FSMC_PCR4_TAR_0                     0x00002000U        /*!<Bit 0 */
-#define  FSMC_PCR4_TAR_1                     0x00004000U        /*!<Bit 1 */
-#define  FSMC_PCR4_TAR_2                     0x00008000U        /*!<Bit 2 */
-#define  FSMC_PCR4_TAR_3                     0x00010000U        /*!<Bit 3 */
-
-#define  FSMC_PCR4_ECCPS                     0x000E0000U        /*!<ECCPS[2:0] bits (ECC page size) */
-#define  FSMC_PCR4_ECCPS_0                   0x00020000U        /*!<Bit 0 */
-#define  FSMC_PCR4_ECCPS_1                   0x00040000U        /*!<Bit 1 */
-#define  FSMC_PCR4_ECCPS_2                   0x00080000U        /*!<Bit 2 */
-
-/*******************  Bit definition for FSMC_SR2 register  *******************/
-#define  FSMC_SR2_IRS                        0x01U               /*!<Interrupt Rising Edge status                */
-#define  FSMC_SR2_ILS                        0x02U               /*!<Interrupt Level status                      */
-#define  FSMC_SR2_IFS                        0x04U               /*!<Interrupt Falling Edge status               */
-#define  FSMC_SR2_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FSMC_SR2_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit        */
-#define  FSMC_SR2_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FSMC_SR2_FEMPT                      0x40U               /*!<FIFO empty */
-
-/*******************  Bit definition for FSMC_SR3 register  *******************/
-#define  FSMC_SR3_IRS                        0x01U               /*!<Interrupt Rising Edge status                */
-#define  FSMC_SR3_ILS                        0x02U               /*!<Interrupt Level status                      */
-#define  FSMC_SR3_IFS                        0x04U               /*!<Interrupt Falling Edge status               */
-#define  FSMC_SR3_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FSMC_SR3_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit        */
-#define  FSMC_SR3_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FSMC_SR3_FEMPT                      0x40U               /*!<FIFO empty */
-
-/*******************  Bit definition for FSMC_SR4 register  *******************/
-#define  FSMC_SR4_IRS                        0x01U               /*!<Interrupt Rising Edge status                 */
-#define  FSMC_SR4_ILS                        0x02U               /*!<Interrupt Level status                       */
-#define  FSMC_SR4_IFS                        0x04U               /*!<Interrupt Falling Edge status                */
-#define  FSMC_SR4_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit   */
-#define  FSMC_SR4_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit         */
-#define  FSMC_SR4_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit  */
-#define  FSMC_SR4_FEMPT                      0x40U               /*!<FIFO empty */
-
-/******************  Bit definition for FSMC_PMEM2 register  ******************/
-#define  FSMC_PMEM2_MEMSET2                  0x000000FFU        /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
-#define  FSMC_PMEM2_MEMSET2_0                0x00000001U        /*!<Bit 0 */
-#define  FSMC_PMEM2_MEMSET2_1                0x00000002U        /*!<Bit 1 */
-#define  FSMC_PMEM2_MEMSET2_2                0x00000004U        /*!<Bit 2 */
-#define  FSMC_PMEM2_MEMSET2_3                0x00000008U        /*!<Bit 3 */
-#define  FSMC_PMEM2_MEMSET2_4                0x00000010U        /*!<Bit 4 */
-#define  FSMC_PMEM2_MEMSET2_5                0x00000020U        /*!<Bit 5 */
-#define  FSMC_PMEM2_MEMSET2_6                0x00000040U        /*!<Bit 6 */
-#define  FSMC_PMEM2_MEMSET2_7                0x00000080U        /*!<Bit 7 */
-
-#define  FSMC_PMEM2_MEMWAIT2                 0x0000FF00U        /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
-#define  FSMC_PMEM2_MEMWAIT2_0               0x00000100U        /*!<Bit 0 */
-#define  FSMC_PMEM2_MEMWAIT2_1               0x00000200U        /*!<Bit 1 */
-#define  FSMC_PMEM2_MEMWAIT2_2               0x00000400U        /*!<Bit 2 */
-#define  FSMC_PMEM2_MEMWAIT2_3               0x00000800U        /*!<Bit 3 */
-#define  FSMC_PMEM2_MEMWAIT2_4               0x00001000U        /*!<Bit 4 */
-#define  FSMC_PMEM2_MEMWAIT2_5               0x00002000U        /*!<Bit 5 */
-#define  FSMC_PMEM2_MEMWAIT2_6               0x00004000U        /*!<Bit 6 */
-#define  FSMC_PMEM2_MEMWAIT2_7               0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_PMEM2_MEMHOLD2                 0x00FF0000U        /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
-#define  FSMC_PMEM2_MEMHOLD2_0               0x00010000U        /*!<Bit 0 */
-#define  FSMC_PMEM2_MEMHOLD2_1               0x00020000U        /*!<Bit 1 */
-#define  FSMC_PMEM2_MEMHOLD2_2               0x00040000U        /*!<Bit 2 */
-#define  FSMC_PMEM2_MEMHOLD2_3               0x00080000U        /*!<Bit 3 */
-#define  FSMC_PMEM2_MEMHOLD2_4               0x00100000U        /*!<Bit 4 */
-#define  FSMC_PMEM2_MEMHOLD2_5               0x00200000U        /*!<Bit 5 */
-#define  FSMC_PMEM2_MEMHOLD2_6               0x00400000U        /*!<Bit 6 */
-#define  FSMC_PMEM2_MEMHOLD2_7               0x00800000U        /*!<Bit 7 */
-
-#define  FSMC_PMEM2_MEMHIZ2                  0xFF000000U        /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
-#define  FSMC_PMEM2_MEMHIZ2_0                0x01000000U        /*!<Bit 0 */
-#define  FSMC_PMEM2_MEMHIZ2_1                0x02000000U        /*!<Bit 1 */
-#define  FSMC_PMEM2_MEMHIZ2_2                0x04000000U        /*!<Bit 2 */
-#define  FSMC_PMEM2_MEMHIZ2_3                0x08000000U        /*!<Bit 3 */
-#define  FSMC_PMEM2_MEMHIZ2_4                0x10000000U        /*!<Bit 4 */
-#define  FSMC_PMEM2_MEMHIZ2_5                0x20000000U        /*!<Bit 5 */
-#define  FSMC_PMEM2_MEMHIZ2_6                0x40000000U        /*!<Bit 6 */
-#define  FSMC_PMEM2_MEMHIZ2_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FSMC_PMEM3 register  ******************/
-#define  FSMC_PMEM3_MEMSET3                  0x000000FFU        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
-#define  FSMC_PMEM3_MEMSET3_0                0x00000001U        /*!<Bit 0 */
-#define  FSMC_PMEM3_MEMSET3_1                0x00000002U        /*!<Bit 1 */
-#define  FSMC_PMEM3_MEMSET3_2                0x00000004U        /*!<Bit 2 */
-#define  FSMC_PMEM3_MEMSET3_3                0x00000008U        /*!<Bit 3 */
-#define  FSMC_PMEM3_MEMSET3_4                0x00000010U        /*!<Bit 4 */
-#define  FSMC_PMEM3_MEMSET3_5                0x00000020U        /*!<Bit 5 */
-#define  FSMC_PMEM3_MEMSET3_6                0x00000040U        /*!<Bit 6 */
-#define  FSMC_PMEM3_MEMSET3_7                0x00000080U        /*!<Bit 7 */
-
-#define  FSMC_PMEM3_MEMWAIT3                 0x0000FF00U        /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
-#define  FSMC_PMEM3_MEMWAIT3_0               0x00000100U        /*!<Bit 0 */
-#define  FSMC_PMEM3_MEMWAIT3_1               0x00000200U        /*!<Bit 1 */
-#define  FSMC_PMEM3_MEMWAIT3_2               0x00000400U        /*!<Bit 2 */
-#define  FSMC_PMEM3_MEMWAIT3_3               0x00000800U        /*!<Bit 3 */
-#define  FSMC_PMEM3_MEMWAIT3_4               0x00001000U        /*!<Bit 4 */
-#define  FSMC_PMEM3_MEMWAIT3_5               0x00002000U        /*!<Bit 5 */
-#define  FSMC_PMEM3_MEMWAIT3_6               0x00004000U        /*!<Bit 6 */
-#define  FSMC_PMEM3_MEMWAIT3_7               0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_PMEM3_MEMHOLD3                 0x00FF0000U        /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
-#define  FSMC_PMEM3_MEMHOLD3_0               0x00010000U        /*!<Bit 0 */
-#define  FSMC_PMEM3_MEMHOLD3_1               0x00020000U        /*!<Bit 1 */
-#define  FSMC_PMEM3_MEMHOLD3_2               0x00040000U        /*!<Bit 2 */
-#define  FSMC_PMEM3_MEMHOLD3_3               0x00080000U        /*!<Bit 3 */
-#define  FSMC_PMEM3_MEMHOLD3_4               0x00100000U        /*!<Bit 4 */
-#define  FSMC_PMEM3_MEMHOLD3_5               0x00200000U        /*!<Bit 5 */
-#define  FSMC_PMEM3_MEMHOLD3_6               0x00400000U        /*!<Bit 6 */
-#define  FSMC_PMEM3_MEMHOLD3_7               0x00800000U        /*!<Bit 7 */
-
-#define  FSMC_PMEM3_MEMHIZ3                  0xFF000000U        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
-#define  FSMC_PMEM3_MEMHIZ3_0                0x01000000U        /*!<Bit 0 */
-#define  FSMC_PMEM3_MEMHIZ3_1                0x02000000U        /*!<Bit 1 */
-#define  FSMC_PMEM3_MEMHIZ3_2                0x04000000U        /*!<Bit 2 */
-#define  FSMC_PMEM3_MEMHIZ3_3                0x08000000U        /*!<Bit 3 */
-#define  FSMC_PMEM3_MEMHIZ3_4                0x10000000U        /*!<Bit 4 */
-#define  FSMC_PMEM3_MEMHIZ3_5                0x20000000U        /*!<Bit 5 */
-#define  FSMC_PMEM3_MEMHIZ3_6                0x40000000U        /*!<Bit 6 */
-#define  FSMC_PMEM3_MEMHIZ3_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FSMC_PMEM4 register  ******************/
-#define  FSMC_PMEM4_MEMSET4                  0x000000FFU        /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
-#define  FSMC_PMEM4_MEMSET4_0                0x00000001U        /*!<Bit 0 */
-#define  FSMC_PMEM4_MEMSET4_1                0x00000002U        /*!<Bit 1 */
-#define  FSMC_PMEM4_MEMSET4_2                0x00000004U        /*!<Bit 2 */
-#define  FSMC_PMEM4_MEMSET4_3                0x00000008U        /*!<Bit 3 */
-#define  FSMC_PMEM4_MEMSET4_4                0x00000010U        /*!<Bit 4 */
-#define  FSMC_PMEM4_MEMSET4_5                0x00000020U        /*!<Bit 5 */
-#define  FSMC_PMEM4_MEMSET4_6                0x00000040U        /*!<Bit 6 */
-#define  FSMC_PMEM4_MEMSET4_7                0x00000080U        /*!<Bit 7 */
-
-#define  FSMC_PMEM4_MEMWAIT4                 0x0000FF00U        /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
-#define  FSMC_PMEM4_MEMWAIT4_0               0x00000100U        /*!<Bit 0 */
-#define  FSMC_PMEM4_MEMWAIT4_1               0x00000200U        /*!<Bit 1 */
-#define  FSMC_PMEM4_MEMWAIT4_2               0x00000400U        /*!<Bit 2 */
-#define  FSMC_PMEM4_MEMWAIT4_3               0x00000800U        /*!<Bit 3 */
-#define  FSMC_PMEM4_MEMWAIT4_4               0x00001000U        /*!<Bit 4 */
-#define  FSMC_PMEM4_MEMWAIT4_5               0x00002000U        /*!<Bit 5 */
-#define  FSMC_PMEM4_MEMWAIT4_6               0x00004000U        /*!<Bit 6 */
-#define  FSMC_PMEM4_MEMWAIT4_7               0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_PMEM4_MEMHOLD4                 0x00FF0000U        /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
-#define  FSMC_PMEM4_MEMHOLD4_0               0x00010000U        /*!<Bit 0 */
-#define  FSMC_PMEM4_MEMHOLD4_1               0x00020000U        /*!<Bit 1 */
-#define  FSMC_PMEM4_MEMHOLD4_2               0x00040000U        /*!<Bit 2 */
-#define  FSMC_PMEM4_MEMHOLD4_3               0x00080000U        /*!<Bit 3 */
-#define  FSMC_PMEM4_MEMHOLD4_4               0x00100000U        /*!<Bit 4 */
-#define  FSMC_PMEM4_MEMHOLD4_5               0x00200000U        /*!<Bit 5 */
-#define  FSMC_PMEM4_MEMHOLD4_6               0x00400000U        /*!<Bit 6 */
-#define  FSMC_PMEM4_MEMHOLD4_7               0x00800000U        /*!<Bit 7 */
-
-#define  FSMC_PMEM4_MEMHIZ4                  0xFF000000U        /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
-#define  FSMC_PMEM4_MEMHIZ4_0                0x01000000U        /*!<Bit 0 */
-#define  FSMC_PMEM4_MEMHIZ4_1                0x02000000U        /*!<Bit 1 */
-#define  FSMC_PMEM4_MEMHIZ4_2                0x04000000U        /*!<Bit 2 */
-#define  FSMC_PMEM4_MEMHIZ4_3                0x08000000U        /*!<Bit 3 */
-#define  FSMC_PMEM4_MEMHIZ4_4                0x10000000U        /*!<Bit 4 */
-#define  FSMC_PMEM4_MEMHIZ4_5                0x20000000U        /*!<Bit 5 */
-#define  FSMC_PMEM4_MEMHIZ4_6                0x40000000U        /*!<Bit 6 */
-#define  FSMC_PMEM4_MEMHIZ4_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FSMC_PATT2 register  ******************/
-#define  FSMC_PATT2_ATTSET2                  0x000000FFU        /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
-#define  FSMC_PATT2_ATTSET2_0                0x00000001U        /*!<Bit 0 */
-#define  FSMC_PATT2_ATTSET2_1                0x00000002U        /*!<Bit 1 */
-#define  FSMC_PATT2_ATTSET2_2                0x00000004U        /*!<Bit 2 */
-#define  FSMC_PATT2_ATTSET2_3                0x00000008U        /*!<Bit 3 */
-#define  FSMC_PATT2_ATTSET2_4                0x00000010U        /*!<Bit 4 */
-#define  FSMC_PATT2_ATTSET2_5                0x00000020U        /*!<Bit 5 */
-#define  FSMC_PATT2_ATTSET2_6                0x00000040U        /*!<Bit 6 */
-#define  FSMC_PATT2_ATTSET2_7                0x00000080U        /*!<Bit 7 */
-
-#define  FSMC_PATT2_ATTWAIT2                 0x0000FF00U        /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
-#define  FSMC_PATT2_ATTWAIT2_0               0x00000100U        /*!<Bit 0 */
-#define  FSMC_PATT2_ATTWAIT2_1               0x00000200U        /*!<Bit 1 */
-#define  FSMC_PATT2_ATTWAIT2_2               0x00000400U        /*!<Bit 2 */
-#define  FSMC_PATT2_ATTWAIT2_3               0x00000800U        /*!<Bit 3 */
-#define  FSMC_PATT2_ATTWAIT2_4               0x00001000U        /*!<Bit 4 */
-#define  FSMC_PATT2_ATTWAIT2_5               0x00002000U        /*!<Bit 5 */
-#define  FSMC_PATT2_ATTWAIT2_6               0x00004000U        /*!<Bit 6 */
-#define  FSMC_PATT2_ATTWAIT2_7               0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_PATT2_ATTHOLD2                 0x00FF0000U        /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
-#define  FSMC_PATT2_ATTHOLD2_0               0x00010000U        /*!<Bit 0 */
-#define  FSMC_PATT2_ATTHOLD2_1               0x00020000U        /*!<Bit 1 */
-#define  FSMC_PATT2_ATTHOLD2_2               0x00040000U        /*!<Bit 2 */
-#define  FSMC_PATT2_ATTHOLD2_3               0x00080000U        /*!<Bit 3 */
-#define  FSMC_PATT2_ATTHOLD2_4               0x00100000U        /*!<Bit 4 */
-#define  FSMC_PATT2_ATTHOLD2_5               0x00200000U        /*!<Bit 5 */
-#define  FSMC_PATT2_ATTHOLD2_6               0x00400000U        /*!<Bit 6 */
-#define  FSMC_PATT2_ATTHOLD2_7               0x00800000U        /*!<Bit 7 */
-
-#define  FSMC_PATT2_ATTHIZ2                  0xFF000000U        /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
-#define  FSMC_PATT2_ATTHIZ2_0                0x01000000U        /*!<Bit 0 */
-#define  FSMC_PATT2_ATTHIZ2_1                0x02000000U        /*!<Bit 1 */
-#define  FSMC_PATT2_ATTHIZ2_2                0x04000000U        /*!<Bit 2 */
-#define  FSMC_PATT2_ATTHIZ2_3                0x08000000U        /*!<Bit 3 */
-#define  FSMC_PATT2_ATTHIZ2_4                0x10000000U        /*!<Bit 4 */
-#define  FSMC_PATT2_ATTHIZ2_5                0x20000000U        /*!<Bit 5 */
-#define  FSMC_PATT2_ATTHIZ2_6                0x40000000U        /*!<Bit 6 */
-#define  FSMC_PATT2_ATTHIZ2_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FSMC_PATT3 register  ******************/
-#define  FSMC_PATT3_ATTSET3                  0x000000FFU        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
-#define  FSMC_PATT3_ATTSET3_0                0x00000001U        /*!<Bit 0 */
-#define  FSMC_PATT3_ATTSET3_1                0x00000002U        /*!<Bit 1 */
-#define  FSMC_PATT3_ATTSET3_2                0x00000004U        /*!<Bit 2 */
-#define  FSMC_PATT3_ATTSET3_3                0x00000008U        /*!<Bit 3 */
-#define  FSMC_PATT3_ATTSET3_4                0x00000010U        /*!<Bit 4 */
-#define  FSMC_PATT3_ATTSET3_5                0x00000020U        /*!<Bit 5 */
-#define  FSMC_PATT3_ATTSET3_6                0x00000040U        /*!<Bit 6 */
-#define  FSMC_PATT3_ATTSET3_7                0x00000080U        /*!<Bit 7 */
-
-#define  FSMC_PATT3_ATTWAIT3                 0x0000FF00U        /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
-#define  FSMC_PATT3_ATTWAIT3_0               0x00000100U        /*!<Bit 0 */
-#define  FSMC_PATT3_ATTWAIT3_1               0x00000200U        /*!<Bit 1 */
-#define  FSMC_PATT3_ATTWAIT3_2               0x00000400U        /*!<Bit 2 */
-#define  FSMC_PATT3_ATTWAIT3_3               0x00000800U        /*!<Bit 3 */
-#define  FSMC_PATT3_ATTWAIT3_4               0x00001000U        /*!<Bit 4 */
-#define  FSMC_PATT3_ATTWAIT3_5               0x00002000U        /*!<Bit 5 */
-#define  FSMC_PATT3_ATTWAIT3_6               0x00004000U        /*!<Bit 6 */
-#define  FSMC_PATT3_ATTWAIT3_7               0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_PATT3_ATTHOLD3                 0x00FF0000U        /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
-#define  FSMC_PATT3_ATTHOLD3_0               0x00010000U        /*!<Bit 0 */
-#define  FSMC_PATT3_ATTHOLD3_1               0x00020000U        /*!<Bit 1 */
-#define  FSMC_PATT3_ATTHOLD3_2               0x00040000U        /*!<Bit 2 */
-#define  FSMC_PATT3_ATTHOLD3_3               0x00080000U        /*!<Bit 3 */
-#define  FSMC_PATT3_ATTHOLD3_4               0x00100000U        /*!<Bit 4 */
-#define  FSMC_PATT3_ATTHOLD3_5               0x00200000U        /*!<Bit 5 */
-#define  FSMC_PATT3_ATTHOLD3_6               0x00400000U        /*!<Bit 6 */
-#define  FSMC_PATT3_ATTHOLD3_7               0x00800000U        /*!<Bit 7 */
-
-#define  FSMC_PATT3_ATTHIZ3                  0xFF000000U        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
-#define  FSMC_PATT3_ATTHIZ3_0                0x01000000U        /*!<Bit 0 */
-#define  FSMC_PATT3_ATTHIZ3_1                0x02000000U        /*!<Bit 1 */
-#define  FSMC_PATT3_ATTHIZ3_2                0x04000000U        /*!<Bit 2 */
-#define  FSMC_PATT3_ATTHIZ3_3                0x08000000U        /*!<Bit 3 */
-#define  FSMC_PATT3_ATTHIZ3_4                0x10000000U        /*!<Bit 4 */
-#define  FSMC_PATT3_ATTHIZ3_5                0x20000000U        /*!<Bit 5 */
-#define  FSMC_PATT3_ATTHIZ3_6                0x40000000U        /*!<Bit 6 */
-#define  FSMC_PATT3_ATTHIZ3_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FSMC_PATT4 register  ******************/
-#define  FSMC_PATT4_ATTSET4                  0x000000FFU        /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
-#define  FSMC_PATT4_ATTSET4_0                0x00000001U        /*!<Bit 0 */
-#define  FSMC_PATT4_ATTSET4_1                0x00000002U        /*!<Bit 1 */
-#define  FSMC_PATT4_ATTSET4_2                0x00000004U        /*!<Bit 2 */
-#define  FSMC_PATT4_ATTSET4_3                0x00000008U        /*!<Bit 3 */
-#define  FSMC_PATT4_ATTSET4_4                0x00000010U        /*!<Bit 4 */
-#define  FSMC_PATT4_ATTSET4_5                0x00000020U        /*!<Bit 5 */
-#define  FSMC_PATT4_ATTSET4_6                0x00000040U        /*!<Bit 6 */
-#define  FSMC_PATT4_ATTSET4_7                0x00000080U        /*!<Bit 7 */
-
-#define  FSMC_PATT4_ATTWAIT4                 0x0000FF00U        /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
-#define  FSMC_PATT4_ATTWAIT4_0               0x00000100U        /*!<Bit 0 */
-#define  FSMC_PATT4_ATTWAIT4_1               0x00000200U        /*!<Bit 1 */
-#define  FSMC_PATT4_ATTWAIT4_2               0x00000400U        /*!<Bit 2 */
-#define  FSMC_PATT4_ATTWAIT4_3               0x00000800U        /*!<Bit 3 */
-#define  FSMC_PATT4_ATTWAIT4_4               0x00001000U        /*!<Bit 4 */
-#define  FSMC_PATT4_ATTWAIT4_5               0x00002000U        /*!<Bit 5 */
-#define  FSMC_PATT4_ATTWAIT4_6               0x00004000U        /*!<Bit 6 */
-#define  FSMC_PATT4_ATTWAIT4_7               0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_PATT4_ATTHOLD4                 0x00FF0000U        /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
-#define  FSMC_PATT4_ATTHOLD4_0               0x00010000U        /*!<Bit 0 */
-#define  FSMC_PATT4_ATTHOLD4_1               0x00020000U        /*!<Bit 1 */
-#define  FSMC_PATT4_ATTHOLD4_2               0x00040000U        /*!<Bit 2 */
-#define  FSMC_PATT4_ATTHOLD4_3               0x00080000U        /*!<Bit 3 */
-#define  FSMC_PATT4_ATTHOLD4_4               0x00100000U        /*!<Bit 4 */
-#define  FSMC_PATT4_ATTHOLD4_5               0x00200000U        /*!<Bit 5 */
-#define  FSMC_PATT4_ATTHOLD4_6               0x00400000U        /*!<Bit 6 */
-#define  FSMC_PATT4_ATTHOLD4_7               0x00800000U        /*!<Bit 7 */
-
-#define  FSMC_PATT4_ATTHIZ4                  0xFF000000U        /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
-#define  FSMC_PATT4_ATTHIZ4_0                0x01000000U        /*!<Bit 0 */
-#define  FSMC_PATT4_ATTHIZ4_1                0x02000000U        /*!<Bit 1 */
-#define  FSMC_PATT4_ATTHIZ4_2                0x04000000U        /*!<Bit 2 */
-#define  FSMC_PATT4_ATTHIZ4_3                0x08000000U        /*!<Bit 3 */
-#define  FSMC_PATT4_ATTHIZ4_4                0x10000000U        /*!<Bit 4 */
-#define  FSMC_PATT4_ATTHIZ4_5                0x20000000U        /*!<Bit 5 */
-#define  FSMC_PATT4_ATTHIZ4_6                0x40000000U        /*!<Bit 6 */
-#define  FSMC_PATT4_ATTHIZ4_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FSMC_PIO4 register  *******************/
-#define  FSMC_PIO4_IOSET4                    0x000000FFU        /*!<IOSET4[7:0] bits (I/O 4 setup time) */
-#define  FSMC_PIO4_IOSET4_0                  0x00000001U        /*!<Bit 0 */
-#define  FSMC_PIO4_IOSET4_1                  0x00000002U        /*!<Bit 1 */
-#define  FSMC_PIO4_IOSET4_2                  0x00000004U        /*!<Bit 2 */
-#define  FSMC_PIO4_IOSET4_3                  0x00000008U        /*!<Bit 3 */
-#define  FSMC_PIO4_IOSET4_4                  0x00000010U        /*!<Bit 4 */
-#define  FSMC_PIO4_IOSET4_5                  0x00000020U        /*!<Bit 5 */
-#define  FSMC_PIO4_IOSET4_6                  0x00000040U        /*!<Bit 6 */
-#define  FSMC_PIO4_IOSET4_7                  0x00000080U        /*!<Bit 7 */
-
-#define  FSMC_PIO4_IOWAIT4                   0x0000FF00U        /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
-#define  FSMC_PIO4_IOWAIT4_0                 0x00000100U        /*!<Bit 0 */
-#define  FSMC_PIO4_IOWAIT4_1                 0x00000200U        /*!<Bit 1 */
-#define  FSMC_PIO4_IOWAIT4_2                 0x00000400U        /*!<Bit 2 */
-#define  FSMC_PIO4_IOWAIT4_3                 0x00000800U        /*!<Bit 3 */
-#define  FSMC_PIO4_IOWAIT4_4                 0x00001000U        /*!<Bit 4 */
-#define  FSMC_PIO4_IOWAIT4_5                 0x00002000U        /*!<Bit 5 */
-#define  FSMC_PIO4_IOWAIT4_6                 0x00004000U        /*!<Bit 6 */
-#define  FSMC_PIO4_IOWAIT4_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_PIO4_IOHOLD4                   0x00FF0000U        /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
-#define  FSMC_PIO4_IOHOLD4_0                 0x00010000U        /*!<Bit 0 */
-#define  FSMC_PIO4_IOHOLD4_1                 0x00020000U        /*!<Bit 1 */
-#define  FSMC_PIO4_IOHOLD4_2                 0x00040000U        /*!<Bit 2 */
-#define  FSMC_PIO4_IOHOLD4_3                 0x00080000U        /*!<Bit 3 */
-#define  FSMC_PIO4_IOHOLD4_4                 0x00100000U        /*!<Bit 4 */
-#define  FSMC_PIO4_IOHOLD4_5                 0x00200000U        /*!<Bit 5 */
-#define  FSMC_PIO4_IOHOLD4_6                 0x00400000U        /*!<Bit 6 */
-#define  FSMC_PIO4_IOHOLD4_7                 0x00800000U        /*!<Bit 7 */
-
-#define  FSMC_PIO4_IOHIZ4                    0xFF000000U        /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
-#define  FSMC_PIO4_IOHIZ4_0                  0x01000000U        /*!<Bit 0 */
-#define  FSMC_PIO4_IOHIZ4_1                  0x02000000U        /*!<Bit 1 */
-#define  FSMC_PIO4_IOHIZ4_2                  0x04000000U        /*!<Bit 2 */
-#define  FSMC_PIO4_IOHIZ4_3                  0x08000000U        /*!<Bit 3 */
-#define  FSMC_PIO4_IOHIZ4_4                  0x10000000U        /*!<Bit 4 */
-#define  FSMC_PIO4_IOHIZ4_5                  0x20000000U        /*!<Bit 5 */
-#define  FSMC_PIO4_IOHIZ4_6                  0x40000000U        /*!<Bit 6 */
-#define  FSMC_PIO4_IOHIZ4_7                  0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FSMC_ECCR2 register  ******************/
-#define  FSMC_ECCR2_ECC2                     0xFFFFFFFFU        /*!<ECC result */
-
-/******************  Bit definition for FSMC_ECCR3 register  ******************/
-#define  FSMC_ECCR3_ECC3                     0xFFFFFFFFU        /*!<ECC result */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    0x00000003U
-#define GPIO_MODER_MODER0_0                  0x00000001U
-#define GPIO_MODER_MODER0_1                  0x00000002U
-
-#define GPIO_MODER_MODER1                    0x0000000CU
-#define GPIO_MODER_MODER1_0                  0x00000004U
-#define GPIO_MODER_MODER1_1                  0x00000008U
-
-#define GPIO_MODER_MODER2                    0x00000030U
-#define GPIO_MODER_MODER2_0                  0x00000010U
-#define GPIO_MODER_MODER2_1                  0x00000020U
-
-#define GPIO_MODER_MODER3                    0x000000C0U
-#define GPIO_MODER_MODER3_0                  0x00000040U
-#define GPIO_MODER_MODER3_1                  0x00000080U
-
-#define GPIO_MODER_MODER4                    0x00000300U
-#define GPIO_MODER_MODER4_0                  0x00000100U
-#define GPIO_MODER_MODER4_1                  0x00000200U
-
-#define GPIO_MODER_MODER5                    0x00000C00U
-#define GPIO_MODER_MODER5_0                  0x00000400U
-#define GPIO_MODER_MODER5_1                  0x00000800U
-
-#define GPIO_MODER_MODER6                    0x00003000U
-#define GPIO_MODER_MODER6_0                  0x00001000U
-#define GPIO_MODER_MODER6_1                  0x00002000U
-
-#define GPIO_MODER_MODER7                    0x0000C000U
-#define GPIO_MODER_MODER7_0                  0x00004000U
-#define GPIO_MODER_MODER7_1                  0x00008000U
-
-#define GPIO_MODER_MODER8                    0x00030000U
-#define GPIO_MODER_MODER8_0                  0x00010000U
-#define GPIO_MODER_MODER8_1                  0x00020000U
-
-#define GPIO_MODER_MODER9                    0x000C0000U
-#define GPIO_MODER_MODER9_0                  0x00040000U
-#define GPIO_MODER_MODER9_1                  0x00080000U
-
-#define GPIO_MODER_MODER10                   0x00300000U
-#define GPIO_MODER_MODER10_0                 0x00100000U
-#define GPIO_MODER_MODER10_1                 0x00200000U
-
-#define GPIO_MODER_MODER11                   0x00C00000U
-#define GPIO_MODER_MODER11_0                 0x00400000U
-#define GPIO_MODER_MODER11_1                 0x00800000U
-
-#define GPIO_MODER_MODER12                   0x03000000U
-#define GPIO_MODER_MODER12_0                 0x01000000U
-#define GPIO_MODER_MODER12_1                 0x02000000U
-
-#define GPIO_MODER_MODER13                   0x0C000000U
-#define GPIO_MODER_MODER13_0                 0x04000000U
-#define GPIO_MODER_MODER13_1                 0x08000000U
-
-#define GPIO_MODER_MODER14                   0x30000000U
-#define GPIO_MODER_MODER14_0                 0x10000000U
-#define GPIO_MODER_MODER14_1                 0x20000000U
-
-#define GPIO_MODER_MODER15                   0xC0000000U
-#define GPIO_MODER_MODER15_0                 0x40000000U
-#define GPIO_MODER_MODER15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     0x00000001U
-#define GPIO_OTYPER_OT_1                     0x00000002U
-#define GPIO_OTYPER_OT_2                     0x00000004U
-#define GPIO_OTYPER_OT_3                     0x00000008U
-#define GPIO_OTYPER_OT_4                     0x00000010U
-#define GPIO_OTYPER_OT_5                     0x00000020U
-#define GPIO_OTYPER_OT_6                     0x00000040U
-#define GPIO_OTYPER_OT_7                     0x00000080U
-#define GPIO_OTYPER_OT_8                     0x00000100U
-#define GPIO_OTYPER_OT_9                     0x00000200U
-#define GPIO_OTYPER_OT_10                    0x00000400U
-#define GPIO_OTYPER_OT_11                    0x00000800U
-#define GPIO_OTYPER_OT_12                    0x00001000U
-#define GPIO_OTYPER_OT_13                    0x00002000U
-#define GPIO_OTYPER_OT_14                    0x00004000U
-#define GPIO_OTYPER_OT_15                    0x00008000U
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
-#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
-#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
-
-#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
-#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
-#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
-
-#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
-#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
-#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
-
-#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
-#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
-#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
-
-#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
-#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
-#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
-
-#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
-#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
-#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
-
-#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
-#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
-#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
-
-#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
-#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
-#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
-
-#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
-#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
-#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
-
-#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
-#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
-#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
-
-#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
-#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
-#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
-
-#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
-#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
-#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
-
-#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
-#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
-#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
-
-#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
-#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
-#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
-
-#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
-#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
-#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
-
-#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
-#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
-#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    0x00000003U
-#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
-#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
-
-#define GPIO_PUPDR_PUPDR1                    0x0000000CU
-#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
-#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
-
-#define GPIO_PUPDR_PUPDR2                    0x00000030U
-#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
-#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
-
-#define GPIO_PUPDR_PUPDR3                    0x000000C0U
-#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
-#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
-
-#define GPIO_PUPDR_PUPDR4                    0x00000300U
-#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
-#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
-
-#define GPIO_PUPDR_PUPDR5                    0x00000C00U
-#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
-#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
-
-#define GPIO_PUPDR_PUPDR6                    0x00003000U
-#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
-#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
-
-#define GPIO_PUPDR_PUPDR7                    0x0000C000U
-#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
-#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
-
-#define GPIO_PUPDR_PUPDR8                    0x00030000U
-#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
-#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
-
-#define GPIO_PUPDR_PUPDR9                    0x000C0000U
-#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
-#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
-
-#define GPIO_PUPDR_PUPDR10                   0x00300000U
-#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
-#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
-
-#define GPIO_PUPDR_PUPDR11                   0x00C00000U
-#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
-#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
-
-#define GPIO_PUPDR_PUPDR12                   0x03000000U
-#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
-#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
-
-#define GPIO_PUPDR_PUPDR13                   0x0C000000U
-#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
-#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
-
-#define GPIO_PUPDR_PUPDR14                   0x30000000U
-#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
-#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
-
-#define GPIO_PUPDR_PUPDR15                   0xC0000000U
-#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
-#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       0x00000001U
-#define GPIO_IDR_IDR_1                       0x00000002U
-#define GPIO_IDR_IDR_2                       0x00000004U
-#define GPIO_IDR_IDR_3                       0x00000008U
-#define GPIO_IDR_IDR_4                       0x00000010U
-#define GPIO_IDR_IDR_5                       0x00000020U
-#define GPIO_IDR_IDR_6                       0x00000040U
-#define GPIO_IDR_IDR_7                       0x00000080U
-#define GPIO_IDR_IDR_8                       0x00000100U
-#define GPIO_IDR_IDR_9                       0x00000200U
-#define GPIO_IDR_IDR_10                      0x00000400U
-#define GPIO_IDR_IDR_11                      0x00000800U
-#define GPIO_IDR_IDR_12                      0x00001000U
-#define GPIO_IDR_IDR_13                      0x00002000U
-#define GPIO_IDR_IDR_14                      0x00004000U
-#define GPIO_IDR_IDR_15                      0x00008000U
-/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
-#define GPIO_OTYPER_IDR_0                    GPIO_IDR_IDR_0
-#define GPIO_OTYPER_IDR_1                    GPIO_IDR_IDR_1
-#define GPIO_OTYPER_IDR_2                    GPIO_IDR_IDR_2
-#define GPIO_OTYPER_IDR_3                    GPIO_IDR_IDR_3
-#define GPIO_OTYPER_IDR_4                    GPIO_IDR_IDR_4
-#define GPIO_OTYPER_IDR_5                    GPIO_IDR_IDR_5
-#define GPIO_OTYPER_IDR_6                    GPIO_IDR_IDR_6
-#define GPIO_OTYPER_IDR_7                    GPIO_IDR_IDR_7
-#define GPIO_OTYPER_IDR_8                    GPIO_IDR_IDR_8
-#define GPIO_OTYPER_IDR_9                    GPIO_IDR_IDR_9
-#define GPIO_OTYPER_IDR_10                   GPIO_IDR_IDR_10
-#define GPIO_OTYPER_IDR_11                   GPIO_IDR_IDR_11
-#define GPIO_OTYPER_IDR_12                   GPIO_IDR_IDR_12
-#define GPIO_OTYPER_IDR_13                   GPIO_IDR_IDR_13
-#define GPIO_OTYPER_IDR_14                   GPIO_IDR_IDR_14
-#define GPIO_OTYPER_IDR_15                   GPIO_IDR_IDR_15
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       0x00000001U
-#define GPIO_ODR_ODR_1                       0x00000002U
-#define GPIO_ODR_ODR_2                       0x00000004U
-#define GPIO_ODR_ODR_3                       0x00000008U
-#define GPIO_ODR_ODR_4                       0x00000010U
-#define GPIO_ODR_ODR_5                       0x00000020U
-#define GPIO_ODR_ODR_6                       0x00000040U
-#define GPIO_ODR_ODR_7                       0x00000080U
-#define GPIO_ODR_ODR_8                       0x00000100U
-#define GPIO_ODR_ODR_9                       0x00000200U
-#define GPIO_ODR_ODR_10                      0x00000400U
-#define GPIO_ODR_ODR_11                      0x00000800U
-#define GPIO_ODR_ODR_12                      0x00001000U
-#define GPIO_ODR_ODR_13                      0x00002000U
-#define GPIO_ODR_ODR_14                      0x00004000U
-#define GPIO_ODR_ODR_15                      0x00008000U
-/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
-#define GPIO_OTYPER_ODR_0                    GPIO_ODR_ODR_0
-#define GPIO_OTYPER_ODR_1                    GPIO_ODR_ODR_1
-#define GPIO_OTYPER_ODR_2                    GPIO_ODR_ODR_2
-#define GPIO_OTYPER_ODR_3                    GPIO_ODR_ODR_3
-#define GPIO_OTYPER_ODR_4                    GPIO_ODR_ODR_4
-#define GPIO_OTYPER_ODR_5                    GPIO_ODR_ODR_5
-#define GPIO_OTYPER_ODR_6                    GPIO_ODR_ODR_6
-#define GPIO_OTYPER_ODR_7                    GPIO_ODR_ODR_7
-#define GPIO_OTYPER_ODR_8                    GPIO_ODR_ODR_8
-#define GPIO_OTYPER_ODR_9                    GPIO_ODR_ODR_9
-#define GPIO_OTYPER_ODR_10                   GPIO_ODR_ODR_10
-#define GPIO_OTYPER_ODR_11                   GPIO_ODR_ODR_11
-#define GPIO_OTYPER_ODR_12                   GPIO_ODR_ODR_12
-#define GPIO_OTYPER_ODR_13                   GPIO_ODR_ODR_13
-#define GPIO_OTYPER_ODR_14                   GPIO_ODR_ODR_14
-#define GPIO_OTYPER_ODR_15                   GPIO_ODR_ODR_15
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       0x00000001U
-#define GPIO_BSRR_BS_1                       0x00000002U
-#define GPIO_BSRR_BS_2                       0x00000004U
-#define GPIO_BSRR_BS_3                       0x00000008U
-#define GPIO_BSRR_BS_4                       0x00000010U
-#define GPIO_BSRR_BS_5                       0x00000020U
-#define GPIO_BSRR_BS_6                       0x00000040U
-#define GPIO_BSRR_BS_7                       0x00000080U
-#define GPIO_BSRR_BS_8                       0x00000100U
-#define GPIO_BSRR_BS_9                       0x00000200U
-#define GPIO_BSRR_BS_10                      0x00000400U
-#define GPIO_BSRR_BS_11                      0x00000800U
-#define GPIO_BSRR_BS_12                      0x00001000U
-#define GPIO_BSRR_BS_13                      0x00002000U
-#define GPIO_BSRR_BS_14                      0x00004000U
-#define GPIO_BSRR_BS_15                      0x00008000U
-#define GPIO_BSRR_BR_0                       0x00010000U
-#define GPIO_BSRR_BR_1                       0x00020000U
-#define GPIO_BSRR_BR_2                       0x00040000U
-#define GPIO_BSRR_BR_3                       0x00080000U
-#define GPIO_BSRR_BR_4                       0x00100000U
-#define GPIO_BSRR_BR_5                       0x00200000U
-#define GPIO_BSRR_BR_6                       0x00400000U
-#define GPIO_BSRR_BR_7                       0x00800000U
-#define GPIO_BSRR_BR_8                       0x01000000U
-#define GPIO_BSRR_BR_9                       0x02000000U
-#define GPIO_BSRR_BR_10                      0x04000000U
-#define GPIO_BSRR_BR_11                      0x08000000U
-#define GPIO_BSRR_BR_12                      0x10000000U
-#define GPIO_BSRR_BR_13                      0x20000000U
-#define GPIO_BSRR_BR_14                      0x40000000U
-#define GPIO_BSRR_BR_15                      0x80000000U
-
-/****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0                       0x00000001U
-#define GPIO_LCKR_LCK1                       0x00000002U
-#define GPIO_LCKR_LCK2                       0x00000004U
-#define GPIO_LCKR_LCK3                       0x00000008U
-#define GPIO_LCKR_LCK4                       0x00000010U
-#define GPIO_LCKR_LCK5                       0x00000020U
-#define GPIO_LCKR_LCK6                       0x00000040U
-#define GPIO_LCKR_LCK7                       0x00000080U
-#define GPIO_LCKR_LCK8                       0x00000100U
-#define GPIO_LCKR_LCK9                       0x00000200U
-#define GPIO_LCKR_LCK10                      0x00000400U
-#define GPIO_LCKR_LCK11                      0x00000800U
-#define GPIO_LCKR_LCK12                      0x00001000U
-#define GPIO_LCKR_LCK13                      0x00002000U
-#define GPIO_LCKR_LCK14                      0x00004000U
-#define GPIO_LCKR_LCK15                      0x00008000U
-#define GPIO_LCKR_LCKK                       0x00010000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Inter-integrated Circuit Interface                    */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          0x00000001U     /*!<Peripheral Enable                             */
-#define  I2C_CR1_SMBUS                       0x00000002U     /*!<SMBus Mode                                    */
-#define  I2C_CR1_SMBTYPE                     0x00000008U     /*!<SMBus Type                                    */
-#define  I2C_CR1_ENARP                       0x00000010U     /*!<ARP Enable                                    */
-#define  I2C_CR1_ENPEC                       0x00000020U     /*!<PEC Enable                                    */
-#define  I2C_CR1_ENGC                        0x00000040U     /*!<General Call Enable                           */
-#define  I2C_CR1_NOSTRETCH                   0x00000080U     /*!<Clock Stretching Disable (Slave mode)  */
-#define  I2C_CR1_START                       0x00000100U     /*!<Start Generation                              */
-#define  I2C_CR1_STOP                        0x00000200U     /*!<Stop Generation                               */
-#define  I2C_CR1_ACK                         0x00000400U     /*!<Acknowledge Enable                            */
-#define  I2C_CR1_POS                         0x00000800U     /*!<Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         0x00001000U     /*!<Packet Error Checking                         */
-#define  I2C_CR1_ALERT                       0x00002000U     /*!<SMBus Alert                                   */
-#define  I2C_CR1_SWRST                       0x00008000U     /*!<Software Reset                                */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        0x0000003FU     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
-#define  I2C_CR2_FREQ_0                      0x00000001U     /*!<Bit 0 */
-#define  I2C_CR2_FREQ_1                      0x00000002U     /*!<Bit 1 */
-#define  I2C_CR2_FREQ_2                      0x00000004U     /*!<Bit 2 */
-#define  I2C_CR2_FREQ_3                      0x00000008U     /*!<Bit 3 */
-#define  I2C_CR2_FREQ_4                      0x00000010U     /*!<Bit 4 */
-#define  I2C_CR2_FREQ_5                      0x00000020U     /*!<Bit 5 */
-
-#define  I2C_CR2_ITERREN                     0x00000100U     /*!<Error Interrupt Enable  */
-#define  I2C_CR2_ITEVTEN                     0x00000200U     /*!<Event Interrupt Enable  */
-#define  I2C_CR2_ITBUFEN                     0x00000400U     /*!<Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       0x00000800U     /*!<DMA Requests Enable     */
-#define  I2C_CR2_LAST                        0x00001000U     /*!<DMA Last Transfer       */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     0x000000FEU     /*!<Interface Address */
-#define  I2C_OAR1_ADD8_9                     0x00000300U     /*!<Interface Address */
-
-#define  I2C_OAR1_ADD0                       0x00000001U     /*!<Bit 0 */
-#define  I2C_OAR1_ADD1                       0x00000002U     /*!<Bit 1 */
-#define  I2C_OAR1_ADD2                       0x00000004U     /*!<Bit 2 */
-#define  I2C_OAR1_ADD3                       0x00000008U     /*!<Bit 3 */
-#define  I2C_OAR1_ADD4                       0x00000010U     /*!<Bit 4 */
-#define  I2C_OAR1_ADD5                       0x00000020U     /*!<Bit 5 */
-#define  I2C_OAR1_ADD6                       0x00000040U     /*!<Bit 6 */
-#define  I2C_OAR1_ADD7                       0x00000080U     /*!<Bit 7 */
-#define  I2C_OAR1_ADD8                       0x00000100U     /*!<Bit 8 */
-#define  I2C_OAR1_ADD9                       0x00000200U     /*!<Bit 9 */
-
-#define  I2C_OAR1_ADDMODE                    0x00008000U     /*!<Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     0x00000001U        /*!<Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       0x000000FEU        /*!<Interface address           */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           0x000000FFU        /*!<8-bit Data Register         */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          0x00000001U     /*!<Start Bit (Master mode)                  */
-#define  I2C_SR1_ADDR                        0x00000002U     /*!<Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         0x00000004U     /*!<Byte Transfer Finished                          */
-#define  I2C_SR1_ADD10                       0x00000008U     /*!<10-bit header sent (Master mode)         */
-#define  I2C_SR1_STOPF                       0x00000010U     /*!<Stop detection (Slave mode)              */
-#define  I2C_SR1_RXNE                        0x00000040U     /*!<Data Register not Empty (receivers)      */
-#define  I2C_SR1_TXE                         0x00000080U     /*!<Data Register Empty (transmitters)       */
-#define  I2C_SR1_BERR                        0x00000100U     /*!<Bus Error                                       */
-#define  I2C_SR1_ARLO                        0x00000200U     /*!<Arbitration Lost (master mode)           */
-#define  I2C_SR1_AF                          0x00000400U     /*!<Acknowledge Failure                             */
-#define  I2C_SR1_OVR                         0x00000800U     /*!<Overrun/Underrun                                */
-#define  I2C_SR1_PECERR                      0x00001000U     /*!<PEC Error in reception                          */
-#define  I2C_SR1_TIMEOUT                     0x00004000U     /*!<Timeout or Tlow Error                           */
-#define  I2C_SR1_SMBALERT                    0x00008000U     /*!<SMBus Alert                                     */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         0x00000001U     /*!<Master/Slave                              */
-#define  I2C_SR2_BUSY                        0x00000002U     /*!<Bus Busy                                  */
-#define  I2C_SR2_TRA                         0x00000004U     /*!<Transmitter/Receiver                      */
-#define  I2C_SR2_GENCALL                     0x00000010U     /*!<General Call Address (Slave mode)  */
-#define  I2C_SR2_SMBDEFAULT                  0x00000020U     /*!<SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     0x00000040U     /*!<SMBus Host Header (Slave mode)     */
-#define  I2C_SR2_DUALF                       0x00000080U     /*!<Dual Flag (Slave mode)             */
-#define  I2C_SR2_PEC                         0x0000FF00U     /*!<Packet Error Checking Register            */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         0x00000FFFU     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        0x00004000U     /*!<Fast Mode Duty Cycle                                       */
-#define  I2C_CCR_FS                          0x00008000U     /*!<I2C Master Mode Selection                                  */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     0x0000003FU     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************  Bit definition for I2C_FLTR register  *******************/
-#define  I2C_FLTR_DNF                        0x0000000FU     /*!<Digital Noise Filter */
-#define  I2C_FLTR_ANOFF                      0x00000010U     /*!<Analog Noise Filter OFF */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Independent WATCHDOG                             */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         0x01U               /*!<Watchdog prescaler value update      */
-#define  IWDG_SR_RVU                         0x02U               /*!<Watchdog counter reload value update */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                             Power Control                                  */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
-#define  PWR_CR_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
-#define  PWR_CR_CWUF                         0x00000004U     /*!< Clear Wakeup Flag                   */
-#define  PWR_CR_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
-#define  PWR_CR_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
-
-#define  PWR_CR_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        0x00000020U     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        0x00000040U     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        0x00000080U     /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
-
-#define  PWR_CR_DBP                          0x00000100U     /*!< Disable Backup Domain write protection               */
-#define  PWR_CR_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                        */
-#define  PWR_CR_VOS                          0x00004000U     /*!< VOS bit (Regulator voltage scaling output selection) */
-
-/* Legacy define */
-#define  PWR_CR_PMODE                        PWR_CR_VOS
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         0x00000001U     /*!< Wakeup Flag                                      */
-#define  PWR_CSR_SBF                         0x00000002U     /*!< Standby Flag                                     */
-#define  PWR_CSR_PVDO                        0x00000004U     /*!< PVD Output                                       */
-#define  PWR_CSR_BRR                         0x00000008U     /*!< Backup regulator ready                           */
-#define  PWR_CSR_EWUP                        0x00000100U     /*!< Enable WKUP pin                                  */
-#define  PWR_CSR_BRE                         0x00000200U     /*!< Backup regulator enable                          */
-#define  PWR_CSR_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
-
-/* Legacy define */
-#define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        0x00000001U
-#define  RCC_CR_HSIRDY                       0x00000002U
-
-#define  RCC_CR_HSITRIM                      0x000000F8U
-#define  RCC_CR_HSITRIM_0                    0x00000008U/*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    0x00000010U/*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    0x00000020U/*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    0x00000040U/*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    0x00000080U/*!<Bit 4 */
-
-#define  RCC_CR_HSICAL                       0x0000FF00U
-#define  RCC_CR_HSICAL_0                     0x00000100U/*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     0x00000200U/*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     0x00000400U/*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     0x00000800U/*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     0x00001000U/*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     0x00002000U/*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     0x00004000U/*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     0x00008000U/*!<Bit 7 */
-
-#define  RCC_CR_HSEON                        0x00010000U
-#define  RCC_CR_HSERDY                       0x00020000U
-#define  RCC_CR_HSEBYP                       0x00040000U
-#define  RCC_CR_CSSON                        0x00080000U
-#define  RCC_CR_PLLON                        0x01000000U
-#define  RCC_CR_PLLRDY                       0x02000000U
-#define  RCC_CR_PLLI2SON                     0x04000000U
-#define  RCC_CR_PLLI2SRDY                    0x08000000U
-
-/********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    0x0000003FU
-#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
-#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
-#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
-#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
-#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
-#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
-
-#define  RCC_PLLCFGR_PLLN                     0x00007FC0U
-#define  RCC_PLLCFGR_PLLN_0                   0x00000040U
-#define  RCC_PLLCFGR_PLLN_1                   0x00000080U
-#define  RCC_PLLCFGR_PLLN_2                   0x00000100U
-#define  RCC_PLLCFGR_PLLN_3                   0x00000200U
-#define  RCC_PLLCFGR_PLLN_4                   0x00000400U
-#define  RCC_PLLCFGR_PLLN_5                   0x00000800U
-#define  RCC_PLLCFGR_PLLN_6                   0x00001000U
-#define  RCC_PLLCFGR_PLLN_7                   0x00002000U
-#define  RCC_PLLCFGR_PLLN_8                   0x00004000U
-
-#define  RCC_PLLCFGR_PLLP                    0x00030000U
-#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
-#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
-
-#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
-
-#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
-#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
-#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
-#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
-#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-/*!< SW configuration */
-#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
-
-#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
-
-#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
-
-#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
-
-/*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     0x001F0000U
-#define  RCC_CFGR_RTCPRE_0                   0x00010000U
-#define  RCC_CFGR_RTCPRE_1                   0x00020000U
-#define  RCC_CFGR_RTCPRE_2                   0x00040000U
-#define  RCC_CFGR_RTCPRE_3                   0x00080000U
-#define  RCC_CFGR_RTCPRE_4                   0x00100000U
-
-/*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       0x00600000U
-#define  RCC_CFGR_MCO1_0                     0x00200000U
-#define  RCC_CFGR_MCO1_1                     0x00400000U
-
-#define  RCC_CFGR_I2SSRC                     0x00800000U
-
-#define  RCC_CFGR_MCO1PRE                    0x07000000U
-#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
-#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
-#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
-
-#define  RCC_CFGR_MCO2PRE                    0x38000000U
-#define  RCC_CFGR_MCO2PRE_0                  0x08000000U
-#define  RCC_CFGR_MCO2PRE_1                  0x10000000U
-#define  RCC_CFGR_MCO2PRE_2                  0x20000000U
-
-#define  RCC_CFGR_MCO2                       0xC0000000U
-#define  RCC_CFGR_MCO2_0                     0x40000000U
-#define  RCC_CFGR_MCO2_1                     0x80000000U
-
-/********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     0x00000001U
-#define  RCC_CIR_LSERDYF                     0x00000002U
-#define  RCC_CIR_HSIRDYF                     0x00000004U
-#define  RCC_CIR_HSERDYF                     0x00000008U
-#define  RCC_CIR_PLLRDYF                     0x00000010U
-#define  RCC_CIR_PLLI2SRDYF                  0x00000020U
-
-#define  RCC_CIR_CSSF                        0x00000080U
-#define  RCC_CIR_LSIRDYIE                    0x00000100U
-#define  RCC_CIR_LSERDYIE                    0x00000200U
-#define  RCC_CIR_HSIRDYIE                    0x00000400U
-#define  RCC_CIR_HSERDYIE                    0x00000800U
-#define  RCC_CIR_PLLRDYIE                    0x00001000U
-#define  RCC_CIR_PLLI2SRDYIE                 0x00002000U
-
-#define  RCC_CIR_LSIRDYC                     0x00010000U
-#define  RCC_CIR_LSERDYC                     0x00020000U
-#define  RCC_CIR_HSIRDYC                     0x00040000U
-#define  RCC_CIR_HSERDYC                     0x00080000U
-#define  RCC_CIR_PLLRDYC                     0x00100000U
-#define  RCC_CIR_PLLI2SRDYC                  0x00200000U
-
-#define  RCC_CIR_CSSC                        0x00800000U
-
-/********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
-#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
-#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
-#define  RCC_AHB1RSTR_GPIODRST               0x00000008U
-#define  RCC_AHB1RSTR_GPIOERST               0x00000010U
-#define  RCC_AHB1RSTR_GPIOFRST               0x00000020U
-#define  RCC_AHB1RSTR_GPIOGRST               0x00000040U
-#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
-#define  RCC_AHB1RSTR_GPIOIRST               0x00000100U
-#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
-#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
-#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
-#define  RCC_AHB1RSTR_OTGHRST                0x20000000U
-
-/********************  Bit definition for RCC_AHB2RSTR register  **************/
-#define  RCC_AHB2RSTR_RNGRST                 0x00000040U
-#define  RCC_AHB2RSTR_OTGFSRST               0x00000080U
-
-/********************  Bit definition for RCC_AHB3RSTR register  **************/
-
-#define  RCC_AHB3RSTR_FSMCRST                0x00000001U
-
-/********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM2RST                0x00000001U
-#define  RCC_APB1RSTR_TIM3RST                0x00000002U
-#define  RCC_APB1RSTR_TIM4RST                0x00000004U
-#define  RCC_APB1RSTR_TIM5RST                0x00000008U
-#define  RCC_APB1RSTR_TIM6RST                0x00000010U
-#define  RCC_APB1RSTR_TIM7RST                0x00000020U
-#define  RCC_APB1RSTR_TIM12RST               0x00000040U
-#define  RCC_APB1RSTR_TIM13RST               0x00000080U
-#define  RCC_APB1RSTR_TIM14RST               0x00000100U
-#define  RCC_APB1RSTR_WWDGRST                0x00000800U
-#define  RCC_APB1RSTR_SPI2RST                0x00004000U
-#define  RCC_APB1RSTR_SPI3RST                0x00008000U
-#define  RCC_APB1RSTR_USART2RST              0x00020000U
-#define  RCC_APB1RSTR_USART3RST              0x00040000U
-#define  RCC_APB1RSTR_UART4RST               0x00080000U
-#define  RCC_APB1RSTR_UART5RST               0x00100000U
-#define  RCC_APB1RSTR_I2C1RST                0x00200000U
-#define  RCC_APB1RSTR_I2C2RST                0x00400000U
-#define  RCC_APB1RSTR_I2C3RST                0x00800000U
-#define  RCC_APB1RSTR_CAN1RST                0x02000000U
-#define  RCC_APB1RSTR_CAN2RST                0x04000000U
-#define  RCC_APB1RSTR_PWRRST                 0x10000000U
-#define  RCC_APB1RSTR_DACRST                 0x20000000U
-
-/********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                0x00000001U
-#define  RCC_APB2RSTR_TIM8RST                0x00000002U
-#define  RCC_APB2RSTR_USART1RST              0x00000010U
-#define  RCC_APB2RSTR_USART6RST              0x00000020U
-#define  RCC_APB2RSTR_ADCRST                 0x00000100U
-#define  RCC_APB2RSTR_SDIORST                0x00000800U
-#define  RCC_APB2RSTR_SPI1RST                0x00001000U
-#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
-#define  RCC_APB2RSTR_TIM9RST                0x00010000U
-#define  RCC_APB2RSTR_TIM10RST               0x00020000U
-#define  RCC_APB2RSTR_TIM11RST               0x00040000U
-
-/* Old SPI1RST bit definition, maintained for legacy purpose */
-#define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
-
-/********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
-#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
-#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
-#define  RCC_AHB1ENR_GPIODEN                 0x00000008U
-#define  RCC_AHB1ENR_GPIOEEN                 0x00000010U
-#define  RCC_AHB1ENR_GPIOFEN                 0x00000020U
-#define  RCC_AHB1ENR_GPIOGEN                 0x00000040U
-#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
-#define  RCC_AHB1ENR_GPIOIEN                 0x00000100U
-#define  RCC_AHB1ENR_CRCEN                   0x00001000U
-#define  RCC_AHB1ENR_BKPSRAMEN               0x00040000U
-#define  RCC_AHB1ENR_CCMDATARAMEN            0x00100000U
-#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
-#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
-
-#define  RCC_AHB1ENR_OTGHSEN                 0x20000000U
-#define  RCC_AHB1ENR_OTGHSULPIEN             0x40000000U
-
-/********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define  RCC_AHB2ENR_RNGEN                   0x00000040U
-#define  RCC_AHB2ENR_OTGFSEN                 0x00000080U
-
-/********************  Bit definition for RCC_AHB3ENR register  ***************/
-
-#define  RCC_AHB3ENR_FSMCEN                  0x00000001U
-
-/********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM2EN                  0x00000001U
-#define  RCC_APB1ENR_TIM3EN                  0x00000002U
-#define  RCC_APB1ENR_TIM4EN                  0x00000004U
-#define  RCC_APB1ENR_TIM5EN                  0x00000008U
-#define  RCC_APB1ENR_TIM6EN                  0x00000010U
-#define  RCC_APB1ENR_TIM7EN                  0x00000020U
-#define  RCC_APB1ENR_TIM12EN                 0x00000040U
-#define  RCC_APB1ENR_TIM13EN                 0x00000080U
-#define  RCC_APB1ENR_TIM14EN                 0x00000100U
-#define  RCC_APB1ENR_WWDGEN                  0x00000800U
-#define  RCC_APB1ENR_SPI2EN                  0x00004000U
-#define  RCC_APB1ENR_SPI3EN                  0x00008000U
-#define  RCC_APB1ENR_USART2EN                0x00020000U
-#define  RCC_APB1ENR_USART3EN                0x00040000U
-#define  RCC_APB1ENR_UART4EN                 0x00080000U
-#define  RCC_APB1ENR_UART5EN                 0x00100000U
-#define  RCC_APB1ENR_I2C1EN                  0x00200000U
-#define  RCC_APB1ENR_I2C2EN                  0x00400000U
-#define  RCC_APB1ENR_I2C3EN                  0x00800000U
-#define  RCC_APB1ENR_CAN1EN                  0x02000000U
-#define  RCC_APB1ENR_CAN2EN                  0x04000000U
-#define  RCC_APB1ENR_PWREN                   0x10000000U
-#define  RCC_APB1ENR_DACEN                   0x20000000U
-
-/********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  0x00000001U
-#define  RCC_APB2ENR_TIM8EN                  0x00000002U
-#define  RCC_APB2ENR_USART1EN                0x00000010U
-#define  RCC_APB2ENR_USART6EN                0x00000020U
-#define  RCC_APB2ENR_ADC1EN                  0x00000100U
-#define  RCC_APB2ENR_ADC2EN                  0x00000200U
-#define  RCC_APB2ENR_ADC3EN                  0x00000400U
-#define  RCC_APB2ENR_SDIOEN                  0x00000800U
-#define  RCC_APB2ENR_SPI1EN                  0x00001000U
-#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
-#define  RCC_APB2ENR_TIM9EN                  0x00010000U
-#define  RCC_APB2ENR_TIM10EN                 0x00020000U
-#define  RCC_APB2ENR_TIM11EN                 0x00040000U
-#define  RCC_APB2ENR_SPI5EN                  0x00100000U
-#define  RCC_APB2ENR_SPI6EN                  0x00200000U
-
-/********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
-#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
-#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
-#define  RCC_AHB1LPENR_GPIODLPEN             0x00000008U
-#define  RCC_AHB1LPENR_GPIOELPEN             0x00000010U
-#define  RCC_AHB1LPENR_GPIOFLPEN             0x00000020U
-#define  RCC_AHB1LPENR_GPIOGLPEN             0x00000040U
-#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
-#define  RCC_AHB1LPENR_GPIOILPEN             0x00000100U
-#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
-#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
-#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
-#define  RCC_AHB1LPENR_SRAM2LPEN             0x00020000U
-#define  RCC_AHB1LPENR_BKPSRAMLPEN           0x00040000U
-#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
-#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
-#define  RCC_AHB1LPENR_OTGHSLPEN             0x20000000U
-#define  RCC_AHB1LPENR_OTGHSULPILPEN         0x40000000U
-
-/********************  Bit definition for RCC_AHB2LPENR register  *************/
-#define  RCC_AHB2LPENR_RNGLPEN               0x00000040U
-#define  RCC_AHB2LPENR_OTGFSLPEN             0x00000080U
-
-/********************  Bit definition for RCC_AHB3LPENR register  *************/
-
-#define  RCC_AHB3LPENR_FSMCLPEN              0x00000001U
-
-/********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM2LPEN              0x00000001U
-#define  RCC_APB1LPENR_TIM3LPEN              0x00000002U
-#define  RCC_APB1LPENR_TIM4LPEN              0x00000004U
-#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
-#define  RCC_APB1LPENR_TIM6LPEN              0x00000010U
-#define  RCC_APB1LPENR_TIM7LPEN              0x00000020U
-#define  RCC_APB1LPENR_TIM12LPEN             0x00000040U
-#define  RCC_APB1LPENR_TIM13LPEN             0x00000080U
-#define  RCC_APB1LPENR_TIM14LPEN             0x00000100U
-#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
-#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U
-#define  RCC_APB1LPENR_SPI3LPEN              0x00008000U
-#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
-#define  RCC_APB1LPENR_USART3LPEN            0x00040000U
-#define  RCC_APB1LPENR_UART4LPEN             0x00080000U
-#define  RCC_APB1LPENR_UART5LPEN             0x00100000U
-#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
-#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
-#define  RCC_APB1LPENR_I2C3LPEN              0x00800000U
-#define  RCC_APB1LPENR_CAN1LPEN              0x02000000U
-#define  RCC_APB1LPENR_CAN2LPEN              0x04000000U
-#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
-#define  RCC_APB1LPENR_DACLPEN               0x20000000U
-
-/********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
-#define  RCC_APB2LPENR_TIM8LPEN              0x00000002U
-#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
-#define  RCC_APB2LPENR_USART6LPEN            0x00000020U
-#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
-#define  RCC_APB2LPENR_ADC2LPEN              0x00000200U
-#define  RCC_APB2LPENR_ADC3LPEN              0x00000400U
-#define  RCC_APB2LPENR_SDIOLPEN              0x00000800U
-#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
-#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
-#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
-#define  RCC_APB2LPENR_TIM10LPEN             0x00020000U
-#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
-
-/********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      0x00000001U
-#define  RCC_BDCR_LSERDY                     0x00000002U
-#define  RCC_BDCR_LSEBYP                     0x00000004U
-
-#define  RCC_BDCR_RTCSEL                    0x00000300U
-#define  RCC_BDCR_RTCSEL_0                  0x00000100U
-#define  RCC_BDCR_RTCSEL_1                  0x00000200U
-
-#define  RCC_BDCR_RTCEN                      0x00008000U
-#define  RCC_BDCR_BDRST                      0x00010000U
-
-/********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       0x00000001U
-#define  RCC_CSR_LSIRDY                      0x00000002U
-#define  RCC_CSR_RMVF                        0x01000000U
-#define  RCC_CSR_BORRSTF                     0x02000000U
-#define  RCC_CSR_PADRSTF                     0x04000000U
-#define  RCC_CSR_PORRSTF                     0x08000000U
-#define  RCC_CSR_SFTRSTF                     0x10000000U
-#define  RCC_CSR_WDGRSTF                     0x20000000U
-#define  RCC_CSR_WWDGRSTF                    0x40000000U
-#define  RCC_CSR_LPWRRSTF                    0x80000000U
-
-/********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    0x00001FFFU
-#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
-#define  RCC_SSCGR_SPREADSEL                 0x40000000U
-#define  RCC_SSCGR_SSCGEN                    0x80000000U
-
-/********************  Bit definition for RCC_PLLI2SCFGR register  ************/
-#define  RCC_PLLI2SCFGR_PLLI2SN              0x00007FC0U
-#define  RCC_PLLI2SCFGR_PLLI2SN_0            0x00000040U
-#define  RCC_PLLI2SCFGR_PLLI2SN_1            0x00000080U
-#define  RCC_PLLI2SCFGR_PLLI2SN_2            0x00000100U
-#define  RCC_PLLI2SCFGR_PLLI2SN_3            0x00000200U
-#define  RCC_PLLI2SCFGR_PLLI2SN_4            0x00000400U
-#define  RCC_PLLI2SCFGR_PLLI2SN_5            0x00000800U
-#define  RCC_PLLI2SCFGR_PLLI2SN_6            0x00001000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_7            0x00002000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_8            0x00004000U
-
-#define  RCC_PLLI2SCFGR_PLLI2SR              0x70000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_0            0x10000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_1            0x20000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_2            0x40000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    RNG                                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN                         0x00000004U
-#define RNG_CR_IE                            0x00000008U
-
-/********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY                          0x00000001U
-#define RNG_SR_CECS                          0x00000002U
-#define RNG_SR_SECS                          0x00000004U
-#define RNG_SR_CEIS                          0x00000020U
-#define RNG_SR_SEIS                          0x00000040U
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            0x00400000U
-#define RTC_TR_HT                            0x00300000U
-#define RTC_TR_HT_0                          0x00100000U
-#define RTC_TR_HT_1                          0x00200000U
-#define RTC_TR_HU                            0x000F0000U
-#define RTC_TR_HU_0                          0x00010000U
-#define RTC_TR_HU_1                          0x00020000U
-#define RTC_TR_HU_2                          0x00040000U
-#define RTC_TR_HU_3                          0x00080000U
-#define RTC_TR_MNT                           0x00007000U
-#define RTC_TR_MNT_0                         0x00001000U
-#define RTC_TR_MNT_1                         0x00002000U
-#define RTC_TR_MNT_2                         0x00004000U
-#define RTC_TR_MNU                           0x00000F00U
-#define RTC_TR_MNU_0                         0x00000100U
-#define RTC_TR_MNU_1                         0x00000200U
-#define RTC_TR_MNU_2                         0x00000400U
-#define RTC_TR_MNU_3                         0x00000800U
-#define RTC_TR_ST                            0x00000070U
-#define RTC_TR_ST_0                          0x00000010U
-#define RTC_TR_ST_1                          0x00000020U
-#define RTC_TR_ST_2                          0x00000040U
-#define RTC_TR_SU                            0x0000000FU
-#define RTC_TR_SU_0                          0x00000001U
-#define RTC_TR_SU_1                          0x00000002U
-#define RTC_TR_SU_2                          0x00000004U
-#define RTC_TR_SU_3                          0x00000008U
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            0x00F00000U
-#define RTC_DR_YT_0                          0x00100000U
-#define RTC_DR_YT_1                          0x00200000U
-#define RTC_DR_YT_2                          0x00400000U
-#define RTC_DR_YT_3                          0x00800000U
-#define RTC_DR_YU                            0x000F0000U
-#define RTC_DR_YU_0                          0x00010000U
-#define RTC_DR_YU_1                          0x00020000U
-#define RTC_DR_YU_2                          0x00040000U
-#define RTC_DR_YU_3                          0x00080000U
-#define RTC_DR_WDU                           0x0000E000U
-#define RTC_DR_WDU_0                         0x00002000U
-#define RTC_DR_WDU_1                         0x00004000U
-#define RTC_DR_WDU_2                         0x00008000U
-#define RTC_DR_MT                            0x00001000U
-#define RTC_DR_MU                            0x00000F00U
-#define RTC_DR_MU_0                          0x00000100U
-#define RTC_DR_MU_1                          0x00000200U
-#define RTC_DR_MU_2                          0x00000400U
-#define RTC_DR_MU_3                          0x00000800U
-#define RTC_DR_DT                            0x00000030U
-#define RTC_DR_DT_0                          0x00000010U
-#define RTC_DR_DT_1                          0x00000020U
-#define RTC_DR_DU                            0x0000000FU
-#define RTC_DR_DU_0                          0x00000001U
-#define RTC_DR_DU_1                          0x00000002U
-#define RTC_DR_DU_2                          0x00000004U
-#define RTC_DR_DU_3                          0x00000008U
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           0x00800000U
-#define RTC_CR_OSEL                          0x00600000U
-#define RTC_CR_OSEL_0                        0x00200000U
-#define RTC_CR_OSEL_1                        0x00400000U
-#define RTC_CR_POL                           0x00100000U
-#define RTC_CR_COSEL                         0x00080000U
-#define RTC_CR_BCK                           0x00040000U
-#define RTC_CR_SUB1H                         0x00020000U
-#define RTC_CR_ADD1H                         0x00010000U
-#define RTC_CR_TSIE                          0x00008000U
-#define RTC_CR_WUTIE                         0x00004000U
-#define RTC_CR_ALRBIE                        0x00002000U
-#define RTC_CR_ALRAIE                        0x00001000U
-#define RTC_CR_TSE                           0x00000800U
-#define RTC_CR_WUTE                          0x00000400U
-#define RTC_CR_ALRBE                         0x00000200U
-#define RTC_CR_ALRAE                         0x00000100U
-#define RTC_CR_DCE                           0x00000080U
-#define RTC_CR_FMT                           0x00000040U
-#define RTC_CR_BYPSHAD                       0x00000020U
-#define RTC_CR_REFCKON                       0x00000010U
-#define RTC_CR_TSEDGE                        0x00000008U
-#define RTC_CR_WUCKSEL                       0x00000007U
-#define RTC_CR_WUCKSEL_0                     0x00000001U
-#define RTC_CR_WUCKSEL_1                     0x00000002U
-#define RTC_CR_WUCKSEL_2                     0x00000004U
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      0x00010000U
-#define RTC_ISR_TAMP1F                       0x00002000U
-#define RTC_ISR_TAMP2F                       0x00004000U
-#define RTC_ISR_TSOVF                        0x00001000U
-#define RTC_ISR_TSF                          0x00000800U
-#define RTC_ISR_WUTF                         0x00000400U
-#define RTC_ISR_ALRBF                        0x00000200U
-#define RTC_ISR_ALRAF                        0x00000100U
-#define RTC_ISR_INIT                         0x00000080U
-#define RTC_ISR_INITF                        0x00000040U
-#define RTC_ISR_RSF                          0x00000020U
-#define RTC_ISR_INITS                        0x00000010U
-#define RTC_ISR_SHPF                         0x00000008U
-#define RTC_ISR_WUTWF                        0x00000004U
-#define RTC_ISR_ALRBWF                       0x00000002U
-#define RTC_ISR_ALRAWF                       0x00000001U
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    0x007F0000U
-#define RTC_PRER_PREDIV_S                    0x00007FFFU
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS                       0x00000080U
-#define RTC_CALIBR_DC                        0x0000001FU
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      0x80000000U
-#define RTC_ALRMAR_WDSEL                     0x40000000U
-#define RTC_ALRMAR_DT                        0x30000000U
-#define RTC_ALRMAR_DT_0                      0x10000000U
-#define RTC_ALRMAR_DT_1                      0x20000000U
-#define RTC_ALRMAR_DU                        0x0F000000U
-#define RTC_ALRMAR_DU_0                      0x01000000U
-#define RTC_ALRMAR_DU_1                      0x02000000U
-#define RTC_ALRMAR_DU_2                      0x04000000U
-#define RTC_ALRMAR_DU_3                      0x08000000U
-#define RTC_ALRMAR_MSK3                      0x00800000U
-#define RTC_ALRMAR_PM                        0x00400000U
-#define RTC_ALRMAR_HT                        0x00300000U
-#define RTC_ALRMAR_HT_0                      0x00100000U
-#define RTC_ALRMAR_HT_1                      0x00200000U
-#define RTC_ALRMAR_HU                        0x000F0000U
-#define RTC_ALRMAR_HU_0                      0x00010000U
-#define RTC_ALRMAR_HU_1                      0x00020000U
-#define RTC_ALRMAR_HU_2                      0x00040000U
-#define RTC_ALRMAR_HU_3                      0x00080000U
-#define RTC_ALRMAR_MSK2                      0x00008000U
-#define RTC_ALRMAR_MNT                       0x00007000U
-#define RTC_ALRMAR_MNT_0                     0x00001000U
-#define RTC_ALRMAR_MNT_1                     0x00002000U
-#define RTC_ALRMAR_MNT_2                     0x00004000U
-#define RTC_ALRMAR_MNU                       0x00000F00U
-#define RTC_ALRMAR_MNU_0                     0x00000100U
-#define RTC_ALRMAR_MNU_1                     0x00000200U
-#define RTC_ALRMAR_MNU_2                     0x00000400U
-#define RTC_ALRMAR_MNU_3                     0x00000800U
-#define RTC_ALRMAR_MSK1                      0x00000080U
-#define RTC_ALRMAR_ST                        0x00000070U
-#define RTC_ALRMAR_ST_0                      0x00000010U
-#define RTC_ALRMAR_ST_1                      0x00000020U
-#define RTC_ALRMAR_ST_2                      0x00000040U
-#define RTC_ALRMAR_SU                        0x0000000FU
-#define RTC_ALRMAR_SU_0                      0x00000001U
-#define RTC_ALRMAR_SU_1                      0x00000002U
-#define RTC_ALRMAR_SU_2                      0x00000004U
-#define RTC_ALRMAR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      0x80000000U
-#define RTC_ALRMBR_WDSEL                     0x40000000U
-#define RTC_ALRMBR_DT                        0x30000000U
-#define RTC_ALRMBR_DT_0                      0x10000000U
-#define RTC_ALRMBR_DT_1                      0x20000000U
-#define RTC_ALRMBR_DU                        0x0F000000U
-#define RTC_ALRMBR_DU_0                      0x01000000U
-#define RTC_ALRMBR_DU_1                      0x02000000U
-#define RTC_ALRMBR_DU_2                      0x04000000U
-#define RTC_ALRMBR_DU_3                      0x08000000U
-#define RTC_ALRMBR_MSK3                      0x00800000U
-#define RTC_ALRMBR_PM                        0x00400000U
-#define RTC_ALRMBR_HT                        0x00300000U
-#define RTC_ALRMBR_HT_0                      0x00100000U
-#define RTC_ALRMBR_HT_1                      0x00200000U
-#define RTC_ALRMBR_HU                        0x000F0000U
-#define RTC_ALRMBR_HU_0                      0x00010000U
-#define RTC_ALRMBR_HU_1                      0x00020000U
-#define RTC_ALRMBR_HU_2                      0x00040000U
-#define RTC_ALRMBR_HU_3                      0x00080000U
-#define RTC_ALRMBR_MSK2                      0x00008000U
-#define RTC_ALRMBR_MNT                       0x00007000U
-#define RTC_ALRMBR_MNT_0                     0x00001000U
-#define RTC_ALRMBR_MNT_1                     0x00002000U
-#define RTC_ALRMBR_MNT_2                     0x00004000U
-#define RTC_ALRMBR_MNU                       0x00000F00U
-#define RTC_ALRMBR_MNU_0                     0x00000100U
-#define RTC_ALRMBR_MNU_1                     0x00000200U
-#define RTC_ALRMBR_MNU_2                     0x00000400U
-#define RTC_ALRMBR_MNU_3                     0x00000800U
-#define RTC_ALRMBR_MSK1                      0x00000080U
-#define RTC_ALRMBR_ST                        0x00000070U
-#define RTC_ALRMBR_ST_0                      0x00000010U
-#define RTC_ALRMBR_ST_1                      0x00000020U
-#define RTC_ALRMBR_ST_2                      0x00000040U
-#define RTC_ALRMBR_SU                        0x0000000FU
-#define RTC_ALRMBR_SU_0                      0x00000001U
-#define RTC_ALRMBR_SU_1                      0x00000002U
-#define RTC_ALRMBR_SU_2                      0x00000004U
-#define RTC_ALRMBR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          0x000000FFU
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           0x0000FFFFU
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     0x00007FFFU
-#define RTC_SHIFTR_ADD1S                     0x80000000U
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          0x00400000U
-#define RTC_TSTR_HT                          0x00300000U
-#define RTC_TSTR_HT_0                        0x00100000U
-#define RTC_TSTR_HT_1                        0x00200000U
-#define RTC_TSTR_HU                          0x000F0000U
-#define RTC_TSTR_HU_0                        0x00010000U
-#define RTC_TSTR_HU_1                        0x00020000U
-#define RTC_TSTR_HU_2                        0x00040000U
-#define RTC_TSTR_HU_3                        0x00080000U
-#define RTC_TSTR_MNT                         0x00007000U
-#define RTC_TSTR_MNT_0                       0x00001000U
-#define RTC_TSTR_MNT_1                       0x00002000U
-#define RTC_TSTR_MNT_2                       0x00004000U
-#define RTC_TSTR_MNU                         0x00000F00U
-#define RTC_TSTR_MNU_0                       0x00000100U
-#define RTC_TSTR_MNU_1                       0x00000200U
-#define RTC_TSTR_MNU_2                       0x00000400U
-#define RTC_TSTR_MNU_3                       0x00000800U
-#define RTC_TSTR_ST                          0x00000070U
-#define RTC_TSTR_ST_0                        0x00000010U
-#define RTC_TSTR_ST_1                        0x00000020U
-#define RTC_TSTR_ST_2                        0x00000040U
-#define RTC_TSTR_SU                          0x0000000FU
-#define RTC_TSTR_SU_0                        0x00000001U
-#define RTC_TSTR_SU_1                        0x00000002U
-#define RTC_TSTR_SU_2                        0x00000004U
-#define RTC_TSTR_SU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         0x0000E000U
-#define RTC_TSDR_WDU_0                       0x00002000U
-#define RTC_TSDR_WDU_1                       0x00004000U
-#define RTC_TSDR_WDU_2                       0x00008000U
-#define RTC_TSDR_MT                          0x00001000U
-#define RTC_TSDR_MU                          0x00000F00U
-#define RTC_TSDR_MU_0                        0x00000100U
-#define RTC_TSDR_MU_1                        0x00000200U
-#define RTC_TSDR_MU_2                        0x00000400U
-#define RTC_TSDR_MU_3                        0x00000800U
-#define RTC_TSDR_DT                          0x00000030U
-#define RTC_TSDR_DT_0                        0x00000010U
-#define RTC_TSDR_DT_1                        0x00000020U
-#define RTC_TSDR_DU                          0x0000000FU
-#define RTC_TSDR_DU_0                        0x00000001U
-#define RTC_TSDR_DU_1                        0x00000002U
-#define RTC_TSDR_DU_2                        0x00000004U
-#define RTC_TSDR_DU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        0x00008000U
-#define RTC_CALR_CALW8                       0x00004000U
-#define RTC_CALR_CALW16                      0x00002000U
-#define RTC_CALR_CALM                        0x000001FFU
-#define RTC_CALR_CALM_0                      0x00000001U
-#define RTC_CALR_CALM_1                      0x00000002U
-#define RTC_CALR_CALM_2                      0x00000004U
-#define RTC_CALR_CALM_3                      0x00000008U
-#define RTC_CALR_CALM_4                      0x00000010U
-#define RTC_CALR_CALM_5                      0x00000020U
-#define RTC_CALR_CALM_6                      0x00000040U
-#define RTC_CALR_CALM_7                      0x00000080U
-#define RTC_CALR_CALM_8                      0x00000100U
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               0x00040000U
-#define RTC_TAFCR_TSINSEL                    0x00020000U
-#define RTC_TAFCR_TAMPINSEL                  0x00010000U
-#define RTC_TAFCR_TAMPPUDIS                  0x00008000U
-#define RTC_TAFCR_TAMPPRCH                   0x00006000U
-#define RTC_TAFCR_TAMPPRCH_0                 0x00002000U
-#define RTC_TAFCR_TAMPPRCH_1                 0x00004000U
-#define RTC_TAFCR_TAMPFLT                    0x00001800U
-#define RTC_TAFCR_TAMPFLT_0                  0x00000800U
-#define RTC_TAFCR_TAMPFLT_1                  0x00001000U
-#define RTC_TAFCR_TAMPFREQ                   0x00000700U
-#define RTC_TAFCR_TAMPFREQ_0                 0x00000100U
-#define RTC_TAFCR_TAMPFREQ_1                 0x00000200U
-#define RTC_TAFCR_TAMPFREQ_2                 0x00000400U
-#define RTC_TAFCR_TAMPTS                     0x00000080U
-#define RTC_TAFCR_TAMP2TRG                   0x00000010U
-#define RTC_TAFCR_TAMP2E                     0x00000008U
-#define RTC_TAFCR_TAMPIE                     0x00000004U
-#define RTC_TAFCR_TAMP1TRG                   0x00000002U
-#define RTC_TAFCR_TAMP1E                     0x00000001U
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  0x0F000000U
-#define RTC_ALRMASSR_MASKSS_0                0x01000000U
-#define RTC_ALRMASSR_MASKSS_1                0x02000000U
-#define RTC_ALRMASSR_MASKSS_2                0x04000000U
-#define RTC_ALRMASSR_MASKSS_3                0x08000000U
-#define RTC_ALRMASSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
-#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
-#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
-#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
-#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
-#define RTC_ALRMBSSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           0xFFFFFFFFU
-
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          SD host Interface                                 */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SDIO_POWER register  ******************/
-#define  SDIO_POWER_PWRCTRL                  0x03U               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDIO_POWER_PWRCTRL_0                0x01U               /*!<Bit 0 */
-#define  SDIO_POWER_PWRCTRL_1                0x02U               /*!<Bit 1 */
-
-/******************  Bit definition for SDIO_CLKCR register  ******************/
-#define  SDIO_CLKCR_CLKDIV                   0x00FFU            /*!<Clock divide factor             */
-#define  SDIO_CLKCR_CLKEN                    0x0100U            /*!<Clock enable bit                */
-#define  SDIO_CLKCR_PWRSAV                   0x0200U            /*!<Power saving configuration bit  */
-#define  SDIO_CLKCR_BYPASS                   0x0400U            /*!<Clock divider bypass enable bit */
-
-#define  SDIO_CLKCR_WIDBUS                   0x1800U            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDIO_CLKCR_WIDBUS_0                 0x0800U            /*!<Bit 0 */
-#define  SDIO_CLKCR_WIDBUS_1                 0x1000U            /*!<Bit 1 */
-
-#define  SDIO_CLKCR_NEGEDGE                  0x2000U            /*!<SDIO_CK dephasing selection bit */
-#define  SDIO_CLKCR_HWFC_EN                  0x4000U            /*!<HW Flow Control enable          */
-
-/*******************  Bit definition for SDIO_ARG register  *******************/
-#define  SDIO_ARG_CMDARG                     0xFFFFFFFFU            /*!<Command argument */
-
-/*******************  Bit definition for SDIO_CMD register  *******************/
-#define  SDIO_CMD_CMDINDEX                   0x003FU            /*!<Command Index                               */
-
-#define  SDIO_CMD_WAITRESP                   0x00C0U            /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDIO_CMD_WAITRESP_0                 0x0040U            /*!< Bit 0 */
-#define  SDIO_CMD_WAITRESP_1                 0x0080U            /*!< Bit 1 */
-
-#define  SDIO_CMD_WAITINT                    0x0100U            /*!<CPSM Waits for Interrupt Request                               */
-#define  SDIO_CMD_WAITPEND                   0x0200U            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDIO_CMD_CPSMEN                     0x0400U            /*!<Command path state machine (CPSM) Enable bit                   */
-#define  SDIO_CMD_SDIOSUSPEND                0x0800U            /*!<SD I/O suspend command                                         */
-#define  SDIO_CMD_ENCMDCOMPL                 0x1000U            /*!<Enable CMD completion                                          */
-#define  SDIO_CMD_NIEN                       0x2000U            /*!<Not Interrupt Enable */
-#define  SDIO_CMD_CEATACMD                   0x4000U            /*!<CE-ATA command       */
-
-/*****************  Bit definition for SDIO_RESPCMD register  *****************/
-#define  SDIO_RESPCMD_RESPCMD                0x3FU               /*!<Response command index */
-
-/******************  Bit definition for SDIO_RESP0 register  ******************/
-#define  SDIO_RESP0_CARDSTATUS0              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP1 register  ******************/
-#define  SDIO_RESP1_CARDSTATUS1              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP2 register  ******************/
-#define  SDIO_RESP2_CARDSTATUS2              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP3 register  ******************/
-#define  SDIO_RESP3_CARDSTATUS3              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP4 register  ******************/
-#define  SDIO_RESP4_CARDSTATUS4              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_DTIMER register  *****************/
-#define  SDIO_DTIMER_DATATIME                0xFFFFFFFFU        /*!<Data timeout period. */
-
-/******************  Bit definition for SDIO_DLEN register  *******************/
-#define  SDIO_DLEN_DATALENGTH                0x01FFFFFFU        /*!<Data length value    */
-
-/******************  Bit definition for SDIO_DCTRL register  ******************/
-#define  SDIO_DCTRL_DTEN                     0x0001U            /*!<Data transfer enabled bit         */
-#define  SDIO_DCTRL_DTDIR                    0x0002U            /*!<Data transfer direction selection */
-#define  SDIO_DCTRL_DTMODE                   0x0004U            /*!<Data transfer mode selection      */
-#define  SDIO_DCTRL_DMAEN                    0x0008U            /*!<DMA enabled bit                   */
-
-#define  SDIO_DCTRL_DBLOCKSIZE               0x00F0U            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDIO_DCTRL_DBLOCKSIZE_0             0x0010U            /*!<Bit 0 */
-#define  SDIO_DCTRL_DBLOCKSIZE_1             0x0020U            /*!<Bit 1 */
-#define  SDIO_DCTRL_DBLOCKSIZE_2             0x0040U            /*!<Bit 2 */
-#define  SDIO_DCTRL_DBLOCKSIZE_3             0x0080U            /*!<Bit 3 */
-
-#define  SDIO_DCTRL_RWSTART                  0x0100U            /*!<Read wait start         */
-#define  SDIO_DCTRL_RWSTOP                   0x0200U            /*!<Read wait stop          */
-#define  SDIO_DCTRL_RWMOD                    0x0400U            /*!<Read wait mode          */
-#define  SDIO_DCTRL_SDIOEN                   0x0800U            /*!<SD I/O enable functions */
-
-/******************  Bit definition for SDIO_DCOUNT register  *****************/
-#define  SDIO_DCOUNT_DATACOUNT               0x01FFFFFFU        /*!<Data count value */
-
-/******************  Bit definition for SDIO_STA register  ********************/
-#define  SDIO_STA_CCRCFAIL                   0x00000001U        /*!<Command response received (CRC check failed)  */
-#define  SDIO_STA_DCRCFAIL                   0x00000002U        /*!<Data block sent/received (CRC check failed)   */
-#define  SDIO_STA_CTIMEOUT                   0x00000004U        /*!<Command response timeout                      */
-#define  SDIO_STA_DTIMEOUT                   0x00000008U        /*!<Data timeout                                  */
-#define  SDIO_STA_TXUNDERR                   0x00000010U        /*!<Transmit FIFO underrun error                  */
-#define  SDIO_STA_RXOVERR                    0x00000020U        /*!<Received FIFO overrun error                   */
-#define  SDIO_STA_CMDREND                    0x00000040U        /*!<Command response received (CRC check passed)  */
-#define  SDIO_STA_CMDSENT                    0x00000080U        /*!<Command sent (no response required)           */
-#define  SDIO_STA_DATAEND                    0x00000100U        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
-#define  SDIO_STA_STBITERR                   0x00000200U        /*!<Start bit not detected on all data signals in wide bus mode */
-#define  SDIO_STA_DBCKEND                    0x00000400U        /*!<Data block sent/received (CRC check passed)   */
-#define  SDIO_STA_CMDACT                     0x00000800U        /*!<Command transfer in progress                  */
-#define  SDIO_STA_TXACT                      0x00001000U        /*!<Data transmit in progress                     */
-#define  SDIO_STA_RXACT                      0x00002000U        /*!<Data receive in progress                      */
-#define  SDIO_STA_TXFIFOHE                   0x00004000U        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDIO_STA_RXFIFOHF                   0x00008000U        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDIO_STA_TXFIFOF                    0x00010000U        /*!<Transmit FIFO full                            */
-#define  SDIO_STA_RXFIFOF                    0x00020000U        /*!<Receive FIFO full                             */
-#define  SDIO_STA_TXFIFOE                    0x00040000U        /*!<Transmit FIFO empty                           */
-#define  SDIO_STA_RXFIFOE                    0x00080000U        /*!<Receive FIFO empty                            */
-#define  SDIO_STA_TXDAVL                     0x00100000U        /*!<Data available in transmit FIFO               */
-#define  SDIO_STA_RXDAVL                     0x00200000U        /*!<Data available in receive FIFO                */
-#define  SDIO_STA_SDIOIT                     0x00400000U        /*!<SDIO interrupt received                       */
-#define  SDIO_STA_CEATAEND                   0x00800000U        /*!<CE-ATA command completion signal received for CMD61 */
-
-/*******************  Bit definition for SDIO_ICR register  *******************/
-#define  SDIO_ICR_CCRCFAILC                  0x00000001U        /*!<CCRCFAIL flag clear bit */
-#define  SDIO_ICR_DCRCFAILC                  0x00000002U        /*!<DCRCFAIL flag clear bit */
-#define  SDIO_ICR_CTIMEOUTC                  0x00000004U        /*!<CTIMEOUT flag clear bit */
-#define  SDIO_ICR_DTIMEOUTC                  0x00000008U        /*!<DTIMEOUT flag clear bit */
-#define  SDIO_ICR_TXUNDERRC                  0x00000010U        /*!<TXUNDERR flag clear bit */
-#define  SDIO_ICR_RXOVERRC                   0x00000020U        /*!<RXOVERR flag clear bit  */
-#define  SDIO_ICR_CMDRENDC                   0x00000040U        /*!<CMDREND flag clear bit  */
-#define  SDIO_ICR_CMDSENTC                   0x00000080U        /*!<CMDSENT flag clear bit  */
-#define  SDIO_ICR_DATAENDC                   0x00000100U        /*!<DATAEND flag clear bit  */
-#define  SDIO_ICR_STBITERRC                  0x00000200U        /*!<STBITERR flag clear bit */
-#define  SDIO_ICR_DBCKENDC                   0x00000400U        /*!<DBCKEND flag clear bit  */
-#define  SDIO_ICR_SDIOITC                    0x00400000U        /*!<SDIOIT flag clear bit   */
-#define  SDIO_ICR_CEATAENDC                  0x00800000U        /*!<CEATAEND flag clear bit */
-
-/******************  Bit definition for SDIO_MASK register  *******************/
-#define  SDIO_MASK_CCRCFAILIE                0x00000001U        /*!<Command CRC Fail Interrupt Enable          */
-#define  SDIO_MASK_DCRCFAILIE                0x00000002U        /*!<Data CRC Fail Interrupt Enable             */
-#define  SDIO_MASK_CTIMEOUTIE                0x00000004U        /*!<Command TimeOut Interrupt Enable           */
-#define  SDIO_MASK_DTIMEOUTIE                0x00000008U        /*!<Data TimeOut Interrupt Enable              */
-#define  SDIO_MASK_TXUNDERRIE                0x00000010U        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
-#define  SDIO_MASK_RXOVERRIE                 0x00000020U        /*!<Rx FIFO OverRun Error Interrupt Enable     */
-#define  SDIO_MASK_CMDRENDIE                 0x00000040U        /*!<Command Response Received Interrupt Enable */
-#define  SDIO_MASK_CMDSENTIE                 0x00000080U        /*!<Command Sent Interrupt Enable              */
-#define  SDIO_MASK_DATAENDIE                 0x00000100U        /*!<Data End Interrupt Enable                  */
-#define  SDIO_MASK_STBITERRIE                0x00000200U        /*!<Start Bit Error Interrupt Enable           */
-#define  SDIO_MASK_DBCKENDIE                 0x00000400U        /*!<Data Block End Interrupt Enable            */
-#define  SDIO_MASK_CMDACTIE                  0x00000800U        /*!<CCommand Acting Interrupt Enable           */
-#define  SDIO_MASK_TXACTIE                   0x00001000U        /*!<Data Transmit Acting Interrupt Enable      */
-#define  SDIO_MASK_RXACTIE                   0x00002000U        /*!<Data receive acting interrupt enabled      */
-#define  SDIO_MASK_TXFIFOHEIE                0x00004000U        /*!<Tx FIFO Half Empty interrupt Enable        */
-#define  SDIO_MASK_RXFIFOHFIE                0x00008000U        /*!<Rx FIFO Half Full interrupt Enable         */
-#define  SDIO_MASK_TXFIFOFIE                 0x00010000U        /*!<Tx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_RXFIFOFIE                 0x00020000U        /*!<Rx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_TXFIFOEIE                 0x00040000U        /*!<Tx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_RXFIFOEIE                 0x00080000U        /*!<Rx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_TXDAVLIE                  0x00100000U        /*!<Data available in Tx FIFO interrupt Enable */
-#define  SDIO_MASK_RXDAVLIE                  0x00200000U        /*!<Data available in Rx FIFO interrupt Enable */
-#define  SDIO_MASK_SDIOITIE                  0x00400000U        /*!<SDIO Mode Interrupt Received interrupt Enable */
-#define  SDIO_MASK_CEATAENDIE                0x00800000U        /*!<CE-ATA command completion signal received Interrupt Enable */
-
-/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
-#define  SDIO_FIFOCNT_FIFOCOUNT              0x00FFFFFFU        /*!<Remaining number of words to be written to or read from the FIFO */
-
-/******************  Bit definition for SDIO_FIFO register  *******************/
-#define  SDIO_FIFO_FIFODATA                  0xFFFFFFFFU        /*!<Receive and transmit FIFO data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        0x00000001U            /*!<Clock Phase      */
-#define  SPI_CR1_CPOL                        0x00000002U            /*!<Clock Polarity   */
-#define  SPI_CR1_MSTR                        0x00000004U            /*!<Master Selection */
-
-#define  SPI_CR1_BR                          0x00000038U            /*!<BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        0x00000008U            /*!<Bit 0 */
-#define  SPI_CR1_BR_1                        0x00000010U            /*!<Bit 1 */
-#define  SPI_CR1_BR_2                        0x00000020U            /*!<Bit 2 */
-
-#define  SPI_CR1_SPE                         0x00000040U            /*!<SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    0x00000080U            /*!<Frame Format                        */
-#define  SPI_CR1_SSI                         0x00000100U            /*!<Internal slave select               */
-#define  SPI_CR1_SSM                         0x00000200U            /*!<Software slave management           */
-#define  SPI_CR1_RXONLY                      0x00000400U            /*!<Receive only                        */
-#define  SPI_CR1_DFF                         0x00000800U            /*!<Data Frame Format                   */
-#define  SPI_CR1_CRCNEXT                     0x00001000U            /*!<Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       0x00002000U            /*!<Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      0x00004000U            /*!<Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    0x00008000U            /*!<Bidirectional data mode enable      */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     0x00000001U               /*!<Rx Buffer DMA Enable                 */
-#define  SPI_CR2_TXDMAEN                     0x00000002U               /*!<Tx Buffer DMA Enable                 */
-#define  SPI_CR2_SSOE                        0x00000004U               /*!<SS Output Enable                     */
-#define  SPI_CR2_FRF                         0x00000010U               /*!<Frame Format                         */
-#define  SPI_CR2_ERRIE                       0x00000020U               /*!<Error Interrupt Enable               */
-#define  SPI_CR2_RXNEIE                      0x00000040U               /*!<RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       0x00000080U               /*!<Tx buffer Empty Interrupt Enable     */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         0x00000001U               /*!<Receive buffer Not Empty */
-#define  SPI_SR_TXE                          0x00000002U               /*!<Transmit buffer Empty    */
-#define  SPI_SR_CHSIDE                       0x00000004U               /*!<Channel side             */
-#define  SPI_SR_UDR                          0x00000008U               /*!<Underrun flag            */
-#define  SPI_SR_CRCERR                       0x00000010U               /*!<CRC Error flag           */
-#define  SPI_SR_MODF                         0x00000020U               /*!<Mode fault               */
-#define  SPI_SR_OVR                          0x00000040U               /*!<Overrun flag             */
-#define  SPI_SR_BSY                          0x00000080U               /*!<Busy flag                */
-#define  SPI_SR_FRE                          0x00000100U               /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           0x0000FFFFU            /*!<Data Register           */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   0x0000FFFFU            /*!<CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    0x0000FFFFU            /*!<Rx CRC Register         */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    0x0000FFFFU            /*!<Tx CRC Register         */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   0x00000001U            /*!<Channel length (number of bits per audio channel) */
-
-#define  SPI_I2SCFGR_DATLEN                  0x00000006U            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define  SPI_I2SCFGR_DATLEN_0                0x00000002U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                0x00000004U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_CKPOL                   0x00000008U            /*!<steady state clock polarity               */
-
-#define  SPI_I2SCFGR_I2SSTD                  0x00000030U            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U            /*!<PCM frame synchronization                 */
-
-#define  SPI_I2SCFGR_I2SCFG                  0x00000300U            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_I2SE                    0x00000400U            /*!<I2S Enable         */
-#define  SPI_I2SCFGR_I2SMOD                  0x00000800U            /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    0x000000FFU            /*!<I2S Linear prescaler         */
-#define  SPI_I2SPR_ODD                       0x00000100U            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     0x00000200U            /*!<Master Clock Output Enable   */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 SYSCFG                                     */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
-#define SYSCFG_MEMRMP_MEM_MODE          0x00000007U /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        0x00000001U
-#define SYSCFG_MEMRMP_MEM_MODE_1        0x00000002U
-#define SYSCFG_MEMRMP_MEM_MODE_2        0x00000004U
-
-/******************  Bit definition for SYSCFG_PMC register  ******************/
-#define SYSCFG_PMC_MII_RMII_SEL         0x00800000U /*!<Ethernet PHY interface selection */
-/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
-#define SYSCFG_PMC_MII_RMII             SYSCFG_PMC_MII_RMII_SEL
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
-/** 
-  * @brief   EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         0x0003U /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         0x0004U /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         0x0005U /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         0x0006U /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PI         0x0008U /*!<PI[0] pin */
-
-/** 
-  * @brief   EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         0x0030U /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         0x0040U /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         0x0050U /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         0x0060U /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PI         0x0080U /*!<PI[1] pin */
-
-/** 
-  * @brief   EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         0x0300U /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         0x0400U /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         0x0500U /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         0x0600U /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PI         0x0800U /*!<PI[2] pin */
-
-/** 
-  * @brief   EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         0x3000U /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         0x4000U /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         0x5000U /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         0x6000U /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PI         0x8000U /*!<PI[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
-/** 
-  * @brief   EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         0x0003U /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         0x0004U /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         0x0005U /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         0x0006U /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PI         0x0008U /*!<PI[4] pin */
-
-/** 
-  * @brief   EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         0x0030U /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         0x0040U /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         0x0050U /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         0x0060U /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PI         0x0080U /*!<PI[5] pin */
-
-/** 
-  * @brief   EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         0x0300U /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         0x0400U /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         0x0500U /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         0x0600U /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PI         0x0800U /*!<PI[6] pin */
-
-/** 
-  * @brief   EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         0x3000U /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         0x4000U /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         0x5000U /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         0x6000U /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PI         0x8000U /*!<PI[7] pin */
-
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
-           
-/** 
-  * @brief   EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         0x0003U /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         0x0004U /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         0x0005U /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         0x0006U /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PI         0x0008U /*!<PI[8] pin */
-
-/** 
-  * @brief   EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         0x0030U /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         0x0040U /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         0x0050U /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         0x0060U /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PI         0x0080U /*!<PI[9] pin */
-
-/** 
-  * @brief   EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        0x0300U /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        0x0400U /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        0x0500U /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        0x0600U /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PI        0x0800U /*!<PI[10] pin */
-
-/** 
-  * @brief   EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        0x3000U /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        0x4000U /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        0x5000U /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        0x6000U /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PI        0x8000U /*!<PI[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
-/** 
-  * @brief   EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        0x0003U /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        0x0004U /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        0x0005U /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        0x0006U /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
-
-/** 
-  * @brief   EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        0x0030U /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        0x0040U /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        0x0050U /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        0x0060U /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
-
-/** 
-  * @brief   EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        0x0300U /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        0x0400U /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        0x0500U /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        0x0600U /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
-
-/** 
-  * @brief   EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        0x3000U /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        0x4000U /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        0x5000U /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        0x6000U /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
-
-/******************  Bit definition for SYSCFG_CMPCR register  ****************/  
-#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell ready flag */
-#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell power-down */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    TIM                                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
-#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
-#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
-#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
-#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
-
-#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
-
-#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
-
-#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        0x0001U            /*!<Capture/Compare Preloaded Control        */
-#define  TIM_CR2_CCUS                        0x0004U            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        0x0008U            /*!<Capture/Compare DMA Selection            */
-
-#define  TIM_CR2_MMS                         0x0070U            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
-#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
-#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
-#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        0x0007U            /*!<SMS[2:0] bits (Slave mode selection)    */
-#define  TIM_SMCR_SMS_0                      0x0001U            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      0x0002U            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      0x0004U            /*!<Bit 2 */
-
-#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
-#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
-
-#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
-
-#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
-
-#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
-#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
-#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
-#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
-#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
-#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
-#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
-#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
-#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
-#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
-#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
-#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
-#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
-#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
-#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
-#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
-#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
-#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
-#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          0x01U               /*!<Update Generation                         */
-#define  TIM_EGR_CC1G                        0x02U               /*!<Capture/Compare 1 Generation              */
-#define  TIM_EGR_CC2G                        0x04U               /*!<Capture/Compare 2 Generation              */
-#define  TIM_EGR_CC3G                        0x08U               /*!<Capture/Compare 3 Generation              */
-#define  TIM_EGR_CC4G                        0x10U               /*!<Capture/Compare 4 Generation              */
-#define  TIM_EGR_COMG                        0x20U               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          0x40U               /*!<Trigger Generation                        */
-#define  TIM_EGR_BG                          0x80U               /*!<Break Generation                          */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      0x0003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    0x0001U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    0x0002U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC1FE                     0x0004U            /*!<Output Compare 1 Fast enable                 */
-#define  TIM_CCMR1_OC1PE                     0x0008U            /*!<Output Compare 1 Preload enable              */
-
-#define  TIM_CCMR1_OC1M                      0x0070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define  TIM_CCMR1_OC1M_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    0x0040U            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC1CE                     0x0080U            /*!<Output Compare 1Clear Enable                 */
-
-#define  TIM_CCMR1_CC2S                      0x0300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    0x0100U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    0x0200U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC2FE                     0x0400U            /*!<Output Compare 2 Fast enable                 */
-#define  TIM_CCMR1_OC2PE                     0x0800U            /*!<Output Compare 2 Preload enable              */
-
-#define  TIM_CCMR1_OC2M                      0x7000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define  TIM_CCMR1_OC2M_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    0x4000U            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC2CE                     0x8000U            /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      0x0003U            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define  TIM_CCMR2_CC3S_0                    0x0001U            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    0x0002U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC3FE                     0x0004U            /*!<Output Compare 3 Fast enable           */
-#define  TIM_CCMR2_OC3PE                     0x0008U            /*!<Output Compare 3 Preload enable        */
-
-#define  TIM_CCMR2_OC3M                      0x0070U            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    0x0040U            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC3CE                     0x0080U            /*!<Output Compare 3 Clear Enable */
-
-#define  TIM_CCMR2_CC4S                      0x0300U            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    0x0100U            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    0x0200U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC4FE                     0x0400U            /*!<Output Compare 4 Fast enable    */
-#define  TIM_CCMR2_OC4PE                     0x0800U            /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR2_OC4M                      0x7000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    0x4000U            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       0x0001U            /*!<Capture/Compare 1 output enable                 */
-#define  TIM_CCER_CC1P                       0x0002U            /*!<Capture/Compare 1 output Polarity               */
-#define  TIM_CCER_CC1NE                      0x0004U            /*!<Capture/Compare 1 Complementary output enable   */
-#define  TIM_CCER_CC1NP                      0x0008U            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       0x0010U            /*!<Capture/Compare 2 output enable                 */
-#define  TIM_CCER_CC2P                       0x0020U            /*!<Capture/Compare 2 output Polarity               */
-#define  TIM_CCER_CC2NE                      0x0040U            /*!<Capture/Compare 2 Complementary output enable   */
-#define  TIM_CCER_CC2NP                      0x0080U            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       0x0100U            /*!<Capture/Compare 3 output enable                 */
-#define  TIM_CCER_CC3P                       0x0200U            /*!<Capture/Compare 3 output Polarity               */
-#define  TIM_CCER_CC3NE                      0x0400U            /*!<Capture/Compare 3 Complementary output enable   */
-#define  TIM_CCER_CC3NP                      0x0800U            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       0x1000U            /*!<Capture/Compare 4 output enable                 */
-#define  TIM_CCER_CC4P                       0x2000U            /*!<Capture/Compare 4 output Polarity               */
-#define  TIM_CCER_CC4NP                      0x8000U            /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         0xFFU               /*!<Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
-
-/*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        0x00FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      0x0001U            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      0x0002U            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      0x0004U            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      0x0008U            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      0x0010U            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      0x0020U            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      0x0040U            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      0x0080U            /*!<Bit 7 */
-
-#define  TIM_BDTR_LOCK                       0x0300U            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     0x0100U            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     0x0200U            /*!<Bit 1 */
-
-#define  TIM_BDTR_OSSI                       0x0400U            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       0x0800U            /*!<Off-State Selection for Run mode  */
-#define  TIM_BDTR_BKE                        0x1000U            /*!<Break enable                      */
-#define  TIM_BDTR_BKP                        0x2000U            /*!<Break Polarity                    */
-#define  TIM_BDTR_AOE                        0x4000U            /*!<Automatic Output enable           */
-#define  TIM_BDTR_MOE                        0x8000U            /*!<Main Output enable                */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
-
-#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
-#define TIM_OR_ITR1_RMP                      0x0C00U            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
-#define TIM_OR_ITR1_RMP_0                    0x0400U            /*!<Bit 0 */
-#define TIM_OR_ITR1_RMP_1                    0x0800U            /*!<Bit 1 */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*         Universal Synchronous Asynchronous Receiver Transmitter            */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         0x0001U            /*!<Parity Error                 */
-#define  USART_SR_FE                         0x0002U            /*!<Framing Error                */
-#define  USART_SR_NE                         0x0004U            /*!<Noise Error Flag             */
-#define  USART_SR_ORE                        0x0008U            /*!<OverRun Error                */
-#define  USART_SR_IDLE                       0x0010U            /*!<IDLE line detected           */
-#define  USART_SR_RXNE                       0x0020U            /*!<Read Data Register Not Empty */
-#define  USART_SR_TC                         0x0040U            /*!<Transmission Complete        */
-#define  USART_SR_TXE                        0x0080U            /*!<Transmit Data Register Empty */
-#define  USART_SR_LBD                        0x0100U            /*!<LIN Break Detection Flag     */
-#define  USART_SR_CTS                        0x0200U            /*!<CTS Flag                     */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         0x01FFU            /*!<Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_Fraction              0x000FU            /*!<Fraction of USARTDIV */
-#define  USART_BRR_DIV_Mantissa              0xFFF0U            /*!<Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       0x0001U            /*!<Send Break                             */
-#define  USART_CR1_RWU                       0x0002U            /*!<Receiver wakeup                        */
-#define  USART_CR1_RE                        0x0004U            /*!<Receiver Enable                        */
-#define  USART_CR1_TE                        0x0008U            /*!<Transmitter Enable                     */
-#define  USART_CR1_IDLEIE                    0x0010U            /*!<IDLE Interrupt Enable                  */
-#define  USART_CR1_RXNEIE                    0x0020U            /*!<RXNE Interrupt Enable                  */
-#define  USART_CR1_TCIE                      0x0040U            /*!<Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     0x0080U            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PEIE                      0x0100U            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PS                        0x0200U            /*!<Parity Selection                       */
-#define  USART_CR1_PCE                       0x0400U            /*!<Parity Control Enable                  */
-#define  USART_CR1_WAKE                      0x0800U            /*!<Wakeup method                          */
-#define  USART_CR1_M                         0x1000U            /*!<Word length                            */
-#define  USART_CR1_UE                        0x2000U            /*!<USART Enable                           */
-#define  USART_CR1_OVER8                     0x8000U            /*!<USART Oversampling by 8 enable         */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       0x000FU            /*!<Address of the USART node            */
-#define  USART_CR2_LBDL                      0x0020U            /*!<LIN Break Detection Length           */
-#define  USART_CR2_LBDIE                     0x0040U            /*!<LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      0x0100U            /*!<Last Bit Clock pulse                 */
-#define  USART_CR2_CPHA                      0x0200U            /*!<Clock Phase                          */
-#define  USART_CR2_CPOL                      0x0400U            /*!<Clock Polarity                       */
-#define  USART_CR2_CLKEN                     0x0800U            /*!<Clock Enable                         */
-
-#define  USART_CR2_STOP                      0x3000U            /*!<STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    0x1000U            /*!<Bit 0 */
-#define  USART_CR2_STOP_1                    0x2000U            /*!<Bit 1 */
-
-#define  USART_CR2_LINEN                     0x4000U            /*!<LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       0x0001U            /*!<Error Interrupt Enable      */
-#define  USART_CR3_IREN                      0x0002U            /*!<IrDA mode Enable            */
-#define  USART_CR3_IRLP                      0x0004U            /*!<IrDA Low-Power              */
-#define  USART_CR3_HDSEL                     0x0008U            /*!<Half-Duplex Selection       */
-#define  USART_CR3_NACK                      0x0010U            /*!<Smartcard NACK enable       */
-#define  USART_CR3_SCEN                      0x0020U            /*!<Smartcard mode enable       */
-#define  USART_CR3_DMAR                      0x0040U            /*!<DMA Enable Receiver         */
-#define  USART_CR3_DMAT                      0x0080U            /*!<DMA Enable Transmitter      */
-#define  USART_CR3_RTSE                      0x0100U            /*!<RTS Enable                  */
-#define  USART_CR3_CTSE                      0x0200U            /*!<CTS Enable                  */
-#define  USART_CR3_CTSIE                     0x0400U            /*!<CTS Interrupt Enable        */
-#define  USART_CR3_ONEBIT                    0x0800U            /*!<USART One bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      0x00FFU            /*!<PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    0x0001U            /*!<Bit 0 */
-#define  USART_GTPR_PSC_1                    0x0002U            /*!<Bit 1 */
-#define  USART_GTPR_PSC_2                    0x0004U            /*!<Bit 2 */
-#define  USART_GTPR_PSC_3                    0x0008U            /*!<Bit 3 */
-#define  USART_GTPR_PSC_4                    0x0010U            /*!<Bit 4 */
-#define  USART_GTPR_PSC_5                    0x0020U            /*!<Bit 5 */
-#define  USART_GTPR_PSC_6                    0x0040U            /*!<Bit 6 */
-#define  USART_GTPR_PSC_7                    0x0080U            /*!<Bit 7 */
-
-#define  USART_GTPR_GT                       0xFF00U            /*!<Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Window WATCHDOG                                 */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           0x7FU               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T_0                         0x01U               /*!<Bit 0 */
-#define  WWDG_CR_T_1                         0x02U               /*!<Bit 1 */
-#define  WWDG_CR_T_2                         0x04U               /*!<Bit 2 */
-#define  WWDG_CR_T_3                         0x08U               /*!<Bit 3 */
-#define  WWDG_CR_T_4                         0x10U               /*!<Bit 4 */
-#define  WWDG_CR_T_5                         0x20U               /*!<Bit 5 */
-#define  WWDG_CR_T_6                         0x40U               /*!<Bit 6 */
-/* Legacy defines */
-#define  WWDG_CR_T0                          WWDG_CR_T_0
-#define  WWDG_CR_T1                          WWDG_CR_T_1
-#define  WWDG_CR_T2                          WWDG_CR_T_2
-#define  WWDG_CR_T3                          WWDG_CR_T_3
-#define  WWDG_CR_T4                          WWDG_CR_T_4
-#define  WWDG_CR_T5                          WWDG_CR_T_5
-#define  WWDG_CR_T6                          WWDG_CR_T_6
-
-#define  WWDG_CR_WDGA                        0x80U               /*!<Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          0x007FU            /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W_0                        0x0001U            /*!<Bit 0 */
-#define  WWDG_CFR_W_1                        0x0002U            /*!<Bit 1 */
-#define  WWDG_CFR_W_2                        0x0004U            /*!<Bit 2 */
-#define  WWDG_CFR_W_3                        0x0008U            /*!<Bit 3 */
-#define  WWDG_CFR_W_4                        0x0010U            /*!<Bit 4 */
-#define  WWDG_CFR_W_5                        0x0020U            /*!<Bit 5 */
-#define  WWDG_CFR_W_6                        0x0040U            /*!<Bit 6 */
-/* Legacy defines */
-#define  WWDG_CFR_W0                         WWDG_CFR_W_0
-#define  WWDG_CFR_W1                         WWDG_CFR_W_1
-#define  WWDG_CFR_W2                         WWDG_CFR_W_2
-#define  WWDG_CFR_W3                         WWDG_CFR_W_3
-#define  WWDG_CFR_W4                         WWDG_CFR_W_4
-#define  WWDG_CFR_W5                         WWDG_CFR_W_5
-#define  WWDG_CFR_W6                         WWDG_CFR_W_6
-
-#define  WWDG_CFR_WDGTB                      0x0180U            /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB_0                    0x0080U            /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB_1                    0x0100U            /*!<Bit 1 */
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
-
-#define  WWDG_CFR_EWI                        0x0200U            /*!<Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        0x01U               /*!<Early Wakeup Interrupt Flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                DBG                                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
-#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
-
-/********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
-#define  DBGMCU_CR_DBG_STOP                  0x00000002U
-#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
-#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
-
-#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
-#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U/*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U/*!<Bit 1 */
-
-/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            0x00000001U
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            0x00000002U
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            0x00000004U
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            0x00000020U
-#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           0x00000040U
-#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           0x00000080U
-#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           0x00000100U
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
-#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
-/* Old IWDGSTOP bit definition, maintained for legacy purpose */
-#define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
-
-/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        0x00000001U
-#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        0x00000002U
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        0x00010000U
-#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       0x00020000U
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       0x00040000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                                       USB_OTG			                        */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/
-#define USB_OTG_GOTGCTL_SRQSCS                  0x00000001U            /*!< Session request success */
-#define USB_OTG_GOTGCTL_SRQ                     0x00000002U            /*!< Session request */
-#define USB_OTG_GOTGCTL_HNGSCS                  0x00000100U            /*!< Host negotiation success */
-#define USB_OTG_GOTGCTL_HNPRQ                   0x00000200U            /*!< HNP request */
-#define USB_OTG_GOTGCTL_HSHNPEN                 0x00000400U            /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_DHNPEN                  0x00000800U            /*!< Device HNP enabled */
-#define USB_OTG_GOTGCTL_CIDSTS                  0x00010000U            /*!< Connector ID status */
-#define USB_OTG_GOTGCTL_DBCT                    0x00020000U            /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD                   0x00040000U            /*!< A-session valid */
-#define USB_OTG_GOTGCTL_BSVLD                   0x00080000U            /*!< B-session valid */
-
-/********************  Bit definition forUSB_OTG_HCFG register  ********************/
-
-#define USB_OTG_HCFG_FSLSPCS                 0x00000003U            /*!< FS/LS PHY clock select */
-#define USB_OTG_HCFG_FSLSPCS_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCFG_FSLSPCS_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCFG_FSLSS                   0x00000004U            /*!< FS- and LS-only support */
-
-/********************  Bit definition forUSB_OTG_DCFG register  ********************/
-
-#define USB_OTG_DCFG_DSPD                    0x00000003U            /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                  0x00000001U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DSPD_1                  0x00000002U            /*!<Bit 1 */
-#define USB_OTG_DCFG_NZLSOHSK                0x00000004U            /*!< Nonzero-length status OUT handshake */
-
-#define USB_OTG_DCFG_DAD                     0x000007F0U            /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                   0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DAD_1                   0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCFG_DAD_2                   0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCFG_DAD_3                   0x00000080U            /*!<Bit 3 */
-#define USB_OTG_DCFG_DAD_4                   0x00000100U            /*!<Bit 4 */
-#define USB_OTG_DCFG_DAD_5                   0x00000200U            /*!<Bit 5 */
-#define USB_OTG_DCFG_DAD_6                   0x00000400U            /*!<Bit 6 */
-
-#define USB_OTG_DCFG_PFIVL                   0x00001800U            /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PFIVL_1                 0x00001000U            /*!<Bit 1 */
-
-#define USB_OTG_DCFG_PERSCHIVL               0x03000000U            /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0             0x01000000U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PERSCHIVL_1             0x02000000U            /*!<Bit 1 */
-
-/********************  Bit definition forUSB_OTG_PCGCR register  ********************/
-#define USB_OTG_PCGCR_STPPCLK                 0x00000001U            /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK                0x00000002U            /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP                 0x00000010U            /*!< PHY suspended */
-
-/********************  Bit definition forUSB_OTG_GOTGINT register  ********************/
-#define USB_OTG_GOTGINT_SEDET                   0x00000004U            /*!< Session end detected */
-#define USB_OTG_GOTGINT_SRSSCHG                 0x00000100U            /*!< Session request success status change */
-#define USB_OTG_GOTGINT_HNSSCHG                 0x00000200U            /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET                  0x00020000U            /*!< Host negotiation detected */
-#define USB_OTG_GOTGINT_ADTOCHG                 0x00040000U            /*!< A-device timeout change */
-#define USB_OTG_GOTGINT_DBCDNE                  0x00080000U            /*!< Debounce done */
-
-/********************  Bit definition forUSB_OTG_DCTL register  ********************/
-#define USB_OTG_DCTL_RWUSIG                  0x00000001U            /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS                    0x00000002U            /*!< Soft disconnect */
-#define USB_OTG_DCTL_GINSTS                  0x00000004U            /*!< Global IN NAK status */
-#define USB_OTG_DCTL_GONSTS                  0x00000008U            /*!< Global OUT NAK status */
-
-#define USB_OTG_DCTL_TCTL                    0x00000070U            /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                  0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCTL_TCTL_1                  0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCTL_TCTL_2                  0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCTL_SGINAK                  0x00000080U            /*!< Set global IN NAK */
-#define USB_OTG_DCTL_CGINAK                  0x00000100U            /*!< Clear global IN NAK */
-#define USB_OTG_DCTL_SGONAK                  0x00000200U            /*!< Set global OUT NAK */
-#define USB_OTG_DCTL_CGONAK                  0x00000400U            /*!< Clear global OUT NAK */
-#define USB_OTG_DCTL_POPRGDNE                0x00000800U            /*!< Power-on programming done */
-
-/********************  Bit definition forUSB_OTG_HFIR register  ********************/
-#define USB_OTG_HFIR_FRIVL                   0x0000FFFFU            /*!< Frame interval */
-
-/********************  Bit definition forUSB_OTG_HFNUM register  ********************/
-#define USB_OTG_HFNUM_FRNUM                   0x0000FFFFU            /*!< Frame number */
-#define USB_OTG_HFNUM_FTREM                   0xFFFF0000U            /*!< Frame time remaining */
-
-/********************  Bit definition forUSB_OTG_DSTS register  ********************/
-#define USB_OTG_DSTS_SUSPSTS                 0x00000001U            /*!< Suspend status */
-
-#define USB_OTG_DSTS_ENUMSPD                 0x00000006U            /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_DSTS_ENUMSPD_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_DSTS_EERR                    0x00000008U            /*!< Erratic error */
-#define USB_OTG_DSTS_FNSOF                   0x003FFF00U            /*!< Frame number of the received SOF */
-
-/********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/
-#define USB_OTG_GAHBCFG_GINT                    0x00000001U            /*!< Global interrupt mask */
-
-#define USB_OTG_GAHBCFG_HBSTLEN                 0x0000001EU            /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_GAHBCFG_HBSTLEN_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_GAHBCFG_HBSTLEN_2               0x00000008U            /*!<Bit 2 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3               0x00000010U            /*!<Bit 3 */
-#define USB_OTG_GAHBCFG_DMAEN                   0x00000020U            /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL                 0x00000080U            /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL                0x00000100U            /*!< Periodic TxFIFO empty level */
-
-/********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/
-
-#define USB_OTG_GUSBCFG_TOCAL                   0x00000007U            /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TOCAL_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TOCAL_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_PHYSEL                  0x00000040U            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP                  0x00000100U            /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP                  0x00000200U            /*!< HNP-capable */
-
-#define USB_OTG_GUSBCFG_TRDT                    0x00003C00U            /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                  0x00000400U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TRDT_1                  0x00000800U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TRDT_2                  0x00001000U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_TRDT_3                  0x00002000U            /*!<Bit 3 */
-#define USB_OTG_GUSBCFG_PHYLPCS                 0x00008000U            /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS                0x00020000U            /*!< ULPI FS/LS select */
-#define USB_OTG_GUSBCFG_ULPIAR                  0x00040000U            /*!< ULPI Auto-resume */
-#define USB_OTG_GUSBCFG_ULPICSM                 0x00080000U            /*!< ULPI Clock SuspendM */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD              0x00100000U            /*!< ULPI External VBUS Drive */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI              0x00200000U            /*!< ULPI external VBUS indicator */
-#define USB_OTG_GUSBCFG_TSDPS                   0x00400000U            /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI                    0x00800000U            /*!< Indicator complement */
-#define USB_OTG_GUSBCFG_PTCI                    0x01000000U            /*!< Indicator pass through */
-#define USB_OTG_GUSBCFG_ULPIIPD                 0x02000000U            /*!< ULPI interface protect disable */
-#define USB_OTG_GUSBCFG_FHMOD                   0x20000000U            /*!< Forced host mode */
-#define USB_OTG_GUSBCFG_FDMOD                   0x40000000U            /*!< Forced peripheral mode */
-#define USB_OTG_GUSBCFG_CTXPKT                  0x80000000U            /*!< Corrupt Tx packet */
-
-/********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
-#define USB_OTG_GRSTCTL_CSRST                   0x00000001U            /*!< Core soft reset */
-#define USB_OTG_GRSTCTL_HSRST                   0x00000002U            /*!< HCLK soft reset */
-#define USB_OTG_GRSTCTL_FCRST                   0x00000004U            /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH                 0x00000010U            /*!< RxFIFO flush */
-#define USB_OTG_GRSTCTL_TXFFLSH                 0x00000020U            /*!< TxFIFO flush */
-
-#define USB_OTG_GRSTCTL_TXFNUM                  0x000007C0U            /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                0x00000040U            /*!<Bit 0 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                0x00000080U            /*!<Bit 1 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                0x00000100U            /*!<Bit 2 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                0x00000200U            /*!<Bit 3 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                0x00000400U            /*!<Bit 4 */
-#define USB_OTG_GRSTCTL_DMAREQ                  0x40000000U            /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL                  0x80000000U            /*!< AHB master idle */
-
-/********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/
-#define USB_OTG_DIEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPMSK_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPMSK_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPMSK_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPMSK_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPMSK_BIM                     0x00000200U            /*!< BNA interrupt mask */
-
-/********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/
-#define USB_OTG_HPTXSTS_PTXFSAVL                0x0000FFFFU            /*!< Periodic transmit data FIFO space available */
-
-#define USB_OTG_HPTXSTS_PTXQSAV                 0x00FF0000U            /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0               0x00010000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1               0x00020000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2               0x00040000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3               0x00080000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4               0x00100000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5               0x00200000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6               0x00400000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7               0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_HPTXSTS_PTXQTOP                 0xFF000000U            /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0               0x01000000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1               0x02000000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2               0x04000000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3               0x08000000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4               0x10000000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5               0x20000000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6               0x40000000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7               0x80000000U            /*!<Bit 7 */
-
-/********************  Bit definition forUSB_OTG_HAINT register  ********************/
-#define USB_OTG_HAINT_HAINT                   0x0000FFFFU            /*!< Channel interrupts */
-
-/********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/
-#define USB_OTG_DOEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPMSK_STUPM                   0x00000008U            /*!< SETUP phase done mask */
-#define USB_OTG_DOEPMSK_OTEPDM                  0x00000010U            /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received mask */
-#define USB_OTG_DOEPMSK_OPEM                    0x00000100U            /*!< OUT packet error mask */
-#define USB_OTG_DOEPMSK_BOIM                    0x00000200U            /*!< BNA interrupt mask */
-
-/********************  Bit definition forUSB_OTG_GINTSTS register  ********************/
-#define USB_OTG_GINTSTS_CMOD                    0x00000001U            /*!< Current mode of operation */
-#define USB_OTG_GINTSTS_MMIS                    0x00000002U            /*!< Mode mismatch interrupt */
-#define USB_OTG_GINTSTS_OTGINT                  0x00000004U            /*!< OTG interrupt */
-#define USB_OTG_GINTSTS_SOF                     0x00000008U            /*!< Start of frame */
-#define USB_OTG_GINTSTS_RXFLVL                  0x00000010U            /*!< RxFIFO nonempty */
-#define USB_OTG_GINTSTS_NPTXFE                  0x00000020U            /*!< Nonperiodic TxFIFO empty */
-#define USB_OTG_GINTSTS_GINAKEFF                0x00000040U            /*!< Global IN nonperiodic NAK effective */
-#define USB_OTG_GINTSTS_BOUTNAKEFF              0x00000080U            /*!< Global OUT NAK effective */
-#define USB_OTG_GINTSTS_ESUSP                   0x00000400U            /*!< Early suspend */
-#define USB_OTG_GINTSTS_USBSUSP                 0x00000800U            /*!< USB suspend */
-#define USB_OTG_GINTSTS_USBRST                  0x00001000U            /*!< USB reset */
-#define USB_OTG_GINTSTS_ENUMDNE                 0x00002000U            /*!< Enumeration done */
-#define USB_OTG_GINTSTS_ISOODRP                 0x00004000U            /*!< Isochronous OUT packet dropped interrupt */
-#define USB_OTG_GINTSTS_EOPF                    0x00008000U            /*!< End of periodic frame interrupt */
-#define USB_OTG_GINTSTS_IEPINT                  0x00040000U            /*!< IN endpoint interrupt */
-#define USB_OTG_GINTSTS_OEPINT                  0x00080000U            /*!< OUT endpoint interrupt */
-#define USB_OTG_GINTSTS_IISOIXFR                0x00100000U            /*!< Incomplete isochronous IN transfer */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       0x00200000U            /*!< Incomplete periodic transfer */
-#define USB_OTG_GINTSTS_DATAFSUSP               0x00400000U            /*!< Data fetch suspended */
-#define USB_OTG_GINTSTS_HPRTINT                 0x01000000U            /*!< Host port interrupt */
-#define USB_OTG_GINTSTS_HCINT                   0x02000000U            /*!< Host channels interrupt */
-#define USB_OTG_GINTSTS_PTXFE                   0x04000000U            /*!< Periodic TxFIFO empty */
-#define USB_OTG_GINTSTS_CIDSCHG                 0x10000000U            /*!< Connector ID status change */
-#define USB_OTG_GINTSTS_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt */
-#define USB_OTG_GINTSTS_SRQINT                  0x40000000U            /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT                  0x80000000U            /*!< Resume/remote wakeup detected interrupt */
-
-/********************  Bit definition forUSB_OTG_GINTMSK register  ********************/
-#define USB_OTG_GINTMSK_MMISM                   0x00000002U            /*!< Mode mismatch interrupt mask */
-#define USB_OTG_GINTMSK_OTGINT                  0x00000004U            /*!< OTG interrupt mask */
-#define USB_OTG_GINTMSK_SOFM                    0x00000008U            /*!< Start of frame mask */
-#define USB_OTG_GINTMSK_RXFLVLM                 0x00000010U            /*!< Receive FIFO nonempty mask */
-#define USB_OTG_GINTMSK_NPTXFEM                 0x00000020U            /*!< Nonperiodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_GINAKEFFM               0x00000040U            /*!< Global nonperiodic IN NAK effective mask */
-#define USB_OTG_GINTMSK_GONAKEFFM               0x00000080U            /*!< Global OUT NAK effective mask */
-#define USB_OTG_GINTMSK_ESUSPM                  0x00000400U            /*!< Early suspend mask */
-#define USB_OTG_GINTMSK_USBSUSPM                0x00000800U            /*!< USB suspend mask */
-#define USB_OTG_GINTMSK_USBRST                  0x00001000U            /*!< USB reset mask */
-#define USB_OTG_GINTMSK_ENUMDNEM                0x00002000U            /*!< Enumeration done mask */
-#define USB_OTG_GINTMSK_ISOODRPM                0x00004000U            /*!< Isochronous OUT packet dropped interrupt mask */
-#define USB_OTG_GINTMSK_EOPFM                   0x00008000U            /*!< End of periodic frame interrupt mask */
-#define USB_OTG_GINTMSK_EPMISM                  0x00020000U            /*!< Endpoint mismatch interrupt mask */
-#define USB_OTG_GINTMSK_IEPINT                  0x00040000U            /*!< IN endpoints interrupt mask */
-#define USB_OTG_GINTMSK_OEPINT                  0x00080000U            /*!< OUT endpoints interrupt mask */
-#define USB_OTG_GINTMSK_IISOIXFRM               0x00100000U            /*!< Incomplete isochronous IN transfer mask */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         0x00200000U            /*!< Incomplete periodic transfer mask */
-#define USB_OTG_GINTMSK_FSUSPM                  0x00400000U            /*!< Data fetch suspended mask */
-#define USB_OTG_GINTMSK_PRTIM                   0x01000000U            /*!< Host port interrupt mask */
-#define USB_OTG_GINTMSK_HCIM                    0x02000000U            /*!< Host channels interrupt mask */
-#define USB_OTG_GINTMSK_PTXFEM                  0x04000000U            /*!< Periodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_CIDSCHGM                0x10000000U            /*!< Connector ID status change mask */
-#define USB_OTG_GINTMSK_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt mask */
-#define USB_OTG_GINTMSK_SRQIM                   0x40000000U            /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM                    0x80000000U            /*!< Resume/remote wakeup detected interrupt mask */
-
-/********************  Bit definition forUSB_OTG_DAINT register  ********************/
-#define USB_OTG_DAINT_IEPINT                  0x0000FFFFU            /*!< IN endpoint interrupt bits */
-#define USB_OTG_DAINT_OEPINT                  0xFFFF0000U            /*!< OUT endpoint interrupt bits */
-
-/********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/
-#define USB_OTG_HAINTMSK_HAINTM                  0x0000FFFFU            /*!< Channel interrupt mask */
-
-/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
-#define USB_OTG_GRXSTSP_EPNUM                    0x0000000FU            /*!< IN EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_BCNT                     0x00007FF0U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID                     0x00018000U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS                   0x001E0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/
-#define USB_OTG_DAINTMSK_IEPM                    0x0000FFFFU            /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM                    0xFFFF0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for OTG register  ********************/
-
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition for OTG register  ********************/
-
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/
-#define USB_OTG_GRXFSIZ_RXFD                    0x0000FFFFU            /*!< RxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/
-#define USB_OTG_DVBUSDIS_VBUSDT                  0x0000FFFFU            /*!< Device VBUS discharge time */
-
-/********************  Bit definition for OTG register  ********************/
-#define USB_OTG_NPTXFSA                 0x0000FFFFU            /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD                  0xFFFF0000U            /*!< Nonperiodic TxFIFO depth */
-#define USB_OTG_TX0FSA                  0x0000FFFFU            /*!< Endpoint 0 transmit RAM start address */
-#define USB_OTG_TX0FD                   0xFFFF0000U            /*!< Endpoint 0 TxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
-#define USB_OTG_DVBUSPULSE_DVBUSP                  0x00000FFFU            /*!< Device VBUS pulsing time */
-
-/********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/
-#define USB_OTG_GNPTXSTS_NPTXFSAV                0x0000FFFFU            /*!< Nonperiodic TxFIFO space available */
-
-#define USB_OTG_GNPTXSTS_NPTQXSAV                0x00FF0000U            /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0              0x00010000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1              0x00020000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2              0x00040000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3              0x00080000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4              0x00100000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5              0x00200000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6              0x00400000U            /*!<Bit 6 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7              0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_GNPTXSTS_NPTXQTOP                0x7F000000U            /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0              0x01000000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1              0x02000000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2              0x04000000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3              0x08000000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4              0x10000000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5              0x20000000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6              0x40000000U            /*!<Bit 6 */
-
-/********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/
-#define USB_OTG_DTHRCTL_NONISOTHREN             0x00000001U            /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN                0x00000002U            /*!< ISO IN endpoint threshold enable */
-
-#define USB_OTG_DTHRCTL_TXTHRLEN                0x000007FCU            /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0              0x00000004U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1              0x00000008U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2              0x00000010U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3              0x00000020U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4              0x00000040U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5              0x00000080U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6              0x00000100U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7              0x00000200U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8              0x00000400U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_RXTHREN                 0x00010000U            /*!< Receive threshold enable */
-
-#define USB_OTG_DTHRCTL_RXTHRLEN                0x03FE0000U            /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0              0x00020000U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1              0x00040000U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2              0x00080000U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3              0x00100000U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4              0x00200000U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5              0x00400000U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6              0x00800000U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7              0x01000000U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8              0x02000000U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_ARPEN                   0x08000000U            /*!< Arbiter parking enable */
-
-/********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM               0x0000FFFFU            /*!< IN EP Tx FIFO empty interrupt mask bits */
-
-/********************  Bit definition forUSB_OTG_DEACHINT register  ********************/
-#define USB_OTG_DEACHINT_IEP1INT                 0x00000002U            /*!< IN endpoint 1interrupt bit */
-#define USB_OTG_DEACHINT_OEP1INT                 0x00020000U            /*!< OUT endpoint 1 interrupt bit */
-
-/********************  Bit definition forUSB_OTG_GCCFG register  ********************/
-#define USB_OTG_GCCFG_PWRDWN                  0x00010000U            /*!< Power down */
-#define USB_OTG_GCCFG_I2CPADEN                0x00020000U            /*!< Enable I2C bus connection for the external I2C PHY interface */
-#define USB_OTG_GCCFG_VBUSASEN                0x00040000U            /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_VBUSBSEN                0x00080000U            /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_SOFOUTEN                0x00100000U            /*!< SOF output enable */
-#define USB_OTG_GCCFG_NOVBUSSENS              0x00200000U            /*!< VBUS sensing disable option */
-
-/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
-#define USB_OTG_DEACHINTMSK_IEP1INTM                0x00000002U            /*!< IN Endpoint 1 interrupt mask bit */
-#define USB_OTG_DEACHINTMSK_OEP1INTM                0x00020000U            /*!< OUT Endpoint 1 interrupt mask bit */
-
-/********************  Bit definition forUSB_OTG_CID register  ********************/
-#define USB_OTG_CID_PRODUCT_ID              0xFFFFFFFFU            /*!< Product ID field */
-
-/********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/
-#define USB_OTG_DIEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPEACHMSK1_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
-
-/********************  Bit definition forUSB_OTG_HPRT register  ********************/
-#define USB_OTG_HPRT_PCSTS                   0x00000001U            /*!< Port connect status */
-#define USB_OTG_HPRT_PCDET                   0x00000002U            /*!< Port connect detected */
-#define USB_OTG_HPRT_PENA                    0x00000004U            /*!< Port enable */
-#define USB_OTG_HPRT_PENCHNG                 0x00000008U            /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA                    0x00000010U            /*!< Port overcurrent active */
-#define USB_OTG_HPRT_POCCHNG                 0x00000020U            /*!< Port overcurrent change */
-#define USB_OTG_HPRT_PRES                    0x00000040U            /*!< Port resume */
-#define USB_OTG_HPRT_PSUSP                   0x00000080U            /*!< Port suspend */
-#define USB_OTG_HPRT_PRST                    0x00000100U            /*!< Port reset */
-
-#define USB_OTG_HPRT_PLSTS                   0x00000C00U            /*!< Port line status */
-#define USB_OTG_HPRT_PLSTS_0                 0x00000400U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PLSTS_1                 0x00000800U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PPWR                    0x00001000U            /*!< Port power */
-
-#define USB_OTG_HPRT_PTCTL                   0x0001E000U            /*!< Port test control */
-#define USB_OTG_HPRT_PTCTL_0                 0x00002000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PTCTL_1                 0x00004000U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PTCTL_2                 0x00008000U            /*!<Bit 2 */
-#define USB_OTG_HPRT_PTCTL_3                 0x00010000U            /*!<Bit 3 */
-
-#define USB_OTG_HPRT_PSPD                    0x00060000U            /*!< Port speed */
-#define USB_OTG_HPRT_PSPD_0                  0x00020000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PSPD_1                  0x00040000U            /*!<Bit 1 */
-
-/********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/
-#define USB_OTG_DOEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DOEPEACHMSK1_TXFURM                  0x00000100U            /*!< OUT packet error mask */
-#define USB_OTG_DOEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_BERRM                   0x00001000U            /*!< Bubble error interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NYETM                   0x00004000U            /*!< NYET interrupt mask */
-
-/********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/
-#define USB_OTG_HPTXFSIZ_PTXSA                   0x0000FFFFU            /*!< Host periodic TxFIFO start address */
-#define USB_OTG_HPTXFSIZ_PTXFD                   0xFFFF0000U            /*!< Host periodic TxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/
-#define USB_OTG_DIEPCTL_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
-#define USB_OTG_DIEPCTL_USBAEP                  0x00008000U            /*!< USB active endpoint */
-#define USB_OTG_DIEPCTL_EONUM_DPID              0x00010000U            /*!< Even/odd frame */
-#define USB_OTG_DIEPCTL_NAKSTS                  0x00020000U            /*!< NAK status */
-
-#define USB_OTG_DIEPCTL_EPTYP                   0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_DIEPCTL_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_STALL                   0x00200000U            /*!< STALL handshake */
-
-#define USB_OTG_DIEPCTL_TXFNUM                  0x03C00000U            /*!< TxFIFO number */
-#define USB_OTG_DIEPCTL_TXFNUM_0                0x00400000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                0x00800000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                0x01000000U            /*!<Bit 2 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                0x02000000U            /*!<Bit 3 */
-#define USB_OTG_DIEPCTL_CNAK                    0x04000000U            /*!< Clear NAK */
-#define USB_OTG_DIEPCTL_SNAK                    0x08000000U            /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          0x10000000U            /*!< Set DATA0 PID */
-#define USB_OTG_DIEPCTL_SODDFRM                 0x20000000U            /*!< Set odd frame */
-#define USB_OTG_DIEPCTL_EPDIS                   0x40000000U            /*!< Endpoint disable */
-#define USB_OTG_DIEPCTL_EPENA                   0x80000000U            /*!< Endpoint enable */
-
-/********************  Bit definition forUSB_OTG_HCCHAR register  ********************/
-#define USB_OTG_HCCHAR_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
-
-#define USB_OTG_HCCHAR_EPNUM                   0x00007800U            /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPNUM_1                 0x00001000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_EPNUM_2                 0x00002000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_EPNUM_3                 0x00004000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_EPDIR                   0x00008000U            /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV                   0x00020000U            /*!< Low-speed device */
-
-#define USB_OTG_HCCHAR_EPTYP                   0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_MC                      0x00300000U            /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                    0x00100000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_MC_1                    0x00200000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_DAD                     0x1FC00000U            /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                   0x00400000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_DAD_1                   0x00800000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_DAD_2                   0x01000000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_DAD_3                   0x02000000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_DAD_4                   0x04000000U            /*!<Bit 4 */
-#define USB_OTG_HCCHAR_DAD_5                   0x08000000U            /*!<Bit 5 */
-#define USB_OTG_HCCHAR_DAD_6                   0x10000000U            /*!<Bit 6 */
-#define USB_OTG_HCCHAR_ODDFRM                  0x20000000U            /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS                   0x40000000U            /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA                   0x80000000U            /*!< Channel enable */
-
-/********************  Bit definition forUSB_OTG_HCSPLT register  ********************/
-
-#define USB_OTG_HCSPLT_PRTADDR                 0x0000007FU            /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_PRTADDR_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_PRTADDR_2               0x00000004U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_PRTADDR_3               0x00000008U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_PRTADDR_4               0x00000010U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_PRTADDR_5               0x00000020U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_PRTADDR_6               0x00000040U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_HUBADDR                 0x00003F80U            /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0               0x00000080U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_HUBADDR_1               0x00000100U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_HUBADDR_2               0x00000200U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_HUBADDR_3               0x00000400U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_HUBADDR_4               0x00000800U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_HUBADDR_5               0x00001000U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_HUBADDR_6               0x00002000U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_XACTPOS                 0x0000C000U            /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0               0x00004000U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_XACTPOS_1               0x00008000U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_COMPLSPLT               0x00010000U            /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN                 0x80000000U            /*!< Split enable */
-
-/********************  Bit definition forUSB_OTG_HCINT register  ********************/
-#define USB_OTG_HCINT_XFRC                    0x00000001U            /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH                     0x00000002U            /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINT_STALL                   0x00000008U            /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK                     0x00000010U            /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK                     0x00000020U            /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET                    0x00000040U            /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR                   0x00000080U            /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR                   0x00000100U            /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR                   0x00000200U            /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR                   0x00000400U            /*!< Data toggle error */
-
-/********************  Bit definition forUSB_OTG_DIEPINT register  ********************/
-#define USB_OTG_DIEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_TOC                     0x00000008U            /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE                  0x00000010U            /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNE                  0x00000040U            /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE                    0x00000080U            /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN              0x00000100U            /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA                     0x00000200U            /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS               0x00000800U            /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR                    0x00001000U            /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK                     0x00002000U            /*!< NAK interrupt */
-
-/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
-#define USB_OTG_HCINTMSK_XFRCM                   0x00000001U            /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM                    0x00000002U            /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM                  0x00000008U            /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM                    0x00000010U            /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM                    0x00000020U            /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET                    0x00000040U            /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM                  0x00000080U            /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM                  0x00000100U            /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM                  0x00000200U            /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM                  0x00000400U            /*!< Data toggle error mask */
-
-/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
-
-#define USB_OTG_DIEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT                  0x60000000U            /*!< Packet count */
-/********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/
-#define USB_OTG_HCTSIZ_XFRSIZ                    0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT                    0x1FF80000U            /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING                    0x80000000U            /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID                      0x60000000U            /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                    0x20000000U            /*!<Bit 0 */
-#define USB_OTG_HCTSIZ_DPID_1                    0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/
-#define USB_OTG_DIEPDMA_DMAADDR                  0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition forUSB_OTG_HCDMA register  ********************/
-#define USB_OTG_HCDMA_DMAADDR                    0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/
-#define USB_OTG_DTXFSTS_INEPTFSAV                0x0000FFFFU            /*!< IN endpoint TxFIFO space avail */
-
-/********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/
-#define USB_OTG_DIEPTXF_INEPTXSA                 0x0000FFFFU            /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD                 0xFFFF0000U            /*!< IN endpoint TxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/
-
-#define USB_OTG_DOEPCTL_MPSIZ                     0x000007FFU            /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP                    0x00008000U            /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS                    0x00020000U            /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            0x10000000U            /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM                   0x20000000U            /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP                     0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                   0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DOEPCTL_EPTYP_1                   0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_SNPM                      0x00100000U            /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL                     0x00200000U            /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK                      0x04000000U            /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK                      0x08000000U            /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS                     0x40000000U            /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA                     0x80000000U            /*!< Endpoint enable */
-
-/********************  Bit definition forUSB_OTG_DOEPINT register  ********************/
-#define USB_OTG_DOEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_STUP                    0x00000008U            /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS                 0x00000010U            /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_NYET                    0x00004000U            /*!< NYET interrupt */
-
-/********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/
-
-#define USB_OTG_DOEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-
-#define USB_OTG_DOEPTSIZ_STUPCNT                 0x60000000U            /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0               0x20000000U            /*!<Bit 0 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1               0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition for PCGCCTL register  ********************/
-#define USB_OTG_PCGCCTL_STOPCLK                 0x00000001U            /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK                 0x00000002U            /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP                 0x00000010U            /*!<Bit 1 */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
- 
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
-                                       ((INSTANCE) == ADC2) || \
-                                       ((INSTANCE) == ADC3))
-
-/******************************* CAN Instances ********************************/
-#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
-                                       ((INSTANCE) == CAN2))
- 
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DAC Instances ********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/******************************** DMA Instances *******************************/
-#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
-                                              ((INSTANCE) == DMA1_Stream1) || \
-                                              ((INSTANCE) == DMA1_Stream2) || \
-                                              ((INSTANCE) == DMA1_Stream3) || \
-                                              ((INSTANCE) == DMA1_Stream4) || \
-                                              ((INSTANCE) == DMA1_Stream5) || \
-                                              ((INSTANCE) == DMA1_Stream6) || \
-                                              ((INSTANCE) == DMA1_Stream7) || \
-                                              ((INSTANCE) == DMA2_Stream0) || \
-                                              ((INSTANCE) == DMA2_Stream1) || \
-                                              ((INSTANCE) == DMA2_Stream2) || \
-                                              ((INSTANCE) == DMA2_Stream3) || \
-                                              ((INSTANCE) == DMA2_Stream4) || \
-                                              ((INSTANCE) == DMA2_Stream5) || \
-                                              ((INSTANCE) == DMA2_Stream6) || \
-                                              ((INSTANCE) == DMA2_Stream7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOF) || \
-                                        ((INSTANCE) == GPIOG) || \
-                                        ((INSTANCE) == GPIOH) || \
-                                        ((INSTANCE) == GPIOI))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2) || \
-                                       ((INSTANCE) == I2C3))
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI2) || \
-                                    ((INSTANCE) == SPI3))
-
-/*************************** I2S Extended Instances ***************************/
-#define IS_I2S_ALL_INSTANCE_EXT(PERIPH)  (((INSTANCE) == SPI2)    || \
-                                          ((INSTANCE) == SPI3)    || \
-                                          ((INSTANCE) == I2S2ext) || \
-                                          ((INSTANCE) == I2S3ext))
-
-/******************************* RNG Instances ********************************/
-#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-
-/*************************** SPI Extended Instances ***************************/
-#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1)    || \
-                                           ((INSTANCE) == SPI2)    || \
-                                           ((INSTANCE) == SPI3)    || \
-                                           ((INSTANCE) == I2S2ext) || \
-                                           ((INSTANCE) == I2S3ext))
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
-                                   ((INSTANCE) == TIM2)   || \
-                                   ((INSTANCE) == TIM3)   || \
-                                   ((INSTANCE) == TIM4)   || \
-                                   ((INSTANCE) == TIM5)   || \
-                                   ((INSTANCE) == TIM6)   || \
-                                   ((INSTANCE) == TIM7)   || \
-                                   ((INSTANCE) == TIM8)   || \
-                                   ((INSTANCE) == TIM9)   || \
-                                   ((INSTANCE) == TIM10)  || \
-                                   ((INSTANCE) == TIM11)  || \
-                                   ((INSTANCE) == TIM12)  || \
-                                   ((INSTANCE) == TIM13)  || \
-                                   ((INSTANCE) == TIM14))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
-                                         ((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM8)  || \
-                                         ((INSTANCE) == TIM9)  || \
-                                         ((INSTANCE) == TIM10) || \
-                                         ((INSTANCE) == TIM11) || \
-                                         ((INSTANCE) == TIM12) || \
-                                         ((INSTANCE) == TIM13) || \
-                                         ((INSTANCE) == TIM14))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM8) || \
-                                       ((INSTANCE) == TIM9) || \
-                                       ((INSTANCE) == TIM12))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8))
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM8))
-
-/******************** TIM Instances : Advanced-control timers *****************/
-#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                            ((INSTANCE) == TIM8))
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8))
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM6) || \
-                                       ((INSTANCE) == TIM7) || \
-                                       ((INSTANCE) == TIM8))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM8))
-
-/************ TIM Instances : DMA requests generation (COMDE) *****************/
-#define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM8)) 
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                             ((INSTANCE) == TIM2) || \
-                                             ((INSTANCE) == TIM3) || \
-                                             ((INSTANCE) == TIM4) || \
-                                             ((INSTANCE) == TIM5) || \
-                                             ((INSTANCE) == TIM8))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM6) || \
-                                          ((INSTANCE) == TIM7) || \
-                                          ((INSTANCE) == TIM8) || \
-                                          ((INSTANCE) == TIM9) || \
-                                          ((INSTANCE) == TIM12))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8) || \
-                                         ((INSTANCE) == TIM9) || \
-                                         ((INSTANCE) == TIM12))
-
-/********************** TIM Instances : 32 bit Counter ************************/
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
-                                              ((INSTANCE) == TIM5))
-
-/***************** TIM Instances : external trigger input availabe ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                        ((INSTANCE) == TIM2) || \
-                                        ((INSTANCE) == TIM3) || \
-                                        ((INSTANCE) == TIM4) || \
-                                        ((INSTANCE) == TIM5) || \
-                                        ((INSTANCE) == TIM8))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM11))
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM1) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM5) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM8) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM12) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM13) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM14) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-/************ TIM Instances : complementary output(s) available ***************/
-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
-   ((((INSTANCE) == TIM1) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3)))            \
-    ||                                          \
-    (((INSTANCE) == TIM8) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3))))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3) || \
-                                     ((INSTANCE) == USART6))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5)  || \
-                                    ((INSTANCE) == USART6))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3) || \
-                                           ((INSTANCE) == USART6))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3) || \
-                                         ((INSTANCE) == USART6))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5)  || \
-                                    ((INSTANCE) == USART6))     
-
-/*********************** PCD Instances ****************************************/
-/*********************** PCD Instances ****************************************/
-#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
-                                        ((INSTANCE) == USB_OTG_HS))
-
-/*********************** HCD Instances ****************************************/
-#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
-                                       ((INSTANCE) == USB_OTG_HS))
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/****************************** SDIO Instances ********************************/
-#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
-
-/****************************** USB Exported Constants ************************/
-#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                8U
-#define USB_OTG_FS_MAX_IN_ENDPOINTS                    4U    /* Including EP0 */
-#define USB_OTG_FS_MAX_OUT_ENDPOINTS                   4U    /* Including EP0 */
-#define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */
-
-#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR                12U
-#define USB_OTG_HS_MAX_IN_ENDPOINTS                    6U    /* Including EP0 */
-#define USB_OTG_HS_MAX_OUT_ENDPOINTS                   6U    /* Including EP0 */
-#define USB_OTG_HS_TOTAL_FIFO_SIZE                     4096U /* in Bytes */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32F4xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */
-/*  product lines within the same STM32F4 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-#define FMC_IRQn              FSMC_IRQn
-
-/* Aliases for __IRQHandler */
-#define FMC_IRQHandler        FSMC_IRQHandler
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32F405xx_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/cmsis/stm32f407xx.h b/stmhal/cmsis/stm32f407xx.h
deleted file mode 100644
index 115394902c..0000000000
--- a/stmhal/cmsis/stm32f407xx.h
+++ /dev/null
@@ -1,8140 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f407xx.h
-  * @author  MCD Application Team
-  * @version V2.5.1
-  * @date    28-June-2016
-  * @brief   CMSIS STM32F407xx Device Peripheral Access Layer Header File.
-  *
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - peripherals registers declarations and bits definition
-  *           - Macros to access peripheral’s registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f407xx
-  * @{
-  */
-    
-#ifndef __STM32F407xx_H
-#define __STM32F407xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-  
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-
-/**
-  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
-  */
-#define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */
-#define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */
-#define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1U       /*!< FPU present                                   */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32F4XX Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-typedef enum
-{
-/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
-  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
-/******  STM32 specific Interrupt Numbers **********************************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
-  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
-  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
-  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
-  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
-  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
-  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
-  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
-  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
-  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
-  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
-  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
-  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
-  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
-  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
-  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
-  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
-  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */    
-  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
-  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
-  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
-  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
-  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
-  FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                             */
-  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
-  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
-  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
-  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
-  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
-  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
-  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
-  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
-  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
-  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
-  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
-  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
-  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
-  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
-  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
-  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
-  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
-  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
-  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
-  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
-  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
-  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
-  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
-  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
-  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
-  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
-  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
-  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
-  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
-  HASH_RNG_IRQn               = 80,     /*!< Hash and RNG global interrupt                                     */
-  FPU_IRQn                    = 81      /*!< FPU global interrupt                                              */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
-#include "system_stm32f4xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */      
-  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
-  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
-  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
-  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
-  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
-  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
-  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
-  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
-  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
-  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
-  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
-  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
-  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
-  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
-  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
-                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
-} ADC_Common_TypeDef;
-
-
-/** 
-  * @brief Controller Area Network TxMailBox 
-  */
-
-typedef struct
-{
-  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
-  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
-  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
-  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
-} CAN_TxMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FIFOMailBox 
-  */
-  
-typedef struct
-{
-  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
-  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
-  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
-  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
-} CAN_FIFOMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FilterRegister 
-  */
-  
-typedef struct
-{
-  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
-  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
-} CAN_FilterRegister_TypeDef;
-
-/** 
-  * @brief Controller Area Network 
-  */
-  
-typedef struct
-{
-  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
-  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
-  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
-  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
-  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
-  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
-  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
-  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
-  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
-  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
-  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
-  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
-  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
-  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
-  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
-  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
-  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
-  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
-  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
-  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
-  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */ 
-  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
-} CAN_TypeDef;
-
-/** 
-  * @brief CRC calculation unit 
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
-  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */
-  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
-  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
-  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
-  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
-  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
-  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
-  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
-  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
-  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
-  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
-  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
-  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
-  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
-  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
-  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
-  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
-  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
-  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DCMI
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
-  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
-  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
-  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
-  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
-  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
-  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
-  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
-  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
-  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
-  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
-} DCMI_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
-  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
-  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
-  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
-  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
-  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
-} DMA_Stream_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
-  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
-  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
-  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
-} DMA_TypeDef;
-
-
-/** 
-  * @brief Ethernet MAC
-  */
-
-typedef struct
-{
-  __IO uint32_t MACCR;
-  __IO uint32_t MACFFR;
-  __IO uint32_t MACHTHR;
-  __IO uint32_t MACHTLR;
-  __IO uint32_t MACMIIAR;
-  __IO uint32_t MACMIIDR;
-  __IO uint32_t MACFCR;
-  __IO uint32_t MACVLANTR;             /*    8 */
-  uint32_t      RESERVED0[2];
-  __IO uint32_t MACRWUFFR;             /*   11 */
-  __IO uint32_t MACPMTCSR;
-  uint32_t      RESERVED1[2];
-  __IO uint32_t MACSR;                 /*   15 */
-  __IO uint32_t MACIMR;
-  __IO uint32_t MACA0HR;
-  __IO uint32_t MACA0LR;
-  __IO uint32_t MACA1HR;
-  __IO uint32_t MACA1LR;
-  __IO uint32_t MACA2HR;
-  __IO uint32_t MACA2LR;
-  __IO uint32_t MACA3HR;
-  __IO uint32_t MACA3LR;               /*   24 */
-  uint32_t      RESERVED2[40];
-  __IO uint32_t MMCCR;                 /*   65 */
-  __IO uint32_t MMCRIR;
-  __IO uint32_t MMCTIR;
-  __IO uint32_t MMCRIMR;
-  __IO uint32_t MMCTIMR;               /*   69 */
-  uint32_t      RESERVED3[14];
-  __IO uint32_t MMCTGFSCCR;            /*   84 */
-  __IO uint32_t MMCTGFMSCCR;
-  uint32_t      RESERVED4[5];
-  __IO uint32_t MMCTGFCR;
-  uint32_t      RESERVED5[10];
-  __IO uint32_t MMCRFCECR;
-  __IO uint32_t MMCRFAECR;
-  uint32_t      RESERVED6[10];
-  __IO uint32_t MMCRGUFCR;
-  uint32_t      RESERVED7[334];
-  __IO uint32_t PTPTSCR;
-  __IO uint32_t PTPSSIR;
-  __IO uint32_t PTPTSHR;
-  __IO uint32_t PTPTSLR;
-  __IO uint32_t PTPTSHUR;
-  __IO uint32_t PTPTSLUR;
-  __IO uint32_t PTPTSAR;
-  __IO uint32_t PTPTTHR;
-  __IO uint32_t PTPTTLR;
-  __IO uint32_t RESERVED8;
-  __IO uint32_t PTPTSSR;
-  uint32_t      RESERVED9[565];
-  __IO uint32_t DMABMR;
-  __IO uint32_t DMATPDR;
-  __IO uint32_t DMARPDR;
-  __IO uint32_t DMARDLAR;
-  __IO uint32_t DMATDLAR;
-  __IO uint32_t DMASR;
-  __IO uint32_t DMAOMR;
-  __IO uint32_t DMAIER;
-  __IO uint32_t DMAMFBOCR;
-  __IO uint32_t DMARSWTR;
-  uint32_t      RESERVED10[8];
-  __IO uint32_t DMACHTDR;
-  __IO uint32_t DMACHRDR;
-  __IO uint32_t DMACHTBAR;
-  __IO uint32_t DMACHRBAR;
-} ETH_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
-  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
-  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
-  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
-  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
-  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-
-typedef struct
-{
-  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */
-  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */
-  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */
-  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */
-  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */
-  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */
-} FLASH_TypeDef;
-
-
-/** 
-  * @brief Flexible Static Memory Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */   
-} FSMC_Bank1_TypeDef; 
-
-/** 
-  * @brief Flexible Static Memory Controller Bank1E
-  */
-  
-typedef struct
-{
-  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
-} FSMC_Bank1E_TypeDef;
-
-/** 
-  * @brief Flexible Static Memory Controller Bank2
-  */
-  
-typedef struct
-{
-  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */
-  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */
-  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */
-  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
-  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */
-  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */
-  uint32_t      RESERVED1;  /*!< Reserved, 0x78                                                            */
-  uint32_t      RESERVED2;  /*!< Reserved, 0x7C                                                            */
-  __IO uint32_t PCR3;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */
-  __IO uint32_t SR3;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */
-  __IO uint32_t PMEM3;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */
-  __IO uint32_t PATT3;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
-  uint32_t      RESERVED3;  /*!< Reserved, 0x90                                                            */
-  __IO uint32_t ECCR3;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */
-} FSMC_Bank2_3_TypeDef;
-
-/** 
-  * @brief Flexible Static Memory Controller Bank4
-  */
-  
-typedef struct
-{
-  __IO uint32_t PCR4;       /*!< PC Card  control register 4,                       Address offset: 0xA0 */
-  __IO uint32_t SR4;        /*!< PC Card  FIFO status and interrupt register 4,     Address offset: 0xA4 */
-  __IO uint32_t PMEM4;      /*!< PC Card  Common memory space timing register 4,    Address offset: 0xA8 */
-  __IO uint32_t PATT4;      /*!< PC Card  Attribute memory space timing register 4, Address offset: 0xAC */
-  __IO uint32_t PIO4;       /*!< PC Card  I/O space timing register 4,              Address offset: 0xB0 */
-} FSMC_Bank4_TypeDef; 
-
-
-/** 
-  * @brief General Purpose I/O
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
-  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
-  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
-  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
-  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
-  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
-  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
-  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/** 
-  * @brief System configuration controller
-  */
-  
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */ 
-  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */
-  __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */
-  __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */
-  __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */
-  __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */
-  __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
-  __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
-  __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
-  __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
-  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
-  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
-  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
-  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
-  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
-  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
-  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
-  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
-  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
-  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
-  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
-  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
-  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
-  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
-  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
-  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
-  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
-  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
-  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
-  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
-  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
-
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-
-typedef struct
-{
-  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
-  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
-  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
-  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
-  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
-  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
-  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */
-  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
-  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */
-  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
-  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */
-  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */
-  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */
-  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */
-  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
-  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */
-  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
-  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
-  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
-  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
-  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
-  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
-  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
-  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
-  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
-  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
-  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
-  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
-  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
-  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
-  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
-  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
-  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
-  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
-  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
-  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
-  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
-} RTC_TypeDef;
-
-
-/** 
-  * @brief SD host Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t POWER;          /*!< SDIO power control register,    Address offset: 0x00 */
-  __IO uint32_t CLKCR;          /*!< SDI clock control register,     Address offset: 0x04 */
-  __IO uint32_t ARG;            /*!< SDIO argument register,         Address offset: 0x08 */
-  __IO uint32_t CMD;            /*!< SDIO command register,          Address offset: 0x0C */
-  __I uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */
-  __I uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */
-  __I uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */
-  __I uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */
-  __I uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */
-  __IO uint32_t DTIMER;         /*!< SDIO data timer register,       Address offset: 0x24 */
-  __IO uint32_t DLEN;           /*!< SDIO data length register,      Address offset: 0x28 */
-  __IO uint32_t DCTRL;          /*!< SDIO data control register,     Address offset: 0x2C */
-  __I uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */
-  __I uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */
-  __IO uint32_t ICR;            /*!< SDIO interrupt clear register,  Address offset: 0x38 */
-  __IO uint32_t MASK;           /*!< SDIO mask register,             Address offset: 0x3C */
-  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
-  __I uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */
-  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
-  __IO uint32_t FIFO;           /*!< SDIO data FIFO register,        Address offset: 0x80 */
-} SDIO_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
-  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
-  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
-  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief RNG
-  */
-  
-typedef struct 
-{
-  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
-  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
-  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
-} RNG_TypeDef;
-
-
- 
-/** 
-  * @brief __USB_OTG_Core_register
-  */
-typedef struct
-{
-  __IO uint32_t GOTGCTL;      /*!<  USB_OTG Control and Status Register    000h*/
-  __IO uint32_t GOTGINT;      /*!<  USB_OTG Interrupt Register             004h*/
-  __IO uint32_t GAHBCFG;      /*!<  Core AHB Configuration Register    008h*/
-  __IO uint32_t GUSBCFG;      /*!<  Core USB Configuration Register    00Ch*/
-  __IO uint32_t GRSTCTL;      /*!<  Core Reset Register                010h*/
-  __IO uint32_t GINTSTS;      /*!<  Core Interrupt Register            014h*/
-  __IO uint32_t GINTMSK;      /*!<  Core Interrupt Mask Register       018h*/
-  __IO uint32_t GRXSTSR;      /*!<  Receive Sts Q Read Register        01Ch*/
-  __IO uint32_t GRXSTSP;      /*!<  Receive Sts Q Read & POP Register  020h*/
-  __IO uint32_t GRXFSIZ;      /* Receive FIFO Size Register         024h*/
-  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!<  EP0 / Non Periodic Tx FIFO Size Register 028h*/
-  __IO uint32_t HNPTXSTS;     /*!<  Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
-  uint32_t Reserved30[2];     /* Reserved                           030h*/
-  __IO uint32_t GCCFG;        /* General Purpose IO Register        038h*/
-  __IO uint32_t CID;          /* User ID Register                   03Ch*/
-  uint32_t  Reserved40[48];   /* Reserved                      040h-0FFh*/
-  __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg     100h*/
-  __IO uint32_t DIEPTXF[0x0F];/* dev Periodic Transmit FIFO */
-}
-USB_OTG_GlobalTypeDef;
-
-
-
-/** 
-  * @brief __device_Registers
-  */
-typedef struct 
-{
-  __IO uint32_t DCFG;         /* dev Configuration Register   800h*/
-  __IO uint32_t DCTL;         /* dev Control Register         804h*/
-  __IO uint32_t DSTS;         /* dev Status Register (RO)     808h*/
-  uint32_t Reserved0C;           /* Reserved                     80Ch*/
-  __IO uint32_t DIEPMSK;   /* dev IN Endpoint Mask         810h*/
-  __IO uint32_t DOEPMSK;  /* dev OUT Endpoint Mask        814h*/
-  __IO uint32_t DAINT;     /* dev All Endpoints Itr Reg    818h*/
-  __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask   81Ch*/
-  uint32_t  Reserved20;          /* Reserved                     820h*/
-  uint32_t Reserved9;       /* Reserved                     824h*/
-  __IO uint32_t DVBUSDIS;    /* dev VBUS discharge Register  828h*/
-  __IO uint32_t DVBUSPULSE;  /* dev VBUS Pulse Register      82Ch*/
-  __IO uint32_t DTHRCTL;     /* dev thr                      830h*/
-  __IO uint32_t DIEPEMPMSK; /* dev empty msk             834h*/
-  __IO uint32_t DEACHINT;    /* dedicated EP interrupt       838h*/
-  __IO uint32_t DEACHMSK;    /* dedicated EP msk             83Ch*/  
-  uint32_t Reserved40;      /* dedicated EP mask           840h*/
-  __IO uint32_t DINEP1MSK;  /* dedicated EP mask           844h*/
-  uint32_t  Reserved44[15];      /* Reserved                 844-87Ch*/
-  __IO uint32_t DOUTEP1MSK; /* dedicated EP msk            884h*/   
-}
-USB_OTG_DeviceTypeDef;
-
-
-/** 
-  * @brief __IN_Endpoint-Specific_Register
-  */
-typedef struct 
-{
-  __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
-  uint32_t Reserved04;             /* Reserved                       900h + (ep_num * 20h) + 04h*/
-  __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg     900h + (ep_num * 20h) + 08h*/
-  uint32_t Reserved0C;             /* Reserved                       900h + (ep_num * 20h) + 0Ch*/
-  __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size   900h + (ep_num * 20h) + 10h*/
-  __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h*/
-  __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
-  uint32_t Reserved18;             /* Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
-}
-USB_OTG_INEndpointTypeDef;
-
-
-/** 
-  * @brief __OUT_Endpoint-Specific_Registers
-  */
-typedef struct 
-{
-  __IO uint32_t DOEPCTL;       /* dev OUT Endpoint Control Reg  B00h + (ep_num * 20h) + 00h*/
-  uint32_t Reserved04;         /* Reserved                      B00h + (ep_num * 20h) + 04h*/
-  __IO uint32_t DOEPINT;       /* dev OUT Endpoint Itr Reg      B00h + (ep_num * 20h) + 08h*/
-  uint32_t Reserved0C;         /* Reserved                      B00h + (ep_num * 20h) + 0Ch*/
-  __IO uint32_t DOEPTSIZ;      /* dev OUT Endpoint Txfer Size   B00h + (ep_num * 20h) + 10h*/
-  __IO uint32_t DOEPDMA;       /* dev OUT Endpoint DMA Address  B00h + (ep_num * 20h) + 14h*/
-  uint32_t Reserved18[2];      /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
-}
-USB_OTG_OUTEndpointTypeDef;
-
-
-/** 
-  * @brief __Host_Mode_Register_Structures
-  */
-typedef struct 
-{
-  __IO uint32_t HCFG;             /* Host Configuration Register    400h*/
-  __IO uint32_t HFIR;      /* Host Frame Interval Register   404h*/
-  __IO uint32_t HFNUM;         /* Host Frame Nbr/Frame Remaining 408h*/
-  uint32_t Reserved40C;                   /* Reserved                       40Ch*/
-  __IO uint32_t HPTXSTS;   /* Host Periodic Tx FIFO/ Queue Status 410h*/
-  __IO uint32_t HAINT;   /* Host All Channels Interrupt Register 414h*/
-  __IO uint32_t HAINTMSK;   /* Host All Channels Interrupt Mask 418h*/
-}
-USB_OTG_HostTypeDef;
-
-
-/** 
-  * @brief __Host_Channel_Specific_Registers
-  */
-typedef struct
-{
-  __IO uint32_t HCCHAR;
-  __IO uint32_t HCSPLT;
-  __IO uint32_t HCINT;
-  __IO uint32_t HCINTMSK;
-  __IO uint32_t HCTSIZ;
-  __IO uint32_t HCDMA;
-  uint32_t Reserved[2];
-}
-USB_OTG_HostChannelTypeDef;
-
-    
-/** 
-  * @brief Peripheral_memory_map
-  */
-#define FLASH_BASE            0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region                         */
-#define CCMDATARAM_BASE       0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
-#define SRAM1_BASE            0x20000000U /*!< SRAM1(112 KB) base address in the alias region                             */
-#define SRAM2_BASE            0x2001C000U /*!< SRAM2(16 KB) base address in the alias region                              */
-#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region                                */
-#define BKPSRAM_BASE          0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region                         */
-#define FSMC_R_BASE           0xA0000000U /*!< FSMC registers base address                                                */
-#define SRAM1_BB_BASE         0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region                             */
-#define SRAM2_BB_BASE         0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region                              */
-#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region                                */
-#define BKPSRAM_BB_BASE       0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region                         */
-#define FLASH_END             0x080FFFFFU /*!< FLASH end address */
-#define CCMDATARAM_END        0x1000FFFFU /*!< CCM data RAM end address */
-
-/* Legacy defines */
-#define SRAM_BASE             SRAM1_BASE
-#define SRAM_BB_BASE          SRAM1_BB_BASE
-
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000U)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)
-#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800U)
-#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00U)
-#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000U)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)
-#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400U)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)
-#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000U)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800U)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00U)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x5000U)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)
-#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)
-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)
-#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800U)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)
-
-/*!< APB2 peripherals */
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000U)
-#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400U)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x1000U)
-#define USART6_BASE           (APB2PERIPH_BASE + 0x1400U)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000U)
-#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100U)
-#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200U)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x2300U)
-#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00U)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800U)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00U)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000U)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400U)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800U)
-
-/*!< AHB1 peripherals */
-#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000U)
-#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400U)
-#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800U)
-#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00U)
-#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000U)
-#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400U)
-#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800U)
-#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00U)
-#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000U)
-#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)
-#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800U)
-#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00U)
-#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000U)
-#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010U)
-#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028U)
-#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040U)
-#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058U)
-#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070U)
-#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088U)
-#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0U)
-#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8U)
-#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400U)
-#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010U)
-#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028U)
-#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040U)
-#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058U)
-#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070U)
-#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088U)
-#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0U)
-#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)
-#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000U)
-#define ETH_MAC_BASE          (ETH_BASE)
-#define ETH_MMC_BASE          (ETH_BASE + 0x0100U)
-#define ETH_PTP_BASE          (ETH_BASE + 0x0700U)
-#define ETH_DMA_BASE          (ETH_BASE + 0x1000U)
-
-/*!< AHB2 peripherals */
-#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000U)
-#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800U)
-
-/*!< FSMC Bankx registers base address */
-#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000U)
-#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104U)
-#define FSMC_Bank2_3_R_BASE   (FSMC_R_BASE + 0x0060U)
-#define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0U)
-
-/* Debug MCU registers base address */
-#define DBGMCU_BASE           0xE0042000U
-
-/*!< USB registers base address */
-#define USB_OTG_HS_PERIPH_BASE               0x40040000U
-#define USB_OTG_FS_PERIPH_BASE               0x50000000U
-
-#define USB_OTG_GLOBAL_BASE                  0x000U
-#define USB_OTG_DEVICE_BASE                  0x800U
-#define USB_OTG_IN_ENDPOINT_BASE             0x900U
-#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U
-#define USB_OTG_EP_REG_SIZE                  0x20U
-#define USB_OTG_HOST_BASE                    0x400U
-#define USB_OTG_HOST_PORT_BASE               0x440U
-#define USB_OTG_HOST_CHANNEL_BASE            0x500U
-#define USB_OTG_HOST_CHANNEL_SIZE            0x20U
-#define USB_OTG_PCGCCTL_BASE                 0xE00U
-#define USB_OTG_FIFO_BASE                    0x1000U
-#define USB_OTG_FIFO_SIZE                    0x1000U
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
-#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
-#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define UART4               ((USART_TypeDef *) UART4_BASE)
-#define UART5               ((USART_TypeDef *) UART5_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
-#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
-#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
-#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define USART6              ((USART_TypeDef *) USART6_BASE)
-#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
-#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
-#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE) 
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
-#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
-#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
-#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
-#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
-#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
-#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
-#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
-#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
-#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
-#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
-#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
-#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
-#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
-#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
-#define ETH                 ((ETH_TypeDef *) ETH_BASE)  
-#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
-#define RNG                 ((RNG_TypeDef *) RNG_BASE)
-#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
-#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
-#define FSMC_Bank2_3        ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)
-#define FSMC_Bank4          ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
-
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
-#define USB_OTG_HS          ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers_Bits_Definition               */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Analog to Digital Converter                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          0x00000001U       /*!<Analog watchdog flag */
-#define  ADC_SR_EOC                          0x00000002U       /*!<End of conversion */
-#define  ADC_SR_JEOC                         0x00000004U       /*!<Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        0x00000008U       /*!<Injected channel Start flag */
-#define  ADC_SR_STRT                         0x00000010U       /*!<Regular channel Start flag */
-#define  ADC_SR_OVR                          0x00000020U       /*!<Overrun flag */
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
-#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels */
-#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels */
-#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution) */
-#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
-  
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion */
-#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode */
-#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC) */
-#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection */
-#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment */
-#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      0xFFFFU            /*!<Injected data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag */
-#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion */
-#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag */
-#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag */
-#define  ADC_CSR_OVR1                        0x00000020U        /*!<ADC1 DMA overrun  flag */
-#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag */
-#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion */
-#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag */
-#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag */
-#define  ADC_CSR_OVR2                        0x00002000U        /*!<ADC2 DMA overrun  flag */
-#define  ADC_CSR_AWD3                        0x00010000U        /*!<ADC3 Analog watchdog flag */
-#define  ADC_CSR_EOC3                        0x00020000U        /*!<ADC3 End of conversion */
-#define  ADC_CSR_JEOC3                       0x00040000U        /*!<ADC3 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT3                      0x00080000U        /*!<ADC3 Injected channel Start flag */
-#define  ADC_CSR_STRT3                       0x00100000U        /*!<ADC3 Regular channel Start flag */
-#define  ADC_CSR_OVR3                        0x00200000U        /*!<ADC3 DMA overrun  flag */
-
-/* Legacy defines */
-#define  ADC_CSR_DOVR1                        ADC_CSR_OVR1
-#define  ADC_CSR_DOVR2                        ADC_CSR_OVR2
-#define  ADC_CSR_DOVR3                        ADC_CSR_OVR3
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
-#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
-#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
-#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
-#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
-
-/*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                      0x0000FFFFU         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                      0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Controller Area Network                            */
-/*                                                                            */
-/******************************************************************************/
-/*!<CAN control and status registers */
-/*******************  Bit definition for CAN_MCR register  ********************/
-#define  CAN_MCR_INRQ                        0x00000001U        /*!<Initialization Request */
-#define  CAN_MCR_SLEEP                       0x00000002U        /*!<Sleep Mode Request */
-#define  CAN_MCR_TXFP                        0x00000004U        /*!<Transmit FIFO Priority */
-#define  CAN_MCR_RFLM                        0x00000008U        /*!<Receive FIFO Locked Mode */
-#define  CAN_MCR_NART                        0x00000010U        /*!<No Automatic Retransmission */
-#define  CAN_MCR_AWUM                        0x00000020U        /*!<Automatic Wakeup Mode */
-#define  CAN_MCR_ABOM                        0x00000040U        /*!<Automatic Bus-Off Management */
-#define  CAN_MCR_TTCM                        0x00000080U        /*!<Time Triggered Communication Mode */
-#define  CAN_MCR_RESET                       0x00008000U        /*!<bxCAN software master reset */
-#define  CAN_MCR_DBF                         0x00010000U        /*!<bxCAN Debug freeze */
-/*******************  Bit definition for CAN_MSR register  ********************/
-#define  CAN_MSR_INAK                        0x0001U            /*!<Initialization Acknowledge */
-#define  CAN_MSR_SLAK                        0x0002U            /*!<Sleep Acknowledge */
-#define  CAN_MSR_ERRI                        0x0004U            /*!<Error Interrupt */
-#define  CAN_MSR_WKUI                        0x0008U            /*!<Wakeup Interrupt */
-#define  CAN_MSR_SLAKI                       0x0010U            /*!<Sleep Acknowledge Interrupt */
-#define  CAN_MSR_TXM                         0x0100U            /*!<Transmit Mode */
-#define  CAN_MSR_RXM                         0x0200U            /*!<Receive Mode */
-#define  CAN_MSR_SAMP                        0x0400U            /*!<Last Sample Point */
-#define  CAN_MSR_RX                          0x0800U            /*!<CAN Rx Signal */
-
-/*******************  Bit definition for CAN_TSR register  ********************/
-#define  CAN_TSR_RQCP0                       0x00000001U        /*!<Request Completed Mailbox0 */
-#define  CAN_TSR_TXOK0                       0x00000002U        /*!<Transmission OK of Mailbox0 */
-#define  CAN_TSR_ALST0                       0x00000004U        /*!<Arbitration Lost for Mailbox0 */
-#define  CAN_TSR_TERR0                       0x00000008U        /*!<Transmission Error of Mailbox0 */
-#define  CAN_TSR_ABRQ0                       0x00000080U        /*!<Abort Request for Mailbox0 */
-#define  CAN_TSR_RQCP1                       0x00000100U        /*!<Request Completed Mailbox1 */
-#define  CAN_TSR_TXOK1                       0x00000200U        /*!<Transmission OK of Mailbox1 */
-#define  CAN_TSR_ALST1                       0x00000400U        /*!<Arbitration Lost for Mailbox1 */
-#define  CAN_TSR_TERR1                       0x00000800U        /*!<Transmission Error of Mailbox1 */
-#define  CAN_TSR_ABRQ1                       0x00008000U        /*!<Abort Request for Mailbox 1 */
-#define  CAN_TSR_RQCP2                       0x00010000U        /*!<Request Completed Mailbox2 */
-#define  CAN_TSR_TXOK2                       0x00020000U        /*!<Transmission OK of Mailbox 2 */
-#define  CAN_TSR_ALST2                       0x00040000U        /*!<Arbitration Lost for mailbox 2 */
-#define  CAN_TSR_TERR2                       0x00080000U        /*!<Transmission Error of Mailbox 2 */
-#define  CAN_TSR_ABRQ2                       0x00800000U        /*!<Abort Request for Mailbox 2 */
-#define  CAN_TSR_CODE                        0x03000000U        /*!<Mailbox Code */
-
-#define  CAN_TSR_TME                         0x1C000000U        /*!<TME[2:0] bits */
-#define  CAN_TSR_TME0                        0x04000000U        /*!<Transmit Mailbox 0 Empty */
-#define  CAN_TSR_TME1                        0x08000000U        /*!<Transmit Mailbox 1 Empty */
-#define  CAN_TSR_TME2                        0x10000000U        /*!<Transmit Mailbox 2 Empty */
-
-#define  CAN_TSR_LOW                         0xE0000000U        /*!<LOW[2:0] bits */
-#define  CAN_TSR_LOW0                        0x20000000U        /*!<Lowest Priority Flag for Mailbox 0 */
-#define  CAN_TSR_LOW1                        0x40000000U        /*!<Lowest Priority Flag for Mailbox 1 */
-#define  CAN_TSR_LOW2                        0x80000000U        /*!<Lowest Priority Flag for Mailbox 2 */
-
-/*******************  Bit definition for CAN_RF0R register  *******************/
-#define  CAN_RF0R_FMP0                       0x03U               /*!<FIFO 0 Message Pending */
-#define  CAN_RF0R_FULL0                      0x08U               /*!<FIFO 0 Full */
-#define  CAN_RF0R_FOVR0                      0x10U               /*!<FIFO 0 Overrun */
-#define  CAN_RF0R_RFOM0                      0x20U               /*!<Release FIFO 0 Output Mailbox */
-
-/*******************  Bit definition for CAN_RF1R register  *******************/
-#define  CAN_RF1R_FMP1                       0x03U               /*!<FIFO 1 Message Pending */
-#define  CAN_RF1R_FULL1                      0x08U               /*!<FIFO 1 Full */
-#define  CAN_RF1R_FOVR1                      0x10U               /*!<FIFO 1 Overrun */
-#define  CAN_RF1R_RFOM1                      0x20U               /*!<Release FIFO 1 Output Mailbox */
-
-/********************  Bit definition for CAN_IER register  *******************/
-#define  CAN_IER_TMEIE                       0x00000001U        /*!<Transmit Mailbox Empty Interrupt Enable */
-#define  CAN_IER_FMPIE0                      0x00000002U        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE0                       0x00000004U        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE0                      0x00000008U        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_FMPIE1                      0x00000010U        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE1                       0x00000020U        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE1                      0x00000040U        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error Warning Interrupt Enable */
-#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error Passive Interrupt Enable */
-#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-Off Interrupt Enable */
-#define  CAN_IER_LECIE                       0x00000800U        /*!<Last Error Code Interrupt Enable */
-#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error Interrupt Enable */
-#define  CAN_IER_WKUIE                       0x00010000U        /*!<Wakeup Interrupt Enable */
-#define  CAN_IER_SLKIE                       0x00020000U        /*!<Sleep Interrupt Enable */
-#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error warning interrupt enable */
-#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error passive interrupt enable */
-#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-off interrupt enable */
-#define  CAN_IER_LECIE                       0x00000800U        /*!<Last error code interrupt enable */
-#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error interrupt enable */
-
-
-/********************  Bit definition for CAN_ESR register  *******************/
-#define  CAN_ESR_EWGF                        0x00000001U        /*!<Error Warning Flag */
-#define  CAN_ESR_EPVF                        0x00000002U        /*!<Error Passive Flag */
-#define  CAN_ESR_BOFF                        0x00000004U        /*!<Bus-Off Flag */
-
-#define  CAN_ESR_LEC                         0x00000070U        /*!<LEC[2:0] bits (Last Error Code) */
-#define  CAN_ESR_LEC_0                       0x00000010U        /*!<Bit 0 */
-#define  CAN_ESR_LEC_1                       0x00000020U        /*!<Bit 1 */
-#define  CAN_ESR_LEC_2                       0x00000040U        /*!<Bit 2 */
-
-#define  CAN_ESR_TEC                         0x00FF0000U        /*!<Least significant byte of the 9-bit Transmit Error Counter */
-#define  CAN_ESR_REC                         0xFF000000U        /*!<Receive Error Counter */
-
-/*******************  Bit definition for CAN_BTR register  ********************/
-#define  CAN_BTR_BRP                         0x000003FFU        /*!<Baud Rate Prescaler */
-#define  CAN_BTR_TS1                         0x000F0000U        /*!<Time Segment 1 */
-#define  CAN_BTR_TS1_0                       0x00010000U        /*!<Bit 0 */
-#define  CAN_BTR_TS1_1                       0x00020000U        /*!<Bit 1 */
-#define  CAN_BTR_TS1_2                       0x00040000U        /*!<Bit 2 */
-#define  CAN_BTR_TS1_3                       0x00080000U        /*!<Bit 3 */
-#define  CAN_BTR_TS2                         0x00700000U        /*!<Time Segment 2 */
-#define  CAN_BTR_TS2_0                       0x00100000U        /*!<Bit 0 */
-#define  CAN_BTR_TS2_1                       0x00200000U        /*!<Bit 1 */
-#define  CAN_BTR_TS2_2                       0x00400000U        /*!<Bit 2 */
-#define  CAN_BTR_SJW                         0x03000000U        /*!<Resynchronization Jump Width */
-#define  CAN_BTR_SJW_0                       0x01000000U        /*!<Bit 0 */
-#define  CAN_BTR_SJW_1                       0x02000000U        /*!<Bit 1 */
-#define  CAN_BTR_LBKM                        0x40000000U        /*!<Loop Back Mode (Debug) */
-#define  CAN_BTR_SILM                        0x80000000U        /*!<Silent Mode */
-
-
-/*!<Mailbox registers */
-/******************  Bit definition for CAN_TI0R register  ********************/
-#define  CAN_TI0R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI0R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_TI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/******************  Bit definition for CAN_TDT0R register  *******************/
-#define  CAN_TDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT0R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/******************  Bit definition for CAN_TDL0R register  *******************/
-#define  CAN_TDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/******************  Bit definition for CAN_TDH0R register  *******************/
-#define  CAN_TDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI1R register  *******************/
-#define  CAN_TI1R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI1R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI1R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_TI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT1R register  ******************/
-#define  CAN_TDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT1R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL1R register  ******************/
-#define  CAN_TDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH1R register  ******************/
-#define  CAN_TDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI2R register  *******************/
-#define  CAN_TI2R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI2R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI2R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI2R_EXID                       0x001FFFF8U        /*!<Extended identifier */
-#define  CAN_TI2R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT2R register  ******************/  
-#define  CAN_TDT2R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT2R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT2R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL2R register  ******************/
-#define  CAN_TDL2R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL2R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL2R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL2R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH2R register  ******************/
-#define  CAN_TDH2R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH2R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH2R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH2R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI0R register  *******************/
-#define  CAN_RI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_RI0R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_RI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_RI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT0R register  ******************/
-#define  CAN_RDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_RDT0R_FMI                       0x0000FF00U        /*!<Filter Match Index */
-#define  CAN_RDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL0R register  ******************/
-#define  CAN_RDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_RDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_RDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_RDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH0R register  ******************/
-#define  CAN_RDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_RDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_RDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_RDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI1R register  *******************/
-#define  CAN_RI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_RI1R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_RI1R_EXID                       0x001FFFF8U        /*!<Extended identifier */
-#define  CAN_RI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT1R register  ******************/
-#define  CAN_RDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_RDT1R_FMI                       0x0000FF00U        /*!<Filter Match Index */
-#define  CAN_RDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL1R register  ******************/
-#define  CAN_RDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_RDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_RDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_RDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH1R register  ******************/
-#define  CAN_RDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_RDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_RDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_RDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*!<CAN filter registers */
-/*******************  Bit definition for CAN_FMR register  ********************/
-#define  CAN_FMR_FINIT                       0x01U               /*!<Filter Init Mode */
-#define  CAN_FMR_CAN2SB                      0x00003F00U        /*!<CAN2 start bank */
-
-/*******************  Bit definition for CAN_FM1R register  *******************/
-#define  CAN_FM1R_FBM                        0x0FFFFFFFU        /*!<Filter Mode */
-#define  CAN_FM1R_FBM0                       0x00000001U        /*!<Filter Init Mode bit 0 */
-#define  CAN_FM1R_FBM1                       0x00000002U        /*!<Filter Init Mode bit 1 */
-#define  CAN_FM1R_FBM2                       0x00000004U        /*!<Filter Init Mode bit 2 */
-#define  CAN_FM1R_FBM3                       0x00000008U        /*!<Filter Init Mode bit 3 */
-#define  CAN_FM1R_FBM4                       0x00000010U        /*!<Filter Init Mode bit 4 */
-#define  CAN_FM1R_FBM5                       0x00000020U        /*!<Filter Init Mode bit 5 */
-#define  CAN_FM1R_FBM6                       0x00000040U        /*!<Filter Init Mode bit 6 */
-#define  CAN_FM1R_FBM7                       0x00000080U        /*!<Filter Init Mode bit 7 */
-#define  CAN_FM1R_FBM8                       0x00000100U        /*!<Filter Init Mode bit 8 */
-#define  CAN_FM1R_FBM9                       0x00000200U        /*!<Filter Init Mode bit 9 */
-#define  CAN_FM1R_FBM10                      0x00000400U        /*!<Filter Init Mode bit 10 */
-#define  CAN_FM1R_FBM11                      0x00000800U        /*!<Filter Init Mode bit 11 */
-#define  CAN_FM1R_FBM12                      0x00001000U        /*!<Filter Init Mode bit 12 */
-#define  CAN_FM1R_FBM13                      0x00002000U        /*!<Filter Init Mode bit 13 */
-#define  CAN_FM1R_FBM14                      0x00004000U        /*!<Filter Init Mode bit 14 */
-#define  CAN_FM1R_FBM15                      0x00008000U        /*!<Filter Init Mode bit 15 */
-#define  CAN_FM1R_FBM16                      0x00010000U        /*!<Filter Init Mode bit 16 */
-#define  CAN_FM1R_FBM17                      0x00020000U        /*!<Filter Init Mode bit 17 */
-#define  CAN_FM1R_FBM18                      0x00040000U        /*!<Filter Init Mode bit 18 */
-#define  CAN_FM1R_FBM19                      0x00080000U        /*!<Filter Init Mode bit 19 */
-#define  CAN_FM1R_FBM20                      0x00100000U        /*!<Filter Init Mode bit 20 */
-#define  CAN_FM1R_FBM21                      0x00200000U        /*!<Filter Init Mode bit 21 */
-#define  CAN_FM1R_FBM22                      0x00400000U        /*!<Filter Init Mode bit 22 */
-#define  CAN_FM1R_FBM23                      0x00800000U        /*!<Filter Init Mode bit 23 */
-#define  CAN_FM1R_FBM24                      0x01000000U        /*!<Filter Init Mode bit 24 */
-#define  CAN_FM1R_FBM25                      0x02000000U        /*!<Filter Init Mode bit 25 */
-#define  CAN_FM1R_FBM26                      0x04000000U        /*!<Filter Init Mode bit 26 */
-#define  CAN_FM1R_FBM27                      0x08000000U        /*!<Filter Init Mode bit 27 */
-
-/*******************  Bit definition for CAN_FS1R register  *******************/
-#define  CAN_FS1R_FSC                        0x0FFFFFFFU        /*!<Filter Scale Configuration */
-#define  CAN_FS1R_FSC0                       0x00000001U        /*!<Filter Scale Configuration bit 0 */
-#define  CAN_FS1R_FSC1                       0x00000002U        /*!<Filter Scale Configuration bit 1 */
-#define  CAN_FS1R_FSC2                       0x00000004U        /*!<Filter Scale Configuration bit 2 */
-#define  CAN_FS1R_FSC3                       0x00000008U        /*!<Filter Scale Configuration bit 3 */
-#define  CAN_FS1R_FSC4                       0x00000010U        /*!<Filter Scale Configuration bit 4 */
-#define  CAN_FS1R_FSC5                       0x00000020U        /*!<Filter Scale Configuration bit 5 */
-#define  CAN_FS1R_FSC6                       0x00000040U        /*!<Filter Scale Configuration bit 6 */
-#define  CAN_FS1R_FSC7                       0x00000080U        /*!<Filter Scale Configuration bit 7 */
-#define  CAN_FS1R_FSC8                       0x00000100U        /*!<Filter Scale Configuration bit 8 */
-#define  CAN_FS1R_FSC9                       0x00000200U        /*!<Filter Scale Configuration bit 9 */
-#define  CAN_FS1R_FSC10                      0x00000400U        /*!<Filter Scale Configuration bit 10 */
-#define  CAN_FS1R_FSC11                      0x00000800U        /*!<Filter Scale Configuration bit 11 */
-#define  CAN_FS1R_FSC12                      0x00001000U        /*!<Filter Scale Configuration bit 12 */
-#define  CAN_FS1R_FSC13                      0x00002000U        /*!<Filter Scale Configuration bit 13 */
-#define  CAN_FS1R_FSC14                      0x00004000U        /*!<Filter Scale Configuration bit 14 */
-#define  CAN_FS1R_FSC15                      0x00008000U        /*!<Filter Scale Configuration bit 15 */
-#define  CAN_FS1R_FSC16                      0x00010000U        /*!<Filter Scale Configuration bit 16 */
-#define  CAN_FS1R_FSC17                      0x00020000U        /*!<Filter Scale Configuration bit 17 */
-#define  CAN_FS1R_FSC18                      0x00040000U        /*!<Filter Scale Configuration bit 18 */
-#define  CAN_FS1R_FSC19                      0x00080000U        /*!<Filter Scale Configuration bit 19 */
-#define  CAN_FS1R_FSC20                      0x00100000U        /*!<Filter Scale Configuration bit 20 */
-#define  CAN_FS1R_FSC21                      0x00200000U        /*!<Filter Scale Configuration bit 21 */
-#define  CAN_FS1R_FSC22                      0x00400000U        /*!<Filter Scale Configuration bit 22 */
-#define  CAN_FS1R_FSC23                      0x00800000U        /*!<Filter Scale Configuration bit 23 */
-#define  CAN_FS1R_FSC24                      0x01000000U        /*!<Filter Scale Configuration bit 24 */
-#define  CAN_FS1R_FSC25                      0x02000000U        /*!<Filter Scale Configuration bit 25 */
-#define  CAN_FS1R_FSC26                      0x04000000U        /*!<Filter Scale Configuration bit 26 */
-#define  CAN_FS1R_FSC27                      0x08000000U        /*!<Filter Scale Configuration bit 27 */
-
-/******************  Bit definition for CAN_FFA1R register  *******************/
-#define  CAN_FFA1R_FFA                        0x0FFFFFFFU        /*!<Filter FIFO Assignment */
-#define  CAN_FFA1R_FFA0                       0x00000001U        /*!<Filter FIFO Assignment bit 0 */
-#define  CAN_FFA1R_FFA1                       0x00000002U        /*!<Filter FIFO Assignment bit 1 */
-#define  CAN_FFA1R_FFA2                       0x00000004U        /*!<Filter FIFO Assignment bit 2 */
-#define  CAN_FFA1R_FFA3                       0x00000008U        /*!<Filter FIFO Assignment bit 3 */
-#define  CAN_FFA1R_FFA4                       0x00000010U        /*!<Filter FIFO Assignment bit 4 */
-#define  CAN_FFA1R_FFA5                       0x00000020U        /*!<Filter FIFO Assignment bit 5 */
-#define  CAN_FFA1R_FFA6                       0x00000040U        /*!<Filter FIFO Assignment bit 6 */
-#define  CAN_FFA1R_FFA7                       0x00000080U        /*!<Filter FIFO Assignment bit 7 */
-#define  CAN_FFA1R_FFA8                       0x00000100U        /*!<Filter FIFO Assignment bit 8 */
-#define  CAN_FFA1R_FFA9                       0x00000200U        /*!<Filter FIFO Assignment bit 9 */
-#define  CAN_FFA1R_FFA10                      0x00000400U        /*!<Filter FIFO Assignment bit 10 */
-#define  CAN_FFA1R_FFA11                      0x00000800U        /*!<Filter FIFO Assignment bit 11 */
-#define  CAN_FFA1R_FFA12                      0x00001000U        /*!<Filter FIFO Assignment bit 12 */
-#define  CAN_FFA1R_FFA13                      0x00002000U        /*!<Filter FIFO Assignment bit 13 */
-#define  CAN_FFA1R_FFA14                      0x00004000U        /*!<Filter FIFO Assignment bit 14 */
-#define  CAN_FFA1R_FFA15                      0x00008000U        /*!<Filter FIFO Assignment bit 15 */
-#define  CAN_FFA1R_FFA16                      0x00010000U        /*!<Filter FIFO Assignment bit 16 */
-#define  CAN_FFA1R_FFA17                      0x00020000U        /*!<Filter FIFO Assignment bit 17 */
-#define  CAN_FFA1R_FFA18                      0x00040000U        /*!<Filter FIFO Assignment bit 18 */
-#define  CAN_FFA1R_FFA19                      0x00080000U        /*!<Filter FIFO Assignment bit 19 */
-#define  CAN_FFA1R_FFA20                      0x00100000U        /*!<Filter FIFO Assignment bit 20 */
-#define  CAN_FFA1R_FFA21                      0x00200000U        /*!<Filter FIFO Assignment bit 21 */
-#define  CAN_FFA1R_FFA22                      0x00400000U        /*!<Filter FIFO Assignment bit 22 */
-#define  CAN_FFA1R_FFA23                      0x00800000U        /*!<Filter FIFO Assignment bit 23 */
-#define  CAN_FFA1R_FFA24                      0x01000000U        /*!<Filter FIFO Assignment bit 24 */
-#define  CAN_FFA1R_FFA25                      0x02000000U        /*!<Filter FIFO Assignment bit 25 */
-#define  CAN_FFA1R_FFA26                      0x04000000U        /*!<Filter FIFO Assignment bit 26 */
-#define  CAN_FFA1R_FFA27                      0x08000000U        /*!<Filter FIFO Assignment bit 27 */
-
-/*******************  Bit definition for CAN_FA1R register  *******************/
-#define  CAN_FA1R_FACT                        0x0FFFFFFFU        /*!<Filter Active */
-#define  CAN_FA1R_FACT0                       0x00000001U        /*!<Filter Active bit 0 */
-#define  CAN_FA1R_FACT1                       0x00000002U        /*!<Filter Active bit 1 */
-#define  CAN_FA1R_FACT2                       0x00000004U        /*!<Filter Active bit 2 */
-#define  CAN_FA1R_FACT3                       0x00000008U        /*!<Filter Active bit 3 */
-#define  CAN_FA1R_FACT4                       0x00000010U        /*!<Filter Active bit 4 */
-#define  CAN_FA1R_FACT5                       0x00000020U        /*!<Filter Active bit 5 */
-#define  CAN_FA1R_FACT6                       0x00000040U        /*!<Filter Active bit 6 */
-#define  CAN_FA1R_FACT7                       0x00000080U        /*!<Filter Active bit 7 */
-#define  CAN_FA1R_FACT8                       0x00000100U        /*!<Filter Active bit 8 */
-#define  CAN_FA1R_FACT9                       0x00000200U        /*!<Filter Active bit 9 */
-#define  CAN_FA1R_FACT10                      0x00000400U        /*!<Filter Active bit 10 */
-#define  CAN_FA1R_FACT11                      0x00000800U        /*!<Filter Active bit 11 */
-#define  CAN_FA1R_FACT12                      0x00001000U        /*!<Filter Active bit 12 */
-#define  CAN_FA1R_FACT13                      0x00002000U        /*!<Filter Active bit 13 */
-#define  CAN_FA1R_FACT14                      0x00004000U        /*!<Filter Active bit 14 */
-#define  CAN_FA1R_FACT15                      0x00008000U        /*!<Filter Active bit 15 */
-#define  CAN_FA1R_FACT16                      0x00010000U        /*!<Filter Active bit 16 */
-#define  CAN_FA1R_FACT17                      0x00020000U        /*!<Filter Active bit 17 */
-#define  CAN_FA1R_FACT18                      0x00040000U        /*!<Filter Active bit 18 */
-#define  CAN_FA1R_FACT19                      0x00080000U        /*!<Filter Active bit 19 */
-#define  CAN_FA1R_FACT20                      0x00100000U        /*!<Filter Active bit 20 */
-#define  CAN_FA1R_FACT21                      0x00200000U        /*!<Filter Active bit 21 */
-#define  CAN_FA1R_FACT22                      0x00400000U        /*!<Filter Active bit 22 */
-#define  CAN_FA1R_FACT23                      0x00800000U        /*!<Filter Active bit 23 */
-#define  CAN_FA1R_FACT24                      0x01000000U        /*!<Filter Active bit 24 */
-#define  CAN_FA1R_FACT25                      0x02000000U        /*!<Filter Active bit 25 */
-#define  CAN_FA1R_FACT26                      0x04000000U        /*!<Filter Active bit 26 */
-#define  CAN_FA1R_FACT27                      0x08000000U        /*!<Filter Active bit 27 */
-
-/*******************  Bit definition for CAN_F0R1 register  *******************/
-#define  CAN_F0R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F0R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F0R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F0R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F0R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F0R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F0R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F0R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F0R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F0R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F0R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F0R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F0R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F0R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F0R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F0R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F0R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F0R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F0R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F0R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F0R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F0R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F0R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F0R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F0R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F0R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F0R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F0R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F0R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F0R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F0R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F0R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R1 register  *******************/
-#define  CAN_F1R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F1R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F1R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F1R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F1R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F1R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F1R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F1R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F1R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F1R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F1R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F1R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F1R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F1R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F1R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F1R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F1R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F1R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F1R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F1R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F1R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F1R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F1R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F1R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F1R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F1R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F1R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F1R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F1R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F1R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F1R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F1R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R1 register  *******************/
-#define  CAN_F2R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F2R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F2R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F2R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F2R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F2R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F2R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F2R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F2R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F2R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F2R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F2R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F2R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F2R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F2R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F2R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F2R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F2R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F2R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F2R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F2R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F2R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F2R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F2R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F2R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F2R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F2R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F2R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F2R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F2R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F2R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F2R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R1 register  *******************/
-#define  CAN_F3R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F3R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F3R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F3R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F3R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F3R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F3R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F3R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F3R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F3R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F3R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F3R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F3R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F3R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F3R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F3R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F3R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F3R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F3R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F3R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F3R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F3R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F3R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F3R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F3R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F3R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F3R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F3R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F3R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F3R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F3R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F3R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R1 register  *******************/
-#define  CAN_F4R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F4R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F4R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F4R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F4R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F4R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F4R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F4R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F4R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F4R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F4R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F4R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F4R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F4R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F4R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F4R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F4R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F4R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F4R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F4R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F4R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F4R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F4R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F4R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F4R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F4R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F4R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F4R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F4R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F4R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F4R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F4R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R1 register  *******************/
-#define  CAN_F5R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F5R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F5R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F5R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F5R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F5R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F5R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F5R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F5R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F5R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F5R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F5R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F5R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F5R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F5R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F5R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F5R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F5R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F5R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F5R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F5R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F5R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F5R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F5R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F5R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F5R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F5R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F5R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F5R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F5R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F5R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F5R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R1 register  *******************/
-#define  CAN_F6R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F6R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F6R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F6R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F6R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F6R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F6R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F6R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F6R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F6R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F6R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F6R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F6R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F6R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F6R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F6R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F6R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F6R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F6R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F6R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F6R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F6R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F6R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F6R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F6R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F6R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F6R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F6R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F6R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F6R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F6R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F6R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R1 register  *******************/
-#define  CAN_F7R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F7R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F7R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F7R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F7R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F7R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F7R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F7R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F7R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F7R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F7R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F7R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F7R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F7R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F7R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F7R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F7R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F7R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F7R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F7R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F7R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F7R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F7R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F7R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F7R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F7R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F7R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F7R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F7R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F7R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F7R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F7R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R1 register  *******************/
-#define  CAN_F8R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F8R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F8R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F8R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F8R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F8R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F8R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F8R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F8R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F8R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F8R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F8R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F8R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F8R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F8R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F8R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F8R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F8R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F8R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F8R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F8R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F8R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F8R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F8R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F8R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F8R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F8R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F8R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F8R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F8R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F8R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F8R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R1 register  *******************/
-#define  CAN_F9R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F9R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F9R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F9R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F9R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F9R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F9R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F9R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F9R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F9R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F9R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F9R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F9R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F9R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F9R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F9R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F9R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F9R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F9R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F9R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F9R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F9R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F9R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F9R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F9R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F9R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F9R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F9R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F9R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F9R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F9R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F9R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R1 register  ******************/
-#define  CAN_F10R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F10R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F10R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F10R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F10R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F10R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F10R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F10R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F10R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F10R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F10R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F10R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F10R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F10R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F10R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F10R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F10R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F10R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F10R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F10R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F10R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F10R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F10R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F10R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F10R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F10R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F10R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F10R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F10R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F10R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F10R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F10R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R1 register  ******************/
-#define  CAN_F11R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F11R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F11R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F11R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F11R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F11R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F11R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F11R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F11R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F11R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F11R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F11R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F11R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F11R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F11R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F11R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F11R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F11R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F11R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F11R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F11R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F11R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F11R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F11R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F11R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F11R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F11R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F11R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F11R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F11R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F11R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F11R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R1 register  ******************/
-#define  CAN_F12R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F12R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F12R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F12R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F12R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F12R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F12R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F12R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F12R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F12R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F12R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F12R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F12R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F12R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F12R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F12R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F12R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F12R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F12R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F12R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F12R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F12R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F12R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F12R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F12R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F12R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F12R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F12R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F12R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F12R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F12R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F12R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R1 register  ******************/
-#define  CAN_F13R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F13R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F13R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F13R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F13R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F13R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F13R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F13R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F13R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F13R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F13R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F13R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F13R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F13R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F13R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F13R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F13R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F13R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F13R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F13R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F13R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F13R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F13R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F13R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F13R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F13R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F13R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F13R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F13R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F13R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F13R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F13R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F0R2 register  *******************/
-#define  CAN_F0R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F0R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F0R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F0R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F0R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F0R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F0R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F0R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F0R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F0R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F0R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F0R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F0R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F0R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F0R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F0R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F0R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F0R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F0R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F0R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F0R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F0R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F0R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F0R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F0R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F0R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F0R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F0R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F0R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F0R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F0R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F0R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R2 register  *******************/
-#define  CAN_F1R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F1R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F1R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F1R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F1R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F1R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F1R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F1R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F1R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F1R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F1R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F1R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F1R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F1R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F1R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F1R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F1R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F1R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F1R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F1R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F1R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F1R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F1R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F1R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F1R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F1R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F1R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F1R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F1R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F1R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F1R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F1R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R2 register  *******************/
-#define  CAN_F2R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F2R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F2R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F2R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F2R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F2R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F2R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F2R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F2R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F2R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F2R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F2R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F2R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F2R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F2R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F2R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F2R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F2R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F2R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F2R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F2R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F2R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F2R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F2R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F2R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F2R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F2R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F2R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F2R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F2R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F2R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F2R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R2 register  *******************/
-#define  CAN_F3R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F3R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F3R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F3R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F3R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F3R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F3R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F3R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F3R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F3R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F3R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F3R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F3R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F3R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F3R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F3R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F3R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F3R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F3R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F3R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F3R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F3R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F3R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F3R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F3R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F3R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F3R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F3R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F3R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F3R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F3R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F3R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R2 register  *******************/
-#define  CAN_F4R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F4R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F4R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F4R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F4R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F4R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F4R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F4R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F4R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F4R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F4R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F4R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F4R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F4R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F4R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F4R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F4R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F4R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F4R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F4R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F4R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F4R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F4R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F4R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F4R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F4R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F4R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F4R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F4R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F4R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F4R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F4R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R2 register  *******************/
-#define  CAN_F5R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F5R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F5R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F5R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F5R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F5R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F5R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F5R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F5R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F5R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F5R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F5R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F5R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F5R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F5R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F5R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F5R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F5R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F5R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F5R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F5R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F5R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F5R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F5R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F5R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F5R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F5R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F5R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F5R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F5R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F5R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F5R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R2 register  *******************/
-#define  CAN_F6R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F6R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F6R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F6R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F6R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F6R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F6R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F6R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F6R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F6R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F6R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F6R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F6R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F6R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F6R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F6R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F6R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F6R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F6R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F6R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F6R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F6R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F6R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F6R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F6R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F6R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F6R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F6R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F6R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F6R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F6R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F6R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R2 register  *******************/
-#define  CAN_F7R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F7R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F7R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F7R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F7R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F7R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F7R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F7R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F7R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F7R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F7R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F7R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F7R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F7R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F7R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F7R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F7R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F7R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F7R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F7R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F7R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F7R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F7R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F7R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F7R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F7R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F7R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F7R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F7R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F7R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F7R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F7R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R2 register  *******************/
-#define  CAN_F8R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F8R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F8R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F8R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F8R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F8R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F8R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F8R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F8R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F8R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F8R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F8R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F8R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F8R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F8R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F8R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F8R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F8R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F8R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F8R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F8R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F8R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F8R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F8R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F8R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F8R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F8R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F8R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F8R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F8R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F8R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F8R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R2 register  *******************/
-#define  CAN_F9R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F9R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F9R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F9R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F9R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F9R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F9R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F9R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F9R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F9R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F9R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F9R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F9R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F9R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F9R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F9R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F9R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F9R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F9R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F9R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F9R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F9R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F9R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F9R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F9R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F9R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F9R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F9R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F9R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F9R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F9R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F9R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R2 register  ******************/
-#define  CAN_F10R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F10R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F10R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F10R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F10R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F10R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F10R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F10R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F10R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F10R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F10R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F10R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F10R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F10R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F10R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F10R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F10R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F10R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F10R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F10R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F10R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F10R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F10R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F10R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F10R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F10R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F10R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F10R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F10R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F10R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F10R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F10R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R2 register  ******************/
-#define  CAN_F11R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F11R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F11R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F11R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F11R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F11R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F11R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F11R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F11R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F11R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F11R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F11R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F11R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F11R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F11R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F11R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F11R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F11R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F11R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F11R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F11R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F11R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F11R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F11R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F11R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F11R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F11R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F11R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F11R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F11R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F11R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F11R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R2 register  ******************/
-#define  CAN_F12R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F12R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F12R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F12R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F12R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F12R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F12R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F12R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F12R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F12R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F12R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F12R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F12R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F12R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F12R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F12R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F12R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F12R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F12R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F12R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F12R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F12R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F12R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F12R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F12R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F12R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F12R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F12R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F12R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F12R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F12R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F12R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R2 register  ******************/
-#define  CAN_F13R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F13R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F13R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F13R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F13R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F13R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F13R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F13R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F13R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F13R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F13R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F13R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F13R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F13R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F13R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F13R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F13R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F13R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F13R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F13R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F13R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F13R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F13R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F13R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F13R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F13R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F13R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F13R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F13R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F13R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F13R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F13R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRC calculation unit                              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           0xFFFFFFFFU /*!< Data register bits */
-
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         0xFFU        /*!< General-purpose 8-bit data register bits */
-
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        0x01U        /*!< RESET bit */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Digital to Analog Converter                           */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DAC_CR register  ********************/
-#define  DAC_CR_EN1                          0x00000001U        /*!<DAC channel1 enable */
-#define  DAC_CR_BOFF1                        0x00000002U        /*!<DAC channel1 output buffer disable */
-#define  DAC_CR_TEN1                         0x00000004U        /*!<DAC channel1 Trigger enable */
-
-#define  DAC_CR_TSEL1                        0x00000038U        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define  DAC_CR_TSEL1_0                      0x00000008U        /*!<Bit 0 */
-#define  DAC_CR_TSEL1_1                      0x00000010U        /*!<Bit 1 */
-#define  DAC_CR_TSEL1_2                      0x00000020U        /*!<Bit 2 */
-
-#define  DAC_CR_WAVE1                        0x000000C0U        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE1_0                      0x00000040U        /*!<Bit 0 */
-#define  DAC_CR_WAVE1_1                      0x00000080U        /*!<Bit 1 */
-
-#define  DAC_CR_MAMP1                        0x00000F00U        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP1_0                      0x00000100U        /*!<Bit 0 */
-#define  DAC_CR_MAMP1_1                      0x00000200U        /*!<Bit 1 */
-#define  DAC_CR_MAMP1_2                      0x00000400U        /*!<Bit 2 */
-#define  DAC_CR_MAMP1_3                      0x00000800U        /*!<Bit 3 */
-
-#define  DAC_CR_DMAEN1                       0x00001000U        /*!<DAC channel1 DMA enable */
-#define  DAC_CR_DMAUDRIE1                    0x00002000U        /*!<DAC channel1 DMA underrun interrupt enable*/
-#define  DAC_CR_EN2                          0x00010000U        /*!<DAC channel2 enable */
-#define  DAC_CR_BOFF2                        0x00020000U        /*!<DAC channel2 output buffer disable */
-#define  DAC_CR_TEN2                         0x00040000U        /*!<DAC channel2 Trigger enable */
-
-#define  DAC_CR_TSEL2                        0x00380000U        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define  DAC_CR_TSEL2_0                      0x00080000U        /*!<Bit 0 */
-#define  DAC_CR_TSEL2_1                      0x00100000U        /*!<Bit 1 */
-#define  DAC_CR_TSEL2_2                      0x00200000U        /*!<Bit 2 */
-
-#define  DAC_CR_WAVE2                        0x00C00000U        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE2_0                      0x00400000U        /*!<Bit 0 */
-#define  DAC_CR_WAVE2_1                      0x00800000U        /*!<Bit 1 */
-
-#define  DAC_CR_MAMP2                        0x0F000000U        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP2_0                      0x01000000U        /*!<Bit 0 */
-#define  DAC_CR_MAMP2_1                      0x02000000U        /*!<Bit 1 */
-#define  DAC_CR_MAMP2_2                      0x04000000U        /*!<Bit 2 */
-#define  DAC_CR_MAMP2_3                      0x08000000U        /*!<Bit 3 */
-
-#define  DAC_CR_DMAEN2                       0x10000000U        /*!<DAC channel2 DMA enabled */
-#define  DAC_CR_DMAUDRIE2                    0x20000000U        /*!<DAC channel2 DMA underrun interrupt enable*/
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define  DAC_SWTRIGR_SWTRIG1                 0x01U               /*!<DAC channel1 software trigger */
-#define  DAC_SWTRIGR_SWTRIG2                 0x02U               /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define  DAC_DHR12R1_DACC1DHR                0x0FFFU            /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define  DAC_DHR12L1_DACC1DHR                0xFFF0U            /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define  DAC_DHR8R1_DACC1DHR                 0xFFU               /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define  DAC_DHR12R2_DACC2DHR                0x0FFFU            /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define  DAC_DHR12L2_DACC2DHR                0xFFF0U            /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define  DAC_DHR8R2_DACC2DHR                 0xFFU               /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define  DAC_DHR12RD_DACC1DHR                0x00000FFFU        /*!<DAC channel1 12-bit Right aligned data */
-#define  DAC_DHR12RD_DACC2DHR                0x0FFF0000U        /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define  DAC_DHR12LD_DACC1DHR                0x0000FFF0U        /*!<DAC channel1 12-bit Left aligned data */
-#define  DAC_DHR12LD_DACC2DHR                0xFFF00000U        /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define  DAC_DHR8RD_DACC1DHR                 0x00FFU            /*!<DAC channel1 8-bit Right aligned data */
-#define  DAC_DHR8RD_DACC2DHR                 0xFF00U            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define  DAC_DOR1_DACC1DOR                   0x0FFFU            /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define  DAC_DOR2_DACC2DOR                   0x0FFFU            /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define  DAC_SR_DMAUDR1                      0x00002000U        /*!<DAC channel1 DMA underrun flag */
-#define  DAC_SR_DMAUDR2                      0x20000000U        /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 Debug MCU                                  */
-/*                                                                            */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    DCMI                                    */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DCMI_CR register  ******************/
-#define DCMI_CR_CAPTURE                      0x00000001U
-#define DCMI_CR_CM                           0x00000002U
-#define DCMI_CR_CROP                         0x00000004U
-#define DCMI_CR_JPEG                         0x00000008U
-#define DCMI_CR_ESS                          0x00000010U
-#define DCMI_CR_PCKPOL                       0x00000020U
-#define DCMI_CR_HSPOL                        0x00000040U
-#define DCMI_CR_VSPOL                        0x00000080U
-#define DCMI_CR_FCRC_0                       0x00000100U
-#define DCMI_CR_FCRC_1                       0x00000200U
-#define DCMI_CR_EDM_0                        0x00000400U
-#define DCMI_CR_EDM_1                        0x00000800U
-#define DCMI_CR_CRE                          0x00001000U
-#define DCMI_CR_ENABLE                       0x00004000U
-
-/********************  Bits definition for DCMI_SR register  ******************/
-#define DCMI_SR_HSYNC                        0x00000001U
-#define DCMI_SR_VSYNC                        0x00000002U
-#define DCMI_SR_FNE                          0x00000004U
-
-/********************  Bits definition for DCMI_RIS register  *****************/
-#define DCMI_RIS_FRAME_RIS                   0x00000001U
-#define DCMI_RIS_OVR_RIS                     0x00000002U
-#define DCMI_RIS_ERR_RIS                     0x00000004U
-#define DCMI_RIS_VSYNC_RIS                   0x00000008U
-#define DCMI_RIS_LINE_RIS                    0x00000010U
-/* Legacy defines */
-#define DCMI_RISR_FRAME_RIS                  DCMI_RIS_FRAME_RIS
-#define DCMI_RISR_OVR_RIS                    DCMI_RIS_OVR_RIS
-#define DCMI_RISR_ERR_RIS                    DCMI_RIS_ERR_RIS
-#define DCMI_RISR_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS
-#define DCMI_RISR_LINE_RIS                   DCMI_RIS_LINE_RIS
-#define DCMI_RISR_OVF_RIS                    DCMI_RIS_OVR_RIS
-
-/********************  Bits definition for DCMI_IER register  *****************/
-#define DCMI_IER_FRAME_IE                    0x00000001U
-#define DCMI_IER_OVR_IE                      0x00000002U
-#define DCMI_IER_ERR_IE                      0x00000004U
-#define DCMI_IER_VSYNC_IE                    0x00000008U
-#define DCMI_IER_LINE_IE                     0x00000010U
-/* Legacy defines */
-#define DCMI_IER_OVF_IE                      DCMI_IER_OVR_IE
-
-/********************  Bits definition for DCMI_MIS register  *****************/
-#define DCMI_MIS_FRAME_MIS                   0x00000001U
-#define DCMI_MIS_OVR_MIS                     0x00000002U
-#define DCMI_MIS_ERR_MIS                     0x00000004U
-#define DCMI_MIS_VSYNC_MIS                   0x00000008U
-#define DCMI_MIS_LINE_MIS                    0x00000010U
-
-/* Legacy defines */
-#define DCMI_MISR_FRAME_MIS                  DCMI_MIS_FRAME_MIS
-#define DCMI_MISR_OVF_MIS                    DCMI_MIS_OVR_MIS
-#define DCMI_MISR_ERR_MIS                    DCMI_MIS_ERR_MIS
-#define DCMI_MISR_VSYNC_MIS                  DCMI_MIS_VSYNC_MIS
-#define DCMI_MISR_LINE_MIS                   DCMI_MIS_LINE_MIS
-
-/********************  Bits definition for DCMI_ICR register  *****************/
-#define DCMI_ICR_FRAME_ISC                   0x00000001U
-#define DCMI_ICR_OVR_ISC                     0x00000002U
-#define DCMI_ICR_ERR_ISC                     0x00000004U
-#define DCMI_ICR_VSYNC_ISC                   0x00000008U
-#define DCMI_ICR_LINE_ISC                    0x00000010U
-
-/* Legacy defines */
-#define DCMI_ICR_OVF_ISC                     DCMI_ICR_OVR_ISC
-
-/********************  Bits definition for DCMI_ESCR register  ******************/
-#define DCMI_ESCR_FSC                        0x000000FFU
-#define DCMI_ESCR_LSC                        0x0000FF00U
-#define DCMI_ESCR_LEC                        0x00FF0000U
-#define DCMI_ESCR_FEC                        0xFF000000U
-
-/********************  Bits definition for DCMI_ESUR register  ******************/
-#define DCMI_ESUR_FSU                        0x000000FFU
-#define DCMI_ESUR_LSU                        0x0000FF00U
-#define DCMI_ESUR_LEU                        0x00FF0000U
-#define DCMI_ESUR_FEU                        0xFF000000U
-
-/********************  Bits definition for DCMI_CWSTRT register  ******************/
-#define DCMI_CWSTRT_HOFFCNT                  0x00003FFFU
-#define DCMI_CWSTRT_VST                      0x1FFF0000U
-
-/********************  Bits definition for DCMI_CWSIZE register  ******************/
-#define DCMI_CWSIZE_CAPCNT                   0x00003FFFU
-#define DCMI_CWSIZE_VLINE                    0x3FFF0000U
-
-/********************  Bits definition for DCMI_DR register  ******************/
-#define DCMI_DR_BYTE0                        0x000000FFU
-#define DCMI_DR_BYTE1                        0x0000FF00U
-#define DCMI_DR_BYTE2                        0x00FF0000U
-#define DCMI_DR_BYTE3                        0xFF000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                             DMA Controller                                 */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DMA_SxCR register  *****************/
-#define DMA_SxCR_CHSEL                       0x0E000000U
-#define DMA_SxCR_CHSEL_0                     0x02000000U
-#define DMA_SxCR_CHSEL_1                     0x04000000U
-#define DMA_SxCR_CHSEL_2                     0x08000000U
-#define DMA_SxCR_MBURST                      0x01800000U
-#define DMA_SxCR_MBURST_0                    0x00800000U
-#define DMA_SxCR_MBURST_1                    0x01000000U
-#define DMA_SxCR_PBURST                      0x00600000U
-#define DMA_SxCR_PBURST_0                    0x00200000U
-#define DMA_SxCR_PBURST_1                    0x00400000U
-#define DMA_SxCR_CT                          0x00080000U
-#define DMA_SxCR_DBM                         0x00040000U
-#define DMA_SxCR_PL                          0x00030000U
-#define DMA_SxCR_PL_0                        0x00010000U
-#define DMA_SxCR_PL_1                        0x00020000U
-#define DMA_SxCR_PINCOS                      0x00008000U
-#define DMA_SxCR_MSIZE                       0x00006000U
-#define DMA_SxCR_MSIZE_0                     0x00002000U
-#define DMA_SxCR_MSIZE_1                     0x00004000U
-#define DMA_SxCR_PSIZE                       0x00001800U
-#define DMA_SxCR_PSIZE_0                     0x00000800U
-#define DMA_SxCR_PSIZE_1                     0x00001000U
-#define DMA_SxCR_MINC                        0x00000400U
-#define DMA_SxCR_PINC                        0x00000200U
-#define DMA_SxCR_CIRC                        0x00000100U
-#define DMA_SxCR_DIR                         0x000000C0U
-#define DMA_SxCR_DIR_0                       0x00000040U
-#define DMA_SxCR_DIR_1                       0x00000080U
-#define DMA_SxCR_PFCTRL                      0x00000020U
-#define DMA_SxCR_TCIE                        0x00000010U
-#define DMA_SxCR_HTIE                        0x00000008U
-#define DMA_SxCR_TEIE                        0x00000004U
-#define DMA_SxCR_DMEIE                       0x00000002U
-#define DMA_SxCR_EN                          0x00000001U
-
-/* Legacy defines */
-#define DMA_SxCR_ACK                         0x00100000U
-
-/********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            0x0000FFFFU
-#define DMA_SxNDT_0                          0x00000001U
-#define DMA_SxNDT_1                          0x00000002U
-#define DMA_SxNDT_2                          0x00000004U
-#define DMA_SxNDT_3                          0x00000008U
-#define DMA_SxNDT_4                          0x00000010U
-#define DMA_SxNDT_5                          0x00000020U
-#define DMA_SxNDT_6                          0x00000040U
-#define DMA_SxNDT_7                          0x00000080U
-#define DMA_SxNDT_8                          0x00000100U
-#define DMA_SxNDT_9                          0x00000200U
-#define DMA_SxNDT_10                         0x00000400U
-#define DMA_SxNDT_11                         0x00000800U
-#define DMA_SxNDT_12                         0x00001000U
-#define DMA_SxNDT_13                         0x00002000U
-#define DMA_SxNDT_14                         0x00004000U
-#define DMA_SxNDT_15                         0x00008000U
-
-/********************  Bits definition for DMA_SxFCR register  ****************/ 
-#define DMA_SxFCR_FEIE                       0x00000080U
-#define DMA_SxFCR_FS                         0x00000038U
-#define DMA_SxFCR_FS_0                       0x00000008U
-#define DMA_SxFCR_FS_1                       0x00000010U
-#define DMA_SxFCR_FS_2                       0x00000020U
-#define DMA_SxFCR_DMDIS                      0x00000004U
-#define DMA_SxFCR_FTH                        0x00000003U
-#define DMA_SxFCR_FTH_0                      0x00000001U
-#define DMA_SxFCR_FTH_1                      0x00000002U
-
-/********************  Bits definition for DMA_LISR register  *****************/ 
-#define DMA_LISR_TCIF3                       0x08000000U
-#define DMA_LISR_HTIF3                       0x04000000U
-#define DMA_LISR_TEIF3                       0x02000000U
-#define DMA_LISR_DMEIF3                      0x01000000U
-#define DMA_LISR_FEIF3                       0x00400000U
-#define DMA_LISR_TCIF2                       0x00200000U
-#define DMA_LISR_HTIF2                       0x00100000U
-#define DMA_LISR_TEIF2                       0x00080000U
-#define DMA_LISR_DMEIF2                      0x00040000U
-#define DMA_LISR_FEIF2                       0x00010000U
-#define DMA_LISR_TCIF1                       0x00000800U
-#define DMA_LISR_HTIF1                       0x00000400U
-#define DMA_LISR_TEIF1                       0x00000200U
-#define DMA_LISR_DMEIF1                      0x00000100U
-#define DMA_LISR_FEIF1                       0x00000040U
-#define DMA_LISR_TCIF0                       0x00000020U
-#define DMA_LISR_HTIF0                       0x00000010U
-#define DMA_LISR_TEIF0                       0x00000008U
-#define DMA_LISR_DMEIF0                      0x00000004U
-#define DMA_LISR_FEIF0                       0x00000001U
-
-/********************  Bits definition for DMA_HISR register  *****************/ 
-#define DMA_HISR_TCIF7                       0x08000000U
-#define DMA_HISR_HTIF7                       0x04000000U
-#define DMA_HISR_TEIF7                       0x02000000U
-#define DMA_HISR_DMEIF7                      0x01000000U
-#define DMA_HISR_FEIF7                       0x00400000U
-#define DMA_HISR_TCIF6                       0x00200000U
-#define DMA_HISR_HTIF6                       0x00100000U
-#define DMA_HISR_TEIF6                       0x00080000U
-#define DMA_HISR_DMEIF6                      0x00040000U
-#define DMA_HISR_FEIF6                       0x00010000U
-#define DMA_HISR_TCIF5                       0x00000800U
-#define DMA_HISR_HTIF5                       0x00000400U
-#define DMA_HISR_TEIF5                       0x00000200U
-#define DMA_HISR_DMEIF5                      0x00000100U
-#define DMA_HISR_FEIF5                       0x00000040U
-#define DMA_HISR_TCIF4                       0x00000020U
-#define DMA_HISR_HTIF4                       0x00000010U
-#define DMA_HISR_TEIF4                       0x00000008U
-#define DMA_HISR_DMEIF4                      0x00000004U
-#define DMA_HISR_FEIF4                       0x00000001U
-
-/********************  Bits definition for DMA_LIFCR register  ****************/ 
-#define DMA_LIFCR_CTCIF3                     0x08000000U
-#define DMA_LIFCR_CHTIF3                     0x04000000U
-#define DMA_LIFCR_CTEIF3                     0x02000000U
-#define DMA_LIFCR_CDMEIF3                    0x01000000U
-#define DMA_LIFCR_CFEIF3                     0x00400000U
-#define DMA_LIFCR_CTCIF2                     0x00200000U
-#define DMA_LIFCR_CHTIF2                     0x00100000U
-#define DMA_LIFCR_CTEIF2                     0x00080000U
-#define DMA_LIFCR_CDMEIF2                    0x00040000U
-#define DMA_LIFCR_CFEIF2                     0x00010000U
-#define DMA_LIFCR_CTCIF1                     0x00000800U
-#define DMA_LIFCR_CHTIF1                     0x00000400U
-#define DMA_LIFCR_CTEIF1                     0x00000200U
-#define DMA_LIFCR_CDMEIF1                    0x00000100U
-#define DMA_LIFCR_CFEIF1                     0x00000040U
-#define DMA_LIFCR_CTCIF0                     0x00000020U
-#define DMA_LIFCR_CHTIF0                     0x00000010U
-#define DMA_LIFCR_CTEIF0                     0x00000008U
-#define DMA_LIFCR_CDMEIF0                    0x00000004U
-#define DMA_LIFCR_CFEIF0                     0x00000001U
-
-/********************  Bits definition for DMA_HIFCR  register  ****************/ 
-#define DMA_HIFCR_CTCIF7                     0x08000000U
-#define DMA_HIFCR_CHTIF7                     0x04000000U
-#define DMA_HIFCR_CTEIF7                     0x02000000U
-#define DMA_HIFCR_CDMEIF7                    0x01000000U
-#define DMA_HIFCR_CFEIF7                     0x00400000U
-#define DMA_HIFCR_CTCIF6                     0x00200000U
-#define DMA_HIFCR_CHTIF6                     0x00100000U
-#define DMA_HIFCR_CTEIF6                     0x00080000U
-#define DMA_HIFCR_CDMEIF6                    0x00040000U
-#define DMA_HIFCR_CFEIF6                     0x00010000U
-#define DMA_HIFCR_CTCIF5                     0x00000800U
-#define DMA_HIFCR_CHTIF5                     0x00000400U
-#define DMA_HIFCR_CTEIF5                     0x00000200U
-#define DMA_HIFCR_CDMEIF5                    0x00000100U
-#define DMA_HIFCR_CFEIF5                     0x00000040U
-#define DMA_HIFCR_CTCIF4                     0x00000020U
-#define DMA_HIFCR_CHTIF4                     0x00000010U
-#define DMA_HIFCR_CTEIF4                     0x00000008U
-#define DMA_HIFCR_CDMEIF4                    0x00000004U
-#define DMA_HIFCR_CFEIF4                     0x00000001U
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                    External Interrupt/Event Controller                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    FLASH                                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    0x0000000FU
-#define FLASH_ACR_LATENCY_0WS                0x00000000U
-#define FLASH_ACR_LATENCY_1WS                0x00000001U
-#define FLASH_ACR_LATENCY_2WS                0x00000002U
-#define FLASH_ACR_LATENCY_3WS                0x00000003U
-#define FLASH_ACR_LATENCY_4WS                0x00000004U
-#define FLASH_ACR_LATENCY_5WS                0x00000005U
-#define FLASH_ACR_LATENCY_6WS                0x00000006U
-#define FLASH_ACR_LATENCY_7WS                0x00000007U
-
-#define FLASH_ACR_PRFTEN                     0x00000100U
-#define FLASH_ACR_ICEN                       0x00000200U
-#define FLASH_ACR_DCEN                       0x00000400U
-#define FLASH_ACR_ICRST                      0x00000800U
-#define FLASH_ACR_DCRST                      0x00001000U
-#define FLASH_ACR_BYTE0_ADDRESS              0x40023C00U
-#define FLASH_ACR_BYTE2_ADDRESS              0x40023C03U
-
-/*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         0x00000001U
-#define FLASH_SR_SOP                         0x00000002U
-#define FLASH_SR_WRPERR                      0x00000010U
-#define FLASH_SR_PGAERR                      0x00000020U
-#define FLASH_SR_PGPERR                      0x00000040U
-#define FLASH_SR_PGSERR                      0x00000080U
-#define FLASH_SR_BSY                         0x00010000U
-
-/*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          0x00000001U
-#define FLASH_CR_SER                         0x00000002U
-#define FLASH_CR_MER                         0x00000004U
-#define FLASH_CR_SNB                         0x000000F8U
-#define FLASH_CR_SNB_0                       0x00000008U
-#define FLASH_CR_SNB_1                       0x00000010U
-#define FLASH_CR_SNB_2                       0x00000020U
-#define FLASH_CR_SNB_3                       0x00000040U
-#define FLASH_CR_SNB_4                       0x00000080U
-#define FLASH_CR_PSIZE                       0x00000300U
-#define FLASH_CR_PSIZE_0                     0x00000100U
-#define FLASH_CR_PSIZE_1                     0x00000200U
-#define FLASH_CR_STRT                        0x00010000U
-#define FLASH_CR_EOPIE                       0x01000000U
-#define FLASH_CR_LOCK                        0x80000000U
-
-/*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                 0x00000001U
-#define FLASH_OPTCR_OPTSTRT                 0x00000002U
-#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
-#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
-#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
-
-#define FLASH_OPTCR_WDG_SW                  0x00000020U
-#define FLASH_OPTCR_nRST_STOP               0x00000040U
-#define FLASH_OPTCR_nRST_STDBY              0x00000080U
-#define FLASH_OPTCR_RDP                     0x0000FF00U
-#define FLASH_OPTCR_RDP_0                   0x00000100U
-#define FLASH_OPTCR_RDP_1                   0x00000200U
-#define FLASH_OPTCR_RDP_2                   0x00000400U
-#define FLASH_OPTCR_RDP_3                   0x00000800U
-#define FLASH_OPTCR_RDP_4                   0x00001000U
-#define FLASH_OPTCR_RDP_5                   0x00002000U
-#define FLASH_OPTCR_RDP_6                   0x00004000U
-#define FLASH_OPTCR_RDP_7                   0x00008000U
-#define FLASH_OPTCR_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR_nWRP_0                  0x00010000U
-#define FLASH_OPTCR_nWRP_1                  0x00020000U
-#define FLASH_OPTCR_nWRP_2                  0x00040000U
-#define FLASH_OPTCR_nWRP_3                  0x00080000U
-#define FLASH_OPTCR_nWRP_4                  0x00100000U
-#define FLASH_OPTCR_nWRP_5                  0x00200000U
-#define FLASH_OPTCR_nWRP_6                  0x00400000U
-#define FLASH_OPTCR_nWRP_7                  0x00800000U
-#define FLASH_OPTCR_nWRP_8                  0x01000000U
-#define FLASH_OPTCR_nWRP_9                  0x02000000U
-#define FLASH_OPTCR_nWRP_10                 0x04000000U
-#define FLASH_OPTCR_nWRP_11                 0x08000000U
-                                             
-/******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR1_nWRP_0                  0x00010000U
-#define FLASH_OPTCR1_nWRP_1                  0x00020000U
-#define FLASH_OPTCR1_nWRP_2                  0x00040000U
-#define FLASH_OPTCR1_nWRP_3                  0x00080000U
-#define FLASH_OPTCR1_nWRP_4                  0x00100000U
-#define FLASH_OPTCR1_nWRP_5                  0x00200000U
-#define FLASH_OPTCR1_nWRP_6                  0x00400000U
-#define FLASH_OPTCR1_nWRP_7                  0x00800000U
-#define FLASH_OPTCR1_nWRP_8                  0x01000000U
-#define FLASH_OPTCR1_nWRP_9                  0x02000000U
-#define FLASH_OPTCR1_nWRP_10                 0x04000000U
-#define FLASH_OPTCR1_nWRP_11                 0x08000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Flexible Static Memory Controller                    */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for FSMC_BCR1 register  *******************/
-#define  FSMC_BCR1_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FSMC_BCR1_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FSMC_BCR1_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FSMC_BCR1_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FSMC_BCR1_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FSMC_BCR1_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR1_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FSMC_BCR1_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FSMC_BCR1_FACCEN                    0x00000040U        /*!<Flash access enable                    */
-#define  FSMC_BCR1_BURSTEN                   0x00000100U        /*!<Burst enable bit                       */
-#define  FSMC_BCR1_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit               */
-#define  FSMC_BCR1_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support             */
-#define  FSMC_BCR1_WAITCFG                   0x00000800U        /*!<Wait timing configuration              */
-#define  FSMC_BCR1_WREN                      0x00001000U        /*!<Write enable bit                       */
-#define  FSMC_BCR1_WAITEN                    0x00002000U        /*!<Wait enable bit                        */
-#define  FSMC_BCR1_EXTMOD                    0x00004000U        /*!<Extended mode enable                   */
-#define  FSMC_BCR1_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait                      */
-#define  FSMC_BCR1_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FSMC_BCR1_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FSMC_BCR1_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FSMC_BCR1_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FSMC_BCR1_CBURSTRW                  0x00080000U        /*!<Write burst enable                     */
-
-/******************  Bit definition for FSMC_BCR2 register  *******************/
-#define  FSMC_BCR2_MBKEN                     0x00000001U        /*!<Memory bank enable bit                */
-#define  FSMC_BCR2_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FSMC_BCR2_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FSMC_BCR2_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FSMC_BCR2_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FSMC_BCR2_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR2_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FSMC_BCR2_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FSMC_BCR2_FACCEN                    0x00000040U        /*!<Flash access enable                    */
-#define  FSMC_BCR2_BURSTEN                   0x00000100U        /*!<Burst enable bit                       */
-#define  FSMC_BCR2_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit               */
-#define  FSMC_BCR2_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support             */
-#define  FSMC_BCR2_WAITCFG                   0x00000800U        /*!<Wait timing configuration              */
-#define  FSMC_BCR2_WREN                      0x00001000U        /*!<Write enable bit                       */
-#define  FSMC_BCR2_WAITEN                    0x00002000U        /*!<Wait enable bit                        */
-#define  FSMC_BCR2_EXTMOD                    0x00004000U        /*!<Extended mode enable                   */
-#define  FSMC_BCR2_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait                      */
-#define  FSMC_BCR2_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FSMC_BCR2_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FSMC_BCR2_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FSMC_BCR2_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FSMC_BCR2_CBURSTRW                  0x00080000U        /*!<Write burst enable                     */
-
-/******************  Bit definition for FSMC_BCR3 register  *******************/
-#define  FSMC_BCR3_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FSMC_BCR3_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FSMC_BCR3_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FSMC_BCR3_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FSMC_BCR3_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FSMC_BCR3_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR3_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FSMC_BCR3_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FSMC_BCR3_FACCEN                    0x00000040U        /*!<Flash access enable                    */
-#define  FSMC_BCR3_BURSTEN                   0x00000100U        /*!<Burst enable bit                       */
-#define  FSMC_BCR3_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit               */
-#define  FSMC_BCR3_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support             */
-#define  FSMC_BCR3_WAITCFG                   0x00000800U        /*!<Wait timing configuration              */
-#define  FSMC_BCR3_WREN                      0x00001000U        /*!<Write enable bit                       */
-#define  FSMC_BCR3_WAITEN                    0x00002000U        /*!<Wait enable bit                        */
-#define  FSMC_BCR3_EXTMOD                    0x00004000U        /*!<Extended mode enable                   */
-#define  FSMC_BCR3_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait                      */
-#define  FSMC_BCR3_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FSMC_BCR3_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FSMC_BCR3_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FSMC_BCR3_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FSMC_BCR3_CBURSTRW                  0x00080000U        /*!<Write burst enable                     */
-
-/******************  Bit definition for FSMC_BCR4 register  *******************/
-#define  FSMC_BCR4_MBKEN                     0x00000001U        /*!<Memory bank enable bit */
-#define  FSMC_BCR4_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FSMC_BCR4_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FSMC_BCR4_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FSMC_BCR4_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FSMC_BCR4_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR4_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FSMC_BCR4_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FSMC_BCR4_FACCEN                    0x00000040U        /*!<Flash access enable                    */
-#define  FSMC_BCR4_BURSTEN                   0x00000100U        /*!<Burst enable bit                       */
-#define  FSMC_BCR4_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit               */
-#define  FSMC_BCR4_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support             */
-#define  FSMC_BCR4_WAITCFG                   0x00000800U        /*!<Wait timing configuration              */
-#define  FSMC_BCR4_WREN                      0x00001000U        /*!<Write enable bit                       */
-#define  FSMC_BCR4_WAITEN                    0x00002000U        /*!<Wait enable bit                        */
-#define  FSMC_BCR4_EXTMOD                    0x00004000U        /*!<Extended mode enable                   */
-#define  FSMC_BCR4_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait                      */
-#define  FSMC_BCR4_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FSMC_BCR4_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FSMC_BCR4_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FSMC_BCR4_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FSMC_BCR4_CBURSTRW                  0x00080000U        /*!<Write burst enable                     */
-
-/******************  Bit definition for FSMC_BTR1 register  ******************/
-#define  FSMC_BTR1_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR1_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FSMC_BTR1_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FSMC_BTR1_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FSMC_BTR1_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BTR1_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR1_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FSMC_BTR1_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FSMC_BTR1_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FSMC_BTR1_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BTR1_DATAST                    0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */
-#define  FSMC_BTR1_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FSMC_BTR1_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FSMC_BTR1_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FSMC_BTR1_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FSMC_BTR1_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FSMC_BTR1_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FSMC_BTR1_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FSMC_BTR1_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BTR1_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR1_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FSMC_BTR1_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FSMC_BTR1_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FSMC_BTR1_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BTR1_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR1_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FSMC_BTR1_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FSMC_BTR1_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FSMC_BTR1_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FSMC_BTR1_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR1_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FSMC_BTR1_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FSMC_BTR1_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FSMC_BTR1_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FSMC_BTR1_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR1_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FSMC_BTR1_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BTR2 register  *******************/
-#define  FSMC_BTR2_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR2_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FSMC_BTR2_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FSMC_BTR2_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FSMC_BTR2_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BTR2_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR2_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FSMC_BTR2_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FSMC_BTR2_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FSMC_BTR2_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BTR2_DATAST                    0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */
-#define  FSMC_BTR2_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FSMC_BTR2_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FSMC_BTR2_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FSMC_BTR2_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FSMC_BTR2_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FSMC_BTR2_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FSMC_BTR2_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FSMC_BTR2_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BTR2_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR2_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FSMC_BTR2_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FSMC_BTR2_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FSMC_BTR2_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BTR2_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR2_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FSMC_BTR2_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FSMC_BTR2_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FSMC_BTR2_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FSMC_BTR2_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR2_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FSMC_BTR2_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FSMC_BTR2_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FSMC_BTR2_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FSMC_BTR2_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR2_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FSMC_BTR2_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/*******************  Bit definition for FSMC_BTR3 register  *******************/
-#define  FSMC_BTR3_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR3_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FSMC_BTR3_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FSMC_BTR3_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FSMC_BTR3_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BTR3_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR3_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FSMC_BTR3_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FSMC_BTR3_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FSMC_BTR3_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BTR3_DATAST                    0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */
-#define  FSMC_BTR3_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FSMC_BTR3_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FSMC_BTR3_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FSMC_BTR3_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FSMC_BTR3_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FSMC_BTR3_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FSMC_BTR3_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FSMC_BTR3_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BTR3_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR3_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FSMC_BTR3_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FSMC_BTR3_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FSMC_BTR3_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BTR3_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR3_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FSMC_BTR3_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FSMC_BTR3_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FSMC_BTR3_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FSMC_BTR3_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR3_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FSMC_BTR3_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FSMC_BTR3_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FSMC_BTR3_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FSMC_BTR3_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR3_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FSMC_BTR3_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BTR4 register  *******************/
-#define  FSMC_BTR4_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR4_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FSMC_BTR4_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FSMC_BTR4_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FSMC_BTR4_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BTR4_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR4_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FSMC_BTR4_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FSMC_BTR4_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FSMC_BTR4_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BTR4_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BTR4_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FSMC_BTR4_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FSMC_BTR4_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FSMC_BTR4_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FSMC_BTR4_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FSMC_BTR4_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FSMC_BTR4_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FSMC_BTR4_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BTR4_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR4_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FSMC_BTR4_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FSMC_BTR4_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FSMC_BTR4_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BTR4_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR4_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FSMC_BTR4_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FSMC_BTR4_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FSMC_BTR4_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FSMC_BTR4_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR4_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FSMC_BTR4_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FSMC_BTR4_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FSMC_BTR4_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FSMC_BTR4_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR4_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FSMC_BTR4_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR1 register  ******************/
-#define  FSMC_BWTR1_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR1_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FSMC_BWTR1_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FSMC_BWTR1_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FSMC_BWTR1_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BWTR1_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR1_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FSMC_BWTR1_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FSMC_BWTR1_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FSMC_BWTR1_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BWTR1_DATAST                   0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */
-#define  FSMC_BWTR1_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FSMC_BWTR1_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FSMC_BWTR1_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FSMC_BWTR1_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FSMC_BWTR1_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FSMC_BWTR1_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FSMC_BWTR1_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FSMC_BWTR1_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BWTR1_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FSMC_BWTR1_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FSMC_BWTR1_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FSMC_BWTR1_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FSMC_BWTR1_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BWTR1_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR1_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FSMC_BWTR1_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR2 register  ******************/
-#define  FSMC_BWTR2_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR2_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FSMC_BWTR2_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FSMC_BWTR2_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FSMC_BWTR2_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BWTR2_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR2_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FSMC_BWTR2_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FSMC_BWTR2_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FSMC_BWTR2_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BWTR2_DATAST                   0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */
-#define  FSMC_BWTR2_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FSMC_BWTR2_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FSMC_BWTR2_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FSMC_BWTR2_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FSMC_BWTR2_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FSMC_BWTR2_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FSMC_BWTR2_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FSMC_BWTR2_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BWTR2_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FSMC_BWTR2_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FSMC_BWTR2_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FSMC_BWTR2_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FSMC_BWTR2_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BWTR2_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR2_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FSMC_BWTR2_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR3 register  ******************/
-#define  FSMC_BWTR3_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR3_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FSMC_BWTR3_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FSMC_BWTR3_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FSMC_BWTR3_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BWTR3_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR3_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FSMC_BWTR3_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FSMC_BWTR3_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FSMC_BWTR3_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BWTR3_DATAST                   0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */
-#define  FSMC_BWTR3_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FSMC_BWTR3_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FSMC_BWTR3_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FSMC_BWTR3_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FSMC_BWTR3_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FSMC_BWTR3_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FSMC_BWTR3_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FSMC_BWTR3_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BWTR3_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FSMC_BWTR3_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FSMC_BWTR3_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FSMC_BWTR3_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FSMC_BWTR3_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BWTR3_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR3_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FSMC_BWTR3_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR4 register  ******************/
-#define  FSMC_BWTR4_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR4_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FSMC_BWTR4_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FSMC_BWTR4_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FSMC_BWTR4_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BWTR4_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR4_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FSMC_BWTR4_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FSMC_BWTR4_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FSMC_BWTR4_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BWTR4_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BWTR4_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FSMC_BWTR4_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FSMC_BWTR4_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FSMC_BWTR4_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FSMC_BWTR4_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FSMC_BWTR4_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FSMC_BWTR4_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FSMC_BWTR4_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BWTR4_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FSMC_BWTR4_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FSMC_BWTR4_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FSMC_BWTR4_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FSMC_BWTR4_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BWTR4_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR4_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FSMC_BWTR4_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_PCR2 register  *******************/
-#define  FSMC_PCR2_PWAITEN                   0x00000002U        /*!<Wait feature enable bit */
-#define  FSMC_PCR2_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FSMC_PCR2_PTYP                      0x00000008U        /*!<Memory type */
-
-#define  FSMC_PCR2_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FSMC_PCR2_PWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FSMC_PCR2_PWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FSMC_PCR2_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit */
-
-#define  FSMC_PCR2_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay) */
-#define  FSMC_PCR2_TCLR_0                    0x00000200U        /*!<Bit 0 */
-#define  FSMC_PCR2_TCLR_1                    0x00000400U        /*!<Bit 1 */
-#define  FSMC_PCR2_TCLR_2                    0x00000800U        /*!<Bit 2 */
-#define  FSMC_PCR2_TCLR_3                    0x00001000U        /*!<Bit 3 */
-
-#define  FSMC_PCR2_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay) */
-#define  FSMC_PCR2_TAR_0                     0x00002000U        /*!<Bit 0 */
-#define  FSMC_PCR2_TAR_1                     0x00004000U        /*!<Bit 1 */
-#define  FSMC_PCR2_TAR_2                     0x00008000U        /*!<Bit 2 */
-#define  FSMC_PCR2_TAR_3                     0x00010000U        /*!<Bit 3 */
-
-#define  FSMC_PCR2_ECCPS                     0x000E0000U        /*!<ECCPS[1:0] bits (ECC page size) */
-#define  FSMC_PCR2_ECCPS_0                   0x00020000U        /*!<Bit 0 */
-#define  FSMC_PCR2_ECCPS_1                   0x00040000U        /*!<Bit 1 */
-#define  FSMC_PCR2_ECCPS_2                   0x00080000U        /*!<Bit 2 */
-
-/******************  Bit definition for FSMC_PCR3 register  *******************/
-#define  FSMC_PCR3_PWAITEN                   0x00000002U        /*!<Wait feature enable bit */
-#define  FSMC_PCR3_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FSMC_PCR3_PTYP                      0x00000008U        /*!<Memory type */
-
-#define  FSMC_PCR3_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FSMC_PCR3_PWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FSMC_PCR3_PWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FSMC_PCR3_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit */
-
-#define  FSMC_PCR3_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay) */
-#define  FSMC_PCR3_TCLR_0                    0x00000200U        /*!<Bit 0 */
-#define  FSMC_PCR3_TCLR_1                    0x00000400U        /*!<Bit 1 */
-#define  FSMC_PCR3_TCLR_2                    0x00000800U        /*!<Bit 2 */
-#define  FSMC_PCR3_TCLR_3                    0x00001000U        /*!<Bit 3 */
-
-#define  FSMC_PCR3_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay) */
-#define  FSMC_PCR3_TAR_0                     0x00002000U        /*!<Bit 0 */
-#define  FSMC_PCR3_TAR_1                     0x00004000U        /*!<Bit 1 */
-#define  FSMC_PCR3_TAR_2                     0x00008000U        /*!<Bit 2 */
-#define  FSMC_PCR3_TAR_3                     0x00010000U        /*!<Bit 3 */
-
-#define  FSMC_PCR3_ECCPS                     0x000E0000U        /*!<ECCPS[2:0] bits (ECC page size) */
-#define  FSMC_PCR3_ECCPS_0                   0x00020000U        /*!<Bit 0 */
-#define  FSMC_PCR3_ECCPS_1                   0x00040000U        /*!<Bit 1 */
-#define  FSMC_PCR3_ECCPS_2                   0x00080000U        /*!<Bit 2 */
-
-/******************  Bit definition for FSMC_PCR4 register  *******************/
-#define  FSMC_PCR4_PWAITEN                   0x00000002U        /*!<Wait feature enable bit */
-#define  FSMC_PCR4_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FSMC_PCR4_PTYP                      0x00000008U        /*!<Memory type */
-
-#define  FSMC_PCR4_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FSMC_PCR4_PWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FSMC_PCR4_PWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FSMC_PCR4_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit */
-
-#define  FSMC_PCR4_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay) */
-#define  FSMC_PCR4_TCLR_0                    0x00000200U        /*!<Bit 0 */
-#define  FSMC_PCR4_TCLR_1                    0x00000400U        /*!<Bit 1 */
-#define  FSMC_PCR4_TCLR_2                    0x00000800U        /*!<Bit 2 */
-#define  FSMC_PCR4_TCLR_3                    0x00001000U        /*!<Bit 3 */
-
-#define  FSMC_PCR4_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay) */
-#define  FSMC_PCR4_TAR_0                     0x00002000U        /*!<Bit 0 */
-#define  FSMC_PCR4_TAR_1                     0x00004000U        /*!<Bit 1 */
-#define  FSMC_PCR4_TAR_2                     0x00008000U        /*!<Bit 2 */
-#define  FSMC_PCR4_TAR_3                     0x00010000U        /*!<Bit 3 */
-
-#define  FSMC_PCR4_ECCPS                     0x000E0000U        /*!<ECCPS[2:0] bits (ECC page size) */
-#define  FSMC_PCR4_ECCPS_0                   0x00020000U        /*!<Bit 0 */
-#define  FSMC_PCR4_ECCPS_1                   0x00040000U        /*!<Bit 1 */
-#define  FSMC_PCR4_ECCPS_2                   0x00080000U        /*!<Bit 2 */
-
-/*******************  Bit definition for FSMC_SR2 register  *******************/
-#define  FSMC_SR2_IRS                        0x01U               /*!<Interrupt Rising Edge status                */
-#define  FSMC_SR2_ILS                        0x02U               /*!<Interrupt Level status                      */
-#define  FSMC_SR2_IFS                        0x04U               /*!<Interrupt Falling Edge status               */
-#define  FSMC_SR2_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FSMC_SR2_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit        */
-#define  FSMC_SR2_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FSMC_SR2_FEMPT                      0x40U               /*!<FIFO empty */
-
-/*******************  Bit definition for FSMC_SR3 register  *******************/
-#define  FSMC_SR3_IRS                        0x01U               /*!<Interrupt Rising Edge status                */
-#define  FSMC_SR3_ILS                        0x02U               /*!<Interrupt Level status                      */
-#define  FSMC_SR3_IFS                        0x04U               /*!<Interrupt Falling Edge status               */
-#define  FSMC_SR3_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FSMC_SR3_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit        */
-#define  FSMC_SR3_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FSMC_SR3_FEMPT                      0x40U               /*!<FIFO empty */
-
-/*******************  Bit definition for FSMC_SR4 register  *******************/
-#define  FSMC_SR4_IRS                        0x01U               /*!<Interrupt Rising Edge status                 */
-#define  FSMC_SR4_ILS                        0x02U               /*!<Interrupt Level status                       */
-#define  FSMC_SR4_IFS                        0x04U               /*!<Interrupt Falling Edge status                */
-#define  FSMC_SR4_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit   */
-#define  FSMC_SR4_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit         */
-#define  FSMC_SR4_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit  */
-#define  FSMC_SR4_FEMPT                      0x40U               /*!<FIFO empty */
-
-/******************  Bit definition for FSMC_PMEM2 register  ******************/
-#define  FSMC_PMEM2_MEMSET2                  0x000000FFU        /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
-#define  FSMC_PMEM2_MEMSET2_0                0x00000001U        /*!<Bit 0 */
-#define  FSMC_PMEM2_MEMSET2_1                0x00000002U        /*!<Bit 1 */
-#define  FSMC_PMEM2_MEMSET2_2                0x00000004U        /*!<Bit 2 */
-#define  FSMC_PMEM2_MEMSET2_3                0x00000008U        /*!<Bit 3 */
-#define  FSMC_PMEM2_MEMSET2_4                0x00000010U        /*!<Bit 4 */
-#define  FSMC_PMEM2_MEMSET2_5                0x00000020U        /*!<Bit 5 */
-#define  FSMC_PMEM2_MEMSET2_6                0x00000040U        /*!<Bit 6 */
-#define  FSMC_PMEM2_MEMSET2_7                0x00000080U        /*!<Bit 7 */
-
-#define  FSMC_PMEM2_MEMWAIT2                 0x0000FF00U        /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
-#define  FSMC_PMEM2_MEMWAIT2_0               0x00000100U        /*!<Bit 0 */
-#define  FSMC_PMEM2_MEMWAIT2_1               0x00000200U        /*!<Bit 1 */
-#define  FSMC_PMEM2_MEMWAIT2_2               0x00000400U        /*!<Bit 2 */
-#define  FSMC_PMEM2_MEMWAIT2_3               0x00000800U        /*!<Bit 3 */
-#define  FSMC_PMEM2_MEMWAIT2_4               0x00001000U        /*!<Bit 4 */
-#define  FSMC_PMEM2_MEMWAIT2_5               0x00002000U        /*!<Bit 5 */
-#define  FSMC_PMEM2_MEMWAIT2_6               0x00004000U        /*!<Bit 6 */
-#define  FSMC_PMEM2_MEMWAIT2_7               0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_PMEM2_MEMHOLD2                 0x00FF0000U        /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
-#define  FSMC_PMEM2_MEMHOLD2_0               0x00010000U        /*!<Bit 0 */
-#define  FSMC_PMEM2_MEMHOLD2_1               0x00020000U        /*!<Bit 1 */
-#define  FSMC_PMEM2_MEMHOLD2_2               0x00040000U        /*!<Bit 2 */
-#define  FSMC_PMEM2_MEMHOLD2_3               0x00080000U        /*!<Bit 3 */
-#define  FSMC_PMEM2_MEMHOLD2_4               0x00100000U        /*!<Bit 4 */
-#define  FSMC_PMEM2_MEMHOLD2_5               0x00200000U        /*!<Bit 5 */
-#define  FSMC_PMEM2_MEMHOLD2_6               0x00400000U        /*!<Bit 6 */
-#define  FSMC_PMEM2_MEMHOLD2_7               0x00800000U        /*!<Bit 7 */
-
-#define  FSMC_PMEM2_MEMHIZ2                  0xFF000000U        /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
-#define  FSMC_PMEM2_MEMHIZ2_0                0x01000000U        /*!<Bit 0 */
-#define  FSMC_PMEM2_MEMHIZ2_1                0x02000000U        /*!<Bit 1 */
-#define  FSMC_PMEM2_MEMHIZ2_2                0x04000000U        /*!<Bit 2 */
-#define  FSMC_PMEM2_MEMHIZ2_3                0x08000000U        /*!<Bit 3 */
-#define  FSMC_PMEM2_MEMHIZ2_4                0x10000000U        /*!<Bit 4 */
-#define  FSMC_PMEM2_MEMHIZ2_5                0x20000000U        /*!<Bit 5 */
-#define  FSMC_PMEM2_MEMHIZ2_6                0x40000000U        /*!<Bit 6 */
-#define  FSMC_PMEM2_MEMHIZ2_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FSMC_PMEM3 register  ******************/
-#define  FSMC_PMEM3_MEMSET3                  0x000000FFU        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
-#define  FSMC_PMEM3_MEMSET3_0                0x00000001U        /*!<Bit 0 */
-#define  FSMC_PMEM3_MEMSET3_1                0x00000002U        /*!<Bit 1 */
-#define  FSMC_PMEM3_MEMSET3_2                0x00000004U        /*!<Bit 2 */
-#define  FSMC_PMEM3_MEMSET3_3                0x00000008U        /*!<Bit 3 */
-#define  FSMC_PMEM3_MEMSET3_4                0x00000010U        /*!<Bit 4 */
-#define  FSMC_PMEM3_MEMSET3_5                0x00000020U        /*!<Bit 5 */
-#define  FSMC_PMEM3_MEMSET3_6                0x00000040U        /*!<Bit 6 */
-#define  FSMC_PMEM3_MEMSET3_7                0x00000080U        /*!<Bit 7 */
-
-#define  FSMC_PMEM3_MEMWAIT3                 0x0000FF00U        /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
-#define  FSMC_PMEM3_MEMWAIT3_0               0x00000100U        /*!<Bit 0 */
-#define  FSMC_PMEM3_MEMWAIT3_1               0x00000200U        /*!<Bit 1 */
-#define  FSMC_PMEM3_MEMWAIT3_2               0x00000400U        /*!<Bit 2 */
-#define  FSMC_PMEM3_MEMWAIT3_3               0x00000800U        /*!<Bit 3 */
-#define  FSMC_PMEM3_MEMWAIT3_4               0x00001000U        /*!<Bit 4 */
-#define  FSMC_PMEM3_MEMWAIT3_5               0x00002000U        /*!<Bit 5 */
-#define  FSMC_PMEM3_MEMWAIT3_6               0x00004000U        /*!<Bit 6 */
-#define  FSMC_PMEM3_MEMWAIT3_7               0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_PMEM3_MEMHOLD3                 0x00FF0000U        /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
-#define  FSMC_PMEM3_MEMHOLD3_0               0x00010000U        /*!<Bit 0 */
-#define  FSMC_PMEM3_MEMHOLD3_1               0x00020000U        /*!<Bit 1 */
-#define  FSMC_PMEM3_MEMHOLD3_2               0x00040000U        /*!<Bit 2 */
-#define  FSMC_PMEM3_MEMHOLD3_3               0x00080000U        /*!<Bit 3 */
-#define  FSMC_PMEM3_MEMHOLD3_4               0x00100000U        /*!<Bit 4 */
-#define  FSMC_PMEM3_MEMHOLD3_5               0x00200000U        /*!<Bit 5 */
-#define  FSMC_PMEM3_MEMHOLD3_6               0x00400000U        /*!<Bit 6 */
-#define  FSMC_PMEM3_MEMHOLD3_7               0x00800000U        /*!<Bit 7 */
-
-#define  FSMC_PMEM3_MEMHIZ3                  0xFF000000U        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
-#define  FSMC_PMEM3_MEMHIZ3_0                0x01000000U        /*!<Bit 0 */
-#define  FSMC_PMEM3_MEMHIZ3_1                0x02000000U        /*!<Bit 1 */
-#define  FSMC_PMEM3_MEMHIZ3_2                0x04000000U        /*!<Bit 2 */
-#define  FSMC_PMEM3_MEMHIZ3_3                0x08000000U        /*!<Bit 3 */
-#define  FSMC_PMEM3_MEMHIZ3_4                0x10000000U        /*!<Bit 4 */
-#define  FSMC_PMEM3_MEMHIZ3_5                0x20000000U        /*!<Bit 5 */
-#define  FSMC_PMEM3_MEMHIZ3_6                0x40000000U        /*!<Bit 6 */
-#define  FSMC_PMEM3_MEMHIZ3_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FSMC_PMEM4 register  ******************/
-#define  FSMC_PMEM4_MEMSET4                  0x000000FFU        /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
-#define  FSMC_PMEM4_MEMSET4_0                0x00000001U        /*!<Bit 0 */
-#define  FSMC_PMEM4_MEMSET4_1                0x00000002U        /*!<Bit 1 */
-#define  FSMC_PMEM4_MEMSET4_2                0x00000004U        /*!<Bit 2 */
-#define  FSMC_PMEM4_MEMSET4_3                0x00000008U        /*!<Bit 3 */
-#define  FSMC_PMEM4_MEMSET4_4                0x00000010U        /*!<Bit 4 */
-#define  FSMC_PMEM4_MEMSET4_5                0x00000020U        /*!<Bit 5 */
-#define  FSMC_PMEM4_MEMSET4_6                0x00000040U        /*!<Bit 6 */
-#define  FSMC_PMEM4_MEMSET4_7                0x00000080U        /*!<Bit 7 */
-
-#define  FSMC_PMEM4_MEMWAIT4                 0x0000FF00U        /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
-#define  FSMC_PMEM4_MEMWAIT4_0               0x00000100U        /*!<Bit 0 */
-#define  FSMC_PMEM4_MEMWAIT4_1               0x00000200U        /*!<Bit 1 */
-#define  FSMC_PMEM4_MEMWAIT4_2               0x00000400U        /*!<Bit 2 */
-#define  FSMC_PMEM4_MEMWAIT4_3               0x00000800U        /*!<Bit 3 */
-#define  FSMC_PMEM4_MEMWAIT4_4               0x00001000U        /*!<Bit 4 */
-#define  FSMC_PMEM4_MEMWAIT4_5               0x00002000U        /*!<Bit 5 */
-#define  FSMC_PMEM4_MEMWAIT4_6               0x00004000U        /*!<Bit 6 */
-#define  FSMC_PMEM4_MEMWAIT4_7               0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_PMEM4_MEMHOLD4                 0x00FF0000U        /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
-#define  FSMC_PMEM4_MEMHOLD4_0               0x00010000U        /*!<Bit 0 */
-#define  FSMC_PMEM4_MEMHOLD4_1               0x00020000U        /*!<Bit 1 */
-#define  FSMC_PMEM4_MEMHOLD4_2               0x00040000U        /*!<Bit 2 */
-#define  FSMC_PMEM4_MEMHOLD4_3               0x00080000U        /*!<Bit 3 */
-#define  FSMC_PMEM4_MEMHOLD4_4               0x00100000U        /*!<Bit 4 */
-#define  FSMC_PMEM4_MEMHOLD4_5               0x00200000U        /*!<Bit 5 */
-#define  FSMC_PMEM4_MEMHOLD4_6               0x00400000U        /*!<Bit 6 */
-#define  FSMC_PMEM4_MEMHOLD4_7               0x00800000U        /*!<Bit 7 */
-
-#define  FSMC_PMEM4_MEMHIZ4                  0xFF000000U        /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
-#define  FSMC_PMEM4_MEMHIZ4_0                0x01000000U        /*!<Bit 0 */
-#define  FSMC_PMEM4_MEMHIZ4_1                0x02000000U        /*!<Bit 1 */
-#define  FSMC_PMEM4_MEMHIZ4_2                0x04000000U        /*!<Bit 2 */
-#define  FSMC_PMEM4_MEMHIZ4_3                0x08000000U        /*!<Bit 3 */
-#define  FSMC_PMEM4_MEMHIZ4_4                0x10000000U        /*!<Bit 4 */
-#define  FSMC_PMEM4_MEMHIZ4_5                0x20000000U        /*!<Bit 5 */
-#define  FSMC_PMEM4_MEMHIZ4_6                0x40000000U        /*!<Bit 6 */
-#define  FSMC_PMEM4_MEMHIZ4_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FSMC_PATT2 register  ******************/
-#define  FSMC_PATT2_ATTSET2                  0x000000FFU        /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
-#define  FSMC_PATT2_ATTSET2_0                0x00000001U        /*!<Bit 0 */
-#define  FSMC_PATT2_ATTSET2_1                0x00000002U        /*!<Bit 1 */
-#define  FSMC_PATT2_ATTSET2_2                0x00000004U        /*!<Bit 2 */
-#define  FSMC_PATT2_ATTSET2_3                0x00000008U        /*!<Bit 3 */
-#define  FSMC_PATT2_ATTSET2_4                0x00000010U        /*!<Bit 4 */
-#define  FSMC_PATT2_ATTSET2_5                0x00000020U        /*!<Bit 5 */
-#define  FSMC_PATT2_ATTSET2_6                0x00000040U        /*!<Bit 6 */
-#define  FSMC_PATT2_ATTSET2_7                0x00000080U        /*!<Bit 7 */
-
-#define  FSMC_PATT2_ATTWAIT2                 0x0000FF00U        /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
-#define  FSMC_PATT2_ATTWAIT2_0               0x00000100U        /*!<Bit 0 */
-#define  FSMC_PATT2_ATTWAIT2_1               0x00000200U        /*!<Bit 1 */
-#define  FSMC_PATT2_ATTWAIT2_2               0x00000400U        /*!<Bit 2 */
-#define  FSMC_PATT2_ATTWAIT2_3               0x00000800U        /*!<Bit 3 */
-#define  FSMC_PATT2_ATTWAIT2_4               0x00001000U        /*!<Bit 4 */
-#define  FSMC_PATT2_ATTWAIT2_5               0x00002000U        /*!<Bit 5 */
-#define  FSMC_PATT2_ATTWAIT2_6               0x00004000U        /*!<Bit 6 */
-#define  FSMC_PATT2_ATTWAIT2_7               0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_PATT2_ATTHOLD2                 0x00FF0000U        /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
-#define  FSMC_PATT2_ATTHOLD2_0               0x00010000U        /*!<Bit 0 */
-#define  FSMC_PATT2_ATTHOLD2_1               0x00020000U        /*!<Bit 1 */
-#define  FSMC_PATT2_ATTHOLD2_2               0x00040000U        /*!<Bit 2 */
-#define  FSMC_PATT2_ATTHOLD2_3               0x00080000U        /*!<Bit 3 */
-#define  FSMC_PATT2_ATTHOLD2_4               0x00100000U        /*!<Bit 4 */
-#define  FSMC_PATT2_ATTHOLD2_5               0x00200000U        /*!<Bit 5 */
-#define  FSMC_PATT2_ATTHOLD2_6               0x00400000U        /*!<Bit 6 */
-#define  FSMC_PATT2_ATTHOLD2_7               0x00800000U        /*!<Bit 7 */
-
-#define  FSMC_PATT2_ATTHIZ2                  0xFF000000U        /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
-#define  FSMC_PATT2_ATTHIZ2_0                0x01000000U        /*!<Bit 0 */
-#define  FSMC_PATT2_ATTHIZ2_1                0x02000000U        /*!<Bit 1 */
-#define  FSMC_PATT2_ATTHIZ2_2                0x04000000U        /*!<Bit 2 */
-#define  FSMC_PATT2_ATTHIZ2_3                0x08000000U        /*!<Bit 3 */
-#define  FSMC_PATT2_ATTHIZ2_4                0x10000000U        /*!<Bit 4 */
-#define  FSMC_PATT2_ATTHIZ2_5                0x20000000U        /*!<Bit 5 */
-#define  FSMC_PATT2_ATTHIZ2_6                0x40000000U        /*!<Bit 6 */
-#define  FSMC_PATT2_ATTHIZ2_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FSMC_PATT3 register  ******************/
-#define  FSMC_PATT3_ATTSET3                  0x000000FFU        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
-#define  FSMC_PATT3_ATTSET3_0                0x00000001U        /*!<Bit 0 */
-#define  FSMC_PATT3_ATTSET3_1                0x00000002U        /*!<Bit 1 */
-#define  FSMC_PATT3_ATTSET3_2                0x00000004U        /*!<Bit 2 */
-#define  FSMC_PATT3_ATTSET3_3                0x00000008U        /*!<Bit 3 */
-#define  FSMC_PATT3_ATTSET3_4                0x00000010U        /*!<Bit 4 */
-#define  FSMC_PATT3_ATTSET3_5                0x00000020U        /*!<Bit 5 */
-#define  FSMC_PATT3_ATTSET3_6                0x00000040U        /*!<Bit 6 */
-#define  FSMC_PATT3_ATTSET3_7                0x00000080U        /*!<Bit 7 */
-
-#define  FSMC_PATT3_ATTWAIT3                 0x0000FF00U        /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
-#define  FSMC_PATT3_ATTWAIT3_0               0x00000100U        /*!<Bit 0 */
-#define  FSMC_PATT3_ATTWAIT3_1               0x00000200U        /*!<Bit 1 */
-#define  FSMC_PATT3_ATTWAIT3_2               0x00000400U        /*!<Bit 2 */
-#define  FSMC_PATT3_ATTWAIT3_3               0x00000800U        /*!<Bit 3 */
-#define  FSMC_PATT3_ATTWAIT3_4               0x00001000U        /*!<Bit 4 */
-#define  FSMC_PATT3_ATTWAIT3_5               0x00002000U        /*!<Bit 5 */
-#define  FSMC_PATT3_ATTWAIT3_6               0x00004000U        /*!<Bit 6 */
-#define  FSMC_PATT3_ATTWAIT3_7               0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_PATT3_ATTHOLD3                 0x00FF0000U        /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
-#define  FSMC_PATT3_ATTHOLD3_0               0x00010000U        /*!<Bit 0 */
-#define  FSMC_PATT3_ATTHOLD3_1               0x00020000U        /*!<Bit 1 */
-#define  FSMC_PATT3_ATTHOLD3_2               0x00040000U        /*!<Bit 2 */
-#define  FSMC_PATT3_ATTHOLD3_3               0x00080000U        /*!<Bit 3 */
-#define  FSMC_PATT3_ATTHOLD3_4               0x00100000U        /*!<Bit 4 */
-#define  FSMC_PATT3_ATTHOLD3_5               0x00200000U        /*!<Bit 5 */
-#define  FSMC_PATT3_ATTHOLD3_6               0x00400000U        /*!<Bit 6 */
-#define  FSMC_PATT3_ATTHOLD3_7               0x00800000U        /*!<Bit 7 */
-
-#define  FSMC_PATT3_ATTHIZ3                  0xFF000000U        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
-#define  FSMC_PATT3_ATTHIZ3_0                0x01000000U        /*!<Bit 0 */
-#define  FSMC_PATT3_ATTHIZ3_1                0x02000000U        /*!<Bit 1 */
-#define  FSMC_PATT3_ATTHIZ3_2                0x04000000U        /*!<Bit 2 */
-#define  FSMC_PATT3_ATTHIZ3_3                0x08000000U        /*!<Bit 3 */
-#define  FSMC_PATT3_ATTHIZ3_4                0x10000000U        /*!<Bit 4 */
-#define  FSMC_PATT3_ATTHIZ3_5                0x20000000U        /*!<Bit 5 */
-#define  FSMC_PATT3_ATTHIZ3_6                0x40000000U        /*!<Bit 6 */
-#define  FSMC_PATT3_ATTHIZ3_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FSMC_PATT4 register  ******************/
-#define  FSMC_PATT4_ATTSET4                  0x000000FFU        /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
-#define  FSMC_PATT4_ATTSET4_0                0x00000001U        /*!<Bit 0 */
-#define  FSMC_PATT4_ATTSET4_1                0x00000002U        /*!<Bit 1 */
-#define  FSMC_PATT4_ATTSET4_2                0x00000004U        /*!<Bit 2 */
-#define  FSMC_PATT4_ATTSET4_3                0x00000008U        /*!<Bit 3 */
-#define  FSMC_PATT4_ATTSET4_4                0x00000010U        /*!<Bit 4 */
-#define  FSMC_PATT4_ATTSET4_5                0x00000020U        /*!<Bit 5 */
-#define  FSMC_PATT4_ATTSET4_6                0x00000040U        /*!<Bit 6 */
-#define  FSMC_PATT4_ATTSET4_7                0x00000080U        /*!<Bit 7 */
-
-#define  FSMC_PATT4_ATTWAIT4                 0x0000FF00U        /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
-#define  FSMC_PATT4_ATTWAIT4_0               0x00000100U        /*!<Bit 0 */
-#define  FSMC_PATT4_ATTWAIT4_1               0x00000200U        /*!<Bit 1 */
-#define  FSMC_PATT4_ATTWAIT4_2               0x00000400U        /*!<Bit 2 */
-#define  FSMC_PATT4_ATTWAIT4_3               0x00000800U        /*!<Bit 3 */
-#define  FSMC_PATT4_ATTWAIT4_4               0x00001000U        /*!<Bit 4 */
-#define  FSMC_PATT4_ATTWAIT4_5               0x00002000U        /*!<Bit 5 */
-#define  FSMC_PATT4_ATTWAIT4_6               0x00004000U        /*!<Bit 6 */
-#define  FSMC_PATT4_ATTWAIT4_7               0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_PATT4_ATTHOLD4                 0x00FF0000U        /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
-#define  FSMC_PATT4_ATTHOLD4_0               0x00010000U        /*!<Bit 0 */
-#define  FSMC_PATT4_ATTHOLD4_1               0x00020000U        /*!<Bit 1 */
-#define  FSMC_PATT4_ATTHOLD4_2               0x00040000U        /*!<Bit 2 */
-#define  FSMC_PATT4_ATTHOLD4_3               0x00080000U        /*!<Bit 3 */
-#define  FSMC_PATT4_ATTHOLD4_4               0x00100000U        /*!<Bit 4 */
-#define  FSMC_PATT4_ATTHOLD4_5               0x00200000U        /*!<Bit 5 */
-#define  FSMC_PATT4_ATTHOLD4_6               0x00400000U        /*!<Bit 6 */
-#define  FSMC_PATT4_ATTHOLD4_7               0x00800000U        /*!<Bit 7 */
-
-#define  FSMC_PATT4_ATTHIZ4                  0xFF000000U        /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
-#define  FSMC_PATT4_ATTHIZ4_0                0x01000000U        /*!<Bit 0 */
-#define  FSMC_PATT4_ATTHIZ4_1                0x02000000U        /*!<Bit 1 */
-#define  FSMC_PATT4_ATTHIZ4_2                0x04000000U        /*!<Bit 2 */
-#define  FSMC_PATT4_ATTHIZ4_3                0x08000000U        /*!<Bit 3 */
-#define  FSMC_PATT4_ATTHIZ4_4                0x10000000U        /*!<Bit 4 */
-#define  FSMC_PATT4_ATTHIZ4_5                0x20000000U        /*!<Bit 5 */
-#define  FSMC_PATT4_ATTHIZ4_6                0x40000000U        /*!<Bit 6 */
-#define  FSMC_PATT4_ATTHIZ4_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FSMC_PIO4 register  *******************/
-#define  FSMC_PIO4_IOSET4                    0x000000FFU        /*!<IOSET4[7:0] bits (I/O 4 setup time) */
-#define  FSMC_PIO4_IOSET4_0                  0x00000001U        /*!<Bit 0 */
-#define  FSMC_PIO4_IOSET4_1                  0x00000002U        /*!<Bit 1 */
-#define  FSMC_PIO4_IOSET4_2                  0x00000004U        /*!<Bit 2 */
-#define  FSMC_PIO4_IOSET4_3                  0x00000008U        /*!<Bit 3 */
-#define  FSMC_PIO4_IOSET4_4                  0x00000010U        /*!<Bit 4 */
-#define  FSMC_PIO4_IOSET4_5                  0x00000020U        /*!<Bit 5 */
-#define  FSMC_PIO4_IOSET4_6                  0x00000040U        /*!<Bit 6 */
-#define  FSMC_PIO4_IOSET4_7                  0x00000080U        /*!<Bit 7 */
-
-#define  FSMC_PIO4_IOWAIT4                   0x0000FF00U        /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
-#define  FSMC_PIO4_IOWAIT4_0                 0x00000100U        /*!<Bit 0 */
-#define  FSMC_PIO4_IOWAIT4_1                 0x00000200U        /*!<Bit 1 */
-#define  FSMC_PIO4_IOWAIT4_2                 0x00000400U        /*!<Bit 2 */
-#define  FSMC_PIO4_IOWAIT4_3                 0x00000800U        /*!<Bit 3 */
-#define  FSMC_PIO4_IOWAIT4_4                 0x00001000U        /*!<Bit 4 */
-#define  FSMC_PIO4_IOWAIT4_5                 0x00002000U        /*!<Bit 5 */
-#define  FSMC_PIO4_IOWAIT4_6                 0x00004000U        /*!<Bit 6 */
-#define  FSMC_PIO4_IOWAIT4_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_PIO4_IOHOLD4                   0x00FF0000U        /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
-#define  FSMC_PIO4_IOHOLD4_0                 0x00010000U        /*!<Bit 0 */
-#define  FSMC_PIO4_IOHOLD4_1                 0x00020000U        /*!<Bit 1 */
-#define  FSMC_PIO4_IOHOLD4_2                 0x00040000U        /*!<Bit 2 */
-#define  FSMC_PIO4_IOHOLD4_3                 0x00080000U        /*!<Bit 3 */
-#define  FSMC_PIO4_IOHOLD4_4                 0x00100000U        /*!<Bit 4 */
-#define  FSMC_PIO4_IOHOLD4_5                 0x00200000U        /*!<Bit 5 */
-#define  FSMC_PIO4_IOHOLD4_6                 0x00400000U        /*!<Bit 6 */
-#define  FSMC_PIO4_IOHOLD4_7                 0x00800000U        /*!<Bit 7 */
-
-#define  FSMC_PIO4_IOHIZ4                    0xFF000000U        /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
-#define  FSMC_PIO4_IOHIZ4_0                  0x01000000U        /*!<Bit 0 */
-#define  FSMC_PIO4_IOHIZ4_1                  0x02000000U        /*!<Bit 1 */
-#define  FSMC_PIO4_IOHIZ4_2                  0x04000000U        /*!<Bit 2 */
-#define  FSMC_PIO4_IOHIZ4_3                  0x08000000U        /*!<Bit 3 */
-#define  FSMC_PIO4_IOHIZ4_4                  0x10000000U        /*!<Bit 4 */
-#define  FSMC_PIO4_IOHIZ4_5                  0x20000000U        /*!<Bit 5 */
-#define  FSMC_PIO4_IOHIZ4_6                  0x40000000U        /*!<Bit 6 */
-#define  FSMC_PIO4_IOHIZ4_7                  0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FSMC_ECCR2 register  ******************/
-#define  FSMC_ECCR2_ECC2                     0xFFFFFFFFU        /*!<ECC result */
-
-/******************  Bit definition for FSMC_ECCR3 register  ******************/
-#define  FSMC_ECCR3_ECC3                     0xFFFFFFFFU        /*!<ECC result */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    0x00000003U
-#define GPIO_MODER_MODER0_0                  0x00000001U
-#define GPIO_MODER_MODER0_1                  0x00000002U
-
-#define GPIO_MODER_MODER1                    0x0000000CU
-#define GPIO_MODER_MODER1_0                  0x00000004U
-#define GPIO_MODER_MODER1_1                  0x00000008U
-
-#define GPIO_MODER_MODER2                    0x00000030U
-#define GPIO_MODER_MODER2_0                  0x00000010U
-#define GPIO_MODER_MODER2_1                  0x00000020U
-
-#define GPIO_MODER_MODER3                    0x000000C0U
-#define GPIO_MODER_MODER3_0                  0x00000040U
-#define GPIO_MODER_MODER3_1                  0x00000080U
-
-#define GPIO_MODER_MODER4                    0x00000300U
-#define GPIO_MODER_MODER4_0                  0x00000100U
-#define GPIO_MODER_MODER4_1                  0x00000200U
-
-#define GPIO_MODER_MODER5                    0x00000C00U
-#define GPIO_MODER_MODER5_0                  0x00000400U
-#define GPIO_MODER_MODER5_1                  0x00000800U
-
-#define GPIO_MODER_MODER6                    0x00003000U
-#define GPIO_MODER_MODER6_0                  0x00001000U
-#define GPIO_MODER_MODER6_1                  0x00002000U
-
-#define GPIO_MODER_MODER7                    0x0000C000U
-#define GPIO_MODER_MODER7_0                  0x00004000U
-#define GPIO_MODER_MODER7_1                  0x00008000U
-
-#define GPIO_MODER_MODER8                    0x00030000U
-#define GPIO_MODER_MODER8_0                  0x00010000U
-#define GPIO_MODER_MODER8_1                  0x00020000U
-
-#define GPIO_MODER_MODER9                    0x000C0000U
-#define GPIO_MODER_MODER9_0                  0x00040000U
-#define GPIO_MODER_MODER9_1                  0x00080000U
-
-#define GPIO_MODER_MODER10                   0x00300000U
-#define GPIO_MODER_MODER10_0                 0x00100000U
-#define GPIO_MODER_MODER10_1                 0x00200000U
-
-#define GPIO_MODER_MODER11                   0x00C00000U
-#define GPIO_MODER_MODER11_0                 0x00400000U
-#define GPIO_MODER_MODER11_1                 0x00800000U
-
-#define GPIO_MODER_MODER12                   0x03000000U
-#define GPIO_MODER_MODER12_0                 0x01000000U
-#define GPIO_MODER_MODER12_1                 0x02000000U
-
-#define GPIO_MODER_MODER13                   0x0C000000U
-#define GPIO_MODER_MODER13_0                 0x04000000U
-#define GPIO_MODER_MODER13_1                 0x08000000U
-
-#define GPIO_MODER_MODER14                   0x30000000U
-#define GPIO_MODER_MODER14_0                 0x10000000U
-#define GPIO_MODER_MODER14_1                 0x20000000U
-
-#define GPIO_MODER_MODER15                   0xC0000000U
-#define GPIO_MODER_MODER15_0                 0x40000000U
-#define GPIO_MODER_MODER15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     0x00000001U
-#define GPIO_OTYPER_OT_1                     0x00000002U
-#define GPIO_OTYPER_OT_2                     0x00000004U
-#define GPIO_OTYPER_OT_3                     0x00000008U
-#define GPIO_OTYPER_OT_4                     0x00000010U
-#define GPIO_OTYPER_OT_5                     0x00000020U
-#define GPIO_OTYPER_OT_6                     0x00000040U
-#define GPIO_OTYPER_OT_7                     0x00000080U
-#define GPIO_OTYPER_OT_8                     0x00000100U
-#define GPIO_OTYPER_OT_9                     0x00000200U
-#define GPIO_OTYPER_OT_10                    0x00000400U
-#define GPIO_OTYPER_OT_11                    0x00000800U
-#define GPIO_OTYPER_OT_12                    0x00001000U
-#define GPIO_OTYPER_OT_13                    0x00002000U
-#define GPIO_OTYPER_OT_14                    0x00004000U
-#define GPIO_OTYPER_OT_15                    0x00008000U
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
-#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
-#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
-
-#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
-#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
-#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
-
-#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
-#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
-#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
-
-#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
-#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
-#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
-
-#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
-#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
-#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
-
-#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
-#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
-#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
-
-#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
-#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
-#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
-
-#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
-#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
-#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
-
-#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
-#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
-#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
-
-#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
-#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
-#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
-
-#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
-#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
-#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
-
-#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
-#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
-#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
-
-#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
-#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
-#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
-
-#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
-#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
-#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
-
-#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
-#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
-#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
-
-#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
-#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
-#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    0x00000003U
-#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
-#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
-
-#define GPIO_PUPDR_PUPDR1                    0x0000000CU
-#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
-#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
-
-#define GPIO_PUPDR_PUPDR2                    0x00000030U
-#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
-#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
-
-#define GPIO_PUPDR_PUPDR3                    0x000000C0U
-#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
-#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
-
-#define GPIO_PUPDR_PUPDR4                    0x00000300U
-#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
-#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
-
-#define GPIO_PUPDR_PUPDR5                    0x00000C00U
-#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
-#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
-
-#define GPIO_PUPDR_PUPDR6                    0x00003000U
-#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
-#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
-
-#define GPIO_PUPDR_PUPDR7                    0x0000C000U
-#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
-#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
-
-#define GPIO_PUPDR_PUPDR8                    0x00030000U
-#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
-#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
-
-#define GPIO_PUPDR_PUPDR9                    0x000C0000U
-#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
-#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
-
-#define GPIO_PUPDR_PUPDR10                   0x00300000U
-#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
-#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
-
-#define GPIO_PUPDR_PUPDR11                   0x00C00000U
-#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
-#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
-
-#define GPIO_PUPDR_PUPDR12                   0x03000000U
-#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
-#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
-
-#define GPIO_PUPDR_PUPDR13                   0x0C000000U
-#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
-#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
-
-#define GPIO_PUPDR_PUPDR14                   0x30000000U
-#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
-#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
-
-#define GPIO_PUPDR_PUPDR15                   0xC0000000U
-#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
-#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       0x00000001U
-#define GPIO_IDR_IDR_1                       0x00000002U
-#define GPIO_IDR_IDR_2                       0x00000004U
-#define GPIO_IDR_IDR_3                       0x00000008U
-#define GPIO_IDR_IDR_4                       0x00000010U
-#define GPIO_IDR_IDR_5                       0x00000020U
-#define GPIO_IDR_IDR_6                       0x00000040U
-#define GPIO_IDR_IDR_7                       0x00000080U
-#define GPIO_IDR_IDR_8                       0x00000100U
-#define GPIO_IDR_IDR_9                       0x00000200U
-#define GPIO_IDR_IDR_10                      0x00000400U
-#define GPIO_IDR_IDR_11                      0x00000800U
-#define GPIO_IDR_IDR_12                      0x00001000U
-#define GPIO_IDR_IDR_13                      0x00002000U
-#define GPIO_IDR_IDR_14                      0x00004000U
-#define GPIO_IDR_IDR_15                      0x00008000U
-/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
-#define GPIO_OTYPER_IDR_0                    GPIO_IDR_IDR_0
-#define GPIO_OTYPER_IDR_1                    GPIO_IDR_IDR_1
-#define GPIO_OTYPER_IDR_2                    GPIO_IDR_IDR_2
-#define GPIO_OTYPER_IDR_3                    GPIO_IDR_IDR_3
-#define GPIO_OTYPER_IDR_4                    GPIO_IDR_IDR_4
-#define GPIO_OTYPER_IDR_5                    GPIO_IDR_IDR_5
-#define GPIO_OTYPER_IDR_6                    GPIO_IDR_IDR_6
-#define GPIO_OTYPER_IDR_7                    GPIO_IDR_IDR_7
-#define GPIO_OTYPER_IDR_8                    GPIO_IDR_IDR_8
-#define GPIO_OTYPER_IDR_9                    GPIO_IDR_IDR_9
-#define GPIO_OTYPER_IDR_10                   GPIO_IDR_IDR_10
-#define GPIO_OTYPER_IDR_11                   GPIO_IDR_IDR_11
-#define GPIO_OTYPER_IDR_12                   GPIO_IDR_IDR_12
-#define GPIO_OTYPER_IDR_13                   GPIO_IDR_IDR_13
-#define GPIO_OTYPER_IDR_14                   GPIO_IDR_IDR_14
-#define GPIO_OTYPER_IDR_15                   GPIO_IDR_IDR_15
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       0x00000001U
-#define GPIO_ODR_ODR_1                       0x00000002U
-#define GPIO_ODR_ODR_2                       0x00000004U
-#define GPIO_ODR_ODR_3                       0x00000008U
-#define GPIO_ODR_ODR_4                       0x00000010U
-#define GPIO_ODR_ODR_5                       0x00000020U
-#define GPIO_ODR_ODR_6                       0x00000040U
-#define GPIO_ODR_ODR_7                       0x00000080U
-#define GPIO_ODR_ODR_8                       0x00000100U
-#define GPIO_ODR_ODR_9                       0x00000200U
-#define GPIO_ODR_ODR_10                      0x00000400U
-#define GPIO_ODR_ODR_11                      0x00000800U
-#define GPIO_ODR_ODR_12                      0x00001000U
-#define GPIO_ODR_ODR_13                      0x00002000U
-#define GPIO_ODR_ODR_14                      0x00004000U
-#define GPIO_ODR_ODR_15                      0x00008000U
-/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
-#define GPIO_OTYPER_ODR_0                    GPIO_ODR_ODR_0
-#define GPIO_OTYPER_ODR_1                    GPIO_ODR_ODR_1
-#define GPIO_OTYPER_ODR_2                    GPIO_ODR_ODR_2
-#define GPIO_OTYPER_ODR_3                    GPIO_ODR_ODR_3
-#define GPIO_OTYPER_ODR_4                    GPIO_ODR_ODR_4
-#define GPIO_OTYPER_ODR_5                    GPIO_ODR_ODR_5
-#define GPIO_OTYPER_ODR_6                    GPIO_ODR_ODR_6
-#define GPIO_OTYPER_ODR_7                    GPIO_ODR_ODR_7
-#define GPIO_OTYPER_ODR_8                    GPIO_ODR_ODR_8
-#define GPIO_OTYPER_ODR_9                    GPIO_ODR_ODR_9
-#define GPIO_OTYPER_ODR_10                   GPIO_ODR_ODR_10
-#define GPIO_OTYPER_ODR_11                   GPIO_ODR_ODR_11
-#define GPIO_OTYPER_ODR_12                   GPIO_ODR_ODR_12
-#define GPIO_OTYPER_ODR_13                   GPIO_ODR_ODR_13
-#define GPIO_OTYPER_ODR_14                   GPIO_ODR_ODR_14
-#define GPIO_OTYPER_ODR_15                   GPIO_ODR_ODR_15
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       0x00000001U
-#define GPIO_BSRR_BS_1                       0x00000002U
-#define GPIO_BSRR_BS_2                       0x00000004U
-#define GPIO_BSRR_BS_3                       0x00000008U
-#define GPIO_BSRR_BS_4                       0x00000010U
-#define GPIO_BSRR_BS_5                       0x00000020U
-#define GPIO_BSRR_BS_6                       0x00000040U
-#define GPIO_BSRR_BS_7                       0x00000080U
-#define GPIO_BSRR_BS_8                       0x00000100U
-#define GPIO_BSRR_BS_9                       0x00000200U
-#define GPIO_BSRR_BS_10                      0x00000400U
-#define GPIO_BSRR_BS_11                      0x00000800U
-#define GPIO_BSRR_BS_12                      0x00001000U
-#define GPIO_BSRR_BS_13                      0x00002000U
-#define GPIO_BSRR_BS_14                      0x00004000U
-#define GPIO_BSRR_BS_15                      0x00008000U
-#define GPIO_BSRR_BR_0                       0x00010000U
-#define GPIO_BSRR_BR_1                       0x00020000U
-#define GPIO_BSRR_BR_2                       0x00040000U
-#define GPIO_BSRR_BR_3                       0x00080000U
-#define GPIO_BSRR_BR_4                       0x00100000U
-#define GPIO_BSRR_BR_5                       0x00200000U
-#define GPIO_BSRR_BR_6                       0x00400000U
-#define GPIO_BSRR_BR_7                       0x00800000U
-#define GPIO_BSRR_BR_8                       0x01000000U
-#define GPIO_BSRR_BR_9                       0x02000000U
-#define GPIO_BSRR_BR_10                      0x04000000U
-#define GPIO_BSRR_BR_11                      0x08000000U
-#define GPIO_BSRR_BR_12                      0x10000000U
-#define GPIO_BSRR_BR_13                      0x20000000U
-#define GPIO_BSRR_BR_14                      0x40000000U
-#define GPIO_BSRR_BR_15                      0x80000000U
-
-/****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0                       0x00000001U
-#define GPIO_LCKR_LCK1                       0x00000002U
-#define GPIO_LCKR_LCK2                       0x00000004U
-#define GPIO_LCKR_LCK3                       0x00000008U
-#define GPIO_LCKR_LCK4                       0x00000010U
-#define GPIO_LCKR_LCK5                       0x00000020U
-#define GPIO_LCKR_LCK6                       0x00000040U
-#define GPIO_LCKR_LCK7                       0x00000080U
-#define GPIO_LCKR_LCK8                       0x00000100U
-#define GPIO_LCKR_LCK9                       0x00000200U
-#define GPIO_LCKR_LCK10                      0x00000400U
-#define GPIO_LCKR_LCK11                      0x00000800U
-#define GPIO_LCKR_LCK12                      0x00001000U
-#define GPIO_LCKR_LCK13                      0x00002000U
-#define GPIO_LCKR_LCK14                      0x00004000U
-#define GPIO_LCKR_LCK15                      0x00008000U
-#define GPIO_LCKR_LCKK                       0x00010000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Inter-integrated Circuit Interface                    */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          0x00000001U     /*!<Peripheral Enable                             */
-#define  I2C_CR1_SMBUS                       0x00000002U     /*!<SMBus Mode                                    */
-#define  I2C_CR1_SMBTYPE                     0x00000008U     /*!<SMBus Type                                    */
-#define  I2C_CR1_ENARP                       0x00000010U     /*!<ARP Enable                                    */
-#define  I2C_CR1_ENPEC                       0x00000020U     /*!<PEC Enable                                    */
-#define  I2C_CR1_ENGC                        0x00000040U     /*!<General Call Enable                           */
-#define  I2C_CR1_NOSTRETCH                   0x00000080U     /*!<Clock Stretching Disable (Slave mode)  */
-#define  I2C_CR1_START                       0x00000100U     /*!<Start Generation                              */
-#define  I2C_CR1_STOP                        0x00000200U     /*!<Stop Generation                               */
-#define  I2C_CR1_ACK                         0x00000400U     /*!<Acknowledge Enable                            */
-#define  I2C_CR1_POS                         0x00000800U     /*!<Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         0x00001000U     /*!<Packet Error Checking                         */
-#define  I2C_CR1_ALERT                       0x00002000U     /*!<SMBus Alert                                   */
-#define  I2C_CR1_SWRST                       0x00008000U     /*!<Software Reset                                */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        0x0000003FU     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
-#define  I2C_CR2_FREQ_0                      0x00000001U     /*!<Bit 0 */
-#define  I2C_CR2_FREQ_1                      0x00000002U     /*!<Bit 1 */
-#define  I2C_CR2_FREQ_2                      0x00000004U     /*!<Bit 2 */
-#define  I2C_CR2_FREQ_3                      0x00000008U     /*!<Bit 3 */
-#define  I2C_CR2_FREQ_4                      0x00000010U     /*!<Bit 4 */
-#define  I2C_CR2_FREQ_5                      0x00000020U     /*!<Bit 5 */
-
-#define  I2C_CR2_ITERREN                     0x00000100U     /*!<Error Interrupt Enable  */
-#define  I2C_CR2_ITEVTEN                     0x00000200U     /*!<Event Interrupt Enable  */
-#define  I2C_CR2_ITBUFEN                     0x00000400U     /*!<Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       0x00000800U     /*!<DMA Requests Enable     */
-#define  I2C_CR2_LAST                        0x00001000U     /*!<DMA Last Transfer       */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     0x000000FEU     /*!<Interface Address */
-#define  I2C_OAR1_ADD8_9                     0x00000300U     /*!<Interface Address */
-
-#define  I2C_OAR1_ADD0                       0x00000001U     /*!<Bit 0 */
-#define  I2C_OAR1_ADD1                       0x00000002U     /*!<Bit 1 */
-#define  I2C_OAR1_ADD2                       0x00000004U     /*!<Bit 2 */
-#define  I2C_OAR1_ADD3                       0x00000008U     /*!<Bit 3 */
-#define  I2C_OAR1_ADD4                       0x00000010U     /*!<Bit 4 */
-#define  I2C_OAR1_ADD5                       0x00000020U     /*!<Bit 5 */
-#define  I2C_OAR1_ADD6                       0x00000040U     /*!<Bit 6 */
-#define  I2C_OAR1_ADD7                       0x00000080U     /*!<Bit 7 */
-#define  I2C_OAR1_ADD8                       0x00000100U     /*!<Bit 8 */
-#define  I2C_OAR1_ADD9                       0x00000200U     /*!<Bit 9 */
-
-#define  I2C_OAR1_ADDMODE                    0x00008000U     /*!<Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     0x00000001U        /*!<Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       0x000000FEU        /*!<Interface address           */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           0x000000FFU        /*!<8-bit Data Register         */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          0x00000001U     /*!<Start Bit (Master mode)                  */
-#define  I2C_SR1_ADDR                        0x00000002U     /*!<Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         0x00000004U     /*!<Byte Transfer Finished                          */
-#define  I2C_SR1_ADD10                       0x00000008U     /*!<10-bit header sent (Master mode)         */
-#define  I2C_SR1_STOPF                       0x00000010U     /*!<Stop detection (Slave mode)              */
-#define  I2C_SR1_RXNE                        0x00000040U     /*!<Data Register not Empty (receivers)      */
-#define  I2C_SR1_TXE                         0x00000080U     /*!<Data Register Empty (transmitters)       */
-#define  I2C_SR1_BERR                        0x00000100U     /*!<Bus Error                                       */
-#define  I2C_SR1_ARLO                        0x00000200U     /*!<Arbitration Lost (master mode)           */
-#define  I2C_SR1_AF                          0x00000400U     /*!<Acknowledge Failure                             */
-#define  I2C_SR1_OVR                         0x00000800U     /*!<Overrun/Underrun                                */
-#define  I2C_SR1_PECERR                      0x00001000U     /*!<PEC Error in reception                          */
-#define  I2C_SR1_TIMEOUT                     0x00004000U     /*!<Timeout or Tlow Error                           */
-#define  I2C_SR1_SMBALERT                    0x00008000U     /*!<SMBus Alert                                     */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         0x00000001U     /*!<Master/Slave                              */
-#define  I2C_SR2_BUSY                        0x00000002U     /*!<Bus Busy                                  */
-#define  I2C_SR2_TRA                         0x00000004U     /*!<Transmitter/Receiver                      */
-#define  I2C_SR2_GENCALL                     0x00000010U     /*!<General Call Address (Slave mode)  */
-#define  I2C_SR2_SMBDEFAULT                  0x00000020U     /*!<SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     0x00000040U     /*!<SMBus Host Header (Slave mode)     */
-#define  I2C_SR2_DUALF                       0x00000080U     /*!<Dual Flag (Slave mode)             */
-#define  I2C_SR2_PEC                         0x0000FF00U     /*!<Packet Error Checking Register            */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         0x00000FFFU     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        0x00004000U     /*!<Fast Mode Duty Cycle                                       */
-#define  I2C_CCR_FS                          0x00008000U     /*!<I2C Master Mode Selection                                  */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     0x0000003FU     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************  Bit definition for I2C_FLTR register  *******************/
-#define  I2C_FLTR_DNF                        0x0000000FU     /*!<Digital Noise Filter */
-#define  I2C_FLTR_ANOFF                      0x00000010U     /*!<Analog Noise Filter OFF */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Independent WATCHDOG                             */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         0x01U               /*!<Watchdog prescaler value update      */
-#define  IWDG_SR_RVU                         0x02U               /*!<Watchdog counter reload value update */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                             Power Control                                  */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
-#define  PWR_CR_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
-#define  PWR_CR_CWUF                         0x00000004U     /*!< Clear Wakeup Flag                   */
-#define  PWR_CR_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
-#define  PWR_CR_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
-
-#define  PWR_CR_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        0x00000020U     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        0x00000040U     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        0x00000080U     /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
-
-#define  PWR_CR_DBP                          0x00000100U     /*!< Disable Backup Domain write protection               */
-#define  PWR_CR_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                        */
-#define  PWR_CR_VOS                          0x00004000U     /*!< VOS bit (Regulator voltage scaling output selection) */
-
-/* Legacy define */
-#define  PWR_CR_PMODE                        PWR_CR_VOS
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         0x00000001U     /*!< Wakeup Flag                                      */
-#define  PWR_CSR_SBF                         0x00000002U     /*!< Standby Flag                                     */
-#define  PWR_CSR_PVDO                        0x00000004U     /*!< PVD Output                                       */
-#define  PWR_CSR_BRR                         0x00000008U     /*!< Backup regulator ready                           */
-#define  PWR_CSR_EWUP                        0x00000100U     /*!< Enable WKUP pin                                  */
-#define  PWR_CSR_BRE                         0x00000200U     /*!< Backup regulator enable                          */
-#define  PWR_CSR_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
-
-/* Legacy define */
-#define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        0x00000001U
-#define  RCC_CR_HSIRDY                       0x00000002U
-
-#define  RCC_CR_HSITRIM                      0x000000F8U
-#define  RCC_CR_HSITRIM_0                    0x00000008U/*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    0x00000010U/*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    0x00000020U/*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    0x00000040U/*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    0x00000080U/*!<Bit 4 */
-
-#define  RCC_CR_HSICAL                       0x0000FF00U
-#define  RCC_CR_HSICAL_0                     0x00000100U/*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     0x00000200U/*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     0x00000400U/*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     0x00000800U/*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     0x00001000U/*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     0x00002000U/*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     0x00004000U/*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     0x00008000U/*!<Bit 7 */
-
-#define  RCC_CR_HSEON                        0x00010000U
-#define  RCC_CR_HSERDY                       0x00020000U
-#define  RCC_CR_HSEBYP                       0x00040000U
-#define  RCC_CR_CSSON                        0x00080000U
-#define  RCC_CR_PLLON                        0x01000000U
-#define  RCC_CR_PLLRDY                       0x02000000U
-#define  RCC_CR_PLLI2SON                     0x04000000U
-#define  RCC_CR_PLLI2SRDY                    0x08000000U
-
-/********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    0x0000003FU
-#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
-#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
-#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
-#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
-#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
-#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
-
-#define  RCC_PLLCFGR_PLLN                     0x00007FC0U
-#define  RCC_PLLCFGR_PLLN_0                   0x00000040U
-#define  RCC_PLLCFGR_PLLN_1                   0x00000080U
-#define  RCC_PLLCFGR_PLLN_2                   0x00000100U
-#define  RCC_PLLCFGR_PLLN_3                   0x00000200U
-#define  RCC_PLLCFGR_PLLN_4                   0x00000400U
-#define  RCC_PLLCFGR_PLLN_5                   0x00000800U
-#define  RCC_PLLCFGR_PLLN_6                   0x00001000U
-#define  RCC_PLLCFGR_PLLN_7                   0x00002000U
-#define  RCC_PLLCFGR_PLLN_8                   0x00004000U
-
-#define  RCC_PLLCFGR_PLLP                    0x00030000U
-#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
-#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
-
-#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
-
-#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
-#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
-#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
-#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
-#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-/*!< SW configuration */
-#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
-
-#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
-
-#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
-
-#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
-
-/*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     0x001F0000U
-#define  RCC_CFGR_RTCPRE_0                   0x00010000U
-#define  RCC_CFGR_RTCPRE_1                   0x00020000U
-#define  RCC_CFGR_RTCPRE_2                   0x00040000U
-#define  RCC_CFGR_RTCPRE_3                   0x00080000U
-#define  RCC_CFGR_RTCPRE_4                   0x00100000U
-
-/*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       0x00600000U
-#define  RCC_CFGR_MCO1_0                     0x00200000U
-#define  RCC_CFGR_MCO1_1                     0x00400000U
-
-#define  RCC_CFGR_I2SSRC                     0x00800000U
-
-#define  RCC_CFGR_MCO1PRE                    0x07000000U
-#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
-#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
-#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
-
-#define  RCC_CFGR_MCO2PRE                    0x38000000U
-#define  RCC_CFGR_MCO2PRE_0                  0x08000000U
-#define  RCC_CFGR_MCO2PRE_1                  0x10000000U
-#define  RCC_CFGR_MCO2PRE_2                  0x20000000U
-
-#define  RCC_CFGR_MCO2                       0xC0000000U
-#define  RCC_CFGR_MCO2_0                     0x40000000U
-#define  RCC_CFGR_MCO2_1                     0x80000000U
-
-/********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     0x00000001U
-#define  RCC_CIR_LSERDYF                     0x00000002U
-#define  RCC_CIR_HSIRDYF                     0x00000004U
-#define  RCC_CIR_HSERDYF                     0x00000008U
-#define  RCC_CIR_PLLRDYF                     0x00000010U
-#define  RCC_CIR_PLLI2SRDYF                  0x00000020U
-
-#define  RCC_CIR_CSSF                        0x00000080U
-#define  RCC_CIR_LSIRDYIE                    0x00000100U
-#define  RCC_CIR_LSERDYIE                    0x00000200U
-#define  RCC_CIR_HSIRDYIE                    0x00000400U
-#define  RCC_CIR_HSERDYIE                    0x00000800U
-#define  RCC_CIR_PLLRDYIE                    0x00001000U
-#define  RCC_CIR_PLLI2SRDYIE                 0x00002000U
-
-#define  RCC_CIR_LSIRDYC                     0x00010000U
-#define  RCC_CIR_LSERDYC                     0x00020000U
-#define  RCC_CIR_HSIRDYC                     0x00040000U
-#define  RCC_CIR_HSERDYC                     0x00080000U
-#define  RCC_CIR_PLLRDYC                     0x00100000U
-#define  RCC_CIR_PLLI2SRDYC                  0x00200000U
-
-#define  RCC_CIR_CSSC                        0x00800000U
-
-/********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
-#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
-#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
-#define  RCC_AHB1RSTR_GPIODRST               0x00000008U
-#define  RCC_AHB1RSTR_GPIOERST               0x00000010U
-#define  RCC_AHB1RSTR_GPIOFRST               0x00000020U
-#define  RCC_AHB1RSTR_GPIOGRST               0x00000040U
-#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
-#define  RCC_AHB1RSTR_GPIOIRST               0x00000100U
-#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
-#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
-#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
-#define  RCC_AHB1RSTR_ETHMACRST              0x02000000U
-#define  RCC_AHB1RSTR_OTGHRST                0x20000000U
-
-/********************  Bit definition for RCC_AHB2RSTR register  **************/
-#define  RCC_AHB2RSTR_DCMIRST                0x00000001U
-#define  RCC_AHB2RSTR_RNGRST                 0x00000040U
-#define  RCC_AHB2RSTR_OTGFSRST               0x00000080U
-
-/********************  Bit definition for RCC_AHB3RSTR register  **************/
-
-#define  RCC_AHB3RSTR_FSMCRST                0x00000001U
-
-/********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM2RST                0x00000001U
-#define  RCC_APB1RSTR_TIM3RST                0x00000002U
-#define  RCC_APB1RSTR_TIM4RST                0x00000004U
-#define  RCC_APB1RSTR_TIM5RST                0x00000008U
-#define  RCC_APB1RSTR_TIM6RST                0x00000010U
-#define  RCC_APB1RSTR_TIM7RST                0x00000020U
-#define  RCC_APB1RSTR_TIM12RST               0x00000040U
-#define  RCC_APB1RSTR_TIM13RST               0x00000080U
-#define  RCC_APB1RSTR_TIM14RST               0x00000100U
-#define  RCC_APB1RSTR_WWDGRST                0x00000800U
-#define  RCC_APB1RSTR_SPI2RST                0x00004000U
-#define  RCC_APB1RSTR_SPI3RST                0x00008000U
-#define  RCC_APB1RSTR_USART2RST              0x00020000U
-#define  RCC_APB1RSTR_USART3RST              0x00040000U
-#define  RCC_APB1RSTR_UART4RST               0x00080000U
-#define  RCC_APB1RSTR_UART5RST               0x00100000U
-#define  RCC_APB1RSTR_I2C1RST                0x00200000U
-#define  RCC_APB1RSTR_I2C2RST                0x00400000U
-#define  RCC_APB1RSTR_I2C3RST                0x00800000U
-#define  RCC_APB1RSTR_CAN1RST                0x02000000U
-#define  RCC_APB1RSTR_CAN2RST                0x04000000U
-#define  RCC_APB1RSTR_PWRRST                 0x10000000U
-#define  RCC_APB1RSTR_DACRST                 0x20000000U
-
-/********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                0x00000001U
-#define  RCC_APB2RSTR_TIM8RST                0x00000002U
-#define  RCC_APB2RSTR_USART1RST              0x00000010U
-#define  RCC_APB2RSTR_USART6RST              0x00000020U
-#define  RCC_APB2RSTR_ADCRST                 0x00000100U
-#define  RCC_APB2RSTR_SDIORST                0x00000800U
-#define  RCC_APB2RSTR_SPI1RST                0x00001000U
-#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
-#define  RCC_APB2RSTR_TIM9RST                0x00010000U
-#define  RCC_APB2RSTR_TIM10RST               0x00020000U
-#define  RCC_APB2RSTR_TIM11RST               0x00040000U
-
-/* Old SPI1RST bit definition, maintained for legacy purpose */
-#define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
-
-/********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
-#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
-#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
-#define  RCC_AHB1ENR_GPIODEN                 0x00000008U
-#define  RCC_AHB1ENR_GPIOEEN                 0x00000010U
-#define  RCC_AHB1ENR_GPIOFEN                 0x00000020U
-#define  RCC_AHB1ENR_GPIOGEN                 0x00000040U
-#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
-#define  RCC_AHB1ENR_GPIOIEN                 0x00000100U
-#define  RCC_AHB1ENR_CRCEN                   0x00001000U
-#define  RCC_AHB1ENR_BKPSRAMEN               0x00040000U
-#define  RCC_AHB1ENR_CCMDATARAMEN            0x00100000U
-#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
-#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
-
-#define  RCC_AHB1ENR_ETHMACEN                0x02000000U
-#define  RCC_AHB1ENR_ETHMACTXEN              0x04000000U
-#define  RCC_AHB1ENR_ETHMACRXEN              0x08000000U
-#define  RCC_AHB1ENR_ETHMACPTPEN             0x10000000U
-#define  RCC_AHB1ENR_OTGHSEN                 0x20000000U
-#define  RCC_AHB1ENR_OTGHSULPIEN             0x40000000U
-
-/********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define  RCC_AHB2ENR_DCMIEN                  0x00000001U
-#define  RCC_AHB2ENR_RNGEN                   0x00000040U
-#define  RCC_AHB2ENR_OTGFSEN                 0x00000080U
-
-/********************  Bit definition for RCC_AHB3ENR register  ***************/
-
-#define  RCC_AHB3ENR_FSMCEN                  0x00000001U
-
-/********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM2EN                  0x00000001U
-#define  RCC_APB1ENR_TIM3EN                  0x00000002U
-#define  RCC_APB1ENR_TIM4EN                  0x00000004U
-#define  RCC_APB1ENR_TIM5EN                  0x00000008U
-#define  RCC_APB1ENR_TIM6EN                  0x00000010U
-#define  RCC_APB1ENR_TIM7EN                  0x00000020U
-#define  RCC_APB1ENR_TIM12EN                 0x00000040U
-#define  RCC_APB1ENR_TIM13EN                 0x00000080U
-#define  RCC_APB1ENR_TIM14EN                 0x00000100U
-#define  RCC_APB1ENR_WWDGEN                  0x00000800U
-#define  RCC_APB1ENR_SPI2EN                  0x00004000U
-#define  RCC_APB1ENR_SPI3EN                  0x00008000U
-#define  RCC_APB1ENR_USART2EN                0x00020000U
-#define  RCC_APB1ENR_USART3EN                0x00040000U
-#define  RCC_APB1ENR_UART4EN                 0x00080000U
-#define  RCC_APB1ENR_UART5EN                 0x00100000U
-#define  RCC_APB1ENR_I2C1EN                  0x00200000U
-#define  RCC_APB1ENR_I2C2EN                  0x00400000U
-#define  RCC_APB1ENR_I2C3EN                  0x00800000U
-#define  RCC_APB1ENR_CAN1EN                  0x02000000U
-#define  RCC_APB1ENR_CAN2EN                  0x04000000U
-#define  RCC_APB1ENR_PWREN                   0x10000000U
-#define  RCC_APB1ENR_DACEN                   0x20000000U
-
-/********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  0x00000001U
-#define  RCC_APB2ENR_TIM8EN                  0x00000002U
-#define  RCC_APB2ENR_USART1EN                0x00000010U
-#define  RCC_APB2ENR_USART6EN                0x00000020U
-#define  RCC_APB2ENR_ADC1EN                  0x00000100U
-#define  RCC_APB2ENR_ADC2EN                  0x00000200U
-#define  RCC_APB2ENR_ADC3EN                  0x00000400U
-#define  RCC_APB2ENR_SDIOEN                  0x00000800U
-#define  RCC_APB2ENR_SPI1EN                  0x00001000U
-#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
-#define  RCC_APB2ENR_TIM9EN                  0x00010000U
-#define  RCC_APB2ENR_TIM10EN                 0x00020000U
-#define  RCC_APB2ENR_TIM11EN                 0x00040000U
-#define  RCC_APB2ENR_SPI5EN                  0x00100000U
-#define  RCC_APB2ENR_SPI6EN                  0x00200000U
-
-/********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
-#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
-#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
-#define  RCC_AHB1LPENR_GPIODLPEN             0x00000008U
-#define  RCC_AHB1LPENR_GPIOELPEN             0x00000010U
-#define  RCC_AHB1LPENR_GPIOFLPEN             0x00000020U
-#define  RCC_AHB1LPENR_GPIOGLPEN             0x00000040U
-#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
-#define  RCC_AHB1LPENR_GPIOILPEN             0x00000100U
-#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
-#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
-#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
-#define  RCC_AHB1LPENR_SRAM2LPEN             0x00020000U
-#define  RCC_AHB1LPENR_BKPSRAMLPEN           0x00040000U
-#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
-#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
-#define  RCC_AHB1LPENR_ETHMACLPEN            0x02000000U
-#define  RCC_AHB1LPENR_ETHMACTXLPEN          0x04000000U
-#define  RCC_AHB1LPENR_ETHMACRXLPEN          0x08000000U
-#define  RCC_AHB1LPENR_ETHMACPTPLPEN         0x10000000U
-#define  RCC_AHB1LPENR_OTGHSLPEN             0x20000000U
-#define  RCC_AHB1LPENR_OTGHSULPILPEN         0x40000000U
-
-/********************  Bit definition for RCC_AHB2LPENR register  *************/
-#define  RCC_AHB2LPENR_DCMILPEN              0x00000001U
-#define  RCC_AHB2LPENR_RNGLPEN               0x00000040U
-#define  RCC_AHB2LPENR_OTGFSLPEN             0x00000080U
-
-/********************  Bit definition for RCC_AHB3LPENR register  *************/
-
-#define  RCC_AHB3LPENR_FSMCLPEN              0x00000001U
-
-/********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM2LPEN              0x00000001U
-#define  RCC_APB1LPENR_TIM3LPEN              0x00000002U
-#define  RCC_APB1LPENR_TIM4LPEN              0x00000004U
-#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
-#define  RCC_APB1LPENR_TIM6LPEN              0x00000010U
-#define  RCC_APB1LPENR_TIM7LPEN              0x00000020U
-#define  RCC_APB1LPENR_TIM12LPEN             0x00000040U
-#define  RCC_APB1LPENR_TIM13LPEN             0x00000080U
-#define  RCC_APB1LPENR_TIM14LPEN             0x00000100U
-#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
-#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U
-#define  RCC_APB1LPENR_SPI3LPEN              0x00008000U
-#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
-#define  RCC_APB1LPENR_USART3LPEN            0x00040000U
-#define  RCC_APB1LPENR_UART4LPEN             0x00080000U
-#define  RCC_APB1LPENR_UART5LPEN             0x00100000U
-#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
-#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
-#define  RCC_APB1LPENR_I2C3LPEN              0x00800000U
-#define  RCC_APB1LPENR_CAN1LPEN              0x02000000U
-#define  RCC_APB1LPENR_CAN2LPEN              0x04000000U
-#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
-#define  RCC_APB1LPENR_DACLPEN               0x20000000U
-
-/********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
-#define  RCC_APB2LPENR_TIM8LPEN              0x00000002U
-#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
-#define  RCC_APB2LPENR_USART6LPEN            0x00000020U
-#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
-#define  RCC_APB2LPENR_ADC2LPEN              0x00000200U
-#define  RCC_APB2LPENR_ADC3LPEN              0x00000400U
-#define  RCC_APB2LPENR_SDIOLPEN              0x00000800U
-#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
-#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
-#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
-#define  RCC_APB2LPENR_TIM10LPEN             0x00020000U
-#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
-
-/********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      0x00000001U
-#define  RCC_BDCR_LSERDY                     0x00000002U
-#define  RCC_BDCR_LSEBYP                     0x00000004U
-
-#define  RCC_BDCR_RTCSEL                    0x00000300U
-#define  RCC_BDCR_RTCSEL_0                  0x00000100U
-#define  RCC_BDCR_RTCSEL_1                  0x00000200U
-
-#define  RCC_BDCR_RTCEN                      0x00008000U
-#define  RCC_BDCR_BDRST                      0x00010000U
-
-/********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       0x00000001U
-#define  RCC_CSR_LSIRDY                      0x00000002U
-#define  RCC_CSR_RMVF                        0x01000000U
-#define  RCC_CSR_BORRSTF                     0x02000000U
-#define  RCC_CSR_PADRSTF                     0x04000000U
-#define  RCC_CSR_PORRSTF                     0x08000000U
-#define  RCC_CSR_SFTRSTF                     0x10000000U
-#define  RCC_CSR_WDGRSTF                     0x20000000U
-#define  RCC_CSR_WWDGRSTF                    0x40000000U
-#define  RCC_CSR_LPWRRSTF                    0x80000000U
-
-/********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    0x00001FFFU
-#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
-#define  RCC_SSCGR_SPREADSEL                 0x40000000U
-#define  RCC_SSCGR_SSCGEN                    0x80000000U
-
-/********************  Bit definition for RCC_PLLI2SCFGR register  ************/
-#define  RCC_PLLI2SCFGR_PLLI2SN              0x00007FC0U
-#define  RCC_PLLI2SCFGR_PLLI2SN_0            0x00000040U
-#define  RCC_PLLI2SCFGR_PLLI2SN_1            0x00000080U
-#define  RCC_PLLI2SCFGR_PLLI2SN_2            0x00000100U
-#define  RCC_PLLI2SCFGR_PLLI2SN_3            0x00000200U
-#define  RCC_PLLI2SCFGR_PLLI2SN_4            0x00000400U
-#define  RCC_PLLI2SCFGR_PLLI2SN_5            0x00000800U
-#define  RCC_PLLI2SCFGR_PLLI2SN_6            0x00001000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_7            0x00002000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_8            0x00004000U
-
-#define  RCC_PLLI2SCFGR_PLLI2SR              0x70000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_0            0x10000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_1            0x20000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_2            0x40000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    RNG                                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN                         0x00000004U
-#define RNG_CR_IE                            0x00000008U
-
-/********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY                          0x00000001U
-#define RNG_SR_CECS                          0x00000002U
-#define RNG_SR_SECS                          0x00000004U
-#define RNG_SR_CEIS                          0x00000020U
-#define RNG_SR_SEIS                          0x00000040U
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            0x00400000U
-#define RTC_TR_HT                            0x00300000U
-#define RTC_TR_HT_0                          0x00100000U
-#define RTC_TR_HT_1                          0x00200000U
-#define RTC_TR_HU                            0x000F0000U
-#define RTC_TR_HU_0                          0x00010000U
-#define RTC_TR_HU_1                          0x00020000U
-#define RTC_TR_HU_2                          0x00040000U
-#define RTC_TR_HU_3                          0x00080000U
-#define RTC_TR_MNT                           0x00007000U
-#define RTC_TR_MNT_0                         0x00001000U
-#define RTC_TR_MNT_1                         0x00002000U
-#define RTC_TR_MNT_2                         0x00004000U
-#define RTC_TR_MNU                           0x00000F00U
-#define RTC_TR_MNU_0                         0x00000100U
-#define RTC_TR_MNU_1                         0x00000200U
-#define RTC_TR_MNU_2                         0x00000400U
-#define RTC_TR_MNU_3                         0x00000800U
-#define RTC_TR_ST                            0x00000070U
-#define RTC_TR_ST_0                          0x00000010U
-#define RTC_TR_ST_1                          0x00000020U
-#define RTC_TR_ST_2                          0x00000040U
-#define RTC_TR_SU                            0x0000000FU
-#define RTC_TR_SU_0                          0x00000001U
-#define RTC_TR_SU_1                          0x00000002U
-#define RTC_TR_SU_2                          0x00000004U
-#define RTC_TR_SU_3                          0x00000008U
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            0x00F00000U
-#define RTC_DR_YT_0                          0x00100000U
-#define RTC_DR_YT_1                          0x00200000U
-#define RTC_DR_YT_2                          0x00400000U
-#define RTC_DR_YT_3                          0x00800000U
-#define RTC_DR_YU                            0x000F0000U
-#define RTC_DR_YU_0                          0x00010000U
-#define RTC_DR_YU_1                          0x00020000U
-#define RTC_DR_YU_2                          0x00040000U
-#define RTC_DR_YU_3                          0x00080000U
-#define RTC_DR_WDU                           0x0000E000U
-#define RTC_DR_WDU_0                         0x00002000U
-#define RTC_DR_WDU_1                         0x00004000U
-#define RTC_DR_WDU_2                         0x00008000U
-#define RTC_DR_MT                            0x00001000U
-#define RTC_DR_MU                            0x00000F00U
-#define RTC_DR_MU_0                          0x00000100U
-#define RTC_DR_MU_1                          0x00000200U
-#define RTC_DR_MU_2                          0x00000400U
-#define RTC_DR_MU_3                          0x00000800U
-#define RTC_DR_DT                            0x00000030U
-#define RTC_DR_DT_0                          0x00000010U
-#define RTC_DR_DT_1                          0x00000020U
-#define RTC_DR_DU                            0x0000000FU
-#define RTC_DR_DU_0                          0x00000001U
-#define RTC_DR_DU_1                          0x00000002U
-#define RTC_DR_DU_2                          0x00000004U
-#define RTC_DR_DU_3                          0x00000008U
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           0x00800000U
-#define RTC_CR_OSEL                          0x00600000U
-#define RTC_CR_OSEL_0                        0x00200000U
-#define RTC_CR_OSEL_1                        0x00400000U
-#define RTC_CR_POL                           0x00100000U
-#define RTC_CR_COSEL                         0x00080000U
-#define RTC_CR_BCK                           0x00040000U
-#define RTC_CR_SUB1H                         0x00020000U
-#define RTC_CR_ADD1H                         0x00010000U
-#define RTC_CR_TSIE                          0x00008000U
-#define RTC_CR_WUTIE                         0x00004000U
-#define RTC_CR_ALRBIE                        0x00002000U
-#define RTC_CR_ALRAIE                        0x00001000U
-#define RTC_CR_TSE                           0x00000800U
-#define RTC_CR_WUTE                          0x00000400U
-#define RTC_CR_ALRBE                         0x00000200U
-#define RTC_CR_ALRAE                         0x00000100U
-#define RTC_CR_DCE                           0x00000080U
-#define RTC_CR_FMT                           0x00000040U
-#define RTC_CR_BYPSHAD                       0x00000020U
-#define RTC_CR_REFCKON                       0x00000010U
-#define RTC_CR_TSEDGE                        0x00000008U
-#define RTC_CR_WUCKSEL                       0x00000007U
-#define RTC_CR_WUCKSEL_0                     0x00000001U
-#define RTC_CR_WUCKSEL_1                     0x00000002U
-#define RTC_CR_WUCKSEL_2                     0x00000004U
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      0x00010000U
-#define RTC_ISR_TAMP1F                       0x00002000U
-#define RTC_ISR_TAMP2F                       0x00004000U
-#define RTC_ISR_TSOVF                        0x00001000U
-#define RTC_ISR_TSF                          0x00000800U
-#define RTC_ISR_WUTF                         0x00000400U
-#define RTC_ISR_ALRBF                        0x00000200U
-#define RTC_ISR_ALRAF                        0x00000100U
-#define RTC_ISR_INIT                         0x00000080U
-#define RTC_ISR_INITF                        0x00000040U
-#define RTC_ISR_RSF                          0x00000020U
-#define RTC_ISR_INITS                        0x00000010U
-#define RTC_ISR_SHPF                         0x00000008U
-#define RTC_ISR_WUTWF                        0x00000004U
-#define RTC_ISR_ALRBWF                       0x00000002U
-#define RTC_ISR_ALRAWF                       0x00000001U
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    0x007F0000U
-#define RTC_PRER_PREDIV_S                    0x00007FFFU
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS                       0x00000080U
-#define RTC_CALIBR_DC                        0x0000001FU
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      0x80000000U
-#define RTC_ALRMAR_WDSEL                     0x40000000U
-#define RTC_ALRMAR_DT                        0x30000000U
-#define RTC_ALRMAR_DT_0                      0x10000000U
-#define RTC_ALRMAR_DT_1                      0x20000000U
-#define RTC_ALRMAR_DU                        0x0F000000U
-#define RTC_ALRMAR_DU_0                      0x01000000U
-#define RTC_ALRMAR_DU_1                      0x02000000U
-#define RTC_ALRMAR_DU_2                      0x04000000U
-#define RTC_ALRMAR_DU_3                      0x08000000U
-#define RTC_ALRMAR_MSK3                      0x00800000U
-#define RTC_ALRMAR_PM                        0x00400000U
-#define RTC_ALRMAR_HT                        0x00300000U
-#define RTC_ALRMAR_HT_0                      0x00100000U
-#define RTC_ALRMAR_HT_1                      0x00200000U
-#define RTC_ALRMAR_HU                        0x000F0000U
-#define RTC_ALRMAR_HU_0                      0x00010000U
-#define RTC_ALRMAR_HU_1                      0x00020000U
-#define RTC_ALRMAR_HU_2                      0x00040000U
-#define RTC_ALRMAR_HU_3                      0x00080000U
-#define RTC_ALRMAR_MSK2                      0x00008000U
-#define RTC_ALRMAR_MNT                       0x00007000U
-#define RTC_ALRMAR_MNT_0                     0x00001000U
-#define RTC_ALRMAR_MNT_1                     0x00002000U
-#define RTC_ALRMAR_MNT_2                     0x00004000U
-#define RTC_ALRMAR_MNU                       0x00000F00U
-#define RTC_ALRMAR_MNU_0                     0x00000100U
-#define RTC_ALRMAR_MNU_1                     0x00000200U
-#define RTC_ALRMAR_MNU_2                     0x00000400U
-#define RTC_ALRMAR_MNU_3                     0x00000800U
-#define RTC_ALRMAR_MSK1                      0x00000080U
-#define RTC_ALRMAR_ST                        0x00000070U
-#define RTC_ALRMAR_ST_0                      0x00000010U
-#define RTC_ALRMAR_ST_1                      0x00000020U
-#define RTC_ALRMAR_ST_2                      0x00000040U
-#define RTC_ALRMAR_SU                        0x0000000FU
-#define RTC_ALRMAR_SU_0                      0x00000001U
-#define RTC_ALRMAR_SU_1                      0x00000002U
-#define RTC_ALRMAR_SU_2                      0x00000004U
-#define RTC_ALRMAR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      0x80000000U
-#define RTC_ALRMBR_WDSEL                     0x40000000U
-#define RTC_ALRMBR_DT                        0x30000000U
-#define RTC_ALRMBR_DT_0                      0x10000000U
-#define RTC_ALRMBR_DT_1                      0x20000000U
-#define RTC_ALRMBR_DU                        0x0F000000U
-#define RTC_ALRMBR_DU_0                      0x01000000U
-#define RTC_ALRMBR_DU_1                      0x02000000U
-#define RTC_ALRMBR_DU_2                      0x04000000U
-#define RTC_ALRMBR_DU_3                      0x08000000U
-#define RTC_ALRMBR_MSK3                      0x00800000U
-#define RTC_ALRMBR_PM                        0x00400000U
-#define RTC_ALRMBR_HT                        0x00300000U
-#define RTC_ALRMBR_HT_0                      0x00100000U
-#define RTC_ALRMBR_HT_1                      0x00200000U
-#define RTC_ALRMBR_HU                        0x000F0000U
-#define RTC_ALRMBR_HU_0                      0x00010000U
-#define RTC_ALRMBR_HU_1                      0x00020000U
-#define RTC_ALRMBR_HU_2                      0x00040000U
-#define RTC_ALRMBR_HU_3                      0x00080000U
-#define RTC_ALRMBR_MSK2                      0x00008000U
-#define RTC_ALRMBR_MNT                       0x00007000U
-#define RTC_ALRMBR_MNT_0                     0x00001000U
-#define RTC_ALRMBR_MNT_1                     0x00002000U
-#define RTC_ALRMBR_MNT_2                     0x00004000U
-#define RTC_ALRMBR_MNU                       0x00000F00U
-#define RTC_ALRMBR_MNU_0                     0x00000100U
-#define RTC_ALRMBR_MNU_1                     0x00000200U
-#define RTC_ALRMBR_MNU_2                     0x00000400U
-#define RTC_ALRMBR_MNU_3                     0x00000800U
-#define RTC_ALRMBR_MSK1                      0x00000080U
-#define RTC_ALRMBR_ST                        0x00000070U
-#define RTC_ALRMBR_ST_0                      0x00000010U
-#define RTC_ALRMBR_ST_1                      0x00000020U
-#define RTC_ALRMBR_ST_2                      0x00000040U
-#define RTC_ALRMBR_SU                        0x0000000FU
-#define RTC_ALRMBR_SU_0                      0x00000001U
-#define RTC_ALRMBR_SU_1                      0x00000002U
-#define RTC_ALRMBR_SU_2                      0x00000004U
-#define RTC_ALRMBR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          0x000000FFU
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           0x0000FFFFU
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     0x00007FFFU
-#define RTC_SHIFTR_ADD1S                     0x80000000U
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          0x00400000U
-#define RTC_TSTR_HT                          0x00300000U
-#define RTC_TSTR_HT_0                        0x00100000U
-#define RTC_TSTR_HT_1                        0x00200000U
-#define RTC_TSTR_HU                          0x000F0000U
-#define RTC_TSTR_HU_0                        0x00010000U
-#define RTC_TSTR_HU_1                        0x00020000U
-#define RTC_TSTR_HU_2                        0x00040000U
-#define RTC_TSTR_HU_3                        0x00080000U
-#define RTC_TSTR_MNT                         0x00007000U
-#define RTC_TSTR_MNT_0                       0x00001000U
-#define RTC_TSTR_MNT_1                       0x00002000U
-#define RTC_TSTR_MNT_2                       0x00004000U
-#define RTC_TSTR_MNU                         0x00000F00U
-#define RTC_TSTR_MNU_0                       0x00000100U
-#define RTC_TSTR_MNU_1                       0x00000200U
-#define RTC_TSTR_MNU_2                       0x00000400U
-#define RTC_TSTR_MNU_3                       0x00000800U
-#define RTC_TSTR_ST                          0x00000070U
-#define RTC_TSTR_ST_0                        0x00000010U
-#define RTC_TSTR_ST_1                        0x00000020U
-#define RTC_TSTR_ST_2                        0x00000040U
-#define RTC_TSTR_SU                          0x0000000FU
-#define RTC_TSTR_SU_0                        0x00000001U
-#define RTC_TSTR_SU_1                        0x00000002U
-#define RTC_TSTR_SU_2                        0x00000004U
-#define RTC_TSTR_SU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         0x0000E000U
-#define RTC_TSDR_WDU_0                       0x00002000U
-#define RTC_TSDR_WDU_1                       0x00004000U
-#define RTC_TSDR_WDU_2                       0x00008000U
-#define RTC_TSDR_MT                          0x00001000U
-#define RTC_TSDR_MU                          0x00000F00U
-#define RTC_TSDR_MU_0                        0x00000100U
-#define RTC_TSDR_MU_1                        0x00000200U
-#define RTC_TSDR_MU_2                        0x00000400U
-#define RTC_TSDR_MU_3                        0x00000800U
-#define RTC_TSDR_DT                          0x00000030U
-#define RTC_TSDR_DT_0                        0x00000010U
-#define RTC_TSDR_DT_1                        0x00000020U
-#define RTC_TSDR_DU                          0x0000000FU
-#define RTC_TSDR_DU_0                        0x00000001U
-#define RTC_TSDR_DU_1                        0x00000002U
-#define RTC_TSDR_DU_2                        0x00000004U
-#define RTC_TSDR_DU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        0x00008000U
-#define RTC_CALR_CALW8                       0x00004000U
-#define RTC_CALR_CALW16                      0x00002000U
-#define RTC_CALR_CALM                        0x000001FFU
-#define RTC_CALR_CALM_0                      0x00000001U
-#define RTC_CALR_CALM_1                      0x00000002U
-#define RTC_CALR_CALM_2                      0x00000004U
-#define RTC_CALR_CALM_3                      0x00000008U
-#define RTC_CALR_CALM_4                      0x00000010U
-#define RTC_CALR_CALM_5                      0x00000020U
-#define RTC_CALR_CALM_6                      0x00000040U
-#define RTC_CALR_CALM_7                      0x00000080U
-#define RTC_CALR_CALM_8                      0x00000100U
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               0x00040000U
-#define RTC_TAFCR_TSINSEL                    0x00020000U
-#define RTC_TAFCR_TAMPINSEL                  0x00010000U
-#define RTC_TAFCR_TAMPPUDIS                  0x00008000U
-#define RTC_TAFCR_TAMPPRCH                   0x00006000U
-#define RTC_TAFCR_TAMPPRCH_0                 0x00002000U
-#define RTC_TAFCR_TAMPPRCH_1                 0x00004000U
-#define RTC_TAFCR_TAMPFLT                    0x00001800U
-#define RTC_TAFCR_TAMPFLT_0                  0x00000800U
-#define RTC_TAFCR_TAMPFLT_1                  0x00001000U
-#define RTC_TAFCR_TAMPFREQ                   0x00000700U
-#define RTC_TAFCR_TAMPFREQ_0                 0x00000100U
-#define RTC_TAFCR_TAMPFREQ_1                 0x00000200U
-#define RTC_TAFCR_TAMPFREQ_2                 0x00000400U
-#define RTC_TAFCR_TAMPTS                     0x00000080U
-#define RTC_TAFCR_TAMP2TRG                   0x00000010U
-#define RTC_TAFCR_TAMP2E                     0x00000008U
-#define RTC_TAFCR_TAMPIE                     0x00000004U
-#define RTC_TAFCR_TAMP1TRG                   0x00000002U
-#define RTC_TAFCR_TAMP1E                     0x00000001U
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  0x0F000000U
-#define RTC_ALRMASSR_MASKSS_0                0x01000000U
-#define RTC_ALRMASSR_MASKSS_1                0x02000000U
-#define RTC_ALRMASSR_MASKSS_2                0x04000000U
-#define RTC_ALRMASSR_MASKSS_3                0x08000000U
-#define RTC_ALRMASSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
-#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
-#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
-#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
-#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
-#define RTC_ALRMBSSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           0xFFFFFFFFU
-
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          SD host Interface                                 */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SDIO_POWER register  ******************/
-#define  SDIO_POWER_PWRCTRL                  0x03U               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDIO_POWER_PWRCTRL_0                0x01U               /*!<Bit 0 */
-#define  SDIO_POWER_PWRCTRL_1                0x02U               /*!<Bit 1 */
-
-/******************  Bit definition for SDIO_CLKCR register  ******************/
-#define  SDIO_CLKCR_CLKDIV                   0x00FFU            /*!<Clock divide factor             */
-#define  SDIO_CLKCR_CLKEN                    0x0100U            /*!<Clock enable bit                */
-#define  SDIO_CLKCR_PWRSAV                   0x0200U            /*!<Power saving configuration bit  */
-#define  SDIO_CLKCR_BYPASS                   0x0400U            /*!<Clock divider bypass enable bit */
-
-#define  SDIO_CLKCR_WIDBUS                   0x1800U            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDIO_CLKCR_WIDBUS_0                 0x0800U            /*!<Bit 0 */
-#define  SDIO_CLKCR_WIDBUS_1                 0x1000U            /*!<Bit 1 */
-
-#define  SDIO_CLKCR_NEGEDGE                  0x2000U            /*!<SDIO_CK dephasing selection bit */
-#define  SDIO_CLKCR_HWFC_EN                  0x4000U            /*!<HW Flow Control enable          */
-
-/*******************  Bit definition for SDIO_ARG register  *******************/
-#define  SDIO_ARG_CMDARG                     0xFFFFFFFFU            /*!<Command argument */
-
-/*******************  Bit definition for SDIO_CMD register  *******************/
-#define  SDIO_CMD_CMDINDEX                   0x003FU            /*!<Command Index                               */
-
-#define  SDIO_CMD_WAITRESP                   0x00C0U            /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDIO_CMD_WAITRESP_0                 0x0040U            /*!< Bit 0 */
-#define  SDIO_CMD_WAITRESP_1                 0x0080U            /*!< Bit 1 */
-
-#define  SDIO_CMD_WAITINT                    0x0100U            /*!<CPSM Waits for Interrupt Request                               */
-#define  SDIO_CMD_WAITPEND                   0x0200U            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDIO_CMD_CPSMEN                     0x0400U            /*!<Command path state machine (CPSM) Enable bit                   */
-#define  SDIO_CMD_SDIOSUSPEND                0x0800U            /*!<SD I/O suspend command                                         */
-#define  SDIO_CMD_ENCMDCOMPL                 0x1000U            /*!<Enable CMD completion                                          */
-#define  SDIO_CMD_NIEN                       0x2000U            /*!<Not Interrupt Enable */
-#define  SDIO_CMD_CEATACMD                   0x4000U            /*!<CE-ATA command       */
-
-/*****************  Bit definition for SDIO_RESPCMD register  *****************/
-#define  SDIO_RESPCMD_RESPCMD                0x3FU               /*!<Response command index */
-
-/******************  Bit definition for SDIO_RESP0 register  ******************/
-#define  SDIO_RESP0_CARDSTATUS0              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP1 register  ******************/
-#define  SDIO_RESP1_CARDSTATUS1              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP2 register  ******************/
-#define  SDIO_RESP2_CARDSTATUS2              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP3 register  ******************/
-#define  SDIO_RESP3_CARDSTATUS3              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP4 register  ******************/
-#define  SDIO_RESP4_CARDSTATUS4              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_DTIMER register  *****************/
-#define  SDIO_DTIMER_DATATIME                0xFFFFFFFFU        /*!<Data timeout period. */
-
-/******************  Bit definition for SDIO_DLEN register  *******************/
-#define  SDIO_DLEN_DATALENGTH                0x01FFFFFFU        /*!<Data length value    */
-
-/******************  Bit definition for SDIO_DCTRL register  ******************/
-#define  SDIO_DCTRL_DTEN                     0x0001U            /*!<Data transfer enabled bit         */
-#define  SDIO_DCTRL_DTDIR                    0x0002U            /*!<Data transfer direction selection */
-#define  SDIO_DCTRL_DTMODE                   0x0004U            /*!<Data transfer mode selection      */
-#define  SDIO_DCTRL_DMAEN                    0x0008U            /*!<DMA enabled bit                   */
-
-#define  SDIO_DCTRL_DBLOCKSIZE               0x00F0U            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDIO_DCTRL_DBLOCKSIZE_0             0x0010U            /*!<Bit 0 */
-#define  SDIO_DCTRL_DBLOCKSIZE_1             0x0020U            /*!<Bit 1 */
-#define  SDIO_DCTRL_DBLOCKSIZE_2             0x0040U            /*!<Bit 2 */
-#define  SDIO_DCTRL_DBLOCKSIZE_3             0x0080U            /*!<Bit 3 */
-
-#define  SDIO_DCTRL_RWSTART                  0x0100U            /*!<Read wait start         */
-#define  SDIO_DCTRL_RWSTOP                   0x0200U            /*!<Read wait stop          */
-#define  SDIO_DCTRL_RWMOD                    0x0400U            /*!<Read wait mode          */
-#define  SDIO_DCTRL_SDIOEN                   0x0800U            /*!<SD I/O enable functions */
-
-/******************  Bit definition for SDIO_DCOUNT register  *****************/
-#define  SDIO_DCOUNT_DATACOUNT               0x01FFFFFFU        /*!<Data count value */
-
-/******************  Bit definition for SDIO_STA register  ********************/
-#define  SDIO_STA_CCRCFAIL                   0x00000001U        /*!<Command response received (CRC check failed)  */
-#define  SDIO_STA_DCRCFAIL                   0x00000002U        /*!<Data block sent/received (CRC check failed)   */
-#define  SDIO_STA_CTIMEOUT                   0x00000004U        /*!<Command response timeout                      */
-#define  SDIO_STA_DTIMEOUT                   0x00000008U        /*!<Data timeout                                  */
-#define  SDIO_STA_TXUNDERR                   0x00000010U        /*!<Transmit FIFO underrun error                  */
-#define  SDIO_STA_RXOVERR                    0x00000020U        /*!<Received FIFO overrun error                   */
-#define  SDIO_STA_CMDREND                    0x00000040U        /*!<Command response received (CRC check passed)  */
-#define  SDIO_STA_CMDSENT                    0x00000080U        /*!<Command sent (no response required)           */
-#define  SDIO_STA_DATAEND                    0x00000100U        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
-#define  SDIO_STA_STBITERR                   0x00000200U        /*!<Start bit not detected on all data signals in wide bus mode */
-#define  SDIO_STA_DBCKEND                    0x00000400U        /*!<Data block sent/received (CRC check passed)   */
-#define  SDIO_STA_CMDACT                     0x00000800U        /*!<Command transfer in progress                  */
-#define  SDIO_STA_TXACT                      0x00001000U        /*!<Data transmit in progress                     */
-#define  SDIO_STA_RXACT                      0x00002000U        /*!<Data receive in progress                      */
-#define  SDIO_STA_TXFIFOHE                   0x00004000U        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDIO_STA_RXFIFOHF                   0x00008000U        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDIO_STA_TXFIFOF                    0x00010000U        /*!<Transmit FIFO full                            */
-#define  SDIO_STA_RXFIFOF                    0x00020000U        /*!<Receive FIFO full                             */
-#define  SDIO_STA_TXFIFOE                    0x00040000U        /*!<Transmit FIFO empty                           */
-#define  SDIO_STA_RXFIFOE                    0x00080000U        /*!<Receive FIFO empty                            */
-#define  SDIO_STA_TXDAVL                     0x00100000U        /*!<Data available in transmit FIFO               */
-#define  SDIO_STA_RXDAVL                     0x00200000U        /*!<Data available in receive FIFO                */
-#define  SDIO_STA_SDIOIT                     0x00400000U        /*!<SDIO interrupt received                       */
-#define  SDIO_STA_CEATAEND                   0x00800000U        /*!<CE-ATA command completion signal received for CMD61 */
-
-/*******************  Bit definition for SDIO_ICR register  *******************/
-#define  SDIO_ICR_CCRCFAILC                  0x00000001U        /*!<CCRCFAIL flag clear bit */
-#define  SDIO_ICR_DCRCFAILC                  0x00000002U        /*!<DCRCFAIL flag clear bit */
-#define  SDIO_ICR_CTIMEOUTC                  0x00000004U        /*!<CTIMEOUT flag clear bit */
-#define  SDIO_ICR_DTIMEOUTC                  0x00000008U        /*!<DTIMEOUT flag clear bit */
-#define  SDIO_ICR_TXUNDERRC                  0x00000010U        /*!<TXUNDERR flag clear bit */
-#define  SDIO_ICR_RXOVERRC                   0x00000020U        /*!<RXOVERR flag clear bit  */
-#define  SDIO_ICR_CMDRENDC                   0x00000040U        /*!<CMDREND flag clear bit  */
-#define  SDIO_ICR_CMDSENTC                   0x00000080U        /*!<CMDSENT flag clear bit  */
-#define  SDIO_ICR_DATAENDC                   0x00000100U        /*!<DATAEND flag clear bit  */
-#define  SDIO_ICR_STBITERRC                  0x00000200U        /*!<STBITERR flag clear bit */
-#define  SDIO_ICR_DBCKENDC                   0x00000400U        /*!<DBCKEND flag clear bit  */
-#define  SDIO_ICR_SDIOITC                    0x00400000U        /*!<SDIOIT flag clear bit   */
-#define  SDIO_ICR_CEATAENDC                  0x00800000U        /*!<CEATAEND flag clear bit */
-
-/******************  Bit definition for SDIO_MASK register  *******************/
-#define  SDIO_MASK_CCRCFAILIE                0x00000001U        /*!<Command CRC Fail Interrupt Enable          */
-#define  SDIO_MASK_DCRCFAILIE                0x00000002U        /*!<Data CRC Fail Interrupt Enable             */
-#define  SDIO_MASK_CTIMEOUTIE                0x00000004U        /*!<Command TimeOut Interrupt Enable           */
-#define  SDIO_MASK_DTIMEOUTIE                0x00000008U        /*!<Data TimeOut Interrupt Enable              */
-#define  SDIO_MASK_TXUNDERRIE                0x00000010U        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
-#define  SDIO_MASK_RXOVERRIE                 0x00000020U        /*!<Rx FIFO OverRun Error Interrupt Enable     */
-#define  SDIO_MASK_CMDRENDIE                 0x00000040U        /*!<Command Response Received Interrupt Enable */
-#define  SDIO_MASK_CMDSENTIE                 0x00000080U        /*!<Command Sent Interrupt Enable              */
-#define  SDIO_MASK_DATAENDIE                 0x00000100U        /*!<Data End Interrupt Enable                  */
-#define  SDIO_MASK_STBITERRIE                0x00000200U        /*!<Start Bit Error Interrupt Enable           */
-#define  SDIO_MASK_DBCKENDIE                 0x00000400U        /*!<Data Block End Interrupt Enable            */
-#define  SDIO_MASK_CMDACTIE                  0x00000800U        /*!<CCommand Acting Interrupt Enable           */
-#define  SDIO_MASK_TXACTIE                   0x00001000U        /*!<Data Transmit Acting Interrupt Enable      */
-#define  SDIO_MASK_RXACTIE                   0x00002000U        /*!<Data receive acting interrupt enabled      */
-#define  SDIO_MASK_TXFIFOHEIE                0x00004000U        /*!<Tx FIFO Half Empty interrupt Enable        */
-#define  SDIO_MASK_RXFIFOHFIE                0x00008000U        /*!<Rx FIFO Half Full interrupt Enable         */
-#define  SDIO_MASK_TXFIFOFIE                 0x00010000U        /*!<Tx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_RXFIFOFIE                 0x00020000U        /*!<Rx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_TXFIFOEIE                 0x00040000U        /*!<Tx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_RXFIFOEIE                 0x00080000U        /*!<Rx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_TXDAVLIE                  0x00100000U        /*!<Data available in Tx FIFO interrupt Enable */
-#define  SDIO_MASK_RXDAVLIE                  0x00200000U        /*!<Data available in Rx FIFO interrupt Enable */
-#define  SDIO_MASK_SDIOITIE                  0x00400000U        /*!<SDIO Mode Interrupt Received interrupt Enable */
-#define  SDIO_MASK_CEATAENDIE                0x00800000U        /*!<CE-ATA command completion signal received Interrupt Enable */
-
-/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
-#define  SDIO_FIFOCNT_FIFOCOUNT              0x00FFFFFFU        /*!<Remaining number of words to be written to or read from the FIFO */
-
-/******************  Bit definition for SDIO_FIFO register  *******************/
-#define  SDIO_FIFO_FIFODATA                  0xFFFFFFFFU        /*!<Receive and transmit FIFO data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        0x00000001U            /*!<Clock Phase      */
-#define  SPI_CR1_CPOL                        0x00000002U            /*!<Clock Polarity   */
-#define  SPI_CR1_MSTR                        0x00000004U            /*!<Master Selection */
-
-#define  SPI_CR1_BR                          0x00000038U            /*!<BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        0x00000008U            /*!<Bit 0 */
-#define  SPI_CR1_BR_1                        0x00000010U            /*!<Bit 1 */
-#define  SPI_CR1_BR_2                        0x00000020U            /*!<Bit 2 */
-
-#define  SPI_CR1_SPE                         0x00000040U            /*!<SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    0x00000080U            /*!<Frame Format                        */
-#define  SPI_CR1_SSI                         0x00000100U            /*!<Internal slave select               */
-#define  SPI_CR1_SSM                         0x00000200U            /*!<Software slave management           */
-#define  SPI_CR1_RXONLY                      0x00000400U            /*!<Receive only                        */
-#define  SPI_CR1_DFF                         0x00000800U            /*!<Data Frame Format                   */
-#define  SPI_CR1_CRCNEXT                     0x00001000U            /*!<Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       0x00002000U            /*!<Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      0x00004000U            /*!<Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    0x00008000U            /*!<Bidirectional data mode enable      */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     0x00000001U               /*!<Rx Buffer DMA Enable                 */
-#define  SPI_CR2_TXDMAEN                     0x00000002U               /*!<Tx Buffer DMA Enable                 */
-#define  SPI_CR2_SSOE                        0x00000004U               /*!<SS Output Enable                     */
-#define  SPI_CR2_FRF                         0x00000010U               /*!<Frame Format                         */
-#define  SPI_CR2_ERRIE                       0x00000020U               /*!<Error Interrupt Enable               */
-#define  SPI_CR2_RXNEIE                      0x00000040U               /*!<RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       0x00000080U               /*!<Tx buffer Empty Interrupt Enable     */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         0x00000001U               /*!<Receive buffer Not Empty */
-#define  SPI_SR_TXE                          0x00000002U               /*!<Transmit buffer Empty    */
-#define  SPI_SR_CHSIDE                       0x00000004U               /*!<Channel side             */
-#define  SPI_SR_UDR                          0x00000008U               /*!<Underrun flag            */
-#define  SPI_SR_CRCERR                       0x00000010U               /*!<CRC Error flag           */
-#define  SPI_SR_MODF                         0x00000020U               /*!<Mode fault               */
-#define  SPI_SR_OVR                          0x00000040U               /*!<Overrun flag             */
-#define  SPI_SR_BSY                          0x00000080U               /*!<Busy flag                */
-#define  SPI_SR_FRE                          0x00000100U               /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           0x0000FFFFU            /*!<Data Register           */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   0x0000FFFFU            /*!<CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    0x0000FFFFU            /*!<Rx CRC Register         */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    0x0000FFFFU            /*!<Tx CRC Register         */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   0x00000001U            /*!<Channel length (number of bits per audio channel) */
-
-#define  SPI_I2SCFGR_DATLEN                  0x00000006U            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define  SPI_I2SCFGR_DATLEN_0                0x00000002U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                0x00000004U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_CKPOL                   0x00000008U            /*!<steady state clock polarity               */
-
-#define  SPI_I2SCFGR_I2SSTD                  0x00000030U            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U            /*!<PCM frame synchronization                 */
-
-#define  SPI_I2SCFGR_I2SCFG                  0x00000300U            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_I2SE                    0x00000400U            /*!<I2S Enable         */
-#define  SPI_I2SCFGR_I2SMOD                  0x00000800U            /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    0x000000FFU            /*!<I2S Linear prescaler         */
-#define  SPI_I2SPR_ODD                       0x00000100U            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     0x00000200U            /*!<Master Clock Output Enable   */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 SYSCFG                                     */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
-#define SYSCFG_MEMRMP_MEM_MODE          0x00000007U /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        0x00000001U
-#define SYSCFG_MEMRMP_MEM_MODE_1        0x00000002U
-#define SYSCFG_MEMRMP_MEM_MODE_2        0x00000004U
-
-/******************  Bit definition for SYSCFG_PMC register  ******************/
-#define SYSCFG_PMC_MII_RMII_SEL         0x00800000U /*!<Ethernet PHY interface selection */
-/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
-#define SYSCFG_PMC_MII_RMII             SYSCFG_PMC_MII_RMII_SEL
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
-/** 
-  * @brief   EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         0x0003U /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         0x0004U /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         0x0005U /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         0x0006U /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PI         0x0008U /*!<PI[0] pin */
-
-/** 
-  * @brief   EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         0x0030U /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         0x0040U /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         0x0050U /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         0x0060U /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PI         0x0080U /*!<PI[1] pin */
-
-/** 
-  * @brief   EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         0x0300U /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         0x0400U /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         0x0500U /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         0x0600U /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PI         0x0800U /*!<PI[2] pin */
-
-/** 
-  * @brief   EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         0x3000U /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         0x4000U /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         0x5000U /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         0x6000U /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PI         0x8000U /*!<PI[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
-/** 
-  * @brief   EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         0x0003U /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         0x0004U /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         0x0005U /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         0x0006U /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PI         0x0008U /*!<PI[4] pin */
-
-/** 
-  * @brief   EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         0x0030U /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         0x0040U /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         0x0050U /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         0x0060U /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PI         0x0080U /*!<PI[5] pin */
-
-/** 
-  * @brief   EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         0x0300U /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         0x0400U /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         0x0500U /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         0x0600U /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PI         0x0800U /*!<PI[6] pin */
-
-/** 
-  * @brief   EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         0x3000U /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         0x4000U /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         0x5000U /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         0x6000U /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PI         0x8000U /*!<PI[7] pin */
-
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
-           
-/** 
-  * @brief   EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         0x0003U /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         0x0004U /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         0x0005U /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         0x0006U /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PI         0x0008U /*!<PI[8] pin */
-
-/** 
-  * @brief   EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         0x0030U /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         0x0040U /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         0x0050U /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         0x0060U /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PI         0x0080U /*!<PI[9] pin */
-
-/** 
-  * @brief   EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        0x0300U /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        0x0400U /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        0x0500U /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        0x0600U /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PI        0x0800U /*!<PI[10] pin */
-
-/** 
-  * @brief   EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        0x3000U /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        0x4000U /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        0x5000U /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        0x6000U /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PI        0x8000U /*!<PI[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
-/** 
-  * @brief   EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        0x0003U /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        0x0004U /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        0x0005U /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        0x0006U /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
-
-/** 
-  * @brief   EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        0x0030U /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        0x0040U /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        0x0050U /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        0x0060U /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
-
-/** 
-  * @brief   EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        0x0300U /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        0x0400U /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        0x0500U /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        0x0600U /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
-
-/** 
-  * @brief   EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        0x3000U /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        0x4000U /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        0x5000U /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        0x6000U /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
-
-/******************  Bit definition for SYSCFG_CMPCR register  ****************/  
-#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell ready flag */
-#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell power-down */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    TIM                                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
-#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
-#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
-#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
-#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
-
-#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
-
-#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
-
-#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        0x0001U            /*!<Capture/Compare Preloaded Control        */
-#define  TIM_CR2_CCUS                        0x0004U            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        0x0008U            /*!<Capture/Compare DMA Selection            */
-
-#define  TIM_CR2_MMS                         0x0070U            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
-#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
-#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
-#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        0x0007U            /*!<SMS[2:0] bits (Slave mode selection)    */
-#define  TIM_SMCR_SMS_0                      0x0001U            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      0x0002U            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      0x0004U            /*!<Bit 2 */
-
-#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
-#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
-
-#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
-
-#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
-
-#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
-#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
-#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
-#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
-#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
-#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
-#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
-#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
-#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
-#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
-#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
-#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
-#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
-#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
-#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
-#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
-#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
-#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
-#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          0x01U               /*!<Update Generation                         */
-#define  TIM_EGR_CC1G                        0x02U               /*!<Capture/Compare 1 Generation              */
-#define  TIM_EGR_CC2G                        0x04U               /*!<Capture/Compare 2 Generation              */
-#define  TIM_EGR_CC3G                        0x08U               /*!<Capture/Compare 3 Generation              */
-#define  TIM_EGR_CC4G                        0x10U               /*!<Capture/Compare 4 Generation              */
-#define  TIM_EGR_COMG                        0x20U               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          0x40U               /*!<Trigger Generation                        */
-#define  TIM_EGR_BG                          0x80U               /*!<Break Generation                          */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      0x0003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    0x0001U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    0x0002U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC1FE                     0x0004U            /*!<Output Compare 1 Fast enable                 */
-#define  TIM_CCMR1_OC1PE                     0x0008U            /*!<Output Compare 1 Preload enable              */
-
-#define  TIM_CCMR1_OC1M                      0x0070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define  TIM_CCMR1_OC1M_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    0x0040U            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC1CE                     0x0080U            /*!<Output Compare 1Clear Enable                 */
-
-#define  TIM_CCMR1_CC2S                      0x0300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    0x0100U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    0x0200U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC2FE                     0x0400U            /*!<Output Compare 2 Fast enable                 */
-#define  TIM_CCMR1_OC2PE                     0x0800U            /*!<Output Compare 2 Preload enable              */
-
-#define  TIM_CCMR1_OC2M                      0x7000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define  TIM_CCMR1_OC2M_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    0x4000U            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC2CE                     0x8000U            /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      0x0003U            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define  TIM_CCMR2_CC3S_0                    0x0001U            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    0x0002U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC3FE                     0x0004U            /*!<Output Compare 3 Fast enable           */
-#define  TIM_CCMR2_OC3PE                     0x0008U            /*!<Output Compare 3 Preload enable        */
-
-#define  TIM_CCMR2_OC3M                      0x0070U            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    0x0040U            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC3CE                     0x0080U            /*!<Output Compare 3 Clear Enable */
-
-#define  TIM_CCMR2_CC4S                      0x0300U            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    0x0100U            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    0x0200U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC4FE                     0x0400U            /*!<Output Compare 4 Fast enable    */
-#define  TIM_CCMR2_OC4PE                     0x0800U            /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR2_OC4M                      0x7000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    0x4000U            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       0x0001U            /*!<Capture/Compare 1 output enable                 */
-#define  TIM_CCER_CC1P                       0x0002U            /*!<Capture/Compare 1 output Polarity               */
-#define  TIM_CCER_CC1NE                      0x0004U            /*!<Capture/Compare 1 Complementary output enable   */
-#define  TIM_CCER_CC1NP                      0x0008U            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       0x0010U            /*!<Capture/Compare 2 output enable                 */
-#define  TIM_CCER_CC2P                       0x0020U            /*!<Capture/Compare 2 output Polarity               */
-#define  TIM_CCER_CC2NE                      0x0040U            /*!<Capture/Compare 2 Complementary output enable   */
-#define  TIM_CCER_CC2NP                      0x0080U            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       0x0100U            /*!<Capture/Compare 3 output enable                 */
-#define  TIM_CCER_CC3P                       0x0200U            /*!<Capture/Compare 3 output Polarity               */
-#define  TIM_CCER_CC3NE                      0x0400U            /*!<Capture/Compare 3 Complementary output enable   */
-#define  TIM_CCER_CC3NP                      0x0800U            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       0x1000U            /*!<Capture/Compare 4 output enable                 */
-#define  TIM_CCER_CC4P                       0x2000U            /*!<Capture/Compare 4 output Polarity               */
-#define  TIM_CCER_CC4NP                      0x8000U            /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         0xFFU               /*!<Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
-
-/*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        0x00FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      0x0001U            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      0x0002U            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      0x0004U            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      0x0008U            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      0x0010U            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      0x0020U            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      0x0040U            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      0x0080U            /*!<Bit 7 */
-
-#define  TIM_BDTR_LOCK                       0x0300U            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     0x0100U            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     0x0200U            /*!<Bit 1 */
-
-#define  TIM_BDTR_OSSI                       0x0400U            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       0x0800U            /*!<Off-State Selection for Run mode  */
-#define  TIM_BDTR_BKE                        0x1000U            /*!<Break enable                      */
-#define  TIM_BDTR_BKP                        0x2000U            /*!<Break Polarity                    */
-#define  TIM_BDTR_AOE                        0x4000U            /*!<Automatic Output enable           */
-#define  TIM_BDTR_MOE                        0x8000U            /*!<Main Output enable                */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
-
-#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
-#define TIM_OR_ITR1_RMP                      0x0C00U            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
-#define TIM_OR_ITR1_RMP_0                    0x0400U            /*!<Bit 0 */
-#define TIM_OR_ITR1_RMP_1                    0x0800U            /*!<Bit 1 */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*         Universal Synchronous Asynchronous Receiver Transmitter            */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         0x0001U            /*!<Parity Error                 */
-#define  USART_SR_FE                         0x0002U            /*!<Framing Error                */
-#define  USART_SR_NE                         0x0004U            /*!<Noise Error Flag             */
-#define  USART_SR_ORE                        0x0008U            /*!<OverRun Error                */
-#define  USART_SR_IDLE                       0x0010U            /*!<IDLE line detected           */
-#define  USART_SR_RXNE                       0x0020U            /*!<Read Data Register Not Empty */
-#define  USART_SR_TC                         0x0040U            /*!<Transmission Complete        */
-#define  USART_SR_TXE                        0x0080U            /*!<Transmit Data Register Empty */
-#define  USART_SR_LBD                        0x0100U            /*!<LIN Break Detection Flag     */
-#define  USART_SR_CTS                        0x0200U            /*!<CTS Flag                     */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         0x01FFU            /*!<Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_Fraction              0x000FU            /*!<Fraction of USARTDIV */
-#define  USART_BRR_DIV_Mantissa              0xFFF0U            /*!<Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       0x0001U            /*!<Send Break                             */
-#define  USART_CR1_RWU                       0x0002U            /*!<Receiver wakeup                        */
-#define  USART_CR1_RE                        0x0004U            /*!<Receiver Enable                        */
-#define  USART_CR1_TE                        0x0008U            /*!<Transmitter Enable                     */
-#define  USART_CR1_IDLEIE                    0x0010U            /*!<IDLE Interrupt Enable                  */
-#define  USART_CR1_RXNEIE                    0x0020U            /*!<RXNE Interrupt Enable                  */
-#define  USART_CR1_TCIE                      0x0040U            /*!<Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     0x0080U            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PEIE                      0x0100U            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PS                        0x0200U            /*!<Parity Selection                       */
-#define  USART_CR1_PCE                       0x0400U            /*!<Parity Control Enable                  */
-#define  USART_CR1_WAKE                      0x0800U            /*!<Wakeup method                          */
-#define  USART_CR1_M                         0x1000U            /*!<Word length                            */
-#define  USART_CR1_UE                        0x2000U            /*!<USART Enable                           */
-#define  USART_CR1_OVER8                     0x8000U            /*!<USART Oversampling by 8 enable         */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       0x000FU            /*!<Address of the USART node            */
-#define  USART_CR2_LBDL                      0x0020U            /*!<LIN Break Detection Length           */
-#define  USART_CR2_LBDIE                     0x0040U            /*!<LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      0x0100U            /*!<Last Bit Clock pulse                 */
-#define  USART_CR2_CPHA                      0x0200U            /*!<Clock Phase                          */
-#define  USART_CR2_CPOL                      0x0400U            /*!<Clock Polarity                       */
-#define  USART_CR2_CLKEN                     0x0800U            /*!<Clock Enable                         */
-
-#define  USART_CR2_STOP                      0x3000U            /*!<STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    0x1000U            /*!<Bit 0 */
-#define  USART_CR2_STOP_1                    0x2000U            /*!<Bit 1 */
-
-#define  USART_CR2_LINEN                     0x4000U            /*!<LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       0x0001U            /*!<Error Interrupt Enable      */
-#define  USART_CR3_IREN                      0x0002U            /*!<IrDA mode Enable            */
-#define  USART_CR3_IRLP                      0x0004U            /*!<IrDA Low-Power              */
-#define  USART_CR3_HDSEL                     0x0008U            /*!<Half-Duplex Selection       */
-#define  USART_CR3_NACK                      0x0010U            /*!<Smartcard NACK enable       */
-#define  USART_CR3_SCEN                      0x0020U            /*!<Smartcard mode enable       */
-#define  USART_CR3_DMAR                      0x0040U            /*!<DMA Enable Receiver         */
-#define  USART_CR3_DMAT                      0x0080U            /*!<DMA Enable Transmitter      */
-#define  USART_CR3_RTSE                      0x0100U            /*!<RTS Enable                  */
-#define  USART_CR3_CTSE                      0x0200U            /*!<CTS Enable                  */
-#define  USART_CR3_CTSIE                     0x0400U            /*!<CTS Interrupt Enable        */
-#define  USART_CR3_ONEBIT                    0x0800U            /*!<USART One bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      0x00FFU            /*!<PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    0x0001U            /*!<Bit 0 */
-#define  USART_GTPR_PSC_1                    0x0002U            /*!<Bit 1 */
-#define  USART_GTPR_PSC_2                    0x0004U            /*!<Bit 2 */
-#define  USART_GTPR_PSC_3                    0x0008U            /*!<Bit 3 */
-#define  USART_GTPR_PSC_4                    0x0010U            /*!<Bit 4 */
-#define  USART_GTPR_PSC_5                    0x0020U            /*!<Bit 5 */
-#define  USART_GTPR_PSC_6                    0x0040U            /*!<Bit 6 */
-#define  USART_GTPR_PSC_7                    0x0080U            /*!<Bit 7 */
-
-#define  USART_GTPR_GT                       0xFF00U            /*!<Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Window WATCHDOG                                 */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           0x7FU               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T_0                         0x01U               /*!<Bit 0 */
-#define  WWDG_CR_T_1                         0x02U               /*!<Bit 1 */
-#define  WWDG_CR_T_2                         0x04U               /*!<Bit 2 */
-#define  WWDG_CR_T_3                         0x08U               /*!<Bit 3 */
-#define  WWDG_CR_T_4                         0x10U               /*!<Bit 4 */
-#define  WWDG_CR_T_5                         0x20U               /*!<Bit 5 */
-#define  WWDG_CR_T_6                         0x40U               /*!<Bit 6 */
-/* Legacy defines */
-#define  WWDG_CR_T0                          WWDG_CR_T_0
-#define  WWDG_CR_T1                          WWDG_CR_T_1
-#define  WWDG_CR_T2                          WWDG_CR_T_2
-#define  WWDG_CR_T3                          WWDG_CR_T_3
-#define  WWDG_CR_T4                          WWDG_CR_T_4
-#define  WWDG_CR_T5                          WWDG_CR_T_5
-#define  WWDG_CR_T6                          WWDG_CR_T_6
-
-#define  WWDG_CR_WDGA                        0x80U               /*!<Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          0x007FU            /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W_0                        0x0001U            /*!<Bit 0 */
-#define  WWDG_CFR_W_1                        0x0002U            /*!<Bit 1 */
-#define  WWDG_CFR_W_2                        0x0004U            /*!<Bit 2 */
-#define  WWDG_CFR_W_3                        0x0008U            /*!<Bit 3 */
-#define  WWDG_CFR_W_4                        0x0010U            /*!<Bit 4 */
-#define  WWDG_CFR_W_5                        0x0020U            /*!<Bit 5 */
-#define  WWDG_CFR_W_6                        0x0040U            /*!<Bit 6 */
-/* Legacy defines */
-#define  WWDG_CFR_W0                         WWDG_CFR_W_0
-#define  WWDG_CFR_W1                         WWDG_CFR_W_1
-#define  WWDG_CFR_W2                         WWDG_CFR_W_2
-#define  WWDG_CFR_W3                         WWDG_CFR_W_3
-#define  WWDG_CFR_W4                         WWDG_CFR_W_4
-#define  WWDG_CFR_W5                         WWDG_CFR_W_5
-#define  WWDG_CFR_W6                         WWDG_CFR_W_6
-
-#define  WWDG_CFR_WDGTB                      0x0180U            /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB_0                    0x0080U            /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB_1                    0x0100U            /*!<Bit 1 */
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
-
-#define  WWDG_CFR_EWI                        0x0200U            /*!<Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        0x01U               /*!<Early Wakeup Interrupt Flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                DBG                                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
-#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
-
-/********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
-#define  DBGMCU_CR_DBG_STOP                  0x00000002U
-#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
-#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
-
-#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
-#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U/*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U/*!<Bit 1 */
-
-/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            0x00000001U
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            0x00000002U
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            0x00000004U
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            0x00000020U
-#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           0x00000040U
-#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           0x00000080U
-#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           0x00000100U
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
-#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
-/* Old IWDGSTOP bit definition, maintained for legacy purpose */
-#define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
-
-/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        0x00000001U
-#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        0x00000002U
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        0x00010000U
-#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       0x00020000U
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       0x00040000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                Ethernet MAC Registers bits definitions                     */
-/*                                                                            */
-/******************************************************************************/
-/* Bit definition for Ethernet MAC Control Register register */
-#define ETH_MACCR_WD      0x00800000U  /* Watchdog disable */
-#define ETH_MACCR_JD      0x00400000U  /* Jabber disable */
-#define ETH_MACCR_IFG     0x000E0000U  /* Inter-frame gap */
-#define ETH_MACCR_IFG_96Bit     0x00000000U  /* Minimum IFG between frames during transmission is 96Bit */
-  #define ETH_MACCR_IFG_88Bit     0x00020000U  /* Minimum IFG between frames during transmission is 88Bit */
-  #define ETH_MACCR_IFG_80Bit     0x00040000U  /* Minimum IFG between frames during transmission is 80Bit */
-  #define ETH_MACCR_IFG_72Bit     0x00060000U  /* Minimum IFG between frames during transmission is 72Bit */
-  #define ETH_MACCR_IFG_64Bit     0x00080000U  /* Minimum IFG between frames during transmission is 64Bit */        
-  #define ETH_MACCR_IFG_56Bit     0x000A0000U  /* Minimum IFG between frames during transmission is 56Bit */
-  #define ETH_MACCR_IFG_48Bit     0x000C0000U  /* Minimum IFG between frames during transmission is 48Bit */
-  #define ETH_MACCR_IFG_40Bit     0x000E0000U  /* Minimum IFG between frames during transmission is 40Bit */              
-#define ETH_MACCR_CSD     0x00010000U  /* Carrier sense disable (during transmission) */
-#define ETH_MACCR_FES     0x00004000U  /* Fast ethernet speed */
-#define ETH_MACCR_ROD     0x00002000U  /* Receive own disable */
-#define ETH_MACCR_LM      0x00001000U  /* loopback mode */
-#define ETH_MACCR_DM      0x00000800U  /* Duplex mode */
-#define ETH_MACCR_IPCO    0x00000400U  /* IP Checksum offload */
-#define ETH_MACCR_RD      0x00000200U  /* Retry disable */
-#define ETH_MACCR_APCS    0x00000080U  /* Automatic Pad/CRC stripping */
-#define ETH_MACCR_BL      0x00000060U  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
-                                                       a transmission attempt during retries after a collision: 0 =< r <2^k */
-  #define ETH_MACCR_BL_10    0x00000000U  /* k = min (n, 10) */
-  #define ETH_MACCR_BL_8     0x00000020U  /* k = min (n, 8) */
-  #define ETH_MACCR_BL_4     0x00000040U  /* k = min (n, 4) */
-  #define ETH_MACCR_BL_1     0x00000060U  /* k = min (n, 1) */ 
-#define ETH_MACCR_DC      0x00000010U  /* Defferal check */
-#define ETH_MACCR_TE      0x00000008U  /* Transmitter enable */
-#define ETH_MACCR_RE      0x00000004U  /* Receiver enable */
-
-/* Bit definition for Ethernet MAC Frame Filter Register */
-#define ETH_MACFFR_RA     0x80000000U  /* Receive all */ 
-#define ETH_MACFFR_HPF    0x00000400U  /* Hash or perfect filter */ 
-#define ETH_MACFFR_SAF    0x00000200U  /* Source address filter enable */ 
-#define ETH_MACFFR_SAIF   0x00000100U  /* SA inverse filtering */ 
-#define ETH_MACFFR_PCF    0x000000C0U  /* Pass control frames: 3 cases */
-  #define ETH_MACFFR_PCF_BlockAll                0x00000040U  /* MAC filters all control frames from reaching the application */
-  #define ETH_MACFFR_PCF_ForwardAll              0x00000080U  /* MAC forwards all control frames to application even if they fail the Address Filter */
-  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U  /* MAC forwards control frames that pass the Address Filter. */ 
-#define ETH_MACFFR_BFD    0x00000020U  /* Broadcast frame disable */ 
-#define ETH_MACFFR_PAM    0x00000010U  /* Pass all mutlicast */ 
-#define ETH_MACFFR_DAIF   0x00000008U  /* DA Inverse filtering */ 
-#define ETH_MACFFR_HM     0x00000004U  /* Hash multicast */ 
-#define ETH_MACFFR_HU     0x00000002U  /* Hash unicast */
-#define ETH_MACFFR_PM     0x00000001U  /* Promiscuous mode */
-
-/* Bit definition for Ethernet MAC Hash Table High Register */
-#define ETH_MACHTHR_HTH   0xFFFFFFFFU  /* Hash table high */
-
-/* Bit definition for Ethernet MAC Hash Table Low Register */
-#define ETH_MACHTLR_HTL   0xFFFFFFFFU  /* Hash table low */
-
-/* Bit definition for Ethernet MAC MII Address Register */
-#define ETH_MACMIIAR_PA   0x0000F800U  /* Physical layer address */ 
-#define ETH_MACMIIAR_MR   0x000007C0U  /* MII register in the selected PHY */ 
-#define ETH_MACMIIAR_CR   0x0000001CU  /* CR clock range: 6 cases */ 
-  #define ETH_MACMIIAR_CR_Div42   0x00000000U  /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
-  #define ETH_MACMIIAR_CR_Div62   0x00000004U  /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
-  #define ETH_MACMIIAR_CR_Div16   0x00000008U  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
-  #define ETH_MACMIIAR_CR_Div26   0x0000000CU  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
-  #define ETH_MACMIIAR_CR_Div102  0x00000010U  /* HCLK:150-168 MHz; MDC clock= HCLK/102 */  
-#define ETH_MACMIIAR_MW   0x00000002U  /* MII write */ 
-#define ETH_MACMIIAR_MB   0x00000001U  /* MII busy */ 
-  
-/* Bit definition for Ethernet MAC MII Data Register */
-#define ETH_MACMIIDR_MD   0x0000FFFFU  /* MII data: read/write data from/to PHY */
-
-/* Bit definition for Ethernet MAC Flow Control Register */
-#define ETH_MACFCR_PT     0xFFFF0000U  /* Pause time */
-#define ETH_MACFCR_ZQPD   0x00000080U  /* Zero-quanta pause disable */
-#define ETH_MACFCR_PLT    0x00000030U  /* Pause low threshold: 4 cases */
-  #define ETH_MACFCR_PLT_Minus4   0x00000000U  /* Pause time minus 4 slot times */
-  #define ETH_MACFCR_PLT_Minus28  0x00000010U  /* Pause time minus 28 slot times */
-  #define ETH_MACFCR_PLT_Minus144 0x00000020U  /* Pause time minus 144 slot times */
-  #define ETH_MACFCR_PLT_Minus256 0x00000030U  /* Pause time minus 256 slot times */      
-#define ETH_MACFCR_UPFD   0x00000008U  /* Unicast pause frame detect */
-#define ETH_MACFCR_RFCE   0x00000004U  /* Receive flow control enable */
-#define ETH_MACFCR_TFCE   0x00000002U  /* Transmit flow control enable */
-#define ETH_MACFCR_FCBBPA 0x00000001U  /* Flow control busy/backpressure activate */
-
-/* Bit definition for Ethernet MAC VLAN Tag Register */
-#define ETH_MACVLANTR_VLANTC 0x00010000U  /* 12-bit VLAN tag comparison */
-#define ETH_MACVLANTR_VLANTI 0x0000FFFFU  /* VLAN tag identifier (for receive frames) */
-
-/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ 
-#define ETH_MACRWUFFR_D   0xFFFFFFFFU  /* Wake-up frame filter register data */
-/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
-   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
-/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
-   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
-   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
-   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
-   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - 
-                              RSVD - Filter1 Command - RSVD - Filter0 Command
-   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
-   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
-   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
-
-/* Bit definition for Ethernet MAC PMT Control and Status Register */ 
-#define ETH_MACPMTCSR_WFFRPR 0x80000000U  /* Wake-Up Frame Filter Register Pointer Reset */
-#define ETH_MACPMTCSR_GU     0x00000200U  /* Global Unicast */
-#define ETH_MACPMTCSR_WFR    0x00000040U  /* Wake-Up Frame Received */
-#define ETH_MACPMTCSR_MPR    0x00000020U  /* Magic Packet Received */
-#define ETH_MACPMTCSR_WFE    0x00000004U  /* Wake-Up Frame Enable */
-#define ETH_MACPMTCSR_MPE    0x00000002U  /* Magic Packet Enable */
-#define ETH_MACPMTCSR_PD     0x00000001U  /* Power Down */
-
-/* Bit definition for Ethernet MAC Status Register */
-#define ETH_MACSR_TSTS      0x00000200U  /* Time stamp trigger status */
-#define ETH_MACSR_MMCTS     0x00000040U  /* MMC transmit status */
-#define ETH_MACSR_MMMCRS    0x00000020U  /* MMC receive status */
-#define ETH_MACSR_MMCS      0x00000010U  /* MMC status */
-#define ETH_MACSR_PMTS      0x00000008U  /* PMT status */
-
-/* Bit definition for Ethernet MAC Interrupt Mask Register */
-#define ETH_MACIMR_TSTIM     0x00000200U  /* Time stamp trigger interrupt mask */
-#define ETH_MACIMR_PMTIM     0x00000008U  /* PMT interrupt mask */
-
-/* Bit definition for Ethernet MAC Address0 High Register */
-#define ETH_MACA0HR_MACA0H   0x0000FFFFU  /* MAC address0 high */
-
-/* Bit definition for Ethernet MAC Address0 Low Register */
-#define ETH_MACA0LR_MACA0L   0xFFFFFFFFU  /* MAC address0 low */
-
-/* Bit definition for Ethernet MAC Address1 High Register */
-#define ETH_MACA1HR_AE       0x80000000U  /* Address enable */
-#define ETH_MACA1HR_SA       0x40000000U  /* Source address */
-#define ETH_MACA1HR_MBC      0x3F000000U  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
-  #define ETH_MACA1HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA1HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA1HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA1HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA1HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA1HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [7:0] */ 
-#define ETH_MACA1HR_MACA1H   0x0000FFFFU  /* MAC address1 high */
-
-/* Bit definition for Ethernet MAC Address1 Low Register */
-#define ETH_MACA1LR_MACA1L   0xFFFFFFFFU  /* MAC address1 low */
-
-/* Bit definition for Ethernet MAC Address2 High Register */
-#define ETH_MACA2HR_AE       0x80000000U  /* Address enable */
-#define ETH_MACA2HR_SA       0x40000000U  /* Source address */
-#define ETH_MACA2HR_MBC      0x3F000000U  /* Mask byte control */
-  #define ETH_MACA2HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA2HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA2HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA2HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA2HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA2HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA2HR_MACA2H   0x0000FFFFU  /* MAC address1 high */
-
-/* Bit definition for Ethernet MAC Address2 Low Register */
-#define ETH_MACA2LR_MACA2L   0xFFFFFFFFU  /* MAC address2 low */
-
-/* Bit definition for Ethernet MAC Address3 High Register */
-#define ETH_MACA3HR_AE       0x80000000U  /* Address enable */
-#define ETH_MACA3HR_SA       0x40000000U  /* Source address */
-#define ETH_MACA3HR_MBC      0x3F000000U  /* Mask byte control */
-  #define ETH_MACA3HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA3HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA3HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA3HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA3HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA3HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA3HR_MACA3H   0x0000FFFFU  /* MAC address3 high */
-
-/* Bit definition for Ethernet MAC Address3 Low Register */
-#define ETH_MACA3LR_MACA3L   0xFFFFFFFFU  /* MAC address3 low */
-
-/******************************************************************************/
-/*                Ethernet MMC Registers bits definition                      */
-/******************************************************************************/
-
-/* Bit definition for Ethernet MMC Contol Register */
-#define ETH_MMCCR_MCFHP      0x00000020U  /* MMC counter Full-Half preset */
-#define ETH_MMCCR_MCP        0x00000010U  /* MMC counter preset */
-#define ETH_MMCCR_MCF        0x00000008U  /* MMC Counter Freeze */
-#define ETH_MMCCR_ROR        0x00000004U  /* Reset on Read */
-#define ETH_MMCCR_CSR        0x00000002U  /* Counter Stop Rollover */
-#define ETH_MMCCR_CR         0x00000001U  /* Counters Reset */
-
-/* Bit definition for Ethernet MMC Receive Interrupt Register */
-#define ETH_MMCRIR_RGUFS     0x00020000U  /* Set when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIR_RFAES     0x00000040U  /* Set when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIR_RFCES     0x00000020U  /* Set when Rx crc error counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmit Interrupt Register */
-#define ETH_MMCTIR_TGFS      0x00200000U  /* Set when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFMSCS   0x00008000U  /* Set when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFSCS    0x00004000U  /* Set when Tx good single col counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
-#define ETH_MMCRIMR_RGUFM    0x00020000U  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFAEM    0x00000040U  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFCEM    0x00000020U  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
-#define ETH_MMCTIMR_TGFM     0x00200000U  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFMSCM  0x00008000U  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFSCM   0x00004000U  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
-#define ETH_MMCTGFSCCR_TGFSCC     0xFFFFFFFFU  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
-#define ETH_MMCTGFMSCCR_TGFMSCC   0xFFFFFFFFU  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
-#define ETH_MMCTGFCR_TGFC    0xFFFFFFFFU  /* Number of good frames transmitted. */
-
-/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
-#define ETH_MMCRFCECR_RFCEC  0xFFFFFFFFU  /* Number of frames received with CRC error. */
-
-/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
-#define ETH_MMCRFAECR_RFAEC  0xFFFFFFFFU  /* Number of frames received with alignment (dribble) error */
-
-/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
-#define ETH_MMCRGUFCR_RGUFC  0xFFFFFFFFU  /* Number of good unicast frames received. */
-
-/******************************************************************************/
-/*               Ethernet PTP Registers bits definition                       */
-/******************************************************************************/
-
-/* Bit definition for Ethernet PTP Time Stamp Contol Register */
-#define ETH_PTPTSCR_TSCNT       0x00030000U  /* Time stamp clock node type */
-#define ETH_PTPTSSR_TSSMRME     0x00008000U  /* Time stamp snapshot for message relevant to master enable */
-#define ETH_PTPTSSR_TSSEME      0x00004000U  /* Time stamp snapshot for event message enable */
-#define ETH_PTPTSSR_TSSIPV4FE   0x00002000U  /* Time stamp snapshot for IPv4 frames enable */
-#define ETH_PTPTSSR_TSSIPV6FE   0x00001000U  /* Time stamp snapshot for IPv6 frames enable */
-#define ETH_PTPTSSR_TSSPTPOEFE  0x00000800U  /* Time stamp snapshot for PTP over ethernet frames enable */
-#define ETH_PTPTSSR_TSPTPPSV2E  0x00000400U  /* Time stamp PTP packet snooping for version2 format enable */
-#define ETH_PTPTSSR_TSSSR       0x00000200U  /* Time stamp Sub-seconds rollover */
-#define ETH_PTPTSSR_TSSARFE     0x00000100U  /* Time stamp snapshot for all received frames enable */
-
-#define ETH_PTPTSCR_TSARU    0x00000020U  /* Addend register update */
-#define ETH_PTPTSCR_TSITE    0x00000010U  /* Time stamp interrupt trigger enable */
-#define ETH_PTPTSCR_TSSTU    0x00000008U  /* Time stamp update */
-#define ETH_PTPTSCR_TSSTI    0x00000004U  /* Time stamp initialize */
-#define ETH_PTPTSCR_TSFCU    0x00000002U  /* Time stamp fine or coarse update */
-#define ETH_PTPTSCR_TSE      0x00000001U  /* Time stamp enable */
-
-/* Bit definition for Ethernet PTP Sub-Second Increment Register */
-#define ETH_PTPSSIR_STSSI    0x000000FFU  /* System time Sub-second increment value */
-
-/* Bit definition for Ethernet PTP Time Stamp High Register */
-#define ETH_PTPTSHR_STS      0xFFFFFFFFU  /* System Time second */
-
-/* Bit definition for Ethernet PTP Time Stamp Low Register */
-#define ETH_PTPTSLR_STPNS    0x80000000U  /* System Time Positive or negative time */
-#define ETH_PTPTSLR_STSS     0x7FFFFFFFU  /* System Time sub-seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp High Update Register */
-#define ETH_PTPTSHUR_TSUS    0xFFFFFFFFU  /* Time stamp update seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
-#define ETH_PTPTSLUR_TSUPNS  0x80000000U  /* Time stamp update Positive or negative time */
-#define ETH_PTPTSLUR_TSUSS   0x7FFFFFFFU  /* Time stamp update sub-seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp Addend Register */
-#define ETH_PTPTSAR_TSA      0xFFFFFFFFU  /* Time stamp addend */
-
-/* Bit definition for Ethernet PTP Target Time High Register */
-#define ETH_PTPTTHR_TTSH     0xFFFFFFFFU  /* Target time stamp high */
-
-/* Bit definition for Ethernet PTP Target Time Low Register */
-#define ETH_PTPTTLR_TTSL     0xFFFFFFFFU  /* Target time stamp low */
-
-/* Bit definition for Ethernet PTP Time Stamp Status Register */
-#define ETH_PTPTSSR_TSTTR    0x00000020U  /* Time stamp target time reached */
-#define ETH_PTPTSSR_TSSO     0x00000010U  /* Time stamp seconds overflow */
-
-/******************************************************************************/
-/*                 Ethernet DMA Registers bits definition                     */
-/******************************************************************************/
-
-/* Bit definition for Ethernet DMA Bus Mode Register */
-#define ETH_DMABMR_AAB       0x02000000U  /* Address-Aligned beats */
-#define ETH_DMABMR_FPM        0x01000000U  /* 4xPBL mode */
-#define ETH_DMABMR_USP       0x00800000U  /* Use separate PBL */
-#define ETH_DMABMR_RDP       0x007E0000U  /* RxDMA PBL */
-  #define ETH_DMABMR_RDP_1Beat    0x00020000U  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
-  #define ETH_DMABMR_RDP_2Beat    0x00040000U  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
-  #define ETH_DMABMR_RDP_4Beat    0x00080000U  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-  #define ETH_DMABMR_RDP_8Beat    0x00100000U  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-  #define ETH_DMABMR_RDP_16Beat   0x00200000U  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-  #define ETH_DMABMR_RDP_32Beat   0x00400000U  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */                
-  #define ETH_DMABMR_RDP_4xPBL_4Beat   0x01020000U  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-  #define ETH_DMABMR_RDP_4xPBL_8Beat   0x01040000U  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-  #define ETH_DMABMR_RDP_4xPBL_16Beat  0x01080000U  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-  #define ETH_DMABMR_RDP_4xPBL_32Beat  0x01100000U  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
-  #define ETH_DMABMR_RDP_4xPBL_64Beat  0x01200000U  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
-  #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */  
-#define ETH_DMABMR_FB        0x00010000U  /* Fixed Burst */
-#define ETH_DMABMR_RTPR      0x0000C000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_1_1     0x00000000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_2_1     0x00004000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_3_1     0x00008000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_4_1     0x0000C000U  /* Rx Tx priority ratio */  
-#define ETH_DMABMR_PBL    0x00003F00U  /* Programmable burst length */
-  #define ETH_DMABMR_PBL_1Beat    0x00000100U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
-  #define ETH_DMABMR_PBL_2Beat    0x00000200U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
-  #define ETH_DMABMR_PBL_4Beat    0x00000400U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-  #define ETH_DMABMR_PBL_8Beat    0x00000800U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-  #define ETH_DMABMR_PBL_16Beat   0x00001000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-  #define ETH_DMABMR_PBL_32Beat   0x00002000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
-  #define ETH_DMABMR_PBL_4xPBL_4Beat   0x01000100U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-  #define ETH_DMABMR_PBL_4xPBL_8Beat   0x01000200U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-  #define ETH_DMABMR_PBL_4xPBL_16Beat  0x01000400U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-  #define ETH_DMABMR_PBL_4xPBL_32Beat  0x01000800U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
-  #define ETH_DMABMR_PBL_4xPBL_64Beat  0x01001000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
-  #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
-#define ETH_DMABMR_EDE       0x00000080U  /* Enhanced Descriptor Enable */
-#define ETH_DMABMR_DSL       0x0000007CU  /* Descriptor Skip Length */
-#define ETH_DMABMR_DA        0x00000002U  /* DMA arbitration scheme */
-#define ETH_DMABMR_SR        0x00000001U  /* Software reset */
-
-/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
-#define ETH_DMATPDR_TPD      0xFFFFFFFFU  /* Transmit poll demand */
-
-/* Bit definition for Ethernet DMA Receive Poll Demand Register */
-#define ETH_DMARPDR_RPD      0xFFFFFFFFU  /* Receive poll demand  */
-
-/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
-#define ETH_DMARDLAR_SRL     0xFFFFFFFFU  /* Start of receive list */
-
-/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
-#define ETH_DMATDLAR_STL     0xFFFFFFFFU  /* Start of transmit list */
-
-/* Bit definition for Ethernet DMA Status Register */
-#define ETH_DMASR_TSTS       0x20000000U  /* Time-stamp trigger status */
-#define ETH_DMASR_PMTS       0x10000000U  /* PMT status */
-#define ETH_DMASR_MMCS       0x08000000U  /* MMC status */
-#define ETH_DMASR_EBS        0x03800000U  /* Error bits status */
-  /* combination with EBS[2:0] for GetFlagStatus function */
-  #define ETH_DMASR_EBS_DescAccess      0x02000000U  /* Error bits 0-data buffer, 1-desc. access */
-  #define ETH_DMASR_EBS_ReadTransf      0x01000000U  /* Error bits 0-write trnsf, 1-read transfr */
-  #define ETH_DMASR_EBS_DataTransfTx    0x00800000U  /* Error bits 0-Rx DMA, 1-Tx DMA */
-#define ETH_DMASR_TPS         0x00700000U  /* Transmit process state */
-  #define ETH_DMASR_TPS_Stopped         0x00000000U  /* Stopped - Reset or Stop Tx Command issued  */
-  #define ETH_DMASR_TPS_Fetching        0x00100000U  /* Running - fetching the Tx descriptor */
-  #define ETH_DMASR_TPS_Waiting         0x00200000U  /* Running - waiting for status */
-  #define ETH_DMASR_TPS_Reading         0x00300000U  /* Running - reading the data from host memory */
-  #define ETH_DMASR_TPS_Suspended       0x00600000U  /* Suspended - Tx Descriptor unavailabe */
-  #define ETH_DMASR_TPS_Closing         0x00700000U  /* Running - closing Rx descriptor */
-#define ETH_DMASR_RPS         0x000E0000U  /* Receive process state */
-  #define ETH_DMASR_RPS_Stopped         0x00000000U  /* Stopped - Reset or Stop Rx Command issued */
-  #define ETH_DMASR_RPS_Fetching        0x00020000U  /* Running - fetching the Rx descriptor */
-  #define ETH_DMASR_RPS_Waiting         0x00060000U  /* Running - waiting for packet */
-  #define ETH_DMASR_RPS_Suspended       0x00080000U  /* Suspended - Rx Descriptor unavailable */
-  #define ETH_DMASR_RPS_Closing         0x000A0000U  /* Running - closing descriptor */
-  #define ETH_DMASR_RPS_Queuing         0x000E0000U  /* Running - queuing the recieve frame into host memory */
-#define ETH_DMASR_NIS        0x00010000U  /* Normal interrupt summary */
-#define ETH_DMASR_AIS        0x00008000U  /* Abnormal interrupt summary */
-#define ETH_DMASR_ERS        0x00004000U  /* Early receive status */
-#define ETH_DMASR_FBES       0x00002000U  /* Fatal bus error status */
-#define ETH_DMASR_ETS        0x00000400U  /* Early transmit status */
-#define ETH_DMASR_RWTS       0x00000200U  /* Receive watchdog timeout status */
-#define ETH_DMASR_RPSS       0x00000100U  /* Receive process stopped status */
-#define ETH_DMASR_RBUS       0x00000080U  /* Receive buffer unavailable status */
-#define ETH_DMASR_RS         0x00000040U  /* Receive status */
-#define ETH_DMASR_TUS        0x00000020U  /* Transmit underflow status */
-#define ETH_DMASR_ROS        0x00000010U  /* Receive overflow status */
-#define ETH_DMASR_TJTS       0x00000008U  /* Transmit jabber timeout status */
-#define ETH_DMASR_TBUS       0x00000004U  /* Transmit buffer unavailable status */
-#define ETH_DMASR_TPSS       0x00000002U  /* Transmit process stopped status */
-#define ETH_DMASR_TS         0x00000001U  /* Transmit status */
-
-/* Bit definition for Ethernet DMA Operation Mode Register */
-#define ETH_DMAOMR_DTCEFD    0x04000000U  /* Disable Dropping of TCP/IP checksum error frames */
-#define ETH_DMAOMR_RSF       0x02000000U  /* Receive store and forward */
-#define ETH_DMAOMR_DFRF      0x01000000U  /* Disable flushing of received frames */
-#define ETH_DMAOMR_TSF       0x00200000U  /* Transmit store and forward */
-#define ETH_DMAOMR_FTF       0x00100000U  /* Flush transmit FIFO */
-#define ETH_DMAOMR_TTC       0x0001C000U  /* Transmit threshold control */
-  #define ETH_DMAOMR_TTC_64Bytes       0x00000000U  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
-  #define ETH_DMAOMR_TTC_128Bytes      0x00004000U  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
-  #define ETH_DMAOMR_TTC_192Bytes      0x00008000U  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
-  #define ETH_DMAOMR_TTC_256Bytes      0x0000C000U  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
-  #define ETH_DMAOMR_TTC_40Bytes       0x00010000U  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
-  #define ETH_DMAOMR_TTC_32Bytes       0x00014000U  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
-  #define ETH_DMAOMR_TTC_24Bytes       0x00018000U  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
-  #define ETH_DMAOMR_TTC_16Bytes       0x0001C000U  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
-#define ETH_DMAOMR_ST        0x00002000U  /* Start/stop transmission command */
-#define ETH_DMAOMR_FEF       0x00000080U  /* Forward error frames */
-#define ETH_DMAOMR_FUGF      0x00000040U  /* Forward undersized good frames */
-#define ETH_DMAOMR_RTC       0x00000018U  /* receive threshold control */
-  #define ETH_DMAOMR_RTC_64Bytes       0x00000000U  /* threshold level of the MTL Receive FIFO is 64 Bytes */
-  #define ETH_DMAOMR_RTC_32Bytes       0x00000008U  /* threshold level of the MTL Receive FIFO is 32 Bytes */
-  #define ETH_DMAOMR_RTC_96Bytes       0x00000010U  /* threshold level of the MTL Receive FIFO is 96 Bytes */
-  #define ETH_DMAOMR_RTC_128Bytes      0x00000018U  /* threshold level of the MTL Receive FIFO is 128 Bytes */
-#define ETH_DMAOMR_OSF       0x00000004U  /* operate on second frame */
-#define ETH_DMAOMR_SR        0x00000002U  /* Start/stop receive */
-
-/* Bit definition for Ethernet DMA Interrupt Enable Register */
-#define ETH_DMAIER_NISE      0x00010000U  /* Normal interrupt summary enable */
-#define ETH_DMAIER_AISE      0x00008000U  /* Abnormal interrupt summary enable */
-#define ETH_DMAIER_ERIE      0x00004000U  /* Early receive interrupt enable */
-#define ETH_DMAIER_FBEIE     0x00002000U  /* Fatal bus error interrupt enable */
-#define ETH_DMAIER_ETIE      0x00000400U  /* Early transmit interrupt enable */
-#define ETH_DMAIER_RWTIE     0x00000200U  /* Receive watchdog timeout interrupt enable */
-#define ETH_DMAIER_RPSIE     0x00000100U  /* Receive process stopped interrupt enable */
-#define ETH_DMAIER_RBUIE     0x00000080U  /* Receive buffer unavailable interrupt enable */
-#define ETH_DMAIER_RIE       0x00000040U  /* Receive interrupt enable */
-#define ETH_DMAIER_TUIE      0x00000020U  /* Transmit Underflow interrupt enable */
-#define ETH_DMAIER_ROIE      0x00000010U  /* Receive Overflow interrupt enable */
-#define ETH_DMAIER_TJTIE     0x00000008U  /* Transmit jabber timeout interrupt enable */
-#define ETH_DMAIER_TBUIE     0x00000004U  /* Transmit buffer unavailable interrupt enable */
-#define ETH_DMAIER_TPSIE     0x00000002U  /* Transmit process stopped interrupt enable */
-#define ETH_DMAIER_TIE       0x00000001U  /* Transmit interrupt enable */
-
-/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
-#define ETH_DMAMFBOCR_OFOC   0x10000000U  /* Overflow bit for FIFO overflow counter */
-#define ETH_DMAMFBOCR_MFA    0x0FFE0000U  /* Number of frames missed by the application */
-#define ETH_DMAMFBOCR_OMFC   0x00010000U  /* Overflow bit for missed frame counter */
-#define ETH_DMAMFBOCR_MFC    0x0000FFFFU  /* Number of frames missed by the controller */
-
-/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
-#define ETH_DMACHTDR_HTDAP   0xFFFFFFFFU  /* Host transmit descriptor address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
-#define ETH_DMACHRDR_HRDAP   0xFFFFFFFFU  /* Host receive descriptor address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
-#define ETH_DMACHTBAR_HTBAP  0xFFFFFFFFU  /* Host transmit buffer address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
-#define ETH_DMACHRBAR_HRBAP  0xFFFFFFFFU  /* Host receive buffer address pointer */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                       USB_OTG			                        */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/
-#define USB_OTG_GOTGCTL_SRQSCS                  0x00000001U            /*!< Session request success */
-#define USB_OTG_GOTGCTL_SRQ                     0x00000002U            /*!< Session request */
-#define USB_OTG_GOTGCTL_HNGSCS                  0x00000100U            /*!< Host negotiation success */
-#define USB_OTG_GOTGCTL_HNPRQ                   0x00000200U            /*!< HNP request */
-#define USB_OTG_GOTGCTL_HSHNPEN                 0x00000400U            /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_DHNPEN                  0x00000800U            /*!< Device HNP enabled */
-#define USB_OTG_GOTGCTL_CIDSTS                  0x00010000U            /*!< Connector ID status */
-#define USB_OTG_GOTGCTL_DBCT                    0x00020000U            /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD                   0x00040000U            /*!< A-session valid */
-#define USB_OTG_GOTGCTL_BSVLD                   0x00080000U            /*!< B-session valid */
-
-/********************  Bit definition forUSB_OTG_HCFG register  ********************/
-
-#define USB_OTG_HCFG_FSLSPCS                 0x00000003U            /*!< FS/LS PHY clock select */
-#define USB_OTG_HCFG_FSLSPCS_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCFG_FSLSPCS_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCFG_FSLSS                   0x00000004U            /*!< FS- and LS-only support */
-
-/********************  Bit definition forUSB_OTG_DCFG register  ********************/
-
-#define USB_OTG_DCFG_DSPD                    0x00000003U            /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                  0x00000001U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DSPD_1                  0x00000002U            /*!<Bit 1 */
-#define USB_OTG_DCFG_NZLSOHSK                0x00000004U            /*!< Nonzero-length status OUT handshake */
-
-#define USB_OTG_DCFG_DAD                     0x000007F0U            /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                   0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DAD_1                   0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCFG_DAD_2                   0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCFG_DAD_3                   0x00000080U            /*!<Bit 3 */
-#define USB_OTG_DCFG_DAD_4                   0x00000100U            /*!<Bit 4 */
-#define USB_OTG_DCFG_DAD_5                   0x00000200U            /*!<Bit 5 */
-#define USB_OTG_DCFG_DAD_6                   0x00000400U            /*!<Bit 6 */
-
-#define USB_OTG_DCFG_PFIVL                   0x00001800U            /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PFIVL_1                 0x00001000U            /*!<Bit 1 */
-
-#define USB_OTG_DCFG_PERSCHIVL               0x03000000U            /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0             0x01000000U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PERSCHIVL_1             0x02000000U            /*!<Bit 1 */
-
-/********************  Bit definition forUSB_OTG_PCGCR register  ********************/
-#define USB_OTG_PCGCR_STPPCLK                 0x00000001U            /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK                0x00000002U            /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP                 0x00000010U            /*!< PHY suspended */
-
-/********************  Bit definition forUSB_OTG_GOTGINT register  ********************/
-#define USB_OTG_GOTGINT_SEDET                   0x00000004U            /*!< Session end detected */
-#define USB_OTG_GOTGINT_SRSSCHG                 0x00000100U            /*!< Session request success status change */
-#define USB_OTG_GOTGINT_HNSSCHG                 0x00000200U            /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET                  0x00020000U            /*!< Host negotiation detected */
-#define USB_OTG_GOTGINT_ADTOCHG                 0x00040000U            /*!< A-device timeout change */
-#define USB_OTG_GOTGINT_DBCDNE                  0x00080000U            /*!< Debounce done */
-
-/********************  Bit definition forUSB_OTG_DCTL register  ********************/
-#define USB_OTG_DCTL_RWUSIG                  0x00000001U            /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS                    0x00000002U            /*!< Soft disconnect */
-#define USB_OTG_DCTL_GINSTS                  0x00000004U            /*!< Global IN NAK status */
-#define USB_OTG_DCTL_GONSTS                  0x00000008U            /*!< Global OUT NAK status */
-
-#define USB_OTG_DCTL_TCTL                    0x00000070U            /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                  0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCTL_TCTL_1                  0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCTL_TCTL_2                  0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCTL_SGINAK                  0x00000080U            /*!< Set global IN NAK */
-#define USB_OTG_DCTL_CGINAK                  0x00000100U            /*!< Clear global IN NAK */
-#define USB_OTG_DCTL_SGONAK                  0x00000200U            /*!< Set global OUT NAK */
-#define USB_OTG_DCTL_CGONAK                  0x00000400U            /*!< Clear global OUT NAK */
-#define USB_OTG_DCTL_POPRGDNE                0x00000800U            /*!< Power-on programming done */
-
-/********************  Bit definition forUSB_OTG_HFIR register  ********************/
-#define USB_OTG_HFIR_FRIVL                   0x0000FFFFU            /*!< Frame interval */
-
-/********************  Bit definition forUSB_OTG_HFNUM register  ********************/
-#define USB_OTG_HFNUM_FRNUM                   0x0000FFFFU            /*!< Frame number */
-#define USB_OTG_HFNUM_FTREM                   0xFFFF0000U            /*!< Frame time remaining */
-
-/********************  Bit definition forUSB_OTG_DSTS register  ********************/
-#define USB_OTG_DSTS_SUSPSTS                 0x00000001U            /*!< Suspend status */
-
-#define USB_OTG_DSTS_ENUMSPD                 0x00000006U            /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_DSTS_ENUMSPD_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_DSTS_EERR                    0x00000008U            /*!< Erratic error */
-#define USB_OTG_DSTS_FNSOF                   0x003FFF00U            /*!< Frame number of the received SOF */
-
-/********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/
-#define USB_OTG_GAHBCFG_GINT                    0x00000001U            /*!< Global interrupt mask */
-
-#define USB_OTG_GAHBCFG_HBSTLEN                 0x0000001EU            /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_GAHBCFG_HBSTLEN_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_GAHBCFG_HBSTLEN_2               0x00000008U            /*!<Bit 2 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3               0x00000010U            /*!<Bit 3 */
-#define USB_OTG_GAHBCFG_DMAEN                   0x00000020U            /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL                 0x00000080U            /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL                0x00000100U            /*!< Periodic TxFIFO empty level */
-
-/********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/
-
-#define USB_OTG_GUSBCFG_TOCAL                   0x00000007U            /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TOCAL_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TOCAL_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_PHYSEL                  0x00000040U            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP                  0x00000100U            /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP                  0x00000200U            /*!< HNP-capable */
-
-#define USB_OTG_GUSBCFG_TRDT                    0x00003C00U            /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                  0x00000400U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TRDT_1                  0x00000800U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TRDT_2                  0x00001000U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_TRDT_3                  0x00002000U            /*!<Bit 3 */
-#define USB_OTG_GUSBCFG_PHYLPCS                 0x00008000U            /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS                0x00020000U            /*!< ULPI FS/LS select */
-#define USB_OTG_GUSBCFG_ULPIAR                  0x00040000U            /*!< ULPI Auto-resume */
-#define USB_OTG_GUSBCFG_ULPICSM                 0x00080000U            /*!< ULPI Clock SuspendM */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD              0x00100000U            /*!< ULPI External VBUS Drive */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI              0x00200000U            /*!< ULPI external VBUS indicator */
-#define USB_OTG_GUSBCFG_TSDPS                   0x00400000U            /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI                    0x00800000U            /*!< Indicator complement */
-#define USB_OTG_GUSBCFG_PTCI                    0x01000000U            /*!< Indicator pass through */
-#define USB_OTG_GUSBCFG_ULPIIPD                 0x02000000U            /*!< ULPI interface protect disable */
-#define USB_OTG_GUSBCFG_FHMOD                   0x20000000U            /*!< Forced host mode */
-#define USB_OTG_GUSBCFG_FDMOD                   0x40000000U            /*!< Forced peripheral mode */
-#define USB_OTG_GUSBCFG_CTXPKT                  0x80000000U            /*!< Corrupt Tx packet */
-
-/********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
-#define USB_OTG_GRSTCTL_CSRST                   0x00000001U            /*!< Core soft reset */
-#define USB_OTG_GRSTCTL_HSRST                   0x00000002U            /*!< HCLK soft reset */
-#define USB_OTG_GRSTCTL_FCRST                   0x00000004U            /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH                 0x00000010U            /*!< RxFIFO flush */
-#define USB_OTG_GRSTCTL_TXFFLSH                 0x00000020U            /*!< TxFIFO flush */
-
-#define USB_OTG_GRSTCTL_TXFNUM                  0x000007C0U            /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                0x00000040U            /*!<Bit 0 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                0x00000080U            /*!<Bit 1 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                0x00000100U            /*!<Bit 2 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                0x00000200U            /*!<Bit 3 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                0x00000400U            /*!<Bit 4 */
-#define USB_OTG_GRSTCTL_DMAREQ                  0x40000000U            /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL                  0x80000000U            /*!< AHB master idle */
-
-/********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/
-#define USB_OTG_DIEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPMSK_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPMSK_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPMSK_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPMSK_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPMSK_BIM                     0x00000200U            /*!< BNA interrupt mask */
-
-/********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/
-#define USB_OTG_HPTXSTS_PTXFSAVL                0x0000FFFFU            /*!< Periodic transmit data FIFO space available */
-
-#define USB_OTG_HPTXSTS_PTXQSAV                 0x00FF0000U            /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0               0x00010000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1               0x00020000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2               0x00040000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3               0x00080000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4               0x00100000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5               0x00200000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6               0x00400000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7               0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_HPTXSTS_PTXQTOP                 0xFF000000U            /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0               0x01000000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1               0x02000000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2               0x04000000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3               0x08000000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4               0x10000000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5               0x20000000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6               0x40000000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7               0x80000000U            /*!<Bit 7 */
-
-/********************  Bit definition forUSB_OTG_HAINT register  ********************/
-#define USB_OTG_HAINT_HAINT                   0x0000FFFFU            /*!< Channel interrupts */
-
-/********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/
-#define USB_OTG_DOEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPMSK_STUPM                   0x00000008U            /*!< SETUP phase done mask */
-#define USB_OTG_DOEPMSK_OTEPDM                  0x00000010U            /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received mask */
-#define USB_OTG_DOEPMSK_OPEM                    0x00000100U            /*!< OUT packet error mask */
-#define USB_OTG_DOEPMSK_BOIM                    0x00000200U            /*!< BNA interrupt mask */
-
-/********************  Bit definition forUSB_OTG_GINTSTS register  ********************/
-#define USB_OTG_GINTSTS_CMOD                    0x00000001U            /*!< Current mode of operation */
-#define USB_OTG_GINTSTS_MMIS                    0x00000002U            /*!< Mode mismatch interrupt */
-#define USB_OTG_GINTSTS_OTGINT                  0x00000004U            /*!< OTG interrupt */
-#define USB_OTG_GINTSTS_SOF                     0x00000008U            /*!< Start of frame */
-#define USB_OTG_GINTSTS_RXFLVL                  0x00000010U            /*!< RxFIFO nonempty */
-#define USB_OTG_GINTSTS_NPTXFE                  0x00000020U            /*!< Nonperiodic TxFIFO empty */
-#define USB_OTG_GINTSTS_GINAKEFF                0x00000040U            /*!< Global IN nonperiodic NAK effective */
-#define USB_OTG_GINTSTS_BOUTNAKEFF              0x00000080U            /*!< Global OUT NAK effective */
-#define USB_OTG_GINTSTS_ESUSP                   0x00000400U            /*!< Early suspend */
-#define USB_OTG_GINTSTS_USBSUSP                 0x00000800U            /*!< USB suspend */
-#define USB_OTG_GINTSTS_USBRST                  0x00001000U            /*!< USB reset */
-#define USB_OTG_GINTSTS_ENUMDNE                 0x00002000U            /*!< Enumeration done */
-#define USB_OTG_GINTSTS_ISOODRP                 0x00004000U            /*!< Isochronous OUT packet dropped interrupt */
-#define USB_OTG_GINTSTS_EOPF                    0x00008000U            /*!< End of periodic frame interrupt */
-#define USB_OTG_GINTSTS_IEPINT                  0x00040000U            /*!< IN endpoint interrupt */
-#define USB_OTG_GINTSTS_OEPINT                  0x00080000U            /*!< OUT endpoint interrupt */
-#define USB_OTG_GINTSTS_IISOIXFR                0x00100000U            /*!< Incomplete isochronous IN transfer */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       0x00200000U            /*!< Incomplete periodic transfer */
-#define USB_OTG_GINTSTS_DATAFSUSP               0x00400000U            /*!< Data fetch suspended */
-#define USB_OTG_GINTSTS_HPRTINT                 0x01000000U            /*!< Host port interrupt */
-#define USB_OTG_GINTSTS_HCINT                   0x02000000U            /*!< Host channels interrupt */
-#define USB_OTG_GINTSTS_PTXFE                   0x04000000U            /*!< Periodic TxFIFO empty */
-#define USB_OTG_GINTSTS_CIDSCHG                 0x10000000U            /*!< Connector ID status change */
-#define USB_OTG_GINTSTS_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt */
-#define USB_OTG_GINTSTS_SRQINT                  0x40000000U            /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT                  0x80000000U            /*!< Resume/remote wakeup detected interrupt */
-
-/********************  Bit definition forUSB_OTG_GINTMSK register  ********************/
-#define USB_OTG_GINTMSK_MMISM                   0x00000002U            /*!< Mode mismatch interrupt mask */
-#define USB_OTG_GINTMSK_OTGINT                  0x00000004U            /*!< OTG interrupt mask */
-#define USB_OTG_GINTMSK_SOFM                    0x00000008U            /*!< Start of frame mask */
-#define USB_OTG_GINTMSK_RXFLVLM                 0x00000010U            /*!< Receive FIFO nonempty mask */
-#define USB_OTG_GINTMSK_NPTXFEM                 0x00000020U            /*!< Nonperiodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_GINAKEFFM               0x00000040U            /*!< Global nonperiodic IN NAK effective mask */
-#define USB_OTG_GINTMSK_GONAKEFFM               0x00000080U            /*!< Global OUT NAK effective mask */
-#define USB_OTG_GINTMSK_ESUSPM                  0x00000400U            /*!< Early suspend mask */
-#define USB_OTG_GINTMSK_USBSUSPM                0x00000800U            /*!< USB suspend mask */
-#define USB_OTG_GINTMSK_USBRST                  0x00001000U            /*!< USB reset mask */
-#define USB_OTG_GINTMSK_ENUMDNEM                0x00002000U            /*!< Enumeration done mask */
-#define USB_OTG_GINTMSK_ISOODRPM                0x00004000U            /*!< Isochronous OUT packet dropped interrupt mask */
-#define USB_OTG_GINTMSK_EOPFM                   0x00008000U            /*!< End of periodic frame interrupt mask */
-#define USB_OTG_GINTMSK_EPMISM                  0x00020000U            /*!< Endpoint mismatch interrupt mask */
-#define USB_OTG_GINTMSK_IEPINT                  0x00040000U            /*!< IN endpoints interrupt mask */
-#define USB_OTG_GINTMSK_OEPINT                  0x00080000U            /*!< OUT endpoints interrupt mask */
-#define USB_OTG_GINTMSK_IISOIXFRM               0x00100000U            /*!< Incomplete isochronous IN transfer mask */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         0x00200000U            /*!< Incomplete periodic transfer mask */
-#define USB_OTG_GINTMSK_FSUSPM                  0x00400000U            /*!< Data fetch suspended mask */
-#define USB_OTG_GINTMSK_PRTIM                   0x01000000U            /*!< Host port interrupt mask */
-#define USB_OTG_GINTMSK_HCIM                    0x02000000U            /*!< Host channels interrupt mask */
-#define USB_OTG_GINTMSK_PTXFEM                  0x04000000U            /*!< Periodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_CIDSCHGM                0x10000000U            /*!< Connector ID status change mask */
-#define USB_OTG_GINTMSK_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt mask */
-#define USB_OTG_GINTMSK_SRQIM                   0x40000000U            /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM                    0x80000000U            /*!< Resume/remote wakeup detected interrupt mask */
-
-/********************  Bit definition forUSB_OTG_DAINT register  ********************/
-#define USB_OTG_DAINT_IEPINT                  0x0000FFFFU            /*!< IN endpoint interrupt bits */
-#define USB_OTG_DAINT_OEPINT                  0xFFFF0000U            /*!< OUT endpoint interrupt bits */
-
-/********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/
-#define USB_OTG_HAINTMSK_HAINTM                  0x0000FFFFU            /*!< Channel interrupt mask */
-
-/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
-#define USB_OTG_GRXSTSP_EPNUM                    0x0000000FU            /*!< IN EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_BCNT                     0x00007FF0U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID                     0x00018000U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS                   0x001E0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/
-#define USB_OTG_DAINTMSK_IEPM                    0x0000FFFFU            /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM                    0xFFFF0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for OTG register  ********************/
-
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition for OTG register  ********************/
-
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/
-#define USB_OTG_GRXFSIZ_RXFD                    0x0000FFFFU            /*!< RxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/
-#define USB_OTG_DVBUSDIS_VBUSDT                  0x0000FFFFU            /*!< Device VBUS discharge time */
-
-/********************  Bit definition for OTG register  ********************/
-#define USB_OTG_NPTXFSA                 0x0000FFFFU            /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD                  0xFFFF0000U            /*!< Nonperiodic TxFIFO depth */
-#define USB_OTG_TX0FSA                  0x0000FFFFU            /*!< Endpoint 0 transmit RAM start address */
-#define USB_OTG_TX0FD                   0xFFFF0000U            /*!< Endpoint 0 TxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
-#define USB_OTG_DVBUSPULSE_DVBUSP                  0x00000FFFU            /*!< Device VBUS pulsing time */
-
-/********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/
-#define USB_OTG_GNPTXSTS_NPTXFSAV                0x0000FFFFU            /*!< Nonperiodic TxFIFO space available */
-
-#define USB_OTG_GNPTXSTS_NPTQXSAV                0x00FF0000U            /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0              0x00010000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1              0x00020000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2              0x00040000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3              0x00080000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4              0x00100000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5              0x00200000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6              0x00400000U            /*!<Bit 6 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7              0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_GNPTXSTS_NPTXQTOP                0x7F000000U            /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0              0x01000000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1              0x02000000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2              0x04000000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3              0x08000000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4              0x10000000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5              0x20000000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6              0x40000000U            /*!<Bit 6 */
-
-/********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/
-#define USB_OTG_DTHRCTL_NONISOTHREN             0x00000001U            /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN                0x00000002U            /*!< ISO IN endpoint threshold enable */
-
-#define USB_OTG_DTHRCTL_TXTHRLEN                0x000007FCU            /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0              0x00000004U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1              0x00000008U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2              0x00000010U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3              0x00000020U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4              0x00000040U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5              0x00000080U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6              0x00000100U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7              0x00000200U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8              0x00000400U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_RXTHREN                 0x00010000U            /*!< Receive threshold enable */
-
-#define USB_OTG_DTHRCTL_RXTHRLEN                0x03FE0000U            /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0              0x00020000U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1              0x00040000U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2              0x00080000U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3              0x00100000U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4              0x00200000U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5              0x00400000U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6              0x00800000U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7              0x01000000U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8              0x02000000U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_ARPEN                   0x08000000U            /*!< Arbiter parking enable */
-
-/********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM               0x0000FFFFU            /*!< IN EP Tx FIFO empty interrupt mask bits */
-
-/********************  Bit definition forUSB_OTG_DEACHINT register  ********************/
-#define USB_OTG_DEACHINT_IEP1INT                 0x00000002U            /*!< IN endpoint 1interrupt bit */
-#define USB_OTG_DEACHINT_OEP1INT                 0x00020000U            /*!< OUT endpoint 1 interrupt bit */
-
-/********************  Bit definition forUSB_OTG_GCCFG register  ********************/
-#define USB_OTG_GCCFG_PWRDWN                  0x00010000U            /*!< Power down */
-#define USB_OTG_GCCFG_I2CPADEN                0x00020000U            /*!< Enable I2C bus connection for the external I2C PHY interface */
-#define USB_OTG_GCCFG_VBUSASEN                0x00040000U            /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_VBUSBSEN                0x00080000U            /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_SOFOUTEN                0x00100000U            /*!< SOF output enable */
-#define USB_OTG_GCCFG_NOVBUSSENS              0x00200000U            /*!< VBUS sensing disable option */
-
-/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
-#define USB_OTG_DEACHINTMSK_IEP1INTM                0x00000002U            /*!< IN Endpoint 1 interrupt mask bit */
-#define USB_OTG_DEACHINTMSK_OEP1INTM                0x00020000U            /*!< OUT Endpoint 1 interrupt mask bit */
-
-/********************  Bit definition forUSB_OTG_CID register  ********************/
-#define USB_OTG_CID_PRODUCT_ID              0xFFFFFFFFU            /*!< Product ID field */
-
-/********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/
-#define USB_OTG_DIEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPEACHMSK1_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
-
-/********************  Bit definition forUSB_OTG_HPRT register  ********************/
-#define USB_OTG_HPRT_PCSTS                   0x00000001U            /*!< Port connect status */
-#define USB_OTG_HPRT_PCDET                   0x00000002U            /*!< Port connect detected */
-#define USB_OTG_HPRT_PENA                    0x00000004U            /*!< Port enable */
-#define USB_OTG_HPRT_PENCHNG                 0x00000008U            /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA                    0x00000010U            /*!< Port overcurrent active */
-#define USB_OTG_HPRT_POCCHNG                 0x00000020U            /*!< Port overcurrent change */
-#define USB_OTG_HPRT_PRES                    0x00000040U            /*!< Port resume */
-#define USB_OTG_HPRT_PSUSP                   0x00000080U            /*!< Port suspend */
-#define USB_OTG_HPRT_PRST                    0x00000100U            /*!< Port reset */
-
-#define USB_OTG_HPRT_PLSTS                   0x00000C00U            /*!< Port line status */
-#define USB_OTG_HPRT_PLSTS_0                 0x00000400U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PLSTS_1                 0x00000800U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PPWR                    0x00001000U            /*!< Port power */
-
-#define USB_OTG_HPRT_PTCTL                   0x0001E000U            /*!< Port test control */
-#define USB_OTG_HPRT_PTCTL_0                 0x00002000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PTCTL_1                 0x00004000U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PTCTL_2                 0x00008000U            /*!<Bit 2 */
-#define USB_OTG_HPRT_PTCTL_3                 0x00010000U            /*!<Bit 3 */
-
-#define USB_OTG_HPRT_PSPD                    0x00060000U            /*!< Port speed */
-#define USB_OTG_HPRT_PSPD_0                  0x00020000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PSPD_1                  0x00040000U            /*!<Bit 1 */
-
-/********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/
-#define USB_OTG_DOEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DOEPEACHMSK1_TXFURM                  0x00000100U            /*!< OUT packet error mask */
-#define USB_OTG_DOEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_BERRM                   0x00001000U            /*!< Bubble error interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NYETM                   0x00004000U            /*!< NYET interrupt mask */
-
-/********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/
-#define USB_OTG_HPTXFSIZ_PTXSA                   0x0000FFFFU            /*!< Host periodic TxFIFO start address */
-#define USB_OTG_HPTXFSIZ_PTXFD                   0xFFFF0000U            /*!< Host periodic TxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/
-#define USB_OTG_DIEPCTL_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
-#define USB_OTG_DIEPCTL_USBAEP                  0x00008000U            /*!< USB active endpoint */
-#define USB_OTG_DIEPCTL_EONUM_DPID              0x00010000U            /*!< Even/odd frame */
-#define USB_OTG_DIEPCTL_NAKSTS                  0x00020000U            /*!< NAK status */
-
-#define USB_OTG_DIEPCTL_EPTYP                   0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_DIEPCTL_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_STALL                   0x00200000U            /*!< STALL handshake */
-
-#define USB_OTG_DIEPCTL_TXFNUM                  0x03C00000U            /*!< TxFIFO number */
-#define USB_OTG_DIEPCTL_TXFNUM_0                0x00400000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                0x00800000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                0x01000000U            /*!<Bit 2 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                0x02000000U            /*!<Bit 3 */
-#define USB_OTG_DIEPCTL_CNAK                    0x04000000U            /*!< Clear NAK */
-#define USB_OTG_DIEPCTL_SNAK                    0x08000000U            /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          0x10000000U            /*!< Set DATA0 PID */
-#define USB_OTG_DIEPCTL_SODDFRM                 0x20000000U            /*!< Set odd frame */
-#define USB_OTG_DIEPCTL_EPDIS                   0x40000000U            /*!< Endpoint disable */
-#define USB_OTG_DIEPCTL_EPENA                   0x80000000U            /*!< Endpoint enable */
-
-/********************  Bit definition forUSB_OTG_HCCHAR register  ********************/
-#define USB_OTG_HCCHAR_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
-
-#define USB_OTG_HCCHAR_EPNUM                   0x00007800U            /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPNUM_1                 0x00001000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_EPNUM_2                 0x00002000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_EPNUM_3                 0x00004000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_EPDIR                   0x00008000U            /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV                   0x00020000U            /*!< Low-speed device */
-
-#define USB_OTG_HCCHAR_EPTYP                   0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_MC                      0x00300000U            /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                    0x00100000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_MC_1                    0x00200000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_DAD                     0x1FC00000U            /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                   0x00400000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_DAD_1                   0x00800000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_DAD_2                   0x01000000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_DAD_3                   0x02000000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_DAD_4                   0x04000000U            /*!<Bit 4 */
-#define USB_OTG_HCCHAR_DAD_5                   0x08000000U            /*!<Bit 5 */
-#define USB_OTG_HCCHAR_DAD_6                   0x10000000U            /*!<Bit 6 */
-#define USB_OTG_HCCHAR_ODDFRM                  0x20000000U            /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS                   0x40000000U            /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA                   0x80000000U            /*!< Channel enable */
-
-/********************  Bit definition forUSB_OTG_HCSPLT register  ********************/
-
-#define USB_OTG_HCSPLT_PRTADDR                 0x0000007FU            /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_PRTADDR_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_PRTADDR_2               0x00000004U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_PRTADDR_3               0x00000008U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_PRTADDR_4               0x00000010U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_PRTADDR_5               0x00000020U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_PRTADDR_6               0x00000040U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_HUBADDR                 0x00003F80U            /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0               0x00000080U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_HUBADDR_1               0x00000100U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_HUBADDR_2               0x00000200U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_HUBADDR_3               0x00000400U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_HUBADDR_4               0x00000800U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_HUBADDR_5               0x00001000U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_HUBADDR_6               0x00002000U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_XACTPOS                 0x0000C000U            /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0               0x00004000U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_XACTPOS_1               0x00008000U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_COMPLSPLT               0x00010000U            /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN                 0x80000000U            /*!< Split enable */
-
-/********************  Bit definition forUSB_OTG_HCINT register  ********************/
-#define USB_OTG_HCINT_XFRC                    0x00000001U            /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH                     0x00000002U            /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINT_STALL                   0x00000008U            /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK                     0x00000010U            /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK                     0x00000020U            /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET                    0x00000040U            /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR                   0x00000080U            /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR                   0x00000100U            /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR                   0x00000200U            /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR                   0x00000400U            /*!< Data toggle error */
-
-/********************  Bit definition forUSB_OTG_DIEPINT register  ********************/
-#define USB_OTG_DIEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_TOC                     0x00000008U            /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE                  0x00000010U            /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNE                  0x00000040U            /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE                    0x00000080U            /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN              0x00000100U            /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA                     0x00000200U            /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS               0x00000800U            /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR                    0x00001000U            /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK                     0x00002000U            /*!< NAK interrupt */
-
-/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
-#define USB_OTG_HCINTMSK_XFRCM                   0x00000001U            /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM                    0x00000002U            /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM                  0x00000008U            /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM                    0x00000010U            /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM                    0x00000020U            /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET                    0x00000040U            /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM                  0x00000080U            /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM                  0x00000100U            /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM                  0x00000200U            /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM                  0x00000400U            /*!< Data toggle error mask */
-
-/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
-
-#define USB_OTG_DIEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT                  0x60000000U            /*!< Packet count */
-/********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/
-#define USB_OTG_HCTSIZ_XFRSIZ                    0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT                    0x1FF80000U            /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING                    0x80000000U            /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID                      0x60000000U            /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                    0x20000000U            /*!<Bit 0 */
-#define USB_OTG_HCTSIZ_DPID_1                    0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/
-#define USB_OTG_DIEPDMA_DMAADDR                  0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition forUSB_OTG_HCDMA register  ********************/
-#define USB_OTG_HCDMA_DMAADDR                    0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/
-#define USB_OTG_DTXFSTS_INEPTFSAV                0x0000FFFFU            /*!< IN endpoint TxFIFO space avail */
-
-/********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/
-#define USB_OTG_DIEPTXF_INEPTXSA                 0x0000FFFFU            /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD                 0xFFFF0000U            /*!< IN endpoint TxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/
-
-#define USB_OTG_DOEPCTL_MPSIZ                     0x000007FFU            /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP                    0x00008000U            /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS                    0x00020000U            /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            0x10000000U            /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM                   0x20000000U            /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP                     0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                   0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DOEPCTL_EPTYP_1                   0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_SNPM                      0x00100000U            /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL                     0x00200000U            /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK                      0x04000000U            /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK                      0x08000000U            /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS                     0x40000000U            /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA                     0x80000000U            /*!< Endpoint enable */
-
-/********************  Bit definition forUSB_OTG_DOEPINT register  ********************/
-#define USB_OTG_DOEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_STUP                    0x00000008U            /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS                 0x00000010U            /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_NYET                    0x00004000U            /*!< NYET interrupt */
-
-/********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/
-
-#define USB_OTG_DOEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-
-#define USB_OTG_DOEPTSIZ_STUPCNT                 0x60000000U            /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0               0x20000000U            /*!<Bit 0 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1               0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition for PCGCCTL register  ********************/
-#define USB_OTG_PCGCCTL_STOPCLK                 0x00000001U            /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK                 0x00000002U            /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP                 0x00000010U            /*!<Bit 1 */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
- 
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
-                                       ((INSTANCE) == ADC2) || \
-                                       ((INSTANCE) == ADC3))
-
-/******************************* CAN Instances ********************************/
-#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
-                                       ((INSTANCE) == CAN2))
- 
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DAC Instances ********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/******************************* DCMI Instances *******************************/
-#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
-
-/******************************** DMA Instances *******************************/
-#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
-                                              ((INSTANCE) == DMA1_Stream1) || \
-                                              ((INSTANCE) == DMA1_Stream2) || \
-                                              ((INSTANCE) == DMA1_Stream3) || \
-                                              ((INSTANCE) == DMA1_Stream4) || \
-                                              ((INSTANCE) == DMA1_Stream5) || \
-                                              ((INSTANCE) == DMA1_Stream6) || \
-                                              ((INSTANCE) == DMA1_Stream7) || \
-                                              ((INSTANCE) == DMA2_Stream0) || \
-                                              ((INSTANCE) == DMA2_Stream1) || \
-                                              ((INSTANCE) == DMA2_Stream2) || \
-                                              ((INSTANCE) == DMA2_Stream3) || \
-                                              ((INSTANCE) == DMA2_Stream4) || \
-                                              ((INSTANCE) == DMA2_Stream5) || \
-                                              ((INSTANCE) == DMA2_Stream6) || \
-                                              ((INSTANCE) == DMA2_Stream7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOF) || \
-                                        ((INSTANCE) == GPIOG) || \
-                                        ((INSTANCE) == GPIOH) || \
-                                        ((INSTANCE) == GPIOI))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2) || \
-                                       ((INSTANCE) == I2C3))
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI2) || \
-                                        ((INSTANCE) == SPI3))
-
-/*************************** I2S Extended Instances ***************************/
-#define IS_I2S_ALL_INSTANCE_EXT(PERIPH)  (((INSTANCE) == SPI2)    || \
-                                          ((INSTANCE) == SPI3)    || \
-                                          ((INSTANCE) == I2S2ext) || \
-                                          ((INSTANCE) == I2S3ext))
-
-/******************************* RNG Instances ********************************/
-#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-
-/*************************** SPI Extended Instances ***************************/
-#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1)    || \
-                                           ((INSTANCE) == SPI2)    || \
-                                           ((INSTANCE) == SPI3)    || \
-                                           ((INSTANCE) == I2S2ext) || \
-                                           ((INSTANCE) == I2S3ext))
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
-                                   ((INSTANCE) == TIM2)   || \
-                                   ((INSTANCE) == TIM3)   || \
-                                   ((INSTANCE) == TIM4)   || \
-                                   ((INSTANCE) == TIM5)   || \
-                                   ((INSTANCE) == TIM6)   || \
-                                   ((INSTANCE) == TIM7)   || \
-                                   ((INSTANCE) == TIM8)   || \
-                                   ((INSTANCE) == TIM9)   || \
-                                   ((INSTANCE) == TIM10)  || \
-                                   ((INSTANCE) == TIM11)  || \
-                                   ((INSTANCE) == TIM12)  || \
-                                   ((INSTANCE) == TIM13)  || \
-                                   ((INSTANCE) == TIM14))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
-                                         ((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM8)  || \
-                                         ((INSTANCE) == TIM9)  || \
-                                         ((INSTANCE) == TIM10) || \
-                                         ((INSTANCE) == TIM11) || \
-                                         ((INSTANCE) == TIM12) || \
-                                         ((INSTANCE) == TIM13) || \
-                                         ((INSTANCE) == TIM14))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM8) || \
-                                       ((INSTANCE) == TIM9) || \
-                                       ((INSTANCE) == TIM12))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8))
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM8))
-
-/******************** TIM Instances : Advanced-control timers *****************/
-#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                            ((INSTANCE) == TIM8))
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8))
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM6) || \
-                                       ((INSTANCE) == TIM7) || \
-                                       ((INSTANCE) == TIM8))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM8))
-
-/************ TIM Instances : DMA requests generation (COMDE) *****************/
-#define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM8)) 
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                             ((INSTANCE) == TIM2) || \
-                                             ((INSTANCE) == TIM3) || \
-                                             ((INSTANCE) == TIM4) || \
-                                             ((INSTANCE) == TIM5) || \
-                                             ((INSTANCE) == TIM8))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM6) || \
-                                          ((INSTANCE) == TIM7) || \
-                                          ((INSTANCE) == TIM8) || \
-                                          ((INSTANCE) == TIM9) || \
-                                          ((INSTANCE) == TIM12))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8) || \
-                                         ((INSTANCE) == TIM9) || \
-                                         ((INSTANCE) == TIM12))
-
-/********************** TIM Instances : 32 bit Counter ************************/
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
-                                              ((INSTANCE) == TIM5))
-
-/***************** TIM Instances : external trigger input availabe ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                        ((INSTANCE) == TIM2) || \
-                                        ((INSTANCE) == TIM3) || \
-                                        ((INSTANCE) == TIM4) || \
-                                        ((INSTANCE) == TIM5) || \
-                                        ((INSTANCE) == TIM8))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM11))
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM1) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM5) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM8) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM12) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM13) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM14) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-/************ TIM Instances : complementary output(s) available ***************/
-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
-   ((((INSTANCE) == TIM1) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3)))            \
-    ||                                          \
-    (((INSTANCE) == TIM8) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3))))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3) || \
-                                     ((INSTANCE) == USART6))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5)  || \
-                                    ((INSTANCE) == USART6))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3) || \
-                                           ((INSTANCE) == USART6))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3) || \
-                                         ((INSTANCE) == USART6))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5)  || \
-                                    ((INSTANCE) == USART6))     
-
-/*********************** PCD Instances ****************************************/
-/*********************** PCD Instances ****************************************/
-#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
-                                        ((INSTANCE) == USB_OTG_HS))
-
-/*********************** HCD Instances ****************************************/
-#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
-                                       ((INSTANCE) == USB_OTG_HS))
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/****************************** SDIO Instances ********************************/
-#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
-
-/****************************** USB Exported Constants ************************/
-#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                8U
-#define USB_OTG_FS_MAX_IN_ENDPOINTS                    4U    /* Including EP0 */
-#define USB_OTG_FS_MAX_OUT_ENDPOINTS                   4U    /* Including EP0 */
-#define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */
-
-#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR                12U
-#define USB_OTG_HS_MAX_IN_ENDPOINTS                    6U    /* Including EP0 */
-#define USB_OTG_HS_MAX_OUT_ENDPOINTS                   6U    /* Including EP0 */
-#define USB_OTG_HS_TOTAL_FIFO_SIZE                     4096U /* in Bytes */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32F4xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */
-/*  product lines within the same STM32F4 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-#define FMC_IRQn              FSMC_IRQn
-
-/* Aliases for __IRQHandler */
-#define FMC_IRQHandler        FSMC_IRQHandler
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32F407xx_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/cmsis/stm32f410cx.h b/stmhal/cmsis/stm32f410cx.h
deleted file mode 100644
index c3266ccecd..0000000000
--- a/stmhal/cmsis/stm32f410cx.h
+++ /dev/null
@@ -1,3997 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f410cx.h
-  * @author  MCD Application Team
-  * @version V2.5.1
-  * @date    28-June-2016
-  * @brief   CMSIS STM32F410Cx Device Peripheral Access Layer Header File. 
-  *
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - peripherals registers declarations and bits definition
-  *           - Macros to access peripheral’s registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f410cx
-  * @{
-  */
-    
-#ifndef __STM32F410Cx_H
-#define __STM32F410Cx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-  
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-
-/**
-  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
-  */
-#define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */
-#define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */
-#define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1U       /*!< FPU present                                   */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32F4XX Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-typedef enum
-{
-/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
-  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
-/******  STM32 specific Interrupt Numbers **********************************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
-  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
-  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
-  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
-  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
-  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
-  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
-  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
-  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
-  ADC_IRQn                    = 18,     /*!< ADC1 global Interrupts                                            */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
-  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
-  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                             */
-  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
-  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
-  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global Interrupt and DAC Global Interrupt                    */
-  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
-  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
-  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
-  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
-  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
-  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
-  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
-  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
-  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
-  RNG_IRQn                    = 80,     /*!< RNG global Interrupt                                              */
-  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
-  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */
-  FMPI2C1_EV_IRQn             = 95,     /*!< FMPI2C1 Event Interrupt                                           */
-  FMPI2C1_ER_IRQn             = 96,     /*!< FMPI2C1 Error Interrupt                                           */
-  LPTIM1_IRQn                 = 97      /*!< LPTIM1 interrupt                                                  */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
-#include "system_stm32f4xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */
-  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
-  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
-  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
-  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
-  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
-  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
-  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
-  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
-  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
-  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
-  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
-  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
-  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
-  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
-  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
-                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief CRC calculation unit 
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
-  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */
-  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
-  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
-  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
-  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
-  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
-  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
-  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
-  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
-  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
-  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
-  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
-  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
-  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
-  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
-  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
-  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
-  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
-  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
-  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
-  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
-  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
-  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
-  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
-} DMA_Stream_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
-  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
-  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
-  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
-} DMA_TypeDef;
-
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
-  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
-  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
-  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
-  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
-  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-
-typedef struct
-{
-  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */
-  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */
-  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */
-  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */
-  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */
-  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief General Purpose I/O
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
-  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
-  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
-  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
-  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
-  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
-  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
-  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/** 
-  * @brief System configuration controller
-  */
-  
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-  uint32_t      RESERVED;     /*!< Reserved, 0x18                                                               */
-  uint32_t      CFGR2;        /*!< Reserved, 0x1C                                                               */
-  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
-  uint32_t      RESERVED1[2]; /*!< Reserved, 0x24-0x28                                                          */
-  __IO uint32_t CFGR;         /*!< SYSCFG Configuration register,                     Address offset: 0x2C      */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */
-  __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */
-  __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */
-  __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */
-  __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */
-  __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
-  __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
-  __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
-  __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */
-} I2C_TypeDef;
-
-/**
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< FMPI2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< FMPI2C Control register 2,            Address offset: 0x04 */
-  __IO uint32_t OAR1;        /*!< FMPI2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;        /*!< FMPI2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;     /*!< FMPI2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR;    /*!< FMPI2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;         /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;         /*!< FMPI2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;        /*!< FMPI2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;        /*!< FMPI2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;        /*!< FMPI2C Transmit data register,        Address offset: 0x28 */
-} FMPI2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
-  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
-  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
-  uint32_t      RESERVED0[3];  /*!< Reserved, 0x14-0x1C                                                               */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
-  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
-  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
-  uint32_t      RESERVED2[3];  /*!< Reserved, 0x34-0x3C                                                               */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
-  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
-  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
-  uint32_t      RESERVED4[3];  /*!< Reserved, 0x54-0x5C                                                               */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
-  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
-  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
-  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
-  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
-  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
-  uint32_t      RESERVED7[2];  /*!< Reserved, 0x84-0x88                                                               */
-  __IO uint32_t DCKCFGR;       /*!< RCC Dedicated Clocks configuration register,                 Address offset: 0x8C */
-  __IO uint32_t CKGATENR;       /*!< RCC Clocks Gated ENable Register,                           Address offset: 0x90 */
-  __IO uint32_t DCKCFGR2;      /*!< RCC Dedicated Clocks configuration register 2,               Address offset: 0x94 */
-
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-
-typedef struct
-{
-  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
-  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
-  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
-  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
-  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
-  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
-  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */
-  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
-  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */
-  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
-  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */
-  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */
-  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */
-  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */
-  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
-  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */
-  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
-  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
-  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
-  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
-  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
-  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
-  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
-  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
-  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
-  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
-  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
-  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
-  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
-  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
-  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
-  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
-  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
-  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
-  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
-  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
-  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
-} RTC_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
-  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
-  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
-  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-
-/** 
-  * @brief RNG
-  */
-  
-typedef struct 
-{
-  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
-  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
-  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
-} RNG_TypeDef;
-
-
-/**
-  * @brief LPTIMER
-  */
-typedef struct
-{
-  __IO uint32_t ISR;         /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */
-  __IO uint32_t ICR;         /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */
-  __IO uint32_t IER;         /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */
-  __IO uint32_t CFGR;        /*!< LPTIM Configuration register,                       Address offset: 0x0C */
-  __IO uint32_t CR;          /*!< LPTIM Control register,                             Address offset: 0x10 */
-  __IO uint32_t CMP;         /*!< LPTIM Compare register,                             Address offset: 0x14 */
-  __IO uint32_t ARR;         /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
-  __IO uint32_t CNT;         /*!< LPTIM Counter register,                             Address offset: 0x1C */
-  __IO uint32_t OR;          /*!< LPTIM Option register,                              Address offset: 0x20 */
-} LPTIM_TypeDef;
-
-/** 
-  * @brief Peripheral_memory_map
-  */
-#define FLASH_BASE            0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region                         */
-#define SRAM1_BASE            0x20000000U /*!< SRAM1(32 KB) base address in the alias region                              */
-#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region                                */
-#define SRAM1_BB_BASE         0x22000000U /*!< SRAM1(32 KB) base address in the bit-band region                           */
-#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region                             */
-#define FLASH_END             0x0801FFFFU /*!< FLASH end address */
-
-/* Legacy defines */
-#define SRAM_BASE             SRAM1_BASE
-#define SRAM_BB_BASE          SRAM1_BB_BASE
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
-
-/*!< APB1 peripherals */
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)
-#define LPTIM1_BASE           (APB1PERIPH_BASE + 0x2400U)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)
-#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400U)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)
-#define FMPI2C1_BASE          (APB1PERIPH_BASE + 0x6000U)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)
-/*!< APB2 peripherals */
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000U)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x1000U)
-#define USART6_BASE           (APB2PERIPH_BASE + 0x1400U)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000U)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x2300U)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800U)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00U)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000U)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800U)
-#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000U)
-
-/*!< AHB1 peripherals */
-#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000U)
-#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400U)
-#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800U)
-#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00U)
-#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)
-#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800U)
-#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00U)
-#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000U)
-#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010U)
-#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028U)
-#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040U)
-#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058U)
-#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070U)
-#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088U)
-#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0U)
-#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8U)
-#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400U)
-#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010U)
-#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028U)
-#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040U)
-#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058U)
-#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070U)
-#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088U)
-#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0U)
-#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)
-#define RNG_BASE              (PERIPH_BASE + 0x80000U)
-
-/* Debug MCU registers base address */
-#define DBGMCU_BASE           0xE0042000U
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define FMPI2C1             ((FMPI2C_TypeDef *) FMPI2C1_BASE)
-#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define USART6              ((USART_TypeDef *) USART6_BASE)
-#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-#define SPI5                ((SPI_TypeDef *) SPI5_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
-#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
-#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
-#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
-#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
-#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
-#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
-#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
-#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
-#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
-#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
-#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
-#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
-#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
-#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
-#define RNG                 ((RNG_TypeDef *) RNG_BASE)
-
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers_Bits_Definition               */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Analog to Digital Converter                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          0x00000001U       /*!<Analog watchdog flag */
-#define  ADC_SR_EOC                          0x00000002U       /*!<End of conversion */
-#define  ADC_SR_JEOC                         0x00000004U       /*!<Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        0x00000008U       /*!<Injected channel Start flag */
-#define  ADC_SR_STRT                         0x00000010U       /*!<Regular channel Start flag */
-#define  ADC_SR_OVR                          0x00000020U       /*!<Overrun flag */
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
-#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels */
-#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels */
-#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution) */
-#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
-  
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion */
-#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode */
-#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC) */
-#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection */
-#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment */
-#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      0xFFFFU            /*!<Injected data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag */
-#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion */
-#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag */
-#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag */
-#define  ADC_CSR_OVR1                        0x00000020U        /*!<ADC1 DMA overrun  flag */
-#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag */
-#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion */
-#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag */
-#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag */
-#define  ADC_CSR_OVR2                        0x00002000U        /*!<ADC2 DMA overrun  flag */
-#define  ADC_CSR_AWD3                        0x00010000U        /*!<ADC3 Analog watchdog flag */
-#define  ADC_CSR_EOC3                        0x00020000U        /*!<ADC3 End of conversion */
-#define  ADC_CSR_JEOC3                       0x00040000U        /*!<ADC3 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT3                      0x00080000U        /*!<ADC3 Injected channel Start flag */
-#define  ADC_CSR_STRT3                       0x00100000U        /*!<ADC3 Regular channel Start flag */
-#define  ADC_CSR_OVR3                        0x00200000U        /*!<ADC3 DMA overrun  flag */
-
-/* Legacy defines */
-#define  ADC_CSR_DOVR1                        ADC_CSR_OVR1
-#define  ADC_CSR_DOVR2                        ADC_CSR_OVR2
-#define  ADC_CSR_DOVR3                        ADC_CSR_OVR3
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
-#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
-#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
-#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
-#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
-
-/*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                      0x0000FFFFU         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                      0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRC calculation unit                              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           0xFFFFFFFFU /*!< Data register bits */
-
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         0xFFU        /*!< General-purpose 8-bit data register bits */
-
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        0x01U        /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 Debug MCU                                  */
-/*                                                                            */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                             DMA Controller                                 */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DMA_SxCR register  *****************/
-#define DMA_SxCR_CHSEL                       0x0E000000U
-#define DMA_SxCR_CHSEL_0                     0x02000000U
-#define DMA_SxCR_CHSEL_1                     0x04000000U
-#define DMA_SxCR_CHSEL_2                     0x08000000U
-#define DMA_SxCR_MBURST                      0x01800000U
-#define DMA_SxCR_MBURST_0                    0x00800000U
-#define DMA_SxCR_MBURST_1                    0x01000000U
-#define DMA_SxCR_PBURST                      0x00600000U
-#define DMA_SxCR_PBURST_0                    0x00200000U
-#define DMA_SxCR_PBURST_1                    0x00400000U
-#define DMA_SxCR_CT                          0x00080000U
-#define DMA_SxCR_DBM                         0x00040000U
-#define DMA_SxCR_PL                          0x00030000U
-#define DMA_SxCR_PL_0                        0x00010000U
-#define DMA_SxCR_PL_1                        0x00020000U
-#define DMA_SxCR_PINCOS                      0x00008000U
-#define DMA_SxCR_MSIZE                       0x00006000U
-#define DMA_SxCR_MSIZE_0                     0x00002000U
-#define DMA_SxCR_MSIZE_1                     0x00004000U
-#define DMA_SxCR_PSIZE                       0x00001800U
-#define DMA_SxCR_PSIZE_0                     0x00000800U
-#define DMA_SxCR_PSIZE_1                     0x00001000U
-#define DMA_SxCR_MINC                        0x00000400U
-#define DMA_SxCR_PINC                        0x00000200U
-#define DMA_SxCR_CIRC                        0x00000100U
-#define DMA_SxCR_DIR                         0x000000C0U
-#define DMA_SxCR_DIR_0                       0x00000040U
-#define DMA_SxCR_DIR_1                       0x00000080U
-#define DMA_SxCR_PFCTRL                      0x00000020U
-#define DMA_SxCR_TCIE                        0x00000010U
-#define DMA_SxCR_HTIE                        0x00000008U
-#define DMA_SxCR_TEIE                        0x00000004U
-#define DMA_SxCR_DMEIE                       0x00000002U
-#define DMA_SxCR_EN                          0x00000001U
-
-/* Legacy defines */
-#define DMA_SxCR_ACK                         0x00100000U
-
-/********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            0x0000FFFFU
-#define DMA_SxNDT_0                          0x00000001U
-#define DMA_SxNDT_1                          0x00000002U
-#define DMA_SxNDT_2                          0x00000004U
-#define DMA_SxNDT_3                          0x00000008U
-#define DMA_SxNDT_4                          0x00000010U
-#define DMA_SxNDT_5                          0x00000020U
-#define DMA_SxNDT_6                          0x00000040U
-#define DMA_SxNDT_7                          0x00000080U
-#define DMA_SxNDT_8                          0x00000100U
-#define DMA_SxNDT_9                          0x00000200U
-#define DMA_SxNDT_10                         0x00000400U
-#define DMA_SxNDT_11                         0x00000800U
-#define DMA_SxNDT_12                         0x00001000U
-#define DMA_SxNDT_13                         0x00002000U
-#define DMA_SxNDT_14                         0x00004000U
-#define DMA_SxNDT_15                         0x00008000U
-
-/********************  Bits definition for DMA_SxFCR register  ****************/ 
-#define DMA_SxFCR_FEIE                       0x00000080U
-#define DMA_SxFCR_FS                         0x00000038U
-#define DMA_SxFCR_FS_0                       0x00000008U
-#define DMA_SxFCR_FS_1                       0x00000010U
-#define DMA_SxFCR_FS_2                       0x00000020U
-#define DMA_SxFCR_DMDIS                      0x00000004U
-#define DMA_SxFCR_FTH                        0x00000003U
-#define DMA_SxFCR_FTH_0                      0x00000001U
-#define DMA_SxFCR_FTH_1                      0x00000002U
-
-/********************  Bits definition for DMA_LISR register  *****************/ 
-#define DMA_LISR_TCIF3                       0x08000000U
-#define DMA_LISR_HTIF3                       0x04000000U
-#define DMA_LISR_TEIF3                       0x02000000U
-#define DMA_LISR_DMEIF3                      0x01000000U
-#define DMA_LISR_FEIF3                       0x00400000U
-#define DMA_LISR_TCIF2                       0x00200000U
-#define DMA_LISR_HTIF2                       0x00100000U
-#define DMA_LISR_TEIF2                       0x00080000U
-#define DMA_LISR_DMEIF2                      0x00040000U
-#define DMA_LISR_FEIF2                       0x00010000U
-#define DMA_LISR_TCIF1                       0x00000800U
-#define DMA_LISR_HTIF1                       0x00000400U
-#define DMA_LISR_TEIF1                       0x00000200U
-#define DMA_LISR_DMEIF1                      0x00000100U
-#define DMA_LISR_FEIF1                       0x00000040U
-#define DMA_LISR_TCIF0                       0x00000020U
-#define DMA_LISR_HTIF0                       0x00000010U
-#define DMA_LISR_TEIF0                       0x00000008U
-#define DMA_LISR_DMEIF0                      0x00000004U
-#define DMA_LISR_FEIF0                       0x00000001U
-
-/********************  Bits definition for DMA_HISR register  *****************/ 
-#define DMA_HISR_TCIF7                       0x08000000U
-#define DMA_HISR_HTIF7                       0x04000000U
-#define DMA_HISR_TEIF7                       0x02000000U
-#define DMA_HISR_DMEIF7                      0x01000000U
-#define DMA_HISR_FEIF7                       0x00400000U
-#define DMA_HISR_TCIF6                       0x00200000U
-#define DMA_HISR_HTIF6                       0x00100000U
-#define DMA_HISR_TEIF6                       0x00080000U
-#define DMA_HISR_DMEIF6                      0x00040000U
-#define DMA_HISR_FEIF6                       0x00010000U
-#define DMA_HISR_TCIF5                       0x00000800U
-#define DMA_HISR_HTIF5                       0x00000400U
-#define DMA_HISR_TEIF5                       0x00000200U
-#define DMA_HISR_DMEIF5                      0x00000100U
-#define DMA_HISR_FEIF5                       0x00000040U
-#define DMA_HISR_TCIF4                       0x00000020U
-#define DMA_HISR_HTIF4                       0x00000010U
-#define DMA_HISR_TEIF4                       0x00000008U
-#define DMA_HISR_DMEIF4                      0x00000004U
-#define DMA_HISR_FEIF4                       0x00000001U
-
-/********************  Bits definition for DMA_LIFCR register  ****************/ 
-#define DMA_LIFCR_CTCIF3                     0x08000000U
-#define DMA_LIFCR_CHTIF3                     0x04000000U
-#define DMA_LIFCR_CTEIF3                     0x02000000U
-#define DMA_LIFCR_CDMEIF3                    0x01000000U
-#define DMA_LIFCR_CFEIF3                     0x00400000U
-#define DMA_LIFCR_CTCIF2                     0x00200000U
-#define DMA_LIFCR_CHTIF2                     0x00100000U
-#define DMA_LIFCR_CTEIF2                     0x00080000U
-#define DMA_LIFCR_CDMEIF2                    0x00040000U
-#define DMA_LIFCR_CFEIF2                     0x00010000U
-#define DMA_LIFCR_CTCIF1                     0x00000800U
-#define DMA_LIFCR_CHTIF1                     0x00000400U
-#define DMA_LIFCR_CTEIF1                     0x00000200U
-#define DMA_LIFCR_CDMEIF1                    0x00000100U
-#define DMA_LIFCR_CFEIF1                     0x00000040U
-#define DMA_LIFCR_CTCIF0                     0x00000020U
-#define DMA_LIFCR_CHTIF0                     0x00000010U
-#define DMA_LIFCR_CTEIF0                     0x00000008U
-#define DMA_LIFCR_CDMEIF0                    0x00000004U
-#define DMA_LIFCR_CFEIF0                     0x00000001U
-
-/********************  Bits definition for DMA_HIFCR  register  ****************/ 
-#define DMA_HIFCR_CTCIF7                     0x08000000U
-#define DMA_HIFCR_CHTIF7                     0x04000000U
-#define DMA_HIFCR_CTEIF7                     0x02000000U
-#define DMA_HIFCR_CDMEIF7                    0x01000000U
-#define DMA_HIFCR_CFEIF7                     0x00400000U
-#define DMA_HIFCR_CTCIF6                     0x00200000U
-#define DMA_HIFCR_CHTIF6                     0x00100000U
-#define DMA_HIFCR_CTEIF6                     0x00080000U
-#define DMA_HIFCR_CDMEIF6                    0x00040000U
-#define DMA_HIFCR_CFEIF6                     0x00010000U
-#define DMA_HIFCR_CTCIF5                     0x00000800U
-#define DMA_HIFCR_CHTIF5                     0x00000400U
-#define DMA_HIFCR_CTEIF5                     0x00000200U
-#define DMA_HIFCR_CDMEIF5                    0x00000100U
-#define DMA_HIFCR_CFEIF5                     0x00000040U
-#define DMA_HIFCR_CTCIF4                     0x00000020U
-#define DMA_HIFCR_CHTIF4                     0x00000010U
-#define DMA_HIFCR_CTEIF4                     0x00000008U
-#define DMA_HIFCR_CDMEIF4                    0x00000004U
-#define DMA_HIFCR_CFEIF4                     0x00000001U
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                    External Interrupt/Event Controller                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
-#define  EXTI_IMR_MR23                       0x00800000U        /*!< Interrupt Mask on line 23 */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
-#define  EXTI_EMR_MR23                       0x00800000U        /*!< Event Mask on line 23 */
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
-#define  EXTI_RTSR_TR23                      0x00800000U        /*!< Rising trigger event configuration bit of line 23 */
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
-#define  EXTI_FTSR_TR23                      0x00800000U        /*!< Falling trigger event configuration bit of line 23 */
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
-#define  EXTI_SWIER_SWIER23                  0x00800000U        /*!< Software Interrupt on line 23 */
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
-#define  EXTI_PR_PR23                        0x00800000U        /*!< Pending bit for line 23 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    FLASH                                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    0x0000000FU
-#define FLASH_ACR_LATENCY_0WS                0x00000000U
-#define FLASH_ACR_LATENCY_1WS                0x00000001U
-#define FLASH_ACR_LATENCY_2WS                0x00000002U
-#define FLASH_ACR_LATENCY_3WS                0x00000003U
-#define FLASH_ACR_LATENCY_4WS                0x00000004U
-#define FLASH_ACR_LATENCY_5WS                0x00000005U
-#define FLASH_ACR_LATENCY_6WS                0x00000006U
-#define FLASH_ACR_LATENCY_7WS                0x00000007U
-
-#define FLASH_ACR_PRFTEN                     0x00000100U
-#define FLASH_ACR_ICEN                       0x00000200U
-#define FLASH_ACR_DCEN                       0x00000400U
-#define FLASH_ACR_ICRST                      0x00000800U
-#define FLASH_ACR_DCRST                      0x00001000U
-#define FLASH_ACR_BYTE0_ADDRESS              0x40023C00U
-#define FLASH_ACR_BYTE2_ADDRESS              0x40023C03U
-
-/*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         0x00000001U
-#define FLASH_SR_SOP                         0x00000002U
-#define FLASH_SR_WRPERR                      0x00000010U
-#define FLASH_SR_PGAERR                      0x00000020U
-#define FLASH_SR_PGPERR                      0x00000040U
-#define FLASH_SR_PGSERR                      0x00000080U
-#define FLASH_SR_BSY                         0x00010000U
-
-/*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          0x00000001U
-#define FLASH_CR_SER                         0x00000002U
-#define FLASH_CR_MER                         0x00000004U
-#define FLASH_CR_SNB                         0x000000F8U
-#define FLASH_CR_SNB_0                       0x00000008U
-#define FLASH_CR_SNB_1                       0x00000010U
-#define FLASH_CR_SNB_2                       0x00000020U
-#define FLASH_CR_SNB_3                       0x00000040U
-#define FLASH_CR_SNB_4                       0x00000080U
-#define FLASH_CR_PSIZE                       0x00000300U
-#define FLASH_CR_PSIZE_0                     0x00000100U
-#define FLASH_CR_PSIZE_1                     0x00000200U
-#define FLASH_CR_STRT                        0x00010000U
-#define FLASH_CR_EOPIE                       0x01000000U
-#define FLASH_CR_LOCK                        0x80000000U
-
-/*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                 0x00000001U
-#define FLASH_OPTCR_OPTSTRT                 0x00000002U
-#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
-#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
-#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
-
-#define FLASH_OPTCR_WDG_SW                  0x00000020U
-#define FLASH_OPTCR_nRST_STOP               0x00000040U
-#define FLASH_OPTCR_nRST_STDBY              0x00000080U
-#define FLASH_OPTCR_RDP                     0x0000FF00U
-#define FLASH_OPTCR_RDP_0                   0x00000100U
-#define FLASH_OPTCR_RDP_1                   0x00000200U
-#define FLASH_OPTCR_RDP_2                   0x00000400U
-#define FLASH_OPTCR_RDP_3                   0x00000800U
-#define FLASH_OPTCR_RDP_4                   0x00001000U
-#define FLASH_OPTCR_RDP_5                   0x00002000U
-#define FLASH_OPTCR_RDP_6                   0x00004000U
-#define FLASH_OPTCR_RDP_7                   0x00008000U
-#define FLASH_OPTCR_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR_nWRP_0                  0x00010000U
-#define FLASH_OPTCR_nWRP_1                  0x00020000U
-#define FLASH_OPTCR_nWRP_2                  0x00040000U
-#define FLASH_OPTCR_nWRP_3                  0x00080000U
-#define FLASH_OPTCR_nWRP_4                  0x00100000U
-#define FLASH_OPTCR_nWRP_5                  0x00200000U
-#define FLASH_OPTCR_nWRP_6                  0x00400000U
-#define FLASH_OPTCR_nWRP_7                  0x00800000U
-#define FLASH_OPTCR_nWRP_8                  0x01000000U
-#define FLASH_OPTCR_nWRP_9                  0x02000000U
-#define FLASH_OPTCR_nWRP_10                 0x04000000U
-#define FLASH_OPTCR_nWRP_11                 0x08000000U
-                                             
-/******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR1_nWRP_0                  0x00010000U
-#define FLASH_OPTCR1_nWRP_1                  0x00020000U
-#define FLASH_OPTCR1_nWRP_2                  0x00040000U
-#define FLASH_OPTCR1_nWRP_3                  0x00080000U
-#define FLASH_OPTCR1_nWRP_4                  0x00100000U
-#define FLASH_OPTCR1_nWRP_5                  0x00200000U
-#define FLASH_OPTCR1_nWRP_6                  0x00400000U
-#define FLASH_OPTCR1_nWRP_7                  0x00800000U
-#define FLASH_OPTCR1_nWRP_8                  0x01000000U
-#define FLASH_OPTCR1_nWRP_9                  0x02000000U
-#define FLASH_OPTCR1_nWRP_10                 0x04000000U
-#define FLASH_OPTCR1_nWRP_11                 0x08000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    0x00000003U
-#define GPIO_MODER_MODER0_0                  0x00000001U
-#define GPIO_MODER_MODER0_1                  0x00000002U
-
-#define GPIO_MODER_MODER1                    0x0000000CU
-#define GPIO_MODER_MODER1_0                  0x00000004U
-#define GPIO_MODER_MODER1_1                  0x00000008U
-
-#define GPIO_MODER_MODER2                    0x00000030U
-#define GPIO_MODER_MODER2_0                  0x00000010U
-#define GPIO_MODER_MODER2_1                  0x00000020U
-
-#define GPIO_MODER_MODER3                    0x000000C0U
-#define GPIO_MODER_MODER3_0                  0x00000040U
-#define GPIO_MODER_MODER3_1                  0x00000080U
-
-#define GPIO_MODER_MODER4                    0x00000300U
-#define GPIO_MODER_MODER4_0                  0x00000100U
-#define GPIO_MODER_MODER4_1                  0x00000200U
-
-#define GPIO_MODER_MODER5                    0x00000C00U
-#define GPIO_MODER_MODER5_0                  0x00000400U
-#define GPIO_MODER_MODER5_1                  0x00000800U
-
-#define GPIO_MODER_MODER6                    0x00003000U
-#define GPIO_MODER_MODER6_0                  0x00001000U
-#define GPIO_MODER_MODER6_1                  0x00002000U
-
-#define GPIO_MODER_MODER7                    0x0000C000U
-#define GPIO_MODER_MODER7_0                  0x00004000U
-#define GPIO_MODER_MODER7_1                  0x00008000U
-
-#define GPIO_MODER_MODER8                    0x00030000U
-#define GPIO_MODER_MODER8_0                  0x00010000U
-#define GPIO_MODER_MODER8_1                  0x00020000U
-
-#define GPIO_MODER_MODER9                    0x000C0000U
-#define GPIO_MODER_MODER9_0                  0x00040000U
-#define GPIO_MODER_MODER9_1                  0x00080000U
-
-#define GPIO_MODER_MODER10                   0x00300000U
-#define GPIO_MODER_MODER10_0                 0x00100000U
-#define GPIO_MODER_MODER10_1                 0x00200000U
-
-#define GPIO_MODER_MODER11                   0x00C00000U
-#define GPIO_MODER_MODER11_0                 0x00400000U
-#define GPIO_MODER_MODER11_1                 0x00800000U
-
-#define GPIO_MODER_MODER12                   0x03000000U
-#define GPIO_MODER_MODER12_0                 0x01000000U
-#define GPIO_MODER_MODER12_1                 0x02000000U
-
-#define GPIO_MODER_MODER13                   0x0C000000U
-#define GPIO_MODER_MODER13_0                 0x04000000U
-#define GPIO_MODER_MODER13_1                 0x08000000U
-
-#define GPIO_MODER_MODER14                   0x30000000U
-#define GPIO_MODER_MODER14_0                 0x10000000U
-#define GPIO_MODER_MODER14_1                 0x20000000U
-
-#define GPIO_MODER_MODER15                   0xC0000000U
-#define GPIO_MODER_MODER15_0                 0x40000000U
-#define GPIO_MODER_MODER15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     0x00000001U
-#define GPIO_OTYPER_OT_1                     0x00000002U
-#define GPIO_OTYPER_OT_2                     0x00000004U
-#define GPIO_OTYPER_OT_3                     0x00000008U
-#define GPIO_OTYPER_OT_4                     0x00000010U
-#define GPIO_OTYPER_OT_5                     0x00000020U
-#define GPIO_OTYPER_OT_6                     0x00000040U
-#define GPIO_OTYPER_OT_7                     0x00000080U
-#define GPIO_OTYPER_OT_8                     0x00000100U
-#define GPIO_OTYPER_OT_9                     0x00000200U
-#define GPIO_OTYPER_OT_10                    0x00000400U
-#define GPIO_OTYPER_OT_11                    0x00000800U
-#define GPIO_OTYPER_OT_12                    0x00001000U
-#define GPIO_OTYPER_OT_13                    0x00002000U
-#define GPIO_OTYPER_OT_14                    0x00004000U
-#define GPIO_OTYPER_OT_15                    0x00008000U
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
-#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
-#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
-
-#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
-#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
-#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
-
-#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
-#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
-#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
-
-#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
-#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
-#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
-
-#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
-#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
-#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
-
-#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
-#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
-#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
-
-#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
-#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
-#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
-
-#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
-#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
-#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
-
-#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
-#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
-#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
-
-#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
-#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
-#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
-
-#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
-#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
-#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
-
-#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
-#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
-#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
-
-#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
-#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
-#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
-
-#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
-#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
-#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
-
-#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
-#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
-#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
-
-#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
-#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
-#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    0x00000003U
-#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
-#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
-
-#define GPIO_PUPDR_PUPDR1                    0x0000000CU
-#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
-#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
-
-#define GPIO_PUPDR_PUPDR2                    0x00000030U
-#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
-#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
-
-#define GPIO_PUPDR_PUPDR3                    0x000000C0U
-#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
-#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
-
-#define GPIO_PUPDR_PUPDR4                    0x00000300U
-#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
-#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
-
-#define GPIO_PUPDR_PUPDR5                    0x00000C00U
-#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
-#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
-
-#define GPIO_PUPDR_PUPDR6                    0x00003000U
-#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
-#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
-
-#define GPIO_PUPDR_PUPDR7                    0x0000C000U
-#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
-#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
-
-#define GPIO_PUPDR_PUPDR8                    0x00030000U
-#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
-#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
-
-#define GPIO_PUPDR_PUPDR9                    0x000C0000U
-#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
-#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
-
-#define GPIO_PUPDR_PUPDR10                   0x00300000U
-#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
-#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
-
-#define GPIO_PUPDR_PUPDR11                   0x00C00000U
-#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
-#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
-
-#define GPIO_PUPDR_PUPDR12                   0x03000000U
-#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
-#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
-
-#define GPIO_PUPDR_PUPDR13                   0x0C000000U
-#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
-#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
-
-#define GPIO_PUPDR_PUPDR14                   0x30000000U
-#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
-#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
-
-#define GPIO_PUPDR_PUPDR15                   0xC0000000U
-#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
-#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       0x00000001U
-#define GPIO_IDR_IDR_1                       0x00000002U
-#define GPIO_IDR_IDR_2                       0x00000004U
-#define GPIO_IDR_IDR_3                       0x00000008U
-#define GPIO_IDR_IDR_4                       0x00000010U
-#define GPIO_IDR_IDR_5                       0x00000020U
-#define GPIO_IDR_IDR_6                       0x00000040U
-#define GPIO_IDR_IDR_7                       0x00000080U
-#define GPIO_IDR_IDR_8                       0x00000100U
-#define GPIO_IDR_IDR_9                       0x00000200U
-#define GPIO_IDR_IDR_10                      0x00000400U
-#define GPIO_IDR_IDR_11                      0x00000800U
-#define GPIO_IDR_IDR_12                      0x00001000U
-#define GPIO_IDR_IDR_13                      0x00002000U
-#define GPIO_IDR_IDR_14                      0x00004000U
-#define GPIO_IDR_IDR_15                      0x00008000U
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       0x00000001U
-#define GPIO_ODR_ODR_1                       0x00000002U
-#define GPIO_ODR_ODR_2                       0x00000004U
-#define GPIO_ODR_ODR_3                       0x00000008U
-#define GPIO_ODR_ODR_4                       0x00000010U
-#define GPIO_ODR_ODR_5                       0x00000020U
-#define GPIO_ODR_ODR_6                       0x00000040U
-#define GPIO_ODR_ODR_7                       0x00000080U
-#define GPIO_ODR_ODR_8                       0x00000100U
-#define GPIO_ODR_ODR_9                       0x00000200U
-#define GPIO_ODR_ODR_10                      0x00000400U
-#define GPIO_ODR_ODR_11                      0x00000800U
-#define GPIO_ODR_ODR_12                      0x00001000U
-#define GPIO_ODR_ODR_13                      0x00002000U
-#define GPIO_ODR_ODR_14                      0x00004000U
-#define GPIO_ODR_ODR_15                      0x00008000U
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       0x00000001U
-#define GPIO_BSRR_BS_1                       0x00000002U
-#define GPIO_BSRR_BS_2                       0x00000004U
-#define GPIO_BSRR_BS_3                       0x00000008U
-#define GPIO_BSRR_BS_4                       0x00000010U
-#define GPIO_BSRR_BS_5                       0x00000020U
-#define GPIO_BSRR_BS_6                       0x00000040U
-#define GPIO_BSRR_BS_7                       0x00000080U
-#define GPIO_BSRR_BS_8                       0x00000100U
-#define GPIO_BSRR_BS_9                       0x00000200U
-#define GPIO_BSRR_BS_10                      0x00000400U
-#define GPIO_BSRR_BS_11                      0x00000800U
-#define GPIO_BSRR_BS_12                      0x00001000U
-#define GPIO_BSRR_BS_13                      0x00002000U
-#define GPIO_BSRR_BS_14                      0x00004000U
-#define GPIO_BSRR_BS_15                      0x00008000U
-#define GPIO_BSRR_BR_0                       0x00010000U
-#define GPIO_BSRR_BR_1                       0x00020000U
-#define GPIO_BSRR_BR_2                       0x00040000U
-#define GPIO_BSRR_BR_3                       0x00080000U
-#define GPIO_BSRR_BR_4                       0x00100000U
-#define GPIO_BSRR_BR_5                       0x00200000U
-#define GPIO_BSRR_BR_6                       0x00400000U
-#define GPIO_BSRR_BR_7                       0x00800000U
-#define GPIO_BSRR_BR_8                       0x01000000U
-#define GPIO_BSRR_BR_9                       0x02000000U
-#define GPIO_BSRR_BR_10                      0x04000000U
-#define GPIO_BSRR_BR_11                      0x08000000U
-#define GPIO_BSRR_BR_12                      0x10000000U
-#define GPIO_BSRR_BR_13                      0x20000000U
-#define GPIO_BSRR_BR_14                      0x40000000U
-#define GPIO_BSRR_BR_15                      0x80000000U
-
-/****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0                       0x00000001U
-#define GPIO_LCKR_LCK1                       0x00000002U
-#define GPIO_LCKR_LCK2                       0x00000004U
-#define GPIO_LCKR_LCK3                       0x00000008U
-#define GPIO_LCKR_LCK4                       0x00000010U
-#define GPIO_LCKR_LCK5                       0x00000020U
-#define GPIO_LCKR_LCK6                       0x00000040U
-#define GPIO_LCKR_LCK7                       0x00000080U
-#define GPIO_LCKR_LCK8                       0x00000100U
-#define GPIO_LCKR_LCK9                       0x00000200U
-#define GPIO_LCKR_LCK10                      0x00000400U
-#define GPIO_LCKR_LCK11                      0x00000800U
-#define GPIO_LCKR_LCK12                      0x00001000U
-#define GPIO_LCKR_LCK13                      0x00002000U
-#define GPIO_LCKR_LCK14                      0x00004000U
-#define GPIO_LCKR_LCK15                      0x00008000U
-#define GPIO_LCKR_LCKK                       0x00010000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Inter-integrated Circuit Interface                    */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          0x00000001U     /*!<Peripheral Enable                             */
-#define  I2C_CR1_SMBUS                       0x00000002U     /*!<SMBus Mode                                    */
-#define  I2C_CR1_SMBTYPE                     0x00000008U     /*!<SMBus Type                                    */
-#define  I2C_CR1_ENARP                       0x00000010U     /*!<ARP Enable                                    */
-#define  I2C_CR1_ENPEC                       0x00000020U     /*!<PEC Enable                                    */
-#define  I2C_CR1_ENGC                        0x00000040U     /*!<General Call Enable                           */
-#define  I2C_CR1_NOSTRETCH                   0x00000080U     /*!<Clock Stretching Disable (Slave mode)  */
-#define  I2C_CR1_START                       0x00000100U     /*!<Start Generation                              */
-#define  I2C_CR1_STOP                        0x00000200U     /*!<Stop Generation                               */
-#define  I2C_CR1_ACK                         0x00000400U     /*!<Acknowledge Enable                            */
-#define  I2C_CR1_POS                         0x00000800U     /*!<Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         0x00001000U     /*!<Packet Error Checking                         */
-#define  I2C_CR1_ALERT                       0x00002000U     /*!<SMBus Alert                                   */
-#define  I2C_CR1_SWRST                       0x00008000U     /*!<Software Reset                                */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        0x0000003FU     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
-#define  I2C_CR2_FREQ_0                      0x00000001U     /*!<Bit 0 */
-#define  I2C_CR2_FREQ_1                      0x00000002U     /*!<Bit 1 */
-#define  I2C_CR2_FREQ_2                      0x00000004U     /*!<Bit 2 */
-#define  I2C_CR2_FREQ_3                      0x00000008U     /*!<Bit 3 */
-#define  I2C_CR2_FREQ_4                      0x00000010U     /*!<Bit 4 */
-#define  I2C_CR2_FREQ_5                      0x00000020U     /*!<Bit 5 */
-
-#define  I2C_CR2_ITERREN                     0x00000100U     /*!<Error Interrupt Enable  */
-#define  I2C_CR2_ITEVTEN                     0x00000200U     /*!<Event Interrupt Enable  */
-#define  I2C_CR2_ITBUFEN                     0x00000400U     /*!<Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       0x00000800U     /*!<DMA Requests Enable     */
-#define  I2C_CR2_LAST                        0x00001000U     /*!<DMA Last Transfer       */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     0x000000FEU     /*!<Interface Address */
-#define  I2C_OAR1_ADD8_9                     0x00000300U     /*!<Interface Address */
-
-#define  I2C_OAR1_ADD0                       0x00000001U     /*!<Bit 0 */
-#define  I2C_OAR1_ADD1                       0x00000002U     /*!<Bit 1 */
-#define  I2C_OAR1_ADD2                       0x00000004U     /*!<Bit 2 */
-#define  I2C_OAR1_ADD3                       0x00000008U     /*!<Bit 3 */
-#define  I2C_OAR1_ADD4                       0x00000010U     /*!<Bit 4 */
-#define  I2C_OAR1_ADD5                       0x00000020U     /*!<Bit 5 */
-#define  I2C_OAR1_ADD6                       0x00000040U     /*!<Bit 6 */
-#define  I2C_OAR1_ADD7                       0x00000080U     /*!<Bit 7 */
-#define  I2C_OAR1_ADD8                       0x00000100U     /*!<Bit 8 */
-#define  I2C_OAR1_ADD9                       0x00000200U     /*!<Bit 9 */
-
-#define  I2C_OAR1_ADDMODE                    0x00008000U     /*!<Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     0x00000001U        /*!<Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       0x000000FEU        /*!<Interface address           */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           0x000000FFU        /*!<8-bit Data Register         */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          0x00000001U     /*!<Start Bit (Master mode)                  */
-#define  I2C_SR1_ADDR                        0x00000002U     /*!<Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         0x00000004U     /*!<Byte Transfer Finished                          */
-#define  I2C_SR1_ADD10                       0x00000008U     /*!<10-bit header sent (Master mode)         */
-#define  I2C_SR1_STOPF                       0x00000010U     /*!<Stop detection (Slave mode)              */
-#define  I2C_SR1_RXNE                        0x00000040U     /*!<Data Register not Empty (receivers)      */
-#define  I2C_SR1_TXE                         0x00000080U     /*!<Data Register Empty (transmitters)       */
-#define  I2C_SR1_BERR                        0x00000100U     /*!<Bus Error                                       */
-#define  I2C_SR1_ARLO                        0x00000200U     /*!<Arbitration Lost (master mode)           */
-#define  I2C_SR1_AF                          0x00000400U     /*!<Acknowledge Failure                             */
-#define  I2C_SR1_OVR                         0x00000800U     /*!<Overrun/Underrun                                */
-#define  I2C_SR1_PECERR                      0x00001000U     /*!<PEC Error in reception                          */
-#define  I2C_SR1_TIMEOUT                     0x00004000U     /*!<Timeout or Tlow Error                           */
-#define  I2C_SR1_SMBALERT                    0x00008000U     /*!<SMBus Alert                                     */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         0x00000001U     /*!<Master/Slave                              */
-#define  I2C_SR2_BUSY                        0x00000002U     /*!<Bus Busy                                  */
-#define  I2C_SR2_TRA                         0x00000004U     /*!<Transmitter/Receiver                      */
-#define  I2C_SR2_GENCALL                     0x00000010U     /*!<General Call Address (Slave mode)  */
-#define  I2C_SR2_SMBDEFAULT                  0x00000020U     /*!<SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     0x00000040U     /*!<SMBus Host Header (Slave mode)     */
-#define  I2C_SR2_DUALF                       0x00000080U     /*!<Dual Flag (Slave mode)             */
-#define  I2C_SR2_PEC                         0x0000FF00U     /*!<Packet Error Checking Register            */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         0x00000FFFU     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        0x00004000U     /*!<Fast Mode Duty Cycle                                       */
-#define  I2C_CCR_FS                          0x00008000U     /*!<I2C Master Mode Selection                                  */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     0x0000003FU     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************  Bit definition for I2C_FLTR register  *******************/
-#define  I2C_FLTR_DNF                        0x0000000FU     /*!<Digital Noise Filter */
-#define  I2C_FLTR_ANOFF                      0x00000010U     /*!<Analog Noise Filter OFF */
-
-/******************************************************************************/
-/*                                                                            */
-/*        Fast Mode Plus Inter-integrated Circuit Interface (I2C)             */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define  FMPI2C_CR1_PE                        0x00000001U        /*!< Peripheral enable                   */
-#define  FMPI2C_CR1_TXIE                      0x00000002U        /*!< TX interrupt enable                 */
-#define  FMPI2C_CR1_RXIE                      0x00000004U        /*!< RX interrupt enable                 */
-#define  FMPI2C_CR1_ADDRIE                    0x00000008U        /*!< Address match interrupt enable      */
-#define  FMPI2C_CR1_NACKIE                    0x00000010U        /*!< NACK received interrupt enable      */
-#define  FMPI2C_CR1_STOPIE                    0x00000020U        /*!< STOP detection interrupt enable     */
-#define  FMPI2C_CR1_TCIE                      0x00000040U        /*!< Transfer complete interrupt enable  */
-#define  FMPI2C_CR1_ERRIE                     0x00000080U        /*!< Errors interrupt enable             */
-#define  FMPI2C_CR1_DFN                       0x00000F00U        /*!< Digital noise filter                */
-#define  FMPI2C_CR1_ANFOFF                    0x00001000U        /*!< Analog noise filter OFF             */
-#define  FMPI2C_CR1_TXDMAEN                   0x00004000U        /*!< DMA transmission requests enable    */
-#define  FMPI2C_CR1_RXDMAEN                   0x00008000U        /*!< DMA reception requests enable       */
-#define  FMPI2C_CR1_SBC                       0x00010000U        /*!< Slave byte control                  */
-#define  FMPI2C_CR1_NOSTRETCH                 0x00020000U        /*!< Clock stretching disable            */
-#define  FMPI2C_CR1_GCEN                      0x00080000U        /*!< General call enable                 */
-#define  FMPI2C_CR1_SMBHEN                    0x00100000U        /*!< SMBus host address enable           */
-#define  FMPI2C_CR1_SMBDEN                    0x00200000U        /*!< SMBus device default address enable */
-#define  FMPI2C_CR1_ALERTEN                   0x00400000U        /*!< SMBus alert enable                  */
-#define  FMPI2C_CR1_PECEN                     0x00800000U        /*!< PEC enable                          */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define  FMPI2C_CR2_SADD                      0x000003FFU        /*!< Slave address (master mode)                             */
-#define  FMPI2C_CR2_RD_WRN                    0x00000400U        /*!< Transfer direction (master mode)                        */
-#define  FMPI2C_CR2_ADD10                     0x00000800U        /*!< 10-bit addressing mode (master mode)                    */
-#define  FMPI2C_CR2_HEAD10R                   0x00001000U        /*!< 10-bit address header only read direction (master mode) */
-#define  FMPI2C_CR2_START                     0x00002000U        /*!< START generation                                        */
-#define  FMPI2C_CR2_STOP                      0x00004000U        /*!< STOP generation (master mode)                           */
-#define  FMPI2C_CR2_NACK                      0x00008000U        /*!< NACK generation (slave mode)                            */
-#define  FMPI2C_CR2_NBYTES                    0x00FF0000U        /*!< Number of bytes                                         */
-#define  FMPI2C_CR2_RELOAD                    0x01000000U        /*!< NBYTES reload mode                                      */
-#define  FMPI2C_CR2_AUTOEND                   0x02000000U        /*!< Automatic end mode (master mode)                        */
-#define  FMPI2C_CR2_PECBYTE                   0x04000000U        /*!< Packet error checking byte                              */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define  FMPI2C_OAR1_OA1                      0x000003FFU        /*!< Interface own address 1   */
-#define  FMPI2C_OAR1_OA1MODE                  0x00000400U        /*!< Own address 1 10-bit mode */
-#define  FMPI2C_OAR1_OA1EN                    0x00008000U        /*!< Own address 1 enable      */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define  FMPI2C_OAR2_OA2                      0x000000FEU        /*!< Interface own address 2 */
-#define  FMPI2C_OAR2_OA2MSK                   0x00000700U        /*!< Own address 2 masks     */
-#define  FMPI2C_OAR2_OA2EN                    0x00008000U        /*!< Own address 2 enable    */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define  FMPI2C_TIMINGR_SCLL                  0x000000FFU        /*!< SCL low period (master mode)  */
-#define  FMPI2C_TIMINGR_SCLH                  0x0000FF00U        /*!< SCL high period (master mode) */
-#define  FMPI2C_TIMINGR_SDADEL                0x000F0000U        /*!< Data hold time                */
-#define  FMPI2C_TIMINGR_SCLDEL                0x00F00000U        /*!< Data setup time               */
-#define  FMPI2C_TIMINGR_PRESC                 0xF0000000U        /*!< Timings prescaler             */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define  FMPI2C_TIMEOUTR_TIMEOUTA             0x00000FFFU        /*!< Bus timeout A                 */
-#define  FMPI2C_TIMEOUTR_TIDLE                0x00001000U        /*!< Idle clock timeout detection  */
-#define  FMPI2C_TIMEOUTR_TIMOUTEN             0x00008000U        /*!< Clock timeout enable          */
-#define  FMPI2C_TIMEOUTR_TIMEOUTB             0x0FFF0000U        /*!< Bus timeout B                 */
-#define  FMPI2C_TIMEOUTR_TEXTEN               0x80000000U        /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define  FMPI2C_ISR_TXE                       0x00000001U        /*!< Transmit data register empty     */
-#define  FMPI2C_ISR_TXIS                      0x00000002U        /*!< Transmit interrupt status        */
-#define  FMPI2C_ISR_RXNE                      0x00000004U        /*!< Receive data register not empty  */
-#define  FMPI2C_ISR_ADDR                      0x00000008U        /*!< Address matched (slave mode)     */
-#define  FMPI2C_ISR_NACKF                     0x00000010U        /*!< NACK received flag               */
-#define  FMPI2C_ISR_STOPF                     0x00000020U        /*!< STOP detection flag              */
-#define  FMPI2C_ISR_TC                        0x00000040U        /*!< Transfer complete (master mode)  */
-#define  FMPI2C_ISR_TCR                       0x00000080U        /*!< Transfer complete reload         */
-#define  FMPI2C_ISR_BERR                      0x00000100U        /*!< Bus error                        */
-#define  FMPI2C_ISR_ARLO                      0x00000200U        /*!< Arbitration lost                 */
-#define  FMPI2C_ISR_OVR                       0x00000400U        /*!< Overrun/Underrun                 */
-#define  FMPI2C_ISR_PECERR                    0x00000800U        /*!< PEC error in reception           */
-#define  FMPI2C_ISR_TIMEOUT                   0x00001000U        /*!< Timeout or Tlow detection flag   */
-#define  FMPI2C_ISR_ALERT                     0x00002000U        /*!< SMBus alert                      */
-#define  FMPI2C_ISR_BUSY                      0x00008000U        /*!< Bus busy                         */
-#define  FMPI2C_ISR_DIR                       0x00010000U        /*!< Transfer direction (slave mode)  */
-#define  FMPI2C_ISR_ADDCODE                   0x00FE0000U        /*!< Address match code (slave mode)  */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define  FMPI2C_ICR_ADDRCF                    0x00000008U        /*!< Address matched clear flag  */
-#define  FMPI2C_ICR_NACKCF                    0x00000010U        /*!< NACK clear flag             */
-#define  FMPI2C_ICR_STOPCF                    0x00000020U        /*!< STOP detection clear flag   */
-#define  FMPI2C_ICR_BERRCF                    0x00000100U        /*!< Bus error clear flag        */
-#define  FMPI2C_ICR_ARLOCF                    0x00000200U        /*!< Arbitration lost clear flag */
-#define  FMPI2C_ICR_OVRCF                     0x00000400U        /*!< Overrun/Underrun clear flag */
-#define  FMPI2C_ICR_PECCF                     0x00000800U        /*!< PAC error clear flag        */
-#define  FMPI2C_ICR_TIMOUTCF                  0x00001000U        /*!< Timeout clear flag          */
-#define  FMPI2C_ICR_ALERTCF                   0x00002000U        /*!< Alert clear flag            */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define  FMPI2C_PECR_PEC                      0x000000FFU        /*!< PEC register */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define  FMPI2C_RXDR_RXDATA                   0x000000FFU        /*!< 8-bit receive data */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define  FMPI2C_TXDR_TXDATA                   0x000000FFU        /*!< 8-bit transmit data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Independent WATCHDOG                             */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         0x01U               /*!<Watchdog prescaler value update      */
-#define  IWDG_SR_RVU                         0x02U               /*!<Watchdog counter reload value update */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                             Power Control                                  */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
-#define  PWR_CR_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
-#define  PWR_CR_CWUF                         0x00000004U     /*!< Clear Wakeup Flag                   */
-#define  PWR_CR_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
-#define  PWR_CR_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
-
-#define  PWR_CR_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        0x00000020U     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        0x00000040U     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        0x00000080U     /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
-
-#define  PWR_CR_DBP                          0x00000100U     /*!< Disable Backup Domain write protection                     */
-#define  PWR_CR_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                              */
-#define  PWR_CR_LPLVDS                       0x00000400U     /*!< Low Power Regulator Low Voltage in Deep Sleep mode         */
-#define  PWR_CR_MRLVDS                       0x00000800U     /*!< Main Regulator Low Voltage in Deep Sleep mode              */
-#define  PWR_CR_ADCDC1                       0x00002000U     /*!< Refer to AN4073 on how to use this bit                     */
-
-#define  PWR_CR_VOS                          0x0000C000U     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
-#define  PWR_CR_VOS_0                        0x00004000U     /*!< Bit 0 */
-#define  PWR_CR_VOS_1                        0x00008000U     /*!< Bit 1 */
-
-#define  PWR_CR_FMSSR                        0x00100000U     /*!< Flash Memory Sleep System Run        */
-#define  PWR_CR_FISSR                        0x00200000U     /*!< Flash Interface Stop while System Run */
-/* Legacy define */
-#define  PWR_CR_PMODE                        PWR_CR_VOS
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         0x00000001U     /*!< Wakeup Flag                                      */
-#define  PWR_CSR_SBF                         0x00000002U     /*!< Standby Flag                                     */
-#define  PWR_CSR_PVDO                        0x00000004U     /*!< PVD Output                                       */
-#define  PWR_CSR_BRR                         0x00000008U     /*!< Backup regulator ready                           */
-#define  PWR_CSR_EWUP                        0x00000100U     /*!< Enable WKUP pin                                  */
-#define  PWR_CSR_BRE                         0x00000200U     /*!< Backup regulator enable                          */
-#define  PWR_CSR_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
-
-/* Legacy define */
-#define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        0x00000001U
-#define  RCC_CR_HSIRDY                       0x00000002U
-
-#define  RCC_CR_HSITRIM                      0x000000F8U
-#define  RCC_CR_HSITRIM_0                    0x00000008U/*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    0x00000010U/*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    0x00000020U/*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    0x00000040U/*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    0x00000080U/*!<Bit 4 */
-
-#define  RCC_CR_HSICAL                       0x0000FF00U
-#define  RCC_CR_HSICAL_0                     0x00000100U/*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     0x00000200U/*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     0x00000400U/*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     0x00000800U/*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     0x00001000U/*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     0x00002000U/*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     0x00004000U/*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     0x00008000U/*!<Bit 7 */
-
-#define  RCC_CR_HSEON                        0x00010000U
-#define  RCC_CR_HSERDY                       0x00020000U
-#define  RCC_CR_HSEBYP                       0x00040000U
-#define  RCC_CR_CSSON                        0x00080000U
-#define  RCC_CR_PLLON                        0x01000000U
-#define  RCC_CR_PLLRDY                       0x02000000U
-
-/********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    0x0000003FU
-#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
-#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
-#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
-#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
-#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
-#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
-
-#define  RCC_PLLCFGR_PLLN                     0x00007FC0U
-#define  RCC_PLLCFGR_PLLN_0                   0x00000040U
-#define  RCC_PLLCFGR_PLLN_1                   0x00000080U
-#define  RCC_PLLCFGR_PLLN_2                   0x00000100U
-#define  RCC_PLLCFGR_PLLN_3                   0x00000200U
-#define  RCC_PLLCFGR_PLLN_4                   0x00000400U
-#define  RCC_PLLCFGR_PLLN_5                   0x00000800U
-#define  RCC_PLLCFGR_PLLN_6                   0x00001000U
-#define  RCC_PLLCFGR_PLLN_7                   0x00002000U
-#define  RCC_PLLCFGR_PLLN_8                   0x00004000U
-
-#define  RCC_PLLCFGR_PLLP                    0x00030000U
-#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
-#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
-
-#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
-
-#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
-#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
-#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
-#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
-#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
-
-#define  RCC_PLLCFGR_PLLR                    0x70000000U
-#define  RCC_PLLCFGR_PLLR_0                  0x10000000U
-#define  RCC_PLLCFGR_PLLR_1                  0x20000000U
-#define  RCC_PLLCFGR_PLLR_2                  0x40000000U
-/********************  Bit definition for RCC_CFGR register  ******************/
-/*!< SW configuration */
-#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
-
-#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
-
-#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
-
-#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
-
-/*!< MCO1EN configuration */
-#define  RCC_CFGR_MCO1EN                     0x00000100U        /*!< MCO1EN bit */
-
-/*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
-
-/*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     0x001F0000U
-#define  RCC_CFGR_RTCPRE_0                   0x00010000U
-#define  RCC_CFGR_RTCPRE_1                   0x00020000U
-#define  RCC_CFGR_RTCPRE_2                   0x00040000U
-#define  RCC_CFGR_RTCPRE_3                   0x00080000U
-#define  RCC_CFGR_RTCPRE_4                   0x00100000U
-
-/*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       0x00600000U
-#define  RCC_CFGR_MCO1_0                     0x00200000U
-#define  RCC_CFGR_MCO1_1                     0x00400000U
-
-#define  RCC_CFGR_MCO1PRE                    0x07000000U
-#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
-#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
-#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
-
-#define  RCC_CFGR_MCO2PRE                    0x38000000U
-#define  RCC_CFGR_MCO2PRE_0                  0x08000000U
-#define  RCC_CFGR_MCO2PRE_1                  0x10000000U
-#define  RCC_CFGR_MCO2PRE_2                  0x20000000U
-
-#define  RCC_CFGR_MCO2                       0xC0000000U
-#define  RCC_CFGR_MCO2_0                     0x40000000U
-#define  RCC_CFGR_MCO2_1                     0x80000000U
-
-/********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     0x00000001U
-#define  RCC_CIR_LSERDYF                     0x00000002U
-#define  RCC_CIR_HSIRDYF                     0x00000004U
-#define  RCC_CIR_HSERDYF                     0x00000008U
-#define  RCC_CIR_PLLRDYF                     0x00000010U
-
-#define  RCC_CIR_CSSF                        0x00000080U
-#define  RCC_CIR_LSIRDYIE                    0x00000100U
-#define  RCC_CIR_LSERDYIE                    0x00000200U
-#define  RCC_CIR_HSIRDYIE                    0x00000400U
-#define  RCC_CIR_HSERDYIE                    0x00000800U
-#define  RCC_CIR_PLLRDYIE                    0x00001000U
-
-#define  RCC_CIR_LSIRDYC                     0x00010000U
-#define  RCC_CIR_LSERDYC                     0x00020000U
-#define  RCC_CIR_HSIRDYC                     0x00040000U
-#define  RCC_CIR_HSERDYC                     0x00080000U
-#define  RCC_CIR_PLLRDYC                     0x00100000U
-
-#define  RCC_CIR_CSSC                        0x00800000U
-
-/********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
-#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
-#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
-#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
-#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
-#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
-#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
-#define  RCC_AHB1RSTR_RNGRST                 0x80000000U
-
-/********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM5RST                0x00000008U
-#define  RCC_APB1RSTR_TIM6RST                0x00000010U
-#define  RCC_APB1RSTR_LPTIM1RST              0x00000200U
-#define  RCC_APB1RSTR_WWDGRST                0x00000800U
-#define  RCC_APB1RSTR_SPI2RST                0x00004000U
-#define  RCC_APB1RSTR_USART2RST              0x00020000U
-#define  RCC_APB1RSTR_I2C1RST                0x00200000U
-#define  RCC_APB1RSTR_I2C2RST                0x00400000U
-#define  RCC_APB1RSTR_FMPI2C1RST             0x01000000U
-#define  RCC_APB1RSTR_PWRRST                 0x10000000U
-#define  RCC_APB1RSTR_DACRST                 0x20000000U
-
-/********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                0x00000001U
-#define  RCC_APB2RSTR_USART1RST              0x00000010U
-#define  RCC_APB2RSTR_USART6RST              0x00000020U
-#define  RCC_APB2RSTR_ADCRST                 0x00000100U
-#define  RCC_APB2RSTR_SPI1RST                0x00001000U
-#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
-#define  RCC_APB2RSTR_TIM9RST                0x00010000U
-#define  RCC_APB2RSTR_TIM11RST               0x00040000U
-#define  RCC_APB2RSTR_SPI5RST                0x00100000U
-
-/********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
-#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
-#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
-#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
-#define  RCC_AHB1ENR_CRCEN                   0x00001000U
-#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
-#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
-#define  RCC_AHB1ENR_RNGEN                   0x80000000U
-
-/********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM5EN                  0x00000008U
-#define  RCC_APB1ENR_TIM6EN                  0x00000010U
-#define  RCC_APB1ENR_LPTIM1EN                0x00000200U
-#define  RCC_APB1ENR_RTCAPBEN                0x00000400U
-#define  RCC_APB1ENR_WWDGEN                  0x00000800U
-#define  RCC_APB1ENR_SPI2EN                  0x00004000U
-#define  RCC_APB1ENR_USART2EN                0x00020000U
-#define  RCC_APB1ENR_I2C1EN                  0x00200000U
-#define  RCC_APB1ENR_I2C2EN                  0x00400000U
-#define  RCC_APB1ENR_FMPI2C1EN               0x01000000U
-#define  RCC_APB1ENR_PWREN                   0x10000000U
-#define  RCC_APB1ENR_DACEN                   0x20000000U
-
-/********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  0x00000001U
-#define  RCC_APB2ENR_USART1EN                0x00000010U
-#define  RCC_APB2ENR_USART6EN                0x00000020U
-#define  RCC_APB2ENR_ADC1EN                  0x00000100U
-#define  RCC_APB2ENR_SPI1EN                  0x00001000U
-#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
-#define  RCC_APB2ENR_EXTITEN                 0x00008000U
-#define  RCC_APB2ENR_TIM9EN                  0x00010000U
-#define  RCC_APB2ENR_TIM11EN                 0x00040000U
-#define  RCC_APB2ENR_SPI5EN                  0x00100000U
-
-/********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
-#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
-#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
-#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
-#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
-#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
-#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
-#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
-#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
-#define  RCC_AHB1LPENR_RNGLPEN               0x80000000U
-
-/********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
-#define  RCC_APB1LPENR_TIM6LPEN              0x00000010U
-#define  RCC_APB1LPENR_LPTIM1LPEN            0x00000200U
-#define  RCC_APB1LPENR_RTCAPBLPEN            0x00000400U
-#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
-#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U
-#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
-#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
-#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
-#define  RCC_APB1LPENR_FMPI2C1LPEN           0x01000000U
-#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
-#define  RCC_APB1LPENR_DACLPEN               0x20000000U
-
-/********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
-#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
-#define  RCC_APB2LPENR_USART6LPEN            0x00000020U
-#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
-#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
-#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
-#define  RCC_APB2LPENR_EXTITLPEN             0x00008000U
-#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
-#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
-#define  RCC_APB2LPENR_SPI5LPEN              0x00100000U
-
-/********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      0x00000001U
-#define  RCC_BDCR_LSERDY                     0x00000002U
-#define  RCC_BDCR_LSEBYP                     0x00000004U
-#define  RCC_BDCR_LSEMOD                     0x00000008U
-
-#define  RCC_BDCR_RTCSEL                    0x00000300U
-#define  RCC_BDCR_RTCSEL_0                  0x00000100U
-#define  RCC_BDCR_RTCSEL_1                  0x00000200U
-
-#define  RCC_BDCR_RTCEN                      0x00008000U
-#define  RCC_BDCR_BDRST                      0x00010000U
-
-/********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       0x00000001U
-#define  RCC_CSR_LSIRDY                      0x00000002U
-#define  RCC_CSR_RMVF                        0x01000000U
-#define  RCC_CSR_BORRSTF                     0x02000000U
-#define  RCC_CSR_PADRSTF                     0x04000000U
-#define  RCC_CSR_PORRSTF                     0x08000000U
-#define  RCC_CSR_SFTRSTF                     0x10000000U
-#define  RCC_CSR_WDGRSTF                     0x20000000U
-#define  RCC_CSR_WWDGRSTF                    0x40000000U
-#define  RCC_CSR_LPWRRSTF                    0x80000000U
-
-/********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    0x00001FFFU
-#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
-#define  RCC_SSCGR_SPREADSEL                 0x40000000U
-#define  RCC_SSCGR_SSCGEN                    0x80000000U
-
-/********************  Bit definition for RCC_DCKCFGR register  ***************/
-#define  RCC_DCKCFGR_TIMPRE                  0x01000000U
-#define  RCC_DCKCFGR_I2SSRC                  0x06000000U
-#define  RCC_DCKCFGR_I2SSRC_0                0x02000000U
-#define  RCC_DCKCFGR_I2SSRC_1                0x04000000U
-
-/********************  Bit definition for RCC_CKGATENR register  **************/
-#define  RCC_CKGATENR_AHB2APB1_CKEN          0x00000001U
-#define  RCC_CKGATENR_AHB2APB2_CKEN          0x00000002U
-#define  RCC_CKGATENR_CM4DBG_CKEN            0x00000004U
-#define  RCC_CKGATENR_SPARE_CKEN             0x00000008U
-#define  RCC_CKGATENR_SRAM_CKEN              0x00000010U
-#define  RCC_CKGATENR_FLITF_CKEN             0x00000020U
-#define  RCC_CKGATENR_RCC_CKEN               0x00000040U
-
-/********************  Bit definition for RCC_DCKCFGR2 register  **************/
-#define  RCC_DCKCFGR2_FMPI2C1SEL             0x00C00000U
-#define  RCC_DCKCFGR2_FMPI2C1SEL_0           0x00400000U
-#define  RCC_DCKCFGR2_FMPI2C1SEL_1           0x00800000U
-#define  RCC_DCKCFGR2_LPTIM1SEL              0xC0000000U
-#define  RCC_DCKCFGR2_LPTIM1SEL_0            0x40000000U
-#define  RCC_DCKCFGR2_LPTIM1SEL_1            0x80000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    RNG                                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN                         0x00000004U
-#define RNG_CR_IE                            0x00000008U
-
-/********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY                          0x00000001U
-#define RNG_SR_CECS                          0x00000002U
-#define RNG_SR_SECS                          0x00000004U
-#define RNG_SR_CEIS                          0x00000020U
-#define RNG_SR_SEIS                          0x00000040U
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            0x00400000U
-#define RTC_TR_HT                            0x00300000U
-#define RTC_TR_HT_0                          0x00100000U
-#define RTC_TR_HT_1                          0x00200000U
-#define RTC_TR_HU                            0x000F0000U
-#define RTC_TR_HU_0                          0x00010000U
-#define RTC_TR_HU_1                          0x00020000U
-#define RTC_TR_HU_2                          0x00040000U
-#define RTC_TR_HU_3                          0x00080000U
-#define RTC_TR_MNT                           0x00007000U
-#define RTC_TR_MNT_0                         0x00001000U
-#define RTC_TR_MNT_1                         0x00002000U
-#define RTC_TR_MNT_2                         0x00004000U
-#define RTC_TR_MNU                           0x00000F00U
-#define RTC_TR_MNU_0                         0x00000100U
-#define RTC_TR_MNU_1                         0x00000200U
-#define RTC_TR_MNU_2                         0x00000400U
-#define RTC_TR_MNU_3                         0x00000800U
-#define RTC_TR_ST                            0x00000070U
-#define RTC_TR_ST_0                          0x00000010U
-#define RTC_TR_ST_1                          0x00000020U
-#define RTC_TR_ST_2                          0x00000040U
-#define RTC_TR_SU                            0x0000000FU
-#define RTC_TR_SU_0                          0x00000001U
-#define RTC_TR_SU_1                          0x00000002U
-#define RTC_TR_SU_2                          0x00000004U
-#define RTC_TR_SU_3                          0x00000008U
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            0x00F00000U
-#define RTC_DR_YT_0                          0x00100000U
-#define RTC_DR_YT_1                          0x00200000U
-#define RTC_DR_YT_2                          0x00400000U
-#define RTC_DR_YT_3                          0x00800000U
-#define RTC_DR_YU                            0x000F0000U
-#define RTC_DR_YU_0                          0x00010000U
-#define RTC_DR_YU_1                          0x00020000U
-#define RTC_DR_YU_2                          0x00040000U
-#define RTC_DR_YU_3                          0x00080000U
-#define RTC_DR_WDU                           0x0000E000U
-#define RTC_DR_WDU_0                         0x00002000U
-#define RTC_DR_WDU_1                         0x00004000U
-#define RTC_DR_WDU_2                         0x00008000U
-#define RTC_DR_MT                            0x00001000U
-#define RTC_DR_MU                            0x00000F00U
-#define RTC_DR_MU_0                          0x00000100U
-#define RTC_DR_MU_1                          0x00000200U
-#define RTC_DR_MU_2                          0x00000400U
-#define RTC_DR_MU_3                          0x00000800U
-#define RTC_DR_DT                            0x00000030U
-#define RTC_DR_DT_0                          0x00000010U
-#define RTC_DR_DT_1                          0x00000020U
-#define RTC_DR_DU                            0x0000000FU
-#define RTC_DR_DU_0                          0x00000001U
-#define RTC_DR_DU_1                          0x00000002U
-#define RTC_DR_DU_2                          0x00000004U
-#define RTC_DR_DU_3                          0x00000008U
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           0x00800000U
-#define RTC_CR_OSEL                          0x00600000U
-#define RTC_CR_OSEL_0                        0x00200000U
-#define RTC_CR_OSEL_1                        0x00400000U
-#define RTC_CR_POL                           0x00100000U
-#define RTC_CR_COSEL                         0x00080000U
-#define RTC_CR_BCK                           0x00040000U
-#define RTC_CR_SUB1H                         0x00020000U
-#define RTC_CR_ADD1H                         0x00010000U
-#define RTC_CR_TSIE                          0x00008000U
-#define RTC_CR_WUTIE                         0x00004000U
-#define RTC_CR_ALRBIE                        0x00002000U
-#define RTC_CR_ALRAIE                        0x00001000U
-#define RTC_CR_TSE                           0x00000800U
-#define RTC_CR_WUTE                          0x00000400U
-#define RTC_CR_ALRBE                         0x00000200U
-#define RTC_CR_ALRAE                         0x00000100U
-#define RTC_CR_DCE                           0x00000080U
-#define RTC_CR_FMT                           0x00000040U
-#define RTC_CR_BYPSHAD                       0x00000020U
-#define RTC_CR_REFCKON                       0x00000010U
-#define RTC_CR_TSEDGE                        0x00000008U
-#define RTC_CR_WUCKSEL                       0x00000007U
-#define RTC_CR_WUCKSEL_0                     0x00000001U
-#define RTC_CR_WUCKSEL_1                     0x00000002U
-#define RTC_CR_WUCKSEL_2                     0x00000004U
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      0x00010000U
-#define RTC_ISR_TAMP1F                       0x00002000U
-#define RTC_ISR_TAMP2F                       0x00004000U
-#define RTC_ISR_TSOVF                        0x00001000U
-#define RTC_ISR_TSF                          0x00000800U
-#define RTC_ISR_WUTF                         0x00000400U
-#define RTC_ISR_ALRBF                        0x00000200U
-#define RTC_ISR_ALRAF                        0x00000100U
-#define RTC_ISR_INIT                         0x00000080U
-#define RTC_ISR_INITF                        0x00000040U
-#define RTC_ISR_RSF                          0x00000020U
-#define RTC_ISR_INITS                        0x00000010U
-#define RTC_ISR_SHPF                         0x00000008U
-#define RTC_ISR_WUTWF                        0x00000004U
-#define RTC_ISR_ALRBWF                       0x00000002U
-#define RTC_ISR_ALRAWF                       0x00000001U
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    0x007F0000U
-#define RTC_PRER_PREDIV_S                    0x00007FFFU
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS                       0x00000080U
-#define RTC_CALIBR_DC                        0x0000001FU
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      0x80000000U
-#define RTC_ALRMAR_WDSEL                     0x40000000U
-#define RTC_ALRMAR_DT                        0x30000000U
-#define RTC_ALRMAR_DT_0                      0x10000000U
-#define RTC_ALRMAR_DT_1                      0x20000000U
-#define RTC_ALRMAR_DU                        0x0F000000U
-#define RTC_ALRMAR_DU_0                      0x01000000U
-#define RTC_ALRMAR_DU_1                      0x02000000U
-#define RTC_ALRMAR_DU_2                      0x04000000U
-#define RTC_ALRMAR_DU_3                      0x08000000U
-#define RTC_ALRMAR_MSK3                      0x00800000U
-#define RTC_ALRMAR_PM                        0x00400000U
-#define RTC_ALRMAR_HT                        0x00300000U
-#define RTC_ALRMAR_HT_0                      0x00100000U
-#define RTC_ALRMAR_HT_1                      0x00200000U
-#define RTC_ALRMAR_HU                        0x000F0000U
-#define RTC_ALRMAR_HU_0                      0x00010000U
-#define RTC_ALRMAR_HU_1                      0x00020000U
-#define RTC_ALRMAR_HU_2                      0x00040000U
-#define RTC_ALRMAR_HU_3                      0x00080000U
-#define RTC_ALRMAR_MSK2                      0x00008000U
-#define RTC_ALRMAR_MNT                       0x00007000U
-#define RTC_ALRMAR_MNT_0                     0x00001000U
-#define RTC_ALRMAR_MNT_1                     0x00002000U
-#define RTC_ALRMAR_MNT_2                     0x00004000U
-#define RTC_ALRMAR_MNU                       0x00000F00U
-#define RTC_ALRMAR_MNU_0                     0x00000100U
-#define RTC_ALRMAR_MNU_1                     0x00000200U
-#define RTC_ALRMAR_MNU_2                     0x00000400U
-#define RTC_ALRMAR_MNU_3                     0x00000800U
-#define RTC_ALRMAR_MSK1                      0x00000080U
-#define RTC_ALRMAR_ST                        0x00000070U
-#define RTC_ALRMAR_ST_0                      0x00000010U
-#define RTC_ALRMAR_ST_1                      0x00000020U
-#define RTC_ALRMAR_ST_2                      0x00000040U
-#define RTC_ALRMAR_SU                        0x0000000FU
-#define RTC_ALRMAR_SU_0                      0x00000001U
-#define RTC_ALRMAR_SU_1                      0x00000002U
-#define RTC_ALRMAR_SU_2                      0x00000004U
-#define RTC_ALRMAR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      0x80000000U
-#define RTC_ALRMBR_WDSEL                     0x40000000U
-#define RTC_ALRMBR_DT                        0x30000000U
-#define RTC_ALRMBR_DT_0                      0x10000000U
-#define RTC_ALRMBR_DT_1                      0x20000000U
-#define RTC_ALRMBR_DU                        0x0F000000U
-#define RTC_ALRMBR_DU_0                      0x01000000U
-#define RTC_ALRMBR_DU_1                      0x02000000U
-#define RTC_ALRMBR_DU_2                      0x04000000U
-#define RTC_ALRMBR_DU_3                      0x08000000U
-#define RTC_ALRMBR_MSK3                      0x00800000U
-#define RTC_ALRMBR_PM                        0x00400000U
-#define RTC_ALRMBR_HT                        0x00300000U
-#define RTC_ALRMBR_HT_0                      0x00100000U
-#define RTC_ALRMBR_HT_1                      0x00200000U
-#define RTC_ALRMBR_HU                        0x000F0000U
-#define RTC_ALRMBR_HU_0                      0x00010000U
-#define RTC_ALRMBR_HU_1                      0x00020000U
-#define RTC_ALRMBR_HU_2                      0x00040000U
-#define RTC_ALRMBR_HU_3                      0x00080000U
-#define RTC_ALRMBR_MSK2                      0x00008000U
-#define RTC_ALRMBR_MNT                       0x00007000U
-#define RTC_ALRMBR_MNT_0                     0x00001000U
-#define RTC_ALRMBR_MNT_1                     0x00002000U
-#define RTC_ALRMBR_MNT_2                     0x00004000U
-#define RTC_ALRMBR_MNU                       0x00000F00U
-#define RTC_ALRMBR_MNU_0                     0x00000100U
-#define RTC_ALRMBR_MNU_1                     0x00000200U
-#define RTC_ALRMBR_MNU_2                     0x00000400U
-#define RTC_ALRMBR_MNU_3                     0x00000800U
-#define RTC_ALRMBR_MSK1                      0x00000080U
-#define RTC_ALRMBR_ST                        0x00000070U
-#define RTC_ALRMBR_ST_0                      0x00000010U
-#define RTC_ALRMBR_ST_1                      0x00000020U
-#define RTC_ALRMBR_ST_2                      0x00000040U
-#define RTC_ALRMBR_SU                        0x0000000FU
-#define RTC_ALRMBR_SU_0                      0x00000001U
-#define RTC_ALRMBR_SU_1                      0x00000002U
-#define RTC_ALRMBR_SU_2                      0x00000004U
-#define RTC_ALRMBR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          0x000000FFU
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           0x0000FFFFU
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     0x00007FFFU
-#define RTC_SHIFTR_ADD1S                     0x80000000U
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          0x00400000U
-#define RTC_TSTR_HT                          0x00300000U
-#define RTC_TSTR_HT_0                        0x00100000U
-#define RTC_TSTR_HT_1                        0x00200000U
-#define RTC_TSTR_HU                          0x000F0000U
-#define RTC_TSTR_HU_0                        0x00010000U
-#define RTC_TSTR_HU_1                        0x00020000U
-#define RTC_TSTR_HU_2                        0x00040000U
-#define RTC_TSTR_HU_3                        0x00080000U
-#define RTC_TSTR_MNT                         0x00007000U
-#define RTC_TSTR_MNT_0                       0x00001000U
-#define RTC_TSTR_MNT_1                       0x00002000U
-#define RTC_TSTR_MNT_2                       0x00004000U
-#define RTC_TSTR_MNU                         0x00000F00U
-#define RTC_TSTR_MNU_0                       0x00000100U
-#define RTC_TSTR_MNU_1                       0x00000200U
-#define RTC_TSTR_MNU_2                       0x00000400U
-#define RTC_TSTR_MNU_3                       0x00000800U
-#define RTC_TSTR_ST                          0x00000070U
-#define RTC_TSTR_ST_0                        0x00000010U
-#define RTC_TSTR_ST_1                        0x00000020U
-#define RTC_TSTR_ST_2                        0x00000040U
-#define RTC_TSTR_SU                          0x0000000FU
-#define RTC_TSTR_SU_0                        0x00000001U
-#define RTC_TSTR_SU_1                        0x00000002U
-#define RTC_TSTR_SU_2                        0x00000004U
-#define RTC_TSTR_SU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         0x0000E000U
-#define RTC_TSDR_WDU_0                       0x00002000U
-#define RTC_TSDR_WDU_1                       0x00004000U
-#define RTC_TSDR_WDU_2                       0x00008000U
-#define RTC_TSDR_MT                          0x00001000U
-#define RTC_TSDR_MU                          0x00000F00U
-#define RTC_TSDR_MU_0                        0x00000100U
-#define RTC_TSDR_MU_1                        0x00000200U
-#define RTC_TSDR_MU_2                        0x00000400U
-#define RTC_TSDR_MU_3                        0x00000800U
-#define RTC_TSDR_DT                          0x00000030U
-#define RTC_TSDR_DT_0                        0x00000010U
-#define RTC_TSDR_DT_1                        0x00000020U
-#define RTC_TSDR_DU                          0x0000000FU
-#define RTC_TSDR_DU_0                        0x00000001U
-#define RTC_TSDR_DU_1                        0x00000002U
-#define RTC_TSDR_DU_2                        0x00000004U
-#define RTC_TSDR_DU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        0x00008000U
-#define RTC_CALR_CALW8                       0x00004000U
-#define RTC_CALR_CALW16                      0x00002000U
-#define RTC_CALR_CALM                        0x000001FFU
-#define RTC_CALR_CALM_0                      0x00000001U
-#define RTC_CALR_CALM_1                      0x00000002U
-#define RTC_CALR_CALM_2                      0x00000004U
-#define RTC_CALR_CALM_3                      0x00000008U
-#define RTC_CALR_CALM_4                      0x00000010U
-#define RTC_CALR_CALM_5                      0x00000020U
-#define RTC_CALR_CALM_6                      0x00000040U
-#define RTC_CALR_CALM_7                      0x00000080U
-#define RTC_CALR_CALM_8                      0x00000100U
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               0x00040000U
-#define RTC_TAFCR_TSINSEL                    0x00020000U
-#define RTC_TAFCR_TAMPINSEL                  0x00010000U
-#define RTC_TAFCR_TAMPPUDIS                  0x00008000U
-#define RTC_TAFCR_TAMPPRCH                   0x00006000U
-#define RTC_TAFCR_TAMPPRCH_0                 0x00002000U
-#define RTC_TAFCR_TAMPPRCH_1                 0x00004000U
-#define RTC_TAFCR_TAMPFLT                    0x00001800U
-#define RTC_TAFCR_TAMPFLT_0                  0x00000800U
-#define RTC_TAFCR_TAMPFLT_1                  0x00001000U
-#define RTC_TAFCR_TAMPFREQ                   0x00000700U
-#define RTC_TAFCR_TAMPFREQ_0                 0x00000100U
-#define RTC_TAFCR_TAMPFREQ_1                 0x00000200U
-#define RTC_TAFCR_TAMPFREQ_2                 0x00000400U
-#define RTC_TAFCR_TAMPTS                     0x00000080U
-#define RTC_TAFCR_TAMP2TRG                   0x00000010U
-#define RTC_TAFCR_TAMP2E                     0x00000008U
-#define RTC_TAFCR_TAMPIE                     0x00000004U
-#define RTC_TAFCR_TAMP1TRG                   0x00000002U
-#define RTC_TAFCR_TAMP1E                     0x00000001U
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  0x0F000000U
-#define RTC_ALRMASSR_MASKSS_0                0x01000000U
-#define RTC_ALRMASSR_MASKSS_1                0x02000000U
-#define RTC_ALRMASSR_MASKSS_2                0x04000000U
-#define RTC_ALRMASSR_MASKSS_3                0x08000000U
-#define RTC_ALRMASSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
-#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
-#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
-#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
-#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
-#define RTC_ALRMBSSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           0xFFFFFFFFU
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        0x00000001U            /*!<Clock Phase      */
-#define  SPI_CR1_CPOL                        0x00000002U            /*!<Clock Polarity   */
-#define  SPI_CR1_MSTR                        0x00000004U            /*!<Master Selection */
-
-#define  SPI_CR1_BR                          0x00000038U            /*!<BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        0x00000008U            /*!<Bit 0 */
-#define  SPI_CR1_BR_1                        0x00000010U            /*!<Bit 1 */
-#define  SPI_CR1_BR_2                        0x00000020U            /*!<Bit 2 */
-
-#define  SPI_CR1_SPE                         0x00000040U            /*!<SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    0x00000080U            /*!<Frame Format                        */
-#define  SPI_CR1_SSI                         0x00000100U            /*!<Internal slave select               */
-#define  SPI_CR1_SSM                         0x00000200U            /*!<Software slave management           */
-#define  SPI_CR1_RXONLY                      0x00000400U            /*!<Receive only                        */
-#define  SPI_CR1_DFF                         0x00000800U            /*!<Data Frame Format                   */
-#define  SPI_CR1_CRCNEXT                     0x00001000U            /*!<Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       0x00002000U            /*!<Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      0x00004000U            /*!<Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    0x00008000U            /*!<Bidirectional data mode enable      */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     0x00000001U               /*!<Rx Buffer DMA Enable                 */
-#define  SPI_CR2_TXDMAEN                     0x00000002U               /*!<Tx Buffer DMA Enable                 */
-#define  SPI_CR2_SSOE                        0x00000004U               /*!<SS Output Enable                     */
-#define  SPI_CR2_FRF                         0x00000010U               /*!<Frame Format                         */
-#define  SPI_CR2_ERRIE                       0x00000020U               /*!<Error Interrupt Enable               */
-#define  SPI_CR2_RXNEIE                      0x00000040U               /*!<RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       0x00000080U               /*!<Tx buffer Empty Interrupt Enable     */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         0x00000001U               /*!<Receive buffer Not Empty */
-#define  SPI_SR_TXE                          0x00000002U               /*!<Transmit buffer Empty    */
-#define  SPI_SR_CHSIDE                       0x00000004U               /*!<Channel side             */
-#define  SPI_SR_UDR                          0x00000008U               /*!<Underrun flag            */
-#define  SPI_SR_CRCERR                       0x00000010U               /*!<CRC Error flag           */
-#define  SPI_SR_MODF                         0x00000020U               /*!<Mode fault               */
-#define  SPI_SR_OVR                          0x00000040U               /*!<Overrun flag             */
-#define  SPI_SR_BSY                          0x00000080U               /*!<Busy flag                */
-#define  SPI_SR_FRE                          0x00000100U               /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           0x0000FFFFU            /*!<Data Register           */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   0x0000FFFFU            /*!<CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    0x0000FFFFU            /*!<Rx CRC Register         */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    0x0000FFFFU            /*!<Tx CRC Register         */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   0x00000001U            /*!<Channel length (number of bits per audio channel) */
-
-#define  SPI_I2SCFGR_DATLEN                  0x00000006U            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define  SPI_I2SCFGR_DATLEN_0                0x00000002U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                0x00000004U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_CKPOL                   0x00000008U            /*!<steady state clock polarity               */
-
-#define  SPI_I2SCFGR_I2SSTD                  0x00000030U            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U            /*!<PCM frame synchronization                 */
-
-#define  SPI_I2SCFGR_I2SCFG                  0x00000300U            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_I2SE                    0x00000400U            /*!<I2S Enable         */
-#define  SPI_I2SCFGR_I2SMOD                  0x00000800U            /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    0x000000FFU            /*!<I2S Linear prescaler         */
-#define  SPI_I2SPR_ODD                       0x00000100U            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     0x00000200U            /*!<Master Clock Output Enable   */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 SYSCFG                                     */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
-#define SYSCFG_MEMRMP_MEM_MODE          0x00000007U /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        0x00000001U
-#define SYSCFG_MEMRMP_MEM_MODE_1        0x00000002U
-#define SYSCFG_MEMRMP_MEM_MODE_2        0x00000004U
-
-/******************  Bit definition for SYSCFG_PMC register  ******************/
-#define SYSCFG_PMC_ADC1DC2              0x00010000U /*!< Refer to AN4073 on how to use this bit  */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
-/** 
-  * @brief   EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
-
-/** 
-  * @brief   EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
-
-/** 
-  * @brief   EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
-
-/** 
-  * @brief   EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
-/** 
-  * @brief   EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
-
-/** 
-  * @brief   EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
-
-/** 
-  * @brief   EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
-
-/** 
-  * @brief   EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
-
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
-           
-/** 
-  * @brief   EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
-
-/** 
-  * @brief   EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
-
-/** 
-  * @brief   EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
-
-/** 
-  * @brief   EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
-/** 
-  * @brief   EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
-
-/** 
-  * @brief   EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
-
-/** 
-  * @brief   EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
-
-/** 
-  * @brief   EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
-
-/******************  Bit definition for SYSCFG_CMPCR register  ****************/
-#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell ready flag */
-#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell power-down */
-
-/******************  Bit definition for SYSCFG_CFGR register  *****************/
-#define SYSCFG_CFGR_FMPI2C1_SCL         0x00000001U /*!<FM+ drive capability for FMPI2C1_SCL pin */
-#define SYSCFG_CFGR_FMPI2C1_SDA         0x00000002U /*!<FM+ drive capability for FMPI2C1_SDA pin */
-
-/******************  Bit definition for SYSCFG_CFGR2 register  *****************/
-#define SYSCFG_CFGR2_LOCKUP_LOCK        0x00000001U /*!<Core Lockup lock */
-#define SYSCFG_CFGR2_PVD_LOCK           0x00000004U /*!<PVD Lock         */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    TIM                                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
-#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
-#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
-#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
-#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
-
-#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
-
-#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
-
-#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        0x0001U            /*!<Capture/Compare Preloaded Control        */
-#define  TIM_CR2_CCUS                        0x0004U            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        0x0008U            /*!<Capture/Compare DMA Selection            */
-
-#define  TIM_CR2_MMS                         0x0070U            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
-#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
-#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
-#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        0x0007U            /*!<SMS[2:0] bits (Slave mode selection)    */
-#define  TIM_SMCR_SMS_0                      0x0001U            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      0x0002U            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      0x0004U            /*!<Bit 2 */
-
-#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
-#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
-
-#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
-
-#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
-
-#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
-#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
-#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
-#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
-#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
-#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
-#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
-#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
-#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
-#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
-#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
-#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
-#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
-#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
-#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
-#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
-#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
-#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
-#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          0x01U               /*!<Update Generation                         */
-#define  TIM_EGR_CC1G                        0x02U               /*!<Capture/Compare 1 Generation              */
-#define  TIM_EGR_CC2G                        0x04U               /*!<Capture/Compare 2 Generation              */
-#define  TIM_EGR_CC3G                        0x08U               /*!<Capture/Compare 3 Generation              */
-#define  TIM_EGR_CC4G                        0x10U               /*!<Capture/Compare 4 Generation              */
-#define  TIM_EGR_COMG                        0x20U               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          0x40U               /*!<Trigger Generation                        */
-#define  TIM_EGR_BG                          0x80U               /*!<Break Generation                          */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      0x0003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    0x0001U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    0x0002U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC1FE                     0x0004U            /*!<Output Compare 1 Fast enable                 */
-#define  TIM_CCMR1_OC1PE                     0x0008U            /*!<Output Compare 1 Preload enable              */
-
-#define  TIM_CCMR1_OC1M                      0x0070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define  TIM_CCMR1_OC1M_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    0x0040U            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC1CE                     0x0080U            /*!<Output Compare 1Clear Enable                 */
-
-#define  TIM_CCMR1_CC2S                      0x0300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    0x0100U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    0x0200U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC2FE                     0x0400U            /*!<Output Compare 2 Fast enable                 */
-#define  TIM_CCMR1_OC2PE                     0x0800U            /*!<Output Compare 2 Preload enable              */
-
-#define  TIM_CCMR1_OC2M                      0x7000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define  TIM_CCMR1_OC2M_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    0x4000U            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC2CE                     0x8000U            /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      0x0003U            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define  TIM_CCMR2_CC3S_0                    0x0001U            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    0x0002U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC3FE                     0x0004U            /*!<Output Compare 3 Fast enable           */
-#define  TIM_CCMR2_OC3PE                     0x0008U            /*!<Output Compare 3 Preload enable        */
-
-#define  TIM_CCMR2_OC3M                      0x0070U            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    0x0040U            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC3CE                     0x0080U            /*!<Output Compare 3 Clear Enable */
-
-#define  TIM_CCMR2_CC4S                      0x0300U            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    0x0100U            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    0x0200U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC4FE                     0x0400U            /*!<Output Compare 4 Fast enable    */
-#define  TIM_CCMR2_OC4PE                     0x0800U            /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR2_OC4M                      0x7000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    0x4000U            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       0x0001U            /*!<Capture/Compare 1 output enable                 */
-#define  TIM_CCER_CC1P                       0x0002U            /*!<Capture/Compare 1 output Polarity               */
-#define  TIM_CCER_CC1NE                      0x0004U            /*!<Capture/Compare 1 Complementary output enable   */
-#define  TIM_CCER_CC1NP                      0x0008U            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       0x0010U            /*!<Capture/Compare 2 output enable                 */
-#define  TIM_CCER_CC2P                       0x0020U            /*!<Capture/Compare 2 output Polarity               */
-#define  TIM_CCER_CC2NE                      0x0040U            /*!<Capture/Compare 2 Complementary output enable   */
-#define  TIM_CCER_CC2NP                      0x0080U            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       0x0100U            /*!<Capture/Compare 3 output enable                 */
-#define  TIM_CCER_CC3P                       0x0200U            /*!<Capture/Compare 3 output Polarity               */
-#define  TIM_CCER_CC3NE                      0x0400U            /*!<Capture/Compare 3 Complementary output enable   */
-#define  TIM_CCER_CC3NP                      0x0800U            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       0x1000U            /*!<Capture/Compare 4 output enable                 */
-#define  TIM_CCER_CC4P                       0x2000U            /*!<Capture/Compare 4 output Polarity               */
-#define  TIM_CCER_CC4NP                      0x8000U            /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         0xFFU               /*!<Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
-
-/*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        0x00FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      0x0001U            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      0x0002U            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      0x0004U            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      0x0008U            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      0x0010U            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      0x0020U            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      0x0040U            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      0x0080U            /*!<Bit 7 */
-
-#define  TIM_BDTR_LOCK                       0x0300U            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     0x0100U            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     0x0200U            /*!<Bit 1 */
-
-#define  TIM_BDTR_OSSI                       0x0400U            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       0x0800U            /*!<Off-State Selection for Run mode  */
-#define  TIM_BDTR_BKE                        0x1000U            /*!<Break enable                      */
-#define  TIM_BDTR_BKP                        0x2000U            /*!<Break Polarity                    */
-#define  TIM_BDTR_AOE                        0x4000U            /*!<Automatic Output enable           */
-#define  TIM_BDTR_MOE                        0x8000U            /*!<Main Output enable                */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
-
-#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Low Power Timer (LPTIM)                            */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for LPTIM_ISR register  *******************/
-#define  LPTIM_ISR_CMPM                         0x00000001U            /*!< Compare match                       */
-#define  LPTIM_ISR_ARRM                         0x00000002U            /*!< Autoreload match                    */
-#define  LPTIM_ISR_EXTTRIG                      0x00000004U            /*!< External trigger edge event         */
-#define  LPTIM_ISR_CMPOK                        0x00000008U            /*!< Compare register update OK          */
-#define  LPTIM_ISR_ARROK                        0x00000010U            /*!< Autoreload register update OK       */
-#define  LPTIM_ISR_UP                           0x00000020U            /*!< Counter direction change down to up */
-#define  LPTIM_ISR_DOWN                         0x00000040U            /*!< Counter direction change up to down */
-
-/******************  Bit definition for LPTIM_ICR register  *******************/
-#define  LPTIM_ICR_CMPMCF                       0x00000001U            /*!< Compare match Clear Flag                       */
-#define  LPTIM_ICR_ARRMCF                       0x00000002U            /*!< Autoreload match Clear Flag                    */
-#define  LPTIM_ICR_EXTTRIGCF                    0x00000004U            /*!< External trigger edge event Clear Flag         */
-#define  LPTIM_ICR_CMPOKCF                      0x00000008U            /*!< Compare register update OK Clear Flag          */
-#define  LPTIM_ICR_ARROKCF                      0x00000010U            /*!< Autoreload register update OK Clear Flag       */
-#define  LPTIM_ICR_UPCF                         0x00000020U            /*!< Counter direction change down to up Clear Flag */
-#define  LPTIM_ICR_DOWNCF                       0x00000040U            /*!< Counter direction change up to down Clear Flag */
-
-/******************  Bit definition for LPTIM_IER register ********************/
-#define  LPTIM_IER_CMPMIE                       0x00000001U            /*!< Compare match Interrupt Enable                       */
-#define  LPTIM_IER_ARRMIE                       0x00000002U            /*!< Autoreload match Interrupt Enable                    */
-#define  LPTIM_IER_EXTTRIGIE                    0x00000004U            /*!< External trigger edge event Interrupt Enable         */
-#define  LPTIM_IER_CMPOKIE                      0x00000008U            /*!< Compare register update OK Interrupt Enable          */
-#define  LPTIM_IER_ARROKIE                      0x00000010U            /*!< Autoreload register update OK Interrupt Enable       */
-#define  LPTIM_IER_UPIE                         0x00000020U            /*!< Counter direction change down to up Interrupt Enable */
-#define  LPTIM_IER_DOWNIE                       0x00000040U            /*!< Counter direction change up to down Interrupt Enable */
-
-/******************  Bit definition for LPTIM_CFGR register *******************/
-#define  LPTIM_CFGR_CKSEL                       0x00000001U             /*!< Clock selector */
-
-#define  LPTIM_CFGR_CKPOL                       0x00000006U             /*!< CKPOL[1:0] bits (Clock polarity) */
-#define  LPTIM_CFGR_CKPOL_0                     0x00000002U             /*!< Bit 0 */
-#define  LPTIM_CFGR_CKPOL_1                     0x00000004U             /*!< Bit 1 */
-
-#define  LPTIM_CFGR_CKFLT                       0x00000018U             /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
-#define  LPTIM_CFGR_CKFLT_0                     0x00000008U             /*!< Bit 0 */
-#define  LPTIM_CFGR_CKFLT_1                     0x00000010U             /*!< Bit 1 */
-
-#define  LPTIM_CFGR_TRGFLT                      0x000000C0U             /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
-#define  LPTIM_CFGR_TRGFLT_0                    0x00000040U             /*!< Bit 0 */
-#define  LPTIM_CFGR_TRGFLT_1                    0x00000080U             /*!< Bit 1 */
-
-#define  LPTIM_CFGR_PRESC                       0x00000E00U             /*!< PRESC[2:0] bits (Clock prescaler) */
-#define  LPTIM_CFGR_PRESC_0                     0x00000200U             /*!< Bit 0 */
-#define  LPTIM_CFGR_PRESC_1                     0x00000400U             /*!< Bit 1 */
-#define  LPTIM_CFGR_PRESC_2                     0x00000800U             /*!< Bit 2 */
-
-#define  LPTIM_CFGR_TRIGSEL                     0x0000E000U             /*!< TRIGSEL[2:0]] bits (Trigger selector) */
-#define  LPTIM_CFGR_TRIGSEL_0                   0x00002000U             /*!< Bit 0 */
-#define  LPTIM_CFGR_TRIGSEL_1                   0x00004000U             /*!< Bit 1 */
-#define  LPTIM_CFGR_TRIGSEL_2                   0x00008000U             /*!< Bit 2 */
-
-#define  LPTIM_CFGR_TRIGEN                      0x00060000U             /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
-#define  LPTIM_CFGR_TRIGEN_0                    0x00020000U             /*!< Bit 0 */
-#define  LPTIM_CFGR_TRIGEN_1                    0x00040000U             /*!< Bit 1 */
-
-#define  LPTIM_CFGR_TIMOUT                      0x00080000U             /*!< Timout enable           */
-#define  LPTIM_CFGR_WAVE                        0x00100000U             /*!< Waveform shape          */
-#define  LPTIM_CFGR_WAVPOL                      0x00200000U             /*!< Waveform shape polarity */
-#define  LPTIM_CFGR_PRELOAD                     0x00400000U             /*!< Reg update mode         */
-#define  LPTIM_CFGR_COUNTMODE                   0x00800000U             /*!< Counter mode enable     */     
-#define  LPTIM_CFGR_ENC                         0x01000000U             /*!< Encoder mode enable     */          
-
-/******************  Bit definition for LPTIM_CR register  ********************/
-#define  LPTIM_CR_ENABLE                        0x00000001U             /*!< LPTIMer enable                 */
-#define  LPTIM_CR_SNGSTRT                       0x00000002U             /*!< Timer start in single mode     */
-#define  LPTIM_CR_CNTSTRT                       0x00000004U             /*!< Timer start in continuous mode */
-
-/******************  Bit definition for LPTIM_CMP register  *******************/
-#define  LPTIM_CMP_CMP                          0x0000FFFFU             /*!< Compare register     */
-
-/******************  Bit definition for LPTIM_ARR register  *******************/
-#define  LPTIM_ARR_ARR                          0x0000FFFFU             /*!< Auto reload register */
-
-/******************  Bit definition for LPTIM_CNT register  *******************/
-#define  LPTIM_CNT_CNT                          0x0000FFFFU             /*!< Counter register     */
-
-/******************  Bit definition for LPTIM_OR register  *******************/
-#define  LPTIM_OR_OR                           0x00000003U               /*!< LPTIMER[1:0] bits (Remap selection) */
-#define  LPTIM_OR_OR_0                         0x00000001U               /*!< Bit 0 */
-#define  LPTIM_OR_OR_1                         0x00000002U               /*!< Bit 1 */
-
-/******************************************************************************/
-/*                                                                            */
-/*         Universal Synchronous Asynchronous Receiver Transmitter            */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         0x0001U            /*!<Parity Error                 */
-#define  USART_SR_FE                         0x0002U            /*!<Framing Error                */
-#define  USART_SR_NE                         0x0004U            /*!<Noise Error Flag             */
-#define  USART_SR_ORE                        0x0008U            /*!<OverRun Error                */
-#define  USART_SR_IDLE                       0x0010U            /*!<IDLE line detected           */
-#define  USART_SR_RXNE                       0x0020U            /*!<Read Data Register Not Empty */
-#define  USART_SR_TC                         0x0040U            /*!<Transmission Complete        */
-#define  USART_SR_TXE                        0x0080U            /*!<Transmit Data Register Empty */
-#define  USART_SR_LBD                        0x0100U            /*!<LIN Break Detection Flag     */
-#define  USART_SR_CTS                        0x0200U            /*!<CTS Flag                     */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         0x01FFU            /*!<Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_Fraction              0x000FU            /*!<Fraction of USARTDIV */
-#define  USART_BRR_DIV_Mantissa              0xFFF0U            /*!<Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       0x0001U            /*!<Send Break                             */
-#define  USART_CR1_RWU                       0x0002U            /*!<Receiver wakeup                        */
-#define  USART_CR1_RE                        0x0004U            /*!<Receiver Enable                        */
-#define  USART_CR1_TE                        0x0008U            /*!<Transmitter Enable                     */
-#define  USART_CR1_IDLEIE                    0x0010U            /*!<IDLE Interrupt Enable                  */
-#define  USART_CR1_RXNEIE                    0x0020U            /*!<RXNE Interrupt Enable                  */
-#define  USART_CR1_TCIE                      0x0040U            /*!<Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     0x0080U            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PEIE                      0x0100U            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PS                        0x0200U            /*!<Parity Selection                       */
-#define  USART_CR1_PCE                       0x0400U            /*!<Parity Control Enable                  */
-#define  USART_CR1_WAKE                      0x0800U            /*!<Wakeup method                          */
-#define  USART_CR1_M                         0x1000U            /*!<Word length                            */
-#define  USART_CR1_UE                        0x2000U            /*!<USART Enable                           */
-#define  USART_CR1_OVER8                     0x8000U            /*!<USART Oversampling by 8 enable         */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       0x000FU            /*!<Address of the USART node            */
-#define  USART_CR2_LBDL                      0x0020U            /*!<LIN Break Detection Length           */
-#define  USART_CR2_LBDIE                     0x0040U            /*!<LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      0x0100U            /*!<Last Bit Clock pulse                 */
-#define  USART_CR2_CPHA                      0x0200U            /*!<Clock Phase                          */
-#define  USART_CR2_CPOL                      0x0400U            /*!<Clock Polarity                       */
-#define  USART_CR2_CLKEN                     0x0800U            /*!<Clock Enable                         */
-
-#define  USART_CR2_STOP                      0x3000U            /*!<STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    0x1000U            /*!<Bit 0 */
-#define  USART_CR2_STOP_1                    0x2000U            /*!<Bit 1 */
-
-#define  USART_CR2_LINEN                     0x4000U            /*!<LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       0x0001U            /*!<Error Interrupt Enable      */
-#define  USART_CR3_IREN                      0x0002U            /*!<IrDA mode Enable            */
-#define  USART_CR3_IRLP                      0x0004U            /*!<IrDA Low-Power              */
-#define  USART_CR3_HDSEL                     0x0008U            /*!<Half-Duplex Selection       */
-#define  USART_CR3_NACK                      0x0010U            /*!<Smartcard NACK enable       */
-#define  USART_CR3_SCEN                      0x0020U            /*!<Smartcard mode enable       */
-#define  USART_CR3_DMAR                      0x0040U            /*!<DMA Enable Receiver         */
-#define  USART_CR3_DMAT                      0x0080U            /*!<DMA Enable Transmitter      */
-#define  USART_CR3_RTSE                      0x0100U            /*!<RTS Enable                  */
-#define  USART_CR3_CTSE                      0x0200U            /*!<CTS Enable                  */
-#define  USART_CR3_CTSIE                     0x0400U            /*!<CTS Interrupt Enable        */
-#define  USART_CR3_ONEBIT                    0x0800U            /*!<USART One bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      0x00FFU            /*!<PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    0x0001U            /*!<Bit 0 */
-#define  USART_GTPR_PSC_1                    0x0002U            /*!<Bit 1 */
-#define  USART_GTPR_PSC_2                    0x0004U            /*!<Bit 2 */
-#define  USART_GTPR_PSC_3                    0x0008U            /*!<Bit 3 */
-#define  USART_GTPR_PSC_4                    0x0010U            /*!<Bit 4 */
-#define  USART_GTPR_PSC_5                    0x0020U            /*!<Bit 5 */
-#define  USART_GTPR_PSC_6                    0x0040U            /*!<Bit 6 */
-#define  USART_GTPR_PSC_7                    0x0080U            /*!<Bit 7 */
-
-#define  USART_GTPR_GT                       0xFF00U            /*!<Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Window WATCHDOG                                 */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           0x7FU               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T_0                         0x01U               /*!<Bit 0 */
-#define  WWDG_CR_T_1                         0x02U               /*!<Bit 1 */
-#define  WWDG_CR_T_2                         0x04U               /*!<Bit 2 */
-#define  WWDG_CR_T_3                         0x08U               /*!<Bit 3 */
-#define  WWDG_CR_T_4                         0x10U               /*!<Bit 4 */
-#define  WWDG_CR_T_5                         0x20U               /*!<Bit 5 */
-#define  WWDG_CR_T_6                         0x40U               /*!<Bit 6 */
-/* Legacy defines */
-#define  WWDG_CR_T0                          WWDG_CR_T_0
-#define  WWDG_CR_T1                          WWDG_CR_T_1
-#define  WWDG_CR_T2                          WWDG_CR_T_2
-#define  WWDG_CR_T3                          WWDG_CR_T_3
-#define  WWDG_CR_T4                          WWDG_CR_T_4
-#define  WWDG_CR_T5                          WWDG_CR_T_5
-#define  WWDG_CR_T6                          WWDG_CR_T_6
-
-#define  WWDG_CR_WDGA                        0x80U               /*!<Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          0x007FU            /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W_0                        0x0001U            /*!<Bit 0 */
-#define  WWDG_CFR_W_1                        0x0002U            /*!<Bit 1 */
-#define  WWDG_CFR_W_2                        0x0004U            /*!<Bit 2 */
-#define  WWDG_CFR_W_3                        0x0008U            /*!<Bit 3 */
-#define  WWDG_CFR_W_4                        0x0010U            /*!<Bit 4 */
-#define  WWDG_CFR_W_5                        0x0020U            /*!<Bit 5 */
-#define  WWDG_CFR_W_6                        0x0040U            /*!<Bit 6 */
-/* Legacy defines */
-#define  WWDG_CFR_W0                         WWDG_CFR_W_0
-#define  WWDG_CFR_W1                         WWDG_CFR_W_1
-#define  WWDG_CFR_W2                         WWDG_CFR_W_2
-#define  WWDG_CFR_W3                         WWDG_CFR_W_3
-#define  WWDG_CFR_W4                         WWDG_CFR_W_4
-#define  WWDG_CFR_W5                         WWDG_CFR_W_5
-#define  WWDG_CFR_W6                         WWDG_CFR_W_6
-
-#define  WWDG_CFR_WDGTB                      0x0180U            /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB_0                    0x0080U            /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB_1                    0x0100U            /*!<Bit 1 */
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
-
-#define  WWDG_CFR_EWI                        0x0200U            /*!<Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        0x01U               /*!<Early Wakeup Interrupt Flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Digital to Analog Converter                           */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DAC_CR register  ********************/
-#define  DAC_CR_EN1                          0x00000001U        /*!<DAC channel1 enable */
-#define  DAC_CR_BOFF1                        0x00000002U        /*!<DAC channel1 output buffer disable */
-#define  DAC_CR_TEN1                         0x00000004U        /*!<DAC channel1 Trigger enable */
-
-#define  DAC_CR_TSEL1                        0x00000038U        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define  DAC_CR_TSEL1_0                      0x00000008U        /*!<Bit 0 */
-#define  DAC_CR_TSEL1_1                      0x00000010U        /*!<Bit 1 */
-#define  DAC_CR_TSEL1_2                      0x00000020U        /*!<Bit 2 */
-
-#define  DAC_CR_WAVE1                        0x000000C0U        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE1_0                      0x00000040U        /*!<Bit 0 */
-#define  DAC_CR_WAVE1_1                      0x00000080U        /*!<Bit 1 */
-
-#define  DAC_CR_MAMP1                        0x00000F00U        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP1_0                      0x00000100U        /*!<Bit 0 */
-#define  DAC_CR_MAMP1_1                      0x00000200U        /*!<Bit 1 */
-#define  DAC_CR_MAMP1_2                      0x00000400U        /*!<Bit 2 */
-#define  DAC_CR_MAMP1_3                      0x00000800U        /*!<Bit 3 */
-
-#define  DAC_CR_DMAEN1                       0x00001000U        /*!<DAC channel1 DMA enable */
-#define  DAC_CR_DMAUDRIE1                    0x00002000U        /*!<DAC channel1 DMA underrun interrupt enable*/
-#define  DAC_CR_EN2                          0x00010000U        /*!<DAC channel2 enable */
-#define  DAC_CR_BOFF2                        0x00020000U        /*!<DAC channel2 output buffer disable */
-#define  DAC_CR_TEN2                         0x00040000U        /*!<DAC channel2 Trigger enable */
-
-#define  DAC_CR_TSEL2                        0x00380000U        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define  DAC_CR_TSEL2_0                      0x00080000U        /*!<Bit 0 */
-#define  DAC_CR_TSEL2_1                      0x00100000U        /*!<Bit 1 */
-#define  DAC_CR_TSEL2_2                      0x00200000U        /*!<Bit 2 */
-
-#define  DAC_CR_WAVE2                        0x00C00000U        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE2_0                      0x00400000U        /*!<Bit 0 */
-#define  DAC_CR_WAVE2_1                      0x00800000U        /*!<Bit 1 */
-
-#define  DAC_CR_MAMP2                        0x0F000000U        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP2_0                      0x01000000U        /*!<Bit 0 */
-#define  DAC_CR_MAMP2_1                      0x02000000U        /*!<Bit 1 */
-#define  DAC_CR_MAMP2_2                      0x04000000U        /*!<Bit 2 */
-#define  DAC_CR_MAMP2_3                      0x08000000U        /*!<Bit 3 */
-
-#define  DAC_CR_DMAEN2                       0x10000000U        /*!<DAC channel2 DMA enabled */
-#define  DAC_CR_DMAUDRIE2                    0x20000000U        /*!<DAC channel2 DMA underrun interrupt enable*/
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define  DAC_SWTRIGR_SWTRIG1                 0x01U               /*!<DAC channel1 software trigger */
-#define  DAC_SWTRIGR_SWTRIG2                 0x02U               /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define  DAC_DHR12R1_DACC1DHR                0x0FFFU            /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define  DAC_DHR12L1_DACC1DHR                0xFFF0U            /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define  DAC_DHR8R1_DACC1DHR                 0xFFU               /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define  DAC_DHR12R2_DACC2DHR                0x0FFFU            /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define  DAC_DHR12L2_DACC2DHR                0xFFF0U            /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define  DAC_DHR8R2_DACC2DHR                 0xFFU               /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define  DAC_DHR12RD_DACC1DHR                0x00000FFFU        /*!<DAC channel1 12-bit Right aligned data */
-#define  DAC_DHR12RD_DACC2DHR                0x0FFF0000U        /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define  DAC_DHR12LD_DACC1DHR                0x0000FFF0U        /*!<DAC channel1 12-bit Left aligned data */
-#define  DAC_DHR12LD_DACC2DHR                0xFFF00000U        /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define  DAC_DHR8RD_DACC1DHR                 0x00FFU            /*!<DAC channel1 8-bit Right aligned data */
-#define  DAC_DHR8RD_DACC2DHR                 0xFF00U            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define  DAC_DOR1_DACC1DOR                   0x0FFFU            /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define  DAC_DOR2_DACC2DOR                   0x0FFFU            /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define  DAC_SR_DMAUDR1                      0x00002000U        /*!<DAC channel1 DMA underrun flag */
-#define  DAC_SR_DMAUDR2                      0x20000000U        /*!<DAC channel2 DMA underrun flag */
-/******************************************************************************/
-/*                                                                            */
-/*                                DBG                                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
-#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
-
-/********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
-#define  DBGMCU_CR_DBG_STOP                  0x00000002U
-#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
-#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
-
-#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
-#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U/*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U/*!<Bit 1 */
-
-/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
-
-/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        0x00000001U
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        0x00010000U
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       0x00040000U
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
- 
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
- 
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DAC Instances ********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/******************************** DMA Instances *******************************/
-#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
-                                              ((INSTANCE) == DMA1_Stream1) || \
-                                              ((INSTANCE) == DMA1_Stream2) || \
-                                              ((INSTANCE) == DMA1_Stream3) || \
-                                              ((INSTANCE) == DMA1_Stream4) || \
-                                              ((INSTANCE) == DMA1_Stream5) || \
-                                              ((INSTANCE) == DMA1_Stream6) || \
-                                              ((INSTANCE) == DMA1_Stream7) || \
-                                              ((INSTANCE) == DMA2_Stream0) || \
-                                              ((INSTANCE) == DMA2_Stream1) || \
-                                              ((INSTANCE) == DMA2_Stream2) || \
-                                              ((INSTANCE) == DMA2_Stream3) || \
-                                              ((INSTANCE) == DMA2_Stream4) || \
-                                              ((INSTANCE) == DMA2_Stream5) || \
-                                              ((INSTANCE) == DMA2_Stream6) || \
-                                              ((INSTANCE) == DMA2_Stream7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOH))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2)) 
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI5))
-
-/******************************* LPTIM Instances ******************************/
-#define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
-
-/******************************* RNG Instances ********************************/
-#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI5))
-/*************************** SPI Extended Instances ***************************/
-#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1)    || \
-                                           ((INSTANCE) == SPI2)    || \
-                                           ((INSTANCE) == SPI5))
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
-                                   ((INSTANCE) == TIM5)   || \
-                                   ((INSTANCE) == TIM6)   || \
-                                   ((INSTANCE) == TIM9)   || \
-                                   ((INSTANCE) == TIM11))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM9)  || \
-                                         ((INSTANCE) == TIM11))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM9))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM5))
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM5))
-
-/******************** TIM Instances : Advanced-control timers *****************/
-#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM5))
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM6))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM5))
-
-/************ TIM Instances : DMA requests generation (COMDE) *****************/
-#define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM5)) 
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                             ((INSTANCE) == TIM5))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM6) || \
-                                          ((INSTANCE) == TIM9))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM9))
-
-/********************** TIM Instances : 32 bit Counter ************************/
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM5))
-
-/***************** TIM Instances : external trigger input availabe ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                        ((INSTANCE) == TIM5))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM11))
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM1) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM5) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-/************ TIM Instances : complementary output(s) available ***************/
-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
-   ((((INSTANCE) == TIM1) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3))))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART6))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART6))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART6))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART6))     
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/***************************** FMPI2C Instances *******************************/
-#define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32F410Cx_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/cmsis/stm32f410rx.h b/stmhal/cmsis/stm32f410rx.h
deleted file mode 100644
index 92647c9c14..0000000000
--- a/stmhal/cmsis/stm32f410rx.h
+++ /dev/null
@@ -1,4001 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f410rx.h
-  * @author  MCD Application Team
-  * @version V2.5.1
-  * @date    28-June-2016
-  * @brief   CMSIS STM32F410Rx Device Peripheral Access Layer Header File. 
-  *
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - peripherals registers declarations and bits definition
-  *           - Macros to access peripheral’s registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f410rx
-  * @{
-  */
-    
-#ifndef __STM32F410Rx_H
-#define __STM32F410Rx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-  
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-
-/**
-  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
-  */
-#define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */
-#define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */
-#define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1U       /*!< FPU present                                   */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32F4XX Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-typedef enum
-{
-/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
-  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
-/******  STM32 specific Interrupt Numbers **********************************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
-  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
-  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
-  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
-  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
-  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
-  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
-  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
-  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
-  ADC_IRQn                    = 18,     /*!< ADC1 global Interrupts                                            */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
-  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
-  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                             */
-  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
-  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
-  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global Interrupt and DAC Global Interrupt                    */
-  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
-  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
-  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
-  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
-  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
-  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
-  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
-  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
-  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
-  RNG_IRQn                    = 80,     /*!< RNG global Interrupt                                              */
-  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
-  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                            */
-  FMPI2C1_EV_IRQn             = 95,     /*!< FMPI2C1 Event Interrupt                                           */
-  FMPI2C1_ER_IRQn             = 96,     /*!< FMPI2C1 Error Interrupt                                          */
-  LPTIM1_IRQn                 = 97      /*!< LPTIM1 interrupt                                                  */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
-#include "system_stm32f4xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */
-  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
-  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
-  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
-  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
-  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
-  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
-  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
-  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
-  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
-  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
-  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
-  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
-  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
-  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
-  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
-                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief CRC calculation unit 
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
-  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */
-  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
-  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
-  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
-  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
-  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
-  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
-  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
-  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
-  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
-  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
-  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
-  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
-  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
-  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
-  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
-  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
-  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
-  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
-  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
-  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
-  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
-  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
-  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
-} DMA_Stream_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
-  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
-  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
-  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
-} DMA_TypeDef;
-
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
-  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
-  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
-  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
-  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
-  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-
-typedef struct
-{
-  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */
-  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */
-  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */
-  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */
-  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */
-  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief General Purpose I/O
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
-  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
-  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
-  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
-  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
-  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
-  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
-  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/** 
-  * @brief System configuration controller
-  */
-  
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-  uint32_t      RESERVED;     /*!< Reserved, 0x18                                                               */
-  uint32_t      CFGR2;        /*!< Reserved, 0x1C                                                               */
-  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
-  uint32_t      RESERVED1[2]; /*!< Reserved, 0x24-0x28                                                          */
-  __IO uint32_t CFGR;         /*!< SYSCFG Configuration register,                     Address offset: 0x2C      */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */
-  __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */
-  __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */
-  __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */
-  __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */
-  __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
-  __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
-  __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
-  __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */
-} I2C_TypeDef;
-
-/**
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< FMPI2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< FMPI2C Control register 2,            Address offset: 0x04 */
-  __IO uint32_t OAR1;        /*!< FMPI2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;        /*!< FMPI2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;     /*!< FMPI2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR;    /*!< FMPI2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;         /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;         /*!< FMPI2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;        /*!< FMPI2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;        /*!< FMPI2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;        /*!< FMPI2C Transmit data register,        Address offset: 0x28 */
-} FMPI2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
-  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
-  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
-  uint32_t      RESERVED0[3];  /*!< Reserved, 0x14-0x1C                                                               */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
-  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
-  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
-  uint32_t      RESERVED2[3];  /*!< Reserved, 0x34-0x3C                                                               */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
-  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
-  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
-  uint32_t      RESERVED4[3];  /*!< Reserved, 0x54-0x5C                                                               */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
-  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
-  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
-  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
-  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
-  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
-  uint32_t      RESERVED7[2];  /*!< Reserved, 0x84-0x88                                                               */
-  __IO uint32_t DCKCFGR;       /*!< RCC Dedicated Clocks configuration register,                 Address offset: 0x8C */
-  __IO uint32_t CKGATENR;       /*!< RCC Clocks Gated ENable Register,                           Address offset: 0x90 */
-  __IO uint32_t DCKCFGR2;      /*!< RCC Dedicated Clocks configuration register 2,               Address offset: 0x94 */
-
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-
-typedef struct
-{
-  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
-  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
-  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
-  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
-  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
-  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
-  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */
-  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
-  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */
-  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
-  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */
-  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */
-  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */
-  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */
-  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
-  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */
-  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
-  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
-  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
-  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
-  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
-  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
-  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
-  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
-  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
-  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
-  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
-  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
-  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
-  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
-  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
-  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
-  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
-  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
-  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
-  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
-  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
-} RTC_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
-  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
-  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
-  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-
-/** 
-  * @brief RNG
-  */
-  
-typedef struct 
-{
-  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
-  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
-  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
-} RNG_TypeDef;
-
-
-/**
-  * @brief LPTIMER
-  */
-typedef struct
-{
-  __IO uint32_t ISR;         /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */
-  __IO uint32_t ICR;         /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */
-  __IO uint32_t IER;         /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */
-  __IO uint32_t CFGR;        /*!< LPTIM Configuration register,                       Address offset: 0x0C */
-  __IO uint32_t CR;          /*!< LPTIM Control register,                             Address offset: 0x10 */
-  __IO uint32_t CMP;         /*!< LPTIM Compare register,                             Address offset: 0x14 */
-  __IO uint32_t ARR;         /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
-  __IO uint32_t CNT;         /*!< LPTIM Counter register,                             Address offset: 0x1C */
-  __IO uint32_t OR;          /*!< LPTIM Option register,                              Address offset: 0x20 */
-} LPTIM_TypeDef;
-
-/** 
-  * @brief Peripheral_memory_map
-  */
-#define FLASH_BASE            0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region                         */
-#define SRAM1_BASE            0x20000000U /*!< SRAM1(32 KB) base address in the alias region                              */
-#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region                                */
-#define SRAM1_BB_BASE         0x22000000U /*!< SRAM1(32 KB) base address in the bit-band region                           */
-#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region                             */
-#define FLASH_END             0x0801FFFFU /*!< FLASH end address */
-
-/* Legacy defines */
-#define SRAM_BASE             SRAM1_BASE
-#define SRAM_BB_BASE          SRAM1_BB_BASE
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
-
-/*!< APB1 peripherals */
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)
-#define LPTIM1_BASE           (APB1PERIPH_BASE + 0x2400U)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)
-#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400U)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)
-#define FMPI2C1_BASE          (APB1PERIPH_BASE + 0x6000U)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)
-/*!< APB2 peripherals */
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000U)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x1000U)
-#define USART6_BASE           (APB2PERIPH_BASE + 0x1400U)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000U)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x2300U)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800U)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00U)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000U)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800U)
-#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000U)
-
-/*!< AHB1 peripherals */
-#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000U)
-#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400U)
-#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800U)
-#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00U)
-#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)
-#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800U)
-#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00U)
-#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000U)
-#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010U)
-#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028U)
-#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040U)
-#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058U)
-#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070U)
-#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088U)
-#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0U)
-#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8U)
-#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400U)
-#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010U)
-#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028U)
-#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040U)
-#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058U)
-#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070U)
-#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088U)
-#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0U)
-#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)
-#define RNG_BASE              (PERIPH_BASE + 0x80000U)
-
-/* Debug MCU registers base address */
-#define DBGMCU_BASE           0xE0042000U
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define FMPI2C1             ((FMPI2C_TypeDef *) FMPI2C1_BASE)
-#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define USART6              ((USART_TypeDef *) USART6_BASE)
-#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-#define SPI5                ((SPI_TypeDef *) SPI5_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
-#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
-#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
-#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
-#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
-#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
-#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
-#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
-#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
-#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
-#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
-#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
-#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
-#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
-#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
-#define RNG                 ((RNG_TypeDef *) RNG_BASE)
-
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers_Bits_Definition               */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Analog to Digital Converter                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          0x00000001U       /*!<Analog watchdog flag */
-#define  ADC_SR_EOC                          0x00000002U       /*!<End of conversion */
-#define  ADC_SR_JEOC                         0x00000004U       /*!<Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        0x00000008U       /*!<Injected channel Start flag */
-#define  ADC_SR_STRT                         0x00000010U       /*!<Regular channel Start flag */
-#define  ADC_SR_OVR                          0x00000020U       /*!<Overrun flag */
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
-#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels */
-#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels */
-#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution) */
-#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
-  
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion */
-#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode */
-#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC) */
-#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection */
-#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment */
-#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      0xFFFFU            /*!<Injected data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag */
-#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion */
-#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag */
-#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag */
-#define  ADC_CSR_OVR1                        0x00000020U        /*!<ADC1 DMA overrun  flag */
-#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag */
-#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion */
-#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag */
-#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag */
-#define  ADC_CSR_OVR2                        0x00002000U        /*!<ADC2 DMA overrun  flag */
-#define  ADC_CSR_AWD3                        0x00010000U        /*!<ADC3 Analog watchdog flag */
-#define  ADC_CSR_EOC3                        0x00020000U        /*!<ADC3 End of conversion */
-#define  ADC_CSR_JEOC3                       0x00040000U        /*!<ADC3 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT3                      0x00080000U        /*!<ADC3 Injected channel Start flag */
-#define  ADC_CSR_STRT3                       0x00100000U        /*!<ADC3 Regular channel Start flag */
-#define  ADC_CSR_OVR3                        0x00200000U        /*!<ADC3 DMA overrun  flag */
-
-/* Legacy defines */
-#define  ADC_CSR_DOVR1                        ADC_CSR_OVR1
-#define  ADC_CSR_DOVR2                        ADC_CSR_OVR2
-#define  ADC_CSR_DOVR3                        ADC_CSR_OVR3
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
-#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
-#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
-#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
-#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
-
-/*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                      0x0000FFFFU         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                      0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRC calculation unit                              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           0xFFFFFFFFU /*!< Data register bits */
-
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         0xFFU        /*!< General-purpose 8-bit data register bits */
-
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        0x01U        /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 Debug MCU                                  */
-/*                                                                            */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                             DMA Controller                                 */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DMA_SxCR register  *****************/
-#define DMA_SxCR_CHSEL                       0x0E000000U
-#define DMA_SxCR_CHSEL_0                     0x02000000U
-#define DMA_SxCR_CHSEL_1                     0x04000000U
-#define DMA_SxCR_CHSEL_2                     0x08000000U
-#define DMA_SxCR_MBURST                      0x01800000U
-#define DMA_SxCR_MBURST_0                    0x00800000U
-#define DMA_SxCR_MBURST_1                    0x01000000U
-#define DMA_SxCR_PBURST                      0x00600000U
-#define DMA_SxCR_PBURST_0                    0x00200000U
-#define DMA_SxCR_PBURST_1                    0x00400000U
-#define DMA_SxCR_CT                          0x00080000U
-#define DMA_SxCR_DBM                         0x00040000U
-#define DMA_SxCR_PL                          0x00030000U
-#define DMA_SxCR_PL_0                        0x00010000U
-#define DMA_SxCR_PL_1                        0x00020000U
-#define DMA_SxCR_PINCOS                      0x00008000U
-#define DMA_SxCR_MSIZE                       0x00006000U
-#define DMA_SxCR_MSIZE_0                     0x00002000U
-#define DMA_SxCR_MSIZE_1                     0x00004000U
-#define DMA_SxCR_PSIZE                       0x00001800U
-#define DMA_SxCR_PSIZE_0                     0x00000800U
-#define DMA_SxCR_PSIZE_1                     0x00001000U
-#define DMA_SxCR_MINC                        0x00000400U
-#define DMA_SxCR_PINC                        0x00000200U
-#define DMA_SxCR_CIRC                        0x00000100U
-#define DMA_SxCR_DIR                         0x000000C0U
-#define DMA_SxCR_DIR_0                       0x00000040U
-#define DMA_SxCR_DIR_1                       0x00000080U
-#define DMA_SxCR_PFCTRL                      0x00000020U
-#define DMA_SxCR_TCIE                        0x00000010U
-#define DMA_SxCR_HTIE                        0x00000008U
-#define DMA_SxCR_TEIE                        0x00000004U
-#define DMA_SxCR_DMEIE                       0x00000002U
-#define DMA_SxCR_EN                          0x00000001U
-
-/* Legacy defines */
-#define DMA_SxCR_ACK                         0x00100000U
-
-/********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            0x0000FFFFU
-#define DMA_SxNDT_0                          0x00000001U
-#define DMA_SxNDT_1                          0x00000002U
-#define DMA_SxNDT_2                          0x00000004U
-#define DMA_SxNDT_3                          0x00000008U
-#define DMA_SxNDT_4                          0x00000010U
-#define DMA_SxNDT_5                          0x00000020U
-#define DMA_SxNDT_6                          0x00000040U
-#define DMA_SxNDT_7                          0x00000080U
-#define DMA_SxNDT_8                          0x00000100U
-#define DMA_SxNDT_9                          0x00000200U
-#define DMA_SxNDT_10                         0x00000400U
-#define DMA_SxNDT_11                         0x00000800U
-#define DMA_SxNDT_12                         0x00001000U
-#define DMA_SxNDT_13                         0x00002000U
-#define DMA_SxNDT_14                         0x00004000U
-#define DMA_SxNDT_15                         0x00008000U
-
-/********************  Bits definition for DMA_SxFCR register  ****************/ 
-#define DMA_SxFCR_FEIE                       0x00000080U
-#define DMA_SxFCR_FS                         0x00000038U
-#define DMA_SxFCR_FS_0                       0x00000008U
-#define DMA_SxFCR_FS_1                       0x00000010U
-#define DMA_SxFCR_FS_2                       0x00000020U
-#define DMA_SxFCR_DMDIS                      0x00000004U
-#define DMA_SxFCR_FTH                        0x00000003U
-#define DMA_SxFCR_FTH_0                      0x00000001U
-#define DMA_SxFCR_FTH_1                      0x00000002U
-
-/********************  Bits definition for DMA_LISR register  *****************/ 
-#define DMA_LISR_TCIF3                       0x08000000U
-#define DMA_LISR_HTIF3                       0x04000000U
-#define DMA_LISR_TEIF3                       0x02000000U
-#define DMA_LISR_DMEIF3                      0x01000000U
-#define DMA_LISR_FEIF3                       0x00400000U
-#define DMA_LISR_TCIF2                       0x00200000U
-#define DMA_LISR_HTIF2                       0x00100000U
-#define DMA_LISR_TEIF2                       0x00080000U
-#define DMA_LISR_DMEIF2                      0x00040000U
-#define DMA_LISR_FEIF2                       0x00010000U
-#define DMA_LISR_TCIF1                       0x00000800U
-#define DMA_LISR_HTIF1                       0x00000400U
-#define DMA_LISR_TEIF1                       0x00000200U
-#define DMA_LISR_DMEIF1                      0x00000100U
-#define DMA_LISR_FEIF1                       0x00000040U
-#define DMA_LISR_TCIF0                       0x00000020U
-#define DMA_LISR_HTIF0                       0x00000010U
-#define DMA_LISR_TEIF0                       0x00000008U
-#define DMA_LISR_DMEIF0                      0x00000004U
-#define DMA_LISR_FEIF0                       0x00000001U
-
-/********************  Bits definition for DMA_HISR register  *****************/ 
-#define DMA_HISR_TCIF7                       0x08000000U
-#define DMA_HISR_HTIF7                       0x04000000U
-#define DMA_HISR_TEIF7                       0x02000000U
-#define DMA_HISR_DMEIF7                      0x01000000U
-#define DMA_HISR_FEIF7                       0x00400000U
-#define DMA_HISR_TCIF6                       0x00200000U
-#define DMA_HISR_HTIF6                       0x00100000U
-#define DMA_HISR_TEIF6                       0x00080000U
-#define DMA_HISR_DMEIF6                      0x00040000U
-#define DMA_HISR_FEIF6                       0x00010000U
-#define DMA_HISR_TCIF5                       0x00000800U
-#define DMA_HISR_HTIF5                       0x00000400U
-#define DMA_HISR_TEIF5                       0x00000200U
-#define DMA_HISR_DMEIF5                      0x00000100U
-#define DMA_HISR_FEIF5                       0x00000040U
-#define DMA_HISR_TCIF4                       0x00000020U
-#define DMA_HISR_HTIF4                       0x00000010U
-#define DMA_HISR_TEIF4                       0x00000008U
-#define DMA_HISR_DMEIF4                      0x00000004U
-#define DMA_HISR_FEIF4                       0x00000001U
-
-/********************  Bits definition for DMA_LIFCR register  ****************/ 
-#define DMA_LIFCR_CTCIF3                     0x08000000U
-#define DMA_LIFCR_CHTIF3                     0x04000000U
-#define DMA_LIFCR_CTEIF3                     0x02000000U
-#define DMA_LIFCR_CDMEIF3                    0x01000000U
-#define DMA_LIFCR_CFEIF3                     0x00400000U
-#define DMA_LIFCR_CTCIF2                     0x00200000U
-#define DMA_LIFCR_CHTIF2                     0x00100000U
-#define DMA_LIFCR_CTEIF2                     0x00080000U
-#define DMA_LIFCR_CDMEIF2                    0x00040000U
-#define DMA_LIFCR_CFEIF2                     0x00010000U
-#define DMA_LIFCR_CTCIF1                     0x00000800U
-#define DMA_LIFCR_CHTIF1                     0x00000400U
-#define DMA_LIFCR_CTEIF1                     0x00000200U
-#define DMA_LIFCR_CDMEIF1                    0x00000100U
-#define DMA_LIFCR_CFEIF1                     0x00000040U
-#define DMA_LIFCR_CTCIF0                     0x00000020U
-#define DMA_LIFCR_CHTIF0                     0x00000010U
-#define DMA_LIFCR_CTEIF0                     0x00000008U
-#define DMA_LIFCR_CDMEIF0                    0x00000004U
-#define DMA_LIFCR_CFEIF0                     0x00000001U
-
-/********************  Bits definition for DMA_HIFCR  register  ****************/ 
-#define DMA_HIFCR_CTCIF7                     0x08000000U
-#define DMA_HIFCR_CHTIF7                     0x04000000U
-#define DMA_HIFCR_CTEIF7                     0x02000000U
-#define DMA_HIFCR_CDMEIF7                    0x01000000U
-#define DMA_HIFCR_CFEIF7                     0x00400000U
-#define DMA_HIFCR_CTCIF6                     0x00200000U
-#define DMA_HIFCR_CHTIF6                     0x00100000U
-#define DMA_HIFCR_CTEIF6                     0x00080000U
-#define DMA_HIFCR_CDMEIF6                    0x00040000U
-#define DMA_HIFCR_CFEIF6                     0x00010000U
-#define DMA_HIFCR_CTCIF5                     0x00000800U
-#define DMA_HIFCR_CHTIF5                     0x00000400U
-#define DMA_HIFCR_CTEIF5                     0x00000200U
-#define DMA_HIFCR_CDMEIF5                    0x00000100U
-#define DMA_HIFCR_CFEIF5                     0x00000040U
-#define DMA_HIFCR_CTCIF4                     0x00000020U
-#define DMA_HIFCR_CHTIF4                     0x00000010U
-#define DMA_HIFCR_CTEIF4                     0x00000008U
-#define DMA_HIFCR_CDMEIF4                    0x00000004U
-#define DMA_HIFCR_CFEIF4                     0x00000001U
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                    External Interrupt/Event Controller                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
-#define  EXTI_IMR_MR23                       0x00800000U        /*!< Interrupt Mask on line 23 */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
-#define  EXTI_EMR_MR23                       0x00800000U        /*!< Event Mask on line 23 */
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
-#define  EXTI_RTSR_TR23                      0x00800000U        /*!< Rising trigger event configuration bit of line 23 */
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
-#define  EXTI_FTSR_TR23                      0x00800000U        /*!< Falling trigger event configuration bit of line 23 */
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
-#define  EXTI_SWIER_SWIER23                  0x00800000U        /*!< Software Interrupt on line 23 */
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
-#define  EXTI_PR_PR23                        0x00800000U        /*!< Pending bit for line 23 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    FLASH                                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    0x0000000FU
-#define FLASH_ACR_LATENCY_0WS                0x00000000U
-#define FLASH_ACR_LATENCY_1WS                0x00000001U
-#define FLASH_ACR_LATENCY_2WS                0x00000002U
-#define FLASH_ACR_LATENCY_3WS                0x00000003U
-#define FLASH_ACR_LATENCY_4WS                0x00000004U
-#define FLASH_ACR_LATENCY_5WS                0x00000005U
-#define FLASH_ACR_LATENCY_6WS                0x00000006U
-#define FLASH_ACR_LATENCY_7WS                0x00000007U
-
-#define FLASH_ACR_PRFTEN                     0x00000100U
-#define FLASH_ACR_ICEN                       0x00000200U
-#define FLASH_ACR_DCEN                       0x00000400U
-#define FLASH_ACR_ICRST                      0x00000800U
-#define FLASH_ACR_DCRST                      0x00001000U
-#define FLASH_ACR_BYTE0_ADDRESS              0x40023C00U
-#define FLASH_ACR_BYTE2_ADDRESS              0x40023C03U
-
-/*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         0x00000001U
-#define FLASH_SR_SOP                         0x00000002U
-#define FLASH_SR_WRPERR                      0x00000010U
-#define FLASH_SR_PGAERR                      0x00000020U
-#define FLASH_SR_PGPERR                      0x00000040U
-#define FLASH_SR_PGSERR                      0x00000080U
-#define FLASH_SR_BSY                         0x00010000U
-
-/*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          0x00000001U
-#define FLASH_CR_SER                         0x00000002U
-#define FLASH_CR_MER                         0x00000004U
-#define FLASH_CR_SNB                         0x000000F8U
-#define FLASH_CR_SNB_0                       0x00000008U
-#define FLASH_CR_SNB_1                       0x00000010U
-#define FLASH_CR_SNB_2                       0x00000020U
-#define FLASH_CR_SNB_3                       0x00000040U
-#define FLASH_CR_SNB_4                       0x00000080U
-#define FLASH_CR_PSIZE                       0x00000300U
-#define FLASH_CR_PSIZE_0                     0x00000100U
-#define FLASH_CR_PSIZE_1                     0x00000200U
-#define FLASH_CR_STRT                        0x00010000U
-#define FLASH_CR_EOPIE                       0x01000000U
-#define FLASH_CR_LOCK                        0x80000000U
-
-/*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                 0x00000001U
-#define FLASH_OPTCR_OPTSTRT                 0x00000002U
-#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
-#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
-#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
-
-#define FLASH_OPTCR_WDG_SW                  0x00000020U
-#define FLASH_OPTCR_nRST_STOP               0x00000040U
-#define FLASH_OPTCR_nRST_STDBY              0x00000080U
-#define FLASH_OPTCR_RDP                     0x0000FF00U
-#define FLASH_OPTCR_RDP_0                   0x00000100U
-#define FLASH_OPTCR_RDP_1                   0x00000200U
-#define FLASH_OPTCR_RDP_2                   0x00000400U
-#define FLASH_OPTCR_RDP_3                   0x00000800U
-#define FLASH_OPTCR_RDP_4                   0x00001000U
-#define FLASH_OPTCR_RDP_5                   0x00002000U
-#define FLASH_OPTCR_RDP_6                   0x00004000U
-#define FLASH_OPTCR_RDP_7                   0x00008000U
-#define FLASH_OPTCR_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR_nWRP_0                  0x00010000U
-#define FLASH_OPTCR_nWRP_1                  0x00020000U
-#define FLASH_OPTCR_nWRP_2                  0x00040000U
-#define FLASH_OPTCR_nWRP_3                  0x00080000U
-#define FLASH_OPTCR_nWRP_4                  0x00100000U
-#define FLASH_OPTCR_nWRP_5                  0x00200000U
-#define FLASH_OPTCR_nWRP_6                  0x00400000U
-#define FLASH_OPTCR_nWRP_7                  0x00800000U
-#define FLASH_OPTCR_nWRP_8                  0x01000000U
-#define FLASH_OPTCR_nWRP_9                  0x02000000U
-#define FLASH_OPTCR_nWRP_10                 0x04000000U
-#define FLASH_OPTCR_nWRP_11                 0x08000000U
-                                             
-/******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR1_nWRP_0                  0x00010000U
-#define FLASH_OPTCR1_nWRP_1                  0x00020000U
-#define FLASH_OPTCR1_nWRP_2                  0x00040000U
-#define FLASH_OPTCR1_nWRP_3                  0x00080000U
-#define FLASH_OPTCR1_nWRP_4                  0x00100000U
-#define FLASH_OPTCR1_nWRP_5                  0x00200000U
-#define FLASH_OPTCR1_nWRP_6                  0x00400000U
-#define FLASH_OPTCR1_nWRP_7                  0x00800000U
-#define FLASH_OPTCR1_nWRP_8                  0x01000000U
-#define FLASH_OPTCR1_nWRP_9                  0x02000000U
-#define FLASH_OPTCR1_nWRP_10                 0x04000000U
-#define FLASH_OPTCR1_nWRP_11                 0x08000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    0x00000003U
-#define GPIO_MODER_MODER0_0                  0x00000001U
-#define GPIO_MODER_MODER0_1                  0x00000002U
-
-#define GPIO_MODER_MODER1                    0x0000000CU
-#define GPIO_MODER_MODER1_0                  0x00000004U
-#define GPIO_MODER_MODER1_1                  0x00000008U
-
-#define GPIO_MODER_MODER2                    0x00000030U
-#define GPIO_MODER_MODER2_0                  0x00000010U
-#define GPIO_MODER_MODER2_1                  0x00000020U
-
-#define GPIO_MODER_MODER3                    0x000000C0U
-#define GPIO_MODER_MODER3_0                  0x00000040U
-#define GPIO_MODER_MODER3_1                  0x00000080U
-
-#define GPIO_MODER_MODER4                    0x00000300U
-#define GPIO_MODER_MODER4_0                  0x00000100U
-#define GPIO_MODER_MODER4_1                  0x00000200U
-
-#define GPIO_MODER_MODER5                    0x00000C00U
-#define GPIO_MODER_MODER5_0                  0x00000400U
-#define GPIO_MODER_MODER5_1                  0x00000800U
-
-#define GPIO_MODER_MODER6                    0x00003000U
-#define GPIO_MODER_MODER6_0                  0x00001000U
-#define GPIO_MODER_MODER6_1                  0x00002000U
-
-#define GPIO_MODER_MODER7                    0x0000C000U
-#define GPIO_MODER_MODER7_0                  0x00004000U
-#define GPIO_MODER_MODER7_1                  0x00008000U
-
-#define GPIO_MODER_MODER8                    0x00030000U
-#define GPIO_MODER_MODER8_0                  0x00010000U
-#define GPIO_MODER_MODER8_1                  0x00020000U
-
-#define GPIO_MODER_MODER9                    0x000C0000U
-#define GPIO_MODER_MODER9_0                  0x00040000U
-#define GPIO_MODER_MODER9_1                  0x00080000U
-
-#define GPIO_MODER_MODER10                   0x00300000U
-#define GPIO_MODER_MODER10_0                 0x00100000U
-#define GPIO_MODER_MODER10_1                 0x00200000U
-
-#define GPIO_MODER_MODER11                   0x00C00000U
-#define GPIO_MODER_MODER11_0                 0x00400000U
-#define GPIO_MODER_MODER11_1                 0x00800000U
-
-#define GPIO_MODER_MODER12                   0x03000000U
-#define GPIO_MODER_MODER12_0                 0x01000000U
-#define GPIO_MODER_MODER12_1                 0x02000000U
-
-#define GPIO_MODER_MODER13                   0x0C000000U
-#define GPIO_MODER_MODER13_0                 0x04000000U
-#define GPIO_MODER_MODER13_1                 0x08000000U
-
-#define GPIO_MODER_MODER14                   0x30000000U
-#define GPIO_MODER_MODER14_0                 0x10000000U
-#define GPIO_MODER_MODER14_1                 0x20000000U
-
-#define GPIO_MODER_MODER15                   0xC0000000U
-#define GPIO_MODER_MODER15_0                 0x40000000U
-#define GPIO_MODER_MODER15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     0x00000001U
-#define GPIO_OTYPER_OT_1                     0x00000002U
-#define GPIO_OTYPER_OT_2                     0x00000004U
-#define GPIO_OTYPER_OT_3                     0x00000008U
-#define GPIO_OTYPER_OT_4                     0x00000010U
-#define GPIO_OTYPER_OT_5                     0x00000020U
-#define GPIO_OTYPER_OT_6                     0x00000040U
-#define GPIO_OTYPER_OT_7                     0x00000080U
-#define GPIO_OTYPER_OT_8                     0x00000100U
-#define GPIO_OTYPER_OT_9                     0x00000200U
-#define GPIO_OTYPER_OT_10                    0x00000400U
-#define GPIO_OTYPER_OT_11                    0x00000800U
-#define GPIO_OTYPER_OT_12                    0x00001000U
-#define GPIO_OTYPER_OT_13                    0x00002000U
-#define GPIO_OTYPER_OT_14                    0x00004000U
-#define GPIO_OTYPER_OT_15                    0x00008000U
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
-#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
-#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
-
-#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
-#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
-#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
-
-#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
-#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
-#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
-
-#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
-#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
-#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
-
-#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
-#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
-#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
-
-#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
-#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
-#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
-
-#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
-#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
-#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
-
-#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
-#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
-#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
-
-#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
-#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
-#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
-
-#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
-#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
-#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
-
-#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
-#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
-#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
-
-#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
-#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
-#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
-
-#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
-#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
-#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
-
-#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
-#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
-#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
-
-#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
-#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
-#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
-
-#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
-#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
-#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    0x00000003U
-#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
-#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
-
-#define GPIO_PUPDR_PUPDR1                    0x0000000CU
-#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
-#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
-
-#define GPIO_PUPDR_PUPDR2                    0x00000030U
-#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
-#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
-
-#define GPIO_PUPDR_PUPDR3                    0x000000C0U
-#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
-#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
-
-#define GPIO_PUPDR_PUPDR4                    0x00000300U
-#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
-#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
-
-#define GPIO_PUPDR_PUPDR5                    0x00000C00U
-#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
-#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
-
-#define GPIO_PUPDR_PUPDR6                    0x00003000U
-#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
-#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
-
-#define GPIO_PUPDR_PUPDR7                    0x0000C000U
-#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
-#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
-
-#define GPIO_PUPDR_PUPDR8                    0x00030000U
-#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
-#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
-
-#define GPIO_PUPDR_PUPDR9                    0x000C0000U
-#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
-#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
-
-#define GPIO_PUPDR_PUPDR10                   0x00300000U
-#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
-#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
-
-#define GPIO_PUPDR_PUPDR11                   0x00C00000U
-#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
-#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
-
-#define GPIO_PUPDR_PUPDR12                   0x03000000U
-#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
-#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
-
-#define GPIO_PUPDR_PUPDR13                   0x0C000000U
-#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
-#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
-
-#define GPIO_PUPDR_PUPDR14                   0x30000000U
-#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
-#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
-
-#define GPIO_PUPDR_PUPDR15                   0xC0000000U
-#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
-#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       0x00000001U
-#define GPIO_IDR_IDR_1                       0x00000002U
-#define GPIO_IDR_IDR_2                       0x00000004U
-#define GPIO_IDR_IDR_3                       0x00000008U
-#define GPIO_IDR_IDR_4                       0x00000010U
-#define GPIO_IDR_IDR_5                       0x00000020U
-#define GPIO_IDR_IDR_6                       0x00000040U
-#define GPIO_IDR_IDR_7                       0x00000080U
-#define GPIO_IDR_IDR_8                       0x00000100U
-#define GPIO_IDR_IDR_9                       0x00000200U
-#define GPIO_IDR_IDR_10                      0x00000400U
-#define GPIO_IDR_IDR_11                      0x00000800U
-#define GPIO_IDR_IDR_12                      0x00001000U
-#define GPIO_IDR_IDR_13                      0x00002000U
-#define GPIO_IDR_IDR_14                      0x00004000U
-#define GPIO_IDR_IDR_15                      0x00008000U
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       0x00000001U
-#define GPIO_ODR_ODR_1                       0x00000002U
-#define GPIO_ODR_ODR_2                       0x00000004U
-#define GPIO_ODR_ODR_3                       0x00000008U
-#define GPIO_ODR_ODR_4                       0x00000010U
-#define GPIO_ODR_ODR_5                       0x00000020U
-#define GPIO_ODR_ODR_6                       0x00000040U
-#define GPIO_ODR_ODR_7                       0x00000080U
-#define GPIO_ODR_ODR_8                       0x00000100U
-#define GPIO_ODR_ODR_9                       0x00000200U
-#define GPIO_ODR_ODR_10                      0x00000400U
-#define GPIO_ODR_ODR_11                      0x00000800U
-#define GPIO_ODR_ODR_12                      0x00001000U
-#define GPIO_ODR_ODR_13                      0x00002000U
-#define GPIO_ODR_ODR_14                      0x00004000U
-#define GPIO_ODR_ODR_15                      0x00008000U
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       0x00000001U
-#define GPIO_BSRR_BS_1                       0x00000002U
-#define GPIO_BSRR_BS_2                       0x00000004U
-#define GPIO_BSRR_BS_3                       0x00000008U
-#define GPIO_BSRR_BS_4                       0x00000010U
-#define GPIO_BSRR_BS_5                       0x00000020U
-#define GPIO_BSRR_BS_6                       0x00000040U
-#define GPIO_BSRR_BS_7                       0x00000080U
-#define GPIO_BSRR_BS_8                       0x00000100U
-#define GPIO_BSRR_BS_9                       0x00000200U
-#define GPIO_BSRR_BS_10                      0x00000400U
-#define GPIO_BSRR_BS_11                      0x00000800U
-#define GPIO_BSRR_BS_12                      0x00001000U
-#define GPIO_BSRR_BS_13                      0x00002000U
-#define GPIO_BSRR_BS_14                      0x00004000U
-#define GPIO_BSRR_BS_15                      0x00008000U
-#define GPIO_BSRR_BR_0                       0x00010000U
-#define GPIO_BSRR_BR_1                       0x00020000U
-#define GPIO_BSRR_BR_2                       0x00040000U
-#define GPIO_BSRR_BR_3                       0x00080000U
-#define GPIO_BSRR_BR_4                       0x00100000U
-#define GPIO_BSRR_BR_5                       0x00200000U
-#define GPIO_BSRR_BR_6                       0x00400000U
-#define GPIO_BSRR_BR_7                       0x00800000U
-#define GPIO_BSRR_BR_8                       0x01000000U
-#define GPIO_BSRR_BR_9                       0x02000000U
-#define GPIO_BSRR_BR_10                      0x04000000U
-#define GPIO_BSRR_BR_11                      0x08000000U
-#define GPIO_BSRR_BR_12                      0x10000000U
-#define GPIO_BSRR_BR_13                      0x20000000U
-#define GPIO_BSRR_BR_14                      0x40000000U
-#define GPIO_BSRR_BR_15                      0x80000000U
-
-/****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0                       0x00000001U
-#define GPIO_LCKR_LCK1                       0x00000002U
-#define GPIO_LCKR_LCK2                       0x00000004U
-#define GPIO_LCKR_LCK3                       0x00000008U
-#define GPIO_LCKR_LCK4                       0x00000010U
-#define GPIO_LCKR_LCK5                       0x00000020U
-#define GPIO_LCKR_LCK6                       0x00000040U
-#define GPIO_LCKR_LCK7                       0x00000080U
-#define GPIO_LCKR_LCK8                       0x00000100U
-#define GPIO_LCKR_LCK9                       0x00000200U
-#define GPIO_LCKR_LCK10                      0x00000400U
-#define GPIO_LCKR_LCK11                      0x00000800U
-#define GPIO_LCKR_LCK12                      0x00001000U
-#define GPIO_LCKR_LCK13                      0x00002000U
-#define GPIO_LCKR_LCK14                      0x00004000U
-#define GPIO_LCKR_LCK15                      0x00008000U
-#define GPIO_LCKR_LCKK                       0x00010000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Inter-integrated Circuit Interface                    */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          0x00000001U     /*!<Peripheral Enable                             */
-#define  I2C_CR1_SMBUS                       0x00000002U     /*!<SMBus Mode                                    */
-#define  I2C_CR1_SMBTYPE                     0x00000008U     /*!<SMBus Type                                    */
-#define  I2C_CR1_ENARP                       0x00000010U     /*!<ARP Enable                                    */
-#define  I2C_CR1_ENPEC                       0x00000020U     /*!<PEC Enable                                    */
-#define  I2C_CR1_ENGC                        0x00000040U     /*!<General Call Enable                           */
-#define  I2C_CR1_NOSTRETCH                   0x00000080U     /*!<Clock Stretching Disable (Slave mode)  */
-#define  I2C_CR1_START                       0x00000100U     /*!<Start Generation                              */
-#define  I2C_CR1_STOP                        0x00000200U     /*!<Stop Generation                               */
-#define  I2C_CR1_ACK                         0x00000400U     /*!<Acknowledge Enable                            */
-#define  I2C_CR1_POS                         0x00000800U     /*!<Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         0x00001000U     /*!<Packet Error Checking                         */
-#define  I2C_CR1_ALERT                       0x00002000U     /*!<SMBus Alert                                   */
-#define  I2C_CR1_SWRST                       0x00008000U     /*!<Software Reset                                */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        0x0000003FU     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
-#define  I2C_CR2_FREQ_0                      0x00000001U     /*!<Bit 0 */
-#define  I2C_CR2_FREQ_1                      0x00000002U     /*!<Bit 1 */
-#define  I2C_CR2_FREQ_2                      0x00000004U     /*!<Bit 2 */
-#define  I2C_CR2_FREQ_3                      0x00000008U     /*!<Bit 3 */
-#define  I2C_CR2_FREQ_4                      0x00000010U     /*!<Bit 4 */
-#define  I2C_CR2_FREQ_5                      0x00000020U     /*!<Bit 5 */
-
-#define  I2C_CR2_ITERREN                     0x00000100U     /*!<Error Interrupt Enable  */
-#define  I2C_CR2_ITEVTEN                     0x00000200U     /*!<Event Interrupt Enable  */
-#define  I2C_CR2_ITBUFEN                     0x00000400U     /*!<Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       0x00000800U     /*!<DMA Requests Enable     */
-#define  I2C_CR2_LAST                        0x00001000U     /*!<DMA Last Transfer       */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     0x000000FEU     /*!<Interface Address */
-#define  I2C_OAR1_ADD8_9                     0x00000300U     /*!<Interface Address */
-
-#define  I2C_OAR1_ADD0                       0x00000001U     /*!<Bit 0 */
-#define  I2C_OAR1_ADD1                       0x00000002U     /*!<Bit 1 */
-#define  I2C_OAR1_ADD2                       0x00000004U     /*!<Bit 2 */
-#define  I2C_OAR1_ADD3                       0x00000008U     /*!<Bit 3 */
-#define  I2C_OAR1_ADD4                       0x00000010U     /*!<Bit 4 */
-#define  I2C_OAR1_ADD5                       0x00000020U     /*!<Bit 5 */
-#define  I2C_OAR1_ADD6                       0x00000040U     /*!<Bit 6 */
-#define  I2C_OAR1_ADD7                       0x00000080U     /*!<Bit 7 */
-#define  I2C_OAR1_ADD8                       0x00000100U     /*!<Bit 8 */
-#define  I2C_OAR1_ADD9                       0x00000200U     /*!<Bit 9 */
-
-#define  I2C_OAR1_ADDMODE                    0x00008000U     /*!<Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     0x00000001U        /*!<Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       0x000000FEU        /*!<Interface address           */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           0x000000FFU        /*!<8-bit Data Register         */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          0x00000001U     /*!<Start Bit (Master mode)                  */
-#define  I2C_SR1_ADDR                        0x00000002U     /*!<Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         0x00000004U     /*!<Byte Transfer Finished                          */
-#define  I2C_SR1_ADD10                       0x00000008U     /*!<10-bit header sent (Master mode)         */
-#define  I2C_SR1_STOPF                       0x00000010U     /*!<Stop detection (Slave mode)              */
-#define  I2C_SR1_RXNE                        0x00000040U     /*!<Data Register not Empty (receivers)      */
-#define  I2C_SR1_TXE                         0x00000080U     /*!<Data Register Empty (transmitters)       */
-#define  I2C_SR1_BERR                        0x00000100U     /*!<Bus Error                                       */
-#define  I2C_SR1_ARLO                        0x00000200U     /*!<Arbitration Lost (master mode)           */
-#define  I2C_SR1_AF                          0x00000400U     /*!<Acknowledge Failure                             */
-#define  I2C_SR1_OVR                         0x00000800U     /*!<Overrun/Underrun                                */
-#define  I2C_SR1_PECERR                      0x00001000U     /*!<PEC Error in reception                          */
-#define  I2C_SR1_TIMEOUT                     0x00004000U     /*!<Timeout or Tlow Error                           */
-#define  I2C_SR1_SMBALERT                    0x00008000U     /*!<SMBus Alert                                     */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         0x00000001U     /*!<Master/Slave                              */
-#define  I2C_SR2_BUSY                        0x00000002U     /*!<Bus Busy                                  */
-#define  I2C_SR2_TRA                         0x00000004U     /*!<Transmitter/Receiver                      */
-#define  I2C_SR2_GENCALL                     0x00000010U     /*!<General Call Address (Slave mode)  */
-#define  I2C_SR2_SMBDEFAULT                  0x00000020U     /*!<SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     0x00000040U     /*!<SMBus Host Header (Slave mode)     */
-#define  I2C_SR2_DUALF                       0x00000080U     /*!<Dual Flag (Slave mode)             */
-#define  I2C_SR2_PEC                         0x0000FF00U     /*!<Packet Error Checking Register            */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         0x00000FFFU     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        0x00004000U     /*!<Fast Mode Duty Cycle                                       */
-#define  I2C_CCR_FS                          0x00008000U     /*!<I2C Master Mode Selection                                  */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     0x0000003FU     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************  Bit definition for I2C_FLTR register  *******************/
-#define  I2C_FLTR_DNF                        0x0000000FU     /*!<Digital Noise Filter */
-#define  I2C_FLTR_ANOFF                      0x00000010U     /*!<Analog Noise Filter OFF */
-
-/******************************************************************************/
-/*                                                                            */
-/*        Fast Mode Plus Inter-integrated Circuit Interface (I2C)             */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define  FMPI2C_CR1_PE                        0x00000001U        /*!< Peripheral enable                   */
-#define  FMPI2C_CR1_TXIE                      0x00000002U        /*!< TX interrupt enable                 */
-#define  FMPI2C_CR1_RXIE                      0x00000004U        /*!< RX interrupt enable                 */
-#define  FMPI2C_CR1_ADDRIE                    0x00000008U        /*!< Address match interrupt enable      */
-#define  FMPI2C_CR1_NACKIE                    0x00000010U        /*!< NACK received interrupt enable      */
-#define  FMPI2C_CR1_STOPIE                    0x00000020U        /*!< STOP detection interrupt enable     */
-#define  FMPI2C_CR1_TCIE                      0x00000040U        /*!< Transfer complete interrupt enable  */
-#define  FMPI2C_CR1_ERRIE                     0x00000080U        /*!< Errors interrupt enable             */
-#define  FMPI2C_CR1_DFN                       0x00000F00U        /*!< Digital noise filter                */
-#define  FMPI2C_CR1_ANFOFF                    0x00001000U        /*!< Analog noise filter OFF             */
-#define  FMPI2C_CR1_TXDMAEN                   0x00004000U        /*!< DMA transmission requests enable    */
-#define  FMPI2C_CR1_RXDMAEN                   0x00008000U        /*!< DMA reception requests enable       */
-#define  FMPI2C_CR1_SBC                       0x00010000U        /*!< Slave byte control                  */
-#define  FMPI2C_CR1_NOSTRETCH                 0x00020000U        /*!< Clock stretching disable            */
-#define  FMPI2C_CR1_GCEN                      0x00080000U        /*!< General call enable                 */
-#define  FMPI2C_CR1_SMBHEN                    0x00100000U        /*!< SMBus host address enable           */
-#define  FMPI2C_CR1_SMBDEN                    0x00200000U        /*!< SMBus device default address enable */
-#define  FMPI2C_CR1_ALERTEN                   0x00400000U        /*!< SMBus alert enable                  */
-#define  FMPI2C_CR1_PECEN                     0x00800000U        /*!< PEC enable                          */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define  FMPI2C_CR2_SADD                      0x000003FFU        /*!< Slave address (master mode)                             */
-#define  FMPI2C_CR2_RD_WRN                    0x00000400U        /*!< Transfer direction (master mode)                        */
-#define  FMPI2C_CR2_ADD10                     0x00000800U        /*!< 10-bit addressing mode (master mode)                    */
-#define  FMPI2C_CR2_HEAD10R                   0x00001000U        /*!< 10-bit address header only read direction (master mode) */
-#define  FMPI2C_CR2_START                     0x00002000U        /*!< START generation                                        */
-#define  FMPI2C_CR2_STOP                      0x00004000U        /*!< STOP generation (master mode)                           */
-#define  FMPI2C_CR2_NACK                      0x00008000U        /*!< NACK generation (slave mode)                            */
-#define  FMPI2C_CR2_NBYTES                    0x00FF0000U        /*!< Number of bytes                                         */
-#define  FMPI2C_CR2_RELOAD                    0x01000000U        /*!< NBYTES reload mode                                      */
-#define  FMPI2C_CR2_AUTOEND                   0x02000000U        /*!< Automatic end mode (master mode)                        */
-#define  FMPI2C_CR2_PECBYTE                   0x04000000U        /*!< Packet error checking byte                              */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define  FMPI2C_OAR1_OA1                      0x000003FFU        /*!< Interface own address 1   */
-#define  FMPI2C_OAR1_OA1MODE                  0x00000400U        /*!< Own address 1 10-bit mode */
-#define  FMPI2C_OAR1_OA1EN                    0x00008000U        /*!< Own address 1 enable      */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define  FMPI2C_OAR2_OA2                      0x000000FEU        /*!< Interface own address 2 */
-#define  FMPI2C_OAR2_OA2MSK                   0x00000700U        /*!< Own address 2 masks     */
-#define  FMPI2C_OAR2_OA2EN                    0x00008000U        /*!< Own address 2 enable    */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define  FMPI2C_TIMINGR_SCLL                  0x000000FFU        /*!< SCL low period (master mode)  */
-#define  FMPI2C_TIMINGR_SCLH                  0x0000FF00U        /*!< SCL high period (master mode) */
-#define  FMPI2C_TIMINGR_SDADEL                0x000F0000U        /*!< Data hold time                */
-#define  FMPI2C_TIMINGR_SCLDEL                0x00F00000U        /*!< Data setup time               */
-#define  FMPI2C_TIMINGR_PRESC                 0xF0000000U        /*!< Timings prescaler             */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define  FMPI2C_TIMEOUTR_TIMEOUTA             0x00000FFFU        /*!< Bus timeout A                 */
-#define  FMPI2C_TIMEOUTR_TIDLE                0x00001000U        /*!< Idle clock timeout detection  */
-#define  FMPI2C_TIMEOUTR_TIMOUTEN             0x00008000U        /*!< Clock timeout enable          */
-#define  FMPI2C_TIMEOUTR_TIMEOUTB             0x0FFF0000U        /*!< Bus timeout B                 */
-#define  FMPI2C_TIMEOUTR_TEXTEN               0x80000000U        /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define  FMPI2C_ISR_TXE                       0x00000001U        /*!< Transmit data register empty     */
-#define  FMPI2C_ISR_TXIS                      0x00000002U        /*!< Transmit interrupt status        */
-#define  FMPI2C_ISR_RXNE                      0x00000004U        /*!< Receive data register not empty  */
-#define  FMPI2C_ISR_ADDR                      0x00000008U        /*!< Address matched (slave mode)     */
-#define  FMPI2C_ISR_NACKF                     0x00000010U        /*!< NACK received flag               */
-#define  FMPI2C_ISR_STOPF                     0x00000020U        /*!< STOP detection flag              */
-#define  FMPI2C_ISR_TC                        0x00000040U        /*!< Transfer complete (master mode)  */
-#define  FMPI2C_ISR_TCR                       0x00000080U        /*!< Transfer complete reload         */
-#define  FMPI2C_ISR_BERR                      0x00000100U        /*!< Bus error                        */
-#define  FMPI2C_ISR_ARLO                      0x00000200U        /*!< Arbitration lost                 */
-#define  FMPI2C_ISR_OVR                       0x00000400U        /*!< Overrun/Underrun                 */
-#define  FMPI2C_ISR_PECERR                    0x00000800U        /*!< PEC error in reception           */
-#define  FMPI2C_ISR_TIMEOUT                   0x00001000U        /*!< Timeout or Tlow detection flag   */
-#define  FMPI2C_ISR_ALERT                     0x00002000U        /*!< SMBus alert                      */
-#define  FMPI2C_ISR_BUSY                      0x00008000U        /*!< Bus busy                         */
-#define  FMPI2C_ISR_DIR                       0x00010000U        /*!< Transfer direction (slave mode)  */
-#define  FMPI2C_ISR_ADDCODE                   0x00FE0000U        /*!< Address match code (slave mode)  */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define  FMPI2C_ICR_ADDRCF                    0x00000008U        /*!< Address matched clear flag  */
-#define  FMPI2C_ICR_NACKCF                    0x00000010U        /*!< NACK clear flag             */
-#define  FMPI2C_ICR_STOPCF                    0x00000020U        /*!< STOP detection clear flag   */
-#define  FMPI2C_ICR_BERRCF                    0x00000100U        /*!< Bus error clear flag        */
-#define  FMPI2C_ICR_ARLOCF                    0x00000200U        /*!< Arbitration lost clear flag */
-#define  FMPI2C_ICR_OVRCF                     0x00000400U        /*!< Overrun/Underrun clear flag */
-#define  FMPI2C_ICR_PECCF                     0x00000800U        /*!< PAC error clear flag        */
-#define  FMPI2C_ICR_TIMOUTCF                  0x00001000U        /*!< Timeout clear flag          */
-#define  FMPI2C_ICR_ALERTCF                   0x00002000U        /*!< Alert clear flag            */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define  FMPI2C_PECR_PEC                      0x000000FFU        /*!< PEC register */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define  FMPI2C_RXDR_RXDATA                   0x000000FFU        /*!< 8-bit receive data */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define  FMPI2C_TXDR_TXDATA                   0x000000FFU        /*!< 8-bit transmit data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Independent WATCHDOG                             */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         0x01U               /*!<Watchdog prescaler value update      */
-#define  IWDG_SR_RVU                         0x02U               /*!<Watchdog counter reload value update */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                             Power Control                                  */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
-#define  PWR_CR_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
-#define  PWR_CR_CWUF                         0x00000004U     /*!< Clear Wakeup Flag                   */
-#define  PWR_CR_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
-#define  PWR_CR_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
-
-#define  PWR_CR_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        0x00000020U     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        0x00000040U     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        0x00000080U     /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
-
-#define  PWR_CR_DBP                          0x00000100U     /*!< Disable Backup Domain write protection                     */
-#define  PWR_CR_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                              */
-#define  PWR_CR_LPLVDS                       0x00000400U     /*!< Low Power Regulator Low Voltage in Deep Sleep mode         */
-#define  PWR_CR_MRLVDS                       0x00000800U     /*!< Main Regulator Low Voltage in Deep Sleep mode              */
-#define  PWR_CR_ADCDC1                       0x00002000U     /*!< Refer to AN4073 on how to use this bit                     */
-
-#define  PWR_CR_VOS                          0x0000C000U     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
-#define  PWR_CR_VOS_0                        0x00004000U     /*!< Bit 0 */
-#define  PWR_CR_VOS_1                        0x00008000U     /*!< Bit 1 */
-
-#define  PWR_CR_FMSSR                        0x00100000U     /*!< Flash Memory Sleep System Run        */
-#define  PWR_CR_FISSR                        0x00200000U     /*!< Flash Interface Stop while System Run */
-/* Legacy define */
-#define  PWR_CR_PMODE                        PWR_CR_VOS
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         0x00000001U     /*!< Wakeup Flag                                      */
-#define  PWR_CSR_SBF                         0x00000002U     /*!< Standby Flag                                     */
-#define  PWR_CSR_PVDO                        0x00000004U     /*!< PVD Output                                       */
-#define  PWR_CSR_BRR                         0x00000008U     /*!< Backup regulator ready                           */
-#define  PWR_CSR_EWUP                        0x00000100U     /*!< Enable WKUP pin                                  */
-#define  PWR_CSR_BRE                         0x00000200U     /*!< Backup regulator enable                          */
-#define  PWR_CSR_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
-
-/* Legacy define */
-#define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        0x00000001U
-#define  RCC_CR_HSIRDY                       0x00000002U
-
-#define  RCC_CR_HSITRIM                      0x000000F8U
-#define  RCC_CR_HSITRIM_0                    0x00000008U/*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    0x00000010U/*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    0x00000020U/*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    0x00000040U/*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    0x00000080U/*!<Bit 4 */
-
-#define  RCC_CR_HSICAL                       0x0000FF00U
-#define  RCC_CR_HSICAL_0                     0x00000100U/*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     0x00000200U/*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     0x00000400U/*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     0x00000800U/*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     0x00001000U/*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     0x00002000U/*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     0x00004000U/*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     0x00008000U/*!<Bit 7 */
-
-#define  RCC_CR_HSEON                        0x00010000U
-#define  RCC_CR_HSERDY                       0x00020000U
-#define  RCC_CR_HSEBYP                       0x00040000U
-#define  RCC_CR_CSSON                        0x00080000U
-#define  RCC_CR_PLLON                        0x01000000U
-#define  RCC_CR_PLLRDY                       0x02000000U
-
-/********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    0x0000003FU
-#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
-#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
-#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
-#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
-#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
-#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
-
-#define  RCC_PLLCFGR_PLLN                     0x00007FC0U
-#define  RCC_PLLCFGR_PLLN_0                   0x00000040U
-#define  RCC_PLLCFGR_PLLN_1                   0x00000080U
-#define  RCC_PLLCFGR_PLLN_2                   0x00000100U
-#define  RCC_PLLCFGR_PLLN_3                   0x00000200U
-#define  RCC_PLLCFGR_PLLN_4                   0x00000400U
-#define  RCC_PLLCFGR_PLLN_5                   0x00000800U
-#define  RCC_PLLCFGR_PLLN_6                   0x00001000U
-#define  RCC_PLLCFGR_PLLN_7                   0x00002000U
-#define  RCC_PLLCFGR_PLLN_8                   0x00004000U
-
-#define  RCC_PLLCFGR_PLLP                    0x00030000U
-#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
-#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
-
-#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
-
-#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
-#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
-#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
-#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
-#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
-
-#define  RCC_PLLCFGR_PLLR                    0x70000000U
-#define  RCC_PLLCFGR_PLLR_0                  0x10000000U
-#define  RCC_PLLCFGR_PLLR_1                  0x20000000U
-#define  RCC_PLLCFGR_PLLR_2                  0x40000000U
-/********************  Bit definition for RCC_CFGR register  ******************/
-/*!< SW configuration */
-#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
-
-#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
-
-#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
-
-#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
-
-/*!< MCO1EN configuration */
-#define  RCC_CFGR_MCO1EN                     0x00000100U        /*!< MCO1EN bit */
-
-/*!< MCO2EN configuration */
-#define  RCC_CFGR_MCO2EN                     0x00000200U        /*!< MCO2EN bit */
-
-/*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
-
-/*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     0x001F0000U
-#define  RCC_CFGR_RTCPRE_0                   0x00010000U
-#define  RCC_CFGR_RTCPRE_1                   0x00020000U
-#define  RCC_CFGR_RTCPRE_2                   0x00040000U
-#define  RCC_CFGR_RTCPRE_3                   0x00080000U
-#define  RCC_CFGR_RTCPRE_4                   0x00100000U
-
-/*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       0x00600000U
-#define  RCC_CFGR_MCO1_0                     0x00200000U
-#define  RCC_CFGR_MCO1_1                     0x00400000U
-
-#define  RCC_CFGR_MCO1PRE                    0x07000000U
-#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
-#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
-#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
-
-#define  RCC_CFGR_MCO2PRE                    0x38000000U
-#define  RCC_CFGR_MCO2PRE_0                  0x08000000U
-#define  RCC_CFGR_MCO2PRE_1                  0x10000000U
-#define  RCC_CFGR_MCO2PRE_2                  0x20000000U
-
-#define  RCC_CFGR_MCO2                       0xC0000000U
-#define  RCC_CFGR_MCO2_0                     0x40000000U
-#define  RCC_CFGR_MCO2_1                     0x80000000U
-
-/********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     0x00000001U
-#define  RCC_CIR_LSERDYF                     0x00000002U
-#define  RCC_CIR_HSIRDYF                     0x00000004U
-#define  RCC_CIR_HSERDYF                     0x00000008U
-#define  RCC_CIR_PLLRDYF                     0x00000010U
-
-#define  RCC_CIR_CSSF                        0x00000080U
-#define  RCC_CIR_LSIRDYIE                    0x00000100U
-#define  RCC_CIR_LSERDYIE                    0x00000200U
-#define  RCC_CIR_HSIRDYIE                    0x00000400U
-#define  RCC_CIR_HSERDYIE                    0x00000800U
-#define  RCC_CIR_PLLRDYIE                    0x00001000U
-
-#define  RCC_CIR_LSIRDYC                     0x00010000U
-#define  RCC_CIR_LSERDYC                     0x00020000U
-#define  RCC_CIR_HSIRDYC                     0x00040000U
-#define  RCC_CIR_HSERDYC                     0x00080000U
-#define  RCC_CIR_PLLRDYC                     0x00100000U
-
-#define  RCC_CIR_CSSC                        0x00800000U
-
-/********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
-#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
-#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
-#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
-#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
-#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
-#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
-#define  RCC_AHB1RSTR_RNGRST                 0x80000000U
-
-/********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM5RST                0x00000008U
-#define  RCC_APB1RSTR_TIM6RST                0x00000010U
-#define  RCC_APB1RSTR_LPTIM1RST              0x00000200U
-#define  RCC_APB1RSTR_WWDGRST                0x00000800U
-#define  RCC_APB1RSTR_SPI2RST                0x00004000U
-#define  RCC_APB1RSTR_USART2RST              0x00020000U
-#define  RCC_APB1RSTR_I2C1RST                0x00200000U
-#define  RCC_APB1RSTR_I2C2RST                0x00400000U
-#define  RCC_APB1RSTR_FMPI2C1RST             0x01000000U
-#define  RCC_APB1RSTR_PWRRST                 0x10000000U
-#define  RCC_APB1RSTR_DACRST                 0x20000000U
-
-/********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                0x00000001U
-#define  RCC_APB2RSTR_USART1RST              0x00000010U
-#define  RCC_APB2RSTR_USART6RST              0x00000020U
-#define  RCC_APB2RSTR_ADCRST                 0x00000100U
-#define  RCC_APB2RSTR_SPI1RST                0x00001000U
-#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
-#define  RCC_APB2RSTR_TIM9RST                0x00010000U
-#define  RCC_APB2RSTR_TIM11RST               0x00040000U
-#define  RCC_APB2RSTR_SPI5RST                0x00100000U
-
-/********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
-#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
-#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
-#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
-#define  RCC_AHB1ENR_CRCEN                   0x00001000U
-#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
-#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
-#define  RCC_AHB1ENR_RNGEN                   0x80000000U
-
-/********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM5EN                  0x00000008U
-#define  RCC_APB1ENR_TIM6EN                  0x00000010U
-#define  RCC_APB1ENR_LPTIM1EN                0x00000200U
-#define  RCC_APB1ENR_RTCAPBEN                0x00000400U
-#define  RCC_APB1ENR_WWDGEN                  0x00000800U
-#define  RCC_APB1ENR_SPI2EN                  0x00004000U
-#define  RCC_APB1ENR_USART2EN                0x00020000U
-#define  RCC_APB1ENR_I2C1EN                  0x00200000U
-#define  RCC_APB1ENR_I2C2EN                  0x00400000U
-#define  RCC_APB1ENR_FMPI2C1EN               0x01000000U
-#define  RCC_APB1ENR_PWREN                   0x10000000U
-#define  RCC_APB1ENR_DACEN                   0x20000000U
-
-/********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  0x00000001U
-#define  RCC_APB2ENR_USART1EN                0x00000010U
-#define  RCC_APB2ENR_USART6EN                0x00000020U
-#define  RCC_APB2ENR_ADC1EN                  0x00000100U
-#define  RCC_APB2ENR_SPI1EN                  0x00001000U
-#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
-#define  RCC_APB2ENR_EXTITEN                 0x00008000U
-#define  RCC_APB2ENR_TIM9EN                  0x00010000U
-#define  RCC_APB2ENR_TIM11EN                 0x00040000U
-#define  RCC_APB2ENR_SPI5EN                  0x00100000U
-
-/********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
-#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
-#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
-#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
-#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
-#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
-#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
-#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
-#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
-#define  RCC_AHB1LPENR_RNGLPEN               0x80000000U
-
-/********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
-#define  RCC_APB1LPENR_TIM6LPEN              0x00000010U
-#define  RCC_APB1LPENR_LPTIM1LPEN            0x00000200U
-#define  RCC_APB1LPENR_RTCAPBLPEN            0x00000400U
-#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
-#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U
-#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
-#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
-#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
-#define  RCC_APB1LPENR_FMPI2C1LPEN           0x01000000U
-#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
-#define  RCC_APB1LPENR_DACLPEN               0x20000000U
-
-/********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
-#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
-#define  RCC_APB2LPENR_USART6LPEN            0x00000020U
-#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
-#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
-#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
-#define  RCC_APB2LPENR_EXTITLPEN             0x00008000U
-#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
-#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
-#define  RCC_APB2LPENR_SPI5LPEN              0x00100000U
-
-/********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      0x00000001U
-#define  RCC_BDCR_LSERDY                     0x00000002U
-#define  RCC_BDCR_LSEBYP                     0x00000004U
-#define  RCC_BDCR_LSEMOD                     0x00000008U
-
-#define  RCC_BDCR_RTCSEL                    0x00000300U
-#define  RCC_BDCR_RTCSEL_0                  0x00000100U
-#define  RCC_BDCR_RTCSEL_1                  0x00000200U
-
-#define  RCC_BDCR_RTCEN                      0x00008000U
-#define  RCC_BDCR_BDRST                      0x00010000U
-
-/********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       0x00000001U
-#define  RCC_CSR_LSIRDY                      0x00000002U
-#define  RCC_CSR_RMVF                        0x01000000U
-#define  RCC_CSR_BORRSTF                     0x02000000U
-#define  RCC_CSR_PADRSTF                     0x04000000U
-#define  RCC_CSR_PORRSTF                     0x08000000U
-#define  RCC_CSR_SFTRSTF                     0x10000000U
-#define  RCC_CSR_WDGRSTF                     0x20000000U
-#define  RCC_CSR_WWDGRSTF                    0x40000000U
-#define  RCC_CSR_LPWRRSTF                    0x80000000U
-
-/********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    0x00001FFFU
-#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
-#define  RCC_SSCGR_SPREADSEL                 0x40000000U
-#define  RCC_SSCGR_SSCGEN                    0x80000000U
-
-/********************  Bit definition for RCC_DCKCFGR register  ***************/
-#define  RCC_DCKCFGR_TIMPRE                  0x01000000U
-#define  RCC_DCKCFGR_I2SSRC                  0x06000000U
-#define  RCC_DCKCFGR_I2SSRC_0                0x02000000U
-#define  RCC_DCKCFGR_I2SSRC_1                0x04000000U
-
-/********************  Bit definition for RCC_CKGATENR register  **************/
-#define  RCC_CKGATENR_AHB2APB1_CKEN          0x00000001U
-#define  RCC_CKGATENR_AHB2APB2_CKEN          0x00000002U
-#define  RCC_CKGATENR_CM4DBG_CKEN            0x00000004U
-#define  RCC_CKGATENR_SPARE_CKEN             0x00000008U
-#define  RCC_CKGATENR_SRAM_CKEN              0x00000010U
-#define  RCC_CKGATENR_FLITF_CKEN             0x00000020U
-#define  RCC_CKGATENR_RCC_CKEN               0x00000040U
-
-/********************  Bit definition for RCC_DCKCFGR2 register  **************/
-#define  RCC_DCKCFGR2_FMPI2C1SEL             0x00C00000U
-#define  RCC_DCKCFGR2_FMPI2C1SEL_0           0x00400000U
-#define  RCC_DCKCFGR2_FMPI2C1SEL_1           0x00800000U
-#define  RCC_DCKCFGR2_LPTIM1SEL              0xC0000000U
-#define  RCC_DCKCFGR2_LPTIM1SEL_0            0x40000000U
-#define  RCC_DCKCFGR2_LPTIM1SEL_1            0x80000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    RNG                                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN                         0x00000004U
-#define RNG_CR_IE                            0x00000008U
-
-/********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY                          0x00000001U
-#define RNG_SR_CECS                          0x00000002U
-#define RNG_SR_SECS                          0x00000004U
-#define RNG_SR_CEIS                          0x00000020U
-#define RNG_SR_SEIS                          0x00000040U
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            0x00400000U
-#define RTC_TR_HT                            0x00300000U
-#define RTC_TR_HT_0                          0x00100000U
-#define RTC_TR_HT_1                          0x00200000U
-#define RTC_TR_HU                            0x000F0000U
-#define RTC_TR_HU_0                          0x00010000U
-#define RTC_TR_HU_1                          0x00020000U
-#define RTC_TR_HU_2                          0x00040000U
-#define RTC_TR_HU_3                          0x00080000U
-#define RTC_TR_MNT                           0x00007000U
-#define RTC_TR_MNT_0                         0x00001000U
-#define RTC_TR_MNT_1                         0x00002000U
-#define RTC_TR_MNT_2                         0x00004000U
-#define RTC_TR_MNU                           0x00000F00U
-#define RTC_TR_MNU_0                         0x00000100U
-#define RTC_TR_MNU_1                         0x00000200U
-#define RTC_TR_MNU_2                         0x00000400U
-#define RTC_TR_MNU_3                         0x00000800U
-#define RTC_TR_ST                            0x00000070U
-#define RTC_TR_ST_0                          0x00000010U
-#define RTC_TR_ST_1                          0x00000020U
-#define RTC_TR_ST_2                          0x00000040U
-#define RTC_TR_SU                            0x0000000FU
-#define RTC_TR_SU_0                          0x00000001U
-#define RTC_TR_SU_1                          0x00000002U
-#define RTC_TR_SU_2                          0x00000004U
-#define RTC_TR_SU_3                          0x00000008U
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            0x00F00000U
-#define RTC_DR_YT_0                          0x00100000U
-#define RTC_DR_YT_1                          0x00200000U
-#define RTC_DR_YT_2                          0x00400000U
-#define RTC_DR_YT_3                          0x00800000U
-#define RTC_DR_YU                            0x000F0000U
-#define RTC_DR_YU_0                          0x00010000U
-#define RTC_DR_YU_1                          0x00020000U
-#define RTC_DR_YU_2                          0x00040000U
-#define RTC_DR_YU_3                          0x00080000U
-#define RTC_DR_WDU                           0x0000E000U
-#define RTC_DR_WDU_0                         0x00002000U
-#define RTC_DR_WDU_1                         0x00004000U
-#define RTC_DR_WDU_2                         0x00008000U
-#define RTC_DR_MT                            0x00001000U
-#define RTC_DR_MU                            0x00000F00U
-#define RTC_DR_MU_0                          0x00000100U
-#define RTC_DR_MU_1                          0x00000200U
-#define RTC_DR_MU_2                          0x00000400U
-#define RTC_DR_MU_3                          0x00000800U
-#define RTC_DR_DT                            0x00000030U
-#define RTC_DR_DT_0                          0x00000010U
-#define RTC_DR_DT_1                          0x00000020U
-#define RTC_DR_DU                            0x0000000FU
-#define RTC_DR_DU_0                          0x00000001U
-#define RTC_DR_DU_1                          0x00000002U
-#define RTC_DR_DU_2                          0x00000004U
-#define RTC_DR_DU_3                          0x00000008U
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           0x00800000U
-#define RTC_CR_OSEL                          0x00600000U
-#define RTC_CR_OSEL_0                        0x00200000U
-#define RTC_CR_OSEL_1                        0x00400000U
-#define RTC_CR_POL                           0x00100000U
-#define RTC_CR_COSEL                         0x00080000U
-#define RTC_CR_BCK                           0x00040000U
-#define RTC_CR_SUB1H                         0x00020000U
-#define RTC_CR_ADD1H                         0x00010000U
-#define RTC_CR_TSIE                          0x00008000U
-#define RTC_CR_WUTIE                         0x00004000U
-#define RTC_CR_ALRBIE                        0x00002000U
-#define RTC_CR_ALRAIE                        0x00001000U
-#define RTC_CR_TSE                           0x00000800U
-#define RTC_CR_WUTE                          0x00000400U
-#define RTC_CR_ALRBE                         0x00000200U
-#define RTC_CR_ALRAE                         0x00000100U
-#define RTC_CR_DCE                           0x00000080U
-#define RTC_CR_FMT                           0x00000040U
-#define RTC_CR_BYPSHAD                       0x00000020U
-#define RTC_CR_REFCKON                       0x00000010U
-#define RTC_CR_TSEDGE                        0x00000008U
-#define RTC_CR_WUCKSEL                       0x00000007U
-#define RTC_CR_WUCKSEL_0                     0x00000001U
-#define RTC_CR_WUCKSEL_1                     0x00000002U
-#define RTC_CR_WUCKSEL_2                     0x00000004U
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      0x00010000U
-#define RTC_ISR_TAMP1F                       0x00002000U
-#define RTC_ISR_TAMP2F                       0x00004000U
-#define RTC_ISR_TSOVF                        0x00001000U
-#define RTC_ISR_TSF                          0x00000800U
-#define RTC_ISR_WUTF                         0x00000400U
-#define RTC_ISR_ALRBF                        0x00000200U
-#define RTC_ISR_ALRAF                        0x00000100U
-#define RTC_ISR_INIT                         0x00000080U
-#define RTC_ISR_INITF                        0x00000040U
-#define RTC_ISR_RSF                          0x00000020U
-#define RTC_ISR_INITS                        0x00000010U
-#define RTC_ISR_SHPF                         0x00000008U
-#define RTC_ISR_WUTWF                        0x00000004U
-#define RTC_ISR_ALRBWF                       0x00000002U
-#define RTC_ISR_ALRAWF                       0x00000001U
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    0x007F0000U
-#define RTC_PRER_PREDIV_S                    0x00007FFFU
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS                       0x00000080U
-#define RTC_CALIBR_DC                        0x0000001FU
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      0x80000000U
-#define RTC_ALRMAR_WDSEL                     0x40000000U
-#define RTC_ALRMAR_DT                        0x30000000U
-#define RTC_ALRMAR_DT_0                      0x10000000U
-#define RTC_ALRMAR_DT_1                      0x20000000U
-#define RTC_ALRMAR_DU                        0x0F000000U
-#define RTC_ALRMAR_DU_0                      0x01000000U
-#define RTC_ALRMAR_DU_1                      0x02000000U
-#define RTC_ALRMAR_DU_2                      0x04000000U
-#define RTC_ALRMAR_DU_3                      0x08000000U
-#define RTC_ALRMAR_MSK3                      0x00800000U
-#define RTC_ALRMAR_PM                        0x00400000U
-#define RTC_ALRMAR_HT                        0x00300000U
-#define RTC_ALRMAR_HT_0                      0x00100000U
-#define RTC_ALRMAR_HT_1                      0x00200000U
-#define RTC_ALRMAR_HU                        0x000F0000U
-#define RTC_ALRMAR_HU_0                      0x00010000U
-#define RTC_ALRMAR_HU_1                      0x00020000U
-#define RTC_ALRMAR_HU_2                      0x00040000U
-#define RTC_ALRMAR_HU_3                      0x00080000U
-#define RTC_ALRMAR_MSK2                      0x00008000U
-#define RTC_ALRMAR_MNT                       0x00007000U
-#define RTC_ALRMAR_MNT_0                     0x00001000U
-#define RTC_ALRMAR_MNT_1                     0x00002000U
-#define RTC_ALRMAR_MNT_2                     0x00004000U
-#define RTC_ALRMAR_MNU                       0x00000F00U
-#define RTC_ALRMAR_MNU_0                     0x00000100U
-#define RTC_ALRMAR_MNU_1                     0x00000200U
-#define RTC_ALRMAR_MNU_2                     0x00000400U
-#define RTC_ALRMAR_MNU_3                     0x00000800U
-#define RTC_ALRMAR_MSK1                      0x00000080U
-#define RTC_ALRMAR_ST                        0x00000070U
-#define RTC_ALRMAR_ST_0                      0x00000010U
-#define RTC_ALRMAR_ST_1                      0x00000020U
-#define RTC_ALRMAR_ST_2                      0x00000040U
-#define RTC_ALRMAR_SU                        0x0000000FU
-#define RTC_ALRMAR_SU_0                      0x00000001U
-#define RTC_ALRMAR_SU_1                      0x00000002U
-#define RTC_ALRMAR_SU_2                      0x00000004U
-#define RTC_ALRMAR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      0x80000000U
-#define RTC_ALRMBR_WDSEL                     0x40000000U
-#define RTC_ALRMBR_DT                        0x30000000U
-#define RTC_ALRMBR_DT_0                      0x10000000U
-#define RTC_ALRMBR_DT_1                      0x20000000U
-#define RTC_ALRMBR_DU                        0x0F000000U
-#define RTC_ALRMBR_DU_0                      0x01000000U
-#define RTC_ALRMBR_DU_1                      0x02000000U
-#define RTC_ALRMBR_DU_2                      0x04000000U
-#define RTC_ALRMBR_DU_3                      0x08000000U
-#define RTC_ALRMBR_MSK3                      0x00800000U
-#define RTC_ALRMBR_PM                        0x00400000U
-#define RTC_ALRMBR_HT                        0x00300000U
-#define RTC_ALRMBR_HT_0                      0x00100000U
-#define RTC_ALRMBR_HT_1                      0x00200000U
-#define RTC_ALRMBR_HU                        0x000F0000U
-#define RTC_ALRMBR_HU_0                      0x00010000U
-#define RTC_ALRMBR_HU_1                      0x00020000U
-#define RTC_ALRMBR_HU_2                      0x00040000U
-#define RTC_ALRMBR_HU_3                      0x00080000U
-#define RTC_ALRMBR_MSK2                      0x00008000U
-#define RTC_ALRMBR_MNT                       0x00007000U
-#define RTC_ALRMBR_MNT_0                     0x00001000U
-#define RTC_ALRMBR_MNT_1                     0x00002000U
-#define RTC_ALRMBR_MNT_2                     0x00004000U
-#define RTC_ALRMBR_MNU                       0x00000F00U
-#define RTC_ALRMBR_MNU_0                     0x00000100U
-#define RTC_ALRMBR_MNU_1                     0x00000200U
-#define RTC_ALRMBR_MNU_2                     0x00000400U
-#define RTC_ALRMBR_MNU_3                     0x00000800U
-#define RTC_ALRMBR_MSK1                      0x00000080U
-#define RTC_ALRMBR_ST                        0x00000070U
-#define RTC_ALRMBR_ST_0                      0x00000010U
-#define RTC_ALRMBR_ST_1                      0x00000020U
-#define RTC_ALRMBR_ST_2                      0x00000040U
-#define RTC_ALRMBR_SU                        0x0000000FU
-#define RTC_ALRMBR_SU_0                      0x00000001U
-#define RTC_ALRMBR_SU_1                      0x00000002U
-#define RTC_ALRMBR_SU_2                      0x00000004U
-#define RTC_ALRMBR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          0x000000FFU
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           0x0000FFFFU
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     0x00007FFFU
-#define RTC_SHIFTR_ADD1S                     0x80000000U
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          0x00400000U
-#define RTC_TSTR_HT                          0x00300000U
-#define RTC_TSTR_HT_0                        0x00100000U
-#define RTC_TSTR_HT_1                        0x00200000U
-#define RTC_TSTR_HU                          0x000F0000U
-#define RTC_TSTR_HU_0                        0x00010000U
-#define RTC_TSTR_HU_1                        0x00020000U
-#define RTC_TSTR_HU_2                        0x00040000U
-#define RTC_TSTR_HU_3                        0x00080000U
-#define RTC_TSTR_MNT                         0x00007000U
-#define RTC_TSTR_MNT_0                       0x00001000U
-#define RTC_TSTR_MNT_1                       0x00002000U
-#define RTC_TSTR_MNT_2                       0x00004000U
-#define RTC_TSTR_MNU                         0x00000F00U
-#define RTC_TSTR_MNU_0                       0x00000100U
-#define RTC_TSTR_MNU_1                       0x00000200U
-#define RTC_TSTR_MNU_2                       0x00000400U
-#define RTC_TSTR_MNU_3                       0x00000800U
-#define RTC_TSTR_ST                          0x00000070U
-#define RTC_TSTR_ST_0                        0x00000010U
-#define RTC_TSTR_ST_1                        0x00000020U
-#define RTC_TSTR_ST_2                        0x00000040U
-#define RTC_TSTR_SU                          0x0000000FU
-#define RTC_TSTR_SU_0                        0x00000001U
-#define RTC_TSTR_SU_1                        0x00000002U
-#define RTC_TSTR_SU_2                        0x00000004U
-#define RTC_TSTR_SU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         0x0000E000U
-#define RTC_TSDR_WDU_0                       0x00002000U
-#define RTC_TSDR_WDU_1                       0x00004000U
-#define RTC_TSDR_WDU_2                       0x00008000U
-#define RTC_TSDR_MT                          0x00001000U
-#define RTC_TSDR_MU                          0x00000F00U
-#define RTC_TSDR_MU_0                        0x00000100U
-#define RTC_TSDR_MU_1                        0x00000200U
-#define RTC_TSDR_MU_2                        0x00000400U
-#define RTC_TSDR_MU_3                        0x00000800U
-#define RTC_TSDR_DT                          0x00000030U
-#define RTC_TSDR_DT_0                        0x00000010U
-#define RTC_TSDR_DT_1                        0x00000020U
-#define RTC_TSDR_DU                          0x0000000FU
-#define RTC_TSDR_DU_0                        0x00000001U
-#define RTC_TSDR_DU_1                        0x00000002U
-#define RTC_TSDR_DU_2                        0x00000004U
-#define RTC_TSDR_DU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        0x00008000U
-#define RTC_CALR_CALW8                       0x00004000U
-#define RTC_CALR_CALW16                      0x00002000U
-#define RTC_CALR_CALM                        0x000001FFU
-#define RTC_CALR_CALM_0                      0x00000001U
-#define RTC_CALR_CALM_1                      0x00000002U
-#define RTC_CALR_CALM_2                      0x00000004U
-#define RTC_CALR_CALM_3                      0x00000008U
-#define RTC_CALR_CALM_4                      0x00000010U
-#define RTC_CALR_CALM_5                      0x00000020U
-#define RTC_CALR_CALM_6                      0x00000040U
-#define RTC_CALR_CALM_7                      0x00000080U
-#define RTC_CALR_CALM_8                      0x00000100U
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               0x00040000U
-#define RTC_TAFCR_TSINSEL                    0x00020000U
-#define RTC_TAFCR_TAMPINSEL                  0x00010000U
-#define RTC_TAFCR_TAMPPUDIS                  0x00008000U
-#define RTC_TAFCR_TAMPPRCH                   0x00006000U
-#define RTC_TAFCR_TAMPPRCH_0                 0x00002000U
-#define RTC_TAFCR_TAMPPRCH_1                 0x00004000U
-#define RTC_TAFCR_TAMPFLT                    0x00001800U
-#define RTC_TAFCR_TAMPFLT_0                  0x00000800U
-#define RTC_TAFCR_TAMPFLT_1                  0x00001000U
-#define RTC_TAFCR_TAMPFREQ                   0x00000700U
-#define RTC_TAFCR_TAMPFREQ_0                 0x00000100U
-#define RTC_TAFCR_TAMPFREQ_1                 0x00000200U
-#define RTC_TAFCR_TAMPFREQ_2                 0x00000400U
-#define RTC_TAFCR_TAMPTS                     0x00000080U
-#define RTC_TAFCR_TAMP2TRG                   0x00000010U
-#define RTC_TAFCR_TAMP2E                     0x00000008U
-#define RTC_TAFCR_TAMPIE                     0x00000004U
-#define RTC_TAFCR_TAMP1TRG                   0x00000002U
-#define RTC_TAFCR_TAMP1E                     0x00000001U
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  0x0F000000U
-#define RTC_ALRMASSR_MASKSS_0                0x01000000U
-#define RTC_ALRMASSR_MASKSS_1                0x02000000U
-#define RTC_ALRMASSR_MASKSS_2                0x04000000U
-#define RTC_ALRMASSR_MASKSS_3                0x08000000U
-#define RTC_ALRMASSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
-#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
-#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
-#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
-#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
-#define RTC_ALRMBSSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           0xFFFFFFFFU
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        0x00000001U            /*!<Clock Phase      */
-#define  SPI_CR1_CPOL                        0x00000002U            /*!<Clock Polarity   */
-#define  SPI_CR1_MSTR                        0x00000004U            /*!<Master Selection */
-
-#define  SPI_CR1_BR                          0x00000038U            /*!<BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        0x00000008U            /*!<Bit 0 */
-#define  SPI_CR1_BR_1                        0x00000010U            /*!<Bit 1 */
-#define  SPI_CR1_BR_2                        0x00000020U            /*!<Bit 2 */
-
-#define  SPI_CR1_SPE                         0x00000040U            /*!<SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    0x00000080U            /*!<Frame Format                        */
-#define  SPI_CR1_SSI                         0x00000100U            /*!<Internal slave select               */
-#define  SPI_CR1_SSM                         0x00000200U            /*!<Software slave management           */
-#define  SPI_CR1_RXONLY                      0x00000400U            /*!<Receive only                        */
-#define  SPI_CR1_DFF                         0x00000800U            /*!<Data Frame Format                   */
-#define  SPI_CR1_CRCNEXT                     0x00001000U            /*!<Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       0x00002000U            /*!<Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      0x00004000U            /*!<Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    0x00008000U            /*!<Bidirectional data mode enable      */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     0x00000001U               /*!<Rx Buffer DMA Enable                 */
-#define  SPI_CR2_TXDMAEN                     0x00000002U               /*!<Tx Buffer DMA Enable                 */
-#define  SPI_CR2_SSOE                        0x00000004U               /*!<SS Output Enable                     */
-#define  SPI_CR2_FRF                         0x00000010U               /*!<Frame Format                         */
-#define  SPI_CR2_ERRIE                       0x00000020U               /*!<Error Interrupt Enable               */
-#define  SPI_CR2_RXNEIE                      0x00000040U               /*!<RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       0x00000080U               /*!<Tx buffer Empty Interrupt Enable     */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         0x00000001U               /*!<Receive buffer Not Empty */
-#define  SPI_SR_TXE                          0x00000002U               /*!<Transmit buffer Empty    */
-#define  SPI_SR_CHSIDE                       0x00000004U               /*!<Channel side             */
-#define  SPI_SR_UDR                          0x00000008U               /*!<Underrun flag            */
-#define  SPI_SR_CRCERR                       0x00000010U               /*!<CRC Error flag           */
-#define  SPI_SR_MODF                         0x00000020U               /*!<Mode fault               */
-#define  SPI_SR_OVR                          0x00000040U               /*!<Overrun flag             */
-#define  SPI_SR_BSY                          0x00000080U               /*!<Busy flag                */
-#define  SPI_SR_FRE                          0x00000100U               /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           0x0000FFFFU            /*!<Data Register           */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   0x0000FFFFU            /*!<CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    0x0000FFFFU            /*!<Rx CRC Register         */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    0x0000FFFFU            /*!<Tx CRC Register         */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   0x00000001U            /*!<Channel length (number of bits per audio channel) */
-
-#define  SPI_I2SCFGR_DATLEN                  0x00000006U            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define  SPI_I2SCFGR_DATLEN_0                0x00000002U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                0x00000004U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_CKPOL                   0x00000008U            /*!<steady state clock polarity               */
-
-#define  SPI_I2SCFGR_I2SSTD                  0x00000030U            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U            /*!<PCM frame synchronization                 */
-
-#define  SPI_I2SCFGR_I2SCFG                  0x00000300U            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_I2SE                    0x00000400U            /*!<I2S Enable         */
-#define  SPI_I2SCFGR_I2SMOD                  0x00000800U            /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    0x000000FFU            /*!<I2S Linear prescaler         */
-#define  SPI_I2SPR_ODD                       0x00000100U            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     0x00000200U            /*!<Master Clock Output Enable   */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 SYSCFG                                     */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
-#define SYSCFG_MEMRMP_MEM_MODE          0x00000007U /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        0x00000001U
-#define SYSCFG_MEMRMP_MEM_MODE_1        0x00000002U
-#define SYSCFG_MEMRMP_MEM_MODE_2        0x00000004U
-
-/******************  Bit definition for SYSCFG_PMC register  ******************/
-#define SYSCFG_PMC_ADC1DC2              0x00010000U /*!< Refer to AN4073 on how to use this bit  */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
-/** 
-  * @brief   EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
-
-/** 
-  * @brief   EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
-
-/** 
-  * @brief   EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
-
-/** 
-  * @brief   EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
-/** 
-  * @brief   EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
-
-/** 
-  * @brief   EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
-
-/** 
-  * @brief   EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
-
-/** 
-  * @brief   EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
-
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
-           
-/** 
-  * @brief   EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
-
-/** 
-  * @brief   EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
-
-/** 
-  * @brief   EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
-
-/** 
-  * @brief   EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
-/** 
-  * @brief   EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
-
-/** 
-  * @brief   EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
-
-/** 
-  * @brief   EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
-
-/** 
-  * @brief   EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
-
-/******************  Bit definition for SYSCFG_CMPCR register  ****************/
-#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell ready flag */
-#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell power-down */
-
-/******************  Bit definition for SYSCFG_CFGR register  *****************/
-#define SYSCFG_CFGR_FMPI2C1_SCL         0x00000001U /*!<FM+ drive capability for FMPI2C1_SCL pin */
-#define SYSCFG_CFGR_FMPI2C1_SDA         0x00000002U /*!<FM+ drive capability for FMPI2C1_SDA pin */
-
-/******************  Bit definition for SYSCFG_CFGR2 register  *****************/
-#define SYSCFG_CFGR2_LOCKUP_LOCK        0x00000001U /*!<Core Lockup lock */
-#define SYSCFG_CFGR2_PVD_LOCK           0x00000004U /*!<PVD Lock         */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    TIM                                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
-#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
-#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
-#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
-#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
-
-#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
-
-#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
-
-#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        0x0001U            /*!<Capture/Compare Preloaded Control        */
-#define  TIM_CR2_CCUS                        0x0004U            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        0x0008U            /*!<Capture/Compare DMA Selection            */
-
-#define  TIM_CR2_MMS                         0x0070U            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
-#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
-#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
-#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        0x0007U            /*!<SMS[2:0] bits (Slave mode selection)    */
-#define  TIM_SMCR_SMS_0                      0x0001U            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      0x0002U            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      0x0004U            /*!<Bit 2 */
-
-#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
-#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
-
-#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
-
-#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
-
-#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
-#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
-#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
-#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
-#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
-#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
-#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
-#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
-#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
-#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
-#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
-#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
-#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
-#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
-#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
-#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
-#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
-#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
-#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          0x01U               /*!<Update Generation                         */
-#define  TIM_EGR_CC1G                        0x02U               /*!<Capture/Compare 1 Generation              */
-#define  TIM_EGR_CC2G                        0x04U               /*!<Capture/Compare 2 Generation              */
-#define  TIM_EGR_CC3G                        0x08U               /*!<Capture/Compare 3 Generation              */
-#define  TIM_EGR_CC4G                        0x10U               /*!<Capture/Compare 4 Generation              */
-#define  TIM_EGR_COMG                        0x20U               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          0x40U               /*!<Trigger Generation                        */
-#define  TIM_EGR_BG                          0x80U               /*!<Break Generation                          */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      0x0003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    0x0001U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    0x0002U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC1FE                     0x0004U            /*!<Output Compare 1 Fast enable                 */
-#define  TIM_CCMR1_OC1PE                     0x0008U            /*!<Output Compare 1 Preload enable              */
-
-#define  TIM_CCMR1_OC1M                      0x0070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define  TIM_CCMR1_OC1M_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    0x0040U            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC1CE                     0x0080U            /*!<Output Compare 1Clear Enable                 */
-
-#define  TIM_CCMR1_CC2S                      0x0300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    0x0100U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    0x0200U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC2FE                     0x0400U            /*!<Output Compare 2 Fast enable                 */
-#define  TIM_CCMR1_OC2PE                     0x0800U            /*!<Output Compare 2 Preload enable              */
-
-#define  TIM_CCMR1_OC2M                      0x7000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define  TIM_CCMR1_OC2M_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    0x4000U            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC2CE                     0x8000U            /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      0x0003U            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define  TIM_CCMR2_CC3S_0                    0x0001U            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    0x0002U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC3FE                     0x0004U            /*!<Output Compare 3 Fast enable           */
-#define  TIM_CCMR2_OC3PE                     0x0008U            /*!<Output Compare 3 Preload enable        */
-
-#define  TIM_CCMR2_OC3M                      0x0070U            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    0x0040U            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC3CE                     0x0080U            /*!<Output Compare 3 Clear Enable */
-
-#define  TIM_CCMR2_CC4S                      0x0300U            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    0x0100U            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    0x0200U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC4FE                     0x0400U            /*!<Output Compare 4 Fast enable    */
-#define  TIM_CCMR2_OC4PE                     0x0800U            /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR2_OC4M                      0x7000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    0x4000U            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       0x0001U            /*!<Capture/Compare 1 output enable                 */
-#define  TIM_CCER_CC1P                       0x0002U            /*!<Capture/Compare 1 output Polarity               */
-#define  TIM_CCER_CC1NE                      0x0004U            /*!<Capture/Compare 1 Complementary output enable   */
-#define  TIM_CCER_CC1NP                      0x0008U            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       0x0010U            /*!<Capture/Compare 2 output enable                 */
-#define  TIM_CCER_CC2P                       0x0020U            /*!<Capture/Compare 2 output Polarity               */
-#define  TIM_CCER_CC2NE                      0x0040U            /*!<Capture/Compare 2 Complementary output enable   */
-#define  TIM_CCER_CC2NP                      0x0080U            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       0x0100U            /*!<Capture/Compare 3 output enable                 */
-#define  TIM_CCER_CC3P                       0x0200U            /*!<Capture/Compare 3 output Polarity               */
-#define  TIM_CCER_CC3NE                      0x0400U            /*!<Capture/Compare 3 Complementary output enable   */
-#define  TIM_CCER_CC3NP                      0x0800U            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       0x1000U            /*!<Capture/Compare 4 output enable                 */
-#define  TIM_CCER_CC4P                       0x2000U            /*!<Capture/Compare 4 output Polarity               */
-#define  TIM_CCER_CC4NP                      0x8000U            /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         0xFFU               /*!<Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
-
-/*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        0x00FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      0x0001U            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      0x0002U            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      0x0004U            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      0x0008U            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      0x0010U            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      0x0020U            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      0x0040U            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      0x0080U            /*!<Bit 7 */
-
-#define  TIM_BDTR_LOCK                       0x0300U            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     0x0100U            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     0x0200U            /*!<Bit 1 */
-
-#define  TIM_BDTR_OSSI                       0x0400U            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       0x0800U            /*!<Off-State Selection for Run mode  */
-#define  TIM_BDTR_BKE                        0x1000U            /*!<Break enable                      */
-#define  TIM_BDTR_BKP                        0x2000U            /*!<Break Polarity                    */
-#define  TIM_BDTR_AOE                        0x4000U            /*!<Automatic Output enable           */
-#define  TIM_BDTR_MOE                        0x8000U            /*!<Main Output enable                */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
-
-#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Low Power Timer (LPTIM)                            */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for LPTIM_ISR register  *******************/
-#define  LPTIM_ISR_CMPM                         0x00000001U            /*!< Compare match                       */
-#define  LPTIM_ISR_ARRM                         0x00000002U            /*!< Autoreload match                    */
-#define  LPTIM_ISR_EXTTRIG                      0x00000004U            /*!< External trigger edge event         */
-#define  LPTIM_ISR_CMPOK                        0x00000008U            /*!< Compare register update OK          */
-#define  LPTIM_ISR_ARROK                        0x00000010U            /*!< Autoreload register update OK       */
-#define  LPTIM_ISR_UP                           0x00000020U            /*!< Counter direction change down to up */
-#define  LPTIM_ISR_DOWN                         0x00000040U            /*!< Counter direction change up to down */
-
-/******************  Bit definition for LPTIM_ICR register  *******************/
-#define  LPTIM_ICR_CMPMCF                       0x00000001U            /*!< Compare match Clear Flag                       */
-#define  LPTIM_ICR_ARRMCF                       0x00000002U            /*!< Autoreload match Clear Flag                    */
-#define  LPTIM_ICR_EXTTRIGCF                    0x00000004U            /*!< External trigger edge event Clear Flag         */
-#define  LPTIM_ICR_CMPOKCF                      0x00000008U            /*!< Compare register update OK Clear Flag          */
-#define  LPTIM_ICR_ARROKCF                      0x00000010U            /*!< Autoreload register update OK Clear Flag       */
-#define  LPTIM_ICR_UPCF                         0x00000020U            /*!< Counter direction change down to up Clear Flag */
-#define  LPTIM_ICR_DOWNCF                       0x00000040U            /*!< Counter direction change up to down Clear Flag */
-
-/******************  Bit definition for LPTIM_IER register ********************/
-#define  LPTIM_IER_CMPMIE                       0x00000001U            /*!< Compare match Interrupt Enable                       */
-#define  LPTIM_IER_ARRMIE                       0x00000002U            /*!< Autoreload match Interrupt Enable                    */
-#define  LPTIM_IER_EXTTRIGIE                    0x00000004U            /*!< External trigger edge event Interrupt Enable         */
-#define  LPTIM_IER_CMPOKIE                      0x00000008U            /*!< Compare register update OK Interrupt Enable          */
-#define  LPTIM_IER_ARROKIE                      0x00000010U            /*!< Autoreload register update OK Interrupt Enable       */
-#define  LPTIM_IER_UPIE                         0x00000020U            /*!< Counter direction change down to up Interrupt Enable */
-#define  LPTIM_IER_DOWNIE                       0x00000040U            /*!< Counter direction change up to down Interrupt Enable */
-
-/******************  Bit definition for LPTIM_CFGR register *******************/
-#define  LPTIM_CFGR_CKSEL                       0x00000001U             /*!< Clock selector */
-
-#define  LPTIM_CFGR_CKPOL                       0x00000006U             /*!< CKPOL[1:0] bits (Clock polarity) */
-#define  LPTIM_CFGR_CKPOL_0                     0x00000002U             /*!< Bit 0 */
-#define  LPTIM_CFGR_CKPOL_1                     0x00000004U             /*!< Bit 1 */
-
-#define  LPTIM_CFGR_CKFLT                       0x00000018U             /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
-#define  LPTIM_CFGR_CKFLT_0                     0x00000008U             /*!< Bit 0 */
-#define  LPTIM_CFGR_CKFLT_1                     0x00000010U             /*!< Bit 1 */
-
-#define  LPTIM_CFGR_TRGFLT                      0x000000C0U             /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
-#define  LPTIM_CFGR_TRGFLT_0                    0x00000040U             /*!< Bit 0 */
-#define  LPTIM_CFGR_TRGFLT_1                    0x00000080U             /*!< Bit 1 */
-
-#define  LPTIM_CFGR_PRESC                       0x00000E00U             /*!< PRESC[2:0] bits (Clock prescaler) */
-#define  LPTIM_CFGR_PRESC_0                     0x00000200U             /*!< Bit 0 */
-#define  LPTIM_CFGR_PRESC_1                     0x00000400U             /*!< Bit 1 */
-#define  LPTIM_CFGR_PRESC_2                     0x00000800U             /*!< Bit 2 */
-
-#define  LPTIM_CFGR_TRIGSEL                     0x0000E000U             /*!< TRIGSEL[2:0]] bits (Trigger selector) */
-#define  LPTIM_CFGR_TRIGSEL_0                   0x00002000U             /*!< Bit 0 */
-#define  LPTIM_CFGR_TRIGSEL_1                   0x00004000U             /*!< Bit 1 */
-#define  LPTIM_CFGR_TRIGSEL_2                   0x00008000U             /*!< Bit 2 */
-
-#define  LPTIM_CFGR_TRIGEN                      0x00060000U             /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
-#define  LPTIM_CFGR_TRIGEN_0                    0x00020000U             /*!< Bit 0 */
-#define  LPTIM_CFGR_TRIGEN_1                    0x00040000U             /*!< Bit 1 */
-
-#define  LPTIM_CFGR_TIMOUT                      0x00080000U             /*!< Timout enable           */
-#define  LPTIM_CFGR_WAVE                        0x00100000U             /*!< Waveform shape          */
-#define  LPTIM_CFGR_WAVPOL                      0x00200000U             /*!< Waveform shape polarity */
-#define  LPTIM_CFGR_PRELOAD                     0x00400000U             /*!< Reg update mode         */
-#define  LPTIM_CFGR_COUNTMODE                   0x00800000U             /*!< Counter mode enable     */     
-#define  LPTIM_CFGR_ENC                         0x01000000U             /*!< Encoder mode enable     */          
-
-/******************  Bit definition for LPTIM_CR register  ********************/
-#define  LPTIM_CR_ENABLE                        0x00000001U             /*!< LPTIMer enable                 */
-#define  LPTIM_CR_SNGSTRT                       0x00000002U             /*!< Timer start in single mode     */
-#define  LPTIM_CR_CNTSTRT                       0x00000004U             /*!< Timer start in continuous mode */
-
-/******************  Bit definition for LPTIM_CMP register  *******************/
-#define  LPTIM_CMP_CMP                          0x0000FFFFU             /*!< Compare register     */
-
-/******************  Bit definition for LPTIM_ARR register  *******************/
-#define  LPTIM_ARR_ARR                          0x0000FFFFU             /*!< Auto reload register */
-
-/******************  Bit definition for LPTIM_CNT register  *******************/
-#define  LPTIM_CNT_CNT                          0x0000FFFFU             /*!< Counter register     */
-
-/******************  Bit definition for LPTIM_OR register  *******************/
-#define  LPTIM_OR_OR                           0x00000003U               /*!< LPTIMER[1:0] bits (Remap selection) */
-#define  LPTIM_OR_OR_0                         0x00000001U               /*!< Bit 0 */
-#define  LPTIM_OR_OR_1                         0x00000002U               /*!< Bit 1 */
-
-/******************************************************************************/
-/*                                                                            */
-/*         Universal Synchronous Asynchronous Receiver Transmitter            */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         0x0001U            /*!<Parity Error                 */
-#define  USART_SR_FE                         0x0002U            /*!<Framing Error                */
-#define  USART_SR_NE                         0x0004U            /*!<Noise Error Flag             */
-#define  USART_SR_ORE                        0x0008U            /*!<OverRun Error                */
-#define  USART_SR_IDLE                       0x0010U            /*!<IDLE line detected           */
-#define  USART_SR_RXNE                       0x0020U            /*!<Read Data Register Not Empty */
-#define  USART_SR_TC                         0x0040U            /*!<Transmission Complete        */
-#define  USART_SR_TXE                        0x0080U            /*!<Transmit Data Register Empty */
-#define  USART_SR_LBD                        0x0100U            /*!<LIN Break Detection Flag     */
-#define  USART_SR_CTS                        0x0200U            /*!<CTS Flag                     */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         0x01FFU            /*!<Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_Fraction              0x000FU            /*!<Fraction of USARTDIV */
-#define  USART_BRR_DIV_Mantissa              0xFFF0U            /*!<Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       0x0001U            /*!<Send Break                             */
-#define  USART_CR1_RWU                       0x0002U            /*!<Receiver wakeup                        */
-#define  USART_CR1_RE                        0x0004U            /*!<Receiver Enable                        */
-#define  USART_CR1_TE                        0x0008U            /*!<Transmitter Enable                     */
-#define  USART_CR1_IDLEIE                    0x0010U            /*!<IDLE Interrupt Enable                  */
-#define  USART_CR1_RXNEIE                    0x0020U            /*!<RXNE Interrupt Enable                  */
-#define  USART_CR1_TCIE                      0x0040U            /*!<Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     0x0080U            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PEIE                      0x0100U            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PS                        0x0200U            /*!<Parity Selection                       */
-#define  USART_CR1_PCE                       0x0400U            /*!<Parity Control Enable                  */
-#define  USART_CR1_WAKE                      0x0800U            /*!<Wakeup method                          */
-#define  USART_CR1_M                         0x1000U            /*!<Word length                            */
-#define  USART_CR1_UE                        0x2000U            /*!<USART Enable                           */
-#define  USART_CR1_OVER8                     0x8000U            /*!<USART Oversampling by 8 enable         */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       0x000FU            /*!<Address of the USART node            */
-#define  USART_CR2_LBDL                      0x0020U            /*!<LIN Break Detection Length           */
-#define  USART_CR2_LBDIE                     0x0040U            /*!<LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      0x0100U            /*!<Last Bit Clock pulse                 */
-#define  USART_CR2_CPHA                      0x0200U            /*!<Clock Phase                          */
-#define  USART_CR2_CPOL                      0x0400U            /*!<Clock Polarity                       */
-#define  USART_CR2_CLKEN                     0x0800U            /*!<Clock Enable                         */
-
-#define  USART_CR2_STOP                      0x3000U            /*!<STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    0x1000U            /*!<Bit 0 */
-#define  USART_CR2_STOP_1                    0x2000U            /*!<Bit 1 */
-
-#define  USART_CR2_LINEN                     0x4000U            /*!<LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       0x0001U            /*!<Error Interrupt Enable      */
-#define  USART_CR3_IREN                      0x0002U            /*!<IrDA mode Enable            */
-#define  USART_CR3_IRLP                      0x0004U            /*!<IrDA Low-Power              */
-#define  USART_CR3_HDSEL                     0x0008U            /*!<Half-Duplex Selection       */
-#define  USART_CR3_NACK                      0x0010U            /*!<Smartcard NACK enable       */
-#define  USART_CR3_SCEN                      0x0020U            /*!<Smartcard mode enable       */
-#define  USART_CR3_DMAR                      0x0040U            /*!<DMA Enable Receiver         */
-#define  USART_CR3_DMAT                      0x0080U            /*!<DMA Enable Transmitter      */
-#define  USART_CR3_RTSE                      0x0100U            /*!<RTS Enable                  */
-#define  USART_CR3_CTSE                      0x0200U            /*!<CTS Enable                  */
-#define  USART_CR3_CTSIE                     0x0400U            /*!<CTS Interrupt Enable        */
-#define  USART_CR3_ONEBIT                    0x0800U            /*!<USART One bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      0x00FFU            /*!<PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    0x0001U            /*!<Bit 0 */
-#define  USART_GTPR_PSC_1                    0x0002U            /*!<Bit 1 */
-#define  USART_GTPR_PSC_2                    0x0004U            /*!<Bit 2 */
-#define  USART_GTPR_PSC_3                    0x0008U            /*!<Bit 3 */
-#define  USART_GTPR_PSC_4                    0x0010U            /*!<Bit 4 */
-#define  USART_GTPR_PSC_5                    0x0020U            /*!<Bit 5 */
-#define  USART_GTPR_PSC_6                    0x0040U            /*!<Bit 6 */
-#define  USART_GTPR_PSC_7                    0x0080U            /*!<Bit 7 */
-
-#define  USART_GTPR_GT                       0xFF00U            /*!<Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Window WATCHDOG                                 */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           0x7FU               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T_0                         0x01U               /*!<Bit 0 */
-#define  WWDG_CR_T_1                         0x02U               /*!<Bit 1 */
-#define  WWDG_CR_T_2                         0x04U               /*!<Bit 2 */
-#define  WWDG_CR_T_3                         0x08U               /*!<Bit 3 */
-#define  WWDG_CR_T_4                         0x10U               /*!<Bit 4 */
-#define  WWDG_CR_T_5                         0x20U               /*!<Bit 5 */
-#define  WWDG_CR_T_6                         0x40U               /*!<Bit 6 */
-/* Legacy defines */
-#define  WWDG_CR_T0                          WWDG_CR_T_0
-#define  WWDG_CR_T1                          WWDG_CR_T_1
-#define  WWDG_CR_T2                          WWDG_CR_T_2
-#define  WWDG_CR_T3                          WWDG_CR_T_3
-#define  WWDG_CR_T4                          WWDG_CR_T_4
-#define  WWDG_CR_T5                          WWDG_CR_T_5
-#define  WWDG_CR_T6                          WWDG_CR_T_6
-
-#define  WWDG_CR_WDGA                        0x80U               /*!<Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          0x007FU            /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W_0                        0x0001U            /*!<Bit 0 */
-#define  WWDG_CFR_W_1                        0x0002U            /*!<Bit 1 */
-#define  WWDG_CFR_W_2                        0x0004U            /*!<Bit 2 */
-#define  WWDG_CFR_W_3                        0x0008U            /*!<Bit 3 */
-#define  WWDG_CFR_W_4                        0x0010U            /*!<Bit 4 */
-#define  WWDG_CFR_W_5                        0x0020U            /*!<Bit 5 */
-#define  WWDG_CFR_W_6                        0x0040U            /*!<Bit 6 */
-/* Legacy defines */
-#define  WWDG_CFR_W0                         WWDG_CFR_W_0
-#define  WWDG_CFR_W1                         WWDG_CFR_W_1
-#define  WWDG_CFR_W2                         WWDG_CFR_W_2
-#define  WWDG_CFR_W3                         WWDG_CFR_W_3
-#define  WWDG_CFR_W4                         WWDG_CFR_W_4
-#define  WWDG_CFR_W5                         WWDG_CFR_W_5
-#define  WWDG_CFR_W6                         WWDG_CFR_W_6
-
-#define  WWDG_CFR_WDGTB                      0x0180U            /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB_0                    0x0080U            /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB_1                    0x0100U            /*!<Bit 1 */
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
-
-#define  WWDG_CFR_EWI                        0x0200U            /*!<Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        0x01U               /*!<Early Wakeup Interrupt Flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Digital to Analog Converter                           */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DAC_CR register  ********************/
-#define  DAC_CR_EN1                          0x00000001U        /*!<DAC channel1 enable */
-#define  DAC_CR_BOFF1                        0x00000002U        /*!<DAC channel1 output buffer disable */
-#define  DAC_CR_TEN1                         0x00000004U        /*!<DAC channel1 Trigger enable */
-
-#define  DAC_CR_TSEL1                        0x00000038U        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define  DAC_CR_TSEL1_0                      0x00000008U        /*!<Bit 0 */
-#define  DAC_CR_TSEL1_1                      0x00000010U        /*!<Bit 1 */
-#define  DAC_CR_TSEL1_2                      0x00000020U        /*!<Bit 2 */
-
-#define  DAC_CR_WAVE1                        0x000000C0U        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE1_0                      0x00000040U        /*!<Bit 0 */
-#define  DAC_CR_WAVE1_1                      0x00000080U        /*!<Bit 1 */
-
-#define  DAC_CR_MAMP1                        0x00000F00U        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP1_0                      0x00000100U        /*!<Bit 0 */
-#define  DAC_CR_MAMP1_1                      0x00000200U        /*!<Bit 1 */
-#define  DAC_CR_MAMP1_2                      0x00000400U        /*!<Bit 2 */
-#define  DAC_CR_MAMP1_3                      0x00000800U        /*!<Bit 3 */
-
-#define  DAC_CR_DMAEN1                       0x00001000U        /*!<DAC channel1 DMA enable */
-#define  DAC_CR_DMAUDRIE1                    0x00002000U        /*!<DAC channel1 DMA underrun interrupt enable*/
-#define  DAC_CR_EN2                          0x00010000U        /*!<DAC channel2 enable */
-#define  DAC_CR_BOFF2                        0x00020000U        /*!<DAC channel2 output buffer disable */
-#define  DAC_CR_TEN2                         0x00040000U        /*!<DAC channel2 Trigger enable */
-
-#define  DAC_CR_TSEL2                        0x00380000U        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define  DAC_CR_TSEL2_0                      0x00080000U        /*!<Bit 0 */
-#define  DAC_CR_TSEL2_1                      0x00100000U        /*!<Bit 1 */
-#define  DAC_CR_TSEL2_2                      0x00200000U        /*!<Bit 2 */
-
-#define  DAC_CR_WAVE2                        0x00C00000U        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE2_0                      0x00400000U        /*!<Bit 0 */
-#define  DAC_CR_WAVE2_1                      0x00800000U        /*!<Bit 1 */
-
-#define  DAC_CR_MAMP2                        0x0F000000U        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP2_0                      0x01000000U        /*!<Bit 0 */
-#define  DAC_CR_MAMP2_1                      0x02000000U        /*!<Bit 1 */
-#define  DAC_CR_MAMP2_2                      0x04000000U        /*!<Bit 2 */
-#define  DAC_CR_MAMP2_3                      0x08000000U        /*!<Bit 3 */
-
-#define  DAC_CR_DMAEN2                       0x10000000U        /*!<DAC channel2 DMA enabled */
-#define  DAC_CR_DMAUDRIE2                    0x20000000U        /*!<DAC channel2 DMA underrun interrupt enable*/
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define  DAC_SWTRIGR_SWTRIG1                 0x01U               /*!<DAC channel1 software trigger */
-#define  DAC_SWTRIGR_SWTRIG2                 0x02U               /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define  DAC_DHR12R1_DACC1DHR                0x0FFFU            /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define  DAC_DHR12L1_DACC1DHR                0xFFF0U            /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define  DAC_DHR8R1_DACC1DHR                 0xFFU               /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define  DAC_DHR12R2_DACC2DHR                0x0FFFU            /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define  DAC_DHR12L2_DACC2DHR                0xFFF0U            /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define  DAC_DHR8R2_DACC2DHR                 0xFFU               /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define  DAC_DHR12RD_DACC1DHR                0x00000FFFU        /*!<DAC channel1 12-bit Right aligned data */
-#define  DAC_DHR12RD_DACC2DHR                0x0FFF0000U        /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define  DAC_DHR12LD_DACC1DHR                0x0000FFF0U        /*!<DAC channel1 12-bit Left aligned data */
-#define  DAC_DHR12LD_DACC2DHR                0xFFF00000U        /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define  DAC_DHR8RD_DACC1DHR                 0x00FFU            /*!<DAC channel1 8-bit Right aligned data */
-#define  DAC_DHR8RD_DACC2DHR                 0xFF00U            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define  DAC_DOR1_DACC1DOR                   0x0FFFU            /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define  DAC_DOR2_DACC2DOR                   0x0FFFU            /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define  DAC_SR_DMAUDR1                      0x00002000U        /*!<DAC channel1 DMA underrun flag */
-#define  DAC_SR_DMAUDR2                      0x20000000U        /*!<DAC channel2 DMA underrun flag */
-/******************************************************************************/
-/*                                                                            */
-/*                                DBG                                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
-#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
-
-/********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
-#define  DBGMCU_CR_DBG_STOP                  0x00000002U
-#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
-#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
-
-#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
-#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U/*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U/*!<Bit 1 */
-
-/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
-
-/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        0x00000001U
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        0x00010000U
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       0x00040000U
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
- 
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
- 
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DAC Instances ********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/******************************** DMA Instances *******************************/
-#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
-                                              ((INSTANCE) == DMA1_Stream1) || \
-                                              ((INSTANCE) == DMA1_Stream2) || \
-                                              ((INSTANCE) == DMA1_Stream3) || \
-                                              ((INSTANCE) == DMA1_Stream4) || \
-                                              ((INSTANCE) == DMA1_Stream5) || \
-                                              ((INSTANCE) == DMA1_Stream6) || \
-                                              ((INSTANCE) == DMA1_Stream7) || \
-                                              ((INSTANCE) == DMA2_Stream0) || \
-                                              ((INSTANCE) == DMA2_Stream1) || \
-                                              ((INSTANCE) == DMA2_Stream2) || \
-                                              ((INSTANCE) == DMA2_Stream3) || \
-                                              ((INSTANCE) == DMA2_Stream4) || \
-                                              ((INSTANCE) == DMA2_Stream5) || \
-                                              ((INSTANCE) == DMA2_Stream6) || \
-                                              ((INSTANCE) == DMA2_Stream7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOH))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2)) 
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI5))
-
-/******************************* LPTIM Instances ******************************/
-#define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
-
-/******************************* RNG Instances ********************************/
-#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI5))
-/*************************** SPI Extended Instances ***************************/
-#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1)    || \
-                                           ((INSTANCE) == SPI2)    || \
-                                           ((INSTANCE) == SPI5))
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
-                                   ((INSTANCE) == TIM5)   || \
-                                   ((INSTANCE) == TIM6)   || \
-                                   ((INSTANCE) == TIM9)   || \
-                                   ((INSTANCE) == TIM11))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM9)  || \
-                                         ((INSTANCE) == TIM11))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM9))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM5))
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM5))
-
-/******************** TIM Instances : Advanced-control timers *****************/
-#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM5))
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM6))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM5))
-
-/************ TIM Instances : DMA requests generation (COMDE) *****************/
-#define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM5)) 
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                             ((INSTANCE) == TIM5))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM6) || \
-                                          ((INSTANCE) == TIM9))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM9))
-
-/********************** TIM Instances : 32 bit Counter ************************/
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM5))
-
-/***************** TIM Instances : external trigger input availabe ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                        ((INSTANCE) == TIM5))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM11))
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM1) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM5) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-/************ TIM Instances : complementary output(s) available ***************/
-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
-   ((((INSTANCE) == TIM1) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3))))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART6))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART6))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART6))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART6))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART6))     
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/***************************** FMPI2C Instances *******************************/
-#define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32F410Rx_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/cmsis/stm32f410tx.h b/stmhal/cmsis/stm32f410tx.h
deleted file mode 100644
index 421d049d04..0000000000
--- a/stmhal/cmsis/stm32f410tx.h
+++ /dev/null
@@ -1,3967 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f410tx.h
-  * @author  MCD Application Team
-  * @version V2.5.1
-  * @date    28-June-2016
-  * @brief   CMSIS STM32F410Tx Device Peripheral Access Layer Header File. 
-  *
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - peripherals registers declarations and bits definition
-  *           - Macros to access peripheral’s registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f410tx
-  * @{
-  */
-    
-#ifndef __STM32F410Tx_H
-#define __STM32F410Tx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-  
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-
-/**
-  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
-  */
-#define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */
-#define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */
-#define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1U       /*!< FPU present                                   */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32F4XX Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-typedef enum
-{
-/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
-  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
-/******  STM32 specific Interrupt Numbers **********************************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
-  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
-  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
-  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
-  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
-  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
-  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
-  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
-  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
-  ADC_IRQn                    = 18,     /*!< ADC1 global Interrupts                                            */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
-  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
-  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                             */
-  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
-  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
-  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global Interrupt and DAC Global Interrupt                    */
-  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
-  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
-  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
-  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
-  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
-  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
-  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
-  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
-  RNG_IRQn                    = 80,     /*!< RNG global Interrupt                                              */
-  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
-  FMPI2C1_EV_IRQn             = 95,     /*!< FMPI2C1 Event Interrupt                                           */
-  FMPI2C1_ER_IRQn             = 96,     /*!< FMPI2C1 Error Interrupt                                           */
-  LPTIM1_IRQn                 = 97      /*!< LPTIM1 interrupt                                                  */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
-#include "system_stm32f4xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */
-  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
-  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
-  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
-  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
-  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
-  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
-  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
-  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
-  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
-  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
-  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
-  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
-  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
-  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
-  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
-                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief CRC calculation unit 
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
-  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */
-  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
-  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
-  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
-  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
-  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
-  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
-  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
-  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
-  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
-  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
-  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
-  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
-  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
-  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
-  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
-  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
-  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
-  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
-  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
-  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
-  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
-  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
-  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
-} DMA_Stream_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
-  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
-  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
-  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
-} DMA_TypeDef;
-
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
-  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
-  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
-  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
-  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
-  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-
-typedef struct
-{
-  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */
-  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */
-  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */
-  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */
-  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */
-  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief General Purpose I/O
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
-  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
-  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
-  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
-  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
-  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
-  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
-  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/** 
-  * @brief System configuration controller
-  */
-  
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-  uint32_t      RESERVED;     /*!< Reserved, 0x18                                                               */
-  uint32_t      CFGR2;        /*!< Reserved, 0x1C                                                               */
-  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
-  uint32_t      RESERVED1[2]; /*!< Reserved, 0x24-0x28                                                          */
-  __IO uint32_t CFGR;         /*!< SYSCFG Configuration register,                     Address offset: 0x2C      */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */
-  __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */
-  __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */
-  __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */
-  __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */
-  __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
-  __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
-  __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
-  __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */
-} I2C_TypeDef;
-
-/**
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< FMPI2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< FMPI2C Control register 2,            Address offset: 0x04 */
-  __IO uint32_t OAR1;        /*!< FMPI2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;        /*!< FMPI2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;     /*!< FMPI2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR;    /*!< FMPI2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;         /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;         /*!< FMPI2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;        /*!< FMPI2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;        /*!< FMPI2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;        /*!< FMPI2C Transmit data register,        Address offset: 0x28 */
-} FMPI2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
-  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
-  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
-  uint32_t      RESERVED0[3];  /*!< Reserved, 0x14-0x1C                                                               */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
-  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
-  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
-  uint32_t      RESERVED2[3];  /*!< Reserved, 0x34-0x3C                                                               */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
-  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
-  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
-  uint32_t      RESERVED4[3];  /*!< Reserved, 0x54-0x5C                                                               */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
-  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
-  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
-  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
-  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
-  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
-  uint32_t      RESERVED7[2];  /*!< Reserved, 0x84-0x88                                                               */
-  __IO uint32_t DCKCFGR;       /*!< RCC Dedicated Clocks configuration register,                 Address offset: 0x8C */
-  __IO uint32_t CKGATENR;       /*!< RCC Clocks Gated ENable Register,                           Address offset: 0x90 */
-  __IO uint32_t DCKCFGR2;      /*!< RCC Dedicated Clocks configuration register 2,               Address offset: 0x94 */
-
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-
-typedef struct
-{
-  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
-  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
-  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
-  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
-  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
-  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
-  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */
-  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
-  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */
-  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
-  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */
-  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */
-  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */
-  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */
-  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
-  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */
-  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
-  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
-  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
-  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
-  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
-  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
-  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
-  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
-  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
-  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
-  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
-  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
-  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
-  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
-  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
-  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
-  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
-  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
-  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
-  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
-  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
-} RTC_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
-  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
-  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
-  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-
-/** 
-  * @brief RNG
-  */
-  
-typedef struct 
-{
-  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
-  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
-  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
-} RNG_TypeDef;
-
-
-/**
-  * @brief LPTIMER
-  */
-typedef struct
-{
-  __IO uint32_t ISR;         /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */
-  __IO uint32_t ICR;         /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */
-  __IO uint32_t IER;         /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */
-  __IO uint32_t CFGR;        /*!< LPTIM Configuration register,                       Address offset: 0x0C */
-  __IO uint32_t CR;          /*!< LPTIM Control register,                             Address offset: 0x10 */
-  __IO uint32_t CMP;         /*!< LPTIM Compare register,                             Address offset: 0x14 */
-  __IO uint32_t ARR;         /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
-  __IO uint32_t CNT;         /*!< LPTIM Counter register,                             Address offset: 0x1C */
-  __IO uint32_t OR;          /*!< LPTIM Option register,                              Address offset: 0x20 */
-} LPTIM_TypeDef;
-
-/** 
-  * @brief Peripheral_memory_map
-  */
-#define FLASH_BASE            0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region                         */
-#define SRAM1_BASE            0x20000000U /*!< SRAM1(32 KB) base address in the alias region                              */
-#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region                                */
-#define SRAM1_BB_BASE         0x22000000U /*!< SRAM1(32 KB) base address in the bit-band region                           */
-#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region                             */
-#define FLASH_END             0x0801FFFFU /*!< FLASH end address */
-
-/* Legacy defines */
-#define SRAM_BASE             SRAM1_BASE
-#define SRAM_BB_BASE          SRAM1_BB_BASE
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
-
-/*!< APB1 peripherals */
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)
-#define LPTIM1_BASE           (APB1PERIPH_BASE + 0x2400U)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)
-#define FMPI2C1_BASE          (APB1PERIPH_BASE + 0x6000U)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)
-/*!< APB2 peripherals */
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000U)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x1000U)
-#define USART6_BASE           (APB2PERIPH_BASE + 0x1400U)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000U)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x2300U)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800U)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00U)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000U)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800U)
-
-/*!< AHB1 peripherals */
-#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000U)
-#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400U)
-#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800U)
-#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00U)
-#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)
-#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800U)
-#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00U)
-#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000U)
-#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010U)
-#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028U)
-#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040U)
-#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058U)
-#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070U)
-#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088U)
-#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0U)
-#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8U)
-#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400U)
-#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010U)
-#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028U)
-#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040U)
-#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058U)
-#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070U)
-#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088U)
-#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0U)
-#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)
-#define RNG_BASE              (PERIPH_BASE + 0x80000U)
-
-/* Debug MCU registers base address */
-#define DBGMCU_BASE           0xE0042000U
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define FMPI2C1             ((FMPI2C_TypeDef *) FMPI2C1_BASE)
-#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define USART6              ((USART_TypeDef *) USART6_BASE)
-#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
-#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
-#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
-#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
-#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
-#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
-#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
-#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
-#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
-#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
-#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
-#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
-#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
-#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
-#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
-#define RNG                 ((RNG_TypeDef *) RNG_BASE)
-
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers_Bits_Definition               */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Analog to Digital Converter                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          0x00000001U       /*!<Analog watchdog flag */
-#define  ADC_SR_EOC                          0x00000002U       /*!<End of conversion */
-#define  ADC_SR_JEOC                         0x00000004U       /*!<Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        0x00000008U       /*!<Injected channel Start flag */
-#define  ADC_SR_STRT                         0x00000010U       /*!<Regular channel Start flag */
-#define  ADC_SR_OVR                          0x00000020U       /*!<Overrun flag */
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
-#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels */
-#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels */
-#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution) */
-#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
-  
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion */
-#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode */
-#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC) */
-#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection */
-#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment */
-#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      0xFFFFU            /*!<Injected data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag */
-#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion */
-#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag */
-#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag */
-#define  ADC_CSR_OVR1                        0x00000020U        /*!<ADC1 DMA overrun  flag */
-#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag */
-#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion */
-#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag */
-#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag */
-#define  ADC_CSR_OVR2                        0x00002000U        /*!<ADC2 DMA overrun  flag */
-#define  ADC_CSR_AWD3                        0x00010000U        /*!<ADC3 Analog watchdog flag */
-#define  ADC_CSR_EOC3                        0x00020000U        /*!<ADC3 End of conversion */
-#define  ADC_CSR_JEOC3                       0x00040000U        /*!<ADC3 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT3                      0x00080000U        /*!<ADC3 Injected channel Start flag */
-#define  ADC_CSR_STRT3                       0x00100000U        /*!<ADC3 Regular channel Start flag */
-#define  ADC_CSR_OVR3                        0x00200000U        /*!<ADC3 DMA overrun  flag */
-
-/* Legacy defines */
-#define  ADC_CSR_DOVR1                        ADC_CSR_OVR1
-#define  ADC_CSR_DOVR2                        ADC_CSR_OVR2
-#define  ADC_CSR_DOVR3                        ADC_CSR_OVR3
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
-#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
-#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
-#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
-#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
-
-/*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                      0x0000FFFFU         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                      0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRC calculation unit                              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           0xFFFFFFFFU /*!< Data register bits */
-
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         0xFFU        /*!< General-purpose 8-bit data register bits */
-
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        0x01U        /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 Debug MCU                                  */
-/*                                                                            */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                             DMA Controller                                 */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DMA_SxCR register  *****************/
-#define DMA_SxCR_CHSEL                       0x0E000000U
-#define DMA_SxCR_CHSEL_0                     0x02000000U
-#define DMA_SxCR_CHSEL_1                     0x04000000U
-#define DMA_SxCR_CHSEL_2                     0x08000000U
-#define DMA_SxCR_MBURST                      0x01800000U
-#define DMA_SxCR_MBURST_0                    0x00800000U
-#define DMA_SxCR_MBURST_1                    0x01000000U
-#define DMA_SxCR_PBURST                      0x00600000U
-#define DMA_SxCR_PBURST_0                    0x00200000U
-#define DMA_SxCR_PBURST_1                    0x00400000U
-#define DMA_SxCR_CT                          0x00080000U
-#define DMA_SxCR_DBM                         0x00040000U
-#define DMA_SxCR_PL                          0x00030000U
-#define DMA_SxCR_PL_0                        0x00010000U
-#define DMA_SxCR_PL_1                        0x00020000U
-#define DMA_SxCR_PINCOS                      0x00008000U
-#define DMA_SxCR_MSIZE                       0x00006000U
-#define DMA_SxCR_MSIZE_0                     0x00002000U
-#define DMA_SxCR_MSIZE_1                     0x00004000U
-#define DMA_SxCR_PSIZE                       0x00001800U
-#define DMA_SxCR_PSIZE_0                     0x00000800U
-#define DMA_SxCR_PSIZE_1                     0x00001000U
-#define DMA_SxCR_MINC                        0x00000400U
-#define DMA_SxCR_PINC                        0x00000200U
-#define DMA_SxCR_CIRC                        0x00000100U
-#define DMA_SxCR_DIR                         0x000000C0U
-#define DMA_SxCR_DIR_0                       0x00000040U
-#define DMA_SxCR_DIR_1                       0x00000080U
-#define DMA_SxCR_PFCTRL                      0x00000020U
-#define DMA_SxCR_TCIE                        0x00000010U
-#define DMA_SxCR_HTIE                        0x00000008U
-#define DMA_SxCR_TEIE                        0x00000004U
-#define DMA_SxCR_DMEIE                       0x00000002U
-#define DMA_SxCR_EN                          0x00000001U
-
-/* Legacy defines */
-#define DMA_SxCR_ACK                         0x00100000U
-
-/********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            0x0000FFFFU
-#define DMA_SxNDT_0                          0x00000001U
-#define DMA_SxNDT_1                          0x00000002U
-#define DMA_SxNDT_2                          0x00000004U
-#define DMA_SxNDT_3                          0x00000008U
-#define DMA_SxNDT_4                          0x00000010U
-#define DMA_SxNDT_5                          0x00000020U
-#define DMA_SxNDT_6                          0x00000040U
-#define DMA_SxNDT_7                          0x00000080U
-#define DMA_SxNDT_8                          0x00000100U
-#define DMA_SxNDT_9                          0x00000200U
-#define DMA_SxNDT_10                         0x00000400U
-#define DMA_SxNDT_11                         0x00000800U
-#define DMA_SxNDT_12                         0x00001000U
-#define DMA_SxNDT_13                         0x00002000U
-#define DMA_SxNDT_14                         0x00004000U
-#define DMA_SxNDT_15                         0x00008000U
-
-/********************  Bits definition for DMA_SxFCR register  ****************/ 
-#define DMA_SxFCR_FEIE                       0x00000080U
-#define DMA_SxFCR_FS                         0x00000038U
-#define DMA_SxFCR_FS_0                       0x00000008U
-#define DMA_SxFCR_FS_1                       0x00000010U
-#define DMA_SxFCR_FS_2                       0x00000020U
-#define DMA_SxFCR_DMDIS                      0x00000004U
-#define DMA_SxFCR_FTH                        0x00000003U
-#define DMA_SxFCR_FTH_0                      0x00000001U
-#define DMA_SxFCR_FTH_1                      0x00000002U
-
-/********************  Bits definition for DMA_LISR register  *****************/ 
-#define DMA_LISR_TCIF3                       0x08000000U
-#define DMA_LISR_HTIF3                       0x04000000U
-#define DMA_LISR_TEIF3                       0x02000000U
-#define DMA_LISR_DMEIF3                      0x01000000U
-#define DMA_LISR_FEIF3                       0x00400000U
-#define DMA_LISR_TCIF2                       0x00200000U
-#define DMA_LISR_HTIF2                       0x00100000U
-#define DMA_LISR_TEIF2                       0x00080000U
-#define DMA_LISR_DMEIF2                      0x00040000U
-#define DMA_LISR_FEIF2                       0x00010000U
-#define DMA_LISR_TCIF1                       0x00000800U
-#define DMA_LISR_HTIF1                       0x00000400U
-#define DMA_LISR_TEIF1                       0x00000200U
-#define DMA_LISR_DMEIF1                      0x00000100U
-#define DMA_LISR_FEIF1                       0x00000040U
-#define DMA_LISR_TCIF0                       0x00000020U
-#define DMA_LISR_HTIF0                       0x00000010U
-#define DMA_LISR_TEIF0                       0x00000008U
-#define DMA_LISR_DMEIF0                      0x00000004U
-#define DMA_LISR_FEIF0                       0x00000001U
-
-/********************  Bits definition for DMA_HISR register  *****************/ 
-#define DMA_HISR_TCIF7                       0x08000000U
-#define DMA_HISR_HTIF7                       0x04000000U
-#define DMA_HISR_TEIF7                       0x02000000U
-#define DMA_HISR_DMEIF7                      0x01000000U
-#define DMA_HISR_FEIF7                       0x00400000U
-#define DMA_HISR_TCIF6                       0x00200000U
-#define DMA_HISR_HTIF6                       0x00100000U
-#define DMA_HISR_TEIF6                       0x00080000U
-#define DMA_HISR_DMEIF6                      0x00040000U
-#define DMA_HISR_FEIF6                       0x00010000U
-#define DMA_HISR_TCIF5                       0x00000800U
-#define DMA_HISR_HTIF5                       0x00000400U
-#define DMA_HISR_TEIF5                       0x00000200U
-#define DMA_HISR_DMEIF5                      0x00000100U
-#define DMA_HISR_FEIF5                       0x00000040U
-#define DMA_HISR_TCIF4                       0x00000020U
-#define DMA_HISR_HTIF4                       0x00000010U
-#define DMA_HISR_TEIF4                       0x00000008U
-#define DMA_HISR_DMEIF4                      0x00000004U
-#define DMA_HISR_FEIF4                       0x00000001U
-
-/********************  Bits definition for DMA_LIFCR register  ****************/ 
-#define DMA_LIFCR_CTCIF3                     0x08000000U
-#define DMA_LIFCR_CHTIF3                     0x04000000U
-#define DMA_LIFCR_CTEIF3                     0x02000000U
-#define DMA_LIFCR_CDMEIF3                    0x01000000U
-#define DMA_LIFCR_CFEIF3                     0x00400000U
-#define DMA_LIFCR_CTCIF2                     0x00200000U
-#define DMA_LIFCR_CHTIF2                     0x00100000U
-#define DMA_LIFCR_CTEIF2                     0x00080000U
-#define DMA_LIFCR_CDMEIF2                    0x00040000U
-#define DMA_LIFCR_CFEIF2                     0x00010000U
-#define DMA_LIFCR_CTCIF1                     0x00000800U
-#define DMA_LIFCR_CHTIF1                     0x00000400U
-#define DMA_LIFCR_CTEIF1                     0x00000200U
-#define DMA_LIFCR_CDMEIF1                    0x00000100U
-#define DMA_LIFCR_CFEIF1                     0x00000040U
-#define DMA_LIFCR_CTCIF0                     0x00000020U
-#define DMA_LIFCR_CHTIF0                     0x00000010U
-#define DMA_LIFCR_CTEIF0                     0x00000008U
-#define DMA_LIFCR_CDMEIF0                    0x00000004U
-#define DMA_LIFCR_CFEIF0                     0x00000001U
-
-/********************  Bits definition for DMA_HIFCR  register  ****************/ 
-#define DMA_HIFCR_CTCIF7                     0x08000000U
-#define DMA_HIFCR_CHTIF7                     0x04000000U
-#define DMA_HIFCR_CTEIF7                     0x02000000U
-#define DMA_HIFCR_CDMEIF7                    0x01000000U
-#define DMA_HIFCR_CFEIF7                     0x00400000U
-#define DMA_HIFCR_CTCIF6                     0x00200000U
-#define DMA_HIFCR_CHTIF6                     0x00100000U
-#define DMA_HIFCR_CTEIF6                     0x00080000U
-#define DMA_HIFCR_CDMEIF6                    0x00040000U
-#define DMA_HIFCR_CFEIF6                     0x00010000U
-#define DMA_HIFCR_CTCIF5                     0x00000800U
-#define DMA_HIFCR_CHTIF5                     0x00000400U
-#define DMA_HIFCR_CTEIF5                     0x00000200U
-#define DMA_HIFCR_CDMEIF5                    0x00000100U
-#define DMA_HIFCR_CFEIF5                     0x00000040U
-#define DMA_HIFCR_CTCIF4                     0x00000020U
-#define DMA_HIFCR_CHTIF4                     0x00000010U
-#define DMA_HIFCR_CTEIF4                     0x00000008U
-#define DMA_HIFCR_CDMEIF4                    0x00000004U
-#define DMA_HIFCR_CFEIF4                     0x00000001U
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                    External Interrupt/Event Controller                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
-#define  EXTI_IMR_MR23                       0x00800000U        /*!< Interrupt Mask on line 23 */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
-#define  EXTI_EMR_MR23                       0x00800000U        /*!< Event Mask on line 23 */
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
-#define  EXTI_RTSR_TR23                      0x00800000U        /*!< Rising trigger event configuration bit of line 23 */
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
-#define  EXTI_FTSR_TR23                      0x00800000U        /*!< Falling trigger event configuration bit of line 23 */
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
-#define  EXTI_SWIER_SWIER23                  0x00800000U        /*!< Software Interrupt on line 23 */
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
-#define  EXTI_PR_PR23                        0x00800000U        /*!< Pending bit for line 23 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    FLASH                                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    0x0000000FU
-#define FLASH_ACR_LATENCY_0WS                0x00000000U
-#define FLASH_ACR_LATENCY_1WS                0x00000001U
-#define FLASH_ACR_LATENCY_2WS                0x00000002U
-#define FLASH_ACR_LATENCY_3WS                0x00000003U
-#define FLASH_ACR_LATENCY_4WS                0x00000004U
-#define FLASH_ACR_LATENCY_5WS                0x00000005U
-#define FLASH_ACR_LATENCY_6WS                0x00000006U
-#define FLASH_ACR_LATENCY_7WS                0x00000007U
-
-#define FLASH_ACR_PRFTEN                     0x00000100U
-#define FLASH_ACR_ICEN                       0x00000200U
-#define FLASH_ACR_DCEN                       0x00000400U
-#define FLASH_ACR_ICRST                      0x00000800U
-#define FLASH_ACR_DCRST                      0x00001000U
-#define FLASH_ACR_BYTE0_ADDRESS              0x40023C00U
-#define FLASH_ACR_BYTE2_ADDRESS              0x40023C03U
-
-/*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         0x00000001U
-#define FLASH_SR_SOP                         0x00000002U
-#define FLASH_SR_WRPERR                      0x00000010U
-#define FLASH_SR_PGAERR                      0x00000020U
-#define FLASH_SR_PGPERR                      0x00000040U
-#define FLASH_SR_PGSERR                      0x00000080U
-#define FLASH_SR_BSY                         0x00010000U
-
-/*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          0x00000001U
-#define FLASH_CR_SER                         0x00000002U
-#define FLASH_CR_MER                         0x00000004U
-#define FLASH_CR_SNB                         0x000000F8U
-#define FLASH_CR_SNB_0                       0x00000008U
-#define FLASH_CR_SNB_1                       0x00000010U
-#define FLASH_CR_SNB_2                       0x00000020U
-#define FLASH_CR_SNB_3                       0x00000040U
-#define FLASH_CR_SNB_4                       0x00000080U
-#define FLASH_CR_PSIZE                       0x00000300U
-#define FLASH_CR_PSIZE_0                     0x00000100U
-#define FLASH_CR_PSIZE_1                     0x00000200U
-#define FLASH_CR_STRT                        0x00010000U
-#define FLASH_CR_EOPIE                       0x01000000U
-#define FLASH_CR_LOCK                        0x80000000U
-
-/*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                 0x00000001U
-#define FLASH_OPTCR_OPTSTRT                 0x00000002U
-#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
-#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
-#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
-
-#define FLASH_OPTCR_WDG_SW                  0x00000020U
-#define FLASH_OPTCR_nRST_STOP               0x00000040U
-#define FLASH_OPTCR_nRST_STDBY              0x00000080U
-#define FLASH_OPTCR_RDP                     0x0000FF00U
-#define FLASH_OPTCR_RDP_0                   0x00000100U
-#define FLASH_OPTCR_RDP_1                   0x00000200U
-#define FLASH_OPTCR_RDP_2                   0x00000400U
-#define FLASH_OPTCR_RDP_3                   0x00000800U
-#define FLASH_OPTCR_RDP_4                   0x00001000U
-#define FLASH_OPTCR_RDP_5                   0x00002000U
-#define FLASH_OPTCR_RDP_6                   0x00004000U
-#define FLASH_OPTCR_RDP_7                   0x00008000U
-#define FLASH_OPTCR_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR_nWRP_0                  0x00010000U
-#define FLASH_OPTCR_nWRP_1                  0x00020000U
-#define FLASH_OPTCR_nWRP_2                  0x00040000U
-#define FLASH_OPTCR_nWRP_3                  0x00080000U
-#define FLASH_OPTCR_nWRP_4                  0x00100000U
-#define FLASH_OPTCR_nWRP_5                  0x00200000U
-#define FLASH_OPTCR_nWRP_6                  0x00400000U
-#define FLASH_OPTCR_nWRP_7                  0x00800000U
-#define FLASH_OPTCR_nWRP_8                  0x01000000U
-#define FLASH_OPTCR_nWRP_9                  0x02000000U
-#define FLASH_OPTCR_nWRP_10                 0x04000000U
-#define FLASH_OPTCR_nWRP_11                 0x08000000U
-                                             
-/******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR1_nWRP_0                  0x00010000U
-#define FLASH_OPTCR1_nWRP_1                  0x00020000U
-#define FLASH_OPTCR1_nWRP_2                  0x00040000U
-#define FLASH_OPTCR1_nWRP_3                  0x00080000U
-#define FLASH_OPTCR1_nWRP_4                  0x00100000U
-#define FLASH_OPTCR1_nWRP_5                  0x00200000U
-#define FLASH_OPTCR1_nWRP_6                  0x00400000U
-#define FLASH_OPTCR1_nWRP_7                  0x00800000U
-#define FLASH_OPTCR1_nWRP_8                  0x01000000U
-#define FLASH_OPTCR1_nWRP_9                  0x02000000U
-#define FLASH_OPTCR1_nWRP_10                 0x04000000U
-#define FLASH_OPTCR1_nWRP_11                 0x08000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    0x00000003U
-#define GPIO_MODER_MODER0_0                  0x00000001U
-#define GPIO_MODER_MODER0_1                  0x00000002U
-
-#define GPIO_MODER_MODER1                    0x0000000CU
-#define GPIO_MODER_MODER1_0                  0x00000004U
-#define GPIO_MODER_MODER1_1                  0x00000008U
-
-#define GPIO_MODER_MODER2                    0x00000030U
-#define GPIO_MODER_MODER2_0                  0x00000010U
-#define GPIO_MODER_MODER2_1                  0x00000020U
-
-#define GPIO_MODER_MODER3                    0x000000C0U
-#define GPIO_MODER_MODER3_0                  0x00000040U
-#define GPIO_MODER_MODER3_1                  0x00000080U
-
-#define GPIO_MODER_MODER4                    0x00000300U
-#define GPIO_MODER_MODER4_0                  0x00000100U
-#define GPIO_MODER_MODER4_1                  0x00000200U
-
-#define GPIO_MODER_MODER5                    0x00000C00U
-#define GPIO_MODER_MODER5_0                  0x00000400U
-#define GPIO_MODER_MODER5_1                  0x00000800U
-
-#define GPIO_MODER_MODER6                    0x00003000U
-#define GPIO_MODER_MODER6_0                  0x00001000U
-#define GPIO_MODER_MODER6_1                  0x00002000U
-
-#define GPIO_MODER_MODER7                    0x0000C000U
-#define GPIO_MODER_MODER7_0                  0x00004000U
-#define GPIO_MODER_MODER7_1                  0x00008000U
-
-#define GPIO_MODER_MODER8                    0x00030000U
-#define GPIO_MODER_MODER8_0                  0x00010000U
-#define GPIO_MODER_MODER8_1                  0x00020000U
-
-#define GPIO_MODER_MODER9                    0x000C0000U
-#define GPIO_MODER_MODER9_0                  0x00040000U
-#define GPIO_MODER_MODER9_1                  0x00080000U
-
-#define GPIO_MODER_MODER10                   0x00300000U
-#define GPIO_MODER_MODER10_0                 0x00100000U
-#define GPIO_MODER_MODER10_1                 0x00200000U
-
-#define GPIO_MODER_MODER11                   0x00C00000U
-#define GPIO_MODER_MODER11_0                 0x00400000U
-#define GPIO_MODER_MODER11_1                 0x00800000U
-
-#define GPIO_MODER_MODER12                   0x03000000U
-#define GPIO_MODER_MODER12_0                 0x01000000U
-#define GPIO_MODER_MODER12_1                 0x02000000U
-
-#define GPIO_MODER_MODER13                   0x0C000000U
-#define GPIO_MODER_MODER13_0                 0x04000000U
-#define GPIO_MODER_MODER13_1                 0x08000000U
-
-#define GPIO_MODER_MODER14                   0x30000000U
-#define GPIO_MODER_MODER14_0                 0x10000000U
-#define GPIO_MODER_MODER14_1                 0x20000000U
-
-#define GPIO_MODER_MODER15                   0xC0000000U
-#define GPIO_MODER_MODER15_0                 0x40000000U
-#define GPIO_MODER_MODER15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     0x00000001U
-#define GPIO_OTYPER_OT_1                     0x00000002U
-#define GPIO_OTYPER_OT_2                     0x00000004U
-#define GPIO_OTYPER_OT_3                     0x00000008U
-#define GPIO_OTYPER_OT_4                     0x00000010U
-#define GPIO_OTYPER_OT_5                     0x00000020U
-#define GPIO_OTYPER_OT_6                     0x00000040U
-#define GPIO_OTYPER_OT_7                     0x00000080U
-#define GPIO_OTYPER_OT_8                     0x00000100U
-#define GPIO_OTYPER_OT_9                     0x00000200U
-#define GPIO_OTYPER_OT_10                    0x00000400U
-#define GPIO_OTYPER_OT_11                    0x00000800U
-#define GPIO_OTYPER_OT_12                    0x00001000U
-#define GPIO_OTYPER_OT_13                    0x00002000U
-#define GPIO_OTYPER_OT_14                    0x00004000U
-#define GPIO_OTYPER_OT_15                    0x00008000U
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
-#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
-#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
-
-#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
-#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
-#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
-
-#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
-#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
-#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
-
-#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
-#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
-#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
-
-#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
-#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
-#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
-
-#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
-#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
-#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
-
-#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
-#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
-#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
-
-#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
-#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
-#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
-
-#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
-#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
-#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
-
-#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
-#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
-#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
-
-#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
-#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
-#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
-
-#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
-#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
-#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
-
-#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
-#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
-#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
-
-#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
-#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
-#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
-
-#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
-#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
-#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
-
-#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
-#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
-#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    0x00000003U
-#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
-#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
-
-#define GPIO_PUPDR_PUPDR1                    0x0000000CU
-#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
-#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
-
-#define GPIO_PUPDR_PUPDR2                    0x00000030U
-#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
-#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
-
-#define GPIO_PUPDR_PUPDR3                    0x000000C0U
-#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
-#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
-
-#define GPIO_PUPDR_PUPDR4                    0x00000300U
-#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
-#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
-
-#define GPIO_PUPDR_PUPDR5                    0x00000C00U
-#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
-#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
-
-#define GPIO_PUPDR_PUPDR6                    0x00003000U
-#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
-#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
-
-#define GPIO_PUPDR_PUPDR7                    0x0000C000U
-#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
-#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
-
-#define GPIO_PUPDR_PUPDR8                    0x00030000U
-#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
-#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
-
-#define GPIO_PUPDR_PUPDR9                    0x000C0000U
-#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
-#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
-
-#define GPIO_PUPDR_PUPDR10                   0x00300000U
-#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
-#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
-
-#define GPIO_PUPDR_PUPDR11                   0x00C00000U
-#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
-#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
-
-#define GPIO_PUPDR_PUPDR12                   0x03000000U
-#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
-#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
-
-#define GPIO_PUPDR_PUPDR13                   0x0C000000U
-#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
-#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
-
-#define GPIO_PUPDR_PUPDR14                   0x30000000U
-#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
-#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
-
-#define GPIO_PUPDR_PUPDR15                   0xC0000000U
-#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
-#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       0x00000001U
-#define GPIO_IDR_IDR_1                       0x00000002U
-#define GPIO_IDR_IDR_2                       0x00000004U
-#define GPIO_IDR_IDR_3                       0x00000008U
-#define GPIO_IDR_IDR_4                       0x00000010U
-#define GPIO_IDR_IDR_5                       0x00000020U
-#define GPIO_IDR_IDR_6                       0x00000040U
-#define GPIO_IDR_IDR_7                       0x00000080U
-#define GPIO_IDR_IDR_8                       0x00000100U
-#define GPIO_IDR_IDR_9                       0x00000200U
-#define GPIO_IDR_IDR_10                      0x00000400U
-#define GPIO_IDR_IDR_11                      0x00000800U
-#define GPIO_IDR_IDR_12                      0x00001000U
-#define GPIO_IDR_IDR_13                      0x00002000U
-#define GPIO_IDR_IDR_14                      0x00004000U
-#define GPIO_IDR_IDR_15                      0x00008000U
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       0x00000001U
-#define GPIO_ODR_ODR_1                       0x00000002U
-#define GPIO_ODR_ODR_2                       0x00000004U
-#define GPIO_ODR_ODR_3                       0x00000008U
-#define GPIO_ODR_ODR_4                       0x00000010U
-#define GPIO_ODR_ODR_5                       0x00000020U
-#define GPIO_ODR_ODR_6                       0x00000040U
-#define GPIO_ODR_ODR_7                       0x00000080U
-#define GPIO_ODR_ODR_8                       0x00000100U
-#define GPIO_ODR_ODR_9                       0x00000200U
-#define GPIO_ODR_ODR_10                      0x00000400U
-#define GPIO_ODR_ODR_11                      0x00000800U
-#define GPIO_ODR_ODR_12                      0x00001000U
-#define GPIO_ODR_ODR_13                      0x00002000U
-#define GPIO_ODR_ODR_14                      0x00004000U
-#define GPIO_ODR_ODR_15                      0x00008000U
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       0x00000001U
-#define GPIO_BSRR_BS_1                       0x00000002U
-#define GPIO_BSRR_BS_2                       0x00000004U
-#define GPIO_BSRR_BS_3                       0x00000008U
-#define GPIO_BSRR_BS_4                       0x00000010U
-#define GPIO_BSRR_BS_5                       0x00000020U
-#define GPIO_BSRR_BS_6                       0x00000040U
-#define GPIO_BSRR_BS_7                       0x00000080U
-#define GPIO_BSRR_BS_8                       0x00000100U
-#define GPIO_BSRR_BS_9                       0x00000200U
-#define GPIO_BSRR_BS_10                      0x00000400U
-#define GPIO_BSRR_BS_11                      0x00000800U
-#define GPIO_BSRR_BS_12                      0x00001000U
-#define GPIO_BSRR_BS_13                      0x00002000U
-#define GPIO_BSRR_BS_14                      0x00004000U
-#define GPIO_BSRR_BS_15                      0x00008000U
-#define GPIO_BSRR_BR_0                       0x00010000U
-#define GPIO_BSRR_BR_1                       0x00020000U
-#define GPIO_BSRR_BR_2                       0x00040000U
-#define GPIO_BSRR_BR_3                       0x00080000U
-#define GPIO_BSRR_BR_4                       0x00100000U
-#define GPIO_BSRR_BR_5                       0x00200000U
-#define GPIO_BSRR_BR_6                       0x00400000U
-#define GPIO_BSRR_BR_7                       0x00800000U
-#define GPIO_BSRR_BR_8                       0x01000000U
-#define GPIO_BSRR_BR_9                       0x02000000U
-#define GPIO_BSRR_BR_10                      0x04000000U
-#define GPIO_BSRR_BR_11                      0x08000000U
-#define GPIO_BSRR_BR_12                      0x10000000U
-#define GPIO_BSRR_BR_13                      0x20000000U
-#define GPIO_BSRR_BR_14                      0x40000000U
-#define GPIO_BSRR_BR_15                      0x80000000U
-
-/****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0                       0x00000001U
-#define GPIO_LCKR_LCK1                       0x00000002U
-#define GPIO_LCKR_LCK2                       0x00000004U
-#define GPIO_LCKR_LCK3                       0x00000008U
-#define GPIO_LCKR_LCK4                       0x00000010U
-#define GPIO_LCKR_LCK5                       0x00000020U
-#define GPIO_LCKR_LCK6                       0x00000040U
-#define GPIO_LCKR_LCK7                       0x00000080U
-#define GPIO_LCKR_LCK8                       0x00000100U
-#define GPIO_LCKR_LCK9                       0x00000200U
-#define GPIO_LCKR_LCK10                      0x00000400U
-#define GPIO_LCKR_LCK11                      0x00000800U
-#define GPIO_LCKR_LCK12                      0x00001000U
-#define GPIO_LCKR_LCK13                      0x00002000U
-#define GPIO_LCKR_LCK14                      0x00004000U
-#define GPIO_LCKR_LCK15                      0x00008000U
-#define GPIO_LCKR_LCKK                       0x00010000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Inter-integrated Circuit Interface                    */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          0x00000001U     /*!<Peripheral Enable                             */
-#define  I2C_CR1_SMBUS                       0x00000002U     /*!<SMBus Mode                                    */
-#define  I2C_CR1_SMBTYPE                     0x00000008U     /*!<SMBus Type                                    */
-#define  I2C_CR1_ENARP                       0x00000010U     /*!<ARP Enable                                    */
-#define  I2C_CR1_ENPEC                       0x00000020U     /*!<PEC Enable                                    */
-#define  I2C_CR1_ENGC                        0x00000040U     /*!<General Call Enable                           */
-#define  I2C_CR1_NOSTRETCH                   0x00000080U     /*!<Clock Stretching Disable (Slave mode)  */
-#define  I2C_CR1_START                       0x00000100U     /*!<Start Generation                              */
-#define  I2C_CR1_STOP                        0x00000200U     /*!<Stop Generation                               */
-#define  I2C_CR1_ACK                         0x00000400U     /*!<Acknowledge Enable                            */
-#define  I2C_CR1_POS                         0x00000800U     /*!<Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         0x00001000U     /*!<Packet Error Checking                         */
-#define  I2C_CR1_ALERT                       0x00002000U     /*!<SMBus Alert                                   */
-#define  I2C_CR1_SWRST                       0x00008000U     /*!<Software Reset                                */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        0x0000003FU     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
-#define  I2C_CR2_FREQ_0                      0x00000001U     /*!<Bit 0 */
-#define  I2C_CR2_FREQ_1                      0x00000002U     /*!<Bit 1 */
-#define  I2C_CR2_FREQ_2                      0x00000004U     /*!<Bit 2 */
-#define  I2C_CR2_FREQ_3                      0x00000008U     /*!<Bit 3 */
-#define  I2C_CR2_FREQ_4                      0x00000010U     /*!<Bit 4 */
-#define  I2C_CR2_FREQ_5                      0x00000020U     /*!<Bit 5 */
-
-#define  I2C_CR2_ITERREN                     0x00000100U     /*!<Error Interrupt Enable  */
-#define  I2C_CR2_ITEVTEN                     0x00000200U     /*!<Event Interrupt Enable  */
-#define  I2C_CR2_ITBUFEN                     0x00000400U     /*!<Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       0x00000800U     /*!<DMA Requests Enable     */
-#define  I2C_CR2_LAST                        0x00001000U     /*!<DMA Last Transfer       */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     0x000000FEU     /*!<Interface Address */
-#define  I2C_OAR1_ADD8_9                     0x00000300U     /*!<Interface Address */
-
-#define  I2C_OAR1_ADD0                       0x00000001U     /*!<Bit 0 */
-#define  I2C_OAR1_ADD1                       0x00000002U     /*!<Bit 1 */
-#define  I2C_OAR1_ADD2                       0x00000004U     /*!<Bit 2 */
-#define  I2C_OAR1_ADD3                       0x00000008U     /*!<Bit 3 */
-#define  I2C_OAR1_ADD4                       0x00000010U     /*!<Bit 4 */
-#define  I2C_OAR1_ADD5                       0x00000020U     /*!<Bit 5 */
-#define  I2C_OAR1_ADD6                       0x00000040U     /*!<Bit 6 */
-#define  I2C_OAR1_ADD7                       0x00000080U     /*!<Bit 7 */
-#define  I2C_OAR1_ADD8                       0x00000100U     /*!<Bit 8 */
-#define  I2C_OAR1_ADD9                       0x00000200U     /*!<Bit 9 */
-
-#define  I2C_OAR1_ADDMODE                    0x00008000U     /*!<Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     0x00000001U        /*!<Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       0x000000FEU        /*!<Interface address           */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           0x000000FFU        /*!<8-bit Data Register         */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          0x00000001U     /*!<Start Bit (Master mode)                  */
-#define  I2C_SR1_ADDR                        0x00000002U     /*!<Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         0x00000004U     /*!<Byte Transfer Finished                          */
-#define  I2C_SR1_ADD10                       0x00000008U     /*!<10-bit header sent (Master mode)         */
-#define  I2C_SR1_STOPF                       0x00000010U     /*!<Stop detection (Slave mode)              */
-#define  I2C_SR1_RXNE                        0x00000040U     /*!<Data Register not Empty (receivers)      */
-#define  I2C_SR1_TXE                         0x00000080U     /*!<Data Register Empty (transmitters)       */
-#define  I2C_SR1_BERR                        0x00000100U     /*!<Bus Error                                       */
-#define  I2C_SR1_ARLO                        0x00000200U     /*!<Arbitration Lost (master mode)           */
-#define  I2C_SR1_AF                          0x00000400U     /*!<Acknowledge Failure                             */
-#define  I2C_SR1_OVR                         0x00000800U     /*!<Overrun/Underrun                                */
-#define  I2C_SR1_PECERR                      0x00001000U     /*!<PEC Error in reception                          */
-#define  I2C_SR1_TIMEOUT                     0x00004000U     /*!<Timeout or Tlow Error                           */
-#define  I2C_SR1_SMBALERT                    0x00008000U     /*!<SMBus Alert                                     */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         0x00000001U     /*!<Master/Slave                              */
-#define  I2C_SR2_BUSY                        0x00000002U     /*!<Bus Busy                                  */
-#define  I2C_SR2_TRA                         0x00000004U     /*!<Transmitter/Receiver                      */
-#define  I2C_SR2_GENCALL                     0x00000010U     /*!<General Call Address (Slave mode)  */
-#define  I2C_SR2_SMBDEFAULT                  0x00000020U     /*!<SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     0x00000040U     /*!<SMBus Host Header (Slave mode)     */
-#define  I2C_SR2_DUALF                       0x00000080U     /*!<Dual Flag (Slave mode)             */
-#define  I2C_SR2_PEC                         0x0000FF00U     /*!<Packet Error Checking Register            */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         0x00000FFFU     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        0x00004000U     /*!<Fast Mode Duty Cycle                                       */
-#define  I2C_CCR_FS                          0x00008000U     /*!<I2C Master Mode Selection                                  */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     0x0000003FU     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************  Bit definition for I2C_FLTR register  *******************/
-#define  I2C_FLTR_DNF                        0x0000000FU     /*!<Digital Noise Filter */
-#define  I2C_FLTR_ANOFF                      0x00000010U     /*!<Analog Noise Filter OFF */
-
-/******************************************************************************/
-/*                                                                            */
-/*        Fast Mode Plus Inter-integrated Circuit Interface (I2C)             */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define  FMPI2C_CR1_PE                        0x00000001U        /*!< Peripheral enable                   */
-#define  FMPI2C_CR1_TXIE                      0x00000002U        /*!< TX interrupt enable                 */
-#define  FMPI2C_CR1_RXIE                      0x00000004U        /*!< RX interrupt enable                 */
-#define  FMPI2C_CR1_ADDRIE                    0x00000008U        /*!< Address match interrupt enable      */
-#define  FMPI2C_CR1_NACKIE                    0x00000010U        /*!< NACK received interrupt enable      */
-#define  FMPI2C_CR1_STOPIE                    0x00000020U        /*!< STOP detection interrupt enable     */
-#define  FMPI2C_CR1_TCIE                      0x00000040U        /*!< Transfer complete interrupt enable  */
-#define  FMPI2C_CR1_ERRIE                     0x00000080U        /*!< Errors interrupt enable             */
-#define  FMPI2C_CR1_DFN                       0x00000F00U        /*!< Digital noise filter                */
-#define  FMPI2C_CR1_ANFOFF                    0x00001000U        /*!< Analog noise filter OFF             */
-#define  FMPI2C_CR1_TXDMAEN                   0x00004000U        /*!< DMA transmission requests enable    */
-#define  FMPI2C_CR1_RXDMAEN                   0x00008000U        /*!< DMA reception requests enable       */
-#define  FMPI2C_CR1_SBC                       0x00010000U        /*!< Slave byte control                  */
-#define  FMPI2C_CR1_NOSTRETCH                 0x00020000U        /*!< Clock stretching disable            */
-#define  FMPI2C_CR1_GCEN                      0x00080000U        /*!< General call enable                 */
-#define  FMPI2C_CR1_ALERTEN                   0x00400000U        /*!< SMBus alert enable                  */
-#define  FMPI2C_CR1_PECEN                     0x00800000U        /*!< PEC enable                          */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define  FMPI2C_CR2_SADD                      0x000003FFU        /*!< Slave address (master mode)                             */
-#define  FMPI2C_CR2_RD_WRN                    0x00000400U        /*!< Transfer direction (master mode)                        */
-#define  FMPI2C_CR2_ADD10                     0x00000800U        /*!< 10-bit addressing mode (master mode)                    */
-#define  FMPI2C_CR2_HEAD10R                   0x00001000U        /*!< 10-bit address header only read direction (master mode) */
-#define  FMPI2C_CR2_START                     0x00002000U        /*!< START generation                                        */
-#define  FMPI2C_CR2_STOP                      0x00004000U        /*!< STOP generation (master mode)                           */
-#define  FMPI2C_CR2_NACK                      0x00008000U        /*!< NACK generation (slave mode)                            */
-#define  FMPI2C_CR2_NBYTES                    0x00FF0000U        /*!< Number of bytes                                         */
-#define  FMPI2C_CR2_RELOAD                    0x01000000U        /*!< NBYTES reload mode                                      */
-#define  FMPI2C_CR2_AUTOEND                   0x02000000U        /*!< Automatic end mode (master mode)                        */
-#define  FMPI2C_CR2_PECBYTE                   0x04000000U        /*!< Packet error checking byte                              */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define  FMPI2C_OAR1_OA1                      0x000003FFU        /*!< Interface own address 1   */
-#define  FMPI2C_OAR1_OA1MODE                  0x00000400U        /*!< Own address 1 10-bit mode */
-#define  FMPI2C_OAR1_OA1EN                    0x00008000U        /*!< Own address 1 enable      */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define  FMPI2C_OAR2_OA2                      0x000000FEU        /*!< Interface own address 2 */
-#define  FMPI2C_OAR2_OA2MSK                   0x00000700U        /*!< Own address 2 masks     */
-#define  FMPI2C_OAR2_OA2EN                    0x00008000U        /*!< Own address 2 enable    */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define  FMPI2C_TIMINGR_SCLL                  0x000000FFU        /*!< SCL low period (master mode)  */
-#define  FMPI2C_TIMINGR_SCLH                  0x0000FF00U        /*!< SCL high period (master mode) */
-#define  FMPI2C_TIMINGR_SDADEL                0x000F0000U        /*!< Data hold time                */
-#define  FMPI2C_TIMINGR_SCLDEL                0x00F00000U        /*!< Data setup time               */
-#define  FMPI2C_TIMINGR_PRESC                 0xF0000000U        /*!< Timings prescaler             */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define  FMPI2C_TIMEOUTR_TIMEOUTA             0x00000FFFU        /*!< Bus timeout A                 */
-#define  FMPI2C_TIMEOUTR_TIDLE                0x00001000U        /*!< Idle clock timeout detection  */
-#define  FMPI2C_TIMEOUTR_TIMOUTEN             0x00008000U        /*!< Clock timeout enable          */
-#define  FMPI2C_TIMEOUTR_TIMEOUTB             0x0FFF0000U        /*!< Bus timeout B                 */
-#define  FMPI2C_TIMEOUTR_TEXTEN               0x80000000U        /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define  FMPI2C_ISR_TXE                       0x00000001U        /*!< Transmit data register empty     */
-#define  FMPI2C_ISR_TXIS                      0x00000002U        /*!< Transmit interrupt status        */
-#define  FMPI2C_ISR_RXNE                      0x00000004U        /*!< Receive data register not empty  */
-#define  FMPI2C_ISR_ADDR                      0x00000008U        /*!< Address matched (slave mode)     */
-#define  FMPI2C_ISR_NACKF                     0x00000010U        /*!< NACK received flag               */
-#define  FMPI2C_ISR_STOPF                     0x00000020U        /*!< STOP detection flag              */
-#define  FMPI2C_ISR_TC                        0x00000040U        /*!< Transfer complete (master mode)  */
-#define  FMPI2C_ISR_TCR                       0x00000080U        /*!< Transfer complete reload         */
-#define  FMPI2C_ISR_BERR                      0x00000100U        /*!< Bus error                        */
-#define  FMPI2C_ISR_ARLO                      0x00000200U        /*!< Arbitration lost                 */
-#define  FMPI2C_ISR_OVR                       0x00000400U        /*!< Overrun/Underrun                 */
-#define  FMPI2C_ISR_PECERR                    0x00000800U        /*!< PEC error in reception           */
-#define  FMPI2C_ISR_TIMEOUT                   0x00001000U        /*!< Timeout or Tlow detection flag   */
-#define  FMPI2C_ISR_ALERT                     0x00002000U        /*!< SMBus alert                      */
-#define  FMPI2C_ISR_BUSY                      0x00008000U        /*!< Bus busy                         */
-#define  FMPI2C_ISR_DIR                       0x00010000U        /*!< Transfer direction (slave mode)  */
-#define  FMPI2C_ISR_ADDCODE                   0x00FE0000U        /*!< Address match code (slave mode)  */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define  FMPI2C_ICR_ADDRCF                    0x00000008U        /*!< Address matched clear flag  */
-#define  FMPI2C_ICR_NACKCF                    0x00000010U        /*!< NACK clear flag             */
-#define  FMPI2C_ICR_STOPCF                    0x00000020U        /*!< STOP detection clear flag   */
-#define  FMPI2C_ICR_BERRCF                    0x00000100U        /*!< Bus error clear flag        */
-#define  FMPI2C_ICR_ARLOCF                    0x00000200U        /*!< Arbitration lost clear flag */
-#define  FMPI2C_ICR_OVRCF                     0x00000400U        /*!< Overrun/Underrun clear flag */
-#define  FMPI2C_ICR_PECCF                     0x00000800U        /*!< PAC error clear flag        */
-#define  FMPI2C_ICR_TIMOUTCF                  0x00001000U        /*!< Timeout clear flag          */
-#define  FMPI2C_ICR_ALERTCF                   0x00002000U        /*!< Alert clear flag            */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define  FMPI2C_PECR_PEC                      0x000000FFU        /*!< PEC register */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define  FMPI2C_RXDR_RXDATA                   0x000000FFU        /*!< 8-bit receive data */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define  FMPI2C_TXDR_TXDATA                   0x000000FFU        /*!< 8-bit transmit data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Independent WATCHDOG                             */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         0x01U               /*!<Watchdog prescaler value update      */
-#define  IWDG_SR_RVU                         0x02U               /*!<Watchdog counter reload value update */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                             Power Control                                  */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
-#define  PWR_CR_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
-#define  PWR_CR_CWUF                         0x00000004U     /*!< Clear Wakeup Flag                   */
-#define  PWR_CR_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
-#define  PWR_CR_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
-
-#define  PWR_CR_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        0x00000020U     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        0x00000040U     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        0x00000080U     /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
-
-#define  PWR_CR_DBP                          0x00000100U     /*!< Disable Backup Domain write protection                     */
-#define  PWR_CR_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                              */
-#define  PWR_CR_LPLVDS                       0x00000400U     /*!< Low Power Regulator Low Voltage in Deep Sleep mode         */
-#define  PWR_CR_MRLVDS                       0x00000800U     /*!< Main Regulator Low Voltage in Deep Sleep mode              */
-#define  PWR_CR_ADCDC1                       0x00002000U     /*!< Refer to AN4073 on how to use this bit                     */
-
-#define  PWR_CR_VOS                          0x0000C000U     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
-#define  PWR_CR_VOS_0                        0x00004000U     /*!< Bit 0 */
-#define  PWR_CR_VOS_1                        0x00008000U     /*!< Bit 1 */
-
-#define  PWR_CR_FMSSR                        0x00100000U     /*!< Flash Memory Sleep System Run        */
-#define  PWR_CR_FISSR                        0x00200000U     /*!< Flash Interface Stop while System Run */
-/* Legacy define */
-#define  PWR_CR_PMODE                        PWR_CR_VOS
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         0x00000001U     /*!< Wakeup Flag                                      */
-#define  PWR_CSR_SBF                         0x00000002U     /*!< Standby Flag                                     */
-#define  PWR_CSR_PVDO                        0x00000004U     /*!< PVD Output                                       */
-#define  PWR_CSR_BRR                         0x00000008U     /*!< Backup regulator ready                           */
-#define  PWR_CSR_EWUP                        0x00000100U     /*!< Enable WKUP pin                                  */
-#define  PWR_CSR_BRE                         0x00000200U     /*!< Backup regulator enable                          */
-#define  PWR_CSR_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
-
-/* Legacy define */
-#define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        0x00000001U
-#define  RCC_CR_HSIRDY                       0x00000002U
-
-#define  RCC_CR_HSITRIM                      0x000000F8U
-#define  RCC_CR_HSITRIM_0                    0x00000008U/*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    0x00000010U/*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    0x00000020U/*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    0x00000040U/*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    0x00000080U/*!<Bit 4 */
-
-#define  RCC_CR_HSICAL                       0x0000FF00U
-#define  RCC_CR_HSICAL_0                     0x00000100U/*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     0x00000200U/*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     0x00000400U/*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     0x00000800U/*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     0x00001000U/*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     0x00002000U/*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     0x00004000U/*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     0x00008000U/*!<Bit 7 */
-
-#define  RCC_CR_HSEON                        0x00010000U
-#define  RCC_CR_HSERDY                       0x00020000U
-#define  RCC_CR_HSEBYP                       0x00040000U
-#define  RCC_CR_CSSON                        0x00080000U
-#define  RCC_CR_PLLON                        0x01000000U
-#define  RCC_CR_PLLRDY                       0x02000000U
-
-/********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    0x0000003FU
-#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
-#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
-#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
-#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
-#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
-#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
-
-#define  RCC_PLLCFGR_PLLN                     0x00007FC0U
-#define  RCC_PLLCFGR_PLLN_0                   0x00000040U
-#define  RCC_PLLCFGR_PLLN_1                   0x00000080U
-#define  RCC_PLLCFGR_PLLN_2                   0x00000100U
-#define  RCC_PLLCFGR_PLLN_3                   0x00000200U
-#define  RCC_PLLCFGR_PLLN_4                   0x00000400U
-#define  RCC_PLLCFGR_PLLN_5                   0x00000800U
-#define  RCC_PLLCFGR_PLLN_6                   0x00001000U
-#define  RCC_PLLCFGR_PLLN_7                   0x00002000U
-#define  RCC_PLLCFGR_PLLN_8                   0x00004000U
-
-#define  RCC_PLLCFGR_PLLP                    0x00030000U
-#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
-#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
-
-#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
-
-#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
-#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
-#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
-#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
-#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
-
-#define  RCC_PLLCFGR_PLLR                    0x70000000U
-#define  RCC_PLLCFGR_PLLR_0                  0x10000000U
-#define  RCC_PLLCFGR_PLLR_1                  0x20000000U
-#define  RCC_PLLCFGR_PLLR_2                  0x40000000U
-/********************  Bit definition for RCC_CFGR register  ******************/
-/*!< SW configuration */
-#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
-
-#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
-
-#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
-
-#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
-
-/*!< MCO1EN configuration */
-#define  RCC_CFGR_MCO1EN                     0x00000100U        /*!< MCO1EN bit */
-
-/*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
-
-/*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     0x001F0000U
-#define  RCC_CFGR_RTCPRE_0                   0x00010000U
-#define  RCC_CFGR_RTCPRE_1                   0x00020000U
-#define  RCC_CFGR_RTCPRE_2                   0x00040000U
-#define  RCC_CFGR_RTCPRE_3                   0x00080000U
-#define  RCC_CFGR_RTCPRE_4                   0x00100000U
-
-/*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       0x00600000U
-#define  RCC_CFGR_MCO1_0                     0x00200000U
-#define  RCC_CFGR_MCO1_1                     0x00400000U
-
-#define  RCC_CFGR_MCO1PRE                    0x07000000U
-#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
-#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
-#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
-
-#define  RCC_CFGR_MCO2PRE                    0x38000000U
-#define  RCC_CFGR_MCO2PRE_0                  0x08000000U
-#define  RCC_CFGR_MCO2PRE_1                  0x10000000U
-#define  RCC_CFGR_MCO2PRE_2                  0x20000000U
-
-#define  RCC_CFGR_MCO2                       0xC0000000U
-#define  RCC_CFGR_MCO2_0                     0x40000000U
-#define  RCC_CFGR_MCO2_1                     0x80000000U
-
-/********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     0x00000001U
-#define  RCC_CIR_LSERDYF                     0x00000002U
-#define  RCC_CIR_HSIRDYF                     0x00000004U
-#define  RCC_CIR_HSERDYF                     0x00000008U
-#define  RCC_CIR_PLLRDYF                     0x00000010U
-
-#define  RCC_CIR_CSSF                        0x00000080U
-#define  RCC_CIR_LSIRDYIE                    0x00000100U
-#define  RCC_CIR_LSERDYIE                    0x00000200U
-#define  RCC_CIR_HSIRDYIE                    0x00000400U
-#define  RCC_CIR_HSERDYIE                    0x00000800U
-#define  RCC_CIR_PLLRDYIE                    0x00001000U
-
-#define  RCC_CIR_LSIRDYC                     0x00010000U
-#define  RCC_CIR_LSERDYC                     0x00020000U
-#define  RCC_CIR_HSIRDYC                     0x00040000U
-#define  RCC_CIR_HSERDYC                     0x00080000U
-#define  RCC_CIR_PLLRDYC                     0x00100000U
-
-#define  RCC_CIR_CSSC                        0x00800000U
-
-/********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
-#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
-#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
-#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
-#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
-#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
-#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
-#define  RCC_AHB1RSTR_RNGRST                 0x80000000U
-
-/********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM5RST                0x00000008U
-#define  RCC_APB1RSTR_TIM6RST                0x00000010U
-#define  RCC_APB1RSTR_LPTIM1RST              0x00000200U
-#define  RCC_APB1RSTR_WWDGRST                0x00000800U
-#define  RCC_APB1RSTR_USART2RST              0x00020000U
-#define  RCC_APB1RSTR_I2C1RST                0x00200000U
-#define  RCC_APB1RSTR_I2C2RST                0x00400000U
-#define  RCC_APB1RSTR_FMPI2C1RST             0x01000000U
-#define  RCC_APB1RSTR_PWRRST                 0x10000000U
-#define  RCC_APB1RSTR_DACRST                 0x20000000U
-
-/********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                0x00000001U
-#define  RCC_APB2RSTR_USART1RST              0x00000010U
-#define  RCC_APB2RSTR_ADCRST                 0x00000100U
-#define  RCC_APB2RSTR_SPI1RST                0x00001000U
-#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
-#define  RCC_APB2RSTR_TIM9RST                0x00010000U
-#define  RCC_APB2RSTR_TIM11RST               0x00040000U
-
-/********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
-#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
-#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
-#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
-#define  RCC_AHB1ENR_CRCEN                   0x00001000U
-#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
-#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
-#define  RCC_AHB1ENR_RNGEN                   0x80000000U
-
-/********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM5EN                  0x00000008U
-#define  RCC_APB1ENR_TIM6EN                  0x00000010U
-#define  RCC_APB1ENR_LPTIM1EN                0x00000200U
-#define  RCC_APB1ENR_RTCAPBEN                0x00000400U
-#define  RCC_APB1ENR_WWDGEN                  0x00000800U
-#define  RCC_APB1ENR_USART2EN                0x00020000U
-#define  RCC_APB1ENR_I2C1EN                  0x00200000U
-#define  RCC_APB1ENR_I2C2EN                  0x00400000U
-#define  RCC_APB1ENR_FMPI2C1EN               0x01000000U
-#define  RCC_APB1ENR_PWREN                   0x10000000U
-#define  RCC_APB1ENR_DACEN                   0x20000000U
-
-/********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  0x00000001U
-#define  RCC_APB2ENR_USART1EN                0x00000010U
-#define  RCC_APB2ENR_ADC1EN                  0x00000100U
-#define  RCC_APB2ENR_SPI1EN                  0x00001000U
-#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
-#define  RCC_APB2ENR_EXTITEN                 0x00008000U
-#define  RCC_APB2ENR_TIM9EN                  0x00010000U
-#define  RCC_APB2ENR_TIM11EN                 0x00040000U
-
-/********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
-#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
-#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
-#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
-#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
-#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
-#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
-#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
-#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
-#define  RCC_AHB1LPENR_RNGLPEN               0x80000000U
-
-/********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
-#define  RCC_APB1LPENR_TIM6LPEN              0x00000010U
-#define  RCC_APB1LPENR_LPTIM1LPEN            0x00000200U
-#define  RCC_APB1LPENR_RTCAPBLPEN            0x00000400U
-#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
-#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
-#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
-#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
-#define  RCC_APB1LPENR_FMPI2C1LPEN           0x01000000U
-#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
-#define  RCC_APB1LPENR_DACLPEN               0x20000000U
-
-/********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
-#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
-#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
-#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
-#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
-#define  RCC_APB2LPENR_EXTITLPEN             0x00008000U
-#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
-#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
-
-/********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      0x00000001U
-#define  RCC_BDCR_LSERDY                     0x00000002U
-#define  RCC_BDCR_LSEBYP                     0x00000004U
-#define  RCC_BDCR_LSEMOD                     0x00000008U
-
-#define  RCC_BDCR_RTCSEL                    0x00000300U
-#define  RCC_BDCR_RTCSEL_0                  0x00000100U
-#define  RCC_BDCR_RTCSEL_1                  0x00000200U
-
-#define  RCC_BDCR_RTCEN                      0x00008000U
-#define  RCC_BDCR_BDRST                      0x00010000U
-
-/********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       0x00000001U
-#define  RCC_CSR_LSIRDY                      0x00000002U
-#define  RCC_CSR_RMVF                        0x01000000U
-#define  RCC_CSR_BORRSTF                     0x02000000U
-#define  RCC_CSR_PADRSTF                     0x04000000U
-#define  RCC_CSR_PORRSTF                     0x08000000U
-#define  RCC_CSR_SFTRSTF                     0x10000000U
-#define  RCC_CSR_WDGRSTF                     0x20000000U
-#define  RCC_CSR_WWDGRSTF                    0x40000000U
-#define  RCC_CSR_LPWRRSTF                    0x80000000U
-
-/********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    0x00001FFFU
-#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
-#define  RCC_SSCGR_SPREADSEL                 0x40000000U
-#define  RCC_SSCGR_SSCGEN                    0x80000000U
-
-/********************  Bit definition for RCC_DCKCFGR register  ***************/
-#define  RCC_DCKCFGR_TIMPRE                  0x01000000U
-#define  RCC_DCKCFGR_I2SSRC                  0x06000000U
-#define  RCC_DCKCFGR_I2SSRC_0                0x02000000U
-#define  RCC_DCKCFGR_I2SSRC_1                0x04000000U
-
-/********************  Bit definition for RCC_CKGATENR register  **************/
-#define  RCC_CKGATENR_AHB2APB1_CKEN          0x00000001U
-#define  RCC_CKGATENR_AHB2APB2_CKEN          0x00000002U
-#define  RCC_CKGATENR_CM4DBG_CKEN            0x00000004U
-#define  RCC_CKGATENR_SPARE_CKEN             0x00000008U
-#define  RCC_CKGATENR_SRAM_CKEN              0x00000010U
-#define  RCC_CKGATENR_FLITF_CKEN             0x00000020U
-#define  RCC_CKGATENR_RCC_CKEN               0x00000040U
-
-/********************  Bit definition for RCC_DCKCFGR2 register  **************/
-#define  RCC_DCKCFGR2_FMPI2C1SEL             0x00C00000U
-#define  RCC_DCKCFGR2_FMPI2C1SEL_0           0x00400000U
-#define  RCC_DCKCFGR2_FMPI2C1SEL_1           0x00800000U
-#define  RCC_DCKCFGR2_LPTIM1SEL              0xC0000000U
-#define  RCC_DCKCFGR2_LPTIM1SEL_0            0x40000000U
-#define  RCC_DCKCFGR2_LPTIM1SEL_1            0x80000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    RNG                                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN                         0x00000004U
-#define RNG_CR_IE                            0x00000008U
-
-/********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY                          0x00000001U
-#define RNG_SR_CECS                          0x00000002U
-#define RNG_SR_SECS                          0x00000004U
-#define RNG_SR_CEIS                          0x00000020U
-#define RNG_SR_SEIS                          0x00000040U
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            0x00400000U
-#define RTC_TR_HT                            0x00300000U
-#define RTC_TR_HT_0                          0x00100000U
-#define RTC_TR_HT_1                          0x00200000U
-#define RTC_TR_HU                            0x000F0000U
-#define RTC_TR_HU_0                          0x00010000U
-#define RTC_TR_HU_1                          0x00020000U
-#define RTC_TR_HU_2                          0x00040000U
-#define RTC_TR_HU_3                          0x00080000U
-#define RTC_TR_MNT                           0x00007000U
-#define RTC_TR_MNT_0                         0x00001000U
-#define RTC_TR_MNT_1                         0x00002000U
-#define RTC_TR_MNT_2                         0x00004000U
-#define RTC_TR_MNU                           0x00000F00U
-#define RTC_TR_MNU_0                         0x00000100U
-#define RTC_TR_MNU_1                         0x00000200U
-#define RTC_TR_MNU_2                         0x00000400U
-#define RTC_TR_MNU_3                         0x00000800U
-#define RTC_TR_ST                            0x00000070U
-#define RTC_TR_ST_0                          0x00000010U
-#define RTC_TR_ST_1                          0x00000020U
-#define RTC_TR_ST_2                          0x00000040U
-#define RTC_TR_SU                            0x0000000FU
-#define RTC_TR_SU_0                          0x00000001U
-#define RTC_TR_SU_1                          0x00000002U
-#define RTC_TR_SU_2                          0x00000004U
-#define RTC_TR_SU_3                          0x00000008U
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            0x00F00000U
-#define RTC_DR_YT_0                          0x00100000U
-#define RTC_DR_YT_1                          0x00200000U
-#define RTC_DR_YT_2                          0x00400000U
-#define RTC_DR_YT_3                          0x00800000U
-#define RTC_DR_YU                            0x000F0000U
-#define RTC_DR_YU_0                          0x00010000U
-#define RTC_DR_YU_1                          0x00020000U
-#define RTC_DR_YU_2                          0x00040000U
-#define RTC_DR_YU_3                          0x00080000U
-#define RTC_DR_WDU                           0x0000E000U
-#define RTC_DR_WDU_0                         0x00002000U
-#define RTC_DR_WDU_1                         0x00004000U
-#define RTC_DR_WDU_2                         0x00008000U
-#define RTC_DR_MT                            0x00001000U
-#define RTC_DR_MU                            0x00000F00U
-#define RTC_DR_MU_0                          0x00000100U
-#define RTC_DR_MU_1                          0x00000200U
-#define RTC_DR_MU_2                          0x00000400U
-#define RTC_DR_MU_3                          0x00000800U
-#define RTC_DR_DT                            0x00000030U
-#define RTC_DR_DT_0                          0x00000010U
-#define RTC_DR_DT_1                          0x00000020U
-#define RTC_DR_DU                            0x0000000FU
-#define RTC_DR_DU_0                          0x00000001U
-#define RTC_DR_DU_1                          0x00000002U
-#define RTC_DR_DU_2                          0x00000004U
-#define RTC_DR_DU_3                          0x00000008U
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           0x00800000U
-#define RTC_CR_OSEL                          0x00600000U
-#define RTC_CR_OSEL_0                        0x00200000U
-#define RTC_CR_OSEL_1                        0x00400000U
-#define RTC_CR_POL                           0x00100000U
-#define RTC_CR_COSEL                         0x00080000U
-#define RTC_CR_BCK                           0x00040000U
-#define RTC_CR_SUB1H                         0x00020000U
-#define RTC_CR_ADD1H                         0x00010000U
-#define RTC_CR_TSIE                          0x00008000U
-#define RTC_CR_WUTIE                         0x00004000U
-#define RTC_CR_ALRBIE                        0x00002000U
-#define RTC_CR_ALRAIE                        0x00001000U
-#define RTC_CR_TSE                           0x00000800U
-#define RTC_CR_WUTE                          0x00000400U
-#define RTC_CR_ALRBE                         0x00000200U
-#define RTC_CR_ALRAE                         0x00000100U
-#define RTC_CR_DCE                           0x00000080U
-#define RTC_CR_FMT                           0x00000040U
-#define RTC_CR_BYPSHAD                       0x00000020U
-#define RTC_CR_REFCKON                       0x00000010U
-#define RTC_CR_TSEDGE                        0x00000008U
-#define RTC_CR_WUCKSEL                       0x00000007U
-#define RTC_CR_WUCKSEL_0                     0x00000001U
-#define RTC_CR_WUCKSEL_1                     0x00000002U
-#define RTC_CR_WUCKSEL_2                     0x00000004U
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      0x00010000U
-#define RTC_ISR_TAMP1F                       0x00002000U
-#define RTC_ISR_TAMP2F                       0x00004000U
-#define RTC_ISR_TSOVF                        0x00001000U
-#define RTC_ISR_TSF                          0x00000800U
-#define RTC_ISR_WUTF                         0x00000400U
-#define RTC_ISR_ALRBF                        0x00000200U
-#define RTC_ISR_ALRAF                        0x00000100U
-#define RTC_ISR_INIT                         0x00000080U
-#define RTC_ISR_INITF                        0x00000040U
-#define RTC_ISR_RSF                          0x00000020U
-#define RTC_ISR_INITS                        0x00000010U
-#define RTC_ISR_SHPF                         0x00000008U
-#define RTC_ISR_WUTWF                        0x00000004U
-#define RTC_ISR_ALRBWF                       0x00000002U
-#define RTC_ISR_ALRAWF                       0x00000001U
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    0x007F0000U
-#define RTC_PRER_PREDIV_S                    0x00007FFFU
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS                       0x00000080U
-#define RTC_CALIBR_DC                        0x0000001FU
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      0x80000000U
-#define RTC_ALRMAR_WDSEL                     0x40000000U
-#define RTC_ALRMAR_DT                        0x30000000U
-#define RTC_ALRMAR_DT_0                      0x10000000U
-#define RTC_ALRMAR_DT_1                      0x20000000U
-#define RTC_ALRMAR_DU                        0x0F000000U
-#define RTC_ALRMAR_DU_0                      0x01000000U
-#define RTC_ALRMAR_DU_1                      0x02000000U
-#define RTC_ALRMAR_DU_2                      0x04000000U
-#define RTC_ALRMAR_DU_3                      0x08000000U
-#define RTC_ALRMAR_MSK3                      0x00800000U
-#define RTC_ALRMAR_PM                        0x00400000U
-#define RTC_ALRMAR_HT                        0x00300000U
-#define RTC_ALRMAR_HT_0                      0x00100000U
-#define RTC_ALRMAR_HT_1                      0x00200000U
-#define RTC_ALRMAR_HU                        0x000F0000U
-#define RTC_ALRMAR_HU_0                      0x00010000U
-#define RTC_ALRMAR_HU_1                      0x00020000U
-#define RTC_ALRMAR_HU_2                      0x00040000U
-#define RTC_ALRMAR_HU_3                      0x00080000U
-#define RTC_ALRMAR_MSK2                      0x00008000U
-#define RTC_ALRMAR_MNT                       0x00007000U
-#define RTC_ALRMAR_MNT_0                     0x00001000U
-#define RTC_ALRMAR_MNT_1                     0x00002000U
-#define RTC_ALRMAR_MNT_2                     0x00004000U
-#define RTC_ALRMAR_MNU                       0x00000F00U
-#define RTC_ALRMAR_MNU_0                     0x00000100U
-#define RTC_ALRMAR_MNU_1                     0x00000200U
-#define RTC_ALRMAR_MNU_2                     0x00000400U
-#define RTC_ALRMAR_MNU_3                     0x00000800U
-#define RTC_ALRMAR_MSK1                      0x00000080U
-#define RTC_ALRMAR_ST                        0x00000070U
-#define RTC_ALRMAR_ST_0                      0x00000010U
-#define RTC_ALRMAR_ST_1                      0x00000020U
-#define RTC_ALRMAR_ST_2                      0x00000040U
-#define RTC_ALRMAR_SU                        0x0000000FU
-#define RTC_ALRMAR_SU_0                      0x00000001U
-#define RTC_ALRMAR_SU_1                      0x00000002U
-#define RTC_ALRMAR_SU_2                      0x00000004U
-#define RTC_ALRMAR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      0x80000000U
-#define RTC_ALRMBR_WDSEL                     0x40000000U
-#define RTC_ALRMBR_DT                        0x30000000U
-#define RTC_ALRMBR_DT_0                      0x10000000U
-#define RTC_ALRMBR_DT_1                      0x20000000U
-#define RTC_ALRMBR_DU                        0x0F000000U
-#define RTC_ALRMBR_DU_0                      0x01000000U
-#define RTC_ALRMBR_DU_1                      0x02000000U
-#define RTC_ALRMBR_DU_2                      0x04000000U
-#define RTC_ALRMBR_DU_3                      0x08000000U
-#define RTC_ALRMBR_MSK3                      0x00800000U
-#define RTC_ALRMBR_PM                        0x00400000U
-#define RTC_ALRMBR_HT                        0x00300000U
-#define RTC_ALRMBR_HT_0                      0x00100000U
-#define RTC_ALRMBR_HT_1                      0x00200000U
-#define RTC_ALRMBR_HU                        0x000F0000U
-#define RTC_ALRMBR_HU_0                      0x00010000U
-#define RTC_ALRMBR_HU_1                      0x00020000U
-#define RTC_ALRMBR_HU_2                      0x00040000U
-#define RTC_ALRMBR_HU_3                      0x00080000U
-#define RTC_ALRMBR_MSK2                      0x00008000U
-#define RTC_ALRMBR_MNT                       0x00007000U
-#define RTC_ALRMBR_MNT_0                     0x00001000U
-#define RTC_ALRMBR_MNT_1                     0x00002000U
-#define RTC_ALRMBR_MNT_2                     0x00004000U
-#define RTC_ALRMBR_MNU                       0x00000F00U
-#define RTC_ALRMBR_MNU_0                     0x00000100U
-#define RTC_ALRMBR_MNU_1                     0x00000200U
-#define RTC_ALRMBR_MNU_2                     0x00000400U
-#define RTC_ALRMBR_MNU_3                     0x00000800U
-#define RTC_ALRMBR_MSK1                      0x00000080U
-#define RTC_ALRMBR_ST                        0x00000070U
-#define RTC_ALRMBR_ST_0                      0x00000010U
-#define RTC_ALRMBR_ST_1                      0x00000020U
-#define RTC_ALRMBR_ST_2                      0x00000040U
-#define RTC_ALRMBR_SU                        0x0000000FU
-#define RTC_ALRMBR_SU_0                      0x00000001U
-#define RTC_ALRMBR_SU_1                      0x00000002U
-#define RTC_ALRMBR_SU_2                      0x00000004U
-#define RTC_ALRMBR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          0x000000FFU
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           0x0000FFFFU
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     0x00007FFFU
-#define RTC_SHIFTR_ADD1S                     0x80000000U
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          0x00400000U
-#define RTC_TSTR_HT                          0x00300000U
-#define RTC_TSTR_HT_0                        0x00100000U
-#define RTC_TSTR_HT_1                        0x00200000U
-#define RTC_TSTR_HU                          0x000F0000U
-#define RTC_TSTR_HU_0                        0x00010000U
-#define RTC_TSTR_HU_1                        0x00020000U
-#define RTC_TSTR_HU_2                        0x00040000U
-#define RTC_TSTR_HU_3                        0x00080000U
-#define RTC_TSTR_MNT                         0x00007000U
-#define RTC_TSTR_MNT_0                       0x00001000U
-#define RTC_TSTR_MNT_1                       0x00002000U
-#define RTC_TSTR_MNT_2                       0x00004000U
-#define RTC_TSTR_MNU                         0x00000F00U
-#define RTC_TSTR_MNU_0                       0x00000100U
-#define RTC_TSTR_MNU_1                       0x00000200U
-#define RTC_TSTR_MNU_2                       0x00000400U
-#define RTC_TSTR_MNU_3                       0x00000800U
-#define RTC_TSTR_ST                          0x00000070U
-#define RTC_TSTR_ST_0                        0x00000010U
-#define RTC_TSTR_ST_1                        0x00000020U
-#define RTC_TSTR_ST_2                        0x00000040U
-#define RTC_TSTR_SU                          0x0000000FU
-#define RTC_TSTR_SU_0                        0x00000001U
-#define RTC_TSTR_SU_1                        0x00000002U
-#define RTC_TSTR_SU_2                        0x00000004U
-#define RTC_TSTR_SU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         0x0000E000U
-#define RTC_TSDR_WDU_0                       0x00002000U
-#define RTC_TSDR_WDU_1                       0x00004000U
-#define RTC_TSDR_WDU_2                       0x00008000U
-#define RTC_TSDR_MT                          0x00001000U
-#define RTC_TSDR_MU                          0x00000F00U
-#define RTC_TSDR_MU_0                        0x00000100U
-#define RTC_TSDR_MU_1                        0x00000200U
-#define RTC_TSDR_MU_2                        0x00000400U
-#define RTC_TSDR_MU_3                        0x00000800U
-#define RTC_TSDR_DT                          0x00000030U
-#define RTC_TSDR_DT_0                        0x00000010U
-#define RTC_TSDR_DT_1                        0x00000020U
-#define RTC_TSDR_DU                          0x0000000FU
-#define RTC_TSDR_DU_0                        0x00000001U
-#define RTC_TSDR_DU_1                        0x00000002U
-#define RTC_TSDR_DU_2                        0x00000004U
-#define RTC_TSDR_DU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        0x00008000U
-#define RTC_CALR_CALW8                       0x00004000U
-#define RTC_CALR_CALW16                      0x00002000U
-#define RTC_CALR_CALM                        0x000001FFU
-#define RTC_CALR_CALM_0                      0x00000001U
-#define RTC_CALR_CALM_1                      0x00000002U
-#define RTC_CALR_CALM_2                      0x00000004U
-#define RTC_CALR_CALM_3                      0x00000008U
-#define RTC_CALR_CALM_4                      0x00000010U
-#define RTC_CALR_CALM_5                      0x00000020U
-#define RTC_CALR_CALM_6                      0x00000040U
-#define RTC_CALR_CALM_7                      0x00000080U
-#define RTC_CALR_CALM_8                      0x00000100U
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               0x00040000U
-#define RTC_TAFCR_TSINSEL                    0x00020000U
-#define RTC_TAFCR_TAMPINSEL                  0x00010000U
-#define RTC_TAFCR_TAMPPUDIS                  0x00008000U
-#define RTC_TAFCR_TAMPPRCH                   0x00006000U
-#define RTC_TAFCR_TAMPPRCH_0                 0x00002000U
-#define RTC_TAFCR_TAMPPRCH_1                 0x00004000U
-#define RTC_TAFCR_TAMPFLT                    0x00001800U
-#define RTC_TAFCR_TAMPFLT_0                  0x00000800U
-#define RTC_TAFCR_TAMPFLT_1                  0x00001000U
-#define RTC_TAFCR_TAMPFREQ                   0x00000700U
-#define RTC_TAFCR_TAMPFREQ_0                 0x00000100U
-#define RTC_TAFCR_TAMPFREQ_1                 0x00000200U
-#define RTC_TAFCR_TAMPFREQ_2                 0x00000400U
-#define RTC_TAFCR_TAMPTS                     0x00000080U
-#define RTC_TAFCR_TAMP2TRG                   0x00000010U
-#define RTC_TAFCR_TAMP2E                     0x00000008U
-#define RTC_TAFCR_TAMPIE                     0x00000004U
-#define RTC_TAFCR_TAMP1TRG                   0x00000002U
-#define RTC_TAFCR_TAMP1E                     0x00000001U
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  0x0F000000U
-#define RTC_ALRMASSR_MASKSS_0                0x01000000U
-#define RTC_ALRMASSR_MASKSS_1                0x02000000U
-#define RTC_ALRMASSR_MASKSS_2                0x04000000U
-#define RTC_ALRMASSR_MASKSS_3                0x08000000U
-#define RTC_ALRMASSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
-#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
-#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
-#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
-#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
-#define RTC_ALRMBSSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           0xFFFFFFFFU
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        0x00000001U            /*!<Clock Phase      */
-#define  SPI_CR1_CPOL                        0x00000002U            /*!<Clock Polarity   */
-#define  SPI_CR1_MSTR                        0x00000004U            /*!<Master Selection */
-
-#define  SPI_CR1_BR                          0x00000038U            /*!<BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        0x00000008U            /*!<Bit 0 */
-#define  SPI_CR1_BR_1                        0x00000010U            /*!<Bit 1 */
-#define  SPI_CR1_BR_2                        0x00000020U            /*!<Bit 2 */
-
-#define  SPI_CR1_SPE                         0x00000040U            /*!<SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    0x00000080U            /*!<Frame Format                        */
-#define  SPI_CR1_SSI                         0x00000100U            /*!<Internal slave select               */
-#define  SPI_CR1_SSM                         0x00000200U            /*!<Software slave management           */
-#define  SPI_CR1_RXONLY                      0x00000400U            /*!<Receive only                        */
-#define  SPI_CR1_DFF                         0x00000800U            /*!<Data Frame Format                   */
-#define  SPI_CR1_CRCNEXT                     0x00001000U            /*!<Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       0x00002000U            /*!<Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      0x00004000U            /*!<Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    0x00008000U            /*!<Bidirectional data mode enable      */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     0x00000001U               /*!<Rx Buffer DMA Enable                 */
-#define  SPI_CR2_TXDMAEN                     0x00000002U               /*!<Tx Buffer DMA Enable                 */
-#define  SPI_CR2_SSOE                        0x00000004U               /*!<SS Output Enable                     */
-#define  SPI_CR2_FRF                         0x00000010U               /*!<Frame Format                         */
-#define  SPI_CR2_ERRIE                       0x00000020U               /*!<Error Interrupt Enable               */
-#define  SPI_CR2_RXNEIE                      0x00000040U               /*!<RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       0x00000080U               /*!<Tx buffer Empty Interrupt Enable     */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         0x00000001U               /*!<Receive buffer Not Empty */
-#define  SPI_SR_TXE                          0x00000002U               /*!<Transmit buffer Empty    */
-#define  SPI_SR_CHSIDE                       0x00000004U               /*!<Channel side             */
-#define  SPI_SR_UDR                          0x00000008U               /*!<Underrun flag            */
-#define  SPI_SR_CRCERR                       0x00000010U               /*!<CRC Error flag           */
-#define  SPI_SR_MODF                         0x00000020U               /*!<Mode fault               */
-#define  SPI_SR_OVR                          0x00000040U               /*!<Overrun flag             */
-#define  SPI_SR_BSY                          0x00000080U               /*!<Busy flag                */
-#define  SPI_SR_FRE                          0x00000100U               /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           0x0000FFFFU            /*!<Data Register           */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   0x0000FFFFU            /*!<CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    0x0000FFFFU            /*!<Rx CRC Register         */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    0x0000FFFFU            /*!<Tx CRC Register         */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   0x00000001U            /*!<Channel length (number of bits per audio channel) */
-
-#define  SPI_I2SCFGR_DATLEN                  0x00000006U            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define  SPI_I2SCFGR_DATLEN_0                0x00000002U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                0x00000004U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_CKPOL                   0x00000008U            /*!<steady state clock polarity               */
-
-#define  SPI_I2SCFGR_I2SSTD                  0x00000030U            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U            /*!<PCM frame synchronization                 */
-
-#define  SPI_I2SCFGR_I2SCFG                  0x00000300U            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_I2SE                    0x00000400U            /*!<I2S Enable         */
-#define  SPI_I2SCFGR_I2SMOD                  0x00000800U            /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    0x000000FFU            /*!<I2S Linear prescaler         */
-#define  SPI_I2SPR_ODD                       0x00000100U            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     0x00000200U            /*!<Master Clock Output Enable   */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 SYSCFG                                     */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
-#define SYSCFG_MEMRMP_MEM_MODE          0x00000007U /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        0x00000001U
-#define SYSCFG_MEMRMP_MEM_MODE_1        0x00000002U
-#define SYSCFG_MEMRMP_MEM_MODE_2        0x00000004U
-
-/******************  Bit definition for SYSCFG_PMC register  ******************/
-#define SYSCFG_PMC_ADC1DC2              0x00010000U /*!< Refer to AN4073 on how to use this bit  */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
-/** 
-  * @brief   EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
-
-/** 
-  * @brief   EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
-
-/** 
-  * @brief   EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
-
-/** 
-  * @brief   EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
-/** 
-  * @brief   EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
-
-/** 
-  * @brief   EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
-
-/** 
-  * @brief   EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
-
-/** 
-  * @brief   EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
-
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
-           
-/** 
-  * @brief   EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
-
-/** 
-  * @brief   EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
-
-/** 
-  * @brief   EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
-
-/** 
-  * @brief   EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
-/** 
-  * @brief   EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
-
-/** 
-  * @brief   EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
-
-/** 
-  * @brief   EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
-
-/** 
-  * @brief   EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
-
-/******************  Bit definition for SYSCFG_CMPCR register  ****************/
-#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell ready flag */
-#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell power-down */
-
-/******************  Bit definition for SYSCFG_CFGR register  *****************/
-#define SYSCFG_CFGR_FMPI2C1_SCL         0x00000001U /*!<FM+ drive capability for FMPI2C1_SCL pin */
-#define SYSCFG_CFGR_FMPI2C1_SDA         0x00000002U /*!<FM+ drive capability for FMPI2C1_SDA pin */
-
-/******************  Bit definition for SYSCFG_CFGR2 register  *****************/
-#define SYSCFG_CFGR2_LOCKUP_LOCK        0x00000001U /*!<Core Lockup lock */
-#define SYSCFG_CFGR2_PVD_LOCK           0x00000004U /*!<PVD Lock         */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    TIM                                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
-#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
-#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
-#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
-#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
-
-#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
-
-#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
-
-#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        0x0001U            /*!<Capture/Compare Preloaded Control        */
-#define  TIM_CR2_CCUS                        0x0004U            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        0x0008U            /*!<Capture/Compare DMA Selection            */
-
-#define  TIM_CR2_MMS                         0x0070U            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
-#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
-#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
-#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        0x0007U            /*!<SMS[2:0] bits (Slave mode selection)    */
-#define  TIM_SMCR_SMS_0                      0x0001U            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      0x0002U            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      0x0004U            /*!<Bit 2 */
-
-#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
-#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
-
-#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
-
-#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
-
-#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
-#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
-#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
-#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
-#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
-#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
-#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
-#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
-#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
-#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
-#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
-#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
-#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
-#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
-#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
-#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
-#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
-#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
-#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          0x01U               /*!<Update Generation                         */
-#define  TIM_EGR_CC1G                        0x02U               /*!<Capture/Compare 1 Generation              */
-#define  TIM_EGR_CC2G                        0x04U               /*!<Capture/Compare 2 Generation              */
-#define  TIM_EGR_CC3G                        0x08U               /*!<Capture/Compare 3 Generation              */
-#define  TIM_EGR_CC4G                        0x10U               /*!<Capture/Compare 4 Generation              */
-#define  TIM_EGR_COMG                        0x20U               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          0x40U               /*!<Trigger Generation                        */
-#define  TIM_EGR_BG                          0x80U               /*!<Break Generation                          */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      0x0003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    0x0001U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    0x0002U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC1FE                     0x0004U            /*!<Output Compare 1 Fast enable                 */
-#define  TIM_CCMR1_OC1PE                     0x0008U            /*!<Output Compare 1 Preload enable              */
-
-#define  TIM_CCMR1_OC1M                      0x0070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define  TIM_CCMR1_OC1M_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    0x0040U            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC1CE                     0x0080U            /*!<Output Compare 1Clear Enable                 */
-
-#define  TIM_CCMR1_CC2S                      0x0300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    0x0100U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    0x0200U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC2FE                     0x0400U            /*!<Output Compare 2 Fast enable                 */
-#define  TIM_CCMR1_OC2PE                     0x0800U            /*!<Output Compare 2 Preload enable              */
-
-#define  TIM_CCMR1_OC2M                      0x7000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define  TIM_CCMR1_OC2M_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    0x4000U            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC2CE                     0x8000U            /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      0x0003U            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define  TIM_CCMR2_CC3S_0                    0x0001U            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    0x0002U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC3FE                     0x0004U            /*!<Output Compare 3 Fast enable           */
-#define  TIM_CCMR2_OC3PE                     0x0008U            /*!<Output Compare 3 Preload enable        */
-
-#define  TIM_CCMR2_OC3M                      0x0070U            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    0x0040U            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC3CE                     0x0080U            /*!<Output Compare 3 Clear Enable */
-
-#define  TIM_CCMR2_CC4S                      0x0300U            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    0x0100U            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    0x0200U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC4FE                     0x0400U            /*!<Output Compare 4 Fast enable    */
-#define  TIM_CCMR2_OC4PE                     0x0800U            /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR2_OC4M                      0x7000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    0x4000U            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       0x0001U            /*!<Capture/Compare 1 output enable                 */
-#define  TIM_CCER_CC1P                       0x0002U            /*!<Capture/Compare 1 output Polarity               */
-#define  TIM_CCER_CC1NE                      0x0004U            /*!<Capture/Compare 1 Complementary output enable   */
-#define  TIM_CCER_CC1NP                      0x0008U            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       0x0010U            /*!<Capture/Compare 2 output enable                 */
-#define  TIM_CCER_CC2P                       0x0020U            /*!<Capture/Compare 2 output Polarity               */
-#define  TIM_CCER_CC2NE                      0x0040U            /*!<Capture/Compare 2 Complementary output enable   */
-#define  TIM_CCER_CC2NP                      0x0080U            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       0x0100U            /*!<Capture/Compare 3 output enable                 */
-#define  TIM_CCER_CC3P                       0x0200U            /*!<Capture/Compare 3 output Polarity               */
-#define  TIM_CCER_CC3NE                      0x0400U            /*!<Capture/Compare 3 Complementary output enable   */
-#define  TIM_CCER_CC3NP                      0x0800U            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       0x1000U            /*!<Capture/Compare 4 output enable                 */
-#define  TIM_CCER_CC4P                       0x2000U            /*!<Capture/Compare 4 output Polarity               */
-#define  TIM_CCER_CC4NP                      0x8000U            /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         0xFFU               /*!<Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
-
-/*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        0x00FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      0x0001U            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      0x0002U            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      0x0004U            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      0x0008U            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      0x0010U            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      0x0020U            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      0x0040U            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      0x0080U            /*!<Bit 7 */
-
-#define  TIM_BDTR_LOCK                       0x0300U            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     0x0100U            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     0x0200U            /*!<Bit 1 */
-
-#define  TIM_BDTR_OSSI                       0x0400U            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       0x0800U            /*!<Off-State Selection for Run mode  */
-#define  TIM_BDTR_BKE                        0x1000U            /*!<Break enable                      */
-#define  TIM_BDTR_BKP                        0x2000U            /*!<Break Polarity                    */
-#define  TIM_BDTR_AOE                        0x4000U            /*!<Automatic Output enable           */
-#define  TIM_BDTR_MOE                        0x8000U            /*!<Main Output enable                */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
-
-#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Low Power Timer (LPTIM)                            */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for LPTIM_ISR register  *******************/
-#define  LPTIM_ISR_CMPM                         0x00000001U            /*!< Compare match                       */
-#define  LPTIM_ISR_ARRM                         0x00000002U            /*!< Autoreload match                    */
-#define  LPTIM_ISR_EXTTRIG                      0x00000004U            /*!< External trigger edge event         */
-#define  LPTIM_ISR_CMPOK                        0x00000008U            /*!< Compare register update OK          */
-#define  LPTIM_ISR_ARROK                        0x00000010U            /*!< Autoreload register update OK       */
-#define  LPTIM_ISR_UP                           0x00000020U            /*!< Counter direction change down to up */
-#define  LPTIM_ISR_DOWN                         0x00000040U            /*!< Counter direction change up to down */
-
-/******************  Bit definition for LPTIM_ICR register  *******************/
-#define  LPTIM_ICR_CMPMCF                       0x00000001U            /*!< Compare match Clear Flag                       */
-#define  LPTIM_ICR_ARRMCF                       0x00000002U            /*!< Autoreload match Clear Flag                    */
-#define  LPTIM_ICR_EXTTRIGCF                    0x00000004U            /*!< External trigger edge event Clear Flag         */
-#define  LPTIM_ICR_CMPOKCF                      0x00000008U            /*!< Compare register update OK Clear Flag          */
-#define  LPTIM_ICR_ARROKCF                      0x00000010U            /*!< Autoreload register update OK Clear Flag       */
-#define  LPTIM_ICR_UPCF                         0x00000020U            /*!< Counter direction change down to up Clear Flag */
-#define  LPTIM_ICR_DOWNCF                       0x00000040U            /*!< Counter direction change up to down Clear Flag */
-
-/******************  Bit definition for LPTIM_IER register ********************/
-#define  LPTIM_IER_CMPMIE                       0x00000001U            /*!< Compare match Interrupt Enable                       */
-#define  LPTIM_IER_ARRMIE                       0x00000002U            /*!< Autoreload match Interrupt Enable                    */
-#define  LPTIM_IER_EXTTRIGIE                    0x00000004U            /*!< External trigger edge event Interrupt Enable         */
-#define  LPTIM_IER_CMPOKIE                      0x00000008U            /*!< Compare register update OK Interrupt Enable          */
-#define  LPTIM_IER_ARROKIE                      0x00000010U            /*!< Autoreload register update OK Interrupt Enable       */
-#define  LPTIM_IER_UPIE                         0x00000020U            /*!< Counter direction change down to up Interrupt Enable */
-#define  LPTIM_IER_DOWNIE                       0x00000040U            /*!< Counter direction change up to down Interrupt Enable */
-
-/******************  Bit definition for LPTIM_CFGR register *******************/
-#define  LPTIM_CFGR_CKSEL                       0x00000001U             /*!< Clock selector */
-
-#define  LPTIM_CFGR_CKPOL                       0x00000006U             /*!< CKPOL[1:0] bits (Clock polarity) */
-#define  LPTIM_CFGR_CKPOL_0                     0x00000002U             /*!< Bit 0 */
-#define  LPTIM_CFGR_CKPOL_1                     0x00000004U             /*!< Bit 1 */
-
-#define  LPTIM_CFGR_CKFLT                       0x00000018U             /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
-#define  LPTIM_CFGR_CKFLT_0                     0x00000008U             /*!< Bit 0 */
-#define  LPTIM_CFGR_CKFLT_1                     0x00000010U             /*!< Bit 1 */
-
-#define  LPTIM_CFGR_TRGFLT                      0x000000C0U             /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
-#define  LPTIM_CFGR_TRGFLT_0                    0x00000040U             /*!< Bit 0 */
-#define  LPTIM_CFGR_TRGFLT_1                    0x00000080U             /*!< Bit 1 */
-
-#define  LPTIM_CFGR_PRESC                       0x00000E00U             /*!< PRESC[2:0] bits (Clock prescaler) */
-#define  LPTIM_CFGR_PRESC_0                     0x00000200U             /*!< Bit 0 */
-#define  LPTIM_CFGR_PRESC_1                     0x00000400U             /*!< Bit 1 */
-#define  LPTIM_CFGR_PRESC_2                     0x00000800U             /*!< Bit 2 */
-
-#define  LPTIM_CFGR_TRIGSEL                     0x0000E000U             /*!< TRIGSEL[2:0]] bits (Trigger selector) */
-#define  LPTIM_CFGR_TRIGSEL_0                   0x00002000U             /*!< Bit 0 */
-#define  LPTIM_CFGR_TRIGSEL_1                   0x00004000U             /*!< Bit 1 */
-#define  LPTIM_CFGR_TRIGSEL_2                   0x00008000U             /*!< Bit 2 */
-
-#define  LPTIM_CFGR_TRIGEN                      0x00060000U             /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
-#define  LPTIM_CFGR_TRIGEN_0                    0x00020000U             /*!< Bit 0 */
-#define  LPTIM_CFGR_TRIGEN_1                    0x00040000U             /*!< Bit 1 */
-
-#define  LPTIM_CFGR_TIMOUT                      0x00080000U             /*!< Timout enable           */
-#define  LPTIM_CFGR_WAVE                        0x00100000U             /*!< Waveform shape          */
-#define  LPTIM_CFGR_WAVPOL                      0x00200000U             /*!< Waveform shape polarity */
-#define  LPTIM_CFGR_PRELOAD                     0x00400000U             /*!< Reg update mode         */
-#define  LPTIM_CFGR_COUNTMODE                   0x00800000U             /*!< Counter mode enable     */
-#define  LPTIM_CFGR_ENC                         0x01000000U             /*!< Encoder mode enable     */
-
-/******************  Bit definition for LPTIM_CR register  ********************/
-#define  LPTIM_CR_ENABLE                        0x00000001U             /*!< LPTIMer enable                 */
-#define  LPTIM_CR_SNGSTRT                       0x00000002U             /*!< Timer start in single mode     */
-#define  LPTIM_CR_CNTSTRT                       0x00000004U             /*!< Timer start in continuous mode */
-
-/******************  Bit definition for LPTIM_CMP register  *******************/
-#define  LPTIM_CMP_CMP                          0x0000FFFFU             /*!< Compare register     */
-
-/******************  Bit definition for LPTIM_ARR register  *******************/
-#define  LPTIM_ARR_ARR                          0x0000FFFFU             /*!< Auto reload register */
-
-/******************  Bit definition for LPTIM_CNT register  *******************/
-#define  LPTIM_CNT_CNT                          0x0000FFFFU             /*!< Counter register     */
-
-/******************  Bit definition for LPTIM_OR register  *******************/
-#define  LPTIM_OR_OR                           0x00000003U               /*!< LPTIMER[1:0] bits (Remap selection) */
-#define  LPTIM_OR_OR_0                         0x00000001U               /*!< Bit 0 */
-#define  LPTIM_OR_OR_1                         0x00000002U               /*!< Bit 1 */
-
-/******************************************************************************/
-/*                                                                            */
-/*         Universal Synchronous Asynchronous Receiver Transmitter            */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         0x0001U            /*!<Parity Error                 */
-#define  USART_SR_FE                         0x0002U            /*!<Framing Error                */
-#define  USART_SR_NE                         0x0004U            /*!<Noise Error Flag             */
-#define  USART_SR_ORE                        0x0008U            /*!<OverRun Error                */
-#define  USART_SR_IDLE                       0x0010U            /*!<IDLE line detected           */
-#define  USART_SR_RXNE                       0x0020U            /*!<Read Data Register Not Empty */
-#define  USART_SR_TC                         0x0040U            /*!<Transmission Complete        */
-#define  USART_SR_TXE                        0x0080U            /*!<Transmit Data Register Empty */
-#define  USART_SR_LBD                        0x0100U            /*!<LIN Break Detection Flag     */
-#define  USART_SR_CTS                        0x0200U            /*!<CTS Flag                     */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         0x01FFU            /*!<Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_Fraction              0x000FU            /*!<Fraction of USARTDIV */
-#define  USART_BRR_DIV_Mantissa              0xFFF0U            /*!<Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       0x0001U            /*!<Send Break                             */
-#define  USART_CR1_RWU                       0x0002U            /*!<Receiver wakeup                        */
-#define  USART_CR1_RE                        0x0004U            /*!<Receiver Enable                        */
-#define  USART_CR1_TE                        0x0008U            /*!<Transmitter Enable                     */
-#define  USART_CR1_IDLEIE                    0x0010U            /*!<IDLE Interrupt Enable                  */
-#define  USART_CR1_RXNEIE                    0x0020U            /*!<RXNE Interrupt Enable                  */
-#define  USART_CR1_TCIE                      0x0040U            /*!<Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     0x0080U            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PEIE                      0x0100U            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PS                        0x0200U            /*!<Parity Selection                       */
-#define  USART_CR1_PCE                       0x0400U            /*!<Parity Control Enable                  */
-#define  USART_CR1_WAKE                      0x0800U            /*!<Wakeup method                          */
-#define  USART_CR1_M                         0x1000U            /*!<Word length                            */
-#define  USART_CR1_UE                        0x2000U            /*!<USART Enable                           */
-#define  USART_CR1_OVER8                     0x8000U            /*!<USART Oversampling by 8 enable         */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       0x000FU            /*!<Address of the USART node            */
-#define  USART_CR2_LBDL                      0x0020U            /*!<LIN Break Detection Length           */
-#define  USART_CR2_LBDIE                     0x0040U            /*!<LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      0x0100U            /*!<Last Bit Clock pulse                 */
-#define  USART_CR2_CPHA                      0x0200U            /*!<Clock Phase                          */
-#define  USART_CR2_CPOL                      0x0400U            /*!<Clock Polarity                       */
-#define  USART_CR2_CLKEN                     0x0800U            /*!<Clock Enable                         */
-
-#define  USART_CR2_STOP                      0x3000U            /*!<STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    0x1000U            /*!<Bit 0 */
-#define  USART_CR2_STOP_1                    0x2000U            /*!<Bit 1 */
-
-#define  USART_CR2_LINEN                     0x4000U            /*!<LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       0x0001U            /*!<Error Interrupt Enable      */
-#define  USART_CR3_IREN                      0x0002U            /*!<IrDA mode Enable            */
-#define  USART_CR3_IRLP                      0x0004U            /*!<IrDA Low-Power              */
-#define  USART_CR3_HDSEL                     0x0008U            /*!<Half-Duplex Selection       */
-#define  USART_CR3_NACK                      0x0010U            /*!<Smartcard NACK enable       */
-#define  USART_CR3_SCEN                      0x0020U            /*!<Smartcard mode enable       */
-#define  USART_CR3_DMAR                      0x0040U            /*!<DMA Enable Receiver         */
-#define  USART_CR3_DMAT                      0x0080U            /*!<DMA Enable Transmitter      */
-#define  USART_CR3_RTSE                      0x0100U            /*!<RTS Enable                  */
-#define  USART_CR3_CTSE                      0x0200U            /*!<CTS Enable                  */
-#define  USART_CR3_CTSIE                     0x0400U            /*!<CTS Interrupt Enable        */
-#define  USART_CR3_ONEBIT                    0x0800U            /*!<USART One bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      0x00FFU            /*!<PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    0x0001U            /*!<Bit 0 */
-#define  USART_GTPR_PSC_1                    0x0002U            /*!<Bit 1 */
-#define  USART_GTPR_PSC_2                    0x0004U            /*!<Bit 2 */
-#define  USART_GTPR_PSC_3                    0x0008U            /*!<Bit 3 */
-#define  USART_GTPR_PSC_4                    0x0010U            /*!<Bit 4 */
-#define  USART_GTPR_PSC_5                    0x0020U            /*!<Bit 5 */
-#define  USART_GTPR_PSC_6                    0x0040U            /*!<Bit 6 */
-#define  USART_GTPR_PSC_7                    0x0080U            /*!<Bit 7 */
-
-#define  USART_GTPR_GT                       0xFF00U            /*!<Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Window WATCHDOG                                 */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           0x7FU               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T_0                         0x01U               /*!<Bit 0 */
-#define  WWDG_CR_T_1                         0x02U               /*!<Bit 1 */
-#define  WWDG_CR_T_2                         0x04U               /*!<Bit 2 */
-#define  WWDG_CR_T_3                         0x08U               /*!<Bit 3 */
-#define  WWDG_CR_T_4                         0x10U               /*!<Bit 4 */
-#define  WWDG_CR_T_5                         0x20U               /*!<Bit 5 */
-#define  WWDG_CR_T_6                         0x40U               /*!<Bit 6 */
-/* Legacy defines */
-#define  WWDG_CR_T0                          WWDG_CR_T_0
-#define  WWDG_CR_T1                          WWDG_CR_T_1
-#define  WWDG_CR_T2                          WWDG_CR_T_2
-#define  WWDG_CR_T3                          WWDG_CR_T_3
-#define  WWDG_CR_T4                          WWDG_CR_T_4
-#define  WWDG_CR_T5                          WWDG_CR_T_5
-#define  WWDG_CR_T6                          WWDG_CR_T_6
-
-#define  WWDG_CR_WDGA                        0x80U               /*!<Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          0x007FU            /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W_0                        0x0001U            /*!<Bit 0 */
-#define  WWDG_CFR_W_1                        0x0002U            /*!<Bit 1 */
-#define  WWDG_CFR_W_2                        0x0004U            /*!<Bit 2 */
-#define  WWDG_CFR_W_3                        0x0008U            /*!<Bit 3 */
-#define  WWDG_CFR_W_4                        0x0010U            /*!<Bit 4 */
-#define  WWDG_CFR_W_5                        0x0020U            /*!<Bit 5 */
-#define  WWDG_CFR_W_6                        0x0040U            /*!<Bit 6 */
-/* Legacy defines */
-#define  WWDG_CFR_W0                         WWDG_CFR_W_0
-#define  WWDG_CFR_W1                         WWDG_CFR_W_1
-#define  WWDG_CFR_W2                         WWDG_CFR_W_2
-#define  WWDG_CFR_W3                         WWDG_CFR_W_3
-#define  WWDG_CFR_W4                         WWDG_CFR_W_4
-#define  WWDG_CFR_W5                         WWDG_CFR_W_5
-#define  WWDG_CFR_W6                         WWDG_CFR_W_6
-
-#define  WWDG_CFR_WDGTB                      0x0180U            /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB_0                    0x0080U            /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB_1                    0x0100U            /*!<Bit 1 */
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
-
-#define  WWDG_CFR_EWI                        0x0200U            /*!<Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        0x01U               /*!<Early Wakeup Interrupt Flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Digital to Analog Converter                           */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DAC_CR register  ********************/
-#define  DAC_CR_EN1                          0x00000001U        /*!<DAC channel1 enable */
-#define  DAC_CR_BOFF1                        0x00000002U        /*!<DAC channel1 output buffer disable */
-#define  DAC_CR_TEN1                         0x00000004U        /*!<DAC channel1 Trigger enable */
-
-#define  DAC_CR_TSEL1                        0x00000038U        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define  DAC_CR_TSEL1_0                      0x00000008U        /*!<Bit 0 */
-#define  DAC_CR_TSEL1_1                      0x00000010U        /*!<Bit 1 */
-#define  DAC_CR_TSEL1_2                      0x00000020U        /*!<Bit 2 */
-
-#define  DAC_CR_WAVE1                        0x000000C0U        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE1_0                      0x00000040U        /*!<Bit 0 */
-#define  DAC_CR_WAVE1_1                      0x00000080U        /*!<Bit 1 */
-
-#define  DAC_CR_MAMP1                        0x00000F00U        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP1_0                      0x00000100U        /*!<Bit 0 */
-#define  DAC_CR_MAMP1_1                      0x00000200U        /*!<Bit 1 */
-#define  DAC_CR_MAMP1_2                      0x00000400U        /*!<Bit 2 */
-#define  DAC_CR_MAMP1_3                      0x00000800U        /*!<Bit 3 */
-
-#define  DAC_CR_DMAEN1                       0x00001000U        /*!<DAC channel1 DMA enable */
-#define  DAC_CR_DMAUDRIE1                    0x00002000U        /*!<DAC channel1 DMA underrun interrupt enable*/
-#define  DAC_CR_EN2                          0x00010000U        /*!<DAC channel2 enable */
-#define  DAC_CR_BOFF2                        0x00020000U        /*!<DAC channel2 output buffer disable */
-#define  DAC_CR_TEN2                         0x00040000U        /*!<DAC channel2 Trigger enable */
-
-#define  DAC_CR_TSEL2                        0x00380000U        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define  DAC_CR_TSEL2_0                      0x00080000U        /*!<Bit 0 */
-#define  DAC_CR_TSEL2_1                      0x00100000U        /*!<Bit 1 */
-#define  DAC_CR_TSEL2_2                      0x00200000U        /*!<Bit 2 */
-
-#define  DAC_CR_WAVE2                        0x00C00000U        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE2_0                      0x00400000U        /*!<Bit 0 */
-#define  DAC_CR_WAVE2_1                      0x00800000U        /*!<Bit 1 */
-
-#define  DAC_CR_MAMP2                        0x0F000000U        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP2_0                      0x01000000U        /*!<Bit 0 */
-#define  DAC_CR_MAMP2_1                      0x02000000U        /*!<Bit 1 */
-#define  DAC_CR_MAMP2_2                      0x04000000U        /*!<Bit 2 */
-#define  DAC_CR_MAMP2_3                      0x08000000U        /*!<Bit 3 */
-
-#define  DAC_CR_DMAEN2                       0x10000000U        /*!<DAC channel2 DMA enabled */
-#define  DAC_CR_DMAUDRIE2                    0x20000000U        /*!<DAC channel2 DMA underrun interrupt enable*/
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define  DAC_SWTRIGR_SWTRIG1                 0x01U               /*!<DAC channel1 software trigger */
-#define  DAC_SWTRIGR_SWTRIG2                 0x02U               /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define  DAC_DHR12R1_DACC1DHR                0x0FFFU            /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define  DAC_DHR12L1_DACC1DHR                0xFFF0U            /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define  DAC_DHR8R1_DACC1DHR                 0xFFU               /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define  DAC_DHR12R2_DACC2DHR                0x0FFFU            /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define  DAC_DHR12L2_DACC2DHR                0xFFF0U            /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define  DAC_DHR8R2_DACC2DHR                 0xFFU               /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define  DAC_DHR12RD_DACC1DHR                0x00000FFFU        /*!<DAC channel1 12-bit Right aligned data */
-#define  DAC_DHR12RD_DACC2DHR                0x0FFF0000U        /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define  DAC_DHR12LD_DACC1DHR                0x0000FFF0U        /*!<DAC channel1 12-bit Left aligned data */
-#define  DAC_DHR12LD_DACC2DHR                0xFFF00000U        /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define  DAC_DHR8RD_DACC1DHR                 0x00FFU            /*!<DAC channel1 8-bit Right aligned data */
-#define  DAC_DHR8RD_DACC2DHR                 0xFF00U            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define  DAC_DOR1_DACC1DOR                   0x0FFFU            /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define  DAC_DOR2_DACC2DOR                   0x0FFFU            /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define  DAC_SR_DMAUDR1                      0x00002000U        /*!<DAC channel1 DMA underrun flag */
-#define  DAC_SR_DMAUDR2                      0x20000000U        /*!<DAC channel2 DMA underrun flag */
-/******************************************************************************/
-/*                                                                            */
-/*                                DBG                                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
-#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
-
-/********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
-#define  DBGMCU_CR_DBG_STOP                  0x00000002U
-#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
-#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
-
-#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
-#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U/*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U/*!<Bit 1 */
-
-/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
-
-/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        0x00000001U
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        0x00010000U
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       0x00040000U
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
- 
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
- 
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DAC Instances ********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/******************************** DMA Instances *******************************/
-#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
-                                              ((INSTANCE) == DMA1_Stream1) || \
-                                              ((INSTANCE) == DMA1_Stream2) || \
-                                              ((INSTANCE) == DMA1_Stream3) || \
-                                              ((INSTANCE) == DMA1_Stream4) || \
-                                              ((INSTANCE) == DMA1_Stream5) || \
-                                              ((INSTANCE) == DMA1_Stream6) || \
-                                              ((INSTANCE) == DMA1_Stream7) || \
-                                              ((INSTANCE) == DMA2_Stream0) || \
-                                              ((INSTANCE) == DMA2_Stream1) || \
-                                              ((INSTANCE) == DMA2_Stream2) || \
-                                              ((INSTANCE) == DMA2_Stream3) || \
-                                              ((INSTANCE) == DMA2_Stream4) || \
-                                              ((INSTANCE) == DMA2_Stream5) || \
-                                              ((INSTANCE) == DMA2_Stream6) || \
-                                              ((INSTANCE) == DMA2_Stream7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOH))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2)) 
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == SPI1)
-
-/******************************* LPTIM Instances ******************************/
-#define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
-
-/******************************* RNG Instances ********************************/
-#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
-/*************************** SPI Extended Instances ***************************/
-#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) ((INSTANCE) == SPI1)
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
-                                   ((INSTANCE) == TIM5)   || \
-                                   ((INSTANCE) == TIM6)   || \
-                                   ((INSTANCE) == TIM9)   || \
-                                   ((INSTANCE) == TIM11))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM9)  || \
-                                         ((INSTANCE) == TIM11))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM9))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM5))
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM5))
-
-/******************** TIM Instances : Advanced-control timers *****************/
-#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM5))
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM6))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM5))
-
-/************ TIM Instances : DMA requests generation (COMDE) *****************/
-#define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM5)) 
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                             ((INSTANCE) == TIM5))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM6) || \
-                                          ((INSTANCE) == TIM9))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM9))
-
-/********************** TIM Instances : 32 bit Counter ************************/
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM5))
-
-/***************** TIM Instances : external trigger input availabe ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                        ((INSTANCE) == TIM5))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM11))
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM1) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM5) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-/************ TIM Instances : complementary output(s) available ***************/
-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
-   ((((INSTANCE) == TIM1) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3))))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (0)
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2))     
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/***************************** FMPI2C Instances *******************************/
-#define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32F410Tx_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/cmsis/stm32f411xe.h b/stmhal/cmsis/stm32f411xe.h
deleted file mode 100644
index fd3c33629d..0000000000
--- a/stmhal/cmsis/stm32f411xe.h
+++ /dev/null
@@ -1,4830 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f411xe.h
-  * @author  MCD Application Team
-  * @version V2.5.1
-  * @date    28-June-2016
-  * @brief   CMSIS STM32F411xExx Device Peripheral Access Layer Header File. 
-  *
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - peripherals registers declarations and bits definition
-  *           - Macros to access peripheral’s registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f411xe
-  * @{
-  */
-    
-#ifndef __STM32F411xE_H
-#define __STM32F411xE_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-  
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-
-/**
-  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
-  */
-#define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */
-#define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */
-#define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1U       /*!< FPU present                                   */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32F4XX Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-typedef enum
-{
-/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
-  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
-/******  STM32 specific Interrupt Numbers **********************************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
-  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
-  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
-  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
-  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
-  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
-  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
-  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
-  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
-  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
-  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
-  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
-  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
-  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */  
-  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
-  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
-  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
-  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
-  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
-  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
-  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
-  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
-  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
-  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
-  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
-  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
-  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
-  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
-  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
-  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
-  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
-  SPI5_IRQn                   = 85      /*!< SPI5 global Interrupt                                             */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
-#include "system_stm32f4xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */      
-  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
-  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
-  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
-  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
-  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
-  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
-  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
-  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
-  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
-  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
-  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
-  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
-  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
-  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
-  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
-                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief CRC calculation unit 
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
-  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */
-  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
-  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
-  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
-} CRC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
-  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
-  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
-  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
-  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
-  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
-  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
-  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
-  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
-} DMA_Stream_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
-  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
-  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
-  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
-} DMA_TypeDef;
-
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
-  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
-  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
-  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
-  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
-  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-
-typedef struct
-{
-  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */
-  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */
-  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */
-  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */
-  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */
-  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief General Purpose I/O
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
-  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
-  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
-  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
-  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
-  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
-  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
-  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/** 
-  * @brief System configuration controller
-  */
-  
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */ 
-  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */
-  __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */
-  __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */
-  __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */
-  __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */
-  __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
-  __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
-  __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
-  __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
-  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
-  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
-  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
-  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
-  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
-  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
-  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
-  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
-  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
-  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
-  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
-  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
-  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
-  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
-  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
-  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
-  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
-  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
-  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
-  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
-  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
-  uint32_t      RESERVED7[1];  /*!< Reserved, 0x88                                                                    */
-  __IO uint32_t DCKCFGR;       /*!< RCC DCKCFGR configuration register,                          Address offset: 0x8C */
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-
-typedef struct
-{
-  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
-  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
-  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
-  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
-  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
-  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
-  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */
-  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
-  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */
-  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
-  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */
-  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */
-  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */
-  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */
-  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
-  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */
-  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
-  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
-  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
-  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
-  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
-  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
-  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
-  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
-  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
-  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
-  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
-  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
-  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
-  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
-  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
-  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
-  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
-  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
-  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
-  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
-  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
-} RTC_TypeDef;
-
-
-/** 
-  * @brief SD host Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t POWER;          /*!< SDIO power control register,    Address offset: 0x00 */
-  __IO uint32_t CLKCR;          /*!< SDI clock control register,     Address offset: 0x04 */
-  __IO uint32_t ARG;            /*!< SDIO argument register,         Address offset: 0x08 */
-  __IO uint32_t CMD;            /*!< SDIO command register,          Address offset: 0x0C */
-  __I uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */
-  __I uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */
-  __I uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */
-  __I uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */
-  __I uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */
-  __IO uint32_t DTIMER;         /*!< SDIO data timer register,       Address offset: 0x24 */
-  __IO uint32_t DLEN;           /*!< SDIO data length register,      Address offset: 0x28 */
-  __IO uint32_t DCTRL;          /*!< SDIO data control register,     Address offset: 0x2C */
-  __I uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */
-  __I uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */
-  __IO uint32_t ICR;            /*!< SDIO interrupt clear register,  Address offset: 0x38 */
-  __IO uint32_t MASK;           /*!< SDIO mask register,             Address offset: 0x3C */
-  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
-  __I uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */
-  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
-  __IO uint32_t FIFO;           /*!< SDIO data FIFO register,        Address offset: 0x80 */
-} SDIO_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
-  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
-  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
-  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-
-/** 
-  * @brief __USB_OTG_Core_register
-  */
-typedef struct
-{
-  __IO uint32_t GOTGCTL;              /*!<  USB_OTG Control and Status Register    Address offset : 0x00      */
-  __IO uint32_t GOTGINT;              /*!<  USB_OTG Interrupt Register             Address offset : 0x04      */
-  __IO uint32_t GAHBCFG;              /*!<  Core AHB Configuration Register        Address offset : 0x08      */
-  __IO uint32_t GUSBCFG;              /*!<  Core USB Configuration Register        Address offset : 0x0C      */
-  __IO uint32_t GRSTCTL;              /*!<  Core Reset Register                    Address offset : 0x10      */
-  __IO uint32_t GINTSTS;              /*!<  Core Interrupt Register                Address offset : 0x14      */
-  __IO uint32_t GINTMSK;              /*!<  Core Interrupt Mask Register           Address offset : 0x18      */
-  __IO uint32_t GRXSTSR;              /*!<  Receive Sts Q Read Register            Address offset : 0x1C      */
-  __IO uint32_t GRXSTSP;              /*!<  Receive Sts Q Read & POP Register      Address offset : 0x20      */
-  __IO uint32_t GRXFSIZ;              /* Receive FIFO Size Register                Address offset : 0x24      */
-  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!<  EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28    */
-  __IO uint32_t HNPTXSTS;             /*!<  Non Periodic Tx FIFO/Queue Sts reg     Address offset : 0x2C      */
-  uint32_t Reserved30[2];             /* Reserved                                  Address offset : 0x30      */
-  __IO uint32_t GCCFG;                /*!<  General Purpose IO Register            Address offset : 0x38      */
-  __IO uint32_t CID;                  /*!< User ID Register                          Address offset : 0x3C      */
-  uint32_t  Reserved40[48];           /*!< Reserved                                  Address offset : 0x40-0xFF */
-  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg            Address offset : 0x100 */
-  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */
-}
-USB_OTG_GlobalTypeDef;
-
-
-
-/** 
-  * @brief __device_Registers
-  */
-typedef struct 
-{
-  __IO uint32_t DCFG;         /*!< dev Configuration Register   Address offset : 0x800 */
-  __IO uint32_t DCTL;         /*!< dev Control Register         Address offset : 0x804 */
-  __IO uint32_t DSTS;         /*!< dev Status Register (RO)     Address offset : 0x808 */
-  uint32_t Reserved0C;        /*!< Reserved                     Address offset : 0x80C */
-  __IO uint32_t DIEPMSK;      /* !< dev IN Endpoint Mask        Address offset : 0x810 */
-  __IO uint32_t DOEPMSK;      /*!< dev OUT Endpoint Mask        Address offset : 0x814 */
-  __IO uint32_t DAINT;        /*!< dev All Endpoints Itr Reg    Address offset : 0x818 */
-  __IO uint32_t DAINTMSK;     /*!< dev All Endpoints Itr Mask   Address offset : 0x81C */
-  uint32_t  Reserved20;       /*!< Reserved                     Address offset : 0x820 */
-  uint32_t Reserved9;         /*!< Reserved                     Address offset : 0x824 */
-  __IO uint32_t DVBUSDIS;     /*!< dev VBUS discharge Register  Address offset : 0x828 */
-  __IO uint32_t DVBUSPULSE;   /*!< dev VBUS Pulse Register      Address offset : 0x82C */
-  __IO uint32_t DTHRCTL;      /*!< dev thr                      Address offset : 0x830 */
-  __IO uint32_t DIEPEMPMSK;   /*!< dev empty msk                Address offset : 0x834 */
-  __IO uint32_t DEACHINT;     /*!< dedicated EP interrupt       Address offset : 0x838 */
-  __IO uint32_t DEACHMSK;     /*!< dedicated EP msk             Address offset : 0x83C */  
-  uint32_t Reserved40;        /*!< dedicated EP mask            Address offset : 0x840 */
-  __IO uint32_t DINEP1MSK;    /*!< dedicated EP mask            Address offset : 0x844 */
-  uint32_t  Reserved44[15];   /*!< Reserved                     Address offset : 0x844-0x87C */
-  __IO uint32_t DOUTEP1MSK;   /*!< dedicated EP msk             Address offset : 0x884 */   
-}
-USB_OTG_DeviceTypeDef;
-
-
-/** 
-  * @brief __IN_Endpoint-Specific_Register
-  */
-typedef struct 
-{
-  __IO uint32_t DIEPCTL;        /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h     */
-  uint32_t Reserved04;          /* Reserved                       900h + (ep_num * 20h) + 04h  */
-  __IO uint32_t DIEPINT;        /* dev IN Endpoint Itr Reg     900h + (ep_num * 20h) + 08h     */
-  uint32_t Reserved0C;          /* Reserved                       900h + (ep_num * 20h) + 0Ch  */
-  __IO uint32_t DIEPTSIZ;       /* IN Endpoint Txfer Size   900h + (ep_num * 20h) + 10h        */
-  __IO uint32_t DIEPDMA;        /* IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h  */
-  __IO uint32_t DTXFSTS;        /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h   */
-  uint32_t Reserved18;           /* Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
-}
-USB_OTG_INEndpointTypeDef;
-
-
-/** 
-  * @brief __OUT_Endpoint-Specific_Registers
-  */
-typedef struct 
-{
-  __IO uint32_t DOEPCTL;       /* dev OUT Endpoint Control Reg  B00h + (ep_num * 20h) + 00h*/
-  uint32_t Reserved04;         /* Reserved                      B00h + (ep_num * 20h) + 04h*/
-  __IO uint32_t DOEPINT;       /* dev OUT Endpoint Itr Reg      B00h + (ep_num * 20h) + 08h*/
-  uint32_t Reserved0C;         /* Reserved                      B00h + (ep_num * 20h) + 0Ch*/
-  __IO uint32_t DOEPTSIZ;      /* dev OUT Endpoint Txfer Size   B00h + (ep_num * 20h) + 10h*/
-  __IO uint32_t DOEPDMA;       /* dev OUT Endpoint DMA Address  B00h + (ep_num * 20h) + 14h*/
-  uint32_t Reserved18[2];      /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
-}
-USB_OTG_OUTEndpointTypeDef;
-
-
-/** 
-  * @brief __Host_Mode_Register_Structures
-  */
-typedef struct 
-{
-  __IO uint32_t HCFG;             /* Host Configuration Register    400h*/
-  __IO uint32_t HFIR;             /* Host Frame Interval Register   404h*/
-  __IO uint32_t HFNUM;            /* Host Frame Nbr/Frame Remaining 408h*/
-  uint32_t Reserved40C;           /* Reserved                       40Ch*/
-  __IO uint32_t HPTXSTS;          /* Host Periodic Tx FIFO/ Queue Status 410h*/
-  __IO uint32_t HAINT;            /* Host All Channels Interrupt Register 414h*/
-  __IO uint32_t HAINTMSK;         /* Host All Channels Interrupt Mask 418h*/
-}
-USB_OTG_HostTypeDef;
-
-
-/** 
-  * @brief __Host_Channel_Specific_Registers
-  */
-typedef struct
-{
-  __IO uint32_t HCCHAR;
-  __IO uint32_t HCSPLT;
-  __IO uint32_t HCINT;
-  __IO uint32_t HCINTMSK;
-  __IO uint32_t HCTSIZ;
-  __IO uint32_t HCDMA;
-  uint32_t Reserved[2];
-}
-USB_OTG_HostChannelTypeDef;
-
-    
-/** 
-  * @brief Peripheral_memory_map
-  */
-#define FLASH_BASE            0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region                         */
-#define SRAM1_BASE            0x20000000U /*!< SRAM1(128 KB) base address in the alias region                             */
-#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region                                */
-#define BKPSRAM_BASE          0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region                         */
-#define SRAM1_BB_BASE         0x22000000U /*!< SRAM1(128 KB) base address in the bit-band region                          */
-#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region                             */
-#define BKPSRAM_BB_BASE       0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region                      */
-#define FLASH_END             0x0807FFFFU /*!< FLASH end address */
-
-/* Legacy defines */
-#define SRAM_BASE             SRAM1_BASE
-#define SRAM_BB_BASE          SRAM1_BB_BASE
-
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000U)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)
-#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400U)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)
-#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000U)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)
-#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)
-
-/*!< APB2 peripherals */
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000U)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x1000U)
-#define USART6_BASE           (APB2PERIPH_BASE + 0x1400U)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000U)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x2300U)
-#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00U)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)
-#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400U)
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800U)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00U)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000U)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400U)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800U)
-#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000U)
-
-/*!< AHB1 peripherals */
-#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000U)
-#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400U)
-#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800U)
-#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00U)
-#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000U)
-#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00U)
-#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)
-#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800U)
-#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00U)
-#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000U)
-#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010U)
-#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028U)
-#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040U)
-#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058U)
-#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070U)
-#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088U)
-#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0U)
-#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8U)
-#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400U)
-#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010U)
-#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028U)
-#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040U)
-#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058U)
-#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070U)
-#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088U)
-#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0U)
-#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)
-
-/* Debug MCU registers base address */
-#define DBGMCU_BASE           0xE0042000U
-
-/*!< USB registers base address */
-#define USB_OTG_FS_PERIPH_BASE               0x50000000U
-
-#define USB_OTG_GLOBAL_BASE                  0x000U
-#define USB_OTG_DEVICE_BASE                  0x800U
-#define USB_OTG_IN_ENDPOINT_BASE             0x900U
-#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U
-#define USB_OTG_EP_REG_SIZE                  0x20U
-#define USB_OTG_HOST_BASE                    0x400U
-#define USB_OTG_HOST_PORT_BASE               0x440U
-#define USB_OTG_HOST_CHANNEL_BASE            0x500U
-#define USB_OTG_HOST_CHANNEL_SIZE            0x20U
-#define USB_OTG_PCGCCTL_BASE                 0xE00U
-#define USB_OTG_FIFO_BASE                    0x1000U
-#define USB_OTG_FIFO_SIZE                    0x1000U
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define USART6              ((USART_TypeDef *) USART6_BASE)
-#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define SPI4                ((SPI_TypeDef *) SPI4_BASE) 
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-#define SPI5                ((SPI_TypeDef *) SPI5_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
-#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
-#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
-#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
-#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
-#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
-#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
-#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
-#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
-#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
-#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
-#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
-#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
-#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
-#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
-
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers_Bits_Definition               */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Analog to Digital Converter                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          0x00000001U       /*!<Analog watchdog flag */
-#define  ADC_SR_EOC                          0x00000002U       /*!<End of conversion */
-#define  ADC_SR_JEOC                         0x00000004U       /*!<Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        0x00000008U       /*!<Injected channel Start flag */
-#define  ADC_SR_STRT                         0x00000010U       /*!<Regular channel Start flag */
-#define  ADC_SR_OVR                          0x00000020U       /*!<Overrun flag */
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
-#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels */
-#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels */
-#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution) */
-#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
-  
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion */
-#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode */
-#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC) */
-#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection */
-#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment */
-#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      0xFFFFU            /*!<Injected data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag */
-#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion */
-#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag */
-#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag */
-#define  ADC_CSR_OVR1                        0x00000020U        /*!<ADC1 DMA overrun  flag */
-#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag */
-#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion */
-#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag */
-#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag */
-#define  ADC_CSR_OVR2                        0x00002000U        /*!<ADC2 DMA overrun  flag */
-#define  ADC_CSR_AWD3                        0x00010000U        /*!<ADC3 Analog watchdog flag */
-#define  ADC_CSR_EOC3                        0x00020000U        /*!<ADC3 End of conversion */
-#define  ADC_CSR_JEOC3                       0x00040000U        /*!<ADC3 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT3                      0x00080000U        /*!<ADC3 Injected channel Start flag */
-#define  ADC_CSR_STRT3                       0x00100000U        /*!<ADC3 Regular channel Start flag */
-#define  ADC_CSR_OVR3                        0x00200000U        /*!<ADC3 DMA overrun  flag */
-
-/* Legacy defines */
-#define  ADC_CSR_DOVR1                        ADC_CSR_OVR1
-#define  ADC_CSR_DOVR2                        ADC_CSR_OVR2
-#define  ADC_CSR_DOVR3                        ADC_CSR_OVR3
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
-#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
-#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
-#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
-#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
-
-/*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                      0x0000FFFFU         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                      0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRC calculation unit                              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           0xFFFFFFFFU /*!< Data register bits */
-
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         0xFFU        /*!< General-purpose 8-bit data register bits */
-
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        0x01U        /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 Debug MCU                                  */
-/*                                                                            */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                             DMA Controller                                 */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DMA_SxCR register  *****************/
-#define DMA_SxCR_CHSEL                       0x0E000000U
-#define DMA_SxCR_CHSEL_0                     0x02000000U
-#define DMA_SxCR_CHSEL_1                     0x04000000U
-#define DMA_SxCR_CHSEL_2                     0x08000000U
-#define DMA_SxCR_MBURST                      0x01800000U
-#define DMA_SxCR_MBURST_0                    0x00800000U
-#define DMA_SxCR_MBURST_1                    0x01000000U
-#define DMA_SxCR_PBURST                      0x00600000U
-#define DMA_SxCR_PBURST_0                    0x00200000U
-#define DMA_SxCR_PBURST_1                    0x00400000U
-#define DMA_SxCR_CT                          0x00080000U
-#define DMA_SxCR_DBM                         0x00040000U
-#define DMA_SxCR_PL                          0x00030000U
-#define DMA_SxCR_PL_0                        0x00010000U
-#define DMA_SxCR_PL_1                        0x00020000U
-#define DMA_SxCR_PINCOS                      0x00008000U
-#define DMA_SxCR_MSIZE                       0x00006000U
-#define DMA_SxCR_MSIZE_0                     0x00002000U
-#define DMA_SxCR_MSIZE_1                     0x00004000U
-#define DMA_SxCR_PSIZE                       0x00001800U
-#define DMA_SxCR_PSIZE_0                     0x00000800U
-#define DMA_SxCR_PSIZE_1                     0x00001000U
-#define DMA_SxCR_MINC                        0x00000400U
-#define DMA_SxCR_PINC                        0x00000200U
-#define DMA_SxCR_CIRC                        0x00000100U
-#define DMA_SxCR_DIR                         0x000000C0U
-#define DMA_SxCR_DIR_0                       0x00000040U
-#define DMA_SxCR_DIR_1                       0x00000080U
-#define DMA_SxCR_PFCTRL                      0x00000020U
-#define DMA_SxCR_TCIE                        0x00000010U
-#define DMA_SxCR_HTIE                        0x00000008U
-#define DMA_SxCR_TEIE                        0x00000004U
-#define DMA_SxCR_DMEIE                       0x00000002U
-#define DMA_SxCR_EN                          0x00000001U
-
-/* Legacy defines */
-#define DMA_SxCR_ACK                         0x00100000U
-
-/********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            0x0000FFFFU
-#define DMA_SxNDT_0                          0x00000001U
-#define DMA_SxNDT_1                          0x00000002U
-#define DMA_SxNDT_2                          0x00000004U
-#define DMA_SxNDT_3                          0x00000008U
-#define DMA_SxNDT_4                          0x00000010U
-#define DMA_SxNDT_5                          0x00000020U
-#define DMA_SxNDT_6                          0x00000040U
-#define DMA_SxNDT_7                          0x00000080U
-#define DMA_SxNDT_8                          0x00000100U
-#define DMA_SxNDT_9                          0x00000200U
-#define DMA_SxNDT_10                         0x00000400U
-#define DMA_SxNDT_11                         0x00000800U
-#define DMA_SxNDT_12                         0x00001000U
-#define DMA_SxNDT_13                         0x00002000U
-#define DMA_SxNDT_14                         0x00004000U
-#define DMA_SxNDT_15                         0x00008000U
-
-/********************  Bits definition for DMA_SxFCR register  ****************/ 
-#define DMA_SxFCR_FEIE                       0x00000080U
-#define DMA_SxFCR_FS                         0x00000038U
-#define DMA_SxFCR_FS_0                       0x00000008U
-#define DMA_SxFCR_FS_1                       0x00000010U
-#define DMA_SxFCR_FS_2                       0x00000020U
-#define DMA_SxFCR_DMDIS                      0x00000004U
-#define DMA_SxFCR_FTH                        0x00000003U
-#define DMA_SxFCR_FTH_0                      0x00000001U
-#define DMA_SxFCR_FTH_1                      0x00000002U
-
-/********************  Bits definition for DMA_LISR register  *****************/ 
-#define DMA_LISR_TCIF3                       0x08000000U
-#define DMA_LISR_HTIF3                       0x04000000U
-#define DMA_LISR_TEIF3                       0x02000000U
-#define DMA_LISR_DMEIF3                      0x01000000U
-#define DMA_LISR_FEIF3                       0x00400000U
-#define DMA_LISR_TCIF2                       0x00200000U
-#define DMA_LISR_HTIF2                       0x00100000U
-#define DMA_LISR_TEIF2                       0x00080000U
-#define DMA_LISR_DMEIF2                      0x00040000U
-#define DMA_LISR_FEIF2                       0x00010000U
-#define DMA_LISR_TCIF1                       0x00000800U
-#define DMA_LISR_HTIF1                       0x00000400U
-#define DMA_LISR_TEIF1                       0x00000200U
-#define DMA_LISR_DMEIF1                      0x00000100U
-#define DMA_LISR_FEIF1                       0x00000040U
-#define DMA_LISR_TCIF0                       0x00000020U
-#define DMA_LISR_HTIF0                       0x00000010U
-#define DMA_LISR_TEIF0                       0x00000008U
-#define DMA_LISR_DMEIF0                      0x00000004U
-#define DMA_LISR_FEIF0                       0x00000001U
-
-/********************  Bits definition for DMA_HISR register  *****************/ 
-#define DMA_HISR_TCIF7                       0x08000000U
-#define DMA_HISR_HTIF7                       0x04000000U
-#define DMA_HISR_TEIF7                       0x02000000U
-#define DMA_HISR_DMEIF7                      0x01000000U
-#define DMA_HISR_FEIF7                       0x00400000U
-#define DMA_HISR_TCIF6                       0x00200000U
-#define DMA_HISR_HTIF6                       0x00100000U
-#define DMA_HISR_TEIF6                       0x00080000U
-#define DMA_HISR_DMEIF6                      0x00040000U
-#define DMA_HISR_FEIF6                       0x00010000U
-#define DMA_HISR_TCIF5                       0x00000800U
-#define DMA_HISR_HTIF5                       0x00000400U
-#define DMA_HISR_TEIF5                       0x00000200U
-#define DMA_HISR_DMEIF5                      0x00000100U
-#define DMA_HISR_FEIF5                       0x00000040U
-#define DMA_HISR_TCIF4                       0x00000020U
-#define DMA_HISR_HTIF4                       0x00000010U
-#define DMA_HISR_TEIF4                       0x00000008U
-#define DMA_HISR_DMEIF4                      0x00000004U
-#define DMA_HISR_FEIF4                       0x00000001U
-
-/********************  Bits definition for DMA_LIFCR register  ****************/ 
-#define DMA_LIFCR_CTCIF3                     0x08000000U
-#define DMA_LIFCR_CHTIF3                     0x04000000U
-#define DMA_LIFCR_CTEIF3                     0x02000000U
-#define DMA_LIFCR_CDMEIF3                    0x01000000U
-#define DMA_LIFCR_CFEIF3                     0x00400000U
-#define DMA_LIFCR_CTCIF2                     0x00200000U
-#define DMA_LIFCR_CHTIF2                     0x00100000U
-#define DMA_LIFCR_CTEIF2                     0x00080000U
-#define DMA_LIFCR_CDMEIF2                    0x00040000U
-#define DMA_LIFCR_CFEIF2                     0x00010000U
-#define DMA_LIFCR_CTCIF1                     0x00000800U
-#define DMA_LIFCR_CHTIF1                     0x00000400U
-#define DMA_LIFCR_CTEIF1                     0x00000200U
-#define DMA_LIFCR_CDMEIF1                    0x00000100U
-#define DMA_LIFCR_CFEIF1                     0x00000040U
-#define DMA_LIFCR_CTCIF0                     0x00000020U
-#define DMA_LIFCR_CHTIF0                     0x00000010U
-#define DMA_LIFCR_CTEIF0                     0x00000008U
-#define DMA_LIFCR_CDMEIF0                    0x00000004U
-#define DMA_LIFCR_CFEIF0                     0x00000001U
-
-/********************  Bits definition for DMA_HIFCR  register  ****************/ 
-#define DMA_HIFCR_CTCIF7                     0x08000000U
-#define DMA_HIFCR_CHTIF7                     0x04000000U
-#define DMA_HIFCR_CTEIF7                     0x02000000U
-#define DMA_HIFCR_CDMEIF7                    0x01000000U
-#define DMA_HIFCR_CFEIF7                     0x00400000U
-#define DMA_HIFCR_CTCIF6                     0x00200000U
-#define DMA_HIFCR_CHTIF6                     0x00100000U
-#define DMA_HIFCR_CTEIF6                     0x00080000U
-#define DMA_HIFCR_CDMEIF6                    0x00040000U
-#define DMA_HIFCR_CFEIF6                     0x00010000U
-#define DMA_HIFCR_CTCIF5                     0x00000800U
-#define DMA_HIFCR_CHTIF5                     0x00000400U
-#define DMA_HIFCR_CTEIF5                     0x00000200U
-#define DMA_HIFCR_CDMEIF5                    0x00000100U
-#define DMA_HIFCR_CFEIF5                     0x00000040U
-#define DMA_HIFCR_CTCIF4                     0x00000020U
-#define DMA_HIFCR_CHTIF4                     0x00000010U
-#define DMA_HIFCR_CTEIF4                     0x00000008U
-#define DMA_HIFCR_CDMEIF4                    0x00000004U
-#define DMA_HIFCR_CFEIF4                     0x00000001U
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                    External Interrupt/Event Controller                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    FLASH                                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    0x0000000FU
-#define FLASH_ACR_LATENCY_0WS                0x00000000U
-#define FLASH_ACR_LATENCY_1WS                0x00000001U
-#define FLASH_ACR_LATENCY_2WS                0x00000002U
-#define FLASH_ACR_LATENCY_3WS                0x00000003U
-#define FLASH_ACR_LATENCY_4WS                0x00000004U
-#define FLASH_ACR_LATENCY_5WS                0x00000005U
-#define FLASH_ACR_LATENCY_6WS                0x00000006U
-#define FLASH_ACR_LATENCY_7WS                0x00000007U
-
-#define FLASH_ACR_PRFTEN                     0x00000100U
-#define FLASH_ACR_ICEN                       0x00000200U
-#define FLASH_ACR_DCEN                       0x00000400U
-#define FLASH_ACR_ICRST                      0x00000800U
-#define FLASH_ACR_DCRST                      0x00001000U
-#define FLASH_ACR_BYTE0_ADDRESS              0x40023C00U
-#define FLASH_ACR_BYTE2_ADDRESS              0x40023C03U
-
-/*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         0x00000001U
-#define FLASH_SR_SOP                         0x00000002U
-#define FLASH_SR_WRPERR                      0x00000010U
-#define FLASH_SR_PGAERR                      0x00000020U
-#define FLASH_SR_PGPERR                      0x00000040U
-#define FLASH_SR_PGSERR                      0x00000080U
-#define FLASH_SR_BSY                         0x00010000U
-
-/*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          0x00000001U
-#define FLASH_CR_SER                         0x00000002U
-#define FLASH_CR_MER                         0x00000004U
-#define FLASH_CR_SNB                         0x000000F8U
-#define FLASH_CR_SNB_0                       0x00000008U
-#define FLASH_CR_SNB_1                       0x00000010U
-#define FLASH_CR_SNB_2                       0x00000020U
-#define FLASH_CR_SNB_3                       0x00000040U
-#define FLASH_CR_SNB_4                       0x00000080U
-#define FLASH_CR_PSIZE                       0x00000300U
-#define FLASH_CR_PSIZE_0                     0x00000100U
-#define FLASH_CR_PSIZE_1                     0x00000200U
-#define FLASH_CR_STRT                        0x00010000U
-#define FLASH_CR_EOPIE                       0x01000000U
-#define FLASH_CR_LOCK                        0x80000000U
-
-/*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                 0x00000001U
-#define FLASH_OPTCR_OPTSTRT                 0x00000002U
-#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
-#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
-#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
-
-#define FLASH_OPTCR_WDG_SW                  0x00000020U
-#define FLASH_OPTCR_nRST_STOP               0x00000040U
-#define FLASH_OPTCR_nRST_STDBY              0x00000080U
-#define FLASH_OPTCR_RDP                     0x0000FF00U
-#define FLASH_OPTCR_RDP_0                   0x00000100U
-#define FLASH_OPTCR_RDP_1                   0x00000200U
-#define FLASH_OPTCR_RDP_2                   0x00000400U
-#define FLASH_OPTCR_RDP_3                   0x00000800U
-#define FLASH_OPTCR_RDP_4                   0x00001000U
-#define FLASH_OPTCR_RDP_5                   0x00002000U
-#define FLASH_OPTCR_RDP_6                   0x00004000U
-#define FLASH_OPTCR_RDP_7                   0x00008000U
-#define FLASH_OPTCR_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR_nWRP_0                  0x00010000U
-#define FLASH_OPTCR_nWRP_1                  0x00020000U
-#define FLASH_OPTCR_nWRP_2                  0x00040000U
-#define FLASH_OPTCR_nWRP_3                  0x00080000U
-#define FLASH_OPTCR_nWRP_4                  0x00100000U
-#define FLASH_OPTCR_nWRP_5                  0x00200000U
-#define FLASH_OPTCR_nWRP_6                  0x00400000U
-#define FLASH_OPTCR_nWRP_7                  0x00800000U
-#define FLASH_OPTCR_nWRP_8                  0x01000000U
-#define FLASH_OPTCR_nWRP_9                  0x02000000U
-#define FLASH_OPTCR_nWRP_10                 0x04000000U
-#define FLASH_OPTCR_nWRP_11                 0x08000000U
-                                             
-/******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR1_nWRP_0                  0x00010000U
-#define FLASH_OPTCR1_nWRP_1                  0x00020000U
-#define FLASH_OPTCR1_nWRP_2                  0x00040000U
-#define FLASH_OPTCR1_nWRP_3                  0x00080000U
-#define FLASH_OPTCR1_nWRP_4                  0x00100000U
-#define FLASH_OPTCR1_nWRP_5                  0x00200000U
-#define FLASH_OPTCR1_nWRP_6                  0x00400000U
-#define FLASH_OPTCR1_nWRP_7                  0x00800000U
-#define FLASH_OPTCR1_nWRP_8                  0x01000000U
-#define FLASH_OPTCR1_nWRP_9                  0x02000000U
-#define FLASH_OPTCR1_nWRP_10                 0x04000000U
-#define FLASH_OPTCR1_nWRP_11                 0x08000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    0x00000003U
-#define GPIO_MODER_MODER0_0                  0x00000001U
-#define GPIO_MODER_MODER0_1                  0x00000002U
-
-#define GPIO_MODER_MODER1                    0x0000000CU
-#define GPIO_MODER_MODER1_0                  0x00000004U
-#define GPIO_MODER_MODER1_1                  0x00000008U
-
-#define GPIO_MODER_MODER2                    0x00000030U
-#define GPIO_MODER_MODER2_0                  0x00000010U
-#define GPIO_MODER_MODER2_1                  0x00000020U
-
-#define GPIO_MODER_MODER3                    0x000000C0U
-#define GPIO_MODER_MODER3_0                  0x00000040U
-#define GPIO_MODER_MODER3_1                  0x00000080U
-
-#define GPIO_MODER_MODER4                    0x00000300U
-#define GPIO_MODER_MODER4_0                  0x00000100U
-#define GPIO_MODER_MODER4_1                  0x00000200U
-
-#define GPIO_MODER_MODER5                    0x00000C00U
-#define GPIO_MODER_MODER5_0                  0x00000400U
-#define GPIO_MODER_MODER5_1                  0x00000800U
-
-#define GPIO_MODER_MODER6                    0x00003000U
-#define GPIO_MODER_MODER6_0                  0x00001000U
-#define GPIO_MODER_MODER6_1                  0x00002000U
-
-#define GPIO_MODER_MODER7                    0x0000C000U
-#define GPIO_MODER_MODER7_0                  0x00004000U
-#define GPIO_MODER_MODER7_1                  0x00008000U
-
-#define GPIO_MODER_MODER8                    0x00030000U
-#define GPIO_MODER_MODER8_0                  0x00010000U
-#define GPIO_MODER_MODER8_1                  0x00020000U
-
-#define GPIO_MODER_MODER9                    0x000C0000U
-#define GPIO_MODER_MODER9_0                  0x00040000U
-#define GPIO_MODER_MODER9_1                  0x00080000U
-
-#define GPIO_MODER_MODER10                   0x00300000U
-#define GPIO_MODER_MODER10_0                 0x00100000U
-#define GPIO_MODER_MODER10_1                 0x00200000U
-
-#define GPIO_MODER_MODER11                   0x00C00000U
-#define GPIO_MODER_MODER11_0                 0x00400000U
-#define GPIO_MODER_MODER11_1                 0x00800000U
-
-#define GPIO_MODER_MODER12                   0x03000000U
-#define GPIO_MODER_MODER12_0                 0x01000000U
-#define GPIO_MODER_MODER12_1                 0x02000000U
-
-#define GPIO_MODER_MODER13                   0x0C000000U
-#define GPIO_MODER_MODER13_0                 0x04000000U
-#define GPIO_MODER_MODER13_1                 0x08000000U
-
-#define GPIO_MODER_MODER14                   0x30000000U
-#define GPIO_MODER_MODER14_0                 0x10000000U
-#define GPIO_MODER_MODER14_1                 0x20000000U
-
-#define GPIO_MODER_MODER15                   0xC0000000U
-#define GPIO_MODER_MODER15_0                 0x40000000U
-#define GPIO_MODER_MODER15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     0x00000001U
-#define GPIO_OTYPER_OT_1                     0x00000002U
-#define GPIO_OTYPER_OT_2                     0x00000004U
-#define GPIO_OTYPER_OT_3                     0x00000008U
-#define GPIO_OTYPER_OT_4                     0x00000010U
-#define GPIO_OTYPER_OT_5                     0x00000020U
-#define GPIO_OTYPER_OT_6                     0x00000040U
-#define GPIO_OTYPER_OT_7                     0x00000080U
-#define GPIO_OTYPER_OT_8                     0x00000100U
-#define GPIO_OTYPER_OT_9                     0x00000200U
-#define GPIO_OTYPER_OT_10                    0x00000400U
-#define GPIO_OTYPER_OT_11                    0x00000800U
-#define GPIO_OTYPER_OT_12                    0x00001000U
-#define GPIO_OTYPER_OT_13                    0x00002000U
-#define GPIO_OTYPER_OT_14                    0x00004000U
-#define GPIO_OTYPER_OT_15                    0x00008000U
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
-#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
-#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
-
-#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
-#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
-#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
-
-#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
-#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
-#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
-
-#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
-#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
-#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
-
-#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
-#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
-#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
-
-#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
-#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
-#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
-
-#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
-#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
-#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
-
-#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
-#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
-#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
-
-#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
-#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
-#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
-
-#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
-#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
-#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
-
-#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
-#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
-#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
-
-#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
-#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
-#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
-
-#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
-#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
-#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
-
-#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
-#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
-#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
-
-#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
-#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
-#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
-
-#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
-#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
-#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    0x00000003U
-#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
-#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
-
-#define GPIO_PUPDR_PUPDR1                    0x0000000CU
-#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
-#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
-
-#define GPIO_PUPDR_PUPDR2                    0x00000030U
-#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
-#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
-
-#define GPIO_PUPDR_PUPDR3                    0x000000C0U
-#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
-#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
-
-#define GPIO_PUPDR_PUPDR4                    0x00000300U
-#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
-#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
-
-#define GPIO_PUPDR_PUPDR5                    0x00000C00U
-#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
-#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
-
-#define GPIO_PUPDR_PUPDR6                    0x00003000U
-#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
-#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
-
-#define GPIO_PUPDR_PUPDR7                    0x0000C000U
-#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
-#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
-
-#define GPIO_PUPDR_PUPDR8                    0x00030000U
-#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
-#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
-
-#define GPIO_PUPDR_PUPDR9                    0x000C0000U
-#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
-#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
-
-#define GPIO_PUPDR_PUPDR10                   0x00300000U
-#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
-#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
-
-#define GPIO_PUPDR_PUPDR11                   0x00C00000U
-#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
-#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
-
-#define GPIO_PUPDR_PUPDR12                   0x03000000U
-#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
-#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
-
-#define GPIO_PUPDR_PUPDR13                   0x0C000000U
-#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
-#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
-
-#define GPIO_PUPDR_PUPDR14                   0x30000000U
-#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
-#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
-
-#define GPIO_PUPDR_PUPDR15                   0xC0000000U
-#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
-#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       0x00000001U
-#define GPIO_IDR_IDR_1                       0x00000002U
-#define GPIO_IDR_IDR_2                       0x00000004U
-#define GPIO_IDR_IDR_3                       0x00000008U
-#define GPIO_IDR_IDR_4                       0x00000010U
-#define GPIO_IDR_IDR_5                       0x00000020U
-#define GPIO_IDR_IDR_6                       0x00000040U
-#define GPIO_IDR_IDR_7                       0x00000080U
-#define GPIO_IDR_IDR_8                       0x00000100U
-#define GPIO_IDR_IDR_9                       0x00000200U
-#define GPIO_IDR_IDR_10                      0x00000400U
-#define GPIO_IDR_IDR_11                      0x00000800U
-#define GPIO_IDR_IDR_12                      0x00001000U
-#define GPIO_IDR_IDR_13                      0x00002000U
-#define GPIO_IDR_IDR_14                      0x00004000U
-#define GPIO_IDR_IDR_15                      0x00008000U
-/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
-#define GPIO_OTYPER_IDR_0                    GPIO_IDR_IDR_0
-#define GPIO_OTYPER_IDR_1                    GPIO_IDR_IDR_1
-#define GPIO_OTYPER_IDR_2                    GPIO_IDR_IDR_2
-#define GPIO_OTYPER_IDR_3                    GPIO_IDR_IDR_3
-#define GPIO_OTYPER_IDR_4                    GPIO_IDR_IDR_4
-#define GPIO_OTYPER_IDR_5                    GPIO_IDR_IDR_5
-#define GPIO_OTYPER_IDR_6                    GPIO_IDR_IDR_6
-#define GPIO_OTYPER_IDR_7                    GPIO_IDR_IDR_7
-#define GPIO_OTYPER_IDR_8                    GPIO_IDR_IDR_8
-#define GPIO_OTYPER_IDR_9                    GPIO_IDR_IDR_9
-#define GPIO_OTYPER_IDR_10                   GPIO_IDR_IDR_10
-#define GPIO_OTYPER_IDR_11                   GPIO_IDR_IDR_11
-#define GPIO_OTYPER_IDR_12                   GPIO_IDR_IDR_12
-#define GPIO_OTYPER_IDR_13                   GPIO_IDR_IDR_13
-#define GPIO_OTYPER_IDR_14                   GPIO_IDR_IDR_14
-#define GPIO_OTYPER_IDR_15                   GPIO_IDR_IDR_15
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       0x00000001U
-#define GPIO_ODR_ODR_1                       0x00000002U
-#define GPIO_ODR_ODR_2                       0x00000004U
-#define GPIO_ODR_ODR_3                       0x00000008U
-#define GPIO_ODR_ODR_4                       0x00000010U
-#define GPIO_ODR_ODR_5                       0x00000020U
-#define GPIO_ODR_ODR_6                       0x00000040U
-#define GPIO_ODR_ODR_7                       0x00000080U
-#define GPIO_ODR_ODR_8                       0x00000100U
-#define GPIO_ODR_ODR_9                       0x00000200U
-#define GPIO_ODR_ODR_10                      0x00000400U
-#define GPIO_ODR_ODR_11                      0x00000800U
-#define GPIO_ODR_ODR_12                      0x00001000U
-#define GPIO_ODR_ODR_13                      0x00002000U
-#define GPIO_ODR_ODR_14                      0x00004000U
-#define GPIO_ODR_ODR_15                      0x00008000U
-/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
-#define GPIO_OTYPER_ODR_0                    GPIO_ODR_ODR_0
-#define GPIO_OTYPER_ODR_1                    GPIO_ODR_ODR_1
-#define GPIO_OTYPER_ODR_2                    GPIO_ODR_ODR_2
-#define GPIO_OTYPER_ODR_3                    GPIO_ODR_ODR_3
-#define GPIO_OTYPER_ODR_4                    GPIO_ODR_ODR_4
-#define GPIO_OTYPER_ODR_5                    GPIO_ODR_ODR_5
-#define GPIO_OTYPER_ODR_6                    GPIO_ODR_ODR_6
-#define GPIO_OTYPER_ODR_7                    GPIO_ODR_ODR_7
-#define GPIO_OTYPER_ODR_8                    GPIO_ODR_ODR_8
-#define GPIO_OTYPER_ODR_9                    GPIO_ODR_ODR_9
-#define GPIO_OTYPER_ODR_10                   GPIO_ODR_ODR_10
-#define GPIO_OTYPER_ODR_11                   GPIO_ODR_ODR_11
-#define GPIO_OTYPER_ODR_12                   GPIO_ODR_ODR_12
-#define GPIO_OTYPER_ODR_13                   GPIO_ODR_ODR_13
-#define GPIO_OTYPER_ODR_14                   GPIO_ODR_ODR_14
-#define GPIO_OTYPER_ODR_15                   GPIO_ODR_ODR_15
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       0x00000001U
-#define GPIO_BSRR_BS_1                       0x00000002U
-#define GPIO_BSRR_BS_2                       0x00000004U
-#define GPIO_BSRR_BS_3                       0x00000008U
-#define GPIO_BSRR_BS_4                       0x00000010U
-#define GPIO_BSRR_BS_5                       0x00000020U
-#define GPIO_BSRR_BS_6                       0x00000040U
-#define GPIO_BSRR_BS_7                       0x00000080U
-#define GPIO_BSRR_BS_8                       0x00000100U
-#define GPIO_BSRR_BS_9                       0x00000200U
-#define GPIO_BSRR_BS_10                      0x00000400U
-#define GPIO_BSRR_BS_11                      0x00000800U
-#define GPIO_BSRR_BS_12                      0x00001000U
-#define GPIO_BSRR_BS_13                      0x00002000U
-#define GPIO_BSRR_BS_14                      0x00004000U
-#define GPIO_BSRR_BS_15                      0x00008000U
-#define GPIO_BSRR_BR_0                       0x00010000U
-#define GPIO_BSRR_BR_1                       0x00020000U
-#define GPIO_BSRR_BR_2                       0x00040000U
-#define GPIO_BSRR_BR_3                       0x00080000U
-#define GPIO_BSRR_BR_4                       0x00100000U
-#define GPIO_BSRR_BR_5                       0x00200000U
-#define GPIO_BSRR_BR_6                       0x00400000U
-#define GPIO_BSRR_BR_7                       0x00800000U
-#define GPIO_BSRR_BR_8                       0x01000000U
-#define GPIO_BSRR_BR_9                       0x02000000U
-#define GPIO_BSRR_BR_10                      0x04000000U
-#define GPIO_BSRR_BR_11                      0x08000000U
-#define GPIO_BSRR_BR_12                      0x10000000U
-#define GPIO_BSRR_BR_13                      0x20000000U
-#define GPIO_BSRR_BR_14                      0x40000000U
-#define GPIO_BSRR_BR_15                      0x80000000U
-
-/****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0                       0x00000001U
-#define GPIO_LCKR_LCK1                       0x00000002U
-#define GPIO_LCKR_LCK2                       0x00000004U
-#define GPIO_LCKR_LCK3                       0x00000008U
-#define GPIO_LCKR_LCK4                       0x00000010U
-#define GPIO_LCKR_LCK5                       0x00000020U
-#define GPIO_LCKR_LCK6                       0x00000040U
-#define GPIO_LCKR_LCK7                       0x00000080U
-#define GPIO_LCKR_LCK8                       0x00000100U
-#define GPIO_LCKR_LCK9                       0x00000200U
-#define GPIO_LCKR_LCK10                      0x00000400U
-#define GPIO_LCKR_LCK11                      0x00000800U
-#define GPIO_LCKR_LCK12                      0x00001000U
-#define GPIO_LCKR_LCK13                      0x00002000U
-#define GPIO_LCKR_LCK14                      0x00004000U
-#define GPIO_LCKR_LCK15                      0x00008000U
-#define GPIO_LCKR_LCKK                       0x00010000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Inter-integrated Circuit Interface                    */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          0x00000001U     /*!<Peripheral Enable                             */
-#define  I2C_CR1_SMBUS                       0x00000002U     /*!<SMBus Mode                                    */
-#define  I2C_CR1_SMBTYPE                     0x00000008U     /*!<SMBus Type                                    */
-#define  I2C_CR1_ENARP                       0x00000010U     /*!<ARP Enable                                    */
-#define  I2C_CR1_ENPEC                       0x00000020U     /*!<PEC Enable                                    */
-#define  I2C_CR1_ENGC                        0x00000040U     /*!<General Call Enable                           */
-#define  I2C_CR1_NOSTRETCH                   0x00000080U     /*!<Clock Stretching Disable (Slave mode)  */
-#define  I2C_CR1_START                       0x00000100U     /*!<Start Generation                              */
-#define  I2C_CR1_STOP                        0x00000200U     /*!<Stop Generation                               */
-#define  I2C_CR1_ACK                         0x00000400U     /*!<Acknowledge Enable                            */
-#define  I2C_CR1_POS                         0x00000800U     /*!<Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         0x00001000U     /*!<Packet Error Checking                         */
-#define  I2C_CR1_ALERT                       0x00002000U     /*!<SMBus Alert                                   */
-#define  I2C_CR1_SWRST                       0x00008000U     /*!<Software Reset                                */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        0x0000003FU     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
-#define  I2C_CR2_FREQ_0                      0x00000001U     /*!<Bit 0 */
-#define  I2C_CR2_FREQ_1                      0x00000002U     /*!<Bit 1 */
-#define  I2C_CR2_FREQ_2                      0x00000004U     /*!<Bit 2 */
-#define  I2C_CR2_FREQ_3                      0x00000008U     /*!<Bit 3 */
-#define  I2C_CR2_FREQ_4                      0x00000010U     /*!<Bit 4 */
-#define  I2C_CR2_FREQ_5                      0x00000020U     /*!<Bit 5 */
-
-#define  I2C_CR2_ITERREN                     0x00000100U     /*!<Error Interrupt Enable  */
-#define  I2C_CR2_ITEVTEN                     0x00000200U     /*!<Event Interrupt Enable  */
-#define  I2C_CR2_ITBUFEN                     0x00000400U     /*!<Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       0x00000800U     /*!<DMA Requests Enable     */
-#define  I2C_CR2_LAST                        0x00001000U     /*!<DMA Last Transfer       */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     0x000000FEU     /*!<Interface Address */
-#define  I2C_OAR1_ADD8_9                     0x00000300U     /*!<Interface Address */
-
-#define  I2C_OAR1_ADD0                       0x00000001U     /*!<Bit 0 */
-#define  I2C_OAR1_ADD1                       0x00000002U     /*!<Bit 1 */
-#define  I2C_OAR1_ADD2                       0x00000004U     /*!<Bit 2 */
-#define  I2C_OAR1_ADD3                       0x00000008U     /*!<Bit 3 */
-#define  I2C_OAR1_ADD4                       0x00000010U     /*!<Bit 4 */
-#define  I2C_OAR1_ADD5                       0x00000020U     /*!<Bit 5 */
-#define  I2C_OAR1_ADD6                       0x00000040U     /*!<Bit 6 */
-#define  I2C_OAR1_ADD7                       0x00000080U     /*!<Bit 7 */
-#define  I2C_OAR1_ADD8                       0x00000100U     /*!<Bit 8 */
-#define  I2C_OAR1_ADD9                       0x00000200U     /*!<Bit 9 */
-
-#define  I2C_OAR1_ADDMODE                    0x00008000U     /*!<Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     0x00000001U        /*!<Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       0x000000FEU        /*!<Interface address           */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           0x000000FFU        /*!<8-bit Data Register         */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          0x00000001U     /*!<Start Bit (Master mode)                  */
-#define  I2C_SR1_ADDR                        0x00000002U     /*!<Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         0x00000004U     /*!<Byte Transfer Finished                          */
-#define  I2C_SR1_ADD10                       0x00000008U     /*!<10-bit header sent (Master mode)         */
-#define  I2C_SR1_STOPF                       0x00000010U     /*!<Stop detection (Slave mode)              */
-#define  I2C_SR1_RXNE                        0x00000040U     /*!<Data Register not Empty (receivers)      */
-#define  I2C_SR1_TXE                         0x00000080U     /*!<Data Register Empty (transmitters)       */
-#define  I2C_SR1_BERR                        0x00000100U     /*!<Bus Error                                       */
-#define  I2C_SR1_ARLO                        0x00000200U     /*!<Arbitration Lost (master mode)           */
-#define  I2C_SR1_AF                          0x00000400U     /*!<Acknowledge Failure                             */
-#define  I2C_SR1_OVR                         0x00000800U     /*!<Overrun/Underrun                                */
-#define  I2C_SR1_PECERR                      0x00001000U     /*!<PEC Error in reception                          */
-#define  I2C_SR1_TIMEOUT                     0x00004000U     /*!<Timeout or Tlow Error                           */
-#define  I2C_SR1_SMBALERT                    0x00008000U     /*!<SMBus Alert                                     */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         0x00000001U     /*!<Master/Slave                              */
-#define  I2C_SR2_BUSY                        0x00000002U     /*!<Bus Busy                                  */
-#define  I2C_SR2_TRA                         0x00000004U     /*!<Transmitter/Receiver                      */
-#define  I2C_SR2_GENCALL                     0x00000010U     /*!<General Call Address (Slave mode)  */
-#define  I2C_SR2_SMBDEFAULT                  0x00000020U     /*!<SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     0x00000040U     /*!<SMBus Host Header (Slave mode)     */
-#define  I2C_SR2_DUALF                       0x00000080U     /*!<Dual Flag (Slave mode)             */
-#define  I2C_SR2_PEC                         0x0000FF00U     /*!<Packet Error Checking Register            */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         0x00000FFFU     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        0x00004000U     /*!<Fast Mode Duty Cycle                                       */
-#define  I2C_CCR_FS                          0x00008000U     /*!<I2C Master Mode Selection                                  */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     0x0000003FU     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************  Bit definition for I2C_FLTR register  *******************/
-#define  I2C_FLTR_DNF                        0x0000000FU     /*!<Digital Noise Filter */
-#define  I2C_FLTR_ANOFF                      0x00000010U     /*!<Analog Noise Filter OFF */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Independent WATCHDOG                             */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         0x01U               /*!<Watchdog prescaler value update      */
-#define  IWDG_SR_RVU                         0x02U               /*!<Watchdog counter reload value update */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                             Power Control                                  */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
-#define  PWR_CR_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
-#define  PWR_CR_CWUF                         0x00000004U     /*!< Clear Wakeup Flag                   */
-#define  PWR_CR_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
-#define  PWR_CR_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
-
-#define  PWR_CR_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        0x00000020U     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        0x00000040U     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        0x00000080U     /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
-
-#define  PWR_CR_DBP                          0x00000100U     /*!< Disable Backup Domain write protection                     */
-#define  PWR_CR_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                              */
-#define  PWR_CR_LPLVDS                       0x00000400U     /*!< Low Power Regulator Low Voltage in Deep Sleep mode         */
-#define  PWR_CR_MRLVDS                       0x00000800U     /*!< Main Regulator Low Voltage in Deep Sleep mode              */
-#define  PWR_CR_ADCDC1                       0x00002000U     /*!< Refer to AN4073 on how to use this bit                     */
-
-#define  PWR_CR_VOS                          0x0000C000U     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
-#define  PWR_CR_VOS_0                        0x00004000U     /*!< Bit 0 */
-#define  PWR_CR_VOS_1                        0x00008000U     /*!< Bit 1 */
-
-#define  PWR_CR_FMSSR                        0x00100000U     /*!< Flash Memory Sleep System Run        */
-#define  PWR_CR_FISSR                        0x00200000U     /*!< Flash Interface Stop while System Run */
-/* Legacy define */
-#define  PWR_CR_PMODE                        PWR_CR_VOS
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         0x00000001U     /*!< Wakeup Flag                                      */
-#define  PWR_CSR_SBF                         0x00000002U     /*!< Standby Flag                                     */
-#define  PWR_CSR_PVDO                        0x00000004U     /*!< PVD Output                                       */
-#define  PWR_CSR_BRR                         0x00000008U     /*!< Backup regulator ready                           */
-#define  PWR_CSR_EWUP                        0x00000100U     /*!< Enable WKUP pin                                  */
-#define  PWR_CSR_BRE                         0x00000200U     /*!< Backup regulator enable                          */
-#define  PWR_CSR_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
-
-/* Legacy define */
-#define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        0x00000001U
-#define  RCC_CR_HSIRDY                       0x00000002U
-
-#define  RCC_CR_HSITRIM                      0x000000F8U
-#define  RCC_CR_HSITRIM_0                    0x00000008U/*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    0x00000010U/*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    0x00000020U/*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    0x00000040U/*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    0x00000080U/*!<Bit 4 */
-
-#define  RCC_CR_HSICAL                       0x0000FF00U
-#define  RCC_CR_HSICAL_0                     0x00000100U/*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     0x00000200U/*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     0x00000400U/*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     0x00000800U/*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     0x00001000U/*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     0x00002000U/*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     0x00004000U/*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     0x00008000U/*!<Bit 7 */
-
-#define  RCC_CR_HSEON                        0x00010000U
-#define  RCC_CR_HSERDY                       0x00020000U
-#define  RCC_CR_HSEBYP                       0x00040000U
-#define  RCC_CR_CSSON                        0x00080000U
-#define  RCC_CR_PLLON                        0x01000000U
-#define  RCC_CR_PLLRDY                       0x02000000U
-#define  RCC_CR_PLLI2SON                     0x04000000U
-#define  RCC_CR_PLLI2SRDY                    0x08000000U
-
-/********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    0x0000003FU
-#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
-#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
-#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
-#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
-#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
-#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
-
-#define  RCC_PLLCFGR_PLLN                     0x00007FC0U
-#define  RCC_PLLCFGR_PLLN_0                   0x00000040U
-#define  RCC_PLLCFGR_PLLN_1                   0x00000080U
-#define  RCC_PLLCFGR_PLLN_2                   0x00000100U
-#define  RCC_PLLCFGR_PLLN_3                   0x00000200U
-#define  RCC_PLLCFGR_PLLN_4                   0x00000400U
-#define  RCC_PLLCFGR_PLLN_5                   0x00000800U
-#define  RCC_PLLCFGR_PLLN_6                   0x00001000U
-#define  RCC_PLLCFGR_PLLN_7                   0x00002000U
-#define  RCC_PLLCFGR_PLLN_8                   0x00004000U
-
-#define  RCC_PLLCFGR_PLLP                    0x00030000U
-#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
-#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
-
-#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
-
-#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
-#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
-#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
-#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
-#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-/*!< SW configuration */
-#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
-
-#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
-
-#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
-
-#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
-
-/*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     0x001F0000U
-#define  RCC_CFGR_RTCPRE_0                   0x00010000U
-#define  RCC_CFGR_RTCPRE_1                   0x00020000U
-#define  RCC_CFGR_RTCPRE_2                   0x00040000U
-#define  RCC_CFGR_RTCPRE_3                   0x00080000U
-#define  RCC_CFGR_RTCPRE_4                   0x00100000U
-
-/*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       0x00600000U
-#define  RCC_CFGR_MCO1_0                     0x00200000U
-#define  RCC_CFGR_MCO1_1                     0x00400000U
-
-#define  RCC_CFGR_I2SSRC                     0x00800000U
-
-#define  RCC_CFGR_MCO1PRE                    0x07000000U
-#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
-#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
-#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
-
-#define  RCC_CFGR_MCO2PRE                    0x38000000U
-#define  RCC_CFGR_MCO2PRE_0                  0x08000000U
-#define  RCC_CFGR_MCO2PRE_1                  0x10000000U
-#define  RCC_CFGR_MCO2PRE_2                  0x20000000U
-
-#define  RCC_CFGR_MCO2                       0xC0000000U
-#define  RCC_CFGR_MCO2_0                     0x40000000U
-#define  RCC_CFGR_MCO2_1                     0x80000000U
-
-/********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     0x00000001U
-#define  RCC_CIR_LSERDYF                     0x00000002U
-#define  RCC_CIR_HSIRDYF                     0x00000004U
-#define  RCC_CIR_HSERDYF                     0x00000008U
-#define  RCC_CIR_PLLRDYF                     0x00000010U
-#define  RCC_CIR_PLLI2SRDYF                  0x00000020U
-
-#define  RCC_CIR_CSSF                        0x00000080U
-#define  RCC_CIR_LSIRDYIE                    0x00000100U
-#define  RCC_CIR_LSERDYIE                    0x00000200U
-#define  RCC_CIR_HSIRDYIE                    0x00000400U
-#define  RCC_CIR_HSERDYIE                    0x00000800U
-#define  RCC_CIR_PLLRDYIE                    0x00001000U
-#define  RCC_CIR_PLLI2SRDYIE                 0x00002000U
-
-#define  RCC_CIR_LSIRDYC                     0x00010000U
-#define  RCC_CIR_LSERDYC                     0x00020000U
-#define  RCC_CIR_HSIRDYC                     0x00040000U
-#define  RCC_CIR_HSERDYC                     0x00080000U
-#define  RCC_CIR_PLLRDYC                     0x00100000U
-#define  RCC_CIR_PLLI2SRDYC                  0x00200000U
-
-#define  RCC_CIR_CSSC                        0x00800000U
-
-/********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
-#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
-#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
-#define  RCC_AHB1RSTR_GPIODRST               0x00000008U
-#define  RCC_AHB1RSTR_GPIOERST               0x00000010U
-#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
-#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
-#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
-#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
-
-/********************  Bit definition for RCC_AHB2RSTR register  **************/
-#define  RCC_AHB2RSTR_OTGFSRST               0x00000080U
-
-/********************  Bit definition for RCC_AHB3RSTR register  **************/
-
-/********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM2RST                0x00000001U
-#define  RCC_APB1RSTR_TIM3RST                0x00000002U
-#define  RCC_APB1RSTR_TIM4RST                0x00000004U
-#define  RCC_APB1RSTR_TIM5RST                0x00000008U
-#define  RCC_APB1RSTR_WWDGRST                0x00000800U
-#define  RCC_APB1RSTR_SPI2RST                0x00004000U
-#define  RCC_APB1RSTR_SPI3RST                0x00008000U
-#define  RCC_APB1RSTR_USART2RST              0x00020000U
-#define  RCC_APB1RSTR_I2C1RST                0x00200000U
-#define  RCC_APB1RSTR_I2C2RST                0x00400000U
-#define  RCC_APB1RSTR_I2C3RST                0x00800000U
-#define  RCC_APB1RSTR_PWRRST                 0x10000000U
-
-/********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                0x00000001U
-#define  RCC_APB2RSTR_USART1RST              0x00000010U
-#define  RCC_APB2RSTR_USART6RST              0x00000020U
-#define  RCC_APB2RSTR_ADCRST                 0x00000100U
-#define  RCC_APB2RSTR_SDIORST                0x00000800U
-#define  RCC_APB2RSTR_SPI1RST                0x00001000U
-#define  RCC_APB2RSTR_SPI4RST                0x00002000U
-#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
-#define  RCC_APB2RSTR_TIM9RST                0x00010000U
-#define  RCC_APB2RSTR_TIM10RST               0x00020000U
-#define  RCC_APB2RSTR_TIM11RST               0x00040000U
-#define  RCC_APB2RSTR_SPI5RST                0x00100000U
-
-/* Old SPI1RST bit definition, maintained for legacy purpose */
-#define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
-
-/********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
-#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
-#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
-#define  RCC_AHB1ENR_GPIODEN                 0x00000008U
-#define  RCC_AHB1ENR_GPIOEEN                 0x00000010U
-#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
-#define  RCC_AHB1ENR_CRCEN                   0x00001000U
-#define  RCC_AHB1ENR_BKPSRAMEN               0x00040000U
-#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
-#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
-
-/********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define  RCC_AHB2ENR_OTGFSEN                 0x00000080U
-
-/********************  Bit definition for RCC_AHB3ENR register  ***************/
-
-/********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM2EN                  0x00000001U
-#define  RCC_APB1ENR_TIM3EN                  0x00000002U
-#define  RCC_APB1ENR_TIM4EN                  0x00000004U
-#define  RCC_APB1ENR_TIM5EN                  0x00000008U
-#define  RCC_APB1ENR_WWDGEN                  0x00000800U
-#define  RCC_APB1ENR_SPI2EN                  0x00004000U
-#define  RCC_APB1ENR_SPI3EN                  0x00008000U
-#define  RCC_APB1ENR_USART2EN                0x00020000U
-#define  RCC_APB1ENR_I2C1EN                  0x00200000U
-#define  RCC_APB1ENR_I2C2EN                  0x00400000U
-#define  RCC_APB1ENR_I2C3EN                  0x00800000U
-#define  RCC_APB1ENR_PWREN                   0x10000000U
-
-/********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  0x00000001U
-#define  RCC_APB2ENR_USART1EN                0x00000010U
-#define  RCC_APB2ENR_USART6EN                0x00000020U
-#define  RCC_APB2ENR_ADC1EN                  0x00000100U
-#define  RCC_APB2ENR_SDIOEN                  0x00000800U
-#define  RCC_APB2ENR_SPI1EN                  0x00001000U
-#define  RCC_APB2ENR_SPI4EN                  0x00002000U
-#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
-#define  RCC_APB2ENR_TIM9EN                  0x00010000U
-#define  RCC_APB2ENR_TIM10EN                 0x00020000U
-#define  RCC_APB2ENR_TIM11EN                 0x00040000U
-#define  RCC_APB2ENR_SPI5EN                  0x00100000U
-
-/********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
-#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
-#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
-#define  RCC_AHB1LPENR_GPIODLPEN             0x00000008U
-#define  RCC_AHB1LPENR_GPIOELPEN             0x00000010U
-#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
-#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
-#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
-#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
-#define  RCC_AHB1LPENR_SRAM2LPEN             0x00020000U
-#define  RCC_AHB1LPENR_BKPSRAMLPEN           0x00040000U
-#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
-#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
-
-/********************  Bit definition for RCC_AHB2LPENR register  *************/
-#define  RCC_AHB2LPENR_OTGFSLPEN             0x00000080U
-
-/********************  Bit definition for RCC_AHB3LPENR register  *************/
-
-/********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM2LPEN              0x00000001U
-#define  RCC_APB1LPENR_TIM3LPEN              0x00000002U
-#define  RCC_APB1LPENR_TIM4LPEN              0x00000004U
-#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
-#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
-#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U
-#define  RCC_APB1LPENR_SPI3LPEN              0x00008000U
-#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
-#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
-#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
-#define  RCC_APB1LPENR_I2C3LPEN              0x00800000U
-#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
-#define  RCC_APB1LPENR_DACLPEN               0x20000000U
-
-/********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
-#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
-#define  RCC_APB2LPENR_USART6LPEN            0x00000020U
-#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
-#define  RCC_APB2LPENR_SDIOLPEN              0x00000800U
-#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
-#define  RCC_APB2LPENR_SPI4LPEN              0x00002000U
-#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
-#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
-#define  RCC_APB2LPENR_TIM10LPEN             0x00020000U
-#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
-#define  RCC_APB2LPENR_SPI5LPEN              0x00100000U
-
-/********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      0x00000001U
-#define  RCC_BDCR_LSERDY                     0x00000002U
-#define  RCC_BDCR_LSEBYP                     0x00000004U
-#define  RCC_BDCR_LSEMOD                     0x00000008U
-
-#define  RCC_BDCR_RTCSEL                    0x00000300U
-#define  RCC_BDCR_RTCSEL_0                  0x00000100U
-#define  RCC_BDCR_RTCSEL_1                  0x00000200U
-
-#define  RCC_BDCR_RTCEN                      0x00008000U
-#define  RCC_BDCR_BDRST                      0x00010000U
-
-/********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       0x00000001U
-#define  RCC_CSR_LSIRDY                      0x00000002U
-#define  RCC_CSR_RMVF                        0x01000000U
-#define  RCC_CSR_BORRSTF                     0x02000000U
-#define  RCC_CSR_PADRSTF                     0x04000000U
-#define  RCC_CSR_PORRSTF                     0x08000000U
-#define  RCC_CSR_SFTRSTF                     0x10000000U
-#define  RCC_CSR_WDGRSTF                     0x20000000U
-#define  RCC_CSR_WWDGRSTF                    0x40000000U
-#define  RCC_CSR_LPWRRSTF                    0x80000000U
-
-/********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    0x00001FFFU
-#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
-#define  RCC_SSCGR_SPREADSEL                 0x40000000U
-#define  RCC_SSCGR_SSCGEN                    0x80000000U
-
-/********************  Bit definition for RCC_PLLI2SCFGR register  ************/
-#define  RCC_PLLI2SCFGR_PLLI2SM              0x0000003FU
-#define  RCC_PLLI2SCFGR_PLLI2SM_0            0x00000001U
-#define  RCC_PLLI2SCFGR_PLLI2SM_1            0x00000002U
-#define  RCC_PLLI2SCFGR_PLLI2SM_2            0x00000004U
-#define  RCC_PLLI2SCFGR_PLLI2SM_3            0x00000008U
-#define  RCC_PLLI2SCFGR_PLLI2SM_4            0x00000010U
-#define  RCC_PLLI2SCFGR_PLLI2SM_5            0x00000020U
-
-#define  RCC_PLLI2SCFGR_PLLI2SN              0x00007FC0U
-#define  RCC_PLLI2SCFGR_PLLI2SN_0            0x00000040U
-#define  RCC_PLLI2SCFGR_PLLI2SN_1            0x00000080U
-#define  RCC_PLLI2SCFGR_PLLI2SN_2            0x00000100U
-#define  RCC_PLLI2SCFGR_PLLI2SN_3            0x00000200U
-#define  RCC_PLLI2SCFGR_PLLI2SN_4            0x00000400U
-#define  RCC_PLLI2SCFGR_PLLI2SN_5            0x00000800U
-#define  RCC_PLLI2SCFGR_PLLI2SN_6            0x00001000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_7            0x00002000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_8            0x00004000U
-
-#define  RCC_PLLI2SCFGR_PLLI2SR              0x70000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_0            0x10000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_1            0x20000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_2            0x40000000U
-
-/********************  Bit definition for RCC_DCKCFGR register  ***************/
-#define  RCC_DCKCFGR_TIMPRE                  0x01000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            0x00400000U
-#define RTC_TR_HT                            0x00300000U
-#define RTC_TR_HT_0                          0x00100000U
-#define RTC_TR_HT_1                          0x00200000U
-#define RTC_TR_HU                            0x000F0000U
-#define RTC_TR_HU_0                          0x00010000U
-#define RTC_TR_HU_1                          0x00020000U
-#define RTC_TR_HU_2                          0x00040000U
-#define RTC_TR_HU_3                          0x00080000U
-#define RTC_TR_MNT                           0x00007000U
-#define RTC_TR_MNT_0                         0x00001000U
-#define RTC_TR_MNT_1                         0x00002000U
-#define RTC_TR_MNT_2                         0x00004000U
-#define RTC_TR_MNU                           0x00000F00U
-#define RTC_TR_MNU_0                         0x00000100U
-#define RTC_TR_MNU_1                         0x00000200U
-#define RTC_TR_MNU_2                         0x00000400U
-#define RTC_TR_MNU_3                         0x00000800U
-#define RTC_TR_ST                            0x00000070U
-#define RTC_TR_ST_0                          0x00000010U
-#define RTC_TR_ST_1                          0x00000020U
-#define RTC_TR_ST_2                          0x00000040U
-#define RTC_TR_SU                            0x0000000FU
-#define RTC_TR_SU_0                          0x00000001U
-#define RTC_TR_SU_1                          0x00000002U
-#define RTC_TR_SU_2                          0x00000004U
-#define RTC_TR_SU_3                          0x00000008U
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            0x00F00000U
-#define RTC_DR_YT_0                          0x00100000U
-#define RTC_DR_YT_1                          0x00200000U
-#define RTC_DR_YT_2                          0x00400000U
-#define RTC_DR_YT_3                          0x00800000U
-#define RTC_DR_YU                            0x000F0000U
-#define RTC_DR_YU_0                          0x00010000U
-#define RTC_DR_YU_1                          0x00020000U
-#define RTC_DR_YU_2                          0x00040000U
-#define RTC_DR_YU_3                          0x00080000U
-#define RTC_DR_WDU                           0x0000E000U
-#define RTC_DR_WDU_0                         0x00002000U
-#define RTC_DR_WDU_1                         0x00004000U
-#define RTC_DR_WDU_2                         0x00008000U
-#define RTC_DR_MT                            0x00001000U
-#define RTC_DR_MU                            0x00000F00U
-#define RTC_DR_MU_0                          0x00000100U
-#define RTC_DR_MU_1                          0x00000200U
-#define RTC_DR_MU_2                          0x00000400U
-#define RTC_DR_MU_3                          0x00000800U
-#define RTC_DR_DT                            0x00000030U
-#define RTC_DR_DT_0                          0x00000010U
-#define RTC_DR_DT_1                          0x00000020U
-#define RTC_DR_DU                            0x0000000FU
-#define RTC_DR_DU_0                          0x00000001U
-#define RTC_DR_DU_1                          0x00000002U
-#define RTC_DR_DU_2                          0x00000004U
-#define RTC_DR_DU_3                          0x00000008U
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           0x00800000U
-#define RTC_CR_OSEL                          0x00600000U
-#define RTC_CR_OSEL_0                        0x00200000U
-#define RTC_CR_OSEL_1                        0x00400000U
-#define RTC_CR_POL                           0x00100000U
-#define RTC_CR_COSEL                         0x00080000U
-#define RTC_CR_BCK                           0x00040000U
-#define RTC_CR_SUB1H                         0x00020000U
-#define RTC_CR_ADD1H                         0x00010000U
-#define RTC_CR_TSIE                          0x00008000U
-#define RTC_CR_WUTIE                         0x00004000U
-#define RTC_CR_ALRBIE                        0x00002000U
-#define RTC_CR_ALRAIE                        0x00001000U
-#define RTC_CR_TSE                           0x00000800U
-#define RTC_CR_WUTE                          0x00000400U
-#define RTC_CR_ALRBE                         0x00000200U
-#define RTC_CR_ALRAE                         0x00000100U
-#define RTC_CR_DCE                           0x00000080U
-#define RTC_CR_FMT                           0x00000040U
-#define RTC_CR_BYPSHAD                       0x00000020U
-#define RTC_CR_REFCKON                       0x00000010U
-#define RTC_CR_TSEDGE                        0x00000008U
-#define RTC_CR_WUCKSEL                       0x00000007U
-#define RTC_CR_WUCKSEL_0                     0x00000001U
-#define RTC_CR_WUCKSEL_1                     0x00000002U
-#define RTC_CR_WUCKSEL_2                     0x00000004U
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      0x00010000U
-#define RTC_ISR_TAMP1F                       0x00002000U
-#define RTC_ISR_TAMP2F                       0x00004000U
-#define RTC_ISR_TSOVF                        0x00001000U
-#define RTC_ISR_TSF                          0x00000800U
-#define RTC_ISR_WUTF                         0x00000400U
-#define RTC_ISR_ALRBF                        0x00000200U
-#define RTC_ISR_ALRAF                        0x00000100U
-#define RTC_ISR_INIT                         0x00000080U
-#define RTC_ISR_INITF                        0x00000040U
-#define RTC_ISR_RSF                          0x00000020U
-#define RTC_ISR_INITS                        0x00000010U
-#define RTC_ISR_SHPF                         0x00000008U
-#define RTC_ISR_WUTWF                        0x00000004U
-#define RTC_ISR_ALRBWF                       0x00000002U
-#define RTC_ISR_ALRAWF                       0x00000001U
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    0x007F0000U
-#define RTC_PRER_PREDIV_S                    0x00007FFFU
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS                       0x00000080U
-#define RTC_CALIBR_DC                        0x0000001FU
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      0x80000000U
-#define RTC_ALRMAR_WDSEL                     0x40000000U
-#define RTC_ALRMAR_DT                        0x30000000U
-#define RTC_ALRMAR_DT_0                      0x10000000U
-#define RTC_ALRMAR_DT_1                      0x20000000U
-#define RTC_ALRMAR_DU                        0x0F000000U
-#define RTC_ALRMAR_DU_0                      0x01000000U
-#define RTC_ALRMAR_DU_1                      0x02000000U
-#define RTC_ALRMAR_DU_2                      0x04000000U
-#define RTC_ALRMAR_DU_3                      0x08000000U
-#define RTC_ALRMAR_MSK3                      0x00800000U
-#define RTC_ALRMAR_PM                        0x00400000U
-#define RTC_ALRMAR_HT                        0x00300000U
-#define RTC_ALRMAR_HT_0                      0x00100000U
-#define RTC_ALRMAR_HT_1                      0x00200000U
-#define RTC_ALRMAR_HU                        0x000F0000U
-#define RTC_ALRMAR_HU_0                      0x00010000U
-#define RTC_ALRMAR_HU_1                      0x00020000U
-#define RTC_ALRMAR_HU_2                      0x00040000U
-#define RTC_ALRMAR_HU_3                      0x00080000U
-#define RTC_ALRMAR_MSK2                      0x00008000U
-#define RTC_ALRMAR_MNT                       0x00007000U
-#define RTC_ALRMAR_MNT_0                     0x00001000U
-#define RTC_ALRMAR_MNT_1                     0x00002000U
-#define RTC_ALRMAR_MNT_2                     0x00004000U
-#define RTC_ALRMAR_MNU                       0x00000F00U
-#define RTC_ALRMAR_MNU_0                     0x00000100U
-#define RTC_ALRMAR_MNU_1                     0x00000200U
-#define RTC_ALRMAR_MNU_2                     0x00000400U
-#define RTC_ALRMAR_MNU_3                     0x00000800U
-#define RTC_ALRMAR_MSK1                      0x00000080U
-#define RTC_ALRMAR_ST                        0x00000070U
-#define RTC_ALRMAR_ST_0                      0x00000010U
-#define RTC_ALRMAR_ST_1                      0x00000020U
-#define RTC_ALRMAR_ST_2                      0x00000040U
-#define RTC_ALRMAR_SU                        0x0000000FU
-#define RTC_ALRMAR_SU_0                      0x00000001U
-#define RTC_ALRMAR_SU_1                      0x00000002U
-#define RTC_ALRMAR_SU_2                      0x00000004U
-#define RTC_ALRMAR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      0x80000000U
-#define RTC_ALRMBR_WDSEL                     0x40000000U
-#define RTC_ALRMBR_DT                        0x30000000U
-#define RTC_ALRMBR_DT_0                      0x10000000U
-#define RTC_ALRMBR_DT_1                      0x20000000U
-#define RTC_ALRMBR_DU                        0x0F000000U
-#define RTC_ALRMBR_DU_0                      0x01000000U
-#define RTC_ALRMBR_DU_1                      0x02000000U
-#define RTC_ALRMBR_DU_2                      0x04000000U
-#define RTC_ALRMBR_DU_3                      0x08000000U
-#define RTC_ALRMBR_MSK3                      0x00800000U
-#define RTC_ALRMBR_PM                        0x00400000U
-#define RTC_ALRMBR_HT                        0x00300000U
-#define RTC_ALRMBR_HT_0                      0x00100000U
-#define RTC_ALRMBR_HT_1                      0x00200000U
-#define RTC_ALRMBR_HU                        0x000F0000U
-#define RTC_ALRMBR_HU_0                      0x00010000U
-#define RTC_ALRMBR_HU_1                      0x00020000U
-#define RTC_ALRMBR_HU_2                      0x00040000U
-#define RTC_ALRMBR_HU_3                      0x00080000U
-#define RTC_ALRMBR_MSK2                      0x00008000U
-#define RTC_ALRMBR_MNT                       0x00007000U
-#define RTC_ALRMBR_MNT_0                     0x00001000U
-#define RTC_ALRMBR_MNT_1                     0x00002000U
-#define RTC_ALRMBR_MNT_2                     0x00004000U
-#define RTC_ALRMBR_MNU                       0x00000F00U
-#define RTC_ALRMBR_MNU_0                     0x00000100U
-#define RTC_ALRMBR_MNU_1                     0x00000200U
-#define RTC_ALRMBR_MNU_2                     0x00000400U
-#define RTC_ALRMBR_MNU_3                     0x00000800U
-#define RTC_ALRMBR_MSK1                      0x00000080U
-#define RTC_ALRMBR_ST                        0x00000070U
-#define RTC_ALRMBR_ST_0                      0x00000010U
-#define RTC_ALRMBR_ST_1                      0x00000020U
-#define RTC_ALRMBR_ST_2                      0x00000040U
-#define RTC_ALRMBR_SU                        0x0000000FU
-#define RTC_ALRMBR_SU_0                      0x00000001U
-#define RTC_ALRMBR_SU_1                      0x00000002U
-#define RTC_ALRMBR_SU_2                      0x00000004U
-#define RTC_ALRMBR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          0x000000FFU
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           0x0000FFFFU
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     0x00007FFFU
-#define RTC_SHIFTR_ADD1S                     0x80000000U
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          0x00400000U
-#define RTC_TSTR_HT                          0x00300000U
-#define RTC_TSTR_HT_0                        0x00100000U
-#define RTC_TSTR_HT_1                        0x00200000U
-#define RTC_TSTR_HU                          0x000F0000U
-#define RTC_TSTR_HU_0                        0x00010000U
-#define RTC_TSTR_HU_1                        0x00020000U
-#define RTC_TSTR_HU_2                        0x00040000U
-#define RTC_TSTR_HU_3                        0x00080000U
-#define RTC_TSTR_MNT                         0x00007000U
-#define RTC_TSTR_MNT_0                       0x00001000U
-#define RTC_TSTR_MNT_1                       0x00002000U
-#define RTC_TSTR_MNT_2                       0x00004000U
-#define RTC_TSTR_MNU                         0x00000F00U
-#define RTC_TSTR_MNU_0                       0x00000100U
-#define RTC_TSTR_MNU_1                       0x00000200U
-#define RTC_TSTR_MNU_2                       0x00000400U
-#define RTC_TSTR_MNU_3                       0x00000800U
-#define RTC_TSTR_ST                          0x00000070U
-#define RTC_TSTR_ST_0                        0x00000010U
-#define RTC_TSTR_ST_1                        0x00000020U
-#define RTC_TSTR_ST_2                        0x00000040U
-#define RTC_TSTR_SU                          0x0000000FU
-#define RTC_TSTR_SU_0                        0x00000001U
-#define RTC_TSTR_SU_1                        0x00000002U
-#define RTC_TSTR_SU_2                        0x00000004U
-#define RTC_TSTR_SU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         0x0000E000U
-#define RTC_TSDR_WDU_0                       0x00002000U
-#define RTC_TSDR_WDU_1                       0x00004000U
-#define RTC_TSDR_WDU_2                       0x00008000U
-#define RTC_TSDR_MT                          0x00001000U
-#define RTC_TSDR_MU                          0x00000F00U
-#define RTC_TSDR_MU_0                        0x00000100U
-#define RTC_TSDR_MU_1                        0x00000200U
-#define RTC_TSDR_MU_2                        0x00000400U
-#define RTC_TSDR_MU_3                        0x00000800U
-#define RTC_TSDR_DT                          0x00000030U
-#define RTC_TSDR_DT_0                        0x00000010U
-#define RTC_TSDR_DT_1                        0x00000020U
-#define RTC_TSDR_DU                          0x0000000FU
-#define RTC_TSDR_DU_0                        0x00000001U
-#define RTC_TSDR_DU_1                        0x00000002U
-#define RTC_TSDR_DU_2                        0x00000004U
-#define RTC_TSDR_DU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        0x00008000U
-#define RTC_CALR_CALW8                       0x00004000U
-#define RTC_CALR_CALW16                      0x00002000U
-#define RTC_CALR_CALM                        0x000001FFU
-#define RTC_CALR_CALM_0                      0x00000001U
-#define RTC_CALR_CALM_1                      0x00000002U
-#define RTC_CALR_CALM_2                      0x00000004U
-#define RTC_CALR_CALM_3                      0x00000008U
-#define RTC_CALR_CALM_4                      0x00000010U
-#define RTC_CALR_CALM_5                      0x00000020U
-#define RTC_CALR_CALM_6                      0x00000040U
-#define RTC_CALR_CALM_7                      0x00000080U
-#define RTC_CALR_CALM_8                      0x00000100U
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               0x00040000U
-#define RTC_TAFCR_TSINSEL                    0x00020000U
-#define RTC_TAFCR_TAMPINSEL                  0x00010000U
-#define RTC_TAFCR_TAMPPUDIS                  0x00008000U
-#define RTC_TAFCR_TAMPPRCH                   0x00006000U
-#define RTC_TAFCR_TAMPPRCH_0                 0x00002000U
-#define RTC_TAFCR_TAMPPRCH_1                 0x00004000U
-#define RTC_TAFCR_TAMPFLT                    0x00001800U
-#define RTC_TAFCR_TAMPFLT_0                  0x00000800U
-#define RTC_TAFCR_TAMPFLT_1                  0x00001000U
-#define RTC_TAFCR_TAMPFREQ                   0x00000700U
-#define RTC_TAFCR_TAMPFREQ_0                 0x00000100U
-#define RTC_TAFCR_TAMPFREQ_1                 0x00000200U
-#define RTC_TAFCR_TAMPFREQ_2                 0x00000400U
-#define RTC_TAFCR_TAMPTS                     0x00000080U
-#define RTC_TAFCR_TAMP2TRG                   0x00000010U
-#define RTC_TAFCR_TAMP2E                     0x00000008U
-#define RTC_TAFCR_TAMPIE                     0x00000004U
-#define RTC_TAFCR_TAMP1TRG                   0x00000002U
-#define RTC_TAFCR_TAMP1E                     0x00000001U
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  0x0F000000U
-#define RTC_ALRMASSR_MASKSS_0                0x01000000U
-#define RTC_ALRMASSR_MASKSS_1                0x02000000U
-#define RTC_ALRMASSR_MASKSS_2                0x04000000U
-#define RTC_ALRMASSR_MASKSS_3                0x08000000U
-#define RTC_ALRMASSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
-#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
-#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
-#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
-#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
-#define RTC_ALRMBSSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           0xFFFFFFFFU
-
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          SD host Interface                                 */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SDIO_POWER register  ******************/
-#define  SDIO_POWER_PWRCTRL                  0x03U               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDIO_POWER_PWRCTRL_0                0x01U               /*!<Bit 0 */
-#define  SDIO_POWER_PWRCTRL_1                0x02U               /*!<Bit 1 */
-
-/******************  Bit definition for SDIO_CLKCR register  ******************/
-#define  SDIO_CLKCR_CLKDIV                   0x00FFU            /*!<Clock divide factor             */
-#define  SDIO_CLKCR_CLKEN                    0x0100U            /*!<Clock enable bit                */
-#define  SDIO_CLKCR_PWRSAV                   0x0200U            /*!<Power saving configuration bit  */
-#define  SDIO_CLKCR_BYPASS                   0x0400U            /*!<Clock divider bypass enable bit */
-
-#define  SDIO_CLKCR_WIDBUS                   0x1800U            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDIO_CLKCR_WIDBUS_0                 0x0800U            /*!<Bit 0 */
-#define  SDIO_CLKCR_WIDBUS_1                 0x1000U            /*!<Bit 1 */
-
-#define  SDIO_CLKCR_NEGEDGE                  0x2000U            /*!<SDIO_CK dephasing selection bit */
-#define  SDIO_CLKCR_HWFC_EN                  0x4000U            /*!<HW Flow Control enable          */
-
-/*******************  Bit definition for SDIO_ARG register  *******************/
-#define  SDIO_ARG_CMDARG                     0xFFFFFFFFU            /*!<Command argument */
-
-/*******************  Bit definition for SDIO_CMD register  *******************/
-#define  SDIO_CMD_CMDINDEX                   0x003FU            /*!<Command Index                               */
-
-#define  SDIO_CMD_WAITRESP                   0x00C0U            /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDIO_CMD_WAITRESP_0                 0x0040U            /*!< Bit 0 */
-#define  SDIO_CMD_WAITRESP_1                 0x0080U            /*!< Bit 1 */
-
-#define  SDIO_CMD_WAITINT                    0x0100U            /*!<CPSM Waits for Interrupt Request                               */
-#define  SDIO_CMD_WAITPEND                   0x0200U            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDIO_CMD_CPSMEN                     0x0400U            /*!<Command path state machine (CPSM) Enable bit                   */
-#define  SDIO_CMD_SDIOSUSPEND                0x0800U            /*!<SD I/O suspend command                                         */
-#define  SDIO_CMD_ENCMDCOMPL                 0x1000U            /*!<Enable CMD completion                                          */
-#define  SDIO_CMD_NIEN                       0x2000U            /*!<Not Interrupt Enable */
-#define  SDIO_CMD_CEATACMD                   0x4000U            /*!<CE-ATA command       */
-
-/*****************  Bit definition for SDIO_RESPCMD register  *****************/
-#define  SDIO_RESPCMD_RESPCMD                0x3FU               /*!<Response command index */
-
-/******************  Bit definition for SDIO_RESP0 register  ******************/
-#define  SDIO_RESP0_CARDSTATUS0              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP1 register  ******************/
-#define  SDIO_RESP1_CARDSTATUS1              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP2 register  ******************/
-#define  SDIO_RESP2_CARDSTATUS2              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP3 register  ******************/
-#define  SDIO_RESP3_CARDSTATUS3              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP4 register  ******************/
-#define  SDIO_RESP4_CARDSTATUS4              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_DTIMER register  *****************/
-#define  SDIO_DTIMER_DATATIME                0xFFFFFFFFU        /*!<Data timeout period. */
-
-/******************  Bit definition for SDIO_DLEN register  *******************/
-#define  SDIO_DLEN_DATALENGTH                0x01FFFFFFU        /*!<Data length value    */
-
-/******************  Bit definition for SDIO_DCTRL register  ******************/
-#define  SDIO_DCTRL_DTEN                     0x0001U            /*!<Data transfer enabled bit         */
-#define  SDIO_DCTRL_DTDIR                    0x0002U            /*!<Data transfer direction selection */
-#define  SDIO_DCTRL_DTMODE                   0x0004U            /*!<Data transfer mode selection      */
-#define  SDIO_DCTRL_DMAEN                    0x0008U            /*!<DMA enabled bit                   */
-
-#define  SDIO_DCTRL_DBLOCKSIZE               0x00F0U            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDIO_DCTRL_DBLOCKSIZE_0             0x0010U            /*!<Bit 0 */
-#define  SDIO_DCTRL_DBLOCKSIZE_1             0x0020U            /*!<Bit 1 */
-#define  SDIO_DCTRL_DBLOCKSIZE_2             0x0040U            /*!<Bit 2 */
-#define  SDIO_DCTRL_DBLOCKSIZE_3             0x0080U            /*!<Bit 3 */
-
-#define  SDIO_DCTRL_RWSTART                  0x0100U            /*!<Read wait start         */
-#define  SDIO_DCTRL_RWSTOP                   0x0200U            /*!<Read wait stop          */
-#define  SDIO_DCTRL_RWMOD                    0x0400U            /*!<Read wait mode          */
-#define  SDIO_DCTRL_SDIOEN                   0x0800U            /*!<SD I/O enable functions */
-
-/******************  Bit definition for SDIO_DCOUNT register  *****************/
-#define  SDIO_DCOUNT_DATACOUNT               0x01FFFFFFU        /*!<Data count value */
-
-/******************  Bit definition for SDIO_STA register  ********************/
-#define  SDIO_STA_CCRCFAIL                   0x00000001U        /*!<Command response received (CRC check failed)  */
-#define  SDIO_STA_DCRCFAIL                   0x00000002U        /*!<Data block sent/received (CRC check failed)   */
-#define  SDIO_STA_CTIMEOUT                   0x00000004U        /*!<Command response timeout                      */
-#define  SDIO_STA_DTIMEOUT                   0x00000008U        /*!<Data timeout                                  */
-#define  SDIO_STA_TXUNDERR                   0x00000010U        /*!<Transmit FIFO underrun error                  */
-#define  SDIO_STA_RXOVERR                    0x00000020U        /*!<Received FIFO overrun error                   */
-#define  SDIO_STA_CMDREND                    0x00000040U        /*!<Command response received (CRC check passed)  */
-#define  SDIO_STA_CMDSENT                    0x00000080U        /*!<Command sent (no response required)           */
-#define  SDIO_STA_DATAEND                    0x00000100U        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
-#define  SDIO_STA_STBITERR                   0x00000200U        /*!<Start bit not detected on all data signals in wide bus mode */
-#define  SDIO_STA_DBCKEND                    0x00000400U        /*!<Data block sent/received (CRC check passed)   */
-#define  SDIO_STA_CMDACT                     0x00000800U        /*!<Command transfer in progress                  */
-#define  SDIO_STA_TXACT                      0x00001000U        /*!<Data transmit in progress                     */
-#define  SDIO_STA_RXACT                      0x00002000U        /*!<Data receive in progress                      */
-#define  SDIO_STA_TXFIFOHE                   0x00004000U        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDIO_STA_RXFIFOHF                   0x00008000U        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDIO_STA_TXFIFOF                    0x00010000U        /*!<Transmit FIFO full                            */
-#define  SDIO_STA_RXFIFOF                    0x00020000U        /*!<Receive FIFO full                             */
-#define  SDIO_STA_TXFIFOE                    0x00040000U        /*!<Transmit FIFO empty                           */
-#define  SDIO_STA_RXFIFOE                    0x00080000U        /*!<Receive FIFO empty                            */
-#define  SDIO_STA_TXDAVL                     0x00100000U        /*!<Data available in transmit FIFO               */
-#define  SDIO_STA_RXDAVL                     0x00200000U        /*!<Data available in receive FIFO                */
-#define  SDIO_STA_SDIOIT                     0x00400000U        /*!<SDIO interrupt received                       */
-#define  SDIO_STA_CEATAEND                   0x00800000U        /*!<CE-ATA command completion signal received for CMD61 */
-
-/*******************  Bit definition for SDIO_ICR register  *******************/
-#define  SDIO_ICR_CCRCFAILC                  0x00000001U        /*!<CCRCFAIL flag clear bit */
-#define  SDIO_ICR_DCRCFAILC                  0x00000002U        /*!<DCRCFAIL flag clear bit */
-#define  SDIO_ICR_CTIMEOUTC                  0x00000004U        /*!<CTIMEOUT flag clear bit */
-#define  SDIO_ICR_DTIMEOUTC                  0x00000008U        /*!<DTIMEOUT flag clear bit */
-#define  SDIO_ICR_TXUNDERRC                  0x00000010U        /*!<TXUNDERR flag clear bit */
-#define  SDIO_ICR_RXOVERRC                   0x00000020U        /*!<RXOVERR flag clear bit  */
-#define  SDIO_ICR_CMDRENDC                   0x00000040U        /*!<CMDREND flag clear bit  */
-#define  SDIO_ICR_CMDSENTC                   0x00000080U        /*!<CMDSENT flag clear bit  */
-#define  SDIO_ICR_DATAENDC                   0x00000100U        /*!<DATAEND flag clear bit  */
-#define  SDIO_ICR_STBITERRC                  0x00000200U        /*!<STBITERR flag clear bit */
-#define  SDIO_ICR_DBCKENDC                   0x00000400U        /*!<DBCKEND flag clear bit  */
-#define  SDIO_ICR_SDIOITC                    0x00400000U        /*!<SDIOIT flag clear bit   */
-#define  SDIO_ICR_CEATAENDC                  0x00800000U        /*!<CEATAEND flag clear bit */
-
-/******************  Bit definition for SDIO_MASK register  *******************/
-#define  SDIO_MASK_CCRCFAILIE                0x00000001U        /*!<Command CRC Fail Interrupt Enable          */
-#define  SDIO_MASK_DCRCFAILIE                0x00000002U        /*!<Data CRC Fail Interrupt Enable             */
-#define  SDIO_MASK_CTIMEOUTIE                0x00000004U        /*!<Command TimeOut Interrupt Enable           */
-#define  SDIO_MASK_DTIMEOUTIE                0x00000008U        /*!<Data TimeOut Interrupt Enable              */
-#define  SDIO_MASK_TXUNDERRIE                0x00000010U        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
-#define  SDIO_MASK_RXOVERRIE                 0x00000020U        /*!<Rx FIFO OverRun Error Interrupt Enable     */
-#define  SDIO_MASK_CMDRENDIE                 0x00000040U        /*!<Command Response Received Interrupt Enable */
-#define  SDIO_MASK_CMDSENTIE                 0x00000080U        /*!<Command Sent Interrupt Enable              */
-#define  SDIO_MASK_DATAENDIE                 0x00000100U        /*!<Data End Interrupt Enable                  */
-#define  SDIO_MASK_STBITERRIE                0x00000200U        /*!<Start Bit Error Interrupt Enable           */
-#define  SDIO_MASK_DBCKENDIE                 0x00000400U        /*!<Data Block End Interrupt Enable            */
-#define  SDIO_MASK_CMDACTIE                  0x00000800U        /*!<CCommand Acting Interrupt Enable           */
-#define  SDIO_MASK_TXACTIE                   0x00001000U        /*!<Data Transmit Acting Interrupt Enable      */
-#define  SDIO_MASK_RXACTIE                   0x00002000U        /*!<Data receive acting interrupt enabled      */
-#define  SDIO_MASK_TXFIFOHEIE                0x00004000U        /*!<Tx FIFO Half Empty interrupt Enable        */
-#define  SDIO_MASK_RXFIFOHFIE                0x00008000U        /*!<Rx FIFO Half Full interrupt Enable         */
-#define  SDIO_MASK_TXFIFOFIE                 0x00010000U        /*!<Tx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_RXFIFOFIE                 0x00020000U        /*!<Rx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_TXFIFOEIE                 0x00040000U        /*!<Tx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_RXFIFOEIE                 0x00080000U        /*!<Rx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_TXDAVLIE                  0x00100000U        /*!<Data available in Tx FIFO interrupt Enable */
-#define  SDIO_MASK_RXDAVLIE                  0x00200000U        /*!<Data available in Rx FIFO interrupt Enable */
-#define  SDIO_MASK_SDIOITIE                  0x00400000U        /*!<SDIO Mode Interrupt Received interrupt Enable */
-#define  SDIO_MASK_CEATAENDIE                0x00800000U        /*!<CE-ATA command completion signal received Interrupt Enable */
-
-/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
-#define  SDIO_FIFOCNT_FIFOCOUNT              0x00FFFFFFU        /*!<Remaining number of words to be written to or read from the FIFO */
-
-/******************  Bit definition for SDIO_FIFO register  *******************/
-#define  SDIO_FIFO_FIFODATA                  0xFFFFFFFFU        /*!<Receive and transmit FIFO data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        0x00000001U            /*!<Clock Phase      */
-#define  SPI_CR1_CPOL                        0x00000002U            /*!<Clock Polarity   */
-#define  SPI_CR1_MSTR                        0x00000004U            /*!<Master Selection */
-
-#define  SPI_CR1_BR                          0x00000038U            /*!<BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        0x00000008U            /*!<Bit 0 */
-#define  SPI_CR1_BR_1                        0x00000010U            /*!<Bit 1 */
-#define  SPI_CR1_BR_2                        0x00000020U            /*!<Bit 2 */
-
-#define  SPI_CR1_SPE                         0x00000040U            /*!<SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    0x00000080U            /*!<Frame Format                        */
-#define  SPI_CR1_SSI                         0x00000100U            /*!<Internal slave select               */
-#define  SPI_CR1_SSM                         0x00000200U            /*!<Software slave management           */
-#define  SPI_CR1_RXONLY                      0x00000400U            /*!<Receive only                        */
-#define  SPI_CR1_DFF                         0x00000800U            /*!<Data Frame Format                   */
-#define  SPI_CR1_CRCNEXT                     0x00001000U            /*!<Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       0x00002000U            /*!<Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      0x00004000U            /*!<Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    0x00008000U            /*!<Bidirectional data mode enable      */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     0x00000001U               /*!<Rx Buffer DMA Enable                 */
-#define  SPI_CR2_TXDMAEN                     0x00000002U               /*!<Tx Buffer DMA Enable                 */
-#define  SPI_CR2_SSOE                        0x00000004U               /*!<SS Output Enable                     */
-#define  SPI_CR2_FRF                         0x00000010U               /*!<Frame Format                         */
-#define  SPI_CR2_ERRIE                       0x00000020U               /*!<Error Interrupt Enable               */
-#define  SPI_CR2_RXNEIE                      0x00000040U               /*!<RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       0x00000080U               /*!<Tx buffer Empty Interrupt Enable     */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         0x00000001U               /*!<Receive buffer Not Empty */
-#define  SPI_SR_TXE                          0x00000002U               /*!<Transmit buffer Empty    */
-#define  SPI_SR_CHSIDE                       0x00000004U               /*!<Channel side             */
-#define  SPI_SR_UDR                          0x00000008U               /*!<Underrun flag            */
-#define  SPI_SR_CRCERR                       0x00000010U               /*!<CRC Error flag           */
-#define  SPI_SR_MODF                         0x00000020U               /*!<Mode fault               */
-#define  SPI_SR_OVR                          0x00000040U               /*!<Overrun flag             */
-#define  SPI_SR_BSY                          0x00000080U               /*!<Busy flag                */
-#define  SPI_SR_FRE                          0x00000100U               /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           0x0000FFFFU            /*!<Data Register           */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   0x0000FFFFU            /*!<CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    0x0000FFFFU            /*!<Rx CRC Register         */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    0x0000FFFFU            /*!<Tx CRC Register         */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   0x00000001U            /*!<Channel length (number of bits per audio channel) */
-
-#define  SPI_I2SCFGR_DATLEN                  0x00000006U            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define  SPI_I2SCFGR_DATLEN_0                0x00000002U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                0x00000004U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_CKPOL                   0x00000008U            /*!<steady state clock polarity               */
-
-#define  SPI_I2SCFGR_I2SSTD                  0x00000030U            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U            /*!<PCM frame synchronization                 */
-
-#define  SPI_I2SCFGR_I2SCFG                  0x00000300U            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_I2SE                    0x00000400U            /*!<I2S Enable         */
-#define  SPI_I2SCFGR_I2SMOD                  0x00000800U            /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    0x000000FFU            /*!<I2S Linear prescaler         */
-#define  SPI_I2SPR_ODD                       0x00000100U            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     0x00000200U            /*!<Master Clock Output Enable   */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 SYSCFG                                     */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
-#define SYSCFG_MEMRMP_MEM_MODE          0x00000007U /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        0x00000001U
-#define SYSCFG_MEMRMP_MEM_MODE_1        0x00000002U
-#define SYSCFG_MEMRMP_MEM_MODE_2        0x00000004U
-
-/******************  Bit definition for SYSCFG_PMC register  ******************/
-#define SYSCFG_PMC_ADC1DC2              0x00010000U /*!< Refer to AN4073 on how to use this bit  */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
-/** 
-  * @brief   EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         0x0003U /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         0x0004U /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
-
-/** 
-  * @brief   EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         0x0030U /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         0x0040U /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
-
-/** 
-  * @brief   EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         0x0300U /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         0x0400U /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
-
-/** 
-  * @brief   EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         0x3000U /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         0x4000U /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
-/** 
-  * @brief   EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         0x0003U /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         0x0004U /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
-
-/** 
-  * @brief   EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         0x0030U /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         0x0040U /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
-
-/** 
-  * @brief   EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         0x0300U /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         0x0400U /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
-
-/** 
-  * @brief   EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         0x3000U /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         0x4000U /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
-
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
-           
-/** 
-  * @brief   EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         0x0003U /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         0x0004U /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
-
-/** 
-  * @brief   EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         0x0030U /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         0x0040U /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
-
-/** 
-  * @brief   EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        0x0300U /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        0x0400U /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
-
-/** 
-  * @brief   EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        0x3000U /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        0x4000U /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
-/** 
-  * @brief   EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        0x0003U /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        0x0004U /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
-
-/** 
-  * @brief   EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        0x0030U /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        0x0040U /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
-
-/** 
-  * @brief   EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        0x0300U /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        0x0400U /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
-
-/** 
-  * @brief   EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        0x3000U /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        0x4000U /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
-
-/******************  Bit definition for SYSCFG_CMPCR register  ****************/  
-#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell ready flag */
-#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell power-down */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    TIM                                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
-#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
-#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
-#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
-#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
-
-#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
-
-#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
-
-#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        0x0001U            /*!<Capture/Compare Preloaded Control        */
-#define  TIM_CR2_CCUS                        0x0004U            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        0x0008U            /*!<Capture/Compare DMA Selection            */
-
-#define  TIM_CR2_MMS                         0x0070U            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
-#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
-#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
-#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        0x0007U            /*!<SMS[2:0] bits (Slave mode selection)    */
-#define  TIM_SMCR_SMS_0                      0x0001U            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      0x0002U            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      0x0004U            /*!<Bit 2 */
-
-#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
-#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
-
-#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
-
-#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
-
-#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
-#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
-#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
-#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
-#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
-#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
-#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
-#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
-#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
-#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
-#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
-#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
-#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
-#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
-#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
-#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
-#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
-#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
-#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          0x01U               /*!<Update Generation                         */
-#define  TIM_EGR_CC1G                        0x02U               /*!<Capture/Compare 1 Generation              */
-#define  TIM_EGR_CC2G                        0x04U               /*!<Capture/Compare 2 Generation              */
-#define  TIM_EGR_CC3G                        0x08U               /*!<Capture/Compare 3 Generation              */
-#define  TIM_EGR_CC4G                        0x10U               /*!<Capture/Compare 4 Generation              */
-#define  TIM_EGR_COMG                        0x20U               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          0x40U               /*!<Trigger Generation                        */
-#define  TIM_EGR_BG                          0x80U               /*!<Break Generation                          */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      0x0003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    0x0001U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    0x0002U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC1FE                     0x0004U            /*!<Output Compare 1 Fast enable                 */
-#define  TIM_CCMR1_OC1PE                     0x0008U            /*!<Output Compare 1 Preload enable              */
-
-#define  TIM_CCMR1_OC1M                      0x0070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define  TIM_CCMR1_OC1M_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    0x0040U            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC1CE                     0x0080U            /*!<Output Compare 1Clear Enable                 */
-
-#define  TIM_CCMR1_CC2S                      0x0300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    0x0100U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    0x0200U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC2FE                     0x0400U            /*!<Output Compare 2 Fast enable                 */
-#define  TIM_CCMR1_OC2PE                     0x0800U            /*!<Output Compare 2 Preload enable              */
-
-#define  TIM_CCMR1_OC2M                      0x7000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define  TIM_CCMR1_OC2M_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    0x4000U            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC2CE                     0x8000U            /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      0x0003U            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define  TIM_CCMR2_CC3S_0                    0x0001U            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    0x0002U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC3FE                     0x0004U            /*!<Output Compare 3 Fast enable           */
-#define  TIM_CCMR2_OC3PE                     0x0008U            /*!<Output Compare 3 Preload enable        */
-
-#define  TIM_CCMR2_OC3M                      0x0070U            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    0x0040U            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC3CE                     0x0080U            /*!<Output Compare 3 Clear Enable */
-
-#define  TIM_CCMR2_CC4S                      0x0300U            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    0x0100U            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    0x0200U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC4FE                     0x0400U            /*!<Output Compare 4 Fast enable    */
-#define  TIM_CCMR2_OC4PE                     0x0800U            /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR2_OC4M                      0x7000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    0x4000U            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       0x0001U            /*!<Capture/Compare 1 output enable                 */
-#define  TIM_CCER_CC1P                       0x0002U            /*!<Capture/Compare 1 output Polarity               */
-#define  TIM_CCER_CC1NE                      0x0004U            /*!<Capture/Compare 1 Complementary output enable   */
-#define  TIM_CCER_CC1NP                      0x0008U            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       0x0010U            /*!<Capture/Compare 2 output enable                 */
-#define  TIM_CCER_CC2P                       0x0020U            /*!<Capture/Compare 2 output Polarity               */
-#define  TIM_CCER_CC2NE                      0x0040U            /*!<Capture/Compare 2 Complementary output enable   */
-#define  TIM_CCER_CC2NP                      0x0080U            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       0x0100U            /*!<Capture/Compare 3 output enable                 */
-#define  TIM_CCER_CC3P                       0x0200U            /*!<Capture/Compare 3 output Polarity               */
-#define  TIM_CCER_CC3NE                      0x0400U            /*!<Capture/Compare 3 Complementary output enable   */
-#define  TIM_CCER_CC3NP                      0x0800U            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       0x1000U            /*!<Capture/Compare 4 output enable                 */
-#define  TIM_CCER_CC4P                       0x2000U            /*!<Capture/Compare 4 output Polarity               */
-#define  TIM_CCER_CC4NP                      0x8000U            /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         0xFFU               /*!<Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
-
-/*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        0x00FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      0x0001U            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      0x0002U            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      0x0004U            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      0x0008U            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      0x0010U            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      0x0020U            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      0x0040U            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      0x0080U            /*!<Bit 7 */
-
-#define  TIM_BDTR_LOCK                       0x0300U            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     0x0100U            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     0x0200U            /*!<Bit 1 */
-
-#define  TIM_BDTR_OSSI                       0x0400U            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       0x0800U            /*!<Off-State Selection for Run mode  */
-#define  TIM_BDTR_BKE                        0x1000U            /*!<Break enable                      */
-#define  TIM_BDTR_BKP                        0x2000U            /*!<Break Polarity                    */
-#define  TIM_BDTR_AOE                        0x4000U            /*!<Automatic Output enable           */
-#define  TIM_BDTR_MOE                        0x8000U            /*!<Main Output enable                */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
-
-#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
-#define TIM_OR_ITR1_RMP                      0x0C00U            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
-#define TIM_OR_ITR1_RMP_0                    0x0400U            /*!<Bit 0 */
-#define TIM_OR_ITR1_RMP_1                    0x0800U            /*!<Bit 1 */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*         Universal Synchronous Asynchronous Receiver Transmitter            */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         0x0001U            /*!<Parity Error                 */
-#define  USART_SR_FE                         0x0002U            /*!<Framing Error                */
-#define  USART_SR_NE                         0x0004U            /*!<Noise Error Flag             */
-#define  USART_SR_ORE                        0x0008U            /*!<OverRun Error                */
-#define  USART_SR_IDLE                       0x0010U            /*!<IDLE line detected           */
-#define  USART_SR_RXNE                       0x0020U            /*!<Read Data Register Not Empty */
-#define  USART_SR_TC                         0x0040U            /*!<Transmission Complete        */
-#define  USART_SR_TXE                        0x0080U            /*!<Transmit Data Register Empty */
-#define  USART_SR_LBD                        0x0100U            /*!<LIN Break Detection Flag     */
-#define  USART_SR_CTS                        0x0200U            /*!<CTS Flag                     */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         0x01FFU            /*!<Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_Fraction              0x000FU            /*!<Fraction of USARTDIV */
-#define  USART_BRR_DIV_Mantissa              0xFFF0U            /*!<Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       0x0001U            /*!<Send Break                             */
-#define  USART_CR1_RWU                       0x0002U            /*!<Receiver wakeup                        */
-#define  USART_CR1_RE                        0x0004U            /*!<Receiver Enable                        */
-#define  USART_CR1_TE                        0x0008U            /*!<Transmitter Enable                     */
-#define  USART_CR1_IDLEIE                    0x0010U            /*!<IDLE Interrupt Enable                  */
-#define  USART_CR1_RXNEIE                    0x0020U            /*!<RXNE Interrupt Enable                  */
-#define  USART_CR1_TCIE                      0x0040U            /*!<Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     0x0080U            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PEIE                      0x0100U            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PS                        0x0200U            /*!<Parity Selection                       */
-#define  USART_CR1_PCE                       0x0400U            /*!<Parity Control Enable                  */
-#define  USART_CR1_WAKE                      0x0800U            /*!<Wakeup method                          */
-#define  USART_CR1_M                         0x1000U            /*!<Word length                            */
-#define  USART_CR1_UE                        0x2000U            /*!<USART Enable                           */
-#define  USART_CR1_OVER8                     0x8000U            /*!<USART Oversampling by 8 enable         */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       0x000FU            /*!<Address of the USART node            */
-#define  USART_CR2_LBDL                      0x0020U            /*!<LIN Break Detection Length           */
-#define  USART_CR2_LBDIE                     0x0040U            /*!<LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      0x0100U            /*!<Last Bit Clock pulse                 */
-#define  USART_CR2_CPHA                      0x0200U            /*!<Clock Phase                          */
-#define  USART_CR2_CPOL                      0x0400U            /*!<Clock Polarity                       */
-#define  USART_CR2_CLKEN                     0x0800U            /*!<Clock Enable                         */
-
-#define  USART_CR2_STOP                      0x3000U            /*!<STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    0x1000U            /*!<Bit 0 */
-#define  USART_CR2_STOP_1                    0x2000U            /*!<Bit 1 */
-
-#define  USART_CR2_LINEN                     0x4000U            /*!<LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       0x0001U            /*!<Error Interrupt Enable      */
-#define  USART_CR3_IREN                      0x0002U            /*!<IrDA mode Enable            */
-#define  USART_CR3_IRLP                      0x0004U            /*!<IrDA Low-Power              */
-#define  USART_CR3_HDSEL                     0x0008U            /*!<Half-Duplex Selection       */
-#define  USART_CR3_NACK                      0x0010U            /*!<Smartcard NACK enable       */
-#define  USART_CR3_SCEN                      0x0020U            /*!<Smartcard mode enable       */
-#define  USART_CR3_DMAR                      0x0040U            /*!<DMA Enable Receiver         */
-#define  USART_CR3_DMAT                      0x0080U            /*!<DMA Enable Transmitter      */
-#define  USART_CR3_RTSE                      0x0100U            /*!<RTS Enable                  */
-#define  USART_CR3_CTSE                      0x0200U            /*!<CTS Enable                  */
-#define  USART_CR3_CTSIE                     0x0400U            /*!<CTS Interrupt Enable        */
-#define  USART_CR3_ONEBIT                    0x0800U            /*!<USART One bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      0x00FFU            /*!<PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    0x0001U            /*!<Bit 0 */
-#define  USART_GTPR_PSC_1                    0x0002U            /*!<Bit 1 */
-#define  USART_GTPR_PSC_2                    0x0004U            /*!<Bit 2 */
-#define  USART_GTPR_PSC_3                    0x0008U            /*!<Bit 3 */
-#define  USART_GTPR_PSC_4                    0x0010U            /*!<Bit 4 */
-#define  USART_GTPR_PSC_5                    0x0020U            /*!<Bit 5 */
-#define  USART_GTPR_PSC_6                    0x0040U            /*!<Bit 6 */
-#define  USART_GTPR_PSC_7                    0x0080U            /*!<Bit 7 */
-
-#define  USART_GTPR_GT                       0xFF00U            /*!<Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Window WATCHDOG                                 */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           0x7FU               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T_0                         0x01U               /*!<Bit 0 */
-#define  WWDG_CR_T_1                         0x02U               /*!<Bit 1 */
-#define  WWDG_CR_T_2                         0x04U               /*!<Bit 2 */
-#define  WWDG_CR_T_3                         0x08U               /*!<Bit 3 */
-#define  WWDG_CR_T_4                         0x10U               /*!<Bit 4 */
-#define  WWDG_CR_T_5                         0x20U               /*!<Bit 5 */
-#define  WWDG_CR_T_6                         0x40U               /*!<Bit 6 */
-/* Legacy defines */
-#define  WWDG_CR_T0                          WWDG_CR_T_0
-#define  WWDG_CR_T1                          WWDG_CR_T_1
-#define  WWDG_CR_T2                          WWDG_CR_T_2
-#define  WWDG_CR_T3                          WWDG_CR_T_3
-#define  WWDG_CR_T4                          WWDG_CR_T_4
-#define  WWDG_CR_T5                          WWDG_CR_T_5
-#define  WWDG_CR_T6                          WWDG_CR_T_6
-
-#define  WWDG_CR_WDGA                        0x80U               /*!<Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          0x007FU            /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W_0                        0x0001U            /*!<Bit 0 */
-#define  WWDG_CFR_W_1                        0x0002U            /*!<Bit 1 */
-#define  WWDG_CFR_W_2                        0x0004U            /*!<Bit 2 */
-#define  WWDG_CFR_W_3                        0x0008U            /*!<Bit 3 */
-#define  WWDG_CFR_W_4                        0x0010U            /*!<Bit 4 */
-#define  WWDG_CFR_W_5                        0x0020U            /*!<Bit 5 */
-#define  WWDG_CFR_W_6                        0x0040U            /*!<Bit 6 */
-/* Legacy defines */
-#define  WWDG_CFR_W0                         WWDG_CFR_W_0
-#define  WWDG_CFR_W1                         WWDG_CFR_W_1
-#define  WWDG_CFR_W2                         WWDG_CFR_W_2
-#define  WWDG_CFR_W3                         WWDG_CFR_W_3
-#define  WWDG_CFR_W4                         WWDG_CFR_W_4
-#define  WWDG_CFR_W5                         WWDG_CFR_W_5
-#define  WWDG_CFR_W6                         WWDG_CFR_W_6
-
-#define  WWDG_CFR_WDGTB                      0x0180U            /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB_0                    0x0080U            /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB_1                    0x0100U            /*!<Bit 1 */
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
-
-#define  WWDG_CFR_EWI                        0x0200U            /*!<Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        0x01U               /*!<Early Wakeup Interrupt Flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                DBG                                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
-#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
-
-/********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
-#define  DBGMCU_CR_DBG_STOP                  0x00000002U
-#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
-#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
-
-#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
-#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U/*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U/*!<Bit 1 */
-
-/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            0x00000001U
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            0x00000002U
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            0x00000004U
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            0x00000020U
-#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           0x00000040U
-#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           0x00000080U
-#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           0x00000100U
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
-#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
-/* Old IWDGSTOP bit definition, maintained for legacy purpose */
-#define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
-
-/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        0x00000001U
-#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        0x00000002U
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        0x00010000U
-#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       0x00020000U
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       0x00040000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                                       USB_OTG			                        */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/
-#define USB_OTG_GOTGCTL_SRQSCS                  0x00000001U            /*!< Session request success */
-#define USB_OTG_GOTGCTL_SRQ                     0x00000002U            /*!< Session request */
-#define USB_OTG_GOTGCTL_HNGSCS                  0x00000100U            /*!< Host negotiation success */
-#define USB_OTG_GOTGCTL_HNPRQ                   0x00000200U            /*!< HNP request */
-#define USB_OTG_GOTGCTL_HSHNPEN                 0x00000400U            /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_DHNPEN                  0x00000800U            /*!< Device HNP enabled */
-#define USB_OTG_GOTGCTL_CIDSTS                  0x00010000U            /*!< Connector ID status */
-#define USB_OTG_GOTGCTL_DBCT                    0x00020000U            /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD                   0x00040000U            /*!< A-session valid */
-#define USB_OTG_GOTGCTL_BSVLD                   0x00080000U            /*!< B-session valid */
-
-/********************  Bit definition forUSB_OTG_HCFG register  ********************/
-
-#define USB_OTG_HCFG_FSLSPCS                 0x00000003U            /*!< FS/LS PHY clock select */
-#define USB_OTG_HCFG_FSLSPCS_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCFG_FSLSPCS_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCFG_FSLSS                   0x00000004U            /*!< FS- and LS-only support */
-
-/********************  Bit definition forUSB_OTG_DCFG register  ********************/
-
-#define USB_OTG_DCFG_DSPD                    0x00000003U            /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                  0x00000001U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DSPD_1                  0x00000002U            /*!<Bit 1 */
-#define USB_OTG_DCFG_NZLSOHSK                0x00000004U            /*!< Nonzero-length status OUT handshake */
-
-#define USB_OTG_DCFG_DAD                     0x000007F0U            /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                   0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DAD_1                   0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCFG_DAD_2                   0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCFG_DAD_3                   0x00000080U            /*!<Bit 3 */
-#define USB_OTG_DCFG_DAD_4                   0x00000100U            /*!<Bit 4 */
-#define USB_OTG_DCFG_DAD_5                   0x00000200U            /*!<Bit 5 */
-#define USB_OTG_DCFG_DAD_6                   0x00000400U            /*!<Bit 6 */
-
-#define USB_OTG_DCFG_PFIVL                   0x00001800U            /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PFIVL_1                 0x00001000U            /*!<Bit 1 */
-
-#define USB_OTG_DCFG_PERSCHIVL               0x03000000U            /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0             0x01000000U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PERSCHIVL_1             0x02000000U            /*!<Bit 1 */
-
-/********************  Bit definition forUSB_OTG_PCGCR register  ********************/
-#define USB_OTG_PCGCR_STPPCLK                 0x00000001U            /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK                0x00000002U            /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP                 0x00000010U            /*!< PHY suspended */
-
-/********************  Bit definition forUSB_OTG_GOTGINT register  ********************/
-#define USB_OTG_GOTGINT_SEDET                   0x00000004U            /*!< Session end detected */
-#define USB_OTG_GOTGINT_SRSSCHG                 0x00000100U            /*!< Session request success status change */
-#define USB_OTG_GOTGINT_HNSSCHG                 0x00000200U            /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET                  0x00020000U            /*!< Host negotiation detected */
-#define USB_OTG_GOTGINT_ADTOCHG                 0x00040000U            /*!< A-device timeout change */
-#define USB_OTG_GOTGINT_DBCDNE                  0x00080000U            /*!< Debounce done */
-
-/********************  Bit definition forUSB_OTG_DCTL register  ********************/
-#define USB_OTG_DCTL_RWUSIG                  0x00000001U            /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS                    0x00000002U            /*!< Soft disconnect */
-#define USB_OTG_DCTL_GINSTS                  0x00000004U            /*!< Global IN NAK status */
-#define USB_OTG_DCTL_GONSTS                  0x00000008U            /*!< Global OUT NAK status */
-
-#define USB_OTG_DCTL_TCTL                    0x00000070U            /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                  0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCTL_TCTL_1                  0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCTL_TCTL_2                  0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCTL_SGINAK                  0x00000080U            /*!< Set global IN NAK */
-#define USB_OTG_DCTL_CGINAK                  0x00000100U            /*!< Clear global IN NAK */
-#define USB_OTG_DCTL_SGONAK                  0x00000200U            /*!< Set global OUT NAK */
-#define USB_OTG_DCTL_CGONAK                  0x00000400U            /*!< Clear global OUT NAK */
-#define USB_OTG_DCTL_POPRGDNE                0x00000800U            /*!< Power-on programming done */
-
-/********************  Bit definition forUSB_OTG_HFIR register  ********************/
-#define USB_OTG_HFIR_FRIVL                   0x0000FFFFU            /*!< Frame interval */
-
-/********************  Bit definition forUSB_OTG_HFNUM register  ********************/
-#define USB_OTG_HFNUM_FRNUM                   0x0000FFFFU            /*!< Frame number */
-#define USB_OTG_HFNUM_FTREM                   0xFFFF0000U            /*!< Frame time remaining */
-
-/********************  Bit definition forUSB_OTG_DSTS register  ********************/
-#define USB_OTG_DSTS_SUSPSTS                 0x00000001U            /*!< Suspend status */
-
-#define USB_OTG_DSTS_ENUMSPD                 0x00000006U            /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_DSTS_ENUMSPD_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_DSTS_EERR                    0x00000008U            /*!< Erratic error */
-#define USB_OTG_DSTS_FNSOF                   0x003FFF00U            /*!< Frame number of the received SOF */
-
-/********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/
-#define USB_OTG_GAHBCFG_GINT                    0x00000001U            /*!< Global interrupt mask */
-
-#define USB_OTG_GAHBCFG_HBSTLEN                 0x0000001EU            /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_GAHBCFG_HBSTLEN_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_GAHBCFG_HBSTLEN_2               0x00000008U            /*!<Bit 2 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3               0x00000010U            /*!<Bit 3 */
-#define USB_OTG_GAHBCFG_DMAEN                   0x00000020U            /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL                 0x00000080U            /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL                0x00000100U            /*!< Periodic TxFIFO empty level */
-
-/********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/
-
-#define USB_OTG_GUSBCFG_TOCAL                   0x00000007U            /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TOCAL_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TOCAL_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_PHYSEL                  0x00000040U            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP                  0x00000100U            /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP                  0x00000200U            /*!< HNP-capable */
-
-#define USB_OTG_GUSBCFG_TRDT                    0x00003C00U            /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                  0x00000400U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TRDT_1                  0x00000800U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TRDT_2                  0x00001000U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_TRDT_3                  0x00002000U            /*!<Bit 3 */
-#define USB_OTG_GUSBCFG_PHYLPCS                 0x00008000U            /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS                0x00020000U            /*!< ULPI FS/LS select */
-#define USB_OTG_GUSBCFG_ULPIAR                  0x00040000U            /*!< ULPI Auto-resume */
-#define USB_OTG_GUSBCFG_ULPICSM                 0x00080000U            /*!< ULPI Clock SuspendM */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD              0x00100000U            /*!< ULPI External VBUS Drive */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI              0x00200000U            /*!< ULPI external VBUS indicator */
-#define USB_OTG_GUSBCFG_TSDPS                   0x00400000U            /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI                    0x00800000U            /*!< Indicator complement */
-#define USB_OTG_GUSBCFG_PTCI                    0x01000000U            /*!< Indicator pass through */
-#define USB_OTG_GUSBCFG_ULPIIPD                 0x02000000U            /*!< ULPI interface protect disable */
-#define USB_OTG_GUSBCFG_FHMOD                   0x20000000U            /*!< Forced host mode */
-#define USB_OTG_GUSBCFG_FDMOD                   0x40000000U            /*!< Forced peripheral mode */
-#define USB_OTG_GUSBCFG_CTXPKT                  0x80000000U            /*!< Corrupt Tx packet */
-
-/********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
-#define USB_OTG_GRSTCTL_CSRST                   0x00000001U            /*!< Core soft reset */
-#define USB_OTG_GRSTCTL_HSRST                   0x00000002U            /*!< HCLK soft reset */
-#define USB_OTG_GRSTCTL_FCRST                   0x00000004U            /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH                 0x00000010U            /*!< RxFIFO flush */
-#define USB_OTG_GRSTCTL_TXFFLSH                 0x00000020U            /*!< TxFIFO flush */
-
-#define USB_OTG_GRSTCTL_TXFNUM                  0x000007C0U            /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                0x00000040U            /*!<Bit 0 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                0x00000080U            /*!<Bit 1 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                0x00000100U            /*!<Bit 2 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                0x00000200U            /*!<Bit 3 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                0x00000400U            /*!<Bit 4 */
-#define USB_OTG_GRSTCTL_DMAREQ                  0x40000000U            /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL                  0x80000000U            /*!< AHB master idle */
-
-/********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/
-#define USB_OTG_DIEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPMSK_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPMSK_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPMSK_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPMSK_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPMSK_BIM                     0x00000200U            /*!< BNA interrupt mask */
-
-/********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/
-#define USB_OTG_HPTXSTS_PTXFSAVL                0x0000FFFFU            /*!< Periodic transmit data FIFO space available */
-
-#define USB_OTG_HPTXSTS_PTXQSAV                 0x00FF0000U            /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0               0x00010000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1               0x00020000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2               0x00040000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3               0x00080000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4               0x00100000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5               0x00200000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6               0x00400000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7               0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_HPTXSTS_PTXQTOP                 0xFF000000U            /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0               0x01000000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1               0x02000000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2               0x04000000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3               0x08000000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4               0x10000000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5               0x20000000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6               0x40000000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7               0x80000000U            /*!<Bit 7 */
-
-/********************  Bit definition forUSB_OTG_HAINT register  ********************/
-#define USB_OTG_HAINT_HAINT                   0x0000FFFFU            /*!< Channel interrupts */
-
-/********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/
-#define USB_OTG_DOEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPMSK_STUPM                   0x00000008U            /*!< SETUP phase done mask */
-#define USB_OTG_DOEPMSK_OTEPDM                  0x00000010U            /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received mask */
-#define USB_OTG_DOEPMSK_OPEM                    0x00000100U            /*!< OUT packet error mask */
-#define USB_OTG_DOEPMSK_BOIM                    0x00000200U            /*!< BNA interrupt mask */
-
-/********************  Bit definition forUSB_OTG_GINTSTS register  ********************/
-#define USB_OTG_GINTSTS_CMOD                    0x00000001U            /*!< Current mode of operation */
-#define USB_OTG_GINTSTS_MMIS                    0x00000002U            /*!< Mode mismatch interrupt */
-#define USB_OTG_GINTSTS_OTGINT                  0x00000004U            /*!< OTG interrupt */
-#define USB_OTG_GINTSTS_SOF                     0x00000008U            /*!< Start of frame */
-#define USB_OTG_GINTSTS_RXFLVL                  0x00000010U            /*!< RxFIFO nonempty */
-#define USB_OTG_GINTSTS_NPTXFE                  0x00000020U            /*!< Nonperiodic TxFIFO empty */
-#define USB_OTG_GINTSTS_GINAKEFF                0x00000040U            /*!< Global IN nonperiodic NAK effective */
-#define USB_OTG_GINTSTS_BOUTNAKEFF              0x00000080U            /*!< Global OUT NAK effective */
-#define USB_OTG_GINTSTS_ESUSP                   0x00000400U            /*!< Early suspend */
-#define USB_OTG_GINTSTS_USBSUSP                 0x00000800U            /*!< USB suspend */
-#define USB_OTG_GINTSTS_USBRST                  0x00001000U            /*!< USB reset */
-#define USB_OTG_GINTSTS_ENUMDNE                 0x00002000U            /*!< Enumeration done */
-#define USB_OTG_GINTSTS_ISOODRP                 0x00004000U            /*!< Isochronous OUT packet dropped interrupt */
-#define USB_OTG_GINTSTS_EOPF                    0x00008000U            /*!< End of periodic frame interrupt */
-#define USB_OTG_GINTSTS_IEPINT                  0x00040000U            /*!< IN endpoint interrupt */
-#define USB_OTG_GINTSTS_OEPINT                  0x00080000U            /*!< OUT endpoint interrupt */
-#define USB_OTG_GINTSTS_IISOIXFR                0x00100000U            /*!< Incomplete isochronous IN transfer */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       0x00200000U            /*!< Incomplete periodic transfer */
-#define USB_OTG_GINTSTS_DATAFSUSP               0x00400000U            /*!< Data fetch suspended */
-#define USB_OTG_GINTSTS_HPRTINT                 0x01000000U            /*!< Host port interrupt */
-#define USB_OTG_GINTSTS_HCINT                   0x02000000U            /*!< Host channels interrupt */
-#define USB_OTG_GINTSTS_PTXFE                   0x04000000U            /*!< Periodic TxFIFO empty */
-#define USB_OTG_GINTSTS_CIDSCHG                 0x10000000U            /*!< Connector ID status change */
-#define USB_OTG_GINTSTS_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt */
-#define USB_OTG_GINTSTS_SRQINT                  0x40000000U            /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT                  0x80000000U            /*!< Resume/remote wakeup detected interrupt */
-
-/********************  Bit definition forUSB_OTG_GINTMSK register  ********************/
-#define USB_OTG_GINTMSK_MMISM                   0x00000002U            /*!< Mode mismatch interrupt mask */
-#define USB_OTG_GINTMSK_OTGINT                  0x00000004U            /*!< OTG interrupt mask */
-#define USB_OTG_GINTMSK_SOFM                    0x00000008U            /*!< Start of frame mask */
-#define USB_OTG_GINTMSK_RXFLVLM                 0x00000010U            /*!< Receive FIFO nonempty mask */
-#define USB_OTG_GINTMSK_NPTXFEM                 0x00000020U            /*!< Nonperiodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_GINAKEFFM               0x00000040U            /*!< Global nonperiodic IN NAK effective mask */
-#define USB_OTG_GINTMSK_GONAKEFFM               0x00000080U            /*!< Global OUT NAK effective mask */
-#define USB_OTG_GINTMSK_ESUSPM                  0x00000400U            /*!< Early suspend mask */
-#define USB_OTG_GINTMSK_USBSUSPM                0x00000800U            /*!< USB suspend mask */
-#define USB_OTG_GINTMSK_USBRST                  0x00001000U            /*!< USB reset mask */
-#define USB_OTG_GINTMSK_ENUMDNEM                0x00002000U            /*!< Enumeration done mask */
-#define USB_OTG_GINTMSK_ISOODRPM                0x00004000U            /*!< Isochronous OUT packet dropped interrupt mask */
-#define USB_OTG_GINTMSK_EOPFM                   0x00008000U            /*!< End of periodic frame interrupt mask */
-#define USB_OTG_GINTMSK_EPMISM                  0x00020000U            /*!< Endpoint mismatch interrupt mask */
-#define USB_OTG_GINTMSK_IEPINT                  0x00040000U            /*!< IN endpoints interrupt mask */
-#define USB_OTG_GINTMSK_OEPINT                  0x00080000U            /*!< OUT endpoints interrupt mask */
-#define USB_OTG_GINTMSK_IISOIXFRM               0x00100000U            /*!< Incomplete isochronous IN transfer mask */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         0x00200000U            /*!< Incomplete periodic transfer mask */
-#define USB_OTG_GINTMSK_FSUSPM                  0x00400000U            /*!< Data fetch suspended mask */
-#define USB_OTG_GINTMSK_PRTIM                   0x01000000U            /*!< Host port interrupt mask */
-#define USB_OTG_GINTMSK_HCIM                    0x02000000U            /*!< Host channels interrupt mask */
-#define USB_OTG_GINTMSK_PTXFEM                  0x04000000U            /*!< Periodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_CIDSCHGM                0x10000000U            /*!< Connector ID status change mask */
-#define USB_OTG_GINTMSK_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt mask */
-#define USB_OTG_GINTMSK_SRQIM                   0x40000000U            /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM                    0x80000000U            /*!< Resume/remote wakeup detected interrupt mask */
-
-/********************  Bit definition forUSB_OTG_DAINT register  ********************/
-#define USB_OTG_DAINT_IEPINT                  0x0000FFFFU            /*!< IN endpoint interrupt bits */
-#define USB_OTG_DAINT_OEPINT                  0xFFFF0000U            /*!< OUT endpoint interrupt bits */
-
-/********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/
-#define USB_OTG_HAINTMSK_HAINTM                  0x0000FFFFU            /*!< Channel interrupt mask */
-
-/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
-#define USB_OTG_GRXSTSP_EPNUM                    0x0000000FU            /*!< IN EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_BCNT                     0x00007FF0U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID                     0x00018000U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS                   0x001E0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/
-#define USB_OTG_DAINTMSK_IEPM                    0x0000FFFFU            /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM                    0xFFFF0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for OTG register  ********************/
-
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition for OTG register  ********************/
-
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/
-#define USB_OTG_GRXFSIZ_RXFD                    0x0000FFFFU            /*!< RxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/
-#define USB_OTG_DVBUSDIS_VBUSDT                  0x0000FFFFU            /*!< Device VBUS discharge time */
-
-/********************  Bit definition for OTG register  ********************/
-#define USB_OTG_NPTXFSA                 0x0000FFFFU            /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD                  0xFFFF0000U            /*!< Nonperiodic TxFIFO depth */
-#define USB_OTG_TX0FSA                  0x0000FFFFU            /*!< Endpoint 0 transmit RAM start address */
-#define USB_OTG_TX0FD                   0xFFFF0000U            /*!< Endpoint 0 TxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
-#define USB_OTG_DVBUSPULSE_DVBUSP                  0x00000FFFU            /*!< Device VBUS pulsing time */
-
-/********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/
-#define USB_OTG_GNPTXSTS_NPTXFSAV                0x0000FFFFU            /*!< Nonperiodic TxFIFO space available */
-
-#define USB_OTG_GNPTXSTS_NPTQXSAV                0x00FF0000U            /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0              0x00010000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1              0x00020000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2              0x00040000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3              0x00080000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4              0x00100000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5              0x00200000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6              0x00400000U            /*!<Bit 6 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7              0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_GNPTXSTS_NPTXQTOP                0x7F000000U            /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0              0x01000000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1              0x02000000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2              0x04000000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3              0x08000000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4              0x10000000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5              0x20000000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6              0x40000000U            /*!<Bit 6 */
-
-/********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/
-#define USB_OTG_DTHRCTL_NONISOTHREN             0x00000001U            /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN                0x00000002U            /*!< ISO IN endpoint threshold enable */
-
-#define USB_OTG_DTHRCTL_TXTHRLEN                0x000007FCU            /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0              0x00000004U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1              0x00000008U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2              0x00000010U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3              0x00000020U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4              0x00000040U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5              0x00000080U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6              0x00000100U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7              0x00000200U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8              0x00000400U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_RXTHREN                 0x00010000U            /*!< Receive threshold enable */
-
-#define USB_OTG_DTHRCTL_RXTHRLEN                0x03FE0000U            /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0              0x00020000U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1              0x00040000U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2              0x00080000U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3              0x00100000U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4              0x00200000U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5              0x00400000U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6              0x00800000U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7              0x01000000U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8              0x02000000U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_ARPEN                   0x08000000U            /*!< Arbiter parking enable */
-
-/********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM               0x0000FFFFU            /*!< IN EP Tx FIFO empty interrupt mask bits */
-
-/********************  Bit definition forUSB_OTG_DEACHINT register  ********************/
-#define USB_OTG_DEACHINT_IEP1INT                 0x00000002U            /*!< IN endpoint 1interrupt bit */
-#define USB_OTG_DEACHINT_OEP1INT                 0x00020000U            /*!< OUT endpoint 1 interrupt bit */
-
-/********************  Bit definition forUSB_OTG_GCCFG register  ********************/
-#define USB_OTG_GCCFG_PWRDWN                  0x00010000U            /*!< Power down */
-#define USB_OTG_GCCFG_I2CPADEN                0x00020000U            /*!< Enable I2C bus connection for the external I2C PHY interface */
-#define USB_OTG_GCCFG_VBUSASEN                0x00040000U            /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_VBUSBSEN                0x00080000U            /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_SOFOUTEN                0x00100000U            /*!< SOF output enable */
-#define USB_OTG_GCCFG_NOVBUSSENS              0x00200000U            /*!< VBUS sensing disable option */
-
-/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
-#define USB_OTG_DEACHINTMSK_IEP1INTM                0x00000002U            /*!< IN Endpoint 1 interrupt mask bit */
-#define USB_OTG_DEACHINTMSK_OEP1INTM                0x00020000U            /*!< OUT Endpoint 1 interrupt mask bit */
-
-/********************  Bit definition forUSB_OTG_CID register  ********************/
-#define USB_OTG_CID_PRODUCT_ID              0xFFFFFFFFU            /*!< Product ID field */
-
-/********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/
-#define USB_OTG_DIEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPEACHMSK1_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
-
-/********************  Bit definition forUSB_OTG_HPRT register  ********************/
-#define USB_OTG_HPRT_PCSTS                   0x00000001U            /*!< Port connect status */
-#define USB_OTG_HPRT_PCDET                   0x00000002U            /*!< Port connect detected */
-#define USB_OTG_HPRT_PENA                    0x00000004U            /*!< Port enable */
-#define USB_OTG_HPRT_PENCHNG                 0x00000008U            /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA                    0x00000010U            /*!< Port overcurrent active */
-#define USB_OTG_HPRT_POCCHNG                 0x00000020U            /*!< Port overcurrent change */
-#define USB_OTG_HPRT_PRES                    0x00000040U            /*!< Port resume */
-#define USB_OTG_HPRT_PSUSP                   0x00000080U            /*!< Port suspend */
-#define USB_OTG_HPRT_PRST                    0x00000100U            /*!< Port reset */
-
-#define USB_OTG_HPRT_PLSTS                   0x00000C00U            /*!< Port line status */
-#define USB_OTG_HPRT_PLSTS_0                 0x00000400U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PLSTS_1                 0x00000800U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PPWR                    0x00001000U            /*!< Port power */
-
-#define USB_OTG_HPRT_PTCTL                   0x0001E000U            /*!< Port test control */
-#define USB_OTG_HPRT_PTCTL_0                 0x00002000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PTCTL_1                 0x00004000U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PTCTL_2                 0x00008000U            /*!<Bit 2 */
-#define USB_OTG_HPRT_PTCTL_3                 0x00010000U            /*!<Bit 3 */
-
-#define USB_OTG_HPRT_PSPD                    0x00060000U            /*!< Port speed */
-#define USB_OTG_HPRT_PSPD_0                  0x00020000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PSPD_1                  0x00040000U            /*!<Bit 1 */
-
-/********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/
-#define USB_OTG_DOEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DOEPEACHMSK1_TXFURM                  0x00000100U            /*!< OUT packet error mask */
-#define USB_OTG_DOEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_BERRM                   0x00001000U            /*!< Bubble error interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NYETM                   0x00004000U            /*!< NYET interrupt mask */
-
-/********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/
-#define USB_OTG_HPTXFSIZ_PTXSA                   0x0000FFFFU            /*!< Host periodic TxFIFO start address */
-#define USB_OTG_HPTXFSIZ_PTXFD                   0xFFFF0000U            /*!< Host periodic TxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/
-#define USB_OTG_DIEPCTL_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
-#define USB_OTG_DIEPCTL_USBAEP                  0x00008000U            /*!< USB active endpoint */
-#define USB_OTG_DIEPCTL_EONUM_DPID              0x00010000U            /*!< Even/odd frame */
-#define USB_OTG_DIEPCTL_NAKSTS                  0x00020000U            /*!< NAK status */
-
-#define USB_OTG_DIEPCTL_EPTYP                   0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_DIEPCTL_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_STALL                   0x00200000U            /*!< STALL handshake */
-
-#define USB_OTG_DIEPCTL_TXFNUM                  0x03C00000U            /*!< TxFIFO number */
-#define USB_OTG_DIEPCTL_TXFNUM_0                0x00400000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                0x00800000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                0x01000000U            /*!<Bit 2 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                0x02000000U            /*!<Bit 3 */
-#define USB_OTG_DIEPCTL_CNAK                    0x04000000U            /*!< Clear NAK */
-#define USB_OTG_DIEPCTL_SNAK                    0x08000000U            /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          0x10000000U            /*!< Set DATA0 PID */
-#define USB_OTG_DIEPCTL_SODDFRM                 0x20000000U            /*!< Set odd frame */
-#define USB_OTG_DIEPCTL_EPDIS                   0x40000000U            /*!< Endpoint disable */
-#define USB_OTG_DIEPCTL_EPENA                   0x80000000U            /*!< Endpoint enable */
-
-/********************  Bit definition forUSB_OTG_HCCHAR register  ********************/
-#define USB_OTG_HCCHAR_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
-
-#define USB_OTG_HCCHAR_EPNUM                   0x00007800U            /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPNUM_1                 0x00001000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_EPNUM_2                 0x00002000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_EPNUM_3                 0x00004000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_EPDIR                   0x00008000U            /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV                   0x00020000U            /*!< Low-speed device */
-
-#define USB_OTG_HCCHAR_EPTYP                   0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_MC                      0x00300000U            /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                    0x00100000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_MC_1                    0x00200000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_DAD                     0x1FC00000U            /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                   0x00400000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_DAD_1                   0x00800000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_DAD_2                   0x01000000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_DAD_3                   0x02000000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_DAD_4                   0x04000000U            /*!<Bit 4 */
-#define USB_OTG_HCCHAR_DAD_5                   0x08000000U            /*!<Bit 5 */
-#define USB_OTG_HCCHAR_DAD_6                   0x10000000U            /*!<Bit 6 */
-#define USB_OTG_HCCHAR_ODDFRM                  0x20000000U            /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS                   0x40000000U            /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA                   0x80000000U            /*!< Channel enable */
-
-/********************  Bit definition forUSB_OTG_HCSPLT register  ********************/
-
-#define USB_OTG_HCSPLT_PRTADDR                 0x0000007FU            /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_PRTADDR_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_PRTADDR_2               0x00000004U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_PRTADDR_3               0x00000008U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_PRTADDR_4               0x00000010U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_PRTADDR_5               0x00000020U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_PRTADDR_6               0x00000040U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_HUBADDR                 0x00003F80U            /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0               0x00000080U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_HUBADDR_1               0x00000100U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_HUBADDR_2               0x00000200U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_HUBADDR_3               0x00000400U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_HUBADDR_4               0x00000800U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_HUBADDR_5               0x00001000U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_HUBADDR_6               0x00002000U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_XACTPOS                 0x0000C000U            /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0               0x00004000U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_XACTPOS_1               0x00008000U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_COMPLSPLT               0x00010000U            /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN                 0x80000000U            /*!< Split enable */
-
-/********************  Bit definition forUSB_OTG_HCINT register  ********************/
-#define USB_OTG_HCINT_XFRC                    0x00000001U            /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH                     0x00000002U            /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINT_STALL                   0x00000008U            /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK                     0x00000010U            /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK                     0x00000020U            /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET                    0x00000040U            /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR                   0x00000080U            /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR                   0x00000100U            /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR                   0x00000200U            /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR                   0x00000400U            /*!< Data toggle error */
-
-/********************  Bit definition forUSB_OTG_DIEPINT register  ********************/
-#define USB_OTG_DIEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_TOC                     0x00000008U            /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE                  0x00000010U            /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNE                  0x00000040U            /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE                    0x00000080U            /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN              0x00000100U            /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA                     0x00000200U            /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS               0x00000800U            /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR                    0x00001000U            /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK                     0x00002000U            /*!< NAK interrupt */
-
-/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
-#define USB_OTG_HCINTMSK_XFRCM                   0x00000001U            /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM                    0x00000002U            /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM                  0x00000008U            /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM                    0x00000010U            /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM                    0x00000020U            /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET                    0x00000040U            /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM                  0x00000080U            /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM                  0x00000100U            /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM                  0x00000200U            /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM                  0x00000400U            /*!< Data toggle error mask */
-
-/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
-
-#define USB_OTG_DIEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT                  0x60000000U            /*!< Packet count */
-/********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/
-#define USB_OTG_HCTSIZ_XFRSIZ                    0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT                    0x1FF80000U            /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING                    0x80000000U            /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID                      0x60000000U            /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                    0x20000000U            /*!<Bit 0 */
-#define USB_OTG_HCTSIZ_DPID_1                    0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/
-#define USB_OTG_DIEPDMA_DMAADDR                  0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition forUSB_OTG_HCDMA register  ********************/
-#define USB_OTG_HCDMA_DMAADDR                    0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/
-#define USB_OTG_DTXFSTS_INEPTFSAV                0x0000FFFFU            /*!< IN endpoint TxFIFO space avail */
-
-/********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/
-#define USB_OTG_DIEPTXF_INEPTXSA                 0x0000FFFFU            /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD                 0xFFFF0000U            /*!< IN endpoint TxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/
-
-#define USB_OTG_DOEPCTL_MPSIZ                     0x000007FFU            /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP                    0x00008000U            /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS                    0x00020000U            /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            0x10000000U            /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM                   0x20000000U            /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP                     0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                   0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DOEPCTL_EPTYP_1                   0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_SNPM                      0x00100000U            /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL                     0x00200000U            /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK                      0x04000000U            /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK                      0x08000000U            /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS                     0x40000000U            /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA                     0x80000000U            /*!< Endpoint enable */
-
-/********************  Bit definition forUSB_OTG_DOEPINT register  ********************/
-#define USB_OTG_DOEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_STUP                    0x00000008U            /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS                 0x00000010U            /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_NYET                    0x00004000U            /*!< NYET interrupt */
-
-/********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/
-
-#define USB_OTG_DOEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-
-#define USB_OTG_DOEPTSIZ_STUPCNT                 0x60000000U            /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0               0x20000000U            /*!<Bit 0 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1               0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition for PCGCCTL register  ********************/
-#define USB_OTG_PCGCCTL_STOPCLK                 0x00000001U            /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK                 0x00000002U            /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP                 0x00000010U            /*!<Bit 1 */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
- 
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
- 
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************** DMA Instances *******************************/
-#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
-                                              ((INSTANCE) == DMA1_Stream1) || \
-                                              ((INSTANCE) == DMA1_Stream2) || \
-                                              ((INSTANCE) == DMA1_Stream3) || \
-                                              ((INSTANCE) == DMA1_Stream4) || \
-                                              ((INSTANCE) == DMA1_Stream5) || \
-                                              ((INSTANCE) == DMA1_Stream6) || \
-                                              ((INSTANCE) == DMA1_Stream7) || \
-                                              ((INSTANCE) == DMA2_Stream0) || \
-                                              ((INSTANCE) == DMA2_Stream1) || \
-                                              ((INSTANCE) == DMA2_Stream2) || \
-                                              ((INSTANCE) == DMA2_Stream3) || \
-                                              ((INSTANCE) == DMA2_Stream4) || \
-                                              ((INSTANCE) == DMA2_Stream5) || \
-                                              ((INSTANCE) == DMA2_Stream6) || \
-                                              ((INSTANCE) == DMA2_Stream7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOH))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2) || \
-                                       ((INSTANCE) == I2C3))
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI1) || \
-                                    ((INSTANCE) == SPI2) || \
-                                    ((INSTANCE) == SPI3) || \
-                                    ((INSTANCE) == SPI4) || \
-                                    ((INSTANCE) == SPI5))
-
-/*************************** I2S Extended Instances ***************************/
-#define IS_I2S_ALL_INSTANCE_EXT(PERIPH)  (((INSTANCE) == SPI2)    || \
-                                          ((INSTANCE) == SPI3)    || \
-                                          ((INSTANCE) == I2S2ext) || \
-                                          ((INSTANCE) == I2S3ext))
-
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3) || \
-                                       ((INSTANCE) == SPI4) || \
-                                       ((INSTANCE) == SPI5))
-/*************************** SPI Extended Instances ***************************/
-#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1)    || \
-                                           ((INSTANCE) == SPI2)    || \
-                                           ((INSTANCE) == SPI3)    || \
-                                           ((INSTANCE) == SPI4)    || \
-                                           ((INSTANCE) == SPI5)    || \
-                                           ((INSTANCE) == I2S2ext) || \
-                                           ((INSTANCE) == I2S3ext))
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
-                                   ((INSTANCE) == TIM2)   || \
-                                   ((INSTANCE) == TIM3)   || \
-                                   ((INSTANCE) == TIM4)   || \
-                                   ((INSTANCE) == TIM5)   || \
-                                   ((INSTANCE) == TIM9)   || \
-                                   ((INSTANCE) == TIM10)  || \
-                                   ((INSTANCE) == TIM11))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
-                                         ((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM9)  || \
-                                         ((INSTANCE) == TIM10) || \
-                                         ((INSTANCE) == TIM11))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM9))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5))
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5))
-
-/******************** TIM Instances : Advanced-control timers *****************/
-#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5))
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5))
-
-/************ TIM Instances : DMA requests generation (COMDE) *****************/
-#define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5)) 
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                             ((INSTANCE) == TIM2) || \
-                                             ((INSTANCE) == TIM3) || \
-                                             ((INSTANCE) == TIM4) || \
-                                             ((INSTANCE) == TIM5))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM9))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM9))
-
-/********************** TIM Instances : 32 bit Counter ************************/
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
-                                              ((INSTANCE) == TIM5))
-
-/***************** TIM Instances : external trigger input availabe ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                        ((INSTANCE) == TIM2) || \
-                                        ((INSTANCE) == TIM3) || \
-                                        ((INSTANCE) == TIM4) || \
-                                        ((INSTANCE) == TIM5))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM11))
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM1) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM5) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-/************ TIM Instances : complementary output(s) available ***************/
-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
-   ((((INSTANCE) == TIM1) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3))))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART6))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART6))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART6))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART6))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART6))     
-
-/*********************** PCD Instances ****************************************/
-#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
-
-/*********************** HCD Instances ****************************************/
-#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/****************************** SDIO Instances ********************************/
-#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
-
-/****************************** USB Exported Constants ************************/
-#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                8U
-#define USB_OTG_FS_MAX_IN_ENDPOINTS                    4U    /* Including EP0 */
-#define USB_OTG_FS_MAX_OUT_ENDPOINTS                   4U    /* Including EP0 */
-#define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32F411xE_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/cmsis/stm32f412cx.h b/stmhal/cmsis/stm32f412cx.h
deleted file mode 100644
index 07243e15e5..0000000000
--- a/stmhal/cmsis/stm32f412cx.h
+++ /dev/null
@@ -1,6743 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f412cx.h
-  * @author  MCD Application Team
-  * @version V2.5.1
-  * @date    28-June-2016
-  * @brief   CMSIS STM32F412Cx Device Peripheral Access Layer Header File. 
-  *
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - peripherals registers declarations and bits definition
-  *           - Macros to access peripheral’s registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f412cx
-  * @{
-  */
-    
-#ifndef __STM32F412Cx_H
-#define __STM32F412Cx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-  
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-
-/**
-  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
-  */
-#define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */
-#define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */
-#define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1U       /*!< FPU present                                   */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32F4XX Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-typedef enum
-{
-/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
-  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
-/******  STM32 specific Interrupt Numbers **********************************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
-  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
-  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
-  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
-  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
-  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
-  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
-  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
-  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
-  ADC_IRQn                    = 18,     /*!< ADC1 global Interrupts                                            */
-  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
-  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
-  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
-  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
-  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
-  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
-  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
-  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */
-  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
-  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
-  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
-  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
-  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
-  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
-  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
-  TIM6_IRQn                   = 54,     /*!< TIM6 global interrupt                                             */
-  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
-  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
-  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
-  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
-  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
-  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
-  DFSDM1_FLT0_IRQn            = 61,     /*!< DFSDM1 Filter 0 global Interrupt                                  */
-  DFSDM1_FLT1_IRQn            = 62,     /*!< DFSDM1 Filter 1 global Interrupt                                  */
-  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
-  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
-  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
-  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
-  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
-  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
-  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
-  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
-  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
-  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
-  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
-  RNG_IRQn                    = 80,     /*!< RNG global Interrupt                                              */
-  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
-  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
-  SPI5_IRQn                   = 85,      /*!< SPI5 global Interrupt                                            */
-  FMPI2C1_EV_IRQn             = 95,     /*!< FMPI2C1 Event Interrupt                                           */
-  FMPI2C1_ER_IRQn             = 96      /*!< FMPI2C1 Error Interrupt                                           */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
-#include "system_stm32f4xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */
-  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
-  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
-  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
-  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
-  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
-  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
-  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
-  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
-  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
-  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
-  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
-  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
-  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
-  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
-  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
-                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief Controller Area Network TxMailBox 
-  */
-
-typedef struct
-{
-  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
-  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
-  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
-  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
-} CAN_TxMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FIFOMailBox 
-  */
-  
-typedef struct
-{
-  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
-  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
-  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
-  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
-} CAN_FIFOMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FilterRegister 
-  */
-  
-typedef struct
-{
-  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
-  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
-} CAN_FilterRegister_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
-  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
-  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
-  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
-  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
-  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
-  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
-  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
-  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
-  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
-  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
-  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
-  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
-  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
-  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
-  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
-  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
-  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
-  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
-  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
-  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */ 
-  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
-} CAN_TypeDef;
-
-/** 
-  * @brief CRC calculation unit 
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
-  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */
-  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
-  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
-  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
-}CRC_TypeDef;
-
-/**
-  * @brief DFSDM module registers
-  */
-typedef struct
-{
-  __IO uint32_t FLTCR1;      /*!< DFSDM control register1,                          Address offset: 0x100 */
-  __IO uint32_t FLTCR2;      /*!< DFSDM control register2,                          Address offset: 0x104 */
-  __IO uint32_t FLTISR;      /*!< DFSDM interrupt and status register,              Address offset: 0x108 */
-  __IO uint32_t FLTICR;      /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */
-  __IO uint32_t FLTJCHGR;    /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */
-  __IO uint32_t FLTFCR;      /*!< DFSDM filter control register,                    Address offset: 0x114 */
-  __IO uint32_t FLTJDATAR;   /*!< DFSDM data register for injected group,           Address offset: 0x118 */
-  __IO uint32_t FLTRDATAR;   /*!< DFSDM data register for regular group,            Address offset: 0x11C */
-  __IO uint32_t FLTAWHTR;    /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */
-  __IO uint32_t FLTAWLTR;    /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */
-  __IO uint32_t FLTAWSR;     /*!< DFSDM analog watchdog status register             Address offset: 0x128 */
-  __IO uint32_t FLTAWCFR;    /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */
-  __IO uint32_t FLTEXMAX;    /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */
-  __IO uint32_t FLTEXMIN;    /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */
-  __IO uint32_t FLTCNVTIMR;  /*!< DFSDM conversion timer,                           Address offset: 0x138 */
-} DFSDM_Filter_TypeDef;
-
-/**
-  * @brief DFSDM channel configuration registers
-  */
-typedef struct
-{
-  __IO uint32_t CHCFGR1;     /*!< DFSDM channel configuration register1,            Address offset: 0x00 */
-  __IO uint32_t CHCFGR2;     /*!< DFSDM channel configuration register2,            Address offset: 0x04 */
-  __IO uint32_t CHAWSCDR;    /*!< DFSDM channel analog watchdog and
-                                  short circuit detector register,                  Address offset: 0x08 */
-  __IO uint32_t CHWDATAR;    /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */
-  __IO uint32_t CHDATINR;    /*!< DFSDM channel data input register,                Address offset: 0x10 */
-} DFSDM_Channel_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-typedef struct
-{
-  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
-  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
-  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
-  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
-  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
-  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
-  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
-  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
-  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
-} DMA_Stream_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
-  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
-  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
-  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
-} DMA_TypeDef;
-
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
-  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
-  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
-  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
-  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
-  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-
-typedef struct
-{
-  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */
-  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */
-  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */
-  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */
-  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */
-  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief General Purpose I/O
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
-  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
-  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
-  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
-  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
-  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
-  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
-  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/** 
-  * @brief System configuration controller
-  */
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */ 
-  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
-  uint32_t      RESERVED1[2]; /*!< Reserved, 0x24-0x28                                                          */ 
-  __IO uint32_t CFGR;         /*!< SYSCFG Configuration register,                     Address offset: 0x2C      */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */
-  __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */
-  __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */
-  __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */
-  __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */
-  __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
-  __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
-  __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
-  __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */
-} I2C_TypeDef;
-
-/**
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< FMPI2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< FMPI2C Control register 2,            Address offset: 0x04 */
-  __IO uint32_t OAR1;        /*!< FMPI2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;        /*!< FMPI2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;     /*!< FMPI2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR;    /*!< FMPI2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;         /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;         /*!< FMPI2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;        /*!< FMPI2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;        /*!< FMPI2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;        /*!< FMPI2C Transmit data register,        Address offset: 0x28 */
-} FMPI2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
-  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
-  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
-  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
-  uint32_t      RESERVED0[2];     /*!< Reserved, 0x18-0x1C                                                            */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
-  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
-  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
-  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
-  uint32_t      RESERVED2[2];     /*!< Reserved, 0x38-0x3C                                                            */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
-  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
-  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
-  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
-  uint32_t      RESERVED4[2];     /*!< Reserved, 0x58-0x5C                                                            */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
-  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
-  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
-  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
-  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
-  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
-  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
-  uint32_t      RESERVED7;     /*!< Reserved, 0x84                                                                    */
-  __IO uint32_t DCKCFGR;       /*!< RCC Dedicated Clocks configuration register,                 Address offset: 0x8C */
-  __IO uint32_t CKGATENR;       /*!< RCC Clocks Gated ENable Register,                           Address offset: 0x90 */
-  __IO uint32_t DCKCFGR2;      /*!< RCC Dedicated Clocks configuration register 2,               Address offset: 0x94 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-
-typedef struct
-{
-  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
-  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
-  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
-  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
-  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
-  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
-  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */
-  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
-  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */
-  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
-  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */
-  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */
-  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */
-  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */
-  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
-  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */
-  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
-  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
-  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
-  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
-  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
-  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
-  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
-  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
-  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
-  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
-  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
-  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
-  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
-  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
-  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
-  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
-  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
-  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
-  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
-  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
-  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
-} RTC_TypeDef;
-
-
-/** 
-  * @brief SD host Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t POWER;          /*!< SDIO power control register,    Address offset: 0x00 */
-  __IO uint32_t CLKCR;          /*!< SDI clock control register,     Address offset: 0x04 */
-  __IO uint32_t ARG;            /*!< SDIO argument register,         Address offset: 0x08 */
-  __IO uint32_t CMD;            /*!< SDIO command register,          Address offset: 0x0C */
-  __I uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */
-  __I uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */
-  __I uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */
-  __I uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */
-  __I uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */
-  __IO uint32_t DTIMER;         /*!< SDIO data timer register,       Address offset: 0x24 */
-  __IO uint32_t DLEN;           /*!< SDIO data length register,      Address offset: 0x28 */
-  __IO uint32_t DCTRL;          /*!< SDIO data control register,     Address offset: 0x2C */
-  __I uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */
-  __I uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */
-  __IO uint32_t ICR;            /*!< SDIO interrupt clear register,  Address offset: 0x38 */
-  __IO uint32_t MASK;           /*!< SDIO mask register,             Address offset: 0x3C */
-  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
-  __I uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */
-  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
-  __IO uint32_t FIFO;           /*!< SDIO data FIFO register,        Address offset: 0x80 */
-} SDIO_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
-  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
-  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
-  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-
-/** 
-  * @brief RNG
-  */
-  
-typedef struct 
-{
-  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
-  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
-  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
-} RNG_TypeDef;
-
-
-/** 
-  * @brief USB_OTG_Core_Registers
-  */
-typedef struct
-{
-  __IO uint32_t GOTGCTL;              /*!<  USB_OTG Control and Status Register            000h*/
-  __IO uint32_t GOTGINT;              /*!<  USB_OTG Interrupt Register                     004h*/
-  __IO uint32_t GAHBCFG;              /*!<  Core AHB Configuration Register                008h*/
-  __IO uint32_t GUSBCFG;              /*!<  Core USB Configuration Register                00Ch*/
-  __IO uint32_t GRSTCTL;              /*!<  Core Reset Register                            010h*/
-  __IO uint32_t GINTSTS;              /*!<  Core Interrupt Register                        014h*/
-  __IO uint32_t GINTMSK;              /*!<  Core Interrupt Mask Register                   018h*/
-  __IO uint32_t GRXSTSR;              /*!<  Receive Sts Q Read Register                    01Ch*/
-  __IO uint32_t GRXSTSP;              /*!<  Receive Sts Q Read & POP Register              020h*/
-  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                      024h*/
-  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!<  EP0 / Non Periodic Tx FIFO Size Register       028h*/
-  __IO uint32_t HNPTXSTS;             /*!<  Non Periodic Tx FIFO/Queue Sts reg             02Ch*/
-  uint32_t Reserved30[2];             /*!< Reserved                                        030h*/
-  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                     038h*/
-  __IO uint32_t CID;                  /*!< User ID Register                                03Ch*/
-  uint32_t  Reserved5[3];             /*!< Reserved                                        040h-048h*/
-  __IO uint32_t GHWCFG3;              /*!< User HW config3                                 04Ch*/
-  uint32_t  Reserved6;                /*!< Reserved                                        050h*/ 
-  __IO uint32_t GLPMCFG;              /*!< LPM Register                                    054h*/
-  uint32_t  Reserved;                 /*!< Reserved                                     058h */
-  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register                  05Ch*/
-  uint32_t  Reserved43[40];           /*!< Reserved                                        058h-0FFh*/
-  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg                  100h*/
-  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */
-} USB_OTG_GlobalTypeDef;
-
-
-/** 
-  * @brief USB_OTG_device_Registers
-  */
-typedef struct 
-{
-  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */
-  __IO uint32_t DCTL;            /*!< dev Control Register         804h */
-  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */
-  uint32_t Reserved0C;           /*!< Reserved                     80Ch */
-  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */
-  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */
-  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */
-  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */
-  uint32_t  Reserved20;          /*!< Reserved                     820h */
-  uint32_t Reserved9;            /*!< Reserved                     824h */
-  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */
-  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */
-  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */
-  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */
-  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */
-  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */
-  uint32_t Reserved40;           /*!< dedicated EP mask            840h */
-  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */
-  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */
-  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */
-} USB_OTG_DeviceTypeDef;
-
-
-/** 
-  * @brief USB_OTG_IN_Endpoint-Specific_Register
-  */
-typedef struct 
-{
-  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */
-  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */
-  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */
-  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */
-  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */
-  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */
-  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
-  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
-} USB_OTG_INEndpointTypeDef;
-
-
-/** 
-  * @brief USB_OTG_OUT_Endpoint-Specific_Registers
-  */
-typedef struct 
-{
-  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */
-  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */
-  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */
-  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */
-  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */
-  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */
-  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
-} USB_OTG_OUTEndpointTypeDef;
-
-
-/** 
-  * @brief USB_OTG_Host_Mode_Register_Structures
-  */
-typedef struct 
-{
-  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */
-  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */
-  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */
-  uint32_t Reserved40C;           /*!< Reserved                             40Ch */
-  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */
-  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */
-  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */
-} USB_OTG_HostTypeDef;
-
-
-/** 
-  * @brief USB_OTG_Host_Channel_Specific_Registers
-  */
-typedef struct
-{
-  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */
-  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */
-  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */
-  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */
-  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */
-  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */
-  uint32_t Reserved[2];           /*!< Reserved                                      */
-} USB_OTG_HostChannelTypeDef;
-
-    
-/** 
-  * @brief Peripheral_memory_map
-  */
-#define FLASH_BASE            0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region                         */
-#define SRAM1_BASE            0x20000000U /*!< SRAM1(256 KB) base address in the alias region                             */
-#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region                                */
-
-#define SRAM1_BB_BASE         0x22000000U /*!< SRAM1(256 KB) base address in the bit-band region                             */
-#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region                                */
-#define FLASH_END             0x080FFFFFU /*!< FLASH end address                                                             */
-
-/* Legacy defines */
-#define SRAM_BASE             SRAM1_BASE
-#define SRAM_BB_BASE          SRAM1_BB_BASE
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000U)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)
-#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800U)
-#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00U)
-#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000U)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)
-#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400U)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)
-#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000U)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)
-#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)
-#define FMPI2C1_BASE          (APB1PERIPH_BASE + 0x6000U)
-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)
-#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800U)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)
-
-/*!< APB2 peripherals */
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000U)
-#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400U)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x1000U)
-#define USART6_BASE           (APB2PERIPH_BASE + 0x1400U)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000U)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x2300U)
-#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00U)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)
-#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400U)
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800U)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00U)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000U)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400U)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800U)
-#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000U)
-#define DFSDM1_BASE           (APB2PERIPH_BASE + 0x6000U)
-#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00U)
-#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20U)
-#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40U)
-#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60U)
-#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100U)
-#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180U)
-
-/*!< AHB1 peripherals */
-#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000U)
-#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400U)
-#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800U)
-#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00U)
-#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000U)
-#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400U)
-#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800U)
-#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00U)
-#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)
-#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800U)
-#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00U)
-#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000U)
-#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010U)
-#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028U)
-#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040U)
-#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058U)
-#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070U)
-#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088U)
-#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0U)
-#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8U)
-#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400U)
-#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010U)
-#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028U)
-#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040U)
-#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058U)
-#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070U)
-#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088U)
-#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0U)
-#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)
-
-/*!< AHB2 peripherals */
-#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800U)
-
-/* Debug MCU registers base address */
-#define DBGMCU_BASE           0xE0042000U
-
-/*!< USB registers base address */
-#define USB_OTG_FS_PERIPH_BASE               0x50000000U
-
-#define USB_OTG_GLOBAL_BASE                  0x000U
-#define USB_OTG_DEVICE_BASE                  0x800U
-#define USB_OTG_IN_ENDPOINT_BASE             0x900U
-#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U
-#define USB_OTG_EP_REG_SIZE                  0x20U
-#define USB_OTG_HOST_BASE                    0x400U
-#define USB_OTG_HOST_PORT_BASE               0x440U
-#define USB_OTG_HOST_CHANNEL_BASE            0x500U
-#define USB_OTG_HOST_CHANNEL_SIZE            0x20U
-#define USB_OTG_PCGCCTL_BASE                 0xE00U
-#define USB_OTG_FIFO_BASE                    0x1000U
-#define USB_OTG_FIFO_SIZE                    0x1000U
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
-#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
-#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
-#define FMPI2C1             ((FMPI2C_TypeDef *) FMPI2C1_BASE)
-#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
-#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
-#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define USART6              ((USART_TypeDef *) USART6_BASE)
-#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define SPI4                ((SPI_TypeDef *) SPI4_BASE)
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-#define SPI5                ((SPI_TypeDef *) SPI5_BASE)
-#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
-#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
-#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
-#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
-#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
-#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
-#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
-#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
-#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
-#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
-#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
-#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
-#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
-#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
-#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
-#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
-#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
-#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
-#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
-#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
-#define RNG                 ((RNG_TypeDef *) RNG_BASE)
-
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers_Bits_Definition               */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Analog to Digital Converter                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          0x00000001U       /*!<Analog watchdog flag */
-#define  ADC_SR_EOC                          0x00000002U       /*!<End of conversion */
-#define  ADC_SR_JEOC                         0x00000004U       /*!<Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        0x00000008U       /*!<Injected channel Start flag */
-#define  ADC_SR_STRT                         0x00000010U       /*!<Regular channel Start flag */
-#define  ADC_SR_OVR                          0x00000020U       /*!<Overrun flag */
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
-#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels */
-#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels */
-#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution) */
-#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
-  
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion */
-#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode */
-#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC) */
-#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection */
-#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment */
-#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      0xFFFFU            /*!<Injected data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag */
-#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion */
-#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag */
-#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag */
-#define  ADC_CSR_DOVR1                       0x00000020U        /*!<ADC1 DMA overrun  flag */
-#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag */
-#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion */
-#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag */
-#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag */
-#define  ADC_CSR_DOVR2                       0x00002000U        /*!<ADC2 DMA overrun  flag */
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
-#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
-#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
-#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
-#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
-
-/*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                      0x0000FFFFU         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                      0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Controller Area Network                            */
-/*                                                                            */
-/******************************************************************************/
-/*!<CAN control and status registers */
-/*******************  Bit definition for CAN_MCR register  ********************/
-#define  CAN_MCR_INRQ                        0x00000001U        /*!<Initialization Request */
-#define  CAN_MCR_SLEEP                       0x00000002U        /*!<Sleep Mode Request */
-#define  CAN_MCR_TXFP                        0x00000004U        /*!<Transmit FIFO Priority */
-#define  CAN_MCR_RFLM                        0x00000008U        /*!<Receive FIFO Locked Mode */
-#define  CAN_MCR_NART                        0x00000010U        /*!<No Automatic Retransmission */
-#define  CAN_MCR_AWUM                        0x00000020U        /*!<Automatic Wakeup Mode */
-#define  CAN_MCR_ABOM                        0x00000040U        /*!<Automatic Bus-Off Management */
-#define  CAN_MCR_TTCM                        0x00000080U        /*!<Time Triggered Communication Mode */
-#define  CAN_MCR_RESET                       0x00008000U        /*!<bxCAN software master reset */
-#define  CAN_MCR_DBF                         0x00010000U        /*!<bxCAN Debug freeze */
-/*******************  Bit definition for CAN_MSR register  ********************/
-#define  CAN_MSR_INAK                        0x0001U            /*!<Initialization Acknowledge */
-#define  CAN_MSR_SLAK                        0x0002U            /*!<Sleep Acknowledge */
-#define  CAN_MSR_ERRI                        0x0004U            /*!<Error Interrupt */
-#define  CAN_MSR_WKUI                        0x0008U            /*!<Wakeup Interrupt */
-#define  CAN_MSR_SLAKI                       0x0010U            /*!<Sleep Acknowledge Interrupt */
-#define  CAN_MSR_TXM                         0x0100U            /*!<Transmit Mode */
-#define  CAN_MSR_RXM                         0x0200U            /*!<Receive Mode */
-#define  CAN_MSR_SAMP                        0x0400U            /*!<Last Sample Point */
-#define  CAN_MSR_RX                          0x0800U            /*!<CAN Rx Signal */
-
-/*******************  Bit definition for CAN_TSR register  ********************/
-#define  CAN_TSR_RQCP0                       0x00000001U        /*!<Request Completed Mailbox0 */
-#define  CAN_TSR_TXOK0                       0x00000002U        /*!<Transmission OK of Mailbox0 */
-#define  CAN_TSR_ALST0                       0x00000004U        /*!<Arbitration Lost for Mailbox0 */
-#define  CAN_TSR_TERR0                       0x00000008U        /*!<Transmission Error of Mailbox0 */
-#define  CAN_TSR_ABRQ0                       0x00000080U        /*!<Abort Request for Mailbox0 */
-#define  CAN_TSR_RQCP1                       0x00000100U        /*!<Request Completed Mailbox1 */
-#define  CAN_TSR_TXOK1                       0x00000200U        /*!<Transmission OK of Mailbox1 */
-#define  CAN_TSR_ALST1                       0x00000400U        /*!<Arbitration Lost for Mailbox1 */
-#define  CAN_TSR_TERR1                       0x00000800U        /*!<Transmission Error of Mailbox1 */
-#define  CAN_TSR_ABRQ1                       0x00008000U        /*!<Abort Request for Mailbox 1 */
-#define  CAN_TSR_RQCP2                       0x00010000U        /*!<Request Completed Mailbox2 */
-#define  CAN_TSR_TXOK2                       0x00020000U        /*!<Transmission OK of Mailbox 2 */
-#define  CAN_TSR_ALST2                       0x00040000U        /*!<Arbitration Lost for mailbox 2 */
-#define  CAN_TSR_TERR2                       0x00080000U        /*!<Transmission Error of Mailbox 2 */
-#define  CAN_TSR_ABRQ2                       0x00800000U        /*!<Abort Request for Mailbox 2 */
-#define  CAN_TSR_CODE                        0x03000000U        /*!<Mailbox Code */
-
-#define  CAN_TSR_TME                         0x1C000000U        /*!<TME[2:0] bits */
-#define  CAN_TSR_TME0                        0x04000000U        /*!<Transmit Mailbox 0 Empty */
-#define  CAN_TSR_TME1                        0x08000000U        /*!<Transmit Mailbox 1 Empty */
-#define  CAN_TSR_TME2                        0x10000000U        /*!<Transmit Mailbox 2 Empty */
-
-#define  CAN_TSR_LOW                         0xE0000000U        /*!<LOW[2:0] bits */
-#define  CAN_TSR_LOW0                        0x20000000U        /*!<Lowest Priority Flag for Mailbox 0 */
-#define  CAN_TSR_LOW1                        0x40000000U        /*!<Lowest Priority Flag for Mailbox 1 */
-#define  CAN_TSR_LOW2                        0x80000000U        /*!<Lowest Priority Flag for Mailbox 2 */
-
-/*******************  Bit definition for CAN_RF0R register  *******************/
-#define  CAN_RF0R_FMP0                       0x03U               /*!<FIFO 0 Message Pending */
-#define  CAN_RF0R_FULL0                      0x08U               /*!<FIFO 0 Full */
-#define  CAN_RF0R_FOVR0                      0x10U               /*!<FIFO 0 Overrun */
-#define  CAN_RF0R_RFOM0                      0x20U               /*!<Release FIFO 0 Output Mailbox */
-
-/*******************  Bit definition for CAN_RF1R register  *******************/
-#define  CAN_RF1R_FMP1                       0x03U               /*!<FIFO 1 Message Pending */
-#define  CAN_RF1R_FULL1                      0x08U               /*!<FIFO 1 Full */
-#define  CAN_RF1R_FOVR1                      0x10U               /*!<FIFO 1 Overrun */
-#define  CAN_RF1R_RFOM1                      0x20U               /*!<Release FIFO 1 Output Mailbox */
-
-/********************  Bit definition for CAN_IER register  *******************/
-#define  CAN_IER_TMEIE                       0x00000001U        /*!<Transmit Mailbox Empty Interrupt Enable */
-#define  CAN_IER_FMPIE0                      0x00000002U        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE0                       0x00000004U        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE0                      0x00000008U        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_FMPIE1                      0x00000010U        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE1                       0x00000020U        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE1                      0x00000040U        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error Warning Interrupt Enable */
-#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error Passive Interrupt Enable */
-#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-Off Interrupt Enable */
-#define  CAN_IER_LECIE                       0x00000800U        /*!<Last Error Code Interrupt Enable */
-#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error Interrupt Enable */
-#define  CAN_IER_WKUIE                       0x00010000U        /*!<Wakeup Interrupt Enable */
-#define  CAN_IER_SLKIE                       0x00020000U        /*!<Sleep Interrupt Enable */
-#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error warning interrupt enable */
-#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error passive interrupt enable */
-#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-off interrupt enable */
-#define  CAN_IER_LECIE                       0x00000800U        /*!<Last error code interrupt enable */
-#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error interrupt enable */
-
-
-/********************  Bit definition for CAN_ESR register  *******************/
-#define  CAN_ESR_EWGF                        0x00000001U        /*!<Error Warning Flag */
-#define  CAN_ESR_EPVF                        0x00000002U        /*!<Error Passive Flag */
-#define  CAN_ESR_BOFF                        0x00000004U        /*!<Bus-Off Flag */
-
-#define  CAN_ESR_LEC                         0x00000070U        /*!<LEC[2:0] bits (Last Error Code) */
-#define  CAN_ESR_LEC_0                       0x00000010U        /*!<Bit 0 */
-#define  CAN_ESR_LEC_1                       0x00000020U        /*!<Bit 1 */
-#define  CAN_ESR_LEC_2                       0x00000040U        /*!<Bit 2 */
-
-#define  CAN_ESR_TEC                         0x00FF0000U        /*!<Least significant byte of the 9-bit Transmit Error Counter */
-#define  CAN_ESR_REC                         0xFF000000U        /*!<Receive Error Counter */
-
-/*******************  Bit definition for CAN_BTR register  ********************/
-#define  CAN_BTR_BRP                         0x000003FFU        /*!<Baud Rate Prescaler */
-#define  CAN_BTR_TS1                         0x000F0000U        /*!<Time Segment 1 */
-#define  CAN_BTR_TS1_0                       0x00010000U        /*!<Bit 0 */
-#define  CAN_BTR_TS1_1                       0x00020000U        /*!<Bit 1 */
-#define  CAN_BTR_TS1_2                       0x00040000U        /*!<Bit 2 */
-#define  CAN_BTR_TS1_3                       0x00080000U        /*!<Bit 3 */
-#define  CAN_BTR_TS2                         0x00700000U        /*!<Time Segment 2 */
-#define  CAN_BTR_TS2_0                       0x00100000U        /*!<Bit 0 */
-#define  CAN_BTR_TS2_1                       0x00200000U        /*!<Bit 1 */
-#define  CAN_BTR_TS2_2                       0x00400000U        /*!<Bit 2 */
-#define  CAN_BTR_SJW                         0x03000000U        /*!<Resynchronization Jump Width */
-#define  CAN_BTR_SJW_0                       0x01000000U        /*!<Bit 0 */
-#define  CAN_BTR_SJW_1                       0x02000000U        /*!<Bit 1 */
-#define  CAN_BTR_LBKM                        0x40000000U        /*!<Loop Back Mode (Debug) */
-#define  CAN_BTR_SILM                        0x80000000U        /*!<Silent Mode */
-
-
-/*!<Mailbox registers */
-/******************  Bit definition for CAN_TI0R register  ********************/
-#define  CAN_TI0R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI0R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_TI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/******************  Bit definition for CAN_TDT0R register  *******************/
-#define  CAN_TDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT0R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/******************  Bit definition for CAN_TDL0R register  *******************/
-#define  CAN_TDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/******************  Bit definition for CAN_TDH0R register  *******************/
-#define  CAN_TDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI1R register  *******************/
-#define  CAN_TI1R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI1R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI1R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_TI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT1R register  ******************/
-#define  CAN_TDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT1R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL1R register  ******************/
-#define  CAN_TDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH1R register  ******************/
-#define  CAN_TDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI2R register  *******************/
-#define  CAN_TI2R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI2R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI2R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI2R_EXID                       0x001FFFF8U        /*!<Extended identifier */
-#define  CAN_TI2R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT2R register  ******************/  
-#define  CAN_TDT2R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT2R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT2R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL2R register  ******************/
-#define  CAN_TDL2R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL2R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL2R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL2R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH2R register  ******************/
-#define  CAN_TDH2R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH2R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH2R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH2R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI0R register  *******************/
-#define  CAN_RI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_RI0R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_RI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_RI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT0R register  ******************/
-#define  CAN_RDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_RDT0R_FMI                       0x0000FF00U        /*!<Filter Match Index */
-#define  CAN_RDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL0R register  ******************/
-#define  CAN_RDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_RDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_RDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_RDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH0R register  ******************/
-#define  CAN_RDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_RDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_RDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_RDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI1R register  *******************/
-#define  CAN_RI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_RI1R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_RI1R_EXID                       0x001FFFF8U        /*!<Extended identifier */
-#define  CAN_RI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT1R register  ******************/
-#define  CAN_RDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_RDT1R_FMI                       0x0000FF00U        /*!<Filter Match Index */
-#define  CAN_RDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL1R register  ******************/
-#define  CAN_RDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_RDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_RDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_RDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH1R register  ******************/
-#define  CAN_RDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_RDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_RDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_RDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*!<CAN filter registers */
-/*******************  Bit definition for CAN_FMR register  ********************/
-#define  CAN_FMR_FINIT                       0x01U               /*!<Filter Init Mode */
-#define  CAN_FMR_CAN2SB                      0x00003F00U        /*!<CAN2 start bank */
-
-/*******************  Bit definition for CAN_FM1R register  *******************/
-#define  CAN_FM1R_FBM                        0x0FFFFFFFU        /*!<Filter Mode */
-#define  CAN_FM1R_FBM0                       0x00000001U        /*!<Filter Init Mode bit 0 */
-#define  CAN_FM1R_FBM1                       0x00000002U        /*!<Filter Init Mode bit 1 */
-#define  CAN_FM1R_FBM2                       0x00000004U        /*!<Filter Init Mode bit 2 */
-#define  CAN_FM1R_FBM3                       0x00000008U        /*!<Filter Init Mode bit 3 */
-#define  CAN_FM1R_FBM4                       0x00000010U        /*!<Filter Init Mode bit 4 */
-#define  CAN_FM1R_FBM5                       0x00000020U        /*!<Filter Init Mode bit 5 */
-#define  CAN_FM1R_FBM6                       0x00000040U        /*!<Filter Init Mode bit 6 */
-#define  CAN_FM1R_FBM7                       0x00000080U        /*!<Filter Init Mode bit 7 */
-#define  CAN_FM1R_FBM8                       0x00000100U        /*!<Filter Init Mode bit 8 */
-#define  CAN_FM1R_FBM9                       0x00000200U        /*!<Filter Init Mode bit 9 */
-#define  CAN_FM1R_FBM10                      0x00000400U        /*!<Filter Init Mode bit 10 */
-#define  CAN_FM1R_FBM11                      0x00000800U        /*!<Filter Init Mode bit 11 */
-#define  CAN_FM1R_FBM12                      0x00001000U        /*!<Filter Init Mode bit 12 */
-#define  CAN_FM1R_FBM13                      0x00002000U        /*!<Filter Init Mode bit 13 */
-#define  CAN_FM1R_FBM14                      0x00004000U        /*!<Filter Init Mode bit 14 */
-#define  CAN_FM1R_FBM15                      0x00008000U        /*!<Filter Init Mode bit 15 */
-#define  CAN_FM1R_FBM16                      0x00010000U        /*!<Filter Init Mode bit 16 */
-#define  CAN_FM1R_FBM17                      0x00020000U        /*!<Filter Init Mode bit 17 */
-#define  CAN_FM1R_FBM18                      0x00040000U        /*!<Filter Init Mode bit 18 */
-#define  CAN_FM1R_FBM19                      0x00080000U        /*!<Filter Init Mode bit 19 */
-#define  CAN_FM1R_FBM20                      0x00100000U        /*!<Filter Init Mode bit 20 */
-#define  CAN_FM1R_FBM21                      0x00200000U        /*!<Filter Init Mode bit 21 */
-#define  CAN_FM1R_FBM22                      0x00400000U        /*!<Filter Init Mode bit 22 */
-#define  CAN_FM1R_FBM23                      0x00800000U        /*!<Filter Init Mode bit 23 */
-#define  CAN_FM1R_FBM24                      0x01000000U        /*!<Filter Init Mode bit 24 */
-#define  CAN_FM1R_FBM25                      0x02000000U        /*!<Filter Init Mode bit 25 */
-#define  CAN_FM1R_FBM26                      0x04000000U        /*!<Filter Init Mode bit 26 */
-#define  CAN_FM1R_FBM27                      0x08000000U        /*!<Filter Init Mode bit 27 */
-
-/*******************  Bit definition for CAN_FS1R register  *******************/
-#define  CAN_FS1R_FSC                        0x0FFFFFFFU        /*!<Filter Scale Configuration */
-#define  CAN_FS1R_FSC0                       0x00000001U        /*!<Filter Scale Configuration bit 0 */
-#define  CAN_FS1R_FSC1                       0x00000002U        /*!<Filter Scale Configuration bit 1 */
-#define  CAN_FS1R_FSC2                       0x00000004U        /*!<Filter Scale Configuration bit 2 */
-#define  CAN_FS1R_FSC3                       0x00000008U        /*!<Filter Scale Configuration bit 3 */
-#define  CAN_FS1R_FSC4                       0x00000010U        /*!<Filter Scale Configuration bit 4 */
-#define  CAN_FS1R_FSC5                       0x00000020U        /*!<Filter Scale Configuration bit 5 */
-#define  CAN_FS1R_FSC6                       0x00000040U        /*!<Filter Scale Configuration bit 6 */
-#define  CAN_FS1R_FSC7                       0x00000080U        /*!<Filter Scale Configuration bit 7 */
-#define  CAN_FS1R_FSC8                       0x00000100U        /*!<Filter Scale Configuration bit 8 */
-#define  CAN_FS1R_FSC9                       0x00000200U        /*!<Filter Scale Configuration bit 9 */
-#define  CAN_FS1R_FSC10                      0x00000400U        /*!<Filter Scale Configuration bit 10 */
-#define  CAN_FS1R_FSC11                      0x00000800U        /*!<Filter Scale Configuration bit 11 */
-#define  CAN_FS1R_FSC12                      0x00001000U        /*!<Filter Scale Configuration bit 12 */
-#define  CAN_FS1R_FSC13                      0x00002000U        /*!<Filter Scale Configuration bit 13 */
-#define  CAN_FS1R_FSC14                      0x00004000U        /*!<Filter Scale Configuration bit 14 */
-#define  CAN_FS1R_FSC15                      0x00008000U        /*!<Filter Scale Configuration bit 15 */
-#define  CAN_FS1R_FSC16                      0x00010000U        /*!<Filter Scale Configuration bit 16 */
-#define  CAN_FS1R_FSC17                      0x00020000U        /*!<Filter Scale Configuration bit 17 */
-#define  CAN_FS1R_FSC18                      0x00040000U        /*!<Filter Scale Configuration bit 18 */
-#define  CAN_FS1R_FSC19                      0x00080000U        /*!<Filter Scale Configuration bit 19 */
-#define  CAN_FS1R_FSC20                      0x00100000U        /*!<Filter Scale Configuration bit 20 */
-#define  CAN_FS1R_FSC21                      0x00200000U        /*!<Filter Scale Configuration bit 21 */
-#define  CAN_FS1R_FSC22                      0x00400000U        /*!<Filter Scale Configuration bit 22 */
-#define  CAN_FS1R_FSC23                      0x00800000U        /*!<Filter Scale Configuration bit 23 */
-#define  CAN_FS1R_FSC24                      0x01000000U        /*!<Filter Scale Configuration bit 24 */
-#define  CAN_FS1R_FSC25                      0x02000000U        /*!<Filter Scale Configuration bit 25 */
-#define  CAN_FS1R_FSC26                      0x04000000U        /*!<Filter Scale Configuration bit 26 */
-#define  CAN_FS1R_FSC27                      0x08000000U        /*!<Filter Scale Configuration bit 27 */
-
-/******************  Bit definition for CAN_FFA1R register  *******************/
-#define  CAN_FFA1R_FFA                        0x0FFFFFFFU        /*!<Filter FIFO Assignment */
-#define  CAN_FFA1R_FFA0                       0x00000001U        /*!<Filter FIFO Assignment bit 0 */
-#define  CAN_FFA1R_FFA1                       0x00000002U        /*!<Filter FIFO Assignment bit 1 */
-#define  CAN_FFA1R_FFA2                       0x00000004U        /*!<Filter FIFO Assignment bit 2 */
-#define  CAN_FFA1R_FFA3                       0x00000008U        /*!<Filter FIFO Assignment bit 3 */
-#define  CAN_FFA1R_FFA4                       0x00000010U        /*!<Filter FIFO Assignment bit 4 */
-#define  CAN_FFA1R_FFA5                       0x00000020U        /*!<Filter FIFO Assignment bit 5 */
-#define  CAN_FFA1R_FFA6                       0x00000040U        /*!<Filter FIFO Assignment bit 6 */
-#define  CAN_FFA1R_FFA7                       0x00000080U        /*!<Filter FIFO Assignment bit 7 */
-#define  CAN_FFA1R_FFA8                       0x00000100U        /*!<Filter FIFO Assignment bit 8 */
-#define  CAN_FFA1R_FFA9                       0x00000200U        /*!<Filter FIFO Assignment bit 9 */
-#define  CAN_FFA1R_FFA10                      0x00000400U        /*!<Filter FIFO Assignment bit 10 */
-#define  CAN_FFA1R_FFA11                      0x00000800U        /*!<Filter FIFO Assignment bit 11 */
-#define  CAN_FFA1R_FFA12                      0x00001000U        /*!<Filter FIFO Assignment bit 12 */
-#define  CAN_FFA1R_FFA13                      0x00002000U        /*!<Filter FIFO Assignment bit 13 */
-#define  CAN_FFA1R_FFA14                      0x00004000U        /*!<Filter FIFO Assignment bit 14 */
-#define  CAN_FFA1R_FFA15                      0x00008000U        /*!<Filter FIFO Assignment bit 15 */
-#define  CAN_FFA1R_FFA16                      0x00010000U        /*!<Filter FIFO Assignment bit 16 */
-#define  CAN_FFA1R_FFA17                      0x00020000U        /*!<Filter FIFO Assignment bit 17 */
-#define  CAN_FFA1R_FFA18                      0x00040000U        /*!<Filter FIFO Assignment bit 18 */
-#define  CAN_FFA1R_FFA19                      0x00080000U        /*!<Filter FIFO Assignment bit 19 */
-#define  CAN_FFA1R_FFA20                      0x00100000U        /*!<Filter FIFO Assignment bit 20 */
-#define  CAN_FFA1R_FFA21                      0x00200000U        /*!<Filter FIFO Assignment bit 21 */
-#define  CAN_FFA1R_FFA22                      0x00400000U        /*!<Filter FIFO Assignment bit 22 */
-#define  CAN_FFA1R_FFA23                      0x00800000U        /*!<Filter FIFO Assignment bit 23 */
-#define  CAN_FFA1R_FFA24                      0x01000000U        /*!<Filter FIFO Assignment bit 24 */
-#define  CAN_FFA1R_FFA25                      0x02000000U        /*!<Filter FIFO Assignment bit 25 */
-#define  CAN_FFA1R_FFA26                      0x04000000U        /*!<Filter FIFO Assignment bit 26 */
-#define  CAN_FFA1R_FFA27                      0x08000000U        /*!<Filter FIFO Assignment bit 27 */
-
-/*******************  Bit definition for CAN_FA1R register  *******************/
-#define  CAN_FA1R_FACT                        0x0FFFFFFFU        /*!<Filter Active */
-#define  CAN_FA1R_FACT0                       0x00000001U        /*!<Filter Active bit 0 */
-#define  CAN_FA1R_FACT1                       0x00000002U        /*!<Filter Active bit 1 */
-#define  CAN_FA1R_FACT2                       0x00000004U        /*!<Filter Active bit 2 */
-#define  CAN_FA1R_FACT3                       0x00000008U        /*!<Filter Active bit 3 */
-#define  CAN_FA1R_FACT4                       0x00000010U        /*!<Filter Active bit 4 */
-#define  CAN_FA1R_FACT5                       0x00000020U        /*!<Filter Active bit 5 */
-#define  CAN_FA1R_FACT6                       0x00000040U        /*!<Filter Active bit 6 */
-#define  CAN_FA1R_FACT7                       0x00000080U        /*!<Filter Active bit 7 */
-#define  CAN_FA1R_FACT8                       0x00000100U        /*!<Filter Active bit 8 */
-#define  CAN_FA1R_FACT9                       0x00000200U        /*!<Filter Active bit 9 */
-#define  CAN_FA1R_FACT10                      0x00000400U        /*!<Filter Active bit 10 */
-#define  CAN_FA1R_FACT11                      0x00000800U        /*!<Filter Active bit 11 */
-#define  CAN_FA1R_FACT12                      0x00001000U        /*!<Filter Active bit 12 */
-#define  CAN_FA1R_FACT13                      0x00002000U        /*!<Filter Active bit 13 */
-#define  CAN_FA1R_FACT14                      0x00004000U        /*!<Filter Active bit 14 */
-#define  CAN_FA1R_FACT15                      0x00008000U        /*!<Filter Active bit 15 */
-#define  CAN_FA1R_FACT16                      0x00010000U        /*!<Filter Active bit 16 */
-#define  CAN_FA1R_FACT17                      0x00020000U        /*!<Filter Active bit 17 */
-#define  CAN_FA1R_FACT18                      0x00040000U        /*!<Filter Active bit 18 */
-#define  CAN_FA1R_FACT19                      0x00080000U        /*!<Filter Active bit 19 */
-#define  CAN_FA1R_FACT20                      0x00100000U        /*!<Filter Active bit 20 */
-#define  CAN_FA1R_FACT21                      0x00200000U        /*!<Filter Active bit 21 */
-#define  CAN_FA1R_FACT22                      0x00400000U        /*!<Filter Active bit 22 */
-#define  CAN_FA1R_FACT23                      0x00800000U        /*!<Filter Active bit 23 */
-#define  CAN_FA1R_FACT24                      0x01000000U        /*!<Filter Active bit 24 */
-#define  CAN_FA1R_FACT25                      0x02000000U        /*!<Filter Active bit 25 */
-#define  CAN_FA1R_FACT26                      0x04000000U        /*!<Filter Active bit 26 */
-#define  CAN_FA1R_FACT27                      0x08000000U        /*!<Filter Active bit 27 */
-
-/*******************  Bit definition for CAN_F0R1 register  *******************/
-#define  CAN_F0R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F0R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F0R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F0R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F0R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F0R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F0R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F0R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F0R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F0R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F0R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F0R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F0R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F0R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F0R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F0R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F0R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F0R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F0R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F0R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F0R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F0R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F0R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F0R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F0R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F0R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F0R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F0R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F0R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F0R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F0R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F0R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R1 register  *******************/
-#define  CAN_F1R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F1R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F1R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F1R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F1R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F1R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F1R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F1R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F1R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F1R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F1R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F1R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F1R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F1R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F1R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F1R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F1R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F1R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F1R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F1R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F1R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F1R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F1R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F1R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F1R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F1R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F1R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F1R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F1R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F1R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F1R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F1R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R1 register  *******************/
-#define  CAN_F2R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F2R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F2R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F2R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F2R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F2R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F2R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F2R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F2R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F2R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F2R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F2R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F2R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F2R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F2R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F2R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F2R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F2R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F2R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F2R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F2R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F2R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F2R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F2R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F2R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F2R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F2R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F2R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F2R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F2R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F2R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F2R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R1 register  *******************/
-#define  CAN_F3R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F3R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F3R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F3R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F3R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F3R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F3R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F3R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F3R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F3R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F3R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F3R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F3R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F3R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F3R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F3R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F3R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F3R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F3R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F3R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F3R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F3R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F3R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F3R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F3R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F3R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F3R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F3R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F3R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F3R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F3R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F3R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R1 register  *******************/
-#define  CAN_F4R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F4R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F4R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F4R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F4R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F4R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F4R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F4R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F4R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F4R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F4R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F4R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F4R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F4R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F4R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F4R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F4R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F4R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F4R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F4R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F4R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F4R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F4R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F4R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F4R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F4R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F4R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F4R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F4R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F4R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F4R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F4R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R1 register  *******************/
-#define  CAN_F5R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F5R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F5R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F5R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F5R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F5R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F5R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F5R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F5R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F5R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F5R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F5R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F5R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F5R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F5R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F5R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F5R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F5R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F5R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F5R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F5R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F5R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F5R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F5R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F5R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F5R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F5R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F5R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F5R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F5R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F5R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F5R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R1 register  *******************/
-#define  CAN_F6R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F6R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F6R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F6R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F6R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F6R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F6R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F6R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F6R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F6R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F6R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F6R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F6R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F6R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F6R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F6R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F6R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F6R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F6R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F6R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F6R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F6R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F6R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F6R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F6R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F6R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F6R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F6R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F6R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F6R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F6R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F6R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R1 register  *******************/
-#define  CAN_F7R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F7R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F7R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F7R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F7R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F7R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F7R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F7R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F7R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F7R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F7R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F7R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F7R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F7R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F7R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F7R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F7R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F7R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F7R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F7R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F7R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F7R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F7R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F7R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F7R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F7R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F7R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F7R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F7R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F7R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F7R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F7R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R1 register  *******************/
-#define  CAN_F8R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F8R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F8R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F8R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F8R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F8R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F8R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F8R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F8R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F8R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F8R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F8R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F8R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F8R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F8R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F8R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F8R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F8R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F8R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F8R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F8R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F8R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F8R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F8R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F8R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F8R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F8R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F8R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F8R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F8R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F8R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F8R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R1 register  *******************/
-#define  CAN_F9R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F9R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F9R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F9R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F9R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F9R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F9R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F9R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F9R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F9R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F9R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F9R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F9R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F9R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F9R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F9R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F9R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F9R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F9R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F9R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F9R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F9R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F9R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F9R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F9R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F9R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F9R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F9R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F9R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F9R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F9R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F9R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R1 register  ******************/
-#define  CAN_F10R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F10R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F10R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F10R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F10R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F10R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F10R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F10R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F10R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F10R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F10R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F10R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F10R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F10R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F10R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F10R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F10R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F10R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F10R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F10R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F10R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F10R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F10R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F10R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F10R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F10R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F10R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F10R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F10R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F10R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F10R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F10R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R1 register  ******************/
-#define  CAN_F11R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F11R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F11R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F11R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F11R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F11R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F11R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F11R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F11R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F11R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F11R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F11R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F11R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F11R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F11R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F11R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F11R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F11R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F11R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F11R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F11R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F11R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F11R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F11R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F11R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F11R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F11R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F11R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F11R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F11R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F11R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F11R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R1 register  ******************/
-#define  CAN_F12R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F12R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F12R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F12R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F12R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F12R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F12R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F12R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F12R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F12R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F12R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F12R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F12R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F12R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F12R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F12R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F12R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F12R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F12R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F12R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F12R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F12R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F12R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F12R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F12R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F12R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F12R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F12R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F12R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F12R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F12R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F12R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R1 register  ******************/
-#define  CAN_F13R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F13R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F13R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F13R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F13R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F13R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F13R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F13R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F13R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F13R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F13R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F13R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F13R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F13R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F13R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F13R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F13R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F13R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F13R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F13R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F13R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F13R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F13R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F13R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F13R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F13R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F13R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F13R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F13R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F13R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F13R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F13R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F0R2 register  *******************/
-#define  CAN_F0R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F0R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F0R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F0R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F0R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F0R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F0R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F0R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F0R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F0R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F0R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F0R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F0R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F0R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F0R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F0R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F0R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F0R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F0R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F0R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F0R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F0R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F0R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F0R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F0R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F0R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F0R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F0R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F0R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F0R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F0R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F0R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R2 register  *******************/
-#define  CAN_F1R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F1R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F1R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F1R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F1R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F1R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F1R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F1R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F1R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F1R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F1R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F1R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F1R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F1R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F1R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F1R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F1R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F1R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F1R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F1R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F1R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F1R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F1R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F1R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F1R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F1R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F1R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F1R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F1R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F1R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F1R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F1R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R2 register  *******************/
-#define  CAN_F2R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F2R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F2R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F2R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F2R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F2R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F2R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F2R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F2R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F2R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F2R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F2R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F2R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F2R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F2R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F2R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F2R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F2R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F2R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F2R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F2R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F2R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F2R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F2R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F2R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F2R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F2R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F2R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F2R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F2R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F2R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F2R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R2 register  *******************/
-#define  CAN_F3R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F3R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F3R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F3R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F3R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F3R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F3R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F3R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F3R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F3R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F3R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F3R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F3R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F3R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F3R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F3R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F3R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F3R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F3R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F3R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F3R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F3R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F3R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F3R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F3R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F3R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F3R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F3R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F3R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F3R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F3R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F3R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R2 register  *******************/
-#define  CAN_F4R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F4R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F4R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F4R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F4R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F4R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F4R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F4R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F4R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F4R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F4R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F4R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F4R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F4R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F4R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F4R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F4R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F4R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F4R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F4R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F4R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F4R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F4R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F4R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F4R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F4R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F4R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F4R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F4R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F4R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F4R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F4R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R2 register  *******************/
-#define  CAN_F5R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F5R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F5R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F5R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F5R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F5R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F5R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F5R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F5R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F5R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F5R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F5R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F5R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F5R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F5R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F5R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F5R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F5R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F5R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F5R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F5R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F5R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F5R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F5R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F5R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F5R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F5R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F5R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F5R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F5R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F5R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F5R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R2 register  *******************/
-#define  CAN_F6R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F6R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F6R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F6R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F6R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F6R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F6R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F6R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F6R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F6R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F6R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F6R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F6R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F6R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F6R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F6R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F6R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F6R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F6R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F6R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F6R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F6R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F6R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F6R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F6R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F6R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F6R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F6R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F6R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F6R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F6R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F6R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R2 register  *******************/
-#define  CAN_F7R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F7R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F7R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F7R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F7R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F7R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F7R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F7R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F7R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F7R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F7R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F7R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F7R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F7R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F7R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F7R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F7R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F7R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F7R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F7R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F7R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F7R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F7R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F7R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F7R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F7R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F7R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F7R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F7R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F7R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F7R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F7R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R2 register  *******************/
-#define  CAN_F8R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F8R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F8R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F8R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F8R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F8R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F8R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F8R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F8R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F8R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F8R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F8R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F8R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F8R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F8R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F8R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F8R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F8R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F8R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F8R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F8R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F8R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F8R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F8R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F8R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F8R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F8R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F8R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F8R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F8R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F8R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F8R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R2 register  *******************/
-#define  CAN_F9R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F9R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F9R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F9R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F9R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F9R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F9R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F9R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F9R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F9R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F9R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F9R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F9R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F9R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F9R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F9R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F9R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F9R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F9R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F9R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F9R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F9R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F9R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F9R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F9R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F9R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F9R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F9R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F9R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F9R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F9R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F9R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R2 register  ******************/
-#define  CAN_F10R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F10R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F10R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F10R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F10R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F10R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F10R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F10R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F10R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F10R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F10R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F10R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F10R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F10R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F10R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F10R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F10R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F10R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F10R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F10R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F10R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F10R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F10R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F10R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F10R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F10R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F10R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F10R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F10R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F10R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F10R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F10R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R2 register  ******************/
-#define  CAN_F11R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F11R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F11R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F11R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F11R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F11R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F11R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F11R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F11R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F11R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F11R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F11R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F11R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F11R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F11R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F11R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F11R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F11R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F11R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F11R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F11R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F11R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F11R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F11R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F11R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F11R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F11R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F11R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F11R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F11R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F11R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F11R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R2 register  ******************/
-#define  CAN_F12R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F12R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F12R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F12R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F12R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F12R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F12R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F12R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F12R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F12R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F12R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F12R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F12R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F12R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F12R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F12R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F12R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F12R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F12R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F12R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F12R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F12R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F12R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F12R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F12R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F12R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F12R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F12R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F12R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F12R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F12R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F12R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R2 register  ******************/
-#define  CAN_F13R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F13R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F13R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F13R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F13R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F13R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F13R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F13R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F13R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F13R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F13R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F13R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F13R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F13R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F13R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F13R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F13R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F13R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F13R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F13R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F13R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F13R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F13R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F13R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F13R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F13R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F13R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F13R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F13R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F13R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F13R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F13R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRC calculation unit                              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           0xFFFFFFFFU /*!< Data register bits */
-
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         0xFFU        /*!< General-purpose 8-bit data register bits */
-
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        0x01U        /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 Debug MCU                                  */
-/*                                                                            */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                 Digital Filter for Sigma Delta Modulators                  */
-/*                                                                            */
-/******************************************************************************/
-
-/****************   DFSDM channel configuration registers  ********************/
-
-/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/
-#define  DFSDM_CHCFGR1_DFSDMEN                0x80000000U            /*!< Global enable for DFSDM interface */
-#define  DFSDM_CHCFGR1_CKOUTSRC               0x40000000U            /*!< Output serial clock source selection */
-#define  DFSDM_CHCFGR1_CKOUTDIV               0x00FF0000U            /*!< CKOUTDIV[7:0] output serial clock divider */
-#define  DFSDM_CHCFGR1_DATPACK                0x0000C000U            /*!< DATPACK[1:0] Data packing mode */
-#define  DFSDM_CHCFGR1_DATPACK_1              0x00008000U            /*!< Data packing mode, Bit 1 */
-#define  DFSDM_CHCFGR1_DATPACK_0              0x00004000U            /*!< Data packing mode, Bit 0 */
-#define  DFSDM_CHCFGR1_DATMPX                 0x00003000U            /*!< DATMPX[1:0] Input data multiplexer for channel y */
-#define  DFSDM_CHCFGR1_DATMPX_1               0x00002000U            /*!< Input data multiplexer for channel y, Bit 1 */
-#define  DFSDM_CHCFGR1_DATMPX_0               0x00001000U            /*!< Input data multiplexer for channel y, Bit 0 */
-#define  DFSDM_CHCFGR1_CHINSEL                0x00000100U            /*!< Serial inputs selection for channel y */
-#define  DFSDM_CHCFGR1_CHEN                   0x00000080U            /*!< Channel y enable */
-#define  DFSDM_CHCFGR1_CKABEN                 0x00000040U            /*!< Clock absence detector enable on channel y */
-#define  DFSDM_CHCFGR1_SCDEN                  0x00000020U            /*!< Short circuit detector enable on channel y */
-#define  DFSDM_CHCFGR1_SPICKSEL               0x0000000CU            /*!< SPICKSEL[1:0] SPI clock select for channel y */
-#define  DFSDM_CHCFGR1_SPICKSEL_1             0x00000008U            /*!< SPI clock select for channel y, Bit 1 */
-#define  DFSDM_CHCFGR1_SPICKSEL_0             0x00000004U            /*!< SPI clock select for channel y, Bit 0 */
-#define  DFSDM_CHCFGR1_SITP                   0x00000003U            /*!< SITP[1:0] Serial interface type for channel y */
-#define  DFSDM_CHCFGR1_SITP_1                 0x00000002U            /*!< Serial interface type for channel y, Bit 1 */
-#define  DFSDM_CHCFGR1_SITP_0                 0x00000001U            /*!< Serial interface type for channel y, Bit 0 */
-
-/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/
-#define  DFSDM_CHCFGR2_OFFSET                 0xFFFFFF00U            /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
-#define  DFSDM_CHCFGR2_DTRBS                  0x000000F8U            /*!< DTRBS[4:0] Data right bit-shift for channel y */
-
-/****************  Bit definition for DFSDM_CHAWSCDR register *****************/
-#define  DFSDM_CHAWSCDR_AWFORD                0x00C00000U            /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
-#define  DFSDM_CHAWSCDR_AWFORD_1              0x00800000U            /*!< Analog watchdog Sinc filter order on channel y, Bit 1 */
-#define  DFSDM_CHAWSCDR_AWFORD_0              0x00400000U            /*!< Analog watchdog Sinc filter order on channel y, Bit 0 */
-#define  DFSDM_CHAWSCDR_AWFOSR                0x001F0000U            /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
-#define  DFSDM_CHAWSCDR_BKSCD                 0x0000F000U            /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
-#define  DFSDM_CHAWSCDR_SCDT                  0x000000FFU            /*!< SCDT[7:0] Short circuit detector threshold for channel y */
-
-/****************  Bit definition for DFSDM_CHWDATR register *******************/
-#define  DFSDM_CHWDATR_WDATA                  0x0000FFFFU            /*!< WDATA[15:0] Input channel y watchdog data */
-
-/****************  Bit definition for DFSDM_CHDATINR register *****************/
-#define  DFSDM_CHDATINR_INDAT0                0x0000FFFFU            /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
-#define  DFSDM_CHDATINR_INDAT1                0xFFFF0000U            /*!< INDAT0[15:0] Input data for channel y */
-
-/************************   DFSDM module registers  ****************************/
-
-/*****************  Bit definition for DFSDM_FLTCR1 register *******************/
-#define  DFSDM_FLTCR1_AWFSEL                  0x40000000U            /*!< Analog watchdog fast mode select */
-#define  DFSDM_FLTCR1_FAST                    0x20000000U            /*!< Fast conversion mode selection */
-#define  DFSDM_FLTCR1_RCH                     0x07000000U            /*!< RCH[2:0] Regular channel selection */
-#define  DFSDM_FLTCR1_RDMAEN                  0x00200000U            /*!< DMA channel enabled to read data for the regular conversion */
-#define  DFSDM_FLTCR1_RSYNC                   0x00080000U            /*!< Launch regular conversion synchronously with DFSDMx */
-#define  DFSDM_FLTCR1_RCONT                   0x00040000U            /*!< Continuous mode selection for regular conversions */
-#define  DFSDM_FLTCR1_RSWSTART                0x00020000U            /*!< Software start of a conversion on the regular channel */
-#define  DFSDM_FLTCR1_JEXTEN                  0x00006000U            /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
-#define  DFSDM_FLTCR1_JEXTEN_1                0x00004000U            /*!< Trigger enable and trigger edge selection for injected conversions, Bit 1 */
-#define  DFSDM_FLTCR1_JEXTEN_0                0x00002000U            /*!< Trigger enable and trigger edge selection for injected conversions, Bit 0 */
-#define  DFSDM_FLTCR1_JEXTSEL                 0x00000700U            /*!< JEXTSEL[2:0]Trigger signal selection for launching injected conversions */
-#define  DFSDM_FLTCR1_JEXTSEL_2               0x00000400U            /*!< Trigger signal selection for launching injected conversions, Bit 2 */
-#define  DFSDM_FLTCR1_JEXTSEL_1               0x00000200U            /*!< Trigger signal selection for launching injected conversions, Bit 1 */
-#define  DFSDM_FLTCR1_JEXTSEL_0               0x00000100U            /*!< Trigger signal selection for launching injected conversions, Bit 0 */
-#define  DFSDM_FLTCR1_JDMAEN                  0x00000020U            /*!< DMA channel enabled to read data for the injected channel group */
-#define  DFSDM_FLTCR1_JSCAN                   0x00000010U            /*!< Scanning conversion in continuous mode selection for injected conversions */
-#define  DFSDM_FLTCR1_JSYNC                   0x00000008U            /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */
-#define  DFSDM_FLTCR1_JSWSTART                0x00000002U            /*!< Start the conversion of the injected group of channels */
-#define  DFSDM_FLTCR1_DFEN                    0x00000001U            /*!< DFSDM enable */
-
-/*****************  Bit definition for DFSDM_FLTCR2 register *******************/
-#define  DFSDM_FLTCR2_AWDCH                   0x000F0000U            /*!< AWDCH[7:0] Analog watchdog channel selection */
-#define  DFSDM_FLTCR2_EXCH                    0x00000F00U            /*!< EXCH[7:0] Extreme detector channel selection */
-#define  DFSDM_FLTCR2_CKABIE                  0x00000040U            /*!< Clock absence interrupt enable */
-#define  DFSDM_FLTCR2_SCDIE                   0x00000020U            /*!< Short circuit detector interrupt enable */
-#define  DFSDM_FLTCR2_AWDIE                   0x00000010U            /*!< Analog watchdog interrupt enable */
-#define  DFSDM_FLTCR2_ROVRIE                  0x00000008U            /*!< Regular data overrun interrupt enable */
-#define  DFSDM_FLTCR2_JOVRIE                  0x00000004U            /*!< Injected data overrun interrupt enable */
-#define  DFSDM_FLTCR2_REOCIE                  0x00000002U            /*!< Regular end of conversion interrupt enable */
-#define  DFSDM_FLTCR2_JEOCIE                  0x00000001U            /*!< Injected end of conversion interrupt enable */
-
-/*****************  Bit definition for DFSDM_FLTISR register *******************/
-#define  DFSDM_FLTISR_SCDF                    0x0F000000U            /*!< SCDF[7:0] Short circuit detector flag */
-#define  DFSDM_FLTISR_CKABF                   0x000F0000U            /*!< CKABF[7:0] Clock absence flag */
-#define  DFSDM_FLTISR_RCIP                    0x00004000U            /*!< Regular conversion in progress status */
-#define  DFSDM_FLTISR_JCIP                    0x00002000U            /*!< Injected conversion in progress status */
-#define  DFSDM_FLTISR_AWDF                    0x00000010U            /*!< Analog watchdog */
-#define  DFSDM_FLTISR_ROVRF                   0x00000008U            /*!< Regular conversion overrun flag */
-#define  DFSDM_FLTISR_JOVRF                   0x00000004U            /*!< Injected conversion overrun flag */
-#define  DFSDM_FLTISR_REOCF                   0x00000002U            /*!< End of regular conversion flag */
-#define  DFSDM_FLTISR_JEOCF                   0x00000001U            /*!< End of injected conversion flag */
-
-/*****************  Bit definition for DFSDM_FLTICR register *******************/
-#define  DFSDM_FLTICR_CLRSCSDF                0x0F000000U            /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
-#define  DFSDM_FLTICR_CLRCKABF                0x000F0000U            /*!< CLRCKABF[7:0] Clear the clock absence flag */
-#define  DFSDM_FLTICR_CLRROVRF                0x00000008U            /*!< Clear the regular conversion overrun flag */
-#define  DFSDM_FLTICR_CLRJOVRF                0x00000004U            /*!< Clear the injected conversion overrun flag */
-
-/****************  Bit definition for DFSDM_FLTJCHGR register ******************/
-#define  DFSDM_FLTJCHGR_JCHG                  0x0000000FU            /*!< JCHG[7:0] Injected channel group selection */
-
-/*****************  Bit definition for DFSDM_FLTFCR register *******************/
-#define  DFSDM_FLTFCR_FORD                    0xE0000000U            /*!< FORD[2:0] Sinc filter order */
-#define  DFSDM_FLTFCR_FORD_2                  0x80000000U            /*!< Sinc filter order, Bit 2 */
-#define  DFSDM_FLTFCR_FORD_1                  0x40000000U            /*!< Sinc filter order, Bit 1 */
-#define  DFSDM_FLTFCR_FORD_0                  0x20000000U            /*!< Sinc filter order, Bit 0 */
-#define  DFSDM_FLTFCR_FOSR                    0x03FF0000U            /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
-#define  DFSDM_FLTFCR_IOSR                    0x000000FFU            /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
-
-/***************  Bit definition for DFSDM_FLTJDATAR register *****************/
-#define  DFSDM_FLTJDATAR_JDATA                0xFFFFFF00U            /*!< JDATA[23:0] Injected group conversion data */
-#define  DFSDM_FLTJDATAR_JDATACH              0x00000007U            /*!< JDATACH[2:0] Injected channel most recently converted */
-
-/***************  Bit definition for DFSDM_FLTRDATAR register *****************/
-#define  DFSDM_FLTRDATAR_RDATA                0xFFFFFF00U            /*!< RDATA[23:0] Regular channel conversion data */
-#define  DFSDM_FLTRDATAR_RPEND                0x00000010U            /*!< RPEND Regular channel pending data */
-#define  DFSDM_FLTRDATAR_RDATACH              0x00000007U            /*!< RDATACH[2:0] Regular channel most recently converted */
-
-/***************  Bit definition for DFSDM_FLTAWHTR register ******************/
-#define  DFSDM_FLTAWHTR_AWHT                 0xFFFFFF00U             /*!< AWHT[23:0] Analog watchdog high threshold */
-#define  DFSDM_FLTAWHTR_BKAWH                0x0000000FU             /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
-
-/***************  Bit definition for DFSDM_FLTAWLTR register ******************/
-#define  DFSDM_FLTAWLTR_AWLT                 0xFFFFFF00U             /*!< AWLT[23:0] Analog watchdog low threshold */
-#define  DFSDM_FLTAWLTR_BKAWL                0x0000000FU             /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
-
-/***************  Bit definition for DFSDM_FLTAWSR register *******************/
-#define  DFSDM_FLTAWSR_AWHTF                 0x00000F00U             /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
-#define  DFSDM_FLTAWSR_AWLTF                 0x0000000FU             /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
-
-/***************  Bit definition for DFSDM_FLTAWCFR register ******************/
-#define  DFSDM_FLTAWCFR_CLRAWHTF             0x00000F00U             /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
-#define  DFSDM_FLTAWCFR_CLRAWLTF             0x0000000FU             /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
-
-/***************  Bit definition for DFSDM_FLTEXMAX register ******************/
-#define  DFSDM_FLTEXMAX_EXMAX                0xFFFFFF00U             /*!< EXMAX[23:0] Extreme detector maximum value */
-#define  DFSDM_FLTEXMAX_EXMAXCH              0x00000007U             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
-
-/***************  Bit definition for DFSDM_FLTEXMIN register ******************/
-#define  DFSDM_FLTEXMIN_EXMIN                0xFFFFFF00U             /*!< EXMIN[23:0] Extreme detector minimum value */
-#define  DFSDM_FLTEXMIN_EXMINCH              0x00000007U             /*!< EXMINCH[2:0] Extreme detector minimum data channel */
-
-/***************  Bit definition for DFSDM_FLTCNVTIMR register ****************/
-#define  DFSDM_FLTCNVTIMR_CNVCNT             0xFFFFFFF0U             /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
-
-/******************************************************************************/
-/*                                                                            */
-/*                             DMA Controller                                 */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DMA_SxCR register  *****************/
-#define DMA_SxCR_CHSEL                       0x0E000000U
-#define DMA_SxCR_CHSEL_0                     0x02000000U
-#define DMA_SxCR_CHSEL_1                     0x04000000U
-#define DMA_SxCR_CHSEL_2                     0x08000000U
-#define DMA_SxCR_MBURST                      0x01800000U
-#define DMA_SxCR_MBURST_0                    0x00800000U
-#define DMA_SxCR_MBURST_1                    0x01000000U
-#define DMA_SxCR_PBURST                      0x00600000U
-#define DMA_SxCR_PBURST_0                    0x00200000U
-#define DMA_SxCR_PBURST_1                    0x00400000U
-#define DMA_SxCR_CT                          0x00080000U
-#define DMA_SxCR_DBM                         0x00040000U
-#define DMA_SxCR_PL                          0x00030000U
-#define DMA_SxCR_PL_0                        0x00010000U
-#define DMA_SxCR_PL_1                        0x00020000U
-#define DMA_SxCR_PINCOS                      0x00008000U
-#define DMA_SxCR_MSIZE                       0x00006000U
-#define DMA_SxCR_MSIZE_0                     0x00002000U
-#define DMA_SxCR_MSIZE_1                     0x00004000U
-#define DMA_SxCR_PSIZE                       0x00001800U
-#define DMA_SxCR_PSIZE_0                     0x00000800U
-#define DMA_SxCR_PSIZE_1                     0x00001000U
-#define DMA_SxCR_MINC                        0x00000400U
-#define DMA_SxCR_PINC                        0x00000200U
-#define DMA_SxCR_CIRC                        0x00000100U
-#define DMA_SxCR_DIR                         0x000000C0U
-#define DMA_SxCR_DIR_0                       0x00000040U
-#define DMA_SxCR_DIR_1                       0x00000080U
-#define DMA_SxCR_PFCTRL                      0x00000020U
-#define DMA_SxCR_TCIE                        0x00000010U
-#define DMA_SxCR_HTIE                        0x00000008U
-#define DMA_SxCR_TEIE                        0x00000004U
-#define DMA_SxCR_DMEIE                       0x00000002U
-#define DMA_SxCR_EN                          0x00000001U
-
-/* Legacy defines */
-#define DMA_SxCR_ACK                         0x00100000U
-
-/********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            0x0000FFFFU
-#define DMA_SxNDT_0                          0x00000001U
-#define DMA_SxNDT_1                          0x00000002U
-#define DMA_SxNDT_2                          0x00000004U
-#define DMA_SxNDT_3                          0x00000008U
-#define DMA_SxNDT_4                          0x00000010U
-#define DMA_SxNDT_5                          0x00000020U
-#define DMA_SxNDT_6                          0x00000040U
-#define DMA_SxNDT_7                          0x00000080U
-#define DMA_SxNDT_8                          0x00000100U
-#define DMA_SxNDT_9                          0x00000200U
-#define DMA_SxNDT_10                         0x00000400U
-#define DMA_SxNDT_11                         0x00000800U
-#define DMA_SxNDT_12                         0x00001000U
-#define DMA_SxNDT_13                         0x00002000U
-#define DMA_SxNDT_14                         0x00004000U
-#define DMA_SxNDT_15                         0x00008000U
-
-/********************  Bits definition for DMA_SxFCR register  ****************/ 
-#define DMA_SxFCR_FEIE                       0x00000080U
-#define DMA_SxFCR_FS                         0x00000038U
-#define DMA_SxFCR_FS_0                       0x00000008U
-#define DMA_SxFCR_FS_1                       0x00000010U
-#define DMA_SxFCR_FS_2                       0x00000020U
-#define DMA_SxFCR_DMDIS                      0x00000004U
-#define DMA_SxFCR_FTH                        0x00000003U
-#define DMA_SxFCR_FTH_0                      0x00000001U
-#define DMA_SxFCR_FTH_1                      0x00000002U
-
-/********************  Bits definition for DMA_LISR register  *****************/ 
-#define DMA_LISR_TCIF3                       0x08000000U
-#define DMA_LISR_HTIF3                       0x04000000U
-#define DMA_LISR_TEIF3                       0x02000000U
-#define DMA_LISR_DMEIF3                      0x01000000U
-#define DMA_LISR_FEIF3                       0x00400000U
-#define DMA_LISR_TCIF2                       0x00200000U
-#define DMA_LISR_HTIF2                       0x00100000U
-#define DMA_LISR_TEIF2                       0x00080000U
-#define DMA_LISR_DMEIF2                      0x00040000U
-#define DMA_LISR_FEIF2                       0x00010000U
-#define DMA_LISR_TCIF1                       0x00000800U
-#define DMA_LISR_HTIF1                       0x00000400U
-#define DMA_LISR_TEIF1                       0x00000200U
-#define DMA_LISR_DMEIF1                      0x00000100U
-#define DMA_LISR_FEIF1                       0x00000040U
-#define DMA_LISR_TCIF0                       0x00000020U
-#define DMA_LISR_HTIF0                       0x00000010U
-#define DMA_LISR_TEIF0                       0x00000008U
-#define DMA_LISR_DMEIF0                      0x00000004U
-#define DMA_LISR_FEIF0                       0x00000001U
-
-/********************  Bits definition for DMA_HISR register  *****************/ 
-#define DMA_HISR_TCIF7                       0x08000000U
-#define DMA_HISR_HTIF7                       0x04000000U
-#define DMA_HISR_TEIF7                       0x02000000U
-#define DMA_HISR_DMEIF7                      0x01000000U
-#define DMA_HISR_FEIF7                       0x00400000U
-#define DMA_HISR_TCIF6                       0x00200000U
-#define DMA_HISR_HTIF6                       0x00100000U
-#define DMA_HISR_TEIF6                       0x00080000U
-#define DMA_HISR_DMEIF6                      0x00040000U
-#define DMA_HISR_FEIF6                       0x00010000U
-#define DMA_HISR_TCIF5                       0x00000800U
-#define DMA_HISR_HTIF5                       0x00000400U
-#define DMA_HISR_TEIF5                       0x00000200U
-#define DMA_HISR_DMEIF5                      0x00000100U
-#define DMA_HISR_FEIF5                       0x00000040U
-#define DMA_HISR_TCIF4                       0x00000020U
-#define DMA_HISR_HTIF4                       0x00000010U
-#define DMA_HISR_TEIF4                       0x00000008U
-#define DMA_HISR_DMEIF4                      0x00000004U
-#define DMA_HISR_FEIF4                       0x00000001U
-
-/********************  Bits definition for DMA_LIFCR register  ****************/ 
-#define DMA_LIFCR_CTCIF3                     0x08000000U
-#define DMA_LIFCR_CHTIF3                     0x04000000U
-#define DMA_LIFCR_CTEIF3                     0x02000000U
-#define DMA_LIFCR_CDMEIF3                    0x01000000U
-#define DMA_LIFCR_CFEIF3                     0x00400000U
-#define DMA_LIFCR_CTCIF2                     0x00200000U
-#define DMA_LIFCR_CHTIF2                     0x00100000U
-#define DMA_LIFCR_CTEIF2                     0x00080000U
-#define DMA_LIFCR_CDMEIF2                    0x00040000U
-#define DMA_LIFCR_CFEIF2                     0x00010000U
-#define DMA_LIFCR_CTCIF1                     0x00000800U
-#define DMA_LIFCR_CHTIF1                     0x00000400U
-#define DMA_LIFCR_CTEIF1                     0x00000200U
-#define DMA_LIFCR_CDMEIF1                    0x00000100U
-#define DMA_LIFCR_CFEIF1                     0x00000040U
-#define DMA_LIFCR_CTCIF0                     0x00000020U
-#define DMA_LIFCR_CHTIF0                     0x00000010U
-#define DMA_LIFCR_CTEIF0                     0x00000008U
-#define DMA_LIFCR_CDMEIF0                    0x00000004U
-#define DMA_LIFCR_CFEIF0                     0x00000001U
-
-/********************  Bits definition for DMA_HIFCR  register  ****************/ 
-#define DMA_HIFCR_CTCIF7                     0x08000000U
-#define DMA_HIFCR_CHTIF7                     0x04000000U
-#define DMA_HIFCR_CTEIF7                     0x02000000U
-#define DMA_HIFCR_CDMEIF7                    0x01000000U
-#define DMA_HIFCR_CFEIF7                     0x00400000U
-#define DMA_HIFCR_CTCIF6                     0x00200000U
-#define DMA_HIFCR_CHTIF6                     0x00100000U
-#define DMA_HIFCR_CTEIF6                     0x00080000U
-#define DMA_HIFCR_CDMEIF6                    0x00040000U
-#define DMA_HIFCR_CFEIF6                     0x00010000U
-#define DMA_HIFCR_CTCIF5                     0x00000800U
-#define DMA_HIFCR_CHTIF5                     0x00000400U
-#define DMA_HIFCR_CTEIF5                     0x00000200U
-#define DMA_HIFCR_CDMEIF5                    0x00000100U
-#define DMA_HIFCR_CFEIF5                     0x00000040U
-#define DMA_HIFCR_CTCIF4                     0x00000020U
-#define DMA_HIFCR_CHTIF4                     0x00000010U
-#define DMA_HIFCR_CTEIF4                     0x00000008U
-#define DMA_HIFCR_CDMEIF4                    0x00000004U
-#define DMA_HIFCR_CFEIF4                     0x00000001U
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                    External Interrupt/Event Controller                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    FLASH                                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    0x0000000FU
-#define FLASH_ACR_LATENCY_0WS                0x00000000U
-#define FLASH_ACR_LATENCY_1WS                0x00000001U
-#define FLASH_ACR_LATENCY_2WS                0x00000002U
-#define FLASH_ACR_LATENCY_3WS                0x00000003U
-#define FLASH_ACR_LATENCY_4WS                0x00000004U
-#define FLASH_ACR_LATENCY_5WS                0x00000005U
-#define FLASH_ACR_LATENCY_6WS                0x00000006U
-#define FLASH_ACR_LATENCY_7WS                0x00000007U
-
-#define FLASH_ACR_PRFTEN                     0x00000100U
-#define FLASH_ACR_ICEN                       0x00000200U
-#define FLASH_ACR_DCEN                       0x00000400U
-#define FLASH_ACR_ICRST                      0x00000800U
-#define FLASH_ACR_DCRST                      0x00001000U
-#define FLASH_ACR_BYTE0_ADDRESS              0x40023C00U
-#define FLASH_ACR_BYTE2_ADDRESS              0x40023C03U
-
-/*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         0x00000001U
-#define FLASH_SR_SOP                         0x00000002U
-#define FLASH_SR_WRPERR                      0x00000010U
-#define FLASH_SR_PGAERR                      0x00000020U
-#define FLASH_SR_PGPERR                      0x00000040U
-#define FLASH_SR_PGSERR                      0x00000080U
-#define FLASH_SR_BSY                         0x00010000U
-
-/*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          0x00000001U
-#define FLASH_CR_SER                         0x00000002U
-#define FLASH_CR_MER                         0x00000004U
-#define FLASH_CR_SNB                         0x000000F8U
-#define FLASH_CR_SNB_0                       0x00000008U
-#define FLASH_CR_SNB_1                       0x00000010U
-#define FLASH_CR_SNB_2                       0x00000020U
-#define FLASH_CR_SNB_3                       0x00000040U
-#define FLASH_CR_SNB_4                       0x00000080U
-#define FLASH_CR_PSIZE                       0x00000300U
-#define FLASH_CR_PSIZE_0                     0x00000100U
-#define FLASH_CR_PSIZE_1                     0x00000200U
-#define FLASH_CR_STRT                        0x00010000U
-#define FLASH_CR_EOPIE                       0x01000000U
-#define FLASH_CR_LOCK                        0x80000000U
-
-/*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                 0x00000001U
-#define FLASH_OPTCR_OPTSTRT                 0x00000002U
-#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
-#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
-#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
-
-#define FLASH_OPTCR_WDG_SW                  0x00000020U
-#define FLASH_OPTCR_nRST_STOP               0x00000040U
-#define FLASH_OPTCR_nRST_STDBY              0x00000080U
-#define FLASH_OPTCR_RDP                     0x0000FF00U
-#define FLASH_OPTCR_RDP_0                   0x00000100U
-#define FLASH_OPTCR_RDP_1                   0x00000200U
-#define FLASH_OPTCR_RDP_2                   0x00000400U
-#define FLASH_OPTCR_RDP_3                   0x00000800U
-#define FLASH_OPTCR_RDP_4                   0x00001000U
-#define FLASH_OPTCR_RDP_5                   0x00002000U
-#define FLASH_OPTCR_RDP_6                   0x00004000U
-#define FLASH_OPTCR_RDP_7                   0x00008000U
-#define FLASH_OPTCR_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR_nWRP_0                  0x00010000U
-#define FLASH_OPTCR_nWRP_1                  0x00020000U
-#define FLASH_OPTCR_nWRP_2                  0x00040000U
-#define FLASH_OPTCR_nWRP_3                  0x00080000U
-#define FLASH_OPTCR_nWRP_4                  0x00100000U
-#define FLASH_OPTCR_nWRP_5                  0x00200000U
-#define FLASH_OPTCR_nWRP_6                  0x00400000U
-#define FLASH_OPTCR_nWRP_7                  0x00800000U
-#define FLASH_OPTCR_nWRP_8                  0x01000000U
-#define FLASH_OPTCR_nWRP_9                  0x02000000U
-#define FLASH_OPTCR_nWRP_10                 0x04000000U
-#define FLASH_OPTCR_nWRP_11                 0x08000000U
-                                             
-/******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR1_nWRP_0                  0x00010000U
-#define FLASH_OPTCR1_nWRP_1                  0x00020000U
-#define FLASH_OPTCR1_nWRP_2                  0x00040000U
-#define FLASH_OPTCR1_nWRP_3                  0x00080000U
-#define FLASH_OPTCR1_nWRP_4                  0x00100000U
-#define FLASH_OPTCR1_nWRP_5                  0x00200000U
-#define FLASH_OPTCR1_nWRP_6                  0x00400000U
-#define FLASH_OPTCR1_nWRP_7                  0x00800000U
-#define FLASH_OPTCR1_nWRP_8                  0x01000000U
-#define FLASH_OPTCR1_nWRP_9                  0x02000000U
-#define FLASH_OPTCR1_nWRP_10                 0x04000000U
-#define FLASH_OPTCR1_nWRP_11                 0x08000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    0x00000003U
-#define GPIO_MODER_MODER0_0                  0x00000001U
-#define GPIO_MODER_MODER0_1                  0x00000002U
-
-#define GPIO_MODER_MODER1                    0x0000000CU
-#define GPIO_MODER_MODER1_0                  0x00000004U
-#define GPIO_MODER_MODER1_1                  0x00000008U
-
-#define GPIO_MODER_MODER2                    0x00000030U
-#define GPIO_MODER_MODER2_0                  0x00000010U
-#define GPIO_MODER_MODER2_1                  0x00000020U
-
-#define GPIO_MODER_MODER3                    0x000000C0U
-#define GPIO_MODER_MODER3_0                  0x00000040U
-#define GPIO_MODER_MODER3_1                  0x00000080U
-
-#define GPIO_MODER_MODER4                    0x00000300U
-#define GPIO_MODER_MODER4_0                  0x00000100U
-#define GPIO_MODER_MODER4_1                  0x00000200U
-
-#define GPIO_MODER_MODER5                    0x00000C00U
-#define GPIO_MODER_MODER5_0                  0x00000400U
-#define GPIO_MODER_MODER5_1                  0x00000800U
-
-#define GPIO_MODER_MODER6                    0x00003000U
-#define GPIO_MODER_MODER6_0                  0x00001000U
-#define GPIO_MODER_MODER6_1                  0x00002000U
-
-#define GPIO_MODER_MODER7                    0x0000C000U
-#define GPIO_MODER_MODER7_0                  0x00004000U
-#define GPIO_MODER_MODER7_1                  0x00008000U
-
-#define GPIO_MODER_MODER8                    0x00030000U
-#define GPIO_MODER_MODER8_0                  0x00010000U
-#define GPIO_MODER_MODER8_1                  0x00020000U
-
-#define GPIO_MODER_MODER9                    0x000C0000U
-#define GPIO_MODER_MODER9_0                  0x00040000U
-#define GPIO_MODER_MODER9_1                  0x00080000U
-
-#define GPIO_MODER_MODER10                   0x00300000U
-#define GPIO_MODER_MODER10_0                 0x00100000U
-#define GPIO_MODER_MODER10_1                 0x00200000U
-
-#define GPIO_MODER_MODER11                   0x00C00000U
-#define GPIO_MODER_MODER11_0                 0x00400000U
-#define GPIO_MODER_MODER11_1                 0x00800000U
-
-#define GPIO_MODER_MODER12                   0x03000000U
-#define GPIO_MODER_MODER12_0                 0x01000000U
-#define GPIO_MODER_MODER12_1                 0x02000000U
-
-#define GPIO_MODER_MODER13                   0x0C000000U
-#define GPIO_MODER_MODER13_0                 0x04000000U
-#define GPIO_MODER_MODER13_1                 0x08000000U
-
-#define GPIO_MODER_MODER14                   0x30000000U
-#define GPIO_MODER_MODER14_0                 0x10000000U
-#define GPIO_MODER_MODER14_1                 0x20000000U
-
-#define GPIO_MODER_MODER15                   0xC0000000U
-#define GPIO_MODER_MODER15_0                 0x40000000U
-#define GPIO_MODER_MODER15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     0x00000001U
-#define GPIO_OTYPER_OT_1                     0x00000002U
-#define GPIO_OTYPER_OT_2                     0x00000004U
-#define GPIO_OTYPER_OT_3                     0x00000008U
-#define GPIO_OTYPER_OT_4                     0x00000010U
-#define GPIO_OTYPER_OT_5                     0x00000020U
-#define GPIO_OTYPER_OT_6                     0x00000040U
-#define GPIO_OTYPER_OT_7                     0x00000080U
-#define GPIO_OTYPER_OT_8                     0x00000100U
-#define GPIO_OTYPER_OT_9                     0x00000200U
-#define GPIO_OTYPER_OT_10                    0x00000400U
-#define GPIO_OTYPER_OT_11                    0x00000800U
-#define GPIO_OTYPER_OT_12                    0x00001000U
-#define GPIO_OTYPER_OT_13                    0x00002000U
-#define GPIO_OTYPER_OT_14                    0x00004000U
-#define GPIO_OTYPER_OT_15                    0x00008000U
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
-#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
-#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
-
-#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
-#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
-#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
-
-#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
-#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
-#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
-
-#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
-#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
-#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
-
-#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
-#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
-#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
-
-#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
-#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
-#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
-
-#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
-#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
-#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
-
-#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
-#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
-#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
-
-#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
-#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
-#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
-
-#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
-#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
-#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
-
-#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
-#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
-#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
-
-#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
-#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
-#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
-
-#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
-#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
-#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
-
-#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
-#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
-#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
-
-#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
-#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
-#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
-
-#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
-#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
-#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    0x00000003U
-#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
-#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
-
-#define GPIO_PUPDR_PUPDR1                    0x0000000CU
-#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
-#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
-
-#define GPIO_PUPDR_PUPDR2                    0x00000030U
-#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
-#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
-
-#define GPIO_PUPDR_PUPDR3                    0x000000C0U
-#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
-#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
-
-#define GPIO_PUPDR_PUPDR4                    0x00000300U
-#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
-#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
-
-#define GPIO_PUPDR_PUPDR5                    0x00000C00U
-#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
-#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
-
-#define GPIO_PUPDR_PUPDR6                    0x00003000U
-#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
-#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
-
-#define GPIO_PUPDR_PUPDR7                    0x0000C000U
-#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
-#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
-
-#define GPIO_PUPDR_PUPDR8                    0x00030000U
-#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
-#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
-
-#define GPIO_PUPDR_PUPDR9                    0x000C0000U
-#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
-#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
-
-#define GPIO_PUPDR_PUPDR10                   0x00300000U
-#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
-#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
-
-#define GPIO_PUPDR_PUPDR11                   0x00C00000U
-#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
-#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
-
-#define GPIO_PUPDR_PUPDR12                   0x03000000U
-#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
-#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
-
-#define GPIO_PUPDR_PUPDR13                   0x0C000000U
-#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
-#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
-
-#define GPIO_PUPDR_PUPDR14                   0x30000000U
-#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
-#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
-
-#define GPIO_PUPDR_PUPDR15                   0xC0000000U
-#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
-#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       0x00000001U
-#define GPIO_IDR_IDR_1                       0x00000002U
-#define GPIO_IDR_IDR_2                       0x00000004U
-#define GPIO_IDR_IDR_3                       0x00000008U
-#define GPIO_IDR_IDR_4                       0x00000010U
-#define GPIO_IDR_IDR_5                       0x00000020U
-#define GPIO_IDR_IDR_6                       0x00000040U
-#define GPIO_IDR_IDR_7                       0x00000080U
-#define GPIO_IDR_IDR_8                       0x00000100U
-#define GPIO_IDR_IDR_9                       0x00000200U
-#define GPIO_IDR_IDR_10                      0x00000400U
-#define GPIO_IDR_IDR_11                      0x00000800U
-#define GPIO_IDR_IDR_12                      0x00001000U
-#define GPIO_IDR_IDR_13                      0x00002000U
-#define GPIO_IDR_IDR_14                      0x00004000U
-#define GPIO_IDR_IDR_15                      0x00008000U
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       0x00000001U
-#define GPIO_ODR_ODR_1                       0x00000002U
-#define GPIO_ODR_ODR_2                       0x00000004U
-#define GPIO_ODR_ODR_3                       0x00000008U
-#define GPIO_ODR_ODR_4                       0x00000010U
-#define GPIO_ODR_ODR_5                       0x00000020U
-#define GPIO_ODR_ODR_6                       0x00000040U
-#define GPIO_ODR_ODR_7                       0x00000080U
-#define GPIO_ODR_ODR_8                       0x00000100U
-#define GPIO_ODR_ODR_9                       0x00000200U
-#define GPIO_ODR_ODR_10                      0x00000400U
-#define GPIO_ODR_ODR_11                      0x00000800U
-#define GPIO_ODR_ODR_12                      0x00001000U
-#define GPIO_ODR_ODR_13                      0x00002000U
-#define GPIO_ODR_ODR_14                      0x00004000U
-#define GPIO_ODR_ODR_15                      0x00008000U
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       0x00000001U
-#define GPIO_BSRR_BS_1                       0x00000002U
-#define GPIO_BSRR_BS_2                       0x00000004U
-#define GPIO_BSRR_BS_3                       0x00000008U
-#define GPIO_BSRR_BS_4                       0x00000010U
-#define GPIO_BSRR_BS_5                       0x00000020U
-#define GPIO_BSRR_BS_6                       0x00000040U
-#define GPIO_BSRR_BS_7                       0x00000080U
-#define GPIO_BSRR_BS_8                       0x00000100U
-#define GPIO_BSRR_BS_9                       0x00000200U
-#define GPIO_BSRR_BS_10                      0x00000400U
-#define GPIO_BSRR_BS_11                      0x00000800U
-#define GPIO_BSRR_BS_12                      0x00001000U
-#define GPIO_BSRR_BS_13                      0x00002000U
-#define GPIO_BSRR_BS_14                      0x00004000U
-#define GPIO_BSRR_BS_15                      0x00008000U
-#define GPIO_BSRR_BR_0                       0x00010000U
-#define GPIO_BSRR_BR_1                       0x00020000U
-#define GPIO_BSRR_BR_2                       0x00040000U
-#define GPIO_BSRR_BR_3                       0x00080000U
-#define GPIO_BSRR_BR_4                       0x00100000U
-#define GPIO_BSRR_BR_5                       0x00200000U
-#define GPIO_BSRR_BR_6                       0x00400000U
-#define GPIO_BSRR_BR_7                       0x00800000U
-#define GPIO_BSRR_BR_8                       0x01000000U
-#define GPIO_BSRR_BR_9                       0x02000000U
-#define GPIO_BSRR_BR_10                      0x04000000U
-#define GPIO_BSRR_BR_11                      0x08000000U
-#define GPIO_BSRR_BR_12                      0x10000000U
-#define GPIO_BSRR_BR_13                      0x20000000U
-#define GPIO_BSRR_BR_14                      0x40000000U
-#define GPIO_BSRR_BR_15                      0x80000000U
-
-/****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0                       0x00000001U
-#define GPIO_LCKR_LCK1                       0x00000002U
-#define GPIO_LCKR_LCK2                       0x00000004U
-#define GPIO_LCKR_LCK3                       0x00000008U
-#define GPIO_LCKR_LCK4                       0x00000010U
-#define GPIO_LCKR_LCK5                       0x00000020U
-#define GPIO_LCKR_LCK6                       0x00000040U
-#define GPIO_LCKR_LCK7                       0x00000080U
-#define GPIO_LCKR_LCK8                       0x00000100U
-#define GPIO_LCKR_LCK9                       0x00000200U
-#define GPIO_LCKR_LCK10                      0x00000400U
-#define GPIO_LCKR_LCK11                      0x00000800U
-#define GPIO_LCKR_LCK12                      0x00001000U
-#define GPIO_LCKR_LCK13                      0x00002000U
-#define GPIO_LCKR_LCK14                      0x00004000U
-#define GPIO_LCKR_LCK15                      0x00008000U
-#define GPIO_LCKR_LCKK                       0x00010000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Inter-integrated Circuit Interface                    */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          0x00000001U     /*!<Peripheral Enable                             */
-#define  I2C_CR1_SMBUS                       0x00000002U     /*!<SMBus Mode                                    */
-#define  I2C_CR1_SMBTYPE                     0x00000008U     /*!<SMBus Type                                    */
-#define  I2C_CR1_ENARP                       0x00000010U     /*!<ARP Enable                                    */
-#define  I2C_CR1_ENPEC                       0x00000020U     /*!<PEC Enable                                    */
-#define  I2C_CR1_ENGC                        0x00000040U     /*!<General Call Enable                           */
-#define  I2C_CR1_NOSTRETCH                   0x00000080U     /*!<Clock Stretching Disable (Slave mode)  */
-#define  I2C_CR1_START                       0x00000100U     /*!<Start Generation                              */
-#define  I2C_CR1_STOP                        0x00000200U     /*!<Stop Generation                               */
-#define  I2C_CR1_ACK                         0x00000400U     /*!<Acknowledge Enable                            */
-#define  I2C_CR1_POS                         0x00000800U     /*!<Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         0x00001000U     /*!<Packet Error Checking                         */
-#define  I2C_CR1_ALERT                       0x00002000U     /*!<SMBus Alert                                   */
-#define  I2C_CR1_SWRST                       0x00008000U     /*!<Software Reset                                */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        0x0000003FU     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
-#define  I2C_CR2_FREQ_0                      0x00000001U     /*!<Bit 0 */
-#define  I2C_CR2_FREQ_1                      0x00000002U     /*!<Bit 1 */
-#define  I2C_CR2_FREQ_2                      0x00000004U     /*!<Bit 2 */
-#define  I2C_CR2_FREQ_3                      0x00000008U     /*!<Bit 3 */
-#define  I2C_CR2_FREQ_4                      0x00000010U     /*!<Bit 4 */
-#define  I2C_CR2_FREQ_5                      0x00000020U     /*!<Bit 5 */
-
-#define  I2C_CR2_ITERREN                     0x00000100U     /*!<Error Interrupt Enable  */
-#define  I2C_CR2_ITEVTEN                     0x00000200U     /*!<Event Interrupt Enable  */
-#define  I2C_CR2_ITBUFEN                     0x00000400U     /*!<Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       0x00000800U     /*!<DMA Requests Enable     */
-#define  I2C_CR2_LAST                        0x00001000U     /*!<DMA Last Transfer       */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     0x000000FEU     /*!<Interface Address */
-#define  I2C_OAR1_ADD8_9                     0x00000300U     /*!<Interface Address */
-
-#define  I2C_OAR1_ADD0                       0x00000001U     /*!<Bit 0 */
-#define  I2C_OAR1_ADD1                       0x00000002U     /*!<Bit 1 */
-#define  I2C_OAR1_ADD2                       0x00000004U     /*!<Bit 2 */
-#define  I2C_OAR1_ADD3                       0x00000008U     /*!<Bit 3 */
-#define  I2C_OAR1_ADD4                       0x00000010U     /*!<Bit 4 */
-#define  I2C_OAR1_ADD5                       0x00000020U     /*!<Bit 5 */
-#define  I2C_OAR1_ADD6                       0x00000040U     /*!<Bit 6 */
-#define  I2C_OAR1_ADD7                       0x00000080U     /*!<Bit 7 */
-#define  I2C_OAR1_ADD8                       0x00000100U     /*!<Bit 8 */
-#define  I2C_OAR1_ADD9                       0x00000200U     /*!<Bit 9 */
-
-#define  I2C_OAR1_ADDMODE                    0x00008000U     /*!<Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     0x00000001U        /*!<Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       0x000000FEU        /*!<Interface address           */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           0x000000FFU        /*!<8-bit Data Register         */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          0x00000001U     /*!<Start Bit (Master mode)                  */
-#define  I2C_SR1_ADDR                        0x00000002U     /*!<Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         0x00000004U     /*!<Byte Transfer Finished                          */
-#define  I2C_SR1_ADD10                       0x00000008U     /*!<10-bit header sent (Master mode)         */
-#define  I2C_SR1_STOPF                       0x00000010U     /*!<Stop detection (Slave mode)              */
-#define  I2C_SR1_RXNE                        0x00000040U     /*!<Data Register not Empty (receivers)      */
-#define  I2C_SR1_TXE                         0x00000080U     /*!<Data Register Empty (transmitters)       */
-#define  I2C_SR1_BERR                        0x00000100U     /*!<Bus Error                                       */
-#define  I2C_SR1_ARLO                        0x00000200U     /*!<Arbitration Lost (master mode)           */
-#define  I2C_SR1_AF                          0x00000400U     /*!<Acknowledge Failure                             */
-#define  I2C_SR1_OVR                         0x00000800U     /*!<Overrun/Underrun                                */
-#define  I2C_SR1_PECERR                      0x00001000U     /*!<PEC Error in reception                          */
-#define  I2C_SR1_TIMEOUT                     0x00004000U     /*!<Timeout or Tlow Error                           */
-#define  I2C_SR1_SMBALERT                    0x00008000U     /*!<SMBus Alert                                     */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         0x00000001U     /*!<Master/Slave                              */
-#define  I2C_SR2_BUSY                        0x00000002U     /*!<Bus Busy                                  */
-#define  I2C_SR2_TRA                         0x00000004U     /*!<Transmitter/Receiver                      */
-#define  I2C_SR2_GENCALL                     0x00000010U     /*!<General Call Address (Slave mode)  */
-#define  I2C_SR2_SMBDEFAULT                  0x00000020U     /*!<SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     0x00000040U     /*!<SMBus Host Header (Slave mode)     */
-#define  I2C_SR2_DUALF                       0x00000080U     /*!<Dual Flag (Slave mode)             */
-#define  I2C_SR2_PEC                         0x0000FF00U     /*!<Packet Error Checking Register            */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         0x00000FFFU     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        0x00004000U     /*!<Fast Mode Duty Cycle                                       */
-#define  I2C_CCR_FS                          0x00008000U     /*!<I2C Master Mode Selection                                  */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     0x0000003FU     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************  Bit definition for I2C_FLTR register  *******************/
-#define  I2C_FLTR_DNF                        0x0000000FU     /*!<Digital Noise Filter */
-#define  I2C_FLTR_ANOFF                      0x00000010U     /*!<Analog Noise Filter OFF */
-
-/******************************************************************************/
-/*                                                                            */
-/*        Fast Mode Plus Inter-integrated Circuit Interface (I2C)             */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define  FMPI2C_CR1_PE                        0x00000001U        /*!< Peripheral enable                   */
-#define  FMPI2C_CR1_TXIE                      0x00000002U        /*!< TX interrupt enable                 */
-#define  FMPI2C_CR1_RXIE                      0x00000004U        /*!< RX interrupt enable                 */
-#define  FMPI2C_CR1_ADDRIE                    0x00000008U        /*!< Address match interrupt enable      */
-#define  FMPI2C_CR1_NACKIE                    0x00000010U        /*!< NACK received interrupt enable      */
-#define  FMPI2C_CR1_STOPIE                    0x00000020U        /*!< STOP detection interrupt enable     */
-#define  FMPI2C_CR1_TCIE                      0x00000040U        /*!< Transfer complete interrupt enable  */
-#define  FMPI2C_CR1_ERRIE                     0x00000080U        /*!< Errors interrupt enable             */
-#define  FMPI2C_CR1_DFN                       0x00000F00U        /*!< Digital noise filter                */
-#define  FMPI2C_CR1_ANFOFF                    0x00001000U        /*!< Analog noise filter OFF             */
-#define  FMPI2C_CR1_TXDMAEN                   0x00004000U        /*!< DMA transmission requests enable    */
-#define  FMPI2C_CR1_RXDMAEN                   0x00008000U        /*!< DMA reception requests enable       */
-#define  FMPI2C_CR1_SBC                       0x00010000U        /*!< Slave byte control                  */
-#define  FMPI2C_CR1_NOSTRETCH                 0x00020000U        /*!< Clock stretching disable            */
-#define  FMPI2C_CR1_GCEN                      0x00080000U        /*!< General call enable                 */
-#define  FMPI2C_CR1_SMBHEN                    0x00100000U        /*!< SMBus host address enable           */
-#define  FMPI2C_CR1_SMBDEN                    0x00200000U        /*!< SMBus device default address enable */
-#define  FMPI2C_CR1_ALERTEN                   0x00400000U        /*!< SMBus alert enable                  */
-#define  FMPI2C_CR1_PECEN                     0x00800000U        /*!< PEC enable                          */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define  FMPI2C_CR2_SADD                      0x000003FFU        /*!< Slave address (master mode)                             */
-#define  FMPI2C_CR2_RD_WRN                    0x00000400U        /*!< Transfer direction (master mode)                        */
-#define  FMPI2C_CR2_ADD10                     0x00000800U        /*!< 10-bit addressing mode (master mode)                    */
-#define  FMPI2C_CR2_HEAD10R                   0x00001000U        /*!< 10-bit address header only read direction (master mode) */
-#define  FMPI2C_CR2_START                     0x00002000U        /*!< START generation                                        */
-#define  FMPI2C_CR2_STOP                      0x00004000U        /*!< STOP generation (master mode)                           */
-#define  FMPI2C_CR2_NACK                      0x00008000U        /*!< NACK generation (slave mode)                            */
-#define  FMPI2C_CR2_NBYTES                    0x00FF0000U        /*!< Number of bytes                                         */
-#define  FMPI2C_CR2_RELOAD                    0x01000000U        /*!< NBYTES reload mode                                      */
-#define  FMPI2C_CR2_AUTOEND                   0x02000000U        /*!< Automatic end mode (master mode)                        */
-#define  FMPI2C_CR2_PECBYTE                   0x04000000U        /*!< Packet error checking byte                              */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define  FMPI2C_OAR1_OA1                      0x000003FFU        /*!< Interface own address 1   */
-#define  FMPI2C_OAR1_OA1MODE                  0x00000400U        /*!< Own address 1 10-bit mode */
-#define  FMPI2C_OAR1_OA1EN                    0x00008000U        /*!< Own address 1 enable      */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define  FMPI2C_OAR2_OA2                      0x000000FEU        /*!< Interface own address 2 */
-#define  FMPI2C_OAR2_OA2MSK                   0x00000700U        /*!< Own address 2 masks     */
-#define  FMPI2C_OAR2_OA2EN                    0x00008000U        /*!< Own address 2 enable    */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define  FMPI2C_TIMINGR_SCLL                  0x000000FFU        /*!< SCL low period (master mode)  */
-#define  FMPI2C_TIMINGR_SCLH                  0x0000FF00U        /*!< SCL high period (master mode) */
-#define  FMPI2C_TIMINGR_SDADEL                0x000F0000U        /*!< Data hold time                */
-#define  FMPI2C_TIMINGR_SCLDEL                0x00F00000U        /*!< Data setup time               */
-#define  FMPI2C_TIMINGR_PRESC                 0xF0000000U        /*!< Timings prescaler             */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define  FMPI2C_TIMEOUTR_TIMEOUTA             0x00000FFFU        /*!< Bus timeout A                 */
-#define  FMPI2C_TIMEOUTR_TIDLE                0x00001000U        /*!< Idle clock timeout detection  */
-#define  FMPI2C_TIMEOUTR_TIMOUTEN             0x00008000U        /*!< Clock timeout enable          */
-#define  FMPI2C_TIMEOUTR_TIMEOUTB             0x0FFF0000U        /*!< Bus timeout B                 */
-#define  FMPI2C_TIMEOUTR_TEXTEN               0x80000000U        /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define  FMPI2C_ISR_TXE                       0x00000001U        /*!< Transmit data register empty     */
-#define  FMPI2C_ISR_TXIS                      0x00000002U        /*!< Transmit interrupt status        */
-#define  FMPI2C_ISR_RXNE                      0x00000004U        /*!< Receive data register not empty  */
-#define  FMPI2C_ISR_ADDR                      0x00000008U        /*!< Address matched (slave mode)     */
-#define  FMPI2C_ISR_NACKF                     0x00000010U        /*!< NACK received flag               */
-#define  FMPI2C_ISR_STOPF                     0x00000020U        /*!< STOP detection flag              */
-#define  FMPI2C_ISR_TC                        0x00000040U        /*!< Transfer complete (master mode)  */
-#define  FMPI2C_ISR_TCR                       0x00000080U        /*!< Transfer complete reload         */
-#define  FMPI2C_ISR_BERR                      0x00000100U        /*!< Bus error                        */
-#define  FMPI2C_ISR_ARLO                      0x00000200U        /*!< Arbitration lost                 */
-#define  FMPI2C_ISR_OVR                       0x00000400U        /*!< Overrun/Underrun                 */
-#define  FMPI2C_ISR_PECERR                    0x00000800U        /*!< PEC error in reception           */
-#define  FMPI2C_ISR_TIMEOUT                   0x00001000U        /*!< Timeout or Tlow detection flag   */
-#define  FMPI2C_ISR_ALERT                     0x00002000U        /*!< SMBus alert                      */
-#define  FMPI2C_ISR_BUSY                      0x00008000U        /*!< Bus busy                         */
-#define  FMPI2C_ISR_DIR                       0x00010000U        /*!< Transfer direction (slave mode)  */
-#define  FMPI2C_ISR_ADDCODE                   0x00FE0000U        /*!< Address match code (slave mode)  */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define  FMPI2C_ICR_ADDRCF                    0x00000008U        /*!< Address matched clear flag  */
-#define  FMPI2C_ICR_NACKCF                    0x00000010U        /*!< NACK clear flag             */
-#define  FMPI2C_ICR_STOPCF                    0x00000020U        /*!< STOP detection clear flag   */
-#define  FMPI2C_ICR_BERRCF                    0x00000100U        /*!< Bus error clear flag        */
-#define  FMPI2C_ICR_ARLOCF                    0x00000200U        /*!< Arbitration lost clear flag */
-#define  FMPI2C_ICR_OVRCF                     0x00000400U        /*!< Overrun/Underrun clear flag */
-#define  FMPI2C_ICR_PECCF                     0x00000800U        /*!< PAC error clear flag        */
-#define  FMPI2C_ICR_TIMOUTCF                  0x00001000U        /*!< Timeout clear flag          */
-#define  FMPI2C_ICR_ALERTCF                   0x00002000U        /*!< Alert clear flag            */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define  FMPI2C_PECR_PEC                      0x000000FFU        /*!< PEC register */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define  FMPI2C_RXDR_RXDATA                   0x000000FFU        /*!< 8-bit receive data */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define  FMPI2C_TXDR_TXDATA                   0x000000FFU        /*!< 8-bit transmit data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Independent WATCHDOG                             */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         0x01U               /*!<Watchdog prescaler value update      */
-#define  IWDG_SR_RVU                         0x02U               /*!<Watchdog counter reload value update */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                             Power Control                                  */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
-#define  PWR_CR_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
-#define  PWR_CR_CWUF                         0x00000004U     /*!< Clear Wakeup Flag                   */
-#define  PWR_CR_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
-#define  PWR_CR_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
-
-#define  PWR_CR_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        0x00000020U     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        0x00000040U     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        0x00000080U     /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
-
-#define  PWR_CR_DBP                          0x00000100U     /*!< Disable Backup Domain write protection                     */
-#define  PWR_CR_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                              */
-#define  PWR_CR_LPLVDS                       0x00000400U     /*!< Low Power Regulator Low Voltage in Deep Sleep mode         */
-#define  PWR_CR_MRLVDS                       0x00000800U     /*!< Main Regulator Low Voltage in Deep Sleep mode              */
-#define  PWR_CR_ADCDC1                       0x00002000U     /*!< Refer to AN4073 on how to use this bit                     */
-
-#define  PWR_CR_VOS                          0x0000C000U     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
-#define  PWR_CR_VOS_0                        0x00004000U     /*!< Bit 0 */
-#define  PWR_CR_VOS_1                        0x00008000U     /*!< Bit 1 */
-
-#define  PWR_CR_FMSSR                        0x00100000U     /*!< Flash Memory Sleep System Run        */
-#define  PWR_CR_FISSR                        0x00200000U     /*!< Flash Interface Stop while System Run */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         0x00000001U     /*!< Wakeup Flag                                      */
-#define  PWR_CSR_SBF                         0x00000002U     /*!< Standby Flag                                     */
-#define  PWR_CSR_PVDO                        0x00000004U     /*!< PVD Output                                       */
-#define  PWR_CSR_BRR                         0x00000008U     /*!< Backup regulator ready                           */
-#define  PWR_CSR_EWUP                        0x00000100U     /*!< Enable WKUP pin                                  */
-#define  PWR_CSR_BRE                         0x00000200U     /*!< Backup regulator enable                          */
-#define  PWR_CSR_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        0x00000001U
-#define  RCC_CR_HSIRDY                       0x00000002U
-
-#define  RCC_CR_HSITRIM                      0x000000F8U
-#define  RCC_CR_HSITRIM_0                    0x00000008U/*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    0x00000010U/*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    0x00000020U/*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    0x00000040U/*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    0x00000080U/*!<Bit 4 */
-
-#define  RCC_CR_HSICAL                       0x0000FF00U
-#define  RCC_CR_HSICAL_0                     0x00000100U/*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     0x00000200U/*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     0x00000400U/*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     0x00000800U/*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     0x00001000U/*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     0x00002000U/*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     0x00004000U/*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     0x00008000U/*!<Bit 7 */
-
-#define  RCC_CR_HSEON                        0x00010000U
-#define  RCC_CR_HSERDY                       0x00020000U
-#define  RCC_CR_HSEBYP                       0x00040000U
-#define  RCC_CR_CSSON                        0x00080000U
-#define  RCC_CR_PLLON                        0x01000000U
-#define  RCC_CR_PLLRDY                       0x02000000U
-#define  RCC_CR_PLLI2SON                     0x04000000U
-#define  RCC_CR_PLLI2SRDY                    0x08000000U
-
-/********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    0x0000003FU
-#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
-#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
-#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
-#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
-#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
-#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
-
-#define  RCC_PLLCFGR_PLLN                     0x00007FC0U
-#define  RCC_PLLCFGR_PLLN_0                   0x00000040U
-#define  RCC_PLLCFGR_PLLN_1                   0x00000080U
-#define  RCC_PLLCFGR_PLLN_2                   0x00000100U
-#define  RCC_PLLCFGR_PLLN_3                   0x00000200U
-#define  RCC_PLLCFGR_PLLN_4                   0x00000400U
-#define  RCC_PLLCFGR_PLLN_5                   0x00000800U
-#define  RCC_PLLCFGR_PLLN_6                   0x00001000U
-#define  RCC_PLLCFGR_PLLN_7                   0x00002000U
-#define  RCC_PLLCFGR_PLLN_8                   0x00004000U
-
-#define  RCC_PLLCFGR_PLLP                    0x00030000U
-#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
-#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
-
-#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
-
-#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
-#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
-#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
-#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
-#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
-
-#define  RCC_PLLCFGR_PLLR                    0x70000000U
-#define  RCC_PLLCFGR_PLLR_0                  0x10000000U
-#define  RCC_PLLCFGR_PLLR_1                  0x20000000U
-#define  RCC_PLLCFGR_PLLR_2                  0x40000000U
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-/*!< SW configuration */
-#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
-
-#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock      */
-#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock      */
-#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL/PLLP selected as system clock */
-#define  RCC_CFGR_SW_PLLR                    0x00000003U        /*!< PLL/PLLR selected as system clock */
-
-/*!< SWS configuration */
-#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
-
-#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL/PLLP used as system clock       */
-#define  RCC_CFGR_SWS_PLLR                   0x0000000CU        /*!< PLL/PLLR used as system clock       */
-
-/*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
-
-#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
-
-/*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     0x001F0000U
-#define  RCC_CFGR_RTCPRE_0                   0x00010000U
-#define  RCC_CFGR_RTCPRE_1                   0x00020000U
-#define  RCC_CFGR_RTCPRE_2                   0x00040000U
-#define  RCC_CFGR_RTCPRE_3                   0x00080000U
-#define  RCC_CFGR_RTCPRE_4                   0x00100000U
-
-/*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       0x00600000U
-#define  RCC_CFGR_MCO1_0                     0x00200000U
-#define  RCC_CFGR_MCO1_1                     0x00400000U
-
-#define  RCC_CFGR_MCO1PRE                    0x07000000U
-#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
-#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
-#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
-
-/********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     0x00000001U
-#define  RCC_CIR_LSERDYF                     0x00000002U
-#define  RCC_CIR_HSIRDYF                     0x00000004U
-#define  RCC_CIR_HSERDYF                     0x00000008U
-#define  RCC_CIR_PLLRDYF                     0x00000010U
-#define  RCC_CIR_PLLI2SRDYF                  0x00000020U
-
-#define  RCC_CIR_CSSF                        0x00000080U
-#define  RCC_CIR_LSIRDYIE                    0x00000100U
-#define  RCC_CIR_LSERDYIE                    0x00000200U
-#define  RCC_CIR_HSIRDYIE                    0x00000400U
-#define  RCC_CIR_HSERDYIE                    0x00000800U
-#define  RCC_CIR_PLLRDYIE                    0x00001000U
-#define  RCC_CIR_PLLI2SRDYIE                 0x00002000U
-
-#define  RCC_CIR_LSIRDYC                     0x00010000U
-#define  RCC_CIR_LSERDYC                     0x00020000U
-#define  RCC_CIR_HSIRDYC                     0x00040000U
-#define  RCC_CIR_HSERDYC                     0x00080000U
-#define  RCC_CIR_PLLRDYC                     0x00100000U
-#define  RCC_CIR_PLLI2SRDYC                  0x00200000U
-
-#define  RCC_CIR_CSSC                        0x00800000U
-
-/********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
-#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
-#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
-#define  RCC_AHB1RSTR_GPIODRST               0x00000008U
-#define  RCC_AHB1RSTR_GPIOERST               0x00000010U
-#define  RCC_AHB1RSTR_GPIOFRST               0x00000020U
-#define  RCC_AHB1RSTR_GPIOGRST               0x00000040U
-#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
-#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
-#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
-#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
-
-/********************  Bit definition for RCC_AHB2RSTR register  **************/
-#define  RCC_AHB2RSTR_RNGRST                 0x00000040U
-#define  RCC_AHB2RSTR_OTGFSRST               0x00000080U
-
-/********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM2RST                0x00000001U
-#define  RCC_APB1RSTR_TIM3RST                0x00000002U
-#define  RCC_APB1RSTR_TIM4RST                0x00000004U
-#define  RCC_APB1RSTR_TIM5RST                0x00000008U
-#define  RCC_APB1RSTR_TIM6RST                0x00000010U
-#define  RCC_APB1RSTR_TIM7RST                0x00000020U
-#define  RCC_APB1RSTR_TIM12RST               0x00000040U
-#define  RCC_APB1RSTR_TIM13RST               0x00000080U
-#define  RCC_APB1RSTR_TIM14RST               0x00000100U
-#define  RCC_APB1RSTR_WWDGRST                0x00000800U
-#define  RCC_APB1RSTR_SPI2RST                0x00004000U
-#define  RCC_APB1RSTR_SPI3RST                0x00008000U
-#define  RCC_APB1RSTR_USART2RST              0x00020000U
-#define  RCC_APB1RSTR_I2C1RST                0x00200000U
-#define  RCC_APB1RSTR_I2C2RST                0x00400000U
-#define  RCC_APB1RSTR_I2C3RST                0x00800000U
-#define  RCC_APB1RSTR_FMPI2C1RST             0x01000000U
-#define  RCC_APB1RSTR_CAN1RST                0x02000000U
-#define  RCC_APB1RSTR_CAN2RST                0x04000000U
-#define  RCC_APB1RSTR_PWRRST                 0x10000000U
-
-/********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                0x00000001U
-#define  RCC_APB2RSTR_TIM8RST                0x00000002U
-#define  RCC_APB2RSTR_USART1RST              0x00000010U
-#define  RCC_APB2RSTR_USART6RST              0x00000020U
-#define  RCC_APB2RSTR_ADCRST                 0x00000100U
-#define  RCC_APB2RSTR_SDIORST                0x00000800U
-#define  RCC_APB2RSTR_SPI1RST                0x00001000U
-#define  RCC_APB2RSTR_SPI4RST                0x00002000U
-#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
-#define  RCC_APB2RSTR_TIM9RST                0x00010000U
-#define  RCC_APB2RSTR_TIM10RST               0x00020000U
-#define  RCC_APB2RSTR_TIM11RST               0x00040000U
-#define  RCC_APB2RSTR_SPI5RST                0x00100000U
-#define  RCC_APB2RSTR_DFSDM1RST              0x01000000U
-
-/********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
-#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
-#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
-#define  RCC_AHB1ENR_GPIODEN                 0x00000008U
-#define  RCC_AHB1ENR_GPIOEEN                 0x00000010U
-#define  RCC_AHB1ENR_GPIOFEN                 0x00000020U
-#define  RCC_AHB1ENR_GPIOGEN                 0x00000040U
-#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
-#define  RCC_AHB1ENR_CRCEN                   0x00001000U
-#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
-#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
-
-/********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define  RCC_AHB2ENR_RNGEN                   0x00000040U
-#define  RCC_AHB2ENR_OTGFSEN                 0x00000080U
-
-/********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM2EN                  0x00000001U
-#define  RCC_APB1ENR_TIM3EN                  0x00000002U
-#define  RCC_APB1ENR_TIM4EN                  0x00000004U
-#define  RCC_APB1ENR_TIM5EN                  0x00000008U
-#define  RCC_APB1ENR_TIM6EN                  0x00000010U
-#define  RCC_APB1ENR_TIM7EN                  0x00000020U
-#define  RCC_APB1ENR_TIM12EN                 0x00000040U
-#define  RCC_APB1ENR_TIM13EN                 0x00000080U
-#define  RCC_APB1ENR_TIM14EN                 0x00000100U
-#define  RCC_APB1ENR_RTCAPBEN                0x00000400U
-#define  RCC_APB1ENR_WWDGEN                  0x00000800U
-#define  RCC_APB1ENR_SPI2EN                  0x00004000U
-#define  RCC_APB1ENR_SPI3EN                  0x00008000U
-#define  RCC_APB1ENR_USART2EN                0x00020000U
-#define  RCC_APB1ENR_I2C1EN                  0x00200000U
-#define  RCC_APB1ENR_I2C2EN                  0x00400000U
-#define  RCC_APB1ENR_I2C3EN                  0x00800000U
-#define  RCC_APB1ENR_FMPI2C1EN               0x01000000U
-#define  RCC_APB1ENR_CAN1EN                  0x02000000U
-#define  RCC_APB1ENR_CAN2EN                  0x04000000U
-#define  RCC_APB1ENR_PWREN                   0x10000000U
-
-/********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  0x00000001U
-#define  RCC_APB2ENR_TIM8EN                  0x00000002U
-#define  RCC_APB2ENR_USART1EN                0x00000010U
-#define  RCC_APB2ENR_USART6EN                0x00000020U
-#define  RCC_APB2ENR_ADC1EN                  0x00000100U
-#define  RCC_APB2ENR_SDIOEN                  0x00000800U
-#define  RCC_APB2ENR_SPI1EN                  0x00001000U
-#define  RCC_APB2ENR_SPI4EN                  0x00002000U
-#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
-#define  RCC_APB2ENR_EXTITEN                 0x00008000U
-#define  RCC_APB2ENR_TIM9EN                  0x00010000U
-#define  RCC_APB2ENR_TIM10EN                 0x00020000U
-#define  RCC_APB2ENR_TIM11EN                 0x00040000U
-#define  RCC_APB2ENR_SPI5EN                  0x00100000U
-#define  RCC_APB2ENR_DFSDM1EN                0x01000000U
-/********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
-#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
-#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
-#define  RCC_AHB1LPENR_GPIODLPEN             0x00000008U
-#define  RCC_AHB1LPENR_GPIOELPEN             0x00000010U
-#define  RCC_AHB1LPENR_GPIOFLPEN             0x00000020U
-#define  RCC_AHB1LPENR_GPIOGLPEN             0x00000040U
-#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
-#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
-#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
-#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
-#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
-#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
-
-/********************  Bit definition for RCC_AHB2LPENR register  *************/
-#define  RCC_AHB2LPENR_RNGLPEN               0x00000040U
-#define  RCC_AHB2LPENR_OTGFSLPEN             0x00000080U
-
-/********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM2LPEN              0x00000001U
-#define  RCC_APB1LPENR_TIM3LPEN              0x00000002U
-#define  RCC_APB1LPENR_TIM4LPEN              0x00000004U
-#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
-#define  RCC_APB1LPENR_TIM6LPEN              0x00000010U
-#define  RCC_APB1LPENR_TIM7LPEN              0x00000020U
-#define  RCC_APB1LPENR_TIM12LPEN             0x00000040U
-#define  RCC_APB1LPENR_TIM13LPEN             0x00000080U
-#define  RCC_APB1LPENR_TIM14LPEN             0x00000100U
-#define  RCC_APB1LPENR_RTCAPBLPEN            0x00000400U
-#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
-#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U
-#define  RCC_APB1LPENR_SPI3LPEN              0x00008000U
-#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
-#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
-#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
-#define  RCC_APB1LPENR_I2C3LPEN              0x00800000U
-#define  RCC_APB1LPENR_FMPI2C1LPEN           0x01000000U
-#define  RCC_APB1LPENR_CAN1LPEN              0x02000000U
-#define  RCC_APB1LPENR_CAN2LPEN              0x04000000U
-#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
-
-/********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
-#define  RCC_APB2LPENR_TIM8LPEN              0x00000002U
-#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
-#define  RCC_APB2LPENR_USART6LPEN            0x00000020U
-#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
-#define  RCC_APB2LPENR_SDIOLPEN              0x00000800U
-#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
-#define  RCC_APB2LPENR_SPI4LPEN              0x00002000U
-#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
-#define  RCC_APB2LPENR_EXTITLPEN             0x00008000U
-#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
-#define  RCC_APB2LPENR_TIM10LPEN             0x00020000U
-#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
-#define  RCC_APB2LPENR_SPI5LPEN              0x00100000U
-#define  RCC_APB2LPENR_DFSDM1LPEN            0x01000000U
-
-/********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      0x00000001U
-#define  RCC_BDCR_LSERDY                     0x00000002U
-#define  RCC_BDCR_LSEBYP                     0x00000004U
-#define  RCC_BDCR_LSEMOD                     0x00000008U
-
-#define  RCC_BDCR_RTCSEL                    0x00000300U
-#define  RCC_BDCR_RTCSEL_0                  0x00000100U
-#define  RCC_BDCR_RTCSEL_1                  0x00000200U
-
-#define  RCC_BDCR_RTCEN                      0x00008000U
-#define  RCC_BDCR_BDRST                      0x00010000U
-
-/********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       0x00000001U
-#define  RCC_CSR_LSIRDY                      0x00000002U
-#define  RCC_CSR_RMVF                        0x01000000U
-#define  RCC_CSR_PADRSTF                     0x04000000U
-#define  RCC_CSR_PORRSTF                     0x08000000U
-#define  RCC_CSR_SFTRSTF                     0x10000000U
-#define  RCC_CSR_WDGRSTF                     0x20000000U
-#define  RCC_CSR_WWDGRSTF                    0x40000000U
-#define  RCC_CSR_LPWRRSTF                    0x80000000U
-
-/********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    0x00001FFFU
-#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
-#define  RCC_SSCGR_SPREADSEL                 0x40000000U
-#define  RCC_SSCGR_SSCGEN                    0x80000000U
-
-/********************  Bit definition for RCC_PLLI2SCFGR register  ************/
-#define  RCC_PLLI2SCFGR_PLLI2SM              0x0000003FU
-#define  RCC_PLLI2SCFGR_PLLI2SM_0            0x00000001U
-#define  RCC_PLLI2SCFGR_PLLI2SM_1            0x00000002U
-#define  RCC_PLLI2SCFGR_PLLI2SM_2            0x00000004U
-#define  RCC_PLLI2SCFGR_PLLI2SM_3            0x00000008U
-#define  RCC_PLLI2SCFGR_PLLI2SM_4            0x00000010U
-#define  RCC_PLLI2SCFGR_PLLI2SM_5            0x00000020U
-
-#define  RCC_PLLI2SCFGR_PLLI2SN              0x00007FC0U
-#define  RCC_PLLI2SCFGR_PLLI2SN_0            0x00000040U
-#define  RCC_PLLI2SCFGR_PLLI2SN_1            0x00000080U
-#define  RCC_PLLI2SCFGR_PLLI2SN_2            0x00000100U
-#define  RCC_PLLI2SCFGR_PLLI2SN_3            0x00000200U
-#define  RCC_PLLI2SCFGR_PLLI2SN_4            0x00000400U
-#define  RCC_PLLI2SCFGR_PLLI2SN_5            0x00000800U
-#define  RCC_PLLI2SCFGR_PLLI2SN_6            0x00001000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_7            0x00002000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_8            0x00004000U
-
-#define  RCC_PLLI2SCFGR_PLLI2SSRC            0x00400000U
-
-#define  RCC_PLLI2SCFGR_PLLI2SQ              0x0F000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_0            0x01000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_1            0x02000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_2            0x04000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_3            0x08000000U
-
-#define  RCC_PLLI2SCFGR_PLLI2SR              0x70000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_0            0x10000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_1            0x20000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_2            0x40000000U
-
-/********************  Bit definition for RCC_DCKCFGR register  ****************/
-#define  RCC_DCKCFGR_CKDFSDM1ASEL            0x00008000U
-#define  RCC_DCKCFGR_TIMPRE                  0x01000000U
-
-#define  RCC_DCKCFGR_I2S1SRC                 0x06000000U
-#define  RCC_DCKCFGR_I2S1SRC_0               0x02000000U
-#define  RCC_DCKCFGR_I2S1SRC_1               0x04000000U
-
-#define  RCC_DCKCFGR_I2S2SRC                 0x18000000U
-#define  RCC_DCKCFGR_I2S2SRC_0               0x08000000U
-#define  RCC_DCKCFGR_I2S2SRC_1               0x10000000U
-
-#define  RCC_DCKCFGR_CKDFSDM1SEL             0x80000000U
-
-/********************  Bit definition for RCC_CKGATENR register  ***************/
-#define  RCC_CKGATENR_AHB2APB1_CKEN          0x00000001U
-#define  RCC_CKGATENR_AHB2APB2_CKEN          0x00000002U
-#define  RCC_CKGATENR_CM4DBG_CKEN            0x00000004U
-#define  RCC_CKGATENR_SPARE_CKEN             0x00000008U
-#define  RCC_CKGATENR_SRAM_CKEN              0x00000010U
-#define  RCC_CKGATENR_FLITF_CKEN             0x00000020U
-#define  RCC_CKGATENR_RCC_CKEN               0x00000040U
-#define  RCC_CKGATENR_RCC_EVTCTL             0x00000080U
-
-/********************  Bit definition for RCC_DCKCFGR2 register  ***************/
-#define  RCC_DCKCFGR2_FMPI2C1SEL             0x00C00000U
-#define  RCC_DCKCFGR2_FMPI2C1SEL_0           0x00400000U
-#define  RCC_DCKCFGR2_FMPI2C1SEL_1           0x00800000U
-
-#define  RCC_DCKCFGR2_CK48MSEL               0x08000000U
-#define  RCC_DCKCFGR2_SDIOSEL                0x10000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    RNG                                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN                         0x00000004U
-#define RNG_CR_IE                            0x00000008U
-
-/********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY                          0x00000001U
-#define RNG_SR_CECS                          0x00000002U
-#define RNG_SR_SECS                          0x00000004U
-#define RNG_SR_CEIS                          0x00000020U
-#define RNG_SR_SEIS                          0x00000040U
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            0x00400000U
-#define RTC_TR_HT                            0x00300000U
-#define RTC_TR_HT_0                          0x00100000U
-#define RTC_TR_HT_1                          0x00200000U
-#define RTC_TR_HU                            0x000F0000U
-#define RTC_TR_HU_0                          0x00010000U
-#define RTC_TR_HU_1                          0x00020000U
-#define RTC_TR_HU_2                          0x00040000U
-#define RTC_TR_HU_3                          0x00080000U
-#define RTC_TR_MNT                           0x00007000U
-#define RTC_TR_MNT_0                         0x00001000U
-#define RTC_TR_MNT_1                         0x00002000U
-#define RTC_TR_MNT_2                         0x00004000U
-#define RTC_TR_MNU                           0x00000F00U
-#define RTC_TR_MNU_0                         0x00000100U
-#define RTC_TR_MNU_1                         0x00000200U
-#define RTC_TR_MNU_2                         0x00000400U
-#define RTC_TR_MNU_3                         0x00000800U
-#define RTC_TR_ST                            0x00000070U
-#define RTC_TR_ST_0                          0x00000010U
-#define RTC_TR_ST_1                          0x00000020U
-#define RTC_TR_ST_2                          0x00000040U
-#define RTC_TR_SU                            0x0000000FU
-#define RTC_TR_SU_0                          0x00000001U
-#define RTC_TR_SU_1                          0x00000002U
-#define RTC_TR_SU_2                          0x00000004U
-#define RTC_TR_SU_3                          0x00000008U
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            0x00F00000U
-#define RTC_DR_YT_0                          0x00100000U
-#define RTC_DR_YT_1                          0x00200000U
-#define RTC_DR_YT_2                          0x00400000U
-#define RTC_DR_YT_3                          0x00800000U
-#define RTC_DR_YU                            0x000F0000U
-#define RTC_DR_YU_0                          0x00010000U
-#define RTC_DR_YU_1                          0x00020000U
-#define RTC_DR_YU_2                          0x00040000U
-#define RTC_DR_YU_3                          0x00080000U
-#define RTC_DR_WDU                           0x0000E000U
-#define RTC_DR_WDU_0                         0x00002000U
-#define RTC_DR_WDU_1                         0x00004000U
-#define RTC_DR_WDU_2                         0x00008000U
-#define RTC_DR_MT                            0x00001000U
-#define RTC_DR_MU                            0x00000F00U
-#define RTC_DR_MU_0                          0x00000100U
-#define RTC_DR_MU_1                          0x00000200U
-#define RTC_DR_MU_2                          0x00000400U
-#define RTC_DR_MU_3                          0x00000800U
-#define RTC_DR_DT                            0x00000030U
-#define RTC_DR_DT_0                          0x00000010U
-#define RTC_DR_DT_1                          0x00000020U
-#define RTC_DR_DU                            0x0000000FU
-#define RTC_DR_DU_0                          0x00000001U
-#define RTC_DR_DU_1                          0x00000002U
-#define RTC_DR_DU_2                          0x00000004U
-#define RTC_DR_DU_3                          0x00000008U
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           0x00800000U
-#define RTC_CR_OSEL                          0x00600000U
-#define RTC_CR_OSEL_0                        0x00200000U
-#define RTC_CR_OSEL_1                        0x00400000U
-#define RTC_CR_POL                           0x00100000U
-#define RTC_CR_COSEL                         0x00080000U
-#define RTC_CR_BCK                           0x00040000U
-#define RTC_CR_SUB1H                         0x00020000U
-#define RTC_CR_ADD1H                         0x00010000U
-#define RTC_CR_TSIE                          0x00008000U
-#define RTC_CR_WUTIE                         0x00004000U
-#define RTC_CR_ALRBIE                        0x00002000U
-#define RTC_CR_ALRAIE                        0x00001000U
-#define RTC_CR_TSE                           0x00000800U
-#define RTC_CR_WUTE                          0x00000400U
-#define RTC_CR_ALRBE                         0x00000200U
-#define RTC_CR_ALRAE                         0x00000100U
-#define RTC_CR_DCE                           0x00000080U
-#define RTC_CR_FMT                           0x00000040U
-#define RTC_CR_BYPSHAD                       0x00000020U
-#define RTC_CR_REFCKON                       0x00000010U
-#define RTC_CR_TSEDGE                        0x00000008U
-#define RTC_CR_WUCKSEL                       0x00000007U
-#define RTC_CR_WUCKSEL_0                     0x00000001U
-#define RTC_CR_WUCKSEL_1                     0x00000002U
-#define RTC_CR_WUCKSEL_2                     0x00000004U
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      0x00010000U
-#define RTC_ISR_TAMP1F                       0x00002000U
-#define RTC_ISR_TAMP2F                       0x00004000U
-#define RTC_ISR_TSOVF                        0x00001000U
-#define RTC_ISR_TSF                          0x00000800U
-#define RTC_ISR_WUTF                         0x00000400U
-#define RTC_ISR_ALRBF                        0x00000200U
-#define RTC_ISR_ALRAF                        0x00000100U
-#define RTC_ISR_INIT                         0x00000080U
-#define RTC_ISR_INITF                        0x00000040U
-#define RTC_ISR_RSF                          0x00000020U
-#define RTC_ISR_INITS                        0x00000010U
-#define RTC_ISR_SHPF                         0x00000008U
-#define RTC_ISR_WUTWF                        0x00000004U
-#define RTC_ISR_ALRBWF                       0x00000002U
-#define RTC_ISR_ALRAWF                       0x00000001U
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    0x007F0000U
-#define RTC_PRER_PREDIV_S                    0x00007FFFU
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS                       0x00000080U
-#define RTC_CALIBR_DC                        0x0000001FU
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      0x80000000U
-#define RTC_ALRMAR_WDSEL                     0x40000000U
-#define RTC_ALRMAR_DT                        0x30000000U
-#define RTC_ALRMAR_DT_0                      0x10000000U
-#define RTC_ALRMAR_DT_1                      0x20000000U
-#define RTC_ALRMAR_DU                        0x0F000000U
-#define RTC_ALRMAR_DU_0                      0x01000000U
-#define RTC_ALRMAR_DU_1                      0x02000000U
-#define RTC_ALRMAR_DU_2                      0x04000000U
-#define RTC_ALRMAR_DU_3                      0x08000000U
-#define RTC_ALRMAR_MSK3                      0x00800000U
-#define RTC_ALRMAR_PM                        0x00400000U
-#define RTC_ALRMAR_HT                        0x00300000U
-#define RTC_ALRMAR_HT_0                      0x00100000U
-#define RTC_ALRMAR_HT_1                      0x00200000U
-#define RTC_ALRMAR_HU                        0x000F0000U
-#define RTC_ALRMAR_HU_0                      0x00010000U
-#define RTC_ALRMAR_HU_1                      0x00020000U
-#define RTC_ALRMAR_HU_2                      0x00040000U
-#define RTC_ALRMAR_HU_3                      0x00080000U
-#define RTC_ALRMAR_MSK2                      0x00008000U
-#define RTC_ALRMAR_MNT                       0x00007000U
-#define RTC_ALRMAR_MNT_0                     0x00001000U
-#define RTC_ALRMAR_MNT_1                     0x00002000U
-#define RTC_ALRMAR_MNT_2                     0x00004000U
-#define RTC_ALRMAR_MNU                       0x00000F00U
-#define RTC_ALRMAR_MNU_0                     0x00000100U
-#define RTC_ALRMAR_MNU_1                     0x00000200U
-#define RTC_ALRMAR_MNU_2                     0x00000400U
-#define RTC_ALRMAR_MNU_3                     0x00000800U
-#define RTC_ALRMAR_MSK1                      0x00000080U
-#define RTC_ALRMAR_ST                        0x00000070U
-#define RTC_ALRMAR_ST_0                      0x00000010U
-#define RTC_ALRMAR_ST_1                      0x00000020U
-#define RTC_ALRMAR_ST_2                      0x00000040U
-#define RTC_ALRMAR_SU                        0x0000000FU
-#define RTC_ALRMAR_SU_0                      0x00000001U
-#define RTC_ALRMAR_SU_1                      0x00000002U
-#define RTC_ALRMAR_SU_2                      0x00000004U
-#define RTC_ALRMAR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      0x80000000U
-#define RTC_ALRMBR_WDSEL                     0x40000000U
-#define RTC_ALRMBR_DT                        0x30000000U
-#define RTC_ALRMBR_DT_0                      0x10000000U
-#define RTC_ALRMBR_DT_1                      0x20000000U
-#define RTC_ALRMBR_DU                        0x0F000000U
-#define RTC_ALRMBR_DU_0                      0x01000000U
-#define RTC_ALRMBR_DU_1                      0x02000000U
-#define RTC_ALRMBR_DU_2                      0x04000000U
-#define RTC_ALRMBR_DU_3                      0x08000000U
-#define RTC_ALRMBR_MSK3                      0x00800000U
-#define RTC_ALRMBR_PM                        0x00400000U
-#define RTC_ALRMBR_HT                        0x00300000U
-#define RTC_ALRMBR_HT_0                      0x00100000U
-#define RTC_ALRMBR_HT_1                      0x00200000U
-#define RTC_ALRMBR_HU                        0x000F0000U
-#define RTC_ALRMBR_HU_0                      0x00010000U
-#define RTC_ALRMBR_HU_1                      0x00020000U
-#define RTC_ALRMBR_HU_2                      0x00040000U
-#define RTC_ALRMBR_HU_3                      0x00080000U
-#define RTC_ALRMBR_MSK2                      0x00008000U
-#define RTC_ALRMBR_MNT                       0x00007000U
-#define RTC_ALRMBR_MNT_0                     0x00001000U
-#define RTC_ALRMBR_MNT_1                     0x00002000U
-#define RTC_ALRMBR_MNT_2                     0x00004000U
-#define RTC_ALRMBR_MNU                       0x00000F00U
-#define RTC_ALRMBR_MNU_0                     0x00000100U
-#define RTC_ALRMBR_MNU_1                     0x00000200U
-#define RTC_ALRMBR_MNU_2                     0x00000400U
-#define RTC_ALRMBR_MNU_3                     0x00000800U
-#define RTC_ALRMBR_MSK1                      0x00000080U
-#define RTC_ALRMBR_ST                        0x00000070U
-#define RTC_ALRMBR_ST_0                      0x00000010U
-#define RTC_ALRMBR_ST_1                      0x00000020U
-#define RTC_ALRMBR_ST_2                      0x00000040U
-#define RTC_ALRMBR_SU                        0x0000000FU
-#define RTC_ALRMBR_SU_0                      0x00000001U
-#define RTC_ALRMBR_SU_1                      0x00000002U
-#define RTC_ALRMBR_SU_2                      0x00000004U
-#define RTC_ALRMBR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          0x000000FFU
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           0x0000FFFFU
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     0x00007FFFU
-#define RTC_SHIFTR_ADD1S                     0x80000000U
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          0x00400000U
-#define RTC_TSTR_HT                          0x00300000U
-#define RTC_TSTR_HT_0                        0x00100000U
-#define RTC_TSTR_HT_1                        0x00200000U
-#define RTC_TSTR_HU                          0x000F0000U
-#define RTC_TSTR_HU_0                        0x00010000U
-#define RTC_TSTR_HU_1                        0x00020000U
-#define RTC_TSTR_HU_2                        0x00040000U
-#define RTC_TSTR_HU_3                        0x00080000U
-#define RTC_TSTR_MNT                         0x00007000U
-#define RTC_TSTR_MNT_0                       0x00001000U
-#define RTC_TSTR_MNT_1                       0x00002000U
-#define RTC_TSTR_MNT_2                       0x00004000U
-#define RTC_TSTR_MNU                         0x00000F00U
-#define RTC_TSTR_MNU_0                       0x00000100U
-#define RTC_TSTR_MNU_1                       0x00000200U
-#define RTC_TSTR_MNU_2                       0x00000400U
-#define RTC_TSTR_MNU_3                       0x00000800U
-#define RTC_TSTR_ST                          0x00000070U
-#define RTC_TSTR_ST_0                        0x00000010U
-#define RTC_TSTR_ST_1                        0x00000020U
-#define RTC_TSTR_ST_2                        0x00000040U
-#define RTC_TSTR_SU                          0x0000000FU
-#define RTC_TSTR_SU_0                        0x00000001U
-#define RTC_TSTR_SU_1                        0x00000002U
-#define RTC_TSTR_SU_2                        0x00000004U
-#define RTC_TSTR_SU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         0x0000E000U
-#define RTC_TSDR_WDU_0                       0x00002000U
-#define RTC_TSDR_WDU_1                       0x00004000U
-#define RTC_TSDR_WDU_2                       0x00008000U
-#define RTC_TSDR_MT                          0x00001000U
-#define RTC_TSDR_MU                          0x00000F00U
-#define RTC_TSDR_MU_0                        0x00000100U
-#define RTC_TSDR_MU_1                        0x00000200U
-#define RTC_TSDR_MU_2                        0x00000400U
-#define RTC_TSDR_MU_3                        0x00000800U
-#define RTC_TSDR_DT                          0x00000030U
-#define RTC_TSDR_DT_0                        0x00000010U
-#define RTC_TSDR_DT_1                        0x00000020U
-#define RTC_TSDR_DU                          0x0000000FU
-#define RTC_TSDR_DU_0                        0x00000001U
-#define RTC_TSDR_DU_1                        0x00000002U
-#define RTC_TSDR_DU_2                        0x00000004U
-#define RTC_TSDR_DU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        0x00008000U
-#define RTC_CALR_CALW8                       0x00004000U
-#define RTC_CALR_CALW16                      0x00002000U
-#define RTC_CALR_CALM                        0x000001FFU
-#define RTC_CALR_CALM_0                      0x00000001U
-#define RTC_CALR_CALM_1                      0x00000002U
-#define RTC_CALR_CALM_2                      0x00000004U
-#define RTC_CALR_CALM_3                      0x00000008U
-#define RTC_CALR_CALM_4                      0x00000010U
-#define RTC_CALR_CALM_5                      0x00000020U
-#define RTC_CALR_CALM_6                      0x00000040U
-#define RTC_CALR_CALM_7                      0x00000080U
-#define RTC_CALR_CALM_8                      0x00000100U
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               0x00040000U
-#define RTC_TAFCR_TSINSEL                    0x00020000U
-#define RTC_TAFCR_TAMPINSEL                  0x00010000U
-#define RTC_TAFCR_TAMPPUDIS                  0x00008000U
-#define RTC_TAFCR_TAMPPRCH                   0x00006000U
-#define RTC_TAFCR_TAMPPRCH_0                 0x00002000U
-#define RTC_TAFCR_TAMPPRCH_1                 0x00004000U
-#define RTC_TAFCR_TAMPFLT                    0x00001800U
-#define RTC_TAFCR_TAMPFLT_0                  0x00000800U
-#define RTC_TAFCR_TAMPFLT_1                  0x00001000U
-#define RTC_TAFCR_TAMPFREQ                   0x00000700U
-#define RTC_TAFCR_TAMPFREQ_0                 0x00000100U
-#define RTC_TAFCR_TAMPFREQ_1                 0x00000200U
-#define RTC_TAFCR_TAMPFREQ_2                 0x00000400U
-#define RTC_TAFCR_TAMPTS                     0x00000080U
-#define RTC_TAFCR_TAMP2TRG                   0x00000010U
-#define RTC_TAFCR_TAMP2E                     0x00000008U
-#define RTC_TAFCR_TAMPIE                     0x00000004U
-#define RTC_TAFCR_TAMP1TRG                   0x00000002U
-#define RTC_TAFCR_TAMP1E                     0x00000001U
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  0x0F000000U
-#define RTC_ALRMASSR_MASKSS_0                0x01000000U
-#define RTC_ALRMASSR_MASKSS_1                0x02000000U
-#define RTC_ALRMASSR_MASKSS_2                0x04000000U
-#define RTC_ALRMASSR_MASKSS_3                0x08000000U
-#define RTC_ALRMASSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
-#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
-#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
-#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
-#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
-#define RTC_ALRMBSSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           0xFFFFFFFFU
-
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          SD host Interface                                 */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SDIO_POWER register  ******************/
-#define  SDIO_POWER_PWRCTRL                  0x03U               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDIO_POWER_PWRCTRL_0                0x01U               /*!<Bit 0 */
-#define  SDIO_POWER_PWRCTRL_1                0x02U               /*!<Bit 1 */
-
-/******************  Bit definition for SDIO_CLKCR register  ******************/
-#define  SDIO_CLKCR_CLKDIV                   0x00FFU            /*!<Clock divide factor             */
-#define  SDIO_CLKCR_CLKEN                    0x0100U            /*!<Clock enable bit                */
-#define  SDIO_CLKCR_PWRSAV                   0x0200U            /*!<Power saving configuration bit  */
-#define  SDIO_CLKCR_BYPASS                   0x0400U            /*!<Clock divider bypass enable bit */
-
-#define  SDIO_CLKCR_WIDBUS                   0x1800U            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDIO_CLKCR_WIDBUS_0                 0x0800U            /*!<Bit 0 */
-#define  SDIO_CLKCR_WIDBUS_1                 0x1000U            /*!<Bit 1 */
-
-#define  SDIO_CLKCR_NEGEDGE                  0x2000U            /*!<SDIO_CK dephasing selection bit */
-#define  SDIO_CLKCR_HWFC_EN                  0x4000U            /*!<HW Flow Control enable          */
-
-/*******************  Bit definition for SDIO_ARG register  *******************/
-#define  SDIO_ARG_CMDARG                     0xFFFFFFFFU            /*!<Command argument */
-
-/*******************  Bit definition for SDIO_CMD register  *******************/
-#define  SDIO_CMD_CMDINDEX                   0x003FU            /*!<Command Index                               */
-
-#define  SDIO_CMD_WAITRESP                   0x00C0U            /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDIO_CMD_WAITRESP_0                 0x0040U            /*!< Bit 0 */
-#define  SDIO_CMD_WAITRESP_1                 0x0080U            /*!< Bit 1 */
-
-#define  SDIO_CMD_WAITINT                    0x0100U            /*!<CPSM Waits for Interrupt Request                               */
-#define  SDIO_CMD_WAITPEND                   0x0200U            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDIO_CMD_CPSMEN                     0x0400U            /*!<Command path state machine (CPSM) Enable bit                   */
-#define  SDIO_CMD_SDIOSUSPEND                0x0800U            /*!<SD I/O suspend command                                         */
-#define  SDIO_CMD_ENCMDCOMPL                 0x1000U            /*!<Enable CMD completion                                          */
-#define  SDIO_CMD_NIEN                       0x2000U            /*!<Not Interrupt Enable */
-#define  SDIO_CMD_CEATACMD                   0x4000U            /*!<CE-ATA command       */
-
-/*****************  Bit definition for SDIO_RESPCMD register  *****************/
-#define  SDIO_RESPCMD_RESPCMD                0x3FU               /*!<Response command index */
-
-/******************  Bit definition for SDIO_RESP0 register  ******************/
-#define  SDIO_RESP0_CARDSTATUS0              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP1 register  ******************/
-#define  SDIO_RESP1_CARDSTATUS1              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP2 register  ******************/
-#define  SDIO_RESP2_CARDSTATUS2              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP3 register  ******************/
-#define  SDIO_RESP3_CARDSTATUS3              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP4 register  ******************/
-#define  SDIO_RESP4_CARDSTATUS4              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_DTIMER register  *****************/
-#define  SDIO_DTIMER_DATATIME                0xFFFFFFFFU        /*!<Data timeout period. */
-
-/******************  Bit definition for SDIO_DLEN register  *******************/
-#define  SDIO_DLEN_DATALENGTH                0x01FFFFFFU        /*!<Data length value    */
-
-/******************  Bit definition for SDIO_DCTRL register  ******************/
-#define  SDIO_DCTRL_DTEN                     0x0001U            /*!<Data transfer enabled bit         */
-#define  SDIO_DCTRL_DTDIR                    0x0002U            /*!<Data transfer direction selection */
-#define  SDIO_DCTRL_DTMODE                   0x0004U            /*!<Data transfer mode selection      */
-#define  SDIO_DCTRL_DMAEN                    0x0008U            /*!<DMA enabled bit                   */
-
-#define  SDIO_DCTRL_DBLOCKSIZE               0x00F0U            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDIO_DCTRL_DBLOCKSIZE_0             0x0010U            /*!<Bit 0 */
-#define  SDIO_DCTRL_DBLOCKSIZE_1             0x0020U            /*!<Bit 1 */
-#define  SDIO_DCTRL_DBLOCKSIZE_2             0x0040U            /*!<Bit 2 */
-#define  SDIO_DCTRL_DBLOCKSIZE_3             0x0080U            /*!<Bit 3 */
-
-#define  SDIO_DCTRL_RWSTART                  0x0100U            /*!<Read wait start         */
-#define  SDIO_DCTRL_RWSTOP                   0x0200U            /*!<Read wait stop          */
-#define  SDIO_DCTRL_RWMOD                    0x0400U            /*!<Read wait mode          */
-#define  SDIO_DCTRL_SDIOEN                   0x0800U            /*!<SD I/O enable functions */
-
-/******************  Bit definition for SDIO_DCOUNT register  *****************/
-#define  SDIO_DCOUNT_DATACOUNT               0x01FFFFFFU        /*!<Data count value */
-
-/******************  Bit definition for SDIO_STA register  ********************/
-#define  SDIO_STA_CCRCFAIL                   0x00000001U        /*!<Command response received (CRC check failed)  */
-#define  SDIO_STA_DCRCFAIL                   0x00000002U        /*!<Data block sent/received (CRC check failed)   */
-#define  SDIO_STA_CTIMEOUT                   0x00000004U        /*!<Command response timeout                      */
-#define  SDIO_STA_DTIMEOUT                   0x00000008U        /*!<Data timeout                                  */
-#define  SDIO_STA_TXUNDERR                   0x00000010U        /*!<Transmit FIFO underrun error                  */
-#define  SDIO_STA_RXOVERR                    0x00000020U        /*!<Received FIFO overrun error                   */
-#define  SDIO_STA_CMDREND                    0x00000040U        /*!<Command response received (CRC check passed)  */
-#define  SDIO_STA_CMDSENT                    0x00000080U        /*!<Command sent (no response required)           */
-#define  SDIO_STA_DATAEND                    0x00000100U        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
-#define  SDIO_STA_STBITERR                   0x00000200U        /*!<Start bit not detected on all data signals in wide bus mode */
-#define  SDIO_STA_DBCKEND                    0x00000400U        /*!<Data block sent/received (CRC check passed)   */
-#define  SDIO_STA_CMDACT                     0x00000800U        /*!<Command transfer in progress                  */
-#define  SDIO_STA_TXACT                      0x00001000U        /*!<Data transmit in progress                     */
-#define  SDIO_STA_RXACT                      0x00002000U        /*!<Data receive in progress                      */
-#define  SDIO_STA_TXFIFOHE                   0x00004000U        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDIO_STA_RXFIFOHF                   0x00008000U        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDIO_STA_TXFIFOF                    0x00010000U        /*!<Transmit FIFO full                            */
-#define  SDIO_STA_RXFIFOF                    0x00020000U        /*!<Receive FIFO full                             */
-#define  SDIO_STA_TXFIFOE                    0x00040000U        /*!<Transmit FIFO empty                           */
-#define  SDIO_STA_RXFIFOE                    0x00080000U        /*!<Receive FIFO empty                            */
-#define  SDIO_STA_TXDAVL                     0x00100000U        /*!<Data available in transmit FIFO               */
-#define  SDIO_STA_RXDAVL                     0x00200000U        /*!<Data available in receive FIFO                */
-#define  SDIO_STA_SDIOIT                     0x00400000U        /*!<SDIO interrupt received                       */
-#define  SDIO_STA_CEATAEND                   0x00800000U        /*!<CE-ATA command completion signal received for CMD61 */
-
-/*******************  Bit definition for SDIO_ICR register  *******************/
-#define  SDIO_ICR_CCRCFAILC                  0x00000001U        /*!<CCRCFAIL flag clear bit */
-#define  SDIO_ICR_DCRCFAILC                  0x00000002U        /*!<DCRCFAIL flag clear bit */
-#define  SDIO_ICR_CTIMEOUTC                  0x00000004U        /*!<CTIMEOUT flag clear bit */
-#define  SDIO_ICR_DTIMEOUTC                  0x00000008U        /*!<DTIMEOUT flag clear bit */
-#define  SDIO_ICR_TXUNDERRC                  0x00000010U        /*!<TXUNDERR flag clear bit */
-#define  SDIO_ICR_RXOVERRC                   0x00000020U        /*!<RXOVERR flag clear bit  */
-#define  SDIO_ICR_CMDRENDC                   0x00000040U        /*!<CMDREND flag clear bit  */
-#define  SDIO_ICR_CMDSENTC                   0x00000080U        /*!<CMDSENT flag clear bit  */
-#define  SDIO_ICR_DATAENDC                   0x00000100U        /*!<DATAEND flag clear bit  */
-#define  SDIO_ICR_STBITERRC                  0x00000200U        /*!<STBITERR flag clear bit */
-#define  SDIO_ICR_DBCKENDC                   0x00000400U        /*!<DBCKEND flag clear bit  */
-#define  SDIO_ICR_SDIOITC                    0x00400000U        /*!<SDIOIT flag clear bit   */
-#define  SDIO_ICR_CEATAENDC                  0x00800000U        /*!<CEATAEND flag clear bit */
-
-/******************  Bit definition for SDIO_MASK register  *******************/
-#define  SDIO_MASK_CCRCFAILIE                0x00000001U        /*!<Command CRC Fail Interrupt Enable          */
-#define  SDIO_MASK_DCRCFAILIE                0x00000002U        /*!<Data CRC Fail Interrupt Enable             */
-#define  SDIO_MASK_CTIMEOUTIE                0x00000004U        /*!<Command TimeOut Interrupt Enable           */
-#define  SDIO_MASK_DTIMEOUTIE                0x00000008U        /*!<Data TimeOut Interrupt Enable              */
-#define  SDIO_MASK_TXUNDERRIE                0x00000010U        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
-#define  SDIO_MASK_RXOVERRIE                 0x00000020U        /*!<Rx FIFO OverRun Error Interrupt Enable     */
-#define  SDIO_MASK_CMDRENDIE                 0x00000040U        /*!<Command Response Received Interrupt Enable */
-#define  SDIO_MASK_CMDSENTIE                 0x00000080U        /*!<Command Sent Interrupt Enable              */
-#define  SDIO_MASK_DATAENDIE                 0x00000100U        /*!<Data End Interrupt Enable                  */
-#define  SDIO_MASK_STBITERRIE                0x00000200U        /*!<Start Bit Error Interrupt Enable           */
-#define  SDIO_MASK_DBCKENDIE                 0x00000400U        /*!<Data Block End Interrupt Enable            */
-#define  SDIO_MASK_CMDACTIE                  0x00000800U        /*!<CCommand Acting Interrupt Enable           */
-#define  SDIO_MASK_TXACTIE                   0x00001000U        /*!<Data Transmit Acting Interrupt Enable      */
-#define  SDIO_MASK_RXACTIE                   0x00002000U        /*!<Data receive acting interrupt enabled      */
-#define  SDIO_MASK_TXFIFOHEIE                0x00004000U        /*!<Tx FIFO Half Empty interrupt Enable        */
-#define  SDIO_MASK_RXFIFOHFIE                0x00008000U        /*!<Rx FIFO Half Full interrupt Enable         */
-#define  SDIO_MASK_TXFIFOFIE                 0x00010000U        /*!<Tx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_RXFIFOFIE                 0x00020000U        /*!<Rx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_TXFIFOEIE                 0x00040000U        /*!<Tx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_RXFIFOEIE                 0x00080000U        /*!<Rx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_TXDAVLIE                  0x00100000U        /*!<Data available in Tx FIFO interrupt Enable */
-#define  SDIO_MASK_RXDAVLIE                  0x00200000U        /*!<Data available in Rx FIFO interrupt Enable */
-#define  SDIO_MASK_SDIOITIE                  0x00400000U        /*!<SDIO Mode Interrupt Received interrupt Enable */
-#define  SDIO_MASK_CEATAENDIE                0x00800000U        /*!<CE-ATA command completion signal received Interrupt Enable */
-
-/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
-#define  SDIO_FIFOCNT_FIFOCOUNT              0x00FFFFFFU        /*!<Remaining number of words to be written to or read from the FIFO */
-
-/******************  Bit definition for SDIO_FIFO register  *******************/
-#define  SDIO_FIFO_FIFODATA                  0xFFFFFFFFU        /*!<Receive and transmit FIFO data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        0x00000001U            /*!<Clock Phase      */
-#define  SPI_CR1_CPOL                        0x00000002U            /*!<Clock Polarity   */
-#define  SPI_CR1_MSTR                        0x00000004U            /*!<Master Selection */
-
-#define  SPI_CR1_BR                          0x00000038U            /*!<BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        0x00000008U            /*!<Bit 0 */
-#define  SPI_CR1_BR_1                        0x00000010U            /*!<Bit 1 */
-#define  SPI_CR1_BR_2                        0x00000020U            /*!<Bit 2 */
-
-#define  SPI_CR1_SPE                         0x00000040U            /*!<SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    0x00000080U            /*!<Frame Format                        */
-#define  SPI_CR1_SSI                         0x00000100U            /*!<Internal slave select               */
-#define  SPI_CR1_SSM                         0x00000200U            /*!<Software slave management           */
-#define  SPI_CR1_RXONLY                      0x00000400U            /*!<Receive only                        */
-#define  SPI_CR1_DFF                         0x00000800U            /*!<Data Frame Format                   */
-#define  SPI_CR1_CRCNEXT                     0x00001000U            /*!<Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       0x00002000U            /*!<Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      0x00004000U            /*!<Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    0x00008000U            /*!<Bidirectional data mode enable      */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     0x00000001U               /*!<Rx Buffer DMA Enable                 */
-#define  SPI_CR2_TXDMAEN                     0x00000002U               /*!<Tx Buffer DMA Enable                 */
-#define  SPI_CR2_SSOE                        0x00000004U               /*!<SS Output Enable                     */
-#define  SPI_CR2_FRF                         0x00000010U               /*!<Frame Format                         */
-#define  SPI_CR2_ERRIE                       0x00000020U               /*!<Error Interrupt Enable               */
-#define  SPI_CR2_RXNEIE                      0x00000040U               /*!<RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       0x00000080U               /*!<Tx buffer Empty Interrupt Enable     */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         0x00000001U               /*!<Receive buffer Not Empty */
-#define  SPI_SR_TXE                          0x00000002U               /*!<Transmit buffer Empty    */
-#define  SPI_SR_CHSIDE                       0x00000004U               /*!<Channel side             */
-#define  SPI_SR_UDR                          0x00000008U               /*!<Underrun flag            */
-#define  SPI_SR_CRCERR                       0x00000010U               /*!<CRC Error flag           */
-#define  SPI_SR_MODF                         0x00000020U               /*!<Mode fault               */
-#define  SPI_SR_OVR                          0x00000040U               /*!<Overrun flag             */
-#define  SPI_SR_BSY                          0x00000080U               /*!<Busy flag                */
-#define  SPI_SR_FRE                          0x00000100U               /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           0x0000FFFFU            /*!<Data Register           */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   0x0000FFFFU            /*!<CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    0x0000FFFFU            /*!<Rx CRC Register         */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    0x0000FFFFU            /*!<Tx CRC Register         */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   0x00000001U            /*!<Channel length (number of bits per audio channel) */
-
-#define  SPI_I2SCFGR_DATLEN                  0x00000006U            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define  SPI_I2SCFGR_DATLEN_0                0x00000002U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                0x00000004U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_CKPOL                   0x00000008U            /*!<steady state clock polarity               */
-
-#define  SPI_I2SCFGR_I2SSTD                  0x00000030U            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U            /*!<PCM frame synchronization                 */
-
-#define  SPI_I2SCFGR_I2SCFG                  0x00000300U            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_I2SE                    0x00000400U            /*!<I2S Enable         */
-#define  SPI_I2SCFGR_I2SMOD                  0x00000800U            /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    0x000000FFU            /*!<I2S Linear prescaler         */
-#define  SPI_I2SPR_ODD                       0x00000100U            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     0x00000200U            /*!<Master Clock Output Enable   */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 SYSCFG                                     */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
-#define SYSCFG_MEMRMP_MEM_MODE          0x00000007U /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        0x00000001U
-#define SYSCFG_MEMRMP_MEM_MODE_1        0x00000002U
-#define SYSCFG_MEMRMP_MEM_MODE_2        0x00000004U
-
-/******************  Bit definition for SYSCFG_PMC register  ******************/
-#define SYSCFG_PMC_ADC1DC2              0x00010000U /*!< Refer to AN4073 on how to use this bit  */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
-/** 
-  * @brief   EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         0x0003U /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         0x0004U /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         0x0005U /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         0x0006U /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
-
-/** 
-  * @brief   EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         0x0030U /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         0x0040U /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         0x0050U /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         0x0060U /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
-
-/** 
-  * @brief   EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         0x0300U /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         0x0400U /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         0x0500U /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         0x0600U /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
-
-/** 
-  * @brief   EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         0x3000U /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         0x4000U /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         0x5000U /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         0x6000U /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
-/** 
-  * @brief   EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         0x0003U /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         0x0004U /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         0x0005U /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         0x0006U /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
-
-/** 
-  * @brief   EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         0x0030U /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         0x0040U /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         0x0050U /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         0x0060U /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
-
-/** 
-  * @brief   EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         0x0300U /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         0x0400U /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         0x0500U /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         0x0600U /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
-
-/** 
-  * @brief   EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         0x3000U /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         0x4000U /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         0x5000U /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         0x6000U /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
-
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
-
-/** 
-  * @brief   EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         0x0003U /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         0x0004U /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         0x0005U /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         0x0006U /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
-
-/** 
-  * @brief   EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         0x0030U /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         0x0040U /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         0x0050U /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         0x0060U /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
-
-/** 
-  * @brief   EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        0x0300U /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        0x0400U /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        0x0500U /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        0x0600U /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
-
-/** 
-  * @brief   EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        0x3000U /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        0x4000U /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        0x5000U /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        0x6000U /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
-/** 
-  * @brief   EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        0x0003U /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        0x0004U /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        0x0005U /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        0x0006U /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
-
-/** 
-  * @brief   EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        0x0030U /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        0x0040U /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        0x0050U /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        0x0060U /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
-
-/** 
-  * @brief   EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        0x0300U /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        0x0400U /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        0x0500U /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        0x0600U /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
-
-/** 
-  * @brief   EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        0x3000U /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        0x4000U /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        0x5000U /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        0x6000U /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
-
-/******************  Bit definition for SYSCFG_CMPCR register  ****************/
-#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell ready flag */
-#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell power-down */
-
-/******************  Bit definition for SYSCFG_CFGR register  *****************/
-#define SYSCFG_CFGR_FMPI2C1_SCL         0x00000001U /*!<FM+ drive capability for FMPI2C1_SCL pin */
-#define SYSCFG_CFGR_FMPI2C1_SDA         0x00000002U /*!<FM+ drive capability for FMPI2C1_SDA pin */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    TIM                                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
-#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
-#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
-#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
-#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
-
-#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
-
-#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
-
-#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        0x0001U            /*!<Capture/Compare Preloaded Control        */
-#define  TIM_CR2_CCUS                        0x0004U            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        0x0008U            /*!<Capture/Compare DMA Selection            */
-
-#define  TIM_CR2_MMS                         0x0070U            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
-#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
-#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
-#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        0x0007U            /*!<SMS[2:0] bits (Slave mode selection)    */
-#define  TIM_SMCR_SMS_0                      0x0001U            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      0x0002U            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      0x0004U            /*!<Bit 2 */
-
-#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
-#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
-
-#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
-
-#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
-
-#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
-#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
-#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
-#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
-#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
-#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
-#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
-#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
-#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
-#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
-#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
-#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
-#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
-#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
-#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
-#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
-#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
-#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
-#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          0x01U               /*!<Update Generation                         */
-#define  TIM_EGR_CC1G                        0x02U               /*!<Capture/Compare 1 Generation              */
-#define  TIM_EGR_CC2G                        0x04U               /*!<Capture/Compare 2 Generation              */
-#define  TIM_EGR_CC3G                        0x08U               /*!<Capture/Compare 3 Generation              */
-#define  TIM_EGR_CC4G                        0x10U               /*!<Capture/Compare 4 Generation              */
-#define  TIM_EGR_COMG                        0x20U               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          0x40U               /*!<Trigger Generation                        */
-#define  TIM_EGR_BG                          0x80U               /*!<Break Generation                          */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      0x0003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    0x0001U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    0x0002U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC1FE                     0x0004U            /*!<Output Compare 1 Fast enable                 */
-#define  TIM_CCMR1_OC1PE                     0x0008U            /*!<Output Compare 1 Preload enable              */
-
-#define  TIM_CCMR1_OC1M                      0x0070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define  TIM_CCMR1_OC1M_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    0x0040U            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC1CE                     0x0080U            /*!<Output Compare 1Clear Enable                 */
-
-#define  TIM_CCMR1_CC2S                      0x0300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    0x0100U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    0x0200U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC2FE                     0x0400U            /*!<Output Compare 2 Fast enable                 */
-#define  TIM_CCMR1_OC2PE                     0x0800U            /*!<Output Compare 2 Preload enable              */
-
-#define  TIM_CCMR1_OC2M                      0x7000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define  TIM_CCMR1_OC2M_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    0x4000U            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC2CE                     0x8000U            /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      0x0003U            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define  TIM_CCMR2_CC3S_0                    0x0001U            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    0x0002U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC3FE                     0x0004U            /*!<Output Compare 3 Fast enable           */
-#define  TIM_CCMR2_OC3PE                     0x0008U            /*!<Output Compare 3 Preload enable        */
-
-#define  TIM_CCMR2_OC3M                      0x0070U            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    0x0040U            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC3CE                     0x0080U            /*!<Output Compare 3 Clear Enable */
-
-#define  TIM_CCMR2_CC4S                      0x0300U            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    0x0100U            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    0x0200U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC4FE                     0x0400U            /*!<Output Compare 4 Fast enable    */
-#define  TIM_CCMR2_OC4PE                     0x0800U            /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR2_OC4M                      0x7000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    0x4000U            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       0x0001U            /*!<Capture/Compare 1 output enable                 */
-#define  TIM_CCER_CC1P                       0x0002U            /*!<Capture/Compare 1 output Polarity               */
-#define  TIM_CCER_CC1NE                      0x0004U            /*!<Capture/Compare 1 Complementary output enable   */
-#define  TIM_CCER_CC1NP                      0x0008U            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       0x0010U            /*!<Capture/Compare 2 output enable                 */
-#define  TIM_CCER_CC2P                       0x0020U            /*!<Capture/Compare 2 output Polarity               */
-#define  TIM_CCER_CC2NE                      0x0040U            /*!<Capture/Compare 2 Complementary output enable   */
-#define  TIM_CCER_CC2NP                      0x0080U            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       0x0100U            /*!<Capture/Compare 3 output enable                 */
-#define  TIM_CCER_CC3P                       0x0200U            /*!<Capture/Compare 3 output Polarity               */
-#define  TIM_CCER_CC3NE                      0x0400U            /*!<Capture/Compare 3 Complementary output enable   */
-#define  TIM_CCER_CC3NP                      0x0800U            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       0x1000U            /*!<Capture/Compare 4 output enable                 */
-#define  TIM_CCER_CC4P                       0x2000U            /*!<Capture/Compare 4 output Polarity               */
-#define  TIM_CCER_CC4NP                      0x8000U            /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         0xFFU               /*!<Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
-
-/*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        0x00FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      0x0001U            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      0x0002U            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      0x0004U            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      0x0008U            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      0x0010U            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      0x0020U            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      0x0040U            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      0x0080U            /*!<Bit 7 */
-
-#define  TIM_BDTR_LOCK                       0x0300U            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     0x0100U            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     0x0200U            /*!<Bit 1 */
-
-#define  TIM_BDTR_OSSI                       0x0400U            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       0x0800U            /*!<Off-State Selection for Run mode  */
-#define  TIM_BDTR_BKE                        0x1000U            /*!<Break enable                      */
-#define  TIM_BDTR_BKP                        0x2000U            /*!<Break Polarity                    */
-#define  TIM_BDTR_AOE                        0x4000U            /*!<Automatic Output enable           */
-#define  TIM_BDTR_MOE                        0x8000U            /*!<Main Output enable                */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
-
-#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
-#define TIM_OR_ITR1_RMP                      0x0C00U            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
-#define TIM_OR_ITR1_RMP_0                    0x0400U            /*!<Bit 0 */
-#define TIM_OR_ITR1_RMP_1                    0x0800U            /*!<Bit 1 */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*         Universal Synchronous Asynchronous Receiver Transmitter            */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         0x0001U            /*!<Parity Error                 */
-#define  USART_SR_FE                         0x0002U            /*!<Framing Error                */
-#define  USART_SR_NE                         0x0004U            /*!<Noise Error Flag             */
-#define  USART_SR_ORE                        0x0008U            /*!<OverRun Error                */
-#define  USART_SR_IDLE                       0x0010U            /*!<IDLE line detected           */
-#define  USART_SR_RXNE                       0x0020U            /*!<Read Data Register Not Empty */
-#define  USART_SR_TC                         0x0040U            /*!<Transmission Complete        */
-#define  USART_SR_TXE                        0x0080U            /*!<Transmit Data Register Empty */
-#define  USART_SR_LBD                        0x0100U            /*!<LIN Break Detection Flag     */
-#define  USART_SR_CTS                        0x0200U            /*!<CTS Flag                     */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         0x01FFU            /*!<Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_Fraction              0x000FU            /*!<Fraction of USARTDIV */
-#define  USART_BRR_DIV_Mantissa              0xFFF0U            /*!<Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       0x0001U            /*!<Send Break                             */
-#define  USART_CR1_RWU                       0x0002U            /*!<Receiver wakeup                        */
-#define  USART_CR1_RE                        0x0004U            /*!<Receiver Enable                        */
-#define  USART_CR1_TE                        0x0008U            /*!<Transmitter Enable                     */
-#define  USART_CR1_IDLEIE                    0x0010U            /*!<IDLE Interrupt Enable                  */
-#define  USART_CR1_RXNEIE                    0x0020U            /*!<RXNE Interrupt Enable                  */
-#define  USART_CR1_TCIE                      0x0040U            /*!<Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     0x0080U            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PEIE                      0x0100U            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PS                        0x0200U            /*!<Parity Selection                       */
-#define  USART_CR1_PCE                       0x0400U            /*!<Parity Control Enable                  */
-#define  USART_CR1_WAKE                      0x0800U            /*!<Wakeup method                          */
-#define  USART_CR1_M                         0x1000U            /*!<Word length                            */
-#define  USART_CR1_UE                        0x2000U            /*!<USART Enable                           */
-#define  USART_CR1_OVER8                     0x8000U            /*!<USART Oversampling by 8 enable         */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       0x000FU            /*!<Address of the USART node            */
-#define  USART_CR2_LBDL                      0x0020U            /*!<LIN Break Detection Length           */
-#define  USART_CR2_LBDIE                     0x0040U            /*!<LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      0x0100U            /*!<Last Bit Clock pulse                 */
-#define  USART_CR2_CPHA                      0x0200U            /*!<Clock Phase                          */
-#define  USART_CR2_CPOL                      0x0400U            /*!<Clock Polarity                       */
-#define  USART_CR2_CLKEN                     0x0800U            /*!<Clock Enable                         */
-
-#define  USART_CR2_STOP                      0x3000U            /*!<STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    0x1000U            /*!<Bit 0 */
-#define  USART_CR2_STOP_1                    0x2000U            /*!<Bit 1 */
-
-#define  USART_CR2_LINEN                     0x4000U            /*!<LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       0x0001U            /*!<Error Interrupt Enable      */
-#define  USART_CR3_IREN                      0x0002U            /*!<IrDA mode Enable            */
-#define  USART_CR3_IRLP                      0x0004U            /*!<IrDA Low-Power              */
-#define  USART_CR3_HDSEL                     0x0008U            /*!<Half-Duplex Selection       */
-#define  USART_CR3_NACK                      0x0010U            /*!<Smartcard NACK enable       */
-#define  USART_CR3_SCEN                      0x0020U            /*!<Smartcard mode enable       */
-#define  USART_CR3_DMAR                      0x0040U            /*!<DMA Enable Receiver         */
-#define  USART_CR3_DMAT                      0x0080U            /*!<DMA Enable Transmitter      */
-#define  USART_CR3_RTSE                      0x0100U            /*!<RTS Enable                  */
-#define  USART_CR3_CTSE                      0x0200U            /*!<CTS Enable                  */
-#define  USART_CR3_CTSIE                     0x0400U            /*!<CTS Interrupt Enable        */
-#define  USART_CR3_ONEBIT                    0x0800U            /*!<USART One bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      0x00FFU            /*!<PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    0x0001U            /*!<Bit 0 */
-#define  USART_GTPR_PSC_1                    0x0002U            /*!<Bit 1 */
-#define  USART_GTPR_PSC_2                    0x0004U            /*!<Bit 2 */
-#define  USART_GTPR_PSC_3                    0x0008U            /*!<Bit 3 */
-#define  USART_GTPR_PSC_4                    0x0010U            /*!<Bit 4 */
-#define  USART_GTPR_PSC_5                    0x0020U            /*!<Bit 5 */
-#define  USART_GTPR_PSC_6                    0x0040U            /*!<Bit 6 */
-#define  USART_GTPR_PSC_7                    0x0080U            /*!<Bit 7 */
-
-#define  USART_GTPR_GT                       0xFF00U            /*!<Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Window WATCHDOG                                 */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           0x7FU               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T_0                         0x01U               /*!<Bit 0 */
-#define  WWDG_CR_T_1                         0x02U               /*!<Bit 1 */
-#define  WWDG_CR_T_2                         0x04U               /*!<Bit 2 */
-#define  WWDG_CR_T_3                         0x08U               /*!<Bit 3 */
-#define  WWDG_CR_T_4                         0x10U               /*!<Bit 4 */
-#define  WWDG_CR_T_5                         0x20U               /*!<Bit 5 */
-#define  WWDG_CR_T_6                         0x40U               /*!<Bit 6 */
-/* Legacy defines */
-#define  WWDG_CR_T0                          WWDG_CR_T_0
-#define  WWDG_CR_T1                          WWDG_CR_T_1
-#define  WWDG_CR_T2                          WWDG_CR_T_2
-#define  WWDG_CR_T3                          WWDG_CR_T_3
-#define  WWDG_CR_T4                          WWDG_CR_T_4
-#define  WWDG_CR_T5                          WWDG_CR_T_5
-#define  WWDG_CR_T6                          WWDG_CR_T_6
-
-#define  WWDG_CR_WDGA                        0x80U               /*!<Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          0x007FU            /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W_0                        0x0001U            /*!<Bit 0 */
-#define  WWDG_CFR_W_1                        0x0002U            /*!<Bit 1 */
-#define  WWDG_CFR_W_2                        0x0004U            /*!<Bit 2 */
-#define  WWDG_CFR_W_3                        0x0008U            /*!<Bit 3 */
-#define  WWDG_CFR_W_4                        0x0010U            /*!<Bit 4 */
-#define  WWDG_CFR_W_5                        0x0020U            /*!<Bit 5 */
-#define  WWDG_CFR_W_6                        0x0040U            /*!<Bit 6 */
-/* Legacy defines */
-#define  WWDG_CFR_W0                         WWDG_CFR_W_0
-#define  WWDG_CFR_W1                         WWDG_CFR_W_1
-#define  WWDG_CFR_W2                         WWDG_CFR_W_2
-#define  WWDG_CFR_W3                         WWDG_CFR_W_3
-#define  WWDG_CFR_W4                         WWDG_CFR_W_4
-#define  WWDG_CFR_W5                         WWDG_CFR_W_5
-#define  WWDG_CFR_W6                         WWDG_CFR_W_6
-
-#define  WWDG_CFR_WDGTB                      0x0180U            /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB_0                    0x0080U            /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB_1                    0x0100U            /*!<Bit 1 */
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
-
-#define  WWDG_CFR_EWI                        0x0200U            /*!<Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        0x01U               /*!<Early Wakeup Interrupt Flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                DBG                                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
-#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
-
-/********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
-#define  DBGMCU_CR_DBG_STOP                  0x00000002U
-#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
-#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
-
-#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
-#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U/*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U/*!<Bit 1 */
-
-/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            0x00000001U
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            0x00000002U
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            0x00000004U
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            0x00000020U
-#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           0x00000040U
-#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           0x00000080U
-#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           0x00000100U
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
-#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
-
-/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        0x00000001U
-#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        0x00000002U
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        0x00010000U
-#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       0x00020000U
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       0x00040000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                                       USB_OTG			                        */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for USB_OTG_GOTGCTL register  ***********/
-#define USB_OTG_GOTGCTL_SRQSCS                  0x00000001U         /*!< Session request success */
-#define USB_OTG_GOTGCTL_SRQ                     0x00000002U         /*!< Session request */
-#define USB_OTG_GOTGCTL_VBVALOEN                0x00000004U         /*!< VBUS valid override enable */
-#define USB_OTG_GOTGCTL_VBVALOVAL               0x00000008U         /*!< VBUS valid override value */
-#define USB_OTG_GOTGCTL_AVALOEN                 0x00000010U         /*!< A-peripheral session valid override enable */
-#define USB_OTG_GOTGCTL_AVALOVAL                0x00000020U         /*!< A-peripheral session valid override value */
-#define USB_OTG_GOTGCTL_BVALOEN                 0x00000040U         /*!< B-peripheral session valid override enable */
-#define USB_OTG_GOTGCTL_BVALOVAL                0x00000080U         /*!< B-peripheral session valid override value  */
-#define USB_OTG_GOTGCTL_HNGSCS                  0x00000100U         /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_HNPRQ                   0x00000200U         /*!< HNP request */
-#define USB_OTG_GOTGCTL_HSHNPEN                 0x00000400U         /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_DHNPEN                  0x00000800U         /*!< Device HNP enabled */
-#define USB_OTG_GOTGCTL_EHEN                    0x00001000U         /*!< Embedded host enable */
-#define USB_OTG_GOTGCTL_CIDSTS                  0x00010000U         /*!< Connector ID status */
-#define USB_OTG_GOTGCTL_DBCT                    0x00020000U         /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD                   0x00040000U         /*!< A-session valid  */
-#define USB_OTG_GOTGCTL_BSESVLD                 0x00080000U         /*!< B-session valid */
-#define USB_OTG_GOTGCTL_OTGVER                  0x00100000U         /*!< OTG version  */
-
-/********************  Bit definition for USB_OTG_HCFG register  **************/
-
-#define USB_OTG_HCFG_FSLSPCS                 0x00000003U            /*!< FS/LS PHY clock select */
-#define USB_OTG_HCFG_FSLSPCS_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCFG_FSLSPCS_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCFG_FSLSS                   0x00000004U            /*!< FS- and LS-only support */
-
-/********************  Bit definition for USB_OTG_DCFG register  **************/
-
-#define USB_OTG_DCFG_DSPD                    0x00000003U            /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                  0x00000001U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DSPD_1                  0x00000002U            /*!<Bit 1 */
-#define USB_OTG_DCFG_NZLSOHSK                0x00000004U            /*!< Nonzero-length status OUT handshake */
-
-#define USB_OTG_DCFG_DAD                     0x000007F0U            /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                   0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DAD_1                   0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCFG_DAD_2                   0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCFG_DAD_3                   0x00000080U            /*!<Bit 3 */
-#define USB_OTG_DCFG_DAD_4                   0x00000100U            /*!<Bit 4 */
-#define USB_OTG_DCFG_DAD_5                   0x00000200U            /*!<Bit 5 */
-#define USB_OTG_DCFG_DAD_6                   0x00000400U            /*!<Bit 6 */
-
-#define USB_OTG_DCFG_PFIVL                   0x00001800U            /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PFIVL_1                 0x00001000U            /*!<Bit 1 */
-
-#define USB_OTG_DCFG_PERSCHIVL               0x03000000U            /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0             0x01000000U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PERSCHIVL_1             0x02000000U            /*!<Bit 1 */
-
-/********************  Bit definition for USB_OTG_PCGCR register  *************/
-#define USB_OTG_PCGCR_STPPCLK                 0x00000001U            /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK                0x00000002U            /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP                 0x00000010U            /*!< PHY suspended */
-
-/********************  Bit definition for USB_OTG_GOTGINT register  ***********/
-#define USB_OTG_GOTGINT_SEDET                   0x00000004U            /*!< Session end detected */
-#define USB_OTG_GOTGINT_SRSSCHG                 0x00000100U            /*!< Session request success status change */
-#define USB_OTG_GOTGINT_HNSSCHG                 0x00000200U            /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET                  0x00020000U            /*!< Host negotiation detected */
-#define USB_OTG_GOTGINT_ADTOCHG                 0x00040000U            /*!< A-device timeout change */
-#define USB_OTG_GOTGINT_DBCDNE                  0x00080000U            /*!< Debounce done */
-#define USB_OTG_GOTGINT_IDCHNG                  0x00100000U            /*!< Change in ID pin input value           */
-
-/********************  Bit definition for USB_OTG_DCTL register  **************/
-#define USB_OTG_DCTL_RWUSIG                  0x00000001U            /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS                    0x00000002U            /*!< Soft disconnect */
-#define USB_OTG_DCTL_GINSTS                  0x00000004U            /*!< Global IN NAK status */
-#define USB_OTG_DCTL_GONSTS                  0x00000008U            /*!< Global OUT NAK status */
-#define USB_OTG_DCTL_TCTL                    0x00000070U            /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                  0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCTL_TCTL_1                  0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCTL_TCTL_2                  0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCTL_SGINAK                  0x00000080U            /*!< Set global IN NAK */
-#define USB_OTG_DCTL_CGINAK                  0x00000100U            /*!< Clear global IN NAK */
-#define USB_OTG_DCTL_SGONAK                  0x00000200U            /*!< Set global OUT NAK */
-#define USB_OTG_DCTL_CGONAK                  0x00000400U            /*!< Clear global OUT NAK */
-#define USB_OTG_DCTL_POPRGDNE                0x00000800U            /*!< Power-on programming done */
-
-/********************  Bit definition for USB_OTG_HFIR register  **************/
-#define USB_OTG_HFIR_FRIVL                   0x0000FFFFU            /*!< Frame interval */
-
-/********************  Bit definition for USB_OTG_HFNUM register  *************/
-#define USB_OTG_HFNUM_FRNUM                   0x0000FFFFU            /*!< Frame number */
-#define USB_OTG_HFNUM_FTREM                   0xFFFF0000U            /*!< Frame time remaining */
-
-/********************  Bit definition for USB_OTG_DSTS register  **************/
-#define USB_OTG_DSTS_SUSPSTS                 0x00000001U            /*!< Suspend status */
-
-#define USB_OTG_DSTS_ENUMSPD                 0x00000006U            /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_DSTS_ENUMSPD_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_DSTS_EERR                    0x00000008U            /*!< Erratic error */
-#define USB_OTG_DSTS_FNSOF                   0x003FFF00U            /*!< Frame number of the received SOF */
-
-/********************  Bit definition for USB_OTG_GAHBCFG register  ***********/
-#define USB_OTG_GAHBCFG_GINT                    0x00000001U            /*!< Global interrupt mask */
-#define USB_OTG_GAHBCFG_HBSTLEN                 0x0000001EU            /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_GAHBCFG_HBSTLEN_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_GAHBCFG_HBSTLEN_2               0x00000008U            /*!<Bit 2 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3               0x00000010U            /*!<Bit 3 */
-#define USB_OTG_GAHBCFG_DMAEN                   0x00000020U            /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL                 0x00000080U            /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL                0x00000100U            /*!< Periodic TxFIFO empty level */
-
-/********************  Bit definition for USB_OTG_GUSBCFG register  ***********/
-#define USB_OTG_GUSBCFG_TOCAL                   0x00000007U            /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TOCAL_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TOCAL_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_PHYSEL                  0x00000040U            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP                  0x00000100U            /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP                  0x00000200U            /*!< HNP-capable */
-
-#define USB_OTG_GUSBCFG_TRDT                    0x00003C00U            /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                  0x00000400U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TRDT_1                  0x00000800U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TRDT_2                  0x00001000U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_TRDT_3                  0x00002000U            /*!<Bit 3 */
-#define USB_OTG_GUSBCFG_PHYLPCS                 0x00008000U            /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS                0x00020000U            /*!< ULPI FS/LS select */
-#define USB_OTG_GUSBCFG_ULPIAR                  0x00040000U            /*!< ULPI Auto-resume */
-#define USB_OTG_GUSBCFG_ULPICSM                 0x00080000U            /*!< ULPI Clock SuspendM */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD              0x00100000U            /*!< ULPI External VBUS Drive */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI              0x00200000U            /*!< ULPI external VBUS indicator */
-#define USB_OTG_GUSBCFG_TSDPS                   0x00400000U            /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI                    0x00800000U            /*!< Indicator complement */
-#define USB_OTG_GUSBCFG_PTCI                    0x01000000U            /*!< Indicator pass through */
-#define USB_OTG_GUSBCFG_ULPIIPD                 0x02000000U            /*!< ULPI interface protect disable */
-#define USB_OTG_GUSBCFG_FHMOD                   0x20000000U            /*!< Forced host mode */
-#define USB_OTG_GUSBCFG_FDMOD                   0x40000000U            /*!< Forced peripheral mode */
-#define USB_OTG_GUSBCFG_CTXPKT                  0x80000000U            /*!< Corrupt Tx packet */
-
-/********************  Bit definition for USB_OTG_GRSTCTL register  ***********/
-#define USB_OTG_GRSTCTL_CSRST                   0x00000001U            /*!< Core soft reset */
-#define USB_OTG_GRSTCTL_HSRST                   0x00000002U            /*!< HCLK soft reset */
-#define USB_OTG_GRSTCTL_FCRST                   0x00000004U            /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH                 0x00000010U            /*!< RxFIFO flush */
-#define USB_OTG_GRSTCTL_TXFFLSH                 0x00000020U            /*!< TxFIFO flush */
-
-#define USB_OTG_GRSTCTL_TXFNUM                  0x000007C0U            /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                0x00000040U            /*!<Bit 0 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                0x00000080U            /*!<Bit 1 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                0x00000100U            /*!<Bit 2 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                0x00000200U            /*!<Bit 3 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                0x00000400U            /*!<Bit 4 */
-#define USB_OTG_GRSTCTL_DMAREQ                  0x40000000U            /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL                  0x80000000U            /*!< AHB master idle */
-
-/********************  Bit definition for USB_OTG_DIEPMSK register  ***********/
-#define USB_OTG_DIEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPMSK_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPMSK_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPMSK_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPMSK_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPMSK_BIM                     0x00000200U            /*!< BNA interrupt mask */
-
-/********************  Bit definition for USB_OTG_HPTXSTS register  ***********/
-#define USB_OTG_HPTXSTS_PTXFSAVL                0x0000FFFFU            /*!< Periodic transmit data FIFO space available */
-
-#define USB_OTG_HPTXSTS_PTXQSAV                 0x00FF0000U            /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0               0x00010000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1               0x00020000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2               0x00040000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3               0x00080000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4               0x00100000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5               0x00200000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6               0x00400000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7               0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_HPTXSTS_PTXQTOP                 0xFF000000U            /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0               0x01000000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1               0x02000000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2               0x04000000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3               0x08000000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4               0x10000000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5               0x20000000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6               0x40000000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7               0x80000000U            /*!<Bit 7 */
-
-/********************  Bit definition for USB_OTG_HAINT register  *************/
-#define USB_OTG_HAINT_HAINT                   0x0000FFFFU            /*!< Channel interrupts */
-
-/********************  Bit definition for USB_OTG_DOEPMSK register  ***********/
-#define USB_OTG_DOEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPMSK_STUPM                   0x00000008U            /*!< SETUP phase done mask */
-#define USB_OTG_DOEPMSK_OTEPDM                  0x00000010U            /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_OTEPSPRM                0x00000020U            /*!< Status Phase Received mask                     */
-#define USB_OTG_DOEPMSK_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received mask */
-#define USB_OTG_DOEPMSK_OPEM                    0x00000100U            /*!< OUT packet error mask */
-#define USB_OTG_DOEPMSK_BOIM                    0x00000200U            /*!< BNA interrupt mask */
-
-/********************  Bit definition for USB_OTG_GINTSTS register  ***********/
-#define USB_OTG_GINTSTS_CMOD                    0x00000001U            /*!< Current mode of operation                      */
-#define USB_OTG_GINTSTS_MMIS                    0x00000002U            /*!< Mode mismatch interrupt                        */
-#define USB_OTG_GINTSTS_OTGINT                  0x00000004U            /*!< OTG interrupt                                  */
-#define USB_OTG_GINTSTS_SOF                     0x00000008U            /*!< Start of frame                                 */
-#define USB_OTG_GINTSTS_RXFLVL                  0x00000010U            /*!< RxFIFO nonempty                                */
-#define USB_OTG_GINTSTS_NPTXFE                  0x00000020U            /*!< Nonperiodic TxFIFO empty                       */
-#define USB_OTG_GINTSTS_GINAKEFF                0x00000040U            /*!< Global IN nonperiodic NAK effective            */
-#define USB_OTG_GINTSTS_BOUTNAKEFF              0x00000080U            /*!< Global OUT NAK effective                       */
-#define USB_OTG_GINTSTS_ESUSP                   0x00000400U            /*!< Early suspend                                  */
-#define USB_OTG_GINTSTS_USBSUSP                 0x00000800U            /*!< USB suspend                                    */
-#define USB_OTG_GINTSTS_USBRST                  0x00001000U            /*!< USB reset                                      */
-#define USB_OTG_GINTSTS_ENUMDNE                 0x00002000U            /*!< Enumeration done                               */
-#define USB_OTG_GINTSTS_ISOODRP                 0x00004000U            /*!< Isochronous OUT packet dropped interrupt       */
-#define USB_OTG_GINTSTS_EOPF                    0x00008000U            /*!< End of periodic frame interrupt                */
-#define USB_OTG_GINTSTS_IEPINT                  0x00040000U            /*!< IN endpoint interrupt                          */
-#define USB_OTG_GINTSTS_OEPINT                  0x00080000U            /*!< OUT endpoint interrupt                         */
-#define USB_OTG_GINTSTS_IISOIXFR                0x00100000U            /*!< Incomplete isochronous IN transfer             */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       0x00200000U            /*!< Incomplete periodic transfer                   */
-#define USB_OTG_GINTSTS_DATAFSUSP               0x00400000U            /*!< Data fetch suspended                           */
-#define USB_OTG_GINTSTS_RSTDET                  0x00800000U            /*!< Reset detected interrupt                       */
-#define USB_OTG_GINTSTS_HPRTINT                 0x01000000U            /*!< Host port interrupt                            */
-#define USB_OTG_GINTSTS_HCINT                   0x02000000U            /*!< Host channels interrupt                        */
-#define USB_OTG_GINTSTS_PTXFE                   0x04000000U            /*!< Periodic TxFIFO empty                          */
-#define USB_OTG_GINTSTS_LPMINT                  0x08000000U            /*!< LPM interrupt                                  */
-#define USB_OTG_GINTSTS_CIDSCHG                 0x10000000U            /*!< Connector ID status change                     */
-#define USB_OTG_GINTSTS_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt                  */
-#define USB_OTG_GINTSTS_SRQINT                  0x40000000U            /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT                  0x80000000U            /*!< Resume/remote wakeup detected interrupt        */
-
-/********************  Bit definition for USB_OTG_GINTMSK register  ***********/
-#define USB_OTG_GINTMSK_MMISM                   0x00000002U         /*!< Mode mismatch interrupt mask */
-#define USB_OTG_GINTMSK_OTGINT                  0x00000004U         /*!< OTG interrupt mask */
-#define USB_OTG_GINTMSK_SOFM                    0x00000008U         /*!< Start of frame mask */
-#define USB_OTG_GINTMSK_RXFLVLM                 0x00000010U         /*!< Receive FIFO nonempty mask */
-#define USB_OTG_GINTMSK_NPTXFEM                 0x00000020U         /*!< Nonperiodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_GINAKEFFM               0x00000040U         /*!< Global nonperiodic IN NAK effective mask */
-#define USB_OTG_GINTMSK_GONAKEFFM               0x00000080U         /*!< Global OUT NAK effective mask */
-#define USB_OTG_GINTMSK_ESUSPM                  0x00000400U         /*!< Early suspend mask */
-#define USB_OTG_GINTMSK_USBSUSPM                0x00000800U         /*!< USB suspend mask */
-#define USB_OTG_GINTMSK_USBRST                  0x00001000U         /*!< USB reset mask */
-#define USB_OTG_GINTMSK_ENUMDNEM                0x00002000U         /*!< Enumeration done mask */
-#define USB_OTG_GINTMSK_ISOODRPM                0x00004000U         /*!< Isochronous OUT packet dropped interrupt mask */
-#define USB_OTG_GINTMSK_EOPFM                   0x00008000U         /*!< End of periodic frame interrupt mask */
-#define USB_OTG_GINTMSK_EPMISM                  0x00020000U         /*!< Endpoint mismatch interrupt mask */
-#define USB_OTG_GINTMSK_IEPINT                  0x00040000U         /*!< IN endpoints interrupt mask */
-#define USB_OTG_GINTMSK_OEPINT                  0x00080000U         /*!< OUT endpoints interrupt mask */
-#define USB_OTG_GINTMSK_IISOIXFRM               0x00100000U         /*!< Incomplete isochronous IN transfer mask */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         0x00200000U         /*!< Incomplete periodic transfer mask */
-#define USB_OTG_GINTMSK_FSUSPM                  0x00400000U         /*!< Data fetch suspended mask */
-#define USB_OTG_GINTMSK_RSTDETM                 0x00800000U         /*!< Reset detected interrupt mask */
-#define USB_OTG_GINTMSK_PRTIM                   0x01000000U         /*!< Host port interrupt mask */
-#define USB_OTG_GINTMSK_HCIM                    0x02000000U         /*!< Host channels interrupt mask */
-#define USB_OTG_GINTMSK_PTXFEM                  0x04000000U         /*!< Periodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_LPMINTM                 0x08000000U         /*!< LPM interrupt Mask */
-#define USB_OTG_GINTMSK_CIDSCHGM                0x10000000U         /*!< Connector ID status change mask */
-#define USB_OTG_GINTMSK_DISCINT                 0x20000000U         /*!< Disconnect detected interrupt mask */
-#define USB_OTG_GINTMSK_SRQIM                   0x40000000U         /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM                    0x80000000U         /*!< Resume/remote wakeup detected interrupt mask */
-
-/********************  Bit definition for USB_OTG_DAINT register  *************/
-#define USB_OTG_DAINT_IEPINT                  0x0000FFFFU            /*!< IN endpoint interrupt bits */
-#define USB_OTG_DAINT_OEPINT                  0xFFFF0000U            /*!< OUT endpoint interrupt bits */
-
-/********************  Bit definition for USB_OTG_HAINTMSK register  **********/
-#define USB_OTG_HAINTMSK_HAINTM                  0x0000FFFFU            /*!< Channel interrupt mask */
-
-/********************  Bit definition for USB_OTG_GRXSTSP register  ***********/
-#define USB_OTG_GRXSTSP_EPNUM                    0x0000000FU            /*!< IN EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_BCNT                     0x00007FF0U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID                     0x00018000U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS                   0x001E0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for USB_OTG_DAINTMSK register  **********/
-#define USB_OTG_DAINTMSK_IEPM                    0x0000FFFFU            /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM                    0xFFFF0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for OTG register  ***********************/
-
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition for OTG register  ***********************/
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition for USB_OTG_GRXFSIZ register  ***********/
-#define USB_OTG_GRXFSIZ_RXFD            0x0000FFFFU            /*!< RxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DVBUSDIS register  **********/
-#define USB_OTG_DVBUSDIS_VBUSDT         0x0000FFFFU            /*!< Device VBUS discharge time */
-
-/********************  Bit definition for OTG register  ***********************/
-#define USB_OTG_NPTXFSA                 0x0000FFFFU            /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD                  0xFFFF0000U            /*!< Nonperiodic TxFIFO depth */
-#define USB_OTG_TX0FSA                  0x0000FFFFU            /*!< Endpoint 0 transmit RAM start address */
-#define USB_OTG_TX0FD                   0xFFFF0000U            /*!< Endpoint 0 TxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DVBUSPULSE register  ********/
-#define USB_OTG_DVBUSPULSE_DVBUSP                  0x00000FFFU            /*!< Device VBUS pulsing time */
-
-/********************  Bit definition for USB_OTG_GNPTXSTS register  **********/
-#define USB_OTG_GNPTXSTS_NPTXFSAV                0x0000FFFFU            /*!< Nonperiodic TxFIFO space available */
-
-#define USB_OTG_GNPTXSTS_NPTQXSAV                0x00FF0000U            /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0              0x00010000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1              0x00020000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2              0x00040000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3              0x00080000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4              0x00100000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5              0x00200000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6              0x00400000U            /*!<Bit 6 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7              0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_GNPTXSTS_NPTXQTOP                0x7F000000U            /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0              0x01000000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1              0x02000000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2              0x04000000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3              0x08000000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4              0x10000000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5              0x20000000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6              0x40000000U            /*!<Bit 6 */
-
-/********************  Bit definition for USB_OTG_DTHRCTL register  ***********/
-#define USB_OTG_DTHRCTL_NONISOTHREN             0x00000001U            /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN                0x00000002U            /*!< ISO IN endpoint threshold enable */
-
-#define USB_OTG_DTHRCTL_TXTHRLEN                0x000007FCU            /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0              0x00000004U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1              0x00000008U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2              0x00000010U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3              0x00000020U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4              0x00000040U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5              0x00000080U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6              0x00000100U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7              0x00000200U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8              0x00000400U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_RXTHREN                 0x00010000U            /*!< Receive threshold enable */
-
-#define USB_OTG_DTHRCTL_RXTHRLEN                0x03FE0000U            /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0              0x00020000U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1              0x00040000U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2              0x00080000U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3              0x00100000U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4              0x00200000U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5              0x00400000U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6              0x00800000U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7              0x01000000U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8              0x02000000U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_ARPEN                   0x08000000U            /*!< Arbiter parking enable */
-
-/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM               0x0000FFFFU            /*!< IN EP Tx FIFO empty interrupt mask bits */
-
-/********************  Bit definition for USB_OTG_DEACHINT register  **********/
-#define USB_OTG_DEACHINT_IEP1INT                 0x00000002U            /*!< IN endpoint 1interrupt bit */
-#define USB_OTG_DEACHINT_OEP1INT                 0x00020000U            /*!< OUT endpoint 1 interrupt bit */
-
-/********************  Bit definition for USB_OTG_GCCFG register  *************/
-#define USB_OTG_GCCFG_DCDET                  0x00000001U              /*!< Data contact detection (DCD) status */
-#define USB_OTG_GCCFG_PDET                   0x00000002U              /*!< Primary detection (PD) status */
-#define USB_OTG_GCCFG_SDET                   0x00000004U              /*!< Secondary detection (SD) status */
-#define USB_OTG_GCCFG_PS2DET                 0x00000008U              /*!< DM pull-up detection status */
-#define USB_OTG_GCCFG_PWRDWN                 0x00010000U              /*!< Power down */
-#define USB_OTG_GCCFG_BCDEN                  0x00020000U              /*!< Battery charging detector (BCD) enable */
-#define USB_OTG_GCCFG_DCDEN                  0x00040000U              /*!< Data contact detection (DCD) mode enable*/
-#define USB_OTG_GCCFG_PDEN                   0x00080000U              /*!< Primary detection (PD) mode enable*/
-#define USB_OTG_GCCFG_SDEN                   0x00100000U              /*!< Secondary detection (SD) mode enable */
-#define USB_OTG_GCCFG_VBDEN                  0x00200000U              /*!< USB VBUS Detection Enable */
-
-/********************  Bit definition for USB_OTG_DEACHINTMSK register  *******/
-#define USB_OTG_DEACHINTMSK_IEP1INTM                0x00000002U            /*!< IN Endpoint 1 interrupt mask bit */
-#define USB_OTG_DEACHINTMSK_OEP1INTM                0x00020000U            /*!< OUT Endpoint 1 interrupt mask bit */
-
-/********************  Bit definition for USB_OTG_CID register  ***************/
-#define USB_OTG_CID_PRODUCT_ID              0xFFFFFFFFU               /*!< Product ID field */
-
-/********************  Bit definition for USB_OTG_GLPMCFG register  ***********/
-#define  USB_OTG_GLPMCFG_LPMEN               0x00000001U            /*!< LPM support enable                                     */
-#define  USB_OTG_GLPMCFG_LPMACK              0x00000002U            /*!< LPM Token acknowledge enable                           */
-#define  USB_OTG_GLPMCFG_BESL                0x0000003CU            /*!< BESL value received with last ACKed LPM Token          */
-#define  USB_OTG_GLPMCFG_REMWAKE             0x00000040U            /*!< bRemoteWake value received with last ACKed LPM Token   */
-#define  USB_OTG_GLPMCFG_L1SSEN              0x00000080U            /*!< L1 shallow sleep enable                                */
-#define  USB_OTG_GLPMCFG_BESLTHRS            0x00000F00U            /*!< BESL threshold                                         */
-#define  USB_OTG_GLPMCFG_L1DSEN              0x00001000U            /*!< L1 deep sleep enable                                   */
-#define  USB_OTG_GLPMCFG_LPMRSP              0x00006000U            /*!< LPM response                                           */
-#define  USB_OTG_GLPMCFG_SLPSTS              0x00008000U            /*!< Port sleep status                                      */
-#define  USB_OTG_GLPMCFG_L1RSMOK             0x00010000U            /*!< Sleep State Resume OK                                  */
-#define  USB_OTG_GLPMCFG_LPMCHIDX            0x001E0000U            /*!< LPM Channel Index                                      */
-#define  USB_OTG_GLPMCFG_LPMRCNT             0x00E00000U            /*!< LPM retry count                                        */
-#define  USB_OTG_GLPMCFG_SNDLPM              0x01000000U            /*!< Send LPM transaction                                   */
-#define  USB_OTG_GLPMCFG_LPMRCNTSTS          0x0E000000U            /*!< LPM retry count status                                 */
-#define  USB_OTG_GLPMCFG_ENBESL              0x10000000U            /*!< Enable best effort service latency                     */
-
-/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ******/
-#define USB_OTG_DIEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPEACHMSK1_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
-
-/********************  Bit definition for USB_OTG_HPRT register  **************/
-#define USB_OTG_HPRT_PCSTS                   0x00000001U            /*!< Port connect status */
-#define USB_OTG_HPRT_PCDET                   0x00000002U            /*!< Port connect detected */
-#define USB_OTG_HPRT_PENA                    0x00000004U            /*!< Port enable */
-#define USB_OTG_HPRT_PENCHNG                 0x00000008U            /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA                    0x00000010U            /*!< Port overcurrent active */
-#define USB_OTG_HPRT_POCCHNG                 0x00000020U            /*!< Port overcurrent change */
-#define USB_OTG_HPRT_PRES                    0x00000040U            /*!< Port resume */
-#define USB_OTG_HPRT_PSUSP                   0x00000080U            /*!< Port suspend */
-#define USB_OTG_HPRT_PRST                    0x00000100U            /*!< Port reset */
-
-#define USB_OTG_HPRT_PLSTS                   0x00000C00U            /*!< Port line status */
-#define USB_OTG_HPRT_PLSTS_0                 0x00000400U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PLSTS_1                 0x00000800U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PPWR                    0x00001000U            /*!< Port power */
-
-#define USB_OTG_HPRT_PTCTL                   0x0001E000U            /*!< Port test control */
-#define USB_OTG_HPRT_PTCTL_0                 0x00002000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PTCTL_1                 0x00004000U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PTCTL_2                 0x00008000U            /*!<Bit 2 */
-#define USB_OTG_HPRT_PTCTL_3                 0x00010000U            /*!<Bit 3 */
-
-#define USB_OTG_HPRT_PSPD                    0x00060000U            /*!< Port speed */
-#define USB_OTG_HPRT_PSPD_0                  0x00020000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PSPD_1                  0x00040000U            /*!<Bit 1 */
-
-/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ******/
-#define USB_OTG_DOEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DOEPEACHMSK1_TXFURM                  0x00000100U            /*!< OUT packet error mask */
-#define USB_OTG_DOEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_BERRM                   0x00001000U            /*!< Bubble error interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NYETM                   0x00004000U            /*!< NYET interrupt mask */
-
-/********************  Bit definition for USB_OTG_HPTXFSIZ register  **********/
-#define USB_OTG_HPTXFSIZ_PTXSA                   0x0000FFFFU            /*!< Host periodic TxFIFO start address */
-#define USB_OTG_HPTXFSIZ_PTXFD                   0xFFFF0000U            /*!< Host periodic TxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DIEPCTL register  ***********/
-#define USB_OTG_DIEPCTL_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
-#define USB_OTG_DIEPCTL_USBAEP                  0x00008000U            /*!< USB active endpoint */
-#define USB_OTG_DIEPCTL_EONUM_DPID              0x00010000U            /*!< Even/odd frame */
-#define USB_OTG_DIEPCTL_NAKSTS                  0x00020000U            /*!< NAK status */
-
-#define USB_OTG_DIEPCTL_EPTYP                   0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_DIEPCTL_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_STALL                   0x00200000U            /*!< STALL handshake */
-
-#define USB_OTG_DIEPCTL_TXFNUM                  0x03C00000U            /*!< TxFIFO number */
-#define USB_OTG_DIEPCTL_TXFNUM_0                0x00400000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                0x00800000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                0x01000000U            /*!<Bit 2 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                0x02000000U            /*!<Bit 3 */
-#define USB_OTG_DIEPCTL_CNAK                    0x04000000U            /*!< Clear NAK */
-#define USB_OTG_DIEPCTL_SNAK                    0x08000000U            /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          0x10000000U            /*!< Set DATA0 PID */
-#define USB_OTG_DIEPCTL_SODDFRM                 0x20000000U            /*!< Set odd frame */
-#define USB_OTG_DIEPCTL_EPDIS                   0x40000000U            /*!< Endpoint disable */
-#define USB_OTG_DIEPCTL_EPENA                   0x80000000U            /*!< Endpoint enable */
-
-/********************  Bit definition for USB_OTG_HCCHAR register  ************/
-#define USB_OTG_HCCHAR_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
-
-#define USB_OTG_HCCHAR_EPNUM                   0x00007800U            /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPNUM_1                 0x00001000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_EPNUM_2                 0x00002000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_EPNUM_3                 0x00004000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_EPDIR                   0x00008000U            /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV                   0x00020000U            /*!< Low-speed device */
-
-#define USB_OTG_HCCHAR_EPTYP                   0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_MC                      0x00300000U            /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                    0x00100000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_MC_1                    0x00200000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_DAD                     0x1FC00000U            /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                   0x00400000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_DAD_1                   0x00800000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_DAD_2                   0x01000000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_DAD_3                   0x02000000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_DAD_4                   0x04000000U            /*!<Bit 4 */
-#define USB_OTG_HCCHAR_DAD_5                   0x08000000U            /*!<Bit 5 */
-#define USB_OTG_HCCHAR_DAD_6                   0x10000000U            /*!<Bit 6 */
-#define USB_OTG_HCCHAR_ODDFRM                  0x20000000U            /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS                   0x40000000U            /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA                   0x80000000U            /*!< Channel enable */
-
-/********************  Bit definition for USB_OTG_HCSPLT register  ************/
-
-#define USB_OTG_HCSPLT_PRTADDR                 0x0000007FU            /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_PRTADDR_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_PRTADDR_2               0x00000004U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_PRTADDR_3               0x00000008U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_PRTADDR_4               0x00000010U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_PRTADDR_5               0x00000020U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_PRTADDR_6               0x00000040U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_HUBADDR                 0x00003F80U            /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0               0x00000080U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_HUBADDR_1               0x00000100U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_HUBADDR_2               0x00000200U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_HUBADDR_3               0x00000400U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_HUBADDR_4               0x00000800U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_HUBADDR_5               0x00001000U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_HUBADDR_6               0x00002000U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_XACTPOS                 0x0000C000U            /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0               0x00004000U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_XACTPOS_1               0x00008000U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_COMPLSPLT               0x00010000U            /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN                 0x80000000U            /*!< Split enable */
-
-/********************  Bit definition for USB_OTG_HCINT register  *************/
-#define USB_OTG_HCINT_XFRC                    0x00000001U            /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH                     0x00000002U            /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINT_STALL                   0x00000008U            /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK                     0x00000010U            /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK                     0x00000020U            /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET                    0x00000040U            /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR                   0x00000080U            /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR                   0x00000100U            /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR                   0x00000200U            /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR                   0x00000400U            /*!< Data toggle error */
-
-/********************  Bit definition for USB_OTG_DIEPINT register  ***********/
-#define USB_OTG_DIEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_TOC                     0x00000008U            /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE                  0x00000010U            /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNE                  0x00000040U            /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE                    0x00000080U            /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN              0x00000100U            /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA                     0x00000200U            /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS               0x00000800U            /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR                    0x00001000U            /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK                     0x00002000U            /*!< NAK interrupt */
-
-/********************  Bit definition for USB_OTG_HCINTMSK register  **********/
-#define USB_OTG_HCINTMSK_XFRCM                   0x00000001U            /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM                    0x00000002U            /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM                  0x00000008U            /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM                    0x00000010U            /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM                    0x00000020U            /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET                    0x00000040U            /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM                  0x00000080U            /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM                  0x00000100U            /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM                  0x00000200U            /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM                  0x00000400U            /*!< Data toggle error mask */
-
-/********************  Bit definition for USB_OTG_DIEPTSIZ register  **********/
-
-#define USB_OTG_DIEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT                  0x60000000U            /*!< Packet count */
-/********************  Bit definition for USB_OTG_HCTSIZ register  ************/
-#define USB_OTG_HCTSIZ_XFRSIZ                    0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT                    0x1FF80000U            /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING                    0x80000000U            /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID                      0x60000000U            /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                    0x20000000U            /*!<Bit 0 */
-#define USB_OTG_HCTSIZ_DPID_1                    0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition for USB_OTG_DIEPDMA register  ***********/
-#define USB_OTG_DIEPDMA_DMAADDR                  0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition for USB_OTG_HCDMA register  *************/
-#define USB_OTG_HCDMA_DMAADDR                    0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition for USB_OTG_DTXFSTS register  ***********/
-#define USB_OTG_DTXFSTS_INEPTFSAV                0x0000FFFFU            /*!< IN endpoint TxFIFO space available */
-
-/********************  Bit definition for USB_OTG_DIEPTXF register  ***********/
-#define USB_OTG_DIEPTXF_INEPTXSA                 0x0000FFFFU            /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD                 0xFFFF0000U            /*!< IN endpoint TxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DOEPCTL register  ***********/
-
-#define USB_OTG_DOEPCTL_MPSIZ                     0x000007FFU            /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP                    0x00008000U            /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS                    0x00020000U            /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            0x10000000U            /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM                   0x20000000U            /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP                     0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                   0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DOEPCTL_EPTYP_1                   0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_SNPM                      0x00100000U            /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL                     0x00200000U            /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK                      0x04000000U            /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK                      0x08000000U            /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS                     0x40000000U            /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA                     0x80000000U            /*!< Endpoint enable */
-
-/********************  Bit definition for USB_OTG_DOEPINT register  ***********/
-#define USB_OTG_DOEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_STUP                    0x00000008U            /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS                 0x00000010U            /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_OTEPSPR                 0x00000020U            /*!< Status Phase Received For Control Write */
-#define USB_OTG_DOEPINT_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_NYET                    0x00004000U            /*!< NYET interrupt */
-
-/********************  Bit definition for USB_OTG_DOEPTSIZ register  **********/
-
-#define USB_OTG_DOEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-
-#define USB_OTG_DOEPTSIZ_STUPCNT                 0x60000000U            /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0               0x20000000U            /*!<Bit 0 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1               0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition for PCGCCTL register  *******************/
-#define USB_OTG_PCGCCTL_STOPCLK                 0x00000001U            /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK                 0x00000002U            /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP                 0x00000010U            /*!<Bit 1 */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
- 
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-
-/******************************* CAN Instances ********************************/
-#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
-                                       ((INSTANCE) == CAN2))
-/****************************** DFSDM Instances *******************************/
-#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
-                                                ((INSTANCE) == DFSDM1_Filter1))
-
-#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
-                                                 ((INSTANCE) == DFSDM1_Channel1) || \
-                                                 ((INSTANCE) == DFSDM1_Channel2) || \
-                                                 ((INSTANCE) == DFSDM1_Channel3))
-
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************** DMA Instances *******************************/
-#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
-                                              ((INSTANCE) == DMA1_Stream1) || \
-                                              ((INSTANCE) == DMA1_Stream2) || \
-                                              ((INSTANCE) == DMA1_Stream3) || \
-                                              ((INSTANCE) == DMA1_Stream4) || \
-                                              ((INSTANCE) == DMA1_Stream5) || \
-                                              ((INSTANCE) == DMA1_Stream6) || \
-                                              ((INSTANCE) == DMA1_Stream7) || \
-                                              ((INSTANCE) == DMA2_Stream0) || \
-                                              ((INSTANCE) == DMA2_Stream1) || \
-                                              ((INSTANCE) == DMA2_Stream2) || \
-                                              ((INSTANCE) == DMA2_Stream3) || \
-                                              ((INSTANCE) == DMA2_Stream4) || \
-                                              ((INSTANCE) == DMA2_Stream5) || \
-                                              ((INSTANCE) == DMA2_Stream6) || \
-                                              ((INSTANCE) == DMA2_Stream7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOF) || \
-                                        ((INSTANCE) == GPIOG) || \
-                                        ((INSTANCE) == GPIOH))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2) || \
-                                       ((INSTANCE) == I2C3))
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI1) || \
-                                    ((INSTANCE) == SPI2) || \
-                                    ((INSTANCE) == SPI3) || \
-                                    ((INSTANCE) == SPI4) || \
-                                    ((INSTANCE) == SPI5))
-
-/*************************** I2S Extended Instances ***************************/
-#define IS_I2S_ALL_INSTANCE_EXT(PERIPH)  (((INSTANCE) == SPI2)    || \
-                                          ((INSTANCE) == SPI3)    || \
-                                          ((INSTANCE) == I2S2ext) || \
-                                          ((INSTANCE) == I2S3ext))
-
-/******************************* RNG Instances ********************************/
-#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3) || \
-                                       ((INSTANCE) == SPI4) || \
-                                       ((INSTANCE) == SPI5))
-/*************************** SPI Extended Instances ***************************/
-#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1)    || \
-                                           ((INSTANCE) == SPI2)    || \
-                                           ((INSTANCE) == SPI3)    || \
-                                           ((INSTANCE) == SPI4)    || \
-                                           ((INSTANCE) == SPI5)    || \
-                                           ((INSTANCE) == I2S2ext) || \
-                                           ((INSTANCE) == I2S3ext))
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
-                                   ((INSTANCE) == TIM2)   || \
-                                   ((INSTANCE) == TIM3)   || \
-                                   ((INSTANCE) == TIM4)   || \
-                                   ((INSTANCE) == TIM5)   || \
-                                   ((INSTANCE) == TIM6)   || \
-                                   ((INSTANCE) == TIM7)   || \
-                                   ((INSTANCE) == TIM8)   || \
-                                   ((INSTANCE) == TIM9)   || \
-                                   ((INSTANCE) == TIM10)  || \
-                                   ((INSTANCE) == TIM11)  || \
-                                   ((INSTANCE) == TIM12)  || \
-                                   ((INSTANCE) == TIM13)  || \
-                                   ((INSTANCE) == TIM14))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
-                                         ((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM8)  || \
-                                         ((INSTANCE) == TIM9)  || \
-                                         ((INSTANCE) == TIM10) || \
-                                         ((INSTANCE) == TIM11) || \
-                                         ((INSTANCE) == TIM12) || \
-                                         ((INSTANCE) == TIM13) || \
-                                         ((INSTANCE) == TIM14))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM8) || \
-                                       ((INSTANCE) == TIM9) || \
-                                       ((INSTANCE) == TIM12))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8))
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM8))
-
-/******************** TIM Instances : Advanced-control timers *****************/
-#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                            ((INSTANCE) == TIM8))
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8))
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM6) || \
-                                       ((INSTANCE) == TIM7) || \
-                                       ((INSTANCE) == TIM8))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM8))
-
-/************ TIM Instances : DMA requests generation (COMDE) *****************/
-#define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM8)) 
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                             ((INSTANCE) == TIM2) || \
-                                             ((INSTANCE) == TIM3) || \
-                                             ((INSTANCE) == TIM4) || \
-                                             ((INSTANCE) == TIM5) || \
-                                             ((INSTANCE) == TIM8))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM6) || \
-                                          ((INSTANCE) == TIM7) || \
-                                          ((INSTANCE) == TIM8) || \
-                                          ((INSTANCE) == TIM9) || \
-                                          ((INSTANCE) == TIM12))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8) || \
-                                         ((INSTANCE) == TIM9) || \
-                                         ((INSTANCE) == TIM12))
-
-/********************** TIM Instances : 32 bit Counter ************************/
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
-                                              ((INSTANCE) == TIM5))
-
-/***************** TIM Instances : external trigger input available ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                        ((INSTANCE) == TIM2) || \
-                                        ((INSTANCE) == TIM3) || \
-                                        ((INSTANCE) == TIM4) || \
-                                        ((INSTANCE) == TIM5) || \
-                                        ((INSTANCE) == TIM8))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM11))
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM1) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM5) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM8) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM12) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM13) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM14) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-/************ TIM Instances : complementary output(s) available ***************/
-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
-   ((((INSTANCE) == TIM1) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3)))            \
-    ||                                          \
-    (((INSTANCE) == TIM8) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3))))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART6))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2))
-
-/********************* UART Instances : Smart card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART6))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART6))
-
-/*********************** PCD Instances ****************************************/
-#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
-
-/*********************** HCD Instances ****************************************/
-#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/***************************** FMPI2C Instances *******************************/
-#define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
-
-/****************************** SDIO Instances ********************************/
-#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
-
-/****************************** USB Instances ********************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
-
-/****************************** USB Exported Constants ************************/
-#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                12U
-#define USB_OTG_FS_MAX_IN_ENDPOINTS                    6U    /* Including EP0 */
-#define USB_OTG_FS_MAX_OUT_ENDPOINTS                   6U    /* Including EP0 */
-#define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32F412Cx_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/cmsis/stm32f412rx.h b/stmhal/cmsis/stm32f412rx.h
deleted file mode 100644
index edfb085e8e..0000000000
--- a/stmhal/cmsis/stm32f412rx.h
+++ /dev/null
@@ -1,7393 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f412rx.h
-  * @author  MCD Application Team
-  * @version V2.5.1
-  * @date    28-June-2016
-  * @brief   CMSIS STM32F412Rx Device Peripheral Access Layer Header File. 
-  *
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - peripherals registers declarations and bits definition
-  *           - Macros to access peripheral’s registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f412rx
-  * @{
-  */
-    
-#ifndef __STM32F412Rx_H
-#define __STM32F412Rx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-  
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-
-/**
-  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
-  */
-#define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */
-#define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */
-#define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1U       /*!< FPU present                                   */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32F4XX Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-typedef enum
-{
-/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
-  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
-/******  STM32 specific Interrupt Numbers **********************************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
-  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
-  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
-  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
-  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
-  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
-  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
-  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
-  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
-  ADC_IRQn                    = 18,     /*!< ADC1 global Interrupts                                            */
-  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
-  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
-  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
-  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
-  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
-  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
-  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
-  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */
-  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
-  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
-  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
-  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
-  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
-  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
-  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
-  TIM6_IRQn                   = 54,     /*!< TIM6 global interrupt                                             */
-  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
-  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
-  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
-  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
-  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
-  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
-  DFSDM1_FLT0_IRQn            = 61,     /*!< DFSDM1 Filter 0 global Interrupt                                  */
-  DFSDM1_FLT1_IRQn            = 62,     /*!< DFSDM1 Filter 1 global Interrupt                                  */
-  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
-  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
-  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
-  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
-  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
-  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
-  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
-  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
-  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
-  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
-  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
-  RNG_IRQn                    = 80,     /*!< RNG global Interrupt                                              */
-  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
-  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
-  SPI5_IRQn                   = 85,      /*!< SPI5 global Interrupt                                            */
-  QUADSPI_IRQn                = 92,     /*!< QuadSPI global Interrupt                                          */
-  FMPI2C1_EV_IRQn             = 95,     /*!< FMPI2C1 Event Interrupt                                           */
-  FMPI2C1_ER_IRQn             = 96      /*!< FMPI2C1 Error Interrupt                                           */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
-#include "system_stm32f4xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */
-  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
-  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
-  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
-  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
-  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
-  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
-  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
-  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
-  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
-  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
-  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
-  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
-  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
-  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
-  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
-                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief Controller Area Network TxMailBox 
-  */
-
-typedef struct
-{
-  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
-  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
-  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
-  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
-} CAN_TxMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FIFOMailBox 
-  */
-  
-typedef struct
-{
-  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
-  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
-  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
-  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
-} CAN_FIFOMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FilterRegister 
-  */
-  
-typedef struct
-{
-  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
-  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
-} CAN_FilterRegister_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
-  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
-  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
-  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
-  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
-  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
-  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
-  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
-  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
-  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
-  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
-  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
-  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
-  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
-  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
-  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
-  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
-  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
-  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
-  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
-  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */ 
-  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
-} CAN_TypeDef;
-
-/** 
-  * @brief CRC calculation unit 
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
-  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */
-  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
-  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
-  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
-}CRC_TypeDef;
-
-/**
-  * @brief DFSDM module registers
-  */
-typedef struct
-{
-  __IO uint32_t FLTCR1;      /*!< DFSDM control register1,                          Address offset: 0x100 */
-  __IO uint32_t FLTCR2;      /*!< DFSDM control register2,                          Address offset: 0x104 */
-  __IO uint32_t FLTISR;      /*!< DFSDM interrupt and status register,              Address offset: 0x108 */
-  __IO uint32_t FLTICR;      /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */
-  __IO uint32_t FLTJCHGR;    /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */
-  __IO uint32_t FLTFCR;      /*!< DFSDM filter control register,                    Address offset: 0x114 */
-  __IO uint32_t FLTJDATAR;   /*!< DFSDM data register for injected group,           Address offset: 0x118 */
-  __IO uint32_t FLTRDATAR;   /*!< DFSDM data register for regular group,            Address offset: 0x11C */
-  __IO uint32_t FLTAWHTR;    /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */
-  __IO uint32_t FLTAWLTR;    /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */
-  __IO uint32_t FLTAWSR;     /*!< DFSDM analog watchdog status register             Address offset: 0x128 */
-  __IO uint32_t FLTAWCFR;    /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */
-  __IO uint32_t FLTEXMAX;    /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */
-  __IO uint32_t FLTEXMIN;    /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */
-  __IO uint32_t FLTCNVTIMR;  /*!< DFSDM conversion timer,                           Address offset: 0x138 */
-} DFSDM_Filter_TypeDef;
-
-/**
-  * @brief DFSDM channel configuration registers
-  */
-typedef struct
-{
-  __IO uint32_t CHCFGR1;     /*!< DFSDM channel configuration register1,            Address offset: 0x00 */
-  __IO uint32_t CHCFGR2;     /*!< DFSDM channel configuration register2,            Address offset: 0x04 */
-  __IO uint32_t CHAWSCDR;    /*!< DFSDM channel analog watchdog and
-                                  short circuit detector register,                  Address offset: 0x08 */
-  __IO uint32_t CHWDATAR;    /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */
-  __IO uint32_t CHDATINR;    /*!< DFSDM channel data input register,                Address offset: 0x10 */
-} DFSDM_Channel_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-typedef struct
-{
-  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
-  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
-  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
-  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
-  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
-  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
-  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
-  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
-  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
-} DMA_Stream_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
-  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
-  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
-  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
-} DMA_TypeDef;
-
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
-  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
-  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
-  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
-  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
-  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-
-typedef struct
-{
-  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */
-  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */
-  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */
-  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */
-  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */
-  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief Flexible Memory Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */   
-} FSMC_Bank1_TypeDef; 
-
-/** 
-  * @brief Flexible Memory Controller Bank1E
-  */
-  
-typedef struct
-{
-  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
-} FSMC_Bank1E_TypeDef;
-
-/** 
-  * @brief General Purpose I/O
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
-  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
-  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
-  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
-  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
-  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
-  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
-  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/** 
-  * @brief System configuration controller
-  */
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */ 
-  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
-  uint32_t      RESERVED1[2]; /*!< Reserved, 0x24-0x28                                                          */ 
-  __IO uint32_t CFGR;         /*!< SYSCFG Configuration register,                     Address offset: 0x2C      */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */
-  __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */
-  __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */
-  __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */
-  __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */
-  __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
-  __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
-  __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
-  __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */
-} I2C_TypeDef;
-
-/**
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< FMPI2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< FMPI2C Control register 2,            Address offset: 0x04 */
-  __IO uint32_t OAR1;        /*!< FMPI2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;        /*!< FMPI2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;     /*!< FMPI2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR;    /*!< FMPI2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;         /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;         /*!< FMPI2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;        /*!< FMPI2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;        /*!< FMPI2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;        /*!< FMPI2C Transmit data register,        Address offset: 0x28 */
-} FMPI2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
-  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
-  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
-  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
-  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
-  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
-  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
-  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
-  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
-  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
-  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
-  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
-  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
-  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
-  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
-  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
-  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
-  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
-  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
-  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
-  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
-  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
-  uint32_t      RESERVED7;     /*!< Reserved, 0x84                                                                    */
-  __IO uint32_t DCKCFGR;       /*!< RCC Dedicated Clocks configuration register,                 Address offset: 0x8C */
-  __IO uint32_t CKGATENR;       /*!< RCC Clocks Gated ENable Register,                           Address offset: 0x90 */
-  __IO uint32_t DCKCFGR2;      /*!< RCC Dedicated Clocks configuration register 2,               Address offset: 0x94 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-
-typedef struct
-{
-  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
-  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
-  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
-  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
-  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
-  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
-  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */
-  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
-  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */
-  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
-  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */
-  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */
-  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */
-  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */
-  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
-  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */
-  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
-  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
-  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
-  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
-  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
-  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
-  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
-  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
-  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
-  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
-  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
-  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
-  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
-  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
-  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
-  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
-  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
-  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
-  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
-  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
-  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
-} RTC_TypeDef;
-
-
-/** 
-  * @brief SD host Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t POWER;          /*!< SDIO power control register,    Address offset: 0x00 */
-  __IO uint32_t CLKCR;          /*!< SDI clock control register,     Address offset: 0x04 */
-  __IO uint32_t ARG;            /*!< SDIO argument register,         Address offset: 0x08 */
-  __IO uint32_t CMD;            /*!< SDIO command register,          Address offset: 0x0C */
-  __I uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */
-  __I uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */
-  __I uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */
-  __I uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */
-  __I uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */
-  __IO uint32_t DTIMER;         /*!< SDIO data timer register,       Address offset: 0x24 */
-  __IO uint32_t DLEN;           /*!< SDIO data length register,      Address offset: 0x28 */
-  __IO uint32_t DCTRL;          /*!< SDIO data control register,     Address offset: 0x2C */
-  __I uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */
-  __I uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */
-  __IO uint32_t ICR;            /*!< SDIO interrupt clear register,  Address offset: 0x38 */
-  __IO uint32_t MASK;           /*!< SDIO mask register,             Address offset: 0x3C */
-  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
-  __I uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */
-  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
-  __IO uint32_t FIFO;           /*!< SDIO data FIFO register,        Address offset: 0x80 */
-} SDIO_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief QUAD Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */
-  __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
-  __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */
-  __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
-  __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
-  __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
-  __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */
-  __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
-  __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */
-  __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
-  __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */                  
-  __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
-  __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */    
-} QUADSPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
-  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
-  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
-  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-
-/** 
-  * @brief RNG
-  */
-  
-typedef struct 
-{
-  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
-  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
-  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
-} RNG_TypeDef;
-
-
-/** 
-  * @brief USB_OTG_Core_Registers
-  */
-typedef struct
-{
-  __IO uint32_t GOTGCTL;              /*!<  USB_OTG Control and Status Register            000h*/
-  __IO uint32_t GOTGINT;              /*!<  USB_OTG Interrupt Register                     004h*/
-  __IO uint32_t GAHBCFG;              /*!<  Core AHB Configuration Register                008h*/
-  __IO uint32_t GUSBCFG;              /*!<  Core USB Configuration Register                00Ch*/
-  __IO uint32_t GRSTCTL;              /*!<  Core Reset Register                            010h*/
-  __IO uint32_t GINTSTS;              /*!<  Core Interrupt Register                        014h*/
-  __IO uint32_t GINTMSK;              /*!<  Core Interrupt Mask Register                   018h*/
-  __IO uint32_t GRXSTSR;              /*!<  Receive Sts Q Read Register                    01Ch*/
-  __IO uint32_t GRXSTSP;              /*!<  Receive Sts Q Read & POP Register              020h*/
-  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                      024h*/
-  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!<  EP0 / Non Periodic Tx FIFO Size Register       028h*/
-  __IO uint32_t HNPTXSTS;             /*!<  Non Periodic Tx FIFO/Queue Sts reg             02Ch*/
-  uint32_t Reserved30[2];             /*!< Reserved                                        030h*/
-  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                     038h*/
-  __IO uint32_t CID;                  /*!< User ID Register                                03Ch*/
-  uint32_t  Reserved5[3];             /*!< Reserved                                        040h-048h*/
-  __IO uint32_t GHWCFG3;              /*!< User HW config3                                 04Ch*/
-  uint32_t  Reserved6;                /*!< Reserved                                        050h*/ 
-  __IO uint32_t GLPMCFG;              /*!< LPM Register                                    054h*/
-  uint32_t  Reserved;                 /*!< Reserved                                        058h */
-  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register                  05Ch */
-  uint32_t  Reserved43[40];           /*!< Reserved                                        058h-0FFh */
-  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg                  100h*/
-  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */
-} USB_OTG_GlobalTypeDef;
-
-
-/** 
-  * @brief USB_OTG_device_Registers
-  */
-typedef struct 
-{
-  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */
-  __IO uint32_t DCTL;            /*!< dev Control Register         804h */
-  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */
-  uint32_t Reserved0C;           /*!< Reserved                     80Ch */
-  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */
-  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */
-  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */
-  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */
-  uint32_t  Reserved20;          /*!< Reserved                     820h */
-  uint32_t Reserved9;            /*!< Reserved                     824h */
-  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */
-  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */
-  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */
-  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */
-  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */
-  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */
-  uint32_t Reserved40;           /*!< dedicated EP mask            840h */
-  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */
-  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */
-  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */
-} USB_OTG_DeviceTypeDef;
-
-
-/** 
-  * @brief USB_OTG_IN_Endpoint-Specific_Register
-  */
-typedef struct 
-{
-  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */
-  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */
-  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */
-  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */
-  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */
-  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */
-  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
-  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
-} USB_OTG_INEndpointTypeDef;
-
-
-/** 
-  * @brief USB_OTG_OUT_Endpoint-Specific_Registers
-  */
-typedef struct 
-{
-  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */
-  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */
-  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */
-  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */
-  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */
-  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */
-  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
-} USB_OTG_OUTEndpointTypeDef;
-
-
-/** 
-  * @brief USB_OTG_Host_Mode_Register_Structures
-  */
-typedef struct 
-{
-  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */
-  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */
-  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */
-  uint32_t Reserved40C;           /*!< Reserved                             40Ch */
-  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */
-  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */
-  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */
-} USB_OTG_HostTypeDef;
-
-
-/** 
-  * @brief USB_OTG_Host_Channel_Specific_Registers
-  */
-typedef struct
-{
-  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */
-  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */
-  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */
-  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */
-  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */
-  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */
-  uint32_t Reserved[2];           /*!< Reserved                                      */
-} USB_OTG_HostChannelTypeDef;
-
-    
-/** 
-  * @brief Peripheral_memory_map
-  */
-#define FLASH_BASE            0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region                         */
-#define SRAM1_BASE            0x20000000U /*!< SRAM1(256 KB) base address in the alias region                             */
-#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region                                */
-#define FSMC_R_BASE           0xA0000000U /*!< FSMC registers base address                                                */
-#define QSPI_R_BASE           0xA0001000U /*!< QuadSPI registers base address                                             */
-
-#define SRAM1_BB_BASE         0x22000000U /*!< SRAM1(256 KB) base address in the bit-band region                             */
-#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region                                */
-#define FLASH_END             0x080FFFFFU /*!< FLASH end address                                                             */
-
-/* Legacy defines */
-#define SRAM_BASE             SRAM1_BASE
-#define SRAM_BB_BASE          SRAM1_BB_BASE
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000U)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)
-#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800U)
-#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00U)
-#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000U)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)
-#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400U)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)
-#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000U)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800U)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)
-#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)
-#define FMPI2C1_BASE          (APB1PERIPH_BASE + 0x6000U)
-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)
-#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800U)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)
-
-/*!< APB2 peripherals */
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000U)
-#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400U)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x1000U)
-#define USART6_BASE           (APB2PERIPH_BASE + 0x1400U)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000U)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x2300U)
-#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00U)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)
-#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400U)
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800U)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00U)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000U)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400U)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800U)
-#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000U)
-#define DFSDM1_BASE           (APB2PERIPH_BASE + 0x6000U)
-#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00U)
-#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20U)
-#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40U)
-#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60U)
-#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100U)
-#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180U)
-
-/*!< AHB1 peripherals */
-#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000U)
-#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400U)
-#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800U)
-#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00U)
-#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000U)
-#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400U)
-#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800U)
-#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00U)
-#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)
-#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800U)
-#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00U)
-#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000U)
-#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010U)
-#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028U)
-#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040U)
-#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058U)
-#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070U)
-#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088U)
-#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0U)
-#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8U)
-#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400U)
-#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010U)
-#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028U)
-#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040U)
-#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058U)
-#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070U)
-#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088U)
-#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0U)
-#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)
-
-/*!< AHB2 peripherals */
-#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800U)
-
-/*!< FSMC Bankx registers base address */
-#define FSMC_Bank1_R_BASE      (FSMC_R_BASE + 0x0000U)
-#define FSMC_Bank1E_R_BASE     (FSMC_R_BASE + 0x0104U)
-
-/* Debug MCU registers base address */
-#define DBGMCU_BASE           0xE0042000U
-
-/*!< USB registers base address */
-#define USB_OTG_FS_PERIPH_BASE               0x50000000U
-
-#define USB_OTG_GLOBAL_BASE                  0x000U
-#define USB_OTG_DEVICE_BASE                  0x800U
-#define USB_OTG_IN_ENDPOINT_BASE             0x900U
-#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U
-#define USB_OTG_EP_REG_SIZE                  0x20U
-#define USB_OTG_HOST_BASE                    0x400U
-#define USB_OTG_HOST_PORT_BASE               0x440U
-#define USB_OTG_HOST_CHANNEL_BASE            0x500U
-#define USB_OTG_HOST_CHANNEL_SIZE            0x20U
-#define USB_OTG_PCGCCTL_BASE                 0xE00U
-#define USB_OTG_FIFO_BASE                    0x1000U
-#define USB_OTG_FIFO_SIZE                    0x1000U
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
-#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
-#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
-#define FMPI2C1             ((FMPI2C_TypeDef *) FMPI2C1_BASE)
-#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
-#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
-#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define USART6              ((USART_TypeDef *) USART6_BASE)
-#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define SPI4                ((SPI_TypeDef *) SPI4_BASE)
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-#define SPI5                ((SPI_TypeDef *) SPI5_BASE)
-#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
-#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
-#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
-#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
-#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
-#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
-#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
-#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
-#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
-#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
-#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
-#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
-#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
-#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
-#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
-#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
-#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
-#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
-#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
-#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
-#define RNG                 ((RNG_TypeDef *) RNG_BASE)
-#define FSMC_Bank1           ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
-#define FSMC_Bank1E          ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
-#define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)
-
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers_Bits_Definition               */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Analog to Digital Converter                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          0x00000001U       /*!<Analog watchdog flag */
-#define  ADC_SR_EOC                          0x00000002U       /*!<End of conversion */
-#define  ADC_SR_JEOC                         0x00000004U       /*!<Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        0x00000008U       /*!<Injected channel Start flag */
-#define  ADC_SR_STRT                         0x00000010U       /*!<Regular channel Start flag */
-#define  ADC_SR_OVR                          0x00000020U       /*!<Overrun flag */
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
-#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels */
-#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels */
-#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution) */
-#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
-  
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion */
-#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode */
-#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC) */
-#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection */
-#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment */
-#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      0xFFFFU            /*!<Injected data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag */
-#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion */
-#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag */
-#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag */
-#define  ADC_CSR_DOVR1                       0x00000020U        /*!<ADC1 DMA overrun  flag */
-#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag */
-#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion */
-#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag */
-#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag */
-#define  ADC_CSR_DOVR2                       0x00002000U        /*!<ADC2 DMA overrun  flag */
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
-#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
-#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
-#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
-#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
-
-/*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                      0x0000FFFFU         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                      0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Controller Area Network                            */
-/*                                                                            */
-/******************************************************************************/
-/*!<CAN control and status registers */
-/*******************  Bit definition for CAN_MCR register  ********************/
-#define  CAN_MCR_INRQ                        0x00000001U        /*!<Initialization Request */
-#define  CAN_MCR_SLEEP                       0x00000002U        /*!<Sleep Mode Request */
-#define  CAN_MCR_TXFP                        0x00000004U        /*!<Transmit FIFO Priority */
-#define  CAN_MCR_RFLM                        0x00000008U        /*!<Receive FIFO Locked Mode */
-#define  CAN_MCR_NART                        0x00000010U        /*!<No Automatic Retransmission */
-#define  CAN_MCR_AWUM                        0x00000020U        /*!<Automatic Wakeup Mode */
-#define  CAN_MCR_ABOM                        0x00000040U        /*!<Automatic Bus-Off Management */
-#define  CAN_MCR_TTCM                        0x00000080U        /*!<Time Triggered Communication Mode */
-#define  CAN_MCR_RESET                       0x00008000U        /*!<bxCAN software master reset */
-#define  CAN_MCR_DBF                         0x00010000U        /*!<bxCAN Debug freeze */
-/*******************  Bit definition for CAN_MSR register  ********************/
-#define  CAN_MSR_INAK                        0x0001U            /*!<Initialization Acknowledge */
-#define  CAN_MSR_SLAK                        0x0002U            /*!<Sleep Acknowledge */
-#define  CAN_MSR_ERRI                        0x0004U            /*!<Error Interrupt */
-#define  CAN_MSR_WKUI                        0x0008U            /*!<Wakeup Interrupt */
-#define  CAN_MSR_SLAKI                       0x0010U            /*!<Sleep Acknowledge Interrupt */
-#define  CAN_MSR_TXM                         0x0100U            /*!<Transmit Mode */
-#define  CAN_MSR_RXM                         0x0200U            /*!<Receive Mode */
-#define  CAN_MSR_SAMP                        0x0400U            /*!<Last Sample Point */
-#define  CAN_MSR_RX                          0x0800U            /*!<CAN Rx Signal */
-
-/*******************  Bit definition for CAN_TSR register  ********************/
-#define  CAN_TSR_RQCP0                       0x00000001U        /*!<Request Completed Mailbox0 */
-#define  CAN_TSR_TXOK0                       0x00000002U        /*!<Transmission OK of Mailbox0 */
-#define  CAN_TSR_ALST0                       0x00000004U        /*!<Arbitration Lost for Mailbox0 */
-#define  CAN_TSR_TERR0                       0x00000008U        /*!<Transmission Error of Mailbox0 */
-#define  CAN_TSR_ABRQ0                       0x00000080U        /*!<Abort Request for Mailbox0 */
-#define  CAN_TSR_RQCP1                       0x00000100U        /*!<Request Completed Mailbox1 */
-#define  CAN_TSR_TXOK1                       0x00000200U        /*!<Transmission OK of Mailbox1 */
-#define  CAN_TSR_ALST1                       0x00000400U        /*!<Arbitration Lost for Mailbox1 */
-#define  CAN_TSR_TERR1                       0x00000800U        /*!<Transmission Error of Mailbox1 */
-#define  CAN_TSR_ABRQ1                       0x00008000U        /*!<Abort Request for Mailbox 1 */
-#define  CAN_TSR_RQCP2                       0x00010000U        /*!<Request Completed Mailbox2 */
-#define  CAN_TSR_TXOK2                       0x00020000U        /*!<Transmission OK of Mailbox 2 */
-#define  CAN_TSR_ALST2                       0x00040000U        /*!<Arbitration Lost for mailbox 2 */
-#define  CAN_TSR_TERR2                       0x00080000U        /*!<Transmission Error of Mailbox 2 */
-#define  CAN_TSR_ABRQ2                       0x00800000U        /*!<Abort Request for Mailbox 2 */
-#define  CAN_TSR_CODE                        0x03000000U        /*!<Mailbox Code */
-
-#define  CAN_TSR_TME                         0x1C000000U        /*!<TME[2:0] bits */
-#define  CAN_TSR_TME0                        0x04000000U        /*!<Transmit Mailbox 0 Empty */
-#define  CAN_TSR_TME1                        0x08000000U        /*!<Transmit Mailbox 1 Empty */
-#define  CAN_TSR_TME2                        0x10000000U        /*!<Transmit Mailbox 2 Empty */
-
-#define  CAN_TSR_LOW                         0xE0000000U        /*!<LOW[2:0] bits */
-#define  CAN_TSR_LOW0                        0x20000000U        /*!<Lowest Priority Flag for Mailbox 0 */
-#define  CAN_TSR_LOW1                        0x40000000U        /*!<Lowest Priority Flag for Mailbox 1 */
-#define  CAN_TSR_LOW2                        0x80000000U        /*!<Lowest Priority Flag for Mailbox 2 */
-
-/*******************  Bit definition for CAN_RF0R register  *******************/
-#define  CAN_RF0R_FMP0                       0x03U               /*!<FIFO 0 Message Pending */
-#define  CAN_RF0R_FULL0                      0x08U               /*!<FIFO 0 Full */
-#define  CAN_RF0R_FOVR0                      0x10U               /*!<FIFO 0 Overrun */
-#define  CAN_RF0R_RFOM0                      0x20U               /*!<Release FIFO 0 Output Mailbox */
-
-/*******************  Bit definition for CAN_RF1R register  *******************/
-#define  CAN_RF1R_FMP1                       0x03U               /*!<FIFO 1 Message Pending */
-#define  CAN_RF1R_FULL1                      0x08U               /*!<FIFO 1 Full */
-#define  CAN_RF1R_FOVR1                      0x10U               /*!<FIFO 1 Overrun */
-#define  CAN_RF1R_RFOM1                      0x20U               /*!<Release FIFO 1 Output Mailbox */
-
-/********************  Bit definition for CAN_IER register  *******************/
-#define  CAN_IER_TMEIE                       0x00000001U        /*!<Transmit Mailbox Empty Interrupt Enable */
-#define  CAN_IER_FMPIE0                      0x00000002U        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE0                       0x00000004U        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE0                      0x00000008U        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_FMPIE1                      0x00000010U        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE1                       0x00000020U        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE1                      0x00000040U        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error Warning Interrupt Enable */
-#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error Passive Interrupt Enable */
-#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-Off Interrupt Enable */
-#define  CAN_IER_LECIE                       0x00000800U        /*!<Last Error Code Interrupt Enable */
-#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error Interrupt Enable */
-#define  CAN_IER_WKUIE                       0x00010000U        /*!<Wakeup Interrupt Enable */
-#define  CAN_IER_SLKIE                       0x00020000U        /*!<Sleep Interrupt Enable */
-#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error warning interrupt enable */
-#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error passive interrupt enable */
-#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-off interrupt enable */
-#define  CAN_IER_LECIE                       0x00000800U        /*!<Last error code interrupt enable */
-#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error interrupt enable */
-
-
-/********************  Bit definition for CAN_ESR register  *******************/
-#define  CAN_ESR_EWGF                        0x00000001U        /*!<Error Warning Flag */
-#define  CAN_ESR_EPVF                        0x00000002U        /*!<Error Passive Flag */
-#define  CAN_ESR_BOFF                        0x00000004U        /*!<Bus-Off Flag */
-
-#define  CAN_ESR_LEC                         0x00000070U        /*!<LEC[2:0] bits (Last Error Code) */
-#define  CAN_ESR_LEC_0                       0x00000010U        /*!<Bit 0 */
-#define  CAN_ESR_LEC_1                       0x00000020U        /*!<Bit 1 */
-#define  CAN_ESR_LEC_2                       0x00000040U        /*!<Bit 2 */
-
-#define  CAN_ESR_TEC                         0x00FF0000U        /*!<Least significant byte of the 9-bit Transmit Error Counter */
-#define  CAN_ESR_REC                         0xFF000000U        /*!<Receive Error Counter */
-
-/*******************  Bit definition for CAN_BTR register  ********************/
-#define  CAN_BTR_BRP                         0x000003FFU        /*!<Baud Rate Prescaler */
-#define  CAN_BTR_TS1                         0x000F0000U        /*!<Time Segment 1 */
-#define  CAN_BTR_TS1_0                       0x00010000U        /*!<Bit 0 */
-#define  CAN_BTR_TS1_1                       0x00020000U        /*!<Bit 1 */
-#define  CAN_BTR_TS1_2                       0x00040000U        /*!<Bit 2 */
-#define  CAN_BTR_TS1_3                       0x00080000U        /*!<Bit 3 */
-#define  CAN_BTR_TS2                         0x00700000U        /*!<Time Segment 2 */
-#define  CAN_BTR_TS2_0                       0x00100000U        /*!<Bit 0 */
-#define  CAN_BTR_TS2_1                       0x00200000U        /*!<Bit 1 */
-#define  CAN_BTR_TS2_2                       0x00400000U        /*!<Bit 2 */
-#define  CAN_BTR_SJW                         0x03000000U        /*!<Resynchronization Jump Width */
-#define  CAN_BTR_SJW_0                       0x01000000U        /*!<Bit 0 */
-#define  CAN_BTR_SJW_1                       0x02000000U        /*!<Bit 1 */
-#define  CAN_BTR_LBKM                        0x40000000U        /*!<Loop Back Mode (Debug) */
-#define  CAN_BTR_SILM                        0x80000000U        /*!<Silent Mode */
-
-
-/*!<Mailbox registers */
-/******************  Bit definition for CAN_TI0R register  ********************/
-#define  CAN_TI0R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI0R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_TI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/******************  Bit definition for CAN_TDT0R register  *******************/
-#define  CAN_TDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT0R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/******************  Bit definition for CAN_TDL0R register  *******************/
-#define  CAN_TDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/******************  Bit definition for CAN_TDH0R register  *******************/
-#define  CAN_TDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI1R register  *******************/
-#define  CAN_TI1R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI1R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI1R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_TI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT1R register  ******************/
-#define  CAN_TDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT1R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL1R register  ******************/
-#define  CAN_TDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH1R register  ******************/
-#define  CAN_TDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI2R register  *******************/
-#define  CAN_TI2R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI2R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI2R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI2R_EXID                       0x001FFFF8U        /*!<Extended identifier */
-#define  CAN_TI2R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT2R register  ******************/  
-#define  CAN_TDT2R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT2R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT2R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL2R register  ******************/
-#define  CAN_TDL2R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL2R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL2R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL2R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH2R register  ******************/
-#define  CAN_TDH2R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH2R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH2R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH2R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI0R register  *******************/
-#define  CAN_RI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_RI0R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_RI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_RI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT0R register  ******************/
-#define  CAN_RDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_RDT0R_FMI                       0x0000FF00U        /*!<Filter Match Index */
-#define  CAN_RDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL0R register  ******************/
-#define  CAN_RDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_RDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_RDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_RDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH0R register  ******************/
-#define  CAN_RDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_RDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_RDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_RDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI1R register  *******************/
-#define  CAN_RI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_RI1R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_RI1R_EXID                       0x001FFFF8U        /*!<Extended identifier */
-#define  CAN_RI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT1R register  ******************/
-#define  CAN_RDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_RDT1R_FMI                       0x0000FF00U        /*!<Filter Match Index */
-#define  CAN_RDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL1R register  ******************/
-#define  CAN_RDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_RDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_RDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_RDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH1R register  ******************/
-#define  CAN_RDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_RDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_RDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_RDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*!<CAN filter registers */
-/*******************  Bit definition for CAN_FMR register  ********************/
-#define  CAN_FMR_FINIT                       0x01U               /*!<Filter Init Mode */
-#define  CAN_FMR_CAN2SB                      0x00003F00U        /*!<CAN2 start bank */
-
-/*******************  Bit definition for CAN_FM1R register  *******************/
-#define  CAN_FM1R_FBM                        0x0FFFFFFFU        /*!<Filter Mode */
-#define  CAN_FM1R_FBM0                       0x00000001U        /*!<Filter Init Mode bit 0 */
-#define  CAN_FM1R_FBM1                       0x00000002U        /*!<Filter Init Mode bit 1 */
-#define  CAN_FM1R_FBM2                       0x00000004U        /*!<Filter Init Mode bit 2 */
-#define  CAN_FM1R_FBM3                       0x00000008U        /*!<Filter Init Mode bit 3 */
-#define  CAN_FM1R_FBM4                       0x00000010U        /*!<Filter Init Mode bit 4 */
-#define  CAN_FM1R_FBM5                       0x00000020U        /*!<Filter Init Mode bit 5 */
-#define  CAN_FM1R_FBM6                       0x00000040U        /*!<Filter Init Mode bit 6 */
-#define  CAN_FM1R_FBM7                       0x00000080U        /*!<Filter Init Mode bit 7 */
-#define  CAN_FM1R_FBM8                       0x00000100U        /*!<Filter Init Mode bit 8 */
-#define  CAN_FM1R_FBM9                       0x00000200U        /*!<Filter Init Mode bit 9 */
-#define  CAN_FM1R_FBM10                      0x00000400U        /*!<Filter Init Mode bit 10 */
-#define  CAN_FM1R_FBM11                      0x00000800U        /*!<Filter Init Mode bit 11 */
-#define  CAN_FM1R_FBM12                      0x00001000U        /*!<Filter Init Mode bit 12 */
-#define  CAN_FM1R_FBM13                      0x00002000U        /*!<Filter Init Mode bit 13 */
-#define  CAN_FM1R_FBM14                      0x00004000U        /*!<Filter Init Mode bit 14 */
-#define  CAN_FM1R_FBM15                      0x00008000U        /*!<Filter Init Mode bit 15 */
-#define  CAN_FM1R_FBM16                      0x00010000U        /*!<Filter Init Mode bit 16 */
-#define  CAN_FM1R_FBM17                      0x00020000U        /*!<Filter Init Mode bit 17 */
-#define  CAN_FM1R_FBM18                      0x00040000U        /*!<Filter Init Mode bit 18 */
-#define  CAN_FM1R_FBM19                      0x00080000U        /*!<Filter Init Mode bit 19 */
-#define  CAN_FM1R_FBM20                      0x00100000U        /*!<Filter Init Mode bit 20 */
-#define  CAN_FM1R_FBM21                      0x00200000U        /*!<Filter Init Mode bit 21 */
-#define  CAN_FM1R_FBM22                      0x00400000U        /*!<Filter Init Mode bit 22 */
-#define  CAN_FM1R_FBM23                      0x00800000U        /*!<Filter Init Mode bit 23 */
-#define  CAN_FM1R_FBM24                      0x01000000U        /*!<Filter Init Mode bit 24 */
-#define  CAN_FM1R_FBM25                      0x02000000U        /*!<Filter Init Mode bit 25 */
-#define  CAN_FM1R_FBM26                      0x04000000U        /*!<Filter Init Mode bit 26 */
-#define  CAN_FM1R_FBM27                      0x08000000U        /*!<Filter Init Mode bit 27 */
-
-/*******************  Bit definition for CAN_FS1R register  *******************/
-#define  CAN_FS1R_FSC                        0x0FFFFFFFU        /*!<Filter Scale Configuration */
-#define  CAN_FS1R_FSC0                       0x00000001U        /*!<Filter Scale Configuration bit 0 */
-#define  CAN_FS1R_FSC1                       0x00000002U        /*!<Filter Scale Configuration bit 1 */
-#define  CAN_FS1R_FSC2                       0x00000004U        /*!<Filter Scale Configuration bit 2 */
-#define  CAN_FS1R_FSC3                       0x00000008U        /*!<Filter Scale Configuration bit 3 */
-#define  CAN_FS1R_FSC4                       0x00000010U        /*!<Filter Scale Configuration bit 4 */
-#define  CAN_FS1R_FSC5                       0x00000020U        /*!<Filter Scale Configuration bit 5 */
-#define  CAN_FS1R_FSC6                       0x00000040U        /*!<Filter Scale Configuration bit 6 */
-#define  CAN_FS1R_FSC7                       0x00000080U        /*!<Filter Scale Configuration bit 7 */
-#define  CAN_FS1R_FSC8                       0x00000100U        /*!<Filter Scale Configuration bit 8 */
-#define  CAN_FS1R_FSC9                       0x00000200U        /*!<Filter Scale Configuration bit 9 */
-#define  CAN_FS1R_FSC10                      0x00000400U        /*!<Filter Scale Configuration bit 10 */
-#define  CAN_FS1R_FSC11                      0x00000800U        /*!<Filter Scale Configuration bit 11 */
-#define  CAN_FS1R_FSC12                      0x00001000U        /*!<Filter Scale Configuration bit 12 */
-#define  CAN_FS1R_FSC13                      0x00002000U        /*!<Filter Scale Configuration bit 13 */
-#define  CAN_FS1R_FSC14                      0x00004000U        /*!<Filter Scale Configuration bit 14 */
-#define  CAN_FS1R_FSC15                      0x00008000U        /*!<Filter Scale Configuration bit 15 */
-#define  CAN_FS1R_FSC16                      0x00010000U        /*!<Filter Scale Configuration bit 16 */
-#define  CAN_FS1R_FSC17                      0x00020000U        /*!<Filter Scale Configuration bit 17 */
-#define  CAN_FS1R_FSC18                      0x00040000U        /*!<Filter Scale Configuration bit 18 */
-#define  CAN_FS1R_FSC19                      0x00080000U        /*!<Filter Scale Configuration bit 19 */
-#define  CAN_FS1R_FSC20                      0x00100000U        /*!<Filter Scale Configuration bit 20 */
-#define  CAN_FS1R_FSC21                      0x00200000U        /*!<Filter Scale Configuration bit 21 */
-#define  CAN_FS1R_FSC22                      0x00400000U        /*!<Filter Scale Configuration bit 22 */
-#define  CAN_FS1R_FSC23                      0x00800000U        /*!<Filter Scale Configuration bit 23 */
-#define  CAN_FS1R_FSC24                      0x01000000U        /*!<Filter Scale Configuration bit 24 */
-#define  CAN_FS1R_FSC25                      0x02000000U        /*!<Filter Scale Configuration bit 25 */
-#define  CAN_FS1R_FSC26                      0x04000000U        /*!<Filter Scale Configuration bit 26 */
-#define  CAN_FS1R_FSC27                      0x08000000U        /*!<Filter Scale Configuration bit 27 */
-
-/******************  Bit definition for CAN_FFA1R register  *******************/
-#define  CAN_FFA1R_FFA                        0x0FFFFFFFU        /*!<Filter FIFO Assignment */
-#define  CAN_FFA1R_FFA0                       0x00000001U        /*!<Filter FIFO Assignment bit 0 */
-#define  CAN_FFA1R_FFA1                       0x00000002U        /*!<Filter FIFO Assignment bit 1 */
-#define  CAN_FFA1R_FFA2                       0x00000004U        /*!<Filter FIFO Assignment bit 2 */
-#define  CAN_FFA1R_FFA3                       0x00000008U        /*!<Filter FIFO Assignment bit 3 */
-#define  CAN_FFA1R_FFA4                       0x00000010U        /*!<Filter FIFO Assignment bit 4 */
-#define  CAN_FFA1R_FFA5                       0x00000020U        /*!<Filter FIFO Assignment bit 5 */
-#define  CAN_FFA1R_FFA6                       0x00000040U        /*!<Filter FIFO Assignment bit 6 */
-#define  CAN_FFA1R_FFA7                       0x00000080U        /*!<Filter FIFO Assignment bit 7 */
-#define  CAN_FFA1R_FFA8                       0x00000100U        /*!<Filter FIFO Assignment bit 8 */
-#define  CAN_FFA1R_FFA9                       0x00000200U        /*!<Filter FIFO Assignment bit 9 */
-#define  CAN_FFA1R_FFA10                      0x00000400U        /*!<Filter FIFO Assignment bit 10 */
-#define  CAN_FFA1R_FFA11                      0x00000800U        /*!<Filter FIFO Assignment bit 11 */
-#define  CAN_FFA1R_FFA12                      0x00001000U        /*!<Filter FIFO Assignment bit 12 */
-#define  CAN_FFA1R_FFA13                      0x00002000U        /*!<Filter FIFO Assignment bit 13 */
-#define  CAN_FFA1R_FFA14                      0x00004000U        /*!<Filter FIFO Assignment bit 14 */
-#define  CAN_FFA1R_FFA15                      0x00008000U        /*!<Filter FIFO Assignment bit 15 */
-#define  CAN_FFA1R_FFA16                      0x00010000U        /*!<Filter FIFO Assignment bit 16 */
-#define  CAN_FFA1R_FFA17                      0x00020000U        /*!<Filter FIFO Assignment bit 17 */
-#define  CAN_FFA1R_FFA18                      0x00040000U        /*!<Filter FIFO Assignment bit 18 */
-#define  CAN_FFA1R_FFA19                      0x00080000U        /*!<Filter FIFO Assignment bit 19 */
-#define  CAN_FFA1R_FFA20                      0x00100000U        /*!<Filter FIFO Assignment bit 20 */
-#define  CAN_FFA1R_FFA21                      0x00200000U        /*!<Filter FIFO Assignment bit 21 */
-#define  CAN_FFA1R_FFA22                      0x00400000U        /*!<Filter FIFO Assignment bit 22 */
-#define  CAN_FFA1R_FFA23                      0x00800000U        /*!<Filter FIFO Assignment bit 23 */
-#define  CAN_FFA1R_FFA24                      0x01000000U        /*!<Filter FIFO Assignment bit 24 */
-#define  CAN_FFA1R_FFA25                      0x02000000U        /*!<Filter FIFO Assignment bit 25 */
-#define  CAN_FFA1R_FFA26                      0x04000000U        /*!<Filter FIFO Assignment bit 26 */
-#define  CAN_FFA1R_FFA27                      0x08000000U        /*!<Filter FIFO Assignment bit 27 */
-
-/*******************  Bit definition for CAN_FA1R register  *******************/
-#define  CAN_FA1R_FACT                        0x0FFFFFFFU        /*!<Filter Active */
-#define  CAN_FA1R_FACT0                       0x00000001U        /*!<Filter Active bit 0 */
-#define  CAN_FA1R_FACT1                       0x00000002U        /*!<Filter Active bit 1 */
-#define  CAN_FA1R_FACT2                       0x00000004U        /*!<Filter Active bit 2 */
-#define  CAN_FA1R_FACT3                       0x00000008U        /*!<Filter Active bit 3 */
-#define  CAN_FA1R_FACT4                       0x00000010U        /*!<Filter Active bit 4 */
-#define  CAN_FA1R_FACT5                       0x00000020U        /*!<Filter Active bit 5 */
-#define  CAN_FA1R_FACT6                       0x00000040U        /*!<Filter Active bit 6 */
-#define  CAN_FA1R_FACT7                       0x00000080U        /*!<Filter Active bit 7 */
-#define  CAN_FA1R_FACT8                       0x00000100U        /*!<Filter Active bit 8 */
-#define  CAN_FA1R_FACT9                       0x00000200U        /*!<Filter Active bit 9 */
-#define  CAN_FA1R_FACT10                      0x00000400U        /*!<Filter Active bit 10 */
-#define  CAN_FA1R_FACT11                      0x00000800U        /*!<Filter Active bit 11 */
-#define  CAN_FA1R_FACT12                      0x00001000U        /*!<Filter Active bit 12 */
-#define  CAN_FA1R_FACT13                      0x00002000U        /*!<Filter Active bit 13 */
-#define  CAN_FA1R_FACT14                      0x00004000U        /*!<Filter Active bit 14 */
-#define  CAN_FA1R_FACT15                      0x00008000U        /*!<Filter Active bit 15 */
-#define  CAN_FA1R_FACT16                      0x00010000U        /*!<Filter Active bit 16 */
-#define  CAN_FA1R_FACT17                      0x00020000U        /*!<Filter Active bit 17 */
-#define  CAN_FA1R_FACT18                      0x00040000U        /*!<Filter Active bit 18 */
-#define  CAN_FA1R_FACT19                      0x00080000U        /*!<Filter Active bit 19 */
-#define  CAN_FA1R_FACT20                      0x00100000U        /*!<Filter Active bit 20 */
-#define  CAN_FA1R_FACT21                      0x00200000U        /*!<Filter Active bit 21 */
-#define  CAN_FA1R_FACT22                      0x00400000U        /*!<Filter Active bit 22 */
-#define  CAN_FA1R_FACT23                      0x00800000U        /*!<Filter Active bit 23 */
-#define  CAN_FA1R_FACT24                      0x01000000U        /*!<Filter Active bit 24 */
-#define  CAN_FA1R_FACT25                      0x02000000U        /*!<Filter Active bit 25 */
-#define  CAN_FA1R_FACT26                      0x04000000U        /*!<Filter Active bit 26 */
-#define  CAN_FA1R_FACT27                      0x08000000U        /*!<Filter Active bit 27 */
-
-/*******************  Bit definition for CAN_F0R1 register  *******************/
-#define  CAN_F0R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F0R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F0R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F0R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F0R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F0R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F0R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F0R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F0R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F0R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F0R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F0R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F0R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F0R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F0R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F0R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F0R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F0R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F0R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F0R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F0R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F0R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F0R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F0R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F0R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F0R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F0R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F0R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F0R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F0R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F0R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F0R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R1 register  *******************/
-#define  CAN_F1R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F1R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F1R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F1R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F1R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F1R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F1R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F1R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F1R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F1R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F1R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F1R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F1R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F1R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F1R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F1R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F1R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F1R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F1R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F1R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F1R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F1R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F1R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F1R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F1R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F1R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F1R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F1R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F1R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F1R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F1R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F1R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R1 register  *******************/
-#define  CAN_F2R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F2R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F2R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F2R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F2R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F2R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F2R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F2R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F2R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F2R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F2R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F2R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F2R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F2R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F2R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F2R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F2R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F2R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F2R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F2R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F2R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F2R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F2R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F2R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F2R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F2R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F2R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F2R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F2R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F2R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F2R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F2R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R1 register  *******************/
-#define  CAN_F3R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F3R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F3R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F3R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F3R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F3R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F3R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F3R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F3R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F3R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F3R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F3R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F3R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F3R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F3R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F3R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F3R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F3R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F3R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F3R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F3R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F3R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F3R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F3R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F3R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F3R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F3R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F3R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F3R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F3R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F3R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F3R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R1 register  *******************/
-#define  CAN_F4R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F4R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F4R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F4R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F4R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F4R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F4R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F4R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F4R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F4R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F4R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F4R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F4R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F4R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F4R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F4R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F4R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F4R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F4R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F4R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F4R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F4R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F4R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F4R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F4R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F4R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F4R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F4R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F4R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F4R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F4R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F4R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R1 register  *******************/
-#define  CAN_F5R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F5R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F5R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F5R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F5R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F5R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F5R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F5R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F5R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F5R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F5R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F5R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F5R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F5R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F5R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F5R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F5R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F5R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F5R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F5R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F5R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F5R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F5R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F5R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F5R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F5R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F5R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F5R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F5R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F5R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F5R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F5R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R1 register  *******************/
-#define  CAN_F6R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F6R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F6R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F6R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F6R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F6R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F6R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F6R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F6R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F6R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F6R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F6R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F6R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F6R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F6R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F6R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F6R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F6R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F6R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F6R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F6R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F6R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F6R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F6R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F6R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F6R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F6R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F6R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F6R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F6R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F6R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F6R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R1 register  *******************/
-#define  CAN_F7R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F7R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F7R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F7R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F7R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F7R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F7R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F7R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F7R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F7R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F7R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F7R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F7R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F7R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F7R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F7R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F7R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F7R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F7R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F7R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F7R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F7R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F7R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F7R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F7R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F7R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F7R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F7R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F7R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F7R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F7R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F7R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R1 register  *******************/
-#define  CAN_F8R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F8R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F8R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F8R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F8R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F8R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F8R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F8R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F8R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F8R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F8R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F8R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F8R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F8R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F8R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F8R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F8R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F8R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F8R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F8R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F8R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F8R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F8R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F8R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F8R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F8R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F8R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F8R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F8R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F8R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F8R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F8R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R1 register  *******************/
-#define  CAN_F9R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F9R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F9R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F9R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F9R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F9R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F9R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F9R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F9R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F9R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F9R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F9R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F9R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F9R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F9R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F9R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F9R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F9R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F9R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F9R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F9R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F9R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F9R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F9R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F9R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F9R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F9R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F9R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F9R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F9R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F9R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F9R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R1 register  ******************/
-#define  CAN_F10R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F10R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F10R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F10R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F10R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F10R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F10R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F10R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F10R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F10R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F10R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F10R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F10R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F10R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F10R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F10R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F10R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F10R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F10R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F10R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F10R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F10R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F10R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F10R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F10R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F10R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F10R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F10R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F10R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F10R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F10R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F10R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R1 register  ******************/
-#define  CAN_F11R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F11R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F11R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F11R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F11R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F11R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F11R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F11R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F11R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F11R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F11R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F11R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F11R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F11R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F11R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F11R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F11R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F11R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F11R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F11R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F11R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F11R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F11R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F11R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F11R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F11R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F11R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F11R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F11R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F11R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F11R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F11R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R1 register  ******************/
-#define  CAN_F12R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F12R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F12R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F12R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F12R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F12R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F12R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F12R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F12R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F12R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F12R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F12R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F12R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F12R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F12R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F12R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F12R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F12R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F12R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F12R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F12R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F12R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F12R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F12R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F12R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F12R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F12R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F12R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F12R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F12R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F12R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F12R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R1 register  ******************/
-#define  CAN_F13R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F13R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F13R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F13R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F13R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F13R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F13R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F13R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F13R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F13R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F13R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F13R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F13R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F13R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F13R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F13R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F13R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F13R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F13R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F13R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F13R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F13R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F13R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F13R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F13R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F13R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F13R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F13R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F13R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F13R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F13R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F13R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F0R2 register  *******************/
-#define  CAN_F0R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F0R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F0R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F0R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F0R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F0R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F0R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F0R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F0R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F0R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F0R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F0R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F0R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F0R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F0R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F0R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F0R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F0R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F0R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F0R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F0R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F0R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F0R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F0R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F0R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F0R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F0R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F0R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F0R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F0R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F0R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F0R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R2 register  *******************/
-#define  CAN_F1R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F1R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F1R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F1R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F1R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F1R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F1R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F1R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F1R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F1R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F1R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F1R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F1R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F1R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F1R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F1R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F1R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F1R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F1R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F1R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F1R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F1R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F1R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F1R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F1R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F1R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F1R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F1R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F1R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F1R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F1R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F1R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R2 register  *******************/
-#define  CAN_F2R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F2R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F2R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F2R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F2R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F2R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F2R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F2R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F2R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F2R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F2R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F2R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F2R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F2R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F2R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F2R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F2R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F2R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F2R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F2R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F2R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F2R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F2R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F2R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F2R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F2R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F2R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F2R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F2R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F2R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F2R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F2R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R2 register  *******************/
-#define  CAN_F3R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F3R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F3R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F3R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F3R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F3R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F3R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F3R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F3R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F3R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F3R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F3R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F3R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F3R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F3R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F3R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F3R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F3R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F3R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F3R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F3R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F3R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F3R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F3R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F3R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F3R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F3R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F3R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F3R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F3R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F3R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F3R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R2 register  *******************/
-#define  CAN_F4R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F4R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F4R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F4R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F4R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F4R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F4R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F4R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F4R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F4R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F4R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F4R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F4R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F4R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F4R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F4R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F4R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F4R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F4R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F4R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F4R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F4R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F4R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F4R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F4R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F4R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F4R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F4R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F4R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F4R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F4R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F4R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R2 register  *******************/
-#define  CAN_F5R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F5R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F5R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F5R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F5R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F5R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F5R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F5R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F5R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F5R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F5R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F5R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F5R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F5R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F5R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F5R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F5R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F5R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F5R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F5R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F5R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F5R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F5R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F5R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F5R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F5R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F5R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F5R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F5R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F5R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F5R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F5R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R2 register  *******************/
-#define  CAN_F6R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F6R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F6R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F6R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F6R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F6R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F6R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F6R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F6R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F6R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F6R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F6R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F6R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F6R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F6R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F6R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F6R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F6R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F6R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F6R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F6R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F6R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F6R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F6R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F6R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F6R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F6R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F6R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F6R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F6R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F6R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F6R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R2 register  *******************/
-#define  CAN_F7R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F7R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F7R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F7R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F7R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F7R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F7R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F7R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F7R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F7R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F7R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F7R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F7R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F7R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F7R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F7R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F7R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F7R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F7R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F7R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F7R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F7R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F7R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F7R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F7R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F7R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F7R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F7R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F7R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F7R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F7R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F7R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R2 register  *******************/
-#define  CAN_F8R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F8R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F8R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F8R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F8R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F8R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F8R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F8R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F8R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F8R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F8R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F8R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F8R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F8R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F8R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F8R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F8R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F8R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F8R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F8R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F8R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F8R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F8R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F8R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F8R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F8R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F8R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F8R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F8R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F8R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F8R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F8R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R2 register  *******************/
-#define  CAN_F9R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F9R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F9R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F9R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F9R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F9R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F9R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F9R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F9R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F9R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F9R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F9R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F9R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F9R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F9R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F9R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F9R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F9R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F9R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F9R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F9R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F9R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F9R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F9R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F9R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F9R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F9R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F9R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F9R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F9R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F9R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F9R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R2 register  ******************/
-#define  CAN_F10R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F10R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F10R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F10R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F10R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F10R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F10R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F10R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F10R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F10R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F10R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F10R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F10R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F10R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F10R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F10R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F10R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F10R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F10R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F10R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F10R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F10R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F10R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F10R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F10R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F10R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F10R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F10R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F10R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F10R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F10R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F10R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R2 register  ******************/
-#define  CAN_F11R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F11R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F11R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F11R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F11R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F11R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F11R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F11R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F11R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F11R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F11R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F11R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F11R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F11R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F11R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F11R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F11R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F11R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F11R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F11R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F11R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F11R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F11R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F11R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F11R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F11R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F11R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F11R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F11R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F11R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F11R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F11R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R2 register  ******************/
-#define  CAN_F12R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F12R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F12R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F12R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F12R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F12R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F12R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F12R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F12R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F12R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F12R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F12R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F12R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F12R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F12R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F12R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F12R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F12R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F12R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F12R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F12R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F12R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F12R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F12R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F12R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F12R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F12R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F12R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F12R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F12R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F12R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F12R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R2 register  ******************/
-#define  CAN_F13R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F13R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F13R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F13R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F13R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F13R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F13R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F13R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F13R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F13R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F13R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F13R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F13R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F13R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F13R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F13R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F13R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F13R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F13R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F13R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F13R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F13R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F13R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F13R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F13R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F13R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F13R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F13R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F13R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F13R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F13R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F13R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRC calculation unit                              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           0xFFFFFFFFU /*!< Data register bits */
-
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         0xFFU        /*!< General-purpose 8-bit data register bits */
-
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        0x01U        /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 Debug MCU                                  */
-/*                                                                            */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                 Digital Filter for Sigma Delta Modulators                  */
-/*                                                                            */
-/******************************************************************************/
-
-/****************   DFSDM channel configuration registers  ********************/
-
-/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/
-#define  DFSDM_CHCFGR1_DFSDMEN                0x80000000U            /*!< Global enable for DFSDM interface */
-#define  DFSDM_CHCFGR1_CKOUTSRC               0x40000000U            /*!< Output serial clock source selection */
-#define  DFSDM_CHCFGR1_CKOUTDIV               0x00FF0000U            /*!< CKOUTDIV[7:0] output serial clock divider */
-#define  DFSDM_CHCFGR1_DATPACK                0x0000C000U            /*!< DATPACK[1:0] Data packing mode */
-#define  DFSDM_CHCFGR1_DATPACK_1              0x00008000U            /*!< Data packing mode, Bit 1 */
-#define  DFSDM_CHCFGR1_DATPACK_0              0x00004000U            /*!< Data packing mode, Bit 0 */
-#define  DFSDM_CHCFGR1_DATMPX                 0x00003000U            /*!< DATMPX[1:0] Input data multiplexer for channel y */
-#define  DFSDM_CHCFGR1_DATMPX_1               0x00002000U            /*!< Input data multiplexer for channel y, Bit 1 */
-#define  DFSDM_CHCFGR1_DATMPX_0               0x00001000U            /*!< Input data multiplexer for channel y, Bit 0 */
-#define  DFSDM_CHCFGR1_CHINSEL                0x00000100U            /*!< Serial inputs selection for channel y */
-#define  DFSDM_CHCFGR1_CHEN                   0x00000080U            /*!< Channel y enable */
-#define  DFSDM_CHCFGR1_CKABEN                 0x00000040U            /*!< Clock absence detector enable on channel y */
-#define  DFSDM_CHCFGR1_SCDEN                  0x00000020U            /*!< Short circuit detector enable on channel y */
-#define  DFSDM_CHCFGR1_SPICKSEL               0x0000000CU            /*!< SPICKSEL[1:0] SPI clock select for channel y */
-#define  DFSDM_CHCFGR1_SPICKSEL_1             0x00000008U            /*!< SPI clock select for channel y, Bit 1 */
-#define  DFSDM_CHCFGR1_SPICKSEL_0             0x00000004U            /*!< SPI clock select for channel y, Bit 0 */
-#define  DFSDM_CHCFGR1_SITP                   0x00000003U            /*!< SITP[1:0] Serial interface type for channel y */
-#define  DFSDM_CHCFGR1_SITP_1                 0x00000002U            /*!< Serial interface type for channel y, Bit 1 */
-#define  DFSDM_CHCFGR1_SITP_0                 0x00000001U            /*!< Serial interface type for channel y, Bit 0 */
-
-/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/
-#define  DFSDM_CHCFGR2_OFFSET                 0xFFFFFF00U            /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
-#define  DFSDM_CHCFGR2_DTRBS                  0x000000F8U            /*!< DTRBS[4:0] Data right bit-shift for channel y */
-
-/****************  Bit definition for DFSDM_CHAWSCDR register *****************/
-#define  DFSDM_CHAWSCDR_AWFORD                0x00C00000U            /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
-#define  DFSDM_CHAWSCDR_AWFORD_1              0x00800000U            /*!< Analog watchdog Sinc filter order on channel y, Bit 1 */
-#define  DFSDM_CHAWSCDR_AWFORD_0              0x00400000U            /*!< Analog watchdog Sinc filter order on channel y, Bit 0 */
-#define  DFSDM_CHAWSCDR_AWFOSR                0x001F0000U            /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
-#define  DFSDM_CHAWSCDR_BKSCD                 0x0000F000U            /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
-#define  DFSDM_CHAWSCDR_SCDT                  0x000000FFU            /*!< SCDT[7:0] Short circuit detector threshold for channel y */
-
-/****************  Bit definition for DFSDM_CHWDATR register *******************/
-#define  DFSDM_CHWDATR_WDATA                  0x0000FFFFU            /*!< WDATA[15:0] Input channel y watchdog data */
-
-/****************  Bit definition for DFSDM_CHDATINR register *****************/
-#define  DFSDM_CHDATINR_INDAT0                0x0000FFFFU            /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
-#define  DFSDM_CHDATINR_INDAT1                0xFFFF0000U            /*!< INDAT0[15:0] Input data for channel y */
-
-/************************   DFSDM module registers  ****************************/
-
-/*****************  Bit definition for DFSDM_FLTCR1 register *******************/
-#define  DFSDM_FLTCR1_AWFSEL                  0x40000000U            /*!< Analog watchdog fast mode select */
-#define  DFSDM_FLTCR1_FAST                    0x20000000U            /*!< Fast conversion mode selection */
-#define  DFSDM_FLTCR1_RCH                     0x07000000U            /*!< RCH[2:0] Regular channel selection */
-#define  DFSDM_FLTCR1_RDMAEN                  0x00200000U            /*!< DMA channel enabled to read data for the regular conversion */
-#define  DFSDM_FLTCR1_RSYNC                   0x00080000U            /*!< Launch regular conversion synchronously with DFSDMx */
-#define  DFSDM_FLTCR1_RCONT                   0x00040000U            /*!< Continuous mode selection for regular conversions */
-#define  DFSDM_FLTCR1_RSWSTART                0x00020000U            /*!< Software start of a conversion on the regular channel */
-#define  DFSDM_FLTCR1_JEXTEN                  0x00006000U            /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
-#define  DFSDM_FLTCR1_JEXTEN_1                0x00004000U            /*!< Trigger enable and trigger edge selection for injected conversions, Bit 1 */
-#define  DFSDM_FLTCR1_JEXTEN_0                0x00002000U            /*!< Trigger enable and trigger edge selection for injected conversions, Bit 0 */
-#define  DFSDM_FLTCR1_JEXTSEL                 0x00000700U            /*!< JEXTSEL[2:0]Trigger signal selection for launching injected conversions */
-#define  DFSDM_FLTCR1_JEXTSEL_2               0x00000400U            /*!< Trigger signal selection for launching injected conversions, Bit 2 */
-#define  DFSDM_FLTCR1_JEXTSEL_1               0x00000200U            /*!< Trigger signal selection for launching injected conversions, Bit 1 */
-#define  DFSDM_FLTCR1_JEXTSEL_0               0x00000100U            /*!< Trigger signal selection for launching injected conversions, Bit 0 */
-#define  DFSDM_FLTCR1_JDMAEN                  0x00000020U            /*!< DMA channel enabled to read data for the injected channel group */
-#define  DFSDM_FLTCR1_JSCAN                   0x00000010U            /*!< Scanning conversion in continuous mode selection for injected conversions */
-#define  DFSDM_FLTCR1_JSYNC                   0x00000008U            /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */
-#define  DFSDM_FLTCR1_JSWSTART                0x00000002U            /*!< Start the conversion of the injected group of channels */
-#define  DFSDM_FLTCR1_DFEN                    0x00000001U            /*!< DFSDM enable */
-
-/*****************  Bit definition for DFSDM_FLTCR2 register *******************/
-#define  DFSDM_FLTCR2_AWDCH                   0x000F0000U            /*!< AWDCH[7:0] Analog watchdog channel selection */
-#define  DFSDM_FLTCR2_EXCH                    0x00000F00U            /*!< EXCH[7:0] Extreme detector channel selection */
-#define  DFSDM_FLTCR2_CKABIE                  0x00000040U            /*!< Clock absence interrupt enable */
-#define  DFSDM_FLTCR2_SCDIE                   0x00000020U            /*!< Short circuit detector interrupt enable */
-#define  DFSDM_FLTCR2_AWDIE                   0x00000010U            /*!< Analog watchdog interrupt enable */
-#define  DFSDM_FLTCR2_ROVRIE                  0x00000008U            /*!< Regular data overrun interrupt enable */
-#define  DFSDM_FLTCR2_JOVRIE                  0x00000004U            /*!< Injected data overrun interrupt enable */
-#define  DFSDM_FLTCR2_REOCIE                  0x00000002U            /*!< Regular end of conversion interrupt enable */
-#define  DFSDM_FLTCR2_JEOCIE                  0x00000001U            /*!< Injected end of conversion interrupt enable */
-
-/*****************  Bit definition for DFSDM_FLTISR register *******************/
-#define  DFSDM_FLTISR_SCDF                    0x0F000000U            /*!< SCDF[7:0] Short circuit detector flag */
-#define  DFSDM_FLTISR_CKABF                   0x000F0000U            /*!< CKABF[7:0] Clock absence flag */
-#define  DFSDM_FLTISR_RCIP                    0x00004000U            /*!< Regular conversion in progress status */
-#define  DFSDM_FLTISR_JCIP                    0x00002000U            /*!< Injected conversion in progress status */
-#define  DFSDM_FLTISR_AWDF                    0x00000010U            /*!< Analog watchdog */
-#define  DFSDM_FLTISR_ROVRF                   0x00000008U            /*!< Regular conversion overrun flag */
-#define  DFSDM_FLTISR_JOVRF                   0x00000004U            /*!< Injected conversion overrun flag */
-#define  DFSDM_FLTISR_REOCF                   0x00000002U            /*!< End of regular conversion flag */
-#define  DFSDM_FLTISR_JEOCF                   0x00000001U            /*!< End of injected conversion flag */
-
-/*****************  Bit definition for DFSDM_FLTICR register *******************/
-#define  DFSDM_FLTICR_CLRSCSDF                0x0F000000U            /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
-#define  DFSDM_FLTICR_CLRCKABF                0x000F0000U            /*!< CLRCKABF[7:0] Clear the clock absence flag */
-#define  DFSDM_FLTICR_CLRROVRF                0x00000008U            /*!< Clear the regular conversion overrun flag */
-#define  DFSDM_FLTICR_CLRJOVRF                0x00000004U            /*!< Clear the injected conversion overrun flag */
-
-/****************  Bit definition for DFSDM_FLTJCHGR register ******************/
-#define  DFSDM_FLTJCHGR_JCHG                  0x0000000FU            /*!< JCHG[7:0] Injected channel group selection */
-
-/*****************  Bit definition for DFSDM_FLTFCR register *******************/
-#define  DFSDM_FLTFCR_FORD                    0xE0000000U            /*!< FORD[2:0] Sinc filter order */
-#define  DFSDM_FLTFCR_FORD_2                  0x80000000U            /*!< Sinc filter order, Bit 2 */
-#define  DFSDM_FLTFCR_FORD_1                  0x40000000U            /*!< Sinc filter order, Bit 1 */
-#define  DFSDM_FLTFCR_FORD_0                  0x20000000U            /*!< Sinc filter order, Bit 0 */
-#define  DFSDM_FLTFCR_FOSR                    0x03FF0000U            /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
-#define  DFSDM_FLTFCR_IOSR                    0x000000FFU            /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
-
-/***************  Bit definition for DFSDM_FLTJDATAR register *****************/
-#define  DFSDM_FLTJDATAR_JDATA                0xFFFFFF00U            /*!< JDATA[23:0] Injected group conversion data */
-#define  DFSDM_FLTJDATAR_JDATACH              0x00000007U            /*!< JDATACH[2:0] Injected channel most recently converted */
-
-/***************  Bit definition for DFSDM_FLTRDATAR register *****************/
-#define  DFSDM_FLTRDATAR_RDATA                0xFFFFFF00U            /*!< RDATA[23:0] Regular channel conversion data */
-#define  DFSDM_FLTRDATAR_RPEND                0x00000010U            /*!< RPEND Regular channel pending data */
-#define  DFSDM_FLTRDATAR_RDATACH              0x00000007U            /*!< RDATACH[2:0] Regular channel most recently converted */
-
-/***************  Bit definition for DFSDM_FLTAWHTR register ******************/
-#define  DFSDM_FLTAWHTR_AWHT                 0xFFFFFF00U             /*!< AWHT[23:0] Analog watchdog high threshold */
-#define  DFSDM_FLTAWHTR_BKAWH                0x0000000FU             /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
-
-/***************  Bit definition for DFSDM_FLTAWLTR register ******************/
-#define  DFSDM_FLTAWLTR_AWLT                 0xFFFFFF00U             /*!< AWLT[23:0] Analog watchdog low threshold */
-#define  DFSDM_FLTAWLTR_BKAWL                0x0000000FU             /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
-
-/***************  Bit definition for DFSDM_FLTAWSR register *******************/
-#define  DFSDM_FLTAWSR_AWHTF                 0x00000F00U             /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
-#define  DFSDM_FLTAWSR_AWLTF                 0x0000000FU             /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
-
-/***************  Bit definition for DFSDM_FLTAWCFR register ******************/
-#define  DFSDM_FLTAWCFR_CLRAWHTF             0x00000F00U             /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
-#define  DFSDM_FLTAWCFR_CLRAWLTF             0x0000000FU             /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
-
-/***************  Bit definition for DFSDM_FLTEXMAX register ******************/
-#define  DFSDM_FLTEXMAX_EXMAX                0xFFFFFF00U             /*!< EXMAX[23:0] Extreme detector maximum value */
-#define  DFSDM_FLTEXMAX_EXMAXCH              0x00000007U             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
-
-/***************  Bit definition for DFSDM_FLTEXMIN register ******************/
-#define  DFSDM_FLTEXMIN_EXMIN                0xFFFFFF00U             /*!< EXMIN[23:0] Extreme detector minimum value */
-#define  DFSDM_FLTEXMIN_EXMINCH              0x00000007U             /*!< EXMINCH[2:0] Extreme detector minimum data channel */
-
-/***************  Bit definition for DFSDM_FLTCNVTIMR register ****************/
-#define  DFSDM_FLTCNVTIMR_CNVCNT             0xFFFFFFF0U             /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
-
-/******************************************************************************/
-/*                                                                            */
-/*                             DMA Controller                                 */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DMA_SxCR register  *****************/ 
-#define DMA_SxCR_CHSEL                       0x0E000000U
-#define DMA_SxCR_CHSEL_0                     0x02000000U
-#define DMA_SxCR_CHSEL_1                     0x04000000U
-#define DMA_SxCR_CHSEL_2                     0x08000000U
-#define DMA_SxCR_MBURST                      0x01800000U
-#define DMA_SxCR_MBURST_0                    0x00800000U
-#define DMA_SxCR_MBURST_1                    0x01000000U
-#define DMA_SxCR_PBURST                      0x00600000U
-#define DMA_SxCR_PBURST_0                    0x00200000U
-#define DMA_SxCR_PBURST_1                    0x00400000U
-#define DMA_SxCR_CT                          0x00080000U
-#define DMA_SxCR_DBM                         0x00040000U
-#define DMA_SxCR_PL                          0x00030000U
-#define DMA_SxCR_PL_0                        0x00010000U
-#define DMA_SxCR_PL_1                        0x00020000U
-#define DMA_SxCR_PINCOS                      0x00008000U
-#define DMA_SxCR_MSIZE                       0x00006000U
-#define DMA_SxCR_MSIZE_0                     0x00002000U
-#define DMA_SxCR_MSIZE_1                     0x00004000U
-#define DMA_SxCR_PSIZE                       0x00001800U
-#define DMA_SxCR_PSIZE_0                     0x00000800U
-#define DMA_SxCR_PSIZE_1                     0x00001000U
-#define DMA_SxCR_MINC                        0x00000400U
-#define DMA_SxCR_PINC                        0x00000200U
-#define DMA_SxCR_CIRC                        0x00000100U
-#define DMA_SxCR_DIR                         0x000000C0U
-#define DMA_SxCR_DIR_0                       0x00000040U
-#define DMA_SxCR_DIR_1                       0x00000080U
-#define DMA_SxCR_PFCTRL                      0x00000020U
-#define DMA_SxCR_TCIE                        0x00000010U
-#define DMA_SxCR_HTIE                        0x00000008U
-#define DMA_SxCR_TEIE                        0x00000004U
-#define DMA_SxCR_DMEIE                       0x00000002U
-#define DMA_SxCR_EN                          0x00000001U
-
-/* Legacy defines */
-#define DMA_SxCR_ACK                         0x00100000U
-
-/********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            0x0000FFFFU
-#define DMA_SxNDT_0                          0x00000001U
-#define DMA_SxNDT_1                          0x00000002U
-#define DMA_SxNDT_2                          0x00000004U
-#define DMA_SxNDT_3                          0x00000008U
-#define DMA_SxNDT_4                          0x00000010U
-#define DMA_SxNDT_5                          0x00000020U
-#define DMA_SxNDT_6                          0x00000040U
-#define DMA_SxNDT_7                          0x00000080U
-#define DMA_SxNDT_8                          0x00000100U
-#define DMA_SxNDT_9                          0x00000200U
-#define DMA_SxNDT_10                         0x00000400U
-#define DMA_SxNDT_11                         0x00000800U
-#define DMA_SxNDT_12                         0x00001000U
-#define DMA_SxNDT_13                         0x00002000U
-#define DMA_SxNDT_14                         0x00004000U
-#define DMA_SxNDT_15                         0x00008000U
-
-/********************  Bits definition for DMA_SxFCR register  ****************/ 
-#define DMA_SxFCR_FEIE                       0x00000080U
-#define DMA_SxFCR_FS                         0x00000038U
-#define DMA_SxFCR_FS_0                       0x00000008U
-#define DMA_SxFCR_FS_1                       0x00000010U
-#define DMA_SxFCR_FS_2                       0x00000020U
-#define DMA_SxFCR_DMDIS                      0x00000004U
-#define DMA_SxFCR_FTH                        0x00000003U
-#define DMA_SxFCR_FTH_0                      0x00000001U
-#define DMA_SxFCR_FTH_1                      0x00000002U
-
-/********************  Bits definition for DMA_LISR register  *****************/ 
-#define DMA_LISR_TCIF3                       0x08000000U
-#define DMA_LISR_HTIF3                       0x04000000U
-#define DMA_LISR_TEIF3                       0x02000000U
-#define DMA_LISR_DMEIF3                      0x01000000U
-#define DMA_LISR_FEIF3                       0x00400000U
-#define DMA_LISR_TCIF2                       0x00200000U
-#define DMA_LISR_HTIF2                       0x00100000U
-#define DMA_LISR_TEIF2                       0x00080000U
-#define DMA_LISR_DMEIF2                      0x00040000U
-#define DMA_LISR_FEIF2                       0x00010000U
-#define DMA_LISR_TCIF1                       0x00000800U
-#define DMA_LISR_HTIF1                       0x00000400U
-#define DMA_LISR_TEIF1                       0x00000200U
-#define DMA_LISR_DMEIF1                      0x00000100U
-#define DMA_LISR_FEIF1                       0x00000040U
-#define DMA_LISR_TCIF0                       0x00000020U
-#define DMA_LISR_HTIF0                       0x00000010U
-#define DMA_LISR_TEIF0                       0x00000008U
-#define DMA_LISR_DMEIF0                      0x00000004U
-#define DMA_LISR_FEIF0                       0x00000001U
-
-/********************  Bits definition for DMA_HISR register  *****************/ 
-#define DMA_HISR_TCIF7                       0x08000000U
-#define DMA_HISR_HTIF7                       0x04000000U
-#define DMA_HISR_TEIF7                       0x02000000U
-#define DMA_HISR_DMEIF7                      0x01000000U
-#define DMA_HISR_FEIF7                       0x00400000U
-#define DMA_HISR_TCIF6                       0x00200000U
-#define DMA_HISR_HTIF6                       0x00100000U
-#define DMA_HISR_TEIF6                       0x00080000U
-#define DMA_HISR_DMEIF6                      0x00040000U
-#define DMA_HISR_FEIF6                       0x00010000U
-#define DMA_HISR_TCIF5                       0x00000800U
-#define DMA_HISR_HTIF5                       0x00000400U
-#define DMA_HISR_TEIF5                       0x00000200U
-#define DMA_HISR_DMEIF5                      0x00000100U
-#define DMA_HISR_FEIF5                       0x00000040U
-#define DMA_HISR_TCIF4                       0x00000020U
-#define DMA_HISR_HTIF4                       0x00000010U
-#define DMA_HISR_TEIF4                       0x00000008U
-#define DMA_HISR_DMEIF4                      0x00000004U
-#define DMA_HISR_FEIF4                       0x00000001U
-
-/********************  Bits definition for DMA_LIFCR register  ****************/ 
-#define DMA_LIFCR_CTCIF3                     0x08000000U
-#define DMA_LIFCR_CHTIF3                     0x04000000U
-#define DMA_LIFCR_CTEIF3                     0x02000000U
-#define DMA_LIFCR_CDMEIF3                    0x01000000U
-#define DMA_LIFCR_CFEIF3                     0x00400000U
-#define DMA_LIFCR_CTCIF2                     0x00200000U
-#define DMA_LIFCR_CHTIF2                     0x00100000U
-#define DMA_LIFCR_CTEIF2                     0x00080000U
-#define DMA_LIFCR_CDMEIF2                    0x00040000U
-#define DMA_LIFCR_CFEIF2                     0x00010000U
-#define DMA_LIFCR_CTCIF1                     0x00000800U
-#define DMA_LIFCR_CHTIF1                     0x00000400U
-#define DMA_LIFCR_CTEIF1                     0x00000200U
-#define DMA_LIFCR_CDMEIF1                    0x00000100U
-#define DMA_LIFCR_CFEIF1                     0x00000040U
-#define DMA_LIFCR_CTCIF0                     0x00000020U
-#define DMA_LIFCR_CHTIF0                     0x00000010U
-#define DMA_LIFCR_CTEIF0                     0x00000008U
-#define DMA_LIFCR_CDMEIF0                    0x00000004U
-#define DMA_LIFCR_CFEIF0                     0x00000001U
-
-/********************  Bits definition for DMA_HIFCR  register  ****************/ 
-#define DMA_HIFCR_CTCIF7                     0x08000000U
-#define DMA_HIFCR_CHTIF7                     0x04000000U
-#define DMA_HIFCR_CTEIF7                     0x02000000U
-#define DMA_HIFCR_CDMEIF7                    0x01000000U
-#define DMA_HIFCR_CFEIF7                     0x00400000U
-#define DMA_HIFCR_CTCIF6                     0x00200000U
-#define DMA_HIFCR_CHTIF6                     0x00100000U
-#define DMA_HIFCR_CTEIF6                     0x00080000U
-#define DMA_HIFCR_CDMEIF6                    0x00040000U
-#define DMA_HIFCR_CFEIF6                     0x00010000U
-#define DMA_HIFCR_CTCIF5                     0x00000800U
-#define DMA_HIFCR_CHTIF5                     0x00000400U
-#define DMA_HIFCR_CTEIF5                     0x00000200U
-#define DMA_HIFCR_CDMEIF5                    0x00000100U
-#define DMA_HIFCR_CFEIF5                     0x00000040U
-#define DMA_HIFCR_CTCIF4                     0x00000020U
-#define DMA_HIFCR_CHTIF4                     0x00000010U
-#define DMA_HIFCR_CTEIF4                     0x00000008U
-#define DMA_HIFCR_CDMEIF4                    0x00000004U
-#define DMA_HIFCR_CFEIF4                     0x00000001U
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                    External Interrupt/Event Controller                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    FLASH                                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    0x0000000FU
-#define FLASH_ACR_LATENCY_0WS                0x00000000U
-#define FLASH_ACR_LATENCY_1WS                0x00000001U
-#define FLASH_ACR_LATENCY_2WS                0x00000002U
-#define FLASH_ACR_LATENCY_3WS                0x00000003U
-#define FLASH_ACR_LATENCY_4WS                0x00000004U
-#define FLASH_ACR_LATENCY_5WS                0x00000005U
-#define FLASH_ACR_LATENCY_6WS                0x00000006U
-#define FLASH_ACR_LATENCY_7WS                0x00000007U
-
-#define FLASH_ACR_PRFTEN                     0x00000100U
-#define FLASH_ACR_ICEN                       0x00000200U
-#define FLASH_ACR_DCEN                       0x00000400U
-#define FLASH_ACR_ICRST                      0x00000800U
-#define FLASH_ACR_DCRST                      0x00001000U
-#define FLASH_ACR_BYTE0_ADDRESS              0x40023C00U
-#define FLASH_ACR_BYTE2_ADDRESS              0x40023C03U
-
-/*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         0x00000001U
-#define FLASH_SR_SOP                         0x00000002U
-#define FLASH_SR_WRPERR                      0x00000010U
-#define FLASH_SR_PGAERR                      0x00000020U
-#define FLASH_SR_PGPERR                      0x00000040U
-#define FLASH_SR_PGSERR                      0x00000080U
-#define FLASH_SR_BSY                         0x00010000U
-
-/*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          0x00000001U
-#define FLASH_CR_SER                         0x00000002U
-#define FLASH_CR_MER                         0x00000004U
-#define FLASH_CR_SNB                         0x000000F8U
-#define FLASH_CR_SNB_0                       0x00000008U
-#define FLASH_CR_SNB_1                       0x00000010U
-#define FLASH_CR_SNB_2                       0x00000020U
-#define FLASH_CR_SNB_3                       0x00000040U
-#define FLASH_CR_SNB_4                       0x00000080U
-#define FLASH_CR_PSIZE                       0x00000300U
-#define FLASH_CR_PSIZE_0                     0x00000100U
-#define FLASH_CR_PSIZE_1                     0x00000200U
-#define FLASH_CR_STRT                        0x00010000U
-#define FLASH_CR_EOPIE                       0x01000000U
-#define FLASH_CR_LOCK                        0x80000000U
-
-/*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                 0x00000001U
-#define FLASH_OPTCR_OPTSTRT                 0x00000002U
-#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
-#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
-#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
-
-#define FLASH_OPTCR_WDG_SW                  0x00000020U
-#define FLASH_OPTCR_nRST_STOP               0x00000040U
-#define FLASH_OPTCR_nRST_STDBY              0x00000080U
-#define FLASH_OPTCR_RDP                     0x0000FF00U
-#define FLASH_OPTCR_RDP_0                   0x00000100U
-#define FLASH_OPTCR_RDP_1                   0x00000200U
-#define FLASH_OPTCR_RDP_2                   0x00000400U
-#define FLASH_OPTCR_RDP_3                   0x00000800U
-#define FLASH_OPTCR_RDP_4                   0x00001000U
-#define FLASH_OPTCR_RDP_5                   0x00002000U
-#define FLASH_OPTCR_RDP_6                   0x00004000U
-#define FLASH_OPTCR_RDP_7                   0x00008000U
-#define FLASH_OPTCR_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR_nWRP_0                  0x00010000U
-#define FLASH_OPTCR_nWRP_1                  0x00020000U
-#define FLASH_OPTCR_nWRP_2                  0x00040000U
-#define FLASH_OPTCR_nWRP_3                  0x00080000U
-#define FLASH_OPTCR_nWRP_4                  0x00100000U
-#define FLASH_OPTCR_nWRP_5                  0x00200000U
-#define FLASH_OPTCR_nWRP_6                  0x00400000U
-#define FLASH_OPTCR_nWRP_7                  0x00800000U
-#define FLASH_OPTCR_nWRP_8                  0x01000000U
-#define FLASH_OPTCR_nWRP_9                  0x02000000U
-#define FLASH_OPTCR_nWRP_10                 0x04000000U
-#define FLASH_OPTCR_nWRP_11                 0x08000000U
-                                             
-/******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR1_nWRP_0                  0x00010000U
-#define FLASH_OPTCR1_nWRP_1                  0x00020000U
-#define FLASH_OPTCR1_nWRP_2                  0x00040000U
-#define FLASH_OPTCR1_nWRP_3                  0x00080000U
-#define FLASH_OPTCR1_nWRP_4                  0x00100000U
-#define FLASH_OPTCR1_nWRP_5                  0x00200000U
-#define FLASH_OPTCR1_nWRP_6                  0x00400000U
-#define FLASH_OPTCR1_nWRP_7                  0x00800000U
-#define FLASH_OPTCR1_nWRP_8                  0x01000000U
-#define FLASH_OPTCR1_nWRP_9                  0x02000000U
-#define FLASH_OPTCR1_nWRP_10                 0x04000000U
-#define FLASH_OPTCR1_nWRP_11                 0x08000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Flexible Static Memory Controller                        */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for FSMC_BCR1 register  *******************/
-#define  FSMC_BCR1_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FSMC_BCR1_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FSMC_BCR1_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FSMC_BCR1_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FSMC_BCR1_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FSMC_BCR1_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR1_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FSMC_BCR1_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FSMC_BCR1_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FSMC_BCR1_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FSMC_BCR1_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FSMC_BCR1_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FSMC_BCR1_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FSMC_BCR1_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FSMC_BCR1_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FSMC_BCR1_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FSMC_BCR1_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FSMC_BCR1_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FSMC_BCR1_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FSMC_BCR1_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FSMC_BCR1_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-#define  FSMC_BCR1_CCLKEN                    0x00100000U        /*!<Continous clock enable     */
-#define  FSMC_BCR1_WFDIS                     0x00200000U        /*!<Write FIFO Disable         */
-
-/******************  Bit definition for FSMC_BCR2 register  *******************/
-#define  FSMC_BCR2_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FSMC_BCR2_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FSMC_BCR2_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FSMC_BCR2_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FSMC_BCR2_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FSMC_BCR2_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR2_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FSMC_BCR2_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FSMC_BCR2_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FSMC_BCR2_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FSMC_BCR2_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FSMC_BCR2_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FSMC_BCR2_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FSMC_BCR2_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FSMC_BCR2_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FSMC_BCR2_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FSMC_BCR2_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FSMC_BCR2_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FSMC_BCR2_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FSMC_BCR2_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FSMC_BCR2_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FSMC_BCR3 register  *******************/
-#define  FSMC_BCR3_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FSMC_BCR3_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FSMC_BCR3_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FSMC_BCR3_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FSMC_BCR3_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FSMC_BCR3_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR3_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FSMC_BCR3_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FSMC_BCR3_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FSMC_BCR3_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FSMC_BCR3_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FSMC_BCR3_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FSMC_BCR3_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FSMC_BCR3_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FSMC_BCR3_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FSMC_BCR3_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FSMC_BCR3_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FSMC_BCR3_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FSMC_BCR3_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FSMC_BCR3_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FSMC_BCR3_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FSMC_BCR4 register  *******************/
-#define  FSMC_BCR4_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FSMC_BCR4_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FSMC_BCR4_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FSMC_BCR4_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FSMC_BCR4_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FSMC_BCR4_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR4_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FSMC_BCR4_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FSMC_BCR4_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FSMC_BCR4_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FSMC_BCR4_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FSMC_BCR4_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FSMC_BCR4_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FSMC_BCR4_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FSMC_BCR4_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FSMC_BCR4_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FSMC_BCR4_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FSMC_BCR4_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FSMC_BCR4_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FSMC_BCR4_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FSMC_BCR4_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FSMC_BTR1 register  ******************/
-#define  FSMC_BTR1_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR1_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FSMC_BTR1_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FSMC_BTR1_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FSMC_BTR1_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BTR1_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
-#define  FSMC_BTR1_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FSMC_BTR1_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FSMC_BTR1_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FSMC_BTR1_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BTR1_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BTR1_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FSMC_BTR1_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FSMC_BTR1_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FSMC_BTR1_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FSMC_BTR1_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FSMC_BTR1_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FSMC_BTR1_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FSMC_BTR1_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BTR1_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR1_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FSMC_BTR1_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FSMC_BTR1_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FSMC_BTR1_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BTR1_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR1_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FSMC_BTR1_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FSMC_BTR1_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FSMC_BTR1_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FSMC_BTR1_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR1_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FSMC_BTR1_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FSMC_BTR1_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FSMC_BTR1_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FSMC_BTR1_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR1_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FSMC_BTR1_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BTR2 register  *******************/
-#define  FSMC_BTR2_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR2_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FSMC_BTR2_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FSMC_BTR2_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FSMC_BTR2_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BTR2_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR2_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FSMC_BTR2_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FSMC_BTR2_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FSMC_BTR2_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BTR2_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BTR2_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FSMC_BTR2_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FSMC_BTR2_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FSMC_BTR2_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FSMC_BTR2_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FSMC_BTR2_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FSMC_BTR2_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FSMC_BTR2_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BTR2_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR2_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FSMC_BTR2_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FSMC_BTR2_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FSMC_BTR2_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BTR2_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR2_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FSMC_BTR2_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FSMC_BTR2_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FSMC_BTR2_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FSMC_BTR2_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR2_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FSMC_BTR2_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FSMC_BTR2_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FSMC_BTR2_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FSMC_BTR2_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR2_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FSMC_BTR2_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/*******************  Bit definition for FSMC_BTR3 register  *******************/
-#define  FSMC_BTR3_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR3_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FSMC_BTR3_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FSMC_BTR3_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FSMC_BTR3_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BTR3_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR3_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FSMC_BTR3_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FSMC_BTR3_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FSMC_BTR3_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BTR3_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BTR3_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FSMC_BTR3_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FSMC_BTR3_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FSMC_BTR3_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FSMC_BTR3_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FSMC_BTR3_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FSMC_BTR3_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FSMC_BTR3_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BTR3_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR3_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FSMC_BTR3_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FSMC_BTR3_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FSMC_BTR3_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BTR3_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR3_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FSMC_BTR3_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FSMC_BTR3_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FSMC_BTR3_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FSMC_BTR3_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR3_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FSMC_BTR3_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FSMC_BTR3_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FSMC_BTR3_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FSMC_BTR3_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR3_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FSMC_BTR3_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BTR4 register  *******************/
-#define  FSMC_BTR4_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR4_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FSMC_BTR4_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FSMC_BTR4_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FSMC_BTR4_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BTR4_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR4_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FSMC_BTR4_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FSMC_BTR4_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FSMC_BTR4_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BTR4_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BTR4_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FSMC_BTR4_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FSMC_BTR4_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FSMC_BTR4_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FSMC_BTR4_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FSMC_BTR4_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FSMC_BTR4_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FSMC_BTR4_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BTR4_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR4_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FSMC_BTR4_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FSMC_BTR4_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FSMC_BTR4_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BTR4_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR4_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FSMC_BTR4_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FSMC_BTR4_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FSMC_BTR4_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FSMC_BTR4_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR4_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FSMC_BTR4_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FSMC_BTR4_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FSMC_BTR4_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FSMC_BTR4_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR4_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FSMC_BTR4_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR1 register  ******************/
-#define  FSMC_BWTR1_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR1_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FSMC_BWTR1_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FSMC_BWTR1_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FSMC_BWTR1_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BWTR1_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR1_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FSMC_BWTR1_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FSMC_BWTR1_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FSMC_BWTR1_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BWTR1_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BWTR1_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FSMC_BWTR1_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FSMC_BWTR1_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FSMC_BWTR1_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FSMC_BWTR1_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FSMC_BWTR1_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FSMC_BWTR1_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FSMC_BWTR1_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BWTR1_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FSMC_BWTR1_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FSMC_BWTR1_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FSMC_BWTR1_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FSMC_BWTR1_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BWTR1_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR1_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FSMC_BWTR1_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR2 register  ******************/
-#define  FSMC_BWTR2_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR2_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FSMC_BWTR2_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FSMC_BWTR2_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FSMC_BWTR2_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BWTR2_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR2_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FSMC_BWTR2_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FSMC_BWTR2_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FSMC_BWTR2_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BWTR2_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BWTR2_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FSMC_BWTR2_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FSMC_BWTR2_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FSMC_BWTR2_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FSMC_BWTR2_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FSMC_BWTR2_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FSMC_BWTR2_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FSMC_BWTR2_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BWTR2_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FSMC_BWTR2_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FSMC_BWTR2_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FSMC_BWTR2_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FSMC_BWTR2_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BWTR2_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR2_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FSMC_BWTR2_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR3 register  ******************/
-#define  FSMC_BWTR3_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR3_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FSMC_BWTR3_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FSMC_BWTR3_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FSMC_BWTR3_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BWTR3_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR3_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FSMC_BWTR3_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FSMC_BWTR3_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FSMC_BWTR3_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BWTR3_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BWTR3_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FSMC_BWTR3_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FSMC_BWTR3_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FSMC_BWTR3_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FSMC_BWTR3_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FSMC_BWTR3_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FSMC_BWTR3_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FSMC_BWTR3_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BWTR3_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FSMC_BWTR3_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FSMC_BWTR3_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FSMC_BWTR3_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FSMC_BWTR3_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BWTR3_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR3_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FSMC_BWTR3_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR4 register  ******************/
-#define  FSMC_BWTR4_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR4_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FSMC_BWTR4_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FSMC_BWTR4_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FSMC_BWTR4_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BWTR4_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR4_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FSMC_BWTR4_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FSMC_BWTR4_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FSMC_BWTR4_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BWTR4_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BWTR4_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FSMC_BWTR4_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FSMC_BWTR4_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FSMC_BWTR4_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FSMC_BWTR4_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FSMC_BWTR4_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FSMC_BWTR4_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FSMC_BWTR4_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BWTR4_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FSMC_BWTR4_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FSMC_BWTR4_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FSMC_BWTR4_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FSMC_BWTR4_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BWTR4_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR4_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FSMC_BWTR4_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    0x00000003U
-#define GPIO_MODER_MODER0_0                  0x00000001U
-#define GPIO_MODER_MODER0_1                  0x00000002U
-
-#define GPIO_MODER_MODER1                    0x0000000CU
-#define GPIO_MODER_MODER1_0                  0x00000004U
-#define GPIO_MODER_MODER1_1                  0x00000008U
-
-#define GPIO_MODER_MODER2                    0x00000030U
-#define GPIO_MODER_MODER2_0                  0x00000010U
-#define GPIO_MODER_MODER2_1                  0x00000020U
-
-#define GPIO_MODER_MODER3                    0x000000C0U
-#define GPIO_MODER_MODER3_0                  0x00000040U
-#define GPIO_MODER_MODER3_1                  0x00000080U
-
-#define GPIO_MODER_MODER4                    0x00000300U
-#define GPIO_MODER_MODER4_0                  0x00000100U
-#define GPIO_MODER_MODER4_1                  0x00000200U
-
-#define GPIO_MODER_MODER5                    0x00000C00U
-#define GPIO_MODER_MODER5_0                  0x00000400U
-#define GPIO_MODER_MODER5_1                  0x00000800U
-
-#define GPIO_MODER_MODER6                    0x00003000U
-#define GPIO_MODER_MODER6_0                  0x00001000U
-#define GPIO_MODER_MODER6_1                  0x00002000U
-
-#define GPIO_MODER_MODER7                    0x0000C000U
-#define GPIO_MODER_MODER7_0                  0x00004000U
-#define GPIO_MODER_MODER7_1                  0x00008000U
-
-#define GPIO_MODER_MODER8                    0x00030000U
-#define GPIO_MODER_MODER8_0                  0x00010000U
-#define GPIO_MODER_MODER8_1                  0x00020000U
-
-#define GPIO_MODER_MODER9                    0x000C0000U
-#define GPIO_MODER_MODER9_0                  0x00040000U
-#define GPIO_MODER_MODER9_1                  0x00080000U
-
-#define GPIO_MODER_MODER10                   0x00300000U
-#define GPIO_MODER_MODER10_0                 0x00100000U
-#define GPIO_MODER_MODER10_1                 0x00200000U
-
-#define GPIO_MODER_MODER11                   0x00C00000U
-#define GPIO_MODER_MODER11_0                 0x00400000U
-#define GPIO_MODER_MODER11_1                 0x00800000U
-
-#define GPIO_MODER_MODER12                   0x03000000U
-#define GPIO_MODER_MODER12_0                 0x01000000U
-#define GPIO_MODER_MODER12_1                 0x02000000U
-
-#define GPIO_MODER_MODER13                   0x0C000000U
-#define GPIO_MODER_MODER13_0                 0x04000000U
-#define GPIO_MODER_MODER13_1                 0x08000000U
-
-#define GPIO_MODER_MODER14                   0x30000000U
-#define GPIO_MODER_MODER14_0                 0x10000000U
-#define GPIO_MODER_MODER14_1                 0x20000000U
-
-#define GPIO_MODER_MODER15                   0xC0000000U
-#define GPIO_MODER_MODER15_0                 0x40000000U
-#define GPIO_MODER_MODER15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     0x00000001U
-#define GPIO_OTYPER_OT_1                     0x00000002U
-#define GPIO_OTYPER_OT_2                     0x00000004U
-#define GPIO_OTYPER_OT_3                     0x00000008U
-#define GPIO_OTYPER_OT_4                     0x00000010U
-#define GPIO_OTYPER_OT_5                     0x00000020U
-#define GPIO_OTYPER_OT_6                     0x00000040U
-#define GPIO_OTYPER_OT_7                     0x00000080U
-#define GPIO_OTYPER_OT_8                     0x00000100U
-#define GPIO_OTYPER_OT_9                     0x00000200U
-#define GPIO_OTYPER_OT_10                    0x00000400U
-#define GPIO_OTYPER_OT_11                    0x00000800U
-#define GPIO_OTYPER_OT_12                    0x00001000U
-#define GPIO_OTYPER_OT_13                    0x00002000U
-#define GPIO_OTYPER_OT_14                    0x00004000U
-#define GPIO_OTYPER_OT_15                    0x00008000U
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
-#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
-#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
-
-#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
-#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
-#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
-
-#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
-#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
-#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
-
-#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
-#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
-#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
-
-#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
-#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
-#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
-
-#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
-#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
-#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
-
-#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
-#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
-#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
-
-#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
-#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
-#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
-
-#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
-#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
-#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
-
-#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
-#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
-#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
-
-#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
-#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
-#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
-
-#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
-#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
-#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
-
-#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
-#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
-#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
-
-#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
-#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
-#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
-
-#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
-#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
-#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
-
-#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
-#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
-#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    0x00000003U
-#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
-#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
-
-#define GPIO_PUPDR_PUPDR1                    0x0000000CU
-#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
-#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
-
-#define GPIO_PUPDR_PUPDR2                    0x00000030U
-#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
-#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
-
-#define GPIO_PUPDR_PUPDR3                    0x000000C0U
-#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
-#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
-
-#define GPIO_PUPDR_PUPDR4                    0x00000300U
-#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
-#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
-
-#define GPIO_PUPDR_PUPDR5                    0x00000C00U
-#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
-#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
-
-#define GPIO_PUPDR_PUPDR6                    0x00003000U
-#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
-#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
-
-#define GPIO_PUPDR_PUPDR7                    0x0000C000U
-#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
-#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
-
-#define GPIO_PUPDR_PUPDR8                    0x00030000U
-#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
-#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
-
-#define GPIO_PUPDR_PUPDR9                    0x000C0000U
-#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
-#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
-
-#define GPIO_PUPDR_PUPDR10                   0x00300000U
-#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
-#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
-
-#define GPIO_PUPDR_PUPDR11                   0x00C00000U
-#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
-#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
-
-#define GPIO_PUPDR_PUPDR12                   0x03000000U
-#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
-#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
-
-#define GPIO_PUPDR_PUPDR13                   0x0C000000U
-#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
-#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
-
-#define GPIO_PUPDR_PUPDR14                   0x30000000U
-#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
-#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
-
-#define GPIO_PUPDR_PUPDR15                   0xC0000000U
-#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
-#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       0x00000001U
-#define GPIO_IDR_IDR_1                       0x00000002U
-#define GPIO_IDR_IDR_2                       0x00000004U
-#define GPIO_IDR_IDR_3                       0x00000008U
-#define GPIO_IDR_IDR_4                       0x00000010U
-#define GPIO_IDR_IDR_5                       0x00000020U
-#define GPIO_IDR_IDR_6                       0x00000040U
-#define GPIO_IDR_IDR_7                       0x00000080U
-#define GPIO_IDR_IDR_8                       0x00000100U
-#define GPIO_IDR_IDR_9                       0x00000200U
-#define GPIO_IDR_IDR_10                      0x00000400U
-#define GPIO_IDR_IDR_11                      0x00000800U
-#define GPIO_IDR_IDR_12                      0x00001000U
-#define GPIO_IDR_IDR_13                      0x00002000U
-#define GPIO_IDR_IDR_14                      0x00004000U
-#define GPIO_IDR_IDR_15                      0x00008000U
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       0x00000001U
-#define GPIO_ODR_ODR_1                       0x00000002U
-#define GPIO_ODR_ODR_2                       0x00000004U
-#define GPIO_ODR_ODR_3                       0x00000008U
-#define GPIO_ODR_ODR_4                       0x00000010U
-#define GPIO_ODR_ODR_5                       0x00000020U
-#define GPIO_ODR_ODR_6                       0x00000040U
-#define GPIO_ODR_ODR_7                       0x00000080U
-#define GPIO_ODR_ODR_8                       0x00000100U
-#define GPIO_ODR_ODR_9                       0x00000200U
-#define GPIO_ODR_ODR_10                      0x00000400U
-#define GPIO_ODR_ODR_11                      0x00000800U
-#define GPIO_ODR_ODR_12                      0x00001000U
-#define GPIO_ODR_ODR_13                      0x00002000U
-#define GPIO_ODR_ODR_14                      0x00004000U
-#define GPIO_ODR_ODR_15                      0x00008000U
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       0x00000001U
-#define GPIO_BSRR_BS_1                       0x00000002U
-#define GPIO_BSRR_BS_2                       0x00000004U
-#define GPIO_BSRR_BS_3                       0x00000008U
-#define GPIO_BSRR_BS_4                       0x00000010U
-#define GPIO_BSRR_BS_5                       0x00000020U
-#define GPIO_BSRR_BS_6                       0x00000040U
-#define GPIO_BSRR_BS_7                       0x00000080U
-#define GPIO_BSRR_BS_8                       0x00000100U
-#define GPIO_BSRR_BS_9                       0x00000200U
-#define GPIO_BSRR_BS_10                      0x00000400U
-#define GPIO_BSRR_BS_11                      0x00000800U
-#define GPIO_BSRR_BS_12                      0x00001000U
-#define GPIO_BSRR_BS_13                      0x00002000U
-#define GPIO_BSRR_BS_14                      0x00004000U
-#define GPIO_BSRR_BS_15                      0x00008000U
-#define GPIO_BSRR_BR_0                       0x00010000U
-#define GPIO_BSRR_BR_1                       0x00020000U
-#define GPIO_BSRR_BR_2                       0x00040000U
-#define GPIO_BSRR_BR_3                       0x00080000U
-#define GPIO_BSRR_BR_4                       0x00100000U
-#define GPIO_BSRR_BR_5                       0x00200000U
-#define GPIO_BSRR_BR_6                       0x00400000U
-#define GPIO_BSRR_BR_7                       0x00800000U
-#define GPIO_BSRR_BR_8                       0x01000000U
-#define GPIO_BSRR_BR_9                       0x02000000U
-#define GPIO_BSRR_BR_10                      0x04000000U
-#define GPIO_BSRR_BR_11                      0x08000000U
-#define GPIO_BSRR_BR_12                      0x10000000U
-#define GPIO_BSRR_BR_13                      0x20000000U
-#define GPIO_BSRR_BR_14                      0x40000000U
-#define GPIO_BSRR_BR_15                      0x80000000U
-
-/****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0                       0x00000001U
-#define GPIO_LCKR_LCK1                       0x00000002U
-#define GPIO_LCKR_LCK2                       0x00000004U
-#define GPIO_LCKR_LCK3                       0x00000008U
-#define GPIO_LCKR_LCK4                       0x00000010U
-#define GPIO_LCKR_LCK5                       0x00000020U
-#define GPIO_LCKR_LCK6                       0x00000040U
-#define GPIO_LCKR_LCK7                       0x00000080U
-#define GPIO_LCKR_LCK8                       0x00000100U
-#define GPIO_LCKR_LCK9                       0x00000200U
-#define GPIO_LCKR_LCK10                      0x00000400U
-#define GPIO_LCKR_LCK11                      0x00000800U
-#define GPIO_LCKR_LCK12                      0x00001000U
-#define GPIO_LCKR_LCK13                      0x00002000U
-#define GPIO_LCKR_LCK14                      0x00004000U
-#define GPIO_LCKR_LCK15                      0x00008000U
-#define GPIO_LCKR_LCKK                       0x00010000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Inter-integrated Circuit Interface                    */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          0x00000001U     /*!<Peripheral Enable                             */
-#define  I2C_CR1_SMBUS                       0x00000002U     /*!<SMBus Mode                                    */
-#define  I2C_CR1_SMBTYPE                     0x00000008U     /*!<SMBus Type                                    */
-#define  I2C_CR1_ENARP                       0x00000010U     /*!<ARP Enable                                    */
-#define  I2C_CR1_ENPEC                       0x00000020U     /*!<PEC Enable                                    */
-#define  I2C_CR1_ENGC                        0x00000040U     /*!<General Call Enable                           */
-#define  I2C_CR1_NOSTRETCH                   0x00000080U     /*!<Clock Stretching Disable (Slave mode)  */
-#define  I2C_CR1_START                       0x00000100U     /*!<Start Generation                              */
-#define  I2C_CR1_STOP                        0x00000200U     /*!<Stop Generation                               */
-#define  I2C_CR1_ACK                         0x00000400U     /*!<Acknowledge Enable                            */
-#define  I2C_CR1_POS                         0x00000800U     /*!<Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         0x00001000U     /*!<Packet Error Checking                         */
-#define  I2C_CR1_ALERT                       0x00002000U     /*!<SMBus Alert                                   */
-#define  I2C_CR1_SWRST                       0x00008000U     /*!<Software Reset                                */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        0x0000003FU     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
-#define  I2C_CR2_FREQ_0                      0x00000001U     /*!<Bit 0 */
-#define  I2C_CR2_FREQ_1                      0x00000002U     /*!<Bit 1 */
-#define  I2C_CR2_FREQ_2                      0x00000004U     /*!<Bit 2 */
-#define  I2C_CR2_FREQ_3                      0x00000008U     /*!<Bit 3 */
-#define  I2C_CR2_FREQ_4                      0x00000010U     /*!<Bit 4 */
-#define  I2C_CR2_FREQ_5                      0x00000020U     /*!<Bit 5 */
-
-#define  I2C_CR2_ITERREN                     0x00000100U     /*!<Error Interrupt Enable  */
-#define  I2C_CR2_ITEVTEN                     0x00000200U     /*!<Event Interrupt Enable  */
-#define  I2C_CR2_ITBUFEN                     0x00000400U     /*!<Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       0x00000800U     /*!<DMA Requests Enable     */
-#define  I2C_CR2_LAST                        0x00001000U     /*!<DMA Last Transfer       */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     0x000000FEU     /*!<Interface Address */
-#define  I2C_OAR1_ADD8_9                     0x00000300U     /*!<Interface Address */
-
-#define  I2C_OAR1_ADD0                       0x00000001U     /*!<Bit 0 */
-#define  I2C_OAR1_ADD1                       0x00000002U     /*!<Bit 1 */
-#define  I2C_OAR1_ADD2                       0x00000004U     /*!<Bit 2 */
-#define  I2C_OAR1_ADD3                       0x00000008U     /*!<Bit 3 */
-#define  I2C_OAR1_ADD4                       0x00000010U     /*!<Bit 4 */
-#define  I2C_OAR1_ADD5                       0x00000020U     /*!<Bit 5 */
-#define  I2C_OAR1_ADD6                       0x00000040U     /*!<Bit 6 */
-#define  I2C_OAR1_ADD7                       0x00000080U     /*!<Bit 7 */
-#define  I2C_OAR1_ADD8                       0x00000100U     /*!<Bit 8 */
-#define  I2C_OAR1_ADD9                       0x00000200U     /*!<Bit 9 */
-
-#define  I2C_OAR1_ADDMODE                    0x00008000U     /*!<Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     0x00000001U        /*!<Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       0x000000FEU        /*!<Interface address           */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           0x000000FFU        /*!<8-bit Data Register         */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          0x00000001U     /*!<Start Bit (Master mode)                  */
-#define  I2C_SR1_ADDR                        0x00000002U     /*!<Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         0x00000004U     /*!<Byte Transfer Finished                          */
-#define  I2C_SR1_ADD10                       0x00000008U     /*!<10-bit header sent (Master mode)         */
-#define  I2C_SR1_STOPF                       0x00000010U     /*!<Stop detection (Slave mode)              */
-#define  I2C_SR1_RXNE                        0x00000040U     /*!<Data Register not Empty (receivers)      */
-#define  I2C_SR1_TXE                         0x00000080U     /*!<Data Register Empty (transmitters)       */
-#define  I2C_SR1_BERR                        0x00000100U     /*!<Bus Error                                       */
-#define  I2C_SR1_ARLO                        0x00000200U     /*!<Arbitration Lost (master mode)           */
-#define  I2C_SR1_AF                          0x00000400U     /*!<Acknowledge Failure                             */
-#define  I2C_SR1_OVR                         0x00000800U     /*!<Overrun/Underrun                                */
-#define  I2C_SR1_PECERR                      0x00001000U     /*!<PEC Error in reception                          */
-#define  I2C_SR1_TIMEOUT                     0x00004000U     /*!<Timeout or Tlow Error                           */
-#define  I2C_SR1_SMBALERT                    0x00008000U     /*!<SMBus Alert                                     */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         0x00000001U     /*!<Master/Slave                              */
-#define  I2C_SR2_BUSY                        0x00000002U     /*!<Bus Busy                                  */
-#define  I2C_SR2_TRA                         0x00000004U     /*!<Transmitter/Receiver                      */
-#define  I2C_SR2_GENCALL                     0x00000010U     /*!<General Call Address (Slave mode)  */
-#define  I2C_SR2_SMBDEFAULT                  0x00000020U     /*!<SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     0x00000040U     /*!<SMBus Host Header (Slave mode)     */
-#define  I2C_SR2_DUALF                       0x00000080U     /*!<Dual Flag (Slave mode)             */
-#define  I2C_SR2_PEC                         0x0000FF00U     /*!<Packet Error Checking Register            */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         0x00000FFFU     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        0x00004000U     /*!<Fast Mode Duty Cycle                                       */
-#define  I2C_CCR_FS                          0x00008000U     /*!<I2C Master Mode Selection                                  */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     0x0000003FU     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************  Bit definition for I2C_FLTR register  *******************/
-#define  I2C_FLTR_DNF                        0x0000000FU     /*!<Digital Noise Filter */
-#define  I2C_FLTR_ANOFF                      0x00000010U     /*!<Analog Noise Filter OFF */
-
-/******************************************************************************/
-/*                                                                            */
-/*        Fast Mode Plus Inter-integrated Circuit Interface (I2C)             */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define  FMPI2C_CR1_PE                        0x00000001U        /*!< Peripheral enable                   */
-#define  FMPI2C_CR1_TXIE                      0x00000002U        /*!< TX interrupt enable                 */
-#define  FMPI2C_CR1_RXIE                      0x00000004U        /*!< RX interrupt enable                 */
-#define  FMPI2C_CR1_ADDRIE                    0x00000008U        /*!< Address match interrupt enable      */
-#define  FMPI2C_CR1_NACKIE                    0x00000010U        /*!< NACK received interrupt enable      */
-#define  FMPI2C_CR1_STOPIE                    0x00000020U        /*!< STOP detection interrupt enable     */
-#define  FMPI2C_CR1_TCIE                      0x00000040U        /*!< Transfer complete interrupt enable  */
-#define  FMPI2C_CR1_ERRIE                     0x00000080U        /*!< Errors interrupt enable             */
-#define  FMPI2C_CR1_DFN                       0x00000F00U        /*!< Digital noise filter                */
-#define  FMPI2C_CR1_ANFOFF                    0x00001000U        /*!< Analog noise filter OFF             */
-#define  FMPI2C_CR1_TXDMAEN                   0x00004000U        /*!< DMA transmission requests enable    */
-#define  FMPI2C_CR1_RXDMAEN                   0x00008000U        /*!< DMA reception requests enable       */
-#define  FMPI2C_CR1_SBC                       0x00010000U        /*!< Slave byte control                  */
-#define  FMPI2C_CR1_NOSTRETCH                 0x00020000U        /*!< Clock stretching disable            */
-#define  FMPI2C_CR1_GCEN                      0x00080000U        /*!< General call enable                 */
-#define  FMPI2C_CR1_SMBHEN                    0x00100000U        /*!< SMBus host address enable           */
-#define  FMPI2C_CR1_SMBDEN                    0x00200000U        /*!< SMBus device default address enable */
-#define  FMPI2C_CR1_ALERTEN                   0x00400000U        /*!< SMBus alert enable                  */
-#define  FMPI2C_CR1_PECEN                     0x00800000U        /*!< PEC enable                          */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define  FMPI2C_CR2_SADD                      0x000003FFU        /*!< Slave address (master mode)                             */
-#define  FMPI2C_CR2_RD_WRN                    0x00000400U        /*!< Transfer direction (master mode)                        */
-#define  FMPI2C_CR2_ADD10                     0x00000800U        /*!< 10-bit addressing mode (master mode)                    */
-#define  FMPI2C_CR2_HEAD10R                   0x00001000U        /*!< 10-bit address header only read direction (master mode) */
-#define  FMPI2C_CR2_START                     0x00002000U        /*!< START generation                                        */
-#define  FMPI2C_CR2_STOP                      0x00004000U        /*!< STOP generation (master mode)                           */
-#define  FMPI2C_CR2_NACK                      0x00008000U        /*!< NACK generation (slave mode)                            */
-#define  FMPI2C_CR2_NBYTES                    0x00FF0000U        /*!< Number of bytes                                         */
-#define  FMPI2C_CR2_RELOAD                    0x01000000U        /*!< NBYTES reload mode                                      */
-#define  FMPI2C_CR2_AUTOEND                   0x02000000U        /*!< Automatic end mode (master mode)                        */
-#define  FMPI2C_CR2_PECBYTE                   0x04000000U        /*!< Packet error checking byte                              */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define  FMPI2C_OAR1_OA1                      0x000003FFU        /*!< Interface own address 1   */
-#define  FMPI2C_OAR1_OA1MODE                  0x00000400U        /*!< Own address 1 10-bit mode */
-#define  FMPI2C_OAR1_OA1EN                    0x00008000U        /*!< Own address 1 enable      */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define  FMPI2C_OAR2_OA2                      0x000000FEU        /*!< Interface own address 2 */
-#define  FMPI2C_OAR2_OA2MSK                   0x00000700U        /*!< Own address 2 masks     */
-#define  FMPI2C_OAR2_OA2EN                    0x00008000U        /*!< Own address 2 enable    */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define  FMPI2C_TIMINGR_SCLL                  0x000000FFU        /*!< SCL low period (master mode)  */
-#define  FMPI2C_TIMINGR_SCLH                  0x0000FF00U        /*!< SCL high period (master mode) */
-#define  FMPI2C_TIMINGR_SDADEL                0x000F0000U        /*!< Data hold time                */
-#define  FMPI2C_TIMINGR_SCLDEL                0x00F00000U        /*!< Data setup time               */
-#define  FMPI2C_TIMINGR_PRESC                 0xF0000000U        /*!< Timings prescaler             */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define  FMPI2C_TIMEOUTR_TIMEOUTA             0x00000FFFU        /*!< Bus timeout A                 */
-#define  FMPI2C_TIMEOUTR_TIDLE                0x00001000U        /*!< Idle clock timeout detection  */
-#define  FMPI2C_TIMEOUTR_TIMOUTEN             0x00008000U        /*!< Clock timeout enable          */
-#define  FMPI2C_TIMEOUTR_TIMEOUTB             0x0FFF0000U        /*!< Bus timeout B                 */
-#define  FMPI2C_TIMEOUTR_TEXTEN               0x80000000U        /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define  FMPI2C_ISR_TXE                       0x00000001U        /*!< Transmit data register empty     */
-#define  FMPI2C_ISR_TXIS                      0x00000002U        /*!< Transmit interrupt status        */
-#define  FMPI2C_ISR_RXNE                      0x00000004U        /*!< Receive data register not empty  */
-#define  FMPI2C_ISR_ADDR                      0x00000008U        /*!< Address matched (slave mode)     */
-#define  FMPI2C_ISR_NACKF                     0x00000010U        /*!< NACK received flag               */
-#define  FMPI2C_ISR_STOPF                     0x00000020U        /*!< STOP detection flag              */
-#define  FMPI2C_ISR_TC                        0x00000040U        /*!< Transfer complete (master mode)  */
-#define  FMPI2C_ISR_TCR                       0x00000080U        /*!< Transfer complete reload         */
-#define  FMPI2C_ISR_BERR                      0x00000100U        /*!< Bus error                        */
-#define  FMPI2C_ISR_ARLO                      0x00000200U        /*!< Arbitration lost                 */
-#define  FMPI2C_ISR_OVR                       0x00000400U        /*!< Overrun/Underrun                 */
-#define  FMPI2C_ISR_PECERR                    0x00000800U        /*!< PEC error in reception           */
-#define  FMPI2C_ISR_TIMEOUT                   0x00001000U        /*!< Timeout or Tlow detection flag   */
-#define  FMPI2C_ISR_ALERT                     0x00002000U        /*!< SMBus alert                      */
-#define  FMPI2C_ISR_BUSY                      0x00008000U        /*!< Bus busy                         */
-#define  FMPI2C_ISR_DIR                       0x00010000U        /*!< Transfer direction (slave mode)  */
-#define  FMPI2C_ISR_ADDCODE                   0x00FE0000U        /*!< Address match code (slave mode)  */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define  FMPI2C_ICR_ADDRCF                    0x00000008U        /*!< Address matched clear flag  */
-#define  FMPI2C_ICR_NACKCF                    0x00000010U        /*!< NACK clear flag             */
-#define  FMPI2C_ICR_STOPCF                    0x00000020U        /*!< STOP detection clear flag   */
-#define  FMPI2C_ICR_BERRCF                    0x00000100U        /*!< Bus error clear flag        */
-#define  FMPI2C_ICR_ARLOCF                    0x00000200U        /*!< Arbitration lost clear flag */
-#define  FMPI2C_ICR_OVRCF                     0x00000400U        /*!< Overrun/Underrun clear flag */
-#define  FMPI2C_ICR_PECCF                     0x00000800U        /*!< PAC error clear flag        */
-#define  FMPI2C_ICR_TIMOUTCF                  0x00001000U        /*!< Timeout clear flag          */
-#define  FMPI2C_ICR_ALERTCF                   0x00002000U        /*!< Alert clear flag            */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define  FMPI2C_PECR_PEC                      0x000000FFU        /*!< PEC register */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define  FMPI2C_RXDR_RXDATA                   0x000000FFU        /*!< 8-bit receive data */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define  FMPI2C_TXDR_TXDATA                   0x000000FFU        /*!< 8-bit transmit data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Independent WATCHDOG                             */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         0x01U               /*!<Watchdog prescaler value update      */
-#define  IWDG_SR_RVU                         0x02U               /*!<Watchdog counter reload value update */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                             Power Control                                  */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
-#define  PWR_CR_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
-#define  PWR_CR_CWUF                         0x00000004U     /*!< Clear Wakeup Flag                   */
-#define  PWR_CR_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
-#define  PWR_CR_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
-
-#define  PWR_CR_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        0x00000020U     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        0x00000040U     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        0x00000080U     /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
-
-#define  PWR_CR_DBP                          0x00000100U     /*!< Disable Backup Domain write protection                     */
-#define  PWR_CR_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                              */
-#define  PWR_CR_LPLVDS                       0x00000400U     /*!< Low Power Regulator Low Voltage in Deep Sleep mode         */
-#define  PWR_CR_MRLVDS                       0x00000800U     /*!< Main Regulator Low Voltage in Deep Sleep mode              */
-#define  PWR_CR_ADCDC1                       0x00002000U     /*!< Refer to AN4073 on how to use this bit                     */
-
-#define  PWR_CR_VOS                          0x0000C000U     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
-#define  PWR_CR_VOS_0                        0x00004000U     /*!< Bit 0 */
-#define  PWR_CR_VOS_1                        0x00008000U     /*!< Bit 1 */
-
-#define  PWR_CR_FMSSR                        0x00100000U     /*!< Flash Memory Sleep System Run        */
-#define  PWR_CR_FISSR                        0x00200000U     /*!< Flash Interface Stop while System Run */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         0x00000001U     /*!< Wakeup Flag                                      */
-#define  PWR_CSR_SBF                         0x00000002U     /*!< Standby Flag                                     */
-#define  PWR_CSR_PVDO                        0x00000004U     /*!< PVD Output                                       */
-#define  PWR_CSR_BRR                         0x00000008U     /*!< Backup regulator ready                           */
-#define  PWR_CSR_EWUP                        0x00000100U     /*!< Enable WKUP pin                                  */
-#define  PWR_CSR_BRE                         0x00000200U     /*!< Backup regulator enable                          */
-#define  PWR_CSR_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
-/******************************************************************************/
-/*                                                                            */
-/*                                    QUADSPI                                 */
-/*                                                                            */
-/******************************************************************************/
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
- */
-#define  QSPI1_V2_1L                                                      /*!< QSPI Virtual Version             */
-
-/*****************  Bit definition for QUADSPI_CR register  *******************/
-#define  QUADSPI_CR_EN                           0x00000001U            /*!< Enable                             */
-#define  QUADSPI_CR_ABORT                        0x00000002U            /*!< Abort request                      */
-#define  QUADSPI_CR_DMAEN                        0x00000004U            /*!< DMA Enable                         */
-#define  QUADSPI_CR_TCEN                         0x00000008U            /*!< Timeout Counter Enable             */
-#define  QUADSPI_CR_SSHIFT                       0x00000010U            /*!< SSHIFT Sample Shift                */
-#define  QUADSPI_CR_DFM                          0x00000040U            /*!< Dual Flash Mode                    */
-#define  QUADSPI_CR_FSEL                         0x00000080U            /*!< Flash Select                       */
-#define  QUADSPI_CR_FTHRES                       0x00001F00U            /*!< FTHRES[3:0] FIFO Level             */
-#define  QUADSPI_CR_FTHRES_0                     0x00000100U            /*!< Bit 0 */
-#define  QUADSPI_CR_FTHRES_1                     0x00000200U            /*!< Bit 1 */
-#define  QUADSPI_CR_FTHRES_2                     0x00000400U            /*!< Bit 2 */
-#define  QUADSPI_CR_FTHRES_3                     0x00000800U            /*!< Bit 3 */
-#define  QUADSPI_CR_FTHRES_4                     0x00001000U            /*!< Bit 4 */
-#define  QUADSPI_CR_TEIE                         0x00010000U            /*!< Transfer Error Interrupt Enable    */
-#define  QUADSPI_CR_TCIE                         0x00020000U            /*!< Transfer Complete Interrupt Enable */
-#define  QUADSPI_CR_FTIE                         0x00040000U            /*!< FIFO Threshold Interrupt Enable    */
-#define  QUADSPI_CR_SMIE                         0x00080000U            /*!< Status Match Interrupt Enable      */
-#define  QUADSPI_CR_TOIE                         0x00100000U            /*!< TimeOut Interrupt Enable           */
-#define  QUADSPI_CR_APMS                         0x00400000U            /*!< Bit 1 */
-#define  QUADSPI_CR_PMM                          0x00800000U            /*!< Polling Match Mode                 */
-#define  QUADSPI_CR_PRESCALER                    0xFF000000U            /*!< PRESCALER[7:0] Clock prescaler     */
-#define  QUADSPI_CR_PRESCALER_0                  0x01000000U            /*!< Bit 0 */
-#define  QUADSPI_CR_PRESCALER_1                  0x02000000U            /*!< Bit 1 */
-#define  QUADSPI_CR_PRESCALER_2                  0x04000000U            /*!< Bit 2 */
-#define  QUADSPI_CR_PRESCALER_3                  0x08000000U            /*!< Bit 3 */
-#define  QUADSPI_CR_PRESCALER_4                  0x10000000U            /*!< Bit 4 */
-#define  QUADSPI_CR_PRESCALER_5                  0x20000000U            /*!< Bit 5 */
-#define  QUADSPI_CR_PRESCALER_6                  0x40000000U            /*!< Bit 6 */
-#define  QUADSPI_CR_PRESCALER_7                  0x80000000U            /*!< Bit 7 */
-
-/*****************  Bit definition for QUADSPI_DCR register  ******************/
-#define  QUADSPI_DCR_CKMODE                      0x00000001U            /*!< Mode 0 / Mode 3                 */
-#define  QUADSPI_DCR_CSHT                        0x00000700U            /*!< CSHT[2:0]: ChipSelect High Time */
-#define  QUADSPI_DCR_CSHT_0                      0x00000100U            /*!< Bit 0 */
-#define  QUADSPI_DCR_CSHT_1                      0x00000200U            /*!< Bit 1 */
-#define  QUADSPI_DCR_CSHT_2                      0x00000400U            /*!< Bit 2 */
-#define  QUADSPI_DCR_FSIZE                       0x001F0000U            /*!< FSIZE[4:0]: Flash Size          */
-#define  QUADSPI_DCR_FSIZE_0                     0x00010000U            /*!< Bit 0 */
-#define  QUADSPI_DCR_FSIZE_1                     0x00020000U            /*!< Bit 1 */
-#define  QUADSPI_DCR_FSIZE_2                     0x00040000U            /*!< Bit 2 */
-#define  QUADSPI_DCR_FSIZE_3                     0x00080000U            /*!< Bit 3 */
-#define  QUADSPI_DCR_FSIZE_4                     0x00100000U            /*!< Bit 4 */
-
-/******************  Bit definition for QUADSPI_SR register  *******************/
-#define  QUADSPI_SR_TEF                          0x00000001U             /*!< Transfer Error Flag    */
-#define  QUADSPI_SR_TCF                          0x00000002U             /*!< Transfer Complete Flag */
-#define  QUADSPI_SR_FTF                          0x00000004U             /*!< FIFO Threshlod Flag    */
-#define  QUADSPI_SR_SMF                          0x00000008U             /*!< Status Match Flag      */
-#define  QUADSPI_SR_TOF                          0x00000010U             /*!< Timeout Flag           */
-#define  QUADSPI_SR_BUSY                         0x00000020U             /*!< Busy                   */
-#define  QUADSPI_SR_FLEVEL                       0x00003F00U             /*!< FIFO Threshlod Flag    */
-#define  QUADSPI_SR_FLEVEL_0                     0x00000100U             /*!< Bit 0 */
-#define  QUADSPI_SR_FLEVEL_1                     0x00000200U             /*!< Bit 1 */
-#define  QUADSPI_SR_FLEVEL_2                     0x00000400U             /*!< Bit 2 */
-#define  QUADSPI_SR_FLEVEL_3                     0x00000800U             /*!< Bit 3 */
-#define  QUADSPI_SR_FLEVEL_4                     0x00001000U             /*!< Bit 4 */
-#define  QUADSPI_SR_FLEVEL_5                     0x00002000U             /*!< Bit 5 */
-
-/******************  Bit definition for QUADSPI_FCR register  ******************/
-#define  QUADSPI_FCR_CTEF                        0x00000001U             /*!< Clear Transfer Error Flag    */
-#define  QUADSPI_FCR_CTCF                        0x00000002U             /*!< Clear Transfer Complete Flag */
-#define  QUADSPI_FCR_CSMF                        0x00000008U             /*!< Clear Status Match Flag      */
-#define  QUADSPI_FCR_CTOF                        0x00000010U             /*!< Clear Timeout Flag           */
-
-/******************  Bit definition for QUADSPI_DLR register  ******************/
-#define  QUADSPI_DLR_DL                        0xFFFFFFFFU               /*!< DL[31:0]: Data Length */
-
-/******************  Bit definition for QUADSPI_CCR register  ******************/
-#define  QUADSPI_CCR_INSTRUCTION                  0x000000FFU            /*!< INSTRUCTION[7:0]: Instruction */
-#define  QUADSPI_CCR_INSTRUCTION_0                0x00000001U            /*!< Bit 0 */
-#define  QUADSPI_CCR_INSTRUCTION_1                0x00000002U            /*!< Bit 1 */
-#define  QUADSPI_CCR_INSTRUCTION_2                0x00000004U            /*!< Bit 2 */
-#define  QUADSPI_CCR_INSTRUCTION_3                0x00000008U            /*!< Bit 3 */
-#define  QUADSPI_CCR_INSTRUCTION_4                0x00000010U            /*!< Bit 4 */
-#define  QUADSPI_CCR_INSTRUCTION_5                0x00000020U            /*!< Bit 5 */
-#define  QUADSPI_CCR_INSTRUCTION_6                0x00000040U            /*!< Bit 6 */
-#define  QUADSPI_CCR_INSTRUCTION_7                0x00000080U            /*!< Bit 7 */
-#define  QUADSPI_CCR_IMODE                        0x00000300U            /*!< IMODE[1:0]: Instruction Mode     */
-#define  QUADSPI_CCR_IMODE_0                      0x00000100U            /*!< Bit 0 */
-#define  QUADSPI_CCR_IMODE_1                      0x00000200U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ADMODE                       0x00000C00U            /*!< ADMODE[1:0]: Address Mode         */
-#define  QUADSPI_CCR_ADMODE_0                     0x00000400U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ADMODE_1                     0x00000800U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ADSIZE                       0x00003000U            /*!< ADSIZE[1:0]: Address Size         */
-#define  QUADSPI_CCR_ADSIZE_0                     0x00001000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ADSIZE_1                     0x00002000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ABMODE                       0x0000C000U            /*!< ABMODE[1:0]: Alternate Bytes Mode */
-#define  QUADSPI_CCR_ABMODE_0                     0x00004000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ABMODE_1                     0x00008000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ABSIZE                       0x00030000U            /*!< ABSIZE[1:0]: Instruction Mode     */
-#define  QUADSPI_CCR_ABSIZE_0                     0x00010000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ABSIZE_1                     0x00020000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_DCYC                         0x007C0000U            /*!< DCYC[4:0]: Dummy Cycles           */
-#define  QUADSPI_CCR_DCYC_0                       0x00040000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_DCYC_1                       0x00080000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_DCYC_2                       0x00100000U            /*!< Bit 2 */
-#define  QUADSPI_CCR_DCYC_3                       0x00200000U            /*!< Bit 3 */
-#define  QUADSPI_CCR_DCYC_4                       0x00400000U            /*!< Bit 4 */
-#define  QUADSPI_CCR_DMODE                        0x03000000U            /*!< DMODE[1:0]: Data Mode                */
-#define  QUADSPI_CCR_DMODE_0                      0x01000000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_DMODE_1                      0x02000000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_FMODE                        0x0C000000U            /*!< FMODE[1:0]: Functional Mode           */
-#define  QUADSPI_CCR_FMODE_0                      0x04000000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_FMODE_1                      0x08000000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_SIOO                         0x10000000U            /*!< SIOO: Send Instruction Only Once Mode */
-#define  QUADSPI_CCR_DHHC                         0x40000000U            /*!< DHHC: Delay Half Hclk Cycle           */
-#define  QUADSPI_CCR_DDRM                         0x80000000U            /*!< DDRM: Double Data Rate Mode           */ 
-/******************  Bit definition for QUADSPI_AR register  *******************/
-#define  QUADSPI_AR_ADDRESS                       0xFFFFFFFFU            /*!< ADDRESS[31:0]: Address                */
-
-/******************  Bit definition for QUADSPI_ABR register  ******************/
-#define  QUADSPI_ABR_ALTERNATE                    0xFFFFFFFFU            /*!< ALTERNATE[31:0]: Alternate Bytes      */
-
-/******************  Bit definition for QUADSPI_DR register  *******************/
-#define  QUADSPI_DR_DATA                          0xFFFFFFFFU            /*!< DATA[31:0]: Data                      */
-
-/******************  Bit definition for QUADSPI_PSMKR register  ****************/
-#define  QUADSPI_PSMKR_MASK                       0xFFFFFFFFU            /*!< MASK[31:0]: Status Mask               */
-
-/******************  Bit definition for QUADSPI_PSMAR register  ****************/
-#define  QUADSPI_PSMAR_MATCH                      0xFFFFFFFFU            /*!< MATCH[31:0]: Status Match             */
-
-/******************  Bit definition for QUADSPI_PIR register  *****************/
-#define  QUADSPI_PIR_INTERVAL                     0x0000FFFFU            /*!< INTERVAL[15:0]: Polling Interval      */
-
-/******************  Bit definition for QUADSPI_LPTR register  *****************/
-#define  QUADSPI_LPTR_TIMEOUT                     0x0000FFFFU            /*!< TIMEOUT[15:0]: Timeout period         */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        0x00000001U
-#define  RCC_CR_HSIRDY                       0x00000002U
-
-#define  RCC_CR_HSITRIM                      0x000000F8U
-#define  RCC_CR_HSITRIM_0                    0x00000008U/*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    0x00000010U/*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    0x00000020U/*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    0x00000040U/*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    0x00000080U/*!<Bit 4 */
-
-#define  RCC_CR_HSICAL                       0x0000FF00U
-#define  RCC_CR_HSICAL_0                     0x00000100U/*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     0x00000200U/*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     0x00000400U/*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     0x00000800U/*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     0x00001000U/*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     0x00002000U/*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     0x00004000U/*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     0x00008000U/*!<Bit 7 */
-
-#define  RCC_CR_HSEON                        0x00010000U
-#define  RCC_CR_HSERDY                       0x00020000U
-#define  RCC_CR_HSEBYP                       0x00040000U
-#define  RCC_CR_CSSON                        0x00080000U
-#define  RCC_CR_PLLON                        0x01000000U
-#define  RCC_CR_PLLRDY                       0x02000000U
-#define  RCC_CR_PLLI2SON                     0x04000000U
-#define  RCC_CR_PLLI2SRDY                    0x08000000U
-
-/********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    0x0000003FU
-#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
-#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
-#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
-#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
-#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
-#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
-
-#define  RCC_PLLCFGR_PLLN                     0x00007FC0U
-#define  RCC_PLLCFGR_PLLN_0                   0x00000040U
-#define  RCC_PLLCFGR_PLLN_1                   0x00000080U
-#define  RCC_PLLCFGR_PLLN_2                   0x00000100U
-#define  RCC_PLLCFGR_PLLN_3                   0x00000200U
-#define  RCC_PLLCFGR_PLLN_4                   0x00000400U
-#define  RCC_PLLCFGR_PLLN_5                   0x00000800U
-#define  RCC_PLLCFGR_PLLN_6                   0x00001000U
-#define  RCC_PLLCFGR_PLLN_7                   0x00002000U
-#define  RCC_PLLCFGR_PLLN_8                   0x00004000U
-
-#define  RCC_PLLCFGR_PLLP                    0x00030000U
-#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
-#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
-
-#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
-
-#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
-#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
-#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
-#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
-#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
-
-#define  RCC_PLLCFGR_PLLR                    0x70000000U
-#define  RCC_PLLCFGR_PLLR_0                  0x10000000U
-#define  RCC_PLLCFGR_PLLR_1                  0x20000000U
-#define  RCC_PLLCFGR_PLLR_2                  0x40000000U
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-/*!< SW configuration */
-#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
-
-#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock      */
-#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock      */
-#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL/PLLP selected as system clock */
-#define  RCC_CFGR_SW_PLLR                    0x00000003U        /*!< PLL/PLLR selected as system clock */
-
-/*!< SWS configuration */
-#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
-
-#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL/PLLP used as system clock       */
-#define  RCC_CFGR_SWS_PLLR                   0x0000000CU        /*!< PLL/PLLR used as system clock       */
-
-/*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
-
-#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
-
-/*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     0x001F0000U
-#define  RCC_CFGR_RTCPRE_0                   0x00010000U
-#define  RCC_CFGR_RTCPRE_1                   0x00020000U
-#define  RCC_CFGR_RTCPRE_2                   0x00040000U
-#define  RCC_CFGR_RTCPRE_3                   0x00080000U
-#define  RCC_CFGR_RTCPRE_4                   0x00100000U
-
-/*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       0x00600000U
-#define  RCC_CFGR_MCO1_0                     0x00200000U
-#define  RCC_CFGR_MCO1_1                     0x00400000U
-
-#define  RCC_CFGR_MCO1PRE                    0x07000000U
-#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
-#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
-#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
-
-#define  RCC_CFGR_MCO2PRE                    0x38000000U
-#define  RCC_CFGR_MCO2PRE_0                  0x08000000U
-#define  RCC_CFGR_MCO2PRE_1                  0x10000000U
-#define  RCC_CFGR_MCO2PRE_2                  0x20000000U
-
-#define  RCC_CFGR_MCO2                       0xC0000000U
-#define  RCC_CFGR_MCO2_0                     0x40000000U
-#define  RCC_CFGR_MCO2_1                     0x80000000U
-
-/********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     0x00000001U
-#define  RCC_CIR_LSERDYF                     0x00000002U
-#define  RCC_CIR_HSIRDYF                     0x00000004U
-#define  RCC_CIR_HSERDYF                     0x00000008U
-#define  RCC_CIR_PLLRDYF                     0x00000010U
-#define  RCC_CIR_PLLI2SRDYF                  0x00000020U
-
-#define  RCC_CIR_CSSF                        0x00000080U
-#define  RCC_CIR_LSIRDYIE                    0x00000100U
-#define  RCC_CIR_LSERDYIE                    0x00000200U
-#define  RCC_CIR_HSIRDYIE                    0x00000400U
-#define  RCC_CIR_HSERDYIE                    0x00000800U
-#define  RCC_CIR_PLLRDYIE                    0x00001000U
-#define  RCC_CIR_PLLI2SRDYIE                 0x00002000U
-
-#define  RCC_CIR_LSIRDYC                     0x00010000U
-#define  RCC_CIR_LSERDYC                     0x00020000U
-#define  RCC_CIR_HSIRDYC                     0x00040000U
-#define  RCC_CIR_HSERDYC                     0x00080000U
-#define  RCC_CIR_PLLRDYC                     0x00100000U
-#define  RCC_CIR_PLLI2SRDYC                  0x00200000U
-
-#define  RCC_CIR_CSSC                        0x00800000U
-
-/********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
-#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
-#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
-#define  RCC_AHB1RSTR_GPIODRST               0x00000008U
-#define  RCC_AHB1RSTR_GPIOERST               0x00000010U
-#define  RCC_AHB1RSTR_GPIOFRST               0x00000020U
-#define  RCC_AHB1RSTR_GPIOGRST               0x00000040U
-#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
-#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
-#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
-#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
-
-/********************  Bit definition for RCC_AHB2RSTR register  **************/
-#define  RCC_AHB2RSTR_RNGRST                 0x00000040U
-#define  RCC_AHB2RSTR_OTGFSRST               0x00000080U
-
-/********************  Bit definition for RCC_AHB3RSTR register  **************/
-#define  RCC_AHB3RSTR_FSMCRST                0x00000001U
-#define  RCC_AHB3RSTR_QSPIRST               0x00000002U
-
-/********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM2RST                0x00000001U
-#define  RCC_APB1RSTR_TIM3RST                0x00000002U
-#define  RCC_APB1RSTR_TIM4RST                0x00000004U
-#define  RCC_APB1RSTR_TIM5RST                0x00000008U
-#define  RCC_APB1RSTR_TIM6RST                0x00000010U
-#define  RCC_APB1RSTR_TIM7RST                0x00000020U
-#define  RCC_APB1RSTR_TIM12RST               0x00000040U
-#define  RCC_APB1RSTR_TIM13RST               0x00000080U
-#define  RCC_APB1RSTR_TIM14RST               0x00000100U
-#define  RCC_APB1RSTR_WWDGRST                0x00000800U
-#define  RCC_APB1RSTR_SPI2RST                0x00004000U
-#define  RCC_APB1RSTR_SPI3RST                0x00008000U
-#define  RCC_APB1RSTR_USART2RST              0x00020000U
-#define  RCC_APB1RSTR_USART3RST              0x00040000U
-#define  RCC_APB1RSTR_I2C1RST                0x00200000U
-#define  RCC_APB1RSTR_I2C2RST                0x00400000U
-#define  RCC_APB1RSTR_I2C3RST                0x00800000U
-#define  RCC_APB1RSTR_FMPI2C1RST             0x01000000U
-#define  RCC_APB1RSTR_CAN1RST                0x02000000U
-#define  RCC_APB1RSTR_CAN2RST                0x04000000U
-#define  RCC_APB1RSTR_PWRRST                 0x10000000U
-
-/********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                0x00000001U
-#define  RCC_APB2RSTR_TIM8RST                0x00000002U
-#define  RCC_APB2RSTR_USART1RST              0x00000010U
-#define  RCC_APB2RSTR_USART6RST              0x00000020U
-#define  RCC_APB2RSTR_ADCRST                 0x00000100U
-#define  RCC_APB2RSTR_SDIORST                0x00000800U
-#define  RCC_APB2RSTR_SPI1RST                0x00001000U
-#define  RCC_APB2RSTR_SPI4RST                0x00002000U
-#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
-#define  RCC_APB2RSTR_TIM9RST                0x00010000U
-#define  RCC_APB2RSTR_TIM10RST               0x00020000U
-#define  RCC_APB2RSTR_TIM11RST               0x00040000U
-#define  RCC_APB2RSTR_SPI5RST                0x00100000U
-#define  RCC_APB2RSTR_DFSDM1RST              0x01000000U
-
-/********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
-#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
-#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
-#define  RCC_AHB1ENR_GPIODEN                 0x00000008U
-#define  RCC_AHB1ENR_GPIOEEN                 0x00000010U
-#define  RCC_AHB1ENR_GPIOFEN                 0x00000020U
-#define  RCC_AHB1ENR_GPIOGEN                 0x00000040U
-#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
-#define  RCC_AHB1ENR_CRCEN                   0x00001000U
-#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
-#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
-
-/********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define  RCC_AHB2ENR_RNGEN                   0x00000040U
-#define  RCC_AHB2ENR_OTGFSEN                 0x00000080U
-
-/********************  Bit definition for RCC_AHB3ENR register  ***************/
-#define  RCC_AHB3ENR_FSMCEN                  0x00000001U
-#define  RCC_AHB3ENR_QSPIEN                 0x00000002U
-
-/********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM2EN                  0x00000001U
-#define  RCC_APB1ENR_TIM3EN                  0x00000002U
-#define  RCC_APB1ENR_TIM4EN                  0x00000004U
-#define  RCC_APB1ENR_TIM5EN                  0x00000008U
-#define  RCC_APB1ENR_TIM6EN                  0x00000010U
-#define  RCC_APB1ENR_TIM7EN                  0x00000020U
-#define  RCC_APB1ENR_TIM12EN                 0x00000040U
-#define  RCC_APB1ENR_TIM13EN                 0x00000080U
-#define  RCC_APB1ENR_TIM14EN                 0x00000100U
-#define  RCC_APB1ENR_RTCAPBEN                0x00000400U
-#define  RCC_APB1ENR_WWDGEN                  0x00000800U
-#define  RCC_APB1ENR_SPI2EN                  0x00004000U
-#define  RCC_APB1ENR_SPI3EN                  0x00008000U
-#define  RCC_APB1ENR_USART2EN                0x00020000U
-#define  RCC_APB1ENR_USART3EN                0x00040000U
-#define  RCC_APB1ENR_I2C1EN                  0x00200000U
-#define  RCC_APB1ENR_I2C2EN                  0x00400000U
-#define  RCC_APB1ENR_I2C3EN                  0x00800000U
-#define  RCC_APB1ENR_FMPI2C1EN               0x01000000U
-#define  RCC_APB1ENR_CAN1EN                  0x02000000U
-#define  RCC_APB1ENR_CAN2EN                  0x04000000U
-#define  RCC_APB1ENR_PWREN                   0x10000000U
-
-/********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  0x00000001U
-#define  RCC_APB2ENR_TIM8EN                  0x00000002U
-#define  RCC_APB2ENR_USART1EN                0x00000010U
-#define  RCC_APB2ENR_USART6EN                0x00000020U
-#define  RCC_APB2ENR_ADC1EN                  0x00000100U
-#define  RCC_APB2ENR_SDIOEN                  0x00000800U
-#define  RCC_APB2ENR_SPI1EN                  0x00001000U
-#define  RCC_APB2ENR_SPI4EN                  0x00002000U
-#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
-#define  RCC_APB2ENR_EXTITEN                 0x00008000U
-#define  RCC_APB2ENR_TIM9EN                  0x00010000U
-#define  RCC_APB2ENR_TIM10EN                 0x00020000U
-#define  RCC_APB2ENR_TIM11EN                 0x00040000U
-#define  RCC_APB2ENR_SPI5EN                  0x00100000U
-#define  RCC_APB2ENR_DFSDM1EN                0x01000000U
-/********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
-#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
-#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
-#define  RCC_AHB1LPENR_GPIODLPEN             0x00000008U
-#define  RCC_AHB1LPENR_GPIOELPEN             0x00000010U
-#define  RCC_AHB1LPENR_GPIOFLPEN             0x00000020U
-#define  RCC_AHB1LPENR_GPIOGLPEN             0x00000040U
-#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
-#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
-#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
-#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
-#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
-#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
-
-/********************  Bit definition for RCC_AHB2LPENR register  *************/
-#define  RCC_AHB2LPENR_RNGLPEN               0x00000040U
-#define  RCC_AHB2LPENR_OTGFSLPEN             0x00000080U
-
-/********************  Bit definition for RCC_AHB3LPENR register  *************/
-#define  RCC_AHB3LPENR_FSMCLPEN              0x00000001U
-#define  RCC_AHB3LPENR_QSPILPEN             0x00000002U
-
-/********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM2LPEN              0x00000001U
-#define  RCC_APB1LPENR_TIM3LPEN              0x00000002U
-#define  RCC_APB1LPENR_TIM4LPEN              0x00000004U
-#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
-#define  RCC_APB1LPENR_TIM6LPEN              0x00000010U
-#define  RCC_APB1LPENR_TIM7LPEN              0x00000020U
-#define  RCC_APB1LPENR_TIM12LPEN             0x00000040U
-#define  RCC_APB1LPENR_TIM13LPEN             0x00000080U
-#define  RCC_APB1LPENR_TIM14LPEN             0x00000100U
-#define  RCC_APB1LPENR_RTCAPBLPEN            0x00000400U
-#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
-#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U
-#define  RCC_APB1LPENR_SPI3LPEN              0x00008000U
-#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
-#define  RCC_APB1LPENR_USART3LPEN            0x00040000U
-#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
-#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
-#define  RCC_APB1LPENR_I2C3LPEN              0x00800000U
-#define  RCC_APB1LPENR_FMPI2C1LPEN           0x01000000U
-#define  RCC_APB1LPENR_CAN1LPEN              0x02000000U
-#define  RCC_APB1LPENR_CAN2LPEN              0x04000000U
-#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
-
-/********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
-#define  RCC_APB2LPENR_TIM8LPEN              0x00000002U
-#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
-#define  RCC_APB2LPENR_USART6LPEN            0x00000020U
-#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
-#define  RCC_APB2LPENR_SDIOLPEN              0x00000800U
-#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
-#define  RCC_APB2LPENR_SPI4LPEN              0x00002000U
-#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
-#define  RCC_APB2LPENR_EXTITLPEN             0x00008000U
-#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
-#define  RCC_APB2LPENR_TIM10LPEN             0x00020000U
-#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
-#define  RCC_APB2LPENR_SPI5LPEN              0x00100000U
-#define  RCC_APB2LPENR_DFSDM1LPEN            0x01000000U
-
-/********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      0x00000001U
-#define  RCC_BDCR_LSERDY                     0x00000002U
-#define  RCC_BDCR_LSEBYP                     0x00000004U
-#define  RCC_BDCR_LSEMOD                     0x00000008U
-
-#define  RCC_BDCR_RTCSEL                    0x00000300U
-#define  RCC_BDCR_RTCSEL_0                  0x00000100U
-#define  RCC_BDCR_RTCSEL_1                  0x00000200U
-
-#define  RCC_BDCR_RTCEN                      0x00008000U
-#define  RCC_BDCR_BDRST                      0x00010000U
-
-/********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       0x00000001U
-#define  RCC_CSR_LSIRDY                      0x00000002U
-#define  RCC_CSR_RMVF                        0x01000000U
-#define  RCC_CSR_PADRSTF                     0x04000000U
-#define  RCC_CSR_PORRSTF                     0x08000000U
-#define  RCC_CSR_SFTRSTF                     0x10000000U
-#define  RCC_CSR_WDGRSTF                     0x20000000U
-#define  RCC_CSR_WWDGRSTF                    0x40000000U
-#define  RCC_CSR_LPWRRSTF                    0x80000000U
-
-/********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    0x00001FFFU
-#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
-#define  RCC_SSCGR_SPREADSEL                 0x40000000U
-#define  RCC_SSCGR_SSCGEN                    0x80000000U
-
-/********************  Bit definition for RCC_PLLI2SCFGR register  ************/
-#define  RCC_PLLI2SCFGR_PLLI2SM              0x0000003FU
-#define  RCC_PLLI2SCFGR_PLLI2SM_0            0x00000001U
-#define  RCC_PLLI2SCFGR_PLLI2SM_1            0x00000002U
-#define  RCC_PLLI2SCFGR_PLLI2SM_2            0x00000004U
-#define  RCC_PLLI2SCFGR_PLLI2SM_3            0x00000008U
-#define  RCC_PLLI2SCFGR_PLLI2SM_4            0x00000010U
-#define  RCC_PLLI2SCFGR_PLLI2SM_5            0x00000020U
-
-#define  RCC_PLLI2SCFGR_PLLI2SN              0x00007FC0U
-#define  RCC_PLLI2SCFGR_PLLI2SN_0            0x00000040U
-#define  RCC_PLLI2SCFGR_PLLI2SN_1            0x00000080U
-#define  RCC_PLLI2SCFGR_PLLI2SN_2            0x00000100U
-#define  RCC_PLLI2SCFGR_PLLI2SN_3            0x00000200U
-#define  RCC_PLLI2SCFGR_PLLI2SN_4            0x00000400U
-#define  RCC_PLLI2SCFGR_PLLI2SN_5            0x00000800U
-#define  RCC_PLLI2SCFGR_PLLI2SN_6            0x00001000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_7            0x00002000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_8            0x00004000U
-
-#define  RCC_PLLI2SCFGR_PLLI2SSRC            0x00400000U
-
-#define  RCC_PLLI2SCFGR_PLLI2SQ              0x0F000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_0            0x01000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_1            0x02000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_2            0x04000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_3            0x08000000U
-
-#define  RCC_PLLI2SCFGR_PLLI2SR              0x70000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_0            0x10000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_1            0x20000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_2            0x40000000U
-
-/********************  Bit definition for RCC_DCKCFGR register  ****************/
-#define  RCC_DCKCFGR_CKDFSDM1ASEL            0x00008000U
-#define  RCC_DCKCFGR_TIMPRE                  0x01000000U
-
-#define  RCC_DCKCFGR_I2S1SRC                 0x06000000U
-#define  RCC_DCKCFGR_I2S1SRC_0               0x02000000U
-#define  RCC_DCKCFGR_I2S1SRC_1               0x04000000U
-
-#define  RCC_DCKCFGR_I2S2SRC                 0x18000000U
-#define  RCC_DCKCFGR_I2S2SRC_0               0x08000000U
-#define  RCC_DCKCFGR_I2S2SRC_1               0x10000000U
-
-#define  RCC_DCKCFGR_CKDFSDM1SEL             0x80000000U
-
-/********************  Bit definition for RCC_CKGATENR register  ***************/
-#define  RCC_CKGATENR_AHB2APB1_CKEN          0x00000001U
-#define  RCC_CKGATENR_AHB2APB2_CKEN          0x00000002U
-#define  RCC_CKGATENR_CM4DBG_CKEN            0x00000004U
-#define  RCC_CKGATENR_SPARE_CKEN             0x00000008U
-#define  RCC_CKGATENR_SRAM_CKEN              0x00000010U
-#define  RCC_CKGATENR_FLITF_CKEN             0x00000020U
-#define  RCC_CKGATENR_RCC_CKEN               0x00000040U
-#define  RCC_CKGATENR_RCC_EVTCTL             0x00000080U
-
-/********************  Bit definition for RCC_DCKCFGR2 register  ***************/
-#define  RCC_DCKCFGR2_FMPI2C1SEL             0x00C00000U
-#define  RCC_DCKCFGR2_FMPI2C1SEL_0           0x00400000U
-#define  RCC_DCKCFGR2_FMPI2C1SEL_1           0x00800000U
-
-#define  RCC_DCKCFGR2_CK48MSEL               0x08000000U
-#define  RCC_DCKCFGR2_SDIOSEL                0x10000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    RNG                                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN                         0x00000004U
-#define RNG_CR_IE                            0x00000008U
-
-/********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY                          0x00000001U
-#define RNG_SR_CECS                          0x00000002U
-#define RNG_SR_SECS                          0x00000004U
-#define RNG_SR_CEIS                          0x00000020U
-#define RNG_SR_SEIS                          0x00000040U
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            0x00400000U
-#define RTC_TR_HT                            0x00300000U
-#define RTC_TR_HT_0                          0x00100000U
-#define RTC_TR_HT_1                          0x00200000U
-#define RTC_TR_HU                            0x000F0000U
-#define RTC_TR_HU_0                          0x00010000U
-#define RTC_TR_HU_1                          0x00020000U
-#define RTC_TR_HU_2                          0x00040000U
-#define RTC_TR_HU_3                          0x00080000U
-#define RTC_TR_MNT                           0x00007000U
-#define RTC_TR_MNT_0                         0x00001000U
-#define RTC_TR_MNT_1                         0x00002000U
-#define RTC_TR_MNT_2                         0x00004000U
-#define RTC_TR_MNU                           0x00000F00U
-#define RTC_TR_MNU_0                         0x00000100U
-#define RTC_TR_MNU_1                         0x00000200U
-#define RTC_TR_MNU_2                         0x00000400U
-#define RTC_TR_MNU_3                         0x00000800U
-#define RTC_TR_ST                            0x00000070U
-#define RTC_TR_ST_0                          0x00000010U
-#define RTC_TR_ST_1                          0x00000020U
-#define RTC_TR_ST_2                          0x00000040U
-#define RTC_TR_SU                            0x0000000FU
-#define RTC_TR_SU_0                          0x00000001U
-#define RTC_TR_SU_1                          0x00000002U
-#define RTC_TR_SU_2                          0x00000004U
-#define RTC_TR_SU_3                          0x00000008U
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            0x00F00000U
-#define RTC_DR_YT_0                          0x00100000U
-#define RTC_DR_YT_1                          0x00200000U
-#define RTC_DR_YT_2                          0x00400000U
-#define RTC_DR_YT_3                          0x00800000U
-#define RTC_DR_YU                            0x000F0000U
-#define RTC_DR_YU_0                          0x00010000U
-#define RTC_DR_YU_1                          0x00020000U
-#define RTC_DR_YU_2                          0x00040000U
-#define RTC_DR_YU_3                          0x00080000U
-#define RTC_DR_WDU                           0x0000E000U
-#define RTC_DR_WDU_0                         0x00002000U
-#define RTC_DR_WDU_1                         0x00004000U
-#define RTC_DR_WDU_2                         0x00008000U
-#define RTC_DR_MT                            0x00001000U
-#define RTC_DR_MU                            0x00000F00U
-#define RTC_DR_MU_0                          0x00000100U
-#define RTC_DR_MU_1                          0x00000200U
-#define RTC_DR_MU_2                          0x00000400U
-#define RTC_DR_MU_3                          0x00000800U
-#define RTC_DR_DT                            0x00000030U
-#define RTC_DR_DT_0                          0x00000010U
-#define RTC_DR_DT_1                          0x00000020U
-#define RTC_DR_DU                            0x0000000FU
-#define RTC_DR_DU_0                          0x00000001U
-#define RTC_DR_DU_1                          0x00000002U
-#define RTC_DR_DU_2                          0x00000004U
-#define RTC_DR_DU_3                          0x00000008U
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           0x00800000U
-#define RTC_CR_OSEL                          0x00600000U
-#define RTC_CR_OSEL_0                        0x00200000U
-#define RTC_CR_OSEL_1                        0x00400000U
-#define RTC_CR_POL                           0x00100000U
-#define RTC_CR_COSEL                         0x00080000U
-#define RTC_CR_BCK                           0x00040000U
-#define RTC_CR_SUB1H                         0x00020000U
-#define RTC_CR_ADD1H                         0x00010000U
-#define RTC_CR_TSIE                          0x00008000U
-#define RTC_CR_WUTIE                         0x00004000U
-#define RTC_CR_ALRBIE                        0x00002000U
-#define RTC_CR_ALRAIE                        0x00001000U
-#define RTC_CR_TSE                           0x00000800U
-#define RTC_CR_WUTE                          0x00000400U
-#define RTC_CR_ALRBE                         0x00000200U
-#define RTC_CR_ALRAE                         0x00000100U
-#define RTC_CR_DCE                           0x00000080U
-#define RTC_CR_FMT                           0x00000040U
-#define RTC_CR_BYPSHAD                       0x00000020U
-#define RTC_CR_REFCKON                       0x00000010U
-#define RTC_CR_TSEDGE                        0x00000008U
-#define RTC_CR_WUCKSEL                       0x00000007U
-#define RTC_CR_WUCKSEL_0                     0x00000001U
-#define RTC_CR_WUCKSEL_1                     0x00000002U
-#define RTC_CR_WUCKSEL_2                     0x00000004U
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      0x00010000U
-#define RTC_ISR_TAMP1F                       0x00002000U
-#define RTC_ISR_TAMP2F                       0x00004000U
-#define RTC_ISR_TSOVF                        0x00001000U
-#define RTC_ISR_TSF                          0x00000800U
-#define RTC_ISR_WUTF                         0x00000400U
-#define RTC_ISR_ALRBF                        0x00000200U
-#define RTC_ISR_ALRAF                        0x00000100U
-#define RTC_ISR_INIT                         0x00000080U
-#define RTC_ISR_INITF                        0x00000040U
-#define RTC_ISR_RSF                          0x00000020U
-#define RTC_ISR_INITS                        0x00000010U
-#define RTC_ISR_SHPF                         0x00000008U
-#define RTC_ISR_WUTWF                        0x00000004U
-#define RTC_ISR_ALRBWF                       0x00000002U
-#define RTC_ISR_ALRAWF                       0x00000001U
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    0x007F0000U
-#define RTC_PRER_PREDIV_S                    0x00007FFFU
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS                       0x00000080U
-#define RTC_CALIBR_DC                        0x0000001FU
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      0x80000000U
-#define RTC_ALRMAR_WDSEL                     0x40000000U
-#define RTC_ALRMAR_DT                        0x30000000U
-#define RTC_ALRMAR_DT_0                      0x10000000U
-#define RTC_ALRMAR_DT_1                      0x20000000U
-#define RTC_ALRMAR_DU                        0x0F000000U
-#define RTC_ALRMAR_DU_0                      0x01000000U
-#define RTC_ALRMAR_DU_1                      0x02000000U
-#define RTC_ALRMAR_DU_2                      0x04000000U
-#define RTC_ALRMAR_DU_3                      0x08000000U
-#define RTC_ALRMAR_MSK3                      0x00800000U
-#define RTC_ALRMAR_PM                        0x00400000U
-#define RTC_ALRMAR_HT                        0x00300000U
-#define RTC_ALRMAR_HT_0                      0x00100000U
-#define RTC_ALRMAR_HT_1                      0x00200000U
-#define RTC_ALRMAR_HU                        0x000F0000U
-#define RTC_ALRMAR_HU_0                      0x00010000U
-#define RTC_ALRMAR_HU_1                      0x00020000U
-#define RTC_ALRMAR_HU_2                      0x00040000U
-#define RTC_ALRMAR_HU_3                      0x00080000U
-#define RTC_ALRMAR_MSK2                      0x00008000U
-#define RTC_ALRMAR_MNT                       0x00007000U
-#define RTC_ALRMAR_MNT_0                     0x00001000U
-#define RTC_ALRMAR_MNT_1                     0x00002000U
-#define RTC_ALRMAR_MNT_2                     0x00004000U
-#define RTC_ALRMAR_MNU                       0x00000F00U
-#define RTC_ALRMAR_MNU_0                     0x00000100U
-#define RTC_ALRMAR_MNU_1                     0x00000200U
-#define RTC_ALRMAR_MNU_2                     0x00000400U
-#define RTC_ALRMAR_MNU_3                     0x00000800U
-#define RTC_ALRMAR_MSK1                      0x00000080U
-#define RTC_ALRMAR_ST                        0x00000070U
-#define RTC_ALRMAR_ST_0                      0x00000010U
-#define RTC_ALRMAR_ST_1                      0x00000020U
-#define RTC_ALRMAR_ST_2                      0x00000040U
-#define RTC_ALRMAR_SU                        0x0000000FU
-#define RTC_ALRMAR_SU_0                      0x00000001U
-#define RTC_ALRMAR_SU_1                      0x00000002U
-#define RTC_ALRMAR_SU_2                      0x00000004U
-#define RTC_ALRMAR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      0x80000000U
-#define RTC_ALRMBR_WDSEL                     0x40000000U
-#define RTC_ALRMBR_DT                        0x30000000U
-#define RTC_ALRMBR_DT_0                      0x10000000U
-#define RTC_ALRMBR_DT_1                      0x20000000U
-#define RTC_ALRMBR_DU                        0x0F000000U
-#define RTC_ALRMBR_DU_0                      0x01000000U
-#define RTC_ALRMBR_DU_1                      0x02000000U
-#define RTC_ALRMBR_DU_2                      0x04000000U
-#define RTC_ALRMBR_DU_3                      0x08000000U
-#define RTC_ALRMBR_MSK3                      0x00800000U
-#define RTC_ALRMBR_PM                        0x00400000U
-#define RTC_ALRMBR_HT                        0x00300000U
-#define RTC_ALRMBR_HT_0                      0x00100000U
-#define RTC_ALRMBR_HT_1                      0x00200000U
-#define RTC_ALRMBR_HU                        0x000F0000U
-#define RTC_ALRMBR_HU_0                      0x00010000U
-#define RTC_ALRMBR_HU_1                      0x00020000U
-#define RTC_ALRMBR_HU_2                      0x00040000U
-#define RTC_ALRMBR_HU_3                      0x00080000U
-#define RTC_ALRMBR_MSK2                      0x00008000U
-#define RTC_ALRMBR_MNT                       0x00007000U
-#define RTC_ALRMBR_MNT_0                     0x00001000U
-#define RTC_ALRMBR_MNT_1                     0x00002000U
-#define RTC_ALRMBR_MNT_2                     0x00004000U
-#define RTC_ALRMBR_MNU                       0x00000F00U
-#define RTC_ALRMBR_MNU_0                     0x00000100U
-#define RTC_ALRMBR_MNU_1                     0x00000200U
-#define RTC_ALRMBR_MNU_2                     0x00000400U
-#define RTC_ALRMBR_MNU_3                     0x00000800U
-#define RTC_ALRMBR_MSK1                      0x00000080U
-#define RTC_ALRMBR_ST                        0x00000070U
-#define RTC_ALRMBR_ST_0                      0x00000010U
-#define RTC_ALRMBR_ST_1                      0x00000020U
-#define RTC_ALRMBR_ST_2                      0x00000040U
-#define RTC_ALRMBR_SU                        0x0000000FU
-#define RTC_ALRMBR_SU_0                      0x00000001U
-#define RTC_ALRMBR_SU_1                      0x00000002U
-#define RTC_ALRMBR_SU_2                      0x00000004U
-#define RTC_ALRMBR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          0x000000FFU
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           0x0000FFFFU
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     0x00007FFFU
-#define RTC_SHIFTR_ADD1S                     0x80000000U
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          0x00400000U
-#define RTC_TSTR_HT                          0x00300000U
-#define RTC_TSTR_HT_0                        0x00100000U
-#define RTC_TSTR_HT_1                        0x00200000U
-#define RTC_TSTR_HU                          0x000F0000U
-#define RTC_TSTR_HU_0                        0x00010000U
-#define RTC_TSTR_HU_1                        0x00020000U
-#define RTC_TSTR_HU_2                        0x00040000U
-#define RTC_TSTR_HU_3                        0x00080000U
-#define RTC_TSTR_MNT                         0x00007000U
-#define RTC_TSTR_MNT_0                       0x00001000U
-#define RTC_TSTR_MNT_1                       0x00002000U
-#define RTC_TSTR_MNT_2                       0x00004000U
-#define RTC_TSTR_MNU                         0x00000F00U
-#define RTC_TSTR_MNU_0                       0x00000100U
-#define RTC_TSTR_MNU_1                       0x00000200U
-#define RTC_TSTR_MNU_2                       0x00000400U
-#define RTC_TSTR_MNU_3                       0x00000800U
-#define RTC_TSTR_ST                          0x00000070U
-#define RTC_TSTR_ST_0                        0x00000010U
-#define RTC_TSTR_ST_1                        0x00000020U
-#define RTC_TSTR_ST_2                        0x00000040U
-#define RTC_TSTR_SU                          0x0000000FU
-#define RTC_TSTR_SU_0                        0x00000001U
-#define RTC_TSTR_SU_1                        0x00000002U
-#define RTC_TSTR_SU_2                        0x00000004U
-#define RTC_TSTR_SU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         0x0000E000U
-#define RTC_TSDR_WDU_0                       0x00002000U
-#define RTC_TSDR_WDU_1                       0x00004000U
-#define RTC_TSDR_WDU_2                       0x00008000U
-#define RTC_TSDR_MT                          0x00001000U
-#define RTC_TSDR_MU                          0x00000F00U
-#define RTC_TSDR_MU_0                        0x00000100U
-#define RTC_TSDR_MU_1                        0x00000200U
-#define RTC_TSDR_MU_2                        0x00000400U
-#define RTC_TSDR_MU_3                        0x00000800U
-#define RTC_TSDR_DT                          0x00000030U
-#define RTC_TSDR_DT_0                        0x00000010U
-#define RTC_TSDR_DT_1                        0x00000020U
-#define RTC_TSDR_DU                          0x0000000FU
-#define RTC_TSDR_DU_0                        0x00000001U
-#define RTC_TSDR_DU_1                        0x00000002U
-#define RTC_TSDR_DU_2                        0x00000004U
-#define RTC_TSDR_DU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        0x00008000U
-#define RTC_CALR_CALW8                       0x00004000U
-#define RTC_CALR_CALW16                      0x00002000U
-#define RTC_CALR_CALM                        0x000001FFU
-#define RTC_CALR_CALM_0                      0x00000001U
-#define RTC_CALR_CALM_1                      0x00000002U
-#define RTC_CALR_CALM_2                      0x00000004U
-#define RTC_CALR_CALM_3                      0x00000008U
-#define RTC_CALR_CALM_4                      0x00000010U
-#define RTC_CALR_CALM_5                      0x00000020U
-#define RTC_CALR_CALM_6                      0x00000040U
-#define RTC_CALR_CALM_7                      0x00000080U
-#define RTC_CALR_CALM_8                      0x00000100U
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               0x00040000U
-#define RTC_TAFCR_TSINSEL                    0x00020000U
-#define RTC_TAFCR_TAMPINSEL                  0x00010000U
-#define RTC_TAFCR_TAMPPUDIS                  0x00008000U
-#define RTC_TAFCR_TAMPPRCH                   0x00006000U
-#define RTC_TAFCR_TAMPPRCH_0                 0x00002000U
-#define RTC_TAFCR_TAMPPRCH_1                 0x00004000U
-#define RTC_TAFCR_TAMPFLT                    0x00001800U
-#define RTC_TAFCR_TAMPFLT_0                  0x00000800U
-#define RTC_TAFCR_TAMPFLT_1                  0x00001000U
-#define RTC_TAFCR_TAMPFREQ                   0x00000700U
-#define RTC_TAFCR_TAMPFREQ_0                 0x00000100U
-#define RTC_TAFCR_TAMPFREQ_1                 0x00000200U
-#define RTC_TAFCR_TAMPFREQ_2                 0x00000400U
-#define RTC_TAFCR_TAMPTS                     0x00000080U
-#define RTC_TAFCR_TAMP2TRG                   0x00000010U
-#define RTC_TAFCR_TAMP2E                     0x00000008U
-#define RTC_TAFCR_TAMPIE                     0x00000004U
-#define RTC_TAFCR_TAMP1TRG                   0x00000002U
-#define RTC_TAFCR_TAMP1E                     0x00000001U
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  0x0F000000U
-#define RTC_ALRMASSR_MASKSS_0                0x01000000U
-#define RTC_ALRMASSR_MASKSS_1                0x02000000U
-#define RTC_ALRMASSR_MASKSS_2                0x04000000U
-#define RTC_ALRMASSR_MASKSS_3                0x08000000U
-#define RTC_ALRMASSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
-#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
-#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
-#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
-#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
-#define RTC_ALRMBSSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           0xFFFFFFFFU
-
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          SD host Interface                                 */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SDIO_POWER register  ******************/
-#define  SDIO_POWER_PWRCTRL                  0x03U               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDIO_POWER_PWRCTRL_0                0x01U               /*!<Bit 0 */
-#define  SDIO_POWER_PWRCTRL_1                0x02U               /*!<Bit 1 */
-
-/******************  Bit definition for SDIO_CLKCR register  ******************/
-#define  SDIO_CLKCR_CLKDIV                   0x00FFU            /*!<Clock divide factor             */
-#define  SDIO_CLKCR_CLKEN                    0x0100U            /*!<Clock enable bit                */
-#define  SDIO_CLKCR_PWRSAV                   0x0200U            /*!<Power saving configuration bit  */
-#define  SDIO_CLKCR_BYPASS                   0x0400U            /*!<Clock divider bypass enable bit */
-
-#define  SDIO_CLKCR_WIDBUS                   0x1800U            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDIO_CLKCR_WIDBUS_0                 0x0800U            /*!<Bit 0 */
-#define  SDIO_CLKCR_WIDBUS_1                 0x1000U            /*!<Bit 1 */
-
-#define  SDIO_CLKCR_NEGEDGE                  0x2000U            /*!<SDIO_CK dephasing selection bit */
-#define  SDIO_CLKCR_HWFC_EN                  0x4000U            /*!<HW Flow Control enable          */
-
-/*******************  Bit definition for SDIO_ARG register  *******************/
-#define  SDIO_ARG_CMDARG                     0xFFFFFFFFU            /*!<Command argument */
-
-/*******************  Bit definition for SDIO_CMD register  *******************/
-#define  SDIO_CMD_CMDINDEX                   0x003FU            /*!<Command Index                               */
-
-#define  SDIO_CMD_WAITRESP                   0x00C0U            /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDIO_CMD_WAITRESP_0                 0x0040U            /*!< Bit 0 */
-#define  SDIO_CMD_WAITRESP_1                 0x0080U            /*!< Bit 1 */
-
-#define  SDIO_CMD_WAITINT                    0x0100U            /*!<CPSM Waits for Interrupt Request                               */
-#define  SDIO_CMD_WAITPEND                   0x0200U            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDIO_CMD_CPSMEN                     0x0400U            /*!<Command path state machine (CPSM) Enable bit                   */
-#define  SDIO_CMD_SDIOSUSPEND                0x0800U            /*!<SD I/O suspend command                                         */
-#define  SDIO_CMD_ENCMDCOMPL                 0x1000U            /*!<Enable CMD completion                                          */
-#define  SDIO_CMD_NIEN                       0x2000U            /*!<Not Interrupt Enable */
-#define  SDIO_CMD_CEATACMD                   0x4000U            /*!<CE-ATA command       */
-
-/*****************  Bit definition for SDIO_RESPCMD register  *****************/
-#define  SDIO_RESPCMD_RESPCMD                0x3FU               /*!<Response command index */
-
-/******************  Bit definition for SDIO_RESP0 register  ******************/
-#define  SDIO_RESP0_CARDSTATUS0              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP1 register  ******************/
-#define  SDIO_RESP1_CARDSTATUS1              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP2 register  ******************/
-#define  SDIO_RESP2_CARDSTATUS2              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP3 register  ******************/
-#define  SDIO_RESP3_CARDSTATUS3              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP4 register  ******************/
-#define  SDIO_RESP4_CARDSTATUS4              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_DTIMER register  *****************/
-#define  SDIO_DTIMER_DATATIME                0xFFFFFFFFU        /*!<Data timeout period. */
-
-/******************  Bit definition for SDIO_DLEN register  *******************/
-#define  SDIO_DLEN_DATALENGTH                0x01FFFFFFU        /*!<Data length value    */
-
-/******************  Bit definition for SDIO_DCTRL register  ******************/
-#define  SDIO_DCTRL_DTEN                     0x0001U            /*!<Data transfer enabled bit         */
-#define  SDIO_DCTRL_DTDIR                    0x0002U            /*!<Data transfer direction selection */
-#define  SDIO_DCTRL_DTMODE                   0x0004U            /*!<Data transfer mode selection      */
-#define  SDIO_DCTRL_DMAEN                    0x0008U            /*!<DMA enabled bit                   */
-
-#define  SDIO_DCTRL_DBLOCKSIZE               0x00F0U            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDIO_DCTRL_DBLOCKSIZE_0             0x0010U            /*!<Bit 0 */
-#define  SDIO_DCTRL_DBLOCKSIZE_1             0x0020U            /*!<Bit 1 */
-#define  SDIO_DCTRL_DBLOCKSIZE_2             0x0040U            /*!<Bit 2 */
-#define  SDIO_DCTRL_DBLOCKSIZE_3             0x0080U            /*!<Bit 3 */
-
-#define  SDIO_DCTRL_RWSTART                  0x0100U            /*!<Read wait start         */
-#define  SDIO_DCTRL_RWSTOP                   0x0200U            /*!<Read wait stop          */
-#define  SDIO_DCTRL_RWMOD                    0x0400U            /*!<Read wait mode          */
-#define  SDIO_DCTRL_SDIOEN                   0x0800U            /*!<SD I/O enable functions */
-
-/******************  Bit definition for SDIO_DCOUNT register  *****************/
-#define  SDIO_DCOUNT_DATACOUNT               0x01FFFFFFU        /*!<Data count value */
-
-/******************  Bit definition for SDIO_STA register  ********************/
-#define  SDIO_STA_CCRCFAIL                   0x00000001U        /*!<Command response received (CRC check failed)  */
-#define  SDIO_STA_DCRCFAIL                   0x00000002U        /*!<Data block sent/received (CRC check failed)   */
-#define  SDIO_STA_CTIMEOUT                   0x00000004U        /*!<Command response timeout                      */
-#define  SDIO_STA_DTIMEOUT                   0x00000008U        /*!<Data timeout                                  */
-#define  SDIO_STA_TXUNDERR                   0x00000010U        /*!<Transmit FIFO underrun error                  */
-#define  SDIO_STA_RXOVERR                    0x00000020U        /*!<Received FIFO overrun error                   */
-#define  SDIO_STA_CMDREND                    0x00000040U        /*!<Command response received (CRC check passed)  */
-#define  SDIO_STA_CMDSENT                    0x00000080U        /*!<Command sent (no response required)           */
-#define  SDIO_STA_DATAEND                    0x00000100U        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
-#define  SDIO_STA_STBITERR                   0x00000200U        /*!<Start bit not detected on all data signals in wide bus mode */
-#define  SDIO_STA_DBCKEND                    0x00000400U        /*!<Data block sent/received (CRC check passed)   */
-#define  SDIO_STA_CMDACT                     0x00000800U        /*!<Command transfer in progress                  */
-#define  SDIO_STA_TXACT                      0x00001000U        /*!<Data transmit in progress                     */
-#define  SDIO_STA_RXACT                      0x00002000U        /*!<Data receive in progress                      */
-#define  SDIO_STA_TXFIFOHE                   0x00004000U        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDIO_STA_RXFIFOHF                   0x00008000U        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDIO_STA_TXFIFOF                    0x00010000U        /*!<Transmit FIFO full                            */
-#define  SDIO_STA_RXFIFOF                    0x00020000U        /*!<Receive FIFO full                             */
-#define  SDIO_STA_TXFIFOE                    0x00040000U        /*!<Transmit FIFO empty                           */
-#define  SDIO_STA_RXFIFOE                    0x00080000U        /*!<Receive FIFO empty                            */
-#define  SDIO_STA_TXDAVL                     0x00100000U        /*!<Data available in transmit FIFO               */
-#define  SDIO_STA_RXDAVL                     0x00200000U        /*!<Data available in receive FIFO                */
-#define  SDIO_STA_SDIOIT                     0x00400000U        /*!<SDIO interrupt received                       */
-#define  SDIO_STA_CEATAEND                   0x00800000U        /*!<CE-ATA command completion signal received for CMD61 */
-
-/*******************  Bit definition for SDIO_ICR register  *******************/
-#define  SDIO_ICR_CCRCFAILC                  0x00000001U        /*!<CCRCFAIL flag clear bit */
-#define  SDIO_ICR_DCRCFAILC                  0x00000002U        /*!<DCRCFAIL flag clear bit */
-#define  SDIO_ICR_CTIMEOUTC                  0x00000004U        /*!<CTIMEOUT flag clear bit */
-#define  SDIO_ICR_DTIMEOUTC                  0x00000008U        /*!<DTIMEOUT flag clear bit */
-#define  SDIO_ICR_TXUNDERRC                  0x00000010U        /*!<TXUNDERR flag clear bit */
-#define  SDIO_ICR_RXOVERRC                   0x00000020U        /*!<RXOVERR flag clear bit  */
-#define  SDIO_ICR_CMDRENDC                   0x00000040U        /*!<CMDREND flag clear bit  */
-#define  SDIO_ICR_CMDSENTC                   0x00000080U        /*!<CMDSENT flag clear bit  */
-#define  SDIO_ICR_DATAENDC                   0x00000100U        /*!<DATAEND flag clear bit  */
-#define  SDIO_ICR_STBITERRC                  0x00000200U        /*!<STBITERR flag clear bit */
-#define  SDIO_ICR_DBCKENDC                   0x00000400U        /*!<DBCKEND flag clear bit  */
-#define  SDIO_ICR_SDIOITC                    0x00400000U        /*!<SDIOIT flag clear bit   */
-#define  SDIO_ICR_CEATAENDC                  0x00800000U        /*!<CEATAEND flag clear bit */
-
-/******************  Bit definition for SDIO_MASK register  *******************/
-#define  SDIO_MASK_CCRCFAILIE                0x00000001U        /*!<Command CRC Fail Interrupt Enable          */
-#define  SDIO_MASK_DCRCFAILIE                0x00000002U        /*!<Data CRC Fail Interrupt Enable             */
-#define  SDIO_MASK_CTIMEOUTIE                0x00000004U        /*!<Command TimeOut Interrupt Enable           */
-#define  SDIO_MASK_DTIMEOUTIE                0x00000008U        /*!<Data TimeOut Interrupt Enable              */
-#define  SDIO_MASK_TXUNDERRIE                0x00000010U        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
-#define  SDIO_MASK_RXOVERRIE                 0x00000020U        /*!<Rx FIFO OverRun Error Interrupt Enable     */
-#define  SDIO_MASK_CMDRENDIE                 0x00000040U        /*!<Command Response Received Interrupt Enable */
-#define  SDIO_MASK_CMDSENTIE                 0x00000080U        /*!<Command Sent Interrupt Enable              */
-#define  SDIO_MASK_DATAENDIE                 0x00000100U        /*!<Data End Interrupt Enable                  */
-#define  SDIO_MASK_STBITERRIE                0x00000200U        /*!<Start Bit Error Interrupt Enable           */
-#define  SDIO_MASK_DBCKENDIE                 0x00000400U        /*!<Data Block End Interrupt Enable            */
-#define  SDIO_MASK_CMDACTIE                  0x00000800U        /*!<CCommand Acting Interrupt Enable           */
-#define  SDIO_MASK_TXACTIE                   0x00001000U        /*!<Data Transmit Acting Interrupt Enable      */
-#define  SDIO_MASK_RXACTIE                   0x00002000U        /*!<Data receive acting interrupt enabled      */
-#define  SDIO_MASK_TXFIFOHEIE                0x00004000U        /*!<Tx FIFO Half Empty interrupt Enable        */
-#define  SDIO_MASK_RXFIFOHFIE                0x00008000U        /*!<Rx FIFO Half Full interrupt Enable         */
-#define  SDIO_MASK_TXFIFOFIE                 0x00010000U        /*!<Tx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_RXFIFOFIE                 0x00020000U        /*!<Rx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_TXFIFOEIE                 0x00040000U        /*!<Tx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_RXFIFOEIE                 0x00080000U        /*!<Rx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_TXDAVLIE                  0x00100000U        /*!<Data available in Tx FIFO interrupt Enable */
-#define  SDIO_MASK_RXDAVLIE                  0x00200000U        /*!<Data available in Rx FIFO interrupt Enable */
-#define  SDIO_MASK_SDIOITIE                  0x00400000U        /*!<SDIO Mode Interrupt Received interrupt Enable */
-#define  SDIO_MASK_CEATAENDIE                0x00800000U        /*!<CE-ATA command completion signal received Interrupt Enable */
-
-/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
-#define  SDIO_FIFOCNT_FIFOCOUNT              0x00FFFFFFU        /*!<Remaining number of words to be written to or read from the FIFO */
-
-/******************  Bit definition for SDIO_FIFO register  *******************/
-#define  SDIO_FIFO_FIFODATA                  0xFFFFFFFFU        /*!<Receive and transmit FIFO data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        0x00000001U            /*!<Clock Phase      */
-#define  SPI_CR1_CPOL                        0x00000002U            /*!<Clock Polarity   */
-#define  SPI_CR1_MSTR                        0x00000004U            /*!<Master Selection */
-
-#define  SPI_CR1_BR                          0x00000038U            /*!<BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        0x00000008U            /*!<Bit 0 */
-#define  SPI_CR1_BR_1                        0x00000010U            /*!<Bit 1 */
-#define  SPI_CR1_BR_2                        0x00000020U            /*!<Bit 2 */
-
-#define  SPI_CR1_SPE                         0x00000040U            /*!<SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    0x00000080U            /*!<Frame Format                        */
-#define  SPI_CR1_SSI                         0x00000100U            /*!<Internal slave select               */
-#define  SPI_CR1_SSM                         0x00000200U            /*!<Software slave management           */
-#define  SPI_CR1_RXONLY                      0x00000400U            /*!<Receive only                        */
-#define  SPI_CR1_DFF                         0x00000800U            /*!<Data Frame Format                   */
-#define  SPI_CR1_CRCNEXT                     0x00001000U            /*!<Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       0x00002000U            /*!<Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      0x00004000U            /*!<Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    0x00008000U            /*!<Bidirectional data mode enable      */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     0x00000001U               /*!<Rx Buffer DMA Enable                 */
-#define  SPI_CR2_TXDMAEN                     0x00000002U               /*!<Tx Buffer DMA Enable                 */
-#define  SPI_CR2_SSOE                        0x00000004U               /*!<SS Output Enable                     */
-#define  SPI_CR2_FRF                         0x00000010U               /*!<Frame Format                         */
-#define  SPI_CR2_ERRIE                       0x00000020U               /*!<Error Interrupt Enable               */
-#define  SPI_CR2_RXNEIE                      0x00000040U               /*!<RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       0x00000080U               /*!<Tx buffer Empty Interrupt Enable     */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         0x00000001U               /*!<Receive buffer Not Empty */
-#define  SPI_SR_TXE                          0x00000002U               /*!<Transmit buffer Empty    */
-#define  SPI_SR_CHSIDE                       0x00000004U               /*!<Channel side             */
-#define  SPI_SR_UDR                          0x00000008U               /*!<Underrun flag            */
-#define  SPI_SR_CRCERR                       0x00000010U               /*!<CRC Error flag           */
-#define  SPI_SR_MODF                         0x00000020U               /*!<Mode fault               */
-#define  SPI_SR_OVR                          0x00000040U               /*!<Overrun flag             */
-#define  SPI_SR_BSY                          0x00000080U               /*!<Busy flag                */
-#define  SPI_SR_FRE                          0x00000100U               /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           0x0000FFFFU            /*!<Data Register           */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   0x0000FFFFU            /*!<CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    0x0000FFFFU            /*!<Rx CRC Register         */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    0x0000FFFFU            /*!<Tx CRC Register         */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   0x00000001U            /*!<Channel length (number of bits per audio channel) */
-
-#define  SPI_I2SCFGR_DATLEN                  0x00000006U            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define  SPI_I2SCFGR_DATLEN_0                0x00000002U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                0x00000004U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_CKPOL                   0x00000008U            /*!<steady state clock polarity               */
-
-#define  SPI_I2SCFGR_I2SSTD                  0x00000030U            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U            /*!<PCM frame synchronization                 */
-
-#define  SPI_I2SCFGR_I2SCFG                  0x00000300U            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_I2SE                    0x00000400U            /*!<I2S Enable         */
-#define  SPI_I2SCFGR_I2SMOD                  0x00000800U            /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    0x000000FFU            /*!<I2S Linear prescaler         */
-#define  SPI_I2SPR_ODD                       0x00000100U            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     0x00000200U            /*!<Master Clock Output Enable   */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 SYSCFG                                     */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
-#define SYSCFG_MEMRMP_MEM_MODE          0x00000007U /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        0x00000001U
-#define SYSCFG_MEMRMP_MEM_MODE_1        0x00000002U
-#define SYSCFG_MEMRMP_MEM_MODE_2        0x00000004U
-
-#define SYSCFG_SWP_FSMC                  0x00000C00U /*!< FSMC memory mapping swap */
-/******************  Bit definition for SYSCFG_PMC register  ******************/
-#define SYSCFG_PMC_ADC1DC2              0x00010000U /*!< Refer to AN4073 on how to use this bit  */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
-/** 
-  * @brief   EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         0x0003U /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         0x0004U /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         0x0005U /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         0x0006U /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
-
-/** 
-  * @brief   EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         0x0030U /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         0x0040U /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         0x0050U /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         0x0060U /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
-
-/** 
-  * @brief   EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         0x0300U /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         0x0400U /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         0x0500U /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         0x0600U /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
-
-/** 
-  * @brief   EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         0x3000U /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         0x4000U /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         0x5000U /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         0x6000U /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
-/** 
-  * @brief   EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         0x0003U /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         0x0004U /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         0x0005U /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         0x0006U /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
-
-/** 
-  * @brief   EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         0x0030U /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         0x0040U /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         0x0050U /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         0x0060U /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
-
-/** 
-  * @brief   EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         0x0300U /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         0x0400U /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         0x0500U /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         0x0600U /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
-
-/** 
-  * @brief   EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         0x3000U /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         0x4000U /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         0x5000U /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         0x6000U /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
-
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
-
-/** 
-  * @brief   EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         0x0003U /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         0x0004U /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         0x0005U /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         0x0006U /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
-
-/** 
-  * @brief   EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         0x0030U /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         0x0040U /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         0x0050U /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         0x0060U /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
-
-/** 
-  * @brief   EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        0x0300U /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        0x0400U /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        0x0500U /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        0x0600U /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
-
-/** 
-  * @brief   EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        0x3000U /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        0x4000U /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        0x5000U /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        0x6000U /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
-/** 
-  * @brief   EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        0x0003U /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        0x0004U /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        0x0005U /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        0x0006U /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
-
-/** 
-  * @brief   EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        0x0030U /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        0x0040U /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        0x0050U /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        0x0060U /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
-
-/** 
-  * @brief   EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        0x0300U /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        0x0400U /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        0x0500U /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        0x0600U /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
-
-/** 
-  * @brief   EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        0x3000U /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        0x4000U /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        0x5000U /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        0x6000U /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
-
-/******************  Bit definition for SYSCFG_CMPCR register  ****************/
-#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell ready flag */
-#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell power-down */
-
-/******************  Bit definition for SYSCFG_CFGR register  *****************/
-#define SYSCFG_CFGR_FMPI2C1_SCL         0x00000001U /*!<FM+ drive capability for FMPI2C1_SCL pin */
-#define SYSCFG_CFGR_FMPI2C1_SDA         0x00000002U /*!<FM+ drive capability for FMPI2C1_SDA pin */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    TIM                                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
-#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
-#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
-#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
-#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
-
-#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
-
-#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
-
-#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        0x0001U            /*!<Capture/Compare Preloaded Control        */
-#define  TIM_CR2_CCUS                        0x0004U            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        0x0008U            /*!<Capture/Compare DMA Selection            */
-
-#define  TIM_CR2_MMS                         0x0070U            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
-#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
-#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
-#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        0x0007U            /*!<SMS[2:0] bits (Slave mode selection)    */
-#define  TIM_SMCR_SMS_0                      0x0001U            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      0x0002U            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      0x0004U            /*!<Bit 2 */
-
-#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
-#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
-
-#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
-
-#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
-
-#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
-#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
-#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
-#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
-#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
-#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
-#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
-#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
-#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
-#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
-#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
-#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
-#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
-#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
-#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
-#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
-#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
-#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
-#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          0x01U               /*!<Update Generation                         */
-#define  TIM_EGR_CC1G                        0x02U               /*!<Capture/Compare 1 Generation              */
-#define  TIM_EGR_CC2G                        0x04U               /*!<Capture/Compare 2 Generation              */
-#define  TIM_EGR_CC3G                        0x08U               /*!<Capture/Compare 3 Generation              */
-#define  TIM_EGR_CC4G                        0x10U               /*!<Capture/Compare 4 Generation              */
-#define  TIM_EGR_COMG                        0x20U               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          0x40U               /*!<Trigger Generation                        */
-#define  TIM_EGR_BG                          0x80U               /*!<Break Generation                          */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      0x0003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    0x0001U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    0x0002U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC1FE                     0x0004U            /*!<Output Compare 1 Fast enable                 */
-#define  TIM_CCMR1_OC1PE                     0x0008U            /*!<Output Compare 1 Preload enable              */
-
-#define  TIM_CCMR1_OC1M                      0x0070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define  TIM_CCMR1_OC1M_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    0x0040U            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC1CE                     0x0080U            /*!<Output Compare 1Clear Enable                 */
-
-#define  TIM_CCMR1_CC2S                      0x0300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    0x0100U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    0x0200U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC2FE                     0x0400U            /*!<Output Compare 2 Fast enable                 */
-#define  TIM_CCMR1_OC2PE                     0x0800U            /*!<Output Compare 2 Preload enable              */
-
-#define  TIM_CCMR1_OC2M                      0x7000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define  TIM_CCMR1_OC2M_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    0x4000U            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC2CE                     0x8000U            /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      0x0003U            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define  TIM_CCMR2_CC3S_0                    0x0001U            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    0x0002U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC3FE                     0x0004U            /*!<Output Compare 3 Fast enable           */
-#define  TIM_CCMR2_OC3PE                     0x0008U            /*!<Output Compare 3 Preload enable        */
-
-#define  TIM_CCMR2_OC3M                      0x0070U            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    0x0040U            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC3CE                     0x0080U            /*!<Output Compare 3 Clear Enable */
-
-#define  TIM_CCMR2_CC4S                      0x0300U            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    0x0100U            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    0x0200U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC4FE                     0x0400U            /*!<Output Compare 4 Fast enable    */
-#define  TIM_CCMR2_OC4PE                     0x0800U            /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR2_OC4M                      0x7000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    0x4000U            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       0x0001U            /*!<Capture/Compare 1 output enable                 */
-#define  TIM_CCER_CC1P                       0x0002U            /*!<Capture/Compare 1 output Polarity               */
-#define  TIM_CCER_CC1NE                      0x0004U            /*!<Capture/Compare 1 Complementary output enable   */
-#define  TIM_CCER_CC1NP                      0x0008U            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       0x0010U            /*!<Capture/Compare 2 output enable                 */
-#define  TIM_CCER_CC2P                       0x0020U            /*!<Capture/Compare 2 output Polarity               */
-#define  TIM_CCER_CC2NE                      0x0040U            /*!<Capture/Compare 2 Complementary output enable   */
-#define  TIM_CCER_CC2NP                      0x0080U            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       0x0100U            /*!<Capture/Compare 3 output enable                 */
-#define  TIM_CCER_CC3P                       0x0200U            /*!<Capture/Compare 3 output Polarity               */
-#define  TIM_CCER_CC3NE                      0x0400U            /*!<Capture/Compare 3 Complementary output enable   */
-#define  TIM_CCER_CC3NP                      0x0800U            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       0x1000U            /*!<Capture/Compare 4 output enable                 */
-#define  TIM_CCER_CC4P                       0x2000U            /*!<Capture/Compare 4 output Polarity               */
-#define  TIM_CCER_CC4NP                      0x8000U            /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         0xFFU               /*!<Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
-
-/*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        0x00FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      0x0001U            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      0x0002U            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      0x0004U            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      0x0008U            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      0x0010U            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      0x0020U            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      0x0040U            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      0x0080U            /*!<Bit 7 */
-
-#define  TIM_BDTR_LOCK                       0x0300U            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     0x0100U            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     0x0200U            /*!<Bit 1 */
-
-#define  TIM_BDTR_OSSI                       0x0400U            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       0x0800U            /*!<Off-State Selection for Run mode  */
-#define  TIM_BDTR_BKE                        0x1000U            /*!<Break enable                      */
-#define  TIM_BDTR_BKP                        0x2000U            /*!<Break Polarity                    */
-#define  TIM_BDTR_AOE                        0x4000U            /*!<Automatic Output enable           */
-#define  TIM_BDTR_MOE                        0x8000U            /*!<Main Output enable                */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
-
-#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
-#define TIM_OR_ITR1_RMP                      0x0C00U            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
-#define TIM_OR_ITR1_RMP_0                    0x0400U            /*!<Bit 0 */
-#define TIM_OR_ITR1_RMP_1                    0x0800U            /*!<Bit 1 */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*         Universal Synchronous Asynchronous Receiver Transmitter            */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         0x0001U            /*!<Parity Error                 */
-#define  USART_SR_FE                         0x0002U            /*!<Framing Error                */
-#define  USART_SR_NE                         0x0004U            /*!<Noise Error Flag             */
-#define  USART_SR_ORE                        0x0008U            /*!<OverRun Error                */
-#define  USART_SR_IDLE                       0x0010U            /*!<IDLE line detected           */
-#define  USART_SR_RXNE                       0x0020U            /*!<Read Data Register Not Empty */
-#define  USART_SR_TC                         0x0040U            /*!<Transmission Complete        */
-#define  USART_SR_TXE                        0x0080U            /*!<Transmit Data Register Empty */
-#define  USART_SR_LBD                        0x0100U            /*!<LIN Break Detection Flag     */
-#define  USART_SR_CTS                        0x0200U            /*!<CTS Flag                     */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         0x01FFU            /*!<Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_Fraction              0x000FU            /*!<Fraction of USARTDIV */
-#define  USART_BRR_DIV_Mantissa              0xFFF0U            /*!<Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       0x0001U            /*!<Send Break                             */
-#define  USART_CR1_RWU                       0x0002U            /*!<Receiver wakeup                        */
-#define  USART_CR1_RE                        0x0004U            /*!<Receiver Enable                        */
-#define  USART_CR1_TE                        0x0008U            /*!<Transmitter Enable                     */
-#define  USART_CR1_IDLEIE                    0x0010U            /*!<IDLE Interrupt Enable                  */
-#define  USART_CR1_RXNEIE                    0x0020U            /*!<RXNE Interrupt Enable                  */
-#define  USART_CR1_TCIE                      0x0040U            /*!<Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     0x0080U            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PEIE                      0x0100U            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PS                        0x0200U            /*!<Parity Selection                       */
-#define  USART_CR1_PCE                       0x0400U            /*!<Parity Control Enable                  */
-#define  USART_CR1_WAKE                      0x0800U            /*!<Wakeup method                          */
-#define  USART_CR1_M                         0x1000U            /*!<Word length                            */
-#define  USART_CR1_UE                        0x2000U            /*!<USART Enable                           */
-#define  USART_CR1_OVER8                     0x8000U            /*!<USART Oversampling by 8 enable         */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       0x000FU            /*!<Address of the USART node            */
-#define  USART_CR2_LBDL                      0x0020U            /*!<LIN Break Detection Length           */
-#define  USART_CR2_LBDIE                     0x0040U            /*!<LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      0x0100U            /*!<Last Bit Clock pulse                 */
-#define  USART_CR2_CPHA                      0x0200U            /*!<Clock Phase                          */
-#define  USART_CR2_CPOL                      0x0400U            /*!<Clock Polarity                       */
-#define  USART_CR2_CLKEN                     0x0800U            /*!<Clock Enable                         */
-
-#define  USART_CR2_STOP                      0x3000U            /*!<STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    0x1000U            /*!<Bit 0 */
-#define  USART_CR2_STOP_1                    0x2000U            /*!<Bit 1 */
-
-#define  USART_CR2_LINEN                     0x4000U            /*!<LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       0x0001U            /*!<Error Interrupt Enable      */
-#define  USART_CR3_IREN                      0x0002U            /*!<IrDA mode Enable            */
-#define  USART_CR3_IRLP                      0x0004U            /*!<IrDA Low-Power              */
-#define  USART_CR3_HDSEL                     0x0008U            /*!<Half-Duplex Selection       */
-#define  USART_CR3_NACK                      0x0010U            /*!<Smartcard NACK enable       */
-#define  USART_CR3_SCEN                      0x0020U            /*!<Smartcard mode enable       */
-#define  USART_CR3_DMAR                      0x0040U            /*!<DMA Enable Receiver         */
-#define  USART_CR3_DMAT                      0x0080U            /*!<DMA Enable Transmitter      */
-#define  USART_CR3_RTSE                      0x0100U            /*!<RTS Enable                  */
-#define  USART_CR3_CTSE                      0x0200U            /*!<CTS Enable                  */
-#define  USART_CR3_CTSIE                     0x0400U            /*!<CTS Interrupt Enable        */
-#define  USART_CR3_ONEBIT                    0x0800U            /*!<USART One bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      0x00FFU            /*!<PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    0x0001U            /*!<Bit 0 */
-#define  USART_GTPR_PSC_1                    0x0002U            /*!<Bit 1 */
-#define  USART_GTPR_PSC_2                    0x0004U            /*!<Bit 2 */
-#define  USART_GTPR_PSC_3                    0x0008U            /*!<Bit 3 */
-#define  USART_GTPR_PSC_4                    0x0010U            /*!<Bit 4 */
-#define  USART_GTPR_PSC_5                    0x0020U            /*!<Bit 5 */
-#define  USART_GTPR_PSC_6                    0x0040U            /*!<Bit 6 */
-#define  USART_GTPR_PSC_7                    0x0080U            /*!<Bit 7 */
-
-#define  USART_GTPR_GT                       0xFF00U            /*!<Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Window WATCHDOG                                 */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           0x7FU               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T_0                         0x01U               /*!<Bit 0 */
-#define  WWDG_CR_T_1                         0x02U               /*!<Bit 1 */
-#define  WWDG_CR_T_2                         0x04U               /*!<Bit 2 */
-#define  WWDG_CR_T_3                         0x08U               /*!<Bit 3 */
-#define  WWDG_CR_T_4                         0x10U               /*!<Bit 4 */
-#define  WWDG_CR_T_5                         0x20U               /*!<Bit 5 */
-#define  WWDG_CR_T_6                         0x40U               /*!<Bit 6 */
-/* Legacy defines */
-#define  WWDG_CR_T0                          WWDG_CR_T_0
-#define  WWDG_CR_T1                          WWDG_CR_T_1
-#define  WWDG_CR_T2                          WWDG_CR_T_2
-#define  WWDG_CR_T3                          WWDG_CR_T_3
-#define  WWDG_CR_T4                          WWDG_CR_T_4
-#define  WWDG_CR_T5                          WWDG_CR_T_5
-#define  WWDG_CR_T6                          WWDG_CR_T_6
-
-#define  WWDG_CR_WDGA                        0x80U               /*!<Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          0x007FU            /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W_0                        0x0001U            /*!<Bit 0 */
-#define  WWDG_CFR_W_1                        0x0002U            /*!<Bit 1 */
-#define  WWDG_CFR_W_2                        0x0004U            /*!<Bit 2 */
-#define  WWDG_CFR_W_3                        0x0008U            /*!<Bit 3 */
-#define  WWDG_CFR_W_4                        0x0010U            /*!<Bit 4 */
-#define  WWDG_CFR_W_5                        0x0020U            /*!<Bit 5 */
-#define  WWDG_CFR_W_6                        0x0040U            /*!<Bit 6 */
-/* Legacy defines */
-#define  WWDG_CFR_W0                         WWDG_CFR_W_0
-#define  WWDG_CFR_W1                         WWDG_CFR_W_1
-#define  WWDG_CFR_W2                         WWDG_CFR_W_2
-#define  WWDG_CFR_W3                         WWDG_CFR_W_3
-#define  WWDG_CFR_W4                         WWDG_CFR_W_4
-#define  WWDG_CFR_W5                         WWDG_CFR_W_5
-#define  WWDG_CFR_W6                         WWDG_CFR_W_6
-
-#define  WWDG_CFR_WDGTB                      0x0180U            /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB_0                    0x0080U            /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB_1                    0x0100U            /*!<Bit 1 */
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
-
-#define  WWDG_CFR_EWI                        0x0200U            /*!<Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        0x01U               /*!<Early Wakeup Interrupt Flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                DBG                                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
-#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
-
-/********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
-#define  DBGMCU_CR_DBG_STOP                  0x00000002U
-#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
-#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
-
-#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
-#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U/*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U/*!<Bit 1 */
-
-/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            0x00000001U
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            0x00000002U
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            0x00000004U
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            0x00000020U
-#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           0x00000040U
-#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           0x00000080U
-#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           0x00000100U
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
-#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
-
-/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        0x00000001U
-#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        0x00000002U
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        0x00010000U
-#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       0x00020000U
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       0x00040000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                                       USB_OTG			                        */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for USB_OTG_GOTGCTL register  ***********/
-#define USB_OTG_GOTGCTL_SRQSCS                  0x00000001U         /*!< Session request success */
-#define USB_OTG_GOTGCTL_SRQ                     0x00000002U         /*!< Session request */
-#define USB_OTG_GOTGCTL_VBVALOEN                0x00000004U         /*!< VBUS valid override enable */
-#define USB_OTG_GOTGCTL_VBVALOVAL               0x00000008U         /*!< VBUS valid override value */
-#define USB_OTG_GOTGCTL_AVALOEN                 0x00000010U         /*!< A-peripheral session valid override enable */
-#define USB_OTG_GOTGCTL_AVALOVAL                0x00000020U         /*!< A-peripheral session valid override value */
-#define USB_OTG_GOTGCTL_BVALOEN                 0x00000040U         /*!< B-peripheral session valid override enable */
-#define USB_OTG_GOTGCTL_BVALOVAL                0x00000080U         /*!< B-peripheral session valid override value  */
-#define USB_OTG_GOTGCTL_HNGSCS                  0x00000100U         /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_HNPRQ                   0x00000200U         /*!< HNP request */
-#define USB_OTG_GOTGCTL_HSHNPEN                 0x00000400U         /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_DHNPEN                  0x00000800U         /*!< Device HNP enabled */
-#define USB_OTG_GOTGCTL_EHEN                    0x00001000U         /*!< Embedded host enable */
-#define USB_OTG_GOTGCTL_CIDSTS                  0x00010000U         /*!< Connector ID status */
-#define USB_OTG_GOTGCTL_DBCT                    0x00020000U         /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD                   0x00040000U         /*!< A-session valid  */
-#define USB_OTG_GOTGCTL_BSESVLD                 0x00080000U         /*!< B-session valid */
-#define USB_OTG_GOTGCTL_OTGVER                  0x00100000U         /*!< OTG version  */
-
-/********************  Bit definition for USB_OTG_HCFG register  **************/
-
-#define USB_OTG_HCFG_FSLSPCS                 0x00000003U            /*!< FS/LS PHY clock select */
-#define USB_OTG_HCFG_FSLSPCS_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCFG_FSLSPCS_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCFG_FSLSS                   0x00000004U            /*!< FS- and LS-only support */
-
-/********************  Bit definition for USB_OTG_DCFG register  **************/
-
-#define USB_OTG_DCFG_DSPD                    0x00000003U            /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                  0x00000001U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DSPD_1                  0x00000002U            /*!<Bit 1 */
-#define USB_OTG_DCFG_NZLSOHSK                0x00000004U            /*!< Nonzero-length status OUT handshake */
-
-#define USB_OTG_DCFG_DAD                     0x000007F0U            /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                   0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DAD_1                   0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCFG_DAD_2                   0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCFG_DAD_3                   0x00000080U            /*!<Bit 3 */
-#define USB_OTG_DCFG_DAD_4                   0x00000100U            /*!<Bit 4 */
-#define USB_OTG_DCFG_DAD_5                   0x00000200U            /*!<Bit 5 */
-#define USB_OTG_DCFG_DAD_6                   0x00000400U            /*!<Bit 6 */
-
-#define USB_OTG_DCFG_PFIVL                   0x00001800U            /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PFIVL_1                 0x00001000U            /*!<Bit 1 */
-
-#define USB_OTG_DCFG_PERSCHIVL               0x03000000U            /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0             0x01000000U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PERSCHIVL_1             0x02000000U            /*!<Bit 1 */
-
-/********************  Bit definition for USB_OTG_PCGCR register  *************/
-#define USB_OTG_PCGCR_STPPCLK                 0x00000001U            /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK                0x00000002U            /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP                 0x00000010U            /*!< PHY suspended */
-
-/********************  Bit definition for USB_OTG_GOTGINT register  ***********/
-#define USB_OTG_GOTGINT_SEDET                   0x00000004U            /*!< Session end detected */
-#define USB_OTG_GOTGINT_SRSSCHG                 0x00000100U            /*!< Session request success status change */
-#define USB_OTG_GOTGINT_HNSSCHG                 0x00000200U            /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET                  0x00020000U            /*!< Host negotiation detected */
-#define USB_OTG_GOTGINT_ADTOCHG                 0x00040000U            /*!< A-device timeout change */
-#define USB_OTG_GOTGINT_DBCDNE                  0x00080000U            /*!< Debounce done */
-#define USB_OTG_GOTGINT_IDCHNG                  0x00100000U            /*!< Change in ID pin input value           */
-
-/********************  Bit definition for USB_OTG_DCTL register  **************/
-#define USB_OTG_DCTL_RWUSIG                  0x00000001U            /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS                    0x00000002U            /*!< Soft disconnect */
-#define USB_OTG_DCTL_GINSTS                  0x00000004U            /*!< Global IN NAK status */
-#define USB_OTG_DCTL_GONSTS                  0x00000008U            /*!< Global OUT NAK status */
-#define USB_OTG_DCTL_TCTL                    0x00000070U            /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                  0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCTL_TCTL_1                  0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCTL_TCTL_2                  0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCTL_SGINAK                  0x00000080U            /*!< Set global IN NAK */
-#define USB_OTG_DCTL_CGINAK                  0x00000100U            /*!< Clear global IN NAK */
-#define USB_OTG_DCTL_SGONAK                  0x00000200U            /*!< Set global OUT NAK */
-#define USB_OTG_DCTL_CGONAK                  0x00000400U            /*!< Clear global OUT NAK */
-#define USB_OTG_DCTL_POPRGDNE                0x00000800U            /*!< Power-on programming done */
-
-/********************  Bit definition for USB_OTG_HFIR register  **************/
-#define USB_OTG_HFIR_FRIVL                   0x0000FFFFU            /*!< Frame interval */
-
-/********************  Bit definition for USB_OTG_HFNUM register  *************/
-#define USB_OTG_HFNUM_FRNUM                   0x0000FFFFU            /*!< Frame number */
-#define USB_OTG_HFNUM_FTREM                   0xFFFF0000U            /*!< Frame time remaining */
-
-/********************  Bit definition for USB_OTG_DSTS register  **************/
-#define USB_OTG_DSTS_SUSPSTS                 0x00000001U            /*!< Suspend status */
-
-#define USB_OTG_DSTS_ENUMSPD                 0x00000006U            /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_DSTS_ENUMSPD_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_DSTS_EERR                    0x00000008U            /*!< Erratic error */
-#define USB_OTG_DSTS_FNSOF                   0x003FFF00U            /*!< Frame number of the received SOF */
-
-/********************  Bit definition for USB_OTG_GAHBCFG register  ***********/
-#define USB_OTG_GAHBCFG_GINT                    0x00000001U            /*!< Global interrupt mask */
-#define USB_OTG_GAHBCFG_HBSTLEN                 0x0000001EU            /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_GAHBCFG_HBSTLEN_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_GAHBCFG_HBSTLEN_2               0x00000008U            /*!<Bit 2 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3               0x00000010U            /*!<Bit 3 */
-#define USB_OTG_GAHBCFG_DMAEN                   0x00000020U            /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL                 0x00000080U            /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL                0x00000100U            /*!< Periodic TxFIFO empty level */
-
-/********************  Bit definition for USB_OTG_GUSBCFG register  ***********/
-#define USB_OTG_GUSBCFG_TOCAL                   0x00000007U            /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TOCAL_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TOCAL_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_PHYSEL                  0x00000040U            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP                  0x00000100U            /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP                  0x00000200U            /*!< HNP-capable */
-
-#define USB_OTG_GUSBCFG_TRDT                    0x00003C00U            /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                  0x00000400U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TRDT_1                  0x00000800U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TRDT_2                  0x00001000U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_TRDT_3                  0x00002000U            /*!<Bit 3 */
-#define USB_OTG_GUSBCFG_PHYLPCS                 0x00008000U            /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS                0x00020000U            /*!< ULPI FS/LS select */
-#define USB_OTG_GUSBCFG_ULPIAR                  0x00040000U            /*!< ULPI Auto-resume */
-#define USB_OTG_GUSBCFG_ULPICSM                 0x00080000U            /*!< ULPI Clock SuspendM */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD              0x00100000U            /*!< ULPI External VBUS Drive */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI              0x00200000U            /*!< ULPI external VBUS indicator */
-#define USB_OTG_GUSBCFG_TSDPS                   0x00400000U            /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI                    0x00800000U            /*!< Indicator complement */
-#define USB_OTG_GUSBCFG_PTCI                    0x01000000U            /*!< Indicator pass through */
-#define USB_OTG_GUSBCFG_ULPIIPD                 0x02000000U            /*!< ULPI interface protect disable */
-#define USB_OTG_GUSBCFG_FHMOD                   0x20000000U            /*!< Forced host mode */
-#define USB_OTG_GUSBCFG_FDMOD                   0x40000000U            /*!< Forced peripheral mode */
-#define USB_OTG_GUSBCFG_CTXPKT                  0x80000000U            /*!< Corrupt Tx packet */
-
-/********************  Bit definition for USB_OTG_GRSTCTL register  ***********/
-#define USB_OTG_GRSTCTL_CSRST                   0x00000001U            /*!< Core soft reset */
-#define USB_OTG_GRSTCTL_HSRST                   0x00000002U            /*!< HCLK soft reset */
-#define USB_OTG_GRSTCTL_FCRST                   0x00000004U            /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH                 0x00000010U            /*!< RxFIFO flush */
-#define USB_OTG_GRSTCTL_TXFFLSH                 0x00000020U            /*!< TxFIFO flush */
-
-#define USB_OTG_GRSTCTL_TXFNUM                  0x000007C0U            /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                0x00000040U            /*!<Bit 0 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                0x00000080U            /*!<Bit 1 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                0x00000100U            /*!<Bit 2 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                0x00000200U            /*!<Bit 3 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                0x00000400U            /*!<Bit 4 */
-#define USB_OTG_GRSTCTL_DMAREQ                  0x40000000U            /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL                  0x80000000U            /*!< AHB master idle */
-
-/********************  Bit definition for USB_OTG_DIEPMSK register  ***********/
-#define USB_OTG_DIEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPMSK_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPMSK_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPMSK_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPMSK_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPMSK_BIM                     0x00000200U            /*!< BNA interrupt mask */
-
-/********************  Bit definition for USB_OTG_HPTXSTS register  ***********/
-#define USB_OTG_HPTXSTS_PTXFSAVL                0x0000FFFFU            /*!< Periodic transmit data FIFO space available */
-
-#define USB_OTG_HPTXSTS_PTXQSAV                 0x00FF0000U            /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0               0x00010000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1               0x00020000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2               0x00040000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3               0x00080000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4               0x00100000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5               0x00200000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6               0x00400000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7               0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_HPTXSTS_PTXQTOP                 0xFF000000U            /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0               0x01000000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1               0x02000000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2               0x04000000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3               0x08000000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4               0x10000000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5               0x20000000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6               0x40000000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7               0x80000000U            /*!<Bit 7 */
-
-/********************  Bit definition for USB_OTG_HAINT register  *************/
-#define USB_OTG_HAINT_HAINT                   0x0000FFFFU            /*!< Channel interrupts */
-
-/********************  Bit definition for USB_OTG_DOEPMSK register  ***********/
-#define USB_OTG_DOEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPMSK_STUPM                   0x00000008U            /*!< SETUP phase done mask */
-#define USB_OTG_DOEPMSK_OTEPDM                  0x00000010U            /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_OTEPSPRM                0x00000020U            /*!< Status Phase Received mask                     */
-#define USB_OTG_DOEPMSK_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received mask */
-#define USB_OTG_DOEPMSK_OPEM                    0x00000100U            /*!< OUT packet error mask */
-#define USB_OTG_DOEPMSK_BOIM                    0x00000200U            /*!< BNA interrupt mask */
-
-/********************  Bit definition for USB_OTG_GINTSTS register  ***********/
-#define USB_OTG_GINTSTS_CMOD                    0x00000001U            /*!< Current mode of operation                      */
-#define USB_OTG_GINTSTS_MMIS                    0x00000002U            /*!< Mode mismatch interrupt                        */
-#define USB_OTG_GINTSTS_OTGINT                  0x00000004U            /*!< OTG interrupt                                  */
-#define USB_OTG_GINTSTS_SOF                     0x00000008U            /*!< Start of frame                                 */
-#define USB_OTG_GINTSTS_RXFLVL                  0x00000010U            /*!< RxFIFO nonempty                                */
-#define USB_OTG_GINTSTS_NPTXFE                  0x00000020U            /*!< Nonperiodic TxFIFO empty                       */
-#define USB_OTG_GINTSTS_GINAKEFF                0x00000040U            /*!< Global IN nonperiodic NAK effective            */
-#define USB_OTG_GINTSTS_BOUTNAKEFF              0x00000080U            /*!< Global OUT NAK effective                       */
-#define USB_OTG_GINTSTS_ESUSP                   0x00000400U            /*!< Early suspend                                  */
-#define USB_OTG_GINTSTS_USBSUSP                 0x00000800U            /*!< USB suspend                                    */
-#define USB_OTG_GINTSTS_USBRST                  0x00001000U            /*!< USB reset                                      */
-#define USB_OTG_GINTSTS_ENUMDNE                 0x00002000U            /*!< Enumeration done                               */
-#define USB_OTG_GINTSTS_ISOODRP                 0x00004000U            /*!< Isochronous OUT packet dropped interrupt       */
-#define USB_OTG_GINTSTS_EOPF                    0x00008000U            /*!< End of periodic frame interrupt                */
-#define USB_OTG_GINTSTS_IEPINT                  0x00040000U            /*!< IN endpoint interrupt                          */
-#define USB_OTG_GINTSTS_OEPINT                  0x00080000U            /*!< OUT endpoint interrupt                         */
-#define USB_OTG_GINTSTS_IISOIXFR                0x00100000U            /*!< Incomplete isochronous IN transfer             */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       0x00200000U            /*!< Incomplete periodic transfer                   */
-#define USB_OTG_GINTSTS_DATAFSUSP               0x00400000U            /*!< Data fetch suspended                           */
-#define USB_OTG_GINTSTS_RSTDET                  0x00800000U            /*!< Reset detected interrupt                       */
-#define USB_OTG_GINTSTS_HPRTINT                 0x01000000U            /*!< Host port interrupt                            */
-#define USB_OTG_GINTSTS_HCINT                   0x02000000U            /*!< Host channels interrupt                        */
-#define USB_OTG_GINTSTS_PTXFE                   0x04000000U            /*!< Periodic TxFIFO empty                          */
-#define USB_OTG_GINTSTS_LPMINT                  0x08000000U            /*!< LPM interrupt                                  */
-#define USB_OTG_GINTSTS_CIDSCHG                 0x10000000U            /*!< Connector ID status change                     */
-#define USB_OTG_GINTSTS_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt                  */
-#define USB_OTG_GINTSTS_SRQINT                  0x40000000U            /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT                  0x80000000U            /*!< Resume/remote wakeup detected interrupt        */
-
-/********************  Bit definition for USB_OTG_GINTMSK register  ***********/
-#define USB_OTG_GINTMSK_MMISM                   0x00000002U         /*!< Mode mismatch interrupt mask */
-#define USB_OTG_GINTMSK_OTGINT                  0x00000004U         /*!< OTG interrupt mask */
-#define USB_OTG_GINTMSK_SOFM                    0x00000008U         /*!< Start of frame mask */
-#define USB_OTG_GINTMSK_RXFLVLM                 0x00000010U         /*!< Receive FIFO nonempty mask */
-#define USB_OTG_GINTMSK_NPTXFEM                 0x00000020U         /*!< Nonperiodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_GINAKEFFM               0x00000040U         /*!< Global nonperiodic IN NAK effective mask */
-#define USB_OTG_GINTMSK_GONAKEFFM               0x00000080U         /*!< Global OUT NAK effective mask */
-#define USB_OTG_GINTMSK_ESUSPM                  0x00000400U         /*!< Early suspend mask */
-#define USB_OTG_GINTMSK_USBSUSPM                0x00000800U         /*!< USB suspend mask */
-#define USB_OTG_GINTMSK_USBRST                  0x00001000U         /*!< USB reset mask */
-#define USB_OTG_GINTMSK_ENUMDNEM                0x00002000U         /*!< Enumeration done mask */
-#define USB_OTG_GINTMSK_ISOODRPM                0x00004000U         /*!< Isochronous OUT packet dropped interrupt mask */
-#define USB_OTG_GINTMSK_EOPFM                   0x00008000U         /*!< End of periodic frame interrupt mask */
-#define USB_OTG_GINTMSK_EPMISM                  0x00020000U         /*!< Endpoint mismatch interrupt mask */
-#define USB_OTG_GINTMSK_IEPINT                  0x00040000U         /*!< IN endpoints interrupt mask */
-#define USB_OTG_GINTMSK_OEPINT                  0x00080000U         /*!< OUT endpoints interrupt mask */
-#define USB_OTG_GINTMSK_IISOIXFRM               0x00100000U         /*!< Incomplete isochronous IN transfer mask */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         0x00200000U         /*!< Incomplete periodic transfer mask */
-#define USB_OTG_GINTMSK_FSUSPM                  0x00400000U         /*!< Data fetch suspended mask */
-#define USB_OTG_GINTMSK_RSTDETM                 0x00800000U         /*!< Reset detected interrupt mask */
-#define USB_OTG_GINTMSK_PRTIM                   0x01000000U         /*!< Host port interrupt mask */
-#define USB_OTG_GINTMSK_HCIM                    0x02000000U         /*!< Host channels interrupt mask */
-#define USB_OTG_GINTMSK_PTXFEM                  0x04000000U         /*!< Periodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_LPMINTM                 0x08000000U         /*!< LPM interrupt Mask */
-#define USB_OTG_GINTMSK_CIDSCHGM                0x10000000U         /*!< Connector ID status change mask */
-#define USB_OTG_GINTMSK_DISCINT                 0x20000000U         /*!< Disconnect detected interrupt mask */
-#define USB_OTG_GINTMSK_SRQIM                   0x40000000U         /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM                    0x80000000U         /*!< Resume/remote wakeup detected interrupt mask */
-
-/********************  Bit definition for USB_OTG_DAINT register  *************/
-#define USB_OTG_DAINT_IEPINT                  0x0000FFFFU            /*!< IN endpoint interrupt bits */
-#define USB_OTG_DAINT_OEPINT                  0xFFFF0000U            /*!< OUT endpoint interrupt bits */
-
-/********************  Bit definition for USB_OTG_HAINTMSK register  **********/
-#define USB_OTG_HAINTMSK_HAINTM                  0x0000FFFFU            /*!< Channel interrupt mask */
-
-/********************  Bit definition for USB_OTG_GRXSTSP register  ***********/
-#define USB_OTG_GRXSTSP_EPNUM                    0x0000000FU            /*!< IN EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_BCNT                     0x00007FF0U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID                     0x00018000U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS                   0x001E0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for USB_OTG_DAINTMSK register  **********/
-#define USB_OTG_DAINTMSK_IEPM                    0x0000FFFFU            /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM                    0xFFFF0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for OTG register  ***********************/
-
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition for OTG register  ***********************/
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition for USB_OTG_GRXFSIZ register  ***********/
-#define USB_OTG_GRXFSIZ_RXFD            0x0000FFFFU            /*!< RxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DVBUSDIS register  **********/
-#define USB_OTG_DVBUSDIS_VBUSDT         0x0000FFFFU            /*!< Device VBUS discharge time */
-
-/********************  Bit definition for OTG register  ***********************/
-#define USB_OTG_NPTXFSA                 0x0000FFFFU            /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD                  0xFFFF0000U            /*!< Nonperiodic TxFIFO depth */
-#define USB_OTG_TX0FSA                  0x0000FFFFU            /*!< Endpoint 0 transmit RAM start address */
-#define USB_OTG_TX0FD                   0xFFFF0000U            /*!< Endpoint 0 TxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DVBUSPULSE register  ********/
-#define USB_OTG_DVBUSPULSE_DVBUSP                  0x00000FFFU            /*!< Device VBUS pulsing time */
-
-/********************  Bit definition for USB_OTG_GNPTXSTS register  **********/
-#define USB_OTG_GNPTXSTS_NPTXFSAV                0x0000FFFFU            /*!< Nonperiodic TxFIFO space available */
-
-#define USB_OTG_GNPTXSTS_NPTQXSAV                0x00FF0000U            /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0              0x00010000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1              0x00020000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2              0x00040000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3              0x00080000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4              0x00100000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5              0x00200000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6              0x00400000U            /*!<Bit 6 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7              0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_GNPTXSTS_NPTXQTOP                0x7F000000U            /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0              0x01000000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1              0x02000000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2              0x04000000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3              0x08000000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4              0x10000000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5              0x20000000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6              0x40000000U            /*!<Bit 6 */
-
-/********************  Bit definition for USB_OTG_DTHRCTL register  ***********/
-#define USB_OTG_DTHRCTL_NONISOTHREN             0x00000001U            /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN                0x00000002U            /*!< ISO IN endpoint threshold enable */
-
-#define USB_OTG_DTHRCTL_TXTHRLEN                0x000007FCU            /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0              0x00000004U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1              0x00000008U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2              0x00000010U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3              0x00000020U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4              0x00000040U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5              0x00000080U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6              0x00000100U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7              0x00000200U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8              0x00000400U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_RXTHREN                 0x00010000U            /*!< Receive threshold enable */
-
-#define USB_OTG_DTHRCTL_RXTHRLEN                0x03FE0000U            /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0              0x00020000U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1              0x00040000U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2              0x00080000U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3              0x00100000U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4              0x00200000U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5              0x00400000U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6              0x00800000U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7              0x01000000U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8              0x02000000U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_ARPEN                   0x08000000U            /*!< Arbiter parking enable */
-
-/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM               0x0000FFFFU            /*!< IN EP Tx FIFO empty interrupt mask bits */
-
-/********************  Bit definition for USB_OTG_DEACHINT register  **********/
-#define USB_OTG_DEACHINT_IEP1INT                 0x00000002U            /*!< IN endpoint 1interrupt bit */
-#define USB_OTG_DEACHINT_OEP1INT                 0x00020000U            /*!< OUT endpoint 1 interrupt bit */
-
-/********************  Bit definition for USB_OTG_GCCFG register  *************/
-#define USB_OTG_GCCFG_DCDET                  0x00000001U              /*!< Data contact detection (DCD) status */
-#define USB_OTG_GCCFG_PDET                   0x00000002U              /*!< Primary detection (PD) status */
-#define USB_OTG_GCCFG_SDET                   0x00000004U              /*!< Secondary detection (SD) status */
-#define USB_OTG_GCCFG_PS2DET                 0x00000008U              /*!< DM pull-up detection status */
-#define USB_OTG_GCCFG_PWRDWN                 0x00010000U              /*!< Power down */
-#define USB_OTG_GCCFG_BCDEN                  0x00020000U              /*!< Battery charging detector (BCD) enable */
-#define USB_OTG_GCCFG_DCDEN                  0x00040000U              /*!< Data contact detection (DCD) mode enable*/
-#define USB_OTG_GCCFG_PDEN                   0x00080000U              /*!< Primary detection (PD) mode enable*/
-#define USB_OTG_GCCFG_SDEN                   0x00100000U              /*!< Secondary detection (SD) mode enable */
-#define USB_OTG_GCCFG_VBDEN                  0x00200000U              /*!< USB VBUS Detection Enable */
-
-/********************  Bit definition for USB_OTG_DEACHINTMSK register  *******/
-#define USB_OTG_DEACHINTMSK_IEP1INTM                0x00000002U            /*!< IN Endpoint 1 interrupt mask bit */
-#define USB_OTG_DEACHINTMSK_OEP1INTM                0x00020000U            /*!< OUT Endpoint 1 interrupt mask bit */
-
-/********************  Bit definition for USB_OTG_CID register  ***************/
-#define USB_OTG_CID_PRODUCT_ID              0xFFFFFFFFU               /*!< Product ID field */
-
-/********************  Bit definition for USB_OTG_GLPMCFG register  ***********/
-#define  USB_OTG_GLPMCFG_LPMEN               0x00000001U            /*!< LPM support enable                                     */
-#define  USB_OTG_GLPMCFG_LPMACK              0x00000002U            /*!< LPM Token acknowledge enable                           */
-#define  USB_OTG_GLPMCFG_BESL                0x0000003CU            /*!< BESL value received with last ACKed LPM Token          */
-#define  USB_OTG_GLPMCFG_REMWAKE             0x00000040U            /*!< bRemoteWake value received with last ACKed LPM Token   */
-#define  USB_OTG_GLPMCFG_L1SSEN              0x00000080U            /*!< L1 shallow sleep enable                                */
-#define  USB_OTG_GLPMCFG_BESLTHRS            0x00000F00U            /*!< BESL threshold                                         */
-#define  USB_OTG_GLPMCFG_L1DSEN              0x00001000U            /*!< L1 deep sleep enable                                   */
-#define  USB_OTG_GLPMCFG_LPMRSP              0x00006000U            /*!< LPM response                                           */
-#define  USB_OTG_GLPMCFG_SLPSTS              0x00008000U            /*!< Port sleep status                                      */
-#define  USB_OTG_GLPMCFG_L1RSMOK             0x00010000U            /*!< Sleep State Resume OK                                  */
-#define  USB_OTG_GLPMCFG_LPMCHIDX            0x001E0000U            /*!< LPM Channel Index                                      */
-#define  USB_OTG_GLPMCFG_LPMRCNT             0x00E00000U            /*!< LPM retry count                                        */
-#define  USB_OTG_GLPMCFG_SNDLPM              0x01000000U            /*!< Send LPM transaction                                   */
-#define  USB_OTG_GLPMCFG_LPMRCNTSTS          0x0E000000U            /*!< LPM retry count status                                 */
-#define  USB_OTG_GLPMCFG_ENBESL              0x10000000U            /*!< Enable best effort service latency                     */
-
-/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ******/
-#define USB_OTG_DIEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPEACHMSK1_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
-
-/********************  Bit definition for USB_OTG_HPRT register  **************/
-#define USB_OTG_HPRT_PCSTS                   0x00000001U            /*!< Port connect status */
-#define USB_OTG_HPRT_PCDET                   0x00000002U            /*!< Port connect detected */
-#define USB_OTG_HPRT_PENA                    0x00000004U            /*!< Port enable */
-#define USB_OTG_HPRT_PENCHNG                 0x00000008U            /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA                    0x00000010U            /*!< Port overcurrent active */
-#define USB_OTG_HPRT_POCCHNG                 0x00000020U            /*!< Port overcurrent change */
-#define USB_OTG_HPRT_PRES                    0x00000040U            /*!< Port resume */
-#define USB_OTG_HPRT_PSUSP                   0x00000080U            /*!< Port suspend */
-#define USB_OTG_HPRT_PRST                    0x00000100U            /*!< Port reset */
-
-#define USB_OTG_HPRT_PLSTS                   0x00000C00U            /*!< Port line status */
-#define USB_OTG_HPRT_PLSTS_0                 0x00000400U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PLSTS_1                 0x00000800U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PPWR                    0x00001000U            /*!< Port power */
-
-#define USB_OTG_HPRT_PTCTL                   0x0001E000U            /*!< Port test control */
-#define USB_OTG_HPRT_PTCTL_0                 0x00002000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PTCTL_1                 0x00004000U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PTCTL_2                 0x00008000U            /*!<Bit 2 */
-#define USB_OTG_HPRT_PTCTL_3                 0x00010000U            /*!<Bit 3 */
-
-#define USB_OTG_HPRT_PSPD                    0x00060000U            /*!< Port speed */
-#define USB_OTG_HPRT_PSPD_0                  0x00020000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PSPD_1                  0x00040000U            /*!<Bit 1 */
-
-/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ******/
-#define USB_OTG_DOEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DOEPEACHMSK1_TXFURM                  0x00000100U            /*!< OUT packet error mask */
-#define USB_OTG_DOEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_BERRM                   0x00001000U            /*!< Bubble error interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NYETM                   0x00004000U            /*!< NYET interrupt mask */
-
-/********************  Bit definition for USB_OTG_HPTXFSIZ register  **********/
-#define USB_OTG_HPTXFSIZ_PTXSA                   0x0000FFFFU            /*!< Host periodic TxFIFO start address */
-#define USB_OTG_HPTXFSIZ_PTXFD                   0xFFFF0000U            /*!< Host periodic TxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DIEPCTL register  ***********/
-#define USB_OTG_DIEPCTL_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
-#define USB_OTG_DIEPCTL_USBAEP                  0x00008000U            /*!< USB active endpoint */
-#define USB_OTG_DIEPCTL_EONUM_DPID              0x00010000U            /*!< Even/odd frame */
-#define USB_OTG_DIEPCTL_NAKSTS                  0x00020000U            /*!< NAK status */
-
-#define USB_OTG_DIEPCTL_EPTYP                   0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_DIEPCTL_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_STALL                   0x00200000U            /*!< STALL handshake */
-
-#define USB_OTG_DIEPCTL_TXFNUM                  0x03C00000U            /*!< TxFIFO number */
-#define USB_OTG_DIEPCTL_TXFNUM_0                0x00400000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                0x00800000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                0x01000000U            /*!<Bit 2 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                0x02000000U            /*!<Bit 3 */
-#define USB_OTG_DIEPCTL_CNAK                    0x04000000U            /*!< Clear NAK */
-#define USB_OTG_DIEPCTL_SNAK                    0x08000000U            /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          0x10000000U            /*!< Set DATA0 PID */
-#define USB_OTG_DIEPCTL_SODDFRM                 0x20000000U            /*!< Set odd frame */
-#define USB_OTG_DIEPCTL_EPDIS                   0x40000000U            /*!< Endpoint disable */
-#define USB_OTG_DIEPCTL_EPENA                   0x80000000U            /*!< Endpoint enable */
-
-/********************  Bit definition for USB_OTG_HCCHAR register  ************/
-#define USB_OTG_HCCHAR_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
-
-#define USB_OTG_HCCHAR_EPNUM                   0x00007800U            /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPNUM_1                 0x00001000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_EPNUM_2                 0x00002000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_EPNUM_3                 0x00004000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_EPDIR                   0x00008000U            /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV                   0x00020000U            /*!< Low-speed device */
-
-#define USB_OTG_HCCHAR_EPTYP                   0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_MC                      0x00300000U            /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                    0x00100000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_MC_1                    0x00200000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_DAD                     0x1FC00000U            /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                   0x00400000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_DAD_1                   0x00800000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_DAD_2                   0x01000000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_DAD_3                   0x02000000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_DAD_4                   0x04000000U            /*!<Bit 4 */
-#define USB_OTG_HCCHAR_DAD_5                   0x08000000U            /*!<Bit 5 */
-#define USB_OTG_HCCHAR_DAD_6                   0x10000000U            /*!<Bit 6 */
-#define USB_OTG_HCCHAR_ODDFRM                  0x20000000U            /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS                   0x40000000U            /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA                   0x80000000U            /*!< Channel enable */
-
-/********************  Bit definition for USB_OTG_HCSPLT register  ************/
-
-#define USB_OTG_HCSPLT_PRTADDR                 0x0000007FU            /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_PRTADDR_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_PRTADDR_2               0x00000004U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_PRTADDR_3               0x00000008U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_PRTADDR_4               0x00000010U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_PRTADDR_5               0x00000020U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_PRTADDR_6               0x00000040U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_HUBADDR                 0x00003F80U            /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0               0x00000080U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_HUBADDR_1               0x00000100U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_HUBADDR_2               0x00000200U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_HUBADDR_3               0x00000400U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_HUBADDR_4               0x00000800U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_HUBADDR_5               0x00001000U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_HUBADDR_6               0x00002000U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_XACTPOS                 0x0000C000U            /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0               0x00004000U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_XACTPOS_1               0x00008000U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_COMPLSPLT               0x00010000U            /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN                 0x80000000U            /*!< Split enable */
-
-/********************  Bit definition for USB_OTG_HCINT register  *************/
-#define USB_OTG_HCINT_XFRC                    0x00000001U            /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH                     0x00000002U            /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINT_STALL                   0x00000008U            /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK                     0x00000010U            /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK                     0x00000020U            /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET                    0x00000040U            /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR                   0x00000080U            /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR                   0x00000100U            /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR                   0x00000200U            /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR                   0x00000400U            /*!< Data toggle error */
-
-/********************  Bit definition for USB_OTG_DIEPINT register  ***********/
-#define USB_OTG_DIEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_TOC                     0x00000008U            /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE                  0x00000010U            /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNE                  0x00000040U            /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE                    0x00000080U            /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN              0x00000100U            /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA                     0x00000200U            /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS               0x00000800U            /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR                    0x00001000U            /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK                     0x00002000U            /*!< NAK interrupt */
-
-/********************  Bit definition for USB_OTG_HCINTMSK register  **********/
-#define USB_OTG_HCINTMSK_XFRCM                   0x00000001U            /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM                    0x00000002U            /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM                  0x00000008U            /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM                    0x00000010U            /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM                    0x00000020U            /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET                    0x00000040U            /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM                  0x00000080U            /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM                  0x00000100U            /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM                  0x00000200U            /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM                  0x00000400U            /*!< Data toggle error mask */
-
-/********************  Bit definition for USB_OTG_DIEPTSIZ register  **********/
-
-#define USB_OTG_DIEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT                  0x60000000U            /*!< Packet count */
-/********************  Bit definition for USB_OTG_HCTSIZ register  ************/
-#define USB_OTG_HCTSIZ_XFRSIZ                    0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT                    0x1FF80000U            /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING                    0x80000000U            /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID                      0x60000000U            /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                    0x20000000U            /*!<Bit 0 */
-#define USB_OTG_HCTSIZ_DPID_1                    0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition for USB_OTG_DIEPDMA register  ***********/
-#define USB_OTG_DIEPDMA_DMAADDR                  0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition for USB_OTG_HCDMA register  *************/
-#define USB_OTG_HCDMA_DMAADDR                    0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition for USB_OTG_DTXFSTS register  ***********/
-#define USB_OTG_DTXFSTS_INEPTFSAV                0x0000FFFFU            /*!< IN endpoint TxFIFO space available */
-
-/********************  Bit definition for USB_OTG_DIEPTXF register  ***********/
-#define USB_OTG_DIEPTXF_INEPTXSA                 0x0000FFFFU            /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD                 0xFFFF0000U            /*!< IN endpoint TxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DOEPCTL register  ***********/
-
-#define USB_OTG_DOEPCTL_MPSIZ                     0x000007FFU            /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP                    0x00008000U            /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS                    0x00020000U            /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            0x10000000U            /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM                   0x20000000U            /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP                     0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                   0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DOEPCTL_EPTYP_1                   0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_SNPM                      0x00100000U            /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL                     0x00200000U            /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK                      0x04000000U            /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK                      0x08000000U            /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS                     0x40000000U            /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA                     0x80000000U            /*!< Endpoint enable */
-
-/********************  Bit definition for USB_OTG_DOEPINT register  ***********/
-#define USB_OTG_DOEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_STUP                    0x00000008U            /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS                 0x00000010U            /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_OTEPSPR                 0x00000020U            /*!< Status Phase Received For Control Write */
-#define USB_OTG_DOEPINT_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_NYET                    0x00004000U            /*!< NYET interrupt */
-
-/********************  Bit definition for USB_OTG_DOEPTSIZ register  **********/
-
-#define USB_OTG_DOEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-
-#define USB_OTG_DOEPTSIZ_STUPCNT                 0x60000000U            /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0               0x20000000U            /*!<Bit 0 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1               0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition for PCGCCTL register  *******************/
-#define USB_OTG_PCGCCTL_STOPCLK                 0x00000001U            /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK                 0x00000002U            /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP                 0x00000010U            /*!<Bit 1 */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
- 
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-
-/******************************* CAN Instances ********************************/
-#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
-                                       ((INSTANCE) == CAN2))
-/****************************** DFSDM Instances *******************************/
-#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
-                                                ((INSTANCE) == DFSDM1_Filter1))
-
-#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
-                                                 ((INSTANCE) == DFSDM1_Channel1) || \
-                                                 ((INSTANCE) == DFSDM1_Channel2) || \
-                                                 ((INSTANCE) == DFSDM1_Channel3))
-
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************** DMA Instances *******************************/
-#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
-                                              ((INSTANCE) == DMA1_Stream1) || \
-                                              ((INSTANCE) == DMA1_Stream2) || \
-                                              ((INSTANCE) == DMA1_Stream3) || \
-                                              ((INSTANCE) == DMA1_Stream4) || \
-                                              ((INSTANCE) == DMA1_Stream5) || \
-                                              ((INSTANCE) == DMA1_Stream6) || \
-                                              ((INSTANCE) == DMA1_Stream7) || \
-                                              ((INSTANCE) == DMA2_Stream0) || \
-                                              ((INSTANCE) == DMA2_Stream1) || \
-                                              ((INSTANCE) == DMA2_Stream2) || \
-                                              ((INSTANCE) == DMA2_Stream3) || \
-                                              ((INSTANCE) == DMA2_Stream4) || \
-                                              ((INSTANCE) == DMA2_Stream5) || \
-                                              ((INSTANCE) == DMA2_Stream6) || \
-                                              ((INSTANCE) == DMA2_Stream7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOF) || \
-                                        ((INSTANCE) == GPIOG) || \
-                                        ((INSTANCE) == GPIOH))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2) || \
-                                       ((INSTANCE) == I2C3))
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI1) || \
-                                    ((INSTANCE) == SPI2) || \
-                                    ((INSTANCE) == SPI3) || \
-                                    ((INSTANCE) == SPI4) || \
-                                    ((INSTANCE) == SPI5))
-
-/*************************** I2S Extended Instances ***************************/
-#define IS_I2S_ALL_INSTANCE_EXT(PERIPH)  (((INSTANCE) == SPI2)    || \
-                                          ((INSTANCE) == SPI3)    || \
-                                          ((INSTANCE) == I2S2ext) || \
-                                          ((INSTANCE) == I2S3ext))
-
-/******************************* RNG Instances ********************************/
-#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3) || \
-                                       ((INSTANCE) == SPI4) || \
-                                       ((INSTANCE) == SPI5))
-/*************************** SPI Extended Instances ***************************/
-#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1)    || \
-                                           ((INSTANCE) == SPI2)    || \
-                                           ((INSTANCE) == SPI3)    || \
-                                           ((INSTANCE) == SPI4)    || \
-                                           ((INSTANCE) == SPI5)    || \
-                                           ((INSTANCE) == I2S2ext) || \
-                                           ((INSTANCE) == I2S3ext))
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
-                                   ((INSTANCE) == TIM2)   || \
-                                   ((INSTANCE) == TIM3)   || \
-                                   ((INSTANCE) == TIM4)   || \
-                                   ((INSTANCE) == TIM5)   || \
-                                   ((INSTANCE) == TIM6)   || \
-                                   ((INSTANCE) == TIM7)   || \
-                                   ((INSTANCE) == TIM8)   || \
-                                   ((INSTANCE) == TIM9)   || \
-                                   ((INSTANCE) == TIM10)  || \
-                                   ((INSTANCE) == TIM11)  || \
-                                   ((INSTANCE) == TIM12)  || \
-                                   ((INSTANCE) == TIM13)  || \
-                                   ((INSTANCE) == TIM14))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
-                                         ((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM8)  || \
-                                         ((INSTANCE) == TIM9)  || \
-                                         ((INSTANCE) == TIM10) || \
-                                         ((INSTANCE) == TIM11) || \
-                                         ((INSTANCE) == TIM12) || \
-                                         ((INSTANCE) == TIM13) || \
-                                         ((INSTANCE) == TIM14))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM8) || \
-                                       ((INSTANCE) == TIM9) || \
-                                       ((INSTANCE) == TIM12))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8))
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM8))
-
-/******************** TIM Instances : Advanced-control timers *****************/
-#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                            ((INSTANCE) == TIM8))
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8))
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM6) || \
-                                       ((INSTANCE) == TIM7) || \
-                                       ((INSTANCE) == TIM8))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM8))
-
-/************ TIM Instances : DMA requests generation (COMDE) *****************/
-#define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM8)) 
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                             ((INSTANCE) == TIM2) || \
-                                             ((INSTANCE) == TIM3) || \
-                                             ((INSTANCE) == TIM4) || \
-                                             ((INSTANCE) == TIM5) || \
-                                             ((INSTANCE) == TIM8))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM6) || \
-                                          ((INSTANCE) == TIM7) || \
-                                          ((INSTANCE) == TIM8) || \
-                                          ((INSTANCE) == TIM9) || \
-                                          ((INSTANCE) == TIM12))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8) || \
-                                         ((INSTANCE) == TIM9) || \
-                                         ((INSTANCE) == TIM12))
-
-/********************** TIM Instances : 32 bit Counter ************************/
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
-                                              ((INSTANCE) == TIM5))
-
-/***************** TIM Instances : external trigger input available ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                        ((INSTANCE) == TIM2) || \
-                                        ((INSTANCE) == TIM3) || \
-                                        ((INSTANCE) == TIM4) || \
-                                        ((INSTANCE) == TIM5) || \
-                                        ((INSTANCE) == TIM8))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM11))
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM1) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM5) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM8) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM12) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM13) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM14) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-/************ TIM Instances : complementary output(s) available ***************/
-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
-   ((((INSTANCE) == TIM1) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3)))            \
-    ||                                          \
-    (((INSTANCE) == TIM8) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3))))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3) || \
-                                     ((INSTANCE) == USART6))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == USART6))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3))
-
-/********************* UART Instances : Smart card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3) || \
-                                         ((INSTANCE) == USART6))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == USART6))
-
-/*********************** PCD Instances ****************************************/
-#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
-
-/*********************** HCD Instances ****************************************/
-#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/****************************** QSPI Instances ********************************/
-#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
-
-/***************************** FMPI2C Instances *******************************/
-#define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
-
-/****************************** SDIO Instances ********************************/
-#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
-
-/****************************** USB Instances ********************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
-
-/****************************** USB Exported Constants ************************/
-#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                12U
-#define USB_OTG_FS_MAX_IN_ENDPOINTS                    6U    /* Including EP0 */
-#define USB_OTG_FS_MAX_OUT_ENDPOINTS                   6U    /* Including EP0 */
-#define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32F412Rx_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/cmsis/stm32f412vx.h b/stmhal/cmsis/stm32f412vx.h
deleted file mode 100644
index 3ea4fbbea5..0000000000
--- a/stmhal/cmsis/stm32f412vx.h
+++ /dev/null
@@ -1,7392 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f412vx.h
-  * @author  MCD Application Team
-  * @version V2.5.1
-  * @date    28-June-2016
-  * @brief   CMSIS STM32F412Vx Device Peripheral Access Layer Header File. 
-  *
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - peripherals registers declarations and bits definition
-  *           - Macros to access peripheral’s registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f412vx
-  * @{
-  */
-    
-#ifndef __STM32F412Vx_H
-#define __STM32F412Vx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-  
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-
-/**
-  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
-  */
-#define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */
-#define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */
-#define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1U       /*!< FPU present                                   */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32F4XX Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-typedef enum
-{
-/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
-  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
-/******  STM32 specific Interrupt Numbers **********************************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
-  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
-  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
-  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
-  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
-  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
-  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
-  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
-  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
-  ADC_IRQn                    = 18,     /*!< ADC1 global Interrupts                                            */
-  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
-  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
-  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
-  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
-  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
-  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
-  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
-  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */
-  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
-  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
-  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
-  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
-  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
-  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
-  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
-  TIM6_IRQn                   = 54,     /*!< TIM6 global interrupt                                             */
-  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
-  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
-  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
-  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
-  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
-  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
-  DFSDM1_FLT0_IRQn            = 61,     /*!< DFSDM1 Filter 0 global Interrupt                                  */
-  DFSDM1_FLT1_IRQn            = 62,     /*!< DFSDM1 Filter 1 global Interrupt                                  */
-  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
-  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
-  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
-  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
-  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
-  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
-  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
-  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
-  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
-  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
-  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
-  RNG_IRQn                    = 80,     /*!< RNG global Interrupt                                              */
-  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
-  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
-  SPI5_IRQn                   = 85,      /*!< SPI5 global Interrupt                                            */
-  QUADSPI_IRQn                = 92,     /*!< QuadSPI global Interrupt                                          */
-  FMPI2C1_EV_IRQn             = 95,     /*!< FMPI2C1 Event Interrupt                                           */
-  FMPI2C1_ER_IRQn             = 96      /*!< FMPI2C1 Error Interrupt                                           */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
-#include "system_stm32f4xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */
-  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
-  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
-  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
-  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
-  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
-  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
-  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
-  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
-  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
-  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
-  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
-  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
-  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
-  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
-  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
-                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief Controller Area Network TxMailBox 
-  */
-
-typedef struct
-{
-  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
-  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
-  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
-  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
-} CAN_TxMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FIFOMailBox 
-  */
-  
-typedef struct
-{
-  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
-  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
-  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
-  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
-} CAN_FIFOMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FilterRegister 
-  */
-  
-typedef struct
-{
-  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
-  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
-} CAN_FilterRegister_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
-  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
-  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
-  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
-  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
-  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
-  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
-  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
-  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
-  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
-  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
-  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
-  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
-  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
-  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
-  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
-  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
-  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
-  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
-  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
-  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */ 
-  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
-} CAN_TypeDef;
-
-/** 
-  * @brief CRC calculation unit 
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
-  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */
-  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
-  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
-  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
-}CRC_TypeDef;
-
-/**
-  * @brief DFSDM module registers
-  */
-typedef struct
-{
-  __IO uint32_t FLTCR1;      /*!< DFSDM control register1,                          Address offset: 0x100 */
-  __IO uint32_t FLTCR2;      /*!< DFSDM control register2,                          Address offset: 0x104 */
-  __IO uint32_t FLTISR;      /*!< DFSDM interrupt and status register,              Address offset: 0x108 */
-  __IO uint32_t FLTICR;      /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */
-  __IO uint32_t FLTJCHGR;    /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */
-  __IO uint32_t FLTFCR;      /*!< DFSDM filter control register,                    Address offset: 0x114 */
-  __IO uint32_t FLTJDATAR;   /*!< DFSDM data register for injected group,           Address offset: 0x118 */
-  __IO uint32_t FLTRDATAR;   /*!< DFSDM data register for regular group,            Address offset: 0x11C */
-  __IO uint32_t FLTAWHTR;    /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */
-  __IO uint32_t FLTAWLTR;    /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */
-  __IO uint32_t FLTAWSR;     /*!< DFSDM analog watchdog status register             Address offset: 0x128 */
-  __IO uint32_t FLTAWCFR;    /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */
-  __IO uint32_t FLTEXMAX;    /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */
-  __IO uint32_t FLTEXMIN;    /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */
-  __IO uint32_t FLTCNVTIMR;  /*!< DFSDM conversion timer,                           Address offset: 0x138 */
-} DFSDM_Filter_TypeDef;
-
-/**
-  * @brief DFSDM channel configuration registers
-  */
-typedef struct
-{
-  __IO uint32_t CHCFGR1;     /*!< DFSDM channel configuration register1,            Address offset: 0x00 */
-  __IO uint32_t CHCFGR2;     /*!< DFSDM channel configuration register2,            Address offset: 0x04 */
-  __IO uint32_t CHAWSCDR;    /*!< DFSDM channel analog watchdog and
-                                  short circuit detector register,                  Address offset: 0x08 */
-  __IO uint32_t CHWDATAR;    /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */
-  __IO uint32_t CHDATINR;    /*!< DFSDM channel data input register,                Address offset: 0x10 */
-} DFSDM_Channel_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-typedef struct
-{
-  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
-  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
-  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
-  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
-  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
-  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
-  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
-  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
-  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
-} DMA_Stream_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
-  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
-  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
-  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
-} DMA_TypeDef;
-
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
-  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
-  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
-  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
-  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
-  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-
-typedef struct
-{
-  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */
-  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */
-  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */
-  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */
-  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */
-  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief Flexible Memory Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */   
-} FSMC_Bank1_TypeDef; 
-
-/** 
-  * @brief Flexible Memory Controller Bank1E
-  */
-  
-typedef struct
-{
-  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
-} FSMC_Bank1E_TypeDef;
-
-/** 
-  * @brief General Purpose I/O
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
-  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
-  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
-  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
-  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
-  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
-  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
-  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/** 
-  * @brief System configuration controller
-  */
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */ 
-  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
-  uint32_t      RESERVED1[2]; /*!< Reserved, 0x24-0x28                                                          */ 
-  __IO uint32_t CFGR;         /*!< SYSCFG Configuration register,                     Address offset: 0x2C      */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */
-  __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */
-  __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */
-  __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */
-  __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */
-  __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
-  __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
-  __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
-  __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */
-} I2C_TypeDef;
-
-/**
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< FMPI2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< FMPI2C Control register 2,            Address offset: 0x04 */
-  __IO uint32_t OAR1;        /*!< FMPI2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;        /*!< FMPI2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;     /*!< FMPI2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR;    /*!< FMPI2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;         /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;         /*!< FMPI2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;        /*!< FMPI2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;        /*!< FMPI2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;        /*!< FMPI2C Transmit data register,        Address offset: 0x28 */
-} FMPI2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
-  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
-  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
-  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
-  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
-  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
-  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
-  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
-  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
-  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
-  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
-  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
-  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
-  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
-  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
-  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
-  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
-  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
-  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
-  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
-  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
-  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
-  uint32_t      RESERVED7;     /*!< Reserved, 0x84                                                                    */
-  __IO uint32_t DCKCFGR;       /*!< RCC Dedicated Clocks configuration register,                 Address offset: 0x8C */
-  __IO uint32_t CKGATENR;       /*!< RCC Clocks Gated ENable Register,                           Address offset: 0x90 */
-  __IO uint32_t DCKCFGR2;      /*!< RCC Dedicated Clocks configuration register 2,               Address offset: 0x94 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-
-typedef struct
-{
-  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
-  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
-  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
-  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
-  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
-  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
-  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */
-  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
-  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */
-  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
-  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */
-  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */
-  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */
-  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */
-  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
-  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */
-  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
-  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
-  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
-  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
-  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
-  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
-  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
-  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
-  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
-  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
-  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
-  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
-  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
-  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
-  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
-  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
-  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
-  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
-  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
-  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
-  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
-} RTC_TypeDef;
-
-
-/** 
-  * @brief SD host Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t POWER;          /*!< SDIO power control register,    Address offset: 0x00 */
-  __IO uint32_t CLKCR;          /*!< SDI clock control register,     Address offset: 0x04 */
-  __IO uint32_t ARG;            /*!< SDIO argument register,         Address offset: 0x08 */
-  __IO uint32_t CMD;            /*!< SDIO command register,          Address offset: 0x0C */
-  __I uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */
-  __I uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */
-  __I uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */
-  __I uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */
-  __I uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */
-  __IO uint32_t DTIMER;         /*!< SDIO data timer register,       Address offset: 0x24 */
-  __IO uint32_t DLEN;           /*!< SDIO data length register,      Address offset: 0x28 */
-  __IO uint32_t DCTRL;          /*!< SDIO data control register,     Address offset: 0x2C */
-  __I uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */
-  __I uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */
-  __IO uint32_t ICR;            /*!< SDIO interrupt clear register,  Address offset: 0x38 */
-  __IO uint32_t MASK;           /*!< SDIO mask register,             Address offset: 0x3C */
-  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
-  __I uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */
-  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
-  __IO uint32_t FIFO;           /*!< SDIO data FIFO register,        Address offset: 0x80 */
-} SDIO_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief QUAD Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */
-  __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
-  __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */
-  __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
-  __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
-  __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
-  __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */
-  __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
-  __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */
-  __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
-  __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */                  
-  __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
-  __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */    
-} QUADSPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
-  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
-  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
-  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-
-/** 
-  * @brief RNG
-  */
-  
-typedef struct 
-{
-  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
-  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
-  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
-} RNG_TypeDef;
-
-
-/** 
-  * @brief USB_OTG_Core_Registers
-  */
-typedef struct
-{
-  __IO uint32_t GOTGCTL;              /*!<  USB_OTG Control and Status Register            000h*/
-  __IO uint32_t GOTGINT;              /*!<  USB_OTG Interrupt Register                     004h*/
-  __IO uint32_t GAHBCFG;              /*!<  Core AHB Configuration Register                008h*/
-  __IO uint32_t GUSBCFG;              /*!<  Core USB Configuration Register                00Ch*/
-  __IO uint32_t GRSTCTL;              /*!<  Core Reset Register                            010h*/
-  __IO uint32_t GINTSTS;              /*!<  Core Interrupt Register                        014h*/
-  __IO uint32_t GINTMSK;              /*!<  Core Interrupt Mask Register                   018h*/
-  __IO uint32_t GRXSTSR;              /*!<  Receive Sts Q Read Register                    01Ch*/
-  __IO uint32_t GRXSTSP;              /*!<  Receive Sts Q Read & POP Register              020h*/
-  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                      024h*/
-  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!<  EP0 / Non Periodic Tx FIFO Size Register       028h*/
-  __IO uint32_t HNPTXSTS;             /*!<  Non Periodic Tx FIFO/Queue Sts reg             02Ch*/
-  uint32_t Reserved30[2];             /*!< Reserved                                        030h*/
-  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                     038h*/
-  __IO uint32_t CID;                  /*!< User ID Register                                03Ch*/
-  uint32_t  Reserved5[3];             /*!< Reserved                                        040h-048h*/
-  __IO uint32_t GHWCFG3;              /*!< User HW config3                                 04Ch*/
-  uint32_t  Reserved6;                /*!< Reserved                                        050h*/ 
-  __IO uint32_t GLPMCFG;              /*!< LPM Register                                    054h*/
-  uint32_t  Reserved;                 /*!< Reserved                                        058h */
-  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register                  05Ch */
-  uint32_t  Reserved43[40];           /*!< Reserved                                        058h-0FFh */
-  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg                  100h*/
-  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */
-} USB_OTG_GlobalTypeDef;
-
-
-/** 
-  * @brief USB_OTG_device_Registers
-  */
-typedef struct 
-{
-  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */
-  __IO uint32_t DCTL;            /*!< dev Control Register         804h */
-  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */
-  uint32_t Reserved0C;           /*!< Reserved                     80Ch */
-  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */
-  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */
-  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */
-  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */
-  uint32_t  Reserved20;          /*!< Reserved                     820h */
-  uint32_t Reserved9;            /*!< Reserved                     824h */
-  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */
-  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */
-  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */
-  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */
-  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */
-  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */
-  uint32_t Reserved40;           /*!< dedicated EP mask            840h */
-  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */
-  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */
-  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */
-} USB_OTG_DeviceTypeDef;
-
-
-/** 
-  * @brief USB_OTG_IN_Endpoint-Specific_Register
-  */
-typedef struct 
-{
-  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */
-  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */
-  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */
-  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */
-  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */
-  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */
-  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
-  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
-} USB_OTG_INEndpointTypeDef;
-
-
-/** 
-  * @brief USB_OTG_OUT_Endpoint-Specific_Registers
-  */
-typedef struct 
-{
-  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */
-  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */
-  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */
-  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */
-  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */
-  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */
-  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
-} USB_OTG_OUTEndpointTypeDef;
-
-
-/** 
-  * @brief USB_OTG_Host_Mode_Register_Structures
-  */
-typedef struct 
-{
-  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */
-  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */
-  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */
-  uint32_t Reserved40C;           /*!< Reserved                             40Ch */
-  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */
-  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */
-  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */
-} USB_OTG_HostTypeDef;
-
-
-/** 
-  * @brief USB_OTG_Host_Channel_Specific_Registers
-  */
-typedef struct
-{
-  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */
-  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */
-  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */
-  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */
-  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */
-  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */
-  uint32_t Reserved[2];           /*!< Reserved                                      */
-} USB_OTG_HostChannelTypeDef;
-
-    
-/** 
-  * @brief Peripheral_memory_map
-  */
-#define FLASH_BASE            0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region                         */
-#define SRAM1_BASE            0x20000000U /*!< SRAM1(256 KB) base address in the alias region                             */
-#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region                                */
-#define FSMC_R_BASE           0xA0000000U /*!< FSMC registers base address                                                */
-#define QSPI_R_BASE           0xA0001000U /*!< QuadSPI registers base address                                             */
-
-#define SRAM1_BB_BASE         0x22000000U /*!< SRAM1(256 KB) base address in the bit-band region                             */
-#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region                                */
-#define FLASH_END             0x080FFFFFU /*!< FLASH end address                                                             */
-
-/* Legacy defines */
-#define SRAM_BASE             SRAM1_BASE
-#define SRAM_BB_BASE          SRAM1_BB_BASE
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000U)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)
-#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800U)
-#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00U)
-#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000U)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)
-#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400U)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)
-#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000U)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800U)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)
-#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)
-#define FMPI2C1_BASE          (APB1PERIPH_BASE + 0x6000U)
-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)
-#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800U)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)
-
-/*!< APB2 peripherals */
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000U)
-#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400U)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x1000U)
-#define USART6_BASE           (APB2PERIPH_BASE + 0x1400U)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000U)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x2300U)
-#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00U)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)
-#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400U)
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800U)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00U)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000U)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400U)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800U)
-#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000U)
-#define DFSDM1_BASE           (APB2PERIPH_BASE + 0x6000U)
-#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00U)
-#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20U)
-#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40U)
-#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60U)
-#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100U)
-#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180U)
-
-/*!< AHB1 peripherals */
-#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000U)
-#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400U)
-#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800U)
-#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00U)
-#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000U)
-#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400U)
-#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800U)
-#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00U)
-#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)
-#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800U)
-#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00U)
-#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000U)
-#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010U)
-#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028U)
-#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040U)
-#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058U)
-#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070U)
-#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088U)
-#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0U)
-#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8U)
-#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400U)
-#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010U)
-#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028U)
-#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040U)
-#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058U)
-#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070U)
-#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088U)
-#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0U)
-#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)
-
-/*!< AHB2 peripherals */
-#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800U)
-
-/*!< FSMC Bankx registers base address */
-#define FSMC_Bank1_R_BASE      (FSMC_R_BASE + 0x0000U)
-#define FSMC_Bank1E_R_BASE     (FSMC_R_BASE + 0x0104U)
-
-/* Debug MCU registers base address */
-#define DBGMCU_BASE           0xE0042000U
-
-/*!< USB registers base address */
-#define USB_OTG_FS_PERIPH_BASE               0x50000000U
-
-#define USB_OTG_GLOBAL_BASE                  0x000U
-#define USB_OTG_DEVICE_BASE                  0x800U
-#define USB_OTG_IN_ENDPOINT_BASE             0x900U
-#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U
-#define USB_OTG_EP_REG_SIZE                  0x20U
-#define USB_OTG_HOST_BASE                    0x400U
-#define USB_OTG_HOST_PORT_BASE               0x440U
-#define USB_OTG_HOST_CHANNEL_BASE            0x500U
-#define USB_OTG_HOST_CHANNEL_SIZE            0x20U
-#define USB_OTG_PCGCCTL_BASE                 0xE00U
-#define USB_OTG_FIFO_BASE                    0x1000U
-#define USB_OTG_FIFO_SIZE                    0x1000U
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
-#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
-#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
-#define FMPI2C1             ((FMPI2C_TypeDef *) FMPI2C1_BASE)
-#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
-#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
-#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define USART6              ((USART_TypeDef *) USART6_BASE)
-#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define SPI4                ((SPI_TypeDef *) SPI4_BASE)
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-#define SPI5                ((SPI_TypeDef *) SPI5_BASE)
-#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
-#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
-#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
-#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
-#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
-#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
-#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
-#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
-#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
-#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
-#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
-#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
-#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
-#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
-#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
-#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
-#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
-#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
-#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
-#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
-#define RNG                 ((RNG_TypeDef *) RNG_BASE)
-#define FSMC_Bank1           ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
-#define FSMC_Bank1E          ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
-#define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)
-
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers_Bits_Definition               */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Analog to Digital Converter                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          0x00000001U       /*!<Analog watchdog flag */
-#define  ADC_SR_EOC                          0x00000002U       /*!<End of conversion */
-#define  ADC_SR_JEOC                         0x00000004U       /*!<Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        0x00000008U       /*!<Injected channel Start flag */
-#define  ADC_SR_STRT                         0x00000010U       /*!<Regular channel Start flag */
-#define  ADC_SR_OVR                          0x00000020U       /*!<Overrun flag */
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
-#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels */
-#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels */
-#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution) */
-#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
-  
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion */
-#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode */
-#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC) */
-#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection */
-#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment */
-#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      0xFFFFU            /*!<Injected data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag */
-#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion */
-#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag */
-#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag */
-#define  ADC_CSR_DOVR1                       0x00000020U        /*!<ADC1 DMA overrun  flag */
-#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag */
-#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion */
-#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag */
-#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag */
-#define  ADC_CSR_DOVR2                       0x00002000U        /*!<ADC2 DMA overrun  flag */
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
-#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
-#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
-#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
-#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
-
-/*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                      0x0000FFFFU         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                      0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Controller Area Network                            */
-/*                                                                            */
-/******************************************************************************/
-/*!<CAN control and status registers */
-/*******************  Bit definition for CAN_MCR register  ********************/
-#define  CAN_MCR_INRQ                        0x00000001U        /*!<Initialization Request */
-#define  CAN_MCR_SLEEP                       0x00000002U        /*!<Sleep Mode Request */
-#define  CAN_MCR_TXFP                        0x00000004U        /*!<Transmit FIFO Priority */
-#define  CAN_MCR_RFLM                        0x00000008U        /*!<Receive FIFO Locked Mode */
-#define  CAN_MCR_NART                        0x00000010U        /*!<No Automatic Retransmission */
-#define  CAN_MCR_AWUM                        0x00000020U        /*!<Automatic Wakeup Mode */
-#define  CAN_MCR_ABOM                        0x00000040U        /*!<Automatic Bus-Off Management */
-#define  CAN_MCR_TTCM                        0x00000080U        /*!<Time Triggered Communication Mode */
-#define  CAN_MCR_RESET                       0x00008000U        /*!<bxCAN software master reset */
-#define  CAN_MCR_DBF                         0x00010000U        /*!<bxCAN Debug freeze */
-/*******************  Bit definition for CAN_MSR register  ********************/
-#define  CAN_MSR_INAK                        0x0001U            /*!<Initialization Acknowledge */
-#define  CAN_MSR_SLAK                        0x0002U            /*!<Sleep Acknowledge */
-#define  CAN_MSR_ERRI                        0x0004U            /*!<Error Interrupt */
-#define  CAN_MSR_WKUI                        0x0008U            /*!<Wakeup Interrupt */
-#define  CAN_MSR_SLAKI                       0x0010U            /*!<Sleep Acknowledge Interrupt */
-#define  CAN_MSR_TXM                         0x0100U            /*!<Transmit Mode */
-#define  CAN_MSR_RXM                         0x0200U            /*!<Receive Mode */
-#define  CAN_MSR_SAMP                        0x0400U            /*!<Last Sample Point */
-#define  CAN_MSR_RX                          0x0800U            /*!<CAN Rx Signal */
-
-/*******************  Bit definition for CAN_TSR register  ********************/
-#define  CAN_TSR_RQCP0                       0x00000001U        /*!<Request Completed Mailbox0 */
-#define  CAN_TSR_TXOK0                       0x00000002U        /*!<Transmission OK of Mailbox0 */
-#define  CAN_TSR_ALST0                       0x00000004U        /*!<Arbitration Lost for Mailbox0 */
-#define  CAN_TSR_TERR0                       0x00000008U        /*!<Transmission Error of Mailbox0 */
-#define  CAN_TSR_ABRQ0                       0x00000080U        /*!<Abort Request for Mailbox0 */
-#define  CAN_TSR_RQCP1                       0x00000100U        /*!<Request Completed Mailbox1 */
-#define  CAN_TSR_TXOK1                       0x00000200U        /*!<Transmission OK of Mailbox1 */
-#define  CAN_TSR_ALST1                       0x00000400U        /*!<Arbitration Lost for Mailbox1 */
-#define  CAN_TSR_TERR1                       0x00000800U        /*!<Transmission Error of Mailbox1 */
-#define  CAN_TSR_ABRQ1                       0x00008000U        /*!<Abort Request for Mailbox 1 */
-#define  CAN_TSR_RQCP2                       0x00010000U        /*!<Request Completed Mailbox2 */
-#define  CAN_TSR_TXOK2                       0x00020000U        /*!<Transmission OK of Mailbox 2 */
-#define  CAN_TSR_ALST2                       0x00040000U        /*!<Arbitration Lost for mailbox 2 */
-#define  CAN_TSR_TERR2                       0x00080000U        /*!<Transmission Error of Mailbox 2 */
-#define  CAN_TSR_ABRQ2                       0x00800000U        /*!<Abort Request for Mailbox 2 */
-#define  CAN_TSR_CODE                        0x03000000U        /*!<Mailbox Code */
-
-#define  CAN_TSR_TME                         0x1C000000U        /*!<TME[2:0] bits */
-#define  CAN_TSR_TME0                        0x04000000U        /*!<Transmit Mailbox 0 Empty */
-#define  CAN_TSR_TME1                        0x08000000U        /*!<Transmit Mailbox 1 Empty */
-#define  CAN_TSR_TME2                        0x10000000U        /*!<Transmit Mailbox 2 Empty */
-
-#define  CAN_TSR_LOW                         0xE0000000U        /*!<LOW[2:0] bits */
-#define  CAN_TSR_LOW0                        0x20000000U        /*!<Lowest Priority Flag for Mailbox 0 */
-#define  CAN_TSR_LOW1                        0x40000000U        /*!<Lowest Priority Flag for Mailbox 1 */
-#define  CAN_TSR_LOW2                        0x80000000U        /*!<Lowest Priority Flag for Mailbox 2 */
-
-/*******************  Bit definition for CAN_RF0R register  *******************/
-#define  CAN_RF0R_FMP0                       0x03U               /*!<FIFO 0 Message Pending */
-#define  CAN_RF0R_FULL0                      0x08U               /*!<FIFO 0 Full */
-#define  CAN_RF0R_FOVR0                      0x10U               /*!<FIFO 0 Overrun */
-#define  CAN_RF0R_RFOM0                      0x20U               /*!<Release FIFO 0 Output Mailbox */
-
-/*******************  Bit definition for CAN_RF1R register  *******************/
-#define  CAN_RF1R_FMP1                       0x03U               /*!<FIFO 1 Message Pending */
-#define  CAN_RF1R_FULL1                      0x08U               /*!<FIFO 1 Full */
-#define  CAN_RF1R_FOVR1                      0x10U               /*!<FIFO 1 Overrun */
-#define  CAN_RF1R_RFOM1                      0x20U               /*!<Release FIFO 1 Output Mailbox */
-
-/********************  Bit definition for CAN_IER register  *******************/
-#define  CAN_IER_TMEIE                       0x00000001U        /*!<Transmit Mailbox Empty Interrupt Enable */
-#define  CAN_IER_FMPIE0                      0x00000002U        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE0                       0x00000004U        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE0                      0x00000008U        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_FMPIE1                      0x00000010U        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE1                       0x00000020U        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE1                      0x00000040U        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error Warning Interrupt Enable */
-#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error Passive Interrupt Enable */
-#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-Off Interrupt Enable */
-#define  CAN_IER_LECIE                       0x00000800U        /*!<Last Error Code Interrupt Enable */
-#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error Interrupt Enable */
-#define  CAN_IER_WKUIE                       0x00010000U        /*!<Wakeup Interrupt Enable */
-#define  CAN_IER_SLKIE                       0x00020000U        /*!<Sleep Interrupt Enable */
-#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error warning interrupt enable */
-#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error passive interrupt enable */
-#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-off interrupt enable */
-#define  CAN_IER_LECIE                       0x00000800U        /*!<Last error code interrupt enable */
-#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error interrupt enable */
-
-
-/********************  Bit definition for CAN_ESR register  *******************/
-#define  CAN_ESR_EWGF                        0x00000001U        /*!<Error Warning Flag */
-#define  CAN_ESR_EPVF                        0x00000002U        /*!<Error Passive Flag */
-#define  CAN_ESR_BOFF                        0x00000004U        /*!<Bus-Off Flag */
-
-#define  CAN_ESR_LEC                         0x00000070U        /*!<LEC[2:0] bits (Last Error Code) */
-#define  CAN_ESR_LEC_0                       0x00000010U        /*!<Bit 0 */
-#define  CAN_ESR_LEC_1                       0x00000020U        /*!<Bit 1 */
-#define  CAN_ESR_LEC_2                       0x00000040U        /*!<Bit 2 */
-
-#define  CAN_ESR_TEC                         0x00FF0000U        /*!<Least significant byte of the 9-bit Transmit Error Counter */
-#define  CAN_ESR_REC                         0xFF000000U        /*!<Receive Error Counter */
-
-/*******************  Bit definition for CAN_BTR register  ********************/
-#define  CAN_BTR_BRP                         0x000003FFU        /*!<Baud Rate Prescaler */
-#define  CAN_BTR_TS1                         0x000F0000U        /*!<Time Segment 1 */
-#define  CAN_BTR_TS1_0                       0x00010000U        /*!<Bit 0 */
-#define  CAN_BTR_TS1_1                       0x00020000U        /*!<Bit 1 */
-#define  CAN_BTR_TS1_2                       0x00040000U        /*!<Bit 2 */
-#define  CAN_BTR_TS1_3                       0x00080000U        /*!<Bit 3 */
-#define  CAN_BTR_TS2                         0x00700000U        /*!<Time Segment 2 */
-#define  CAN_BTR_TS2_0                       0x00100000U        /*!<Bit 0 */
-#define  CAN_BTR_TS2_1                       0x00200000U        /*!<Bit 1 */
-#define  CAN_BTR_TS2_2                       0x00400000U        /*!<Bit 2 */
-#define  CAN_BTR_SJW                         0x03000000U        /*!<Resynchronization Jump Width */
-#define  CAN_BTR_SJW_0                       0x01000000U        /*!<Bit 0 */
-#define  CAN_BTR_SJW_1                       0x02000000U        /*!<Bit 1 */
-#define  CAN_BTR_LBKM                        0x40000000U        /*!<Loop Back Mode (Debug) */
-#define  CAN_BTR_SILM                        0x80000000U        /*!<Silent Mode */
-
-
-/*!<Mailbox registers */
-/******************  Bit definition for CAN_TI0R register  ********************/
-#define  CAN_TI0R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI0R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_TI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/******************  Bit definition for CAN_TDT0R register  *******************/
-#define  CAN_TDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT0R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/******************  Bit definition for CAN_TDL0R register  *******************/
-#define  CAN_TDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/******************  Bit definition for CAN_TDH0R register  *******************/
-#define  CAN_TDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI1R register  *******************/
-#define  CAN_TI1R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI1R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI1R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_TI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT1R register  ******************/
-#define  CAN_TDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT1R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL1R register  ******************/
-#define  CAN_TDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH1R register  ******************/
-#define  CAN_TDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI2R register  *******************/
-#define  CAN_TI2R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI2R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI2R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI2R_EXID                       0x001FFFF8U        /*!<Extended identifier */
-#define  CAN_TI2R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT2R register  ******************/  
-#define  CAN_TDT2R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT2R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT2R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL2R register  ******************/
-#define  CAN_TDL2R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL2R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL2R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL2R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH2R register  ******************/
-#define  CAN_TDH2R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH2R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH2R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH2R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI0R register  *******************/
-#define  CAN_RI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_RI0R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_RI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_RI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT0R register  ******************/
-#define  CAN_RDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_RDT0R_FMI                       0x0000FF00U        /*!<Filter Match Index */
-#define  CAN_RDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL0R register  ******************/
-#define  CAN_RDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_RDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_RDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_RDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH0R register  ******************/
-#define  CAN_RDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_RDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_RDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_RDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI1R register  *******************/
-#define  CAN_RI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_RI1R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_RI1R_EXID                       0x001FFFF8U        /*!<Extended identifier */
-#define  CAN_RI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT1R register  ******************/
-#define  CAN_RDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_RDT1R_FMI                       0x0000FF00U        /*!<Filter Match Index */
-#define  CAN_RDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL1R register  ******************/
-#define  CAN_RDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_RDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_RDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_RDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH1R register  ******************/
-#define  CAN_RDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_RDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_RDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_RDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*!<CAN filter registers */
-/*******************  Bit definition for CAN_FMR register  ********************/
-#define  CAN_FMR_FINIT                       0x01U               /*!<Filter Init Mode */
-#define  CAN_FMR_CAN2SB                      0x00003F00U        /*!<CAN2 start bank */
-
-/*******************  Bit definition for CAN_FM1R register  *******************/
-#define  CAN_FM1R_FBM                        0x0FFFFFFFU        /*!<Filter Mode */
-#define  CAN_FM1R_FBM0                       0x00000001U        /*!<Filter Init Mode bit 0 */
-#define  CAN_FM1R_FBM1                       0x00000002U        /*!<Filter Init Mode bit 1 */
-#define  CAN_FM1R_FBM2                       0x00000004U        /*!<Filter Init Mode bit 2 */
-#define  CAN_FM1R_FBM3                       0x00000008U        /*!<Filter Init Mode bit 3 */
-#define  CAN_FM1R_FBM4                       0x00000010U        /*!<Filter Init Mode bit 4 */
-#define  CAN_FM1R_FBM5                       0x00000020U        /*!<Filter Init Mode bit 5 */
-#define  CAN_FM1R_FBM6                       0x00000040U        /*!<Filter Init Mode bit 6 */
-#define  CAN_FM1R_FBM7                       0x00000080U        /*!<Filter Init Mode bit 7 */
-#define  CAN_FM1R_FBM8                       0x00000100U        /*!<Filter Init Mode bit 8 */
-#define  CAN_FM1R_FBM9                       0x00000200U        /*!<Filter Init Mode bit 9 */
-#define  CAN_FM1R_FBM10                      0x00000400U        /*!<Filter Init Mode bit 10 */
-#define  CAN_FM1R_FBM11                      0x00000800U        /*!<Filter Init Mode bit 11 */
-#define  CAN_FM1R_FBM12                      0x00001000U        /*!<Filter Init Mode bit 12 */
-#define  CAN_FM1R_FBM13                      0x00002000U        /*!<Filter Init Mode bit 13 */
-#define  CAN_FM1R_FBM14                      0x00004000U        /*!<Filter Init Mode bit 14 */
-#define  CAN_FM1R_FBM15                      0x00008000U        /*!<Filter Init Mode bit 15 */
-#define  CAN_FM1R_FBM16                      0x00010000U        /*!<Filter Init Mode bit 16 */
-#define  CAN_FM1R_FBM17                      0x00020000U        /*!<Filter Init Mode bit 17 */
-#define  CAN_FM1R_FBM18                      0x00040000U        /*!<Filter Init Mode bit 18 */
-#define  CAN_FM1R_FBM19                      0x00080000U        /*!<Filter Init Mode bit 19 */
-#define  CAN_FM1R_FBM20                      0x00100000U        /*!<Filter Init Mode bit 20 */
-#define  CAN_FM1R_FBM21                      0x00200000U        /*!<Filter Init Mode bit 21 */
-#define  CAN_FM1R_FBM22                      0x00400000U        /*!<Filter Init Mode bit 22 */
-#define  CAN_FM1R_FBM23                      0x00800000U        /*!<Filter Init Mode bit 23 */
-#define  CAN_FM1R_FBM24                      0x01000000U        /*!<Filter Init Mode bit 24 */
-#define  CAN_FM1R_FBM25                      0x02000000U        /*!<Filter Init Mode bit 25 */
-#define  CAN_FM1R_FBM26                      0x04000000U        /*!<Filter Init Mode bit 26 */
-#define  CAN_FM1R_FBM27                      0x08000000U        /*!<Filter Init Mode bit 27 */
-
-/*******************  Bit definition for CAN_FS1R register  *******************/
-#define  CAN_FS1R_FSC                        0x0FFFFFFFU        /*!<Filter Scale Configuration */
-#define  CAN_FS1R_FSC0                       0x00000001U        /*!<Filter Scale Configuration bit 0 */
-#define  CAN_FS1R_FSC1                       0x00000002U        /*!<Filter Scale Configuration bit 1 */
-#define  CAN_FS1R_FSC2                       0x00000004U        /*!<Filter Scale Configuration bit 2 */
-#define  CAN_FS1R_FSC3                       0x00000008U        /*!<Filter Scale Configuration bit 3 */
-#define  CAN_FS1R_FSC4                       0x00000010U        /*!<Filter Scale Configuration bit 4 */
-#define  CAN_FS1R_FSC5                       0x00000020U        /*!<Filter Scale Configuration bit 5 */
-#define  CAN_FS1R_FSC6                       0x00000040U        /*!<Filter Scale Configuration bit 6 */
-#define  CAN_FS1R_FSC7                       0x00000080U        /*!<Filter Scale Configuration bit 7 */
-#define  CAN_FS1R_FSC8                       0x00000100U        /*!<Filter Scale Configuration bit 8 */
-#define  CAN_FS1R_FSC9                       0x00000200U        /*!<Filter Scale Configuration bit 9 */
-#define  CAN_FS1R_FSC10                      0x00000400U        /*!<Filter Scale Configuration bit 10 */
-#define  CAN_FS1R_FSC11                      0x00000800U        /*!<Filter Scale Configuration bit 11 */
-#define  CAN_FS1R_FSC12                      0x00001000U        /*!<Filter Scale Configuration bit 12 */
-#define  CAN_FS1R_FSC13                      0x00002000U        /*!<Filter Scale Configuration bit 13 */
-#define  CAN_FS1R_FSC14                      0x00004000U        /*!<Filter Scale Configuration bit 14 */
-#define  CAN_FS1R_FSC15                      0x00008000U        /*!<Filter Scale Configuration bit 15 */
-#define  CAN_FS1R_FSC16                      0x00010000U        /*!<Filter Scale Configuration bit 16 */
-#define  CAN_FS1R_FSC17                      0x00020000U        /*!<Filter Scale Configuration bit 17 */
-#define  CAN_FS1R_FSC18                      0x00040000U        /*!<Filter Scale Configuration bit 18 */
-#define  CAN_FS1R_FSC19                      0x00080000U        /*!<Filter Scale Configuration bit 19 */
-#define  CAN_FS1R_FSC20                      0x00100000U        /*!<Filter Scale Configuration bit 20 */
-#define  CAN_FS1R_FSC21                      0x00200000U        /*!<Filter Scale Configuration bit 21 */
-#define  CAN_FS1R_FSC22                      0x00400000U        /*!<Filter Scale Configuration bit 22 */
-#define  CAN_FS1R_FSC23                      0x00800000U        /*!<Filter Scale Configuration bit 23 */
-#define  CAN_FS1R_FSC24                      0x01000000U        /*!<Filter Scale Configuration bit 24 */
-#define  CAN_FS1R_FSC25                      0x02000000U        /*!<Filter Scale Configuration bit 25 */
-#define  CAN_FS1R_FSC26                      0x04000000U        /*!<Filter Scale Configuration bit 26 */
-#define  CAN_FS1R_FSC27                      0x08000000U        /*!<Filter Scale Configuration bit 27 */
-
-/******************  Bit definition for CAN_FFA1R register  *******************/
-#define  CAN_FFA1R_FFA                        0x0FFFFFFFU        /*!<Filter FIFO Assignment */
-#define  CAN_FFA1R_FFA0                       0x00000001U        /*!<Filter FIFO Assignment bit 0 */
-#define  CAN_FFA1R_FFA1                       0x00000002U        /*!<Filter FIFO Assignment bit 1 */
-#define  CAN_FFA1R_FFA2                       0x00000004U        /*!<Filter FIFO Assignment bit 2 */
-#define  CAN_FFA1R_FFA3                       0x00000008U        /*!<Filter FIFO Assignment bit 3 */
-#define  CAN_FFA1R_FFA4                       0x00000010U        /*!<Filter FIFO Assignment bit 4 */
-#define  CAN_FFA1R_FFA5                       0x00000020U        /*!<Filter FIFO Assignment bit 5 */
-#define  CAN_FFA1R_FFA6                       0x00000040U        /*!<Filter FIFO Assignment bit 6 */
-#define  CAN_FFA1R_FFA7                       0x00000080U        /*!<Filter FIFO Assignment bit 7 */
-#define  CAN_FFA1R_FFA8                       0x00000100U        /*!<Filter FIFO Assignment bit 8 */
-#define  CAN_FFA1R_FFA9                       0x00000200U        /*!<Filter FIFO Assignment bit 9 */
-#define  CAN_FFA1R_FFA10                      0x00000400U        /*!<Filter FIFO Assignment bit 10 */
-#define  CAN_FFA1R_FFA11                      0x00000800U        /*!<Filter FIFO Assignment bit 11 */
-#define  CAN_FFA1R_FFA12                      0x00001000U        /*!<Filter FIFO Assignment bit 12 */
-#define  CAN_FFA1R_FFA13                      0x00002000U        /*!<Filter FIFO Assignment bit 13 */
-#define  CAN_FFA1R_FFA14                      0x00004000U        /*!<Filter FIFO Assignment bit 14 */
-#define  CAN_FFA1R_FFA15                      0x00008000U        /*!<Filter FIFO Assignment bit 15 */
-#define  CAN_FFA1R_FFA16                      0x00010000U        /*!<Filter FIFO Assignment bit 16 */
-#define  CAN_FFA1R_FFA17                      0x00020000U        /*!<Filter FIFO Assignment bit 17 */
-#define  CAN_FFA1R_FFA18                      0x00040000U        /*!<Filter FIFO Assignment bit 18 */
-#define  CAN_FFA1R_FFA19                      0x00080000U        /*!<Filter FIFO Assignment bit 19 */
-#define  CAN_FFA1R_FFA20                      0x00100000U        /*!<Filter FIFO Assignment bit 20 */
-#define  CAN_FFA1R_FFA21                      0x00200000U        /*!<Filter FIFO Assignment bit 21 */
-#define  CAN_FFA1R_FFA22                      0x00400000U        /*!<Filter FIFO Assignment bit 22 */
-#define  CAN_FFA1R_FFA23                      0x00800000U        /*!<Filter FIFO Assignment bit 23 */
-#define  CAN_FFA1R_FFA24                      0x01000000U        /*!<Filter FIFO Assignment bit 24 */
-#define  CAN_FFA1R_FFA25                      0x02000000U        /*!<Filter FIFO Assignment bit 25 */
-#define  CAN_FFA1R_FFA26                      0x04000000U        /*!<Filter FIFO Assignment bit 26 */
-#define  CAN_FFA1R_FFA27                      0x08000000U        /*!<Filter FIFO Assignment bit 27 */
-
-/*******************  Bit definition for CAN_FA1R register  *******************/
-#define  CAN_FA1R_FACT                        0x0FFFFFFFU        /*!<Filter Active */
-#define  CAN_FA1R_FACT0                       0x00000001U        /*!<Filter Active bit 0 */
-#define  CAN_FA1R_FACT1                       0x00000002U        /*!<Filter Active bit 1 */
-#define  CAN_FA1R_FACT2                       0x00000004U        /*!<Filter Active bit 2 */
-#define  CAN_FA1R_FACT3                       0x00000008U        /*!<Filter Active bit 3 */
-#define  CAN_FA1R_FACT4                       0x00000010U        /*!<Filter Active bit 4 */
-#define  CAN_FA1R_FACT5                       0x00000020U        /*!<Filter Active bit 5 */
-#define  CAN_FA1R_FACT6                       0x00000040U        /*!<Filter Active bit 6 */
-#define  CAN_FA1R_FACT7                       0x00000080U        /*!<Filter Active bit 7 */
-#define  CAN_FA1R_FACT8                       0x00000100U        /*!<Filter Active bit 8 */
-#define  CAN_FA1R_FACT9                       0x00000200U        /*!<Filter Active bit 9 */
-#define  CAN_FA1R_FACT10                      0x00000400U        /*!<Filter Active bit 10 */
-#define  CAN_FA1R_FACT11                      0x00000800U        /*!<Filter Active bit 11 */
-#define  CAN_FA1R_FACT12                      0x00001000U        /*!<Filter Active bit 12 */
-#define  CAN_FA1R_FACT13                      0x00002000U        /*!<Filter Active bit 13 */
-#define  CAN_FA1R_FACT14                      0x00004000U        /*!<Filter Active bit 14 */
-#define  CAN_FA1R_FACT15                      0x00008000U        /*!<Filter Active bit 15 */
-#define  CAN_FA1R_FACT16                      0x00010000U        /*!<Filter Active bit 16 */
-#define  CAN_FA1R_FACT17                      0x00020000U        /*!<Filter Active bit 17 */
-#define  CAN_FA1R_FACT18                      0x00040000U        /*!<Filter Active bit 18 */
-#define  CAN_FA1R_FACT19                      0x00080000U        /*!<Filter Active bit 19 */
-#define  CAN_FA1R_FACT20                      0x00100000U        /*!<Filter Active bit 20 */
-#define  CAN_FA1R_FACT21                      0x00200000U        /*!<Filter Active bit 21 */
-#define  CAN_FA1R_FACT22                      0x00400000U        /*!<Filter Active bit 22 */
-#define  CAN_FA1R_FACT23                      0x00800000U        /*!<Filter Active bit 23 */
-#define  CAN_FA1R_FACT24                      0x01000000U        /*!<Filter Active bit 24 */
-#define  CAN_FA1R_FACT25                      0x02000000U        /*!<Filter Active bit 25 */
-#define  CAN_FA1R_FACT26                      0x04000000U        /*!<Filter Active bit 26 */
-#define  CAN_FA1R_FACT27                      0x08000000U        /*!<Filter Active bit 27 */
-
-/*******************  Bit definition for CAN_F0R1 register  *******************/
-#define  CAN_F0R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F0R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F0R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F0R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F0R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F0R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F0R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F0R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F0R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F0R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F0R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F0R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F0R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F0R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F0R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F0R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F0R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F0R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F0R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F0R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F0R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F0R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F0R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F0R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F0R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F0R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F0R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F0R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F0R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F0R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F0R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F0R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R1 register  *******************/
-#define  CAN_F1R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F1R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F1R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F1R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F1R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F1R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F1R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F1R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F1R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F1R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F1R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F1R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F1R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F1R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F1R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F1R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F1R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F1R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F1R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F1R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F1R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F1R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F1R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F1R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F1R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F1R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F1R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F1R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F1R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F1R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F1R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F1R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R1 register  *******************/
-#define  CAN_F2R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F2R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F2R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F2R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F2R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F2R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F2R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F2R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F2R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F2R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F2R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F2R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F2R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F2R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F2R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F2R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F2R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F2R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F2R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F2R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F2R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F2R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F2R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F2R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F2R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F2R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F2R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F2R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F2R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F2R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F2R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F2R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R1 register  *******************/
-#define  CAN_F3R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F3R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F3R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F3R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F3R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F3R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F3R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F3R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F3R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F3R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F3R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F3R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F3R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F3R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F3R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F3R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F3R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F3R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F3R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F3R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F3R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F3R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F3R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F3R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F3R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F3R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F3R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F3R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F3R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F3R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F3R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F3R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R1 register  *******************/
-#define  CAN_F4R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F4R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F4R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F4R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F4R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F4R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F4R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F4R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F4R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F4R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F4R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F4R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F4R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F4R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F4R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F4R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F4R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F4R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F4R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F4R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F4R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F4R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F4R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F4R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F4R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F4R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F4R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F4R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F4R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F4R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F4R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F4R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R1 register  *******************/
-#define  CAN_F5R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F5R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F5R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F5R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F5R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F5R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F5R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F5R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F5R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F5R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F5R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F5R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F5R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F5R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F5R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F5R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F5R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F5R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F5R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F5R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F5R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F5R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F5R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F5R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F5R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F5R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F5R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F5R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F5R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F5R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F5R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F5R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R1 register  *******************/
-#define  CAN_F6R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F6R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F6R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F6R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F6R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F6R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F6R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F6R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F6R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F6R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F6R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F6R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F6R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F6R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F6R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F6R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F6R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F6R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F6R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F6R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F6R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F6R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F6R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F6R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F6R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F6R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F6R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F6R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F6R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F6R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F6R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F6R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R1 register  *******************/
-#define  CAN_F7R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F7R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F7R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F7R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F7R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F7R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F7R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F7R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F7R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F7R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F7R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F7R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F7R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F7R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F7R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F7R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F7R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F7R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F7R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F7R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F7R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F7R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F7R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F7R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F7R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F7R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F7R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F7R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F7R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F7R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F7R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F7R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R1 register  *******************/
-#define  CAN_F8R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F8R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F8R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F8R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F8R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F8R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F8R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F8R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F8R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F8R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F8R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F8R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F8R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F8R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F8R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F8R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F8R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F8R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F8R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F8R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F8R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F8R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F8R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F8R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F8R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F8R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F8R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F8R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F8R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F8R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F8R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F8R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R1 register  *******************/
-#define  CAN_F9R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F9R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F9R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F9R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F9R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F9R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F9R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F9R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F9R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F9R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F9R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F9R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F9R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F9R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F9R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F9R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F9R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F9R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F9R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F9R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F9R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F9R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F9R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F9R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F9R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F9R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F9R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F9R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F9R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F9R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F9R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F9R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R1 register  ******************/
-#define  CAN_F10R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F10R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F10R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F10R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F10R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F10R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F10R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F10R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F10R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F10R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F10R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F10R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F10R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F10R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F10R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F10R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F10R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F10R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F10R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F10R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F10R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F10R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F10R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F10R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F10R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F10R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F10R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F10R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F10R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F10R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F10R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F10R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R1 register  ******************/
-#define  CAN_F11R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F11R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F11R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F11R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F11R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F11R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F11R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F11R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F11R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F11R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F11R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F11R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F11R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F11R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F11R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F11R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F11R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F11R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F11R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F11R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F11R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F11R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F11R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F11R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F11R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F11R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F11R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F11R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F11R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F11R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F11R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F11R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R1 register  ******************/
-#define  CAN_F12R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F12R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F12R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F12R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F12R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F12R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F12R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F12R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F12R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F12R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F12R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F12R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F12R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F12R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F12R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F12R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F12R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F12R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F12R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F12R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F12R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F12R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F12R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F12R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F12R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F12R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F12R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F12R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F12R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F12R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F12R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F12R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R1 register  ******************/
-#define  CAN_F13R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F13R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F13R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F13R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F13R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F13R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F13R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F13R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F13R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F13R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F13R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F13R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F13R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F13R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F13R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F13R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F13R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F13R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F13R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F13R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F13R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F13R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F13R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F13R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F13R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F13R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F13R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F13R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F13R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F13R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F13R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F13R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F0R2 register  *******************/
-#define  CAN_F0R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F0R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F0R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F0R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F0R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F0R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F0R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F0R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F0R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F0R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F0R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F0R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F0R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F0R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F0R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F0R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F0R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F0R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F0R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F0R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F0R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F0R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F0R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F0R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F0R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F0R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F0R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F0R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F0R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F0R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F0R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F0R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R2 register  *******************/
-#define  CAN_F1R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F1R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F1R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F1R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F1R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F1R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F1R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F1R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F1R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F1R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F1R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F1R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F1R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F1R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F1R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F1R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F1R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F1R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F1R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F1R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F1R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F1R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F1R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F1R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F1R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F1R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F1R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F1R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F1R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F1R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F1R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F1R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R2 register  *******************/
-#define  CAN_F2R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F2R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F2R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F2R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F2R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F2R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F2R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F2R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F2R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F2R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F2R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F2R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F2R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F2R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F2R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F2R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F2R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F2R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F2R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F2R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F2R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F2R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F2R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F2R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F2R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F2R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F2R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F2R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F2R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F2R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F2R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F2R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R2 register  *******************/
-#define  CAN_F3R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F3R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F3R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F3R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F3R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F3R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F3R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F3R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F3R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F3R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F3R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F3R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F3R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F3R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F3R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F3R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F3R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F3R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F3R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F3R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F3R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F3R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F3R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F3R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F3R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F3R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F3R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F3R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F3R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F3R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F3R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F3R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R2 register  *******************/
-#define  CAN_F4R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F4R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F4R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F4R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F4R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F4R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F4R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F4R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F4R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F4R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F4R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F4R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F4R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F4R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F4R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F4R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F4R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F4R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F4R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F4R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F4R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F4R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F4R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F4R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F4R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F4R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F4R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F4R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F4R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F4R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F4R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F4R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R2 register  *******************/
-#define  CAN_F5R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F5R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F5R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F5R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F5R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F5R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F5R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F5R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F5R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F5R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F5R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F5R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F5R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F5R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F5R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F5R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F5R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F5R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F5R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F5R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F5R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F5R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F5R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F5R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F5R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F5R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F5R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F5R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F5R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F5R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F5R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F5R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R2 register  *******************/
-#define  CAN_F6R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F6R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F6R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F6R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F6R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F6R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F6R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F6R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F6R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F6R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F6R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F6R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F6R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F6R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F6R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F6R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F6R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F6R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F6R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F6R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F6R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F6R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F6R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F6R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F6R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F6R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F6R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F6R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F6R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F6R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F6R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F6R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R2 register  *******************/
-#define  CAN_F7R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F7R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F7R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F7R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F7R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F7R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F7R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F7R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F7R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F7R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F7R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F7R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F7R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F7R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F7R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F7R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F7R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F7R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F7R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F7R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F7R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F7R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F7R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F7R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F7R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F7R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F7R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F7R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F7R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F7R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F7R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F7R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R2 register  *******************/
-#define  CAN_F8R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F8R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F8R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F8R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F8R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F8R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F8R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F8R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F8R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F8R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F8R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F8R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F8R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F8R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F8R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F8R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F8R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F8R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F8R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F8R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F8R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F8R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F8R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F8R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F8R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F8R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F8R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F8R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F8R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F8R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F8R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F8R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R2 register  *******************/
-#define  CAN_F9R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F9R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F9R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F9R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F9R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F9R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F9R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F9R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F9R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F9R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F9R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F9R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F9R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F9R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F9R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F9R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F9R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F9R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F9R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F9R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F9R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F9R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F9R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F9R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F9R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F9R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F9R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F9R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F9R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F9R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F9R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F9R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R2 register  ******************/
-#define  CAN_F10R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F10R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F10R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F10R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F10R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F10R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F10R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F10R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F10R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F10R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F10R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F10R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F10R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F10R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F10R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F10R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F10R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F10R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F10R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F10R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F10R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F10R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F10R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F10R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F10R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F10R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F10R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F10R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F10R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F10R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F10R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F10R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R2 register  ******************/
-#define  CAN_F11R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F11R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F11R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F11R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F11R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F11R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F11R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F11R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F11R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F11R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F11R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F11R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F11R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F11R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F11R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F11R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F11R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F11R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F11R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F11R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F11R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F11R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F11R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F11R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F11R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F11R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F11R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F11R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F11R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F11R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F11R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F11R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R2 register  ******************/
-#define  CAN_F12R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F12R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F12R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F12R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F12R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F12R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F12R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F12R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F12R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F12R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F12R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F12R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F12R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F12R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F12R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F12R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F12R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F12R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F12R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F12R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F12R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F12R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F12R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F12R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F12R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F12R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F12R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F12R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F12R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F12R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F12R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F12R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R2 register  ******************/
-#define  CAN_F13R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F13R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F13R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F13R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F13R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F13R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F13R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F13R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F13R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F13R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F13R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F13R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F13R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F13R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F13R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F13R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F13R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F13R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F13R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F13R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F13R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F13R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F13R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F13R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F13R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F13R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F13R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F13R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F13R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F13R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F13R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F13R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRC calculation unit                              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           0xFFFFFFFFU /*!< Data register bits */
-
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         0xFFU        /*!< General-purpose 8-bit data register bits */
-
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        0x01U        /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 Debug MCU                                  */
-/*                                                                            */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                 Digital Filter for Sigma Delta Modulators                  */
-/*                                                                            */
-/******************************************************************************/
-
-/****************   DFSDM channel configuration registers  ********************/
-
-/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/
-#define  DFSDM_CHCFGR1_DFSDMEN                0x80000000U            /*!< Global enable for DFSDM interface */
-#define  DFSDM_CHCFGR1_CKOUTSRC               0x40000000U            /*!< Output serial clock source selection */
-#define  DFSDM_CHCFGR1_CKOUTDIV               0x00FF0000U            /*!< CKOUTDIV[7:0] output serial clock divider */
-#define  DFSDM_CHCFGR1_DATPACK                0x0000C000U            /*!< DATPACK[1:0] Data packing mode */
-#define  DFSDM_CHCFGR1_DATPACK_1              0x00008000U            /*!< Data packing mode, Bit 1 */
-#define  DFSDM_CHCFGR1_DATPACK_0              0x00004000U            /*!< Data packing mode, Bit 0 */
-#define  DFSDM_CHCFGR1_DATMPX                 0x00003000U            /*!< DATMPX[1:0] Input data multiplexer for channel y */
-#define  DFSDM_CHCFGR1_DATMPX_1               0x00002000U            /*!< Input data multiplexer for channel y, Bit 1 */
-#define  DFSDM_CHCFGR1_DATMPX_0               0x00001000U            /*!< Input data multiplexer for channel y, Bit 0 */
-#define  DFSDM_CHCFGR1_CHINSEL                0x00000100U            /*!< Serial inputs selection for channel y */
-#define  DFSDM_CHCFGR1_CHEN                   0x00000080U            /*!< Channel y enable */
-#define  DFSDM_CHCFGR1_CKABEN                 0x00000040U            /*!< Clock absence detector enable on channel y */
-#define  DFSDM_CHCFGR1_SCDEN                  0x00000020U            /*!< Short circuit detector enable on channel y */
-#define  DFSDM_CHCFGR1_SPICKSEL               0x0000000CU            /*!< SPICKSEL[1:0] SPI clock select for channel y */
-#define  DFSDM_CHCFGR1_SPICKSEL_1             0x00000008U            /*!< SPI clock select for channel y, Bit 1 */
-#define  DFSDM_CHCFGR1_SPICKSEL_0             0x00000004U            /*!< SPI clock select for channel y, Bit 0 */
-#define  DFSDM_CHCFGR1_SITP                   0x00000003U            /*!< SITP[1:0] Serial interface type for channel y */
-#define  DFSDM_CHCFGR1_SITP_1                 0x00000002U            /*!< Serial interface type for channel y, Bit 1 */
-#define  DFSDM_CHCFGR1_SITP_0                 0x00000001U            /*!< Serial interface type for channel y, Bit 0 */
-
-/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/
-#define  DFSDM_CHCFGR2_OFFSET                 0xFFFFFF00U            /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
-#define  DFSDM_CHCFGR2_DTRBS                  0x000000F8U            /*!< DTRBS[4:0] Data right bit-shift for channel y */
-
-/****************  Bit definition for DFSDM_CHAWSCDR register *****************/
-#define  DFSDM_CHAWSCDR_AWFORD                0x00C00000U            /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
-#define  DFSDM_CHAWSCDR_AWFORD_1              0x00800000U            /*!< Analog watchdog Sinc filter order on channel y, Bit 1 */
-#define  DFSDM_CHAWSCDR_AWFORD_0              0x00400000U            /*!< Analog watchdog Sinc filter order on channel y, Bit 0 */
-#define  DFSDM_CHAWSCDR_AWFOSR                0x001F0000U            /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
-#define  DFSDM_CHAWSCDR_BKSCD                 0x0000F000U            /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
-#define  DFSDM_CHAWSCDR_SCDT                  0x000000FFU            /*!< SCDT[7:0] Short circuit detector threshold for channel y */
-
-/****************  Bit definition for DFSDM_CHWDATR register *******************/
-#define  DFSDM_CHWDATR_WDATA                  0x0000FFFFU            /*!< WDATA[15:0] Input channel y watchdog data */
-
-/****************  Bit definition for DFSDM_CHDATINR register *****************/
-#define  DFSDM_CHDATINR_INDAT0                0x0000FFFFU            /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
-#define  DFSDM_CHDATINR_INDAT1                0xFFFF0000U            /*!< INDAT0[15:0] Input data for channel y */
-
-/************************   DFSDM module registers  ****************************/
-
-/*****************  Bit definition for DFSDM_FLTCR1 register *******************/
-#define  DFSDM_FLTCR1_AWFSEL                  0x40000000U            /*!< Analog watchdog fast mode select */
-#define  DFSDM_FLTCR1_FAST                    0x20000000U            /*!< Fast conversion mode selection */
-#define  DFSDM_FLTCR1_RCH                     0x07000000U            /*!< RCH[2:0] Regular channel selection */
-#define  DFSDM_FLTCR1_RDMAEN                  0x00200000U            /*!< DMA channel enabled to read data for the regular conversion */
-#define  DFSDM_FLTCR1_RSYNC                   0x00080000U            /*!< Launch regular conversion synchronously with DFSDMx */
-#define  DFSDM_FLTCR1_RCONT                   0x00040000U            /*!< Continuous mode selection for regular conversions */
-#define  DFSDM_FLTCR1_RSWSTART                0x00020000U            /*!< Software start of a conversion on the regular channel */
-#define  DFSDM_FLTCR1_JEXTEN                  0x00006000U            /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
-#define  DFSDM_FLTCR1_JEXTEN_1                0x00004000U            /*!< Trigger enable and trigger edge selection for injected conversions, Bit 1 */
-#define  DFSDM_FLTCR1_JEXTEN_0                0x00002000U            /*!< Trigger enable and trigger edge selection for injected conversions, Bit 0 */
-#define  DFSDM_FLTCR1_JEXTSEL                 0x00000700U            /*!< JEXTSEL[2:0]Trigger signal selection for launching injected conversions */
-#define  DFSDM_FLTCR1_JEXTSEL_2               0x00000400U            /*!< Trigger signal selection for launching injected conversions, Bit 2 */
-#define  DFSDM_FLTCR1_JEXTSEL_1               0x00000200U            /*!< Trigger signal selection for launching injected conversions, Bit 1 */
-#define  DFSDM_FLTCR1_JEXTSEL_0               0x00000100U            /*!< Trigger signal selection for launching injected conversions, Bit 0 */
-#define  DFSDM_FLTCR1_JDMAEN                  0x00000020U            /*!< DMA channel enabled to read data for the injected channel group */
-#define  DFSDM_FLTCR1_JSCAN                   0x00000010U            /*!< Scanning conversion in continuous mode selection for injected conversions */
-#define  DFSDM_FLTCR1_JSYNC                   0x00000008U            /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */
-#define  DFSDM_FLTCR1_JSWSTART                0x00000002U            /*!< Start the conversion of the injected group of channels */
-#define  DFSDM_FLTCR1_DFEN                    0x00000001U            /*!< DFSDM enable */
-
-/*****************  Bit definition for DFSDM_FLTCR2 register *******************/
-#define  DFSDM_FLTCR2_AWDCH                   0x000F0000U            /*!< AWDCH[7:0] Analog watchdog channel selection */
-#define  DFSDM_FLTCR2_EXCH                    0x00000F00U            /*!< EXCH[7:0] Extreme detector channel selection */
-#define  DFSDM_FLTCR2_CKABIE                  0x00000040U            /*!< Clock absence interrupt enable */
-#define  DFSDM_FLTCR2_SCDIE                   0x00000020U            /*!< Short circuit detector interrupt enable */
-#define  DFSDM_FLTCR2_AWDIE                   0x00000010U            /*!< Analog watchdog interrupt enable */
-#define  DFSDM_FLTCR2_ROVRIE                  0x00000008U            /*!< Regular data overrun interrupt enable */
-#define  DFSDM_FLTCR2_JOVRIE                  0x00000004U            /*!< Injected data overrun interrupt enable */
-#define  DFSDM_FLTCR2_REOCIE                  0x00000002U            /*!< Regular end of conversion interrupt enable */
-#define  DFSDM_FLTCR2_JEOCIE                  0x00000001U            /*!< Injected end of conversion interrupt enable */
-
-/*****************  Bit definition for DFSDM_FLTISR register *******************/
-#define  DFSDM_FLTISR_SCDF                    0x0F000000U            /*!< SCDF[7:0] Short circuit detector flag */
-#define  DFSDM_FLTISR_CKABF                   0x000F0000U            /*!< CKABF[7:0] Clock absence flag */
-#define  DFSDM_FLTISR_RCIP                    0x00004000U            /*!< Regular conversion in progress status */
-#define  DFSDM_FLTISR_JCIP                    0x00002000U            /*!< Injected conversion in progress status */
-#define  DFSDM_FLTISR_AWDF                    0x00000010U            /*!< Analog watchdog */
-#define  DFSDM_FLTISR_ROVRF                   0x00000008U            /*!< Regular conversion overrun flag */
-#define  DFSDM_FLTISR_JOVRF                   0x00000004U            /*!< Injected conversion overrun flag */
-#define  DFSDM_FLTISR_REOCF                   0x00000002U            /*!< End of regular conversion flag */
-#define  DFSDM_FLTISR_JEOCF                   0x00000001U            /*!< End of injected conversion flag */
-
-/*****************  Bit definition for DFSDM_FLTICR register *******************/
-#define  DFSDM_FLTICR_CLRSCSDF                0x0F000000U            /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
-#define  DFSDM_FLTICR_CLRCKABF                0x000F0000U            /*!< CLRCKABF[7:0] Clear the clock absence flag */
-#define  DFSDM_FLTICR_CLRROVRF                0x00000008U            /*!< Clear the regular conversion overrun flag */
-#define  DFSDM_FLTICR_CLRJOVRF                0x00000004U            /*!< Clear the injected conversion overrun flag */
-
-/****************  Bit definition for DFSDM_FLTJCHGR register ******************/
-#define  DFSDM_FLTJCHGR_JCHG                  0x0000000FU            /*!< JCHG[7:0] Injected channel group selection */
-
-/*****************  Bit definition for DFSDM_FLTFCR register *******************/
-#define  DFSDM_FLTFCR_FORD                    0xE0000000U            /*!< FORD[2:0] Sinc filter order */
-#define  DFSDM_FLTFCR_FORD_2                  0x80000000U            /*!< Sinc filter order, Bit 2 */
-#define  DFSDM_FLTFCR_FORD_1                  0x40000000U            /*!< Sinc filter order, Bit 1 */
-#define  DFSDM_FLTFCR_FORD_0                  0x20000000U            /*!< Sinc filter order, Bit 0 */
-#define  DFSDM_FLTFCR_FOSR                    0x03FF0000U            /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
-#define  DFSDM_FLTFCR_IOSR                    0x000000FFU            /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
-
-/***************  Bit definition for DFSDM_FLTJDATAR register *****************/
-#define  DFSDM_FLTJDATAR_JDATA                0xFFFFFF00U            /*!< JDATA[23:0] Injected group conversion data */
-#define  DFSDM_FLTJDATAR_JDATACH              0x00000007U            /*!< JDATACH[2:0] Injected channel most recently converted */
-
-/***************  Bit definition for DFSDM_FLTRDATAR register *****************/
-#define  DFSDM_FLTRDATAR_RDATA                0xFFFFFF00U            /*!< RDATA[23:0] Regular channel conversion data */
-#define  DFSDM_FLTRDATAR_RPEND                0x00000010U            /*!< RPEND Regular channel pending data */
-#define  DFSDM_FLTRDATAR_RDATACH              0x00000007U            /*!< RDATACH[2:0] Regular channel most recently converted */
-
-/***************  Bit definition for DFSDM_FLTAWHTR register ******************/
-#define  DFSDM_FLTAWHTR_AWHT                 0xFFFFFF00U             /*!< AWHT[23:0] Analog watchdog high threshold */
-#define  DFSDM_FLTAWHTR_BKAWH                0x0000000FU             /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
-
-/***************  Bit definition for DFSDM_FLTAWLTR register ******************/
-#define  DFSDM_FLTAWLTR_AWLT                 0xFFFFFF00U             /*!< AWLT[23:0] Analog watchdog low threshold */
-#define  DFSDM_FLTAWLTR_BKAWL                0x0000000FU             /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
-
-/***************  Bit definition for DFSDM_FLTAWSR register *******************/
-#define  DFSDM_FLTAWSR_AWHTF                 0x00000F00U             /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
-#define  DFSDM_FLTAWSR_AWLTF                 0x0000000FU             /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
-
-/***************  Bit definition for DFSDM_FLTAWCFR register ******************/
-#define  DFSDM_FLTAWCFR_CLRAWHTF             0x00000F00U             /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
-#define  DFSDM_FLTAWCFR_CLRAWLTF             0x0000000FU             /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
-
-/***************  Bit definition for DFSDM_FLTEXMAX register ******************/
-#define  DFSDM_FLTEXMAX_EXMAX                0xFFFFFF00U             /*!< EXMAX[23:0] Extreme detector maximum value */
-#define  DFSDM_FLTEXMAX_EXMAXCH              0x00000007U             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
-
-/***************  Bit definition for DFSDM_FLTEXMIN register ******************/
-#define  DFSDM_FLTEXMIN_EXMIN                0xFFFFFF00U             /*!< EXMIN[23:0] Extreme detector minimum value */
-#define  DFSDM_FLTEXMIN_EXMINCH              0x00000007U             /*!< EXMINCH[2:0] Extreme detector minimum data channel */
-
-/***************  Bit definition for DFSDM_FLTCNVTIMR register ****************/
-#define  DFSDM_FLTCNVTIMR_CNVCNT             0xFFFFFFF0U             /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
-
-/******************************************************************************/
-/*                                                                            */
-/*                             DMA Controller                                 */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DMA_SxCR register  *****************/
-#define DMA_SxCR_CHSEL                       0x0E000000U
-#define DMA_SxCR_CHSEL_0                     0x02000000U
-#define DMA_SxCR_CHSEL_1                     0x04000000U
-#define DMA_SxCR_CHSEL_2                     0x08000000U
-#define DMA_SxCR_MBURST                      0x01800000U
-#define DMA_SxCR_MBURST_0                    0x00800000U
-#define DMA_SxCR_MBURST_1                    0x01000000U
-#define DMA_SxCR_PBURST                      0x00600000U
-#define DMA_SxCR_PBURST_0                    0x00200000U
-#define DMA_SxCR_PBURST_1                    0x00400000U
-#define DMA_SxCR_CT                          0x00080000U
-#define DMA_SxCR_DBM                         0x00040000U
-#define DMA_SxCR_PL                          0x00030000U
-#define DMA_SxCR_PL_0                        0x00010000U
-#define DMA_SxCR_PL_1                        0x00020000U
-#define DMA_SxCR_PINCOS                      0x00008000U
-#define DMA_SxCR_MSIZE                       0x00006000U
-#define DMA_SxCR_MSIZE_0                     0x00002000U
-#define DMA_SxCR_MSIZE_1                     0x00004000U
-#define DMA_SxCR_PSIZE                       0x00001800U
-#define DMA_SxCR_PSIZE_0                     0x00000800U
-#define DMA_SxCR_PSIZE_1                     0x00001000U
-#define DMA_SxCR_MINC                        0x00000400U
-#define DMA_SxCR_PINC                        0x00000200U
-#define DMA_SxCR_CIRC                        0x00000100U
-#define DMA_SxCR_DIR                         0x000000C0U
-#define DMA_SxCR_DIR_0                       0x00000040U
-#define DMA_SxCR_DIR_1                       0x00000080U
-#define DMA_SxCR_PFCTRL                      0x00000020U
-#define DMA_SxCR_TCIE                        0x00000010U
-#define DMA_SxCR_HTIE                        0x00000008U
-#define DMA_SxCR_TEIE                        0x00000004U
-#define DMA_SxCR_DMEIE                       0x00000002U
-#define DMA_SxCR_EN                          0x00000001U
-
-/* Legacy defines */
-#define DMA_SxCR_ACK                         0x00100000U
-
-/********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            0x0000FFFFU
-#define DMA_SxNDT_0                          0x00000001U
-#define DMA_SxNDT_1                          0x00000002U
-#define DMA_SxNDT_2                          0x00000004U
-#define DMA_SxNDT_3                          0x00000008U
-#define DMA_SxNDT_4                          0x00000010U
-#define DMA_SxNDT_5                          0x00000020U
-#define DMA_SxNDT_6                          0x00000040U
-#define DMA_SxNDT_7                          0x00000080U
-#define DMA_SxNDT_8                          0x00000100U
-#define DMA_SxNDT_9                          0x00000200U
-#define DMA_SxNDT_10                         0x00000400U
-#define DMA_SxNDT_11                         0x00000800U
-#define DMA_SxNDT_12                         0x00001000U
-#define DMA_SxNDT_13                         0x00002000U
-#define DMA_SxNDT_14                         0x00004000U
-#define DMA_SxNDT_15                         0x00008000U
-
-/********************  Bits definition for DMA_SxFCR register  ****************/ 
-#define DMA_SxFCR_FEIE                       0x00000080U
-#define DMA_SxFCR_FS                         0x00000038U
-#define DMA_SxFCR_FS_0                       0x00000008U
-#define DMA_SxFCR_FS_1                       0x00000010U
-#define DMA_SxFCR_FS_2                       0x00000020U
-#define DMA_SxFCR_DMDIS                      0x00000004U
-#define DMA_SxFCR_FTH                        0x00000003U
-#define DMA_SxFCR_FTH_0                      0x00000001U
-#define DMA_SxFCR_FTH_1                      0x00000002U
-
-/********************  Bits definition for DMA_LISR register  *****************/ 
-#define DMA_LISR_TCIF3                       0x08000000U
-#define DMA_LISR_HTIF3                       0x04000000U
-#define DMA_LISR_TEIF3                       0x02000000U
-#define DMA_LISR_DMEIF3                      0x01000000U
-#define DMA_LISR_FEIF3                       0x00400000U
-#define DMA_LISR_TCIF2                       0x00200000U
-#define DMA_LISR_HTIF2                       0x00100000U
-#define DMA_LISR_TEIF2                       0x00080000U
-#define DMA_LISR_DMEIF2                      0x00040000U
-#define DMA_LISR_FEIF2                       0x00010000U
-#define DMA_LISR_TCIF1                       0x00000800U
-#define DMA_LISR_HTIF1                       0x00000400U
-#define DMA_LISR_TEIF1                       0x00000200U
-#define DMA_LISR_DMEIF1                      0x00000100U
-#define DMA_LISR_FEIF1                       0x00000040U
-#define DMA_LISR_TCIF0                       0x00000020U
-#define DMA_LISR_HTIF0                       0x00000010U
-#define DMA_LISR_TEIF0                       0x00000008U
-#define DMA_LISR_DMEIF0                      0x00000004U
-#define DMA_LISR_FEIF0                       0x00000001U
-
-/********************  Bits definition for DMA_HISR register  *****************/ 
-#define DMA_HISR_TCIF7                       0x08000000U
-#define DMA_HISR_HTIF7                       0x04000000U
-#define DMA_HISR_TEIF7                       0x02000000U
-#define DMA_HISR_DMEIF7                      0x01000000U
-#define DMA_HISR_FEIF7                       0x00400000U
-#define DMA_HISR_TCIF6                       0x00200000U
-#define DMA_HISR_HTIF6                       0x00100000U
-#define DMA_HISR_TEIF6                       0x00080000U
-#define DMA_HISR_DMEIF6                      0x00040000U
-#define DMA_HISR_FEIF6                       0x00010000U
-#define DMA_HISR_TCIF5                       0x00000800U
-#define DMA_HISR_HTIF5                       0x00000400U
-#define DMA_HISR_TEIF5                       0x00000200U
-#define DMA_HISR_DMEIF5                      0x00000100U
-#define DMA_HISR_FEIF5                       0x00000040U
-#define DMA_HISR_TCIF4                       0x00000020U
-#define DMA_HISR_HTIF4                       0x00000010U
-#define DMA_HISR_TEIF4                       0x00000008U
-#define DMA_HISR_DMEIF4                      0x00000004U
-#define DMA_HISR_FEIF4                       0x00000001U
-
-/********************  Bits definition for DMA_LIFCR register  ****************/ 
-#define DMA_LIFCR_CTCIF3                     0x08000000U
-#define DMA_LIFCR_CHTIF3                     0x04000000U
-#define DMA_LIFCR_CTEIF3                     0x02000000U
-#define DMA_LIFCR_CDMEIF3                    0x01000000U
-#define DMA_LIFCR_CFEIF3                     0x00400000U
-#define DMA_LIFCR_CTCIF2                     0x00200000U
-#define DMA_LIFCR_CHTIF2                     0x00100000U
-#define DMA_LIFCR_CTEIF2                     0x00080000U
-#define DMA_LIFCR_CDMEIF2                    0x00040000U
-#define DMA_LIFCR_CFEIF2                     0x00010000U
-#define DMA_LIFCR_CTCIF1                     0x00000800U
-#define DMA_LIFCR_CHTIF1                     0x00000400U
-#define DMA_LIFCR_CTEIF1                     0x00000200U
-#define DMA_LIFCR_CDMEIF1                    0x00000100U
-#define DMA_LIFCR_CFEIF1                     0x00000040U
-#define DMA_LIFCR_CTCIF0                     0x00000020U
-#define DMA_LIFCR_CHTIF0                     0x00000010U
-#define DMA_LIFCR_CTEIF0                     0x00000008U
-#define DMA_LIFCR_CDMEIF0                    0x00000004U
-#define DMA_LIFCR_CFEIF0                     0x00000001U
-
-/********************  Bits definition for DMA_HIFCR  register  ****************/ 
-#define DMA_HIFCR_CTCIF7                     0x08000000U
-#define DMA_HIFCR_CHTIF7                     0x04000000U
-#define DMA_HIFCR_CTEIF7                     0x02000000U
-#define DMA_HIFCR_CDMEIF7                    0x01000000U
-#define DMA_HIFCR_CFEIF7                     0x00400000U
-#define DMA_HIFCR_CTCIF6                     0x00200000U
-#define DMA_HIFCR_CHTIF6                     0x00100000U
-#define DMA_HIFCR_CTEIF6                     0x00080000U
-#define DMA_HIFCR_CDMEIF6                    0x00040000U
-#define DMA_HIFCR_CFEIF6                     0x00010000U
-#define DMA_HIFCR_CTCIF5                     0x00000800U
-#define DMA_HIFCR_CHTIF5                     0x00000400U
-#define DMA_HIFCR_CTEIF5                     0x00000200U
-#define DMA_HIFCR_CDMEIF5                    0x00000100U
-#define DMA_HIFCR_CFEIF5                     0x00000040U
-#define DMA_HIFCR_CTCIF4                     0x00000020U
-#define DMA_HIFCR_CHTIF4                     0x00000010U
-#define DMA_HIFCR_CTEIF4                     0x00000008U
-#define DMA_HIFCR_CDMEIF4                    0x00000004U
-#define DMA_HIFCR_CFEIF4                     0x00000001U
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                    External Interrupt/Event Controller                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    FLASH                                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    0x0000000FU
-#define FLASH_ACR_LATENCY_0WS                0x00000000U
-#define FLASH_ACR_LATENCY_1WS                0x00000001U
-#define FLASH_ACR_LATENCY_2WS                0x00000002U
-#define FLASH_ACR_LATENCY_3WS                0x00000003U
-#define FLASH_ACR_LATENCY_4WS                0x00000004U
-#define FLASH_ACR_LATENCY_5WS                0x00000005U
-#define FLASH_ACR_LATENCY_6WS                0x00000006U
-#define FLASH_ACR_LATENCY_7WS                0x00000007U
-
-#define FLASH_ACR_PRFTEN                     0x00000100U
-#define FLASH_ACR_ICEN                       0x00000200U
-#define FLASH_ACR_DCEN                       0x00000400U
-#define FLASH_ACR_ICRST                      0x00000800U
-#define FLASH_ACR_DCRST                      0x00001000U
-#define FLASH_ACR_BYTE0_ADDRESS              0x40023C00U
-#define FLASH_ACR_BYTE2_ADDRESS              0x40023C03U
-
-/*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         0x00000001U
-#define FLASH_SR_SOP                         0x00000002U
-#define FLASH_SR_WRPERR                      0x00000010U
-#define FLASH_SR_PGAERR                      0x00000020U
-#define FLASH_SR_PGPERR                      0x00000040U
-#define FLASH_SR_PGSERR                      0x00000080U
-#define FLASH_SR_BSY                         0x00010000U
-
-/*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          0x00000001U
-#define FLASH_CR_SER                         0x00000002U
-#define FLASH_CR_MER                         0x00000004U
-#define FLASH_CR_SNB                         0x000000F8U
-#define FLASH_CR_SNB_0                       0x00000008U
-#define FLASH_CR_SNB_1                       0x00000010U
-#define FLASH_CR_SNB_2                       0x00000020U
-#define FLASH_CR_SNB_3                       0x00000040U
-#define FLASH_CR_SNB_4                       0x00000080U
-#define FLASH_CR_PSIZE                       0x00000300U
-#define FLASH_CR_PSIZE_0                     0x00000100U
-#define FLASH_CR_PSIZE_1                     0x00000200U
-#define FLASH_CR_STRT                        0x00010000U
-#define FLASH_CR_EOPIE                       0x01000000U
-#define FLASH_CR_LOCK                        0x80000000U
-
-/*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                 0x00000001U
-#define FLASH_OPTCR_OPTSTRT                 0x00000002U
-#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
-#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
-#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
-
-#define FLASH_OPTCR_WDG_SW                  0x00000020U
-#define FLASH_OPTCR_nRST_STOP               0x00000040U
-#define FLASH_OPTCR_nRST_STDBY              0x00000080U
-#define FLASH_OPTCR_RDP                     0x0000FF00U
-#define FLASH_OPTCR_RDP_0                   0x00000100U
-#define FLASH_OPTCR_RDP_1                   0x00000200U
-#define FLASH_OPTCR_RDP_2                   0x00000400U
-#define FLASH_OPTCR_RDP_3                   0x00000800U
-#define FLASH_OPTCR_RDP_4                   0x00001000U
-#define FLASH_OPTCR_RDP_5                   0x00002000U
-#define FLASH_OPTCR_RDP_6                   0x00004000U
-#define FLASH_OPTCR_RDP_7                   0x00008000U
-#define FLASH_OPTCR_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR_nWRP_0                  0x00010000U
-#define FLASH_OPTCR_nWRP_1                  0x00020000U
-#define FLASH_OPTCR_nWRP_2                  0x00040000U
-#define FLASH_OPTCR_nWRP_3                  0x00080000U
-#define FLASH_OPTCR_nWRP_4                  0x00100000U
-#define FLASH_OPTCR_nWRP_5                  0x00200000U
-#define FLASH_OPTCR_nWRP_6                  0x00400000U
-#define FLASH_OPTCR_nWRP_7                  0x00800000U
-#define FLASH_OPTCR_nWRP_8                  0x01000000U
-#define FLASH_OPTCR_nWRP_9                  0x02000000U
-#define FLASH_OPTCR_nWRP_10                 0x04000000U
-#define FLASH_OPTCR_nWRP_11                 0x08000000U
-                                             
-/******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR1_nWRP_0                  0x00010000U
-#define FLASH_OPTCR1_nWRP_1                  0x00020000U
-#define FLASH_OPTCR1_nWRP_2                  0x00040000U
-#define FLASH_OPTCR1_nWRP_3                  0x00080000U
-#define FLASH_OPTCR1_nWRP_4                  0x00100000U
-#define FLASH_OPTCR1_nWRP_5                  0x00200000U
-#define FLASH_OPTCR1_nWRP_6                  0x00400000U
-#define FLASH_OPTCR1_nWRP_7                  0x00800000U
-#define FLASH_OPTCR1_nWRP_8                  0x01000000U
-#define FLASH_OPTCR1_nWRP_9                  0x02000000U
-#define FLASH_OPTCR1_nWRP_10                 0x04000000U
-#define FLASH_OPTCR1_nWRP_11                 0x08000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Flexible Static Memory Controller                        */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for FSMC_BCR1 register  *******************/
-#define  FSMC_BCR1_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FSMC_BCR1_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FSMC_BCR1_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FSMC_BCR1_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FSMC_BCR1_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FSMC_BCR1_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR1_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FSMC_BCR1_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FSMC_BCR1_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FSMC_BCR1_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FSMC_BCR1_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FSMC_BCR1_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FSMC_BCR1_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FSMC_BCR1_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FSMC_BCR1_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FSMC_BCR1_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FSMC_BCR1_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FSMC_BCR1_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FSMC_BCR1_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FSMC_BCR1_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FSMC_BCR1_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-#define  FSMC_BCR1_CCLKEN                    0x00100000U        /*!<Continous clock enable     */
-#define  FSMC_BCR1_WFDIS                     0x00200000U        /*!<Write FIFO Disable         */
-
-/******************  Bit definition for FSMC_BCR2 register  *******************/
-#define  FSMC_BCR2_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FSMC_BCR2_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FSMC_BCR2_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FSMC_BCR2_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FSMC_BCR2_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FSMC_BCR2_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR2_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FSMC_BCR2_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FSMC_BCR2_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FSMC_BCR2_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FSMC_BCR2_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FSMC_BCR2_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FSMC_BCR2_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FSMC_BCR2_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FSMC_BCR2_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FSMC_BCR2_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FSMC_BCR2_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FSMC_BCR2_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FSMC_BCR2_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FSMC_BCR2_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FSMC_BCR2_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FSMC_BCR3 register  *******************/
-#define  FSMC_BCR3_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FSMC_BCR3_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FSMC_BCR3_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FSMC_BCR3_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FSMC_BCR3_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FSMC_BCR3_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR3_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FSMC_BCR3_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FSMC_BCR3_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FSMC_BCR3_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FSMC_BCR3_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FSMC_BCR3_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FSMC_BCR3_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FSMC_BCR3_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FSMC_BCR3_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FSMC_BCR3_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FSMC_BCR3_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FSMC_BCR3_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FSMC_BCR3_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FSMC_BCR3_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FSMC_BCR3_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FSMC_BCR4 register  *******************/
-#define  FSMC_BCR4_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FSMC_BCR4_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FSMC_BCR4_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FSMC_BCR4_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FSMC_BCR4_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FSMC_BCR4_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR4_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FSMC_BCR4_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FSMC_BCR4_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FSMC_BCR4_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FSMC_BCR4_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FSMC_BCR4_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FSMC_BCR4_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FSMC_BCR4_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FSMC_BCR4_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FSMC_BCR4_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FSMC_BCR4_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FSMC_BCR4_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FSMC_BCR4_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FSMC_BCR4_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FSMC_BCR4_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FSMC_BTR1 register  ******************/
-#define  FSMC_BTR1_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR1_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FSMC_BTR1_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FSMC_BTR1_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FSMC_BTR1_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BTR1_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
-#define  FSMC_BTR1_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FSMC_BTR1_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FSMC_BTR1_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FSMC_BTR1_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BTR1_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BTR1_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FSMC_BTR1_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FSMC_BTR1_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FSMC_BTR1_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FSMC_BTR1_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FSMC_BTR1_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FSMC_BTR1_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FSMC_BTR1_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BTR1_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR1_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FSMC_BTR1_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FSMC_BTR1_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FSMC_BTR1_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BTR1_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR1_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FSMC_BTR1_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FSMC_BTR1_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FSMC_BTR1_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FSMC_BTR1_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR1_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FSMC_BTR1_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FSMC_BTR1_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FSMC_BTR1_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FSMC_BTR1_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR1_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FSMC_BTR1_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BTR2 register  *******************/
-#define  FSMC_BTR2_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR2_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FSMC_BTR2_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FSMC_BTR2_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FSMC_BTR2_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BTR2_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR2_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FSMC_BTR2_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FSMC_BTR2_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FSMC_BTR2_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BTR2_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BTR2_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FSMC_BTR2_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FSMC_BTR2_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FSMC_BTR2_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FSMC_BTR2_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FSMC_BTR2_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FSMC_BTR2_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FSMC_BTR2_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BTR2_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR2_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FSMC_BTR2_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FSMC_BTR2_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FSMC_BTR2_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BTR2_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR2_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FSMC_BTR2_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FSMC_BTR2_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FSMC_BTR2_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FSMC_BTR2_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR2_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FSMC_BTR2_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FSMC_BTR2_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FSMC_BTR2_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FSMC_BTR2_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR2_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FSMC_BTR2_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/*******************  Bit definition for FSMC_BTR3 register  *******************/
-#define  FSMC_BTR3_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR3_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FSMC_BTR3_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FSMC_BTR3_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FSMC_BTR3_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BTR3_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR3_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FSMC_BTR3_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FSMC_BTR3_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FSMC_BTR3_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BTR3_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BTR3_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FSMC_BTR3_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FSMC_BTR3_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FSMC_BTR3_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FSMC_BTR3_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FSMC_BTR3_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FSMC_BTR3_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FSMC_BTR3_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BTR3_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR3_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FSMC_BTR3_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FSMC_BTR3_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FSMC_BTR3_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BTR3_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR3_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FSMC_BTR3_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FSMC_BTR3_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FSMC_BTR3_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FSMC_BTR3_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR3_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FSMC_BTR3_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FSMC_BTR3_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FSMC_BTR3_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FSMC_BTR3_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR3_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FSMC_BTR3_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BTR4 register  *******************/
-#define  FSMC_BTR4_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR4_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FSMC_BTR4_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FSMC_BTR4_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FSMC_BTR4_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BTR4_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR4_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FSMC_BTR4_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FSMC_BTR4_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FSMC_BTR4_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BTR4_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BTR4_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FSMC_BTR4_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FSMC_BTR4_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FSMC_BTR4_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FSMC_BTR4_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FSMC_BTR4_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FSMC_BTR4_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FSMC_BTR4_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BTR4_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR4_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FSMC_BTR4_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FSMC_BTR4_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FSMC_BTR4_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BTR4_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR4_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FSMC_BTR4_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FSMC_BTR4_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FSMC_BTR4_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FSMC_BTR4_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR4_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FSMC_BTR4_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FSMC_BTR4_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FSMC_BTR4_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FSMC_BTR4_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR4_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FSMC_BTR4_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR1 register  ******************/
-#define  FSMC_BWTR1_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR1_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FSMC_BWTR1_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FSMC_BWTR1_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FSMC_BWTR1_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BWTR1_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR1_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FSMC_BWTR1_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FSMC_BWTR1_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FSMC_BWTR1_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BWTR1_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BWTR1_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FSMC_BWTR1_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FSMC_BWTR1_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FSMC_BWTR1_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FSMC_BWTR1_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FSMC_BWTR1_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FSMC_BWTR1_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FSMC_BWTR1_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BWTR1_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FSMC_BWTR1_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FSMC_BWTR1_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FSMC_BWTR1_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FSMC_BWTR1_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BWTR1_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR1_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FSMC_BWTR1_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR2 register  ******************/
-#define  FSMC_BWTR2_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR2_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FSMC_BWTR2_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FSMC_BWTR2_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FSMC_BWTR2_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BWTR2_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR2_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FSMC_BWTR2_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FSMC_BWTR2_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FSMC_BWTR2_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BWTR2_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BWTR2_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FSMC_BWTR2_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FSMC_BWTR2_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FSMC_BWTR2_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FSMC_BWTR2_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FSMC_BWTR2_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FSMC_BWTR2_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FSMC_BWTR2_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BWTR2_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FSMC_BWTR2_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FSMC_BWTR2_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FSMC_BWTR2_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FSMC_BWTR2_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BWTR2_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR2_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FSMC_BWTR2_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR3 register  ******************/
-#define  FSMC_BWTR3_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR3_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FSMC_BWTR3_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FSMC_BWTR3_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FSMC_BWTR3_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BWTR3_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR3_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FSMC_BWTR3_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FSMC_BWTR3_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FSMC_BWTR3_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BWTR3_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BWTR3_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FSMC_BWTR3_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FSMC_BWTR3_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FSMC_BWTR3_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FSMC_BWTR3_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FSMC_BWTR3_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FSMC_BWTR3_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FSMC_BWTR3_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BWTR3_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FSMC_BWTR3_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FSMC_BWTR3_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FSMC_BWTR3_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FSMC_BWTR3_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BWTR3_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR3_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FSMC_BWTR3_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR4 register  ******************/
-#define  FSMC_BWTR4_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR4_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FSMC_BWTR4_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FSMC_BWTR4_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FSMC_BWTR4_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BWTR4_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR4_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FSMC_BWTR4_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FSMC_BWTR4_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FSMC_BWTR4_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BWTR4_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BWTR4_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FSMC_BWTR4_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FSMC_BWTR4_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FSMC_BWTR4_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FSMC_BWTR4_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FSMC_BWTR4_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FSMC_BWTR4_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FSMC_BWTR4_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BWTR4_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FSMC_BWTR4_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FSMC_BWTR4_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FSMC_BWTR4_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FSMC_BWTR4_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BWTR4_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR4_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FSMC_BWTR4_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    0x00000003U
-#define GPIO_MODER_MODER0_0                  0x00000001U
-#define GPIO_MODER_MODER0_1                  0x00000002U
-
-#define GPIO_MODER_MODER1                    0x0000000CU
-#define GPIO_MODER_MODER1_0                  0x00000004U
-#define GPIO_MODER_MODER1_1                  0x00000008U
-
-#define GPIO_MODER_MODER2                    0x00000030U
-#define GPIO_MODER_MODER2_0                  0x00000010U
-#define GPIO_MODER_MODER2_1                  0x00000020U
-
-#define GPIO_MODER_MODER3                    0x000000C0U
-#define GPIO_MODER_MODER3_0                  0x00000040U
-#define GPIO_MODER_MODER3_1                  0x00000080U
-
-#define GPIO_MODER_MODER4                    0x00000300U
-#define GPIO_MODER_MODER4_0                  0x00000100U
-#define GPIO_MODER_MODER4_1                  0x00000200U
-
-#define GPIO_MODER_MODER5                    0x00000C00U
-#define GPIO_MODER_MODER5_0                  0x00000400U
-#define GPIO_MODER_MODER5_1                  0x00000800U
-
-#define GPIO_MODER_MODER6                    0x00003000U
-#define GPIO_MODER_MODER6_0                  0x00001000U
-#define GPIO_MODER_MODER6_1                  0x00002000U
-
-#define GPIO_MODER_MODER7                    0x0000C000U
-#define GPIO_MODER_MODER7_0                  0x00004000U
-#define GPIO_MODER_MODER7_1                  0x00008000U
-
-#define GPIO_MODER_MODER8                    0x00030000U
-#define GPIO_MODER_MODER8_0                  0x00010000U
-#define GPIO_MODER_MODER8_1                  0x00020000U
-
-#define GPIO_MODER_MODER9                    0x000C0000U
-#define GPIO_MODER_MODER9_0                  0x00040000U
-#define GPIO_MODER_MODER9_1                  0x00080000U
-
-#define GPIO_MODER_MODER10                   0x00300000U
-#define GPIO_MODER_MODER10_0                 0x00100000U
-#define GPIO_MODER_MODER10_1                 0x00200000U
-
-#define GPIO_MODER_MODER11                   0x00C00000U
-#define GPIO_MODER_MODER11_0                 0x00400000U
-#define GPIO_MODER_MODER11_1                 0x00800000U
-
-#define GPIO_MODER_MODER12                   0x03000000U
-#define GPIO_MODER_MODER12_0                 0x01000000U
-#define GPIO_MODER_MODER12_1                 0x02000000U
-
-#define GPIO_MODER_MODER13                   0x0C000000U
-#define GPIO_MODER_MODER13_0                 0x04000000U
-#define GPIO_MODER_MODER13_1                 0x08000000U
-
-#define GPIO_MODER_MODER14                   0x30000000U
-#define GPIO_MODER_MODER14_0                 0x10000000U
-#define GPIO_MODER_MODER14_1                 0x20000000U
-
-#define GPIO_MODER_MODER15                   0xC0000000U
-#define GPIO_MODER_MODER15_0                 0x40000000U
-#define GPIO_MODER_MODER15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     0x00000001U
-#define GPIO_OTYPER_OT_1                     0x00000002U
-#define GPIO_OTYPER_OT_2                     0x00000004U
-#define GPIO_OTYPER_OT_3                     0x00000008U
-#define GPIO_OTYPER_OT_4                     0x00000010U
-#define GPIO_OTYPER_OT_5                     0x00000020U
-#define GPIO_OTYPER_OT_6                     0x00000040U
-#define GPIO_OTYPER_OT_7                     0x00000080U
-#define GPIO_OTYPER_OT_8                     0x00000100U
-#define GPIO_OTYPER_OT_9                     0x00000200U
-#define GPIO_OTYPER_OT_10                    0x00000400U
-#define GPIO_OTYPER_OT_11                    0x00000800U
-#define GPIO_OTYPER_OT_12                    0x00001000U
-#define GPIO_OTYPER_OT_13                    0x00002000U
-#define GPIO_OTYPER_OT_14                    0x00004000U
-#define GPIO_OTYPER_OT_15                    0x00008000U
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
-#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
-#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
-
-#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
-#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
-#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
-
-#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
-#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
-#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
-
-#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
-#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
-#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
-
-#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
-#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
-#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
-
-#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
-#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
-#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
-
-#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
-#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
-#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
-
-#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
-#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
-#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
-
-#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
-#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
-#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
-
-#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
-#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
-#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
-
-#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
-#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
-#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
-
-#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
-#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
-#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
-
-#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
-#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
-#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
-
-#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
-#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
-#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
-
-#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
-#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
-#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
-
-#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
-#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
-#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    0x00000003U
-#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
-#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
-
-#define GPIO_PUPDR_PUPDR1                    0x0000000CU
-#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
-#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
-
-#define GPIO_PUPDR_PUPDR2                    0x00000030U
-#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
-#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
-
-#define GPIO_PUPDR_PUPDR3                    0x000000C0U
-#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
-#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
-
-#define GPIO_PUPDR_PUPDR4                    0x00000300U
-#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
-#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
-
-#define GPIO_PUPDR_PUPDR5                    0x00000C00U
-#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
-#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
-
-#define GPIO_PUPDR_PUPDR6                    0x00003000U
-#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
-#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
-
-#define GPIO_PUPDR_PUPDR7                    0x0000C000U
-#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
-#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
-
-#define GPIO_PUPDR_PUPDR8                    0x00030000U
-#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
-#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
-
-#define GPIO_PUPDR_PUPDR9                    0x000C0000U
-#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
-#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
-
-#define GPIO_PUPDR_PUPDR10                   0x00300000U
-#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
-#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
-
-#define GPIO_PUPDR_PUPDR11                   0x00C00000U
-#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
-#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
-
-#define GPIO_PUPDR_PUPDR12                   0x03000000U
-#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
-#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
-
-#define GPIO_PUPDR_PUPDR13                   0x0C000000U
-#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
-#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
-
-#define GPIO_PUPDR_PUPDR14                   0x30000000U
-#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
-#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
-
-#define GPIO_PUPDR_PUPDR15                   0xC0000000U
-#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
-#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       0x00000001U
-#define GPIO_IDR_IDR_1                       0x00000002U
-#define GPIO_IDR_IDR_2                       0x00000004U
-#define GPIO_IDR_IDR_3                       0x00000008U
-#define GPIO_IDR_IDR_4                       0x00000010U
-#define GPIO_IDR_IDR_5                       0x00000020U
-#define GPIO_IDR_IDR_6                       0x00000040U
-#define GPIO_IDR_IDR_7                       0x00000080U
-#define GPIO_IDR_IDR_8                       0x00000100U
-#define GPIO_IDR_IDR_9                       0x00000200U
-#define GPIO_IDR_IDR_10                      0x00000400U
-#define GPIO_IDR_IDR_11                      0x00000800U
-#define GPIO_IDR_IDR_12                      0x00001000U
-#define GPIO_IDR_IDR_13                      0x00002000U
-#define GPIO_IDR_IDR_14                      0x00004000U
-#define GPIO_IDR_IDR_15                      0x00008000U
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       0x00000001U
-#define GPIO_ODR_ODR_1                       0x00000002U
-#define GPIO_ODR_ODR_2                       0x00000004U
-#define GPIO_ODR_ODR_3                       0x00000008U
-#define GPIO_ODR_ODR_4                       0x00000010U
-#define GPIO_ODR_ODR_5                       0x00000020U
-#define GPIO_ODR_ODR_6                       0x00000040U
-#define GPIO_ODR_ODR_7                       0x00000080U
-#define GPIO_ODR_ODR_8                       0x00000100U
-#define GPIO_ODR_ODR_9                       0x00000200U
-#define GPIO_ODR_ODR_10                      0x00000400U
-#define GPIO_ODR_ODR_11                      0x00000800U
-#define GPIO_ODR_ODR_12                      0x00001000U
-#define GPIO_ODR_ODR_13                      0x00002000U
-#define GPIO_ODR_ODR_14                      0x00004000U
-#define GPIO_ODR_ODR_15                      0x00008000U
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       0x00000001U
-#define GPIO_BSRR_BS_1                       0x00000002U
-#define GPIO_BSRR_BS_2                       0x00000004U
-#define GPIO_BSRR_BS_3                       0x00000008U
-#define GPIO_BSRR_BS_4                       0x00000010U
-#define GPIO_BSRR_BS_5                       0x00000020U
-#define GPIO_BSRR_BS_6                       0x00000040U
-#define GPIO_BSRR_BS_7                       0x00000080U
-#define GPIO_BSRR_BS_8                       0x00000100U
-#define GPIO_BSRR_BS_9                       0x00000200U
-#define GPIO_BSRR_BS_10                      0x00000400U
-#define GPIO_BSRR_BS_11                      0x00000800U
-#define GPIO_BSRR_BS_12                      0x00001000U
-#define GPIO_BSRR_BS_13                      0x00002000U
-#define GPIO_BSRR_BS_14                      0x00004000U
-#define GPIO_BSRR_BS_15                      0x00008000U
-#define GPIO_BSRR_BR_0                       0x00010000U
-#define GPIO_BSRR_BR_1                       0x00020000U
-#define GPIO_BSRR_BR_2                       0x00040000U
-#define GPIO_BSRR_BR_3                       0x00080000U
-#define GPIO_BSRR_BR_4                       0x00100000U
-#define GPIO_BSRR_BR_5                       0x00200000U
-#define GPIO_BSRR_BR_6                       0x00400000U
-#define GPIO_BSRR_BR_7                       0x00800000U
-#define GPIO_BSRR_BR_8                       0x01000000U
-#define GPIO_BSRR_BR_9                       0x02000000U
-#define GPIO_BSRR_BR_10                      0x04000000U
-#define GPIO_BSRR_BR_11                      0x08000000U
-#define GPIO_BSRR_BR_12                      0x10000000U
-#define GPIO_BSRR_BR_13                      0x20000000U
-#define GPIO_BSRR_BR_14                      0x40000000U
-#define GPIO_BSRR_BR_15                      0x80000000U
-
-/****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0                       0x00000001U
-#define GPIO_LCKR_LCK1                       0x00000002U
-#define GPIO_LCKR_LCK2                       0x00000004U
-#define GPIO_LCKR_LCK3                       0x00000008U
-#define GPIO_LCKR_LCK4                       0x00000010U
-#define GPIO_LCKR_LCK5                       0x00000020U
-#define GPIO_LCKR_LCK6                       0x00000040U
-#define GPIO_LCKR_LCK7                       0x00000080U
-#define GPIO_LCKR_LCK8                       0x00000100U
-#define GPIO_LCKR_LCK9                       0x00000200U
-#define GPIO_LCKR_LCK10                      0x00000400U
-#define GPIO_LCKR_LCK11                      0x00000800U
-#define GPIO_LCKR_LCK12                      0x00001000U
-#define GPIO_LCKR_LCK13                      0x00002000U
-#define GPIO_LCKR_LCK14                      0x00004000U
-#define GPIO_LCKR_LCK15                      0x00008000U
-#define GPIO_LCKR_LCKK                       0x00010000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Inter-integrated Circuit Interface                    */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          0x00000001U     /*!<Peripheral Enable                             */
-#define  I2C_CR1_SMBUS                       0x00000002U     /*!<SMBus Mode                                    */
-#define  I2C_CR1_SMBTYPE                     0x00000008U     /*!<SMBus Type                                    */
-#define  I2C_CR1_ENARP                       0x00000010U     /*!<ARP Enable                                    */
-#define  I2C_CR1_ENPEC                       0x00000020U     /*!<PEC Enable                                    */
-#define  I2C_CR1_ENGC                        0x00000040U     /*!<General Call Enable                           */
-#define  I2C_CR1_NOSTRETCH                   0x00000080U     /*!<Clock Stretching Disable (Slave mode)  */
-#define  I2C_CR1_START                       0x00000100U     /*!<Start Generation                              */
-#define  I2C_CR1_STOP                        0x00000200U     /*!<Stop Generation                               */
-#define  I2C_CR1_ACK                         0x00000400U     /*!<Acknowledge Enable                            */
-#define  I2C_CR1_POS                         0x00000800U     /*!<Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         0x00001000U     /*!<Packet Error Checking                         */
-#define  I2C_CR1_ALERT                       0x00002000U     /*!<SMBus Alert                                   */
-#define  I2C_CR1_SWRST                       0x00008000U     /*!<Software Reset                                */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        0x0000003FU     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
-#define  I2C_CR2_FREQ_0                      0x00000001U     /*!<Bit 0 */
-#define  I2C_CR2_FREQ_1                      0x00000002U     /*!<Bit 1 */
-#define  I2C_CR2_FREQ_2                      0x00000004U     /*!<Bit 2 */
-#define  I2C_CR2_FREQ_3                      0x00000008U     /*!<Bit 3 */
-#define  I2C_CR2_FREQ_4                      0x00000010U     /*!<Bit 4 */
-#define  I2C_CR2_FREQ_5                      0x00000020U     /*!<Bit 5 */
-
-#define  I2C_CR2_ITERREN                     0x00000100U     /*!<Error Interrupt Enable  */
-#define  I2C_CR2_ITEVTEN                     0x00000200U     /*!<Event Interrupt Enable  */
-#define  I2C_CR2_ITBUFEN                     0x00000400U     /*!<Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       0x00000800U     /*!<DMA Requests Enable     */
-#define  I2C_CR2_LAST                        0x00001000U     /*!<DMA Last Transfer       */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     0x000000FEU     /*!<Interface Address */
-#define  I2C_OAR1_ADD8_9                     0x00000300U     /*!<Interface Address */
-
-#define  I2C_OAR1_ADD0                       0x00000001U     /*!<Bit 0 */
-#define  I2C_OAR1_ADD1                       0x00000002U     /*!<Bit 1 */
-#define  I2C_OAR1_ADD2                       0x00000004U     /*!<Bit 2 */
-#define  I2C_OAR1_ADD3                       0x00000008U     /*!<Bit 3 */
-#define  I2C_OAR1_ADD4                       0x00000010U     /*!<Bit 4 */
-#define  I2C_OAR1_ADD5                       0x00000020U     /*!<Bit 5 */
-#define  I2C_OAR1_ADD6                       0x00000040U     /*!<Bit 6 */
-#define  I2C_OAR1_ADD7                       0x00000080U     /*!<Bit 7 */
-#define  I2C_OAR1_ADD8                       0x00000100U     /*!<Bit 8 */
-#define  I2C_OAR1_ADD9                       0x00000200U     /*!<Bit 9 */
-
-#define  I2C_OAR1_ADDMODE                    0x00008000U     /*!<Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     0x00000001U        /*!<Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       0x000000FEU        /*!<Interface address           */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           0x000000FFU        /*!<8-bit Data Register         */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          0x00000001U     /*!<Start Bit (Master mode)                  */
-#define  I2C_SR1_ADDR                        0x00000002U     /*!<Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         0x00000004U     /*!<Byte Transfer Finished                          */
-#define  I2C_SR1_ADD10                       0x00000008U     /*!<10-bit header sent (Master mode)         */
-#define  I2C_SR1_STOPF                       0x00000010U     /*!<Stop detection (Slave mode)              */
-#define  I2C_SR1_RXNE                        0x00000040U     /*!<Data Register not Empty (receivers)      */
-#define  I2C_SR1_TXE                         0x00000080U     /*!<Data Register Empty (transmitters)       */
-#define  I2C_SR1_BERR                        0x00000100U     /*!<Bus Error                                       */
-#define  I2C_SR1_ARLO                        0x00000200U     /*!<Arbitration Lost (master mode)           */
-#define  I2C_SR1_AF                          0x00000400U     /*!<Acknowledge Failure                             */
-#define  I2C_SR1_OVR                         0x00000800U     /*!<Overrun/Underrun                                */
-#define  I2C_SR1_PECERR                      0x00001000U     /*!<PEC Error in reception                          */
-#define  I2C_SR1_TIMEOUT                     0x00004000U     /*!<Timeout or Tlow Error                           */
-#define  I2C_SR1_SMBALERT                    0x00008000U     /*!<SMBus Alert                                     */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         0x00000001U     /*!<Master/Slave                              */
-#define  I2C_SR2_BUSY                        0x00000002U     /*!<Bus Busy                                  */
-#define  I2C_SR2_TRA                         0x00000004U     /*!<Transmitter/Receiver                      */
-#define  I2C_SR2_GENCALL                     0x00000010U     /*!<General Call Address (Slave mode)  */
-#define  I2C_SR2_SMBDEFAULT                  0x00000020U     /*!<SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     0x00000040U     /*!<SMBus Host Header (Slave mode)     */
-#define  I2C_SR2_DUALF                       0x00000080U     /*!<Dual Flag (Slave mode)             */
-#define  I2C_SR2_PEC                         0x0000FF00U     /*!<Packet Error Checking Register            */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         0x00000FFFU     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        0x00004000U     /*!<Fast Mode Duty Cycle                                       */
-#define  I2C_CCR_FS                          0x00008000U     /*!<I2C Master Mode Selection                                  */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     0x0000003FU     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************  Bit definition for I2C_FLTR register  *******************/
-#define  I2C_FLTR_DNF                        0x0000000FU     /*!<Digital Noise Filter */
-#define  I2C_FLTR_ANOFF                      0x00000010U     /*!<Analog Noise Filter OFF */
-
-/******************************************************************************/
-/*                                                                            */
-/*        Fast Mode Plus Inter-integrated Circuit Interface (I2C)             */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define  FMPI2C_CR1_PE                        0x00000001U        /*!< Peripheral enable                   */
-#define  FMPI2C_CR1_TXIE                      0x00000002U        /*!< TX interrupt enable                 */
-#define  FMPI2C_CR1_RXIE                      0x00000004U        /*!< RX interrupt enable                 */
-#define  FMPI2C_CR1_ADDRIE                    0x00000008U        /*!< Address match interrupt enable      */
-#define  FMPI2C_CR1_NACKIE                    0x00000010U        /*!< NACK received interrupt enable      */
-#define  FMPI2C_CR1_STOPIE                    0x00000020U        /*!< STOP detection interrupt enable     */
-#define  FMPI2C_CR1_TCIE                      0x00000040U        /*!< Transfer complete interrupt enable  */
-#define  FMPI2C_CR1_ERRIE                     0x00000080U        /*!< Errors interrupt enable             */
-#define  FMPI2C_CR1_DFN                       0x00000F00U        /*!< Digital noise filter                */
-#define  FMPI2C_CR1_ANFOFF                    0x00001000U        /*!< Analog noise filter OFF             */
-#define  FMPI2C_CR1_TXDMAEN                   0x00004000U        /*!< DMA transmission requests enable    */
-#define  FMPI2C_CR1_RXDMAEN                   0x00008000U        /*!< DMA reception requests enable       */
-#define  FMPI2C_CR1_SBC                       0x00010000U        /*!< Slave byte control                  */
-#define  FMPI2C_CR1_NOSTRETCH                 0x00020000U        /*!< Clock stretching disable            */
-#define  FMPI2C_CR1_GCEN                      0x00080000U        /*!< General call enable                 */
-#define  FMPI2C_CR1_SMBHEN                    0x00100000U        /*!< SMBus host address enable           */
-#define  FMPI2C_CR1_SMBDEN                    0x00200000U        /*!< SMBus device default address enable */
-#define  FMPI2C_CR1_ALERTEN                   0x00400000U        /*!< SMBus alert enable                  */
-#define  FMPI2C_CR1_PECEN                     0x00800000U        /*!< PEC enable                          */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define  FMPI2C_CR2_SADD                      0x000003FFU        /*!< Slave address (master mode)                             */
-#define  FMPI2C_CR2_RD_WRN                    0x00000400U        /*!< Transfer direction (master mode)                        */
-#define  FMPI2C_CR2_ADD10                     0x00000800U        /*!< 10-bit addressing mode (master mode)                    */
-#define  FMPI2C_CR2_HEAD10R                   0x00001000U        /*!< 10-bit address header only read direction (master mode) */
-#define  FMPI2C_CR2_START                     0x00002000U        /*!< START generation                                        */
-#define  FMPI2C_CR2_STOP                      0x00004000U        /*!< STOP generation (master mode)                           */
-#define  FMPI2C_CR2_NACK                      0x00008000U        /*!< NACK generation (slave mode)                            */
-#define  FMPI2C_CR2_NBYTES                    0x00FF0000U        /*!< Number of bytes                                         */
-#define  FMPI2C_CR2_RELOAD                    0x01000000U        /*!< NBYTES reload mode                                      */
-#define  FMPI2C_CR2_AUTOEND                   0x02000000U        /*!< Automatic end mode (master mode)                        */
-#define  FMPI2C_CR2_PECBYTE                   0x04000000U        /*!< Packet error checking byte                              */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define  FMPI2C_OAR1_OA1                      0x000003FFU        /*!< Interface own address 1   */
-#define  FMPI2C_OAR1_OA1MODE                  0x00000400U        /*!< Own address 1 10-bit mode */
-#define  FMPI2C_OAR1_OA1EN                    0x00008000U        /*!< Own address 1 enable      */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define  FMPI2C_OAR2_OA2                      0x000000FEU        /*!< Interface own address 2 */
-#define  FMPI2C_OAR2_OA2MSK                   0x00000700U        /*!< Own address 2 masks     */
-#define  FMPI2C_OAR2_OA2EN                    0x00008000U        /*!< Own address 2 enable    */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define  FMPI2C_TIMINGR_SCLL                  0x000000FFU        /*!< SCL low period (master mode)  */
-#define  FMPI2C_TIMINGR_SCLH                  0x0000FF00U        /*!< SCL high period (master mode) */
-#define  FMPI2C_TIMINGR_SDADEL                0x000F0000U        /*!< Data hold time                */
-#define  FMPI2C_TIMINGR_SCLDEL                0x00F00000U        /*!< Data setup time               */
-#define  FMPI2C_TIMINGR_PRESC                 0xF0000000U        /*!< Timings prescaler             */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define  FMPI2C_TIMEOUTR_TIMEOUTA             0x00000FFFU        /*!< Bus timeout A                 */
-#define  FMPI2C_TIMEOUTR_TIDLE                0x00001000U        /*!< Idle clock timeout detection  */
-#define  FMPI2C_TIMEOUTR_TIMOUTEN             0x00008000U        /*!< Clock timeout enable          */
-#define  FMPI2C_TIMEOUTR_TIMEOUTB             0x0FFF0000U        /*!< Bus timeout B                 */
-#define  FMPI2C_TIMEOUTR_TEXTEN               0x80000000U        /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define  FMPI2C_ISR_TXE                       0x00000001U        /*!< Transmit data register empty     */
-#define  FMPI2C_ISR_TXIS                      0x00000002U        /*!< Transmit interrupt status        */
-#define  FMPI2C_ISR_RXNE                      0x00000004U        /*!< Receive data register not empty  */
-#define  FMPI2C_ISR_ADDR                      0x00000008U        /*!< Address matched (slave mode)     */
-#define  FMPI2C_ISR_NACKF                     0x00000010U        /*!< NACK received flag               */
-#define  FMPI2C_ISR_STOPF                     0x00000020U        /*!< STOP detection flag              */
-#define  FMPI2C_ISR_TC                        0x00000040U        /*!< Transfer complete (master mode)  */
-#define  FMPI2C_ISR_TCR                       0x00000080U        /*!< Transfer complete reload         */
-#define  FMPI2C_ISR_BERR                      0x00000100U        /*!< Bus error                        */
-#define  FMPI2C_ISR_ARLO                      0x00000200U        /*!< Arbitration lost                 */
-#define  FMPI2C_ISR_OVR                       0x00000400U        /*!< Overrun/Underrun                 */
-#define  FMPI2C_ISR_PECERR                    0x00000800U        /*!< PEC error in reception           */
-#define  FMPI2C_ISR_TIMEOUT                   0x00001000U        /*!< Timeout or Tlow detection flag   */
-#define  FMPI2C_ISR_ALERT                     0x00002000U        /*!< SMBus alert                      */
-#define  FMPI2C_ISR_BUSY                      0x00008000U        /*!< Bus busy                         */
-#define  FMPI2C_ISR_DIR                       0x00010000U        /*!< Transfer direction (slave mode)  */
-#define  FMPI2C_ISR_ADDCODE                   0x00FE0000U        /*!< Address match code (slave mode)  */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define  FMPI2C_ICR_ADDRCF                    0x00000008U        /*!< Address matched clear flag  */
-#define  FMPI2C_ICR_NACKCF                    0x00000010U        /*!< NACK clear flag             */
-#define  FMPI2C_ICR_STOPCF                    0x00000020U        /*!< STOP detection clear flag   */
-#define  FMPI2C_ICR_BERRCF                    0x00000100U        /*!< Bus error clear flag        */
-#define  FMPI2C_ICR_ARLOCF                    0x00000200U        /*!< Arbitration lost clear flag */
-#define  FMPI2C_ICR_OVRCF                     0x00000400U        /*!< Overrun/Underrun clear flag */
-#define  FMPI2C_ICR_PECCF                     0x00000800U        /*!< PAC error clear flag        */
-#define  FMPI2C_ICR_TIMOUTCF                  0x00001000U        /*!< Timeout clear flag          */
-#define  FMPI2C_ICR_ALERTCF                   0x00002000U        /*!< Alert clear flag            */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define  FMPI2C_PECR_PEC                      0x000000FFU        /*!< PEC register */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define  FMPI2C_RXDR_RXDATA                   0x000000FFU        /*!< 8-bit receive data */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define  FMPI2C_TXDR_TXDATA                   0x000000FFU        /*!< 8-bit transmit data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Independent WATCHDOG                             */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         0x01U               /*!<Watchdog prescaler value update      */
-#define  IWDG_SR_RVU                         0x02U               /*!<Watchdog counter reload value update */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                             Power Control                                  */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
-#define  PWR_CR_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
-#define  PWR_CR_CWUF                         0x00000004U     /*!< Clear Wakeup Flag                   */
-#define  PWR_CR_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
-#define  PWR_CR_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
-
-#define  PWR_CR_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        0x00000020U     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        0x00000040U     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        0x00000080U     /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
-
-#define  PWR_CR_DBP                          0x00000100U     /*!< Disable Backup Domain write protection                     */
-#define  PWR_CR_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                              */
-#define  PWR_CR_LPLVDS                       0x00000400U     /*!< Low Power Regulator Low Voltage in Deep Sleep mode         */
-#define  PWR_CR_MRLVDS                       0x00000800U     /*!< Main Regulator Low Voltage in Deep Sleep mode              */
-#define  PWR_CR_ADCDC1                       0x00002000U     /*!< Refer to AN4073 on how to use this bit                     */
-
-#define  PWR_CR_VOS                          0x0000C000U     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
-#define  PWR_CR_VOS_0                        0x00004000U     /*!< Bit 0 */
-#define  PWR_CR_VOS_1                        0x00008000U     /*!< Bit 1 */
-
-#define  PWR_CR_FMSSR                        0x00100000U     /*!< Flash Memory Sleep System Run        */
-#define  PWR_CR_FISSR                        0x00200000U     /*!< Flash Interface Stop while System Run */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         0x00000001U     /*!< Wakeup Flag                                      */
-#define  PWR_CSR_SBF                         0x00000002U     /*!< Standby Flag                                     */
-#define  PWR_CSR_PVDO                        0x00000004U     /*!< PVD Output                                       */
-#define  PWR_CSR_BRR                         0x00000008U     /*!< Backup regulator ready                           */
-#define  PWR_CSR_EWUP                        0x00000100U     /*!< Enable WKUP pin                                  */
-#define  PWR_CSR_BRE                         0x00000200U     /*!< Backup regulator enable                          */
-#define  PWR_CSR_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
-/******************************************************************************/
-/*                                                                            */
-/*                                    QUADSPI                                 */
-/*                                                                            */
-/******************************************************************************/
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
- */
-#define  QSPI1_V2_1L                                                      /*!< QSPI Virtual Version             */
-
-/*****************  Bit definition for QUADSPI_CR register  *******************/
-#define  QUADSPI_CR_EN                           0x00000001U            /*!< Enable                             */
-#define  QUADSPI_CR_ABORT                        0x00000002U            /*!< Abort request                      */
-#define  QUADSPI_CR_DMAEN                        0x00000004U            /*!< DMA Enable                         */
-#define  QUADSPI_CR_TCEN                         0x00000008U            /*!< Timeout Counter Enable             */
-#define  QUADSPI_CR_SSHIFT                       0x00000010U            /*!< SSHIFT Sample Shift                */
-#define  QUADSPI_CR_DFM                          0x00000040U            /*!< Dual Flash Mode                    */
-#define  QUADSPI_CR_FSEL                         0x00000080U            /*!< Flash Select                       */
-#define  QUADSPI_CR_FTHRES                       0x00001F00U            /*!< FTHRES[3:0] FIFO Level             */
-#define  QUADSPI_CR_FTHRES_0                     0x00000100U            /*!< Bit 0 */
-#define  QUADSPI_CR_FTHRES_1                     0x00000200U            /*!< Bit 1 */
-#define  QUADSPI_CR_FTHRES_2                     0x00000400U            /*!< Bit 2 */
-#define  QUADSPI_CR_FTHRES_3                     0x00000800U            /*!< Bit 3 */
-#define  QUADSPI_CR_FTHRES_4                     0x00001000U            /*!< Bit 4 */
-#define  QUADSPI_CR_TEIE                         0x00010000U            /*!< Transfer Error Interrupt Enable    */
-#define  QUADSPI_CR_TCIE                         0x00020000U            /*!< Transfer Complete Interrupt Enable */
-#define  QUADSPI_CR_FTIE                         0x00040000U            /*!< FIFO Threshold Interrupt Enable    */
-#define  QUADSPI_CR_SMIE                         0x00080000U            /*!< Status Match Interrupt Enable      */
-#define  QUADSPI_CR_TOIE                         0x00100000U            /*!< TimeOut Interrupt Enable           */
-#define  QUADSPI_CR_APMS                         0x00400000U            /*!< Bit 1 */
-#define  QUADSPI_CR_PMM                          0x00800000U            /*!< Polling Match Mode                 */
-#define  QUADSPI_CR_PRESCALER                    0xFF000000U            /*!< PRESCALER[7:0] Clock prescaler     */
-#define  QUADSPI_CR_PRESCALER_0                  0x01000000U            /*!< Bit 0 */
-#define  QUADSPI_CR_PRESCALER_1                  0x02000000U            /*!< Bit 1 */
-#define  QUADSPI_CR_PRESCALER_2                  0x04000000U            /*!< Bit 2 */
-#define  QUADSPI_CR_PRESCALER_3                  0x08000000U            /*!< Bit 3 */
-#define  QUADSPI_CR_PRESCALER_4                  0x10000000U            /*!< Bit 4 */
-#define  QUADSPI_CR_PRESCALER_5                  0x20000000U            /*!< Bit 5 */
-#define  QUADSPI_CR_PRESCALER_6                  0x40000000U            /*!< Bit 6 */
-#define  QUADSPI_CR_PRESCALER_7                  0x80000000U            /*!< Bit 7 */
-
-/*****************  Bit definition for QUADSPI_DCR register  ******************/
-#define  QUADSPI_DCR_CKMODE                      0x00000001U            /*!< Mode 0 / Mode 3                 */
-#define  QUADSPI_DCR_CSHT                        0x00000700U            /*!< CSHT[2:0]: ChipSelect High Time */
-#define  QUADSPI_DCR_CSHT_0                      0x00000100U            /*!< Bit 0 */
-#define  QUADSPI_DCR_CSHT_1                      0x00000200U            /*!< Bit 1 */
-#define  QUADSPI_DCR_CSHT_2                      0x00000400U            /*!< Bit 2 */
-#define  QUADSPI_DCR_FSIZE                       0x001F0000U            /*!< FSIZE[4:0]: Flash Size          */
-#define  QUADSPI_DCR_FSIZE_0                     0x00010000U            /*!< Bit 0 */
-#define  QUADSPI_DCR_FSIZE_1                     0x00020000U            /*!< Bit 1 */
-#define  QUADSPI_DCR_FSIZE_2                     0x00040000U            /*!< Bit 2 */
-#define  QUADSPI_DCR_FSIZE_3                     0x00080000U            /*!< Bit 3 */
-#define  QUADSPI_DCR_FSIZE_4                     0x00100000U            /*!< Bit 4 */
-
-/******************  Bit definition for QUADSPI_SR register  *******************/
-#define  QUADSPI_SR_TEF                          0x00000001U             /*!< Transfer Error Flag    */
-#define  QUADSPI_SR_TCF                          0x00000002U             /*!< Transfer Complete Flag */
-#define  QUADSPI_SR_FTF                          0x00000004U             /*!< FIFO Threshlod Flag    */
-#define  QUADSPI_SR_SMF                          0x00000008U             /*!< Status Match Flag      */
-#define  QUADSPI_SR_TOF                          0x00000010U             /*!< Timeout Flag           */
-#define  QUADSPI_SR_BUSY                         0x00000020U             /*!< Busy                   */
-#define  QUADSPI_SR_FLEVEL                       0x00003F00U             /*!< FIFO Threshlod Flag    */
-#define  QUADSPI_SR_FLEVEL_0                     0x00000100U             /*!< Bit 0 */
-#define  QUADSPI_SR_FLEVEL_1                     0x00000200U             /*!< Bit 1 */
-#define  QUADSPI_SR_FLEVEL_2                     0x00000400U             /*!< Bit 2 */
-#define  QUADSPI_SR_FLEVEL_3                     0x00000800U             /*!< Bit 3 */
-#define  QUADSPI_SR_FLEVEL_4                     0x00001000U             /*!< Bit 4 */
-#define  QUADSPI_SR_FLEVEL_5                     0x00002000U             /*!< Bit 5 */
-
-/******************  Bit definition for QUADSPI_FCR register  ******************/
-#define  QUADSPI_FCR_CTEF                        0x00000001U             /*!< Clear Transfer Error Flag    */
-#define  QUADSPI_FCR_CTCF                        0x00000002U             /*!< Clear Transfer Complete Flag */
-#define  QUADSPI_FCR_CSMF                        0x00000008U             /*!< Clear Status Match Flag      */
-#define  QUADSPI_FCR_CTOF                        0x00000010U             /*!< Clear Timeout Flag           */
-
-/******************  Bit definition for QUADSPI_DLR register  ******************/
-#define  QUADSPI_DLR_DL                        0xFFFFFFFFU               /*!< DL[31:0]: Data Length */
-
-/******************  Bit definition for QUADSPI_CCR register  ******************/
-#define  QUADSPI_CCR_INSTRUCTION                  0x000000FFU            /*!< INSTRUCTION[7:0]: Instruction */
-#define  QUADSPI_CCR_INSTRUCTION_0                0x00000001U            /*!< Bit 0 */
-#define  QUADSPI_CCR_INSTRUCTION_1                0x00000002U            /*!< Bit 1 */
-#define  QUADSPI_CCR_INSTRUCTION_2                0x00000004U            /*!< Bit 2 */
-#define  QUADSPI_CCR_INSTRUCTION_3                0x00000008U            /*!< Bit 3 */
-#define  QUADSPI_CCR_INSTRUCTION_4                0x00000010U            /*!< Bit 4 */
-#define  QUADSPI_CCR_INSTRUCTION_5                0x00000020U            /*!< Bit 5 */
-#define  QUADSPI_CCR_INSTRUCTION_6                0x00000040U            /*!< Bit 6 */
-#define  QUADSPI_CCR_INSTRUCTION_7                0x00000080U            /*!< Bit 7 */
-#define  QUADSPI_CCR_IMODE                        0x00000300U            /*!< IMODE[1:0]: Instruction Mode     */
-#define  QUADSPI_CCR_IMODE_0                      0x00000100U            /*!< Bit 0 */
-#define  QUADSPI_CCR_IMODE_1                      0x00000200U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ADMODE                       0x00000C00U            /*!< ADMODE[1:0]: Address Mode         */
-#define  QUADSPI_CCR_ADMODE_0                     0x00000400U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ADMODE_1                     0x00000800U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ADSIZE                       0x00003000U            /*!< ADSIZE[1:0]: Address Size         */
-#define  QUADSPI_CCR_ADSIZE_0                     0x00001000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ADSIZE_1                     0x00002000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ABMODE                       0x0000C000U            /*!< ABMODE[1:0]: Alternate Bytes Mode */
-#define  QUADSPI_CCR_ABMODE_0                     0x00004000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ABMODE_1                     0x00008000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ABSIZE                       0x00030000U            /*!< ABSIZE[1:0]: Instruction Mode     */
-#define  QUADSPI_CCR_ABSIZE_0                     0x00010000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ABSIZE_1                     0x00020000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_DCYC                         0x007C0000U            /*!< DCYC[4:0]: Dummy Cycles           */
-#define  QUADSPI_CCR_DCYC_0                       0x00040000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_DCYC_1                       0x00080000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_DCYC_2                       0x00100000U            /*!< Bit 2 */
-#define  QUADSPI_CCR_DCYC_3                       0x00200000U            /*!< Bit 3 */
-#define  QUADSPI_CCR_DCYC_4                       0x00400000U            /*!< Bit 4 */
-#define  QUADSPI_CCR_DMODE                        0x03000000U            /*!< DMODE[1:0]: Data Mode                */
-#define  QUADSPI_CCR_DMODE_0                      0x01000000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_DMODE_1                      0x02000000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_FMODE                        0x0C000000U            /*!< FMODE[1:0]: Functional Mode           */
-#define  QUADSPI_CCR_FMODE_0                      0x04000000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_FMODE_1                      0x08000000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_SIOO                         0x10000000U            /*!< SIOO: Send Instruction Only Once Mode */
-#define  QUADSPI_CCR_DHHC                         0x40000000U            /*!< DHHC: Delay Half Hclk Cycle           */
-#define  QUADSPI_CCR_DDRM                         0x80000000U            /*!< DDRM: Double Data Rate Mode           */ 
-/******************  Bit definition for QUADSPI_AR register  *******************/
-#define  QUADSPI_AR_ADDRESS                       0xFFFFFFFFU            /*!< ADDRESS[31:0]: Address                */
-
-/******************  Bit definition for QUADSPI_ABR register  ******************/
-#define  QUADSPI_ABR_ALTERNATE                    0xFFFFFFFFU            /*!< ALTERNATE[31:0]: Alternate Bytes      */
-
-/******************  Bit definition for QUADSPI_DR register  *******************/
-#define  QUADSPI_DR_DATA                          0xFFFFFFFFU            /*!< DATA[31:0]: Data                      */
-
-/******************  Bit definition for QUADSPI_PSMKR register  ****************/
-#define  QUADSPI_PSMKR_MASK                       0xFFFFFFFFU            /*!< MASK[31:0]: Status Mask               */
-
-/******************  Bit definition for QUADSPI_PSMAR register  ****************/
-#define  QUADSPI_PSMAR_MATCH                      0xFFFFFFFFU            /*!< MATCH[31:0]: Status Match             */
-
-/******************  Bit definition for QUADSPI_PIR register  *****************/
-#define  QUADSPI_PIR_INTERVAL                     0x0000FFFFU            /*!< INTERVAL[15:0]: Polling Interval      */
-
-/******************  Bit definition for QUADSPI_LPTR register  *****************/
-#define  QUADSPI_LPTR_TIMEOUT                     0x0000FFFFU            /*!< TIMEOUT[15:0]: Timeout period         */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        0x00000001U
-#define  RCC_CR_HSIRDY                       0x00000002U
-
-#define  RCC_CR_HSITRIM                      0x000000F8U
-#define  RCC_CR_HSITRIM_0                    0x00000008U/*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    0x00000010U/*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    0x00000020U/*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    0x00000040U/*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    0x00000080U/*!<Bit 4 */
-
-#define  RCC_CR_HSICAL                       0x0000FF00U
-#define  RCC_CR_HSICAL_0                     0x00000100U/*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     0x00000200U/*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     0x00000400U/*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     0x00000800U/*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     0x00001000U/*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     0x00002000U/*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     0x00004000U/*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     0x00008000U/*!<Bit 7 */
-
-#define  RCC_CR_HSEON                        0x00010000U
-#define  RCC_CR_HSERDY                       0x00020000U
-#define  RCC_CR_HSEBYP                       0x00040000U
-#define  RCC_CR_CSSON                        0x00080000U
-#define  RCC_CR_PLLON                        0x01000000U
-#define  RCC_CR_PLLRDY                       0x02000000U
-#define  RCC_CR_PLLI2SON                     0x04000000U
-#define  RCC_CR_PLLI2SRDY                    0x08000000U
-
-/********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    0x0000003FU
-#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
-#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
-#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
-#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
-#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
-#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
-
-#define  RCC_PLLCFGR_PLLN                     0x00007FC0U
-#define  RCC_PLLCFGR_PLLN_0                   0x00000040U
-#define  RCC_PLLCFGR_PLLN_1                   0x00000080U
-#define  RCC_PLLCFGR_PLLN_2                   0x00000100U
-#define  RCC_PLLCFGR_PLLN_3                   0x00000200U
-#define  RCC_PLLCFGR_PLLN_4                   0x00000400U
-#define  RCC_PLLCFGR_PLLN_5                   0x00000800U
-#define  RCC_PLLCFGR_PLLN_6                   0x00001000U
-#define  RCC_PLLCFGR_PLLN_7                   0x00002000U
-#define  RCC_PLLCFGR_PLLN_8                   0x00004000U
-
-#define  RCC_PLLCFGR_PLLP                    0x00030000U
-#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
-#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
-
-#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
-
-#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
-#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
-#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
-#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
-#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
-
-#define  RCC_PLLCFGR_PLLR                    0x70000000U
-#define  RCC_PLLCFGR_PLLR_0                  0x10000000U
-#define  RCC_PLLCFGR_PLLR_1                  0x20000000U
-#define  RCC_PLLCFGR_PLLR_2                  0x40000000U
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-/*!< SW configuration */
-#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
-
-#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock      */
-#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock      */
-#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL/PLLP selected as system clock */
-#define  RCC_CFGR_SW_PLLR                    0x00000003U        /*!< PLL/PLLR selected as system clock */
-
-/*!< SWS configuration */
-#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
-
-#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL/PLLP used as system clock       */
-#define  RCC_CFGR_SWS_PLLR                   0x0000000CU        /*!< PLL/PLLR used as system clock       */
-
-/*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
-
-#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
-
-/*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     0x001F0000U
-#define  RCC_CFGR_RTCPRE_0                   0x00010000U
-#define  RCC_CFGR_RTCPRE_1                   0x00020000U
-#define  RCC_CFGR_RTCPRE_2                   0x00040000U
-#define  RCC_CFGR_RTCPRE_3                   0x00080000U
-#define  RCC_CFGR_RTCPRE_4                   0x00100000U
-
-/*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       0x00600000U
-#define  RCC_CFGR_MCO1_0                     0x00200000U
-#define  RCC_CFGR_MCO1_1                     0x00400000U
-
-#define  RCC_CFGR_MCO1PRE                    0x07000000U
-#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
-#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
-#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
-
-#define  RCC_CFGR_MCO2PRE                    0x38000000U
-#define  RCC_CFGR_MCO2PRE_0                  0x08000000U
-#define  RCC_CFGR_MCO2PRE_1                  0x10000000U
-#define  RCC_CFGR_MCO2PRE_2                  0x20000000U
-
-#define  RCC_CFGR_MCO2                       0xC0000000U
-#define  RCC_CFGR_MCO2_0                     0x40000000U
-#define  RCC_CFGR_MCO2_1                     0x80000000U
-
-/********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     0x00000001U
-#define  RCC_CIR_LSERDYF                     0x00000002U
-#define  RCC_CIR_HSIRDYF                     0x00000004U
-#define  RCC_CIR_HSERDYF                     0x00000008U
-#define  RCC_CIR_PLLRDYF                     0x00000010U
-#define  RCC_CIR_PLLI2SRDYF                  0x00000020U
-
-#define  RCC_CIR_CSSF                        0x00000080U
-#define  RCC_CIR_LSIRDYIE                    0x00000100U
-#define  RCC_CIR_LSERDYIE                    0x00000200U
-#define  RCC_CIR_HSIRDYIE                    0x00000400U
-#define  RCC_CIR_HSERDYIE                    0x00000800U
-#define  RCC_CIR_PLLRDYIE                    0x00001000U
-#define  RCC_CIR_PLLI2SRDYIE                 0x00002000U
-
-#define  RCC_CIR_LSIRDYC                     0x00010000U
-#define  RCC_CIR_LSERDYC                     0x00020000U
-#define  RCC_CIR_HSIRDYC                     0x00040000U
-#define  RCC_CIR_HSERDYC                     0x00080000U
-#define  RCC_CIR_PLLRDYC                     0x00100000U
-#define  RCC_CIR_PLLI2SRDYC                  0x00200000U
-
-#define  RCC_CIR_CSSC                        0x00800000U
-
-/********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
-#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
-#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
-#define  RCC_AHB1RSTR_GPIODRST               0x00000008U
-#define  RCC_AHB1RSTR_GPIOERST               0x00000010U
-#define  RCC_AHB1RSTR_GPIOFRST               0x00000020U
-#define  RCC_AHB1RSTR_GPIOGRST               0x00000040U
-#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
-#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
-#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
-#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
-
-/********************  Bit definition for RCC_AHB2RSTR register  **************/
-#define  RCC_AHB2RSTR_RNGRST                 0x00000040U
-#define  RCC_AHB2RSTR_OTGFSRST               0x00000080U
-
-/********************  Bit definition for RCC_AHB3RSTR register  **************/
-#define  RCC_AHB3RSTR_FSMCRST                0x00000001U
-#define  RCC_AHB3RSTR_QSPIRST               0x00000002U
-
-/********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM2RST                0x00000001U
-#define  RCC_APB1RSTR_TIM3RST                0x00000002U
-#define  RCC_APB1RSTR_TIM4RST                0x00000004U
-#define  RCC_APB1RSTR_TIM5RST                0x00000008U
-#define  RCC_APB1RSTR_TIM6RST                0x00000010U
-#define  RCC_APB1RSTR_TIM7RST                0x00000020U
-#define  RCC_APB1RSTR_TIM12RST               0x00000040U
-#define  RCC_APB1RSTR_TIM13RST               0x00000080U
-#define  RCC_APB1RSTR_TIM14RST               0x00000100U
-#define  RCC_APB1RSTR_WWDGRST                0x00000800U
-#define  RCC_APB1RSTR_SPI2RST                0x00004000U
-#define  RCC_APB1RSTR_SPI3RST                0x00008000U
-#define  RCC_APB1RSTR_USART2RST              0x00020000U
-#define  RCC_APB1RSTR_USART3RST              0x00040000U
-#define  RCC_APB1RSTR_I2C1RST                0x00200000U
-#define  RCC_APB1RSTR_I2C2RST                0x00400000U
-#define  RCC_APB1RSTR_I2C3RST                0x00800000U
-#define  RCC_APB1RSTR_FMPI2C1RST             0x01000000U
-#define  RCC_APB1RSTR_CAN1RST                0x02000000U
-#define  RCC_APB1RSTR_CAN2RST                0x04000000U
-#define  RCC_APB1RSTR_PWRRST                 0x10000000U
-
-/********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                0x00000001U
-#define  RCC_APB2RSTR_TIM8RST                0x00000002U
-#define  RCC_APB2RSTR_USART1RST              0x00000010U
-#define  RCC_APB2RSTR_USART6RST              0x00000020U
-#define  RCC_APB2RSTR_ADCRST                 0x00000100U
-#define  RCC_APB2RSTR_SDIORST                0x00000800U
-#define  RCC_APB2RSTR_SPI1RST                0x00001000U
-#define  RCC_APB2RSTR_SPI4RST                0x00002000U
-#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
-#define  RCC_APB2RSTR_TIM9RST                0x00010000U
-#define  RCC_APB2RSTR_TIM10RST               0x00020000U
-#define  RCC_APB2RSTR_TIM11RST               0x00040000U
-#define  RCC_APB2RSTR_SPI5RST                0x00100000U
-#define  RCC_APB2RSTR_DFSDM1RST              0x01000000U
-
-/********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
-#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
-#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
-#define  RCC_AHB1ENR_GPIODEN                 0x00000008U
-#define  RCC_AHB1ENR_GPIOEEN                 0x00000010U
-#define  RCC_AHB1ENR_GPIOFEN                 0x00000020U
-#define  RCC_AHB1ENR_GPIOGEN                 0x00000040U
-#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
-#define  RCC_AHB1ENR_CRCEN                   0x00001000U
-#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
-#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
-
-/********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define  RCC_AHB2ENR_RNGEN                   0x00000040U
-#define  RCC_AHB2ENR_OTGFSEN                 0x00000080U
-
-/********************  Bit definition for RCC_AHB3ENR register  ***************/
-#define  RCC_AHB3ENR_FSMCEN                  0x00000001U
-#define  RCC_AHB3ENR_QSPIEN                 0x00000002U
-
-/********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM2EN                  0x00000001U
-#define  RCC_APB1ENR_TIM3EN                  0x00000002U
-#define  RCC_APB1ENR_TIM4EN                  0x00000004U
-#define  RCC_APB1ENR_TIM5EN                  0x00000008U
-#define  RCC_APB1ENR_TIM6EN                  0x00000010U
-#define  RCC_APB1ENR_TIM7EN                  0x00000020U
-#define  RCC_APB1ENR_TIM12EN                 0x00000040U
-#define  RCC_APB1ENR_TIM13EN                 0x00000080U
-#define  RCC_APB1ENR_TIM14EN                 0x00000100U
-#define  RCC_APB1ENR_RTCAPBEN                0x00000400U
-#define  RCC_APB1ENR_WWDGEN                  0x00000800U
-#define  RCC_APB1ENR_SPI2EN                  0x00004000U
-#define  RCC_APB1ENR_SPI3EN                  0x00008000U
-#define  RCC_APB1ENR_USART2EN                0x00020000U
-#define  RCC_APB1ENR_USART3EN                0x00040000U
-#define  RCC_APB1ENR_I2C1EN                  0x00200000U
-#define  RCC_APB1ENR_I2C2EN                  0x00400000U
-#define  RCC_APB1ENR_I2C3EN                  0x00800000U
-#define  RCC_APB1ENR_FMPI2C1EN               0x01000000U
-#define  RCC_APB1ENR_CAN1EN                  0x02000000U
-#define  RCC_APB1ENR_CAN2EN                  0x04000000U
-#define  RCC_APB1ENR_PWREN                   0x10000000U
-
-/********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  0x00000001U
-#define  RCC_APB2ENR_TIM8EN                  0x00000002U
-#define  RCC_APB2ENR_USART1EN                0x00000010U
-#define  RCC_APB2ENR_USART6EN                0x00000020U
-#define  RCC_APB2ENR_ADC1EN                  0x00000100U
-#define  RCC_APB2ENR_SDIOEN                  0x00000800U
-#define  RCC_APB2ENR_SPI1EN                  0x00001000U
-#define  RCC_APB2ENR_SPI4EN                  0x00002000U
-#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
-#define  RCC_APB2ENR_EXTITEN                 0x00008000U
-#define  RCC_APB2ENR_TIM9EN                  0x00010000U
-#define  RCC_APB2ENR_TIM10EN                 0x00020000U
-#define  RCC_APB2ENR_TIM11EN                 0x00040000U
-#define  RCC_APB2ENR_SPI5EN                  0x00100000U
-#define  RCC_APB2ENR_DFSDM1EN                0x01000000U
-/********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
-#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
-#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
-#define  RCC_AHB1LPENR_GPIODLPEN             0x00000008U
-#define  RCC_AHB1LPENR_GPIOELPEN             0x00000010U
-#define  RCC_AHB1LPENR_GPIOFLPEN             0x00000020U
-#define  RCC_AHB1LPENR_GPIOGLPEN             0x00000040U
-#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
-#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
-#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
-#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
-#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
-#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
-
-/********************  Bit definition for RCC_AHB2LPENR register  *************/
-#define  RCC_AHB2LPENR_RNGLPEN               0x00000040U
-#define  RCC_AHB2LPENR_OTGFSLPEN             0x00000080U
-
-/********************  Bit definition for RCC_AHB3LPENR register  *************/
-#define  RCC_AHB3LPENR_FSMCLPEN              0x00000001U
-#define  RCC_AHB3LPENR_QSPILPEN             0x00000002U
-
-/********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM2LPEN              0x00000001U
-#define  RCC_APB1LPENR_TIM3LPEN              0x00000002U
-#define  RCC_APB1LPENR_TIM4LPEN              0x00000004U
-#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
-#define  RCC_APB1LPENR_TIM6LPEN              0x00000010U
-#define  RCC_APB1LPENR_TIM7LPEN              0x00000020U
-#define  RCC_APB1LPENR_TIM12LPEN             0x00000040U
-#define  RCC_APB1LPENR_TIM13LPEN             0x00000080U
-#define  RCC_APB1LPENR_TIM14LPEN             0x00000100U
-#define  RCC_APB1LPENR_RTCAPBLPEN            0x00000400U
-#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
-#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U
-#define  RCC_APB1LPENR_SPI3LPEN              0x00008000U
-#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
-#define  RCC_APB1LPENR_USART3LPEN            0x00040000U
-#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
-#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
-#define  RCC_APB1LPENR_I2C3LPEN              0x00800000U
-#define  RCC_APB1LPENR_FMPI2C1LPEN           0x01000000U
-#define  RCC_APB1LPENR_CAN1LPEN              0x02000000U
-#define  RCC_APB1LPENR_CAN2LPEN              0x04000000U
-#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
-
-/********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
-#define  RCC_APB2LPENR_TIM8LPEN              0x00000002U
-#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
-#define  RCC_APB2LPENR_USART6LPEN            0x00000020U
-#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
-#define  RCC_APB2LPENR_SDIOLPEN              0x00000800U
-#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
-#define  RCC_APB2LPENR_SPI4LPEN              0x00002000U
-#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
-#define  RCC_APB2LPENR_EXTITLPEN             0x00008000U
-#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
-#define  RCC_APB2LPENR_TIM10LPEN             0x00020000U
-#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
-#define  RCC_APB2LPENR_SPI5LPEN              0x00100000U
-#define  RCC_APB2LPENR_DFSDM1LPEN            0x01000000U
-
-/********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      0x00000001U
-#define  RCC_BDCR_LSERDY                     0x00000002U
-#define  RCC_BDCR_LSEBYP                     0x00000004U
-#define  RCC_BDCR_LSEMOD                     0x00000008U
-
-#define  RCC_BDCR_RTCSEL                    0x00000300U
-#define  RCC_BDCR_RTCSEL_0                  0x00000100U
-#define  RCC_BDCR_RTCSEL_1                  0x00000200U
-
-#define  RCC_BDCR_RTCEN                      0x00008000U
-#define  RCC_BDCR_BDRST                      0x00010000U
-
-/********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       0x00000001U
-#define  RCC_CSR_LSIRDY                      0x00000002U
-#define  RCC_CSR_RMVF                        0x01000000U
-#define  RCC_CSR_PADRSTF                     0x04000000U
-#define  RCC_CSR_PORRSTF                     0x08000000U
-#define  RCC_CSR_SFTRSTF                     0x10000000U
-#define  RCC_CSR_WDGRSTF                     0x20000000U
-#define  RCC_CSR_WWDGRSTF                    0x40000000U
-#define  RCC_CSR_LPWRRSTF                    0x80000000U
-
-/********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    0x00001FFFU
-#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
-#define  RCC_SSCGR_SPREADSEL                 0x40000000U
-#define  RCC_SSCGR_SSCGEN                    0x80000000U
-
-/********************  Bit definition for RCC_PLLI2SCFGR register  ************/
-#define  RCC_PLLI2SCFGR_PLLI2SM              0x0000003FU
-#define  RCC_PLLI2SCFGR_PLLI2SM_0            0x00000001U
-#define  RCC_PLLI2SCFGR_PLLI2SM_1            0x00000002U
-#define  RCC_PLLI2SCFGR_PLLI2SM_2            0x00000004U
-#define  RCC_PLLI2SCFGR_PLLI2SM_3            0x00000008U
-#define  RCC_PLLI2SCFGR_PLLI2SM_4            0x00000010U
-#define  RCC_PLLI2SCFGR_PLLI2SM_5            0x00000020U
-
-#define  RCC_PLLI2SCFGR_PLLI2SN              0x00007FC0U
-#define  RCC_PLLI2SCFGR_PLLI2SN_0            0x00000040U
-#define  RCC_PLLI2SCFGR_PLLI2SN_1            0x00000080U
-#define  RCC_PLLI2SCFGR_PLLI2SN_2            0x00000100U
-#define  RCC_PLLI2SCFGR_PLLI2SN_3            0x00000200U
-#define  RCC_PLLI2SCFGR_PLLI2SN_4            0x00000400U
-#define  RCC_PLLI2SCFGR_PLLI2SN_5            0x00000800U
-#define  RCC_PLLI2SCFGR_PLLI2SN_6            0x00001000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_7            0x00002000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_8            0x00004000U
-
-#define  RCC_PLLI2SCFGR_PLLI2SSRC            0x00400000U
-
-#define  RCC_PLLI2SCFGR_PLLI2SQ              0x0F000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_0            0x01000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_1            0x02000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_2            0x04000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_3            0x08000000U
-
-#define  RCC_PLLI2SCFGR_PLLI2SR              0x70000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_0            0x10000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_1            0x20000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_2            0x40000000U
-
-/********************  Bit definition for RCC_DCKCFGR register  ****************/
-#define  RCC_DCKCFGR_CKDFSDM1ASEL            0x00008000U
-#define  RCC_DCKCFGR_TIMPRE                  0x01000000U
-
-#define  RCC_DCKCFGR_I2S1SRC                 0x06000000U
-#define  RCC_DCKCFGR_I2S1SRC_0               0x02000000U
-#define  RCC_DCKCFGR_I2S1SRC_1               0x04000000U
-
-#define  RCC_DCKCFGR_I2S2SRC                 0x18000000U
-#define  RCC_DCKCFGR_I2S2SRC_0               0x08000000U
-#define  RCC_DCKCFGR_I2S2SRC_1               0x10000000U
-
-#define  RCC_DCKCFGR_CKDFSDM1SEL             0x80000000U
-
-/********************  Bit definition for RCC_CKGATENR register  ***************/
-#define  RCC_CKGATENR_AHB2APB1_CKEN          0x00000001U
-#define  RCC_CKGATENR_AHB2APB2_CKEN          0x00000002U
-#define  RCC_CKGATENR_CM4DBG_CKEN            0x00000004U
-#define  RCC_CKGATENR_SPARE_CKEN             0x00000008U
-#define  RCC_CKGATENR_SRAM_CKEN              0x00000010U
-#define  RCC_CKGATENR_FLITF_CKEN             0x00000020U
-#define  RCC_CKGATENR_RCC_CKEN               0x00000040U
-#define  RCC_CKGATENR_RCC_EVTCTL             0x00000080U
-
-/********************  Bit definition for RCC_DCKCFGR2 register  ***************/
-#define  RCC_DCKCFGR2_FMPI2C1SEL             0x00C00000U
-#define  RCC_DCKCFGR2_FMPI2C1SEL_0           0x00400000U
-#define  RCC_DCKCFGR2_FMPI2C1SEL_1           0x00800000U
-
-#define  RCC_DCKCFGR2_CK48MSEL               0x08000000U
-#define  RCC_DCKCFGR2_SDIOSEL                0x10000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    RNG                                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN                         0x00000004U
-#define RNG_CR_IE                            0x00000008U
-
-/********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY                          0x00000001U
-#define RNG_SR_CECS                          0x00000002U
-#define RNG_SR_SECS                          0x00000004U
-#define RNG_SR_CEIS                          0x00000020U
-#define RNG_SR_SEIS                          0x00000040U
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            0x00400000U
-#define RTC_TR_HT                            0x00300000U
-#define RTC_TR_HT_0                          0x00100000U
-#define RTC_TR_HT_1                          0x00200000U
-#define RTC_TR_HU                            0x000F0000U
-#define RTC_TR_HU_0                          0x00010000U
-#define RTC_TR_HU_1                          0x00020000U
-#define RTC_TR_HU_2                          0x00040000U
-#define RTC_TR_HU_3                          0x00080000U
-#define RTC_TR_MNT                           0x00007000U
-#define RTC_TR_MNT_0                         0x00001000U
-#define RTC_TR_MNT_1                         0x00002000U
-#define RTC_TR_MNT_2                         0x00004000U
-#define RTC_TR_MNU                           0x00000F00U
-#define RTC_TR_MNU_0                         0x00000100U
-#define RTC_TR_MNU_1                         0x00000200U
-#define RTC_TR_MNU_2                         0x00000400U
-#define RTC_TR_MNU_3                         0x00000800U
-#define RTC_TR_ST                            0x00000070U
-#define RTC_TR_ST_0                          0x00000010U
-#define RTC_TR_ST_1                          0x00000020U
-#define RTC_TR_ST_2                          0x00000040U
-#define RTC_TR_SU                            0x0000000FU
-#define RTC_TR_SU_0                          0x00000001U
-#define RTC_TR_SU_1                          0x00000002U
-#define RTC_TR_SU_2                          0x00000004U
-#define RTC_TR_SU_3                          0x00000008U
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            0x00F00000U
-#define RTC_DR_YT_0                          0x00100000U
-#define RTC_DR_YT_1                          0x00200000U
-#define RTC_DR_YT_2                          0x00400000U
-#define RTC_DR_YT_3                          0x00800000U
-#define RTC_DR_YU                            0x000F0000U
-#define RTC_DR_YU_0                          0x00010000U
-#define RTC_DR_YU_1                          0x00020000U
-#define RTC_DR_YU_2                          0x00040000U
-#define RTC_DR_YU_3                          0x00080000U
-#define RTC_DR_WDU                           0x0000E000U
-#define RTC_DR_WDU_0                         0x00002000U
-#define RTC_DR_WDU_1                         0x00004000U
-#define RTC_DR_WDU_2                         0x00008000U
-#define RTC_DR_MT                            0x00001000U
-#define RTC_DR_MU                            0x00000F00U
-#define RTC_DR_MU_0                          0x00000100U
-#define RTC_DR_MU_1                          0x00000200U
-#define RTC_DR_MU_2                          0x00000400U
-#define RTC_DR_MU_3                          0x00000800U
-#define RTC_DR_DT                            0x00000030U
-#define RTC_DR_DT_0                          0x00000010U
-#define RTC_DR_DT_1                          0x00000020U
-#define RTC_DR_DU                            0x0000000FU
-#define RTC_DR_DU_0                          0x00000001U
-#define RTC_DR_DU_1                          0x00000002U
-#define RTC_DR_DU_2                          0x00000004U
-#define RTC_DR_DU_3                          0x00000008U
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           0x00800000U
-#define RTC_CR_OSEL                          0x00600000U
-#define RTC_CR_OSEL_0                        0x00200000U
-#define RTC_CR_OSEL_1                        0x00400000U
-#define RTC_CR_POL                           0x00100000U
-#define RTC_CR_COSEL                         0x00080000U
-#define RTC_CR_BCK                           0x00040000U
-#define RTC_CR_SUB1H                         0x00020000U
-#define RTC_CR_ADD1H                         0x00010000U
-#define RTC_CR_TSIE                          0x00008000U
-#define RTC_CR_WUTIE                         0x00004000U
-#define RTC_CR_ALRBIE                        0x00002000U
-#define RTC_CR_ALRAIE                        0x00001000U
-#define RTC_CR_TSE                           0x00000800U
-#define RTC_CR_WUTE                          0x00000400U
-#define RTC_CR_ALRBE                         0x00000200U
-#define RTC_CR_ALRAE                         0x00000100U
-#define RTC_CR_DCE                           0x00000080U
-#define RTC_CR_FMT                           0x00000040U
-#define RTC_CR_BYPSHAD                       0x00000020U
-#define RTC_CR_REFCKON                       0x00000010U
-#define RTC_CR_TSEDGE                        0x00000008U
-#define RTC_CR_WUCKSEL                       0x00000007U
-#define RTC_CR_WUCKSEL_0                     0x00000001U
-#define RTC_CR_WUCKSEL_1                     0x00000002U
-#define RTC_CR_WUCKSEL_2                     0x00000004U
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      0x00010000U
-#define RTC_ISR_TAMP1F                       0x00002000U
-#define RTC_ISR_TAMP2F                       0x00004000U
-#define RTC_ISR_TSOVF                        0x00001000U
-#define RTC_ISR_TSF                          0x00000800U
-#define RTC_ISR_WUTF                         0x00000400U
-#define RTC_ISR_ALRBF                        0x00000200U
-#define RTC_ISR_ALRAF                        0x00000100U
-#define RTC_ISR_INIT                         0x00000080U
-#define RTC_ISR_INITF                        0x00000040U
-#define RTC_ISR_RSF                          0x00000020U
-#define RTC_ISR_INITS                        0x00000010U
-#define RTC_ISR_SHPF                         0x00000008U
-#define RTC_ISR_WUTWF                        0x00000004U
-#define RTC_ISR_ALRBWF                       0x00000002U
-#define RTC_ISR_ALRAWF                       0x00000001U
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    0x007F0000U
-#define RTC_PRER_PREDIV_S                    0x00007FFFU
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS                       0x00000080U
-#define RTC_CALIBR_DC                        0x0000001FU
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      0x80000000U
-#define RTC_ALRMAR_WDSEL                     0x40000000U
-#define RTC_ALRMAR_DT                        0x30000000U
-#define RTC_ALRMAR_DT_0                      0x10000000U
-#define RTC_ALRMAR_DT_1                      0x20000000U
-#define RTC_ALRMAR_DU                        0x0F000000U
-#define RTC_ALRMAR_DU_0                      0x01000000U
-#define RTC_ALRMAR_DU_1                      0x02000000U
-#define RTC_ALRMAR_DU_2                      0x04000000U
-#define RTC_ALRMAR_DU_3                      0x08000000U
-#define RTC_ALRMAR_MSK3                      0x00800000U
-#define RTC_ALRMAR_PM                        0x00400000U
-#define RTC_ALRMAR_HT                        0x00300000U
-#define RTC_ALRMAR_HT_0                      0x00100000U
-#define RTC_ALRMAR_HT_1                      0x00200000U
-#define RTC_ALRMAR_HU                        0x000F0000U
-#define RTC_ALRMAR_HU_0                      0x00010000U
-#define RTC_ALRMAR_HU_1                      0x00020000U
-#define RTC_ALRMAR_HU_2                      0x00040000U
-#define RTC_ALRMAR_HU_3                      0x00080000U
-#define RTC_ALRMAR_MSK2                      0x00008000U
-#define RTC_ALRMAR_MNT                       0x00007000U
-#define RTC_ALRMAR_MNT_0                     0x00001000U
-#define RTC_ALRMAR_MNT_1                     0x00002000U
-#define RTC_ALRMAR_MNT_2                     0x00004000U
-#define RTC_ALRMAR_MNU                       0x00000F00U
-#define RTC_ALRMAR_MNU_0                     0x00000100U
-#define RTC_ALRMAR_MNU_1                     0x00000200U
-#define RTC_ALRMAR_MNU_2                     0x00000400U
-#define RTC_ALRMAR_MNU_3                     0x00000800U
-#define RTC_ALRMAR_MSK1                      0x00000080U
-#define RTC_ALRMAR_ST                        0x00000070U
-#define RTC_ALRMAR_ST_0                      0x00000010U
-#define RTC_ALRMAR_ST_1                      0x00000020U
-#define RTC_ALRMAR_ST_2                      0x00000040U
-#define RTC_ALRMAR_SU                        0x0000000FU
-#define RTC_ALRMAR_SU_0                      0x00000001U
-#define RTC_ALRMAR_SU_1                      0x00000002U
-#define RTC_ALRMAR_SU_2                      0x00000004U
-#define RTC_ALRMAR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      0x80000000U
-#define RTC_ALRMBR_WDSEL                     0x40000000U
-#define RTC_ALRMBR_DT                        0x30000000U
-#define RTC_ALRMBR_DT_0                      0x10000000U
-#define RTC_ALRMBR_DT_1                      0x20000000U
-#define RTC_ALRMBR_DU                        0x0F000000U
-#define RTC_ALRMBR_DU_0                      0x01000000U
-#define RTC_ALRMBR_DU_1                      0x02000000U
-#define RTC_ALRMBR_DU_2                      0x04000000U
-#define RTC_ALRMBR_DU_3                      0x08000000U
-#define RTC_ALRMBR_MSK3                      0x00800000U
-#define RTC_ALRMBR_PM                        0x00400000U
-#define RTC_ALRMBR_HT                        0x00300000U
-#define RTC_ALRMBR_HT_0                      0x00100000U
-#define RTC_ALRMBR_HT_1                      0x00200000U
-#define RTC_ALRMBR_HU                        0x000F0000U
-#define RTC_ALRMBR_HU_0                      0x00010000U
-#define RTC_ALRMBR_HU_1                      0x00020000U
-#define RTC_ALRMBR_HU_2                      0x00040000U
-#define RTC_ALRMBR_HU_3                      0x00080000U
-#define RTC_ALRMBR_MSK2                      0x00008000U
-#define RTC_ALRMBR_MNT                       0x00007000U
-#define RTC_ALRMBR_MNT_0                     0x00001000U
-#define RTC_ALRMBR_MNT_1                     0x00002000U
-#define RTC_ALRMBR_MNT_2                     0x00004000U
-#define RTC_ALRMBR_MNU                       0x00000F00U
-#define RTC_ALRMBR_MNU_0                     0x00000100U
-#define RTC_ALRMBR_MNU_1                     0x00000200U
-#define RTC_ALRMBR_MNU_2                     0x00000400U
-#define RTC_ALRMBR_MNU_3                     0x00000800U
-#define RTC_ALRMBR_MSK1                      0x00000080U
-#define RTC_ALRMBR_ST                        0x00000070U
-#define RTC_ALRMBR_ST_0                      0x00000010U
-#define RTC_ALRMBR_ST_1                      0x00000020U
-#define RTC_ALRMBR_ST_2                      0x00000040U
-#define RTC_ALRMBR_SU                        0x0000000FU
-#define RTC_ALRMBR_SU_0                      0x00000001U
-#define RTC_ALRMBR_SU_1                      0x00000002U
-#define RTC_ALRMBR_SU_2                      0x00000004U
-#define RTC_ALRMBR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          0x000000FFU
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           0x0000FFFFU
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     0x00007FFFU
-#define RTC_SHIFTR_ADD1S                     0x80000000U
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          0x00400000U
-#define RTC_TSTR_HT                          0x00300000U
-#define RTC_TSTR_HT_0                        0x00100000U
-#define RTC_TSTR_HT_1                        0x00200000U
-#define RTC_TSTR_HU                          0x000F0000U
-#define RTC_TSTR_HU_0                        0x00010000U
-#define RTC_TSTR_HU_1                        0x00020000U
-#define RTC_TSTR_HU_2                        0x00040000U
-#define RTC_TSTR_HU_3                        0x00080000U
-#define RTC_TSTR_MNT                         0x00007000U
-#define RTC_TSTR_MNT_0                       0x00001000U
-#define RTC_TSTR_MNT_1                       0x00002000U
-#define RTC_TSTR_MNT_2                       0x00004000U
-#define RTC_TSTR_MNU                         0x00000F00U
-#define RTC_TSTR_MNU_0                       0x00000100U
-#define RTC_TSTR_MNU_1                       0x00000200U
-#define RTC_TSTR_MNU_2                       0x00000400U
-#define RTC_TSTR_MNU_3                       0x00000800U
-#define RTC_TSTR_ST                          0x00000070U
-#define RTC_TSTR_ST_0                        0x00000010U
-#define RTC_TSTR_ST_1                        0x00000020U
-#define RTC_TSTR_ST_2                        0x00000040U
-#define RTC_TSTR_SU                          0x0000000FU
-#define RTC_TSTR_SU_0                        0x00000001U
-#define RTC_TSTR_SU_1                        0x00000002U
-#define RTC_TSTR_SU_2                        0x00000004U
-#define RTC_TSTR_SU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         0x0000E000U
-#define RTC_TSDR_WDU_0                       0x00002000U
-#define RTC_TSDR_WDU_1                       0x00004000U
-#define RTC_TSDR_WDU_2                       0x00008000U
-#define RTC_TSDR_MT                          0x00001000U
-#define RTC_TSDR_MU                          0x00000F00U
-#define RTC_TSDR_MU_0                        0x00000100U
-#define RTC_TSDR_MU_1                        0x00000200U
-#define RTC_TSDR_MU_2                        0x00000400U
-#define RTC_TSDR_MU_3                        0x00000800U
-#define RTC_TSDR_DT                          0x00000030U
-#define RTC_TSDR_DT_0                        0x00000010U
-#define RTC_TSDR_DT_1                        0x00000020U
-#define RTC_TSDR_DU                          0x0000000FU
-#define RTC_TSDR_DU_0                        0x00000001U
-#define RTC_TSDR_DU_1                        0x00000002U
-#define RTC_TSDR_DU_2                        0x00000004U
-#define RTC_TSDR_DU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        0x00008000U
-#define RTC_CALR_CALW8                       0x00004000U
-#define RTC_CALR_CALW16                      0x00002000U
-#define RTC_CALR_CALM                        0x000001FFU
-#define RTC_CALR_CALM_0                      0x00000001U
-#define RTC_CALR_CALM_1                      0x00000002U
-#define RTC_CALR_CALM_2                      0x00000004U
-#define RTC_CALR_CALM_3                      0x00000008U
-#define RTC_CALR_CALM_4                      0x00000010U
-#define RTC_CALR_CALM_5                      0x00000020U
-#define RTC_CALR_CALM_6                      0x00000040U
-#define RTC_CALR_CALM_7                      0x00000080U
-#define RTC_CALR_CALM_8                      0x00000100U
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               0x00040000U
-#define RTC_TAFCR_TSINSEL                    0x00020000U
-#define RTC_TAFCR_TAMPINSEL                  0x00010000U
-#define RTC_TAFCR_TAMPPUDIS                  0x00008000U
-#define RTC_TAFCR_TAMPPRCH                   0x00006000U
-#define RTC_TAFCR_TAMPPRCH_0                 0x00002000U
-#define RTC_TAFCR_TAMPPRCH_1                 0x00004000U
-#define RTC_TAFCR_TAMPFLT                    0x00001800U
-#define RTC_TAFCR_TAMPFLT_0                  0x00000800U
-#define RTC_TAFCR_TAMPFLT_1                  0x00001000U
-#define RTC_TAFCR_TAMPFREQ                   0x00000700U
-#define RTC_TAFCR_TAMPFREQ_0                 0x00000100U
-#define RTC_TAFCR_TAMPFREQ_1                 0x00000200U
-#define RTC_TAFCR_TAMPFREQ_2                 0x00000400U
-#define RTC_TAFCR_TAMPTS                     0x00000080U
-#define RTC_TAFCR_TAMP2TRG                   0x00000010U
-#define RTC_TAFCR_TAMP2E                     0x00000008U
-#define RTC_TAFCR_TAMPIE                     0x00000004U
-#define RTC_TAFCR_TAMP1TRG                   0x00000002U
-#define RTC_TAFCR_TAMP1E                     0x00000001U
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  0x0F000000U
-#define RTC_ALRMASSR_MASKSS_0                0x01000000U
-#define RTC_ALRMASSR_MASKSS_1                0x02000000U
-#define RTC_ALRMASSR_MASKSS_2                0x04000000U
-#define RTC_ALRMASSR_MASKSS_3                0x08000000U
-#define RTC_ALRMASSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
-#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
-#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
-#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
-#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
-#define RTC_ALRMBSSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           0xFFFFFFFFU
-
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          SD host Interface                                 */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SDIO_POWER register  ******************/
-#define  SDIO_POWER_PWRCTRL                  0x03U               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDIO_POWER_PWRCTRL_0                0x01U               /*!<Bit 0 */
-#define  SDIO_POWER_PWRCTRL_1                0x02U               /*!<Bit 1 */
-
-/******************  Bit definition for SDIO_CLKCR register  ******************/
-#define  SDIO_CLKCR_CLKDIV                   0x00FFU            /*!<Clock divide factor             */
-#define  SDIO_CLKCR_CLKEN                    0x0100U            /*!<Clock enable bit                */
-#define  SDIO_CLKCR_PWRSAV                   0x0200U            /*!<Power saving configuration bit  */
-#define  SDIO_CLKCR_BYPASS                   0x0400U            /*!<Clock divider bypass enable bit */
-
-#define  SDIO_CLKCR_WIDBUS                   0x1800U            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDIO_CLKCR_WIDBUS_0                 0x0800U            /*!<Bit 0 */
-#define  SDIO_CLKCR_WIDBUS_1                 0x1000U            /*!<Bit 1 */
-
-#define  SDIO_CLKCR_NEGEDGE                  0x2000U            /*!<SDIO_CK dephasing selection bit */
-#define  SDIO_CLKCR_HWFC_EN                  0x4000U            /*!<HW Flow Control enable          */
-
-/*******************  Bit definition for SDIO_ARG register  *******************/
-#define  SDIO_ARG_CMDARG                     0xFFFFFFFFU            /*!<Command argument */
-
-/*******************  Bit definition for SDIO_CMD register  *******************/
-#define  SDIO_CMD_CMDINDEX                   0x003FU            /*!<Command Index                               */
-
-#define  SDIO_CMD_WAITRESP                   0x00C0U            /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDIO_CMD_WAITRESP_0                 0x0040U            /*!< Bit 0 */
-#define  SDIO_CMD_WAITRESP_1                 0x0080U            /*!< Bit 1 */
-
-#define  SDIO_CMD_WAITINT                    0x0100U            /*!<CPSM Waits for Interrupt Request                               */
-#define  SDIO_CMD_WAITPEND                   0x0200U            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDIO_CMD_CPSMEN                     0x0400U            /*!<Command path state machine (CPSM) Enable bit                   */
-#define  SDIO_CMD_SDIOSUSPEND                0x0800U            /*!<SD I/O suspend command                                         */
-#define  SDIO_CMD_ENCMDCOMPL                 0x1000U            /*!<Enable CMD completion                                          */
-#define  SDIO_CMD_NIEN                       0x2000U            /*!<Not Interrupt Enable */
-#define  SDIO_CMD_CEATACMD                   0x4000U            /*!<CE-ATA command       */
-
-/*****************  Bit definition for SDIO_RESPCMD register  *****************/
-#define  SDIO_RESPCMD_RESPCMD                0x3FU               /*!<Response command index */
-
-/******************  Bit definition for SDIO_RESP0 register  ******************/
-#define  SDIO_RESP0_CARDSTATUS0              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP1 register  ******************/
-#define  SDIO_RESP1_CARDSTATUS1              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP2 register  ******************/
-#define  SDIO_RESP2_CARDSTATUS2              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP3 register  ******************/
-#define  SDIO_RESP3_CARDSTATUS3              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP4 register  ******************/
-#define  SDIO_RESP4_CARDSTATUS4              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_DTIMER register  *****************/
-#define  SDIO_DTIMER_DATATIME                0xFFFFFFFFU        /*!<Data timeout period. */
-
-/******************  Bit definition for SDIO_DLEN register  *******************/
-#define  SDIO_DLEN_DATALENGTH                0x01FFFFFFU        /*!<Data length value    */
-
-/******************  Bit definition for SDIO_DCTRL register  ******************/
-#define  SDIO_DCTRL_DTEN                     0x0001U            /*!<Data transfer enabled bit         */
-#define  SDIO_DCTRL_DTDIR                    0x0002U            /*!<Data transfer direction selection */
-#define  SDIO_DCTRL_DTMODE                   0x0004U            /*!<Data transfer mode selection      */
-#define  SDIO_DCTRL_DMAEN                    0x0008U            /*!<DMA enabled bit                   */
-
-#define  SDIO_DCTRL_DBLOCKSIZE               0x00F0U            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDIO_DCTRL_DBLOCKSIZE_0             0x0010U            /*!<Bit 0 */
-#define  SDIO_DCTRL_DBLOCKSIZE_1             0x0020U            /*!<Bit 1 */
-#define  SDIO_DCTRL_DBLOCKSIZE_2             0x0040U            /*!<Bit 2 */
-#define  SDIO_DCTRL_DBLOCKSIZE_3             0x0080U            /*!<Bit 3 */
-
-#define  SDIO_DCTRL_RWSTART                  0x0100U            /*!<Read wait start         */
-#define  SDIO_DCTRL_RWSTOP                   0x0200U            /*!<Read wait stop          */
-#define  SDIO_DCTRL_RWMOD                    0x0400U            /*!<Read wait mode          */
-#define  SDIO_DCTRL_SDIOEN                   0x0800U            /*!<SD I/O enable functions */
-
-/******************  Bit definition for SDIO_DCOUNT register  *****************/
-#define  SDIO_DCOUNT_DATACOUNT               0x01FFFFFFU        /*!<Data count value */
-
-/******************  Bit definition for SDIO_STA register  ********************/
-#define  SDIO_STA_CCRCFAIL                   0x00000001U        /*!<Command response received (CRC check failed)  */
-#define  SDIO_STA_DCRCFAIL                   0x00000002U        /*!<Data block sent/received (CRC check failed)   */
-#define  SDIO_STA_CTIMEOUT                   0x00000004U        /*!<Command response timeout                      */
-#define  SDIO_STA_DTIMEOUT                   0x00000008U        /*!<Data timeout                                  */
-#define  SDIO_STA_TXUNDERR                   0x00000010U        /*!<Transmit FIFO underrun error                  */
-#define  SDIO_STA_RXOVERR                    0x00000020U        /*!<Received FIFO overrun error                   */
-#define  SDIO_STA_CMDREND                    0x00000040U        /*!<Command response received (CRC check passed)  */
-#define  SDIO_STA_CMDSENT                    0x00000080U        /*!<Command sent (no response required)           */
-#define  SDIO_STA_DATAEND                    0x00000100U        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
-#define  SDIO_STA_STBITERR                   0x00000200U        /*!<Start bit not detected on all data signals in wide bus mode */
-#define  SDIO_STA_DBCKEND                    0x00000400U        /*!<Data block sent/received (CRC check passed)   */
-#define  SDIO_STA_CMDACT                     0x00000800U        /*!<Command transfer in progress                  */
-#define  SDIO_STA_TXACT                      0x00001000U        /*!<Data transmit in progress                     */
-#define  SDIO_STA_RXACT                      0x00002000U        /*!<Data receive in progress                      */
-#define  SDIO_STA_TXFIFOHE                   0x00004000U        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDIO_STA_RXFIFOHF                   0x00008000U        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDIO_STA_TXFIFOF                    0x00010000U        /*!<Transmit FIFO full                            */
-#define  SDIO_STA_RXFIFOF                    0x00020000U        /*!<Receive FIFO full                             */
-#define  SDIO_STA_TXFIFOE                    0x00040000U        /*!<Transmit FIFO empty                           */
-#define  SDIO_STA_RXFIFOE                    0x00080000U        /*!<Receive FIFO empty                            */
-#define  SDIO_STA_TXDAVL                     0x00100000U        /*!<Data available in transmit FIFO               */
-#define  SDIO_STA_RXDAVL                     0x00200000U        /*!<Data available in receive FIFO                */
-#define  SDIO_STA_SDIOIT                     0x00400000U        /*!<SDIO interrupt received                       */
-#define  SDIO_STA_CEATAEND                   0x00800000U        /*!<CE-ATA command completion signal received for CMD61 */
-
-/*******************  Bit definition for SDIO_ICR register  *******************/
-#define  SDIO_ICR_CCRCFAILC                  0x00000001U        /*!<CCRCFAIL flag clear bit */
-#define  SDIO_ICR_DCRCFAILC                  0x00000002U        /*!<DCRCFAIL flag clear bit */
-#define  SDIO_ICR_CTIMEOUTC                  0x00000004U        /*!<CTIMEOUT flag clear bit */
-#define  SDIO_ICR_DTIMEOUTC                  0x00000008U        /*!<DTIMEOUT flag clear bit */
-#define  SDIO_ICR_TXUNDERRC                  0x00000010U        /*!<TXUNDERR flag clear bit */
-#define  SDIO_ICR_RXOVERRC                   0x00000020U        /*!<RXOVERR flag clear bit  */
-#define  SDIO_ICR_CMDRENDC                   0x00000040U        /*!<CMDREND flag clear bit  */
-#define  SDIO_ICR_CMDSENTC                   0x00000080U        /*!<CMDSENT flag clear bit  */
-#define  SDIO_ICR_DATAENDC                   0x00000100U        /*!<DATAEND flag clear bit  */
-#define  SDIO_ICR_STBITERRC                  0x00000200U        /*!<STBITERR flag clear bit */
-#define  SDIO_ICR_DBCKENDC                   0x00000400U        /*!<DBCKEND flag clear bit  */
-#define  SDIO_ICR_SDIOITC                    0x00400000U        /*!<SDIOIT flag clear bit   */
-#define  SDIO_ICR_CEATAENDC                  0x00800000U        /*!<CEATAEND flag clear bit */
-
-/******************  Bit definition for SDIO_MASK register  *******************/
-#define  SDIO_MASK_CCRCFAILIE                0x00000001U        /*!<Command CRC Fail Interrupt Enable          */
-#define  SDIO_MASK_DCRCFAILIE                0x00000002U        /*!<Data CRC Fail Interrupt Enable             */
-#define  SDIO_MASK_CTIMEOUTIE                0x00000004U        /*!<Command TimeOut Interrupt Enable           */
-#define  SDIO_MASK_DTIMEOUTIE                0x00000008U        /*!<Data TimeOut Interrupt Enable              */
-#define  SDIO_MASK_TXUNDERRIE                0x00000010U        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
-#define  SDIO_MASK_RXOVERRIE                 0x00000020U        /*!<Rx FIFO OverRun Error Interrupt Enable     */
-#define  SDIO_MASK_CMDRENDIE                 0x00000040U        /*!<Command Response Received Interrupt Enable */
-#define  SDIO_MASK_CMDSENTIE                 0x00000080U        /*!<Command Sent Interrupt Enable              */
-#define  SDIO_MASK_DATAENDIE                 0x00000100U        /*!<Data End Interrupt Enable                  */
-#define  SDIO_MASK_STBITERRIE                0x00000200U        /*!<Start Bit Error Interrupt Enable           */
-#define  SDIO_MASK_DBCKENDIE                 0x00000400U        /*!<Data Block End Interrupt Enable            */
-#define  SDIO_MASK_CMDACTIE                  0x00000800U        /*!<CCommand Acting Interrupt Enable           */
-#define  SDIO_MASK_TXACTIE                   0x00001000U        /*!<Data Transmit Acting Interrupt Enable      */
-#define  SDIO_MASK_RXACTIE                   0x00002000U        /*!<Data receive acting interrupt enabled      */
-#define  SDIO_MASK_TXFIFOHEIE                0x00004000U        /*!<Tx FIFO Half Empty interrupt Enable        */
-#define  SDIO_MASK_RXFIFOHFIE                0x00008000U        /*!<Rx FIFO Half Full interrupt Enable         */
-#define  SDIO_MASK_TXFIFOFIE                 0x00010000U        /*!<Tx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_RXFIFOFIE                 0x00020000U        /*!<Rx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_TXFIFOEIE                 0x00040000U        /*!<Tx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_RXFIFOEIE                 0x00080000U        /*!<Rx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_TXDAVLIE                  0x00100000U        /*!<Data available in Tx FIFO interrupt Enable */
-#define  SDIO_MASK_RXDAVLIE                  0x00200000U        /*!<Data available in Rx FIFO interrupt Enable */
-#define  SDIO_MASK_SDIOITIE                  0x00400000U        /*!<SDIO Mode Interrupt Received interrupt Enable */
-#define  SDIO_MASK_CEATAENDIE                0x00800000U        /*!<CE-ATA command completion signal received Interrupt Enable */
-
-/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
-#define  SDIO_FIFOCNT_FIFOCOUNT              0x00FFFFFFU        /*!<Remaining number of words to be written to or read from the FIFO */
-
-/******************  Bit definition for SDIO_FIFO register  *******************/
-#define  SDIO_FIFO_FIFODATA                  0xFFFFFFFFU        /*!<Receive and transmit FIFO data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        0x00000001U            /*!<Clock Phase      */
-#define  SPI_CR1_CPOL                        0x00000002U            /*!<Clock Polarity   */
-#define  SPI_CR1_MSTR                        0x00000004U            /*!<Master Selection */
-
-#define  SPI_CR1_BR                          0x00000038U            /*!<BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        0x00000008U            /*!<Bit 0 */
-#define  SPI_CR1_BR_1                        0x00000010U            /*!<Bit 1 */
-#define  SPI_CR1_BR_2                        0x00000020U            /*!<Bit 2 */
-
-#define  SPI_CR1_SPE                         0x00000040U            /*!<SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    0x00000080U            /*!<Frame Format                        */
-#define  SPI_CR1_SSI                         0x00000100U            /*!<Internal slave select               */
-#define  SPI_CR1_SSM                         0x00000200U            /*!<Software slave management           */
-#define  SPI_CR1_RXONLY                      0x00000400U            /*!<Receive only                        */
-#define  SPI_CR1_DFF                         0x00000800U            /*!<Data Frame Format                   */
-#define  SPI_CR1_CRCNEXT                     0x00001000U            /*!<Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       0x00002000U            /*!<Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      0x00004000U            /*!<Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    0x00008000U            /*!<Bidirectional data mode enable      */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     0x00000001U               /*!<Rx Buffer DMA Enable                 */
-#define  SPI_CR2_TXDMAEN                     0x00000002U               /*!<Tx Buffer DMA Enable                 */
-#define  SPI_CR2_SSOE                        0x00000004U               /*!<SS Output Enable                     */
-#define  SPI_CR2_FRF                         0x00000010U               /*!<Frame Format                         */
-#define  SPI_CR2_ERRIE                       0x00000020U               /*!<Error Interrupt Enable               */
-#define  SPI_CR2_RXNEIE                      0x00000040U               /*!<RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       0x00000080U               /*!<Tx buffer Empty Interrupt Enable     */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         0x00000001U               /*!<Receive buffer Not Empty */
-#define  SPI_SR_TXE                          0x00000002U               /*!<Transmit buffer Empty    */
-#define  SPI_SR_CHSIDE                       0x00000004U               /*!<Channel side             */
-#define  SPI_SR_UDR                          0x00000008U               /*!<Underrun flag            */
-#define  SPI_SR_CRCERR                       0x00000010U               /*!<CRC Error flag           */
-#define  SPI_SR_MODF                         0x00000020U               /*!<Mode fault               */
-#define  SPI_SR_OVR                          0x00000040U               /*!<Overrun flag             */
-#define  SPI_SR_BSY                          0x00000080U               /*!<Busy flag                */
-#define  SPI_SR_FRE                          0x00000100U               /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           0x0000FFFFU            /*!<Data Register           */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   0x0000FFFFU            /*!<CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    0x0000FFFFU            /*!<Rx CRC Register         */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    0x0000FFFFU            /*!<Tx CRC Register         */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   0x00000001U            /*!<Channel length (number of bits per audio channel) */
-
-#define  SPI_I2SCFGR_DATLEN                  0x00000006U            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define  SPI_I2SCFGR_DATLEN_0                0x00000002U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                0x00000004U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_CKPOL                   0x00000008U            /*!<steady state clock polarity               */
-
-#define  SPI_I2SCFGR_I2SSTD                  0x00000030U            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U            /*!<PCM frame synchronization                 */
-
-#define  SPI_I2SCFGR_I2SCFG                  0x00000300U            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_I2SE                    0x00000400U            /*!<I2S Enable         */
-#define  SPI_I2SCFGR_I2SMOD                  0x00000800U            /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    0x000000FFU            /*!<I2S Linear prescaler         */
-#define  SPI_I2SPR_ODD                       0x00000100U            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     0x00000200U            /*!<Master Clock Output Enable   */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 SYSCFG                                     */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
-#define SYSCFG_MEMRMP_MEM_MODE          0x00000007U /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        0x00000001U
-#define SYSCFG_MEMRMP_MEM_MODE_1        0x00000002U
-#define SYSCFG_MEMRMP_MEM_MODE_2        0x00000004U
-
-#define SYSCFG_SWP_FSMC                  0x00000C00U /*!< FSMC memory mapping swap */
-/******************  Bit definition for SYSCFG_PMC register  ******************/
-#define SYSCFG_PMC_ADC1DC2              0x00010000U /*!< Refer to AN4073 on how to use this bit  */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
-/** 
-  * @brief   EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         0x0003U /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         0x0004U /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         0x0005U /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         0x0006U /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
-
-/** 
-  * @brief   EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         0x0030U /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         0x0040U /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         0x0050U /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         0x0060U /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
-
-/** 
-  * @brief   EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         0x0300U /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         0x0400U /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         0x0500U /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         0x0600U /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
-
-/** 
-  * @brief   EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         0x3000U /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         0x4000U /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         0x5000U /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         0x6000U /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
-/** 
-  * @brief   EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         0x0003U /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         0x0004U /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         0x0005U /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         0x0006U /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
-
-/** 
-  * @brief   EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         0x0030U /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         0x0040U /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         0x0050U /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         0x0060U /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
-
-/** 
-  * @brief   EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         0x0300U /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         0x0400U /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         0x0500U /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         0x0600U /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
-
-/** 
-  * @brief   EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         0x3000U /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         0x4000U /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         0x5000U /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         0x6000U /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
-
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
-
-/** 
-  * @brief   EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         0x0003U /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         0x0004U /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         0x0005U /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         0x0006U /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
-
-/** 
-  * @brief   EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         0x0030U /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         0x0040U /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         0x0050U /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         0x0060U /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
-
-/** 
-  * @brief   EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        0x0300U /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        0x0400U /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        0x0500U /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        0x0600U /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
-
-/** 
-  * @brief   EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        0x3000U /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        0x4000U /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        0x5000U /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        0x6000U /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
-/** 
-  * @brief   EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        0x0003U /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        0x0004U /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        0x0005U /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        0x0006U /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
-
-/** 
-  * @brief   EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        0x0030U /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        0x0040U /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        0x0050U /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        0x0060U /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
-
-/** 
-  * @brief   EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        0x0300U /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        0x0400U /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        0x0500U /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        0x0600U /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
-
-/** 
-  * @brief   EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        0x3000U /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        0x4000U /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        0x5000U /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        0x6000U /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
-
-/******************  Bit definition for SYSCFG_CMPCR register  ****************/
-#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell ready flag */
-#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell power-down */
-
-/******************  Bit definition for SYSCFG_CFGR register  *****************/
-#define SYSCFG_CFGR_FMPI2C1_SCL         0x00000001U /*!<FM+ drive capability for FMPI2C1_SCL pin */
-#define SYSCFG_CFGR_FMPI2C1_SDA         0x00000002U /*!<FM+ drive capability for FMPI2C1_SDA pin */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    TIM                                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
-#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
-#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
-#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
-#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
-
-#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
-
-#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
-
-#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        0x0001U            /*!<Capture/Compare Preloaded Control        */
-#define  TIM_CR2_CCUS                        0x0004U            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        0x0008U            /*!<Capture/Compare DMA Selection            */
-
-#define  TIM_CR2_MMS                         0x0070U            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
-#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
-#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
-#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        0x0007U            /*!<SMS[2:0] bits (Slave mode selection)    */
-#define  TIM_SMCR_SMS_0                      0x0001U            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      0x0002U            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      0x0004U            /*!<Bit 2 */
-
-#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
-#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
-
-#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
-
-#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
-
-#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
-#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
-#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
-#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
-#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
-#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
-#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
-#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
-#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
-#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
-#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
-#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
-#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
-#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
-#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
-#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
-#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
-#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
-#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          0x01U               /*!<Update Generation                         */
-#define  TIM_EGR_CC1G                        0x02U               /*!<Capture/Compare 1 Generation              */
-#define  TIM_EGR_CC2G                        0x04U               /*!<Capture/Compare 2 Generation              */
-#define  TIM_EGR_CC3G                        0x08U               /*!<Capture/Compare 3 Generation              */
-#define  TIM_EGR_CC4G                        0x10U               /*!<Capture/Compare 4 Generation              */
-#define  TIM_EGR_COMG                        0x20U               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          0x40U               /*!<Trigger Generation                        */
-#define  TIM_EGR_BG                          0x80U               /*!<Break Generation                          */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      0x0003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    0x0001U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    0x0002U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC1FE                     0x0004U            /*!<Output Compare 1 Fast enable                 */
-#define  TIM_CCMR1_OC1PE                     0x0008U            /*!<Output Compare 1 Preload enable              */
-
-#define  TIM_CCMR1_OC1M                      0x0070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define  TIM_CCMR1_OC1M_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    0x0040U            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC1CE                     0x0080U            /*!<Output Compare 1Clear Enable                 */
-
-#define  TIM_CCMR1_CC2S                      0x0300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    0x0100U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    0x0200U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC2FE                     0x0400U            /*!<Output Compare 2 Fast enable                 */
-#define  TIM_CCMR1_OC2PE                     0x0800U            /*!<Output Compare 2 Preload enable              */
-
-#define  TIM_CCMR1_OC2M                      0x7000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define  TIM_CCMR1_OC2M_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    0x4000U            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC2CE                     0x8000U            /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      0x0003U            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define  TIM_CCMR2_CC3S_0                    0x0001U            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    0x0002U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC3FE                     0x0004U            /*!<Output Compare 3 Fast enable           */
-#define  TIM_CCMR2_OC3PE                     0x0008U            /*!<Output Compare 3 Preload enable        */
-
-#define  TIM_CCMR2_OC3M                      0x0070U            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    0x0040U            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC3CE                     0x0080U            /*!<Output Compare 3 Clear Enable */
-
-#define  TIM_CCMR2_CC4S                      0x0300U            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    0x0100U            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    0x0200U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC4FE                     0x0400U            /*!<Output Compare 4 Fast enable    */
-#define  TIM_CCMR2_OC4PE                     0x0800U            /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR2_OC4M                      0x7000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    0x4000U            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       0x0001U            /*!<Capture/Compare 1 output enable                 */
-#define  TIM_CCER_CC1P                       0x0002U            /*!<Capture/Compare 1 output Polarity               */
-#define  TIM_CCER_CC1NE                      0x0004U            /*!<Capture/Compare 1 Complementary output enable   */
-#define  TIM_CCER_CC1NP                      0x0008U            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       0x0010U            /*!<Capture/Compare 2 output enable                 */
-#define  TIM_CCER_CC2P                       0x0020U            /*!<Capture/Compare 2 output Polarity               */
-#define  TIM_CCER_CC2NE                      0x0040U            /*!<Capture/Compare 2 Complementary output enable   */
-#define  TIM_CCER_CC2NP                      0x0080U            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       0x0100U            /*!<Capture/Compare 3 output enable                 */
-#define  TIM_CCER_CC3P                       0x0200U            /*!<Capture/Compare 3 output Polarity               */
-#define  TIM_CCER_CC3NE                      0x0400U            /*!<Capture/Compare 3 Complementary output enable   */
-#define  TIM_CCER_CC3NP                      0x0800U            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       0x1000U            /*!<Capture/Compare 4 output enable                 */
-#define  TIM_CCER_CC4P                       0x2000U            /*!<Capture/Compare 4 output Polarity               */
-#define  TIM_CCER_CC4NP                      0x8000U            /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         0xFFU               /*!<Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
-
-/*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        0x00FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      0x0001U            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      0x0002U            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      0x0004U            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      0x0008U            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      0x0010U            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      0x0020U            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      0x0040U            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      0x0080U            /*!<Bit 7 */
-
-#define  TIM_BDTR_LOCK                       0x0300U            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     0x0100U            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     0x0200U            /*!<Bit 1 */
-
-#define  TIM_BDTR_OSSI                       0x0400U            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       0x0800U            /*!<Off-State Selection for Run mode  */
-#define  TIM_BDTR_BKE                        0x1000U            /*!<Break enable                      */
-#define  TIM_BDTR_BKP                        0x2000U            /*!<Break Polarity                    */
-#define  TIM_BDTR_AOE                        0x4000U            /*!<Automatic Output enable           */
-#define  TIM_BDTR_MOE                        0x8000U            /*!<Main Output enable                */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
-
-#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
-#define TIM_OR_ITR1_RMP                      0x0C00U            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
-#define TIM_OR_ITR1_RMP_0                    0x0400U            /*!<Bit 0 */
-#define TIM_OR_ITR1_RMP_1                    0x0800U            /*!<Bit 1 */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*         Universal Synchronous Asynchronous Receiver Transmitter            */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         0x0001U            /*!<Parity Error                 */
-#define  USART_SR_FE                         0x0002U            /*!<Framing Error                */
-#define  USART_SR_NE                         0x0004U            /*!<Noise Error Flag             */
-#define  USART_SR_ORE                        0x0008U            /*!<OverRun Error                */
-#define  USART_SR_IDLE                       0x0010U            /*!<IDLE line detected           */
-#define  USART_SR_RXNE                       0x0020U            /*!<Read Data Register Not Empty */
-#define  USART_SR_TC                         0x0040U            /*!<Transmission Complete        */
-#define  USART_SR_TXE                        0x0080U            /*!<Transmit Data Register Empty */
-#define  USART_SR_LBD                        0x0100U            /*!<LIN Break Detection Flag     */
-#define  USART_SR_CTS                        0x0200U            /*!<CTS Flag                     */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         0x01FFU            /*!<Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_Fraction              0x000FU            /*!<Fraction of USARTDIV */
-#define  USART_BRR_DIV_Mantissa              0xFFF0U            /*!<Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       0x0001U            /*!<Send Break                             */
-#define  USART_CR1_RWU                       0x0002U            /*!<Receiver wakeup                        */
-#define  USART_CR1_RE                        0x0004U            /*!<Receiver Enable                        */
-#define  USART_CR1_TE                        0x0008U            /*!<Transmitter Enable                     */
-#define  USART_CR1_IDLEIE                    0x0010U            /*!<IDLE Interrupt Enable                  */
-#define  USART_CR1_RXNEIE                    0x0020U            /*!<RXNE Interrupt Enable                  */
-#define  USART_CR1_TCIE                      0x0040U            /*!<Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     0x0080U            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PEIE                      0x0100U            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PS                        0x0200U            /*!<Parity Selection                       */
-#define  USART_CR1_PCE                       0x0400U            /*!<Parity Control Enable                  */
-#define  USART_CR1_WAKE                      0x0800U            /*!<Wakeup method                          */
-#define  USART_CR1_M                         0x1000U            /*!<Word length                            */
-#define  USART_CR1_UE                        0x2000U            /*!<USART Enable                           */
-#define  USART_CR1_OVER8                     0x8000U            /*!<USART Oversampling by 8 enable         */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       0x000FU            /*!<Address of the USART node            */
-#define  USART_CR2_LBDL                      0x0020U            /*!<LIN Break Detection Length           */
-#define  USART_CR2_LBDIE                     0x0040U            /*!<LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      0x0100U            /*!<Last Bit Clock pulse                 */
-#define  USART_CR2_CPHA                      0x0200U            /*!<Clock Phase                          */
-#define  USART_CR2_CPOL                      0x0400U            /*!<Clock Polarity                       */
-#define  USART_CR2_CLKEN                     0x0800U            /*!<Clock Enable                         */
-
-#define  USART_CR2_STOP                      0x3000U            /*!<STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    0x1000U            /*!<Bit 0 */
-#define  USART_CR2_STOP_1                    0x2000U            /*!<Bit 1 */
-
-#define  USART_CR2_LINEN                     0x4000U            /*!<LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       0x0001U            /*!<Error Interrupt Enable      */
-#define  USART_CR3_IREN                      0x0002U            /*!<IrDA mode Enable            */
-#define  USART_CR3_IRLP                      0x0004U            /*!<IrDA Low-Power              */
-#define  USART_CR3_HDSEL                     0x0008U            /*!<Half-Duplex Selection       */
-#define  USART_CR3_NACK                      0x0010U            /*!<Smartcard NACK enable       */
-#define  USART_CR3_SCEN                      0x0020U            /*!<Smartcard mode enable       */
-#define  USART_CR3_DMAR                      0x0040U            /*!<DMA Enable Receiver         */
-#define  USART_CR3_DMAT                      0x0080U            /*!<DMA Enable Transmitter      */
-#define  USART_CR3_RTSE                      0x0100U            /*!<RTS Enable                  */
-#define  USART_CR3_CTSE                      0x0200U            /*!<CTS Enable                  */
-#define  USART_CR3_CTSIE                     0x0400U            /*!<CTS Interrupt Enable        */
-#define  USART_CR3_ONEBIT                    0x0800U            /*!<USART One bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      0x00FFU            /*!<PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    0x0001U            /*!<Bit 0 */
-#define  USART_GTPR_PSC_1                    0x0002U            /*!<Bit 1 */
-#define  USART_GTPR_PSC_2                    0x0004U            /*!<Bit 2 */
-#define  USART_GTPR_PSC_3                    0x0008U            /*!<Bit 3 */
-#define  USART_GTPR_PSC_4                    0x0010U            /*!<Bit 4 */
-#define  USART_GTPR_PSC_5                    0x0020U            /*!<Bit 5 */
-#define  USART_GTPR_PSC_6                    0x0040U            /*!<Bit 6 */
-#define  USART_GTPR_PSC_7                    0x0080U            /*!<Bit 7 */
-
-#define  USART_GTPR_GT                       0xFF00U            /*!<Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Window WATCHDOG                                 */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           0x7FU               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T_0                         0x01U               /*!<Bit 0 */
-#define  WWDG_CR_T_1                         0x02U               /*!<Bit 1 */
-#define  WWDG_CR_T_2                         0x04U               /*!<Bit 2 */
-#define  WWDG_CR_T_3                         0x08U               /*!<Bit 3 */
-#define  WWDG_CR_T_4                         0x10U               /*!<Bit 4 */
-#define  WWDG_CR_T_5                         0x20U               /*!<Bit 5 */
-#define  WWDG_CR_T_6                         0x40U               /*!<Bit 6 */
-/* Legacy defines */
-#define  WWDG_CR_T0                          WWDG_CR_T_0
-#define  WWDG_CR_T1                          WWDG_CR_T_1
-#define  WWDG_CR_T2                          WWDG_CR_T_2
-#define  WWDG_CR_T3                          WWDG_CR_T_3
-#define  WWDG_CR_T4                          WWDG_CR_T_4
-#define  WWDG_CR_T5                          WWDG_CR_T_5
-#define  WWDG_CR_T6                          WWDG_CR_T_6
-
-#define  WWDG_CR_WDGA                        0x80U               /*!<Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          0x007FU            /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W_0                        0x0001U            /*!<Bit 0 */
-#define  WWDG_CFR_W_1                        0x0002U            /*!<Bit 1 */
-#define  WWDG_CFR_W_2                        0x0004U            /*!<Bit 2 */
-#define  WWDG_CFR_W_3                        0x0008U            /*!<Bit 3 */
-#define  WWDG_CFR_W_4                        0x0010U            /*!<Bit 4 */
-#define  WWDG_CFR_W_5                        0x0020U            /*!<Bit 5 */
-#define  WWDG_CFR_W_6                        0x0040U            /*!<Bit 6 */
-/* Legacy defines */
-#define  WWDG_CFR_W0                         WWDG_CFR_W_0
-#define  WWDG_CFR_W1                         WWDG_CFR_W_1
-#define  WWDG_CFR_W2                         WWDG_CFR_W_2
-#define  WWDG_CFR_W3                         WWDG_CFR_W_3
-#define  WWDG_CFR_W4                         WWDG_CFR_W_4
-#define  WWDG_CFR_W5                         WWDG_CFR_W_5
-#define  WWDG_CFR_W6                         WWDG_CFR_W_6
-
-#define  WWDG_CFR_WDGTB                      0x0180U            /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB_0                    0x0080U            /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB_1                    0x0100U            /*!<Bit 1 */
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
-
-#define  WWDG_CFR_EWI                        0x0200U            /*!<Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        0x01U               /*!<Early Wakeup Interrupt Flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                DBG                                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
-#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
-
-/********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
-#define  DBGMCU_CR_DBG_STOP                  0x00000002U
-#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
-#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
-
-#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
-#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U/*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U/*!<Bit 1 */
-
-/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            0x00000001U
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            0x00000002U
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            0x00000004U
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            0x00000020U
-#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           0x00000040U
-#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           0x00000080U
-#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           0x00000100U
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
-#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
-
-/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        0x00000001U
-#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        0x00000002U
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        0x00010000U
-#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       0x00020000U
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       0x00040000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                                       USB_OTG			                        */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for USB_OTG_GOTGCTL register  ***********/
-#define USB_OTG_GOTGCTL_SRQSCS                  0x00000001U         /*!< Session request success */
-#define USB_OTG_GOTGCTL_SRQ                     0x00000002U         /*!< Session request */
-#define USB_OTG_GOTGCTL_VBVALOEN                0x00000004U         /*!< VBUS valid override enable */
-#define USB_OTG_GOTGCTL_VBVALOVAL               0x00000008U         /*!< VBUS valid override value */
-#define USB_OTG_GOTGCTL_AVALOEN                 0x00000010U         /*!< A-peripheral session valid override enable */
-#define USB_OTG_GOTGCTL_AVALOVAL                0x00000020U         /*!< A-peripheral session valid override value */
-#define USB_OTG_GOTGCTL_BVALOEN                 0x00000040U         /*!< B-peripheral session valid override enable */
-#define USB_OTG_GOTGCTL_BVALOVAL                0x00000080U         /*!< B-peripheral session valid override value  */
-#define USB_OTG_GOTGCTL_HNGSCS                  0x00000100U         /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_HNPRQ                   0x00000200U         /*!< HNP request */
-#define USB_OTG_GOTGCTL_HSHNPEN                 0x00000400U         /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_DHNPEN                  0x00000800U         /*!< Device HNP enabled */
-#define USB_OTG_GOTGCTL_EHEN                    0x00001000U         /*!< Embedded host enable */
-#define USB_OTG_GOTGCTL_CIDSTS                  0x00010000U         /*!< Connector ID status */
-#define USB_OTG_GOTGCTL_DBCT                    0x00020000U         /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD                   0x00040000U         /*!< A-session valid  */
-#define USB_OTG_GOTGCTL_BSESVLD                 0x00080000U         /*!< B-session valid */
-#define USB_OTG_GOTGCTL_OTGVER                  0x00100000U         /*!< OTG version  */
-
-/********************  Bit definition for USB_OTG_HCFG register  **************/
-
-#define USB_OTG_HCFG_FSLSPCS                 0x00000003U            /*!< FS/LS PHY clock select */
-#define USB_OTG_HCFG_FSLSPCS_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCFG_FSLSPCS_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCFG_FSLSS                   0x00000004U            /*!< FS- and LS-only support */
-
-/********************  Bit definition for USB_OTG_DCFG register  **************/
-
-#define USB_OTG_DCFG_DSPD                    0x00000003U            /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                  0x00000001U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DSPD_1                  0x00000002U            /*!<Bit 1 */
-#define USB_OTG_DCFG_NZLSOHSK                0x00000004U            /*!< Nonzero-length status OUT handshake */
-
-#define USB_OTG_DCFG_DAD                     0x000007F0U            /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                   0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DAD_1                   0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCFG_DAD_2                   0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCFG_DAD_3                   0x00000080U            /*!<Bit 3 */
-#define USB_OTG_DCFG_DAD_4                   0x00000100U            /*!<Bit 4 */
-#define USB_OTG_DCFG_DAD_5                   0x00000200U            /*!<Bit 5 */
-#define USB_OTG_DCFG_DAD_6                   0x00000400U            /*!<Bit 6 */
-
-#define USB_OTG_DCFG_PFIVL                   0x00001800U            /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PFIVL_1                 0x00001000U            /*!<Bit 1 */
-
-#define USB_OTG_DCFG_PERSCHIVL               0x03000000U            /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0             0x01000000U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PERSCHIVL_1             0x02000000U            /*!<Bit 1 */
-
-/********************  Bit definition for USB_OTG_PCGCR register  *************/
-#define USB_OTG_PCGCR_STPPCLK                 0x00000001U            /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK                0x00000002U            /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP                 0x00000010U            /*!< PHY suspended */
-
-/********************  Bit definition for USB_OTG_GOTGINT register  ***********/
-#define USB_OTG_GOTGINT_SEDET                   0x00000004U            /*!< Session end detected */
-#define USB_OTG_GOTGINT_SRSSCHG                 0x00000100U            /*!< Session request success status change */
-#define USB_OTG_GOTGINT_HNSSCHG                 0x00000200U            /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET                  0x00020000U            /*!< Host negotiation detected */
-#define USB_OTG_GOTGINT_ADTOCHG                 0x00040000U            /*!< A-device timeout change */
-#define USB_OTG_GOTGINT_DBCDNE                  0x00080000U            /*!< Debounce done */
-#define USB_OTG_GOTGINT_IDCHNG                  0x00100000U            /*!< Change in ID pin input value           */
-
-/********************  Bit definition for USB_OTG_DCTL register  **************/
-#define USB_OTG_DCTL_RWUSIG                  0x00000001U            /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS                    0x00000002U            /*!< Soft disconnect */
-#define USB_OTG_DCTL_GINSTS                  0x00000004U            /*!< Global IN NAK status */
-#define USB_OTG_DCTL_GONSTS                  0x00000008U            /*!< Global OUT NAK status */
-#define USB_OTG_DCTL_TCTL                    0x00000070U            /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                  0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCTL_TCTL_1                  0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCTL_TCTL_2                  0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCTL_SGINAK                  0x00000080U            /*!< Set global IN NAK */
-#define USB_OTG_DCTL_CGINAK                  0x00000100U            /*!< Clear global IN NAK */
-#define USB_OTG_DCTL_SGONAK                  0x00000200U            /*!< Set global OUT NAK */
-#define USB_OTG_DCTL_CGONAK                  0x00000400U            /*!< Clear global OUT NAK */
-#define USB_OTG_DCTL_POPRGDNE                0x00000800U            /*!< Power-on programming done */
-
-/********************  Bit definition for USB_OTG_HFIR register  **************/
-#define USB_OTG_HFIR_FRIVL                   0x0000FFFFU            /*!< Frame interval */
-
-/********************  Bit definition for USB_OTG_HFNUM register  *************/
-#define USB_OTG_HFNUM_FRNUM                   0x0000FFFFU            /*!< Frame number */
-#define USB_OTG_HFNUM_FTREM                   0xFFFF0000U            /*!< Frame time remaining */
-
-/********************  Bit definition for USB_OTG_DSTS register  **************/
-#define USB_OTG_DSTS_SUSPSTS                 0x00000001U            /*!< Suspend status */
-
-#define USB_OTG_DSTS_ENUMSPD                 0x00000006U            /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_DSTS_ENUMSPD_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_DSTS_EERR                    0x00000008U            /*!< Erratic error */
-#define USB_OTG_DSTS_FNSOF                   0x003FFF00U            /*!< Frame number of the received SOF */
-
-/********************  Bit definition for USB_OTG_GAHBCFG register  ***********/
-#define USB_OTG_GAHBCFG_GINT                    0x00000001U            /*!< Global interrupt mask */
-#define USB_OTG_GAHBCFG_HBSTLEN                 0x0000001EU            /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_GAHBCFG_HBSTLEN_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_GAHBCFG_HBSTLEN_2               0x00000008U            /*!<Bit 2 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3               0x00000010U            /*!<Bit 3 */
-#define USB_OTG_GAHBCFG_DMAEN                   0x00000020U            /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL                 0x00000080U            /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL                0x00000100U            /*!< Periodic TxFIFO empty level */
-
-/********************  Bit definition for USB_OTG_GUSBCFG register  ***********/
-#define USB_OTG_GUSBCFG_TOCAL                   0x00000007U            /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TOCAL_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TOCAL_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_PHYSEL                  0x00000040U            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP                  0x00000100U            /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP                  0x00000200U            /*!< HNP-capable */
-
-#define USB_OTG_GUSBCFG_TRDT                    0x00003C00U            /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                  0x00000400U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TRDT_1                  0x00000800U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TRDT_2                  0x00001000U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_TRDT_3                  0x00002000U            /*!<Bit 3 */
-#define USB_OTG_GUSBCFG_PHYLPCS                 0x00008000U            /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS                0x00020000U            /*!< ULPI FS/LS select */
-#define USB_OTG_GUSBCFG_ULPIAR                  0x00040000U            /*!< ULPI Auto-resume */
-#define USB_OTG_GUSBCFG_ULPICSM                 0x00080000U            /*!< ULPI Clock SuspendM */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD              0x00100000U            /*!< ULPI External VBUS Drive */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI              0x00200000U            /*!< ULPI external VBUS indicator */
-#define USB_OTG_GUSBCFG_TSDPS                   0x00400000U            /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI                    0x00800000U            /*!< Indicator complement */
-#define USB_OTG_GUSBCFG_PTCI                    0x01000000U            /*!< Indicator pass through */
-#define USB_OTG_GUSBCFG_ULPIIPD                 0x02000000U            /*!< ULPI interface protect disable */
-#define USB_OTG_GUSBCFG_FHMOD                   0x20000000U            /*!< Forced host mode */
-#define USB_OTG_GUSBCFG_FDMOD                   0x40000000U            /*!< Forced peripheral mode */
-#define USB_OTG_GUSBCFG_CTXPKT                  0x80000000U            /*!< Corrupt Tx packet */
-
-/********************  Bit definition for USB_OTG_GRSTCTL register  ***********/
-#define USB_OTG_GRSTCTL_CSRST                   0x00000001U            /*!< Core soft reset */
-#define USB_OTG_GRSTCTL_HSRST                   0x00000002U            /*!< HCLK soft reset */
-#define USB_OTG_GRSTCTL_FCRST                   0x00000004U            /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH                 0x00000010U            /*!< RxFIFO flush */
-#define USB_OTG_GRSTCTL_TXFFLSH                 0x00000020U            /*!< TxFIFO flush */
-
-#define USB_OTG_GRSTCTL_TXFNUM                  0x000007C0U            /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                0x00000040U            /*!<Bit 0 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                0x00000080U            /*!<Bit 1 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                0x00000100U            /*!<Bit 2 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                0x00000200U            /*!<Bit 3 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                0x00000400U            /*!<Bit 4 */
-#define USB_OTG_GRSTCTL_DMAREQ                  0x40000000U            /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL                  0x80000000U            /*!< AHB master idle */
-
-/********************  Bit definition for USB_OTG_DIEPMSK register  ***********/
-#define USB_OTG_DIEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPMSK_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPMSK_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPMSK_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPMSK_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPMSK_BIM                     0x00000200U            /*!< BNA interrupt mask */
-
-/********************  Bit definition for USB_OTG_HPTXSTS register  ***********/
-#define USB_OTG_HPTXSTS_PTXFSAVL                0x0000FFFFU            /*!< Periodic transmit data FIFO space available */
-
-#define USB_OTG_HPTXSTS_PTXQSAV                 0x00FF0000U            /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0               0x00010000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1               0x00020000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2               0x00040000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3               0x00080000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4               0x00100000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5               0x00200000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6               0x00400000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7               0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_HPTXSTS_PTXQTOP                 0xFF000000U            /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0               0x01000000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1               0x02000000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2               0x04000000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3               0x08000000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4               0x10000000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5               0x20000000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6               0x40000000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7               0x80000000U            /*!<Bit 7 */
-
-/********************  Bit definition for USB_OTG_HAINT register  *************/
-#define USB_OTG_HAINT_HAINT                   0x0000FFFFU            /*!< Channel interrupts */
-
-/********************  Bit definition for USB_OTG_DOEPMSK register  ***********/
-#define USB_OTG_DOEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPMSK_STUPM                   0x00000008U            /*!< SETUP phase done mask */
-#define USB_OTG_DOEPMSK_OTEPDM                  0x00000010U            /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_OTEPSPRM                0x00000020U            /*!< Status Phase Received mask                     */
-#define USB_OTG_DOEPMSK_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received mask */
-#define USB_OTG_DOEPMSK_OPEM                    0x00000100U            /*!< OUT packet error mask */
-#define USB_OTG_DOEPMSK_BOIM                    0x00000200U            /*!< BNA interrupt mask */
-
-/********************  Bit definition for USB_OTG_GINTSTS register  ***********/
-#define USB_OTG_GINTSTS_CMOD                    0x00000001U            /*!< Current mode of operation                      */
-#define USB_OTG_GINTSTS_MMIS                    0x00000002U            /*!< Mode mismatch interrupt                        */
-#define USB_OTG_GINTSTS_OTGINT                  0x00000004U            /*!< OTG interrupt                                  */
-#define USB_OTG_GINTSTS_SOF                     0x00000008U            /*!< Start of frame                                 */
-#define USB_OTG_GINTSTS_RXFLVL                  0x00000010U            /*!< RxFIFO nonempty                                */
-#define USB_OTG_GINTSTS_NPTXFE                  0x00000020U            /*!< Nonperiodic TxFIFO empty                       */
-#define USB_OTG_GINTSTS_GINAKEFF                0x00000040U            /*!< Global IN nonperiodic NAK effective            */
-#define USB_OTG_GINTSTS_BOUTNAKEFF              0x00000080U            /*!< Global OUT NAK effective                       */
-#define USB_OTG_GINTSTS_ESUSP                   0x00000400U            /*!< Early suspend                                  */
-#define USB_OTG_GINTSTS_USBSUSP                 0x00000800U            /*!< USB suspend                                    */
-#define USB_OTG_GINTSTS_USBRST                  0x00001000U            /*!< USB reset                                      */
-#define USB_OTG_GINTSTS_ENUMDNE                 0x00002000U            /*!< Enumeration done                               */
-#define USB_OTG_GINTSTS_ISOODRP                 0x00004000U            /*!< Isochronous OUT packet dropped interrupt       */
-#define USB_OTG_GINTSTS_EOPF                    0x00008000U            /*!< End of periodic frame interrupt                */
-#define USB_OTG_GINTSTS_IEPINT                  0x00040000U            /*!< IN endpoint interrupt                          */
-#define USB_OTG_GINTSTS_OEPINT                  0x00080000U            /*!< OUT endpoint interrupt                         */
-#define USB_OTG_GINTSTS_IISOIXFR                0x00100000U            /*!< Incomplete isochronous IN transfer             */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       0x00200000U            /*!< Incomplete periodic transfer                   */
-#define USB_OTG_GINTSTS_DATAFSUSP               0x00400000U            /*!< Data fetch suspended                           */
-#define USB_OTG_GINTSTS_RSTDET                  0x00800000U            /*!< Reset detected interrupt                       */
-#define USB_OTG_GINTSTS_HPRTINT                 0x01000000U            /*!< Host port interrupt                            */
-#define USB_OTG_GINTSTS_HCINT                   0x02000000U            /*!< Host channels interrupt                        */
-#define USB_OTG_GINTSTS_PTXFE                   0x04000000U            /*!< Periodic TxFIFO empty                          */
-#define USB_OTG_GINTSTS_LPMINT                  0x08000000U            /*!< LPM interrupt                                  */
-#define USB_OTG_GINTSTS_CIDSCHG                 0x10000000U            /*!< Connector ID status change                     */
-#define USB_OTG_GINTSTS_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt                  */
-#define USB_OTG_GINTSTS_SRQINT                  0x40000000U            /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT                  0x80000000U            /*!< Resume/remote wakeup detected interrupt        */
-
-/********************  Bit definition for USB_OTG_GINTMSK register  ***********/
-#define USB_OTG_GINTMSK_MMISM                   0x00000002U         /*!< Mode mismatch interrupt mask */
-#define USB_OTG_GINTMSK_OTGINT                  0x00000004U         /*!< OTG interrupt mask */
-#define USB_OTG_GINTMSK_SOFM                    0x00000008U         /*!< Start of frame mask */
-#define USB_OTG_GINTMSK_RXFLVLM                 0x00000010U         /*!< Receive FIFO nonempty mask */
-#define USB_OTG_GINTMSK_NPTXFEM                 0x00000020U         /*!< Nonperiodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_GINAKEFFM               0x00000040U         /*!< Global nonperiodic IN NAK effective mask */
-#define USB_OTG_GINTMSK_GONAKEFFM               0x00000080U         /*!< Global OUT NAK effective mask */
-#define USB_OTG_GINTMSK_ESUSPM                  0x00000400U         /*!< Early suspend mask */
-#define USB_OTG_GINTMSK_USBSUSPM                0x00000800U         /*!< USB suspend mask */
-#define USB_OTG_GINTMSK_USBRST                  0x00001000U         /*!< USB reset mask */
-#define USB_OTG_GINTMSK_ENUMDNEM                0x00002000U         /*!< Enumeration done mask */
-#define USB_OTG_GINTMSK_ISOODRPM                0x00004000U         /*!< Isochronous OUT packet dropped interrupt mask */
-#define USB_OTG_GINTMSK_EOPFM                   0x00008000U         /*!< End of periodic frame interrupt mask */
-#define USB_OTG_GINTMSK_EPMISM                  0x00020000U         /*!< Endpoint mismatch interrupt mask */
-#define USB_OTG_GINTMSK_IEPINT                  0x00040000U         /*!< IN endpoints interrupt mask */
-#define USB_OTG_GINTMSK_OEPINT                  0x00080000U         /*!< OUT endpoints interrupt mask */
-#define USB_OTG_GINTMSK_IISOIXFRM               0x00100000U         /*!< Incomplete isochronous IN transfer mask */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         0x00200000U         /*!< Incomplete periodic transfer mask */
-#define USB_OTG_GINTMSK_FSUSPM                  0x00400000U         /*!< Data fetch suspended mask */
-#define USB_OTG_GINTMSK_RSTDETM                 0x00800000U         /*!< Reset detected interrupt mask */
-#define USB_OTG_GINTMSK_PRTIM                   0x01000000U         /*!< Host port interrupt mask */
-#define USB_OTG_GINTMSK_HCIM                    0x02000000U         /*!< Host channels interrupt mask */
-#define USB_OTG_GINTMSK_PTXFEM                  0x04000000U         /*!< Periodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_LPMINTM                 0x08000000U         /*!< LPM interrupt Mask */
-#define USB_OTG_GINTMSK_CIDSCHGM                0x10000000U         /*!< Connector ID status change mask */
-#define USB_OTG_GINTMSK_DISCINT                 0x20000000U         /*!< Disconnect detected interrupt mask */
-#define USB_OTG_GINTMSK_SRQIM                   0x40000000U         /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM                    0x80000000U         /*!< Resume/remote wakeup detected interrupt mask */
-
-/********************  Bit definition for USB_OTG_DAINT register  *************/
-#define USB_OTG_DAINT_IEPINT                  0x0000FFFFU            /*!< IN endpoint interrupt bits */
-#define USB_OTG_DAINT_OEPINT                  0xFFFF0000U            /*!< OUT endpoint interrupt bits */
-
-/********************  Bit definition for USB_OTG_HAINTMSK register  **********/
-#define USB_OTG_HAINTMSK_HAINTM                  0x0000FFFFU            /*!< Channel interrupt mask */
-
-/********************  Bit definition for USB_OTG_GRXSTSP register  ***********/
-#define USB_OTG_GRXSTSP_EPNUM                    0x0000000FU            /*!< IN EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_BCNT                     0x00007FF0U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID                     0x00018000U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS                   0x001E0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for USB_OTG_DAINTMSK register  **********/
-#define USB_OTG_DAINTMSK_IEPM                    0x0000FFFFU            /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM                    0xFFFF0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for OTG register  ***********************/
-
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition for OTG register  ***********************/
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition for USB_OTG_GRXFSIZ register  ***********/
-#define USB_OTG_GRXFSIZ_RXFD            0x0000FFFFU            /*!< RxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DVBUSDIS register  **********/
-#define USB_OTG_DVBUSDIS_VBUSDT         0x0000FFFFU            /*!< Device VBUS discharge time */
-
-/********************  Bit definition for OTG register  ***********************/
-#define USB_OTG_NPTXFSA                 0x0000FFFFU            /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD                  0xFFFF0000U            /*!< Nonperiodic TxFIFO depth */
-#define USB_OTG_TX0FSA                  0x0000FFFFU            /*!< Endpoint 0 transmit RAM start address */
-#define USB_OTG_TX0FD                   0xFFFF0000U            /*!< Endpoint 0 TxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DVBUSPULSE register  ********/
-#define USB_OTG_DVBUSPULSE_DVBUSP                  0x00000FFFU            /*!< Device VBUS pulsing time */
-
-/********************  Bit definition for USB_OTG_GNPTXSTS register  **********/
-#define USB_OTG_GNPTXSTS_NPTXFSAV                0x0000FFFFU            /*!< Nonperiodic TxFIFO space available */
-
-#define USB_OTG_GNPTXSTS_NPTQXSAV                0x00FF0000U            /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0              0x00010000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1              0x00020000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2              0x00040000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3              0x00080000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4              0x00100000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5              0x00200000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6              0x00400000U            /*!<Bit 6 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7              0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_GNPTXSTS_NPTXQTOP                0x7F000000U            /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0              0x01000000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1              0x02000000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2              0x04000000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3              0x08000000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4              0x10000000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5              0x20000000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6              0x40000000U            /*!<Bit 6 */
-
-/********************  Bit definition for USB_OTG_DTHRCTL register  ***********/
-#define USB_OTG_DTHRCTL_NONISOTHREN             0x00000001U            /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN                0x00000002U            /*!< ISO IN endpoint threshold enable */
-
-#define USB_OTG_DTHRCTL_TXTHRLEN                0x000007FCU            /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0              0x00000004U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1              0x00000008U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2              0x00000010U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3              0x00000020U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4              0x00000040U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5              0x00000080U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6              0x00000100U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7              0x00000200U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8              0x00000400U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_RXTHREN                 0x00010000U            /*!< Receive threshold enable */
-
-#define USB_OTG_DTHRCTL_RXTHRLEN                0x03FE0000U            /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0              0x00020000U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1              0x00040000U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2              0x00080000U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3              0x00100000U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4              0x00200000U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5              0x00400000U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6              0x00800000U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7              0x01000000U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8              0x02000000U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_ARPEN                   0x08000000U            /*!< Arbiter parking enable */
-
-/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM               0x0000FFFFU            /*!< IN EP Tx FIFO empty interrupt mask bits */
-
-/********************  Bit definition for USB_OTG_DEACHINT register  **********/
-#define USB_OTG_DEACHINT_IEP1INT                 0x00000002U            /*!< IN endpoint 1interrupt bit */
-#define USB_OTG_DEACHINT_OEP1INT                 0x00020000U            /*!< OUT endpoint 1 interrupt bit */
-
-/********************  Bit definition for USB_OTG_GCCFG register  *************/
-#define USB_OTG_GCCFG_DCDET                  0x00000001U              /*!< Data contact detection (DCD) status */
-#define USB_OTG_GCCFG_PDET                   0x00000002U              /*!< Primary detection (PD) status */
-#define USB_OTG_GCCFG_SDET                   0x00000004U              /*!< Secondary detection (SD) status */
-#define USB_OTG_GCCFG_PS2DET                 0x00000008U              /*!< DM pull-up detection status */
-#define USB_OTG_GCCFG_PWRDWN                 0x00010000U              /*!< Power down */
-#define USB_OTG_GCCFG_BCDEN                  0x00020000U              /*!< Battery charging detector (BCD) enable */
-#define USB_OTG_GCCFG_DCDEN                  0x00040000U              /*!< Data contact detection (DCD) mode enable*/
-#define USB_OTG_GCCFG_PDEN                   0x00080000U              /*!< Primary detection (PD) mode enable*/
-#define USB_OTG_GCCFG_SDEN                   0x00100000U              /*!< Secondary detection (SD) mode enable */
-#define USB_OTG_GCCFG_VBDEN                  0x00200000U              /*!< USB VBUS Detection Enable */
-
-/********************  Bit definition for USB_OTG_DEACHINTMSK register  *******/
-#define USB_OTG_DEACHINTMSK_IEP1INTM                0x00000002U            /*!< IN Endpoint 1 interrupt mask bit */
-#define USB_OTG_DEACHINTMSK_OEP1INTM                0x00020000U            /*!< OUT Endpoint 1 interrupt mask bit */
-
-/********************  Bit definition for USB_OTG_CID register  ***************/
-#define USB_OTG_CID_PRODUCT_ID              0xFFFFFFFFU               /*!< Product ID field */
-
-/********************  Bit definition for USB_OTG_GLPMCFG register  ***********/
-#define  USB_OTG_GLPMCFG_LPMEN               0x00000001U            /*!< LPM support enable                                     */
-#define  USB_OTG_GLPMCFG_LPMACK              0x00000002U            /*!< LPM Token acknowledge enable                           */
-#define  USB_OTG_GLPMCFG_BESL                0x0000003CU            /*!< BESL value received with last ACKed LPM Token          */
-#define  USB_OTG_GLPMCFG_REMWAKE             0x00000040U            /*!< bRemoteWake value received with last ACKed LPM Token   */
-#define  USB_OTG_GLPMCFG_L1SSEN              0x00000080U            /*!< L1 shallow sleep enable                                */
-#define  USB_OTG_GLPMCFG_BESLTHRS            0x00000F00U            /*!< BESL threshold                                         */
-#define  USB_OTG_GLPMCFG_L1DSEN              0x00001000U            /*!< L1 deep sleep enable                                   */
-#define  USB_OTG_GLPMCFG_LPMRSP              0x00006000U            /*!< LPM response                                           */
-#define  USB_OTG_GLPMCFG_SLPSTS              0x00008000U            /*!< Port sleep status                                      */
-#define  USB_OTG_GLPMCFG_L1RSMOK             0x00010000U            /*!< Sleep State Resume OK                                  */
-#define  USB_OTG_GLPMCFG_LPMCHIDX            0x001E0000U            /*!< LPM Channel Index                                      */
-#define  USB_OTG_GLPMCFG_LPMRCNT             0x00E00000U            /*!< LPM retry count                                        */
-#define  USB_OTG_GLPMCFG_SNDLPM              0x01000000U            /*!< Send LPM transaction                                   */
-#define  USB_OTG_GLPMCFG_LPMRCNTSTS          0x0E000000U            /*!< LPM retry count status                                 */
-#define  USB_OTG_GLPMCFG_ENBESL              0x10000000U            /*!< Enable best effort service latency                     */
-
-/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ******/
-#define USB_OTG_DIEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPEACHMSK1_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
-
-/********************  Bit definition for USB_OTG_HPRT register  **************/
-#define USB_OTG_HPRT_PCSTS                   0x00000001U            /*!< Port connect status */
-#define USB_OTG_HPRT_PCDET                   0x00000002U            /*!< Port connect detected */
-#define USB_OTG_HPRT_PENA                    0x00000004U            /*!< Port enable */
-#define USB_OTG_HPRT_PENCHNG                 0x00000008U            /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA                    0x00000010U            /*!< Port overcurrent active */
-#define USB_OTG_HPRT_POCCHNG                 0x00000020U            /*!< Port overcurrent change */
-#define USB_OTG_HPRT_PRES                    0x00000040U            /*!< Port resume */
-#define USB_OTG_HPRT_PSUSP                   0x00000080U            /*!< Port suspend */
-#define USB_OTG_HPRT_PRST                    0x00000100U            /*!< Port reset */
-
-#define USB_OTG_HPRT_PLSTS                   0x00000C00U            /*!< Port line status */
-#define USB_OTG_HPRT_PLSTS_0                 0x00000400U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PLSTS_1                 0x00000800U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PPWR                    0x00001000U            /*!< Port power */
-
-#define USB_OTG_HPRT_PTCTL                   0x0001E000U            /*!< Port test control */
-#define USB_OTG_HPRT_PTCTL_0                 0x00002000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PTCTL_1                 0x00004000U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PTCTL_2                 0x00008000U            /*!<Bit 2 */
-#define USB_OTG_HPRT_PTCTL_3                 0x00010000U            /*!<Bit 3 */
-
-#define USB_OTG_HPRT_PSPD                    0x00060000U            /*!< Port speed */
-#define USB_OTG_HPRT_PSPD_0                  0x00020000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PSPD_1                  0x00040000U            /*!<Bit 1 */
-
-/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ******/
-#define USB_OTG_DOEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DOEPEACHMSK1_TXFURM                  0x00000100U            /*!< OUT packet error mask */
-#define USB_OTG_DOEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_BERRM                   0x00001000U            /*!< Bubble error interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NYETM                   0x00004000U            /*!< NYET interrupt mask */
-
-/********************  Bit definition for USB_OTG_HPTXFSIZ register  **********/
-#define USB_OTG_HPTXFSIZ_PTXSA                   0x0000FFFFU            /*!< Host periodic TxFIFO start address */
-#define USB_OTG_HPTXFSIZ_PTXFD                   0xFFFF0000U            /*!< Host periodic TxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DIEPCTL register  ***********/
-#define USB_OTG_DIEPCTL_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
-#define USB_OTG_DIEPCTL_USBAEP                  0x00008000U            /*!< USB active endpoint */
-#define USB_OTG_DIEPCTL_EONUM_DPID              0x00010000U            /*!< Even/odd frame */
-#define USB_OTG_DIEPCTL_NAKSTS                  0x00020000U            /*!< NAK status */
-
-#define USB_OTG_DIEPCTL_EPTYP                   0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_DIEPCTL_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_STALL                   0x00200000U            /*!< STALL handshake */
-
-#define USB_OTG_DIEPCTL_TXFNUM                  0x03C00000U            /*!< TxFIFO number */
-#define USB_OTG_DIEPCTL_TXFNUM_0                0x00400000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                0x00800000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                0x01000000U            /*!<Bit 2 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                0x02000000U            /*!<Bit 3 */
-#define USB_OTG_DIEPCTL_CNAK                    0x04000000U            /*!< Clear NAK */
-#define USB_OTG_DIEPCTL_SNAK                    0x08000000U            /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          0x10000000U            /*!< Set DATA0 PID */
-#define USB_OTG_DIEPCTL_SODDFRM                 0x20000000U            /*!< Set odd frame */
-#define USB_OTG_DIEPCTL_EPDIS                   0x40000000U            /*!< Endpoint disable */
-#define USB_OTG_DIEPCTL_EPENA                   0x80000000U            /*!< Endpoint enable */
-
-/********************  Bit definition for USB_OTG_HCCHAR register  ************/
-#define USB_OTG_HCCHAR_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
-
-#define USB_OTG_HCCHAR_EPNUM                   0x00007800U            /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPNUM_1                 0x00001000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_EPNUM_2                 0x00002000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_EPNUM_3                 0x00004000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_EPDIR                   0x00008000U            /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV                   0x00020000U            /*!< Low-speed device */
-
-#define USB_OTG_HCCHAR_EPTYP                   0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_MC                      0x00300000U            /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                    0x00100000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_MC_1                    0x00200000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_DAD                     0x1FC00000U            /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                   0x00400000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_DAD_1                   0x00800000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_DAD_2                   0x01000000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_DAD_3                   0x02000000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_DAD_4                   0x04000000U            /*!<Bit 4 */
-#define USB_OTG_HCCHAR_DAD_5                   0x08000000U            /*!<Bit 5 */
-#define USB_OTG_HCCHAR_DAD_6                   0x10000000U            /*!<Bit 6 */
-#define USB_OTG_HCCHAR_ODDFRM                  0x20000000U            /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS                   0x40000000U            /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA                   0x80000000U            /*!< Channel enable */
-
-/********************  Bit definition for USB_OTG_HCSPLT register  ************/
-
-#define USB_OTG_HCSPLT_PRTADDR                 0x0000007FU            /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_PRTADDR_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_PRTADDR_2               0x00000004U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_PRTADDR_3               0x00000008U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_PRTADDR_4               0x00000010U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_PRTADDR_5               0x00000020U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_PRTADDR_6               0x00000040U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_HUBADDR                 0x00003F80U            /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0               0x00000080U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_HUBADDR_1               0x00000100U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_HUBADDR_2               0x00000200U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_HUBADDR_3               0x00000400U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_HUBADDR_4               0x00000800U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_HUBADDR_5               0x00001000U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_HUBADDR_6               0x00002000U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_XACTPOS                 0x0000C000U            /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0               0x00004000U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_XACTPOS_1               0x00008000U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_COMPLSPLT               0x00010000U            /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN                 0x80000000U            /*!< Split enable */
-
-/********************  Bit definition for USB_OTG_HCINT register  *************/
-#define USB_OTG_HCINT_XFRC                    0x00000001U            /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH                     0x00000002U            /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINT_STALL                   0x00000008U            /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK                     0x00000010U            /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK                     0x00000020U            /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET                    0x00000040U            /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR                   0x00000080U            /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR                   0x00000100U            /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR                   0x00000200U            /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR                   0x00000400U            /*!< Data toggle error */
-
-/********************  Bit definition for USB_OTG_DIEPINT register  ***********/
-#define USB_OTG_DIEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_TOC                     0x00000008U            /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE                  0x00000010U            /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNE                  0x00000040U            /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE                    0x00000080U            /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN              0x00000100U            /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA                     0x00000200U            /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS               0x00000800U            /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR                    0x00001000U            /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK                     0x00002000U            /*!< NAK interrupt */
-
-/********************  Bit definition for USB_OTG_HCINTMSK register  **********/
-#define USB_OTG_HCINTMSK_XFRCM                   0x00000001U            /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM                    0x00000002U            /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM                  0x00000008U            /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM                    0x00000010U            /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM                    0x00000020U            /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET                    0x00000040U            /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM                  0x00000080U            /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM                  0x00000100U            /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM                  0x00000200U            /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM                  0x00000400U            /*!< Data toggle error mask */
-
-/********************  Bit definition for USB_OTG_DIEPTSIZ register  **********/
-
-#define USB_OTG_DIEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT                  0x60000000U            /*!< Packet count */
-/********************  Bit definition for USB_OTG_HCTSIZ register  ************/
-#define USB_OTG_HCTSIZ_XFRSIZ                    0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT                    0x1FF80000U            /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING                    0x80000000U            /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID                      0x60000000U            /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                    0x20000000U            /*!<Bit 0 */
-#define USB_OTG_HCTSIZ_DPID_1                    0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition for USB_OTG_DIEPDMA register  ***********/
-#define USB_OTG_DIEPDMA_DMAADDR                  0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition for USB_OTG_HCDMA register  *************/
-#define USB_OTG_HCDMA_DMAADDR                    0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition for USB_OTG_DTXFSTS register  ***********/
-#define USB_OTG_DTXFSTS_INEPTFSAV                0x0000FFFFU            /*!< IN endpoint TxFIFO space available */
-
-/********************  Bit definition for USB_OTG_DIEPTXF register  ***********/
-#define USB_OTG_DIEPTXF_INEPTXSA                 0x0000FFFFU            /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD                 0xFFFF0000U            /*!< IN endpoint TxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DOEPCTL register  ***********/
-
-#define USB_OTG_DOEPCTL_MPSIZ                     0x000007FFU            /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP                    0x00008000U            /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS                    0x00020000U            /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            0x10000000U            /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM                   0x20000000U            /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP                     0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                   0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DOEPCTL_EPTYP_1                   0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_SNPM                      0x00100000U            /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL                     0x00200000U            /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK                      0x04000000U            /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK                      0x08000000U            /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS                     0x40000000U            /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA                     0x80000000U            /*!< Endpoint enable */
-
-/********************  Bit definition for USB_OTG_DOEPINT register  ***********/
-#define USB_OTG_DOEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_STUP                    0x00000008U            /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS                 0x00000010U            /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_OTEPSPR                 0x00000020U            /*!< Status Phase Received For Control Write */
-#define USB_OTG_DOEPINT_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_NYET                    0x00004000U            /*!< NYET interrupt */
-
-/********************  Bit definition for USB_OTG_DOEPTSIZ register  **********/
-
-#define USB_OTG_DOEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-
-#define USB_OTG_DOEPTSIZ_STUPCNT                 0x60000000U            /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0               0x20000000U            /*!<Bit 0 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1               0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition for PCGCCTL register  *******************/
-#define USB_OTG_PCGCCTL_STOPCLK                 0x00000001U            /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK                 0x00000002U            /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP                 0x00000010U            /*!<Bit 1 */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
- 
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-
-/******************************* CAN Instances ********************************/
-#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
-                                       ((INSTANCE) == CAN2))
-/****************************** DFSDM Instances *******************************/
-#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
-                                                ((INSTANCE) == DFSDM1_Filter1))
-
-#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
-                                                 ((INSTANCE) == DFSDM1_Channel1) || \
-                                                 ((INSTANCE) == DFSDM1_Channel2) || \
-                                                 ((INSTANCE) == DFSDM1_Channel3))
-
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************** DMA Instances *******************************/
-#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
-                                              ((INSTANCE) == DMA1_Stream1) || \
-                                              ((INSTANCE) == DMA1_Stream2) || \
-                                              ((INSTANCE) == DMA1_Stream3) || \
-                                              ((INSTANCE) == DMA1_Stream4) || \
-                                              ((INSTANCE) == DMA1_Stream5) || \
-                                              ((INSTANCE) == DMA1_Stream6) || \
-                                              ((INSTANCE) == DMA1_Stream7) || \
-                                              ((INSTANCE) == DMA2_Stream0) || \
-                                              ((INSTANCE) == DMA2_Stream1) || \
-                                              ((INSTANCE) == DMA2_Stream2) || \
-                                              ((INSTANCE) == DMA2_Stream3) || \
-                                              ((INSTANCE) == DMA2_Stream4) || \
-                                              ((INSTANCE) == DMA2_Stream5) || \
-                                              ((INSTANCE) == DMA2_Stream6) || \
-                                              ((INSTANCE) == DMA2_Stream7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOF) || \
-                                        ((INSTANCE) == GPIOG) || \
-                                        ((INSTANCE) == GPIOH))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2) || \
-                                       ((INSTANCE) == I2C3))
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI1) || \
-                                    ((INSTANCE) == SPI2) || \
-                                    ((INSTANCE) == SPI3) || \
-                                    ((INSTANCE) == SPI4) || \
-                                    ((INSTANCE) == SPI5))
-
-/*************************** I2S Extended Instances ***************************/
-#define IS_I2S_ALL_INSTANCE_EXT(PERIPH)  (((INSTANCE) == SPI2)    || \
-                                          ((INSTANCE) == SPI3)    || \
-                                          ((INSTANCE) == I2S2ext) || \
-                                          ((INSTANCE) == I2S3ext))
-
-/******************************* RNG Instances ********************************/
-#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3) || \
-                                       ((INSTANCE) == SPI4) || \
-                                       ((INSTANCE) == SPI5))
-/*************************** SPI Extended Instances ***************************/
-#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1)    || \
-                                           ((INSTANCE) == SPI2)    || \
-                                           ((INSTANCE) == SPI3)    || \
-                                           ((INSTANCE) == SPI4)    || \
-                                           ((INSTANCE) == SPI5)    || \
-                                           ((INSTANCE) == I2S2ext) || \
-                                           ((INSTANCE) == I2S3ext))
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
-                                   ((INSTANCE) == TIM2)   || \
-                                   ((INSTANCE) == TIM3)   || \
-                                   ((INSTANCE) == TIM4)   || \
-                                   ((INSTANCE) == TIM5)   || \
-                                   ((INSTANCE) == TIM6)   || \
-                                   ((INSTANCE) == TIM7)   || \
-                                   ((INSTANCE) == TIM8)   || \
-                                   ((INSTANCE) == TIM9)   || \
-                                   ((INSTANCE) == TIM10)  || \
-                                   ((INSTANCE) == TIM11)  || \
-                                   ((INSTANCE) == TIM12)  || \
-                                   ((INSTANCE) == TIM13)  || \
-                                   ((INSTANCE) == TIM14))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
-                                         ((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM8)  || \
-                                         ((INSTANCE) == TIM9)  || \
-                                         ((INSTANCE) == TIM10) || \
-                                         ((INSTANCE) == TIM11) || \
-                                         ((INSTANCE) == TIM12) || \
-                                         ((INSTANCE) == TIM13) || \
-                                         ((INSTANCE) == TIM14))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM8) || \
-                                       ((INSTANCE) == TIM9) || \
-                                       ((INSTANCE) == TIM12))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8))
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM8))
-
-/******************** TIM Instances : Advanced-control timers *****************/
-#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                            ((INSTANCE) == TIM8))
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8))
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM6) || \
-                                       ((INSTANCE) == TIM7) || \
-                                       ((INSTANCE) == TIM8))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM8))
-
-/************ TIM Instances : DMA requests generation (COMDE) *****************/
-#define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM8)) 
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                             ((INSTANCE) == TIM2) || \
-                                             ((INSTANCE) == TIM3) || \
-                                             ((INSTANCE) == TIM4) || \
-                                             ((INSTANCE) == TIM5) || \
-                                             ((INSTANCE) == TIM8))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM6) || \
-                                          ((INSTANCE) == TIM7) || \
-                                          ((INSTANCE) == TIM8) || \
-                                          ((INSTANCE) == TIM9) || \
-                                          ((INSTANCE) == TIM12))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8) || \
-                                         ((INSTANCE) == TIM9) || \
-                                         ((INSTANCE) == TIM12))
-
-/********************** TIM Instances : 32 bit Counter ************************/
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
-                                              ((INSTANCE) == TIM5))
-
-/***************** TIM Instances : external trigger input available ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                        ((INSTANCE) == TIM2) || \
-                                        ((INSTANCE) == TIM3) || \
-                                        ((INSTANCE) == TIM4) || \
-                                        ((INSTANCE) == TIM5) || \
-                                        ((INSTANCE) == TIM8))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM11))
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM1) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM5) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM8) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM12) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM13) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM14) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-/************ TIM Instances : complementary output(s) available ***************/
-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
-   ((((INSTANCE) == TIM1) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3)))            \
-    ||                                          \
-    (((INSTANCE) == TIM8) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3))))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3) || \
-                                     ((INSTANCE) == USART6))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == USART6))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3))
-
-/********************* UART Instances : Smart card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3) || \
-                                         ((INSTANCE) == USART6))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == USART6))
-
-/*********************** PCD Instances ****************************************/
-#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
-
-/*********************** HCD Instances ****************************************/
-#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/****************************** QSPI Instances ********************************/
-#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
-
-/***************************** FMPI2C Instances *******************************/
-#define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
-
-/****************************** SDIO Instances ********************************/
-#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
-
-/****************************** USB Instances ********************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
-
-/****************************** USB Exported Constants ************************/
-#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                12U
-#define USB_OTG_FS_MAX_IN_ENDPOINTS                    6U    /* Including EP0 */
-#define USB_OTG_FS_MAX_OUT_ENDPOINTS                   6U    /* Including EP0 */
-#define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32F412Vx_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/cmsis/stm32f412zx.h b/stmhal/cmsis/stm32f412zx.h
deleted file mode 100644
index 7cb25baa36..0000000000
--- a/stmhal/cmsis/stm32f412zx.h
+++ /dev/null
@@ -1,7394 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f412zx.h
-  * @author  MCD Application Team
-  * @version V2.5.1
-  * @date    28-June-2016
-  * @brief   CMSIS STM32F412Zx Device Peripheral Access Layer Header File. 
-  *
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - peripherals registers declarations and bits definition
-  *           - Macros to access peripheral’s registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f412zx
-  * @{
-  */
-    
-#ifndef __STM32F412Zx_H
-#define __STM32F412Zx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-  
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-
-/**
-  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
-  */
-#define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */
-#define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */
-#define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1U       /*!< FPU present                                   */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32F4XX Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-typedef enum
-{
-/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
-  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
-/******  STM32 specific Interrupt Numbers **********************************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
-  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
-  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
-  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
-  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
-  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
-  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
-  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
-  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
-  ADC_IRQn                    = 18,     /*!< ADC1 global Interrupts                                            */
-  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
-  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
-  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
-  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
-  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
-  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
-  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
-  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */
-  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
-  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
-  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
-  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
-  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
-  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
-  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
-  TIM6_IRQn                   = 54,     /*!< TIM6 global interrupt                                             */
-  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
-  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
-  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
-  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
-  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
-  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
-  DFSDM1_FLT0_IRQn            = 61,     /*!< DFSDM1 Filter 0 global Interrupt                                  */
-  DFSDM1_FLT1_IRQn            = 62,     /*!< DFSDM1 Filter 1 global Interrupt                                  */
-  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
-  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
-  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
-  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
-  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
-  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
-  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
-  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
-  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
-  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
-  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
-  RNG_IRQn                    = 80,     /*!< RNG global Interrupt                                              */
-  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
-  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
-  SPI5_IRQn                   = 85,      /*!< SPI5 global Interrupt                                            */
-  QUADSPI_IRQn                = 92,     /*!< QuadSPI global Interrupt                                          */
-  FMPI2C1_EV_IRQn             = 95,     /*!< FMPI2C1 Event Interrupt                                           */
-  FMPI2C1_ER_IRQn             = 96      /*!< FMPI2C1 Error Interrupt                                           */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
-#include "system_stm32f4xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */
-  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
-  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
-  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
-  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
-  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
-  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
-  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
-  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
-  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
-  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
-  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
-  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
-  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
-  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
-  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
-                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief Controller Area Network TxMailBox 
-  */
-
-typedef struct
-{
-  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
-  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
-  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
-  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
-} CAN_TxMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FIFOMailBox 
-  */
-  
-typedef struct
-{
-  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
-  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
-  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
-  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
-} CAN_FIFOMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FilterRegister 
-  */
-  
-typedef struct
-{
-  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
-  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
-} CAN_FilterRegister_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
-  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
-  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
-  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
-  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
-  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
-  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
-  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
-  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
-  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
-  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
-  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
-  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
-  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
-  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
-  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
-  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
-  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
-  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
-  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
-  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */ 
-  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
-} CAN_TypeDef;
-
-/** 
-  * @brief CRC calculation unit 
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
-  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */
-  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
-  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
-  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
-}CRC_TypeDef;
-
-/**
-  * @brief DFSDM module registers
-  */
-typedef struct
-{
-  __IO uint32_t FLTCR1;      /*!< DFSDM control register1,                          Address offset: 0x100 */
-  __IO uint32_t FLTCR2;      /*!< DFSDM control register2,                          Address offset: 0x104 */
-  __IO uint32_t FLTISR;      /*!< DFSDM interrupt and status register,              Address offset: 0x108 */
-  __IO uint32_t FLTICR;      /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */
-  __IO uint32_t FLTJCHGR;    /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */
-  __IO uint32_t FLTFCR;      /*!< DFSDM filter control register,                    Address offset: 0x114 */
-  __IO uint32_t FLTJDATAR;   /*!< DFSDM data register for injected group,           Address offset: 0x118 */
-  __IO uint32_t FLTRDATAR;   /*!< DFSDM data register for regular group,            Address offset: 0x11C */
-  __IO uint32_t FLTAWHTR;    /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */
-  __IO uint32_t FLTAWLTR;    /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */
-  __IO uint32_t FLTAWSR;     /*!< DFSDM analog watchdog status register             Address offset: 0x128 */
-  __IO uint32_t FLTAWCFR;    /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */
-  __IO uint32_t FLTEXMAX;    /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */
-  __IO uint32_t FLTEXMIN;    /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */
-  __IO uint32_t FLTCNVTIMR;  /*!< DFSDM conversion timer,                           Address offset: 0x138 */
-} DFSDM_Filter_TypeDef;
-
-/**
-  * @brief DFSDM channel configuration registers
-  */
-typedef struct
-{
-  __IO uint32_t CHCFGR1;     /*!< DFSDM channel configuration register1,            Address offset: 0x00 */
-  __IO uint32_t CHCFGR2;     /*!< DFSDM channel configuration register2,            Address offset: 0x04 */
-  __IO uint32_t CHAWSCDR;    /*!< DFSDM channel analog watchdog and
-                                  short circuit detector register,                  Address offset: 0x08 */
-  __IO uint32_t CHWDATAR;    /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */
-  __IO uint32_t CHDATINR;    /*!< DFSDM channel data input register,                Address offset: 0x10 */
-} DFSDM_Channel_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-typedef struct
-{
-  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
-  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
-  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
-  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
-  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
-  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
-  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
-  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
-  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
-} DMA_Stream_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
-  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
-  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
-  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
-} DMA_TypeDef;
-
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
-  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
-  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
-  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
-  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
-  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-
-typedef struct
-{
-  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */
-  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */
-  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */
-  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */
-  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */
-  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief Flexible Memory Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */   
-} FSMC_Bank1_TypeDef; 
-
-/** 
-  * @brief Flexible Memory Controller Bank1E
-  */
-  
-typedef struct
-{
-  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
-} FSMC_Bank1E_TypeDef;
-
-/** 
-  * @brief General Purpose I/O
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
-  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
-  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
-  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
-  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
-  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
-  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
-  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/** 
-  * @brief System configuration controller
-  */
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */ 
-  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
-  uint32_t      RESERVED1[2]; /*!< Reserved, 0x24-0x28                                                          */ 
-  __IO uint32_t CFGR;         /*!< SYSCFG Configuration register,                     Address offset: 0x2C      */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */
-  __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */
-  __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */
-  __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */
-  __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */
-  __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
-  __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
-  __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
-  __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */
-} I2C_TypeDef;
-
-/**
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< FMPI2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< FMPI2C Control register 2,            Address offset: 0x04 */
-  __IO uint32_t OAR1;        /*!< FMPI2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;        /*!< FMPI2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;     /*!< FMPI2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR;    /*!< FMPI2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;         /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;         /*!< FMPI2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;        /*!< FMPI2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;        /*!< FMPI2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;        /*!< FMPI2C Transmit data register,        Address offset: 0x28 */
-} FMPI2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
-  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
-  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
-  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
-  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
-  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
-  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
-  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
-  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
-  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
-  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
-  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
-  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
-  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
-  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
-  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
-  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
-  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
-  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
-  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
-  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
-  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
-  uint32_t      RESERVED7;     /*!< Reserved, 0x84                                                                    */
-  __IO uint32_t DCKCFGR;       /*!< RCC Dedicated Clocks configuration register,                 Address offset: 0x8C */
-  __IO uint32_t CKGATENR;       /*!< RCC Clocks Gated ENable Register,                           Address offset: 0x90 */
-  __IO uint32_t DCKCFGR2;      /*!< RCC Dedicated Clocks configuration register 2,               Address offset: 0x94 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-
-typedef struct
-{
-  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
-  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
-  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
-  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
-  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
-  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
-  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */
-  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
-  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */
-  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
-  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */
-  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */
-  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */
-  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */
-  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
-  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */
-  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
-  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
-  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
-  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
-  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
-  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
-  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
-  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
-  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
-  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
-  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
-  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
-  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
-  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
-  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
-  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
-  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
-  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
-  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
-  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
-  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
-} RTC_TypeDef;
-
-
-/** 
-  * @brief SD host Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t POWER;          /*!< SDIO power control register,    Address offset: 0x00 */
-  __IO uint32_t CLKCR;          /*!< SDI clock control register,     Address offset: 0x04 */
-  __IO uint32_t ARG;            /*!< SDIO argument register,         Address offset: 0x08 */
-  __IO uint32_t CMD;            /*!< SDIO command register,          Address offset: 0x0C */
-  __I uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */
-  __I uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */
-  __I uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */
-  __I uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */
-  __I uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */
-  __IO uint32_t DTIMER;         /*!< SDIO data timer register,       Address offset: 0x24 */
-  __IO uint32_t DLEN;           /*!< SDIO data length register,      Address offset: 0x28 */
-  __IO uint32_t DCTRL;          /*!< SDIO data control register,     Address offset: 0x2C */
-  __I uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */
-  __I uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */
-  __IO uint32_t ICR;            /*!< SDIO interrupt clear register,  Address offset: 0x38 */
-  __IO uint32_t MASK;           /*!< SDIO mask register,             Address offset: 0x3C */
-  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
-  __I uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */
-  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
-  __IO uint32_t FIFO;           /*!< SDIO data FIFO register,        Address offset: 0x80 */
-} SDIO_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief QUAD Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */
-  __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
-  __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */
-  __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
-  __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
-  __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
-  __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */
-  __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
-  __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */
-  __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
-  __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */                  
-  __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
-  __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */    
-} QUADSPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
-  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
-  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
-  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-
-/** 
-  * @brief RNG
-  */
-  
-typedef struct 
-{
-  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
-  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
-  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
-} RNG_TypeDef;
-
-
-/** 
-  * @brief USB_OTG_Core_Registers
-  */
-typedef struct
-{
-  __IO uint32_t GOTGCTL;              /*!<  USB_OTG Control and Status Register            000h*/
-  __IO uint32_t GOTGINT;              /*!<  USB_OTG Interrupt Register                     004h*/
-  __IO uint32_t GAHBCFG;              /*!<  Core AHB Configuration Register                008h*/
-  __IO uint32_t GUSBCFG;              /*!<  Core USB Configuration Register                00Ch*/
-  __IO uint32_t GRSTCTL;              /*!<  Core Reset Register                            010h*/
-  __IO uint32_t GINTSTS;              /*!<  Core Interrupt Register                        014h*/
-  __IO uint32_t GINTMSK;              /*!<  Core Interrupt Mask Register                   018h*/
-  __IO uint32_t GRXSTSR;              /*!<  Receive Sts Q Read Register                    01Ch*/
-  __IO uint32_t GRXSTSP;              /*!<  Receive Sts Q Read & POP Register              020h*/
-  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                      024h*/
-  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!<  EP0 / Non Periodic Tx FIFO Size Register       028h*/
-  __IO uint32_t HNPTXSTS;             /*!<  Non Periodic Tx FIFO/Queue Sts reg             02Ch*/
-  uint32_t Reserved30[2];             /*!< Reserved                                        030h*/
-  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                     038h*/
-  __IO uint32_t CID;                  /*!< User ID Register                                03Ch*/
-  uint32_t  Reserved5[3];             /*!< Reserved                                        040h-048h*/
-  __IO uint32_t GHWCFG3;              /*!< User HW config3                                 04Ch*/
-  uint32_t  Reserved6;                /*!< Reserved                                        050h*/ 
-  __IO uint32_t GLPMCFG;              /*!< LPM Register                                    054h*/
-  uint32_t  Reserved;                 /*!< Reserved                                        058h */
-  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register                  05Ch */
-  uint32_t  Reserved43[40];           /*!< Reserved                                        058h-0FFh */
-  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg                  100h*/
-  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */
-} USB_OTG_GlobalTypeDef;
-
-
-/** 
-  * @brief USB_OTG_device_Registers
-  */
-typedef struct 
-{
-  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */
-  __IO uint32_t DCTL;            /*!< dev Control Register         804h */
-  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */
-  uint32_t Reserved0C;           /*!< Reserved                     80Ch */
-  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */
-  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */
-  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */
-  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */
-  uint32_t  Reserved20;          /*!< Reserved                     820h */
-  uint32_t Reserved9;            /*!< Reserved                     824h */
-  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */
-  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */
-  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */
-  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */
-  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */
-  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */
-  uint32_t Reserved40;           /*!< dedicated EP mask            840h */
-  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */
-  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */
-  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */
-} USB_OTG_DeviceTypeDef;
-
-
-/** 
-  * @brief USB_OTG_IN_Endpoint-Specific_Register
-  */
-typedef struct 
-{
-  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */
-  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */
-  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */
-  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */
-  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */
-  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */
-  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
-  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
-} USB_OTG_INEndpointTypeDef;
-
-
-/** 
-  * @brief USB_OTG_OUT_Endpoint-Specific_Registers
-  */
-typedef struct 
-{
-  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */
-  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */
-  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */
-  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */
-  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */
-  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */
-  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
-} USB_OTG_OUTEndpointTypeDef;
-
-
-/** 
-  * @brief USB_OTG_Host_Mode_Register_Structures
-  */
-typedef struct 
-{
-  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */
-  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */
-  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */
-  uint32_t Reserved40C;           /*!< Reserved                             40Ch */
-  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */
-  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */
-  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */
-} USB_OTG_HostTypeDef;
-
-
-/** 
-  * @brief USB_OTG_Host_Channel_Specific_Registers
-  */
-typedef struct
-{
-  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */
-  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */
-  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */
-  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */
-  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */
-  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */
-  uint32_t Reserved[2];           /*!< Reserved                                      */
-} USB_OTG_HostChannelTypeDef;
-
-    
-/** 
-  * @brief Peripheral_memory_map
-  */
-#define FLASH_BASE            0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region                         */
-#define SRAM1_BASE            0x20000000U /*!< SRAM1(256 KB) base address in the alias region                             */
-#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region                                */
-#define FSMC_R_BASE           0xA0000000U /*!< FSMC registers base address                                                */
-#define QSPI_R_BASE           0xA0001000U /*!< QuadSPI registers base address                                             */
-
-#define SRAM1_BB_BASE         0x22000000U /*!< SRAM1(256 KB) base address in the bit-band region                             */
-#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region                                */
-#define FLASH_END             0x080FFFFFU /*!< FLASH end address                                                             */
-
-/* Legacy defines */
-#define SRAM_BASE             SRAM1_BASE
-#define SRAM_BB_BASE          SRAM1_BB_BASE
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000U)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)
-#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800U)
-#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00U)
-#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000U)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)
-#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400U)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)
-#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000U)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800U)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)
-#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)
-#define FMPI2C1_BASE          (APB1PERIPH_BASE + 0x6000U)
-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)
-#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800U)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)
-
-/*!< APB2 peripherals */
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000U)
-#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400U)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x1000U)
-#define USART6_BASE           (APB2PERIPH_BASE + 0x1400U)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000U)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x2300U)
-#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00U)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)
-#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400U)
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800U)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00U)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000U)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400U)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800U)
-#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000U)
-#define DFSDM1_BASE           (APB2PERIPH_BASE + 0x6000U)
-#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00U)
-#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20U)
-#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40U)
-#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60U)
-#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100U)
-#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180U)
-
-/*!< AHB1 peripherals */
-#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000U)
-#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400U)
-#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800U)
-#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00U)
-#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000U)
-#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400U)
-#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800U)
-#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00U)
-#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)
-#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800U)
-#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00U)
-#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000U)
-#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010U)
-#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028U)
-#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040U)
-#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058U)
-#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070U)
-#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088U)
-#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0U)
-#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8U)
-#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400U)
-#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010U)
-#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028U)
-#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040U)
-#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058U)
-#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070U)
-#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088U)
-#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0U)
-#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)
-
-/*!< AHB2 peripherals */
-#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800U)
-
-/*!< FSMC Bankx registers base address */
-#define FSMC_Bank1_R_BASE      (FSMC_R_BASE + 0x0000U)
-#define FSMC_Bank1E_R_BASE     (FSMC_R_BASE + 0x0104U)
-
-/* Debug MCU registers base address */
-#define DBGMCU_BASE           0xE0042000U
-
-/*!< USB registers base address */
-#define USB_OTG_FS_PERIPH_BASE               0x50000000U
-
-#define USB_OTG_GLOBAL_BASE                  0x000U
-#define USB_OTG_DEVICE_BASE                  0x800U
-#define USB_OTG_IN_ENDPOINT_BASE             0x900U
-#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U
-#define USB_OTG_EP_REG_SIZE                  0x20U
-#define USB_OTG_HOST_BASE                    0x400U
-#define USB_OTG_HOST_PORT_BASE               0x440U
-#define USB_OTG_HOST_CHANNEL_BASE            0x500U
-#define USB_OTG_HOST_CHANNEL_SIZE            0x20U
-#define USB_OTG_PCGCCTL_BASE                 0xE00U
-#define USB_OTG_FIFO_BASE                    0x1000U
-#define USB_OTG_FIFO_SIZE                    0x1000U
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
-#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
-#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
-#define FMPI2C1             ((FMPI2C_TypeDef *) FMPI2C1_BASE)
-#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
-#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
-#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define USART6              ((USART_TypeDef *) USART6_BASE)
-#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define SPI4                ((SPI_TypeDef *) SPI4_BASE)
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-#define SPI5                ((SPI_TypeDef *) SPI5_BASE)
-#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
-#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
-#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
-#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
-#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
-#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
-#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
-#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
-#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
-#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
-#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
-#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
-#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
-#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
-#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
-#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
-#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
-#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
-#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
-#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
-#define RNG                 ((RNG_TypeDef *) RNG_BASE)
-#define FSMC_Bank1           ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
-#define FSMC_Bank1E          ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
-#define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)
-
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers_Bits_Definition               */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Analog to Digital Converter                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          0x00000001U       /*!<Analog watchdog flag */
-#define  ADC_SR_EOC                          0x00000002U       /*!<End of conversion */
-#define  ADC_SR_JEOC                         0x00000004U       /*!<Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        0x00000008U       /*!<Injected channel Start flag */
-#define  ADC_SR_STRT                         0x00000010U       /*!<Regular channel Start flag */
-#define  ADC_SR_OVR                          0x00000020U       /*!<Overrun flag */
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
-#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels */
-#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels */
-#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution) */
-#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
-  
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion */
-#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode */
-#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC) */
-#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection */
-#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment */
-#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      0xFFFFU            /*!<Injected data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag */
-#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion */
-#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag */
-#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag */
-#define  ADC_CSR_DOVR1                       0x00000020U        /*!<ADC1 DMA overrun  flag */
-#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag */
-#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion */
-#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag */
-#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag */
-#define  ADC_CSR_DOVR2                       0x00002000U        /*!<ADC2 DMA overrun  flag */
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
-#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
-#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
-#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
-#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
-
-/*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                      0x0000FFFFU         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                      0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Controller Area Network                            */
-/*                                                                            */
-/******************************************************************************/
-/*!<CAN control and status registers */
-/*******************  Bit definition for CAN_MCR register  ********************/
-#define  CAN_MCR_INRQ                        0x00000001U        /*!<Initialization Request */
-#define  CAN_MCR_SLEEP                       0x00000002U        /*!<Sleep Mode Request */
-#define  CAN_MCR_TXFP                        0x00000004U        /*!<Transmit FIFO Priority */
-#define  CAN_MCR_RFLM                        0x00000008U        /*!<Receive FIFO Locked Mode */
-#define  CAN_MCR_NART                        0x00000010U        /*!<No Automatic Retransmission */
-#define  CAN_MCR_AWUM                        0x00000020U        /*!<Automatic Wakeup Mode */
-#define  CAN_MCR_ABOM                        0x00000040U        /*!<Automatic Bus-Off Management */
-#define  CAN_MCR_TTCM                        0x00000080U        /*!<Time Triggered Communication Mode */
-#define  CAN_MCR_RESET                       0x00008000U        /*!<bxCAN software master reset */
-#define  CAN_MCR_DBF                         0x00010000U        /*!<bxCAN Debug freeze */
-/*******************  Bit definition for CAN_MSR register  ********************/
-#define  CAN_MSR_INAK                        0x0001U            /*!<Initialization Acknowledge */
-#define  CAN_MSR_SLAK                        0x0002U            /*!<Sleep Acknowledge */
-#define  CAN_MSR_ERRI                        0x0004U            /*!<Error Interrupt */
-#define  CAN_MSR_WKUI                        0x0008U            /*!<Wakeup Interrupt */
-#define  CAN_MSR_SLAKI                       0x0010U            /*!<Sleep Acknowledge Interrupt */
-#define  CAN_MSR_TXM                         0x0100U            /*!<Transmit Mode */
-#define  CAN_MSR_RXM                         0x0200U            /*!<Receive Mode */
-#define  CAN_MSR_SAMP                        0x0400U            /*!<Last Sample Point */
-#define  CAN_MSR_RX                          0x0800U            /*!<CAN Rx Signal */
-
-/*******************  Bit definition for CAN_TSR register  ********************/
-#define  CAN_TSR_RQCP0                       0x00000001U        /*!<Request Completed Mailbox0 */
-#define  CAN_TSR_TXOK0                       0x00000002U        /*!<Transmission OK of Mailbox0 */
-#define  CAN_TSR_ALST0                       0x00000004U        /*!<Arbitration Lost for Mailbox0 */
-#define  CAN_TSR_TERR0                       0x00000008U        /*!<Transmission Error of Mailbox0 */
-#define  CAN_TSR_ABRQ0                       0x00000080U        /*!<Abort Request for Mailbox0 */
-#define  CAN_TSR_RQCP1                       0x00000100U        /*!<Request Completed Mailbox1 */
-#define  CAN_TSR_TXOK1                       0x00000200U        /*!<Transmission OK of Mailbox1 */
-#define  CAN_TSR_ALST1                       0x00000400U        /*!<Arbitration Lost for Mailbox1 */
-#define  CAN_TSR_TERR1                       0x00000800U        /*!<Transmission Error of Mailbox1 */
-#define  CAN_TSR_ABRQ1                       0x00008000U        /*!<Abort Request for Mailbox 1 */
-#define  CAN_TSR_RQCP2                       0x00010000U        /*!<Request Completed Mailbox2 */
-#define  CAN_TSR_TXOK2                       0x00020000U        /*!<Transmission OK of Mailbox 2 */
-#define  CAN_TSR_ALST2                       0x00040000U        /*!<Arbitration Lost for mailbox 2 */
-#define  CAN_TSR_TERR2                       0x00080000U        /*!<Transmission Error of Mailbox 2 */
-#define  CAN_TSR_ABRQ2                       0x00800000U        /*!<Abort Request for Mailbox 2 */
-#define  CAN_TSR_CODE                        0x03000000U        /*!<Mailbox Code */
-
-#define  CAN_TSR_TME                         0x1C000000U        /*!<TME[2:0] bits */
-#define  CAN_TSR_TME0                        0x04000000U        /*!<Transmit Mailbox 0 Empty */
-#define  CAN_TSR_TME1                        0x08000000U        /*!<Transmit Mailbox 1 Empty */
-#define  CAN_TSR_TME2                        0x10000000U        /*!<Transmit Mailbox 2 Empty */
-
-#define  CAN_TSR_LOW                         0xE0000000U        /*!<LOW[2:0] bits */
-#define  CAN_TSR_LOW0                        0x20000000U        /*!<Lowest Priority Flag for Mailbox 0 */
-#define  CAN_TSR_LOW1                        0x40000000U        /*!<Lowest Priority Flag for Mailbox 1 */
-#define  CAN_TSR_LOW2                        0x80000000U        /*!<Lowest Priority Flag for Mailbox 2 */
-
-/*******************  Bit definition for CAN_RF0R register  *******************/
-#define  CAN_RF0R_FMP0                       0x03U               /*!<FIFO 0 Message Pending */
-#define  CAN_RF0R_FULL0                      0x08U               /*!<FIFO 0 Full */
-#define  CAN_RF0R_FOVR0                      0x10U               /*!<FIFO 0 Overrun */
-#define  CAN_RF0R_RFOM0                      0x20U               /*!<Release FIFO 0 Output Mailbox */
-
-/*******************  Bit definition for CAN_RF1R register  *******************/
-#define  CAN_RF1R_FMP1                       0x03U               /*!<FIFO 1 Message Pending */
-#define  CAN_RF1R_FULL1                      0x08U               /*!<FIFO 1 Full */
-#define  CAN_RF1R_FOVR1                      0x10U               /*!<FIFO 1 Overrun */
-#define  CAN_RF1R_RFOM1                      0x20U               /*!<Release FIFO 1 Output Mailbox */
-
-/********************  Bit definition for CAN_IER register  *******************/
-#define  CAN_IER_TMEIE                       0x00000001U        /*!<Transmit Mailbox Empty Interrupt Enable */
-#define  CAN_IER_FMPIE0                      0x00000002U        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE0                       0x00000004U        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE0                      0x00000008U        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_FMPIE1                      0x00000010U        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE1                       0x00000020U        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE1                      0x00000040U        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error Warning Interrupt Enable */
-#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error Passive Interrupt Enable */
-#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-Off Interrupt Enable */
-#define  CAN_IER_LECIE                       0x00000800U        /*!<Last Error Code Interrupt Enable */
-#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error Interrupt Enable */
-#define  CAN_IER_WKUIE                       0x00010000U        /*!<Wakeup Interrupt Enable */
-#define  CAN_IER_SLKIE                       0x00020000U        /*!<Sleep Interrupt Enable */
-#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error warning interrupt enable */
-#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error passive interrupt enable */
-#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-off interrupt enable */
-#define  CAN_IER_LECIE                       0x00000800U        /*!<Last error code interrupt enable */
-#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error interrupt enable */
-
-
-/********************  Bit definition for CAN_ESR register  *******************/
-#define  CAN_ESR_EWGF                        0x00000001U        /*!<Error Warning Flag */
-#define  CAN_ESR_EPVF                        0x00000002U        /*!<Error Passive Flag */
-#define  CAN_ESR_BOFF                        0x00000004U        /*!<Bus-Off Flag */
-
-#define  CAN_ESR_LEC                         0x00000070U        /*!<LEC[2:0] bits (Last Error Code) */
-#define  CAN_ESR_LEC_0                       0x00000010U        /*!<Bit 0 */
-#define  CAN_ESR_LEC_1                       0x00000020U        /*!<Bit 1 */
-#define  CAN_ESR_LEC_2                       0x00000040U        /*!<Bit 2 */
-
-#define  CAN_ESR_TEC                         0x00FF0000U        /*!<Least significant byte of the 9-bit Transmit Error Counter */
-#define  CAN_ESR_REC                         0xFF000000U        /*!<Receive Error Counter */
-
-/*******************  Bit definition for CAN_BTR register  ********************/
-#define  CAN_BTR_BRP                         0x000003FFU        /*!<Baud Rate Prescaler */
-#define  CAN_BTR_TS1                         0x000F0000U        /*!<Time Segment 1 */
-#define  CAN_BTR_TS1_0                       0x00010000U        /*!<Bit 0 */
-#define  CAN_BTR_TS1_1                       0x00020000U        /*!<Bit 1 */
-#define  CAN_BTR_TS1_2                       0x00040000U        /*!<Bit 2 */
-#define  CAN_BTR_TS1_3                       0x00080000U        /*!<Bit 3 */
-#define  CAN_BTR_TS2                         0x00700000U        /*!<Time Segment 2 */
-#define  CAN_BTR_TS2_0                       0x00100000U        /*!<Bit 0 */
-#define  CAN_BTR_TS2_1                       0x00200000U        /*!<Bit 1 */
-#define  CAN_BTR_TS2_2                       0x00400000U        /*!<Bit 2 */
-#define  CAN_BTR_SJW                         0x03000000U        /*!<Resynchronization Jump Width */
-#define  CAN_BTR_SJW_0                       0x01000000U        /*!<Bit 0 */
-#define  CAN_BTR_SJW_1                       0x02000000U        /*!<Bit 1 */
-#define  CAN_BTR_LBKM                        0x40000000U        /*!<Loop Back Mode (Debug) */
-#define  CAN_BTR_SILM                        0x80000000U        /*!<Silent Mode */
-
-
-/*!<Mailbox registers */
-/******************  Bit definition for CAN_TI0R register  ********************/
-#define  CAN_TI0R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI0R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_TI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/******************  Bit definition for CAN_TDT0R register  *******************/
-#define  CAN_TDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT0R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/******************  Bit definition for CAN_TDL0R register  *******************/
-#define  CAN_TDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/******************  Bit definition for CAN_TDH0R register  *******************/
-#define  CAN_TDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI1R register  *******************/
-#define  CAN_TI1R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI1R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI1R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_TI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT1R register  ******************/
-#define  CAN_TDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT1R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL1R register  ******************/
-#define  CAN_TDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH1R register  ******************/
-#define  CAN_TDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI2R register  *******************/
-#define  CAN_TI2R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI2R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI2R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI2R_EXID                       0x001FFFF8U        /*!<Extended identifier */
-#define  CAN_TI2R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT2R register  ******************/  
-#define  CAN_TDT2R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT2R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT2R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL2R register  ******************/
-#define  CAN_TDL2R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL2R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL2R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL2R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH2R register  ******************/
-#define  CAN_TDH2R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH2R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH2R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH2R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI0R register  *******************/
-#define  CAN_RI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_RI0R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_RI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_RI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT0R register  ******************/
-#define  CAN_RDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_RDT0R_FMI                       0x0000FF00U        /*!<Filter Match Index */
-#define  CAN_RDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL0R register  ******************/
-#define  CAN_RDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_RDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_RDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_RDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH0R register  ******************/
-#define  CAN_RDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_RDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_RDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_RDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI1R register  *******************/
-#define  CAN_RI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_RI1R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_RI1R_EXID                       0x001FFFF8U        /*!<Extended identifier */
-#define  CAN_RI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT1R register  ******************/
-#define  CAN_RDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_RDT1R_FMI                       0x0000FF00U        /*!<Filter Match Index */
-#define  CAN_RDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL1R register  ******************/
-#define  CAN_RDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_RDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_RDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_RDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH1R register  ******************/
-#define  CAN_RDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_RDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_RDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_RDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*!<CAN filter registers */
-/*******************  Bit definition for CAN_FMR register  ********************/
-#define  CAN_FMR_FINIT                       0x01U               /*!<Filter Init Mode */
-#define  CAN_FMR_CAN2SB                      0x00003F00U        /*!<CAN2 start bank */
-
-/*******************  Bit definition for CAN_FM1R register  *******************/
-#define  CAN_FM1R_FBM                        0x0FFFFFFFU        /*!<Filter Mode */
-#define  CAN_FM1R_FBM0                       0x00000001U        /*!<Filter Init Mode bit 0 */
-#define  CAN_FM1R_FBM1                       0x00000002U        /*!<Filter Init Mode bit 1 */
-#define  CAN_FM1R_FBM2                       0x00000004U        /*!<Filter Init Mode bit 2 */
-#define  CAN_FM1R_FBM3                       0x00000008U        /*!<Filter Init Mode bit 3 */
-#define  CAN_FM1R_FBM4                       0x00000010U        /*!<Filter Init Mode bit 4 */
-#define  CAN_FM1R_FBM5                       0x00000020U        /*!<Filter Init Mode bit 5 */
-#define  CAN_FM1R_FBM6                       0x00000040U        /*!<Filter Init Mode bit 6 */
-#define  CAN_FM1R_FBM7                       0x00000080U        /*!<Filter Init Mode bit 7 */
-#define  CAN_FM1R_FBM8                       0x00000100U        /*!<Filter Init Mode bit 8 */
-#define  CAN_FM1R_FBM9                       0x00000200U        /*!<Filter Init Mode bit 9 */
-#define  CAN_FM1R_FBM10                      0x00000400U        /*!<Filter Init Mode bit 10 */
-#define  CAN_FM1R_FBM11                      0x00000800U        /*!<Filter Init Mode bit 11 */
-#define  CAN_FM1R_FBM12                      0x00001000U        /*!<Filter Init Mode bit 12 */
-#define  CAN_FM1R_FBM13                      0x00002000U        /*!<Filter Init Mode bit 13 */
-#define  CAN_FM1R_FBM14                      0x00004000U        /*!<Filter Init Mode bit 14 */
-#define  CAN_FM1R_FBM15                      0x00008000U        /*!<Filter Init Mode bit 15 */
-#define  CAN_FM1R_FBM16                      0x00010000U        /*!<Filter Init Mode bit 16 */
-#define  CAN_FM1R_FBM17                      0x00020000U        /*!<Filter Init Mode bit 17 */
-#define  CAN_FM1R_FBM18                      0x00040000U        /*!<Filter Init Mode bit 18 */
-#define  CAN_FM1R_FBM19                      0x00080000U        /*!<Filter Init Mode bit 19 */
-#define  CAN_FM1R_FBM20                      0x00100000U        /*!<Filter Init Mode bit 20 */
-#define  CAN_FM1R_FBM21                      0x00200000U        /*!<Filter Init Mode bit 21 */
-#define  CAN_FM1R_FBM22                      0x00400000U        /*!<Filter Init Mode bit 22 */
-#define  CAN_FM1R_FBM23                      0x00800000U        /*!<Filter Init Mode bit 23 */
-#define  CAN_FM1R_FBM24                      0x01000000U        /*!<Filter Init Mode bit 24 */
-#define  CAN_FM1R_FBM25                      0x02000000U        /*!<Filter Init Mode bit 25 */
-#define  CAN_FM1R_FBM26                      0x04000000U        /*!<Filter Init Mode bit 26 */
-#define  CAN_FM1R_FBM27                      0x08000000U        /*!<Filter Init Mode bit 27 */
-
-/*******************  Bit definition for CAN_FS1R register  *******************/
-#define  CAN_FS1R_FSC                        0x0FFFFFFFU        /*!<Filter Scale Configuration */
-#define  CAN_FS1R_FSC0                       0x00000001U        /*!<Filter Scale Configuration bit 0 */
-#define  CAN_FS1R_FSC1                       0x00000002U        /*!<Filter Scale Configuration bit 1 */
-#define  CAN_FS1R_FSC2                       0x00000004U        /*!<Filter Scale Configuration bit 2 */
-#define  CAN_FS1R_FSC3                       0x00000008U        /*!<Filter Scale Configuration bit 3 */
-#define  CAN_FS1R_FSC4                       0x00000010U        /*!<Filter Scale Configuration bit 4 */
-#define  CAN_FS1R_FSC5                       0x00000020U        /*!<Filter Scale Configuration bit 5 */
-#define  CAN_FS1R_FSC6                       0x00000040U        /*!<Filter Scale Configuration bit 6 */
-#define  CAN_FS1R_FSC7                       0x00000080U        /*!<Filter Scale Configuration bit 7 */
-#define  CAN_FS1R_FSC8                       0x00000100U        /*!<Filter Scale Configuration bit 8 */
-#define  CAN_FS1R_FSC9                       0x00000200U        /*!<Filter Scale Configuration bit 9 */
-#define  CAN_FS1R_FSC10                      0x00000400U        /*!<Filter Scale Configuration bit 10 */
-#define  CAN_FS1R_FSC11                      0x00000800U        /*!<Filter Scale Configuration bit 11 */
-#define  CAN_FS1R_FSC12                      0x00001000U        /*!<Filter Scale Configuration bit 12 */
-#define  CAN_FS1R_FSC13                      0x00002000U        /*!<Filter Scale Configuration bit 13 */
-#define  CAN_FS1R_FSC14                      0x00004000U        /*!<Filter Scale Configuration bit 14 */
-#define  CAN_FS1R_FSC15                      0x00008000U        /*!<Filter Scale Configuration bit 15 */
-#define  CAN_FS1R_FSC16                      0x00010000U        /*!<Filter Scale Configuration bit 16 */
-#define  CAN_FS1R_FSC17                      0x00020000U        /*!<Filter Scale Configuration bit 17 */
-#define  CAN_FS1R_FSC18                      0x00040000U        /*!<Filter Scale Configuration bit 18 */
-#define  CAN_FS1R_FSC19                      0x00080000U        /*!<Filter Scale Configuration bit 19 */
-#define  CAN_FS1R_FSC20                      0x00100000U        /*!<Filter Scale Configuration bit 20 */
-#define  CAN_FS1R_FSC21                      0x00200000U        /*!<Filter Scale Configuration bit 21 */
-#define  CAN_FS1R_FSC22                      0x00400000U        /*!<Filter Scale Configuration bit 22 */
-#define  CAN_FS1R_FSC23                      0x00800000U        /*!<Filter Scale Configuration bit 23 */
-#define  CAN_FS1R_FSC24                      0x01000000U        /*!<Filter Scale Configuration bit 24 */
-#define  CAN_FS1R_FSC25                      0x02000000U        /*!<Filter Scale Configuration bit 25 */
-#define  CAN_FS1R_FSC26                      0x04000000U        /*!<Filter Scale Configuration bit 26 */
-#define  CAN_FS1R_FSC27                      0x08000000U        /*!<Filter Scale Configuration bit 27 */
-
-/******************  Bit definition for CAN_FFA1R register  *******************/
-#define  CAN_FFA1R_FFA                        0x0FFFFFFFU        /*!<Filter FIFO Assignment */
-#define  CAN_FFA1R_FFA0                       0x00000001U        /*!<Filter FIFO Assignment bit 0 */
-#define  CAN_FFA1R_FFA1                       0x00000002U        /*!<Filter FIFO Assignment bit 1 */
-#define  CAN_FFA1R_FFA2                       0x00000004U        /*!<Filter FIFO Assignment bit 2 */
-#define  CAN_FFA1R_FFA3                       0x00000008U        /*!<Filter FIFO Assignment bit 3 */
-#define  CAN_FFA1R_FFA4                       0x00000010U        /*!<Filter FIFO Assignment bit 4 */
-#define  CAN_FFA1R_FFA5                       0x00000020U        /*!<Filter FIFO Assignment bit 5 */
-#define  CAN_FFA1R_FFA6                       0x00000040U        /*!<Filter FIFO Assignment bit 6 */
-#define  CAN_FFA1R_FFA7                       0x00000080U        /*!<Filter FIFO Assignment bit 7 */
-#define  CAN_FFA1R_FFA8                       0x00000100U        /*!<Filter FIFO Assignment bit 8 */
-#define  CAN_FFA1R_FFA9                       0x00000200U        /*!<Filter FIFO Assignment bit 9 */
-#define  CAN_FFA1R_FFA10                      0x00000400U        /*!<Filter FIFO Assignment bit 10 */
-#define  CAN_FFA1R_FFA11                      0x00000800U        /*!<Filter FIFO Assignment bit 11 */
-#define  CAN_FFA1R_FFA12                      0x00001000U        /*!<Filter FIFO Assignment bit 12 */
-#define  CAN_FFA1R_FFA13                      0x00002000U        /*!<Filter FIFO Assignment bit 13 */
-#define  CAN_FFA1R_FFA14                      0x00004000U        /*!<Filter FIFO Assignment bit 14 */
-#define  CAN_FFA1R_FFA15                      0x00008000U        /*!<Filter FIFO Assignment bit 15 */
-#define  CAN_FFA1R_FFA16                      0x00010000U        /*!<Filter FIFO Assignment bit 16 */
-#define  CAN_FFA1R_FFA17                      0x00020000U        /*!<Filter FIFO Assignment bit 17 */
-#define  CAN_FFA1R_FFA18                      0x00040000U        /*!<Filter FIFO Assignment bit 18 */
-#define  CAN_FFA1R_FFA19                      0x00080000U        /*!<Filter FIFO Assignment bit 19 */
-#define  CAN_FFA1R_FFA20                      0x00100000U        /*!<Filter FIFO Assignment bit 20 */
-#define  CAN_FFA1R_FFA21                      0x00200000U        /*!<Filter FIFO Assignment bit 21 */
-#define  CAN_FFA1R_FFA22                      0x00400000U        /*!<Filter FIFO Assignment bit 22 */
-#define  CAN_FFA1R_FFA23                      0x00800000U        /*!<Filter FIFO Assignment bit 23 */
-#define  CAN_FFA1R_FFA24                      0x01000000U        /*!<Filter FIFO Assignment bit 24 */
-#define  CAN_FFA1R_FFA25                      0x02000000U        /*!<Filter FIFO Assignment bit 25 */
-#define  CAN_FFA1R_FFA26                      0x04000000U        /*!<Filter FIFO Assignment bit 26 */
-#define  CAN_FFA1R_FFA27                      0x08000000U        /*!<Filter FIFO Assignment bit 27 */
-
-/*******************  Bit definition for CAN_FA1R register  *******************/
-#define  CAN_FA1R_FACT                        0x0FFFFFFFU        /*!<Filter Active */
-#define  CAN_FA1R_FACT0                       0x00000001U        /*!<Filter Active bit 0 */
-#define  CAN_FA1R_FACT1                       0x00000002U        /*!<Filter Active bit 1 */
-#define  CAN_FA1R_FACT2                       0x00000004U        /*!<Filter Active bit 2 */
-#define  CAN_FA1R_FACT3                       0x00000008U        /*!<Filter Active bit 3 */
-#define  CAN_FA1R_FACT4                       0x00000010U        /*!<Filter Active bit 4 */
-#define  CAN_FA1R_FACT5                       0x00000020U        /*!<Filter Active bit 5 */
-#define  CAN_FA1R_FACT6                       0x00000040U        /*!<Filter Active bit 6 */
-#define  CAN_FA1R_FACT7                       0x00000080U        /*!<Filter Active bit 7 */
-#define  CAN_FA1R_FACT8                       0x00000100U        /*!<Filter Active bit 8 */
-#define  CAN_FA1R_FACT9                       0x00000200U        /*!<Filter Active bit 9 */
-#define  CAN_FA1R_FACT10                      0x00000400U        /*!<Filter Active bit 10 */
-#define  CAN_FA1R_FACT11                      0x00000800U        /*!<Filter Active bit 11 */
-#define  CAN_FA1R_FACT12                      0x00001000U        /*!<Filter Active bit 12 */
-#define  CAN_FA1R_FACT13                      0x00002000U        /*!<Filter Active bit 13 */
-#define  CAN_FA1R_FACT14                      0x00004000U        /*!<Filter Active bit 14 */
-#define  CAN_FA1R_FACT15                      0x00008000U        /*!<Filter Active bit 15 */
-#define  CAN_FA1R_FACT16                      0x00010000U        /*!<Filter Active bit 16 */
-#define  CAN_FA1R_FACT17                      0x00020000U        /*!<Filter Active bit 17 */
-#define  CAN_FA1R_FACT18                      0x00040000U        /*!<Filter Active bit 18 */
-#define  CAN_FA1R_FACT19                      0x00080000U        /*!<Filter Active bit 19 */
-#define  CAN_FA1R_FACT20                      0x00100000U        /*!<Filter Active bit 20 */
-#define  CAN_FA1R_FACT21                      0x00200000U        /*!<Filter Active bit 21 */
-#define  CAN_FA1R_FACT22                      0x00400000U        /*!<Filter Active bit 22 */
-#define  CAN_FA1R_FACT23                      0x00800000U        /*!<Filter Active bit 23 */
-#define  CAN_FA1R_FACT24                      0x01000000U        /*!<Filter Active bit 24 */
-#define  CAN_FA1R_FACT25                      0x02000000U        /*!<Filter Active bit 25 */
-#define  CAN_FA1R_FACT26                      0x04000000U        /*!<Filter Active bit 26 */
-#define  CAN_FA1R_FACT27                      0x08000000U        /*!<Filter Active bit 27 */
-
-/*******************  Bit definition for CAN_F0R1 register  *******************/
-#define  CAN_F0R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F0R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F0R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F0R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F0R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F0R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F0R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F0R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F0R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F0R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F0R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F0R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F0R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F0R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F0R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F0R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F0R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F0R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F0R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F0R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F0R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F0R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F0R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F0R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F0R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F0R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F0R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F0R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F0R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F0R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F0R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F0R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R1 register  *******************/
-#define  CAN_F1R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F1R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F1R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F1R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F1R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F1R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F1R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F1R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F1R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F1R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F1R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F1R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F1R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F1R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F1R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F1R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F1R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F1R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F1R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F1R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F1R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F1R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F1R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F1R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F1R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F1R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F1R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F1R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F1R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F1R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F1R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F1R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R1 register  *******************/
-#define  CAN_F2R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F2R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F2R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F2R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F2R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F2R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F2R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F2R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F2R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F2R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F2R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F2R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F2R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F2R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F2R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F2R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F2R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F2R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F2R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F2R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F2R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F2R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F2R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F2R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F2R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F2R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F2R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F2R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F2R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F2R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F2R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F2R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R1 register  *******************/
-#define  CAN_F3R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F3R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F3R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F3R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F3R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F3R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F3R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F3R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F3R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F3R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F3R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F3R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F3R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F3R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F3R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F3R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F3R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F3R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F3R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F3R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F3R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F3R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F3R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F3R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F3R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F3R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F3R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F3R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F3R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F3R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F3R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F3R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R1 register  *******************/
-#define  CAN_F4R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F4R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F4R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F4R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F4R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F4R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F4R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F4R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F4R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F4R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F4R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F4R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F4R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F4R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F4R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F4R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F4R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F4R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F4R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F4R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F4R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F4R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F4R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F4R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F4R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F4R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F4R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F4R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F4R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F4R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F4R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F4R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R1 register  *******************/
-#define  CAN_F5R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F5R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F5R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F5R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F5R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F5R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F5R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F5R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F5R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F5R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F5R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F5R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F5R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F5R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F5R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F5R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F5R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F5R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F5R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F5R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F5R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F5R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F5R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F5R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F5R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F5R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F5R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F5R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F5R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F5R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F5R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F5R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R1 register  *******************/
-#define  CAN_F6R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F6R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F6R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F6R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F6R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F6R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F6R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F6R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F6R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F6R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F6R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F6R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F6R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F6R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F6R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F6R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F6R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F6R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F6R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F6R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F6R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F6R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F6R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F6R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F6R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F6R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F6R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F6R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F6R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F6R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F6R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F6R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R1 register  *******************/
-#define  CAN_F7R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F7R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F7R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F7R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F7R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F7R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F7R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F7R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F7R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F7R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F7R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F7R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F7R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F7R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F7R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F7R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F7R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F7R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F7R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F7R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F7R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F7R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F7R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F7R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F7R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F7R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F7R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F7R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F7R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F7R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F7R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F7R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R1 register  *******************/
-#define  CAN_F8R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F8R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F8R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F8R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F8R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F8R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F8R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F8R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F8R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F8R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F8R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F8R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F8R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F8R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F8R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F8R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F8R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F8R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F8R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F8R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F8R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F8R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F8R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F8R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F8R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F8R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F8R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F8R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F8R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F8R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F8R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F8R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R1 register  *******************/
-#define  CAN_F9R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F9R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F9R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F9R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F9R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F9R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F9R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F9R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F9R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F9R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F9R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F9R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F9R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F9R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F9R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F9R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F9R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F9R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F9R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F9R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F9R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F9R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F9R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F9R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F9R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F9R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F9R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F9R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F9R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F9R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F9R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F9R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R1 register  ******************/
-#define  CAN_F10R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F10R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F10R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F10R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F10R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F10R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F10R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F10R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F10R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F10R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F10R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F10R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F10R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F10R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F10R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F10R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F10R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F10R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F10R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F10R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F10R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F10R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F10R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F10R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F10R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F10R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F10R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F10R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F10R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F10R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F10R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F10R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R1 register  ******************/
-#define  CAN_F11R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F11R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F11R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F11R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F11R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F11R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F11R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F11R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F11R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F11R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F11R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F11R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F11R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F11R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F11R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F11R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F11R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F11R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F11R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F11R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F11R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F11R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F11R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F11R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F11R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F11R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F11R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F11R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F11R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F11R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F11R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F11R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R1 register  ******************/
-#define  CAN_F12R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F12R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F12R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F12R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F12R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F12R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F12R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F12R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F12R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F12R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F12R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F12R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F12R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F12R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F12R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F12R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F12R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F12R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F12R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F12R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F12R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F12R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F12R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F12R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F12R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F12R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F12R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F12R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F12R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F12R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F12R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F12R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R1 register  ******************/
-#define  CAN_F13R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F13R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F13R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F13R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F13R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F13R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F13R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F13R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F13R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F13R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F13R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F13R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F13R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F13R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F13R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F13R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F13R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F13R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F13R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F13R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F13R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F13R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F13R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F13R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F13R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F13R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F13R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F13R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F13R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F13R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F13R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F13R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F0R2 register  *******************/
-#define  CAN_F0R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F0R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F0R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F0R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F0R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F0R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F0R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F0R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F0R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F0R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F0R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F0R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F0R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F0R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F0R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F0R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F0R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F0R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F0R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F0R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F0R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F0R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F0R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F0R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F0R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F0R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F0R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F0R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F0R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F0R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F0R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F0R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R2 register  *******************/
-#define  CAN_F1R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F1R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F1R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F1R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F1R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F1R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F1R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F1R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F1R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F1R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F1R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F1R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F1R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F1R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F1R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F1R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F1R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F1R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F1R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F1R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F1R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F1R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F1R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F1R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F1R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F1R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F1R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F1R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F1R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F1R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F1R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F1R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R2 register  *******************/
-#define  CAN_F2R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F2R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F2R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F2R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F2R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F2R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F2R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F2R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F2R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F2R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F2R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F2R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F2R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F2R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F2R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F2R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F2R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F2R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F2R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F2R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F2R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F2R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F2R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F2R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F2R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F2R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F2R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F2R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F2R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F2R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F2R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F2R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R2 register  *******************/
-#define  CAN_F3R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F3R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F3R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F3R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F3R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F3R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F3R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F3R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F3R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F3R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F3R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F3R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F3R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F3R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F3R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F3R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F3R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F3R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F3R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F3R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F3R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F3R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F3R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F3R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F3R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F3R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F3R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F3R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F3R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F3R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F3R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F3R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R2 register  *******************/
-#define  CAN_F4R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F4R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F4R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F4R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F4R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F4R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F4R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F4R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F4R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F4R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F4R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F4R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F4R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F4R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F4R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F4R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F4R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F4R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F4R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F4R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F4R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F4R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F4R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F4R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F4R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F4R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F4R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F4R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F4R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F4R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F4R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F4R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R2 register  *******************/
-#define  CAN_F5R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F5R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F5R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F5R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F5R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F5R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F5R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F5R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F5R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F5R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F5R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F5R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F5R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F5R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F5R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F5R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F5R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F5R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F5R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F5R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F5R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F5R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F5R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F5R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F5R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F5R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F5R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F5R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F5R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F5R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F5R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F5R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R2 register  *******************/
-#define  CAN_F6R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F6R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F6R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F6R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F6R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F6R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F6R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F6R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F6R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F6R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F6R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F6R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F6R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F6R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F6R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F6R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F6R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F6R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F6R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F6R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F6R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F6R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F6R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F6R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F6R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F6R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F6R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F6R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F6R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F6R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F6R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F6R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R2 register  *******************/
-#define  CAN_F7R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F7R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F7R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F7R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F7R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F7R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F7R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F7R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F7R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F7R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F7R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F7R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F7R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F7R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F7R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F7R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F7R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F7R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F7R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F7R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F7R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F7R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F7R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F7R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F7R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F7R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F7R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F7R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F7R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F7R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F7R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F7R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R2 register  *******************/
-#define  CAN_F8R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F8R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F8R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F8R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F8R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F8R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F8R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F8R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F8R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F8R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F8R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F8R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F8R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F8R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F8R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F8R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F8R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F8R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F8R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F8R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F8R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F8R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F8R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F8R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F8R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F8R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F8R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F8R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F8R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F8R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F8R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F8R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R2 register  *******************/
-#define  CAN_F9R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F9R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F9R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F9R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F9R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F9R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F9R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F9R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F9R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F9R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F9R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F9R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F9R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F9R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F9R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F9R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F9R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F9R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F9R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F9R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F9R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F9R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F9R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F9R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F9R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F9R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F9R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F9R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F9R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F9R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F9R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F9R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R2 register  ******************/
-#define  CAN_F10R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F10R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F10R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F10R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F10R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F10R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F10R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F10R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F10R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F10R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F10R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F10R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F10R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F10R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F10R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F10R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F10R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F10R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F10R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F10R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F10R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F10R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F10R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F10R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F10R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F10R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F10R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F10R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F10R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F10R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F10R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F10R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R2 register  ******************/
-#define  CAN_F11R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F11R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F11R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F11R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F11R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F11R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F11R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F11R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F11R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F11R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F11R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F11R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F11R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F11R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F11R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F11R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F11R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F11R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F11R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F11R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F11R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F11R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F11R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F11R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F11R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F11R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F11R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F11R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F11R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F11R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F11R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F11R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R2 register  ******************/
-#define  CAN_F12R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F12R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F12R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F12R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F12R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F12R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F12R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F12R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F12R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F12R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F12R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F12R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F12R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F12R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F12R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F12R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F12R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F12R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F12R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F12R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F12R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F12R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F12R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F12R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F12R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F12R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F12R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F12R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F12R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F12R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F12R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F12R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R2 register  ******************/
-#define  CAN_F13R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F13R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F13R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F13R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F13R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F13R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F13R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F13R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F13R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F13R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F13R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F13R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F13R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F13R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F13R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F13R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F13R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F13R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F13R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F13R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F13R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F13R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F13R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F13R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F13R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F13R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F13R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F13R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F13R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F13R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F13R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F13R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRC calculation unit                              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           0xFFFFFFFFU /*!< Data register bits */
-
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         0xFFU        /*!< General-purpose 8-bit data register bits */
-
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        0x01U        /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 Debug MCU                                  */
-/*                                                                            */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                 Digital Filter for Sigma Delta Modulators                  */
-/*                                                                            */
-/******************************************************************************/
-
-/****************   DFSDM channel configuration registers  ********************/
-
-/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/
-#define  DFSDM_CHCFGR1_DFSDMEN                0x80000000U            /*!< Global enable for DFSDM interface */
-#define  DFSDM_CHCFGR1_CKOUTSRC               0x40000000U            /*!< Output serial clock source selection */
-#define  DFSDM_CHCFGR1_CKOUTDIV               0x00FF0000U            /*!< CKOUTDIV[7:0] output serial clock divider */
-#define  DFSDM_CHCFGR1_DATPACK                0x0000C000U            /*!< DATPACK[1:0] Data packing mode */
-#define  DFSDM_CHCFGR1_DATPACK_1              0x00008000U            /*!< Data packing mode, Bit 1 */
-#define  DFSDM_CHCFGR1_DATPACK_0              0x00004000U            /*!< Data packing mode, Bit 0 */
-#define  DFSDM_CHCFGR1_DATMPX                 0x00003000U            /*!< DATMPX[1:0] Input data multiplexer for channel y */
-#define  DFSDM_CHCFGR1_DATMPX_1               0x00002000U            /*!< Input data multiplexer for channel y, Bit 1 */
-#define  DFSDM_CHCFGR1_DATMPX_0               0x00001000U            /*!< Input data multiplexer for channel y, Bit 0 */
-#define  DFSDM_CHCFGR1_CHINSEL                0x00000100U            /*!< Serial inputs selection for channel y */
-#define  DFSDM_CHCFGR1_CHEN                   0x00000080U            /*!< Channel y enable */
-#define  DFSDM_CHCFGR1_CKABEN                 0x00000040U            /*!< Clock absence detector enable on channel y */
-#define  DFSDM_CHCFGR1_SCDEN                  0x00000020U            /*!< Short circuit detector enable on channel y */
-#define  DFSDM_CHCFGR1_SPICKSEL               0x0000000CU            /*!< SPICKSEL[1:0] SPI clock select for channel y */
-#define  DFSDM_CHCFGR1_SPICKSEL_1             0x00000008U            /*!< SPI clock select for channel y, Bit 1 */
-#define  DFSDM_CHCFGR1_SPICKSEL_0             0x00000004U            /*!< SPI clock select for channel y, Bit 0 */
-#define  DFSDM_CHCFGR1_SITP                   0x00000003U            /*!< SITP[1:0] Serial interface type for channel y */
-#define  DFSDM_CHCFGR1_SITP_1                 0x00000002U            /*!< Serial interface type for channel y, Bit 1 */
-#define  DFSDM_CHCFGR1_SITP_0                 0x00000001U            /*!< Serial interface type for channel y, Bit 0 */
-
-/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/
-#define  DFSDM_CHCFGR2_OFFSET                 0xFFFFFF00U            /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
-#define  DFSDM_CHCFGR2_DTRBS                  0x000000F8U            /*!< DTRBS[4:0] Data right bit-shift for channel y */
-
-/****************  Bit definition for DFSDM_CHAWSCDR register *****************/
-#define  DFSDM_CHAWSCDR_AWFORD                0x00C00000U            /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
-#define  DFSDM_CHAWSCDR_AWFORD_1              0x00800000U            /*!< Analog watchdog Sinc filter order on channel y, Bit 1 */
-#define  DFSDM_CHAWSCDR_AWFORD_0              0x00400000U            /*!< Analog watchdog Sinc filter order on channel y, Bit 0 */
-#define  DFSDM_CHAWSCDR_AWFOSR                0x001F0000U            /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
-#define  DFSDM_CHAWSCDR_BKSCD                 0x0000F000U            /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
-#define  DFSDM_CHAWSCDR_SCDT                  0x000000FFU            /*!< SCDT[7:0] Short circuit detector threshold for channel y */
-
-/****************  Bit definition for DFSDM_CHWDATR register *******************/
-#define  DFSDM_CHWDATR_WDATA                  0x0000FFFFU            /*!< WDATA[15:0] Input channel y watchdog data */
-
-/****************  Bit definition for DFSDM_CHDATINR register *****************/
-#define  DFSDM_CHDATINR_INDAT0                0x0000FFFFU            /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
-#define  DFSDM_CHDATINR_INDAT1                0xFFFF0000U            /*!< INDAT0[15:0] Input data for channel y */
-
-/************************   DFSDM module registers  ****************************/
-
-/*****************  Bit definition for DFSDM_FLTCR1 register *******************/
-#define  DFSDM_FLTCR1_AWFSEL                  0x40000000U            /*!< Analog watchdog fast mode select */
-#define  DFSDM_FLTCR1_FAST                    0x20000000U            /*!< Fast conversion mode selection */
-#define  DFSDM_FLTCR1_RCH                     0x07000000U            /*!< RCH[2:0] Regular channel selection */
-#define  DFSDM_FLTCR1_RDMAEN                  0x00200000U            /*!< DMA channel enabled to read data for the regular conversion */
-#define  DFSDM_FLTCR1_RSYNC                   0x00080000U            /*!< Launch regular conversion synchronously with DFSDMx */
-#define  DFSDM_FLTCR1_RCONT                   0x00040000U            /*!< Continuous mode selection for regular conversions */
-#define  DFSDM_FLTCR1_RSWSTART                0x00020000U            /*!< Software start of a conversion on the regular channel */
-#define  DFSDM_FLTCR1_JEXTEN                  0x00006000U            /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
-#define  DFSDM_FLTCR1_JEXTEN_1                0x00004000U            /*!< Trigger enable and trigger edge selection for injected conversions, Bit 1 */
-#define  DFSDM_FLTCR1_JEXTEN_0                0x00002000U            /*!< Trigger enable and trigger edge selection for injected conversions, Bit 0 */
-#define  DFSDM_FLTCR1_JEXTSEL                 0x00000700U            /*!< JEXTSEL[2:0]Trigger signal selection for launching injected conversions */
-#define  DFSDM_FLTCR1_JEXTSEL_2               0x00000400U            /*!< Trigger signal selection for launching injected conversions, Bit 2 */
-#define  DFSDM_FLTCR1_JEXTSEL_1               0x00000200U            /*!< Trigger signal selection for launching injected conversions, Bit 1 */
-#define  DFSDM_FLTCR1_JEXTSEL_0               0x00000100U            /*!< Trigger signal selection for launching injected conversions, Bit 0 */
-#define  DFSDM_FLTCR1_JDMAEN                  0x00000020U            /*!< DMA channel enabled to read data for the injected channel group */
-#define  DFSDM_FLTCR1_JSCAN                   0x00000010U            /*!< Scanning conversion in continuous mode selection for injected conversions */
-#define  DFSDM_FLTCR1_JSYNC                   0x00000008U            /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */
-#define  DFSDM_FLTCR1_JSWSTART                0x00000002U            /*!< Start the conversion of the injected group of channels */
-#define  DFSDM_FLTCR1_DFEN                    0x00000001U            /*!< DFSDM enable */
-
-/*****************  Bit definition for DFSDM_FLTCR2 register *******************/
-#define  DFSDM_FLTCR2_AWDCH                   0x000F0000U            /*!< AWDCH[7:0] Analog watchdog channel selection */
-#define  DFSDM_FLTCR2_EXCH                    0x00000F00U            /*!< EXCH[7:0] Extreme detector channel selection */
-#define  DFSDM_FLTCR2_CKABIE                  0x00000040U            /*!< Clock absence interrupt enable */
-#define  DFSDM_FLTCR2_SCDIE                   0x00000020U            /*!< Short circuit detector interrupt enable */
-#define  DFSDM_FLTCR2_AWDIE                   0x00000010U            /*!< Analog watchdog interrupt enable */
-#define  DFSDM_FLTCR2_ROVRIE                  0x00000008U            /*!< Regular data overrun interrupt enable */
-#define  DFSDM_FLTCR2_JOVRIE                  0x00000004U            /*!< Injected data overrun interrupt enable */
-#define  DFSDM_FLTCR2_REOCIE                  0x00000002U            /*!< Regular end of conversion interrupt enable */
-#define  DFSDM_FLTCR2_JEOCIE                  0x00000001U            /*!< Injected end of conversion interrupt enable */
-
-/*****************  Bit definition for DFSDM_FLTISR register *******************/
-#define  DFSDM_FLTISR_SCDF                    0x0F000000U            /*!< SCDF[7:0] Short circuit detector flag */
-#define  DFSDM_FLTISR_CKABF                   0x000F0000U            /*!< CKABF[7:0] Clock absence flag */
-#define  DFSDM_FLTISR_RCIP                    0x00004000U            /*!< Regular conversion in progress status */
-#define  DFSDM_FLTISR_JCIP                    0x00002000U            /*!< Injected conversion in progress status */
-#define  DFSDM_FLTISR_AWDF                    0x00000010U            /*!< Analog watchdog */
-#define  DFSDM_FLTISR_ROVRF                   0x00000008U            /*!< Regular conversion overrun flag */
-#define  DFSDM_FLTISR_JOVRF                   0x00000004U            /*!< Injected conversion overrun flag */
-#define  DFSDM_FLTISR_REOCF                   0x00000002U            /*!< End of regular conversion flag */
-#define  DFSDM_FLTISR_JEOCF                   0x00000001U            /*!< End of injected conversion flag */
-
-/*****************  Bit definition for DFSDM_FLTICR register *******************/
-#define  DFSDM_FLTICR_CLRSCSDF                0x0F000000U            /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
-#define  DFSDM_FLTICR_CLRCKABF                0x000F0000U            /*!< CLRCKABF[7:0] Clear the clock absence flag */
-#define  DFSDM_FLTICR_CLRROVRF                0x00000008U            /*!< Clear the regular conversion overrun flag */
-#define  DFSDM_FLTICR_CLRJOVRF                0x00000004U            /*!< Clear the injected conversion overrun flag */
-
-/****************  Bit definition for DFSDM_FLTJCHGR register ******************/
-#define  DFSDM_FLTJCHGR_JCHG                  0x0000000FU            /*!< JCHG[7:0] Injected channel group selection */
-
-/*****************  Bit definition for DFSDM_FLTFCR register *******************/
-#define  DFSDM_FLTFCR_FORD                    0xE0000000U            /*!< FORD[2:0] Sinc filter order */
-#define  DFSDM_FLTFCR_FORD_2                  0x80000000U            /*!< Sinc filter order, Bit 2 */
-#define  DFSDM_FLTFCR_FORD_1                  0x40000000U            /*!< Sinc filter order, Bit 1 */
-#define  DFSDM_FLTFCR_FORD_0                  0x20000000U            /*!< Sinc filter order, Bit 0 */
-#define  DFSDM_FLTFCR_FOSR                    0x03FF0000U            /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
-#define  DFSDM_FLTFCR_IOSR                    0x000000FFU            /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
-
-/***************  Bit definition for DFSDM_FLTJDATAR register *****************/
-#define  DFSDM_FLTJDATAR_JDATA                0xFFFFFF00U            /*!< JDATA[23:0] Injected group conversion data */
-#define  DFSDM_FLTJDATAR_JDATACH              0x00000007U            /*!< JDATACH[2:0] Injected channel most recently converted */
-
-/***************  Bit definition for DFSDM_FLTRDATAR register *****************/
-#define  DFSDM_FLTRDATAR_RDATA                0xFFFFFF00U            /*!< RDATA[23:0] Regular channel conversion data */
-#define  DFSDM_FLTRDATAR_RPEND                0x00000010U            /*!< RPEND Regular channel pending data */
-#define  DFSDM_FLTRDATAR_RDATACH              0x00000007U            /*!< RDATACH[2:0] Regular channel most recently converted */
-
-/***************  Bit definition for DFSDM_FLTAWHTR register ******************/
-#define  DFSDM_FLTAWHTR_AWHT                 0xFFFFFF00U             /*!< AWHT[23:0] Analog watchdog high threshold */
-#define  DFSDM_FLTAWHTR_BKAWH                0x0000000FU             /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
-
-/***************  Bit definition for DFSDM_FLTAWLTR register ******************/
-#define  DFSDM_FLTAWLTR_AWLT                 0xFFFFFF00U             /*!< AWLT[23:0] Analog watchdog low threshold */
-#define  DFSDM_FLTAWLTR_BKAWL                0x0000000FU             /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
-
-/***************  Bit definition for DFSDM_FLTAWSR register *******************/
-#define  DFSDM_FLTAWSR_AWHTF                 0x00000F00U             /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
-#define  DFSDM_FLTAWSR_AWLTF                 0x0000000FU             /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
-
-/***************  Bit definition for DFSDM_FLTAWCFR register ******************/
-#define  DFSDM_FLTAWCFR_CLRAWHTF             0x00000F00U             /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
-#define  DFSDM_FLTAWCFR_CLRAWLTF             0x0000000FU             /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
-
-/***************  Bit definition for DFSDM_FLTEXMAX register ******************/
-#define  DFSDM_FLTEXMAX_EXMAX                0xFFFFFF00U             /*!< EXMAX[23:0] Extreme detector maximum value */
-#define  DFSDM_FLTEXMAX_EXMAXCH              0x00000007U             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
-
-/***************  Bit definition for DFSDM_FLTEXMIN register ******************/
-#define  DFSDM_FLTEXMIN_EXMIN                0xFFFFFF00U             /*!< EXMIN[23:0] Extreme detector minimum value */
-#define  DFSDM_FLTEXMIN_EXMINCH              0x00000007U             /*!< EXMINCH[2:0] Extreme detector minimum data channel */
-
-/***************  Bit definition for DFSDM_FLTCNVTIMR register ****************/
-#define  DFSDM_FLTCNVTIMR_CNVCNT             0xFFFFFFF0U             /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
-
-/******************************************************************************/
-/*                                                                            */
-/*                             DMA Controller                                 */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DMA_SxCR register  *****************/ 
-#define DMA_SxCR_CHSEL                       0x0E000000U
-#define DMA_SxCR_CHSEL_0                     0x02000000U
-#define DMA_SxCR_CHSEL_1                     0x04000000U
-#define DMA_SxCR_CHSEL_2                     0x08000000U
-#define DMA_SxCR_MBURST                      0x01800000U
-#define DMA_SxCR_MBURST_0                    0x00800000U
-#define DMA_SxCR_MBURST_1                    0x01000000U
-#define DMA_SxCR_PBURST                      0x00600000U
-#define DMA_SxCR_PBURST_0                    0x00200000U
-#define DMA_SxCR_PBURST_1                    0x00400000U
-#define DMA_SxCR_CT                          0x00080000U
-#define DMA_SxCR_DBM                         0x00040000U
-#define DMA_SxCR_PL                          0x00030000U
-#define DMA_SxCR_PL_0                        0x00010000U
-#define DMA_SxCR_PL_1                        0x00020000U
-#define DMA_SxCR_PINCOS                      0x00008000U
-#define DMA_SxCR_MSIZE                       0x00006000U
-#define DMA_SxCR_MSIZE_0                     0x00002000U
-#define DMA_SxCR_MSIZE_1                     0x00004000U
-#define DMA_SxCR_PSIZE                       0x00001800U
-#define DMA_SxCR_PSIZE_0                     0x00000800U
-#define DMA_SxCR_PSIZE_1                     0x00001000U
-#define DMA_SxCR_MINC                        0x00000400U
-#define DMA_SxCR_PINC                        0x00000200U
-#define DMA_SxCR_CIRC                        0x00000100U
-#define DMA_SxCR_DIR                         0x000000C0U
-#define DMA_SxCR_DIR_0                       0x00000040U
-#define DMA_SxCR_DIR_1                       0x00000080U
-#define DMA_SxCR_PFCTRL                      0x00000020U
-#define DMA_SxCR_TCIE                        0x00000010U
-#define DMA_SxCR_HTIE                        0x00000008U
-#define DMA_SxCR_TEIE                        0x00000004U
-#define DMA_SxCR_DMEIE                       0x00000002U
-#define DMA_SxCR_EN                          0x00000001U
-
-/* Legacy defines */
-#define DMA_SxCR_ACK                         0x00100000U
-
-/********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            0x0000FFFFU
-#define DMA_SxNDT_0                          0x00000001U
-#define DMA_SxNDT_1                          0x00000002U
-#define DMA_SxNDT_2                          0x00000004U
-#define DMA_SxNDT_3                          0x00000008U
-#define DMA_SxNDT_4                          0x00000010U
-#define DMA_SxNDT_5                          0x00000020U
-#define DMA_SxNDT_6                          0x00000040U
-#define DMA_SxNDT_7                          0x00000080U
-#define DMA_SxNDT_8                          0x00000100U
-#define DMA_SxNDT_9                          0x00000200U
-#define DMA_SxNDT_10                         0x00000400U
-#define DMA_SxNDT_11                         0x00000800U
-#define DMA_SxNDT_12                         0x00001000U
-#define DMA_SxNDT_13                         0x00002000U
-#define DMA_SxNDT_14                         0x00004000U
-#define DMA_SxNDT_15                         0x00008000U
-
-/********************  Bits definition for DMA_SxFCR register  ****************/ 
-#define DMA_SxFCR_FEIE                       0x00000080U
-#define DMA_SxFCR_FS                         0x00000038U
-#define DMA_SxFCR_FS_0                       0x00000008U
-#define DMA_SxFCR_FS_1                       0x00000010U
-#define DMA_SxFCR_FS_2                       0x00000020U
-#define DMA_SxFCR_DMDIS                      0x00000004U
-#define DMA_SxFCR_FTH                        0x00000003U
-#define DMA_SxFCR_FTH_0                      0x00000001U
-#define DMA_SxFCR_FTH_1                      0x00000002U
-
-/********************  Bits definition for DMA_LISR register  *****************/ 
-#define DMA_LISR_TCIF3                       0x08000000U
-#define DMA_LISR_HTIF3                       0x04000000U
-#define DMA_LISR_TEIF3                       0x02000000U
-#define DMA_LISR_DMEIF3                      0x01000000U
-#define DMA_LISR_FEIF3                       0x00400000U
-#define DMA_LISR_TCIF2                       0x00200000U
-#define DMA_LISR_HTIF2                       0x00100000U
-#define DMA_LISR_TEIF2                       0x00080000U
-#define DMA_LISR_DMEIF2                      0x00040000U
-#define DMA_LISR_FEIF2                       0x00010000U
-#define DMA_LISR_TCIF1                       0x00000800U
-#define DMA_LISR_HTIF1                       0x00000400U
-#define DMA_LISR_TEIF1                       0x00000200U
-#define DMA_LISR_DMEIF1                      0x00000100U
-#define DMA_LISR_FEIF1                       0x00000040U
-#define DMA_LISR_TCIF0                       0x00000020U
-#define DMA_LISR_HTIF0                       0x00000010U
-#define DMA_LISR_TEIF0                       0x00000008U
-#define DMA_LISR_DMEIF0                      0x00000004U
-#define DMA_LISR_FEIF0                       0x00000001U
-
-/********************  Bits definition for DMA_HISR register  *****************/ 
-#define DMA_HISR_TCIF7                       0x08000000U
-#define DMA_HISR_HTIF7                       0x04000000U
-#define DMA_HISR_TEIF7                       0x02000000U
-#define DMA_HISR_DMEIF7                      0x01000000U
-#define DMA_HISR_FEIF7                       0x00400000U
-#define DMA_HISR_TCIF6                       0x00200000U
-#define DMA_HISR_HTIF6                       0x00100000U
-#define DMA_HISR_TEIF6                       0x00080000U
-#define DMA_HISR_DMEIF6                      0x00040000U
-#define DMA_HISR_FEIF6                       0x00010000U
-#define DMA_HISR_TCIF5                       0x00000800U
-#define DMA_HISR_HTIF5                       0x00000400U
-#define DMA_HISR_TEIF5                       0x00000200U
-#define DMA_HISR_DMEIF5                      0x00000100U
-#define DMA_HISR_FEIF5                       0x00000040U
-#define DMA_HISR_TCIF4                       0x00000020U
-#define DMA_HISR_HTIF4                       0x00000010U
-#define DMA_HISR_TEIF4                       0x00000008U
-#define DMA_HISR_DMEIF4                      0x00000004U
-#define DMA_HISR_FEIF4                       0x00000001U
-
-/********************  Bits definition for DMA_LIFCR register  ****************/ 
-#define DMA_LIFCR_CTCIF3                     0x08000000U
-#define DMA_LIFCR_CHTIF3                     0x04000000U
-#define DMA_LIFCR_CTEIF3                     0x02000000U
-#define DMA_LIFCR_CDMEIF3                    0x01000000U
-#define DMA_LIFCR_CFEIF3                     0x00400000U
-#define DMA_LIFCR_CTCIF2                     0x00200000U
-#define DMA_LIFCR_CHTIF2                     0x00100000U
-#define DMA_LIFCR_CTEIF2                     0x00080000U
-#define DMA_LIFCR_CDMEIF2                    0x00040000U
-#define DMA_LIFCR_CFEIF2                     0x00010000U
-#define DMA_LIFCR_CTCIF1                     0x00000800U
-#define DMA_LIFCR_CHTIF1                     0x00000400U
-#define DMA_LIFCR_CTEIF1                     0x00000200U
-#define DMA_LIFCR_CDMEIF1                    0x00000100U
-#define DMA_LIFCR_CFEIF1                     0x00000040U
-#define DMA_LIFCR_CTCIF0                     0x00000020U
-#define DMA_LIFCR_CHTIF0                     0x00000010U
-#define DMA_LIFCR_CTEIF0                     0x00000008U
-#define DMA_LIFCR_CDMEIF0                    0x00000004U
-#define DMA_LIFCR_CFEIF0                     0x00000001U
-
-/********************  Bits definition for DMA_HIFCR  register  ****************/ 
-#define DMA_HIFCR_CTCIF7                     0x08000000U
-#define DMA_HIFCR_CHTIF7                     0x04000000U
-#define DMA_HIFCR_CTEIF7                     0x02000000U
-#define DMA_HIFCR_CDMEIF7                    0x01000000U
-#define DMA_HIFCR_CFEIF7                     0x00400000U
-#define DMA_HIFCR_CTCIF6                     0x00200000U
-#define DMA_HIFCR_CHTIF6                     0x00100000U
-#define DMA_HIFCR_CTEIF6                     0x00080000U
-#define DMA_HIFCR_CDMEIF6                    0x00040000U
-#define DMA_HIFCR_CFEIF6                     0x00010000U
-#define DMA_HIFCR_CTCIF5                     0x00000800U
-#define DMA_HIFCR_CHTIF5                     0x00000400U
-#define DMA_HIFCR_CTEIF5                     0x00000200U
-#define DMA_HIFCR_CDMEIF5                    0x00000100U
-#define DMA_HIFCR_CFEIF5                     0x00000040U
-#define DMA_HIFCR_CTCIF4                     0x00000020U
-#define DMA_HIFCR_CHTIF4                     0x00000010U
-#define DMA_HIFCR_CTEIF4                     0x00000008U
-#define DMA_HIFCR_CDMEIF4                    0x00000004U
-#define DMA_HIFCR_CFEIF4                     0x00000001U
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                    External Interrupt/Event Controller                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    FLASH                                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    0x0000000FU
-#define FLASH_ACR_LATENCY_0WS                0x00000000U
-#define FLASH_ACR_LATENCY_1WS                0x00000001U
-#define FLASH_ACR_LATENCY_2WS                0x00000002U
-#define FLASH_ACR_LATENCY_3WS                0x00000003U
-#define FLASH_ACR_LATENCY_4WS                0x00000004U
-#define FLASH_ACR_LATENCY_5WS                0x00000005U
-#define FLASH_ACR_LATENCY_6WS                0x00000006U
-#define FLASH_ACR_LATENCY_7WS                0x00000007U
-
-#define FLASH_ACR_PRFTEN                     0x00000100U
-#define FLASH_ACR_ICEN                       0x00000200U
-#define FLASH_ACR_DCEN                       0x00000400U
-#define FLASH_ACR_ICRST                      0x00000800U
-#define FLASH_ACR_DCRST                      0x00001000U
-#define FLASH_ACR_BYTE0_ADDRESS              0x40023C00U
-#define FLASH_ACR_BYTE2_ADDRESS              0x40023C03U
-
-/*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         0x00000001U
-#define FLASH_SR_SOP                         0x00000002U
-#define FLASH_SR_WRPERR                      0x00000010U
-#define FLASH_SR_PGAERR                      0x00000020U
-#define FLASH_SR_PGPERR                      0x00000040U
-#define FLASH_SR_PGSERR                      0x00000080U
-#define FLASH_SR_BSY                         0x00010000U
-
-/*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          0x00000001U
-#define FLASH_CR_SER                         0x00000002U
-#define FLASH_CR_MER                         0x00000004U
-#define FLASH_CR_SNB                         0x000000F8U
-#define FLASH_CR_SNB_0                       0x00000008U
-#define FLASH_CR_SNB_1                       0x00000010U
-#define FLASH_CR_SNB_2                       0x00000020U
-#define FLASH_CR_SNB_3                       0x00000040U
-#define FLASH_CR_SNB_4                       0x00000080U
-#define FLASH_CR_PSIZE                       0x00000300U
-#define FLASH_CR_PSIZE_0                     0x00000100U
-#define FLASH_CR_PSIZE_1                     0x00000200U
-#define FLASH_CR_STRT                        0x00010000U
-#define FLASH_CR_EOPIE                       0x01000000U
-#define FLASH_CR_LOCK                        0x80000000U
-
-/*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                 0x00000001U
-#define FLASH_OPTCR_OPTSTRT                 0x00000002U
-#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
-#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
-#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
-
-#define FLASH_OPTCR_WDG_SW                  0x00000020U
-#define FLASH_OPTCR_nRST_STOP               0x00000040U
-#define FLASH_OPTCR_nRST_STDBY              0x00000080U
-#define FLASH_OPTCR_RDP                     0x0000FF00U
-#define FLASH_OPTCR_RDP_0                   0x00000100U
-#define FLASH_OPTCR_RDP_1                   0x00000200U
-#define FLASH_OPTCR_RDP_2                   0x00000400U
-#define FLASH_OPTCR_RDP_3                   0x00000800U
-#define FLASH_OPTCR_RDP_4                   0x00001000U
-#define FLASH_OPTCR_RDP_5                   0x00002000U
-#define FLASH_OPTCR_RDP_6                   0x00004000U
-#define FLASH_OPTCR_RDP_7                   0x00008000U
-#define FLASH_OPTCR_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR_nWRP_0                  0x00010000U
-#define FLASH_OPTCR_nWRP_1                  0x00020000U
-#define FLASH_OPTCR_nWRP_2                  0x00040000U
-#define FLASH_OPTCR_nWRP_3                  0x00080000U
-#define FLASH_OPTCR_nWRP_4                  0x00100000U
-#define FLASH_OPTCR_nWRP_5                  0x00200000U
-#define FLASH_OPTCR_nWRP_6                  0x00400000U
-#define FLASH_OPTCR_nWRP_7                  0x00800000U
-#define FLASH_OPTCR_nWRP_8                  0x01000000U
-#define FLASH_OPTCR_nWRP_9                  0x02000000U
-#define FLASH_OPTCR_nWRP_10                 0x04000000U
-#define FLASH_OPTCR_nWRP_11                 0x08000000U
-                                             
-/******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR1_nWRP_0                  0x00010000U
-#define FLASH_OPTCR1_nWRP_1                  0x00020000U
-#define FLASH_OPTCR1_nWRP_2                  0x00040000U
-#define FLASH_OPTCR1_nWRP_3                  0x00080000U
-#define FLASH_OPTCR1_nWRP_4                  0x00100000U
-#define FLASH_OPTCR1_nWRP_5                  0x00200000U
-#define FLASH_OPTCR1_nWRP_6                  0x00400000U
-#define FLASH_OPTCR1_nWRP_7                  0x00800000U
-#define FLASH_OPTCR1_nWRP_8                  0x01000000U
-#define FLASH_OPTCR1_nWRP_9                  0x02000000U
-#define FLASH_OPTCR1_nWRP_10                 0x04000000U
-#define FLASH_OPTCR1_nWRP_11                 0x08000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Flexible Static Memory Controller                        */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for FSMC_BCR1 register  *******************/
-#define  FSMC_BCR1_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FSMC_BCR1_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FSMC_BCR1_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FSMC_BCR1_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FSMC_BCR1_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FSMC_BCR1_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR1_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FSMC_BCR1_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FSMC_BCR1_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FSMC_BCR1_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FSMC_BCR1_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FSMC_BCR1_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FSMC_BCR1_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FSMC_BCR1_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FSMC_BCR1_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FSMC_BCR1_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FSMC_BCR1_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FSMC_BCR1_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FSMC_BCR1_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FSMC_BCR1_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FSMC_BCR1_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-#define  FSMC_BCR1_CCLKEN                    0x00100000U        /*!<Continous clock enable     */
-#define  FSMC_BCR1_WFDIS                     0x00200000U        /*!<Write FIFO Disable         */
-
-/******************  Bit definition for FSMC_BCR2 register  *******************/
-#define  FSMC_BCR2_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FSMC_BCR2_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FSMC_BCR2_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FSMC_BCR2_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FSMC_BCR2_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FSMC_BCR2_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR2_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FSMC_BCR2_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FSMC_BCR2_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FSMC_BCR2_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FSMC_BCR2_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FSMC_BCR2_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FSMC_BCR2_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FSMC_BCR2_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FSMC_BCR2_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FSMC_BCR2_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FSMC_BCR2_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FSMC_BCR2_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FSMC_BCR2_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FSMC_BCR2_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FSMC_BCR2_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FSMC_BCR3 register  *******************/
-#define  FSMC_BCR3_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FSMC_BCR3_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FSMC_BCR3_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FSMC_BCR3_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FSMC_BCR3_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FSMC_BCR3_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR3_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FSMC_BCR3_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FSMC_BCR3_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FSMC_BCR3_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FSMC_BCR3_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FSMC_BCR3_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FSMC_BCR3_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FSMC_BCR3_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FSMC_BCR3_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FSMC_BCR3_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FSMC_BCR3_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FSMC_BCR3_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FSMC_BCR3_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FSMC_BCR3_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FSMC_BCR3_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FSMC_BCR4 register  *******************/
-#define  FSMC_BCR4_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FSMC_BCR4_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FSMC_BCR4_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FSMC_BCR4_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FSMC_BCR4_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FSMC_BCR4_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR4_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FSMC_BCR4_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FSMC_BCR4_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FSMC_BCR4_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FSMC_BCR4_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FSMC_BCR4_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FSMC_BCR4_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FSMC_BCR4_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FSMC_BCR4_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FSMC_BCR4_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FSMC_BCR4_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FSMC_BCR4_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FSMC_BCR4_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FSMC_BCR4_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FSMC_BCR4_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FSMC_BTR1 register  ******************/
-#define  FSMC_BTR1_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR1_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FSMC_BTR1_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FSMC_BTR1_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FSMC_BTR1_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BTR1_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
-#define  FSMC_BTR1_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FSMC_BTR1_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FSMC_BTR1_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FSMC_BTR1_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BTR1_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BTR1_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FSMC_BTR1_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FSMC_BTR1_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FSMC_BTR1_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FSMC_BTR1_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FSMC_BTR1_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FSMC_BTR1_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FSMC_BTR1_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BTR1_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR1_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FSMC_BTR1_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FSMC_BTR1_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FSMC_BTR1_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BTR1_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR1_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FSMC_BTR1_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FSMC_BTR1_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FSMC_BTR1_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FSMC_BTR1_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR1_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FSMC_BTR1_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FSMC_BTR1_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FSMC_BTR1_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FSMC_BTR1_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR1_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FSMC_BTR1_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BTR2 register  *******************/
-#define  FSMC_BTR2_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR2_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FSMC_BTR2_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FSMC_BTR2_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FSMC_BTR2_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BTR2_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR2_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FSMC_BTR2_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FSMC_BTR2_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FSMC_BTR2_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BTR2_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BTR2_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FSMC_BTR2_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FSMC_BTR2_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FSMC_BTR2_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FSMC_BTR2_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FSMC_BTR2_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FSMC_BTR2_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FSMC_BTR2_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BTR2_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR2_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FSMC_BTR2_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FSMC_BTR2_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FSMC_BTR2_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BTR2_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR2_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FSMC_BTR2_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FSMC_BTR2_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FSMC_BTR2_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FSMC_BTR2_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR2_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FSMC_BTR2_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FSMC_BTR2_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FSMC_BTR2_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FSMC_BTR2_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR2_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FSMC_BTR2_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/*******************  Bit definition for FSMC_BTR3 register  *******************/
-#define  FSMC_BTR3_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR3_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FSMC_BTR3_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FSMC_BTR3_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FSMC_BTR3_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BTR3_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR3_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FSMC_BTR3_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FSMC_BTR3_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FSMC_BTR3_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BTR3_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BTR3_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FSMC_BTR3_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FSMC_BTR3_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FSMC_BTR3_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FSMC_BTR3_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FSMC_BTR3_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FSMC_BTR3_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FSMC_BTR3_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BTR3_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR3_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FSMC_BTR3_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FSMC_BTR3_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FSMC_BTR3_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BTR3_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR3_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FSMC_BTR3_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FSMC_BTR3_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FSMC_BTR3_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FSMC_BTR3_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR3_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FSMC_BTR3_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FSMC_BTR3_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FSMC_BTR3_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FSMC_BTR3_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR3_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FSMC_BTR3_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BTR4 register  *******************/
-#define  FSMC_BTR4_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR4_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FSMC_BTR4_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FSMC_BTR4_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FSMC_BTR4_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BTR4_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR4_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FSMC_BTR4_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FSMC_BTR4_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FSMC_BTR4_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BTR4_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BTR4_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FSMC_BTR4_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FSMC_BTR4_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FSMC_BTR4_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FSMC_BTR4_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FSMC_BTR4_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FSMC_BTR4_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FSMC_BTR4_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BTR4_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR4_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FSMC_BTR4_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FSMC_BTR4_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FSMC_BTR4_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BTR4_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR4_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FSMC_BTR4_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FSMC_BTR4_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FSMC_BTR4_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FSMC_BTR4_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR4_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FSMC_BTR4_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FSMC_BTR4_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FSMC_BTR4_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FSMC_BTR4_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR4_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FSMC_BTR4_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR1 register  ******************/
-#define  FSMC_BWTR1_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR1_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FSMC_BWTR1_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FSMC_BWTR1_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FSMC_BWTR1_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BWTR1_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR1_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FSMC_BWTR1_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FSMC_BWTR1_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FSMC_BWTR1_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BWTR1_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BWTR1_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FSMC_BWTR1_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FSMC_BWTR1_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FSMC_BWTR1_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FSMC_BWTR1_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FSMC_BWTR1_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FSMC_BWTR1_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FSMC_BWTR1_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BWTR1_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FSMC_BWTR1_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FSMC_BWTR1_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FSMC_BWTR1_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FSMC_BWTR1_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BWTR1_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR1_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FSMC_BWTR1_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR2 register  ******************/
-#define  FSMC_BWTR2_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR2_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FSMC_BWTR2_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FSMC_BWTR2_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FSMC_BWTR2_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BWTR2_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR2_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FSMC_BWTR2_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FSMC_BWTR2_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FSMC_BWTR2_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BWTR2_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BWTR2_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FSMC_BWTR2_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FSMC_BWTR2_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FSMC_BWTR2_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FSMC_BWTR2_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FSMC_BWTR2_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FSMC_BWTR2_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FSMC_BWTR2_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BWTR2_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FSMC_BWTR2_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FSMC_BWTR2_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FSMC_BWTR2_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FSMC_BWTR2_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BWTR2_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR2_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FSMC_BWTR2_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR3 register  ******************/
-#define  FSMC_BWTR3_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR3_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FSMC_BWTR3_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FSMC_BWTR3_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FSMC_BWTR3_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BWTR3_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR3_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FSMC_BWTR3_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FSMC_BWTR3_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FSMC_BWTR3_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BWTR3_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BWTR3_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FSMC_BWTR3_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FSMC_BWTR3_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FSMC_BWTR3_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FSMC_BWTR3_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FSMC_BWTR3_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FSMC_BWTR3_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FSMC_BWTR3_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BWTR3_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FSMC_BWTR3_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FSMC_BWTR3_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FSMC_BWTR3_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FSMC_BWTR3_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BWTR3_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR3_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FSMC_BWTR3_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR4 register  ******************/
-#define  FSMC_BWTR4_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR4_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FSMC_BWTR4_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FSMC_BWTR4_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FSMC_BWTR4_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BWTR4_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR4_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FSMC_BWTR4_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FSMC_BWTR4_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FSMC_BWTR4_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BWTR4_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BWTR4_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FSMC_BWTR4_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FSMC_BWTR4_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FSMC_BWTR4_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FSMC_BWTR4_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FSMC_BWTR4_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FSMC_BWTR4_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FSMC_BWTR4_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BWTR4_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FSMC_BWTR4_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FSMC_BWTR4_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FSMC_BWTR4_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FSMC_BWTR4_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BWTR4_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR4_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FSMC_BWTR4_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    0x00000003U
-#define GPIO_MODER_MODER0_0                  0x00000001U
-#define GPIO_MODER_MODER0_1                  0x00000002U
-
-#define GPIO_MODER_MODER1                    0x0000000CU
-#define GPIO_MODER_MODER1_0                  0x00000004U
-#define GPIO_MODER_MODER1_1                  0x00000008U
-
-#define GPIO_MODER_MODER2                    0x00000030U
-#define GPIO_MODER_MODER2_0                  0x00000010U
-#define GPIO_MODER_MODER2_1                  0x00000020U
-
-#define GPIO_MODER_MODER3                    0x000000C0U
-#define GPIO_MODER_MODER3_0                  0x00000040U
-#define GPIO_MODER_MODER3_1                  0x00000080U
-
-#define GPIO_MODER_MODER4                    0x00000300U
-#define GPIO_MODER_MODER4_0                  0x00000100U
-#define GPIO_MODER_MODER4_1                  0x00000200U
-
-#define GPIO_MODER_MODER5                    0x00000C00U
-#define GPIO_MODER_MODER5_0                  0x00000400U
-#define GPIO_MODER_MODER5_1                  0x00000800U
-
-#define GPIO_MODER_MODER6                    0x00003000U
-#define GPIO_MODER_MODER6_0                  0x00001000U
-#define GPIO_MODER_MODER6_1                  0x00002000U
-
-#define GPIO_MODER_MODER7                    0x0000C000U
-#define GPIO_MODER_MODER7_0                  0x00004000U
-#define GPIO_MODER_MODER7_1                  0x00008000U
-
-#define GPIO_MODER_MODER8                    0x00030000U
-#define GPIO_MODER_MODER8_0                  0x00010000U
-#define GPIO_MODER_MODER8_1                  0x00020000U
-
-#define GPIO_MODER_MODER9                    0x000C0000U
-#define GPIO_MODER_MODER9_0                  0x00040000U
-#define GPIO_MODER_MODER9_1                  0x00080000U
-
-#define GPIO_MODER_MODER10                   0x00300000U
-#define GPIO_MODER_MODER10_0                 0x00100000U
-#define GPIO_MODER_MODER10_1                 0x00200000U
-
-#define GPIO_MODER_MODER11                   0x00C00000U
-#define GPIO_MODER_MODER11_0                 0x00400000U
-#define GPIO_MODER_MODER11_1                 0x00800000U
-
-#define GPIO_MODER_MODER12                   0x03000000U
-#define GPIO_MODER_MODER12_0                 0x01000000U
-#define GPIO_MODER_MODER12_1                 0x02000000U
-
-#define GPIO_MODER_MODER13                   0x0C000000U
-#define GPIO_MODER_MODER13_0                 0x04000000U
-#define GPIO_MODER_MODER13_1                 0x08000000U
-
-#define GPIO_MODER_MODER14                   0x30000000U
-#define GPIO_MODER_MODER14_0                 0x10000000U
-#define GPIO_MODER_MODER14_1                 0x20000000U
-
-#define GPIO_MODER_MODER15                   0xC0000000U
-#define GPIO_MODER_MODER15_0                 0x40000000U
-#define GPIO_MODER_MODER15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     0x00000001U
-#define GPIO_OTYPER_OT_1                     0x00000002U
-#define GPIO_OTYPER_OT_2                     0x00000004U
-#define GPIO_OTYPER_OT_3                     0x00000008U
-#define GPIO_OTYPER_OT_4                     0x00000010U
-#define GPIO_OTYPER_OT_5                     0x00000020U
-#define GPIO_OTYPER_OT_6                     0x00000040U
-#define GPIO_OTYPER_OT_7                     0x00000080U
-#define GPIO_OTYPER_OT_8                     0x00000100U
-#define GPIO_OTYPER_OT_9                     0x00000200U
-#define GPIO_OTYPER_OT_10                    0x00000400U
-#define GPIO_OTYPER_OT_11                    0x00000800U
-#define GPIO_OTYPER_OT_12                    0x00001000U
-#define GPIO_OTYPER_OT_13                    0x00002000U
-#define GPIO_OTYPER_OT_14                    0x00004000U
-#define GPIO_OTYPER_OT_15                    0x00008000U
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
-#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
-#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
-
-#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
-#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
-#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
-
-#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
-#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
-#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
-
-#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
-#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
-#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
-
-#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
-#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
-#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
-
-#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
-#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
-#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
-
-#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
-#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
-#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
-
-#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
-#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
-#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
-
-#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
-#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
-#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
-
-#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
-#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
-#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
-
-#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
-#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
-#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
-
-#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
-#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
-#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
-
-#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
-#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
-#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
-
-#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
-#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
-#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
-
-#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
-#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
-#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
-
-#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
-#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
-#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    0x00000003U
-#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
-#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
-
-#define GPIO_PUPDR_PUPDR1                    0x0000000CU
-#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
-#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
-
-#define GPIO_PUPDR_PUPDR2                    0x00000030U
-#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
-#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
-
-#define GPIO_PUPDR_PUPDR3                    0x000000C0U
-#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
-#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
-
-#define GPIO_PUPDR_PUPDR4                    0x00000300U
-#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
-#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
-
-#define GPIO_PUPDR_PUPDR5                    0x00000C00U
-#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
-#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
-
-#define GPIO_PUPDR_PUPDR6                    0x00003000U
-#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
-#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
-
-#define GPIO_PUPDR_PUPDR7                    0x0000C000U
-#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
-#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
-
-#define GPIO_PUPDR_PUPDR8                    0x00030000U
-#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
-#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
-
-#define GPIO_PUPDR_PUPDR9                    0x000C0000U
-#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
-#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
-
-#define GPIO_PUPDR_PUPDR10                   0x00300000U
-#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
-#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
-
-#define GPIO_PUPDR_PUPDR11                   0x00C00000U
-#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
-#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
-
-#define GPIO_PUPDR_PUPDR12                   0x03000000U
-#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
-#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
-
-#define GPIO_PUPDR_PUPDR13                   0x0C000000U
-#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
-#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
-
-#define GPIO_PUPDR_PUPDR14                   0x30000000U
-#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
-#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
-
-#define GPIO_PUPDR_PUPDR15                   0xC0000000U
-#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
-#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       0x00000001U
-#define GPIO_IDR_IDR_1                       0x00000002U
-#define GPIO_IDR_IDR_2                       0x00000004U
-#define GPIO_IDR_IDR_3                       0x00000008U
-#define GPIO_IDR_IDR_4                       0x00000010U
-#define GPIO_IDR_IDR_5                       0x00000020U
-#define GPIO_IDR_IDR_6                       0x00000040U
-#define GPIO_IDR_IDR_7                       0x00000080U
-#define GPIO_IDR_IDR_8                       0x00000100U
-#define GPIO_IDR_IDR_9                       0x00000200U
-#define GPIO_IDR_IDR_10                      0x00000400U
-#define GPIO_IDR_IDR_11                      0x00000800U
-#define GPIO_IDR_IDR_12                      0x00001000U
-#define GPIO_IDR_IDR_13                      0x00002000U
-#define GPIO_IDR_IDR_14                      0x00004000U
-#define GPIO_IDR_IDR_15                      0x00008000U
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       0x00000001U
-#define GPIO_ODR_ODR_1                       0x00000002U
-#define GPIO_ODR_ODR_2                       0x00000004U
-#define GPIO_ODR_ODR_3                       0x00000008U
-#define GPIO_ODR_ODR_4                       0x00000010U
-#define GPIO_ODR_ODR_5                       0x00000020U
-#define GPIO_ODR_ODR_6                       0x00000040U
-#define GPIO_ODR_ODR_7                       0x00000080U
-#define GPIO_ODR_ODR_8                       0x00000100U
-#define GPIO_ODR_ODR_9                       0x00000200U
-#define GPIO_ODR_ODR_10                      0x00000400U
-#define GPIO_ODR_ODR_11                      0x00000800U
-#define GPIO_ODR_ODR_12                      0x00001000U
-#define GPIO_ODR_ODR_13                      0x00002000U
-#define GPIO_ODR_ODR_14                      0x00004000U
-#define GPIO_ODR_ODR_15                      0x00008000U
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       0x00000001U
-#define GPIO_BSRR_BS_1                       0x00000002U
-#define GPIO_BSRR_BS_2                       0x00000004U
-#define GPIO_BSRR_BS_3                       0x00000008U
-#define GPIO_BSRR_BS_4                       0x00000010U
-#define GPIO_BSRR_BS_5                       0x00000020U
-#define GPIO_BSRR_BS_6                       0x00000040U
-#define GPIO_BSRR_BS_7                       0x00000080U
-#define GPIO_BSRR_BS_8                       0x00000100U
-#define GPIO_BSRR_BS_9                       0x00000200U
-#define GPIO_BSRR_BS_10                      0x00000400U
-#define GPIO_BSRR_BS_11                      0x00000800U
-#define GPIO_BSRR_BS_12                      0x00001000U
-#define GPIO_BSRR_BS_13                      0x00002000U
-#define GPIO_BSRR_BS_14                      0x00004000U
-#define GPIO_BSRR_BS_15                      0x00008000U
-#define GPIO_BSRR_BR_0                       0x00010000U
-#define GPIO_BSRR_BR_1                       0x00020000U
-#define GPIO_BSRR_BR_2                       0x00040000U
-#define GPIO_BSRR_BR_3                       0x00080000U
-#define GPIO_BSRR_BR_4                       0x00100000U
-#define GPIO_BSRR_BR_5                       0x00200000U
-#define GPIO_BSRR_BR_6                       0x00400000U
-#define GPIO_BSRR_BR_7                       0x00800000U
-#define GPIO_BSRR_BR_8                       0x01000000U
-#define GPIO_BSRR_BR_9                       0x02000000U
-#define GPIO_BSRR_BR_10                      0x04000000U
-#define GPIO_BSRR_BR_11                      0x08000000U
-#define GPIO_BSRR_BR_12                      0x10000000U
-#define GPIO_BSRR_BR_13                      0x20000000U
-#define GPIO_BSRR_BR_14                      0x40000000U
-#define GPIO_BSRR_BR_15                      0x80000000U
-
-/****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0                       0x00000001U
-#define GPIO_LCKR_LCK1                       0x00000002U
-#define GPIO_LCKR_LCK2                       0x00000004U
-#define GPIO_LCKR_LCK3                       0x00000008U
-#define GPIO_LCKR_LCK4                       0x00000010U
-#define GPIO_LCKR_LCK5                       0x00000020U
-#define GPIO_LCKR_LCK6                       0x00000040U
-#define GPIO_LCKR_LCK7                       0x00000080U
-#define GPIO_LCKR_LCK8                       0x00000100U
-#define GPIO_LCKR_LCK9                       0x00000200U
-#define GPIO_LCKR_LCK10                      0x00000400U
-#define GPIO_LCKR_LCK11                      0x00000800U
-#define GPIO_LCKR_LCK12                      0x00001000U
-#define GPIO_LCKR_LCK13                      0x00002000U
-#define GPIO_LCKR_LCK14                      0x00004000U
-#define GPIO_LCKR_LCK15                      0x00008000U
-#define GPIO_LCKR_LCKK                       0x00010000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Inter-integrated Circuit Interface                    */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          0x00000001U     /*!<Peripheral Enable                             */
-#define  I2C_CR1_SMBUS                       0x00000002U     /*!<SMBus Mode                                    */
-#define  I2C_CR1_SMBTYPE                     0x00000008U     /*!<SMBus Type                                    */
-#define  I2C_CR1_ENARP                       0x00000010U     /*!<ARP Enable                                    */
-#define  I2C_CR1_ENPEC                       0x00000020U     /*!<PEC Enable                                    */
-#define  I2C_CR1_ENGC                        0x00000040U     /*!<General Call Enable                           */
-#define  I2C_CR1_NOSTRETCH                   0x00000080U     /*!<Clock Stretching Disable (Slave mode)  */
-#define  I2C_CR1_START                       0x00000100U     /*!<Start Generation                              */
-#define  I2C_CR1_STOP                        0x00000200U     /*!<Stop Generation                               */
-#define  I2C_CR1_ACK                         0x00000400U     /*!<Acknowledge Enable                            */
-#define  I2C_CR1_POS                         0x00000800U     /*!<Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         0x00001000U     /*!<Packet Error Checking                         */
-#define  I2C_CR1_ALERT                       0x00002000U     /*!<SMBus Alert                                   */
-#define  I2C_CR1_SWRST                       0x00008000U     /*!<Software Reset                                */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        0x0000003FU     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
-#define  I2C_CR2_FREQ_0                      0x00000001U     /*!<Bit 0 */
-#define  I2C_CR2_FREQ_1                      0x00000002U     /*!<Bit 1 */
-#define  I2C_CR2_FREQ_2                      0x00000004U     /*!<Bit 2 */
-#define  I2C_CR2_FREQ_3                      0x00000008U     /*!<Bit 3 */
-#define  I2C_CR2_FREQ_4                      0x00000010U     /*!<Bit 4 */
-#define  I2C_CR2_FREQ_5                      0x00000020U     /*!<Bit 5 */
-
-#define  I2C_CR2_ITERREN                     0x00000100U     /*!<Error Interrupt Enable  */
-#define  I2C_CR2_ITEVTEN                     0x00000200U     /*!<Event Interrupt Enable  */
-#define  I2C_CR2_ITBUFEN                     0x00000400U     /*!<Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       0x00000800U     /*!<DMA Requests Enable     */
-#define  I2C_CR2_LAST                        0x00001000U     /*!<DMA Last Transfer       */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     0x000000FEU     /*!<Interface Address */
-#define  I2C_OAR1_ADD8_9                     0x00000300U     /*!<Interface Address */
-
-#define  I2C_OAR1_ADD0                       0x00000001U     /*!<Bit 0 */
-#define  I2C_OAR1_ADD1                       0x00000002U     /*!<Bit 1 */
-#define  I2C_OAR1_ADD2                       0x00000004U     /*!<Bit 2 */
-#define  I2C_OAR1_ADD3                       0x00000008U     /*!<Bit 3 */
-#define  I2C_OAR1_ADD4                       0x00000010U     /*!<Bit 4 */
-#define  I2C_OAR1_ADD5                       0x00000020U     /*!<Bit 5 */
-#define  I2C_OAR1_ADD6                       0x00000040U     /*!<Bit 6 */
-#define  I2C_OAR1_ADD7                       0x00000080U     /*!<Bit 7 */
-#define  I2C_OAR1_ADD8                       0x00000100U     /*!<Bit 8 */
-#define  I2C_OAR1_ADD9                       0x00000200U     /*!<Bit 9 */
-
-#define  I2C_OAR1_ADDMODE                    0x00008000U     /*!<Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     0x00000001U        /*!<Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       0x000000FEU        /*!<Interface address           */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           0x000000FFU        /*!<8-bit Data Register         */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          0x00000001U     /*!<Start Bit (Master mode)                  */
-#define  I2C_SR1_ADDR                        0x00000002U     /*!<Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         0x00000004U     /*!<Byte Transfer Finished                          */
-#define  I2C_SR1_ADD10                       0x00000008U     /*!<10-bit header sent (Master mode)         */
-#define  I2C_SR1_STOPF                       0x00000010U     /*!<Stop detection (Slave mode)              */
-#define  I2C_SR1_RXNE                        0x00000040U     /*!<Data Register not Empty (receivers)      */
-#define  I2C_SR1_TXE                         0x00000080U     /*!<Data Register Empty (transmitters)       */
-#define  I2C_SR1_BERR                        0x00000100U     /*!<Bus Error                                       */
-#define  I2C_SR1_ARLO                        0x00000200U     /*!<Arbitration Lost (master mode)           */
-#define  I2C_SR1_AF                          0x00000400U     /*!<Acknowledge Failure                             */
-#define  I2C_SR1_OVR                         0x00000800U     /*!<Overrun/Underrun                                */
-#define  I2C_SR1_PECERR                      0x00001000U     /*!<PEC Error in reception                          */
-#define  I2C_SR1_TIMEOUT                     0x00004000U     /*!<Timeout or Tlow Error                           */
-#define  I2C_SR1_SMBALERT                    0x00008000U     /*!<SMBus Alert                                     */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         0x00000001U     /*!<Master/Slave                              */
-#define  I2C_SR2_BUSY                        0x00000002U     /*!<Bus Busy                                  */
-#define  I2C_SR2_TRA                         0x00000004U     /*!<Transmitter/Receiver                      */
-#define  I2C_SR2_GENCALL                     0x00000010U     /*!<General Call Address (Slave mode)  */
-#define  I2C_SR2_SMBDEFAULT                  0x00000020U     /*!<SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     0x00000040U     /*!<SMBus Host Header (Slave mode)     */
-#define  I2C_SR2_DUALF                       0x00000080U     /*!<Dual Flag (Slave mode)             */
-#define  I2C_SR2_PEC                         0x0000FF00U     /*!<Packet Error Checking Register            */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         0x00000FFFU     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        0x00004000U     /*!<Fast Mode Duty Cycle                                       */
-#define  I2C_CCR_FS                          0x00008000U     /*!<I2C Master Mode Selection                                  */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     0x0000003FU     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************  Bit definition for I2C_FLTR register  *******************/
-#define  I2C_FLTR_DNF                        0x0000000FU     /*!<Digital Noise Filter */
-#define  I2C_FLTR_ANOFF                      0x00000010U     /*!<Analog Noise Filter OFF */
-
-/******************************************************************************/
-/*                                                                            */
-/*        Fast Mode Plus Inter-integrated Circuit Interface (I2C)             */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define  FMPI2C_CR1_PE                        0x00000001U        /*!< Peripheral enable                   */
-#define  FMPI2C_CR1_TXIE                      0x00000002U        /*!< TX interrupt enable                 */
-#define  FMPI2C_CR1_RXIE                      0x00000004U        /*!< RX interrupt enable                 */
-#define  FMPI2C_CR1_ADDRIE                    0x00000008U        /*!< Address match interrupt enable      */
-#define  FMPI2C_CR1_NACKIE                    0x00000010U        /*!< NACK received interrupt enable      */
-#define  FMPI2C_CR1_STOPIE                    0x00000020U        /*!< STOP detection interrupt enable     */
-#define  FMPI2C_CR1_TCIE                      0x00000040U        /*!< Transfer complete interrupt enable  */
-#define  FMPI2C_CR1_ERRIE                     0x00000080U        /*!< Errors interrupt enable             */
-#define  FMPI2C_CR1_DFN                       0x00000F00U        /*!< Digital noise filter                */
-#define  FMPI2C_CR1_ANFOFF                    0x00001000U        /*!< Analog noise filter OFF             */
-#define  FMPI2C_CR1_TXDMAEN                   0x00004000U        /*!< DMA transmission requests enable    */
-#define  FMPI2C_CR1_RXDMAEN                   0x00008000U        /*!< DMA reception requests enable       */
-#define  FMPI2C_CR1_SBC                       0x00010000U        /*!< Slave byte control                  */
-#define  FMPI2C_CR1_NOSTRETCH                 0x00020000U        /*!< Clock stretching disable            */
-#define  FMPI2C_CR1_GCEN                      0x00080000U        /*!< General call enable                 */
-#define  FMPI2C_CR1_SMBHEN                    0x00100000U        /*!< SMBus host address enable           */
-#define  FMPI2C_CR1_SMBDEN                    0x00200000U        /*!< SMBus device default address enable */
-#define  FMPI2C_CR1_ALERTEN                   0x00400000U        /*!< SMBus alert enable                  */
-#define  FMPI2C_CR1_PECEN                     0x00800000U        /*!< PEC enable                          */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define  FMPI2C_CR2_SADD                      0x000003FFU        /*!< Slave address (master mode)                             */
-#define  FMPI2C_CR2_RD_WRN                    0x00000400U        /*!< Transfer direction (master mode)                        */
-#define  FMPI2C_CR2_ADD10                     0x00000800U        /*!< 10-bit addressing mode (master mode)                    */
-#define  FMPI2C_CR2_HEAD10R                   0x00001000U        /*!< 10-bit address header only read direction (master mode) */
-#define  FMPI2C_CR2_START                     0x00002000U        /*!< START generation                                        */
-#define  FMPI2C_CR2_STOP                      0x00004000U        /*!< STOP generation (master mode)                           */
-#define  FMPI2C_CR2_NACK                      0x00008000U        /*!< NACK generation (slave mode)                            */
-#define  FMPI2C_CR2_NBYTES                    0x00FF0000U        /*!< Number of bytes                                         */
-#define  FMPI2C_CR2_RELOAD                    0x01000000U        /*!< NBYTES reload mode                                      */
-#define  FMPI2C_CR2_AUTOEND                   0x02000000U        /*!< Automatic end mode (master mode)                        */
-#define  FMPI2C_CR2_PECBYTE                   0x04000000U        /*!< Packet error checking byte                              */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define  FMPI2C_OAR1_OA1                      0x000003FFU        /*!< Interface own address 1   */
-#define  FMPI2C_OAR1_OA1MODE                  0x00000400U        /*!< Own address 1 10-bit mode */
-#define  FMPI2C_OAR1_OA1EN                    0x00008000U        /*!< Own address 1 enable      */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define  FMPI2C_OAR2_OA2                      0x000000FEU        /*!< Interface own address 2 */
-#define  FMPI2C_OAR2_OA2MSK                   0x00000700U        /*!< Own address 2 masks     */
-#define  FMPI2C_OAR2_OA2EN                    0x00008000U        /*!< Own address 2 enable    */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define  FMPI2C_TIMINGR_SCLL                  0x000000FFU        /*!< SCL low period (master mode)  */
-#define  FMPI2C_TIMINGR_SCLH                  0x0000FF00U        /*!< SCL high period (master mode) */
-#define  FMPI2C_TIMINGR_SDADEL                0x000F0000U        /*!< Data hold time                */
-#define  FMPI2C_TIMINGR_SCLDEL                0x00F00000U        /*!< Data setup time               */
-#define  FMPI2C_TIMINGR_PRESC                 0xF0000000U        /*!< Timings prescaler             */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define  FMPI2C_TIMEOUTR_TIMEOUTA             0x00000FFFU        /*!< Bus timeout A                 */
-#define  FMPI2C_TIMEOUTR_TIDLE                0x00001000U        /*!< Idle clock timeout detection  */
-#define  FMPI2C_TIMEOUTR_TIMOUTEN             0x00008000U        /*!< Clock timeout enable          */
-#define  FMPI2C_TIMEOUTR_TIMEOUTB             0x0FFF0000U        /*!< Bus timeout B                 */
-#define  FMPI2C_TIMEOUTR_TEXTEN               0x80000000U        /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define  FMPI2C_ISR_TXE                       0x00000001U        /*!< Transmit data register empty     */
-#define  FMPI2C_ISR_TXIS                      0x00000002U        /*!< Transmit interrupt status        */
-#define  FMPI2C_ISR_RXNE                      0x00000004U        /*!< Receive data register not empty  */
-#define  FMPI2C_ISR_ADDR                      0x00000008U        /*!< Address matched (slave mode)     */
-#define  FMPI2C_ISR_NACKF                     0x00000010U        /*!< NACK received flag               */
-#define  FMPI2C_ISR_STOPF                     0x00000020U        /*!< STOP detection flag              */
-#define  FMPI2C_ISR_TC                        0x00000040U        /*!< Transfer complete (master mode)  */
-#define  FMPI2C_ISR_TCR                       0x00000080U        /*!< Transfer complete reload         */
-#define  FMPI2C_ISR_BERR                      0x00000100U        /*!< Bus error                        */
-#define  FMPI2C_ISR_ARLO                      0x00000200U        /*!< Arbitration lost                 */
-#define  FMPI2C_ISR_OVR                       0x00000400U        /*!< Overrun/Underrun                 */
-#define  FMPI2C_ISR_PECERR                    0x00000800U        /*!< PEC error in reception           */
-#define  FMPI2C_ISR_TIMEOUT                   0x00001000U        /*!< Timeout or Tlow detection flag   */
-#define  FMPI2C_ISR_ALERT                     0x00002000U        /*!< SMBus alert                      */
-#define  FMPI2C_ISR_BUSY                      0x00008000U        /*!< Bus busy                         */
-#define  FMPI2C_ISR_DIR                       0x00010000U        /*!< Transfer direction (slave mode)  */
-#define  FMPI2C_ISR_ADDCODE                   0x00FE0000U        /*!< Address match code (slave mode)  */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define  FMPI2C_ICR_ADDRCF                    0x00000008U        /*!< Address matched clear flag  */
-#define  FMPI2C_ICR_NACKCF                    0x00000010U        /*!< NACK clear flag             */
-#define  FMPI2C_ICR_STOPCF                    0x00000020U        /*!< STOP detection clear flag   */
-#define  FMPI2C_ICR_BERRCF                    0x00000100U        /*!< Bus error clear flag        */
-#define  FMPI2C_ICR_ARLOCF                    0x00000200U        /*!< Arbitration lost clear flag */
-#define  FMPI2C_ICR_OVRCF                     0x00000400U        /*!< Overrun/Underrun clear flag */
-#define  FMPI2C_ICR_PECCF                     0x00000800U        /*!< PAC error clear flag        */
-#define  FMPI2C_ICR_TIMOUTCF                  0x00001000U        /*!< Timeout clear flag          */
-#define  FMPI2C_ICR_ALERTCF                   0x00002000U        /*!< Alert clear flag            */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define  FMPI2C_PECR_PEC                      0x000000FFU        /*!< PEC register */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define  FMPI2C_RXDR_RXDATA                   0x000000FFU        /*!< 8-bit receive data */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define  FMPI2C_TXDR_TXDATA                   0x000000FFU        /*!< 8-bit transmit data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Independent WATCHDOG                             */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         0x01U               /*!<Watchdog prescaler value update      */
-#define  IWDG_SR_RVU                         0x02U               /*!<Watchdog counter reload value update */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                             Power Control                                  */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
-#define  PWR_CR_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
-#define  PWR_CR_CWUF                         0x00000004U     /*!< Clear Wakeup Flag                   */
-#define  PWR_CR_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
-#define  PWR_CR_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
-
-#define  PWR_CR_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        0x00000020U     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        0x00000040U     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        0x00000080U     /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
-
-#define  PWR_CR_DBP                          0x00000100U     /*!< Disable Backup Domain write protection                     */
-#define  PWR_CR_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                              */
-#define  PWR_CR_LPLVDS                       0x00000400U     /*!< Low Power Regulator Low Voltage in Deep Sleep mode         */
-#define  PWR_CR_MRLVDS                       0x00000800U     /*!< Main Regulator Low Voltage in Deep Sleep mode              */
-#define  PWR_CR_ADCDC1                       0x00002000U     /*!< Refer to AN4073 on how to use this bit                     */
-
-#define  PWR_CR_VOS                          0x0000C000U     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
-#define  PWR_CR_VOS_0                        0x00004000U     /*!< Bit 0 */
-#define  PWR_CR_VOS_1                        0x00008000U     /*!< Bit 1 */
-
-#define  PWR_CR_FMSSR                        0x00100000U     /*!< Flash Memory Sleep System Run        */
-#define  PWR_CR_FISSR                        0x00200000U     /*!< Flash Interface Stop while System Run */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         0x00000001U     /*!< Wakeup Flag                                      */
-#define  PWR_CSR_SBF                         0x00000002U     /*!< Standby Flag                                     */
-#define  PWR_CSR_PVDO                        0x00000004U     /*!< PVD Output                                       */
-#define  PWR_CSR_BRR                         0x00000008U     /*!< Backup regulator ready                           */
-#define  PWR_CSR_EWUP                        0x00000100U     /*!< Enable WKUP pin                                  */
-#define  PWR_CSR_BRE                         0x00000200U     /*!< Backup regulator enable                          */
-#define  PWR_CSR_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
-/******************************************************************************/
-/*                                                                            */
-/*                                    QUADSPI                                 */
-/*                                                                            */
-/******************************************************************************/
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
- */
-#define  QSPI1_V2_1L                                                      /*!< QSPI Virtual Version             */
-
-/*****************  Bit definition for QUADSPI_CR register  *******************/
-#define  QUADSPI_CR_EN                           0x00000001U            /*!< Enable                             */
-#define  QUADSPI_CR_ABORT                        0x00000002U            /*!< Abort request                      */
-#define  QUADSPI_CR_DMAEN                        0x00000004U            /*!< DMA Enable                         */
-#define  QUADSPI_CR_TCEN                         0x00000008U            /*!< Timeout Counter Enable             */
-#define  QUADSPI_CR_SSHIFT                       0x00000010U            /*!< SSHIFT Sample Shift                */
-#define  QUADSPI_CR_DFM                          0x00000040U            /*!< Dual Flash Mode                    */
-#define  QUADSPI_CR_FSEL                         0x00000080U            /*!< Flash Select                       */
-#define  QUADSPI_CR_FTHRES                       0x00001F00U            /*!< FTHRES[3:0] FIFO Level             */
-#define  QUADSPI_CR_FTHRES_0                     0x00000100U            /*!< Bit 0 */
-#define  QUADSPI_CR_FTHRES_1                     0x00000200U            /*!< Bit 1 */
-#define  QUADSPI_CR_FTHRES_2                     0x00000400U            /*!< Bit 2 */
-#define  QUADSPI_CR_FTHRES_3                     0x00000800U            /*!< Bit 3 */
-#define  QUADSPI_CR_FTHRES_4                     0x00001000U            /*!< Bit 4 */
-#define  QUADSPI_CR_TEIE                         0x00010000U            /*!< Transfer Error Interrupt Enable    */
-#define  QUADSPI_CR_TCIE                         0x00020000U            /*!< Transfer Complete Interrupt Enable */
-#define  QUADSPI_CR_FTIE                         0x00040000U            /*!< FIFO Threshold Interrupt Enable    */
-#define  QUADSPI_CR_SMIE                         0x00080000U            /*!< Status Match Interrupt Enable      */
-#define  QUADSPI_CR_TOIE                         0x00100000U            /*!< TimeOut Interrupt Enable           */
-#define  QUADSPI_CR_APMS                         0x00400000U            /*!< Bit 1 */
-#define  QUADSPI_CR_PMM                          0x00800000U            /*!< Polling Match Mode                 */
-#define  QUADSPI_CR_PRESCALER                    0xFF000000U            /*!< PRESCALER[7:0] Clock prescaler     */
-#define  QUADSPI_CR_PRESCALER_0                  0x01000000U            /*!< Bit 0 */
-#define  QUADSPI_CR_PRESCALER_1                  0x02000000U            /*!< Bit 1 */
-#define  QUADSPI_CR_PRESCALER_2                  0x04000000U            /*!< Bit 2 */
-#define  QUADSPI_CR_PRESCALER_3                  0x08000000U            /*!< Bit 3 */
-#define  QUADSPI_CR_PRESCALER_4                  0x10000000U            /*!< Bit 4 */
-#define  QUADSPI_CR_PRESCALER_5                  0x20000000U            /*!< Bit 5 */
-#define  QUADSPI_CR_PRESCALER_6                  0x40000000U            /*!< Bit 6 */
-#define  QUADSPI_CR_PRESCALER_7                  0x80000000U            /*!< Bit 7 */
-
-/*****************  Bit definition for QUADSPI_DCR register  ******************/
-#define  QUADSPI_DCR_CKMODE                      0x00000001U            /*!< Mode 0 / Mode 3                 */
-#define  QUADSPI_DCR_CSHT                        0x00000700U            /*!< CSHT[2:0]: ChipSelect High Time */
-#define  QUADSPI_DCR_CSHT_0                      0x00000100U            /*!< Bit 0 */
-#define  QUADSPI_DCR_CSHT_1                      0x00000200U            /*!< Bit 1 */
-#define  QUADSPI_DCR_CSHT_2                      0x00000400U            /*!< Bit 2 */
-#define  QUADSPI_DCR_FSIZE                       0x001F0000U            /*!< FSIZE[4:0]: Flash Size          */
-#define  QUADSPI_DCR_FSIZE_0                     0x00010000U            /*!< Bit 0 */
-#define  QUADSPI_DCR_FSIZE_1                     0x00020000U            /*!< Bit 1 */
-#define  QUADSPI_DCR_FSIZE_2                     0x00040000U            /*!< Bit 2 */
-#define  QUADSPI_DCR_FSIZE_3                     0x00080000U            /*!< Bit 3 */
-#define  QUADSPI_DCR_FSIZE_4                     0x00100000U            /*!< Bit 4 */
-
-/******************  Bit definition for QUADSPI_SR register  *******************/
-#define  QUADSPI_SR_TEF                          0x00000001U             /*!< Transfer Error Flag    */
-#define  QUADSPI_SR_TCF                          0x00000002U             /*!< Transfer Complete Flag */
-#define  QUADSPI_SR_FTF                          0x00000004U             /*!< FIFO Threshlod Flag    */
-#define  QUADSPI_SR_SMF                          0x00000008U             /*!< Status Match Flag      */
-#define  QUADSPI_SR_TOF                          0x00000010U             /*!< Timeout Flag           */
-#define  QUADSPI_SR_BUSY                         0x00000020U             /*!< Busy                   */
-#define  QUADSPI_SR_FLEVEL                       0x00003F00U             /*!< FIFO Threshlod Flag    */
-#define  QUADSPI_SR_FLEVEL_0                     0x00000100U             /*!< Bit 0 */
-#define  QUADSPI_SR_FLEVEL_1                     0x00000200U             /*!< Bit 1 */
-#define  QUADSPI_SR_FLEVEL_2                     0x00000400U             /*!< Bit 2 */
-#define  QUADSPI_SR_FLEVEL_3                     0x00000800U             /*!< Bit 3 */
-#define  QUADSPI_SR_FLEVEL_4                     0x00001000U             /*!< Bit 4 */
-#define  QUADSPI_SR_FLEVEL_5                     0x00002000U             /*!< Bit 5 */
-
-/******************  Bit definition for QUADSPI_FCR register  ******************/
-#define  QUADSPI_FCR_CTEF                        0x00000001U             /*!< Clear Transfer Error Flag    */
-#define  QUADSPI_FCR_CTCF                        0x00000002U             /*!< Clear Transfer Complete Flag */
-#define  QUADSPI_FCR_CSMF                        0x00000008U             /*!< Clear Status Match Flag      */
-#define  QUADSPI_FCR_CTOF                        0x00000010U             /*!< Clear Timeout Flag           */
-
-/******************  Bit definition for QUADSPI_DLR register  ******************/
-#define  QUADSPI_DLR_DL                        0xFFFFFFFFU               /*!< DL[31:0]: Data Length */
-
-/******************  Bit definition for QUADSPI_CCR register  ******************/
-#define  QUADSPI_CCR_INSTRUCTION                  0x000000FFU            /*!< INSTRUCTION[7:0]: Instruction */
-#define  QUADSPI_CCR_INSTRUCTION_0                0x00000001U            /*!< Bit 0 */
-#define  QUADSPI_CCR_INSTRUCTION_1                0x00000002U            /*!< Bit 1 */
-#define  QUADSPI_CCR_INSTRUCTION_2                0x00000004U            /*!< Bit 2 */
-#define  QUADSPI_CCR_INSTRUCTION_3                0x00000008U            /*!< Bit 3 */
-#define  QUADSPI_CCR_INSTRUCTION_4                0x00000010U            /*!< Bit 4 */
-#define  QUADSPI_CCR_INSTRUCTION_5                0x00000020U            /*!< Bit 5 */
-#define  QUADSPI_CCR_INSTRUCTION_6                0x00000040U            /*!< Bit 6 */
-#define  QUADSPI_CCR_INSTRUCTION_7                0x00000080U            /*!< Bit 7 */
-#define  QUADSPI_CCR_IMODE                        0x00000300U            /*!< IMODE[1:0]: Instruction Mode     */
-#define  QUADSPI_CCR_IMODE_0                      0x00000100U            /*!< Bit 0 */
-#define  QUADSPI_CCR_IMODE_1                      0x00000200U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ADMODE                       0x00000C00U            /*!< ADMODE[1:0]: Address Mode         */
-#define  QUADSPI_CCR_ADMODE_0                     0x00000400U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ADMODE_1                     0x00000800U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ADSIZE                       0x00003000U            /*!< ADSIZE[1:0]: Address Size         */
-#define  QUADSPI_CCR_ADSIZE_0                     0x00001000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ADSIZE_1                     0x00002000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ABMODE                       0x0000C000U            /*!< ABMODE[1:0]: Alternate Bytes Mode */
-#define  QUADSPI_CCR_ABMODE_0                     0x00004000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ABMODE_1                     0x00008000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ABSIZE                       0x00030000U            /*!< ABSIZE[1:0]: Instruction Mode     */
-#define  QUADSPI_CCR_ABSIZE_0                     0x00010000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ABSIZE_1                     0x00020000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_DCYC                         0x007C0000U            /*!< DCYC[4:0]: Dummy Cycles           */
-#define  QUADSPI_CCR_DCYC_0                       0x00040000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_DCYC_1                       0x00080000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_DCYC_2                       0x00100000U            /*!< Bit 2 */
-#define  QUADSPI_CCR_DCYC_3                       0x00200000U            /*!< Bit 3 */
-#define  QUADSPI_CCR_DCYC_4                       0x00400000U            /*!< Bit 4 */
-#define  QUADSPI_CCR_DMODE                        0x03000000U            /*!< DMODE[1:0]: Data Mode                */
-#define  QUADSPI_CCR_DMODE_0                      0x01000000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_DMODE_1                      0x02000000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_FMODE                        0x0C000000U            /*!< FMODE[1:0]: Functional Mode           */
-#define  QUADSPI_CCR_FMODE_0                      0x04000000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_FMODE_1                      0x08000000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_SIOO                         0x10000000U            /*!< SIOO: Send Instruction Only Once Mode */
-#define  QUADSPI_CCR_DHHC                         0x40000000U            /*!< DHHC: Delay Half Hclk Cycle           */
-#define  QUADSPI_CCR_DDRM                         0x80000000U            /*!< DDRM: Double Data Rate Mode           */ 
-/******************  Bit definition for QUADSPI_AR register  *******************/
-#define  QUADSPI_AR_ADDRESS                       0xFFFFFFFFU            /*!< ADDRESS[31:0]: Address                */
-
-/******************  Bit definition for QUADSPI_ABR register  ******************/
-#define  QUADSPI_ABR_ALTERNATE                    0xFFFFFFFFU            /*!< ALTERNATE[31:0]: Alternate Bytes      */
-
-/******************  Bit definition for QUADSPI_DR register  *******************/
-#define  QUADSPI_DR_DATA                          0xFFFFFFFFU            /*!< DATA[31:0]: Data                      */
-
-/******************  Bit definition for QUADSPI_PSMKR register  ****************/
-#define  QUADSPI_PSMKR_MASK                       0xFFFFFFFFU            /*!< MASK[31:0]: Status Mask               */
-
-/******************  Bit definition for QUADSPI_PSMAR register  ****************/
-#define  QUADSPI_PSMAR_MATCH                      0xFFFFFFFFU            /*!< MATCH[31:0]: Status Match             */
-
-/******************  Bit definition for QUADSPI_PIR register  *****************/
-#define  QUADSPI_PIR_INTERVAL                     0x0000FFFFU            /*!< INTERVAL[15:0]: Polling Interval      */
-
-/******************  Bit definition for QUADSPI_LPTR register  *****************/
-#define  QUADSPI_LPTR_TIMEOUT                     0x0000FFFFU            /*!< TIMEOUT[15:0]: Timeout period         */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        0x00000001U
-#define  RCC_CR_HSIRDY                       0x00000002U
-
-#define  RCC_CR_HSITRIM                      0x000000F8U
-#define  RCC_CR_HSITRIM_0                    0x00000008U/*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    0x00000010U/*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    0x00000020U/*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    0x00000040U/*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    0x00000080U/*!<Bit 4 */
-
-#define  RCC_CR_HSICAL                       0x0000FF00U
-#define  RCC_CR_HSICAL_0                     0x00000100U/*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     0x00000200U/*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     0x00000400U/*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     0x00000800U/*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     0x00001000U/*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     0x00002000U/*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     0x00004000U/*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     0x00008000U/*!<Bit 7 */
-
-#define  RCC_CR_HSEON                        0x00010000U
-#define  RCC_CR_HSERDY                       0x00020000U
-#define  RCC_CR_HSEBYP                       0x00040000U
-#define  RCC_CR_CSSON                        0x00080000U
-#define  RCC_CR_PLLON                        0x01000000U
-#define  RCC_CR_PLLRDY                       0x02000000U
-#define  RCC_CR_PLLI2SON                     0x04000000U
-#define  RCC_CR_PLLI2SRDY                    0x08000000U
-
-/********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    0x0000003FU
-#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
-#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
-#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
-#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
-#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
-#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
-
-#define  RCC_PLLCFGR_PLLN                     0x00007FC0U
-#define  RCC_PLLCFGR_PLLN_0                   0x00000040U
-#define  RCC_PLLCFGR_PLLN_1                   0x00000080U
-#define  RCC_PLLCFGR_PLLN_2                   0x00000100U
-#define  RCC_PLLCFGR_PLLN_3                   0x00000200U
-#define  RCC_PLLCFGR_PLLN_4                   0x00000400U
-#define  RCC_PLLCFGR_PLLN_5                   0x00000800U
-#define  RCC_PLLCFGR_PLLN_6                   0x00001000U
-#define  RCC_PLLCFGR_PLLN_7                   0x00002000U
-#define  RCC_PLLCFGR_PLLN_8                   0x00004000U
-
-#define  RCC_PLLCFGR_PLLP                    0x00030000U
-#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
-#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
-
-#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
-
-#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
-#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
-#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
-#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
-#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
-
-#define  RCC_PLLCFGR_PLLR                    0x70000000U
-#define  RCC_PLLCFGR_PLLR_0                  0x10000000U
-#define  RCC_PLLCFGR_PLLR_1                  0x20000000U
-#define  RCC_PLLCFGR_PLLR_2                  0x40000000U
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-/*!< SW configuration */
-#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
-
-#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock      */
-#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock      */
-#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL/PLLP selected as system clock */
-#define  RCC_CFGR_SW_PLLR                    0x00000003U        /*!< PLL/PLLR selected as system clock */
-
-/*!< SWS configuration */
-#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
-
-#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL/PLLP used as system clock       */
-#define  RCC_CFGR_SWS_PLLR                   0x0000000CU        /*!< PLL/PLLR used as system clock       */
-
-/*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
-
-#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
-
-/*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     0x001F0000U
-#define  RCC_CFGR_RTCPRE_0                   0x00010000U
-#define  RCC_CFGR_RTCPRE_1                   0x00020000U
-#define  RCC_CFGR_RTCPRE_2                   0x00040000U
-#define  RCC_CFGR_RTCPRE_3                   0x00080000U
-#define  RCC_CFGR_RTCPRE_4                   0x00100000U
-
-/*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       0x00600000U
-#define  RCC_CFGR_MCO1_0                     0x00200000U
-#define  RCC_CFGR_MCO1_1                     0x00400000U
-
-#define  RCC_CFGR_MCO1PRE                    0x07000000U
-#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
-#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
-#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
-
-#define  RCC_CFGR_MCO2PRE                    0x38000000U
-#define  RCC_CFGR_MCO2PRE_0                  0x08000000U
-#define  RCC_CFGR_MCO2PRE_1                  0x10000000U
-#define  RCC_CFGR_MCO2PRE_2                  0x20000000U
-
-#define  RCC_CFGR_MCO2                       0xC0000000U
-#define  RCC_CFGR_MCO2_0                     0x40000000U
-#define  RCC_CFGR_MCO2_1                     0x80000000U
-
-/********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     0x00000001U
-#define  RCC_CIR_LSERDYF                     0x00000002U
-#define  RCC_CIR_HSIRDYF                     0x00000004U
-#define  RCC_CIR_HSERDYF                     0x00000008U
-#define  RCC_CIR_PLLRDYF                     0x00000010U
-#define  RCC_CIR_PLLI2SRDYF                  0x00000020U
-
-#define  RCC_CIR_CSSF                        0x00000080U
-#define  RCC_CIR_LSIRDYIE                    0x00000100U
-#define  RCC_CIR_LSERDYIE                    0x00000200U
-#define  RCC_CIR_HSIRDYIE                    0x00000400U
-#define  RCC_CIR_HSERDYIE                    0x00000800U
-#define  RCC_CIR_PLLRDYIE                    0x00001000U
-#define  RCC_CIR_PLLI2SRDYIE                 0x00002000U
-
-#define  RCC_CIR_LSIRDYC                     0x00010000U
-#define  RCC_CIR_LSERDYC                     0x00020000U
-#define  RCC_CIR_HSIRDYC                     0x00040000U
-#define  RCC_CIR_HSERDYC                     0x00080000U
-#define  RCC_CIR_PLLRDYC                     0x00100000U
-#define  RCC_CIR_PLLI2SRDYC                  0x00200000U
-
-#define  RCC_CIR_CSSC                        0x00800000U
-
-/********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
-#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
-#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
-#define  RCC_AHB1RSTR_GPIODRST               0x00000008U
-#define  RCC_AHB1RSTR_GPIOERST               0x00000010U
-#define  RCC_AHB1RSTR_GPIOFRST               0x00000020U
-#define  RCC_AHB1RSTR_GPIOGRST               0x00000040U
-#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
-#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
-#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
-#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
-
-/********************  Bit definition for RCC_AHB2RSTR register  **************/
-#define  RCC_AHB2RSTR_RNGRST                 0x00000040U
-#define  RCC_AHB2RSTR_OTGFSRST               0x00000080U
-
-/********************  Bit definition for RCC_AHB3RSTR register  **************/
-#define  RCC_AHB3RSTR_FSMCRST                0x00000001U
-#define  RCC_AHB3RSTR_QSPIRST               0x00000002U
-
-/********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM2RST                0x00000001U
-#define  RCC_APB1RSTR_TIM3RST                0x00000002U
-#define  RCC_APB1RSTR_TIM4RST                0x00000004U
-#define  RCC_APB1RSTR_TIM5RST                0x00000008U
-#define  RCC_APB1RSTR_TIM6RST                0x00000010U
-#define  RCC_APB1RSTR_TIM7RST                0x00000020U
-#define  RCC_APB1RSTR_TIM12RST               0x00000040U
-#define  RCC_APB1RSTR_TIM13RST               0x00000080U
-#define  RCC_APB1RSTR_TIM14RST               0x00000100U
-#define  RCC_APB1RSTR_WWDGRST                0x00000800U
-#define  RCC_APB1RSTR_SPI2RST                0x00004000U
-#define  RCC_APB1RSTR_SPI3RST                0x00008000U
-#define  RCC_APB1RSTR_USART2RST              0x00020000U
-#define  RCC_APB1RSTR_USART3RST              0x00040000U
-#define  RCC_APB1RSTR_I2C1RST                0x00200000U
-#define  RCC_APB1RSTR_I2C2RST                0x00400000U
-#define  RCC_APB1RSTR_I2C3RST                0x00800000U
-#define  RCC_APB1RSTR_FMPI2C1RST             0x01000000U
-#define  RCC_APB1RSTR_CAN1RST                0x02000000U
-#define  RCC_APB1RSTR_CAN2RST                0x04000000U
-#define  RCC_APB1RSTR_PWRRST                 0x10000000U
-
-/********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                0x00000001U
-#define  RCC_APB2RSTR_TIM8RST                0x00000002U
-#define  RCC_APB2RSTR_USART1RST              0x00000010U
-#define  RCC_APB2RSTR_USART6RST              0x00000020U
-#define  RCC_APB2RSTR_ADCRST                 0x00000100U
-#define  RCC_APB2RSTR_SDIORST                0x00000800U
-#define  RCC_APB2RSTR_SPI1RST                0x00001000U
-#define  RCC_APB2RSTR_SPI4RST                0x00002000U
-#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
-#define  RCC_APB2RSTR_TIM9RST                0x00010000U
-#define  RCC_APB2RSTR_TIM10RST               0x00020000U
-#define  RCC_APB2RSTR_TIM11RST               0x00040000U
-#define  RCC_APB2RSTR_SPI5RST                0x00100000U
-#define  RCC_APB2RSTR_DFSDM1RST              0x01000000U
-
-/********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
-#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
-#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
-#define  RCC_AHB1ENR_GPIODEN                 0x00000008U
-#define  RCC_AHB1ENR_GPIOEEN                 0x00000010U
-#define  RCC_AHB1ENR_GPIOFEN                 0x00000020U
-#define  RCC_AHB1ENR_GPIOGEN                 0x00000040U
-#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
-#define  RCC_AHB1ENR_CRCEN                   0x00001000U
-#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
-#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
-
-/********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define  RCC_AHB2ENR_RNGEN                   0x00000040U
-#define  RCC_AHB2ENR_OTGFSEN                 0x00000080U
-
-/********************  Bit definition for RCC_AHB3ENR register  ***************/
-#define  RCC_AHB3ENR_FSMCEN                  0x00000001U
-#define  RCC_AHB3ENR_QSPIEN                 0x00000002U
-
-/********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM2EN                  0x00000001U
-#define  RCC_APB1ENR_TIM3EN                  0x00000002U
-#define  RCC_APB1ENR_TIM4EN                  0x00000004U
-#define  RCC_APB1ENR_TIM5EN                  0x00000008U
-#define  RCC_APB1ENR_TIM6EN                  0x00000010U
-#define  RCC_APB1ENR_TIM7EN                  0x00000020U
-#define  RCC_APB1ENR_TIM12EN                 0x00000040U
-#define  RCC_APB1ENR_TIM13EN                 0x00000080U
-#define  RCC_APB1ENR_TIM14EN                 0x00000100U
-#define  RCC_APB1ENR_RTCAPBEN                0x00000400U
-#define  RCC_APB1ENR_WWDGEN                  0x00000800U
-#define  RCC_APB1ENR_SPI2EN                  0x00004000U
-#define  RCC_APB1ENR_SPI3EN                  0x00008000U
-#define  RCC_APB1ENR_USART2EN                0x00020000U
-#define  RCC_APB1ENR_USART3EN                0x00040000U
-#define  RCC_APB1ENR_I2C1EN                  0x00200000U
-#define  RCC_APB1ENR_I2C2EN                  0x00400000U
-#define  RCC_APB1ENR_I2C3EN                  0x00800000U
-#define  RCC_APB1ENR_FMPI2C1EN               0x01000000U
-#define  RCC_APB1ENR_CAN1EN                  0x02000000U
-#define  RCC_APB1ENR_CAN2EN                  0x04000000U
-#define  RCC_APB1ENR_PWREN                   0x10000000U
-
-/********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  0x00000001U
-#define  RCC_APB2ENR_TIM8EN                  0x00000002U
-#define  RCC_APB2ENR_USART1EN                0x00000010U
-#define  RCC_APB2ENR_USART6EN                0x00000020U
-#define  RCC_APB2ENR_ADC1EN                  0x00000100U
-#define  RCC_APB2ENR_SDIOEN                  0x00000800U
-#define  RCC_APB2ENR_SPI1EN                  0x00001000U
-#define  RCC_APB2ENR_SPI4EN                  0x00002000U
-#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
-#define  RCC_APB2ENR_EXTITEN                 0x00008000U
-#define  RCC_APB2ENR_TIM9EN                  0x00010000U
-#define  RCC_APB2ENR_TIM10EN                 0x00020000U
-#define  RCC_APB2ENR_TIM11EN                 0x00040000U
-#define  RCC_APB2ENR_SPI5EN                  0x00100000U
-#define  RCC_APB2ENR_DFSDM1EN                0x01000000U
-/********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
-#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
-#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
-#define  RCC_AHB1LPENR_GPIODLPEN             0x00000008U
-#define  RCC_AHB1LPENR_GPIOELPEN             0x00000010U
-#define  RCC_AHB1LPENR_GPIOFLPEN             0x00000020U
-#define  RCC_AHB1LPENR_GPIOGLPEN             0x00000040U
-#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
-#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
-#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
-#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
-#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
-#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
-
-/********************  Bit definition for RCC_AHB2LPENR register  *************/
-#define  RCC_AHB2LPENR_RNGLPEN               0x00000040U
-#define  RCC_AHB2LPENR_OTGFSLPEN             0x00000080U
-
-/********************  Bit definition for RCC_AHB3LPENR register  *************/
-#define  RCC_AHB3LPENR_FSMCLPEN              0x00000001U
-#define  RCC_AHB3LPENR_QSPILPEN             0x00000002U
-
-/********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM2LPEN              0x00000001U
-#define  RCC_APB1LPENR_TIM3LPEN              0x00000002U
-#define  RCC_APB1LPENR_TIM4LPEN              0x00000004U
-#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
-#define  RCC_APB1LPENR_TIM6LPEN              0x00000010U
-#define  RCC_APB1LPENR_TIM7LPEN              0x00000020U
-#define  RCC_APB1LPENR_TIM12LPEN             0x00000040U
-#define  RCC_APB1LPENR_TIM13LPEN             0x00000080U
-#define  RCC_APB1LPENR_TIM14LPEN             0x00000100U
-#define  RCC_APB1LPENR_RTCAPBLPEN            0x00000400U
-#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
-#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U
-#define  RCC_APB1LPENR_SPI3LPEN              0x00008000U
-#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
-#define  RCC_APB1LPENR_USART3LPEN            0x00040000U
-#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
-#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
-#define  RCC_APB1LPENR_I2C3LPEN              0x00800000U
-#define  RCC_APB1LPENR_FMPI2C1LPEN           0x01000000U
-#define  RCC_APB1LPENR_CAN1LPEN              0x02000000U
-#define  RCC_APB1LPENR_CAN2LPEN              0x04000000U
-#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
-
-/********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
-#define  RCC_APB2LPENR_TIM8LPEN              0x00000002U
-#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
-#define  RCC_APB2LPENR_USART6LPEN            0x00000020U
-#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
-#define  RCC_APB2LPENR_SDIOLPEN              0x00000800U
-#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
-#define  RCC_APB2LPENR_SPI4LPEN              0x00002000U
-#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
-#define  RCC_APB2LPENR_EXTITLPEN             0x00008000U
-#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
-#define  RCC_APB2LPENR_TIM10LPEN             0x00020000U
-#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
-#define  RCC_APB2LPENR_SPI5LPEN              0x00100000U
-#define  RCC_APB2LPENR_DFSDM1LPEN            0x01000000U
-
-/********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      0x00000001U
-#define  RCC_BDCR_LSERDY                     0x00000002U
-#define  RCC_BDCR_LSEBYP                     0x00000004U
-#define  RCC_BDCR_LSEMOD                     0x00000008U
-
-#define  RCC_BDCR_RTCSEL                    0x00000300U
-#define  RCC_BDCR_RTCSEL_0                  0x00000100U
-#define  RCC_BDCR_RTCSEL_1                  0x00000200U
-
-#define  RCC_BDCR_RTCEN                      0x00008000U
-#define  RCC_BDCR_BDRST                      0x00010000U
-
-/********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       0x00000001U
-#define  RCC_CSR_LSIRDY                      0x00000002U
-#define  RCC_CSR_RMVF                        0x01000000U
-#define  RCC_CSR_PADRSTF                     0x04000000U
-#define  RCC_CSR_PORRSTF                     0x08000000U
-#define  RCC_CSR_SFTRSTF                     0x10000000U
-#define  RCC_CSR_WDGRSTF                     0x20000000U
-#define  RCC_CSR_WWDGRSTF                    0x40000000U
-#define  RCC_CSR_LPWRRSTF                    0x80000000U
-
-/********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    0x00001FFFU
-#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
-#define  RCC_SSCGR_SPREADSEL                 0x40000000U
-#define  RCC_SSCGR_SSCGEN                    0x80000000U
-
-/********************  Bit definition for RCC_PLLI2SCFGR register  ************/
-#define  RCC_PLLI2SCFGR_PLLI2SM              0x0000003FU
-#define  RCC_PLLI2SCFGR_PLLI2SM_0            0x00000001U
-#define  RCC_PLLI2SCFGR_PLLI2SM_1            0x00000002U
-#define  RCC_PLLI2SCFGR_PLLI2SM_2            0x00000004U
-#define  RCC_PLLI2SCFGR_PLLI2SM_3            0x00000008U
-#define  RCC_PLLI2SCFGR_PLLI2SM_4            0x00000010U
-#define  RCC_PLLI2SCFGR_PLLI2SM_5            0x00000020U
-
-#define  RCC_PLLI2SCFGR_PLLI2SN              0x00007FC0U
-#define  RCC_PLLI2SCFGR_PLLI2SN_0            0x00000040U
-#define  RCC_PLLI2SCFGR_PLLI2SN_1            0x00000080U
-#define  RCC_PLLI2SCFGR_PLLI2SN_2            0x00000100U
-#define  RCC_PLLI2SCFGR_PLLI2SN_3            0x00000200U
-#define  RCC_PLLI2SCFGR_PLLI2SN_4            0x00000400U
-#define  RCC_PLLI2SCFGR_PLLI2SN_5            0x00000800U
-#define  RCC_PLLI2SCFGR_PLLI2SN_6            0x00001000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_7            0x00002000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_8            0x00004000U
-
-#define  RCC_PLLI2SCFGR_PLLI2SSRC            0x00400000U
-
-#define  RCC_PLLI2SCFGR_PLLI2SQ              0x0F000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_0            0x01000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_1            0x02000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_2            0x04000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_3            0x08000000U
-
-#define  RCC_PLLI2SCFGR_PLLI2SR              0x70000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_0            0x10000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_1            0x20000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_2            0x40000000U
-
-/********************  Bit definition for RCC_DCKCFGR register  ****************/
-#define  RCC_DCKCFGR_CKDFSDM1ASEL            0x00008000U
-#define  RCC_DCKCFGR_TIMPRE                  0x01000000U
-
-#define  RCC_DCKCFGR_I2S1SRC                 0x06000000U
-#define  RCC_DCKCFGR_I2S1SRC_0               0x02000000U
-#define  RCC_DCKCFGR_I2S1SRC_1               0x04000000U
-
-#define  RCC_DCKCFGR_I2S2SRC                 0x18000000U
-#define  RCC_DCKCFGR_I2S2SRC_0               0x08000000U
-#define  RCC_DCKCFGR_I2S2SRC_1               0x10000000U
-
-#define  RCC_DCKCFGR_CKDFSDM1SEL             0x80000000U
-
-/********************  Bit definition for RCC_CKGATENR register  ***************/
-#define  RCC_CKGATENR_AHB2APB1_CKEN          0x00000001U
-#define  RCC_CKGATENR_AHB2APB2_CKEN          0x00000002U
-#define  RCC_CKGATENR_CM4DBG_CKEN            0x00000004U
-#define  RCC_CKGATENR_SPARE_CKEN             0x00000008U
-#define  RCC_CKGATENR_SRAM_CKEN              0x00000010U
-#define  RCC_CKGATENR_FLITF_CKEN             0x00000020U
-#define  RCC_CKGATENR_RCC_CKEN               0x00000040U
-#define  RCC_CKGATENR_RCC_EVTCTL             0x00000080U
-
-/********************  Bit definition for RCC_DCKCFGR2 register  ***************/
-#define  RCC_DCKCFGR2_FMPI2C1SEL             0x00C00000U
-#define  RCC_DCKCFGR2_FMPI2C1SEL_0           0x00400000U
-#define  RCC_DCKCFGR2_FMPI2C1SEL_1           0x00800000U
-
-#define  RCC_DCKCFGR2_CK48MSEL               0x08000000U
-#define  RCC_DCKCFGR2_SDIOSEL                0x10000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    RNG                                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN                         0x00000004U
-#define RNG_CR_IE                            0x00000008U
-
-/********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY                          0x00000001U
-#define RNG_SR_CECS                          0x00000002U
-#define RNG_SR_SECS                          0x00000004U
-#define RNG_SR_CEIS                          0x00000020U
-#define RNG_SR_SEIS                          0x00000040U
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            0x00400000U
-#define RTC_TR_HT                            0x00300000U
-#define RTC_TR_HT_0                          0x00100000U
-#define RTC_TR_HT_1                          0x00200000U
-#define RTC_TR_HU                            0x000F0000U
-#define RTC_TR_HU_0                          0x00010000U
-#define RTC_TR_HU_1                          0x00020000U
-#define RTC_TR_HU_2                          0x00040000U
-#define RTC_TR_HU_3                          0x00080000U
-#define RTC_TR_MNT                           0x00007000U
-#define RTC_TR_MNT_0                         0x00001000U
-#define RTC_TR_MNT_1                         0x00002000U
-#define RTC_TR_MNT_2                         0x00004000U
-#define RTC_TR_MNU                           0x00000F00U
-#define RTC_TR_MNU_0                         0x00000100U
-#define RTC_TR_MNU_1                         0x00000200U
-#define RTC_TR_MNU_2                         0x00000400U
-#define RTC_TR_MNU_3                         0x00000800U
-#define RTC_TR_ST                            0x00000070U
-#define RTC_TR_ST_0                          0x00000010U
-#define RTC_TR_ST_1                          0x00000020U
-#define RTC_TR_ST_2                          0x00000040U
-#define RTC_TR_SU                            0x0000000FU
-#define RTC_TR_SU_0                          0x00000001U
-#define RTC_TR_SU_1                          0x00000002U
-#define RTC_TR_SU_2                          0x00000004U
-#define RTC_TR_SU_3                          0x00000008U
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            0x00F00000U
-#define RTC_DR_YT_0                          0x00100000U
-#define RTC_DR_YT_1                          0x00200000U
-#define RTC_DR_YT_2                          0x00400000U
-#define RTC_DR_YT_3                          0x00800000U
-#define RTC_DR_YU                            0x000F0000U
-#define RTC_DR_YU_0                          0x00010000U
-#define RTC_DR_YU_1                          0x00020000U
-#define RTC_DR_YU_2                          0x00040000U
-#define RTC_DR_YU_3                          0x00080000U
-#define RTC_DR_WDU                           0x0000E000U
-#define RTC_DR_WDU_0                         0x00002000U
-#define RTC_DR_WDU_1                         0x00004000U
-#define RTC_DR_WDU_2                         0x00008000U
-#define RTC_DR_MT                            0x00001000U
-#define RTC_DR_MU                            0x00000F00U
-#define RTC_DR_MU_0                          0x00000100U
-#define RTC_DR_MU_1                          0x00000200U
-#define RTC_DR_MU_2                          0x00000400U
-#define RTC_DR_MU_3                          0x00000800U
-#define RTC_DR_DT                            0x00000030U
-#define RTC_DR_DT_0                          0x00000010U
-#define RTC_DR_DT_1                          0x00000020U
-#define RTC_DR_DU                            0x0000000FU
-#define RTC_DR_DU_0                          0x00000001U
-#define RTC_DR_DU_1                          0x00000002U
-#define RTC_DR_DU_2                          0x00000004U
-#define RTC_DR_DU_3                          0x00000008U
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           0x00800000U
-#define RTC_CR_OSEL                          0x00600000U
-#define RTC_CR_OSEL_0                        0x00200000U
-#define RTC_CR_OSEL_1                        0x00400000U
-#define RTC_CR_POL                           0x00100000U
-#define RTC_CR_COSEL                         0x00080000U
-#define RTC_CR_BCK                           0x00040000U
-#define RTC_CR_SUB1H                         0x00020000U
-#define RTC_CR_ADD1H                         0x00010000U
-#define RTC_CR_TSIE                          0x00008000U
-#define RTC_CR_WUTIE                         0x00004000U
-#define RTC_CR_ALRBIE                        0x00002000U
-#define RTC_CR_ALRAIE                        0x00001000U
-#define RTC_CR_TSE                           0x00000800U
-#define RTC_CR_WUTE                          0x00000400U
-#define RTC_CR_ALRBE                         0x00000200U
-#define RTC_CR_ALRAE                         0x00000100U
-#define RTC_CR_DCE                           0x00000080U
-#define RTC_CR_FMT                           0x00000040U
-#define RTC_CR_BYPSHAD                       0x00000020U
-#define RTC_CR_REFCKON                       0x00000010U
-#define RTC_CR_TSEDGE                        0x00000008U
-#define RTC_CR_WUCKSEL                       0x00000007U
-#define RTC_CR_WUCKSEL_0                     0x00000001U
-#define RTC_CR_WUCKSEL_1                     0x00000002U
-#define RTC_CR_WUCKSEL_2                     0x00000004U
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      0x00010000U
-#define RTC_ISR_TAMP1F                       0x00002000U
-#define RTC_ISR_TAMP2F                       0x00004000U
-#define RTC_ISR_TSOVF                        0x00001000U
-#define RTC_ISR_TSF                          0x00000800U
-#define RTC_ISR_WUTF                         0x00000400U
-#define RTC_ISR_ALRBF                        0x00000200U
-#define RTC_ISR_ALRAF                        0x00000100U
-#define RTC_ISR_INIT                         0x00000080U
-#define RTC_ISR_INITF                        0x00000040U
-#define RTC_ISR_RSF                          0x00000020U
-#define RTC_ISR_INITS                        0x00000010U
-#define RTC_ISR_SHPF                         0x00000008U
-#define RTC_ISR_WUTWF                        0x00000004U
-#define RTC_ISR_ALRBWF                       0x00000002U
-#define RTC_ISR_ALRAWF                       0x00000001U
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    0x007F0000U
-#define RTC_PRER_PREDIV_S                    0x00007FFFU
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS                       0x00000080U
-#define RTC_CALIBR_DC                        0x0000001FU
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      0x80000000U
-#define RTC_ALRMAR_WDSEL                     0x40000000U
-#define RTC_ALRMAR_DT                        0x30000000U
-#define RTC_ALRMAR_DT_0                      0x10000000U
-#define RTC_ALRMAR_DT_1                      0x20000000U
-#define RTC_ALRMAR_DU                        0x0F000000U
-#define RTC_ALRMAR_DU_0                      0x01000000U
-#define RTC_ALRMAR_DU_1                      0x02000000U
-#define RTC_ALRMAR_DU_2                      0x04000000U
-#define RTC_ALRMAR_DU_3                      0x08000000U
-#define RTC_ALRMAR_MSK3                      0x00800000U
-#define RTC_ALRMAR_PM                        0x00400000U
-#define RTC_ALRMAR_HT                        0x00300000U
-#define RTC_ALRMAR_HT_0                      0x00100000U
-#define RTC_ALRMAR_HT_1                      0x00200000U
-#define RTC_ALRMAR_HU                        0x000F0000U
-#define RTC_ALRMAR_HU_0                      0x00010000U
-#define RTC_ALRMAR_HU_1                      0x00020000U
-#define RTC_ALRMAR_HU_2                      0x00040000U
-#define RTC_ALRMAR_HU_3                      0x00080000U
-#define RTC_ALRMAR_MSK2                      0x00008000U
-#define RTC_ALRMAR_MNT                       0x00007000U
-#define RTC_ALRMAR_MNT_0                     0x00001000U
-#define RTC_ALRMAR_MNT_1                     0x00002000U
-#define RTC_ALRMAR_MNT_2                     0x00004000U
-#define RTC_ALRMAR_MNU                       0x00000F00U
-#define RTC_ALRMAR_MNU_0                     0x00000100U
-#define RTC_ALRMAR_MNU_1                     0x00000200U
-#define RTC_ALRMAR_MNU_2                     0x00000400U
-#define RTC_ALRMAR_MNU_3                     0x00000800U
-#define RTC_ALRMAR_MSK1                      0x00000080U
-#define RTC_ALRMAR_ST                        0x00000070U
-#define RTC_ALRMAR_ST_0                      0x00000010U
-#define RTC_ALRMAR_ST_1                      0x00000020U
-#define RTC_ALRMAR_ST_2                      0x00000040U
-#define RTC_ALRMAR_SU                        0x0000000FU
-#define RTC_ALRMAR_SU_0                      0x00000001U
-#define RTC_ALRMAR_SU_1                      0x00000002U
-#define RTC_ALRMAR_SU_2                      0x00000004U
-#define RTC_ALRMAR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      0x80000000U
-#define RTC_ALRMBR_WDSEL                     0x40000000U
-#define RTC_ALRMBR_DT                        0x30000000U
-#define RTC_ALRMBR_DT_0                      0x10000000U
-#define RTC_ALRMBR_DT_1                      0x20000000U
-#define RTC_ALRMBR_DU                        0x0F000000U
-#define RTC_ALRMBR_DU_0                      0x01000000U
-#define RTC_ALRMBR_DU_1                      0x02000000U
-#define RTC_ALRMBR_DU_2                      0x04000000U
-#define RTC_ALRMBR_DU_3                      0x08000000U
-#define RTC_ALRMBR_MSK3                      0x00800000U
-#define RTC_ALRMBR_PM                        0x00400000U
-#define RTC_ALRMBR_HT                        0x00300000U
-#define RTC_ALRMBR_HT_0                      0x00100000U
-#define RTC_ALRMBR_HT_1                      0x00200000U
-#define RTC_ALRMBR_HU                        0x000F0000U
-#define RTC_ALRMBR_HU_0                      0x00010000U
-#define RTC_ALRMBR_HU_1                      0x00020000U
-#define RTC_ALRMBR_HU_2                      0x00040000U
-#define RTC_ALRMBR_HU_3                      0x00080000U
-#define RTC_ALRMBR_MSK2                      0x00008000U
-#define RTC_ALRMBR_MNT                       0x00007000U
-#define RTC_ALRMBR_MNT_0                     0x00001000U
-#define RTC_ALRMBR_MNT_1                     0x00002000U
-#define RTC_ALRMBR_MNT_2                     0x00004000U
-#define RTC_ALRMBR_MNU                       0x00000F00U
-#define RTC_ALRMBR_MNU_0                     0x00000100U
-#define RTC_ALRMBR_MNU_1                     0x00000200U
-#define RTC_ALRMBR_MNU_2                     0x00000400U
-#define RTC_ALRMBR_MNU_3                     0x00000800U
-#define RTC_ALRMBR_MSK1                      0x00000080U
-#define RTC_ALRMBR_ST                        0x00000070U
-#define RTC_ALRMBR_ST_0                      0x00000010U
-#define RTC_ALRMBR_ST_1                      0x00000020U
-#define RTC_ALRMBR_ST_2                      0x00000040U
-#define RTC_ALRMBR_SU                        0x0000000FU
-#define RTC_ALRMBR_SU_0                      0x00000001U
-#define RTC_ALRMBR_SU_1                      0x00000002U
-#define RTC_ALRMBR_SU_2                      0x00000004U
-#define RTC_ALRMBR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          0x000000FFU
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           0x0000FFFFU
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     0x00007FFFU
-#define RTC_SHIFTR_ADD1S                     0x80000000U
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          0x00400000U
-#define RTC_TSTR_HT                          0x00300000U
-#define RTC_TSTR_HT_0                        0x00100000U
-#define RTC_TSTR_HT_1                        0x00200000U
-#define RTC_TSTR_HU                          0x000F0000U
-#define RTC_TSTR_HU_0                        0x00010000U
-#define RTC_TSTR_HU_1                        0x00020000U
-#define RTC_TSTR_HU_2                        0x00040000U
-#define RTC_TSTR_HU_3                        0x00080000U
-#define RTC_TSTR_MNT                         0x00007000U
-#define RTC_TSTR_MNT_0                       0x00001000U
-#define RTC_TSTR_MNT_1                       0x00002000U
-#define RTC_TSTR_MNT_2                       0x00004000U
-#define RTC_TSTR_MNU                         0x00000F00U
-#define RTC_TSTR_MNU_0                       0x00000100U
-#define RTC_TSTR_MNU_1                       0x00000200U
-#define RTC_TSTR_MNU_2                       0x00000400U
-#define RTC_TSTR_MNU_3                       0x00000800U
-#define RTC_TSTR_ST                          0x00000070U
-#define RTC_TSTR_ST_0                        0x00000010U
-#define RTC_TSTR_ST_1                        0x00000020U
-#define RTC_TSTR_ST_2                        0x00000040U
-#define RTC_TSTR_SU                          0x0000000FU
-#define RTC_TSTR_SU_0                        0x00000001U
-#define RTC_TSTR_SU_1                        0x00000002U
-#define RTC_TSTR_SU_2                        0x00000004U
-#define RTC_TSTR_SU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         0x0000E000U
-#define RTC_TSDR_WDU_0                       0x00002000U
-#define RTC_TSDR_WDU_1                       0x00004000U
-#define RTC_TSDR_WDU_2                       0x00008000U
-#define RTC_TSDR_MT                          0x00001000U
-#define RTC_TSDR_MU                          0x00000F00U
-#define RTC_TSDR_MU_0                        0x00000100U
-#define RTC_TSDR_MU_1                        0x00000200U
-#define RTC_TSDR_MU_2                        0x00000400U
-#define RTC_TSDR_MU_3                        0x00000800U
-#define RTC_TSDR_DT                          0x00000030U
-#define RTC_TSDR_DT_0                        0x00000010U
-#define RTC_TSDR_DT_1                        0x00000020U
-#define RTC_TSDR_DU                          0x0000000FU
-#define RTC_TSDR_DU_0                        0x00000001U
-#define RTC_TSDR_DU_1                        0x00000002U
-#define RTC_TSDR_DU_2                        0x00000004U
-#define RTC_TSDR_DU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        0x00008000U
-#define RTC_CALR_CALW8                       0x00004000U
-#define RTC_CALR_CALW16                      0x00002000U
-#define RTC_CALR_CALM                        0x000001FFU
-#define RTC_CALR_CALM_0                      0x00000001U
-#define RTC_CALR_CALM_1                      0x00000002U
-#define RTC_CALR_CALM_2                      0x00000004U
-#define RTC_CALR_CALM_3                      0x00000008U
-#define RTC_CALR_CALM_4                      0x00000010U
-#define RTC_CALR_CALM_5                      0x00000020U
-#define RTC_CALR_CALM_6                      0x00000040U
-#define RTC_CALR_CALM_7                      0x00000080U
-#define RTC_CALR_CALM_8                      0x00000100U
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               0x00040000U
-#define RTC_TAFCR_TSINSEL                    0x00020000U
-#define RTC_TAFCR_TAMPINSEL                  0x00010000U
-#define RTC_TAFCR_TAMPPUDIS                  0x00008000U
-#define RTC_TAFCR_TAMPPRCH                   0x00006000U
-#define RTC_TAFCR_TAMPPRCH_0                 0x00002000U
-#define RTC_TAFCR_TAMPPRCH_1                 0x00004000U
-#define RTC_TAFCR_TAMPFLT                    0x00001800U
-#define RTC_TAFCR_TAMPFLT_0                  0x00000800U
-#define RTC_TAFCR_TAMPFLT_1                  0x00001000U
-#define RTC_TAFCR_TAMPFREQ                   0x00000700U
-#define RTC_TAFCR_TAMPFREQ_0                 0x00000100U
-#define RTC_TAFCR_TAMPFREQ_1                 0x00000200U
-#define RTC_TAFCR_TAMPFREQ_2                 0x00000400U
-#define RTC_TAFCR_TAMPTS                     0x00000080U
-#define RTC_TAFCR_TAMP2TRG                   0x00000010U
-#define RTC_TAFCR_TAMP2E                     0x00000008U
-#define RTC_TAFCR_TAMPIE                     0x00000004U
-#define RTC_TAFCR_TAMP1TRG                   0x00000002U
-#define RTC_TAFCR_TAMP1E                     0x00000001U
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  0x0F000000U
-#define RTC_ALRMASSR_MASKSS_0                0x01000000U
-#define RTC_ALRMASSR_MASKSS_1                0x02000000U
-#define RTC_ALRMASSR_MASKSS_2                0x04000000U
-#define RTC_ALRMASSR_MASKSS_3                0x08000000U
-#define RTC_ALRMASSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
-#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
-#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
-#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
-#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
-#define RTC_ALRMBSSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           0xFFFFFFFFU
-
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          SD host Interface                                 */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SDIO_POWER register  ******************/
-#define  SDIO_POWER_PWRCTRL                  0x03U               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDIO_POWER_PWRCTRL_0                0x01U               /*!<Bit 0 */
-#define  SDIO_POWER_PWRCTRL_1                0x02U               /*!<Bit 1 */
-
-/******************  Bit definition for SDIO_CLKCR register  ******************/
-#define  SDIO_CLKCR_CLKDIV                   0x00FFU            /*!<Clock divide factor             */
-#define  SDIO_CLKCR_CLKEN                    0x0100U            /*!<Clock enable bit                */
-#define  SDIO_CLKCR_PWRSAV                   0x0200U            /*!<Power saving configuration bit  */
-#define  SDIO_CLKCR_BYPASS                   0x0400U            /*!<Clock divider bypass enable bit */
-
-#define  SDIO_CLKCR_WIDBUS                   0x1800U            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDIO_CLKCR_WIDBUS_0                 0x0800U            /*!<Bit 0 */
-#define  SDIO_CLKCR_WIDBUS_1                 0x1000U            /*!<Bit 1 */
-
-#define  SDIO_CLKCR_NEGEDGE                  0x2000U            /*!<SDIO_CK dephasing selection bit */
-#define  SDIO_CLKCR_HWFC_EN                  0x4000U            /*!<HW Flow Control enable          */
-
-/*******************  Bit definition for SDIO_ARG register  *******************/
-#define  SDIO_ARG_CMDARG                     0xFFFFFFFFU            /*!<Command argument */
-
-/*******************  Bit definition for SDIO_CMD register  *******************/
-#define  SDIO_CMD_CMDINDEX                   0x003FU            /*!<Command Index                               */
-
-#define  SDIO_CMD_WAITRESP                   0x00C0U            /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDIO_CMD_WAITRESP_0                 0x0040U            /*!< Bit 0 */
-#define  SDIO_CMD_WAITRESP_1                 0x0080U            /*!< Bit 1 */
-
-#define  SDIO_CMD_WAITINT                    0x0100U            /*!<CPSM Waits for Interrupt Request                               */
-#define  SDIO_CMD_WAITPEND                   0x0200U            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDIO_CMD_CPSMEN                     0x0400U            /*!<Command path state machine (CPSM) Enable bit                   */
-#define  SDIO_CMD_SDIOSUSPEND                0x0800U            /*!<SD I/O suspend command                                         */
-#define  SDIO_CMD_ENCMDCOMPL                 0x1000U            /*!<Enable CMD completion                                          */
-#define  SDIO_CMD_NIEN                       0x2000U            /*!<Not Interrupt Enable */
-#define  SDIO_CMD_CEATACMD                   0x4000U            /*!<CE-ATA command       */
-
-/*****************  Bit definition for SDIO_RESPCMD register  *****************/
-#define  SDIO_RESPCMD_RESPCMD                0x3FU               /*!<Response command index */
-
-/******************  Bit definition for SDIO_RESP0 register  ******************/
-#define  SDIO_RESP0_CARDSTATUS0              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP1 register  ******************/
-#define  SDIO_RESP1_CARDSTATUS1              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP2 register  ******************/
-#define  SDIO_RESP2_CARDSTATUS2              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP3 register  ******************/
-#define  SDIO_RESP3_CARDSTATUS3              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP4 register  ******************/
-#define  SDIO_RESP4_CARDSTATUS4              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_DTIMER register  *****************/
-#define  SDIO_DTIMER_DATATIME                0xFFFFFFFFU        /*!<Data timeout period. */
-
-/******************  Bit definition for SDIO_DLEN register  *******************/
-#define  SDIO_DLEN_DATALENGTH                0x01FFFFFFU        /*!<Data length value    */
-
-/******************  Bit definition for SDIO_DCTRL register  ******************/
-#define  SDIO_DCTRL_DTEN                     0x0001U            /*!<Data transfer enabled bit         */
-#define  SDIO_DCTRL_DTDIR                    0x0002U            /*!<Data transfer direction selection */
-#define  SDIO_DCTRL_DTMODE                   0x0004U            /*!<Data transfer mode selection      */
-#define  SDIO_DCTRL_DMAEN                    0x0008U            /*!<DMA enabled bit                   */
-
-#define  SDIO_DCTRL_DBLOCKSIZE               0x00F0U            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDIO_DCTRL_DBLOCKSIZE_0             0x0010U            /*!<Bit 0 */
-#define  SDIO_DCTRL_DBLOCKSIZE_1             0x0020U            /*!<Bit 1 */
-#define  SDIO_DCTRL_DBLOCKSIZE_2             0x0040U            /*!<Bit 2 */
-#define  SDIO_DCTRL_DBLOCKSIZE_3             0x0080U            /*!<Bit 3 */
-
-#define  SDIO_DCTRL_RWSTART                  0x0100U            /*!<Read wait start         */
-#define  SDIO_DCTRL_RWSTOP                   0x0200U            /*!<Read wait stop          */
-#define  SDIO_DCTRL_RWMOD                    0x0400U            /*!<Read wait mode          */
-#define  SDIO_DCTRL_SDIOEN                   0x0800U            /*!<SD I/O enable functions */
-
-/******************  Bit definition for SDIO_DCOUNT register  *****************/
-#define  SDIO_DCOUNT_DATACOUNT               0x01FFFFFFU        /*!<Data count value */
-
-/******************  Bit definition for SDIO_STA register  ********************/
-#define  SDIO_STA_CCRCFAIL                   0x00000001U        /*!<Command response received (CRC check failed)  */
-#define  SDIO_STA_DCRCFAIL                   0x00000002U        /*!<Data block sent/received (CRC check failed)   */
-#define  SDIO_STA_CTIMEOUT                   0x00000004U        /*!<Command response timeout                      */
-#define  SDIO_STA_DTIMEOUT                   0x00000008U        /*!<Data timeout                                  */
-#define  SDIO_STA_TXUNDERR                   0x00000010U        /*!<Transmit FIFO underrun error                  */
-#define  SDIO_STA_RXOVERR                    0x00000020U        /*!<Received FIFO overrun error                   */
-#define  SDIO_STA_CMDREND                    0x00000040U        /*!<Command response received (CRC check passed)  */
-#define  SDIO_STA_CMDSENT                    0x00000080U        /*!<Command sent (no response required)           */
-#define  SDIO_STA_DATAEND                    0x00000100U        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
-#define  SDIO_STA_STBITERR                   0x00000200U        /*!<Start bit not detected on all data signals in wide bus mode */
-#define  SDIO_STA_DBCKEND                    0x00000400U        /*!<Data block sent/received (CRC check passed)   */
-#define  SDIO_STA_CMDACT                     0x00000800U        /*!<Command transfer in progress                  */
-#define  SDIO_STA_TXACT                      0x00001000U        /*!<Data transmit in progress                     */
-#define  SDIO_STA_RXACT                      0x00002000U        /*!<Data receive in progress                      */
-#define  SDIO_STA_TXFIFOHE                   0x00004000U        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDIO_STA_RXFIFOHF                   0x00008000U        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDIO_STA_TXFIFOF                    0x00010000U        /*!<Transmit FIFO full                            */
-#define  SDIO_STA_RXFIFOF                    0x00020000U        /*!<Receive FIFO full                             */
-#define  SDIO_STA_TXFIFOE                    0x00040000U        /*!<Transmit FIFO empty                           */
-#define  SDIO_STA_RXFIFOE                    0x00080000U        /*!<Receive FIFO empty                            */
-#define  SDIO_STA_TXDAVL                     0x00100000U        /*!<Data available in transmit FIFO               */
-#define  SDIO_STA_RXDAVL                     0x00200000U        /*!<Data available in receive FIFO                */
-#define  SDIO_STA_SDIOIT                     0x00400000U        /*!<SDIO interrupt received                       */
-#define  SDIO_STA_CEATAEND                   0x00800000U        /*!<CE-ATA command completion signal received for CMD61 */
-
-/*******************  Bit definition for SDIO_ICR register  *******************/
-#define  SDIO_ICR_CCRCFAILC                  0x00000001U        /*!<CCRCFAIL flag clear bit */
-#define  SDIO_ICR_DCRCFAILC                  0x00000002U        /*!<DCRCFAIL flag clear bit */
-#define  SDIO_ICR_CTIMEOUTC                  0x00000004U        /*!<CTIMEOUT flag clear bit */
-#define  SDIO_ICR_DTIMEOUTC                  0x00000008U        /*!<DTIMEOUT flag clear bit */
-#define  SDIO_ICR_TXUNDERRC                  0x00000010U        /*!<TXUNDERR flag clear bit */
-#define  SDIO_ICR_RXOVERRC                   0x00000020U        /*!<RXOVERR flag clear bit  */
-#define  SDIO_ICR_CMDRENDC                   0x00000040U        /*!<CMDREND flag clear bit  */
-#define  SDIO_ICR_CMDSENTC                   0x00000080U        /*!<CMDSENT flag clear bit  */
-#define  SDIO_ICR_DATAENDC                   0x00000100U        /*!<DATAEND flag clear bit  */
-#define  SDIO_ICR_STBITERRC                  0x00000200U        /*!<STBITERR flag clear bit */
-#define  SDIO_ICR_DBCKENDC                   0x00000400U        /*!<DBCKEND flag clear bit  */
-#define  SDIO_ICR_SDIOITC                    0x00400000U        /*!<SDIOIT flag clear bit   */
-#define  SDIO_ICR_CEATAENDC                  0x00800000U        /*!<CEATAEND flag clear bit */
-
-/******************  Bit definition for SDIO_MASK register  *******************/
-#define  SDIO_MASK_CCRCFAILIE                0x00000001U        /*!<Command CRC Fail Interrupt Enable          */
-#define  SDIO_MASK_DCRCFAILIE                0x00000002U        /*!<Data CRC Fail Interrupt Enable             */
-#define  SDIO_MASK_CTIMEOUTIE                0x00000004U        /*!<Command TimeOut Interrupt Enable           */
-#define  SDIO_MASK_DTIMEOUTIE                0x00000008U        /*!<Data TimeOut Interrupt Enable              */
-#define  SDIO_MASK_TXUNDERRIE                0x00000010U        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
-#define  SDIO_MASK_RXOVERRIE                 0x00000020U        /*!<Rx FIFO OverRun Error Interrupt Enable     */
-#define  SDIO_MASK_CMDRENDIE                 0x00000040U        /*!<Command Response Received Interrupt Enable */
-#define  SDIO_MASK_CMDSENTIE                 0x00000080U        /*!<Command Sent Interrupt Enable              */
-#define  SDIO_MASK_DATAENDIE                 0x00000100U        /*!<Data End Interrupt Enable                  */
-#define  SDIO_MASK_STBITERRIE                0x00000200U        /*!<Start Bit Error Interrupt Enable           */
-#define  SDIO_MASK_DBCKENDIE                 0x00000400U        /*!<Data Block End Interrupt Enable            */
-#define  SDIO_MASK_CMDACTIE                  0x00000800U        /*!<CCommand Acting Interrupt Enable           */
-#define  SDIO_MASK_TXACTIE                   0x00001000U        /*!<Data Transmit Acting Interrupt Enable      */
-#define  SDIO_MASK_RXACTIE                   0x00002000U        /*!<Data receive acting interrupt enabled      */
-#define  SDIO_MASK_TXFIFOHEIE                0x00004000U        /*!<Tx FIFO Half Empty interrupt Enable        */
-#define  SDIO_MASK_RXFIFOHFIE                0x00008000U        /*!<Rx FIFO Half Full interrupt Enable         */
-#define  SDIO_MASK_TXFIFOFIE                 0x00010000U        /*!<Tx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_RXFIFOFIE                 0x00020000U        /*!<Rx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_TXFIFOEIE                 0x00040000U        /*!<Tx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_RXFIFOEIE                 0x00080000U        /*!<Rx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_TXDAVLIE                  0x00100000U        /*!<Data available in Tx FIFO interrupt Enable */
-#define  SDIO_MASK_RXDAVLIE                  0x00200000U        /*!<Data available in Rx FIFO interrupt Enable */
-#define  SDIO_MASK_SDIOITIE                  0x00400000U        /*!<SDIO Mode Interrupt Received interrupt Enable */
-#define  SDIO_MASK_CEATAENDIE                0x00800000U        /*!<CE-ATA command completion signal received Interrupt Enable */
-
-/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
-#define  SDIO_FIFOCNT_FIFOCOUNT              0x00FFFFFFU        /*!<Remaining number of words to be written to or read from the FIFO */
-
-/******************  Bit definition for SDIO_FIFO register  *******************/
-#define  SDIO_FIFO_FIFODATA                  0xFFFFFFFFU        /*!<Receive and transmit FIFO data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        0x00000001U            /*!<Clock Phase      */
-#define  SPI_CR1_CPOL                        0x00000002U            /*!<Clock Polarity   */
-#define  SPI_CR1_MSTR                        0x00000004U            /*!<Master Selection */
-
-#define  SPI_CR1_BR                          0x00000038U            /*!<BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        0x00000008U            /*!<Bit 0 */
-#define  SPI_CR1_BR_1                        0x00000010U            /*!<Bit 1 */
-#define  SPI_CR1_BR_2                        0x00000020U            /*!<Bit 2 */
-
-#define  SPI_CR1_SPE                         0x00000040U            /*!<SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    0x00000080U            /*!<Frame Format                        */
-#define  SPI_CR1_SSI                         0x00000100U            /*!<Internal slave select               */
-#define  SPI_CR1_SSM                         0x00000200U            /*!<Software slave management           */
-#define  SPI_CR1_RXONLY                      0x00000400U            /*!<Receive only                        */
-#define  SPI_CR1_DFF                         0x00000800U            /*!<Data Frame Format                   */
-#define  SPI_CR1_CRCNEXT                     0x00001000U            /*!<Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       0x00002000U            /*!<Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      0x00004000U            /*!<Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    0x00008000U            /*!<Bidirectional data mode enable      */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     0x00000001U               /*!<Rx Buffer DMA Enable                 */
-#define  SPI_CR2_TXDMAEN                     0x00000002U               /*!<Tx Buffer DMA Enable                 */
-#define  SPI_CR2_SSOE                        0x00000004U               /*!<SS Output Enable                     */
-#define  SPI_CR2_FRF                         0x00000010U               /*!<Frame Format                         */
-#define  SPI_CR2_ERRIE                       0x00000020U               /*!<Error Interrupt Enable               */
-#define  SPI_CR2_RXNEIE                      0x00000040U               /*!<RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       0x00000080U               /*!<Tx buffer Empty Interrupt Enable     */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         0x00000001U               /*!<Receive buffer Not Empty */
-#define  SPI_SR_TXE                          0x00000002U               /*!<Transmit buffer Empty    */
-#define  SPI_SR_CHSIDE                       0x00000004U               /*!<Channel side             */
-#define  SPI_SR_UDR                          0x00000008U               /*!<Underrun flag            */
-#define  SPI_SR_CRCERR                       0x00000010U               /*!<CRC Error flag           */
-#define  SPI_SR_MODF                         0x00000020U               /*!<Mode fault               */
-#define  SPI_SR_OVR                          0x00000040U               /*!<Overrun flag             */
-#define  SPI_SR_BSY                          0x00000080U               /*!<Busy flag                */
-#define  SPI_SR_FRE                          0x00000100U               /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           0x0000FFFFU            /*!<Data Register           */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   0x0000FFFFU            /*!<CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    0x0000FFFFU            /*!<Rx CRC Register         */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    0x0000FFFFU            /*!<Tx CRC Register         */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   0x00000001U            /*!<Channel length (number of bits per audio channel) */
-
-#define  SPI_I2SCFGR_DATLEN                  0x00000006U            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define  SPI_I2SCFGR_DATLEN_0                0x00000002U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                0x00000004U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_CKPOL                   0x00000008U            /*!<steady state clock polarity               */
-
-#define  SPI_I2SCFGR_I2SSTD                  0x00000030U            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U            /*!<PCM frame synchronization                 */
-
-#define  SPI_I2SCFGR_I2SCFG                  0x00000300U            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_I2SE                    0x00000400U            /*!<I2S Enable         */
-#define  SPI_I2SCFGR_I2SMOD                  0x00000800U            /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    0x000000FFU            /*!<I2S Linear prescaler         */
-#define  SPI_I2SPR_ODD                       0x00000100U            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     0x00000200U            /*!<Master Clock Output Enable   */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 SYSCFG                                     */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
-#define SYSCFG_MEMRMP_MEM_MODE          0x00000007U /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        0x00000001U
-#define SYSCFG_MEMRMP_MEM_MODE_1        0x00000002U
-#define SYSCFG_MEMRMP_MEM_MODE_2        0x00000004U
-
-#define SYSCFG_SWP_FSMC                  0x00000C00U /*!< FSMC memory mapping swap */
-/******************  Bit definition for SYSCFG_PMC register  ******************/
-#define SYSCFG_PMC_ADC1DC2              0x00010000U /*!< Refer to AN4073 on how to use this bit  */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
-/** 
-  * @brief   EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         0x0003U /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         0x0004U /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         0x0005U /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         0x0006U /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
-
-/** 
-  * @brief   EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         0x0030U /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         0x0040U /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         0x0050U /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         0x0060U /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
-
-/** 
-  * @brief   EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         0x0300U /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         0x0400U /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         0x0500U /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         0x0600U /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
-
-/** 
-  * @brief   EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         0x3000U /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         0x4000U /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         0x5000U /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         0x6000U /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
-/** 
-  * @brief   EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         0x0003U /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         0x0004U /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         0x0005U /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         0x0006U /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
-
-/** 
-  * @brief   EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         0x0030U /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         0x0040U /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         0x0050U /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         0x0060U /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
-
-/** 
-  * @brief   EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         0x0300U /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         0x0400U /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         0x0500U /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         0x0600U /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
-
-/** 
-  * @brief   EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         0x3000U /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         0x4000U /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         0x5000U /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         0x6000U /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
-
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
-
-/** 
-  * @brief   EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         0x0003U /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         0x0004U /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         0x0005U /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         0x0006U /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
-
-/** 
-  * @brief   EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         0x0030U /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         0x0040U /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         0x0050U /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         0x0060U /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
-
-/** 
-  * @brief   EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        0x0300U /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        0x0400U /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        0x0500U /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        0x0600U /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
-
-/** 
-  * @brief   EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        0x3000U /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        0x4000U /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        0x5000U /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        0x6000U /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
-/** 
-  * @brief   EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        0x0003U /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        0x0004U /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        0x0005U /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        0x0006U /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
-
-/** 
-  * @brief   EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        0x0030U /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        0x0040U /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        0x0050U /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        0x0060U /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
-
-/** 
-  * @brief   EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        0x0300U /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        0x0400U /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        0x0500U /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        0x0600U /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
-
-/** 
-  * @brief   EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        0x3000U /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        0x4000U /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        0x5000U /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        0x6000U /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
-
-/******************  Bit definition for SYSCFG_CMPCR register  ****************/
-#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell ready flag */
-#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell power-down */
-
-/******************  Bit definition for SYSCFG_CFGR register  *****************/
-#define SYSCFG_CFGR_FMPI2C1_SCL         0x00000001U /*!<FM+ drive capability for FMPI2C1_SCL pin */
-#define SYSCFG_CFGR_FMPI2C1_SDA         0x00000002U /*!<FM+ drive capability for FMPI2C1_SDA pin */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    TIM                                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
-#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
-#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
-#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
-#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
-
-#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
-
-#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
-
-#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        0x0001U            /*!<Capture/Compare Preloaded Control        */
-#define  TIM_CR2_CCUS                        0x0004U            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        0x0008U            /*!<Capture/Compare DMA Selection            */
-
-#define  TIM_CR2_MMS                         0x0070U            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
-#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
-#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
-#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        0x0007U            /*!<SMS[2:0] bits (Slave mode selection)    */
-#define  TIM_SMCR_SMS_0                      0x0001U            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      0x0002U            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      0x0004U            /*!<Bit 2 */
-
-#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
-#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
-
-#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
-
-#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
-
-#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
-#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
-#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
-#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
-#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
-#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
-#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
-#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
-#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
-#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
-#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
-#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
-#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
-#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
-#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
-#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
-#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
-#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
-#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          0x01U               /*!<Update Generation                         */
-#define  TIM_EGR_CC1G                        0x02U               /*!<Capture/Compare 1 Generation              */
-#define  TIM_EGR_CC2G                        0x04U               /*!<Capture/Compare 2 Generation              */
-#define  TIM_EGR_CC3G                        0x08U               /*!<Capture/Compare 3 Generation              */
-#define  TIM_EGR_CC4G                        0x10U               /*!<Capture/Compare 4 Generation              */
-#define  TIM_EGR_COMG                        0x20U               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          0x40U               /*!<Trigger Generation                        */
-#define  TIM_EGR_BG                          0x80U               /*!<Break Generation                          */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      0x0003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    0x0001U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    0x0002U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC1FE                     0x0004U            /*!<Output Compare 1 Fast enable                 */
-#define  TIM_CCMR1_OC1PE                     0x0008U            /*!<Output Compare 1 Preload enable              */
-
-#define  TIM_CCMR1_OC1M                      0x0070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define  TIM_CCMR1_OC1M_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    0x0040U            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC1CE                     0x0080U            /*!<Output Compare 1Clear Enable                 */
-
-#define  TIM_CCMR1_CC2S                      0x0300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    0x0100U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    0x0200U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC2FE                     0x0400U            /*!<Output Compare 2 Fast enable                 */
-#define  TIM_CCMR1_OC2PE                     0x0800U            /*!<Output Compare 2 Preload enable              */
-
-#define  TIM_CCMR1_OC2M                      0x7000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define  TIM_CCMR1_OC2M_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    0x4000U            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC2CE                     0x8000U            /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      0x0003U            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define  TIM_CCMR2_CC3S_0                    0x0001U            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    0x0002U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC3FE                     0x0004U            /*!<Output Compare 3 Fast enable           */
-#define  TIM_CCMR2_OC3PE                     0x0008U            /*!<Output Compare 3 Preload enable        */
-
-#define  TIM_CCMR2_OC3M                      0x0070U            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    0x0040U            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC3CE                     0x0080U            /*!<Output Compare 3 Clear Enable */
-
-#define  TIM_CCMR2_CC4S                      0x0300U            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    0x0100U            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    0x0200U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC4FE                     0x0400U            /*!<Output Compare 4 Fast enable    */
-#define  TIM_CCMR2_OC4PE                     0x0800U            /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR2_OC4M                      0x7000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    0x4000U            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       0x0001U            /*!<Capture/Compare 1 output enable                 */
-#define  TIM_CCER_CC1P                       0x0002U            /*!<Capture/Compare 1 output Polarity               */
-#define  TIM_CCER_CC1NE                      0x0004U            /*!<Capture/Compare 1 Complementary output enable   */
-#define  TIM_CCER_CC1NP                      0x0008U            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       0x0010U            /*!<Capture/Compare 2 output enable                 */
-#define  TIM_CCER_CC2P                       0x0020U            /*!<Capture/Compare 2 output Polarity               */
-#define  TIM_CCER_CC2NE                      0x0040U            /*!<Capture/Compare 2 Complementary output enable   */
-#define  TIM_CCER_CC2NP                      0x0080U            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       0x0100U            /*!<Capture/Compare 3 output enable                 */
-#define  TIM_CCER_CC3P                       0x0200U            /*!<Capture/Compare 3 output Polarity               */
-#define  TIM_CCER_CC3NE                      0x0400U            /*!<Capture/Compare 3 Complementary output enable   */
-#define  TIM_CCER_CC3NP                      0x0800U            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       0x1000U            /*!<Capture/Compare 4 output enable                 */
-#define  TIM_CCER_CC4P                       0x2000U            /*!<Capture/Compare 4 output Polarity               */
-#define  TIM_CCER_CC4NP                      0x8000U            /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         0xFFU               /*!<Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
-
-/*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        0x00FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      0x0001U            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      0x0002U            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      0x0004U            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      0x0008U            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      0x0010U            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      0x0020U            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      0x0040U            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      0x0080U            /*!<Bit 7 */
-
-#define  TIM_BDTR_LOCK                       0x0300U            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     0x0100U            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     0x0200U            /*!<Bit 1 */
-
-#define  TIM_BDTR_OSSI                       0x0400U            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       0x0800U            /*!<Off-State Selection for Run mode  */
-#define  TIM_BDTR_BKE                        0x1000U            /*!<Break enable                      */
-#define  TIM_BDTR_BKP                        0x2000U            /*!<Break Polarity                    */
-#define  TIM_BDTR_AOE                        0x4000U            /*!<Automatic Output enable           */
-#define  TIM_BDTR_MOE                        0x8000U            /*!<Main Output enable                */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
-
-#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
-#define TIM_OR_ITR1_RMP                      0x0C00U            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
-#define TIM_OR_ITR1_RMP_0                    0x0400U            /*!<Bit 0 */
-#define TIM_OR_ITR1_RMP_1                    0x0800U            /*!<Bit 1 */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*         Universal Synchronous Asynchronous Receiver Transmitter            */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         0x0001U            /*!<Parity Error                 */
-#define  USART_SR_FE                         0x0002U            /*!<Framing Error                */
-#define  USART_SR_NE                         0x0004U            /*!<Noise Error Flag             */
-#define  USART_SR_ORE                        0x0008U            /*!<OverRun Error                */
-#define  USART_SR_IDLE                       0x0010U            /*!<IDLE line detected           */
-#define  USART_SR_RXNE                       0x0020U            /*!<Read Data Register Not Empty */
-#define  USART_SR_TC                         0x0040U            /*!<Transmission Complete        */
-#define  USART_SR_TXE                        0x0080U            /*!<Transmit Data Register Empty */
-#define  USART_SR_LBD                        0x0100U            /*!<LIN Break Detection Flag     */
-#define  USART_SR_CTS                        0x0200U            /*!<CTS Flag                     */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         0x01FFU            /*!<Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_Fraction              0x000FU            /*!<Fraction of USARTDIV */
-#define  USART_BRR_DIV_Mantissa              0xFFF0U            /*!<Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       0x0001U            /*!<Send Break                             */
-#define  USART_CR1_RWU                       0x0002U            /*!<Receiver wakeup                        */
-#define  USART_CR1_RE                        0x0004U            /*!<Receiver Enable                        */
-#define  USART_CR1_TE                        0x0008U            /*!<Transmitter Enable                     */
-#define  USART_CR1_IDLEIE                    0x0010U            /*!<IDLE Interrupt Enable                  */
-#define  USART_CR1_RXNEIE                    0x0020U            /*!<RXNE Interrupt Enable                  */
-#define  USART_CR1_TCIE                      0x0040U            /*!<Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     0x0080U            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PEIE                      0x0100U            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PS                        0x0200U            /*!<Parity Selection                       */
-#define  USART_CR1_PCE                       0x0400U            /*!<Parity Control Enable                  */
-#define  USART_CR1_WAKE                      0x0800U            /*!<Wakeup method                          */
-#define  USART_CR1_M                         0x1000U            /*!<Word length                            */
-#define  USART_CR1_UE                        0x2000U            /*!<USART Enable                           */
-#define  USART_CR1_OVER8                     0x8000U            /*!<USART Oversampling by 8 enable         */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       0x000FU            /*!<Address of the USART node            */
-#define  USART_CR2_LBDL                      0x0020U            /*!<LIN Break Detection Length           */
-#define  USART_CR2_LBDIE                     0x0040U            /*!<LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      0x0100U            /*!<Last Bit Clock pulse                 */
-#define  USART_CR2_CPHA                      0x0200U            /*!<Clock Phase                          */
-#define  USART_CR2_CPOL                      0x0400U            /*!<Clock Polarity                       */
-#define  USART_CR2_CLKEN                     0x0800U            /*!<Clock Enable                         */
-
-#define  USART_CR2_STOP                      0x3000U            /*!<STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    0x1000U            /*!<Bit 0 */
-#define  USART_CR2_STOP_1                    0x2000U            /*!<Bit 1 */
-
-#define  USART_CR2_LINEN                     0x4000U            /*!<LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       0x0001U            /*!<Error Interrupt Enable      */
-#define  USART_CR3_IREN                      0x0002U            /*!<IrDA mode Enable            */
-#define  USART_CR3_IRLP                      0x0004U            /*!<IrDA Low-Power              */
-#define  USART_CR3_HDSEL                     0x0008U            /*!<Half-Duplex Selection       */
-#define  USART_CR3_NACK                      0x0010U            /*!<Smartcard NACK enable       */
-#define  USART_CR3_SCEN                      0x0020U            /*!<Smartcard mode enable       */
-#define  USART_CR3_DMAR                      0x0040U            /*!<DMA Enable Receiver         */
-#define  USART_CR3_DMAT                      0x0080U            /*!<DMA Enable Transmitter      */
-#define  USART_CR3_RTSE                      0x0100U            /*!<RTS Enable                  */
-#define  USART_CR3_CTSE                      0x0200U            /*!<CTS Enable                  */
-#define  USART_CR3_CTSIE                     0x0400U            /*!<CTS Interrupt Enable        */
-#define  USART_CR3_ONEBIT                    0x0800U            /*!<USART One bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      0x00FFU            /*!<PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    0x0001U            /*!<Bit 0 */
-#define  USART_GTPR_PSC_1                    0x0002U            /*!<Bit 1 */
-#define  USART_GTPR_PSC_2                    0x0004U            /*!<Bit 2 */
-#define  USART_GTPR_PSC_3                    0x0008U            /*!<Bit 3 */
-#define  USART_GTPR_PSC_4                    0x0010U            /*!<Bit 4 */
-#define  USART_GTPR_PSC_5                    0x0020U            /*!<Bit 5 */
-#define  USART_GTPR_PSC_6                    0x0040U            /*!<Bit 6 */
-#define  USART_GTPR_PSC_7                    0x0080U            /*!<Bit 7 */
-
-#define  USART_GTPR_GT                       0xFF00U            /*!<Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Window WATCHDOG                                 */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           0x7FU               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T_0                         0x01U               /*!<Bit 0 */
-#define  WWDG_CR_T_1                         0x02U               /*!<Bit 1 */
-#define  WWDG_CR_T_2                         0x04U               /*!<Bit 2 */
-#define  WWDG_CR_T_3                         0x08U               /*!<Bit 3 */
-#define  WWDG_CR_T_4                         0x10U               /*!<Bit 4 */
-#define  WWDG_CR_T_5                         0x20U               /*!<Bit 5 */
-#define  WWDG_CR_T_6                         0x40U               /*!<Bit 6 */
-/* Legacy defines */
-#define  WWDG_CR_T0                          WWDG_CR_T_0
-#define  WWDG_CR_T1                          WWDG_CR_T_1
-#define  WWDG_CR_T2                          WWDG_CR_T_2
-#define  WWDG_CR_T3                          WWDG_CR_T_3
-#define  WWDG_CR_T4                          WWDG_CR_T_4
-#define  WWDG_CR_T5                          WWDG_CR_T_5
-#define  WWDG_CR_T6                          WWDG_CR_T_6
-
-#define  WWDG_CR_WDGA                        0x80U               /*!<Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          0x007FU            /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W_0                        0x0001U            /*!<Bit 0 */
-#define  WWDG_CFR_W_1                        0x0002U            /*!<Bit 1 */
-#define  WWDG_CFR_W_2                        0x0004U            /*!<Bit 2 */
-#define  WWDG_CFR_W_3                        0x0008U            /*!<Bit 3 */
-#define  WWDG_CFR_W_4                        0x0010U            /*!<Bit 4 */
-#define  WWDG_CFR_W_5                        0x0020U            /*!<Bit 5 */
-#define  WWDG_CFR_W_6                        0x0040U            /*!<Bit 6 */
-/* Legacy defines */
-#define  WWDG_CFR_W0                         WWDG_CFR_W_0
-#define  WWDG_CFR_W1                         WWDG_CFR_W_1
-#define  WWDG_CFR_W2                         WWDG_CFR_W_2
-#define  WWDG_CFR_W3                         WWDG_CFR_W_3
-#define  WWDG_CFR_W4                         WWDG_CFR_W_4
-#define  WWDG_CFR_W5                         WWDG_CFR_W_5
-#define  WWDG_CFR_W6                         WWDG_CFR_W_6
-
-#define  WWDG_CFR_WDGTB                      0x0180U            /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB_0                    0x0080U            /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB_1                    0x0100U            /*!<Bit 1 */
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
-
-#define  WWDG_CFR_EWI                        0x0200U            /*!<Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        0x01U               /*!<Early Wakeup Interrupt Flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                DBG                                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
-#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
-
-/********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
-#define  DBGMCU_CR_DBG_STOP                  0x00000002U
-#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
-#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
-
-#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
-#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U/*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U/*!<Bit 1 */
-
-/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            0x00000001U
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            0x00000002U
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            0x00000004U
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            0x00000020U
-#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           0x00000040U
-#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           0x00000080U
-#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           0x00000100U
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
-#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
-
-/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        0x00000001U
-#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        0x00000002U
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        0x00010000U
-#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       0x00020000U
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       0x00040000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                                       USB_OTG			                        */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for USB_OTG_GOTGCTL register  ***********/
-#define USB_OTG_GOTGCTL_SRQSCS                  0x00000001U         /*!< Session request success */
-#define USB_OTG_GOTGCTL_SRQ                     0x00000002U         /*!< Session request */
-#define USB_OTG_GOTGCTL_VBVALOEN                0x00000004U         /*!< VBUS valid override enable */
-#define USB_OTG_GOTGCTL_VBVALOVAL               0x00000008U         /*!< VBUS valid override value */
-#define USB_OTG_GOTGCTL_AVALOEN                 0x00000010U         /*!< A-peripheral session valid override enable */
-#define USB_OTG_GOTGCTL_AVALOVAL                0x00000020U         /*!< A-peripheral session valid override value */
-#define USB_OTG_GOTGCTL_BVALOEN                 0x00000040U         /*!< B-peripheral session valid override enable */
-#define USB_OTG_GOTGCTL_BVALOVAL                0x00000080U         /*!< B-peripheral session valid override value  */
-#define USB_OTG_GOTGCTL_HNGSCS                  0x00000100U         /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_HNPRQ                   0x00000200U         /*!< HNP request */
-#define USB_OTG_GOTGCTL_HSHNPEN                 0x00000400U         /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_DHNPEN                  0x00000800U         /*!< Device HNP enabled */
-#define USB_OTG_GOTGCTL_EHEN                    0x00001000U         /*!< Embedded host enable */
-#define USB_OTG_GOTGCTL_CIDSTS                  0x00010000U         /*!< Connector ID status */
-#define USB_OTG_GOTGCTL_DBCT                    0x00020000U         /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD                   0x00040000U         /*!< A-session valid  */
-#define USB_OTG_GOTGCTL_BSESVLD                 0x00080000U         /*!< B-session valid */
-#define USB_OTG_GOTGCTL_OTGVER                  0x00100000U         /*!< OTG version  */
-
-/********************  Bit definition for USB_OTG_HCFG register  **************/
-
-#define USB_OTG_HCFG_FSLSPCS                 0x00000003U            /*!< FS/LS PHY clock select */
-#define USB_OTG_HCFG_FSLSPCS_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCFG_FSLSPCS_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCFG_FSLSS                   0x00000004U            /*!< FS- and LS-only support */
-
-/********************  Bit definition for USB_OTG_DCFG register  **************/
-
-#define USB_OTG_DCFG_DSPD                    0x00000003U            /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                  0x00000001U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DSPD_1                  0x00000002U            /*!<Bit 1 */
-#define USB_OTG_DCFG_NZLSOHSK                0x00000004U            /*!< Nonzero-length status OUT handshake */
-
-#define USB_OTG_DCFG_DAD                     0x000007F0U            /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                   0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DAD_1                   0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCFG_DAD_2                   0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCFG_DAD_3                   0x00000080U            /*!<Bit 3 */
-#define USB_OTG_DCFG_DAD_4                   0x00000100U            /*!<Bit 4 */
-#define USB_OTG_DCFG_DAD_5                   0x00000200U            /*!<Bit 5 */
-#define USB_OTG_DCFG_DAD_6                   0x00000400U            /*!<Bit 6 */
-
-#define USB_OTG_DCFG_PFIVL                   0x00001800U            /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PFIVL_1                 0x00001000U            /*!<Bit 1 */
-
-#define USB_OTG_DCFG_PERSCHIVL               0x03000000U            /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0             0x01000000U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PERSCHIVL_1             0x02000000U            /*!<Bit 1 */
-
-/********************  Bit definition for USB_OTG_PCGCR register  *************/
-#define USB_OTG_PCGCR_STPPCLK                 0x00000001U            /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK                0x00000002U            /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP                 0x00000010U            /*!< PHY suspended */
-
-/********************  Bit definition for USB_OTG_GOTGINT register  ***********/
-#define USB_OTG_GOTGINT_SEDET                   0x00000004U            /*!< Session end detected */
-#define USB_OTG_GOTGINT_SRSSCHG                 0x00000100U            /*!< Session request success status change */
-#define USB_OTG_GOTGINT_HNSSCHG                 0x00000200U            /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET                  0x00020000U            /*!< Host negotiation detected */
-#define USB_OTG_GOTGINT_ADTOCHG                 0x00040000U            /*!< A-device timeout change */
-#define USB_OTG_GOTGINT_DBCDNE                  0x00080000U            /*!< Debounce done */
-#define USB_OTG_GOTGINT_IDCHNG                  0x00100000U            /*!< Change in ID pin input value           */
-
-/********************  Bit definition for USB_OTG_DCTL register  **************/
-#define USB_OTG_DCTL_RWUSIG                  0x00000001U            /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS                    0x00000002U            /*!< Soft disconnect */
-#define USB_OTG_DCTL_GINSTS                  0x00000004U            /*!< Global IN NAK status */
-#define USB_OTG_DCTL_GONSTS                  0x00000008U            /*!< Global OUT NAK status */
-#define USB_OTG_DCTL_TCTL                    0x00000070U            /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                  0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCTL_TCTL_1                  0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCTL_TCTL_2                  0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCTL_SGINAK                  0x00000080U            /*!< Set global IN NAK */
-#define USB_OTG_DCTL_CGINAK                  0x00000100U            /*!< Clear global IN NAK */
-#define USB_OTG_DCTL_SGONAK                  0x00000200U            /*!< Set global OUT NAK */
-#define USB_OTG_DCTL_CGONAK                  0x00000400U            /*!< Clear global OUT NAK */
-#define USB_OTG_DCTL_POPRGDNE                0x00000800U            /*!< Power-on programming done */
-
-/********************  Bit definition for USB_OTG_HFIR register  **************/
-#define USB_OTG_HFIR_FRIVL                   0x0000FFFFU            /*!< Frame interval */
-
-/********************  Bit definition for USB_OTG_HFNUM register  *************/
-#define USB_OTG_HFNUM_FRNUM                   0x0000FFFFU            /*!< Frame number */
-#define USB_OTG_HFNUM_FTREM                   0xFFFF0000U            /*!< Frame time remaining */
-
-/********************  Bit definition for USB_OTG_DSTS register  **************/
-#define USB_OTG_DSTS_SUSPSTS                 0x00000001U            /*!< Suspend status */
-
-#define USB_OTG_DSTS_ENUMSPD                 0x00000006U            /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_DSTS_ENUMSPD_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_DSTS_EERR                    0x00000008U            /*!< Erratic error */
-#define USB_OTG_DSTS_FNSOF                   0x003FFF00U            /*!< Frame number of the received SOF */
-
-/********************  Bit definition for USB_OTG_GAHBCFG register  ***********/
-#define USB_OTG_GAHBCFG_GINT                    0x00000001U            /*!< Global interrupt mask */
-#define USB_OTG_GAHBCFG_HBSTLEN                 0x0000001EU            /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_GAHBCFG_HBSTLEN_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_GAHBCFG_HBSTLEN_2               0x00000008U            /*!<Bit 2 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3               0x00000010U            /*!<Bit 3 */
-#define USB_OTG_GAHBCFG_DMAEN                   0x00000020U            /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL                 0x00000080U            /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL                0x00000100U            /*!< Periodic TxFIFO empty level */
-
-/********************  Bit definition for USB_OTG_GUSBCFG register  ***********/
-#define USB_OTG_GUSBCFG_TOCAL                   0x00000007U            /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TOCAL_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TOCAL_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_PHYSEL                  0x00000040U            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP                  0x00000100U            /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP                  0x00000200U            /*!< HNP-capable */
-
-#define USB_OTG_GUSBCFG_TRDT                    0x00003C00U            /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                  0x00000400U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TRDT_1                  0x00000800U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TRDT_2                  0x00001000U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_TRDT_3                  0x00002000U            /*!<Bit 3 */
-#define USB_OTG_GUSBCFG_PHYLPCS                 0x00008000U            /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS                0x00020000U            /*!< ULPI FS/LS select */
-#define USB_OTG_GUSBCFG_ULPIAR                  0x00040000U            /*!< ULPI Auto-resume */
-#define USB_OTG_GUSBCFG_ULPICSM                 0x00080000U            /*!< ULPI Clock SuspendM */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD              0x00100000U            /*!< ULPI External VBUS Drive */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI              0x00200000U            /*!< ULPI external VBUS indicator */
-#define USB_OTG_GUSBCFG_TSDPS                   0x00400000U            /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI                    0x00800000U            /*!< Indicator complement */
-#define USB_OTG_GUSBCFG_PTCI                    0x01000000U            /*!< Indicator pass through */
-#define USB_OTG_GUSBCFG_ULPIIPD                 0x02000000U            /*!< ULPI interface protect disable */
-#define USB_OTG_GUSBCFG_FHMOD                   0x20000000U            /*!< Forced host mode */
-#define USB_OTG_GUSBCFG_FDMOD                   0x40000000U            /*!< Forced peripheral mode */
-#define USB_OTG_GUSBCFG_CTXPKT                  0x80000000U            /*!< Corrupt Tx packet */
-
-/********************  Bit definition for USB_OTG_GRSTCTL register  ***********/
-#define USB_OTG_GRSTCTL_CSRST                   0x00000001U            /*!< Core soft reset */
-#define USB_OTG_GRSTCTL_HSRST                   0x00000002U            /*!< HCLK soft reset */
-#define USB_OTG_GRSTCTL_FCRST                   0x00000004U            /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH                 0x00000010U            /*!< RxFIFO flush */
-#define USB_OTG_GRSTCTL_TXFFLSH                 0x00000020U            /*!< TxFIFO flush */
-
-#define USB_OTG_GRSTCTL_TXFNUM                  0x000007C0U            /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                0x00000040U            /*!<Bit 0 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                0x00000080U            /*!<Bit 1 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                0x00000100U            /*!<Bit 2 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                0x00000200U            /*!<Bit 3 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                0x00000400U            /*!<Bit 4 */
-#define USB_OTG_GRSTCTL_DMAREQ                  0x40000000U            /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL                  0x80000000U            /*!< AHB master idle */
-
-/********************  Bit definition for USB_OTG_DIEPMSK register  ***********/
-#define USB_OTG_DIEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPMSK_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPMSK_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPMSK_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPMSK_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPMSK_BIM                     0x00000200U            /*!< BNA interrupt mask */
-
-/********************  Bit definition for USB_OTG_HPTXSTS register  ***********/
-#define USB_OTG_HPTXSTS_PTXFSAVL                0x0000FFFFU            /*!< Periodic transmit data FIFO space available */
-
-#define USB_OTG_HPTXSTS_PTXQSAV                 0x00FF0000U            /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0               0x00010000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1               0x00020000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2               0x00040000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3               0x00080000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4               0x00100000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5               0x00200000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6               0x00400000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7               0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_HPTXSTS_PTXQTOP                 0xFF000000U            /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0               0x01000000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1               0x02000000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2               0x04000000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3               0x08000000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4               0x10000000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5               0x20000000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6               0x40000000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7               0x80000000U            /*!<Bit 7 */
-
-/********************  Bit definition for USB_OTG_HAINT register  *************/
-#define USB_OTG_HAINT_HAINT                   0x0000FFFFU            /*!< Channel interrupts */
-
-/********************  Bit definition for USB_OTG_DOEPMSK register  ***********/
-#define USB_OTG_DOEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPMSK_STUPM                   0x00000008U            /*!< SETUP phase done mask */
-#define USB_OTG_DOEPMSK_OTEPDM                  0x00000010U            /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_OTEPSPRM                0x00000020U            /*!< Status Phase Received mask                     */
-#define USB_OTG_DOEPMSK_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received mask */
-#define USB_OTG_DOEPMSK_OPEM                    0x00000100U            /*!< OUT packet error mask */
-#define USB_OTG_DOEPMSK_BOIM                    0x00000200U            /*!< BNA interrupt mask */
-
-/********************  Bit definition for USB_OTG_GINTSTS register  ***********/
-#define USB_OTG_GINTSTS_CMOD                    0x00000001U            /*!< Current mode of operation                      */
-#define USB_OTG_GINTSTS_MMIS                    0x00000002U            /*!< Mode mismatch interrupt                        */
-#define USB_OTG_GINTSTS_OTGINT                  0x00000004U            /*!< OTG interrupt                                  */
-#define USB_OTG_GINTSTS_SOF                     0x00000008U            /*!< Start of frame                                 */
-#define USB_OTG_GINTSTS_RXFLVL                  0x00000010U            /*!< RxFIFO nonempty                                */
-#define USB_OTG_GINTSTS_NPTXFE                  0x00000020U            /*!< Nonperiodic TxFIFO empty                       */
-#define USB_OTG_GINTSTS_GINAKEFF                0x00000040U            /*!< Global IN nonperiodic NAK effective            */
-#define USB_OTG_GINTSTS_BOUTNAKEFF              0x00000080U            /*!< Global OUT NAK effective                       */
-#define USB_OTG_GINTSTS_ESUSP                   0x00000400U            /*!< Early suspend                                  */
-#define USB_OTG_GINTSTS_USBSUSP                 0x00000800U            /*!< USB suspend                                    */
-#define USB_OTG_GINTSTS_USBRST                  0x00001000U            /*!< USB reset                                      */
-#define USB_OTG_GINTSTS_ENUMDNE                 0x00002000U            /*!< Enumeration done                               */
-#define USB_OTG_GINTSTS_ISOODRP                 0x00004000U            /*!< Isochronous OUT packet dropped interrupt       */
-#define USB_OTG_GINTSTS_EOPF                    0x00008000U            /*!< End of periodic frame interrupt                */
-#define USB_OTG_GINTSTS_IEPINT                  0x00040000U            /*!< IN endpoint interrupt                          */
-#define USB_OTG_GINTSTS_OEPINT                  0x00080000U            /*!< OUT endpoint interrupt                         */
-#define USB_OTG_GINTSTS_IISOIXFR                0x00100000U            /*!< Incomplete isochronous IN transfer             */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       0x00200000U            /*!< Incomplete periodic transfer                   */
-#define USB_OTG_GINTSTS_DATAFSUSP               0x00400000U            /*!< Data fetch suspended                           */
-#define USB_OTG_GINTSTS_RSTDET                  0x00800000U            /*!< Reset detected interrupt                       */
-#define USB_OTG_GINTSTS_HPRTINT                 0x01000000U            /*!< Host port interrupt                            */
-#define USB_OTG_GINTSTS_HCINT                   0x02000000U            /*!< Host channels interrupt                        */
-#define USB_OTG_GINTSTS_PTXFE                   0x04000000U            /*!< Periodic TxFIFO empty                          */
-#define USB_OTG_GINTSTS_LPMINT                  0x08000000U            /*!< LPM interrupt                                  */
-#define USB_OTG_GINTSTS_CIDSCHG                 0x10000000U            /*!< Connector ID status change                     */
-#define USB_OTG_GINTSTS_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt                  */
-#define USB_OTG_GINTSTS_SRQINT                  0x40000000U            /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT                  0x80000000U            /*!< Resume/remote wakeup detected interrupt        */
-
-/********************  Bit definition for USB_OTG_GINTMSK register  ***********/
-#define USB_OTG_GINTMSK_MMISM                   0x00000002U         /*!< Mode mismatch interrupt mask */
-#define USB_OTG_GINTMSK_OTGINT                  0x00000004U         /*!< OTG interrupt mask */
-#define USB_OTG_GINTMSK_SOFM                    0x00000008U         /*!< Start of frame mask */
-#define USB_OTG_GINTMSK_RXFLVLM                 0x00000010U         /*!< Receive FIFO nonempty mask */
-#define USB_OTG_GINTMSK_NPTXFEM                 0x00000020U         /*!< Nonperiodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_GINAKEFFM               0x00000040U         /*!< Global nonperiodic IN NAK effective mask */
-#define USB_OTG_GINTMSK_GONAKEFFM               0x00000080U         /*!< Global OUT NAK effective mask */
-#define USB_OTG_GINTMSK_ESUSPM                  0x00000400U         /*!< Early suspend mask */
-#define USB_OTG_GINTMSK_USBSUSPM                0x00000800U         /*!< USB suspend mask */
-#define USB_OTG_GINTMSK_USBRST                  0x00001000U         /*!< USB reset mask */
-#define USB_OTG_GINTMSK_ENUMDNEM                0x00002000U         /*!< Enumeration done mask */
-#define USB_OTG_GINTMSK_ISOODRPM                0x00004000U         /*!< Isochronous OUT packet dropped interrupt mask */
-#define USB_OTG_GINTMSK_EOPFM                   0x00008000U         /*!< End of periodic frame interrupt mask */
-#define USB_OTG_GINTMSK_EPMISM                  0x00020000U         /*!< Endpoint mismatch interrupt mask */
-#define USB_OTG_GINTMSK_IEPINT                  0x00040000U         /*!< IN endpoints interrupt mask */
-#define USB_OTG_GINTMSK_OEPINT                  0x00080000U         /*!< OUT endpoints interrupt mask */
-#define USB_OTG_GINTMSK_IISOIXFRM               0x00100000U         /*!< Incomplete isochronous IN transfer mask */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         0x00200000U         /*!< Incomplete periodic transfer mask */
-#define USB_OTG_GINTMSK_FSUSPM                  0x00400000U         /*!< Data fetch suspended mask */
-#define USB_OTG_GINTMSK_RSTDETM                 0x00800000U         /*!< Reset detected interrupt mask */
-#define USB_OTG_GINTMSK_PRTIM                   0x01000000U         /*!< Host port interrupt mask */
-#define USB_OTG_GINTMSK_HCIM                    0x02000000U         /*!< Host channels interrupt mask */
-#define USB_OTG_GINTMSK_PTXFEM                  0x04000000U         /*!< Periodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_LPMINTM                 0x08000000U         /*!< LPM interrupt Mask */
-#define USB_OTG_GINTMSK_CIDSCHGM                0x10000000U         /*!< Connector ID status change mask */
-#define USB_OTG_GINTMSK_DISCINT                 0x20000000U         /*!< Disconnect detected interrupt mask */
-#define USB_OTG_GINTMSK_SRQIM                   0x40000000U         /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM                    0x80000000U         /*!< Resume/remote wakeup detected interrupt mask */
-
-/********************  Bit definition for USB_OTG_DAINT register  *************/
-#define USB_OTG_DAINT_IEPINT                  0x0000FFFFU            /*!< IN endpoint interrupt bits */
-#define USB_OTG_DAINT_OEPINT                  0xFFFF0000U            /*!< OUT endpoint interrupt bits */
-
-/********************  Bit definition for USB_OTG_HAINTMSK register  **********/
-#define USB_OTG_HAINTMSK_HAINTM                  0x0000FFFFU            /*!< Channel interrupt mask */
-
-/********************  Bit definition for USB_OTG_GRXSTSP register  ***********/
-#define USB_OTG_GRXSTSP_EPNUM                    0x0000000FU            /*!< IN EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_BCNT                     0x00007FF0U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID                     0x00018000U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS                   0x001E0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for USB_OTG_DAINTMSK register  **********/
-#define USB_OTG_DAINTMSK_IEPM                    0x0000FFFFU            /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM                    0xFFFF0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for OTG register  ***********************/
-
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition for OTG register  ***********************/
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition for USB_OTG_GRXFSIZ register  ***********/
-#define USB_OTG_GRXFSIZ_RXFD            0x0000FFFFU            /*!< RxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DVBUSDIS register  **********/
-#define USB_OTG_DVBUSDIS_VBUSDT         0x0000FFFFU            /*!< Device VBUS discharge time */
-
-/********************  Bit definition for OTG register  ***********************/
-#define USB_OTG_NPTXFSA                 0x0000FFFFU            /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD                  0xFFFF0000U            /*!< Nonperiodic TxFIFO depth */
-#define USB_OTG_TX0FSA                  0x0000FFFFU            /*!< Endpoint 0 transmit RAM start address */
-#define USB_OTG_TX0FD                   0xFFFF0000U            /*!< Endpoint 0 TxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DVBUSPULSE register  ********/
-#define USB_OTG_DVBUSPULSE_DVBUSP                  0x00000FFFU            /*!< Device VBUS pulsing time */
-
-/********************  Bit definition for USB_OTG_GNPTXSTS register  **********/
-#define USB_OTG_GNPTXSTS_NPTXFSAV                0x0000FFFFU            /*!< Nonperiodic TxFIFO space available */
-
-#define USB_OTG_GNPTXSTS_NPTQXSAV                0x00FF0000U            /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0              0x00010000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1              0x00020000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2              0x00040000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3              0x00080000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4              0x00100000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5              0x00200000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6              0x00400000U            /*!<Bit 6 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7              0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_GNPTXSTS_NPTXQTOP                0x7F000000U            /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0              0x01000000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1              0x02000000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2              0x04000000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3              0x08000000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4              0x10000000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5              0x20000000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6              0x40000000U            /*!<Bit 6 */
-
-/********************  Bit definition for USB_OTG_DTHRCTL register  ***********/
-#define USB_OTG_DTHRCTL_NONISOTHREN             0x00000001U            /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN                0x00000002U            /*!< ISO IN endpoint threshold enable */
-
-#define USB_OTG_DTHRCTL_TXTHRLEN                0x000007FCU            /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0              0x00000004U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1              0x00000008U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2              0x00000010U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3              0x00000020U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4              0x00000040U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5              0x00000080U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6              0x00000100U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7              0x00000200U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8              0x00000400U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_RXTHREN                 0x00010000U            /*!< Receive threshold enable */
-
-#define USB_OTG_DTHRCTL_RXTHRLEN                0x03FE0000U            /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0              0x00020000U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1              0x00040000U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2              0x00080000U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3              0x00100000U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4              0x00200000U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5              0x00400000U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6              0x00800000U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7              0x01000000U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8              0x02000000U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_ARPEN                   0x08000000U            /*!< Arbiter parking enable */
-
-/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM               0x0000FFFFU            /*!< IN EP Tx FIFO empty interrupt mask bits */
-
-/********************  Bit definition for USB_OTG_DEACHINT register  **********/
-#define USB_OTG_DEACHINT_IEP1INT                 0x00000002U            /*!< IN endpoint 1interrupt bit */
-#define USB_OTG_DEACHINT_OEP1INT                 0x00020000U            /*!< OUT endpoint 1 interrupt bit */
-
-/********************  Bit definition for USB_OTG_GCCFG register  *************/
-#define USB_OTG_GCCFG_DCDET                  0x00000001U              /*!< Data contact detection (DCD) status */
-#define USB_OTG_GCCFG_PDET                   0x00000002U              /*!< Primary detection (PD) status */
-#define USB_OTG_GCCFG_SDET                   0x00000004U              /*!< Secondary detection (SD) status */
-#define USB_OTG_GCCFG_PS2DET                 0x00000008U              /*!< DM pull-up detection status */
-#define USB_OTG_GCCFG_PWRDWN                 0x00010000U              /*!< Power down */
-#define USB_OTG_GCCFG_BCDEN                  0x00020000U              /*!< Battery charging detector (BCD) enable */
-#define USB_OTG_GCCFG_DCDEN                  0x00040000U              /*!< Data contact detection (DCD) mode enable*/
-#define USB_OTG_GCCFG_PDEN                   0x00080000U              /*!< Primary detection (PD) mode enable*/
-#define USB_OTG_GCCFG_SDEN                   0x00100000U              /*!< Secondary detection (SD) mode enable */
-#define USB_OTG_GCCFG_VBDEN                  0x00200000U              /*!< USB VBUS Detection Enable */
-
-/********************  Bit definition for USB_OTG_DEACHINTMSK register  *******/
-#define USB_OTG_DEACHINTMSK_IEP1INTM                0x00000002U            /*!< IN Endpoint 1 interrupt mask bit */
-#define USB_OTG_DEACHINTMSK_OEP1INTM                0x00020000U            /*!< OUT Endpoint 1 interrupt mask bit */
-
-/********************  Bit definition for USB_OTG_CID register  ***************/
-#define USB_OTG_CID_PRODUCT_ID              0xFFFFFFFFU               /*!< Product ID field */
-
-/********************  Bit definition for USB_OTG_GLPMCFG register  ***********/
-#define  USB_OTG_GLPMCFG_LPMEN               0x00000001U            /*!< LPM support enable                                     */
-#define  USB_OTG_GLPMCFG_LPMACK              0x00000002U            /*!< LPM Token acknowledge enable                           */
-#define  USB_OTG_GLPMCFG_BESL                0x0000003CU            /*!< BESL value received with last ACKed LPM Token          */
-#define  USB_OTG_GLPMCFG_REMWAKE             0x00000040U            /*!< bRemoteWake value received with last ACKed LPM Token   */
-#define  USB_OTG_GLPMCFG_L1SSEN              0x00000080U            /*!< L1 shallow sleep enable                                */
-#define  USB_OTG_GLPMCFG_BESLTHRS            0x00000F00U            /*!< BESL threshold                                         */
-#define  USB_OTG_GLPMCFG_L1DSEN              0x00001000U            /*!< L1 deep sleep enable                                   */
-#define  USB_OTG_GLPMCFG_LPMRSP              0x00006000U            /*!< LPM response                                           */
-#define  USB_OTG_GLPMCFG_SLPSTS              0x00008000U            /*!< Port sleep status                                      */
-#define  USB_OTG_GLPMCFG_L1RSMOK             0x00010000U            /*!< Sleep State Resume OK                                  */
-#define  USB_OTG_GLPMCFG_LPMCHIDX            0x001E0000U            /*!< LPM Channel Index                                      */
-#define  USB_OTG_GLPMCFG_LPMRCNT             0x00E00000U            /*!< LPM retry count                                        */
-#define  USB_OTG_GLPMCFG_SNDLPM              0x01000000U            /*!< Send LPM transaction                                   */
-#define  USB_OTG_GLPMCFG_LPMRCNTSTS          0x0E000000U            /*!< LPM retry count status                                 */
-#define  USB_OTG_GLPMCFG_ENBESL              0x10000000U            /*!< Enable best effort service latency                     */
-
-/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ******/
-#define USB_OTG_DIEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPEACHMSK1_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
-
-/********************  Bit definition for USB_OTG_HPRT register  **************/
-#define USB_OTG_HPRT_PCSTS                   0x00000001U            /*!< Port connect status */
-#define USB_OTG_HPRT_PCDET                   0x00000002U            /*!< Port connect detected */
-#define USB_OTG_HPRT_PENA                    0x00000004U            /*!< Port enable */
-#define USB_OTG_HPRT_PENCHNG                 0x00000008U            /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA                    0x00000010U            /*!< Port overcurrent active */
-#define USB_OTG_HPRT_POCCHNG                 0x00000020U            /*!< Port overcurrent change */
-#define USB_OTG_HPRT_PRES                    0x00000040U            /*!< Port resume */
-#define USB_OTG_HPRT_PSUSP                   0x00000080U            /*!< Port suspend */
-#define USB_OTG_HPRT_PRST                    0x00000100U            /*!< Port reset */
-
-#define USB_OTG_HPRT_PLSTS                   0x00000C00U            /*!< Port line status */
-#define USB_OTG_HPRT_PLSTS_0                 0x00000400U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PLSTS_1                 0x00000800U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PPWR                    0x00001000U            /*!< Port power */
-
-#define USB_OTG_HPRT_PTCTL                   0x0001E000U            /*!< Port test control */
-#define USB_OTG_HPRT_PTCTL_0                 0x00002000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PTCTL_1                 0x00004000U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PTCTL_2                 0x00008000U            /*!<Bit 2 */
-#define USB_OTG_HPRT_PTCTL_3                 0x00010000U            /*!<Bit 3 */
-
-#define USB_OTG_HPRT_PSPD                    0x00060000U            /*!< Port speed */
-#define USB_OTG_HPRT_PSPD_0                  0x00020000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PSPD_1                  0x00040000U            /*!<Bit 1 */
-
-/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ******/
-#define USB_OTG_DOEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DOEPEACHMSK1_TXFURM                  0x00000100U            /*!< OUT packet error mask */
-#define USB_OTG_DOEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_BERRM                   0x00001000U            /*!< Bubble error interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NYETM                   0x00004000U            /*!< NYET interrupt mask */
-
-/********************  Bit definition for USB_OTG_HPTXFSIZ register  **********/
-#define USB_OTG_HPTXFSIZ_PTXSA                   0x0000FFFFU            /*!< Host periodic TxFIFO start address */
-#define USB_OTG_HPTXFSIZ_PTXFD                   0xFFFF0000U            /*!< Host periodic TxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DIEPCTL register  ***********/
-#define USB_OTG_DIEPCTL_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
-#define USB_OTG_DIEPCTL_USBAEP                  0x00008000U            /*!< USB active endpoint */
-#define USB_OTG_DIEPCTL_EONUM_DPID              0x00010000U            /*!< Even/odd frame */
-#define USB_OTG_DIEPCTL_NAKSTS                  0x00020000U            /*!< NAK status */
-
-#define USB_OTG_DIEPCTL_EPTYP                   0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_DIEPCTL_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_STALL                   0x00200000U            /*!< STALL handshake */
-
-#define USB_OTG_DIEPCTL_TXFNUM                  0x03C00000U            /*!< TxFIFO number */
-#define USB_OTG_DIEPCTL_TXFNUM_0                0x00400000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                0x00800000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                0x01000000U            /*!<Bit 2 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                0x02000000U            /*!<Bit 3 */
-#define USB_OTG_DIEPCTL_CNAK                    0x04000000U            /*!< Clear NAK */
-#define USB_OTG_DIEPCTL_SNAK                    0x08000000U            /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          0x10000000U            /*!< Set DATA0 PID */
-#define USB_OTG_DIEPCTL_SODDFRM                 0x20000000U            /*!< Set odd frame */
-#define USB_OTG_DIEPCTL_EPDIS                   0x40000000U            /*!< Endpoint disable */
-#define USB_OTG_DIEPCTL_EPENA                   0x80000000U            /*!< Endpoint enable */
-
-/********************  Bit definition for USB_OTG_HCCHAR register  ************/
-#define USB_OTG_HCCHAR_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
-
-#define USB_OTG_HCCHAR_EPNUM                   0x00007800U            /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPNUM_1                 0x00001000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_EPNUM_2                 0x00002000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_EPNUM_3                 0x00004000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_EPDIR                   0x00008000U            /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV                   0x00020000U            /*!< Low-speed device */
-
-#define USB_OTG_HCCHAR_EPTYP                   0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_MC                      0x00300000U            /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                    0x00100000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_MC_1                    0x00200000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_DAD                     0x1FC00000U            /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                   0x00400000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_DAD_1                   0x00800000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_DAD_2                   0x01000000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_DAD_3                   0x02000000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_DAD_4                   0x04000000U            /*!<Bit 4 */
-#define USB_OTG_HCCHAR_DAD_5                   0x08000000U            /*!<Bit 5 */
-#define USB_OTG_HCCHAR_DAD_6                   0x10000000U            /*!<Bit 6 */
-#define USB_OTG_HCCHAR_ODDFRM                  0x20000000U            /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS                   0x40000000U            /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA                   0x80000000U            /*!< Channel enable */
-
-/********************  Bit definition for USB_OTG_HCSPLT register  ************/
-
-#define USB_OTG_HCSPLT_PRTADDR                 0x0000007FU            /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_PRTADDR_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_PRTADDR_2               0x00000004U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_PRTADDR_3               0x00000008U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_PRTADDR_4               0x00000010U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_PRTADDR_5               0x00000020U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_PRTADDR_6               0x00000040U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_HUBADDR                 0x00003F80U            /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0               0x00000080U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_HUBADDR_1               0x00000100U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_HUBADDR_2               0x00000200U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_HUBADDR_3               0x00000400U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_HUBADDR_4               0x00000800U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_HUBADDR_5               0x00001000U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_HUBADDR_6               0x00002000U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_XACTPOS                 0x0000C000U            /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0               0x00004000U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_XACTPOS_1               0x00008000U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_COMPLSPLT               0x00010000U            /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN                 0x80000000U            /*!< Split enable */
-
-/********************  Bit definition for USB_OTG_HCINT register  *************/
-#define USB_OTG_HCINT_XFRC                    0x00000001U            /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH                     0x00000002U            /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINT_STALL                   0x00000008U            /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK                     0x00000010U            /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK                     0x00000020U            /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET                    0x00000040U            /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR                   0x00000080U            /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR                   0x00000100U            /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR                   0x00000200U            /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR                   0x00000400U            /*!< Data toggle error */
-
-/********************  Bit definition for USB_OTG_DIEPINT register  ***********/
-#define USB_OTG_DIEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_TOC                     0x00000008U            /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE                  0x00000010U            /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNE                  0x00000040U            /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE                    0x00000080U            /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN              0x00000100U            /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA                     0x00000200U            /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS               0x00000800U            /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR                    0x00001000U            /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK                     0x00002000U            /*!< NAK interrupt */
-
-/********************  Bit definition for USB_OTG_HCINTMSK register  **********/
-#define USB_OTG_HCINTMSK_XFRCM                   0x00000001U            /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM                    0x00000002U            /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM                  0x00000008U            /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM                    0x00000010U            /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM                    0x00000020U            /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET                    0x00000040U            /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM                  0x00000080U            /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM                  0x00000100U            /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM                  0x00000200U            /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM                  0x00000400U            /*!< Data toggle error mask */
-
-/********************  Bit definition for USB_OTG_DIEPTSIZ register  **********/
-
-#define USB_OTG_DIEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT                  0x60000000U            /*!< Packet count */
-/********************  Bit definition for USB_OTG_HCTSIZ register  ************/
-#define USB_OTG_HCTSIZ_XFRSIZ                    0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT                    0x1FF80000U            /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING                    0x80000000U            /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID                      0x60000000U            /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                    0x20000000U            /*!<Bit 0 */
-#define USB_OTG_HCTSIZ_DPID_1                    0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition for USB_OTG_DIEPDMA register  ***********/
-#define USB_OTG_DIEPDMA_DMAADDR                  0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition for USB_OTG_HCDMA register  *************/
-#define USB_OTG_HCDMA_DMAADDR                    0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition for USB_OTG_DTXFSTS register  ***********/
-#define USB_OTG_DTXFSTS_INEPTFSAV                0x0000FFFFU            /*!< IN endpoint TxFIFO space available */
-
-/********************  Bit definition for USB_OTG_DIEPTXF register  ***********/
-#define USB_OTG_DIEPTXF_INEPTXSA                 0x0000FFFFU            /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD                 0xFFFF0000U            /*!< IN endpoint TxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DOEPCTL register  ***********/
-
-#define USB_OTG_DOEPCTL_MPSIZ                     0x000007FFU            /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP                    0x00008000U            /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS                    0x00020000U            /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            0x10000000U            /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM                   0x20000000U            /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP                     0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                   0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DOEPCTL_EPTYP_1                   0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_SNPM                      0x00100000U            /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL                     0x00200000U            /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK                      0x04000000U            /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK                      0x08000000U            /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS                     0x40000000U            /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA                     0x80000000U            /*!< Endpoint enable */
-
-/********************  Bit definition for USB_OTG_DOEPINT register  ***********/
-#define USB_OTG_DOEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_STUP                    0x00000008U            /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS                 0x00000010U            /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_OTEPSPR                 0x00000020U            /*!< Status Phase Received For Control Write */
-#define USB_OTG_DOEPINT_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_NYET                    0x00004000U            /*!< NYET interrupt */
-
-/********************  Bit definition for USB_OTG_DOEPTSIZ register  **********/
-
-#define USB_OTG_DOEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-
-#define USB_OTG_DOEPTSIZ_STUPCNT                 0x60000000U            /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0               0x20000000U            /*!<Bit 0 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1               0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition for PCGCCTL register  *******************/
-#define USB_OTG_PCGCCTL_STOPCLK                 0x00000001U            /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK                 0x00000002U            /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP                 0x00000010U            /*!<Bit 1 */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
- 
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-
-/******************************* CAN Instances ********************************/
-#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
-                                       ((INSTANCE) == CAN2))
-/****************************** DFSDM Instances *******************************/
-#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
-                                                ((INSTANCE) == DFSDM1_Filter1))
-
-#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
-                                                 ((INSTANCE) == DFSDM1_Channel1) || \
-                                                 ((INSTANCE) == DFSDM1_Channel2) || \
-                                                 ((INSTANCE) == DFSDM1_Channel3))
-
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************** DMA Instances *******************************/
-#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
-                                              ((INSTANCE) == DMA1_Stream1) || \
-                                              ((INSTANCE) == DMA1_Stream2) || \
-                                              ((INSTANCE) == DMA1_Stream3) || \
-                                              ((INSTANCE) == DMA1_Stream4) || \
-                                              ((INSTANCE) == DMA1_Stream5) || \
-                                              ((INSTANCE) == DMA1_Stream6) || \
-                                              ((INSTANCE) == DMA1_Stream7) || \
-                                              ((INSTANCE) == DMA2_Stream0) || \
-                                              ((INSTANCE) == DMA2_Stream1) || \
-                                              ((INSTANCE) == DMA2_Stream2) || \
-                                              ((INSTANCE) == DMA2_Stream3) || \
-                                              ((INSTANCE) == DMA2_Stream4) || \
-                                              ((INSTANCE) == DMA2_Stream5) || \
-                                              ((INSTANCE) == DMA2_Stream6) || \
-                                              ((INSTANCE) == DMA2_Stream7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOF) || \
-                                        ((INSTANCE) == GPIOG) || \
-                                        ((INSTANCE) == GPIOH))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2) || \
-                                       ((INSTANCE) == I2C3))
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI1) || \
-                                    ((INSTANCE) == SPI2) || \
-                                    ((INSTANCE) == SPI3) || \
-                                    ((INSTANCE) == SPI4) || \
-                                    ((INSTANCE) == SPI5))
-
-/*************************** I2S Extended Instances ***************************/
-#define IS_I2S_ALL_INSTANCE_EXT(PERIPH)  (((INSTANCE) == SPI2)    || \
-                                          ((INSTANCE) == SPI3)    || \
-                                          ((INSTANCE) == I2S2ext) || \
-                                          ((INSTANCE) == I2S3ext))
-
-/******************************* RNG Instances ********************************/
-#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3) || \
-                                       ((INSTANCE) == SPI4) || \
-                                       ((INSTANCE) == SPI5))
-/*************************** SPI Extended Instances ***************************/
-#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1)    || \
-                                           ((INSTANCE) == SPI2)    || \
-                                           ((INSTANCE) == SPI3)    || \
-                                           ((INSTANCE) == SPI4)    || \
-                                           ((INSTANCE) == SPI5)    || \
-                                           ((INSTANCE) == I2S2ext) || \
-                                           ((INSTANCE) == I2S3ext))
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
-                                   ((INSTANCE) == TIM2)   || \
-                                   ((INSTANCE) == TIM3)   || \
-                                   ((INSTANCE) == TIM4)   || \
-                                   ((INSTANCE) == TIM5)   || \
-                                   ((INSTANCE) == TIM6)   || \
-                                   ((INSTANCE) == TIM7)   || \
-                                   ((INSTANCE) == TIM8)   || \
-                                   ((INSTANCE) == TIM9)   || \
-                                   ((INSTANCE) == TIM10)  || \
-                                   ((INSTANCE) == TIM11)  || \
-                                   ((INSTANCE) == TIM12)  || \
-                                   ((INSTANCE) == TIM13)  || \
-                                   ((INSTANCE) == TIM14))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
-                                         ((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM8)  || \
-                                         ((INSTANCE) == TIM9)  || \
-                                         ((INSTANCE) == TIM10) || \
-                                         ((INSTANCE) == TIM11) || \
-                                         ((INSTANCE) == TIM12) || \
-                                         ((INSTANCE) == TIM13) || \
-                                         ((INSTANCE) == TIM14))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM8) || \
-                                       ((INSTANCE) == TIM9) || \
-                                       ((INSTANCE) == TIM12))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8))
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM8))
-
-/******************** TIM Instances : Advanced-control timers *****************/
-#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                            ((INSTANCE) == TIM8))
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8))
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM6) || \
-                                       ((INSTANCE) == TIM7) || \
-                                       ((INSTANCE) == TIM8))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM8))
-
-/************ TIM Instances : DMA requests generation (COMDE) *****************/
-#define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM8)) 
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                             ((INSTANCE) == TIM2) || \
-                                             ((INSTANCE) == TIM3) || \
-                                             ((INSTANCE) == TIM4) || \
-                                             ((INSTANCE) == TIM5) || \
-                                             ((INSTANCE) == TIM8))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM6) || \
-                                          ((INSTANCE) == TIM7) || \
-                                          ((INSTANCE) == TIM8) || \
-                                          ((INSTANCE) == TIM9) || \
-                                          ((INSTANCE) == TIM12))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8) || \
-                                         ((INSTANCE) == TIM9) || \
-                                         ((INSTANCE) == TIM12))
-
-/********************** TIM Instances : 32 bit Counter ************************/
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
-                                              ((INSTANCE) == TIM5))
-
-/***************** TIM Instances : external trigger input available ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                        ((INSTANCE) == TIM2) || \
-                                        ((INSTANCE) == TIM3) || \
-                                        ((INSTANCE) == TIM4) || \
-                                        ((INSTANCE) == TIM5) || \
-                                        ((INSTANCE) == TIM8))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM11))
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM1) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM5) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM8) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM12) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM13) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM14) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-/************ TIM Instances : complementary output(s) available ***************/
-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
-   ((((INSTANCE) == TIM1) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3)))            \
-    ||                                          \
-    (((INSTANCE) == TIM8) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3))))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3) || \
-                                     ((INSTANCE) == USART6))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == USART6))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3) || \
-                                           ((INSTANCE) == USART6))
-
-/********************* UART Instances : Smart card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3) || \
-                                         ((INSTANCE) == USART6))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == USART6))
-
-/*********************** PCD Instances ****************************************/
-#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
-
-/*********************** HCD Instances ****************************************/
-#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/****************************** QSPI Instances ********************************/
-#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
-
-/***************************** FMPI2C Instances *******************************/
-#define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
-
-/****************************** SDIO Instances ********************************/
-#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
-
-/****************************** USB Instances ********************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
-
-/****************************** USB Exported Constants ************************/
-#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                12U
-#define USB_OTG_FS_MAX_IN_ENDPOINTS                    6U    /* Including EP0 */
-#define USB_OTG_FS_MAX_OUT_ENDPOINTS                   6U    /* Including EP0 */
-#define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32F412Zx_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/cmsis/stm32f415xx.h b/stmhal/cmsis/stm32f415xx.h
deleted file mode 100644
index e05ce5b408..0000000000
--- a/stmhal/cmsis/stm32f415xx.h
+++ /dev/null
@@ -1,7684 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f415xx.h
-  * @author  MCD Application Team
-  * @version V2.5.1
-  * @date    28-June-2016
-  * @brief   CMSIS STM32F415xx Device Peripheral Access Layer Header File.
-  *
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - peripherals registers declarations and bits definition
-  *           - Macros to access peripheral’s registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f415xx
-  * @{
-  */
-    
-#ifndef __STM32F415xx_H
-#define __STM32F415xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-  
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-
-/**
-  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
-  */
-#define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */
-#define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */
-#define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1U       /*!< FPU present                                   */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32F4XX Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-typedef enum
-{
-/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
-  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
-/******  STM32 specific Interrupt Numbers **********************************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
-  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
-  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
-  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
-  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
-  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
-  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
-  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
-  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
-  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
-  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
-  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
-  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
-  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
-  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
-  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
-  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
-  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */    
-  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
-  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
-  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
-  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
-  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
-  FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                             */
-  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
-  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
-  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
-  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
-  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
-  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
-  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
-  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
-  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
-  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
-  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
-  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
-  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
-  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
-  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
-  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
-  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
-  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
-  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
-  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
-  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
-  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
-  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
-  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
-  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
-  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
-  CRYP_IRQn                   = 79,     /*!< CRYP crypto global interrupt                                      */
-  HASH_RNG_IRQn               = 80,     /*!< Hash and Rng global interrupt                                     */
-  FPU_IRQn                    = 81      /*!< FPU global interrupt                                              */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
-#include "system_stm32f4xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */      
-  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
-  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
-  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
-  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
-  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
-  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
-  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
-  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
-  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
-  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
-  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
-  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
-  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
-  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
-  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
-                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
-} ADC_Common_TypeDef;
-
-
-/** 
-  * @brief Controller Area Network TxMailBox 
-  */
-
-typedef struct
-{
-  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
-  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
-  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
-  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
-} CAN_TxMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FIFOMailBox 
-  */
-  
-typedef struct
-{
-  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
-  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
-  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
-  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
-} CAN_FIFOMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FilterRegister 
-  */
-  
-typedef struct
-{
-  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
-  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
-} CAN_FilterRegister_TypeDef;
-
-/** 
-  * @brief Controller Area Network 
-  */
-  
-typedef struct
-{
-  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
-  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
-  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
-  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
-  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
-  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
-  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
-  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
-  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
-  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
-  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
-  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
-  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
-  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
-  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
-  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
-  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
-  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
-  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
-  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
-  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */ 
-  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
-} CAN_TypeDef;
-
-/** 
-  * @brief CRC calculation unit 
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
-  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */
-  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
-  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
-  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
-  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
-  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
-  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
-  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
-  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
-  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
-  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
-  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
-  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
-  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
-  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
-  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
-  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
-  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
-  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
-  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
-  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
-  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
-  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
-  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
-} DMA_Stream_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
-  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
-  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
-  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
-} DMA_TypeDef;
-
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
-  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
-  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
-  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
-  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
-  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-
-typedef struct
-{
-  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */
-  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */
-  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */
-  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */
-  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */
-  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */
-} FLASH_TypeDef;
-
-
-/** 
-  * @brief Flexible Static Memory Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */   
-} FSMC_Bank1_TypeDef; 
-
-/** 
-  * @brief Flexible Static Memory Controller Bank1E
-  */
-  
-typedef struct
-{
-  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
-} FSMC_Bank1E_TypeDef;
-
-/** 
-  * @brief Flexible Static Memory Controller Bank2
-  */
-  
-typedef struct
-{
-  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */
-  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */
-  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */
-  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
-  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */
-  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */
-  uint32_t      RESERVED1;  /*!< Reserved, 0x78                                                            */
-  uint32_t      RESERVED2;  /*!< Reserved, 0x7C                                                            */
-  __IO uint32_t PCR3;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */
-  __IO uint32_t SR3;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */
-  __IO uint32_t PMEM3;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */
-  __IO uint32_t PATT3;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
-  uint32_t      RESERVED3;  /*!< Reserved, 0x90                                                            */
-  __IO uint32_t ECCR3;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */
-} FSMC_Bank2_3_TypeDef;
-
-/** 
-  * @brief Flexible Static Memory Controller Bank4
-  */
-  
-typedef struct
-{
-  __IO uint32_t PCR4;       /*!< PC Card  control register 4,                       Address offset: 0xA0 */
-  __IO uint32_t SR4;        /*!< PC Card  FIFO status and interrupt register 4,     Address offset: 0xA4 */
-  __IO uint32_t PMEM4;      /*!< PC Card  Common memory space timing register 4,    Address offset: 0xA8 */
-  __IO uint32_t PATT4;      /*!< PC Card  Attribute memory space timing register 4, Address offset: 0xAC */
-  __IO uint32_t PIO4;       /*!< PC Card  I/O space timing register 4,              Address offset: 0xB0 */
-} FSMC_Bank4_TypeDef; 
-
-
-/** 
-  * @brief General Purpose I/O
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
-  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
-  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
-  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
-  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
-  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
-  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
-  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/** 
-  * @brief System configuration controller
-  */
-  
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */ 
-  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */
-  __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */
-  __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */
-  __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */
-  __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */
-  __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
-  __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
-  __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
-  __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
-  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
-  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
-  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
-  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
-  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
-  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
-  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
-  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
-  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
-  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
-  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
-  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
-  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
-  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
-  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
-  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
-  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
-  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
-  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
-  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
-  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
-
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-
-typedef struct
-{
-  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
-  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
-  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
-  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
-  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
-  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
-  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */
-  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
-  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */
-  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
-  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */
-  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */
-  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */
-  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */
-  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
-  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */
-  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
-  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
-  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
-  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
-  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
-  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
-  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
-  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
-  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
-  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
-  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
-  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
-  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
-  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
-  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
-  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
-  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
-  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
-  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
-  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
-  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
-} RTC_TypeDef;
-
-
-/** 
-  * @brief SD host Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t POWER;          /*!< SDIO power control register,    Address offset: 0x00 */
-  __IO uint32_t CLKCR;          /*!< SDI clock control register,     Address offset: 0x04 */
-  __IO uint32_t ARG;            /*!< SDIO argument register,         Address offset: 0x08 */
-  __IO uint32_t CMD;            /*!< SDIO command register,          Address offset: 0x0C */
-  __I uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */
-  __I uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */
-  __I uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */
-  __I uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */
-  __I uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */
-  __IO uint32_t DTIMER;         /*!< SDIO data timer register,       Address offset: 0x24 */
-  __IO uint32_t DLEN;           /*!< SDIO data length register,      Address offset: 0x28 */
-  __IO uint32_t DCTRL;          /*!< SDIO data control register,     Address offset: 0x2C */
-  __I uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */
-  __I uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */
-  __IO uint32_t ICR;            /*!< SDIO interrupt clear register,  Address offset: 0x38 */
-  __IO uint32_t MASK;           /*!< SDIO mask register,             Address offset: 0x3C */
-  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
-  __I uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */
-  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
-  __IO uint32_t FIFO;           /*!< SDIO data FIFO register,        Address offset: 0x80 */
-} SDIO_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
-  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
-  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
-  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Crypto Processor
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;         /*!< CRYP control register,                                    Address offset: 0x00 */
-  __IO uint32_t SR;         /*!< CRYP status register,                                     Address offset: 0x04 */
-  __IO uint32_t DR;         /*!< CRYP data input register,                                 Address offset: 0x08 */
-  __IO uint32_t DOUT;       /*!< CRYP data output register,                                Address offset: 0x0C */
-  __IO uint32_t DMACR;      /*!< CRYP DMA control register,                                Address offset: 0x10 */
-  __IO uint32_t IMSCR;      /*!< CRYP interrupt mask set/clear register,                   Address offset: 0x14 */
-  __IO uint32_t RISR;       /*!< CRYP raw interrupt status register,                       Address offset: 0x18 */
-  __IO uint32_t MISR;       /*!< CRYP masked interrupt status register,                    Address offset: 0x1C */
-  __IO uint32_t K0LR;       /*!< CRYP key left  register 0,                                Address offset: 0x20 */
-  __IO uint32_t K0RR;       /*!< CRYP key right register 0,                                Address offset: 0x24 */
-  __IO uint32_t K1LR;       /*!< CRYP key left  register 1,                                Address offset: 0x28 */
-  __IO uint32_t K1RR;       /*!< CRYP key right register 1,                                Address offset: 0x2C */
-  __IO uint32_t K2LR;       /*!< CRYP key left  register 2,                                Address offset: 0x30 */
-  __IO uint32_t K2RR;       /*!< CRYP key right register 2,                                Address offset: 0x34 */
-  __IO uint32_t K3LR;       /*!< CRYP key left  register 3,                                Address offset: 0x38 */
-  __IO uint32_t K3RR;       /*!< CRYP key right register 3,                                Address offset: 0x3C */
-  __IO uint32_t IV0LR;      /*!< CRYP initialization vector left-word  register 0,         Address offset: 0x40 */
-  __IO uint32_t IV0RR;      /*!< CRYP initialization vector right-word register 0,         Address offset: 0x44 */
-  __IO uint32_t IV1LR;      /*!< CRYP initialization vector left-word  register 1,         Address offset: 0x48 */
-  __IO uint32_t IV1RR;      /*!< CRYP initialization vector right-word register 1,         Address offset: 0x4C */
-  __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0,        Address offset: 0x50 */
-  __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1,        Address offset: 0x54 */
-  __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2,        Address offset: 0x58 */
-  __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3,        Address offset: 0x5C */
-  __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4,        Address offset: 0x60 */
-  __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5,        Address offset: 0x64 */
-  __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6,        Address offset: 0x68 */
-  __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7,        Address offset: 0x6C */
-  __IO uint32_t CSGCM0R;    /*!< CRYP GCM/GMAC context swap register 0,                    Address offset: 0x70 */
-  __IO uint32_t CSGCM1R;    /*!< CRYP GCM/GMAC context swap register 1,                    Address offset: 0x74 */
-  __IO uint32_t CSGCM2R;    /*!< CRYP GCM/GMAC context swap register 2,                    Address offset: 0x78 */
-  __IO uint32_t CSGCM3R;    /*!< CRYP GCM/GMAC context swap register 3,                    Address offset: 0x7C */
-  __IO uint32_t CSGCM4R;    /*!< CRYP GCM/GMAC context swap register 4,                    Address offset: 0x80 */
-  __IO uint32_t CSGCM5R;    /*!< CRYP GCM/GMAC context swap register 5,                    Address offset: 0x84 */
-  __IO uint32_t CSGCM6R;    /*!< CRYP GCM/GMAC context swap register 6,                    Address offset: 0x88 */
-  __IO uint32_t CSGCM7R;    /*!< CRYP GCM/GMAC context swap register 7,                    Address offset: 0x8C */
-} CRYP_TypeDef;
-
-/** 
-  * @brief HASH
-  */
-  
-typedef struct 
-{
-  __IO uint32_t CR;               /*!< HASH control register,          Address offset: 0x00        */
-  __IO uint32_t DIN;              /*!< HASH data input register,       Address offset: 0x04        */
-  __IO uint32_t STR;              /*!< HASH start register,            Address offset: 0x08        */
-  __IO uint32_t HR[5];            /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */
-  __IO uint32_t IMR;              /*!< HASH interrupt enable register, Address offset: 0x20        */
-  __IO uint32_t SR;               /*!< HASH status register,           Address offset: 0x24        */
-       uint32_t RESERVED[52];     /*!< Reserved, 0x28-0xF4                                         */
-  __IO uint32_t CSR[54];          /*!< HASH context swap registers,    Address offset: 0x0F8-0x1CC */
-} HASH_TypeDef;
-
-/** 
-  * @brief HASH_DIGEST
-  */
-  
-typedef struct 
-{
-  __IO uint32_t HR[8];     /*!< HASH digest registers,          Address offset: 0x310-0x32C */ 
-} HASH_DIGEST_TypeDef;
-
-/** 
-  * @brief RNG
-  */
-  
-typedef struct 
-{
-  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
-  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
-  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
-} RNG_TypeDef;
-
-
- 
-/** 
-  * @brief __USB_OTG_Core_register
-  */
-typedef struct
-{
-  __IO uint32_t GOTGCTL;              /*!<  USB_OTG Control and Status Register    Address offset : 0x00      */
-  __IO uint32_t GOTGINT;              /*!<  USB_OTG Interrupt Register             Address offset : 0x04      */
-  __IO uint32_t GAHBCFG;              /*!<  Core AHB Configuration Register        Address offset : 0x08      */
-  __IO uint32_t GUSBCFG;              /*!<  Core USB Configuration Register        Address offset : 0x0C      */
-  __IO uint32_t GRSTCTL;              /*!<  Core Reset Register                    Address offset : 0x10      */
-  __IO uint32_t GINTSTS;              /*!<  Core Interrupt Register                Address offset : 0x14      */
-  __IO uint32_t GINTMSK;              /*!<  Core Interrupt Mask Register           Address offset : 0x18      */
-  __IO uint32_t GRXSTSR;              /*!<  Receive Sts Q Read Register            Address offset : 0x1C      */
-  __IO uint32_t GRXSTSP;              /*!<  Receive Sts Q Read & POP Register      Address offset : 0x20      */
-  __IO uint32_t GRXFSIZ;              /* Receive FIFO Size Register                Address offset : 0x24      */
-  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!<  EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28    */
-  __IO uint32_t HNPTXSTS;             /*!<  Non Periodic Tx FIFO/Queue Sts reg     Address offset : 0x2C      */
-  uint32_t Reserved30[2];             /* Reserved                                  Address offset : 0x30      */
-  __IO uint32_t GCCFG;                /*!<  General Purpose IO Register            Address offset : 0x38      */
-  __IO uint32_t CID;                  /*!< User ID Register                          Address offset : 0x3C      */
-  uint32_t  Reserved40[48];           /*!< Reserved                                  Address offset : 0x40-0xFF */
-  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg            Address offset : 0x100 */
-  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */
-}
-USB_OTG_GlobalTypeDef;
-
-
-
-/** 
-  * @brief __device_Registers
-  */
-typedef struct 
-{
-  __IO uint32_t DCFG;         /*!< dev Configuration Register   Address offset : 0x800 */
-  __IO uint32_t DCTL;         /*!< dev Control Register         Address offset : 0x804 */
-  __IO uint32_t DSTS;         /*!< dev Status Register (RO)     Address offset : 0x808 */
-  uint32_t Reserved0C;        /*!< Reserved                     Address offset : 0x80C */
-  __IO uint32_t DIEPMSK;      /* !< dev IN Endpoint Mask        Address offset : 0x810 */
-  __IO uint32_t DOEPMSK;      /*!< dev OUT Endpoint Mask        Address offset : 0x814 */
-  __IO uint32_t DAINT;        /*!< dev All Endpoints Itr Reg    Address offset : 0x818 */
-  __IO uint32_t DAINTMSK;     /*!< dev All Endpoints Itr Mask   Address offset : 0x81C */
-  uint32_t  Reserved20;       /*!< Reserved                     Address offset : 0x820 */
-  uint32_t Reserved9;         /*!< Reserved                     Address offset : 0x824 */
-  __IO uint32_t DVBUSDIS;     /*!< dev VBUS discharge Register  Address offset : 0x828 */
-  __IO uint32_t DVBUSPULSE;   /*!< dev VBUS Pulse Register      Address offset : 0x82C */
-  __IO uint32_t DTHRCTL;      /*!< dev thr                      Address offset : 0x830 */
-  __IO uint32_t DIEPEMPMSK;   /*!< dev empty msk                Address offset : 0x834 */
-  __IO uint32_t DEACHINT;     /*!< dedicated EP interrupt       Address offset : 0x838 */
-  __IO uint32_t DEACHMSK;     /*!< dedicated EP msk             Address offset : 0x83C */  
-  uint32_t Reserved40;        /*!< dedicated EP mask            Address offset : 0x840 */
-  __IO uint32_t DINEP1MSK;    /*!< dedicated EP mask            Address offset : 0x844 */
-  uint32_t  Reserved44[15];   /*!< Reserved                     Address offset : 0x844-0x87C */
-  __IO uint32_t DOUTEP1MSK;   /*!< dedicated EP msk             Address offset : 0x884 */   
-}
-USB_OTG_DeviceTypeDef;
-
-
-/** 
-  * @brief __IN_Endpoint-Specific_Register
-  */
-typedef struct 
-{
-  __IO uint32_t DIEPCTL;        /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h     */
-  uint32_t Reserved04;          /* Reserved                       900h + (ep_num * 20h) + 04h  */
-  __IO uint32_t DIEPINT;        /* dev IN Endpoint Itr Reg     900h + (ep_num * 20h) + 08h     */
-  uint32_t Reserved0C;          /* Reserved                       900h + (ep_num * 20h) + 0Ch  */
-  __IO uint32_t DIEPTSIZ;       /* IN Endpoint Txfer Size   900h + (ep_num * 20h) + 10h        */
-  __IO uint32_t DIEPDMA;        /* IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h  */
-  __IO uint32_t DTXFSTS;        /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h   */
-  uint32_t Reserved18;           /* Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
-}
-USB_OTG_INEndpointTypeDef;
-
-
-/** 
-  * @brief __OUT_Endpoint-Specific_Registers
-  */
-typedef struct 
-{
-  __IO uint32_t DOEPCTL;       /* dev OUT Endpoint Control Reg  B00h + (ep_num * 20h) + 00h*/
-  uint32_t Reserved04;         /* Reserved                      B00h + (ep_num * 20h) + 04h*/
-  __IO uint32_t DOEPINT;       /* dev OUT Endpoint Itr Reg      B00h + (ep_num * 20h) + 08h*/
-  uint32_t Reserved0C;         /* Reserved                      B00h + (ep_num * 20h) + 0Ch*/
-  __IO uint32_t DOEPTSIZ;      /* dev OUT Endpoint Txfer Size   B00h + (ep_num * 20h) + 10h*/
-  __IO uint32_t DOEPDMA;       /* dev OUT Endpoint DMA Address  B00h + (ep_num * 20h) + 14h*/
-  uint32_t Reserved18[2];      /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
-}
-USB_OTG_OUTEndpointTypeDef;
-
-
-/** 
-  * @brief __Host_Mode_Register_Structures
-  */
-typedef struct 
-{
-  __IO uint32_t HCFG;             /* Host Configuration Register    400h*/
-  __IO uint32_t HFIR;             /* Host Frame Interval Register   404h*/
-  __IO uint32_t HFNUM;            /* Host Frame Nbr/Frame Remaining 408h*/
-  uint32_t Reserved40C;           /* Reserved                       40Ch*/
-  __IO uint32_t HPTXSTS;          /* Host Periodic Tx FIFO/ Queue Status 410h*/
-  __IO uint32_t HAINT;            /* Host All Channels Interrupt Register 414h*/
-  __IO uint32_t HAINTMSK;         /* Host All Channels Interrupt Mask 418h*/
-}
-USB_OTG_HostTypeDef;
-
-
-/** 
-  * @brief __Host_Channel_Specific_Registers
-  */
-typedef struct
-{
-  __IO uint32_t HCCHAR;
-  __IO uint32_t HCSPLT;
-  __IO uint32_t HCINT;
-  __IO uint32_t HCINTMSK;
-  __IO uint32_t HCTSIZ;
-  __IO uint32_t HCDMA;
-  uint32_t Reserved[2];
-}
-USB_OTG_HostChannelTypeDef;
-
-    
-/** 
-  * @brief Peripheral_memory_map
-  */
-#define FLASH_BASE            0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region                         */
-#define CCMDATARAM_BASE       0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
-#define SRAM1_BASE            0x20000000U /*!< SRAM1(112 KB) base address in the alias region                             */
-#define SRAM2_BASE            0x2001C000U /*!< SRAM2(16 KB) base address in the alias region                              */
-#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region                                */
-#define BKPSRAM_BASE          0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region                         */
-#define FSMC_R_BASE           0xA0000000U /*!< FSMC registers base address                                                */
-#define SRAM1_BB_BASE         0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region                             */
-#define SRAM2_BB_BASE         0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region                              */
-#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region                                */
-#define BKPSRAM_BB_BASE       0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region                         */
-#define FLASH_END             0x080FFFFFU /*!< FLASH end address */
-#define CCMDATARAM_END        0x1000FFFFU /*!< CCM data RAM end address */
-
-/* Legacy defines */
-#define SRAM_BASE             SRAM1_BASE
-#define SRAM_BB_BASE          SRAM1_BB_BASE
-
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000U)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)
-#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800U)
-#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00U)
-#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000U)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)
-#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400U)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)
-#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000U)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800U)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00U)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x5000U)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)
-#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)
-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)
-#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800U)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)
-
-/*!< APB2 peripherals */
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000U)
-#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400U)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x1000U)
-#define USART6_BASE           (APB2PERIPH_BASE + 0x1400U)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000U)
-#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100U)
-#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200U)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x2300U)
-#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00U)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800U)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00U)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000U)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400U)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800U)
-
-/*!< AHB1 peripherals */
-#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000U)
-#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400U)
-#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800U)
-#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00U)
-#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000U)
-#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400U)
-#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800U)
-#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00U)
-#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000U)
-#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)
-#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800U)
-#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00U)
-#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000U)
-#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010U)
-#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028U)
-#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040U)
-#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058U)
-#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070U)
-#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088U)
-#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0U)
-#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8U)
-#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400U)
-#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010U)
-#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028U)
-#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040U)
-#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058U)
-#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070U)
-#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088U)
-#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0U)
-#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)
-
-/*!< AHB2 peripherals */
-#define CRYP_BASE             (AHB2PERIPH_BASE + 0x60000U)
-#define HASH_BASE             (AHB2PERIPH_BASE + 0x60400U)
-#define HASH_DIGEST_BASE      (AHB2PERIPH_BASE + 0x60710U)
-#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800U)
-
-/*!< FSMC Bankx registers base address */
-#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000U)
-#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104U)
-#define FSMC_Bank2_3_R_BASE   (FSMC_R_BASE + 0x0060U)
-#define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0U)
-
-/* Debug MCU registers base address */
-#define DBGMCU_BASE           0xE0042000U
-
-/*!< USB registers base address */
-#define USB_OTG_HS_PERIPH_BASE               0x40040000U
-#define USB_OTG_FS_PERIPH_BASE               0x50000000U
-
-#define USB_OTG_GLOBAL_BASE                  0x000U
-#define USB_OTG_DEVICE_BASE                  0x800U
-#define USB_OTG_IN_ENDPOINT_BASE             0x900U
-#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U
-#define USB_OTG_EP_REG_SIZE                  0x20U
-#define USB_OTG_HOST_BASE                    0x400U
-#define USB_OTG_HOST_PORT_BASE               0x440U
-#define USB_OTG_HOST_CHANNEL_BASE            0x500U
-#define USB_OTG_HOST_CHANNEL_SIZE            0x20U
-#define USB_OTG_PCGCCTL_BASE                 0xE00U
-#define USB_OTG_FIFO_BASE                    0x1000U
-#define USB_OTG_FIFO_SIZE                    0x1000U
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
-#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
-#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define UART4               ((USART_TypeDef *) UART4_BASE)
-#define UART5               ((USART_TypeDef *) UART5_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
-#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
-#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
-#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define USART6              ((USART_TypeDef *) USART6_BASE)
-#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
-#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
-#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE) 
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
-#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
-#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
-#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
-#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
-#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
-#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
-#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
-#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
-#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
-#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
-#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
-#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
-#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
-#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)  
-#define CRYP                ((CRYP_TypeDef *) CRYP_BASE)
-#define HASH                ((HASH_TypeDef *) HASH_BASE)
-#define HASH_DIGEST         ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
-#define RNG                 ((RNG_TypeDef *) RNG_BASE)
-#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
-#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
-#define FSMC_Bank2_3        ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)
-#define FSMC_Bank4          ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
-
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
-#define USB_OTG_HS          ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers_Bits_Definition               */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Analog to Digital Converter                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          0x00000001U       /*!<Analog watchdog flag */
-#define  ADC_SR_EOC                          0x00000002U       /*!<End of conversion */
-#define  ADC_SR_JEOC                         0x00000004U       /*!<Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        0x00000008U       /*!<Injected channel Start flag */
-#define  ADC_SR_STRT                         0x00000010U       /*!<Regular channel Start flag */
-#define  ADC_SR_OVR                          0x00000020U       /*!<Overrun flag */
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
-#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels */
-#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels */
-#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution) */
-#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
-  
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion */
-#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode */
-#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC) */
-#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection */
-#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment */
-#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      0xFFFFU            /*!<Injected data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag */
-#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion */
-#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag */
-#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag */
-#define  ADC_CSR_OVR1                        0x00000020U        /*!<ADC1 DMA overrun  flag */
-#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag */
-#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion */
-#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag */
-#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag */
-#define  ADC_CSR_OVR2                        0x00002000U        /*!<ADC2 DMA overrun  flag */
-#define  ADC_CSR_AWD3                        0x00010000U        /*!<ADC3 Analog watchdog flag */
-#define  ADC_CSR_EOC3                        0x00020000U        /*!<ADC3 End of conversion */
-#define  ADC_CSR_JEOC3                       0x00040000U        /*!<ADC3 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT3                      0x00080000U        /*!<ADC3 Injected channel Start flag */
-#define  ADC_CSR_STRT3                       0x00100000U        /*!<ADC3 Regular channel Start flag */
-#define  ADC_CSR_OVR3                        0x00200000U        /*!<ADC3 DMA overrun  flag */
-
-/* Legacy defines */
-#define  ADC_CSR_DOVR1                        ADC_CSR_OVR1
-#define  ADC_CSR_DOVR2                        ADC_CSR_OVR2
-#define  ADC_CSR_DOVR3                        ADC_CSR_OVR3
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
-#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
-#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
-#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
-#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
-
-/*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                      0x0000FFFFU         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                      0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Controller Area Network                            */
-/*                                                                            */
-/******************************************************************************/
-/*!<CAN control and status registers */
-/*******************  Bit definition for CAN_MCR register  ********************/
-#define  CAN_MCR_INRQ                        0x00000001U        /*!<Initialization Request */
-#define  CAN_MCR_SLEEP                       0x00000002U        /*!<Sleep Mode Request */
-#define  CAN_MCR_TXFP                        0x00000004U        /*!<Transmit FIFO Priority */
-#define  CAN_MCR_RFLM                        0x00000008U        /*!<Receive FIFO Locked Mode */
-#define  CAN_MCR_NART                        0x00000010U        /*!<No Automatic Retransmission */
-#define  CAN_MCR_AWUM                        0x00000020U        /*!<Automatic Wakeup Mode */
-#define  CAN_MCR_ABOM                        0x00000040U        /*!<Automatic Bus-Off Management */
-#define  CAN_MCR_TTCM                        0x00000080U        /*!<Time Triggered Communication Mode */
-#define  CAN_MCR_RESET                       0x00008000U        /*!<bxCAN software master reset */
-#define  CAN_MCR_DBF                         0x00010000U        /*!<bxCAN Debug freeze */
-/*******************  Bit definition for CAN_MSR register  ********************/
-#define  CAN_MSR_INAK                        0x0001U            /*!<Initialization Acknowledge */
-#define  CAN_MSR_SLAK                        0x0002U            /*!<Sleep Acknowledge */
-#define  CAN_MSR_ERRI                        0x0004U            /*!<Error Interrupt */
-#define  CAN_MSR_WKUI                        0x0008U            /*!<Wakeup Interrupt */
-#define  CAN_MSR_SLAKI                       0x0010U            /*!<Sleep Acknowledge Interrupt */
-#define  CAN_MSR_TXM                         0x0100U            /*!<Transmit Mode */
-#define  CAN_MSR_RXM                         0x0200U            /*!<Receive Mode */
-#define  CAN_MSR_SAMP                        0x0400U            /*!<Last Sample Point */
-#define  CAN_MSR_RX                          0x0800U            /*!<CAN Rx Signal */
-
-/*******************  Bit definition for CAN_TSR register  ********************/
-#define  CAN_TSR_RQCP0                       0x00000001U        /*!<Request Completed Mailbox0 */
-#define  CAN_TSR_TXOK0                       0x00000002U        /*!<Transmission OK of Mailbox0 */
-#define  CAN_TSR_ALST0                       0x00000004U        /*!<Arbitration Lost for Mailbox0 */
-#define  CAN_TSR_TERR0                       0x00000008U        /*!<Transmission Error of Mailbox0 */
-#define  CAN_TSR_ABRQ0                       0x00000080U        /*!<Abort Request for Mailbox0 */
-#define  CAN_TSR_RQCP1                       0x00000100U        /*!<Request Completed Mailbox1 */
-#define  CAN_TSR_TXOK1                       0x00000200U        /*!<Transmission OK of Mailbox1 */
-#define  CAN_TSR_ALST1                       0x00000400U        /*!<Arbitration Lost for Mailbox1 */
-#define  CAN_TSR_TERR1                       0x00000800U        /*!<Transmission Error of Mailbox1 */
-#define  CAN_TSR_ABRQ1                       0x00008000U        /*!<Abort Request for Mailbox 1 */
-#define  CAN_TSR_RQCP2                       0x00010000U        /*!<Request Completed Mailbox2 */
-#define  CAN_TSR_TXOK2                       0x00020000U        /*!<Transmission OK of Mailbox 2 */
-#define  CAN_TSR_ALST2                       0x00040000U        /*!<Arbitration Lost for mailbox 2 */
-#define  CAN_TSR_TERR2                       0x00080000U        /*!<Transmission Error of Mailbox 2 */
-#define  CAN_TSR_ABRQ2                       0x00800000U        /*!<Abort Request for Mailbox 2 */
-#define  CAN_TSR_CODE                        0x03000000U        /*!<Mailbox Code */
-
-#define  CAN_TSR_TME                         0x1C000000U        /*!<TME[2:0] bits */
-#define  CAN_TSR_TME0                        0x04000000U        /*!<Transmit Mailbox 0 Empty */
-#define  CAN_TSR_TME1                        0x08000000U        /*!<Transmit Mailbox 1 Empty */
-#define  CAN_TSR_TME2                        0x10000000U        /*!<Transmit Mailbox 2 Empty */
-
-#define  CAN_TSR_LOW                         0xE0000000U        /*!<LOW[2:0] bits */
-#define  CAN_TSR_LOW0                        0x20000000U        /*!<Lowest Priority Flag for Mailbox 0 */
-#define  CAN_TSR_LOW1                        0x40000000U        /*!<Lowest Priority Flag for Mailbox 1 */
-#define  CAN_TSR_LOW2                        0x80000000U        /*!<Lowest Priority Flag for Mailbox 2 */
-
-/*******************  Bit definition for CAN_RF0R register  *******************/
-#define  CAN_RF0R_FMP0                       0x03U               /*!<FIFO 0 Message Pending */
-#define  CAN_RF0R_FULL0                      0x08U               /*!<FIFO 0 Full */
-#define  CAN_RF0R_FOVR0                      0x10U               /*!<FIFO 0 Overrun */
-#define  CAN_RF0R_RFOM0                      0x20U               /*!<Release FIFO 0 Output Mailbox */
-
-/*******************  Bit definition for CAN_RF1R register  *******************/
-#define  CAN_RF1R_FMP1                       0x03U               /*!<FIFO 1 Message Pending */
-#define  CAN_RF1R_FULL1                      0x08U               /*!<FIFO 1 Full */
-#define  CAN_RF1R_FOVR1                      0x10U               /*!<FIFO 1 Overrun */
-#define  CAN_RF1R_RFOM1                      0x20U               /*!<Release FIFO 1 Output Mailbox */
-
-/********************  Bit definition for CAN_IER register  *******************/
-#define  CAN_IER_TMEIE                       0x00000001U        /*!<Transmit Mailbox Empty Interrupt Enable */
-#define  CAN_IER_FMPIE0                      0x00000002U        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE0                       0x00000004U        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE0                      0x00000008U        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_FMPIE1                      0x00000010U        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE1                       0x00000020U        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE1                      0x00000040U        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error Warning Interrupt Enable */
-#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error Passive Interrupt Enable */
-#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-Off Interrupt Enable */
-#define  CAN_IER_LECIE                       0x00000800U        /*!<Last Error Code Interrupt Enable */
-#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error Interrupt Enable */
-#define  CAN_IER_WKUIE                       0x00010000U        /*!<Wakeup Interrupt Enable */
-#define  CAN_IER_SLKIE                       0x00020000U        /*!<Sleep Interrupt Enable */
-#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error warning interrupt enable */
-#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error passive interrupt enable */
-#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-off interrupt enable */
-#define  CAN_IER_LECIE                       0x00000800U        /*!<Last error code interrupt enable */
-#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error interrupt enable */
-
-
-/********************  Bit definition for CAN_ESR register  *******************/
-#define  CAN_ESR_EWGF                        0x00000001U        /*!<Error Warning Flag */
-#define  CAN_ESR_EPVF                        0x00000002U        /*!<Error Passive Flag */
-#define  CAN_ESR_BOFF                        0x00000004U        /*!<Bus-Off Flag */
-
-#define  CAN_ESR_LEC                         0x00000070U        /*!<LEC[2:0] bits (Last Error Code) */
-#define  CAN_ESR_LEC_0                       0x00000010U        /*!<Bit 0 */
-#define  CAN_ESR_LEC_1                       0x00000020U        /*!<Bit 1 */
-#define  CAN_ESR_LEC_2                       0x00000040U        /*!<Bit 2 */
-
-#define  CAN_ESR_TEC                         0x00FF0000U        /*!<Least significant byte of the 9-bit Transmit Error Counter */
-#define  CAN_ESR_REC                         0xFF000000U        /*!<Receive Error Counter */
-
-/*******************  Bit definition for CAN_BTR register  ********************/
-#define  CAN_BTR_BRP                         0x000003FFU        /*!<Baud Rate Prescaler */
-#define  CAN_BTR_TS1                         0x000F0000U        /*!<Time Segment 1 */
-#define  CAN_BTR_TS1_0                       0x00010000U        /*!<Bit 0 */
-#define  CAN_BTR_TS1_1                       0x00020000U        /*!<Bit 1 */
-#define  CAN_BTR_TS1_2                       0x00040000U        /*!<Bit 2 */
-#define  CAN_BTR_TS1_3                       0x00080000U        /*!<Bit 3 */
-#define  CAN_BTR_TS2                         0x00700000U        /*!<Time Segment 2 */
-#define  CAN_BTR_TS2_0                       0x00100000U        /*!<Bit 0 */
-#define  CAN_BTR_TS2_1                       0x00200000U        /*!<Bit 1 */
-#define  CAN_BTR_TS2_2                       0x00400000U        /*!<Bit 2 */
-#define  CAN_BTR_SJW                         0x03000000U        /*!<Resynchronization Jump Width */
-#define  CAN_BTR_SJW_0                       0x01000000U        /*!<Bit 0 */
-#define  CAN_BTR_SJW_1                       0x02000000U        /*!<Bit 1 */
-#define  CAN_BTR_LBKM                        0x40000000U        /*!<Loop Back Mode (Debug) */
-#define  CAN_BTR_SILM                        0x80000000U        /*!<Silent Mode */
-
-
-/*!<Mailbox registers */
-/******************  Bit definition for CAN_TI0R register  ********************/
-#define  CAN_TI0R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI0R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_TI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/******************  Bit definition for CAN_TDT0R register  *******************/
-#define  CAN_TDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT0R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/******************  Bit definition for CAN_TDL0R register  *******************/
-#define  CAN_TDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/******************  Bit definition for CAN_TDH0R register  *******************/
-#define  CAN_TDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI1R register  *******************/
-#define  CAN_TI1R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI1R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI1R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_TI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT1R register  ******************/
-#define  CAN_TDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT1R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL1R register  ******************/
-#define  CAN_TDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH1R register  ******************/
-#define  CAN_TDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI2R register  *******************/
-#define  CAN_TI2R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI2R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI2R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI2R_EXID                       0x001FFFF8U        /*!<Extended identifier */
-#define  CAN_TI2R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT2R register  ******************/  
-#define  CAN_TDT2R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT2R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT2R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL2R register  ******************/
-#define  CAN_TDL2R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL2R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL2R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL2R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH2R register  ******************/
-#define  CAN_TDH2R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH2R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH2R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH2R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI0R register  *******************/
-#define  CAN_RI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_RI0R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_RI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_RI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT0R register  ******************/
-#define  CAN_RDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_RDT0R_FMI                       0x0000FF00U        /*!<Filter Match Index */
-#define  CAN_RDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL0R register  ******************/
-#define  CAN_RDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_RDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_RDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_RDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH0R register  ******************/
-#define  CAN_RDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_RDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_RDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_RDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI1R register  *******************/
-#define  CAN_RI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_RI1R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_RI1R_EXID                       0x001FFFF8U        /*!<Extended identifier */
-#define  CAN_RI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT1R register  ******************/
-#define  CAN_RDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_RDT1R_FMI                       0x0000FF00U        /*!<Filter Match Index */
-#define  CAN_RDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL1R register  ******************/
-#define  CAN_RDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_RDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_RDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_RDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH1R register  ******************/
-#define  CAN_RDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_RDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_RDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_RDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*!<CAN filter registers */
-/*******************  Bit definition for CAN_FMR register  ********************/
-#define  CAN_FMR_FINIT                       0x01U               /*!<Filter Init Mode */
-#define  CAN_FMR_CAN2SB                      0x00003F00U        /*!<CAN2 start bank */
-
-/*******************  Bit definition for CAN_FM1R register  *******************/
-#define  CAN_FM1R_FBM                        0x0FFFFFFFU        /*!<Filter Mode */
-#define  CAN_FM1R_FBM0                       0x00000001U        /*!<Filter Init Mode bit 0 */
-#define  CAN_FM1R_FBM1                       0x00000002U        /*!<Filter Init Mode bit 1 */
-#define  CAN_FM1R_FBM2                       0x00000004U        /*!<Filter Init Mode bit 2 */
-#define  CAN_FM1R_FBM3                       0x00000008U        /*!<Filter Init Mode bit 3 */
-#define  CAN_FM1R_FBM4                       0x00000010U        /*!<Filter Init Mode bit 4 */
-#define  CAN_FM1R_FBM5                       0x00000020U        /*!<Filter Init Mode bit 5 */
-#define  CAN_FM1R_FBM6                       0x00000040U        /*!<Filter Init Mode bit 6 */
-#define  CAN_FM1R_FBM7                       0x00000080U        /*!<Filter Init Mode bit 7 */
-#define  CAN_FM1R_FBM8                       0x00000100U        /*!<Filter Init Mode bit 8 */
-#define  CAN_FM1R_FBM9                       0x00000200U        /*!<Filter Init Mode bit 9 */
-#define  CAN_FM1R_FBM10                      0x00000400U        /*!<Filter Init Mode bit 10 */
-#define  CAN_FM1R_FBM11                      0x00000800U        /*!<Filter Init Mode bit 11 */
-#define  CAN_FM1R_FBM12                      0x00001000U        /*!<Filter Init Mode bit 12 */
-#define  CAN_FM1R_FBM13                      0x00002000U        /*!<Filter Init Mode bit 13 */
-#define  CAN_FM1R_FBM14                      0x00004000U        /*!<Filter Init Mode bit 14 */
-#define  CAN_FM1R_FBM15                      0x00008000U        /*!<Filter Init Mode bit 15 */
-#define  CAN_FM1R_FBM16                      0x00010000U        /*!<Filter Init Mode bit 16 */
-#define  CAN_FM1R_FBM17                      0x00020000U        /*!<Filter Init Mode bit 17 */
-#define  CAN_FM1R_FBM18                      0x00040000U        /*!<Filter Init Mode bit 18 */
-#define  CAN_FM1R_FBM19                      0x00080000U        /*!<Filter Init Mode bit 19 */
-#define  CAN_FM1R_FBM20                      0x00100000U        /*!<Filter Init Mode bit 20 */
-#define  CAN_FM1R_FBM21                      0x00200000U        /*!<Filter Init Mode bit 21 */
-#define  CAN_FM1R_FBM22                      0x00400000U        /*!<Filter Init Mode bit 22 */
-#define  CAN_FM1R_FBM23                      0x00800000U        /*!<Filter Init Mode bit 23 */
-#define  CAN_FM1R_FBM24                      0x01000000U        /*!<Filter Init Mode bit 24 */
-#define  CAN_FM1R_FBM25                      0x02000000U        /*!<Filter Init Mode bit 25 */
-#define  CAN_FM1R_FBM26                      0x04000000U        /*!<Filter Init Mode bit 26 */
-#define  CAN_FM1R_FBM27                      0x08000000U        /*!<Filter Init Mode bit 27 */
-
-/*******************  Bit definition for CAN_FS1R register  *******************/
-#define  CAN_FS1R_FSC                        0x0FFFFFFFU        /*!<Filter Scale Configuration */
-#define  CAN_FS1R_FSC0                       0x00000001U        /*!<Filter Scale Configuration bit 0 */
-#define  CAN_FS1R_FSC1                       0x00000002U        /*!<Filter Scale Configuration bit 1 */
-#define  CAN_FS1R_FSC2                       0x00000004U        /*!<Filter Scale Configuration bit 2 */
-#define  CAN_FS1R_FSC3                       0x00000008U        /*!<Filter Scale Configuration bit 3 */
-#define  CAN_FS1R_FSC4                       0x00000010U        /*!<Filter Scale Configuration bit 4 */
-#define  CAN_FS1R_FSC5                       0x00000020U        /*!<Filter Scale Configuration bit 5 */
-#define  CAN_FS1R_FSC6                       0x00000040U        /*!<Filter Scale Configuration bit 6 */
-#define  CAN_FS1R_FSC7                       0x00000080U        /*!<Filter Scale Configuration bit 7 */
-#define  CAN_FS1R_FSC8                       0x00000100U        /*!<Filter Scale Configuration bit 8 */
-#define  CAN_FS1R_FSC9                       0x00000200U        /*!<Filter Scale Configuration bit 9 */
-#define  CAN_FS1R_FSC10                      0x00000400U        /*!<Filter Scale Configuration bit 10 */
-#define  CAN_FS1R_FSC11                      0x00000800U        /*!<Filter Scale Configuration bit 11 */
-#define  CAN_FS1R_FSC12                      0x00001000U        /*!<Filter Scale Configuration bit 12 */
-#define  CAN_FS1R_FSC13                      0x00002000U        /*!<Filter Scale Configuration bit 13 */
-#define  CAN_FS1R_FSC14                      0x00004000U        /*!<Filter Scale Configuration bit 14 */
-#define  CAN_FS1R_FSC15                      0x00008000U        /*!<Filter Scale Configuration bit 15 */
-#define  CAN_FS1R_FSC16                      0x00010000U        /*!<Filter Scale Configuration bit 16 */
-#define  CAN_FS1R_FSC17                      0x00020000U        /*!<Filter Scale Configuration bit 17 */
-#define  CAN_FS1R_FSC18                      0x00040000U        /*!<Filter Scale Configuration bit 18 */
-#define  CAN_FS1R_FSC19                      0x00080000U        /*!<Filter Scale Configuration bit 19 */
-#define  CAN_FS1R_FSC20                      0x00100000U        /*!<Filter Scale Configuration bit 20 */
-#define  CAN_FS1R_FSC21                      0x00200000U        /*!<Filter Scale Configuration bit 21 */
-#define  CAN_FS1R_FSC22                      0x00400000U        /*!<Filter Scale Configuration bit 22 */
-#define  CAN_FS1R_FSC23                      0x00800000U        /*!<Filter Scale Configuration bit 23 */
-#define  CAN_FS1R_FSC24                      0x01000000U        /*!<Filter Scale Configuration bit 24 */
-#define  CAN_FS1R_FSC25                      0x02000000U        /*!<Filter Scale Configuration bit 25 */
-#define  CAN_FS1R_FSC26                      0x04000000U        /*!<Filter Scale Configuration bit 26 */
-#define  CAN_FS1R_FSC27                      0x08000000U        /*!<Filter Scale Configuration bit 27 */
-
-/******************  Bit definition for CAN_FFA1R register  *******************/
-#define  CAN_FFA1R_FFA                        0x0FFFFFFFU        /*!<Filter FIFO Assignment */
-#define  CAN_FFA1R_FFA0                       0x00000001U        /*!<Filter FIFO Assignment bit 0 */
-#define  CAN_FFA1R_FFA1                       0x00000002U        /*!<Filter FIFO Assignment bit 1 */
-#define  CAN_FFA1R_FFA2                       0x00000004U        /*!<Filter FIFO Assignment bit 2 */
-#define  CAN_FFA1R_FFA3                       0x00000008U        /*!<Filter FIFO Assignment bit 3 */
-#define  CAN_FFA1R_FFA4                       0x00000010U        /*!<Filter FIFO Assignment bit 4 */
-#define  CAN_FFA1R_FFA5                       0x00000020U        /*!<Filter FIFO Assignment bit 5 */
-#define  CAN_FFA1R_FFA6                       0x00000040U        /*!<Filter FIFO Assignment bit 6 */
-#define  CAN_FFA1R_FFA7                       0x00000080U        /*!<Filter FIFO Assignment bit 7 */
-#define  CAN_FFA1R_FFA8                       0x00000100U        /*!<Filter FIFO Assignment bit 8 */
-#define  CAN_FFA1R_FFA9                       0x00000200U        /*!<Filter FIFO Assignment bit 9 */
-#define  CAN_FFA1R_FFA10                      0x00000400U        /*!<Filter FIFO Assignment bit 10 */
-#define  CAN_FFA1R_FFA11                      0x00000800U        /*!<Filter FIFO Assignment bit 11 */
-#define  CAN_FFA1R_FFA12                      0x00001000U        /*!<Filter FIFO Assignment bit 12 */
-#define  CAN_FFA1R_FFA13                      0x00002000U        /*!<Filter FIFO Assignment bit 13 */
-#define  CAN_FFA1R_FFA14                      0x00004000U        /*!<Filter FIFO Assignment bit 14 */
-#define  CAN_FFA1R_FFA15                      0x00008000U        /*!<Filter FIFO Assignment bit 15 */
-#define  CAN_FFA1R_FFA16                      0x00010000U        /*!<Filter FIFO Assignment bit 16 */
-#define  CAN_FFA1R_FFA17                      0x00020000U        /*!<Filter FIFO Assignment bit 17 */
-#define  CAN_FFA1R_FFA18                      0x00040000U        /*!<Filter FIFO Assignment bit 18 */
-#define  CAN_FFA1R_FFA19                      0x00080000U        /*!<Filter FIFO Assignment bit 19 */
-#define  CAN_FFA1R_FFA20                      0x00100000U        /*!<Filter FIFO Assignment bit 20 */
-#define  CAN_FFA1R_FFA21                      0x00200000U        /*!<Filter FIFO Assignment bit 21 */
-#define  CAN_FFA1R_FFA22                      0x00400000U        /*!<Filter FIFO Assignment bit 22 */
-#define  CAN_FFA1R_FFA23                      0x00800000U        /*!<Filter FIFO Assignment bit 23 */
-#define  CAN_FFA1R_FFA24                      0x01000000U        /*!<Filter FIFO Assignment bit 24 */
-#define  CAN_FFA1R_FFA25                      0x02000000U        /*!<Filter FIFO Assignment bit 25 */
-#define  CAN_FFA1R_FFA26                      0x04000000U        /*!<Filter FIFO Assignment bit 26 */
-#define  CAN_FFA1R_FFA27                      0x08000000U        /*!<Filter FIFO Assignment bit 27 */
-
-/*******************  Bit definition for CAN_FA1R register  *******************/
-#define  CAN_FA1R_FACT                        0x0FFFFFFFU        /*!<Filter Active */
-#define  CAN_FA1R_FACT0                       0x00000001U        /*!<Filter Active bit 0 */
-#define  CAN_FA1R_FACT1                       0x00000002U        /*!<Filter Active bit 1 */
-#define  CAN_FA1R_FACT2                       0x00000004U        /*!<Filter Active bit 2 */
-#define  CAN_FA1R_FACT3                       0x00000008U        /*!<Filter Active bit 3 */
-#define  CAN_FA1R_FACT4                       0x00000010U        /*!<Filter Active bit 4 */
-#define  CAN_FA1R_FACT5                       0x00000020U        /*!<Filter Active bit 5 */
-#define  CAN_FA1R_FACT6                       0x00000040U        /*!<Filter Active bit 6 */
-#define  CAN_FA1R_FACT7                       0x00000080U        /*!<Filter Active bit 7 */
-#define  CAN_FA1R_FACT8                       0x00000100U        /*!<Filter Active bit 8 */
-#define  CAN_FA1R_FACT9                       0x00000200U        /*!<Filter Active bit 9 */
-#define  CAN_FA1R_FACT10                      0x00000400U        /*!<Filter Active bit 10 */
-#define  CAN_FA1R_FACT11                      0x00000800U        /*!<Filter Active bit 11 */
-#define  CAN_FA1R_FACT12                      0x00001000U        /*!<Filter Active bit 12 */
-#define  CAN_FA1R_FACT13                      0x00002000U        /*!<Filter Active bit 13 */
-#define  CAN_FA1R_FACT14                      0x00004000U        /*!<Filter Active bit 14 */
-#define  CAN_FA1R_FACT15                      0x00008000U        /*!<Filter Active bit 15 */
-#define  CAN_FA1R_FACT16                      0x00010000U        /*!<Filter Active bit 16 */
-#define  CAN_FA1R_FACT17                      0x00020000U        /*!<Filter Active bit 17 */
-#define  CAN_FA1R_FACT18                      0x00040000U        /*!<Filter Active bit 18 */
-#define  CAN_FA1R_FACT19                      0x00080000U        /*!<Filter Active bit 19 */
-#define  CAN_FA1R_FACT20                      0x00100000U        /*!<Filter Active bit 20 */
-#define  CAN_FA1R_FACT21                      0x00200000U        /*!<Filter Active bit 21 */
-#define  CAN_FA1R_FACT22                      0x00400000U        /*!<Filter Active bit 22 */
-#define  CAN_FA1R_FACT23                      0x00800000U        /*!<Filter Active bit 23 */
-#define  CAN_FA1R_FACT24                      0x01000000U        /*!<Filter Active bit 24 */
-#define  CAN_FA1R_FACT25                      0x02000000U        /*!<Filter Active bit 25 */
-#define  CAN_FA1R_FACT26                      0x04000000U        /*!<Filter Active bit 26 */
-#define  CAN_FA1R_FACT27                      0x08000000U        /*!<Filter Active bit 27 */
-
-/*******************  Bit definition for CAN_F0R1 register  *******************/
-#define  CAN_F0R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F0R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F0R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F0R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F0R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F0R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F0R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F0R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F0R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F0R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F0R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F0R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F0R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F0R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F0R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F0R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F0R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F0R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F0R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F0R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F0R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F0R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F0R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F0R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F0R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F0R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F0R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F0R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F0R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F0R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F0R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F0R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R1 register  *******************/
-#define  CAN_F1R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F1R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F1R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F1R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F1R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F1R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F1R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F1R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F1R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F1R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F1R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F1R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F1R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F1R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F1R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F1R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F1R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F1R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F1R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F1R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F1R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F1R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F1R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F1R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F1R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F1R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F1R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F1R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F1R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F1R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F1R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F1R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R1 register  *******************/
-#define  CAN_F2R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F2R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F2R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F2R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F2R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F2R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F2R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F2R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F2R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F2R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F2R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F2R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F2R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F2R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F2R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F2R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F2R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F2R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F2R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F2R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F2R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F2R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F2R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F2R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F2R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F2R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F2R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F2R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F2R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F2R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F2R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F2R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R1 register  *******************/
-#define  CAN_F3R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F3R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F3R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F3R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F3R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F3R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F3R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F3R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F3R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F3R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F3R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F3R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F3R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F3R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F3R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F3R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F3R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F3R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F3R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F3R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F3R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F3R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F3R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F3R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F3R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F3R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F3R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F3R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F3R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F3R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F3R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F3R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R1 register  *******************/
-#define  CAN_F4R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F4R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F4R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F4R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F4R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F4R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F4R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F4R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F4R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F4R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F4R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F4R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F4R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F4R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F4R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F4R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F4R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F4R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F4R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F4R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F4R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F4R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F4R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F4R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F4R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F4R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F4R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F4R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F4R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F4R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F4R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F4R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R1 register  *******************/
-#define  CAN_F5R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F5R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F5R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F5R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F5R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F5R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F5R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F5R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F5R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F5R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F5R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F5R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F5R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F5R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F5R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F5R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F5R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F5R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F5R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F5R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F5R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F5R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F5R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F5R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F5R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F5R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F5R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F5R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F5R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F5R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F5R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F5R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R1 register  *******************/
-#define  CAN_F6R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F6R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F6R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F6R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F6R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F6R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F6R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F6R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F6R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F6R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F6R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F6R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F6R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F6R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F6R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F6R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F6R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F6R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F6R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F6R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F6R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F6R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F6R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F6R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F6R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F6R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F6R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F6R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F6R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F6R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F6R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F6R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R1 register  *******************/
-#define  CAN_F7R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F7R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F7R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F7R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F7R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F7R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F7R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F7R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F7R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F7R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F7R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F7R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F7R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F7R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F7R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F7R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F7R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F7R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F7R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F7R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F7R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F7R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F7R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F7R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F7R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F7R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F7R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F7R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F7R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F7R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F7R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F7R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R1 register  *******************/
-#define  CAN_F8R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F8R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F8R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F8R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F8R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F8R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F8R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F8R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F8R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F8R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F8R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F8R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F8R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F8R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F8R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F8R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F8R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F8R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F8R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F8R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F8R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F8R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F8R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F8R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F8R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F8R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F8R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F8R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F8R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F8R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F8R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F8R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R1 register  *******************/
-#define  CAN_F9R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F9R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F9R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F9R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F9R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F9R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F9R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F9R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F9R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F9R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F9R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F9R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F9R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F9R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F9R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F9R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F9R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F9R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F9R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F9R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F9R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F9R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F9R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F9R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F9R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F9R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F9R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F9R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F9R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F9R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F9R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F9R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R1 register  ******************/
-#define  CAN_F10R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F10R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F10R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F10R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F10R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F10R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F10R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F10R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F10R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F10R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F10R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F10R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F10R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F10R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F10R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F10R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F10R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F10R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F10R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F10R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F10R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F10R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F10R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F10R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F10R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F10R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F10R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F10R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F10R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F10R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F10R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F10R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R1 register  ******************/
-#define  CAN_F11R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F11R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F11R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F11R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F11R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F11R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F11R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F11R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F11R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F11R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F11R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F11R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F11R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F11R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F11R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F11R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F11R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F11R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F11R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F11R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F11R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F11R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F11R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F11R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F11R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F11R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F11R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F11R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F11R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F11R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F11R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F11R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R1 register  ******************/
-#define  CAN_F12R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F12R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F12R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F12R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F12R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F12R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F12R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F12R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F12R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F12R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F12R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F12R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F12R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F12R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F12R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F12R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F12R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F12R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F12R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F12R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F12R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F12R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F12R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F12R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F12R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F12R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F12R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F12R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F12R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F12R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F12R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F12R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R1 register  ******************/
-#define  CAN_F13R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F13R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F13R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F13R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F13R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F13R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F13R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F13R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F13R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F13R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F13R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F13R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F13R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F13R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F13R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F13R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F13R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F13R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F13R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F13R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F13R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F13R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F13R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F13R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F13R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F13R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F13R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F13R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F13R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F13R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F13R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F13R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F0R2 register  *******************/
-#define  CAN_F0R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F0R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F0R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F0R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F0R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F0R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F0R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F0R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F0R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F0R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F0R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F0R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F0R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F0R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F0R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F0R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F0R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F0R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F0R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F0R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F0R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F0R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F0R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F0R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F0R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F0R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F0R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F0R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F0R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F0R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F0R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F0R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R2 register  *******************/
-#define  CAN_F1R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F1R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F1R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F1R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F1R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F1R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F1R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F1R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F1R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F1R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F1R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F1R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F1R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F1R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F1R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F1R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F1R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F1R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F1R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F1R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F1R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F1R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F1R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F1R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F1R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F1R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F1R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F1R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F1R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F1R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F1R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F1R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R2 register  *******************/
-#define  CAN_F2R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F2R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F2R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F2R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F2R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F2R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F2R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F2R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F2R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F2R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F2R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F2R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F2R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F2R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F2R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F2R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F2R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F2R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F2R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F2R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F2R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F2R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F2R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F2R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F2R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F2R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F2R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F2R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F2R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F2R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F2R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F2R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R2 register  *******************/
-#define  CAN_F3R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F3R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F3R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F3R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F3R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F3R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F3R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F3R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F3R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F3R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F3R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F3R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F3R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F3R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F3R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F3R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F3R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F3R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F3R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F3R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F3R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F3R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F3R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F3R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F3R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F3R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F3R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F3R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F3R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F3R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F3R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F3R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R2 register  *******************/
-#define  CAN_F4R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F4R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F4R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F4R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F4R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F4R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F4R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F4R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F4R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F4R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F4R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F4R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F4R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F4R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F4R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F4R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F4R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F4R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F4R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F4R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F4R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F4R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F4R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F4R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F4R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F4R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F4R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F4R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F4R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F4R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F4R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F4R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R2 register  *******************/
-#define  CAN_F5R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F5R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F5R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F5R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F5R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F5R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F5R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F5R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F5R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F5R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F5R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F5R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F5R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F5R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F5R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F5R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F5R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F5R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F5R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F5R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F5R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F5R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F5R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F5R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F5R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F5R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F5R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F5R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F5R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F5R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F5R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F5R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R2 register  *******************/
-#define  CAN_F6R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F6R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F6R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F6R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F6R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F6R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F6R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F6R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F6R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F6R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F6R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F6R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F6R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F6R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F6R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F6R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F6R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F6R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F6R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F6R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F6R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F6R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F6R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F6R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F6R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F6R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F6R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F6R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F6R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F6R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F6R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F6R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R2 register  *******************/
-#define  CAN_F7R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F7R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F7R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F7R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F7R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F7R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F7R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F7R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F7R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F7R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F7R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F7R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F7R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F7R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F7R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F7R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F7R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F7R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F7R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F7R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F7R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F7R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F7R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F7R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F7R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F7R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F7R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F7R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F7R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F7R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F7R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F7R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R2 register  *******************/
-#define  CAN_F8R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F8R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F8R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F8R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F8R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F8R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F8R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F8R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F8R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F8R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F8R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F8R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F8R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F8R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F8R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F8R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F8R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F8R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F8R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F8R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F8R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F8R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F8R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F8R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F8R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F8R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F8R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F8R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F8R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F8R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F8R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F8R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R2 register  *******************/
-#define  CAN_F9R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F9R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F9R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F9R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F9R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F9R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F9R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F9R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F9R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F9R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F9R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F9R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F9R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F9R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F9R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F9R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F9R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F9R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F9R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F9R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F9R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F9R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F9R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F9R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F9R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F9R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F9R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F9R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F9R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F9R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F9R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F9R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R2 register  ******************/
-#define  CAN_F10R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F10R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F10R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F10R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F10R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F10R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F10R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F10R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F10R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F10R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F10R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F10R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F10R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F10R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F10R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F10R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F10R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F10R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F10R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F10R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F10R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F10R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F10R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F10R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F10R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F10R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F10R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F10R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F10R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F10R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F10R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F10R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R2 register  ******************/
-#define  CAN_F11R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F11R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F11R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F11R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F11R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F11R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F11R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F11R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F11R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F11R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F11R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F11R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F11R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F11R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F11R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F11R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F11R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F11R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F11R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F11R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F11R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F11R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F11R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F11R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F11R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F11R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F11R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F11R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F11R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F11R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F11R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F11R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R2 register  ******************/
-#define  CAN_F12R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F12R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F12R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F12R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F12R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F12R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F12R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F12R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F12R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F12R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F12R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F12R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F12R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F12R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F12R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F12R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F12R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F12R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F12R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F12R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F12R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F12R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F12R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F12R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F12R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F12R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F12R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F12R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F12R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F12R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F12R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F12R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R2 register  ******************/
-#define  CAN_F13R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F13R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F13R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F13R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F13R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F13R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F13R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F13R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F13R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F13R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F13R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F13R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F13R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F13R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F13R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F13R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F13R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F13R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F13R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F13R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F13R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F13R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F13R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F13R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F13R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F13R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F13R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F13R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F13R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F13R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F13R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F13R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRC calculation unit                              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           0xFFFFFFFFU /*!< Data register bits */
-
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         0xFFU        /*!< General-purpose 8-bit data register bits */
-
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        0x01U        /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Crypto Processor                                */
-/*                                                                            */
-/******************************************************************************/
-/******************* Bits definition for CRYP_CR register  ********************/
-#define CRYP_CR_ALGODIR                      0x00000004U
-
-#define CRYP_CR_ALGOMODE                     0x00080038U
-#define CRYP_CR_ALGOMODE_0                   0x00000008U
-#define CRYP_CR_ALGOMODE_1                   0x00000010U
-#define CRYP_CR_ALGOMODE_2                   0x00000020U
-#define CRYP_CR_ALGOMODE_TDES_ECB            0x00000000U
-#define CRYP_CR_ALGOMODE_TDES_CBC            0x00000008U
-#define CRYP_CR_ALGOMODE_DES_ECB             0x00000010U
-#define CRYP_CR_ALGOMODE_DES_CBC             0x00000018U
-#define CRYP_CR_ALGOMODE_AES_ECB             0x00000020U
-#define CRYP_CR_ALGOMODE_AES_CBC             0x00000028U
-#define CRYP_CR_ALGOMODE_AES_CTR             0x00000030U
-#define CRYP_CR_ALGOMODE_AES_KEY             0x00000038U
-
-#define CRYP_CR_DATATYPE                     0x000000C0U
-#define CRYP_CR_DATATYPE_0                   0x00000040U
-#define CRYP_CR_DATATYPE_1                   0x00000080U
-#define CRYP_CR_KEYSIZE                      0x00000300U
-#define CRYP_CR_KEYSIZE_0                    0x00000100U
-#define CRYP_CR_KEYSIZE_1                    0x00000200U
-#define CRYP_CR_FFLUSH                       0x00004000U
-#define CRYP_CR_CRYPEN                       0x00008000U
-
-#define CRYP_CR_GCM_CCMPH                    0x00030000U
-#define CRYP_CR_GCM_CCMPH_0                  0x00010000U
-#define CRYP_CR_GCM_CCMPH_1                  0x00020000U
-#define CRYP_CR_ALGOMODE_3                   0x00080000U 
-
-/****************** Bits definition for CRYP_SR register  *********************/
-#define CRYP_SR_IFEM                         0x00000001U
-#define CRYP_SR_IFNF                         0x00000002U
-#define CRYP_SR_OFNE                         0x00000004U
-#define CRYP_SR_OFFU                         0x00000008U
-#define CRYP_SR_BUSY                         0x00000010U
-/****************** Bits definition for CRYP_DMACR register  ******************/
-#define CRYP_DMACR_DIEN                      0x00000001U
-#define CRYP_DMACR_DOEN                      0x00000002U
-/*****************  Bits definition for CRYP_IMSCR register  ******************/
-#define CRYP_IMSCR_INIM                      0x00000001U
-#define CRYP_IMSCR_OUTIM                     0x00000002U
-/****************** Bits definition for CRYP_RISR register  *******************/
-#define CRYP_RISR_OUTRIS                     0x00000001U
-#define CRYP_RISR_INRIS                      0x00000002U
-/****************** Bits definition for CRYP_MISR register  *******************/
-#define CRYP_MISR_INMIS                      0x00000001U
-#define CRYP_MISR_OUTMIS                     0x00000002U
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Digital to Analog Converter                           */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DAC_CR register  ********************/
-#define  DAC_CR_EN1                          0x00000001U        /*!<DAC channel1 enable */
-#define  DAC_CR_BOFF1                        0x00000002U        /*!<DAC channel1 output buffer disable */
-#define  DAC_CR_TEN1                         0x00000004U        /*!<DAC channel1 Trigger enable */
-
-#define  DAC_CR_TSEL1                        0x00000038U        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define  DAC_CR_TSEL1_0                      0x00000008U        /*!<Bit 0 */
-#define  DAC_CR_TSEL1_1                      0x00000010U        /*!<Bit 1 */
-#define  DAC_CR_TSEL1_2                      0x00000020U        /*!<Bit 2 */
-
-#define  DAC_CR_WAVE1                        0x000000C0U        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE1_0                      0x00000040U        /*!<Bit 0 */
-#define  DAC_CR_WAVE1_1                      0x00000080U        /*!<Bit 1 */
-
-#define  DAC_CR_MAMP1                        0x00000F00U        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP1_0                      0x00000100U        /*!<Bit 0 */
-#define  DAC_CR_MAMP1_1                      0x00000200U        /*!<Bit 1 */
-#define  DAC_CR_MAMP1_2                      0x00000400U        /*!<Bit 2 */
-#define  DAC_CR_MAMP1_3                      0x00000800U        /*!<Bit 3 */
-
-#define  DAC_CR_DMAEN1                       0x00001000U        /*!<DAC channel1 DMA enable */
-#define  DAC_CR_DMAUDRIE1                    0x00002000U        /*!<DAC channel1 DMA underrun interrupt enable*/
-#define  DAC_CR_EN2                          0x00010000U        /*!<DAC channel2 enable */
-#define  DAC_CR_BOFF2                        0x00020000U        /*!<DAC channel2 output buffer disable */
-#define  DAC_CR_TEN2                         0x00040000U        /*!<DAC channel2 Trigger enable */
-
-#define  DAC_CR_TSEL2                        0x00380000U        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define  DAC_CR_TSEL2_0                      0x00080000U        /*!<Bit 0 */
-#define  DAC_CR_TSEL2_1                      0x00100000U        /*!<Bit 1 */
-#define  DAC_CR_TSEL2_2                      0x00200000U        /*!<Bit 2 */
-
-#define  DAC_CR_WAVE2                        0x00C00000U        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE2_0                      0x00400000U        /*!<Bit 0 */
-#define  DAC_CR_WAVE2_1                      0x00800000U        /*!<Bit 1 */
-
-#define  DAC_CR_MAMP2                        0x0F000000U        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP2_0                      0x01000000U        /*!<Bit 0 */
-#define  DAC_CR_MAMP2_1                      0x02000000U        /*!<Bit 1 */
-#define  DAC_CR_MAMP2_2                      0x04000000U        /*!<Bit 2 */
-#define  DAC_CR_MAMP2_3                      0x08000000U        /*!<Bit 3 */
-
-#define  DAC_CR_DMAEN2                       0x10000000U        /*!<DAC channel2 DMA enabled */
-#define  DAC_CR_DMAUDRIE2                    0x20000000U        /*!<DAC channel2 DMA underrun interrupt enable*/
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define  DAC_SWTRIGR_SWTRIG1                 0x01U               /*!<DAC channel1 software trigger */
-#define  DAC_SWTRIGR_SWTRIG2                 0x02U               /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define  DAC_DHR12R1_DACC1DHR                0x0FFFU            /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define  DAC_DHR12L1_DACC1DHR                0xFFF0U            /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define  DAC_DHR8R1_DACC1DHR                 0xFFU               /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define  DAC_DHR12R2_DACC2DHR                0x0FFFU            /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define  DAC_DHR12L2_DACC2DHR                0xFFF0U            /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define  DAC_DHR8R2_DACC2DHR                 0xFFU               /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define  DAC_DHR12RD_DACC1DHR                0x00000FFFU        /*!<DAC channel1 12-bit Right aligned data */
-#define  DAC_DHR12RD_DACC2DHR                0x0FFF0000U        /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define  DAC_DHR12LD_DACC1DHR                0x0000FFF0U        /*!<DAC channel1 12-bit Left aligned data */
-#define  DAC_DHR12LD_DACC2DHR                0xFFF00000U        /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define  DAC_DHR8RD_DACC1DHR                 0x00FFU            /*!<DAC channel1 8-bit Right aligned data */
-#define  DAC_DHR8RD_DACC2DHR                 0xFF00U            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define  DAC_DOR1_DACC1DOR                   0x0FFFU            /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define  DAC_DOR2_DACC2DOR                   0x0FFFU            /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define  DAC_SR_DMAUDR1                      0x00002000U        /*!<DAC channel1 DMA underrun flag */
-#define  DAC_SR_DMAUDR2                      0x20000000U        /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 Debug MCU                                  */
-/*                                                                            */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                             DMA Controller                                 */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DMA_SxCR register  *****************/
-#define DMA_SxCR_CHSEL                       0x0E000000U
-#define DMA_SxCR_CHSEL_0                     0x02000000U
-#define DMA_SxCR_CHSEL_1                     0x04000000U
-#define DMA_SxCR_CHSEL_2                     0x08000000U
-#define DMA_SxCR_MBURST                      0x01800000U
-#define DMA_SxCR_MBURST_0                    0x00800000U
-#define DMA_SxCR_MBURST_1                    0x01000000U
-#define DMA_SxCR_PBURST                      0x00600000U
-#define DMA_SxCR_PBURST_0                    0x00200000U
-#define DMA_SxCR_PBURST_1                    0x00400000U
-#define DMA_SxCR_CT                          0x00080000U
-#define DMA_SxCR_DBM                         0x00040000U
-#define DMA_SxCR_PL                          0x00030000U
-#define DMA_SxCR_PL_0                        0x00010000U
-#define DMA_SxCR_PL_1                        0x00020000U
-#define DMA_SxCR_PINCOS                      0x00008000U
-#define DMA_SxCR_MSIZE                       0x00006000U
-#define DMA_SxCR_MSIZE_0                     0x00002000U
-#define DMA_SxCR_MSIZE_1                     0x00004000U
-#define DMA_SxCR_PSIZE                       0x00001800U
-#define DMA_SxCR_PSIZE_0                     0x00000800U
-#define DMA_SxCR_PSIZE_1                     0x00001000U
-#define DMA_SxCR_MINC                        0x00000400U
-#define DMA_SxCR_PINC                        0x00000200U
-#define DMA_SxCR_CIRC                        0x00000100U
-#define DMA_SxCR_DIR                         0x000000C0U
-#define DMA_SxCR_DIR_0                       0x00000040U
-#define DMA_SxCR_DIR_1                       0x00000080U
-#define DMA_SxCR_PFCTRL                      0x00000020U
-#define DMA_SxCR_TCIE                        0x00000010U
-#define DMA_SxCR_HTIE                        0x00000008U
-#define DMA_SxCR_TEIE                        0x00000004U
-#define DMA_SxCR_DMEIE                       0x00000002U
-#define DMA_SxCR_EN                          0x00000001U
-
-/* Legacy defines */
-#define DMA_SxCR_ACK                         0x00100000U
-
-/********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            0x0000FFFFU
-#define DMA_SxNDT_0                          0x00000001U
-#define DMA_SxNDT_1                          0x00000002U
-#define DMA_SxNDT_2                          0x00000004U
-#define DMA_SxNDT_3                          0x00000008U
-#define DMA_SxNDT_4                          0x00000010U
-#define DMA_SxNDT_5                          0x00000020U
-#define DMA_SxNDT_6                          0x00000040U
-#define DMA_SxNDT_7                          0x00000080U
-#define DMA_SxNDT_8                          0x00000100U
-#define DMA_SxNDT_9                          0x00000200U
-#define DMA_SxNDT_10                         0x00000400U
-#define DMA_SxNDT_11                         0x00000800U
-#define DMA_SxNDT_12                         0x00001000U
-#define DMA_SxNDT_13                         0x00002000U
-#define DMA_SxNDT_14                         0x00004000U
-#define DMA_SxNDT_15                         0x00008000U
-
-/********************  Bits definition for DMA_SxFCR register  ****************/ 
-#define DMA_SxFCR_FEIE                       0x00000080U
-#define DMA_SxFCR_FS                         0x00000038U
-#define DMA_SxFCR_FS_0                       0x00000008U
-#define DMA_SxFCR_FS_1                       0x00000010U
-#define DMA_SxFCR_FS_2                       0x00000020U
-#define DMA_SxFCR_DMDIS                      0x00000004U
-#define DMA_SxFCR_FTH                        0x00000003U
-#define DMA_SxFCR_FTH_0                      0x00000001U
-#define DMA_SxFCR_FTH_1                      0x00000002U
-
-/********************  Bits definition for DMA_LISR register  *****************/ 
-#define DMA_LISR_TCIF3                       0x08000000U
-#define DMA_LISR_HTIF3                       0x04000000U
-#define DMA_LISR_TEIF3                       0x02000000U
-#define DMA_LISR_DMEIF3                      0x01000000U
-#define DMA_LISR_FEIF3                       0x00400000U
-#define DMA_LISR_TCIF2                       0x00200000U
-#define DMA_LISR_HTIF2                       0x00100000U
-#define DMA_LISR_TEIF2                       0x00080000U
-#define DMA_LISR_DMEIF2                      0x00040000U
-#define DMA_LISR_FEIF2                       0x00010000U
-#define DMA_LISR_TCIF1                       0x00000800U
-#define DMA_LISR_HTIF1                       0x00000400U
-#define DMA_LISR_TEIF1                       0x00000200U
-#define DMA_LISR_DMEIF1                      0x00000100U
-#define DMA_LISR_FEIF1                       0x00000040U
-#define DMA_LISR_TCIF0                       0x00000020U
-#define DMA_LISR_HTIF0                       0x00000010U
-#define DMA_LISR_TEIF0                       0x00000008U
-#define DMA_LISR_DMEIF0                      0x00000004U
-#define DMA_LISR_FEIF0                       0x00000001U
-
-/********************  Bits definition for DMA_HISR register  *****************/ 
-#define DMA_HISR_TCIF7                       0x08000000U
-#define DMA_HISR_HTIF7                       0x04000000U
-#define DMA_HISR_TEIF7                       0x02000000U
-#define DMA_HISR_DMEIF7                      0x01000000U
-#define DMA_HISR_FEIF7                       0x00400000U
-#define DMA_HISR_TCIF6                       0x00200000U
-#define DMA_HISR_HTIF6                       0x00100000U
-#define DMA_HISR_TEIF6                       0x00080000U
-#define DMA_HISR_DMEIF6                      0x00040000U
-#define DMA_HISR_FEIF6                       0x00010000U
-#define DMA_HISR_TCIF5                       0x00000800U
-#define DMA_HISR_HTIF5                       0x00000400U
-#define DMA_HISR_TEIF5                       0x00000200U
-#define DMA_HISR_DMEIF5                      0x00000100U
-#define DMA_HISR_FEIF5                       0x00000040U
-#define DMA_HISR_TCIF4                       0x00000020U
-#define DMA_HISR_HTIF4                       0x00000010U
-#define DMA_HISR_TEIF4                       0x00000008U
-#define DMA_HISR_DMEIF4                      0x00000004U
-#define DMA_HISR_FEIF4                       0x00000001U
-
-/********************  Bits definition for DMA_LIFCR register  ****************/ 
-#define DMA_LIFCR_CTCIF3                     0x08000000U
-#define DMA_LIFCR_CHTIF3                     0x04000000U
-#define DMA_LIFCR_CTEIF3                     0x02000000U
-#define DMA_LIFCR_CDMEIF3                    0x01000000U
-#define DMA_LIFCR_CFEIF3                     0x00400000U
-#define DMA_LIFCR_CTCIF2                     0x00200000U
-#define DMA_LIFCR_CHTIF2                     0x00100000U
-#define DMA_LIFCR_CTEIF2                     0x00080000U
-#define DMA_LIFCR_CDMEIF2                    0x00040000U
-#define DMA_LIFCR_CFEIF2                     0x00010000U
-#define DMA_LIFCR_CTCIF1                     0x00000800U
-#define DMA_LIFCR_CHTIF1                     0x00000400U
-#define DMA_LIFCR_CTEIF1                     0x00000200U
-#define DMA_LIFCR_CDMEIF1                    0x00000100U
-#define DMA_LIFCR_CFEIF1                     0x00000040U
-#define DMA_LIFCR_CTCIF0                     0x00000020U
-#define DMA_LIFCR_CHTIF0                     0x00000010U
-#define DMA_LIFCR_CTEIF0                     0x00000008U
-#define DMA_LIFCR_CDMEIF0                    0x00000004U
-#define DMA_LIFCR_CFEIF0                     0x00000001U
-
-/********************  Bits definition for DMA_HIFCR  register  ****************/ 
-#define DMA_HIFCR_CTCIF7                     0x08000000U
-#define DMA_HIFCR_CHTIF7                     0x04000000U
-#define DMA_HIFCR_CTEIF7                     0x02000000U
-#define DMA_HIFCR_CDMEIF7                    0x01000000U
-#define DMA_HIFCR_CFEIF7                     0x00400000U
-#define DMA_HIFCR_CTCIF6                     0x00200000U
-#define DMA_HIFCR_CHTIF6                     0x00100000U
-#define DMA_HIFCR_CTEIF6                     0x00080000U
-#define DMA_HIFCR_CDMEIF6                    0x00040000U
-#define DMA_HIFCR_CFEIF6                     0x00010000U
-#define DMA_HIFCR_CTCIF5                     0x00000800U
-#define DMA_HIFCR_CHTIF5                     0x00000400U
-#define DMA_HIFCR_CTEIF5                     0x00000200U
-#define DMA_HIFCR_CDMEIF5                    0x00000100U
-#define DMA_HIFCR_CFEIF5                     0x00000040U
-#define DMA_HIFCR_CTCIF4                     0x00000020U
-#define DMA_HIFCR_CHTIF4                     0x00000010U
-#define DMA_HIFCR_CTEIF4                     0x00000008U
-#define DMA_HIFCR_CDMEIF4                    0x00000004U
-#define DMA_HIFCR_CFEIF4                     0x00000001U
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                    External Interrupt/Event Controller                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    FLASH                                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    0x0000000FU
-#define FLASH_ACR_LATENCY_0WS                0x00000000U
-#define FLASH_ACR_LATENCY_1WS                0x00000001U
-#define FLASH_ACR_LATENCY_2WS                0x00000002U
-#define FLASH_ACR_LATENCY_3WS                0x00000003U
-#define FLASH_ACR_LATENCY_4WS                0x00000004U
-#define FLASH_ACR_LATENCY_5WS                0x00000005U
-#define FLASH_ACR_LATENCY_6WS                0x00000006U
-#define FLASH_ACR_LATENCY_7WS                0x00000007U
-
-#define FLASH_ACR_PRFTEN                     0x00000100U
-#define FLASH_ACR_ICEN                       0x00000200U
-#define FLASH_ACR_DCEN                       0x00000400U
-#define FLASH_ACR_ICRST                      0x00000800U
-#define FLASH_ACR_DCRST                      0x00001000U
-#define FLASH_ACR_BYTE0_ADDRESS              0x40023C00U
-#define FLASH_ACR_BYTE2_ADDRESS              0x40023C03U
-
-/*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         0x00000001U
-#define FLASH_SR_SOP                         0x00000002U
-#define FLASH_SR_WRPERR                      0x00000010U
-#define FLASH_SR_PGAERR                      0x00000020U
-#define FLASH_SR_PGPERR                      0x00000040U
-#define FLASH_SR_PGSERR                      0x00000080U
-#define FLASH_SR_BSY                         0x00010000U
-
-/*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          0x00000001U
-#define FLASH_CR_SER                         0x00000002U
-#define FLASH_CR_MER                         0x00000004U
-#define FLASH_CR_SNB                         0x000000F8U
-#define FLASH_CR_SNB_0                       0x00000008U
-#define FLASH_CR_SNB_1                       0x00000010U
-#define FLASH_CR_SNB_2                       0x00000020U
-#define FLASH_CR_SNB_3                       0x00000040U
-#define FLASH_CR_SNB_4                       0x00000080U
-#define FLASH_CR_PSIZE                       0x00000300U
-#define FLASH_CR_PSIZE_0                     0x00000100U
-#define FLASH_CR_PSIZE_1                     0x00000200U
-#define FLASH_CR_STRT                        0x00010000U
-#define FLASH_CR_EOPIE                       0x01000000U
-#define FLASH_CR_LOCK                        0x80000000U
-
-/*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                 0x00000001U
-#define FLASH_OPTCR_OPTSTRT                 0x00000002U
-#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
-#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
-#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
-
-#define FLASH_OPTCR_WDG_SW                  0x00000020U
-#define FLASH_OPTCR_nRST_STOP               0x00000040U
-#define FLASH_OPTCR_nRST_STDBY              0x00000080U
-#define FLASH_OPTCR_RDP                     0x0000FF00U
-#define FLASH_OPTCR_RDP_0                   0x00000100U
-#define FLASH_OPTCR_RDP_1                   0x00000200U
-#define FLASH_OPTCR_RDP_2                   0x00000400U
-#define FLASH_OPTCR_RDP_3                   0x00000800U
-#define FLASH_OPTCR_RDP_4                   0x00001000U
-#define FLASH_OPTCR_RDP_5                   0x00002000U
-#define FLASH_OPTCR_RDP_6                   0x00004000U
-#define FLASH_OPTCR_RDP_7                   0x00008000U
-#define FLASH_OPTCR_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR_nWRP_0                  0x00010000U
-#define FLASH_OPTCR_nWRP_1                  0x00020000U
-#define FLASH_OPTCR_nWRP_2                  0x00040000U
-#define FLASH_OPTCR_nWRP_3                  0x00080000U
-#define FLASH_OPTCR_nWRP_4                  0x00100000U
-#define FLASH_OPTCR_nWRP_5                  0x00200000U
-#define FLASH_OPTCR_nWRP_6                  0x00400000U
-#define FLASH_OPTCR_nWRP_7                  0x00800000U
-#define FLASH_OPTCR_nWRP_8                  0x01000000U
-#define FLASH_OPTCR_nWRP_9                  0x02000000U
-#define FLASH_OPTCR_nWRP_10                 0x04000000U
-#define FLASH_OPTCR_nWRP_11                 0x08000000U
-                                             
-/******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR1_nWRP_0                  0x00010000U
-#define FLASH_OPTCR1_nWRP_1                  0x00020000U
-#define FLASH_OPTCR1_nWRP_2                  0x00040000U
-#define FLASH_OPTCR1_nWRP_3                  0x00080000U
-#define FLASH_OPTCR1_nWRP_4                  0x00100000U
-#define FLASH_OPTCR1_nWRP_5                  0x00200000U
-#define FLASH_OPTCR1_nWRP_6                  0x00400000U
-#define FLASH_OPTCR1_nWRP_7                  0x00800000U
-#define FLASH_OPTCR1_nWRP_8                  0x01000000U
-#define FLASH_OPTCR1_nWRP_9                  0x02000000U
-#define FLASH_OPTCR1_nWRP_10                 0x04000000U
-#define FLASH_OPTCR1_nWRP_11                 0x08000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Flexible Static Memory Controller                    */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for FSMC_BCR1 register  *******************/
-#define  FSMC_BCR1_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FSMC_BCR1_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FSMC_BCR1_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FSMC_BCR1_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FSMC_BCR1_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FSMC_BCR1_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR1_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FSMC_BCR1_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FSMC_BCR1_FACCEN                    0x00000040U        /*!<Flash access enable                    */
-#define  FSMC_BCR1_BURSTEN                   0x00000100U        /*!<Burst enable bit                       */
-#define  FSMC_BCR1_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit               */
-#define  FSMC_BCR1_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support             */
-#define  FSMC_BCR1_WAITCFG                   0x00000800U        /*!<Wait timing configuration              */
-#define  FSMC_BCR1_WREN                      0x00001000U        /*!<Write enable bit                       */
-#define  FSMC_BCR1_WAITEN                    0x00002000U        /*!<Wait enable bit                        */
-#define  FSMC_BCR1_EXTMOD                    0x00004000U        /*!<Extended mode enable                   */
-#define  FSMC_BCR1_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait                      */
-#define  FSMC_BCR1_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FSMC_BCR1_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FSMC_BCR1_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FSMC_BCR1_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FSMC_BCR1_CBURSTRW                  0x00080000U        /*!<Write burst enable                     */
-
-/******************  Bit definition for FSMC_BCR2 register  *******************/
-#define  FSMC_BCR2_MBKEN                     0x00000001U        /*!<Memory bank enable bit                */
-#define  FSMC_BCR2_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FSMC_BCR2_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FSMC_BCR2_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FSMC_BCR2_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FSMC_BCR2_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR2_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FSMC_BCR2_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FSMC_BCR2_FACCEN                    0x00000040U        /*!<Flash access enable                    */
-#define  FSMC_BCR2_BURSTEN                   0x00000100U        /*!<Burst enable bit                       */
-#define  FSMC_BCR2_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit               */
-#define  FSMC_BCR2_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support             */
-#define  FSMC_BCR2_WAITCFG                   0x00000800U        /*!<Wait timing configuration              */
-#define  FSMC_BCR2_WREN                      0x00001000U        /*!<Write enable bit                       */
-#define  FSMC_BCR2_WAITEN                    0x00002000U        /*!<Wait enable bit                        */
-#define  FSMC_BCR2_EXTMOD                    0x00004000U        /*!<Extended mode enable                   */
-#define  FSMC_BCR2_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait                      */
-#define  FSMC_BCR2_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FSMC_BCR2_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FSMC_BCR2_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FSMC_BCR2_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FSMC_BCR2_CBURSTRW                  0x00080000U        /*!<Write burst enable                     */
-
-/******************  Bit definition for FSMC_BCR3 register  *******************/
-#define  FSMC_BCR3_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FSMC_BCR3_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FSMC_BCR3_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FSMC_BCR3_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FSMC_BCR3_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FSMC_BCR3_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR3_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FSMC_BCR3_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FSMC_BCR3_FACCEN                    0x00000040U        /*!<Flash access enable                    */
-#define  FSMC_BCR3_BURSTEN                   0x00000100U        /*!<Burst enable bit                       */
-#define  FSMC_BCR3_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit               */
-#define  FSMC_BCR3_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support             */
-#define  FSMC_BCR3_WAITCFG                   0x00000800U        /*!<Wait timing configuration              */
-#define  FSMC_BCR3_WREN                      0x00001000U        /*!<Write enable bit                       */
-#define  FSMC_BCR3_WAITEN                    0x00002000U        /*!<Wait enable bit                        */
-#define  FSMC_BCR3_EXTMOD                    0x00004000U        /*!<Extended mode enable                   */
-#define  FSMC_BCR3_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait                      */
-#define  FSMC_BCR3_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FSMC_BCR3_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FSMC_BCR3_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FSMC_BCR3_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FSMC_BCR3_CBURSTRW                  0x00080000U        /*!<Write burst enable                     */
-
-/******************  Bit definition for FSMC_BCR4 register  *******************/
-#define  FSMC_BCR4_MBKEN                     0x00000001U        /*!<Memory bank enable bit */
-#define  FSMC_BCR4_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FSMC_BCR4_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FSMC_BCR4_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FSMC_BCR4_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FSMC_BCR4_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR4_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FSMC_BCR4_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FSMC_BCR4_FACCEN                    0x00000040U        /*!<Flash access enable                    */
-#define  FSMC_BCR4_BURSTEN                   0x00000100U        /*!<Burst enable bit                       */
-#define  FSMC_BCR4_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit               */
-#define  FSMC_BCR4_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support             */
-#define  FSMC_BCR4_WAITCFG                   0x00000800U        /*!<Wait timing configuration              */
-#define  FSMC_BCR4_WREN                      0x00001000U        /*!<Write enable bit                       */
-#define  FSMC_BCR4_WAITEN                    0x00002000U        /*!<Wait enable bit                        */
-#define  FSMC_BCR4_EXTMOD                    0x00004000U        /*!<Extended mode enable                   */
-#define  FSMC_BCR4_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait                      */
-#define  FSMC_BCR4_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FSMC_BCR4_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FSMC_BCR4_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FSMC_BCR4_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FSMC_BCR4_CBURSTRW                  0x00080000U        /*!<Write burst enable                     */
-
-/******************  Bit definition for FSMC_BTR1 register  ******************/
-#define  FSMC_BTR1_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR1_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FSMC_BTR1_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FSMC_BTR1_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FSMC_BTR1_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BTR1_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR1_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FSMC_BTR1_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FSMC_BTR1_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FSMC_BTR1_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BTR1_DATAST                    0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */
-#define  FSMC_BTR1_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FSMC_BTR1_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FSMC_BTR1_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FSMC_BTR1_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FSMC_BTR1_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FSMC_BTR1_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FSMC_BTR1_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FSMC_BTR1_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BTR1_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR1_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FSMC_BTR1_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FSMC_BTR1_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FSMC_BTR1_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BTR1_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR1_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FSMC_BTR1_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FSMC_BTR1_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FSMC_BTR1_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FSMC_BTR1_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR1_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FSMC_BTR1_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FSMC_BTR1_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FSMC_BTR1_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FSMC_BTR1_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR1_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FSMC_BTR1_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BTR2 register  *******************/
-#define  FSMC_BTR2_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR2_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FSMC_BTR2_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FSMC_BTR2_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FSMC_BTR2_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BTR2_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR2_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FSMC_BTR2_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FSMC_BTR2_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FSMC_BTR2_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BTR2_DATAST                    0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */
-#define  FSMC_BTR2_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FSMC_BTR2_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FSMC_BTR2_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FSMC_BTR2_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FSMC_BTR2_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FSMC_BTR2_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FSMC_BTR2_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FSMC_BTR2_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BTR2_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR2_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FSMC_BTR2_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FSMC_BTR2_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FSMC_BTR2_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BTR2_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR2_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FSMC_BTR2_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FSMC_BTR2_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FSMC_BTR2_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FSMC_BTR2_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR2_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FSMC_BTR2_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FSMC_BTR2_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FSMC_BTR2_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FSMC_BTR2_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR2_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FSMC_BTR2_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/*******************  Bit definition for FSMC_BTR3 register  *******************/
-#define  FSMC_BTR3_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR3_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FSMC_BTR3_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FSMC_BTR3_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FSMC_BTR3_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BTR3_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR3_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FSMC_BTR3_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FSMC_BTR3_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FSMC_BTR3_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BTR3_DATAST                    0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */
-#define  FSMC_BTR3_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FSMC_BTR3_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FSMC_BTR3_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FSMC_BTR3_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FSMC_BTR3_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FSMC_BTR3_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FSMC_BTR3_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FSMC_BTR3_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BTR3_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR3_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FSMC_BTR3_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FSMC_BTR3_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FSMC_BTR3_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BTR3_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR3_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FSMC_BTR3_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FSMC_BTR3_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FSMC_BTR3_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FSMC_BTR3_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR3_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FSMC_BTR3_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FSMC_BTR3_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FSMC_BTR3_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FSMC_BTR3_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR3_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FSMC_BTR3_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BTR4 register  *******************/
-#define  FSMC_BTR4_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR4_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FSMC_BTR4_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FSMC_BTR4_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FSMC_BTR4_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BTR4_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR4_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FSMC_BTR4_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FSMC_BTR4_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FSMC_BTR4_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BTR4_DATAST                    0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */
-#define  FSMC_BTR4_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FSMC_BTR4_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FSMC_BTR4_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FSMC_BTR4_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FSMC_BTR4_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FSMC_BTR4_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FSMC_BTR4_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FSMC_BTR4_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BTR4_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR4_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FSMC_BTR4_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FSMC_BTR4_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FSMC_BTR4_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BTR4_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR4_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FSMC_BTR4_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FSMC_BTR4_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FSMC_BTR4_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FSMC_BTR4_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR4_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FSMC_BTR4_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FSMC_BTR4_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FSMC_BTR4_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FSMC_BTR4_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR4_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FSMC_BTR4_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR1 register  ******************/
-#define  FSMC_BWTR1_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR1_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FSMC_BWTR1_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FSMC_BWTR1_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FSMC_BWTR1_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BWTR1_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR1_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FSMC_BWTR1_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FSMC_BWTR1_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FSMC_BWTR1_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BWTR1_DATAST                   0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */
-#define  FSMC_BWTR1_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FSMC_BWTR1_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FSMC_BWTR1_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FSMC_BWTR1_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FSMC_BWTR1_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FSMC_BWTR1_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FSMC_BWTR1_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FSMC_BWTR1_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BWTR1_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FSMC_BWTR1_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FSMC_BWTR1_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FSMC_BWTR1_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FSMC_BWTR1_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BWTR1_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR1_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FSMC_BWTR1_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR2 register  ******************/
-#define  FSMC_BWTR2_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR2_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FSMC_BWTR2_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FSMC_BWTR2_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FSMC_BWTR2_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BWTR2_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR2_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FSMC_BWTR2_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FSMC_BWTR2_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FSMC_BWTR2_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BWTR2_DATAST                   0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */
-#define  FSMC_BWTR2_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FSMC_BWTR2_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FSMC_BWTR2_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FSMC_BWTR2_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FSMC_BWTR2_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FSMC_BWTR2_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FSMC_BWTR2_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FSMC_BWTR2_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BWTR2_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FSMC_BWTR2_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FSMC_BWTR2_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FSMC_BWTR2_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FSMC_BWTR2_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BWTR2_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR2_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FSMC_BWTR2_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR3 register  ******************/
-#define  FSMC_BWTR3_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR3_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FSMC_BWTR3_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FSMC_BWTR3_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FSMC_BWTR3_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BWTR3_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR3_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FSMC_BWTR3_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FSMC_BWTR3_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FSMC_BWTR3_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BWTR3_DATAST                   0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */
-#define  FSMC_BWTR3_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FSMC_BWTR3_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FSMC_BWTR3_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FSMC_BWTR3_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FSMC_BWTR3_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FSMC_BWTR3_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FSMC_BWTR3_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FSMC_BWTR3_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BWTR3_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FSMC_BWTR3_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FSMC_BWTR3_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FSMC_BWTR3_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FSMC_BWTR3_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BWTR3_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR3_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FSMC_BWTR3_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR4 register  ******************/
-#define  FSMC_BWTR4_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR4_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FSMC_BWTR4_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FSMC_BWTR4_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FSMC_BWTR4_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BWTR4_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR4_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FSMC_BWTR4_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FSMC_BWTR4_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FSMC_BWTR4_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BWTR4_DATAST                   0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */
-#define  FSMC_BWTR4_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FSMC_BWTR4_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FSMC_BWTR4_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FSMC_BWTR4_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FSMC_BWTR4_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FSMC_BWTR4_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FSMC_BWTR4_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FSMC_BWTR4_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BWTR4_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FSMC_BWTR4_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FSMC_BWTR4_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FSMC_BWTR4_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FSMC_BWTR4_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BWTR4_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR4_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FSMC_BWTR4_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_PCR2 register  *******************/
-#define  FSMC_PCR2_PWAITEN                   0x00000002U        /*!<Wait feature enable bit */
-#define  FSMC_PCR2_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FSMC_PCR2_PTYP                      0x00000008U        /*!<Memory type */
-
-#define  FSMC_PCR2_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FSMC_PCR2_PWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FSMC_PCR2_PWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FSMC_PCR2_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit */
-
-#define  FSMC_PCR2_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay) */
-#define  FSMC_PCR2_TCLR_0                    0x00000200U        /*!<Bit 0 */
-#define  FSMC_PCR2_TCLR_1                    0x00000400U        /*!<Bit 1 */
-#define  FSMC_PCR2_TCLR_2                    0x00000800U        /*!<Bit 2 */
-#define  FSMC_PCR2_TCLR_3                    0x00001000U        /*!<Bit 3 */
-
-#define  FSMC_PCR2_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay) */
-#define  FSMC_PCR2_TAR_0                     0x00002000U        /*!<Bit 0 */
-#define  FSMC_PCR2_TAR_1                     0x00004000U        /*!<Bit 1 */
-#define  FSMC_PCR2_TAR_2                     0x00008000U        /*!<Bit 2 */
-#define  FSMC_PCR2_TAR_3                     0x00010000U        /*!<Bit 3 */
-
-#define  FSMC_PCR2_ECCPS                     0x000E0000U        /*!<ECCPS[1:0] bits (ECC page size) */
-#define  FSMC_PCR2_ECCPS_0                   0x00020000U        /*!<Bit 0 */
-#define  FSMC_PCR2_ECCPS_1                   0x00040000U        /*!<Bit 1 */
-#define  FSMC_PCR2_ECCPS_2                   0x00080000U        /*!<Bit 2 */
-
-/******************  Bit definition for FSMC_PCR3 register  *******************/
-#define  FSMC_PCR3_PWAITEN                   0x00000002U        /*!<Wait feature enable bit */
-#define  FSMC_PCR3_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FSMC_PCR3_PTYP                      0x00000008U        /*!<Memory type */
-
-#define  FSMC_PCR3_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FSMC_PCR3_PWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FSMC_PCR3_PWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FSMC_PCR3_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit */
-
-#define  FSMC_PCR3_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay) */
-#define  FSMC_PCR3_TCLR_0                    0x00000200U        /*!<Bit 0 */
-#define  FSMC_PCR3_TCLR_1                    0x00000400U        /*!<Bit 1 */
-#define  FSMC_PCR3_TCLR_2                    0x00000800U        /*!<Bit 2 */
-#define  FSMC_PCR3_TCLR_3                    0x00001000U        /*!<Bit 3 */
-
-#define  FSMC_PCR3_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay) */
-#define  FSMC_PCR3_TAR_0                     0x00002000U        /*!<Bit 0 */
-#define  FSMC_PCR3_TAR_1                     0x00004000U        /*!<Bit 1 */
-#define  FSMC_PCR3_TAR_2                     0x00008000U        /*!<Bit 2 */
-#define  FSMC_PCR3_TAR_3                     0x00010000U        /*!<Bit 3 */
-
-#define  FSMC_PCR3_ECCPS                     0x000E0000U        /*!<ECCPS[2:0] bits (ECC page size) */
-#define  FSMC_PCR3_ECCPS_0                   0x00020000U        /*!<Bit 0 */
-#define  FSMC_PCR3_ECCPS_1                   0x00040000U        /*!<Bit 1 */
-#define  FSMC_PCR3_ECCPS_2                   0x00080000U        /*!<Bit 2 */
-
-/******************  Bit definition for FSMC_PCR4 register  *******************/
-#define  FSMC_PCR4_PWAITEN                   0x00000002U        /*!<Wait feature enable bit */
-#define  FSMC_PCR4_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FSMC_PCR4_PTYP                      0x00000008U        /*!<Memory type */
-
-#define  FSMC_PCR4_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FSMC_PCR4_PWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FSMC_PCR4_PWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FSMC_PCR4_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit */
-
-#define  FSMC_PCR4_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay) */
-#define  FSMC_PCR4_TCLR_0                    0x00000200U        /*!<Bit 0 */
-#define  FSMC_PCR4_TCLR_1                    0x00000400U        /*!<Bit 1 */
-#define  FSMC_PCR4_TCLR_2                    0x00000800U        /*!<Bit 2 */
-#define  FSMC_PCR4_TCLR_3                    0x00001000U        /*!<Bit 3 */
-
-#define  FSMC_PCR4_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay) */
-#define  FSMC_PCR4_TAR_0                     0x00002000U        /*!<Bit 0 */
-#define  FSMC_PCR4_TAR_1                     0x00004000U        /*!<Bit 1 */
-#define  FSMC_PCR4_TAR_2                     0x00008000U        /*!<Bit 2 */
-#define  FSMC_PCR4_TAR_3                     0x00010000U        /*!<Bit 3 */
-
-#define  FSMC_PCR4_ECCPS                     0x000E0000U        /*!<ECCPS[2:0] bits (ECC page size) */
-#define  FSMC_PCR4_ECCPS_0                   0x00020000U        /*!<Bit 0 */
-#define  FSMC_PCR4_ECCPS_1                   0x00040000U        /*!<Bit 1 */
-#define  FSMC_PCR4_ECCPS_2                   0x00080000U        /*!<Bit 2 */
-
-/*******************  Bit definition for FSMC_SR2 register  *******************/
-#define  FSMC_SR2_IRS                        0x01U               /*!<Interrupt Rising Edge status                */
-#define  FSMC_SR2_ILS                        0x02U               /*!<Interrupt Level status                      */
-#define  FSMC_SR2_IFS                        0x04U               /*!<Interrupt Falling Edge status               */
-#define  FSMC_SR2_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FSMC_SR2_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit        */
-#define  FSMC_SR2_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FSMC_SR2_FEMPT                      0x40U               /*!<FIFO empty */
-
-/*******************  Bit definition for FSMC_SR3 register  *******************/
-#define  FSMC_SR3_IRS                        0x01U               /*!<Interrupt Rising Edge status                */
-#define  FSMC_SR3_ILS                        0x02U               /*!<Interrupt Level status                      */
-#define  FSMC_SR3_IFS                        0x04U               /*!<Interrupt Falling Edge status               */
-#define  FSMC_SR3_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FSMC_SR3_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit        */
-#define  FSMC_SR3_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FSMC_SR3_FEMPT                      0x40U               /*!<FIFO empty */
-
-/*******************  Bit definition for FSMC_SR4 register  *******************/
-#define  FSMC_SR4_IRS                        0x01U               /*!<Interrupt Rising Edge status                 */
-#define  FSMC_SR4_ILS                        0x02U               /*!<Interrupt Level status                       */
-#define  FSMC_SR4_IFS                        0x04U               /*!<Interrupt Falling Edge status                */
-#define  FSMC_SR4_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit   */
-#define  FSMC_SR4_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit         */
-#define  FSMC_SR4_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit  */
-#define  FSMC_SR4_FEMPT                      0x40U               /*!<FIFO empty */
-
-/******************  Bit definition for FSMC_PMEM2 register  ******************/
-#define  FSMC_PMEM2_MEMSET2                  0x000000FFU        /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
-#define  FSMC_PMEM2_MEMSET2_0                0x00000001U        /*!<Bit 0 */
-#define  FSMC_PMEM2_MEMSET2_1                0x00000002U        /*!<Bit 1 */
-#define  FSMC_PMEM2_MEMSET2_2                0x00000004U        /*!<Bit 2 */
-#define  FSMC_PMEM2_MEMSET2_3                0x00000008U        /*!<Bit 3 */
-#define  FSMC_PMEM2_MEMSET2_4                0x00000010U        /*!<Bit 4 */
-#define  FSMC_PMEM2_MEMSET2_5                0x00000020U        /*!<Bit 5 */
-#define  FSMC_PMEM2_MEMSET2_6                0x00000040U        /*!<Bit 6 */
-#define  FSMC_PMEM2_MEMSET2_7                0x00000080U        /*!<Bit 7 */
-
-#define  FSMC_PMEM2_MEMWAIT2                 0x0000FF00U        /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
-#define  FSMC_PMEM2_MEMWAIT2_0               0x00000100U        /*!<Bit 0 */
-#define  FSMC_PMEM2_MEMWAIT2_1               0x00000200U        /*!<Bit 1 */
-#define  FSMC_PMEM2_MEMWAIT2_2               0x00000400U        /*!<Bit 2 */
-#define  FSMC_PMEM2_MEMWAIT2_3               0x00000800U        /*!<Bit 3 */
-#define  FSMC_PMEM2_MEMWAIT2_4               0x00001000U        /*!<Bit 4 */
-#define  FSMC_PMEM2_MEMWAIT2_5               0x00002000U        /*!<Bit 5 */
-#define  FSMC_PMEM2_MEMWAIT2_6               0x00004000U        /*!<Bit 6 */
-#define  FSMC_PMEM2_MEMWAIT2_7               0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_PMEM2_MEMHOLD2                 0x00FF0000U        /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
-#define  FSMC_PMEM2_MEMHOLD2_0               0x00010000U        /*!<Bit 0 */
-#define  FSMC_PMEM2_MEMHOLD2_1               0x00020000U        /*!<Bit 1 */
-#define  FSMC_PMEM2_MEMHOLD2_2               0x00040000U        /*!<Bit 2 */
-#define  FSMC_PMEM2_MEMHOLD2_3               0x00080000U        /*!<Bit 3 */
-#define  FSMC_PMEM2_MEMHOLD2_4               0x00100000U        /*!<Bit 4 */
-#define  FSMC_PMEM2_MEMHOLD2_5               0x00200000U        /*!<Bit 5 */
-#define  FSMC_PMEM2_MEMHOLD2_6               0x00400000U        /*!<Bit 6 */
-#define  FSMC_PMEM2_MEMHOLD2_7               0x00800000U        /*!<Bit 7 */
-
-#define  FSMC_PMEM2_MEMHIZ2                  0xFF000000U        /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
-#define  FSMC_PMEM2_MEMHIZ2_0                0x01000000U        /*!<Bit 0 */
-#define  FSMC_PMEM2_MEMHIZ2_1                0x02000000U        /*!<Bit 1 */
-#define  FSMC_PMEM2_MEMHIZ2_2                0x04000000U        /*!<Bit 2 */
-#define  FSMC_PMEM2_MEMHIZ2_3                0x08000000U        /*!<Bit 3 */
-#define  FSMC_PMEM2_MEMHIZ2_4                0x10000000U        /*!<Bit 4 */
-#define  FSMC_PMEM2_MEMHIZ2_5                0x20000000U        /*!<Bit 5 */
-#define  FSMC_PMEM2_MEMHIZ2_6                0x40000000U        /*!<Bit 6 */
-#define  FSMC_PMEM2_MEMHIZ2_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FSMC_PMEM3 register  ******************/
-#define  FSMC_PMEM3_MEMSET3                  0x000000FFU        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
-#define  FSMC_PMEM3_MEMSET3_0                0x00000001U        /*!<Bit 0 */
-#define  FSMC_PMEM3_MEMSET3_1                0x00000002U        /*!<Bit 1 */
-#define  FSMC_PMEM3_MEMSET3_2                0x00000004U        /*!<Bit 2 */
-#define  FSMC_PMEM3_MEMSET3_3                0x00000008U        /*!<Bit 3 */
-#define  FSMC_PMEM3_MEMSET3_4                0x00000010U        /*!<Bit 4 */
-#define  FSMC_PMEM3_MEMSET3_5                0x00000020U        /*!<Bit 5 */
-#define  FSMC_PMEM3_MEMSET3_6                0x00000040U        /*!<Bit 6 */
-#define  FSMC_PMEM3_MEMSET3_7                0x00000080U        /*!<Bit 7 */
-
-#define  FSMC_PMEM3_MEMWAIT3                 0x0000FF00U        /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
-#define  FSMC_PMEM3_MEMWAIT3_0               0x00000100U        /*!<Bit 0 */
-#define  FSMC_PMEM3_MEMWAIT3_1               0x00000200U        /*!<Bit 1 */
-#define  FSMC_PMEM3_MEMWAIT3_2               0x00000400U        /*!<Bit 2 */
-#define  FSMC_PMEM3_MEMWAIT3_3               0x00000800U        /*!<Bit 3 */
-#define  FSMC_PMEM3_MEMWAIT3_4               0x00001000U        /*!<Bit 4 */
-#define  FSMC_PMEM3_MEMWAIT3_5               0x00002000U        /*!<Bit 5 */
-#define  FSMC_PMEM3_MEMWAIT3_6               0x00004000U        /*!<Bit 6 */
-#define  FSMC_PMEM3_MEMWAIT3_7               0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_PMEM3_MEMHOLD3                 0x00FF0000U        /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
-#define  FSMC_PMEM3_MEMHOLD3_0               0x00010000U        /*!<Bit 0 */
-#define  FSMC_PMEM3_MEMHOLD3_1               0x00020000U        /*!<Bit 1 */
-#define  FSMC_PMEM3_MEMHOLD3_2               0x00040000U        /*!<Bit 2 */
-#define  FSMC_PMEM3_MEMHOLD3_3               0x00080000U        /*!<Bit 3 */
-#define  FSMC_PMEM3_MEMHOLD3_4               0x00100000U        /*!<Bit 4 */
-#define  FSMC_PMEM3_MEMHOLD3_5               0x00200000U        /*!<Bit 5 */
-#define  FSMC_PMEM3_MEMHOLD3_6               0x00400000U        /*!<Bit 6 */
-#define  FSMC_PMEM3_MEMHOLD3_7               0x00800000U        /*!<Bit 7 */
-
-#define  FSMC_PMEM3_MEMHIZ3                  0xFF000000U        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
-#define  FSMC_PMEM3_MEMHIZ3_0                0x01000000U        /*!<Bit 0 */
-#define  FSMC_PMEM3_MEMHIZ3_1                0x02000000U        /*!<Bit 1 */
-#define  FSMC_PMEM3_MEMHIZ3_2                0x04000000U        /*!<Bit 2 */
-#define  FSMC_PMEM3_MEMHIZ3_3                0x08000000U        /*!<Bit 3 */
-#define  FSMC_PMEM3_MEMHIZ3_4                0x10000000U        /*!<Bit 4 */
-#define  FSMC_PMEM3_MEMHIZ3_5                0x20000000U        /*!<Bit 5 */
-#define  FSMC_PMEM3_MEMHIZ3_6                0x40000000U        /*!<Bit 6 */
-#define  FSMC_PMEM3_MEMHIZ3_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FSMC_PMEM4 register  ******************/
-#define  FSMC_PMEM4_MEMSET4                  0x000000FFU        /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
-#define  FSMC_PMEM4_MEMSET4_0                0x00000001U        /*!<Bit 0 */
-#define  FSMC_PMEM4_MEMSET4_1                0x00000002U        /*!<Bit 1 */
-#define  FSMC_PMEM4_MEMSET4_2                0x00000004U        /*!<Bit 2 */
-#define  FSMC_PMEM4_MEMSET4_3                0x00000008U        /*!<Bit 3 */
-#define  FSMC_PMEM4_MEMSET4_4                0x00000010U        /*!<Bit 4 */
-#define  FSMC_PMEM4_MEMSET4_5                0x00000020U        /*!<Bit 5 */
-#define  FSMC_PMEM4_MEMSET4_6                0x00000040U        /*!<Bit 6 */
-#define  FSMC_PMEM4_MEMSET4_7                0x00000080U        /*!<Bit 7 */
-
-#define  FSMC_PMEM4_MEMWAIT4                 0x0000FF00U        /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
-#define  FSMC_PMEM4_MEMWAIT4_0               0x00000100U        /*!<Bit 0 */
-#define  FSMC_PMEM4_MEMWAIT4_1               0x00000200U        /*!<Bit 1 */
-#define  FSMC_PMEM4_MEMWAIT4_2               0x00000400U        /*!<Bit 2 */
-#define  FSMC_PMEM4_MEMWAIT4_3               0x00000800U        /*!<Bit 3 */
-#define  FSMC_PMEM4_MEMWAIT4_4               0x00001000U        /*!<Bit 4 */
-#define  FSMC_PMEM4_MEMWAIT4_5               0x00002000U        /*!<Bit 5 */
-#define  FSMC_PMEM4_MEMWAIT4_6               0x00004000U        /*!<Bit 6 */
-#define  FSMC_PMEM4_MEMWAIT4_7               0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_PMEM4_MEMHOLD4                 0x00FF0000U        /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
-#define  FSMC_PMEM4_MEMHOLD4_0               0x00010000U        /*!<Bit 0 */
-#define  FSMC_PMEM4_MEMHOLD4_1               0x00020000U        /*!<Bit 1 */
-#define  FSMC_PMEM4_MEMHOLD4_2               0x00040000U        /*!<Bit 2 */
-#define  FSMC_PMEM4_MEMHOLD4_3               0x00080000U        /*!<Bit 3 */
-#define  FSMC_PMEM4_MEMHOLD4_4               0x00100000U        /*!<Bit 4 */
-#define  FSMC_PMEM4_MEMHOLD4_5               0x00200000U        /*!<Bit 5 */
-#define  FSMC_PMEM4_MEMHOLD4_6               0x00400000U        /*!<Bit 6 */
-#define  FSMC_PMEM4_MEMHOLD4_7               0x00800000U        /*!<Bit 7 */
-
-#define  FSMC_PMEM4_MEMHIZ4                  0xFF000000U        /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
-#define  FSMC_PMEM4_MEMHIZ4_0                0x01000000U        /*!<Bit 0 */
-#define  FSMC_PMEM4_MEMHIZ4_1                0x02000000U        /*!<Bit 1 */
-#define  FSMC_PMEM4_MEMHIZ4_2                0x04000000U        /*!<Bit 2 */
-#define  FSMC_PMEM4_MEMHIZ4_3                0x08000000U        /*!<Bit 3 */
-#define  FSMC_PMEM4_MEMHIZ4_4                0x10000000U        /*!<Bit 4 */
-#define  FSMC_PMEM4_MEMHIZ4_5                0x20000000U        /*!<Bit 5 */
-#define  FSMC_PMEM4_MEMHIZ4_6                0x40000000U        /*!<Bit 6 */
-#define  FSMC_PMEM4_MEMHIZ4_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FSMC_PATT2 register  ******************/
-#define  FSMC_PATT2_ATTSET2                  0x000000FFU        /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
-#define  FSMC_PATT2_ATTSET2_0                0x00000001U        /*!<Bit 0 */
-#define  FSMC_PATT2_ATTSET2_1                0x00000002U        /*!<Bit 1 */
-#define  FSMC_PATT2_ATTSET2_2                0x00000004U        /*!<Bit 2 */
-#define  FSMC_PATT2_ATTSET2_3                0x00000008U        /*!<Bit 3 */
-#define  FSMC_PATT2_ATTSET2_4                0x00000010U        /*!<Bit 4 */
-#define  FSMC_PATT2_ATTSET2_5                0x00000020U        /*!<Bit 5 */
-#define  FSMC_PATT2_ATTSET2_6                0x00000040U        /*!<Bit 6 */
-#define  FSMC_PATT2_ATTSET2_7                0x00000080U        /*!<Bit 7 */
-
-#define  FSMC_PATT2_ATTWAIT2                 0x0000FF00U        /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
-#define  FSMC_PATT2_ATTWAIT2_0               0x00000100U        /*!<Bit 0 */
-#define  FSMC_PATT2_ATTWAIT2_1               0x00000200U        /*!<Bit 1 */
-#define  FSMC_PATT2_ATTWAIT2_2               0x00000400U        /*!<Bit 2 */
-#define  FSMC_PATT2_ATTWAIT2_3               0x00000800U        /*!<Bit 3 */
-#define  FSMC_PATT2_ATTWAIT2_4               0x00001000U        /*!<Bit 4 */
-#define  FSMC_PATT2_ATTWAIT2_5               0x00002000U        /*!<Bit 5 */
-#define  FSMC_PATT2_ATTWAIT2_6               0x00004000U        /*!<Bit 6 */
-#define  FSMC_PATT2_ATTWAIT2_7               0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_PATT2_ATTHOLD2                 0x00FF0000U        /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
-#define  FSMC_PATT2_ATTHOLD2_0               0x00010000U        /*!<Bit 0 */
-#define  FSMC_PATT2_ATTHOLD2_1               0x00020000U        /*!<Bit 1 */
-#define  FSMC_PATT2_ATTHOLD2_2               0x00040000U        /*!<Bit 2 */
-#define  FSMC_PATT2_ATTHOLD2_3               0x00080000U        /*!<Bit 3 */
-#define  FSMC_PATT2_ATTHOLD2_4               0x00100000U        /*!<Bit 4 */
-#define  FSMC_PATT2_ATTHOLD2_5               0x00200000U        /*!<Bit 5 */
-#define  FSMC_PATT2_ATTHOLD2_6               0x00400000U        /*!<Bit 6 */
-#define  FSMC_PATT2_ATTHOLD2_7               0x00800000U        /*!<Bit 7 */
-
-#define  FSMC_PATT2_ATTHIZ2                  0xFF000000U        /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
-#define  FSMC_PATT2_ATTHIZ2_0                0x01000000U        /*!<Bit 0 */
-#define  FSMC_PATT2_ATTHIZ2_1                0x02000000U        /*!<Bit 1 */
-#define  FSMC_PATT2_ATTHIZ2_2                0x04000000U        /*!<Bit 2 */
-#define  FSMC_PATT2_ATTHIZ2_3                0x08000000U        /*!<Bit 3 */
-#define  FSMC_PATT2_ATTHIZ2_4                0x10000000U        /*!<Bit 4 */
-#define  FSMC_PATT2_ATTHIZ2_5                0x20000000U        /*!<Bit 5 */
-#define  FSMC_PATT2_ATTHIZ2_6                0x40000000U        /*!<Bit 6 */
-#define  FSMC_PATT2_ATTHIZ2_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FSMC_PATT3 register  ******************/
-#define  FSMC_PATT3_ATTSET3                  0x000000FFU        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
-#define  FSMC_PATT3_ATTSET3_0                0x00000001U        /*!<Bit 0 */
-#define  FSMC_PATT3_ATTSET3_1                0x00000002U        /*!<Bit 1 */
-#define  FSMC_PATT3_ATTSET3_2                0x00000004U        /*!<Bit 2 */
-#define  FSMC_PATT3_ATTSET3_3                0x00000008U        /*!<Bit 3 */
-#define  FSMC_PATT3_ATTSET3_4                0x00000010U        /*!<Bit 4 */
-#define  FSMC_PATT3_ATTSET3_5                0x00000020U        /*!<Bit 5 */
-#define  FSMC_PATT3_ATTSET3_6                0x00000040U        /*!<Bit 6 */
-#define  FSMC_PATT3_ATTSET3_7                0x00000080U        /*!<Bit 7 */
-
-#define  FSMC_PATT3_ATTWAIT3                 0x0000FF00U        /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
-#define  FSMC_PATT3_ATTWAIT3_0               0x00000100U        /*!<Bit 0 */
-#define  FSMC_PATT3_ATTWAIT3_1               0x00000200U        /*!<Bit 1 */
-#define  FSMC_PATT3_ATTWAIT3_2               0x00000400U        /*!<Bit 2 */
-#define  FSMC_PATT3_ATTWAIT3_3               0x00000800U        /*!<Bit 3 */
-#define  FSMC_PATT3_ATTWAIT3_4               0x00001000U        /*!<Bit 4 */
-#define  FSMC_PATT3_ATTWAIT3_5               0x00002000U        /*!<Bit 5 */
-#define  FSMC_PATT3_ATTWAIT3_6               0x00004000U        /*!<Bit 6 */
-#define  FSMC_PATT3_ATTWAIT3_7               0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_PATT3_ATTHOLD3                 0x00FF0000U        /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
-#define  FSMC_PATT3_ATTHOLD3_0               0x00010000U        /*!<Bit 0 */
-#define  FSMC_PATT3_ATTHOLD3_1               0x00020000U        /*!<Bit 1 */
-#define  FSMC_PATT3_ATTHOLD3_2               0x00040000U        /*!<Bit 2 */
-#define  FSMC_PATT3_ATTHOLD3_3               0x00080000U        /*!<Bit 3 */
-#define  FSMC_PATT3_ATTHOLD3_4               0x00100000U        /*!<Bit 4 */
-#define  FSMC_PATT3_ATTHOLD3_5               0x00200000U        /*!<Bit 5 */
-#define  FSMC_PATT3_ATTHOLD3_6               0x00400000U        /*!<Bit 6 */
-#define  FSMC_PATT3_ATTHOLD3_7               0x00800000U        /*!<Bit 7 */
-
-#define  FSMC_PATT3_ATTHIZ3                  0xFF000000U        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
-#define  FSMC_PATT3_ATTHIZ3_0                0x01000000U        /*!<Bit 0 */
-#define  FSMC_PATT3_ATTHIZ3_1                0x02000000U        /*!<Bit 1 */
-#define  FSMC_PATT3_ATTHIZ3_2                0x04000000U        /*!<Bit 2 */
-#define  FSMC_PATT3_ATTHIZ3_3                0x08000000U        /*!<Bit 3 */
-#define  FSMC_PATT3_ATTHIZ3_4                0x10000000U        /*!<Bit 4 */
-#define  FSMC_PATT3_ATTHIZ3_5                0x20000000U        /*!<Bit 5 */
-#define  FSMC_PATT3_ATTHIZ3_6                0x40000000U        /*!<Bit 6 */
-#define  FSMC_PATT3_ATTHIZ3_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FSMC_PATT4 register  ******************/
-#define  FSMC_PATT4_ATTSET4                  0x000000FFU        /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
-#define  FSMC_PATT4_ATTSET4_0                0x00000001U        /*!<Bit 0 */
-#define  FSMC_PATT4_ATTSET4_1                0x00000002U        /*!<Bit 1 */
-#define  FSMC_PATT4_ATTSET4_2                0x00000004U        /*!<Bit 2 */
-#define  FSMC_PATT4_ATTSET4_3                0x00000008U        /*!<Bit 3 */
-#define  FSMC_PATT4_ATTSET4_4                0x00000010U        /*!<Bit 4 */
-#define  FSMC_PATT4_ATTSET4_5                0x00000020U        /*!<Bit 5 */
-#define  FSMC_PATT4_ATTSET4_6                0x00000040U        /*!<Bit 6 */
-#define  FSMC_PATT4_ATTSET4_7                0x00000080U        /*!<Bit 7 */
-
-#define  FSMC_PATT4_ATTWAIT4                 0x0000FF00U        /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
-#define  FSMC_PATT4_ATTWAIT4_0               0x00000100U        /*!<Bit 0 */
-#define  FSMC_PATT4_ATTWAIT4_1               0x00000200U        /*!<Bit 1 */
-#define  FSMC_PATT4_ATTWAIT4_2               0x00000400U        /*!<Bit 2 */
-#define  FSMC_PATT4_ATTWAIT4_3               0x00000800U        /*!<Bit 3 */
-#define  FSMC_PATT4_ATTWAIT4_4               0x00001000U        /*!<Bit 4 */
-#define  FSMC_PATT4_ATTWAIT4_5               0x00002000U        /*!<Bit 5 */
-#define  FSMC_PATT4_ATTWAIT4_6               0x00004000U        /*!<Bit 6 */
-#define  FSMC_PATT4_ATTWAIT4_7               0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_PATT4_ATTHOLD4                 0x00FF0000U        /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
-#define  FSMC_PATT4_ATTHOLD4_0               0x00010000U        /*!<Bit 0 */
-#define  FSMC_PATT4_ATTHOLD4_1               0x00020000U        /*!<Bit 1 */
-#define  FSMC_PATT4_ATTHOLD4_2               0x00040000U        /*!<Bit 2 */
-#define  FSMC_PATT4_ATTHOLD4_3               0x00080000U        /*!<Bit 3 */
-#define  FSMC_PATT4_ATTHOLD4_4               0x00100000U        /*!<Bit 4 */
-#define  FSMC_PATT4_ATTHOLD4_5               0x00200000U        /*!<Bit 5 */
-#define  FSMC_PATT4_ATTHOLD4_6               0x00400000U        /*!<Bit 6 */
-#define  FSMC_PATT4_ATTHOLD4_7               0x00800000U        /*!<Bit 7 */
-
-#define  FSMC_PATT4_ATTHIZ4                  0xFF000000U        /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
-#define  FSMC_PATT4_ATTHIZ4_0                0x01000000U        /*!<Bit 0 */
-#define  FSMC_PATT4_ATTHIZ4_1                0x02000000U        /*!<Bit 1 */
-#define  FSMC_PATT4_ATTHIZ4_2                0x04000000U        /*!<Bit 2 */
-#define  FSMC_PATT4_ATTHIZ4_3                0x08000000U        /*!<Bit 3 */
-#define  FSMC_PATT4_ATTHIZ4_4                0x10000000U        /*!<Bit 4 */
-#define  FSMC_PATT4_ATTHIZ4_5                0x20000000U        /*!<Bit 5 */
-#define  FSMC_PATT4_ATTHIZ4_6                0x40000000U        /*!<Bit 6 */
-#define  FSMC_PATT4_ATTHIZ4_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FSMC_PIO4 register  *******************/
-#define  FSMC_PIO4_IOSET4                    0x000000FFU        /*!<IOSET4[7:0] bits (I/O 4 setup time) */
-#define  FSMC_PIO4_IOSET4_0                  0x00000001U        /*!<Bit 0 */
-#define  FSMC_PIO4_IOSET4_1                  0x00000002U        /*!<Bit 1 */
-#define  FSMC_PIO4_IOSET4_2                  0x00000004U        /*!<Bit 2 */
-#define  FSMC_PIO4_IOSET4_3                  0x00000008U        /*!<Bit 3 */
-#define  FSMC_PIO4_IOSET4_4                  0x00000010U        /*!<Bit 4 */
-#define  FSMC_PIO4_IOSET4_5                  0x00000020U        /*!<Bit 5 */
-#define  FSMC_PIO4_IOSET4_6                  0x00000040U        /*!<Bit 6 */
-#define  FSMC_PIO4_IOSET4_7                  0x00000080U        /*!<Bit 7 */
-
-#define  FSMC_PIO4_IOWAIT4                   0x0000FF00U        /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
-#define  FSMC_PIO4_IOWAIT4_0                 0x00000100U        /*!<Bit 0 */
-#define  FSMC_PIO4_IOWAIT4_1                 0x00000200U        /*!<Bit 1 */
-#define  FSMC_PIO4_IOWAIT4_2                 0x00000400U        /*!<Bit 2 */
-#define  FSMC_PIO4_IOWAIT4_3                 0x00000800U        /*!<Bit 3 */
-#define  FSMC_PIO4_IOWAIT4_4                 0x00001000U        /*!<Bit 4 */
-#define  FSMC_PIO4_IOWAIT4_5                 0x00002000U        /*!<Bit 5 */
-#define  FSMC_PIO4_IOWAIT4_6                 0x00004000U        /*!<Bit 6 */
-#define  FSMC_PIO4_IOWAIT4_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_PIO4_IOHOLD4                   0x00FF0000U        /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
-#define  FSMC_PIO4_IOHOLD4_0                 0x00010000U        /*!<Bit 0 */
-#define  FSMC_PIO4_IOHOLD4_1                 0x00020000U        /*!<Bit 1 */
-#define  FSMC_PIO4_IOHOLD4_2                 0x00040000U        /*!<Bit 2 */
-#define  FSMC_PIO4_IOHOLD4_3                 0x00080000U        /*!<Bit 3 */
-#define  FSMC_PIO4_IOHOLD4_4                 0x00100000U        /*!<Bit 4 */
-#define  FSMC_PIO4_IOHOLD4_5                 0x00200000U        /*!<Bit 5 */
-#define  FSMC_PIO4_IOHOLD4_6                 0x00400000U        /*!<Bit 6 */
-#define  FSMC_PIO4_IOHOLD4_7                 0x00800000U        /*!<Bit 7 */
-
-#define  FSMC_PIO4_IOHIZ4                    0xFF000000U        /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
-#define  FSMC_PIO4_IOHIZ4_0                  0x01000000U        /*!<Bit 0 */
-#define  FSMC_PIO4_IOHIZ4_1                  0x02000000U        /*!<Bit 1 */
-#define  FSMC_PIO4_IOHIZ4_2                  0x04000000U        /*!<Bit 2 */
-#define  FSMC_PIO4_IOHIZ4_3                  0x08000000U        /*!<Bit 3 */
-#define  FSMC_PIO4_IOHIZ4_4                  0x10000000U        /*!<Bit 4 */
-#define  FSMC_PIO4_IOHIZ4_5                  0x20000000U        /*!<Bit 5 */
-#define  FSMC_PIO4_IOHIZ4_6                  0x40000000U        /*!<Bit 6 */
-#define  FSMC_PIO4_IOHIZ4_7                  0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FSMC_ECCR2 register  ******************/
-#define  FSMC_ECCR2_ECC2                     0xFFFFFFFFU        /*!<ECC result */
-
-/******************  Bit definition for FSMC_ECCR3 register  ******************/
-#define  FSMC_ECCR3_ECC3                     0xFFFFFFFFU        /*!<ECC result */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    0x00000003U
-#define GPIO_MODER_MODER0_0                  0x00000001U
-#define GPIO_MODER_MODER0_1                  0x00000002U
-
-#define GPIO_MODER_MODER1                    0x0000000CU
-#define GPIO_MODER_MODER1_0                  0x00000004U
-#define GPIO_MODER_MODER1_1                  0x00000008U
-
-#define GPIO_MODER_MODER2                    0x00000030U
-#define GPIO_MODER_MODER2_0                  0x00000010U
-#define GPIO_MODER_MODER2_1                  0x00000020U
-
-#define GPIO_MODER_MODER3                    0x000000C0U
-#define GPIO_MODER_MODER3_0                  0x00000040U
-#define GPIO_MODER_MODER3_1                  0x00000080U
-
-#define GPIO_MODER_MODER4                    0x00000300U
-#define GPIO_MODER_MODER4_0                  0x00000100U
-#define GPIO_MODER_MODER4_1                  0x00000200U
-
-#define GPIO_MODER_MODER5                    0x00000C00U
-#define GPIO_MODER_MODER5_0                  0x00000400U
-#define GPIO_MODER_MODER5_1                  0x00000800U
-
-#define GPIO_MODER_MODER6                    0x00003000U
-#define GPIO_MODER_MODER6_0                  0x00001000U
-#define GPIO_MODER_MODER6_1                  0x00002000U
-
-#define GPIO_MODER_MODER7                    0x0000C000U
-#define GPIO_MODER_MODER7_0                  0x00004000U
-#define GPIO_MODER_MODER7_1                  0x00008000U
-
-#define GPIO_MODER_MODER8                    0x00030000U
-#define GPIO_MODER_MODER8_0                  0x00010000U
-#define GPIO_MODER_MODER8_1                  0x00020000U
-
-#define GPIO_MODER_MODER9                    0x000C0000U
-#define GPIO_MODER_MODER9_0                  0x00040000U
-#define GPIO_MODER_MODER9_1                  0x00080000U
-
-#define GPIO_MODER_MODER10                   0x00300000U
-#define GPIO_MODER_MODER10_0                 0x00100000U
-#define GPIO_MODER_MODER10_1                 0x00200000U
-
-#define GPIO_MODER_MODER11                   0x00C00000U
-#define GPIO_MODER_MODER11_0                 0x00400000U
-#define GPIO_MODER_MODER11_1                 0x00800000U
-
-#define GPIO_MODER_MODER12                   0x03000000U
-#define GPIO_MODER_MODER12_0                 0x01000000U
-#define GPIO_MODER_MODER12_1                 0x02000000U
-
-#define GPIO_MODER_MODER13                   0x0C000000U
-#define GPIO_MODER_MODER13_0                 0x04000000U
-#define GPIO_MODER_MODER13_1                 0x08000000U
-
-#define GPIO_MODER_MODER14                   0x30000000U
-#define GPIO_MODER_MODER14_0                 0x10000000U
-#define GPIO_MODER_MODER14_1                 0x20000000U
-
-#define GPIO_MODER_MODER15                   0xC0000000U
-#define GPIO_MODER_MODER15_0                 0x40000000U
-#define GPIO_MODER_MODER15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     0x00000001U
-#define GPIO_OTYPER_OT_1                     0x00000002U
-#define GPIO_OTYPER_OT_2                     0x00000004U
-#define GPIO_OTYPER_OT_3                     0x00000008U
-#define GPIO_OTYPER_OT_4                     0x00000010U
-#define GPIO_OTYPER_OT_5                     0x00000020U
-#define GPIO_OTYPER_OT_6                     0x00000040U
-#define GPIO_OTYPER_OT_7                     0x00000080U
-#define GPIO_OTYPER_OT_8                     0x00000100U
-#define GPIO_OTYPER_OT_9                     0x00000200U
-#define GPIO_OTYPER_OT_10                    0x00000400U
-#define GPIO_OTYPER_OT_11                    0x00000800U
-#define GPIO_OTYPER_OT_12                    0x00001000U
-#define GPIO_OTYPER_OT_13                    0x00002000U
-#define GPIO_OTYPER_OT_14                    0x00004000U
-#define GPIO_OTYPER_OT_15                    0x00008000U
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
-#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
-#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
-
-#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
-#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
-#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
-
-#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
-#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
-#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
-
-#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
-#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
-#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
-
-#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
-#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
-#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
-
-#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
-#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
-#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
-
-#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
-#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
-#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
-
-#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
-#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
-#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
-
-#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
-#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
-#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
-
-#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
-#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
-#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
-
-#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
-#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
-#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
-
-#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
-#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
-#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
-
-#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
-#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
-#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
-
-#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
-#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
-#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
-
-#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
-#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
-#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
-
-#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
-#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
-#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    0x00000003U
-#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
-#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
-
-#define GPIO_PUPDR_PUPDR1                    0x0000000CU
-#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
-#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
-
-#define GPIO_PUPDR_PUPDR2                    0x00000030U
-#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
-#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
-
-#define GPIO_PUPDR_PUPDR3                    0x000000C0U
-#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
-#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
-
-#define GPIO_PUPDR_PUPDR4                    0x00000300U
-#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
-#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
-
-#define GPIO_PUPDR_PUPDR5                    0x00000C00U
-#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
-#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
-
-#define GPIO_PUPDR_PUPDR6                    0x00003000U
-#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
-#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
-
-#define GPIO_PUPDR_PUPDR7                    0x0000C000U
-#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
-#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
-
-#define GPIO_PUPDR_PUPDR8                    0x00030000U
-#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
-#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
-
-#define GPIO_PUPDR_PUPDR9                    0x000C0000U
-#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
-#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
-
-#define GPIO_PUPDR_PUPDR10                   0x00300000U
-#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
-#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
-
-#define GPIO_PUPDR_PUPDR11                   0x00C00000U
-#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
-#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
-
-#define GPIO_PUPDR_PUPDR12                   0x03000000U
-#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
-#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
-
-#define GPIO_PUPDR_PUPDR13                   0x0C000000U
-#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
-#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
-
-#define GPIO_PUPDR_PUPDR14                   0x30000000U
-#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
-#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
-
-#define GPIO_PUPDR_PUPDR15                   0xC0000000U
-#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
-#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       0x00000001U
-#define GPIO_IDR_IDR_1                       0x00000002U
-#define GPIO_IDR_IDR_2                       0x00000004U
-#define GPIO_IDR_IDR_3                       0x00000008U
-#define GPIO_IDR_IDR_4                       0x00000010U
-#define GPIO_IDR_IDR_5                       0x00000020U
-#define GPIO_IDR_IDR_6                       0x00000040U
-#define GPIO_IDR_IDR_7                       0x00000080U
-#define GPIO_IDR_IDR_8                       0x00000100U
-#define GPIO_IDR_IDR_9                       0x00000200U
-#define GPIO_IDR_IDR_10                      0x00000400U
-#define GPIO_IDR_IDR_11                      0x00000800U
-#define GPIO_IDR_IDR_12                      0x00001000U
-#define GPIO_IDR_IDR_13                      0x00002000U
-#define GPIO_IDR_IDR_14                      0x00004000U
-#define GPIO_IDR_IDR_15                      0x00008000U
-/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
-#define GPIO_OTYPER_IDR_0                    GPIO_IDR_IDR_0
-#define GPIO_OTYPER_IDR_1                    GPIO_IDR_IDR_1
-#define GPIO_OTYPER_IDR_2                    GPIO_IDR_IDR_2
-#define GPIO_OTYPER_IDR_3                    GPIO_IDR_IDR_3
-#define GPIO_OTYPER_IDR_4                    GPIO_IDR_IDR_4
-#define GPIO_OTYPER_IDR_5                    GPIO_IDR_IDR_5
-#define GPIO_OTYPER_IDR_6                    GPIO_IDR_IDR_6
-#define GPIO_OTYPER_IDR_7                    GPIO_IDR_IDR_7
-#define GPIO_OTYPER_IDR_8                    GPIO_IDR_IDR_8
-#define GPIO_OTYPER_IDR_9                    GPIO_IDR_IDR_9
-#define GPIO_OTYPER_IDR_10                   GPIO_IDR_IDR_10
-#define GPIO_OTYPER_IDR_11                   GPIO_IDR_IDR_11
-#define GPIO_OTYPER_IDR_12                   GPIO_IDR_IDR_12
-#define GPIO_OTYPER_IDR_13                   GPIO_IDR_IDR_13
-#define GPIO_OTYPER_IDR_14                   GPIO_IDR_IDR_14
-#define GPIO_OTYPER_IDR_15                   GPIO_IDR_IDR_15
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       0x00000001U
-#define GPIO_ODR_ODR_1                       0x00000002U
-#define GPIO_ODR_ODR_2                       0x00000004U
-#define GPIO_ODR_ODR_3                       0x00000008U
-#define GPIO_ODR_ODR_4                       0x00000010U
-#define GPIO_ODR_ODR_5                       0x00000020U
-#define GPIO_ODR_ODR_6                       0x00000040U
-#define GPIO_ODR_ODR_7                       0x00000080U
-#define GPIO_ODR_ODR_8                       0x00000100U
-#define GPIO_ODR_ODR_9                       0x00000200U
-#define GPIO_ODR_ODR_10                      0x00000400U
-#define GPIO_ODR_ODR_11                      0x00000800U
-#define GPIO_ODR_ODR_12                      0x00001000U
-#define GPIO_ODR_ODR_13                      0x00002000U
-#define GPIO_ODR_ODR_14                      0x00004000U
-#define GPIO_ODR_ODR_15                      0x00008000U
-/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
-#define GPIO_OTYPER_ODR_0                    GPIO_ODR_ODR_0
-#define GPIO_OTYPER_ODR_1                    GPIO_ODR_ODR_1
-#define GPIO_OTYPER_ODR_2                    GPIO_ODR_ODR_2
-#define GPIO_OTYPER_ODR_3                    GPIO_ODR_ODR_3
-#define GPIO_OTYPER_ODR_4                    GPIO_ODR_ODR_4
-#define GPIO_OTYPER_ODR_5                    GPIO_ODR_ODR_5
-#define GPIO_OTYPER_ODR_6                    GPIO_ODR_ODR_6
-#define GPIO_OTYPER_ODR_7                    GPIO_ODR_ODR_7
-#define GPIO_OTYPER_ODR_8                    GPIO_ODR_ODR_8
-#define GPIO_OTYPER_ODR_9                    GPIO_ODR_ODR_9
-#define GPIO_OTYPER_ODR_10                   GPIO_ODR_ODR_10
-#define GPIO_OTYPER_ODR_11                   GPIO_ODR_ODR_11
-#define GPIO_OTYPER_ODR_12                   GPIO_ODR_ODR_12
-#define GPIO_OTYPER_ODR_13                   GPIO_ODR_ODR_13
-#define GPIO_OTYPER_ODR_14                   GPIO_ODR_ODR_14
-#define GPIO_OTYPER_ODR_15                   GPIO_ODR_ODR_15
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       0x00000001U
-#define GPIO_BSRR_BS_1                       0x00000002U
-#define GPIO_BSRR_BS_2                       0x00000004U
-#define GPIO_BSRR_BS_3                       0x00000008U
-#define GPIO_BSRR_BS_4                       0x00000010U
-#define GPIO_BSRR_BS_5                       0x00000020U
-#define GPIO_BSRR_BS_6                       0x00000040U
-#define GPIO_BSRR_BS_7                       0x00000080U
-#define GPIO_BSRR_BS_8                       0x00000100U
-#define GPIO_BSRR_BS_9                       0x00000200U
-#define GPIO_BSRR_BS_10                      0x00000400U
-#define GPIO_BSRR_BS_11                      0x00000800U
-#define GPIO_BSRR_BS_12                      0x00001000U
-#define GPIO_BSRR_BS_13                      0x00002000U
-#define GPIO_BSRR_BS_14                      0x00004000U
-#define GPIO_BSRR_BS_15                      0x00008000U
-#define GPIO_BSRR_BR_0                       0x00010000U
-#define GPIO_BSRR_BR_1                       0x00020000U
-#define GPIO_BSRR_BR_2                       0x00040000U
-#define GPIO_BSRR_BR_3                       0x00080000U
-#define GPIO_BSRR_BR_4                       0x00100000U
-#define GPIO_BSRR_BR_5                       0x00200000U
-#define GPIO_BSRR_BR_6                       0x00400000U
-#define GPIO_BSRR_BR_7                       0x00800000U
-#define GPIO_BSRR_BR_8                       0x01000000U
-#define GPIO_BSRR_BR_9                       0x02000000U
-#define GPIO_BSRR_BR_10                      0x04000000U
-#define GPIO_BSRR_BR_11                      0x08000000U
-#define GPIO_BSRR_BR_12                      0x10000000U
-#define GPIO_BSRR_BR_13                      0x20000000U
-#define GPIO_BSRR_BR_14                      0x40000000U
-#define GPIO_BSRR_BR_15                      0x80000000U
-
-/****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0                       0x00000001U
-#define GPIO_LCKR_LCK1                       0x00000002U
-#define GPIO_LCKR_LCK2                       0x00000004U
-#define GPIO_LCKR_LCK3                       0x00000008U
-#define GPIO_LCKR_LCK4                       0x00000010U
-#define GPIO_LCKR_LCK5                       0x00000020U
-#define GPIO_LCKR_LCK6                       0x00000040U
-#define GPIO_LCKR_LCK7                       0x00000080U
-#define GPIO_LCKR_LCK8                       0x00000100U
-#define GPIO_LCKR_LCK9                       0x00000200U
-#define GPIO_LCKR_LCK10                      0x00000400U
-#define GPIO_LCKR_LCK11                      0x00000800U
-#define GPIO_LCKR_LCK12                      0x00001000U
-#define GPIO_LCKR_LCK13                      0x00002000U
-#define GPIO_LCKR_LCK14                      0x00004000U
-#define GPIO_LCKR_LCK15                      0x00008000U
-#define GPIO_LCKR_LCKK                       0x00010000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    HASH                                    */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for HASH_CR register  ********************/
-#define HASH_CR_INIT                         0x00000004U
-#define HASH_CR_DMAE                         0x00000008U
-#define HASH_CR_DATATYPE                     0x00000030U
-#define HASH_CR_DATATYPE_0                   0x00000010U
-#define HASH_CR_DATATYPE_1                   0x00000020U
-#define HASH_CR_MODE                         0x00000040U
-#define HASH_CR_ALGO                         0x00040080U
-#define HASH_CR_ALGO_0                       0x00000080U
-#define HASH_CR_ALGO_1                       0x00040000U
-#define HASH_CR_NBW                          0x00000F00U
-#define HASH_CR_NBW_0                        0x00000100U
-#define HASH_CR_NBW_1                        0x00000200U
-#define HASH_CR_NBW_2                        0x00000400U
-#define HASH_CR_NBW_3                        0x00000800U
-#define HASH_CR_DINNE                        0x00001000U
-#define HASH_CR_MDMAT                        0x00002000U
-#define HASH_CR_LKEY                         0x00010000U
-
-/******************  Bits definition for HASH_STR register  *******************/
-#define HASH_STR_NBLW                        0x0000001FU
-#define HASH_STR_NBLW_0                      0x00000001U
-#define HASH_STR_NBLW_1                      0x00000002U
-#define HASH_STR_NBLW_2                      0x00000004U
-#define HASH_STR_NBLW_3                      0x00000008U
-#define HASH_STR_NBLW_4                      0x00000010U
-#define HASH_STR_DCAL                        0x00000100U
-/* Aliases for HASH_STR register */
-#define HASH_STR_NBW                         HASH_STR_NBLW
-#define HASH_STR_NBW_0                       HASH_STR_NBLW_0
-#define HASH_STR_NBW_1                       HASH_STR_NBLW_1
-#define HASH_STR_NBW_2                       HASH_STR_NBLW_2
-#define HASH_STR_NBW_3                       HASH_STR_NBLW_3
-#define HASH_STR_NBW_4                       HASH_STR_NBLW_4
-
-/******************  Bits definition for HASH_IMR register  *******************/
-#define HASH_IMR_DINIE                       0x00000001U
-#define HASH_IMR_DCIE                        0x00000002U
-/* Aliases for HASH_IMR register */
-#define HASH_IMR_DINIM                       HASH_IMR_DINIE
-#define HASH_IMR_DCIM                        HASH_IMR_DCIE
-
-/******************  Bits definition for HASH_SR register  ********************/
-#define HASH_SR_DINIS                        0x00000001U
-#define HASH_SR_DCIS                         0x00000002U
-#define HASH_SR_DMAS                         0x00000004U
-#define HASH_SR_BUSY                         0x00000008U
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Inter-integrated Circuit Interface                    */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          0x00000001U     /*!<Peripheral Enable                             */
-#define  I2C_CR1_SMBUS                       0x00000002U     /*!<SMBus Mode                                    */
-#define  I2C_CR1_SMBTYPE                     0x00000008U     /*!<SMBus Type                                    */
-#define  I2C_CR1_ENARP                       0x00000010U     /*!<ARP Enable                                    */
-#define  I2C_CR1_ENPEC                       0x00000020U     /*!<PEC Enable                                    */
-#define  I2C_CR1_ENGC                        0x00000040U     /*!<General Call Enable                           */
-#define  I2C_CR1_NOSTRETCH                   0x00000080U     /*!<Clock Stretching Disable (Slave mode)  */
-#define  I2C_CR1_START                       0x00000100U     /*!<Start Generation                              */
-#define  I2C_CR1_STOP                        0x00000200U     /*!<Stop Generation                               */
-#define  I2C_CR1_ACK                         0x00000400U     /*!<Acknowledge Enable                            */
-#define  I2C_CR1_POS                         0x00000800U     /*!<Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         0x00001000U     /*!<Packet Error Checking                         */
-#define  I2C_CR1_ALERT                       0x00002000U     /*!<SMBus Alert                                   */
-#define  I2C_CR1_SWRST                       0x00008000U     /*!<Software Reset                                */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        0x0000003FU     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
-#define  I2C_CR2_FREQ_0                      0x00000001U     /*!<Bit 0 */
-#define  I2C_CR2_FREQ_1                      0x00000002U     /*!<Bit 1 */
-#define  I2C_CR2_FREQ_2                      0x00000004U     /*!<Bit 2 */
-#define  I2C_CR2_FREQ_3                      0x00000008U     /*!<Bit 3 */
-#define  I2C_CR2_FREQ_4                      0x00000010U     /*!<Bit 4 */
-#define  I2C_CR2_FREQ_5                      0x00000020U     /*!<Bit 5 */
-
-#define  I2C_CR2_ITERREN                     0x00000100U     /*!<Error Interrupt Enable  */
-#define  I2C_CR2_ITEVTEN                     0x00000200U     /*!<Event Interrupt Enable  */
-#define  I2C_CR2_ITBUFEN                     0x00000400U     /*!<Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       0x00000800U     /*!<DMA Requests Enable     */
-#define  I2C_CR2_LAST                        0x00001000U     /*!<DMA Last Transfer       */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     0x000000FEU     /*!<Interface Address */
-#define  I2C_OAR1_ADD8_9                     0x00000300U     /*!<Interface Address */
-
-#define  I2C_OAR1_ADD0                       0x00000001U     /*!<Bit 0 */
-#define  I2C_OAR1_ADD1                       0x00000002U     /*!<Bit 1 */
-#define  I2C_OAR1_ADD2                       0x00000004U     /*!<Bit 2 */
-#define  I2C_OAR1_ADD3                       0x00000008U     /*!<Bit 3 */
-#define  I2C_OAR1_ADD4                       0x00000010U     /*!<Bit 4 */
-#define  I2C_OAR1_ADD5                       0x00000020U     /*!<Bit 5 */
-#define  I2C_OAR1_ADD6                       0x00000040U     /*!<Bit 6 */
-#define  I2C_OAR1_ADD7                       0x00000080U     /*!<Bit 7 */
-#define  I2C_OAR1_ADD8                       0x00000100U     /*!<Bit 8 */
-#define  I2C_OAR1_ADD9                       0x00000200U     /*!<Bit 9 */
-
-#define  I2C_OAR1_ADDMODE                    0x00008000U     /*!<Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     0x00000001U        /*!<Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       0x000000FEU        /*!<Interface address           */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           0x000000FFU        /*!<8-bit Data Register         */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          0x00000001U     /*!<Start Bit (Master mode)                  */
-#define  I2C_SR1_ADDR                        0x00000002U     /*!<Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         0x00000004U     /*!<Byte Transfer Finished                          */
-#define  I2C_SR1_ADD10                       0x00000008U     /*!<10-bit header sent (Master mode)         */
-#define  I2C_SR1_STOPF                       0x00000010U     /*!<Stop detection (Slave mode)              */
-#define  I2C_SR1_RXNE                        0x00000040U     /*!<Data Register not Empty (receivers)      */
-#define  I2C_SR1_TXE                         0x00000080U     /*!<Data Register Empty (transmitters)       */
-#define  I2C_SR1_BERR                        0x00000100U     /*!<Bus Error                                       */
-#define  I2C_SR1_ARLO                        0x00000200U     /*!<Arbitration Lost (master mode)           */
-#define  I2C_SR1_AF                          0x00000400U     /*!<Acknowledge Failure                             */
-#define  I2C_SR1_OVR                         0x00000800U     /*!<Overrun/Underrun                                */
-#define  I2C_SR1_PECERR                      0x00001000U     /*!<PEC Error in reception                          */
-#define  I2C_SR1_TIMEOUT                     0x00004000U     /*!<Timeout or Tlow Error                           */
-#define  I2C_SR1_SMBALERT                    0x00008000U     /*!<SMBus Alert                                     */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         0x00000001U     /*!<Master/Slave                              */
-#define  I2C_SR2_BUSY                        0x00000002U     /*!<Bus Busy                                  */
-#define  I2C_SR2_TRA                         0x00000004U     /*!<Transmitter/Receiver                      */
-#define  I2C_SR2_GENCALL                     0x00000010U     /*!<General Call Address (Slave mode)  */
-#define  I2C_SR2_SMBDEFAULT                  0x00000020U     /*!<SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     0x00000040U     /*!<SMBus Host Header (Slave mode)     */
-#define  I2C_SR2_DUALF                       0x00000080U     /*!<Dual Flag (Slave mode)             */
-#define  I2C_SR2_PEC                         0x0000FF00U     /*!<Packet Error Checking Register            */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         0x00000FFFU     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        0x00004000U     /*!<Fast Mode Duty Cycle                                       */
-#define  I2C_CCR_FS                          0x00008000U     /*!<I2C Master Mode Selection                                  */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     0x0000003FU     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************  Bit definition for I2C_FLTR register  *******************/
-#define  I2C_FLTR_DNF                        0x0000000FU     /*!<Digital Noise Filter */
-#define  I2C_FLTR_ANOFF                      0x00000010U     /*!<Analog Noise Filter OFF */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Independent WATCHDOG                             */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         0x01U               /*!<Watchdog prescaler value update      */
-#define  IWDG_SR_RVU                         0x02U               /*!<Watchdog counter reload value update */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                             Power Control                                  */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
-#define  PWR_CR_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
-#define  PWR_CR_CWUF                         0x00000004U     /*!< Clear Wakeup Flag                   */
-#define  PWR_CR_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
-#define  PWR_CR_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
-
-#define  PWR_CR_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        0x00000020U     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        0x00000040U     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        0x00000080U     /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
-
-#define  PWR_CR_DBP                          0x00000100U     /*!< Disable Backup Domain write protection               */
-#define  PWR_CR_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                        */
-#define  PWR_CR_VOS                          0x00004000U     /*!< VOS bit (Regulator voltage scaling output selection) */
-
-/* Legacy define */
-#define  PWR_CR_PMODE                        PWR_CR_VOS
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         0x00000001U     /*!< Wakeup Flag                                      */
-#define  PWR_CSR_SBF                         0x00000002U     /*!< Standby Flag                                     */
-#define  PWR_CSR_PVDO                        0x00000004U     /*!< PVD Output                                       */
-#define  PWR_CSR_BRR                         0x00000008U     /*!< Backup regulator ready                           */
-#define  PWR_CSR_EWUP                        0x00000100U     /*!< Enable WKUP pin                                  */
-#define  PWR_CSR_BRE                         0x00000200U     /*!< Backup regulator enable                          */
-#define  PWR_CSR_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
-
-/* Legacy define */
-#define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        0x00000001U
-#define  RCC_CR_HSIRDY                       0x00000002U
-
-#define  RCC_CR_HSITRIM                      0x000000F8U
-#define  RCC_CR_HSITRIM_0                    0x00000008U/*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    0x00000010U/*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    0x00000020U/*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    0x00000040U/*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    0x00000080U/*!<Bit 4 */
-
-#define  RCC_CR_HSICAL                       0x0000FF00U
-#define  RCC_CR_HSICAL_0                     0x00000100U/*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     0x00000200U/*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     0x00000400U/*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     0x00000800U/*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     0x00001000U/*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     0x00002000U/*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     0x00004000U/*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     0x00008000U/*!<Bit 7 */
-
-#define  RCC_CR_HSEON                        0x00010000U
-#define  RCC_CR_HSERDY                       0x00020000U
-#define  RCC_CR_HSEBYP                       0x00040000U
-#define  RCC_CR_CSSON                        0x00080000U
-#define  RCC_CR_PLLON                        0x01000000U
-#define  RCC_CR_PLLRDY                       0x02000000U
-#define  RCC_CR_PLLI2SON                     0x04000000U
-#define  RCC_CR_PLLI2SRDY                    0x08000000U
-
-/********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    0x0000003FU
-#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
-#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
-#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
-#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
-#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
-#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
-
-#define  RCC_PLLCFGR_PLLN                     0x00007FC0U
-#define  RCC_PLLCFGR_PLLN_0                   0x00000040U
-#define  RCC_PLLCFGR_PLLN_1                   0x00000080U
-#define  RCC_PLLCFGR_PLLN_2                   0x00000100U
-#define  RCC_PLLCFGR_PLLN_3                   0x00000200U
-#define  RCC_PLLCFGR_PLLN_4                   0x00000400U
-#define  RCC_PLLCFGR_PLLN_5                   0x00000800U
-#define  RCC_PLLCFGR_PLLN_6                   0x00001000U
-#define  RCC_PLLCFGR_PLLN_7                   0x00002000U
-#define  RCC_PLLCFGR_PLLN_8                   0x00004000U
-
-#define  RCC_PLLCFGR_PLLP                    0x00030000U
-#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
-#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
-
-#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
-
-#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
-#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
-#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
-#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
-#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-/*!< SW configuration */
-#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
-
-#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
-
-#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
-
-#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
-
-/*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     0x001F0000U
-#define  RCC_CFGR_RTCPRE_0                   0x00010000U
-#define  RCC_CFGR_RTCPRE_1                   0x00020000U
-#define  RCC_CFGR_RTCPRE_2                   0x00040000U
-#define  RCC_CFGR_RTCPRE_3                   0x00080000U
-#define  RCC_CFGR_RTCPRE_4                   0x00100000U
-
-/*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       0x00600000U
-#define  RCC_CFGR_MCO1_0                     0x00200000U
-#define  RCC_CFGR_MCO1_1                     0x00400000U
-
-#define  RCC_CFGR_I2SSRC                     0x00800000U
-
-#define  RCC_CFGR_MCO1PRE                    0x07000000U
-#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
-#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
-#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
-
-#define  RCC_CFGR_MCO2PRE                    0x38000000U
-#define  RCC_CFGR_MCO2PRE_0                  0x08000000U
-#define  RCC_CFGR_MCO2PRE_1                  0x10000000U
-#define  RCC_CFGR_MCO2PRE_2                  0x20000000U
-
-#define  RCC_CFGR_MCO2                       0xC0000000U
-#define  RCC_CFGR_MCO2_0                     0x40000000U
-#define  RCC_CFGR_MCO2_1                     0x80000000U
-
-/********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     0x00000001U
-#define  RCC_CIR_LSERDYF                     0x00000002U
-#define  RCC_CIR_HSIRDYF                     0x00000004U
-#define  RCC_CIR_HSERDYF                     0x00000008U
-#define  RCC_CIR_PLLRDYF                     0x00000010U
-#define  RCC_CIR_PLLI2SRDYF                  0x00000020U
-
-#define  RCC_CIR_CSSF                        0x00000080U
-#define  RCC_CIR_LSIRDYIE                    0x00000100U
-#define  RCC_CIR_LSERDYIE                    0x00000200U
-#define  RCC_CIR_HSIRDYIE                    0x00000400U
-#define  RCC_CIR_HSERDYIE                    0x00000800U
-#define  RCC_CIR_PLLRDYIE                    0x00001000U
-#define  RCC_CIR_PLLI2SRDYIE                 0x00002000U
-
-#define  RCC_CIR_LSIRDYC                     0x00010000U
-#define  RCC_CIR_LSERDYC                     0x00020000U
-#define  RCC_CIR_HSIRDYC                     0x00040000U
-#define  RCC_CIR_HSERDYC                     0x00080000U
-#define  RCC_CIR_PLLRDYC                     0x00100000U
-#define  RCC_CIR_PLLI2SRDYC                  0x00200000U
-
-#define  RCC_CIR_CSSC                        0x00800000U
-
-/********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
-#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
-#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
-#define  RCC_AHB1RSTR_GPIODRST               0x00000008U
-#define  RCC_AHB1RSTR_GPIOERST               0x00000010U
-#define  RCC_AHB1RSTR_GPIOFRST               0x00000020U
-#define  RCC_AHB1RSTR_GPIOGRST               0x00000040U
-#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
-#define  RCC_AHB1RSTR_GPIOIRST               0x00000100U
-#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
-#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
-#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
-#define  RCC_AHB1RSTR_OTGHRST                0x20000000U
-
-/********************  Bit definition for RCC_AHB2RSTR register  **************/
-#define  RCC_AHB2RSTR_CRYPRST                0x00000010U
-#define  RCC_AHB2RSTR_HASHRST                0x00000020U
- /* maintained for legacy purpose */
- #define  RCC_AHB2RSTR_HSAHRST                RCC_AHB2RSTR_HASHRST
-#define  RCC_AHB2RSTR_RNGRST                 0x00000040U
-#define  RCC_AHB2RSTR_OTGFSRST               0x00000080U
-
-/********************  Bit definition for RCC_AHB3RSTR register  **************/
-
-#define  RCC_AHB3RSTR_FSMCRST                0x00000001U
-
-/********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM2RST                0x00000001U
-#define  RCC_APB1RSTR_TIM3RST                0x00000002U
-#define  RCC_APB1RSTR_TIM4RST                0x00000004U
-#define  RCC_APB1RSTR_TIM5RST                0x00000008U
-#define  RCC_APB1RSTR_TIM6RST                0x00000010U
-#define  RCC_APB1RSTR_TIM7RST                0x00000020U
-#define  RCC_APB1RSTR_TIM12RST               0x00000040U
-#define  RCC_APB1RSTR_TIM13RST               0x00000080U
-#define  RCC_APB1RSTR_TIM14RST               0x00000100U
-#define  RCC_APB1RSTR_WWDGRST                0x00000800U
-#define  RCC_APB1RSTR_SPI2RST                0x00004000U
-#define  RCC_APB1RSTR_SPI3RST                0x00008000U
-#define  RCC_APB1RSTR_USART2RST              0x00020000U
-#define  RCC_APB1RSTR_USART3RST              0x00040000U
-#define  RCC_APB1RSTR_UART4RST               0x00080000U
-#define  RCC_APB1RSTR_UART5RST               0x00100000U
-#define  RCC_APB1RSTR_I2C1RST                0x00200000U
-#define  RCC_APB1RSTR_I2C2RST                0x00400000U
-#define  RCC_APB1RSTR_I2C3RST                0x00800000U
-#define  RCC_APB1RSTR_CAN1RST                0x02000000U
-#define  RCC_APB1RSTR_CAN2RST                0x04000000U
-#define  RCC_APB1RSTR_PWRRST                 0x10000000U
-#define  RCC_APB1RSTR_DACRST                 0x20000000U
-
-/********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                0x00000001U
-#define  RCC_APB2RSTR_TIM8RST                0x00000002U
-#define  RCC_APB2RSTR_USART1RST              0x00000010U
-#define  RCC_APB2RSTR_USART6RST              0x00000020U
-#define  RCC_APB2RSTR_ADCRST                 0x00000100U
-#define  RCC_APB2RSTR_SDIORST                0x00000800U
-#define  RCC_APB2RSTR_SPI1RST                0x00001000U
-#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
-#define  RCC_APB2RSTR_TIM9RST                0x00010000U
-#define  RCC_APB2RSTR_TIM10RST               0x00020000U
-#define  RCC_APB2RSTR_TIM11RST               0x00040000U
-
-/* Old SPI1RST bit definition, maintained for legacy purpose */
-#define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
-
-/********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
-#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
-#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
-#define  RCC_AHB1ENR_GPIODEN                 0x00000008U
-#define  RCC_AHB1ENR_GPIOEEN                 0x00000010U
-#define  RCC_AHB1ENR_GPIOFEN                 0x00000020U
-#define  RCC_AHB1ENR_GPIOGEN                 0x00000040U
-#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
-#define  RCC_AHB1ENR_GPIOIEN                 0x00000100U
-#define  RCC_AHB1ENR_CRCEN                   0x00001000U
-#define  RCC_AHB1ENR_BKPSRAMEN               0x00040000U
-#define  RCC_AHB1ENR_CCMDATARAMEN            0x00100000U
-#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
-#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
-
-#define  RCC_AHB1ENR_OTGHSEN                 0x20000000U
-#define  RCC_AHB1ENR_OTGHSULPIEN             0x40000000U
-
-/********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define  RCC_AHB2ENR_CRYPEN                  0x00000010U
-#define  RCC_AHB2ENR_HASHEN                  0x00000020U
-#define  RCC_AHB2ENR_RNGEN                   0x00000040U
-#define  RCC_AHB2ENR_OTGFSEN                 0x00000080U
-
-/********************  Bit definition for RCC_AHB3ENR register  ***************/
-
-#define  RCC_AHB3ENR_FSMCEN                  0x00000001U
-
-/********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM2EN                  0x00000001U
-#define  RCC_APB1ENR_TIM3EN                  0x00000002U
-#define  RCC_APB1ENR_TIM4EN                  0x00000004U
-#define  RCC_APB1ENR_TIM5EN                  0x00000008U
-#define  RCC_APB1ENR_TIM6EN                  0x00000010U
-#define  RCC_APB1ENR_TIM7EN                  0x00000020U
-#define  RCC_APB1ENR_TIM12EN                 0x00000040U
-#define  RCC_APB1ENR_TIM13EN                 0x00000080U
-#define  RCC_APB1ENR_TIM14EN                 0x00000100U
-#define  RCC_APB1ENR_WWDGEN                  0x00000800U
-#define  RCC_APB1ENR_SPI2EN                  0x00004000U
-#define  RCC_APB1ENR_SPI3EN                  0x00008000U
-#define  RCC_APB1ENR_USART2EN                0x00020000U
-#define  RCC_APB1ENR_USART3EN                0x00040000U
-#define  RCC_APB1ENR_UART4EN                 0x00080000U
-#define  RCC_APB1ENR_UART5EN                 0x00100000U
-#define  RCC_APB1ENR_I2C1EN                  0x00200000U
-#define  RCC_APB1ENR_I2C2EN                  0x00400000U
-#define  RCC_APB1ENR_I2C3EN                  0x00800000U
-#define  RCC_APB1ENR_CAN1EN                  0x02000000U
-#define  RCC_APB1ENR_CAN2EN                  0x04000000U
-#define  RCC_APB1ENR_PWREN                   0x10000000U
-#define  RCC_APB1ENR_DACEN                   0x20000000U
-
-/********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  0x00000001U
-#define  RCC_APB2ENR_TIM8EN                  0x00000002U
-#define  RCC_APB2ENR_USART1EN                0x00000010U
-#define  RCC_APB2ENR_USART6EN                0x00000020U
-#define  RCC_APB2ENR_ADC1EN                  0x00000100U
-#define  RCC_APB2ENR_ADC2EN                  0x00000200U
-#define  RCC_APB2ENR_ADC3EN                  0x00000400U
-#define  RCC_APB2ENR_SDIOEN                  0x00000800U
-#define  RCC_APB2ENR_SPI1EN                  0x00001000U
-#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
-#define  RCC_APB2ENR_TIM9EN                  0x00010000U
-#define  RCC_APB2ENR_TIM10EN                 0x00020000U
-#define  RCC_APB2ENR_TIM11EN                 0x00040000U
-#define  RCC_APB2ENR_SPI5EN                  0x00100000U
-#define  RCC_APB2ENR_SPI6EN                  0x00200000U
-
-/********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
-#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
-#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
-#define  RCC_AHB1LPENR_GPIODLPEN             0x00000008U
-#define  RCC_AHB1LPENR_GPIOELPEN             0x00000010U
-#define  RCC_AHB1LPENR_GPIOFLPEN             0x00000020U
-#define  RCC_AHB1LPENR_GPIOGLPEN             0x00000040U
-#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
-#define  RCC_AHB1LPENR_GPIOILPEN             0x00000100U
-#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
-#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
-#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
-#define  RCC_AHB1LPENR_SRAM2LPEN             0x00020000U
-#define  RCC_AHB1LPENR_BKPSRAMLPEN           0x00040000U
-#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
-#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
-#define  RCC_AHB1LPENR_OTGHSLPEN             0x20000000U
-#define  RCC_AHB1LPENR_OTGHSULPILPEN         0x40000000U
-
-/********************  Bit definition for RCC_AHB2LPENR register  *************/
-#define  RCC_AHB2LPENR_CRYPLPEN              0x00000010U
-#define  RCC_AHB2LPENR_HASHLPEN              0x00000020U
-#define  RCC_AHB2LPENR_RNGLPEN               0x00000040U
-#define  RCC_AHB2LPENR_OTGFSLPEN             0x00000080U
-
-/********************  Bit definition for RCC_AHB3LPENR register  *************/
-
-#define  RCC_AHB3LPENR_FSMCLPEN              0x00000001U
-
-/********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM2LPEN              0x00000001U
-#define  RCC_APB1LPENR_TIM3LPEN              0x00000002U
-#define  RCC_APB1LPENR_TIM4LPEN              0x00000004U
-#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
-#define  RCC_APB1LPENR_TIM6LPEN              0x00000010U
-#define  RCC_APB1LPENR_TIM7LPEN              0x00000020U
-#define  RCC_APB1LPENR_TIM12LPEN             0x00000040U
-#define  RCC_APB1LPENR_TIM13LPEN             0x00000080U
-#define  RCC_APB1LPENR_TIM14LPEN             0x00000100U
-#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
-#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U
-#define  RCC_APB1LPENR_SPI3LPEN              0x00008000U
-#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
-#define  RCC_APB1LPENR_USART3LPEN            0x00040000U
-#define  RCC_APB1LPENR_UART4LPEN             0x00080000U
-#define  RCC_APB1LPENR_UART5LPEN             0x00100000U
-#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
-#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
-#define  RCC_APB1LPENR_I2C3LPEN              0x00800000U
-#define  RCC_APB1LPENR_CAN1LPEN              0x02000000U
-#define  RCC_APB1LPENR_CAN2LPEN              0x04000000U
-#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
-#define  RCC_APB1LPENR_DACLPEN               0x20000000U
-
-/********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
-#define  RCC_APB2LPENR_TIM8LPEN              0x00000002U
-#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
-#define  RCC_APB2LPENR_USART6LPEN            0x00000020U
-#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
-#define  RCC_APB2LPENR_ADC2LPEN              0x00000200U
-#define  RCC_APB2LPENR_ADC3LPEN              0x00000400U
-#define  RCC_APB2LPENR_SDIOLPEN              0x00000800U
-#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
-#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
-#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
-#define  RCC_APB2LPENR_TIM10LPEN             0x00020000U
-#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
-
-/********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      0x00000001U
-#define  RCC_BDCR_LSERDY                     0x00000002U
-#define  RCC_BDCR_LSEBYP                     0x00000004U
-
-#define  RCC_BDCR_RTCSEL                    0x00000300U
-#define  RCC_BDCR_RTCSEL_0                  0x00000100U
-#define  RCC_BDCR_RTCSEL_1                  0x00000200U
-
-#define  RCC_BDCR_RTCEN                      0x00008000U
-#define  RCC_BDCR_BDRST                      0x00010000U
-
-/********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       0x00000001U
-#define  RCC_CSR_LSIRDY                      0x00000002U
-#define  RCC_CSR_RMVF                        0x01000000U
-#define  RCC_CSR_BORRSTF                     0x02000000U
-#define  RCC_CSR_PADRSTF                     0x04000000U
-#define  RCC_CSR_PORRSTF                     0x08000000U
-#define  RCC_CSR_SFTRSTF                     0x10000000U
-#define  RCC_CSR_WDGRSTF                     0x20000000U
-#define  RCC_CSR_WWDGRSTF                    0x40000000U
-#define  RCC_CSR_LPWRRSTF                    0x80000000U
-
-/********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    0x00001FFFU
-#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
-#define  RCC_SSCGR_SPREADSEL                 0x40000000U
-#define  RCC_SSCGR_SSCGEN                    0x80000000U
-
-/********************  Bit definition for RCC_PLLI2SCFGR register  ************/
-#define  RCC_PLLI2SCFGR_PLLI2SN              0x00007FC0U
-#define  RCC_PLLI2SCFGR_PLLI2SN_0            0x00000040U
-#define  RCC_PLLI2SCFGR_PLLI2SN_1            0x00000080U
-#define  RCC_PLLI2SCFGR_PLLI2SN_2            0x00000100U
-#define  RCC_PLLI2SCFGR_PLLI2SN_3            0x00000200U
-#define  RCC_PLLI2SCFGR_PLLI2SN_4            0x00000400U
-#define  RCC_PLLI2SCFGR_PLLI2SN_5            0x00000800U
-#define  RCC_PLLI2SCFGR_PLLI2SN_6            0x00001000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_7            0x00002000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_8            0x00004000U
-
-#define  RCC_PLLI2SCFGR_PLLI2SR              0x70000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_0            0x10000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_1            0x20000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_2            0x40000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    RNG                                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN                         0x00000004U
-#define RNG_CR_IE                            0x00000008U
-
-/********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY                          0x00000001U
-#define RNG_SR_CECS                          0x00000002U
-#define RNG_SR_SECS                          0x00000004U
-#define RNG_SR_CEIS                          0x00000020U
-#define RNG_SR_SEIS                          0x00000040U
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            0x00400000U
-#define RTC_TR_HT                            0x00300000U
-#define RTC_TR_HT_0                          0x00100000U
-#define RTC_TR_HT_1                          0x00200000U
-#define RTC_TR_HU                            0x000F0000U
-#define RTC_TR_HU_0                          0x00010000U
-#define RTC_TR_HU_1                          0x00020000U
-#define RTC_TR_HU_2                          0x00040000U
-#define RTC_TR_HU_3                          0x00080000U
-#define RTC_TR_MNT                           0x00007000U
-#define RTC_TR_MNT_0                         0x00001000U
-#define RTC_TR_MNT_1                         0x00002000U
-#define RTC_TR_MNT_2                         0x00004000U
-#define RTC_TR_MNU                           0x00000F00U
-#define RTC_TR_MNU_0                         0x00000100U
-#define RTC_TR_MNU_1                         0x00000200U
-#define RTC_TR_MNU_2                         0x00000400U
-#define RTC_TR_MNU_3                         0x00000800U
-#define RTC_TR_ST                            0x00000070U
-#define RTC_TR_ST_0                          0x00000010U
-#define RTC_TR_ST_1                          0x00000020U
-#define RTC_TR_ST_2                          0x00000040U
-#define RTC_TR_SU                            0x0000000FU
-#define RTC_TR_SU_0                          0x00000001U
-#define RTC_TR_SU_1                          0x00000002U
-#define RTC_TR_SU_2                          0x00000004U
-#define RTC_TR_SU_3                          0x00000008U
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            0x00F00000U
-#define RTC_DR_YT_0                          0x00100000U
-#define RTC_DR_YT_1                          0x00200000U
-#define RTC_DR_YT_2                          0x00400000U
-#define RTC_DR_YT_3                          0x00800000U
-#define RTC_DR_YU                            0x000F0000U
-#define RTC_DR_YU_0                          0x00010000U
-#define RTC_DR_YU_1                          0x00020000U
-#define RTC_DR_YU_2                          0x00040000U
-#define RTC_DR_YU_3                          0x00080000U
-#define RTC_DR_WDU                           0x0000E000U
-#define RTC_DR_WDU_0                         0x00002000U
-#define RTC_DR_WDU_1                         0x00004000U
-#define RTC_DR_WDU_2                         0x00008000U
-#define RTC_DR_MT                            0x00001000U
-#define RTC_DR_MU                            0x00000F00U
-#define RTC_DR_MU_0                          0x00000100U
-#define RTC_DR_MU_1                          0x00000200U
-#define RTC_DR_MU_2                          0x00000400U
-#define RTC_DR_MU_3                          0x00000800U
-#define RTC_DR_DT                            0x00000030U
-#define RTC_DR_DT_0                          0x00000010U
-#define RTC_DR_DT_1                          0x00000020U
-#define RTC_DR_DU                            0x0000000FU
-#define RTC_DR_DU_0                          0x00000001U
-#define RTC_DR_DU_1                          0x00000002U
-#define RTC_DR_DU_2                          0x00000004U
-#define RTC_DR_DU_3                          0x00000008U
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           0x00800000U
-#define RTC_CR_OSEL                          0x00600000U
-#define RTC_CR_OSEL_0                        0x00200000U
-#define RTC_CR_OSEL_1                        0x00400000U
-#define RTC_CR_POL                           0x00100000U
-#define RTC_CR_COSEL                         0x00080000U
-#define RTC_CR_BCK                           0x00040000U
-#define RTC_CR_SUB1H                         0x00020000U
-#define RTC_CR_ADD1H                         0x00010000U
-#define RTC_CR_TSIE                          0x00008000U
-#define RTC_CR_WUTIE                         0x00004000U
-#define RTC_CR_ALRBIE                        0x00002000U
-#define RTC_CR_ALRAIE                        0x00001000U
-#define RTC_CR_TSE                           0x00000800U
-#define RTC_CR_WUTE                          0x00000400U
-#define RTC_CR_ALRBE                         0x00000200U
-#define RTC_CR_ALRAE                         0x00000100U
-#define RTC_CR_DCE                           0x00000080U
-#define RTC_CR_FMT                           0x00000040U
-#define RTC_CR_BYPSHAD                       0x00000020U
-#define RTC_CR_REFCKON                       0x00000010U
-#define RTC_CR_TSEDGE                        0x00000008U
-#define RTC_CR_WUCKSEL                       0x00000007U
-#define RTC_CR_WUCKSEL_0                     0x00000001U
-#define RTC_CR_WUCKSEL_1                     0x00000002U
-#define RTC_CR_WUCKSEL_2                     0x00000004U
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      0x00010000U
-#define RTC_ISR_TAMP1F                       0x00002000U
-#define RTC_ISR_TAMP2F                       0x00004000U
-#define RTC_ISR_TSOVF                        0x00001000U
-#define RTC_ISR_TSF                          0x00000800U
-#define RTC_ISR_WUTF                         0x00000400U
-#define RTC_ISR_ALRBF                        0x00000200U
-#define RTC_ISR_ALRAF                        0x00000100U
-#define RTC_ISR_INIT                         0x00000080U
-#define RTC_ISR_INITF                        0x00000040U
-#define RTC_ISR_RSF                          0x00000020U
-#define RTC_ISR_INITS                        0x00000010U
-#define RTC_ISR_SHPF                         0x00000008U
-#define RTC_ISR_WUTWF                        0x00000004U
-#define RTC_ISR_ALRBWF                       0x00000002U
-#define RTC_ISR_ALRAWF                       0x00000001U
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    0x007F0000U
-#define RTC_PRER_PREDIV_S                    0x00007FFFU
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS                       0x00000080U
-#define RTC_CALIBR_DC                        0x0000001FU
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      0x80000000U
-#define RTC_ALRMAR_WDSEL                     0x40000000U
-#define RTC_ALRMAR_DT                        0x30000000U
-#define RTC_ALRMAR_DT_0                      0x10000000U
-#define RTC_ALRMAR_DT_1                      0x20000000U
-#define RTC_ALRMAR_DU                        0x0F000000U
-#define RTC_ALRMAR_DU_0                      0x01000000U
-#define RTC_ALRMAR_DU_1                      0x02000000U
-#define RTC_ALRMAR_DU_2                      0x04000000U
-#define RTC_ALRMAR_DU_3                      0x08000000U
-#define RTC_ALRMAR_MSK3                      0x00800000U
-#define RTC_ALRMAR_PM                        0x00400000U
-#define RTC_ALRMAR_HT                        0x00300000U
-#define RTC_ALRMAR_HT_0                      0x00100000U
-#define RTC_ALRMAR_HT_1                      0x00200000U
-#define RTC_ALRMAR_HU                        0x000F0000U
-#define RTC_ALRMAR_HU_0                      0x00010000U
-#define RTC_ALRMAR_HU_1                      0x00020000U
-#define RTC_ALRMAR_HU_2                      0x00040000U
-#define RTC_ALRMAR_HU_3                      0x00080000U
-#define RTC_ALRMAR_MSK2                      0x00008000U
-#define RTC_ALRMAR_MNT                       0x00007000U
-#define RTC_ALRMAR_MNT_0                     0x00001000U
-#define RTC_ALRMAR_MNT_1                     0x00002000U
-#define RTC_ALRMAR_MNT_2                     0x00004000U
-#define RTC_ALRMAR_MNU                       0x00000F00U
-#define RTC_ALRMAR_MNU_0                     0x00000100U
-#define RTC_ALRMAR_MNU_1                     0x00000200U
-#define RTC_ALRMAR_MNU_2                     0x00000400U
-#define RTC_ALRMAR_MNU_3                     0x00000800U
-#define RTC_ALRMAR_MSK1                      0x00000080U
-#define RTC_ALRMAR_ST                        0x00000070U
-#define RTC_ALRMAR_ST_0                      0x00000010U
-#define RTC_ALRMAR_ST_1                      0x00000020U
-#define RTC_ALRMAR_ST_2                      0x00000040U
-#define RTC_ALRMAR_SU                        0x0000000FU
-#define RTC_ALRMAR_SU_0                      0x00000001U
-#define RTC_ALRMAR_SU_1                      0x00000002U
-#define RTC_ALRMAR_SU_2                      0x00000004U
-#define RTC_ALRMAR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      0x80000000U
-#define RTC_ALRMBR_WDSEL                     0x40000000U
-#define RTC_ALRMBR_DT                        0x30000000U
-#define RTC_ALRMBR_DT_0                      0x10000000U
-#define RTC_ALRMBR_DT_1                      0x20000000U
-#define RTC_ALRMBR_DU                        0x0F000000U
-#define RTC_ALRMBR_DU_0                      0x01000000U
-#define RTC_ALRMBR_DU_1                      0x02000000U
-#define RTC_ALRMBR_DU_2                      0x04000000U
-#define RTC_ALRMBR_DU_3                      0x08000000U
-#define RTC_ALRMBR_MSK3                      0x00800000U
-#define RTC_ALRMBR_PM                        0x00400000U
-#define RTC_ALRMBR_HT                        0x00300000U
-#define RTC_ALRMBR_HT_0                      0x00100000U
-#define RTC_ALRMBR_HT_1                      0x00200000U
-#define RTC_ALRMBR_HU                        0x000F0000U
-#define RTC_ALRMBR_HU_0                      0x00010000U
-#define RTC_ALRMBR_HU_1                      0x00020000U
-#define RTC_ALRMBR_HU_2                      0x00040000U
-#define RTC_ALRMBR_HU_3                      0x00080000U
-#define RTC_ALRMBR_MSK2                      0x00008000U
-#define RTC_ALRMBR_MNT                       0x00007000U
-#define RTC_ALRMBR_MNT_0                     0x00001000U
-#define RTC_ALRMBR_MNT_1                     0x00002000U
-#define RTC_ALRMBR_MNT_2                     0x00004000U
-#define RTC_ALRMBR_MNU                       0x00000F00U
-#define RTC_ALRMBR_MNU_0                     0x00000100U
-#define RTC_ALRMBR_MNU_1                     0x00000200U
-#define RTC_ALRMBR_MNU_2                     0x00000400U
-#define RTC_ALRMBR_MNU_3                     0x00000800U
-#define RTC_ALRMBR_MSK1                      0x00000080U
-#define RTC_ALRMBR_ST                        0x00000070U
-#define RTC_ALRMBR_ST_0                      0x00000010U
-#define RTC_ALRMBR_ST_1                      0x00000020U
-#define RTC_ALRMBR_ST_2                      0x00000040U
-#define RTC_ALRMBR_SU                        0x0000000FU
-#define RTC_ALRMBR_SU_0                      0x00000001U
-#define RTC_ALRMBR_SU_1                      0x00000002U
-#define RTC_ALRMBR_SU_2                      0x00000004U
-#define RTC_ALRMBR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          0x000000FFU
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           0x0000FFFFU
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     0x00007FFFU
-#define RTC_SHIFTR_ADD1S                     0x80000000U
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          0x00400000U
-#define RTC_TSTR_HT                          0x00300000U
-#define RTC_TSTR_HT_0                        0x00100000U
-#define RTC_TSTR_HT_1                        0x00200000U
-#define RTC_TSTR_HU                          0x000F0000U
-#define RTC_TSTR_HU_0                        0x00010000U
-#define RTC_TSTR_HU_1                        0x00020000U
-#define RTC_TSTR_HU_2                        0x00040000U
-#define RTC_TSTR_HU_3                        0x00080000U
-#define RTC_TSTR_MNT                         0x00007000U
-#define RTC_TSTR_MNT_0                       0x00001000U
-#define RTC_TSTR_MNT_1                       0x00002000U
-#define RTC_TSTR_MNT_2                       0x00004000U
-#define RTC_TSTR_MNU                         0x00000F00U
-#define RTC_TSTR_MNU_0                       0x00000100U
-#define RTC_TSTR_MNU_1                       0x00000200U
-#define RTC_TSTR_MNU_2                       0x00000400U
-#define RTC_TSTR_MNU_3                       0x00000800U
-#define RTC_TSTR_ST                          0x00000070U
-#define RTC_TSTR_ST_0                        0x00000010U
-#define RTC_TSTR_ST_1                        0x00000020U
-#define RTC_TSTR_ST_2                        0x00000040U
-#define RTC_TSTR_SU                          0x0000000FU
-#define RTC_TSTR_SU_0                        0x00000001U
-#define RTC_TSTR_SU_1                        0x00000002U
-#define RTC_TSTR_SU_2                        0x00000004U
-#define RTC_TSTR_SU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         0x0000E000U
-#define RTC_TSDR_WDU_0                       0x00002000U
-#define RTC_TSDR_WDU_1                       0x00004000U
-#define RTC_TSDR_WDU_2                       0x00008000U
-#define RTC_TSDR_MT                          0x00001000U
-#define RTC_TSDR_MU                          0x00000F00U
-#define RTC_TSDR_MU_0                        0x00000100U
-#define RTC_TSDR_MU_1                        0x00000200U
-#define RTC_TSDR_MU_2                        0x00000400U
-#define RTC_TSDR_MU_3                        0x00000800U
-#define RTC_TSDR_DT                          0x00000030U
-#define RTC_TSDR_DT_0                        0x00000010U
-#define RTC_TSDR_DT_1                        0x00000020U
-#define RTC_TSDR_DU                          0x0000000FU
-#define RTC_TSDR_DU_0                        0x00000001U
-#define RTC_TSDR_DU_1                        0x00000002U
-#define RTC_TSDR_DU_2                        0x00000004U
-#define RTC_TSDR_DU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        0x00008000U
-#define RTC_CALR_CALW8                       0x00004000U
-#define RTC_CALR_CALW16                      0x00002000U
-#define RTC_CALR_CALM                        0x000001FFU
-#define RTC_CALR_CALM_0                      0x00000001U
-#define RTC_CALR_CALM_1                      0x00000002U
-#define RTC_CALR_CALM_2                      0x00000004U
-#define RTC_CALR_CALM_3                      0x00000008U
-#define RTC_CALR_CALM_4                      0x00000010U
-#define RTC_CALR_CALM_5                      0x00000020U
-#define RTC_CALR_CALM_6                      0x00000040U
-#define RTC_CALR_CALM_7                      0x00000080U
-#define RTC_CALR_CALM_8                      0x00000100U
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               0x00040000U
-#define RTC_TAFCR_TSINSEL                    0x00020000U
-#define RTC_TAFCR_TAMPINSEL                  0x00010000U
-#define RTC_TAFCR_TAMPPUDIS                  0x00008000U
-#define RTC_TAFCR_TAMPPRCH                   0x00006000U
-#define RTC_TAFCR_TAMPPRCH_0                 0x00002000U
-#define RTC_TAFCR_TAMPPRCH_1                 0x00004000U
-#define RTC_TAFCR_TAMPFLT                    0x00001800U
-#define RTC_TAFCR_TAMPFLT_0                  0x00000800U
-#define RTC_TAFCR_TAMPFLT_1                  0x00001000U
-#define RTC_TAFCR_TAMPFREQ                   0x00000700U
-#define RTC_TAFCR_TAMPFREQ_0                 0x00000100U
-#define RTC_TAFCR_TAMPFREQ_1                 0x00000200U
-#define RTC_TAFCR_TAMPFREQ_2                 0x00000400U
-#define RTC_TAFCR_TAMPTS                     0x00000080U
-#define RTC_TAFCR_TAMP2TRG                   0x00000010U
-#define RTC_TAFCR_TAMP2E                     0x00000008U
-#define RTC_TAFCR_TAMPIE                     0x00000004U
-#define RTC_TAFCR_TAMP1TRG                   0x00000002U
-#define RTC_TAFCR_TAMP1E                     0x00000001U
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  0x0F000000U
-#define RTC_ALRMASSR_MASKSS_0                0x01000000U
-#define RTC_ALRMASSR_MASKSS_1                0x02000000U
-#define RTC_ALRMASSR_MASKSS_2                0x04000000U
-#define RTC_ALRMASSR_MASKSS_3                0x08000000U
-#define RTC_ALRMASSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
-#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
-#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
-#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
-#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
-#define RTC_ALRMBSSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           0xFFFFFFFFU
-
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          SD host Interface                                 */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SDIO_POWER register  ******************/
-#define  SDIO_POWER_PWRCTRL                  0x03U               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDIO_POWER_PWRCTRL_0                0x01U               /*!<Bit 0 */
-#define  SDIO_POWER_PWRCTRL_1                0x02U               /*!<Bit 1 */
-
-/******************  Bit definition for SDIO_CLKCR register  ******************/
-#define  SDIO_CLKCR_CLKDIV                   0x00FFU            /*!<Clock divide factor             */
-#define  SDIO_CLKCR_CLKEN                    0x0100U            /*!<Clock enable bit                */
-#define  SDIO_CLKCR_PWRSAV                   0x0200U            /*!<Power saving configuration bit  */
-#define  SDIO_CLKCR_BYPASS                   0x0400U            /*!<Clock divider bypass enable bit */
-
-#define  SDIO_CLKCR_WIDBUS                   0x1800U            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDIO_CLKCR_WIDBUS_0                 0x0800U            /*!<Bit 0 */
-#define  SDIO_CLKCR_WIDBUS_1                 0x1000U            /*!<Bit 1 */
-
-#define  SDIO_CLKCR_NEGEDGE                  0x2000U            /*!<SDIO_CK dephasing selection bit */
-#define  SDIO_CLKCR_HWFC_EN                  0x4000U            /*!<HW Flow Control enable          */
-
-/*******************  Bit definition for SDIO_ARG register  *******************/
-#define  SDIO_ARG_CMDARG                     0xFFFFFFFFU            /*!<Command argument */
-
-/*******************  Bit definition for SDIO_CMD register  *******************/
-#define  SDIO_CMD_CMDINDEX                   0x003FU            /*!<Command Index                               */
-
-#define  SDIO_CMD_WAITRESP                   0x00C0U            /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDIO_CMD_WAITRESP_0                 0x0040U            /*!< Bit 0 */
-#define  SDIO_CMD_WAITRESP_1                 0x0080U            /*!< Bit 1 */
-
-#define  SDIO_CMD_WAITINT                    0x0100U            /*!<CPSM Waits for Interrupt Request                               */
-#define  SDIO_CMD_WAITPEND                   0x0200U            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDIO_CMD_CPSMEN                     0x0400U            /*!<Command path state machine (CPSM) Enable bit                   */
-#define  SDIO_CMD_SDIOSUSPEND                0x0800U            /*!<SD I/O suspend command                                         */
-#define  SDIO_CMD_ENCMDCOMPL                 0x1000U            /*!<Enable CMD completion                                          */
-#define  SDIO_CMD_NIEN                       0x2000U            /*!<Not Interrupt Enable */
-#define  SDIO_CMD_CEATACMD                   0x4000U            /*!<CE-ATA command       */
-
-/*****************  Bit definition for SDIO_RESPCMD register  *****************/
-#define  SDIO_RESPCMD_RESPCMD                0x3FU               /*!<Response command index */
-
-/******************  Bit definition for SDIO_RESP0 register  ******************/
-#define  SDIO_RESP0_CARDSTATUS0              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP1 register  ******************/
-#define  SDIO_RESP1_CARDSTATUS1              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP2 register  ******************/
-#define  SDIO_RESP2_CARDSTATUS2              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP3 register  ******************/
-#define  SDIO_RESP3_CARDSTATUS3              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP4 register  ******************/
-#define  SDIO_RESP4_CARDSTATUS4              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_DTIMER register  *****************/
-#define  SDIO_DTIMER_DATATIME                0xFFFFFFFFU        /*!<Data timeout period. */
-
-/******************  Bit definition for SDIO_DLEN register  *******************/
-#define  SDIO_DLEN_DATALENGTH                0x01FFFFFFU        /*!<Data length value    */
-
-/******************  Bit definition for SDIO_DCTRL register  ******************/
-#define  SDIO_DCTRL_DTEN                     0x0001U            /*!<Data transfer enabled bit         */
-#define  SDIO_DCTRL_DTDIR                    0x0002U            /*!<Data transfer direction selection */
-#define  SDIO_DCTRL_DTMODE                   0x0004U            /*!<Data transfer mode selection      */
-#define  SDIO_DCTRL_DMAEN                    0x0008U            /*!<DMA enabled bit                   */
-
-#define  SDIO_DCTRL_DBLOCKSIZE               0x00F0U            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDIO_DCTRL_DBLOCKSIZE_0             0x0010U            /*!<Bit 0 */
-#define  SDIO_DCTRL_DBLOCKSIZE_1             0x0020U            /*!<Bit 1 */
-#define  SDIO_DCTRL_DBLOCKSIZE_2             0x0040U            /*!<Bit 2 */
-#define  SDIO_DCTRL_DBLOCKSIZE_3             0x0080U            /*!<Bit 3 */
-
-#define  SDIO_DCTRL_RWSTART                  0x0100U            /*!<Read wait start         */
-#define  SDIO_DCTRL_RWSTOP                   0x0200U            /*!<Read wait stop          */
-#define  SDIO_DCTRL_RWMOD                    0x0400U            /*!<Read wait mode          */
-#define  SDIO_DCTRL_SDIOEN                   0x0800U            /*!<SD I/O enable functions */
-
-/******************  Bit definition for SDIO_DCOUNT register  *****************/
-#define  SDIO_DCOUNT_DATACOUNT               0x01FFFFFFU        /*!<Data count value */
-
-/******************  Bit definition for SDIO_STA register  ********************/
-#define  SDIO_STA_CCRCFAIL                   0x00000001U        /*!<Command response received (CRC check failed)  */
-#define  SDIO_STA_DCRCFAIL                   0x00000002U        /*!<Data block sent/received (CRC check failed)   */
-#define  SDIO_STA_CTIMEOUT                   0x00000004U        /*!<Command response timeout                      */
-#define  SDIO_STA_DTIMEOUT                   0x00000008U        /*!<Data timeout                                  */
-#define  SDIO_STA_TXUNDERR                   0x00000010U        /*!<Transmit FIFO underrun error                  */
-#define  SDIO_STA_RXOVERR                    0x00000020U        /*!<Received FIFO overrun error                   */
-#define  SDIO_STA_CMDREND                    0x00000040U        /*!<Command response received (CRC check passed)  */
-#define  SDIO_STA_CMDSENT                    0x00000080U        /*!<Command sent (no response required)           */
-#define  SDIO_STA_DATAEND                    0x00000100U        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
-#define  SDIO_STA_STBITERR                   0x00000200U        /*!<Start bit not detected on all data signals in wide bus mode */
-#define  SDIO_STA_DBCKEND                    0x00000400U        /*!<Data block sent/received (CRC check passed)   */
-#define  SDIO_STA_CMDACT                     0x00000800U        /*!<Command transfer in progress                  */
-#define  SDIO_STA_TXACT                      0x00001000U        /*!<Data transmit in progress                     */
-#define  SDIO_STA_RXACT                      0x00002000U        /*!<Data receive in progress                      */
-#define  SDIO_STA_TXFIFOHE                   0x00004000U        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDIO_STA_RXFIFOHF                   0x00008000U        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDIO_STA_TXFIFOF                    0x00010000U        /*!<Transmit FIFO full                            */
-#define  SDIO_STA_RXFIFOF                    0x00020000U        /*!<Receive FIFO full                             */
-#define  SDIO_STA_TXFIFOE                    0x00040000U        /*!<Transmit FIFO empty                           */
-#define  SDIO_STA_RXFIFOE                    0x00080000U        /*!<Receive FIFO empty                            */
-#define  SDIO_STA_TXDAVL                     0x00100000U        /*!<Data available in transmit FIFO               */
-#define  SDIO_STA_RXDAVL                     0x00200000U        /*!<Data available in receive FIFO                */
-#define  SDIO_STA_SDIOIT                     0x00400000U        /*!<SDIO interrupt received                       */
-#define  SDIO_STA_CEATAEND                   0x00800000U        /*!<CE-ATA command completion signal received for CMD61 */
-
-/*******************  Bit definition for SDIO_ICR register  *******************/
-#define  SDIO_ICR_CCRCFAILC                  0x00000001U        /*!<CCRCFAIL flag clear bit */
-#define  SDIO_ICR_DCRCFAILC                  0x00000002U        /*!<DCRCFAIL flag clear bit */
-#define  SDIO_ICR_CTIMEOUTC                  0x00000004U        /*!<CTIMEOUT flag clear bit */
-#define  SDIO_ICR_DTIMEOUTC                  0x00000008U        /*!<DTIMEOUT flag clear bit */
-#define  SDIO_ICR_TXUNDERRC                  0x00000010U        /*!<TXUNDERR flag clear bit */
-#define  SDIO_ICR_RXOVERRC                   0x00000020U        /*!<RXOVERR flag clear bit  */
-#define  SDIO_ICR_CMDRENDC                   0x00000040U        /*!<CMDREND flag clear bit  */
-#define  SDIO_ICR_CMDSENTC                   0x00000080U        /*!<CMDSENT flag clear bit  */
-#define  SDIO_ICR_DATAENDC                   0x00000100U        /*!<DATAEND flag clear bit  */
-#define  SDIO_ICR_STBITERRC                  0x00000200U        /*!<STBITERR flag clear bit */
-#define  SDIO_ICR_DBCKENDC                   0x00000400U        /*!<DBCKEND flag clear bit  */
-#define  SDIO_ICR_SDIOITC                    0x00400000U        /*!<SDIOIT flag clear bit   */
-#define  SDIO_ICR_CEATAENDC                  0x00800000U        /*!<CEATAEND flag clear bit */
-
-/******************  Bit definition for SDIO_MASK register  *******************/
-#define  SDIO_MASK_CCRCFAILIE                0x00000001U        /*!<Command CRC Fail Interrupt Enable          */
-#define  SDIO_MASK_DCRCFAILIE                0x00000002U        /*!<Data CRC Fail Interrupt Enable             */
-#define  SDIO_MASK_CTIMEOUTIE                0x00000004U        /*!<Command TimeOut Interrupt Enable           */
-#define  SDIO_MASK_DTIMEOUTIE                0x00000008U        /*!<Data TimeOut Interrupt Enable              */
-#define  SDIO_MASK_TXUNDERRIE                0x00000010U        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
-#define  SDIO_MASK_RXOVERRIE                 0x00000020U        /*!<Rx FIFO OverRun Error Interrupt Enable     */
-#define  SDIO_MASK_CMDRENDIE                 0x00000040U        /*!<Command Response Received Interrupt Enable */
-#define  SDIO_MASK_CMDSENTIE                 0x00000080U        /*!<Command Sent Interrupt Enable              */
-#define  SDIO_MASK_DATAENDIE                 0x00000100U        /*!<Data End Interrupt Enable                  */
-#define  SDIO_MASK_STBITERRIE                0x00000200U        /*!<Start Bit Error Interrupt Enable           */
-#define  SDIO_MASK_DBCKENDIE                 0x00000400U        /*!<Data Block End Interrupt Enable            */
-#define  SDIO_MASK_CMDACTIE                  0x00000800U        /*!<CCommand Acting Interrupt Enable           */
-#define  SDIO_MASK_TXACTIE                   0x00001000U        /*!<Data Transmit Acting Interrupt Enable      */
-#define  SDIO_MASK_RXACTIE                   0x00002000U        /*!<Data receive acting interrupt enabled      */
-#define  SDIO_MASK_TXFIFOHEIE                0x00004000U        /*!<Tx FIFO Half Empty interrupt Enable        */
-#define  SDIO_MASK_RXFIFOHFIE                0x00008000U        /*!<Rx FIFO Half Full interrupt Enable         */
-#define  SDIO_MASK_TXFIFOFIE                 0x00010000U        /*!<Tx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_RXFIFOFIE                 0x00020000U        /*!<Rx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_TXFIFOEIE                 0x00040000U        /*!<Tx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_RXFIFOEIE                 0x00080000U        /*!<Rx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_TXDAVLIE                  0x00100000U        /*!<Data available in Tx FIFO interrupt Enable */
-#define  SDIO_MASK_RXDAVLIE                  0x00200000U        /*!<Data available in Rx FIFO interrupt Enable */
-#define  SDIO_MASK_SDIOITIE                  0x00400000U        /*!<SDIO Mode Interrupt Received interrupt Enable */
-#define  SDIO_MASK_CEATAENDIE                0x00800000U        /*!<CE-ATA command completion signal received Interrupt Enable */
-
-/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
-#define  SDIO_FIFOCNT_FIFOCOUNT              0x00FFFFFFU        /*!<Remaining number of words to be written to or read from the FIFO */
-
-/******************  Bit definition for SDIO_FIFO register  *******************/
-#define  SDIO_FIFO_FIFODATA                  0xFFFFFFFFU        /*!<Receive and transmit FIFO data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        0x00000001U            /*!<Clock Phase      */
-#define  SPI_CR1_CPOL                        0x00000002U            /*!<Clock Polarity   */
-#define  SPI_CR1_MSTR                        0x00000004U            /*!<Master Selection */
-
-#define  SPI_CR1_BR                          0x00000038U            /*!<BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        0x00000008U            /*!<Bit 0 */
-#define  SPI_CR1_BR_1                        0x00000010U            /*!<Bit 1 */
-#define  SPI_CR1_BR_2                        0x00000020U            /*!<Bit 2 */
-
-#define  SPI_CR1_SPE                         0x00000040U            /*!<SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    0x00000080U            /*!<Frame Format                        */
-#define  SPI_CR1_SSI                         0x00000100U            /*!<Internal slave select               */
-#define  SPI_CR1_SSM                         0x00000200U            /*!<Software slave management           */
-#define  SPI_CR1_RXONLY                      0x00000400U            /*!<Receive only                        */
-#define  SPI_CR1_DFF                         0x00000800U            /*!<Data Frame Format                   */
-#define  SPI_CR1_CRCNEXT                     0x00001000U            /*!<Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       0x00002000U            /*!<Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      0x00004000U            /*!<Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    0x00008000U            /*!<Bidirectional data mode enable      */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     0x00000001U               /*!<Rx Buffer DMA Enable                 */
-#define  SPI_CR2_TXDMAEN                     0x00000002U               /*!<Tx Buffer DMA Enable                 */
-#define  SPI_CR2_SSOE                        0x00000004U               /*!<SS Output Enable                     */
-#define  SPI_CR2_FRF                         0x00000010U               /*!<Frame Format                         */
-#define  SPI_CR2_ERRIE                       0x00000020U               /*!<Error Interrupt Enable               */
-#define  SPI_CR2_RXNEIE                      0x00000040U               /*!<RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       0x00000080U               /*!<Tx buffer Empty Interrupt Enable     */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         0x00000001U               /*!<Receive buffer Not Empty */
-#define  SPI_SR_TXE                          0x00000002U               /*!<Transmit buffer Empty    */
-#define  SPI_SR_CHSIDE                       0x00000004U               /*!<Channel side             */
-#define  SPI_SR_UDR                          0x00000008U               /*!<Underrun flag            */
-#define  SPI_SR_CRCERR                       0x00000010U               /*!<CRC Error flag           */
-#define  SPI_SR_MODF                         0x00000020U               /*!<Mode fault               */
-#define  SPI_SR_OVR                          0x00000040U               /*!<Overrun flag             */
-#define  SPI_SR_BSY                          0x00000080U               /*!<Busy flag                */
-#define  SPI_SR_FRE                          0x00000100U               /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           0x0000FFFFU            /*!<Data Register           */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   0x0000FFFFU            /*!<CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    0x0000FFFFU            /*!<Rx CRC Register         */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    0x0000FFFFU            /*!<Tx CRC Register         */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   0x00000001U            /*!<Channel length (number of bits per audio channel) */
-
-#define  SPI_I2SCFGR_DATLEN                  0x00000006U            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define  SPI_I2SCFGR_DATLEN_0                0x00000002U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                0x00000004U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_CKPOL                   0x00000008U            /*!<steady state clock polarity               */
-
-#define  SPI_I2SCFGR_I2SSTD                  0x00000030U            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U            /*!<PCM frame synchronization                 */
-
-#define  SPI_I2SCFGR_I2SCFG                  0x00000300U            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_I2SE                    0x00000400U            /*!<I2S Enable         */
-#define  SPI_I2SCFGR_I2SMOD                  0x00000800U            /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    0x000000FFU            /*!<I2S Linear prescaler         */
-#define  SPI_I2SPR_ODD                       0x00000100U            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     0x00000200U            /*!<Master Clock Output Enable   */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 SYSCFG                                     */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
-#define SYSCFG_MEMRMP_MEM_MODE          0x00000007U /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        0x00000001U
-#define SYSCFG_MEMRMP_MEM_MODE_1        0x00000002U
-#define SYSCFG_MEMRMP_MEM_MODE_2        0x00000004U
-
-/******************  Bit definition for SYSCFG_PMC register  ******************/
-#define SYSCFG_PMC_MII_RMII_SEL         0x00800000U /*!<Ethernet PHY interface selection */
-/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
-#define SYSCFG_PMC_MII_RMII             SYSCFG_PMC_MII_RMII_SEL
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
-/** 
-  * @brief   EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         0x0003U /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         0x0004U /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         0x0005U /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         0x0006U /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PI         0x0008U /*!<PI[0] pin */
-
-/** 
-  * @brief   EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         0x0030U /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         0x0040U /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         0x0050U /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         0x0060U /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PI         0x0080U /*!<PI[1] pin */
-
-/** 
-  * @brief   EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         0x0300U /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         0x0400U /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         0x0500U /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         0x0600U /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PI         0x0800U /*!<PI[2] pin */
-
-/** 
-  * @brief   EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         0x3000U /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         0x4000U /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         0x5000U /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         0x6000U /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PI         0x8000U /*!<PI[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
-/** 
-  * @brief   EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         0x0003U /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         0x0004U /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         0x0005U /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         0x0006U /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PI         0x0008U /*!<PI[4] pin */
-
-/** 
-  * @brief   EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         0x0030U /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         0x0040U /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         0x0050U /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         0x0060U /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PI         0x0080U /*!<PI[5] pin */
-
-/** 
-  * @brief   EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         0x0300U /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         0x0400U /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         0x0500U /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         0x0600U /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PI         0x0800U /*!<PI[6] pin */
-
-/** 
-  * @brief   EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         0x3000U /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         0x4000U /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         0x5000U /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         0x6000U /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PI         0x8000U /*!<PI[7] pin */
-
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
-           
-/** 
-  * @brief   EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         0x0003U /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         0x0004U /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         0x0005U /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         0x0006U /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PI         0x0008U /*!<PI[8] pin */
-
-/** 
-  * @brief   EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         0x0030U /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         0x0040U /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         0x0050U /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         0x0060U /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PI         0x0080U /*!<PI[9] pin */
-
-/** 
-  * @brief   EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        0x0300U /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        0x0400U /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        0x0500U /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        0x0600U /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PI        0x0800U /*!<PI[10] pin */
-
-/** 
-  * @brief   EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        0x3000U /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        0x4000U /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        0x5000U /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        0x6000U /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PI        0x8000U /*!<PI[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
-/** 
-  * @brief   EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        0x0003U /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        0x0004U /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        0x0005U /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        0x0006U /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
-
-/** 
-  * @brief   EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        0x0030U /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        0x0040U /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        0x0050U /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        0x0060U /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
-
-/** 
-  * @brief   EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        0x0300U /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        0x0400U /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        0x0500U /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        0x0600U /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
-
-/** 
-  * @brief   EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        0x3000U /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        0x4000U /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        0x5000U /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        0x6000U /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
-
-/******************  Bit definition for SYSCFG_CMPCR register  ****************/  
-#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell ready flag */
-#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell power-down */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    TIM                                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
-#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
-#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
-#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
-#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
-
-#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
-
-#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
-
-#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        0x0001U            /*!<Capture/Compare Preloaded Control        */
-#define  TIM_CR2_CCUS                        0x0004U            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        0x0008U            /*!<Capture/Compare DMA Selection            */
-
-#define  TIM_CR2_MMS                         0x0070U            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
-#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
-#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
-#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        0x0007U            /*!<SMS[2:0] bits (Slave mode selection)    */
-#define  TIM_SMCR_SMS_0                      0x0001U            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      0x0002U            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      0x0004U            /*!<Bit 2 */
-
-#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
-#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
-
-#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
-
-#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
-
-#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
-#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
-#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
-#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
-#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
-#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
-#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
-#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
-#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
-#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
-#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
-#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
-#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
-#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
-#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
-#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
-#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
-#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
-#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          0x01U               /*!<Update Generation                         */
-#define  TIM_EGR_CC1G                        0x02U               /*!<Capture/Compare 1 Generation              */
-#define  TIM_EGR_CC2G                        0x04U               /*!<Capture/Compare 2 Generation              */
-#define  TIM_EGR_CC3G                        0x08U               /*!<Capture/Compare 3 Generation              */
-#define  TIM_EGR_CC4G                        0x10U               /*!<Capture/Compare 4 Generation              */
-#define  TIM_EGR_COMG                        0x20U               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          0x40U               /*!<Trigger Generation                        */
-#define  TIM_EGR_BG                          0x80U               /*!<Break Generation                          */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      0x0003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    0x0001U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    0x0002U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC1FE                     0x0004U            /*!<Output Compare 1 Fast enable                 */
-#define  TIM_CCMR1_OC1PE                     0x0008U            /*!<Output Compare 1 Preload enable              */
-
-#define  TIM_CCMR1_OC1M                      0x0070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define  TIM_CCMR1_OC1M_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    0x0040U            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC1CE                     0x0080U            /*!<Output Compare 1Clear Enable                 */
-
-#define  TIM_CCMR1_CC2S                      0x0300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    0x0100U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    0x0200U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC2FE                     0x0400U            /*!<Output Compare 2 Fast enable                 */
-#define  TIM_CCMR1_OC2PE                     0x0800U            /*!<Output Compare 2 Preload enable              */
-
-#define  TIM_CCMR1_OC2M                      0x7000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define  TIM_CCMR1_OC2M_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    0x4000U            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC2CE                     0x8000U            /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      0x0003U            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define  TIM_CCMR2_CC3S_0                    0x0001U            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    0x0002U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC3FE                     0x0004U            /*!<Output Compare 3 Fast enable           */
-#define  TIM_CCMR2_OC3PE                     0x0008U            /*!<Output Compare 3 Preload enable        */
-
-#define  TIM_CCMR2_OC3M                      0x0070U            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    0x0040U            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC3CE                     0x0080U            /*!<Output Compare 3 Clear Enable */
-
-#define  TIM_CCMR2_CC4S                      0x0300U            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    0x0100U            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    0x0200U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC4FE                     0x0400U            /*!<Output Compare 4 Fast enable    */
-#define  TIM_CCMR2_OC4PE                     0x0800U            /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR2_OC4M                      0x7000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    0x4000U            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       0x0001U            /*!<Capture/Compare 1 output enable                 */
-#define  TIM_CCER_CC1P                       0x0002U            /*!<Capture/Compare 1 output Polarity               */
-#define  TIM_CCER_CC1NE                      0x0004U            /*!<Capture/Compare 1 Complementary output enable   */
-#define  TIM_CCER_CC1NP                      0x0008U            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       0x0010U            /*!<Capture/Compare 2 output enable                 */
-#define  TIM_CCER_CC2P                       0x0020U            /*!<Capture/Compare 2 output Polarity               */
-#define  TIM_CCER_CC2NE                      0x0040U            /*!<Capture/Compare 2 Complementary output enable   */
-#define  TIM_CCER_CC2NP                      0x0080U            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       0x0100U            /*!<Capture/Compare 3 output enable                 */
-#define  TIM_CCER_CC3P                       0x0200U            /*!<Capture/Compare 3 output Polarity               */
-#define  TIM_CCER_CC3NE                      0x0400U            /*!<Capture/Compare 3 Complementary output enable   */
-#define  TIM_CCER_CC3NP                      0x0800U            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       0x1000U            /*!<Capture/Compare 4 output enable                 */
-#define  TIM_CCER_CC4P                       0x2000U            /*!<Capture/Compare 4 output Polarity               */
-#define  TIM_CCER_CC4NP                      0x8000U            /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         0xFFU               /*!<Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
-
-/*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        0x00FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      0x0001U            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      0x0002U            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      0x0004U            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      0x0008U            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      0x0010U            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      0x0020U            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      0x0040U            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      0x0080U            /*!<Bit 7 */
-
-#define  TIM_BDTR_LOCK                       0x0300U            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     0x0100U            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     0x0200U            /*!<Bit 1 */
-
-#define  TIM_BDTR_OSSI                       0x0400U            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       0x0800U            /*!<Off-State Selection for Run mode  */
-#define  TIM_BDTR_BKE                        0x1000U            /*!<Break enable                      */
-#define  TIM_BDTR_BKP                        0x2000U            /*!<Break Polarity                    */
-#define  TIM_BDTR_AOE                        0x4000U            /*!<Automatic Output enable           */
-#define  TIM_BDTR_MOE                        0x8000U            /*!<Main Output enable                */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
-
-#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
-#define TIM_OR_ITR1_RMP                      0x0C00U            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
-#define TIM_OR_ITR1_RMP_0                    0x0400U            /*!<Bit 0 */
-#define TIM_OR_ITR1_RMP_1                    0x0800U            /*!<Bit 1 */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*         Universal Synchronous Asynchronous Receiver Transmitter            */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         0x0001U            /*!<Parity Error                 */
-#define  USART_SR_FE                         0x0002U            /*!<Framing Error                */
-#define  USART_SR_NE                         0x0004U            /*!<Noise Error Flag             */
-#define  USART_SR_ORE                        0x0008U            /*!<OverRun Error                */
-#define  USART_SR_IDLE                       0x0010U            /*!<IDLE line detected           */
-#define  USART_SR_RXNE                       0x0020U            /*!<Read Data Register Not Empty */
-#define  USART_SR_TC                         0x0040U            /*!<Transmission Complete        */
-#define  USART_SR_TXE                        0x0080U            /*!<Transmit Data Register Empty */
-#define  USART_SR_LBD                        0x0100U            /*!<LIN Break Detection Flag     */
-#define  USART_SR_CTS                        0x0200U            /*!<CTS Flag                     */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         0x01FFU            /*!<Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_Fraction              0x000FU            /*!<Fraction of USARTDIV */
-#define  USART_BRR_DIV_Mantissa              0xFFF0U            /*!<Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       0x0001U            /*!<Send Break                             */
-#define  USART_CR1_RWU                       0x0002U            /*!<Receiver wakeup                        */
-#define  USART_CR1_RE                        0x0004U            /*!<Receiver Enable                        */
-#define  USART_CR1_TE                        0x0008U            /*!<Transmitter Enable                     */
-#define  USART_CR1_IDLEIE                    0x0010U            /*!<IDLE Interrupt Enable                  */
-#define  USART_CR1_RXNEIE                    0x0020U            /*!<RXNE Interrupt Enable                  */
-#define  USART_CR1_TCIE                      0x0040U            /*!<Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     0x0080U            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PEIE                      0x0100U            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PS                        0x0200U            /*!<Parity Selection                       */
-#define  USART_CR1_PCE                       0x0400U            /*!<Parity Control Enable                  */
-#define  USART_CR1_WAKE                      0x0800U            /*!<Wakeup method                          */
-#define  USART_CR1_M                         0x1000U            /*!<Word length                            */
-#define  USART_CR1_UE                        0x2000U            /*!<USART Enable                           */
-#define  USART_CR1_OVER8                     0x8000U            /*!<USART Oversampling by 8 enable         */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       0x000FU            /*!<Address of the USART node            */
-#define  USART_CR2_LBDL                      0x0020U            /*!<LIN Break Detection Length           */
-#define  USART_CR2_LBDIE                     0x0040U            /*!<LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      0x0100U            /*!<Last Bit Clock pulse                 */
-#define  USART_CR2_CPHA                      0x0200U            /*!<Clock Phase                          */
-#define  USART_CR2_CPOL                      0x0400U            /*!<Clock Polarity                       */
-#define  USART_CR2_CLKEN                     0x0800U            /*!<Clock Enable                         */
-
-#define  USART_CR2_STOP                      0x3000U            /*!<STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    0x1000U            /*!<Bit 0 */
-#define  USART_CR2_STOP_1                    0x2000U            /*!<Bit 1 */
-
-#define  USART_CR2_LINEN                     0x4000U            /*!<LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       0x0001U            /*!<Error Interrupt Enable      */
-#define  USART_CR3_IREN                      0x0002U            /*!<IrDA mode Enable            */
-#define  USART_CR3_IRLP                      0x0004U            /*!<IrDA Low-Power              */
-#define  USART_CR3_HDSEL                     0x0008U            /*!<Half-Duplex Selection       */
-#define  USART_CR3_NACK                      0x0010U            /*!<Smartcard NACK enable       */
-#define  USART_CR3_SCEN                      0x0020U            /*!<Smartcard mode enable       */
-#define  USART_CR3_DMAR                      0x0040U            /*!<DMA Enable Receiver         */
-#define  USART_CR3_DMAT                      0x0080U            /*!<DMA Enable Transmitter      */
-#define  USART_CR3_RTSE                      0x0100U            /*!<RTS Enable                  */
-#define  USART_CR3_CTSE                      0x0200U            /*!<CTS Enable                  */
-#define  USART_CR3_CTSIE                     0x0400U            /*!<CTS Interrupt Enable        */
-#define  USART_CR3_ONEBIT                    0x0800U            /*!<USART One bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      0x00FFU            /*!<PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    0x0001U            /*!<Bit 0 */
-#define  USART_GTPR_PSC_1                    0x0002U            /*!<Bit 1 */
-#define  USART_GTPR_PSC_2                    0x0004U            /*!<Bit 2 */
-#define  USART_GTPR_PSC_3                    0x0008U            /*!<Bit 3 */
-#define  USART_GTPR_PSC_4                    0x0010U            /*!<Bit 4 */
-#define  USART_GTPR_PSC_5                    0x0020U            /*!<Bit 5 */
-#define  USART_GTPR_PSC_6                    0x0040U            /*!<Bit 6 */
-#define  USART_GTPR_PSC_7                    0x0080U            /*!<Bit 7 */
-
-#define  USART_GTPR_GT                       0xFF00U            /*!<Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Window WATCHDOG                                 */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           0x7FU               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T_0                         0x01U               /*!<Bit 0 */
-#define  WWDG_CR_T_1                         0x02U               /*!<Bit 1 */
-#define  WWDG_CR_T_2                         0x04U               /*!<Bit 2 */
-#define  WWDG_CR_T_3                         0x08U               /*!<Bit 3 */
-#define  WWDG_CR_T_4                         0x10U               /*!<Bit 4 */
-#define  WWDG_CR_T_5                         0x20U               /*!<Bit 5 */
-#define  WWDG_CR_T_6                         0x40U               /*!<Bit 6 */
-/* Legacy defines */
-#define  WWDG_CR_T0                          WWDG_CR_T_0
-#define  WWDG_CR_T1                          WWDG_CR_T_1
-#define  WWDG_CR_T2                          WWDG_CR_T_2
-#define  WWDG_CR_T3                          WWDG_CR_T_3
-#define  WWDG_CR_T4                          WWDG_CR_T_4
-#define  WWDG_CR_T5                          WWDG_CR_T_5
-#define  WWDG_CR_T6                          WWDG_CR_T_6
-
-#define  WWDG_CR_WDGA                        0x80U               /*!<Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          0x007FU            /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W_0                        0x0001U            /*!<Bit 0 */
-#define  WWDG_CFR_W_1                        0x0002U            /*!<Bit 1 */
-#define  WWDG_CFR_W_2                        0x0004U            /*!<Bit 2 */
-#define  WWDG_CFR_W_3                        0x0008U            /*!<Bit 3 */
-#define  WWDG_CFR_W_4                        0x0010U            /*!<Bit 4 */
-#define  WWDG_CFR_W_5                        0x0020U            /*!<Bit 5 */
-#define  WWDG_CFR_W_6                        0x0040U            /*!<Bit 6 */
-/* Legacy defines */
-#define  WWDG_CFR_W0                         WWDG_CFR_W_0
-#define  WWDG_CFR_W1                         WWDG_CFR_W_1
-#define  WWDG_CFR_W2                         WWDG_CFR_W_2
-#define  WWDG_CFR_W3                         WWDG_CFR_W_3
-#define  WWDG_CFR_W4                         WWDG_CFR_W_4
-#define  WWDG_CFR_W5                         WWDG_CFR_W_5
-#define  WWDG_CFR_W6                         WWDG_CFR_W_6
-
-#define  WWDG_CFR_WDGTB                      0x0180U            /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB_0                    0x0080U            /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB_1                    0x0100U            /*!<Bit 1 */
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
-
-#define  WWDG_CFR_EWI                        0x0200U            /*!<Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        0x01U               /*!<Early Wakeup Interrupt Flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                DBG                                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
-#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
-
-/********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
-#define  DBGMCU_CR_DBG_STOP                  0x00000002U
-#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
-#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
-
-#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
-#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U/*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U/*!<Bit 1 */
-
-/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            0x00000001U
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            0x00000002U
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            0x00000004U
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            0x00000020U
-#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           0x00000040U
-#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           0x00000080U
-#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           0x00000100U
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
-#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
-/* Old IWDGSTOP bit definition, maintained for legacy purpose */
-#define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
-
-/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        0x00000001U
-#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        0x00000002U
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        0x00010000U
-#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       0x00020000U
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       0x00040000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                                       USB_OTG			                        */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/
-#define USB_OTG_GOTGCTL_SRQSCS                  0x00000001U            /*!< Session request success */
-#define USB_OTG_GOTGCTL_SRQ                     0x00000002U            /*!< Session request */
-#define USB_OTG_GOTGCTL_HNGSCS                  0x00000100U            /*!< Host negotiation success */
-#define USB_OTG_GOTGCTL_HNPRQ                   0x00000200U            /*!< HNP request */
-#define USB_OTG_GOTGCTL_HSHNPEN                 0x00000400U            /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_DHNPEN                  0x00000800U            /*!< Device HNP enabled */
-#define USB_OTG_GOTGCTL_CIDSTS                  0x00010000U            /*!< Connector ID status */
-#define USB_OTG_GOTGCTL_DBCT                    0x00020000U            /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD                   0x00040000U            /*!< A-session valid */
-#define USB_OTG_GOTGCTL_BSVLD                   0x00080000U            /*!< B-session valid */
-
-/********************  Bit definition forUSB_OTG_HCFG register  ********************/
-
-#define USB_OTG_HCFG_FSLSPCS                 0x00000003U            /*!< FS/LS PHY clock select */
-#define USB_OTG_HCFG_FSLSPCS_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCFG_FSLSPCS_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCFG_FSLSS                   0x00000004U            /*!< FS- and LS-only support */
-
-/********************  Bit definition forUSB_OTG_DCFG register  ********************/
-
-#define USB_OTG_DCFG_DSPD                    0x00000003U            /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                  0x00000001U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DSPD_1                  0x00000002U            /*!<Bit 1 */
-#define USB_OTG_DCFG_NZLSOHSK                0x00000004U            /*!< Nonzero-length status OUT handshake */
-
-#define USB_OTG_DCFG_DAD                     0x000007F0U            /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                   0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DAD_1                   0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCFG_DAD_2                   0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCFG_DAD_3                   0x00000080U            /*!<Bit 3 */
-#define USB_OTG_DCFG_DAD_4                   0x00000100U            /*!<Bit 4 */
-#define USB_OTG_DCFG_DAD_5                   0x00000200U            /*!<Bit 5 */
-#define USB_OTG_DCFG_DAD_6                   0x00000400U            /*!<Bit 6 */
-
-#define USB_OTG_DCFG_PFIVL                   0x00001800U            /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PFIVL_1                 0x00001000U            /*!<Bit 1 */
-
-#define USB_OTG_DCFG_PERSCHIVL               0x03000000U            /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0             0x01000000U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PERSCHIVL_1             0x02000000U            /*!<Bit 1 */
-
-/********************  Bit definition forUSB_OTG_PCGCR register  ********************/
-#define USB_OTG_PCGCR_STPPCLK                 0x00000001U            /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK                0x00000002U            /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP                 0x00000010U            /*!< PHY suspended */
-
-/********************  Bit definition forUSB_OTG_GOTGINT register  ********************/
-#define USB_OTG_GOTGINT_SEDET                   0x00000004U            /*!< Session end detected */
-#define USB_OTG_GOTGINT_SRSSCHG                 0x00000100U            /*!< Session request success status change */
-#define USB_OTG_GOTGINT_HNSSCHG                 0x00000200U            /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET                  0x00020000U            /*!< Host negotiation detected */
-#define USB_OTG_GOTGINT_ADTOCHG                 0x00040000U            /*!< A-device timeout change */
-#define USB_OTG_GOTGINT_DBCDNE                  0x00080000U            /*!< Debounce done */
-
-/********************  Bit definition forUSB_OTG_DCTL register  ********************/
-#define USB_OTG_DCTL_RWUSIG                  0x00000001U            /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS                    0x00000002U            /*!< Soft disconnect */
-#define USB_OTG_DCTL_GINSTS                  0x00000004U            /*!< Global IN NAK status */
-#define USB_OTG_DCTL_GONSTS                  0x00000008U            /*!< Global OUT NAK status */
-
-#define USB_OTG_DCTL_TCTL                    0x00000070U            /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                  0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCTL_TCTL_1                  0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCTL_TCTL_2                  0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCTL_SGINAK                  0x00000080U            /*!< Set global IN NAK */
-#define USB_OTG_DCTL_CGINAK                  0x00000100U            /*!< Clear global IN NAK */
-#define USB_OTG_DCTL_SGONAK                  0x00000200U            /*!< Set global OUT NAK */
-#define USB_OTG_DCTL_CGONAK                  0x00000400U            /*!< Clear global OUT NAK */
-#define USB_OTG_DCTL_POPRGDNE                0x00000800U            /*!< Power-on programming done */
-
-/********************  Bit definition forUSB_OTG_HFIR register  ********************/
-#define USB_OTG_HFIR_FRIVL                   0x0000FFFFU            /*!< Frame interval */
-
-/********************  Bit definition forUSB_OTG_HFNUM register  ********************/
-#define USB_OTG_HFNUM_FRNUM                   0x0000FFFFU            /*!< Frame number */
-#define USB_OTG_HFNUM_FTREM                   0xFFFF0000U            /*!< Frame time remaining */
-
-/********************  Bit definition forUSB_OTG_DSTS register  ********************/
-#define USB_OTG_DSTS_SUSPSTS                 0x00000001U            /*!< Suspend status */
-
-#define USB_OTG_DSTS_ENUMSPD                 0x00000006U            /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_DSTS_ENUMSPD_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_DSTS_EERR                    0x00000008U            /*!< Erratic error */
-#define USB_OTG_DSTS_FNSOF                   0x003FFF00U            /*!< Frame number of the received SOF */
-
-/********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/
-#define USB_OTG_GAHBCFG_GINT                    0x00000001U            /*!< Global interrupt mask */
-
-#define USB_OTG_GAHBCFG_HBSTLEN                 0x0000001EU            /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_GAHBCFG_HBSTLEN_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_GAHBCFG_HBSTLEN_2               0x00000008U            /*!<Bit 2 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3               0x00000010U            /*!<Bit 3 */
-#define USB_OTG_GAHBCFG_DMAEN                   0x00000020U            /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL                 0x00000080U            /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL                0x00000100U            /*!< Periodic TxFIFO empty level */
-
-/********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/
-
-#define USB_OTG_GUSBCFG_TOCAL                   0x00000007U            /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TOCAL_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TOCAL_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_PHYSEL                  0x00000040U            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP                  0x00000100U            /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP                  0x00000200U            /*!< HNP-capable */
-
-#define USB_OTG_GUSBCFG_TRDT                    0x00003C00U            /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                  0x00000400U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TRDT_1                  0x00000800U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TRDT_2                  0x00001000U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_TRDT_3                  0x00002000U            /*!<Bit 3 */
-#define USB_OTG_GUSBCFG_PHYLPCS                 0x00008000U            /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS                0x00020000U            /*!< ULPI FS/LS select */
-#define USB_OTG_GUSBCFG_ULPIAR                  0x00040000U            /*!< ULPI Auto-resume */
-#define USB_OTG_GUSBCFG_ULPICSM                 0x00080000U            /*!< ULPI Clock SuspendM */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD              0x00100000U            /*!< ULPI External VBUS Drive */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI              0x00200000U            /*!< ULPI external VBUS indicator */
-#define USB_OTG_GUSBCFG_TSDPS                   0x00400000U            /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI                    0x00800000U            /*!< Indicator complement */
-#define USB_OTG_GUSBCFG_PTCI                    0x01000000U            /*!< Indicator pass through */
-#define USB_OTG_GUSBCFG_ULPIIPD                 0x02000000U            /*!< ULPI interface protect disable */
-#define USB_OTG_GUSBCFG_FHMOD                   0x20000000U            /*!< Forced host mode */
-#define USB_OTG_GUSBCFG_FDMOD                   0x40000000U            /*!< Forced peripheral mode */
-#define USB_OTG_GUSBCFG_CTXPKT                  0x80000000U            /*!< Corrupt Tx packet */
-
-/********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
-#define USB_OTG_GRSTCTL_CSRST                   0x00000001U            /*!< Core soft reset */
-#define USB_OTG_GRSTCTL_HSRST                   0x00000002U            /*!< HCLK soft reset */
-#define USB_OTG_GRSTCTL_FCRST                   0x00000004U            /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH                 0x00000010U            /*!< RxFIFO flush */
-#define USB_OTG_GRSTCTL_TXFFLSH                 0x00000020U            /*!< TxFIFO flush */
-
-#define USB_OTG_GRSTCTL_TXFNUM                  0x000007C0U            /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                0x00000040U            /*!<Bit 0 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                0x00000080U            /*!<Bit 1 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                0x00000100U            /*!<Bit 2 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                0x00000200U            /*!<Bit 3 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                0x00000400U            /*!<Bit 4 */
-#define USB_OTG_GRSTCTL_DMAREQ                  0x40000000U            /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL                  0x80000000U            /*!< AHB master idle */
-
-/********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/
-#define USB_OTG_DIEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPMSK_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPMSK_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPMSK_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPMSK_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPMSK_BIM                     0x00000200U            /*!< BNA interrupt mask */
-
-/********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/
-#define USB_OTG_HPTXSTS_PTXFSAVL                0x0000FFFFU            /*!< Periodic transmit data FIFO space available */
-
-#define USB_OTG_HPTXSTS_PTXQSAV                 0x00FF0000U            /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0               0x00010000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1               0x00020000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2               0x00040000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3               0x00080000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4               0x00100000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5               0x00200000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6               0x00400000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7               0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_HPTXSTS_PTXQTOP                 0xFF000000U            /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0               0x01000000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1               0x02000000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2               0x04000000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3               0x08000000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4               0x10000000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5               0x20000000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6               0x40000000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7               0x80000000U            /*!<Bit 7 */
-
-/********************  Bit definition forUSB_OTG_HAINT register  ********************/
-#define USB_OTG_HAINT_HAINT                   0x0000FFFFU            /*!< Channel interrupts */
-
-/********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/
-#define USB_OTG_DOEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPMSK_STUPM                   0x00000008U            /*!< SETUP phase done mask */
-#define USB_OTG_DOEPMSK_OTEPDM                  0x00000010U            /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received mask */
-#define USB_OTG_DOEPMSK_OPEM                    0x00000100U            /*!< OUT packet error mask */
-#define USB_OTG_DOEPMSK_BOIM                    0x00000200U            /*!< BNA interrupt mask */
-
-/********************  Bit definition forUSB_OTG_GINTSTS register  ********************/
-#define USB_OTG_GINTSTS_CMOD                    0x00000001U            /*!< Current mode of operation */
-#define USB_OTG_GINTSTS_MMIS                    0x00000002U            /*!< Mode mismatch interrupt */
-#define USB_OTG_GINTSTS_OTGINT                  0x00000004U            /*!< OTG interrupt */
-#define USB_OTG_GINTSTS_SOF                     0x00000008U            /*!< Start of frame */
-#define USB_OTG_GINTSTS_RXFLVL                  0x00000010U            /*!< RxFIFO nonempty */
-#define USB_OTG_GINTSTS_NPTXFE                  0x00000020U            /*!< Nonperiodic TxFIFO empty */
-#define USB_OTG_GINTSTS_GINAKEFF                0x00000040U            /*!< Global IN nonperiodic NAK effective */
-#define USB_OTG_GINTSTS_BOUTNAKEFF              0x00000080U            /*!< Global OUT NAK effective */
-#define USB_OTG_GINTSTS_ESUSP                   0x00000400U            /*!< Early suspend */
-#define USB_OTG_GINTSTS_USBSUSP                 0x00000800U            /*!< USB suspend */
-#define USB_OTG_GINTSTS_USBRST                  0x00001000U            /*!< USB reset */
-#define USB_OTG_GINTSTS_ENUMDNE                 0x00002000U            /*!< Enumeration done */
-#define USB_OTG_GINTSTS_ISOODRP                 0x00004000U            /*!< Isochronous OUT packet dropped interrupt */
-#define USB_OTG_GINTSTS_EOPF                    0x00008000U            /*!< End of periodic frame interrupt */
-#define USB_OTG_GINTSTS_IEPINT                  0x00040000U            /*!< IN endpoint interrupt */
-#define USB_OTG_GINTSTS_OEPINT                  0x00080000U            /*!< OUT endpoint interrupt */
-#define USB_OTG_GINTSTS_IISOIXFR                0x00100000U            /*!< Incomplete isochronous IN transfer */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       0x00200000U            /*!< Incomplete periodic transfer */
-#define USB_OTG_GINTSTS_DATAFSUSP               0x00400000U            /*!< Data fetch suspended */
-#define USB_OTG_GINTSTS_HPRTINT                 0x01000000U            /*!< Host port interrupt */
-#define USB_OTG_GINTSTS_HCINT                   0x02000000U            /*!< Host channels interrupt */
-#define USB_OTG_GINTSTS_PTXFE                   0x04000000U            /*!< Periodic TxFIFO empty */
-#define USB_OTG_GINTSTS_CIDSCHG                 0x10000000U            /*!< Connector ID status change */
-#define USB_OTG_GINTSTS_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt */
-#define USB_OTG_GINTSTS_SRQINT                  0x40000000U            /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT                  0x80000000U            /*!< Resume/remote wakeup detected interrupt */
-
-/********************  Bit definition forUSB_OTG_GINTMSK register  ********************/
-#define USB_OTG_GINTMSK_MMISM                   0x00000002U            /*!< Mode mismatch interrupt mask */
-#define USB_OTG_GINTMSK_OTGINT                  0x00000004U            /*!< OTG interrupt mask */
-#define USB_OTG_GINTMSK_SOFM                    0x00000008U            /*!< Start of frame mask */
-#define USB_OTG_GINTMSK_RXFLVLM                 0x00000010U            /*!< Receive FIFO nonempty mask */
-#define USB_OTG_GINTMSK_NPTXFEM                 0x00000020U            /*!< Nonperiodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_GINAKEFFM               0x00000040U            /*!< Global nonperiodic IN NAK effective mask */
-#define USB_OTG_GINTMSK_GONAKEFFM               0x00000080U            /*!< Global OUT NAK effective mask */
-#define USB_OTG_GINTMSK_ESUSPM                  0x00000400U            /*!< Early suspend mask */
-#define USB_OTG_GINTMSK_USBSUSPM                0x00000800U            /*!< USB suspend mask */
-#define USB_OTG_GINTMSK_USBRST                  0x00001000U            /*!< USB reset mask */
-#define USB_OTG_GINTMSK_ENUMDNEM                0x00002000U            /*!< Enumeration done mask */
-#define USB_OTG_GINTMSK_ISOODRPM                0x00004000U            /*!< Isochronous OUT packet dropped interrupt mask */
-#define USB_OTG_GINTMSK_EOPFM                   0x00008000U            /*!< End of periodic frame interrupt mask */
-#define USB_OTG_GINTMSK_EPMISM                  0x00020000U            /*!< Endpoint mismatch interrupt mask */
-#define USB_OTG_GINTMSK_IEPINT                  0x00040000U            /*!< IN endpoints interrupt mask */
-#define USB_OTG_GINTMSK_OEPINT                  0x00080000U            /*!< OUT endpoints interrupt mask */
-#define USB_OTG_GINTMSK_IISOIXFRM               0x00100000U            /*!< Incomplete isochronous IN transfer mask */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         0x00200000U            /*!< Incomplete periodic transfer mask */
-#define USB_OTG_GINTMSK_FSUSPM                  0x00400000U            /*!< Data fetch suspended mask */
-#define USB_OTG_GINTMSK_PRTIM                   0x01000000U            /*!< Host port interrupt mask */
-#define USB_OTG_GINTMSK_HCIM                    0x02000000U            /*!< Host channels interrupt mask */
-#define USB_OTG_GINTMSK_PTXFEM                  0x04000000U            /*!< Periodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_CIDSCHGM                0x10000000U            /*!< Connector ID status change mask */
-#define USB_OTG_GINTMSK_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt mask */
-#define USB_OTG_GINTMSK_SRQIM                   0x40000000U            /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM                    0x80000000U            /*!< Resume/remote wakeup detected interrupt mask */
-
-/********************  Bit definition forUSB_OTG_DAINT register  ********************/
-#define USB_OTG_DAINT_IEPINT                  0x0000FFFFU            /*!< IN endpoint interrupt bits */
-#define USB_OTG_DAINT_OEPINT                  0xFFFF0000U            /*!< OUT endpoint interrupt bits */
-
-/********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/
-#define USB_OTG_HAINTMSK_HAINTM                  0x0000FFFFU            /*!< Channel interrupt mask */
-
-/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
-#define USB_OTG_GRXSTSP_EPNUM                    0x0000000FU            /*!< IN EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_BCNT                     0x00007FF0U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID                     0x00018000U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS                   0x001E0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/
-#define USB_OTG_DAINTMSK_IEPM                    0x0000FFFFU            /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM                    0xFFFF0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for OTG register  ********************/
-
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition for OTG register  ********************/
-
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/
-#define USB_OTG_GRXFSIZ_RXFD                    0x0000FFFFU            /*!< RxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/
-#define USB_OTG_DVBUSDIS_VBUSDT                  0x0000FFFFU            /*!< Device VBUS discharge time */
-
-/********************  Bit definition for OTG register  ********************/
-#define USB_OTG_NPTXFSA                 0x0000FFFFU            /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD                  0xFFFF0000U            /*!< Nonperiodic TxFIFO depth */
-#define USB_OTG_TX0FSA                  0x0000FFFFU            /*!< Endpoint 0 transmit RAM start address */
-#define USB_OTG_TX0FD                   0xFFFF0000U            /*!< Endpoint 0 TxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
-#define USB_OTG_DVBUSPULSE_DVBUSP                  0x00000FFFU            /*!< Device VBUS pulsing time */
-
-/********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/
-#define USB_OTG_GNPTXSTS_NPTXFSAV                0x0000FFFFU            /*!< Nonperiodic TxFIFO space available */
-
-#define USB_OTG_GNPTXSTS_NPTQXSAV                0x00FF0000U            /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0              0x00010000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1              0x00020000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2              0x00040000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3              0x00080000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4              0x00100000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5              0x00200000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6              0x00400000U            /*!<Bit 6 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7              0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_GNPTXSTS_NPTXQTOP                0x7F000000U            /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0              0x01000000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1              0x02000000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2              0x04000000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3              0x08000000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4              0x10000000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5              0x20000000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6              0x40000000U            /*!<Bit 6 */
-
-/********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/
-#define USB_OTG_DTHRCTL_NONISOTHREN             0x00000001U            /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN                0x00000002U            /*!< ISO IN endpoint threshold enable */
-
-#define USB_OTG_DTHRCTL_TXTHRLEN                0x000007FCU            /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0              0x00000004U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1              0x00000008U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2              0x00000010U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3              0x00000020U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4              0x00000040U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5              0x00000080U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6              0x00000100U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7              0x00000200U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8              0x00000400U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_RXTHREN                 0x00010000U            /*!< Receive threshold enable */
-
-#define USB_OTG_DTHRCTL_RXTHRLEN                0x03FE0000U            /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0              0x00020000U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1              0x00040000U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2              0x00080000U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3              0x00100000U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4              0x00200000U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5              0x00400000U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6              0x00800000U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7              0x01000000U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8              0x02000000U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_ARPEN                   0x08000000U            /*!< Arbiter parking enable */
-
-/********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM               0x0000FFFFU            /*!< IN EP Tx FIFO empty interrupt mask bits */
-
-/********************  Bit definition forUSB_OTG_DEACHINT register  ********************/
-#define USB_OTG_DEACHINT_IEP1INT                 0x00000002U            /*!< IN endpoint 1interrupt bit */
-#define USB_OTG_DEACHINT_OEP1INT                 0x00020000U            /*!< OUT endpoint 1 interrupt bit */
-
-/********************  Bit definition forUSB_OTG_GCCFG register  ********************/
-#define USB_OTG_GCCFG_PWRDWN                  0x00010000U            /*!< Power down */
-#define USB_OTG_GCCFG_I2CPADEN                0x00020000U            /*!< Enable I2C bus connection for the external I2C PHY interface */
-#define USB_OTG_GCCFG_VBUSASEN                0x00040000U            /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_VBUSBSEN                0x00080000U            /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_SOFOUTEN                0x00100000U            /*!< SOF output enable */
-#define USB_OTG_GCCFG_NOVBUSSENS              0x00200000U            /*!< VBUS sensing disable option */
-
-/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
-#define USB_OTG_DEACHINTMSK_IEP1INTM                0x00000002U            /*!< IN Endpoint 1 interrupt mask bit */
-#define USB_OTG_DEACHINTMSK_OEP1INTM                0x00020000U            /*!< OUT Endpoint 1 interrupt mask bit */
-
-/********************  Bit definition forUSB_OTG_CID register  ********************/
-#define USB_OTG_CID_PRODUCT_ID              0xFFFFFFFFU            /*!< Product ID field */
-
-/********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/
-#define USB_OTG_DIEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPEACHMSK1_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
-
-/********************  Bit definition forUSB_OTG_HPRT register  ********************/
-#define USB_OTG_HPRT_PCSTS                   0x00000001U            /*!< Port connect status */
-#define USB_OTG_HPRT_PCDET                   0x00000002U            /*!< Port connect detected */
-#define USB_OTG_HPRT_PENA                    0x00000004U            /*!< Port enable */
-#define USB_OTG_HPRT_PENCHNG                 0x00000008U            /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA                    0x00000010U            /*!< Port overcurrent active */
-#define USB_OTG_HPRT_POCCHNG                 0x00000020U            /*!< Port overcurrent change */
-#define USB_OTG_HPRT_PRES                    0x00000040U            /*!< Port resume */
-#define USB_OTG_HPRT_PSUSP                   0x00000080U            /*!< Port suspend */
-#define USB_OTG_HPRT_PRST                    0x00000100U            /*!< Port reset */
-
-#define USB_OTG_HPRT_PLSTS                   0x00000C00U            /*!< Port line status */
-#define USB_OTG_HPRT_PLSTS_0                 0x00000400U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PLSTS_1                 0x00000800U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PPWR                    0x00001000U            /*!< Port power */
-
-#define USB_OTG_HPRT_PTCTL                   0x0001E000U            /*!< Port test control */
-#define USB_OTG_HPRT_PTCTL_0                 0x00002000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PTCTL_1                 0x00004000U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PTCTL_2                 0x00008000U            /*!<Bit 2 */
-#define USB_OTG_HPRT_PTCTL_3                 0x00010000U            /*!<Bit 3 */
-
-#define USB_OTG_HPRT_PSPD                    0x00060000U            /*!< Port speed */
-#define USB_OTG_HPRT_PSPD_0                  0x00020000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PSPD_1                  0x00040000U            /*!<Bit 1 */
-
-/********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/
-#define USB_OTG_DOEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DOEPEACHMSK1_TXFURM                  0x00000100U            /*!< OUT packet error mask */
-#define USB_OTG_DOEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_BERRM                   0x00001000U            /*!< Bubble error interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NYETM                   0x00004000U            /*!< NYET interrupt mask */
-
-/********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/
-#define USB_OTG_HPTXFSIZ_PTXSA                   0x0000FFFFU            /*!< Host periodic TxFIFO start address */
-#define USB_OTG_HPTXFSIZ_PTXFD                   0xFFFF0000U            /*!< Host periodic TxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/
-#define USB_OTG_DIEPCTL_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
-#define USB_OTG_DIEPCTL_USBAEP                  0x00008000U            /*!< USB active endpoint */
-#define USB_OTG_DIEPCTL_EONUM_DPID              0x00010000U            /*!< Even/odd frame */
-#define USB_OTG_DIEPCTL_NAKSTS                  0x00020000U            /*!< NAK status */
-
-#define USB_OTG_DIEPCTL_EPTYP                   0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_DIEPCTL_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_STALL                   0x00200000U            /*!< STALL handshake */
-
-#define USB_OTG_DIEPCTL_TXFNUM                  0x03C00000U            /*!< TxFIFO number */
-#define USB_OTG_DIEPCTL_TXFNUM_0                0x00400000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                0x00800000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                0x01000000U            /*!<Bit 2 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                0x02000000U            /*!<Bit 3 */
-#define USB_OTG_DIEPCTL_CNAK                    0x04000000U            /*!< Clear NAK */
-#define USB_OTG_DIEPCTL_SNAK                    0x08000000U            /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          0x10000000U            /*!< Set DATA0 PID */
-#define USB_OTG_DIEPCTL_SODDFRM                 0x20000000U            /*!< Set odd frame */
-#define USB_OTG_DIEPCTL_EPDIS                   0x40000000U            /*!< Endpoint disable */
-#define USB_OTG_DIEPCTL_EPENA                   0x80000000U            /*!< Endpoint enable */
-
-/********************  Bit definition forUSB_OTG_HCCHAR register  ********************/
-#define USB_OTG_HCCHAR_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
-
-#define USB_OTG_HCCHAR_EPNUM                   0x00007800U            /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPNUM_1                 0x00001000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_EPNUM_2                 0x00002000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_EPNUM_3                 0x00004000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_EPDIR                   0x00008000U            /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV                   0x00020000U            /*!< Low-speed device */
-
-#define USB_OTG_HCCHAR_EPTYP                   0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_MC                      0x00300000U            /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                    0x00100000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_MC_1                    0x00200000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_DAD                     0x1FC00000U            /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                   0x00400000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_DAD_1                   0x00800000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_DAD_2                   0x01000000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_DAD_3                   0x02000000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_DAD_4                   0x04000000U            /*!<Bit 4 */
-#define USB_OTG_HCCHAR_DAD_5                   0x08000000U            /*!<Bit 5 */
-#define USB_OTG_HCCHAR_DAD_6                   0x10000000U            /*!<Bit 6 */
-#define USB_OTG_HCCHAR_ODDFRM                  0x20000000U            /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS                   0x40000000U            /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA                   0x80000000U            /*!< Channel enable */
-
-/********************  Bit definition forUSB_OTG_HCSPLT register  ********************/
-
-#define USB_OTG_HCSPLT_PRTADDR                 0x0000007FU            /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_PRTADDR_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_PRTADDR_2               0x00000004U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_PRTADDR_3               0x00000008U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_PRTADDR_4               0x00000010U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_PRTADDR_5               0x00000020U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_PRTADDR_6               0x00000040U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_HUBADDR                 0x00003F80U            /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0               0x00000080U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_HUBADDR_1               0x00000100U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_HUBADDR_2               0x00000200U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_HUBADDR_3               0x00000400U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_HUBADDR_4               0x00000800U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_HUBADDR_5               0x00001000U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_HUBADDR_6               0x00002000U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_XACTPOS                 0x0000C000U            /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0               0x00004000U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_XACTPOS_1               0x00008000U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_COMPLSPLT               0x00010000U            /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN                 0x80000000U            /*!< Split enable */
-
-/********************  Bit definition forUSB_OTG_HCINT register  ********************/
-#define USB_OTG_HCINT_XFRC                    0x00000001U            /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH                     0x00000002U            /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINT_STALL                   0x00000008U            /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK                     0x00000010U            /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK                     0x00000020U            /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET                    0x00000040U            /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR                   0x00000080U            /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR                   0x00000100U            /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR                   0x00000200U            /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR                   0x00000400U            /*!< Data toggle error */
-
-/********************  Bit definition forUSB_OTG_DIEPINT register  ********************/
-#define USB_OTG_DIEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_TOC                     0x00000008U            /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE                  0x00000010U            /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNE                  0x00000040U            /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE                    0x00000080U            /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN              0x00000100U            /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA                     0x00000200U            /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS               0x00000800U            /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR                    0x00001000U            /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK                     0x00002000U            /*!< NAK interrupt */
-
-/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
-#define USB_OTG_HCINTMSK_XFRCM                   0x00000001U            /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM                    0x00000002U            /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM                  0x00000008U            /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM                    0x00000010U            /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM                    0x00000020U            /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET                    0x00000040U            /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM                  0x00000080U            /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM                  0x00000100U            /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM                  0x00000200U            /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM                  0x00000400U            /*!< Data toggle error mask */
-
-/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
-
-#define USB_OTG_DIEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT                  0x60000000U            /*!< Packet count */
-/********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/
-#define USB_OTG_HCTSIZ_XFRSIZ                    0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT                    0x1FF80000U            /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING                    0x80000000U            /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID                      0x60000000U            /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                    0x20000000U            /*!<Bit 0 */
-#define USB_OTG_HCTSIZ_DPID_1                    0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/
-#define USB_OTG_DIEPDMA_DMAADDR                  0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition forUSB_OTG_HCDMA register  ********************/
-#define USB_OTG_HCDMA_DMAADDR                    0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/
-#define USB_OTG_DTXFSTS_INEPTFSAV                0x0000FFFFU            /*!< IN endpoint TxFIFO space avail */
-
-/********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/
-#define USB_OTG_DIEPTXF_INEPTXSA                 0x0000FFFFU            /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD                 0xFFFF0000U            /*!< IN endpoint TxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/
-
-#define USB_OTG_DOEPCTL_MPSIZ                     0x000007FFU            /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP                    0x00008000U            /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS                    0x00020000U            /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            0x10000000U            /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM                   0x20000000U            /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP                     0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                   0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DOEPCTL_EPTYP_1                   0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_SNPM                      0x00100000U            /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL                     0x00200000U            /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK                      0x04000000U            /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK                      0x08000000U            /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS                     0x40000000U            /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA                     0x80000000U            /*!< Endpoint enable */
-
-/********************  Bit definition forUSB_OTG_DOEPINT register  ********************/
-#define USB_OTG_DOEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_STUP                    0x00000008U            /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS                 0x00000010U            /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_NYET                    0x00004000U            /*!< NYET interrupt */
-
-/********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/
-
-#define USB_OTG_DOEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-
-#define USB_OTG_DOEPTSIZ_STUPCNT                 0x60000000U            /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0               0x20000000U            /*!<Bit 0 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1               0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition for PCGCCTL register  ********************/
-#define USB_OTG_PCGCCTL_STOPCLK                 0x00000001U            /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK                 0x00000002U            /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP                 0x00000010U            /*!<Bit 1 */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
- 
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
-                                       ((INSTANCE) == ADC2) || \
-                                       ((INSTANCE) == ADC3))
-
-/******************************* CAN Instances ********************************/
-#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
-                                       ((INSTANCE) == CAN2))
- 
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DAC Instances ********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/******************************** DMA Instances *******************************/
-#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
-                                              ((INSTANCE) == DMA1_Stream1) || \
-                                              ((INSTANCE) == DMA1_Stream2) || \
-                                              ((INSTANCE) == DMA1_Stream3) || \
-                                              ((INSTANCE) == DMA1_Stream4) || \
-                                              ((INSTANCE) == DMA1_Stream5) || \
-                                              ((INSTANCE) == DMA1_Stream6) || \
-                                              ((INSTANCE) == DMA1_Stream7) || \
-                                              ((INSTANCE) == DMA2_Stream0) || \
-                                              ((INSTANCE) == DMA2_Stream1) || \
-                                              ((INSTANCE) == DMA2_Stream2) || \
-                                              ((INSTANCE) == DMA2_Stream3) || \
-                                              ((INSTANCE) == DMA2_Stream4) || \
-                                              ((INSTANCE) == DMA2_Stream5) || \
-                                              ((INSTANCE) == DMA2_Stream6) || \
-                                              ((INSTANCE) == DMA2_Stream7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOF) || \
-                                        ((INSTANCE) == GPIOG) || \
-                                        ((INSTANCE) == GPIOH) || \
-                                        ((INSTANCE) == GPIOI))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2) || \
-                                       ((INSTANCE) == I2C3))
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI2) || \
-                                    ((INSTANCE) == SPI3))
-
-/*************************** I2S Extended Instances ***************************/
-#define IS_I2S_ALL_INSTANCE_EXT(PERIPH)  (((INSTANCE) == SPI2)    || \
-                                          ((INSTANCE) == SPI3)    || \
-                                          ((INSTANCE) == I2S2ext) || \
-                                          ((INSTANCE) == I2S3ext))
-
-/******************************* RNG Instances ********************************/
-#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-
-/*************************** SPI Extended Instances ***************************/
-#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1)    || \
-                                           ((INSTANCE) == SPI2)    || \
-                                           ((INSTANCE) == SPI3)    || \
-                                           ((INSTANCE) == I2S2ext) || \
-                                           ((INSTANCE) == I2S3ext))
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
-                                   ((INSTANCE) == TIM2)   || \
-                                   ((INSTANCE) == TIM3)   || \
-                                   ((INSTANCE) == TIM4)   || \
-                                   ((INSTANCE) == TIM5)   || \
-                                   ((INSTANCE) == TIM6)   || \
-                                   ((INSTANCE) == TIM7)   || \
-                                   ((INSTANCE) == TIM8)   || \
-                                   ((INSTANCE) == TIM9)   || \
-                                   ((INSTANCE) == TIM10)  || \
-                                   ((INSTANCE) == TIM11)  || \
-                                   ((INSTANCE) == TIM12)  || \
-                                   ((INSTANCE) == TIM13)  || \
-                                   ((INSTANCE) == TIM14))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
-                                         ((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM8)  || \
-                                         ((INSTANCE) == TIM9)  || \
-                                         ((INSTANCE) == TIM10) || \
-                                         ((INSTANCE) == TIM11) || \
-                                         ((INSTANCE) == TIM12) || \
-                                         ((INSTANCE) == TIM13) || \
-                                         ((INSTANCE) == TIM14))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM8) || \
-                                       ((INSTANCE) == TIM9) || \
-                                       ((INSTANCE) == TIM12))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8))
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM8))
-
-/******************** TIM Instances : Advanced-control timers *****************/
-#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                            ((INSTANCE) == TIM8))
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8))
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM6) || \
-                                       ((INSTANCE) == TIM7) || \
-                                       ((INSTANCE) == TIM8))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM8))
-
-/************ TIM Instances : DMA requests generation (COMDE) *****************/
-#define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM8)) 
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                             ((INSTANCE) == TIM2) || \
-                                             ((INSTANCE) == TIM3) || \
-                                             ((INSTANCE) == TIM4) || \
-                                             ((INSTANCE) == TIM5) || \
-                                             ((INSTANCE) == TIM8))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM6) || \
-                                          ((INSTANCE) == TIM7) || \
-                                          ((INSTANCE) == TIM8) || \
-                                          ((INSTANCE) == TIM9) || \
-                                          ((INSTANCE) == TIM12))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8) || \
-                                         ((INSTANCE) == TIM9) || \
-                                         ((INSTANCE) == TIM12))
-
-/********************** TIM Instances : 32 bit Counter ************************/
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
-                                              ((INSTANCE) == TIM5))
-
-/***************** TIM Instances : external trigger input availabe ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                        ((INSTANCE) == TIM2) || \
-                                        ((INSTANCE) == TIM3) || \
-                                        ((INSTANCE) == TIM4) || \
-                                        ((INSTANCE) == TIM5) || \
-                                        ((INSTANCE) == TIM8))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM11))
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM1) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM5) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM8) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM12) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM13) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM14) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-/************ TIM Instances : complementary output(s) available ***************/
-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
-   ((((INSTANCE) == TIM1) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3)))            \
-    ||                                          \
-    (((INSTANCE) == TIM8) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3))))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3) || \
-                                     ((INSTANCE) == USART6))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5)  || \
-                                    ((INSTANCE) == USART6))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3) || \
-                                           ((INSTANCE) == USART6))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3) || \
-                                         ((INSTANCE) == USART6))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5)  || \
-                                    ((INSTANCE) == USART6))     
-
-/*********************** PCD Instances ****************************************/
-/*********************** PCD Instances ****************************************/
-#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
-                                        ((INSTANCE) == USB_OTG_HS))
-
-/*********************** HCD Instances ****************************************/
-#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
-                                       ((INSTANCE) == USB_OTG_HS))
-
-/*********************** HCD Instances ****************************************/
-#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
-                                       ((INSTANCE) == USB_OTG_HS))
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/****************************** SDIO Instances ********************************/
-#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
-
-/****************************** USB Exported Constants ************************/
-#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                8U
-#define USB_OTG_FS_MAX_IN_ENDPOINTS                    4U    /* Including EP0 */
-#define USB_OTG_FS_MAX_OUT_ENDPOINTS                   4U    /* Including EP0 */
-#define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */
-
-#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR                12U
-#define USB_OTG_HS_MAX_IN_ENDPOINTS                    6U    /* Including EP0 */
-#define USB_OTG_HS_MAX_OUT_ENDPOINTS                   6U    /* Including EP0 */
-#define USB_OTG_HS_TOTAL_FIFO_SIZE                     4096U /* in Bytes */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32F4xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */
-/*  product lines within the same STM32F4 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-#define FMC_IRQn              FSMC_IRQn
-
-/* Aliases for __IRQHandler */
-#define FMC_IRQHandler        FSMC_IRQHandler
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32F415xx_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/cmsis/stm32f417xx.h b/stmhal/cmsis/stm32f417xx.h
deleted file mode 100644
index c72821fb16..0000000000
--- a/stmhal/cmsis/stm32f417xx.h
+++ /dev/null
@@ -1,8328 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f417xx.h
-  * @author  MCD Application Team
-  * @version V2.5.1
-  * @date    28-June-2016
-  * @brief   CMSIS STM32F417xx Device Peripheral Access Layer Header File.
-  *
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - peripherals registers declarations and bits definition
-  *           - Macros to access peripheral’s registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f417xx
-  * @{
-  */
-    
-#ifndef __STM32F417xx_H
-#define __STM32F417xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-  
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-
-/**
-  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
-  */
-#define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */
-#define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */
-#define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1U       /*!< FPU present                                   */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32F4XX Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-typedef enum
-{
-/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
-  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
-/******  STM32 specific Interrupt Numbers **********************************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
-  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
-  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
-  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
-  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
-  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
-  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
-  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
-  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
-  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
-  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
-  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
-  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
-  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
-  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
-  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
-  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
-  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */    
-  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
-  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
-  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
-  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
-  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
-  FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                             */
-  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
-  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
-  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
-  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
-  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
-  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
-  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
-  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
-  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
-  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
-  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
-  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
-  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
-  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
-  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
-  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
-  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
-  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
-  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
-  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
-  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
-  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
-  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
-  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
-  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
-  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
-  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
-  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
-  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
-  CRYP_IRQn                   = 79,     /*!< CRYP crypto global interrupt                                      */
-  HASH_RNG_IRQn               = 80,     /*!< Hash and Rng global interrupt                                     */
-  FPU_IRQn                    = 81      /*!< FPU global interrupt                                              */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
-#include "system_stm32f4xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */      
-  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
-  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
-  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
-  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
-  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
-  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
-  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
-  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
-  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
-  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
-  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
-  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
-  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
-  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
-  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
-                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
-} ADC_Common_TypeDef;
-
-
-/** 
-  * @brief Controller Area Network TxMailBox 
-  */
-
-typedef struct
-{
-  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
-  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
-  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
-  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
-} CAN_TxMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FIFOMailBox 
-  */
-  
-typedef struct
-{
-  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
-  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
-  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
-  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
-} CAN_FIFOMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FilterRegister 
-  */
-  
-typedef struct
-{
-  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
-  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
-} CAN_FilterRegister_TypeDef;
-
-/** 
-  * @brief Controller Area Network 
-  */
-  
-typedef struct
-{
-  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
-  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
-  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
-  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
-  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
-  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
-  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
-  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
-  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
-  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
-  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
-  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
-  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
-  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
-  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
-  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
-  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
-  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
-  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
-  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
-  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */ 
-  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
-} CAN_TypeDef;
-
-/** 
-  * @brief CRC calculation unit 
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
-  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */
-  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
-  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
-  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
-  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
-  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
-  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
-  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
-  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
-  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
-  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
-  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
-  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
-  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
-  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
-  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
-  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
-  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
-  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DCMI
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
-  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
-  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
-  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
-  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
-  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
-  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
-  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
-  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
-  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
-  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
-} DCMI_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
-  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
-  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
-  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
-  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
-  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
-} DMA_Stream_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
-  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
-  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
-  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
-} DMA_TypeDef;
-
-
-/** 
-  * @brief Ethernet MAC
-  */
-
-typedef struct
-{
-  __IO uint32_t MACCR;
-  __IO uint32_t MACFFR;
-  __IO uint32_t MACHTHR;
-  __IO uint32_t MACHTLR;
-  __IO uint32_t MACMIIAR;
-  __IO uint32_t MACMIIDR;
-  __IO uint32_t MACFCR;
-  __IO uint32_t MACVLANTR;             /*    8 */
-  uint32_t      RESERVED0[2];
-  __IO uint32_t MACRWUFFR;             /*   11 */
-  __IO uint32_t MACPMTCSR;
-  uint32_t      RESERVED1[2];
-  __IO uint32_t MACSR;                 /*   15 */
-  __IO uint32_t MACIMR;
-  __IO uint32_t MACA0HR;
-  __IO uint32_t MACA0LR;
-  __IO uint32_t MACA1HR;
-  __IO uint32_t MACA1LR;
-  __IO uint32_t MACA2HR;
-  __IO uint32_t MACA2LR;
-  __IO uint32_t MACA3HR;
-  __IO uint32_t MACA3LR;               /*   24 */
-  uint32_t      RESERVED2[40];
-  __IO uint32_t MMCCR;                 /*   65 */
-  __IO uint32_t MMCRIR;
-  __IO uint32_t MMCTIR;
-  __IO uint32_t MMCRIMR;
-  __IO uint32_t MMCTIMR;               /*   69 */
-  uint32_t      RESERVED3[14];
-  __IO uint32_t MMCTGFSCCR;            /*   84 */
-  __IO uint32_t MMCTGFMSCCR;
-  uint32_t      RESERVED4[5];
-  __IO uint32_t MMCTGFCR;
-  uint32_t      RESERVED5[10];
-  __IO uint32_t MMCRFCECR;
-  __IO uint32_t MMCRFAECR;
-  uint32_t      RESERVED6[10];
-  __IO uint32_t MMCRGUFCR;
-  uint32_t      RESERVED7[334];
-  __IO uint32_t PTPTSCR;
-  __IO uint32_t PTPSSIR;
-  __IO uint32_t PTPTSHR;
-  __IO uint32_t PTPTSLR;
-  __IO uint32_t PTPTSHUR;
-  __IO uint32_t PTPTSLUR;
-  __IO uint32_t PTPTSAR;
-  __IO uint32_t PTPTTHR;
-  __IO uint32_t PTPTTLR;
-  __IO uint32_t RESERVED8;
-  __IO uint32_t PTPTSSR;
-  uint32_t      RESERVED9[565];
-  __IO uint32_t DMABMR;
-  __IO uint32_t DMATPDR;
-  __IO uint32_t DMARPDR;
-  __IO uint32_t DMARDLAR;
-  __IO uint32_t DMATDLAR;
-  __IO uint32_t DMASR;
-  __IO uint32_t DMAOMR;
-  __IO uint32_t DMAIER;
-  __IO uint32_t DMAMFBOCR;
-  __IO uint32_t DMARSWTR;
-  uint32_t      RESERVED10[8];
-  __IO uint32_t DMACHTDR;
-  __IO uint32_t DMACHRDR;
-  __IO uint32_t DMACHTBAR;
-  __IO uint32_t DMACHRBAR;
-} ETH_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
-  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
-  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
-  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
-  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
-  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-
-typedef struct
-{
-  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */
-  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */
-  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */
-  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */
-  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */
-  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */
-} FLASH_TypeDef;
-
-
-/** 
-  * @brief Flexible Static Memory Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */   
-} FSMC_Bank1_TypeDef; 
-
-/** 
-  * @brief Flexible Static Memory Controller Bank1E
-  */
-  
-typedef struct
-{
-  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
-} FSMC_Bank1E_TypeDef;
-
-/** 
-  * @brief Flexible Static Memory Controller Bank2
-  */
-  
-typedef struct
-{
-  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */
-  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */
-  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */
-  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
-  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */
-  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */
-  uint32_t      RESERVED1;  /*!< Reserved, 0x78                                                            */
-  uint32_t      RESERVED2;  /*!< Reserved, 0x7C                                                            */
-  __IO uint32_t PCR3;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */
-  __IO uint32_t SR3;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */
-  __IO uint32_t PMEM3;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */
-  __IO uint32_t PATT3;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
-  uint32_t      RESERVED3;  /*!< Reserved, 0x90                                                            */
-  __IO uint32_t ECCR3;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */
-} FSMC_Bank2_3_TypeDef;
-
-/** 
-  * @brief Flexible Static Memory Controller Bank4
-  */
-  
-typedef struct
-{
-  __IO uint32_t PCR4;       /*!< PC Card  control register 4,                       Address offset: 0xA0 */
-  __IO uint32_t SR4;        /*!< PC Card  FIFO status and interrupt register 4,     Address offset: 0xA4 */
-  __IO uint32_t PMEM4;      /*!< PC Card  Common memory space timing register 4,    Address offset: 0xA8 */
-  __IO uint32_t PATT4;      /*!< PC Card  Attribute memory space timing register 4, Address offset: 0xAC */
-  __IO uint32_t PIO4;       /*!< PC Card  I/O space timing register 4,              Address offset: 0xB0 */
-} FSMC_Bank4_TypeDef; 
-
-
-/** 
-  * @brief General Purpose I/O
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
-  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
-  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
-  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
-  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
-  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
-  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
-  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/** 
-  * @brief System configuration controller
-  */
-  
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */ 
-  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */
-  __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */
-  __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */
-  __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */
-  __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */
-  __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
-  __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
-  __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
-  __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
-  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
-  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
-  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
-  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
-  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
-  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
-  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
-  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
-  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
-  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
-  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
-  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
-  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
-  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
-  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
-  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
-  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
-  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
-  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
-  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
-  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
-
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-
-typedef struct
-{
-  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
-  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
-  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
-  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
-  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
-  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
-  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */
-  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
-  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */
-  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
-  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */
-  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */
-  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */
-  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */
-  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
-  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */
-  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
-  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
-  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
-  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
-  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
-  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
-  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
-  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
-  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
-  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
-  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
-  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
-  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
-  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
-  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
-  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
-  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
-  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
-  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
-  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
-  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
-} RTC_TypeDef;
-
-
-/** 
-  * @brief SD host Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t POWER;          /*!< SDIO power control register,    Address offset: 0x00 */
-  __IO uint32_t CLKCR;          /*!< SDI clock control register,     Address offset: 0x04 */
-  __IO uint32_t ARG;            /*!< SDIO argument register,         Address offset: 0x08 */
-  __IO uint32_t CMD;            /*!< SDIO command register,          Address offset: 0x0C */
-  __I uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */
-  __I uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */
-  __I uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */
-  __I uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */
-  __I uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */
-  __IO uint32_t DTIMER;         /*!< SDIO data timer register,       Address offset: 0x24 */
-  __IO uint32_t DLEN;           /*!< SDIO data length register,      Address offset: 0x28 */
-  __IO uint32_t DCTRL;          /*!< SDIO data control register,     Address offset: 0x2C */
-  __I uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */
-  __I uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */
-  __IO uint32_t ICR;            /*!< SDIO interrupt clear register,  Address offset: 0x38 */
-  __IO uint32_t MASK;           /*!< SDIO mask register,             Address offset: 0x3C */
-  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
-  __I uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */
-  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
-  __IO uint32_t FIFO;           /*!< SDIO data FIFO register,        Address offset: 0x80 */
-} SDIO_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
-  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
-  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
-  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Crypto Processor
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;         /*!< CRYP control register,                                    Address offset: 0x00 */
-  __IO uint32_t SR;         /*!< CRYP status register,                                     Address offset: 0x04 */
-  __IO uint32_t DR;         /*!< CRYP data input register,                                 Address offset: 0x08 */
-  __IO uint32_t DOUT;       /*!< CRYP data output register,                                Address offset: 0x0C */
-  __IO uint32_t DMACR;      /*!< CRYP DMA control register,                                Address offset: 0x10 */
-  __IO uint32_t IMSCR;      /*!< CRYP interrupt mask set/clear register,                   Address offset: 0x14 */
-  __IO uint32_t RISR;       /*!< CRYP raw interrupt status register,                       Address offset: 0x18 */
-  __IO uint32_t MISR;       /*!< CRYP masked interrupt status register,                    Address offset: 0x1C */
-  __IO uint32_t K0LR;       /*!< CRYP key left  register 0,                                Address offset: 0x20 */
-  __IO uint32_t K0RR;       /*!< CRYP key right register 0,                                Address offset: 0x24 */
-  __IO uint32_t K1LR;       /*!< CRYP key left  register 1,                                Address offset: 0x28 */
-  __IO uint32_t K1RR;       /*!< CRYP key right register 1,                                Address offset: 0x2C */
-  __IO uint32_t K2LR;       /*!< CRYP key left  register 2,                                Address offset: 0x30 */
-  __IO uint32_t K2RR;       /*!< CRYP key right register 2,                                Address offset: 0x34 */
-  __IO uint32_t K3LR;       /*!< CRYP key left  register 3,                                Address offset: 0x38 */
-  __IO uint32_t K3RR;       /*!< CRYP key right register 3,                                Address offset: 0x3C */
-  __IO uint32_t IV0LR;      /*!< CRYP initialization vector left-word  register 0,         Address offset: 0x40 */
-  __IO uint32_t IV0RR;      /*!< CRYP initialization vector right-word register 0,         Address offset: 0x44 */
-  __IO uint32_t IV1LR;      /*!< CRYP initialization vector left-word  register 1,         Address offset: 0x48 */
-  __IO uint32_t IV1RR;      /*!< CRYP initialization vector right-word register 1,         Address offset: 0x4C */
-  __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0,        Address offset: 0x50 */
-  __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1,        Address offset: 0x54 */
-  __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2,        Address offset: 0x58 */
-  __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3,        Address offset: 0x5C */
-  __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4,        Address offset: 0x60 */
-  __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5,        Address offset: 0x64 */
-  __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6,        Address offset: 0x68 */
-  __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7,        Address offset: 0x6C */
-  __IO uint32_t CSGCM0R;    /*!< CRYP GCM/GMAC context swap register 0,                    Address offset: 0x70 */
-  __IO uint32_t CSGCM1R;    /*!< CRYP GCM/GMAC context swap register 1,                    Address offset: 0x74 */
-  __IO uint32_t CSGCM2R;    /*!< CRYP GCM/GMAC context swap register 2,                    Address offset: 0x78 */
-  __IO uint32_t CSGCM3R;    /*!< CRYP GCM/GMAC context swap register 3,                    Address offset: 0x7C */
-  __IO uint32_t CSGCM4R;    /*!< CRYP GCM/GMAC context swap register 4,                    Address offset: 0x80 */
-  __IO uint32_t CSGCM5R;    /*!< CRYP GCM/GMAC context swap register 5,                    Address offset: 0x84 */
-  __IO uint32_t CSGCM6R;    /*!< CRYP GCM/GMAC context swap register 6,                    Address offset: 0x88 */
-  __IO uint32_t CSGCM7R;    /*!< CRYP GCM/GMAC context swap register 7,                    Address offset: 0x8C */
-} CRYP_TypeDef;
-
-/** 
-  * @brief HASH
-  */
-  
-typedef struct 
-{
-  __IO uint32_t CR;               /*!< HASH control register,          Address offset: 0x00        */
-  __IO uint32_t DIN;              /*!< HASH data input register,       Address offset: 0x04        */
-  __IO uint32_t STR;              /*!< HASH start register,            Address offset: 0x08        */
-  __IO uint32_t HR[5];            /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */
-  __IO uint32_t IMR;              /*!< HASH interrupt enable register, Address offset: 0x20        */
-  __IO uint32_t SR;               /*!< HASH status register,           Address offset: 0x24        */
-       uint32_t RESERVED[52];     /*!< Reserved, 0x28-0xF4                                         */
-  __IO uint32_t CSR[54];          /*!< HASH context swap registers,    Address offset: 0x0F8-0x1CC */
-} HASH_TypeDef;
-
-/** 
-  * @brief HASH_DIGEST
-  */
-  
-typedef struct 
-{
-  __IO uint32_t HR[8];     /*!< HASH digest registers,          Address offset: 0x310-0x32C */ 
-} HASH_DIGEST_TypeDef;
-
-/** 
-  * @brief RNG
-  */
-  
-typedef struct 
-{
-  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
-  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
-  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
-} RNG_TypeDef;
-
-
- 
-/** 
-  * @brief __USB_OTG_Core_register
-  */
-typedef struct
-{
-  __IO uint32_t GOTGCTL;      /*!<  USB_OTG Control and Status Register    000h*/
-  __IO uint32_t GOTGINT;      /*!<  USB_OTG Interrupt Register             004h*/
-  __IO uint32_t GAHBCFG;      /*!<  Core AHB Configuration Register    008h*/
-  __IO uint32_t GUSBCFG;      /*!<  Core USB Configuration Register    00Ch*/
-  __IO uint32_t GRSTCTL;      /*!<  Core Reset Register                010h*/
-  __IO uint32_t GINTSTS;      /*!<  Core Interrupt Register            014h*/
-  __IO uint32_t GINTMSK;      /*!<  Core Interrupt Mask Register       018h*/
-  __IO uint32_t GRXSTSR;      /*!<  Receive Sts Q Read Register        01Ch*/
-  __IO uint32_t GRXSTSP;      /*!<  Receive Sts Q Read & POP Register  020h*/
-  __IO uint32_t GRXFSIZ;      /* Receive FIFO Size Register         024h*/
-  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!<  EP0 / Non Periodic Tx FIFO Size Register 028h*/
-  __IO uint32_t HNPTXSTS;     /*!<  Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
-  uint32_t Reserved30[2];     /* Reserved                           030h*/
-  __IO uint32_t GCCFG;        /* General Purpose IO Register        038h*/
-  __IO uint32_t CID;          /* User ID Register                   03Ch*/
-  uint32_t  Reserved40[48];   /* Reserved                      040h-0FFh*/
-  __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg     100h*/
-  __IO uint32_t DIEPTXF[0x0F];/* dev Periodic Transmit FIFO */
-}
-USB_OTG_GlobalTypeDef;
-
-
-
-/** 
-  * @brief __device_Registers
-  */
-typedef struct 
-{
-  __IO uint32_t DCFG;         /* dev Configuration Register   800h*/
-  __IO uint32_t DCTL;         /* dev Control Register         804h*/
-  __IO uint32_t DSTS;         /* dev Status Register (RO)     808h*/
-  uint32_t Reserved0C;           /* Reserved                     80Ch*/
-  __IO uint32_t DIEPMSK;   /* dev IN Endpoint Mask         810h*/
-  __IO uint32_t DOEPMSK;  /* dev OUT Endpoint Mask        814h*/
-  __IO uint32_t DAINT;     /* dev All Endpoints Itr Reg    818h*/
-  __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask   81Ch*/
-  uint32_t  Reserved20;          /* Reserved                     820h*/
-  uint32_t Reserved9;       /* Reserved                     824h*/
-  __IO uint32_t DVBUSDIS;    /* dev VBUS discharge Register  828h*/
-  __IO uint32_t DVBUSPULSE;  /* dev VBUS Pulse Register      82Ch*/
-  __IO uint32_t DTHRCTL;     /* dev thr                      830h*/
-  __IO uint32_t DIEPEMPMSK; /* dev empty msk             834h*/
-  __IO uint32_t DEACHINT;    /* dedicated EP interrupt       838h*/
-  __IO uint32_t DEACHMSK;    /* dedicated EP msk             83Ch*/  
-  uint32_t Reserved40;      /* dedicated EP mask           840h*/
-  __IO uint32_t DINEP1MSK;  /* dedicated EP mask           844h*/
-  uint32_t  Reserved44[15];      /* Reserved                 844-87Ch*/
-  __IO uint32_t DOUTEP1MSK; /* dedicated EP msk            884h*/   
-}
-USB_OTG_DeviceTypeDef;
-
-
-/** 
-  * @brief __IN_Endpoint-Specific_Register
-  */
-typedef struct 
-{
-  __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
-  uint32_t Reserved04;             /* Reserved                       900h + (ep_num * 20h) + 04h*/
-  __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg     900h + (ep_num * 20h) + 08h*/
-  uint32_t Reserved0C;             /* Reserved                       900h + (ep_num * 20h) + 0Ch*/
-  __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size   900h + (ep_num * 20h) + 10h*/
-  __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h*/
-  __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
-  uint32_t Reserved18;             /* Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
-}
-USB_OTG_INEndpointTypeDef;
-
-
-/** 
-  * @brief __OUT_Endpoint-Specific_Registers
-  */
-typedef struct 
-{
-  __IO uint32_t DOEPCTL;       /* dev OUT Endpoint Control Reg  B00h + (ep_num * 20h) + 00h*/
-  uint32_t Reserved04;         /* Reserved                      B00h + (ep_num * 20h) + 04h*/
-  __IO uint32_t DOEPINT;       /* dev OUT Endpoint Itr Reg      B00h + (ep_num * 20h) + 08h*/
-  uint32_t Reserved0C;         /* Reserved                      B00h + (ep_num * 20h) + 0Ch*/
-  __IO uint32_t DOEPTSIZ;      /* dev OUT Endpoint Txfer Size   B00h + (ep_num * 20h) + 10h*/
-  __IO uint32_t DOEPDMA;       /* dev OUT Endpoint DMA Address  B00h + (ep_num * 20h) + 14h*/
-  uint32_t Reserved18[2];      /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
-}
-USB_OTG_OUTEndpointTypeDef;
-
-
-/** 
-  * @brief __Host_Mode_Register_Structures
-  */
-typedef struct 
-{
-  __IO uint32_t HCFG;             /* Host Configuration Register    400h*/
-  __IO uint32_t HFIR;      /* Host Frame Interval Register   404h*/
-  __IO uint32_t HFNUM;         /* Host Frame Nbr/Frame Remaining 408h*/
-  uint32_t Reserved40C;                   /* Reserved                       40Ch*/
-  __IO uint32_t HPTXSTS;   /* Host Periodic Tx FIFO/ Queue Status 410h*/
-  __IO uint32_t HAINT;   /* Host All Channels Interrupt Register 414h*/
-  __IO uint32_t HAINTMSK;   /* Host All Channels Interrupt Mask 418h*/
-}
-USB_OTG_HostTypeDef;
-
-
-/** 
-  * @brief __Host_Channel_Specific_Registers
-  */
-typedef struct
-{
-  __IO uint32_t HCCHAR;
-  __IO uint32_t HCSPLT;
-  __IO uint32_t HCINT;
-  __IO uint32_t HCINTMSK;
-  __IO uint32_t HCTSIZ;
-  __IO uint32_t HCDMA;
-  uint32_t Reserved[2];
-}
-USB_OTG_HostChannelTypeDef;
-
-    
-/** 
-  * @brief Peripheral_memory_map
-  */
-#define FLASH_BASE            0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region                         */
-#define CCMDATARAM_BASE       0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
-#define SRAM1_BASE            0x20000000U /*!< SRAM1(112 KB) base address in the alias region                             */
-#define SRAM2_BASE            0x2001C000U /*!< SRAM2(16 KB) base address in the alias region                              */
-#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region                                */
-#define BKPSRAM_BASE          0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region                         */
-#define FSMC_R_BASE           0xA0000000U /*!< FSMC registers base address                                                */
-#define SRAM1_BB_BASE         0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region                             */
-#define SRAM2_BB_BASE         0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region                              */
-#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region                                */
-#define BKPSRAM_BB_BASE       0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region                         */
-#define FLASH_END             0x080FFFFFU /*!< FLASH end address */
-#define CCMDATARAM_END        0x1000FFFFU /*!< CCM data RAM end address */
-
-/* Legacy defines */
-#define SRAM_BASE             SRAM1_BASE
-#define SRAM_BB_BASE          SRAM1_BB_BASE
-
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000U)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)
-#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800U)
-#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00U)
-#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000U)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)
-#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400U)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)
-#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000U)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800U)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00U)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x5000U)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)
-#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)
-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)
-#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800U)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)
-
-/*!< APB2 peripherals */
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000U)
-#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400U)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x1000U)
-#define USART6_BASE           (APB2PERIPH_BASE + 0x1400U)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000U)
-#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100U)
-#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200U)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x2300U)
-#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00U)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800U)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00U)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000U)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400U)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800U)
-
-/*!< AHB1 peripherals */
-#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000U)
-#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400U)
-#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800U)
-#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00U)
-#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000U)
-#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400U)
-#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800U)
-#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00U)
-#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000U)
-#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)
-#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800U)
-#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00U)
-#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000U)
-#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010U)
-#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028U)
-#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040U)
-#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058U)
-#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070U)
-#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088U)
-#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0U)
-#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8U)
-#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400U)
-#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010U)
-#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028U)
-#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040U)
-#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058U)
-#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070U)
-#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088U)
-#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0U)
-#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)
-#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000U)
-#define ETH_MAC_BASE          (ETH_BASE)
-#define ETH_MMC_BASE          (ETH_BASE + 0x0100U)
-#define ETH_PTP_BASE          (ETH_BASE + 0x0700U)
-#define ETH_DMA_BASE          (ETH_BASE + 0x1000U)
-
-/*!< AHB2 peripherals */
-#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000U)
-#define CRYP_BASE             (AHB2PERIPH_BASE + 0x60000U)
-#define HASH_BASE             (AHB2PERIPH_BASE + 0x60400U)
-#define HASH_DIGEST_BASE      (AHB2PERIPH_BASE + 0x60710U)
-#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800U)
-
-/*!< FSMC Bankx registers base address */
-#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000U)
-#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104U)
-#define FSMC_Bank2_3_R_BASE   (FSMC_R_BASE + 0x0060U)
-#define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0U)
-
-/* Debug MCU registers base address */
-#define DBGMCU_BASE           0xE0042000U
-
-/*!< USB registers base address */
-#define USB_OTG_HS_PERIPH_BASE               0x40040000U
-#define USB_OTG_FS_PERIPH_BASE               0x50000000U
-
-#define USB_OTG_GLOBAL_BASE                  0x000U
-#define USB_OTG_DEVICE_BASE                  0x800U
-#define USB_OTG_IN_ENDPOINT_BASE             0x900U
-#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U
-#define USB_OTG_EP_REG_SIZE                  0x20U
-#define USB_OTG_HOST_BASE                    0x400U
-#define USB_OTG_HOST_PORT_BASE               0x440U
-#define USB_OTG_HOST_CHANNEL_BASE            0x500U
-#define USB_OTG_HOST_CHANNEL_SIZE            0x20U
-#define USB_OTG_PCGCCTL_BASE                 0xE00U
-#define USB_OTG_FIFO_BASE                    0x1000U
-#define USB_OTG_FIFO_SIZE                    0x1000U
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
-#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
-#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define UART4               ((USART_TypeDef *) UART4_BASE)
-#define UART5               ((USART_TypeDef *) UART5_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
-#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
-#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
-#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define USART6              ((USART_TypeDef *) USART6_BASE)
-#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
-#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
-#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE) 
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
-#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
-#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
-#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
-#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
-#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
-#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
-#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
-#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
-#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
-#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
-#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
-#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
-#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
-#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
-#define ETH                 ((ETH_TypeDef *) ETH_BASE)  
-#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
-#define CRYP                ((CRYP_TypeDef *) CRYP_BASE)
-#define HASH                ((HASH_TypeDef *) HASH_BASE)
-#define HASH_DIGEST         ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
-#define RNG                 ((RNG_TypeDef *) RNG_BASE)
-#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
-#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
-#define FSMC_Bank2_3        ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)
-#define FSMC_Bank4          ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
-
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
-#define USB_OTG_HS          ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers_Bits_Definition               */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Analog to Digital Converter                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          0x00000001U       /*!<Analog watchdog flag */
-#define  ADC_SR_EOC                          0x00000002U       /*!<End of conversion */
-#define  ADC_SR_JEOC                         0x00000004U       /*!<Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        0x00000008U       /*!<Injected channel Start flag */
-#define  ADC_SR_STRT                         0x00000010U       /*!<Regular channel Start flag */
-#define  ADC_SR_OVR                          0x00000020U       /*!<Overrun flag */
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
-#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels */
-#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels */
-#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution) */
-#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
-  
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion */
-#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode */
-#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC) */
-#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection */
-#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment */
-#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      0xFFFFU            /*!<Injected data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag */
-#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion */
-#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag */
-#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag */
-#define  ADC_CSR_OVR1                        0x00000020U        /*!<ADC1 DMA overrun  flag */
-#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag */
-#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion */
-#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag */
-#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag */
-#define  ADC_CSR_OVR2                        0x00002000U        /*!<ADC2 DMA overrun  flag */
-#define  ADC_CSR_AWD3                        0x00010000U        /*!<ADC3 Analog watchdog flag */
-#define  ADC_CSR_EOC3                        0x00020000U        /*!<ADC3 End of conversion */
-#define  ADC_CSR_JEOC3                       0x00040000U        /*!<ADC3 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT3                      0x00080000U        /*!<ADC3 Injected channel Start flag */
-#define  ADC_CSR_STRT3                       0x00100000U        /*!<ADC3 Regular channel Start flag */
-#define  ADC_CSR_OVR3                        0x00200000U        /*!<ADC3 DMA overrun  flag */
-
-/* Legacy defines */
-#define  ADC_CSR_DOVR1                        ADC_CSR_OVR1
-#define  ADC_CSR_DOVR2                        ADC_CSR_OVR2
-#define  ADC_CSR_DOVR3                        ADC_CSR_OVR3
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
-#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
-#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
-#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
-#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
-
-/*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                      0x0000FFFFU         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                      0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Controller Area Network                            */
-/*                                                                            */
-/******************************************************************************/
-/*!<CAN control and status registers */
-/*******************  Bit definition for CAN_MCR register  ********************/
-#define  CAN_MCR_INRQ                        0x00000001U        /*!<Initialization Request */
-#define  CAN_MCR_SLEEP                       0x00000002U        /*!<Sleep Mode Request */
-#define  CAN_MCR_TXFP                        0x00000004U        /*!<Transmit FIFO Priority */
-#define  CAN_MCR_RFLM                        0x00000008U        /*!<Receive FIFO Locked Mode */
-#define  CAN_MCR_NART                        0x00000010U        /*!<No Automatic Retransmission */
-#define  CAN_MCR_AWUM                        0x00000020U        /*!<Automatic Wakeup Mode */
-#define  CAN_MCR_ABOM                        0x00000040U        /*!<Automatic Bus-Off Management */
-#define  CAN_MCR_TTCM                        0x00000080U        /*!<Time Triggered Communication Mode */
-#define  CAN_MCR_RESET                       0x00008000U        /*!<bxCAN software master reset */
-#define  CAN_MCR_DBF                         0x00010000U        /*!<bxCAN Debug freeze */
-/*******************  Bit definition for CAN_MSR register  ********************/
-#define  CAN_MSR_INAK                        0x0001U            /*!<Initialization Acknowledge */
-#define  CAN_MSR_SLAK                        0x0002U            /*!<Sleep Acknowledge */
-#define  CAN_MSR_ERRI                        0x0004U            /*!<Error Interrupt */
-#define  CAN_MSR_WKUI                        0x0008U            /*!<Wakeup Interrupt */
-#define  CAN_MSR_SLAKI                       0x0010U            /*!<Sleep Acknowledge Interrupt */
-#define  CAN_MSR_TXM                         0x0100U            /*!<Transmit Mode */
-#define  CAN_MSR_RXM                         0x0200U            /*!<Receive Mode */
-#define  CAN_MSR_SAMP                        0x0400U            /*!<Last Sample Point */
-#define  CAN_MSR_RX                          0x0800U            /*!<CAN Rx Signal */
-
-/*******************  Bit definition for CAN_TSR register  ********************/
-#define  CAN_TSR_RQCP0                       0x00000001U        /*!<Request Completed Mailbox0 */
-#define  CAN_TSR_TXOK0                       0x00000002U        /*!<Transmission OK of Mailbox0 */
-#define  CAN_TSR_ALST0                       0x00000004U        /*!<Arbitration Lost for Mailbox0 */
-#define  CAN_TSR_TERR0                       0x00000008U        /*!<Transmission Error of Mailbox0 */
-#define  CAN_TSR_ABRQ0                       0x00000080U        /*!<Abort Request for Mailbox0 */
-#define  CAN_TSR_RQCP1                       0x00000100U        /*!<Request Completed Mailbox1 */
-#define  CAN_TSR_TXOK1                       0x00000200U        /*!<Transmission OK of Mailbox1 */
-#define  CAN_TSR_ALST1                       0x00000400U        /*!<Arbitration Lost for Mailbox1 */
-#define  CAN_TSR_TERR1                       0x00000800U        /*!<Transmission Error of Mailbox1 */
-#define  CAN_TSR_ABRQ1                       0x00008000U        /*!<Abort Request for Mailbox 1 */
-#define  CAN_TSR_RQCP2                       0x00010000U        /*!<Request Completed Mailbox2 */
-#define  CAN_TSR_TXOK2                       0x00020000U        /*!<Transmission OK of Mailbox 2 */
-#define  CAN_TSR_ALST2                       0x00040000U        /*!<Arbitration Lost for mailbox 2 */
-#define  CAN_TSR_TERR2                       0x00080000U        /*!<Transmission Error of Mailbox 2 */
-#define  CAN_TSR_ABRQ2                       0x00800000U        /*!<Abort Request for Mailbox 2 */
-#define  CAN_TSR_CODE                        0x03000000U        /*!<Mailbox Code */
-
-#define  CAN_TSR_TME                         0x1C000000U        /*!<TME[2:0] bits */
-#define  CAN_TSR_TME0                        0x04000000U        /*!<Transmit Mailbox 0 Empty */
-#define  CAN_TSR_TME1                        0x08000000U        /*!<Transmit Mailbox 1 Empty */
-#define  CAN_TSR_TME2                        0x10000000U        /*!<Transmit Mailbox 2 Empty */
-
-#define  CAN_TSR_LOW                         0xE0000000U        /*!<LOW[2:0] bits */
-#define  CAN_TSR_LOW0                        0x20000000U        /*!<Lowest Priority Flag for Mailbox 0 */
-#define  CAN_TSR_LOW1                        0x40000000U        /*!<Lowest Priority Flag for Mailbox 1 */
-#define  CAN_TSR_LOW2                        0x80000000U        /*!<Lowest Priority Flag for Mailbox 2 */
-
-/*******************  Bit definition for CAN_RF0R register  *******************/
-#define  CAN_RF0R_FMP0                       0x03U               /*!<FIFO 0 Message Pending */
-#define  CAN_RF0R_FULL0                      0x08U               /*!<FIFO 0 Full */
-#define  CAN_RF0R_FOVR0                      0x10U               /*!<FIFO 0 Overrun */
-#define  CAN_RF0R_RFOM0                      0x20U               /*!<Release FIFO 0 Output Mailbox */
-
-/*******************  Bit definition for CAN_RF1R register  *******************/
-#define  CAN_RF1R_FMP1                       0x03U               /*!<FIFO 1 Message Pending */
-#define  CAN_RF1R_FULL1                      0x08U               /*!<FIFO 1 Full */
-#define  CAN_RF1R_FOVR1                      0x10U               /*!<FIFO 1 Overrun */
-#define  CAN_RF1R_RFOM1                      0x20U               /*!<Release FIFO 1 Output Mailbox */
-
-/********************  Bit definition for CAN_IER register  *******************/
-#define  CAN_IER_TMEIE                       0x00000001U        /*!<Transmit Mailbox Empty Interrupt Enable */
-#define  CAN_IER_FMPIE0                      0x00000002U        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE0                       0x00000004U        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE0                      0x00000008U        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_FMPIE1                      0x00000010U        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE1                       0x00000020U        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE1                      0x00000040U        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error Warning Interrupt Enable */
-#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error Passive Interrupt Enable */
-#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-Off Interrupt Enable */
-#define  CAN_IER_LECIE                       0x00000800U        /*!<Last Error Code Interrupt Enable */
-#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error Interrupt Enable */
-#define  CAN_IER_WKUIE                       0x00010000U        /*!<Wakeup Interrupt Enable */
-#define  CAN_IER_SLKIE                       0x00020000U        /*!<Sleep Interrupt Enable */
-#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error warning interrupt enable */
-#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error passive interrupt enable */
-#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-off interrupt enable */
-#define  CAN_IER_LECIE                       0x00000800U        /*!<Last error code interrupt enable */
-#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error interrupt enable */
-
-
-/********************  Bit definition for CAN_ESR register  *******************/
-#define  CAN_ESR_EWGF                        0x00000001U        /*!<Error Warning Flag */
-#define  CAN_ESR_EPVF                        0x00000002U        /*!<Error Passive Flag */
-#define  CAN_ESR_BOFF                        0x00000004U        /*!<Bus-Off Flag */
-
-#define  CAN_ESR_LEC                         0x00000070U        /*!<LEC[2:0] bits (Last Error Code) */
-#define  CAN_ESR_LEC_0                       0x00000010U        /*!<Bit 0 */
-#define  CAN_ESR_LEC_1                       0x00000020U        /*!<Bit 1 */
-#define  CAN_ESR_LEC_2                       0x00000040U        /*!<Bit 2 */
-
-#define  CAN_ESR_TEC                         0x00FF0000U        /*!<Least significant byte of the 9-bit Transmit Error Counter */
-#define  CAN_ESR_REC                         0xFF000000U        /*!<Receive Error Counter */
-
-/*******************  Bit definition for CAN_BTR register  ********************/
-#define  CAN_BTR_BRP                         0x000003FFU        /*!<Baud Rate Prescaler */
-#define  CAN_BTR_TS1                         0x000F0000U        /*!<Time Segment 1 */
-#define  CAN_BTR_TS1_0                       0x00010000U        /*!<Bit 0 */
-#define  CAN_BTR_TS1_1                       0x00020000U        /*!<Bit 1 */
-#define  CAN_BTR_TS1_2                       0x00040000U        /*!<Bit 2 */
-#define  CAN_BTR_TS1_3                       0x00080000U        /*!<Bit 3 */
-#define  CAN_BTR_TS2                         0x00700000U        /*!<Time Segment 2 */
-#define  CAN_BTR_TS2_0                       0x00100000U        /*!<Bit 0 */
-#define  CAN_BTR_TS2_1                       0x00200000U        /*!<Bit 1 */
-#define  CAN_BTR_TS2_2                       0x00400000U        /*!<Bit 2 */
-#define  CAN_BTR_SJW                         0x03000000U        /*!<Resynchronization Jump Width */
-#define  CAN_BTR_SJW_0                       0x01000000U        /*!<Bit 0 */
-#define  CAN_BTR_SJW_1                       0x02000000U        /*!<Bit 1 */
-#define  CAN_BTR_LBKM                        0x40000000U        /*!<Loop Back Mode (Debug) */
-#define  CAN_BTR_SILM                        0x80000000U        /*!<Silent Mode */
-
-
-/*!<Mailbox registers */
-/******************  Bit definition for CAN_TI0R register  ********************/
-#define  CAN_TI0R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI0R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_TI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/******************  Bit definition for CAN_TDT0R register  *******************/
-#define  CAN_TDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT0R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/******************  Bit definition for CAN_TDL0R register  *******************/
-#define  CAN_TDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/******************  Bit definition for CAN_TDH0R register  *******************/
-#define  CAN_TDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI1R register  *******************/
-#define  CAN_TI1R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI1R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI1R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_TI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT1R register  ******************/
-#define  CAN_TDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT1R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL1R register  ******************/
-#define  CAN_TDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH1R register  ******************/
-#define  CAN_TDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI2R register  *******************/
-#define  CAN_TI2R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI2R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI2R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI2R_EXID                       0x001FFFF8U        /*!<Extended identifier */
-#define  CAN_TI2R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT2R register  ******************/  
-#define  CAN_TDT2R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT2R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT2R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL2R register  ******************/
-#define  CAN_TDL2R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL2R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL2R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL2R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH2R register  ******************/
-#define  CAN_TDH2R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH2R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH2R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH2R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI0R register  *******************/
-#define  CAN_RI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_RI0R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_RI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_RI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT0R register  ******************/
-#define  CAN_RDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_RDT0R_FMI                       0x0000FF00U        /*!<Filter Match Index */
-#define  CAN_RDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL0R register  ******************/
-#define  CAN_RDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_RDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_RDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_RDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH0R register  ******************/
-#define  CAN_RDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_RDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_RDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_RDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI1R register  *******************/
-#define  CAN_RI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_RI1R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_RI1R_EXID                       0x001FFFF8U        /*!<Extended identifier */
-#define  CAN_RI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT1R register  ******************/
-#define  CAN_RDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_RDT1R_FMI                       0x0000FF00U        /*!<Filter Match Index */
-#define  CAN_RDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL1R register  ******************/
-#define  CAN_RDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_RDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_RDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_RDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH1R register  ******************/
-#define  CAN_RDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_RDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_RDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_RDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*!<CAN filter registers */
-/*******************  Bit definition for CAN_FMR register  ********************/
-#define  CAN_FMR_FINIT                       0x01U               /*!<Filter Init Mode */
-#define  CAN_FMR_CAN2SB                      0x00003F00U        /*!<CAN2 start bank */
-
-/*******************  Bit definition for CAN_FM1R register  *******************/
-#define  CAN_FM1R_FBM                        0x0FFFFFFFU        /*!<Filter Mode */
-#define  CAN_FM1R_FBM0                       0x00000001U        /*!<Filter Init Mode bit 0 */
-#define  CAN_FM1R_FBM1                       0x00000002U        /*!<Filter Init Mode bit 1 */
-#define  CAN_FM1R_FBM2                       0x00000004U        /*!<Filter Init Mode bit 2 */
-#define  CAN_FM1R_FBM3                       0x00000008U        /*!<Filter Init Mode bit 3 */
-#define  CAN_FM1R_FBM4                       0x00000010U        /*!<Filter Init Mode bit 4 */
-#define  CAN_FM1R_FBM5                       0x00000020U        /*!<Filter Init Mode bit 5 */
-#define  CAN_FM1R_FBM6                       0x00000040U        /*!<Filter Init Mode bit 6 */
-#define  CAN_FM1R_FBM7                       0x00000080U        /*!<Filter Init Mode bit 7 */
-#define  CAN_FM1R_FBM8                       0x00000100U        /*!<Filter Init Mode bit 8 */
-#define  CAN_FM1R_FBM9                       0x00000200U        /*!<Filter Init Mode bit 9 */
-#define  CAN_FM1R_FBM10                      0x00000400U        /*!<Filter Init Mode bit 10 */
-#define  CAN_FM1R_FBM11                      0x00000800U        /*!<Filter Init Mode bit 11 */
-#define  CAN_FM1R_FBM12                      0x00001000U        /*!<Filter Init Mode bit 12 */
-#define  CAN_FM1R_FBM13                      0x00002000U        /*!<Filter Init Mode bit 13 */
-#define  CAN_FM1R_FBM14                      0x00004000U        /*!<Filter Init Mode bit 14 */
-#define  CAN_FM1R_FBM15                      0x00008000U        /*!<Filter Init Mode bit 15 */
-#define  CAN_FM1R_FBM16                      0x00010000U        /*!<Filter Init Mode bit 16 */
-#define  CAN_FM1R_FBM17                      0x00020000U        /*!<Filter Init Mode bit 17 */
-#define  CAN_FM1R_FBM18                      0x00040000U        /*!<Filter Init Mode bit 18 */
-#define  CAN_FM1R_FBM19                      0x00080000U        /*!<Filter Init Mode bit 19 */
-#define  CAN_FM1R_FBM20                      0x00100000U        /*!<Filter Init Mode bit 20 */
-#define  CAN_FM1R_FBM21                      0x00200000U        /*!<Filter Init Mode bit 21 */
-#define  CAN_FM1R_FBM22                      0x00400000U        /*!<Filter Init Mode bit 22 */
-#define  CAN_FM1R_FBM23                      0x00800000U        /*!<Filter Init Mode bit 23 */
-#define  CAN_FM1R_FBM24                      0x01000000U        /*!<Filter Init Mode bit 24 */
-#define  CAN_FM1R_FBM25                      0x02000000U        /*!<Filter Init Mode bit 25 */
-#define  CAN_FM1R_FBM26                      0x04000000U        /*!<Filter Init Mode bit 26 */
-#define  CAN_FM1R_FBM27                      0x08000000U        /*!<Filter Init Mode bit 27 */
-
-/*******************  Bit definition for CAN_FS1R register  *******************/
-#define  CAN_FS1R_FSC                        0x0FFFFFFFU        /*!<Filter Scale Configuration */
-#define  CAN_FS1R_FSC0                       0x00000001U        /*!<Filter Scale Configuration bit 0 */
-#define  CAN_FS1R_FSC1                       0x00000002U        /*!<Filter Scale Configuration bit 1 */
-#define  CAN_FS1R_FSC2                       0x00000004U        /*!<Filter Scale Configuration bit 2 */
-#define  CAN_FS1R_FSC3                       0x00000008U        /*!<Filter Scale Configuration bit 3 */
-#define  CAN_FS1R_FSC4                       0x00000010U        /*!<Filter Scale Configuration bit 4 */
-#define  CAN_FS1R_FSC5                       0x00000020U        /*!<Filter Scale Configuration bit 5 */
-#define  CAN_FS1R_FSC6                       0x00000040U        /*!<Filter Scale Configuration bit 6 */
-#define  CAN_FS1R_FSC7                       0x00000080U        /*!<Filter Scale Configuration bit 7 */
-#define  CAN_FS1R_FSC8                       0x00000100U        /*!<Filter Scale Configuration bit 8 */
-#define  CAN_FS1R_FSC9                       0x00000200U        /*!<Filter Scale Configuration bit 9 */
-#define  CAN_FS1R_FSC10                      0x00000400U        /*!<Filter Scale Configuration bit 10 */
-#define  CAN_FS1R_FSC11                      0x00000800U        /*!<Filter Scale Configuration bit 11 */
-#define  CAN_FS1R_FSC12                      0x00001000U        /*!<Filter Scale Configuration bit 12 */
-#define  CAN_FS1R_FSC13                      0x00002000U        /*!<Filter Scale Configuration bit 13 */
-#define  CAN_FS1R_FSC14                      0x00004000U        /*!<Filter Scale Configuration bit 14 */
-#define  CAN_FS1R_FSC15                      0x00008000U        /*!<Filter Scale Configuration bit 15 */
-#define  CAN_FS1R_FSC16                      0x00010000U        /*!<Filter Scale Configuration bit 16 */
-#define  CAN_FS1R_FSC17                      0x00020000U        /*!<Filter Scale Configuration bit 17 */
-#define  CAN_FS1R_FSC18                      0x00040000U        /*!<Filter Scale Configuration bit 18 */
-#define  CAN_FS1R_FSC19                      0x00080000U        /*!<Filter Scale Configuration bit 19 */
-#define  CAN_FS1R_FSC20                      0x00100000U        /*!<Filter Scale Configuration bit 20 */
-#define  CAN_FS1R_FSC21                      0x00200000U        /*!<Filter Scale Configuration bit 21 */
-#define  CAN_FS1R_FSC22                      0x00400000U        /*!<Filter Scale Configuration bit 22 */
-#define  CAN_FS1R_FSC23                      0x00800000U        /*!<Filter Scale Configuration bit 23 */
-#define  CAN_FS1R_FSC24                      0x01000000U        /*!<Filter Scale Configuration bit 24 */
-#define  CAN_FS1R_FSC25                      0x02000000U        /*!<Filter Scale Configuration bit 25 */
-#define  CAN_FS1R_FSC26                      0x04000000U        /*!<Filter Scale Configuration bit 26 */
-#define  CAN_FS1R_FSC27                      0x08000000U        /*!<Filter Scale Configuration bit 27 */
-
-/******************  Bit definition for CAN_FFA1R register  *******************/
-#define  CAN_FFA1R_FFA                        0x0FFFFFFFU        /*!<Filter FIFO Assignment */
-#define  CAN_FFA1R_FFA0                       0x00000001U        /*!<Filter FIFO Assignment bit 0 */
-#define  CAN_FFA1R_FFA1                       0x00000002U        /*!<Filter FIFO Assignment bit 1 */
-#define  CAN_FFA1R_FFA2                       0x00000004U        /*!<Filter FIFO Assignment bit 2 */
-#define  CAN_FFA1R_FFA3                       0x00000008U        /*!<Filter FIFO Assignment bit 3 */
-#define  CAN_FFA1R_FFA4                       0x00000010U        /*!<Filter FIFO Assignment bit 4 */
-#define  CAN_FFA1R_FFA5                       0x00000020U        /*!<Filter FIFO Assignment bit 5 */
-#define  CAN_FFA1R_FFA6                       0x00000040U        /*!<Filter FIFO Assignment bit 6 */
-#define  CAN_FFA1R_FFA7                       0x00000080U        /*!<Filter FIFO Assignment bit 7 */
-#define  CAN_FFA1R_FFA8                       0x00000100U        /*!<Filter FIFO Assignment bit 8 */
-#define  CAN_FFA1R_FFA9                       0x00000200U        /*!<Filter FIFO Assignment bit 9 */
-#define  CAN_FFA1R_FFA10                      0x00000400U        /*!<Filter FIFO Assignment bit 10 */
-#define  CAN_FFA1R_FFA11                      0x00000800U        /*!<Filter FIFO Assignment bit 11 */
-#define  CAN_FFA1R_FFA12                      0x00001000U        /*!<Filter FIFO Assignment bit 12 */
-#define  CAN_FFA1R_FFA13                      0x00002000U        /*!<Filter FIFO Assignment bit 13 */
-#define  CAN_FFA1R_FFA14                      0x00004000U        /*!<Filter FIFO Assignment bit 14 */
-#define  CAN_FFA1R_FFA15                      0x00008000U        /*!<Filter FIFO Assignment bit 15 */
-#define  CAN_FFA1R_FFA16                      0x00010000U        /*!<Filter FIFO Assignment bit 16 */
-#define  CAN_FFA1R_FFA17                      0x00020000U        /*!<Filter FIFO Assignment bit 17 */
-#define  CAN_FFA1R_FFA18                      0x00040000U        /*!<Filter FIFO Assignment bit 18 */
-#define  CAN_FFA1R_FFA19                      0x00080000U        /*!<Filter FIFO Assignment bit 19 */
-#define  CAN_FFA1R_FFA20                      0x00100000U        /*!<Filter FIFO Assignment bit 20 */
-#define  CAN_FFA1R_FFA21                      0x00200000U        /*!<Filter FIFO Assignment bit 21 */
-#define  CAN_FFA1R_FFA22                      0x00400000U        /*!<Filter FIFO Assignment bit 22 */
-#define  CAN_FFA1R_FFA23                      0x00800000U        /*!<Filter FIFO Assignment bit 23 */
-#define  CAN_FFA1R_FFA24                      0x01000000U        /*!<Filter FIFO Assignment bit 24 */
-#define  CAN_FFA1R_FFA25                      0x02000000U        /*!<Filter FIFO Assignment bit 25 */
-#define  CAN_FFA1R_FFA26                      0x04000000U        /*!<Filter FIFO Assignment bit 26 */
-#define  CAN_FFA1R_FFA27                      0x08000000U        /*!<Filter FIFO Assignment bit 27 */
-
-/*******************  Bit definition for CAN_FA1R register  *******************/
-#define  CAN_FA1R_FACT                        0x0FFFFFFFU        /*!<Filter Active */
-#define  CAN_FA1R_FACT0                       0x00000001U        /*!<Filter Active bit 0 */
-#define  CAN_FA1R_FACT1                       0x00000002U        /*!<Filter Active bit 1 */
-#define  CAN_FA1R_FACT2                       0x00000004U        /*!<Filter Active bit 2 */
-#define  CAN_FA1R_FACT3                       0x00000008U        /*!<Filter Active bit 3 */
-#define  CAN_FA1R_FACT4                       0x00000010U        /*!<Filter Active bit 4 */
-#define  CAN_FA1R_FACT5                       0x00000020U        /*!<Filter Active bit 5 */
-#define  CAN_FA1R_FACT6                       0x00000040U        /*!<Filter Active bit 6 */
-#define  CAN_FA1R_FACT7                       0x00000080U        /*!<Filter Active bit 7 */
-#define  CAN_FA1R_FACT8                       0x00000100U        /*!<Filter Active bit 8 */
-#define  CAN_FA1R_FACT9                       0x00000200U        /*!<Filter Active bit 9 */
-#define  CAN_FA1R_FACT10                      0x00000400U        /*!<Filter Active bit 10 */
-#define  CAN_FA1R_FACT11                      0x00000800U        /*!<Filter Active bit 11 */
-#define  CAN_FA1R_FACT12                      0x00001000U        /*!<Filter Active bit 12 */
-#define  CAN_FA1R_FACT13                      0x00002000U        /*!<Filter Active bit 13 */
-#define  CAN_FA1R_FACT14                      0x00004000U        /*!<Filter Active bit 14 */
-#define  CAN_FA1R_FACT15                      0x00008000U        /*!<Filter Active bit 15 */
-#define  CAN_FA1R_FACT16                      0x00010000U        /*!<Filter Active bit 16 */
-#define  CAN_FA1R_FACT17                      0x00020000U        /*!<Filter Active bit 17 */
-#define  CAN_FA1R_FACT18                      0x00040000U        /*!<Filter Active bit 18 */
-#define  CAN_FA1R_FACT19                      0x00080000U        /*!<Filter Active bit 19 */
-#define  CAN_FA1R_FACT20                      0x00100000U        /*!<Filter Active bit 20 */
-#define  CAN_FA1R_FACT21                      0x00200000U        /*!<Filter Active bit 21 */
-#define  CAN_FA1R_FACT22                      0x00400000U        /*!<Filter Active bit 22 */
-#define  CAN_FA1R_FACT23                      0x00800000U        /*!<Filter Active bit 23 */
-#define  CAN_FA1R_FACT24                      0x01000000U        /*!<Filter Active bit 24 */
-#define  CAN_FA1R_FACT25                      0x02000000U        /*!<Filter Active bit 25 */
-#define  CAN_FA1R_FACT26                      0x04000000U        /*!<Filter Active bit 26 */
-#define  CAN_FA1R_FACT27                      0x08000000U        /*!<Filter Active bit 27 */
-
-/*******************  Bit definition for CAN_F0R1 register  *******************/
-#define  CAN_F0R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F0R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F0R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F0R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F0R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F0R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F0R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F0R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F0R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F0R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F0R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F0R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F0R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F0R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F0R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F0R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F0R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F0R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F0R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F0R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F0R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F0R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F0R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F0R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F0R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F0R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F0R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F0R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F0R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F0R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F0R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F0R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R1 register  *******************/
-#define  CAN_F1R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F1R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F1R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F1R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F1R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F1R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F1R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F1R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F1R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F1R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F1R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F1R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F1R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F1R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F1R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F1R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F1R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F1R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F1R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F1R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F1R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F1R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F1R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F1R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F1R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F1R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F1R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F1R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F1R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F1R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F1R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F1R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R1 register  *******************/
-#define  CAN_F2R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F2R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F2R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F2R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F2R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F2R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F2R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F2R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F2R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F2R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F2R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F2R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F2R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F2R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F2R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F2R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F2R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F2R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F2R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F2R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F2R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F2R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F2R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F2R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F2R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F2R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F2R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F2R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F2R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F2R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F2R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F2R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R1 register  *******************/
-#define  CAN_F3R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F3R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F3R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F3R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F3R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F3R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F3R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F3R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F3R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F3R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F3R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F3R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F3R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F3R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F3R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F3R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F3R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F3R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F3R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F3R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F3R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F3R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F3R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F3R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F3R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F3R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F3R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F3R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F3R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F3R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F3R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F3R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R1 register  *******************/
-#define  CAN_F4R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F4R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F4R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F4R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F4R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F4R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F4R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F4R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F4R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F4R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F4R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F4R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F4R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F4R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F4R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F4R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F4R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F4R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F4R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F4R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F4R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F4R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F4R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F4R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F4R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F4R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F4R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F4R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F4R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F4R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F4R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F4R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R1 register  *******************/
-#define  CAN_F5R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F5R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F5R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F5R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F5R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F5R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F5R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F5R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F5R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F5R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F5R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F5R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F5R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F5R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F5R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F5R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F5R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F5R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F5R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F5R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F5R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F5R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F5R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F5R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F5R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F5R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F5R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F5R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F5R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F5R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F5R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F5R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R1 register  *******************/
-#define  CAN_F6R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F6R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F6R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F6R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F6R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F6R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F6R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F6R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F6R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F6R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F6R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F6R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F6R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F6R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F6R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F6R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F6R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F6R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F6R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F6R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F6R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F6R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F6R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F6R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F6R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F6R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F6R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F6R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F6R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F6R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F6R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F6R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R1 register  *******************/
-#define  CAN_F7R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F7R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F7R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F7R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F7R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F7R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F7R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F7R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F7R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F7R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F7R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F7R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F7R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F7R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F7R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F7R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F7R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F7R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F7R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F7R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F7R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F7R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F7R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F7R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F7R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F7R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F7R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F7R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F7R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F7R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F7R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F7R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R1 register  *******************/
-#define  CAN_F8R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F8R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F8R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F8R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F8R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F8R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F8R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F8R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F8R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F8R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F8R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F8R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F8R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F8R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F8R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F8R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F8R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F8R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F8R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F8R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F8R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F8R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F8R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F8R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F8R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F8R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F8R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F8R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F8R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F8R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F8R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F8R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R1 register  *******************/
-#define  CAN_F9R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F9R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F9R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F9R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F9R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F9R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F9R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F9R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F9R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F9R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F9R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F9R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F9R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F9R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F9R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F9R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F9R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F9R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F9R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F9R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F9R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F9R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F9R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F9R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F9R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F9R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F9R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F9R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F9R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F9R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F9R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F9R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R1 register  ******************/
-#define  CAN_F10R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F10R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F10R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F10R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F10R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F10R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F10R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F10R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F10R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F10R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F10R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F10R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F10R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F10R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F10R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F10R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F10R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F10R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F10R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F10R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F10R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F10R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F10R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F10R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F10R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F10R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F10R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F10R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F10R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F10R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F10R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F10R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R1 register  ******************/
-#define  CAN_F11R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F11R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F11R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F11R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F11R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F11R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F11R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F11R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F11R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F11R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F11R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F11R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F11R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F11R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F11R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F11R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F11R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F11R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F11R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F11R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F11R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F11R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F11R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F11R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F11R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F11R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F11R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F11R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F11R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F11R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F11R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F11R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R1 register  ******************/
-#define  CAN_F12R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F12R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F12R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F12R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F12R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F12R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F12R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F12R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F12R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F12R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F12R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F12R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F12R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F12R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F12R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F12R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F12R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F12R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F12R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F12R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F12R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F12R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F12R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F12R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F12R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F12R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F12R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F12R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F12R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F12R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F12R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F12R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R1 register  ******************/
-#define  CAN_F13R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F13R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F13R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F13R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F13R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F13R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F13R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F13R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F13R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F13R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F13R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F13R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F13R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F13R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F13R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F13R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F13R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F13R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F13R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F13R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F13R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F13R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F13R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F13R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F13R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F13R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F13R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F13R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F13R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F13R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F13R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F13R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F0R2 register  *******************/
-#define  CAN_F0R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F0R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F0R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F0R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F0R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F0R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F0R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F0R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F0R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F0R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F0R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F0R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F0R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F0R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F0R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F0R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F0R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F0R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F0R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F0R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F0R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F0R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F0R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F0R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F0R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F0R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F0R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F0R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F0R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F0R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F0R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F0R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R2 register  *******************/
-#define  CAN_F1R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F1R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F1R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F1R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F1R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F1R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F1R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F1R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F1R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F1R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F1R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F1R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F1R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F1R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F1R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F1R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F1R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F1R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F1R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F1R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F1R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F1R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F1R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F1R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F1R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F1R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F1R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F1R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F1R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F1R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F1R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F1R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R2 register  *******************/
-#define  CAN_F2R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F2R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F2R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F2R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F2R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F2R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F2R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F2R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F2R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F2R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F2R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F2R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F2R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F2R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F2R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F2R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F2R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F2R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F2R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F2R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F2R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F2R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F2R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F2R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F2R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F2R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F2R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F2R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F2R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F2R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F2R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F2R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R2 register  *******************/
-#define  CAN_F3R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F3R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F3R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F3R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F3R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F3R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F3R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F3R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F3R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F3R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F3R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F3R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F3R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F3R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F3R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F3R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F3R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F3R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F3R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F3R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F3R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F3R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F3R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F3R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F3R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F3R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F3R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F3R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F3R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F3R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F3R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F3R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R2 register  *******************/
-#define  CAN_F4R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F4R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F4R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F4R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F4R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F4R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F4R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F4R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F4R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F4R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F4R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F4R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F4R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F4R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F4R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F4R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F4R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F4R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F4R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F4R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F4R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F4R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F4R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F4R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F4R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F4R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F4R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F4R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F4R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F4R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F4R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F4R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R2 register  *******************/
-#define  CAN_F5R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F5R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F5R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F5R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F5R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F5R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F5R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F5R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F5R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F5R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F5R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F5R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F5R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F5R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F5R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F5R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F5R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F5R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F5R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F5R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F5R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F5R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F5R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F5R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F5R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F5R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F5R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F5R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F5R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F5R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F5R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F5R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R2 register  *******************/
-#define  CAN_F6R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F6R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F6R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F6R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F6R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F6R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F6R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F6R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F6R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F6R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F6R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F6R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F6R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F6R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F6R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F6R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F6R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F6R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F6R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F6R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F6R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F6R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F6R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F6R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F6R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F6R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F6R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F6R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F6R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F6R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F6R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F6R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R2 register  *******************/
-#define  CAN_F7R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F7R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F7R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F7R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F7R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F7R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F7R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F7R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F7R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F7R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F7R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F7R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F7R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F7R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F7R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F7R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F7R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F7R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F7R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F7R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F7R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F7R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F7R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F7R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F7R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F7R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F7R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F7R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F7R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F7R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F7R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F7R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R2 register  *******************/
-#define  CAN_F8R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F8R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F8R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F8R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F8R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F8R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F8R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F8R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F8R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F8R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F8R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F8R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F8R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F8R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F8R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F8R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F8R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F8R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F8R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F8R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F8R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F8R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F8R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F8R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F8R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F8R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F8R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F8R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F8R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F8R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F8R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F8R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R2 register  *******************/
-#define  CAN_F9R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F9R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F9R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F9R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F9R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F9R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F9R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F9R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F9R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F9R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F9R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F9R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F9R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F9R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F9R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F9R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F9R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F9R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F9R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F9R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F9R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F9R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F9R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F9R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F9R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F9R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F9R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F9R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F9R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F9R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F9R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F9R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R2 register  ******************/
-#define  CAN_F10R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F10R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F10R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F10R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F10R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F10R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F10R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F10R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F10R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F10R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F10R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F10R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F10R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F10R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F10R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F10R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F10R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F10R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F10R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F10R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F10R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F10R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F10R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F10R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F10R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F10R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F10R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F10R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F10R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F10R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F10R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F10R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R2 register  ******************/
-#define  CAN_F11R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F11R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F11R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F11R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F11R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F11R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F11R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F11R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F11R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F11R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F11R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F11R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F11R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F11R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F11R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F11R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F11R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F11R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F11R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F11R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F11R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F11R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F11R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F11R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F11R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F11R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F11R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F11R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F11R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F11R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F11R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F11R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R2 register  ******************/
-#define  CAN_F12R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F12R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F12R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F12R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F12R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F12R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F12R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F12R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F12R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F12R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F12R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F12R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F12R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F12R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F12R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F12R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F12R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F12R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F12R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F12R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F12R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F12R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F12R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F12R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F12R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F12R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F12R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F12R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F12R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F12R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F12R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F12R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R2 register  ******************/
-#define  CAN_F13R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F13R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F13R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F13R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F13R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F13R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F13R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F13R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F13R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F13R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F13R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F13R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F13R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F13R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F13R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F13R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F13R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F13R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F13R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F13R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F13R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F13R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F13R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F13R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F13R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F13R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F13R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F13R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F13R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F13R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F13R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F13R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRC calculation unit                              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           0xFFFFFFFFU /*!< Data register bits */
-
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         0xFFU        /*!< General-purpose 8-bit data register bits */
-
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        0x01U        /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Crypto Processor                                */
-/*                                                                            */
-/******************************************************************************/
-/******************* Bits definition for CRYP_CR register  ********************/
-#define CRYP_CR_ALGODIR                      0x00000004U
-
-#define CRYP_CR_ALGOMODE                     0x00080038U
-#define CRYP_CR_ALGOMODE_0                   0x00000008U
-#define CRYP_CR_ALGOMODE_1                   0x00000010U
-#define CRYP_CR_ALGOMODE_2                   0x00000020U
-#define CRYP_CR_ALGOMODE_TDES_ECB            0x00000000U
-#define CRYP_CR_ALGOMODE_TDES_CBC            0x00000008U
-#define CRYP_CR_ALGOMODE_DES_ECB             0x00000010U
-#define CRYP_CR_ALGOMODE_DES_CBC             0x00000018U
-#define CRYP_CR_ALGOMODE_AES_ECB             0x00000020U
-#define CRYP_CR_ALGOMODE_AES_CBC             0x00000028U
-#define CRYP_CR_ALGOMODE_AES_CTR             0x00000030U
-#define CRYP_CR_ALGOMODE_AES_KEY             0x00000038U
-
-#define CRYP_CR_DATATYPE                     0x000000C0U
-#define CRYP_CR_DATATYPE_0                   0x00000040U
-#define CRYP_CR_DATATYPE_1                   0x00000080U
-#define CRYP_CR_KEYSIZE                      0x00000300U
-#define CRYP_CR_KEYSIZE_0                    0x00000100U
-#define CRYP_CR_KEYSIZE_1                    0x00000200U
-#define CRYP_CR_FFLUSH                       0x00004000U
-#define CRYP_CR_CRYPEN                       0x00008000U
-
-#define CRYP_CR_GCM_CCMPH                    0x00030000U
-#define CRYP_CR_GCM_CCMPH_0                  0x00010000U
-#define CRYP_CR_GCM_CCMPH_1                  0x00020000U
-#define CRYP_CR_ALGOMODE_3                   0x00080000U 
-
-/****************** Bits definition for CRYP_SR register  *********************/
-#define CRYP_SR_IFEM                         0x00000001U
-#define CRYP_SR_IFNF                         0x00000002U
-#define CRYP_SR_OFNE                         0x00000004U
-#define CRYP_SR_OFFU                         0x00000008U
-#define CRYP_SR_BUSY                         0x00000010U
-/****************** Bits definition for CRYP_DMACR register  ******************/
-#define CRYP_DMACR_DIEN                      0x00000001U
-#define CRYP_DMACR_DOEN                      0x00000002U
-/*****************  Bits definition for CRYP_IMSCR register  ******************/
-#define CRYP_IMSCR_INIM                      0x00000001U
-#define CRYP_IMSCR_OUTIM                     0x00000002U
-/****************** Bits definition for CRYP_RISR register  *******************/
-#define CRYP_RISR_OUTRIS                     0x00000001U
-#define CRYP_RISR_INRIS                      0x00000002U
-/****************** Bits definition for CRYP_MISR register  *******************/
-#define CRYP_MISR_INMIS                      0x00000001U
-#define CRYP_MISR_OUTMIS                     0x00000002U
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Digital to Analog Converter                           */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DAC_CR register  ********************/
-#define  DAC_CR_EN1                          0x00000001U        /*!<DAC channel1 enable */
-#define  DAC_CR_BOFF1                        0x00000002U        /*!<DAC channel1 output buffer disable */
-#define  DAC_CR_TEN1                         0x00000004U        /*!<DAC channel1 Trigger enable */
-
-#define  DAC_CR_TSEL1                        0x00000038U        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define  DAC_CR_TSEL1_0                      0x00000008U        /*!<Bit 0 */
-#define  DAC_CR_TSEL1_1                      0x00000010U        /*!<Bit 1 */
-#define  DAC_CR_TSEL1_2                      0x00000020U        /*!<Bit 2 */
-
-#define  DAC_CR_WAVE1                        0x000000C0U        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE1_0                      0x00000040U        /*!<Bit 0 */
-#define  DAC_CR_WAVE1_1                      0x00000080U        /*!<Bit 1 */
-
-#define  DAC_CR_MAMP1                        0x00000F00U        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP1_0                      0x00000100U        /*!<Bit 0 */
-#define  DAC_CR_MAMP1_1                      0x00000200U        /*!<Bit 1 */
-#define  DAC_CR_MAMP1_2                      0x00000400U        /*!<Bit 2 */
-#define  DAC_CR_MAMP1_3                      0x00000800U        /*!<Bit 3 */
-
-#define  DAC_CR_DMAEN1                       0x00001000U        /*!<DAC channel1 DMA enable */
-#define  DAC_CR_DMAUDRIE1                    0x00002000U        /*!<DAC channel1 DMA underrun interrupt enable*/
-#define  DAC_CR_EN2                          0x00010000U        /*!<DAC channel2 enable */
-#define  DAC_CR_BOFF2                        0x00020000U        /*!<DAC channel2 output buffer disable */
-#define  DAC_CR_TEN2                         0x00040000U        /*!<DAC channel2 Trigger enable */
-
-#define  DAC_CR_TSEL2                        0x00380000U        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define  DAC_CR_TSEL2_0                      0x00080000U        /*!<Bit 0 */
-#define  DAC_CR_TSEL2_1                      0x00100000U        /*!<Bit 1 */
-#define  DAC_CR_TSEL2_2                      0x00200000U        /*!<Bit 2 */
-
-#define  DAC_CR_WAVE2                        0x00C00000U        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE2_0                      0x00400000U        /*!<Bit 0 */
-#define  DAC_CR_WAVE2_1                      0x00800000U        /*!<Bit 1 */
-
-#define  DAC_CR_MAMP2                        0x0F000000U        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP2_0                      0x01000000U        /*!<Bit 0 */
-#define  DAC_CR_MAMP2_1                      0x02000000U        /*!<Bit 1 */
-#define  DAC_CR_MAMP2_2                      0x04000000U        /*!<Bit 2 */
-#define  DAC_CR_MAMP2_3                      0x08000000U        /*!<Bit 3 */
-
-#define  DAC_CR_DMAEN2                       0x10000000U        /*!<DAC channel2 DMA enabled */
-#define  DAC_CR_DMAUDRIE2                    0x20000000U        /*!<DAC channel2 DMA underrun interrupt enable*/
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define  DAC_SWTRIGR_SWTRIG1                 0x01U               /*!<DAC channel1 software trigger */
-#define  DAC_SWTRIGR_SWTRIG2                 0x02U               /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define  DAC_DHR12R1_DACC1DHR                0x0FFFU            /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define  DAC_DHR12L1_DACC1DHR                0xFFF0U            /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define  DAC_DHR8R1_DACC1DHR                 0xFFU               /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define  DAC_DHR12R2_DACC2DHR                0x0FFFU            /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define  DAC_DHR12L2_DACC2DHR                0xFFF0U            /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define  DAC_DHR8R2_DACC2DHR                 0xFFU               /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define  DAC_DHR12RD_DACC1DHR                0x00000FFFU        /*!<DAC channel1 12-bit Right aligned data */
-#define  DAC_DHR12RD_DACC2DHR                0x0FFF0000U        /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define  DAC_DHR12LD_DACC1DHR                0x0000FFF0U        /*!<DAC channel1 12-bit Left aligned data */
-#define  DAC_DHR12LD_DACC2DHR                0xFFF00000U        /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define  DAC_DHR8RD_DACC1DHR                 0x00FFU            /*!<DAC channel1 8-bit Right aligned data */
-#define  DAC_DHR8RD_DACC2DHR                 0xFF00U            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define  DAC_DOR1_DACC1DOR                   0x0FFFU            /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define  DAC_DOR2_DACC2DOR                   0x0FFFU            /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define  DAC_SR_DMAUDR1                      0x00002000U        /*!<DAC channel1 DMA underrun flag */
-#define  DAC_SR_DMAUDR2                      0x20000000U        /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 Debug MCU                                  */
-/*                                                                            */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    DCMI                                    */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DCMI_CR register  ******************/
-#define DCMI_CR_CAPTURE                      0x00000001U
-#define DCMI_CR_CM                           0x00000002U
-#define DCMI_CR_CROP                         0x00000004U
-#define DCMI_CR_JPEG                         0x00000008U
-#define DCMI_CR_ESS                          0x00000010U
-#define DCMI_CR_PCKPOL                       0x00000020U
-#define DCMI_CR_HSPOL                        0x00000040U
-#define DCMI_CR_VSPOL                        0x00000080U
-#define DCMI_CR_FCRC_0                       0x00000100U
-#define DCMI_CR_FCRC_1                       0x00000200U
-#define DCMI_CR_EDM_0                        0x00000400U
-#define DCMI_CR_EDM_1                        0x00000800U
-#define DCMI_CR_CRE                          0x00001000U
-#define DCMI_CR_ENABLE                       0x00004000U
-
-/********************  Bits definition for DCMI_SR register  ******************/
-#define DCMI_SR_HSYNC                        0x00000001U
-#define DCMI_SR_VSYNC                        0x00000002U
-#define DCMI_SR_FNE                          0x00000004U
-
-/********************  Bits definition for DCMI_RIS register  *****************/
-#define DCMI_RIS_FRAME_RIS                   0x00000001U
-#define DCMI_RIS_OVR_RIS                     0x00000002U
-#define DCMI_RIS_ERR_RIS                     0x00000004U
-#define DCMI_RIS_VSYNC_RIS                   0x00000008U
-#define DCMI_RIS_LINE_RIS                    0x00000010U
-/* Legacy defines */
-#define DCMI_RISR_FRAME_RIS                  DCMI_RIS_FRAME_RIS
-#define DCMI_RISR_OVR_RIS                    DCMI_RIS_OVR_RIS
-#define DCMI_RISR_ERR_RIS                    DCMI_RIS_ERR_RIS
-#define DCMI_RISR_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS
-#define DCMI_RISR_LINE_RIS                   DCMI_RIS_LINE_RIS
-#define DCMI_RISR_OVF_RIS                    DCMI_RIS_OVR_RIS
-
-/********************  Bits definition for DCMI_IER register  *****************/
-#define DCMI_IER_FRAME_IE                    0x00000001U
-#define DCMI_IER_OVR_IE                      0x00000002U
-#define DCMI_IER_ERR_IE                      0x00000004U
-#define DCMI_IER_VSYNC_IE                    0x00000008U
-#define DCMI_IER_LINE_IE                     0x00000010U
-/* Legacy defines */
-#define DCMI_IER_OVF_IE                      DCMI_IER_OVR_IE
-
-/********************  Bits definition for DCMI_MIS register  *****************/
-#define DCMI_MIS_FRAME_MIS                   0x00000001U
-#define DCMI_MIS_OVR_MIS                     0x00000002U
-#define DCMI_MIS_ERR_MIS                     0x00000004U
-#define DCMI_MIS_VSYNC_MIS                   0x00000008U
-#define DCMI_MIS_LINE_MIS                    0x00000010U
-
-/* Legacy defines */
-#define DCMI_MISR_FRAME_MIS                  DCMI_MIS_FRAME_MIS
-#define DCMI_MISR_OVF_MIS                    DCMI_MIS_OVR_MIS
-#define DCMI_MISR_ERR_MIS                    DCMI_MIS_ERR_MIS
-#define DCMI_MISR_VSYNC_MIS                  DCMI_MIS_VSYNC_MIS
-#define DCMI_MISR_LINE_MIS                   DCMI_MIS_LINE_MIS
-
-/********************  Bits definition for DCMI_ICR register  *****************/
-#define DCMI_ICR_FRAME_ISC                   0x00000001U
-#define DCMI_ICR_OVR_ISC                     0x00000002U
-#define DCMI_ICR_ERR_ISC                     0x00000004U
-#define DCMI_ICR_VSYNC_ISC                   0x00000008U
-#define DCMI_ICR_LINE_ISC                    0x00000010U
-
-/* Legacy defines */
-#define DCMI_ICR_OVF_ISC                     DCMI_ICR_OVR_ISC
-
-/********************  Bits definition for DCMI_ESCR register  ******************/
-#define DCMI_ESCR_FSC                        0x000000FFU
-#define DCMI_ESCR_LSC                        0x0000FF00U
-#define DCMI_ESCR_LEC                        0x00FF0000U
-#define DCMI_ESCR_FEC                        0xFF000000U
-
-/********************  Bits definition for DCMI_ESUR register  ******************/
-#define DCMI_ESUR_FSU                        0x000000FFU
-#define DCMI_ESUR_LSU                        0x0000FF00U
-#define DCMI_ESUR_LEU                        0x00FF0000U
-#define DCMI_ESUR_FEU                        0xFF000000U
-
-/********************  Bits definition for DCMI_CWSTRT register  ******************/
-#define DCMI_CWSTRT_HOFFCNT                  0x00003FFFU
-#define DCMI_CWSTRT_VST                      0x1FFF0000U
-
-/********************  Bits definition for DCMI_CWSIZE register  ******************/
-#define DCMI_CWSIZE_CAPCNT                   0x00003FFFU
-#define DCMI_CWSIZE_VLINE                    0x3FFF0000U
-
-/********************  Bits definition for DCMI_DR register  ******************/
-#define DCMI_DR_BYTE0                        0x000000FFU
-#define DCMI_DR_BYTE1                        0x0000FF00U
-#define DCMI_DR_BYTE2                        0x00FF0000U
-#define DCMI_DR_BYTE3                        0xFF000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                             DMA Controller                                 */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DMA_SxCR register  *****************/
-#define DMA_SxCR_CHSEL                       0x0E000000U
-#define DMA_SxCR_CHSEL_0                     0x02000000U
-#define DMA_SxCR_CHSEL_1                     0x04000000U
-#define DMA_SxCR_CHSEL_2                     0x08000000U
-#define DMA_SxCR_MBURST                      0x01800000U
-#define DMA_SxCR_MBURST_0                    0x00800000U
-#define DMA_SxCR_MBURST_1                    0x01000000U
-#define DMA_SxCR_PBURST                      0x00600000U
-#define DMA_SxCR_PBURST_0                    0x00200000U
-#define DMA_SxCR_PBURST_1                    0x00400000U
-#define DMA_SxCR_CT                          0x00080000U
-#define DMA_SxCR_DBM                         0x00040000U
-#define DMA_SxCR_PL                          0x00030000U
-#define DMA_SxCR_PL_0                        0x00010000U
-#define DMA_SxCR_PL_1                        0x00020000U
-#define DMA_SxCR_PINCOS                      0x00008000U
-#define DMA_SxCR_MSIZE                       0x00006000U
-#define DMA_SxCR_MSIZE_0                     0x00002000U
-#define DMA_SxCR_MSIZE_1                     0x00004000U
-#define DMA_SxCR_PSIZE                       0x00001800U
-#define DMA_SxCR_PSIZE_0                     0x00000800U
-#define DMA_SxCR_PSIZE_1                     0x00001000U
-#define DMA_SxCR_MINC                        0x00000400U
-#define DMA_SxCR_PINC                        0x00000200U
-#define DMA_SxCR_CIRC                        0x00000100U
-#define DMA_SxCR_DIR                         0x000000C0U
-#define DMA_SxCR_DIR_0                       0x00000040U
-#define DMA_SxCR_DIR_1                       0x00000080U
-#define DMA_SxCR_PFCTRL                      0x00000020U
-#define DMA_SxCR_TCIE                        0x00000010U
-#define DMA_SxCR_HTIE                        0x00000008U
-#define DMA_SxCR_TEIE                        0x00000004U
-#define DMA_SxCR_DMEIE                       0x00000002U
-#define DMA_SxCR_EN                          0x00000001U
-
-/* Legacy defines */
-#define DMA_SxCR_ACK                         0x00100000U
-
-/********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            0x0000FFFFU
-#define DMA_SxNDT_0                          0x00000001U
-#define DMA_SxNDT_1                          0x00000002U
-#define DMA_SxNDT_2                          0x00000004U
-#define DMA_SxNDT_3                          0x00000008U
-#define DMA_SxNDT_4                          0x00000010U
-#define DMA_SxNDT_5                          0x00000020U
-#define DMA_SxNDT_6                          0x00000040U
-#define DMA_SxNDT_7                          0x00000080U
-#define DMA_SxNDT_8                          0x00000100U
-#define DMA_SxNDT_9                          0x00000200U
-#define DMA_SxNDT_10                         0x00000400U
-#define DMA_SxNDT_11                         0x00000800U
-#define DMA_SxNDT_12                         0x00001000U
-#define DMA_SxNDT_13                         0x00002000U
-#define DMA_SxNDT_14                         0x00004000U
-#define DMA_SxNDT_15                         0x00008000U
-
-/********************  Bits definition for DMA_SxFCR register  ****************/ 
-#define DMA_SxFCR_FEIE                       0x00000080U
-#define DMA_SxFCR_FS                         0x00000038U
-#define DMA_SxFCR_FS_0                       0x00000008U
-#define DMA_SxFCR_FS_1                       0x00000010U
-#define DMA_SxFCR_FS_2                       0x00000020U
-#define DMA_SxFCR_DMDIS                      0x00000004U
-#define DMA_SxFCR_FTH                        0x00000003U
-#define DMA_SxFCR_FTH_0                      0x00000001U
-#define DMA_SxFCR_FTH_1                      0x00000002U
-
-/********************  Bits definition for DMA_LISR register  *****************/ 
-#define DMA_LISR_TCIF3                       0x08000000U
-#define DMA_LISR_HTIF3                       0x04000000U
-#define DMA_LISR_TEIF3                       0x02000000U
-#define DMA_LISR_DMEIF3                      0x01000000U
-#define DMA_LISR_FEIF3                       0x00400000U
-#define DMA_LISR_TCIF2                       0x00200000U
-#define DMA_LISR_HTIF2                       0x00100000U
-#define DMA_LISR_TEIF2                       0x00080000U
-#define DMA_LISR_DMEIF2                      0x00040000U
-#define DMA_LISR_FEIF2                       0x00010000U
-#define DMA_LISR_TCIF1                       0x00000800U
-#define DMA_LISR_HTIF1                       0x00000400U
-#define DMA_LISR_TEIF1                       0x00000200U
-#define DMA_LISR_DMEIF1                      0x00000100U
-#define DMA_LISR_FEIF1                       0x00000040U
-#define DMA_LISR_TCIF0                       0x00000020U
-#define DMA_LISR_HTIF0                       0x00000010U
-#define DMA_LISR_TEIF0                       0x00000008U
-#define DMA_LISR_DMEIF0                      0x00000004U
-#define DMA_LISR_FEIF0                       0x00000001U
-
-/********************  Bits definition for DMA_HISR register  *****************/ 
-#define DMA_HISR_TCIF7                       0x08000000U
-#define DMA_HISR_HTIF7                       0x04000000U
-#define DMA_HISR_TEIF7                       0x02000000U
-#define DMA_HISR_DMEIF7                      0x01000000U
-#define DMA_HISR_FEIF7                       0x00400000U
-#define DMA_HISR_TCIF6                       0x00200000U
-#define DMA_HISR_HTIF6                       0x00100000U
-#define DMA_HISR_TEIF6                       0x00080000U
-#define DMA_HISR_DMEIF6                      0x00040000U
-#define DMA_HISR_FEIF6                       0x00010000U
-#define DMA_HISR_TCIF5                       0x00000800U
-#define DMA_HISR_HTIF5                       0x00000400U
-#define DMA_HISR_TEIF5                       0x00000200U
-#define DMA_HISR_DMEIF5                      0x00000100U
-#define DMA_HISR_FEIF5                       0x00000040U
-#define DMA_HISR_TCIF4                       0x00000020U
-#define DMA_HISR_HTIF4                       0x00000010U
-#define DMA_HISR_TEIF4                       0x00000008U
-#define DMA_HISR_DMEIF4                      0x00000004U
-#define DMA_HISR_FEIF4                       0x00000001U
-
-/********************  Bits definition for DMA_LIFCR register  ****************/ 
-#define DMA_LIFCR_CTCIF3                     0x08000000U
-#define DMA_LIFCR_CHTIF3                     0x04000000U
-#define DMA_LIFCR_CTEIF3                     0x02000000U
-#define DMA_LIFCR_CDMEIF3                    0x01000000U
-#define DMA_LIFCR_CFEIF3                     0x00400000U
-#define DMA_LIFCR_CTCIF2                     0x00200000U
-#define DMA_LIFCR_CHTIF2                     0x00100000U
-#define DMA_LIFCR_CTEIF2                     0x00080000U
-#define DMA_LIFCR_CDMEIF2                    0x00040000U
-#define DMA_LIFCR_CFEIF2                     0x00010000U
-#define DMA_LIFCR_CTCIF1                     0x00000800U
-#define DMA_LIFCR_CHTIF1                     0x00000400U
-#define DMA_LIFCR_CTEIF1                     0x00000200U
-#define DMA_LIFCR_CDMEIF1                    0x00000100U
-#define DMA_LIFCR_CFEIF1                     0x00000040U
-#define DMA_LIFCR_CTCIF0                     0x00000020U
-#define DMA_LIFCR_CHTIF0                     0x00000010U
-#define DMA_LIFCR_CTEIF0                     0x00000008U
-#define DMA_LIFCR_CDMEIF0                    0x00000004U
-#define DMA_LIFCR_CFEIF0                     0x00000001U
-
-/********************  Bits definition for DMA_HIFCR  register  ****************/ 
-#define DMA_HIFCR_CTCIF7                     0x08000000U
-#define DMA_HIFCR_CHTIF7                     0x04000000U
-#define DMA_HIFCR_CTEIF7                     0x02000000U
-#define DMA_HIFCR_CDMEIF7                    0x01000000U
-#define DMA_HIFCR_CFEIF7                     0x00400000U
-#define DMA_HIFCR_CTCIF6                     0x00200000U
-#define DMA_HIFCR_CHTIF6                     0x00100000U
-#define DMA_HIFCR_CTEIF6                     0x00080000U
-#define DMA_HIFCR_CDMEIF6                    0x00040000U
-#define DMA_HIFCR_CFEIF6                     0x00010000U
-#define DMA_HIFCR_CTCIF5                     0x00000800U
-#define DMA_HIFCR_CHTIF5                     0x00000400U
-#define DMA_HIFCR_CTEIF5                     0x00000200U
-#define DMA_HIFCR_CDMEIF5                    0x00000100U
-#define DMA_HIFCR_CFEIF5                     0x00000040U
-#define DMA_HIFCR_CTCIF4                     0x00000020U
-#define DMA_HIFCR_CHTIF4                     0x00000010U
-#define DMA_HIFCR_CTEIF4                     0x00000008U
-#define DMA_HIFCR_CDMEIF4                    0x00000004U
-#define DMA_HIFCR_CFEIF4                     0x00000001U
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                    External Interrupt/Event Controller                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    FLASH                                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    0x0000000FU
-#define FLASH_ACR_LATENCY_0WS                0x00000000U
-#define FLASH_ACR_LATENCY_1WS                0x00000001U
-#define FLASH_ACR_LATENCY_2WS                0x00000002U
-#define FLASH_ACR_LATENCY_3WS                0x00000003U
-#define FLASH_ACR_LATENCY_4WS                0x00000004U
-#define FLASH_ACR_LATENCY_5WS                0x00000005U
-#define FLASH_ACR_LATENCY_6WS                0x00000006U
-#define FLASH_ACR_LATENCY_7WS                0x00000007U
-
-#define FLASH_ACR_PRFTEN                     0x00000100U
-#define FLASH_ACR_ICEN                       0x00000200U
-#define FLASH_ACR_DCEN                       0x00000400U
-#define FLASH_ACR_ICRST                      0x00000800U
-#define FLASH_ACR_DCRST                      0x00001000U
-#define FLASH_ACR_BYTE0_ADDRESS              0x40023C00U
-#define FLASH_ACR_BYTE2_ADDRESS              0x40023C03U
-
-/*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         0x00000001U
-#define FLASH_SR_SOP                         0x00000002U
-#define FLASH_SR_WRPERR                      0x00000010U
-#define FLASH_SR_PGAERR                      0x00000020U
-#define FLASH_SR_PGPERR                      0x00000040U
-#define FLASH_SR_PGSERR                      0x00000080U
-#define FLASH_SR_BSY                         0x00010000U
-
-/*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          0x00000001U
-#define FLASH_CR_SER                         0x00000002U
-#define FLASH_CR_MER                         0x00000004U
-#define FLASH_CR_SNB                         0x000000F8U
-#define FLASH_CR_SNB_0                       0x00000008U
-#define FLASH_CR_SNB_1                       0x00000010U
-#define FLASH_CR_SNB_2                       0x00000020U
-#define FLASH_CR_SNB_3                       0x00000040U
-#define FLASH_CR_SNB_4                       0x00000080U
-#define FLASH_CR_PSIZE                       0x00000300U
-#define FLASH_CR_PSIZE_0                     0x00000100U
-#define FLASH_CR_PSIZE_1                     0x00000200U
-#define FLASH_CR_STRT                        0x00010000U
-#define FLASH_CR_EOPIE                       0x01000000U
-#define FLASH_CR_LOCK                        0x80000000U
-
-/*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                 0x00000001U
-#define FLASH_OPTCR_OPTSTRT                 0x00000002U
-#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
-#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
-#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
-
-#define FLASH_OPTCR_WDG_SW                  0x00000020U
-#define FLASH_OPTCR_nRST_STOP               0x00000040U
-#define FLASH_OPTCR_nRST_STDBY              0x00000080U
-#define FLASH_OPTCR_RDP                     0x0000FF00U
-#define FLASH_OPTCR_RDP_0                   0x00000100U
-#define FLASH_OPTCR_RDP_1                   0x00000200U
-#define FLASH_OPTCR_RDP_2                   0x00000400U
-#define FLASH_OPTCR_RDP_3                   0x00000800U
-#define FLASH_OPTCR_RDP_4                   0x00001000U
-#define FLASH_OPTCR_RDP_5                   0x00002000U
-#define FLASH_OPTCR_RDP_6                   0x00004000U
-#define FLASH_OPTCR_RDP_7                   0x00008000U
-#define FLASH_OPTCR_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR_nWRP_0                  0x00010000U
-#define FLASH_OPTCR_nWRP_1                  0x00020000U
-#define FLASH_OPTCR_nWRP_2                  0x00040000U
-#define FLASH_OPTCR_nWRP_3                  0x00080000U
-#define FLASH_OPTCR_nWRP_4                  0x00100000U
-#define FLASH_OPTCR_nWRP_5                  0x00200000U
-#define FLASH_OPTCR_nWRP_6                  0x00400000U
-#define FLASH_OPTCR_nWRP_7                  0x00800000U
-#define FLASH_OPTCR_nWRP_8                  0x01000000U
-#define FLASH_OPTCR_nWRP_9                  0x02000000U
-#define FLASH_OPTCR_nWRP_10                 0x04000000U
-#define FLASH_OPTCR_nWRP_11                 0x08000000U
-                                             
-/******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR1_nWRP_0                  0x00010000U
-#define FLASH_OPTCR1_nWRP_1                  0x00020000U
-#define FLASH_OPTCR1_nWRP_2                  0x00040000U
-#define FLASH_OPTCR1_nWRP_3                  0x00080000U
-#define FLASH_OPTCR1_nWRP_4                  0x00100000U
-#define FLASH_OPTCR1_nWRP_5                  0x00200000U
-#define FLASH_OPTCR1_nWRP_6                  0x00400000U
-#define FLASH_OPTCR1_nWRP_7                  0x00800000U
-#define FLASH_OPTCR1_nWRP_8                  0x01000000U
-#define FLASH_OPTCR1_nWRP_9                  0x02000000U
-#define FLASH_OPTCR1_nWRP_10                 0x04000000U
-#define FLASH_OPTCR1_nWRP_11                 0x08000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Flexible Static Memory Controller                    */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for FSMC_BCR1 register  *******************/
-#define  FSMC_BCR1_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FSMC_BCR1_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FSMC_BCR1_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FSMC_BCR1_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FSMC_BCR1_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FSMC_BCR1_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR1_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FSMC_BCR1_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FSMC_BCR1_FACCEN                    0x00000040U        /*!<Flash access enable                    */
-#define  FSMC_BCR1_BURSTEN                   0x00000100U        /*!<Burst enable bit                       */
-#define  FSMC_BCR1_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit               */
-#define  FSMC_BCR1_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support             */
-#define  FSMC_BCR1_WAITCFG                   0x00000800U        /*!<Wait timing configuration              */
-#define  FSMC_BCR1_WREN                      0x00001000U        /*!<Write enable bit                       */
-#define  FSMC_BCR1_WAITEN                    0x00002000U        /*!<Wait enable bit                        */
-#define  FSMC_BCR1_EXTMOD                    0x00004000U        /*!<Extended mode enable                   */
-#define  FSMC_BCR1_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait                      */
-#define  FSMC_BCR1_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FSMC_BCR1_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FSMC_BCR1_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FSMC_BCR1_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FSMC_BCR1_CBURSTRW                  0x00080000U        /*!<Write burst enable                     */
-
-/******************  Bit definition for FSMC_BCR2 register  *******************/
-#define  FSMC_BCR2_MBKEN                     0x00000001U        /*!<Memory bank enable bit                */
-#define  FSMC_BCR2_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FSMC_BCR2_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FSMC_BCR2_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FSMC_BCR2_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FSMC_BCR2_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR2_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FSMC_BCR2_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FSMC_BCR2_FACCEN                    0x00000040U        /*!<Flash access enable                    */
-#define  FSMC_BCR2_BURSTEN                   0x00000100U        /*!<Burst enable bit                       */
-#define  FSMC_BCR2_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit               */
-#define  FSMC_BCR2_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support             */
-#define  FSMC_BCR2_WAITCFG                   0x00000800U        /*!<Wait timing configuration              */
-#define  FSMC_BCR2_WREN                      0x00001000U        /*!<Write enable bit                       */
-#define  FSMC_BCR2_WAITEN                    0x00002000U        /*!<Wait enable bit                        */
-#define  FSMC_BCR2_EXTMOD                    0x00004000U        /*!<Extended mode enable                   */
-#define  FSMC_BCR2_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait                      */
-#define  FSMC_BCR2_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FSMC_BCR2_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FSMC_BCR2_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FSMC_BCR2_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FSMC_BCR2_CBURSTRW                  0x00080000U        /*!<Write burst enable                     */
-
-/******************  Bit definition for FSMC_BCR3 register  *******************/
-#define  FSMC_BCR3_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FSMC_BCR3_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FSMC_BCR3_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FSMC_BCR3_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FSMC_BCR3_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FSMC_BCR3_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR3_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FSMC_BCR3_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FSMC_BCR3_FACCEN                    0x00000040U        /*!<Flash access enable                    */
-#define  FSMC_BCR3_BURSTEN                   0x00000100U        /*!<Burst enable bit                       */
-#define  FSMC_BCR3_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit               */
-#define  FSMC_BCR3_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support             */
-#define  FSMC_BCR3_WAITCFG                   0x00000800U        /*!<Wait timing configuration              */
-#define  FSMC_BCR3_WREN                      0x00001000U        /*!<Write enable bit                       */
-#define  FSMC_BCR3_WAITEN                    0x00002000U        /*!<Wait enable bit                        */
-#define  FSMC_BCR3_EXTMOD                    0x00004000U        /*!<Extended mode enable                   */
-#define  FSMC_BCR3_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait                      */
-#define  FSMC_BCR3_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FSMC_BCR3_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FSMC_BCR3_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FSMC_BCR3_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FSMC_BCR3_CBURSTRW                  0x00080000U        /*!<Write burst enable                     */
-
-/******************  Bit definition for FSMC_BCR4 register  *******************/
-#define  FSMC_BCR4_MBKEN                     0x00000001U        /*!<Memory bank enable bit */
-#define  FSMC_BCR4_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FSMC_BCR4_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FSMC_BCR4_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FSMC_BCR4_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FSMC_BCR4_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR4_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FSMC_BCR4_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FSMC_BCR4_FACCEN                    0x00000040U        /*!<Flash access enable                    */
-#define  FSMC_BCR4_BURSTEN                   0x00000100U        /*!<Burst enable bit                       */
-#define  FSMC_BCR4_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit               */
-#define  FSMC_BCR4_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support             */
-#define  FSMC_BCR4_WAITCFG                   0x00000800U        /*!<Wait timing configuration              */
-#define  FSMC_BCR4_WREN                      0x00001000U        /*!<Write enable bit                       */
-#define  FSMC_BCR4_WAITEN                    0x00002000U        /*!<Wait enable bit                        */
-#define  FSMC_BCR4_EXTMOD                    0x00004000U        /*!<Extended mode enable                   */
-#define  FSMC_BCR4_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait                      */
-#define  FSMC_BCR4_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FSMC_BCR4_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FSMC_BCR4_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FSMC_BCR4_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FSMC_BCR4_CBURSTRW                  0x00080000U        /*!<Write burst enable                     */
-
-/******************  Bit definition for FSMC_BTR1 register  ******************/
-#define  FSMC_BTR1_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR1_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FSMC_BTR1_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FSMC_BTR1_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FSMC_BTR1_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BTR1_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR1_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FSMC_BTR1_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FSMC_BTR1_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FSMC_BTR1_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BTR1_DATAST                    0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */
-#define  FSMC_BTR1_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FSMC_BTR1_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FSMC_BTR1_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FSMC_BTR1_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FSMC_BTR1_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FSMC_BTR1_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FSMC_BTR1_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FSMC_BTR1_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BTR1_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR1_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FSMC_BTR1_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FSMC_BTR1_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FSMC_BTR1_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BTR1_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR1_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FSMC_BTR1_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FSMC_BTR1_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FSMC_BTR1_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FSMC_BTR1_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR1_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FSMC_BTR1_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FSMC_BTR1_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FSMC_BTR1_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FSMC_BTR1_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR1_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FSMC_BTR1_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BTR2 register  *******************/
-#define  FSMC_BTR2_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR2_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FSMC_BTR2_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FSMC_BTR2_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FSMC_BTR2_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BTR2_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR2_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FSMC_BTR2_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FSMC_BTR2_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FSMC_BTR2_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BTR2_DATAST                    0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */
-#define  FSMC_BTR2_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FSMC_BTR2_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FSMC_BTR2_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FSMC_BTR2_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FSMC_BTR2_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FSMC_BTR2_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FSMC_BTR2_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FSMC_BTR2_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BTR2_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR2_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FSMC_BTR2_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FSMC_BTR2_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FSMC_BTR2_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BTR2_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR2_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FSMC_BTR2_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FSMC_BTR2_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FSMC_BTR2_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FSMC_BTR2_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR2_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FSMC_BTR2_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FSMC_BTR2_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FSMC_BTR2_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FSMC_BTR2_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR2_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FSMC_BTR2_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/*******************  Bit definition for FSMC_BTR3 register  *******************/
-#define  FSMC_BTR3_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR3_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FSMC_BTR3_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FSMC_BTR3_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FSMC_BTR3_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BTR3_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR3_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FSMC_BTR3_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FSMC_BTR3_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FSMC_BTR3_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BTR3_DATAST                    0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */
-#define  FSMC_BTR3_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FSMC_BTR3_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FSMC_BTR3_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FSMC_BTR3_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FSMC_BTR3_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FSMC_BTR3_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FSMC_BTR3_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FSMC_BTR3_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BTR3_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR3_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FSMC_BTR3_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FSMC_BTR3_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FSMC_BTR3_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BTR3_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR3_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FSMC_BTR3_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FSMC_BTR3_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FSMC_BTR3_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FSMC_BTR3_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR3_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FSMC_BTR3_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FSMC_BTR3_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FSMC_BTR3_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FSMC_BTR3_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR3_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FSMC_BTR3_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BTR4 register  *******************/
-#define  FSMC_BTR4_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR4_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FSMC_BTR4_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FSMC_BTR4_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FSMC_BTR4_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BTR4_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR4_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FSMC_BTR4_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FSMC_BTR4_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FSMC_BTR4_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BTR4_DATAST                    0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */
-#define  FSMC_BTR4_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FSMC_BTR4_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FSMC_BTR4_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FSMC_BTR4_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FSMC_BTR4_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FSMC_BTR4_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FSMC_BTR4_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FSMC_BTR4_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BTR4_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR4_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FSMC_BTR4_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FSMC_BTR4_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FSMC_BTR4_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BTR4_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR4_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FSMC_BTR4_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FSMC_BTR4_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FSMC_BTR4_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FSMC_BTR4_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR4_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FSMC_BTR4_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FSMC_BTR4_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FSMC_BTR4_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FSMC_BTR4_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR4_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FSMC_BTR4_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR1 register  ******************/
-#define  FSMC_BWTR1_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR1_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FSMC_BWTR1_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FSMC_BWTR1_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FSMC_BWTR1_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BWTR1_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR1_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FSMC_BWTR1_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FSMC_BWTR1_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FSMC_BWTR1_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BWTR1_DATAST                   0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */
-#define  FSMC_BWTR1_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FSMC_BWTR1_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FSMC_BWTR1_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FSMC_BWTR1_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FSMC_BWTR1_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FSMC_BWTR1_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FSMC_BWTR1_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FSMC_BWTR1_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BWTR1_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FSMC_BWTR1_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FSMC_BWTR1_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FSMC_BWTR1_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FSMC_BWTR1_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BWTR1_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR1_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FSMC_BWTR1_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR2 register  ******************/
-#define  FSMC_BWTR2_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR2_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FSMC_BWTR2_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FSMC_BWTR2_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FSMC_BWTR2_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BWTR2_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR2_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FSMC_BWTR2_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FSMC_BWTR2_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FSMC_BWTR2_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BWTR2_DATAST                   0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */
-#define  FSMC_BWTR2_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FSMC_BWTR2_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FSMC_BWTR2_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FSMC_BWTR2_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FSMC_BWTR2_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FSMC_BWTR2_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FSMC_BWTR2_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FSMC_BWTR2_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BWTR2_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FSMC_BWTR2_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FSMC_BWTR2_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FSMC_BWTR2_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FSMC_BWTR2_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BWTR2_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR2_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FSMC_BWTR2_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR3 register  ******************/
-#define  FSMC_BWTR3_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR3_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FSMC_BWTR3_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FSMC_BWTR3_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FSMC_BWTR3_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BWTR3_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR3_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FSMC_BWTR3_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FSMC_BWTR3_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FSMC_BWTR3_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BWTR3_DATAST                   0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */
-#define  FSMC_BWTR3_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FSMC_BWTR3_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FSMC_BWTR3_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FSMC_BWTR3_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FSMC_BWTR3_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FSMC_BWTR3_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FSMC_BWTR3_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FSMC_BWTR3_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BWTR3_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FSMC_BWTR3_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FSMC_BWTR3_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FSMC_BWTR3_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FSMC_BWTR3_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BWTR3_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR3_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FSMC_BWTR3_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR4 register  ******************/
-#define  FSMC_BWTR4_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR4_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FSMC_BWTR4_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FSMC_BWTR4_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FSMC_BWTR4_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FSMC_BWTR4_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR4_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FSMC_BWTR4_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FSMC_BWTR4_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FSMC_BWTR4_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FSMC_BWTR4_DATAST                   0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */
-#define  FSMC_BWTR4_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FSMC_BWTR4_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FSMC_BWTR4_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FSMC_BWTR4_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FSMC_BWTR4_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FSMC_BWTR4_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FSMC_BWTR4_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FSMC_BWTR4_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_BWTR4_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FSMC_BWTR4_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FSMC_BWTR4_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FSMC_BWTR4_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FSMC_BWTR4_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FSMC_BWTR4_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR4_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FSMC_BWTR4_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_PCR2 register  *******************/
-#define  FSMC_PCR2_PWAITEN                   0x00000002U        /*!<Wait feature enable bit */
-#define  FSMC_PCR2_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FSMC_PCR2_PTYP                      0x00000008U        /*!<Memory type */
-
-#define  FSMC_PCR2_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FSMC_PCR2_PWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FSMC_PCR2_PWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FSMC_PCR2_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit */
-
-#define  FSMC_PCR2_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay) */
-#define  FSMC_PCR2_TCLR_0                    0x00000200U        /*!<Bit 0 */
-#define  FSMC_PCR2_TCLR_1                    0x00000400U        /*!<Bit 1 */
-#define  FSMC_PCR2_TCLR_2                    0x00000800U        /*!<Bit 2 */
-#define  FSMC_PCR2_TCLR_3                    0x00001000U        /*!<Bit 3 */
-
-#define  FSMC_PCR2_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay) */
-#define  FSMC_PCR2_TAR_0                     0x00002000U        /*!<Bit 0 */
-#define  FSMC_PCR2_TAR_1                     0x00004000U        /*!<Bit 1 */
-#define  FSMC_PCR2_TAR_2                     0x00008000U        /*!<Bit 2 */
-#define  FSMC_PCR2_TAR_3                     0x00010000U        /*!<Bit 3 */
-
-#define  FSMC_PCR2_ECCPS                     0x000E0000U        /*!<ECCPS[1:0] bits (ECC page size) */
-#define  FSMC_PCR2_ECCPS_0                   0x00020000U        /*!<Bit 0 */
-#define  FSMC_PCR2_ECCPS_1                   0x00040000U        /*!<Bit 1 */
-#define  FSMC_PCR2_ECCPS_2                   0x00080000U        /*!<Bit 2 */
-
-/******************  Bit definition for FSMC_PCR3 register  *******************/
-#define  FSMC_PCR3_PWAITEN                   0x00000002U        /*!<Wait feature enable bit */
-#define  FSMC_PCR3_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FSMC_PCR3_PTYP                      0x00000008U        /*!<Memory type */
-
-#define  FSMC_PCR3_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FSMC_PCR3_PWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FSMC_PCR3_PWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FSMC_PCR3_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit */
-
-#define  FSMC_PCR3_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay) */
-#define  FSMC_PCR3_TCLR_0                    0x00000200U        /*!<Bit 0 */
-#define  FSMC_PCR3_TCLR_1                    0x00000400U        /*!<Bit 1 */
-#define  FSMC_PCR3_TCLR_2                    0x00000800U        /*!<Bit 2 */
-#define  FSMC_PCR3_TCLR_3                    0x00001000U        /*!<Bit 3 */
-
-#define  FSMC_PCR3_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay) */
-#define  FSMC_PCR3_TAR_0                     0x00002000U        /*!<Bit 0 */
-#define  FSMC_PCR3_TAR_1                     0x00004000U        /*!<Bit 1 */
-#define  FSMC_PCR3_TAR_2                     0x00008000U        /*!<Bit 2 */
-#define  FSMC_PCR3_TAR_3                     0x00010000U        /*!<Bit 3 */
-
-#define  FSMC_PCR3_ECCPS                     0x000E0000U        /*!<ECCPS[2:0] bits (ECC page size) */
-#define  FSMC_PCR3_ECCPS_0                   0x00020000U        /*!<Bit 0 */
-#define  FSMC_PCR3_ECCPS_1                   0x00040000U        /*!<Bit 1 */
-#define  FSMC_PCR3_ECCPS_2                   0x00080000U        /*!<Bit 2 */
-
-/******************  Bit definition for FSMC_PCR4 register  *******************/
-#define  FSMC_PCR4_PWAITEN                   0x00000002U        /*!<Wait feature enable bit */
-#define  FSMC_PCR4_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FSMC_PCR4_PTYP                      0x00000008U        /*!<Memory type */
-
-#define  FSMC_PCR4_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FSMC_PCR4_PWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FSMC_PCR4_PWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FSMC_PCR4_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit */
-
-#define  FSMC_PCR4_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay) */
-#define  FSMC_PCR4_TCLR_0                    0x00000200U        /*!<Bit 0 */
-#define  FSMC_PCR4_TCLR_1                    0x00000400U        /*!<Bit 1 */
-#define  FSMC_PCR4_TCLR_2                    0x00000800U        /*!<Bit 2 */
-#define  FSMC_PCR4_TCLR_3                    0x00001000U        /*!<Bit 3 */
-
-#define  FSMC_PCR4_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay) */
-#define  FSMC_PCR4_TAR_0                     0x00002000U        /*!<Bit 0 */
-#define  FSMC_PCR4_TAR_1                     0x00004000U        /*!<Bit 1 */
-#define  FSMC_PCR4_TAR_2                     0x00008000U        /*!<Bit 2 */
-#define  FSMC_PCR4_TAR_3                     0x00010000U        /*!<Bit 3 */
-
-#define  FSMC_PCR4_ECCPS                     0x000E0000U        /*!<ECCPS[2:0] bits (ECC page size) */
-#define  FSMC_PCR4_ECCPS_0                   0x00020000U        /*!<Bit 0 */
-#define  FSMC_PCR4_ECCPS_1                   0x00040000U        /*!<Bit 1 */
-#define  FSMC_PCR4_ECCPS_2                   0x00080000U        /*!<Bit 2 */
-
-/*******************  Bit definition for FSMC_SR2 register  *******************/
-#define  FSMC_SR2_IRS                        0x01U               /*!<Interrupt Rising Edge status                */
-#define  FSMC_SR2_ILS                        0x02U               /*!<Interrupt Level status                      */
-#define  FSMC_SR2_IFS                        0x04U               /*!<Interrupt Falling Edge status               */
-#define  FSMC_SR2_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FSMC_SR2_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit        */
-#define  FSMC_SR2_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FSMC_SR2_FEMPT                      0x40U               /*!<FIFO empty */
-
-/*******************  Bit definition for FSMC_SR3 register  *******************/
-#define  FSMC_SR3_IRS                        0x01U               /*!<Interrupt Rising Edge status                */
-#define  FSMC_SR3_ILS                        0x02U               /*!<Interrupt Level status                      */
-#define  FSMC_SR3_IFS                        0x04U               /*!<Interrupt Falling Edge status               */
-#define  FSMC_SR3_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FSMC_SR3_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit        */
-#define  FSMC_SR3_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FSMC_SR3_FEMPT                      0x40U               /*!<FIFO empty */
-
-/*******************  Bit definition for FSMC_SR4 register  *******************/
-#define  FSMC_SR4_IRS                        0x01U               /*!<Interrupt Rising Edge status                 */
-#define  FSMC_SR4_ILS                        0x02U               /*!<Interrupt Level status                       */
-#define  FSMC_SR4_IFS                        0x04U               /*!<Interrupt Falling Edge status                */
-#define  FSMC_SR4_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit   */
-#define  FSMC_SR4_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit         */
-#define  FSMC_SR4_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit  */
-#define  FSMC_SR4_FEMPT                      0x40U               /*!<FIFO empty */
-
-/******************  Bit definition for FSMC_PMEM2 register  ******************/
-#define  FSMC_PMEM2_MEMSET2                  0x000000FFU        /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
-#define  FSMC_PMEM2_MEMSET2_0                0x00000001U        /*!<Bit 0 */
-#define  FSMC_PMEM2_MEMSET2_1                0x00000002U        /*!<Bit 1 */
-#define  FSMC_PMEM2_MEMSET2_2                0x00000004U        /*!<Bit 2 */
-#define  FSMC_PMEM2_MEMSET2_3                0x00000008U        /*!<Bit 3 */
-#define  FSMC_PMEM2_MEMSET2_4                0x00000010U        /*!<Bit 4 */
-#define  FSMC_PMEM2_MEMSET2_5                0x00000020U        /*!<Bit 5 */
-#define  FSMC_PMEM2_MEMSET2_6                0x00000040U        /*!<Bit 6 */
-#define  FSMC_PMEM2_MEMSET2_7                0x00000080U        /*!<Bit 7 */
-
-#define  FSMC_PMEM2_MEMWAIT2                 0x0000FF00U        /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
-#define  FSMC_PMEM2_MEMWAIT2_0               0x00000100U        /*!<Bit 0 */
-#define  FSMC_PMEM2_MEMWAIT2_1               0x00000200U        /*!<Bit 1 */
-#define  FSMC_PMEM2_MEMWAIT2_2               0x00000400U        /*!<Bit 2 */
-#define  FSMC_PMEM2_MEMWAIT2_3               0x00000800U        /*!<Bit 3 */
-#define  FSMC_PMEM2_MEMWAIT2_4               0x00001000U        /*!<Bit 4 */
-#define  FSMC_PMEM2_MEMWAIT2_5               0x00002000U        /*!<Bit 5 */
-#define  FSMC_PMEM2_MEMWAIT2_6               0x00004000U        /*!<Bit 6 */
-#define  FSMC_PMEM2_MEMWAIT2_7               0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_PMEM2_MEMHOLD2                 0x00FF0000U        /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
-#define  FSMC_PMEM2_MEMHOLD2_0               0x00010000U        /*!<Bit 0 */
-#define  FSMC_PMEM2_MEMHOLD2_1               0x00020000U        /*!<Bit 1 */
-#define  FSMC_PMEM2_MEMHOLD2_2               0x00040000U        /*!<Bit 2 */
-#define  FSMC_PMEM2_MEMHOLD2_3               0x00080000U        /*!<Bit 3 */
-#define  FSMC_PMEM2_MEMHOLD2_4               0x00100000U        /*!<Bit 4 */
-#define  FSMC_PMEM2_MEMHOLD2_5               0x00200000U        /*!<Bit 5 */
-#define  FSMC_PMEM2_MEMHOLD2_6               0x00400000U        /*!<Bit 6 */
-#define  FSMC_PMEM2_MEMHOLD2_7               0x00800000U        /*!<Bit 7 */
-
-#define  FSMC_PMEM2_MEMHIZ2                  0xFF000000U        /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
-#define  FSMC_PMEM2_MEMHIZ2_0                0x01000000U        /*!<Bit 0 */
-#define  FSMC_PMEM2_MEMHIZ2_1                0x02000000U        /*!<Bit 1 */
-#define  FSMC_PMEM2_MEMHIZ2_2                0x04000000U        /*!<Bit 2 */
-#define  FSMC_PMEM2_MEMHIZ2_3                0x08000000U        /*!<Bit 3 */
-#define  FSMC_PMEM2_MEMHIZ2_4                0x10000000U        /*!<Bit 4 */
-#define  FSMC_PMEM2_MEMHIZ2_5                0x20000000U        /*!<Bit 5 */
-#define  FSMC_PMEM2_MEMHIZ2_6                0x40000000U        /*!<Bit 6 */
-#define  FSMC_PMEM2_MEMHIZ2_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FSMC_PMEM3 register  ******************/
-#define  FSMC_PMEM3_MEMSET3                  0x000000FFU        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
-#define  FSMC_PMEM3_MEMSET3_0                0x00000001U        /*!<Bit 0 */
-#define  FSMC_PMEM3_MEMSET3_1                0x00000002U        /*!<Bit 1 */
-#define  FSMC_PMEM3_MEMSET3_2                0x00000004U        /*!<Bit 2 */
-#define  FSMC_PMEM3_MEMSET3_3                0x00000008U        /*!<Bit 3 */
-#define  FSMC_PMEM3_MEMSET3_4                0x00000010U        /*!<Bit 4 */
-#define  FSMC_PMEM3_MEMSET3_5                0x00000020U        /*!<Bit 5 */
-#define  FSMC_PMEM3_MEMSET3_6                0x00000040U        /*!<Bit 6 */
-#define  FSMC_PMEM3_MEMSET3_7                0x00000080U        /*!<Bit 7 */
-
-#define  FSMC_PMEM3_MEMWAIT3                 0x0000FF00U        /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
-#define  FSMC_PMEM3_MEMWAIT3_0               0x00000100U        /*!<Bit 0 */
-#define  FSMC_PMEM3_MEMWAIT3_1               0x00000200U        /*!<Bit 1 */
-#define  FSMC_PMEM3_MEMWAIT3_2               0x00000400U        /*!<Bit 2 */
-#define  FSMC_PMEM3_MEMWAIT3_3               0x00000800U        /*!<Bit 3 */
-#define  FSMC_PMEM3_MEMWAIT3_4               0x00001000U        /*!<Bit 4 */
-#define  FSMC_PMEM3_MEMWAIT3_5               0x00002000U        /*!<Bit 5 */
-#define  FSMC_PMEM3_MEMWAIT3_6               0x00004000U        /*!<Bit 6 */
-#define  FSMC_PMEM3_MEMWAIT3_7               0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_PMEM3_MEMHOLD3                 0x00FF0000U        /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
-#define  FSMC_PMEM3_MEMHOLD3_0               0x00010000U        /*!<Bit 0 */
-#define  FSMC_PMEM3_MEMHOLD3_1               0x00020000U        /*!<Bit 1 */
-#define  FSMC_PMEM3_MEMHOLD3_2               0x00040000U        /*!<Bit 2 */
-#define  FSMC_PMEM3_MEMHOLD3_3               0x00080000U        /*!<Bit 3 */
-#define  FSMC_PMEM3_MEMHOLD3_4               0x00100000U        /*!<Bit 4 */
-#define  FSMC_PMEM3_MEMHOLD3_5               0x00200000U        /*!<Bit 5 */
-#define  FSMC_PMEM3_MEMHOLD3_6               0x00400000U        /*!<Bit 6 */
-#define  FSMC_PMEM3_MEMHOLD3_7               0x00800000U        /*!<Bit 7 */
-
-#define  FSMC_PMEM3_MEMHIZ3                  0xFF000000U        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
-#define  FSMC_PMEM3_MEMHIZ3_0                0x01000000U        /*!<Bit 0 */
-#define  FSMC_PMEM3_MEMHIZ3_1                0x02000000U        /*!<Bit 1 */
-#define  FSMC_PMEM3_MEMHIZ3_2                0x04000000U        /*!<Bit 2 */
-#define  FSMC_PMEM3_MEMHIZ3_3                0x08000000U        /*!<Bit 3 */
-#define  FSMC_PMEM3_MEMHIZ3_4                0x10000000U        /*!<Bit 4 */
-#define  FSMC_PMEM3_MEMHIZ3_5                0x20000000U        /*!<Bit 5 */
-#define  FSMC_PMEM3_MEMHIZ3_6                0x40000000U        /*!<Bit 6 */
-#define  FSMC_PMEM3_MEMHIZ3_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FSMC_PMEM4 register  ******************/
-#define  FSMC_PMEM4_MEMSET4                  0x000000FFU        /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
-#define  FSMC_PMEM4_MEMSET4_0                0x00000001U        /*!<Bit 0 */
-#define  FSMC_PMEM4_MEMSET4_1                0x00000002U        /*!<Bit 1 */
-#define  FSMC_PMEM4_MEMSET4_2                0x00000004U        /*!<Bit 2 */
-#define  FSMC_PMEM4_MEMSET4_3                0x00000008U        /*!<Bit 3 */
-#define  FSMC_PMEM4_MEMSET4_4                0x00000010U        /*!<Bit 4 */
-#define  FSMC_PMEM4_MEMSET4_5                0x00000020U        /*!<Bit 5 */
-#define  FSMC_PMEM4_MEMSET4_6                0x00000040U        /*!<Bit 6 */
-#define  FSMC_PMEM4_MEMSET4_7                0x00000080U        /*!<Bit 7 */
-
-#define  FSMC_PMEM4_MEMWAIT4                 0x0000FF00U        /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
-#define  FSMC_PMEM4_MEMWAIT4_0               0x00000100U        /*!<Bit 0 */
-#define  FSMC_PMEM4_MEMWAIT4_1               0x00000200U        /*!<Bit 1 */
-#define  FSMC_PMEM4_MEMWAIT4_2               0x00000400U        /*!<Bit 2 */
-#define  FSMC_PMEM4_MEMWAIT4_3               0x00000800U        /*!<Bit 3 */
-#define  FSMC_PMEM4_MEMWAIT4_4               0x00001000U        /*!<Bit 4 */
-#define  FSMC_PMEM4_MEMWAIT4_5               0x00002000U        /*!<Bit 5 */
-#define  FSMC_PMEM4_MEMWAIT4_6               0x00004000U        /*!<Bit 6 */
-#define  FSMC_PMEM4_MEMWAIT4_7               0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_PMEM4_MEMHOLD4                 0x00FF0000U        /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
-#define  FSMC_PMEM4_MEMHOLD4_0               0x00010000U        /*!<Bit 0 */
-#define  FSMC_PMEM4_MEMHOLD4_1               0x00020000U        /*!<Bit 1 */
-#define  FSMC_PMEM4_MEMHOLD4_2               0x00040000U        /*!<Bit 2 */
-#define  FSMC_PMEM4_MEMHOLD4_3               0x00080000U        /*!<Bit 3 */
-#define  FSMC_PMEM4_MEMHOLD4_4               0x00100000U        /*!<Bit 4 */
-#define  FSMC_PMEM4_MEMHOLD4_5               0x00200000U        /*!<Bit 5 */
-#define  FSMC_PMEM4_MEMHOLD4_6               0x00400000U        /*!<Bit 6 */
-#define  FSMC_PMEM4_MEMHOLD4_7               0x00800000U        /*!<Bit 7 */
-
-#define  FSMC_PMEM4_MEMHIZ4                  0xFF000000U        /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
-#define  FSMC_PMEM4_MEMHIZ4_0                0x01000000U        /*!<Bit 0 */
-#define  FSMC_PMEM4_MEMHIZ4_1                0x02000000U        /*!<Bit 1 */
-#define  FSMC_PMEM4_MEMHIZ4_2                0x04000000U        /*!<Bit 2 */
-#define  FSMC_PMEM4_MEMHIZ4_3                0x08000000U        /*!<Bit 3 */
-#define  FSMC_PMEM4_MEMHIZ4_4                0x10000000U        /*!<Bit 4 */
-#define  FSMC_PMEM4_MEMHIZ4_5                0x20000000U        /*!<Bit 5 */
-#define  FSMC_PMEM4_MEMHIZ4_6                0x40000000U        /*!<Bit 6 */
-#define  FSMC_PMEM4_MEMHIZ4_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FSMC_PATT2 register  ******************/
-#define  FSMC_PATT2_ATTSET2                  0x000000FFU        /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
-#define  FSMC_PATT2_ATTSET2_0                0x00000001U        /*!<Bit 0 */
-#define  FSMC_PATT2_ATTSET2_1                0x00000002U        /*!<Bit 1 */
-#define  FSMC_PATT2_ATTSET2_2                0x00000004U        /*!<Bit 2 */
-#define  FSMC_PATT2_ATTSET2_3                0x00000008U        /*!<Bit 3 */
-#define  FSMC_PATT2_ATTSET2_4                0x00000010U        /*!<Bit 4 */
-#define  FSMC_PATT2_ATTSET2_5                0x00000020U        /*!<Bit 5 */
-#define  FSMC_PATT2_ATTSET2_6                0x00000040U        /*!<Bit 6 */
-#define  FSMC_PATT2_ATTSET2_7                0x00000080U        /*!<Bit 7 */
-
-#define  FSMC_PATT2_ATTWAIT2                 0x0000FF00U        /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
-#define  FSMC_PATT2_ATTWAIT2_0               0x00000100U        /*!<Bit 0 */
-#define  FSMC_PATT2_ATTWAIT2_1               0x00000200U        /*!<Bit 1 */
-#define  FSMC_PATT2_ATTWAIT2_2               0x00000400U        /*!<Bit 2 */
-#define  FSMC_PATT2_ATTWAIT2_3               0x00000800U        /*!<Bit 3 */
-#define  FSMC_PATT2_ATTWAIT2_4               0x00001000U        /*!<Bit 4 */
-#define  FSMC_PATT2_ATTWAIT2_5               0x00002000U        /*!<Bit 5 */
-#define  FSMC_PATT2_ATTWAIT2_6               0x00004000U        /*!<Bit 6 */
-#define  FSMC_PATT2_ATTWAIT2_7               0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_PATT2_ATTHOLD2                 0x00FF0000U        /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
-#define  FSMC_PATT2_ATTHOLD2_0               0x00010000U        /*!<Bit 0 */
-#define  FSMC_PATT2_ATTHOLD2_1               0x00020000U        /*!<Bit 1 */
-#define  FSMC_PATT2_ATTHOLD2_2               0x00040000U        /*!<Bit 2 */
-#define  FSMC_PATT2_ATTHOLD2_3               0x00080000U        /*!<Bit 3 */
-#define  FSMC_PATT2_ATTHOLD2_4               0x00100000U        /*!<Bit 4 */
-#define  FSMC_PATT2_ATTHOLD2_5               0x00200000U        /*!<Bit 5 */
-#define  FSMC_PATT2_ATTHOLD2_6               0x00400000U        /*!<Bit 6 */
-#define  FSMC_PATT2_ATTHOLD2_7               0x00800000U        /*!<Bit 7 */
-
-#define  FSMC_PATT2_ATTHIZ2                  0xFF000000U        /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
-#define  FSMC_PATT2_ATTHIZ2_0                0x01000000U        /*!<Bit 0 */
-#define  FSMC_PATT2_ATTHIZ2_1                0x02000000U        /*!<Bit 1 */
-#define  FSMC_PATT2_ATTHIZ2_2                0x04000000U        /*!<Bit 2 */
-#define  FSMC_PATT2_ATTHIZ2_3                0x08000000U        /*!<Bit 3 */
-#define  FSMC_PATT2_ATTHIZ2_4                0x10000000U        /*!<Bit 4 */
-#define  FSMC_PATT2_ATTHIZ2_5                0x20000000U        /*!<Bit 5 */
-#define  FSMC_PATT2_ATTHIZ2_6                0x40000000U        /*!<Bit 6 */
-#define  FSMC_PATT2_ATTHIZ2_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FSMC_PATT3 register  ******************/
-#define  FSMC_PATT3_ATTSET3                  0x000000FFU        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
-#define  FSMC_PATT3_ATTSET3_0                0x00000001U        /*!<Bit 0 */
-#define  FSMC_PATT3_ATTSET3_1                0x00000002U        /*!<Bit 1 */
-#define  FSMC_PATT3_ATTSET3_2                0x00000004U        /*!<Bit 2 */
-#define  FSMC_PATT3_ATTSET3_3                0x00000008U        /*!<Bit 3 */
-#define  FSMC_PATT3_ATTSET3_4                0x00000010U        /*!<Bit 4 */
-#define  FSMC_PATT3_ATTSET3_5                0x00000020U        /*!<Bit 5 */
-#define  FSMC_PATT3_ATTSET3_6                0x00000040U        /*!<Bit 6 */
-#define  FSMC_PATT3_ATTSET3_7                0x00000080U        /*!<Bit 7 */
-
-#define  FSMC_PATT3_ATTWAIT3                 0x0000FF00U        /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
-#define  FSMC_PATT3_ATTWAIT3_0               0x00000100U        /*!<Bit 0 */
-#define  FSMC_PATT3_ATTWAIT3_1               0x00000200U        /*!<Bit 1 */
-#define  FSMC_PATT3_ATTWAIT3_2               0x00000400U        /*!<Bit 2 */
-#define  FSMC_PATT3_ATTWAIT3_3               0x00000800U        /*!<Bit 3 */
-#define  FSMC_PATT3_ATTWAIT3_4               0x00001000U        /*!<Bit 4 */
-#define  FSMC_PATT3_ATTWAIT3_5               0x00002000U        /*!<Bit 5 */
-#define  FSMC_PATT3_ATTWAIT3_6               0x00004000U        /*!<Bit 6 */
-#define  FSMC_PATT3_ATTWAIT3_7               0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_PATT3_ATTHOLD3                 0x00FF0000U        /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
-#define  FSMC_PATT3_ATTHOLD3_0               0x00010000U        /*!<Bit 0 */
-#define  FSMC_PATT3_ATTHOLD3_1               0x00020000U        /*!<Bit 1 */
-#define  FSMC_PATT3_ATTHOLD3_2               0x00040000U        /*!<Bit 2 */
-#define  FSMC_PATT3_ATTHOLD3_3               0x00080000U        /*!<Bit 3 */
-#define  FSMC_PATT3_ATTHOLD3_4               0x00100000U        /*!<Bit 4 */
-#define  FSMC_PATT3_ATTHOLD3_5               0x00200000U        /*!<Bit 5 */
-#define  FSMC_PATT3_ATTHOLD3_6               0x00400000U        /*!<Bit 6 */
-#define  FSMC_PATT3_ATTHOLD3_7               0x00800000U        /*!<Bit 7 */
-
-#define  FSMC_PATT3_ATTHIZ3                  0xFF000000U        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
-#define  FSMC_PATT3_ATTHIZ3_0                0x01000000U        /*!<Bit 0 */
-#define  FSMC_PATT3_ATTHIZ3_1                0x02000000U        /*!<Bit 1 */
-#define  FSMC_PATT3_ATTHIZ3_2                0x04000000U        /*!<Bit 2 */
-#define  FSMC_PATT3_ATTHIZ3_3                0x08000000U        /*!<Bit 3 */
-#define  FSMC_PATT3_ATTHIZ3_4                0x10000000U        /*!<Bit 4 */
-#define  FSMC_PATT3_ATTHIZ3_5                0x20000000U        /*!<Bit 5 */
-#define  FSMC_PATT3_ATTHIZ3_6                0x40000000U        /*!<Bit 6 */
-#define  FSMC_PATT3_ATTHIZ3_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FSMC_PATT4 register  ******************/
-#define  FSMC_PATT4_ATTSET4                  0x000000FFU        /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
-#define  FSMC_PATT4_ATTSET4_0                0x00000001U        /*!<Bit 0 */
-#define  FSMC_PATT4_ATTSET4_1                0x00000002U        /*!<Bit 1 */
-#define  FSMC_PATT4_ATTSET4_2                0x00000004U        /*!<Bit 2 */
-#define  FSMC_PATT4_ATTSET4_3                0x00000008U        /*!<Bit 3 */
-#define  FSMC_PATT4_ATTSET4_4                0x00000010U        /*!<Bit 4 */
-#define  FSMC_PATT4_ATTSET4_5                0x00000020U        /*!<Bit 5 */
-#define  FSMC_PATT4_ATTSET4_6                0x00000040U        /*!<Bit 6 */
-#define  FSMC_PATT4_ATTSET4_7                0x00000080U        /*!<Bit 7 */
-
-#define  FSMC_PATT4_ATTWAIT4                 0x0000FF00U        /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
-#define  FSMC_PATT4_ATTWAIT4_0               0x00000100U        /*!<Bit 0 */
-#define  FSMC_PATT4_ATTWAIT4_1               0x00000200U        /*!<Bit 1 */
-#define  FSMC_PATT4_ATTWAIT4_2               0x00000400U        /*!<Bit 2 */
-#define  FSMC_PATT4_ATTWAIT4_3               0x00000800U        /*!<Bit 3 */
-#define  FSMC_PATT4_ATTWAIT4_4               0x00001000U        /*!<Bit 4 */
-#define  FSMC_PATT4_ATTWAIT4_5               0x00002000U        /*!<Bit 5 */
-#define  FSMC_PATT4_ATTWAIT4_6               0x00004000U        /*!<Bit 6 */
-#define  FSMC_PATT4_ATTWAIT4_7               0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_PATT4_ATTHOLD4                 0x00FF0000U        /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
-#define  FSMC_PATT4_ATTHOLD4_0               0x00010000U        /*!<Bit 0 */
-#define  FSMC_PATT4_ATTHOLD4_1               0x00020000U        /*!<Bit 1 */
-#define  FSMC_PATT4_ATTHOLD4_2               0x00040000U        /*!<Bit 2 */
-#define  FSMC_PATT4_ATTHOLD4_3               0x00080000U        /*!<Bit 3 */
-#define  FSMC_PATT4_ATTHOLD4_4               0x00100000U        /*!<Bit 4 */
-#define  FSMC_PATT4_ATTHOLD4_5               0x00200000U        /*!<Bit 5 */
-#define  FSMC_PATT4_ATTHOLD4_6               0x00400000U        /*!<Bit 6 */
-#define  FSMC_PATT4_ATTHOLD4_7               0x00800000U        /*!<Bit 7 */
-
-#define  FSMC_PATT4_ATTHIZ4                  0xFF000000U        /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
-#define  FSMC_PATT4_ATTHIZ4_0                0x01000000U        /*!<Bit 0 */
-#define  FSMC_PATT4_ATTHIZ4_1                0x02000000U        /*!<Bit 1 */
-#define  FSMC_PATT4_ATTHIZ4_2                0x04000000U        /*!<Bit 2 */
-#define  FSMC_PATT4_ATTHIZ4_3                0x08000000U        /*!<Bit 3 */
-#define  FSMC_PATT4_ATTHIZ4_4                0x10000000U        /*!<Bit 4 */
-#define  FSMC_PATT4_ATTHIZ4_5                0x20000000U        /*!<Bit 5 */
-#define  FSMC_PATT4_ATTHIZ4_6                0x40000000U        /*!<Bit 6 */
-#define  FSMC_PATT4_ATTHIZ4_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FSMC_PIO4 register  *******************/
-#define  FSMC_PIO4_IOSET4                    0x000000FFU        /*!<IOSET4[7:0] bits (I/O 4 setup time) */
-#define  FSMC_PIO4_IOSET4_0                  0x00000001U        /*!<Bit 0 */
-#define  FSMC_PIO4_IOSET4_1                  0x00000002U        /*!<Bit 1 */
-#define  FSMC_PIO4_IOSET4_2                  0x00000004U        /*!<Bit 2 */
-#define  FSMC_PIO4_IOSET4_3                  0x00000008U        /*!<Bit 3 */
-#define  FSMC_PIO4_IOSET4_4                  0x00000010U        /*!<Bit 4 */
-#define  FSMC_PIO4_IOSET4_5                  0x00000020U        /*!<Bit 5 */
-#define  FSMC_PIO4_IOSET4_6                  0x00000040U        /*!<Bit 6 */
-#define  FSMC_PIO4_IOSET4_7                  0x00000080U        /*!<Bit 7 */
-
-#define  FSMC_PIO4_IOWAIT4                   0x0000FF00U        /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
-#define  FSMC_PIO4_IOWAIT4_0                 0x00000100U        /*!<Bit 0 */
-#define  FSMC_PIO4_IOWAIT4_1                 0x00000200U        /*!<Bit 1 */
-#define  FSMC_PIO4_IOWAIT4_2                 0x00000400U        /*!<Bit 2 */
-#define  FSMC_PIO4_IOWAIT4_3                 0x00000800U        /*!<Bit 3 */
-#define  FSMC_PIO4_IOWAIT4_4                 0x00001000U        /*!<Bit 4 */
-#define  FSMC_PIO4_IOWAIT4_5                 0x00002000U        /*!<Bit 5 */
-#define  FSMC_PIO4_IOWAIT4_6                 0x00004000U        /*!<Bit 6 */
-#define  FSMC_PIO4_IOWAIT4_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FSMC_PIO4_IOHOLD4                   0x00FF0000U        /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
-#define  FSMC_PIO4_IOHOLD4_0                 0x00010000U        /*!<Bit 0 */
-#define  FSMC_PIO4_IOHOLD4_1                 0x00020000U        /*!<Bit 1 */
-#define  FSMC_PIO4_IOHOLD4_2                 0x00040000U        /*!<Bit 2 */
-#define  FSMC_PIO4_IOHOLD4_3                 0x00080000U        /*!<Bit 3 */
-#define  FSMC_PIO4_IOHOLD4_4                 0x00100000U        /*!<Bit 4 */
-#define  FSMC_PIO4_IOHOLD4_5                 0x00200000U        /*!<Bit 5 */
-#define  FSMC_PIO4_IOHOLD4_6                 0x00400000U        /*!<Bit 6 */
-#define  FSMC_PIO4_IOHOLD4_7                 0x00800000U        /*!<Bit 7 */
-
-#define  FSMC_PIO4_IOHIZ4                    0xFF000000U        /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
-#define  FSMC_PIO4_IOHIZ4_0                  0x01000000U        /*!<Bit 0 */
-#define  FSMC_PIO4_IOHIZ4_1                  0x02000000U        /*!<Bit 1 */
-#define  FSMC_PIO4_IOHIZ4_2                  0x04000000U        /*!<Bit 2 */
-#define  FSMC_PIO4_IOHIZ4_3                  0x08000000U        /*!<Bit 3 */
-#define  FSMC_PIO4_IOHIZ4_4                  0x10000000U        /*!<Bit 4 */
-#define  FSMC_PIO4_IOHIZ4_5                  0x20000000U        /*!<Bit 5 */
-#define  FSMC_PIO4_IOHIZ4_6                  0x40000000U        /*!<Bit 6 */
-#define  FSMC_PIO4_IOHIZ4_7                  0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FSMC_ECCR2 register  ******************/
-#define  FSMC_ECCR2_ECC2                     0xFFFFFFFFU        /*!<ECC result */
-
-/******************  Bit definition for FSMC_ECCR3 register  ******************/
-#define  FSMC_ECCR3_ECC3                     0xFFFFFFFFU        /*!<ECC result */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    0x00000003U
-#define GPIO_MODER_MODER0_0                  0x00000001U
-#define GPIO_MODER_MODER0_1                  0x00000002U
-
-#define GPIO_MODER_MODER1                    0x0000000CU
-#define GPIO_MODER_MODER1_0                  0x00000004U
-#define GPIO_MODER_MODER1_1                  0x00000008U
-
-#define GPIO_MODER_MODER2                    0x00000030U
-#define GPIO_MODER_MODER2_0                  0x00000010U
-#define GPIO_MODER_MODER2_1                  0x00000020U
-
-#define GPIO_MODER_MODER3                    0x000000C0U
-#define GPIO_MODER_MODER3_0                  0x00000040U
-#define GPIO_MODER_MODER3_1                  0x00000080U
-
-#define GPIO_MODER_MODER4                    0x00000300U
-#define GPIO_MODER_MODER4_0                  0x00000100U
-#define GPIO_MODER_MODER4_1                  0x00000200U
-
-#define GPIO_MODER_MODER5                    0x00000C00U
-#define GPIO_MODER_MODER5_0                  0x00000400U
-#define GPIO_MODER_MODER5_1                  0x00000800U
-
-#define GPIO_MODER_MODER6                    0x00003000U
-#define GPIO_MODER_MODER6_0                  0x00001000U
-#define GPIO_MODER_MODER6_1                  0x00002000U
-
-#define GPIO_MODER_MODER7                    0x0000C000U
-#define GPIO_MODER_MODER7_0                  0x00004000U
-#define GPIO_MODER_MODER7_1                  0x00008000U
-
-#define GPIO_MODER_MODER8                    0x00030000U
-#define GPIO_MODER_MODER8_0                  0x00010000U
-#define GPIO_MODER_MODER8_1                  0x00020000U
-
-#define GPIO_MODER_MODER9                    0x000C0000U
-#define GPIO_MODER_MODER9_0                  0x00040000U
-#define GPIO_MODER_MODER9_1                  0x00080000U
-
-#define GPIO_MODER_MODER10                   0x00300000U
-#define GPIO_MODER_MODER10_0                 0x00100000U
-#define GPIO_MODER_MODER10_1                 0x00200000U
-
-#define GPIO_MODER_MODER11                   0x00C00000U
-#define GPIO_MODER_MODER11_0                 0x00400000U
-#define GPIO_MODER_MODER11_1                 0x00800000U
-
-#define GPIO_MODER_MODER12                   0x03000000U
-#define GPIO_MODER_MODER12_0                 0x01000000U
-#define GPIO_MODER_MODER12_1                 0x02000000U
-
-#define GPIO_MODER_MODER13                   0x0C000000U
-#define GPIO_MODER_MODER13_0                 0x04000000U
-#define GPIO_MODER_MODER13_1                 0x08000000U
-
-#define GPIO_MODER_MODER14                   0x30000000U
-#define GPIO_MODER_MODER14_0                 0x10000000U
-#define GPIO_MODER_MODER14_1                 0x20000000U
-
-#define GPIO_MODER_MODER15                   0xC0000000U
-#define GPIO_MODER_MODER15_0                 0x40000000U
-#define GPIO_MODER_MODER15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     0x00000001U
-#define GPIO_OTYPER_OT_1                     0x00000002U
-#define GPIO_OTYPER_OT_2                     0x00000004U
-#define GPIO_OTYPER_OT_3                     0x00000008U
-#define GPIO_OTYPER_OT_4                     0x00000010U
-#define GPIO_OTYPER_OT_5                     0x00000020U
-#define GPIO_OTYPER_OT_6                     0x00000040U
-#define GPIO_OTYPER_OT_7                     0x00000080U
-#define GPIO_OTYPER_OT_8                     0x00000100U
-#define GPIO_OTYPER_OT_9                     0x00000200U
-#define GPIO_OTYPER_OT_10                    0x00000400U
-#define GPIO_OTYPER_OT_11                    0x00000800U
-#define GPIO_OTYPER_OT_12                    0x00001000U
-#define GPIO_OTYPER_OT_13                    0x00002000U
-#define GPIO_OTYPER_OT_14                    0x00004000U
-#define GPIO_OTYPER_OT_15                    0x00008000U
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
-#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
-#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
-
-#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
-#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
-#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
-
-#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
-#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
-#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
-
-#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
-#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
-#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
-
-#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
-#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
-#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
-
-#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
-#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
-#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
-
-#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
-#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
-#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
-
-#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
-#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
-#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
-
-#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
-#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
-#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
-
-#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
-#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
-#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
-
-#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
-#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
-#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
-
-#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
-#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
-#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
-
-#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
-#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
-#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
-
-#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
-#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
-#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
-
-#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
-#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
-#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
-
-#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
-#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
-#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    0x00000003U
-#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
-#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
-
-#define GPIO_PUPDR_PUPDR1                    0x0000000CU
-#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
-#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
-
-#define GPIO_PUPDR_PUPDR2                    0x00000030U
-#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
-#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
-
-#define GPIO_PUPDR_PUPDR3                    0x000000C0U
-#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
-#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
-
-#define GPIO_PUPDR_PUPDR4                    0x00000300U
-#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
-#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
-
-#define GPIO_PUPDR_PUPDR5                    0x00000C00U
-#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
-#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
-
-#define GPIO_PUPDR_PUPDR6                    0x00003000U
-#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
-#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
-
-#define GPIO_PUPDR_PUPDR7                    0x0000C000U
-#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
-#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
-
-#define GPIO_PUPDR_PUPDR8                    0x00030000U
-#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
-#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
-
-#define GPIO_PUPDR_PUPDR9                    0x000C0000U
-#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
-#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
-
-#define GPIO_PUPDR_PUPDR10                   0x00300000U
-#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
-#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
-
-#define GPIO_PUPDR_PUPDR11                   0x00C00000U
-#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
-#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
-
-#define GPIO_PUPDR_PUPDR12                   0x03000000U
-#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
-#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
-
-#define GPIO_PUPDR_PUPDR13                   0x0C000000U
-#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
-#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
-
-#define GPIO_PUPDR_PUPDR14                   0x30000000U
-#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
-#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
-
-#define GPIO_PUPDR_PUPDR15                   0xC0000000U
-#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
-#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       0x00000001U
-#define GPIO_IDR_IDR_1                       0x00000002U
-#define GPIO_IDR_IDR_2                       0x00000004U
-#define GPIO_IDR_IDR_3                       0x00000008U
-#define GPIO_IDR_IDR_4                       0x00000010U
-#define GPIO_IDR_IDR_5                       0x00000020U
-#define GPIO_IDR_IDR_6                       0x00000040U
-#define GPIO_IDR_IDR_7                       0x00000080U
-#define GPIO_IDR_IDR_8                       0x00000100U
-#define GPIO_IDR_IDR_9                       0x00000200U
-#define GPIO_IDR_IDR_10                      0x00000400U
-#define GPIO_IDR_IDR_11                      0x00000800U
-#define GPIO_IDR_IDR_12                      0x00001000U
-#define GPIO_IDR_IDR_13                      0x00002000U
-#define GPIO_IDR_IDR_14                      0x00004000U
-#define GPIO_IDR_IDR_15                      0x00008000U
-/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
-#define GPIO_OTYPER_IDR_0                    GPIO_IDR_IDR_0
-#define GPIO_OTYPER_IDR_1                    GPIO_IDR_IDR_1
-#define GPIO_OTYPER_IDR_2                    GPIO_IDR_IDR_2
-#define GPIO_OTYPER_IDR_3                    GPIO_IDR_IDR_3
-#define GPIO_OTYPER_IDR_4                    GPIO_IDR_IDR_4
-#define GPIO_OTYPER_IDR_5                    GPIO_IDR_IDR_5
-#define GPIO_OTYPER_IDR_6                    GPIO_IDR_IDR_6
-#define GPIO_OTYPER_IDR_7                    GPIO_IDR_IDR_7
-#define GPIO_OTYPER_IDR_8                    GPIO_IDR_IDR_8
-#define GPIO_OTYPER_IDR_9                    GPIO_IDR_IDR_9
-#define GPIO_OTYPER_IDR_10                   GPIO_IDR_IDR_10
-#define GPIO_OTYPER_IDR_11                   GPIO_IDR_IDR_11
-#define GPIO_OTYPER_IDR_12                   GPIO_IDR_IDR_12
-#define GPIO_OTYPER_IDR_13                   GPIO_IDR_IDR_13
-#define GPIO_OTYPER_IDR_14                   GPIO_IDR_IDR_14
-#define GPIO_OTYPER_IDR_15                   GPIO_IDR_IDR_15
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       0x00000001U
-#define GPIO_ODR_ODR_1                       0x00000002U
-#define GPIO_ODR_ODR_2                       0x00000004U
-#define GPIO_ODR_ODR_3                       0x00000008U
-#define GPIO_ODR_ODR_4                       0x00000010U
-#define GPIO_ODR_ODR_5                       0x00000020U
-#define GPIO_ODR_ODR_6                       0x00000040U
-#define GPIO_ODR_ODR_7                       0x00000080U
-#define GPIO_ODR_ODR_8                       0x00000100U
-#define GPIO_ODR_ODR_9                       0x00000200U
-#define GPIO_ODR_ODR_10                      0x00000400U
-#define GPIO_ODR_ODR_11                      0x00000800U
-#define GPIO_ODR_ODR_12                      0x00001000U
-#define GPIO_ODR_ODR_13                      0x00002000U
-#define GPIO_ODR_ODR_14                      0x00004000U
-#define GPIO_ODR_ODR_15                      0x00008000U
-/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
-#define GPIO_OTYPER_ODR_0                    GPIO_ODR_ODR_0
-#define GPIO_OTYPER_ODR_1                    GPIO_ODR_ODR_1
-#define GPIO_OTYPER_ODR_2                    GPIO_ODR_ODR_2
-#define GPIO_OTYPER_ODR_3                    GPIO_ODR_ODR_3
-#define GPIO_OTYPER_ODR_4                    GPIO_ODR_ODR_4
-#define GPIO_OTYPER_ODR_5                    GPIO_ODR_ODR_5
-#define GPIO_OTYPER_ODR_6                    GPIO_ODR_ODR_6
-#define GPIO_OTYPER_ODR_7                    GPIO_ODR_ODR_7
-#define GPIO_OTYPER_ODR_8                    GPIO_ODR_ODR_8
-#define GPIO_OTYPER_ODR_9                    GPIO_ODR_ODR_9
-#define GPIO_OTYPER_ODR_10                   GPIO_ODR_ODR_10
-#define GPIO_OTYPER_ODR_11                   GPIO_ODR_ODR_11
-#define GPIO_OTYPER_ODR_12                   GPIO_ODR_ODR_12
-#define GPIO_OTYPER_ODR_13                   GPIO_ODR_ODR_13
-#define GPIO_OTYPER_ODR_14                   GPIO_ODR_ODR_14
-#define GPIO_OTYPER_ODR_15                   GPIO_ODR_ODR_15
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       0x00000001U
-#define GPIO_BSRR_BS_1                       0x00000002U
-#define GPIO_BSRR_BS_2                       0x00000004U
-#define GPIO_BSRR_BS_3                       0x00000008U
-#define GPIO_BSRR_BS_4                       0x00000010U
-#define GPIO_BSRR_BS_5                       0x00000020U
-#define GPIO_BSRR_BS_6                       0x00000040U
-#define GPIO_BSRR_BS_7                       0x00000080U
-#define GPIO_BSRR_BS_8                       0x00000100U
-#define GPIO_BSRR_BS_9                       0x00000200U
-#define GPIO_BSRR_BS_10                      0x00000400U
-#define GPIO_BSRR_BS_11                      0x00000800U
-#define GPIO_BSRR_BS_12                      0x00001000U
-#define GPIO_BSRR_BS_13                      0x00002000U
-#define GPIO_BSRR_BS_14                      0x00004000U
-#define GPIO_BSRR_BS_15                      0x00008000U
-#define GPIO_BSRR_BR_0                       0x00010000U
-#define GPIO_BSRR_BR_1                       0x00020000U
-#define GPIO_BSRR_BR_2                       0x00040000U
-#define GPIO_BSRR_BR_3                       0x00080000U
-#define GPIO_BSRR_BR_4                       0x00100000U
-#define GPIO_BSRR_BR_5                       0x00200000U
-#define GPIO_BSRR_BR_6                       0x00400000U
-#define GPIO_BSRR_BR_7                       0x00800000U
-#define GPIO_BSRR_BR_8                       0x01000000U
-#define GPIO_BSRR_BR_9                       0x02000000U
-#define GPIO_BSRR_BR_10                      0x04000000U
-#define GPIO_BSRR_BR_11                      0x08000000U
-#define GPIO_BSRR_BR_12                      0x10000000U
-#define GPIO_BSRR_BR_13                      0x20000000U
-#define GPIO_BSRR_BR_14                      0x40000000U
-#define GPIO_BSRR_BR_15                      0x80000000U
-
-/****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0                       0x00000001U
-#define GPIO_LCKR_LCK1                       0x00000002U
-#define GPIO_LCKR_LCK2                       0x00000004U
-#define GPIO_LCKR_LCK3                       0x00000008U
-#define GPIO_LCKR_LCK4                       0x00000010U
-#define GPIO_LCKR_LCK5                       0x00000020U
-#define GPIO_LCKR_LCK6                       0x00000040U
-#define GPIO_LCKR_LCK7                       0x00000080U
-#define GPIO_LCKR_LCK8                       0x00000100U
-#define GPIO_LCKR_LCK9                       0x00000200U
-#define GPIO_LCKR_LCK10                      0x00000400U
-#define GPIO_LCKR_LCK11                      0x00000800U
-#define GPIO_LCKR_LCK12                      0x00001000U
-#define GPIO_LCKR_LCK13                      0x00002000U
-#define GPIO_LCKR_LCK14                      0x00004000U
-#define GPIO_LCKR_LCK15                      0x00008000U
-#define GPIO_LCKR_LCKK                       0x00010000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    HASH                                    */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for HASH_CR register  ********************/
-#define HASH_CR_INIT                         0x00000004U
-#define HASH_CR_DMAE                         0x00000008U
-#define HASH_CR_DATATYPE                     0x00000030U
-#define HASH_CR_DATATYPE_0                   0x00000010U
-#define HASH_CR_DATATYPE_1                   0x00000020U
-#define HASH_CR_MODE                         0x00000040U
-#define HASH_CR_ALGO                         0x00040080U
-#define HASH_CR_ALGO_0                       0x00000080U
-#define HASH_CR_ALGO_1                       0x00040000U
-#define HASH_CR_NBW                          0x00000F00U
-#define HASH_CR_NBW_0                        0x00000100U
-#define HASH_CR_NBW_1                        0x00000200U
-#define HASH_CR_NBW_2                        0x00000400U
-#define HASH_CR_NBW_3                        0x00000800U
-#define HASH_CR_DINNE                        0x00001000U
-#define HASH_CR_MDMAT                        0x00002000U
-#define HASH_CR_LKEY                         0x00010000U
-
-/******************  Bits definition for HASH_STR register  *******************/
-#define HASH_STR_NBLW                        0x0000001FU
-#define HASH_STR_NBLW_0                      0x00000001U
-#define HASH_STR_NBLW_1                      0x00000002U
-#define HASH_STR_NBLW_2                      0x00000004U
-#define HASH_STR_NBLW_3                      0x00000008U
-#define HASH_STR_NBLW_4                      0x00000010U
-#define HASH_STR_DCAL                        0x00000100U
-/* Aliases for HASH_STR register */
-#define HASH_STR_NBW                         HASH_STR_NBLW
-#define HASH_STR_NBW_0                       HASH_STR_NBLW_0
-#define HASH_STR_NBW_1                       HASH_STR_NBLW_1
-#define HASH_STR_NBW_2                       HASH_STR_NBLW_2
-#define HASH_STR_NBW_3                       HASH_STR_NBLW_3
-#define HASH_STR_NBW_4                       HASH_STR_NBLW_4
-
-/******************  Bits definition for HASH_IMR register  *******************/
-#define HASH_IMR_DINIE                       0x00000001U
-#define HASH_IMR_DCIE                        0x00000002U
-/* Aliases for HASH_IMR register */
-#define HASH_IMR_DINIM                       HASH_IMR_DINIE
-#define HASH_IMR_DCIM                        HASH_IMR_DCIE
-
-/******************  Bits definition for HASH_SR register  ********************/
-#define HASH_SR_DINIS                        0x00000001U
-#define HASH_SR_DCIS                         0x00000002U
-#define HASH_SR_DMAS                         0x00000004U
-#define HASH_SR_BUSY                         0x00000008U
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Inter-integrated Circuit Interface                    */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          0x00000001U     /*!<Peripheral Enable                             */
-#define  I2C_CR1_SMBUS                       0x00000002U     /*!<SMBus Mode                                    */
-#define  I2C_CR1_SMBTYPE                     0x00000008U     /*!<SMBus Type                                    */
-#define  I2C_CR1_ENARP                       0x00000010U     /*!<ARP Enable                                    */
-#define  I2C_CR1_ENPEC                       0x00000020U     /*!<PEC Enable                                    */
-#define  I2C_CR1_ENGC                        0x00000040U     /*!<General Call Enable                           */
-#define  I2C_CR1_NOSTRETCH                   0x00000080U     /*!<Clock Stretching Disable (Slave mode)  */
-#define  I2C_CR1_START                       0x00000100U     /*!<Start Generation                              */
-#define  I2C_CR1_STOP                        0x00000200U     /*!<Stop Generation                               */
-#define  I2C_CR1_ACK                         0x00000400U     /*!<Acknowledge Enable                            */
-#define  I2C_CR1_POS                         0x00000800U     /*!<Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         0x00001000U     /*!<Packet Error Checking                         */
-#define  I2C_CR1_ALERT                       0x00002000U     /*!<SMBus Alert                                   */
-#define  I2C_CR1_SWRST                       0x00008000U     /*!<Software Reset                                */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        0x0000003FU     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
-#define  I2C_CR2_FREQ_0                      0x00000001U     /*!<Bit 0 */
-#define  I2C_CR2_FREQ_1                      0x00000002U     /*!<Bit 1 */
-#define  I2C_CR2_FREQ_2                      0x00000004U     /*!<Bit 2 */
-#define  I2C_CR2_FREQ_3                      0x00000008U     /*!<Bit 3 */
-#define  I2C_CR2_FREQ_4                      0x00000010U     /*!<Bit 4 */
-#define  I2C_CR2_FREQ_5                      0x00000020U     /*!<Bit 5 */
-
-#define  I2C_CR2_ITERREN                     0x00000100U     /*!<Error Interrupt Enable  */
-#define  I2C_CR2_ITEVTEN                     0x00000200U     /*!<Event Interrupt Enable  */
-#define  I2C_CR2_ITBUFEN                     0x00000400U     /*!<Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       0x00000800U     /*!<DMA Requests Enable     */
-#define  I2C_CR2_LAST                        0x00001000U     /*!<DMA Last Transfer       */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     0x000000FEU     /*!<Interface Address */
-#define  I2C_OAR1_ADD8_9                     0x00000300U     /*!<Interface Address */
-
-#define  I2C_OAR1_ADD0                       0x00000001U     /*!<Bit 0 */
-#define  I2C_OAR1_ADD1                       0x00000002U     /*!<Bit 1 */
-#define  I2C_OAR1_ADD2                       0x00000004U     /*!<Bit 2 */
-#define  I2C_OAR1_ADD3                       0x00000008U     /*!<Bit 3 */
-#define  I2C_OAR1_ADD4                       0x00000010U     /*!<Bit 4 */
-#define  I2C_OAR1_ADD5                       0x00000020U     /*!<Bit 5 */
-#define  I2C_OAR1_ADD6                       0x00000040U     /*!<Bit 6 */
-#define  I2C_OAR1_ADD7                       0x00000080U     /*!<Bit 7 */
-#define  I2C_OAR1_ADD8                       0x00000100U     /*!<Bit 8 */
-#define  I2C_OAR1_ADD9                       0x00000200U     /*!<Bit 9 */
-
-#define  I2C_OAR1_ADDMODE                    0x00008000U     /*!<Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     0x00000001U        /*!<Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       0x000000FEU        /*!<Interface address           */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           0x000000FFU        /*!<8-bit Data Register         */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          0x00000001U     /*!<Start Bit (Master mode)                  */
-#define  I2C_SR1_ADDR                        0x00000002U     /*!<Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         0x00000004U     /*!<Byte Transfer Finished                          */
-#define  I2C_SR1_ADD10                       0x00000008U     /*!<10-bit header sent (Master mode)         */
-#define  I2C_SR1_STOPF                       0x00000010U     /*!<Stop detection (Slave mode)              */
-#define  I2C_SR1_RXNE                        0x00000040U     /*!<Data Register not Empty (receivers)      */
-#define  I2C_SR1_TXE                         0x00000080U     /*!<Data Register Empty (transmitters)       */
-#define  I2C_SR1_BERR                        0x00000100U     /*!<Bus Error                                       */
-#define  I2C_SR1_ARLO                        0x00000200U     /*!<Arbitration Lost (master mode)           */
-#define  I2C_SR1_AF                          0x00000400U     /*!<Acknowledge Failure                             */
-#define  I2C_SR1_OVR                         0x00000800U     /*!<Overrun/Underrun                                */
-#define  I2C_SR1_PECERR                      0x00001000U     /*!<PEC Error in reception                          */
-#define  I2C_SR1_TIMEOUT                     0x00004000U     /*!<Timeout or Tlow Error                           */
-#define  I2C_SR1_SMBALERT                    0x00008000U     /*!<SMBus Alert                                     */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         0x00000001U     /*!<Master/Slave                              */
-#define  I2C_SR2_BUSY                        0x00000002U     /*!<Bus Busy                                  */
-#define  I2C_SR2_TRA                         0x00000004U     /*!<Transmitter/Receiver                      */
-#define  I2C_SR2_GENCALL                     0x00000010U     /*!<General Call Address (Slave mode)  */
-#define  I2C_SR2_SMBDEFAULT                  0x00000020U     /*!<SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     0x00000040U     /*!<SMBus Host Header (Slave mode)     */
-#define  I2C_SR2_DUALF                       0x00000080U     /*!<Dual Flag (Slave mode)             */
-#define  I2C_SR2_PEC                         0x0000FF00U     /*!<Packet Error Checking Register            */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         0x00000FFFU     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        0x00004000U     /*!<Fast Mode Duty Cycle                                       */
-#define  I2C_CCR_FS                          0x00008000U     /*!<I2C Master Mode Selection                                  */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     0x0000003FU     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************  Bit definition for I2C_FLTR register  *******************/
-#define  I2C_FLTR_DNF                        0x0000000FU     /*!<Digital Noise Filter */
-#define  I2C_FLTR_ANOFF                      0x00000010U     /*!<Analog Noise Filter OFF */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Independent WATCHDOG                             */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         0x01U               /*!<Watchdog prescaler value update      */
-#define  IWDG_SR_RVU                         0x02U               /*!<Watchdog counter reload value update */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                             Power Control                                  */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
-#define  PWR_CR_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
-#define  PWR_CR_CWUF                         0x00000004U     /*!< Clear Wakeup Flag                   */
-#define  PWR_CR_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
-#define  PWR_CR_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
-
-#define  PWR_CR_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        0x00000020U     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        0x00000040U     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        0x00000080U     /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
-
-#define  PWR_CR_DBP                          0x00000100U     /*!< Disable Backup Domain write protection               */
-#define  PWR_CR_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                        */
-#define  PWR_CR_VOS                          0x00004000U     /*!< VOS bit (Regulator voltage scaling output selection) */
-
-/* Legacy define */
-#define  PWR_CR_PMODE                        PWR_CR_VOS
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         0x00000001U     /*!< Wakeup Flag                                      */
-#define  PWR_CSR_SBF                         0x00000002U     /*!< Standby Flag                                     */
-#define  PWR_CSR_PVDO                        0x00000004U     /*!< PVD Output                                       */
-#define  PWR_CSR_BRR                         0x00000008U     /*!< Backup regulator ready                           */
-#define  PWR_CSR_EWUP                        0x00000100U     /*!< Enable WKUP pin                                  */
-#define  PWR_CSR_BRE                         0x00000200U     /*!< Backup regulator enable                          */
-#define  PWR_CSR_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
-
-/* Legacy define */
-#define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        0x00000001U
-#define  RCC_CR_HSIRDY                       0x00000002U
-
-#define  RCC_CR_HSITRIM                      0x000000F8U
-#define  RCC_CR_HSITRIM_0                    0x00000008U/*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    0x00000010U/*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    0x00000020U/*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    0x00000040U/*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    0x00000080U/*!<Bit 4 */
-
-#define  RCC_CR_HSICAL                       0x0000FF00U
-#define  RCC_CR_HSICAL_0                     0x00000100U/*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     0x00000200U/*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     0x00000400U/*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     0x00000800U/*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     0x00001000U/*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     0x00002000U/*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     0x00004000U/*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     0x00008000U/*!<Bit 7 */
-
-#define  RCC_CR_HSEON                        0x00010000U
-#define  RCC_CR_HSERDY                       0x00020000U
-#define  RCC_CR_HSEBYP                       0x00040000U
-#define  RCC_CR_CSSON                        0x00080000U
-#define  RCC_CR_PLLON                        0x01000000U
-#define  RCC_CR_PLLRDY                       0x02000000U
-#define  RCC_CR_PLLI2SON                     0x04000000U
-#define  RCC_CR_PLLI2SRDY                    0x08000000U
-
-/********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    0x0000003FU
-#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
-#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
-#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
-#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
-#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
-#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
-
-#define  RCC_PLLCFGR_PLLN                     0x00007FC0U
-#define  RCC_PLLCFGR_PLLN_0                   0x00000040U
-#define  RCC_PLLCFGR_PLLN_1                   0x00000080U
-#define  RCC_PLLCFGR_PLLN_2                   0x00000100U
-#define  RCC_PLLCFGR_PLLN_3                   0x00000200U
-#define  RCC_PLLCFGR_PLLN_4                   0x00000400U
-#define  RCC_PLLCFGR_PLLN_5                   0x00000800U
-#define  RCC_PLLCFGR_PLLN_6                   0x00001000U
-#define  RCC_PLLCFGR_PLLN_7                   0x00002000U
-#define  RCC_PLLCFGR_PLLN_8                   0x00004000U
-
-#define  RCC_PLLCFGR_PLLP                    0x00030000U
-#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
-#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
-
-#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
-
-#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
-#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
-#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
-#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
-#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-/*!< SW configuration */
-#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
-
-#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
-
-#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
-
-#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
-
-/*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     0x001F0000U
-#define  RCC_CFGR_RTCPRE_0                   0x00010000U
-#define  RCC_CFGR_RTCPRE_1                   0x00020000U
-#define  RCC_CFGR_RTCPRE_2                   0x00040000U
-#define  RCC_CFGR_RTCPRE_3                   0x00080000U
-#define  RCC_CFGR_RTCPRE_4                   0x00100000U
-
-/*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       0x00600000U
-#define  RCC_CFGR_MCO1_0                     0x00200000U
-#define  RCC_CFGR_MCO1_1                     0x00400000U
-
-#define  RCC_CFGR_I2SSRC                     0x00800000U
-
-#define  RCC_CFGR_MCO1PRE                    0x07000000U
-#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
-#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
-#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
-
-#define  RCC_CFGR_MCO2PRE                    0x38000000U
-#define  RCC_CFGR_MCO2PRE_0                  0x08000000U
-#define  RCC_CFGR_MCO2PRE_1                  0x10000000U
-#define  RCC_CFGR_MCO2PRE_2                  0x20000000U
-
-#define  RCC_CFGR_MCO2                       0xC0000000U
-#define  RCC_CFGR_MCO2_0                     0x40000000U
-#define  RCC_CFGR_MCO2_1                     0x80000000U
-
-/********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     0x00000001U
-#define  RCC_CIR_LSERDYF                     0x00000002U
-#define  RCC_CIR_HSIRDYF                     0x00000004U
-#define  RCC_CIR_HSERDYF                     0x00000008U
-#define  RCC_CIR_PLLRDYF                     0x00000010U
-#define  RCC_CIR_PLLI2SRDYF                  0x00000020U
-
-#define  RCC_CIR_CSSF                        0x00000080U
-#define  RCC_CIR_LSIRDYIE                    0x00000100U
-#define  RCC_CIR_LSERDYIE                    0x00000200U
-#define  RCC_CIR_HSIRDYIE                    0x00000400U
-#define  RCC_CIR_HSERDYIE                    0x00000800U
-#define  RCC_CIR_PLLRDYIE                    0x00001000U
-#define  RCC_CIR_PLLI2SRDYIE                 0x00002000U
-
-#define  RCC_CIR_LSIRDYC                     0x00010000U
-#define  RCC_CIR_LSERDYC                     0x00020000U
-#define  RCC_CIR_HSIRDYC                     0x00040000U
-#define  RCC_CIR_HSERDYC                     0x00080000U
-#define  RCC_CIR_PLLRDYC                     0x00100000U
-#define  RCC_CIR_PLLI2SRDYC                  0x00200000U
-
-#define  RCC_CIR_CSSC                        0x00800000U
-
-/********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
-#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
-#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
-#define  RCC_AHB1RSTR_GPIODRST               0x00000008U
-#define  RCC_AHB1RSTR_GPIOERST               0x00000010U
-#define  RCC_AHB1RSTR_GPIOFRST               0x00000020U
-#define  RCC_AHB1RSTR_GPIOGRST               0x00000040U
-#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
-#define  RCC_AHB1RSTR_GPIOIRST               0x00000100U
-#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
-#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
-#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
-#define  RCC_AHB1RSTR_ETHMACRST              0x02000000U
-#define  RCC_AHB1RSTR_OTGHRST                0x20000000U
-
-/********************  Bit definition for RCC_AHB2RSTR register  **************/
-#define  RCC_AHB2RSTR_DCMIRST                0x00000001U
-#define  RCC_AHB2RSTR_CRYPRST                0x00000010U
-#define  RCC_AHB2RSTR_HASHRST                0x00000020U
- /* maintained for legacy purpose */
- #define  RCC_AHB2RSTR_HSAHRST                RCC_AHB2RSTR_HASHRST
-#define  RCC_AHB2RSTR_RNGRST                 0x00000040U
-#define  RCC_AHB2RSTR_OTGFSRST               0x00000080U
-
-/********************  Bit definition for RCC_AHB3RSTR register  **************/
-
-#define  RCC_AHB3RSTR_FSMCRST                0x00000001U
-
-/********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM2RST                0x00000001U
-#define  RCC_APB1RSTR_TIM3RST                0x00000002U
-#define  RCC_APB1RSTR_TIM4RST                0x00000004U
-#define  RCC_APB1RSTR_TIM5RST                0x00000008U
-#define  RCC_APB1RSTR_TIM6RST                0x00000010U
-#define  RCC_APB1RSTR_TIM7RST                0x00000020U
-#define  RCC_APB1RSTR_TIM12RST               0x00000040U
-#define  RCC_APB1RSTR_TIM13RST               0x00000080U
-#define  RCC_APB1RSTR_TIM14RST               0x00000100U
-#define  RCC_APB1RSTR_WWDGRST                0x00000800U
-#define  RCC_APB1RSTR_SPI2RST                0x00004000U
-#define  RCC_APB1RSTR_SPI3RST                0x00008000U
-#define  RCC_APB1RSTR_USART2RST              0x00020000U
-#define  RCC_APB1RSTR_USART3RST              0x00040000U
-#define  RCC_APB1RSTR_UART4RST               0x00080000U
-#define  RCC_APB1RSTR_UART5RST               0x00100000U
-#define  RCC_APB1RSTR_I2C1RST                0x00200000U
-#define  RCC_APB1RSTR_I2C2RST                0x00400000U
-#define  RCC_APB1RSTR_I2C3RST                0x00800000U
-#define  RCC_APB1RSTR_CAN1RST                0x02000000U
-#define  RCC_APB1RSTR_CAN2RST                0x04000000U
-#define  RCC_APB1RSTR_PWRRST                 0x10000000U
-#define  RCC_APB1RSTR_DACRST                 0x20000000U
-
-/********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                0x00000001U
-#define  RCC_APB2RSTR_TIM8RST                0x00000002U
-#define  RCC_APB2RSTR_USART1RST              0x00000010U
-#define  RCC_APB2RSTR_USART6RST              0x00000020U
-#define  RCC_APB2RSTR_ADCRST                 0x00000100U
-#define  RCC_APB2RSTR_SDIORST                0x00000800U
-#define  RCC_APB2RSTR_SPI1RST                0x00001000U
-#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
-#define  RCC_APB2RSTR_TIM9RST                0x00010000U
-#define  RCC_APB2RSTR_TIM10RST               0x00020000U
-#define  RCC_APB2RSTR_TIM11RST               0x00040000U
-
-/* Old SPI1RST bit definition, maintained for legacy purpose */
-#define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
-
-/********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
-#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
-#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
-#define  RCC_AHB1ENR_GPIODEN                 0x00000008U
-#define  RCC_AHB1ENR_GPIOEEN                 0x00000010U
-#define  RCC_AHB1ENR_GPIOFEN                 0x00000020U
-#define  RCC_AHB1ENR_GPIOGEN                 0x00000040U
-#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
-#define  RCC_AHB1ENR_GPIOIEN                 0x00000100U
-#define  RCC_AHB1ENR_CRCEN                   0x00001000U
-#define  RCC_AHB1ENR_BKPSRAMEN               0x00040000U
-#define  RCC_AHB1ENR_CCMDATARAMEN            0x00100000U
-#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
-#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
-
-#define  RCC_AHB1ENR_ETHMACEN                0x02000000U
-#define  RCC_AHB1ENR_ETHMACTXEN              0x04000000U
-#define  RCC_AHB1ENR_ETHMACRXEN              0x08000000U
-#define  RCC_AHB1ENR_ETHMACPTPEN             0x10000000U
-#define  RCC_AHB1ENR_OTGHSEN                 0x20000000U
-#define  RCC_AHB1ENR_OTGHSULPIEN             0x40000000U
-
-/********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define  RCC_AHB2ENR_DCMIEN                  0x00000001U
-#define  RCC_AHB2ENR_CRYPEN                  0x00000010U
-#define  RCC_AHB2ENR_HASHEN                  0x00000020U
-#define  RCC_AHB2ENR_RNGEN                   0x00000040U
-#define  RCC_AHB2ENR_OTGFSEN                 0x00000080U
-
-/********************  Bit definition for RCC_AHB3ENR register  ***************/
-
-#define  RCC_AHB3ENR_FSMCEN                  0x00000001U
-
-/********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM2EN                  0x00000001U
-#define  RCC_APB1ENR_TIM3EN                  0x00000002U
-#define  RCC_APB1ENR_TIM4EN                  0x00000004U
-#define  RCC_APB1ENR_TIM5EN                  0x00000008U
-#define  RCC_APB1ENR_TIM6EN                  0x00000010U
-#define  RCC_APB1ENR_TIM7EN                  0x00000020U
-#define  RCC_APB1ENR_TIM12EN                 0x00000040U
-#define  RCC_APB1ENR_TIM13EN                 0x00000080U
-#define  RCC_APB1ENR_TIM14EN                 0x00000100U
-#define  RCC_APB1ENR_WWDGEN                  0x00000800U
-#define  RCC_APB1ENR_SPI2EN                  0x00004000U
-#define  RCC_APB1ENR_SPI3EN                  0x00008000U
-#define  RCC_APB1ENR_USART2EN                0x00020000U
-#define  RCC_APB1ENR_USART3EN                0x00040000U
-#define  RCC_APB1ENR_UART4EN                 0x00080000U
-#define  RCC_APB1ENR_UART5EN                 0x00100000U
-#define  RCC_APB1ENR_I2C1EN                  0x00200000U
-#define  RCC_APB1ENR_I2C2EN                  0x00400000U
-#define  RCC_APB1ENR_I2C3EN                  0x00800000U
-#define  RCC_APB1ENR_CAN1EN                  0x02000000U
-#define  RCC_APB1ENR_CAN2EN                  0x04000000U
-#define  RCC_APB1ENR_PWREN                   0x10000000U
-#define  RCC_APB1ENR_DACEN                   0x20000000U
-
-/********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  0x00000001U
-#define  RCC_APB2ENR_TIM8EN                  0x00000002U
-#define  RCC_APB2ENR_USART1EN                0x00000010U
-#define  RCC_APB2ENR_USART6EN                0x00000020U
-#define  RCC_APB2ENR_ADC1EN                  0x00000100U
-#define  RCC_APB2ENR_ADC2EN                  0x00000200U
-#define  RCC_APB2ENR_ADC3EN                  0x00000400U
-#define  RCC_APB2ENR_SDIOEN                  0x00000800U
-#define  RCC_APB2ENR_SPI1EN                  0x00001000U
-#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
-#define  RCC_APB2ENR_TIM9EN                  0x00010000U
-#define  RCC_APB2ENR_TIM10EN                 0x00020000U
-#define  RCC_APB2ENR_TIM11EN                 0x00040000U
-#define  RCC_APB2ENR_SPI5EN                  0x00100000U
-#define  RCC_APB2ENR_SPI6EN                  0x00200000U
-
-/********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
-#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
-#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
-#define  RCC_AHB1LPENR_GPIODLPEN             0x00000008U
-#define  RCC_AHB1LPENR_GPIOELPEN             0x00000010U
-#define  RCC_AHB1LPENR_GPIOFLPEN             0x00000020U
-#define  RCC_AHB1LPENR_GPIOGLPEN             0x00000040U
-#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
-#define  RCC_AHB1LPENR_GPIOILPEN             0x00000100U
-#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
-#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
-#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
-#define  RCC_AHB1LPENR_SRAM2LPEN             0x00020000U
-#define  RCC_AHB1LPENR_BKPSRAMLPEN           0x00040000U
-#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
-#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
-#define  RCC_AHB1LPENR_ETHMACLPEN            0x02000000U
-#define  RCC_AHB1LPENR_ETHMACTXLPEN          0x04000000U
-#define  RCC_AHB1LPENR_ETHMACRXLPEN          0x08000000U
-#define  RCC_AHB1LPENR_ETHMACPTPLPEN         0x10000000U
-#define  RCC_AHB1LPENR_OTGHSLPEN             0x20000000U
-#define  RCC_AHB1LPENR_OTGHSULPILPEN         0x40000000U
-
-/********************  Bit definition for RCC_AHB2LPENR register  *************/
-#define  RCC_AHB2LPENR_DCMILPEN              0x00000001U
-#define  RCC_AHB2LPENR_CRYPLPEN              0x00000010U
-#define  RCC_AHB2LPENR_HASHLPEN              0x00000020U
-#define  RCC_AHB2LPENR_RNGLPEN               0x00000040U
-#define  RCC_AHB2LPENR_OTGFSLPEN             0x00000080U
-
-/********************  Bit definition for RCC_AHB3LPENR register  *************/
-
-#define  RCC_AHB3LPENR_FSMCLPEN              0x00000001U
-
-/********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM2LPEN              0x00000001U
-#define  RCC_APB1LPENR_TIM3LPEN              0x00000002U
-#define  RCC_APB1LPENR_TIM4LPEN              0x00000004U
-#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
-#define  RCC_APB1LPENR_TIM6LPEN              0x00000010U
-#define  RCC_APB1LPENR_TIM7LPEN              0x00000020U
-#define  RCC_APB1LPENR_TIM12LPEN             0x00000040U
-#define  RCC_APB1LPENR_TIM13LPEN             0x00000080U
-#define  RCC_APB1LPENR_TIM14LPEN             0x00000100U
-#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
-#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U
-#define  RCC_APB1LPENR_SPI3LPEN              0x00008000U
-#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
-#define  RCC_APB1LPENR_USART3LPEN            0x00040000U
-#define  RCC_APB1LPENR_UART4LPEN             0x00080000U
-#define  RCC_APB1LPENR_UART5LPEN             0x00100000U
-#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
-#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
-#define  RCC_APB1LPENR_I2C3LPEN              0x00800000U
-#define  RCC_APB1LPENR_CAN1LPEN              0x02000000U
-#define  RCC_APB1LPENR_CAN2LPEN              0x04000000U
-#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
-#define  RCC_APB1LPENR_DACLPEN               0x20000000U
-
-/********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
-#define  RCC_APB2LPENR_TIM8LPEN              0x00000002U
-#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
-#define  RCC_APB2LPENR_USART6LPEN            0x00000020U
-#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
-#define  RCC_APB2LPENR_ADC2LPEN              0x00000200U
-#define  RCC_APB2LPENR_ADC3LPEN              0x00000400U
-#define  RCC_APB2LPENR_SDIOLPEN              0x00000800U
-#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
-#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
-#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
-#define  RCC_APB2LPENR_TIM10LPEN             0x00020000U
-#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
-
-/********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      0x00000001U
-#define  RCC_BDCR_LSERDY                     0x00000002U
-#define  RCC_BDCR_LSEBYP                     0x00000004U
-
-#define  RCC_BDCR_RTCSEL                    0x00000300U
-#define  RCC_BDCR_RTCSEL_0                  0x00000100U
-#define  RCC_BDCR_RTCSEL_1                  0x00000200U
-
-#define  RCC_BDCR_RTCEN                      0x00008000U
-#define  RCC_BDCR_BDRST                      0x00010000U
-
-/********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       0x00000001U
-#define  RCC_CSR_LSIRDY                      0x00000002U
-#define  RCC_CSR_RMVF                        0x01000000U
-#define  RCC_CSR_BORRSTF                     0x02000000U
-#define  RCC_CSR_PADRSTF                     0x04000000U
-#define  RCC_CSR_PORRSTF                     0x08000000U
-#define  RCC_CSR_SFTRSTF                     0x10000000U
-#define  RCC_CSR_WDGRSTF                     0x20000000U
-#define  RCC_CSR_WWDGRSTF                    0x40000000U
-#define  RCC_CSR_LPWRRSTF                    0x80000000U
-
-/********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    0x00001FFFU
-#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
-#define  RCC_SSCGR_SPREADSEL                 0x40000000U
-#define  RCC_SSCGR_SSCGEN                    0x80000000U
-
-/********************  Bit definition for RCC_PLLI2SCFGR register  ************/
-#define  RCC_PLLI2SCFGR_PLLI2SN              0x00007FC0U
-#define  RCC_PLLI2SCFGR_PLLI2SN_0            0x00000040U
-#define  RCC_PLLI2SCFGR_PLLI2SN_1            0x00000080U
-#define  RCC_PLLI2SCFGR_PLLI2SN_2            0x00000100U
-#define  RCC_PLLI2SCFGR_PLLI2SN_3            0x00000200U
-#define  RCC_PLLI2SCFGR_PLLI2SN_4            0x00000400U
-#define  RCC_PLLI2SCFGR_PLLI2SN_5            0x00000800U
-#define  RCC_PLLI2SCFGR_PLLI2SN_6            0x00001000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_7            0x00002000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_8            0x00004000U
-
-#define  RCC_PLLI2SCFGR_PLLI2SR              0x70000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_0            0x10000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_1            0x20000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_2            0x40000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    RNG                                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN                         0x00000004U
-#define RNG_CR_IE                            0x00000008U
-
-/********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY                          0x00000001U
-#define RNG_SR_CECS                          0x00000002U
-#define RNG_SR_SECS                          0x00000004U
-#define RNG_SR_CEIS                          0x00000020U
-#define RNG_SR_SEIS                          0x00000040U
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            0x00400000U
-#define RTC_TR_HT                            0x00300000U
-#define RTC_TR_HT_0                          0x00100000U
-#define RTC_TR_HT_1                          0x00200000U
-#define RTC_TR_HU                            0x000F0000U
-#define RTC_TR_HU_0                          0x00010000U
-#define RTC_TR_HU_1                          0x00020000U
-#define RTC_TR_HU_2                          0x00040000U
-#define RTC_TR_HU_3                          0x00080000U
-#define RTC_TR_MNT                           0x00007000U
-#define RTC_TR_MNT_0                         0x00001000U
-#define RTC_TR_MNT_1                         0x00002000U
-#define RTC_TR_MNT_2                         0x00004000U
-#define RTC_TR_MNU                           0x00000F00U
-#define RTC_TR_MNU_0                         0x00000100U
-#define RTC_TR_MNU_1                         0x00000200U
-#define RTC_TR_MNU_2                         0x00000400U
-#define RTC_TR_MNU_3                         0x00000800U
-#define RTC_TR_ST                            0x00000070U
-#define RTC_TR_ST_0                          0x00000010U
-#define RTC_TR_ST_1                          0x00000020U
-#define RTC_TR_ST_2                          0x00000040U
-#define RTC_TR_SU                            0x0000000FU
-#define RTC_TR_SU_0                          0x00000001U
-#define RTC_TR_SU_1                          0x00000002U
-#define RTC_TR_SU_2                          0x00000004U
-#define RTC_TR_SU_3                          0x00000008U
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            0x00F00000U
-#define RTC_DR_YT_0                          0x00100000U
-#define RTC_DR_YT_1                          0x00200000U
-#define RTC_DR_YT_2                          0x00400000U
-#define RTC_DR_YT_3                          0x00800000U
-#define RTC_DR_YU                            0x000F0000U
-#define RTC_DR_YU_0                          0x00010000U
-#define RTC_DR_YU_1                          0x00020000U
-#define RTC_DR_YU_2                          0x00040000U
-#define RTC_DR_YU_3                          0x00080000U
-#define RTC_DR_WDU                           0x0000E000U
-#define RTC_DR_WDU_0                         0x00002000U
-#define RTC_DR_WDU_1                         0x00004000U
-#define RTC_DR_WDU_2                         0x00008000U
-#define RTC_DR_MT                            0x00001000U
-#define RTC_DR_MU                            0x00000F00U
-#define RTC_DR_MU_0                          0x00000100U
-#define RTC_DR_MU_1                          0x00000200U
-#define RTC_DR_MU_2                          0x00000400U
-#define RTC_DR_MU_3                          0x00000800U
-#define RTC_DR_DT                            0x00000030U
-#define RTC_DR_DT_0                          0x00000010U
-#define RTC_DR_DT_1                          0x00000020U
-#define RTC_DR_DU                            0x0000000FU
-#define RTC_DR_DU_0                          0x00000001U
-#define RTC_DR_DU_1                          0x00000002U
-#define RTC_DR_DU_2                          0x00000004U
-#define RTC_DR_DU_3                          0x00000008U
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           0x00800000U
-#define RTC_CR_OSEL                          0x00600000U
-#define RTC_CR_OSEL_0                        0x00200000U
-#define RTC_CR_OSEL_1                        0x00400000U
-#define RTC_CR_POL                           0x00100000U
-#define RTC_CR_COSEL                         0x00080000U
-#define RTC_CR_BCK                           0x00040000U
-#define RTC_CR_SUB1H                         0x00020000U
-#define RTC_CR_ADD1H                         0x00010000U
-#define RTC_CR_TSIE                          0x00008000U
-#define RTC_CR_WUTIE                         0x00004000U
-#define RTC_CR_ALRBIE                        0x00002000U
-#define RTC_CR_ALRAIE                        0x00001000U
-#define RTC_CR_TSE                           0x00000800U
-#define RTC_CR_WUTE                          0x00000400U
-#define RTC_CR_ALRBE                         0x00000200U
-#define RTC_CR_ALRAE                         0x00000100U
-#define RTC_CR_DCE                           0x00000080U
-#define RTC_CR_FMT                           0x00000040U
-#define RTC_CR_BYPSHAD                       0x00000020U
-#define RTC_CR_REFCKON                       0x00000010U
-#define RTC_CR_TSEDGE                        0x00000008U
-#define RTC_CR_WUCKSEL                       0x00000007U
-#define RTC_CR_WUCKSEL_0                     0x00000001U
-#define RTC_CR_WUCKSEL_1                     0x00000002U
-#define RTC_CR_WUCKSEL_2                     0x00000004U
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      0x00010000U
-#define RTC_ISR_TAMP1F                       0x00002000U
-#define RTC_ISR_TAMP2F                       0x00004000U
-#define RTC_ISR_TSOVF                        0x00001000U
-#define RTC_ISR_TSF                          0x00000800U
-#define RTC_ISR_WUTF                         0x00000400U
-#define RTC_ISR_ALRBF                        0x00000200U
-#define RTC_ISR_ALRAF                        0x00000100U
-#define RTC_ISR_INIT                         0x00000080U
-#define RTC_ISR_INITF                        0x00000040U
-#define RTC_ISR_RSF                          0x00000020U
-#define RTC_ISR_INITS                        0x00000010U
-#define RTC_ISR_SHPF                         0x00000008U
-#define RTC_ISR_WUTWF                        0x00000004U
-#define RTC_ISR_ALRBWF                       0x00000002U
-#define RTC_ISR_ALRAWF                       0x00000001U
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    0x007F0000U
-#define RTC_PRER_PREDIV_S                    0x00007FFFU
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS                       0x00000080U
-#define RTC_CALIBR_DC                        0x0000001FU
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      0x80000000U
-#define RTC_ALRMAR_WDSEL                     0x40000000U
-#define RTC_ALRMAR_DT                        0x30000000U
-#define RTC_ALRMAR_DT_0                      0x10000000U
-#define RTC_ALRMAR_DT_1                      0x20000000U
-#define RTC_ALRMAR_DU                        0x0F000000U
-#define RTC_ALRMAR_DU_0                      0x01000000U
-#define RTC_ALRMAR_DU_1                      0x02000000U
-#define RTC_ALRMAR_DU_2                      0x04000000U
-#define RTC_ALRMAR_DU_3                      0x08000000U
-#define RTC_ALRMAR_MSK3                      0x00800000U
-#define RTC_ALRMAR_PM                        0x00400000U
-#define RTC_ALRMAR_HT                        0x00300000U
-#define RTC_ALRMAR_HT_0                      0x00100000U
-#define RTC_ALRMAR_HT_1                      0x00200000U
-#define RTC_ALRMAR_HU                        0x000F0000U
-#define RTC_ALRMAR_HU_0                      0x00010000U
-#define RTC_ALRMAR_HU_1                      0x00020000U
-#define RTC_ALRMAR_HU_2                      0x00040000U
-#define RTC_ALRMAR_HU_3                      0x00080000U
-#define RTC_ALRMAR_MSK2                      0x00008000U
-#define RTC_ALRMAR_MNT                       0x00007000U
-#define RTC_ALRMAR_MNT_0                     0x00001000U
-#define RTC_ALRMAR_MNT_1                     0x00002000U
-#define RTC_ALRMAR_MNT_2                     0x00004000U
-#define RTC_ALRMAR_MNU                       0x00000F00U
-#define RTC_ALRMAR_MNU_0                     0x00000100U
-#define RTC_ALRMAR_MNU_1                     0x00000200U
-#define RTC_ALRMAR_MNU_2                     0x00000400U
-#define RTC_ALRMAR_MNU_3                     0x00000800U
-#define RTC_ALRMAR_MSK1                      0x00000080U
-#define RTC_ALRMAR_ST                        0x00000070U
-#define RTC_ALRMAR_ST_0                      0x00000010U
-#define RTC_ALRMAR_ST_1                      0x00000020U
-#define RTC_ALRMAR_ST_2                      0x00000040U
-#define RTC_ALRMAR_SU                        0x0000000FU
-#define RTC_ALRMAR_SU_0                      0x00000001U
-#define RTC_ALRMAR_SU_1                      0x00000002U
-#define RTC_ALRMAR_SU_2                      0x00000004U
-#define RTC_ALRMAR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      0x80000000U
-#define RTC_ALRMBR_WDSEL                     0x40000000U
-#define RTC_ALRMBR_DT                        0x30000000U
-#define RTC_ALRMBR_DT_0                      0x10000000U
-#define RTC_ALRMBR_DT_1                      0x20000000U
-#define RTC_ALRMBR_DU                        0x0F000000U
-#define RTC_ALRMBR_DU_0                      0x01000000U
-#define RTC_ALRMBR_DU_1                      0x02000000U
-#define RTC_ALRMBR_DU_2                      0x04000000U
-#define RTC_ALRMBR_DU_3                      0x08000000U
-#define RTC_ALRMBR_MSK3                      0x00800000U
-#define RTC_ALRMBR_PM                        0x00400000U
-#define RTC_ALRMBR_HT                        0x00300000U
-#define RTC_ALRMBR_HT_0                      0x00100000U
-#define RTC_ALRMBR_HT_1                      0x00200000U
-#define RTC_ALRMBR_HU                        0x000F0000U
-#define RTC_ALRMBR_HU_0                      0x00010000U
-#define RTC_ALRMBR_HU_1                      0x00020000U
-#define RTC_ALRMBR_HU_2                      0x00040000U
-#define RTC_ALRMBR_HU_3                      0x00080000U
-#define RTC_ALRMBR_MSK2                      0x00008000U
-#define RTC_ALRMBR_MNT                       0x00007000U
-#define RTC_ALRMBR_MNT_0                     0x00001000U
-#define RTC_ALRMBR_MNT_1                     0x00002000U
-#define RTC_ALRMBR_MNT_2                     0x00004000U
-#define RTC_ALRMBR_MNU                       0x00000F00U
-#define RTC_ALRMBR_MNU_0                     0x00000100U
-#define RTC_ALRMBR_MNU_1                     0x00000200U
-#define RTC_ALRMBR_MNU_2                     0x00000400U
-#define RTC_ALRMBR_MNU_3                     0x00000800U
-#define RTC_ALRMBR_MSK1                      0x00000080U
-#define RTC_ALRMBR_ST                        0x00000070U
-#define RTC_ALRMBR_ST_0                      0x00000010U
-#define RTC_ALRMBR_ST_1                      0x00000020U
-#define RTC_ALRMBR_ST_2                      0x00000040U
-#define RTC_ALRMBR_SU                        0x0000000FU
-#define RTC_ALRMBR_SU_0                      0x00000001U
-#define RTC_ALRMBR_SU_1                      0x00000002U
-#define RTC_ALRMBR_SU_2                      0x00000004U
-#define RTC_ALRMBR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          0x000000FFU
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           0x0000FFFFU
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     0x00007FFFU
-#define RTC_SHIFTR_ADD1S                     0x80000000U
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          0x00400000U
-#define RTC_TSTR_HT                          0x00300000U
-#define RTC_TSTR_HT_0                        0x00100000U
-#define RTC_TSTR_HT_1                        0x00200000U
-#define RTC_TSTR_HU                          0x000F0000U
-#define RTC_TSTR_HU_0                        0x00010000U
-#define RTC_TSTR_HU_1                        0x00020000U
-#define RTC_TSTR_HU_2                        0x00040000U
-#define RTC_TSTR_HU_3                        0x00080000U
-#define RTC_TSTR_MNT                         0x00007000U
-#define RTC_TSTR_MNT_0                       0x00001000U
-#define RTC_TSTR_MNT_1                       0x00002000U
-#define RTC_TSTR_MNT_2                       0x00004000U
-#define RTC_TSTR_MNU                         0x00000F00U
-#define RTC_TSTR_MNU_0                       0x00000100U
-#define RTC_TSTR_MNU_1                       0x00000200U
-#define RTC_TSTR_MNU_2                       0x00000400U
-#define RTC_TSTR_MNU_3                       0x00000800U
-#define RTC_TSTR_ST                          0x00000070U
-#define RTC_TSTR_ST_0                        0x00000010U
-#define RTC_TSTR_ST_1                        0x00000020U
-#define RTC_TSTR_ST_2                        0x00000040U
-#define RTC_TSTR_SU                          0x0000000FU
-#define RTC_TSTR_SU_0                        0x00000001U
-#define RTC_TSTR_SU_1                        0x00000002U
-#define RTC_TSTR_SU_2                        0x00000004U
-#define RTC_TSTR_SU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         0x0000E000U
-#define RTC_TSDR_WDU_0                       0x00002000U
-#define RTC_TSDR_WDU_1                       0x00004000U
-#define RTC_TSDR_WDU_2                       0x00008000U
-#define RTC_TSDR_MT                          0x00001000U
-#define RTC_TSDR_MU                          0x00000F00U
-#define RTC_TSDR_MU_0                        0x00000100U
-#define RTC_TSDR_MU_1                        0x00000200U
-#define RTC_TSDR_MU_2                        0x00000400U
-#define RTC_TSDR_MU_3                        0x00000800U
-#define RTC_TSDR_DT                          0x00000030U
-#define RTC_TSDR_DT_0                        0x00000010U
-#define RTC_TSDR_DT_1                        0x00000020U
-#define RTC_TSDR_DU                          0x0000000FU
-#define RTC_TSDR_DU_0                        0x00000001U
-#define RTC_TSDR_DU_1                        0x00000002U
-#define RTC_TSDR_DU_2                        0x00000004U
-#define RTC_TSDR_DU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        0x00008000U
-#define RTC_CALR_CALW8                       0x00004000U
-#define RTC_CALR_CALW16                      0x00002000U
-#define RTC_CALR_CALM                        0x000001FFU
-#define RTC_CALR_CALM_0                      0x00000001U
-#define RTC_CALR_CALM_1                      0x00000002U
-#define RTC_CALR_CALM_2                      0x00000004U
-#define RTC_CALR_CALM_3                      0x00000008U
-#define RTC_CALR_CALM_4                      0x00000010U
-#define RTC_CALR_CALM_5                      0x00000020U
-#define RTC_CALR_CALM_6                      0x00000040U
-#define RTC_CALR_CALM_7                      0x00000080U
-#define RTC_CALR_CALM_8                      0x00000100U
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               0x00040000U
-#define RTC_TAFCR_TSINSEL                    0x00020000U
-#define RTC_TAFCR_TAMPINSEL                  0x00010000U
-#define RTC_TAFCR_TAMPPUDIS                  0x00008000U
-#define RTC_TAFCR_TAMPPRCH                   0x00006000U
-#define RTC_TAFCR_TAMPPRCH_0                 0x00002000U
-#define RTC_TAFCR_TAMPPRCH_1                 0x00004000U
-#define RTC_TAFCR_TAMPFLT                    0x00001800U
-#define RTC_TAFCR_TAMPFLT_0                  0x00000800U
-#define RTC_TAFCR_TAMPFLT_1                  0x00001000U
-#define RTC_TAFCR_TAMPFREQ                   0x00000700U
-#define RTC_TAFCR_TAMPFREQ_0                 0x00000100U
-#define RTC_TAFCR_TAMPFREQ_1                 0x00000200U
-#define RTC_TAFCR_TAMPFREQ_2                 0x00000400U
-#define RTC_TAFCR_TAMPTS                     0x00000080U
-#define RTC_TAFCR_TAMP2TRG                   0x00000010U
-#define RTC_TAFCR_TAMP2E                     0x00000008U
-#define RTC_TAFCR_TAMPIE                     0x00000004U
-#define RTC_TAFCR_TAMP1TRG                   0x00000002U
-#define RTC_TAFCR_TAMP1E                     0x00000001U
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  0x0F000000U
-#define RTC_ALRMASSR_MASKSS_0                0x01000000U
-#define RTC_ALRMASSR_MASKSS_1                0x02000000U
-#define RTC_ALRMASSR_MASKSS_2                0x04000000U
-#define RTC_ALRMASSR_MASKSS_3                0x08000000U
-#define RTC_ALRMASSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
-#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
-#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
-#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
-#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
-#define RTC_ALRMBSSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           0xFFFFFFFFU
-
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          SD host Interface                                 */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SDIO_POWER register  ******************/
-#define  SDIO_POWER_PWRCTRL                  0x03U               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDIO_POWER_PWRCTRL_0                0x01U               /*!<Bit 0 */
-#define  SDIO_POWER_PWRCTRL_1                0x02U               /*!<Bit 1 */
-
-/******************  Bit definition for SDIO_CLKCR register  ******************/
-#define  SDIO_CLKCR_CLKDIV                   0x00FFU            /*!<Clock divide factor             */
-#define  SDIO_CLKCR_CLKEN                    0x0100U            /*!<Clock enable bit                */
-#define  SDIO_CLKCR_PWRSAV                   0x0200U            /*!<Power saving configuration bit  */
-#define  SDIO_CLKCR_BYPASS                   0x0400U            /*!<Clock divider bypass enable bit */
-
-#define  SDIO_CLKCR_WIDBUS                   0x1800U            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDIO_CLKCR_WIDBUS_0                 0x0800U            /*!<Bit 0 */
-#define  SDIO_CLKCR_WIDBUS_1                 0x1000U            /*!<Bit 1 */
-
-#define  SDIO_CLKCR_NEGEDGE                  0x2000U            /*!<SDIO_CK dephasing selection bit */
-#define  SDIO_CLKCR_HWFC_EN                  0x4000U            /*!<HW Flow Control enable          */
-
-/*******************  Bit definition for SDIO_ARG register  *******************/
-#define  SDIO_ARG_CMDARG                     0xFFFFFFFFU            /*!<Command argument */
-
-/*******************  Bit definition for SDIO_CMD register  *******************/
-#define  SDIO_CMD_CMDINDEX                   0x003FU            /*!<Command Index                               */
-
-#define  SDIO_CMD_WAITRESP                   0x00C0U            /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDIO_CMD_WAITRESP_0                 0x0040U            /*!< Bit 0 */
-#define  SDIO_CMD_WAITRESP_1                 0x0080U            /*!< Bit 1 */
-
-#define  SDIO_CMD_WAITINT                    0x0100U            /*!<CPSM Waits for Interrupt Request                               */
-#define  SDIO_CMD_WAITPEND                   0x0200U            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDIO_CMD_CPSMEN                     0x0400U            /*!<Command path state machine (CPSM) Enable bit                   */
-#define  SDIO_CMD_SDIOSUSPEND                0x0800U            /*!<SD I/O suspend command                                         */
-#define  SDIO_CMD_ENCMDCOMPL                 0x1000U            /*!<Enable CMD completion                                          */
-#define  SDIO_CMD_NIEN                       0x2000U            /*!<Not Interrupt Enable */
-#define  SDIO_CMD_CEATACMD                   0x4000U            /*!<CE-ATA command       */
-
-/*****************  Bit definition for SDIO_RESPCMD register  *****************/
-#define  SDIO_RESPCMD_RESPCMD                0x3FU               /*!<Response command index */
-
-/******************  Bit definition for SDIO_RESP0 register  ******************/
-#define  SDIO_RESP0_CARDSTATUS0              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP1 register  ******************/
-#define  SDIO_RESP1_CARDSTATUS1              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP2 register  ******************/
-#define  SDIO_RESP2_CARDSTATUS2              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP3 register  ******************/
-#define  SDIO_RESP3_CARDSTATUS3              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP4 register  ******************/
-#define  SDIO_RESP4_CARDSTATUS4              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_DTIMER register  *****************/
-#define  SDIO_DTIMER_DATATIME                0xFFFFFFFFU        /*!<Data timeout period. */
-
-/******************  Bit definition for SDIO_DLEN register  *******************/
-#define  SDIO_DLEN_DATALENGTH                0x01FFFFFFU        /*!<Data length value    */
-
-/******************  Bit definition for SDIO_DCTRL register  ******************/
-#define  SDIO_DCTRL_DTEN                     0x0001U            /*!<Data transfer enabled bit         */
-#define  SDIO_DCTRL_DTDIR                    0x0002U            /*!<Data transfer direction selection */
-#define  SDIO_DCTRL_DTMODE                   0x0004U            /*!<Data transfer mode selection      */
-#define  SDIO_DCTRL_DMAEN                    0x0008U            /*!<DMA enabled bit                   */
-
-#define  SDIO_DCTRL_DBLOCKSIZE               0x00F0U            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDIO_DCTRL_DBLOCKSIZE_0             0x0010U            /*!<Bit 0 */
-#define  SDIO_DCTRL_DBLOCKSIZE_1             0x0020U            /*!<Bit 1 */
-#define  SDIO_DCTRL_DBLOCKSIZE_2             0x0040U            /*!<Bit 2 */
-#define  SDIO_DCTRL_DBLOCKSIZE_3             0x0080U            /*!<Bit 3 */
-
-#define  SDIO_DCTRL_RWSTART                  0x0100U            /*!<Read wait start         */
-#define  SDIO_DCTRL_RWSTOP                   0x0200U            /*!<Read wait stop          */
-#define  SDIO_DCTRL_RWMOD                    0x0400U            /*!<Read wait mode          */
-#define  SDIO_DCTRL_SDIOEN                   0x0800U            /*!<SD I/O enable functions */
-
-/******************  Bit definition for SDIO_DCOUNT register  *****************/
-#define  SDIO_DCOUNT_DATACOUNT               0x01FFFFFFU        /*!<Data count value */
-
-/******************  Bit definition for SDIO_STA register  ********************/
-#define  SDIO_STA_CCRCFAIL                   0x00000001U        /*!<Command response received (CRC check failed)  */
-#define  SDIO_STA_DCRCFAIL                   0x00000002U        /*!<Data block sent/received (CRC check failed)   */
-#define  SDIO_STA_CTIMEOUT                   0x00000004U        /*!<Command response timeout                      */
-#define  SDIO_STA_DTIMEOUT                   0x00000008U        /*!<Data timeout                                  */
-#define  SDIO_STA_TXUNDERR                   0x00000010U        /*!<Transmit FIFO underrun error                  */
-#define  SDIO_STA_RXOVERR                    0x00000020U        /*!<Received FIFO overrun error                   */
-#define  SDIO_STA_CMDREND                    0x00000040U        /*!<Command response received (CRC check passed)  */
-#define  SDIO_STA_CMDSENT                    0x00000080U        /*!<Command sent (no response required)           */
-#define  SDIO_STA_DATAEND                    0x00000100U        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
-#define  SDIO_STA_STBITERR                   0x00000200U        /*!<Start bit not detected on all data signals in wide bus mode */
-#define  SDIO_STA_DBCKEND                    0x00000400U        /*!<Data block sent/received (CRC check passed)   */
-#define  SDIO_STA_CMDACT                     0x00000800U        /*!<Command transfer in progress                  */
-#define  SDIO_STA_TXACT                      0x00001000U        /*!<Data transmit in progress                     */
-#define  SDIO_STA_RXACT                      0x00002000U        /*!<Data receive in progress                      */
-#define  SDIO_STA_TXFIFOHE                   0x00004000U        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDIO_STA_RXFIFOHF                   0x00008000U        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDIO_STA_TXFIFOF                    0x00010000U        /*!<Transmit FIFO full                            */
-#define  SDIO_STA_RXFIFOF                    0x00020000U        /*!<Receive FIFO full                             */
-#define  SDIO_STA_TXFIFOE                    0x00040000U        /*!<Transmit FIFO empty                           */
-#define  SDIO_STA_RXFIFOE                    0x00080000U        /*!<Receive FIFO empty                            */
-#define  SDIO_STA_TXDAVL                     0x00100000U        /*!<Data available in transmit FIFO               */
-#define  SDIO_STA_RXDAVL                     0x00200000U        /*!<Data available in receive FIFO                */
-#define  SDIO_STA_SDIOIT                     0x00400000U        /*!<SDIO interrupt received                       */
-#define  SDIO_STA_CEATAEND                   0x00800000U        /*!<CE-ATA command completion signal received for CMD61 */
-
-/*******************  Bit definition for SDIO_ICR register  *******************/
-#define  SDIO_ICR_CCRCFAILC                  0x00000001U        /*!<CCRCFAIL flag clear bit */
-#define  SDIO_ICR_DCRCFAILC                  0x00000002U        /*!<DCRCFAIL flag clear bit */
-#define  SDIO_ICR_CTIMEOUTC                  0x00000004U        /*!<CTIMEOUT flag clear bit */
-#define  SDIO_ICR_DTIMEOUTC                  0x00000008U        /*!<DTIMEOUT flag clear bit */
-#define  SDIO_ICR_TXUNDERRC                  0x00000010U        /*!<TXUNDERR flag clear bit */
-#define  SDIO_ICR_RXOVERRC                   0x00000020U        /*!<RXOVERR flag clear bit  */
-#define  SDIO_ICR_CMDRENDC                   0x00000040U        /*!<CMDREND flag clear bit  */
-#define  SDIO_ICR_CMDSENTC                   0x00000080U        /*!<CMDSENT flag clear bit  */
-#define  SDIO_ICR_DATAENDC                   0x00000100U        /*!<DATAEND flag clear bit  */
-#define  SDIO_ICR_STBITERRC                  0x00000200U        /*!<STBITERR flag clear bit */
-#define  SDIO_ICR_DBCKENDC                   0x00000400U        /*!<DBCKEND flag clear bit  */
-#define  SDIO_ICR_SDIOITC                    0x00400000U        /*!<SDIOIT flag clear bit   */
-#define  SDIO_ICR_CEATAENDC                  0x00800000U        /*!<CEATAEND flag clear bit */
-
-/******************  Bit definition for SDIO_MASK register  *******************/
-#define  SDIO_MASK_CCRCFAILIE                0x00000001U        /*!<Command CRC Fail Interrupt Enable          */
-#define  SDIO_MASK_DCRCFAILIE                0x00000002U        /*!<Data CRC Fail Interrupt Enable             */
-#define  SDIO_MASK_CTIMEOUTIE                0x00000004U        /*!<Command TimeOut Interrupt Enable           */
-#define  SDIO_MASK_DTIMEOUTIE                0x00000008U        /*!<Data TimeOut Interrupt Enable              */
-#define  SDIO_MASK_TXUNDERRIE                0x00000010U        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
-#define  SDIO_MASK_RXOVERRIE                 0x00000020U        /*!<Rx FIFO OverRun Error Interrupt Enable     */
-#define  SDIO_MASK_CMDRENDIE                 0x00000040U        /*!<Command Response Received Interrupt Enable */
-#define  SDIO_MASK_CMDSENTIE                 0x00000080U        /*!<Command Sent Interrupt Enable              */
-#define  SDIO_MASK_DATAENDIE                 0x00000100U        /*!<Data End Interrupt Enable                  */
-#define  SDIO_MASK_STBITERRIE                0x00000200U        /*!<Start Bit Error Interrupt Enable           */
-#define  SDIO_MASK_DBCKENDIE                 0x00000400U        /*!<Data Block End Interrupt Enable            */
-#define  SDIO_MASK_CMDACTIE                  0x00000800U        /*!<CCommand Acting Interrupt Enable           */
-#define  SDIO_MASK_TXACTIE                   0x00001000U        /*!<Data Transmit Acting Interrupt Enable      */
-#define  SDIO_MASK_RXACTIE                   0x00002000U        /*!<Data receive acting interrupt enabled      */
-#define  SDIO_MASK_TXFIFOHEIE                0x00004000U        /*!<Tx FIFO Half Empty interrupt Enable        */
-#define  SDIO_MASK_RXFIFOHFIE                0x00008000U        /*!<Rx FIFO Half Full interrupt Enable         */
-#define  SDIO_MASK_TXFIFOFIE                 0x00010000U        /*!<Tx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_RXFIFOFIE                 0x00020000U        /*!<Rx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_TXFIFOEIE                 0x00040000U        /*!<Tx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_RXFIFOEIE                 0x00080000U        /*!<Rx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_TXDAVLIE                  0x00100000U        /*!<Data available in Tx FIFO interrupt Enable */
-#define  SDIO_MASK_RXDAVLIE                  0x00200000U        /*!<Data available in Rx FIFO interrupt Enable */
-#define  SDIO_MASK_SDIOITIE                  0x00400000U        /*!<SDIO Mode Interrupt Received interrupt Enable */
-#define  SDIO_MASK_CEATAENDIE                0x00800000U        /*!<CE-ATA command completion signal received Interrupt Enable */
-
-/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
-#define  SDIO_FIFOCNT_FIFOCOUNT              0x00FFFFFFU        /*!<Remaining number of words to be written to or read from the FIFO */
-
-/******************  Bit definition for SDIO_FIFO register  *******************/
-#define  SDIO_FIFO_FIFODATA                  0xFFFFFFFFU        /*!<Receive and transmit FIFO data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        0x00000001U            /*!<Clock Phase      */
-#define  SPI_CR1_CPOL                        0x00000002U            /*!<Clock Polarity   */
-#define  SPI_CR1_MSTR                        0x00000004U            /*!<Master Selection */
-
-#define  SPI_CR1_BR                          0x00000038U            /*!<BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        0x00000008U            /*!<Bit 0 */
-#define  SPI_CR1_BR_1                        0x00000010U            /*!<Bit 1 */
-#define  SPI_CR1_BR_2                        0x00000020U            /*!<Bit 2 */
-
-#define  SPI_CR1_SPE                         0x00000040U            /*!<SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    0x00000080U            /*!<Frame Format                        */
-#define  SPI_CR1_SSI                         0x00000100U            /*!<Internal slave select               */
-#define  SPI_CR1_SSM                         0x00000200U            /*!<Software slave management           */
-#define  SPI_CR1_RXONLY                      0x00000400U            /*!<Receive only                        */
-#define  SPI_CR1_DFF                         0x00000800U            /*!<Data Frame Format                   */
-#define  SPI_CR1_CRCNEXT                     0x00001000U            /*!<Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       0x00002000U            /*!<Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      0x00004000U            /*!<Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    0x00008000U            /*!<Bidirectional data mode enable      */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     0x00000001U               /*!<Rx Buffer DMA Enable                 */
-#define  SPI_CR2_TXDMAEN                     0x00000002U               /*!<Tx Buffer DMA Enable                 */
-#define  SPI_CR2_SSOE                        0x00000004U               /*!<SS Output Enable                     */
-#define  SPI_CR2_FRF                         0x00000010U               /*!<Frame Format                         */
-#define  SPI_CR2_ERRIE                       0x00000020U               /*!<Error Interrupt Enable               */
-#define  SPI_CR2_RXNEIE                      0x00000040U               /*!<RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       0x00000080U               /*!<Tx buffer Empty Interrupt Enable     */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         0x00000001U               /*!<Receive buffer Not Empty */
-#define  SPI_SR_TXE                          0x00000002U               /*!<Transmit buffer Empty    */
-#define  SPI_SR_CHSIDE                       0x00000004U               /*!<Channel side             */
-#define  SPI_SR_UDR                          0x00000008U               /*!<Underrun flag            */
-#define  SPI_SR_CRCERR                       0x00000010U               /*!<CRC Error flag           */
-#define  SPI_SR_MODF                         0x00000020U               /*!<Mode fault               */
-#define  SPI_SR_OVR                          0x00000040U               /*!<Overrun flag             */
-#define  SPI_SR_BSY                          0x00000080U               /*!<Busy flag                */
-#define  SPI_SR_FRE                          0x00000100U               /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           0x0000FFFFU            /*!<Data Register           */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   0x0000FFFFU            /*!<CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    0x0000FFFFU            /*!<Rx CRC Register         */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    0x0000FFFFU            /*!<Tx CRC Register         */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   0x00000001U            /*!<Channel length (number of bits per audio channel) */
-
-#define  SPI_I2SCFGR_DATLEN                  0x00000006U            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define  SPI_I2SCFGR_DATLEN_0                0x00000002U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                0x00000004U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_CKPOL                   0x00000008U            /*!<steady state clock polarity               */
-
-#define  SPI_I2SCFGR_I2SSTD                  0x00000030U            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U            /*!<PCM frame synchronization                 */
-
-#define  SPI_I2SCFGR_I2SCFG                  0x00000300U            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_I2SE                    0x00000400U            /*!<I2S Enable         */
-#define  SPI_I2SCFGR_I2SMOD                  0x00000800U            /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    0x000000FFU            /*!<I2S Linear prescaler         */
-#define  SPI_I2SPR_ODD                       0x00000100U            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     0x00000200U            /*!<Master Clock Output Enable   */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 SYSCFG                                     */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
-#define SYSCFG_MEMRMP_MEM_MODE          0x00000007U /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        0x00000001U
-#define SYSCFG_MEMRMP_MEM_MODE_1        0x00000002U
-#define SYSCFG_MEMRMP_MEM_MODE_2        0x00000004U
-
-/******************  Bit definition for SYSCFG_PMC register  ******************/
-#define SYSCFG_PMC_MII_RMII_SEL         0x00800000U /*!<Ethernet PHY interface selection */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
-/** 
-  * @brief   EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         0x0003U /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         0x0004U /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         0x0005U /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         0x0006U /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PI         0x0008U /*!<PI[0] pin */
-
-/** 
-  * @brief   EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         0x0030U /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         0x0040U /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         0x0050U /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         0x0060U /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PI         0x0080U /*!<PI[1] pin */
-
-/** 
-  * @brief   EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         0x0300U /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         0x0400U /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         0x0500U /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         0x0600U /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PI         0x0800U /*!<PI[2] pin */
-
-/** 
-  * @brief   EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         0x3000U /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         0x4000U /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         0x5000U /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         0x6000U /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PI         0x8000U /*!<PI[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
-/** 
-  * @brief   EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         0x0003U /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         0x0004U /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         0x0005U /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         0x0006U /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PI         0x0008U /*!<PI[4] pin */
-
-/** 
-  * @brief   EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         0x0030U /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         0x0040U /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         0x0050U /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         0x0060U /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PI         0x0080U /*!<PI[5] pin */
-
-/** 
-  * @brief   EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         0x0300U /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         0x0400U /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         0x0500U /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         0x0600U /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PI         0x0800U /*!<PI[6] pin */
-
-/** 
-  * @brief   EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         0x3000U /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         0x4000U /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         0x5000U /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         0x6000U /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PI         0x8000U /*!<PI[7] pin */
-
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
-           
-/** 
-  * @brief   EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         0x0003U /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         0x0004U /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         0x0005U /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         0x0006U /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PI         0x0008U /*!<PI[8] pin */
-
-/** 
-  * @brief   EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         0x0030U /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         0x0040U /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         0x0050U /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         0x0060U /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PI         0x0080U /*!<PI[9] pin */
-
-/** 
-  * @brief   EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        0x0300U /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        0x0400U /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        0x0500U /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        0x0600U /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PI        0x0800U /*!<PI[10] pin */
-
-/** 
-  * @brief   EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        0x3000U /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        0x4000U /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        0x5000U /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        0x6000U /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PI        0x8000U /*!<PI[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
-/** 
-  * @brief   EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        0x0003U /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        0x0004U /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        0x0005U /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        0x0006U /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
-
-/** 
-  * @brief   EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        0x0030U /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        0x0040U /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        0x0050U /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        0x0060U /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
-
-/** 
-  * @brief   EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        0x0300U /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        0x0400U /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        0x0500U /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        0x0600U /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
-
-/** 
-  * @brief   EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        0x3000U /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        0x4000U /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        0x5000U /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        0x6000U /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
-
-/******************  Bit definition for SYSCFG_CMPCR register  ****************/  
-#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell ready flag */
-#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell power-down */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    TIM                                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
-#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
-#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
-#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
-#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
-
-#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
-
-#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
-
-#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        0x0001U            /*!<Capture/Compare Preloaded Control        */
-#define  TIM_CR2_CCUS                        0x0004U            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        0x0008U            /*!<Capture/Compare DMA Selection            */
-
-#define  TIM_CR2_MMS                         0x0070U            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
-#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
-#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
-#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        0x0007U            /*!<SMS[2:0] bits (Slave mode selection)    */
-#define  TIM_SMCR_SMS_0                      0x0001U            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      0x0002U            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      0x0004U            /*!<Bit 2 */
-
-#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
-#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
-
-#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
-
-#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
-
-#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
-#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
-#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
-#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
-#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
-#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
-#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
-#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
-#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
-#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
-#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
-#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
-#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
-#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
-#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
-#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
-#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
-#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
-#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          0x01U               /*!<Update Generation                         */
-#define  TIM_EGR_CC1G                        0x02U               /*!<Capture/Compare 1 Generation              */
-#define  TIM_EGR_CC2G                        0x04U               /*!<Capture/Compare 2 Generation              */
-#define  TIM_EGR_CC3G                        0x08U               /*!<Capture/Compare 3 Generation              */
-#define  TIM_EGR_CC4G                        0x10U               /*!<Capture/Compare 4 Generation              */
-#define  TIM_EGR_COMG                        0x20U               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          0x40U               /*!<Trigger Generation                        */
-#define  TIM_EGR_BG                          0x80U               /*!<Break Generation                          */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      0x0003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    0x0001U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    0x0002U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC1FE                     0x0004U            /*!<Output Compare 1 Fast enable                 */
-#define  TIM_CCMR1_OC1PE                     0x0008U            /*!<Output Compare 1 Preload enable              */
-
-#define  TIM_CCMR1_OC1M                      0x0070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define  TIM_CCMR1_OC1M_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    0x0040U            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC1CE                     0x0080U            /*!<Output Compare 1Clear Enable                 */
-
-#define  TIM_CCMR1_CC2S                      0x0300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    0x0100U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    0x0200U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC2FE                     0x0400U            /*!<Output Compare 2 Fast enable                 */
-#define  TIM_CCMR1_OC2PE                     0x0800U            /*!<Output Compare 2 Preload enable              */
-
-#define  TIM_CCMR1_OC2M                      0x7000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define  TIM_CCMR1_OC2M_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    0x4000U            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC2CE                     0x8000U            /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      0x0003U            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define  TIM_CCMR2_CC3S_0                    0x0001U            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    0x0002U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC3FE                     0x0004U            /*!<Output Compare 3 Fast enable           */
-#define  TIM_CCMR2_OC3PE                     0x0008U            /*!<Output Compare 3 Preload enable        */
-
-#define  TIM_CCMR2_OC3M                      0x0070U            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    0x0040U            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC3CE                     0x0080U            /*!<Output Compare 3 Clear Enable */
-
-#define  TIM_CCMR2_CC4S                      0x0300U            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    0x0100U            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    0x0200U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC4FE                     0x0400U            /*!<Output Compare 4 Fast enable    */
-#define  TIM_CCMR2_OC4PE                     0x0800U            /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR2_OC4M                      0x7000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    0x4000U            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       0x0001U            /*!<Capture/Compare 1 output enable                 */
-#define  TIM_CCER_CC1P                       0x0002U            /*!<Capture/Compare 1 output Polarity               */
-#define  TIM_CCER_CC1NE                      0x0004U            /*!<Capture/Compare 1 Complementary output enable   */
-#define  TIM_CCER_CC1NP                      0x0008U            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       0x0010U            /*!<Capture/Compare 2 output enable                 */
-#define  TIM_CCER_CC2P                       0x0020U            /*!<Capture/Compare 2 output Polarity               */
-#define  TIM_CCER_CC2NE                      0x0040U            /*!<Capture/Compare 2 Complementary output enable   */
-#define  TIM_CCER_CC2NP                      0x0080U            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       0x0100U            /*!<Capture/Compare 3 output enable                 */
-#define  TIM_CCER_CC3P                       0x0200U            /*!<Capture/Compare 3 output Polarity               */
-#define  TIM_CCER_CC3NE                      0x0400U            /*!<Capture/Compare 3 Complementary output enable   */
-#define  TIM_CCER_CC3NP                      0x0800U            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       0x1000U            /*!<Capture/Compare 4 output enable                 */
-#define  TIM_CCER_CC4P                       0x2000U            /*!<Capture/Compare 4 output Polarity               */
-#define  TIM_CCER_CC4NP                      0x8000U            /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         0xFFU               /*!<Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
-
-/*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        0x00FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      0x0001U            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      0x0002U            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      0x0004U            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      0x0008U            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      0x0010U            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      0x0020U            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      0x0040U            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      0x0080U            /*!<Bit 7 */
-
-#define  TIM_BDTR_LOCK                       0x0300U            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     0x0100U            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     0x0200U            /*!<Bit 1 */
-
-#define  TIM_BDTR_OSSI                       0x0400U            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       0x0800U            /*!<Off-State Selection for Run mode  */
-#define  TIM_BDTR_BKE                        0x1000U            /*!<Break enable                      */
-#define  TIM_BDTR_BKP                        0x2000U            /*!<Break Polarity                    */
-#define  TIM_BDTR_AOE                        0x4000U            /*!<Automatic Output enable           */
-#define  TIM_BDTR_MOE                        0x8000U            /*!<Main Output enable                */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
-
-#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
-#define TIM_OR_ITR1_RMP                      0x0C00U            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
-#define TIM_OR_ITR1_RMP_0                    0x0400U            /*!<Bit 0 */
-#define TIM_OR_ITR1_RMP_1                    0x0800U            /*!<Bit 1 */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*         Universal Synchronous Asynchronous Receiver Transmitter            */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         0x0001U            /*!<Parity Error                 */
-#define  USART_SR_FE                         0x0002U            /*!<Framing Error                */
-#define  USART_SR_NE                         0x0004U            /*!<Noise Error Flag             */
-#define  USART_SR_ORE                        0x0008U            /*!<OverRun Error                */
-#define  USART_SR_IDLE                       0x0010U            /*!<IDLE line detected           */
-#define  USART_SR_RXNE                       0x0020U            /*!<Read Data Register Not Empty */
-#define  USART_SR_TC                         0x0040U            /*!<Transmission Complete        */
-#define  USART_SR_TXE                        0x0080U            /*!<Transmit Data Register Empty */
-#define  USART_SR_LBD                        0x0100U            /*!<LIN Break Detection Flag     */
-#define  USART_SR_CTS                        0x0200U            /*!<CTS Flag                     */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         0x01FFU            /*!<Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_Fraction              0x000FU            /*!<Fraction of USARTDIV */
-#define  USART_BRR_DIV_Mantissa              0xFFF0U            /*!<Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       0x0001U            /*!<Send Break                             */
-#define  USART_CR1_RWU                       0x0002U            /*!<Receiver wakeup                        */
-#define  USART_CR1_RE                        0x0004U            /*!<Receiver Enable                        */
-#define  USART_CR1_TE                        0x0008U            /*!<Transmitter Enable                     */
-#define  USART_CR1_IDLEIE                    0x0010U            /*!<IDLE Interrupt Enable                  */
-#define  USART_CR1_RXNEIE                    0x0020U            /*!<RXNE Interrupt Enable                  */
-#define  USART_CR1_TCIE                      0x0040U            /*!<Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     0x0080U            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PEIE                      0x0100U            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PS                        0x0200U            /*!<Parity Selection                       */
-#define  USART_CR1_PCE                       0x0400U            /*!<Parity Control Enable                  */
-#define  USART_CR1_WAKE                      0x0800U            /*!<Wakeup method                          */
-#define  USART_CR1_M                         0x1000U            /*!<Word length                            */
-#define  USART_CR1_UE                        0x2000U            /*!<USART Enable                           */
-#define  USART_CR1_OVER8                     0x8000U            /*!<USART Oversampling by 8 enable         */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       0x000FU            /*!<Address of the USART node            */
-#define  USART_CR2_LBDL                      0x0020U            /*!<LIN Break Detection Length           */
-#define  USART_CR2_LBDIE                     0x0040U            /*!<LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      0x0100U            /*!<Last Bit Clock pulse                 */
-#define  USART_CR2_CPHA                      0x0200U            /*!<Clock Phase                          */
-#define  USART_CR2_CPOL                      0x0400U            /*!<Clock Polarity                       */
-#define  USART_CR2_CLKEN                     0x0800U            /*!<Clock Enable                         */
-
-#define  USART_CR2_STOP                      0x3000U            /*!<STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    0x1000U            /*!<Bit 0 */
-#define  USART_CR2_STOP_1                    0x2000U            /*!<Bit 1 */
-
-#define  USART_CR2_LINEN                     0x4000U            /*!<LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       0x0001U            /*!<Error Interrupt Enable      */
-#define  USART_CR3_IREN                      0x0002U            /*!<IrDA mode Enable            */
-#define  USART_CR3_IRLP                      0x0004U            /*!<IrDA Low-Power              */
-#define  USART_CR3_HDSEL                     0x0008U            /*!<Half-Duplex Selection       */
-#define  USART_CR3_NACK                      0x0010U            /*!<Smartcard NACK enable       */
-#define  USART_CR3_SCEN                      0x0020U            /*!<Smartcard mode enable       */
-#define  USART_CR3_DMAR                      0x0040U            /*!<DMA Enable Receiver         */
-#define  USART_CR3_DMAT                      0x0080U            /*!<DMA Enable Transmitter      */
-#define  USART_CR3_RTSE                      0x0100U            /*!<RTS Enable                  */
-#define  USART_CR3_CTSE                      0x0200U            /*!<CTS Enable                  */
-#define  USART_CR3_CTSIE                     0x0400U            /*!<CTS Interrupt Enable        */
-#define  USART_CR3_ONEBIT                    0x0800U            /*!<USART One bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      0x00FFU            /*!<PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    0x0001U            /*!<Bit 0 */
-#define  USART_GTPR_PSC_1                    0x0002U            /*!<Bit 1 */
-#define  USART_GTPR_PSC_2                    0x0004U            /*!<Bit 2 */
-#define  USART_GTPR_PSC_3                    0x0008U            /*!<Bit 3 */
-#define  USART_GTPR_PSC_4                    0x0010U            /*!<Bit 4 */
-#define  USART_GTPR_PSC_5                    0x0020U            /*!<Bit 5 */
-#define  USART_GTPR_PSC_6                    0x0040U            /*!<Bit 6 */
-#define  USART_GTPR_PSC_7                    0x0080U            /*!<Bit 7 */
-
-#define  USART_GTPR_GT                       0xFF00U            /*!<Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Window WATCHDOG                                 */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           0x7FU               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T_0                         0x01U               /*!<Bit 0 */
-#define  WWDG_CR_T_1                         0x02U               /*!<Bit 1 */
-#define  WWDG_CR_T_2                         0x04U               /*!<Bit 2 */
-#define  WWDG_CR_T_3                         0x08U               /*!<Bit 3 */
-#define  WWDG_CR_T_4                         0x10U               /*!<Bit 4 */
-#define  WWDG_CR_T_5                         0x20U               /*!<Bit 5 */
-#define  WWDG_CR_T_6                         0x40U               /*!<Bit 6 */
-/* Legacy defines */
-#define  WWDG_CR_T0                          WWDG_CR_T_0
-#define  WWDG_CR_T1                          WWDG_CR_T_1
-#define  WWDG_CR_T2                          WWDG_CR_T_2
-#define  WWDG_CR_T3                          WWDG_CR_T_3
-#define  WWDG_CR_T4                          WWDG_CR_T_4
-#define  WWDG_CR_T5                          WWDG_CR_T_5
-#define  WWDG_CR_T6                          WWDG_CR_T_6
-
-#define  WWDG_CR_WDGA                        0x80U               /*!<Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          0x007FU            /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W_0                        0x0001U            /*!<Bit 0 */
-#define  WWDG_CFR_W_1                        0x0002U            /*!<Bit 1 */
-#define  WWDG_CFR_W_2                        0x0004U            /*!<Bit 2 */
-#define  WWDG_CFR_W_3                        0x0008U            /*!<Bit 3 */
-#define  WWDG_CFR_W_4                        0x0010U            /*!<Bit 4 */
-#define  WWDG_CFR_W_5                        0x0020U            /*!<Bit 5 */
-#define  WWDG_CFR_W_6                        0x0040U            /*!<Bit 6 */
-/* Legacy defines */
-#define  WWDG_CFR_W0                         WWDG_CFR_W_0
-#define  WWDG_CFR_W1                         WWDG_CFR_W_1
-#define  WWDG_CFR_W2                         WWDG_CFR_W_2
-#define  WWDG_CFR_W3                         WWDG_CFR_W_3
-#define  WWDG_CFR_W4                         WWDG_CFR_W_4
-#define  WWDG_CFR_W5                         WWDG_CFR_W_5
-#define  WWDG_CFR_W6                         WWDG_CFR_W_6
-
-#define  WWDG_CFR_WDGTB                      0x0180U            /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB_0                    0x0080U            /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB_1                    0x0100U            /*!<Bit 1 */
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
-
-#define  WWDG_CFR_EWI                        0x0200U            /*!<Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        0x01U               /*!<Early Wakeup Interrupt Flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                DBG                                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
-#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
-
-/********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
-#define  DBGMCU_CR_DBG_STOP                  0x00000002U
-#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
-#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
-
-#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
-#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U/*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U/*!<Bit 1 */
-
-/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            0x00000001U
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            0x00000002U
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            0x00000004U
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            0x00000020U
-#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           0x00000040U
-#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           0x00000080U
-#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           0x00000100U
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
-#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
-/* Old IWDGSTOP bit definition, maintained for legacy purpose */
-#define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
-
-/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        0x00000001U
-#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        0x00000002U
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        0x00010000U
-#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       0x00020000U
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       0x00040000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                Ethernet MAC Registers bits definitions                     */
-/*                                                                            */
-/******************************************************************************/
-/* Bit definition for Ethernet MAC Control Register register */
-#define ETH_MACCR_WD      0x00800000U  /* Watchdog disable */
-#define ETH_MACCR_JD      0x00400000U  /* Jabber disable */
-#define ETH_MACCR_IFG     0x000E0000U  /* Inter-frame gap */
-#define ETH_MACCR_IFG_96Bit     0x00000000U  /* Minimum IFG between frames during transmission is 96Bit */
-  #define ETH_MACCR_IFG_88Bit     0x00020000U  /* Minimum IFG between frames during transmission is 88Bit */
-  #define ETH_MACCR_IFG_80Bit     0x00040000U  /* Minimum IFG between frames during transmission is 80Bit */
-  #define ETH_MACCR_IFG_72Bit     0x00060000U  /* Minimum IFG between frames during transmission is 72Bit */
-  #define ETH_MACCR_IFG_64Bit     0x00080000U  /* Minimum IFG between frames during transmission is 64Bit */        
-  #define ETH_MACCR_IFG_56Bit     0x000A0000U  /* Minimum IFG between frames during transmission is 56Bit */
-  #define ETH_MACCR_IFG_48Bit     0x000C0000U  /* Minimum IFG between frames during transmission is 48Bit */
-  #define ETH_MACCR_IFG_40Bit     0x000E0000U  /* Minimum IFG between frames during transmission is 40Bit */              
-#define ETH_MACCR_CSD     0x00010000U  /* Carrier sense disable (during transmission) */
-#define ETH_MACCR_FES     0x00004000U  /* Fast ethernet speed */
-#define ETH_MACCR_ROD     0x00002000U  /* Receive own disable */
-#define ETH_MACCR_LM      0x00001000U  /* loopback mode */
-#define ETH_MACCR_DM      0x00000800U  /* Duplex mode */
-#define ETH_MACCR_IPCO    0x00000400U  /* IP Checksum offload */
-#define ETH_MACCR_RD      0x00000200U  /* Retry disable */
-#define ETH_MACCR_APCS    0x00000080U  /* Automatic Pad/CRC stripping */
-#define ETH_MACCR_BL      0x00000060U  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
-                                                       a transmission attempt during retries after a collision: 0 =< r <2^k */
-  #define ETH_MACCR_BL_10    0x00000000U  /* k = min (n, 10) */
-  #define ETH_MACCR_BL_8     0x00000020U  /* k = min (n, 8) */
-  #define ETH_MACCR_BL_4     0x00000040U  /* k = min (n, 4) */
-  #define ETH_MACCR_BL_1     0x00000060U  /* k = min (n, 1) */ 
-#define ETH_MACCR_DC      0x00000010U  /* Defferal check */
-#define ETH_MACCR_TE      0x00000008U  /* Transmitter enable */
-#define ETH_MACCR_RE      0x00000004U  /* Receiver enable */
-
-/* Bit definition for Ethernet MAC Frame Filter Register */
-#define ETH_MACFFR_RA     0x80000000U  /* Receive all */ 
-#define ETH_MACFFR_HPF    0x00000400U  /* Hash or perfect filter */ 
-#define ETH_MACFFR_SAF    0x00000200U  /* Source address filter enable */ 
-#define ETH_MACFFR_SAIF   0x00000100U  /* SA inverse filtering */ 
-#define ETH_MACFFR_PCF    0x000000C0U  /* Pass control frames: 3 cases */
-  #define ETH_MACFFR_PCF_BlockAll                0x00000040U  /* MAC filters all control frames from reaching the application */
-  #define ETH_MACFFR_PCF_ForwardAll              0x00000080U  /* MAC forwards all control frames to application even if they fail the Address Filter */
-  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U  /* MAC forwards control frames that pass the Address Filter. */ 
-#define ETH_MACFFR_BFD    0x00000020U  /* Broadcast frame disable */ 
-#define ETH_MACFFR_PAM    0x00000010U  /* Pass all mutlicast */ 
-#define ETH_MACFFR_DAIF   0x00000008U  /* DA Inverse filtering */ 
-#define ETH_MACFFR_HM     0x00000004U  /* Hash multicast */ 
-#define ETH_MACFFR_HU     0x00000002U  /* Hash unicast */
-#define ETH_MACFFR_PM     0x00000001U  /* Promiscuous mode */
-
-/* Bit definition for Ethernet MAC Hash Table High Register */
-#define ETH_MACHTHR_HTH   0xFFFFFFFFU  /* Hash table high */
-
-/* Bit definition for Ethernet MAC Hash Table Low Register */
-#define ETH_MACHTLR_HTL   0xFFFFFFFFU  /* Hash table low */
-
-/* Bit definition for Ethernet MAC MII Address Register */
-#define ETH_MACMIIAR_PA   0x0000F800U  /* Physical layer address */ 
-#define ETH_MACMIIAR_MR   0x000007C0U  /* MII register in the selected PHY */ 
-#define ETH_MACMIIAR_CR   0x0000001CU  /* CR clock range: 6 cases */ 
-  #define ETH_MACMIIAR_CR_Div42   0x00000000U  /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
-  #define ETH_MACMIIAR_CR_Div62   0x00000004U  /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
-  #define ETH_MACMIIAR_CR_Div16   0x00000008U  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
-  #define ETH_MACMIIAR_CR_Div26   0x0000000CU  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
-  #define ETH_MACMIIAR_CR_Div102  0x00000010U  /* HCLK:150-168 MHz; MDC clock= HCLK/102 */  
-#define ETH_MACMIIAR_MW   0x00000002U  /* MII write */ 
-#define ETH_MACMIIAR_MB   0x00000001U  /* MII busy */ 
-  
-/* Bit definition for Ethernet MAC MII Data Register */
-#define ETH_MACMIIDR_MD   0x0000FFFFU  /* MII data: read/write data from/to PHY */
-
-/* Bit definition for Ethernet MAC Flow Control Register */
-#define ETH_MACFCR_PT     0xFFFF0000U  /* Pause time */
-#define ETH_MACFCR_ZQPD   0x00000080U  /* Zero-quanta pause disable */
-#define ETH_MACFCR_PLT    0x00000030U  /* Pause low threshold: 4 cases */
-  #define ETH_MACFCR_PLT_Minus4   0x00000000U  /* Pause time minus 4 slot times */
-  #define ETH_MACFCR_PLT_Minus28  0x00000010U  /* Pause time minus 28 slot times */
-  #define ETH_MACFCR_PLT_Minus144 0x00000020U  /* Pause time minus 144 slot times */
-  #define ETH_MACFCR_PLT_Minus256 0x00000030U  /* Pause time minus 256 slot times */      
-#define ETH_MACFCR_UPFD   0x00000008U  /* Unicast pause frame detect */
-#define ETH_MACFCR_RFCE   0x00000004U  /* Receive flow control enable */
-#define ETH_MACFCR_TFCE   0x00000002U  /* Transmit flow control enable */
-#define ETH_MACFCR_FCBBPA 0x00000001U  /* Flow control busy/backpressure activate */
-
-/* Bit definition for Ethernet MAC VLAN Tag Register */
-#define ETH_MACVLANTR_VLANTC 0x00010000U  /* 12-bit VLAN tag comparison */
-#define ETH_MACVLANTR_VLANTI 0x0000FFFFU  /* VLAN tag identifier (for receive frames) */
-
-/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ 
-#define ETH_MACRWUFFR_D   0xFFFFFFFFU  /* Wake-up frame filter register data */
-/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
-   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
-/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
-   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
-   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
-   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
-   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - 
-                              RSVD - Filter1 Command - RSVD - Filter0 Command
-   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
-   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
-   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
-
-/* Bit definition for Ethernet MAC PMT Control and Status Register */ 
-#define ETH_MACPMTCSR_WFFRPR 0x80000000U  /* Wake-Up Frame Filter Register Pointer Reset */
-#define ETH_MACPMTCSR_GU     0x00000200U  /* Global Unicast */
-#define ETH_MACPMTCSR_WFR    0x00000040U  /* Wake-Up Frame Received */
-#define ETH_MACPMTCSR_MPR    0x00000020U  /* Magic Packet Received */
-#define ETH_MACPMTCSR_WFE    0x00000004U  /* Wake-Up Frame Enable */
-#define ETH_MACPMTCSR_MPE    0x00000002U  /* Magic Packet Enable */
-#define ETH_MACPMTCSR_PD     0x00000001U  /* Power Down */
-
-/* Bit definition for Ethernet MAC Status Register */
-#define ETH_MACSR_TSTS      0x00000200U  /* Time stamp trigger status */
-#define ETH_MACSR_MMCTS     0x00000040U  /* MMC transmit status */
-#define ETH_MACSR_MMMCRS    0x00000020U  /* MMC receive status */
-#define ETH_MACSR_MMCS      0x00000010U  /* MMC status */
-#define ETH_MACSR_PMTS      0x00000008U  /* PMT status */
-
-/* Bit definition for Ethernet MAC Interrupt Mask Register */
-#define ETH_MACIMR_TSTIM     0x00000200U  /* Time stamp trigger interrupt mask */
-#define ETH_MACIMR_PMTIM     0x00000008U  /* PMT interrupt mask */
-
-/* Bit definition for Ethernet MAC Address0 High Register */
-#define ETH_MACA0HR_MACA0H   0x0000FFFFU  /* MAC address0 high */
-
-/* Bit definition for Ethernet MAC Address0 Low Register */
-#define ETH_MACA0LR_MACA0L   0xFFFFFFFFU  /* MAC address0 low */
-
-/* Bit definition for Ethernet MAC Address1 High Register */
-#define ETH_MACA1HR_AE       0x80000000U  /* Address enable */
-#define ETH_MACA1HR_SA       0x40000000U  /* Source address */
-#define ETH_MACA1HR_MBC      0x3F000000U  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
-  #define ETH_MACA1HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA1HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA1HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA1HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA1HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA1HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [7:0] */ 
-#define ETH_MACA1HR_MACA1H   0x0000FFFFU  /* MAC address1 high */
-
-/* Bit definition for Ethernet MAC Address1 Low Register */
-#define ETH_MACA1LR_MACA1L   0xFFFFFFFFU  /* MAC address1 low */
-
-/* Bit definition for Ethernet MAC Address2 High Register */
-#define ETH_MACA2HR_AE       0x80000000U  /* Address enable */
-#define ETH_MACA2HR_SA       0x40000000U  /* Source address */
-#define ETH_MACA2HR_MBC      0x3F000000U  /* Mask byte control */
-  #define ETH_MACA2HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA2HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA2HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA2HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA2HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA2HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA2HR_MACA2H   0x0000FFFFU  /* MAC address1 high */
-
-/* Bit definition for Ethernet MAC Address2 Low Register */
-#define ETH_MACA2LR_MACA2L   0xFFFFFFFFU  /* MAC address2 low */
-
-/* Bit definition for Ethernet MAC Address3 High Register */
-#define ETH_MACA3HR_AE       0x80000000U  /* Address enable */
-#define ETH_MACA3HR_SA       0x40000000U  /* Source address */
-#define ETH_MACA3HR_MBC      0x3F000000U  /* Mask byte control */
-  #define ETH_MACA3HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA3HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA3HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA3HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA3HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA3HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA3HR_MACA3H   0x0000FFFFU  /* MAC address3 high */
-
-/* Bit definition for Ethernet MAC Address3 Low Register */
-#define ETH_MACA3LR_MACA3L   0xFFFFFFFFU  /* MAC address3 low */
-
-/******************************************************************************/
-/*                Ethernet MMC Registers bits definition                      */
-/******************************************************************************/
-
-/* Bit definition for Ethernet MMC Contol Register */
-#define ETH_MMCCR_MCFHP      0x00000020U  /* MMC counter Full-Half preset */
-#define ETH_MMCCR_MCP        0x00000010U  /* MMC counter preset */
-#define ETH_MMCCR_MCF        0x00000008U  /* MMC Counter Freeze */
-#define ETH_MMCCR_ROR        0x00000004U  /* Reset on Read */
-#define ETH_MMCCR_CSR        0x00000002U  /* Counter Stop Rollover */
-#define ETH_MMCCR_CR         0x00000001U  /* Counters Reset */
-
-/* Bit definition for Ethernet MMC Receive Interrupt Register */
-#define ETH_MMCRIR_RGUFS     0x00020000U  /* Set when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIR_RFAES     0x00000040U  /* Set when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIR_RFCES     0x00000020U  /* Set when Rx crc error counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmit Interrupt Register */
-#define ETH_MMCTIR_TGFS      0x00200000U  /* Set when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFMSCS   0x00008000U  /* Set when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFSCS    0x00004000U  /* Set when Tx good single col counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
-#define ETH_MMCRIMR_RGUFM    0x00020000U  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFAEM    0x00000040U  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFCEM    0x00000020U  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
-#define ETH_MMCTIMR_TGFM     0x00200000U  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFMSCM  0x00008000U  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFSCM   0x00004000U  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
-#define ETH_MMCTGFSCCR_TGFSCC     0xFFFFFFFFU  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
-#define ETH_MMCTGFMSCCR_TGFMSCC   0xFFFFFFFFU  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
-#define ETH_MMCTGFCR_TGFC    0xFFFFFFFFU  /* Number of good frames transmitted. */
-
-/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
-#define ETH_MMCRFCECR_RFCEC  0xFFFFFFFFU  /* Number of frames received with CRC error. */
-
-/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
-#define ETH_MMCRFAECR_RFAEC  0xFFFFFFFFU  /* Number of frames received with alignment (dribble) error */
-
-/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
-#define ETH_MMCRGUFCR_RGUFC  0xFFFFFFFFU  /* Number of good unicast frames received. */
-
-/******************************************************************************/
-/*               Ethernet PTP Registers bits definition                       */
-/******************************************************************************/
-
-/* Bit definition for Ethernet PTP Time Stamp Contol Register */
-#define ETH_PTPTSCR_TSCNT       0x00030000U  /* Time stamp clock node type */
-#define ETH_PTPTSSR_TSSMRME     0x00008000U  /* Time stamp snapshot for message relevant to master enable */
-#define ETH_PTPTSSR_TSSEME      0x00004000U  /* Time stamp snapshot for event message enable */
-#define ETH_PTPTSSR_TSSIPV4FE   0x00002000U  /* Time stamp snapshot for IPv4 frames enable */
-#define ETH_PTPTSSR_TSSIPV6FE   0x00001000U  /* Time stamp snapshot for IPv6 frames enable */
-#define ETH_PTPTSSR_TSSPTPOEFE  0x00000800U  /* Time stamp snapshot for PTP over ethernet frames enable */
-#define ETH_PTPTSSR_TSPTPPSV2E  0x00000400U  /* Time stamp PTP packet snooping for version2 format enable */
-#define ETH_PTPTSSR_TSSSR       0x00000200U  /* Time stamp Sub-seconds rollover */
-#define ETH_PTPTSSR_TSSARFE     0x00000100U  /* Time stamp snapshot for all received frames enable */
-
-#define ETH_PTPTSCR_TSARU    0x00000020U  /* Addend register update */
-#define ETH_PTPTSCR_TSITE    0x00000010U  /* Time stamp interrupt trigger enable */
-#define ETH_PTPTSCR_TSSTU    0x00000008U  /* Time stamp update */
-#define ETH_PTPTSCR_TSSTI    0x00000004U  /* Time stamp initialize */
-#define ETH_PTPTSCR_TSFCU    0x00000002U  /* Time stamp fine or coarse update */
-#define ETH_PTPTSCR_TSE      0x00000001U  /* Time stamp enable */
-
-/* Bit definition for Ethernet PTP Sub-Second Increment Register */
-#define ETH_PTPSSIR_STSSI    0x000000FFU  /* System time Sub-second increment value */
-
-/* Bit definition for Ethernet PTP Time Stamp High Register */
-#define ETH_PTPTSHR_STS      0xFFFFFFFFU  /* System Time second */
-
-/* Bit definition for Ethernet PTP Time Stamp Low Register */
-#define ETH_PTPTSLR_STPNS    0x80000000U  /* System Time Positive or negative time */
-#define ETH_PTPTSLR_STSS     0x7FFFFFFFU  /* System Time sub-seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp High Update Register */
-#define ETH_PTPTSHUR_TSUS    0xFFFFFFFFU  /* Time stamp update seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
-#define ETH_PTPTSLUR_TSUPNS  0x80000000U  /* Time stamp update Positive or negative time */
-#define ETH_PTPTSLUR_TSUSS   0x7FFFFFFFU  /* Time stamp update sub-seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp Addend Register */
-#define ETH_PTPTSAR_TSA      0xFFFFFFFFU  /* Time stamp addend */
-
-/* Bit definition for Ethernet PTP Target Time High Register */
-#define ETH_PTPTTHR_TTSH     0xFFFFFFFFU  /* Target time stamp high */
-
-/* Bit definition for Ethernet PTP Target Time Low Register */
-#define ETH_PTPTTLR_TTSL     0xFFFFFFFFU  /* Target time stamp low */
-
-/* Bit definition for Ethernet PTP Time Stamp Status Register */
-#define ETH_PTPTSSR_TSTTR    0x00000020U  /* Time stamp target time reached */
-#define ETH_PTPTSSR_TSSO     0x00000010U  /* Time stamp seconds overflow */
-
-/******************************************************************************/
-/*                 Ethernet DMA Registers bits definition                     */
-/******************************************************************************/
-
-/* Bit definition for Ethernet DMA Bus Mode Register */
-#define ETH_DMABMR_AAB       0x02000000U  /* Address-Aligned beats */
-#define ETH_DMABMR_FPM        0x01000000U  /* 4xPBL mode */
-#define ETH_DMABMR_USP       0x00800000U  /* Use separate PBL */
-#define ETH_DMABMR_RDP       0x007E0000U  /* RxDMA PBL */
-  #define ETH_DMABMR_RDP_1Beat    0x00020000U  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
-  #define ETH_DMABMR_RDP_2Beat    0x00040000U  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
-  #define ETH_DMABMR_RDP_4Beat    0x00080000U  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-  #define ETH_DMABMR_RDP_8Beat    0x00100000U  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-  #define ETH_DMABMR_RDP_16Beat   0x00200000U  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-  #define ETH_DMABMR_RDP_32Beat   0x00400000U  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */                
-  #define ETH_DMABMR_RDP_4xPBL_4Beat   0x01020000U  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-  #define ETH_DMABMR_RDP_4xPBL_8Beat   0x01040000U  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-  #define ETH_DMABMR_RDP_4xPBL_16Beat  0x01080000U  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-  #define ETH_DMABMR_RDP_4xPBL_32Beat  0x01100000U  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
-  #define ETH_DMABMR_RDP_4xPBL_64Beat  0x01200000U  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
-  #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */  
-#define ETH_DMABMR_FB        0x00010000U  /* Fixed Burst */
-#define ETH_DMABMR_RTPR      0x0000C000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_1_1     0x00000000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_2_1     0x00004000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_3_1     0x00008000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_4_1     0x0000C000U  /* Rx Tx priority ratio */  
-#define ETH_DMABMR_PBL    0x00003F00U  /* Programmable burst length */
-  #define ETH_DMABMR_PBL_1Beat    0x00000100U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
-  #define ETH_DMABMR_PBL_2Beat    0x00000200U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
-  #define ETH_DMABMR_PBL_4Beat    0x00000400U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-  #define ETH_DMABMR_PBL_8Beat    0x00000800U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-  #define ETH_DMABMR_PBL_16Beat   0x00001000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-  #define ETH_DMABMR_PBL_32Beat   0x00002000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
-  #define ETH_DMABMR_PBL_4xPBL_4Beat   0x01000100U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-  #define ETH_DMABMR_PBL_4xPBL_8Beat   0x01000200U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-  #define ETH_DMABMR_PBL_4xPBL_16Beat  0x01000400U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-  #define ETH_DMABMR_PBL_4xPBL_32Beat  0x01000800U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
-  #define ETH_DMABMR_PBL_4xPBL_64Beat  0x01001000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
-  #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
-#define ETH_DMABMR_EDE       0x00000080U  /* Enhanced Descriptor Enable */
-#define ETH_DMABMR_DSL       0x0000007CU  /* Descriptor Skip Length */
-#define ETH_DMABMR_DA        0x00000002U  /* DMA arbitration scheme */
-#define ETH_DMABMR_SR        0x00000001U  /* Software reset */
-
-/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
-#define ETH_DMATPDR_TPD      0xFFFFFFFFU  /* Transmit poll demand */
-
-/* Bit definition for Ethernet DMA Receive Poll Demand Register */
-#define ETH_DMARPDR_RPD      0xFFFFFFFFU  /* Receive poll demand  */
-
-/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
-#define ETH_DMARDLAR_SRL     0xFFFFFFFFU  /* Start of receive list */
-
-/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
-#define ETH_DMATDLAR_STL     0xFFFFFFFFU  /* Start of transmit list */
-
-/* Bit definition for Ethernet DMA Status Register */
-#define ETH_DMASR_TSTS       0x20000000U  /* Time-stamp trigger status */
-#define ETH_DMASR_PMTS       0x10000000U  /* PMT status */
-#define ETH_DMASR_MMCS       0x08000000U  /* MMC status */
-#define ETH_DMASR_EBS        0x03800000U  /* Error bits status */
-  /* combination with EBS[2:0] for GetFlagStatus function */
-  #define ETH_DMASR_EBS_DescAccess      0x02000000U  /* Error bits 0-data buffer, 1-desc. access */
-  #define ETH_DMASR_EBS_ReadTransf      0x01000000U  /* Error bits 0-write trnsf, 1-read transfr */
-  #define ETH_DMASR_EBS_DataTransfTx    0x00800000U  /* Error bits 0-Rx DMA, 1-Tx DMA */
-#define ETH_DMASR_TPS         0x00700000U  /* Transmit process state */
-  #define ETH_DMASR_TPS_Stopped         0x00000000U  /* Stopped - Reset or Stop Tx Command issued  */
-  #define ETH_DMASR_TPS_Fetching        0x00100000U  /* Running - fetching the Tx descriptor */
-  #define ETH_DMASR_TPS_Waiting         0x00200000U  /* Running - waiting for status */
-  #define ETH_DMASR_TPS_Reading         0x00300000U  /* Running - reading the data from host memory */
-  #define ETH_DMASR_TPS_Suspended       0x00600000U  /* Suspended - Tx Descriptor unavailabe */
-  #define ETH_DMASR_TPS_Closing         0x00700000U  /* Running - closing Rx descriptor */
-#define ETH_DMASR_RPS         0x000E0000U  /* Receive process state */
-  #define ETH_DMASR_RPS_Stopped         0x00000000U  /* Stopped - Reset or Stop Rx Command issued */
-  #define ETH_DMASR_RPS_Fetching        0x00020000U  /* Running - fetching the Rx descriptor */
-  #define ETH_DMASR_RPS_Waiting         0x00060000U  /* Running - waiting for packet */
-  #define ETH_DMASR_RPS_Suspended       0x00080000U  /* Suspended - Rx Descriptor unavailable */
-  #define ETH_DMASR_RPS_Closing         0x000A0000U  /* Running - closing descriptor */
-  #define ETH_DMASR_RPS_Queuing         0x000E0000U  /* Running - queuing the recieve frame into host memory */
-#define ETH_DMASR_NIS        0x00010000U  /* Normal interrupt summary */
-#define ETH_DMASR_AIS        0x00008000U  /* Abnormal interrupt summary */
-#define ETH_DMASR_ERS        0x00004000U  /* Early receive status */
-#define ETH_DMASR_FBES       0x00002000U  /* Fatal bus error status */
-#define ETH_DMASR_ETS        0x00000400U  /* Early transmit status */
-#define ETH_DMASR_RWTS       0x00000200U  /* Receive watchdog timeout status */
-#define ETH_DMASR_RPSS       0x00000100U  /* Receive process stopped status */
-#define ETH_DMASR_RBUS       0x00000080U  /* Receive buffer unavailable status */
-#define ETH_DMASR_RS         0x00000040U  /* Receive status */
-#define ETH_DMASR_TUS        0x00000020U  /* Transmit underflow status */
-#define ETH_DMASR_ROS        0x00000010U  /* Receive overflow status */
-#define ETH_DMASR_TJTS       0x00000008U  /* Transmit jabber timeout status */
-#define ETH_DMASR_TBUS       0x00000004U  /* Transmit buffer unavailable status */
-#define ETH_DMASR_TPSS       0x00000002U  /* Transmit process stopped status */
-#define ETH_DMASR_TS         0x00000001U  /* Transmit status */
-
-/* Bit definition for Ethernet DMA Operation Mode Register */
-#define ETH_DMAOMR_DTCEFD    0x04000000U  /* Disable Dropping of TCP/IP checksum error frames */
-#define ETH_DMAOMR_RSF       0x02000000U  /* Receive store and forward */
-#define ETH_DMAOMR_DFRF      0x01000000U  /* Disable flushing of received frames */
-#define ETH_DMAOMR_TSF       0x00200000U  /* Transmit store and forward */
-#define ETH_DMAOMR_FTF       0x00100000U  /* Flush transmit FIFO */
-#define ETH_DMAOMR_TTC       0x0001C000U  /* Transmit threshold control */
-  #define ETH_DMAOMR_TTC_64Bytes       0x00000000U  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
-  #define ETH_DMAOMR_TTC_128Bytes      0x00004000U  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
-  #define ETH_DMAOMR_TTC_192Bytes      0x00008000U  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
-  #define ETH_DMAOMR_TTC_256Bytes      0x0000C000U  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
-  #define ETH_DMAOMR_TTC_40Bytes       0x00010000U  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
-  #define ETH_DMAOMR_TTC_32Bytes       0x00014000U  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
-  #define ETH_DMAOMR_TTC_24Bytes       0x00018000U  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
-  #define ETH_DMAOMR_TTC_16Bytes       0x0001C000U  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
-#define ETH_DMAOMR_ST        0x00002000U  /* Start/stop transmission command */
-#define ETH_DMAOMR_FEF       0x00000080U  /* Forward error frames */
-#define ETH_DMAOMR_FUGF      0x00000040U  /* Forward undersized good frames */
-#define ETH_DMAOMR_RTC       0x00000018U  /* receive threshold control */
-  #define ETH_DMAOMR_RTC_64Bytes       0x00000000U  /* threshold level of the MTL Receive FIFO is 64 Bytes */
-  #define ETH_DMAOMR_RTC_32Bytes       0x00000008U  /* threshold level of the MTL Receive FIFO is 32 Bytes */
-  #define ETH_DMAOMR_RTC_96Bytes       0x00000010U  /* threshold level of the MTL Receive FIFO is 96 Bytes */
-  #define ETH_DMAOMR_RTC_128Bytes      0x00000018U  /* threshold level of the MTL Receive FIFO is 128 Bytes */
-#define ETH_DMAOMR_OSF       0x00000004U  /* operate on second frame */
-#define ETH_DMAOMR_SR        0x00000002U  /* Start/stop receive */
-
-/* Bit definition for Ethernet DMA Interrupt Enable Register */
-#define ETH_DMAIER_NISE      0x00010000U  /* Normal interrupt summary enable */
-#define ETH_DMAIER_AISE      0x00008000U  /* Abnormal interrupt summary enable */
-#define ETH_DMAIER_ERIE      0x00004000U  /* Early receive interrupt enable */
-#define ETH_DMAIER_FBEIE     0x00002000U  /* Fatal bus error interrupt enable */
-#define ETH_DMAIER_ETIE      0x00000400U  /* Early transmit interrupt enable */
-#define ETH_DMAIER_RWTIE     0x00000200U  /* Receive watchdog timeout interrupt enable */
-#define ETH_DMAIER_RPSIE     0x00000100U  /* Receive process stopped interrupt enable */
-#define ETH_DMAIER_RBUIE     0x00000080U  /* Receive buffer unavailable interrupt enable */
-#define ETH_DMAIER_RIE       0x00000040U  /* Receive interrupt enable */
-#define ETH_DMAIER_TUIE      0x00000020U  /* Transmit Underflow interrupt enable */
-#define ETH_DMAIER_ROIE      0x00000010U  /* Receive Overflow interrupt enable */
-#define ETH_DMAIER_TJTIE     0x00000008U  /* Transmit jabber timeout interrupt enable */
-#define ETH_DMAIER_TBUIE     0x00000004U  /* Transmit buffer unavailable interrupt enable */
-#define ETH_DMAIER_TPSIE     0x00000002U  /* Transmit process stopped interrupt enable */
-#define ETH_DMAIER_TIE       0x00000001U  /* Transmit interrupt enable */
-
-/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
-#define ETH_DMAMFBOCR_OFOC   0x10000000U  /* Overflow bit for FIFO overflow counter */
-#define ETH_DMAMFBOCR_MFA    0x0FFE0000U  /* Number of frames missed by the application */
-#define ETH_DMAMFBOCR_OMFC   0x00010000U  /* Overflow bit for missed frame counter */
-#define ETH_DMAMFBOCR_MFC    0x0000FFFFU  /* Number of frames missed by the controller */
-
-/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
-#define ETH_DMACHTDR_HTDAP   0xFFFFFFFFU  /* Host transmit descriptor address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
-#define ETH_DMACHRDR_HRDAP   0xFFFFFFFFU  /* Host receive descriptor address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
-#define ETH_DMACHTBAR_HTBAP  0xFFFFFFFFU  /* Host transmit buffer address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
-#define ETH_DMACHRBAR_HRBAP  0xFFFFFFFFU  /* Host receive buffer address pointer */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                       USB_OTG			                        */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/
-#define USB_OTG_GOTGCTL_SRQSCS                  0x00000001U            /*!< Session request success */
-#define USB_OTG_GOTGCTL_SRQ                     0x00000002U            /*!< Session request */
-#define USB_OTG_GOTGCTL_HNGSCS                  0x00000100U            /*!< Host negotiation success */
-#define USB_OTG_GOTGCTL_HNPRQ                   0x00000200U            /*!< HNP request */
-#define USB_OTG_GOTGCTL_HSHNPEN                 0x00000400U            /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_DHNPEN                  0x00000800U            /*!< Device HNP enabled */
-#define USB_OTG_GOTGCTL_CIDSTS                  0x00010000U            /*!< Connector ID status */
-#define USB_OTG_GOTGCTL_DBCT                    0x00020000U            /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD                   0x00040000U            /*!< A-session valid */
-#define USB_OTG_GOTGCTL_BSVLD                   0x00080000U            /*!< B-session valid */
-
-/********************  Bit definition forUSB_OTG_HCFG register  ********************/
-
-#define USB_OTG_HCFG_FSLSPCS                 0x00000003U            /*!< FS/LS PHY clock select */
-#define USB_OTG_HCFG_FSLSPCS_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCFG_FSLSPCS_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCFG_FSLSS                   0x00000004U            /*!< FS- and LS-only support */
-
-/********************  Bit definition forUSB_OTG_DCFG register  ********************/
-
-#define USB_OTG_DCFG_DSPD                    0x00000003U            /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                  0x00000001U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DSPD_1                  0x00000002U            /*!<Bit 1 */
-#define USB_OTG_DCFG_NZLSOHSK                0x00000004U            /*!< Nonzero-length status OUT handshake */
-
-#define USB_OTG_DCFG_DAD                     0x000007F0U            /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                   0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DAD_1                   0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCFG_DAD_2                   0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCFG_DAD_3                   0x00000080U            /*!<Bit 3 */
-#define USB_OTG_DCFG_DAD_4                   0x00000100U            /*!<Bit 4 */
-#define USB_OTG_DCFG_DAD_5                   0x00000200U            /*!<Bit 5 */
-#define USB_OTG_DCFG_DAD_6                   0x00000400U            /*!<Bit 6 */
-
-#define USB_OTG_DCFG_PFIVL                   0x00001800U            /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PFIVL_1                 0x00001000U            /*!<Bit 1 */
-
-#define USB_OTG_DCFG_PERSCHIVL               0x03000000U            /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0             0x01000000U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PERSCHIVL_1             0x02000000U            /*!<Bit 1 */
-
-/********************  Bit definition forUSB_OTG_PCGCR register  ********************/
-#define USB_OTG_PCGCR_STPPCLK                 0x00000001U            /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK                0x00000002U            /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP                 0x00000010U            /*!< PHY suspended */
-
-/********************  Bit definition forUSB_OTG_GOTGINT register  ********************/
-#define USB_OTG_GOTGINT_SEDET                   0x00000004U            /*!< Session end detected */
-#define USB_OTG_GOTGINT_SRSSCHG                 0x00000100U            /*!< Session request success status change */
-#define USB_OTG_GOTGINT_HNSSCHG                 0x00000200U            /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET                  0x00020000U            /*!< Host negotiation detected */
-#define USB_OTG_GOTGINT_ADTOCHG                 0x00040000U            /*!< A-device timeout change */
-#define USB_OTG_GOTGINT_DBCDNE                  0x00080000U            /*!< Debounce done */
-
-/********************  Bit definition forUSB_OTG_DCTL register  ********************/
-#define USB_OTG_DCTL_RWUSIG                  0x00000001U            /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS                    0x00000002U            /*!< Soft disconnect */
-#define USB_OTG_DCTL_GINSTS                  0x00000004U            /*!< Global IN NAK status */
-#define USB_OTG_DCTL_GONSTS                  0x00000008U            /*!< Global OUT NAK status */
-
-#define USB_OTG_DCTL_TCTL                    0x00000070U            /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                  0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCTL_TCTL_1                  0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCTL_TCTL_2                  0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCTL_SGINAK                  0x00000080U            /*!< Set global IN NAK */
-#define USB_OTG_DCTL_CGINAK                  0x00000100U            /*!< Clear global IN NAK */
-#define USB_OTG_DCTL_SGONAK                  0x00000200U            /*!< Set global OUT NAK */
-#define USB_OTG_DCTL_CGONAK                  0x00000400U            /*!< Clear global OUT NAK */
-#define USB_OTG_DCTL_POPRGDNE                0x00000800U            /*!< Power-on programming done */
-
-/********************  Bit definition forUSB_OTG_HFIR register  ********************/
-#define USB_OTG_HFIR_FRIVL                   0x0000FFFFU            /*!< Frame interval */
-
-/********************  Bit definition forUSB_OTG_HFNUM register  ********************/
-#define USB_OTG_HFNUM_FRNUM                   0x0000FFFFU            /*!< Frame number */
-#define USB_OTG_HFNUM_FTREM                   0xFFFF0000U            /*!< Frame time remaining */
-
-/********************  Bit definition forUSB_OTG_DSTS register  ********************/
-#define USB_OTG_DSTS_SUSPSTS                 0x00000001U            /*!< Suspend status */
-
-#define USB_OTG_DSTS_ENUMSPD                 0x00000006U            /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_DSTS_ENUMSPD_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_DSTS_EERR                    0x00000008U            /*!< Erratic error */
-#define USB_OTG_DSTS_FNSOF                   0x003FFF00U            /*!< Frame number of the received SOF */
-
-/********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/
-#define USB_OTG_GAHBCFG_GINT                    0x00000001U            /*!< Global interrupt mask */
-
-#define USB_OTG_GAHBCFG_HBSTLEN                 0x0000001EU            /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_GAHBCFG_HBSTLEN_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_GAHBCFG_HBSTLEN_2               0x00000008U            /*!<Bit 2 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3               0x00000010U            /*!<Bit 3 */
-#define USB_OTG_GAHBCFG_DMAEN                   0x00000020U            /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL                 0x00000080U            /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL                0x00000100U            /*!< Periodic TxFIFO empty level */
-
-/********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/
-
-#define USB_OTG_GUSBCFG_TOCAL                   0x00000007U            /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TOCAL_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TOCAL_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_PHYSEL                  0x00000040U            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP                  0x00000100U            /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP                  0x00000200U            /*!< HNP-capable */
-
-#define USB_OTG_GUSBCFG_TRDT                    0x00003C00U            /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                  0x00000400U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TRDT_1                  0x00000800U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TRDT_2                  0x00001000U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_TRDT_3                  0x00002000U            /*!<Bit 3 */
-#define USB_OTG_GUSBCFG_PHYLPCS                 0x00008000U            /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS                0x00020000U            /*!< ULPI FS/LS select */
-#define USB_OTG_GUSBCFG_ULPIAR                  0x00040000U            /*!< ULPI Auto-resume */
-#define USB_OTG_GUSBCFG_ULPICSM                 0x00080000U            /*!< ULPI Clock SuspendM */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD              0x00100000U            /*!< ULPI External VBUS Drive */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI              0x00200000U            /*!< ULPI external VBUS indicator */
-#define USB_OTG_GUSBCFG_TSDPS                   0x00400000U            /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI                    0x00800000U            /*!< Indicator complement */
-#define USB_OTG_GUSBCFG_PTCI                    0x01000000U            /*!< Indicator pass through */
-#define USB_OTG_GUSBCFG_ULPIIPD                 0x02000000U            /*!< ULPI interface protect disable */
-#define USB_OTG_GUSBCFG_FHMOD                   0x20000000U            /*!< Forced host mode */
-#define USB_OTG_GUSBCFG_FDMOD                   0x40000000U            /*!< Forced peripheral mode */
-#define USB_OTG_GUSBCFG_CTXPKT                  0x80000000U            /*!< Corrupt Tx packet */
-
-/********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
-#define USB_OTG_GRSTCTL_CSRST                   0x00000001U            /*!< Core soft reset */
-#define USB_OTG_GRSTCTL_HSRST                   0x00000002U            /*!< HCLK soft reset */
-#define USB_OTG_GRSTCTL_FCRST                   0x00000004U            /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH                 0x00000010U            /*!< RxFIFO flush */
-#define USB_OTG_GRSTCTL_TXFFLSH                 0x00000020U            /*!< TxFIFO flush */
-
-#define USB_OTG_GRSTCTL_TXFNUM                  0x000007C0U            /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                0x00000040U            /*!<Bit 0 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                0x00000080U            /*!<Bit 1 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                0x00000100U            /*!<Bit 2 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                0x00000200U            /*!<Bit 3 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                0x00000400U            /*!<Bit 4 */
-#define USB_OTG_GRSTCTL_DMAREQ                  0x40000000U            /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL                  0x80000000U            /*!< AHB master idle */
-
-/********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/
-#define USB_OTG_DIEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPMSK_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPMSK_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPMSK_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPMSK_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPMSK_BIM                     0x00000200U            /*!< BNA interrupt mask */
-
-/********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/
-#define USB_OTG_HPTXSTS_PTXFSAVL                0x0000FFFFU            /*!< Periodic transmit data FIFO space available */
-
-#define USB_OTG_HPTXSTS_PTXQSAV                 0x00FF0000U            /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0               0x00010000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1               0x00020000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2               0x00040000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3               0x00080000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4               0x00100000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5               0x00200000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6               0x00400000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7               0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_HPTXSTS_PTXQTOP                 0xFF000000U            /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0               0x01000000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1               0x02000000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2               0x04000000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3               0x08000000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4               0x10000000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5               0x20000000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6               0x40000000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7               0x80000000U            /*!<Bit 7 */
-
-/********************  Bit definition forUSB_OTG_HAINT register  ********************/
-#define USB_OTG_HAINT_HAINT                   0x0000FFFFU            /*!< Channel interrupts */
-
-/********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/
-#define USB_OTG_DOEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPMSK_STUPM                   0x00000008U            /*!< SETUP phase done mask */
-#define USB_OTG_DOEPMSK_OTEPDM                  0x00000010U            /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received mask */
-#define USB_OTG_DOEPMSK_OPEM                    0x00000100U            /*!< OUT packet error mask */
-#define USB_OTG_DOEPMSK_BOIM                    0x00000200U            /*!< BNA interrupt mask */
-
-/********************  Bit definition forUSB_OTG_GINTSTS register  ********************/
-#define USB_OTG_GINTSTS_CMOD                    0x00000001U            /*!< Current mode of operation */
-#define USB_OTG_GINTSTS_MMIS                    0x00000002U            /*!< Mode mismatch interrupt */
-#define USB_OTG_GINTSTS_OTGINT                  0x00000004U            /*!< OTG interrupt */
-#define USB_OTG_GINTSTS_SOF                     0x00000008U            /*!< Start of frame */
-#define USB_OTG_GINTSTS_RXFLVL                  0x00000010U            /*!< RxFIFO nonempty */
-#define USB_OTG_GINTSTS_NPTXFE                  0x00000020U            /*!< Nonperiodic TxFIFO empty */
-#define USB_OTG_GINTSTS_GINAKEFF                0x00000040U            /*!< Global IN nonperiodic NAK effective */
-#define USB_OTG_GINTSTS_BOUTNAKEFF              0x00000080U            /*!< Global OUT NAK effective */
-#define USB_OTG_GINTSTS_ESUSP                   0x00000400U            /*!< Early suspend */
-#define USB_OTG_GINTSTS_USBSUSP                 0x00000800U            /*!< USB suspend */
-#define USB_OTG_GINTSTS_USBRST                  0x00001000U            /*!< USB reset */
-#define USB_OTG_GINTSTS_ENUMDNE                 0x00002000U            /*!< Enumeration done */
-#define USB_OTG_GINTSTS_ISOODRP                 0x00004000U            /*!< Isochronous OUT packet dropped interrupt */
-#define USB_OTG_GINTSTS_EOPF                    0x00008000U            /*!< End of periodic frame interrupt */
-#define USB_OTG_GINTSTS_IEPINT                  0x00040000U            /*!< IN endpoint interrupt */
-#define USB_OTG_GINTSTS_OEPINT                  0x00080000U            /*!< OUT endpoint interrupt */
-#define USB_OTG_GINTSTS_IISOIXFR                0x00100000U            /*!< Incomplete isochronous IN transfer */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       0x00200000U            /*!< Incomplete periodic transfer */
-#define USB_OTG_GINTSTS_DATAFSUSP               0x00400000U            /*!< Data fetch suspended */
-#define USB_OTG_GINTSTS_HPRTINT                 0x01000000U            /*!< Host port interrupt */
-#define USB_OTG_GINTSTS_HCINT                   0x02000000U            /*!< Host channels interrupt */
-#define USB_OTG_GINTSTS_PTXFE                   0x04000000U            /*!< Periodic TxFIFO empty */
-#define USB_OTG_GINTSTS_CIDSCHG                 0x10000000U            /*!< Connector ID status change */
-#define USB_OTG_GINTSTS_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt */
-#define USB_OTG_GINTSTS_SRQINT                  0x40000000U            /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT                  0x80000000U            /*!< Resume/remote wakeup detected interrupt */
-
-/********************  Bit definition forUSB_OTG_GINTMSK register  ********************/
-#define USB_OTG_GINTMSK_MMISM                   0x00000002U            /*!< Mode mismatch interrupt mask */
-#define USB_OTG_GINTMSK_OTGINT                  0x00000004U            /*!< OTG interrupt mask */
-#define USB_OTG_GINTMSK_SOFM                    0x00000008U            /*!< Start of frame mask */
-#define USB_OTG_GINTMSK_RXFLVLM                 0x00000010U            /*!< Receive FIFO nonempty mask */
-#define USB_OTG_GINTMSK_NPTXFEM                 0x00000020U            /*!< Nonperiodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_GINAKEFFM               0x00000040U            /*!< Global nonperiodic IN NAK effective mask */
-#define USB_OTG_GINTMSK_GONAKEFFM               0x00000080U            /*!< Global OUT NAK effective mask */
-#define USB_OTG_GINTMSK_ESUSPM                  0x00000400U            /*!< Early suspend mask */
-#define USB_OTG_GINTMSK_USBSUSPM                0x00000800U            /*!< USB suspend mask */
-#define USB_OTG_GINTMSK_USBRST                  0x00001000U            /*!< USB reset mask */
-#define USB_OTG_GINTMSK_ENUMDNEM                0x00002000U            /*!< Enumeration done mask */
-#define USB_OTG_GINTMSK_ISOODRPM                0x00004000U            /*!< Isochronous OUT packet dropped interrupt mask */
-#define USB_OTG_GINTMSK_EOPFM                   0x00008000U            /*!< End of periodic frame interrupt mask */
-#define USB_OTG_GINTMSK_EPMISM                  0x00020000U            /*!< Endpoint mismatch interrupt mask */
-#define USB_OTG_GINTMSK_IEPINT                  0x00040000U            /*!< IN endpoints interrupt mask */
-#define USB_OTG_GINTMSK_OEPINT                  0x00080000U            /*!< OUT endpoints interrupt mask */
-#define USB_OTG_GINTMSK_IISOIXFRM               0x00100000U            /*!< Incomplete isochronous IN transfer mask */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         0x00200000U            /*!< Incomplete periodic transfer mask */
-#define USB_OTG_GINTMSK_FSUSPM                  0x00400000U            /*!< Data fetch suspended mask */
-#define USB_OTG_GINTMSK_PRTIM                   0x01000000U            /*!< Host port interrupt mask */
-#define USB_OTG_GINTMSK_HCIM                    0x02000000U            /*!< Host channels interrupt mask */
-#define USB_OTG_GINTMSK_PTXFEM                  0x04000000U            /*!< Periodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_CIDSCHGM                0x10000000U            /*!< Connector ID status change mask */
-#define USB_OTG_GINTMSK_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt mask */
-#define USB_OTG_GINTMSK_SRQIM                   0x40000000U            /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM                    0x80000000U            /*!< Resume/remote wakeup detected interrupt mask */
-
-/********************  Bit definition forUSB_OTG_DAINT register  ********************/
-#define USB_OTG_DAINT_IEPINT                  0x0000FFFFU            /*!< IN endpoint interrupt bits */
-#define USB_OTG_DAINT_OEPINT                  0xFFFF0000U            /*!< OUT endpoint interrupt bits */
-
-/********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/
-#define USB_OTG_HAINTMSK_HAINTM                  0x0000FFFFU            /*!< Channel interrupt mask */
-
-/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
-#define USB_OTG_GRXSTSP_EPNUM                    0x0000000FU            /*!< IN EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_BCNT                     0x00007FF0U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID                     0x00018000U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS                   0x001E0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/
-#define USB_OTG_DAINTMSK_IEPM                    0x0000FFFFU            /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM                    0xFFFF0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for OTG register  ********************/
-
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition for OTG register  ********************/
-
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/
-#define USB_OTG_GRXFSIZ_RXFD                    0x0000FFFFU            /*!< RxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/
-#define USB_OTG_DVBUSDIS_VBUSDT                  0x0000FFFFU            /*!< Device VBUS discharge time */
-
-/********************  Bit definition for OTG register  ********************/
-#define USB_OTG_NPTXFSA                 0x0000FFFFU            /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD                  0xFFFF0000U            /*!< Nonperiodic TxFIFO depth */
-#define USB_OTG_TX0FSA                  0x0000FFFFU            /*!< Endpoint 0 transmit RAM start address */
-#define USB_OTG_TX0FD                   0xFFFF0000U            /*!< Endpoint 0 TxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
-#define USB_OTG_DVBUSPULSE_DVBUSP                  0x00000FFFU            /*!< Device VBUS pulsing time */
-
-/********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/
-#define USB_OTG_GNPTXSTS_NPTXFSAV                0x0000FFFFU            /*!< Nonperiodic TxFIFO space available */
-
-#define USB_OTG_GNPTXSTS_NPTQXSAV                0x00FF0000U            /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0              0x00010000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1              0x00020000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2              0x00040000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3              0x00080000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4              0x00100000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5              0x00200000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6              0x00400000U            /*!<Bit 6 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7              0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_GNPTXSTS_NPTXQTOP                0x7F000000U            /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0              0x01000000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1              0x02000000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2              0x04000000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3              0x08000000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4              0x10000000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5              0x20000000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6              0x40000000U            /*!<Bit 6 */
-
-/********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/
-#define USB_OTG_DTHRCTL_NONISOTHREN             0x00000001U            /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN                0x00000002U            /*!< ISO IN endpoint threshold enable */
-
-#define USB_OTG_DTHRCTL_TXTHRLEN                0x000007FCU            /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0              0x00000004U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1              0x00000008U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2              0x00000010U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3              0x00000020U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4              0x00000040U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5              0x00000080U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6              0x00000100U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7              0x00000200U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8              0x00000400U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_RXTHREN                 0x00010000U            /*!< Receive threshold enable */
-
-#define USB_OTG_DTHRCTL_RXTHRLEN                0x03FE0000U            /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0              0x00020000U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1              0x00040000U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2              0x00080000U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3              0x00100000U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4              0x00200000U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5              0x00400000U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6              0x00800000U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7              0x01000000U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8              0x02000000U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_ARPEN                   0x08000000U            /*!< Arbiter parking enable */
-
-/********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM               0x0000FFFFU            /*!< IN EP Tx FIFO empty interrupt mask bits */
-
-/********************  Bit definition forUSB_OTG_DEACHINT register  ********************/
-#define USB_OTG_DEACHINT_IEP1INT                 0x00000002U            /*!< IN endpoint 1interrupt bit */
-#define USB_OTG_DEACHINT_OEP1INT                 0x00020000U            /*!< OUT endpoint 1 interrupt bit */
-
-/********************  Bit definition forUSB_OTG_GCCFG register  ********************/
-#define USB_OTG_GCCFG_PWRDWN                  0x00010000U            /*!< Power down */
-#define USB_OTG_GCCFG_I2CPADEN                0x00020000U            /*!< Enable I2C bus connection for the external I2C PHY interface */
-#define USB_OTG_GCCFG_VBUSASEN                0x00040000U            /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_VBUSBSEN                0x00080000U            /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_SOFOUTEN                0x00100000U            /*!< SOF output enable */
-#define USB_OTG_GCCFG_NOVBUSSENS              0x00200000U            /*!< VBUS sensing disable option */
-
-/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
-#define USB_OTG_DEACHINTMSK_IEP1INTM                0x00000002U            /*!< IN Endpoint 1 interrupt mask bit */
-#define USB_OTG_DEACHINTMSK_OEP1INTM                0x00020000U            /*!< OUT Endpoint 1 interrupt mask bit */
-
-/********************  Bit definition forUSB_OTG_CID register  ********************/
-#define USB_OTG_CID_PRODUCT_ID              0xFFFFFFFFU            /*!< Product ID field */
-
-/********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/
-#define USB_OTG_DIEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPEACHMSK1_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
-
-/********************  Bit definition forUSB_OTG_HPRT register  ********************/
-#define USB_OTG_HPRT_PCSTS                   0x00000001U            /*!< Port connect status */
-#define USB_OTG_HPRT_PCDET                   0x00000002U            /*!< Port connect detected */
-#define USB_OTG_HPRT_PENA                    0x00000004U            /*!< Port enable */
-#define USB_OTG_HPRT_PENCHNG                 0x00000008U            /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA                    0x00000010U            /*!< Port overcurrent active */
-#define USB_OTG_HPRT_POCCHNG                 0x00000020U            /*!< Port overcurrent change */
-#define USB_OTG_HPRT_PRES                    0x00000040U            /*!< Port resume */
-#define USB_OTG_HPRT_PSUSP                   0x00000080U            /*!< Port suspend */
-#define USB_OTG_HPRT_PRST                    0x00000100U            /*!< Port reset */
-
-#define USB_OTG_HPRT_PLSTS                   0x00000C00U            /*!< Port line status */
-#define USB_OTG_HPRT_PLSTS_0                 0x00000400U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PLSTS_1                 0x00000800U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PPWR                    0x00001000U            /*!< Port power */
-
-#define USB_OTG_HPRT_PTCTL                   0x0001E000U            /*!< Port test control */
-#define USB_OTG_HPRT_PTCTL_0                 0x00002000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PTCTL_1                 0x00004000U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PTCTL_2                 0x00008000U            /*!<Bit 2 */
-#define USB_OTG_HPRT_PTCTL_3                 0x00010000U            /*!<Bit 3 */
-
-#define USB_OTG_HPRT_PSPD                    0x00060000U            /*!< Port speed */
-#define USB_OTG_HPRT_PSPD_0                  0x00020000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PSPD_1                  0x00040000U            /*!<Bit 1 */
-
-/********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/
-#define USB_OTG_DOEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DOEPEACHMSK1_TXFURM                  0x00000100U            /*!< OUT packet error mask */
-#define USB_OTG_DOEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_BERRM                   0x00001000U            /*!< Bubble error interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NYETM                   0x00004000U            /*!< NYET interrupt mask */
-
-/********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/
-#define USB_OTG_HPTXFSIZ_PTXSA                   0x0000FFFFU            /*!< Host periodic TxFIFO start address */
-#define USB_OTG_HPTXFSIZ_PTXFD                   0xFFFF0000U            /*!< Host periodic TxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/
-#define USB_OTG_DIEPCTL_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
-#define USB_OTG_DIEPCTL_USBAEP                  0x00008000U            /*!< USB active endpoint */
-#define USB_OTG_DIEPCTL_EONUM_DPID              0x00010000U            /*!< Even/odd frame */
-#define USB_OTG_DIEPCTL_NAKSTS                  0x00020000U            /*!< NAK status */
-
-#define USB_OTG_DIEPCTL_EPTYP                   0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_DIEPCTL_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_STALL                   0x00200000U            /*!< STALL handshake */
-
-#define USB_OTG_DIEPCTL_TXFNUM                  0x03C00000U            /*!< TxFIFO number */
-#define USB_OTG_DIEPCTL_TXFNUM_0                0x00400000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                0x00800000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                0x01000000U            /*!<Bit 2 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                0x02000000U            /*!<Bit 3 */
-#define USB_OTG_DIEPCTL_CNAK                    0x04000000U            /*!< Clear NAK */
-#define USB_OTG_DIEPCTL_SNAK                    0x08000000U            /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          0x10000000U            /*!< Set DATA0 PID */
-#define USB_OTG_DIEPCTL_SODDFRM                 0x20000000U            /*!< Set odd frame */
-#define USB_OTG_DIEPCTL_EPDIS                   0x40000000U            /*!< Endpoint disable */
-#define USB_OTG_DIEPCTL_EPENA                   0x80000000U            /*!< Endpoint enable */
-
-/********************  Bit definition forUSB_OTG_HCCHAR register  ********************/
-#define USB_OTG_HCCHAR_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
-
-#define USB_OTG_HCCHAR_EPNUM                   0x00007800U            /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPNUM_1                 0x00001000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_EPNUM_2                 0x00002000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_EPNUM_3                 0x00004000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_EPDIR                   0x00008000U            /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV                   0x00020000U            /*!< Low-speed device */
-
-#define USB_OTG_HCCHAR_EPTYP                   0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_MC                      0x00300000U            /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                    0x00100000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_MC_1                    0x00200000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_DAD                     0x1FC00000U            /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                   0x00400000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_DAD_1                   0x00800000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_DAD_2                   0x01000000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_DAD_3                   0x02000000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_DAD_4                   0x04000000U            /*!<Bit 4 */
-#define USB_OTG_HCCHAR_DAD_5                   0x08000000U            /*!<Bit 5 */
-#define USB_OTG_HCCHAR_DAD_6                   0x10000000U            /*!<Bit 6 */
-#define USB_OTG_HCCHAR_ODDFRM                  0x20000000U            /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS                   0x40000000U            /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA                   0x80000000U            /*!< Channel enable */
-
-/********************  Bit definition forUSB_OTG_HCSPLT register  ********************/
-
-#define USB_OTG_HCSPLT_PRTADDR                 0x0000007FU            /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_PRTADDR_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_PRTADDR_2               0x00000004U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_PRTADDR_3               0x00000008U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_PRTADDR_4               0x00000010U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_PRTADDR_5               0x00000020U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_PRTADDR_6               0x00000040U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_HUBADDR                 0x00003F80U            /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0               0x00000080U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_HUBADDR_1               0x00000100U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_HUBADDR_2               0x00000200U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_HUBADDR_3               0x00000400U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_HUBADDR_4               0x00000800U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_HUBADDR_5               0x00001000U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_HUBADDR_6               0x00002000U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_XACTPOS                 0x0000C000U            /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0               0x00004000U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_XACTPOS_1               0x00008000U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_COMPLSPLT               0x00010000U            /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN                 0x80000000U            /*!< Split enable */
-
-/********************  Bit definition forUSB_OTG_HCINT register  ********************/
-#define USB_OTG_HCINT_XFRC                    0x00000001U            /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH                     0x00000002U            /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINT_STALL                   0x00000008U            /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK                     0x00000010U            /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK                     0x00000020U            /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET                    0x00000040U            /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR                   0x00000080U            /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR                   0x00000100U            /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR                   0x00000200U            /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR                   0x00000400U            /*!< Data toggle error */
-
-/********************  Bit definition forUSB_OTG_DIEPINT register  ********************/
-#define USB_OTG_DIEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_TOC                     0x00000008U            /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE                  0x00000010U            /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNE                  0x00000040U            /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE                    0x00000080U            /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN              0x00000100U            /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA                     0x00000200U            /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS               0x00000800U            /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR                    0x00001000U            /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK                     0x00002000U            /*!< NAK interrupt */
-
-/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
-#define USB_OTG_HCINTMSK_XFRCM                   0x00000001U            /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM                    0x00000002U            /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM                  0x00000008U            /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM                    0x00000010U            /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM                    0x00000020U            /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET                    0x00000040U            /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM                  0x00000080U            /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM                  0x00000100U            /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM                  0x00000200U            /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM                  0x00000400U            /*!< Data toggle error mask */
-
-/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
-
-#define USB_OTG_DIEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT                  0x60000000U            /*!< Packet count */
-/********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/
-#define USB_OTG_HCTSIZ_XFRSIZ                    0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT                    0x1FF80000U            /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING                    0x80000000U            /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID                      0x60000000U            /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                    0x20000000U            /*!<Bit 0 */
-#define USB_OTG_HCTSIZ_DPID_1                    0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/
-#define USB_OTG_DIEPDMA_DMAADDR                  0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition forUSB_OTG_HCDMA register  ********************/
-#define USB_OTG_HCDMA_DMAADDR                    0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/
-#define USB_OTG_DTXFSTS_INEPTFSAV                0x0000FFFFU            /*!< IN endpoint TxFIFO space avail */
-
-/********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/
-#define USB_OTG_DIEPTXF_INEPTXSA                 0x0000FFFFU            /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD                 0xFFFF0000U            /*!< IN endpoint TxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/
-
-#define USB_OTG_DOEPCTL_MPSIZ                     0x000007FFU            /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP                    0x00008000U            /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS                    0x00020000U            /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            0x10000000U            /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM                   0x20000000U            /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP                     0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                   0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DOEPCTL_EPTYP_1                   0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_SNPM                      0x00100000U            /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL                     0x00200000U            /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK                      0x04000000U            /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK                      0x08000000U            /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS                     0x40000000U            /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA                     0x80000000U            /*!< Endpoint enable */
-
-/********************  Bit definition forUSB_OTG_DOEPINT register  ********************/
-#define USB_OTG_DOEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_STUP                    0x00000008U            /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS                 0x00000010U            /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_NYET                    0x00004000U            /*!< NYET interrupt */
-
-/********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/
-
-#define USB_OTG_DOEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-
-#define USB_OTG_DOEPTSIZ_STUPCNT                 0x60000000U            /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0               0x20000000U            /*!<Bit 0 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1               0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition for PCGCCTL register  ********************/
-#define USB_OTG_PCGCCTL_STOPCLK                 0x00000001U            /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK                 0x00000002U            /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP                 0x00000010U            /*!<Bit 1 */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
- 
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
-                                       ((INSTANCE) == ADC2) || \
-                                       ((INSTANCE) == ADC3))
-
-/******************************* CAN Instances ********************************/
-#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
-                                       ((INSTANCE) == CAN2))
- 
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DAC Instances ********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/******************************* DCMI Instances *******************************/
-#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
-
-/******************************** DMA Instances *******************************/
-#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
-                                              ((INSTANCE) == DMA1_Stream1) || \
-                                              ((INSTANCE) == DMA1_Stream2) || \
-                                              ((INSTANCE) == DMA1_Stream3) || \
-                                              ((INSTANCE) == DMA1_Stream4) || \
-                                              ((INSTANCE) == DMA1_Stream5) || \
-                                              ((INSTANCE) == DMA1_Stream6) || \
-                                              ((INSTANCE) == DMA1_Stream7) || \
-                                              ((INSTANCE) == DMA2_Stream0) || \
-                                              ((INSTANCE) == DMA2_Stream1) || \
-                                              ((INSTANCE) == DMA2_Stream2) || \
-                                              ((INSTANCE) == DMA2_Stream3) || \
-                                              ((INSTANCE) == DMA2_Stream4) || \
-                                              ((INSTANCE) == DMA2_Stream5) || \
-                                              ((INSTANCE) == DMA2_Stream6) || \
-                                              ((INSTANCE) == DMA2_Stream7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOF) || \
-                                        ((INSTANCE) == GPIOG) || \
-                                        ((INSTANCE) == GPIOH) || \
-                                        ((INSTANCE) == GPIOI))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2) || \
-                                       ((INSTANCE) == I2C3))
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI2) || \
-                                        ((INSTANCE) == SPI3))
-
-/*************************** I2S Extended Instances ***************************/
-#define IS_I2S_ALL_INSTANCE_EXT(PERIPH)  (((INSTANCE) == SPI2)    || \
-                                          ((INSTANCE) == SPI3)    || \
-                                          ((INSTANCE) == I2S2ext) || \
-                                          ((INSTANCE) == I2S3ext))
-
-/******************************* RNG Instances ********************************/
-#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-
-/*************************** SPI Extended Instances ***************************/
-#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1)    || \
-                                           ((INSTANCE) == SPI2)    || \
-                                           ((INSTANCE) == SPI3)    || \
-                                           ((INSTANCE) == I2S2ext) || \
-                                           ((INSTANCE) == I2S3ext))
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
-                                   ((INSTANCE) == TIM2)   || \
-                                   ((INSTANCE) == TIM3)   || \
-                                   ((INSTANCE) == TIM4)   || \
-                                   ((INSTANCE) == TIM5)   || \
-                                   ((INSTANCE) == TIM6)   || \
-                                   ((INSTANCE) == TIM7)   || \
-                                   ((INSTANCE) == TIM8)   || \
-                                   ((INSTANCE) == TIM9)   || \
-                                   ((INSTANCE) == TIM10)  || \
-                                   ((INSTANCE) == TIM11)  || \
-                                   ((INSTANCE) == TIM12)  || \
-                                   ((INSTANCE) == TIM13)  || \
-                                   ((INSTANCE) == TIM14))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
-                                         ((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM8)  || \
-                                         ((INSTANCE) == TIM9)  || \
-                                         ((INSTANCE) == TIM10) || \
-                                         ((INSTANCE) == TIM11) || \
-                                         ((INSTANCE) == TIM12) || \
-                                         ((INSTANCE) == TIM13) || \
-                                         ((INSTANCE) == TIM14))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM8) || \
-                                       ((INSTANCE) == TIM9) || \
-                                       ((INSTANCE) == TIM12))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8))
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM8))
-
-/******************** TIM Instances : Advanced-control timers *****************/
-#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                            ((INSTANCE) == TIM8))
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8))
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM6) || \
-                                       ((INSTANCE) == TIM7) || \
-                                       ((INSTANCE) == TIM8))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM8))
-
-/************ TIM Instances : DMA requests generation (COMDE) *****************/
-#define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM8)) 
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                             ((INSTANCE) == TIM2) || \
-                                             ((INSTANCE) == TIM3) || \
-                                             ((INSTANCE) == TIM4) || \
-                                             ((INSTANCE) == TIM5) || \
-                                             ((INSTANCE) == TIM8))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM6) || \
-                                          ((INSTANCE) == TIM7) || \
-                                          ((INSTANCE) == TIM8) || \
-                                          ((INSTANCE) == TIM9) || \
-                                          ((INSTANCE) == TIM12))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8) || \
-                                         ((INSTANCE) == TIM9) || \
-                                         ((INSTANCE) == TIM12))
-
-/********************** TIM Instances : 32 bit Counter ************************/
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
-                                              ((INSTANCE) == TIM5))
-
-/***************** TIM Instances : external trigger input availabe ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                        ((INSTANCE) == TIM2) || \
-                                        ((INSTANCE) == TIM3) || \
-                                        ((INSTANCE) == TIM4) || \
-                                        ((INSTANCE) == TIM5) || \
-                                        ((INSTANCE) == TIM8))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM11))
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM1) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM5) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM8) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM12) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM13) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM14) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-/************ TIM Instances : complementary output(s) available ***************/
-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
-   ((((INSTANCE) == TIM1) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3)))            \
-    ||                                          \
-    (((INSTANCE) == TIM8) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3))))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3) || \
-                                     ((INSTANCE) == USART6))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5)  || \
-                                    ((INSTANCE) == USART6))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3) || \
-                                           ((INSTANCE) == USART6))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3) || \
-                                         ((INSTANCE) == USART6))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5)  || \
-                                    ((INSTANCE) == USART6))     
-
-/*********************** PCD Instances ****************************************/
-/*********************** PCD Instances ****************************************/
-#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
-                                        ((INSTANCE) == USB_OTG_HS))
-
-/*********************** HCD Instances ****************************************/
-#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
-                                       ((INSTANCE) == USB_OTG_HS))
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/****************************** SDIO Instances ********************************/
-#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
-
-/****************************** USB Exported Constants ************************/
-#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                8U
-#define USB_OTG_FS_MAX_IN_ENDPOINTS                    4U    /* Including EP0 */
-#define USB_OTG_FS_MAX_OUT_ENDPOINTS                   4U    /* Including EP0 */
-#define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */
-
-#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR                12U
-#define USB_OTG_HS_MAX_IN_ENDPOINTS                    6U    /* Including EP0 */
-#define USB_OTG_HS_MAX_OUT_ENDPOINTS                   6U    /* Including EP0 */
-#define USB_OTG_HS_TOTAL_FIFO_SIZE                     4096U /* in Bytes */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32F4xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */
-/*  product lines within the same STM32F4 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-#define FMC_IRQn              FSMC_IRQn
-
-/* Aliases for __IRQHandler */
-#define FMC_IRQHandler        FSMC_IRQHandler
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32F4xx_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/cmsis/stm32f427xx.h b/stmhal/cmsis/stm32f427xx.h
deleted file mode 100644
index ab6fc244fa..0000000000
--- a/stmhal/cmsis/stm32f427xx.h
+++ /dev/null
@@ -1,8901 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f427xx.h
-  * @author  MCD Application Team
-  * @version V2.5.1
-  * @date    28-June-2016
-  * @brief   CMSIS STM32F427xx Device Peripheral Access Layer Header File.
-  *
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - peripherals registers declarations and bits definition
-  *           - Macros to access peripheral’s registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS_Device
-  * @{
-  */
-
-/** @addtogroup stm32f427xx
-  * @{
-  */
-    
-#ifndef __stm32f427xx_H
-#define __stm32f427xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-  
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-
-/**
-  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
-  */
-#define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */
-#define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */
-#define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1U       /*!< FPU present                                   */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32F4XX Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-typedef enum
-{
-/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
-  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
-/******  STM32 specific Interrupt Numbers **********************************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
-  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
-  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
-  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
-  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
-  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
-  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
-  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
-  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
-  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
-  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
-  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
-  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
-  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
-  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
-  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
-  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
-  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */    
-  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
-  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
-  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
-  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
-  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
-  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
-  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
-  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
-  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
-  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
-  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
-  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
-  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
-  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
-  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
-  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
-  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
-  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
-  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
-  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
-  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
-  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
-  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
-  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
-  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
-  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
-  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
-  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
-  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
-  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
-  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
-  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
-  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
-  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
-  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
-  HASH_RNG_IRQn               = 80,     /*!< Hash and RNG global interrupt                                     */
-  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
-  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */
-  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */
-  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
-  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */
-  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */
-  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
-  DMA2D_IRQn                  = 90      /*!< DMA2D global Interrupt                                            */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
-#include "system_stm32f4xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */      
-  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
-  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
-  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
-  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
-  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
-  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
-  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
-  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
-  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
-  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
-  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
-  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
-  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
-  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
-  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
-                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
-} ADC_Common_TypeDef;
-
-
-/** 
-  * @brief Controller Area Network TxMailBox 
-  */
-
-typedef struct
-{
-  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
-  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
-  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
-  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
-} CAN_TxMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FIFOMailBox 
-  */
-  
-typedef struct
-{
-  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
-  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
-  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
-  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
-} CAN_FIFOMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FilterRegister 
-  */
-  
-typedef struct
-{
-  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
-  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
-} CAN_FilterRegister_TypeDef;
-
-/** 
-  * @brief Controller Area Network 
-  */
-  
-typedef struct
-{
-  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
-  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
-  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
-  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
-  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
-  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
-  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
-  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
-  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
-  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
-  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
-  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
-  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
-  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
-  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
-  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
-  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
-  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
-  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
-  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
-  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */ 
-  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
-} CAN_TypeDef;
-
-/** 
-  * @brief CRC calculation unit 
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
-  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */
-  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
-  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
-  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
-  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
-  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
-  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
-  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
-  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
-  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
-  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
-  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
-  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
-  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
-  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
-  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
-  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
-  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
-  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DCMI
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
-  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
-  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
-  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
-  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
-  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
-  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
-  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
-  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
-  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
-  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
-} DCMI_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
-  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
-  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
-  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
-  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
-  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
-} DMA_Stream_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
-  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
-  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
-  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
-} DMA_TypeDef;
-
-/** 
-  * @brief DMA2D Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
-  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
-  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
-  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
-  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
-  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
-  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
-  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
-  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
-  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
-  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
-  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
-  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
-  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
-  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
-  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
-  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
-  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
-  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
-  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
-  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
-  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */
-  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */
-} DMA2D_TypeDef;
-
-/** 
-  * @brief Ethernet MAC
-  */
-
-typedef struct
-{
-  __IO uint32_t MACCR;
-  __IO uint32_t MACFFR;
-  __IO uint32_t MACHTHR;
-  __IO uint32_t MACHTLR;
-  __IO uint32_t MACMIIAR;
-  __IO uint32_t MACMIIDR;
-  __IO uint32_t MACFCR;
-  __IO uint32_t MACVLANTR;             /*    8 */
-  uint32_t      RESERVED0[2];
-  __IO uint32_t MACRWUFFR;             /*   11 */
-  __IO uint32_t MACPMTCSR;
-  uint32_t      RESERVED1[2];
-  __IO uint32_t MACSR;                 /*   15 */
-  __IO uint32_t MACIMR;
-  __IO uint32_t MACA0HR;
-  __IO uint32_t MACA0LR;
-  __IO uint32_t MACA1HR;
-  __IO uint32_t MACA1LR;
-  __IO uint32_t MACA2HR;
-  __IO uint32_t MACA2LR;
-  __IO uint32_t MACA3HR;
-  __IO uint32_t MACA3LR;               /*   24 */
-  uint32_t      RESERVED2[40];
-  __IO uint32_t MMCCR;                 /*   65 */
-  __IO uint32_t MMCRIR;
-  __IO uint32_t MMCTIR;
-  __IO uint32_t MMCRIMR;
-  __IO uint32_t MMCTIMR;               /*   69 */
-  uint32_t      RESERVED3[14];
-  __IO uint32_t MMCTGFSCCR;            /*   84 */
-  __IO uint32_t MMCTGFMSCCR;
-  uint32_t      RESERVED4[5];
-  __IO uint32_t MMCTGFCR;
-  uint32_t      RESERVED5[10];
-  __IO uint32_t MMCRFCECR;
-  __IO uint32_t MMCRFAECR;
-  uint32_t      RESERVED6[10];
-  __IO uint32_t MMCRGUFCR;
-  uint32_t      RESERVED7[334];
-  __IO uint32_t PTPTSCR;
-  __IO uint32_t PTPSSIR;
-  __IO uint32_t PTPTSHR;
-  __IO uint32_t PTPTSLR;
-  __IO uint32_t PTPTSHUR;
-  __IO uint32_t PTPTSLUR;
-  __IO uint32_t PTPTSAR;
-  __IO uint32_t PTPTTHR;
-  __IO uint32_t PTPTTLR;
-  __IO uint32_t RESERVED8;
-  __IO uint32_t PTPTSSR;
-  uint32_t      RESERVED9[565];
-  __IO uint32_t DMABMR;
-  __IO uint32_t DMATPDR;
-  __IO uint32_t DMARPDR;
-  __IO uint32_t DMARDLAR;
-  __IO uint32_t DMATDLAR;
-  __IO uint32_t DMASR;
-  __IO uint32_t DMAOMR;
-  __IO uint32_t DMAIER;
-  __IO uint32_t DMAMFBOCR;
-  __IO uint32_t DMARSWTR;
-  uint32_t      RESERVED10[8];
-  __IO uint32_t DMACHTDR;
-  __IO uint32_t DMACHRDR;
-  __IO uint32_t DMACHTBAR;
-  __IO uint32_t DMACHRBAR;
-} ETH_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
-  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
-  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
-  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
-  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
-  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-
-typedef struct
-{
-  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */
-  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */
-  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */
-  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */
-  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */
-  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief Flexible Memory Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */   
-} FMC_Bank1_TypeDef; 
-
-/** 
-  * @brief Flexible Memory Controller Bank1E
-  */
-  
-typedef struct
-{
-  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
-} FMC_Bank1E_TypeDef;
-
-/** 
-  * @brief Flexible Memory Controller Bank2
-  */
-  
-typedef struct
-{
-  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */
-  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */
-  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */
-  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
-  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */
-  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */
-  uint32_t      RESERVED1;  /*!< Reserved, 0x78                                                            */
-  uint32_t      RESERVED2;  /*!< Reserved, 0x7C                                                            */
-  __IO uint32_t PCR3;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */
-  __IO uint32_t SR3;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */
-  __IO uint32_t PMEM3;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */
-  __IO uint32_t PATT3;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
-  uint32_t      RESERVED3;  /*!< Reserved, 0x90                                                            */
-  __IO uint32_t ECCR3;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */
-} FMC_Bank2_3_TypeDef;
-
-/** 
-  * @brief Flexible Memory Controller Bank4
-  */
-  
-typedef struct
-{
-  __IO uint32_t PCR4;       /*!< PC Card  control register 4,                       Address offset: 0xA0 */
-  __IO uint32_t SR4;        /*!< PC Card  FIFO status and interrupt register 4,     Address offset: 0xA4 */
-  __IO uint32_t PMEM4;      /*!< PC Card  Common memory space timing register 4,    Address offset: 0xA8 */
-  __IO uint32_t PATT4;      /*!< PC Card  Attribute memory space timing register 4, Address offset: 0xAC */
-  __IO uint32_t PIO4;       /*!< PC Card  I/O space timing register 4,              Address offset: 0xB0 */
-} FMC_Bank4_TypeDef; 
-
-/** 
-  * @brief Flexible Memory Controller Bank5_6
-  */
-  
-typedef struct
-{
-  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */
-  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */
-  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */
-  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */
-  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */
-} FMC_Bank5_6_TypeDef; 
-
-/** 
-  * @brief General Purpose I/O
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
-  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
-  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
-  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
-  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
-  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
-  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
-  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/** 
-  * @brief System configuration controller
-  */
-  
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */ 
-  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */
-  __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */
-  __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */
-  __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */
-  __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */
-  __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
-  __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
-  __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
-  __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
-  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
-  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
-  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
-  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
-  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
-  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
-  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
-  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
-  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
-  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
-  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
-  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
-  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
-  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
-  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
-  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
-  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
-  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
-  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
-  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
-  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
-  __IO uint32_t PLLSAICFGR;    /*!< RCC PLLSAI configuration register,                           Address offset: 0x88 */
-  __IO uint32_t DCKCFGR;       /*!< RCC Dedicated Clocks configuration register,                 Address offset: 0x8C */
-
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-
-typedef struct
-{
-  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
-  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
-  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
-  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
-  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
-  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
-  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */
-  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
-  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */
-  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
-  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */
-  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */
-  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */
-  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */
-  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
-  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */
-  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
-  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
-  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
-  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
-  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
-  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
-  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
-  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
-  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
-  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
-  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
-  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
-  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
-  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
-  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
-  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
-  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
-  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
-  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
-  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
-  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
-} RTC_TypeDef;
-
-/** 
-  * @brief Serial Audio Interface
-  */
-  
-typedef struct
-{
-  __IO uint32_t GCR;      /*!< SAI global configuration register,        Address offset: 0x00 */
-} SAI_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */
-  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */
-  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */
-  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */
-  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
-  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */
-  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */
-  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */
-} SAI_Block_TypeDef;
-
-/** 
-  * @brief SD host Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t POWER;          /*!< SDIO power control register,    Address offset: 0x00 */
-  __IO uint32_t CLKCR;          /*!< SDI clock control register,     Address offset: 0x04 */
-  __IO uint32_t ARG;            /*!< SDIO argument register,         Address offset: 0x08 */
-  __IO uint32_t CMD;            /*!< SDIO command register,          Address offset: 0x0C */
-  __I uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */
-  __I uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */
-  __I uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */
-  __I uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */
-  __I uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */
-  __IO uint32_t DTIMER;         /*!< SDIO data timer register,       Address offset: 0x24 */
-  __IO uint32_t DLEN;           /*!< SDIO data length register,      Address offset: 0x28 */
-  __IO uint32_t DCTRL;          /*!< SDIO data control register,     Address offset: 0x2C */
-  __I uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */
-  __I uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */
-  __IO uint32_t ICR;            /*!< SDIO interrupt clear register,  Address offset: 0x38 */
-  __IO uint32_t MASK;           /*!< SDIO mask register,             Address offset: 0x3C */
-  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
-  __I uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */
-  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
-  __IO uint32_t FIFO;           /*!< SDIO data FIFO register,        Address offset: 0x80 */
-} SDIO_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
-  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
-  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
-  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-
-/** 
-  * @brief RNG
-  */
-  
-typedef struct 
-{
-  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
-  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
-  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
-} RNG_TypeDef;
-
- 
-/** 
-  * @brief __USB_OTG_Core_register
-  */
-typedef struct
-{
-  __IO uint32_t GOTGCTL;      /*!<  USB_OTG Control and Status Register    000h */
-  __IO uint32_t GOTGINT;      /*!<  USB_OTG Interrupt Register             004h */
-  __IO uint32_t GAHBCFG;      /*!<  Core AHB Configuration Register        008h */
-  __IO uint32_t GUSBCFG;      /*!<  Core USB Configuration Register        00Ch */
-  __IO uint32_t GRSTCTL;      /*!<  Core Reset Register                    010h */
-  __IO uint32_t GINTSTS;      /*!<  Core Interrupt Register                014h */
-  __IO uint32_t GINTMSK;      /*!<  Core Interrupt Mask Register           018h */
-  __IO uint32_t GRXSTSR;      /*!<  Receive Sts Q Read Register            01Ch */
-  __IO uint32_t GRXSTSP;      /*!<  Receive Sts Q Read & POP Register      020h */
-  __IO uint32_t GRXFSIZ;      /* Receive FIFO Size Register                024h */
-  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!<  EP0 / Non Periodic Tx FIFO Size Register 028h*/
-  __IO uint32_t HNPTXSTS;     /*!<  Non Periodic Tx FIFO/Queue Sts reg     02Ch */
-  uint32_t Reserved30[2];     /* Reserved                           030h*/
-  __IO uint32_t GCCFG;        /* General Purpose IO Register        038h*/
-  __IO uint32_t CID;          /* User ID Register                   03Ch*/
-  uint32_t  Reserved40[48];   /* Reserved                      040h-0FFh*/
-  __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg     100h*/
-  __IO uint32_t DIEPTXF[0x0F];/* dev Periodic Transmit FIFO */
-}
-USB_OTG_GlobalTypeDef;
-
-
-/** 
-  * @brief __device_Registers
-  */
-typedef struct 
-{
-  __IO uint32_t DCFG;         /* dev Configuration Register   800h*/
-  __IO uint32_t DCTL;         /* dev Control Register         804h*/
-  __IO uint32_t DSTS;         /* dev Status Register (RO)     808h*/
-  uint32_t Reserved0C;           /* Reserved                     80Ch*/
-  __IO uint32_t DIEPMSK;   /* dev IN Endpoint Mask         810h*/
-  __IO uint32_t DOEPMSK;  /* dev OUT Endpoint Mask        814h*/
-  __IO uint32_t DAINT;     /* dev All Endpoints Itr Reg    818h*/
-  __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask   81Ch*/
-  uint32_t  Reserved20;          /* Reserved                     820h*/
-  uint32_t Reserved9;       /* Reserved                     824h*/
-  __IO uint32_t DVBUSDIS;    /* dev VBUS discharge Register  828h*/
-  __IO uint32_t DVBUSPULSE;  /* dev VBUS Pulse Register      82Ch*/
-  __IO uint32_t DTHRCTL;     /* dev thr                      830h*/
-  __IO uint32_t DIEPEMPMSK; /* dev empty msk             834h*/
-  __IO uint32_t DEACHINT;    /* dedicated EP interrupt       838h*/
-  __IO uint32_t DEACHMSK;    /* dedicated EP msk             83Ch*/  
-  uint32_t Reserved40;      /* dedicated EP mask           840h*/
-  __IO uint32_t DINEP1MSK;  /* dedicated EP mask           844h*/
-  uint32_t  Reserved44[15];      /* Reserved                 844-87Ch*/
-  __IO uint32_t DOUTEP1MSK; /* dedicated EP msk            884h*/   
-}
-USB_OTG_DeviceTypeDef;
-
-
-/** 
-  * @brief __IN_Endpoint-Specific_Register
-  */
-typedef struct 
-{
-  __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
-  uint32_t Reserved04;             /* Reserved                       900h + (ep_num * 20h) + 04h*/
-  __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg     900h + (ep_num * 20h) + 08h*/
-  uint32_t Reserved0C;             /* Reserved                       900h + (ep_num * 20h) + 0Ch*/
-  __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size   900h + (ep_num * 20h) + 10h*/
-  __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h*/
-  __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
-  uint32_t Reserved18;             /* Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
-}
-USB_OTG_INEndpointTypeDef;
-
-
-/** 
-  * @brief __OUT_Endpoint-Specific_Registers
-  */
-typedef struct 
-{
-  __IO uint32_t DOEPCTL;       /* dev OUT Endpoint Control Reg  B00h + (ep_num * 20h) + 00h*/
-  uint32_t Reserved04;         /* Reserved                      B00h + (ep_num * 20h) + 04h*/
-  __IO uint32_t DOEPINT;       /* dev OUT Endpoint Itr Reg      B00h + (ep_num * 20h) + 08h*/
-  uint32_t Reserved0C;         /* Reserved                      B00h + (ep_num * 20h) + 0Ch*/
-  __IO uint32_t DOEPTSIZ;      /* dev OUT Endpoint Txfer Size   B00h + (ep_num * 20h) + 10h*/
-  __IO uint32_t DOEPDMA;       /* dev OUT Endpoint DMA Address  B00h + (ep_num * 20h) + 14h*/
-  uint32_t Reserved18[2];      /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
-}
-USB_OTG_OUTEndpointTypeDef;
-
-
-/** 
-  * @brief __Host_Mode_Register_Structures
-  */
-typedef struct 
-{
-  __IO uint32_t HCFG;             /* Host Configuration Register    400h*/
-  __IO uint32_t HFIR;      /* Host Frame Interval Register   404h*/
-  __IO uint32_t HFNUM;         /* Host Frame Nbr/Frame Remaining 408h*/
-  uint32_t Reserved40C;                   /* Reserved                       40Ch*/
-  __IO uint32_t HPTXSTS;   /* Host Periodic Tx FIFO/ Queue Status 410h*/
-  __IO uint32_t HAINT;   /* Host All Channels Interrupt Register 414h*/
-  __IO uint32_t HAINTMSK;   /* Host All Channels Interrupt Mask 418h*/
-}
-USB_OTG_HostTypeDef;
-
-/** 
-  * @brief __Host_Channel_Specific_Registers
-  */
-typedef struct
-{
-  __IO uint32_t HCCHAR;
-  __IO uint32_t HCSPLT;
-  __IO uint32_t HCINT;
-  __IO uint32_t HCINTMSK;
-  __IO uint32_t HCTSIZ;
-  __IO uint32_t HCDMA;
-  uint32_t Reserved[2];
-}
-USB_OTG_HostChannelTypeDef;
-/**
-  * @}
-  */
-    
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-#define FLASH_BASE            0x08000000U /*!< FLASH(up to 2 MB) base address in the alias region                         */
-#define CCMDATARAM_BASE       0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
-#define SRAM1_BASE            0x20000000U /*!< SRAM1(112 KB) base address in the alias region                             */
-#define SRAM2_BASE            0x2001C000U /*!< SRAM2(16 KB) base address in the alias region                              */
-#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region                                */
-#define BKPSRAM_BASE          0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region                         */
-#define FMC_R_BASE            0xA0000000U /*!< FMC registers base address                                                 */
-#define SRAM1_BB_BASE         0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region                             */
-#define SRAM2_BB_BASE         0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region                              */
-#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region                                */
-#define BKPSRAM_BB_BASE       0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region                         */
-#define FLASH_END             0x081FFFFFU /*!< FLASH end address */
-#define CCMDATARAM_END        0x1000FFFFU /*!< CCM data RAM end address */
-
-/* Legacy defines */
-#define SRAM_BASE             SRAM1_BASE
-#define SRAM_BB_BASE          SRAM1_BB_BASE
-
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000U)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)
-#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800U)
-#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00U)
-#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000U)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)
-#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400U)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)
-#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000U)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800U)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00U)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x5000U)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)
-#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)
-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)
-#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800U)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)
-#define UART7_BASE            (APB1PERIPH_BASE + 0x7800U)
-#define UART8_BASE            (APB1PERIPH_BASE + 0x7C00U)
-
-/*!< APB2 peripherals */
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000U)
-#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400U)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x1000U)
-#define USART6_BASE           (APB2PERIPH_BASE + 0x1400U)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000U)
-#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100U)
-#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200U)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x2300U)
-#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00U)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)
-#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400U)
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800U)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00U)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000U)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400U)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800U)
-#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000U)
-#define SPI6_BASE             (APB2PERIPH_BASE + 0x5400U)
-#define SAI1_BASE             (APB2PERIPH_BASE + 0x5800U)
-#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004U)
-#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024U)
-
-/*!< AHB1 peripherals */
-#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000U)
-#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400U)
-#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800U)
-#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00U)
-#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000U)
-#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400U)
-#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800U)
-#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00U)
-#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000U)
-#define GPIOJ_BASE            (AHB1PERIPH_BASE + 0x2400U)
-#define GPIOK_BASE            (AHB1PERIPH_BASE + 0x2800U)
-#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)
-#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800U)
-#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00U)
-#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000U)
-#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010U)
-#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028U)
-#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040U)
-#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058U)
-#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070U)
-#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088U)
-#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0U)
-#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8U)
-#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400U)
-#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010U)
-#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028U)
-#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040U)
-#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058U)
-#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070U)
-#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088U)
-#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0U)
-#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)
-#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000U)
-#define ETH_MAC_BASE          (ETH_BASE)
-#define ETH_MMC_BASE          (ETH_BASE + 0x0100U)
-#define ETH_PTP_BASE          (ETH_BASE + 0x0700U)
-#define ETH_DMA_BASE          (ETH_BASE + 0x1000U)
-#define DMA2D_BASE            (AHB1PERIPH_BASE + 0xB000U)
-
-/*!< AHB2 peripherals */
-#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000U)
-#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800U)
-
-/*!< FMC Bankx registers base address */
-#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000U)
-#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104U)
-#define FMC_Bank2_3_R_BASE    (FMC_R_BASE + 0x0060U)
-#define FMC_Bank4_R_BASE      (FMC_R_BASE + 0x00A0U)
-#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140U)
-
-/* Debug MCU registers base address */
-#define DBGMCU_BASE           0xE0042000U
-
-/*!< USB registers base address */
-#define USB_OTG_HS_PERIPH_BASE               0x40040000U
-#define USB_OTG_FS_PERIPH_BASE               0x50000000U
-
-#define USB_OTG_GLOBAL_BASE                  0x000U
-#define USB_OTG_DEVICE_BASE                  0x800U
-#define USB_OTG_IN_ENDPOINT_BASE             0x900U
-#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U
-#define USB_OTG_EP_REG_SIZE                  0x20U
-#define USB_OTG_HOST_BASE                    0x400U
-#define USB_OTG_HOST_PORT_BASE               0x440U
-#define USB_OTG_HOST_CHANNEL_BASE            0x500U
-#define USB_OTG_HOST_CHANNEL_SIZE            0x20U
-#define USB_OTG_PCGCCTL_BASE                 0xE00U
-#define USB_OTG_FIFO_BASE                    0x1000U
-#define USB_OTG_FIFO_SIZE                    0x1000U
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
-#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
-#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define UART4               ((USART_TypeDef *) UART4_BASE)
-#define UART5               ((USART_TypeDef *) UART5_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
-#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
-#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
-#define UART7               ((USART_TypeDef *) UART7_BASE)
-#define UART8               ((USART_TypeDef *) UART8_BASE)
-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
-#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define USART6              ((USART_TypeDef *) USART6_BASE)
-#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
-#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
-#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE) 
-#define SPI4                ((SPI_TypeDef *) SPI4_BASE)
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-#define SPI5                ((SPI_TypeDef *) SPI5_BASE)
-#define SPI6                ((SPI_TypeDef *) SPI6_BASE)
-#define SAI1                ((SAI_TypeDef *) SAI1_BASE)
-#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
-#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
-
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
-#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)
-#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
-#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
-#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
-#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
-#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
-#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
-#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
-#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
-#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
-#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
-#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
-#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
-#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
-#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
-#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
-#define ETH                 ((ETH_TypeDef *) ETH_BASE)  
-#define DMA2D               ((DMA2D_TypeDef *)DMA2D_BASE)
-#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
-#define RNG                 ((RNG_TypeDef *) RNG_BASE)
-#define FMC_Bank1           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
-#define FMC_Bank1E          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
-#define FMC_Bank2_3         ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
-#define FMC_Bank4           ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
-#define FMC_Bank5_6         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
-
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
-#define USB_OTG_HS          ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers_Bits_Definition               */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Analog to Digital Converter                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          0x00000001U        /*!<Analog watchdog flag */
-#define  ADC_SR_EOC                          0x00000002U        /*!<End of conversion */
-#define  ADC_SR_JEOC                         0x00000004U        /*!<Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        0x00000008U        /*!<Injected channel Start flag */
-#define  ADC_SR_STRT                         0x00000010U        /*!<Regular channel Start flag */
-#define  ADC_SR_OVR                          0x00000020U        /*!<Overrun flag */
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
-#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels */
-#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels */
-#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution) */
-#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
-  
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion */
-#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode */
-#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC) */
-#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection */
-#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment */
-#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      0xFFFFU            /*!<Injected data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag */
-#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion */
-#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag */
-#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag */
-#define  ADC_CSR_OVR1                        0x00000020U        /*!<ADC1 DMA overrun  flag */
-#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag */
-#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion */
-#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag */
-#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag */
-#define  ADC_CSR_OVR2                        0x00002000U        /*!<ADC2 DMA overrun  flag */
-#define  ADC_CSR_AWD3                        0x00010000U        /*!<ADC3 Analog watchdog flag */
-#define  ADC_CSR_EOC3                        0x00020000U        /*!<ADC3 End of conversion */
-#define  ADC_CSR_JEOC3                       0x00040000U        /*!<ADC3 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT3                      0x00080000U        /*!<ADC3 Injected channel Start flag */
-#define  ADC_CSR_STRT3                       0x00100000U        /*!<ADC3 Regular channel Start flag */
-#define  ADC_CSR_OVR3                        0x00200000U        /*!<ADC3 DMA overrun  flag */
-
-/* Legacy defines */
-#define  ADC_CSR_DOVR1                        ADC_CSR_OVR1
-#define  ADC_CSR_DOVR2                        ADC_CSR_OVR2
-#define  ADC_CSR_DOVR3                        ADC_CSR_OVR3
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
-#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
-#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
-#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
-#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
-
-/*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                      0x0000FFFFU         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                      0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Controller Area Network                            */
-/*                                                                            */
-/******************************************************************************/
-/*!<CAN control and status registers */
-/*******************  Bit definition for CAN_MCR register  ********************/
-#define  CAN_MCR_INRQ                        0x00000001U        /*!<Initialization Request */
-#define  CAN_MCR_SLEEP                       0x00000002U        /*!<Sleep Mode Request */
-#define  CAN_MCR_TXFP                        0x00000004U        /*!<Transmit FIFO Priority */
-#define  CAN_MCR_RFLM                        0x00000008U        /*!<Receive FIFO Locked Mode */
-#define  CAN_MCR_NART                        0x00000010U        /*!<No Automatic Retransmission */
-#define  CAN_MCR_AWUM                        0x00000020U        /*!<Automatic Wakeup Mode */
-#define  CAN_MCR_ABOM                        0x00000040U        /*!<Automatic Bus-Off Management */
-#define  CAN_MCR_TTCM                        0x00000080U        /*!<Time Triggered Communication Mode */
-#define  CAN_MCR_RESET                       0x00008000U        /*!<bxCAN software master reset */
-#define  CAN_MCR_DBF                         0x00010000U        /*!<bxCAN Debug freeze */
-/*******************  Bit definition for CAN_MSR register  ********************/
-#define  CAN_MSR_INAK                        0x0001U            /*!<Initialization Acknowledge */
-#define  CAN_MSR_SLAK                        0x0002U            /*!<Sleep Acknowledge */
-#define  CAN_MSR_ERRI                        0x0004U            /*!<Error Interrupt */
-#define  CAN_MSR_WKUI                        0x0008U            /*!<Wakeup Interrupt */
-#define  CAN_MSR_SLAKI                       0x0010U            /*!<Sleep Acknowledge Interrupt */
-#define  CAN_MSR_TXM                         0x0100U            /*!<Transmit Mode */
-#define  CAN_MSR_RXM                         0x0200U            /*!<Receive Mode */
-#define  CAN_MSR_SAMP                        0x0400U            /*!<Last Sample Point */
-#define  CAN_MSR_RX                          0x0800U            /*!<CAN Rx Signal */
-
-/*******************  Bit definition for CAN_TSR register  ********************/
-#define  CAN_TSR_RQCP0                       0x00000001U        /*!<Request Completed Mailbox0 */
-#define  CAN_TSR_TXOK0                       0x00000002U        /*!<Transmission OK of Mailbox0 */
-#define  CAN_TSR_ALST0                       0x00000004U        /*!<Arbitration Lost for Mailbox0 */
-#define  CAN_TSR_TERR0                       0x00000008U        /*!<Transmission Error of Mailbox0 */
-#define  CAN_TSR_ABRQ0                       0x00000080U        /*!<Abort Request for Mailbox0 */
-#define  CAN_TSR_RQCP1                       0x00000100U        /*!<Request Completed Mailbox1 */
-#define  CAN_TSR_TXOK1                       0x00000200U        /*!<Transmission OK of Mailbox1 */
-#define  CAN_TSR_ALST1                       0x00000400U        /*!<Arbitration Lost for Mailbox1 */
-#define  CAN_TSR_TERR1                       0x00000800U        /*!<Transmission Error of Mailbox1 */
-#define  CAN_TSR_ABRQ1                       0x00008000U        /*!<Abort Request for Mailbox 1 */
-#define  CAN_TSR_RQCP2                       0x00010000U        /*!<Request Completed Mailbox2 */
-#define  CAN_TSR_TXOK2                       0x00020000U        /*!<Transmission OK of Mailbox 2 */
-#define  CAN_TSR_ALST2                       0x00040000U        /*!<Arbitration Lost for mailbox 2 */
-#define  CAN_TSR_TERR2                       0x00080000U        /*!<Transmission Error of Mailbox 2 */
-#define  CAN_TSR_ABRQ2                       0x00800000U        /*!<Abort Request for Mailbox 2 */
-#define  CAN_TSR_CODE                        0x03000000U        /*!<Mailbox Code */
-
-#define  CAN_TSR_TME                         0x1C000000U        /*!<TME[2:0] bits */
-#define  CAN_TSR_TME0                        0x04000000U        /*!<Transmit Mailbox 0 Empty */
-#define  CAN_TSR_TME1                        0x08000000U        /*!<Transmit Mailbox 1 Empty */
-#define  CAN_TSR_TME2                        0x10000000U        /*!<Transmit Mailbox 2 Empty */
-
-#define  CAN_TSR_LOW                         0xE0000000U        /*!<LOW[2:0] bits */
-#define  CAN_TSR_LOW0                        0x20000000U        /*!<Lowest Priority Flag for Mailbox 0 */
-#define  CAN_TSR_LOW1                        0x40000000U        /*!<Lowest Priority Flag for Mailbox 1 */
-#define  CAN_TSR_LOW2                        0x80000000U        /*!<Lowest Priority Flag for Mailbox 2 */
-
-/*******************  Bit definition for CAN_RF0R register  *******************/
-#define  CAN_RF0R_FMP0                       0x03U               /*!<FIFO 0 Message Pending */
-#define  CAN_RF0R_FULL0                      0x08U               /*!<FIFO 0 Full */
-#define  CAN_RF0R_FOVR0                      0x10U               /*!<FIFO 0 Overrun */
-#define  CAN_RF0R_RFOM0                      0x20U               /*!<Release FIFO 0 Output Mailbox */
-
-/*******************  Bit definition for CAN_RF1R register  *******************/
-#define  CAN_RF1R_FMP1                       0x03U               /*!<FIFO 1 Message Pending */
-#define  CAN_RF1R_FULL1                      0x08U               /*!<FIFO 1 Full */
-#define  CAN_RF1R_FOVR1                      0x10U               /*!<FIFO 1 Overrun */
-#define  CAN_RF1R_RFOM1                      0x20U               /*!<Release FIFO 1 Output Mailbox */
-
-/********************  Bit definition for CAN_IER register  *******************/
-#define  CAN_IER_TMEIE                       0x00000001U        /*!<Transmit Mailbox Empty Interrupt Enable */
-#define  CAN_IER_FMPIE0                      0x00000002U        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE0                       0x00000004U        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE0                      0x00000008U        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_FMPIE1                      0x00000010U        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE1                       0x00000020U        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE1                      0x00000040U        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error Warning Interrupt Enable */
-#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error Passive Interrupt Enable */
-#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-Off Interrupt Enable */
-#define  CAN_IER_LECIE                       0x00000800U        /*!<Last Error Code Interrupt Enable */
-#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error Interrupt Enable */
-#define  CAN_IER_WKUIE                       0x00010000U        /*!<Wakeup Interrupt Enable */
-#define  CAN_IER_SLKIE                       0x00020000U        /*!<Sleep Interrupt Enable */
-#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error warning interrupt enable */
-#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error passive interrupt enable */
-#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-off interrupt enable */
-#define  CAN_IER_LECIE                       0x00000800U        /*!<Last error code interrupt enable */
-#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error interrupt enable */
-
-
-/********************  Bit definition for CAN_ESR register  *******************/
-#define  CAN_ESR_EWGF                        0x00000001U        /*!<Error Warning Flag */
-#define  CAN_ESR_EPVF                        0x00000002U        /*!<Error Passive Flag */
-#define  CAN_ESR_BOFF                        0x00000004U        /*!<Bus-Off Flag */
-
-#define  CAN_ESR_LEC                         0x00000070U        /*!<LEC[2:0] bits (Last Error Code) */
-#define  CAN_ESR_LEC_0                       0x00000010U        /*!<Bit 0 */
-#define  CAN_ESR_LEC_1                       0x00000020U        /*!<Bit 1 */
-#define  CAN_ESR_LEC_2                       0x00000040U        /*!<Bit 2 */
-
-#define  CAN_ESR_TEC                         0x00FF0000U        /*!<Least significant byte of the 9-bit Transmit Error Counter */
-#define  CAN_ESR_REC                         0xFF000000U        /*!<Receive Error Counter */
-
-/*******************  Bit definition for CAN_BTR register  ********************/
-#define  CAN_BTR_BRP                         0x000003FFU        /*!<Baud Rate Prescaler */
-#define  CAN_BTR_TS1                         0x000F0000U        /*!<Time Segment 1 */
-#define  CAN_BTR_TS1_0                       0x00010000U        /*!<Bit 0 */
-#define  CAN_BTR_TS1_1                       0x00020000U        /*!<Bit 1 */
-#define  CAN_BTR_TS1_2                       0x00040000U        /*!<Bit 2 */
-#define  CAN_BTR_TS1_3                       0x00080000U        /*!<Bit 3 */
-#define  CAN_BTR_TS2                         0x00700000U        /*!<Time Segment 2 */
-#define  CAN_BTR_TS2_0                       0x00100000U        /*!<Bit 0 */
-#define  CAN_BTR_TS2_1                       0x00200000U        /*!<Bit 1 */
-#define  CAN_BTR_TS2_2                       0x00400000U        /*!<Bit 2 */
-#define  CAN_BTR_SJW                         0x03000000U        /*!<Resynchronization Jump Width */
-#define  CAN_BTR_SJW_0                       0x01000000U        /*!<Bit 0 */
-#define  CAN_BTR_SJW_1                       0x02000000U        /*!<Bit 1 */
-#define  CAN_BTR_LBKM                        0x40000000U        /*!<Loop Back Mode (Debug) */
-#define  CAN_BTR_SILM                        0x80000000U        /*!<Silent Mode */
-
-
-/*!<Mailbox registers */
-/******************  Bit definition for CAN_TI0R register  ********************/
-#define  CAN_TI0R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI0R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_TI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/******************  Bit definition for CAN_TDT0R register  *******************/
-#define  CAN_TDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT0R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/******************  Bit definition for CAN_TDL0R register  *******************/
-#define  CAN_TDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/******************  Bit definition for CAN_TDH0R register  *******************/
-#define  CAN_TDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI1R register  *******************/
-#define  CAN_TI1R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI1R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI1R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_TI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT1R register  ******************/
-#define  CAN_TDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT1R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL1R register  ******************/
-#define  CAN_TDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH1R register  ******************/
-#define  CAN_TDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI2R register  *******************/
-#define  CAN_TI2R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI2R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI2R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI2R_EXID                       0x001FFFF8U        /*!<Extended identifier */
-#define  CAN_TI2R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT2R register  ******************/  
-#define  CAN_TDT2R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT2R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT2R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL2R register  ******************/
-#define  CAN_TDL2R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL2R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL2R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL2R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH2R register  ******************/
-#define  CAN_TDH2R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH2R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH2R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH2R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI0R register  *******************/
-#define  CAN_RI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_RI0R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_RI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_RI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT0R register  ******************/
-#define  CAN_RDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_RDT0R_FMI                       0x0000FF00U        /*!<Filter Match Index */
-#define  CAN_RDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL0R register  ******************/
-#define  CAN_RDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_RDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_RDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_RDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH0R register  ******************/
-#define  CAN_RDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_RDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_RDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_RDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI1R register  *******************/
-#define  CAN_RI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_RI1R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_RI1R_EXID                       0x001FFFF8U        /*!<Extended identifier */
-#define  CAN_RI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT1R register  ******************/
-#define  CAN_RDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_RDT1R_FMI                       0x0000FF00U        /*!<Filter Match Index */
-#define  CAN_RDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL1R register  ******************/
-#define  CAN_RDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_RDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_RDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_RDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH1R register  ******************/
-#define  CAN_RDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_RDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_RDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_RDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*!<CAN filter registers */
-/*******************  Bit definition for CAN_FMR register  ********************/
-#define  CAN_FMR_FINIT                       0x01U               /*!<Filter Init Mode */
-#define  CAN_FMR_CAN2SB                      0x00003F00U        /*!<CAN2 start bank */
-
-/*******************  Bit definition for CAN_FM1R register  *******************/
-#define  CAN_FM1R_FBM                        0x0FFFFFFFU        /*!<Filter Mode */
-#define  CAN_FM1R_FBM0                       0x00000001U        /*!<Filter Init Mode bit 0 */
-#define  CAN_FM1R_FBM1                       0x00000002U        /*!<Filter Init Mode bit 1 */
-#define  CAN_FM1R_FBM2                       0x00000004U        /*!<Filter Init Mode bit 2 */
-#define  CAN_FM1R_FBM3                       0x00000008U        /*!<Filter Init Mode bit 3 */
-#define  CAN_FM1R_FBM4                       0x00000010U        /*!<Filter Init Mode bit 4 */
-#define  CAN_FM1R_FBM5                       0x00000020U        /*!<Filter Init Mode bit 5 */
-#define  CAN_FM1R_FBM6                       0x00000040U        /*!<Filter Init Mode bit 6 */
-#define  CAN_FM1R_FBM7                       0x00000080U        /*!<Filter Init Mode bit 7 */
-#define  CAN_FM1R_FBM8                       0x00000100U        /*!<Filter Init Mode bit 8 */
-#define  CAN_FM1R_FBM9                       0x00000200U        /*!<Filter Init Mode bit 9 */
-#define  CAN_FM1R_FBM10                      0x00000400U        /*!<Filter Init Mode bit 10 */
-#define  CAN_FM1R_FBM11                      0x00000800U        /*!<Filter Init Mode bit 11 */
-#define  CAN_FM1R_FBM12                      0x00001000U        /*!<Filter Init Mode bit 12 */
-#define  CAN_FM1R_FBM13                      0x00002000U        /*!<Filter Init Mode bit 13 */
-#define  CAN_FM1R_FBM14                      0x00004000U        /*!<Filter Init Mode bit 14 */
-#define  CAN_FM1R_FBM15                      0x00008000U        /*!<Filter Init Mode bit 15 */
-#define  CAN_FM1R_FBM16                      0x00010000U        /*!<Filter Init Mode bit 16 */
-#define  CAN_FM1R_FBM17                      0x00020000U        /*!<Filter Init Mode bit 17 */
-#define  CAN_FM1R_FBM18                      0x00040000U        /*!<Filter Init Mode bit 18 */
-#define  CAN_FM1R_FBM19                      0x00080000U        /*!<Filter Init Mode bit 19 */
-#define  CAN_FM1R_FBM20                      0x00100000U        /*!<Filter Init Mode bit 20 */
-#define  CAN_FM1R_FBM21                      0x00200000U        /*!<Filter Init Mode bit 21 */
-#define  CAN_FM1R_FBM22                      0x00400000U        /*!<Filter Init Mode bit 22 */
-#define  CAN_FM1R_FBM23                      0x00800000U        /*!<Filter Init Mode bit 23 */
-#define  CAN_FM1R_FBM24                      0x01000000U        /*!<Filter Init Mode bit 24 */
-#define  CAN_FM1R_FBM25                      0x02000000U        /*!<Filter Init Mode bit 25 */
-#define  CAN_FM1R_FBM26                      0x04000000U        /*!<Filter Init Mode bit 26 */
-#define  CAN_FM1R_FBM27                      0x08000000U        /*!<Filter Init Mode bit 27 */
-
-/*******************  Bit definition for CAN_FS1R register  *******************/
-#define  CAN_FS1R_FSC                        0x0FFFFFFFU        /*!<Filter Scale Configuration */
-#define  CAN_FS1R_FSC0                       0x00000001U        /*!<Filter Scale Configuration bit 0 */
-#define  CAN_FS1R_FSC1                       0x00000002U        /*!<Filter Scale Configuration bit 1 */
-#define  CAN_FS1R_FSC2                       0x00000004U        /*!<Filter Scale Configuration bit 2 */
-#define  CAN_FS1R_FSC3                       0x00000008U        /*!<Filter Scale Configuration bit 3 */
-#define  CAN_FS1R_FSC4                       0x00000010U        /*!<Filter Scale Configuration bit 4 */
-#define  CAN_FS1R_FSC5                       0x00000020U        /*!<Filter Scale Configuration bit 5 */
-#define  CAN_FS1R_FSC6                       0x00000040U        /*!<Filter Scale Configuration bit 6 */
-#define  CAN_FS1R_FSC7                       0x00000080U        /*!<Filter Scale Configuration bit 7 */
-#define  CAN_FS1R_FSC8                       0x00000100U        /*!<Filter Scale Configuration bit 8 */
-#define  CAN_FS1R_FSC9                       0x00000200U        /*!<Filter Scale Configuration bit 9 */
-#define  CAN_FS1R_FSC10                      0x00000400U        /*!<Filter Scale Configuration bit 10 */
-#define  CAN_FS1R_FSC11                      0x00000800U        /*!<Filter Scale Configuration bit 11 */
-#define  CAN_FS1R_FSC12                      0x00001000U        /*!<Filter Scale Configuration bit 12 */
-#define  CAN_FS1R_FSC13                      0x00002000U        /*!<Filter Scale Configuration bit 13 */
-#define  CAN_FS1R_FSC14                      0x00004000U        /*!<Filter Scale Configuration bit 14 */
-#define  CAN_FS1R_FSC15                      0x00008000U        /*!<Filter Scale Configuration bit 15 */
-#define  CAN_FS1R_FSC16                      0x00010000U        /*!<Filter Scale Configuration bit 16 */
-#define  CAN_FS1R_FSC17                      0x00020000U        /*!<Filter Scale Configuration bit 17 */
-#define  CAN_FS1R_FSC18                      0x00040000U        /*!<Filter Scale Configuration bit 18 */
-#define  CAN_FS1R_FSC19                      0x00080000U        /*!<Filter Scale Configuration bit 19 */
-#define  CAN_FS1R_FSC20                      0x00100000U        /*!<Filter Scale Configuration bit 20 */
-#define  CAN_FS1R_FSC21                      0x00200000U        /*!<Filter Scale Configuration bit 21 */
-#define  CAN_FS1R_FSC22                      0x00400000U        /*!<Filter Scale Configuration bit 22 */
-#define  CAN_FS1R_FSC23                      0x00800000U        /*!<Filter Scale Configuration bit 23 */
-#define  CAN_FS1R_FSC24                      0x01000000U        /*!<Filter Scale Configuration bit 24 */
-#define  CAN_FS1R_FSC25                      0x02000000U        /*!<Filter Scale Configuration bit 25 */
-#define  CAN_FS1R_FSC26                      0x04000000U        /*!<Filter Scale Configuration bit 26 */
-#define  CAN_FS1R_FSC27                      0x08000000U        /*!<Filter Scale Configuration bit 27 */
-
-/******************  Bit definition for CAN_FFA1R register  *******************/
-#define  CAN_FFA1R_FFA                        0x0FFFFFFFU        /*!<Filter FIFO Assignment */
-#define  CAN_FFA1R_FFA0                       0x00000001U        /*!<Filter FIFO Assignment bit 0 */
-#define  CAN_FFA1R_FFA1                       0x00000002U        /*!<Filter FIFO Assignment bit 1 */
-#define  CAN_FFA1R_FFA2                       0x00000004U        /*!<Filter FIFO Assignment bit 2 */
-#define  CAN_FFA1R_FFA3                       0x00000008U        /*!<Filter FIFO Assignment bit 3 */
-#define  CAN_FFA1R_FFA4                       0x00000010U        /*!<Filter FIFO Assignment bit 4 */
-#define  CAN_FFA1R_FFA5                       0x00000020U        /*!<Filter FIFO Assignment bit 5 */
-#define  CAN_FFA1R_FFA6                       0x00000040U        /*!<Filter FIFO Assignment bit 6 */
-#define  CAN_FFA1R_FFA7                       0x00000080U        /*!<Filter FIFO Assignment bit 7 */
-#define  CAN_FFA1R_FFA8                       0x00000100U        /*!<Filter FIFO Assignment bit 8 */
-#define  CAN_FFA1R_FFA9                       0x00000200U        /*!<Filter FIFO Assignment bit 9 */
-#define  CAN_FFA1R_FFA10                      0x00000400U        /*!<Filter FIFO Assignment bit 10 */
-#define  CAN_FFA1R_FFA11                      0x00000800U        /*!<Filter FIFO Assignment bit 11 */
-#define  CAN_FFA1R_FFA12                      0x00001000U        /*!<Filter FIFO Assignment bit 12 */
-#define  CAN_FFA1R_FFA13                      0x00002000U        /*!<Filter FIFO Assignment bit 13 */
-#define  CAN_FFA1R_FFA14                      0x00004000U        /*!<Filter FIFO Assignment bit 14 */
-#define  CAN_FFA1R_FFA15                      0x00008000U        /*!<Filter FIFO Assignment bit 15 */
-#define  CAN_FFA1R_FFA16                      0x00010000U        /*!<Filter FIFO Assignment bit 16 */
-#define  CAN_FFA1R_FFA17                      0x00020000U        /*!<Filter FIFO Assignment bit 17 */
-#define  CAN_FFA1R_FFA18                      0x00040000U        /*!<Filter FIFO Assignment bit 18 */
-#define  CAN_FFA1R_FFA19                      0x00080000U        /*!<Filter FIFO Assignment bit 19 */
-#define  CAN_FFA1R_FFA20                      0x00100000U        /*!<Filter FIFO Assignment bit 20 */
-#define  CAN_FFA1R_FFA21                      0x00200000U        /*!<Filter FIFO Assignment bit 21 */
-#define  CAN_FFA1R_FFA22                      0x00400000U        /*!<Filter FIFO Assignment bit 22 */
-#define  CAN_FFA1R_FFA23                      0x00800000U        /*!<Filter FIFO Assignment bit 23 */
-#define  CAN_FFA1R_FFA24                      0x01000000U        /*!<Filter FIFO Assignment bit 24 */
-#define  CAN_FFA1R_FFA25                      0x02000000U        /*!<Filter FIFO Assignment bit 25 */
-#define  CAN_FFA1R_FFA26                      0x04000000U        /*!<Filter FIFO Assignment bit 26 */
-#define  CAN_FFA1R_FFA27                      0x08000000U        /*!<Filter FIFO Assignment bit 27 */
-
-/*******************  Bit definition for CAN_FA1R register  *******************/
-#define  CAN_FA1R_FACT                        0x0FFFFFFFU        /*!<Filter Active */
-#define  CAN_FA1R_FACT0                       0x00000001U        /*!<Filter Active bit 0 */
-#define  CAN_FA1R_FACT1                       0x00000002U        /*!<Filter Active bit 1 */
-#define  CAN_FA1R_FACT2                       0x00000004U        /*!<Filter Active bit 2 */
-#define  CAN_FA1R_FACT3                       0x00000008U        /*!<Filter Active bit 3 */
-#define  CAN_FA1R_FACT4                       0x00000010U        /*!<Filter Active bit 4 */
-#define  CAN_FA1R_FACT5                       0x00000020U        /*!<Filter Active bit 5 */
-#define  CAN_FA1R_FACT6                       0x00000040U        /*!<Filter Active bit 6 */
-#define  CAN_FA1R_FACT7                       0x00000080U        /*!<Filter Active bit 7 */
-#define  CAN_FA1R_FACT8                       0x00000100U        /*!<Filter Active bit 8 */
-#define  CAN_FA1R_FACT9                       0x00000200U        /*!<Filter Active bit 9 */
-#define  CAN_FA1R_FACT10                      0x00000400U        /*!<Filter Active bit 10 */
-#define  CAN_FA1R_FACT11                      0x00000800U        /*!<Filter Active bit 11 */
-#define  CAN_FA1R_FACT12                      0x00001000U        /*!<Filter Active bit 12 */
-#define  CAN_FA1R_FACT13                      0x00002000U        /*!<Filter Active bit 13 */
-#define  CAN_FA1R_FACT14                      0x00004000U        /*!<Filter Active bit 14 */
-#define  CAN_FA1R_FACT15                      0x00008000U        /*!<Filter Active bit 15 */
-#define  CAN_FA1R_FACT16                      0x00010000U        /*!<Filter Active bit 16 */
-#define  CAN_FA1R_FACT17                      0x00020000U        /*!<Filter Active bit 17 */
-#define  CAN_FA1R_FACT18                      0x00040000U        /*!<Filter Active bit 18 */
-#define  CAN_FA1R_FACT19                      0x00080000U        /*!<Filter Active bit 19 */
-#define  CAN_FA1R_FACT20                      0x00100000U        /*!<Filter Active bit 20 */
-#define  CAN_FA1R_FACT21                      0x00200000U        /*!<Filter Active bit 21 */
-#define  CAN_FA1R_FACT22                      0x00400000U        /*!<Filter Active bit 22 */
-#define  CAN_FA1R_FACT23                      0x00800000U        /*!<Filter Active bit 23 */
-#define  CAN_FA1R_FACT24                      0x01000000U        /*!<Filter Active bit 24 */
-#define  CAN_FA1R_FACT25                      0x02000000U        /*!<Filter Active bit 25 */
-#define  CAN_FA1R_FACT26                      0x04000000U        /*!<Filter Active bit 26 */
-#define  CAN_FA1R_FACT27                      0x08000000U        /*!<Filter Active bit 27 */
-
-/*******************  Bit definition for CAN_F0R1 register  *******************/
-#define  CAN_F0R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F0R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F0R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F0R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F0R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F0R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F0R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F0R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F0R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F0R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F0R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F0R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F0R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F0R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F0R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F0R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F0R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F0R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F0R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F0R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F0R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F0R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F0R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F0R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F0R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F0R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F0R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F0R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F0R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F0R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F0R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F0R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R1 register  *******************/
-#define  CAN_F1R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F1R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F1R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F1R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F1R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F1R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F1R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F1R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F1R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F1R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F1R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F1R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F1R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F1R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F1R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F1R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F1R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F1R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F1R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F1R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F1R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F1R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F1R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F1R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F1R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F1R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F1R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F1R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F1R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F1R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F1R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F1R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R1 register  *******************/
-#define  CAN_F2R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F2R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F2R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F2R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F2R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F2R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F2R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F2R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F2R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F2R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F2R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F2R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F2R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F2R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F2R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F2R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F2R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F2R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F2R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F2R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F2R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F2R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F2R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F2R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F2R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F2R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F2R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F2R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F2R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F2R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F2R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F2R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R1 register  *******************/
-#define  CAN_F3R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F3R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F3R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F3R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F3R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F3R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F3R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F3R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F3R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F3R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F3R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F3R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F3R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F3R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F3R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F3R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F3R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F3R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F3R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F3R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F3R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F3R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F3R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F3R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F3R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F3R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F3R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F3R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F3R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F3R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F3R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F3R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R1 register  *******************/
-#define  CAN_F4R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F4R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F4R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F4R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F4R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F4R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F4R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F4R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F4R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F4R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F4R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F4R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F4R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F4R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F4R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F4R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F4R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F4R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F4R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F4R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F4R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F4R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F4R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F4R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F4R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F4R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F4R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F4R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F4R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F4R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F4R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F4R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R1 register  *******************/
-#define  CAN_F5R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F5R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F5R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F5R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F5R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F5R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F5R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F5R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F5R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F5R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F5R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F5R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F5R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F5R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F5R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F5R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F5R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F5R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F5R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F5R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F5R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F5R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F5R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F5R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F5R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F5R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F5R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F5R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F5R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F5R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F5R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F5R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R1 register  *******************/
-#define  CAN_F6R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F6R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F6R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F6R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F6R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F6R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F6R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F6R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F6R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F6R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F6R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F6R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F6R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F6R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F6R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F6R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F6R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F6R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F6R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F6R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F6R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F6R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F6R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F6R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F6R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F6R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F6R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F6R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F6R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F6R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F6R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F6R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R1 register  *******************/
-#define  CAN_F7R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F7R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F7R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F7R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F7R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F7R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F7R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F7R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F7R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F7R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F7R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F7R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F7R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F7R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F7R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F7R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F7R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F7R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F7R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F7R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F7R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F7R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F7R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F7R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F7R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F7R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F7R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F7R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F7R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F7R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F7R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F7R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R1 register  *******************/
-#define  CAN_F8R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F8R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F8R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F8R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F8R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F8R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F8R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F8R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F8R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F8R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F8R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F8R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F8R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F8R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F8R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F8R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F8R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F8R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F8R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F8R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F8R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F8R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F8R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F8R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F8R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F8R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F8R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F8R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F8R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F8R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F8R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F8R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R1 register  *******************/
-#define  CAN_F9R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F9R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F9R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F9R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F9R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F9R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F9R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F9R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F9R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F9R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F9R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F9R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F9R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F9R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F9R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F9R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F9R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F9R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F9R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F9R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F9R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F9R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F9R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F9R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F9R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F9R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F9R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F9R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F9R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F9R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F9R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F9R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R1 register  ******************/
-#define  CAN_F10R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F10R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F10R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F10R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F10R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F10R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F10R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F10R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F10R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F10R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F10R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F10R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F10R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F10R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F10R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F10R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F10R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F10R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F10R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F10R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F10R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F10R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F10R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F10R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F10R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F10R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F10R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F10R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F10R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F10R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F10R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F10R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R1 register  ******************/
-#define  CAN_F11R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F11R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F11R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F11R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F11R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F11R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F11R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F11R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F11R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F11R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F11R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F11R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F11R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F11R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F11R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F11R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F11R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F11R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F11R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F11R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F11R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F11R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F11R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F11R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F11R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F11R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F11R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F11R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F11R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F11R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F11R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F11R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R1 register  ******************/
-#define  CAN_F12R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F12R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F12R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F12R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F12R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F12R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F12R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F12R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F12R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F12R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F12R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F12R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F12R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F12R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F12R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F12R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F12R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F12R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F12R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F12R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F12R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F12R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F12R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F12R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F12R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F12R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F12R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F12R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F12R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F12R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F12R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F12R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R1 register  ******************/
-#define  CAN_F13R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F13R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F13R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F13R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F13R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F13R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F13R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F13R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F13R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F13R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F13R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F13R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F13R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F13R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F13R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F13R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F13R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F13R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F13R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F13R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F13R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F13R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F13R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F13R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F13R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F13R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F13R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F13R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F13R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F13R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F13R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F13R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F0R2 register  *******************/
-#define  CAN_F0R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F0R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F0R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F0R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F0R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F0R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F0R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F0R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F0R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F0R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F0R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F0R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F0R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F0R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F0R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F0R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F0R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F0R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F0R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F0R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F0R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F0R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F0R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F0R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F0R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F0R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F0R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F0R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F0R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F0R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F0R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F0R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R2 register  *******************/
-#define  CAN_F1R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F1R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F1R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F1R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F1R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F1R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F1R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F1R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F1R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F1R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F1R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F1R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F1R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F1R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F1R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F1R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F1R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F1R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F1R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F1R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F1R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F1R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F1R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F1R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F1R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F1R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F1R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F1R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F1R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F1R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F1R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F1R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R2 register  *******************/
-#define  CAN_F2R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F2R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F2R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F2R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F2R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F2R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F2R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F2R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F2R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F2R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F2R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F2R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F2R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F2R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F2R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F2R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F2R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F2R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F2R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F2R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F2R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F2R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F2R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F2R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F2R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F2R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F2R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F2R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F2R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F2R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F2R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F2R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R2 register  *******************/
-#define  CAN_F3R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F3R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F3R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F3R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F3R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F3R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F3R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F3R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F3R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F3R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F3R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F3R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F3R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F3R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F3R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F3R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F3R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F3R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F3R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F3R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F3R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F3R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F3R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F3R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F3R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F3R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F3R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F3R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F3R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F3R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F3R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F3R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R2 register  *******************/
-#define  CAN_F4R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F4R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F4R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F4R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F4R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F4R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F4R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F4R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F4R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F4R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F4R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F4R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F4R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F4R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F4R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F4R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F4R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F4R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F4R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F4R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F4R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F4R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F4R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F4R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F4R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F4R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F4R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F4R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F4R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F4R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F4R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F4R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R2 register  *******************/
-#define  CAN_F5R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F5R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F5R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F5R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F5R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F5R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F5R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F5R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F5R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F5R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F5R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F5R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F5R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F5R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F5R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F5R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F5R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F5R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F5R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F5R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F5R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F5R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F5R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F5R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F5R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F5R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F5R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F5R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F5R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F5R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F5R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F5R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R2 register  *******************/
-#define  CAN_F6R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F6R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F6R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F6R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F6R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F6R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F6R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F6R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F6R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F6R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F6R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F6R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F6R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F6R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F6R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F6R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F6R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F6R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F6R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F6R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F6R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F6R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F6R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F6R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F6R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F6R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F6R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F6R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F6R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F6R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F6R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F6R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R2 register  *******************/
-#define  CAN_F7R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F7R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F7R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F7R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F7R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F7R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F7R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F7R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F7R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F7R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F7R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F7R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F7R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F7R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F7R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F7R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F7R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F7R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F7R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F7R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F7R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F7R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F7R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F7R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F7R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F7R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F7R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F7R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F7R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F7R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F7R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F7R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R2 register  *******************/
-#define  CAN_F8R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F8R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F8R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F8R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F8R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F8R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F8R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F8R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F8R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F8R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F8R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F8R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F8R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F8R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F8R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F8R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F8R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F8R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F8R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F8R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F8R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F8R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F8R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F8R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F8R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F8R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F8R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F8R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F8R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F8R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F8R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F8R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R2 register  *******************/
-#define  CAN_F9R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F9R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F9R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F9R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F9R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F9R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F9R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F9R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F9R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F9R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F9R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F9R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F9R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F9R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F9R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F9R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F9R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F9R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F9R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F9R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F9R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F9R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F9R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F9R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F9R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F9R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F9R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F9R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F9R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F9R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F9R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F9R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R2 register  ******************/
-#define  CAN_F10R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F10R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F10R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F10R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F10R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F10R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F10R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F10R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F10R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F10R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F10R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F10R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F10R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F10R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F10R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F10R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F10R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F10R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F10R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F10R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F10R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F10R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F10R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F10R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F10R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F10R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F10R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F10R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F10R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F10R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F10R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F10R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R2 register  ******************/
-#define  CAN_F11R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F11R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F11R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F11R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F11R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F11R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F11R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F11R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F11R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F11R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F11R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F11R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F11R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F11R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F11R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F11R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F11R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F11R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F11R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F11R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F11R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F11R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F11R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F11R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F11R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F11R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F11R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F11R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F11R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F11R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F11R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F11R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R2 register  ******************/
-#define  CAN_F12R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F12R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F12R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F12R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F12R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F12R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F12R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F12R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F12R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F12R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F12R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F12R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F12R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F12R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F12R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F12R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F12R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F12R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F12R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F12R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F12R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F12R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F12R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F12R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F12R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F12R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F12R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F12R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F12R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F12R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F12R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F12R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R2 register  ******************/
-#define  CAN_F13R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F13R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F13R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F13R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F13R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F13R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F13R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F13R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F13R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F13R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F13R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F13R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F13R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F13R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F13R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F13R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F13R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F13R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F13R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F13R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F13R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F13R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F13R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F13R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F13R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F13R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F13R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F13R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F13R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F13R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F13R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F13R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRC calculation unit                              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           0xFFFFFFFFU /*!< Data register bits */
-
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         0xFFU        /*!< General-purpose 8-bit data register bits */
-
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        0x01U        /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Digital to Analog Converter                           */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DAC_CR register  ********************/
-#define  DAC_CR_EN1                          0x00000001U        /*!<DAC channel1 enable */
-#define  DAC_CR_BOFF1                        0x00000002U        /*!<DAC channel1 output buffer disable */
-#define  DAC_CR_TEN1                         0x00000004U        /*!<DAC channel1 Trigger enable */
-
-#define  DAC_CR_TSEL1                        0x00000038U        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define  DAC_CR_TSEL1_0                      0x00000008U        /*!<Bit 0 */
-#define  DAC_CR_TSEL1_1                      0x00000010U        /*!<Bit 1 */
-#define  DAC_CR_TSEL1_2                      0x00000020U        /*!<Bit 2 */
-
-#define  DAC_CR_WAVE1                        0x000000C0U        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE1_0                      0x00000040U        /*!<Bit 0 */
-#define  DAC_CR_WAVE1_1                      0x00000080U        /*!<Bit 1 */
-
-#define  DAC_CR_MAMP1                        0x00000F00U        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP1_0                      0x00000100U        /*!<Bit 0 */
-#define  DAC_CR_MAMP1_1                      0x00000200U        /*!<Bit 1 */
-#define  DAC_CR_MAMP1_2                      0x00000400U        /*!<Bit 2 */
-#define  DAC_CR_MAMP1_3                      0x00000800U        /*!<Bit 3 */
-
-#define  DAC_CR_DMAEN1                       0x00001000U        /*!<DAC channel1 DMA enable */
-#define  DAC_CR_DMAUDRIE1                    0x00002000U        /*!<DAC channel1 DMA underrun interrupt enable*/
-#define  DAC_CR_EN2                          0x00010000U        /*!<DAC channel2 enable */
-#define  DAC_CR_BOFF2                        0x00020000U        /*!<DAC channel2 output buffer disable */
-#define  DAC_CR_TEN2                         0x00040000U        /*!<DAC channel2 Trigger enable */
-
-#define  DAC_CR_TSEL2                        0x00380000U        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define  DAC_CR_TSEL2_0                      0x00080000U        /*!<Bit 0 */
-#define  DAC_CR_TSEL2_1                      0x00100000U        /*!<Bit 1 */
-#define  DAC_CR_TSEL2_2                      0x00200000U        /*!<Bit 2 */
-
-#define  DAC_CR_WAVE2                        0x00C00000U        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE2_0                      0x00400000U        /*!<Bit 0 */
-#define  DAC_CR_WAVE2_1                      0x00800000U        /*!<Bit 1 */
-
-#define  DAC_CR_MAMP2                        0x0F000000U        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP2_0                      0x01000000U        /*!<Bit 0 */
-#define  DAC_CR_MAMP2_1                      0x02000000U        /*!<Bit 1 */
-#define  DAC_CR_MAMP2_2                      0x04000000U        /*!<Bit 2 */
-#define  DAC_CR_MAMP2_3                      0x08000000U        /*!<Bit 3 */
-
-#define  DAC_CR_DMAEN2                       0x10000000U        /*!<DAC channel2 DMA enabled */
-#define  DAC_CR_DMAUDRIE2                    0x20000000U        /*!<DAC channel2 DMA underrun interrupt enable*/
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define  DAC_SWTRIGR_SWTRIG1                 0x01U               /*!<DAC channel1 software trigger */
-#define  DAC_SWTRIGR_SWTRIG2                 0x02U               /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define  DAC_DHR12R1_DACC1DHR                0x0FFFU            /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define  DAC_DHR12L1_DACC1DHR                0xFFF0U            /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define  DAC_DHR8R1_DACC1DHR                 0xFFU               /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define  DAC_DHR12R2_DACC2DHR                0x0FFFU            /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define  DAC_DHR12L2_DACC2DHR                0xFFF0U            /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define  DAC_DHR8R2_DACC2DHR                 0xFFU               /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define  DAC_DHR12RD_DACC1DHR                0x00000FFFU        /*!<DAC channel1 12-bit Right aligned data */
-#define  DAC_DHR12RD_DACC2DHR                0x0FFF0000U        /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define  DAC_DHR12LD_DACC1DHR                0x0000FFF0U        /*!<DAC channel1 12-bit Left aligned data */
-#define  DAC_DHR12LD_DACC2DHR                0xFFF00000U        /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define  DAC_DHR8RD_DACC1DHR                 0x00FFU            /*!<DAC channel1 8-bit Right aligned data */
-#define  DAC_DHR8RD_DACC2DHR                 0xFF00U            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define  DAC_DOR1_DACC1DOR                   0x0FFFU            /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define  DAC_DOR2_DACC2DOR                   0x0FFFU            /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define  DAC_SR_DMAUDR1                      0x00002000U        /*!<DAC channel1 DMA underrun flag */
-#define  DAC_SR_DMAUDR2                      0x20000000U        /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 Debug MCU                                  */
-/*                                                                            */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    DCMI                                    */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DCMI_CR register  ******************/
-#define DCMI_CR_CAPTURE                      0x00000001U
-#define DCMI_CR_CM                           0x00000002U
-#define DCMI_CR_CROP                         0x00000004U
-#define DCMI_CR_JPEG                         0x00000008U
-#define DCMI_CR_ESS                          0x00000010U
-#define DCMI_CR_PCKPOL                       0x00000020U
-#define DCMI_CR_HSPOL                        0x00000040U
-#define DCMI_CR_VSPOL                        0x00000080U
-#define DCMI_CR_FCRC_0                       0x00000100U
-#define DCMI_CR_FCRC_1                       0x00000200U
-#define DCMI_CR_EDM_0                        0x00000400U
-#define DCMI_CR_EDM_1                        0x00000800U
-#define DCMI_CR_CRE                          0x00001000U
-#define DCMI_CR_ENABLE                       0x00004000U
-
-/********************  Bits definition for DCMI_SR register  ******************/
-#define DCMI_SR_HSYNC                        0x00000001U
-#define DCMI_SR_VSYNC                        0x00000002U
-#define DCMI_SR_FNE                          0x00000004U
-
-/********************  Bits definition for DCMI_RIS register  *****************/
-#define DCMI_RIS_FRAME_RIS                   0x00000001U
-#define DCMI_RIS_OVR_RIS                     0x00000002U
-#define DCMI_RIS_ERR_RIS                     0x00000004U
-#define DCMI_RIS_VSYNC_RIS                   0x00000008U
-#define DCMI_RIS_LINE_RIS                    0x00000010U
-/* Legacy defines */
-#define DCMI_RISR_FRAME_RIS                  DCMI_RIS_FRAME_RIS
-#define DCMI_RISR_OVR_RIS                    DCMI_RIS_OVR_RIS
-#define DCMI_RISR_ERR_RIS                    DCMI_RIS_ERR_RIS
-#define DCMI_RISR_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS
-#define DCMI_RISR_LINE_RIS                   DCMI_RIS_LINE_RIS
-#define DCMI_RISR_OVF_RIS                    DCMI_RIS_OVR_RIS
-
-/********************  Bits definition for DCMI_IER register  *****************/
-#define DCMI_IER_FRAME_IE                    0x00000001U
-#define DCMI_IER_OVR_IE                      0x00000002U
-#define DCMI_IER_ERR_IE                      0x00000004U
-#define DCMI_IER_VSYNC_IE                    0x00000008U
-#define DCMI_IER_LINE_IE                     0x00000010U
-/* Legacy defines */
-#define DCMI_IER_OVF_IE                      DCMI_IER_OVR_IE
-
-/********************  Bits definition for DCMI_MIS register  *****************/
-#define DCMI_MIS_FRAME_MIS                   0x00000001U
-#define DCMI_MIS_OVR_MIS                     0x00000002U
-#define DCMI_MIS_ERR_MIS                     0x00000004U
-#define DCMI_MIS_VSYNC_MIS                   0x00000008U
-#define DCMI_MIS_LINE_MIS                    0x00000010U
-
-/* Legacy defines */
-#define DCMI_MISR_FRAME_MIS                  DCMI_MIS_FRAME_MIS
-#define DCMI_MISR_OVF_MIS                    DCMI_MIS_OVR_MIS
-#define DCMI_MISR_ERR_MIS                    DCMI_MIS_ERR_MIS
-#define DCMI_MISR_VSYNC_MIS                  DCMI_MIS_VSYNC_MIS
-#define DCMI_MISR_LINE_MIS                   DCMI_MIS_LINE_MIS
-
-/********************  Bits definition for DCMI_ICR register  *****************/
-#define DCMI_ICR_FRAME_ISC                   0x00000001U
-#define DCMI_ICR_OVR_ISC                     0x00000002U
-#define DCMI_ICR_ERR_ISC                     0x00000004U
-#define DCMI_ICR_VSYNC_ISC                   0x00000008U
-#define DCMI_ICR_LINE_ISC                    0x00000010U
-
-/* Legacy defines */
-#define DCMI_ICR_OVF_ISC                     DCMI_ICR_OVR_ISC
-
-/********************  Bits definition for DCMI_ESCR register  ******************/
-#define DCMI_ESCR_FSC                        0x000000FFU
-#define DCMI_ESCR_LSC                        0x0000FF00U
-#define DCMI_ESCR_LEC                        0x00FF0000U
-#define DCMI_ESCR_FEC                        0xFF000000U
-
-/********************  Bits definition for DCMI_ESUR register  ******************/
-#define DCMI_ESUR_FSU                        0x000000FFU
-#define DCMI_ESUR_LSU                        0x0000FF00U
-#define DCMI_ESUR_LEU                        0x00FF0000U
-#define DCMI_ESUR_FEU                        0xFF000000U
-
-/********************  Bits definition for DCMI_CWSTRT register  ******************/
-#define DCMI_CWSTRT_HOFFCNT                  0x00003FFFU
-#define DCMI_CWSTRT_VST                      0x1FFF0000U
-
-/********************  Bits definition for DCMI_CWSIZE register  ******************/
-#define DCMI_CWSIZE_CAPCNT                   0x00003FFFU
-#define DCMI_CWSIZE_VLINE                    0x3FFF0000U
-
-/********************  Bits definition for DCMI_DR register  ******************/
-#define DCMI_DR_BYTE0                        0x000000FFU
-#define DCMI_DR_BYTE1                        0x0000FF00U
-#define DCMI_DR_BYTE2                        0x00FF0000U
-#define DCMI_DR_BYTE3                        0xFF000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                             DMA Controller                                 */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DMA_SxCR register  *****************/
-#define DMA_SxCR_CHSEL                       0x0E000000U
-#define DMA_SxCR_CHSEL_0                     0x02000000U
-#define DMA_SxCR_CHSEL_1                     0x04000000U
-#define DMA_SxCR_CHSEL_2                     0x08000000U
-#define DMA_SxCR_MBURST                      0x01800000U
-#define DMA_SxCR_MBURST_0                    0x00800000U
-#define DMA_SxCR_MBURST_1                    0x01000000U
-#define DMA_SxCR_PBURST                      0x00600000U
-#define DMA_SxCR_PBURST_0                    0x00200000U
-#define DMA_SxCR_PBURST_1                    0x00400000U
-#define DMA_SxCR_CT                          0x00080000U
-#define DMA_SxCR_DBM                         0x00040000U
-#define DMA_SxCR_PL                          0x00030000U
-#define DMA_SxCR_PL_0                        0x00010000U
-#define DMA_SxCR_PL_1                        0x00020000U
-#define DMA_SxCR_PINCOS                      0x00008000U
-#define DMA_SxCR_MSIZE                       0x00006000U
-#define DMA_SxCR_MSIZE_0                     0x00002000U
-#define DMA_SxCR_MSIZE_1                     0x00004000U
-#define DMA_SxCR_PSIZE                       0x00001800U
-#define DMA_SxCR_PSIZE_0                     0x00000800U
-#define DMA_SxCR_PSIZE_1                     0x00001000U
-#define DMA_SxCR_MINC                        0x00000400U
-#define DMA_SxCR_PINC                        0x00000200U
-#define DMA_SxCR_CIRC                        0x00000100U
-#define DMA_SxCR_DIR                         0x000000C0U
-#define DMA_SxCR_DIR_0                       0x00000040U
-#define DMA_SxCR_DIR_1                       0x00000080U
-#define DMA_SxCR_PFCTRL                      0x00000020U
-#define DMA_SxCR_TCIE                        0x00000010U
-#define DMA_SxCR_HTIE                        0x00000008U
-#define DMA_SxCR_TEIE                        0x00000004U
-#define DMA_SxCR_DMEIE                       0x00000002U
-#define DMA_SxCR_EN                          0x00000001U
-
-/* Legacy defines */
-#define DMA_SxCR_ACK                         0x00100000U
-
-/********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            0x0000FFFFU
-#define DMA_SxNDT_0                          0x00000001U
-#define DMA_SxNDT_1                          0x00000002U
-#define DMA_SxNDT_2                          0x00000004U
-#define DMA_SxNDT_3                          0x00000008U
-#define DMA_SxNDT_4                          0x00000010U
-#define DMA_SxNDT_5                          0x00000020U
-#define DMA_SxNDT_6                          0x00000040U
-#define DMA_SxNDT_7                          0x00000080U
-#define DMA_SxNDT_8                          0x00000100U
-#define DMA_SxNDT_9                          0x00000200U
-#define DMA_SxNDT_10                         0x00000400U
-#define DMA_SxNDT_11                         0x00000800U
-#define DMA_SxNDT_12                         0x00001000U
-#define DMA_SxNDT_13                         0x00002000U
-#define DMA_SxNDT_14                         0x00004000U
-#define DMA_SxNDT_15                         0x00008000U
-
-/********************  Bits definition for DMA_SxFCR register  ****************/ 
-#define DMA_SxFCR_FEIE                       0x00000080U
-#define DMA_SxFCR_FS                         0x00000038U
-#define DMA_SxFCR_FS_0                       0x00000008U
-#define DMA_SxFCR_FS_1                       0x00000010U
-#define DMA_SxFCR_FS_2                       0x00000020U
-#define DMA_SxFCR_DMDIS                      0x00000004U
-#define DMA_SxFCR_FTH                        0x00000003U
-#define DMA_SxFCR_FTH_0                      0x00000001U
-#define DMA_SxFCR_FTH_1                      0x00000002U
-
-/********************  Bits definition for DMA_LISR register  *****************/ 
-#define DMA_LISR_TCIF3                       0x08000000U
-#define DMA_LISR_HTIF3                       0x04000000U
-#define DMA_LISR_TEIF3                       0x02000000U
-#define DMA_LISR_DMEIF3                      0x01000000U
-#define DMA_LISR_FEIF3                       0x00400000U
-#define DMA_LISR_TCIF2                       0x00200000U
-#define DMA_LISR_HTIF2                       0x00100000U
-#define DMA_LISR_TEIF2                       0x00080000U
-#define DMA_LISR_DMEIF2                      0x00040000U
-#define DMA_LISR_FEIF2                       0x00010000U
-#define DMA_LISR_TCIF1                       0x00000800U
-#define DMA_LISR_HTIF1                       0x00000400U
-#define DMA_LISR_TEIF1                       0x00000200U
-#define DMA_LISR_DMEIF1                      0x00000100U
-#define DMA_LISR_FEIF1                       0x00000040U
-#define DMA_LISR_TCIF0                       0x00000020U
-#define DMA_LISR_HTIF0                       0x00000010U
-#define DMA_LISR_TEIF0                       0x00000008U
-#define DMA_LISR_DMEIF0                      0x00000004U
-#define DMA_LISR_FEIF0                       0x00000001U
-
-/********************  Bits definition for DMA_HISR register  *****************/ 
-#define DMA_HISR_TCIF7                       0x08000000U
-#define DMA_HISR_HTIF7                       0x04000000U
-#define DMA_HISR_TEIF7                       0x02000000U
-#define DMA_HISR_DMEIF7                      0x01000000U
-#define DMA_HISR_FEIF7                       0x00400000U
-#define DMA_HISR_TCIF6                       0x00200000U
-#define DMA_HISR_HTIF6                       0x00100000U
-#define DMA_HISR_TEIF6                       0x00080000U
-#define DMA_HISR_DMEIF6                      0x00040000U
-#define DMA_HISR_FEIF6                       0x00010000U
-#define DMA_HISR_TCIF5                       0x00000800U
-#define DMA_HISR_HTIF5                       0x00000400U
-#define DMA_HISR_TEIF5                       0x00000200U
-#define DMA_HISR_DMEIF5                      0x00000100U
-#define DMA_HISR_FEIF5                       0x00000040U
-#define DMA_HISR_TCIF4                       0x00000020U
-#define DMA_HISR_HTIF4                       0x00000010U
-#define DMA_HISR_TEIF4                       0x00000008U
-#define DMA_HISR_DMEIF4                      0x00000004U
-#define DMA_HISR_FEIF4                       0x00000001U
-
-/********************  Bits definition for DMA_LIFCR register  ****************/ 
-#define DMA_LIFCR_CTCIF3                     0x08000000U
-#define DMA_LIFCR_CHTIF3                     0x04000000U
-#define DMA_LIFCR_CTEIF3                     0x02000000U
-#define DMA_LIFCR_CDMEIF3                    0x01000000U
-#define DMA_LIFCR_CFEIF3                     0x00400000U
-#define DMA_LIFCR_CTCIF2                     0x00200000U
-#define DMA_LIFCR_CHTIF2                     0x00100000U
-#define DMA_LIFCR_CTEIF2                     0x00080000U
-#define DMA_LIFCR_CDMEIF2                    0x00040000U
-#define DMA_LIFCR_CFEIF2                     0x00010000U
-#define DMA_LIFCR_CTCIF1                     0x00000800U
-#define DMA_LIFCR_CHTIF1                     0x00000400U
-#define DMA_LIFCR_CTEIF1                     0x00000200U
-#define DMA_LIFCR_CDMEIF1                    0x00000100U
-#define DMA_LIFCR_CFEIF1                     0x00000040U
-#define DMA_LIFCR_CTCIF0                     0x00000020U
-#define DMA_LIFCR_CHTIF0                     0x00000010U
-#define DMA_LIFCR_CTEIF0                     0x00000008U
-#define DMA_LIFCR_CDMEIF0                    0x00000004U
-#define DMA_LIFCR_CFEIF0                     0x00000001U
-
-/********************  Bits definition for DMA_HIFCR  register  ****************/ 
-#define DMA_HIFCR_CTCIF7                     0x08000000U
-#define DMA_HIFCR_CHTIF7                     0x04000000U
-#define DMA_HIFCR_CTEIF7                     0x02000000U
-#define DMA_HIFCR_CDMEIF7                    0x01000000U
-#define DMA_HIFCR_CFEIF7                     0x00400000U
-#define DMA_HIFCR_CTCIF6                     0x00200000U
-#define DMA_HIFCR_CHTIF6                     0x00100000U
-#define DMA_HIFCR_CTEIF6                     0x00080000U
-#define DMA_HIFCR_CDMEIF6                    0x00040000U
-#define DMA_HIFCR_CFEIF6                     0x00010000U
-#define DMA_HIFCR_CTCIF5                     0x00000800U
-#define DMA_HIFCR_CHTIF5                     0x00000400U
-#define DMA_HIFCR_CTEIF5                     0x00000200U
-#define DMA_HIFCR_CDMEIF5                    0x00000100U
-#define DMA_HIFCR_CFEIF5                     0x00000040U
-#define DMA_HIFCR_CTCIF4                     0x00000020U
-#define DMA_HIFCR_CHTIF4                     0x00000010U
-#define DMA_HIFCR_CTEIF4                     0x00000008U
-#define DMA_HIFCR_CDMEIF4                    0x00000004U
-#define DMA_HIFCR_CFEIF4                     0x00000001U
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                         AHB Master DMA2D Controller (DMA2D)                */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for DMA2D_CR register  ******************/
-
-#define DMA2D_CR_START                     0x00000001U               /*!< Start transfer */
-#define DMA2D_CR_SUSP                      0x00000002U               /*!< Suspend transfer */
-#define DMA2D_CR_ABORT                     0x00000004U               /*!< Abort transfer */
-#define DMA2D_CR_TEIE                      0x00000100U               /*!< Transfer Error Interrupt Enable */
-#define DMA2D_CR_TCIE                      0x00000200U               /*!< Transfer Complete Interrupt Enable */
-#define DMA2D_CR_TWIE                      0x00000400U               /*!< Transfer Watermark Interrupt Enable */
-#define DMA2D_CR_CAEIE                     0x00000800U               /*!< CLUT Access Error Interrupt Enable */
-#define DMA2D_CR_CTCIE                     0x00001000U               /*!< CLUT Transfer Complete Interrupt Enable */
-#define DMA2D_CR_CEIE                      0x00002000U               /*!< Configuration Error Interrupt Enable */
-#define DMA2D_CR_MODE                      0x00030000U               /*!< DMA2D Mode[1:0] */
-#define DMA2D_CR_MODE_0                    0x00010000U               /*!< DMA2D Mode bit 0 */
-#define DMA2D_CR_MODE_1                    0x00020000U               /*!< DMA2D Mode bit 1 */
-
-/********************  Bit definition for DMA2D_ISR register  *****************/
-
-#define DMA2D_ISR_TEIF                     0x00000001U               /*!< Transfer Error Interrupt Flag */
-#define DMA2D_ISR_TCIF                     0x00000002U               /*!< Transfer Complete Interrupt Flag */
-#define DMA2D_ISR_TWIF                     0x00000004U               /*!< Transfer Watermark Interrupt Flag */
-#define DMA2D_ISR_CAEIF                    0x00000008U               /*!< CLUT Access Error Interrupt Flag */
-#define DMA2D_ISR_CTCIF                    0x00000010U               /*!< CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_ISR_CEIF                     0x00000020U               /*!< Configuration Error Interrupt Flag */
-
-/********************  Bit definition for DMA2D_IFCR register  ****************/
-
-#define DMA2D_IFCR_CTEIF                   0x00000001U               /*!< Clears Transfer Error Interrupt Flag         */
-#define DMA2D_IFCR_CTCIF                   0x00000002U               /*!< Clears Transfer Complete Interrupt Flag      */
-#define DMA2D_IFCR_CTWIF                   0x00000004U               /*!< Clears Transfer Watermark Interrupt Flag     */
-#define DMA2D_IFCR_CAECIF                  0x00000008U               /*!< Clears CLUT Access Error Interrupt Flag      */
-#define DMA2D_IFCR_CCTCIF                  0x00000010U               /*!< Clears CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_IFCR_CCEIF                   0x00000020U               /*!< Clears Configuration Error Interrupt Flag    */
-
-/* Legacy defines */
-#define DMA2D_IFSR_CTEIF                   DMA2D_IFCR_CTEIF                     /*!< Clears Transfer Error Interrupt Flag         */
-#define DMA2D_IFSR_CTCIF                   DMA2D_IFCR_CTCIF                     /*!< Clears Transfer Complete Interrupt Flag      */
-#define DMA2D_IFSR_CTWIF                   DMA2D_IFCR_CTWIF                     /*!< Clears Transfer Watermark Interrupt Flag     */
-#define DMA2D_IFSR_CCAEIF                  DMA2D_IFCR_CAECIF                    /*!< Clears CLUT Access Error Interrupt Flag      */
-#define DMA2D_IFSR_CCTCIF                  DMA2D_IFCR_CCTCIF                    /*!< Clears CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_IFSR_CCEIF                   DMA2D_IFCR_CCEIF                     /*!< Clears Configuration Error Interrupt Flag    */
-
-/********************  Bit definition for DMA2D_FGMAR register  ***************/
-
-#define DMA2D_FGMAR_MA                     0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_FGOR register  ****************/
-
-#define DMA2D_FGOR_LO                      0x00003FFFU               /*!< Line Offset */
-
-/********************  Bit definition for DMA2D_BGMAR register  ***************/
-
-#define DMA2D_BGMAR_MA                     0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_BGOR register  ****************/
-
-#define DMA2D_BGOR_LO                      0x00003FFFU               /*!< Line Offset */
-
-/********************  Bit definition for DMA2D_FGPFCCR register  *************/
-
-#define DMA2D_FGPFCCR_CM                   0x0000000FU               /*!< Input color mode CM[3:0] */
-#define DMA2D_FGPFCCR_CM_0                 0x00000001U               /*!< Input color mode CM bit 0 */
-#define DMA2D_FGPFCCR_CM_1                 0x00000002U               /*!< Input color mode CM bit 1 */
-#define DMA2D_FGPFCCR_CM_2                 0x00000004U               /*!< Input color mode CM bit 2 */
-#define DMA2D_FGPFCCR_CM_3                 0x00000008U               /*!< Input color mode CM bit 3 */
-#define DMA2D_FGPFCCR_CCM                  0x00000010U               /*!< CLUT Color mode */
-#define DMA2D_FGPFCCR_START                0x00000020U               /*!< Start */
-#define DMA2D_FGPFCCR_CS                   0x0000FF00U               /*!< CLUT size */
-#define DMA2D_FGPFCCR_AM                   0x00030000U               /*!< Alpha mode AM[1:0] */
-#define DMA2D_FGPFCCR_AM_0                 0x00010000U               /*!< Alpha mode AM bit 0 */
-#define DMA2D_FGPFCCR_AM_1                 0x00020000U               /*!< Alpha mode AM bit 1 */
-#define DMA2D_FGPFCCR_ALPHA                0xFF000000U               /*!< Alpha value */
-
-/********************  Bit definition for DMA2D_FGCOLR register  **************/
-
-#define DMA2D_FGCOLR_BLUE                  0x000000FFU               /*!< Blue Value */
-#define DMA2D_FGCOLR_GREEN                 0x0000FF00U               /*!< Green Value */
-#define DMA2D_FGCOLR_RED                   0x00FF0000U               /*!< Red Value */   
-
-/********************  Bit definition for DMA2D_BGPFCCR register  *************/
-
-#define DMA2D_BGPFCCR_CM                   0x0000000FU               /*!< Input color mode CM[3:0] */
-#define DMA2D_BGPFCCR_CM_0                 0x00000001U               /*!< Input color mode CM bit 0 */
-#define DMA2D_BGPFCCR_CM_1                 0x00000002U               /*!< Input color mode CM bit 1 */
-#define DMA2D_BGPFCCR_CM_2                 0x00000004U               /*!< Input color mode CM bit 2 */
-#define DMA2D_FGPFCCR_CM_3                 0x00000008U               /*!< Input color mode CM bit 3 */
-#define DMA2D_BGPFCCR_CCM                  0x00000010U               /*!< CLUT Color mode */
-#define DMA2D_BGPFCCR_START                0x00000020U               /*!< Start */
-#define DMA2D_BGPFCCR_CS                   0x0000FF00U               /*!< CLUT size */
-#define DMA2D_BGPFCCR_AM                   0x00030000U               /*!< Alpha mode AM[1:0] */
-#define DMA2D_BGPFCCR_AM_0                 0x00010000U               /*!< Alpha mode AM bit 0 */
-#define DMA2D_BGPFCCR_AM_1                 0x00020000U               /*!< Alpha mode AM bit 1 */
-#define DMA2D_BGPFCCR_ALPHA                0xFF000000U               /*!< background Input Alpha value */
-
-/********************  Bit definition for DMA2D_BGCOLR register  **************/
-
-#define DMA2D_BGCOLR_BLUE                  0x000000FFU               /*!< Blue Value */
-#define DMA2D_BGCOLR_GREEN                 0x0000FF00U               /*!< Green Value */
-#define DMA2D_BGCOLR_RED                   0x00FF0000U               /*!< Red Value */
-
-/********************  Bit definition for DMA2D_FGCMAR register  **************/
-
-#define DMA2D_FGCMAR_MA                    0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_BGCMAR register  **************/
-
-#define DMA2D_BGCMAR_MA                    0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_OPFCCR register  **************/
-
-#define DMA2D_OPFCCR_CM                    0x00000007U               /*!< Color mode CM[2:0] */
-#define DMA2D_OPFCCR_CM_0                  0x00000001U               /*!< Color mode CM bit 0 */
-#define DMA2D_OPFCCR_CM_1                  0x00000002U               /*!< Color mode CM bit 1 */
-#define DMA2D_OPFCCR_CM_2                  0x00000004U               /*!< Color mode CM bit 2 */
-
-/********************  Bit definition for DMA2D_OCOLR register  ***************/
-
-/*!<Mode_ARGB8888/RGB888 */
-
-#define DMA2D_OCOLR_BLUE_1                 0x000000FFU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_1                0x0000FF00U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_1                  0x00FF0000U               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_1                0xFF000000U               /*!< Alpha Channel Value */
-
-/*!<Mode_RGB565 */
-#define DMA2D_OCOLR_BLUE_2                 0x0000001FU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_2                0x000007E0U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_2                  0x0000F800U               /*!< Red Value */
-
-/*!<Mode_ARGB1555 */
-#define DMA2D_OCOLR_BLUE_3                 0x0000001FU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_3                0x000003E0U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_3                  0x00007C00U               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_3                0x00008000U               /*!< Alpha Channel Value */
-
-/*!<Mode_ARGB4444 */
-#define DMA2D_OCOLR_BLUE_4                 0x0000000FU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_4                0x000000F0U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_4                  0x00000F00U               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_4                0x0000F000U               /*!< Alpha Channel Value */
-
-/********************  Bit definition for DMA2D_OMAR register  ****************/
-
-#define DMA2D_OMAR_MA                      0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_OOR register  *****************/
-
-#define DMA2D_OOR_LO                       0x00003FFFU               /*!< Line Offset */
-
-/********************  Bit definition for DMA2D_NLR register  *****************/
-
-#define DMA2D_NLR_NL                       0x0000FFFFU               /*!< Number of Lines */
-#define DMA2D_NLR_PL                       0x3FFF0000U               /*!< Pixel per Lines */
-
-/********************  Bit definition for DMA2D_LWR register  *****************/
-
-#define DMA2D_LWR_LW                       0x0000FFFFU               /*!< Line Watermark */
-
-/********************  Bit definition for DMA2D_AMTCR register  ***************/
-
-#define DMA2D_AMTCR_EN                     0x00000001U               /*!< Enable */
-#define DMA2D_AMTCR_DT                     0x0000FF00U               /*!< Dead Time */
-
-/********************  Bit definition for DMA2D_FGCLUT register  **************/
-                                                                     
-/********************  Bit definition for DMA2D_BGCLUT register  **************/
-
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                    External Interrupt/Event Controller                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    FLASH                                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    0x0000000FU
-#define FLASH_ACR_LATENCY_0WS                0x00000000U
-#define FLASH_ACR_LATENCY_1WS                0x00000001U
-#define FLASH_ACR_LATENCY_2WS                0x00000002U
-#define FLASH_ACR_LATENCY_3WS                0x00000003U
-#define FLASH_ACR_LATENCY_4WS                0x00000004U
-#define FLASH_ACR_LATENCY_5WS                0x00000005U
-#define FLASH_ACR_LATENCY_6WS                0x00000006U
-#define FLASH_ACR_LATENCY_7WS                0x00000007U
-#define FLASH_ACR_LATENCY_8WS                0x00000008U
-#define FLASH_ACR_LATENCY_9WS                0x00000009U
-#define FLASH_ACR_LATENCY_10WS               0x0000000AU
-#define FLASH_ACR_LATENCY_11WS               0x0000000BU
-#define FLASH_ACR_LATENCY_12WS               0x0000000CU
-#define FLASH_ACR_LATENCY_13WS               0x0000000DU
-#define FLASH_ACR_LATENCY_14WS               0x0000000EU
-#define FLASH_ACR_LATENCY_15WS               0x0000000FU
-#define FLASH_ACR_PRFTEN                     0x00000100U
-#define FLASH_ACR_ICEN                       0x00000200U
-#define FLASH_ACR_DCEN                       0x00000400U
-#define FLASH_ACR_ICRST                      0x00000800U
-#define FLASH_ACR_DCRST                      0x00001000U
-#define FLASH_ACR_BYTE0_ADDRESS              0x40023C00U
-#define FLASH_ACR_BYTE2_ADDRESS              0x40023C03U
-
-/*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         0x00000001U
-#define FLASH_SR_SOP                         0x00000002U
-#define FLASH_SR_WRPERR                      0x00000010U
-#define FLASH_SR_PGAERR                      0x00000020U
-#define FLASH_SR_PGPERR                      0x00000040U
-#define FLASH_SR_PGSERR                      0x00000080U
-#define FLASH_SR_BSY                         0x00010000U
-
-/*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          0x00000001U
-#define FLASH_CR_SER                         0x00000002U
-#define FLASH_CR_MER                         0x00000004U
-#define FLASH_CR_MER1                        FLASH_CR_MER
-#define FLASH_CR_SNB                         0x000000F8U
-#define FLASH_CR_SNB_0                       0x00000008U
-#define FLASH_CR_SNB_1                       0x00000010U
-#define FLASH_CR_SNB_2                       0x00000020U
-#define FLASH_CR_SNB_3                       0x00000040U
-#define FLASH_CR_SNB_4                       0x00000080U
-#define FLASH_CR_PSIZE                       0x00000300U
-#define FLASH_CR_PSIZE_0                     0x00000100U
-#define FLASH_CR_PSIZE_1                     0x00000200U
-#define FLASH_CR_MER2                        0x00008000U
-#define FLASH_CR_STRT                        0x00010000U
-#define FLASH_CR_EOPIE                       0x01000000U
-#define FLASH_CR_LOCK                        0x80000000U
-
-/*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                 0x00000001U
-#define FLASH_OPTCR_OPTSTRT                 0x00000002U
-#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
-#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
-#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
-#define FLASH_OPTCR_BFB2                    0x00000010U
-#define FLASH_OPTCR_WDG_SW                  0x00000020U
-#define FLASH_OPTCR_nRST_STOP               0x00000040U
-#define FLASH_OPTCR_nRST_STDBY              0x00000080U
-#define FLASH_OPTCR_RDP                     0x0000FF00U
-#define FLASH_OPTCR_RDP_0                   0x00000100U
-#define FLASH_OPTCR_RDP_1                   0x00000200U
-#define FLASH_OPTCR_RDP_2                   0x00000400U
-#define FLASH_OPTCR_RDP_3                   0x00000800U
-#define FLASH_OPTCR_RDP_4                   0x00001000U
-#define FLASH_OPTCR_RDP_5                   0x00002000U
-#define FLASH_OPTCR_RDP_6                   0x00004000U
-#define FLASH_OPTCR_RDP_7                   0x00008000U
-#define FLASH_OPTCR_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR_nWRP_0                  0x00010000U
-#define FLASH_OPTCR_nWRP_1                  0x00020000U
-#define FLASH_OPTCR_nWRP_2                  0x00040000U
-#define FLASH_OPTCR_nWRP_3                  0x00080000U
-#define FLASH_OPTCR_nWRP_4                  0x00100000U
-#define FLASH_OPTCR_nWRP_5                  0x00200000U
-#define FLASH_OPTCR_nWRP_6                  0x00400000U
-#define FLASH_OPTCR_nWRP_7                  0x00800000U
-#define FLASH_OPTCR_nWRP_8                  0x01000000U
-#define FLASH_OPTCR_nWRP_9                  0x02000000U
-#define FLASH_OPTCR_nWRP_10                 0x04000000U
-#define FLASH_OPTCR_nWRP_11                 0x08000000U
-#define FLASH_OPTCR_DB1M                    0x40000000U 
-#define FLASH_OPTCR_SPRMOD                  0x80000000U 
-                                             
-/******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR1_nWRP_0                  0x00010000U
-#define FLASH_OPTCR1_nWRP_1                  0x00020000U
-#define FLASH_OPTCR1_nWRP_2                  0x00040000U
-#define FLASH_OPTCR1_nWRP_3                  0x00080000U
-#define FLASH_OPTCR1_nWRP_4                  0x00100000U
-#define FLASH_OPTCR1_nWRP_5                  0x00200000U
-#define FLASH_OPTCR1_nWRP_6                  0x00400000U
-#define FLASH_OPTCR1_nWRP_7                  0x00800000U
-#define FLASH_OPTCR1_nWRP_8                  0x01000000U
-#define FLASH_OPTCR1_nWRP_9                  0x02000000U
-#define FLASH_OPTCR1_nWRP_10                 0x04000000U
-#define FLASH_OPTCR1_nWRP_11                 0x08000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Flexible Memory Controller                        */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for FMC_BCR1 register  *******************/
-#define  FMC_BCR1_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR1_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FMC_BCR1_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR1_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR1_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FMC_BCR1_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR1_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR1_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_BCR1_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR1_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR1_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR1_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
-#define  FMC_BCR1_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR1_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR1_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR1_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR1_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR1_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FMC_BCR1_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FMC_BCR1_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FMC_BCR1_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FMC_BCR1_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-#define  FMC_BCR1_CCLKEN                    0x00100000U        /*!<Continous clock enable     */
-
-/******************  Bit definition for FMC_BCR2 register  *******************/
-#define  FMC_BCR2_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR2_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FMC_BCR2_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR2_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR2_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FMC_BCR2_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR2_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR2_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_BCR2_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR2_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR2_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR2_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
-#define  FMC_BCR2_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR2_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR2_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR2_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR2_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR2_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FMC_BCR2_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FMC_BCR2_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FMC_BCR2_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FMC_BCR2_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FMC_BCR3 register  *******************/
-#define  FMC_BCR3_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR3_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FMC_BCR3_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR3_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR3_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FMC_BCR3_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR3_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR3_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_BCR3_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR3_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR3_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR3_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
-#define  FMC_BCR3_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR3_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR3_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR3_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR3_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR3_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FMC_BCR3_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FMC_BCR3_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FMC_BCR3_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FMC_BCR3_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FMC_BCR4 register  *******************/
-#define  FMC_BCR4_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR4_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FMC_BCR4_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR4_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR4_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FMC_BCR4_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR4_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR4_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_BCR4_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR4_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR4_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR4_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
-#define  FMC_BCR4_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR4_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR4_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR4_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR4_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR4_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FMC_BCR4_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FMC_BCR4_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FMC_BCR4_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FMC_BCR4_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FMC_BTR1 register  ******************/
-#define  FMC_BTR1_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR1_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR1_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR1_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR1_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BTR1_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
-#define  FMC_BTR1_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR1_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR1_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR1_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BTR1_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR1_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR1_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR1_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR1_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR1_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR1_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR1_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR1_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BTR1_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR1_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR1_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR1_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR1_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BTR1_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR1_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR1_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR1_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR1_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FMC_BTR1_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR1_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR1_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR1_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR1_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FMC_BTR1_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR1_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR1_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BTR2 register  *******************/
-#define  FMC_BTR2_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR2_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR2_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR2_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR2_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BTR2_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR2_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR2_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR2_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR2_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BTR2_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR2_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR2_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR2_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR2_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR2_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR2_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR2_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR2_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BTR2_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR2_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR2_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR2_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR2_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BTR2_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR2_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR2_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR2_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR2_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FMC_BTR2_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR2_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR2_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR2_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR2_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FMC_BTR2_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR2_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR2_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/*******************  Bit definition for FMC_BTR3 register  *******************/
-#define  FMC_BTR3_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR3_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR3_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR3_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR3_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BTR3_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR3_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR3_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR3_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR3_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BTR3_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR3_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR3_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR3_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR3_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR3_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR3_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR3_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR3_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BTR3_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR3_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR3_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR3_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR3_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BTR3_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR3_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR3_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR3_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR3_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FMC_BTR3_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR3_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR3_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR3_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR3_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FMC_BTR3_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR3_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR3_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BTR4 register  *******************/
-#define  FMC_BTR4_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR4_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR4_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR4_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR4_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BTR4_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR4_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR4_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR4_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR4_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BTR4_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR4_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR4_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR4_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR4_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR4_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR4_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR4_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR4_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BTR4_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR4_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR4_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR4_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR4_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BTR4_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR4_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR4_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR4_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR4_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FMC_BTR4_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR4_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR4_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR4_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR4_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FMC_BTR4_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR4_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR4_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR1 register  ******************/
-#define  FMC_BWTR1_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR1_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR1_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR1_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR1_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BWTR1_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR1_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR1_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR1_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR1_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BWTR1_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR1_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR1_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR1_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR1_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR1_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR1_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR1_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR1_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BWTR1_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR1_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR1_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR1_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR1_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BWTR1_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR1_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR1_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR2 register  ******************/
-#define  FMC_BWTR2_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR2_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR2_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR2_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR2_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BWTR2_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR2_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR2_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR2_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR2_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BWTR2_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR2_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR2_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR2_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR2_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR2_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR2_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR2_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR2_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BWTR2_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR2_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR2_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR2_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR2_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BWTR2_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR2_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR2_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR3 register  ******************/
-#define  FMC_BWTR3_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR3_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR3_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR3_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR3_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BWTR3_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR3_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR3_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR3_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR3_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BWTR3_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR3_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR3_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR3_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR3_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR3_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR3_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR3_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR3_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BWTR3_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR3_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR3_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR3_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR3_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BWTR3_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR3_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR3_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR4 register  ******************/
-#define  FMC_BWTR4_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR4_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR4_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR4_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR4_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BWTR4_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR4_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR4_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR4_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR4_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BWTR4_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR4_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR4_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR4_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR4_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR4_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR4_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR4_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR4_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BWTR4_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR4_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR4_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR4_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR4_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BWTR4_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR4_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR4_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_PCR2 register  *******************/
-#define  FMC_PCR2_PWAITEN                   0x00000002U        /*!<Wait feature enable bit                   */
-#define  FMC_PCR2_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FMC_PCR2_PTYP                      0x00000008U        /*!<Memory type                               */
-
-#define  FMC_PCR2_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FMC_PCR2_PWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_PCR2_PWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_PCR2_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit          */
-
-#define  FMC_PCR2_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay)          */
-#define  FMC_PCR2_TCLR_0                    0x00000200U        /*!<Bit 0 */
-#define  FMC_PCR2_TCLR_1                    0x00000400U        /*!<Bit 1 */
-#define  FMC_PCR2_TCLR_2                    0x00000800U        /*!<Bit 2 */
-#define  FMC_PCR2_TCLR_3                    0x00001000U        /*!<Bit 3 */
-
-#define  FMC_PCR2_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay)           */
-#define  FMC_PCR2_TAR_0                     0x00002000U        /*!<Bit 0 */
-#define  FMC_PCR2_TAR_1                     0x00004000U        /*!<Bit 1 */
-#define  FMC_PCR2_TAR_2                     0x00008000U        /*!<Bit 2 */
-#define  FMC_PCR2_TAR_3                     0x00010000U        /*!<Bit 3 */
-
-#define  FMC_PCR2_ECCPS                     0x000E0000U        /*!<ECCPS[1:0] bits (ECC page size)           */
-#define  FMC_PCR2_ECCPS_0                   0x00020000U        /*!<Bit 0 */
-#define  FMC_PCR2_ECCPS_1                   0x00040000U        /*!<Bit 1 */
-#define  FMC_PCR2_ECCPS_2                   0x00080000U        /*!<Bit 2 */
-
-/******************  Bit definition for FMC_PCR3 register  *******************/
-#define  FMC_PCR3_PWAITEN                   0x00000002U        /*!<Wait feature enable bit                   */
-#define  FMC_PCR3_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FMC_PCR3_PTYP                      0x00000008U        /*!<Memory type                               */
-
-#define  FMC_PCR3_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FMC_PCR3_PWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_PCR3_PWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_PCR3_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit          */
-
-#define  FMC_PCR3_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay)          */
-#define  FMC_PCR3_TCLR_0                    0x00000200U        /*!<Bit 0 */
-#define  FMC_PCR3_TCLR_1                    0x00000400U        /*!<Bit 1 */
-#define  FMC_PCR3_TCLR_2                    0x00000800U        /*!<Bit 2 */
-#define  FMC_PCR3_TCLR_3                    0x00001000U        /*!<Bit 3 */
-
-#define  FMC_PCR3_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay)           */
-#define  FMC_PCR3_TAR_0                     0x00002000U        /*!<Bit 0 */
-#define  FMC_PCR3_TAR_1                     0x00004000U        /*!<Bit 1 */
-#define  FMC_PCR3_TAR_2                     0x00008000U        /*!<Bit 2 */
-#define  FMC_PCR3_TAR_3                     0x00010000U        /*!<Bit 3 */
-
-#define  FMC_PCR3_ECCPS                     0x000E0000U        /*!<ECCPS[2:0] bits (ECC page size)           */
-#define  FMC_PCR3_ECCPS_0                   0x00020000U        /*!<Bit 0 */
-#define  FMC_PCR3_ECCPS_1                   0x00040000U        /*!<Bit 1 */
-#define  FMC_PCR3_ECCPS_2                   0x00080000U        /*!<Bit 2 */
-
-/******************  Bit definition for FMC_PCR4 register  *******************/
-#define  FMC_PCR4_PWAITEN                   0x00000002U        /*!<Wait feature enable bit                   */
-#define  FMC_PCR4_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FMC_PCR4_PTYP                      0x00000008U        /*!<Memory type                               */
-
-#define  FMC_PCR4_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FMC_PCR4_PWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_PCR4_PWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_PCR4_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit          */
-
-#define  FMC_PCR4_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay)          */
-#define  FMC_PCR4_TCLR_0                    0x00000200U        /*!<Bit 0 */
-#define  FMC_PCR4_TCLR_1                    0x00000400U        /*!<Bit 1 */
-#define  FMC_PCR4_TCLR_2                    0x00000800U        /*!<Bit 2 */
-#define  FMC_PCR4_TCLR_3                    0x00001000U        /*!<Bit 3 */
-
-#define  FMC_PCR4_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay)           */
-#define  FMC_PCR4_TAR_0                     0x00002000U        /*!<Bit 0 */
-#define  FMC_PCR4_TAR_1                     0x00004000U        /*!<Bit 1 */
-#define  FMC_PCR4_TAR_2                     0x00008000U        /*!<Bit 2 */
-#define  FMC_PCR4_TAR_3                     0x00010000U        /*!<Bit 3 */
-
-#define  FMC_PCR4_ECCPS                     0x000E0000U        /*!<ECCPS[2:0] bits (ECC page size)           */
-#define  FMC_PCR4_ECCPS_0                   0x00020000U        /*!<Bit 0 */
-#define  FMC_PCR4_ECCPS_1                   0x00040000U        /*!<Bit 1 */
-#define  FMC_PCR4_ECCPS_2                   0x00080000U        /*!<Bit 2 */
-
-/*******************  Bit definition for FMC_SR2 register  *******************/
-#define  FMC_SR2_IRS                        0x01U               /*!<Interrupt Rising Edge status                */
-#define  FMC_SR2_ILS                        0x02U               /*!<Interrupt Level status                      */
-#define  FMC_SR2_IFS                        0x04U               /*!<Interrupt Falling Edge status               */
-#define  FMC_SR2_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FMC_SR2_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit        */
-#define  FMC_SR2_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FMC_SR2_FEMPT                      0x40U               /*!<FIFO empty                                  */
-
-/*******************  Bit definition for FMC_SR3 register  *******************/
-#define  FMC_SR3_IRS                        0x01U               /*!<Interrupt Rising Edge status                */
-#define  FMC_SR3_ILS                        0x02U               /*!<Interrupt Level status                      */
-#define  FMC_SR3_IFS                        0x04U               /*!<Interrupt Falling Edge status               */
-#define  FMC_SR3_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FMC_SR3_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit        */
-#define  FMC_SR3_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FMC_SR3_FEMPT                      0x40U               /*!<FIFO empty                                  */
-
-/*******************  Bit definition for FMC_SR4 register  *******************/
-#define  FMC_SR4_IRS                        0x01U               /*!<Interrupt Rising Edge status                */
-#define  FMC_SR4_ILS                        0x02U               /*!<Interrupt Level status                      */
-#define  FMC_SR4_IFS                        0x04U               /*!<Interrupt Falling Edge status               */
-#define  FMC_SR4_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FMC_SR4_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit        */
-#define  FMC_SR4_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FMC_SR4_FEMPT                      0x40U               /*!<FIFO empty                                  */
-
-/******************  Bit definition for FMC_PMEM2 register  ******************/
-#define  FMC_PMEM2_MEMSET2                  0x000000FFU        /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
-#define  FMC_PMEM2_MEMSET2_0                0x00000001U        /*!<Bit 0 */
-#define  FMC_PMEM2_MEMSET2_1                0x00000002U        /*!<Bit 1 */
-#define  FMC_PMEM2_MEMSET2_2                0x00000004U        /*!<Bit 2 */
-#define  FMC_PMEM2_MEMSET2_3                0x00000008U        /*!<Bit 3 */
-#define  FMC_PMEM2_MEMSET2_4                0x00000010U        /*!<Bit 4 */
-#define  FMC_PMEM2_MEMSET2_5                0x00000020U        /*!<Bit 5 */
-#define  FMC_PMEM2_MEMSET2_6                0x00000040U        /*!<Bit 6 */
-#define  FMC_PMEM2_MEMSET2_7                0x00000080U        /*!<Bit 7 */
-
-#define  FMC_PMEM2_MEMWAIT2                 0x0000FF00U        /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
-#define  FMC_PMEM2_MEMWAIT2_0               0x00000100U        /*!<Bit 0 */
-#define  FMC_PMEM2_MEMWAIT2_1               0x00000200U        /*!<Bit 1 */
-#define  FMC_PMEM2_MEMWAIT2_2               0x00000400U        /*!<Bit 2 */
-#define  FMC_PMEM2_MEMWAIT2_3               0x00000800U        /*!<Bit 3 */
-#define  FMC_PMEM2_MEMWAIT2_4               0x00001000U        /*!<Bit 4 */
-#define  FMC_PMEM2_MEMWAIT2_5               0x00002000U        /*!<Bit 5 */
-#define  FMC_PMEM2_MEMWAIT2_6               0x00004000U        /*!<Bit 6 */
-#define  FMC_PMEM2_MEMWAIT2_7               0x00008000U        /*!<Bit 7 */
-
-#define  FMC_PMEM2_MEMHOLD2                 0x00FF0000U        /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
-#define  FMC_PMEM2_MEMHOLD2_0               0x00010000U        /*!<Bit 0 */
-#define  FMC_PMEM2_MEMHOLD2_1               0x00020000U        /*!<Bit 1 */
-#define  FMC_PMEM2_MEMHOLD2_2               0x00040000U        /*!<Bit 2 */
-#define  FMC_PMEM2_MEMHOLD2_3               0x00080000U        /*!<Bit 3 */
-#define  FMC_PMEM2_MEMHOLD2_4               0x00100000U        /*!<Bit 4 */
-#define  FMC_PMEM2_MEMHOLD2_5               0x00200000U        /*!<Bit 5 */
-#define  FMC_PMEM2_MEMHOLD2_6               0x00400000U        /*!<Bit 6 */
-#define  FMC_PMEM2_MEMHOLD2_7               0x00800000U        /*!<Bit 7 */
-
-#define  FMC_PMEM2_MEMHIZ2                  0xFF000000U        /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
-#define  FMC_PMEM2_MEMHIZ2_0                0x01000000U        /*!<Bit 0 */
-#define  FMC_PMEM2_MEMHIZ2_1                0x02000000U        /*!<Bit 1 */
-#define  FMC_PMEM2_MEMHIZ2_2                0x04000000U        /*!<Bit 2 */
-#define  FMC_PMEM2_MEMHIZ2_3                0x08000000U        /*!<Bit 3 */
-#define  FMC_PMEM2_MEMHIZ2_4                0x10000000U        /*!<Bit 4 */
-#define  FMC_PMEM2_MEMHIZ2_5                0x20000000U        /*!<Bit 5 */
-#define  FMC_PMEM2_MEMHIZ2_6                0x40000000U        /*!<Bit 6 */
-#define  FMC_PMEM2_MEMHIZ2_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_PMEM3 register  ******************/
-#define  FMC_PMEM3_MEMSET3                  0x000000FFU        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
-#define  FMC_PMEM3_MEMSET3_0                0x00000001U        /*!<Bit 0 */
-#define  FMC_PMEM3_MEMSET3_1                0x00000002U        /*!<Bit 1 */
-#define  FMC_PMEM3_MEMSET3_2                0x00000004U        /*!<Bit 2 */
-#define  FMC_PMEM3_MEMSET3_3                0x00000008U        /*!<Bit 3 */
-#define  FMC_PMEM3_MEMSET3_4                0x00000010U        /*!<Bit 4 */
-#define  FMC_PMEM3_MEMSET3_5                0x00000020U        /*!<Bit 5 */
-#define  FMC_PMEM3_MEMSET3_6                0x00000040U        /*!<Bit 6 */
-#define  FMC_PMEM3_MEMSET3_7                0x00000080U        /*!<Bit 7 */
-
-#define  FMC_PMEM3_MEMWAIT3                 0x0000FF00U        /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
-#define  FMC_PMEM3_MEMWAIT3_0               0x00000100U        /*!<Bit 0 */
-#define  FMC_PMEM3_MEMWAIT3_1               0x00000200U        /*!<Bit 1 */
-#define  FMC_PMEM3_MEMWAIT3_2               0x00000400U        /*!<Bit 2 */
-#define  FMC_PMEM3_MEMWAIT3_3               0x00000800U        /*!<Bit 3 */
-#define  FMC_PMEM3_MEMWAIT3_4               0x00001000U        /*!<Bit 4 */
-#define  FMC_PMEM3_MEMWAIT3_5               0x00002000U        /*!<Bit 5 */
-#define  FMC_PMEM3_MEMWAIT3_6               0x00004000U        /*!<Bit 6 */
-#define  FMC_PMEM3_MEMWAIT3_7               0x00008000U        /*!<Bit 7 */
-
-#define  FMC_PMEM3_MEMHOLD3                 0x00FF0000U        /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
-#define  FMC_PMEM3_MEMHOLD3_0               0x00010000U        /*!<Bit 0 */
-#define  FMC_PMEM3_MEMHOLD3_1               0x00020000U        /*!<Bit 1 */
-#define  FMC_PMEM3_MEMHOLD3_2               0x00040000U        /*!<Bit 2 */
-#define  FMC_PMEM3_MEMHOLD3_3               0x00080000U        /*!<Bit 3 */
-#define  FMC_PMEM3_MEMHOLD3_4               0x00100000U        /*!<Bit 4 */
-#define  FMC_PMEM3_MEMHOLD3_5               0x00200000U        /*!<Bit 5 */
-#define  FMC_PMEM3_MEMHOLD3_6               0x00400000U        /*!<Bit 6 */
-#define  FMC_PMEM3_MEMHOLD3_7               0x00800000U        /*!<Bit 7 */
-
-#define  FMC_PMEM3_MEMHIZ3                  0xFF000000U        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
-#define  FMC_PMEM3_MEMHIZ3_0                0x01000000U        /*!<Bit 0 */
-#define  FMC_PMEM3_MEMHIZ3_1                0x02000000U        /*!<Bit 1 */
-#define  FMC_PMEM3_MEMHIZ3_2                0x04000000U        /*!<Bit 2 */
-#define  FMC_PMEM3_MEMHIZ3_3                0x08000000U        /*!<Bit 3 */
-#define  FMC_PMEM3_MEMHIZ3_4                0x10000000U        /*!<Bit 4 */
-#define  FMC_PMEM3_MEMHIZ3_5                0x20000000U        /*!<Bit 5 */
-#define  FMC_PMEM3_MEMHIZ3_6                0x40000000U        /*!<Bit 6 */
-#define  FMC_PMEM3_MEMHIZ3_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_PMEM4 register  ******************/
-#define  FMC_PMEM4_MEMSET4                  0x000000FFU        /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
-#define  FMC_PMEM4_MEMSET4_0                0x00000001U        /*!<Bit 0 */
-#define  FMC_PMEM4_MEMSET4_1                0x00000002U        /*!<Bit 1 */
-#define  FMC_PMEM4_MEMSET4_2                0x00000004U        /*!<Bit 2 */
-#define  FMC_PMEM4_MEMSET4_3                0x00000008U        /*!<Bit 3 */
-#define  FMC_PMEM4_MEMSET4_4                0x00000010U        /*!<Bit 4 */
-#define  FMC_PMEM4_MEMSET4_5                0x00000020U        /*!<Bit 5 */
-#define  FMC_PMEM4_MEMSET4_6                0x00000040U        /*!<Bit 6 */
-#define  FMC_PMEM4_MEMSET4_7                0x00000080U        /*!<Bit 7 */
-
-#define  FMC_PMEM4_MEMWAIT4                 0x0000FF00U        /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
-#define  FMC_PMEM4_MEMWAIT4_0               0x00000100U        /*!<Bit 0 */
-#define  FMC_PMEM4_MEMWAIT4_1               0x00000200U        /*!<Bit 1 */
-#define  FMC_PMEM4_MEMWAIT4_2               0x00000400U        /*!<Bit 2 */
-#define  FMC_PMEM4_MEMWAIT4_3               0x00000800U        /*!<Bit 3 */
-#define  FMC_PMEM4_MEMWAIT4_4               0x00001000U        /*!<Bit 4 */
-#define  FMC_PMEM4_MEMWAIT4_5               0x00002000U        /*!<Bit 5 */
-#define  FMC_PMEM4_MEMWAIT4_6               0x00004000U        /*!<Bit 6 */
-#define  FMC_PMEM4_MEMWAIT4_7               0x00008000U        /*!<Bit 7 */
-
-#define  FMC_PMEM4_MEMHOLD4                 0x00FF0000U        /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
-#define  FMC_PMEM4_MEMHOLD4_0               0x00010000U        /*!<Bit 0 */
-#define  FMC_PMEM4_MEMHOLD4_1               0x00020000U        /*!<Bit 1 */
-#define  FMC_PMEM4_MEMHOLD4_2               0x00040000U        /*!<Bit 2 */
-#define  FMC_PMEM4_MEMHOLD4_3               0x00080000U        /*!<Bit 3 */
-#define  FMC_PMEM4_MEMHOLD4_4               0x00100000U        /*!<Bit 4 */
-#define  FMC_PMEM4_MEMHOLD4_5               0x00200000U        /*!<Bit 5 */
-#define  FMC_PMEM4_MEMHOLD4_6               0x00400000U        /*!<Bit 6 */
-#define  FMC_PMEM4_MEMHOLD4_7               0x00800000U        /*!<Bit 7 */
-
-#define  FMC_PMEM4_MEMHIZ4                  0xFF000000U        /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
-#define  FMC_PMEM4_MEMHIZ4_0                0x01000000U        /*!<Bit 0 */
-#define  FMC_PMEM4_MEMHIZ4_1                0x02000000U        /*!<Bit 1 */
-#define  FMC_PMEM4_MEMHIZ4_2                0x04000000U        /*!<Bit 2 */
-#define  FMC_PMEM4_MEMHIZ4_3                0x08000000U        /*!<Bit 3 */
-#define  FMC_PMEM4_MEMHIZ4_4                0x10000000U        /*!<Bit 4 */
-#define  FMC_PMEM4_MEMHIZ4_5                0x20000000U        /*!<Bit 5 */
-#define  FMC_PMEM4_MEMHIZ4_6                0x40000000U        /*!<Bit 6 */
-#define  FMC_PMEM4_MEMHIZ4_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_PATT2 register  ******************/
-#define  FMC_PATT2_ATTSET2                  0x000000FFU        /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
-#define  FMC_PATT2_ATTSET2_0                0x00000001U        /*!<Bit 0 */
-#define  FMC_PATT2_ATTSET2_1                0x00000002U        /*!<Bit 1 */
-#define  FMC_PATT2_ATTSET2_2                0x00000004U        /*!<Bit 2 */
-#define  FMC_PATT2_ATTSET2_3                0x00000008U        /*!<Bit 3 */
-#define  FMC_PATT2_ATTSET2_4                0x00000010U        /*!<Bit 4 */
-#define  FMC_PATT2_ATTSET2_5                0x00000020U        /*!<Bit 5 */
-#define  FMC_PATT2_ATTSET2_6                0x00000040U        /*!<Bit 6 */
-#define  FMC_PATT2_ATTSET2_7                0x00000080U        /*!<Bit 7 */
-
-#define  FMC_PATT2_ATTWAIT2                 0x0000FF00U        /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
-#define  FMC_PATT2_ATTWAIT2_0               0x00000100U        /*!<Bit 0 */
-#define  FMC_PATT2_ATTWAIT2_1               0x00000200U        /*!<Bit 1 */
-#define  FMC_PATT2_ATTWAIT2_2               0x00000400U        /*!<Bit 2 */
-#define  FMC_PATT2_ATTWAIT2_3               0x00000800U        /*!<Bit 3 */
-#define  FMC_PATT2_ATTWAIT2_4               0x00001000U        /*!<Bit 4 */
-#define  FMC_PATT2_ATTWAIT2_5               0x00002000U        /*!<Bit 5 */
-#define  FMC_PATT2_ATTWAIT2_6               0x00004000U        /*!<Bit 6 */
-#define  FMC_PATT2_ATTWAIT2_7               0x00008000U        /*!<Bit 7 */
-
-#define  FMC_PATT2_ATTHOLD2                 0x00FF0000U        /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
-#define  FMC_PATT2_ATTHOLD2_0               0x00010000U        /*!<Bit 0 */
-#define  FMC_PATT2_ATTHOLD2_1               0x00020000U        /*!<Bit 1 */
-#define  FMC_PATT2_ATTHOLD2_2               0x00040000U        /*!<Bit 2 */
-#define  FMC_PATT2_ATTHOLD2_3               0x00080000U        /*!<Bit 3 */
-#define  FMC_PATT2_ATTHOLD2_4               0x00100000U        /*!<Bit 4 */
-#define  FMC_PATT2_ATTHOLD2_5               0x00200000U        /*!<Bit 5 */
-#define  FMC_PATT2_ATTHOLD2_6               0x00400000U        /*!<Bit 6 */
-#define  FMC_PATT2_ATTHOLD2_7               0x00800000U        /*!<Bit 7 */
-
-#define  FMC_PATT2_ATTHIZ2                  0xFF000000U        /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
-#define  FMC_PATT2_ATTHIZ2_0                0x01000000U        /*!<Bit 0 */
-#define  FMC_PATT2_ATTHIZ2_1                0x02000000U        /*!<Bit 1 */
-#define  FMC_PATT2_ATTHIZ2_2                0x04000000U        /*!<Bit 2 */
-#define  FMC_PATT2_ATTHIZ2_3                0x08000000U        /*!<Bit 3 */
-#define  FMC_PATT2_ATTHIZ2_4                0x10000000U        /*!<Bit 4 */
-#define  FMC_PATT2_ATTHIZ2_5                0x20000000U        /*!<Bit 5 */
-#define  FMC_PATT2_ATTHIZ2_6                0x40000000U        /*!<Bit 6 */
-#define  FMC_PATT2_ATTHIZ2_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_PATT3 register  ******************/
-#define  FMC_PATT3_ATTSET3                  0x000000FFU        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
-#define  FMC_PATT3_ATTSET3_0                0x00000001U        /*!<Bit 0 */
-#define  FMC_PATT3_ATTSET3_1                0x00000002U        /*!<Bit 1 */
-#define  FMC_PATT3_ATTSET3_2                0x00000004U        /*!<Bit 2 */
-#define  FMC_PATT3_ATTSET3_3                0x00000008U        /*!<Bit 3 */
-#define  FMC_PATT3_ATTSET3_4                0x00000010U        /*!<Bit 4 */
-#define  FMC_PATT3_ATTSET3_5                0x00000020U        /*!<Bit 5 */
-#define  FMC_PATT3_ATTSET3_6                0x00000040U        /*!<Bit 6 */
-#define  FMC_PATT3_ATTSET3_7                0x00000080U        /*!<Bit 7 */
-
-#define  FMC_PATT3_ATTWAIT3                 0x0000FF00U        /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
-#define  FMC_PATT3_ATTWAIT3_0               0x00000100U        /*!<Bit 0 */
-#define  FMC_PATT3_ATTWAIT3_1               0x00000200U        /*!<Bit 1 */
-#define  FMC_PATT3_ATTWAIT3_2               0x00000400U        /*!<Bit 2 */
-#define  FMC_PATT3_ATTWAIT3_3               0x00000800U        /*!<Bit 3 */
-#define  FMC_PATT3_ATTWAIT3_4               0x00001000U        /*!<Bit 4 */
-#define  FMC_PATT3_ATTWAIT3_5               0x00002000U        /*!<Bit 5 */
-#define  FMC_PATT3_ATTWAIT3_6               0x00004000U        /*!<Bit 6 */
-#define  FMC_PATT3_ATTWAIT3_7               0x00008000U        /*!<Bit 7 */
-
-#define  FMC_PATT3_ATTHOLD3                 0x00FF0000U        /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
-#define  FMC_PATT3_ATTHOLD3_0               0x00010000U        /*!<Bit 0 */
-#define  FMC_PATT3_ATTHOLD3_1               0x00020000U        /*!<Bit 1 */
-#define  FMC_PATT3_ATTHOLD3_2               0x00040000U        /*!<Bit 2 */
-#define  FMC_PATT3_ATTHOLD3_3               0x00080000U        /*!<Bit 3 */
-#define  FMC_PATT3_ATTHOLD3_4               0x00100000U        /*!<Bit 4 */
-#define  FMC_PATT3_ATTHOLD3_5               0x00200000U        /*!<Bit 5 */
-#define  FMC_PATT3_ATTHOLD3_6               0x00400000U        /*!<Bit 6 */
-#define  FMC_PATT3_ATTHOLD3_7               0x00800000U        /*!<Bit 7 */
-
-#define  FMC_PATT3_ATTHIZ3                  0xFF000000U        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
-#define  FMC_PATT3_ATTHIZ3_0                0x01000000U        /*!<Bit 0 */
-#define  FMC_PATT3_ATTHIZ3_1                0x02000000U        /*!<Bit 1 */
-#define  FMC_PATT3_ATTHIZ3_2                0x04000000U        /*!<Bit 2 */
-#define  FMC_PATT3_ATTHIZ3_3                0x08000000U        /*!<Bit 3 */
-#define  FMC_PATT3_ATTHIZ3_4                0x10000000U        /*!<Bit 4 */
-#define  FMC_PATT3_ATTHIZ3_5                0x20000000U        /*!<Bit 5 */
-#define  FMC_PATT3_ATTHIZ3_6                0x40000000U        /*!<Bit 6 */
-#define  FMC_PATT3_ATTHIZ3_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_PATT4 register  ******************/
-#define  FMC_PATT4_ATTSET4                  0x000000FFU        /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
-#define  FMC_PATT4_ATTSET4_0                0x00000001U        /*!<Bit 0 */
-#define  FMC_PATT4_ATTSET4_1                0x00000002U        /*!<Bit 1 */
-#define  FMC_PATT4_ATTSET4_2                0x00000004U        /*!<Bit 2 */
-#define  FMC_PATT4_ATTSET4_3                0x00000008U        /*!<Bit 3 */
-#define  FMC_PATT4_ATTSET4_4                0x00000010U        /*!<Bit 4 */
-#define  FMC_PATT4_ATTSET4_5                0x00000020U        /*!<Bit 5 */
-#define  FMC_PATT4_ATTSET4_6                0x00000040U        /*!<Bit 6 */
-#define  FMC_PATT4_ATTSET4_7                0x00000080U        /*!<Bit 7 */
-
-#define  FMC_PATT4_ATTWAIT4                 0x0000FF00U        /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
-#define  FMC_PATT4_ATTWAIT4_0               0x00000100U        /*!<Bit 0 */
-#define  FMC_PATT4_ATTWAIT4_1               0x00000200U        /*!<Bit 1 */
-#define  FMC_PATT4_ATTWAIT4_2               0x00000400U        /*!<Bit 2 */
-#define  FMC_PATT4_ATTWAIT4_3               0x00000800U        /*!<Bit 3 */
-#define  FMC_PATT4_ATTWAIT4_4               0x00001000U        /*!<Bit 4 */
-#define  FMC_PATT4_ATTWAIT4_5               0x00002000U        /*!<Bit 5 */
-#define  FMC_PATT4_ATTWAIT4_6               0x00004000U        /*!<Bit 6 */
-#define  FMC_PATT4_ATTWAIT4_7               0x00008000U        /*!<Bit 7 */
-
-#define  FMC_PATT4_ATTHOLD4                 0x00FF0000U        /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
-#define  FMC_PATT4_ATTHOLD4_0               0x00010000U        /*!<Bit 0 */
-#define  FMC_PATT4_ATTHOLD4_1               0x00020000U        /*!<Bit 1 */
-#define  FMC_PATT4_ATTHOLD4_2               0x00040000U        /*!<Bit 2 */
-#define  FMC_PATT4_ATTHOLD4_3               0x00080000U        /*!<Bit 3 */
-#define  FMC_PATT4_ATTHOLD4_4               0x00100000U        /*!<Bit 4 */
-#define  FMC_PATT4_ATTHOLD4_5               0x00200000U        /*!<Bit 5 */
-#define  FMC_PATT4_ATTHOLD4_6               0x00400000U        /*!<Bit 6 */
-#define  FMC_PATT4_ATTHOLD4_7               0x00800000U        /*!<Bit 7 */
-
-#define  FMC_PATT4_ATTHIZ4                  0xFF000000U        /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
-#define  FMC_PATT4_ATTHIZ4_0                0x01000000U        /*!<Bit 0 */
-#define  FMC_PATT4_ATTHIZ4_1                0x02000000U        /*!<Bit 1 */
-#define  FMC_PATT4_ATTHIZ4_2                0x04000000U        /*!<Bit 2 */
-#define  FMC_PATT4_ATTHIZ4_3                0x08000000U        /*!<Bit 3 */
-#define  FMC_PATT4_ATTHIZ4_4                0x10000000U        /*!<Bit 4 */
-#define  FMC_PATT4_ATTHIZ4_5                0x20000000U        /*!<Bit 5 */
-#define  FMC_PATT4_ATTHIZ4_6                0x40000000U        /*!<Bit 6 */
-#define  FMC_PATT4_ATTHIZ4_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_PIO4 register  *******************/
-#define  FMC_PIO4_IOSET4                    0x000000FFU        /*!<IOSET4[7:0] bits (I/O 4 setup time) */
-#define  FMC_PIO4_IOSET4_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_PIO4_IOSET4_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_PIO4_IOSET4_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_PIO4_IOSET4_3                  0x00000008U        /*!<Bit 3 */
-#define  FMC_PIO4_IOSET4_4                  0x00000010U        /*!<Bit 4 */
-#define  FMC_PIO4_IOSET4_5                  0x00000020U        /*!<Bit 5 */
-#define  FMC_PIO4_IOSET4_6                  0x00000040U        /*!<Bit 6 */
-#define  FMC_PIO4_IOSET4_7                  0x00000080U        /*!<Bit 7 */
-
-#define  FMC_PIO4_IOWAIT4                   0x0000FF00U        /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
-#define  FMC_PIO4_IOWAIT4_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_PIO4_IOWAIT4_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_PIO4_IOWAIT4_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_PIO4_IOWAIT4_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_PIO4_IOWAIT4_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_PIO4_IOWAIT4_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_PIO4_IOWAIT4_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_PIO4_IOWAIT4_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FMC_PIO4_IOHOLD4                   0x00FF0000U        /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
-#define  FMC_PIO4_IOHOLD4_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_PIO4_IOHOLD4_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_PIO4_IOHOLD4_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_PIO4_IOHOLD4_3                 0x00080000U        /*!<Bit 3 */
-#define  FMC_PIO4_IOHOLD4_4                 0x00100000U        /*!<Bit 4 */
-#define  FMC_PIO4_IOHOLD4_5                 0x00200000U        /*!<Bit 5 */
-#define  FMC_PIO4_IOHOLD4_6                 0x00400000U        /*!<Bit 6 */
-#define  FMC_PIO4_IOHOLD4_7                 0x00800000U        /*!<Bit 7 */
-
-#define  FMC_PIO4_IOHIZ4                    0xFF000000U        /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
-#define  FMC_PIO4_IOHIZ4_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_PIO4_IOHIZ4_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_PIO4_IOHIZ4_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_PIO4_IOHIZ4_3                  0x08000000U        /*!<Bit 3 */
-#define  FMC_PIO4_IOHIZ4_4                  0x10000000U        /*!<Bit 4 */
-#define  FMC_PIO4_IOHIZ4_5                  0x20000000U        /*!<Bit 5 */
-#define  FMC_PIO4_IOHIZ4_6                  0x40000000U        /*!<Bit 6 */
-#define  FMC_PIO4_IOHIZ4_7                  0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_ECCR2 register  ******************/
-#define  FMC_ECCR2_ECC2                     0xFFFFFFFFU        /*!<ECC result */
-
-/******************  Bit definition for FMC_ECCR3 register  ******************/
-#define  FMC_ECCR3_ECC3                     0xFFFFFFFFU        /*!<ECC result */
-
-/******************  Bit definition for FMC_SDCR1 register  ******************/
-#define  FMC_SDCR1_NC                       0x00000003U        /*!<NC[1:0] bits (Number of column bits) */
-#define  FMC_SDCR1_NC_0                     0x00000001U        /*!<Bit 0 */
-#define  FMC_SDCR1_NC_1                     0x00000002U        /*!<Bit 1 */
-
-#define  FMC_SDCR1_NR                       0x0000000CU        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR1_NR_0                     0x00000004U        /*!<Bit 0 */
-#define  FMC_SDCR1_NR_1                     0x00000008U        /*!<Bit 1 */
-
-#define  FMC_SDCR1_MWID                     0x00000030U        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR1_MWID_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDCR1_MWID_1                   0x00000020U        /*!<Bit 1 */
-
-#define  FMC_SDCR1_NB                       0x00000040U        /*!<Number of internal bank */
-
-#define  FMC_SDCR1_CAS                      0x00000180U        /*!<CAS[1:0] bits (CAS latency) */
-#define  FMC_SDCR1_CAS_0                    0x00000080U        /*!<Bit 0 */
-#define  FMC_SDCR1_CAS_1                    0x00000100U        /*!<Bit 1 */
-
-#define  FMC_SDCR1_WP                       0x00000200U        /*!<Write protection */
-
-#define  FMC_SDCR1_SDCLK                    0x00000C00U        /*!<SDRAM clock configuration */
-#define  FMC_SDCR1_SDCLK_0                  0x00000400U        /*!<Bit 0 */
-#define  FMC_SDCR1_SDCLK_1                  0x00000800U        /*!<Bit 1 */
-
-#define  FMC_SDCR1_RBURST                   0x00001000U        /*!<Read burst */
-
-#define  FMC_SDCR1_RPIPE                    0x00006000U        /*!<Write protection */
-#define  FMC_SDCR1_RPIPE_0                  0x00002000U        /*!<Bit 0 */
-#define  FMC_SDCR1_RPIPE_1                  0x00004000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_SDCR2 register  ******************/
-#define  FMC_SDCR2_NC                       0x00000003U        /*!<NC[1:0] bits (Number of column bits) */
-#define  FMC_SDCR2_NC_0                     0x00000001U        /*!<Bit 0 */
-#define  FMC_SDCR2_NC_1                     0x00000002U        /*!<Bit 1 */
-
-#define  FMC_SDCR2_NR                       0x0000000CU        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR2_NR_0                     0x00000004U        /*!<Bit 0 */
-#define  FMC_SDCR2_NR_1                     0x00000008U        /*!<Bit 1 */
-
-#define  FMC_SDCR2_MWID                     0x00000030U        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR2_MWID_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDCR2_MWID_1                   0x00000020U        /*!<Bit 1 */
-
-#define  FMC_SDCR2_NB                       0x00000040U        /*!<Number of internal bank */
-
-#define  FMC_SDCR2_CAS                      0x00000180U        /*!<CAS[1:0] bits (CAS latency) */
-#define  FMC_SDCR2_CAS_0                    0x00000080U        /*!<Bit 0 */
-#define  FMC_SDCR2_CAS_1                    0x00000100U        /*!<Bit 1 */
-
-#define  FMC_SDCR2_WP                       0x00000200U        /*!<Write protection */
-
-#define  FMC_SDCR2_SDCLK                    0x00000C00U        /*!<SDCLK[1:0] (SDRAM clock configuration) */
-#define  FMC_SDCR2_SDCLK_0                  0x00000400U        /*!<Bit 0 */
-#define  FMC_SDCR2_SDCLK_1                  0x00000800U        /*!<Bit 1 */
-
-#define  FMC_SDCR2_RBURST                   0x00001000U        /*!<Read burst */
-
-#define  FMC_SDCR2_RPIPE                    0x00006000U        /*!<RPIPE[1:0](Read pipe) */
-#define  FMC_SDCR2_RPIPE_0                  0x00002000U        /*!<Bit 0 */
-#define  FMC_SDCR2_RPIPE_1                  0x00004000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_SDTR1 register  ******************/
-#define  FMC_SDTR1_TMRD                     0x0000000FU        /*!<TMRD[3:0] bits (Load mode register to active) */
-#define  FMC_SDTR1_TMRD_0                   0x00000001U        /*!<Bit 0 */
-#define  FMC_SDTR1_TMRD_1                   0x00000002U        /*!<Bit 1 */
-#define  FMC_SDTR1_TMRD_2                   0x00000004U        /*!<Bit 2 */
-#define  FMC_SDTR1_TMRD_3                   0x00000008U        /*!<Bit 3 */
-                                            
-#define  FMC_SDTR1_TXSR                     0x000000F0U        /*!<TXSR[3:0] bits (Exit self refresh) */
-#define  FMC_SDTR1_TXSR_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDTR1_TXSR_1                   0x00000020U        /*!<Bit 1 */
-#define  FMC_SDTR1_TXSR_2                   0x00000040U        /*!<Bit 2 */
-#define  FMC_SDTR1_TXSR_3                   0x00000080U        /*!<Bit 3 */
-
-#define  FMC_SDTR1_TRAS                     0x00000F00U        /*!<TRAS[3:0] bits (Self refresh time) */
-#define  FMC_SDTR1_TRAS_0                   0x00000100U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRAS_1                   0x00000200U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRAS_2                   0x00000400U        /*!<Bit 2 */
-#define  FMC_SDTR1_TRAS_3                   0x00000800U        /*!<Bit 3 */
-
-#define  FMC_SDTR1_TRC                      0x0000F000U        /*!<TRC[2:0] bits (Row cycle delay) */
-#define  FMC_SDTR1_TRC_0                    0x00001000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRC_1                    0x00002000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRC_2                    0x00004000U        /*!<Bit 2 */
-
-#define  FMC_SDTR1_TWR                      0x000F0000U        /*!<TRC[2:0] bits (Write recovery delay) */
-#define  FMC_SDTR1_TWR_0                    0x00010000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TWR_1                    0x00020000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TWR_2                    0x00040000U        /*!<Bit 2 */
-
-#define  FMC_SDTR1_TRP                      0x00F00000U        /*!<TRP[2:0] bits (Row precharge delay) */
-#define  FMC_SDTR1_TRP_0                    0x00100000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRP_1                    0x00200000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRP_2                    0x00400000U        /*!<Bit 2 */
-
-#define  FMC_SDTR1_TRCD                     0x0F000000U        /*!<TRP[2:0] bits (Row to column delay) */
-#define  FMC_SDTR1_TRCD_0                   0x01000000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRCD_1                   0x02000000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRCD_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for FMC_SDTR2 register  ******************/
-#define  FMC_SDTR2_TMRD                     0x0000000FU        /*!<TMRD[3:0] bits (Load mode register to active) */
-#define  FMC_SDTR2_TMRD_0                   0x00000001U        /*!<Bit 0 */
-#define  FMC_SDTR2_TMRD_1                   0x00000002U        /*!<Bit 1 */
-#define  FMC_SDTR2_TMRD_2                   0x00000004U        /*!<Bit 2 */
-#define  FMC_SDTR2_TMRD_3                   0x00000008U        /*!<Bit 3 */
-                                            
-#define  FMC_SDTR2_TXSR                     0x000000F0U        /*!<TXSR[3:0] bits (Exit self refresh) */
-#define  FMC_SDTR2_TXSR_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDTR2_TXSR_1                   0x00000020U        /*!<Bit 1 */
-#define  FMC_SDTR2_TXSR_2                   0x00000040U        /*!<Bit 2 */
-#define  FMC_SDTR2_TXSR_3                   0x00000080U        /*!<Bit 3 */
-
-#define  FMC_SDTR2_TRAS                     0x00000F00U        /*!<TRAS[3:0] bits (Self refresh time) */
-#define  FMC_SDTR2_TRAS_0                   0x00000100U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRAS_1                   0x00000200U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRAS_2                   0x00000400U        /*!<Bit 2 */
-#define  FMC_SDTR2_TRAS_3                   0x00000800U        /*!<Bit 3 */
-
-#define  FMC_SDTR2_TRC                      0x0000F000U        /*!<TRC[2:0] bits (Row cycle delay) */
-#define  FMC_SDTR2_TRC_0                    0x00001000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRC_1                    0x00002000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRC_2                    0x00004000U        /*!<Bit 2 */
-
-#define  FMC_SDTR2_TWR                      0x000F0000U        /*!<TRC[2:0] bits (Write recovery delay) */
-#define  FMC_SDTR2_TWR_0                    0x00010000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TWR_1                    0x00020000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TWR_2                    0x00040000U        /*!<Bit 2 */
-
-#define  FMC_SDTR2_TRP                      0x00F00000U        /*!<TRP[2:0] bits (Row precharge delay) */
-#define  FMC_SDTR2_TRP_0                    0x00100000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRP_1                    0x00200000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRP_2                    0x00400000U        /*!<Bit 2 */
-
-#define  FMC_SDTR2_TRCD                     0x0F000000U        /*!<TRP[2:0] bits (Row to column delay) */
-#define  FMC_SDTR2_TRCD_0                   0x01000000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRCD_1                   0x02000000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRCD_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for FMC_SDCMR register  ******************/
-#define  FMC_SDCMR_MODE                     0x00000007U        /*!<MODE[2:0] bits (Command mode) */
-#define  FMC_SDCMR_MODE_0                   0x00000001U        /*!<Bit 0 */
-#define  FMC_SDCMR_MODE_1                   0x00000002U        /*!<Bit 1 */
-#define  FMC_SDCMR_MODE_2                   0x00000004U        /*!<Bit 2 */
-                                            
-#define  FMC_SDCMR_CTB2                     0x00000008U        /*!<Command target 2 */
-
-#define  FMC_SDCMR_CTB1                     0x00000010U        /*!<Command target 1 */
-
-#define  FMC_SDCMR_NRFS                     0x000001E0U        /*!<NRFS[3:0] bits (Number of auto-refresh) */
-#define  FMC_SDCMR_NRFS_0                   0x00000020U        /*!<Bit 0 */
-#define  FMC_SDCMR_NRFS_1                   0x00000040U        /*!<Bit 1 */
-#define  FMC_SDCMR_NRFS_2                   0x00000080U        /*!<Bit 2 */
-#define  FMC_SDCMR_NRFS_3                   0x00000100U        /*!<Bit 3 */
-
-#define  FMC_SDCMR_MRD                      0x003FFE00U        /*!<MRD[12:0] bits (Mode register definition) */
-
-/******************  Bit definition for FMC_SDRTR register  ******************/
-#define  FMC_SDRTR_CRE                      0x00000001U        /*!<Clear refresh error flag */
-
-#define  FMC_SDRTR_COUNT                    0x00003FFEU        /*!<COUNT[12:0] bits (Refresh timer count) */
-
-#define  FMC_SDRTR_REIE                     0x00004000U        /*!<RES interupt enable */
-
-/******************  Bit definition for FMC_SDSR register  ******************/
-#define  FMC_SDSR_RE                        0x00000001U        /*!<Refresh error flag */
-
-#define  FMC_SDSR_MODES1                    0x00000006U        /*!<MODES1[1:0]bits (Status mode for bank 1) */
-#define  FMC_SDSR_MODES1_0                  0x00000002U        /*!<Bit 0 */
-#define  FMC_SDSR_MODES1_1                  0x00000004U        /*!<Bit 1 */
-
-#define  FMC_SDSR_MODES2                    0x00000018U        /*!<MODES2[1:0]bits (Status mode for bank 2) */
-#define  FMC_SDSR_MODES2_0                  0x00000008U        /*!<Bit 0 */
-#define  FMC_SDSR_MODES2_1                  0x00000010U        /*!<Bit 1 */
-#define  FMC_SDSR_BUSY                      0x00000020U        /*!<Busy status */
-
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    0x00000003U
-#define GPIO_MODER_MODER0_0                  0x00000001U
-#define GPIO_MODER_MODER0_1                  0x00000002U
-
-#define GPIO_MODER_MODER1                    0x0000000CU
-#define GPIO_MODER_MODER1_0                  0x00000004U
-#define GPIO_MODER_MODER1_1                  0x00000008U
-
-#define GPIO_MODER_MODER2                    0x00000030U
-#define GPIO_MODER_MODER2_0                  0x00000010U
-#define GPIO_MODER_MODER2_1                  0x00000020U
-
-#define GPIO_MODER_MODER3                    0x000000C0U
-#define GPIO_MODER_MODER3_0                  0x00000040U
-#define GPIO_MODER_MODER3_1                  0x00000080U
-
-#define GPIO_MODER_MODER4                    0x00000300U
-#define GPIO_MODER_MODER4_0                  0x00000100U
-#define GPIO_MODER_MODER4_1                  0x00000200U
-
-#define GPIO_MODER_MODER5                    0x00000C00U
-#define GPIO_MODER_MODER5_0                  0x00000400U
-#define GPIO_MODER_MODER5_1                  0x00000800U
-
-#define GPIO_MODER_MODER6                    0x00003000U
-#define GPIO_MODER_MODER6_0                  0x00001000U
-#define GPIO_MODER_MODER6_1                  0x00002000U
-
-#define GPIO_MODER_MODER7                    0x0000C000U
-#define GPIO_MODER_MODER7_0                  0x00004000U
-#define GPIO_MODER_MODER7_1                  0x00008000U
-
-#define GPIO_MODER_MODER8                    0x00030000U
-#define GPIO_MODER_MODER8_0                  0x00010000U
-#define GPIO_MODER_MODER8_1                  0x00020000U
-
-#define GPIO_MODER_MODER9                    0x000C0000U
-#define GPIO_MODER_MODER9_0                  0x00040000U
-#define GPIO_MODER_MODER9_1                  0x00080000U
-
-#define GPIO_MODER_MODER10                   0x00300000U
-#define GPIO_MODER_MODER10_0                 0x00100000U
-#define GPIO_MODER_MODER10_1                 0x00200000U
-
-#define GPIO_MODER_MODER11                   0x00C00000U
-#define GPIO_MODER_MODER11_0                 0x00400000U
-#define GPIO_MODER_MODER11_1                 0x00800000U
-
-#define GPIO_MODER_MODER12                   0x03000000U
-#define GPIO_MODER_MODER12_0                 0x01000000U
-#define GPIO_MODER_MODER12_1                 0x02000000U
-
-#define GPIO_MODER_MODER13                   0x0C000000U
-#define GPIO_MODER_MODER13_0                 0x04000000U
-#define GPIO_MODER_MODER13_1                 0x08000000U
-
-#define GPIO_MODER_MODER14                   0x30000000U
-#define GPIO_MODER_MODER14_0                 0x10000000U
-#define GPIO_MODER_MODER14_1                 0x20000000U
-
-#define GPIO_MODER_MODER15                   0xC0000000U
-#define GPIO_MODER_MODER15_0                 0x40000000U
-#define GPIO_MODER_MODER15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     0x00000001U
-#define GPIO_OTYPER_OT_1                     0x00000002U
-#define GPIO_OTYPER_OT_2                     0x00000004U
-#define GPIO_OTYPER_OT_3                     0x00000008U
-#define GPIO_OTYPER_OT_4                     0x00000010U
-#define GPIO_OTYPER_OT_5                     0x00000020U
-#define GPIO_OTYPER_OT_6                     0x00000040U
-#define GPIO_OTYPER_OT_7                     0x00000080U
-#define GPIO_OTYPER_OT_8                     0x00000100U
-#define GPIO_OTYPER_OT_9                     0x00000200U
-#define GPIO_OTYPER_OT_10                    0x00000400U
-#define GPIO_OTYPER_OT_11                    0x00000800U
-#define GPIO_OTYPER_OT_12                    0x00001000U
-#define GPIO_OTYPER_OT_13                    0x00002000U
-#define GPIO_OTYPER_OT_14                    0x00004000U
-#define GPIO_OTYPER_OT_15                    0x00008000U
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
-#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
-#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
-
-#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
-#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
-#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
-
-#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
-#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
-#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
-
-#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
-#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
-#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
-
-#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
-#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
-#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
-
-#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
-#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
-#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
-
-#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
-#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
-#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
-
-#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
-#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
-#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
-
-#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
-#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
-#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
-
-#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
-#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
-#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
-
-#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
-#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
-#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
-
-#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
-#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
-#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
-
-#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
-#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
-#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
-
-#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
-#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
-#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
-
-#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
-#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
-#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
-
-#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
-#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
-#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    0x00000003U
-#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
-#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
-
-#define GPIO_PUPDR_PUPDR1                    0x0000000CU
-#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
-#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
-
-#define GPIO_PUPDR_PUPDR2                    0x00000030U
-#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
-#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
-
-#define GPIO_PUPDR_PUPDR3                    0x000000C0U
-#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
-#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
-
-#define GPIO_PUPDR_PUPDR4                    0x00000300U
-#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
-#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
-
-#define GPIO_PUPDR_PUPDR5                    0x00000C00U
-#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
-#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
-
-#define GPIO_PUPDR_PUPDR6                    0x00003000U
-#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
-#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
-
-#define GPIO_PUPDR_PUPDR7                    0x0000C000U
-#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
-#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
-
-#define GPIO_PUPDR_PUPDR8                    0x00030000U
-#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
-#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
-
-#define GPIO_PUPDR_PUPDR9                    0x000C0000U
-#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
-#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
-
-#define GPIO_PUPDR_PUPDR10                   0x00300000U
-#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
-#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
-
-#define GPIO_PUPDR_PUPDR11                   0x00C00000U
-#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
-#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
-
-#define GPIO_PUPDR_PUPDR12                   0x03000000U
-#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
-#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
-
-#define GPIO_PUPDR_PUPDR13                   0x0C000000U
-#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
-#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
-
-#define GPIO_PUPDR_PUPDR14                   0x30000000U
-#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
-#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
-
-#define GPIO_PUPDR_PUPDR15                   0xC0000000U
-#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
-#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       0x00000001U
-#define GPIO_IDR_IDR_1                       0x00000002U
-#define GPIO_IDR_IDR_2                       0x00000004U
-#define GPIO_IDR_IDR_3                       0x00000008U
-#define GPIO_IDR_IDR_4                       0x00000010U
-#define GPIO_IDR_IDR_5                       0x00000020U
-#define GPIO_IDR_IDR_6                       0x00000040U
-#define GPIO_IDR_IDR_7                       0x00000080U
-#define GPIO_IDR_IDR_8                       0x00000100U
-#define GPIO_IDR_IDR_9                       0x00000200U
-#define GPIO_IDR_IDR_10                      0x00000400U
-#define GPIO_IDR_IDR_11                      0x00000800U
-#define GPIO_IDR_IDR_12                      0x00001000U
-#define GPIO_IDR_IDR_13                      0x00002000U
-#define GPIO_IDR_IDR_14                      0x00004000U
-#define GPIO_IDR_IDR_15                      0x00008000U
-/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
-#define GPIO_OTYPER_IDR_0                    GPIO_IDR_IDR_0
-#define GPIO_OTYPER_IDR_1                    GPIO_IDR_IDR_1
-#define GPIO_OTYPER_IDR_2                    GPIO_IDR_IDR_2
-#define GPIO_OTYPER_IDR_3                    GPIO_IDR_IDR_3
-#define GPIO_OTYPER_IDR_4                    GPIO_IDR_IDR_4
-#define GPIO_OTYPER_IDR_5                    GPIO_IDR_IDR_5
-#define GPIO_OTYPER_IDR_6                    GPIO_IDR_IDR_6
-#define GPIO_OTYPER_IDR_7                    GPIO_IDR_IDR_7
-#define GPIO_OTYPER_IDR_8                    GPIO_IDR_IDR_8
-#define GPIO_OTYPER_IDR_9                    GPIO_IDR_IDR_9
-#define GPIO_OTYPER_IDR_10                   GPIO_IDR_IDR_10
-#define GPIO_OTYPER_IDR_11                   GPIO_IDR_IDR_11
-#define GPIO_OTYPER_IDR_12                   GPIO_IDR_IDR_12
-#define GPIO_OTYPER_IDR_13                   GPIO_IDR_IDR_13
-#define GPIO_OTYPER_IDR_14                   GPIO_IDR_IDR_14
-#define GPIO_OTYPER_IDR_15                   GPIO_IDR_IDR_15
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       0x00000001U
-#define GPIO_ODR_ODR_1                       0x00000002U
-#define GPIO_ODR_ODR_2                       0x00000004U
-#define GPIO_ODR_ODR_3                       0x00000008U
-#define GPIO_ODR_ODR_4                       0x00000010U
-#define GPIO_ODR_ODR_5                       0x00000020U
-#define GPIO_ODR_ODR_6                       0x00000040U
-#define GPIO_ODR_ODR_7                       0x00000080U
-#define GPIO_ODR_ODR_8                       0x00000100U
-#define GPIO_ODR_ODR_9                       0x00000200U
-#define GPIO_ODR_ODR_10                      0x00000400U
-#define GPIO_ODR_ODR_11                      0x00000800U
-#define GPIO_ODR_ODR_12                      0x00001000U
-#define GPIO_ODR_ODR_13                      0x00002000U
-#define GPIO_ODR_ODR_14                      0x00004000U
-#define GPIO_ODR_ODR_15                      0x00008000U
-/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
-#define GPIO_OTYPER_ODR_0                    GPIO_ODR_ODR_0
-#define GPIO_OTYPER_ODR_1                    GPIO_ODR_ODR_1
-#define GPIO_OTYPER_ODR_2                    GPIO_ODR_ODR_2
-#define GPIO_OTYPER_ODR_3                    GPIO_ODR_ODR_3
-#define GPIO_OTYPER_ODR_4                    GPIO_ODR_ODR_4
-#define GPIO_OTYPER_ODR_5                    GPIO_ODR_ODR_5
-#define GPIO_OTYPER_ODR_6                    GPIO_ODR_ODR_6
-#define GPIO_OTYPER_ODR_7                    GPIO_ODR_ODR_7
-#define GPIO_OTYPER_ODR_8                    GPIO_ODR_ODR_8
-#define GPIO_OTYPER_ODR_9                    GPIO_ODR_ODR_9
-#define GPIO_OTYPER_ODR_10                   GPIO_ODR_ODR_10
-#define GPIO_OTYPER_ODR_11                   GPIO_ODR_ODR_11
-#define GPIO_OTYPER_ODR_12                   GPIO_ODR_ODR_12
-#define GPIO_OTYPER_ODR_13                   GPIO_ODR_ODR_13
-#define GPIO_OTYPER_ODR_14                   GPIO_ODR_ODR_14
-#define GPIO_OTYPER_ODR_15                   GPIO_ODR_ODR_15
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       0x00000001U
-#define GPIO_BSRR_BS_1                       0x00000002U
-#define GPIO_BSRR_BS_2                       0x00000004U
-#define GPIO_BSRR_BS_3                       0x00000008U
-#define GPIO_BSRR_BS_4                       0x00000010U
-#define GPIO_BSRR_BS_5                       0x00000020U
-#define GPIO_BSRR_BS_6                       0x00000040U
-#define GPIO_BSRR_BS_7                       0x00000080U
-#define GPIO_BSRR_BS_8                       0x00000100U
-#define GPIO_BSRR_BS_9                       0x00000200U
-#define GPIO_BSRR_BS_10                      0x00000400U
-#define GPIO_BSRR_BS_11                      0x00000800U
-#define GPIO_BSRR_BS_12                      0x00001000U
-#define GPIO_BSRR_BS_13                      0x00002000U
-#define GPIO_BSRR_BS_14                      0x00004000U
-#define GPIO_BSRR_BS_15                      0x00008000U
-#define GPIO_BSRR_BR_0                       0x00010000U
-#define GPIO_BSRR_BR_1                       0x00020000U
-#define GPIO_BSRR_BR_2                       0x00040000U
-#define GPIO_BSRR_BR_3                       0x00080000U
-#define GPIO_BSRR_BR_4                       0x00100000U
-#define GPIO_BSRR_BR_5                       0x00200000U
-#define GPIO_BSRR_BR_6                       0x00400000U
-#define GPIO_BSRR_BR_7                       0x00800000U
-#define GPIO_BSRR_BR_8                       0x01000000U
-#define GPIO_BSRR_BR_9                       0x02000000U
-#define GPIO_BSRR_BR_10                      0x04000000U
-#define GPIO_BSRR_BR_11                      0x08000000U
-#define GPIO_BSRR_BR_12                      0x10000000U
-#define GPIO_BSRR_BR_13                      0x20000000U
-#define GPIO_BSRR_BR_14                      0x40000000U
-#define GPIO_BSRR_BR_15                      0x80000000U
-
-/****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0                       0x00000001U
-#define GPIO_LCKR_LCK1                       0x00000002U
-#define GPIO_LCKR_LCK2                       0x00000004U
-#define GPIO_LCKR_LCK3                       0x00000008U
-#define GPIO_LCKR_LCK4                       0x00000010U
-#define GPIO_LCKR_LCK5                       0x00000020U
-#define GPIO_LCKR_LCK6                       0x00000040U
-#define GPIO_LCKR_LCK7                       0x00000080U
-#define GPIO_LCKR_LCK8                       0x00000100U
-#define GPIO_LCKR_LCK9                       0x00000200U
-#define GPIO_LCKR_LCK10                      0x00000400U
-#define GPIO_LCKR_LCK11                      0x00000800U
-#define GPIO_LCKR_LCK12                      0x00001000U
-#define GPIO_LCKR_LCK13                      0x00002000U
-#define GPIO_LCKR_LCK14                      0x00004000U
-#define GPIO_LCKR_LCK15                      0x00008000U
-#define GPIO_LCKR_LCKK                       0x00010000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Inter-integrated Circuit Interface                    */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          0x00000001U     /*!<Peripheral Enable                             */
-#define  I2C_CR1_SMBUS                       0x00000002U     /*!<SMBus Mode                                    */
-#define  I2C_CR1_SMBTYPE                     0x00000008U     /*!<SMBus Type                                    */
-#define  I2C_CR1_ENARP                       0x00000010U     /*!<ARP Enable                                    */
-#define  I2C_CR1_ENPEC                       0x00000020U     /*!<PEC Enable                                    */
-#define  I2C_CR1_ENGC                        0x00000040U     /*!<General Call Enable                           */
-#define  I2C_CR1_NOSTRETCH                   0x00000080U     /*!<Clock Stretching Disable (Slave mode)  */
-#define  I2C_CR1_START                       0x00000100U     /*!<Start Generation                              */
-#define  I2C_CR1_STOP                        0x00000200U     /*!<Stop Generation                               */
-#define  I2C_CR1_ACK                         0x00000400U     /*!<Acknowledge Enable                            */
-#define  I2C_CR1_POS                         0x00000800U     /*!<Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         0x00001000U     /*!<Packet Error Checking                         */
-#define  I2C_CR1_ALERT                       0x00002000U     /*!<SMBus Alert                                   */
-#define  I2C_CR1_SWRST                       0x00008000U     /*!<Software Reset                                */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        0x0000003FU     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
-#define  I2C_CR2_FREQ_0                      0x00000001U     /*!<Bit 0 */
-#define  I2C_CR2_FREQ_1                      0x00000002U     /*!<Bit 1 */
-#define  I2C_CR2_FREQ_2                      0x00000004U     /*!<Bit 2 */
-#define  I2C_CR2_FREQ_3                      0x00000008U     /*!<Bit 3 */
-#define  I2C_CR2_FREQ_4                      0x00000010U     /*!<Bit 4 */
-#define  I2C_CR2_FREQ_5                      0x00000020U     /*!<Bit 5 */
-
-#define  I2C_CR2_ITERREN                     0x00000100U     /*!<Error Interrupt Enable  */
-#define  I2C_CR2_ITEVTEN                     0x00000200U     /*!<Event Interrupt Enable  */
-#define  I2C_CR2_ITBUFEN                     0x00000400U     /*!<Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       0x00000800U     /*!<DMA Requests Enable     */
-#define  I2C_CR2_LAST                        0x00001000U     /*!<DMA Last Transfer       */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     0x000000FEU     /*!<Interface Address */
-#define  I2C_OAR1_ADD8_9                     0x00000300U     /*!<Interface Address */
-
-#define  I2C_OAR1_ADD0                       0x00000001U     /*!<Bit 0 */
-#define  I2C_OAR1_ADD1                       0x00000002U     /*!<Bit 1 */
-#define  I2C_OAR1_ADD2                       0x00000004U     /*!<Bit 2 */
-#define  I2C_OAR1_ADD3                       0x00000008U     /*!<Bit 3 */
-#define  I2C_OAR1_ADD4                       0x00000010U     /*!<Bit 4 */
-#define  I2C_OAR1_ADD5                       0x00000020U     /*!<Bit 5 */
-#define  I2C_OAR1_ADD6                       0x00000040U     /*!<Bit 6 */
-#define  I2C_OAR1_ADD7                       0x00000080U     /*!<Bit 7 */
-#define  I2C_OAR1_ADD8                       0x00000100U     /*!<Bit 8 */
-#define  I2C_OAR1_ADD9                       0x00000200U     /*!<Bit 9 */
-
-#define  I2C_OAR1_ADDMODE                    0x00008000U     /*!<Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     0x00000001U        /*!<Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       0x000000FEU        /*!<Interface address           */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           0x000000FFU        /*!<8-bit Data Register         */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          0x00000001U     /*!<Start Bit (Master mode)                  */
-#define  I2C_SR1_ADDR                        0x00000002U     /*!<Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         0x00000004U     /*!<Byte Transfer Finished                          */
-#define  I2C_SR1_ADD10                       0x00000008U     /*!<10-bit header sent (Master mode)         */
-#define  I2C_SR1_STOPF                       0x00000010U     /*!<Stop detection (Slave mode)              */
-#define  I2C_SR1_RXNE                        0x00000040U     /*!<Data Register not Empty (receivers)      */
-#define  I2C_SR1_TXE                         0x00000080U     /*!<Data Register Empty (transmitters)       */
-#define  I2C_SR1_BERR                        0x00000100U     /*!<Bus Error                                       */
-#define  I2C_SR1_ARLO                        0x00000200U     /*!<Arbitration Lost (master mode)           */
-#define  I2C_SR1_AF                          0x00000400U     /*!<Acknowledge Failure                             */
-#define  I2C_SR1_OVR                         0x00000800U     /*!<Overrun/Underrun                                */
-#define  I2C_SR1_PECERR                      0x00001000U     /*!<PEC Error in reception                          */
-#define  I2C_SR1_TIMEOUT                     0x00004000U     /*!<Timeout or Tlow Error                           */
-#define  I2C_SR1_SMBALERT                    0x00008000U     /*!<SMBus Alert                                     */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         0x00000001U     /*!<Master/Slave                              */
-#define  I2C_SR2_BUSY                        0x00000002U     /*!<Bus Busy                                  */
-#define  I2C_SR2_TRA                         0x00000004U     /*!<Transmitter/Receiver                      */
-#define  I2C_SR2_GENCALL                     0x00000010U     /*!<General Call Address (Slave mode)  */
-#define  I2C_SR2_SMBDEFAULT                  0x00000020U     /*!<SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     0x00000040U     /*!<SMBus Host Header (Slave mode)     */
-#define  I2C_SR2_DUALF                       0x00000080U     /*!<Dual Flag (Slave mode)             */
-#define  I2C_SR2_PEC                         0x0000FF00U     /*!<Packet Error Checking Register            */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         0x00000FFFU     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        0x00004000U     /*!<Fast Mode Duty Cycle                                       */
-#define  I2C_CCR_FS                          0x00008000U     /*!<I2C Master Mode Selection                                  */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     0x0000003FU     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************  Bit definition for I2C_FLTR register  *******************/
-#define  I2C_FLTR_DNF                        0x0000000FU     /*!<Digital Noise Filter */
-#define  I2C_FLTR_ANOFF                      0x00000010U     /*!<Analog Noise Filter OFF */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Independent WATCHDOG                             */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         0x01U               /*!<Watchdog prescaler value update      */
-#define  IWDG_SR_RVU                         0x02U               /*!<Watchdog counter reload value update */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                             Power Control                                  */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
-#define  PWR_CR_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
-#define  PWR_CR_CWUF                         0x00000004U     /*!< Clear Wakeup Flag                   */
-#define  PWR_CR_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
-#define  PWR_CR_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
-
-#define  PWR_CR_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        0x00000020U     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        0x00000040U     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        0x00000080U     /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
-#define  PWR_CR_DBP                          0x00000100U     /*!< Disable Backup Domain write protection                     */
-#define  PWR_CR_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                              */
-#define  PWR_CR_LPLVDS                       0x00000400U     /*!< Low-Power Regulator Low Voltage Scaling in Stop mode       */
-#define  PWR_CR_MRLVDS                       0x00000800U     /*!< Main regulator Low Voltage Scaling in Stop mode            */
-#define  PWR_CR_ADCDC1                       0x00002000U     /*!< Refer to AN4073 on how to use this bit */ 
-#define  PWR_CR_VOS                          0x0000C000U     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
-#define  PWR_CR_VOS_0                        0x00004000U     /*!< Bit 0 */
-#define  PWR_CR_VOS_1                        0x00008000U     /*!< Bit 1 */
-#define  PWR_CR_ODEN                         0x00010000U     /*!< Over Drive enable                   */
-#define  PWR_CR_ODSWEN                       0x00020000U     /*!< Over Drive switch enabled           */
-#define  PWR_CR_UDEN                         0x000C0000U     /*!< Under Drive enable in stop mode     */
-#define  PWR_CR_UDEN_0                       0x00040000U     /*!< Bit 0                               */
-#define  PWR_CR_UDEN_1                       0x00080000U     /*!< Bit 1                               */
-
-/* Legacy define */
-#define  PWR_CR_PMODE                        PWR_CR_VOS
-#define  PWR_CR_LPUDS                        PWR_CR_LPLVDS     /*!< Low-Power Regulator in deepsleep under-drive mode          */
-#define  PWR_CR_MRUDS                        PWR_CR_MRLVDS     /*!< Main regulator in deepsleep under-drive mode               */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         0x00000001U     /*!< Wakeup Flag                                      */
-#define  PWR_CSR_SBF                         0x00000002U     /*!< Standby Flag                                     */
-#define  PWR_CSR_PVDO                        0x00000004U     /*!< PVD Output                                       */
-#define  PWR_CSR_BRR                         0x00000008U     /*!< Backup regulator ready                           */
-#define  PWR_CSR_EWUP                        0x00000100U     /*!< Enable WKUP pin                                  */
-#define  PWR_CSR_BRE                         0x00000200U     /*!< Backup regulator enable                          */
-#define  PWR_CSR_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
-#define  PWR_CSR_ODRDY                       0x00010000U     /*!< Over Drive generator ready                       */
-#define  PWR_CSR_ODSWRDY                     0x00020000U     /*!< Over Drive Switch ready                          */
-#define  PWR_CSR_UDSWRDY                     0x000C0000U     /*!< Under Drive ready                                */
-
-/* Legacy define */
-#define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        0x00000001U
-#define  RCC_CR_HSIRDY                       0x00000002U
-
-#define  RCC_CR_HSITRIM                      0x000000F8U
-#define  RCC_CR_HSITRIM_0                    0x00000008U/*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    0x00000010U/*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    0x00000020U/*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    0x00000040U/*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    0x00000080U/*!<Bit 4 */
-
-#define  RCC_CR_HSICAL                       0x0000FF00U
-#define  RCC_CR_HSICAL_0                     0x00000100U/*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     0x00000200U/*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     0x00000400U/*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     0x00000800U/*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     0x00001000U/*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     0x00002000U/*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     0x00004000U/*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     0x00008000U/*!<Bit 7 */
-
-#define  RCC_CR_HSEON                        0x00010000U
-#define  RCC_CR_HSERDY                       0x00020000U
-#define  RCC_CR_HSEBYP                       0x00040000U
-#define  RCC_CR_CSSON                        0x00080000U
-#define  RCC_CR_PLLON                        0x01000000U
-#define  RCC_CR_PLLRDY                       0x02000000U
-#define  RCC_CR_PLLI2SON                     0x04000000U
-#define  RCC_CR_PLLI2SRDY                    0x08000000U
-#define  RCC_CR_PLLSAION                     0x10000000U
-#define  RCC_CR_PLLSAIRDY                    0x20000000U
-
-/********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    0x0000003FU
-#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
-#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
-#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
-#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
-#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
-#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
-
-#define  RCC_PLLCFGR_PLLN                     0x00007FC0U
-#define  RCC_PLLCFGR_PLLN_0                   0x00000040U
-#define  RCC_PLLCFGR_PLLN_1                   0x00000080U
-#define  RCC_PLLCFGR_PLLN_2                   0x00000100U
-#define  RCC_PLLCFGR_PLLN_3                   0x00000200U
-#define  RCC_PLLCFGR_PLLN_4                   0x00000400U
-#define  RCC_PLLCFGR_PLLN_5                   0x00000800U
-#define  RCC_PLLCFGR_PLLN_6                   0x00001000U
-#define  RCC_PLLCFGR_PLLN_7                   0x00002000U
-#define  RCC_PLLCFGR_PLLN_8                   0x00004000U
-
-#define  RCC_PLLCFGR_PLLP                    0x00030000U
-#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
-#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
-
-#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
-
-#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
-#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
-#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
-#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
-#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-/*!< SW configuration */
-#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
-
-#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
-
-#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
-
-#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
-
-/*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     0x001F0000U
-#define  RCC_CFGR_RTCPRE_0                   0x00010000U
-#define  RCC_CFGR_RTCPRE_1                   0x00020000U
-#define  RCC_CFGR_RTCPRE_2                   0x00040000U
-#define  RCC_CFGR_RTCPRE_3                   0x00080000U
-#define  RCC_CFGR_RTCPRE_4                   0x00100000U
-
-/*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       0x00600000U
-#define  RCC_CFGR_MCO1_0                     0x00200000U
-#define  RCC_CFGR_MCO1_1                     0x00400000U
-
-#define  RCC_CFGR_I2SSRC                     0x00800000U
-
-#define  RCC_CFGR_MCO1PRE                    0x07000000U
-#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
-#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
-#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
-
-#define  RCC_CFGR_MCO2PRE                    0x38000000U
-#define  RCC_CFGR_MCO2PRE_0                  0x08000000U
-#define  RCC_CFGR_MCO2PRE_1                  0x10000000U
-#define  RCC_CFGR_MCO2PRE_2                  0x20000000U
-
-#define  RCC_CFGR_MCO2                       0xC0000000U
-#define  RCC_CFGR_MCO2_0                     0x40000000U
-#define  RCC_CFGR_MCO2_1                     0x80000000U
-
-/********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     0x00000001U
-#define  RCC_CIR_LSERDYF                     0x00000002U
-#define  RCC_CIR_HSIRDYF                     0x00000004U
-#define  RCC_CIR_HSERDYF                     0x00000008U
-#define  RCC_CIR_PLLRDYF                     0x00000010U
-#define  RCC_CIR_PLLI2SRDYF                  0x00000020U
-#define  RCC_CIR_PLLSAIRDYF                  0x00000040U
-#define  RCC_CIR_CSSF                        0x00000080U
-#define  RCC_CIR_LSIRDYIE                    0x00000100U
-#define  RCC_CIR_LSERDYIE                    0x00000200U
-#define  RCC_CIR_HSIRDYIE                    0x00000400U
-#define  RCC_CIR_HSERDYIE                    0x00000800U
-#define  RCC_CIR_PLLRDYIE                    0x00001000U
-#define  RCC_CIR_PLLI2SRDYIE                 0x00002000U
-#define  RCC_CIR_PLLSAIRDYIE                 0x00004000U
-#define  RCC_CIR_LSIRDYC                     0x00010000U
-#define  RCC_CIR_LSERDYC                     0x00020000U
-#define  RCC_CIR_HSIRDYC                     0x00040000U
-#define  RCC_CIR_HSERDYC                     0x00080000U
-#define  RCC_CIR_PLLRDYC                     0x00100000U
-#define  RCC_CIR_PLLI2SRDYC                  0x00200000U
-#define  RCC_CIR_PLLSAIRDYC                  0x00400000U
-#define  RCC_CIR_CSSC                        0x00800000U
-
-/********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
-#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
-#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
-#define  RCC_AHB1RSTR_GPIODRST               0x00000008U
-#define  RCC_AHB1RSTR_GPIOERST               0x00000010U
-#define  RCC_AHB1RSTR_GPIOFRST               0x00000020U
-#define  RCC_AHB1RSTR_GPIOGRST               0x00000040U
-#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
-#define  RCC_AHB1RSTR_GPIOIRST               0x00000100U
-#define  RCC_AHB1RSTR_GPIOJRST               0x00000200U
-#define  RCC_AHB1RSTR_GPIOKRST               0x00000400U
-#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
-#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
-#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
-#define  RCC_AHB1RSTR_DMA2DRST               0x00800000U
-#define  RCC_AHB1RSTR_ETHMACRST              0x02000000U
-#define  RCC_AHB1RSTR_OTGHRST                0x20000000U
-
-/********************  Bit definition for RCC_AHB2RSTR register  **************/
-#define  RCC_AHB2RSTR_DCMIRST                0x00000001U
-#define  RCC_AHB2RSTR_RNGRST                 0x00000040U
-#define  RCC_AHB2RSTR_OTGFSRST               0x00000080U
-
-/********************  Bit definition for RCC_AHB3RSTR register  **************/
-#define  RCC_AHB3RSTR_FMCRST                0x00000001U
-
-/********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM2RST                0x00000001U
-#define  RCC_APB1RSTR_TIM3RST                0x00000002U
-#define  RCC_APB1RSTR_TIM4RST                0x00000004U
-#define  RCC_APB1RSTR_TIM5RST                0x00000008U
-#define  RCC_APB1RSTR_TIM6RST                0x00000010U
-#define  RCC_APB1RSTR_TIM7RST                0x00000020U
-#define  RCC_APB1RSTR_TIM12RST               0x00000040U
-#define  RCC_APB1RSTR_TIM13RST               0x00000080U
-#define  RCC_APB1RSTR_TIM14RST               0x00000100U
-#define  RCC_APB1RSTR_WWDGRST                0x00000800U
-#define  RCC_APB1RSTR_SPI2RST                0x00004000U
-#define  RCC_APB1RSTR_SPI3RST                0x00008000U
-#define  RCC_APB1RSTR_USART2RST              0x00020000U
-#define  RCC_APB1RSTR_USART3RST              0x00040000U
-#define  RCC_APB1RSTR_UART4RST               0x00080000U
-#define  RCC_APB1RSTR_UART5RST               0x00100000U
-#define  RCC_APB1RSTR_I2C1RST                0x00200000U
-#define  RCC_APB1RSTR_I2C2RST                0x00400000U
-#define  RCC_APB1RSTR_I2C3RST                0x00800000U
-#define  RCC_APB1RSTR_CAN1RST                0x02000000U
-#define  RCC_APB1RSTR_CAN2RST                0x04000000U
-#define  RCC_APB1RSTR_PWRRST                 0x10000000U
-#define  RCC_APB1RSTR_DACRST                 0x20000000U
-#define  RCC_APB1RSTR_UART7RST               0x40000000U
-#define  RCC_APB1RSTR_UART8RST               0x80000000U
-
-/********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                0x00000001U
-#define  RCC_APB2RSTR_TIM8RST                0x00000002U
-#define  RCC_APB2RSTR_USART1RST              0x00000010U
-#define  RCC_APB2RSTR_USART6RST              0x00000020U
-#define  RCC_APB2RSTR_ADCRST                 0x00000100U
-#define  RCC_APB2RSTR_SDIORST                0x00000800U
-#define  RCC_APB2RSTR_SPI1RST                0x00001000U
-#define  RCC_APB2RSTR_SPI4RST                0x00002000U
-#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
-#define  RCC_APB2RSTR_TIM9RST                0x00010000U
-#define  RCC_APB2RSTR_TIM10RST               0x00020000U
-#define  RCC_APB2RSTR_TIM11RST               0x00040000U
-#define  RCC_APB2RSTR_SPI5RST                0x00100000U
-#define  RCC_APB2RSTR_SPI6RST                0x00200000U
-#define  RCC_APB2RSTR_SAI1RST                0x00400000U
-
-/* Old SPI1RST bit definition, maintained for legacy purpose */
-#define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
-
-/********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
-#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
-#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
-#define  RCC_AHB1ENR_GPIODEN                 0x00000008U
-#define  RCC_AHB1ENR_GPIOEEN                 0x00000010U
-#define  RCC_AHB1ENR_GPIOFEN                 0x00000020U
-#define  RCC_AHB1ENR_GPIOGEN                 0x00000040U
-#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
-#define  RCC_AHB1ENR_GPIOIEN                 0x00000100U
-#define  RCC_AHB1ENR_GPIOJEN                 0x00000200U
-#define  RCC_AHB1ENR_GPIOKEN                 0x00000400U
-
-#define  RCC_AHB1ENR_CRCEN                   0x00001000U
-#define  RCC_AHB1ENR_BKPSRAMEN               0x00040000U
-#define  RCC_AHB1ENR_CCMDATARAMEN            0x00100000U
-#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
-#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
-#define  RCC_AHB1ENR_DMA2DEN                 0x00800000U
-
-#define  RCC_AHB1ENR_ETHMACEN                0x02000000U
-#define  RCC_AHB1ENR_ETHMACTXEN              0x04000000U
-#define  RCC_AHB1ENR_ETHMACRXEN              0x08000000U
-#define  RCC_AHB1ENR_ETHMACPTPEN             0x10000000U
-#define  RCC_AHB1ENR_OTGHSEN                 0x20000000U
-#define  RCC_AHB1ENR_OTGHSULPIEN             0x40000000U
-
-/********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define  RCC_AHB2ENR_DCMIEN                  0x00000001U
-#define  RCC_AHB2ENR_RNGEN                   0x00000040U
-#define  RCC_AHB2ENR_OTGFSEN                 0x00000080U
-
-/********************  Bit definition for RCC_AHB3ENR register  ***************/
-#define  RCC_AHB3ENR_FMCEN                  0x00000001U
-
-/********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM2EN                  0x00000001U
-#define  RCC_APB1ENR_TIM3EN                  0x00000002U
-#define  RCC_APB1ENR_TIM4EN                  0x00000004U
-#define  RCC_APB1ENR_TIM5EN                  0x00000008U
-#define  RCC_APB1ENR_TIM6EN                  0x00000010U
-#define  RCC_APB1ENR_TIM7EN                  0x00000020U
-#define  RCC_APB1ENR_TIM12EN                 0x00000040U
-#define  RCC_APB1ENR_TIM13EN                 0x00000080U
-#define  RCC_APB1ENR_TIM14EN                 0x00000100U
-#define  RCC_APB1ENR_WWDGEN                  0x00000800U
-#define  RCC_APB1ENR_SPI2EN                  0x00004000U
-#define  RCC_APB1ENR_SPI3EN                  0x00008000U
-#define  RCC_APB1ENR_USART2EN                0x00020000U
-#define  RCC_APB1ENR_USART3EN                0x00040000U
-#define  RCC_APB1ENR_UART4EN                 0x00080000U
-#define  RCC_APB1ENR_UART5EN                 0x00100000U
-#define  RCC_APB1ENR_I2C1EN                  0x00200000U
-#define  RCC_APB1ENR_I2C2EN                  0x00400000U
-#define  RCC_APB1ENR_I2C3EN                  0x00800000U
-#define  RCC_APB1ENR_CAN1EN                  0x02000000U
-#define  RCC_APB1ENR_CAN2EN                  0x04000000U
-#define  RCC_APB1ENR_PWREN                   0x10000000U
-#define  RCC_APB1ENR_DACEN                   0x20000000U
-#define  RCC_APB1ENR_UART7EN                 0x40000000U
-#define  RCC_APB1ENR_UART8EN                 0x80000000U
-
-/********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  0x00000001U
-#define  RCC_APB2ENR_TIM8EN                  0x00000002U
-#define  RCC_APB2ENR_USART1EN                0x00000010U
-#define  RCC_APB2ENR_USART6EN                0x00000020U
-#define  RCC_APB2ENR_ADC1EN                  0x00000100U
-#define  RCC_APB2ENR_ADC2EN                  0x00000200U
-#define  RCC_APB2ENR_ADC3EN                  0x00000400U
-#define  RCC_APB2ENR_SDIOEN                  0x00000800U
-#define  RCC_APB2ENR_SPI1EN                  0x00001000U
-#define  RCC_APB2ENR_SPI4EN                  0x00002000U
-#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
-#define  RCC_APB2ENR_TIM9EN                  0x00010000U
-#define  RCC_APB2ENR_TIM10EN                 0x00020000U
-#define  RCC_APB2ENR_TIM11EN                 0x00040000U
-#define  RCC_APB2ENR_SPI5EN                  0x00100000U
-#define  RCC_APB2ENR_SPI6EN                  0x00200000U
-#define  RCC_APB2ENR_SAI1EN                  0x00400000U
-
-/********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
-#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
-#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
-#define  RCC_AHB1LPENR_GPIODLPEN             0x00000008U
-#define  RCC_AHB1LPENR_GPIOELPEN             0x00000010U
-#define  RCC_AHB1LPENR_GPIOFLPEN             0x00000020U
-#define  RCC_AHB1LPENR_GPIOGLPEN             0x00000040U
-#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
-#define  RCC_AHB1LPENR_GPIOILPEN             0x00000100U
-#define  RCC_AHB1LPENR_GPIOJLPEN             0x00000200U
-#define  RCC_AHB1LPENR_GPIOKLPEN             0x00000400U
-
-#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
-#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
-#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
-#define  RCC_AHB1LPENR_SRAM2LPEN             0x00020000U
-#define  RCC_AHB1LPENR_BKPSRAMLPEN           0x00040000U
-#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
-#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
-#define  RCC_AHB1LPENR_DMA2DLPEN             0x00800000U
-
-#define  RCC_AHB1LPENR_ETHMACLPEN            0x02000000U
-#define  RCC_AHB1LPENR_ETHMACTXLPEN          0x04000000U
-#define  RCC_AHB1LPENR_ETHMACRXLPEN          0x08000000U
-#define  RCC_AHB1LPENR_ETHMACPTPLPEN         0x10000000U
-#define  RCC_AHB1LPENR_OTGHSLPEN             0x20000000U
-#define  RCC_AHB1LPENR_OTGHSULPILPEN         0x40000000U
-
-/********************  Bit definition for RCC_AHB2LPENR register  *************/
-#define  RCC_AHB2LPENR_DCMILPEN              0x00000001U
-#define  RCC_AHB2LPENR_RNGLPEN               0x00000040U
-#define  RCC_AHB2LPENR_OTGFSLPEN             0x00000080U
-
-/********************  Bit definition for RCC_AHB3LPENR register  *************/
-#define  RCC_AHB3LPENR_FMCLPEN              0x00000001U
-
-/********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM2LPEN              0x00000001U
-#define  RCC_APB1LPENR_TIM3LPEN              0x00000002U
-#define  RCC_APB1LPENR_TIM4LPEN              0x00000004U
-#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
-#define  RCC_APB1LPENR_TIM6LPEN              0x00000010U
-#define  RCC_APB1LPENR_TIM7LPEN              0x00000020U
-#define  RCC_APB1LPENR_TIM12LPEN             0x00000040U
-#define  RCC_APB1LPENR_TIM13LPEN             0x00000080U
-#define  RCC_APB1LPENR_TIM14LPEN             0x00000100U
-#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
-#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U
-#define  RCC_APB1LPENR_SPI3LPEN              0x00008000U
-#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
-#define  RCC_APB1LPENR_USART3LPEN            0x00040000U
-#define  RCC_APB1LPENR_UART4LPEN             0x00080000U
-#define  RCC_APB1LPENR_UART5LPEN             0x00100000U
-#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
-#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
-#define  RCC_APB1LPENR_I2C3LPEN              0x00800000U
-#define  RCC_APB1LPENR_CAN1LPEN              0x02000000U
-#define  RCC_APB1LPENR_CAN2LPEN              0x04000000U
-#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
-#define  RCC_APB1LPENR_DACLPEN               0x20000000U
-#define  RCC_APB1LPENR_UART7LPEN             0x40000000U
-#define  RCC_APB1LPENR_UART8LPEN             0x80000000U
-
-/********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
-#define  RCC_APB2LPENR_TIM8LPEN              0x00000002U
-#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
-#define  RCC_APB2LPENR_USART6LPEN            0x00000020U
-#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
-#define  RCC_APB2LPENR_ADC2LPEN              0x00000200U
-#define  RCC_APB2LPENR_ADC3LPEN              0x00000400U
-#define  RCC_APB2LPENR_SDIOLPEN              0x00000800U
-#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
-#define  RCC_APB2LPENR_SPI4LPEN              0x00002000U
-#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
-#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
-#define  RCC_APB2LPENR_TIM10LPEN             0x00020000U
-#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
-#define  RCC_APB2LPENR_SPI5LPEN              0x00100000U
-#define  RCC_APB2LPENR_SPI6LPEN              0x00200000U
-#define  RCC_APB2LPENR_SAI1LPEN              0x00400000U
-
-/********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      0x00000001U
-#define  RCC_BDCR_LSERDY                     0x00000002U
-#define  RCC_BDCR_LSEBYP                     0x00000004U
-
-#define  RCC_BDCR_RTCSEL                    0x00000300U
-#define  RCC_BDCR_RTCSEL_0                  0x00000100U
-#define  RCC_BDCR_RTCSEL_1                  0x00000200U
-
-#define  RCC_BDCR_RTCEN                      0x00008000U
-#define  RCC_BDCR_BDRST                      0x00010000U
-
-/********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       0x00000001U
-#define  RCC_CSR_LSIRDY                      0x00000002U
-#define  RCC_CSR_RMVF                        0x01000000U
-#define  RCC_CSR_BORRSTF                     0x02000000U
-#define  RCC_CSR_PADRSTF                     0x04000000U
-#define  RCC_CSR_PORRSTF                     0x08000000U
-#define  RCC_CSR_SFTRSTF                     0x10000000U
-#define  RCC_CSR_WDGRSTF                     0x20000000U
-#define  RCC_CSR_WWDGRSTF                    0x40000000U
-#define  RCC_CSR_LPWRRSTF                    0x80000000U
-
-/********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    0x00001FFFU
-#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
-#define  RCC_SSCGR_SPREADSEL                 0x40000000U
-#define  RCC_SSCGR_SSCGEN                    0x80000000U
-
-/********************  Bit definition for RCC_PLLI2SCFGR register  ************/
-#define  RCC_PLLI2SCFGR_PLLI2SN              0x00007FC0U
-#define  RCC_PLLI2SCFGR_PLLI2SN_0            0x00000040U
-#define  RCC_PLLI2SCFGR_PLLI2SN_1            0x00000080U
-#define  RCC_PLLI2SCFGR_PLLI2SN_2            0x00000100U
-#define  RCC_PLLI2SCFGR_PLLI2SN_3            0x00000200U
-#define  RCC_PLLI2SCFGR_PLLI2SN_4            0x00000400U
-#define  RCC_PLLI2SCFGR_PLLI2SN_5            0x00000800U
-#define  RCC_PLLI2SCFGR_PLLI2SN_6            0x00001000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_7            0x00002000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_8            0x00004000U
-
-#define  RCC_PLLI2SCFGR_PLLI2SQ              0x0F000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_0            0x01000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_1            0x02000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_2            0x04000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_3            0x08000000U
-
-#define  RCC_PLLI2SCFGR_PLLI2SR              0x70000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_0            0x10000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_1            0x20000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_2            0x40000000U
-
-
-/********************  Bit definition for RCC_PLLSAICFGR register  ************/
-#define  RCC_PLLSAICFGR_PLLSAIN              0x00007FC0U
-#define  RCC_PLLSAICFGR_PLLSAIN_0            0x00000040U
-#define  RCC_PLLSAICFGR_PLLSAIN_1            0x00000080U
-#define  RCC_PLLSAICFGR_PLLSAIN_2            0x00000100U
-#define  RCC_PLLSAICFGR_PLLSAIN_3            0x00000200U
-#define  RCC_PLLSAICFGR_PLLSAIN_4            0x00000400U
-#define  RCC_PLLSAICFGR_PLLSAIN_5            0x00000800U
-#define  RCC_PLLSAICFGR_PLLSAIN_6            0x00001000U
-#define  RCC_PLLSAICFGR_PLLSAIN_7            0x00002000U
-#define  RCC_PLLSAICFGR_PLLSAIN_8            0x00004000U
-
-#define  RCC_PLLSAICFGR_PLLSAIQ              0x0F000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_0            0x01000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_1            0x02000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_2            0x04000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_3            0x08000000U
-
-#define  RCC_PLLSAICFGR_PLLSAIR              0x70000000U
-#define  RCC_PLLSAICFGR_PLLSAIR_0            0x10000000U
-#define  RCC_PLLSAICFGR_PLLSAIR_1            0x20000000U
-#define  RCC_PLLSAICFGR_PLLSAIR_2            0x40000000U
-
-/********************  Bit definition for RCC_DCKCFGR register  ***************/
-#define  RCC_DCKCFGR_PLLI2SDIVQ              0x0000001FU
-#define  RCC_DCKCFGR_PLLSAIDIVQ              0x00001F00U
-#define  RCC_DCKCFGR_PLLSAIDIVR              0x00030000U
-#define  RCC_DCKCFGR_SAI1ASRC                0x00300000U
-#define  RCC_DCKCFGR_SAI1ASRC_0              0x00100000U
-#define  RCC_DCKCFGR_SAI1ASRC_1              0x00200000U
-#define  RCC_DCKCFGR_SAI1BSRC                0x00C00000U
-#define  RCC_DCKCFGR_SAI1BSRC_0              0x00400000U
-#define  RCC_DCKCFGR_SAI1BSRC_1              0x00800000U
-#define  RCC_DCKCFGR_TIMPRE                  0x01000000U
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    RNG                                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN                         0x00000004U
-#define RNG_CR_IE                            0x00000008U
-
-/********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY                          0x00000001U
-#define RNG_SR_CECS                          0x00000002U
-#define RNG_SR_SECS                          0x00000004U
-#define RNG_SR_CEIS                          0x00000020U
-#define RNG_SR_SEIS                          0x00000040U
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            0x00400000U
-#define RTC_TR_HT                            0x00300000U
-#define RTC_TR_HT_0                          0x00100000U
-#define RTC_TR_HT_1                          0x00200000U
-#define RTC_TR_HU                            0x000F0000U
-#define RTC_TR_HU_0                          0x00010000U
-#define RTC_TR_HU_1                          0x00020000U
-#define RTC_TR_HU_2                          0x00040000U
-#define RTC_TR_HU_3                          0x00080000U
-#define RTC_TR_MNT                           0x00007000U
-#define RTC_TR_MNT_0                         0x00001000U
-#define RTC_TR_MNT_1                         0x00002000U
-#define RTC_TR_MNT_2                         0x00004000U
-#define RTC_TR_MNU                           0x00000F00U
-#define RTC_TR_MNU_0                         0x00000100U
-#define RTC_TR_MNU_1                         0x00000200U
-#define RTC_TR_MNU_2                         0x00000400U
-#define RTC_TR_MNU_3                         0x00000800U
-#define RTC_TR_ST                            0x00000070U
-#define RTC_TR_ST_0                          0x00000010U
-#define RTC_TR_ST_1                          0x00000020U
-#define RTC_TR_ST_2                          0x00000040U
-#define RTC_TR_SU                            0x0000000FU
-#define RTC_TR_SU_0                          0x00000001U
-#define RTC_TR_SU_1                          0x00000002U
-#define RTC_TR_SU_2                          0x00000004U
-#define RTC_TR_SU_3                          0x00000008U
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            0x00F00000U
-#define RTC_DR_YT_0                          0x00100000U
-#define RTC_DR_YT_1                          0x00200000U
-#define RTC_DR_YT_2                          0x00400000U
-#define RTC_DR_YT_3                          0x00800000U
-#define RTC_DR_YU                            0x000F0000U
-#define RTC_DR_YU_0                          0x00010000U
-#define RTC_DR_YU_1                          0x00020000U
-#define RTC_DR_YU_2                          0x00040000U
-#define RTC_DR_YU_3                          0x00080000U
-#define RTC_DR_WDU                           0x0000E000U
-#define RTC_DR_WDU_0                         0x00002000U
-#define RTC_DR_WDU_1                         0x00004000U
-#define RTC_DR_WDU_2                         0x00008000U
-#define RTC_DR_MT                            0x00001000U
-#define RTC_DR_MU                            0x00000F00U
-#define RTC_DR_MU_0                          0x00000100U
-#define RTC_DR_MU_1                          0x00000200U
-#define RTC_DR_MU_2                          0x00000400U
-#define RTC_DR_MU_3                          0x00000800U
-#define RTC_DR_DT                            0x00000030U
-#define RTC_DR_DT_0                          0x00000010U
-#define RTC_DR_DT_1                          0x00000020U
-#define RTC_DR_DU                            0x0000000FU
-#define RTC_DR_DU_0                          0x00000001U
-#define RTC_DR_DU_1                          0x00000002U
-#define RTC_DR_DU_2                          0x00000004U
-#define RTC_DR_DU_3                          0x00000008U
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           0x00800000U
-#define RTC_CR_OSEL                          0x00600000U
-#define RTC_CR_OSEL_0                        0x00200000U
-#define RTC_CR_OSEL_1                        0x00400000U
-#define RTC_CR_POL                           0x00100000U
-#define RTC_CR_COSEL                         0x00080000U
-#define RTC_CR_BCK                           0x00040000U
-#define RTC_CR_SUB1H                         0x00020000U
-#define RTC_CR_ADD1H                         0x00010000U
-#define RTC_CR_TSIE                          0x00008000U
-#define RTC_CR_WUTIE                         0x00004000U
-#define RTC_CR_ALRBIE                        0x00002000U
-#define RTC_CR_ALRAIE                        0x00001000U
-#define RTC_CR_TSE                           0x00000800U
-#define RTC_CR_WUTE                          0x00000400U
-#define RTC_CR_ALRBE                         0x00000200U
-#define RTC_CR_ALRAE                         0x00000100U
-#define RTC_CR_DCE                           0x00000080U
-#define RTC_CR_FMT                           0x00000040U
-#define RTC_CR_BYPSHAD                       0x00000020U
-#define RTC_CR_REFCKON                       0x00000010U
-#define RTC_CR_TSEDGE                        0x00000008U
-#define RTC_CR_WUCKSEL                       0x00000007U
-#define RTC_CR_WUCKSEL_0                     0x00000001U
-#define RTC_CR_WUCKSEL_1                     0x00000002U
-#define RTC_CR_WUCKSEL_2                     0x00000004U
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      0x00010000U
-#define RTC_ISR_TAMP1F                       0x00002000U
-#define RTC_ISR_TAMP2F                       0x00004000U
-#define RTC_ISR_TSOVF                        0x00001000U
-#define RTC_ISR_TSF                          0x00000800U
-#define RTC_ISR_WUTF                         0x00000400U
-#define RTC_ISR_ALRBF                        0x00000200U
-#define RTC_ISR_ALRAF                        0x00000100U
-#define RTC_ISR_INIT                         0x00000080U
-#define RTC_ISR_INITF                        0x00000040U
-#define RTC_ISR_RSF                          0x00000020U
-#define RTC_ISR_INITS                        0x00000010U
-#define RTC_ISR_SHPF                         0x00000008U
-#define RTC_ISR_WUTWF                        0x00000004U
-#define RTC_ISR_ALRBWF                       0x00000002U
-#define RTC_ISR_ALRAWF                       0x00000001U
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    0x007F0000U
-#define RTC_PRER_PREDIV_S                    0x00007FFFU
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS                       0x00000080U
-#define RTC_CALIBR_DC                        0x0000001FU
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      0x80000000U
-#define RTC_ALRMAR_WDSEL                     0x40000000U
-#define RTC_ALRMAR_DT                        0x30000000U
-#define RTC_ALRMAR_DT_0                      0x10000000U
-#define RTC_ALRMAR_DT_1                      0x20000000U
-#define RTC_ALRMAR_DU                        0x0F000000U
-#define RTC_ALRMAR_DU_0                      0x01000000U
-#define RTC_ALRMAR_DU_1                      0x02000000U
-#define RTC_ALRMAR_DU_2                      0x04000000U
-#define RTC_ALRMAR_DU_3                      0x08000000U
-#define RTC_ALRMAR_MSK3                      0x00800000U
-#define RTC_ALRMAR_PM                        0x00400000U
-#define RTC_ALRMAR_HT                        0x00300000U
-#define RTC_ALRMAR_HT_0                      0x00100000U
-#define RTC_ALRMAR_HT_1                      0x00200000U
-#define RTC_ALRMAR_HU                        0x000F0000U
-#define RTC_ALRMAR_HU_0                      0x00010000U
-#define RTC_ALRMAR_HU_1                      0x00020000U
-#define RTC_ALRMAR_HU_2                      0x00040000U
-#define RTC_ALRMAR_HU_3                      0x00080000U
-#define RTC_ALRMAR_MSK2                      0x00008000U
-#define RTC_ALRMAR_MNT                       0x00007000U
-#define RTC_ALRMAR_MNT_0                     0x00001000U
-#define RTC_ALRMAR_MNT_1                     0x00002000U
-#define RTC_ALRMAR_MNT_2                     0x00004000U
-#define RTC_ALRMAR_MNU                       0x00000F00U
-#define RTC_ALRMAR_MNU_0                     0x00000100U
-#define RTC_ALRMAR_MNU_1                     0x00000200U
-#define RTC_ALRMAR_MNU_2                     0x00000400U
-#define RTC_ALRMAR_MNU_3                     0x00000800U
-#define RTC_ALRMAR_MSK1                      0x00000080U
-#define RTC_ALRMAR_ST                        0x00000070U
-#define RTC_ALRMAR_ST_0                      0x00000010U
-#define RTC_ALRMAR_ST_1                      0x00000020U
-#define RTC_ALRMAR_ST_2                      0x00000040U
-#define RTC_ALRMAR_SU                        0x0000000FU
-#define RTC_ALRMAR_SU_0                      0x00000001U
-#define RTC_ALRMAR_SU_1                      0x00000002U
-#define RTC_ALRMAR_SU_2                      0x00000004U
-#define RTC_ALRMAR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      0x80000000U
-#define RTC_ALRMBR_WDSEL                     0x40000000U
-#define RTC_ALRMBR_DT                        0x30000000U
-#define RTC_ALRMBR_DT_0                      0x10000000U
-#define RTC_ALRMBR_DT_1                      0x20000000U
-#define RTC_ALRMBR_DU                        0x0F000000U
-#define RTC_ALRMBR_DU_0                      0x01000000U
-#define RTC_ALRMBR_DU_1                      0x02000000U
-#define RTC_ALRMBR_DU_2                      0x04000000U
-#define RTC_ALRMBR_DU_3                      0x08000000U
-#define RTC_ALRMBR_MSK3                      0x00800000U
-#define RTC_ALRMBR_PM                        0x00400000U
-#define RTC_ALRMBR_HT                        0x00300000U
-#define RTC_ALRMBR_HT_0                      0x00100000U
-#define RTC_ALRMBR_HT_1                      0x00200000U
-#define RTC_ALRMBR_HU                        0x000F0000U
-#define RTC_ALRMBR_HU_0                      0x00010000U
-#define RTC_ALRMBR_HU_1                      0x00020000U
-#define RTC_ALRMBR_HU_2                      0x00040000U
-#define RTC_ALRMBR_HU_3                      0x00080000U
-#define RTC_ALRMBR_MSK2                      0x00008000U
-#define RTC_ALRMBR_MNT                       0x00007000U
-#define RTC_ALRMBR_MNT_0                     0x00001000U
-#define RTC_ALRMBR_MNT_1                     0x00002000U
-#define RTC_ALRMBR_MNT_2                     0x00004000U
-#define RTC_ALRMBR_MNU                       0x00000F00U
-#define RTC_ALRMBR_MNU_0                     0x00000100U
-#define RTC_ALRMBR_MNU_1                     0x00000200U
-#define RTC_ALRMBR_MNU_2                     0x00000400U
-#define RTC_ALRMBR_MNU_3                     0x00000800U
-#define RTC_ALRMBR_MSK1                      0x00000080U
-#define RTC_ALRMBR_ST                        0x00000070U
-#define RTC_ALRMBR_ST_0                      0x00000010U
-#define RTC_ALRMBR_ST_1                      0x00000020U
-#define RTC_ALRMBR_ST_2                      0x00000040U
-#define RTC_ALRMBR_SU                        0x0000000FU
-#define RTC_ALRMBR_SU_0                      0x00000001U
-#define RTC_ALRMBR_SU_1                      0x00000002U
-#define RTC_ALRMBR_SU_2                      0x00000004U
-#define RTC_ALRMBR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          0x000000FFU
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           0x0000FFFFU
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     0x00007FFFU
-#define RTC_SHIFTR_ADD1S                     0x80000000U
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          0x00400000U
-#define RTC_TSTR_HT                          0x00300000U
-#define RTC_TSTR_HT_0                        0x00100000U
-#define RTC_TSTR_HT_1                        0x00200000U
-#define RTC_TSTR_HU                          0x000F0000U
-#define RTC_TSTR_HU_0                        0x00010000U
-#define RTC_TSTR_HU_1                        0x00020000U
-#define RTC_TSTR_HU_2                        0x00040000U
-#define RTC_TSTR_HU_3                        0x00080000U
-#define RTC_TSTR_MNT                         0x00007000U
-#define RTC_TSTR_MNT_0                       0x00001000U
-#define RTC_TSTR_MNT_1                       0x00002000U
-#define RTC_TSTR_MNT_2                       0x00004000U
-#define RTC_TSTR_MNU                         0x00000F00U
-#define RTC_TSTR_MNU_0                       0x00000100U
-#define RTC_TSTR_MNU_1                       0x00000200U
-#define RTC_TSTR_MNU_2                       0x00000400U
-#define RTC_TSTR_MNU_3                       0x00000800U
-#define RTC_TSTR_ST                          0x00000070U
-#define RTC_TSTR_ST_0                        0x00000010U
-#define RTC_TSTR_ST_1                        0x00000020U
-#define RTC_TSTR_ST_2                        0x00000040U
-#define RTC_TSTR_SU                          0x0000000FU
-#define RTC_TSTR_SU_0                        0x00000001U
-#define RTC_TSTR_SU_1                        0x00000002U
-#define RTC_TSTR_SU_2                        0x00000004U
-#define RTC_TSTR_SU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         0x0000E000U
-#define RTC_TSDR_WDU_0                       0x00002000U
-#define RTC_TSDR_WDU_1                       0x00004000U
-#define RTC_TSDR_WDU_2                       0x00008000U
-#define RTC_TSDR_MT                          0x00001000U
-#define RTC_TSDR_MU                          0x00000F00U
-#define RTC_TSDR_MU_0                        0x00000100U
-#define RTC_TSDR_MU_1                        0x00000200U
-#define RTC_TSDR_MU_2                        0x00000400U
-#define RTC_TSDR_MU_3                        0x00000800U
-#define RTC_TSDR_DT                          0x00000030U
-#define RTC_TSDR_DT_0                        0x00000010U
-#define RTC_TSDR_DT_1                        0x00000020U
-#define RTC_TSDR_DU                          0x0000000FU
-#define RTC_TSDR_DU_0                        0x00000001U
-#define RTC_TSDR_DU_1                        0x00000002U
-#define RTC_TSDR_DU_2                        0x00000004U
-#define RTC_TSDR_DU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        0x00008000U
-#define RTC_CALR_CALW8                       0x00004000U
-#define RTC_CALR_CALW16                      0x00002000U
-#define RTC_CALR_CALM                        0x000001FFU
-#define RTC_CALR_CALM_0                      0x00000001U
-#define RTC_CALR_CALM_1                      0x00000002U
-#define RTC_CALR_CALM_2                      0x00000004U
-#define RTC_CALR_CALM_3                      0x00000008U
-#define RTC_CALR_CALM_4                      0x00000010U
-#define RTC_CALR_CALM_5                      0x00000020U
-#define RTC_CALR_CALM_6                      0x00000040U
-#define RTC_CALR_CALM_7                      0x00000080U
-#define RTC_CALR_CALM_8                      0x00000100U
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               0x00040000U
-#define RTC_TAFCR_TSINSEL                    0x00020000U
-#define RTC_TAFCR_TAMPINSEL                  0x00010000U
-#define RTC_TAFCR_TAMPPUDIS                  0x00008000U
-#define RTC_TAFCR_TAMPPRCH                   0x00006000U
-#define RTC_TAFCR_TAMPPRCH_0                 0x00002000U
-#define RTC_TAFCR_TAMPPRCH_1                 0x00004000U
-#define RTC_TAFCR_TAMPFLT                    0x00001800U
-#define RTC_TAFCR_TAMPFLT_0                  0x00000800U
-#define RTC_TAFCR_TAMPFLT_1                  0x00001000U
-#define RTC_TAFCR_TAMPFREQ                   0x00000700U
-#define RTC_TAFCR_TAMPFREQ_0                 0x00000100U
-#define RTC_TAFCR_TAMPFREQ_1                 0x00000200U
-#define RTC_TAFCR_TAMPFREQ_2                 0x00000400U
-#define RTC_TAFCR_TAMPTS                     0x00000080U
-#define RTC_TAFCR_TAMP2TRG                   0x00000010U
-#define RTC_TAFCR_TAMP2E                     0x00000008U
-#define RTC_TAFCR_TAMPIE                     0x00000004U
-#define RTC_TAFCR_TAMP1TRG                   0x00000002U
-#define RTC_TAFCR_TAMP1E                     0x00000001U
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  0x0F000000U
-#define RTC_ALRMASSR_MASKSS_0                0x01000000U
-#define RTC_ALRMASSR_MASKSS_1                0x02000000U
-#define RTC_ALRMASSR_MASKSS_2                0x04000000U
-#define RTC_ALRMASSR_MASKSS_3                0x08000000U
-#define RTC_ALRMASSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
-#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
-#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
-#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
-#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
-#define RTC_ALRMBSSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           0xFFFFFFFFU
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Serial Audio Interface                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for SAI_GCR register  *******************/
-#define  SAI_GCR_SYNCIN                  0x00000003U        /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
-#define  SAI_GCR_SYNCIN_0                0x00000001U        /*!<Bit 0 */
-#define  SAI_GCR_SYNCIN_1                0x00000002U        /*!<Bit 1 */
-
-#define  SAI_GCR_SYNCOUT                 0x00000030U        /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
-#define  SAI_GCR_SYNCOUT_0               0x00000010U        /*!<Bit 0 */
-#define  SAI_GCR_SYNCOUT_1               0x00000020U        /*!<Bit 1 */
-
-/*******************  Bit definition for SAI_xCR1 register  *******************/
-#define  SAI_xCR1_MODE                    0x00000003U        /*!<MODE[1:0] bits (Audio Block Mode)           */
-#define  SAI_xCR1_MODE_0                  0x00000001U        /*!<Bit 0 */
-#define  SAI_xCR1_MODE_1                  0x00000002U        /*!<Bit 1 */
-
-#define  SAI_xCR1_PRTCFG                  0x0000000CU        /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
-#define  SAI_xCR1_PRTCFG_0                0x00000004U        /*!<Bit 0 */
-#define  SAI_xCR1_PRTCFG_1                0x00000008U        /*!<Bit 1 */
-
-#define  SAI_xCR1_DS                      0x000000E0U        /*!<DS[1:0] bits (Data Size) */
-#define  SAI_xCR1_DS_0                    0x00000020U        /*!<Bit 0 */
-#define  SAI_xCR1_DS_1                    0x00000040U        /*!<Bit 1 */
-#define  SAI_xCR1_DS_2                    0x00000080U        /*!<Bit 2 */
-
-#define  SAI_xCR1_LSBFIRST                0x00000100U        /*!<LSB First Configuration  */
-#define  SAI_xCR1_CKSTR                   0x00000200U        /*!<ClocK STRobing edge      */
-
-#define  SAI_xCR1_SYNCEN                  0x00000C00U        /*!<SYNCEN[1:0](SYNChronization ENable) */
-#define  SAI_xCR1_SYNCEN_0                0x00000400U        /*!<Bit 0 */
-#define  SAI_xCR1_SYNCEN_1                0x00000800U        /*!<Bit 1 */
-
-#define  SAI_xCR1_MONO                    0x00001000U        /*!<Mono mode                  */
-#define  SAI_xCR1_OUTDRIV                 0x00002000U        /*!<Output Drive               */
-#define  SAI_xCR1_SAIEN                   0x00010000U        /*!<Audio Block enable         */
-#define  SAI_xCR1_DMAEN                   0x00020000U        /*!<DMA enable                 */
-#define  SAI_xCR1_NODIV                   0x00080000U        /*!<No Divider Configuration   */
-
-#define  SAI_xCR1_MCKDIV                  0x00F00000U        /*!<MCKDIV[3:0] (Master ClocK Divider)  */
-#define  SAI_xCR1_MCKDIV_0                0x00100000U        /*!<Bit 0  */
-#define  SAI_xCR1_MCKDIV_1                0x00200000U        /*!<Bit 1  */
-#define  SAI_xCR1_MCKDIV_2                0x00400000U        /*!<Bit 2  */
-#define  SAI_xCR1_MCKDIV_3                0x00800000U        /*!<Bit 3  */
-
-/*******************  Bit definition for SAI_xCR2 register  *******************/
-#define  SAI_xCR2_FTH                     0x00000007U        /*!<FTH[2:0](Fifo THreshold)  */
-#define  SAI_xCR2_FTH_0                   0x00000001U        /*!<Bit 0 */
-#define  SAI_xCR2_FTH_1                   0x00000002U        /*!<Bit 1 */
-#define  SAI_xCR2_FTH_2                   0x00000004U        /*!<Bit 2 */
-
-#define  SAI_xCR2_FFLUSH                  0x00000008U        /*!<Fifo FLUSH                       */
-#define  SAI_xCR2_TRIS                    0x00000010U        /*!<TRIState Management on data line */
-#define  SAI_xCR2_MUTE                    0x00000020U        /*!<Mute mode                        */
-#define  SAI_xCR2_MUTEVAL                 0x00000040U        /*!<Muate value                      */
-
-#define  SAI_xCR2_MUTECNT                  0x00001F80U       /*!<MUTECNT[5:0] (MUTE counter) */
-#define  SAI_xCR2_MUTECNT_0               0x00000080U        /*!<Bit 0 */
-#define  SAI_xCR2_MUTECNT_1               0x00000100U        /*!<Bit 1 */
-#define  SAI_xCR2_MUTECNT_2               0x00000200U        /*!<Bit 2 */
-#define  SAI_xCR2_MUTECNT_3               0x00000400U        /*!<Bit 3 */
-#define  SAI_xCR2_MUTECNT_4               0x00000800U        /*!<Bit 4 */
-#define  SAI_xCR2_MUTECNT_5               0x00001000U        /*!<Bit 5 */
-
-#define  SAI_xCR2_CPL                     0x00002000U        /*!< Complement Bit             */
-
-#define  SAI_xCR2_COMP                    0x0000C000U        /*!<COMP[1:0] (Companding mode) */
-#define  SAI_xCR2_COMP_0                  0x00004000U        /*!<Bit 0 */
-#define  SAI_xCR2_COMP_1                  0x00008000U        /*!<Bit 1 */
-
-/******************  Bit definition for SAI_xFRCR register  *******************/
-#define  SAI_xFRCR_FRL                    0x000000FFU        /*!<FRL[1:0](Frame length)  */
-#define  SAI_xFRCR_FRL_0                  0x00000001U        /*!<Bit 0 */
-#define  SAI_xFRCR_FRL_1                  0x00000002U        /*!<Bit 1 */
-#define  SAI_xFRCR_FRL_2                  0x00000004U        /*!<Bit 2 */
-#define  SAI_xFRCR_FRL_3                  0x00000008U        /*!<Bit 3 */
-#define  SAI_xFRCR_FRL_4                  0x00000010U        /*!<Bit 4 */
-#define  SAI_xFRCR_FRL_5                  0x00000020U        /*!<Bit 5 */
-#define  SAI_xFRCR_FRL_6                  0x00000040U        /*!<Bit 6 */
-#define  SAI_xFRCR_FRL_7                  0x00000080U        /*!<Bit 7 */
-
-#define  SAI_xFRCR_FSALL                  0x00007F00U        /*!<FRL[1:0] (Frame synchronization active level length)  */
-#define  SAI_xFRCR_FSALL_0                0x00000100U        /*!<Bit 0 */
-#define  SAI_xFRCR_FSALL_1                0x00000200U        /*!<Bit 1 */
-#define  SAI_xFRCR_FSALL_2                0x00000400U        /*!<Bit 2 */
-#define  SAI_xFRCR_FSALL_3                0x00000800U        /*!<Bit 3 */
-#define  SAI_xFRCR_FSALL_4                0x00001000U        /*!<Bit 4 */
-#define  SAI_xFRCR_FSALL_5                0x00002000U        /*!<Bit 5 */
-#define  SAI_xFRCR_FSALL_6                0x00004000U        /*!<Bit 6 */
-
-#define  SAI_xFRCR_FSDEF                  0x00010000U        /*!< Frame Synchronization Definition */
-#define  SAI_xFRCR_FSPOL                  0x00020000U        /*!<Frame Synchronization POLarity    */
-#define  SAI_xFRCR_FSOFF                  0x00040000U        /*!<Frame Synchronization OFFset      */
-/* Legacy defines */
-#define  SAI_xFRCR_FSPO                   SAI_xFRCR_FSPOL
-
-/******************  Bit definition for SAI_xSLOTR register  *******************/
-#define  SAI_xSLOTR_FBOFF                 0x0000001FU        /*!<FRL[4:0](First Bit Offset)  */
-#define  SAI_xSLOTR_FBOFF_0               0x00000001U        /*!<Bit 0 */
-#define  SAI_xSLOTR_FBOFF_1               0x00000002U        /*!<Bit 1 */
-#define  SAI_xSLOTR_FBOFF_2               0x00000004U        /*!<Bit 2 */
-#define  SAI_xSLOTR_FBOFF_3               0x00000008U        /*!<Bit 3 */
-#define  SAI_xSLOTR_FBOFF_4               0x00000010U        /*!<Bit 4 */
-
-#define  SAI_xSLOTR_SLOTSZ                0x000000C0U        /*!<SLOTSZ[1:0] (Slot size)  */
-#define  SAI_xSLOTR_SLOTSZ_0              0x00000040U        /*!<Bit 0 */
-#define  SAI_xSLOTR_SLOTSZ_1              0x00000080U        /*!<Bit 1 */
-
-#define  SAI_xSLOTR_NBSLOT                0x00000F00U        /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
-#define  SAI_xSLOTR_NBSLOT_0              0x00000100U        /*!<Bit 0 */
-#define  SAI_xSLOTR_NBSLOT_1              0x00000200U        /*!<Bit 1 */
-#define  SAI_xSLOTR_NBSLOT_2              0x00000400U        /*!<Bit 2 */
-#define  SAI_xSLOTR_NBSLOT_3              0x00000800U        /*!<Bit 3 */
-
-#define  SAI_xSLOTR_SLOTEN                0xFFFF0000U        /*!<SLOTEN[15:0] (Slot Enable)  */
-
-/*******************  Bit definition for SAI_xIMR register  *******************/
-#define  SAI_xIMR_OVRUDRIE                0x00000001U        /*!<Overrun underrun interrupt enable                              */
-#define  SAI_xIMR_MUTEDETIE               0x00000002U        /*!<Mute detection interrupt enable                                */
-#define  SAI_xIMR_WCKCFGIE                0x00000004U        /*!<Wrong Clock Configuration interrupt enable                     */
-#define  SAI_xIMR_FREQIE                  0x00000008U        /*!<FIFO request interrupt enable                                  */
-#define  SAI_xIMR_CNRDYIE                 0x00000010U        /*!<Codec not ready interrupt enable                               */
-#define  SAI_xIMR_AFSDETIE                0x00000020U        /*!<Anticipated frame synchronization detection interrupt enable   */
-#define  SAI_xIMR_LFSDETIE                0x00000040U        /*!<Late frame synchronization detection interrupt enable          */
-
-/********************  Bit definition for SAI_xSR register  *******************/
-#define  SAI_xSR_OVRUDR                   0x00000001U         /*!<Overrun underrun                               */
-#define  SAI_xSR_MUTEDET                  0x00000002U         /*!<Mute detection                                 */
-#define  SAI_xSR_WCKCFG                   0x00000004U         /*!<Wrong Clock Configuration                      */
-#define  SAI_xSR_FREQ                     0x00000008U         /*!<FIFO request                                   */
-#define  SAI_xSR_CNRDY                    0x00000010U         /*!<Codec not ready                                */
-#define  SAI_xSR_AFSDET                   0x00000020U         /*!<Anticipated frame synchronization detection    */
-#define  SAI_xSR_LFSDET                   0x00000040U         /*!<Late frame synchronization detection           */
-
-#define  SAI_xSR_FLVL                     0x00070000U         /*!<FLVL[2:0] (FIFO Level Threshold)               */
-#define  SAI_xSR_FLVL_0                   0x00010000U         /*!<Bit 0 */
-#define  SAI_xSR_FLVL_1                   0x00020000U         /*!<Bit 1 */
-#define  SAI_xSR_FLVL_2                   0x00040000U         /*!<Bit 2 */
-
-/******************  Bit definition for SAI_xCLRFR register  ******************/
-#define  SAI_xCLRFR_COVRUDR               0x00000001U        /*!<Clear Overrun underrun                               */
-#define  SAI_xCLRFR_CMUTEDET              0x00000002U        /*!<Clear Mute detection                                 */
-#define  SAI_xCLRFR_CWCKCFG               0x00000004U        /*!<Clear Wrong Clock Configuration                      */
-#define  SAI_xCLRFR_CFREQ                 0x00000008U        /*!<Clear FIFO request                                   */
-#define  SAI_xCLRFR_CCNRDY                0x00000010U        /*!<Clear Codec not ready                                */
-#define  SAI_xCLRFR_CAFSDET               0x00000020U        /*!<Clear Anticipated frame synchronization detection    */
-#define  SAI_xCLRFR_CLFSDET               0x00000040U        /*!<Clear Late frame synchronization detection           */
-
-/******************  Bit definition for SAI_xDR register  ******************/
-#define  SAI_xDR_DATA                     0xFFFFFFFFU        
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          SD host Interface                                 */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SDIO_POWER register  ******************/
-#define  SDIO_POWER_PWRCTRL                  0x03U               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDIO_POWER_PWRCTRL_0                0x01U               /*!<Bit 0 */
-#define  SDIO_POWER_PWRCTRL_1                0x02U               /*!<Bit 1 */
-
-/******************  Bit definition for SDIO_CLKCR register  ******************/
-#define  SDIO_CLKCR_CLKDIV                   0x00FFU            /*!<Clock divide factor             */
-#define  SDIO_CLKCR_CLKEN                    0x0100U            /*!<Clock enable bit                */
-#define  SDIO_CLKCR_PWRSAV                   0x0200U            /*!<Power saving configuration bit  */
-#define  SDIO_CLKCR_BYPASS                   0x0400U            /*!<Clock divider bypass enable bit */
-
-#define  SDIO_CLKCR_WIDBUS                   0x1800U            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDIO_CLKCR_WIDBUS_0                 0x0800U            /*!<Bit 0 */
-#define  SDIO_CLKCR_WIDBUS_1                 0x1000U            /*!<Bit 1 */
-
-#define  SDIO_CLKCR_NEGEDGE                  0x2000U            /*!<SDIO_CK dephasing selection bit */
-#define  SDIO_CLKCR_HWFC_EN                  0x4000U            /*!<HW Flow Control enable          */
-
-/*******************  Bit definition for SDIO_ARG register  *******************/
-#define  SDIO_ARG_CMDARG                     0xFFFFFFFFU            /*!<Command argument */
-
-/*******************  Bit definition for SDIO_CMD register  *******************/
-#define  SDIO_CMD_CMDINDEX                   0x003FU            /*!<Command Index                               */
-
-#define  SDIO_CMD_WAITRESP                   0x00C0U            /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDIO_CMD_WAITRESP_0                 0x0040U            /*!< Bit 0 */
-#define  SDIO_CMD_WAITRESP_1                 0x0080U            /*!< Bit 1 */
-
-#define  SDIO_CMD_WAITINT                    0x0100U            /*!<CPSM Waits for Interrupt Request                               */
-#define  SDIO_CMD_WAITPEND                   0x0200U            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDIO_CMD_CPSMEN                     0x0400U            /*!<Command path state machine (CPSM) Enable bit                   */
-#define  SDIO_CMD_SDIOSUSPEND                0x0800U            /*!<SD I/O suspend command                                         */
-#define  SDIO_CMD_ENCMDCOMPL                 0x1000U            /*!<Enable CMD completion                                          */
-#define  SDIO_CMD_NIEN                       0x2000U            /*!<Not Interrupt Enable */
-#define  SDIO_CMD_CEATACMD                   0x4000U            /*!<CE-ATA command       */
-
-/*****************  Bit definition for SDIO_RESPCMD register  *****************/
-#define  SDIO_RESPCMD_RESPCMD                0x3FU               /*!<Response command index */
-
-/******************  Bit definition for SDIO_RESP0 register  ******************/
-#define  SDIO_RESP0_CARDSTATUS0              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP1 register  ******************/
-#define  SDIO_RESP1_CARDSTATUS1              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP2 register  ******************/
-#define  SDIO_RESP2_CARDSTATUS2              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP3 register  ******************/
-#define  SDIO_RESP3_CARDSTATUS3              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP4 register  ******************/
-#define  SDIO_RESP4_CARDSTATUS4              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_DTIMER register  *****************/
-#define  SDIO_DTIMER_DATATIME                0xFFFFFFFFU        /*!<Data timeout period. */
-
-/******************  Bit definition for SDIO_DLEN register  *******************/
-#define  SDIO_DLEN_DATALENGTH                0x01FFFFFFU        /*!<Data length value    */
-
-/******************  Bit definition for SDIO_DCTRL register  ******************/
-#define  SDIO_DCTRL_DTEN                     0x0001U            /*!<Data transfer enabled bit         */
-#define  SDIO_DCTRL_DTDIR                    0x0002U            /*!<Data transfer direction selection */
-#define  SDIO_DCTRL_DTMODE                   0x0004U            /*!<Data transfer mode selection      */
-#define  SDIO_DCTRL_DMAEN                    0x0008U            /*!<DMA enabled bit                   */
-
-#define  SDIO_DCTRL_DBLOCKSIZE               0x00F0U            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDIO_DCTRL_DBLOCKSIZE_0             0x0010U            /*!<Bit 0 */
-#define  SDIO_DCTRL_DBLOCKSIZE_1             0x0020U            /*!<Bit 1 */
-#define  SDIO_DCTRL_DBLOCKSIZE_2             0x0040U            /*!<Bit 2 */
-#define  SDIO_DCTRL_DBLOCKSIZE_3             0x0080U            /*!<Bit 3 */
-
-#define  SDIO_DCTRL_RWSTART                  0x0100U            /*!<Read wait start         */
-#define  SDIO_DCTRL_RWSTOP                   0x0200U            /*!<Read wait stop          */
-#define  SDIO_DCTRL_RWMOD                    0x0400U            /*!<Read wait mode          */
-#define  SDIO_DCTRL_SDIOEN                   0x0800U            /*!<SD I/O enable functions */
-
-/******************  Bit definition for SDIO_DCOUNT register  *****************/
-#define  SDIO_DCOUNT_DATACOUNT               0x01FFFFFFU        /*!<Data count value */
-
-/******************  Bit definition for SDIO_STA register  ********************/
-#define  SDIO_STA_CCRCFAIL                   0x00000001U        /*!<Command response received (CRC check failed)  */
-#define  SDIO_STA_DCRCFAIL                   0x00000002U        /*!<Data block sent/received (CRC check failed)   */
-#define  SDIO_STA_CTIMEOUT                   0x00000004U        /*!<Command response timeout                      */
-#define  SDIO_STA_DTIMEOUT                   0x00000008U        /*!<Data timeout                                  */
-#define  SDIO_STA_TXUNDERR                   0x00000010U        /*!<Transmit FIFO underrun error                  */
-#define  SDIO_STA_RXOVERR                    0x00000020U        /*!<Received FIFO overrun error                   */
-#define  SDIO_STA_CMDREND                    0x00000040U        /*!<Command response received (CRC check passed)  */
-#define  SDIO_STA_CMDSENT                    0x00000080U        /*!<Command sent (no response required)           */
-#define  SDIO_STA_DATAEND                    0x00000100U        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
-#define  SDIO_STA_STBITERR                   0x00000200U        /*!<Start bit not detected on all data signals in wide bus mode */
-#define  SDIO_STA_DBCKEND                    0x00000400U        /*!<Data block sent/received (CRC check passed)   */
-#define  SDIO_STA_CMDACT                     0x00000800U        /*!<Command transfer in progress                  */
-#define  SDIO_STA_TXACT                      0x00001000U        /*!<Data transmit in progress                     */
-#define  SDIO_STA_RXACT                      0x00002000U        /*!<Data receive in progress                      */
-#define  SDIO_STA_TXFIFOHE                   0x00004000U        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDIO_STA_RXFIFOHF                   0x00008000U        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDIO_STA_TXFIFOF                    0x00010000U        /*!<Transmit FIFO full                            */
-#define  SDIO_STA_RXFIFOF                    0x00020000U        /*!<Receive FIFO full                             */
-#define  SDIO_STA_TXFIFOE                    0x00040000U        /*!<Transmit FIFO empty                           */
-#define  SDIO_STA_RXFIFOE                    0x00080000U        /*!<Receive FIFO empty                            */
-#define  SDIO_STA_TXDAVL                     0x00100000U        /*!<Data available in transmit FIFO               */
-#define  SDIO_STA_RXDAVL                     0x00200000U        /*!<Data available in receive FIFO                */
-#define  SDIO_STA_SDIOIT                     0x00400000U        /*!<SDIO interrupt received                       */
-#define  SDIO_STA_CEATAEND                   0x00800000U        /*!<CE-ATA command completion signal received for CMD61 */
-
-/*******************  Bit definition for SDIO_ICR register  *******************/
-#define  SDIO_ICR_CCRCFAILC                  0x00000001U        /*!<CCRCFAIL flag clear bit */
-#define  SDIO_ICR_DCRCFAILC                  0x00000002U        /*!<DCRCFAIL flag clear bit */
-#define  SDIO_ICR_CTIMEOUTC                  0x00000004U        /*!<CTIMEOUT flag clear bit */
-#define  SDIO_ICR_DTIMEOUTC                  0x00000008U        /*!<DTIMEOUT flag clear bit */
-#define  SDIO_ICR_TXUNDERRC                  0x00000010U        /*!<TXUNDERR flag clear bit */
-#define  SDIO_ICR_RXOVERRC                   0x00000020U        /*!<RXOVERR flag clear bit  */
-#define  SDIO_ICR_CMDRENDC                   0x00000040U        /*!<CMDREND flag clear bit  */
-#define  SDIO_ICR_CMDSENTC                   0x00000080U        /*!<CMDSENT flag clear bit  */
-#define  SDIO_ICR_DATAENDC                   0x00000100U        /*!<DATAEND flag clear bit  */
-#define  SDIO_ICR_STBITERRC                  0x00000200U        /*!<STBITERR flag clear bit */
-#define  SDIO_ICR_DBCKENDC                   0x00000400U        /*!<DBCKEND flag clear bit  */
-#define  SDIO_ICR_SDIOITC                    0x00400000U        /*!<SDIOIT flag clear bit   */
-#define  SDIO_ICR_CEATAENDC                  0x00800000U        /*!<CEATAEND flag clear bit */
-
-/******************  Bit definition for SDIO_MASK register  *******************/
-#define  SDIO_MASK_CCRCFAILIE                0x00000001U        /*!<Command CRC Fail Interrupt Enable          */
-#define  SDIO_MASK_DCRCFAILIE                0x00000002U        /*!<Data CRC Fail Interrupt Enable             */
-#define  SDIO_MASK_CTIMEOUTIE                0x00000004U        /*!<Command TimeOut Interrupt Enable           */
-#define  SDIO_MASK_DTIMEOUTIE                0x00000008U        /*!<Data TimeOut Interrupt Enable              */
-#define  SDIO_MASK_TXUNDERRIE                0x00000010U        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
-#define  SDIO_MASK_RXOVERRIE                 0x00000020U        /*!<Rx FIFO OverRun Error Interrupt Enable     */
-#define  SDIO_MASK_CMDRENDIE                 0x00000040U        /*!<Command Response Received Interrupt Enable */
-#define  SDIO_MASK_CMDSENTIE                 0x00000080U        /*!<Command Sent Interrupt Enable              */
-#define  SDIO_MASK_DATAENDIE                 0x00000100U        /*!<Data End Interrupt Enable                  */
-#define  SDIO_MASK_STBITERRIE                0x00000200U        /*!<Start Bit Error Interrupt Enable           */
-#define  SDIO_MASK_DBCKENDIE                 0x00000400U        /*!<Data Block End Interrupt Enable            */
-#define  SDIO_MASK_CMDACTIE                  0x00000800U        /*!<CCommand Acting Interrupt Enable           */
-#define  SDIO_MASK_TXACTIE                   0x00001000U        /*!<Data Transmit Acting Interrupt Enable      */
-#define  SDIO_MASK_RXACTIE                   0x00002000U        /*!<Data receive acting interrupt enabled      */
-#define  SDIO_MASK_TXFIFOHEIE                0x00004000U        /*!<Tx FIFO Half Empty interrupt Enable        */
-#define  SDIO_MASK_RXFIFOHFIE                0x00008000U        /*!<Rx FIFO Half Full interrupt Enable         */
-#define  SDIO_MASK_TXFIFOFIE                 0x00010000U        /*!<Tx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_RXFIFOFIE                 0x00020000U        /*!<Rx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_TXFIFOEIE                 0x00040000U        /*!<Tx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_RXFIFOEIE                 0x00080000U        /*!<Rx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_TXDAVLIE                  0x00100000U        /*!<Data available in Tx FIFO interrupt Enable */
-#define  SDIO_MASK_RXDAVLIE                  0x00200000U        /*!<Data available in Rx FIFO interrupt Enable */
-#define  SDIO_MASK_SDIOITIE                  0x00400000U        /*!<SDIO Mode Interrupt Received interrupt Enable */
-#define  SDIO_MASK_CEATAENDIE                0x00800000U        /*!<CE-ATA command completion signal received Interrupt Enable */
-
-/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
-#define  SDIO_FIFOCNT_FIFOCOUNT              0x00FFFFFFU        /*!<Remaining number of words to be written to or read from the FIFO */
-
-/******************  Bit definition for SDIO_FIFO register  *******************/
-#define  SDIO_FIFO_FIFODATA                  0xFFFFFFFFU        /*!<Receive and transmit FIFO data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        0x00000001U            /*!<Clock Phase      */
-#define  SPI_CR1_CPOL                        0x00000002U            /*!<Clock Polarity   */
-#define  SPI_CR1_MSTR                        0x00000004U            /*!<Master Selection */
-
-#define  SPI_CR1_BR                          0x00000038U            /*!<BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        0x00000008U            /*!<Bit 0 */
-#define  SPI_CR1_BR_1                        0x00000010U            /*!<Bit 1 */
-#define  SPI_CR1_BR_2                        0x00000020U            /*!<Bit 2 */
-
-#define  SPI_CR1_SPE                         0x00000040U            /*!<SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    0x00000080U            /*!<Frame Format                        */
-#define  SPI_CR1_SSI                         0x00000100U            /*!<Internal slave select               */
-#define  SPI_CR1_SSM                         0x00000200U            /*!<Software slave management           */
-#define  SPI_CR1_RXONLY                      0x00000400U            /*!<Receive only                        */
-#define  SPI_CR1_DFF                         0x00000800U            /*!<Data Frame Format                   */
-#define  SPI_CR1_CRCNEXT                     0x00001000U            /*!<Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       0x00002000U            /*!<Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      0x00004000U            /*!<Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    0x00008000U            /*!<Bidirectional data mode enable      */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     0x00000001U               /*!<Rx Buffer DMA Enable                 */
-#define  SPI_CR2_TXDMAEN                     0x00000002U               /*!<Tx Buffer DMA Enable                 */
-#define  SPI_CR2_SSOE                        0x00000004U               /*!<SS Output Enable                     */
-#define  SPI_CR2_FRF                         0x00000010U               /*!<Frame Format                         */
-#define  SPI_CR2_ERRIE                       0x00000020U               /*!<Error Interrupt Enable               */
-#define  SPI_CR2_RXNEIE                      0x00000040U               /*!<RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       0x00000080U               /*!<Tx buffer Empty Interrupt Enable     */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         0x00000001U               /*!<Receive buffer Not Empty */
-#define  SPI_SR_TXE                          0x00000002U               /*!<Transmit buffer Empty    */
-#define  SPI_SR_CHSIDE                       0x00000004U               /*!<Channel side             */
-#define  SPI_SR_UDR                          0x00000008U               /*!<Underrun flag            */
-#define  SPI_SR_CRCERR                       0x00000010U               /*!<CRC Error flag           */
-#define  SPI_SR_MODF                         0x00000020U               /*!<Mode fault               */
-#define  SPI_SR_OVR                          0x00000040U               /*!<Overrun flag             */
-#define  SPI_SR_BSY                          0x00000080U               /*!<Busy flag                */
-#define  SPI_SR_FRE                          0x00000100U               /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           0x0000FFFFU            /*!<Data Register           */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   0x0000FFFFU            /*!<CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    0x0000FFFFU            /*!<Rx CRC Register         */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    0x0000FFFFU            /*!<Tx CRC Register         */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   0x00000001U            /*!<Channel length (number of bits per audio channel) */
-
-#define  SPI_I2SCFGR_DATLEN                  0x00000006U            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define  SPI_I2SCFGR_DATLEN_0                0x00000002U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                0x00000004U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_CKPOL                   0x00000008U            /*!<steady state clock polarity               */
-
-#define  SPI_I2SCFGR_I2SSTD                  0x00000030U            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U            /*!<PCM frame synchronization                 */
-
-#define  SPI_I2SCFGR_I2SCFG                  0x00000300U            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_I2SE                    0x00000400U            /*!<I2S Enable         */
-#define  SPI_I2SCFGR_I2SMOD                  0x00000800U            /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    0x000000FFU            /*!<I2S Linear prescaler         */
-#define  SPI_I2SPR_ODD                       0x00000100U            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     0x00000200U            /*!<Master Clock Output Enable   */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 SYSCFG                                     */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
-#define SYSCFG_MEMRMP_MEM_MODE          0x00000007U /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        0x00000001U
-#define SYSCFG_MEMRMP_MEM_MODE_1        0x00000002U
-#define SYSCFG_MEMRMP_MEM_MODE_2        0x00000004U
-
-#define SYSCFG_MEMRMP_UFB_MODE          0x00000100U /*!< User Flash Bank mode    */
-#define SYSCFG_SWP_FMC                  0x00000C00U /*!< FMC memory mapping swap */
-
-/******************  Bit definition for SYSCFG_PMC register  ******************/
-#define SYSCFG_PMC_ADCxDC2              0x00070000U /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC1DC2              0x00010000U /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC2DC2              0x00020000U /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC3DC2              0x00040000U /*!< Refer to AN4073 on how to use this bit  */
-
-#define SYSCFG_PMC_MII_RMII_SEL         0x00800000U /*!<Ethernet PHY interface selection */
-/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
-#define SYSCFG_PMC_MII_RMII             SYSCFG_PMC_MII_RMII_SEL
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
-/** 
-  * @brief   EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         0x0003U /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         0x0004U /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         0x0005U /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         0x0006U /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PI         0x0008U /*!<PI[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PJ         0x0009U /*!<PJ[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PK         0x000AU /*!<PK[0] pin */
-
-/** 
-  * @brief   EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         0x0030U /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         0x0040U /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         0x0050U /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         0x0060U /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PI         0x0080U /*!<PI[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PJ         0x0090U /*!<PJ[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PK         0x00A0U /*!<PK[1] pin */
-
-
-/** 
-  * @brief   EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         0x0300U /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         0x0400U /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         0x0500U /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         0x0600U /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PI         0x0800U /*!<PI[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PJ         0x0900U /*!<PJ[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PK         0x0A00U /*!<PK[2] pin */
-
-
-/** 
-  * @brief   EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         0x3000U /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         0x4000U /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         0x5000U /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         0x6000U /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PI         0x8000U /*!<PI[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PJ         0x9000U /*!<PJ[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PK         0xA000U /*!<PK[3] pin */
-
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
-/** 
-  * @brief   EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         0x0003U /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         0x0004U /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         0x0005U /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         0x0006U /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PI         0x0008U /*!<PI[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PJ         0x0009U /*!<PJ[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PK         0x000AU /*!<PK[4] pin */
-
-/** 
-  * @brief   EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         0x0030U /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         0x0040U /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         0x0050U /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         0x0060U /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PI         0x0080U /*!<PI[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PJ         0x0090U /*!<PJ[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PK         0x00A0U /*!<PK[5] pin */
-
-/** 
-  * @brief   EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         0x0300U /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         0x0400U /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         0x0500U /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         0x0600U /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PI         0x0800U /*!<PI[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PJ         0x0900U /*!<PJ[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PK         0x0A00U /*!<PK[6] pin */
-
-
-/** 
-  * @brief   EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         0x3000U /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         0x4000U /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         0x5000U /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         0x6000U /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PI         0x8000U /*!<PI[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PJ         0x9000U /*!<PJ[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PK         0xA000U /*!<PK[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
-           
-/** 
-  * @brief   EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         0x0003U /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         0x0004U /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         0x0005U /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         0x0006U /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PI         0x0008U /*!<PI[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PJ         0x0009U /*!<PJ[8] pin */
-
-/** 
-  * @brief   EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         0x0030U /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         0x0040U /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         0x0050U /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         0x0060U /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PI         0x0080U /*!<PI[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PJ         0x0090U /*!<PJ[9] pin */
-
-
-/** 
-  * @brief   EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        0x0300U /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        0x0400U /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        0x0500U /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        0x0600U /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PI        0x0800U /*!<PI[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PJ        0x0900U /*!<PJ[10] pin */
-
-
-/** 
-  * @brief   EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        0x3000U /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        0x4000U /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        0x5000U /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        0x6000U /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PI        0x8000U /*!<PI[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PJ        0x9000U /*!<PJ[11] pin */
-
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
-/** 
-  * @brief   EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        0x0003U /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        0x0004U /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        0x0005U /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        0x0006U /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PI        0x0008U /*!<PI[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PJ        0x0009U /*!<PJ[12] pin */
-
-
-/** 
-  * @brief   EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        0x0030U /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        0x0040U /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        0x0050U /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        0x0060U /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PI        0x0008U /*!<PI[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PJ        0x0009U /*!<PJ[13] pin */
-
-
-/** 
-  * @brief   EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        0x0300U /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        0x0400U /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        0x0500U /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        0x0600U /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PI        0x0800U /*!<PI[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PJ        0x0900U /*!<PJ[14] pin */
-
-
-/** 
-  * @brief   EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        0x3000U /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        0x4000U /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        0x5000U /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        0x6000U /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PI        0x8000U /*!<PI[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PJ        0x9000U /*!<PJ[15] pin */
-
-/******************  Bit definition for SYSCFG_CMPCR register  ****************/  
-#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell ready flag */
-#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell power-down */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    TIM                                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
-#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
-#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
-#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
-#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
-
-#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
-
-#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
-
-#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        0x0001U            /*!<Capture/Compare Preloaded Control        */
-#define  TIM_CR2_CCUS                        0x0004U            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        0x0008U            /*!<Capture/Compare DMA Selection            */
-
-#define  TIM_CR2_MMS                         0x0070U            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
-#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
-#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
-#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        0x0007U            /*!<SMS[2:0] bits (Slave mode selection)    */
-#define  TIM_SMCR_SMS_0                      0x0001U            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      0x0002U            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      0x0004U            /*!<Bit 2 */
-
-#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
-#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
-
-#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
-
-#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
-
-#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
-#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
-#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
-#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
-#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
-#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
-#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
-#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
-#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
-#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
-#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
-#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
-#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
-#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
-#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
-#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
-#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
-#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
-#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          0x01U               /*!<Update Generation                         */
-#define  TIM_EGR_CC1G                        0x02U               /*!<Capture/Compare 1 Generation              */
-#define  TIM_EGR_CC2G                        0x04U               /*!<Capture/Compare 2 Generation              */
-#define  TIM_EGR_CC3G                        0x08U               /*!<Capture/Compare 3 Generation              */
-#define  TIM_EGR_CC4G                        0x10U               /*!<Capture/Compare 4 Generation              */
-#define  TIM_EGR_COMG                        0x20U               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          0x40U               /*!<Trigger Generation                        */
-#define  TIM_EGR_BG                          0x80U               /*!<Break Generation                          */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      0x0003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    0x0001U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    0x0002U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC1FE                     0x0004U            /*!<Output Compare 1 Fast enable                 */
-#define  TIM_CCMR1_OC1PE                     0x0008U            /*!<Output Compare 1 Preload enable              */
-
-#define  TIM_CCMR1_OC1M                      0x0070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define  TIM_CCMR1_OC1M_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    0x0040U            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC1CE                     0x0080U            /*!<Output Compare 1Clear Enable                 */
-
-#define  TIM_CCMR1_CC2S                      0x0300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    0x0100U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    0x0200U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC2FE                     0x0400U            /*!<Output Compare 2 Fast enable                 */
-#define  TIM_CCMR1_OC2PE                     0x0800U            /*!<Output Compare 2 Preload enable              */
-
-#define  TIM_CCMR1_OC2M                      0x7000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define  TIM_CCMR1_OC2M_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    0x4000U            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC2CE                     0x8000U            /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      0x0003U            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define  TIM_CCMR2_CC3S_0                    0x0001U            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    0x0002U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC3FE                     0x0004U            /*!<Output Compare 3 Fast enable           */
-#define  TIM_CCMR2_OC3PE                     0x0008U            /*!<Output Compare 3 Preload enable        */
-
-#define  TIM_CCMR2_OC3M                      0x0070U            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    0x0040U            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC3CE                     0x0080U            /*!<Output Compare 3 Clear Enable */
-
-#define  TIM_CCMR2_CC4S                      0x0300U            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    0x0100U            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    0x0200U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC4FE                     0x0400U            /*!<Output Compare 4 Fast enable    */
-#define  TIM_CCMR2_OC4PE                     0x0800U            /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR2_OC4M                      0x7000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    0x4000U            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       0x0001U            /*!<Capture/Compare 1 output enable                 */
-#define  TIM_CCER_CC1P                       0x0002U            /*!<Capture/Compare 1 output Polarity               */
-#define  TIM_CCER_CC1NE                      0x0004U            /*!<Capture/Compare 1 Complementary output enable   */
-#define  TIM_CCER_CC1NP                      0x0008U            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       0x0010U            /*!<Capture/Compare 2 output enable                 */
-#define  TIM_CCER_CC2P                       0x0020U            /*!<Capture/Compare 2 output Polarity               */
-#define  TIM_CCER_CC2NE                      0x0040U            /*!<Capture/Compare 2 Complementary output enable   */
-#define  TIM_CCER_CC2NP                      0x0080U            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       0x0100U            /*!<Capture/Compare 3 output enable                 */
-#define  TIM_CCER_CC3P                       0x0200U            /*!<Capture/Compare 3 output Polarity               */
-#define  TIM_CCER_CC3NE                      0x0400U            /*!<Capture/Compare 3 Complementary output enable   */
-#define  TIM_CCER_CC3NP                      0x0800U            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       0x1000U            /*!<Capture/Compare 4 output enable                 */
-#define  TIM_CCER_CC4P                       0x2000U            /*!<Capture/Compare 4 output Polarity               */
-#define  TIM_CCER_CC4NP                      0x8000U            /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         0xFFU               /*!<Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
-
-/*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        0x00FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      0x0001U            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      0x0002U            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      0x0004U            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      0x0008U            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      0x0010U            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      0x0020U            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      0x0040U            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      0x0080U            /*!<Bit 7 */
-
-#define  TIM_BDTR_LOCK                       0x0300U            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     0x0100U            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     0x0200U            /*!<Bit 1 */
-
-#define  TIM_BDTR_OSSI                       0x0400U            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       0x0800U            /*!<Off-State Selection for Run mode  */
-#define  TIM_BDTR_BKE                        0x1000U            /*!<Break enable                      */
-#define  TIM_BDTR_BKP                        0x2000U            /*!<Break Polarity                    */
-#define  TIM_BDTR_AOE                        0x4000U            /*!<Automatic Output enable           */
-#define  TIM_BDTR_MOE                        0x8000U            /*!<Main Output enable                */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
-
-#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
-#define TIM_OR_ITR1_RMP                      0x0C00U            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
-#define TIM_OR_ITR1_RMP_0                    0x0400U            /*!<Bit 0 */
-#define TIM_OR_ITR1_RMP_1                    0x0800U            /*!<Bit 1 */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*         Universal Synchronous Asynchronous Receiver Transmitter            */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         0x0001U            /*!<Parity Error                 */
-#define  USART_SR_FE                         0x0002U            /*!<Framing Error                */
-#define  USART_SR_NE                         0x0004U            /*!<Noise Error Flag             */
-#define  USART_SR_ORE                        0x0008U            /*!<OverRun Error                */
-#define  USART_SR_IDLE                       0x0010U            /*!<IDLE line detected           */
-#define  USART_SR_RXNE                       0x0020U            /*!<Read Data Register Not Empty */
-#define  USART_SR_TC                         0x0040U            /*!<Transmission Complete        */
-#define  USART_SR_TXE                        0x0080U            /*!<Transmit Data Register Empty */
-#define  USART_SR_LBD                        0x0100U            /*!<LIN Break Detection Flag     */
-#define  USART_SR_CTS                        0x0200U            /*!<CTS Flag                     */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         0x01FFU            /*!<Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_Fraction              0x000FU            /*!<Fraction of USARTDIV */
-#define  USART_BRR_DIV_Mantissa              0xFFF0U            /*!<Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       0x0001U            /*!<Send Break                             */
-#define  USART_CR1_RWU                       0x0002U            /*!<Receiver wakeup                        */
-#define  USART_CR1_RE                        0x0004U            /*!<Receiver Enable                        */
-#define  USART_CR1_TE                        0x0008U            /*!<Transmitter Enable                     */
-#define  USART_CR1_IDLEIE                    0x0010U            /*!<IDLE Interrupt Enable                  */
-#define  USART_CR1_RXNEIE                    0x0020U            /*!<RXNE Interrupt Enable                  */
-#define  USART_CR1_TCIE                      0x0040U            /*!<Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     0x0080U            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PEIE                      0x0100U            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PS                        0x0200U            /*!<Parity Selection                       */
-#define  USART_CR1_PCE                       0x0400U            /*!<Parity Control Enable                  */
-#define  USART_CR1_WAKE                      0x0800U            /*!<Wakeup method                          */
-#define  USART_CR1_M                         0x1000U            /*!<Word length                            */
-#define  USART_CR1_UE                        0x2000U            /*!<USART Enable                           */
-#define  USART_CR1_OVER8                     0x8000U            /*!<USART Oversampling by 8 enable         */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       0x000FU            /*!<Address of the USART node            */
-#define  USART_CR2_LBDL                      0x0020U            /*!<LIN Break Detection Length           */
-#define  USART_CR2_LBDIE                     0x0040U            /*!<LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      0x0100U            /*!<Last Bit Clock pulse                 */
-#define  USART_CR2_CPHA                      0x0200U            /*!<Clock Phase                          */
-#define  USART_CR2_CPOL                      0x0400U            /*!<Clock Polarity                       */
-#define  USART_CR2_CLKEN                     0x0800U            /*!<Clock Enable                         */
-
-#define  USART_CR2_STOP                      0x3000U            /*!<STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    0x1000U            /*!<Bit 0 */
-#define  USART_CR2_STOP_1                    0x2000U            /*!<Bit 1 */
-
-#define  USART_CR2_LINEN                     0x4000U            /*!<LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       0x0001U            /*!<Error Interrupt Enable      */
-#define  USART_CR3_IREN                      0x0002U            /*!<IrDA mode Enable            */
-#define  USART_CR3_IRLP                      0x0004U            /*!<IrDA Low-Power              */
-#define  USART_CR3_HDSEL                     0x0008U            /*!<Half-Duplex Selection       */
-#define  USART_CR3_NACK                      0x0010U            /*!<Smartcard NACK enable       */
-#define  USART_CR3_SCEN                      0x0020U            /*!<Smartcard mode enable       */
-#define  USART_CR3_DMAR                      0x0040U            /*!<DMA Enable Receiver         */
-#define  USART_CR3_DMAT                      0x0080U            /*!<DMA Enable Transmitter      */
-#define  USART_CR3_RTSE                      0x0100U            /*!<RTS Enable                  */
-#define  USART_CR3_CTSE                      0x0200U            /*!<CTS Enable                  */
-#define  USART_CR3_CTSIE                     0x0400U            /*!<CTS Interrupt Enable        */
-#define  USART_CR3_ONEBIT                    0x0800U            /*!<USART One bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      0x00FFU            /*!<PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    0x0001U            /*!<Bit 0 */
-#define  USART_GTPR_PSC_1                    0x0002U            /*!<Bit 1 */
-#define  USART_GTPR_PSC_2                    0x0004U            /*!<Bit 2 */
-#define  USART_GTPR_PSC_3                    0x0008U            /*!<Bit 3 */
-#define  USART_GTPR_PSC_4                    0x0010U            /*!<Bit 4 */
-#define  USART_GTPR_PSC_5                    0x0020U            /*!<Bit 5 */
-#define  USART_GTPR_PSC_6                    0x0040U            /*!<Bit 6 */
-#define  USART_GTPR_PSC_7                    0x0080U            /*!<Bit 7 */
-
-#define  USART_GTPR_GT                       0xFF00U            /*!<Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Window WATCHDOG                                 */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           0x7FU               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T_0                         0x01U               /*!<Bit 0 */
-#define  WWDG_CR_T_1                         0x02U               /*!<Bit 1 */
-#define  WWDG_CR_T_2                         0x04U               /*!<Bit 2 */
-#define  WWDG_CR_T_3                         0x08U               /*!<Bit 3 */
-#define  WWDG_CR_T_4                         0x10U               /*!<Bit 4 */
-#define  WWDG_CR_T_5                         0x20U               /*!<Bit 5 */
-#define  WWDG_CR_T_6                         0x40U               /*!<Bit 6 */
-/* Legacy defines */
-#define  WWDG_CR_T0                          WWDG_CR_T_0
-#define  WWDG_CR_T1                          WWDG_CR_T_1
-#define  WWDG_CR_T2                          WWDG_CR_T_2
-#define  WWDG_CR_T3                          WWDG_CR_T_3
-#define  WWDG_CR_T4                          WWDG_CR_T_4
-#define  WWDG_CR_T5                          WWDG_CR_T_5
-#define  WWDG_CR_T6                          WWDG_CR_T_6
-
-#define  WWDG_CR_WDGA                        0x80U               /*!<Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          0x007FU            /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W_0                        0x0001U            /*!<Bit 0 */
-#define  WWDG_CFR_W_1                        0x0002U            /*!<Bit 1 */
-#define  WWDG_CFR_W_2                        0x0004U            /*!<Bit 2 */
-#define  WWDG_CFR_W_3                        0x0008U            /*!<Bit 3 */
-#define  WWDG_CFR_W_4                        0x0010U            /*!<Bit 4 */
-#define  WWDG_CFR_W_5                        0x0020U            /*!<Bit 5 */
-#define  WWDG_CFR_W_6                        0x0040U            /*!<Bit 6 */
-/* Legacy defines */
-#define  WWDG_CFR_W0                         WWDG_CFR_W_0
-#define  WWDG_CFR_W1                         WWDG_CFR_W_1
-#define  WWDG_CFR_W2                         WWDG_CFR_W_2
-#define  WWDG_CFR_W3                         WWDG_CFR_W_3
-#define  WWDG_CFR_W4                         WWDG_CFR_W_4
-#define  WWDG_CFR_W5                         WWDG_CFR_W_5
-#define  WWDG_CFR_W6                         WWDG_CFR_W_6
-
-#define  WWDG_CFR_WDGTB                      0x0180U            /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB_0                    0x0080U            /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB_1                    0x0100U            /*!<Bit 1 */
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
-
-#define  WWDG_CFR_EWI                        0x0200U            /*!<Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        0x01U               /*!<Early Wakeup Interrupt Flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                DBG                                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
-#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
-
-/********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
-#define  DBGMCU_CR_DBG_STOP                  0x00000002U
-#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
-#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
-
-#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
-#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U/*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U/*!<Bit 1 */
-
-/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            0x00000001U
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            0x00000002U
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            0x00000004U
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            0x00000020U
-#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           0x00000040U
-#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           0x00000080U
-#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           0x00000100U
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
-#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
-/* Old IWDGSTOP bit definition, maintained for legacy purpose */
-#define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
-
-/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        0x00000001U
-#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        0x00000002U
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        0x00010000U
-#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       0x00020000U
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       0x00040000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                Ethernet MAC Registers bits definitions                     */
-/*                                                                            */
-/******************************************************************************/
-/* Bit definition for Ethernet MAC Control Register register */
-#define ETH_MACCR_WD      0x00800000U  /* Watchdog disable */
-#define ETH_MACCR_JD      0x00400000U  /* Jabber disable */
-#define ETH_MACCR_IFG     0x000E0000U  /* Inter-frame gap */
-#define ETH_MACCR_IFG_96Bit     0x00000000U  /* Minimum IFG between frames during transmission is 96Bit */
-  #define ETH_MACCR_IFG_88Bit     0x00020000U  /* Minimum IFG between frames during transmission is 88Bit */
-  #define ETH_MACCR_IFG_80Bit     0x00040000U  /* Minimum IFG between frames during transmission is 80Bit */
-  #define ETH_MACCR_IFG_72Bit     0x00060000U  /* Minimum IFG between frames during transmission is 72Bit */
-  #define ETH_MACCR_IFG_64Bit     0x00080000U  /* Minimum IFG between frames during transmission is 64Bit */        
-  #define ETH_MACCR_IFG_56Bit     0x000A0000U  /* Minimum IFG between frames during transmission is 56Bit */
-  #define ETH_MACCR_IFG_48Bit     0x000C0000U  /* Minimum IFG between frames during transmission is 48Bit */
-  #define ETH_MACCR_IFG_40Bit     0x000E0000U  /* Minimum IFG between frames during transmission is 40Bit */              
-#define ETH_MACCR_CSD     0x00010000U  /* Carrier sense disable (during transmission) */
-#define ETH_MACCR_FES     0x00004000U  /* Fast ethernet speed */
-#define ETH_MACCR_ROD     0x00002000U  /* Receive own disable */
-#define ETH_MACCR_LM      0x00001000U  /* loopback mode */
-#define ETH_MACCR_DM      0x00000800U  /* Duplex mode */
-#define ETH_MACCR_IPCO    0x00000400U  /* IP Checksum offload */
-#define ETH_MACCR_RD      0x00000200U  /* Retry disable */
-#define ETH_MACCR_APCS    0x00000080U  /* Automatic Pad/CRC stripping */
-#define ETH_MACCR_BL      0x00000060U  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
-                                                       a transmission attempt during retries after a collision: 0 =< r <2^k */
-  #define ETH_MACCR_BL_10    0x00000000U  /* k = min (n, 10) */
-  #define ETH_MACCR_BL_8     0x00000020U  /* k = min (n, 8) */
-  #define ETH_MACCR_BL_4     0x00000040U  /* k = min (n, 4) */
-  #define ETH_MACCR_BL_1     0x00000060U  /* k = min (n, 1) */ 
-#define ETH_MACCR_DC      0x00000010U  /* Defferal check */
-#define ETH_MACCR_TE      0x00000008U  /* Transmitter enable */
-#define ETH_MACCR_RE      0x00000004U  /* Receiver enable */
-
-/* Bit definition for Ethernet MAC Frame Filter Register */
-#define ETH_MACFFR_RA     0x80000000U  /* Receive all */ 
-#define ETH_MACFFR_HPF    0x00000400U  /* Hash or perfect filter */ 
-#define ETH_MACFFR_SAF    0x00000200U  /* Source address filter enable */ 
-#define ETH_MACFFR_SAIF   0x00000100U  /* SA inverse filtering */ 
-#define ETH_MACFFR_PCF    0x000000C0U  /* Pass control frames: 3 cases */
-  #define ETH_MACFFR_PCF_BlockAll                0x00000040U  /* MAC filters all control frames from reaching the application */
-  #define ETH_MACFFR_PCF_ForwardAll              0x00000080U  /* MAC forwards all control frames to application even if they fail the Address Filter */
-  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U  /* MAC forwards control frames that pass the Address Filter. */ 
-#define ETH_MACFFR_BFD    0x00000020U  /* Broadcast frame disable */ 
-#define ETH_MACFFR_PAM    0x00000010U  /* Pass all mutlicast */ 
-#define ETH_MACFFR_DAIF   0x00000008U  /* DA Inverse filtering */ 
-#define ETH_MACFFR_HM     0x00000004U  /* Hash multicast */ 
-#define ETH_MACFFR_HU     0x00000002U  /* Hash unicast */
-#define ETH_MACFFR_PM     0x00000001U  /* Promiscuous mode */
-
-/* Bit definition for Ethernet MAC Hash Table High Register */
-#define ETH_MACHTHR_HTH   0xFFFFFFFFU  /* Hash table high */
-
-/* Bit definition for Ethernet MAC Hash Table Low Register */
-#define ETH_MACHTLR_HTL   0xFFFFFFFFU  /* Hash table low */
-
-/* Bit definition for Ethernet MAC MII Address Register */
-#define ETH_MACMIIAR_PA   0x0000F800U  /* Physical layer address */ 
-#define ETH_MACMIIAR_MR   0x000007C0U  /* MII register in the selected PHY */ 
-#define ETH_MACMIIAR_CR   0x0000001CU  /* CR clock range: 6 cases */ 
-  #define ETH_MACMIIAR_CR_Div42   0x00000000U  /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
-  #define ETH_MACMIIAR_CR_Div62   0x00000004U  /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
-  #define ETH_MACMIIAR_CR_Div16   0x00000008U  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
-  #define ETH_MACMIIAR_CR_Div26   0x0000000CU  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
-  #define ETH_MACMIIAR_CR_Div102  0x00000010U  /* HCLK:150-168 MHz; MDC clock= HCLK/102 */  
-#define ETH_MACMIIAR_MW   0x00000002U  /* MII write */ 
-#define ETH_MACMIIAR_MB   0x00000001U  /* MII busy */ 
-  
-/* Bit definition for Ethernet MAC MII Data Register */
-#define ETH_MACMIIDR_MD   0x0000FFFFU  /* MII data: read/write data from/to PHY */
-
-/* Bit definition for Ethernet MAC Flow Control Register */
-#define ETH_MACFCR_PT     0xFFFF0000U  /* Pause time */
-#define ETH_MACFCR_ZQPD   0x00000080U  /* Zero-quanta pause disable */
-#define ETH_MACFCR_PLT    0x00000030U  /* Pause low threshold: 4 cases */
-  #define ETH_MACFCR_PLT_Minus4   0x00000000U  /* Pause time minus 4 slot times */
-  #define ETH_MACFCR_PLT_Minus28  0x00000010U  /* Pause time minus 28 slot times */
-  #define ETH_MACFCR_PLT_Minus144 0x00000020U  /* Pause time minus 144 slot times */
-  #define ETH_MACFCR_PLT_Minus256 0x00000030U  /* Pause time minus 256 slot times */      
-#define ETH_MACFCR_UPFD   0x00000008U  /* Unicast pause frame detect */
-#define ETH_MACFCR_RFCE   0x00000004U  /* Receive flow control enable */
-#define ETH_MACFCR_TFCE   0x00000002U  /* Transmit flow control enable */
-#define ETH_MACFCR_FCBBPA 0x00000001U  /* Flow control busy/backpressure activate */
-
-/* Bit definition for Ethernet MAC VLAN Tag Register */
-#define ETH_MACVLANTR_VLANTC 0x00010000U  /* 12-bit VLAN tag comparison */
-#define ETH_MACVLANTR_VLANTI 0x0000FFFFU  /* VLAN tag identifier (for receive frames) */
-
-/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ 
-#define ETH_MACRWUFFR_D   0xFFFFFFFFU  /* Wake-up frame filter register data */
-/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
-   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
-/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
-   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
-   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
-   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
-   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - 
-                              RSVD - Filter1 Command - RSVD - Filter0 Command
-   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
-   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
-   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
-
-/* Bit definition for Ethernet MAC PMT Control and Status Register */ 
-#define ETH_MACPMTCSR_WFFRPR 0x80000000U  /* Wake-Up Frame Filter Register Pointer Reset */
-#define ETH_MACPMTCSR_GU     0x00000200U  /* Global Unicast */
-#define ETH_MACPMTCSR_WFR    0x00000040U  /* Wake-Up Frame Received */
-#define ETH_MACPMTCSR_MPR    0x00000020U  /* Magic Packet Received */
-#define ETH_MACPMTCSR_WFE    0x00000004U  /* Wake-Up Frame Enable */
-#define ETH_MACPMTCSR_MPE    0x00000002U  /* Magic Packet Enable */
-#define ETH_MACPMTCSR_PD     0x00000001U  /* Power Down */
-
-/* Bit definition for Ethernet MAC Status Register */
-#define ETH_MACSR_TSTS      0x00000200U  /* Time stamp trigger status */
-#define ETH_MACSR_MMCTS     0x00000040U  /* MMC transmit status */
-#define ETH_MACSR_MMMCRS    0x00000020U  /* MMC receive status */
-#define ETH_MACSR_MMCS      0x00000010U  /* MMC status */
-#define ETH_MACSR_PMTS      0x00000008U  /* PMT status */
-
-/* Bit definition for Ethernet MAC Interrupt Mask Register */
-#define ETH_MACIMR_TSTIM     0x00000200U  /* Time stamp trigger interrupt mask */
-#define ETH_MACIMR_PMTIM     0x00000008U  /* PMT interrupt mask */
-
-/* Bit definition for Ethernet MAC Address0 High Register */
-#define ETH_MACA0HR_MACA0H   0x0000FFFFU  /* MAC address0 high */
-
-/* Bit definition for Ethernet MAC Address0 Low Register */
-#define ETH_MACA0LR_MACA0L   0xFFFFFFFFU  /* MAC address0 low */
-
-/* Bit definition for Ethernet MAC Address1 High Register */
-#define ETH_MACA1HR_AE       0x80000000U  /* Address enable */
-#define ETH_MACA1HR_SA       0x40000000U  /* Source address */
-#define ETH_MACA1HR_MBC      0x3F000000U  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
-  #define ETH_MACA1HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA1HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA1HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA1HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA1HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA1HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [7:0] */ 
-#define ETH_MACA1HR_MACA1H   0x0000FFFFU  /* MAC address1 high */
-
-/* Bit definition for Ethernet MAC Address1 Low Register */
-#define ETH_MACA1LR_MACA1L   0xFFFFFFFFU  /* MAC address1 low */
-
-/* Bit definition for Ethernet MAC Address2 High Register */
-#define ETH_MACA2HR_AE       0x80000000U  /* Address enable */
-#define ETH_MACA2HR_SA       0x40000000U  /* Source address */
-#define ETH_MACA2HR_MBC      0x3F000000U  /* Mask byte control */
-  #define ETH_MACA2HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA2HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA2HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA2HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA2HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA2HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA2HR_MACA2H   0x0000FFFFU  /* MAC address1 high */
-
-/* Bit definition for Ethernet MAC Address2 Low Register */
-#define ETH_MACA2LR_MACA2L   0xFFFFFFFFU  /* MAC address2 low */
-
-/* Bit definition for Ethernet MAC Address3 High Register */
-#define ETH_MACA3HR_AE       0x80000000U  /* Address enable */
-#define ETH_MACA3HR_SA       0x40000000U  /* Source address */
-#define ETH_MACA3HR_MBC      0x3F000000U  /* Mask byte control */
-  #define ETH_MACA3HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA3HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA3HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA3HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA3HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA3HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA3HR_MACA3H   0x0000FFFFU  /* MAC address3 high */
-
-/* Bit definition for Ethernet MAC Address3 Low Register */
-#define ETH_MACA3LR_MACA3L   0xFFFFFFFFU  /* MAC address3 low */
-
-/******************************************************************************/
-/*                Ethernet MMC Registers bits definition                      */
-/******************************************************************************/
-
-/* Bit definition for Ethernet MMC Contol Register */
-#define ETH_MMCCR_MCFHP      0x00000020U  /* MMC counter Full-Half preset */
-#define ETH_MMCCR_MCP        0x00000010U  /* MMC counter preset */
-#define ETH_MMCCR_MCF        0x00000008U  /* MMC Counter Freeze */
-#define ETH_MMCCR_ROR        0x00000004U  /* Reset on Read */
-#define ETH_MMCCR_CSR        0x00000002U  /* Counter Stop Rollover */
-#define ETH_MMCCR_CR         0x00000001U  /* Counters Reset */
-
-/* Bit definition for Ethernet MMC Receive Interrupt Register */
-#define ETH_MMCRIR_RGUFS     0x00020000U  /* Set when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIR_RFAES     0x00000040U  /* Set when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIR_RFCES     0x00000020U  /* Set when Rx crc error counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmit Interrupt Register */
-#define ETH_MMCTIR_TGFS      0x00200000U  /* Set when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFMSCS   0x00008000U  /* Set when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFSCS    0x00004000U  /* Set when Tx good single col counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
-#define ETH_MMCRIMR_RGUFM    0x00020000U  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFAEM    0x00000040U  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFCEM    0x00000020U  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
-#define ETH_MMCTIMR_TGFM     0x00200000U  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFMSCM  0x00008000U  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFSCM   0x00004000U  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
-#define ETH_MMCTGFSCCR_TGFSCC     0xFFFFFFFFU  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
-#define ETH_MMCTGFMSCCR_TGFMSCC   0xFFFFFFFFU  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
-#define ETH_MMCTGFCR_TGFC    0xFFFFFFFFU  /* Number of good frames transmitted. */
-
-/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
-#define ETH_MMCRFCECR_RFCEC  0xFFFFFFFFU  /* Number of frames received with CRC error. */
-
-/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
-#define ETH_MMCRFAECR_RFAEC  0xFFFFFFFFU  /* Number of frames received with alignment (dribble) error */
-
-/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
-#define ETH_MMCRGUFCR_RGUFC  0xFFFFFFFFU  /* Number of good unicast frames received. */
-
-/******************************************************************************/
-/*               Ethernet PTP Registers bits definition                       */
-/******************************************************************************/
-
-/* Bit definition for Ethernet PTP Time Stamp Contol Register */
-#define ETH_PTPTSCR_TSCNT       0x00030000U  /* Time stamp clock node type */
-#define ETH_PTPTSSR_TSSMRME     0x00008000U  /* Time stamp snapshot for message relevant to master enable */
-#define ETH_PTPTSSR_TSSEME      0x00004000U  /* Time stamp snapshot for event message enable */
-#define ETH_PTPTSSR_TSSIPV4FE   0x00002000U  /* Time stamp snapshot for IPv4 frames enable */
-#define ETH_PTPTSSR_TSSIPV6FE   0x00001000U  /* Time stamp snapshot for IPv6 frames enable */
-#define ETH_PTPTSSR_TSSPTPOEFE  0x00000800U  /* Time stamp snapshot for PTP over ethernet frames enable */
-#define ETH_PTPTSSR_TSPTPPSV2E  0x00000400U  /* Time stamp PTP packet snooping for version2 format enable */
-#define ETH_PTPTSSR_TSSSR       0x00000200U  /* Time stamp Sub-seconds rollover */
-#define ETH_PTPTSSR_TSSARFE     0x00000100U  /* Time stamp snapshot for all received frames enable */
-
-#define ETH_PTPTSCR_TSARU    0x00000020U  /* Addend register update */
-#define ETH_PTPTSCR_TSITE    0x00000010U  /* Time stamp interrupt trigger enable */
-#define ETH_PTPTSCR_TSSTU    0x00000008U  /* Time stamp update */
-#define ETH_PTPTSCR_TSSTI    0x00000004U  /* Time stamp initialize */
-#define ETH_PTPTSCR_TSFCU    0x00000002U  /* Time stamp fine or coarse update */
-#define ETH_PTPTSCR_TSE      0x00000001U  /* Time stamp enable */
-
-/* Bit definition for Ethernet PTP Sub-Second Increment Register */
-#define ETH_PTPSSIR_STSSI    0x000000FFU  /* System time Sub-second increment value */
-
-/* Bit definition for Ethernet PTP Time Stamp High Register */
-#define ETH_PTPTSHR_STS      0xFFFFFFFFU  /* System Time second */
-
-/* Bit definition for Ethernet PTP Time Stamp Low Register */
-#define ETH_PTPTSLR_STPNS    0x80000000U  /* System Time Positive or negative time */
-#define ETH_PTPTSLR_STSS     0x7FFFFFFFU  /* System Time sub-seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp High Update Register */
-#define ETH_PTPTSHUR_TSUS    0xFFFFFFFFU  /* Time stamp update seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
-#define ETH_PTPTSLUR_TSUPNS  0x80000000U  /* Time stamp update Positive or negative time */
-#define ETH_PTPTSLUR_TSUSS   0x7FFFFFFFU  /* Time stamp update sub-seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp Addend Register */
-#define ETH_PTPTSAR_TSA      0xFFFFFFFFU  /* Time stamp addend */
-
-/* Bit definition for Ethernet PTP Target Time High Register */
-#define ETH_PTPTTHR_TTSH     0xFFFFFFFFU  /* Target time stamp high */
-
-/* Bit definition for Ethernet PTP Target Time Low Register */
-#define ETH_PTPTTLR_TTSL     0xFFFFFFFFU  /* Target time stamp low */
-
-/* Bit definition for Ethernet PTP Time Stamp Status Register */
-#define ETH_PTPTSSR_TSTTR    0x00000020U  /* Time stamp target time reached */
-#define ETH_PTPTSSR_TSSO     0x00000010U  /* Time stamp seconds overflow */
-
-/******************************************************************************/
-/*                 Ethernet DMA Registers bits definition                     */
-/******************************************************************************/
-
-/* Bit definition for Ethernet DMA Bus Mode Register */
-#define ETH_DMABMR_AAB       0x02000000U  /* Address-Aligned beats */
-#define ETH_DMABMR_FPM        0x01000000U  /* 4xPBL mode */
-#define ETH_DMABMR_USP       0x00800000U  /* Use separate PBL */
-#define ETH_DMABMR_RDP       0x007E0000U  /* RxDMA PBL */
-  #define ETH_DMABMR_RDP_1Beat    0x00020000U  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
-  #define ETH_DMABMR_RDP_2Beat    0x00040000U  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
-  #define ETH_DMABMR_RDP_4Beat    0x00080000U  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-  #define ETH_DMABMR_RDP_8Beat    0x00100000U  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-  #define ETH_DMABMR_RDP_16Beat   0x00200000U  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-  #define ETH_DMABMR_RDP_32Beat   0x00400000U  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */                
-  #define ETH_DMABMR_RDP_4xPBL_4Beat   0x01020000U  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-  #define ETH_DMABMR_RDP_4xPBL_8Beat   0x01040000U  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-  #define ETH_DMABMR_RDP_4xPBL_16Beat  0x01080000U  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-  #define ETH_DMABMR_RDP_4xPBL_32Beat  0x01100000U  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
-  #define ETH_DMABMR_RDP_4xPBL_64Beat  0x01200000U  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
-  #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */  
-#define ETH_DMABMR_FB        0x00010000U  /* Fixed Burst */
-#define ETH_DMABMR_RTPR      0x0000C000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_1_1     0x00000000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_2_1     0x00004000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_3_1     0x00008000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_4_1     0x0000C000U  /* Rx Tx priority ratio */  
-#define ETH_DMABMR_PBL    0x00003F00U  /* Programmable burst length */
-  #define ETH_DMABMR_PBL_1Beat    0x00000100U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
-  #define ETH_DMABMR_PBL_2Beat    0x00000200U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
-  #define ETH_DMABMR_PBL_4Beat    0x00000400U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-  #define ETH_DMABMR_PBL_8Beat    0x00000800U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-  #define ETH_DMABMR_PBL_16Beat   0x00001000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-  #define ETH_DMABMR_PBL_32Beat   0x00002000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
-  #define ETH_DMABMR_PBL_4xPBL_4Beat   0x01000100U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-  #define ETH_DMABMR_PBL_4xPBL_8Beat   0x01000200U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-  #define ETH_DMABMR_PBL_4xPBL_16Beat  0x01000400U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-  #define ETH_DMABMR_PBL_4xPBL_32Beat  0x01000800U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
-  #define ETH_DMABMR_PBL_4xPBL_64Beat  0x01001000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
-  #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
-#define ETH_DMABMR_EDE       0x00000080U  /* Enhanced Descriptor Enable */
-#define ETH_DMABMR_DSL       0x0000007CU  /* Descriptor Skip Length */
-#define ETH_DMABMR_DA        0x00000002U  /* DMA arbitration scheme */
-#define ETH_DMABMR_SR        0x00000001U  /* Software reset */
-
-/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
-#define ETH_DMATPDR_TPD      0xFFFFFFFFU  /* Transmit poll demand */
-
-/* Bit definition for Ethernet DMA Receive Poll Demand Register */
-#define ETH_DMARPDR_RPD      0xFFFFFFFFU  /* Receive poll demand  */
-
-/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
-#define ETH_DMARDLAR_SRL     0xFFFFFFFFU  /* Start of receive list */
-
-/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
-#define ETH_DMATDLAR_STL     0xFFFFFFFFU  /* Start of transmit list */
-
-/* Bit definition for Ethernet DMA Status Register */
-#define ETH_DMASR_TSTS       0x20000000U  /* Time-stamp trigger status */
-#define ETH_DMASR_PMTS       0x10000000U  /* PMT status */
-#define ETH_DMASR_MMCS       0x08000000U  /* MMC status */
-#define ETH_DMASR_EBS        0x03800000U  /* Error bits status */
-  /* combination with EBS[2:0] for GetFlagStatus function */
-  #define ETH_DMASR_EBS_DescAccess      0x02000000U  /* Error bits 0-data buffer, 1-desc. access */
-  #define ETH_DMASR_EBS_ReadTransf      0x01000000U  /* Error bits 0-write trnsf, 1-read transfr */
-  #define ETH_DMASR_EBS_DataTransfTx    0x00800000U  /* Error bits 0-Rx DMA, 1-Tx DMA */
-#define ETH_DMASR_TPS         0x00700000U  /* Transmit process state */
-  #define ETH_DMASR_TPS_Stopped         0x00000000U  /* Stopped - Reset or Stop Tx Command issued  */
-  #define ETH_DMASR_TPS_Fetching        0x00100000U  /* Running - fetching the Tx descriptor */
-  #define ETH_DMASR_TPS_Waiting         0x00200000U  /* Running - waiting for status */
-  #define ETH_DMASR_TPS_Reading         0x00300000U  /* Running - reading the data from host memory */
-  #define ETH_DMASR_TPS_Suspended       0x00600000U  /* Suspended - Tx Descriptor unavailabe */
-  #define ETH_DMASR_TPS_Closing         0x00700000U  /* Running - closing Rx descriptor */
-#define ETH_DMASR_RPS         0x000E0000U  /* Receive process state */
-  #define ETH_DMASR_RPS_Stopped         0x00000000U  /* Stopped - Reset or Stop Rx Command issued */
-  #define ETH_DMASR_RPS_Fetching        0x00020000U  /* Running - fetching the Rx descriptor */
-  #define ETH_DMASR_RPS_Waiting         0x00060000U  /* Running - waiting for packet */
-  #define ETH_DMASR_RPS_Suspended       0x00080000U  /* Suspended - Rx Descriptor unavailable */
-  #define ETH_DMASR_RPS_Closing         0x000A0000U  /* Running - closing descriptor */
-  #define ETH_DMASR_RPS_Queuing         0x000E0000U  /* Running - queuing the recieve frame into host memory */
-#define ETH_DMASR_NIS        0x00010000U  /* Normal interrupt summary */
-#define ETH_DMASR_AIS        0x00008000U  /* Abnormal interrupt summary */
-#define ETH_DMASR_ERS        0x00004000U  /* Early receive status */
-#define ETH_DMASR_FBES       0x00002000U  /* Fatal bus error status */
-#define ETH_DMASR_ETS        0x00000400U  /* Early transmit status */
-#define ETH_DMASR_RWTS       0x00000200U  /* Receive watchdog timeout status */
-#define ETH_DMASR_RPSS       0x00000100U  /* Receive process stopped status */
-#define ETH_DMASR_RBUS       0x00000080U  /* Receive buffer unavailable status */
-#define ETH_DMASR_RS         0x00000040U  /* Receive status */
-#define ETH_DMASR_TUS        0x00000020U  /* Transmit underflow status */
-#define ETH_DMASR_ROS        0x00000010U  /* Receive overflow status */
-#define ETH_DMASR_TJTS       0x00000008U  /* Transmit jabber timeout status */
-#define ETH_DMASR_TBUS       0x00000004U  /* Transmit buffer unavailable status */
-#define ETH_DMASR_TPSS       0x00000002U  /* Transmit process stopped status */
-#define ETH_DMASR_TS         0x00000001U  /* Transmit status */
-
-/* Bit definition for Ethernet DMA Operation Mode Register */
-#define ETH_DMAOMR_DTCEFD    0x04000000U  /* Disable Dropping of TCP/IP checksum error frames */
-#define ETH_DMAOMR_RSF       0x02000000U  /* Receive store and forward */
-#define ETH_DMAOMR_DFRF      0x01000000U  /* Disable flushing of received frames */
-#define ETH_DMAOMR_TSF       0x00200000U  /* Transmit store and forward */
-#define ETH_DMAOMR_FTF       0x00100000U  /* Flush transmit FIFO */
-#define ETH_DMAOMR_TTC       0x0001C000U  /* Transmit threshold control */
-  #define ETH_DMAOMR_TTC_64Bytes       0x00000000U  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
-  #define ETH_DMAOMR_TTC_128Bytes      0x00004000U  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
-  #define ETH_DMAOMR_TTC_192Bytes      0x00008000U  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
-  #define ETH_DMAOMR_TTC_256Bytes      0x0000C000U  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
-  #define ETH_DMAOMR_TTC_40Bytes       0x00010000U  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
-  #define ETH_DMAOMR_TTC_32Bytes       0x00014000U  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
-  #define ETH_DMAOMR_TTC_24Bytes       0x00018000U  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
-  #define ETH_DMAOMR_TTC_16Bytes       0x0001C000U  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
-#define ETH_DMAOMR_ST        0x00002000U  /* Start/stop transmission command */
-#define ETH_DMAOMR_FEF       0x00000080U  /* Forward error frames */
-#define ETH_DMAOMR_FUGF      0x00000040U  /* Forward undersized good frames */
-#define ETH_DMAOMR_RTC       0x00000018U  /* receive threshold control */
-  #define ETH_DMAOMR_RTC_64Bytes       0x00000000U  /* threshold level of the MTL Receive FIFO is 64 Bytes */
-  #define ETH_DMAOMR_RTC_32Bytes       0x00000008U  /* threshold level of the MTL Receive FIFO is 32 Bytes */
-  #define ETH_DMAOMR_RTC_96Bytes       0x00000010U  /* threshold level of the MTL Receive FIFO is 96 Bytes */
-  #define ETH_DMAOMR_RTC_128Bytes      0x00000018U  /* threshold level of the MTL Receive FIFO is 128 Bytes */
-#define ETH_DMAOMR_OSF       0x00000004U  /* operate on second frame */
-#define ETH_DMAOMR_SR        0x00000002U  /* Start/stop receive */
-
-/* Bit definition for Ethernet DMA Interrupt Enable Register */
-#define ETH_DMAIER_NISE      0x00010000U  /* Normal interrupt summary enable */
-#define ETH_DMAIER_AISE      0x00008000U  /* Abnormal interrupt summary enable */
-#define ETH_DMAIER_ERIE      0x00004000U  /* Early receive interrupt enable */
-#define ETH_DMAIER_FBEIE     0x00002000U  /* Fatal bus error interrupt enable */
-#define ETH_DMAIER_ETIE      0x00000400U  /* Early transmit interrupt enable */
-#define ETH_DMAIER_RWTIE     0x00000200U  /* Receive watchdog timeout interrupt enable */
-#define ETH_DMAIER_RPSIE     0x00000100U  /* Receive process stopped interrupt enable */
-#define ETH_DMAIER_RBUIE     0x00000080U  /* Receive buffer unavailable interrupt enable */
-#define ETH_DMAIER_RIE       0x00000040U  /* Receive interrupt enable */
-#define ETH_DMAIER_TUIE      0x00000020U  /* Transmit Underflow interrupt enable */
-#define ETH_DMAIER_ROIE      0x00000010U  /* Receive Overflow interrupt enable */
-#define ETH_DMAIER_TJTIE     0x00000008U  /* Transmit jabber timeout interrupt enable */
-#define ETH_DMAIER_TBUIE     0x00000004U  /* Transmit buffer unavailable interrupt enable */
-#define ETH_DMAIER_TPSIE     0x00000002U  /* Transmit process stopped interrupt enable */
-#define ETH_DMAIER_TIE       0x00000001U  /* Transmit interrupt enable */
-
-/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
-#define ETH_DMAMFBOCR_OFOC   0x10000000U  /* Overflow bit for FIFO overflow counter */
-#define ETH_DMAMFBOCR_MFA    0x0FFE0000U  /* Number of frames missed by the application */
-#define ETH_DMAMFBOCR_OMFC   0x00010000U  /* Overflow bit for missed frame counter */
-#define ETH_DMAMFBOCR_MFC    0x0000FFFFU  /* Number of frames missed by the controller */
-
-/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
-#define ETH_DMACHTDR_HTDAP   0xFFFFFFFFU  /* Host transmit descriptor address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
-#define ETH_DMACHRDR_HRDAP   0xFFFFFFFFU  /* Host receive descriptor address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
-#define ETH_DMACHTBAR_HTBAP  0xFFFFFFFFU  /* Host transmit buffer address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
-#define ETH_DMACHRBAR_HRBAP  0xFFFFFFFFU  /* Host receive buffer address pointer */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                       USB_OTG			                        */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/
-#define USB_OTG_GOTGCTL_SRQSCS                  0x00000001U            /*!< Session request success  */
-#define USB_OTG_GOTGCTL_SRQ                     0x00000002U            /*!< Session request          */
-#define USB_OTG_GOTGCTL_HNGSCS                  0x00000100U            /*!< Host negotiation success */
-#define USB_OTG_GOTGCTL_HNPRQ                   0x00000200U            /*!< HNP request              */
-#define USB_OTG_GOTGCTL_HSHNPEN                 0x00000400U            /*!< Host set HNP enable      */
-#define USB_OTG_GOTGCTL_DHNPEN                  0x00000800U            /*!< Device HNP enabled       */
-#define USB_OTG_GOTGCTL_CIDSTS                  0x00010000U            /*!< Connector ID status      */
-#define USB_OTG_GOTGCTL_DBCT                    0x00020000U            /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD                   0x00040000U            /*!< A-session valid          */
-#define USB_OTG_GOTGCTL_BSVLD                   0x00080000U            /*!< B-session valid          */
-
-/********************  Bit definition forUSB_OTG_HCFG register  ********************/
-
-#define USB_OTG_HCFG_FSLSPCS                 0x00000003U            /*!< FS/LS PHY clock select  */
-#define USB_OTG_HCFG_FSLSPCS_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCFG_FSLSPCS_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCFG_FSLSS                   0x00000004U            /*!< FS- and LS-only support */
-
-/********************  Bit definition forUSB_OTG_DCFG register  ********************/
-
-#define USB_OTG_DCFG_DSPD                    0x00000003U            /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                  0x00000001U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DSPD_1                  0x00000002U            /*!<Bit 1 */
-#define USB_OTG_DCFG_NZLSOHSK                0x00000004U            /*!< Nonzero-length status OUT handshake */
-
-#define USB_OTG_DCFG_DAD                     0x000007F0U            /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                   0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DAD_1                   0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCFG_DAD_2                   0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCFG_DAD_3                   0x00000080U            /*!<Bit 3 */
-#define USB_OTG_DCFG_DAD_4                   0x00000100U            /*!<Bit 4 */
-#define USB_OTG_DCFG_DAD_5                   0x00000200U            /*!<Bit 5 */
-#define USB_OTG_DCFG_DAD_6                   0x00000400U            /*!<Bit 6 */
-
-#define USB_OTG_DCFG_PFIVL                   0x00001800U            /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PFIVL_1                 0x00001000U            /*!<Bit 1 */
-
-#define USB_OTG_DCFG_PERSCHIVL               0x03000000U            /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0             0x01000000U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PERSCHIVL_1             0x02000000U            /*!<Bit 1 */
-
-/********************  Bit definition forUSB_OTG_PCGCR register  ********************/
-#define USB_OTG_PCGCR_STPPCLK                 0x00000001U            /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK                0x00000002U            /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP                 0x00000010U            /*!< PHY suspended */
-
-/********************  Bit definition forUSB_OTG_GOTGINT register  ********************/
-#define USB_OTG_GOTGINT_SEDET                   0x00000004U            /*!< Session end detected                   */
-#define USB_OTG_GOTGINT_SRSSCHG                 0x00000100U            /*!< Session request success status change  */
-#define USB_OTG_GOTGINT_HNSSCHG                 0x00000200U            /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET                  0x00020000U            /*!< Host negotiation detected              */
-#define USB_OTG_GOTGINT_ADTOCHG                 0x00040000U            /*!< A-device timeout change                */
-#define USB_OTG_GOTGINT_DBCDNE                  0x00080000U            /*!< Debounce done                          */
-
-/********************  Bit definition forUSB_OTG_DCTL register  ********************/
-#define USB_OTG_DCTL_RWUSIG                  0x00000001U            /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS                    0x00000002U            /*!< Soft disconnect         */
-#define USB_OTG_DCTL_GINSTS                  0x00000004U            /*!< Global IN NAK status    */
-#define USB_OTG_DCTL_GONSTS                  0x00000008U            /*!< Global OUT NAK status   */
-
-#define USB_OTG_DCTL_TCTL                    0x00000070U            /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                  0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCTL_TCTL_1                  0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCTL_TCTL_2                  0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCTL_SGINAK                  0x00000080U            /*!< Set global IN NAK         */
-#define USB_OTG_DCTL_CGINAK                  0x00000100U            /*!< Clear global IN NAK       */
-#define USB_OTG_DCTL_SGONAK                  0x00000200U            /*!< Set global OUT NAK        */
-#define USB_OTG_DCTL_CGONAK                  0x00000400U            /*!< Clear global OUT NAK      */
-#define USB_OTG_DCTL_POPRGDNE                0x00000800U            /*!< Power-on programming done */
-
-/********************  Bit definition forUSB_OTG_HFIR register  ********************/
-#define USB_OTG_HFIR_FRIVL                   0x0000FFFFU            /*!< Frame interval */
-
-/********************  Bit definition forUSB_OTG_HFNUM register  ********************/
-#define USB_OTG_HFNUM_FRNUM                   0x0000FFFFU            /*!< Frame number         */
-#define USB_OTG_HFNUM_FTREM                   0xFFFF0000U            /*!< Frame time remaining */
-
-/********************  Bit definition forUSB_OTG_DSTS register  ********************/
-#define USB_OTG_DSTS_SUSPSTS                 0x00000001U            /*!< Suspend status   */
-
-#define USB_OTG_DSTS_ENUMSPD                 0x00000006U            /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_DSTS_ENUMSPD_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_DSTS_EERR                    0x00000008U            /*!< Erratic error     */
-#define USB_OTG_DSTS_FNSOF                   0x003FFF00U            /*!< Frame number of the received SOF */
-
-/********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/
-#define USB_OTG_GAHBCFG_GINT                    0x00000001U            /*!< Global interrupt mask */
-
-#define USB_OTG_GAHBCFG_HBSTLEN                 0x0000001EU            /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_GAHBCFG_HBSTLEN_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_GAHBCFG_HBSTLEN_2               0x00000008U            /*!<Bit 2 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3               0x00000010U            /*!<Bit 3 */
-#define USB_OTG_GAHBCFG_DMAEN                   0x00000020U            /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL                 0x00000080U            /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL                0x00000100U            /*!< Periodic TxFIFO empty level */
-
-/********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/
-
-#define USB_OTG_GUSBCFG_TOCAL                   0x00000007U            /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TOCAL_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TOCAL_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_PHYSEL                  0x00000040U            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP                  0x00000100U            /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP                  0x00000200U            /*!< HNP-capable */
-
-#define USB_OTG_GUSBCFG_TRDT                    0x00003C00U            /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                  0x00000400U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TRDT_1                  0x00000800U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TRDT_2                  0x00001000U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_TRDT_3                  0x00002000U            /*!<Bit 3 */
-#define USB_OTG_GUSBCFG_PHYLPCS                 0x00008000U            /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS                0x00020000U            /*!< ULPI FS/LS select               */
-#define USB_OTG_GUSBCFG_ULPIAR                  0x00040000U            /*!< ULPI Auto-resume                */
-#define USB_OTG_GUSBCFG_ULPICSM                 0x00080000U            /*!< ULPI Clock SuspendM             */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD              0x00100000U            /*!< ULPI External VBUS Drive        */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI              0x00200000U            /*!< ULPI external VBUS indicator    */
-#define USB_OTG_GUSBCFG_TSDPS                   0x00400000U            /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI                    0x00800000U            /*!< Indicator complement            */
-#define USB_OTG_GUSBCFG_PTCI                    0x01000000U            /*!< Indicator pass through          */
-#define USB_OTG_GUSBCFG_ULPIIPD                 0x02000000U            /*!< ULPI interface protect disable  */
-#define USB_OTG_GUSBCFG_FHMOD                   0x20000000U            /*!< Forced host mode                */
-#define USB_OTG_GUSBCFG_FDMOD                   0x40000000U            /*!< Forced peripheral mode          */
-#define USB_OTG_GUSBCFG_CTXPKT                  0x80000000U            /*!< Corrupt Tx packet               */
-
-/********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
-#define USB_OTG_GRSTCTL_CSRST                   0x00000001U            /*!< Core soft reset          */
-#define USB_OTG_GRSTCTL_HSRST                   0x00000002U            /*!< HCLK soft reset          */
-#define USB_OTG_GRSTCTL_FCRST                   0x00000004U            /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH                 0x00000010U            /*!< RxFIFO flush             */
-#define USB_OTG_GRSTCTL_TXFFLSH                 0x00000020U            /*!< TxFIFO flush             */
-
-#define USB_OTG_GRSTCTL_TXFNUM                  0x000007C0U            /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                0x00000040U            /*!<Bit 0 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                0x00000080U            /*!<Bit 1 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                0x00000100U            /*!<Bit 2 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                0x00000200U            /*!<Bit 3 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                0x00000400U            /*!<Bit 4 */
-#define USB_OTG_GRSTCTL_DMAREQ                  0x40000000U            /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL                  0x80000000U            /*!< AHB master idle */
-
-/********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/
-#define USB_OTG_DIEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask                 */
-#define USB_OTG_DIEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask                  */
-#define USB_OTG_DIEPMSK_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask          */
-#define USB_OTG_DIEPMSK_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask           */
-#define USB_OTG_DIEPMSK_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask                    */
-#define USB_OTG_DIEPMSK_TXFURM                  0x00000100U            /*!< FIFO underrun mask                                */
-#define USB_OTG_DIEPMSK_BIM                     0x00000200U            /*!< BNA interrupt mask                                */
-
-/********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/
-#define USB_OTG_HPTXSTS_PTXFSAVL                0x0000FFFFU            /*!< Periodic transmit data FIFO space available     */
-
-#define USB_OTG_HPTXSTS_PTXQSAV                 0x00FF0000U            /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0               0x00010000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1               0x00020000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2               0x00040000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3               0x00080000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4               0x00100000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5               0x00200000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6               0x00400000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7               0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_HPTXSTS_PTXQTOP                 0xFF000000U            /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0               0x01000000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1               0x02000000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2               0x04000000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3               0x08000000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4               0x10000000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5               0x20000000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6               0x40000000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7               0x80000000U            /*!<Bit 7 */
-
-/********************  Bit definition forUSB_OTG_HAINT register  ********************/
-#define USB_OTG_HAINT_HAINT                   0x0000FFFFU            /*!< Channel interrupts */
-
-/********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/
-#define USB_OTG_DOEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask               */
-#define USB_OTG_DOEPMSK_STUPM                   0x00000008U            /*!< SETUP phase done mask                          */
-#define USB_OTG_DOEPMSK_OTEPDM                  0x00000010U            /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received mask       */
-#define USB_OTG_DOEPMSK_OPEM                    0x00000100U            /*!< OUT packet error mask                          */
-#define USB_OTG_DOEPMSK_BOIM                    0x00000200U            /*!< BNA interrupt mask                             */
-
-/********************  Bit definition forUSB_OTG_GINTSTS register  ********************/
-#define USB_OTG_GINTSTS_CMOD                    0x00000001U            /*!< Current mode of operation           */
-#define USB_OTG_GINTSTS_MMIS                    0x00000002U            /*!< Mode mismatch interrupt             */
-#define USB_OTG_GINTSTS_OTGINT                  0x00000004U            /*!< OTG interrupt                       */
-#define USB_OTG_GINTSTS_SOF                     0x00000008U            /*!< Start of frame                      */
-#define USB_OTG_GINTSTS_RXFLVL                  0x00000010U            /*!< RxFIFO nonempty                     */
-#define USB_OTG_GINTSTS_NPTXFE                  0x00000020U            /*!< Nonperiodic TxFIFO empty            */
-#define USB_OTG_GINTSTS_GINAKEFF                0x00000040U            /*!< Global IN nonperiodic NAK effective */
-#define USB_OTG_GINTSTS_BOUTNAKEFF              0x00000080U            /*!< Global OUT NAK effective            */
-#define USB_OTG_GINTSTS_ESUSP                   0x00000400U            /*!< Early suspend                            */
-#define USB_OTG_GINTSTS_USBSUSP                 0x00000800U            /*!< USB suspend                              */
-#define USB_OTG_GINTSTS_USBRST                  0x00001000U            /*!< USB reset                                */
-#define USB_OTG_GINTSTS_ENUMDNE                 0x00002000U            /*!< Enumeration done                         */
-#define USB_OTG_GINTSTS_ISOODRP                 0x00004000U            /*!< Isochronous OUT packet dropped interrupt */
-#define USB_OTG_GINTSTS_EOPF                    0x00008000U            /*!< End of periodic frame interrupt          */
-#define USB_OTG_GINTSTS_IEPINT                  0x00040000U            /*!< IN endpoint interrupt                          */
-#define USB_OTG_GINTSTS_OEPINT                  0x00080000U            /*!< OUT endpoint interrupt                         */
-#define USB_OTG_GINTSTS_IISOIXFR                0x00100000U            /*!< Incomplete isochronous IN transfer             */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       0x00200000U            /*!< Incomplete periodic transfer                   */
-#define USB_OTG_GINTSTS_DATAFSUSP               0x00400000U            /*!< Data fetch suspended                           */
-#define USB_OTG_GINTSTS_HPRTINT                 0x01000000U            /*!< Host port interrupt                            */
-#define USB_OTG_GINTSTS_HCINT                   0x02000000U            /*!< Host channels interrupt                        */
-#define USB_OTG_GINTSTS_PTXFE                   0x04000000U            /*!< Periodic TxFIFO empty                          */
-#define USB_OTG_GINTSTS_CIDSCHG                 0x10000000U            /*!< Connector ID status change                     */
-#define USB_OTG_GINTSTS_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt                  */
-#define USB_OTG_GINTSTS_SRQINT                  0x40000000U            /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT                  0x80000000U            /*!< Resume/remote wakeup detected interrupt        */
-
-/********************  Bit definition forUSB_OTG_GINTMSK register  ********************/
-#define USB_OTG_GINTMSK_MMISM                   0x00000002U            /*!< Mode mismatch interrupt mask                        */
-#define USB_OTG_GINTMSK_OTGINT                  0x00000004U            /*!< OTG interrupt mask                                  */
-#define USB_OTG_GINTMSK_SOFM                    0x00000008U            /*!< Start of frame mask                                 */
-#define USB_OTG_GINTMSK_RXFLVLM                 0x00000010U            /*!< Receive FIFO nonempty mask                          */
-#define USB_OTG_GINTMSK_NPTXFEM                 0x00000020U            /*!< Nonperiodic TxFIFO empty mask                       */
-#define USB_OTG_GINTMSK_GINAKEFFM               0x00000040U            /*!< Global nonperiodic IN NAK effective mask            */
-#define USB_OTG_GINTMSK_GONAKEFFM               0x00000080U            /*!< Global OUT NAK effective mask                       */
-#define USB_OTG_GINTMSK_ESUSPM                  0x00000400U            /*!< Early suspend mask                                  */
-#define USB_OTG_GINTMSK_USBSUSPM                0x00000800U            /*!< USB suspend mask                                    */
-#define USB_OTG_GINTMSK_USBRST                  0x00001000U            /*!< USB reset mask                                      */
-#define USB_OTG_GINTMSK_ENUMDNEM                0x00002000U            /*!< Enumeration done mask                               */
-#define USB_OTG_GINTMSK_ISOODRPM                0x00004000U            /*!< Isochronous OUT packet dropped interrupt mask       */
-#define USB_OTG_GINTMSK_EOPFM                   0x00008000U            /*!< End of periodic frame interrupt mask                */
-#define USB_OTG_GINTMSK_EPMISM                  0x00020000U            /*!< Endpoint mismatch interrupt mask                    */
-#define USB_OTG_GINTMSK_IEPINT                  0x00040000U            /*!< IN endpoints interrupt mask                         */
-#define USB_OTG_GINTMSK_OEPINT                  0x00080000U            /*!< OUT endpoints interrupt mask                        */
-#define USB_OTG_GINTMSK_IISOIXFRM               0x00100000U            /*!< Incomplete isochronous IN transfer mask             */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         0x00200000U            /*!< Incomplete periodic transfer mask                   */
-#define USB_OTG_GINTMSK_FSUSPM                  0x00400000U            /*!< Data fetch suspended mask                           */
-#define USB_OTG_GINTMSK_PRTIM                   0x01000000U            /*!< Host port interrupt mask                            */
-#define USB_OTG_GINTMSK_HCIM                    0x02000000U            /*!< Host channels interrupt mask                        */
-#define USB_OTG_GINTMSK_PTXFEM                  0x04000000U            /*!< Periodic TxFIFO empty mask                          */
-#define USB_OTG_GINTMSK_CIDSCHGM                0x10000000U            /*!< Connector ID status change mask                     */
-#define USB_OTG_GINTMSK_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt mask                  */
-#define USB_OTG_GINTMSK_SRQIM                   0x40000000U            /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM                    0x80000000U            /*!< Resume/remote wakeup detected interrupt mask        */
-
-/********************  Bit definition forUSB_OTG_DAINT register  ********************/
-#define USB_OTG_DAINT_IEPINT                  0x0000FFFFU            /*!< IN endpoint interrupt bits  */
-#define USB_OTG_DAINT_OEPINT                  0xFFFF0000U            /*!< OUT endpoint interrupt bits */
-
-/********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/
-#define USB_OTG_HAINTMSK_HAINTM                  0x0000FFFFU            /*!< Channel interrupt mask */
-
-/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
-#define USB_OTG_GRXSTSP_EPNUM                    0x0000000FU            /*!< IN EP interrupt mask bits  */
-#define USB_OTG_GRXSTSP_BCNT                     0x00007FF0U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID                     0x00018000U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS                   0x001E0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/
-#define USB_OTG_DAINTMSK_IEPM                    0x0000FFFFU            /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM                    0xFFFF0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for OTG register  ********************/
-
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition for OTG register  ********************/
-
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/
-#define USB_OTG_GRXFSIZ_RXFD            0x0000FFFFU            /*!< RxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/
-#define USB_OTG_DVBUSDIS_VBUSDT         0x0000FFFFU            /*!< Device VBUS discharge time */
-
-/********************  Bit definition for OTG register  ********************/
-#define USB_OTG_NPTXFSA                 0x0000FFFFU            /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD                  0xFFFF0000U            /*!< Nonperiodic TxFIFO depth               */
-#define USB_OTG_TX0FSA                  0x0000FFFFU            /*!< Endpoint 0 transmit RAM start address  */
-#define USB_OTG_TX0FD                   0xFFFF0000U            /*!< Endpoint 0 TxFIFO depth                */
-
-/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
-#define USB_OTG_DVBUSPULSE_DVBUSP                  0x00000FFFU            /*!< Device VBUS pulsing time */
-
-/********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/
-#define USB_OTG_GNPTXSTS_NPTXFSAV                0x0000FFFFU            /*!< Nonperiodic TxFIFO space available */
-
-#define USB_OTG_GNPTXSTS_NPTQXSAV                0x00FF0000U            /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0              0x00010000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1              0x00020000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2              0x00040000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3              0x00080000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4              0x00100000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5              0x00200000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6              0x00400000U            /*!<Bit 6 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7              0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_GNPTXSTS_NPTXQTOP                0x7F000000U            /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0              0x01000000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1              0x02000000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2              0x04000000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3              0x08000000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4              0x10000000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5              0x20000000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6              0x40000000U            /*!<Bit 6 */
-
-/********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/
-#define USB_OTG_DTHRCTL_NONISOTHREN             0x00000001U            /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN                0x00000002U            /*!< ISO IN endpoint threshold enable */
-
-#define USB_OTG_DTHRCTL_TXTHRLEN                0x000007FCU            /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0              0x00000004U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1              0x00000008U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2              0x00000010U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3              0x00000020U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4              0x00000040U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5              0x00000080U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6              0x00000100U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7              0x00000200U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8              0x00000400U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_RXTHREN                 0x00010000U            /*!< Receive threshold enable */
-
-#define USB_OTG_DTHRCTL_RXTHRLEN                0x03FE0000U            /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0              0x00020000U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1              0x00040000U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2              0x00080000U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3              0x00100000U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4              0x00200000U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5              0x00400000U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6              0x00800000U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7              0x01000000U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8              0x02000000U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_ARPEN                   0x08000000U            /*!< Arbiter parking enable */
-
-/********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM               0x0000FFFFU            /*!< IN EP Tx FIFO empty interrupt mask bits */
-
-/********************  Bit definition forUSB_OTG_DEACHINT register  ********************/
-#define USB_OTG_DEACHINT_IEP1INT                 0x00000002U            /*!< IN endpoint 1interrupt bit   */
-#define USB_OTG_DEACHINT_OEP1INT                 0x00020000U            /*!< OUT endpoint 1 interrupt bit */
-
-/********************  Bit definition forUSB_OTG_GCCFG register  ********************/
-#define USB_OTG_GCCFG_PWRDWN                  0x00010000U            /*!< Power down */
-#define USB_OTG_GCCFG_I2CPADEN                0x00020000U            /*!< Enable I2C bus connection for the external I2C PHY interface */
-#define USB_OTG_GCCFG_VBUSASEN                0x00040000U            /*!< Enable the VBUS sensing device                               */
-#define USB_OTG_GCCFG_VBUSBSEN                0x00080000U            /*!< Enable the VBUS sensing device                               */
-#define USB_OTG_GCCFG_SOFOUTEN                0x00100000U            /*!< SOF output enable                                            */
-#define USB_OTG_GCCFG_NOVBUSSENS              0x00200000U            /*!< VBUS sensing disable option                                  */
-
-/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
-#define USB_OTG_DEACHINTMSK_IEP1INTM                0x00000002U            /*!< IN Endpoint 1 interrupt mask bit  */
-#define USB_OTG_DEACHINTMSK_OEP1INTM                0x00020000U            /*!< OUT Endpoint 1 interrupt mask bit */
-
-/********************  Bit definition forUSB_OTG_CID register  ********************/
-#define USB_OTG_CID_PRODUCT_ID              0xFFFFFFFFU            /*!< Product ID field */
-
-/********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/
-#define USB_OTG_DIEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask                 */
-#define USB_OTG_DIEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask                  */
-#define USB_OTG_DIEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask          */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask           */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask                    */
-#define USB_OTG_DIEPEACHMSK1_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
-
-/********************  Bit definition forUSB_OTG_HPRT register  ********************/
-#define USB_OTG_HPRT_PCSTS                   0x00000001U            /*!< Port connect status        */
-#define USB_OTG_HPRT_PCDET                   0x00000002U            /*!< Port connect detected      */
-#define USB_OTG_HPRT_PENA                    0x00000004U            /*!< Port enable                */
-#define USB_OTG_HPRT_PENCHNG                 0x00000008U            /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA                    0x00000010U            /*!< Port overcurrent active    */
-#define USB_OTG_HPRT_POCCHNG                 0x00000020U            /*!< Port overcurrent change    */
-#define USB_OTG_HPRT_PRES                    0x00000040U            /*!< Port resume   */
-#define USB_OTG_HPRT_PSUSP                   0x00000080U            /*!< Port suspend  */
-#define USB_OTG_HPRT_PRST                    0x00000100U            /*!< Port reset    */
-
-#define USB_OTG_HPRT_PLSTS                   0x00000C00U            /*!< Port line status */
-#define USB_OTG_HPRT_PLSTS_0                 0x00000400U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PLSTS_1                 0x00000800U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PPWR                    0x00001000U            /*!< Port power */
-
-#define USB_OTG_HPRT_PTCTL                   0x0001E000U            /*!< Port test control */
-#define USB_OTG_HPRT_PTCTL_0                 0x00002000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PTCTL_1                 0x00004000U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PTCTL_2                 0x00008000U            /*!<Bit 2 */
-#define USB_OTG_HPRT_PTCTL_3                 0x00010000U            /*!<Bit 3 */
-
-#define USB_OTG_HPRT_PSPD                    0x00060000U            /*!< Port speed */
-#define USB_OTG_HPRT_PSPD_0                  0x00020000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PSPD_1                  0x00040000U            /*!<Bit 1 */
-
-/********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/
-#define USB_OTG_DOEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DOEPEACHMSK1_TXFURM                  0x00000100U            /*!< OUT packet error mask */
-#define USB_OTG_DOEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_BERRM                   0x00001000U            /*!< Bubble error interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NYETM                   0x00004000U            /*!< NYET interrupt mask */
-
-/********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/
-#define USB_OTG_HPTXFSIZ_PTXSA                   0x0000FFFFU            /*!< Host periodic TxFIFO start address */
-#define USB_OTG_HPTXFSIZ_PTXFD                   0xFFFF0000U            /*!< Host periodic TxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/
-#define USB_OTG_DIEPCTL_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
-#define USB_OTG_DIEPCTL_USBAEP                  0x00008000U            /*!< USB active endpoint */
-#define USB_OTG_DIEPCTL_EONUM_DPID              0x00010000U            /*!< Even/odd frame */
-#define USB_OTG_DIEPCTL_NAKSTS                  0x00020000U            /*!< NAK status */
-
-#define USB_OTG_DIEPCTL_EPTYP                   0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_DIEPCTL_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_STALL                   0x00200000U            /*!< STALL handshake */
-
-#define USB_OTG_DIEPCTL_TXFNUM                  0x03C00000U            /*!< TxFIFO number */
-#define USB_OTG_DIEPCTL_TXFNUM_0                0x00400000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                0x00800000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                0x01000000U            /*!<Bit 2 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                0x02000000U            /*!<Bit 3 */
-#define USB_OTG_DIEPCTL_CNAK                    0x04000000U            /*!< Clear NAK */
-#define USB_OTG_DIEPCTL_SNAK                    0x08000000U            /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          0x10000000U            /*!< Set DATA0 PID */
-#define USB_OTG_DIEPCTL_SODDFRM                 0x20000000U            /*!< Set odd frame */
-#define USB_OTG_DIEPCTL_EPDIS                   0x40000000U            /*!< Endpoint disable */
-#define USB_OTG_DIEPCTL_EPENA                   0x80000000U            /*!< Endpoint enable */
-
-/********************  Bit definition forUSB_OTG_HCCHAR register  ********************/
-#define USB_OTG_HCCHAR_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
-
-#define USB_OTG_HCCHAR_EPNUM                   0x00007800U            /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPNUM_1                 0x00001000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_EPNUM_2                 0x00002000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_EPNUM_3                 0x00004000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_EPDIR                   0x00008000U            /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV                   0x00020000U            /*!< Low-speed device */
-
-#define USB_OTG_HCCHAR_EPTYP                   0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_MC                      0x00300000U            /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                    0x00100000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_MC_1                    0x00200000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_DAD                     0x1FC00000U            /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                   0x00400000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_DAD_1                   0x00800000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_DAD_2                   0x01000000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_DAD_3                   0x02000000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_DAD_4                   0x04000000U            /*!<Bit 4 */
-#define USB_OTG_HCCHAR_DAD_5                   0x08000000U            /*!<Bit 5 */
-#define USB_OTG_HCCHAR_DAD_6                   0x10000000U            /*!<Bit 6 */
-#define USB_OTG_HCCHAR_ODDFRM                  0x20000000U            /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS                   0x40000000U            /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA                   0x80000000U            /*!< Channel enable */
-
-/********************  Bit definition forUSB_OTG_HCSPLT register  ********************/
-
-#define USB_OTG_HCSPLT_PRTADDR                 0x0000007FU            /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_PRTADDR_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_PRTADDR_2               0x00000004U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_PRTADDR_3               0x00000008U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_PRTADDR_4               0x00000010U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_PRTADDR_5               0x00000020U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_PRTADDR_6               0x00000040U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_HUBADDR                 0x00003F80U            /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0               0x00000080U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_HUBADDR_1               0x00000100U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_HUBADDR_2               0x00000200U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_HUBADDR_3               0x00000400U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_HUBADDR_4               0x00000800U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_HUBADDR_5               0x00001000U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_HUBADDR_6               0x00002000U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_XACTPOS                 0x0000C000U            /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0               0x00004000U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_XACTPOS_1               0x00008000U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_COMPLSPLT               0x00010000U            /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN                 0x80000000U            /*!< Split enable */
-
-/********************  Bit definition forUSB_OTG_HCINT register  ********************/
-#define USB_OTG_HCINT_XFRC                    0x00000001U            /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH                     0x00000002U            /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINT_STALL                   0x00000008U            /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK                     0x00000010U            /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK                     0x00000020U            /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET                    0x00000040U            /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR                   0x00000080U            /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR                   0x00000100U            /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR                   0x00000200U            /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR                   0x00000400U            /*!< Data toggle error */
-
-/********************  Bit definition forUSB_OTG_DIEPINT register  ********************/
-#define USB_OTG_DIEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_TOC                     0x00000008U            /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE                  0x00000010U            /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNE                  0x00000040U            /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE                    0x00000080U            /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN              0x00000100U            /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA                     0x00000200U            /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS               0x00000800U            /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR                    0x00001000U            /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK                     0x00002000U            /*!< NAK interrupt */
-
-/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
-#define USB_OTG_HCINTMSK_XFRCM                   0x00000001U            /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM                    0x00000002U            /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM                  0x00000008U            /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM                    0x00000010U            /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM                    0x00000020U            /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET                    0x00000040U            /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM                  0x00000080U            /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM                  0x00000100U            /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM                  0x00000200U            /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM                  0x00000400U            /*!< Data toggle error mask */
-
-/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
-
-#define USB_OTG_DIEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT                  0x60000000U            /*!< Packet count */
-/********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/
-#define USB_OTG_HCTSIZ_XFRSIZ                    0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT                    0x1FF80000U            /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING                    0x80000000U            /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID                      0x60000000U            /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                    0x20000000U            /*!<Bit 0 */
-#define USB_OTG_HCTSIZ_DPID_1                    0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/
-#define USB_OTG_DIEPDMA_DMAADDR                  0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition forUSB_OTG_HCDMA register  ********************/
-#define USB_OTG_HCDMA_DMAADDR                    0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/
-#define USB_OTG_DTXFSTS_INEPTFSAV                0x0000FFFFU            /*!< IN endpoint TxFIFO space available */
-
-/********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/
-#define USB_OTG_DIEPTXF_INEPTXSA                 0x0000FFFFU            /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD                 0xFFFF0000U            /*!< IN endpoint TxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/
-
-#define USB_OTG_DOEPCTL_MPSIZ                     0x000007FFU            /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP                    0x00008000U            /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS                    0x00020000U            /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            0x10000000U            /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM                   0x20000000U            /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP                     0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                   0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DOEPCTL_EPTYP_1                   0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_SNPM                      0x00100000U            /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL                     0x00200000U            /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK                      0x04000000U            /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK                      0x08000000U            /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS                     0x40000000U            /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA                     0x80000000U            /*!< Endpoint enable */
-
-/********************  Bit definition forUSB_OTG_DOEPINT register  ********************/
-#define USB_OTG_DOEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_STUP                    0x00000008U            /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS                 0x00000010U            /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_NYET                    0x00004000U            /*!< NYET interrupt */
-
-/********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/
-
-#define USB_OTG_DOEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-
-#define USB_OTG_DOEPTSIZ_STUPCNT                 0x60000000U            /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0               0x20000000U            /*!<Bit 0 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1               0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition for PCGCCTL register  ********************/
-#define USB_OTG_PCGCCTL_STOPCLK                 0x00000001U            /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK                 0x00000002U            /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP                 0x00000010U            /*!<Bit 1 */
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
-                                       ((INSTANCE) == ADC2) || \
-                                       ((INSTANCE) == ADC3))
-
-/******************************* CAN Instances ********************************/
-#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
-                                       ((INSTANCE) == CAN2))
- 
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DAC Instances ********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/******************************* DCMI Instances *******************************/
-#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
-
-/******************************* DMA2D Instances *******************************/
-#define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
-
-/******************************** DMA Instances *******************************/
-#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
-                                              ((INSTANCE) == DMA1_Stream1) || \
-                                              ((INSTANCE) == DMA1_Stream2) || \
-                                              ((INSTANCE) == DMA1_Stream3) || \
-                                              ((INSTANCE) == DMA1_Stream4) || \
-                                              ((INSTANCE) == DMA1_Stream5) || \
-                                              ((INSTANCE) == DMA1_Stream6) || \
-                                              ((INSTANCE) == DMA1_Stream7) || \
-                                              ((INSTANCE) == DMA2_Stream0) || \
-                                              ((INSTANCE) == DMA2_Stream1) || \
-                                              ((INSTANCE) == DMA2_Stream2) || \
-                                              ((INSTANCE) == DMA2_Stream3) || \
-                                              ((INSTANCE) == DMA2_Stream4) || \
-                                              ((INSTANCE) == DMA2_Stream5) || \
-                                              ((INSTANCE) == DMA2_Stream6) || \
-                                              ((INSTANCE) == DMA2_Stream7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOF) || \
-                                        ((INSTANCE) == GPIOG) || \
-                                        ((INSTANCE) == GPIOH) || \
-                                        ((INSTANCE) == GPIOI) || \
-                                        ((INSTANCE) == GPIOJ) || \
-                                        ((INSTANCE) == GPIOK))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2) || \
-                                       ((INSTANCE) == I2C3))
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI2) || \
-                                        ((INSTANCE) == SPI3))
-
-/*************************** I2S Extended Instances ***************************/
-#define IS_I2S_ALL_INSTANCE_EXT(PERIPH)  (((INSTANCE) == SPI2)    || \
-                                          ((INSTANCE) == SPI3)    || \
-                                          ((INSTANCE) == I2S2ext) || \
-                                          ((INSTANCE) == I2S3ext))
-
-/******************************* RNG Instances ********************************/
-#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************* SAI Instances ********************************/
-#define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
-                                     ((PERIPH) == SAI1_Block_B))
-/* Legacy define */
-#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3) || \
-                                       ((INSTANCE) == SPI4) || \
-                                       ((INSTANCE) == SPI5) || \
-                                       ((INSTANCE) == SPI6))
-
-/*************************** SPI Extended Instances ***************************/
-#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1)    || \
-                                           ((INSTANCE) == SPI2)    || \
-                                           ((INSTANCE) == SPI3)    || \
-                                           ((INSTANCE) == SPI4)    || \
-                                           ((INSTANCE) == SPI5)    || \
-                                           ((INSTANCE) == SPI6)    || \
-                                           ((INSTANCE) == I2S2ext) || \
-                                           ((INSTANCE) == I2S3ext))
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
-                                   ((INSTANCE) == TIM2)   || \
-                                   ((INSTANCE) == TIM3)   || \
-                                   ((INSTANCE) == TIM4)   || \
-                                   ((INSTANCE) == TIM5)   || \
-                                   ((INSTANCE) == TIM6)   || \
-                                   ((INSTANCE) == TIM7)   || \
-                                   ((INSTANCE) == TIM8)   || \
-                                   ((INSTANCE) == TIM9)   || \
-                                   ((INSTANCE) == TIM10)  || \
-                                   ((INSTANCE) == TIM11)  || \
-                                   ((INSTANCE) == TIM12)  || \
-                                   ((INSTANCE) == TIM13)  || \
-                                   ((INSTANCE) == TIM14))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
-                                         ((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM8)  || \
-                                         ((INSTANCE) == TIM9)  || \
-                                         ((INSTANCE) == TIM10) || \
-                                         ((INSTANCE) == TIM11) || \
-                                         ((INSTANCE) == TIM12) || \
-                                         ((INSTANCE) == TIM13) || \
-                                         ((INSTANCE) == TIM14))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM8) || \
-                                       ((INSTANCE) == TIM9) || \
-                                       ((INSTANCE) == TIM12))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8))
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM8))
-
-/******************** TIM Instances : Advanced-control timers *****************/
-#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                            ((INSTANCE) == TIM8))
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8))
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM6) || \
-                                       ((INSTANCE) == TIM7) || \
-                                       ((INSTANCE) == TIM8))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM8))
-
-/************ TIM Instances : DMA requests generation (COMDE) *****************/
-#define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM8)) 
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                             ((INSTANCE) == TIM2) || \
-                                             ((INSTANCE) == TIM3) || \
-                                             ((INSTANCE) == TIM4) || \
-                                             ((INSTANCE) == TIM5) || \
-                                             ((INSTANCE) == TIM8))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM6) || \
-                                          ((INSTANCE) == TIM7) || \
-                                          ((INSTANCE) == TIM8) || \
-                                          ((INSTANCE) == TIM9) || \
-                                          ((INSTANCE) == TIM12))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8) || \
-                                         ((INSTANCE) == TIM9) || \
-                                         ((INSTANCE) == TIM12))
-
-/********************** TIM Instances : 32 bit Counter ************************/
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
-                                              ((INSTANCE) == TIM5))
-
-/***************** TIM Instances : external trigger input availabe ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                        ((INSTANCE) == TIM2) || \
-                                        ((INSTANCE) == TIM3) || \
-                                        ((INSTANCE) == TIM4) || \
-                                        ((INSTANCE) == TIM5) || \
-                                        ((INSTANCE) == TIM8))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM11))
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM1) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM5) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM8) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM12) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM13) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM14) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-/************ TIM Instances : complementary output(s) available ***************/
-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
-   ((((INSTANCE) == TIM1) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3)))            \
-    ||                                          \
-    (((INSTANCE) == TIM8) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3))))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3) || \
-                                     ((INSTANCE) == USART6))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5)  || \
-                                    ((INSTANCE) == USART6) || \
-                                    ((INSTANCE) == UART7)  || \
-                                    ((INSTANCE) == UART8))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3) || \
-                                           ((INSTANCE) == USART6))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3) || \
-                                         ((INSTANCE) == USART6))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5)  || \
-                                    ((INSTANCE) == USART6) || \
-                                    ((INSTANCE) == UART7)  || \
-                                    ((INSTANCE) == UART8))     
-
-/*********************** PCD Instances ****************************************/
-/*********************** PCD Instances ****************************************/
-#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
-                                        ((INSTANCE) == USB_OTG_HS))
-
-/*********************** HCD Instances ****************************************/
-#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
-                                       ((INSTANCE) == USB_OTG_HS))
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/****************************** SDIO Instances ********************************/
-#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
-
-/****************************** USB Exported Constants ************************/
-#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                8U
-#define USB_OTG_FS_MAX_IN_ENDPOINTS                    4U    /* Including EP0 */
-#define USB_OTG_FS_MAX_OUT_ENDPOINTS                   4U    /* Including EP0 */
-#define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */
-
-#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR                12U
-#define USB_OTG_HS_MAX_IN_ENDPOINTS                    6U    /* Including EP0 */
-#define USB_OTG_HS_MAX_OUT_ENDPOINTS                   6U    /* Including EP0 */
-#define USB_OTG_HS_TOTAL_FIFO_SIZE                     4096U /* in Bytes */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32F4xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */
-/*  product lines within the same STM32F4 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-#define FSMC_IRQn              FMC_IRQn
-
-/* Aliases for __IRQHandler */
-#define FSMC_IRQHandler        FMC_IRQHandler
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __stm32f427xx_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/cmsis/stm32f429xx.h b/stmhal/cmsis/stm32f429xx.h
deleted file mode 100644
index 4a240556e4..0000000000
--- a/stmhal/cmsis/stm32f429xx.h
+++ /dev/null
@@ -1,9118 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f429xx.h
-  * @author  MCD Application Team
-  * @version V2.5.1
-  * @date    28-June-2016
-  * @brief   CMSIS STM32F429xx Device Peripheral Access Layer Header File.
-  *
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - peripherals registers declarations and bits definition
-  *           - Macros to access peripheral’s registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS_Device
-  * @{
-  */
-
-/** @addtogroup stm32f429xx
-  * @{
-  */
-    
-#ifndef __STM32F429xx_H
-#define __STM32F429xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-  
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-
-/**
-  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
-  */
-#define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */
-#define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */
-#define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1U       /*!< FPU present                                   */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32F4XX Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-typedef enum
-{
-/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
-  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
-/******  STM32 specific Interrupt Numbers **********************************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
-  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
-  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
-  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
-  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
-  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
-  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
-  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
-  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
-  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
-  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
-  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
-  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
-  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
-  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
-  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
-  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
-  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */    
-  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
-  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
-  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
-  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
-  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
-  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
-  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
-  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
-  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
-  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
-  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
-  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
-  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
-  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
-  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
-  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
-  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
-  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
-  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
-  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
-  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
-  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
-  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
-  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
-  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
-  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
-  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
-  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
-  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
-  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
-  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
-  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
-  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
-  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
-  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
-  HASH_RNG_IRQn               = 80,     /*!< Hash and RNG global interrupt                                     */
-  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
-  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */
-  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */
-  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
-  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */
-  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */
-  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
-  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                              */
-  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                        */
-  DMA2D_IRQn                  = 90      /*!< DMA2D global Interrupt                                            */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
-#include "system_stm32f4xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */      
-  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
-  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
-  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
-  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
-  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
-  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
-  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
-  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
-  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
-  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
-  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
-  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
-  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
-  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
-  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
-                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
-} ADC_Common_TypeDef;
-
-
-/** 
-  * @brief Controller Area Network TxMailBox 
-  */
-
-typedef struct
-{
-  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
-  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
-  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
-  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
-} CAN_TxMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FIFOMailBox 
-  */
-  
-typedef struct
-{
-  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
-  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
-  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
-  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
-} CAN_FIFOMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FilterRegister 
-  */
-  
-typedef struct
-{
-  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
-  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
-} CAN_FilterRegister_TypeDef;
-
-/** 
-  * @brief Controller Area Network 
-  */
-  
-typedef struct
-{
-  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
-  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
-  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
-  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
-  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
-  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
-  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
-  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
-  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
-  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
-  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
-  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
-  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
-  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
-  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
-  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
-  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
-  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
-  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
-  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
-  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */ 
-  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
-} CAN_TypeDef;
-
-/** 
-  * @brief CRC calculation unit 
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
-  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */
-  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
-  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
-  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
-  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
-  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
-  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
-  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
-  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
-  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
-  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
-  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
-  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
-  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
-  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
-  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
-  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
-  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
-  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DCMI
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
-  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
-  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
-  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
-  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
-  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
-  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
-  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
-  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
-  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
-  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
-} DCMI_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
-  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
-  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
-  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
-  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
-  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
-} DMA_Stream_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
-  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
-  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
-  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
-} DMA_TypeDef;
-
-/** 
-  * @brief DMA2D Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
-  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
-  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
-  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
-  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
-  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
-  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
-  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
-  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
-  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
-  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
-  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
-  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
-  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
-  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
-  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
-  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
-  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
-  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
-  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
-  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
-  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */
-  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */
-} DMA2D_TypeDef;
-
-/** 
-  * @brief Ethernet MAC
-  */
-
-typedef struct
-{
-  __IO uint32_t MACCR;
-  __IO uint32_t MACFFR;
-  __IO uint32_t MACHTHR;
-  __IO uint32_t MACHTLR;
-  __IO uint32_t MACMIIAR;
-  __IO uint32_t MACMIIDR;
-  __IO uint32_t MACFCR;
-  __IO uint32_t MACVLANTR;             /*    8 */
-  uint32_t      RESERVED0[2];
-  __IO uint32_t MACRWUFFR;             /*   11 */
-  __IO uint32_t MACPMTCSR;
-  uint32_t      RESERVED1[2];
-  __IO uint32_t MACSR;                 /*   15 */
-  __IO uint32_t MACIMR;
-  __IO uint32_t MACA0HR;
-  __IO uint32_t MACA0LR;
-  __IO uint32_t MACA1HR;
-  __IO uint32_t MACA1LR;
-  __IO uint32_t MACA2HR;
-  __IO uint32_t MACA2LR;
-  __IO uint32_t MACA3HR;
-  __IO uint32_t MACA3LR;               /*   24 */
-  uint32_t      RESERVED2[40];
-  __IO uint32_t MMCCR;                 /*   65 */
-  __IO uint32_t MMCRIR;
-  __IO uint32_t MMCTIR;
-  __IO uint32_t MMCRIMR;
-  __IO uint32_t MMCTIMR;               /*   69 */
-  uint32_t      RESERVED3[14];
-  __IO uint32_t MMCTGFSCCR;            /*   84 */
-  __IO uint32_t MMCTGFMSCCR;
-  uint32_t      RESERVED4[5];
-  __IO uint32_t MMCTGFCR;
-  uint32_t      RESERVED5[10];
-  __IO uint32_t MMCRFCECR;
-  __IO uint32_t MMCRFAECR;
-  uint32_t      RESERVED6[10];
-  __IO uint32_t MMCRGUFCR;
-  uint32_t      RESERVED7[334];
-  __IO uint32_t PTPTSCR;
-  __IO uint32_t PTPSSIR;
-  __IO uint32_t PTPTSHR;
-  __IO uint32_t PTPTSLR;
-  __IO uint32_t PTPTSHUR;
-  __IO uint32_t PTPTSLUR;
-  __IO uint32_t PTPTSAR;
-  __IO uint32_t PTPTTHR;
-  __IO uint32_t PTPTTLR;
-  __IO uint32_t RESERVED8;
-  __IO uint32_t PTPTSSR;
-  uint32_t      RESERVED9[565];
-  __IO uint32_t DMABMR;
-  __IO uint32_t DMATPDR;
-  __IO uint32_t DMARPDR;
-  __IO uint32_t DMARDLAR;
-  __IO uint32_t DMATDLAR;
-  __IO uint32_t DMASR;
-  __IO uint32_t DMAOMR;
-  __IO uint32_t DMAIER;
-  __IO uint32_t DMAMFBOCR;
-  __IO uint32_t DMARSWTR;
-  uint32_t      RESERVED10[8];
-  __IO uint32_t DMACHTDR;
-  __IO uint32_t DMACHRDR;
-  __IO uint32_t DMACHTBAR;
-  __IO uint32_t DMACHRBAR;
-} ETH_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
-  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
-  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
-  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
-  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
-  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-
-typedef struct
-{
-  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */
-  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */
-  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */
-  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */
-  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */
-  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief Flexible Memory Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */   
-} FMC_Bank1_TypeDef; 
-
-/** 
-  * @brief Flexible Memory Controller Bank1E
-  */
-  
-typedef struct
-{
-  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
-} FMC_Bank1E_TypeDef;
-
-/** 
-  * @brief Flexible Memory Controller Bank2
-  */
-  
-typedef struct
-{
-  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */
-  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */
-  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */
-  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
-  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */
-  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */
-  uint32_t      RESERVED1;  /*!< Reserved, 0x78                                                            */
-  uint32_t      RESERVED2;  /*!< Reserved, 0x7C                                                            */
-  __IO uint32_t PCR3;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */
-  __IO uint32_t SR3;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */
-  __IO uint32_t PMEM3;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */
-  __IO uint32_t PATT3;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
-  uint32_t      RESERVED3;  /*!< Reserved, 0x90                                                            */
-  __IO uint32_t ECCR3;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */
-} FMC_Bank2_3_TypeDef;
-
-/** 
-  * @brief Flexible Memory Controller Bank4
-  */
-  
-typedef struct
-{
-  __IO uint32_t PCR4;       /*!< PC Card  control register 4,                       Address offset: 0xA0 */
-  __IO uint32_t SR4;        /*!< PC Card  FIFO status and interrupt register 4,     Address offset: 0xA4 */
-  __IO uint32_t PMEM4;      /*!< PC Card  Common memory space timing register 4,    Address offset: 0xA8 */
-  __IO uint32_t PATT4;      /*!< PC Card  Attribute memory space timing register 4, Address offset: 0xAC */
-  __IO uint32_t PIO4;       /*!< PC Card  I/O space timing register 4,              Address offset: 0xB0 */
-} FMC_Bank4_TypeDef; 
-
-/** 
-  * @brief Flexible Memory Controller Bank5_6
-  */
-  
-typedef struct
-{
-  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */
-  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */
-  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */
-  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */
-  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */
-} FMC_Bank5_6_TypeDef; 
-
-/** 
-  * @brief General Purpose I/O
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
-  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
-  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
-  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
-  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
-  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
-  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
-  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/** 
-  * @brief System configuration controller
-  */
-  
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */ 
-  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */
-  __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */
-  __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */
-  __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */
-  __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */
-  __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
-  __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
-  __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
-  __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief LCD-TFT Display Controller
-  */
-  
-typedef struct
-{
-  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04 */
-  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */
-  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */
-  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */
-  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */
-  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */
-  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20 */
-  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */
-  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28 */
-  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */
-  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30 */
-  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */
-  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */
-  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */
-  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
-  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */
-  __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                       Address offset: 0x48 */
-} LTDC_TypeDef;  
-
-/** 
-  * @brief LCD-TFT Display layer x Controller
-  */
-  
-typedef struct
-{  
-  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */
-  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
-  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */
-  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */
-  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */
-  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */
-  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */
-  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */
-  uint32_t      RESERVED0[2];  /*!< Reserved */
-  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */
-  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */
-  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */
-  uint32_t      RESERVED1[3];  /*!< Reserved */
-  __IO uint32_t CLUTWR;         /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */
-
-} LTDC_Layer_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
-  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
-  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
-  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
-  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
-  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
-  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
-  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
-  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
-  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
-  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
-  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
-  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
-  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
-  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
-  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
-  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
-  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
-  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
-  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
-  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
-  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
-  __IO uint32_t PLLSAICFGR;    /*!< RCC PLLSAI configuration register,                           Address offset: 0x88 */
-  __IO uint32_t DCKCFGR;       /*!< RCC Dedicated Clocks configuration register,                 Address offset: 0x8C */
-
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-
-typedef struct
-{
-  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
-  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
-  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
-  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
-  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
-  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
-  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */
-  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
-  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */
-  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
-  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */
-  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */
-  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */
-  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */
-  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
-  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */
-  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
-  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
-  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
-  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
-  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
-  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
-  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
-  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
-  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
-  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
-  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
-  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
-  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
-  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
-  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
-  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
-  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
-  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
-  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
-  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
-  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
-} RTC_TypeDef;
-
-/** 
-  * @brief Serial Audio Interface
-  */
-  
-typedef struct
-{
-  __IO uint32_t GCR;      /*!< SAI global configuration register,        Address offset: 0x00 */
-} SAI_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */
-  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */
-  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */
-  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */
-  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
-  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */
-  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */
-  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */
-} SAI_Block_TypeDef;
-
-/** 
-  * @brief SD host Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t POWER;          /*!< SDIO power control register,    Address offset: 0x00 */
-  __IO uint32_t CLKCR;          /*!< SDI clock control register,     Address offset: 0x04 */
-  __IO uint32_t ARG;            /*!< SDIO argument register,         Address offset: 0x08 */
-  __IO uint32_t CMD;            /*!< SDIO command register,          Address offset: 0x0C */
-  __I uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */
-  __I uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */
-  __I uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */
-  __I uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */
-  __I uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */
-  __IO uint32_t DTIMER;         /*!< SDIO data timer register,       Address offset: 0x24 */
-  __IO uint32_t DLEN;           /*!< SDIO data length register,      Address offset: 0x28 */
-  __IO uint32_t DCTRL;          /*!< SDIO data control register,     Address offset: 0x2C */
-  __I uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */
-  __I uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */
-  __IO uint32_t ICR;            /*!< SDIO interrupt clear register,  Address offset: 0x38 */
-  __IO uint32_t MASK;           /*!< SDIO mask register,             Address offset: 0x3C */
-  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
-  __I uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */
-  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
-  __IO uint32_t FIFO;           /*!< SDIO data FIFO register,        Address offset: 0x80 */
-} SDIO_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
-  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
-  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
-  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-
-/** 
-  * @brief RNG
-  */
-  
-typedef struct 
-{
-  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
-  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
-  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
-} RNG_TypeDef;
-
- 
-/** 
-  * @brief __USB_OTG_Core_register
-  */
-typedef struct
-{
-  __IO uint32_t GOTGCTL;      /*!<  USB_OTG Control and Status Register    000h */
-  __IO uint32_t GOTGINT;      /*!<  USB_OTG Interrupt Register             004h */
-  __IO uint32_t GAHBCFG;      /*!<  Core AHB Configuration Register        008h */
-  __IO uint32_t GUSBCFG;      /*!<  Core USB Configuration Register        00Ch */
-  __IO uint32_t GRSTCTL;      /*!<  Core Reset Register                    010h */
-  __IO uint32_t GINTSTS;      /*!<  Core Interrupt Register                014h */
-  __IO uint32_t GINTMSK;      /*!<  Core Interrupt Mask Register           018h */
-  __IO uint32_t GRXSTSR;      /*!<  Receive Sts Q Read Register            01Ch */
-  __IO uint32_t GRXSTSP;      /*!<  Receive Sts Q Read & POP Register      020h */
-  __IO uint32_t GRXFSIZ;      /* Receive FIFO Size Register                024h */
-  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!<  EP0 / Non Periodic Tx FIFO Size Register 028h*/
-  __IO uint32_t HNPTXSTS;     /*!<  Non Periodic Tx FIFO/Queue Sts reg     02Ch */
-  uint32_t Reserved30[2];     /* Reserved                           030h*/
-  __IO uint32_t GCCFG;        /* General Purpose IO Register        038h*/
-  __IO uint32_t CID;          /* User ID Register                   03Ch*/
-  uint32_t  Reserved40[48];   /* Reserved                      040h-0FFh*/
-  __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg     100h*/
-  __IO uint32_t DIEPTXF[0x0F];/* dev Periodic Transmit FIFO */
-}
-USB_OTG_GlobalTypeDef;
-
-
-/** 
-  * @brief __device_Registers
-  */
-typedef struct 
-{
-  __IO uint32_t DCFG;         /* dev Configuration Register   800h*/
-  __IO uint32_t DCTL;         /* dev Control Register         804h*/
-  __IO uint32_t DSTS;         /* dev Status Register (RO)     808h*/
-  uint32_t Reserved0C;           /* Reserved                     80Ch*/
-  __IO uint32_t DIEPMSK;   /* dev IN Endpoint Mask         810h*/
-  __IO uint32_t DOEPMSK;  /* dev OUT Endpoint Mask        814h*/
-  __IO uint32_t DAINT;     /* dev All Endpoints Itr Reg    818h*/
-  __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask   81Ch*/
-  uint32_t  Reserved20;          /* Reserved                     820h*/
-  uint32_t Reserved9;       /* Reserved                     824h*/
-  __IO uint32_t DVBUSDIS;    /* dev VBUS discharge Register  828h*/
-  __IO uint32_t DVBUSPULSE;  /* dev VBUS Pulse Register      82Ch*/
-  __IO uint32_t DTHRCTL;     /* dev thr                      830h*/
-  __IO uint32_t DIEPEMPMSK; /* dev empty msk             834h*/
-  __IO uint32_t DEACHINT;    /* dedicated EP interrupt       838h*/
-  __IO uint32_t DEACHMSK;    /* dedicated EP msk             83Ch*/  
-  uint32_t Reserved40;      /* dedicated EP mask           840h*/
-  __IO uint32_t DINEP1MSK;  /* dedicated EP mask           844h*/
-  uint32_t  Reserved44[15];      /* Reserved                 844-87Ch*/
-  __IO uint32_t DOUTEP1MSK; /* dedicated EP msk            884h*/   
-}
-USB_OTG_DeviceTypeDef;
-
-
-/** 
-  * @brief __IN_Endpoint-Specific_Register
-  */
-typedef struct 
-{
-  __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
-  uint32_t Reserved04;             /* Reserved                       900h + (ep_num * 20h) + 04h*/
-  __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg     900h + (ep_num * 20h) + 08h*/
-  uint32_t Reserved0C;             /* Reserved                       900h + (ep_num * 20h) + 0Ch*/
-  __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size   900h + (ep_num * 20h) + 10h*/
-  __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h*/
-  __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
-  uint32_t Reserved18;             /* Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
-}
-USB_OTG_INEndpointTypeDef;
-
-
-/** 
-  * @brief __OUT_Endpoint-Specific_Registers
-  */
-typedef struct 
-{
-  __IO uint32_t DOEPCTL;       /* dev OUT Endpoint Control Reg  B00h + (ep_num * 20h) + 00h*/
-  uint32_t Reserved04;         /* Reserved                      B00h + (ep_num * 20h) + 04h*/
-  __IO uint32_t DOEPINT;       /* dev OUT Endpoint Itr Reg      B00h + (ep_num * 20h) + 08h*/
-  uint32_t Reserved0C;         /* Reserved                      B00h + (ep_num * 20h) + 0Ch*/
-  __IO uint32_t DOEPTSIZ;      /* dev OUT Endpoint Txfer Size   B00h + (ep_num * 20h) + 10h*/
-  __IO uint32_t DOEPDMA;       /* dev OUT Endpoint DMA Address  B00h + (ep_num * 20h) + 14h*/
-  uint32_t Reserved18[2];      /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
-}
-USB_OTG_OUTEndpointTypeDef;
-
-
-/** 
-  * @brief __Host_Mode_Register_Structures
-  */
-typedef struct 
-{
-  __IO uint32_t HCFG;             /* Host Configuration Register    400h*/
-  __IO uint32_t HFIR;      /* Host Frame Interval Register   404h*/
-  __IO uint32_t HFNUM;         /* Host Frame Nbr/Frame Remaining 408h*/
-  uint32_t Reserved40C;                   /* Reserved                       40Ch*/
-  __IO uint32_t HPTXSTS;   /* Host Periodic Tx FIFO/ Queue Status 410h*/
-  __IO uint32_t HAINT;   /* Host All Channels Interrupt Register 414h*/
-  __IO uint32_t HAINTMSK;   /* Host All Channels Interrupt Mask 418h*/
-}
-USB_OTG_HostTypeDef;
-
-/** 
-  * @brief __Host_Channel_Specific_Registers
-  */
-typedef struct
-{
-  __IO uint32_t HCCHAR;
-  __IO uint32_t HCSPLT;
-  __IO uint32_t HCINT;
-  __IO uint32_t HCINTMSK;
-  __IO uint32_t HCTSIZ;
-  __IO uint32_t HCDMA;
-  uint32_t Reserved[2];
-}
-USB_OTG_HostChannelTypeDef;
-/**
-  * @}
-  */
-    
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-#define FLASH_BASE            0x08000000U /*!< FLASH(up to 2 MB) base address in the alias region                         */
-#define CCMDATARAM_BASE       0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
-#define SRAM1_BASE            0x20000000U /*!< SRAM1(112 KB) base address in the alias region                             */
-#define SRAM2_BASE            0x2001C000U /*!< SRAM2(16 KB) base address in the alias region                              */
-#define SRAM3_BASE            0x20020000U /*!< SRAM3(64 KB) base address in the alias region                              */
-#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region                                */
-#define BKPSRAM_BASE          0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region                         */
-#define FMC_R_BASE            0xA0000000U /*!< FMC registers base address                                                 */
-#define SRAM1_BB_BASE         0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region                             */
-#define SRAM2_BB_BASE         0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region                              */
-#define SRAM3_BB_BASE         0x22400000U /*!< SRAM3(64 KB) base address in the bit-band region                              */
-#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region                                */
-#define BKPSRAM_BB_BASE       0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region                         */
-#define FLASH_END             0x081FFFFFU /*!< FLASH end address */
-#define CCMDATARAM_END        0x1000FFFFU /*!< CCM data RAM end address */
-
-/* Legacy defines */
-#define SRAM_BASE             SRAM1_BASE
-#define SRAM_BB_BASE          SRAM1_BB_BASE
-
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000U)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)
-#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800U)
-#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00U)
-#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000U)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)
-#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400U)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)
-#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000U)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800U)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00U)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x5000U)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)
-#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)
-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)
-#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800U)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)
-#define UART7_BASE            (APB1PERIPH_BASE + 0x7800U)
-#define UART8_BASE            (APB1PERIPH_BASE + 0x7C00U)
-
-/*!< APB2 peripherals */
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000U)
-#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400U)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x1000U)
-#define USART6_BASE           (APB2PERIPH_BASE + 0x1400U)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000U)
-#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100U)
-#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200U)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x2300U)
-#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00U)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)
-#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400U)
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800U)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00U)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000U)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400U)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800U)
-#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000U)
-#define SPI6_BASE             (APB2PERIPH_BASE + 0x5400U)
-#define SAI1_BASE             (APB2PERIPH_BASE + 0x5800U)
-#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004U)
-#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024U)
-#define LTDC_BASE             (APB2PERIPH_BASE + 0x6800U)
-#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84U)
-#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104U) 
-
-/*!< AHB1 peripherals */
-#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000U)
-#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400U)
-#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800U)
-#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00U)
-#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000U)
-#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400U)
-#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800U)
-#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00U)
-#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000U)
-#define GPIOJ_BASE            (AHB1PERIPH_BASE + 0x2400U)
-#define GPIOK_BASE            (AHB1PERIPH_BASE + 0x2800U)
-#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)
-#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800U)
-#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00U)
-#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000U)
-#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010U)
-#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028U)
-#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040U)
-#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058U)
-#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070U)
-#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088U)
-#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0U)
-#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8U)
-#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400U)
-#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010U)
-#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028U)
-#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040U)
-#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058U)
-#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070U)
-#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088U)
-#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0U)
-#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)
-#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000U)
-#define ETH_MAC_BASE          (ETH_BASE)
-#define ETH_MMC_BASE          (ETH_BASE + 0x0100U)
-#define ETH_PTP_BASE          (ETH_BASE + 0x0700U)
-#define ETH_DMA_BASE          (ETH_BASE + 0x1000U)
-#define DMA2D_BASE            (AHB1PERIPH_BASE + 0xB000U)
-
-/*!< AHB2 peripherals */
-#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000U)
-#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800U)
-
-/*!< FMC Bankx registers base address */
-#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000U)
-#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104U)
-#define FMC_Bank2_3_R_BASE    (FMC_R_BASE + 0x0060U)
-#define FMC_Bank4_R_BASE      (FMC_R_BASE + 0x00A0U)
-#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140U)
-
-/* Debug MCU registers base address */
-#define DBGMCU_BASE           0xE0042000U
-
-/*!< USB registers base address */
-#define USB_OTG_HS_PERIPH_BASE               0x40040000U
-#define USB_OTG_FS_PERIPH_BASE               0x50000000U
-
-#define USB_OTG_GLOBAL_BASE                  0x000U
-#define USB_OTG_DEVICE_BASE                  0x800U
-#define USB_OTG_IN_ENDPOINT_BASE             0x900U
-#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U
-#define USB_OTG_EP_REG_SIZE                  0x20U
-#define USB_OTG_HOST_BASE                    0x400U
-#define USB_OTG_HOST_PORT_BASE               0x440U
-#define USB_OTG_HOST_CHANNEL_BASE            0x500U
-#define USB_OTG_HOST_CHANNEL_SIZE            0x20U
-#define USB_OTG_PCGCCTL_BASE                 0xE00U
-#define USB_OTG_FIFO_BASE                    0x1000U
-#define USB_OTG_FIFO_SIZE                    0x1000U
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
-#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
-#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define UART4               ((USART_TypeDef *) UART4_BASE)
-#define UART5               ((USART_TypeDef *) UART5_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
-#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
-#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
-#define UART7               ((USART_TypeDef *) UART7_BASE)
-#define UART8               ((USART_TypeDef *) UART8_BASE)
-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
-#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define USART6              ((USART_TypeDef *) USART6_BASE)
-#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
-#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
-#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE) 
-#define SPI4                ((SPI_TypeDef *) SPI4_BASE)
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-#define SPI5                ((SPI_TypeDef *) SPI5_BASE)
-#define SPI6                ((SPI_TypeDef *) SPI6_BASE)
-#define SAI1                ((SAI_TypeDef *) SAI1_BASE)
-#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
-#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
-#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)
-#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
-#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
-
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
-#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)
-#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
-#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
-#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
-#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
-#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
-#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
-#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
-#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
-#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
-#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
-#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
-#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
-#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
-#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
-#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
-#define ETH                 ((ETH_TypeDef *) ETH_BASE)  
-#define DMA2D               ((DMA2D_TypeDef *)DMA2D_BASE)
-#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
-#define RNG                 ((RNG_TypeDef *) RNG_BASE)
-#define FMC_Bank1           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
-#define FMC_Bank1E          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
-#define FMC_Bank2_3         ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
-#define FMC_Bank4           ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
-#define FMC_Bank5_6         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
-
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
-#define USB_OTG_HS          ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers_Bits_Definition               */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Analog to Digital Converter                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          0x00000001U        /*!<Analog watchdog flag */
-#define  ADC_SR_EOC                          0x00000002U        /*!<End of conversion */
-#define  ADC_SR_JEOC                         0x00000004U        /*!<Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        0x00000008U        /*!<Injected channel Start flag */
-#define  ADC_SR_STRT                         0x00000010U        /*!<Regular channel Start flag */
-#define  ADC_SR_OVR                          0x00000020U        /*!<Overrun flag */
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
-#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels */
-#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels */
-#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution) */
-#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
-  
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion */
-#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode */
-#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC) */
-#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection */
-#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment */
-#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      0xFFFFU            /*!<Injected data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag */
-#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion */
-#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag */
-#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag */
-#define  ADC_CSR_OVR1                        0x00000020U        /*!<ADC1 DMA overrun  flag */
-#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag */
-#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion */
-#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag */
-#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag */
-#define  ADC_CSR_OVR2                        0x00002000U        /*!<ADC2 DMA overrun  flag */
-#define  ADC_CSR_AWD3                        0x00010000U        /*!<ADC3 Analog watchdog flag */
-#define  ADC_CSR_EOC3                        0x00020000U        /*!<ADC3 End of conversion */
-#define  ADC_CSR_JEOC3                       0x00040000U        /*!<ADC3 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT3                      0x00080000U        /*!<ADC3 Injected channel Start flag */
-#define  ADC_CSR_STRT3                       0x00100000U        /*!<ADC3 Regular channel Start flag */
-#define  ADC_CSR_OVR3                        0x00200000U        /*!<ADC3 DMA overrun  flag */
-
-/* Legacy defines */
-#define  ADC_CSR_DOVR1                        ADC_CSR_OVR1
-#define  ADC_CSR_DOVR2                        ADC_CSR_OVR2
-#define  ADC_CSR_DOVR3                        ADC_CSR_OVR3
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
-#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
-#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
-#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
-#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
-
-/*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                      0x0000FFFFU         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                      0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Controller Area Network                            */
-/*                                                                            */
-/******************************************************************************/
-/*!<CAN control and status registers */
-/*******************  Bit definition for CAN_MCR register  ********************/
-#define  CAN_MCR_INRQ                        0x00000001U        /*!<Initialization Request */
-#define  CAN_MCR_SLEEP                       0x00000002U        /*!<Sleep Mode Request */
-#define  CAN_MCR_TXFP                        0x00000004U        /*!<Transmit FIFO Priority */
-#define  CAN_MCR_RFLM                        0x00000008U        /*!<Receive FIFO Locked Mode */
-#define  CAN_MCR_NART                        0x00000010U        /*!<No Automatic Retransmission */
-#define  CAN_MCR_AWUM                        0x00000020U        /*!<Automatic Wakeup Mode */
-#define  CAN_MCR_ABOM                        0x00000040U        /*!<Automatic Bus-Off Management */
-#define  CAN_MCR_TTCM                        0x00000080U        /*!<Time Triggered Communication Mode */
-#define  CAN_MCR_RESET                       0x00008000U        /*!<bxCAN software master reset */
-#define  CAN_MCR_DBF                         0x00010000U        /*!<bxCAN Debug freeze */
-/*******************  Bit definition for CAN_MSR register  ********************/
-#define  CAN_MSR_INAK                        0x0001U            /*!<Initialization Acknowledge */
-#define  CAN_MSR_SLAK                        0x0002U            /*!<Sleep Acknowledge */
-#define  CAN_MSR_ERRI                        0x0004U            /*!<Error Interrupt */
-#define  CAN_MSR_WKUI                        0x0008U            /*!<Wakeup Interrupt */
-#define  CAN_MSR_SLAKI                       0x0010U            /*!<Sleep Acknowledge Interrupt */
-#define  CAN_MSR_TXM                         0x0100U            /*!<Transmit Mode */
-#define  CAN_MSR_RXM                         0x0200U            /*!<Receive Mode */
-#define  CAN_MSR_SAMP                        0x0400U            /*!<Last Sample Point */
-#define  CAN_MSR_RX                          0x0800U            /*!<CAN Rx Signal */
-
-/*******************  Bit definition for CAN_TSR register  ********************/
-#define  CAN_TSR_RQCP0                       0x00000001U        /*!<Request Completed Mailbox0 */
-#define  CAN_TSR_TXOK0                       0x00000002U        /*!<Transmission OK of Mailbox0 */
-#define  CAN_TSR_ALST0                       0x00000004U        /*!<Arbitration Lost for Mailbox0 */
-#define  CAN_TSR_TERR0                       0x00000008U        /*!<Transmission Error of Mailbox0 */
-#define  CAN_TSR_ABRQ0                       0x00000080U        /*!<Abort Request for Mailbox0 */
-#define  CAN_TSR_RQCP1                       0x00000100U        /*!<Request Completed Mailbox1 */
-#define  CAN_TSR_TXOK1                       0x00000200U        /*!<Transmission OK of Mailbox1 */
-#define  CAN_TSR_ALST1                       0x00000400U        /*!<Arbitration Lost for Mailbox1 */
-#define  CAN_TSR_TERR1                       0x00000800U        /*!<Transmission Error of Mailbox1 */
-#define  CAN_TSR_ABRQ1                       0x00008000U        /*!<Abort Request for Mailbox 1 */
-#define  CAN_TSR_RQCP2                       0x00010000U        /*!<Request Completed Mailbox2 */
-#define  CAN_TSR_TXOK2                       0x00020000U        /*!<Transmission OK of Mailbox 2 */
-#define  CAN_TSR_ALST2                       0x00040000U        /*!<Arbitration Lost for mailbox 2 */
-#define  CAN_TSR_TERR2                       0x00080000U        /*!<Transmission Error of Mailbox 2 */
-#define  CAN_TSR_ABRQ2                       0x00800000U        /*!<Abort Request for Mailbox 2 */
-#define  CAN_TSR_CODE                        0x03000000U        /*!<Mailbox Code */
-
-#define  CAN_TSR_TME                         0x1C000000U        /*!<TME[2:0] bits */
-#define  CAN_TSR_TME0                        0x04000000U        /*!<Transmit Mailbox 0 Empty */
-#define  CAN_TSR_TME1                        0x08000000U        /*!<Transmit Mailbox 1 Empty */
-#define  CAN_TSR_TME2                        0x10000000U        /*!<Transmit Mailbox 2 Empty */
-
-#define  CAN_TSR_LOW                         0xE0000000U        /*!<LOW[2:0] bits */
-#define  CAN_TSR_LOW0                        0x20000000U        /*!<Lowest Priority Flag for Mailbox 0 */
-#define  CAN_TSR_LOW1                        0x40000000U        /*!<Lowest Priority Flag for Mailbox 1 */
-#define  CAN_TSR_LOW2                        0x80000000U        /*!<Lowest Priority Flag for Mailbox 2 */
-
-/*******************  Bit definition for CAN_RF0R register  *******************/
-#define  CAN_RF0R_FMP0                       0x03U               /*!<FIFO 0 Message Pending */
-#define  CAN_RF0R_FULL0                      0x08U               /*!<FIFO 0 Full */
-#define  CAN_RF0R_FOVR0                      0x10U               /*!<FIFO 0 Overrun */
-#define  CAN_RF0R_RFOM0                      0x20U               /*!<Release FIFO 0 Output Mailbox */
-
-/*******************  Bit definition for CAN_RF1R register  *******************/
-#define  CAN_RF1R_FMP1                       0x03U               /*!<FIFO 1 Message Pending */
-#define  CAN_RF1R_FULL1                      0x08U               /*!<FIFO 1 Full */
-#define  CAN_RF1R_FOVR1                      0x10U               /*!<FIFO 1 Overrun */
-#define  CAN_RF1R_RFOM1                      0x20U               /*!<Release FIFO 1 Output Mailbox */
-
-/********************  Bit definition for CAN_IER register  *******************/
-#define  CAN_IER_TMEIE                       0x00000001U        /*!<Transmit Mailbox Empty Interrupt Enable */
-#define  CAN_IER_FMPIE0                      0x00000002U        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE0                       0x00000004U        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE0                      0x00000008U        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_FMPIE1                      0x00000010U        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE1                       0x00000020U        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE1                      0x00000040U        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error Warning Interrupt Enable */
-#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error Passive Interrupt Enable */
-#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-Off Interrupt Enable */
-#define  CAN_IER_LECIE                       0x00000800U        /*!<Last Error Code Interrupt Enable */
-#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error Interrupt Enable */
-#define  CAN_IER_WKUIE                       0x00010000U        /*!<Wakeup Interrupt Enable */
-#define  CAN_IER_SLKIE                       0x00020000U        /*!<Sleep Interrupt Enable */
-#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error warning interrupt enable */
-#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error passive interrupt enable */
-#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-off interrupt enable */
-#define  CAN_IER_LECIE                       0x00000800U        /*!<Last error code interrupt enable */
-#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error interrupt enable */
-
-
-/********************  Bit definition for CAN_ESR register  *******************/
-#define  CAN_ESR_EWGF                        0x00000001U        /*!<Error Warning Flag */
-#define  CAN_ESR_EPVF                        0x00000002U        /*!<Error Passive Flag */
-#define  CAN_ESR_BOFF                        0x00000004U        /*!<Bus-Off Flag */
-
-#define  CAN_ESR_LEC                         0x00000070U        /*!<LEC[2:0] bits (Last Error Code) */
-#define  CAN_ESR_LEC_0                       0x00000010U        /*!<Bit 0 */
-#define  CAN_ESR_LEC_1                       0x00000020U        /*!<Bit 1 */
-#define  CAN_ESR_LEC_2                       0x00000040U        /*!<Bit 2 */
-
-#define  CAN_ESR_TEC                         0x00FF0000U        /*!<Least significant byte of the 9-bit Transmit Error Counter */
-#define  CAN_ESR_REC                         0xFF000000U        /*!<Receive Error Counter */
-
-/*******************  Bit definition for CAN_BTR register  ********************/
-#define  CAN_BTR_BRP                         0x000003FFU        /*!<Baud Rate Prescaler */
-#define  CAN_BTR_TS1                         0x000F0000U        /*!<Time Segment 1 */
-#define  CAN_BTR_TS1_0                       0x00010000U        /*!<Bit 0 */
-#define  CAN_BTR_TS1_1                       0x00020000U        /*!<Bit 1 */
-#define  CAN_BTR_TS1_2                       0x00040000U        /*!<Bit 2 */
-#define  CAN_BTR_TS1_3                       0x00080000U        /*!<Bit 3 */
-#define  CAN_BTR_TS2                         0x00700000U        /*!<Time Segment 2 */
-#define  CAN_BTR_TS2_0                       0x00100000U        /*!<Bit 0 */
-#define  CAN_BTR_TS2_1                       0x00200000U        /*!<Bit 1 */
-#define  CAN_BTR_TS2_2                       0x00400000U        /*!<Bit 2 */
-#define  CAN_BTR_SJW                         0x03000000U        /*!<Resynchronization Jump Width */
-#define  CAN_BTR_SJW_0                       0x01000000U        /*!<Bit 0 */
-#define  CAN_BTR_SJW_1                       0x02000000U        /*!<Bit 1 */
-#define  CAN_BTR_LBKM                        0x40000000U        /*!<Loop Back Mode (Debug) */
-#define  CAN_BTR_SILM                        0x80000000U        /*!<Silent Mode */
-
-
-/*!<Mailbox registers */
-/******************  Bit definition for CAN_TI0R register  ********************/
-#define  CAN_TI0R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI0R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_TI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/******************  Bit definition for CAN_TDT0R register  *******************/
-#define  CAN_TDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT0R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/******************  Bit definition for CAN_TDL0R register  *******************/
-#define  CAN_TDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/******************  Bit definition for CAN_TDH0R register  *******************/
-#define  CAN_TDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI1R register  *******************/
-#define  CAN_TI1R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI1R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI1R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_TI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT1R register  ******************/
-#define  CAN_TDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT1R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL1R register  ******************/
-#define  CAN_TDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH1R register  ******************/
-#define  CAN_TDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI2R register  *******************/
-#define  CAN_TI2R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI2R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI2R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI2R_EXID                       0x001FFFF8U        /*!<Extended identifier */
-#define  CAN_TI2R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT2R register  ******************/  
-#define  CAN_TDT2R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT2R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT2R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL2R register  ******************/
-#define  CAN_TDL2R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL2R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL2R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL2R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH2R register  ******************/
-#define  CAN_TDH2R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH2R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH2R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH2R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI0R register  *******************/
-#define  CAN_RI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_RI0R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_RI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_RI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT0R register  ******************/
-#define  CAN_RDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_RDT0R_FMI                       0x0000FF00U        /*!<Filter Match Index */
-#define  CAN_RDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL0R register  ******************/
-#define  CAN_RDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_RDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_RDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_RDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH0R register  ******************/
-#define  CAN_RDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_RDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_RDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_RDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI1R register  *******************/
-#define  CAN_RI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_RI1R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_RI1R_EXID                       0x001FFFF8U        /*!<Extended identifier */
-#define  CAN_RI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT1R register  ******************/
-#define  CAN_RDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_RDT1R_FMI                       0x0000FF00U        /*!<Filter Match Index */
-#define  CAN_RDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL1R register  ******************/
-#define  CAN_RDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_RDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_RDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_RDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH1R register  ******************/
-#define  CAN_RDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_RDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_RDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_RDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*!<CAN filter registers */
-/*******************  Bit definition for CAN_FMR register  ********************/
-#define  CAN_FMR_FINIT                       0x01U               /*!<Filter Init Mode */
-#define  CAN_FMR_CAN2SB                      0x00003F00U        /*!<CAN2 start bank */
-
-/*******************  Bit definition for CAN_FM1R register  *******************/
-#define  CAN_FM1R_FBM                        0x0FFFFFFFU        /*!<Filter Mode */
-#define  CAN_FM1R_FBM0                       0x00000001U        /*!<Filter Init Mode bit 0 */
-#define  CAN_FM1R_FBM1                       0x00000002U        /*!<Filter Init Mode bit 1 */
-#define  CAN_FM1R_FBM2                       0x00000004U        /*!<Filter Init Mode bit 2 */
-#define  CAN_FM1R_FBM3                       0x00000008U        /*!<Filter Init Mode bit 3 */
-#define  CAN_FM1R_FBM4                       0x00000010U        /*!<Filter Init Mode bit 4 */
-#define  CAN_FM1R_FBM5                       0x00000020U        /*!<Filter Init Mode bit 5 */
-#define  CAN_FM1R_FBM6                       0x00000040U        /*!<Filter Init Mode bit 6 */
-#define  CAN_FM1R_FBM7                       0x00000080U        /*!<Filter Init Mode bit 7 */
-#define  CAN_FM1R_FBM8                       0x00000100U        /*!<Filter Init Mode bit 8 */
-#define  CAN_FM1R_FBM9                       0x00000200U        /*!<Filter Init Mode bit 9 */
-#define  CAN_FM1R_FBM10                      0x00000400U        /*!<Filter Init Mode bit 10 */
-#define  CAN_FM1R_FBM11                      0x00000800U        /*!<Filter Init Mode bit 11 */
-#define  CAN_FM1R_FBM12                      0x00001000U        /*!<Filter Init Mode bit 12 */
-#define  CAN_FM1R_FBM13                      0x00002000U        /*!<Filter Init Mode bit 13 */
-#define  CAN_FM1R_FBM14                      0x00004000U        /*!<Filter Init Mode bit 14 */
-#define  CAN_FM1R_FBM15                      0x00008000U        /*!<Filter Init Mode bit 15 */
-#define  CAN_FM1R_FBM16                      0x00010000U        /*!<Filter Init Mode bit 16 */
-#define  CAN_FM1R_FBM17                      0x00020000U        /*!<Filter Init Mode bit 17 */
-#define  CAN_FM1R_FBM18                      0x00040000U        /*!<Filter Init Mode bit 18 */
-#define  CAN_FM1R_FBM19                      0x00080000U        /*!<Filter Init Mode bit 19 */
-#define  CAN_FM1R_FBM20                      0x00100000U        /*!<Filter Init Mode bit 20 */
-#define  CAN_FM1R_FBM21                      0x00200000U        /*!<Filter Init Mode bit 21 */
-#define  CAN_FM1R_FBM22                      0x00400000U        /*!<Filter Init Mode bit 22 */
-#define  CAN_FM1R_FBM23                      0x00800000U        /*!<Filter Init Mode bit 23 */
-#define  CAN_FM1R_FBM24                      0x01000000U        /*!<Filter Init Mode bit 24 */
-#define  CAN_FM1R_FBM25                      0x02000000U        /*!<Filter Init Mode bit 25 */
-#define  CAN_FM1R_FBM26                      0x04000000U        /*!<Filter Init Mode bit 26 */
-#define  CAN_FM1R_FBM27                      0x08000000U        /*!<Filter Init Mode bit 27 */
-
-/*******************  Bit definition for CAN_FS1R register  *******************/
-#define  CAN_FS1R_FSC                        0x0FFFFFFFU        /*!<Filter Scale Configuration */
-#define  CAN_FS1R_FSC0                       0x00000001U        /*!<Filter Scale Configuration bit 0 */
-#define  CAN_FS1R_FSC1                       0x00000002U        /*!<Filter Scale Configuration bit 1 */
-#define  CAN_FS1R_FSC2                       0x00000004U        /*!<Filter Scale Configuration bit 2 */
-#define  CAN_FS1R_FSC3                       0x00000008U        /*!<Filter Scale Configuration bit 3 */
-#define  CAN_FS1R_FSC4                       0x00000010U        /*!<Filter Scale Configuration bit 4 */
-#define  CAN_FS1R_FSC5                       0x00000020U        /*!<Filter Scale Configuration bit 5 */
-#define  CAN_FS1R_FSC6                       0x00000040U        /*!<Filter Scale Configuration bit 6 */
-#define  CAN_FS1R_FSC7                       0x00000080U        /*!<Filter Scale Configuration bit 7 */
-#define  CAN_FS1R_FSC8                       0x00000100U        /*!<Filter Scale Configuration bit 8 */
-#define  CAN_FS1R_FSC9                       0x00000200U        /*!<Filter Scale Configuration bit 9 */
-#define  CAN_FS1R_FSC10                      0x00000400U        /*!<Filter Scale Configuration bit 10 */
-#define  CAN_FS1R_FSC11                      0x00000800U        /*!<Filter Scale Configuration bit 11 */
-#define  CAN_FS1R_FSC12                      0x00001000U        /*!<Filter Scale Configuration bit 12 */
-#define  CAN_FS1R_FSC13                      0x00002000U        /*!<Filter Scale Configuration bit 13 */
-#define  CAN_FS1R_FSC14                      0x00004000U        /*!<Filter Scale Configuration bit 14 */
-#define  CAN_FS1R_FSC15                      0x00008000U        /*!<Filter Scale Configuration bit 15 */
-#define  CAN_FS1R_FSC16                      0x00010000U        /*!<Filter Scale Configuration bit 16 */
-#define  CAN_FS1R_FSC17                      0x00020000U        /*!<Filter Scale Configuration bit 17 */
-#define  CAN_FS1R_FSC18                      0x00040000U        /*!<Filter Scale Configuration bit 18 */
-#define  CAN_FS1R_FSC19                      0x00080000U        /*!<Filter Scale Configuration bit 19 */
-#define  CAN_FS1R_FSC20                      0x00100000U        /*!<Filter Scale Configuration bit 20 */
-#define  CAN_FS1R_FSC21                      0x00200000U        /*!<Filter Scale Configuration bit 21 */
-#define  CAN_FS1R_FSC22                      0x00400000U        /*!<Filter Scale Configuration bit 22 */
-#define  CAN_FS1R_FSC23                      0x00800000U        /*!<Filter Scale Configuration bit 23 */
-#define  CAN_FS1R_FSC24                      0x01000000U        /*!<Filter Scale Configuration bit 24 */
-#define  CAN_FS1R_FSC25                      0x02000000U        /*!<Filter Scale Configuration bit 25 */
-#define  CAN_FS1R_FSC26                      0x04000000U        /*!<Filter Scale Configuration bit 26 */
-#define  CAN_FS1R_FSC27                      0x08000000U        /*!<Filter Scale Configuration bit 27 */
-
-/******************  Bit definition for CAN_FFA1R register  *******************/
-#define  CAN_FFA1R_FFA                        0x0FFFFFFFU        /*!<Filter FIFO Assignment */
-#define  CAN_FFA1R_FFA0                       0x00000001U        /*!<Filter FIFO Assignment bit 0 */
-#define  CAN_FFA1R_FFA1                       0x00000002U        /*!<Filter FIFO Assignment bit 1 */
-#define  CAN_FFA1R_FFA2                       0x00000004U        /*!<Filter FIFO Assignment bit 2 */
-#define  CAN_FFA1R_FFA3                       0x00000008U        /*!<Filter FIFO Assignment bit 3 */
-#define  CAN_FFA1R_FFA4                       0x00000010U        /*!<Filter FIFO Assignment bit 4 */
-#define  CAN_FFA1R_FFA5                       0x00000020U        /*!<Filter FIFO Assignment bit 5 */
-#define  CAN_FFA1R_FFA6                       0x00000040U        /*!<Filter FIFO Assignment bit 6 */
-#define  CAN_FFA1R_FFA7                       0x00000080U        /*!<Filter FIFO Assignment bit 7 */
-#define  CAN_FFA1R_FFA8                       0x00000100U        /*!<Filter FIFO Assignment bit 8 */
-#define  CAN_FFA1R_FFA9                       0x00000200U        /*!<Filter FIFO Assignment bit 9 */
-#define  CAN_FFA1R_FFA10                      0x00000400U        /*!<Filter FIFO Assignment bit 10 */
-#define  CAN_FFA1R_FFA11                      0x00000800U        /*!<Filter FIFO Assignment bit 11 */
-#define  CAN_FFA1R_FFA12                      0x00001000U        /*!<Filter FIFO Assignment bit 12 */
-#define  CAN_FFA1R_FFA13                      0x00002000U        /*!<Filter FIFO Assignment bit 13 */
-#define  CAN_FFA1R_FFA14                      0x00004000U        /*!<Filter FIFO Assignment bit 14 */
-#define  CAN_FFA1R_FFA15                      0x00008000U        /*!<Filter FIFO Assignment bit 15 */
-#define  CAN_FFA1R_FFA16                      0x00010000U        /*!<Filter FIFO Assignment bit 16 */
-#define  CAN_FFA1R_FFA17                      0x00020000U        /*!<Filter FIFO Assignment bit 17 */
-#define  CAN_FFA1R_FFA18                      0x00040000U        /*!<Filter FIFO Assignment bit 18 */
-#define  CAN_FFA1R_FFA19                      0x00080000U        /*!<Filter FIFO Assignment bit 19 */
-#define  CAN_FFA1R_FFA20                      0x00100000U        /*!<Filter FIFO Assignment bit 20 */
-#define  CAN_FFA1R_FFA21                      0x00200000U        /*!<Filter FIFO Assignment bit 21 */
-#define  CAN_FFA1R_FFA22                      0x00400000U        /*!<Filter FIFO Assignment bit 22 */
-#define  CAN_FFA1R_FFA23                      0x00800000U        /*!<Filter FIFO Assignment bit 23 */
-#define  CAN_FFA1R_FFA24                      0x01000000U        /*!<Filter FIFO Assignment bit 24 */
-#define  CAN_FFA1R_FFA25                      0x02000000U        /*!<Filter FIFO Assignment bit 25 */
-#define  CAN_FFA1R_FFA26                      0x04000000U        /*!<Filter FIFO Assignment bit 26 */
-#define  CAN_FFA1R_FFA27                      0x08000000U        /*!<Filter FIFO Assignment bit 27 */
-
-/*******************  Bit definition for CAN_FA1R register  *******************/
-#define  CAN_FA1R_FACT                        0x0FFFFFFFU        /*!<Filter Active */
-#define  CAN_FA1R_FACT0                       0x00000001U        /*!<Filter Active bit 0 */
-#define  CAN_FA1R_FACT1                       0x00000002U        /*!<Filter Active bit 1 */
-#define  CAN_FA1R_FACT2                       0x00000004U        /*!<Filter Active bit 2 */
-#define  CAN_FA1R_FACT3                       0x00000008U        /*!<Filter Active bit 3 */
-#define  CAN_FA1R_FACT4                       0x00000010U        /*!<Filter Active bit 4 */
-#define  CAN_FA1R_FACT5                       0x00000020U        /*!<Filter Active bit 5 */
-#define  CAN_FA1R_FACT6                       0x00000040U        /*!<Filter Active bit 6 */
-#define  CAN_FA1R_FACT7                       0x00000080U        /*!<Filter Active bit 7 */
-#define  CAN_FA1R_FACT8                       0x00000100U        /*!<Filter Active bit 8 */
-#define  CAN_FA1R_FACT9                       0x00000200U        /*!<Filter Active bit 9 */
-#define  CAN_FA1R_FACT10                      0x00000400U        /*!<Filter Active bit 10 */
-#define  CAN_FA1R_FACT11                      0x00000800U        /*!<Filter Active bit 11 */
-#define  CAN_FA1R_FACT12                      0x00001000U        /*!<Filter Active bit 12 */
-#define  CAN_FA1R_FACT13                      0x00002000U        /*!<Filter Active bit 13 */
-#define  CAN_FA1R_FACT14                      0x00004000U        /*!<Filter Active bit 14 */
-#define  CAN_FA1R_FACT15                      0x00008000U        /*!<Filter Active bit 15 */
-#define  CAN_FA1R_FACT16                      0x00010000U        /*!<Filter Active bit 16 */
-#define  CAN_FA1R_FACT17                      0x00020000U        /*!<Filter Active bit 17 */
-#define  CAN_FA1R_FACT18                      0x00040000U        /*!<Filter Active bit 18 */
-#define  CAN_FA1R_FACT19                      0x00080000U        /*!<Filter Active bit 19 */
-#define  CAN_FA1R_FACT20                      0x00100000U        /*!<Filter Active bit 20 */
-#define  CAN_FA1R_FACT21                      0x00200000U        /*!<Filter Active bit 21 */
-#define  CAN_FA1R_FACT22                      0x00400000U        /*!<Filter Active bit 22 */
-#define  CAN_FA1R_FACT23                      0x00800000U        /*!<Filter Active bit 23 */
-#define  CAN_FA1R_FACT24                      0x01000000U        /*!<Filter Active bit 24 */
-#define  CAN_FA1R_FACT25                      0x02000000U        /*!<Filter Active bit 25 */
-#define  CAN_FA1R_FACT26                      0x04000000U        /*!<Filter Active bit 26 */
-#define  CAN_FA1R_FACT27                      0x08000000U        /*!<Filter Active bit 27 */
-
-/*******************  Bit definition for CAN_F0R1 register  *******************/
-#define  CAN_F0R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F0R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F0R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F0R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F0R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F0R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F0R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F0R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F0R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F0R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F0R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F0R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F0R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F0R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F0R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F0R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F0R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F0R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F0R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F0R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F0R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F0R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F0R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F0R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F0R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F0R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F0R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F0R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F0R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F0R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F0R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F0R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R1 register  *******************/
-#define  CAN_F1R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F1R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F1R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F1R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F1R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F1R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F1R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F1R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F1R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F1R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F1R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F1R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F1R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F1R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F1R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F1R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F1R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F1R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F1R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F1R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F1R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F1R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F1R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F1R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F1R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F1R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F1R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F1R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F1R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F1R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F1R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F1R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R1 register  *******************/
-#define  CAN_F2R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F2R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F2R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F2R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F2R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F2R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F2R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F2R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F2R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F2R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F2R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F2R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F2R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F2R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F2R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F2R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F2R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F2R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F2R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F2R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F2R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F2R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F2R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F2R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F2R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F2R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F2R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F2R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F2R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F2R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F2R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F2R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R1 register  *******************/
-#define  CAN_F3R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F3R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F3R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F3R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F3R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F3R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F3R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F3R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F3R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F3R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F3R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F3R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F3R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F3R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F3R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F3R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F3R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F3R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F3R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F3R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F3R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F3R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F3R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F3R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F3R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F3R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F3R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F3R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F3R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F3R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F3R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F3R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R1 register  *******************/
-#define  CAN_F4R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F4R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F4R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F4R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F4R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F4R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F4R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F4R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F4R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F4R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F4R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F4R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F4R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F4R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F4R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F4R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F4R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F4R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F4R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F4R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F4R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F4R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F4R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F4R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F4R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F4R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F4R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F4R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F4R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F4R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F4R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F4R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R1 register  *******************/
-#define  CAN_F5R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F5R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F5R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F5R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F5R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F5R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F5R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F5R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F5R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F5R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F5R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F5R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F5R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F5R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F5R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F5R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F5R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F5R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F5R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F5R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F5R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F5R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F5R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F5R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F5R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F5R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F5R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F5R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F5R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F5R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F5R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F5R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R1 register  *******************/
-#define  CAN_F6R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F6R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F6R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F6R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F6R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F6R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F6R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F6R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F6R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F6R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F6R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F6R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F6R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F6R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F6R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F6R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F6R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F6R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F6R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F6R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F6R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F6R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F6R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F6R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F6R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F6R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F6R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F6R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F6R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F6R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F6R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F6R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R1 register  *******************/
-#define  CAN_F7R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F7R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F7R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F7R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F7R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F7R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F7R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F7R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F7R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F7R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F7R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F7R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F7R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F7R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F7R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F7R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F7R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F7R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F7R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F7R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F7R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F7R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F7R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F7R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F7R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F7R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F7R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F7R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F7R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F7R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F7R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F7R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R1 register  *******************/
-#define  CAN_F8R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F8R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F8R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F8R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F8R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F8R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F8R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F8R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F8R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F8R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F8R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F8R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F8R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F8R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F8R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F8R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F8R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F8R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F8R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F8R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F8R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F8R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F8R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F8R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F8R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F8R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F8R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F8R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F8R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F8R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F8R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F8R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R1 register  *******************/
-#define  CAN_F9R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F9R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F9R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F9R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F9R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F9R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F9R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F9R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F9R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F9R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F9R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F9R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F9R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F9R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F9R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F9R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F9R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F9R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F9R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F9R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F9R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F9R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F9R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F9R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F9R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F9R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F9R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F9R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F9R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F9R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F9R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F9R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R1 register  ******************/
-#define  CAN_F10R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F10R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F10R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F10R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F10R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F10R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F10R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F10R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F10R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F10R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F10R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F10R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F10R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F10R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F10R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F10R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F10R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F10R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F10R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F10R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F10R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F10R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F10R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F10R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F10R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F10R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F10R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F10R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F10R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F10R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F10R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F10R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R1 register  ******************/
-#define  CAN_F11R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F11R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F11R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F11R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F11R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F11R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F11R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F11R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F11R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F11R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F11R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F11R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F11R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F11R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F11R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F11R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F11R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F11R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F11R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F11R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F11R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F11R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F11R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F11R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F11R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F11R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F11R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F11R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F11R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F11R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F11R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F11R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R1 register  ******************/
-#define  CAN_F12R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F12R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F12R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F12R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F12R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F12R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F12R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F12R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F12R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F12R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F12R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F12R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F12R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F12R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F12R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F12R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F12R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F12R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F12R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F12R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F12R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F12R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F12R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F12R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F12R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F12R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F12R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F12R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F12R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F12R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F12R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F12R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R1 register  ******************/
-#define  CAN_F13R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F13R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F13R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F13R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F13R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F13R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F13R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F13R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F13R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F13R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F13R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F13R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F13R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F13R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F13R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F13R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F13R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F13R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F13R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F13R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F13R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F13R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F13R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F13R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F13R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F13R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F13R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F13R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F13R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F13R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F13R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F13R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F0R2 register  *******************/
-#define  CAN_F0R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F0R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F0R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F0R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F0R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F0R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F0R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F0R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F0R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F0R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F0R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F0R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F0R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F0R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F0R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F0R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F0R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F0R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F0R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F0R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F0R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F0R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F0R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F0R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F0R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F0R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F0R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F0R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F0R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F0R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F0R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F0R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R2 register  *******************/
-#define  CAN_F1R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F1R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F1R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F1R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F1R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F1R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F1R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F1R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F1R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F1R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F1R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F1R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F1R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F1R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F1R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F1R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F1R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F1R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F1R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F1R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F1R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F1R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F1R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F1R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F1R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F1R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F1R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F1R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F1R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F1R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F1R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F1R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R2 register  *******************/
-#define  CAN_F2R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F2R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F2R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F2R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F2R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F2R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F2R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F2R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F2R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F2R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F2R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F2R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F2R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F2R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F2R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F2R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F2R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F2R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F2R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F2R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F2R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F2R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F2R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F2R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F2R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F2R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F2R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F2R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F2R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F2R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F2R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F2R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R2 register  *******************/
-#define  CAN_F3R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F3R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F3R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F3R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F3R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F3R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F3R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F3R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F3R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F3R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F3R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F3R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F3R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F3R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F3R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F3R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F3R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F3R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F3R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F3R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F3R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F3R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F3R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F3R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F3R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F3R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F3R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F3R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F3R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F3R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F3R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F3R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R2 register  *******************/
-#define  CAN_F4R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F4R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F4R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F4R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F4R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F4R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F4R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F4R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F4R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F4R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F4R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F4R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F4R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F4R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F4R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F4R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F4R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F4R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F4R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F4R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F4R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F4R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F4R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F4R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F4R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F4R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F4R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F4R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F4R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F4R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F4R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F4R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R2 register  *******************/
-#define  CAN_F5R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F5R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F5R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F5R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F5R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F5R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F5R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F5R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F5R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F5R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F5R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F5R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F5R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F5R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F5R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F5R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F5R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F5R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F5R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F5R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F5R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F5R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F5R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F5R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F5R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F5R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F5R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F5R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F5R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F5R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F5R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F5R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R2 register  *******************/
-#define  CAN_F6R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F6R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F6R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F6R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F6R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F6R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F6R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F6R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F6R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F6R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F6R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F6R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F6R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F6R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F6R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F6R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F6R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F6R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F6R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F6R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F6R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F6R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F6R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F6R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F6R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F6R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F6R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F6R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F6R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F6R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F6R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F6R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R2 register  *******************/
-#define  CAN_F7R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F7R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F7R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F7R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F7R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F7R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F7R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F7R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F7R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F7R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F7R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F7R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F7R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F7R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F7R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F7R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F7R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F7R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F7R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F7R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F7R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F7R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F7R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F7R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F7R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F7R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F7R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F7R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F7R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F7R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F7R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F7R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R2 register  *******************/
-#define  CAN_F8R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F8R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F8R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F8R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F8R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F8R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F8R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F8R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F8R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F8R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F8R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F8R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F8R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F8R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F8R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F8R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F8R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F8R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F8R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F8R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F8R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F8R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F8R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F8R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F8R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F8R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F8R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F8R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F8R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F8R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F8R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F8R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R2 register  *******************/
-#define  CAN_F9R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F9R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F9R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F9R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F9R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F9R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F9R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F9R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F9R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F9R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F9R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F9R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F9R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F9R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F9R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F9R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F9R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F9R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F9R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F9R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F9R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F9R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F9R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F9R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F9R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F9R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F9R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F9R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F9R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F9R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F9R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F9R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R2 register  ******************/
-#define  CAN_F10R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F10R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F10R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F10R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F10R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F10R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F10R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F10R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F10R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F10R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F10R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F10R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F10R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F10R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F10R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F10R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F10R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F10R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F10R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F10R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F10R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F10R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F10R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F10R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F10R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F10R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F10R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F10R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F10R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F10R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F10R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F10R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R2 register  ******************/
-#define  CAN_F11R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F11R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F11R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F11R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F11R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F11R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F11R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F11R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F11R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F11R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F11R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F11R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F11R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F11R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F11R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F11R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F11R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F11R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F11R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F11R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F11R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F11R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F11R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F11R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F11R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F11R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F11R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F11R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F11R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F11R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F11R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F11R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R2 register  ******************/
-#define  CAN_F12R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F12R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F12R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F12R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F12R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F12R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F12R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F12R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F12R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F12R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F12R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F12R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F12R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F12R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F12R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F12R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F12R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F12R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F12R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F12R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F12R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F12R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F12R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F12R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F12R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F12R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F12R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F12R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F12R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F12R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F12R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F12R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R2 register  ******************/
-#define  CAN_F13R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F13R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F13R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F13R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F13R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F13R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F13R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F13R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F13R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F13R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F13R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F13R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F13R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F13R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F13R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F13R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F13R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F13R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F13R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F13R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F13R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F13R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F13R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F13R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F13R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F13R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F13R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F13R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F13R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F13R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F13R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F13R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRC calculation unit                              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           0xFFFFFFFFU /*!< Data register bits */
-
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         0xFFU        /*!< General-purpose 8-bit data register bits */
-
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        0x01U        /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Digital to Analog Converter                           */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DAC_CR register  ********************/
-#define  DAC_CR_EN1                          0x00000001U        /*!<DAC channel1 enable */
-#define  DAC_CR_BOFF1                        0x00000002U        /*!<DAC channel1 output buffer disable */
-#define  DAC_CR_TEN1                         0x00000004U        /*!<DAC channel1 Trigger enable */
-
-#define  DAC_CR_TSEL1                        0x00000038U        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define  DAC_CR_TSEL1_0                      0x00000008U        /*!<Bit 0 */
-#define  DAC_CR_TSEL1_1                      0x00000010U        /*!<Bit 1 */
-#define  DAC_CR_TSEL1_2                      0x00000020U        /*!<Bit 2 */
-
-#define  DAC_CR_WAVE1                        0x000000C0U        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE1_0                      0x00000040U        /*!<Bit 0 */
-#define  DAC_CR_WAVE1_1                      0x00000080U        /*!<Bit 1 */
-
-#define  DAC_CR_MAMP1                        0x00000F00U        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP1_0                      0x00000100U        /*!<Bit 0 */
-#define  DAC_CR_MAMP1_1                      0x00000200U        /*!<Bit 1 */
-#define  DAC_CR_MAMP1_2                      0x00000400U        /*!<Bit 2 */
-#define  DAC_CR_MAMP1_3                      0x00000800U        /*!<Bit 3 */
-
-#define  DAC_CR_DMAEN1                       0x00001000U        /*!<DAC channel1 DMA enable */
-#define  DAC_CR_DMAUDRIE1                    0x00002000U        /*!<DAC channel1 DMA underrun interrupt enable*/
-#define  DAC_CR_EN2                          0x00010000U        /*!<DAC channel2 enable */
-#define  DAC_CR_BOFF2                        0x00020000U        /*!<DAC channel2 output buffer disable */
-#define  DAC_CR_TEN2                         0x00040000U        /*!<DAC channel2 Trigger enable */
-
-#define  DAC_CR_TSEL2                        0x00380000U        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define  DAC_CR_TSEL2_0                      0x00080000U        /*!<Bit 0 */
-#define  DAC_CR_TSEL2_1                      0x00100000U        /*!<Bit 1 */
-#define  DAC_CR_TSEL2_2                      0x00200000U        /*!<Bit 2 */
-
-#define  DAC_CR_WAVE2                        0x00C00000U        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE2_0                      0x00400000U        /*!<Bit 0 */
-#define  DAC_CR_WAVE2_1                      0x00800000U        /*!<Bit 1 */
-
-#define  DAC_CR_MAMP2                        0x0F000000U        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP2_0                      0x01000000U        /*!<Bit 0 */
-#define  DAC_CR_MAMP2_1                      0x02000000U        /*!<Bit 1 */
-#define  DAC_CR_MAMP2_2                      0x04000000U        /*!<Bit 2 */
-#define  DAC_CR_MAMP2_3                      0x08000000U        /*!<Bit 3 */
-
-#define  DAC_CR_DMAEN2                       0x10000000U        /*!<DAC channel2 DMA enabled */
-#define  DAC_CR_DMAUDRIE2                    0x20000000U        /*!<DAC channel2 DMA underrun interrupt enable*/
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define  DAC_SWTRIGR_SWTRIG1                 0x01U               /*!<DAC channel1 software trigger */
-#define  DAC_SWTRIGR_SWTRIG2                 0x02U               /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define  DAC_DHR12R1_DACC1DHR                0x0FFFU            /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define  DAC_DHR12L1_DACC1DHR                0xFFF0U            /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define  DAC_DHR8R1_DACC1DHR                 0xFFU               /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define  DAC_DHR12R2_DACC2DHR                0x0FFFU            /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define  DAC_DHR12L2_DACC2DHR                0xFFF0U            /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define  DAC_DHR8R2_DACC2DHR                 0xFFU               /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define  DAC_DHR12RD_DACC1DHR                0x00000FFFU        /*!<DAC channel1 12-bit Right aligned data */
-#define  DAC_DHR12RD_DACC2DHR                0x0FFF0000U        /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define  DAC_DHR12LD_DACC1DHR                0x0000FFF0U        /*!<DAC channel1 12-bit Left aligned data */
-#define  DAC_DHR12LD_DACC2DHR                0xFFF00000U        /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define  DAC_DHR8RD_DACC1DHR                 0x00FFU            /*!<DAC channel1 8-bit Right aligned data */
-#define  DAC_DHR8RD_DACC2DHR                 0xFF00U            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define  DAC_DOR1_DACC1DOR                   0x0FFFU            /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define  DAC_DOR2_DACC2DOR                   0x0FFFU            /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define  DAC_SR_DMAUDR1                      0x00002000U        /*!<DAC channel1 DMA underrun flag */
-#define  DAC_SR_DMAUDR2                      0x20000000U        /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 Debug MCU                                  */
-/*                                                                            */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    DCMI                                    */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DCMI_CR register  ******************/
-#define DCMI_CR_CAPTURE                      0x00000001U
-#define DCMI_CR_CM                           0x00000002U
-#define DCMI_CR_CROP                         0x00000004U
-#define DCMI_CR_JPEG                         0x00000008U
-#define DCMI_CR_ESS                          0x00000010U
-#define DCMI_CR_PCKPOL                       0x00000020U
-#define DCMI_CR_HSPOL                        0x00000040U
-#define DCMI_CR_VSPOL                        0x00000080U
-#define DCMI_CR_FCRC_0                       0x00000100U
-#define DCMI_CR_FCRC_1                       0x00000200U
-#define DCMI_CR_EDM_0                        0x00000400U
-#define DCMI_CR_EDM_1                        0x00000800U
-#define DCMI_CR_CRE                          0x00001000U
-#define DCMI_CR_ENABLE                       0x00004000U
-
-/********************  Bits definition for DCMI_SR register  ******************/
-#define DCMI_SR_HSYNC                        0x00000001U
-#define DCMI_SR_VSYNC                        0x00000002U
-#define DCMI_SR_FNE                          0x00000004U
-
-/********************  Bits definition for DCMI_RIS register  *****************/
-#define DCMI_RIS_FRAME_RIS                   0x00000001U
-#define DCMI_RIS_OVR_RIS                     0x00000002U
-#define DCMI_RIS_ERR_RIS                     0x00000004U
-#define DCMI_RIS_VSYNC_RIS                   0x00000008U
-#define DCMI_RIS_LINE_RIS                    0x00000010U
-/* Legacy defines */
-#define DCMI_RISR_FRAME_RIS                  DCMI_RIS_FRAME_RIS
-#define DCMI_RISR_OVR_RIS                    DCMI_RIS_OVR_RIS
-#define DCMI_RISR_ERR_RIS                    DCMI_RIS_ERR_RIS
-#define DCMI_RISR_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS
-#define DCMI_RISR_LINE_RIS                   DCMI_RIS_LINE_RIS
-#define DCMI_RISR_OVF_RIS                    DCMI_RIS_OVR_RIS
-
-/********************  Bits definition for DCMI_IER register  *****************/
-#define DCMI_IER_FRAME_IE                    0x00000001U
-#define DCMI_IER_OVR_IE                      0x00000002U
-#define DCMI_IER_ERR_IE                      0x00000004U
-#define DCMI_IER_VSYNC_IE                    0x00000008U
-#define DCMI_IER_LINE_IE                     0x00000010U
-/* Legacy defines */
-#define DCMI_IER_OVF_IE                      DCMI_IER_OVR_IE
-
-/********************  Bits definition for DCMI_MIS register  *****************/
-#define DCMI_MIS_FRAME_MIS                   0x00000001U
-#define DCMI_MIS_OVR_MIS                     0x00000002U
-#define DCMI_MIS_ERR_MIS                     0x00000004U
-#define DCMI_MIS_VSYNC_MIS                   0x00000008U
-#define DCMI_MIS_LINE_MIS                    0x00000010U
-
-/* Legacy defines */
-#define DCMI_MISR_FRAME_MIS                  DCMI_MIS_FRAME_MIS
-#define DCMI_MISR_OVF_MIS                    DCMI_MIS_OVR_MIS
-#define DCMI_MISR_ERR_MIS                    DCMI_MIS_ERR_MIS
-#define DCMI_MISR_VSYNC_MIS                  DCMI_MIS_VSYNC_MIS
-#define DCMI_MISR_LINE_MIS                   DCMI_MIS_LINE_MIS
-
-/********************  Bits definition for DCMI_ICR register  *****************/
-#define DCMI_ICR_FRAME_ISC                   0x00000001U
-#define DCMI_ICR_OVR_ISC                     0x00000002U
-#define DCMI_ICR_ERR_ISC                     0x00000004U
-#define DCMI_ICR_VSYNC_ISC                   0x00000008U
-#define DCMI_ICR_LINE_ISC                    0x00000010U
-
-/* Legacy defines */
-#define DCMI_ICR_OVF_ISC                     DCMI_ICR_OVR_ISC
-
-/********************  Bits definition for DCMI_ESCR register  ******************/
-#define DCMI_ESCR_FSC                        0x000000FFU
-#define DCMI_ESCR_LSC                        0x0000FF00U
-#define DCMI_ESCR_LEC                        0x00FF0000U
-#define DCMI_ESCR_FEC                        0xFF000000U
-
-/********************  Bits definition for DCMI_ESUR register  ******************/
-#define DCMI_ESUR_FSU                        0x000000FFU
-#define DCMI_ESUR_LSU                        0x0000FF00U
-#define DCMI_ESUR_LEU                        0x00FF0000U
-#define DCMI_ESUR_FEU                        0xFF000000U
-
-/********************  Bits definition for DCMI_CWSTRT register  ******************/
-#define DCMI_CWSTRT_HOFFCNT                  0x00003FFFU
-#define DCMI_CWSTRT_VST                      0x1FFF0000U
-
-/********************  Bits definition for DCMI_CWSIZE register  ******************/
-#define DCMI_CWSIZE_CAPCNT                   0x00003FFFU
-#define DCMI_CWSIZE_VLINE                    0x3FFF0000U
-
-/********************  Bits definition for DCMI_DR register  ******************/
-#define DCMI_DR_BYTE0                        0x000000FFU
-#define DCMI_DR_BYTE1                        0x0000FF00U
-#define DCMI_DR_BYTE2                        0x00FF0000U
-#define DCMI_DR_BYTE3                        0xFF000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                             DMA Controller                                 */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DMA_SxCR register  *****************/
-#define DMA_SxCR_CHSEL                       0x0E000000U
-#define DMA_SxCR_CHSEL_0                     0x02000000U
-#define DMA_SxCR_CHSEL_1                     0x04000000U
-#define DMA_SxCR_CHSEL_2                     0x08000000U
-#define DMA_SxCR_MBURST                      0x01800000U
-#define DMA_SxCR_MBURST_0                    0x00800000U
-#define DMA_SxCR_MBURST_1                    0x01000000U
-#define DMA_SxCR_PBURST                      0x00600000U
-#define DMA_SxCR_PBURST_0                    0x00200000U
-#define DMA_SxCR_PBURST_1                    0x00400000U
-#define DMA_SxCR_CT                          0x00080000U
-#define DMA_SxCR_DBM                         0x00040000U
-#define DMA_SxCR_PL                          0x00030000U
-#define DMA_SxCR_PL_0                        0x00010000U
-#define DMA_SxCR_PL_1                        0x00020000U
-#define DMA_SxCR_PINCOS                      0x00008000U
-#define DMA_SxCR_MSIZE                       0x00006000U
-#define DMA_SxCR_MSIZE_0                     0x00002000U
-#define DMA_SxCR_MSIZE_1                     0x00004000U
-#define DMA_SxCR_PSIZE                       0x00001800U
-#define DMA_SxCR_PSIZE_0                     0x00000800U
-#define DMA_SxCR_PSIZE_1                     0x00001000U
-#define DMA_SxCR_MINC                        0x00000400U
-#define DMA_SxCR_PINC                        0x00000200U
-#define DMA_SxCR_CIRC                        0x00000100U
-#define DMA_SxCR_DIR                         0x000000C0U
-#define DMA_SxCR_DIR_0                       0x00000040U
-#define DMA_SxCR_DIR_1                       0x00000080U
-#define DMA_SxCR_PFCTRL                      0x00000020U
-#define DMA_SxCR_TCIE                        0x00000010U
-#define DMA_SxCR_HTIE                        0x00000008U
-#define DMA_SxCR_TEIE                        0x00000004U
-#define DMA_SxCR_DMEIE                       0x00000002U
-#define DMA_SxCR_EN                          0x00000001U
-
-/* Legacy defines */
-#define DMA_SxCR_ACK                         0x00100000U
-
-/********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            0x0000FFFFU
-#define DMA_SxNDT_0                          0x00000001U
-#define DMA_SxNDT_1                          0x00000002U
-#define DMA_SxNDT_2                          0x00000004U
-#define DMA_SxNDT_3                          0x00000008U
-#define DMA_SxNDT_4                          0x00000010U
-#define DMA_SxNDT_5                          0x00000020U
-#define DMA_SxNDT_6                          0x00000040U
-#define DMA_SxNDT_7                          0x00000080U
-#define DMA_SxNDT_8                          0x00000100U
-#define DMA_SxNDT_9                          0x00000200U
-#define DMA_SxNDT_10                         0x00000400U
-#define DMA_SxNDT_11                         0x00000800U
-#define DMA_SxNDT_12                         0x00001000U
-#define DMA_SxNDT_13                         0x00002000U
-#define DMA_SxNDT_14                         0x00004000U
-#define DMA_SxNDT_15                         0x00008000U
-
-/********************  Bits definition for DMA_SxFCR register  ****************/ 
-#define DMA_SxFCR_FEIE                       0x00000080U
-#define DMA_SxFCR_FS                         0x00000038U
-#define DMA_SxFCR_FS_0                       0x00000008U
-#define DMA_SxFCR_FS_1                       0x00000010U
-#define DMA_SxFCR_FS_2                       0x00000020U
-#define DMA_SxFCR_DMDIS                      0x00000004U
-#define DMA_SxFCR_FTH                        0x00000003U
-#define DMA_SxFCR_FTH_0                      0x00000001U
-#define DMA_SxFCR_FTH_1                      0x00000002U
-
-/********************  Bits definition for DMA_LISR register  *****************/ 
-#define DMA_LISR_TCIF3                       0x08000000U
-#define DMA_LISR_HTIF3                       0x04000000U
-#define DMA_LISR_TEIF3                       0x02000000U
-#define DMA_LISR_DMEIF3                      0x01000000U
-#define DMA_LISR_FEIF3                       0x00400000U
-#define DMA_LISR_TCIF2                       0x00200000U
-#define DMA_LISR_HTIF2                       0x00100000U
-#define DMA_LISR_TEIF2                       0x00080000U
-#define DMA_LISR_DMEIF2                      0x00040000U
-#define DMA_LISR_FEIF2                       0x00010000U
-#define DMA_LISR_TCIF1                       0x00000800U
-#define DMA_LISR_HTIF1                       0x00000400U
-#define DMA_LISR_TEIF1                       0x00000200U
-#define DMA_LISR_DMEIF1                      0x00000100U
-#define DMA_LISR_FEIF1                       0x00000040U
-#define DMA_LISR_TCIF0                       0x00000020U
-#define DMA_LISR_HTIF0                       0x00000010U
-#define DMA_LISR_TEIF0                       0x00000008U
-#define DMA_LISR_DMEIF0                      0x00000004U
-#define DMA_LISR_FEIF0                       0x00000001U
-
-/********************  Bits definition for DMA_HISR register  *****************/ 
-#define DMA_HISR_TCIF7                       0x08000000U
-#define DMA_HISR_HTIF7                       0x04000000U
-#define DMA_HISR_TEIF7                       0x02000000U
-#define DMA_HISR_DMEIF7                      0x01000000U
-#define DMA_HISR_FEIF7                       0x00400000U
-#define DMA_HISR_TCIF6                       0x00200000U
-#define DMA_HISR_HTIF6                       0x00100000U
-#define DMA_HISR_TEIF6                       0x00080000U
-#define DMA_HISR_DMEIF6                      0x00040000U
-#define DMA_HISR_FEIF6                       0x00010000U
-#define DMA_HISR_TCIF5                       0x00000800U
-#define DMA_HISR_HTIF5                       0x00000400U
-#define DMA_HISR_TEIF5                       0x00000200U
-#define DMA_HISR_DMEIF5                      0x00000100U
-#define DMA_HISR_FEIF5                       0x00000040U
-#define DMA_HISR_TCIF4                       0x00000020U
-#define DMA_HISR_HTIF4                       0x00000010U
-#define DMA_HISR_TEIF4                       0x00000008U
-#define DMA_HISR_DMEIF4                      0x00000004U
-#define DMA_HISR_FEIF4                       0x00000001U
-
-/********************  Bits definition for DMA_LIFCR register  ****************/ 
-#define DMA_LIFCR_CTCIF3                     0x08000000U
-#define DMA_LIFCR_CHTIF3                     0x04000000U
-#define DMA_LIFCR_CTEIF3                     0x02000000U
-#define DMA_LIFCR_CDMEIF3                    0x01000000U
-#define DMA_LIFCR_CFEIF3                     0x00400000U
-#define DMA_LIFCR_CTCIF2                     0x00200000U
-#define DMA_LIFCR_CHTIF2                     0x00100000U
-#define DMA_LIFCR_CTEIF2                     0x00080000U
-#define DMA_LIFCR_CDMEIF2                    0x00040000U
-#define DMA_LIFCR_CFEIF2                     0x00010000U
-#define DMA_LIFCR_CTCIF1                     0x00000800U
-#define DMA_LIFCR_CHTIF1                     0x00000400U
-#define DMA_LIFCR_CTEIF1                     0x00000200U
-#define DMA_LIFCR_CDMEIF1                    0x00000100U
-#define DMA_LIFCR_CFEIF1                     0x00000040U
-#define DMA_LIFCR_CTCIF0                     0x00000020U
-#define DMA_LIFCR_CHTIF0                     0x00000010U
-#define DMA_LIFCR_CTEIF0                     0x00000008U
-#define DMA_LIFCR_CDMEIF0                    0x00000004U
-#define DMA_LIFCR_CFEIF0                     0x00000001U
-
-/********************  Bits definition for DMA_HIFCR  register  ****************/ 
-#define DMA_HIFCR_CTCIF7                     0x08000000U
-#define DMA_HIFCR_CHTIF7                     0x04000000U
-#define DMA_HIFCR_CTEIF7                     0x02000000U
-#define DMA_HIFCR_CDMEIF7                    0x01000000U
-#define DMA_HIFCR_CFEIF7                     0x00400000U
-#define DMA_HIFCR_CTCIF6                     0x00200000U
-#define DMA_HIFCR_CHTIF6                     0x00100000U
-#define DMA_HIFCR_CTEIF6                     0x00080000U
-#define DMA_HIFCR_CDMEIF6                    0x00040000U
-#define DMA_HIFCR_CFEIF6                     0x00010000U
-#define DMA_HIFCR_CTCIF5                     0x00000800U
-#define DMA_HIFCR_CHTIF5                     0x00000400U
-#define DMA_HIFCR_CTEIF5                     0x00000200U
-#define DMA_HIFCR_CDMEIF5                    0x00000100U
-#define DMA_HIFCR_CFEIF5                     0x00000040U
-#define DMA_HIFCR_CTCIF4                     0x00000020U
-#define DMA_HIFCR_CHTIF4                     0x00000010U
-#define DMA_HIFCR_CTEIF4                     0x00000008U
-#define DMA_HIFCR_CDMEIF4                    0x00000004U
-#define DMA_HIFCR_CFEIF4                     0x00000001U
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                         AHB Master DMA2D Controller (DMA2D)                */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for DMA2D_CR register  ******************/
-
-#define DMA2D_CR_START                     0x00000001U               /*!< Start transfer */
-#define DMA2D_CR_SUSP                      0x00000002U               /*!< Suspend transfer */
-#define DMA2D_CR_ABORT                     0x00000004U               /*!< Abort transfer */
-#define DMA2D_CR_TEIE                      0x00000100U               /*!< Transfer Error Interrupt Enable */
-#define DMA2D_CR_TCIE                      0x00000200U               /*!< Transfer Complete Interrupt Enable */
-#define DMA2D_CR_TWIE                      0x00000400U               /*!< Transfer Watermark Interrupt Enable */
-#define DMA2D_CR_CAEIE                     0x00000800U               /*!< CLUT Access Error Interrupt Enable */
-#define DMA2D_CR_CTCIE                     0x00001000U               /*!< CLUT Transfer Complete Interrupt Enable */
-#define DMA2D_CR_CEIE                      0x00002000U               /*!< Configuration Error Interrupt Enable */
-#define DMA2D_CR_MODE                      0x00030000U               /*!< DMA2D Mode[1:0] */
-#define DMA2D_CR_MODE_0                    0x00010000U               /*!< DMA2D Mode bit 0 */
-#define DMA2D_CR_MODE_1                    0x00020000U               /*!< DMA2D Mode bit 1 */
-
-/********************  Bit definition for DMA2D_ISR register  *****************/
-
-#define DMA2D_ISR_TEIF                     0x00000001U               /*!< Transfer Error Interrupt Flag */
-#define DMA2D_ISR_TCIF                     0x00000002U               /*!< Transfer Complete Interrupt Flag */
-#define DMA2D_ISR_TWIF                     0x00000004U               /*!< Transfer Watermark Interrupt Flag */
-#define DMA2D_ISR_CAEIF                    0x00000008U               /*!< CLUT Access Error Interrupt Flag */
-#define DMA2D_ISR_CTCIF                    0x00000010U               /*!< CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_ISR_CEIF                     0x00000020U               /*!< Configuration Error Interrupt Flag */
-
-/********************  Bit definition for DMA2D_IFCR register  ****************/
-
-#define DMA2D_IFCR_CTEIF                   0x00000001U               /*!< Clears Transfer Error Interrupt Flag         */
-#define DMA2D_IFCR_CTCIF                   0x00000002U               /*!< Clears Transfer Complete Interrupt Flag      */
-#define DMA2D_IFCR_CTWIF                   0x00000004U               /*!< Clears Transfer Watermark Interrupt Flag     */
-#define DMA2D_IFCR_CAECIF                  0x00000008U               /*!< Clears CLUT Access Error Interrupt Flag      */
-#define DMA2D_IFCR_CCTCIF                  0x00000010U               /*!< Clears CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_IFCR_CCEIF                   0x00000020U               /*!< Clears Configuration Error Interrupt Flag    */
-
-/* Legacy defines */
-#define DMA2D_IFSR_CTEIF                   DMA2D_IFCR_CTEIF                     /*!< Clears Transfer Error Interrupt Flag         */
-#define DMA2D_IFSR_CTCIF                   DMA2D_IFCR_CTCIF                     /*!< Clears Transfer Complete Interrupt Flag      */
-#define DMA2D_IFSR_CTWIF                   DMA2D_IFCR_CTWIF                     /*!< Clears Transfer Watermark Interrupt Flag     */
-#define DMA2D_IFSR_CCAEIF                  DMA2D_IFCR_CAECIF                    /*!< Clears CLUT Access Error Interrupt Flag      */
-#define DMA2D_IFSR_CCTCIF                  DMA2D_IFCR_CCTCIF                    /*!< Clears CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_IFSR_CCEIF                   DMA2D_IFCR_CCEIF                     /*!< Clears Configuration Error Interrupt Flag    */
-
-/********************  Bit definition for DMA2D_FGMAR register  ***************/
-
-#define DMA2D_FGMAR_MA                     0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_FGOR register  ****************/
-
-#define DMA2D_FGOR_LO                      0x00003FFFU               /*!< Line Offset */
-
-/********************  Bit definition for DMA2D_BGMAR register  ***************/
-
-#define DMA2D_BGMAR_MA                     0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_BGOR register  ****************/
-
-#define DMA2D_BGOR_LO                      0x00003FFFU               /*!< Line Offset */
-
-/********************  Bit definition for DMA2D_FGPFCCR register  *************/
-
-#define DMA2D_FGPFCCR_CM                   0x0000000FU               /*!< Input color mode CM[3:0] */
-#define DMA2D_FGPFCCR_CM_0                 0x00000001U               /*!< Input color mode CM bit 0 */
-#define DMA2D_FGPFCCR_CM_1                 0x00000002U               /*!< Input color mode CM bit 1 */
-#define DMA2D_FGPFCCR_CM_2                 0x00000004U               /*!< Input color mode CM bit 2 */
-#define DMA2D_FGPFCCR_CM_3                 0x00000008U               /*!< Input color mode CM bit 3 */
-#define DMA2D_FGPFCCR_CCM                  0x00000010U               /*!< CLUT Color mode */
-#define DMA2D_FGPFCCR_START                0x00000020U               /*!< Start */
-#define DMA2D_FGPFCCR_CS                   0x0000FF00U               /*!< CLUT size */
-#define DMA2D_FGPFCCR_AM                   0x00030000U               /*!< Alpha mode AM[1:0] */
-#define DMA2D_FGPFCCR_AM_0                 0x00010000U               /*!< Alpha mode AM bit 0 */
-#define DMA2D_FGPFCCR_AM_1                 0x00020000U               /*!< Alpha mode AM bit 1 */
-#define DMA2D_FGPFCCR_ALPHA                0xFF000000U               /*!< Alpha value */
-
-/********************  Bit definition for DMA2D_FGCOLR register  **************/
-
-#define DMA2D_FGCOLR_BLUE                  0x000000FFU               /*!< Blue Value */
-#define DMA2D_FGCOLR_GREEN                 0x0000FF00U               /*!< Green Value */
-#define DMA2D_FGCOLR_RED                   0x00FF0000U               /*!< Red Value */   
-
-/********************  Bit definition for DMA2D_BGPFCCR register  *************/
-
-#define DMA2D_BGPFCCR_CM                   0x0000000FU               /*!< Input color mode CM[3:0] */
-#define DMA2D_BGPFCCR_CM_0                 0x00000001U               /*!< Input color mode CM bit 0 */
-#define DMA2D_BGPFCCR_CM_1                 0x00000002U               /*!< Input color mode CM bit 1 */
-#define DMA2D_BGPFCCR_CM_2                 0x00000004U               /*!< Input color mode CM bit 2 */
-#define DMA2D_FGPFCCR_CM_3                 0x00000008U               /*!< Input color mode CM bit 3 */
-#define DMA2D_BGPFCCR_CCM                  0x00000010U               /*!< CLUT Color mode */
-#define DMA2D_BGPFCCR_START                0x00000020U               /*!< Start */
-#define DMA2D_BGPFCCR_CS                   0x0000FF00U               /*!< CLUT size */
-#define DMA2D_BGPFCCR_AM                   0x00030000U               /*!< Alpha mode AM[1:0] */
-#define DMA2D_BGPFCCR_AM_0                 0x00010000U               /*!< Alpha mode AM bit 0 */
-#define DMA2D_BGPFCCR_AM_1                 0x00020000U               /*!< Alpha mode AM bit 1 */
-#define DMA2D_BGPFCCR_ALPHA                0xFF000000U               /*!< background Input Alpha value */
-
-/********************  Bit definition for DMA2D_BGCOLR register  **************/
-
-#define DMA2D_BGCOLR_BLUE                  0x000000FFU               /*!< Blue Value */
-#define DMA2D_BGCOLR_GREEN                 0x0000FF00U               /*!< Green Value */
-#define DMA2D_BGCOLR_RED                   0x00FF0000U               /*!< Red Value */
-
-/********************  Bit definition for DMA2D_FGCMAR register  **************/
-
-#define DMA2D_FGCMAR_MA                    0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_BGCMAR register  **************/
-
-#define DMA2D_BGCMAR_MA                    0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_OPFCCR register  **************/
-
-#define DMA2D_OPFCCR_CM                    0x00000007U               /*!< Color mode CM[2:0] */
-#define DMA2D_OPFCCR_CM_0                  0x00000001U               /*!< Color mode CM bit 0 */
-#define DMA2D_OPFCCR_CM_1                  0x00000002U               /*!< Color mode CM bit 1 */
-#define DMA2D_OPFCCR_CM_2                  0x00000004U               /*!< Color mode CM bit 2 */
-
-/********************  Bit definition for DMA2D_OCOLR register  ***************/
-
-/*!<Mode_ARGB8888/RGB888 */
-
-#define DMA2D_OCOLR_BLUE_1                 0x000000FFU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_1                0x0000FF00U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_1                  0x00FF0000U               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_1                0xFF000000U               /*!< Alpha Channel Value */
-
-/*!<Mode_RGB565 */
-#define DMA2D_OCOLR_BLUE_2                 0x0000001FU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_2                0x000007E0U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_2                  0x0000F800U               /*!< Red Value */
-
-/*!<Mode_ARGB1555 */
-#define DMA2D_OCOLR_BLUE_3                 0x0000001FU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_3                0x000003E0U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_3                  0x00007C00U               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_3                0x00008000U               /*!< Alpha Channel Value */
-
-/*!<Mode_ARGB4444 */
-#define DMA2D_OCOLR_BLUE_4                 0x0000000FU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_4                0x000000F0U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_4                  0x00000F00U               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_4                0x0000F000U               /*!< Alpha Channel Value */
-
-/********************  Bit definition for DMA2D_OMAR register  ****************/
-
-#define DMA2D_OMAR_MA                      0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_OOR register  *****************/
-
-#define DMA2D_OOR_LO                       0x00003FFFU               /*!< Line Offset */
-
-/********************  Bit definition for DMA2D_NLR register  *****************/
-
-#define DMA2D_NLR_NL                       0x0000FFFFU               /*!< Number of Lines */
-#define DMA2D_NLR_PL                       0x3FFF0000U               /*!< Pixel per Lines */
-
-/********************  Bit definition for DMA2D_LWR register  *****************/
-
-#define DMA2D_LWR_LW                       0x0000FFFFU               /*!< Line Watermark */
-
-/********************  Bit definition for DMA2D_AMTCR register  ***************/
-
-#define DMA2D_AMTCR_EN                     0x00000001U               /*!< Enable */
-#define DMA2D_AMTCR_DT                     0x0000FF00U               /*!< Dead Time */
-
-/********************  Bit definition for DMA2D_FGCLUT register  **************/
-                                                                     
-/********************  Bit definition for DMA2D_BGCLUT register  **************/
-
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                    External Interrupt/Event Controller                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    FLASH                                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    0x0000000FU
-#define FLASH_ACR_LATENCY_0WS                0x00000000U
-#define FLASH_ACR_LATENCY_1WS                0x00000001U
-#define FLASH_ACR_LATENCY_2WS                0x00000002U
-#define FLASH_ACR_LATENCY_3WS                0x00000003U
-#define FLASH_ACR_LATENCY_4WS                0x00000004U
-#define FLASH_ACR_LATENCY_5WS                0x00000005U
-#define FLASH_ACR_LATENCY_6WS                0x00000006U
-#define FLASH_ACR_LATENCY_7WS                0x00000007U
-#define FLASH_ACR_LATENCY_8WS                0x00000008U
-#define FLASH_ACR_LATENCY_9WS                0x00000009U
-#define FLASH_ACR_LATENCY_10WS               0x0000000AU
-#define FLASH_ACR_LATENCY_11WS               0x0000000BU
-#define FLASH_ACR_LATENCY_12WS               0x0000000CU
-#define FLASH_ACR_LATENCY_13WS               0x0000000DU
-#define FLASH_ACR_LATENCY_14WS               0x0000000EU
-#define FLASH_ACR_LATENCY_15WS               0x0000000FU
-#define FLASH_ACR_PRFTEN                     0x00000100U
-#define FLASH_ACR_ICEN                       0x00000200U
-#define FLASH_ACR_DCEN                       0x00000400U
-#define FLASH_ACR_ICRST                      0x00000800U
-#define FLASH_ACR_DCRST                      0x00001000U
-#define FLASH_ACR_BYTE0_ADDRESS              0x40023C00U
-#define FLASH_ACR_BYTE2_ADDRESS              0x40023C03U
-
-/*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         0x00000001U
-#define FLASH_SR_SOP                         0x00000002U
-#define FLASH_SR_WRPERR                      0x00000010U
-#define FLASH_SR_PGAERR                      0x00000020U
-#define FLASH_SR_PGPERR                      0x00000040U
-#define FLASH_SR_PGSERR                      0x00000080U
-#define FLASH_SR_BSY                         0x00010000U
-
-/*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          0x00000001U
-#define FLASH_CR_SER                         0x00000002U
-#define FLASH_CR_MER                         0x00000004U
-#define FLASH_CR_MER1                        FLASH_CR_MER
-#define FLASH_CR_SNB                         0x000000F8U
-#define FLASH_CR_SNB_0                       0x00000008U
-#define FLASH_CR_SNB_1                       0x00000010U
-#define FLASH_CR_SNB_2                       0x00000020U
-#define FLASH_CR_SNB_3                       0x00000040U
-#define FLASH_CR_SNB_4                       0x00000080U
-#define FLASH_CR_PSIZE                       0x00000300U
-#define FLASH_CR_PSIZE_0                     0x00000100U
-#define FLASH_CR_PSIZE_1                     0x00000200U
-#define FLASH_CR_MER2                        0x00008000U
-#define FLASH_CR_STRT                        0x00010000U
-#define FLASH_CR_EOPIE                       0x01000000U
-#define FLASH_CR_LOCK                        0x80000000U
-
-/*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                 0x00000001U
-#define FLASH_OPTCR_OPTSTRT                 0x00000002U
-#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
-#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
-#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
-#define FLASH_OPTCR_BFB2                    0x00000010U
-#define FLASH_OPTCR_WDG_SW                  0x00000020U
-#define FLASH_OPTCR_nRST_STOP               0x00000040U
-#define FLASH_OPTCR_nRST_STDBY              0x00000080U
-#define FLASH_OPTCR_RDP                     0x0000FF00U
-#define FLASH_OPTCR_RDP_0                   0x00000100U
-#define FLASH_OPTCR_RDP_1                   0x00000200U
-#define FLASH_OPTCR_RDP_2                   0x00000400U
-#define FLASH_OPTCR_RDP_3                   0x00000800U
-#define FLASH_OPTCR_RDP_4                   0x00001000U
-#define FLASH_OPTCR_RDP_5                   0x00002000U
-#define FLASH_OPTCR_RDP_6                   0x00004000U
-#define FLASH_OPTCR_RDP_7                   0x00008000U
-#define FLASH_OPTCR_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR_nWRP_0                  0x00010000U
-#define FLASH_OPTCR_nWRP_1                  0x00020000U
-#define FLASH_OPTCR_nWRP_2                  0x00040000U
-#define FLASH_OPTCR_nWRP_3                  0x00080000U
-#define FLASH_OPTCR_nWRP_4                  0x00100000U
-#define FLASH_OPTCR_nWRP_5                  0x00200000U
-#define FLASH_OPTCR_nWRP_6                  0x00400000U
-#define FLASH_OPTCR_nWRP_7                  0x00800000U
-#define FLASH_OPTCR_nWRP_8                  0x01000000U
-#define FLASH_OPTCR_nWRP_9                  0x02000000U
-#define FLASH_OPTCR_nWRP_10                 0x04000000U
-#define FLASH_OPTCR_nWRP_11                 0x08000000U
-#define FLASH_OPTCR_DB1M                    0x40000000U 
-#define FLASH_OPTCR_SPRMOD                  0x80000000U 
-                                             
-/******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR1_nWRP_0                  0x00010000U
-#define FLASH_OPTCR1_nWRP_1                  0x00020000U
-#define FLASH_OPTCR1_nWRP_2                  0x00040000U
-#define FLASH_OPTCR1_nWRP_3                  0x00080000U
-#define FLASH_OPTCR1_nWRP_4                  0x00100000U
-#define FLASH_OPTCR1_nWRP_5                  0x00200000U
-#define FLASH_OPTCR1_nWRP_6                  0x00400000U
-#define FLASH_OPTCR1_nWRP_7                  0x00800000U
-#define FLASH_OPTCR1_nWRP_8                  0x01000000U
-#define FLASH_OPTCR1_nWRP_9                  0x02000000U
-#define FLASH_OPTCR1_nWRP_10                 0x04000000U
-#define FLASH_OPTCR1_nWRP_11                 0x08000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Flexible Memory Controller                        */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for FMC_BCR1 register  *******************/
-#define  FMC_BCR1_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR1_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FMC_BCR1_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR1_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR1_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FMC_BCR1_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR1_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR1_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_BCR1_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR1_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR1_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR1_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
-#define  FMC_BCR1_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR1_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR1_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR1_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR1_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR1_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FMC_BCR1_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FMC_BCR1_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FMC_BCR1_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FMC_BCR1_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-#define  FMC_BCR1_CCLKEN                    0x00100000U        /*!<Continous clock enable     */
-
-/******************  Bit definition for FMC_BCR2 register  *******************/
-#define  FMC_BCR2_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR2_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FMC_BCR2_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR2_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR2_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FMC_BCR2_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR2_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR2_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_BCR2_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR2_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR2_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR2_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
-#define  FMC_BCR2_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR2_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR2_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR2_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR2_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR2_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FMC_BCR2_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FMC_BCR2_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FMC_BCR2_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FMC_BCR2_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FMC_BCR3 register  *******************/
-#define  FMC_BCR3_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR3_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FMC_BCR3_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR3_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR3_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FMC_BCR3_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR3_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR3_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_BCR3_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR3_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR3_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR3_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
-#define  FMC_BCR3_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR3_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR3_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR3_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR3_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR3_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FMC_BCR3_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FMC_BCR3_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FMC_BCR3_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FMC_BCR3_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FMC_BCR4 register  *******************/
-#define  FMC_BCR4_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR4_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FMC_BCR4_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR4_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR4_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FMC_BCR4_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR4_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR4_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_BCR4_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR4_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR4_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR4_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
-#define  FMC_BCR4_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR4_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR4_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR4_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR4_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR4_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FMC_BCR4_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FMC_BCR4_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FMC_BCR4_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FMC_BCR4_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FMC_BTR1 register  ******************/
-#define  FMC_BTR1_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR1_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR1_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR1_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR1_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BTR1_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
-#define  FMC_BTR1_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR1_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR1_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR1_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BTR1_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR1_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR1_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR1_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR1_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR1_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR1_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR1_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR1_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BTR1_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR1_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR1_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR1_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR1_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BTR1_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR1_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR1_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR1_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR1_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FMC_BTR1_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR1_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR1_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR1_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR1_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FMC_BTR1_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR1_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR1_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BTR2 register  *******************/
-#define  FMC_BTR2_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR2_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR2_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR2_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR2_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BTR2_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR2_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR2_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR2_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR2_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BTR2_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR2_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR2_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR2_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR2_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR2_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR2_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR2_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR2_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BTR2_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR2_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR2_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR2_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR2_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BTR2_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR2_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR2_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR2_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR2_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FMC_BTR2_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR2_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR2_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR2_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR2_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FMC_BTR2_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR2_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR2_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/*******************  Bit definition for FMC_BTR3 register  *******************/
-#define  FMC_BTR3_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR3_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR3_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR3_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR3_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BTR3_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR3_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR3_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR3_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR3_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BTR3_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR3_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR3_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR3_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR3_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR3_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR3_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR3_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR3_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BTR3_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR3_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR3_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR3_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR3_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BTR3_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR3_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR3_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR3_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR3_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FMC_BTR3_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR3_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR3_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR3_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR3_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FMC_BTR3_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR3_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR3_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BTR4 register  *******************/
-#define  FMC_BTR4_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR4_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR4_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR4_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR4_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BTR4_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR4_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR4_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR4_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR4_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BTR4_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR4_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR4_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR4_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR4_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR4_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR4_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR4_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR4_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BTR4_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR4_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR4_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR4_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR4_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BTR4_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR4_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR4_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR4_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR4_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FMC_BTR4_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR4_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR4_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR4_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR4_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FMC_BTR4_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR4_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR4_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR1 register  ******************/
-#define  FMC_BWTR1_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR1_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR1_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR1_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR1_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BWTR1_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR1_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR1_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR1_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR1_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BWTR1_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR1_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR1_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR1_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR1_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR1_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR1_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR1_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR1_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BWTR1_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR1_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR1_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR1_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR1_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BWTR1_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR1_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR1_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR2 register  ******************/
-#define  FMC_BWTR2_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR2_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR2_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR2_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR2_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BWTR2_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR2_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR2_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR2_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR2_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BWTR2_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR2_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR2_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR2_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR2_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR2_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR2_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR2_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR2_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BWTR2_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR2_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR2_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR2_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR2_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BWTR2_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR2_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR2_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR3 register  ******************/
-#define  FMC_BWTR3_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR3_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR3_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR3_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR3_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BWTR3_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR3_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR3_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR3_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR3_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BWTR3_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR3_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR3_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR3_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR3_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR3_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR3_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR3_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR3_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BWTR3_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR3_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR3_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR3_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR3_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BWTR3_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR3_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR3_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR4 register  ******************/
-#define  FMC_BWTR4_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR4_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR4_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR4_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR4_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BWTR4_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR4_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR4_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR4_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR4_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BWTR4_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR4_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR4_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR4_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR4_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR4_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR4_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR4_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR4_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BWTR4_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR4_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR4_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR4_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR4_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BWTR4_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR4_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR4_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_PCR2 register  *******************/
-#define  FMC_PCR2_PWAITEN                   0x00000002U        /*!<Wait feature enable bit                   */
-#define  FMC_PCR2_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FMC_PCR2_PTYP                      0x00000008U        /*!<Memory type                               */
-
-#define  FMC_PCR2_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FMC_PCR2_PWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_PCR2_PWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_PCR2_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit          */
-
-#define  FMC_PCR2_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay)          */
-#define  FMC_PCR2_TCLR_0                    0x00000200U        /*!<Bit 0 */
-#define  FMC_PCR2_TCLR_1                    0x00000400U        /*!<Bit 1 */
-#define  FMC_PCR2_TCLR_2                    0x00000800U        /*!<Bit 2 */
-#define  FMC_PCR2_TCLR_3                    0x00001000U        /*!<Bit 3 */
-
-#define  FMC_PCR2_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay)           */
-#define  FMC_PCR2_TAR_0                     0x00002000U        /*!<Bit 0 */
-#define  FMC_PCR2_TAR_1                     0x00004000U        /*!<Bit 1 */
-#define  FMC_PCR2_TAR_2                     0x00008000U        /*!<Bit 2 */
-#define  FMC_PCR2_TAR_3                     0x00010000U        /*!<Bit 3 */
-
-#define  FMC_PCR2_ECCPS                     0x000E0000U        /*!<ECCPS[1:0] bits (ECC page size)           */
-#define  FMC_PCR2_ECCPS_0                   0x00020000U        /*!<Bit 0 */
-#define  FMC_PCR2_ECCPS_1                   0x00040000U        /*!<Bit 1 */
-#define  FMC_PCR2_ECCPS_2                   0x00080000U        /*!<Bit 2 */
-
-/******************  Bit definition for FMC_PCR3 register  *******************/
-#define  FMC_PCR3_PWAITEN                   0x00000002U        /*!<Wait feature enable bit                   */
-#define  FMC_PCR3_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FMC_PCR3_PTYP                      0x00000008U        /*!<Memory type                               */
-
-#define  FMC_PCR3_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FMC_PCR3_PWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_PCR3_PWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_PCR3_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit          */
-
-#define  FMC_PCR3_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay)          */
-#define  FMC_PCR3_TCLR_0                    0x00000200U        /*!<Bit 0 */
-#define  FMC_PCR3_TCLR_1                    0x00000400U        /*!<Bit 1 */
-#define  FMC_PCR3_TCLR_2                    0x00000800U        /*!<Bit 2 */
-#define  FMC_PCR3_TCLR_3                    0x00001000U        /*!<Bit 3 */
-
-#define  FMC_PCR3_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay)           */
-#define  FMC_PCR3_TAR_0                     0x00002000U        /*!<Bit 0 */
-#define  FMC_PCR3_TAR_1                     0x00004000U        /*!<Bit 1 */
-#define  FMC_PCR3_TAR_2                     0x00008000U        /*!<Bit 2 */
-#define  FMC_PCR3_TAR_3                     0x00010000U        /*!<Bit 3 */
-
-#define  FMC_PCR3_ECCPS                     0x000E0000U        /*!<ECCPS[2:0] bits (ECC page size)           */
-#define  FMC_PCR3_ECCPS_0                   0x00020000U        /*!<Bit 0 */
-#define  FMC_PCR3_ECCPS_1                   0x00040000U        /*!<Bit 1 */
-#define  FMC_PCR3_ECCPS_2                   0x00080000U        /*!<Bit 2 */
-
-/******************  Bit definition for FMC_PCR4 register  *******************/
-#define  FMC_PCR4_PWAITEN                   0x00000002U        /*!<Wait feature enable bit                   */
-#define  FMC_PCR4_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FMC_PCR4_PTYP                      0x00000008U        /*!<Memory type                               */
-
-#define  FMC_PCR4_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FMC_PCR4_PWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_PCR4_PWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_PCR4_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit          */
-
-#define  FMC_PCR4_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay)          */
-#define  FMC_PCR4_TCLR_0                    0x00000200U        /*!<Bit 0 */
-#define  FMC_PCR4_TCLR_1                    0x00000400U        /*!<Bit 1 */
-#define  FMC_PCR4_TCLR_2                    0x00000800U        /*!<Bit 2 */
-#define  FMC_PCR4_TCLR_3                    0x00001000U        /*!<Bit 3 */
-
-#define  FMC_PCR4_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay)           */
-#define  FMC_PCR4_TAR_0                     0x00002000U        /*!<Bit 0 */
-#define  FMC_PCR4_TAR_1                     0x00004000U        /*!<Bit 1 */
-#define  FMC_PCR4_TAR_2                     0x00008000U        /*!<Bit 2 */
-#define  FMC_PCR4_TAR_3                     0x00010000U        /*!<Bit 3 */
-
-#define  FMC_PCR4_ECCPS                     0x000E0000U        /*!<ECCPS[2:0] bits (ECC page size)           */
-#define  FMC_PCR4_ECCPS_0                   0x00020000U        /*!<Bit 0 */
-#define  FMC_PCR4_ECCPS_1                   0x00040000U        /*!<Bit 1 */
-#define  FMC_PCR4_ECCPS_2                   0x00080000U        /*!<Bit 2 */
-
-/*******************  Bit definition for FMC_SR2 register  *******************/
-#define  FMC_SR2_IRS                        0x01U               /*!<Interrupt Rising Edge status                */
-#define  FMC_SR2_ILS                        0x02U               /*!<Interrupt Level status                      */
-#define  FMC_SR2_IFS                        0x04U               /*!<Interrupt Falling Edge status               */
-#define  FMC_SR2_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FMC_SR2_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit        */
-#define  FMC_SR2_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FMC_SR2_FEMPT                      0x40U               /*!<FIFO empty                                  */
-
-/*******************  Bit definition for FMC_SR3 register  *******************/
-#define  FMC_SR3_IRS                        0x01U               /*!<Interrupt Rising Edge status                */
-#define  FMC_SR3_ILS                        0x02U               /*!<Interrupt Level status                      */
-#define  FMC_SR3_IFS                        0x04U               /*!<Interrupt Falling Edge status               */
-#define  FMC_SR3_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FMC_SR3_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit        */
-#define  FMC_SR3_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FMC_SR3_FEMPT                      0x40U               /*!<FIFO empty                                  */
-
-/*******************  Bit definition for FMC_SR4 register  *******************/
-#define  FMC_SR4_IRS                        0x01U               /*!<Interrupt Rising Edge status                */
-#define  FMC_SR4_ILS                        0x02U               /*!<Interrupt Level status                      */
-#define  FMC_SR4_IFS                        0x04U               /*!<Interrupt Falling Edge status               */
-#define  FMC_SR4_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FMC_SR4_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit        */
-#define  FMC_SR4_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FMC_SR4_FEMPT                      0x40U               /*!<FIFO empty                                  */
-
-/******************  Bit definition for FMC_PMEM2 register  ******************/
-#define  FMC_PMEM2_MEMSET2                  0x000000FFU        /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
-#define  FMC_PMEM2_MEMSET2_0                0x00000001U        /*!<Bit 0 */
-#define  FMC_PMEM2_MEMSET2_1                0x00000002U        /*!<Bit 1 */
-#define  FMC_PMEM2_MEMSET2_2                0x00000004U        /*!<Bit 2 */
-#define  FMC_PMEM2_MEMSET2_3                0x00000008U        /*!<Bit 3 */
-#define  FMC_PMEM2_MEMSET2_4                0x00000010U        /*!<Bit 4 */
-#define  FMC_PMEM2_MEMSET2_5                0x00000020U        /*!<Bit 5 */
-#define  FMC_PMEM2_MEMSET2_6                0x00000040U        /*!<Bit 6 */
-#define  FMC_PMEM2_MEMSET2_7                0x00000080U        /*!<Bit 7 */
-
-#define  FMC_PMEM2_MEMWAIT2                 0x0000FF00U        /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
-#define  FMC_PMEM2_MEMWAIT2_0               0x00000100U        /*!<Bit 0 */
-#define  FMC_PMEM2_MEMWAIT2_1               0x00000200U        /*!<Bit 1 */
-#define  FMC_PMEM2_MEMWAIT2_2               0x00000400U        /*!<Bit 2 */
-#define  FMC_PMEM2_MEMWAIT2_3               0x00000800U        /*!<Bit 3 */
-#define  FMC_PMEM2_MEMWAIT2_4               0x00001000U        /*!<Bit 4 */
-#define  FMC_PMEM2_MEMWAIT2_5               0x00002000U        /*!<Bit 5 */
-#define  FMC_PMEM2_MEMWAIT2_6               0x00004000U        /*!<Bit 6 */
-#define  FMC_PMEM2_MEMWAIT2_7               0x00008000U        /*!<Bit 7 */
-
-#define  FMC_PMEM2_MEMHOLD2                 0x00FF0000U        /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
-#define  FMC_PMEM2_MEMHOLD2_0               0x00010000U        /*!<Bit 0 */
-#define  FMC_PMEM2_MEMHOLD2_1               0x00020000U        /*!<Bit 1 */
-#define  FMC_PMEM2_MEMHOLD2_2               0x00040000U        /*!<Bit 2 */
-#define  FMC_PMEM2_MEMHOLD2_3               0x00080000U        /*!<Bit 3 */
-#define  FMC_PMEM2_MEMHOLD2_4               0x00100000U        /*!<Bit 4 */
-#define  FMC_PMEM2_MEMHOLD2_5               0x00200000U        /*!<Bit 5 */
-#define  FMC_PMEM2_MEMHOLD2_6               0x00400000U        /*!<Bit 6 */
-#define  FMC_PMEM2_MEMHOLD2_7               0x00800000U        /*!<Bit 7 */
-
-#define  FMC_PMEM2_MEMHIZ2                  0xFF000000U        /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
-#define  FMC_PMEM2_MEMHIZ2_0                0x01000000U        /*!<Bit 0 */
-#define  FMC_PMEM2_MEMHIZ2_1                0x02000000U        /*!<Bit 1 */
-#define  FMC_PMEM2_MEMHIZ2_2                0x04000000U        /*!<Bit 2 */
-#define  FMC_PMEM2_MEMHIZ2_3                0x08000000U        /*!<Bit 3 */
-#define  FMC_PMEM2_MEMHIZ2_4                0x10000000U        /*!<Bit 4 */
-#define  FMC_PMEM2_MEMHIZ2_5                0x20000000U        /*!<Bit 5 */
-#define  FMC_PMEM2_MEMHIZ2_6                0x40000000U        /*!<Bit 6 */
-#define  FMC_PMEM2_MEMHIZ2_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_PMEM3 register  ******************/
-#define  FMC_PMEM3_MEMSET3                  0x000000FFU        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
-#define  FMC_PMEM3_MEMSET3_0                0x00000001U        /*!<Bit 0 */
-#define  FMC_PMEM3_MEMSET3_1                0x00000002U        /*!<Bit 1 */
-#define  FMC_PMEM3_MEMSET3_2                0x00000004U        /*!<Bit 2 */
-#define  FMC_PMEM3_MEMSET3_3                0x00000008U        /*!<Bit 3 */
-#define  FMC_PMEM3_MEMSET3_4                0x00000010U        /*!<Bit 4 */
-#define  FMC_PMEM3_MEMSET3_5                0x00000020U        /*!<Bit 5 */
-#define  FMC_PMEM3_MEMSET3_6                0x00000040U        /*!<Bit 6 */
-#define  FMC_PMEM3_MEMSET3_7                0x00000080U        /*!<Bit 7 */
-
-#define  FMC_PMEM3_MEMWAIT3                 0x0000FF00U        /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
-#define  FMC_PMEM3_MEMWAIT3_0               0x00000100U        /*!<Bit 0 */
-#define  FMC_PMEM3_MEMWAIT3_1               0x00000200U        /*!<Bit 1 */
-#define  FMC_PMEM3_MEMWAIT3_2               0x00000400U        /*!<Bit 2 */
-#define  FMC_PMEM3_MEMWAIT3_3               0x00000800U        /*!<Bit 3 */
-#define  FMC_PMEM3_MEMWAIT3_4               0x00001000U        /*!<Bit 4 */
-#define  FMC_PMEM3_MEMWAIT3_5               0x00002000U        /*!<Bit 5 */
-#define  FMC_PMEM3_MEMWAIT3_6               0x00004000U        /*!<Bit 6 */
-#define  FMC_PMEM3_MEMWAIT3_7               0x00008000U        /*!<Bit 7 */
-
-#define  FMC_PMEM3_MEMHOLD3                 0x00FF0000U        /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
-#define  FMC_PMEM3_MEMHOLD3_0               0x00010000U        /*!<Bit 0 */
-#define  FMC_PMEM3_MEMHOLD3_1               0x00020000U        /*!<Bit 1 */
-#define  FMC_PMEM3_MEMHOLD3_2               0x00040000U        /*!<Bit 2 */
-#define  FMC_PMEM3_MEMHOLD3_3               0x00080000U        /*!<Bit 3 */
-#define  FMC_PMEM3_MEMHOLD3_4               0x00100000U        /*!<Bit 4 */
-#define  FMC_PMEM3_MEMHOLD3_5               0x00200000U        /*!<Bit 5 */
-#define  FMC_PMEM3_MEMHOLD3_6               0x00400000U        /*!<Bit 6 */
-#define  FMC_PMEM3_MEMHOLD3_7               0x00800000U        /*!<Bit 7 */
-
-#define  FMC_PMEM3_MEMHIZ3                  0xFF000000U        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
-#define  FMC_PMEM3_MEMHIZ3_0                0x01000000U        /*!<Bit 0 */
-#define  FMC_PMEM3_MEMHIZ3_1                0x02000000U        /*!<Bit 1 */
-#define  FMC_PMEM3_MEMHIZ3_2                0x04000000U        /*!<Bit 2 */
-#define  FMC_PMEM3_MEMHIZ3_3                0x08000000U        /*!<Bit 3 */
-#define  FMC_PMEM3_MEMHIZ3_4                0x10000000U        /*!<Bit 4 */
-#define  FMC_PMEM3_MEMHIZ3_5                0x20000000U        /*!<Bit 5 */
-#define  FMC_PMEM3_MEMHIZ3_6                0x40000000U        /*!<Bit 6 */
-#define  FMC_PMEM3_MEMHIZ3_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_PMEM4 register  ******************/
-#define  FMC_PMEM4_MEMSET4                  0x000000FFU        /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
-#define  FMC_PMEM4_MEMSET4_0                0x00000001U        /*!<Bit 0 */
-#define  FMC_PMEM4_MEMSET4_1                0x00000002U        /*!<Bit 1 */
-#define  FMC_PMEM4_MEMSET4_2                0x00000004U        /*!<Bit 2 */
-#define  FMC_PMEM4_MEMSET4_3                0x00000008U        /*!<Bit 3 */
-#define  FMC_PMEM4_MEMSET4_4                0x00000010U        /*!<Bit 4 */
-#define  FMC_PMEM4_MEMSET4_5                0x00000020U        /*!<Bit 5 */
-#define  FMC_PMEM4_MEMSET4_6                0x00000040U        /*!<Bit 6 */
-#define  FMC_PMEM4_MEMSET4_7                0x00000080U        /*!<Bit 7 */
-
-#define  FMC_PMEM4_MEMWAIT4                 0x0000FF00U        /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
-#define  FMC_PMEM4_MEMWAIT4_0               0x00000100U        /*!<Bit 0 */
-#define  FMC_PMEM4_MEMWAIT4_1               0x00000200U        /*!<Bit 1 */
-#define  FMC_PMEM4_MEMWAIT4_2               0x00000400U        /*!<Bit 2 */
-#define  FMC_PMEM4_MEMWAIT4_3               0x00000800U        /*!<Bit 3 */
-#define  FMC_PMEM4_MEMWAIT4_4               0x00001000U        /*!<Bit 4 */
-#define  FMC_PMEM4_MEMWAIT4_5               0x00002000U        /*!<Bit 5 */
-#define  FMC_PMEM4_MEMWAIT4_6               0x00004000U        /*!<Bit 6 */
-#define  FMC_PMEM4_MEMWAIT4_7               0x00008000U        /*!<Bit 7 */
-
-#define  FMC_PMEM4_MEMHOLD4                 0x00FF0000U        /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
-#define  FMC_PMEM4_MEMHOLD4_0               0x00010000U        /*!<Bit 0 */
-#define  FMC_PMEM4_MEMHOLD4_1               0x00020000U        /*!<Bit 1 */
-#define  FMC_PMEM4_MEMHOLD4_2               0x00040000U        /*!<Bit 2 */
-#define  FMC_PMEM4_MEMHOLD4_3               0x00080000U        /*!<Bit 3 */
-#define  FMC_PMEM4_MEMHOLD4_4               0x00100000U        /*!<Bit 4 */
-#define  FMC_PMEM4_MEMHOLD4_5               0x00200000U        /*!<Bit 5 */
-#define  FMC_PMEM4_MEMHOLD4_6               0x00400000U        /*!<Bit 6 */
-#define  FMC_PMEM4_MEMHOLD4_7               0x00800000U        /*!<Bit 7 */
-
-#define  FMC_PMEM4_MEMHIZ4                  0xFF000000U        /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
-#define  FMC_PMEM4_MEMHIZ4_0                0x01000000U        /*!<Bit 0 */
-#define  FMC_PMEM4_MEMHIZ4_1                0x02000000U        /*!<Bit 1 */
-#define  FMC_PMEM4_MEMHIZ4_2                0x04000000U        /*!<Bit 2 */
-#define  FMC_PMEM4_MEMHIZ4_3                0x08000000U        /*!<Bit 3 */
-#define  FMC_PMEM4_MEMHIZ4_4                0x10000000U        /*!<Bit 4 */
-#define  FMC_PMEM4_MEMHIZ4_5                0x20000000U        /*!<Bit 5 */
-#define  FMC_PMEM4_MEMHIZ4_6                0x40000000U        /*!<Bit 6 */
-#define  FMC_PMEM4_MEMHIZ4_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_PATT2 register  ******************/
-#define  FMC_PATT2_ATTSET2                  0x000000FFU        /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
-#define  FMC_PATT2_ATTSET2_0                0x00000001U        /*!<Bit 0 */
-#define  FMC_PATT2_ATTSET2_1                0x00000002U        /*!<Bit 1 */
-#define  FMC_PATT2_ATTSET2_2                0x00000004U        /*!<Bit 2 */
-#define  FMC_PATT2_ATTSET2_3                0x00000008U        /*!<Bit 3 */
-#define  FMC_PATT2_ATTSET2_4                0x00000010U        /*!<Bit 4 */
-#define  FMC_PATT2_ATTSET2_5                0x00000020U        /*!<Bit 5 */
-#define  FMC_PATT2_ATTSET2_6                0x00000040U        /*!<Bit 6 */
-#define  FMC_PATT2_ATTSET2_7                0x00000080U        /*!<Bit 7 */
-
-#define  FMC_PATT2_ATTWAIT2                 0x0000FF00U        /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
-#define  FMC_PATT2_ATTWAIT2_0               0x00000100U        /*!<Bit 0 */
-#define  FMC_PATT2_ATTWAIT2_1               0x00000200U        /*!<Bit 1 */
-#define  FMC_PATT2_ATTWAIT2_2               0x00000400U        /*!<Bit 2 */
-#define  FMC_PATT2_ATTWAIT2_3               0x00000800U        /*!<Bit 3 */
-#define  FMC_PATT2_ATTWAIT2_4               0x00001000U        /*!<Bit 4 */
-#define  FMC_PATT2_ATTWAIT2_5               0x00002000U        /*!<Bit 5 */
-#define  FMC_PATT2_ATTWAIT2_6               0x00004000U        /*!<Bit 6 */
-#define  FMC_PATT2_ATTWAIT2_7               0x00008000U        /*!<Bit 7 */
-
-#define  FMC_PATT2_ATTHOLD2                 0x00FF0000U        /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
-#define  FMC_PATT2_ATTHOLD2_0               0x00010000U        /*!<Bit 0 */
-#define  FMC_PATT2_ATTHOLD2_1               0x00020000U        /*!<Bit 1 */
-#define  FMC_PATT2_ATTHOLD2_2               0x00040000U        /*!<Bit 2 */
-#define  FMC_PATT2_ATTHOLD2_3               0x00080000U        /*!<Bit 3 */
-#define  FMC_PATT2_ATTHOLD2_4               0x00100000U        /*!<Bit 4 */
-#define  FMC_PATT2_ATTHOLD2_5               0x00200000U        /*!<Bit 5 */
-#define  FMC_PATT2_ATTHOLD2_6               0x00400000U        /*!<Bit 6 */
-#define  FMC_PATT2_ATTHOLD2_7               0x00800000U        /*!<Bit 7 */
-
-#define  FMC_PATT2_ATTHIZ2                  0xFF000000U        /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
-#define  FMC_PATT2_ATTHIZ2_0                0x01000000U        /*!<Bit 0 */
-#define  FMC_PATT2_ATTHIZ2_1                0x02000000U        /*!<Bit 1 */
-#define  FMC_PATT2_ATTHIZ2_2                0x04000000U        /*!<Bit 2 */
-#define  FMC_PATT2_ATTHIZ2_3                0x08000000U        /*!<Bit 3 */
-#define  FMC_PATT2_ATTHIZ2_4                0x10000000U        /*!<Bit 4 */
-#define  FMC_PATT2_ATTHIZ2_5                0x20000000U        /*!<Bit 5 */
-#define  FMC_PATT2_ATTHIZ2_6                0x40000000U        /*!<Bit 6 */
-#define  FMC_PATT2_ATTHIZ2_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_PATT3 register  ******************/
-#define  FMC_PATT3_ATTSET3                  0x000000FFU        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
-#define  FMC_PATT3_ATTSET3_0                0x00000001U        /*!<Bit 0 */
-#define  FMC_PATT3_ATTSET3_1                0x00000002U        /*!<Bit 1 */
-#define  FMC_PATT3_ATTSET3_2                0x00000004U        /*!<Bit 2 */
-#define  FMC_PATT3_ATTSET3_3                0x00000008U        /*!<Bit 3 */
-#define  FMC_PATT3_ATTSET3_4                0x00000010U        /*!<Bit 4 */
-#define  FMC_PATT3_ATTSET3_5                0x00000020U        /*!<Bit 5 */
-#define  FMC_PATT3_ATTSET3_6                0x00000040U        /*!<Bit 6 */
-#define  FMC_PATT3_ATTSET3_7                0x00000080U        /*!<Bit 7 */
-
-#define  FMC_PATT3_ATTWAIT3                 0x0000FF00U        /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
-#define  FMC_PATT3_ATTWAIT3_0               0x00000100U        /*!<Bit 0 */
-#define  FMC_PATT3_ATTWAIT3_1               0x00000200U        /*!<Bit 1 */
-#define  FMC_PATT3_ATTWAIT3_2               0x00000400U        /*!<Bit 2 */
-#define  FMC_PATT3_ATTWAIT3_3               0x00000800U        /*!<Bit 3 */
-#define  FMC_PATT3_ATTWAIT3_4               0x00001000U        /*!<Bit 4 */
-#define  FMC_PATT3_ATTWAIT3_5               0x00002000U        /*!<Bit 5 */
-#define  FMC_PATT3_ATTWAIT3_6               0x00004000U        /*!<Bit 6 */
-#define  FMC_PATT3_ATTWAIT3_7               0x00008000U        /*!<Bit 7 */
-
-#define  FMC_PATT3_ATTHOLD3                 0x00FF0000U        /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
-#define  FMC_PATT3_ATTHOLD3_0               0x00010000U        /*!<Bit 0 */
-#define  FMC_PATT3_ATTHOLD3_1               0x00020000U        /*!<Bit 1 */
-#define  FMC_PATT3_ATTHOLD3_2               0x00040000U        /*!<Bit 2 */
-#define  FMC_PATT3_ATTHOLD3_3               0x00080000U        /*!<Bit 3 */
-#define  FMC_PATT3_ATTHOLD3_4               0x00100000U        /*!<Bit 4 */
-#define  FMC_PATT3_ATTHOLD3_5               0x00200000U        /*!<Bit 5 */
-#define  FMC_PATT3_ATTHOLD3_6               0x00400000U        /*!<Bit 6 */
-#define  FMC_PATT3_ATTHOLD3_7               0x00800000U        /*!<Bit 7 */
-
-#define  FMC_PATT3_ATTHIZ3                  0xFF000000U        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
-#define  FMC_PATT3_ATTHIZ3_0                0x01000000U        /*!<Bit 0 */
-#define  FMC_PATT3_ATTHIZ3_1                0x02000000U        /*!<Bit 1 */
-#define  FMC_PATT3_ATTHIZ3_2                0x04000000U        /*!<Bit 2 */
-#define  FMC_PATT3_ATTHIZ3_3                0x08000000U        /*!<Bit 3 */
-#define  FMC_PATT3_ATTHIZ3_4                0x10000000U        /*!<Bit 4 */
-#define  FMC_PATT3_ATTHIZ3_5                0x20000000U        /*!<Bit 5 */
-#define  FMC_PATT3_ATTHIZ3_6                0x40000000U        /*!<Bit 6 */
-#define  FMC_PATT3_ATTHIZ3_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_PATT4 register  ******************/
-#define  FMC_PATT4_ATTSET4                  0x000000FFU        /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
-#define  FMC_PATT4_ATTSET4_0                0x00000001U        /*!<Bit 0 */
-#define  FMC_PATT4_ATTSET4_1                0x00000002U        /*!<Bit 1 */
-#define  FMC_PATT4_ATTSET4_2                0x00000004U        /*!<Bit 2 */
-#define  FMC_PATT4_ATTSET4_3                0x00000008U        /*!<Bit 3 */
-#define  FMC_PATT4_ATTSET4_4                0x00000010U        /*!<Bit 4 */
-#define  FMC_PATT4_ATTSET4_5                0x00000020U        /*!<Bit 5 */
-#define  FMC_PATT4_ATTSET4_6                0x00000040U        /*!<Bit 6 */
-#define  FMC_PATT4_ATTSET4_7                0x00000080U        /*!<Bit 7 */
-
-#define  FMC_PATT4_ATTWAIT4                 0x0000FF00U        /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
-#define  FMC_PATT4_ATTWAIT4_0               0x00000100U        /*!<Bit 0 */
-#define  FMC_PATT4_ATTWAIT4_1               0x00000200U        /*!<Bit 1 */
-#define  FMC_PATT4_ATTWAIT4_2               0x00000400U        /*!<Bit 2 */
-#define  FMC_PATT4_ATTWAIT4_3               0x00000800U        /*!<Bit 3 */
-#define  FMC_PATT4_ATTWAIT4_4               0x00001000U        /*!<Bit 4 */
-#define  FMC_PATT4_ATTWAIT4_5               0x00002000U        /*!<Bit 5 */
-#define  FMC_PATT4_ATTWAIT4_6               0x00004000U        /*!<Bit 6 */
-#define  FMC_PATT4_ATTWAIT4_7               0x00008000U        /*!<Bit 7 */
-
-#define  FMC_PATT4_ATTHOLD4                 0x00FF0000U        /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
-#define  FMC_PATT4_ATTHOLD4_0               0x00010000U        /*!<Bit 0 */
-#define  FMC_PATT4_ATTHOLD4_1               0x00020000U        /*!<Bit 1 */
-#define  FMC_PATT4_ATTHOLD4_2               0x00040000U        /*!<Bit 2 */
-#define  FMC_PATT4_ATTHOLD4_3               0x00080000U        /*!<Bit 3 */
-#define  FMC_PATT4_ATTHOLD4_4               0x00100000U        /*!<Bit 4 */
-#define  FMC_PATT4_ATTHOLD4_5               0x00200000U        /*!<Bit 5 */
-#define  FMC_PATT4_ATTHOLD4_6               0x00400000U        /*!<Bit 6 */
-#define  FMC_PATT4_ATTHOLD4_7               0x00800000U        /*!<Bit 7 */
-
-#define  FMC_PATT4_ATTHIZ4                  0xFF000000U        /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
-#define  FMC_PATT4_ATTHIZ4_0                0x01000000U        /*!<Bit 0 */
-#define  FMC_PATT4_ATTHIZ4_1                0x02000000U        /*!<Bit 1 */
-#define  FMC_PATT4_ATTHIZ4_2                0x04000000U        /*!<Bit 2 */
-#define  FMC_PATT4_ATTHIZ4_3                0x08000000U        /*!<Bit 3 */
-#define  FMC_PATT4_ATTHIZ4_4                0x10000000U        /*!<Bit 4 */
-#define  FMC_PATT4_ATTHIZ4_5                0x20000000U        /*!<Bit 5 */
-#define  FMC_PATT4_ATTHIZ4_6                0x40000000U        /*!<Bit 6 */
-#define  FMC_PATT4_ATTHIZ4_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_PIO4 register  *******************/
-#define  FMC_PIO4_IOSET4                    0x000000FFU        /*!<IOSET4[7:0] bits (I/O 4 setup time) */
-#define  FMC_PIO4_IOSET4_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_PIO4_IOSET4_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_PIO4_IOSET4_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_PIO4_IOSET4_3                  0x00000008U        /*!<Bit 3 */
-#define  FMC_PIO4_IOSET4_4                  0x00000010U        /*!<Bit 4 */
-#define  FMC_PIO4_IOSET4_5                  0x00000020U        /*!<Bit 5 */
-#define  FMC_PIO4_IOSET4_6                  0x00000040U        /*!<Bit 6 */
-#define  FMC_PIO4_IOSET4_7                  0x00000080U        /*!<Bit 7 */
-
-#define  FMC_PIO4_IOWAIT4                   0x0000FF00U        /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
-#define  FMC_PIO4_IOWAIT4_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_PIO4_IOWAIT4_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_PIO4_IOWAIT4_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_PIO4_IOWAIT4_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_PIO4_IOWAIT4_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_PIO4_IOWAIT4_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_PIO4_IOWAIT4_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_PIO4_IOWAIT4_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FMC_PIO4_IOHOLD4                   0x00FF0000U        /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
-#define  FMC_PIO4_IOHOLD4_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_PIO4_IOHOLD4_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_PIO4_IOHOLD4_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_PIO4_IOHOLD4_3                 0x00080000U        /*!<Bit 3 */
-#define  FMC_PIO4_IOHOLD4_4                 0x00100000U        /*!<Bit 4 */
-#define  FMC_PIO4_IOHOLD4_5                 0x00200000U        /*!<Bit 5 */
-#define  FMC_PIO4_IOHOLD4_6                 0x00400000U        /*!<Bit 6 */
-#define  FMC_PIO4_IOHOLD4_7                 0x00800000U        /*!<Bit 7 */
-
-#define  FMC_PIO4_IOHIZ4                    0xFF000000U        /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
-#define  FMC_PIO4_IOHIZ4_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_PIO4_IOHIZ4_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_PIO4_IOHIZ4_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_PIO4_IOHIZ4_3                  0x08000000U        /*!<Bit 3 */
-#define  FMC_PIO4_IOHIZ4_4                  0x10000000U        /*!<Bit 4 */
-#define  FMC_PIO4_IOHIZ4_5                  0x20000000U        /*!<Bit 5 */
-#define  FMC_PIO4_IOHIZ4_6                  0x40000000U        /*!<Bit 6 */
-#define  FMC_PIO4_IOHIZ4_7                  0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_ECCR2 register  ******************/
-#define  FMC_ECCR2_ECC2                     0xFFFFFFFFU        /*!<ECC result */
-
-/******************  Bit definition for FMC_ECCR3 register  ******************/
-#define  FMC_ECCR3_ECC3                     0xFFFFFFFFU        /*!<ECC result */
-
-/******************  Bit definition for FMC_SDCR1 register  ******************/
-#define  FMC_SDCR1_NC                       0x00000003U        /*!<NC[1:0] bits (Number of column bits) */
-#define  FMC_SDCR1_NC_0                     0x00000001U        /*!<Bit 0 */
-#define  FMC_SDCR1_NC_1                     0x00000002U        /*!<Bit 1 */
-
-#define  FMC_SDCR1_NR                       0x0000000CU        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR1_NR_0                     0x00000004U        /*!<Bit 0 */
-#define  FMC_SDCR1_NR_1                     0x00000008U        /*!<Bit 1 */
-
-#define  FMC_SDCR1_MWID                     0x00000030U        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR1_MWID_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDCR1_MWID_1                   0x00000020U        /*!<Bit 1 */
-
-#define  FMC_SDCR1_NB                       0x00000040U        /*!<Number of internal bank */
-
-#define  FMC_SDCR1_CAS                      0x00000180U        /*!<CAS[1:0] bits (CAS latency) */
-#define  FMC_SDCR1_CAS_0                    0x00000080U        /*!<Bit 0 */
-#define  FMC_SDCR1_CAS_1                    0x00000100U        /*!<Bit 1 */
-
-#define  FMC_SDCR1_WP                       0x00000200U        /*!<Write protection */
-
-#define  FMC_SDCR1_SDCLK                    0x00000C00U        /*!<SDRAM clock configuration */
-#define  FMC_SDCR1_SDCLK_0                  0x00000400U        /*!<Bit 0 */
-#define  FMC_SDCR1_SDCLK_1                  0x00000800U        /*!<Bit 1 */
-
-#define  FMC_SDCR1_RBURST                   0x00001000U        /*!<Read burst */
-
-#define  FMC_SDCR1_RPIPE                    0x00006000U        /*!<Write protection */
-#define  FMC_SDCR1_RPIPE_0                  0x00002000U        /*!<Bit 0 */
-#define  FMC_SDCR1_RPIPE_1                  0x00004000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_SDCR2 register  ******************/
-#define  FMC_SDCR2_NC                       0x00000003U        /*!<NC[1:0] bits (Number of column bits) */
-#define  FMC_SDCR2_NC_0                     0x00000001U        /*!<Bit 0 */
-#define  FMC_SDCR2_NC_1                     0x00000002U        /*!<Bit 1 */
-
-#define  FMC_SDCR2_NR                       0x0000000CU        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR2_NR_0                     0x00000004U        /*!<Bit 0 */
-#define  FMC_SDCR2_NR_1                     0x00000008U        /*!<Bit 1 */
-
-#define  FMC_SDCR2_MWID                     0x00000030U        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR2_MWID_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDCR2_MWID_1                   0x00000020U        /*!<Bit 1 */
-
-#define  FMC_SDCR2_NB                       0x00000040U        /*!<Number of internal bank */
-
-#define  FMC_SDCR2_CAS                      0x00000180U        /*!<CAS[1:0] bits (CAS latency) */
-#define  FMC_SDCR2_CAS_0                    0x00000080U        /*!<Bit 0 */
-#define  FMC_SDCR2_CAS_1                    0x00000100U        /*!<Bit 1 */
-
-#define  FMC_SDCR2_WP                       0x00000200U        /*!<Write protection */
-
-#define  FMC_SDCR2_SDCLK                    0x00000C00U        /*!<SDCLK[1:0] (SDRAM clock configuration) */
-#define  FMC_SDCR2_SDCLK_0                  0x00000400U        /*!<Bit 0 */
-#define  FMC_SDCR2_SDCLK_1                  0x00000800U        /*!<Bit 1 */
-
-#define  FMC_SDCR2_RBURST                   0x00001000U        /*!<Read burst */
-
-#define  FMC_SDCR2_RPIPE                    0x00006000U        /*!<RPIPE[1:0](Read pipe) */
-#define  FMC_SDCR2_RPIPE_0                  0x00002000U        /*!<Bit 0 */
-#define  FMC_SDCR2_RPIPE_1                  0x00004000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_SDTR1 register  ******************/
-#define  FMC_SDTR1_TMRD                     0x0000000FU        /*!<TMRD[3:0] bits (Load mode register to active) */
-#define  FMC_SDTR1_TMRD_0                   0x00000001U        /*!<Bit 0 */
-#define  FMC_SDTR1_TMRD_1                   0x00000002U        /*!<Bit 1 */
-#define  FMC_SDTR1_TMRD_2                   0x00000004U        /*!<Bit 2 */
-#define  FMC_SDTR1_TMRD_3                   0x00000008U        /*!<Bit 3 */
-                                            
-#define  FMC_SDTR1_TXSR                     0x000000F0U        /*!<TXSR[3:0] bits (Exit self refresh) */
-#define  FMC_SDTR1_TXSR_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDTR1_TXSR_1                   0x00000020U        /*!<Bit 1 */
-#define  FMC_SDTR1_TXSR_2                   0x00000040U        /*!<Bit 2 */
-#define  FMC_SDTR1_TXSR_3                   0x00000080U        /*!<Bit 3 */
-
-#define  FMC_SDTR1_TRAS                     0x00000F00U        /*!<TRAS[3:0] bits (Self refresh time) */
-#define  FMC_SDTR1_TRAS_0                   0x00000100U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRAS_1                   0x00000200U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRAS_2                   0x00000400U        /*!<Bit 2 */
-#define  FMC_SDTR1_TRAS_3                   0x00000800U        /*!<Bit 3 */
-
-#define  FMC_SDTR1_TRC                      0x0000F000U        /*!<TRC[2:0] bits (Row cycle delay) */
-#define  FMC_SDTR1_TRC_0                    0x00001000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRC_1                    0x00002000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRC_2                    0x00004000U        /*!<Bit 2 */
-
-#define  FMC_SDTR1_TWR                      0x000F0000U        /*!<TRC[2:0] bits (Write recovery delay) */
-#define  FMC_SDTR1_TWR_0                    0x00010000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TWR_1                    0x00020000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TWR_2                    0x00040000U        /*!<Bit 2 */
-
-#define  FMC_SDTR1_TRP                      0x00F00000U        /*!<TRP[2:0] bits (Row precharge delay) */
-#define  FMC_SDTR1_TRP_0                    0x00100000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRP_1                    0x00200000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRP_2                    0x00400000U        /*!<Bit 2 */
-
-#define  FMC_SDTR1_TRCD                     0x0F000000U        /*!<TRP[2:0] bits (Row to column delay) */
-#define  FMC_SDTR1_TRCD_0                   0x01000000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRCD_1                   0x02000000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRCD_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for FMC_SDTR2 register  ******************/
-#define  FMC_SDTR2_TMRD                     0x0000000FU        /*!<TMRD[3:0] bits (Load mode register to active) */
-#define  FMC_SDTR2_TMRD_0                   0x00000001U        /*!<Bit 0 */
-#define  FMC_SDTR2_TMRD_1                   0x00000002U        /*!<Bit 1 */
-#define  FMC_SDTR2_TMRD_2                   0x00000004U        /*!<Bit 2 */
-#define  FMC_SDTR2_TMRD_3                   0x00000008U        /*!<Bit 3 */
-                                            
-#define  FMC_SDTR2_TXSR                     0x000000F0U        /*!<TXSR[3:0] bits (Exit self refresh) */
-#define  FMC_SDTR2_TXSR_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDTR2_TXSR_1                   0x00000020U        /*!<Bit 1 */
-#define  FMC_SDTR2_TXSR_2                   0x00000040U        /*!<Bit 2 */
-#define  FMC_SDTR2_TXSR_3                   0x00000080U        /*!<Bit 3 */
-
-#define  FMC_SDTR2_TRAS                     0x00000F00U        /*!<TRAS[3:0] bits (Self refresh time) */
-#define  FMC_SDTR2_TRAS_0                   0x00000100U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRAS_1                   0x00000200U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRAS_2                   0x00000400U        /*!<Bit 2 */
-#define  FMC_SDTR2_TRAS_3                   0x00000800U        /*!<Bit 3 */
-
-#define  FMC_SDTR2_TRC                      0x0000F000U        /*!<TRC[2:0] bits (Row cycle delay) */
-#define  FMC_SDTR2_TRC_0                    0x00001000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRC_1                    0x00002000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRC_2                    0x00004000U        /*!<Bit 2 */
-
-#define  FMC_SDTR2_TWR                      0x000F0000U        /*!<TRC[2:0] bits (Write recovery delay) */
-#define  FMC_SDTR2_TWR_0                    0x00010000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TWR_1                    0x00020000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TWR_2                    0x00040000U        /*!<Bit 2 */
-
-#define  FMC_SDTR2_TRP                      0x00F00000U        /*!<TRP[2:0] bits (Row precharge delay) */
-#define  FMC_SDTR2_TRP_0                    0x00100000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRP_1                    0x00200000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRP_2                    0x00400000U        /*!<Bit 2 */
-
-#define  FMC_SDTR2_TRCD                     0x0F000000U        /*!<TRP[2:0] bits (Row to column delay) */
-#define  FMC_SDTR2_TRCD_0                   0x01000000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRCD_1                   0x02000000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRCD_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for FMC_SDCMR register  ******************/
-#define  FMC_SDCMR_MODE                     0x00000007U        /*!<MODE[2:0] bits (Command mode) */
-#define  FMC_SDCMR_MODE_0                   0x00000001U        /*!<Bit 0 */
-#define  FMC_SDCMR_MODE_1                   0x00000002U        /*!<Bit 1 */
-#define  FMC_SDCMR_MODE_2                   0x00000004U        /*!<Bit 2 */
-                                            
-#define  FMC_SDCMR_CTB2                     0x00000008U        /*!<Command target 2 */
-
-#define  FMC_SDCMR_CTB1                     0x00000010U        /*!<Command target 1 */
-
-#define  FMC_SDCMR_NRFS                     0x000001E0U        /*!<NRFS[3:0] bits (Number of auto-refresh) */
-#define  FMC_SDCMR_NRFS_0                   0x00000020U        /*!<Bit 0 */
-#define  FMC_SDCMR_NRFS_1                   0x00000040U        /*!<Bit 1 */
-#define  FMC_SDCMR_NRFS_2                   0x00000080U        /*!<Bit 2 */
-#define  FMC_SDCMR_NRFS_3                   0x00000100U        /*!<Bit 3 */
-
-#define  FMC_SDCMR_MRD                      0x003FFE00U        /*!<MRD[12:0] bits (Mode register definition) */
-
-/******************  Bit definition for FMC_SDRTR register  ******************/
-#define  FMC_SDRTR_CRE                      0x00000001U        /*!<Clear refresh error flag */
-
-#define  FMC_SDRTR_COUNT                    0x00003FFEU        /*!<COUNT[12:0] bits (Refresh timer count) */
-
-#define  FMC_SDRTR_REIE                     0x00004000U        /*!<RES interupt enable */
-
-/******************  Bit definition for FMC_SDSR register  ******************/
-#define  FMC_SDSR_RE                        0x00000001U        /*!<Refresh error flag */
-
-#define  FMC_SDSR_MODES1                    0x00000006U        /*!<MODES1[1:0]bits (Status mode for bank 1) */
-#define  FMC_SDSR_MODES1_0                  0x00000002U        /*!<Bit 0 */
-#define  FMC_SDSR_MODES1_1                  0x00000004U        /*!<Bit 1 */
-
-#define  FMC_SDSR_MODES2                    0x00000018U        /*!<MODES2[1:0]bits (Status mode for bank 2) */
-#define  FMC_SDSR_MODES2_0                  0x00000008U        /*!<Bit 0 */
-#define  FMC_SDSR_MODES2_1                  0x00000010U        /*!<Bit 1 */
-#define  FMC_SDSR_BUSY                      0x00000020U        /*!<Busy status */
-
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    0x00000003U
-#define GPIO_MODER_MODER0_0                  0x00000001U
-#define GPIO_MODER_MODER0_1                  0x00000002U
-
-#define GPIO_MODER_MODER1                    0x0000000CU
-#define GPIO_MODER_MODER1_0                  0x00000004U
-#define GPIO_MODER_MODER1_1                  0x00000008U
-
-#define GPIO_MODER_MODER2                    0x00000030U
-#define GPIO_MODER_MODER2_0                  0x00000010U
-#define GPIO_MODER_MODER2_1                  0x00000020U
-
-#define GPIO_MODER_MODER3                    0x000000C0U
-#define GPIO_MODER_MODER3_0                  0x00000040U
-#define GPIO_MODER_MODER3_1                  0x00000080U
-
-#define GPIO_MODER_MODER4                    0x00000300U
-#define GPIO_MODER_MODER4_0                  0x00000100U
-#define GPIO_MODER_MODER4_1                  0x00000200U
-
-#define GPIO_MODER_MODER5                    0x00000C00U
-#define GPIO_MODER_MODER5_0                  0x00000400U
-#define GPIO_MODER_MODER5_1                  0x00000800U
-
-#define GPIO_MODER_MODER6                    0x00003000U
-#define GPIO_MODER_MODER6_0                  0x00001000U
-#define GPIO_MODER_MODER6_1                  0x00002000U
-
-#define GPIO_MODER_MODER7                    0x0000C000U
-#define GPIO_MODER_MODER7_0                  0x00004000U
-#define GPIO_MODER_MODER7_1                  0x00008000U
-
-#define GPIO_MODER_MODER8                    0x00030000U
-#define GPIO_MODER_MODER8_0                  0x00010000U
-#define GPIO_MODER_MODER8_1                  0x00020000U
-
-#define GPIO_MODER_MODER9                    0x000C0000U
-#define GPIO_MODER_MODER9_0                  0x00040000U
-#define GPIO_MODER_MODER9_1                  0x00080000U
-
-#define GPIO_MODER_MODER10                   0x00300000U
-#define GPIO_MODER_MODER10_0                 0x00100000U
-#define GPIO_MODER_MODER10_1                 0x00200000U
-
-#define GPIO_MODER_MODER11                   0x00C00000U
-#define GPIO_MODER_MODER11_0                 0x00400000U
-#define GPIO_MODER_MODER11_1                 0x00800000U
-
-#define GPIO_MODER_MODER12                   0x03000000U
-#define GPIO_MODER_MODER12_0                 0x01000000U
-#define GPIO_MODER_MODER12_1                 0x02000000U
-
-#define GPIO_MODER_MODER13                   0x0C000000U
-#define GPIO_MODER_MODER13_0                 0x04000000U
-#define GPIO_MODER_MODER13_1                 0x08000000U
-
-#define GPIO_MODER_MODER14                   0x30000000U
-#define GPIO_MODER_MODER14_0                 0x10000000U
-#define GPIO_MODER_MODER14_1                 0x20000000U
-
-#define GPIO_MODER_MODER15                   0xC0000000U
-#define GPIO_MODER_MODER15_0                 0x40000000U
-#define GPIO_MODER_MODER15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     0x00000001U
-#define GPIO_OTYPER_OT_1                     0x00000002U
-#define GPIO_OTYPER_OT_2                     0x00000004U
-#define GPIO_OTYPER_OT_3                     0x00000008U
-#define GPIO_OTYPER_OT_4                     0x00000010U
-#define GPIO_OTYPER_OT_5                     0x00000020U
-#define GPIO_OTYPER_OT_6                     0x00000040U
-#define GPIO_OTYPER_OT_7                     0x00000080U
-#define GPIO_OTYPER_OT_8                     0x00000100U
-#define GPIO_OTYPER_OT_9                     0x00000200U
-#define GPIO_OTYPER_OT_10                    0x00000400U
-#define GPIO_OTYPER_OT_11                    0x00000800U
-#define GPIO_OTYPER_OT_12                    0x00001000U
-#define GPIO_OTYPER_OT_13                    0x00002000U
-#define GPIO_OTYPER_OT_14                    0x00004000U
-#define GPIO_OTYPER_OT_15                    0x00008000U
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
-#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
-#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
-
-#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
-#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
-#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
-
-#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
-#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
-#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
-
-#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
-#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
-#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
-
-#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
-#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
-#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
-
-#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
-#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
-#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
-
-#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
-#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
-#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
-
-#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
-#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
-#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
-
-#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
-#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
-#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
-
-#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
-#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
-#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
-
-#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
-#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
-#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
-
-#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
-#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
-#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
-
-#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
-#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
-#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
-
-#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
-#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
-#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
-
-#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
-#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
-#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
-
-#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
-#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
-#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    0x00000003U
-#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
-#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
-
-#define GPIO_PUPDR_PUPDR1                    0x0000000CU
-#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
-#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
-
-#define GPIO_PUPDR_PUPDR2                    0x00000030U
-#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
-#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
-
-#define GPIO_PUPDR_PUPDR3                    0x000000C0U
-#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
-#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
-
-#define GPIO_PUPDR_PUPDR4                    0x00000300U
-#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
-#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
-
-#define GPIO_PUPDR_PUPDR5                    0x00000C00U
-#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
-#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
-
-#define GPIO_PUPDR_PUPDR6                    0x00003000U
-#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
-#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
-
-#define GPIO_PUPDR_PUPDR7                    0x0000C000U
-#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
-#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
-
-#define GPIO_PUPDR_PUPDR8                    0x00030000U
-#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
-#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
-
-#define GPIO_PUPDR_PUPDR9                    0x000C0000U
-#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
-#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
-
-#define GPIO_PUPDR_PUPDR10                   0x00300000U
-#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
-#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
-
-#define GPIO_PUPDR_PUPDR11                   0x00C00000U
-#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
-#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
-
-#define GPIO_PUPDR_PUPDR12                   0x03000000U
-#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
-#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
-
-#define GPIO_PUPDR_PUPDR13                   0x0C000000U
-#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
-#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
-
-#define GPIO_PUPDR_PUPDR14                   0x30000000U
-#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
-#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
-
-#define GPIO_PUPDR_PUPDR15                   0xC0000000U
-#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
-#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       0x00000001U
-#define GPIO_IDR_IDR_1                       0x00000002U
-#define GPIO_IDR_IDR_2                       0x00000004U
-#define GPIO_IDR_IDR_3                       0x00000008U
-#define GPIO_IDR_IDR_4                       0x00000010U
-#define GPIO_IDR_IDR_5                       0x00000020U
-#define GPIO_IDR_IDR_6                       0x00000040U
-#define GPIO_IDR_IDR_7                       0x00000080U
-#define GPIO_IDR_IDR_8                       0x00000100U
-#define GPIO_IDR_IDR_9                       0x00000200U
-#define GPIO_IDR_IDR_10                      0x00000400U
-#define GPIO_IDR_IDR_11                      0x00000800U
-#define GPIO_IDR_IDR_12                      0x00001000U
-#define GPIO_IDR_IDR_13                      0x00002000U
-#define GPIO_IDR_IDR_14                      0x00004000U
-#define GPIO_IDR_IDR_15                      0x00008000U
-/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
-#define GPIO_OTYPER_IDR_0                    GPIO_IDR_IDR_0
-#define GPIO_OTYPER_IDR_1                    GPIO_IDR_IDR_1
-#define GPIO_OTYPER_IDR_2                    GPIO_IDR_IDR_2
-#define GPIO_OTYPER_IDR_3                    GPIO_IDR_IDR_3
-#define GPIO_OTYPER_IDR_4                    GPIO_IDR_IDR_4
-#define GPIO_OTYPER_IDR_5                    GPIO_IDR_IDR_5
-#define GPIO_OTYPER_IDR_6                    GPIO_IDR_IDR_6
-#define GPIO_OTYPER_IDR_7                    GPIO_IDR_IDR_7
-#define GPIO_OTYPER_IDR_8                    GPIO_IDR_IDR_8
-#define GPIO_OTYPER_IDR_9                    GPIO_IDR_IDR_9
-#define GPIO_OTYPER_IDR_10                   GPIO_IDR_IDR_10
-#define GPIO_OTYPER_IDR_11                   GPIO_IDR_IDR_11
-#define GPIO_OTYPER_IDR_12                   GPIO_IDR_IDR_12
-#define GPIO_OTYPER_IDR_13                   GPIO_IDR_IDR_13
-#define GPIO_OTYPER_IDR_14                   GPIO_IDR_IDR_14
-#define GPIO_OTYPER_IDR_15                   GPIO_IDR_IDR_15
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       0x00000001U
-#define GPIO_ODR_ODR_1                       0x00000002U
-#define GPIO_ODR_ODR_2                       0x00000004U
-#define GPIO_ODR_ODR_3                       0x00000008U
-#define GPIO_ODR_ODR_4                       0x00000010U
-#define GPIO_ODR_ODR_5                       0x00000020U
-#define GPIO_ODR_ODR_6                       0x00000040U
-#define GPIO_ODR_ODR_7                       0x00000080U
-#define GPIO_ODR_ODR_8                       0x00000100U
-#define GPIO_ODR_ODR_9                       0x00000200U
-#define GPIO_ODR_ODR_10                      0x00000400U
-#define GPIO_ODR_ODR_11                      0x00000800U
-#define GPIO_ODR_ODR_12                      0x00001000U
-#define GPIO_ODR_ODR_13                      0x00002000U
-#define GPIO_ODR_ODR_14                      0x00004000U
-#define GPIO_ODR_ODR_15                      0x00008000U
-/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
-#define GPIO_OTYPER_ODR_0                    GPIO_ODR_ODR_0
-#define GPIO_OTYPER_ODR_1                    GPIO_ODR_ODR_1
-#define GPIO_OTYPER_ODR_2                    GPIO_ODR_ODR_2
-#define GPIO_OTYPER_ODR_3                    GPIO_ODR_ODR_3
-#define GPIO_OTYPER_ODR_4                    GPIO_ODR_ODR_4
-#define GPIO_OTYPER_ODR_5                    GPIO_ODR_ODR_5
-#define GPIO_OTYPER_ODR_6                    GPIO_ODR_ODR_6
-#define GPIO_OTYPER_ODR_7                    GPIO_ODR_ODR_7
-#define GPIO_OTYPER_ODR_8                    GPIO_ODR_ODR_8
-#define GPIO_OTYPER_ODR_9                    GPIO_ODR_ODR_9
-#define GPIO_OTYPER_ODR_10                   GPIO_ODR_ODR_10
-#define GPIO_OTYPER_ODR_11                   GPIO_ODR_ODR_11
-#define GPIO_OTYPER_ODR_12                   GPIO_ODR_ODR_12
-#define GPIO_OTYPER_ODR_13                   GPIO_ODR_ODR_13
-#define GPIO_OTYPER_ODR_14                   GPIO_ODR_ODR_14
-#define GPIO_OTYPER_ODR_15                   GPIO_ODR_ODR_15
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       0x00000001U
-#define GPIO_BSRR_BS_1                       0x00000002U
-#define GPIO_BSRR_BS_2                       0x00000004U
-#define GPIO_BSRR_BS_3                       0x00000008U
-#define GPIO_BSRR_BS_4                       0x00000010U
-#define GPIO_BSRR_BS_5                       0x00000020U
-#define GPIO_BSRR_BS_6                       0x00000040U
-#define GPIO_BSRR_BS_7                       0x00000080U
-#define GPIO_BSRR_BS_8                       0x00000100U
-#define GPIO_BSRR_BS_9                       0x00000200U
-#define GPIO_BSRR_BS_10                      0x00000400U
-#define GPIO_BSRR_BS_11                      0x00000800U
-#define GPIO_BSRR_BS_12                      0x00001000U
-#define GPIO_BSRR_BS_13                      0x00002000U
-#define GPIO_BSRR_BS_14                      0x00004000U
-#define GPIO_BSRR_BS_15                      0x00008000U
-#define GPIO_BSRR_BR_0                       0x00010000U
-#define GPIO_BSRR_BR_1                       0x00020000U
-#define GPIO_BSRR_BR_2                       0x00040000U
-#define GPIO_BSRR_BR_3                       0x00080000U
-#define GPIO_BSRR_BR_4                       0x00100000U
-#define GPIO_BSRR_BR_5                       0x00200000U
-#define GPIO_BSRR_BR_6                       0x00400000U
-#define GPIO_BSRR_BR_7                       0x00800000U
-#define GPIO_BSRR_BR_8                       0x01000000U
-#define GPIO_BSRR_BR_9                       0x02000000U
-#define GPIO_BSRR_BR_10                      0x04000000U
-#define GPIO_BSRR_BR_11                      0x08000000U
-#define GPIO_BSRR_BR_12                      0x10000000U
-#define GPIO_BSRR_BR_13                      0x20000000U
-#define GPIO_BSRR_BR_14                      0x40000000U
-#define GPIO_BSRR_BR_15                      0x80000000U
-
-/****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0                       0x00000001U
-#define GPIO_LCKR_LCK1                       0x00000002U
-#define GPIO_LCKR_LCK2                       0x00000004U
-#define GPIO_LCKR_LCK3                       0x00000008U
-#define GPIO_LCKR_LCK4                       0x00000010U
-#define GPIO_LCKR_LCK5                       0x00000020U
-#define GPIO_LCKR_LCK6                       0x00000040U
-#define GPIO_LCKR_LCK7                       0x00000080U
-#define GPIO_LCKR_LCK8                       0x00000100U
-#define GPIO_LCKR_LCK9                       0x00000200U
-#define GPIO_LCKR_LCK10                      0x00000400U
-#define GPIO_LCKR_LCK11                      0x00000800U
-#define GPIO_LCKR_LCK12                      0x00001000U
-#define GPIO_LCKR_LCK13                      0x00002000U
-#define GPIO_LCKR_LCK14                      0x00004000U
-#define GPIO_LCKR_LCK15                      0x00008000U
-#define GPIO_LCKR_LCKK                       0x00010000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Inter-integrated Circuit Interface                    */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          0x00000001U     /*!<Peripheral Enable                             */
-#define  I2C_CR1_SMBUS                       0x00000002U     /*!<SMBus Mode                                    */
-#define  I2C_CR1_SMBTYPE                     0x00000008U     /*!<SMBus Type                                    */
-#define  I2C_CR1_ENARP                       0x00000010U     /*!<ARP Enable                                    */
-#define  I2C_CR1_ENPEC                       0x00000020U     /*!<PEC Enable                                    */
-#define  I2C_CR1_ENGC                        0x00000040U     /*!<General Call Enable                           */
-#define  I2C_CR1_NOSTRETCH                   0x00000080U     /*!<Clock Stretching Disable (Slave mode)  */
-#define  I2C_CR1_START                       0x00000100U     /*!<Start Generation                              */
-#define  I2C_CR1_STOP                        0x00000200U     /*!<Stop Generation                               */
-#define  I2C_CR1_ACK                         0x00000400U     /*!<Acknowledge Enable                            */
-#define  I2C_CR1_POS                         0x00000800U     /*!<Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         0x00001000U     /*!<Packet Error Checking                         */
-#define  I2C_CR1_ALERT                       0x00002000U     /*!<SMBus Alert                                   */
-#define  I2C_CR1_SWRST                       0x00008000U     /*!<Software Reset                                */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        0x0000003FU     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
-#define  I2C_CR2_FREQ_0                      0x00000001U     /*!<Bit 0 */
-#define  I2C_CR2_FREQ_1                      0x00000002U     /*!<Bit 1 */
-#define  I2C_CR2_FREQ_2                      0x00000004U     /*!<Bit 2 */
-#define  I2C_CR2_FREQ_3                      0x00000008U     /*!<Bit 3 */
-#define  I2C_CR2_FREQ_4                      0x00000010U     /*!<Bit 4 */
-#define  I2C_CR2_FREQ_5                      0x00000020U     /*!<Bit 5 */
-
-#define  I2C_CR2_ITERREN                     0x00000100U     /*!<Error Interrupt Enable  */
-#define  I2C_CR2_ITEVTEN                     0x00000200U     /*!<Event Interrupt Enable  */
-#define  I2C_CR2_ITBUFEN                     0x00000400U     /*!<Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       0x00000800U     /*!<DMA Requests Enable     */
-#define  I2C_CR2_LAST                        0x00001000U     /*!<DMA Last Transfer       */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     0x000000FEU     /*!<Interface Address */
-#define  I2C_OAR1_ADD8_9                     0x00000300U     /*!<Interface Address */
-
-#define  I2C_OAR1_ADD0                       0x00000001U     /*!<Bit 0 */
-#define  I2C_OAR1_ADD1                       0x00000002U     /*!<Bit 1 */
-#define  I2C_OAR1_ADD2                       0x00000004U     /*!<Bit 2 */
-#define  I2C_OAR1_ADD3                       0x00000008U     /*!<Bit 3 */
-#define  I2C_OAR1_ADD4                       0x00000010U     /*!<Bit 4 */
-#define  I2C_OAR1_ADD5                       0x00000020U     /*!<Bit 5 */
-#define  I2C_OAR1_ADD6                       0x00000040U     /*!<Bit 6 */
-#define  I2C_OAR1_ADD7                       0x00000080U     /*!<Bit 7 */
-#define  I2C_OAR1_ADD8                       0x00000100U     /*!<Bit 8 */
-#define  I2C_OAR1_ADD9                       0x00000200U     /*!<Bit 9 */
-
-#define  I2C_OAR1_ADDMODE                    0x00008000U     /*!<Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     0x00000001U        /*!<Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       0x000000FEU        /*!<Interface address           */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           0x000000FFU        /*!<8-bit Data Register         */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          0x00000001U     /*!<Start Bit (Master mode)                  */
-#define  I2C_SR1_ADDR                        0x00000002U     /*!<Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         0x00000004U     /*!<Byte Transfer Finished                          */
-#define  I2C_SR1_ADD10                       0x00000008U     /*!<10-bit header sent (Master mode)         */
-#define  I2C_SR1_STOPF                       0x00000010U     /*!<Stop detection (Slave mode)              */
-#define  I2C_SR1_RXNE                        0x00000040U     /*!<Data Register not Empty (receivers)      */
-#define  I2C_SR1_TXE                         0x00000080U     /*!<Data Register Empty (transmitters)       */
-#define  I2C_SR1_BERR                        0x00000100U     /*!<Bus Error                                       */
-#define  I2C_SR1_ARLO                        0x00000200U     /*!<Arbitration Lost (master mode)           */
-#define  I2C_SR1_AF                          0x00000400U     /*!<Acknowledge Failure                             */
-#define  I2C_SR1_OVR                         0x00000800U     /*!<Overrun/Underrun                                */
-#define  I2C_SR1_PECERR                      0x00001000U     /*!<PEC Error in reception                          */
-#define  I2C_SR1_TIMEOUT                     0x00004000U     /*!<Timeout or Tlow Error                           */
-#define  I2C_SR1_SMBALERT                    0x00008000U     /*!<SMBus Alert                                     */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         0x00000001U     /*!<Master/Slave                              */
-#define  I2C_SR2_BUSY                        0x00000002U     /*!<Bus Busy                                  */
-#define  I2C_SR2_TRA                         0x00000004U     /*!<Transmitter/Receiver                      */
-#define  I2C_SR2_GENCALL                     0x00000010U     /*!<General Call Address (Slave mode)  */
-#define  I2C_SR2_SMBDEFAULT                  0x00000020U     /*!<SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     0x00000040U     /*!<SMBus Host Header (Slave mode)     */
-#define  I2C_SR2_DUALF                       0x00000080U     /*!<Dual Flag (Slave mode)             */
-#define  I2C_SR2_PEC                         0x0000FF00U     /*!<Packet Error Checking Register            */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         0x00000FFFU     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        0x00004000U     /*!<Fast Mode Duty Cycle                                       */
-#define  I2C_CCR_FS                          0x00008000U     /*!<I2C Master Mode Selection                                  */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     0x0000003FU     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************  Bit definition for I2C_FLTR register  *******************/
-#define  I2C_FLTR_DNF                        0x0000000FU     /*!<Digital Noise Filter */
-#define  I2C_FLTR_ANOFF                      0x00000010U     /*!<Analog Noise Filter OFF */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Independent WATCHDOG                             */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         0x01U               /*!<Watchdog prescaler value update      */
-#define  IWDG_SR_RVU                         0x02U               /*!<Watchdog counter reload value update */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                      LCD-TFT Display Controller (LTDC)                     */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for LTDC_SSCR register  *****************/
-
-#define LTDC_SSCR_VSH                       0x000007FFU              /*!< Vertical Synchronization Height */
-#define LTDC_SSCR_HSW                       0x0FFF0000U              /*!< Horizontal Synchronization Width */
-
-/********************  Bit definition for LTDC_BPCR register  *****************/
-
-#define LTDC_BPCR_AVBP                      0x000007FFU              /*!< Accumulated Vertical Back Porch */
-#define LTDC_BPCR_AHBP                      0x0FFF0000U              /*!< Accumulated Horizontal Back Porch */
-
-/********************  Bit definition for LTDC_AWCR register  *****************/
-
-#define LTDC_AWCR_AAH                       0x000007FFU              /*!< Accumulated Active heigh */
-#define LTDC_AWCR_AAW                       0x0FFF0000U              /*!< Accumulated Active Width */
-
-/********************  Bit definition for LTDC_TWCR register  *****************/
-
-#define LTDC_TWCR_TOTALH                    0x000007FFU              /*!< Total Heigh */
-#define LTDC_TWCR_TOTALW                    0x0FFF0000U              /*!< Total Width */
-
-/********************  Bit definition for LTDC_GCR register  ******************/
-
-#define LTDC_GCR_LTDCEN                     0x00000001U              /*!< LCD-TFT controller enable bit */
-#define LTDC_GCR_DBW                        0x00000070U              /*!< Dither Blue Width */
-#define LTDC_GCR_DGW                        0x00000700U              /*!< Dither Green Width */
-#define LTDC_GCR_DRW                        0x00007000U              /*!< Dither Red Width */
-#define LTDC_GCR_DEN                        0x00010000U              /*!< Dither Enable */
-#define LTDC_GCR_PCPOL                      0x10000000U              /*!< Pixel Clock Polarity */
-#define LTDC_GCR_DEPOL                      0x20000000U              /*!< Data Enable Polarity */
-#define LTDC_GCR_VSPOL                      0x40000000U              /*!< Vertical Synchronization Polarity */
-#define LTDC_GCR_HSPOL                      0x80000000U              /*!< Horizontal Synchronization Polarity */
-
-/* Legacy defines */
-#define LTDC_GCR_DTEN                       LTDC_GCR_DEN
-
-/********************  Bit definition for LTDC_SRCR register  *****************/
-
-#define LTDC_SRCR_IMR                      0x00000001U               /*!< Immediate Reload */
-#define LTDC_SRCR_VBR                      0x00000002U               /*!< Vertical Blanking Reload */
-
-/********************  Bit definition for LTDC_BCCR register  *****************/
-
-#define LTDC_BCCR_BCBLUE                    0x000000FFU              /*!< Background Blue value */
-#define LTDC_BCCR_BCGREEN                   0x0000FF00U              /*!< Background Green value */
-#define LTDC_BCCR_BCRED                     0x00FF0000U              /*!< Background Red value */
-
-/********************  Bit definition for LTDC_IER register  ******************/
-
-#define LTDC_IER_LIE                        0x00000001U              /*!< Line Interrupt Enable */
-#define LTDC_IER_FUIE                       0x00000002U              /*!< FIFO Underrun Interrupt Enable */
-#define LTDC_IER_TERRIE                     0x00000004U              /*!< Transfer Error Interrupt Enable */
-#define LTDC_IER_RRIE                       0x00000008U              /*!< Register Reload interrupt enable */
-
-/********************  Bit definition for LTDC_ISR register  ******************/
-
-#define LTDC_ISR_LIF                        0x00000001U              /*!< Line Interrupt Flag */
-#define LTDC_ISR_FUIF                       0x00000002U              /*!< FIFO Underrun Interrupt Flag */
-#define LTDC_ISR_TERRIF                     0x00000004U              /*!< Transfer Error Interrupt Flag */
-#define LTDC_ISR_RRIF                       0x00000008U              /*!< Register Reload interrupt Flag */
-
-/********************  Bit definition for LTDC_ICR register  ******************/
-
-#define LTDC_ICR_CLIF                       0x00000001U              /*!< Clears the Line Interrupt Flag */
-#define LTDC_ICR_CFUIF                      0x00000002U              /*!< Clears the FIFO Underrun Interrupt Flag */
-#define LTDC_ICR_CTERRIF                    0x00000004U              /*!< Clears the Transfer Error Interrupt Flag */
-#define LTDC_ICR_CRRIF                      0x00000008U              /*!< Clears Register Reload interrupt Flag */
-
-/********************  Bit definition for LTDC_LIPCR register  ****************/
-
-#define LTDC_LIPCR_LIPOS                    0x000007FFU              /*!< Line Interrupt Position */
-
-/********************  Bit definition for LTDC_CPSR register  *****************/
-
-#define LTDC_CPSR_CYPOS                     0x0000FFFFU              /*!< Current Y Position */
-#define LTDC_CPSR_CXPOS                     0xFFFF0000U              /*!< Current X Position */
-
-/********************  Bit definition for LTDC_CDSR register  *****************/
-
-#define LTDC_CDSR_VDES                      0x00000001U              /*!< Vertical Data Enable Status */
-#define LTDC_CDSR_HDES                      0x00000002U              /*!< Horizontal Data Enable Status */
-#define LTDC_CDSR_VSYNCS                    0x00000004U              /*!< Vertical Synchronization Status */
-#define LTDC_CDSR_HSYNCS                    0x00000008U              /*!< Horizontal Synchronization Status */
-
-/********************  Bit definition for LTDC_LxCR register  *****************/
-
-#define LTDC_LxCR_LEN                       0x00000001U              /*!< Layer Enable */
-#define LTDC_LxCR_COLKEN                    0x00000002U              /*!< Color Keying Enable */
-#define LTDC_LxCR_CLUTEN                    0x00000010U              /*!< Color Lockup Table Enable */
-
-/********************  Bit definition for LTDC_LxWHPCR register  **************/
-
-#define LTDC_LxWHPCR_WHSTPOS                0x00000FFFU              /*!< Window Horizontal Start Position */
-#define LTDC_LxWHPCR_WHSPPOS                0xFFFF0000U              /*!< Window Horizontal Stop Position */
-
-/********************  Bit definition for LTDC_LxWVPCR register  **************/
-
-#define LTDC_LxWVPCR_WVSTPOS                0x00000FFFU              /*!< Window Vertical Start Position */
-#define LTDC_LxWVPCR_WVSPPOS                0xFFFF0000U              /*!< Window Vertical Stop Position */
-
-/********************  Bit definition for LTDC_LxCKCR register  ***************/
-
-#define LTDC_LxCKCR_CKBLUE                  0x000000FFU              /*!< Color Key Blue value */
-#define LTDC_LxCKCR_CKGREEN                 0x0000FF00U              /*!< Color Key Green value */
-#define LTDC_LxCKCR_CKRED                   0x00FF0000U              /*!< Color Key Red value */
-
-/********************  Bit definition for LTDC_LxPFCR register  ***************/
-
-#define LTDC_LxPFCR_PF                      0x00000007U              /*!< Pixel Format */
-
-/********************  Bit definition for LTDC_LxCACR register  ***************/
-
-#define LTDC_LxCACR_CONSTA                  0x000000FFU              /*!< Constant Alpha */
-
-/********************  Bit definition for LTDC_LxDCCR register  ***************/
-
-#define LTDC_LxDCCR_DCBLUE                  0x000000FFU              /*!< Default Color Blue */
-#define LTDC_LxDCCR_DCGREEN                 0x0000FF00U              /*!< Default Color Green */
-#define LTDC_LxDCCR_DCRED                   0x00FF0000U              /*!< Default Color Red */
-#define LTDC_LxDCCR_DCALPHA                 0xFF000000U              /*!< Default Color Alpha */
-                                
-/********************  Bit definition for LTDC_LxBFCR register  ***************/
-
-#define LTDC_LxBFCR_BF2                     0x00000007U              /*!< Blending Factor 2 */
-#define LTDC_LxBFCR_BF1                     0x00000700U              /*!< Blending Factor 1 */
-
-/********************  Bit definition for LTDC_LxCFBAR register  **************/
-
-#define LTDC_LxCFBAR_CFBADD                 0xFFFFFFFFU              /*!< Color Frame Buffer Start Address */
-
-/********************  Bit definition for LTDC_LxCFBLR register  **************/
-
-#define LTDC_LxCFBLR_CFBLL                  0x00001FFFU              /*!< Color Frame Buffer Line Length */
-#define LTDC_LxCFBLR_CFBP                   0x1FFF0000U              /*!< Color Frame Buffer Pitch in bytes */
-
-/********************  Bit definition for LTDC_LxCFBLNR register  *************/
-
-#define LTDC_LxCFBLNR_CFBLNBR               0x000007FFU              /*!< Frame Buffer Line Number */
-
-/********************  Bit definition for LTDC_LxCLUTWR register  *************/
-
-#define LTDC_LxCLUTWR_BLUE                  0x000000FFU              /*!< Blue value */
-#define LTDC_LxCLUTWR_GREEN                 0x0000FF00U              /*!< Green value */
-#define LTDC_LxCLUTWR_RED                   0x00FF0000U              /*!< Red value */
-#define LTDC_LxCLUTWR_CLUTADD               0xFF000000U              /*!< CLUT address */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                             Power Control                                  */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
-#define  PWR_CR_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
-#define  PWR_CR_CWUF                         0x00000004U     /*!< Clear Wakeup Flag                   */
-#define  PWR_CR_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
-#define  PWR_CR_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
-
-#define  PWR_CR_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        0x00000020U     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        0x00000040U     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        0x00000080U     /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
-#define  PWR_CR_DBP                          0x00000100U     /*!< Disable Backup Domain write protection                     */
-#define  PWR_CR_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                              */
-#define  PWR_CR_LPLVDS                       0x00000400U     /*!< Low-Power Regulator Low Voltage Scaling in Stop mode       */
-#define  PWR_CR_MRLVDS                       0x00000800U     /*!< Main regulator Low Voltage Scaling in Stop mode            */
-#define  PWR_CR_ADCDC1                       0x00002000U     /*!< Refer to AN4073 on how to use this bit */ 
-#define  PWR_CR_VOS                          0x0000C000U     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
-#define  PWR_CR_VOS_0                        0x00004000U     /*!< Bit 0 */
-#define  PWR_CR_VOS_1                        0x00008000U     /*!< Bit 1 */
-#define  PWR_CR_ODEN                         0x00010000U     /*!< Over Drive enable                   */
-#define  PWR_CR_ODSWEN                       0x00020000U     /*!< Over Drive switch enabled           */
-#define  PWR_CR_UDEN                         0x000C0000U     /*!< Under Drive enable in stop mode     */
-#define  PWR_CR_UDEN_0                       0x00040000U     /*!< Bit 0                               */
-#define  PWR_CR_UDEN_1                       0x00080000U     /*!< Bit 1                               */
-
-/* Legacy define */
-#define  PWR_CR_PMODE                        PWR_CR_VOS
-#define  PWR_CR_LPUDS                        PWR_CR_LPLVDS     /*!< Low-Power Regulator in deepsleep under-drive mode          */
-#define  PWR_CR_MRUDS                        PWR_CR_MRLVDS     /*!< Main regulator in deepsleep under-drive mode               */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         0x00000001U     /*!< Wakeup Flag                                      */
-#define  PWR_CSR_SBF                         0x00000002U     /*!< Standby Flag                                     */
-#define  PWR_CSR_PVDO                        0x00000004U     /*!< PVD Output                                       */
-#define  PWR_CSR_BRR                         0x00000008U     /*!< Backup regulator ready                           */
-#define  PWR_CSR_EWUP                        0x00000100U     /*!< Enable WKUP pin                                  */
-#define  PWR_CSR_BRE                         0x00000200U     /*!< Backup regulator enable                          */
-#define  PWR_CSR_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
-#define  PWR_CSR_ODRDY                       0x00010000U     /*!< Over Drive generator ready                       */
-#define  PWR_CSR_ODSWRDY                     0x00020000U     /*!< Over Drive Switch ready                          */
-#define  PWR_CSR_UDSWRDY                     0x000C0000U     /*!< Under Drive ready                                */
-
-/* Legacy define */
-#define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        0x00000001U
-#define  RCC_CR_HSIRDY                       0x00000002U
-
-#define  RCC_CR_HSITRIM                      0x000000F8U
-#define  RCC_CR_HSITRIM_0                    0x00000008U/*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    0x00000010U/*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    0x00000020U/*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    0x00000040U/*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    0x00000080U/*!<Bit 4 */
-
-#define  RCC_CR_HSICAL                       0x0000FF00U
-#define  RCC_CR_HSICAL_0                     0x00000100U/*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     0x00000200U/*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     0x00000400U/*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     0x00000800U/*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     0x00001000U/*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     0x00002000U/*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     0x00004000U/*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     0x00008000U/*!<Bit 7 */
-
-#define  RCC_CR_HSEON                        0x00010000U
-#define  RCC_CR_HSERDY                       0x00020000U
-#define  RCC_CR_HSEBYP                       0x00040000U
-#define  RCC_CR_CSSON                        0x00080000U
-#define  RCC_CR_PLLON                        0x01000000U
-#define  RCC_CR_PLLRDY                       0x02000000U
-#define  RCC_CR_PLLI2SON                     0x04000000U
-#define  RCC_CR_PLLI2SRDY                    0x08000000U
-#define  RCC_CR_PLLSAION                     0x10000000U
-#define  RCC_CR_PLLSAIRDY                    0x20000000U
-
-/********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    0x0000003FU
-#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
-#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
-#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
-#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
-#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
-#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
-
-#define  RCC_PLLCFGR_PLLN                     0x00007FC0U
-#define  RCC_PLLCFGR_PLLN_0                   0x00000040U
-#define  RCC_PLLCFGR_PLLN_1                   0x00000080U
-#define  RCC_PLLCFGR_PLLN_2                   0x00000100U
-#define  RCC_PLLCFGR_PLLN_3                   0x00000200U
-#define  RCC_PLLCFGR_PLLN_4                   0x00000400U
-#define  RCC_PLLCFGR_PLLN_5                   0x00000800U
-#define  RCC_PLLCFGR_PLLN_6                   0x00001000U
-#define  RCC_PLLCFGR_PLLN_7                   0x00002000U
-#define  RCC_PLLCFGR_PLLN_8                   0x00004000U
-
-#define  RCC_PLLCFGR_PLLP                    0x00030000U
-#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
-#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
-
-#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
-
-#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
-#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
-#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
-#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
-#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-/*!< SW configuration */
-#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
-
-#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
-
-#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
-
-#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
-
-/*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     0x001F0000U
-#define  RCC_CFGR_RTCPRE_0                   0x00010000U
-#define  RCC_CFGR_RTCPRE_1                   0x00020000U
-#define  RCC_CFGR_RTCPRE_2                   0x00040000U
-#define  RCC_CFGR_RTCPRE_3                   0x00080000U
-#define  RCC_CFGR_RTCPRE_4                   0x00100000U
-
-/*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       0x00600000U
-#define  RCC_CFGR_MCO1_0                     0x00200000U
-#define  RCC_CFGR_MCO1_1                     0x00400000U
-
-#define  RCC_CFGR_I2SSRC                     0x00800000U
-
-#define  RCC_CFGR_MCO1PRE                    0x07000000U
-#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
-#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
-#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
-
-#define  RCC_CFGR_MCO2PRE                    0x38000000U
-#define  RCC_CFGR_MCO2PRE_0                  0x08000000U
-#define  RCC_CFGR_MCO2PRE_1                  0x10000000U
-#define  RCC_CFGR_MCO2PRE_2                  0x20000000U
-
-#define  RCC_CFGR_MCO2                       0xC0000000U
-#define  RCC_CFGR_MCO2_0                     0x40000000U
-#define  RCC_CFGR_MCO2_1                     0x80000000U
-
-/********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     0x00000001U
-#define  RCC_CIR_LSERDYF                     0x00000002U
-#define  RCC_CIR_HSIRDYF                     0x00000004U
-#define  RCC_CIR_HSERDYF                     0x00000008U
-#define  RCC_CIR_PLLRDYF                     0x00000010U
-#define  RCC_CIR_PLLI2SRDYF                  0x00000020U
-#define  RCC_CIR_PLLSAIRDYF                  0x00000040U
-#define  RCC_CIR_CSSF                        0x00000080U
-#define  RCC_CIR_LSIRDYIE                    0x00000100U
-#define  RCC_CIR_LSERDYIE                    0x00000200U
-#define  RCC_CIR_HSIRDYIE                    0x00000400U
-#define  RCC_CIR_HSERDYIE                    0x00000800U
-#define  RCC_CIR_PLLRDYIE                    0x00001000U
-#define  RCC_CIR_PLLI2SRDYIE                 0x00002000U
-#define  RCC_CIR_PLLSAIRDYIE                 0x00004000U
-#define  RCC_CIR_LSIRDYC                     0x00010000U
-#define  RCC_CIR_LSERDYC                     0x00020000U
-#define  RCC_CIR_HSIRDYC                     0x00040000U
-#define  RCC_CIR_HSERDYC                     0x00080000U
-#define  RCC_CIR_PLLRDYC                     0x00100000U
-#define  RCC_CIR_PLLI2SRDYC                  0x00200000U
-#define  RCC_CIR_PLLSAIRDYC                  0x00400000U
-#define  RCC_CIR_CSSC                        0x00800000U
-
-/********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
-#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
-#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
-#define  RCC_AHB1RSTR_GPIODRST               0x00000008U
-#define  RCC_AHB1RSTR_GPIOERST               0x00000010U
-#define  RCC_AHB1RSTR_GPIOFRST               0x00000020U
-#define  RCC_AHB1RSTR_GPIOGRST               0x00000040U
-#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
-#define  RCC_AHB1RSTR_GPIOIRST               0x00000100U
-#define  RCC_AHB1RSTR_GPIOJRST               0x00000200U
-#define  RCC_AHB1RSTR_GPIOKRST               0x00000400U
-#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
-#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
-#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
-#define  RCC_AHB1RSTR_DMA2DRST               0x00800000U
-#define  RCC_AHB1RSTR_ETHMACRST              0x02000000U
-#define  RCC_AHB1RSTR_OTGHRST                0x20000000U
-
-/********************  Bit definition for RCC_AHB2RSTR register  **************/
-#define  RCC_AHB2RSTR_DCMIRST                0x00000001U
-#define  RCC_AHB2RSTR_RNGRST                 0x00000040U
-#define  RCC_AHB2RSTR_OTGFSRST               0x00000080U
-
-/********************  Bit definition for RCC_AHB3RSTR register  **************/
-#define  RCC_AHB3RSTR_FMCRST                0x00000001U
-
-/********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM2RST                0x00000001U
-#define  RCC_APB1RSTR_TIM3RST                0x00000002U
-#define  RCC_APB1RSTR_TIM4RST                0x00000004U
-#define  RCC_APB1RSTR_TIM5RST                0x00000008U
-#define  RCC_APB1RSTR_TIM6RST                0x00000010U
-#define  RCC_APB1RSTR_TIM7RST                0x00000020U
-#define  RCC_APB1RSTR_TIM12RST               0x00000040U
-#define  RCC_APB1RSTR_TIM13RST               0x00000080U
-#define  RCC_APB1RSTR_TIM14RST               0x00000100U
-#define  RCC_APB1RSTR_WWDGRST                0x00000800U
-#define  RCC_APB1RSTR_SPI2RST                0x00004000U
-#define  RCC_APB1RSTR_SPI3RST                0x00008000U
-#define  RCC_APB1RSTR_USART2RST              0x00020000U
-#define  RCC_APB1RSTR_USART3RST              0x00040000U
-#define  RCC_APB1RSTR_UART4RST               0x00080000U
-#define  RCC_APB1RSTR_UART5RST               0x00100000U
-#define  RCC_APB1RSTR_I2C1RST                0x00200000U
-#define  RCC_APB1RSTR_I2C2RST                0x00400000U
-#define  RCC_APB1RSTR_I2C3RST                0x00800000U
-#define  RCC_APB1RSTR_CAN1RST                0x02000000U
-#define  RCC_APB1RSTR_CAN2RST                0x04000000U
-#define  RCC_APB1RSTR_PWRRST                 0x10000000U
-#define  RCC_APB1RSTR_DACRST                 0x20000000U
-#define  RCC_APB1RSTR_UART7RST               0x40000000U
-#define  RCC_APB1RSTR_UART8RST               0x80000000U
-
-/********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                0x00000001U
-#define  RCC_APB2RSTR_TIM8RST                0x00000002U
-#define  RCC_APB2RSTR_USART1RST              0x00000010U
-#define  RCC_APB2RSTR_USART6RST              0x00000020U
-#define  RCC_APB2RSTR_ADCRST                 0x00000100U
-#define  RCC_APB2RSTR_SDIORST                0x00000800U
-#define  RCC_APB2RSTR_SPI1RST                0x00001000U
-#define  RCC_APB2RSTR_SPI4RST                0x00002000U
-#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
-#define  RCC_APB2RSTR_TIM9RST                0x00010000U
-#define  RCC_APB2RSTR_TIM10RST               0x00020000U
-#define  RCC_APB2RSTR_TIM11RST               0x00040000U
-#define  RCC_APB2RSTR_SPI5RST                0x00100000U
-#define  RCC_APB2RSTR_SPI6RST                0x00200000U
-#define  RCC_APB2RSTR_SAI1RST                0x00400000U
-#define  RCC_APB2RSTR_LTDCRST                0x04000000U
-
-/* Old SPI1RST bit definition, maintained for legacy purpose */
-#define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
-
-/********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
-#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
-#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
-#define  RCC_AHB1ENR_GPIODEN                 0x00000008U
-#define  RCC_AHB1ENR_GPIOEEN                 0x00000010U
-#define  RCC_AHB1ENR_GPIOFEN                 0x00000020U
-#define  RCC_AHB1ENR_GPIOGEN                 0x00000040U
-#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
-#define  RCC_AHB1ENR_GPIOIEN                 0x00000100U
-#define  RCC_AHB1ENR_GPIOJEN                 0x00000200U
-#define  RCC_AHB1ENR_GPIOKEN                 0x00000400U
-
-#define  RCC_AHB1ENR_CRCEN                   0x00001000U
-#define  RCC_AHB1ENR_BKPSRAMEN               0x00040000U
-#define  RCC_AHB1ENR_CCMDATARAMEN            0x00100000U
-#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
-#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
-#define  RCC_AHB1ENR_DMA2DEN                 0x00800000U
-
-#define  RCC_AHB1ENR_ETHMACEN                0x02000000U
-#define  RCC_AHB1ENR_ETHMACTXEN              0x04000000U
-#define  RCC_AHB1ENR_ETHMACRXEN              0x08000000U
-#define  RCC_AHB1ENR_ETHMACPTPEN             0x10000000U
-#define  RCC_AHB1ENR_OTGHSEN                 0x20000000U
-#define  RCC_AHB1ENR_OTGHSULPIEN             0x40000000U
-
-/********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define  RCC_AHB2ENR_DCMIEN                  0x00000001U
-#define  RCC_AHB2ENR_RNGEN                   0x00000040U
-#define  RCC_AHB2ENR_OTGFSEN                 0x00000080U
-
-/********************  Bit definition for RCC_AHB3ENR register  ***************/
-#define  RCC_AHB3ENR_FMCEN                  0x00000001U
-
-/********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM2EN                  0x00000001U
-#define  RCC_APB1ENR_TIM3EN                  0x00000002U
-#define  RCC_APB1ENR_TIM4EN                  0x00000004U
-#define  RCC_APB1ENR_TIM5EN                  0x00000008U
-#define  RCC_APB1ENR_TIM6EN                  0x00000010U
-#define  RCC_APB1ENR_TIM7EN                  0x00000020U
-#define  RCC_APB1ENR_TIM12EN                 0x00000040U
-#define  RCC_APB1ENR_TIM13EN                 0x00000080U
-#define  RCC_APB1ENR_TIM14EN                 0x00000100U
-#define  RCC_APB1ENR_WWDGEN                  0x00000800U
-#define  RCC_APB1ENR_SPI2EN                  0x00004000U
-#define  RCC_APB1ENR_SPI3EN                  0x00008000U
-#define  RCC_APB1ENR_USART2EN                0x00020000U
-#define  RCC_APB1ENR_USART3EN                0x00040000U
-#define  RCC_APB1ENR_UART4EN                 0x00080000U
-#define  RCC_APB1ENR_UART5EN                 0x00100000U
-#define  RCC_APB1ENR_I2C1EN                  0x00200000U
-#define  RCC_APB1ENR_I2C2EN                  0x00400000U
-#define  RCC_APB1ENR_I2C3EN                  0x00800000U
-#define  RCC_APB1ENR_CAN1EN                  0x02000000U
-#define  RCC_APB1ENR_CAN2EN                  0x04000000U
-#define  RCC_APB1ENR_PWREN                   0x10000000U
-#define  RCC_APB1ENR_DACEN                   0x20000000U
-#define  RCC_APB1ENR_UART7EN                 0x40000000U
-#define  RCC_APB1ENR_UART8EN                 0x80000000U
-
-/********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  0x00000001U
-#define  RCC_APB2ENR_TIM8EN                  0x00000002U
-#define  RCC_APB2ENR_USART1EN                0x00000010U
-#define  RCC_APB2ENR_USART6EN                0x00000020U
-#define  RCC_APB2ENR_ADC1EN                  0x00000100U
-#define  RCC_APB2ENR_ADC2EN                  0x00000200U
-#define  RCC_APB2ENR_ADC3EN                  0x00000400U
-#define  RCC_APB2ENR_SDIOEN                  0x00000800U
-#define  RCC_APB2ENR_SPI1EN                  0x00001000U
-#define  RCC_APB2ENR_SPI4EN                  0x00002000U
-#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
-#define  RCC_APB2ENR_TIM9EN                  0x00010000U
-#define  RCC_APB2ENR_TIM10EN                 0x00020000U
-#define  RCC_APB2ENR_TIM11EN                 0x00040000U
-#define  RCC_APB2ENR_SPI5EN                  0x00100000U
-#define  RCC_APB2ENR_SPI6EN                  0x00200000U
-#define  RCC_APB2ENR_SAI1EN                  0x00400000U
-#define  RCC_APB2ENR_LTDCEN                  0x04000000U
-
-/********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
-#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
-#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
-#define  RCC_AHB1LPENR_GPIODLPEN             0x00000008U
-#define  RCC_AHB1LPENR_GPIOELPEN             0x00000010U
-#define  RCC_AHB1LPENR_GPIOFLPEN             0x00000020U
-#define  RCC_AHB1LPENR_GPIOGLPEN             0x00000040U
-#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
-#define  RCC_AHB1LPENR_GPIOILPEN             0x00000100U
-#define  RCC_AHB1LPENR_GPIOJLPEN             0x00000200U
-#define  RCC_AHB1LPENR_GPIOKLPEN             0x00000400U
-
-#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
-#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
-#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
-#define  RCC_AHB1LPENR_SRAM2LPEN             0x00020000U
-#define  RCC_AHB1LPENR_BKPSRAMLPEN           0x00040000U
-#define  RCC_AHB1LPENR_SRAM3LPEN             0x00080000U
-#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
-#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
-#define  RCC_AHB1LPENR_DMA2DLPEN             0x00800000U
-
-#define  RCC_AHB1LPENR_ETHMACLPEN            0x02000000U
-#define  RCC_AHB1LPENR_ETHMACTXLPEN          0x04000000U
-#define  RCC_AHB1LPENR_ETHMACRXLPEN          0x08000000U
-#define  RCC_AHB1LPENR_ETHMACPTPLPEN         0x10000000U
-#define  RCC_AHB1LPENR_OTGHSLPEN             0x20000000U
-#define  RCC_AHB1LPENR_OTGHSULPILPEN         0x40000000U
-
-/********************  Bit definition for RCC_AHB2LPENR register  *************/
-#define  RCC_AHB2LPENR_DCMILPEN              0x00000001U
-#define  RCC_AHB2LPENR_RNGLPEN               0x00000040U
-#define  RCC_AHB2LPENR_OTGFSLPEN             0x00000080U
-
-/********************  Bit definition for RCC_AHB3LPENR register  *************/
-#define  RCC_AHB3LPENR_FMCLPEN              0x00000001U
-
-/********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM2LPEN              0x00000001U
-#define  RCC_APB1LPENR_TIM3LPEN              0x00000002U
-#define  RCC_APB1LPENR_TIM4LPEN              0x00000004U
-#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
-#define  RCC_APB1LPENR_TIM6LPEN              0x00000010U
-#define  RCC_APB1LPENR_TIM7LPEN              0x00000020U
-#define  RCC_APB1LPENR_TIM12LPEN             0x00000040U
-#define  RCC_APB1LPENR_TIM13LPEN             0x00000080U
-#define  RCC_APB1LPENR_TIM14LPEN             0x00000100U
-#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
-#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U
-#define  RCC_APB1LPENR_SPI3LPEN              0x00008000U
-#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
-#define  RCC_APB1LPENR_USART3LPEN            0x00040000U
-#define  RCC_APB1LPENR_UART4LPEN             0x00080000U
-#define  RCC_APB1LPENR_UART5LPEN             0x00100000U
-#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
-#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
-#define  RCC_APB1LPENR_I2C3LPEN              0x00800000U
-#define  RCC_APB1LPENR_CAN1LPEN              0x02000000U
-#define  RCC_APB1LPENR_CAN2LPEN              0x04000000U
-#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
-#define  RCC_APB1LPENR_DACLPEN               0x20000000U
-#define  RCC_APB1LPENR_UART7LPEN             0x40000000U
-#define  RCC_APB1LPENR_UART8LPEN             0x80000000U
-
-/********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
-#define  RCC_APB2LPENR_TIM8LPEN              0x00000002U
-#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
-#define  RCC_APB2LPENR_USART6LPEN            0x00000020U
-#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
-#define  RCC_APB2LPENR_ADC2LPEN              0x00000200U
-#define  RCC_APB2LPENR_ADC3LPEN              0x00000400U
-#define  RCC_APB2LPENR_SDIOLPEN              0x00000800U
-#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
-#define  RCC_APB2LPENR_SPI4LPEN              0x00002000U
-#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
-#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
-#define  RCC_APB2LPENR_TIM10LPEN             0x00020000U
-#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
-#define  RCC_APB2LPENR_SPI5LPEN              0x00100000U
-#define  RCC_APB2LPENR_SPI6LPEN              0x00200000U
-#define  RCC_APB2LPENR_SAI1LPEN              0x00400000U
-#define  RCC_APB2LPENR_LTDCLPEN              0x04000000U
-
-/********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      0x00000001U
-#define  RCC_BDCR_LSERDY                     0x00000002U
-#define  RCC_BDCR_LSEBYP                     0x00000004U
-
-#define  RCC_BDCR_RTCSEL                    0x00000300U
-#define  RCC_BDCR_RTCSEL_0                  0x00000100U
-#define  RCC_BDCR_RTCSEL_1                  0x00000200U
-
-#define  RCC_BDCR_RTCEN                      0x00008000U
-#define  RCC_BDCR_BDRST                      0x00010000U
-
-/********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       0x00000001U
-#define  RCC_CSR_LSIRDY                      0x00000002U
-#define  RCC_CSR_RMVF                        0x01000000U
-#define  RCC_CSR_BORRSTF                     0x02000000U
-#define  RCC_CSR_PADRSTF                     0x04000000U
-#define  RCC_CSR_PORRSTF                     0x08000000U
-#define  RCC_CSR_SFTRSTF                     0x10000000U
-#define  RCC_CSR_WDGRSTF                     0x20000000U
-#define  RCC_CSR_WWDGRSTF                    0x40000000U
-#define  RCC_CSR_LPWRRSTF                    0x80000000U
-
-/********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    0x00001FFFU
-#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
-#define  RCC_SSCGR_SPREADSEL                 0x40000000U
-#define  RCC_SSCGR_SSCGEN                    0x80000000U
-
-/********************  Bit definition for RCC_PLLI2SCFGR register  ************/
-#define  RCC_PLLI2SCFGR_PLLI2SN              0x00007FC0U
-#define  RCC_PLLI2SCFGR_PLLI2SN_0            0x00000040U
-#define  RCC_PLLI2SCFGR_PLLI2SN_1            0x00000080U
-#define  RCC_PLLI2SCFGR_PLLI2SN_2            0x00000100U
-#define  RCC_PLLI2SCFGR_PLLI2SN_3            0x00000200U
-#define  RCC_PLLI2SCFGR_PLLI2SN_4            0x00000400U
-#define  RCC_PLLI2SCFGR_PLLI2SN_5            0x00000800U
-#define  RCC_PLLI2SCFGR_PLLI2SN_6            0x00001000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_7            0x00002000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_8            0x00004000U
-
-#define  RCC_PLLI2SCFGR_PLLI2SQ              0x0F000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_0            0x01000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_1            0x02000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_2            0x04000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_3            0x08000000U
-
-#define  RCC_PLLI2SCFGR_PLLI2SR              0x70000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_0            0x10000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_1            0x20000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_2            0x40000000U
-
-
-/********************  Bit definition for RCC_PLLSAICFGR register  ************/
-#define  RCC_PLLSAICFGR_PLLSAIN              0x00007FC0U
-#define  RCC_PLLSAICFGR_PLLSAIN_0            0x00000040U
-#define  RCC_PLLSAICFGR_PLLSAIN_1            0x00000080U
-#define  RCC_PLLSAICFGR_PLLSAIN_2            0x00000100U
-#define  RCC_PLLSAICFGR_PLLSAIN_3            0x00000200U
-#define  RCC_PLLSAICFGR_PLLSAIN_4            0x00000400U
-#define  RCC_PLLSAICFGR_PLLSAIN_5            0x00000800U
-#define  RCC_PLLSAICFGR_PLLSAIN_6            0x00001000U
-#define  RCC_PLLSAICFGR_PLLSAIN_7            0x00002000U
-#define  RCC_PLLSAICFGR_PLLSAIN_8            0x00004000U
-
-#define  RCC_PLLSAICFGR_PLLSAIQ              0x0F000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_0            0x01000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_1            0x02000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_2            0x04000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_3            0x08000000U
-
-#define  RCC_PLLSAICFGR_PLLSAIR              0x70000000U
-#define  RCC_PLLSAICFGR_PLLSAIR_0            0x10000000U
-#define  RCC_PLLSAICFGR_PLLSAIR_1            0x20000000U
-#define  RCC_PLLSAICFGR_PLLSAIR_2            0x40000000U
-
-/********************  Bit definition for RCC_DCKCFGR register  ***************/
-#define  RCC_DCKCFGR_PLLI2SDIVQ              0x0000001FU
-#define  RCC_DCKCFGR_PLLSAIDIVQ              0x00001F00U
-#define  RCC_DCKCFGR_PLLSAIDIVR              0x00030000U
-#define  RCC_DCKCFGR_SAI1ASRC                0x00300000U
-#define  RCC_DCKCFGR_SAI1ASRC_0              0x00100000U
-#define  RCC_DCKCFGR_SAI1ASRC_1              0x00200000U
-#define  RCC_DCKCFGR_SAI1BSRC                0x00C00000U
-#define  RCC_DCKCFGR_SAI1BSRC_0              0x00400000U
-#define  RCC_DCKCFGR_SAI1BSRC_1              0x00800000U
-#define  RCC_DCKCFGR_TIMPRE                  0x01000000U
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    RNG                                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN                         0x00000004U
-#define RNG_CR_IE                            0x00000008U
-
-/********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY                          0x00000001U
-#define RNG_SR_CECS                          0x00000002U
-#define RNG_SR_SECS                          0x00000004U
-#define RNG_SR_CEIS                          0x00000020U
-#define RNG_SR_SEIS                          0x00000040U
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            0x00400000U
-#define RTC_TR_HT                            0x00300000U
-#define RTC_TR_HT_0                          0x00100000U
-#define RTC_TR_HT_1                          0x00200000U
-#define RTC_TR_HU                            0x000F0000U
-#define RTC_TR_HU_0                          0x00010000U
-#define RTC_TR_HU_1                          0x00020000U
-#define RTC_TR_HU_2                          0x00040000U
-#define RTC_TR_HU_3                          0x00080000U
-#define RTC_TR_MNT                           0x00007000U
-#define RTC_TR_MNT_0                         0x00001000U
-#define RTC_TR_MNT_1                         0x00002000U
-#define RTC_TR_MNT_2                         0x00004000U
-#define RTC_TR_MNU                           0x00000F00U
-#define RTC_TR_MNU_0                         0x00000100U
-#define RTC_TR_MNU_1                         0x00000200U
-#define RTC_TR_MNU_2                         0x00000400U
-#define RTC_TR_MNU_3                         0x00000800U
-#define RTC_TR_ST                            0x00000070U
-#define RTC_TR_ST_0                          0x00000010U
-#define RTC_TR_ST_1                          0x00000020U
-#define RTC_TR_ST_2                          0x00000040U
-#define RTC_TR_SU                            0x0000000FU
-#define RTC_TR_SU_0                          0x00000001U
-#define RTC_TR_SU_1                          0x00000002U
-#define RTC_TR_SU_2                          0x00000004U
-#define RTC_TR_SU_3                          0x00000008U
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            0x00F00000U
-#define RTC_DR_YT_0                          0x00100000U
-#define RTC_DR_YT_1                          0x00200000U
-#define RTC_DR_YT_2                          0x00400000U
-#define RTC_DR_YT_3                          0x00800000U
-#define RTC_DR_YU                            0x000F0000U
-#define RTC_DR_YU_0                          0x00010000U
-#define RTC_DR_YU_1                          0x00020000U
-#define RTC_DR_YU_2                          0x00040000U
-#define RTC_DR_YU_3                          0x00080000U
-#define RTC_DR_WDU                           0x0000E000U
-#define RTC_DR_WDU_0                         0x00002000U
-#define RTC_DR_WDU_1                         0x00004000U
-#define RTC_DR_WDU_2                         0x00008000U
-#define RTC_DR_MT                            0x00001000U
-#define RTC_DR_MU                            0x00000F00U
-#define RTC_DR_MU_0                          0x00000100U
-#define RTC_DR_MU_1                          0x00000200U
-#define RTC_DR_MU_2                          0x00000400U
-#define RTC_DR_MU_3                          0x00000800U
-#define RTC_DR_DT                            0x00000030U
-#define RTC_DR_DT_0                          0x00000010U
-#define RTC_DR_DT_1                          0x00000020U
-#define RTC_DR_DU                            0x0000000FU
-#define RTC_DR_DU_0                          0x00000001U
-#define RTC_DR_DU_1                          0x00000002U
-#define RTC_DR_DU_2                          0x00000004U
-#define RTC_DR_DU_3                          0x00000008U
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           0x00800000U
-#define RTC_CR_OSEL                          0x00600000U
-#define RTC_CR_OSEL_0                        0x00200000U
-#define RTC_CR_OSEL_1                        0x00400000U
-#define RTC_CR_POL                           0x00100000U
-#define RTC_CR_COSEL                         0x00080000U
-#define RTC_CR_BCK                           0x00040000U
-#define RTC_CR_SUB1H                         0x00020000U
-#define RTC_CR_ADD1H                         0x00010000U
-#define RTC_CR_TSIE                          0x00008000U
-#define RTC_CR_WUTIE                         0x00004000U
-#define RTC_CR_ALRBIE                        0x00002000U
-#define RTC_CR_ALRAIE                        0x00001000U
-#define RTC_CR_TSE                           0x00000800U
-#define RTC_CR_WUTE                          0x00000400U
-#define RTC_CR_ALRBE                         0x00000200U
-#define RTC_CR_ALRAE                         0x00000100U
-#define RTC_CR_DCE                           0x00000080U
-#define RTC_CR_FMT                           0x00000040U
-#define RTC_CR_BYPSHAD                       0x00000020U
-#define RTC_CR_REFCKON                       0x00000010U
-#define RTC_CR_TSEDGE                        0x00000008U
-#define RTC_CR_WUCKSEL                       0x00000007U
-#define RTC_CR_WUCKSEL_0                     0x00000001U
-#define RTC_CR_WUCKSEL_1                     0x00000002U
-#define RTC_CR_WUCKSEL_2                     0x00000004U
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      0x00010000U
-#define RTC_ISR_TAMP1F                       0x00002000U
-#define RTC_ISR_TAMP2F                       0x00004000U
-#define RTC_ISR_TSOVF                        0x00001000U
-#define RTC_ISR_TSF                          0x00000800U
-#define RTC_ISR_WUTF                         0x00000400U
-#define RTC_ISR_ALRBF                        0x00000200U
-#define RTC_ISR_ALRAF                        0x00000100U
-#define RTC_ISR_INIT                         0x00000080U
-#define RTC_ISR_INITF                        0x00000040U
-#define RTC_ISR_RSF                          0x00000020U
-#define RTC_ISR_INITS                        0x00000010U
-#define RTC_ISR_SHPF                         0x00000008U
-#define RTC_ISR_WUTWF                        0x00000004U
-#define RTC_ISR_ALRBWF                       0x00000002U
-#define RTC_ISR_ALRAWF                       0x00000001U
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    0x007F0000U
-#define RTC_PRER_PREDIV_S                    0x00007FFFU
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS                       0x00000080U
-#define RTC_CALIBR_DC                        0x0000001FU
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      0x80000000U
-#define RTC_ALRMAR_WDSEL                     0x40000000U
-#define RTC_ALRMAR_DT                        0x30000000U
-#define RTC_ALRMAR_DT_0                      0x10000000U
-#define RTC_ALRMAR_DT_1                      0x20000000U
-#define RTC_ALRMAR_DU                        0x0F000000U
-#define RTC_ALRMAR_DU_0                      0x01000000U
-#define RTC_ALRMAR_DU_1                      0x02000000U
-#define RTC_ALRMAR_DU_2                      0x04000000U
-#define RTC_ALRMAR_DU_3                      0x08000000U
-#define RTC_ALRMAR_MSK3                      0x00800000U
-#define RTC_ALRMAR_PM                        0x00400000U
-#define RTC_ALRMAR_HT                        0x00300000U
-#define RTC_ALRMAR_HT_0                      0x00100000U
-#define RTC_ALRMAR_HT_1                      0x00200000U
-#define RTC_ALRMAR_HU                        0x000F0000U
-#define RTC_ALRMAR_HU_0                      0x00010000U
-#define RTC_ALRMAR_HU_1                      0x00020000U
-#define RTC_ALRMAR_HU_2                      0x00040000U
-#define RTC_ALRMAR_HU_3                      0x00080000U
-#define RTC_ALRMAR_MSK2                      0x00008000U
-#define RTC_ALRMAR_MNT                       0x00007000U
-#define RTC_ALRMAR_MNT_0                     0x00001000U
-#define RTC_ALRMAR_MNT_1                     0x00002000U
-#define RTC_ALRMAR_MNT_2                     0x00004000U
-#define RTC_ALRMAR_MNU                       0x00000F00U
-#define RTC_ALRMAR_MNU_0                     0x00000100U
-#define RTC_ALRMAR_MNU_1                     0x00000200U
-#define RTC_ALRMAR_MNU_2                     0x00000400U
-#define RTC_ALRMAR_MNU_3                     0x00000800U
-#define RTC_ALRMAR_MSK1                      0x00000080U
-#define RTC_ALRMAR_ST                        0x00000070U
-#define RTC_ALRMAR_ST_0                      0x00000010U
-#define RTC_ALRMAR_ST_1                      0x00000020U
-#define RTC_ALRMAR_ST_2                      0x00000040U
-#define RTC_ALRMAR_SU                        0x0000000FU
-#define RTC_ALRMAR_SU_0                      0x00000001U
-#define RTC_ALRMAR_SU_1                      0x00000002U
-#define RTC_ALRMAR_SU_2                      0x00000004U
-#define RTC_ALRMAR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      0x80000000U
-#define RTC_ALRMBR_WDSEL                     0x40000000U
-#define RTC_ALRMBR_DT                        0x30000000U
-#define RTC_ALRMBR_DT_0                      0x10000000U
-#define RTC_ALRMBR_DT_1                      0x20000000U
-#define RTC_ALRMBR_DU                        0x0F000000U
-#define RTC_ALRMBR_DU_0                      0x01000000U
-#define RTC_ALRMBR_DU_1                      0x02000000U
-#define RTC_ALRMBR_DU_2                      0x04000000U
-#define RTC_ALRMBR_DU_3                      0x08000000U
-#define RTC_ALRMBR_MSK3                      0x00800000U
-#define RTC_ALRMBR_PM                        0x00400000U
-#define RTC_ALRMBR_HT                        0x00300000U
-#define RTC_ALRMBR_HT_0                      0x00100000U
-#define RTC_ALRMBR_HT_1                      0x00200000U
-#define RTC_ALRMBR_HU                        0x000F0000U
-#define RTC_ALRMBR_HU_0                      0x00010000U
-#define RTC_ALRMBR_HU_1                      0x00020000U
-#define RTC_ALRMBR_HU_2                      0x00040000U
-#define RTC_ALRMBR_HU_3                      0x00080000U
-#define RTC_ALRMBR_MSK2                      0x00008000U
-#define RTC_ALRMBR_MNT                       0x00007000U
-#define RTC_ALRMBR_MNT_0                     0x00001000U
-#define RTC_ALRMBR_MNT_1                     0x00002000U
-#define RTC_ALRMBR_MNT_2                     0x00004000U
-#define RTC_ALRMBR_MNU                       0x00000F00U
-#define RTC_ALRMBR_MNU_0                     0x00000100U
-#define RTC_ALRMBR_MNU_1                     0x00000200U
-#define RTC_ALRMBR_MNU_2                     0x00000400U
-#define RTC_ALRMBR_MNU_3                     0x00000800U
-#define RTC_ALRMBR_MSK1                      0x00000080U
-#define RTC_ALRMBR_ST                        0x00000070U
-#define RTC_ALRMBR_ST_0                      0x00000010U
-#define RTC_ALRMBR_ST_1                      0x00000020U
-#define RTC_ALRMBR_ST_2                      0x00000040U
-#define RTC_ALRMBR_SU                        0x0000000FU
-#define RTC_ALRMBR_SU_0                      0x00000001U
-#define RTC_ALRMBR_SU_1                      0x00000002U
-#define RTC_ALRMBR_SU_2                      0x00000004U
-#define RTC_ALRMBR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          0x000000FFU
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           0x0000FFFFU
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     0x00007FFFU
-#define RTC_SHIFTR_ADD1S                     0x80000000U
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          0x00400000U
-#define RTC_TSTR_HT                          0x00300000U
-#define RTC_TSTR_HT_0                        0x00100000U
-#define RTC_TSTR_HT_1                        0x00200000U
-#define RTC_TSTR_HU                          0x000F0000U
-#define RTC_TSTR_HU_0                        0x00010000U
-#define RTC_TSTR_HU_1                        0x00020000U
-#define RTC_TSTR_HU_2                        0x00040000U
-#define RTC_TSTR_HU_3                        0x00080000U
-#define RTC_TSTR_MNT                         0x00007000U
-#define RTC_TSTR_MNT_0                       0x00001000U
-#define RTC_TSTR_MNT_1                       0x00002000U
-#define RTC_TSTR_MNT_2                       0x00004000U
-#define RTC_TSTR_MNU                         0x00000F00U
-#define RTC_TSTR_MNU_0                       0x00000100U
-#define RTC_TSTR_MNU_1                       0x00000200U
-#define RTC_TSTR_MNU_2                       0x00000400U
-#define RTC_TSTR_MNU_3                       0x00000800U
-#define RTC_TSTR_ST                          0x00000070U
-#define RTC_TSTR_ST_0                        0x00000010U
-#define RTC_TSTR_ST_1                        0x00000020U
-#define RTC_TSTR_ST_2                        0x00000040U
-#define RTC_TSTR_SU                          0x0000000FU
-#define RTC_TSTR_SU_0                        0x00000001U
-#define RTC_TSTR_SU_1                        0x00000002U
-#define RTC_TSTR_SU_2                        0x00000004U
-#define RTC_TSTR_SU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         0x0000E000U
-#define RTC_TSDR_WDU_0                       0x00002000U
-#define RTC_TSDR_WDU_1                       0x00004000U
-#define RTC_TSDR_WDU_2                       0x00008000U
-#define RTC_TSDR_MT                          0x00001000U
-#define RTC_TSDR_MU                          0x00000F00U
-#define RTC_TSDR_MU_0                        0x00000100U
-#define RTC_TSDR_MU_1                        0x00000200U
-#define RTC_TSDR_MU_2                        0x00000400U
-#define RTC_TSDR_MU_3                        0x00000800U
-#define RTC_TSDR_DT                          0x00000030U
-#define RTC_TSDR_DT_0                        0x00000010U
-#define RTC_TSDR_DT_1                        0x00000020U
-#define RTC_TSDR_DU                          0x0000000FU
-#define RTC_TSDR_DU_0                        0x00000001U
-#define RTC_TSDR_DU_1                        0x00000002U
-#define RTC_TSDR_DU_2                        0x00000004U
-#define RTC_TSDR_DU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        0x00008000U
-#define RTC_CALR_CALW8                       0x00004000U
-#define RTC_CALR_CALW16                      0x00002000U
-#define RTC_CALR_CALM                        0x000001FFU
-#define RTC_CALR_CALM_0                      0x00000001U
-#define RTC_CALR_CALM_1                      0x00000002U
-#define RTC_CALR_CALM_2                      0x00000004U
-#define RTC_CALR_CALM_3                      0x00000008U
-#define RTC_CALR_CALM_4                      0x00000010U
-#define RTC_CALR_CALM_5                      0x00000020U
-#define RTC_CALR_CALM_6                      0x00000040U
-#define RTC_CALR_CALM_7                      0x00000080U
-#define RTC_CALR_CALM_8                      0x00000100U
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               0x00040000U
-#define RTC_TAFCR_TSINSEL                    0x00020000U
-#define RTC_TAFCR_TAMPINSEL                  0x00010000U
-#define RTC_TAFCR_TAMPPUDIS                  0x00008000U
-#define RTC_TAFCR_TAMPPRCH                   0x00006000U
-#define RTC_TAFCR_TAMPPRCH_0                 0x00002000U
-#define RTC_TAFCR_TAMPPRCH_1                 0x00004000U
-#define RTC_TAFCR_TAMPFLT                    0x00001800U
-#define RTC_TAFCR_TAMPFLT_0                  0x00000800U
-#define RTC_TAFCR_TAMPFLT_1                  0x00001000U
-#define RTC_TAFCR_TAMPFREQ                   0x00000700U
-#define RTC_TAFCR_TAMPFREQ_0                 0x00000100U
-#define RTC_TAFCR_TAMPFREQ_1                 0x00000200U
-#define RTC_TAFCR_TAMPFREQ_2                 0x00000400U
-#define RTC_TAFCR_TAMPTS                     0x00000080U
-#define RTC_TAFCR_TAMP2TRG                   0x00000010U
-#define RTC_TAFCR_TAMP2E                     0x00000008U
-#define RTC_TAFCR_TAMPIE                     0x00000004U
-#define RTC_TAFCR_TAMP1TRG                   0x00000002U
-#define RTC_TAFCR_TAMP1E                     0x00000001U
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  0x0F000000U
-#define RTC_ALRMASSR_MASKSS_0                0x01000000U
-#define RTC_ALRMASSR_MASKSS_1                0x02000000U
-#define RTC_ALRMASSR_MASKSS_2                0x04000000U
-#define RTC_ALRMASSR_MASKSS_3                0x08000000U
-#define RTC_ALRMASSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
-#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
-#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
-#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
-#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
-#define RTC_ALRMBSSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           0xFFFFFFFFU
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Serial Audio Interface                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for SAI_GCR register  *******************/
-#define  SAI_GCR_SYNCIN                  0x00000003U        /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
-#define  SAI_GCR_SYNCIN_0                0x00000001U        /*!<Bit 0 */
-#define  SAI_GCR_SYNCIN_1                0x00000002U        /*!<Bit 1 */
-
-#define  SAI_GCR_SYNCOUT                 0x00000030U        /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
-#define  SAI_GCR_SYNCOUT_0               0x00000010U        /*!<Bit 0 */
-#define  SAI_GCR_SYNCOUT_1               0x00000020U        /*!<Bit 1 */
-
-/*******************  Bit definition for SAI_xCR1 register  *******************/
-#define  SAI_xCR1_MODE                    0x00000003U        /*!<MODE[1:0] bits (Audio Block Mode)           */
-#define  SAI_xCR1_MODE_0                  0x00000001U        /*!<Bit 0 */
-#define  SAI_xCR1_MODE_1                  0x00000002U        /*!<Bit 1 */
-
-#define  SAI_xCR1_PRTCFG                  0x0000000CU        /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
-#define  SAI_xCR1_PRTCFG_0                0x00000004U        /*!<Bit 0 */
-#define  SAI_xCR1_PRTCFG_1                0x00000008U        /*!<Bit 1 */
-
-#define  SAI_xCR1_DS                      0x000000E0U        /*!<DS[1:0] bits (Data Size) */
-#define  SAI_xCR1_DS_0                    0x00000020U        /*!<Bit 0 */
-#define  SAI_xCR1_DS_1                    0x00000040U        /*!<Bit 1 */
-#define  SAI_xCR1_DS_2                    0x00000080U        /*!<Bit 2 */
-
-#define  SAI_xCR1_LSBFIRST                0x00000100U        /*!<LSB First Configuration  */
-#define  SAI_xCR1_CKSTR                   0x00000200U        /*!<ClocK STRobing edge      */
-
-#define  SAI_xCR1_SYNCEN                  0x00000C00U        /*!<SYNCEN[1:0](SYNChronization ENable) */
-#define  SAI_xCR1_SYNCEN_0                0x00000400U        /*!<Bit 0 */
-#define  SAI_xCR1_SYNCEN_1                0x00000800U        /*!<Bit 1 */
-
-#define  SAI_xCR1_MONO                    0x00001000U        /*!<Mono mode                  */
-#define  SAI_xCR1_OUTDRIV                 0x00002000U        /*!<Output Drive               */
-#define  SAI_xCR1_SAIEN                   0x00010000U        /*!<Audio Block enable         */
-#define  SAI_xCR1_DMAEN                   0x00020000U        /*!<DMA enable                 */
-#define  SAI_xCR1_NODIV                   0x00080000U        /*!<No Divider Configuration   */
-
-#define  SAI_xCR1_MCKDIV                  0x00F00000U        /*!<MCKDIV[3:0] (Master ClocK Divider)  */
-#define  SAI_xCR1_MCKDIV_0                0x00100000U        /*!<Bit 0  */
-#define  SAI_xCR1_MCKDIV_1                0x00200000U        /*!<Bit 1  */
-#define  SAI_xCR1_MCKDIV_2                0x00400000U        /*!<Bit 2  */
-#define  SAI_xCR1_MCKDIV_3                0x00800000U        /*!<Bit 3  */
-
-/*******************  Bit definition for SAI_xCR2 register  *******************/
-#define  SAI_xCR2_FTH                     0x00000007U        /*!<FTH[2:0](Fifo THreshold)  */
-#define  SAI_xCR2_FTH_0                   0x00000001U        /*!<Bit 0 */
-#define  SAI_xCR2_FTH_1                   0x00000002U        /*!<Bit 1 */
-#define  SAI_xCR2_FTH_2                   0x00000004U        /*!<Bit 2 */
-
-#define  SAI_xCR2_FFLUSH                  0x00000008U        /*!<Fifo FLUSH                       */
-#define  SAI_xCR2_TRIS                    0x00000010U        /*!<TRIState Management on data line */
-#define  SAI_xCR2_MUTE                    0x00000020U        /*!<Mute mode                        */
-#define  SAI_xCR2_MUTEVAL                 0x00000040U        /*!<Muate value                      */
-
-#define  SAI_xCR2_MUTECNT                  0x00001F80U       /*!<MUTECNT[5:0] (MUTE counter) */
-#define  SAI_xCR2_MUTECNT_0               0x00000080U        /*!<Bit 0 */
-#define  SAI_xCR2_MUTECNT_1               0x00000100U        /*!<Bit 1 */
-#define  SAI_xCR2_MUTECNT_2               0x00000200U        /*!<Bit 2 */
-#define  SAI_xCR2_MUTECNT_3               0x00000400U        /*!<Bit 3 */
-#define  SAI_xCR2_MUTECNT_4               0x00000800U        /*!<Bit 4 */
-#define  SAI_xCR2_MUTECNT_5               0x00001000U        /*!<Bit 5 */
-
-#define  SAI_xCR2_CPL                     0x00002000U        /*!< Complement Bit             */
-
-#define  SAI_xCR2_COMP                    0x0000C000U        /*!<COMP[1:0] (Companding mode) */
-#define  SAI_xCR2_COMP_0                  0x00004000U        /*!<Bit 0 */
-#define  SAI_xCR2_COMP_1                  0x00008000U        /*!<Bit 1 */
-
-/******************  Bit definition for SAI_xFRCR register  *******************/
-#define  SAI_xFRCR_FRL                    0x000000FFU        /*!<FRL[1:0](Frame length)  */
-#define  SAI_xFRCR_FRL_0                  0x00000001U        /*!<Bit 0 */
-#define  SAI_xFRCR_FRL_1                  0x00000002U        /*!<Bit 1 */
-#define  SAI_xFRCR_FRL_2                  0x00000004U        /*!<Bit 2 */
-#define  SAI_xFRCR_FRL_3                  0x00000008U        /*!<Bit 3 */
-#define  SAI_xFRCR_FRL_4                  0x00000010U        /*!<Bit 4 */
-#define  SAI_xFRCR_FRL_5                  0x00000020U        /*!<Bit 5 */
-#define  SAI_xFRCR_FRL_6                  0x00000040U        /*!<Bit 6 */
-#define  SAI_xFRCR_FRL_7                  0x00000080U        /*!<Bit 7 */
-
-#define  SAI_xFRCR_FSALL                  0x00007F00U        /*!<FRL[1:0] (Frame synchronization active level length)  */
-#define  SAI_xFRCR_FSALL_0                0x00000100U        /*!<Bit 0 */
-#define  SAI_xFRCR_FSALL_1                0x00000200U        /*!<Bit 1 */
-#define  SAI_xFRCR_FSALL_2                0x00000400U        /*!<Bit 2 */
-#define  SAI_xFRCR_FSALL_3                0x00000800U        /*!<Bit 3 */
-#define  SAI_xFRCR_FSALL_4                0x00001000U        /*!<Bit 4 */
-#define  SAI_xFRCR_FSALL_5                0x00002000U        /*!<Bit 5 */
-#define  SAI_xFRCR_FSALL_6                0x00004000U        /*!<Bit 6 */
-
-#define  SAI_xFRCR_FSDEF                  0x00010000U        /*!< Frame Synchronization Definition */
-#define  SAI_xFRCR_FSPOL                  0x00020000U        /*!<Frame Synchronization POLarity    */
-#define  SAI_xFRCR_FSOFF                  0x00040000U        /*!<Frame Synchronization OFFset      */
-/* Legacy defines */
-#define  SAI_xFRCR_FSPO                   SAI_xFRCR_FSPOL
-
-/******************  Bit definition for SAI_xSLOTR register  *******************/
-#define  SAI_xSLOTR_FBOFF                 0x0000001FU        /*!<FRL[4:0](First Bit Offset)  */
-#define  SAI_xSLOTR_FBOFF_0               0x00000001U        /*!<Bit 0 */
-#define  SAI_xSLOTR_FBOFF_1               0x00000002U        /*!<Bit 1 */
-#define  SAI_xSLOTR_FBOFF_2               0x00000004U        /*!<Bit 2 */
-#define  SAI_xSLOTR_FBOFF_3               0x00000008U        /*!<Bit 3 */
-#define  SAI_xSLOTR_FBOFF_4               0x00000010U        /*!<Bit 4 */
-
-#define  SAI_xSLOTR_SLOTSZ                0x000000C0U        /*!<SLOTSZ[1:0] (Slot size)  */
-#define  SAI_xSLOTR_SLOTSZ_0              0x00000040U        /*!<Bit 0 */
-#define  SAI_xSLOTR_SLOTSZ_1              0x00000080U        /*!<Bit 1 */
-
-#define  SAI_xSLOTR_NBSLOT                0x00000F00U        /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
-#define  SAI_xSLOTR_NBSLOT_0              0x00000100U        /*!<Bit 0 */
-#define  SAI_xSLOTR_NBSLOT_1              0x00000200U        /*!<Bit 1 */
-#define  SAI_xSLOTR_NBSLOT_2              0x00000400U        /*!<Bit 2 */
-#define  SAI_xSLOTR_NBSLOT_3              0x00000800U        /*!<Bit 3 */
-
-#define  SAI_xSLOTR_SLOTEN                0xFFFF0000U        /*!<SLOTEN[15:0] (Slot Enable)  */
-
-/*******************  Bit definition for SAI_xIMR register  *******************/
-#define  SAI_xIMR_OVRUDRIE                0x00000001U        /*!<Overrun underrun interrupt enable                              */
-#define  SAI_xIMR_MUTEDETIE               0x00000002U        /*!<Mute detection interrupt enable                                */
-#define  SAI_xIMR_WCKCFGIE                0x00000004U        /*!<Wrong Clock Configuration interrupt enable                     */
-#define  SAI_xIMR_FREQIE                  0x00000008U        /*!<FIFO request interrupt enable                                  */
-#define  SAI_xIMR_CNRDYIE                 0x00000010U        /*!<Codec not ready interrupt enable                               */
-#define  SAI_xIMR_AFSDETIE                0x00000020U        /*!<Anticipated frame synchronization detection interrupt enable   */
-#define  SAI_xIMR_LFSDETIE                0x00000040U        /*!<Late frame synchronization detection interrupt enable          */
-
-/********************  Bit definition for SAI_xSR register  *******************/
-#define  SAI_xSR_OVRUDR                   0x00000001U         /*!<Overrun underrun                               */
-#define  SAI_xSR_MUTEDET                  0x00000002U         /*!<Mute detection                                 */
-#define  SAI_xSR_WCKCFG                   0x00000004U         /*!<Wrong Clock Configuration                      */
-#define  SAI_xSR_FREQ                     0x00000008U         /*!<FIFO request                                   */
-#define  SAI_xSR_CNRDY                    0x00000010U         /*!<Codec not ready                                */
-#define  SAI_xSR_AFSDET                   0x00000020U         /*!<Anticipated frame synchronization detection    */
-#define  SAI_xSR_LFSDET                   0x00000040U         /*!<Late frame synchronization detection           */
-
-#define  SAI_xSR_FLVL                     0x00070000U         /*!<FLVL[2:0] (FIFO Level Threshold)               */
-#define  SAI_xSR_FLVL_0                   0x00010000U         /*!<Bit 0 */
-#define  SAI_xSR_FLVL_1                   0x00020000U         /*!<Bit 1 */
-#define  SAI_xSR_FLVL_2                   0x00040000U         /*!<Bit 2 */
-
-/******************  Bit definition for SAI_xCLRFR register  ******************/
-#define  SAI_xCLRFR_COVRUDR               0x00000001U        /*!<Clear Overrun underrun                               */
-#define  SAI_xCLRFR_CMUTEDET              0x00000002U        /*!<Clear Mute detection                                 */
-#define  SAI_xCLRFR_CWCKCFG               0x00000004U        /*!<Clear Wrong Clock Configuration                      */
-#define  SAI_xCLRFR_CFREQ                 0x00000008U        /*!<Clear FIFO request                                   */
-#define  SAI_xCLRFR_CCNRDY                0x00000010U        /*!<Clear Codec not ready                                */
-#define  SAI_xCLRFR_CAFSDET               0x00000020U        /*!<Clear Anticipated frame synchronization detection    */
-#define  SAI_xCLRFR_CLFSDET               0x00000040U        /*!<Clear Late frame synchronization detection           */
-
-/******************  Bit definition for SAI_xDR register  ******************/
-#define  SAI_xDR_DATA                     0xFFFFFFFFU        
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          SD host Interface                                 */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SDIO_POWER register  ******************/
-#define  SDIO_POWER_PWRCTRL                  0x03U               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDIO_POWER_PWRCTRL_0                0x01U               /*!<Bit 0 */
-#define  SDIO_POWER_PWRCTRL_1                0x02U               /*!<Bit 1 */
-
-/******************  Bit definition for SDIO_CLKCR register  ******************/
-#define  SDIO_CLKCR_CLKDIV                   0x00FFU            /*!<Clock divide factor             */
-#define  SDIO_CLKCR_CLKEN                    0x0100U            /*!<Clock enable bit                */
-#define  SDIO_CLKCR_PWRSAV                   0x0200U            /*!<Power saving configuration bit  */
-#define  SDIO_CLKCR_BYPASS                   0x0400U            /*!<Clock divider bypass enable bit */
-
-#define  SDIO_CLKCR_WIDBUS                   0x1800U            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDIO_CLKCR_WIDBUS_0                 0x0800U            /*!<Bit 0 */
-#define  SDIO_CLKCR_WIDBUS_1                 0x1000U            /*!<Bit 1 */
-
-#define  SDIO_CLKCR_NEGEDGE                  0x2000U            /*!<SDIO_CK dephasing selection bit */
-#define  SDIO_CLKCR_HWFC_EN                  0x4000U            /*!<HW Flow Control enable          */
-
-/*******************  Bit definition for SDIO_ARG register  *******************/
-#define  SDIO_ARG_CMDARG                     0xFFFFFFFFU            /*!<Command argument */
-
-/*******************  Bit definition for SDIO_CMD register  *******************/
-#define  SDIO_CMD_CMDINDEX                   0x003FU            /*!<Command Index                               */
-
-#define  SDIO_CMD_WAITRESP                   0x00C0U            /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDIO_CMD_WAITRESP_0                 0x0040U            /*!< Bit 0 */
-#define  SDIO_CMD_WAITRESP_1                 0x0080U            /*!< Bit 1 */
-
-#define  SDIO_CMD_WAITINT                    0x0100U            /*!<CPSM Waits for Interrupt Request                               */
-#define  SDIO_CMD_WAITPEND                   0x0200U            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDIO_CMD_CPSMEN                     0x0400U            /*!<Command path state machine (CPSM) Enable bit                   */
-#define  SDIO_CMD_SDIOSUSPEND                0x0800U            /*!<SD I/O suspend command                                         */
-#define  SDIO_CMD_ENCMDCOMPL                 0x1000U            /*!<Enable CMD completion                                          */
-#define  SDIO_CMD_NIEN                       0x2000U            /*!<Not Interrupt Enable */
-#define  SDIO_CMD_CEATACMD                   0x4000U            /*!<CE-ATA command       */
-
-/*****************  Bit definition for SDIO_RESPCMD register  *****************/
-#define  SDIO_RESPCMD_RESPCMD                0x3FU               /*!<Response command index */
-
-/******************  Bit definition for SDIO_RESP0 register  ******************/
-#define  SDIO_RESP0_CARDSTATUS0              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP1 register  ******************/
-#define  SDIO_RESP1_CARDSTATUS1              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP2 register  ******************/
-#define  SDIO_RESP2_CARDSTATUS2              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP3 register  ******************/
-#define  SDIO_RESP3_CARDSTATUS3              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP4 register  ******************/
-#define  SDIO_RESP4_CARDSTATUS4              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_DTIMER register  *****************/
-#define  SDIO_DTIMER_DATATIME                0xFFFFFFFFU        /*!<Data timeout period. */
-
-/******************  Bit definition for SDIO_DLEN register  *******************/
-#define  SDIO_DLEN_DATALENGTH                0x01FFFFFFU        /*!<Data length value    */
-
-/******************  Bit definition for SDIO_DCTRL register  ******************/
-#define  SDIO_DCTRL_DTEN                     0x0001U            /*!<Data transfer enabled bit         */
-#define  SDIO_DCTRL_DTDIR                    0x0002U            /*!<Data transfer direction selection */
-#define  SDIO_DCTRL_DTMODE                   0x0004U            /*!<Data transfer mode selection      */
-#define  SDIO_DCTRL_DMAEN                    0x0008U            /*!<DMA enabled bit                   */
-
-#define  SDIO_DCTRL_DBLOCKSIZE               0x00F0U            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDIO_DCTRL_DBLOCKSIZE_0             0x0010U            /*!<Bit 0 */
-#define  SDIO_DCTRL_DBLOCKSIZE_1             0x0020U            /*!<Bit 1 */
-#define  SDIO_DCTRL_DBLOCKSIZE_2             0x0040U            /*!<Bit 2 */
-#define  SDIO_DCTRL_DBLOCKSIZE_3             0x0080U            /*!<Bit 3 */
-
-#define  SDIO_DCTRL_RWSTART                  0x0100U            /*!<Read wait start         */
-#define  SDIO_DCTRL_RWSTOP                   0x0200U            /*!<Read wait stop          */
-#define  SDIO_DCTRL_RWMOD                    0x0400U            /*!<Read wait mode          */
-#define  SDIO_DCTRL_SDIOEN                   0x0800U            /*!<SD I/O enable functions */
-
-/******************  Bit definition for SDIO_DCOUNT register  *****************/
-#define  SDIO_DCOUNT_DATACOUNT               0x01FFFFFFU        /*!<Data count value */
-
-/******************  Bit definition for SDIO_STA register  ********************/
-#define  SDIO_STA_CCRCFAIL                   0x00000001U        /*!<Command response received (CRC check failed)  */
-#define  SDIO_STA_DCRCFAIL                   0x00000002U        /*!<Data block sent/received (CRC check failed)   */
-#define  SDIO_STA_CTIMEOUT                   0x00000004U        /*!<Command response timeout                      */
-#define  SDIO_STA_DTIMEOUT                   0x00000008U        /*!<Data timeout                                  */
-#define  SDIO_STA_TXUNDERR                   0x00000010U        /*!<Transmit FIFO underrun error                  */
-#define  SDIO_STA_RXOVERR                    0x00000020U        /*!<Received FIFO overrun error                   */
-#define  SDIO_STA_CMDREND                    0x00000040U        /*!<Command response received (CRC check passed)  */
-#define  SDIO_STA_CMDSENT                    0x00000080U        /*!<Command sent (no response required)           */
-#define  SDIO_STA_DATAEND                    0x00000100U        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
-#define  SDIO_STA_STBITERR                   0x00000200U        /*!<Start bit not detected on all data signals in wide bus mode */
-#define  SDIO_STA_DBCKEND                    0x00000400U        /*!<Data block sent/received (CRC check passed)   */
-#define  SDIO_STA_CMDACT                     0x00000800U        /*!<Command transfer in progress                  */
-#define  SDIO_STA_TXACT                      0x00001000U        /*!<Data transmit in progress                     */
-#define  SDIO_STA_RXACT                      0x00002000U        /*!<Data receive in progress                      */
-#define  SDIO_STA_TXFIFOHE                   0x00004000U        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDIO_STA_RXFIFOHF                   0x00008000U        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDIO_STA_TXFIFOF                    0x00010000U        /*!<Transmit FIFO full                            */
-#define  SDIO_STA_RXFIFOF                    0x00020000U        /*!<Receive FIFO full                             */
-#define  SDIO_STA_TXFIFOE                    0x00040000U        /*!<Transmit FIFO empty                           */
-#define  SDIO_STA_RXFIFOE                    0x00080000U        /*!<Receive FIFO empty                            */
-#define  SDIO_STA_TXDAVL                     0x00100000U        /*!<Data available in transmit FIFO               */
-#define  SDIO_STA_RXDAVL                     0x00200000U        /*!<Data available in receive FIFO                */
-#define  SDIO_STA_SDIOIT                     0x00400000U        /*!<SDIO interrupt received                       */
-#define  SDIO_STA_CEATAEND                   0x00800000U        /*!<CE-ATA command completion signal received for CMD61 */
-
-/*******************  Bit definition for SDIO_ICR register  *******************/
-#define  SDIO_ICR_CCRCFAILC                  0x00000001U        /*!<CCRCFAIL flag clear bit */
-#define  SDIO_ICR_DCRCFAILC                  0x00000002U        /*!<DCRCFAIL flag clear bit */
-#define  SDIO_ICR_CTIMEOUTC                  0x00000004U        /*!<CTIMEOUT flag clear bit */
-#define  SDIO_ICR_DTIMEOUTC                  0x00000008U        /*!<DTIMEOUT flag clear bit */
-#define  SDIO_ICR_TXUNDERRC                  0x00000010U        /*!<TXUNDERR flag clear bit */
-#define  SDIO_ICR_RXOVERRC                   0x00000020U        /*!<RXOVERR flag clear bit  */
-#define  SDIO_ICR_CMDRENDC                   0x00000040U        /*!<CMDREND flag clear bit  */
-#define  SDIO_ICR_CMDSENTC                   0x00000080U        /*!<CMDSENT flag clear bit  */
-#define  SDIO_ICR_DATAENDC                   0x00000100U        /*!<DATAEND flag clear bit  */
-#define  SDIO_ICR_STBITERRC                  0x00000200U        /*!<STBITERR flag clear bit */
-#define  SDIO_ICR_DBCKENDC                   0x00000400U        /*!<DBCKEND flag clear bit  */
-#define  SDIO_ICR_SDIOITC                    0x00400000U        /*!<SDIOIT flag clear bit   */
-#define  SDIO_ICR_CEATAENDC                  0x00800000U        /*!<CEATAEND flag clear bit */
-
-/******************  Bit definition for SDIO_MASK register  *******************/
-#define  SDIO_MASK_CCRCFAILIE                0x00000001U        /*!<Command CRC Fail Interrupt Enable          */
-#define  SDIO_MASK_DCRCFAILIE                0x00000002U        /*!<Data CRC Fail Interrupt Enable             */
-#define  SDIO_MASK_CTIMEOUTIE                0x00000004U        /*!<Command TimeOut Interrupt Enable           */
-#define  SDIO_MASK_DTIMEOUTIE                0x00000008U        /*!<Data TimeOut Interrupt Enable              */
-#define  SDIO_MASK_TXUNDERRIE                0x00000010U        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
-#define  SDIO_MASK_RXOVERRIE                 0x00000020U        /*!<Rx FIFO OverRun Error Interrupt Enable     */
-#define  SDIO_MASK_CMDRENDIE                 0x00000040U        /*!<Command Response Received Interrupt Enable */
-#define  SDIO_MASK_CMDSENTIE                 0x00000080U        /*!<Command Sent Interrupt Enable              */
-#define  SDIO_MASK_DATAENDIE                 0x00000100U        /*!<Data End Interrupt Enable                  */
-#define  SDIO_MASK_STBITERRIE                0x00000200U        /*!<Start Bit Error Interrupt Enable           */
-#define  SDIO_MASK_DBCKENDIE                 0x00000400U        /*!<Data Block End Interrupt Enable            */
-#define  SDIO_MASK_CMDACTIE                  0x00000800U        /*!<CCommand Acting Interrupt Enable           */
-#define  SDIO_MASK_TXACTIE                   0x00001000U        /*!<Data Transmit Acting Interrupt Enable      */
-#define  SDIO_MASK_RXACTIE                   0x00002000U        /*!<Data receive acting interrupt enabled      */
-#define  SDIO_MASK_TXFIFOHEIE                0x00004000U        /*!<Tx FIFO Half Empty interrupt Enable        */
-#define  SDIO_MASK_RXFIFOHFIE                0x00008000U        /*!<Rx FIFO Half Full interrupt Enable         */
-#define  SDIO_MASK_TXFIFOFIE                 0x00010000U        /*!<Tx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_RXFIFOFIE                 0x00020000U        /*!<Rx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_TXFIFOEIE                 0x00040000U        /*!<Tx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_RXFIFOEIE                 0x00080000U        /*!<Rx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_TXDAVLIE                  0x00100000U        /*!<Data available in Tx FIFO interrupt Enable */
-#define  SDIO_MASK_RXDAVLIE                  0x00200000U        /*!<Data available in Rx FIFO interrupt Enable */
-#define  SDIO_MASK_SDIOITIE                  0x00400000U        /*!<SDIO Mode Interrupt Received interrupt Enable */
-#define  SDIO_MASK_CEATAENDIE                0x00800000U        /*!<CE-ATA command completion signal received Interrupt Enable */
-
-/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
-#define  SDIO_FIFOCNT_FIFOCOUNT              0x00FFFFFFU        /*!<Remaining number of words to be written to or read from the FIFO */
-
-/******************  Bit definition for SDIO_FIFO register  *******************/
-#define  SDIO_FIFO_FIFODATA                  0xFFFFFFFFU        /*!<Receive and transmit FIFO data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        0x00000001U            /*!<Clock Phase      */
-#define  SPI_CR1_CPOL                        0x00000002U            /*!<Clock Polarity   */
-#define  SPI_CR1_MSTR                        0x00000004U            /*!<Master Selection */
-
-#define  SPI_CR1_BR                          0x00000038U            /*!<BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        0x00000008U            /*!<Bit 0 */
-#define  SPI_CR1_BR_1                        0x00000010U            /*!<Bit 1 */
-#define  SPI_CR1_BR_2                        0x00000020U            /*!<Bit 2 */
-
-#define  SPI_CR1_SPE                         0x00000040U            /*!<SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    0x00000080U            /*!<Frame Format                        */
-#define  SPI_CR1_SSI                         0x00000100U            /*!<Internal slave select               */
-#define  SPI_CR1_SSM                         0x00000200U            /*!<Software slave management           */
-#define  SPI_CR1_RXONLY                      0x00000400U            /*!<Receive only                        */
-#define  SPI_CR1_DFF                         0x00000800U            /*!<Data Frame Format                   */
-#define  SPI_CR1_CRCNEXT                     0x00001000U            /*!<Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       0x00002000U            /*!<Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      0x00004000U            /*!<Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    0x00008000U            /*!<Bidirectional data mode enable      */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     0x00000001U               /*!<Rx Buffer DMA Enable                 */
-#define  SPI_CR2_TXDMAEN                     0x00000002U               /*!<Tx Buffer DMA Enable                 */
-#define  SPI_CR2_SSOE                        0x00000004U               /*!<SS Output Enable                     */
-#define  SPI_CR2_FRF                         0x00000010U               /*!<Frame Format                         */
-#define  SPI_CR2_ERRIE                       0x00000020U               /*!<Error Interrupt Enable               */
-#define  SPI_CR2_RXNEIE                      0x00000040U               /*!<RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       0x00000080U               /*!<Tx buffer Empty Interrupt Enable     */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         0x00000001U               /*!<Receive buffer Not Empty */
-#define  SPI_SR_TXE                          0x00000002U               /*!<Transmit buffer Empty    */
-#define  SPI_SR_CHSIDE                       0x00000004U               /*!<Channel side             */
-#define  SPI_SR_UDR                          0x00000008U               /*!<Underrun flag            */
-#define  SPI_SR_CRCERR                       0x00000010U               /*!<CRC Error flag           */
-#define  SPI_SR_MODF                         0x00000020U               /*!<Mode fault               */
-#define  SPI_SR_OVR                          0x00000040U               /*!<Overrun flag             */
-#define  SPI_SR_BSY                          0x00000080U               /*!<Busy flag                */
-#define  SPI_SR_FRE                          0x00000100U               /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           0x0000FFFFU            /*!<Data Register           */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   0x0000FFFFU            /*!<CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    0x0000FFFFU            /*!<Rx CRC Register         */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    0x0000FFFFU            /*!<Tx CRC Register         */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   0x00000001U            /*!<Channel length (number of bits per audio channel) */
-
-#define  SPI_I2SCFGR_DATLEN                  0x00000006U            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define  SPI_I2SCFGR_DATLEN_0                0x00000002U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                0x00000004U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_CKPOL                   0x00000008U            /*!<steady state clock polarity               */
-
-#define  SPI_I2SCFGR_I2SSTD                  0x00000030U            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U            /*!<PCM frame synchronization                 */
-
-#define  SPI_I2SCFGR_I2SCFG                  0x00000300U            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_I2SE                    0x00000400U            /*!<I2S Enable         */
-#define  SPI_I2SCFGR_I2SMOD                  0x00000800U            /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    0x000000FFU            /*!<I2S Linear prescaler         */
-#define  SPI_I2SPR_ODD                       0x00000100U            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     0x00000200U            /*!<Master Clock Output Enable   */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 SYSCFG                                     */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
-#define SYSCFG_MEMRMP_MEM_MODE          0x00000007U /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        0x00000001U
-#define SYSCFG_MEMRMP_MEM_MODE_1        0x00000002U
-#define SYSCFG_MEMRMP_MEM_MODE_2        0x00000004U
-
-#define SYSCFG_MEMRMP_UFB_MODE          0x00000100U /*!< User Flash Bank mode    */
-#define SYSCFG_SWP_FMC                  0x00000C00U /*!< FMC memory mapping swap */
-
-/******************  Bit definition for SYSCFG_PMC register  ******************/
-#define SYSCFG_PMC_ADCxDC2              0x00070000U /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC1DC2              0x00010000U /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC2DC2              0x00020000U /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC3DC2              0x00040000U /*!< Refer to AN4073 on how to use this bit  */
-
-#define SYSCFG_PMC_MII_RMII_SEL         0x00800000U /*!<Ethernet PHY interface selection */
-/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
-#define SYSCFG_PMC_MII_RMII             SYSCFG_PMC_MII_RMII_SEL
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
-/** 
-  * @brief   EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         0x0003U /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         0x0004U /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         0x0005U /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         0x0006U /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PI         0x0008U /*!<PI[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PJ         0x0009U /*!<PJ[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PK         0x000AU /*!<PK[0] pin */
-
-/** 
-  * @brief   EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         0x0030U /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         0x0040U /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         0x0050U /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         0x0060U /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PI         0x0080U /*!<PI[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PJ         0x0090U /*!<PJ[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PK         0x00A0U /*!<PK[1] pin */
-
-
-/** 
-  * @brief   EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         0x0300U /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         0x0400U /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         0x0500U /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         0x0600U /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PI         0x0800U /*!<PI[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PJ         0x0900U /*!<PJ[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PK         0x0A00U /*!<PK[2] pin */
-
-
-/** 
-  * @brief   EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         0x3000U /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         0x4000U /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         0x5000U /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         0x6000U /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PI         0x8000U /*!<PI[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PJ         0x9000U /*!<PJ[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PK         0xA000U /*!<PK[3] pin */
-
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
-/** 
-  * @brief   EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         0x0003U /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         0x0004U /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         0x0005U /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         0x0006U /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PI         0x0008U /*!<PI[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PJ         0x0009U /*!<PJ[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PK         0x000AU /*!<PK[4] pin */
-
-/** 
-  * @brief   EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         0x0030U /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         0x0040U /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         0x0050U /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         0x0060U /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PI         0x0080U /*!<PI[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PJ         0x0090U /*!<PJ[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PK         0x00A0U /*!<PK[5] pin */
-
-/** 
-  * @brief   EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         0x0300U /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         0x0400U /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         0x0500U /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         0x0600U /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PI         0x0800U /*!<PI[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PJ         0x0900U /*!<PJ[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PK         0x0A00U /*!<PK[6] pin */
-
-
-/** 
-  * @brief   EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         0x3000U /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         0x4000U /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         0x5000U /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         0x6000U /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PI         0x8000U /*!<PI[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PJ         0x9000U /*!<PJ[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PK         0xA000U /*!<PK[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
-           
-/** 
-  * @brief   EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         0x0003U /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         0x0004U /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         0x0005U /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         0x0006U /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PI         0x0008U /*!<PI[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PJ         0x0009U /*!<PJ[8] pin */
-
-/** 
-  * @brief   EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         0x0030U /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         0x0040U /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         0x0050U /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         0x0060U /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PI         0x0080U /*!<PI[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PJ         0x0090U /*!<PJ[9] pin */
-
-
-/** 
-  * @brief   EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        0x0300U /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        0x0400U /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        0x0500U /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        0x0600U /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PI        0x0800U /*!<PI[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PJ        0x0900U /*!<PJ[10] pin */
-
-
-/** 
-  * @brief   EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        0x3000U /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        0x4000U /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        0x5000U /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        0x6000U /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PI        0x8000U /*!<PI[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PJ        0x9000U /*!<PJ[11] pin */
-
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
-/** 
-  * @brief   EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        0x0003U /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        0x0004U /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        0x0005U /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        0x0006U /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PI        0x0008U /*!<PI[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PJ        0x0009U /*!<PJ[12] pin */
-
-
-/** 
-  * @brief   EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        0x0030U /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        0x0040U /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        0x0050U /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        0x0060U /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PI        0x0008U /*!<PI[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PJ        0x0009U /*!<PJ[13] pin */
-
-
-/** 
-  * @brief   EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        0x0300U /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        0x0400U /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        0x0500U /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        0x0600U /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PI        0x0800U /*!<PI[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PJ        0x0900U /*!<PJ[14] pin */
-
-
-/** 
-  * @brief   EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        0x3000U /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        0x4000U /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        0x5000U /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        0x6000U /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PI        0x8000U /*!<PI[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PJ        0x9000U /*!<PJ[15] pin */
-
-/******************  Bit definition for SYSCFG_CMPCR register  ****************/  
-#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell ready flag */
-#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell power-down */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    TIM                                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
-#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
-#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
-#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
-#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
-
-#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
-
-#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
-
-#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        0x0001U            /*!<Capture/Compare Preloaded Control        */
-#define  TIM_CR2_CCUS                        0x0004U            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        0x0008U            /*!<Capture/Compare DMA Selection            */
-
-#define  TIM_CR2_MMS                         0x0070U            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
-#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
-#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
-#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        0x0007U            /*!<SMS[2:0] bits (Slave mode selection)    */
-#define  TIM_SMCR_SMS_0                      0x0001U            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      0x0002U            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      0x0004U            /*!<Bit 2 */
-
-#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
-#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
-
-#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
-
-#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
-
-#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
-#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
-#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
-#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
-#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
-#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
-#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
-#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
-#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
-#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
-#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
-#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
-#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
-#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
-#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
-#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
-#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
-#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
-#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          0x01U               /*!<Update Generation                         */
-#define  TIM_EGR_CC1G                        0x02U               /*!<Capture/Compare 1 Generation              */
-#define  TIM_EGR_CC2G                        0x04U               /*!<Capture/Compare 2 Generation              */
-#define  TIM_EGR_CC3G                        0x08U               /*!<Capture/Compare 3 Generation              */
-#define  TIM_EGR_CC4G                        0x10U               /*!<Capture/Compare 4 Generation              */
-#define  TIM_EGR_COMG                        0x20U               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          0x40U               /*!<Trigger Generation                        */
-#define  TIM_EGR_BG                          0x80U               /*!<Break Generation                          */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      0x0003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    0x0001U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    0x0002U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC1FE                     0x0004U            /*!<Output Compare 1 Fast enable                 */
-#define  TIM_CCMR1_OC1PE                     0x0008U            /*!<Output Compare 1 Preload enable              */
-
-#define  TIM_CCMR1_OC1M                      0x0070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define  TIM_CCMR1_OC1M_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    0x0040U            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC1CE                     0x0080U            /*!<Output Compare 1Clear Enable                 */
-
-#define  TIM_CCMR1_CC2S                      0x0300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    0x0100U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    0x0200U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC2FE                     0x0400U            /*!<Output Compare 2 Fast enable                 */
-#define  TIM_CCMR1_OC2PE                     0x0800U            /*!<Output Compare 2 Preload enable              */
-
-#define  TIM_CCMR1_OC2M                      0x7000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define  TIM_CCMR1_OC2M_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    0x4000U            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC2CE                     0x8000U            /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      0x0003U            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define  TIM_CCMR2_CC3S_0                    0x0001U            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    0x0002U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC3FE                     0x0004U            /*!<Output Compare 3 Fast enable           */
-#define  TIM_CCMR2_OC3PE                     0x0008U            /*!<Output Compare 3 Preload enable        */
-
-#define  TIM_CCMR2_OC3M                      0x0070U            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    0x0040U            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC3CE                     0x0080U            /*!<Output Compare 3 Clear Enable */
-
-#define  TIM_CCMR2_CC4S                      0x0300U            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    0x0100U            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    0x0200U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC4FE                     0x0400U            /*!<Output Compare 4 Fast enable    */
-#define  TIM_CCMR2_OC4PE                     0x0800U            /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR2_OC4M                      0x7000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    0x4000U            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       0x0001U            /*!<Capture/Compare 1 output enable                 */
-#define  TIM_CCER_CC1P                       0x0002U            /*!<Capture/Compare 1 output Polarity               */
-#define  TIM_CCER_CC1NE                      0x0004U            /*!<Capture/Compare 1 Complementary output enable   */
-#define  TIM_CCER_CC1NP                      0x0008U            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       0x0010U            /*!<Capture/Compare 2 output enable                 */
-#define  TIM_CCER_CC2P                       0x0020U            /*!<Capture/Compare 2 output Polarity               */
-#define  TIM_CCER_CC2NE                      0x0040U            /*!<Capture/Compare 2 Complementary output enable   */
-#define  TIM_CCER_CC2NP                      0x0080U            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       0x0100U            /*!<Capture/Compare 3 output enable                 */
-#define  TIM_CCER_CC3P                       0x0200U            /*!<Capture/Compare 3 output Polarity               */
-#define  TIM_CCER_CC3NE                      0x0400U            /*!<Capture/Compare 3 Complementary output enable   */
-#define  TIM_CCER_CC3NP                      0x0800U            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       0x1000U            /*!<Capture/Compare 4 output enable                 */
-#define  TIM_CCER_CC4P                       0x2000U            /*!<Capture/Compare 4 output Polarity               */
-#define  TIM_CCER_CC4NP                      0x8000U            /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         0xFFU               /*!<Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
-
-/*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        0x00FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      0x0001U            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      0x0002U            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      0x0004U            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      0x0008U            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      0x0010U            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      0x0020U            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      0x0040U            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      0x0080U            /*!<Bit 7 */
-
-#define  TIM_BDTR_LOCK                       0x0300U            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     0x0100U            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     0x0200U            /*!<Bit 1 */
-
-#define  TIM_BDTR_OSSI                       0x0400U            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       0x0800U            /*!<Off-State Selection for Run mode  */
-#define  TIM_BDTR_BKE                        0x1000U            /*!<Break enable                      */
-#define  TIM_BDTR_BKP                        0x2000U            /*!<Break Polarity                    */
-#define  TIM_BDTR_AOE                        0x4000U            /*!<Automatic Output enable           */
-#define  TIM_BDTR_MOE                        0x8000U            /*!<Main Output enable                */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
-
-#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
-#define TIM_OR_ITR1_RMP                      0x0C00U            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
-#define TIM_OR_ITR1_RMP_0                    0x0400U            /*!<Bit 0 */
-#define TIM_OR_ITR1_RMP_1                    0x0800U            /*!<Bit 1 */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*         Universal Synchronous Asynchronous Receiver Transmitter            */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         0x0001U            /*!<Parity Error                 */
-#define  USART_SR_FE                         0x0002U            /*!<Framing Error                */
-#define  USART_SR_NE                         0x0004U            /*!<Noise Error Flag             */
-#define  USART_SR_ORE                        0x0008U            /*!<OverRun Error                */
-#define  USART_SR_IDLE                       0x0010U            /*!<IDLE line detected           */
-#define  USART_SR_RXNE                       0x0020U            /*!<Read Data Register Not Empty */
-#define  USART_SR_TC                         0x0040U            /*!<Transmission Complete        */
-#define  USART_SR_TXE                        0x0080U            /*!<Transmit Data Register Empty */
-#define  USART_SR_LBD                        0x0100U            /*!<LIN Break Detection Flag     */
-#define  USART_SR_CTS                        0x0200U            /*!<CTS Flag                     */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         0x01FFU            /*!<Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_Fraction              0x000FU            /*!<Fraction of USARTDIV */
-#define  USART_BRR_DIV_Mantissa              0xFFF0U            /*!<Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       0x0001U            /*!<Send Break                             */
-#define  USART_CR1_RWU                       0x0002U            /*!<Receiver wakeup                        */
-#define  USART_CR1_RE                        0x0004U            /*!<Receiver Enable                        */
-#define  USART_CR1_TE                        0x0008U            /*!<Transmitter Enable                     */
-#define  USART_CR1_IDLEIE                    0x0010U            /*!<IDLE Interrupt Enable                  */
-#define  USART_CR1_RXNEIE                    0x0020U            /*!<RXNE Interrupt Enable                  */
-#define  USART_CR1_TCIE                      0x0040U            /*!<Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     0x0080U            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PEIE                      0x0100U            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PS                        0x0200U            /*!<Parity Selection                       */
-#define  USART_CR1_PCE                       0x0400U            /*!<Parity Control Enable                  */
-#define  USART_CR1_WAKE                      0x0800U            /*!<Wakeup method                          */
-#define  USART_CR1_M                         0x1000U            /*!<Word length                            */
-#define  USART_CR1_UE                        0x2000U            /*!<USART Enable                           */
-#define  USART_CR1_OVER8                     0x8000U            /*!<USART Oversampling by 8 enable         */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       0x000FU            /*!<Address of the USART node            */
-#define  USART_CR2_LBDL                      0x0020U            /*!<LIN Break Detection Length           */
-#define  USART_CR2_LBDIE                     0x0040U            /*!<LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      0x0100U            /*!<Last Bit Clock pulse                 */
-#define  USART_CR2_CPHA                      0x0200U            /*!<Clock Phase                          */
-#define  USART_CR2_CPOL                      0x0400U            /*!<Clock Polarity                       */
-#define  USART_CR2_CLKEN                     0x0800U            /*!<Clock Enable                         */
-
-#define  USART_CR2_STOP                      0x3000U            /*!<STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    0x1000U            /*!<Bit 0 */
-#define  USART_CR2_STOP_1                    0x2000U            /*!<Bit 1 */
-
-#define  USART_CR2_LINEN                     0x4000U            /*!<LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       0x0001U            /*!<Error Interrupt Enable      */
-#define  USART_CR3_IREN                      0x0002U            /*!<IrDA mode Enable            */
-#define  USART_CR3_IRLP                      0x0004U            /*!<IrDA Low-Power              */
-#define  USART_CR3_HDSEL                     0x0008U            /*!<Half-Duplex Selection       */
-#define  USART_CR3_NACK                      0x0010U            /*!<Smartcard NACK enable       */
-#define  USART_CR3_SCEN                      0x0020U            /*!<Smartcard mode enable       */
-#define  USART_CR3_DMAR                      0x0040U            /*!<DMA Enable Receiver         */
-#define  USART_CR3_DMAT                      0x0080U            /*!<DMA Enable Transmitter      */
-#define  USART_CR3_RTSE                      0x0100U            /*!<RTS Enable                  */
-#define  USART_CR3_CTSE                      0x0200U            /*!<CTS Enable                  */
-#define  USART_CR3_CTSIE                     0x0400U            /*!<CTS Interrupt Enable        */
-#define  USART_CR3_ONEBIT                    0x0800U            /*!<USART One bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      0x00FFU            /*!<PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    0x0001U            /*!<Bit 0 */
-#define  USART_GTPR_PSC_1                    0x0002U            /*!<Bit 1 */
-#define  USART_GTPR_PSC_2                    0x0004U            /*!<Bit 2 */
-#define  USART_GTPR_PSC_3                    0x0008U            /*!<Bit 3 */
-#define  USART_GTPR_PSC_4                    0x0010U            /*!<Bit 4 */
-#define  USART_GTPR_PSC_5                    0x0020U            /*!<Bit 5 */
-#define  USART_GTPR_PSC_6                    0x0040U            /*!<Bit 6 */
-#define  USART_GTPR_PSC_7                    0x0080U            /*!<Bit 7 */
-
-#define  USART_GTPR_GT                       0xFF00U            /*!<Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Window WATCHDOG                                 */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           0x7FU               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T_0                         0x01U               /*!<Bit 0 */
-#define  WWDG_CR_T_1                         0x02U               /*!<Bit 1 */
-#define  WWDG_CR_T_2                         0x04U               /*!<Bit 2 */
-#define  WWDG_CR_T_3                         0x08U               /*!<Bit 3 */
-#define  WWDG_CR_T_4                         0x10U               /*!<Bit 4 */
-#define  WWDG_CR_T_5                         0x20U               /*!<Bit 5 */
-#define  WWDG_CR_T_6                         0x40U               /*!<Bit 6 */
-/* Legacy defines */
-#define  WWDG_CR_T0                          WWDG_CR_T_0
-#define  WWDG_CR_T1                          WWDG_CR_T_1
-#define  WWDG_CR_T2                          WWDG_CR_T_2
-#define  WWDG_CR_T3                          WWDG_CR_T_3
-#define  WWDG_CR_T4                          WWDG_CR_T_4
-#define  WWDG_CR_T5                          WWDG_CR_T_5
-#define  WWDG_CR_T6                          WWDG_CR_T_6
-
-#define  WWDG_CR_WDGA                        0x80U               /*!<Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          0x007FU            /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W_0                        0x0001U            /*!<Bit 0 */
-#define  WWDG_CFR_W_1                        0x0002U            /*!<Bit 1 */
-#define  WWDG_CFR_W_2                        0x0004U            /*!<Bit 2 */
-#define  WWDG_CFR_W_3                        0x0008U            /*!<Bit 3 */
-#define  WWDG_CFR_W_4                        0x0010U            /*!<Bit 4 */
-#define  WWDG_CFR_W_5                        0x0020U            /*!<Bit 5 */
-#define  WWDG_CFR_W_6                        0x0040U            /*!<Bit 6 */
-/* Legacy defines */
-#define  WWDG_CFR_W0                         WWDG_CFR_W_0
-#define  WWDG_CFR_W1                         WWDG_CFR_W_1
-#define  WWDG_CFR_W2                         WWDG_CFR_W_2
-#define  WWDG_CFR_W3                         WWDG_CFR_W_3
-#define  WWDG_CFR_W4                         WWDG_CFR_W_4
-#define  WWDG_CFR_W5                         WWDG_CFR_W_5
-#define  WWDG_CFR_W6                         WWDG_CFR_W_6
-
-#define  WWDG_CFR_WDGTB                      0x0180U            /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB_0                    0x0080U            /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB_1                    0x0100U            /*!<Bit 1 */
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
-
-#define  WWDG_CFR_EWI                        0x0200U            /*!<Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        0x01U               /*!<Early Wakeup Interrupt Flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                DBG                                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
-#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
-
-/********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
-#define  DBGMCU_CR_DBG_STOP                  0x00000002U
-#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
-#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
-
-#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
-#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U/*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U/*!<Bit 1 */
-
-/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            0x00000001U
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            0x00000002U
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            0x00000004U
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            0x00000020U
-#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           0x00000040U
-#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           0x00000080U
-#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           0x00000100U
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
-#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
-/* Old IWDGSTOP bit definition, maintained for legacy purpose */
-#define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
-
-/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        0x00000001U
-#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        0x00000002U
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        0x00010000U
-#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       0x00020000U
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       0x00040000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                Ethernet MAC Registers bits definitions                     */
-/*                                                                            */
-/******************************************************************************/
-/* Bit definition for Ethernet MAC Control Register register */
-#define ETH_MACCR_WD      0x00800000U  /* Watchdog disable */
-#define ETH_MACCR_JD      0x00400000U  /* Jabber disable */
-#define ETH_MACCR_IFG     0x000E0000U  /* Inter-frame gap */
-#define ETH_MACCR_IFG_96Bit     0x00000000U  /* Minimum IFG between frames during transmission is 96Bit */
-  #define ETH_MACCR_IFG_88Bit     0x00020000U  /* Minimum IFG between frames during transmission is 88Bit */
-  #define ETH_MACCR_IFG_80Bit     0x00040000U  /* Minimum IFG between frames during transmission is 80Bit */
-  #define ETH_MACCR_IFG_72Bit     0x00060000U  /* Minimum IFG between frames during transmission is 72Bit */
-  #define ETH_MACCR_IFG_64Bit     0x00080000U  /* Minimum IFG between frames during transmission is 64Bit */        
-  #define ETH_MACCR_IFG_56Bit     0x000A0000U  /* Minimum IFG between frames during transmission is 56Bit */
-  #define ETH_MACCR_IFG_48Bit     0x000C0000U  /* Minimum IFG between frames during transmission is 48Bit */
-  #define ETH_MACCR_IFG_40Bit     0x000E0000U  /* Minimum IFG between frames during transmission is 40Bit */              
-#define ETH_MACCR_CSD     0x00010000U  /* Carrier sense disable (during transmission) */
-#define ETH_MACCR_FES     0x00004000U  /* Fast ethernet speed */
-#define ETH_MACCR_ROD     0x00002000U  /* Receive own disable */
-#define ETH_MACCR_LM      0x00001000U  /* loopback mode */
-#define ETH_MACCR_DM      0x00000800U  /* Duplex mode */
-#define ETH_MACCR_IPCO    0x00000400U  /* IP Checksum offload */
-#define ETH_MACCR_RD      0x00000200U  /* Retry disable */
-#define ETH_MACCR_APCS    0x00000080U  /* Automatic Pad/CRC stripping */
-#define ETH_MACCR_BL      0x00000060U  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
-                                                       a transmission attempt during retries after a collision: 0 =< r <2^k */
-  #define ETH_MACCR_BL_10    0x00000000U  /* k = min (n, 10) */
-  #define ETH_MACCR_BL_8     0x00000020U  /* k = min (n, 8) */
-  #define ETH_MACCR_BL_4     0x00000040U  /* k = min (n, 4) */
-  #define ETH_MACCR_BL_1     0x00000060U  /* k = min (n, 1) */ 
-#define ETH_MACCR_DC      0x00000010U  /* Defferal check */
-#define ETH_MACCR_TE      0x00000008U  /* Transmitter enable */
-#define ETH_MACCR_RE      0x00000004U  /* Receiver enable */
-
-/* Bit definition for Ethernet MAC Frame Filter Register */
-#define ETH_MACFFR_RA     0x80000000U  /* Receive all */ 
-#define ETH_MACFFR_HPF    0x00000400U  /* Hash or perfect filter */ 
-#define ETH_MACFFR_SAF    0x00000200U  /* Source address filter enable */ 
-#define ETH_MACFFR_SAIF   0x00000100U  /* SA inverse filtering */ 
-#define ETH_MACFFR_PCF    0x000000C0U  /* Pass control frames: 3 cases */
-  #define ETH_MACFFR_PCF_BlockAll                0x00000040U  /* MAC filters all control frames from reaching the application */
-  #define ETH_MACFFR_PCF_ForwardAll              0x00000080U  /* MAC forwards all control frames to application even if they fail the Address Filter */
-  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U  /* MAC forwards control frames that pass the Address Filter. */ 
-#define ETH_MACFFR_BFD    0x00000020U  /* Broadcast frame disable */ 
-#define ETH_MACFFR_PAM    0x00000010U  /* Pass all mutlicast */ 
-#define ETH_MACFFR_DAIF   0x00000008U  /* DA Inverse filtering */ 
-#define ETH_MACFFR_HM     0x00000004U  /* Hash multicast */ 
-#define ETH_MACFFR_HU     0x00000002U  /* Hash unicast */
-#define ETH_MACFFR_PM     0x00000001U  /* Promiscuous mode */
-
-/* Bit definition for Ethernet MAC Hash Table High Register */
-#define ETH_MACHTHR_HTH   0xFFFFFFFFU  /* Hash table high */
-
-/* Bit definition for Ethernet MAC Hash Table Low Register */
-#define ETH_MACHTLR_HTL   0xFFFFFFFFU  /* Hash table low */
-
-/* Bit definition for Ethernet MAC MII Address Register */
-#define ETH_MACMIIAR_PA   0x0000F800U  /* Physical layer address */ 
-#define ETH_MACMIIAR_MR   0x000007C0U  /* MII register in the selected PHY */ 
-#define ETH_MACMIIAR_CR   0x0000001CU  /* CR clock range: 6 cases */ 
-  #define ETH_MACMIIAR_CR_Div42   0x00000000U  /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
-  #define ETH_MACMIIAR_CR_Div62   0x00000004U  /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
-  #define ETH_MACMIIAR_CR_Div16   0x00000008U  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
-  #define ETH_MACMIIAR_CR_Div26   0x0000000CU  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
-  #define ETH_MACMIIAR_CR_Div102  0x00000010U  /* HCLK:150-168 MHz; MDC clock= HCLK/102 */  
-#define ETH_MACMIIAR_MW   0x00000002U  /* MII write */ 
-#define ETH_MACMIIAR_MB   0x00000001U  /* MII busy */ 
-  
-/* Bit definition for Ethernet MAC MII Data Register */
-#define ETH_MACMIIDR_MD   0x0000FFFFU  /* MII data: read/write data from/to PHY */
-
-/* Bit definition for Ethernet MAC Flow Control Register */
-#define ETH_MACFCR_PT     0xFFFF0000U  /* Pause time */
-#define ETH_MACFCR_ZQPD   0x00000080U  /* Zero-quanta pause disable */
-#define ETH_MACFCR_PLT    0x00000030U  /* Pause low threshold: 4 cases */
-  #define ETH_MACFCR_PLT_Minus4   0x00000000U  /* Pause time minus 4 slot times */
-  #define ETH_MACFCR_PLT_Minus28  0x00000010U  /* Pause time minus 28 slot times */
-  #define ETH_MACFCR_PLT_Minus144 0x00000020U  /* Pause time minus 144 slot times */
-  #define ETH_MACFCR_PLT_Minus256 0x00000030U  /* Pause time minus 256 slot times */      
-#define ETH_MACFCR_UPFD   0x00000008U  /* Unicast pause frame detect */
-#define ETH_MACFCR_RFCE   0x00000004U  /* Receive flow control enable */
-#define ETH_MACFCR_TFCE   0x00000002U  /* Transmit flow control enable */
-#define ETH_MACFCR_FCBBPA 0x00000001U  /* Flow control busy/backpressure activate */
-
-/* Bit definition for Ethernet MAC VLAN Tag Register */
-#define ETH_MACVLANTR_VLANTC 0x00010000U  /* 12-bit VLAN tag comparison */
-#define ETH_MACVLANTR_VLANTI 0x0000FFFFU  /* VLAN tag identifier (for receive frames) */
-
-/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ 
-#define ETH_MACRWUFFR_D   0xFFFFFFFFU  /* Wake-up frame filter register data */
-/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
-   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
-/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
-   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
-   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
-   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
-   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - 
-                              RSVD - Filter1 Command - RSVD - Filter0 Command
-   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
-   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
-   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
-
-/* Bit definition for Ethernet MAC PMT Control and Status Register */ 
-#define ETH_MACPMTCSR_WFFRPR 0x80000000U  /* Wake-Up Frame Filter Register Pointer Reset */
-#define ETH_MACPMTCSR_GU     0x00000200U  /* Global Unicast */
-#define ETH_MACPMTCSR_WFR    0x00000040U  /* Wake-Up Frame Received */
-#define ETH_MACPMTCSR_MPR    0x00000020U  /* Magic Packet Received */
-#define ETH_MACPMTCSR_WFE    0x00000004U  /* Wake-Up Frame Enable */
-#define ETH_MACPMTCSR_MPE    0x00000002U  /* Magic Packet Enable */
-#define ETH_MACPMTCSR_PD     0x00000001U  /* Power Down */
-
-/* Bit definition for Ethernet MAC Status Register */
-#define ETH_MACSR_TSTS      0x00000200U  /* Time stamp trigger status */
-#define ETH_MACSR_MMCTS     0x00000040U  /* MMC transmit status */
-#define ETH_MACSR_MMMCRS    0x00000020U  /* MMC receive status */
-#define ETH_MACSR_MMCS      0x00000010U  /* MMC status */
-#define ETH_MACSR_PMTS      0x00000008U  /* PMT status */
-
-/* Bit definition for Ethernet MAC Interrupt Mask Register */
-#define ETH_MACIMR_TSTIM     0x00000200U  /* Time stamp trigger interrupt mask */
-#define ETH_MACIMR_PMTIM     0x00000008U  /* PMT interrupt mask */
-
-/* Bit definition for Ethernet MAC Address0 High Register */
-#define ETH_MACA0HR_MACA0H   0x0000FFFFU  /* MAC address0 high */
-
-/* Bit definition for Ethernet MAC Address0 Low Register */
-#define ETH_MACA0LR_MACA0L   0xFFFFFFFFU  /* MAC address0 low */
-
-/* Bit definition for Ethernet MAC Address1 High Register */
-#define ETH_MACA1HR_AE       0x80000000U  /* Address enable */
-#define ETH_MACA1HR_SA       0x40000000U  /* Source address */
-#define ETH_MACA1HR_MBC      0x3F000000U  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
-  #define ETH_MACA1HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA1HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA1HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA1HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA1HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA1HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [7:0] */ 
-#define ETH_MACA1HR_MACA1H   0x0000FFFFU  /* MAC address1 high */
-
-/* Bit definition for Ethernet MAC Address1 Low Register */
-#define ETH_MACA1LR_MACA1L   0xFFFFFFFFU  /* MAC address1 low */
-
-/* Bit definition for Ethernet MAC Address2 High Register */
-#define ETH_MACA2HR_AE       0x80000000U  /* Address enable */
-#define ETH_MACA2HR_SA       0x40000000U  /* Source address */
-#define ETH_MACA2HR_MBC      0x3F000000U  /* Mask byte control */
-  #define ETH_MACA2HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA2HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA2HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA2HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA2HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA2HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA2HR_MACA2H   0x0000FFFFU  /* MAC address1 high */
-
-/* Bit definition for Ethernet MAC Address2 Low Register */
-#define ETH_MACA2LR_MACA2L   0xFFFFFFFFU  /* MAC address2 low */
-
-/* Bit definition for Ethernet MAC Address3 High Register */
-#define ETH_MACA3HR_AE       0x80000000U  /* Address enable */
-#define ETH_MACA3HR_SA       0x40000000U  /* Source address */
-#define ETH_MACA3HR_MBC      0x3F000000U  /* Mask byte control */
-  #define ETH_MACA3HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA3HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA3HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA3HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA3HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA3HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA3HR_MACA3H   0x0000FFFFU  /* MAC address3 high */
-
-/* Bit definition for Ethernet MAC Address3 Low Register */
-#define ETH_MACA3LR_MACA3L   0xFFFFFFFFU  /* MAC address3 low */
-
-/******************************************************************************/
-/*                Ethernet MMC Registers bits definition                      */
-/******************************************************************************/
-
-/* Bit definition for Ethernet MMC Contol Register */
-#define ETH_MMCCR_MCFHP      0x00000020U  /* MMC counter Full-Half preset */
-#define ETH_MMCCR_MCP        0x00000010U  /* MMC counter preset */
-#define ETH_MMCCR_MCF        0x00000008U  /* MMC Counter Freeze */
-#define ETH_MMCCR_ROR        0x00000004U  /* Reset on Read */
-#define ETH_MMCCR_CSR        0x00000002U  /* Counter Stop Rollover */
-#define ETH_MMCCR_CR         0x00000001U  /* Counters Reset */
-
-/* Bit definition for Ethernet MMC Receive Interrupt Register */
-#define ETH_MMCRIR_RGUFS     0x00020000U  /* Set when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIR_RFAES     0x00000040U  /* Set when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIR_RFCES     0x00000020U  /* Set when Rx crc error counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmit Interrupt Register */
-#define ETH_MMCTIR_TGFS      0x00200000U  /* Set when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFMSCS   0x00008000U  /* Set when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFSCS    0x00004000U  /* Set when Tx good single col counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
-#define ETH_MMCRIMR_RGUFM    0x00020000U  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFAEM    0x00000040U  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFCEM    0x00000020U  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
-#define ETH_MMCTIMR_TGFM     0x00200000U  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFMSCM  0x00008000U  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFSCM   0x00004000U  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
-#define ETH_MMCTGFSCCR_TGFSCC     0xFFFFFFFFU  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
-#define ETH_MMCTGFMSCCR_TGFMSCC   0xFFFFFFFFU  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
-#define ETH_MMCTGFCR_TGFC    0xFFFFFFFFU  /* Number of good frames transmitted. */
-
-/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
-#define ETH_MMCRFCECR_RFCEC  0xFFFFFFFFU  /* Number of frames received with CRC error. */
-
-/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
-#define ETH_MMCRFAECR_RFAEC  0xFFFFFFFFU  /* Number of frames received with alignment (dribble) error */
-
-/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
-#define ETH_MMCRGUFCR_RGUFC  0xFFFFFFFFU  /* Number of good unicast frames received. */
-
-/******************************************************************************/
-/*               Ethernet PTP Registers bits definition                       */
-/******************************************************************************/
-
-/* Bit definition for Ethernet PTP Time Stamp Contol Register */
-#define ETH_PTPTSCR_TSCNT       0x00030000U  /* Time stamp clock node type */
-#define ETH_PTPTSSR_TSSMRME     0x00008000U  /* Time stamp snapshot for message relevant to master enable */
-#define ETH_PTPTSSR_TSSEME      0x00004000U  /* Time stamp snapshot for event message enable */
-#define ETH_PTPTSSR_TSSIPV4FE   0x00002000U  /* Time stamp snapshot for IPv4 frames enable */
-#define ETH_PTPTSSR_TSSIPV6FE   0x00001000U  /* Time stamp snapshot for IPv6 frames enable */
-#define ETH_PTPTSSR_TSSPTPOEFE  0x00000800U  /* Time stamp snapshot for PTP over ethernet frames enable */
-#define ETH_PTPTSSR_TSPTPPSV2E  0x00000400U  /* Time stamp PTP packet snooping for version2 format enable */
-#define ETH_PTPTSSR_TSSSR       0x00000200U  /* Time stamp Sub-seconds rollover */
-#define ETH_PTPTSSR_TSSARFE     0x00000100U  /* Time stamp snapshot for all received frames enable */
-
-#define ETH_PTPTSCR_TSARU    0x00000020U  /* Addend register update */
-#define ETH_PTPTSCR_TSITE    0x00000010U  /* Time stamp interrupt trigger enable */
-#define ETH_PTPTSCR_TSSTU    0x00000008U  /* Time stamp update */
-#define ETH_PTPTSCR_TSSTI    0x00000004U  /* Time stamp initialize */
-#define ETH_PTPTSCR_TSFCU    0x00000002U  /* Time stamp fine or coarse update */
-#define ETH_PTPTSCR_TSE      0x00000001U  /* Time stamp enable */
-
-/* Bit definition for Ethernet PTP Sub-Second Increment Register */
-#define ETH_PTPSSIR_STSSI    0x000000FFU  /* System time Sub-second increment value */
-
-/* Bit definition for Ethernet PTP Time Stamp High Register */
-#define ETH_PTPTSHR_STS      0xFFFFFFFFU  /* System Time second */
-
-/* Bit definition for Ethernet PTP Time Stamp Low Register */
-#define ETH_PTPTSLR_STPNS    0x80000000U  /* System Time Positive or negative time */
-#define ETH_PTPTSLR_STSS     0x7FFFFFFFU  /* System Time sub-seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp High Update Register */
-#define ETH_PTPTSHUR_TSUS    0xFFFFFFFFU  /* Time stamp update seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
-#define ETH_PTPTSLUR_TSUPNS  0x80000000U  /* Time stamp update Positive or negative time */
-#define ETH_PTPTSLUR_TSUSS   0x7FFFFFFFU  /* Time stamp update sub-seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp Addend Register */
-#define ETH_PTPTSAR_TSA      0xFFFFFFFFU  /* Time stamp addend */
-
-/* Bit definition for Ethernet PTP Target Time High Register */
-#define ETH_PTPTTHR_TTSH     0xFFFFFFFFU  /* Target time stamp high */
-
-/* Bit definition for Ethernet PTP Target Time Low Register */
-#define ETH_PTPTTLR_TTSL     0xFFFFFFFFU  /* Target time stamp low */
-
-/* Bit definition for Ethernet PTP Time Stamp Status Register */
-#define ETH_PTPTSSR_TSTTR    0x00000020U  /* Time stamp target time reached */
-#define ETH_PTPTSSR_TSSO     0x00000010U  /* Time stamp seconds overflow */
-
-/******************************************************************************/
-/*                 Ethernet DMA Registers bits definition                     */
-/******************************************************************************/
-
-/* Bit definition for Ethernet DMA Bus Mode Register */
-#define ETH_DMABMR_AAB       0x02000000U  /* Address-Aligned beats */
-#define ETH_DMABMR_FPM        0x01000000U  /* 4xPBL mode */
-#define ETH_DMABMR_USP       0x00800000U  /* Use separate PBL */
-#define ETH_DMABMR_RDP       0x007E0000U  /* RxDMA PBL */
-  #define ETH_DMABMR_RDP_1Beat    0x00020000U  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
-  #define ETH_DMABMR_RDP_2Beat    0x00040000U  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
-  #define ETH_DMABMR_RDP_4Beat    0x00080000U  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-  #define ETH_DMABMR_RDP_8Beat    0x00100000U  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-  #define ETH_DMABMR_RDP_16Beat   0x00200000U  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-  #define ETH_DMABMR_RDP_32Beat   0x00400000U  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */                
-  #define ETH_DMABMR_RDP_4xPBL_4Beat   0x01020000U  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-  #define ETH_DMABMR_RDP_4xPBL_8Beat   0x01040000U  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-  #define ETH_DMABMR_RDP_4xPBL_16Beat  0x01080000U  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-  #define ETH_DMABMR_RDP_4xPBL_32Beat  0x01100000U  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
-  #define ETH_DMABMR_RDP_4xPBL_64Beat  0x01200000U  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
-  #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */  
-#define ETH_DMABMR_FB        0x00010000U  /* Fixed Burst */
-#define ETH_DMABMR_RTPR      0x0000C000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_1_1     0x00000000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_2_1     0x00004000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_3_1     0x00008000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_4_1     0x0000C000U  /* Rx Tx priority ratio */  
-#define ETH_DMABMR_PBL    0x00003F00U  /* Programmable burst length */
-  #define ETH_DMABMR_PBL_1Beat    0x00000100U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
-  #define ETH_DMABMR_PBL_2Beat    0x00000200U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
-  #define ETH_DMABMR_PBL_4Beat    0x00000400U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-  #define ETH_DMABMR_PBL_8Beat    0x00000800U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-  #define ETH_DMABMR_PBL_16Beat   0x00001000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-  #define ETH_DMABMR_PBL_32Beat   0x00002000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
-  #define ETH_DMABMR_PBL_4xPBL_4Beat   0x01000100U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-  #define ETH_DMABMR_PBL_4xPBL_8Beat   0x01000200U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-  #define ETH_DMABMR_PBL_4xPBL_16Beat  0x01000400U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-  #define ETH_DMABMR_PBL_4xPBL_32Beat  0x01000800U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
-  #define ETH_DMABMR_PBL_4xPBL_64Beat  0x01001000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
-  #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
-#define ETH_DMABMR_EDE       0x00000080U  /* Enhanced Descriptor Enable */
-#define ETH_DMABMR_DSL       0x0000007CU  /* Descriptor Skip Length */
-#define ETH_DMABMR_DA        0x00000002U  /* DMA arbitration scheme */
-#define ETH_DMABMR_SR        0x00000001U  /* Software reset */
-
-/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
-#define ETH_DMATPDR_TPD      0xFFFFFFFFU  /* Transmit poll demand */
-
-/* Bit definition for Ethernet DMA Receive Poll Demand Register */
-#define ETH_DMARPDR_RPD      0xFFFFFFFFU  /* Receive poll demand  */
-
-/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
-#define ETH_DMARDLAR_SRL     0xFFFFFFFFU  /* Start of receive list */
-
-/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
-#define ETH_DMATDLAR_STL     0xFFFFFFFFU  /* Start of transmit list */
-
-/* Bit definition for Ethernet DMA Status Register */
-#define ETH_DMASR_TSTS       0x20000000U  /* Time-stamp trigger status */
-#define ETH_DMASR_PMTS       0x10000000U  /* PMT status */
-#define ETH_DMASR_MMCS       0x08000000U  /* MMC status */
-#define ETH_DMASR_EBS        0x03800000U  /* Error bits status */
-  /* combination with EBS[2:0] for GetFlagStatus function */
-  #define ETH_DMASR_EBS_DescAccess      0x02000000U  /* Error bits 0-data buffer, 1-desc. access */
-  #define ETH_DMASR_EBS_ReadTransf      0x01000000U  /* Error bits 0-write trnsf, 1-read transfr */
-  #define ETH_DMASR_EBS_DataTransfTx    0x00800000U  /* Error bits 0-Rx DMA, 1-Tx DMA */
-#define ETH_DMASR_TPS         0x00700000U  /* Transmit process state */
-  #define ETH_DMASR_TPS_Stopped         0x00000000U  /* Stopped - Reset or Stop Tx Command issued  */
-  #define ETH_DMASR_TPS_Fetching        0x00100000U  /* Running - fetching the Tx descriptor */
-  #define ETH_DMASR_TPS_Waiting         0x00200000U  /* Running - waiting for status */
-  #define ETH_DMASR_TPS_Reading         0x00300000U  /* Running - reading the data from host memory */
-  #define ETH_DMASR_TPS_Suspended       0x00600000U  /* Suspended - Tx Descriptor unavailabe */
-  #define ETH_DMASR_TPS_Closing         0x00700000U  /* Running - closing Rx descriptor */
-#define ETH_DMASR_RPS         0x000E0000U  /* Receive process state */
-  #define ETH_DMASR_RPS_Stopped         0x00000000U  /* Stopped - Reset or Stop Rx Command issued */
-  #define ETH_DMASR_RPS_Fetching        0x00020000U  /* Running - fetching the Rx descriptor */
-  #define ETH_DMASR_RPS_Waiting         0x00060000U  /* Running - waiting for packet */
-  #define ETH_DMASR_RPS_Suspended       0x00080000U  /* Suspended - Rx Descriptor unavailable */
-  #define ETH_DMASR_RPS_Closing         0x000A0000U  /* Running - closing descriptor */
-  #define ETH_DMASR_RPS_Queuing         0x000E0000U  /* Running - queuing the recieve frame into host memory */
-#define ETH_DMASR_NIS        0x00010000U  /* Normal interrupt summary */
-#define ETH_DMASR_AIS        0x00008000U  /* Abnormal interrupt summary */
-#define ETH_DMASR_ERS        0x00004000U  /* Early receive status */
-#define ETH_DMASR_FBES       0x00002000U  /* Fatal bus error status */
-#define ETH_DMASR_ETS        0x00000400U  /* Early transmit status */
-#define ETH_DMASR_RWTS       0x00000200U  /* Receive watchdog timeout status */
-#define ETH_DMASR_RPSS       0x00000100U  /* Receive process stopped status */
-#define ETH_DMASR_RBUS       0x00000080U  /* Receive buffer unavailable status */
-#define ETH_DMASR_RS         0x00000040U  /* Receive status */
-#define ETH_DMASR_TUS        0x00000020U  /* Transmit underflow status */
-#define ETH_DMASR_ROS        0x00000010U  /* Receive overflow status */
-#define ETH_DMASR_TJTS       0x00000008U  /* Transmit jabber timeout status */
-#define ETH_DMASR_TBUS       0x00000004U  /* Transmit buffer unavailable status */
-#define ETH_DMASR_TPSS       0x00000002U  /* Transmit process stopped status */
-#define ETH_DMASR_TS         0x00000001U  /* Transmit status */
-
-/* Bit definition for Ethernet DMA Operation Mode Register */
-#define ETH_DMAOMR_DTCEFD    0x04000000U  /* Disable Dropping of TCP/IP checksum error frames */
-#define ETH_DMAOMR_RSF       0x02000000U  /* Receive store and forward */
-#define ETH_DMAOMR_DFRF      0x01000000U  /* Disable flushing of received frames */
-#define ETH_DMAOMR_TSF       0x00200000U  /* Transmit store and forward */
-#define ETH_DMAOMR_FTF       0x00100000U  /* Flush transmit FIFO */
-#define ETH_DMAOMR_TTC       0x0001C000U  /* Transmit threshold control */
-  #define ETH_DMAOMR_TTC_64Bytes       0x00000000U  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
-  #define ETH_DMAOMR_TTC_128Bytes      0x00004000U  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
-  #define ETH_DMAOMR_TTC_192Bytes      0x00008000U  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
-  #define ETH_DMAOMR_TTC_256Bytes      0x0000C000U  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
-  #define ETH_DMAOMR_TTC_40Bytes       0x00010000U  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
-  #define ETH_DMAOMR_TTC_32Bytes       0x00014000U  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
-  #define ETH_DMAOMR_TTC_24Bytes       0x00018000U  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
-  #define ETH_DMAOMR_TTC_16Bytes       0x0001C000U  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
-#define ETH_DMAOMR_ST        0x00002000U  /* Start/stop transmission command */
-#define ETH_DMAOMR_FEF       0x00000080U  /* Forward error frames */
-#define ETH_DMAOMR_FUGF      0x00000040U  /* Forward undersized good frames */
-#define ETH_DMAOMR_RTC       0x00000018U  /* receive threshold control */
-  #define ETH_DMAOMR_RTC_64Bytes       0x00000000U  /* threshold level of the MTL Receive FIFO is 64 Bytes */
-  #define ETH_DMAOMR_RTC_32Bytes       0x00000008U  /* threshold level of the MTL Receive FIFO is 32 Bytes */
-  #define ETH_DMAOMR_RTC_96Bytes       0x00000010U  /* threshold level of the MTL Receive FIFO is 96 Bytes */
-  #define ETH_DMAOMR_RTC_128Bytes      0x00000018U  /* threshold level of the MTL Receive FIFO is 128 Bytes */
-#define ETH_DMAOMR_OSF       0x00000004U  /* operate on second frame */
-#define ETH_DMAOMR_SR        0x00000002U  /* Start/stop receive */
-
-/* Bit definition for Ethernet DMA Interrupt Enable Register */
-#define ETH_DMAIER_NISE      0x00010000U  /* Normal interrupt summary enable */
-#define ETH_DMAIER_AISE      0x00008000U  /* Abnormal interrupt summary enable */
-#define ETH_DMAIER_ERIE      0x00004000U  /* Early receive interrupt enable */
-#define ETH_DMAIER_FBEIE     0x00002000U  /* Fatal bus error interrupt enable */
-#define ETH_DMAIER_ETIE      0x00000400U  /* Early transmit interrupt enable */
-#define ETH_DMAIER_RWTIE     0x00000200U  /* Receive watchdog timeout interrupt enable */
-#define ETH_DMAIER_RPSIE     0x00000100U  /* Receive process stopped interrupt enable */
-#define ETH_DMAIER_RBUIE     0x00000080U  /* Receive buffer unavailable interrupt enable */
-#define ETH_DMAIER_RIE       0x00000040U  /* Receive interrupt enable */
-#define ETH_DMAIER_TUIE      0x00000020U  /* Transmit Underflow interrupt enable */
-#define ETH_DMAIER_ROIE      0x00000010U  /* Receive Overflow interrupt enable */
-#define ETH_DMAIER_TJTIE     0x00000008U  /* Transmit jabber timeout interrupt enable */
-#define ETH_DMAIER_TBUIE     0x00000004U  /* Transmit buffer unavailable interrupt enable */
-#define ETH_DMAIER_TPSIE     0x00000002U  /* Transmit process stopped interrupt enable */
-#define ETH_DMAIER_TIE       0x00000001U  /* Transmit interrupt enable */
-
-/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
-#define ETH_DMAMFBOCR_OFOC   0x10000000U  /* Overflow bit for FIFO overflow counter */
-#define ETH_DMAMFBOCR_MFA    0x0FFE0000U  /* Number of frames missed by the application */
-#define ETH_DMAMFBOCR_OMFC   0x00010000U  /* Overflow bit for missed frame counter */
-#define ETH_DMAMFBOCR_MFC    0x0000FFFFU  /* Number of frames missed by the controller */
-
-/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
-#define ETH_DMACHTDR_HTDAP   0xFFFFFFFFU  /* Host transmit descriptor address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
-#define ETH_DMACHRDR_HRDAP   0xFFFFFFFFU  /* Host receive descriptor address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
-#define ETH_DMACHTBAR_HTBAP  0xFFFFFFFFU  /* Host transmit buffer address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
-#define ETH_DMACHRBAR_HRBAP  0xFFFFFFFFU  /* Host receive buffer address pointer */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                       USB_OTG			                        */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/
-#define USB_OTG_GOTGCTL_SRQSCS                  0x00000001U            /*!< Session request success  */
-#define USB_OTG_GOTGCTL_SRQ                     0x00000002U            /*!< Session request          */
-#define USB_OTG_GOTGCTL_HNGSCS                  0x00000100U            /*!< Host negotiation success */
-#define USB_OTG_GOTGCTL_HNPRQ                   0x00000200U            /*!< HNP request              */
-#define USB_OTG_GOTGCTL_HSHNPEN                 0x00000400U            /*!< Host set HNP enable      */
-#define USB_OTG_GOTGCTL_DHNPEN                  0x00000800U            /*!< Device HNP enabled       */
-#define USB_OTG_GOTGCTL_CIDSTS                  0x00010000U            /*!< Connector ID status      */
-#define USB_OTG_GOTGCTL_DBCT                    0x00020000U            /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD                   0x00040000U            /*!< A-session valid          */
-#define USB_OTG_GOTGCTL_BSVLD                   0x00080000U            /*!< B-session valid          */
-
-/********************  Bit definition forUSB_OTG_HCFG register  ********************/
-
-#define USB_OTG_HCFG_FSLSPCS                 0x00000003U            /*!< FS/LS PHY clock select  */
-#define USB_OTG_HCFG_FSLSPCS_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCFG_FSLSPCS_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCFG_FSLSS                   0x00000004U            /*!< FS- and LS-only support */
-
-/********************  Bit definition forUSB_OTG_DCFG register  ********************/
-
-#define USB_OTG_DCFG_DSPD                    0x00000003U            /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                  0x00000001U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DSPD_1                  0x00000002U            /*!<Bit 1 */
-#define USB_OTG_DCFG_NZLSOHSK                0x00000004U            /*!< Nonzero-length status OUT handshake */
-
-#define USB_OTG_DCFG_DAD                     0x000007F0U            /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                   0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DAD_1                   0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCFG_DAD_2                   0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCFG_DAD_3                   0x00000080U            /*!<Bit 3 */
-#define USB_OTG_DCFG_DAD_4                   0x00000100U            /*!<Bit 4 */
-#define USB_OTG_DCFG_DAD_5                   0x00000200U            /*!<Bit 5 */
-#define USB_OTG_DCFG_DAD_6                   0x00000400U            /*!<Bit 6 */
-
-#define USB_OTG_DCFG_PFIVL                   0x00001800U            /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PFIVL_1                 0x00001000U            /*!<Bit 1 */
-
-#define USB_OTG_DCFG_PERSCHIVL               0x03000000U            /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0             0x01000000U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PERSCHIVL_1             0x02000000U            /*!<Bit 1 */
-
-/********************  Bit definition forUSB_OTG_PCGCR register  ********************/
-#define USB_OTG_PCGCR_STPPCLK                 0x00000001U            /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK                0x00000002U            /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP                 0x00000010U            /*!< PHY suspended */
-
-/********************  Bit definition forUSB_OTG_GOTGINT register  ********************/
-#define USB_OTG_GOTGINT_SEDET                   0x00000004U            /*!< Session end detected                   */
-#define USB_OTG_GOTGINT_SRSSCHG                 0x00000100U            /*!< Session request success status change  */
-#define USB_OTG_GOTGINT_HNSSCHG                 0x00000200U            /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET                  0x00020000U            /*!< Host negotiation detected              */
-#define USB_OTG_GOTGINT_ADTOCHG                 0x00040000U            /*!< A-device timeout change                */
-#define USB_OTG_GOTGINT_DBCDNE                  0x00080000U            /*!< Debounce done                          */
-
-/********************  Bit definition forUSB_OTG_DCTL register  ********************/
-#define USB_OTG_DCTL_RWUSIG                  0x00000001U            /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS                    0x00000002U            /*!< Soft disconnect         */
-#define USB_OTG_DCTL_GINSTS                  0x00000004U            /*!< Global IN NAK status    */
-#define USB_OTG_DCTL_GONSTS                  0x00000008U            /*!< Global OUT NAK status   */
-
-#define USB_OTG_DCTL_TCTL                    0x00000070U            /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                  0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCTL_TCTL_1                  0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCTL_TCTL_2                  0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCTL_SGINAK                  0x00000080U            /*!< Set global IN NAK         */
-#define USB_OTG_DCTL_CGINAK                  0x00000100U            /*!< Clear global IN NAK       */
-#define USB_OTG_DCTL_SGONAK                  0x00000200U            /*!< Set global OUT NAK        */
-#define USB_OTG_DCTL_CGONAK                  0x00000400U            /*!< Clear global OUT NAK      */
-#define USB_OTG_DCTL_POPRGDNE                0x00000800U            /*!< Power-on programming done */
-
-/********************  Bit definition forUSB_OTG_HFIR register  ********************/
-#define USB_OTG_HFIR_FRIVL                   0x0000FFFFU            /*!< Frame interval */
-
-/********************  Bit definition forUSB_OTG_HFNUM register  ********************/
-#define USB_OTG_HFNUM_FRNUM                   0x0000FFFFU            /*!< Frame number         */
-#define USB_OTG_HFNUM_FTREM                   0xFFFF0000U            /*!< Frame time remaining */
-
-/********************  Bit definition forUSB_OTG_DSTS register  ********************/
-#define USB_OTG_DSTS_SUSPSTS                 0x00000001U            /*!< Suspend status   */
-
-#define USB_OTG_DSTS_ENUMSPD                 0x00000006U            /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_DSTS_ENUMSPD_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_DSTS_EERR                    0x00000008U            /*!< Erratic error     */
-#define USB_OTG_DSTS_FNSOF                   0x003FFF00U            /*!< Frame number of the received SOF */
-
-/********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/
-#define USB_OTG_GAHBCFG_GINT                    0x00000001U            /*!< Global interrupt mask */
-
-#define USB_OTG_GAHBCFG_HBSTLEN                 0x0000001EU            /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_GAHBCFG_HBSTLEN_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_GAHBCFG_HBSTLEN_2               0x00000008U            /*!<Bit 2 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3               0x00000010U            /*!<Bit 3 */
-#define USB_OTG_GAHBCFG_DMAEN                   0x00000020U            /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL                 0x00000080U            /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL                0x00000100U            /*!< Periodic TxFIFO empty level */
-
-/********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/
-
-#define USB_OTG_GUSBCFG_TOCAL                   0x00000007U            /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TOCAL_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TOCAL_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_PHYSEL                  0x00000040U            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP                  0x00000100U            /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP                  0x00000200U            /*!< HNP-capable */
-
-#define USB_OTG_GUSBCFG_TRDT                    0x00003C00U            /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                  0x00000400U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TRDT_1                  0x00000800U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TRDT_2                  0x00001000U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_TRDT_3                  0x00002000U            /*!<Bit 3 */
-#define USB_OTG_GUSBCFG_PHYLPCS                 0x00008000U            /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS                0x00020000U            /*!< ULPI FS/LS select               */
-#define USB_OTG_GUSBCFG_ULPIAR                  0x00040000U            /*!< ULPI Auto-resume                */
-#define USB_OTG_GUSBCFG_ULPICSM                 0x00080000U            /*!< ULPI Clock SuspendM             */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD              0x00100000U            /*!< ULPI External VBUS Drive        */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI              0x00200000U            /*!< ULPI external VBUS indicator    */
-#define USB_OTG_GUSBCFG_TSDPS                   0x00400000U            /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI                    0x00800000U            /*!< Indicator complement            */
-#define USB_OTG_GUSBCFG_PTCI                    0x01000000U            /*!< Indicator pass through          */
-#define USB_OTG_GUSBCFG_ULPIIPD                 0x02000000U            /*!< ULPI interface protect disable  */
-#define USB_OTG_GUSBCFG_FHMOD                   0x20000000U            /*!< Forced host mode                */
-#define USB_OTG_GUSBCFG_FDMOD                   0x40000000U            /*!< Forced peripheral mode          */
-#define USB_OTG_GUSBCFG_CTXPKT                  0x80000000U            /*!< Corrupt Tx packet               */
-
-/********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
-#define USB_OTG_GRSTCTL_CSRST                   0x00000001U            /*!< Core soft reset          */
-#define USB_OTG_GRSTCTL_HSRST                   0x00000002U            /*!< HCLK soft reset          */
-#define USB_OTG_GRSTCTL_FCRST                   0x00000004U            /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH                 0x00000010U            /*!< RxFIFO flush             */
-#define USB_OTG_GRSTCTL_TXFFLSH                 0x00000020U            /*!< TxFIFO flush             */
-
-#define USB_OTG_GRSTCTL_TXFNUM                  0x000007C0U            /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                0x00000040U            /*!<Bit 0 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                0x00000080U            /*!<Bit 1 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                0x00000100U            /*!<Bit 2 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                0x00000200U            /*!<Bit 3 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                0x00000400U            /*!<Bit 4 */
-#define USB_OTG_GRSTCTL_DMAREQ                  0x40000000U            /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL                  0x80000000U            /*!< AHB master idle */
-
-/********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/
-#define USB_OTG_DIEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask                 */
-#define USB_OTG_DIEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask                  */
-#define USB_OTG_DIEPMSK_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask          */
-#define USB_OTG_DIEPMSK_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask           */
-#define USB_OTG_DIEPMSK_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask                    */
-#define USB_OTG_DIEPMSK_TXFURM                  0x00000100U            /*!< FIFO underrun mask                                */
-#define USB_OTG_DIEPMSK_BIM                     0x00000200U            /*!< BNA interrupt mask                                */
-
-/********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/
-#define USB_OTG_HPTXSTS_PTXFSAVL                0x0000FFFFU            /*!< Periodic transmit data FIFO space available     */
-
-#define USB_OTG_HPTXSTS_PTXQSAV                 0x00FF0000U            /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0               0x00010000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1               0x00020000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2               0x00040000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3               0x00080000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4               0x00100000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5               0x00200000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6               0x00400000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7               0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_HPTXSTS_PTXQTOP                 0xFF000000U            /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0               0x01000000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1               0x02000000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2               0x04000000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3               0x08000000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4               0x10000000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5               0x20000000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6               0x40000000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7               0x80000000U            /*!<Bit 7 */
-
-/********************  Bit definition forUSB_OTG_HAINT register  ********************/
-#define USB_OTG_HAINT_HAINT                   0x0000FFFFU            /*!< Channel interrupts */
-
-/********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/
-#define USB_OTG_DOEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask               */
-#define USB_OTG_DOEPMSK_STUPM                   0x00000008U            /*!< SETUP phase done mask                          */
-#define USB_OTG_DOEPMSK_OTEPDM                  0x00000010U            /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received mask       */
-#define USB_OTG_DOEPMSK_OPEM                    0x00000100U            /*!< OUT packet error mask                          */
-#define USB_OTG_DOEPMSK_BOIM                    0x00000200U            /*!< BNA interrupt mask                             */
-
-/********************  Bit definition forUSB_OTG_GINTSTS register  ********************/
-#define USB_OTG_GINTSTS_CMOD                    0x00000001U            /*!< Current mode of operation           */
-#define USB_OTG_GINTSTS_MMIS                    0x00000002U            /*!< Mode mismatch interrupt             */
-#define USB_OTG_GINTSTS_OTGINT                  0x00000004U            /*!< OTG interrupt                       */
-#define USB_OTG_GINTSTS_SOF                     0x00000008U            /*!< Start of frame                      */
-#define USB_OTG_GINTSTS_RXFLVL                  0x00000010U            /*!< RxFIFO nonempty                     */
-#define USB_OTG_GINTSTS_NPTXFE                  0x00000020U            /*!< Nonperiodic TxFIFO empty            */
-#define USB_OTG_GINTSTS_GINAKEFF                0x00000040U            /*!< Global IN nonperiodic NAK effective */
-#define USB_OTG_GINTSTS_BOUTNAKEFF              0x00000080U            /*!< Global OUT NAK effective            */
-#define USB_OTG_GINTSTS_ESUSP                   0x00000400U            /*!< Early suspend                            */
-#define USB_OTG_GINTSTS_USBSUSP                 0x00000800U            /*!< USB suspend                              */
-#define USB_OTG_GINTSTS_USBRST                  0x00001000U            /*!< USB reset                                */
-#define USB_OTG_GINTSTS_ENUMDNE                 0x00002000U            /*!< Enumeration done                         */
-#define USB_OTG_GINTSTS_ISOODRP                 0x00004000U            /*!< Isochronous OUT packet dropped interrupt */
-#define USB_OTG_GINTSTS_EOPF                    0x00008000U            /*!< End of periodic frame interrupt          */
-#define USB_OTG_GINTSTS_IEPINT                  0x00040000U            /*!< IN endpoint interrupt                          */
-#define USB_OTG_GINTSTS_OEPINT                  0x00080000U            /*!< OUT endpoint interrupt                         */
-#define USB_OTG_GINTSTS_IISOIXFR                0x00100000U            /*!< Incomplete isochronous IN transfer             */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       0x00200000U            /*!< Incomplete periodic transfer                   */
-#define USB_OTG_GINTSTS_DATAFSUSP               0x00400000U            /*!< Data fetch suspended                           */
-#define USB_OTG_GINTSTS_HPRTINT                 0x01000000U            /*!< Host port interrupt                            */
-#define USB_OTG_GINTSTS_HCINT                   0x02000000U            /*!< Host channels interrupt                        */
-#define USB_OTG_GINTSTS_PTXFE                   0x04000000U            /*!< Periodic TxFIFO empty                          */
-#define USB_OTG_GINTSTS_CIDSCHG                 0x10000000U            /*!< Connector ID status change                     */
-#define USB_OTG_GINTSTS_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt                  */
-#define USB_OTG_GINTSTS_SRQINT                  0x40000000U            /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT                  0x80000000U            /*!< Resume/remote wakeup detected interrupt        */
-
-/********************  Bit definition forUSB_OTG_GINTMSK register  ********************/
-#define USB_OTG_GINTMSK_MMISM                   0x00000002U            /*!< Mode mismatch interrupt mask                        */
-#define USB_OTG_GINTMSK_OTGINT                  0x00000004U            /*!< OTG interrupt mask                                  */
-#define USB_OTG_GINTMSK_SOFM                    0x00000008U            /*!< Start of frame mask                                 */
-#define USB_OTG_GINTMSK_RXFLVLM                 0x00000010U            /*!< Receive FIFO nonempty mask                          */
-#define USB_OTG_GINTMSK_NPTXFEM                 0x00000020U            /*!< Nonperiodic TxFIFO empty mask                       */
-#define USB_OTG_GINTMSK_GINAKEFFM               0x00000040U            /*!< Global nonperiodic IN NAK effective mask            */
-#define USB_OTG_GINTMSK_GONAKEFFM               0x00000080U            /*!< Global OUT NAK effective mask                       */
-#define USB_OTG_GINTMSK_ESUSPM                  0x00000400U            /*!< Early suspend mask                                  */
-#define USB_OTG_GINTMSK_USBSUSPM                0x00000800U            /*!< USB suspend mask                                    */
-#define USB_OTG_GINTMSK_USBRST                  0x00001000U            /*!< USB reset mask                                      */
-#define USB_OTG_GINTMSK_ENUMDNEM                0x00002000U            /*!< Enumeration done mask                               */
-#define USB_OTG_GINTMSK_ISOODRPM                0x00004000U            /*!< Isochronous OUT packet dropped interrupt mask       */
-#define USB_OTG_GINTMSK_EOPFM                   0x00008000U            /*!< End of periodic frame interrupt mask                */
-#define USB_OTG_GINTMSK_EPMISM                  0x00020000U            /*!< Endpoint mismatch interrupt mask                    */
-#define USB_OTG_GINTMSK_IEPINT                  0x00040000U            /*!< IN endpoints interrupt mask                         */
-#define USB_OTG_GINTMSK_OEPINT                  0x00080000U            /*!< OUT endpoints interrupt mask                        */
-#define USB_OTG_GINTMSK_IISOIXFRM               0x00100000U            /*!< Incomplete isochronous IN transfer mask             */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         0x00200000U            /*!< Incomplete periodic transfer mask                   */
-#define USB_OTG_GINTMSK_FSUSPM                  0x00400000U            /*!< Data fetch suspended mask                           */
-#define USB_OTG_GINTMSK_PRTIM                   0x01000000U            /*!< Host port interrupt mask                            */
-#define USB_OTG_GINTMSK_HCIM                    0x02000000U            /*!< Host channels interrupt mask                        */
-#define USB_OTG_GINTMSK_PTXFEM                  0x04000000U            /*!< Periodic TxFIFO empty mask                          */
-#define USB_OTG_GINTMSK_CIDSCHGM                0x10000000U            /*!< Connector ID status change mask                     */
-#define USB_OTG_GINTMSK_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt mask                  */
-#define USB_OTG_GINTMSK_SRQIM                   0x40000000U            /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM                    0x80000000U            /*!< Resume/remote wakeup detected interrupt mask        */
-
-/********************  Bit definition forUSB_OTG_DAINT register  ********************/
-#define USB_OTG_DAINT_IEPINT                  0x0000FFFFU            /*!< IN endpoint interrupt bits  */
-#define USB_OTG_DAINT_OEPINT                  0xFFFF0000U            /*!< OUT endpoint interrupt bits */
-
-/********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/
-#define USB_OTG_HAINTMSK_HAINTM                  0x0000FFFFU            /*!< Channel interrupt mask */
-
-/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
-#define USB_OTG_GRXSTSP_EPNUM                    0x0000000FU            /*!< IN EP interrupt mask bits  */
-#define USB_OTG_GRXSTSP_BCNT                     0x00007FF0U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID                     0x00018000U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS                   0x001E0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/
-#define USB_OTG_DAINTMSK_IEPM                    0x0000FFFFU            /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM                    0xFFFF0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for OTG register  ********************/
-
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition for OTG register  ********************/
-
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/
-#define USB_OTG_GRXFSIZ_RXFD            0x0000FFFFU            /*!< RxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/
-#define USB_OTG_DVBUSDIS_VBUSDT         0x0000FFFFU            /*!< Device VBUS discharge time */
-
-/********************  Bit definition for OTG register  ********************/
-#define USB_OTG_NPTXFSA                 0x0000FFFFU            /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD                  0xFFFF0000U            /*!< Nonperiodic TxFIFO depth               */
-#define USB_OTG_TX0FSA                  0x0000FFFFU            /*!< Endpoint 0 transmit RAM start address  */
-#define USB_OTG_TX0FD                   0xFFFF0000U            /*!< Endpoint 0 TxFIFO depth                */
-
-/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
-#define USB_OTG_DVBUSPULSE_DVBUSP                  0x00000FFFU            /*!< Device VBUS pulsing time */
-
-/********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/
-#define USB_OTG_GNPTXSTS_NPTXFSAV                0x0000FFFFU            /*!< Nonperiodic TxFIFO space available */
-
-#define USB_OTG_GNPTXSTS_NPTQXSAV                0x00FF0000U            /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0              0x00010000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1              0x00020000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2              0x00040000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3              0x00080000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4              0x00100000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5              0x00200000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6              0x00400000U            /*!<Bit 6 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7              0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_GNPTXSTS_NPTXQTOP                0x7F000000U            /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0              0x01000000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1              0x02000000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2              0x04000000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3              0x08000000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4              0x10000000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5              0x20000000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6              0x40000000U            /*!<Bit 6 */
-
-/********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/
-#define USB_OTG_DTHRCTL_NONISOTHREN             0x00000001U            /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN                0x00000002U            /*!< ISO IN endpoint threshold enable */
-
-#define USB_OTG_DTHRCTL_TXTHRLEN                0x000007FCU            /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0              0x00000004U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1              0x00000008U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2              0x00000010U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3              0x00000020U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4              0x00000040U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5              0x00000080U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6              0x00000100U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7              0x00000200U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8              0x00000400U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_RXTHREN                 0x00010000U            /*!< Receive threshold enable */
-
-#define USB_OTG_DTHRCTL_RXTHRLEN                0x03FE0000U            /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0              0x00020000U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1              0x00040000U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2              0x00080000U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3              0x00100000U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4              0x00200000U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5              0x00400000U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6              0x00800000U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7              0x01000000U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8              0x02000000U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_ARPEN                   0x08000000U            /*!< Arbiter parking enable */
-
-/********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM               0x0000FFFFU            /*!< IN EP Tx FIFO empty interrupt mask bits */
-
-/********************  Bit definition forUSB_OTG_DEACHINT register  ********************/
-#define USB_OTG_DEACHINT_IEP1INT                 0x00000002U            /*!< IN endpoint 1interrupt bit   */
-#define USB_OTG_DEACHINT_OEP1INT                 0x00020000U            /*!< OUT endpoint 1 interrupt bit */
-
-/********************  Bit definition forUSB_OTG_GCCFG register  ********************/
-#define USB_OTG_GCCFG_PWRDWN                  0x00010000U            /*!< Power down */
-#define USB_OTG_GCCFG_I2CPADEN                0x00020000U            /*!< Enable I2C bus connection for the external I2C PHY interface */
-#define USB_OTG_GCCFG_VBUSASEN                0x00040000U            /*!< Enable the VBUS sensing device                               */
-#define USB_OTG_GCCFG_VBUSBSEN                0x00080000U            /*!< Enable the VBUS sensing device                               */
-#define USB_OTG_GCCFG_SOFOUTEN                0x00100000U            /*!< SOF output enable                                            */
-#define USB_OTG_GCCFG_NOVBUSSENS              0x00200000U            /*!< VBUS sensing disable option                                  */
-
-/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
-#define USB_OTG_DEACHINTMSK_IEP1INTM                0x00000002U            /*!< IN Endpoint 1 interrupt mask bit  */
-#define USB_OTG_DEACHINTMSK_OEP1INTM                0x00020000U            /*!< OUT Endpoint 1 interrupt mask bit */
-
-/********************  Bit definition forUSB_OTG_CID register  ********************/
-#define USB_OTG_CID_PRODUCT_ID              0xFFFFFFFFU            /*!< Product ID field */
-
-/********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/
-#define USB_OTG_DIEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask                 */
-#define USB_OTG_DIEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask                  */
-#define USB_OTG_DIEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask          */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask           */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask                    */
-#define USB_OTG_DIEPEACHMSK1_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
-
-/********************  Bit definition forUSB_OTG_HPRT register  ********************/
-#define USB_OTG_HPRT_PCSTS                   0x00000001U            /*!< Port connect status        */
-#define USB_OTG_HPRT_PCDET                   0x00000002U            /*!< Port connect detected      */
-#define USB_OTG_HPRT_PENA                    0x00000004U            /*!< Port enable                */
-#define USB_OTG_HPRT_PENCHNG                 0x00000008U            /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA                    0x00000010U            /*!< Port overcurrent active    */
-#define USB_OTG_HPRT_POCCHNG                 0x00000020U            /*!< Port overcurrent change    */
-#define USB_OTG_HPRT_PRES                    0x00000040U            /*!< Port resume   */
-#define USB_OTG_HPRT_PSUSP                   0x00000080U            /*!< Port suspend  */
-#define USB_OTG_HPRT_PRST                    0x00000100U            /*!< Port reset    */
-
-#define USB_OTG_HPRT_PLSTS                   0x00000C00U            /*!< Port line status */
-#define USB_OTG_HPRT_PLSTS_0                 0x00000400U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PLSTS_1                 0x00000800U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PPWR                    0x00001000U            /*!< Port power */
-
-#define USB_OTG_HPRT_PTCTL                   0x0001E000U            /*!< Port test control */
-#define USB_OTG_HPRT_PTCTL_0                 0x00002000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PTCTL_1                 0x00004000U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PTCTL_2                 0x00008000U            /*!<Bit 2 */
-#define USB_OTG_HPRT_PTCTL_3                 0x00010000U            /*!<Bit 3 */
-
-#define USB_OTG_HPRT_PSPD                    0x00060000U            /*!< Port speed */
-#define USB_OTG_HPRT_PSPD_0                  0x00020000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PSPD_1                  0x00040000U            /*!<Bit 1 */
-
-/********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/
-#define USB_OTG_DOEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DOEPEACHMSK1_TXFURM                  0x00000100U            /*!< OUT packet error mask */
-#define USB_OTG_DOEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_BERRM                   0x00001000U            /*!< Bubble error interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NYETM                   0x00004000U            /*!< NYET interrupt mask */
-
-/********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/
-#define USB_OTG_HPTXFSIZ_PTXSA                   0x0000FFFFU            /*!< Host periodic TxFIFO start address */
-#define USB_OTG_HPTXFSIZ_PTXFD                   0xFFFF0000U            /*!< Host periodic TxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/
-#define USB_OTG_DIEPCTL_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
-#define USB_OTG_DIEPCTL_USBAEP                  0x00008000U            /*!< USB active endpoint */
-#define USB_OTG_DIEPCTL_EONUM_DPID              0x00010000U            /*!< Even/odd frame */
-#define USB_OTG_DIEPCTL_NAKSTS                  0x00020000U            /*!< NAK status */
-
-#define USB_OTG_DIEPCTL_EPTYP                   0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_DIEPCTL_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_STALL                   0x00200000U            /*!< STALL handshake */
-
-#define USB_OTG_DIEPCTL_TXFNUM                  0x03C00000U            /*!< TxFIFO number */
-#define USB_OTG_DIEPCTL_TXFNUM_0                0x00400000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                0x00800000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                0x01000000U            /*!<Bit 2 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                0x02000000U            /*!<Bit 3 */
-#define USB_OTG_DIEPCTL_CNAK                    0x04000000U            /*!< Clear NAK */
-#define USB_OTG_DIEPCTL_SNAK                    0x08000000U            /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          0x10000000U            /*!< Set DATA0 PID */
-#define USB_OTG_DIEPCTL_SODDFRM                 0x20000000U            /*!< Set odd frame */
-#define USB_OTG_DIEPCTL_EPDIS                   0x40000000U            /*!< Endpoint disable */
-#define USB_OTG_DIEPCTL_EPENA                   0x80000000U            /*!< Endpoint enable */
-
-/********************  Bit definition forUSB_OTG_HCCHAR register  ********************/
-#define USB_OTG_HCCHAR_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
-
-#define USB_OTG_HCCHAR_EPNUM                   0x00007800U            /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPNUM_1                 0x00001000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_EPNUM_2                 0x00002000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_EPNUM_3                 0x00004000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_EPDIR                   0x00008000U            /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV                   0x00020000U            /*!< Low-speed device */
-
-#define USB_OTG_HCCHAR_EPTYP                   0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_MC                      0x00300000U            /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                    0x00100000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_MC_1                    0x00200000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_DAD                     0x1FC00000U            /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                   0x00400000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_DAD_1                   0x00800000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_DAD_2                   0x01000000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_DAD_3                   0x02000000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_DAD_4                   0x04000000U            /*!<Bit 4 */
-#define USB_OTG_HCCHAR_DAD_5                   0x08000000U            /*!<Bit 5 */
-#define USB_OTG_HCCHAR_DAD_6                   0x10000000U            /*!<Bit 6 */
-#define USB_OTG_HCCHAR_ODDFRM                  0x20000000U            /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS                   0x40000000U            /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA                   0x80000000U            /*!< Channel enable */
-
-/********************  Bit definition forUSB_OTG_HCSPLT register  ********************/
-
-#define USB_OTG_HCSPLT_PRTADDR                 0x0000007FU            /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_PRTADDR_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_PRTADDR_2               0x00000004U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_PRTADDR_3               0x00000008U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_PRTADDR_4               0x00000010U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_PRTADDR_5               0x00000020U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_PRTADDR_6               0x00000040U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_HUBADDR                 0x00003F80U            /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0               0x00000080U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_HUBADDR_1               0x00000100U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_HUBADDR_2               0x00000200U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_HUBADDR_3               0x00000400U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_HUBADDR_4               0x00000800U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_HUBADDR_5               0x00001000U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_HUBADDR_6               0x00002000U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_XACTPOS                 0x0000C000U            /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0               0x00004000U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_XACTPOS_1               0x00008000U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_COMPLSPLT               0x00010000U            /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN                 0x80000000U            /*!< Split enable */
-
-/********************  Bit definition forUSB_OTG_HCINT register  ********************/
-#define USB_OTG_HCINT_XFRC                    0x00000001U            /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH                     0x00000002U            /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINT_STALL                   0x00000008U            /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK                     0x00000010U            /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK                     0x00000020U            /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET                    0x00000040U            /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR                   0x00000080U            /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR                   0x00000100U            /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR                   0x00000200U            /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR                   0x00000400U            /*!< Data toggle error */
-
-/********************  Bit definition forUSB_OTG_DIEPINT register  ********************/
-#define USB_OTG_DIEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_TOC                     0x00000008U            /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE                  0x00000010U            /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNE                  0x00000040U            /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE                    0x00000080U            /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN              0x00000100U            /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA                     0x00000200U            /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS               0x00000800U            /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR                    0x00001000U            /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK                     0x00002000U            /*!< NAK interrupt */
-
-/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
-#define USB_OTG_HCINTMSK_XFRCM                   0x00000001U            /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM                    0x00000002U            /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM                  0x00000008U            /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM                    0x00000010U            /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM                    0x00000020U            /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET                    0x00000040U            /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM                  0x00000080U            /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM                  0x00000100U            /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM                  0x00000200U            /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM                  0x00000400U            /*!< Data toggle error mask */
-
-/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
-
-#define USB_OTG_DIEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT                  0x60000000U            /*!< Packet count */
-/********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/
-#define USB_OTG_HCTSIZ_XFRSIZ                    0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT                    0x1FF80000U            /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING                    0x80000000U            /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID                      0x60000000U            /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                    0x20000000U            /*!<Bit 0 */
-#define USB_OTG_HCTSIZ_DPID_1                    0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/
-#define USB_OTG_DIEPDMA_DMAADDR                  0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition forUSB_OTG_HCDMA register  ********************/
-#define USB_OTG_HCDMA_DMAADDR                    0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/
-#define USB_OTG_DTXFSTS_INEPTFSAV                0x0000FFFFU            /*!< IN endpoint TxFIFO space available */
-
-/********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/
-#define USB_OTG_DIEPTXF_INEPTXSA                 0x0000FFFFU            /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD                 0xFFFF0000U            /*!< IN endpoint TxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/
-
-#define USB_OTG_DOEPCTL_MPSIZ                     0x000007FFU            /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP                    0x00008000U            /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS                    0x00020000U            /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            0x10000000U            /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM                   0x20000000U            /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP                     0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                   0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DOEPCTL_EPTYP_1                   0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_SNPM                      0x00100000U            /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL                     0x00200000U            /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK                      0x04000000U            /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK                      0x08000000U            /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS                     0x40000000U            /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA                     0x80000000U            /*!< Endpoint enable */
-
-/********************  Bit definition forUSB_OTG_DOEPINT register  ********************/
-#define USB_OTG_DOEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_STUP                    0x00000008U            /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS                 0x00000010U            /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_NYET                    0x00004000U            /*!< NYET interrupt */
-
-/********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/
-
-#define USB_OTG_DOEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-
-#define USB_OTG_DOEPTSIZ_STUPCNT                 0x60000000U            /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0               0x20000000U            /*!<Bit 0 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1               0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition for PCGCCTL register  ********************/
-#define USB_OTG_PCGCCTL_STOPCLK                 0x00000001U            /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK                 0x00000002U            /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP                 0x00000010U            /*!<Bit 1 */
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
-                                       ((INSTANCE) == ADC2) || \
-                                       ((INSTANCE) == ADC3))
-
-/******************************* CAN Instances ********************************/
-#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
-                                       ((INSTANCE) == CAN2))
- 
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DAC Instances ********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/******************************* DCMI Instances *******************************/
-#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
-
-/******************************* DMA2D Instances *******************************/
-#define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
-
-/******************************** DMA Instances *******************************/
-#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
-                                              ((INSTANCE) == DMA1_Stream1) || \
-                                              ((INSTANCE) == DMA1_Stream2) || \
-                                              ((INSTANCE) == DMA1_Stream3) || \
-                                              ((INSTANCE) == DMA1_Stream4) || \
-                                              ((INSTANCE) == DMA1_Stream5) || \
-                                              ((INSTANCE) == DMA1_Stream6) || \
-                                              ((INSTANCE) == DMA1_Stream7) || \
-                                              ((INSTANCE) == DMA2_Stream0) || \
-                                              ((INSTANCE) == DMA2_Stream1) || \
-                                              ((INSTANCE) == DMA2_Stream2) || \
-                                              ((INSTANCE) == DMA2_Stream3) || \
-                                              ((INSTANCE) == DMA2_Stream4) || \
-                                              ((INSTANCE) == DMA2_Stream5) || \
-                                              ((INSTANCE) == DMA2_Stream6) || \
-                                              ((INSTANCE) == DMA2_Stream7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOF) || \
-                                        ((INSTANCE) == GPIOG) || \
-                                        ((INSTANCE) == GPIOH) || \
-                                        ((INSTANCE) == GPIOI) || \
-                                        ((INSTANCE) == GPIOJ) || \
-                                        ((INSTANCE) == GPIOK))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2) || \
-                                       ((INSTANCE) == I2C3))
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI2) || \
-                                        ((INSTANCE) == SPI3))
-
-/*************************** I2S Extended Instances ***************************/
-#define IS_I2S_ALL_INSTANCE_EXT(PERIPH)  (((INSTANCE) == SPI2)    || \
-                                          ((INSTANCE) == SPI3)    || \
-                                          ((INSTANCE) == I2S2ext) || \
-                                          ((INSTANCE) == I2S3ext))
-
-/****************************** LTDC Instances ********************************/
-#define IS_LTDC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == LTDC)
-
-/******************************* RNG Instances ********************************/
-#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************* SAI Instances ********************************/
-#define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
-                                     ((PERIPH) == SAI1_Block_B))
-/* Legacy define */
-#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3) || \
-                                       ((INSTANCE) == SPI4) || \
-                                       ((INSTANCE) == SPI5) || \
-                                       ((INSTANCE) == SPI6))
-
-/*************************** SPI Extended Instances ***************************/
-#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1)    || \
-                                           ((INSTANCE) == SPI2)    || \
-                                           ((INSTANCE) == SPI3)    || \
-                                           ((INSTANCE) == SPI4)    || \
-                                           ((INSTANCE) == SPI5)    || \
-                                           ((INSTANCE) == SPI6)    || \
-                                           ((INSTANCE) == I2S2ext) || \
-                                           ((INSTANCE) == I2S3ext))
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
-                                   ((INSTANCE) == TIM2)   || \
-                                   ((INSTANCE) == TIM3)   || \
-                                   ((INSTANCE) == TIM4)   || \
-                                   ((INSTANCE) == TIM5)   || \
-                                   ((INSTANCE) == TIM6)   || \
-                                   ((INSTANCE) == TIM7)   || \
-                                   ((INSTANCE) == TIM8)   || \
-                                   ((INSTANCE) == TIM9)   || \
-                                   ((INSTANCE) == TIM10)  || \
-                                   ((INSTANCE) == TIM11)  || \
-                                   ((INSTANCE) == TIM12)  || \
-                                   ((INSTANCE) == TIM13)  || \
-                                   ((INSTANCE) == TIM14))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
-                                         ((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM8)  || \
-                                         ((INSTANCE) == TIM9)  || \
-                                         ((INSTANCE) == TIM10) || \
-                                         ((INSTANCE) == TIM11) || \
-                                         ((INSTANCE) == TIM12) || \
-                                         ((INSTANCE) == TIM13) || \
-                                         ((INSTANCE) == TIM14))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM8) || \
-                                       ((INSTANCE) == TIM9) || \
-                                       ((INSTANCE) == TIM12))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8))
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM8))
-
-/******************** TIM Instances : Advanced-control timers *****************/
-#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                            ((INSTANCE) == TIM8))
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8))
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM6) || \
-                                       ((INSTANCE) == TIM7) || \
-                                       ((INSTANCE) == TIM8))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM8))
-
-/************ TIM Instances : DMA requests generation (COMDE) *****************/
-#define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM8)) 
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                             ((INSTANCE) == TIM2) || \
-                                             ((INSTANCE) == TIM3) || \
-                                             ((INSTANCE) == TIM4) || \
-                                             ((INSTANCE) == TIM5) || \
-                                             ((INSTANCE) == TIM8))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM6) || \
-                                          ((INSTANCE) == TIM7) || \
-                                          ((INSTANCE) == TIM8) || \
-                                          ((INSTANCE) == TIM9) || \
-                                          ((INSTANCE) == TIM12))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8) || \
-                                         ((INSTANCE) == TIM9) || \
-                                         ((INSTANCE) == TIM12))
-
-/********************** TIM Instances : 32 bit Counter ************************/
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
-                                              ((INSTANCE) == TIM5))
-
-/***************** TIM Instances : external trigger input availabe ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                        ((INSTANCE) == TIM2) || \
-                                        ((INSTANCE) == TIM3) || \
-                                        ((INSTANCE) == TIM4) || \
-                                        ((INSTANCE) == TIM5) || \
-                                        ((INSTANCE) == TIM8))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM11))
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM1) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM5) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM8) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM12) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM13) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM14) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-/************ TIM Instances : complementary output(s) available ***************/
-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
-   ((((INSTANCE) == TIM1) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3)))            \
-    ||                                          \
-    (((INSTANCE) == TIM8) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3))))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3) || \
-                                     ((INSTANCE) == USART6))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5)  || \
-                                    ((INSTANCE) == USART6) || \
-                                    ((INSTANCE) == UART7)  || \
-                                    ((INSTANCE) == UART8))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3) || \
-                                           ((INSTANCE) == USART6))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3) || \
-                                         ((INSTANCE) == USART6))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5)  || \
-                                    ((INSTANCE) == USART6) || \
-                                    ((INSTANCE) == UART7)  || \
-                                    ((INSTANCE) == UART8))     
-
-/*********************** PCD Instances ****************************************/
-#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
-                                        ((INSTANCE) == USB_OTG_HS))
-
-/*********************** HCD Instances ****************************************/
-#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
-                                       ((INSTANCE) == USB_OTG_HS))
-
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/****************************** SDIO Instances ********************************/
-#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
-
-/****************************** USB Exported Constants ************************/
-#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                8U
-#define USB_OTG_FS_MAX_IN_ENDPOINTS                    4U    /* Including EP0 */
-#define USB_OTG_FS_MAX_OUT_ENDPOINTS                   4U    /* Including EP0 */
-#define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */
-
-#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR                12U
-#define USB_OTG_HS_MAX_IN_ENDPOINTS                    6U    /* Including EP0 */
-#define USB_OTG_HS_MAX_OUT_ENDPOINTS                   6U    /* Including EP0 */
-#define USB_OTG_HS_TOTAL_FIFO_SIZE                     4096U /* in Bytes */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32F4xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */
-/*  product lines within the same STM32F4 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-#define FSMC_IRQn              FMC_IRQn
-
-/* Aliases for __IRQHandler */
-#define FSMC_IRQHandler        FMC_IRQHandler
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32F429xx_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/cmsis/stm32f437xx.h b/stmhal/cmsis/stm32f437xx.h
deleted file mode 100644
index 7a1af53c58..0000000000
--- a/stmhal/cmsis/stm32f437xx.h
+++ /dev/null
@@ -1,9093 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f437xx.h
-  * @author  MCD Application Team
-  * @version V2.5.1
-  * @date    28-June-2016
-  * @brief   CMSIS STM32F437xx Device Peripheral Access Layer Header File.
-  *
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - peripherals registers declarations and bits definition
-  *           - Macros to access peripheral’s registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS_Device
-  * @{
-  */
-
-/** @addtogroup stm32f437xx
-  * @{
-  */
-    
-#ifndef __STM32F437xx_H
-#define __STM32F437xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-  
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-
-/**
-  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
-  */
-#define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */
-#define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */
-#define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1U       /*!< FPU present                                   */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32F4XX Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-typedef enum
-{
-/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
-  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
-/******  STM32 specific Interrupt Numbers **********************************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
-  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
-  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
-  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
-  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
-  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
-  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
-  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
-  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
-  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
-  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
-  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
-  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
-  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
-  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
-  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
-  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
-  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */    
-  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
-  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
-  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
-  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
-  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
-  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
-  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
-  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
-  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
-  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
-  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
-  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
-  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
-  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
-  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
-  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
-  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
-  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
-  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
-  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
-  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
-  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
-  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
-  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
-  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
-  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
-  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
-  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
-  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
-  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
-  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
-  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
-  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
-  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
-  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
-  CRYP_IRQn                   = 79,     /*!< CRYP crypto global interrupt                                      */
-  HASH_RNG_IRQn               = 80,     /*!< Hash and Rng global interrupt                                     */
-  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
-  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */
-  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */
-  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
-  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */
-  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */
-  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
-  DMA2D_IRQn                  = 90      /*!< DMA2D global Interrupt                                            */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
-#include "system_stm32f4xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */      
-  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
-  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
-  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
-  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
-  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
-  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
-  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
-  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
-  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
-  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
-  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
-  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
-  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
-  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
-  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
-                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
-} ADC_Common_TypeDef;
-
-
-/** 
-  * @brief Controller Area Network TxMailBox 
-  */
-
-typedef struct
-{
-  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
-  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
-  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
-  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
-} CAN_TxMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FIFOMailBox 
-  */
-  
-typedef struct
-{
-  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
-  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
-  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
-  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
-} CAN_FIFOMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FilterRegister 
-  */
-  
-typedef struct
-{
-  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
-  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
-} CAN_FilterRegister_TypeDef;
-
-/** 
-  * @brief Controller Area Network 
-  */
-  
-typedef struct
-{
-  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
-  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
-  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
-  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
-  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
-  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
-  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
-  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
-  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
-  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
-  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
-  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
-  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
-  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
-  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
-  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
-  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
-  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
-  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
-  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
-  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */ 
-  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
-} CAN_TypeDef;
-
-/** 
-  * @brief CRC calculation unit 
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
-  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */
-  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
-  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
-  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
-  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
-  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
-  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
-  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
-  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
-  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
-  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
-  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
-  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
-  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
-  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
-  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
-  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
-  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
-  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DCMI
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
-  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
-  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
-  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
-  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
-  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
-  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
-  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
-  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
-  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
-  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
-} DCMI_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
-  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
-  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
-  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
-  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
-  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
-} DMA_Stream_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
-  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
-  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
-  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
-} DMA_TypeDef;
-
-/** 
-  * @brief DMA2D Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
-  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
-  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
-  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
-  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
-  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
-  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
-  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
-  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
-  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
-  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
-  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
-  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
-  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
-  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
-  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
-  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
-  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
-  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
-  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
-  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
-  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */
-  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */
-} DMA2D_TypeDef;
-
-/** 
-  * @brief Ethernet MAC
-  */
-
-typedef struct
-{
-  __IO uint32_t MACCR;
-  __IO uint32_t MACFFR;
-  __IO uint32_t MACHTHR;
-  __IO uint32_t MACHTLR;
-  __IO uint32_t MACMIIAR;
-  __IO uint32_t MACMIIDR;
-  __IO uint32_t MACFCR;
-  __IO uint32_t MACVLANTR;             /*    8 */
-  uint32_t      RESERVED0[2];
-  __IO uint32_t MACRWUFFR;             /*   11 */
-  __IO uint32_t MACPMTCSR;
-  uint32_t      RESERVED1[2];
-  __IO uint32_t MACSR;                 /*   15 */
-  __IO uint32_t MACIMR;
-  __IO uint32_t MACA0HR;
-  __IO uint32_t MACA0LR;
-  __IO uint32_t MACA1HR;
-  __IO uint32_t MACA1LR;
-  __IO uint32_t MACA2HR;
-  __IO uint32_t MACA2LR;
-  __IO uint32_t MACA3HR;
-  __IO uint32_t MACA3LR;               /*   24 */
-  uint32_t      RESERVED2[40];
-  __IO uint32_t MMCCR;                 /*   65 */
-  __IO uint32_t MMCRIR;
-  __IO uint32_t MMCTIR;
-  __IO uint32_t MMCRIMR;
-  __IO uint32_t MMCTIMR;               /*   69 */
-  uint32_t      RESERVED3[14];
-  __IO uint32_t MMCTGFSCCR;            /*   84 */
-  __IO uint32_t MMCTGFMSCCR;
-  uint32_t      RESERVED4[5];
-  __IO uint32_t MMCTGFCR;
-  uint32_t      RESERVED5[10];
-  __IO uint32_t MMCRFCECR;
-  __IO uint32_t MMCRFAECR;
-  uint32_t      RESERVED6[10];
-  __IO uint32_t MMCRGUFCR;
-  uint32_t      RESERVED7[334];
-  __IO uint32_t PTPTSCR;
-  __IO uint32_t PTPSSIR;
-  __IO uint32_t PTPTSHR;
-  __IO uint32_t PTPTSLR;
-  __IO uint32_t PTPTSHUR;
-  __IO uint32_t PTPTSLUR;
-  __IO uint32_t PTPTSAR;
-  __IO uint32_t PTPTTHR;
-  __IO uint32_t PTPTTLR;
-  __IO uint32_t RESERVED8;
-  __IO uint32_t PTPTSSR;
-  uint32_t      RESERVED9[565];
-  __IO uint32_t DMABMR;
-  __IO uint32_t DMATPDR;
-  __IO uint32_t DMARPDR;
-  __IO uint32_t DMARDLAR;
-  __IO uint32_t DMATDLAR;
-  __IO uint32_t DMASR;
-  __IO uint32_t DMAOMR;
-  __IO uint32_t DMAIER;
-  __IO uint32_t DMAMFBOCR;
-  __IO uint32_t DMARSWTR;
-  uint32_t      RESERVED10[8];
-  __IO uint32_t DMACHTDR;
-  __IO uint32_t DMACHRDR;
-  __IO uint32_t DMACHTBAR;
-  __IO uint32_t DMACHRBAR;
-} ETH_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
-  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
-  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
-  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
-  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
-  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-
-typedef struct
-{
-  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */
-  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */
-  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */
-  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */
-  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */
-  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief Flexible Memory Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */   
-} FMC_Bank1_TypeDef; 
-
-/** 
-  * @brief Flexible Memory Controller Bank1E
-  */
-  
-typedef struct
-{
-  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
-} FMC_Bank1E_TypeDef;
-
-/** 
-  * @brief Flexible Memory Controller Bank2
-  */
-  
-typedef struct
-{
-  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */
-  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */
-  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */
-  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
-  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */
-  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */
-  uint32_t      RESERVED1;  /*!< Reserved, 0x78                                                            */
-  uint32_t      RESERVED2;  /*!< Reserved, 0x7C                                                            */
-  __IO uint32_t PCR3;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */
-  __IO uint32_t SR3;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */
-  __IO uint32_t PMEM3;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */
-  __IO uint32_t PATT3;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
-  uint32_t      RESERVED3;  /*!< Reserved, 0x90                                                            */
-  __IO uint32_t ECCR3;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */
-} FMC_Bank2_3_TypeDef;
-
-/** 
-  * @brief Flexible Memory Controller Bank4
-  */
-  
-typedef struct
-{
-  __IO uint32_t PCR4;       /*!< PC Card  control register 4,                       Address offset: 0xA0 */
-  __IO uint32_t SR4;        /*!< PC Card  FIFO status and interrupt register 4,     Address offset: 0xA4 */
-  __IO uint32_t PMEM4;      /*!< PC Card  Common memory space timing register 4,    Address offset: 0xA8 */
-  __IO uint32_t PATT4;      /*!< PC Card  Attribute memory space timing register 4, Address offset: 0xAC */
-  __IO uint32_t PIO4;       /*!< PC Card  I/O space timing register 4,              Address offset: 0xB0 */
-} FMC_Bank4_TypeDef; 
-
-/** 
-  * @brief Flexible Memory Controller Bank5_6
-  */
-  
-typedef struct
-{
-  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */
-  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */
-  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */
-  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */
-  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */
-} FMC_Bank5_6_TypeDef; 
-
-/** 
-  * @brief General Purpose I/O
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
-  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
-  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
-  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
-  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
-  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
-  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
-  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/** 
-  * @brief System configuration controller
-  */
-  
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */ 
-  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */
-  __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */
-  __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */
-  __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */
-  __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */
-  __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
-  __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
-  __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
-  __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-} IWDG_TypeDef;
-
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
-  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
-  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
-  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
-  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
-  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
-  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
-  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
-  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
-  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
-  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
-  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
-  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
-  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
-  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
-  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
-  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
-  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
-  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
-  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
-  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
-  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
-  __IO uint32_t PLLSAICFGR;    /*!< RCC PLLSAI configuration register,                           Address offset: 0x88 */
-  __IO uint32_t DCKCFGR;       /*!< RCC Dedicated Clocks configuration register,                 Address offset: 0x8C */
-
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-
-typedef struct
-{
-  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
-  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
-  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
-  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
-  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
-  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
-  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */
-  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
-  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */
-  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
-  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */
-  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */
-  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */
-  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */
-  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
-  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */
-  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
-  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
-  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
-  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
-  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
-  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
-  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
-  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
-  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
-  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
-  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
-  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
-  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
-  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
-  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
-  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
-  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
-  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
-  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
-  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
-  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
-} RTC_TypeDef;
-
-/** 
-  * @brief Serial Audio Interface
-  */
-  
-typedef struct
-{
-  __IO uint32_t GCR;      /*!< SAI global configuration register,        Address offset: 0x00 */
-} SAI_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */
-  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */
-  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */
-  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */
-  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
-  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */
-  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */
-  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */
-} SAI_Block_TypeDef;
-
-/** 
-  * @brief SD host Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t POWER;          /*!< SDIO power control register,    Address offset: 0x00 */
-  __IO uint32_t CLKCR;          /*!< SDI clock control register,     Address offset: 0x04 */
-  __IO uint32_t ARG;            /*!< SDIO argument register,         Address offset: 0x08 */
-  __IO uint32_t CMD;            /*!< SDIO command register,          Address offset: 0x0C */
-  __I uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */
-  __I uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */
-  __I uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */
-  __I uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */
-  __I uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */
-  __IO uint32_t DTIMER;         /*!< SDIO data timer register,       Address offset: 0x24 */
-  __IO uint32_t DLEN;           /*!< SDIO data length register,      Address offset: 0x28 */
-  __IO uint32_t DCTRL;          /*!< SDIO data control register,     Address offset: 0x2C */
-  __I uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */
-  __I uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */
-  __IO uint32_t ICR;            /*!< SDIO interrupt clear register,  Address offset: 0x38 */
-  __IO uint32_t MASK;           /*!< SDIO mask register,             Address offset: 0x3C */
-  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
-  __I uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */
-  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
-  __IO uint32_t FIFO;           /*!< SDIO data FIFO register,        Address offset: 0x80 */
-} SDIO_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
-  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
-  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
-  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Crypto Processor
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;         /*!< CRYP control register,                                    Address offset: 0x00 */
-  __IO uint32_t SR;         /*!< CRYP status register,                                     Address offset: 0x04 */
-  __IO uint32_t DR;         /*!< CRYP data input register,                                 Address offset: 0x08 */
-  __IO uint32_t DOUT;       /*!< CRYP data output register,                                Address offset: 0x0C */
-  __IO uint32_t DMACR;      /*!< CRYP DMA control register,                                Address offset: 0x10 */
-  __IO uint32_t IMSCR;      /*!< CRYP interrupt mask set/clear register,                   Address offset: 0x14 */
-  __IO uint32_t RISR;       /*!< CRYP raw interrupt status register,                       Address offset: 0x18 */
-  __IO uint32_t MISR;       /*!< CRYP masked interrupt status register,                    Address offset: 0x1C */
-  __IO uint32_t K0LR;       /*!< CRYP key left  register 0,                                Address offset: 0x20 */
-  __IO uint32_t K0RR;       /*!< CRYP key right register 0,                                Address offset: 0x24 */
-  __IO uint32_t K1LR;       /*!< CRYP key left  register 1,                                Address offset: 0x28 */
-  __IO uint32_t K1RR;       /*!< CRYP key right register 1,                                Address offset: 0x2C */
-  __IO uint32_t K2LR;       /*!< CRYP key left  register 2,                                Address offset: 0x30 */
-  __IO uint32_t K2RR;       /*!< CRYP key right register 2,                                Address offset: 0x34 */
-  __IO uint32_t K3LR;       /*!< CRYP key left  register 3,                                Address offset: 0x38 */
-  __IO uint32_t K3RR;       /*!< CRYP key right register 3,                                Address offset: 0x3C */
-  __IO uint32_t IV0LR;      /*!< CRYP initialization vector left-word  register 0,         Address offset: 0x40 */
-  __IO uint32_t IV0RR;      /*!< CRYP initialization vector right-word register 0,         Address offset: 0x44 */
-  __IO uint32_t IV1LR;      /*!< CRYP initialization vector left-word  register 1,         Address offset: 0x48 */
-  __IO uint32_t IV1RR;      /*!< CRYP initialization vector right-word register 1,         Address offset: 0x4C */
-  __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0,        Address offset: 0x50 */
-  __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1,        Address offset: 0x54 */
-  __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2,        Address offset: 0x58 */
-  __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3,        Address offset: 0x5C */
-  __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4,        Address offset: 0x60 */
-  __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5,        Address offset: 0x64 */
-  __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6,        Address offset: 0x68 */
-  __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7,        Address offset: 0x6C */
-  __IO uint32_t CSGCM0R;    /*!< CRYP GCM/GMAC context swap register 0,                    Address offset: 0x70 */
-  __IO uint32_t CSGCM1R;    /*!< CRYP GCM/GMAC context swap register 1,                    Address offset: 0x74 */
-  __IO uint32_t CSGCM2R;    /*!< CRYP GCM/GMAC context swap register 2,                    Address offset: 0x78 */
-  __IO uint32_t CSGCM3R;    /*!< CRYP GCM/GMAC context swap register 3,                    Address offset: 0x7C */
-  __IO uint32_t CSGCM4R;    /*!< CRYP GCM/GMAC context swap register 4,                    Address offset: 0x80 */
-  __IO uint32_t CSGCM5R;    /*!< CRYP GCM/GMAC context swap register 5,                    Address offset: 0x84 */
-  __IO uint32_t CSGCM6R;    /*!< CRYP GCM/GMAC context swap register 6,                    Address offset: 0x88 */
-  __IO uint32_t CSGCM7R;    /*!< CRYP GCM/GMAC context swap register 7,                    Address offset: 0x8C */
-} CRYP_TypeDef;
-
-/** 
-  * @brief HASH
-  */
-  
-typedef struct 
-{
-  __IO uint32_t CR;               /*!< HASH control register,          Address offset: 0x00        */
-  __IO uint32_t DIN;              /*!< HASH data input register,       Address offset: 0x04        */
-  __IO uint32_t STR;              /*!< HASH start register,            Address offset: 0x08        */
-  __IO uint32_t HR[5];            /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */
-  __IO uint32_t IMR;              /*!< HASH interrupt enable register, Address offset: 0x20        */
-  __IO uint32_t SR;               /*!< HASH status register,           Address offset: 0x24        */
-       uint32_t RESERVED[52];     /*!< Reserved, 0x28-0xF4                                         */
-  __IO uint32_t CSR[54];          /*!< HASH context swap registers,    Address offset: 0x0F8-0x1CC */
-} HASH_TypeDef;
-
-/** 
-  * @brief HASH_DIGEST
-  */
-  
-typedef struct 
-{
-  __IO uint32_t HR[8];     /*!< HASH digest registers,          Address offset: 0x310-0x32C */ 
-} HASH_DIGEST_TypeDef;
-
-/** 
-  * @brief RNG
-  */
-  
-typedef struct 
-{
-  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
-  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
-  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
-} RNG_TypeDef;
-
- 
-/** 
-  * @brief __USB_OTG_Core_register
-  */
-typedef struct
-{
-  __IO uint32_t GOTGCTL;      /*!<  USB_OTG Control and Status Register    000h */
-  __IO uint32_t GOTGINT;      /*!<  USB_OTG Interrupt Register             004h */
-  __IO uint32_t GAHBCFG;      /*!<  Core AHB Configuration Register        008h */
-  __IO uint32_t GUSBCFG;      /*!<  Core USB Configuration Register        00Ch */
-  __IO uint32_t GRSTCTL;      /*!<  Core Reset Register                    010h */
-  __IO uint32_t GINTSTS;      /*!<  Core Interrupt Register                014h */
-  __IO uint32_t GINTMSK;      /*!<  Core Interrupt Mask Register           018h */
-  __IO uint32_t GRXSTSR;      /*!<  Receive Sts Q Read Register            01Ch */
-  __IO uint32_t GRXSTSP;      /*!<  Receive Sts Q Read & POP Register      020h */
-  __IO uint32_t GRXFSIZ;      /* Receive FIFO Size Register                024h */
-  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!<  EP0 / Non Periodic Tx FIFO Size Register 028h*/
-  __IO uint32_t HNPTXSTS;     /*!<  Non Periodic Tx FIFO/Queue Sts reg     02Ch */
-  uint32_t Reserved30[2];     /* Reserved                           030h*/
-  __IO uint32_t GCCFG;        /* General Purpose IO Register        038h*/
-  __IO uint32_t CID;          /* User ID Register                   03Ch*/
-  uint32_t  Reserved40[48];   /* Reserved                      040h-0FFh*/
-  __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg     100h*/
-  __IO uint32_t DIEPTXF[0x0F];/* dev Periodic Transmit FIFO */
-}
-USB_OTG_GlobalTypeDef;
-
-
-/** 
-  * @brief __device_Registers
-  */
-typedef struct 
-{
-  __IO uint32_t DCFG;         /* dev Configuration Register   800h*/
-  __IO uint32_t DCTL;         /* dev Control Register         804h*/
-  __IO uint32_t DSTS;         /* dev Status Register (RO)     808h*/
-  uint32_t Reserved0C;           /* Reserved                     80Ch*/
-  __IO uint32_t DIEPMSK;   /* dev IN Endpoint Mask         810h*/
-  __IO uint32_t DOEPMSK;  /* dev OUT Endpoint Mask        814h*/
-  __IO uint32_t DAINT;     /* dev All Endpoints Itr Reg    818h*/
-  __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask   81Ch*/
-  uint32_t  Reserved20;          /* Reserved                     820h*/
-  uint32_t Reserved9;       /* Reserved                     824h*/
-  __IO uint32_t DVBUSDIS;    /* dev VBUS discharge Register  828h*/
-  __IO uint32_t DVBUSPULSE;  /* dev VBUS Pulse Register      82Ch*/
-  __IO uint32_t DTHRCTL;     /* dev thr                      830h*/
-  __IO uint32_t DIEPEMPMSK; /* dev empty msk             834h*/
-  __IO uint32_t DEACHINT;    /* dedicated EP interrupt       838h*/
-  __IO uint32_t DEACHMSK;    /* dedicated EP msk             83Ch*/  
-  uint32_t Reserved40;      /* dedicated EP mask           840h*/
-  __IO uint32_t DINEP1MSK;  /* dedicated EP mask           844h*/
-  uint32_t  Reserved44[15];      /* Reserved                 844-87Ch*/
-  __IO uint32_t DOUTEP1MSK; /* dedicated EP msk            884h*/   
-}
-USB_OTG_DeviceTypeDef;
-
-
-/** 
-  * @brief __IN_Endpoint-Specific_Register
-  */
-typedef struct 
-{
-  __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
-  uint32_t Reserved04;             /* Reserved                       900h + (ep_num * 20h) + 04h*/
-  __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg     900h + (ep_num * 20h) + 08h*/
-  uint32_t Reserved0C;             /* Reserved                       900h + (ep_num * 20h) + 0Ch*/
-  __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size   900h + (ep_num * 20h) + 10h*/
-  __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h*/
-  __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
-  uint32_t Reserved18;             /* Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
-}
-USB_OTG_INEndpointTypeDef;
-
-
-/** 
-  * @brief __OUT_Endpoint-Specific_Registers
-  */
-typedef struct 
-{
-  __IO uint32_t DOEPCTL;       /* dev OUT Endpoint Control Reg  B00h + (ep_num * 20h) + 00h*/
-  uint32_t Reserved04;         /* Reserved                      B00h + (ep_num * 20h) + 04h*/
-  __IO uint32_t DOEPINT;       /* dev OUT Endpoint Itr Reg      B00h + (ep_num * 20h) + 08h*/
-  uint32_t Reserved0C;         /* Reserved                      B00h + (ep_num * 20h) + 0Ch*/
-  __IO uint32_t DOEPTSIZ;      /* dev OUT Endpoint Txfer Size   B00h + (ep_num * 20h) + 10h*/
-  __IO uint32_t DOEPDMA;       /* dev OUT Endpoint DMA Address  B00h + (ep_num * 20h) + 14h*/
-  uint32_t Reserved18[2];      /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
-}
-USB_OTG_OUTEndpointTypeDef;
-
-
-/** 
-  * @brief __Host_Mode_Register_Structures
-  */
-typedef struct 
-{
-  __IO uint32_t HCFG;             /* Host Configuration Register    400h*/
-  __IO uint32_t HFIR;      /* Host Frame Interval Register   404h*/
-  __IO uint32_t HFNUM;         /* Host Frame Nbr/Frame Remaining 408h*/
-  uint32_t Reserved40C;                   /* Reserved                       40Ch*/
-  __IO uint32_t HPTXSTS;   /* Host Periodic Tx FIFO/ Queue Status 410h*/
-  __IO uint32_t HAINT;   /* Host All Channels Interrupt Register 414h*/
-  __IO uint32_t HAINTMSK;   /* Host All Channels Interrupt Mask 418h*/
-}
-USB_OTG_HostTypeDef;
-
-/** 
-  * @brief __Host_Channel_Specific_Registers
-  */
-typedef struct
-{
-  __IO uint32_t HCCHAR;
-  __IO uint32_t HCSPLT;
-  __IO uint32_t HCINT;
-  __IO uint32_t HCINTMSK;
-  __IO uint32_t HCTSIZ;
-  __IO uint32_t HCDMA;
-  uint32_t Reserved[2];
-}
-USB_OTG_HostChannelTypeDef;
-/**
-  * @}
-  */
-    
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-#define FLASH_BASE            0x08000000U /*!< FLASH(up to 2 MB) base address in the alias region                         */
-#define CCMDATARAM_BASE       0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
-#define SRAM1_BASE            0x20000000U /*!< SRAM1(112 KB) base address in the alias region                             */
-#define SRAM2_BASE            0x2001C000U /*!< SRAM2(16 KB) base address in the alias region                              */
-#define SRAM3_BASE            0x20020000U /*!< SRAM3(64 KB) base address in the alias region                              */
-#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region                                */
-#define BKPSRAM_BASE          0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region                         */
-#define FMC_R_BASE            0xA0000000U /*!< FMC registers base address                                                 */
-#define SRAM1_BB_BASE         0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region                             */
-#define SRAM2_BB_BASE         0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region                              */
-#define SRAM3_BB_BASE         0x22400000U /*!< SRAM3(64 KB) base address in the bit-band region                              */
-#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region                                */
-#define BKPSRAM_BB_BASE       0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region                         */
-#define FLASH_END             0x081FFFFFU /*!< FLASH end address */
-#define CCMDATARAM_END        0x1000FFFFU /*!< CCM data RAM end address */
-
-/* Legacy defines */
-#define SRAM_BASE             SRAM1_BASE
-#define SRAM_BB_BASE          SRAM1_BB_BASE
-
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000U)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)
-#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800U)
-#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00U)
-#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000U)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)
-#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400U)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)
-#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000U)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800U)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00U)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x5000U)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)
-#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)
-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)
-#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800U)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)
-#define UART7_BASE            (APB1PERIPH_BASE + 0x7800U)
-#define UART8_BASE            (APB1PERIPH_BASE + 0x7C00U)
-
-/*!< APB2 peripherals */
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000U)
-#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400U)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x1000U)
-#define USART6_BASE           (APB2PERIPH_BASE + 0x1400U)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000U)
-#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100U)
-#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200U)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x2300U)
-#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00U)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)
-#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400U)
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800U)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00U)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000U)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400U)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800U)
-#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000U)
-#define SPI6_BASE             (APB2PERIPH_BASE + 0x5400U)
-#define SAI1_BASE             (APB2PERIPH_BASE + 0x5800U)
-#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004U)
-#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024U)
-
-/*!< AHB1 peripherals */
-#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000U)
-#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400U)
-#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800U)
-#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00U)
-#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000U)
-#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400U)
-#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800U)
-#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00U)
-#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000U)
-#define GPIOJ_BASE            (AHB1PERIPH_BASE + 0x2400U)
-#define GPIOK_BASE            (AHB1PERIPH_BASE + 0x2800U)
-#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)
-#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800U)
-#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00U)
-#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000U)
-#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010U)
-#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028U)
-#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040U)
-#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058U)
-#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070U)
-#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088U)
-#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0U)
-#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8U)
-#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400U)
-#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010U)
-#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028U)
-#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040U)
-#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058U)
-#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070U)
-#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088U)
-#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0U)
-#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)
-#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000U)
-#define ETH_MAC_BASE          (ETH_BASE)
-#define ETH_MMC_BASE          (ETH_BASE + 0x0100U)
-#define ETH_PTP_BASE          (ETH_BASE + 0x0700U)
-#define ETH_DMA_BASE          (ETH_BASE + 0x1000U)
-#define DMA2D_BASE            (AHB1PERIPH_BASE + 0xB000U)
-
-/*!< AHB2 peripherals */
-#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000U)
-#define CRYP_BASE             (AHB2PERIPH_BASE + 0x60000U)
-#define HASH_BASE             (AHB2PERIPH_BASE + 0x60400U)
-#define HASH_DIGEST_BASE      (AHB2PERIPH_BASE + 0x60710U)
-#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800U)
-
-/*!< FMC Bankx registers base address */
-#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000U)
-#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104U)
-#define FMC_Bank2_3_R_BASE    (FMC_R_BASE + 0x0060U)
-#define FMC_Bank4_R_BASE      (FMC_R_BASE + 0x00A0U)
-#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140U)
-
-/* Debug MCU registers base address */
-#define DBGMCU_BASE           0xE0042000U
-
-/*!< USB registers base address */
-#define USB_OTG_HS_PERIPH_BASE               0x40040000U
-#define USB_OTG_FS_PERIPH_BASE               0x50000000U
-
-#define USB_OTG_GLOBAL_BASE                  0x000U
-#define USB_OTG_DEVICE_BASE                  0x800U
-#define USB_OTG_IN_ENDPOINT_BASE             0x900U
-#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U
-#define USB_OTG_EP_REG_SIZE                  0x20U
-#define USB_OTG_HOST_BASE                    0x400U
-#define USB_OTG_HOST_PORT_BASE               0x440U
-#define USB_OTG_HOST_CHANNEL_BASE            0x500U
-#define USB_OTG_HOST_CHANNEL_SIZE            0x20U
-#define USB_OTG_PCGCCTL_BASE                 0xE00U
-#define USB_OTG_FIFO_BASE                    0x1000U
-#define USB_OTG_FIFO_SIZE                    0x1000U
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
-#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
-#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define UART4               ((USART_TypeDef *) UART4_BASE)
-#define UART5               ((USART_TypeDef *) UART5_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
-#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
-#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
-#define UART7               ((USART_TypeDef *) UART7_BASE)
-#define UART8               ((USART_TypeDef *) UART8_BASE)
-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
-#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define USART6              ((USART_TypeDef *) USART6_BASE)
-#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
-#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
-#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE) 
-#define SPI4                ((SPI_TypeDef *) SPI4_BASE)
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-#define SPI5                ((SPI_TypeDef *) SPI5_BASE)
-#define SPI6                ((SPI_TypeDef *) SPI6_BASE)
-#define SAI1                ((SAI_TypeDef *) SAI1_BASE)
-#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
-#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
-
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
-#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)
-#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
-#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
-#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
-#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
-#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
-#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
-#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
-#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
-#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
-#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
-#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
-#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
-#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
-#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
-#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
-#define ETH                 ((ETH_TypeDef *) ETH_BASE)  
-#define DMA2D               ((DMA2D_TypeDef *)DMA2D_BASE)
-#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
-#define CRYP                ((CRYP_TypeDef *) CRYP_BASE)
-#define HASH                ((HASH_TypeDef *) HASH_BASE)
-#define HASH_DIGEST         ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
-#define RNG                 ((RNG_TypeDef *) RNG_BASE)
-#define FMC_Bank1           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
-#define FMC_Bank1E          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
-#define FMC_Bank2_3         ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
-#define FMC_Bank4           ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
-#define FMC_Bank5_6         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
-
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
-#define USB_OTG_HS          ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers_Bits_Definition               */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Analog to Digital Converter                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          0x00000001U        /*!<Analog watchdog flag */
-#define  ADC_SR_EOC                          0x00000002U        /*!<End of conversion */
-#define  ADC_SR_JEOC                         0x00000004U        /*!<Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        0x00000008U        /*!<Injected channel Start flag */
-#define  ADC_SR_STRT                         0x00000010U        /*!<Regular channel Start flag */
-#define  ADC_SR_OVR                          0x00000020U        /*!<Overrun flag */
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
-#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels */
-#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels */
-#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution) */
-#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
-  
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion */
-#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode */
-#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC) */
-#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection */
-#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment */
-#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      0xFFFFU            /*!<Injected data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag */
-#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion */
-#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag */
-#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag */
-#define  ADC_CSR_OVR1                        0x00000020U        /*!<ADC1 DMA overrun  flag */
-#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag */
-#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion */
-#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag */
-#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag */
-#define  ADC_CSR_OVR2                        0x00002000U        /*!<ADC2 DMA overrun  flag */
-#define  ADC_CSR_AWD3                        0x00010000U        /*!<ADC3 Analog watchdog flag */
-#define  ADC_CSR_EOC3                        0x00020000U        /*!<ADC3 End of conversion */
-#define  ADC_CSR_JEOC3                       0x00040000U        /*!<ADC3 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT3                      0x00080000U        /*!<ADC3 Injected channel Start flag */
-#define  ADC_CSR_STRT3                       0x00100000U        /*!<ADC3 Regular channel Start flag */
-#define  ADC_CSR_OVR3                        0x00200000U        /*!<ADC3 DMA overrun  flag */
-
-/* Legacy defines */
-#define  ADC_CSR_DOVR1                        ADC_CSR_OVR1
-#define  ADC_CSR_DOVR2                        ADC_CSR_OVR2
-#define  ADC_CSR_DOVR3                        ADC_CSR_OVR3
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
-#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
-#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
-#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
-#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
-
-/*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                      0x0000FFFFU         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                      0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Controller Area Network                            */
-/*                                                                            */
-/******************************************************************************/
-/*!<CAN control and status registers */
-/*******************  Bit definition for CAN_MCR register  ********************/
-#define  CAN_MCR_INRQ                        0x00000001U        /*!<Initialization Request */
-#define  CAN_MCR_SLEEP                       0x00000002U        /*!<Sleep Mode Request */
-#define  CAN_MCR_TXFP                        0x00000004U        /*!<Transmit FIFO Priority */
-#define  CAN_MCR_RFLM                        0x00000008U        /*!<Receive FIFO Locked Mode */
-#define  CAN_MCR_NART                        0x00000010U        /*!<No Automatic Retransmission */
-#define  CAN_MCR_AWUM                        0x00000020U        /*!<Automatic Wakeup Mode */
-#define  CAN_MCR_ABOM                        0x00000040U        /*!<Automatic Bus-Off Management */
-#define  CAN_MCR_TTCM                        0x00000080U        /*!<Time Triggered Communication Mode */
-#define  CAN_MCR_RESET                       0x00008000U        /*!<bxCAN software master reset */
-#define  CAN_MCR_DBF                         0x00010000U        /*!<bxCAN Debug freeze */
-/*******************  Bit definition for CAN_MSR register  ********************/
-#define  CAN_MSR_INAK                        0x0001U            /*!<Initialization Acknowledge */
-#define  CAN_MSR_SLAK                        0x0002U            /*!<Sleep Acknowledge */
-#define  CAN_MSR_ERRI                        0x0004U            /*!<Error Interrupt */
-#define  CAN_MSR_WKUI                        0x0008U            /*!<Wakeup Interrupt */
-#define  CAN_MSR_SLAKI                       0x0010U            /*!<Sleep Acknowledge Interrupt */
-#define  CAN_MSR_TXM                         0x0100U            /*!<Transmit Mode */
-#define  CAN_MSR_RXM                         0x0200U            /*!<Receive Mode */
-#define  CAN_MSR_SAMP                        0x0400U            /*!<Last Sample Point */
-#define  CAN_MSR_RX                          0x0800U            /*!<CAN Rx Signal */
-
-/*******************  Bit definition for CAN_TSR register  ********************/
-#define  CAN_TSR_RQCP0                       0x00000001U        /*!<Request Completed Mailbox0 */
-#define  CAN_TSR_TXOK0                       0x00000002U        /*!<Transmission OK of Mailbox0 */
-#define  CAN_TSR_ALST0                       0x00000004U        /*!<Arbitration Lost for Mailbox0 */
-#define  CAN_TSR_TERR0                       0x00000008U        /*!<Transmission Error of Mailbox0 */
-#define  CAN_TSR_ABRQ0                       0x00000080U        /*!<Abort Request for Mailbox0 */
-#define  CAN_TSR_RQCP1                       0x00000100U        /*!<Request Completed Mailbox1 */
-#define  CAN_TSR_TXOK1                       0x00000200U        /*!<Transmission OK of Mailbox1 */
-#define  CAN_TSR_ALST1                       0x00000400U        /*!<Arbitration Lost for Mailbox1 */
-#define  CAN_TSR_TERR1                       0x00000800U        /*!<Transmission Error of Mailbox1 */
-#define  CAN_TSR_ABRQ1                       0x00008000U        /*!<Abort Request for Mailbox 1 */
-#define  CAN_TSR_RQCP2                       0x00010000U        /*!<Request Completed Mailbox2 */
-#define  CAN_TSR_TXOK2                       0x00020000U        /*!<Transmission OK of Mailbox 2 */
-#define  CAN_TSR_ALST2                       0x00040000U        /*!<Arbitration Lost for mailbox 2 */
-#define  CAN_TSR_TERR2                       0x00080000U        /*!<Transmission Error of Mailbox 2 */
-#define  CAN_TSR_ABRQ2                       0x00800000U        /*!<Abort Request for Mailbox 2 */
-#define  CAN_TSR_CODE                        0x03000000U        /*!<Mailbox Code */
-
-#define  CAN_TSR_TME                         0x1C000000U        /*!<TME[2:0] bits */
-#define  CAN_TSR_TME0                        0x04000000U        /*!<Transmit Mailbox 0 Empty */
-#define  CAN_TSR_TME1                        0x08000000U        /*!<Transmit Mailbox 1 Empty */
-#define  CAN_TSR_TME2                        0x10000000U        /*!<Transmit Mailbox 2 Empty */
-
-#define  CAN_TSR_LOW                         0xE0000000U        /*!<LOW[2:0] bits */
-#define  CAN_TSR_LOW0                        0x20000000U        /*!<Lowest Priority Flag for Mailbox 0 */
-#define  CAN_TSR_LOW1                        0x40000000U        /*!<Lowest Priority Flag for Mailbox 1 */
-#define  CAN_TSR_LOW2                        0x80000000U        /*!<Lowest Priority Flag for Mailbox 2 */
-
-/*******************  Bit definition for CAN_RF0R register  *******************/
-#define  CAN_RF0R_FMP0                       0x03U               /*!<FIFO 0 Message Pending */
-#define  CAN_RF0R_FULL0                      0x08U               /*!<FIFO 0 Full */
-#define  CAN_RF0R_FOVR0                      0x10U               /*!<FIFO 0 Overrun */
-#define  CAN_RF0R_RFOM0                      0x20U               /*!<Release FIFO 0 Output Mailbox */
-
-/*******************  Bit definition for CAN_RF1R register  *******************/
-#define  CAN_RF1R_FMP1                       0x03U               /*!<FIFO 1 Message Pending */
-#define  CAN_RF1R_FULL1                      0x08U               /*!<FIFO 1 Full */
-#define  CAN_RF1R_FOVR1                      0x10U               /*!<FIFO 1 Overrun */
-#define  CAN_RF1R_RFOM1                      0x20U               /*!<Release FIFO 1 Output Mailbox */
-
-/********************  Bit definition for CAN_IER register  *******************/
-#define  CAN_IER_TMEIE                       0x00000001U        /*!<Transmit Mailbox Empty Interrupt Enable */
-#define  CAN_IER_FMPIE0                      0x00000002U        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE0                       0x00000004U        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE0                      0x00000008U        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_FMPIE1                      0x00000010U        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE1                       0x00000020U        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE1                      0x00000040U        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error Warning Interrupt Enable */
-#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error Passive Interrupt Enable */
-#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-Off Interrupt Enable */
-#define  CAN_IER_LECIE                       0x00000800U        /*!<Last Error Code Interrupt Enable */
-#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error Interrupt Enable */
-#define  CAN_IER_WKUIE                       0x00010000U        /*!<Wakeup Interrupt Enable */
-#define  CAN_IER_SLKIE                       0x00020000U        /*!<Sleep Interrupt Enable */
-#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error warning interrupt enable */
-#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error passive interrupt enable */
-#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-off interrupt enable */
-#define  CAN_IER_LECIE                       0x00000800U        /*!<Last error code interrupt enable */
-#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error interrupt enable */
-
-
-/********************  Bit definition for CAN_ESR register  *******************/
-#define  CAN_ESR_EWGF                        0x00000001U        /*!<Error Warning Flag */
-#define  CAN_ESR_EPVF                        0x00000002U        /*!<Error Passive Flag */
-#define  CAN_ESR_BOFF                        0x00000004U        /*!<Bus-Off Flag */
-
-#define  CAN_ESR_LEC                         0x00000070U        /*!<LEC[2:0] bits (Last Error Code) */
-#define  CAN_ESR_LEC_0                       0x00000010U        /*!<Bit 0 */
-#define  CAN_ESR_LEC_1                       0x00000020U        /*!<Bit 1 */
-#define  CAN_ESR_LEC_2                       0x00000040U        /*!<Bit 2 */
-
-#define  CAN_ESR_TEC                         0x00FF0000U        /*!<Least significant byte of the 9-bit Transmit Error Counter */
-#define  CAN_ESR_REC                         0xFF000000U        /*!<Receive Error Counter */
-
-/*******************  Bit definition for CAN_BTR register  ********************/
-#define  CAN_BTR_BRP                         0x000003FFU        /*!<Baud Rate Prescaler */
-#define  CAN_BTR_TS1                         0x000F0000U        /*!<Time Segment 1 */
-#define  CAN_BTR_TS1_0                       0x00010000U        /*!<Bit 0 */
-#define  CAN_BTR_TS1_1                       0x00020000U        /*!<Bit 1 */
-#define  CAN_BTR_TS1_2                       0x00040000U        /*!<Bit 2 */
-#define  CAN_BTR_TS1_3                       0x00080000U        /*!<Bit 3 */
-#define  CAN_BTR_TS2                         0x00700000U        /*!<Time Segment 2 */
-#define  CAN_BTR_TS2_0                       0x00100000U        /*!<Bit 0 */
-#define  CAN_BTR_TS2_1                       0x00200000U        /*!<Bit 1 */
-#define  CAN_BTR_TS2_2                       0x00400000U        /*!<Bit 2 */
-#define  CAN_BTR_SJW                         0x03000000U        /*!<Resynchronization Jump Width */
-#define  CAN_BTR_SJW_0                       0x01000000U        /*!<Bit 0 */
-#define  CAN_BTR_SJW_1                       0x02000000U        /*!<Bit 1 */
-#define  CAN_BTR_LBKM                        0x40000000U        /*!<Loop Back Mode (Debug) */
-#define  CAN_BTR_SILM                        0x80000000U        /*!<Silent Mode */
-
-
-/*!<Mailbox registers */
-/******************  Bit definition for CAN_TI0R register  ********************/
-#define  CAN_TI0R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI0R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_TI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/******************  Bit definition for CAN_TDT0R register  *******************/
-#define  CAN_TDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT0R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/******************  Bit definition for CAN_TDL0R register  *******************/
-#define  CAN_TDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/******************  Bit definition for CAN_TDH0R register  *******************/
-#define  CAN_TDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI1R register  *******************/
-#define  CAN_TI1R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI1R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI1R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_TI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT1R register  ******************/
-#define  CAN_TDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT1R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL1R register  ******************/
-#define  CAN_TDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH1R register  ******************/
-#define  CAN_TDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI2R register  *******************/
-#define  CAN_TI2R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI2R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI2R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI2R_EXID                       0x001FFFF8U        /*!<Extended identifier */
-#define  CAN_TI2R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT2R register  ******************/  
-#define  CAN_TDT2R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT2R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT2R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL2R register  ******************/
-#define  CAN_TDL2R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL2R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL2R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL2R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH2R register  ******************/
-#define  CAN_TDH2R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH2R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH2R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH2R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI0R register  *******************/
-#define  CAN_RI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_RI0R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_RI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_RI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT0R register  ******************/
-#define  CAN_RDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_RDT0R_FMI                       0x0000FF00U        /*!<Filter Match Index */
-#define  CAN_RDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL0R register  ******************/
-#define  CAN_RDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_RDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_RDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_RDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH0R register  ******************/
-#define  CAN_RDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_RDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_RDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_RDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI1R register  *******************/
-#define  CAN_RI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_RI1R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_RI1R_EXID                       0x001FFFF8U        /*!<Extended identifier */
-#define  CAN_RI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT1R register  ******************/
-#define  CAN_RDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_RDT1R_FMI                       0x0000FF00U        /*!<Filter Match Index */
-#define  CAN_RDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL1R register  ******************/
-#define  CAN_RDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_RDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_RDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_RDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH1R register  ******************/
-#define  CAN_RDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_RDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_RDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_RDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*!<CAN filter registers */
-/*******************  Bit definition for CAN_FMR register  ********************/
-#define  CAN_FMR_FINIT                       0x01U               /*!<Filter Init Mode */
-#define  CAN_FMR_CAN2SB                      0x00003F00U        /*!<CAN2 start bank */
-
-/*******************  Bit definition for CAN_FM1R register  *******************/
-#define  CAN_FM1R_FBM                        0x0FFFFFFFU        /*!<Filter Mode */
-#define  CAN_FM1R_FBM0                       0x00000001U        /*!<Filter Init Mode bit 0 */
-#define  CAN_FM1R_FBM1                       0x00000002U        /*!<Filter Init Mode bit 1 */
-#define  CAN_FM1R_FBM2                       0x00000004U        /*!<Filter Init Mode bit 2 */
-#define  CAN_FM1R_FBM3                       0x00000008U        /*!<Filter Init Mode bit 3 */
-#define  CAN_FM1R_FBM4                       0x00000010U        /*!<Filter Init Mode bit 4 */
-#define  CAN_FM1R_FBM5                       0x00000020U        /*!<Filter Init Mode bit 5 */
-#define  CAN_FM1R_FBM6                       0x00000040U        /*!<Filter Init Mode bit 6 */
-#define  CAN_FM1R_FBM7                       0x00000080U        /*!<Filter Init Mode bit 7 */
-#define  CAN_FM1R_FBM8                       0x00000100U        /*!<Filter Init Mode bit 8 */
-#define  CAN_FM1R_FBM9                       0x00000200U        /*!<Filter Init Mode bit 9 */
-#define  CAN_FM1R_FBM10                      0x00000400U        /*!<Filter Init Mode bit 10 */
-#define  CAN_FM1R_FBM11                      0x00000800U        /*!<Filter Init Mode bit 11 */
-#define  CAN_FM1R_FBM12                      0x00001000U        /*!<Filter Init Mode bit 12 */
-#define  CAN_FM1R_FBM13                      0x00002000U        /*!<Filter Init Mode bit 13 */
-#define  CAN_FM1R_FBM14                      0x00004000U        /*!<Filter Init Mode bit 14 */
-#define  CAN_FM1R_FBM15                      0x00008000U        /*!<Filter Init Mode bit 15 */
-#define  CAN_FM1R_FBM16                      0x00010000U        /*!<Filter Init Mode bit 16 */
-#define  CAN_FM1R_FBM17                      0x00020000U        /*!<Filter Init Mode bit 17 */
-#define  CAN_FM1R_FBM18                      0x00040000U        /*!<Filter Init Mode bit 18 */
-#define  CAN_FM1R_FBM19                      0x00080000U        /*!<Filter Init Mode bit 19 */
-#define  CAN_FM1R_FBM20                      0x00100000U        /*!<Filter Init Mode bit 20 */
-#define  CAN_FM1R_FBM21                      0x00200000U        /*!<Filter Init Mode bit 21 */
-#define  CAN_FM1R_FBM22                      0x00400000U        /*!<Filter Init Mode bit 22 */
-#define  CAN_FM1R_FBM23                      0x00800000U        /*!<Filter Init Mode bit 23 */
-#define  CAN_FM1R_FBM24                      0x01000000U        /*!<Filter Init Mode bit 24 */
-#define  CAN_FM1R_FBM25                      0x02000000U        /*!<Filter Init Mode bit 25 */
-#define  CAN_FM1R_FBM26                      0x04000000U        /*!<Filter Init Mode bit 26 */
-#define  CAN_FM1R_FBM27                      0x08000000U        /*!<Filter Init Mode bit 27 */
-
-/*******************  Bit definition for CAN_FS1R register  *******************/
-#define  CAN_FS1R_FSC                        0x0FFFFFFFU        /*!<Filter Scale Configuration */
-#define  CAN_FS1R_FSC0                       0x00000001U        /*!<Filter Scale Configuration bit 0 */
-#define  CAN_FS1R_FSC1                       0x00000002U        /*!<Filter Scale Configuration bit 1 */
-#define  CAN_FS1R_FSC2                       0x00000004U        /*!<Filter Scale Configuration bit 2 */
-#define  CAN_FS1R_FSC3                       0x00000008U        /*!<Filter Scale Configuration bit 3 */
-#define  CAN_FS1R_FSC4                       0x00000010U        /*!<Filter Scale Configuration bit 4 */
-#define  CAN_FS1R_FSC5                       0x00000020U        /*!<Filter Scale Configuration bit 5 */
-#define  CAN_FS1R_FSC6                       0x00000040U        /*!<Filter Scale Configuration bit 6 */
-#define  CAN_FS1R_FSC7                       0x00000080U        /*!<Filter Scale Configuration bit 7 */
-#define  CAN_FS1R_FSC8                       0x00000100U        /*!<Filter Scale Configuration bit 8 */
-#define  CAN_FS1R_FSC9                       0x00000200U        /*!<Filter Scale Configuration bit 9 */
-#define  CAN_FS1R_FSC10                      0x00000400U        /*!<Filter Scale Configuration bit 10 */
-#define  CAN_FS1R_FSC11                      0x00000800U        /*!<Filter Scale Configuration bit 11 */
-#define  CAN_FS1R_FSC12                      0x00001000U        /*!<Filter Scale Configuration bit 12 */
-#define  CAN_FS1R_FSC13                      0x00002000U        /*!<Filter Scale Configuration bit 13 */
-#define  CAN_FS1R_FSC14                      0x00004000U        /*!<Filter Scale Configuration bit 14 */
-#define  CAN_FS1R_FSC15                      0x00008000U        /*!<Filter Scale Configuration bit 15 */
-#define  CAN_FS1R_FSC16                      0x00010000U        /*!<Filter Scale Configuration bit 16 */
-#define  CAN_FS1R_FSC17                      0x00020000U        /*!<Filter Scale Configuration bit 17 */
-#define  CAN_FS1R_FSC18                      0x00040000U        /*!<Filter Scale Configuration bit 18 */
-#define  CAN_FS1R_FSC19                      0x00080000U        /*!<Filter Scale Configuration bit 19 */
-#define  CAN_FS1R_FSC20                      0x00100000U        /*!<Filter Scale Configuration bit 20 */
-#define  CAN_FS1R_FSC21                      0x00200000U        /*!<Filter Scale Configuration bit 21 */
-#define  CAN_FS1R_FSC22                      0x00400000U        /*!<Filter Scale Configuration bit 22 */
-#define  CAN_FS1R_FSC23                      0x00800000U        /*!<Filter Scale Configuration bit 23 */
-#define  CAN_FS1R_FSC24                      0x01000000U        /*!<Filter Scale Configuration bit 24 */
-#define  CAN_FS1R_FSC25                      0x02000000U        /*!<Filter Scale Configuration bit 25 */
-#define  CAN_FS1R_FSC26                      0x04000000U        /*!<Filter Scale Configuration bit 26 */
-#define  CAN_FS1R_FSC27                      0x08000000U        /*!<Filter Scale Configuration bit 27 */
-
-/******************  Bit definition for CAN_FFA1R register  *******************/
-#define  CAN_FFA1R_FFA                        0x0FFFFFFFU        /*!<Filter FIFO Assignment */
-#define  CAN_FFA1R_FFA0                       0x00000001U        /*!<Filter FIFO Assignment bit 0 */
-#define  CAN_FFA1R_FFA1                       0x00000002U        /*!<Filter FIFO Assignment bit 1 */
-#define  CAN_FFA1R_FFA2                       0x00000004U        /*!<Filter FIFO Assignment bit 2 */
-#define  CAN_FFA1R_FFA3                       0x00000008U        /*!<Filter FIFO Assignment bit 3 */
-#define  CAN_FFA1R_FFA4                       0x00000010U        /*!<Filter FIFO Assignment bit 4 */
-#define  CAN_FFA1R_FFA5                       0x00000020U        /*!<Filter FIFO Assignment bit 5 */
-#define  CAN_FFA1R_FFA6                       0x00000040U        /*!<Filter FIFO Assignment bit 6 */
-#define  CAN_FFA1R_FFA7                       0x00000080U        /*!<Filter FIFO Assignment bit 7 */
-#define  CAN_FFA1R_FFA8                       0x00000100U        /*!<Filter FIFO Assignment bit 8 */
-#define  CAN_FFA1R_FFA9                       0x00000200U        /*!<Filter FIFO Assignment bit 9 */
-#define  CAN_FFA1R_FFA10                      0x00000400U        /*!<Filter FIFO Assignment bit 10 */
-#define  CAN_FFA1R_FFA11                      0x00000800U        /*!<Filter FIFO Assignment bit 11 */
-#define  CAN_FFA1R_FFA12                      0x00001000U        /*!<Filter FIFO Assignment bit 12 */
-#define  CAN_FFA1R_FFA13                      0x00002000U        /*!<Filter FIFO Assignment bit 13 */
-#define  CAN_FFA1R_FFA14                      0x00004000U        /*!<Filter FIFO Assignment bit 14 */
-#define  CAN_FFA1R_FFA15                      0x00008000U        /*!<Filter FIFO Assignment bit 15 */
-#define  CAN_FFA1R_FFA16                      0x00010000U        /*!<Filter FIFO Assignment bit 16 */
-#define  CAN_FFA1R_FFA17                      0x00020000U        /*!<Filter FIFO Assignment bit 17 */
-#define  CAN_FFA1R_FFA18                      0x00040000U        /*!<Filter FIFO Assignment bit 18 */
-#define  CAN_FFA1R_FFA19                      0x00080000U        /*!<Filter FIFO Assignment bit 19 */
-#define  CAN_FFA1R_FFA20                      0x00100000U        /*!<Filter FIFO Assignment bit 20 */
-#define  CAN_FFA1R_FFA21                      0x00200000U        /*!<Filter FIFO Assignment bit 21 */
-#define  CAN_FFA1R_FFA22                      0x00400000U        /*!<Filter FIFO Assignment bit 22 */
-#define  CAN_FFA1R_FFA23                      0x00800000U        /*!<Filter FIFO Assignment bit 23 */
-#define  CAN_FFA1R_FFA24                      0x01000000U        /*!<Filter FIFO Assignment bit 24 */
-#define  CAN_FFA1R_FFA25                      0x02000000U        /*!<Filter FIFO Assignment bit 25 */
-#define  CAN_FFA1R_FFA26                      0x04000000U        /*!<Filter FIFO Assignment bit 26 */
-#define  CAN_FFA1R_FFA27                      0x08000000U        /*!<Filter FIFO Assignment bit 27 */
-
-/*******************  Bit definition for CAN_FA1R register  *******************/
-#define  CAN_FA1R_FACT                        0x0FFFFFFFU        /*!<Filter Active */
-#define  CAN_FA1R_FACT0                       0x00000001U        /*!<Filter Active bit 0 */
-#define  CAN_FA1R_FACT1                       0x00000002U        /*!<Filter Active bit 1 */
-#define  CAN_FA1R_FACT2                       0x00000004U        /*!<Filter Active bit 2 */
-#define  CAN_FA1R_FACT3                       0x00000008U        /*!<Filter Active bit 3 */
-#define  CAN_FA1R_FACT4                       0x00000010U        /*!<Filter Active bit 4 */
-#define  CAN_FA1R_FACT5                       0x00000020U        /*!<Filter Active bit 5 */
-#define  CAN_FA1R_FACT6                       0x00000040U        /*!<Filter Active bit 6 */
-#define  CAN_FA1R_FACT7                       0x00000080U        /*!<Filter Active bit 7 */
-#define  CAN_FA1R_FACT8                       0x00000100U        /*!<Filter Active bit 8 */
-#define  CAN_FA1R_FACT9                       0x00000200U        /*!<Filter Active bit 9 */
-#define  CAN_FA1R_FACT10                      0x00000400U        /*!<Filter Active bit 10 */
-#define  CAN_FA1R_FACT11                      0x00000800U        /*!<Filter Active bit 11 */
-#define  CAN_FA1R_FACT12                      0x00001000U        /*!<Filter Active bit 12 */
-#define  CAN_FA1R_FACT13                      0x00002000U        /*!<Filter Active bit 13 */
-#define  CAN_FA1R_FACT14                      0x00004000U        /*!<Filter Active bit 14 */
-#define  CAN_FA1R_FACT15                      0x00008000U        /*!<Filter Active bit 15 */
-#define  CAN_FA1R_FACT16                      0x00010000U        /*!<Filter Active bit 16 */
-#define  CAN_FA1R_FACT17                      0x00020000U        /*!<Filter Active bit 17 */
-#define  CAN_FA1R_FACT18                      0x00040000U        /*!<Filter Active bit 18 */
-#define  CAN_FA1R_FACT19                      0x00080000U        /*!<Filter Active bit 19 */
-#define  CAN_FA1R_FACT20                      0x00100000U        /*!<Filter Active bit 20 */
-#define  CAN_FA1R_FACT21                      0x00200000U        /*!<Filter Active bit 21 */
-#define  CAN_FA1R_FACT22                      0x00400000U        /*!<Filter Active bit 22 */
-#define  CAN_FA1R_FACT23                      0x00800000U        /*!<Filter Active bit 23 */
-#define  CAN_FA1R_FACT24                      0x01000000U        /*!<Filter Active bit 24 */
-#define  CAN_FA1R_FACT25                      0x02000000U        /*!<Filter Active bit 25 */
-#define  CAN_FA1R_FACT26                      0x04000000U        /*!<Filter Active bit 26 */
-#define  CAN_FA1R_FACT27                      0x08000000U        /*!<Filter Active bit 27 */
-
-/*******************  Bit definition for CAN_F0R1 register  *******************/
-#define  CAN_F0R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F0R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F0R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F0R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F0R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F0R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F0R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F0R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F0R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F0R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F0R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F0R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F0R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F0R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F0R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F0R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F0R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F0R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F0R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F0R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F0R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F0R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F0R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F0R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F0R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F0R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F0R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F0R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F0R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F0R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F0R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F0R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R1 register  *******************/
-#define  CAN_F1R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F1R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F1R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F1R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F1R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F1R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F1R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F1R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F1R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F1R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F1R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F1R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F1R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F1R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F1R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F1R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F1R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F1R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F1R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F1R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F1R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F1R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F1R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F1R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F1R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F1R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F1R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F1R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F1R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F1R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F1R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F1R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R1 register  *******************/
-#define  CAN_F2R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F2R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F2R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F2R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F2R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F2R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F2R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F2R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F2R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F2R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F2R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F2R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F2R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F2R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F2R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F2R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F2R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F2R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F2R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F2R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F2R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F2R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F2R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F2R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F2R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F2R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F2R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F2R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F2R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F2R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F2R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F2R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R1 register  *******************/
-#define  CAN_F3R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F3R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F3R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F3R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F3R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F3R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F3R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F3R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F3R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F3R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F3R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F3R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F3R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F3R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F3R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F3R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F3R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F3R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F3R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F3R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F3R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F3R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F3R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F3R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F3R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F3R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F3R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F3R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F3R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F3R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F3R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F3R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R1 register  *******************/
-#define  CAN_F4R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F4R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F4R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F4R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F4R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F4R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F4R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F4R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F4R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F4R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F4R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F4R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F4R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F4R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F4R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F4R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F4R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F4R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F4R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F4R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F4R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F4R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F4R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F4R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F4R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F4R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F4R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F4R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F4R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F4R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F4R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F4R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R1 register  *******************/
-#define  CAN_F5R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F5R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F5R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F5R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F5R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F5R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F5R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F5R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F5R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F5R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F5R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F5R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F5R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F5R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F5R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F5R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F5R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F5R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F5R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F5R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F5R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F5R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F5R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F5R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F5R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F5R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F5R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F5R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F5R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F5R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F5R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F5R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R1 register  *******************/
-#define  CAN_F6R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F6R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F6R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F6R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F6R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F6R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F6R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F6R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F6R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F6R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F6R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F6R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F6R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F6R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F6R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F6R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F6R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F6R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F6R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F6R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F6R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F6R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F6R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F6R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F6R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F6R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F6R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F6R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F6R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F6R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F6R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F6R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R1 register  *******************/
-#define  CAN_F7R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F7R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F7R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F7R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F7R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F7R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F7R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F7R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F7R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F7R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F7R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F7R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F7R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F7R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F7R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F7R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F7R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F7R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F7R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F7R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F7R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F7R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F7R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F7R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F7R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F7R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F7R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F7R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F7R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F7R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F7R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F7R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R1 register  *******************/
-#define  CAN_F8R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F8R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F8R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F8R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F8R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F8R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F8R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F8R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F8R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F8R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F8R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F8R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F8R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F8R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F8R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F8R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F8R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F8R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F8R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F8R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F8R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F8R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F8R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F8R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F8R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F8R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F8R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F8R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F8R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F8R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F8R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F8R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R1 register  *******************/
-#define  CAN_F9R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F9R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F9R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F9R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F9R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F9R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F9R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F9R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F9R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F9R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F9R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F9R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F9R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F9R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F9R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F9R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F9R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F9R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F9R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F9R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F9R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F9R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F9R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F9R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F9R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F9R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F9R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F9R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F9R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F9R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F9R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F9R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R1 register  ******************/
-#define  CAN_F10R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F10R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F10R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F10R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F10R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F10R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F10R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F10R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F10R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F10R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F10R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F10R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F10R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F10R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F10R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F10R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F10R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F10R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F10R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F10R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F10R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F10R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F10R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F10R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F10R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F10R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F10R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F10R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F10R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F10R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F10R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F10R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R1 register  ******************/
-#define  CAN_F11R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F11R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F11R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F11R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F11R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F11R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F11R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F11R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F11R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F11R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F11R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F11R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F11R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F11R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F11R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F11R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F11R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F11R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F11R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F11R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F11R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F11R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F11R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F11R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F11R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F11R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F11R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F11R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F11R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F11R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F11R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F11R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R1 register  ******************/
-#define  CAN_F12R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F12R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F12R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F12R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F12R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F12R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F12R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F12R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F12R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F12R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F12R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F12R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F12R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F12R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F12R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F12R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F12R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F12R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F12R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F12R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F12R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F12R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F12R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F12R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F12R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F12R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F12R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F12R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F12R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F12R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F12R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F12R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R1 register  ******************/
-#define  CAN_F13R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F13R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F13R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F13R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F13R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F13R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F13R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F13R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F13R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F13R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F13R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F13R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F13R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F13R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F13R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F13R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F13R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F13R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F13R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F13R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F13R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F13R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F13R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F13R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F13R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F13R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F13R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F13R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F13R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F13R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F13R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F13R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F0R2 register  *******************/
-#define  CAN_F0R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F0R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F0R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F0R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F0R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F0R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F0R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F0R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F0R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F0R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F0R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F0R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F0R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F0R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F0R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F0R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F0R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F0R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F0R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F0R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F0R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F0R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F0R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F0R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F0R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F0R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F0R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F0R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F0R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F0R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F0R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F0R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R2 register  *******************/
-#define  CAN_F1R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F1R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F1R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F1R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F1R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F1R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F1R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F1R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F1R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F1R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F1R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F1R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F1R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F1R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F1R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F1R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F1R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F1R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F1R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F1R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F1R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F1R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F1R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F1R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F1R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F1R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F1R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F1R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F1R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F1R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F1R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F1R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R2 register  *******************/
-#define  CAN_F2R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F2R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F2R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F2R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F2R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F2R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F2R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F2R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F2R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F2R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F2R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F2R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F2R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F2R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F2R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F2R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F2R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F2R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F2R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F2R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F2R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F2R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F2R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F2R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F2R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F2R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F2R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F2R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F2R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F2R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F2R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F2R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R2 register  *******************/
-#define  CAN_F3R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F3R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F3R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F3R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F3R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F3R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F3R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F3R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F3R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F3R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F3R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F3R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F3R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F3R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F3R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F3R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F3R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F3R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F3R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F3R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F3R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F3R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F3R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F3R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F3R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F3R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F3R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F3R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F3R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F3R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F3R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F3R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R2 register  *******************/
-#define  CAN_F4R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F4R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F4R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F4R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F4R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F4R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F4R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F4R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F4R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F4R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F4R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F4R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F4R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F4R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F4R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F4R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F4R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F4R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F4R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F4R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F4R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F4R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F4R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F4R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F4R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F4R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F4R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F4R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F4R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F4R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F4R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F4R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R2 register  *******************/
-#define  CAN_F5R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F5R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F5R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F5R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F5R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F5R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F5R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F5R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F5R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F5R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F5R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F5R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F5R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F5R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F5R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F5R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F5R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F5R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F5R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F5R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F5R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F5R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F5R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F5R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F5R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F5R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F5R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F5R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F5R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F5R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F5R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F5R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R2 register  *******************/
-#define  CAN_F6R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F6R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F6R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F6R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F6R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F6R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F6R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F6R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F6R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F6R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F6R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F6R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F6R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F6R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F6R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F6R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F6R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F6R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F6R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F6R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F6R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F6R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F6R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F6R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F6R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F6R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F6R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F6R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F6R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F6R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F6R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F6R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R2 register  *******************/
-#define  CAN_F7R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F7R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F7R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F7R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F7R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F7R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F7R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F7R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F7R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F7R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F7R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F7R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F7R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F7R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F7R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F7R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F7R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F7R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F7R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F7R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F7R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F7R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F7R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F7R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F7R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F7R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F7R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F7R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F7R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F7R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F7R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F7R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R2 register  *******************/
-#define  CAN_F8R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F8R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F8R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F8R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F8R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F8R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F8R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F8R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F8R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F8R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F8R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F8R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F8R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F8R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F8R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F8R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F8R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F8R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F8R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F8R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F8R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F8R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F8R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F8R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F8R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F8R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F8R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F8R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F8R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F8R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F8R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F8R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R2 register  *******************/
-#define  CAN_F9R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F9R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F9R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F9R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F9R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F9R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F9R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F9R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F9R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F9R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F9R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F9R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F9R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F9R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F9R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F9R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F9R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F9R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F9R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F9R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F9R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F9R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F9R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F9R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F9R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F9R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F9R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F9R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F9R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F9R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F9R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F9R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R2 register  ******************/
-#define  CAN_F10R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F10R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F10R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F10R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F10R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F10R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F10R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F10R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F10R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F10R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F10R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F10R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F10R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F10R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F10R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F10R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F10R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F10R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F10R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F10R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F10R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F10R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F10R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F10R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F10R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F10R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F10R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F10R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F10R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F10R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F10R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F10R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R2 register  ******************/
-#define  CAN_F11R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F11R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F11R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F11R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F11R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F11R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F11R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F11R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F11R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F11R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F11R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F11R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F11R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F11R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F11R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F11R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F11R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F11R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F11R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F11R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F11R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F11R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F11R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F11R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F11R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F11R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F11R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F11R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F11R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F11R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F11R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F11R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R2 register  ******************/
-#define  CAN_F12R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F12R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F12R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F12R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F12R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F12R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F12R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F12R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F12R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F12R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F12R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F12R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F12R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F12R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F12R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F12R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F12R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F12R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F12R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F12R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F12R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F12R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F12R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F12R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F12R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F12R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F12R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F12R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F12R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F12R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F12R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F12R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R2 register  ******************/
-#define  CAN_F13R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F13R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F13R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F13R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F13R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F13R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F13R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F13R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F13R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F13R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F13R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F13R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F13R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F13R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F13R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F13R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F13R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F13R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F13R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F13R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F13R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F13R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F13R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F13R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F13R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F13R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F13R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F13R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F13R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F13R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F13R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F13R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRC calculation unit                              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           0xFFFFFFFFU /*!< Data register bits */
-
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         0xFFU        /*!< General-purpose 8-bit data register bits */
-
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        0x01U        /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Crypto Processor                                */
-/*                                                                            */
-/******************************************************************************/
-/******************* Bits definition for CRYP_CR register  ********************/
-#define CRYP_CR_ALGODIR                      0x00000004U
-
-#define CRYP_CR_ALGOMODE                     0x00080038U
-#define CRYP_CR_ALGOMODE_0                   0x00000008U
-#define CRYP_CR_ALGOMODE_1                   0x00000010U
-#define CRYP_CR_ALGOMODE_2                   0x00000020U
-#define CRYP_CR_ALGOMODE_TDES_ECB            0x00000000U
-#define CRYP_CR_ALGOMODE_TDES_CBC            0x00000008U
-#define CRYP_CR_ALGOMODE_DES_ECB             0x00000010U
-#define CRYP_CR_ALGOMODE_DES_CBC             0x00000018U
-#define CRYP_CR_ALGOMODE_AES_ECB             0x00000020U
-#define CRYP_CR_ALGOMODE_AES_CBC             0x00000028U
-#define CRYP_CR_ALGOMODE_AES_CTR             0x00000030U
-#define CRYP_CR_ALGOMODE_AES_KEY             0x00000038U
-
-#define CRYP_CR_DATATYPE                     0x000000C0U
-#define CRYP_CR_DATATYPE_0                   0x00000040U
-#define CRYP_CR_DATATYPE_1                   0x00000080U
-#define CRYP_CR_KEYSIZE                      0x00000300U
-#define CRYP_CR_KEYSIZE_0                    0x00000100U
-#define CRYP_CR_KEYSIZE_1                    0x00000200U
-#define CRYP_CR_FFLUSH                       0x00004000U
-#define CRYP_CR_CRYPEN                       0x00008000U
-
-#define CRYP_CR_GCM_CCMPH                    0x00030000U
-#define CRYP_CR_GCM_CCMPH_0                  0x00010000U
-#define CRYP_CR_GCM_CCMPH_1                  0x00020000U
-#define CRYP_CR_ALGOMODE_3                   0x00080000U 
-
-/****************** Bits definition for CRYP_SR register  *********************/
-#define CRYP_SR_IFEM                         0x00000001U
-#define CRYP_SR_IFNF                         0x00000002U
-#define CRYP_SR_OFNE                         0x00000004U
-#define CRYP_SR_OFFU                         0x00000008U
-#define CRYP_SR_BUSY                         0x00000010U
-/****************** Bits definition for CRYP_DMACR register  ******************/
-#define CRYP_DMACR_DIEN                      0x00000001U
-#define CRYP_DMACR_DOEN                      0x00000002U
-/*****************  Bits definition for CRYP_IMSCR register  ******************/
-#define CRYP_IMSCR_INIM                      0x00000001U
-#define CRYP_IMSCR_OUTIM                     0x00000002U
-/****************** Bits definition for CRYP_RISR register  *******************/
-#define CRYP_RISR_OUTRIS                     0x00000001U
-#define CRYP_RISR_INRIS                      0x00000002U
-/****************** Bits definition for CRYP_MISR register  *******************/
-#define CRYP_MISR_INMIS                      0x00000001U
-#define CRYP_MISR_OUTMIS                     0x00000002U
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Digital to Analog Converter                           */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DAC_CR register  ********************/
-#define  DAC_CR_EN1                          0x00000001U        /*!<DAC channel1 enable */
-#define  DAC_CR_BOFF1                        0x00000002U        /*!<DAC channel1 output buffer disable */
-#define  DAC_CR_TEN1                         0x00000004U        /*!<DAC channel1 Trigger enable */
-
-#define  DAC_CR_TSEL1                        0x00000038U        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define  DAC_CR_TSEL1_0                      0x00000008U        /*!<Bit 0 */
-#define  DAC_CR_TSEL1_1                      0x00000010U        /*!<Bit 1 */
-#define  DAC_CR_TSEL1_2                      0x00000020U        /*!<Bit 2 */
-
-#define  DAC_CR_WAVE1                        0x000000C0U        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE1_0                      0x00000040U        /*!<Bit 0 */
-#define  DAC_CR_WAVE1_1                      0x00000080U        /*!<Bit 1 */
-
-#define  DAC_CR_MAMP1                        0x00000F00U        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP1_0                      0x00000100U        /*!<Bit 0 */
-#define  DAC_CR_MAMP1_1                      0x00000200U        /*!<Bit 1 */
-#define  DAC_CR_MAMP1_2                      0x00000400U        /*!<Bit 2 */
-#define  DAC_CR_MAMP1_3                      0x00000800U        /*!<Bit 3 */
-
-#define  DAC_CR_DMAEN1                       0x00001000U        /*!<DAC channel1 DMA enable */
-#define  DAC_CR_DMAUDRIE1                    0x00002000U        /*!<DAC channel1 DMA underrun interrupt enable*/
-#define  DAC_CR_EN2                          0x00010000U        /*!<DAC channel2 enable */
-#define  DAC_CR_BOFF2                        0x00020000U        /*!<DAC channel2 output buffer disable */
-#define  DAC_CR_TEN2                         0x00040000U        /*!<DAC channel2 Trigger enable */
-
-#define  DAC_CR_TSEL2                        0x00380000U        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define  DAC_CR_TSEL2_0                      0x00080000U        /*!<Bit 0 */
-#define  DAC_CR_TSEL2_1                      0x00100000U        /*!<Bit 1 */
-#define  DAC_CR_TSEL2_2                      0x00200000U        /*!<Bit 2 */
-
-#define  DAC_CR_WAVE2                        0x00C00000U        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE2_0                      0x00400000U        /*!<Bit 0 */
-#define  DAC_CR_WAVE2_1                      0x00800000U        /*!<Bit 1 */
-
-#define  DAC_CR_MAMP2                        0x0F000000U        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP2_0                      0x01000000U        /*!<Bit 0 */
-#define  DAC_CR_MAMP2_1                      0x02000000U        /*!<Bit 1 */
-#define  DAC_CR_MAMP2_2                      0x04000000U        /*!<Bit 2 */
-#define  DAC_CR_MAMP2_3                      0x08000000U        /*!<Bit 3 */
-
-#define  DAC_CR_DMAEN2                       0x10000000U        /*!<DAC channel2 DMA enabled */
-#define  DAC_CR_DMAUDRIE2                    0x20000000U        /*!<DAC channel2 DMA underrun interrupt enable*/
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define  DAC_SWTRIGR_SWTRIG1                 0x01U               /*!<DAC channel1 software trigger */
-#define  DAC_SWTRIGR_SWTRIG2                 0x02U               /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define  DAC_DHR12R1_DACC1DHR                0x0FFFU            /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define  DAC_DHR12L1_DACC1DHR                0xFFF0U            /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define  DAC_DHR8R1_DACC1DHR                 0xFFU               /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define  DAC_DHR12R2_DACC2DHR                0x0FFFU            /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define  DAC_DHR12L2_DACC2DHR                0xFFF0U            /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define  DAC_DHR8R2_DACC2DHR                 0xFFU               /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define  DAC_DHR12RD_DACC1DHR                0x00000FFFU        /*!<DAC channel1 12-bit Right aligned data */
-#define  DAC_DHR12RD_DACC2DHR                0x0FFF0000U        /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define  DAC_DHR12LD_DACC1DHR                0x0000FFF0U        /*!<DAC channel1 12-bit Left aligned data */
-#define  DAC_DHR12LD_DACC2DHR                0xFFF00000U        /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define  DAC_DHR8RD_DACC1DHR                 0x00FFU            /*!<DAC channel1 8-bit Right aligned data */
-#define  DAC_DHR8RD_DACC2DHR                 0xFF00U            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define  DAC_DOR1_DACC1DOR                   0x0FFFU            /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define  DAC_DOR2_DACC2DOR                   0x0FFFU            /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define  DAC_SR_DMAUDR1                      0x00002000U        /*!<DAC channel1 DMA underrun flag */
-#define  DAC_SR_DMAUDR2                      0x20000000U        /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 Debug MCU                                  */
-/*                                                                            */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    DCMI                                    */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DCMI_CR register  ******************/
-#define DCMI_CR_CAPTURE                      0x00000001U
-#define DCMI_CR_CM                           0x00000002U
-#define DCMI_CR_CROP                         0x00000004U
-#define DCMI_CR_JPEG                         0x00000008U
-#define DCMI_CR_ESS                          0x00000010U
-#define DCMI_CR_PCKPOL                       0x00000020U
-#define DCMI_CR_HSPOL                        0x00000040U
-#define DCMI_CR_VSPOL                        0x00000080U
-#define DCMI_CR_FCRC_0                       0x00000100U
-#define DCMI_CR_FCRC_1                       0x00000200U
-#define DCMI_CR_EDM_0                        0x00000400U
-#define DCMI_CR_EDM_1                        0x00000800U
-#define DCMI_CR_CRE                          0x00001000U
-#define DCMI_CR_ENABLE                       0x00004000U
-
-/********************  Bits definition for DCMI_SR register  ******************/
-#define DCMI_SR_HSYNC                        0x00000001U
-#define DCMI_SR_VSYNC                        0x00000002U
-#define DCMI_SR_FNE                          0x00000004U
-
-/********************  Bits definition for DCMI_RIS register  *****************/
-#define DCMI_RIS_FRAME_RIS                   0x00000001U
-#define DCMI_RIS_OVR_RIS                     0x00000002U
-#define DCMI_RIS_ERR_RIS                     0x00000004U
-#define DCMI_RIS_VSYNC_RIS                   0x00000008U
-#define DCMI_RIS_LINE_RIS                    0x00000010U
-/* Legacy defines */
-#define DCMI_RISR_FRAME_RIS                  DCMI_RIS_FRAME_RIS
-#define DCMI_RISR_OVR_RIS                    DCMI_RIS_OVR_RIS
-#define DCMI_RISR_ERR_RIS                    DCMI_RIS_ERR_RIS
-#define DCMI_RISR_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS
-#define DCMI_RISR_LINE_RIS                   DCMI_RIS_LINE_RIS
-#define DCMI_RISR_OVF_RIS                    DCMI_RIS_OVR_RIS
-
-/********************  Bits definition for DCMI_IER register  *****************/
-#define DCMI_IER_FRAME_IE                    0x00000001U
-#define DCMI_IER_OVR_IE                      0x00000002U
-#define DCMI_IER_ERR_IE                      0x00000004U
-#define DCMI_IER_VSYNC_IE                    0x00000008U
-#define DCMI_IER_LINE_IE                     0x00000010U
-/* Legacy defines */
-#define DCMI_IER_OVF_IE                      DCMI_IER_OVR_IE
-
-/********************  Bits definition for DCMI_MIS register  *****************/
-#define DCMI_MIS_FRAME_MIS                   0x00000001U
-#define DCMI_MIS_OVR_MIS                     0x00000002U
-#define DCMI_MIS_ERR_MIS                     0x00000004U
-#define DCMI_MIS_VSYNC_MIS                   0x00000008U
-#define DCMI_MIS_LINE_MIS                    0x00000010U
-
-/* Legacy defines */
-#define DCMI_MISR_FRAME_MIS                  DCMI_MIS_FRAME_MIS
-#define DCMI_MISR_OVF_MIS                    DCMI_MIS_OVR_MIS
-#define DCMI_MISR_ERR_MIS                    DCMI_MIS_ERR_MIS
-#define DCMI_MISR_VSYNC_MIS                  DCMI_MIS_VSYNC_MIS
-#define DCMI_MISR_LINE_MIS                   DCMI_MIS_LINE_MIS
-
-/********************  Bits definition for DCMI_ICR register  *****************/
-#define DCMI_ICR_FRAME_ISC                   0x00000001U
-#define DCMI_ICR_OVR_ISC                     0x00000002U
-#define DCMI_ICR_ERR_ISC                     0x00000004U
-#define DCMI_ICR_VSYNC_ISC                   0x00000008U
-#define DCMI_ICR_LINE_ISC                    0x00000010U
-
-/* Legacy defines */
-#define DCMI_ICR_OVF_ISC                     DCMI_ICR_OVR_ISC
-
-/********************  Bits definition for DCMI_ESCR register  ******************/
-#define DCMI_ESCR_FSC                        0x000000FFU
-#define DCMI_ESCR_LSC                        0x0000FF00U
-#define DCMI_ESCR_LEC                        0x00FF0000U
-#define DCMI_ESCR_FEC                        0xFF000000U
-
-/********************  Bits definition for DCMI_ESUR register  ******************/
-#define DCMI_ESUR_FSU                        0x000000FFU
-#define DCMI_ESUR_LSU                        0x0000FF00U
-#define DCMI_ESUR_LEU                        0x00FF0000U
-#define DCMI_ESUR_FEU                        0xFF000000U
-
-/********************  Bits definition for DCMI_CWSTRT register  ******************/
-#define DCMI_CWSTRT_HOFFCNT                  0x00003FFFU
-#define DCMI_CWSTRT_VST                      0x1FFF0000U
-
-/********************  Bits definition for DCMI_CWSIZE register  ******************/
-#define DCMI_CWSIZE_CAPCNT                   0x00003FFFU
-#define DCMI_CWSIZE_VLINE                    0x3FFF0000U
-
-/********************  Bits definition for DCMI_DR register  ******************/
-#define DCMI_DR_BYTE0                        0x000000FFU
-#define DCMI_DR_BYTE1                        0x0000FF00U
-#define DCMI_DR_BYTE2                        0x00FF0000U
-#define DCMI_DR_BYTE3                        0xFF000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                             DMA Controller                                 */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DMA_SxCR register  *****************/
-#define DMA_SxCR_CHSEL                       0x0E000000U
-#define DMA_SxCR_CHSEL_0                     0x02000000U
-#define DMA_SxCR_CHSEL_1                     0x04000000U
-#define DMA_SxCR_CHSEL_2                     0x08000000U
-#define DMA_SxCR_MBURST                      0x01800000U
-#define DMA_SxCR_MBURST_0                    0x00800000U
-#define DMA_SxCR_MBURST_1                    0x01000000U
-#define DMA_SxCR_PBURST                      0x00600000U
-#define DMA_SxCR_PBURST_0                    0x00200000U
-#define DMA_SxCR_PBURST_1                    0x00400000U
-#define DMA_SxCR_CT                          0x00080000U
-#define DMA_SxCR_DBM                         0x00040000U
-#define DMA_SxCR_PL                          0x00030000U
-#define DMA_SxCR_PL_0                        0x00010000U
-#define DMA_SxCR_PL_1                        0x00020000U
-#define DMA_SxCR_PINCOS                      0x00008000U
-#define DMA_SxCR_MSIZE                       0x00006000U
-#define DMA_SxCR_MSIZE_0                     0x00002000U
-#define DMA_SxCR_MSIZE_1                     0x00004000U
-#define DMA_SxCR_PSIZE                       0x00001800U
-#define DMA_SxCR_PSIZE_0                     0x00000800U
-#define DMA_SxCR_PSIZE_1                     0x00001000U
-#define DMA_SxCR_MINC                        0x00000400U
-#define DMA_SxCR_PINC                        0x00000200U
-#define DMA_SxCR_CIRC                        0x00000100U
-#define DMA_SxCR_DIR                         0x000000C0U
-#define DMA_SxCR_DIR_0                       0x00000040U
-#define DMA_SxCR_DIR_1                       0x00000080U
-#define DMA_SxCR_PFCTRL                      0x00000020U
-#define DMA_SxCR_TCIE                        0x00000010U
-#define DMA_SxCR_HTIE                        0x00000008U
-#define DMA_SxCR_TEIE                        0x00000004U
-#define DMA_SxCR_DMEIE                       0x00000002U
-#define DMA_SxCR_EN                          0x00000001U
-
-/* Legacy defines */
-#define DMA_SxCR_ACK                         0x00100000U
-
-/********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            0x0000FFFFU
-#define DMA_SxNDT_0                          0x00000001U
-#define DMA_SxNDT_1                          0x00000002U
-#define DMA_SxNDT_2                          0x00000004U
-#define DMA_SxNDT_3                          0x00000008U
-#define DMA_SxNDT_4                          0x00000010U
-#define DMA_SxNDT_5                          0x00000020U
-#define DMA_SxNDT_6                          0x00000040U
-#define DMA_SxNDT_7                          0x00000080U
-#define DMA_SxNDT_8                          0x00000100U
-#define DMA_SxNDT_9                          0x00000200U
-#define DMA_SxNDT_10                         0x00000400U
-#define DMA_SxNDT_11                         0x00000800U
-#define DMA_SxNDT_12                         0x00001000U
-#define DMA_SxNDT_13                         0x00002000U
-#define DMA_SxNDT_14                         0x00004000U
-#define DMA_SxNDT_15                         0x00008000U
-
-/********************  Bits definition for DMA_SxFCR register  ****************/ 
-#define DMA_SxFCR_FEIE                       0x00000080U
-#define DMA_SxFCR_FS                         0x00000038U
-#define DMA_SxFCR_FS_0                       0x00000008U
-#define DMA_SxFCR_FS_1                       0x00000010U
-#define DMA_SxFCR_FS_2                       0x00000020U
-#define DMA_SxFCR_DMDIS                      0x00000004U
-#define DMA_SxFCR_FTH                        0x00000003U
-#define DMA_SxFCR_FTH_0                      0x00000001U
-#define DMA_SxFCR_FTH_1                      0x00000002U
-
-/********************  Bits definition for DMA_LISR register  *****************/ 
-#define DMA_LISR_TCIF3                       0x08000000U
-#define DMA_LISR_HTIF3                       0x04000000U
-#define DMA_LISR_TEIF3                       0x02000000U
-#define DMA_LISR_DMEIF3                      0x01000000U
-#define DMA_LISR_FEIF3                       0x00400000U
-#define DMA_LISR_TCIF2                       0x00200000U
-#define DMA_LISR_HTIF2                       0x00100000U
-#define DMA_LISR_TEIF2                       0x00080000U
-#define DMA_LISR_DMEIF2                      0x00040000U
-#define DMA_LISR_FEIF2                       0x00010000U
-#define DMA_LISR_TCIF1                       0x00000800U
-#define DMA_LISR_HTIF1                       0x00000400U
-#define DMA_LISR_TEIF1                       0x00000200U
-#define DMA_LISR_DMEIF1                      0x00000100U
-#define DMA_LISR_FEIF1                       0x00000040U
-#define DMA_LISR_TCIF0                       0x00000020U
-#define DMA_LISR_HTIF0                       0x00000010U
-#define DMA_LISR_TEIF0                       0x00000008U
-#define DMA_LISR_DMEIF0                      0x00000004U
-#define DMA_LISR_FEIF0                       0x00000001U
-
-/********************  Bits definition for DMA_HISR register  *****************/ 
-#define DMA_HISR_TCIF7                       0x08000000U
-#define DMA_HISR_HTIF7                       0x04000000U
-#define DMA_HISR_TEIF7                       0x02000000U
-#define DMA_HISR_DMEIF7                      0x01000000U
-#define DMA_HISR_FEIF7                       0x00400000U
-#define DMA_HISR_TCIF6                       0x00200000U
-#define DMA_HISR_HTIF6                       0x00100000U
-#define DMA_HISR_TEIF6                       0x00080000U
-#define DMA_HISR_DMEIF6                      0x00040000U
-#define DMA_HISR_FEIF6                       0x00010000U
-#define DMA_HISR_TCIF5                       0x00000800U
-#define DMA_HISR_HTIF5                       0x00000400U
-#define DMA_HISR_TEIF5                       0x00000200U
-#define DMA_HISR_DMEIF5                      0x00000100U
-#define DMA_HISR_FEIF5                       0x00000040U
-#define DMA_HISR_TCIF4                       0x00000020U
-#define DMA_HISR_HTIF4                       0x00000010U
-#define DMA_HISR_TEIF4                       0x00000008U
-#define DMA_HISR_DMEIF4                      0x00000004U
-#define DMA_HISR_FEIF4                       0x00000001U
-
-/********************  Bits definition for DMA_LIFCR register  ****************/ 
-#define DMA_LIFCR_CTCIF3                     0x08000000U
-#define DMA_LIFCR_CHTIF3                     0x04000000U
-#define DMA_LIFCR_CTEIF3                     0x02000000U
-#define DMA_LIFCR_CDMEIF3                    0x01000000U
-#define DMA_LIFCR_CFEIF3                     0x00400000U
-#define DMA_LIFCR_CTCIF2                     0x00200000U
-#define DMA_LIFCR_CHTIF2                     0x00100000U
-#define DMA_LIFCR_CTEIF2                     0x00080000U
-#define DMA_LIFCR_CDMEIF2                    0x00040000U
-#define DMA_LIFCR_CFEIF2                     0x00010000U
-#define DMA_LIFCR_CTCIF1                     0x00000800U
-#define DMA_LIFCR_CHTIF1                     0x00000400U
-#define DMA_LIFCR_CTEIF1                     0x00000200U
-#define DMA_LIFCR_CDMEIF1                    0x00000100U
-#define DMA_LIFCR_CFEIF1                     0x00000040U
-#define DMA_LIFCR_CTCIF0                     0x00000020U
-#define DMA_LIFCR_CHTIF0                     0x00000010U
-#define DMA_LIFCR_CTEIF0                     0x00000008U
-#define DMA_LIFCR_CDMEIF0                    0x00000004U
-#define DMA_LIFCR_CFEIF0                     0x00000001U
-
-/********************  Bits definition for DMA_HIFCR  register  ****************/ 
-#define DMA_HIFCR_CTCIF7                     0x08000000U
-#define DMA_HIFCR_CHTIF7                     0x04000000U
-#define DMA_HIFCR_CTEIF7                     0x02000000U
-#define DMA_HIFCR_CDMEIF7                    0x01000000U
-#define DMA_HIFCR_CFEIF7                     0x00400000U
-#define DMA_HIFCR_CTCIF6                     0x00200000U
-#define DMA_HIFCR_CHTIF6                     0x00100000U
-#define DMA_HIFCR_CTEIF6                     0x00080000U
-#define DMA_HIFCR_CDMEIF6                    0x00040000U
-#define DMA_HIFCR_CFEIF6                     0x00010000U
-#define DMA_HIFCR_CTCIF5                     0x00000800U
-#define DMA_HIFCR_CHTIF5                     0x00000400U
-#define DMA_HIFCR_CTEIF5                     0x00000200U
-#define DMA_HIFCR_CDMEIF5                    0x00000100U
-#define DMA_HIFCR_CFEIF5                     0x00000040U
-#define DMA_HIFCR_CTCIF4                     0x00000020U
-#define DMA_HIFCR_CHTIF4                     0x00000010U
-#define DMA_HIFCR_CTEIF4                     0x00000008U
-#define DMA_HIFCR_CDMEIF4                    0x00000004U
-#define DMA_HIFCR_CFEIF4                     0x00000001U
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                         AHB Master DMA2D Controller (DMA2D)                */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for DMA2D_CR register  ******************/
-
-#define DMA2D_CR_START                     0x00000001U               /*!< Start transfer */
-#define DMA2D_CR_SUSP                      0x00000002U               /*!< Suspend transfer */
-#define DMA2D_CR_ABORT                     0x00000004U               /*!< Abort transfer */
-#define DMA2D_CR_TEIE                      0x00000100U               /*!< Transfer Error Interrupt Enable */
-#define DMA2D_CR_TCIE                      0x00000200U               /*!< Transfer Complete Interrupt Enable */
-#define DMA2D_CR_TWIE                      0x00000400U               /*!< Transfer Watermark Interrupt Enable */
-#define DMA2D_CR_CAEIE                     0x00000800U               /*!< CLUT Access Error Interrupt Enable */
-#define DMA2D_CR_CTCIE                     0x00001000U               /*!< CLUT Transfer Complete Interrupt Enable */
-#define DMA2D_CR_CEIE                      0x00002000U               /*!< Configuration Error Interrupt Enable */
-#define DMA2D_CR_MODE                      0x00030000U               /*!< DMA2D Mode[1:0] */
-#define DMA2D_CR_MODE_0                    0x00010000U               /*!< DMA2D Mode bit 0 */
-#define DMA2D_CR_MODE_1                    0x00020000U               /*!< DMA2D Mode bit 1 */
-
-/********************  Bit definition for DMA2D_ISR register  *****************/
-
-#define DMA2D_ISR_TEIF                     0x00000001U               /*!< Transfer Error Interrupt Flag */
-#define DMA2D_ISR_TCIF                     0x00000002U               /*!< Transfer Complete Interrupt Flag */
-#define DMA2D_ISR_TWIF                     0x00000004U               /*!< Transfer Watermark Interrupt Flag */
-#define DMA2D_ISR_CAEIF                    0x00000008U               /*!< CLUT Access Error Interrupt Flag */
-#define DMA2D_ISR_CTCIF                    0x00000010U               /*!< CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_ISR_CEIF                     0x00000020U               /*!< Configuration Error Interrupt Flag */
-
-/********************  Bit definition for DMA2D_IFCR register  ****************/
-
-#define DMA2D_IFCR_CTEIF                   0x00000001U               /*!< Clears Transfer Error Interrupt Flag         */
-#define DMA2D_IFCR_CTCIF                   0x00000002U               /*!< Clears Transfer Complete Interrupt Flag      */
-#define DMA2D_IFCR_CTWIF                   0x00000004U               /*!< Clears Transfer Watermark Interrupt Flag     */
-#define DMA2D_IFCR_CAECIF                  0x00000008U               /*!< Clears CLUT Access Error Interrupt Flag      */
-#define DMA2D_IFCR_CCTCIF                  0x00000010U               /*!< Clears CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_IFCR_CCEIF                   0x00000020U               /*!< Clears Configuration Error Interrupt Flag    */
-
-/* Legacy defines */
-#define DMA2D_IFSR_CTEIF                   DMA2D_IFCR_CTEIF                     /*!< Clears Transfer Error Interrupt Flag         */
-#define DMA2D_IFSR_CTCIF                   DMA2D_IFCR_CTCIF                     /*!< Clears Transfer Complete Interrupt Flag      */
-#define DMA2D_IFSR_CTWIF                   DMA2D_IFCR_CTWIF                     /*!< Clears Transfer Watermark Interrupt Flag     */
-#define DMA2D_IFSR_CCAEIF                  DMA2D_IFCR_CAECIF                    /*!< Clears CLUT Access Error Interrupt Flag      */
-#define DMA2D_IFSR_CCTCIF                  DMA2D_IFCR_CCTCIF                    /*!< Clears CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_IFSR_CCEIF                   DMA2D_IFCR_CCEIF                     /*!< Clears Configuration Error Interrupt Flag    */
-
-/********************  Bit definition for DMA2D_FGMAR register  ***************/
-
-#define DMA2D_FGMAR_MA                     0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_FGOR register  ****************/
-
-#define DMA2D_FGOR_LO                      0x00003FFFU               /*!< Line Offset */
-
-/********************  Bit definition for DMA2D_BGMAR register  ***************/
-
-#define DMA2D_BGMAR_MA                     0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_BGOR register  ****************/
-
-#define DMA2D_BGOR_LO                      0x00003FFFU               /*!< Line Offset */
-
-/********************  Bit definition for DMA2D_FGPFCCR register  *************/
-
-#define DMA2D_FGPFCCR_CM                   0x0000000FU               /*!< Input color mode CM[3:0] */
-#define DMA2D_FGPFCCR_CM_0                 0x00000001U               /*!< Input color mode CM bit 0 */
-#define DMA2D_FGPFCCR_CM_1                 0x00000002U               /*!< Input color mode CM bit 1 */
-#define DMA2D_FGPFCCR_CM_2                 0x00000004U               /*!< Input color mode CM bit 2 */
-#define DMA2D_FGPFCCR_CM_3                 0x00000008U               /*!< Input color mode CM bit 3 */
-#define DMA2D_FGPFCCR_CCM                  0x00000010U               /*!< CLUT Color mode */
-#define DMA2D_FGPFCCR_START                0x00000020U               /*!< Start */
-#define DMA2D_FGPFCCR_CS                   0x0000FF00U               /*!< CLUT size */
-#define DMA2D_FGPFCCR_AM                   0x00030000U               /*!< Alpha mode AM[1:0] */
-#define DMA2D_FGPFCCR_AM_0                 0x00010000U               /*!< Alpha mode AM bit 0 */
-#define DMA2D_FGPFCCR_AM_1                 0x00020000U               /*!< Alpha mode AM bit 1 */
-#define DMA2D_FGPFCCR_ALPHA                0xFF000000U               /*!< Alpha value */
-
-/********************  Bit definition for DMA2D_FGCOLR register  **************/
-
-#define DMA2D_FGCOLR_BLUE                  0x000000FFU               /*!< Blue Value */
-#define DMA2D_FGCOLR_GREEN                 0x0000FF00U               /*!< Green Value */
-#define DMA2D_FGCOLR_RED                   0x00FF0000U               /*!< Red Value */   
-
-/********************  Bit definition for DMA2D_BGPFCCR register  *************/
-
-#define DMA2D_BGPFCCR_CM                   0x0000000FU               /*!< Input color mode CM[3:0] */
-#define DMA2D_BGPFCCR_CM_0                 0x00000001U               /*!< Input color mode CM bit 0 */
-#define DMA2D_BGPFCCR_CM_1                 0x00000002U               /*!< Input color mode CM bit 1 */
-#define DMA2D_BGPFCCR_CM_2                 0x00000004U               /*!< Input color mode CM bit 2 */
-#define DMA2D_FGPFCCR_CM_3                 0x00000008U               /*!< Input color mode CM bit 3 */
-#define DMA2D_BGPFCCR_CCM                  0x00000010U               /*!< CLUT Color mode */
-#define DMA2D_BGPFCCR_START                0x00000020U               /*!< Start */
-#define DMA2D_BGPFCCR_CS                   0x0000FF00U               /*!< CLUT size */
-#define DMA2D_BGPFCCR_AM                   0x00030000U               /*!< Alpha mode AM[1:0] */
-#define DMA2D_BGPFCCR_AM_0                 0x00010000U               /*!< Alpha mode AM bit 0 */
-#define DMA2D_BGPFCCR_AM_1                 0x00020000U               /*!< Alpha mode AM bit 1 */
-#define DMA2D_BGPFCCR_ALPHA                0xFF000000U               /*!< background Input Alpha value */
-
-/********************  Bit definition for DMA2D_BGCOLR register  **************/
-
-#define DMA2D_BGCOLR_BLUE                  0x000000FFU               /*!< Blue Value */
-#define DMA2D_BGCOLR_GREEN                 0x0000FF00U               /*!< Green Value */
-#define DMA2D_BGCOLR_RED                   0x00FF0000U               /*!< Red Value */
-
-/********************  Bit definition for DMA2D_FGCMAR register  **************/
-
-#define DMA2D_FGCMAR_MA                    0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_BGCMAR register  **************/
-
-#define DMA2D_BGCMAR_MA                    0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_OPFCCR register  **************/
-
-#define DMA2D_OPFCCR_CM                    0x00000007U               /*!< Color mode CM[2:0] */
-#define DMA2D_OPFCCR_CM_0                  0x00000001U               /*!< Color mode CM bit 0 */
-#define DMA2D_OPFCCR_CM_1                  0x00000002U               /*!< Color mode CM bit 1 */
-#define DMA2D_OPFCCR_CM_2                  0x00000004U               /*!< Color mode CM bit 2 */
-
-/********************  Bit definition for DMA2D_OCOLR register  ***************/
-
-/*!<Mode_ARGB8888/RGB888 */
-
-#define DMA2D_OCOLR_BLUE_1                 0x000000FFU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_1                0x0000FF00U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_1                  0x00FF0000U               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_1                0xFF000000U               /*!< Alpha Channel Value */
-
-/*!<Mode_RGB565 */
-#define DMA2D_OCOLR_BLUE_2                 0x0000001FU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_2                0x000007E0U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_2                  0x0000F800U               /*!< Red Value */
-
-/*!<Mode_ARGB1555 */
-#define DMA2D_OCOLR_BLUE_3                 0x0000001FU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_3                0x000003E0U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_3                  0x00007C00U               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_3                0x00008000U               /*!< Alpha Channel Value */
-
-/*!<Mode_ARGB4444 */
-#define DMA2D_OCOLR_BLUE_4                 0x0000000FU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_4                0x000000F0U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_4                  0x00000F00U               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_4                0x0000F000U               /*!< Alpha Channel Value */
-
-/********************  Bit definition for DMA2D_OMAR register  ****************/
-
-#define DMA2D_OMAR_MA                      0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_OOR register  *****************/
-
-#define DMA2D_OOR_LO                       0x00003FFFU               /*!< Line Offset */
-
-/********************  Bit definition for DMA2D_NLR register  *****************/
-
-#define DMA2D_NLR_NL                       0x0000FFFFU               /*!< Number of Lines */
-#define DMA2D_NLR_PL                       0x3FFF0000U               /*!< Pixel per Lines */
-
-/********************  Bit definition for DMA2D_LWR register  *****************/
-
-#define DMA2D_LWR_LW                       0x0000FFFFU               /*!< Line Watermark */
-
-/********************  Bit definition for DMA2D_AMTCR register  ***************/
-
-#define DMA2D_AMTCR_EN                     0x00000001U               /*!< Enable */
-#define DMA2D_AMTCR_DT                     0x0000FF00U               /*!< Dead Time */
-
-/********************  Bit definition for DMA2D_FGCLUT register  **************/
-                                                                     
-/********************  Bit definition for DMA2D_BGCLUT register  **************/
-
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                    External Interrupt/Event Controller                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    FLASH                                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    0x0000000FU
-#define FLASH_ACR_LATENCY_0WS                0x00000000U
-#define FLASH_ACR_LATENCY_1WS                0x00000001U
-#define FLASH_ACR_LATENCY_2WS                0x00000002U
-#define FLASH_ACR_LATENCY_3WS                0x00000003U
-#define FLASH_ACR_LATENCY_4WS                0x00000004U
-#define FLASH_ACR_LATENCY_5WS                0x00000005U
-#define FLASH_ACR_LATENCY_6WS                0x00000006U
-#define FLASH_ACR_LATENCY_7WS                0x00000007U
-#define FLASH_ACR_LATENCY_8WS                0x00000008U
-#define FLASH_ACR_LATENCY_9WS                0x00000009U
-#define FLASH_ACR_LATENCY_10WS               0x0000000AU
-#define FLASH_ACR_LATENCY_11WS               0x0000000BU
-#define FLASH_ACR_LATENCY_12WS               0x0000000CU
-#define FLASH_ACR_LATENCY_13WS               0x0000000DU
-#define FLASH_ACR_LATENCY_14WS               0x0000000EU
-#define FLASH_ACR_LATENCY_15WS               0x0000000FU
-#define FLASH_ACR_PRFTEN                     0x00000100U
-#define FLASH_ACR_ICEN                       0x00000200U
-#define FLASH_ACR_DCEN                       0x00000400U
-#define FLASH_ACR_ICRST                      0x00000800U
-#define FLASH_ACR_DCRST                      0x00001000U
-#define FLASH_ACR_BYTE0_ADDRESS              0x40023C00U
-#define FLASH_ACR_BYTE2_ADDRESS              0x40023C03U
-
-/*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         0x00000001U
-#define FLASH_SR_SOP                         0x00000002U
-#define FLASH_SR_WRPERR                      0x00000010U
-#define FLASH_SR_PGAERR                      0x00000020U
-#define FLASH_SR_PGPERR                      0x00000040U
-#define FLASH_SR_PGSERR                      0x00000080U
-#define FLASH_SR_BSY                         0x00010000U
-
-/*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          0x00000001U
-#define FLASH_CR_SER                         0x00000002U
-#define FLASH_CR_MER                         0x00000004U
-#define FLASH_CR_MER1                        FLASH_CR_MER
-#define FLASH_CR_SNB                         0x000000F8U
-#define FLASH_CR_SNB_0                       0x00000008U
-#define FLASH_CR_SNB_1                       0x00000010U
-#define FLASH_CR_SNB_2                       0x00000020U
-#define FLASH_CR_SNB_3                       0x00000040U
-#define FLASH_CR_SNB_4                       0x00000080U
-#define FLASH_CR_PSIZE                       0x00000300U
-#define FLASH_CR_PSIZE_0                     0x00000100U
-#define FLASH_CR_PSIZE_1                     0x00000200U
-#define FLASH_CR_MER2                        0x00008000U
-#define FLASH_CR_STRT                        0x00010000U
-#define FLASH_CR_EOPIE                       0x01000000U
-#define FLASH_CR_LOCK                        0x80000000U
-
-/*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                 0x00000001U
-#define FLASH_OPTCR_OPTSTRT                 0x00000002U
-#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
-#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
-#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
-#define FLASH_OPTCR_BFB2                    0x00000010U
-#define FLASH_OPTCR_WDG_SW                  0x00000020U
-#define FLASH_OPTCR_nRST_STOP               0x00000040U
-#define FLASH_OPTCR_nRST_STDBY              0x00000080U
-#define FLASH_OPTCR_RDP                     0x0000FF00U
-#define FLASH_OPTCR_RDP_0                   0x00000100U
-#define FLASH_OPTCR_RDP_1                   0x00000200U
-#define FLASH_OPTCR_RDP_2                   0x00000400U
-#define FLASH_OPTCR_RDP_3                   0x00000800U
-#define FLASH_OPTCR_RDP_4                   0x00001000U
-#define FLASH_OPTCR_RDP_5                   0x00002000U
-#define FLASH_OPTCR_RDP_6                   0x00004000U
-#define FLASH_OPTCR_RDP_7                   0x00008000U
-#define FLASH_OPTCR_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR_nWRP_0                  0x00010000U
-#define FLASH_OPTCR_nWRP_1                  0x00020000U
-#define FLASH_OPTCR_nWRP_2                  0x00040000U
-#define FLASH_OPTCR_nWRP_3                  0x00080000U
-#define FLASH_OPTCR_nWRP_4                  0x00100000U
-#define FLASH_OPTCR_nWRP_5                  0x00200000U
-#define FLASH_OPTCR_nWRP_6                  0x00400000U
-#define FLASH_OPTCR_nWRP_7                  0x00800000U
-#define FLASH_OPTCR_nWRP_8                  0x01000000U
-#define FLASH_OPTCR_nWRP_9                  0x02000000U
-#define FLASH_OPTCR_nWRP_10                 0x04000000U
-#define FLASH_OPTCR_nWRP_11                 0x08000000U
-#define FLASH_OPTCR_DB1M                    0x40000000U 
-#define FLASH_OPTCR_SPRMOD                  0x80000000U 
-                                             
-/******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR1_nWRP_0                  0x00010000U
-#define FLASH_OPTCR1_nWRP_1                  0x00020000U
-#define FLASH_OPTCR1_nWRP_2                  0x00040000U
-#define FLASH_OPTCR1_nWRP_3                  0x00080000U
-#define FLASH_OPTCR1_nWRP_4                  0x00100000U
-#define FLASH_OPTCR1_nWRP_5                  0x00200000U
-#define FLASH_OPTCR1_nWRP_6                  0x00400000U
-#define FLASH_OPTCR1_nWRP_7                  0x00800000U
-#define FLASH_OPTCR1_nWRP_8                  0x01000000U
-#define FLASH_OPTCR1_nWRP_9                  0x02000000U
-#define FLASH_OPTCR1_nWRP_10                 0x04000000U
-#define FLASH_OPTCR1_nWRP_11                 0x08000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Flexible Memory Controller                        */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for FMC_BCR1 register  *******************/
-#define  FMC_BCR1_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR1_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FMC_BCR1_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR1_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR1_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FMC_BCR1_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR1_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR1_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_BCR1_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR1_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR1_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR1_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
-#define  FMC_BCR1_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR1_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR1_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR1_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR1_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR1_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FMC_BCR1_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FMC_BCR1_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FMC_BCR1_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FMC_BCR1_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-#define  FMC_BCR1_CCLKEN                    0x00100000U        /*!<Continous clock enable     */
-
-/******************  Bit definition for FMC_BCR2 register  *******************/
-#define  FMC_BCR2_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR2_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FMC_BCR2_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR2_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR2_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FMC_BCR2_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR2_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR2_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_BCR2_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR2_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR2_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR2_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
-#define  FMC_BCR2_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR2_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR2_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR2_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR2_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR2_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FMC_BCR2_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FMC_BCR2_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FMC_BCR2_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FMC_BCR2_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FMC_BCR3 register  *******************/
-#define  FMC_BCR3_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR3_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FMC_BCR3_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR3_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR3_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FMC_BCR3_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR3_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR3_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_BCR3_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR3_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR3_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR3_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
-#define  FMC_BCR3_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR3_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR3_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR3_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR3_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR3_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FMC_BCR3_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FMC_BCR3_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FMC_BCR3_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FMC_BCR3_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FMC_BCR4 register  *******************/
-#define  FMC_BCR4_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR4_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FMC_BCR4_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR4_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR4_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FMC_BCR4_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR4_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR4_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_BCR4_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR4_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR4_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR4_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
-#define  FMC_BCR4_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR4_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR4_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR4_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR4_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR4_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FMC_BCR4_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FMC_BCR4_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FMC_BCR4_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FMC_BCR4_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FMC_BTR1 register  ******************/
-#define  FMC_BTR1_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR1_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR1_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR1_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR1_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BTR1_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
-#define  FMC_BTR1_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR1_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR1_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR1_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BTR1_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR1_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR1_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR1_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR1_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR1_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR1_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR1_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR1_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BTR1_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR1_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR1_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR1_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR1_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BTR1_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR1_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR1_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR1_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR1_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FMC_BTR1_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR1_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR1_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR1_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR1_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FMC_BTR1_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR1_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR1_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BTR2 register  *******************/
-#define  FMC_BTR2_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR2_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR2_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR2_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR2_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BTR2_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR2_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR2_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR2_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR2_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BTR2_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR2_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR2_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR2_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR2_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR2_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR2_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR2_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR2_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BTR2_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR2_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR2_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR2_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR2_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BTR2_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR2_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR2_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR2_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR2_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FMC_BTR2_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR2_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR2_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR2_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR2_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FMC_BTR2_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR2_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR2_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/*******************  Bit definition for FMC_BTR3 register  *******************/
-#define  FMC_BTR3_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR3_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR3_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR3_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR3_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BTR3_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR3_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR3_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR3_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR3_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BTR3_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR3_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR3_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR3_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR3_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR3_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR3_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR3_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR3_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BTR3_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR3_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR3_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR3_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR3_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BTR3_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR3_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR3_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR3_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR3_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FMC_BTR3_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR3_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR3_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR3_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR3_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FMC_BTR3_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR3_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR3_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BTR4 register  *******************/
-#define  FMC_BTR4_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR4_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR4_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR4_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR4_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BTR4_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR4_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR4_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR4_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR4_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BTR4_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR4_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR4_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR4_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR4_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR4_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR4_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR4_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR4_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BTR4_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR4_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR4_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR4_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR4_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BTR4_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR4_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR4_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR4_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR4_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FMC_BTR4_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR4_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR4_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR4_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR4_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FMC_BTR4_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR4_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR4_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR1 register  ******************/
-#define  FMC_BWTR1_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR1_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR1_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR1_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR1_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BWTR1_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR1_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR1_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR1_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR1_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BWTR1_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR1_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR1_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR1_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR1_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR1_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR1_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR1_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR1_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BWTR1_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR1_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR1_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR1_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR1_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BWTR1_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR1_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR1_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR2 register  ******************/
-#define  FMC_BWTR2_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR2_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR2_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR2_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR2_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BWTR2_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR2_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR2_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR2_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR2_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BWTR2_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR2_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR2_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR2_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR2_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR2_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR2_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR2_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR2_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BWTR2_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR2_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR2_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR2_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR2_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BWTR2_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR2_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR2_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR3 register  ******************/
-#define  FMC_BWTR3_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR3_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR3_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR3_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR3_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BWTR3_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR3_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR3_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR3_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR3_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BWTR3_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR3_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR3_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR3_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR3_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR3_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR3_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR3_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR3_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BWTR3_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR3_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR3_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR3_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR3_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BWTR3_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR3_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR3_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR4 register  ******************/
-#define  FMC_BWTR4_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR4_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR4_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR4_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR4_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BWTR4_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR4_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR4_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR4_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR4_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BWTR4_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR4_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR4_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR4_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR4_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR4_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR4_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR4_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR4_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BWTR4_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR4_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR4_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR4_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR4_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BWTR4_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR4_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR4_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_PCR2 register  *******************/
-#define  FMC_PCR2_PWAITEN                   0x00000002U        /*!<Wait feature enable bit                   */
-#define  FMC_PCR2_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FMC_PCR2_PTYP                      0x00000008U        /*!<Memory type                               */
-
-#define  FMC_PCR2_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FMC_PCR2_PWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_PCR2_PWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_PCR2_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit          */
-
-#define  FMC_PCR2_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay)          */
-#define  FMC_PCR2_TCLR_0                    0x00000200U        /*!<Bit 0 */
-#define  FMC_PCR2_TCLR_1                    0x00000400U        /*!<Bit 1 */
-#define  FMC_PCR2_TCLR_2                    0x00000800U        /*!<Bit 2 */
-#define  FMC_PCR2_TCLR_3                    0x00001000U        /*!<Bit 3 */
-
-#define  FMC_PCR2_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay)           */
-#define  FMC_PCR2_TAR_0                     0x00002000U        /*!<Bit 0 */
-#define  FMC_PCR2_TAR_1                     0x00004000U        /*!<Bit 1 */
-#define  FMC_PCR2_TAR_2                     0x00008000U        /*!<Bit 2 */
-#define  FMC_PCR2_TAR_3                     0x00010000U        /*!<Bit 3 */
-
-#define  FMC_PCR2_ECCPS                     0x000E0000U        /*!<ECCPS[1:0] bits (ECC page size)           */
-#define  FMC_PCR2_ECCPS_0                   0x00020000U        /*!<Bit 0 */
-#define  FMC_PCR2_ECCPS_1                   0x00040000U        /*!<Bit 1 */
-#define  FMC_PCR2_ECCPS_2                   0x00080000U        /*!<Bit 2 */
-
-/******************  Bit definition for FMC_PCR3 register  *******************/
-#define  FMC_PCR3_PWAITEN                   0x00000002U        /*!<Wait feature enable bit                   */
-#define  FMC_PCR3_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FMC_PCR3_PTYP                      0x00000008U        /*!<Memory type                               */
-
-#define  FMC_PCR3_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FMC_PCR3_PWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_PCR3_PWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_PCR3_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit          */
-
-#define  FMC_PCR3_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay)          */
-#define  FMC_PCR3_TCLR_0                    0x00000200U        /*!<Bit 0 */
-#define  FMC_PCR3_TCLR_1                    0x00000400U        /*!<Bit 1 */
-#define  FMC_PCR3_TCLR_2                    0x00000800U        /*!<Bit 2 */
-#define  FMC_PCR3_TCLR_3                    0x00001000U        /*!<Bit 3 */
-
-#define  FMC_PCR3_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay)           */
-#define  FMC_PCR3_TAR_0                     0x00002000U        /*!<Bit 0 */
-#define  FMC_PCR3_TAR_1                     0x00004000U        /*!<Bit 1 */
-#define  FMC_PCR3_TAR_2                     0x00008000U        /*!<Bit 2 */
-#define  FMC_PCR3_TAR_3                     0x00010000U        /*!<Bit 3 */
-
-#define  FMC_PCR3_ECCPS                     0x000E0000U        /*!<ECCPS[2:0] bits (ECC page size)           */
-#define  FMC_PCR3_ECCPS_0                   0x00020000U        /*!<Bit 0 */
-#define  FMC_PCR3_ECCPS_1                   0x00040000U        /*!<Bit 1 */
-#define  FMC_PCR3_ECCPS_2                   0x00080000U        /*!<Bit 2 */
-
-/******************  Bit definition for FMC_PCR4 register  *******************/
-#define  FMC_PCR4_PWAITEN                   0x00000002U        /*!<Wait feature enable bit                   */
-#define  FMC_PCR4_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FMC_PCR4_PTYP                      0x00000008U        /*!<Memory type                               */
-
-#define  FMC_PCR4_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FMC_PCR4_PWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_PCR4_PWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_PCR4_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit          */
-
-#define  FMC_PCR4_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay)          */
-#define  FMC_PCR4_TCLR_0                    0x00000200U        /*!<Bit 0 */
-#define  FMC_PCR4_TCLR_1                    0x00000400U        /*!<Bit 1 */
-#define  FMC_PCR4_TCLR_2                    0x00000800U        /*!<Bit 2 */
-#define  FMC_PCR4_TCLR_3                    0x00001000U        /*!<Bit 3 */
-
-#define  FMC_PCR4_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay)           */
-#define  FMC_PCR4_TAR_0                     0x00002000U        /*!<Bit 0 */
-#define  FMC_PCR4_TAR_1                     0x00004000U        /*!<Bit 1 */
-#define  FMC_PCR4_TAR_2                     0x00008000U        /*!<Bit 2 */
-#define  FMC_PCR4_TAR_3                     0x00010000U        /*!<Bit 3 */
-
-#define  FMC_PCR4_ECCPS                     0x000E0000U        /*!<ECCPS[2:0] bits (ECC page size)           */
-#define  FMC_PCR4_ECCPS_0                   0x00020000U        /*!<Bit 0 */
-#define  FMC_PCR4_ECCPS_1                   0x00040000U        /*!<Bit 1 */
-#define  FMC_PCR4_ECCPS_2                   0x00080000U        /*!<Bit 2 */
-
-/*******************  Bit definition for FMC_SR2 register  *******************/
-#define  FMC_SR2_IRS                        0x01U               /*!<Interrupt Rising Edge status                */
-#define  FMC_SR2_ILS                        0x02U               /*!<Interrupt Level status                      */
-#define  FMC_SR2_IFS                        0x04U               /*!<Interrupt Falling Edge status               */
-#define  FMC_SR2_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FMC_SR2_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit        */
-#define  FMC_SR2_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FMC_SR2_FEMPT                      0x40U               /*!<FIFO empty                                  */
-
-/*******************  Bit definition for FMC_SR3 register  *******************/
-#define  FMC_SR3_IRS                        0x01U               /*!<Interrupt Rising Edge status                */
-#define  FMC_SR3_ILS                        0x02U               /*!<Interrupt Level status                      */
-#define  FMC_SR3_IFS                        0x04U               /*!<Interrupt Falling Edge status               */
-#define  FMC_SR3_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FMC_SR3_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit        */
-#define  FMC_SR3_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FMC_SR3_FEMPT                      0x40U               /*!<FIFO empty                                  */
-
-/*******************  Bit definition for FMC_SR4 register  *******************/
-#define  FMC_SR4_IRS                        0x01U               /*!<Interrupt Rising Edge status                */
-#define  FMC_SR4_ILS                        0x02U               /*!<Interrupt Level status                      */
-#define  FMC_SR4_IFS                        0x04U               /*!<Interrupt Falling Edge status               */
-#define  FMC_SR4_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FMC_SR4_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit        */
-#define  FMC_SR4_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FMC_SR4_FEMPT                      0x40U               /*!<FIFO empty                                  */
-
-/******************  Bit definition for FMC_PMEM2 register  ******************/
-#define  FMC_PMEM2_MEMSET2                  0x000000FFU        /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
-#define  FMC_PMEM2_MEMSET2_0                0x00000001U        /*!<Bit 0 */
-#define  FMC_PMEM2_MEMSET2_1                0x00000002U        /*!<Bit 1 */
-#define  FMC_PMEM2_MEMSET2_2                0x00000004U        /*!<Bit 2 */
-#define  FMC_PMEM2_MEMSET2_3                0x00000008U        /*!<Bit 3 */
-#define  FMC_PMEM2_MEMSET2_4                0x00000010U        /*!<Bit 4 */
-#define  FMC_PMEM2_MEMSET2_5                0x00000020U        /*!<Bit 5 */
-#define  FMC_PMEM2_MEMSET2_6                0x00000040U        /*!<Bit 6 */
-#define  FMC_PMEM2_MEMSET2_7                0x00000080U        /*!<Bit 7 */
-
-#define  FMC_PMEM2_MEMWAIT2                 0x0000FF00U        /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
-#define  FMC_PMEM2_MEMWAIT2_0               0x00000100U        /*!<Bit 0 */
-#define  FMC_PMEM2_MEMWAIT2_1               0x00000200U        /*!<Bit 1 */
-#define  FMC_PMEM2_MEMWAIT2_2               0x00000400U        /*!<Bit 2 */
-#define  FMC_PMEM2_MEMWAIT2_3               0x00000800U        /*!<Bit 3 */
-#define  FMC_PMEM2_MEMWAIT2_4               0x00001000U        /*!<Bit 4 */
-#define  FMC_PMEM2_MEMWAIT2_5               0x00002000U        /*!<Bit 5 */
-#define  FMC_PMEM2_MEMWAIT2_6               0x00004000U        /*!<Bit 6 */
-#define  FMC_PMEM2_MEMWAIT2_7               0x00008000U        /*!<Bit 7 */
-
-#define  FMC_PMEM2_MEMHOLD2                 0x00FF0000U        /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
-#define  FMC_PMEM2_MEMHOLD2_0               0x00010000U        /*!<Bit 0 */
-#define  FMC_PMEM2_MEMHOLD2_1               0x00020000U        /*!<Bit 1 */
-#define  FMC_PMEM2_MEMHOLD2_2               0x00040000U        /*!<Bit 2 */
-#define  FMC_PMEM2_MEMHOLD2_3               0x00080000U        /*!<Bit 3 */
-#define  FMC_PMEM2_MEMHOLD2_4               0x00100000U        /*!<Bit 4 */
-#define  FMC_PMEM2_MEMHOLD2_5               0x00200000U        /*!<Bit 5 */
-#define  FMC_PMEM2_MEMHOLD2_6               0x00400000U        /*!<Bit 6 */
-#define  FMC_PMEM2_MEMHOLD2_7               0x00800000U        /*!<Bit 7 */
-
-#define  FMC_PMEM2_MEMHIZ2                  0xFF000000U        /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
-#define  FMC_PMEM2_MEMHIZ2_0                0x01000000U        /*!<Bit 0 */
-#define  FMC_PMEM2_MEMHIZ2_1                0x02000000U        /*!<Bit 1 */
-#define  FMC_PMEM2_MEMHIZ2_2                0x04000000U        /*!<Bit 2 */
-#define  FMC_PMEM2_MEMHIZ2_3                0x08000000U        /*!<Bit 3 */
-#define  FMC_PMEM2_MEMHIZ2_4                0x10000000U        /*!<Bit 4 */
-#define  FMC_PMEM2_MEMHIZ2_5                0x20000000U        /*!<Bit 5 */
-#define  FMC_PMEM2_MEMHIZ2_6                0x40000000U        /*!<Bit 6 */
-#define  FMC_PMEM2_MEMHIZ2_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_PMEM3 register  ******************/
-#define  FMC_PMEM3_MEMSET3                  0x000000FFU        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
-#define  FMC_PMEM3_MEMSET3_0                0x00000001U        /*!<Bit 0 */
-#define  FMC_PMEM3_MEMSET3_1                0x00000002U        /*!<Bit 1 */
-#define  FMC_PMEM3_MEMSET3_2                0x00000004U        /*!<Bit 2 */
-#define  FMC_PMEM3_MEMSET3_3                0x00000008U        /*!<Bit 3 */
-#define  FMC_PMEM3_MEMSET3_4                0x00000010U        /*!<Bit 4 */
-#define  FMC_PMEM3_MEMSET3_5                0x00000020U        /*!<Bit 5 */
-#define  FMC_PMEM3_MEMSET3_6                0x00000040U        /*!<Bit 6 */
-#define  FMC_PMEM3_MEMSET3_7                0x00000080U        /*!<Bit 7 */
-
-#define  FMC_PMEM3_MEMWAIT3                 0x0000FF00U        /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
-#define  FMC_PMEM3_MEMWAIT3_0               0x00000100U        /*!<Bit 0 */
-#define  FMC_PMEM3_MEMWAIT3_1               0x00000200U        /*!<Bit 1 */
-#define  FMC_PMEM3_MEMWAIT3_2               0x00000400U        /*!<Bit 2 */
-#define  FMC_PMEM3_MEMWAIT3_3               0x00000800U        /*!<Bit 3 */
-#define  FMC_PMEM3_MEMWAIT3_4               0x00001000U        /*!<Bit 4 */
-#define  FMC_PMEM3_MEMWAIT3_5               0x00002000U        /*!<Bit 5 */
-#define  FMC_PMEM3_MEMWAIT3_6               0x00004000U        /*!<Bit 6 */
-#define  FMC_PMEM3_MEMWAIT3_7               0x00008000U        /*!<Bit 7 */
-
-#define  FMC_PMEM3_MEMHOLD3                 0x00FF0000U        /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
-#define  FMC_PMEM3_MEMHOLD3_0               0x00010000U        /*!<Bit 0 */
-#define  FMC_PMEM3_MEMHOLD3_1               0x00020000U        /*!<Bit 1 */
-#define  FMC_PMEM3_MEMHOLD3_2               0x00040000U        /*!<Bit 2 */
-#define  FMC_PMEM3_MEMHOLD3_3               0x00080000U        /*!<Bit 3 */
-#define  FMC_PMEM3_MEMHOLD3_4               0x00100000U        /*!<Bit 4 */
-#define  FMC_PMEM3_MEMHOLD3_5               0x00200000U        /*!<Bit 5 */
-#define  FMC_PMEM3_MEMHOLD3_6               0x00400000U        /*!<Bit 6 */
-#define  FMC_PMEM3_MEMHOLD3_7               0x00800000U        /*!<Bit 7 */
-
-#define  FMC_PMEM3_MEMHIZ3                  0xFF000000U        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
-#define  FMC_PMEM3_MEMHIZ3_0                0x01000000U        /*!<Bit 0 */
-#define  FMC_PMEM3_MEMHIZ3_1                0x02000000U        /*!<Bit 1 */
-#define  FMC_PMEM3_MEMHIZ3_2                0x04000000U        /*!<Bit 2 */
-#define  FMC_PMEM3_MEMHIZ3_3                0x08000000U        /*!<Bit 3 */
-#define  FMC_PMEM3_MEMHIZ3_4                0x10000000U        /*!<Bit 4 */
-#define  FMC_PMEM3_MEMHIZ3_5                0x20000000U        /*!<Bit 5 */
-#define  FMC_PMEM3_MEMHIZ3_6                0x40000000U        /*!<Bit 6 */
-#define  FMC_PMEM3_MEMHIZ3_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_PMEM4 register  ******************/
-#define  FMC_PMEM4_MEMSET4                  0x000000FFU        /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
-#define  FMC_PMEM4_MEMSET4_0                0x00000001U        /*!<Bit 0 */
-#define  FMC_PMEM4_MEMSET4_1                0x00000002U        /*!<Bit 1 */
-#define  FMC_PMEM4_MEMSET4_2                0x00000004U        /*!<Bit 2 */
-#define  FMC_PMEM4_MEMSET4_3                0x00000008U        /*!<Bit 3 */
-#define  FMC_PMEM4_MEMSET4_4                0x00000010U        /*!<Bit 4 */
-#define  FMC_PMEM4_MEMSET4_5                0x00000020U        /*!<Bit 5 */
-#define  FMC_PMEM4_MEMSET4_6                0x00000040U        /*!<Bit 6 */
-#define  FMC_PMEM4_MEMSET4_7                0x00000080U        /*!<Bit 7 */
-
-#define  FMC_PMEM4_MEMWAIT4                 0x0000FF00U        /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
-#define  FMC_PMEM4_MEMWAIT4_0               0x00000100U        /*!<Bit 0 */
-#define  FMC_PMEM4_MEMWAIT4_1               0x00000200U        /*!<Bit 1 */
-#define  FMC_PMEM4_MEMWAIT4_2               0x00000400U        /*!<Bit 2 */
-#define  FMC_PMEM4_MEMWAIT4_3               0x00000800U        /*!<Bit 3 */
-#define  FMC_PMEM4_MEMWAIT4_4               0x00001000U        /*!<Bit 4 */
-#define  FMC_PMEM4_MEMWAIT4_5               0x00002000U        /*!<Bit 5 */
-#define  FMC_PMEM4_MEMWAIT4_6               0x00004000U        /*!<Bit 6 */
-#define  FMC_PMEM4_MEMWAIT4_7               0x00008000U        /*!<Bit 7 */
-
-#define  FMC_PMEM4_MEMHOLD4                 0x00FF0000U        /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
-#define  FMC_PMEM4_MEMHOLD4_0               0x00010000U        /*!<Bit 0 */
-#define  FMC_PMEM4_MEMHOLD4_1               0x00020000U        /*!<Bit 1 */
-#define  FMC_PMEM4_MEMHOLD4_2               0x00040000U        /*!<Bit 2 */
-#define  FMC_PMEM4_MEMHOLD4_3               0x00080000U        /*!<Bit 3 */
-#define  FMC_PMEM4_MEMHOLD4_4               0x00100000U        /*!<Bit 4 */
-#define  FMC_PMEM4_MEMHOLD4_5               0x00200000U        /*!<Bit 5 */
-#define  FMC_PMEM4_MEMHOLD4_6               0x00400000U        /*!<Bit 6 */
-#define  FMC_PMEM4_MEMHOLD4_7               0x00800000U        /*!<Bit 7 */
-
-#define  FMC_PMEM4_MEMHIZ4                  0xFF000000U        /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
-#define  FMC_PMEM4_MEMHIZ4_0                0x01000000U        /*!<Bit 0 */
-#define  FMC_PMEM4_MEMHIZ4_1                0x02000000U        /*!<Bit 1 */
-#define  FMC_PMEM4_MEMHIZ4_2                0x04000000U        /*!<Bit 2 */
-#define  FMC_PMEM4_MEMHIZ4_3                0x08000000U        /*!<Bit 3 */
-#define  FMC_PMEM4_MEMHIZ4_4                0x10000000U        /*!<Bit 4 */
-#define  FMC_PMEM4_MEMHIZ4_5                0x20000000U        /*!<Bit 5 */
-#define  FMC_PMEM4_MEMHIZ4_6                0x40000000U        /*!<Bit 6 */
-#define  FMC_PMEM4_MEMHIZ4_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_PATT2 register  ******************/
-#define  FMC_PATT2_ATTSET2                  0x000000FFU        /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
-#define  FMC_PATT2_ATTSET2_0                0x00000001U        /*!<Bit 0 */
-#define  FMC_PATT2_ATTSET2_1                0x00000002U        /*!<Bit 1 */
-#define  FMC_PATT2_ATTSET2_2                0x00000004U        /*!<Bit 2 */
-#define  FMC_PATT2_ATTSET2_3                0x00000008U        /*!<Bit 3 */
-#define  FMC_PATT2_ATTSET2_4                0x00000010U        /*!<Bit 4 */
-#define  FMC_PATT2_ATTSET2_5                0x00000020U        /*!<Bit 5 */
-#define  FMC_PATT2_ATTSET2_6                0x00000040U        /*!<Bit 6 */
-#define  FMC_PATT2_ATTSET2_7                0x00000080U        /*!<Bit 7 */
-
-#define  FMC_PATT2_ATTWAIT2                 0x0000FF00U        /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
-#define  FMC_PATT2_ATTWAIT2_0               0x00000100U        /*!<Bit 0 */
-#define  FMC_PATT2_ATTWAIT2_1               0x00000200U        /*!<Bit 1 */
-#define  FMC_PATT2_ATTWAIT2_2               0x00000400U        /*!<Bit 2 */
-#define  FMC_PATT2_ATTWAIT2_3               0x00000800U        /*!<Bit 3 */
-#define  FMC_PATT2_ATTWAIT2_4               0x00001000U        /*!<Bit 4 */
-#define  FMC_PATT2_ATTWAIT2_5               0x00002000U        /*!<Bit 5 */
-#define  FMC_PATT2_ATTWAIT2_6               0x00004000U        /*!<Bit 6 */
-#define  FMC_PATT2_ATTWAIT2_7               0x00008000U        /*!<Bit 7 */
-
-#define  FMC_PATT2_ATTHOLD2                 0x00FF0000U        /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
-#define  FMC_PATT2_ATTHOLD2_0               0x00010000U        /*!<Bit 0 */
-#define  FMC_PATT2_ATTHOLD2_1               0x00020000U        /*!<Bit 1 */
-#define  FMC_PATT2_ATTHOLD2_2               0x00040000U        /*!<Bit 2 */
-#define  FMC_PATT2_ATTHOLD2_3               0x00080000U        /*!<Bit 3 */
-#define  FMC_PATT2_ATTHOLD2_4               0x00100000U        /*!<Bit 4 */
-#define  FMC_PATT2_ATTHOLD2_5               0x00200000U        /*!<Bit 5 */
-#define  FMC_PATT2_ATTHOLD2_6               0x00400000U        /*!<Bit 6 */
-#define  FMC_PATT2_ATTHOLD2_7               0x00800000U        /*!<Bit 7 */
-
-#define  FMC_PATT2_ATTHIZ2                  0xFF000000U        /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
-#define  FMC_PATT2_ATTHIZ2_0                0x01000000U        /*!<Bit 0 */
-#define  FMC_PATT2_ATTHIZ2_1                0x02000000U        /*!<Bit 1 */
-#define  FMC_PATT2_ATTHIZ2_2                0x04000000U        /*!<Bit 2 */
-#define  FMC_PATT2_ATTHIZ2_3                0x08000000U        /*!<Bit 3 */
-#define  FMC_PATT2_ATTHIZ2_4                0x10000000U        /*!<Bit 4 */
-#define  FMC_PATT2_ATTHIZ2_5                0x20000000U        /*!<Bit 5 */
-#define  FMC_PATT2_ATTHIZ2_6                0x40000000U        /*!<Bit 6 */
-#define  FMC_PATT2_ATTHIZ2_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_PATT3 register  ******************/
-#define  FMC_PATT3_ATTSET3                  0x000000FFU        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
-#define  FMC_PATT3_ATTSET3_0                0x00000001U        /*!<Bit 0 */
-#define  FMC_PATT3_ATTSET3_1                0x00000002U        /*!<Bit 1 */
-#define  FMC_PATT3_ATTSET3_2                0x00000004U        /*!<Bit 2 */
-#define  FMC_PATT3_ATTSET3_3                0x00000008U        /*!<Bit 3 */
-#define  FMC_PATT3_ATTSET3_4                0x00000010U        /*!<Bit 4 */
-#define  FMC_PATT3_ATTSET3_5                0x00000020U        /*!<Bit 5 */
-#define  FMC_PATT3_ATTSET3_6                0x00000040U        /*!<Bit 6 */
-#define  FMC_PATT3_ATTSET3_7                0x00000080U        /*!<Bit 7 */
-
-#define  FMC_PATT3_ATTWAIT3                 0x0000FF00U        /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
-#define  FMC_PATT3_ATTWAIT3_0               0x00000100U        /*!<Bit 0 */
-#define  FMC_PATT3_ATTWAIT3_1               0x00000200U        /*!<Bit 1 */
-#define  FMC_PATT3_ATTWAIT3_2               0x00000400U        /*!<Bit 2 */
-#define  FMC_PATT3_ATTWAIT3_3               0x00000800U        /*!<Bit 3 */
-#define  FMC_PATT3_ATTWAIT3_4               0x00001000U        /*!<Bit 4 */
-#define  FMC_PATT3_ATTWAIT3_5               0x00002000U        /*!<Bit 5 */
-#define  FMC_PATT3_ATTWAIT3_6               0x00004000U        /*!<Bit 6 */
-#define  FMC_PATT3_ATTWAIT3_7               0x00008000U        /*!<Bit 7 */
-
-#define  FMC_PATT3_ATTHOLD3                 0x00FF0000U        /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
-#define  FMC_PATT3_ATTHOLD3_0               0x00010000U        /*!<Bit 0 */
-#define  FMC_PATT3_ATTHOLD3_1               0x00020000U        /*!<Bit 1 */
-#define  FMC_PATT3_ATTHOLD3_2               0x00040000U        /*!<Bit 2 */
-#define  FMC_PATT3_ATTHOLD3_3               0x00080000U        /*!<Bit 3 */
-#define  FMC_PATT3_ATTHOLD3_4               0x00100000U        /*!<Bit 4 */
-#define  FMC_PATT3_ATTHOLD3_5               0x00200000U        /*!<Bit 5 */
-#define  FMC_PATT3_ATTHOLD3_6               0x00400000U        /*!<Bit 6 */
-#define  FMC_PATT3_ATTHOLD3_7               0x00800000U        /*!<Bit 7 */
-
-#define  FMC_PATT3_ATTHIZ3                  0xFF000000U        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
-#define  FMC_PATT3_ATTHIZ3_0                0x01000000U        /*!<Bit 0 */
-#define  FMC_PATT3_ATTHIZ3_1                0x02000000U        /*!<Bit 1 */
-#define  FMC_PATT3_ATTHIZ3_2                0x04000000U        /*!<Bit 2 */
-#define  FMC_PATT3_ATTHIZ3_3                0x08000000U        /*!<Bit 3 */
-#define  FMC_PATT3_ATTHIZ3_4                0x10000000U        /*!<Bit 4 */
-#define  FMC_PATT3_ATTHIZ3_5                0x20000000U        /*!<Bit 5 */
-#define  FMC_PATT3_ATTHIZ3_6                0x40000000U        /*!<Bit 6 */
-#define  FMC_PATT3_ATTHIZ3_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_PATT4 register  ******************/
-#define  FMC_PATT4_ATTSET4                  0x000000FFU        /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
-#define  FMC_PATT4_ATTSET4_0                0x00000001U        /*!<Bit 0 */
-#define  FMC_PATT4_ATTSET4_1                0x00000002U        /*!<Bit 1 */
-#define  FMC_PATT4_ATTSET4_2                0x00000004U        /*!<Bit 2 */
-#define  FMC_PATT4_ATTSET4_3                0x00000008U        /*!<Bit 3 */
-#define  FMC_PATT4_ATTSET4_4                0x00000010U        /*!<Bit 4 */
-#define  FMC_PATT4_ATTSET4_5                0x00000020U        /*!<Bit 5 */
-#define  FMC_PATT4_ATTSET4_6                0x00000040U        /*!<Bit 6 */
-#define  FMC_PATT4_ATTSET4_7                0x00000080U        /*!<Bit 7 */
-
-#define  FMC_PATT4_ATTWAIT4                 0x0000FF00U        /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
-#define  FMC_PATT4_ATTWAIT4_0               0x00000100U        /*!<Bit 0 */
-#define  FMC_PATT4_ATTWAIT4_1               0x00000200U        /*!<Bit 1 */
-#define  FMC_PATT4_ATTWAIT4_2               0x00000400U        /*!<Bit 2 */
-#define  FMC_PATT4_ATTWAIT4_3               0x00000800U        /*!<Bit 3 */
-#define  FMC_PATT4_ATTWAIT4_4               0x00001000U        /*!<Bit 4 */
-#define  FMC_PATT4_ATTWAIT4_5               0x00002000U        /*!<Bit 5 */
-#define  FMC_PATT4_ATTWAIT4_6               0x00004000U        /*!<Bit 6 */
-#define  FMC_PATT4_ATTWAIT4_7               0x00008000U        /*!<Bit 7 */
-
-#define  FMC_PATT4_ATTHOLD4                 0x00FF0000U        /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
-#define  FMC_PATT4_ATTHOLD4_0               0x00010000U        /*!<Bit 0 */
-#define  FMC_PATT4_ATTHOLD4_1               0x00020000U        /*!<Bit 1 */
-#define  FMC_PATT4_ATTHOLD4_2               0x00040000U        /*!<Bit 2 */
-#define  FMC_PATT4_ATTHOLD4_3               0x00080000U        /*!<Bit 3 */
-#define  FMC_PATT4_ATTHOLD4_4               0x00100000U        /*!<Bit 4 */
-#define  FMC_PATT4_ATTHOLD4_5               0x00200000U        /*!<Bit 5 */
-#define  FMC_PATT4_ATTHOLD4_6               0x00400000U        /*!<Bit 6 */
-#define  FMC_PATT4_ATTHOLD4_7               0x00800000U        /*!<Bit 7 */
-
-#define  FMC_PATT4_ATTHIZ4                  0xFF000000U        /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
-#define  FMC_PATT4_ATTHIZ4_0                0x01000000U        /*!<Bit 0 */
-#define  FMC_PATT4_ATTHIZ4_1                0x02000000U        /*!<Bit 1 */
-#define  FMC_PATT4_ATTHIZ4_2                0x04000000U        /*!<Bit 2 */
-#define  FMC_PATT4_ATTHIZ4_3                0x08000000U        /*!<Bit 3 */
-#define  FMC_PATT4_ATTHIZ4_4                0x10000000U        /*!<Bit 4 */
-#define  FMC_PATT4_ATTHIZ4_5                0x20000000U        /*!<Bit 5 */
-#define  FMC_PATT4_ATTHIZ4_6                0x40000000U        /*!<Bit 6 */
-#define  FMC_PATT4_ATTHIZ4_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_PIO4 register  *******************/
-#define  FMC_PIO4_IOSET4                    0x000000FFU        /*!<IOSET4[7:0] bits (I/O 4 setup time) */
-#define  FMC_PIO4_IOSET4_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_PIO4_IOSET4_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_PIO4_IOSET4_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_PIO4_IOSET4_3                  0x00000008U        /*!<Bit 3 */
-#define  FMC_PIO4_IOSET4_4                  0x00000010U        /*!<Bit 4 */
-#define  FMC_PIO4_IOSET4_5                  0x00000020U        /*!<Bit 5 */
-#define  FMC_PIO4_IOSET4_6                  0x00000040U        /*!<Bit 6 */
-#define  FMC_PIO4_IOSET4_7                  0x00000080U        /*!<Bit 7 */
-
-#define  FMC_PIO4_IOWAIT4                   0x0000FF00U        /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
-#define  FMC_PIO4_IOWAIT4_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_PIO4_IOWAIT4_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_PIO4_IOWAIT4_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_PIO4_IOWAIT4_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_PIO4_IOWAIT4_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_PIO4_IOWAIT4_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_PIO4_IOWAIT4_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_PIO4_IOWAIT4_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FMC_PIO4_IOHOLD4                   0x00FF0000U        /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
-#define  FMC_PIO4_IOHOLD4_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_PIO4_IOHOLD4_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_PIO4_IOHOLD4_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_PIO4_IOHOLD4_3                 0x00080000U        /*!<Bit 3 */
-#define  FMC_PIO4_IOHOLD4_4                 0x00100000U        /*!<Bit 4 */
-#define  FMC_PIO4_IOHOLD4_5                 0x00200000U        /*!<Bit 5 */
-#define  FMC_PIO4_IOHOLD4_6                 0x00400000U        /*!<Bit 6 */
-#define  FMC_PIO4_IOHOLD4_7                 0x00800000U        /*!<Bit 7 */
-
-#define  FMC_PIO4_IOHIZ4                    0xFF000000U        /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
-#define  FMC_PIO4_IOHIZ4_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_PIO4_IOHIZ4_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_PIO4_IOHIZ4_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_PIO4_IOHIZ4_3                  0x08000000U        /*!<Bit 3 */
-#define  FMC_PIO4_IOHIZ4_4                  0x10000000U        /*!<Bit 4 */
-#define  FMC_PIO4_IOHIZ4_5                  0x20000000U        /*!<Bit 5 */
-#define  FMC_PIO4_IOHIZ4_6                  0x40000000U        /*!<Bit 6 */
-#define  FMC_PIO4_IOHIZ4_7                  0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_ECCR2 register  ******************/
-#define  FMC_ECCR2_ECC2                     0xFFFFFFFFU        /*!<ECC result */
-
-/******************  Bit definition for FMC_ECCR3 register  ******************/
-#define  FMC_ECCR3_ECC3                     0xFFFFFFFFU        /*!<ECC result */
-
-/******************  Bit definition for FMC_SDCR1 register  ******************/
-#define  FMC_SDCR1_NC                       0x00000003U        /*!<NC[1:0] bits (Number of column bits) */
-#define  FMC_SDCR1_NC_0                     0x00000001U        /*!<Bit 0 */
-#define  FMC_SDCR1_NC_1                     0x00000002U        /*!<Bit 1 */
-
-#define  FMC_SDCR1_NR                       0x0000000CU        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR1_NR_0                     0x00000004U        /*!<Bit 0 */
-#define  FMC_SDCR1_NR_1                     0x00000008U        /*!<Bit 1 */
-
-#define  FMC_SDCR1_MWID                     0x00000030U        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR1_MWID_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDCR1_MWID_1                   0x00000020U        /*!<Bit 1 */
-
-#define  FMC_SDCR1_NB                       0x00000040U        /*!<Number of internal bank */
-
-#define  FMC_SDCR1_CAS                      0x00000180U        /*!<CAS[1:0] bits (CAS latency) */
-#define  FMC_SDCR1_CAS_0                    0x00000080U        /*!<Bit 0 */
-#define  FMC_SDCR1_CAS_1                    0x00000100U        /*!<Bit 1 */
-
-#define  FMC_SDCR1_WP                       0x00000200U        /*!<Write protection */
-
-#define  FMC_SDCR1_SDCLK                    0x00000C00U        /*!<SDRAM clock configuration */
-#define  FMC_SDCR1_SDCLK_0                  0x00000400U        /*!<Bit 0 */
-#define  FMC_SDCR1_SDCLK_1                  0x00000800U        /*!<Bit 1 */
-
-#define  FMC_SDCR1_RBURST                   0x00001000U        /*!<Read burst */
-
-#define  FMC_SDCR1_RPIPE                    0x00006000U        /*!<Write protection */
-#define  FMC_SDCR1_RPIPE_0                  0x00002000U        /*!<Bit 0 */
-#define  FMC_SDCR1_RPIPE_1                  0x00004000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_SDCR2 register  ******************/
-#define  FMC_SDCR2_NC                       0x00000003U        /*!<NC[1:0] bits (Number of column bits) */
-#define  FMC_SDCR2_NC_0                     0x00000001U        /*!<Bit 0 */
-#define  FMC_SDCR2_NC_1                     0x00000002U        /*!<Bit 1 */
-
-#define  FMC_SDCR2_NR                       0x0000000CU        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR2_NR_0                     0x00000004U        /*!<Bit 0 */
-#define  FMC_SDCR2_NR_1                     0x00000008U        /*!<Bit 1 */
-
-#define  FMC_SDCR2_MWID                     0x00000030U        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR2_MWID_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDCR2_MWID_1                   0x00000020U        /*!<Bit 1 */
-
-#define  FMC_SDCR2_NB                       0x00000040U        /*!<Number of internal bank */
-
-#define  FMC_SDCR2_CAS                      0x00000180U        /*!<CAS[1:0] bits (CAS latency) */
-#define  FMC_SDCR2_CAS_0                    0x00000080U        /*!<Bit 0 */
-#define  FMC_SDCR2_CAS_1                    0x00000100U        /*!<Bit 1 */
-
-#define  FMC_SDCR2_WP                       0x00000200U        /*!<Write protection */
-
-#define  FMC_SDCR2_SDCLK                    0x00000C00U        /*!<SDCLK[1:0] (SDRAM clock configuration) */
-#define  FMC_SDCR2_SDCLK_0                  0x00000400U        /*!<Bit 0 */
-#define  FMC_SDCR2_SDCLK_1                  0x00000800U        /*!<Bit 1 */
-
-#define  FMC_SDCR2_RBURST                   0x00001000U        /*!<Read burst */
-
-#define  FMC_SDCR2_RPIPE                    0x00006000U        /*!<RPIPE[1:0](Read pipe) */
-#define  FMC_SDCR2_RPIPE_0                  0x00002000U        /*!<Bit 0 */
-#define  FMC_SDCR2_RPIPE_1                  0x00004000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_SDTR1 register  ******************/
-#define  FMC_SDTR1_TMRD                     0x0000000FU        /*!<TMRD[3:0] bits (Load mode register to active) */
-#define  FMC_SDTR1_TMRD_0                   0x00000001U        /*!<Bit 0 */
-#define  FMC_SDTR1_TMRD_1                   0x00000002U        /*!<Bit 1 */
-#define  FMC_SDTR1_TMRD_2                   0x00000004U        /*!<Bit 2 */
-#define  FMC_SDTR1_TMRD_3                   0x00000008U        /*!<Bit 3 */
-                                            
-#define  FMC_SDTR1_TXSR                     0x000000F0U        /*!<TXSR[3:0] bits (Exit self refresh) */
-#define  FMC_SDTR1_TXSR_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDTR1_TXSR_1                   0x00000020U        /*!<Bit 1 */
-#define  FMC_SDTR1_TXSR_2                   0x00000040U        /*!<Bit 2 */
-#define  FMC_SDTR1_TXSR_3                   0x00000080U        /*!<Bit 3 */
-
-#define  FMC_SDTR1_TRAS                     0x00000F00U        /*!<TRAS[3:0] bits (Self refresh time) */
-#define  FMC_SDTR1_TRAS_0                   0x00000100U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRAS_1                   0x00000200U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRAS_2                   0x00000400U        /*!<Bit 2 */
-#define  FMC_SDTR1_TRAS_3                   0x00000800U        /*!<Bit 3 */
-
-#define  FMC_SDTR1_TRC                      0x0000F000U        /*!<TRC[2:0] bits (Row cycle delay) */
-#define  FMC_SDTR1_TRC_0                    0x00001000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRC_1                    0x00002000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRC_2                    0x00004000U        /*!<Bit 2 */
-
-#define  FMC_SDTR1_TWR                      0x000F0000U        /*!<TRC[2:0] bits (Write recovery delay) */
-#define  FMC_SDTR1_TWR_0                    0x00010000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TWR_1                    0x00020000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TWR_2                    0x00040000U        /*!<Bit 2 */
-
-#define  FMC_SDTR1_TRP                      0x00F00000U        /*!<TRP[2:0] bits (Row precharge delay) */
-#define  FMC_SDTR1_TRP_0                    0x00100000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRP_1                    0x00200000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRP_2                    0x00400000U        /*!<Bit 2 */
-
-#define  FMC_SDTR1_TRCD                     0x0F000000U        /*!<TRP[2:0] bits (Row to column delay) */
-#define  FMC_SDTR1_TRCD_0                   0x01000000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRCD_1                   0x02000000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRCD_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for FMC_SDTR2 register  ******************/
-#define  FMC_SDTR2_TMRD                     0x0000000FU        /*!<TMRD[3:0] bits (Load mode register to active) */
-#define  FMC_SDTR2_TMRD_0                   0x00000001U        /*!<Bit 0 */
-#define  FMC_SDTR2_TMRD_1                   0x00000002U        /*!<Bit 1 */
-#define  FMC_SDTR2_TMRD_2                   0x00000004U        /*!<Bit 2 */
-#define  FMC_SDTR2_TMRD_3                   0x00000008U        /*!<Bit 3 */
-                                            
-#define  FMC_SDTR2_TXSR                     0x000000F0U        /*!<TXSR[3:0] bits (Exit self refresh) */
-#define  FMC_SDTR2_TXSR_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDTR2_TXSR_1                   0x00000020U        /*!<Bit 1 */
-#define  FMC_SDTR2_TXSR_2                   0x00000040U        /*!<Bit 2 */
-#define  FMC_SDTR2_TXSR_3                   0x00000080U        /*!<Bit 3 */
-
-#define  FMC_SDTR2_TRAS                     0x00000F00U        /*!<TRAS[3:0] bits (Self refresh time) */
-#define  FMC_SDTR2_TRAS_0                   0x00000100U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRAS_1                   0x00000200U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRAS_2                   0x00000400U        /*!<Bit 2 */
-#define  FMC_SDTR2_TRAS_3                   0x00000800U        /*!<Bit 3 */
-
-#define  FMC_SDTR2_TRC                      0x0000F000U        /*!<TRC[2:0] bits (Row cycle delay) */
-#define  FMC_SDTR2_TRC_0                    0x00001000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRC_1                    0x00002000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRC_2                    0x00004000U        /*!<Bit 2 */
-
-#define  FMC_SDTR2_TWR                      0x000F0000U        /*!<TRC[2:0] bits (Write recovery delay) */
-#define  FMC_SDTR2_TWR_0                    0x00010000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TWR_1                    0x00020000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TWR_2                    0x00040000U        /*!<Bit 2 */
-
-#define  FMC_SDTR2_TRP                      0x00F00000U        /*!<TRP[2:0] bits (Row precharge delay) */
-#define  FMC_SDTR2_TRP_0                    0x00100000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRP_1                    0x00200000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRP_2                    0x00400000U        /*!<Bit 2 */
-
-#define  FMC_SDTR2_TRCD                     0x0F000000U        /*!<TRP[2:0] bits (Row to column delay) */
-#define  FMC_SDTR2_TRCD_0                   0x01000000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRCD_1                   0x02000000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRCD_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for FMC_SDCMR register  ******************/
-#define  FMC_SDCMR_MODE                     0x00000007U        /*!<MODE[2:0] bits (Command mode) */
-#define  FMC_SDCMR_MODE_0                   0x00000001U        /*!<Bit 0 */
-#define  FMC_SDCMR_MODE_1                   0x00000002U        /*!<Bit 1 */
-#define  FMC_SDCMR_MODE_2                   0x00000004U        /*!<Bit 2 */
-                                            
-#define  FMC_SDCMR_CTB2                     0x00000008U        /*!<Command target 2 */
-
-#define  FMC_SDCMR_CTB1                     0x00000010U        /*!<Command target 1 */
-
-#define  FMC_SDCMR_NRFS                     0x000001E0U        /*!<NRFS[3:0] bits (Number of auto-refresh) */
-#define  FMC_SDCMR_NRFS_0                   0x00000020U        /*!<Bit 0 */
-#define  FMC_SDCMR_NRFS_1                   0x00000040U        /*!<Bit 1 */
-#define  FMC_SDCMR_NRFS_2                   0x00000080U        /*!<Bit 2 */
-#define  FMC_SDCMR_NRFS_3                   0x00000100U        /*!<Bit 3 */
-
-#define  FMC_SDCMR_MRD                      0x003FFE00U        /*!<MRD[12:0] bits (Mode register definition) */
-
-/******************  Bit definition for FMC_SDRTR register  ******************/
-#define  FMC_SDRTR_CRE                      0x00000001U        /*!<Clear refresh error flag */
-
-#define  FMC_SDRTR_COUNT                    0x00003FFEU        /*!<COUNT[12:0] bits (Refresh timer count) */
-
-#define  FMC_SDRTR_REIE                     0x00004000U        /*!<RES interupt enable */
-
-/******************  Bit definition for FMC_SDSR register  ******************/
-#define  FMC_SDSR_RE                        0x00000001U        /*!<Refresh error flag */
-
-#define  FMC_SDSR_MODES1                    0x00000006U        /*!<MODES1[1:0]bits (Status mode for bank 1) */
-#define  FMC_SDSR_MODES1_0                  0x00000002U        /*!<Bit 0 */
-#define  FMC_SDSR_MODES1_1                  0x00000004U        /*!<Bit 1 */
-
-#define  FMC_SDSR_MODES2                    0x00000018U        /*!<MODES2[1:0]bits (Status mode for bank 2) */
-#define  FMC_SDSR_MODES2_0                  0x00000008U        /*!<Bit 0 */
-#define  FMC_SDSR_MODES2_1                  0x00000010U        /*!<Bit 1 */
-#define  FMC_SDSR_BUSY                      0x00000020U        /*!<Busy status */
-
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    0x00000003U
-#define GPIO_MODER_MODER0_0                  0x00000001U
-#define GPIO_MODER_MODER0_1                  0x00000002U
-
-#define GPIO_MODER_MODER1                    0x0000000CU
-#define GPIO_MODER_MODER1_0                  0x00000004U
-#define GPIO_MODER_MODER1_1                  0x00000008U
-
-#define GPIO_MODER_MODER2                    0x00000030U
-#define GPIO_MODER_MODER2_0                  0x00000010U
-#define GPIO_MODER_MODER2_1                  0x00000020U
-
-#define GPIO_MODER_MODER3                    0x000000C0U
-#define GPIO_MODER_MODER3_0                  0x00000040U
-#define GPIO_MODER_MODER3_1                  0x00000080U
-
-#define GPIO_MODER_MODER4                    0x00000300U
-#define GPIO_MODER_MODER4_0                  0x00000100U
-#define GPIO_MODER_MODER4_1                  0x00000200U
-
-#define GPIO_MODER_MODER5                    0x00000C00U
-#define GPIO_MODER_MODER5_0                  0x00000400U
-#define GPIO_MODER_MODER5_1                  0x00000800U
-
-#define GPIO_MODER_MODER6                    0x00003000U
-#define GPIO_MODER_MODER6_0                  0x00001000U
-#define GPIO_MODER_MODER6_1                  0x00002000U
-
-#define GPIO_MODER_MODER7                    0x0000C000U
-#define GPIO_MODER_MODER7_0                  0x00004000U
-#define GPIO_MODER_MODER7_1                  0x00008000U
-
-#define GPIO_MODER_MODER8                    0x00030000U
-#define GPIO_MODER_MODER8_0                  0x00010000U
-#define GPIO_MODER_MODER8_1                  0x00020000U
-
-#define GPIO_MODER_MODER9                    0x000C0000U
-#define GPIO_MODER_MODER9_0                  0x00040000U
-#define GPIO_MODER_MODER9_1                  0x00080000U
-
-#define GPIO_MODER_MODER10                   0x00300000U
-#define GPIO_MODER_MODER10_0                 0x00100000U
-#define GPIO_MODER_MODER10_1                 0x00200000U
-
-#define GPIO_MODER_MODER11                   0x00C00000U
-#define GPIO_MODER_MODER11_0                 0x00400000U
-#define GPIO_MODER_MODER11_1                 0x00800000U
-
-#define GPIO_MODER_MODER12                   0x03000000U
-#define GPIO_MODER_MODER12_0                 0x01000000U
-#define GPIO_MODER_MODER12_1                 0x02000000U
-
-#define GPIO_MODER_MODER13                   0x0C000000U
-#define GPIO_MODER_MODER13_0                 0x04000000U
-#define GPIO_MODER_MODER13_1                 0x08000000U
-
-#define GPIO_MODER_MODER14                   0x30000000U
-#define GPIO_MODER_MODER14_0                 0x10000000U
-#define GPIO_MODER_MODER14_1                 0x20000000U
-
-#define GPIO_MODER_MODER15                   0xC0000000U
-#define GPIO_MODER_MODER15_0                 0x40000000U
-#define GPIO_MODER_MODER15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     0x00000001U
-#define GPIO_OTYPER_OT_1                     0x00000002U
-#define GPIO_OTYPER_OT_2                     0x00000004U
-#define GPIO_OTYPER_OT_3                     0x00000008U
-#define GPIO_OTYPER_OT_4                     0x00000010U
-#define GPIO_OTYPER_OT_5                     0x00000020U
-#define GPIO_OTYPER_OT_6                     0x00000040U
-#define GPIO_OTYPER_OT_7                     0x00000080U
-#define GPIO_OTYPER_OT_8                     0x00000100U
-#define GPIO_OTYPER_OT_9                     0x00000200U
-#define GPIO_OTYPER_OT_10                    0x00000400U
-#define GPIO_OTYPER_OT_11                    0x00000800U
-#define GPIO_OTYPER_OT_12                    0x00001000U
-#define GPIO_OTYPER_OT_13                    0x00002000U
-#define GPIO_OTYPER_OT_14                    0x00004000U
-#define GPIO_OTYPER_OT_15                    0x00008000U
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
-#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
-#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
-
-#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
-#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
-#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
-
-#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
-#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
-#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
-
-#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
-#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
-#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
-
-#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
-#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
-#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
-
-#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
-#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
-#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
-
-#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
-#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
-#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
-
-#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
-#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
-#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
-
-#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
-#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
-#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
-
-#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
-#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
-#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
-
-#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
-#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
-#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
-
-#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
-#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
-#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
-
-#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
-#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
-#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
-
-#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
-#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
-#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
-
-#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
-#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
-#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
-
-#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
-#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
-#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    0x00000003U
-#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
-#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
-
-#define GPIO_PUPDR_PUPDR1                    0x0000000CU
-#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
-#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
-
-#define GPIO_PUPDR_PUPDR2                    0x00000030U
-#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
-#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
-
-#define GPIO_PUPDR_PUPDR3                    0x000000C0U
-#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
-#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
-
-#define GPIO_PUPDR_PUPDR4                    0x00000300U
-#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
-#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
-
-#define GPIO_PUPDR_PUPDR5                    0x00000C00U
-#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
-#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
-
-#define GPIO_PUPDR_PUPDR6                    0x00003000U
-#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
-#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
-
-#define GPIO_PUPDR_PUPDR7                    0x0000C000U
-#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
-#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
-
-#define GPIO_PUPDR_PUPDR8                    0x00030000U
-#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
-#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
-
-#define GPIO_PUPDR_PUPDR9                    0x000C0000U
-#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
-#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
-
-#define GPIO_PUPDR_PUPDR10                   0x00300000U
-#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
-#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
-
-#define GPIO_PUPDR_PUPDR11                   0x00C00000U
-#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
-#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
-
-#define GPIO_PUPDR_PUPDR12                   0x03000000U
-#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
-#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
-
-#define GPIO_PUPDR_PUPDR13                   0x0C000000U
-#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
-#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
-
-#define GPIO_PUPDR_PUPDR14                   0x30000000U
-#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
-#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
-
-#define GPIO_PUPDR_PUPDR15                   0xC0000000U
-#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
-#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       0x00000001U
-#define GPIO_IDR_IDR_1                       0x00000002U
-#define GPIO_IDR_IDR_2                       0x00000004U
-#define GPIO_IDR_IDR_3                       0x00000008U
-#define GPIO_IDR_IDR_4                       0x00000010U
-#define GPIO_IDR_IDR_5                       0x00000020U
-#define GPIO_IDR_IDR_6                       0x00000040U
-#define GPIO_IDR_IDR_7                       0x00000080U
-#define GPIO_IDR_IDR_8                       0x00000100U
-#define GPIO_IDR_IDR_9                       0x00000200U
-#define GPIO_IDR_IDR_10                      0x00000400U
-#define GPIO_IDR_IDR_11                      0x00000800U
-#define GPIO_IDR_IDR_12                      0x00001000U
-#define GPIO_IDR_IDR_13                      0x00002000U
-#define GPIO_IDR_IDR_14                      0x00004000U
-#define GPIO_IDR_IDR_15                      0x00008000U
-/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
-#define GPIO_OTYPER_IDR_0                    GPIO_IDR_IDR_0
-#define GPIO_OTYPER_IDR_1                    GPIO_IDR_IDR_1
-#define GPIO_OTYPER_IDR_2                    GPIO_IDR_IDR_2
-#define GPIO_OTYPER_IDR_3                    GPIO_IDR_IDR_3
-#define GPIO_OTYPER_IDR_4                    GPIO_IDR_IDR_4
-#define GPIO_OTYPER_IDR_5                    GPIO_IDR_IDR_5
-#define GPIO_OTYPER_IDR_6                    GPIO_IDR_IDR_6
-#define GPIO_OTYPER_IDR_7                    GPIO_IDR_IDR_7
-#define GPIO_OTYPER_IDR_8                    GPIO_IDR_IDR_8
-#define GPIO_OTYPER_IDR_9                    GPIO_IDR_IDR_9
-#define GPIO_OTYPER_IDR_10                   GPIO_IDR_IDR_10
-#define GPIO_OTYPER_IDR_11                   GPIO_IDR_IDR_11
-#define GPIO_OTYPER_IDR_12                   GPIO_IDR_IDR_12
-#define GPIO_OTYPER_IDR_13                   GPIO_IDR_IDR_13
-#define GPIO_OTYPER_IDR_14                   GPIO_IDR_IDR_14
-#define GPIO_OTYPER_IDR_15                   GPIO_IDR_IDR_15
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       0x00000001U
-#define GPIO_ODR_ODR_1                       0x00000002U
-#define GPIO_ODR_ODR_2                       0x00000004U
-#define GPIO_ODR_ODR_3                       0x00000008U
-#define GPIO_ODR_ODR_4                       0x00000010U
-#define GPIO_ODR_ODR_5                       0x00000020U
-#define GPIO_ODR_ODR_6                       0x00000040U
-#define GPIO_ODR_ODR_7                       0x00000080U
-#define GPIO_ODR_ODR_8                       0x00000100U
-#define GPIO_ODR_ODR_9                       0x00000200U
-#define GPIO_ODR_ODR_10                      0x00000400U
-#define GPIO_ODR_ODR_11                      0x00000800U
-#define GPIO_ODR_ODR_12                      0x00001000U
-#define GPIO_ODR_ODR_13                      0x00002000U
-#define GPIO_ODR_ODR_14                      0x00004000U
-#define GPIO_ODR_ODR_15                      0x00008000U
-/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
-#define GPIO_OTYPER_ODR_0                    GPIO_ODR_ODR_0
-#define GPIO_OTYPER_ODR_1                    GPIO_ODR_ODR_1
-#define GPIO_OTYPER_ODR_2                    GPIO_ODR_ODR_2
-#define GPIO_OTYPER_ODR_3                    GPIO_ODR_ODR_3
-#define GPIO_OTYPER_ODR_4                    GPIO_ODR_ODR_4
-#define GPIO_OTYPER_ODR_5                    GPIO_ODR_ODR_5
-#define GPIO_OTYPER_ODR_6                    GPIO_ODR_ODR_6
-#define GPIO_OTYPER_ODR_7                    GPIO_ODR_ODR_7
-#define GPIO_OTYPER_ODR_8                    GPIO_ODR_ODR_8
-#define GPIO_OTYPER_ODR_9                    GPIO_ODR_ODR_9
-#define GPIO_OTYPER_ODR_10                   GPIO_ODR_ODR_10
-#define GPIO_OTYPER_ODR_11                   GPIO_ODR_ODR_11
-#define GPIO_OTYPER_ODR_12                   GPIO_ODR_ODR_12
-#define GPIO_OTYPER_ODR_13                   GPIO_ODR_ODR_13
-#define GPIO_OTYPER_ODR_14                   GPIO_ODR_ODR_14
-#define GPIO_OTYPER_ODR_15                   GPIO_ODR_ODR_15
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       0x00000001U
-#define GPIO_BSRR_BS_1                       0x00000002U
-#define GPIO_BSRR_BS_2                       0x00000004U
-#define GPIO_BSRR_BS_3                       0x00000008U
-#define GPIO_BSRR_BS_4                       0x00000010U
-#define GPIO_BSRR_BS_5                       0x00000020U
-#define GPIO_BSRR_BS_6                       0x00000040U
-#define GPIO_BSRR_BS_7                       0x00000080U
-#define GPIO_BSRR_BS_8                       0x00000100U
-#define GPIO_BSRR_BS_9                       0x00000200U
-#define GPIO_BSRR_BS_10                      0x00000400U
-#define GPIO_BSRR_BS_11                      0x00000800U
-#define GPIO_BSRR_BS_12                      0x00001000U
-#define GPIO_BSRR_BS_13                      0x00002000U
-#define GPIO_BSRR_BS_14                      0x00004000U
-#define GPIO_BSRR_BS_15                      0x00008000U
-#define GPIO_BSRR_BR_0                       0x00010000U
-#define GPIO_BSRR_BR_1                       0x00020000U
-#define GPIO_BSRR_BR_2                       0x00040000U
-#define GPIO_BSRR_BR_3                       0x00080000U
-#define GPIO_BSRR_BR_4                       0x00100000U
-#define GPIO_BSRR_BR_5                       0x00200000U
-#define GPIO_BSRR_BR_6                       0x00400000U
-#define GPIO_BSRR_BR_7                       0x00800000U
-#define GPIO_BSRR_BR_8                       0x01000000U
-#define GPIO_BSRR_BR_9                       0x02000000U
-#define GPIO_BSRR_BR_10                      0x04000000U
-#define GPIO_BSRR_BR_11                      0x08000000U
-#define GPIO_BSRR_BR_12                      0x10000000U
-#define GPIO_BSRR_BR_13                      0x20000000U
-#define GPIO_BSRR_BR_14                      0x40000000U
-#define GPIO_BSRR_BR_15                      0x80000000U
-
-/****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0                       0x00000001U
-#define GPIO_LCKR_LCK1                       0x00000002U
-#define GPIO_LCKR_LCK2                       0x00000004U
-#define GPIO_LCKR_LCK3                       0x00000008U
-#define GPIO_LCKR_LCK4                       0x00000010U
-#define GPIO_LCKR_LCK5                       0x00000020U
-#define GPIO_LCKR_LCK6                       0x00000040U
-#define GPIO_LCKR_LCK7                       0x00000080U
-#define GPIO_LCKR_LCK8                       0x00000100U
-#define GPIO_LCKR_LCK9                       0x00000200U
-#define GPIO_LCKR_LCK10                      0x00000400U
-#define GPIO_LCKR_LCK11                      0x00000800U
-#define GPIO_LCKR_LCK12                      0x00001000U
-#define GPIO_LCKR_LCK13                      0x00002000U
-#define GPIO_LCKR_LCK14                      0x00004000U
-#define GPIO_LCKR_LCK15                      0x00008000U
-#define GPIO_LCKR_LCKK                       0x00010000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    HASH                                    */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for HASH_CR register  ********************/
-#define HASH_CR_INIT                         0x00000004U
-#define HASH_CR_DMAE                         0x00000008U
-#define HASH_CR_DATATYPE                     0x00000030U
-#define HASH_CR_DATATYPE_0                   0x00000010U
-#define HASH_CR_DATATYPE_1                   0x00000020U
-#define HASH_CR_MODE                         0x00000040U
-#define HASH_CR_ALGO                         0x00040080U
-#define HASH_CR_ALGO_0                       0x00000080U
-#define HASH_CR_ALGO_1                       0x00040000U
-#define HASH_CR_NBW                          0x00000F00U
-#define HASH_CR_NBW_0                        0x00000100U
-#define HASH_CR_NBW_1                        0x00000200U
-#define HASH_CR_NBW_2                        0x00000400U
-#define HASH_CR_NBW_3                        0x00000800U
-#define HASH_CR_DINNE                        0x00001000U
-#define HASH_CR_MDMAT                        0x00002000U
-#define HASH_CR_LKEY                         0x00010000U
-
-/******************  Bits definition for HASH_STR register  *******************/
-#define HASH_STR_NBLW                        0x0000001FU
-#define HASH_STR_NBLW_0                      0x00000001U
-#define HASH_STR_NBLW_1                      0x00000002U
-#define HASH_STR_NBLW_2                      0x00000004U
-#define HASH_STR_NBLW_3                      0x00000008U
-#define HASH_STR_NBLW_4                      0x00000010U
-#define HASH_STR_DCAL                        0x00000100U
-/* Aliases for HASH_STR register */
-#define HASH_STR_NBW                         HASH_STR_NBLW
-#define HASH_STR_NBW_0                       HASH_STR_NBLW_0
-#define HASH_STR_NBW_1                       HASH_STR_NBLW_1
-#define HASH_STR_NBW_2                       HASH_STR_NBLW_2
-#define HASH_STR_NBW_3                       HASH_STR_NBLW_3
-#define HASH_STR_NBW_4                       HASH_STR_NBLW_4
-
-/******************  Bits definition for HASH_IMR register  *******************/
-#define HASH_IMR_DINIE                       0x00000001U
-#define HASH_IMR_DCIE                        0x00000002U
-/* Aliases for HASH_IMR register */
-#define HASH_IMR_DINIM                       HASH_IMR_DINIE
-#define HASH_IMR_DCIM                        HASH_IMR_DCIE
-
-/******************  Bits definition for HASH_SR register  ********************/
-#define HASH_SR_DINIS                        0x00000001U
-#define HASH_SR_DCIS                         0x00000002U
-#define HASH_SR_DMAS                         0x00000004U
-#define HASH_SR_BUSY                         0x00000008U
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Inter-integrated Circuit Interface                    */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          0x00000001U     /*!<Peripheral Enable                             */
-#define  I2C_CR1_SMBUS                       0x00000002U     /*!<SMBus Mode                                    */
-#define  I2C_CR1_SMBTYPE                     0x00000008U     /*!<SMBus Type                                    */
-#define  I2C_CR1_ENARP                       0x00000010U     /*!<ARP Enable                                    */
-#define  I2C_CR1_ENPEC                       0x00000020U     /*!<PEC Enable                                    */
-#define  I2C_CR1_ENGC                        0x00000040U     /*!<General Call Enable                           */
-#define  I2C_CR1_NOSTRETCH                   0x00000080U     /*!<Clock Stretching Disable (Slave mode)  */
-#define  I2C_CR1_START                       0x00000100U     /*!<Start Generation                              */
-#define  I2C_CR1_STOP                        0x00000200U     /*!<Stop Generation                               */
-#define  I2C_CR1_ACK                         0x00000400U     /*!<Acknowledge Enable                            */
-#define  I2C_CR1_POS                         0x00000800U     /*!<Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         0x00001000U     /*!<Packet Error Checking                         */
-#define  I2C_CR1_ALERT                       0x00002000U     /*!<SMBus Alert                                   */
-#define  I2C_CR1_SWRST                       0x00008000U     /*!<Software Reset                                */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        0x0000003FU     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
-#define  I2C_CR2_FREQ_0                      0x00000001U     /*!<Bit 0 */
-#define  I2C_CR2_FREQ_1                      0x00000002U     /*!<Bit 1 */
-#define  I2C_CR2_FREQ_2                      0x00000004U     /*!<Bit 2 */
-#define  I2C_CR2_FREQ_3                      0x00000008U     /*!<Bit 3 */
-#define  I2C_CR2_FREQ_4                      0x00000010U     /*!<Bit 4 */
-#define  I2C_CR2_FREQ_5                      0x00000020U     /*!<Bit 5 */
-
-#define  I2C_CR2_ITERREN                     0x00000100U     /*!<Error Interrupt Enable  */
-#define  I2C_CR2_ITEVTEN                     0x00000200U     /*!<Event Interrupt Enable  */
-#define  I2C_CR2_ITBUFEN                     0x00000400U     /*!<Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       0x00000800U     /*!<DMA Requests Enable     */
-#define  I2C_CR2_LAST                        0x00001000U     /*!<DMA Last Transfer       */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     0x000000FEU     /*!<Interface Address */
-#define  I2C_OAR1_ADD8_9                     0x00000300U     /*!<Interface Address */
-
-#define  I2C_OAR1_ADD0                       0x00000001U     /*!<Bit 0 */
-#define  I2C_OAR1_ADD1                       0x00000002U     /*!<Bit 1 */
-#define  I2C_OAR1_ADD2                       0x00000004U     /*!<Bit 2 */
-#define  I2C_OAR1_ADD3                       0x00000008U     /*!<Bit 3 */
-#define  I2C_OAR1_ADD4                       0x00000010U     /*!<Bit 4 */
-#define  I2C_OAR1_ADD5                       0x00000020U     /*!<Bit 5 */
-#define  I2C_OAR1_ADD6                       0x00000040U     /*!<Bit 6 */
-#define  I2C_OAR1_ADD7                       0x00000080U     /*!<Bit 7 */
-#define  I2C_OAR1_ADD8                       0x00000100U     /*!<Bit 8 */
-#define  I2C_OAR1_ADD9                       0x00000200U     /*!<Bit 9 */
-
-#define  I2C_OAR1_ADDMODE                    0x00008000U     /*!<Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     0x00000001U        /*!<Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       0x000000FEU        /*!<Interface address           */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           0x000000FFU        /*!<8-bit Data Register         */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          0x00000001U     /*!<Start Bit (Master mode)                  */
-#define  I2C_SR1_ADDR                        0x00000002U     /*!<Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         0x00000004U     /*!<Byte Transfer Finished                          */
-#define  I2C_SR1_ADD10                       0x00000008U     /*!<10-bit header sent (Master mode)         */
-#define  I2C_SR1_STOPF                       0x00000010U     /*!<Stop detection (Slave mode)              */
-#define  I2C_SR1_RXNE                        0x00000040U     /*!<Data Register not Empty (receivers)      */
-#define  I2C_SR1_TXE                         0x00000080U     /*!<Data Register Empty (transmitters)       */
-#define  I2C_SR1_BERR                        0x00000100U     /*!<Bus Error                                       */
-#define  I2C_SR1_ARLO                        0x00000200U     /*!<Arbitration Lost (master mode)           */
-#define  I2C_SR1_AF                          0x00000400U     /*!<Acknowledge Failure                             */
-#define  I2C_SR1_OVR                         0x00000800U     /*!<Overrun/Underrun                                */
-#define  I2C_SR1_PECERR                      0x00001000U     /*!<PEC Error in reception                          */
-#define  I2C_SR1_TIMEOUT                     0x00004000U     /*!<Timeout or Tlow Error                           */
-#define  I2C_SR1_SMBALERT                    0x00008000U     /*!<SMBus Alert                                     */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         0x00000001U     /*!<Master/Slave                              */
-#define  I2C_SR2_BUSY                        0x00000002U     /*!<Bus Busy                                  */
-#define  I2C_SR2_TRA                         0x00000004U     /*!<Transmitter/Receiver                      */
-#define  I2C_SR2_GENCALL                     0x00000010U     /*!<General Call Address (Slave mode)  */
-#define  I2C_SR2_SMBDEFAULT                  0x00000020U     /*!<SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     0x00000040U     /*!<SMBus Host Header (Slave mode)     */
-#define  I2C_SR2_DUALF                       0x00000080U     /*!<Dual Flag (Slave mode)             */
-#define  I2C_SR2_PEC                         0x0000FF00U     /*!<Packet Error Checking Register            */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         0x00000FFFU     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        0x00004000U     /*!<Fast Mode Duty Cycle                                       */
-#define  I2C_CCR_FS                          0x00008000U     /*!<I2C Master Mode Selection                                  */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     0x0000003FU     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************  Bit definition for I2C_FLTR register  *******************/
-#define  I2C_FLTR_DNF                        0x0000000FU     /*!<Digital Noise Filter */
-#define  I2C_FLTR_ANOFF                      0x00000010U     /*!<Analog Noise Filter OFF */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Independent WATCHDOG                             */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         0x01U               /*!<Watchdog prescaler value update      */
-#define  IWDG_SR_RVU                         0x02U               /*!<Watchdog counter reload value update */
-
-/******************************************************************************/
-/*                                                                            */
-/*                             Power Control                                  */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
-#define  PWR_CR_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
-#define  PWR_CR_CWUF                         0x00000004U     /*!< Clear Wakeup Flag                   */
-#define  PWR_CR_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
-#define  PWR_CR_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
-
-#define  PWR_CR_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        0x00000020U     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        0x00000040U     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        0x00000080U     /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
-#define  PWR_CR_DBP                          0x00000100U     /*!< Disable Backup Domain write protection                     */
-#define  PWR_CR_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                              */
-#define  PWR_CR_LPLVDS                       0x00000400U     /*!< Low-Power Regulator Low Voltage Scaling in Stop mode       */
-#define  PWR_CR_MRLVDS                       0x00000800U     /*!< Main regulator Low Voltage Scaling in Stop mode            */
-#define  PWR_CR_ADCDC1                       0x00002000U     /*!< Refer to AN4073 on how to use this bit */ 
-#define  PWR_CR_VOS                          0x0000C000U     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
-#define  PWR_CR_VOS_0                        0x00004000U     /*!< Bit 0 */
-#define  PWR_CR_VOS_1                        0x00008000U     /*!< Bit 1 */
-#define  PWR_CR_ODEN                         0x00010000U     /*!< Over Drive enable                   */
-#define  PWR_CR_ODSWEN                       0x00020000U     /*!< Over Drive switch enabled           */
-#define  PWR_CR_UDEN                         0x000C0000U     /*!< Under Drive enable in stop mode     */
-#define  PWR_CR_UDEN_0                       0x00040000U     /*!< Bit 0                               */
-#define  PWR_CR_UDEN_1                       0x00080000U     /*!< Bit 1                               */
-
-/* Legacy define */
-#define  PWR_CR_PMODE                        PWR_CR_VOS
-#define  PWR_CR_LPUDS                        PWR_CR_LPLVDS     /*!< Low-Power Regulator in deepsleep under-drive mode          */
-#define  PWR_CR_MRUDS                        PWR_CR_MRLVDS     /*!< Main regulator in deepsleep under-drive mode               */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         0x00000001U     /*!< Wakeup Flag                                      */
-#define  PWR_CSR_SBF                         0x00000002U     /*!< Standby Flag                                     */
-#define  PWR_CSR_PVDO                        0x00000004U     /*!< PVD Output                                       */
-#define  PWR_CSR_BRR                         0x00000008U     /*!< Backup regulator ready                           */
-#define  PWR_CSR_EWUP                        0x00000100U     /*!< Enable WKUP pin                                  */
-#define  PWR_CSR_BRE                         0x00000200U     /*!< Backup regulator enable                          */
-#define  PWR_CSR_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
-#define  PWR_CSR_ODRDY                       0x00010000U     /*!< Over Drive generator ready                       */
-#define  PWR_CSR_ODSWRDY                     0x00020000U     /*!< Over Drive Switch ready                          */
-#define  PWR_CSR_UDSWRDY                     0x000C0000U     /*!< Under Drive ready                                */
-
-/* Legacy define */
-#define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        0x00000001U
-#define  RCC_CR_HSIRDY                       0x00000002U
-
-#define  RCC_CR_HSITRIM                      0x000000F8U
-#define  RCC_CR_HSITRIM_0                    0x00000008U/*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    0x00000010U/*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    0x00000020U/*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    0x00000040U/*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    0x00000080U/*!<Bit 4 */
-
-#define  RCC_CR_HSICAL                       0x0000FF00U
-#define  RCC_CR_HSICAL_0                     0x00000100U/*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     0x00000200U/*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     0x00000400U/*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     0x00000800U/*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     0x00001000U/*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     0x00002000U/*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     0x00004000U/*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     0x00008000U/*!<Bit 7 */
-
-#define  RCC_CR_HSEON                        0x00010000U
-#define  RCC_CR_HSERDY                       0x00020000U
-#define  RCC_CR_HSEBYP                       0x00040000U
-#define  RCC_CR_CSSON                        0x00080000U
-#define  RCC_CR_PLLON                        0x01000000U
-#define  RCC_CR_PLLRDY                       0x02000000U
-#define  RCC_CR_PLLI2SON                     0x04000000U
-#define  RCC_CR_PLLI2SRDY                    0x08000000U
-#define  RCC_CR_PLLSAION                     0x10000000U
-#define  RCC_CR_PLLSAIRDY                    0x20000000U
-
-/********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    0x0000003FU
-#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
-#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
-#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
-#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
-#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
-#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
-
-#define  RCC_PLLCFGR_PLLN                     0x00007FC0U
-#define  RCC_PLLCFGR_PLLN_0                   0x00000040U
-#define  RCC_PLLCFGR_PLLN_1                   0x00000080U
-#define  RCC_PLLCFGR_PLLN_2                   0x00000100U
-#define  RCC_PLLCFGR_PLLN_3                   0x00000200U
-#define  RCC_PLLCFGR_PLLN_4                   0x00000400U
-#define  RCC_PLLCFGR_PLLN_5                   0x00000800U
-#define  RCC_PLLCFGR_PLLN_6                   0x00001000U
-#define  RCC_PLLCFGR_PLLN_7                   0x00002000U
-#define  RCC_PLLCFGR_PLLN_8                   0x00004000U
-
-#define  RCC_PLLCFGR_PLLP                    0x00030000U
-#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
-#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
-
-#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
-
-#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
-#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
-#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
-#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
-#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-/*!< SW configuration */
-#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
-
-#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
-
-#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
-
-#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
-
-/*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     0x001F0000U
-#define  RCC_CFGR_RTCPRE_0                   0x00010000U
-#define  RCC_CFGR_RTCPRE_1                   0x00020000U
-#define  RCC_CFGR_RTCPRE_2                   0x00040000U
-#define  RCC_CFGR_RTCPRE_3                   0x00080000U
-#define  RCC_CFGR_RTCPRE_4                   0x00100000U
-
-/*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       0x00600000U
-#define  RCC_CFGR_MCO1_0                     0x00200000U
-#define  RCC_CFGR_MCO1_1                     0x00400000U
-
-#define  RCC_CFGR_I2SSRC                     0x00800000U
-
-#define  RCC_CFGR_MCO1PRE                    0x07000000U
-#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
-#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
-#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
-
-#define  RCC_CFGR_MCO2PRE                    0x38000000U
-#define  RCC_CFGR_MCO2PRE_0                  0x08000000U
-#define  RCC_CFGR_MCO2PRE_1                  0x10000000U
-#define  RCC_CFGR_MCO2PRE_2                  0x20000000U
-
-#define  RCC_CFGR_MCO2                       0xC0000000U
-#define  RCC_CFGR_MCO2_0                     0x40000000U
-#define  RCC_CFGR_MCO2_1                     0x80000000U
-
-/********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     0x00000001U
-#define  RCC_CIR_LSERDYF                     0x00000002U
-#define  RCC_CIR_HSIRDYF                     0x00000004U
-#define  RCC_CIR_HSERDYF                     0x00000008U
-#define  RCC_CIR_PLLRDYF                     0x00000010U
-#define  RCC_CIR_PLLI2SRDYF                  0x00000020U
-#define  RCC_CIR_PLLSAIRDYF                  0x00000040U
-#define  RCC_CIR_CSSF                        0x00000080U
-#define  RCC_CIR_LSIRDYIE                    0x00000100U
-#define  RCC_CIR_LSERDYIE                    0x00000200U
-#define  RCC_CIR_HSIRDYIE                    0x00000400U
-#define  RCC_CIR_HSERDYIE                    0x00000800U
-#define  RCC_CIR_PLLRDYIE                    0x00001000U
-#define  RCC_CIR_PLLI2SRDYIE                 0x00002000U
-#define  RCC_CIR_PLLSAIRDYIE                 0x00004000U
-#define  RCC_CIR_LSIRDYC                     0x00010000U
-#define  RCC_CIR_LSERDYC                     0x00020000U
-#define  RCC_CIR_HSIRDYC                     0x00040000U
-#define  RCC_CIR_HSERDYC                     0x00080000U
-#define  RCC_CIR_PLLRDYC                     0x00100000U
-#define  RCC_CIR_PLLI2SRDYC                  0x00200000U
-#define  RCC_CIR_PLLSAIRDYC                  0x00400000U
-#define  RCC_CIR_CSSC                        0x00800000U
-
-/********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
-#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
-#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
-#define  RCC_AHB1RSTR_GPIODRST               0x00000008U
-#define  RCC_AHB1RSTR_GPIOERST               0x00000010U
-#define  RCC_AHB1RSTR_GPIOFRST               0x00000020U
-#define  RCC_AHB1RSTR_GPIOGRST               0x00000040U
-#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
-#define  RCC_AHB1RSTR_GPIOIRST               0x00000100U
-#define  RCC_AHB1RSTR_GPIOJRST               0x00000200U
-#define  RCC_AHB1RSTR_GPIOKRST               0x00000400U
-#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
-#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
-#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
-#define  RCC_AHB1RSTR_DMA2DRST               0x00800000U
-#define  RCC_AHB1RSTR_ETHMACRST              0x02000000U
-#define  RCC_AHB1RSTR_OTGHRST                0x20000000U
-
-/********************  Bit definition for RCC_AHB2RSTR register  **************/
-#define  RCC_AHB2RSTR_DCMIRST                0x00000001U
-#define  RCC_AHB2RSTR_CRYPRST                0x00000010U
-#define  RCC_AHB2RSTR_HASHRST                0x00000020U
- /* maintained for legacy purpose */
- #define  RCC_AHB2RSTR_HSAHRST                RCC_AHB2RSTR_HASHRST
-#define  RCC_AHB2RSTR_RNGRST                 0x00000040U
-#define  RCC_AHB2RSTR_OTGFSRST               0x00000080U
-
-/********************  Bit definition for RCC_AHB3RSTR register  **************/
-#define  RCC_AHB3RSTR_FMCRST                0x00000001U
-
-/********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM2RST                0x00000001U
-#define  RCC_APB1RSTR_TIM3RST                0x00000002U
-#define  RCC_APB1RSTR_TIM4RST                0x00000004U
-#define  RCC_APB1RSTR_TIM5RST                0x00000008U
-#define  RCC_APB1RSTR_TIM6RST                0x00000010U
-#define  RCC_APB1RSTR_TIM7RST                0x00000020U
-#define  RCC_APB1RSTR_TIM12RST               0x00000040U
-#define  RCC_APB1RSTR_TIM13RST               0x00000080U
-#define  RCC_APB1RSTR_TIM14RST               0x00000100U
-#define  RCC_APB1RSTR_WWDGRST                0x00000800U
-#define  RCC_APB1RSTR_SPI2RST                0x00004000U
-#define  RCC_APB1RSTR_SPI3RST                0x00008000U
-#define  RCC_APB1RSTR_USART2RST              0x00020000U
-#define  RCC_APB1RSTR_USART3RST              0x00040000U
-#define  RCC_APB1RSTR_UART4RST               0x00080000U
-#define  RCC_APB1RSTR_UART5RST               0x00100000U
-#define  RCC_APB1RSTR_I2C1RST                0x00200000U
-#define  RCC_APB1RSTR_I2C2RST                0x00400000U
-#define  RCC_APB1RSTR_I2C3RST                0x00800000U
-#define  RCC_APB1RSTR_CAN1RST                0x02000000U
-#define  RCC_APB1RSTR_CAN2RST                0x04000000U
-#define  RCC_APB1RSTR_PWRRST                 0x10000000U
-#define  RCC_APB1RSTR_DACRST                 0x20000000U
-#define  RCC_APB1RSTR_UART7RST               0x40000000U
-#define  RCC_APB1RSTR_UART8RST               0x80000000U
-
-/********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                0x00000001U
-#define  RCC_APB2RSTR_TIM8RST                0x00000002U
-#define  RCC_APB2RSTR_USART1RST              0x00000010U
-#define  RCC_APB2RSTR_USART6RST              0x00000020U
-#define  RCC_APB2RSTR_ADCRST                 0x00000100U
-#define  RCC_APB2RSTR_SDIORST                0x00000800U
-#define  RCC_APB2RSTR_SPI1RST                0x00001000U
-#define  RCC_APB2RSTR_SPI4RST                0x00002000U
-#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
-#define  RCC_APB2RSTR_TIM9RST                0x00010000U
-#define  RCC_APB2RSTR_TIM10RST               0x00020000U
-#define  RCC_APB2RSTR_TIM11RST               0x00040000U
-#define  RCC_APB2RSTR_SPI5RST                0x00100000U
-#define  RCC_APB2RSTR_SPI6RST                0x00200000U
-#define  RCC_APB2RSTR_SAI1RST                0x00400000U
-
-/* Old SPI1RST bit definition, maintained for legacy purpose */
-#define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
-
-/********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
-#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
-#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
-#define  RCC_AHB1ENR_GPIODEN                 0x00000008U
-#define  RCC_AHB1ENR_GPIOEEN                 0x00000010U
-#define  RCC_AHB1ENR_GPIOFEN                 0x00000020U
-#define  RCC_AHB1ENR_GPIOGEN                 0x00000040U
-#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
-#define  RCC_AHB1ENR_GPIOIEN                 0x00000100U
-#define  RCC_AHB1ENR_GPIOJEN                 0x00000200U
-#define  RCC_AHB1ENR_GPIOKEN                 0x00000400U
-
-#define  RCC_AHB1ENR_CRCEN                   0x00001000U
-#define  RCC_AHB1ENR_BKPSRAMEN               0x00040000U
-#define  RCC_AHB1ENR_CCMDATARAMEN            0x00100000U
-#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
-#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
-#define  RCC_AHB1ENR_DMA2DEN                 0x00800000U
-
-#define  RCC_AHB1ENR_ETHMACEN                0x02000000U
-#define  RCC_AHB1ENR_ETHMACTXEN              0x04000000U
-#define  RCC_AHB1ENR_ETHMACRXEN              0x08000000U
-#define  RCC_AHB1ENR_ETHMACPTPEN             0x10000000U
-#define  RCC_AHB1ENR_OTGHSEN                 0x20000000U
-#define  RCC_AHB1ENR_OTGHSULPIEN             0x40000000U
-
-/********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define  RCC_AHB2ENR_DCMIEN                  0x00000001U
-#define  RCC_AHB2ENR_CRYPEN                  0x00000010U
-#define  RCC_AHB2ENR_HASHEN                  0x00000020U
-#define  RCC_AHB2ENR_RNGEN                   0x00000040U
-#define  RCC_AHB2ENR_OTGFSEN                 0x00000080U
-
-/********************  Bit definition for RCC_AHB3ENR register  ***************/
-#define  RCC_AHB3ENR_FMCEN                  0x00000001U
-
-/********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM2EN                  0x00000001U
-#define  RCC_APB1ENR_TIM3EN                  0x00000002U
-#define  RCC_APB1ENR_TIM4EN                  0x00000004U
-#define  RCC_APB1ENR_TIM5EN                  0x00000008U
-#define  RCC_APB1ENR_TIM6EN                  0x00000010U
-#define  RCC_APB1ENR_TIM7EN                  0x00000020U
-#define  RCC_APB1ENR_TIM12EN                 0x00000040U
-#define  RCC_APB1ENR_TIM13EN                 0x00000080U
-#define  RCC_APB1ENR_TIM14EN                 0x00000100U
-#define  RCC_APB1ENR_WWDGEN                  0x00000800U
-#define  RCC_APB1ENR_SPI2EN                  0x00004000U
-#define  RCC_APB1ENR_SPI3EN                  0x00008000U
-#define  RCC_APB1ENR_USART2EN                0x00020000U
-#define  RCC_APB1ENR_USART3EN                0x00040000U
-#define  RCC_APB1ENR_UART4EN                 0x00080000U
-#define  RCC_APB1ENR_UART5EN                 0x00100000U
-#define  RCC_APB1ENR_I2C1EN                  0x00200000U
-#define  RCC_APB1ENR_I2C2EN                  0x00400000U
-#define  RCC_APB1ENR_I2C3EN                  0x00800000U
-#define  RCC_APB1ENR_CAN1EN                  0x02000000U
-#define  RCC_APB1ENR_CAN2EN                  0x04000000U
-#define  RCC_APB1ENR_PWREN                   0x10000000U
-#define  RCC_APB1ENR_DACEN                   0x20000000U
-#define  RCC_APB1ENR_UART7EN                 0x40000000U
-#define  RCC_APB1ENR_UART8EN                 0x80000000U
-
-/********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  0x00000001U
-#define  RCC_APB2ENR_TIM8EN                  0x00000002U
-#define  RCC_APB2ENR_USART1EN                0x00000010U
-#define  RCC_APB2ENR_USART6EN                0x00000020U
-#define  RCC_APB2ENR_ADC1EN                  0x00000100U
-#define  RCC_APB2ENR_ADC2EN                  0x00000200U
-#define  RCC_APB2ENR_ADC3EN                  0x00000400U
-#define  RCC_APB2ENR_SDIOEN                  0x00000800U
-#define  RCC_APB2ENR_SPI1EN                  0x00001000U
-#define  RCC_APB2ENR_SPI4EN                  0x00002000U
-#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
-#define  RCC_APB2ENR_TIM9EN                  0x00010000U
-#define  RCC_APB2ENR_TIM10EN                 0x00020000U
-#define  RCC_APB2ENR_TIM11EN                 0x00040000U
-#define  RCC_APB2ENR_SPI5EN                  0x00100000U
-#define  RCC_APB2ENR_SPI6EN                  0x00200000U
-#define  RCC_APB2ENR_SAI1EN                  0x00400000U
-
-/********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
-#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
-#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
-#define  RCC_AHB1LPENR_GPIODLPEN             0x00000008U
-#define  RCC_AHB1LPENR_GPIOELPEN             0x00000010U
-#define  RCC_AHB1LPENR_GPIOFLPEN             0x00000020U
-#define  RCC_AHB1LPENR_GPIOGLPEN             0x00000040U
-#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
-#define  RCC_AHB1LPENR_GPIOILPEN             0x00000100U
-#define  RCC_AHB1LPENR_GPIOJLPEN             0x00000200U
-#define  RCC_AHB1LPENR_GPIOKLPEN             0x00000400U
-
-#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
-#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
-#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
-#define  RCC_AHB1LPENR_SRAM2LPEN             0x00020000U
-#define  RCC_AHB1LPENR_BKPSRAMLPEN           0x00040000U
-#define  RCC_AHB1LPENR_SRAM3LPEN             0x00080000U
-#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
-#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
-#define  RCC_AHB1LPENR_DMA2DLPEN             0x00800000U
-
-#define  RCC_AHB1LPENR_ETHMACLPEN            0x02000000U
-#define  RCC_AHB1LPENR_ETHMACTXLPEN          0x04000000U
-#define  RCC_AHB1LPENR_ETHMACRXLPEN          0x08000000U
-#define  RCC_AHB1LPENR_ETHMACPTPLPEN         0x10000000U
-#define  RCC_AHB1LPENR_OTGHSLPEN             0x20000000U
-#define  RCC_AHB1LPENR_OTGHSULPILPEN         0x40000000U
-
-/********************  Bit definition for RCC_AHB2LPENR register  *************/
-#define  RCC_AHB2LPENR_DCMILPEN              0x00000001U
-#define  RCC_AHB2LPENR_CRYPLPEN              0x00000010U
-#define  RCC_AHB2LPENR_HASHLPEN              0x00000020U
-#define  RCC_AHB2LPENR_RNGLPEN               0x00000040U
-#define  RCC_AHB2LPENR_OTGFSLPEN             0x00000080U
-
-/********************  Bit definition for RCC_AHB3LPENR register  *************/
-#define  RCC_AHB3LPENR_FMCLPEN              0x00000001U
-
-/********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM2LPEN              0x00000001U
-#define  RCC_APB1LPENR_TIM3LPEN              0x00000002U
-#define  RCC_APB1LPENR_TIM4LPEN              0x00000004U
-#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
-#define  RCC_APB1LPENR_TIM6LPEN              0x00000010U
-#define  RCC_APB1LPENR_TIM7LPEN              0x00000020U
-#define  RCC_APB1LPENR_TIM12LPEN             0x00000040U
-#define  RCC_APB1LPENR_TIM13LPEN             0x00000080U
-#define  RCC_APB1LPENR_TIM14LPEN             0x00000100U
-#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
-#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U
-#define  RCC_APB1LPENR_SPI3LPEN              0x00008000U
-#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
-#define  RCC_APB1LPENR_USART3LPEN            0x00040000U
-#define  RCC_APB1LPENR_UART4LPEN             0x00080000U
-#define  RCC_APB1LPENR_UART5LPEN             0x00100000U
-#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
-#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
-#define  RCC_APB1LPENR_I2C3LPEN              0x00800000U
-#define  RCC_APB1LPENR_CAN1LPEN              0x02000000U
-#define  RCC_APB1LPENR_CAN2LPEN              0x04000000U
-#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
-#define  RCC_APB1LPENR_DACLPEN               0x20000000U
-#define  RCC_APB1LPENR_UART7LPEN             0x40000000U
-#define  RCC_APB1LPENR_UART8LPEN             0x80000000U
-
-/********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
-#define  RCC_APB2LPENR_TIM8LPEN              0x00000002U
-#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
-#define  RCC_APB2LPENR_USART6LPEN            0x00000020U
-#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
-#define  RCC_APB2LPENR_ADC2LPEN              0x00000200U
-#define  RCC_APB2LPENR_ADC3LPEN              0x00000400U
-#define  RCC_APB2LPENR_SDIOLPEN              0x00000800U
-#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
-#define  RCC_APB2LPENR_SPI4LPEN              0x00002000U
-#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
-#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
-#define  RCC_APB2LPENR_TIM10LPEN             0x00020000U
-#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
-#define  RCC_APB2LPENR_SPI5LPEN              0x00100000U
-#define  RCC_APB2LPENR_SPI6LPEN              0x00200000U
-#define  RCC_APB2LPENR_SAI1LPEN              0x00400000U
-
-/********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      0x00000001U
-#define  RCC_BDCR_LSERDY                     0x00000002U
-#define  RCC_BDCR_LSEBYP                     0x00000004U
-
-#define  RCC_BDCR_RTCSEL                    0x00000300U
-#define  RCC_BDCR_RTCSEL_0                  0x00000100U
-#define  RCC_BDCR_RTCSEL_1                  0x00000200U
-
-#define  RCC_BDCR_RTCEN                      0x00008000U
-#define  RCC_BDCR_BDRST                      0x00010000U
-
-/********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       0x00000001U
-#define  RCC_CSR_LSIRDY                      0x00000002U
-#define  RCC_CSR_RMVF                        0x01000000U
-#define  RCC_CSR_BORRSTF                     0x02000000U
-#define  RCC_CSR_PADRSTF                     0x04000000U
-#define  RCC_CSR_PORRSTF                     0x08000000U
-#define  RCC_CSR_SFTRSTF                     0x10000000U
-#define  RCC_CSR_WDGRSTF                     0x20000000U
-#define  RCC_CSR_WWDGRSTF                    0x40000000U
-#define  RCC_CSR_LPWRRSTF                    0x80000000U
-
-/********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    0x00001FFFU
-#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
-#define  RCC_SSCGR_SPREADSEL                 0x40000000U
-#define  RCC_SSCGR_SSCGEN                    0x80000000U
-
-/********************  Bit definition for RCC_PLLI2SCFGR register  ************/
-#define  RCC_PLLI2SCFGR_PLLI2SN              0x00007FC0U
-#define  RCC_PLLI2SCFGR_PLLI2SN_0            0x00000040U
-#define  RCC_PLLI2SCFGR_PLLI2SN_1            0x00000080U
-#define  RCC_PLLI2SCFGR_PLLI2SN_2            0x00000100U
-#define  RCC_PLLI2SCFGR_PLLI2SN_3            0x00000200U
-#define  RCC_PLLI2SCFGR_PLLI2SN_4            0x00000400U
-#define  RCC_PLLI2SCFGR_PLLI2SN_5            0x00000800U
-#define  RCC_PLLI2SCFGR_PLLI2SN_6            0x00001000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_7            0x00002000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_8            0x00004000U
-
-#define  RCC_PLLI2SCFGR_PLLI2SQ              0x0F000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_0            0x01000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_1            0x02000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_2            0x04000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_3            0x08000000U
-
-#define  RCC_PLLI2SCFGR_PLLI2SR              0x70000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_0            0x10000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_1            0x20000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_2            0x40000000U
-
-
-/********************  Bit definition for RCC_PLLSAICFGR register  ************/
-#define  RCC_PLLSAICFGR_PLLSAIN              0x00007FC0U
-#define  RCC_PLLSAICFGR_PLLSAIN_0            0x00000040U
-#define  RCC_PLLSAICFGR_PLLSAIN_1            0x00000080U
-#define  RCC_PLLSAICFGR_PLLSAIN_2            0x00000100U
-#define  RCC_PLLSAICFGR_PLLSAIN_3            0x00000200U
-#define  RCC_PLLSAICFGR_PLLSAIN_4            0x00000400U
-#define  RCC_PLLSAICFGR_PLLSAIN_5            0x00000800U
-#define  RCC_PLLSAICFGR_PLLSAIN_6            0x00001000U
-#define  RCC_PLLSAICFGR_PLLSAIN_7            0x00002000U
-#define  RCC_PLLSAICFGR_PLLSAIN_8            0x00004000U
-
-#define  RCC_PLLSAICFGR_PLLSAIQ              0x0F000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_0            0x01000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_1            0x02000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_2            0x04000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_3            0x08000000U
-
-#define  RCC_PLLSAICFGR_PLLSAIR              0x70000000U
-#define  RCC_PLLSAICFGR_PLLSAIR_0            0x10000000U
-#define  RCC_PLLSAICFGR_PLLSAIR_1            0x20000000U
-#define  RCC_PLLSAICFGR_PLLSAIR_2            0x40000000U
-
-/********************  Bit definition for RCC_DCKCFGR register  ***************/
-#define  RCC_DCKCFGR_PLLI2SDIVQ              0x0000001FU
-#define  RCC_DCKCFGR_PLLSAIDIVQ              0x00001F00U
-#define  RCC_DCKCFGR_PLLSAIDIVR              0x00030000U
-#define  RCC_DCKCFGR_SAI1ASRC                0x00300000U
-#define  RCC_DCKCFGR_SAI1ASRC_0              0x00100000U
-#define  RCC_DCKCFGR_SAI1ASRC_1              0x00200000U
-#define  RCC_DCKCFGR_SAI1BSRC                0x00C00000U
-#define  RCC_DCKCFGR_SAI1BSRC_0              0x00400000U
-#define  RCC_DCKCFGR_SAI1BSRC_1              0x00800000U
-#define  RCC_DCKCFGR_TIMPRE                  0x01000000U
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    RNG                                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN                         0x00000004U
-#define RNG_CR_IE                            0x00000008U
-
-/********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY                          0x00000001U
-#define RNG_SR_CECS                          0x00000002U
-#define RNG_SR_SECS                          0x00000004U
-#define RNG_SR_CEIS                          0x00000020U
-#define RNG_SR_SEIS                          0x00000040U
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            0x00400000U
-#define RTC_TR_HT                            0x00300000U
-#define RTC_TR_HT_0                          0x00100000U
-#define RTC_TR_HT_1                          0x00200000U
-#define RTC_TR_HU                            0x000F0000U
-#define RTC_TR_HU_0                          0x00010000U
-#define RTC_TR_HU_1                          0x00020000U
-#define RTC_TR_HU_2                          0x00040000U
-#define RTC_TR_HU_3                          0x00080000U
-#define RTC_TR_MNT                           0x00007000U
-#define RTC_TR_MNT_0                         0x00001000U
-#define RTC_TR_MNT_1                         0x00002000U
-#define RTC_TR_MNT_2                         0x00004000U
-#define RTC_TR_MNU                           0x00000F00U
-#define RTC_TR_MNU_0                         0x00000100U
-#define RTC_TR_MNU_1                         0x00000200U
-#define RTC_TR_MNU_2                         0x00000400U
-#define RTC_TR_MNU_3                         0x00000800U
-#define RTC_TR_ST                            0x00000070U
-#define RTC_TR_ST_0                          0x00000010U
-#define RTC_TR_ST_1                          0x00000020U
-#define RTC_TR_ST_2                          0x00000040U
-#define RTC_TR_SU                            0x0000000FU
-#define RTC_TR_SU_0                          0x00000001U
-#define RTC_TR_SU_1                          0x00000002U
-#define RTC_TR_SU_2                          0x00000004U
-#define RTC_TR_SU_3                          0x00000008U
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            0x00F00000U
-#define RTC_DR_YT_0                          0x00100000U
-#define RTC_DR_YT_1                          0x00200000U
-#define RTC_DR_YT_2                          0x00400000U
-#define RTC_DR_YT_3                          0x00800000U
-#define RTC_DR_YU                            0x000F0000U
-#define RTC_DR_YU_0                          0x00010000U
-#define RTC_DR_YU_1                          0x00020000U
-#define RTC_DR_YU_2                          0x00040000U
-#define RTC_DR_YU_3                          0x00080000U
-#define RTC_DR_WDU                           0x0000E000U
-#define RTC_DR_WDU_0                         0x00002000U
-#define RTC_DR_WDU_1                         0x00004000U
-#define RTC_DR_WDU_2                         0x00008000U
-#define RTC_DR_MT                            0x00001000U
-#define RTC_DR_MU                            0x00000F00U
-#define RTC_DR_MU_0                          0x00000100U
-#define RTC_DR_MU_1                          0x00000200U
-#define RTC_DR_MU_2                          0x00000400U
-#define RTC_DR_MU_3                          0x00000800U
-#define RTC_DR_DT                            0x00000030U
-#define RTC_DR_DT_0                          0x00000010U
-#define RTC_DR_DT_1                          0x00000020U
-#define RTC_DR_DU                            0x0000000FU
-#define RTC_DR_DU_0                          0x00000001U
-#define RTC_DR_DU_1                          0x00000002U
-#define RTC_DR_DU_2                          0x00000004U
-#define RTC_DR_DU_3                          0x00000008U
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           0x00800000U
-#define RTC_CR_OSEL                          0x00600000U
-#define RTC_CR_OSEL_0                        0x00200000U
-#define RTC_CR_OSEL_1                        0x00400000U
-#define RTC_CR_POL                           0x00100000U
-#define RTC_CR_COSEL                         0x00080000U
-#define RTC_CR_BCK                           0x00040000U
-#define RTC_CR_SUB1H                         0x00020000U
-#define RTC_CR_ADD1H                         0x00010000U
-#define RTC_CR_TSIE                          0x00008000U
-#define RTC_CR_WUTIE                         0x00004000U
-#define RTC_CR_ALRBIE                        0x00002000U
-#define RTC_CR_ALRAIE                        0x00001000U
-#define RTC_CR_TSE                           0x00000800U
-#define RTC_CR_WUTE                          0x00000400U
-#define RTC_CR_ALRBE                         0x00000200U
-#define RTC_CR_ALRAE                         0x00000100U
-#define RTC_CR_DCE                           0x00000080U
-#define RTC_CR_FMT                           0x00000040U
-#define RTC_CR_BYPSHAD                       0x00000020U
-#define RTC_CR_REFCKON                       0x00000010U
-#define RTC_CR_TSEDGE                        0x00000008U
-#define RTC_CR_WUCKSEL                       0x00000007U
-#define RTC_CR_WUCKSEL_0                     0x00000001U
-#define RTC_CR_WUCKSEL_1                     0x00000002U
-#define RTC_CR_WUCKSEL_2                     0x00000004U
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      0x00010000U
-#define RTC_ISR_TAMP1F                       0x00002000U
-#define RTC_ISR_TAMP2F                       0x00004000U
-#define RTC_ISR_TSOVF                        0x00001000U
-#define RTC_ISR_TSF                          0x00000800U
-#define RTC_ISR_WUTF                         0x00000400U
-#define RTC_ISR_ALRBF                        0x00000200U
-#define RTC_ISR_ALRAF                        0x00000100U
-#define RTC_ISR_INIT                         0x00000080U
-#define RTC_ISR_INITF                        0x00000040U
-#define RTC_ISR_RSF                          0x00000020U
-#define RTC_ISR_INITS                        0x00000010U
-#define RTC_ISR_SHPF                         0x00000008U
-#define RTC_ISR_WUTWF                        0x00000004U
-#define RTC_ISR_ALRBWF                       0x00000002U
-#define RTC_ISR_ALRAWF                       0x00000001U
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    0x007F0000U
-#define RTC_PRER_PREDIV_S                    0x00007FFFU
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS                       0x00000080U
-#define RTC_CALIBR_DC                        0x0000001FU
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      0x80000000U
-#define RTC_ALRMAR_WDSEL                     0x40000000U
-#define RTC_ALRMAR_DT                        0x30000000U
-#define RTC_ALRMAR_DT_0                      0x10000000U
-#define RTC_ALRMAR_DT_1                      0x20000000U
-#define RTC_ALRMAR_DU                        0x0F000000U
-#define RTC_ALRMAR_DU_0                      0x01000000U
-#define RTC_ALRMAR_DU_1                      0x02000000U
-#define RTC_ALRMAR_DU_2                      0x04000000U
-#define RTC_ALRMAR_DU_3                      0x08000000U
-#define RTC_ALRMAR_MSK3                      0x00800000U
-#define RTC_ALRMAR_PM                        0x00400000U
-#define RTC_ALRMAR_HT                        0x00300000U
-#define RTC_ALRMAR_HT_0                      0x00100000U
-#define RTC_ALRMAR_HT_1                      0x00200000U
-#define RTC_ALRMAR_HU                        0x000F0000U
-#define RTC_ALRMAR_HU_0                      0x00010000U
-#define RTC_ALRMAR_HU_1                      0x00020000U
-#define RTC_ALRMAR_HU_2                      0x00040000U
-#define RTC_ALRMAR_HU_3                      0x00080000U
-#define RTC_ALRMAR_MSK2                      0x00008000U
-#define RTC_ALRMAR_MNT                       0x00007000U
-#define RTC_ALRMAR_MNT_0                     0x00001000U
-#define RTC_ALRMAR_MNT_1                     0x00002000U
-#define RTC_ALRMAR_MNT_2                     0x00004000U
-#define RTC_ALRMAR_MNU                       0x00000F00U
-#define RTC_ALRMAR_MNU_0                     0x00000100U
-#define RTC_ALRMAR_MNU_1                     0x00000200U
-#define RTC_ALRMAR_MNU_2                     0x00000400U
-#define RTC_ALRMAR_MNU_3                     0x00000800U
-#define RTC_ALRMAR_MSK1                      0x00000080U
-#define RTC_ALRMAR_ST                        0x00000070U
-#define RTC_ALRMAR_ST_0                      0x00000010U
-#define RTC_ALRMAR_ST_1                      0x00000020U
-#define RTC_ALRMAR_ST_2                      0x00000040U
-#define RTC_ALRMAR_SU                        0x0000000FU
-#define RTC_ALRMAR_SU_0                      0x00000001U
-#define RTC_ALRMAR_SU_1                      0x00000002U
-#define RTC_ALRMAR_SU_2                      0x00000004U
-#define RTC_ALRMAR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      0x80000000U
-#define RTC_ALRMBR_WDSEL                     0x40000000U
-#define RTC_ALRMBR_DT                        0x30000000U
-#define RTC_ALRMBR_DT_0                      0x10000000U
-#define RTC_ALRMBR_DT_1                      0x20000000U
-#define RTC_ALRMBR_DU                        0x0F000000U
-#define RTC_ALRMBR_DU_0                      0x01000000U
-#define RTC_ALRMBR_DU_1                      0x02000000U
-#define RTC_ALRMBR_DU_2                      0x04000000U
-#define RTC_ALRMBR_DU_3                      0x08000000U
-#define RTC_ALRMBR_MSK3                      0x00800000U
-#define RTC_ALRMBR_PM                        0x00400000U
-#define RTC_ALRMBR_HT                        0x00300000U
-#define RTC_ALRMBR_HT_0                      0x00100000U
-#define RTC_ALRMBR_HT_1                      0x00200000U
-#define RTC_ALRMBR_HU                        0x000F0000U
-#define RTC_ALRMBR_HU_0                      0x00010000U
-#define RTC_ALRMBR_HU_1                      0x00020000U
-#define RTC_ALRMBR_HU_2                      0x00040000U
-#define RTC_ALRMBR_HU_3                      0x00080000U
-#define RTC_ALRMBR_MSK2                      0x00008000U
-#define RTC_ALRMBR_MNT                       0x00007000U
-#define RTC_ALRMBR_MNT_0                     0x00001000U
-#define RTC_ALRMBR_MNT_1                     0x00002000U
-#define RTC_ALRMBR_MNT_2                     0x00004000U
-#define RTC_ALRMBR_MNU                       0x00000F00U
-#define RTC_ALRMBR_MNU_0                     0x00000100U
-#define RTC_ALRMBR_MNU_1                     0x00000200U
-#define RTC_ALRMBR_MNU_2                     0x00000400U
-#define RTC_ALRMBR_MNU_3                     0x00000800U
-#define RTC_ALRMBR_MSK1                      0x00000080U
-#define RTC_ALRMBR_ST                        0x00000070U
-#define RTC_ALRMBR_ST_0                      0x00000010U
-#define RTC_ALRMBR_ST_1                      0x00000020U
-#define RTC_ALRMBR_ST_2                      0x00000040U
-#define RTC_ALRMBR_SU                        0x0000000FU
-#define RTC_ALRMBR_SU_0                      0x00000001U
-#define RTC_ALRMBR_SU_1                      0x00000002U
-#define RTC_ALRMBR_SU_2                      0x00000004U
-#define RTC_ALRMBR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          0x000000FFU
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           0x0000FFFFU
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     0x00007FFFU
-#define RTC_SHIFTR_ADD1S                     0x80000000U
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          0x00400000U
-#define RTC_TSTR_HT                          0x00300000U
-#define RTC_TSTR_HT_0                        0x00100000U
-#define RTC_TSTR_HT_1                        0x00200000U
-#define RTC_TSTR_HU                          0x000F0000U
-#define RTC_TSTR_HU_0                        0x00010000U
-#define RTC_TSTR_HU_1                        0x00020000U
-#define RTC_TSTR_HU_2                        0x00040000U
-#define RTC_TSTR_HU_3                        0x00080000U
-#define RTC_TSTR_MNT                         0x00007000U
-#define RTC_TSTR_MNT_0                       0x00001000U
-#define RTC_TSTR_MNT_1                       0x00002000U
-#define RTC_TSTR_MNT_2                       0x00004000U
-#define RTC_TSTR_MNU                         0x00000F00U
-#define RTC_TSTR_MNU_0                       0x00000100U
-#define RTC_TSTR_MNU_1                       0x00000200U
-#define RTC_TSTR_MNU_2                       0x00000400U
-#define RTC_TSTR_MNU_3                       0x00000800U
-#define RTC_TSTR_ST                          0x00000070U
-#define RTC_TSTR_ST_0                        0x00000010U
-#define RTC_TSTR_ST_1                        0x00000020U
-#define RTC_TSTR_ST_2                        0x00000040U
-#define RTC_TSTR_SU                          0x0000000FU
-#define RTC_TSTR_SU_0                        0x00000001U
-#define RTC_TSTR_SU_1                        0x00000002U
-#define RTC_TSTR_SU_2                        0x00000004U
-#define RTC_TSTR_SU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         0x0000E000U
-#define RTC_TSDR_WDU_0                       0x00002000U
-#define RTC_TSDR_WDU_1                       0x00004000U
-#define RTC_TSDR_WDU_2                       0x00008000U
-#define RTC_TSDR_MT                          0x00001000U
-#define RTC_TSDR_MU                          0x00000F00U
-#define RTC_TSDR_MU_0                        0x00000100U
-#define RTC_TSDR_MU_1                        0x00000200U
-#define RTC_TSDR_MU_2                        0x00000400U
-#define RTC_TSDR_MU_3                        0x00000800U
-#define RTC_TSDR_DT                          0x00000030U
-#define RTC_TSDR_DT_0                        0x00000010U
-#define RTC_TSDR_DT_1                        0x00000020U
-#define RTC_TSDR_DU                          0x0000000FU
-#define RTC_TSDR_DU_0                        0x00000001U
-#define RTC_TSDR_DU_1                        0x00000002U
-#define RTC_TSDR_DU_2                        0x00000004U
-#define RTC_TSDR_DU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        0x00008000U
-#define RTC_CALR_CALW8                       0x00004000U
-#define RTC_CALR_CALW16                      0x00002000U
-#define RTC_CALR_CALM                        0x000001FFU
-#define RTC_CALR_CALM_0                      0x00000001U
-#define RTC_CALR_CALM_1                      0x00000002U
-#define RTC_CALR_CALM_2                      0x00000004U
-#define RTC_CALR_CALM_3                      0x00000008U
-#define RTC_CALR_CALM_4                      0x00000010U
-#define RTC_CALR_CALM_5                      0x00000020U
-#define RTC_CALR_CALM_6                      0x00000040U
-#define RTC_CALR_CALM_7                      0x00000080U
-#define RTC_CALR_CALM_8                      0x00000100U
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               0x00040000U
-#define RTC_TAFCR_TSINSEL                    0x00020000U
-#define RTC_TAFCR_TAMPINSEL                  0x00010000U
-#define RTC_TAFCR_TAMPPUDIS                  0x00008000U
-#define RTC_TAFCR_TAMPPRCH                   0x00006000U
-#define RTC_TAFCR_TAMPPRCH_0                 0x00002000U
-#define RTC_TAFCR_TAMPPRCH_1                 0x00004000U
-#define RTC_TAFCR_TAMPFLT                    0x00001800U
-#define RTC_TAFCR_TAMPFLT_0                  0x00000800U
-#define RTC_TAFCR_TAMPFLT_1                  0x00001000U
-#define RTC_TAFCR_TAMPFREQ                   0x00000700U
-#define RTC_TAFCR_TAMPFREQ_0                 0x00000100U
-#define RTC_TAFCR_TAMPFREQ_1                 0x00000200U
-#define RTC_TAFCR_TAMPFREQ_2                 0x00000400U
-#define RTC_TAFCR_TAMPTS                     0x00000080U
-#define RTC_TAFCR_TAMP2TRG                   0x00000010U
-#define RTC_TAFCR_TAMP2E                     0x00000008U
-#define RTC_TAFCR_TAMPIE                     0x00000004U
-#define RTC_TAFCR_TAMP1TRG                   0x00000002U
-#define RTC_TAFCR_TAMP1E                     0x00000001U
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  0x0F000000U
-#define RTC_ALRMASSR_MASKSS_0                0x01000000U
-#define RTC_ALRMASSR_MASKSS_1                0x02000000U
-#define RTC_ALRMASSR_MASKSS_2                0x04000000U
-#define RTC_ALRMASSR_MASKSS_3                0x08000000U
-#define RTC_ALRMASSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
-#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
-#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
-#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
-#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
-#define RTC_ALRMBSSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           0xFFFFFFFFU
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Serial Audio Interface                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for SAI_GCR register  *******************/
-#define  SAI_GCR_SYNCIN                  0x00000003U        /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
-#define  SAI_GCR_SYNCIN_0                0x00000001U        /*!<Bit 0 */
-#define  SAI_GCR_SYNCIN_1                0x00000002U        /*!<Bit 1 */
-
-#define  SAI_GCR_SYNCOUT                 0x00000030U        /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
-#define  SAI_GCR_SYNCOUT_0               0x00000010U        /*!<Bit 0 */
-#define  SAI_GCR_SYNCOUT_1               0x00000020U        /*!<Bit 1 */
-
-/*******************  Bit definition for SAI_xCR1 register  *******************/
-#define  SAI_xCR1_MODE                    0x00000003U        /*!<MODE[1:0] bits (Audio Block Mode)           */
-#define  SAI_xCR1_MODE_0                  0x00000001U        /*!<Bit 0 */
-#define  SAI_xCR1_MODE_1                  0x00000002U        /*!<Bit 1 */
-
-#define  SAI_xCR1_PRTCFG                  0x0000000CU        /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
-#define  SAI_xCR1_PRTCFG_0                0x00000004U        /*!<Bit 0 */
-#define  SAI_xCR1_PRTCFG_1                0x00000008U        /*!<Bit 1 */
-
-#define  SAI_xCR1_DS                      0x000000E0U        /*!<DS[1:0] bits (Data Size) */
-#define  SAI_xCR1_DS_0                    0x00000020U        /*!<Bit 0 */
-#define  SAI_xCR1_DS_1                    0x00000040U        /*!<Bit 1 */
-#define  SAI_xCR1_DS_2                    0x00000080U        /*!<Bit 2 */
-
-#define  SAI_xCR1_LSBFIRST                0x00000100U        /*!<LSB First Configuration  */
-#define  SAI_xCR1_CKSTR                   0x00000200U        /*!<ClocK STRobing edge      */
-
-#define  SAI_xCR1_SYNCEN                  0x00000C00U        /*!<SYNCEN[1:0](SYNChronization ENable) */
-#define  SAI_xCR1_SYNCEN_0                0x00000400U        /*!<Bit 0 */
-#define  SAI_xCR1_SYNCEN_1                0x00000800U        /*!<Bit 1 */
-
-#define  SAI_xCR1_MONO                    0x00001000U        /*!<Mono mode                  */
-#define  SAI_xCR1_OUTDRIV                 0x00002000U        /*!<Output Drive               */
-#define  SAI_xCR1_SAIEN                   0x00010000U        /*!<Audio Block enable         */
-#define  SAI_xCR1_DMAEN                   0x00020000U        /*!<DMA enable                 */
-#define  SAI_xCR1_NODIV                   0x00080000U        /*!<No Divider Configuration   */
-
-#define  SAI_xCR1_MCKDIV                  0x00F00000U        /*!<MCKDIV[3:0] (Master ClocK Divider)  */
-#define  SAI_xCR1_MCKDIV_0                0x00100000U        /*!<Bit 0  */
-#define  SAI_xCR1_MCKDIV_1                0x00200000U        /*!<Bit 1  */
-#define  SAI_xCR1_MCKDIV_2                0x00400000U        /*!<Bit 2  */
-#define  SAI_xCR1_MCKDIV_3                0x00800000U        /*!<Bit 3  */
-
-/*******************  Bit definition for SAI_xCR2 register  *******************/
-#define  SAI_xCR2_FTH                     0x00000007U        /*!<FTH[2:0](Fifo THreshold)  */
-#define  SAI_xCR2_FTH_0                   0x00000001U        /*!<Bit 0 */
-#define  SAI_xCR2_FTH_1                   0x00000002U        /*!<Bit 1 */
-#define  SAI_xCR2_FTH_2                   0x00000004U        /*!<Bit 2 */
-
-#define  SAI_xCR2_FFLUSH                  0x00000008U        /*!<Fifo FLUSH                       */
-#define  SAI_xCR2_TRIS                    0x00000010U        /*!<TRIState Management on data line */
-#define  SAI_xCR2_MUTE                    0x00000020U        /*!<Mute mode                        */
-#define  SAI_xCR2_MUTEVAL                 0x00000040U        /*!<Muate value                      */
-
-#define  SAI_xCR2_MUTECNT                  0x00001F80U       /*!<MUTECNT[5:0] (MUTE counter) */
-#define  SAI_xCR2_MUTECNT_0               0x00000080U        /*!<Bit 0 */
-#define  SAI_xCR2_MUTECNT_1               0x00000100U        /*!<Bit 1 */
-#define  SAI_xCR2_MUTECNT_2               0x00000200U        /*!<Bit 2 */
-#define  SAI_xCR2_MUTECNT_3               0x00000400U        /*!<Bit 3 */
-#define  SAI_xCR2_MUTECNT_4               0x00000800U        /*!<Bit 4 */
-#define  SAI_xCR2_MUTECNT_5               0x00001000U        /*!<Bit 5 */
-
-#define  SAI_xCR2_CPL                     0x00002000U        /*!< Complement Bit             */
-
-#define  SAI_xCR2_COMP                    0x0000C000U        /*!<COMP[1:0] (Companding mode) */
-#define  SAI_xCR2_COMP_0                  0x00004000U        /*!<Bit 0 */
-#define  SAI_xCR2_COMP_1                  0x00008000U        /*!<Bit 1 */
-
-/******************  Bit definition for SAI_xFRCR register  *******************/
-#define  SAI_xFRCR_FRL                    0x000000FFU        /*!<FRL[1:0](Frame length)  */
-#define  SAI_xFRCR_FRL_0                  0x00000001U        /*!<Bit 0 */
-#define  SAI_xFRCR_FRL_1                  0x00000002U        /*!<Bit 1 */
-#define  SAI_xFRCR_FRL_2                  0x00000004U        /*!<Bit 2 */
-#define  SAI_xFRCR_FRL_3                  0x00000008U        /*!<Bit 3 */
-#define  SAI_xFRCR_FRL_4                  0x00000010U        /*!<Bit 4 */
-#define  SAI_xFRCR_FRL_5                  0x00000020U        /*!<Bit 5 */
-#define  SAI_xFRCR_FRL_6                  0x00000040U        /*!<Bit 6 */
-#define  SAI_xFRCR_FRL_7                  0x00000080U        /*!<Bit 7 */
-
-#define  SAI_xFRCR_FSALL                  0x00007F00U        /*!<FRL[1:0] (Frame synchronization active level length)  */
-#define  SAI_xFRCR_FSALL_0                0x00000100U        /*!<Bit 0 */
-#define  SAI_xFRCR_FSALL_1                0x00000200U        /*!<Bit 1 */
-#define  SAI_xFRCR_FSALL_2                0x00000400U        /*!<Bit 2 */
-#define  SAI_xFRCR_FSALL_3                0x00000800U        /*!<Bit 3 */
-#define  SAI_xFRCR_FSALL_4                0x00001000U        /*!<Bit 4 */
-#define  SAI_xFRCR_FSALL_5                0x00002000U        /*!<Bit 5 */
-#define  SAI_xFRCR_FSALL_6                0x00004000U        /*!<Bit 6 */
-
-#define  SAI_xFRCR_FSDEF                  0x00010000U        /*!< Frame Synchronization Definition */
-#define  SAI_xFRCR_FSPOL                  0x00020000U        /*!<Frame Synchronization POLarity    */
-#define  SAI_xFRCR_FSOFF                  0x00040000U        /*!<Frame Synchronization OFFset      */
-/* Legacy defines */
-#define  SAI_xFRCR_FSPO                   SAI_xFRCR_FSPOL
-
-/******************  Bit definition for SAI_xSLOTR register  *******************/
-#define  SAI_xSLOTR_FBOFF                 0x0000001FU        /*!<FRL[4:0](First Bit Offset)  */
-#define  SAI_xSLOTR_FBOFF_0               0x00000001U        /*!<Bit 0 */
-#define  SAI_xSLOTR_FBOFF_1               0x00000002U        /*!<Bit 1 */
-#define  SAI_xSLOTR_FBOFF_2               0x00000004U        /*!<Bit 2 */
-#define  SAI_xSLOTR_FBOFF_3               0x00000008U        /*!<Bit 3 */
-#define  SAI_xSLOTR_FBOFF_4               0x00000010U        /*!<Bit 4 */
-
-#define  SAI_xSLOTR_SLOTSZ                0x000000C0U        /*!<SLOTSZ[1:0] (Slot size)  */
-#define  SAI_xSLOTR_SLOTSZ_0              0x00000040U        /*!<Bit 0 */
-#define  SAI_xSLOTR_SLOTSZ_1              0x00000080U        /*!<Bit 1 */
-
-#define  SAI_xSLOTR_NBSLOT                0x00000F00U        /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
-#define  SAI_xSLOTR_NBSLOT_0              0x00000100U        /*!<Bit 0 */
-#define  SAI_xSLOTR_NBSLOT_1              0x00000200U        /*!<Bit 1 */
-#define  SAI_xSLOTR_NBSLOT_2              0x00000400U        /*!<Bit 2 */
-#define  SAI_xSLOTR_NBSLOT_3              0x00000800U        /*!<Bit 3 */
-
-#define  SAI_xSLOTR_SLOTEN                0xFFFF0000U        /*!<SLOTEN[15:0] (Slot Enable)  */
-
-/*******************  Bit definition for SAI_xIMR register  *******************/
-#define  SAI_xIMR_OVRUDRIE                0x00000001U        /*!<Overrun underrun interrupt enable                              */
-#define  SAI_xIMR_MUTEDETIE               0x00000002U        /*!<Mute detection interrupt enable                                */
-#define  SAI_xIMR_WCKCFGIE                0x00000004U        /*!<Wrong Clock Configuration interrupt enable                     */
-#define  SAI_xIMR_FREQIE                  0x00000008U        /*!<FIFO request interrupt enable                                  */
-#define  SAI_xIMR_CNRDYIE                 0x00000010U        /*!<Codec not ready interrupt enable                               */
-#define  SAI_xIMR_AFSDETIE                0x00000020U        /*!<Anticipated frame synchronization detection interrupt enable   */
-#define  SAI_xIMR_LFSDETIE                0x00000040U        /*!<Late frame synchronization detection interrupt enable          */
-
-/********************  Bit definition for SAI_xSR register  *******************/
-#define  SAI_xSR_OVRUDR                   0x00000001U         /*!<Overrun underrun                               */
-#define  SAI_xSR_MUTEDET                  0x00000002U         /*!<Mute detection                                 */
-#define  SAI_xSR_WCKCFG                   0x00000004U         /*!<Wrong Clock Configuration                      */
-#define  SAI_xSR_FREQ                     0x00000008U         /*!<FIFO request                                   */
-#define  SAI_xSR_CNRDY                    0x00000010U         /*!<Codec not ready                                */
-#define  SAI_xSR_AFSDET                   0x00000020U         /*!<Anticipated frame synchronization detection    */
-#define  SAI_xSR_LFSDET                   0x00000040U         /*!<Late frame synchronization detection           */
-
-#define  SAI_xSR_FLVL                     0x00070000U         /*!<FLVL[2:0] (FIFO Level Threshold)               */
-#define  SAI_xSR_FLVL_0                   0x00010000U         /*!<Bit 0 */
-#define  SAI_xSR_FLVL_1                   0x00020000U         /*!<Bit 1 */
-#define  SAI_xSR_FLVL_2                   0x00040000U         /*!<Bit 2 */
-
-/******************  Bit definition for SAI_xCLRFR register  ******************/
-#define  SAI_xCLRFR_COVRUDR               0x00000001U        /*!<Clear Overrun underrun                               */
-#define  SAI_xCLRFR_CMUTEDET              0x00000002U        /*!<Clear Mute detection                                 */
-#define  SAI_xCLRFR_CWCKCFG               0x00000004U        /*!<Clear Wrong Clock Configuration                      */
-#define  SAI_xCLRFR_CFREQ                 0x00000008U        /*!<Clear FIFO request                                   */
-#define  SAI_xCLRFR_CCNRDY                0x00000010U        /*!<Clear Codec not ready                                */
-#define  SAI_xCLRFR_CAFSDET               0x00000020U        /*!<Clear Anticipated frame synchronization detection    */
-#define  SAI_xCLRFR_CLFSDET               0x00000040U        /*!<Clear Late frame synchronization detection           */
-
-/******************  Bit definition for SAI_xDR register  ******************/
-#define  SAI_xDR_DATA                     0xFFFFFFFFU        
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          SD host Interface                                 */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SDIO_POWER register  ******************/
-#define  SDIO_POWER_PWRCTRL                  0x03U               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDIO_POWER_PWRCTRL_0                0x01U               /*!<Bit 0 */
-#define  SDIO_POWER_PWRCTRL_1                0x02U               /*!<Bit 1 */
-
-/******************  Bit definition for SDIO_CLKCR register  ******************/
-#define  SDIO_CLKCR_CLKDIV                   0x00FFU            /*!<Clock divide factor             */
-#define  SDIO_CLKCR_CLKEN                    0x0100U            /*!<Clock enable bit                */
-#define  SDIO_CLKCR_PWRSAV                   0x0200U            /*!<Power saving configuration bit  */
-#define  SDIO_CLKCR_BYPASS                   0x0400U            /*!<Clock divider bypass enable bit */
-
-#define  SDIO_CLKCR_WIDBUS                   0x1800U            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDIO_CLKCR_WIDBUS_0                 0x0800U            /*!<Bit 0 */
-#define  SDIO_CLKCR_WIDBUS_1                 0x1000U            /*!<Bit 1 */
-
-#define  SDIO_CLKCR_NEGEDGE                  0x2000U            /*!<SDIO_CK dephasing selection bit */
-#define  SDIO_CLKCR_HWFC_EN                  0x4000U            /*!<HW Flow Control enable          */
-
-/*******************  Bit definition for SDIO_ARG register  *******************/
-#define  SDIO_ARG_CMDARG                     0xFFFFFFFFU            /*!<Command argument */
-
-/*******************  Bit definition for SDIO_CMD register  *******************/
-#define  SDIO_CMD_CMDINDEX                   0x003FU            /*!<Command Index                               */
-
-#define  SDIO_CMD_WAITRESP                   0x00C0U            /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDIO_CMD_WAITRESP_0                 0x0040U            /*!< Bit 0 */
-#define  SDIO_CMD_WAITRESP_1                 0x0080U            /*!< Bit 1 */
-
-#define  SDIO_CMD_WAITINT                    0x0100U            /*!<CPSM Waits for Interrupt Request                               */
-#define  SDIO_CMD_WAITPEND                   0x0200U            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDIO_CMD_CPSMEN                     0x0400U            /*!<Command path state machine (CPSM) Enable bit                   */
-#define  SDIO_CMD_SDIOSUSPEND                0x0800U            /*!<SD I/O suspend command                                         */
-#define  SDIO_CMD_ENCMDCOMPL                 0x1000U            /*!<Enable CMD completion                                          */
-#define  SDIO_CMD_NIEN                       0x2000U            /*!<Not Interrupt Enable */
-#define  SDIO_CMD_CEATACMD                   0x4000U            /*!<CE-ATA command       */
-
-/*****************  Bit definition for SDIO_RESPCMD register  *****************/
-#define  SDIO_RESPCMD_RESPCMD                0x3FU               /*!<Response command index */
-
-/******************  Bit definition for SDIO_RESP0 register  ******************/
-#define  SDIO_RESP0_CARDSTATUS0              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP1 register  ******************/
-#define  SDIO_RESP1_CARDSTATUS1              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP2 register  ******************/
-#define  SDIO_RESP2_CARDSTATUS2              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP3 register  ******************/
-#define  SDIO_RESP3_CARDSTATUS3              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP4 register  ******************/
-#define  SDIO_RESP4_CARDSTATUS4              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_DTIMER register  *****************/
-#define  SDIO_DTIMER_DATATIME                0xFFFFFFFFU        /*!<Data timeout period. */
-
-/******************  Bit definition for SDIO_DLEN register  *******************/
-#define  SDIO_DLEN_DATALENGTH                0x01FFFFFFU        /*!<Data length value    */
-
-/******************  Bit definition for SDIO_DCTRL register  ******************/
-#define  SDIO_DCTRL_DTEN                     0x0001U            /*!<Data transfer enabled bit         */
-#define  SDIO_DCTRL_DTDIR                    0x0002U            /*!<Data transfer direction selection */
-#define  SDIO_DCTRL_DTMODE                   0x0004U            /*!<Data transfer mode selection      */
-#define  SDIO_DCTRL_DMAEN                    0x0008U            /*!<DMA enabled bit                   */
-
-#define  SDIO_DCTRL_DBLOCKSIZE               0x00F0U            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDIO_DCTRL_DBLOCKSIZE_0             0x0010U            /*!<Bit 0 */
-#define  SDIO_DCTRL_DBLOCKSIZE_1             0x0020U            /*!<Bit 1 */
-#define  SDIO_DCTRL_DBLOCKSIZE_2             0x0040U            /*!<Bit 2 */
-#define  SDIO_DCTRL_DBLOCKSIZE_3             0x0080U            /*!<Bit 3 */
-
-#define  SDIO_DCTRL_RWSTART                  0x0100U            /*!<Read wait start         */
-#define  SDIO_DCTRL_RWSTOP                   0x0200U            /*!<Read wait stop          */
-#define  SDIO_DCTRL_RWMOD                    0x0400U            /*!<Read wait mode          */
-#define  SDIO_DCTRL_SDIOEN                   0x0800U            /*!<SD I/O enable functions */
-
-/******************  Bit definition for SDIO_DCOUNT register  *****************/
-#define  SDIO_DCOUNT_DATACOUNT               0x01FFFFFFU        /*!<Data count value */
-
-/******************  Bit definition for SDIO_STA register  ********************/
-#define  SDIO_STA_CCRCFAIL                   0x00000001U        /*!<Command response received (CRC check failed)  */
-#define  SDIO_STA_DCRCFAIL                   0x00000002U        /*!<Data block sent/received (CRC check failed)   */
-#define  SDIO_STA_CTIMEOUT                   0x00000004U        /*!<Command response timeout                      */
-#define  SDIO_STA_DTIMEOUT                   0x00000008U        /*!<Data timeout                                  */
-#define  SDIO_STA_TXUNDERR                   0x00000010U        /*!<Transmit FIFO underrun error                  */
-#define  SDIO_STA_RXOVERR                    0x00000020U        /*!<Received FIFO overrun error                   */
-#define  SDIO_STA_CMDREND                    0x00000040U        /*!<Command response received (CRC check passed)  */
-#define  SDIO_STA_CMDSENT                    0x00000080U        /*!<Command sent (no response required)           */
-#define  SDIO_STA_DATAEND                    0x00000100U        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
-#define  SDIO_STA_STBITERR                   0x00000200U        /*!<Start bit not detected on all data signals in wide bus mode */
-#define  SDIO_STA_DBCKEND                    0x00000400U        /*!<Data block sent/received (CRC check passed)   */
-#define  SDIO_STA_CMDACT                     0x00000800U        /*!<Command transfer in progress                  */
-#define  SDIO_STA_TXACT                      0x00001000U        /*!<Data transmit in progress                     */
-#define  SDIO_STA_RXACT                      0x00002000U        /*!<Data receive in progress                      */
-#define  SDIO_STA_TXFIFOHE                   0x00004000U        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDIO_STA_RXFIFOHF                   0x00008000U        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDIO_STA_TXFIFOF                    0x00010000U        /*!<Transmit FIFO full                            */
-#define  SDIO_STA_RXFIFOF                    0x00020000U        /*!<Receive FIFO full                             */
-#define  SDIO_STA_TXFIFOE                    0x00040000U        /*!<Transmit FIFO empty                           */
-#define  SDIO_STA_RXFIFOE                    0x00080000U        /*!<Receive FIFO empty                            */
-#define  SDIO_STA_TXDAVL                     0x00100000U        /*!<Data available in transmit FIFO               */
-#define  SDIO_STA_RXDAVL                     0x00200000U        /*!<Data available in receive FIFO                */
-#define  SDIO_STA_SDIOIT                     0x00400000U        /*!<SDIO interrupt received                       */
-#define  SDIO_STA_CEATAEND                   0x00800000U        /*!<CE-ATA command completion signal received for CMD61 */
-
-/*******************  Bit definition for SDIO_ICR register  *******************/
-#define  SDIO_ICR_CCRCFAILC                  0x00000001U        /*!<CCRCFAIL flag clear bit */
-#define  SDIO_ICR_DCRCFAILC                  0x00000002U        /*!<DCRCFAIL flag clear bit */
-#define  SDIO_ICR_CTIMEOUTC                  0x00000004U        /*!<CTIMEOUT flag clear bit */
-#define  SDIO_ICR_DTIMEOUTC                  0x00000008U        /*!<DTIMEOUT flag clear bit */
-#define  SDIO_ICR_TXUNDERRC                  0x00000010U        /*!<TXUNDERR flag clear bit */
-#define  SDIO_ICR_RXOVERRC                   0x00000020U        /*!<RXOVERR flag clear bit  */
-#define  SDIO_ICR_CMDRENDC                   0x00000040U        /*!<CMDREND flag clear bit  */
-#define  SDIO_ICR_CMDSENTC                   0x00000080U        /*!<CMDSENT flag clear bit  */
-#define  SDIO_ICR_DATAENDC                   0x00000100U        /*!<DATAEND flag clear bit  */
-#define  SDIO_ICR_STBITERRC                  0x00000200U        /*!<STBITERR flag clear bit */
-#define  SDIO_ICR_DBCKENDC                   0x00000400U        /*!<DBCKEND flag clear bit  */
-#define  SDIO_ICR_SDIOITC                    0x00400000U        /*!<SDIOIT flag clear bit   */
-#define  SDIO_ICR_CEATAENDC                  0x00800000U        /*!<CEATAEND flag clear bit */
-
-/******************  Bit definition for SDIO_MASK register  *******************/
-#define  SDIO_MASK_CCRCFAILIE                0x00000001U        /*!<Command CRC Fail Interrupt Enable          */
-#define  SDIO_MASK_DCRCFAILIE                0x00000002U        /*!<Data CRC Fail Interrupt Enable             */
-#define  SDIO_MASK_CTIMEOUTIE                0x00000004U        /*!<Command TimeOut Interrupt Enable           */
-#define  SDIO_MASK_DTIMEOUTIE                0x00000008U        /*!<Data TimeOut Interrupt Enable              */
-#define  SDIO_MASK_TXUNDERRIE                0x00000010U        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
-#define  SDIO_MASK_RXOVERRIE                 0x00000020U        /*!<Rx FIFO OverRun Error Interrupt Enable     */
-#define  SDIO_MASK_CMDRENDIE                 0x00000040U        /*!<Command Response Received Interrupt Enable */
-#define  SDIO_MASK_CMDSENTIE                 0x00000080U        /*!<Command Sent Interrupt Enable              */
-#define  SDIO_MASK_DATAENDIE                 0x00000100U        /*!<Data End Interrupt Enable                  */
-#define  SDIO_MASK_STBITERRIE                0x00000200U        /*!<Start Bit Error Interrupt Enable           */
-#define  SDIO_MASK_DBCKENDIE                 0x00000400U        /*!<Data Block End Interrupt Enable            */
-#define  SDIO_MASK_CMDACTIE                  0x00000800U        /*!<CCommand Acting Interrupt Enable           */
-#define  SDIO_MASK_TXACTIE                   0x00001000U        /*!<Data Transmit Acting Interrupt Enable      */
-#define  SDIO_MASK_RXACTIE                   0x00002000U        /*!<Data receive acting interrupt enabled      */
-#define  SDIO_MASK_TXFIFOHEIE                0x00004000U        /*!<Tx FIFO Half Empty interrupt Enable        */
-#define  SDIO_MASK_RXFIFOHFIE                0x00008000U        /*!<Rx FIFO Half Full interrupt Enable         */
-#define  SDIO_MASK_TXFIFOFIE                 0x00010000U        /*!<Tx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_RXFIFOFIE                 0x00020000U        /*!<Rx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_TXFIFOEIE                 0x00040000U        /*!<Tx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_RXFIFOEIE                 0x00080000U        /*!<Rx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_TXDAVLIE                  0x00100000U        /*!<Data available in Tx FIFO interrupt Enable */
-#define  SDIO_MASK_RXDAVLIE                  0x00200000U        /*!<Data available in Rx FIFO interrupt Enable */
-#define  SDIO_MASK_SDIOITIE                  0x00400000U        /*!<SDIO Mode Interrupt Received interrupt Enable */
-#define  SDIO_MASK_CEATAENDIE                0x00800000U        /*!<CE-ATA command completion signal received Interrupt Enable */
-
-/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
-#define  SDIO_FIFOCNT_FIFOCOUNT              0x00FFFFFFU        /*!<Remaining number of words to be written to or read from the FIFO */
-
-/******************  Bit definition for SDIO_FIFO register  *******************/
-#define  SDIO_FIFO_FIFODATA                  0xFFFFFFFFU        /*!<Receive and transmit FIFO data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        0x00000001U            /*!<Clock Phase      */
-#define  SPI_CR1_CPOL                        0x00000002U            /*!<Clock Polarity   */
-#define  SPI_CR1_MSTR                        0x00000004U            /*!<Master Selection */
-
-#define  SPI_CR1_BR                          0x00000038U            /*!<BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        0x00000008U            /*!<Bit 0 */
-#define  SPI_CR1_BR_1                        0x00000010U            /*!<Bit 1 */
-#define  SPI_CR1_BR_2                        0x00000020U            /*!<Bit 2 */
-
-#define  SPI_CR1_SPE                         0x00000040U            /*!<SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    0x00000080U            /*!<Frame Format                        */
-#define  SPI_CR1_SSI                         0x00000100U            /*!<Internal slave select               */
-#define  SPI_CR1_SSM                         0x00000200U            /*!<Software slave management           */
-#define  SPI_CR1_RXONLY                      0x00000400U            /*!<Receive only                        */
-#define  SPI_CR1_DFF                         0x00000800U            /*!<Data Frame Format                   */
-#define  SPI_CR1_CRCNEXT                     0x00001000U            /*!<Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       0x00002000U            /*!<Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      0x00004000U            /*!<Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    0x00008000U            /*!<Bidirectional data mode enable      */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     0x00000001U               /*!<Rx Buffer DMA Enable                 */
-#define  SPI_CR2_TXDMAEN                     0x00000002U               /*!<Tx Buffer DMA Enable                 */
-#define  SPI_CR2_SSOE                        0x00000004U               /*!<SS Output Enable                     */
-#define  SPI_CR2_FRF                         0x00000010U               /*!<Frame Format                         */
-#define  SPI_CR2_ERRIE                       0x00000020U               /*!<Error Interrupt Enable               */
-#define  SPI_CR2_RXNEIE                      0x00000040U               /*!<RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       0x00000080U               /*!<Tx buffer Empty Interrupt Enable     */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         0x00000001U               /*!<Receive buffer Not Empty */
-#define  SPI_SR_TXE                          0x00000002U               /*!<Transmit buffer Empty    */
-#define  SPI_SR_CHSIDE                       0x00000004U               /*!<Channel side             */
-#define  SPI_SR_UDR                          0x00000008U               /*!<Underrun flag            */
-#define  SPI_SR_CRCERR                       0x00000010U               /*!<CRC Error flag           */
-#define  SPI_SR_MODF                         0x00000020U               /*!<Mode fault               */
-#define  SPI_SR_OVR                          0x00000040U               /*!<Overrun flag             */
-#define  SPI_SR_BSY                          0x00000080U               /*!<Busy flag                */
-#define  SPI_SR_FRE                          0x00000100U               /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           0x0000FFFFU            /*!<Data Register           */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   0x0000FFFFU            /*!<CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    0x0000FFFFU            /*!<Rx CRC Register         */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    0x0000FFFFU            /*!<Tx CRC Register         */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   0x00000001U            /*!<Channel length (number of bits per audio channel) */
-
-#define  SPI_I2SCFGR_DATLEN                  0x00000006U            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define  SPI_I2SCFGR_DATLEN_0                0x00000002U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                0x00000004U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_CKPOL                   0x00000008U            /*!<steady state clock polarity               */
-
-#define  SPI_I2SCFGR_I2SSTD                  0x00000030U            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U            /*!<PCM frame synchronization                 */
-
-#define  SPI_I2SCFGR_I2SCFG                  0x00000300U            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_I2SE                    0x00000400U            /*!<I2S Enable         */
-#define  SPI_I2SCFGR_I2SMOD                  0x00000800U            /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    0x000000FFU            /*!<I2S Linear prescaler         */
-#define  SPI_I2SPR_ODD                       0x00000100U            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     0x00000200U            /*!<Master Clock Output Enable   */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 SYSCFG                                     */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
-#define SYSCFG_MEMRMP_MEM_MODE          0x00000007U /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        0x00000001U
-#define SYSCFG_MEMRMP_MEM_MODE_1        0x00000002U
-#define SYSCFG_MEMRMP_MEM_MODE_2        0x00000004U
-
-#define SYSCFG_MEMRMP_UFB_MODE          0x00000100U /*!< User Flash Bank mode    */
-#define SYSCFG_SWP_FMC                  0x00000C00U /*!< FMC memory mapping swap */
-
-/******************  Bit definition for SYSCFG_PMC register  ******************/
-#define SYSCFG_PMC_ADCxDC2              0x00070000U /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC1DC2              0x00010000U /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC2DC2              0x00020000U /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC3DC2              0x00040000U /*!< Refer to AN4073 on how to use this bit  */
-
-#define SYSCFG_PMC_MII_RMII_SEL         0x00800000U /*!<Ethernet PHY interface selection */
-/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
-#define SYSCFG_PMC_MII_RMII             SYSCFG_PMC_MII_RMII_SEL
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
-/** 
-  * @brief   EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         0x0003U /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         0x0004U /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         0x0005U /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         0x0006U /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PI         0x0008U /*!<PI[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PJ         0x0009U /*!<PJ[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PK         0x000AU /*!<PK[0] pin */
-
-/** 
-  * @brief   EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         0x0030U /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         0x0040U /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         0x0050U /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         0x0060U /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PI         0x0080U /*!<PI[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PJ         0x0090U /*!<PJ[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PK         0x00A0U /*!<PK[1] pin */
-
-
-/** 
-  * @brief   EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         0x0300U /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         0x0400U /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         0x0500U /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         0x0600U /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PI         0x0800U /*!<PI[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PJ         0x0900U /*!<PJ[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PK         0x0A00U /*!<PK[2] pin */
-
-
-/** 
-  * @brief   EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         0x3000U /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         0x4000U /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         0x5000U /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         0x6000U /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PI         0x8000U /*!<PI[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PJ         0x9000U /*!<PJ[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PK         0xA000U /*!<PK[3] pin */
-
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
-/** 
-  * @brief   EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         0x0003U /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         0x0004U /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         0x0005U /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         0x0006U /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PI         0x0008U /*!<PI[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PJ         0x0009U /*!<PJ[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PK         0x000AU /*!<PK[4] pin */
-
-/** 
-  * @brief   EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         0x0030U /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         0x0040U /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         0x0050U /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         0x0060U /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PI         0x0080U /*!<PI[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PJ         0x0090U /*!<PJ[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PK         0x00A0U /*!<PK[5] pin */
-
-/** 
-  * @brief   EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         0x0300U /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         0x0400U /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         0x0500U /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         0x0600U /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PI         0x0800U /*!<PI[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PJ         0x0900U /*!<PJ[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PK         0x0A00U /*!<PK[6] pin */
-
-
-/** 
-  * @brief   EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         0x3000U /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         0x4000U /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         0x5000U /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         0x6000U /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PI         0x8000U /*!<PI[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PJ         0x9000U /*!<PJ[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PK         0xA000U /*!<PK[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
-           
-/** 
-  * @brief   EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         0x0003U /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         0x0004U /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         0x0005U /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         0x0006U /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PI         0x0008U /*!<PI[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PJ         0x0009U /*!<PJ[8] pin */
-
-/** 
-  * @brief   EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         0x0030U /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         0x0040U /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         0x0050U /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         0x0060U /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PI         0x0080U /*!<PI[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PJ         0x0090U /*!<PJ[9] pin */
-
-
-/** 
-  * @brief   EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        0x0300U /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        0x0400U /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        0x0500U /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        0x0600U /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PI        0x0800U /*!<PI[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PJ        0x0900U /*!<PJ[10] pin */
-
-
-/** 
-  * @brief   EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        0x3000U /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        0x4000U /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        0x5000U /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        0x6000U /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PI        0x8000U /*!<PI[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PJ        0x9000U /*!<PJ[11] pin */
-
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
-/** 
-  * @brief   EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        0x0003U /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        0x0004U /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        0x0005U /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        0x0006U /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PI        0x0008U /*!<PI[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PJ        0x0009U /*!<PJ[12] pin */
-
-
-/** 
-  * @brief   EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        0x0030U /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        0x0040U /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        0x0050U /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        0x0060U /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PI        0x0008U /*!<PI[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PJ        0x0009U /*!<PJ[13] pin */
-
-
-/** 
-  * @brief   EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        0x0300U /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        0x0400U /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        0x0500U /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        0x0600U /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PI        0x0800U /*!<PI[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PJ        0x0900U /*!<PJ[14] pin */
-
-
-/** 
-  * @brief   EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        0x3000U /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        0x4000U /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        0x5000U /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        0x6000U /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PI        0x8000U /*!<PI[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PJ        0x9000U /*!<PJ[15] pin */
-
-/******************  Bit definition for SYSCFG_CMPCR register  ****************/  
-#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell ready flag */
-#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell power-down */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    TIM                                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
-#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
-#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
-#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
-#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
-
-#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
-
-#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
-
-#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        0x0001U            /*!<Capture/Compare Preloaded Control        */
-#define  TIM_CR2_CCUS                        0x0004U            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        0x0008U            /*!<Capture/Compare DMA Selection            */
-
-#define  TIM_CR2_MMS                         0x0070U            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
-#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
-#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
-#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        0x0007U            /*!<SMS[2:0] bits (Slave mode selection)    */
-#define  TIM_SMCR_SMS_0                      0x0001U            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      0x0002U            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      0x0004U            /*!<Bit 2 */
-
-#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
-#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
-
-#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
-
-#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
-
-#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
-#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
-#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
-#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
-#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
-#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
-#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
-#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
-#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
-#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
-#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
-#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
-#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
-#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
-#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
-#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
-#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
-#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
-#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          0x01U               /*!<Update Generation                         */
-#define  TIM_EGR_CC1G                        0x02U               /*!<Capture/Compare 1 Generation              */
-#define  TIM_EGR_CC2G                        0x04U               /*!<Capture/Compare 2 Generation              */
-#define  TIM_EGR_CC3G                        0x08U               /*!<Capture/Compare 3 Generation              */
-#define  TIM_EGR_CC4G                        0x10U               /*!<Capture/Compare 4 Generation              */
-#define  TIM_EGR_COMG                        0x20U               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          0x40U               /*!<Trigger Generation                        */
-#define  TIM_EGR_BG                          0x80U               /*!<Break Generation                          */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      0x0003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    0x0001U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    0x0002U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC1FE                     0x0004U            /*!<Output Compare 1 Fast enable                 */
-#define  TIM_CCMR1_OC1PE                     0x0008U            /*!<Output Compare 1 Preload enable              */
-
-#define  TIM_CCMR1_OC1M                      0x0070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define  TIM_CCMR1_OC1M_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    0x0040U            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC1CE                     0x0080U            /*!<Output Compare 1Clear Enable                 */
-
-#define  TIM_CCMR1_CC2S                      0x0300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    0x0100U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    0x0200U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC2FE                     0x0400U            /*!<Output Compare 2 Fast enable                 */
-#define  TIM_CCMR1_OC2PE                     0x0800U            /*!<Output Compare 2 Preload enable              */
-
-#define  TIM_CCMR1_OC2M                      0x7000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define  TIM_CCMR1_OC2M_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    0x4000U            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC2CE                     0x8000U            /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      0x0003U            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define  TIM_CCMR2_CC3S_0                    0x0001U            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    0x0002U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC3FE                     0x0004U            /*!<Output Compare 3 Fast enable           */
-#define  TIM_CCMR2_OC3PE                     0x0008U            /*!<Output Compare 3 Preload enable        */
-
-#define  TIM_CCMR2_OC3M                      0x0070U            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    0x0040U            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC3CE                     0x0080U            /*!<Output Compare 3 Clear Enable */
-
-#define  TIM_CCMR2_CC4S                      0x0300U            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    0x0100U            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    0x0200U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC4FE                     0x0400U            /*!<Output Compare 4 Fast enable    */
-#define  TIM_CCMR2_OC4PE                     0x0800U            /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR2_OC4M                      0x7000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    0x4000U            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       0x0001U            /*!<Capture/Compare 1 output enable                 */
-#define  TIM_CCER_CC1P                       0x0002U            /*!<Capture/Compare 1 output Polarity               */
-#define  TIM_CCER_CC1NE                      0x0004U            /*!<Capture/Compare 1 Complementary output enable   */
-#define  TIM_CCER_CC1NP                      0x0008U            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       0x0010U            /*!<Capture/Compare 2 output enable                 */
-#define  TIM_CCER_CC2P                       0x0020U            /*!<Capture/Compare 2 output Polarity               */
-#define  TIM_CCER_CC2NE                      0x0040U            /*!<Capture/Compare 2 Complementary output enable   */
-#define  TIM_CCER_CC2NP                      0x0080U            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       0x0100U            /*!<Capture/Compare 3 output enable                 */
-#define  TIM_CCER_CC3P                       0x0200U            /*!<Capture/Compare 3 output Polarity               */
-#define  TIM_CCER_CC3NE                      0x0400U            /*!<Capture/Compare 3 Complementary output enable   */
-#define  TIM_CCER_CC3NP                      0x0800U            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       0x1000U            /*!<Capture/Compare 4 output enable                 */
-#define  TIM_CCER_CC4P                       0x2000U            /*!<Capture/Compare 4 output Polarity               */
-#define  TIM_CCER_CC4NP                      0x8000U            /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         0xFFU               /*!<Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
-
-/*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        0x00FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      0x0001U            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      0x0002U            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      0x0004U            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      0x0008U            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      0x0010U            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      0x0020U            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      0x0040U            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      0x0080U            /*!<Bit 7 */
-
-#define  TIM_BDTR_LOCK                       0x0300U            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     0x0100U            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     0x0200U            /*!<Bit 1 */
-
-#define  TIM_BDTR_OSSI                       0x0400U            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       0x0800U            /*!<Off-State Selection for Run mode  */
-#define  TIM_BDTR_BKE                        0x1000U            /*!<Break enable                      */
-#define  TIM_BDTR_BKP                        0x2000U            /*!<Break Polarity                    */
-#define  TIM_BDTR_AOE                        0x4000U            /*!<Automatic Output enable           */
-#define  TIM_BDTR_MOE                        0x8000U            /*!<Main Output enable                */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
-
-#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
-#define TIM_OR_ITR1_RMP                      0x0C00U            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
-#define TIM_OR_ITR1_RMP_0                    0x0400U            /*!<Bit 0 */
-#define TIM_OR_ITR1_RMP_1                    0x0800U            /*!<Bit 1 */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*         Universal Synchronous Asynchronous Receiver Transmitter            */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         0x0001U            /*!<Parity Error                 */
-#define  USART_SR_FE                         0x0002U            /*!<Framing Error                */
-#define  USART_SR_NE                         0x0004U            /*!<Noise Error Flag             */
-#define  USART_SR_ORE                        0x0008U            /*!<OverRun Error                */
-#define  USART_SR_IDLE                       0x0010U            /*!<IDLE line detected           */
-#define  USART_SR_RXNE                       0x0020U            /*!<Read Data Register Not Empty */
-#define  USART_SR_TC                         0x0040U            /*!<Transmission Complete        */
-#define  USART_SR_TXE                        0x0080U            /*!<Transmit Data Register Empty */
-#define  USART_SR_LBD                        0x0100U            /*!<LIN Break Detection Flag     */
-#define  USART_SR_CTS                        0x0200U            /*!<CTS Flag                     */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         0x01FFU            /*!<Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_Fraction              0x000FU            /*!<Fraction of USARTDIV */
-#define  USART_BRR_DIV_Mantissa              0xFFF0U            /*!<Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       0x0001U            /*!<Send Break                             */
-#define  USART_CR1_RWU                       0x0002U            /*!<Receiver wakeup                        */
-#define  USART_CR1_RE                        0x0004U            /*!<Receiver Enable                        */
-#define  USART_CR1_TE                        0x0008U            /*!<Transmitter Enable                     */
-#define  USART_CR1_IDLEIE                    0x0010U            /*!<IDLE Interrupt Enable                  */
-#define  USART_CR1_RXNEIE                    0x0020U            /*!<RXNE Interrupt Enable                  */
-#define  USART_CR1_TCIE                      0x0040U            /*!<Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     0x0080U            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PEIE                      0x0100U            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PS                        0x0200U            /*!<Parity Selection                       */
-#define  USART_CR1_PCE                       0x0400U            /*!<Parity Control Enable                  */
-#define  USART_CR1_WAKE                      0x0800U            /*!<Wakeup method                          */
-#define  USART_CR1_M                         0x1000U            /*!<Word length                            */
-#define  USART_CR1_UE                        0x2000U            /*!<USART Enable                           */
-#define  USART_CR1_OVER8                     0x8000U            /*!<USART Oversampling by 8 enable         */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       0x000FU            /*!<Address of the USART node            */
-#define  USART_CR2_LBDL                      0x0020U            /*!<LIN Break Detection Length           */
-#define  USART_CR2_LBDIE                     0x0040U            /*!<LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      0x0100U            /*!<Last Bit Clock pulse                 */
-#define  USART_CR2_CPHA                      0x0200U            /*!<Clock Phase                          */
-#define  USART_CR2_CPOL                      0x0400U            /*!<Clock Polarity                       */
-#define  USART_CR2_CLKEN                     0x0800U            /*!<Clock Enable                         */
-
-#define  USART_CR2_STOP                      0x3000U            /*!<STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    0x1000U            /*!<Bit 0 */
-#define  USART_CR2_STOP_1                    0x2000U            /*!<Bit 1 */
-
-#define  USART_CR2_LINEN                     0x4000U            /*!<LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       0x0001U            /*!<Error Interrupt Enable      */
-#define  USART_CR3_IREN                      0x0002U            /*!<IrDA mode Enable            */
-#define  USART_CR3_IRLP                      0x0004U            /*!<IrDA Low-Power              */
-#define  USART_CR3_HDSEL                     0x0008U            /*!<Half-Duplex Selection       */
-#define  USART_CR3_NACK                      0x0010U            /*!<Smartcard NACK enable       */
-#define  USART_CR3_SCEN                      0x0020U            /*!<Smartcard mode enable       */
-#define  USART_CR3_DMAR                      0x0040U            /*!<DMA Enable Receiver         */
-#define  USART_CR3_DMAT                      0x0080U            /*!<DMA Enable Transmitter      */
-#define  USART_CR3_RTSE                      0x0100U            /*!<RTS Enable                  */
-#define  USART_CR3_CTSE                      0x0200U            /*!<CTS Enable                  */
-#define  USART_CR3_CTSIE                     0x0400U            /*!<CTS Interrupt Enable        */
-#define  USART_CR3_ONEBIT                    0x0800U            /*!<USART One bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      0x00FFU            /*!<PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    0x0001U            /*!<Bit 0 */
-#define  USART_GTPR_PSC_1                    0x0002U            /*!<Bit 1 */
-#define  USART_GTPR_PSC_2                    0x0004U            /*!<Bit 2 */
-#define  USART_GTPR_PSC_3                    0x0008U            /*!<Bit 3 */
-#define  USART_GTPR_PSC_4                    0x0010U            /*!<Bit 4 */
-#define  USART_GTPR_PSC_5                    0x0020U            /*!<Bit 5 */
-#define  USART_GTPR_PSC_6                    0x0040U            /*!<Bit 6 */
-#define  USART_GTPR_PSC_7                    0x0080U            /*!<Bit 7 */
-
-#define  USART_GTPR_GT                       0xFF00U            /*!<Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Window WATCHDOG                                 */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           0x7FU               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T_0                         0x01U               /*!<Bit 0 */
-#define  WWDG_CR_T_1                         0x02U               /*!<Bit 1 */
-#define  WWDG_CR_T_2                         0x04U               /*!<Bit 2 */
-#define  WWDG_CR_T_3                         0x08U               /*!<Bit 3 */
-#define  WWDG_CR_T_4                         0x10U               /*!<Bit 4 */
-#define  WWDG_CR_T_5                         0x20U               /*!<Bit 5 */
-#define  WWDG_CR_T_6                         0x40U               /*!<Bit 6 */
-/* Legacy defines */
-#define  WWDG_CR_T0                          WWDG_CR_T_0
-#define  WWDG_CR_T1                          WWDG_CR_T_1
-#define  WWDG_CR_T2                          WWDG_CR_T_2
-#define  WWDG_CR_T3                          WWDG_CR_T_3
-#define  WWDG_CR_T4                          WWDG_CR_T_4
-#define  WWDG_CR_T5                          WWDG_CR_T_5
-#define  WWDG_CR_T6                          WWDG_CR_T_6
-
-#define  WWDG_CR_WDGA                        0x80U               /*!<Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          0x007FU            /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W_0                        0x0001U            /*!<Bit 0 */
-#define  WWDG_CFR_W_1                        0x0002U            /*!<Bit 1 */
-#define  WWDG_CFR_W_2                        0x0004U            /*!<Bit 2 */
-#define  WWDG_CFR_W_3                        0x0008U            /*!<Bit 3 */
-#define  WWDG_CFR_W_4                        0x0010U            /*!<Bit 4 */
-#define  WWDG_CFR_W_5                        0x0020U            /*!<Bit 5 */
-#define  WWDG_CFR_W_6                        0x0040U            /*!<Bit 6 */
-/* Legacy defines */
-#define  WWDG_CFR_W0                         WWDG_CFR_W_0
-#define  WWDG_CFR_W1                         WWDG_CFR_W_1
-#define  WWDG_CFR_W2                         WWDG_CFR_W_2
-#define  WWDG_CFR_W3                         WWDG_CFR_W_3
-#define  WWDG_CFR_W4                         WWDG_CFR_W_4
-#define  WWDG_CFR_W5                         WWDG_CFR_W_5
-#define  WWDG_CFR_W6                         WWDG_CFR_W_6
-
-#define  WWDG_CFR_WDGTB                      0x0180U            /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB_0                    0x0080U            /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB_1                    0x0100U            /*!<Bit 1 */
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
-
-#define  WWDG_CFR_EWI                        0x0200U            /*!<Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        0x01U               /*!<Early Wakeup Interrupt Flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                DBG                                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
-#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
-
-/********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
-#define  DBGMCU_CR_DBG_STOP                  0x00000002U
-#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
-#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
-
-#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
-#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U/*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U/*!<Bit 1 */
-
-/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            0x00000001U
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            0x00000002U
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            0x00000004U
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            0x00000020U
-#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           0x00000040U
-#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           0x00000080U
-#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           0x00000100U
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
-#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
-/* Old IWDGSTOP bit definition, maintained for legacy purpose */
-#define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
-
-/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        0x00000001U
-#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        0x00000002U
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        0x00010000U
-#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       0x00020000U
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       0x00040000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                Ethernet MAC Registers bits definitions                     */
-/*                                                                            */
-/******************************************************************************/
-/* Bit definition for Ethernet MAC Control Register register */
-#define ETH_MACCR_WD      0x00800000U  /* Watchdog disable */
-#define ETH_MACCR_JD      0x00400000U  /* Jabber disable */
-#define ETH_MACCR_IFG     0x000E0000U  /* Inter-frame gap */
-#define ETH_MACCR_IFG_96Bit     0x00000000U  /* Minimum IFG between frames during transmission is 96Bit */
-  #define ETH_MACCR_IFG_88Bit     0x00020000U  /* Minimum IFG between frames during transmission is 88Bit */
-  #define ETH_MACCR_IFG_80Bit     0x00040000U  /* Minimum IFG between frames during transmission is 80Bit */
-  #define ETH_MACCR_IFG_72Bit     0x00060000U  /* Minimum IFG between frames during transmission is 72Bit */
-  #define ETH_MACCR_IFG_64Bit     0x00080000U  /* Minimum IFG between frames during transmission is 64Bit */        
-  #define ETH_MACCR_IFG_56Bit     0x000A0000U  /* Minimum IFG between frames during transmission is 56Bit */
-  #define ETH_MACCR_IFG_48Bit     0x000C0000U  /* Minimum IFG between frames during transmission is 48Bit */
-  #define ETH_MACCR_IFG_40Bit     0x000E0000U  /* Minimum IFG between frames during transmission is 40Bit */              
-#define ETH_MACCR_CSD     0x00010000U  /* Carrier sense disable (during transmission) */
-#define ETH_MACCR_FES     0x00004000U  /* Fast ethernet speed */
-#define ETH_MACCR_ROD     0x00002000U  /* Receive own disable */
-#define ETH_MACCR_LM      0x00001000U  /* loopback mode */
-#define ETH_MACCR_DM      0x00000800U  /* Duplex mode */
-#define ETH_MACCR_IPCO    0x00000400U  /* IP Checksum offload */
-#define ETH_MACCR_RD      0x00000200U  /* Retry disable */
-#define ETH_MACCR_APCS    0x00000080U  /* Automatic Pad/CRC stripping */
-#define ETH_MACCR_BL      0x00000060U  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
-                                                       a transmission attempt during retries after a collision: 0 =< r <2^k */
-  #define ETH_MACCR_BL_10    0x00000000U  /* k = min (n, 10) */
-  #define ETH_MACCR_BL_8     0x00000020U  /* k = min (n, 8) */
-  #define ETH_MACCR_BL_4     0x00000040U  /* k = min (n, 4) */
-  #define ETH_MACCR_BL_1     0x00000060U  /* k = min (n, 1) */ 
-#define ETH_MACCR_DC      0x00000010U  /* Defferal check */
-#define ETH_MACCR_TE      0x00000008U  /* Transmitter enable */
-#define ETH_MACCR_RE      0x00000004U  /* Receiver enable */
-
-/* Bit definition for Ethernet MAC Frame Filter Register */
-#define ETH_MACFFR_RA     0x80000000U  /* Receive all */ 
-#define ETH_MACFFR_HPF    0x00000400U  /* Hash or perfect filter */ 
-#define ETH_MACFFR_SAF    0x00000200U  /* Source address filter enable */ 
-#define ETH_MACFFR_SAIF   0x00000100U  /* SA inverse filtering */ 
-#define ETH_MACFFR_PCF    0x000000C0U  /* Pass control frames: 3 cases */
-  #define ETH_MACFFR_PCF_BlockAll                0x00000040U  /* MAC filters all control frames from reaching the application */
-  #define ETH_MACFFR_PCF_ForwardAll              0x00000080U  /* MAC forwards all control frames to application even if they fail the Address Filter */
-  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U  /* MAC forwards control frames that pass the Address Filter. */ 
-#define ETH_MACFFR_BFD    0x00000020U  /* Broadcast frame disable */ 
-#define ETH_MACFFR_PAM    0x00000010U  /* Pass all mutlicast */ 
-#define ETH_MACFFR_DAIF   0x00000008U  /* DA Inverse filtering */ 
-#define ETH_MACFFR_HM     0x00000004U  /* Hash multicast */ 
-#define ETH_MACFFR_HU     0x00000002U  /* Hash unicast */
-#define ETH_MACFFR_PM     0x00000001U  /* Promiscuous mode */
-
-/* Bit definition for Ethernet MAC Hash Table High Register */
-#define ETH_MACHTHR_HTH   0xFFFFFFFFU  /* Hash table high */
-
-/* Bit definition for Ethernet MAC Hash Table Low Register */
-#define ETH_MACHTLR_HTL   0xFFFFFFFFU  /* Hash table low */
-
-/* Bit definition for Ethernet MAC MII Address Register */
-#define ETH_MACMIIAR_PA   0x0000F800U  /* Physical layer address */ 
-#define ETH_MACMIIAR_MR   0x000007C0U  /* MII register in the selected PHY */ 
-#define ETH_MACMIIAR_CR   0x0000001CU  /* CR clock range: 6 cases */ 
-  #define ETH_MACMIIAR_CR_Div42   0x00000000U  /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
-  #define ETH_MACMIIAR_CR_Div62   0x00000004U  /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
-  #define ETH_MACMIIAR_CR_Div16   0x00000008U  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
-  #define ETH_MACMIIAR_CR_Div26   0x0000000CU  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
-  #define ETH_MACMIIAR_CR_Div102  0x00000010U  /* HCLK:150-168 MHz; MDC clock= HCLK/102 */  
-#define ETH_MACMIIAR_MW   0x00000002U  /* MII write */ 
-#define ETH_MACMIIAR_MB   0x00000001U  /* MII busy */ 
-  
-/* Bit definition for Ethernet MAC MII Data Register */
-#define ETH_MACMIIDR_MD   0x0000FFFFU  /* MII data: read/write data from/to PHY */
-
-/* Bit definition for Ethernet MAC Flow Control Register */
-#define ETH_MACFCR_PT     0xFFFF0000U  /* Pause time */
-#define ETH_MACFCR_ZQPD   0x00000080U  /* Zero-quanta pause disable */
-#define ETH_MACFCR_PLT    0x00000030U  /* Pause low threshold: 4 cases */
-  #define ETH_MACFCR_PLT_Minus4   0x00000000U  /* Pause time minus 4 slot times */
-  #define ETH_MACFCR_PLT_Minus28  0x00000010U  /* Pause time minus 28 slot times */
-  #define ETH_MACFCR_PLT_Minus144 0x00000020U  /* Pause time minus 144 slot times */
-  #define ETH_MACFCR_PLT_Minus256 0x00000030U  /* Pause time minus 256 slot times */      
-#define ETH_MACFCR_UPFD   0x00000008U  /* Unicast pause frame detect */
-#define ETH_MACFCR_RFCE   0x00000004U  /* Receive flow control enable */
-#define ETH_MACFCR_TFCE   0x00000002U  /* Transmit flow control enable */
-#define ETH_MACFCR_FCBBPA 0x00000001U  /* Flow control busy/backpressure activate */
-
-/* Bit definition for Ethernet MAC VLAN Tag Register */
-#define ETH_MACVLANTR_VLANTC 0x00010000U  /* 12-bit VLAN tag comparison */
-#define ETH_MACVLANTR_VLANTI 0x0000FFFFU  /* VLAN tag identifier (for receive frames) */
-
-/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ 
-#define ETH_MACRWUFFR_D   0xFFFFFFFFU  /* Wake-up frame filter register data */
-/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
-   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
-/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
-   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
-   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
-   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
-   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - 
-                              RSVD - Filter1 Command - RSVD - Filter0 Command
-   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
-   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
-   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
-
-/* Bit definition for Ethernet MAC PMT Control and Status Register */ 
-#define ETH_MACPMTCSR_WFFRPR 0x80000000U  /* Wake-Up Frame Filter Register Pointer Reset */
-#define ETH_MACPMTCSR_GU     0x00000200U  /* Global Unicast */
-#define ETH_MACPMTCSR_WFR    0x00000040U  /* Wake-Up Frame Received */
-#define ETH_MACPMTCSR_MPR    0x00000020U  /* Magic Packet Received */
-#define ETH_MACPMTCSR_WFE    0x00000004U  /* Wake-Up Frame Enable */
-#define ETH_MACPMTCSR_MPE    0x00000002U  /* Magic Packet Enable */
-#define ETH_MACPMTCSR_PD     0x00000001U  /* Power Down */
-
-/* Bit definition for Ethernet MAC Status Register */
-#define ETH_MACSR_TSTS      0x00000200U  /* Time stamp trigger status */
-#define ETH_MACSR_MMCTS     0x00000040U  /* MMC transmit status */
-#define ETH_MACSR_MMMCRS    0x00000020U  /* MMC receive status */
-#define ETH_MACSR_MMCS      0x00000010U  /* MMC status */
-#define ETH_MACSR_PMTS      0x00000008U  /* PMT status */
-
-/* Bit definition for Ethernet MAC Interrupt Mask Register */
-#define ETH_MACIMR_TSTIM     0x00000200U  /* Time stamp trigger interrupt mask */
-#define ETH_MACIMR_PMTIM     0x00000008U  /* PMT interrupt mask */
-
-/* Bit definition for Ethernet MAC Address0 High Register */
-#define ETH_MACA0HR_MACA0H   0x0000FFFFU  /* MAC address0 high */
-
-/* Bit definition for Ethernet MAC Address0 Low Register */
-#define ETH_MACA0LR_MACA0L   0xFFFFFFFFU  /* MAC address0 low */
-
-/* Bit definition for Ethernet MAC Address1 High Register */
-#define ETH_MACA1HR_AE       0x80000000U  /* Address enable */
-#define ETH_MACA1HR_SA       0x40000000U  /* Source address */
-#define ETH_MACA1HR_MBC      0x3F000000U  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
-  #define ETH_MACA1HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA1HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA1HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA1HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA1HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA1HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [7:0] */ 
-#define ETH_MACA1HR_MACA1H   0x0000FFFFU  /* MAC address1 high */
-
-/* Bit definition for Ethernet MAC Address1 Low Register */
-#define ETH_MACA1LR_MACA1L   0xFFFFFFFFU  /* MAC address1 low */
-
-/* Bit definition for Ethernet MAC Address2 High Register */
-#define ETH_MACA2HR_AE       0x80000000U  /* Address enable */
-#define ETH_MACA2HR_SA       0x40000000U  /* Source address */
-#define ETH_MACA2HR_MBC      0x3F000000U  /* Mask byte control */
-  #define ETH_MACA2HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA2HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA2HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA2HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA2HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA2HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA2HR_MACA2H   0x0000FFFFU  /* MAC address1 high */
-
-/* Bit definition for Ethernet MAC Address2 Low Register */
-#define ETH_MACA2LR_MACA2L   0xFFFFFFFFU  /* MAC address2 low */
-
-/* Bit definition for Ethernet MAC Address3 High Register */
-#define ETH_MACA3HR_AE       0x80000000U  /* Address enable */
-#define ETH_MACA3HR_SA       0x40000000U  /* Source address */
-#define ETH_MACA3HR_MBC      0x3F000000U  /* Mask byte control */
-  #define ETH_MACA3HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA3HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA3HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA3HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA3HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA3HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA3HR_MACA3H   0x0000FFFFU  /* MAC address3 high */
-
-/* Bit definition for Ethernet MAC Address3 Low Register */
-#define ETH_MACA3LR_MACA3L   0xFFFFFFFFU  /* MAC address3 low */
-
-/******************************************************************************/
-/*                Ethernet MMC Registers bits definition                      */
-/******************************************************************************/
-
-/* Bit definition for Ethernet MMC Contol Register */
-#define ETH_MMCCR_MCFHP      0x00000020U  /* MMC counter Full-Half preset */
-#define ETH_MMCCR_MCP        0x00000010U  /* MMC counter preset */
-#define ETH_MMCCR_MCF        0x00000008U  /* MMC Counter Freeze */
-#define ETH_MMCCR_ROR        0x00000004U  /* Reset on Read */
-#define ETH_MMCCR_CSR        0x00000002U  /* Counter Stop Rollover */
-#define ETH_MMCCR_CR         0x00000001U  /* Counters Reset */
-
-/* Bit definition for Ethernet MMC Receive Interrupt Register */
-#define ETH_MMCRIR_RGUFS     0x00020000U  /* Set when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIR_RFAES     0x00000040U  /* Set when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIR_RFCES     0x00000020U  /* Set when Rx crc error counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmit Interrupt Register */
-#define ETH_MMCTIR_TGFS      0x00200000U  /* Set when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFMSCS   0x00008000U  /* Set when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFSCS    0x00004000U  /* Set when Tx good single col counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
-#define ETH_MMCRIMR_RGUFM    0x00020000U  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFAEM    0x00000040U  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFCEM    0x00000020U  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
-#define ETH_MMCTIMR_TGFM     0x00200000U  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFMSCM  0x00008000U  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFSCM   0x00004000U  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
-#define ETH_MMCTGFSCCR_TGFSCC     0xFFFFFFFFU  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
-#define ETH_MMCTGFMSCCR_TGFMSCC   0xFFFFFFFFU  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
-#define ETH_MMCTGFCR_TGFC    0xFFFFFFFFU  /* Number of good frames transmitted. */
-
-/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
-#define ETH_MMCRFCECR_RFCEC  0xFFFFFFFFU  /* Number of frames received with CRC error. */
-
-/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
-#define ETH_MMCRFAECR_RFAEC  0xFFFFFFFFU  /* Number of frames received with alignment (dribble) error */
-
-/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
-#define ETH_MMCRGUFCR_RGUFC  0xFFFFFFFFU  /* Number of good unicast frames received. */
-
-/******************************************************************************/
-/*               Ethernet PTP Registers bits definition                       */
-/******************************************************************************/
-
-/* Bit definition for Ethernet PTP Time Stamp Contol Register */
-#define ETH_PTPTSCR_TSCNT       0x00030000U  /* Time stamp clock node type */
-#define ETH_PTPTSSR_TSSMRME     0x00008000U  /* Time stamp snapshot for message relevant to master enable */
-#define ETH_PTPTSSR_TSSEME      0x00004000U  /* Time stamp snapshot for event message enable */
-#define ETH_PTPTSSR_TSSIPV4FE   0x00002000U  /* Time stamp snapshot for IPv4 frames enable */
-#define ETH_PTPTSSR_TSSIPV6FE   0x00001000U  /* Time stamp snapshot for IPv6 frames enable */
-#define ETH_PTPTSSR_TSSPTPOEFE  0x00000800U  /* Time stamp snapshot for PTP over ethernet frames enable */
-#define ETH_PTPTSSR_TSPTPPSV2E  0x00000400U  /* Time stamp PTP packet snooping for version2 format enable */
-#define ETH_PTPTSSR_TSSSR       0x00000200U  /* Time stamp Sub-seconds rollover */
-#define ETH_PTPTSSR_TSSARFE     0x00000100U  /* Time stamp snapshot for all received frames enable */
-
-#define ETH_PTPTSCR_TSARU    0x00000020U  /* Addend register update */
-#define ETH_PTPTSCR_TSITE    0x00000010U  /* Time stamp interrupt trigger enable */
-#define ETH_PTPTSCR_TSSTU    0x00000008U  /* Time stamp update */
-#define ETH_PTPTSCR_TSSTI    0x00000004U  /* Time stamp initialize */
-#define ETH_PTPTSCR_TSFCU    0x00000002U  /* Time stamp fine or coarse update */
-#define ETH_PTPTSCR_TSE      0x00000001U  /* Time stamp enable */
-
-/* Bit definition for Ethernet PTP Sub-Second Increment Register */
-#define ETH_PTPSSIR_STSSI    0x000000FFU  /* System time Sub-second increment value */
-
-/* Bit definition for Ethernet PTP Time Stamp High Register */
-#define ETH_PTPTSHR_STS      0xFFFFFFFFU  /* System Time second */
-
-/* Bit definition for Ethernet PTP Time Stamp Low Register */
-#define ETH_PTPTSLR_STPNS    0x80000000U  /* System Time Positive or negative time */
-#define ETH_PTPTSLR_STSS     0x7FFFFFFFU  /* System Time sub-seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp High Update Register */
-#define ETH_PTPTSHUR_TSUS    0xFFFFFFFFU  /* Time stamp update seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
-#define ETH_PTPTSLUR_TSUPNS  0x80000000U  /* Time stamp update Positive or negative time */
-#define ETH_PTPTSLUR_TSUSS   0x7FFFFFFFU  /* Time stamp update sub-seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp Addend Register */
-#define ETH_PTPTSAR_TSA      0xFFFFFFFFU  /* Time stamp addend */
-
-/* Bit definition for Ethernet PTP Target Time High Register */
-#define ETH_PTPTTHR_TTSH     0xFFFFFFFFU  /* Target time stamp high */
-
-/* Bit definition for Ethernet PTP Target Time Low Register */
-#define ETH_PTPTTLR_TTSL     0xFFFFFFFFU  /* Target time stamp low */
-
-/* Bit definition for Ethernet PTP Time Stamp Status Register */
-#define ETH_PTPTSSR_TSTTR    0x00000020U  /* Time stamp target time reached */
-#define ETH_PTPTSSR_TSSO     0x00000010U  /* Time stamp seconds overflow */
-
-/******************************************************************************/
-/*                 Ethernet DMA Registers bits definition                     */
-/******************************************************************************/
-
-/* Bit definition for Ethernet DMA Bus Mode Register */
-#define ETH_DMABMR_AAB       0x02000000U  /* Address-Aligned beats */
-#define ETH_DMABMR_FPM        0x01000000U  /* 4xPBL mode */
-#define ETH_DMABMR_USP       0x00800000U  /* Use separate PBL */
-#define ETH_DMABMR_RDP       0x007E0000U  /* RxDMA PBL */
-  #define ETH_DMABMR_RDP_1Beat    0x00020000U  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
-  #define ETH_DMABMR_RDP_2Beat    0x00040000U  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
-  #define ETH_DMABMR_RDP_4Beat    0x00080000U  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-  #define ETH_DMABMR_RDP_8Beat    0x00100000U  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-  #define ETH_DMABMR_RDP_16Beat   0x00200000U  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-  #define ETH_DMABMR_RDP_32Beat   0x00400000U  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */                
-  #define ETH_DMABMR_RDP_4xPBL_4Beat   0x01020000U  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-  #define ETH_DMABMR_RDP_4xPBL_8Beat   0x01040000U  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-  #define ETH_DMABMR_RDP_4xPBL_16Beat  0x01080000U  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-  #define ETH_DMABMR_RDP_4xPBL_32Beat  0x01100000U  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
-  #define ETH_DMABMR_RDP_4xPBL_64Beat  0x01200000U  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
-  #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */  
-#define ETH_DMABMR_FB        0x00010000U  /* Fixed Burst */
-#define ETH_DMABMR_RTPR      0x0000C000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_1_1     0x00000000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_2_1     0x00004000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_3_1     0x00008000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_4_1     0x0000C000U  /* Rx Tx priority ratio */  
-#define ETH_DMABMR_PBL    0x00003F00U  /* Programmable burst length */
-  #define ETH_DMABMR_PBL_1Beat    0x00000100U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
-  #define ETH_DMABMR_PBL_2Beat    0x00000200U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
-  #define ETH_DMABMR_PBL_4Beat    0x00000400U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-  #define ETH_DMABMR_PBL_8Beat    0x00000800U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-  #define ETH_DMABMR_PBL_16Beat   0x00001000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-  #define ETH_DMABMR_PBL_32Beat   0x00002000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
-  #define ETH_DMABMR_PBL_4xPBL_4Beat   0x01000100U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-  #define ETH_DMABMR_PBL_4xPBL_8Beat   0x01000200U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-  #define ETH_DMABMR_PBL_4xPBL_16Beat  0x01000400U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-  #define ETH_DMABMR_PBL_4xPBL_32Beat  0x01000800U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
-  #define ETH_DMABMR_PBL_4xPBL_64Beat  0x01001000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
-  #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
-#define ETH_DMABMR_EDE       0x00000080U  /* Enhanced Descriptor Enable */
-#define ETH_DMABMR_DSL       0x0000007CU  /* Descriptor Skip Length */
-#define ETH_DMABMR_DA        0x00000002U  /* DMA arbitration scheme */
-#define ETH_DMABMR_SR        0x00000001U  /* Software reset */
-
-/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
-#define ETH_DMATPDR_TPD      0xFFFFFFFFU  /* Transmit poll demand */
-
-/* Bit definition for Ethernet DMA Receive Poll Demand Register */
-#define ETH_DMARPDR_RPD      0xFFFFFFFFU  /* Receive poll demand  */
-
-/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
-#define ETH_DMARDLAR_SRL     0xFFFFFFFFU  /* Start of receive list */
-
-/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
-#define ETH_DMATDLAR_STL     0xFFFFFFFFU  /* Start of transmit list */
-
-/* Bit definition for Ethernet DMA Status Register */
-#define ETH_DMASR_TSTS       0x20000000U  /* Time-stamp trigger status */
-#define ETH_DMASR_PMTS       0x10000000U  /* PMT status */
-#define ETH_DMASR_MMCS       0x08000000U  /* MMC status */
-#define ETH_DMASR_EBS        0x03800000U  /* Error bits status */
-  /* combination with EBS[2:0] for GetFlagStatus function */
-  #define ETH_DMASR_EBS_DescAccess      0x02000000U  /* Error bits 0-data buffer, 1-desc. access */
-  #define ETH_DMASR_EBS_ReadTransf      0x01000000U  /* Error bits 0-write trnsf, 1-read transfr */
-  #define ETH_DMASR_EBS_DataTransfTx    0x00800000U  /* Error bits 0-Rx DMA, 1-Tx DMA */
-#define ETH_DMASR_TPS         0x00700000U  /* Transmit process state */
-  #define ETH_DMASR_TPS_Stopped         0x00000000U  /* Stopped - Reset or Stop Tx Command issued  */
-  #define ETH_DMASR_TPS_Fetching        0x00100000U  /* Running - fetching the Tx descriptor */
-  #define ETH_DMASR_TPS_Waiting         0x00200000U  /* Running - waiting for status */
-  #define ETH_DMASR_TPS_Reading         0x00300000U  /* Running - reading the data from host memory */
-  #define ETH_DMASR_TPS_Suspended       0x00600000U  /* Suspended - Tx Descriptor unavailabe */
-  #define ETH_DMASR_TPS_Closing         0x00700000U  /* Running - closing Rx descriptor */
-#define ETH_DMASR_RPS         0x000E0000U  /* Receive process state */
-  #define ETH_DMASR_RPS_Stopped         0x00000000U  /* Stopped - Reset or Stop Rx Command issued */
-  #define ETH_DMASR_RPS_Fetching        0x00020000U  /* Running - fetching the Rx descriptor */
-  #define ETH_DMASR_RPS_Waiting         0x00060000U  /* Running - waiting for packet */
-  #define ETH_DMASR_RPS_Suspended       0x00080000U  /* Suspended - Rx Descriptor unavailable */
-  #define ETH_DMASR_RPS_Closing         0x000A0000U  /* Running - closing descriptor */
-  #define ETH_DMASR_RPS_Queuing         0x000E0000U  /* Running - queuing the recieve frame into host memory */
-#define ETH_DMASR_NIS        0x00010000U  /* Normal interrupt summary */
-#define ETH_DMASR_AIS        0x00008000U  /* Abnormal interrupt summary */
-#define ETH_DMASR_ERS        0x00004000U  /* Early receive status */
-#define ETH_DMASR_FBES       0x00002000U  /* Fatal bus error status */
-#define ETH_DMASR_ETS        0x00000400U  /* Early transmit status */
-#define ETH_DMASR_RWTS       0x00000200U  /* Receive watchdog timeout status */
-#define ETH_DMASR_RPSS       0x00000100U  /* Receive process stopped status */
-#define ETH_DMASR_RBUS       0x00000080U  /* Receive buffer unavailable status */
-#define ETH_DMASR_RS         0x00000040U  /* Receive status */
-#define ETH_DMASR_TUS        0x00000020U  /* Transmit underflow status */
-#define ETH_DMASR_ROS        0x00000010U  /* Receive overflow status */
-#define ETH_DMASR_TJTS       0x00000008U  /* Transmit jabber timeout status */
-#define ETH_DMASR_TBUS       0x00000004U  /* Transmit buffer unavailable status */
-#define ETH_DMASR_TPSS       0x00000002U  /* Transmit process stopped status */
-#define ETH_DMASR_TS         0x00000001U  /* Transmit status */
-
-/* Bit definition for Ethernet DMA Operation Mode Register */
-#define ETH_DMAOMR_DTCEFD    0x04000000U  /* Disable Dropping of TCP/IP checksum error frames */
-#define ETH_DMAOMR_RSF       0x02000000U  /* Receive store and forward */
-#define ETH_DMAOMR_DFRF      0x01000000U  /* Disable flushing of received frames */
-#define ETH_DMAOMR_TSF       0x00200000U  /* Transmit store and forward */
-#define ETH_DMAOMR_FTF       0x00100000U  /* Flush transmit FIFO */
-#define ETH_DMAOMR_TTC       0x0001C000U  /* Transmit threshold control */
-  #define ETH_DMAOMR_TTC_64Bytes       0x00000000U  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
-  #define ETH_DMAOMR_TTC_128Bytes      0x00004000U  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
-  #define ETH_DMAOMR_TTC_192Bytes      0x00008000U  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
-  #define ETH_DMAOMR_TTC_256Bytes      0x0000C000U  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
-  #define ETH_DMAOMR_TTC_40Bytes       0x00010000U  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
-  #define ETH_DMAOMR_TTC_32Bytes       0x00014000U  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
-  #define ETH_DMAOMR_TTC_24Bytes       0x00018000U  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
-  #define ETH_DMAOMR_TTC_16Bytes       0x0001C000U  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
-#define ETH_DMAOMR_ST        0x00002000U  /* Start/stop transmission command */
-#define ETH_DMAOMR_FEF       0x00000080U  /* Forward error frames */
-#define ETH_DMAOMR_FUGF      0x00000040U  /* Forward undersized good frames */
-#define ETH_DMAOMR_RTC       0x00000018U  /* receive threshold control */
-  #define ETH_DMAOMR_RTC_64Bytes       0x00000000U  /* threshold level of the MTL Receive FIFO is 64 Bytes */
-  #define ETH_DMAOMR_RTC_32Bytes       0x00000008U  /* threshold level of the MTL Receive FIFO is 32 Bytes */
-  #define ETH_DMAOMR_RTC_96Bytes       0x00000010U  /* threshold level of the MTL Receive FIFO is 96 Bytes */
-  #define ETH_DMAOMR_RTC_128Bytes      0x00000018U  /* threshold level of the MTL Receive FIFO is 128 Bytes */
-#define ETH_DMAOMR_OSF       0x00000004U  /* operate on second frame */
-#define ETH_DMAOMR_SR        0x00000002U  /* Start/stop receive */
-
-/* Bit definition for Ethernet DMA Interrupt Enable Register */
-#define ETH_DMAIER_NISE      0x00010000U  /* Normal interrupt summary enable */
-#define ETH_DMAIER_AISE      0x00008000U  /* Abnormal interrupt summary enable */
-#define ETH_DMAIER_ERIE      0x00004000U  /* Early receive interrupt enable */
-#define ETH_DMAIER_FBEIE     0x00002000U  /* Fatal bus error interrupt enable */
-#define ETH_DMAIER_ETIE      0x00000400U  /* Early transmit interrupt enable */
-#define ETH_DMAIER_RWTIE     0x00000200U  /* Receive watchdog timeout interrupt enable */
-#define ETH_DMAIER_RPSIE     0x00000100U  /* Receive process stopped interrupt enable */
-#define ETH_DMAIER_RBUIE     0x00000080U  /* Receive buffer unavailable interrupt enable */
-#define ETH_DMAIER_RIE       0x00000040U  /* Receive interrupt enable */
-#define ETH_DMAIER_TUIE      0x00000020U  /* Transmit Underflow interrupt enable */
-#define ETH_DMAIER_ROIE      0x00000010U  /* Receive Overflow interrupt enable */
-#define ETH_DMAIER_TJTIE     0x00000008U  /* Transmit jabber timeout interrupt enable */
-#define ETH_DMAIER_TBUIE     0x00000004U  /* Transmit buffer unavailable interrupt enable */
-#define ETH_DMAIER_TPSIE     0x00000002U  /* Transmit process stopped interrupt enable */
-#define ETH_DMAIER_TIE       0x00000001U  /* Transmit interrupt enable */
-
-/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
-#define ETH_DMAMFBOCR_OFOC   0x10000000U  /* Overflow bit for FIFO overflow counter */
-#define ETH_DMAMFBOCR_MFA    0x0FFE0000U  /* Number of frames missed by the application */
-#define ETH_DMAMFBOCR_OMFC   0x00010000U  /* Overflow bit for missed frame counter */
-#define ETH_DMAMFBOCR_MFC    0x0000FFFFU  /* Number of frames missed by the controller */
-
-/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
-#define ETH_DMACHTDR_HTDAP   0xFFFFFFFFU  /* Host transmit descriptor address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
-#define ETH_DMACHRDR_HRDAP   0xFFFFFFFFU  /* Host receive descriptor address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
-#define ETH_DMACHTBAR_HTBAP  0xFFFFFFFFU  /* Host transmit buffer address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
-#define ETH_DMACHRBAR_HRBAP  0xFFFFFFFFU  /* Host receive buffer address pointer */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                       USB_OTG			                        */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/
-#define USB_OTG_GOTGCTL_SRQSCS                  0x00000001U            /*!< Session request success  */
-#define USB_OTG_GOTGCTL_SRQ                     0x00000002U            /*!< Session request          */
-#define USB_OTG_GOTGCTL_HNGSCS                  0x00000100U            /*!< Host negotiation success */
-#define USB_OTG_GOTGCTL_HNPRQ                   0x00000200U            /*!< HNP request              */
-#define USB_OTG_GOTGCTL_HSHNPEN                 0x00000400U            /*!< Host set HNP enable      */
-#define USB_OTG_GOTGCTL_DHNPEN                  0x00000800U            /*!< Device HNP enabled       */
-#define USB_OTG_GOTGCTL_CIDSTS                  0x00010000U            /*!< Connector ID status      */
-#define USB_OTG_GOTGCTL_DBCT                    0x00020000U            /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD                   0x00040000U            /*!< A-session valid          */
-#define USB_OTG_GOTGCTL_BSVLD                   0x00080000U            /*!< B-session valid          */
-
-/********************  Bit definition forUSB_OTG_HCFG register  ********************/
-
-#define USB_OTG_HCFG_FSLSPCS                 0x00000003U            /*!< FS/LS PHY clock select  */
-#define USB_OTG_HCFG_FSLSPCS_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCFG_FSLSPCS_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCFG_FSLSS                   0x00000004U            /*!< FS- and LS-only support */
-
-/********************  Bit definition forUSB_OTG_DCFG register  ********************/
-
-#define USB_OTG_DCFG_DSPD                    0x00000003U            /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                  0x00000001U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DSPD_1                  0x00000002U            /*!<Bit 1 */
-#define USB_OTG_DCFG_NZLSOHSK                0x00000004U            /*!< Nonzero-length status OUT handshake */
-
-#define USB_OTG_DCFG_DAD                     0x000007F0U            /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                   0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DAD_1                   0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCFG_DAD_2                   0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCFG_DAD_3                   0x00000080U            /*!<Bit 3 */
-#define USB_OTG_DCFG_DAD_4                   0x00000100U            /*!<Bit 4 */
-#define USB_OTG_DCFG_DAD_5                   0x00000200U            /*!<Bit 5 */
-#define USB_OTG_DCFG_DAD_6                   0x00000400U            /*!<Bit 6 */
-
-#define USB_OTG_DCFG_PFIVL                   0x00001800U            /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PFIVL_1                 0x00001000U            /*!<Bit 1 */
-
-#define USB_OTG_DCFG_PERSCHIVL               0x03000000U            /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0             0x01000000U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PERSCHIVL_1             0x02000000U            /*!<Bit 1 */
-
-/********************  Bit definition forUSB_OTG_PCGCR register  ********************/
-#define USB_OTG_PCGCR_STPPCLK                 0x00000001U            /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK                0x00000002U            /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP                 0x00000010U            /*!< PHY suspended */
-
-/********************  Bit definition forUSB_OTG_GOTGINT register  ********************/
-#define USB_OTG_GOTGINT_SEDET                   0x00000004U            /*!< Session end detected                   */
-#define USB_OTG_GOTGINT_SRSSCHG                 0x00000100U            /*!< Session request success status change  */
-#define USB_OTG_GOTGINT_HNSSCHG                 0x00000200U            /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET                  0x00020000U            /*!< Host negotiation detected              */
-#define USB_OTG_GOTGINT_ADTOCHG                 0x00040000U            /*!< A-device timeout change                */
-#define USB_OTG_GOTGINT_DBCDNE                  0x00080000U            /*!< Debounce done                          */
-
-/********************  Bit definition forUSB_OTG_DCTL register  ********************/
-#define USB_OTG_DCTL_RWUSIG                  0x00000001U            /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS                    0x00000002U            /*!< Soft disconnect         */
-#define USB_OTG_DCTL_GINSTS                  0x00000004U            /*!< Global IN NAK status    */
-#define USB_OTG_DCTL_GONSTS                  0x00000008U            /*!< Global OUT NAK status   */
-
-#define USB_OTG_DCTL_TCTL                    0x00000070U            /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                  0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCTL_TCTL_1                  0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCTL_TCTL_2                  0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCTL_SGINAK                  0x00000080U            /*!< Set global IN NAK         */
-#define USB_OTG_DCTL_CGINAK                  0x00000100U            /*!< Clear global IN NAK       */
-#define USB_OTG_DCTL_SGONAK                  0x00000200U            /*!< Set global OUT NAK        */
-#define USB_OTG_DCTL_CGONAK                  0x00000400U            /*!< Clear global OUT NAK      */
-#define USB_OTG_DCTL_POPRGDNE                0x00000800U            /*!< Power-on programming done */
-
-/********************  Bit definition forUSB_OTG_HFIR register  ********************/
-#define USB_OTG_HFIR_FRIVL                   0x0000FFFFU            /*!< Frame interval */
-
-/********************  Bit definition forUSB_OTG_HFNUM register  ********************/
-#define USB_OTG_HFNUM_FRNUM                   0x0000FFFFU            /*!< Frame number         */
-#define USB_OTG_HFNUM_FTREM                   0xFFFF0000U            /*!< Frame time remaining */
-
-/********************  Bit definition forUSB_OTG_DSTS register  ********************/
-#define USB_OTG_DSTS_SUSPSTS                 0x00000001U            /*!< Suspend status   */
-
-#define USB_OTG_DSTS_ENUMSPD                 0x00000006U            /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_DSTS_ENUMSPD_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_DSTS_EERR                    0x00000008U            /*!< Erratic error     */
-#define USB_OTG_DSTS_FNSOF                   0x003FFF00U            /*!< Frame number of the received SOF */
-
-/********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/
-#define USB_OTG_GAHBCFG_GINT                    0x00000001U            /*!< Global interrupt mask */
-
-#define USB_OTG_GAHBCFG_HBSTLEN                 0x0000001EU            /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_GAHBCFG_HBSTLEN_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_GAHBCFG_HBSTLEN_2               0x00000008U            /*!<Bit 2 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3               0x00000010U            /*!<Bit 3 */
-#define USB_OTG_GAHBCFG_DMAEN                   0x00000020U            /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL                 0x00000080U            /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL                0x00000100U            /*!< Periodic TxFIFO empty level */
-
-/********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/
-
-#define USB_OTG_GUSBCFG_TOCAL                   0x00000007U            /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TOCAL_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TOCAL_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_PHYSEL                  0x00000040U            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP                  0x00000100U            /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP                  0x00000200U            /*!< HNP-capable */
-
-#define USB_OTG_GUSBCFG_TRDT                    0x00003C00U            /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                  0x00000400U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TRDT_1                  0x00000800U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TRDT_2                  0x00001000U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_TRDT_3                  0x00002000U            /*!<Bit 3 */
-#define USB_OTG_GUSBCFG_PHYLPCS                 0x00008000U            /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS                0x00020000U            /*!< ULPI FS/LS select               */
-#define USB_OTG_GUSBCFG_ULPIAR                  0x00040000U            /*!< ULPI Auto-resume                */
-#define USB_OTG_GUSBCFG_ULPICSM                 0x00080000U            /*!< ULPI Clock SuspendM             */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD              0x00100000U            /*!< ULPI External VBUS Drive        */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI              0x00200000U            /*!< ULPI external VBUS indicator    */
-#define USB_OTG_GUSBCFG_TSDPS                   0x00400000U            /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI                    0x00800000U            /*!< Indicator complement            */
-#define USB_OTG_GUSBCFG_PTCI                    0x01000000U            /*!< Indicator pass through          */
-#define USB_OTG_GUSBCFG_ULPIIPD                 0x02000000U            /*!< ULPI interface protect disable  */
-#define USB_OTG_GUSBCFG_FHMOD                   0x20000000U            /*!< Forced host mode                */
-#define USB_OTG_GUSBCFG_FDMOD                   0x40000000U            /*!< Forced peripheral mode          */
-#define USB_OTG_GUSBCFG_CTXPKT                  0x80000000U            /*!< Corrupt Tx packet               */
-
-/********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
-#define USB_OTG_GRSTCTL_CSRST                   0x00000001U            /*!< Core soft reset          */
-#define USB_OTG_GRSTCTL_HSRST                   0x00000002U            /*!< HCLK soft reset          */
-#define USB_OTG_GRSTCTL_FCRST                   0x00000004U            /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH                 0x00000010U            /*!< RxFIFO flush             */
-#define USB_OTG_GRSTCTL_TXFFLSH                 0x00000020U            /*!< TxFIFO flush             */
-
-#define USB_OTG_GRSTCTL_TXFNUM                  0x000007C0U            /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                0x00000040U            /*!<Bit 0 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                0x00000080U            /*!<Bit 1 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                0x00000100U            /*!<Bit 2 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                0x00000200U            /*!<Bit 3 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                0x00000400U            /*!<Bit 4 */
-#define USB_OTG_GRSTCTL_DMAREQ                  0x40000000U            /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL                  0x80000000U            /*!< AHB master idle */
-
-/********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/
-#define USB_OTG_DIEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask                 */
-#define USB_OTG_DIEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask                  */
-#define USB_OTG_DIEPMSK_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask          */
-#define USB_OTG_DIEPMSK_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask           */
-#define USB_OTG_DIEPMSK_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask                    */
-#define USB_OTG_DIEPMSK_TXFURM                  0x00000100U            /*!< FIFO underrun mask                                */
-#define USB_OTG_DIEPMSK_BIM                     0x00000200U            /*!< BNA interrupt mask                                */
-
-/********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/
-#define USB_OTG_HPTXSTS_PTXFSAVL                0x0000FFFFU            /*!< Periodic transmit data FIFO space available     */
-
-#define USB_OTG_HPTXSTS_PTXQSAV                 0x00FF0000U            /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0               0x00010000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1               0x00020000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2               0x00040000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3               0x00080000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4               0x00100000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5               0x00200000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6               0x00400000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7               0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_HPTXSTS_PTXQTOP                 0xFF000000U            /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0               0x01000000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1               0x02000000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2               0x04000000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3               0x08000000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4               0x10000000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5               0x20000000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6               0x40000000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7               0x80000000U            /*!<Bit 7 */
-
-/********************  Bit definition forUSB_OTG_HAINT register  ********************/
-#define USB_OTG_HAINT_HAINT                   0x0000FFFFU            /*!< Channel interrupts */
-
-/********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/
-#define USB_OTG_DOEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask               */
-#define USB_OTG_DOEPMSK_STUPM                   0x00000008U            /*!< SETUP phase done mask                          */
-#define USB_OTG_DOEPMSK_OTEPDM                  0x00000010U            /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received mask       */
-#define USB_OTG_DOEPMSK_OPEM                    0x00000100U            /*!< OUT packet error mask                          */
-#define USB_OTG_DOEPMSK_BOIM                    0x00000200U            /*!< BNA interrupt mask                             */
-
-/********************  Bit definition forUSB_OTG_GINTSTS register  ********************/
-#define USB_OTG_GINTSTS_CMOD                    0x00000001U            /*!< Current mode of operation           */
-#define USB_OTG_GINTSTS_MMIS                    0x00000002U            /*!< Mode mismatch interrupt             */
-#define USB_OTG_GINTSTS_OTGINT                  0x00000004U            /*!< OTG interrupt                       */
-#define USB_OTG_GINTSTS_SOF                     0x00000008U            /*!< Start of frame                      */
-#define USB_OTG_GINTSTS_RXFLVL                  0x00000010U            /*!< RxFIFO nonempty                     */
-#define USB_OTG_GINTSTS_NPTXFE                  0x00000020U            /*!< Nonperiodic TxFIFO empty            */
-#define USB_OTG_GINTSTS_GINAKEFF                0x00000040U            /*!< Global IN nonperiodic NAK effective */
-#define USB_OTG_GINTSTS_BOUTNAKEFF              0x00000080U            /*!< Global OUT NAK effective            */
-#define USB_OTG_GINTSTS_ESUSP                   0x00000400U            /*!< Early suspend                            */
-#define USB_OTG_GINTSTS_USBSUSP                 0x00000800U            /*!< USB suspend                              */
-#define USB_OTG_GINTSTS_USBRST                  0x00001000U            /*!< USB reset                                */
-#define USB_OTG_GINTSTS_ENUMDNE                 0x00002000U            /*!< Enumeration done                         */
-#define USB_OTG_GINTSTS_ISOODRP                 0x00004000U            /*!< Isochronous OUT packet dropped interrupt */
-#define USB_OTG_GINTSTS_EOPF                    0x00008000U            /*!< End of periodic frame interrupt          */
-#define USB_OTG_GINTSTS_IEPINT                  0x00040000U            /*!< IN endpoint interrupt                          */
-#define USB_OTG_GINTSTS_OEPINT                  0x00080000U            /*!< OUT endpoint interrupt                         */
-#define USB_OTG_GINTSTS_IISOIXFR                0x00100000U            /*!< Incomplete isochronous IN transfer             */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       0x00200000U            /*!< Incomplete periodic transfer                   */
-#define USB_OTG_GINTSTS_DATAFSUSP               0x00400000U            /*!< Data fetch suspended                           */
-#define USB_OTG_GINTSTS_HPRTINT                 0x01000000U            /*!< Host port interrupt                            */
-#define USB_OTG_GINTSTS_HCINT                   0x02000000U            /*!< Host channels interrupt                        */
-#define USB_OTG_GINTSTS_PTXFE                   0x04000000U            /*!< Periodic TxFIFO empty                          */
-#define USB_OTG_GINTSTS_CIDSCHG                 0x10000000U            /*!< Connector ID status change                     */
-#define USB_OTG_GINTSTS_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt                  */
-#define USB_OTG_GINTSTS_SRQINT                  0x40000000U            /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT                  0x80000000U            /*!< Resume/remote wakeup detected interrupt        */
-
-/********************  Bit definition forUSB_OTG_GINTMSK register  ********************/
-#define USB_OTG_GINTMSK_MMISM                   0x00000002U            /*!< Mode mismatch interrupt mask                        */
-#define USB_OTG_GINTMSK_OTGINT                  0x00000004U            /*!< OTG interrupt mask                                  */
-#define USB_OTG_GINTMSK_SOFM                    0x00000008U            /*!< Start of frame mask                                 */
-#define USB_OTG_GINTMSK_RXFLVLM                 0x00000010U            /*!< Receive FIFO nonempty mask                          */
-#define USB_OTG_GINTMSK_NPTXFEM                 0x00000020U            /*!< Nonperiodic TxFIFO empty mask                       */
-#define USB_OTG_GINTMSK_GINAKEFFM               0x00000040U            /*!< Global nonperiodic IN NAK effective mask            */
-#define USB_OTG_GINTMSK_GONAKEFFM               0x00000080U            /*!< Global OUT NAK effective mask                       */
-#define USB_OTG_GINTMSK_ESUSPM                  0x00000400U            /*!< Early suspend mask                                  */
-#define USB_OTG_GINTMSK_USBSUSPM                0x00000800U            /*!< USB suspend mask                                    */
-#define USB_OTG_GINTMSK_USBRST                  0x00001000U            /*!< USB reset mask                                      */
-#define USB_OTG_GINTMSK_ENUMDNEM                0x00002000U            /*!< Enumeration done mask                               */
-#define USB_OTG_GINTMSK_ISOODRPM                0x00004000U            /*!< Isochronous OUT packet dropped interrupt mask       */
-#define USB_OTG_GINTMSK_EOPFM                   0x00008000U            /*!< End of periodic frame interrupt mask                */
-#define USB_OTG_GINTMSK_EPMISM                  0x00020000U            /*!< Endpoint mismatch interrupt mask                    */
-#define USB_OTG_GINTMSK_IEPINT                  0x00040000U            /*!< IN endpoints interrupt mask                         */
-#define USB_OTG_GINTMSK_OEPINT                  0x00080000U            /*!< OUT endpoints interrupt mask                        */
-#define USB_OTG_GINTMSK_IISOIXFRM               0x00100000U            /*!< Incomplete isochronous IN transfer mask             */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         0x00200000U            /*!< Incomplete periodic transfer mask                   */
-#define USB_OTG_GINTMSK_FSUSPM                  0x00400000U            /*!< Data fetch suspended mask                           */
-#define USB_OTG_GINTMSK_PRTIM                   0x01000000U            /*!< Host port interrupt mask                            */
-#define USB_OTG_GINTMSK_HCIM                    0x02000000U            /*!< Host channels interrupt mask                        */
-#define USB_OTG_GINTMSK_PTXFEM                  0x04000000U            /*!< Periodic TxFIFO empty mask                          */
-#define USB_OTG_GINTMSK_CIDSCHGM                0x10000000U            /*!< Connector ID status change mask                     */
-#define USB_OTG_GINTMSK_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt mask                  */
-#define USB_OTG_GINTMSK_SRQIM                   0x40000000U            /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM                    0x80000000U            /*!< Resume/remote wakeup detected interrupt mask        */
-
-/********************  Bit definition forUSB_OTG_DAINT register  ********************/
-#define USB_OTG_DAINT_IEPINT                  0x0000FFFFU            /*!< IN endpoint interrupt bits  */
-#define USB_OTG_DAINT_OEPINT                  0xFFFF0000U            /*!< OUT endpoint interrupt bits */
-
-/********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/
-#define USB_OTG_HAINTMSK_HAINTM                  0x0000FFFFU            /*!< Channel interrupt mask */
-
-/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
-#define USB_OTG_GRXSTSP_EPNUM                    0x0000000FU            /*!< IN EP interrupt mask bits  */
-#define USB_OTG_GRXSTSP_BCNT                     0x00007FF0U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID                     0x00018000U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS                   0x001E0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/
-#define USB_OTG_DAINTMSK_IEPM                    0x0000FFFFU            /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM                    0xFFFF0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for OTG register  ********************/
-
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition for OTG register  ********************/
-
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/
-#define USB_OTG_GRXFSIZ_RXFD            0x0000FFFFU            /*!< RxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/
-#define USB_OTG_DVBUSDIS_VBUSDT         0x0000FFFFU            /*!< Device VBUS discharge time */
-
-/********************  Bit definition for OTG register  ********************/
-#define USB_OTG_NPTXFSA                 0x0000FFFFU            /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD                  0xFFFF0000U            /*!< Nonperiodic TxFIFO depth               */
-#define USB_OTG_TX0FSA                  0x0000FFFFU            /*!< Endpoint 0 transmit RAM start address  */
-#define USB_OTG_TX0FD                   0xFFFF0000U            /*!< Endpoint 0 TxFIFO depth                */
-
-/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
-#define USB_OTG_DVBUSPULSE_DVBUSP                  0x00000FFFU            /*!< Device VBUS pulsing time */
-
-/********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/
-#define USB_OTG_GNPTXSTS_NPTXFSAV                0x0000FFFFU            /*!< Nonperiodic TxFIFO space available */
-
-#define USB_OTG_GNPTXSTS_NPTQXSAV                0x00FF0000U            /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0              0x00010000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1              0x00020000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2              0x00040000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3              0x00080000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4              0x00100000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5              0x00200000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6              0x00400000U            /*!<Bit 6 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7              0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_GNPTXSTS_NPTXQTOP                0x7F000000U            /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0              0x01000000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1              0x02000000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2              0x04000000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3              0x08000000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4              0x10000000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5              0x20000000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6              0x40000000U            /*!<Bit 6 */
-
-/********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/
-#define USB_OTG_DTHRCTL_NONISOTHREN             0x00000001U            /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN                0x00000002U            /*!< ISO IN endpoint threshold enable */
-
-#define USB_OTG_DTHRCTL_TXTHRLEN                0x000007FCU            /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0              0x00000004U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1              0x00000008U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2              0x00000010U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3              0x00000020U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4              0x00000040U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5              0x00000080U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6              0x00000100U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7              0x00000200U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8              0x00000400U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_RXTHREN                 0x00010000U            /*!< Receive threshold enable */
-
-#define USB_OTG_DTHRCTL_RXTHRLEN                0x03FE0000U            /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0              0x00020000U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1              0x00040000U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2              0x00080000U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3              0x00100000U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4              0x00200000U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5              0x00400000U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6              0x00800000U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7              0x01000000U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8              0x02000000U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_ARPEN                   0x08000000U            /*!< Arbiter parking enable */
-
-/********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM               0x0000FFFFU            /*!< IN EP Tx FIFO empty interrupt mask bits */
-
-/********************  Bit definition forUSB_OTG_DEACHINT register  ********************/
-#define USB_OTG_DEACHINT_IEP1INT                 0x00000002U            /*!< IN endpoint 1interrupt bit   */
-#define USB_OTG_DEACHINT_OEP1INT                 0x00020000U            /*!< OUT endpoint 1 interrupt bit */
-
-/********************  Bit definition forUSB_OTG_GCCFG register  ********************/
-#define USB_OTG_GCCFG_PWRDWN                  0x00010000U            /*!< Power down */
-#define USB_OTG_GCCFG_I2CPADEN                0x00020000U            /*!< Enable I2C bus connection for the external I2C PHY interface */
-#define USB_OTG_GCCFG_VBUSASEN                0x00040000U            /*!< Enable the VBUS sensing device                               */
-#define USB_OTG_GCCFG_VBUSBSEN                0x00080000U            /*!< Enable the VBUS sensing device                               */
-#define USB_OTG_GCCFG_SOFOUTEN                0x00100000U            /*!< SOF output enable                                            */
-#define USB_OTG_GCCFG_NOVBUSSENS              0x00200000U            /*!< VBUS sensing disable option                                  */
-
-/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
-#define USB_OTG_DEACHINTMSK_IEP1INTM                0x00000002U            /*!< IN Endpoint 1 interrupt mask bit  */
-#define USB_OTG_DEACHINTMSK_OEP1INTM                0x00020000U            /*!< OUT Endpoint 1 interrupt mask bit */
-
-/********************  Bit definition forUSB_OTG_CID register  ********************/
-#define USB_OTG_CID_PRODUCT_ID              0xFFFFFFFFU            /*!< Product ID field */
-
-/********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/
-#define USB_OTG_DIEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask                 */
-#define USB_OTG_DIEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask                  */
-#define USB_OTG_DIEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask          */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask           */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask                    */
-#define USB_OTG_DIEPEACHMSK1_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
-
-/********************  Bit definition forUSB_OTG_HPRT register  ********************/
-#define USB_OTG_HPRT_PCSTS                   0x00000001U            /*!< Port connect status        */
-#define USB_OTG_HPRT_PCDET                   0x00000002U            /*!< Port connect detected      */
-#define USB_OTG_HPRT_PENA                    0x00000004U            /*!< Port enable                */
-#define USB_OTG_HPRT_PENCHNG                 0x00000008U            /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA                    0x00000010U            /*!< Port overcurrent active    */
-#define USB_OTG_HPRT_POCCHNG                 0x00000020U            /*!< Port overcurrent change    */
-#define USB_OTG_HPRT_PRES                    0x00000040U            /*!< Port resume   */
-#define USB_OTG_HPRT_PSUSP                   0x00000080U            /*!< Port suspend  */
-#define USB_OTG_HPRT_PRST                    0x00000100U            /*!< Port reset    */
-
-#define USB_OTG_HPRT_PLSTS                   0x00000C00U            /*!< Port line status */
-#define USB_OTG_HPRT_PLSTS_0                 0x00000400U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PLSTS_1                 0x00000800U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PPWR                    0x00001000U            /*!< Port power */
-
-#define USB_OTG_HPRT_PTCTL                   0x0001E000U            /*!< Port test control */
-#define USB_OTG_HPRT_PTCTL_0                 0x00002000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PTCTL_1                 0x00004000U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PTCTL_2                 0x00008000U            /*!<Bit 2 */
-#define USB_OTG_HPRT_PTCTL_3                 0x00010000U            /*!<Bit 3 */
-
-#define USB_OTG_HPRT_PSPD                    0x00060000U            /*!< Port speed */
-#define USB_OTG_HPRT_PSPD_0                  0x00020000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PSPD_1                  0x00040000U            /*!<Bit 1 */
-
-/********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/
-#define USB_OTG_DOEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DOEPEACHMSK1_TXFURM                  0x00000100U            /*!< OUT packet error mask */
-#define USB_OTG_DOEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_BERRM                   0x00001000U            /*!< Bubble error interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NYETM                   0x00004000U            /*!< NYET interrupt mask */
-
-/********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/
-#define USB_OTG_HPTXFSIZ_PTXSA                   0x0000FFFFU            /*!< Host periodic TxFIFO start address */
-#define USB_OTG_HPTXFSIZ_PTXFD                   0xFFFF0000U            /*!< Host periodic TxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/
-#define USB_OTG_DIEPCTL_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
-#define USB_OTG_DIEPCTL_USBAEP                  0x00008000U            /*!< USB active endpoint */
-#define USB_OTG_DIEPCTL_EONUM_DPID              0x00010000U            /*!< Even/odd frame */
-#define USB_OTG_DIEPCTL_NAKSTS                  0x00020000U            /*!< NAK status */
-
-#define USB_OTG_DIEPCTL_EPTYP                   0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_DIEPCTL_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_STALL                   0x00200000U            /*!< STALL handshake */
-
-#define USB_OTG_DIEPCTL_TXFNUM                  0x03C00000U            /*!< TxFIFO number */
-#define USB_OTG_DIEPCTL_TXFNUM_0                0x00400000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                0x00800000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                0x01000000U            /*!<Bit 2 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                0x02000000U            /*!<Bit 3 */
-#define USB_OTG_DIEPCTL_CNAK                    0x04000000U            /*!< Clear NAK */
-#define USB_OTG_DIEPCTL_SNAK                    0x08000000U            /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          0x10000000U            /*!< Set DATA0 PID */
-#define USB_OTG_DIEPCTL_SODDFRM                 0x20000000U            /*!< Set odd frame */
-#define USB_OTG_DIEPCTL_EPDIS                   0x40000000U            /*!< Endpoint disable */
-#define USB_OTG_DIEPCTL_EPENA                   0x80000000U            /*!< Endpoint enable */
-
-/********************  Bit definition forUSB_OTG_HCCHAR register  ********************/
-#define USB_OTG_HCCHAR_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
-
-#define USB_OTG_HCCHAR_EPNUM                   0x00007800U            /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPNUM_1                 0x00001000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_EPNUM_2                 0x00002000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_EPNUM_3                 0x00004000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_EPDIR                   0x00008000U            /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV                   0x00020000U            /*!< Low-speed device */
-
-#define USB_OTG_HCCHAR_EPTYP                   0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_MC                      0x00300000U            /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                    0x00100000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_MC_1                    0x00200000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_DAD                     0x1FC00000U            /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                   0x00400000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_DAD_1                   0x00800000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_DAD_2                   0x01000000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_DAD_3                   0x02000000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_DAD_4                   0x04000000U            /*!<Bit 4 */
-#define USB_OTG_HCCHAR_DAD_5                   0x08000000U            /*!<Bit 5 */
-#define USB_OTG_HCCHAR_DAD_6                   0x10000000U            /*!<Bit 6 */
-#define USB_OTG_HCCHAR_ODDFRM                  0x20000000U            /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS                   0x40000000U            /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA                   0x80000000U            /*!< Channel enable */
-
-/********************  Bit definition forUSB_OTG_HCSPLT register  ********************/
-
-#define USB_OTG_HCSPLT_PRTADDR                 0x0000007FU            /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_PRTADDR_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_PRTADDR_2               0x00000004U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_PRTADDR_3               0x00000008U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_PRTADDR_4               0x00000010U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_PRTADDR_5               0x00000020U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_PRTADDR_6               0x00000040U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_HUBADDR                 0x00003F80U            /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0               0x00000080U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_HUBADDR_1               0x00000100U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_HUBADDR_2               0x00000200U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_HUBADDR_3               0x00000400U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_HUBADDR_4               0x00000800U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_HUBADDR_5               0x00001000U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_HUBADDR_6               0x00002000U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_XACTPOS                 0x0000C000U            /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0               0x00004000U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_XACTPOS_1               0x00008000U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_COMPLSPLT               0x00010000U            /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN                 0x80000000U            /*!< Split enable */
-
-/********************  Bit definition forUSB_OTG_HCINT register  ********************/
-#define USB_OTG_HCINT_XFRC                    0x00000001U            /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH                     0x00000002U            /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINT_STALL                   0x00000008U            /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK                     0x00000010U            /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK                     0x00000020U            /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET                    0x00000040U            /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR                   0x00000080U            /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR                   0x00000100U            /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR                   0x00000200U            /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR                   0x00000400U            /*!< Data toggle error */
-
-/********************  Bit definition forUSB_OTG_DIEPINT register  ********************/
-#define USB_OTG_DIEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_TOC                     0x00000008U            /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE                  0x00000010U            /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNE                  0x00000040U            /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE                    0x00000080U            /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN              0x00000100U            /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA                     0x00000200U            /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS               0x00000800U            /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR                    0x00001000U            /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK                     0x00002000U            /*!< NAK interrupt */
-
-/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
-#define USB_OTG_HCINTMSK_XFRCM                   0x00000001U            /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM                    0x00000002U            /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM                  0x00000008U            /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM                    0x00000010U            /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM                    0x00000020U            /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET                    0x00000040U            /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM                  0x00000080U            /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM                  0x00000100U            /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM                  0x00000200U            /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM                  0x00000400U            /*!< Data toggle error mask */
-
-/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
-
-#define USB_OTG_DIEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT                  0x60000000U            /*!< Packet count */
-/********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/
-#define USB_OTG_HCTSIZ_XFRSIZ                    0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT                    0x1FF80000U            /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING                    0x80000000U            /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID                      0x60000000U            /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                    0x20000000U            /*!<Bit 0 */
-#define USB_OTG_HCTSIZ_DPID_1                    0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/
-#define USB_OTG_DIEPDMA_DMAADDR                  0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition forUSB_OTG_HCDMA register  ********************/
-#define USB_OTG_HCDMA_DMAADDR                    0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/
-#define USB_OTG_DTXFSTS_INEPTFSAV                0x0000FFFFU            /*!< IN endpoint TxFIFO space available */
-
-/********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/
-#define USB_OTG_DIEPTXF_INEPTXSA                 0x0000FFFFU            /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD                 0xFFFF0000U            /*!< IN endpoint TxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/
-
-#define USB_OTG_DOEPCTL_MPSIZ                     0x000007FFU            /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP                    0x00008000U            /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS                    0x00020000U            /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            0x10000000U            /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM                   0x20000000U            /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP                     0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                   0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DOEPCTL_EPTYP_1                   0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_SNPM                      0x00100000U            /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL                     0x00200000U            /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK                      0x04000000U            /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK                      0x08000000U            /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS                     0x40000000U            /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA                     0x80000000U            /*!< Endpoint enable */
-
-/********************  Bit definition forUSB_OTG_DOEPINT register  ********************/
-#define USB_OTG_DOEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_STUP                    0x00000008U            /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS                 0x00000010U            /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_NYET                    0x00004000U            /*!< NYET interrupt */
-
-/********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/
-
-#define USB_OTG_DOEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-
-#define USB_OTG_DOEPTSIZ_STUPCNT                 0x60000000U            /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0               0x20000000U            /*!<Bit 0 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1               0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition for PCGCCTL register  ********************/
-#define USB_OTG_PCGCCTL_STOPCLK                 0x00000001U            /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK                 0x00000002U            /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP                 0x00000010U            /*!<Bit 1 */
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
-                                       ((INSTANCE) == ADC2) || \
-                                       ((INSTANCE) == ADC3))
-
-/******************************* CAN Instances ********************************/
-#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
-                                       ((INSTANCE) == CAN2))
- 
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DAC Instances ********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/******************************* DCMI Instances *******************************/
-#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
-
-/******************************* DMA2D Instances *******************************/
-#define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
-
-/******************************** DMA Instances *******************************/
-#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
-                                              ((INSTANCE) == DMA1_Stream1) || \
-                                              ((INSTANCE) == DMA1_Stream2) || \
-                                              ((INSTANCE) == DMA1_Stream3) || \
-                                              ((INSTANCE) == DMA1_Stream4) || \
-                                              ((INSTANCE) == DMA1_Stream5) || \
-                                              ((INSTANCE) == DMA1_Stream6) || \
-                                              ((INSTANCE) == DMA1_Stream7) || \
-                                              ((INSTANCE) == DMA2_Stream0) || \
-                                              ((INSTANCE) == DMA2_Stream1) || \
-                                              ((INSTANCE) == DMA2_Stream2) || \
-                                              ((INSTANCE) == DMA2_Stream3) || \
-                                              ((INSTANCE) == DMA2_Stream4) || \
-                                              ((INSTANCE) == DMA2_Stream5) || \
-                                              ((INSTANCE) == DMA2_Stream6) || \
-                                              ((INSTANCE) == DMA2_Stream7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOF) || \
-                                        ((INSTANCE) == GPIOG) || \
-                                        ((INSTANCE) == GPIOH) || \
-                                        ((INSTANCE) == GPIOI) || \
-                                        ((INSTANCE) == GPIOJ) || \
-                                        ((INSTANCE) == GPIOK))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2) || \
-                                       ((INSTANCE) == I2C3))
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI2) || \
-                                        ((INSTANCE) == SPI3))
-
-/*************************** I2S Extended Instances ***************************/
-#define IS_I2S_ALL_INSTANCE_EXT(PERIPH)  (((INSTANCE) == SPI2)    || \
-                                          ((INSTANCE) == SPI3)    || \
-                                          ((INSTANCE) == I2S2ext) || \
-                                          ((INSTANCE) == I2S3ext))
-
-/******************************* RNG Instances ********************************/
-#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************* SAI Instances ********************************/
-#define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
-                                     ((PERIPH) == SAI1_Block_B))
-/* Legacy define */
-#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3) || \
-                                       ((INSTANCE) == SPI4) || \
-                                       ((INSTANCE) == SPI5) || \
-                                       ((INSTANCE) == SPI6))
-
-/*************************** SPI Extended Instances ***************************/
-#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1)    || \
-                                           ((INSTANCE) == SPI2)    || \
-                                           ((INSTANCE) == SPI3)    || \
-                                           ((INSTANCE) == SPI4)    || \
-                                           ((INSTANCE) == SPI5)    || \
-                                           ((INSTANCE) == SPI6)    || \
-                                           ((INSTANCE) == I2S2ext) || \
-                                           ((INSTANCE) == I2S3ext))
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
-                                   ((INSTANCE) == TIM2)   || \
-                                   ((INSTANCE) == TIM3)   || \
-                                   ((INSTANCE) == TIM4)   || \
-                                   ((INSTANCE) == TIM5)   || \
-                                   ((INSTANCE) == TIM6)   || \
-                                   ((INSTANCE) == TIM7)   || \
-                                   ((INSTANCE) == TIM8)   || \
-                                   ((INSTANCE) == TIM9)   || \
-                                   ((INSTANCE) == TIM10)  || \
-                                   ((INSTANCE) == TIM11)  || \
-                                   ((INSTANCE) == TIM12)  || \
-                                   ((INSTANCE) == TIM13)  || \
-                                   ((INSTANCE) == TIM14))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
-                                         ((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM8)  || \
-                                         ((INSTANCE) == TIM9)  || \
-                                         ((INSTANCE) == TIM10) || \
-                                         ((INSTANCE) == TIM11) || \
-                                         ((INSTANCE) == TIM12) || \
-                                         ((INSTANCE) == TIM13) || \
-                                         ((INSTANCE) == TIM14))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM8) || \
-                                       ((INSTANCE) == TIM9) || \
-                                       ((INSTANCE) == TIM12))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8))
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM8))
-
-/******************** TIM Instances : Advanced-control timers *****************/
-#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                            ((INSTANCE) == TIM8))
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8))
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM6) || \
-                                       ((INSTANCE) == TIM7) || \
-                                       ((INSTANCE) == TIM8))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM8))
-
-/************ TIM Instances : DMA requests generation (COMDE) *****************/
-#define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM8)) 
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                             ((INSTANCE) == TIM2) || \
-                                             ((INSTANCE) == TIM3) || \
-                                             ((INSTANCE) == TIM4) || \
-                                             ((INSTANCE) == TIM5) || \
-                                             ((INSTANCE) == TIM8))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM6) || \
-                                          ((INSTANCE) == TIM7) || \
-                                          ((INSTANCE) == TIM8) || \
-                                          ((INSTANCE) == TIM9) || \
-                                          ((INSTANCE) == TIM12))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8) || \
-                                         ((INSTANCE) == TIM9) || \
-                                         ((INSTANCE) == TIM12))
-
-/********************** TIM Instances : 32 bit Counter ************************/
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
-                                              ((INSTANCE) == TIM5))
-
-/***************** TIM Instances : external trigger input availabe ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                        ((INSTANCE) == TIM2) || \
-                                        ((INSTANCE) == TIM3) || \
-                                        ((INSTANCE) == TIM4) || \
-                                        ((INSTANCE) == TIM5) || \
-                                        ((INSTANCE) == TIM8))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM11))
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM1) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM5) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM8) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM12) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM13) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM14) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-/************ TIM Instances : complementary output(s) available ***************/
-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
-   ((((INSTANCE) == TIM1) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3)))            \
-    ||                                          \
-    (((INSTANCE) == TIM8) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3))))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3) || \
-                                     ((INSTANCE) == USART6))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5)  || \
-                                    ((INSTANCE) == USART6) || \
-                                    ((INSTANCE) == UART7)  || \
-                                    ((INSTANCE) == UART8))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3) || \
-                                           ((INSTANCE) == USART6))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3) || \
-                                         ((INSTANCE) == USART6))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5)  || \
-                                    ((INSTANCE) == USART6) || \
-                                    ((INSTANCE) == UART7)  || \
-                                    ((INSTANCE) == UART8))     
-
-/*********************** PCD Instances ****************************************/
-#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
-                                        ((INSTANCE) == USB_OTG_HS))
-
-/*********************** HCD Instances ****************************************/
-#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
-                                       ((INSTANCE) == USB_OTG_HS))
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/****************************** SDIO Instances ********************************/
-#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
-
-/****************************** USB Exported Constants ************************/
-#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                8U
-#define USB_OTG_FS_MAX_IN_ENDPOINTS                    4U    /* Including EP0 */
-#define USB_OTG_FS_MAX_OUT_ENDPOINTS                   4U    /* Including EP0 */
-#define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */
-
-#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR                12U
-#define USB_OTG_HS_MAX_IN_ENDPOINTS                    6U    /* Including EP0 */
-#define USB_OTG_HS_MAX_OUT_ENDPOINTS                   6U    /* Including EP0 */
-#define USB_OTG_HS_TOTAL_FIFO_SIZE                     4096U /* in Bytes */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32F4xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */
-/*  product lines within the same STM32F4 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-#define FSMC_IRQn              FMC_IRQn
-
-/* Aliases for __IRQHandler */
-#define FSMC_IRQHandler        FMC_IRQHandler
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32F437xx_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/cmsis/stm32f439xx.h b/stmhal/cmsis/stm32f439xx.h
deleted file mode 100644
index a37aea87fb..0000000000
--- a/stmhal/cmsis/stm32f439xx.h
+++ /dev/null
@@ -1,9306 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f439xx.h
-  * @author  MCD Application Team
-  * @version V2.5.1
-  * @date    28-June-2016
-  * @brief   CMSIS STM32F439xx Device Peripheral Access Layer Header File.
-  *
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - peripherals registers declarations and bits definition
-  *           - Macros to access peripheral’s registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS_Device
-  * @{
-  */
-
-/** @addtogroup stm32f439xx
-  * @{
-  */
-    
-#ifndef __STM32F439xx_H
-#define __STM32F439xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-  
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-
-/**
-  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
-  */
-#define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */
-#define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */
-#define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1U       /*!< FPU present                                   */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32F4XX Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-typedef enum
-{
-/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
-  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
-/******  STM32 specific Interrupt Numbers **********************************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
-  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
-  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
-  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
-  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
-  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
-  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
-  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
-  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
-  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
-  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
-  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
-  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
-  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
-  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
-  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
-  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
-  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */    
-  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
-  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
-  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
-  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
-  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
-  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
-  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
-  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
-  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
-  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
-  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
-  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
-  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
-  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
-  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
-  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
-  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
-  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
-  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
-  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
-  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
-  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
-  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
-  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
-  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
-  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
-  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
-  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
-  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
-  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
-  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
-  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
-  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
-  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
-  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
-  CRYP_IRQn                   = 79,     /*!< CRYP crypto global interrupt                                      */
-  HASH_RNG_IRQn               = 80,     /*!< Hash and Rng global interrupt                                     */
-  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
-  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */
-  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */
-  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
-  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */
-  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */
-  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
-  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                              */
-  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                        */
-  DMA2D_IRQn                  = 90      /*!< DMA2D global Interrupt                                            */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
-#include "system_stm32f4xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */      
-  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
-  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
-  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
-  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
-  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
-  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
-  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
-  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
-  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
-  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
-  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
-  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
-  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
-  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
-  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
-                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
-} ADC_Common_TypeDef;
-
-
-/** 
-  * @brief Controller Area Network TxMailBox 
-  */
-
-typedef struct
-{
-  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
-  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
-  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
-  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
-} CAN_TxMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FIFOMailBox 
-  */
-  
-typedef struct
-{
-  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
-  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
-  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
-  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
-} CAN_FIFOMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FilterRegister 
-  */
-  
-typedef struct
-{
-  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
-  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
-} CAN_FilterRegister_TypeDef;
-
-/** 
-  * @brief Controller Area Network 
-  */
-  
-typedef struct
-{
-  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
-  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
-  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
-  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
-  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
-  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
-  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
-  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
-  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
-  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
-  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
-  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
-  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
-  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
-  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
-  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
-  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
-  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
-  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
-  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
-  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */ 
-  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
-} CAN_TypeDef;
-
-/** 
-  * @brief CRC calculation unit 
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
-  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */
-  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
-  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
-  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
-  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
-  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
-  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
-  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
-  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
-  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
-  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
-  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
-  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
-  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
-  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
-  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
-  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
-  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
-  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DCMI
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
-  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
-  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
-  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
-  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
-  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
-  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
-  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
-  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
-  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
-  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
-} DCMI_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
-  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
-  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
-  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
-  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
-  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
-} DMA_Stream_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
-  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
-  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
-  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
-} DMA_TypeDef;
-
-/** 
-  * @brief DMA2D Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
-  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
-  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
-  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
-  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
-  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
-  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
-  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
-  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
-  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
-  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
-  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
-  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
-  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
-  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
-  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
-  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
-  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
-  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
-  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
-  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
-  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */
-  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */
-} DMA2D_TypeDef;
-
-/** 
-  * @brief Ethernet MAC
-  */
-
-typedef struct
-{
-  __IO uint32_t MACCR;
-  __IO uint32_t MACFFR;
-  __IO uint32_t MACHTHR;
-  __IO uint32_t MACHTLR;
-  __IO uint32_t MACMIIAR;
-  __IO uint32_t MACMIIDR;
-  __IO uint32_t MACFCR;
-  __IO uint32_t MACVLANTR;             /*    8 */
-  uint32_t      RESERVED0[2];
-  __IO uint32_t MACRWUFFR;             /*   11 */
-  __IO uint32_t MACPMTCSR;
-  uint32_t      RESERVED1[2];
-  __IO uint32_t MACSR;                 /*   15 */
-  __IO uint32_t MACIMR;
-  __IO uint32_t MACA0HR;
-  __IO uint32_t MACA0LR;
-  __IO uint32_t MACA1HR;
-  __IO uint32_t MACA1LR;
-  __IO uint32_t MACA2HR;
-  __IO uint32_t MACA2LR;
-  __IO uint32_t MACA3HR;
-  __IO uint32_t MACA3LR;               /*   24 */
-  uint32_t      RESERVED2[40];
-  __IO uint32_t MMCCR;                 /*   65 */
-  __IO uint32_t MMCRIR;
-  __IO uint32_t MMCTIR;
-  __IO uint32_t MMCRIMR;
-  __IO uint32_t MMCTIMR;               /*   69 */
-  uint32_t      RESERVED3[14];
-  __IO uint32_t MMCTGFSCCR;            /*   84 */
-  __IO uint32_t MMCTGFMSCCR;
-  uint32_t      RESERVED4[5];
-  __IO uint32_t MMCTGFCR;
-  uint32_t      RESERVED5[10];
-  __IO uint32_t MMCRFCECR;
-  __IO uint32_t MMCRFAECR;
-  uint32_t      RESERVED6[10];
-  __IO uint32_t MMCRGUFCR;
-  uint32_t      RESERVED7[334];
-  __IO uint32_t PTPTSCR;
-  __IO uint32_t PTPSSIR;
-  __IO uint32_t PTPTSHR;
-  __IO uint32_t PTPTSLR;
-  __IO uint32_t PTPTSHUR;
-  __IO uint32_t PTPTSLUR;
-  __IO uint32_t PTPTSAR;
-  __IO uint32_t PTPTTHR;
-  __IO uint32_t PTPTTLR;
-  __IO uint32_t RESERVED8;
-  __IO uint32_t PTPTSSR;
-  uint32_t      RESERVED9[565];
-  __IO uint32_t DMABMR;
-  __IO uint32_t DMATPDR;
-  __IO uint32_t DMARPDR;
-  __IO uint32_t DMARDLAR;
-  __IO uint32_t DMATDLAR;
-  __IO uint32_t DMASR;
-  __IO uint32_t DMAOMR;
-  __IO uint32_t DMAIER;
-  __IO uint32_t DMAMFBOCR;
-  __IO uint32_t DMARSWTR;
-  uint32_t      RESERVED10[8];
-  __IO uint32_t DMACHTDR;
-  __IO uint32_t DMACHRDR;
-  __IO uint32_t DMACHTBAR;
-  __IO uint32_t DMACHRBAR;
-} ETH_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
-  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
-  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
-  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
-  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
-  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-
-typedef struct
-{
-  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */
-  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */
-  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */
-  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */
-  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */
-  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief Flexible Memory Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */   
-} FMC_Bank1_TypeDef; 
-
-/** 
-  * @brief Flexible Memory Controller Bank1E
-  */
-  
-typedef struct
-{
-  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
-} FMC_Bank1E_TypeDef;
-
-/** 
-  * @brief Flexible Memory Controller Bank2
-  */
-  
-typedef struct
-{
-  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */
-  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */
-  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */
-  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
-  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */
-  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */
-  uint32_t      RESERVED1;  /*!< Reserved, 0x78                                                            */
-  uint32_t      RESERVED2;  /*!< Reserved, 0x7C                                                            */
-  __IO uint32_t PCR3;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */
-  __IO uint32_t SR3;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */
-  __IO uint32_t PMEM3;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */
-  __IO uint32_t PATT3;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
-  uint32_t      RESERVED3;  /*!< Reserved, 0x90                                                            */
-  __IO uint32_t ECCR3;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */
-} FMC_Bank2_3_TypeDef;
-
-/** 
-  * @brief Flexible Memory Controller Bank4
-  */
-  
-typedef struct
-{
-  __IO uint32_t PCR4;       /*!< PC Card  control register 4,                       Address offset: 0xA0 */
-  __IO uint32_t SR4;        /*!< PC Card  FIFO status and interrupt register 4,     Address offset: 0xA4 */
-  __IO uint32_t PMEM4;      /*!< PC Card  Common memory space timing register 4,    Address offset: 0xA8 */
-  __IO uint32_t PATT4;      /*!< PC Card  Attribute memory space timing register 4, Address offset: 0xAC */
-  __IO uint32_t PIO4;       /*!< PC Card  I/O space timing register 4,              Address offset: 0xB0 */
-} FMC_Bank4_TypeDef; 
-
-/** 
-  * @brief Flexible Memory Controller Bank5_6
-  */
-  
-typedef struct
-{
-  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */
-  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */
-  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */
-  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */
-  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */
-} FMC_Bank5_6_TypeDef; 
-
-/** 
-  * @brief General Purpose I/O
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
-  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
-  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
-  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
-  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
-  __IO uint32_t BSRR;    /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
-  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
-  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/** 
-  * @brief System configuration controller
-  */
-  
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */ 
-  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */
-  __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */
-  __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */
-  __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */
-  __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */
-  __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
-  __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
-  __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
-  __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief LCD-TFT Display Controller
-  */
-  
-typedef struct
-{
-  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04 */
-  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */
-  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */
-  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */
-  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */
-  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */
-  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20 */
-  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */
-  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28 */
-  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */
-  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30 */
-  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */
-  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */
-  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */
-  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
-  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */
-  __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                       Address offset: 0x48 */
-} LTDC_TypeDef;  
-
-/** 
-  * @brief LCD-TFT Display layer x Controller
-  */
-  
-typedef struct
-{  
-  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */
-  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
-  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */
-  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */
-  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */
-  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */
-  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */
-  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */
-  uint32_t      RESERVED0[2];  /*!< Reserved */
-  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */
-  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */
-  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */
-  uint32_t      RESERVED1[3];  /*!< Reserved */
-  __IO uint32_t CLUTWR;         /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */
-
-} LTDC_Layer_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
-  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
-  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
-  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
-  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
-  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
-  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
-  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
-  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
-  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
-  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
-  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
-  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
-  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
-  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
-  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
-  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
-  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
-  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
-  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
-  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
-  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
-  __IO uint32_t PLLSAICFGR;    /*!< RCC PLLSAI configuration register,                           Address offset: 0x88 */
-  __IO uint32_t DCKCFGR;       /*!< RCC Dedicated Clocks configuration register,                 Address offset: 0x8C */
-
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-
-typedef struct
-{
-  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
-  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
-  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
-  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
-  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
-  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
-  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */
-  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
-  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */
-  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
-  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */
-  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */
-  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */
-  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */
-  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
-  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */
-  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
-  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
-  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
-  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
-  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
-  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
-  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
-  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
-  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
-  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
-  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
-  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
-  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
-  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
-  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
-  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
-  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
-  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
-  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
-  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
-  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
-} RTC_TypeDef;
-
-/** 
-  * @brief Serial Audio Interface
-  */
-  
-typedef struct
-{
-  __IO uint32_t GCR;      /*!< SAI global configuration register,        Address offset: 0x00 */
-} SAI_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */
-  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */
-  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */
-  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */
-  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
-  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */
-  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */
-  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */
-} SAI_Block_TypeDef;
-
-/** 
-  * @brief SD host Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t POWER;          /*!< SDIO power control register,    Address offset: 0x00 */
-  __IO uint32_t CLKCR;          /*!< SDI clock control register,     Address offset: 0x04 */
-  __IO uint32_t ARG;            /*!< SDIO argument register,         Address offset: 0x08 */
-  __IO uint32_t CMD;            /*!< SDIO command register,          Address offset: 0x0C */
-  __I uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */
-  __I uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */
-  __I uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */
-  __I uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */
-  __I uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */
-  __IO uint32_t DTIMER;         /*!< SDIO data timer register,       Address offset: 0x24 */
-  __IO uint32_t DLEN;           /*!< SDIO data length register,      Address offset: 0x28 */
-  __IO uint32_t DCTRL;          /*!< SDIO data control register,     Address offset: 0x2C */
-  __I uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */
-  __I uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */
-  __IO uint32_t ICR;            /*!< SDIO interrupt clear register,  Address offset: 0x38 */
-  __IO uint32_t MASK;           /*!< SDIO mask register,             Address offset: 0x3C */
-  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
-  __I uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */
-  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
-  __IO uint32_t FIFO;           /*!< SDIO data FIFO register,        Address offset: 0x80 */
-} SDIO_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
-  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
-  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
-  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Crypto Processor
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;         /*!< CRYP control register,                                    Address offset: 0x00 */
-  __IO uint32_t SR;         /*!< CRYP status register,                                     Address offset: 0x04 */
-  __IO uint32_t DR;         /*!< CRYP data input register,                                 Address offset: 0x08 */
-  __IO uint32_t DOUT;       /*!< CRYP data output register,                                Address offset: 0x0C */
-  __IO uint32_t DMACR;      /*!< CRYP DMA control register,                                Address offset: 0x10 */
-  __IO uint32_t IMSCR;      /*!< CRYP interrupt mask set/clear register,                   Address offset: 0x14 */
-  __IO uint32_t RISR;       /*!< CRYP raw interrupt status register,                       Address offset: 0x18 */
-  __IO uint32_t MISR;       /*!< CRYP masked interrupt status register,                    Address offset: 0x1C */
-  __IO uint32_t K0LR;       /*!< CRYP key left  register 0,                                Address offset: 0x20 */
-  __IO uint32_t K0RR;       /*!< CRYP key right register 0,                                Address offset: 0x24 */
-  __IO uint32_t K1LR;       /*!< CRYP key left  register 1,                                Address offset: 0x28 */
-  __IO uint32_t K1RR;       /*!< CRYP key right register 1,                                Address offset: 0x2C */
-  __IO uint32_t K2LR;       /*!< CRYP key left  register 2,                                Address offset: 0x30 */
-  __IO uint32_t K2RR;       /*!< CRYP key right register 2,                                Address offset: 0x34 */
-  __IO uint32_t K3LR;       /*!< CRYP key left  register 3,                                Address offset: 0x38 */
-  __IO uint32_t K3RR;       /*!< CRYP key right register 3,                                Address offset: 0x3C */
-  __IO uint32_t IV0LR;      /*!< CRYP initialization vector left-word  register 0,         Address offset: 0x40 */
-  __IO uint32_t IV0RR;      /*!< CRYP initialization vector right-word register 0,         Address offset: 0x44 */
-  __IO uint32_t IV1LR;      /*!< CRYP initialization vector left-word  register 1,         Address offset: 0x48 */
-  __IO uint32_t IV1RR;      /*!< CRYP initialization vector right-word register 1,         Address offset: 0x4C */
-  __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0,        Address offset: 0x50 */
-  __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1,        Address offset: 0x54 */
-  __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2,        Address offset: 0x58 */
-  __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3,        Address offset: 0x5C */
-  __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4,        Address offset: 0x60 */
-  __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5,        Address offset: 0x64 */
-  __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6,        Address offset: 0x68 */
-  __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7,        Address offset: 0x6C */
-  __IO uint32_t CSGCM0R;    /*!< CRYP GCM/GMAC context swap register 0,                    Address offset: 0x70 */
-  __IO uint32_t CSGCM1R;    /*!< CRYP GCM/GMAC context swap register 1,                    Address offset: 0x74 */
-  __IO uint32_t CSGCM2R;    /*!< CRYP GCM/GMAC context swap register 2,                    Address offset: 0x78 */
-  __IO uint32_t CSGCM3R;    /*!< CRYP GCM/GMAC context swap register 3,                    Address offset: 0x7C */
-  __IO uint32_t CSGCM4R;    /*!< CRYP GCM/GMAC context swap register 4,                    Address offset: 0x80 */
-  __IO uint32_t CSGCM5R;    /*!< CRYP GCM/GMAC context swap register 5,                    Address offset: 0x84 */
-  __IO uint32_t CSGCM6R;    /*!< CRYP GCM/GMAC context swap register 6,                    Address offset: 0x88 */
-  __IO uint32_t CSGCM7R;    /*!< CRYP GCM/GMAC context swap register 7,                    Address offset: 0x8C */
-} CRYP_TypeDef;
-
-/** 
-  * @brief HASH
-  */
-  
-typedef struct 
-{
-  __IO uint32_t CR;               /*!< HASH control register,          Address offset: 0x00        */
-  __IO uint32_t DIN;              /*!< HASH data input register,       Address offset: 0x04        */
-  __IO uint32_t STR;              /*!< HASH start register,            Address offset: 0x08        */
-  __IO uint32_t HR[5];            /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */
-  __IO uint32_t IMR;              /*!< HASH interrupt enable register, Address offset: 0x20        */
-  __IO uint32_t SR;               /*!< HASH status register,           Address offset: 0x24        */
-       uint32_t RESERVED[52];     /*!< Reserved, 0x28-0xF4                                         */
-  __IO uint32_t CSR[54];          /*!< HASH context swap registers,    Address offset: 0x0F8-0x1CC */
-} HASH_TypeDef;
-
-/** 
-  * @brief HASH_DIGEST
-  */
-  
-typedef struct 
-{
-  __IO uint32_t HR[8];     /*!< HASH digest registers,          Address offset: 0x310-0x32C */ 
-} HASH_DIGEST_TypeDef;
-
-/** 
-  * @brief RNG
-  */
-  
-typedef struct 
-{
-  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
-  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
-  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
-} RNG_TypeDef;
-
- 
-/** 
-  * @brief __USB_OTG_Core_register
-  */
-typedef struct
-{
-  __IO uint32_t GOTGCTL;      /*!<  USB_OTG Control and Status Register    000h */
-  __IO uint32_t GOTGINT;      /*!<  USB_OTG Interrupt Register             004h */
-  __IO uint32_t GAHBCFG;      /*!<  Core AHB Configuration Register        008h */
-  __IO uint32_t GUSBCFG;      /*!<  Core USB Configuration Register        00Ch */
-  __IO uint32_t GRSTCTL;      /*!<  Core Reset Register                    010h */
-  __IO uint32_t GINTSTS;      /*!<  Core Interrupt Register                014h */
-  __IO uint32_t GINTMSK;      /*!<  Core Interrupt Mask Register           018h */
-  __IO uint32_t GRXSTSR;      /*!<  Receive Sts Q Read Register            01Ch */
-  __IO uint32_t GRXSTSP;      /*!<  Receive Sts Q Read & POP Register      020h */
-  __IO uint32_t GRXFSIZ;      /* Receive FIFO Size Register                024h */
-  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!<  EP0 / Non Periodic Tx FIFO Size Register 028h*/
-  __IO uint32_t HNPTXSTS;     /*!<  Non Periodic Tx FIFO/Queue Sts reg     02Ch */
-  uint32_t Reserved30[2];     /* Reserved                           030h*/
-  __IO uint32_t GCCFG;        /* General Purpose IO Register        038h*/
-  __IO uint32_t CID;          /* User ID Register                   03Ch*/
-  uint32_t  Reserved40[48];   /* Reserved                      040h-0FFh*/
-  __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg     100h*/
-  __IO uint32_t DIEPTXF[0x0F];/* dev Periodic Transmit FIFO */
-}
-USB_OTG_GlobalTypeDef;
-
-
-/** 
-  * @brief __device_Registers
-  */
-typedef struct 
-{
-  __IO uint32_t DCFG;         /* dev Configuration Register   800h*/
-  __IO uint32_t DCTL;         /* dev Control Register         804h*/
-  __IO uint32_t DSTS;         /* dev Status Register (RO)     808h*/
-  uint32_t Reserved0C;           /* Reserved                     80Ch*/
-  __IO uint32_t DIEPMSK;   /* dev IN Endpoint Mask         810h*/
-  __IO uint32_t DOEPMSK;  /* dev OUT Endpoint Mask        814h*/
-  __IO uint32_t DAINT;     /* dev All Endpoints Itr Reg    818h*/
-  __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask   81Ch*/
-  uint32_t  Reserved20;          /* Reserved                     820h*/
-  uint32_t Reserved9;       /* Reserved                     824h*/
-  __IO uint32_t DVBUSDIS;    /* dev VBUS discharge Register  828h*/
-  __IO uint32_t DVBUSPULSE;  /* dev VBUS Pulse Register      82Ch*/
-  __IO uint32_t DTHRCTL;     /* dev thr                      830h*/
-  __IO uint32_t DIEPEMPMSK; /* dev empty msk             834h*/
-  __IO uint32_t DEACHINT;    /* dedicated EP interrupt       838h*/
-  __IO uint32_t DEACHMSK;    /* dedicated EP msk             83Ch*/  
-  uint32_t Reserved40;      /* dedicated EP mask           840h*/
-  __IO uint32_t DINEP1MSK;  /* dedicated EP mask           844h*/
-  uint32_t  Reserved44[15];      /* Reserved                 844-87Ch*/
-  __IO uint32_t DOUTEP1MSK; /* dedicated EP msk            884h*/   
-}
-USB_OTG_DeviceTypeDef;
-
-
-/** 
-  * @brief __IN_Endpoint-Specific_Register
-  */
-typedef struct 
-{
-  __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
-  uint32_t Reserved04;             /* Reserved                       900h + (ep_num * 20h) + 04h*/
-  __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg     900h + (ep_num * 20h) + 08h*/
-  uint32_t Reserved0C;             /* Reserved                       900h + (ep_num * 20h) + 0Ch*/
-  __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size   900h + (ep_num * 20h) + 10h*/
-  __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h*/
-  __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
-  uint32_t Reserved18;             /* Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
-}
-USB_OTG_INEndpointTypeDef;
-
-
-/** 
-  * @brief __OUT_Endpoint-Specific_Registers
-  */
-typedef struct 
-{
-  __IO uint32_t DOEPCTL;       /* dev OUT Endpoint Control Reg  B00h + (ep_num * 20h) + 00h*/
-  uint32_t Reserved04;         /* Reserved                      B00h + (ep_num * 20h) + 04h*/
-  __IO uint32_t DOEPINT;       /* dev OUT Endpoint Itr Reg      B00h + (ep_num * 20h) + 08h*/
-  uint32_t Reserved0C;         /* Reserved                      B00h + (ep_num * 20h) + 0Ch*/
-  __IO uint32_t DOEPTSIZ;      /* dev OUT Endpoint Txfer Size   B00h + (ep_num * 20h) + 10h*/
-  __IO uint32_t DOEPDMA;       /* dev OUT Endpoint DMA Address  B00h + (ep_num * 20h) + 14h*/
-  uint32_t Reserved18[2];      /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
-}
-USB_OTG_OUTEndpointTypeDef;
-
-
-/** 
-  * @brief __Host_Mode_Register_Structures
-  */
-typedef struct 
-{
-  __IO uint32_t HCFG;             /* Host Configuration Register    400h*/
-  __IO uint32_t HFIR;      /* Host Frame Interval Register   404h*/
-  __IO uint32_t HFNUM;         /* Host Frame Nbr/Frame Remaining 408h*/
-  uint32_t Reserved40C;                   /* Reserved                       40Ch*/
-  __IO uint32_t HPTXSTS;   /* Host Periodic Tx FIFO/ Queue Status 410h*/
-  __IO uint32_t HAINT;   /* Host All Channels Interrupt Register 414h*/
-  __IO uint32_t HAINTMSK;   /* Host All Channels Interrupt Mask 418h*/
-}
-USB_OTG_HostTypeDef;
-
-/** 
-  * @brief __Host_Channel_Specific_Registers
-  */
-typedef struct
-{
-  __IO uint32_t HCCHAR;
-  __IO uint32_t HCSPLT;
-  __IO uint32_t HCINT;
-  __IO uint32_t HCINTMSK;
-  __IO uint32_t HCTSIZ;
-  __IO uint32_t HCDMA;
-  uint32_t Reserved[2];
-}
-USB_OTG_HostChannelTypeDef;
-/**
-  * @}
-  */
-    
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-#define FLASH_BASE            0x08000000U /*!< FLASH(up to 2 MB) base address in the alias region                         */
-#define CCMDATARAM_BASE       0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
-#define SRAM1_BASE            0x20000000U /*!< SRAM1(112 KB) base address in the alias region                             */
-#define SRAM2_BASE            0x2001C000U /*!< SRAM2(16 KB) base address in the alias region                              */
-#define SRAM3_BASE            0x20020000U /*!< SRAM3(64 KB) base address in the alias region                              */
-#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region                                */
-#define BKPSRAM_BASE          0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region                         */
-#define FMC_R_BASE            0xA0000000U /*!< FMC registers base address                                                 */
-#define SRAM1_BB_BASE         0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region                             */
-#define SRAM2_BB_BASE         0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region                              */
-#define SRAM3_BB_BASE         0x22400000U /*!< SRAM3(64 KB) base address in the bit-band region                              */
-#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region                                */
-#define BKPSRAM_BB_BASE       0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region                         */
-#define FLASH_END             0x081FFFFFU /*!< FLASH end address */
-#define CCMDATARAM_END        0x1000FFFFU /*!< CCM data RAM end address */
-
-/* Legacy defines */
-#define SRAM_BASE             SRAM1_BASE
-#define SRAM_BB_BASE          SRAM1_BB_BASE
-
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000U)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)
-#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800U)
-#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00U)
-#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000U)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)
-#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400U)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)
-#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000U)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800U)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00U)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x5000U)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)
-#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)
-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)
-#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800U)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)
-#define UART7_BASE            (APB1PERIPH_BASE + 0x7800U)
-#define UART8_BASE            (APB1PERIPH_BASE + 0x7C00U)
-
-/*!< APB2 peripherals */
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000U)
-#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400U)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x1000U)
-#define USART6_BASE           (APB2PERIPH_BASE + 0x1400U)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000U)
-#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100U)
-#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200U)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x2300U)
-#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00U)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)
-#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400U)
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800U)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00U)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000U)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400U)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800U)
-#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000U)
-#define SPI6_BASE             (APB2PERIPH_BASE + 0x5400U)
-#define SAI1_BASE             (APB2PERIPH_BASE + 0x5800U)
-#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004U)
-#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024U)
-#define LTDC_BASE             (APB2PERIPH_BASE + 0x6800U)
-#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84U)
-#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104U) 
-
-/*!< AHB1 peripherals */
-#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000U)
-#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400U)
-#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800U)
-#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00U)
-#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000U)
-#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400U)
-#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800U)
-#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00U)
-#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000U)
-#define GPIOJ_BASE            (AHB1PERIPH_BASE + 0x2400U)
-#define GPIOK_BASE            (AHB1PERIPH_BASE + 0x2800U)
-#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)
-#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800U)
-#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00U)
-#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000U)
-#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010U)
-#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028U)
-#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040U)
-#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058U)
-#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070U)
-#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088U)
-#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0U)
-#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8U)
-#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400U)
-#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010U)
-#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028U)
-#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040U)
-#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058U)
-#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070U)
-#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088U)
-#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0U)
-#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)
-#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000U)
-#define ETH_MAC_BASE          (ETH_BASE)
-#define ETH_MMC_BASE          (ETH_BASE + 0x0100U)
-#define ETH_PTP_BASE          (ETH_BASE + 0x0700U)
-#define ETH_DMA_BASE          (ETH_BASE + 0x1000U)
-#define DMA2D_BASE            (AHB1PERIPH_BASE + 0xB000U)
-
-/*!< AHB2 peripherals */
-#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000U)
-#define CRYP_BASE             (AHB2PERIPH_BASE + 0x60000U)
-#define HASH_BASE             (AHB2PERIPH_BASE + 0x60400U)
-#define HASH_DIGEST_BASE      (AHB2PERIPH_BASE + 0x60710U)
-#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800U)
-
-/*!< FMC Bankx registers base address */
-#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000U)
-#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104U)
-#define FMC_Bank2_3_R_BASE    (FMC_R_BASE + 0x0060U)
-#define FMC_Bank4_R_BASE      (FMC_R_BASE + 0x00A0U)
-#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140U)
-
-/* Debug MCU registers base address */
-#define DBGMCU_BASE           0xE0042000U
-
-/*!< USB registers base address */
-#define USB_OTG_HS_PERIPH_BASE               0x40040000U
-#define USB_OTG_FS_PERIPH_BASE               0x50000000U
-
-#define USB_OTG_GLOBAL_BASE                  0x000U
-#define USB_OTG_DEVICE_BASE                  0x800U
-#define USB_OTG_IN_ENDPOINT_BASE             0x900U
-#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U
-#define USB_OTG_EP_REG_SIZE                  0x20U
-#define USB_OTG_HOST_BASE                    0x400U
-#define USB_OTG_HOST_PORT_BASE               0x440U
-#define USB_OTG_HOST_CHANNEL_BASE            0x500U
-#define USB_OTG_HOST_CHANNEL_SIZE            0x20U
-#define USB_OTG_PCGCCTL_BASE                 0xE00U
-#define USB_OTG_FIFO_BASE                    0x1000U
-#define USB_OTG_FIFO_SIZE                    0x1000U
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
-#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
-#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define UART4               ((USART_TypeDef *) UART4_BASE)
-#define UART5               ((USART_TypeDef *) UART5_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
-#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
-#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
-#define UART7               ((USART_TypeDef *) UART7_BASE)
-#define UART8               ((USART_TypeDef *) UART8_BASE)
-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
-#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define USART6              ((USART_TypeDef *) USART6_BASE)
-#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
-#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
-#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE) 
-#define SPI4                ((SPI_TypeDef *) SPI4_BASE)
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-#define SPI5                ((SPI_TypeDef *) SPI5_BASE)
-#define SPI6                ((SPI_TypeDef *) SPI6_BASE)
-#define SAI1                ((SAI_TypeDef *) SAI1_BASE)
-#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
-#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
-#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)
-#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
-#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
-
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
-#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)
-#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
-#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
-#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
-#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
-#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
-#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
-#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
-#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
-#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
-#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
-#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
-#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
-#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
-#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
-#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
-#define ETH                 ((ETH_TypeDef *) ETH_BASE)  
-#define DMA2D               ((DMA2D_TypeDef *)DMA2D_BASE)
-#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
-#define CRYP                ((CRYP_TypeDef *) CRYP_BASE)
-#define HASH                ((HASH_TypeDef *) HASH_BASE)
-#define HASH_DIGEST         ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
-#define RNG                 ((RNG_TypeDef *) RNG_BASE)
-#define FMC_Bank1           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
-#define FMC_Bank1E          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
-#define FMC_Bank2_3         ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
-#define FMC_Bank4           ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
-#define FMC_Bank5_6         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
-
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
-#define USB_OTG_HS          ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers_Bits_Definition               */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Analog to Digital Converter                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          0x00000001U        /*!<Analog watchdog flag */
-#define  ADC_SR_EOC                          0x00000002U        /*!<End of conversion */
-#define  ADC_SR_JEOC                         0x00000004U        /*!<Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        0x00000008U        /*!<Injected channel Start flag */
-#define  ADC_SR_STRT                         0x00000010U        /*!<Regular channel Start flag */
-#define  ADC_SR_OVR                          0x00000020U        /*!<Overrun flag */
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
-#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels */
-#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels */
-#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution) */
-#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
-  
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion */
-#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode */
-#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC) */
-#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection */
-#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment */
-#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      0xFFFFU            /*!<Injected data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag */
-#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion */
-#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag */
-#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag */
-#define  ADC_CSR_OVR1                        0x00000020U        /*!<ADC1 DMA overrun  flag */
-#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag */
-#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion */
-#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag */
-#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag */
-#define  ADC_CSR_OVR2                        0x00002000U        /*!<ADC2 DMA overrun  flag */
-#define  ADC_CSR_AWD3                        0x00010000U        /*!<ADC3 Analog watchdog flag */
-#define  ADC_CSR_EOC3                        0x00020000U        /*!<ADC3 End of conversion */
-#define  ADC_CSR_JEOC3                       0x00040000U        /*!<ADC3 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT3                      0x00080000U        /*!<ADC3 Injected channel Start flag */
-#define  ADC_CSR_STRT3                       0x00100000U        /*!<ADC3 Regular channel Start flag */
-#define  ADC_CSR_OVR3                        0x00200000U        /*!<ADC3 DMA overrun  flag */
-
-/* Legacy defines */
-#define  ADC_CSR_DOVR1                        ADC_CSR_OVR1
-#define  ADC_CSR_DOVR2                        ADC_CSR_OVR2
-#define  ADC_CSR_DOVR3                        ADC_CSR_OVR3
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
-#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
-#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
-#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
-#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
-
-/*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                      0x0000FFFFU         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                      0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Controller Area Network                            */
-/*                                                                            */
-/******************************************************************************/
-/*!<CAN control and status registers */
-/*******************  Bit definition for CAN_MCR register  ********************/
-#define  CAN_MCR_INRQ                        0x00000001U        /*!<Initialization Request */
-#define  CAN_MCR_SLEEP                       0x00000002U        /*!<Sleep Mode Request */
-#define  CAN_MCR_TXFP                        0x00000004U        /*!<Transmit FIFO Priority */
-#define  CAN_MCR_RFLM                        0x00000008U        /*!<Receive FIFO Locked Mode */
-#define  CAN_MCR_NART                        0x00000010U        /*!<No Automatic Retransmission */
-#define  CAN_MCR_AWUM                        0x00000020U        /*!<Automatic Wakeup Mode */
-#define  CAN_MCR_ABOM                        0x00000040U        /*!<Automatic Bus-Off Management */
-#define  CAN_MCR_TTCM                        0x00000080U        /*!<Time Triggered Communication Mode */
-#define  CAN_MCR_RESET                       0x00008000U        /*!<bxCAN software master reset */
-#define  CAN_MCR_DBF                         0x00010000U        /*!<bxCAN Debug freeze */
-/*******************  Bit definition for CAN_MSR register  ********************/
-#define  CAN_MSR_INAK                        0x0001U            /*!<Initialization Acknowledge */
-#define  CAN_MSR_SLAK                        0x0002U            /*!<Sleep Acknowledge */
-#define  CAN_MSR_ERRI                        0x0004U            /*!<Error Interrupt */
-#define  CAN_MSR_WKUI                        0x0008U            /*!<Wakeup Interrupt */
-#define  CAN_MSR_SLAKI                       0x0010U            /*!<Sleep Acknowledge Interrupt */
-#define  CAN_MSR_TXM                         0x0100U            /*!<Transmit Mode */
-#define  CAN_MSR_RXM                         0x0200U            /*!<Receive Mode */
-#define  CAN_MSR_SAMP                        0x0400U            /*!<Last Sample Point */
-#define  CAN_MSR_RX                          0x0800U            /*!<CAN Rx Signal */
-
-/*******************  Bit definition for CAN_TSR register  ********************/
-#define  CAN_TSR_RQCP0                       0x00000001U        /*!<Request Completed Mailbox0 */
-#define  CAN_TSR_TXOK0                       0x00000002U        /*!<Transmission OK of Mailbox0 */
-#define  CAN_TSR_ALST0                       0x00000004U        /*!<Arbitration Lost for Mailbox0 */
-#define  CAN_TSR_TERR0                       0x00000008U        /*!<Transmission Error of Mailbox0 */
-#define  CAN_TSR_ABRQ0                       0x00000080U        /*!<Abort Request for Mailbox0 */
-#define  CAN_TSR_RQCP1                       0x00000100U        /*!<Request Completed Mailbox1 */
-#define  CAN_TSR_TXOK1                       0x00000200U        /*!<Transmission OK of Mailbox1 */
-#define  CAN_TSR_ALST1                       0x00000400U        /*!<Arbitration Lost for Mailbox1 */
-#define  CAN_TSR_TERR1                       0x00000800U        /*!<Transmission Error of Mailbox1 */
-#define  CAN_TSR_ABRQ1                       0x00008000U        /*!<Abort Request for Mailbox 1 */
-#define  CAN_TSR_RQCP2                       0x00010000U        /*!<Request Completed Mailbox2 */
-#define  CAN_TSR_TXOK2                       0x00020000U        /*!<Transmission OK of Mailbox 2 */
-#define  CAN_TSR_ALST2                       0x00040000U        /*!<Arbitration Lost for mailbox 2 */
-#define  CAN_TSR_TERR2                       0x00080000U        /*!<Transmission Error of Mailbox 2 */
-#define  CAN_TSR_ABRQ2                       0x00800000U        /*!<Abort Request for Mailbox 2 */
-#define  CAN_TSR_CODE                        0x03000000U        /*!<Mailbox Code */
-
-#define  CAN_TSR_TME                         0x1C000000U        /*!<TME[2:0] bits */
-#define  CAN_TSR_TME0                        0x04000000U        /*!<Transmit Mailbox 0 Empty */
-#define  CAN_TSR_TME1                        0x08000000U        /*!<Transmit Mailbox 1 Empty */
-#define  CAN_TSR_TME2                        0x10000000U        /*!<Transmit Mailbox 2 Empty */
-
-#define  CAN_TSR_LOW                         0xE0000000U        /*!<LOW[2:0] bits */
-#define  CAN_TSR_LOW0                        0x20000000U        /*!<Lowest Priority Flag for Mailbox 0 */
-#define  CAN_TSR_LOW1                        0x40000000U        /*!<Lowest Priority Flag for Mailbox 1 */
-#define  CAN_TSR_LOW2                        0x80000000U        /*!<Lowest Priority Flag for Mailbox 2 */
-
-/*******************  Bit definition for CAN_RF0R register  *******************/
-#define  CAN_RF0R_FMP0                       0x03U               /*!<FIFO 0 Message Pending */
-#define  CAN_RF0R_FULL0                      0x08U               /*!<FIFO 0 Full */
-#define  CAN_RF0R_FOVR0                      0x10U               /*!<FIFO 0 Overrun */
-#define  CAN_RF0R_RFOM0                      0x20U               /*!<Release FIFO 0 Output Mailbox */
-
-/*******************  Bit definition for CAN_RF1R register  *******************/
-#define  CAN_RF1R_FMP1                       0x03U               /*!<FIFO 1 Message Pending */
-#define  CAN_RF1R_FULL1                      0x08U               /*!<FIFO 1 Full */
-#define  CAN_RF1R_FOVR1                      0x10U               /*!<FIFO 1 Overrun */
-#define  CAN_RF1R_RFOM1                      0x20U               /*!<Release FIFO 1 Output Mailbox */
-
-/********************  Bit definition for CAN_IER register  *******************/
-#define  CAN_IER_TMEIE                       0x00000001U        /*!<Transmit Mailbox Empty Interrupt Enable */
-#define  CAN_IER_FMPIE0                      0x00000002U        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE0                       0x00000004U        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE0                      0x00000008U        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_FMPIE1                      0x00000010U        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE1                       0x00000020U        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE1                      0x00000040U        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error Warning Interrupt Enable */
-#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error Passive Interrupt Enable */
-#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-Off Interrupt Enable */
-#define  CAN_IER_LECIE                       0x00000800U        /*!<Last Error Code Interrupt Enable */
-#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error Interrupt Enable */
-#define  CAN_IER_WKUIE                       0x00010000U        /*!<Wakeup Interrupt Enable */
-#define  CAN_IER_SLKIE                       0x00020000U        /*!<Sleep Interrupt Enable */
-#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error warning interrupt enable */
-#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error passive interrupt enable */
-#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-off interrupt enable */
-#define  CAN_IER_LECIE                       0x00000800U        /*!<Last error code interrupt enable */
-#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error interrupt enable */
-
-
-/********************  Bit definition for CAN_ESR register  *******************/
-#define  CAN_ESR_EWGF                        0x00000001U        /*!<Error Warning Flag */
-#define  CAN_ESR_EPVF                        0x00000002U        /*!<Error Passive Flag */
-#define  CAN_ESR_BOFF                        0x00000004U        /*!<Bus-Off Flag */
-
-#define  CAN_ESR_LEC                         0x00000070U        /*!<LEC[2:0] bits (Last Error Code) */
-#define  CAN_ESR_LEC_0                       0x00000010U        /*!<Bit 0 */
-#define  CAN_ESR_LEC_1                       0x00000020U        /*!<Bit 1 */
-#define  CAN_ESR_LEC_2                       0x00000040U        /*!<Bit 2 */
-
-#define  CAN_ESR_TEC                         0x00FF0000U        /*!<Least significant byte of the 9-bit Transmit Error Counter */
-#define  CAN_ESR_REC                         0xFF000000U        /*!<Receive Error Counter */
-
-/*******************  Bit definition for CAN_BTR register  ********************/
-#define  CAN_BTR_BRP                         0x000003FFU        /*!<Baud Rate Prescaler */
-#define  CAN_BTR_TS1                         0x000F0000U        /*!<Time Segment 1 */
-#define  CAN_BTR_TS1_0                       0x00010000U        /*!<Bit 0 */
-#define  CAN_BTR_TS1_1                       0x00020000U        /*!<Bit 1 */
-#define  CAN_BTR_TS1_2                       0x00040000U        /*!<Bit 2 */
-#define  CAN_BTR_TS1_3                       0x00080000U        /*!<Bit 3 */
-#define  CAN_BTR_TS2                         0x00700000U        /*!<Time Segment 2 */
-#define  CAN_BTR_TS2_0                       0x00100000U        /*!<Bit 0 */
-#define  CAN_BTR_TS2_1                       0x00200000U        /*!<Bit 1 */
-#define  CAN_BTR_TS2_2                       0x00400000U        /*!<Bit 2 */
-#define  CAN_BTR_SJW                         0x03000000U        /*!<Resynchronization Jump Width */
-#define  CAN_BTR_SJW_0                       0x01000000U        /*!<Bit 0 */
-#define  CAN_BTR_SJW_1                       0x02000000U        /*!<Bit 1 */
-#define  CAN_BTR_LBKM                        0x40000000U        /*!<Loop Back Mode (Debug) */
-#define  CAN_BTR_SILM                        0x80000000U        /*!<Silent Mode */
-
-
-/*!<Mailbox registers */
-/******************  Bit definition for CAN_TI0R register  ********************/
-#define  CAN_TI0R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI0R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_TI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/******************  Bit definition for CAN_TDT0R register  *******************/
-#define  CAN_TDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT0R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/******************  Bit definition for CAN_TDL0R register  *******************/
-#define  CAN_TDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/******************  Bit definition for CAN_TDH0R register  *******************/
-#define  CAN_TDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI1R register  *******************/
-#define  CAN_TI1R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI1R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI1R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_TI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT1R register  ******************/
-#define  CAN_TDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT1R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL1R register  ******************/
-#define  CAN_TDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH1R register  ******************/
-#define  CAN_TDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI2R register  *******************/
-#define  CAN_TI2R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI2R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI2R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI2R_EXID                       0x001FFFF8U        /*!<Extended identifier */
-#define  CAN_TI2R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT2R register  ******************/  
-#define  CAN_TDT2R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT2R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT2R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL2R register  ******************/
-#define  CAN_TDL2R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL2R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL2R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL2R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH2R register  ******************/
-#define  CAN_TDH2R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH2R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH2R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH2R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI0R register  *******************/
-#define  CAN_RI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_RI0R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_RI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_RI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT0R register  ******************/
-#define  CAN_RDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_RDT0R_FMI                       0x0000FF00U        /*!<Filter Match Index */
-#define  CAN_RDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL0R register  ******************/
-#define  CAN_RDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_RDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_RDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_RDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH0R register  ******************/
-#define  CAN_RDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_RDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_RDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_RDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI1R register  *******************/
-#define  CAN_RI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_RI1R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_RI1R_EXID                       0x001FFFF8U        /*!<Extended identifier */
-#define  CAN_RI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT1R register  ******************/
-#define  CAN_RDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_RDT1R_FMI                       0x0000FF00U        /*!<Filter Match Index */
-#define  CAN_RDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL1R register  ******************/
-#define  CAN_RDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_RDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_RDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_RDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH1R register  ******************/
-#define  CAN_RDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_RDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_RDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_RDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*!<CAN filter registers */
-/*******************  Bit definition for CAN_FMR register  ********************/
-#define  CAN_FMR_FINIT                       0x01U               /*!<Filter Init Mode */
-#define  CAN_FMR_CAN2SB                      0x00003F00U        /*!<CAN2 start bank */
-
-/*******************  Bit definition for CAN_FM1R register  *******************/
-#define  CAN_FM1R_FBM                        0x0FFFFFFFU        /*!<Filter Mode */
-#define  CAN_FM1R_FBM0                       0x00000001U        /*!<Filter Init Mode bit 0 */
-#define  CAN_FM1R_FBM1                       0x00000002U        /*!<Filter Init Mode bit 1 */
-#define  CAN_FM1R_FBM2                       0x00000004U        /*!<Filter Init Mode bit 2 */
-#define  CAN_FM1R_FBM3                       0x00000008U        /*!<Filter Init Mode bit 3 */
-#define  CAN_FM1R_FBM4                       0x00000010U        /*!<Filter Init Mode bit 4 */
-#define  CAN_FM1R_FBM5                       0x00000020U        /*!<Filter Init Mode bit 5 */
-#define  CAN_FM1R_FBM6                       0x00000040U        /*!<Filter Init Mode bit 6 */
-#define  CAN_FM1R_FBM7                       0x00000080U        /*!<Filter Init Mode bit 7 */
-#define  CAN_FM1R_FBM8                       0x00000100U        /*!<Filter Init Mode bit 8 */
-#define  CAN_FM1R_FBM9                       0x00000200U        /*!<Filter Init Mode bit 9 */
-#define  CAN_FM1R_FBM10                      0x00000400U        /*!<Filter Init Mode bit 10 */
-#define  CAN_FM1R_FBM11                      0x00000800U        /*!<Filter Init Mode bit 11 */
-#define  CAN_FM1R_FBM12                      0x00001000U        /*!<Filter Init Mode bit 12 */
-#define  CAN_FM1R_FBM13                      0x00002000U        /*!<Filter Init Mode bit 13 */
-#define  CAN_FM1R_FBM14                      0x00004000U        /*!<Filter Init Mode bit 14 */
-#define  CAN_FM1R_FBM15                      0x00008000U        /*!<Filter Init Mode bit 15 */
-#define  CAN_FM1R_FBM16                      0x00010000U        /*!<Filter Init Mode bit 16 */
-#define  CAN_FM1R_FBM17                      0x00020000U        /*!<Filter Init Mode bit 17 */
-#define  CAN_FM1R_FBM18                      0x00040000U        /*!<Filter Init Mode bit 18 */
-#define  CAN_FM1R_FBM19                      0x00080000U        /*!<Filter Init Mode bit 19 */
-#define  CAN_FM1R_FBM20                      0x00100000U        /*!<Filter Init Mode bit 20 */
-#define  CAN_FM1R_FBM21                      0x00200000U        /*!<Filter Init Mode bit 21 */
-#define  CAN_FM1R_FBM22                      0x00400000U        /*!<Filter Init Mode bit 22 */
-#define  CAN_FM1R_FBM23                      0x00800000U        /*!<Filter Init Mode bit 23 */
-#define  CAN_FM1R_FBM24                      0x01000000U        /*!<Filter Init Mode bit 24 */
-#define  CAN_FM1R_FBM25                      0x02000000U        /*!<Filter Init Mode bit 25 */
-#define  CAN_FM1R_FBM26                      0x04000000U        /*!<Filter Init Mode bit 26 */
-#define  CAN_FM1R_FBM27                      0x08000000U        /*!<Filter Init Mode bit 27 */
-
-/*******************  Bit definition for CAN_FS1R register  *******************/
-#define  CAN_FS1R_FSC                        0x0FFFFFFFU        /*!<Filter Scale Configuration */
-#define  CAN_FS1R_FSC0                       0x00000001U        /*!<Filter Scale Configuration bit 0 */
-#define  CAN_FS1R_FSC1                       0x00000002U        /*!<Filter Scale Configuration bit 1 */
-#define  CAN_FS1R_FSC2                       0x00000004U        /*!<Filter Scale Configuration bit 2 */
-#define  CAN_FS1R_FSC3                       0x00000008U        /*!<Filter Scale Configuration bit 3 */
-#define  CAN_FS1R_FSC4                       0x00000010U        /*!<Filter Scale Configuration bit 4 */
-#define  CAN_FS1R_FSC5                       0x00000020U        /*!<Filter Scale Configuration bit 5 */
-#define  CAN_FS1R_FSC6                       0x00000040U        /*!<Filter Scale Configuration bit 6 */
-#define  CAN_FS1R_FSC7                       0x00000080U        /*!<Filter Scale Configuration bit 7 */
-#define  CAN_FS1R_FSC8                       0x00000100U        /*!<Filter Scale Configuration bit 8 */
-#define  CAN_FS1R_FSC9                       0x00000200U        /*!<Filter Scale Configuration bit 9 */
-#define  CAN_FS1R_FSC10                      0x00000400U        /*!<Filter Scale Configuration bit 10 */
-#define  CAN_FS1R_FSC11                      0x00000800U        /*!<Filter Scale Configuration bit 11 */
-#define  CAN_FS1R_FSC12                      0x00001000U        /*!<Filter Scale Configuration bit 12 */
-#define  CAN_FS1R_FSC13                      0x00002000U        /*!<Filter Scale Configuration bit 13 */
-#define  CAN_FS1R_FSC14                      0x00004000U        /*!<Filter Scale Configuration bit 14 */
-#define  CAN_FS1R_FSC15                      0x00008000U        /*!<Filter Scale Configuration bit 15 */
-#define  CAN_FS1R_FSC16                      0x00010000U        /*!<Filter Scale Configuration bit 16 */
-#define  CAN_FS1R_FSC17                      0x00020000U        /*!<Filter Scale Configuration bit 17 */
-#define  CAN_FS1R_FSC18                      0x00040000U        /*!<Filter Scale Configuration bit 18 */
-#define  CAN_FS1R_FSC19                      0x00080000U        /*!<Filter Scale Configuration bit 19 */
-#define  CAN_FS1R_FSC20                      0x00100000U        /*!<Filter Scale Configuration bit 20 */
-#define  CAN_FS1R_FSC21                      0x00200000U        /*!<Filter Scale Configuration bit 21 */
-#define  CAN_FS1R_FSC22                      0x00400000U        /*!<Filter Scale Configuration bit 22 */
-#define  CAN_FS1R_FSC23                      0x00800000U        /*!<Filter Scale Configuration bit 23 */
-#define  CAN_FS1R_FSC24                      0x01000000U        /*!<Filter Scale Configuration bit 24 */
-#define  CAN_FS1R_FSC25                      0x02000000U        /*!<Filter Scale Configuration bit 25 */
-#define  CAN_FS1R_FSC26                      0x04000000U        /*!<Filter Scale Configuration bit 26 */
-#define  CAN_FS1R_FSC27                      0x08000000U        /*!<Filter Scale Configuration bit 27 */
-
-/******************  Bit definition for CAN_FFA1R register  *******************/
-#define  CAN_FFA1R_FFA                        0x0FFFFFFFU        /*!<Filter FIFO Assignment */
-#define  CAN_FFA1R_FFA0                       0x00000001U        /*!<Filter FIFO Assignment bit 0 */
-#define  CAN_FFA1R_FFA1                       0x00000002U        /*!<Filter FIFO Assignment bit 1 */
-#define  CAN_FFA1R_FFA2                       0x00000004U        /*!<Filter FIFO Assignment bit 2 */
-#define  CAN_FFA1R_FFA3                       0x00000008U        /*!<Filter FIFO Assignment bit 3 */
-#define  CAN_FFA1R_FFA4                       0x00000010U        /*!<Filter FIFO Assignment bit 4 */
-#define  CAN_FFA1R_FFA5                       0x00000020U        /*!<Filter FIFO Assignment bit 5 */
-#define  CAN_FFA1R_FFA6                       0x00000040U        /*!<Filter FIFO Assignment bit 6 */
-#define  CAN_FFA1R_FFA7                       0x00000080U        /*!<Filter FIFO Assignment bit 7 */
-#define  CAN_FFA1R_FFA8                       0x00000100U        /*!<Filter FIFO Assignment bit 8 */
-#define  CAN_FFA1R_FFA9                       0x00000200U        /*!<Filter FIFO Assignment bit 9 */
-#define  CAN_FFA1R_FFA10                      0x00000400U        /*!<Filter FIFO Assignment bit 10 */
-#define  CAN_FFA1R_FFA11                      0x00000800U        /*!<Filter FIFO Assignment bit 11 */
-#define  CAN_FFA1R_FFA12                      0x00001000U        /*!<Filter FIFO Assignment bit 12 */
-#define  CAN_FFA1R_FFA13                      0x00002000U        /*!<Filter FIFO Assignment bit 13 */
-#define  CAN_FFA1R_FFA14                      0x00004000U        /*!<Filter FIFO Assignment bit 14 */
-#define  CAN_FFA1R_FFA15                      0x00008000U        /*!<Filter FIFO Assignment bit 15 */
-#define  CAN_FFA1R_FFA16                      0x00010000U        /*!<Filter FIFO Assignment bit 16 */
-#define  CAN_FFA1R_FFA17                      0x00020000U        /*!<Filter FIFO Assignment bit 17 */
-#define  CAN_FFA1R_FFA18                      0x00040000U        /*!<Filter FIFO Assignment bit 18 */
-#define  CAN_FFA1R_FFA19                      0x00080000U        /*!<Filter FIFO Assignment bit 19 */
-#define  CAN_FFA1R_FFA20                      0x00100000U        /*!<Filter FIFO Assignment bit 20 */
-#define  CAN_FFA1R_FFA21                      0x00200000U        /*!<Filter FIFO Assignment bit 21 */
-#define  CAN_FFA1R_FFA22                      0x00400000U        /*!<Filter FIFO Assignment bit 22 */
-#define  CAN_FFA1R_FFA23                      0x00800000U        /*!<Filter FIFO Assignment bit 23 */
-#define  CAN_FFA1R_FFA24                      0x01000000U        /*!<Filter FIFO Assignment bit 24 */
-#define  CAN_FFA1R_FFA25                      0x02000000U        /*!<Filter FIFO Assignment bit 25 */
-#define  CAN_FFA1R_FFA26                      0x04000000U        /*!<Filter FIFO Assignment bit 26 */
-#define  CAN_FFA1R_FFA27                      0x08000000U        /*!<Filter FIFO Assignment bit 27 */
-
-/*******************  Bit definition for CAN_FA1R register  *******************/
-#define  CAN_FA1R_FACT                        0x0FFFFFFFU        /*!<Filter Active */
-#define  CAN_FA1R_FACT0                       0x00000001U        /*!<Filter Active bit 0 */
-#define  CAN_FA1R_FACT1                       0x00000002U        /*!<Filter Active bit 1 */
-#define  CAN_FA1R_FACT2                       0x00000004U        /*!<Filter Active bit 2 */
-#define  CAN_FA1R_FACT3                       0x00000008U        /*!<Filter Active bit 3 */
-#define  CAN_FA1R_FACT4                       0x00000010U        /*!<Filter Active bit 4 */
-#define  CAN_FA1R_FACT5                       0x00000020U        /*!<Filter Active bit 5 */
-#define  CAN_FA1R_FACT6                       0x00000040U        /*!<Filter Active bit 6 */
-#define  CAN_FA1R_FACT7                       0x00000080U        /*!<Filter Active bit 7 */
-#define  CAN_FA1R_FACT8                       0x00000100U        /*!<Filter Active bit 8 */
-#define  CAN_FA1R_FACT9                       0x00000200U        /*!<Filter Active bit 9 */
-#define  CAN_FA1R_FACT10                      0x00000400U        /*!<Filter Active bit 10 */
-#define  CAN_FA1R_FACT11                      0x00000800U        /*!<Filter Active bit 11 */
-#define  CAN_FA1R_FACT12                      0x00001000U        /*!<Filter Active bit 12 */
-#define  CAN_FA1R_FACT13                      0x00002000U        /*!<Filter Active bit 13 */
-#define  CAN_FA1R_FACT14                      0x00004000U        /*!<Filter Active bit 14 */
-#define  CAN_FA1R_FACT15                      0x00008000U        /*!<Filter Active bit 15 */
-#define  CAN_FA1R_FACT16                      0x00010000U        /*!<Filter Active bit 16 */
-#define  CAN_FA1R_FACT17                      0x00020000U        /*!<Filter Active bit 17 */
-#define  CAN_FA1R_FACT18                      0x00040000U        /*!<Filter Active bit 18 */
-#define  CAN_FA1R_FACT19                      0x00080000U        /*!<Filter Active bit 19 */
-#define  CAN_FA1R_FACT20                      0x00100000U        /*!<Filter Active bit 20 */
-#define  CAN_FA1R_FACT21                      0x00200000U        /*!<Filter Active bit 21 */
-#define  CAN_FA1R_FACT22                      0x00400000U        /*!<Filter Active bit 22 */
-#define  CAN_FA1R_FACT23                      0x00800000U        /*!<Filter Active bit 23 */
-#define  CAN_FA1R_FACT24                      0x01000000U        /*!<Filter Active bit 24 */
-#define  CAN_FA1R_FACT25                      0x02000000U        /*!<Filter Active bit 25 */
-#define  CAN_FA1R_FACT26                      0x04000000U        /*!<Filter Active bit 26 */
-#define  CAN_FA1R_FACT27                      0x08000000U        /*!<Filter Active bit 27 */
-
-/*******************  Bit definition for CAN_F0R1 register  *******************/
-#define  CAN_F0R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F0R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F0R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F0R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F0R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F0R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F0R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F0R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F0R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F0R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F0R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F0R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F0R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F0R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F0R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F0R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F0R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F0R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F0R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F0R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F0R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F0R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F0R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F0R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F0R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F0R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F0R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F0R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F0R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F0R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F0R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F0R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R1 register  *******************/
-#define  CAN_F1R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F1R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F1R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F1R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F1R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F1R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F1R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F1R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F1R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F1R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F1R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F1R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F1R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F1R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F1R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F1R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F1R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F1R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F1R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F1R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F1R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F1R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F1R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F1R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F1R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F1R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F1R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F1R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F1R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F1R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F1R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F1R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R1 register  *******************/
-#define  CAN_F2R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F2R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F2R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F2R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F2R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F2R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F2R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F2R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F2R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F2R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F2R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F2R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F2R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F2R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F2R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F2R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F2R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F2R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F2R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F2R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F2R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F2R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F2R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F2R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F2R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F2R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F2R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F2R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F2R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F2R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F2R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F2R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R1 register  *******************/
-#define  CAN_F3R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F3R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F3R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F3R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F3R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F3R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F3R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F3R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F3R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F3R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F3R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F3R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F3R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F3R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F3R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F3R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F3R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F3R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F3R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F3R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F3R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F3R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F3R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F3R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F3R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F3R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F3R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F3R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F3R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F3R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F3R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F3R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R1 register  *******************/
-#define  CAN_F4R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F4R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F4R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F4R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F4R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F4R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F4R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F4R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F4R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F4R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F4R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F4R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F4R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F4R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F4R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F4R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F4R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F4R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F4R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F4R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F4R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F4R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F4R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F4R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F4R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F4R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F4R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F4R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F4R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F4R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F4R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F4R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R1 register  *******************/
-#define  CAN_F5R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F5R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F5R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F5R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F5R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F5R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F5R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F5R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F5R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F5R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F5R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F5R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F5R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F5R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F5R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F5R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F5R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F5R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F5R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F5R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F5R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F5R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F5R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F5R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F5R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F5R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F5R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F5R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F5R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F5R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F5R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F5R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R1 register  *******************/
-#define  CAN_F6R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F6R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F6R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F6R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F6R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F6R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F6R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F6R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F6R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F6R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F6R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F6R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F6R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F6R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F6R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F6R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F6R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F6R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F6R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F6R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F6R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F6R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F6R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F6R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F6R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F6R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F6R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F6R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F6R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F6R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F6R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F6R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R1 register  *******************/
-#define  CAN_F7R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F7R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F7R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F7R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F7R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F7R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F7R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F7R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F7R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F7R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F7R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F7R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F7R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F7R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F7R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F7R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F7R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F7R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F7R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F7R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F7R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F7R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F7R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F7R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F7R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F7R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F7R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F7R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F7R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F7R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F7R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F7R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R1 register  *******************/
-#define  CAN_F8R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F8R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F8R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F8R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F8R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F8R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F8R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F8R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F8R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F8R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F8R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F8R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F8R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F8R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F8R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F8R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F8R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F8R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F8R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F8R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F8R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F8R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F8R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F8R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F8R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F8R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F8R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F8R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F8R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F8R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F8R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F8R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R1 register  *******************/
-#define  CAN_F9R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F9R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F9R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F9R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F9R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F9R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F9R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F9R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F9R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F9R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F9R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F9R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F9R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F9R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F9R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F9R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F9R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F9R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F9R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F9R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F9R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F9R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F9R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F9R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F9R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F9R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F9R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F9R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F9R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F9R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F9R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F9R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R1 register  ******************/
-#define  CAN_F10R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F10R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F10R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F10R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F10R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F10R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F10R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F10R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F10R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F10R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F10R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F10R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F10R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F10R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F10R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F10R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F10R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F10R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F10R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F10R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F10R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F10R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F10R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F10R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F10R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F10R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F10R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F10R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F10R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F10R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F10R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F10R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R1 register  ******************/
-#define  CAN_F11R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F11R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F11R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F11R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F11R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F11R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F11R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F11R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F11R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F11R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F11R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F11R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F11R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F11R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F11R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F11R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F11R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F11R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F11R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F11R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F11R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F11R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F11R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F11R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F11R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F11R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F11R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F11R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F11R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F11R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F11R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F11R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R1 register  ******************/
-#define  CAN_F12R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F12R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F12R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F12R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F12R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F12R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F12R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F12R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F12R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F12R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F12R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F12R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F12R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F12R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F12R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F12R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F12R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F12R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F12R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F12R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F12R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F12R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F12R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F12R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F12R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F12R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F12R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F12R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F12R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F12R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F12R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F12R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R1 register  ******************/
-#define  CAN_F13R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F13R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F13R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F13R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F13R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F13R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F13R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F13R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F13R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F13R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F13R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F13R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F13R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F13R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F13R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F13R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F13R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F13R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F13R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F13R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F13R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F13R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F13R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F13R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F13R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F13R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F13R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F13R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F13R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F13R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F13R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F13R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F0R2 register  *******************/
-#define  CAN_F0R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F0R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F0R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F0R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F0R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F0R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F0R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F0R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F0R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F0R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F0R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F0R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F0R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F0R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F0R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F0R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F0R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F0R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F0R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F0R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F0R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F0R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F0R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F0R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F0R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F0R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F0R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F0R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F0R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F0R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F0R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F0R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R2 register  *******************/
-#define  CAN_F1R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F1R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F1R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F1R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F1R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F1R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F1R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F1R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F1R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F1R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F1R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F1R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F1R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F1R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F1R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F1R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F1R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F1R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F1R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F1R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F1R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F1R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F1R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F1R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F1R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F1R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F1R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F1R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F1R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F1R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F1R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F1R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R2 register  *******************/
-#define  CAN_F2R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F2R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F2R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F2R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F2R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F2R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F2R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F2R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F2R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F2R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F2R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F2R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F2R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F2R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F2R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F2R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F2R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F2R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F2R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F2R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F2R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F2R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F2R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F2R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F2R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F2R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F2R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F2R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F2R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F2R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F2R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F2R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R2 register  *******************/
-#define  CAN_F3R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F3R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F3R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F3R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F3R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F3R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F3R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F3R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F3R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F3R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F3R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F3R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F3R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F3R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F3R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F3R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F3R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F3R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F3R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F3R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F3R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F3R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F3R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F3R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F3R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F3R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F3R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F3R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F3R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F3R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F3R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F3R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R2 register  *******************/
-#define  CAN_F4R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F4R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F4R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F4R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F4R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F4R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F4R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F4R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F4R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F4R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F4R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F4R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F4R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F4R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F4R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F4R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F4R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F4R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F4R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F4R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F4R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F4R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F4R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F4R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F4R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F4R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F4R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F4R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F4R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F4R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F4R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F4R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R2 register  *******************/
-#define  CAN_F5R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F5R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F5R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F5R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F5R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F5R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F5R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F5R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F5R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F5R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F5R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F5R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F5R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F5R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F5R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F5R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F5R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F5R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F5R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F5R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F5R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F5R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F5R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F5R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F5R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F5R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F5R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F5R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F5R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F5R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F5R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F5R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R2 register  *******************/
-#define  CAN_F6R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F6R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F6R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F6R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F6R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F6R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F6R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F6R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F6R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F6R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F6R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F6R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F6R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F6R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F6R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F6R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F6R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F6R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F6R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F6R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F6R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F6R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F6R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F6R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F6R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F6R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F6R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F6R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F6R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F6R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F6R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F6R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R2 register  *******************/
-#define  CAN_F7R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F7R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F7R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F7R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F7R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F7R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F7R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F7R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F7R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F7R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F7R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F7R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F7R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F7R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F7R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F7R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F7R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F7R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F7R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F7R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F7R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F7R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F7R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F7R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F7R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F7R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F7R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F7R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F7R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F7R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F7R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F7R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R2 register  *******************/
-#define  CAN_F8R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F8R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F8R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F8R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F8R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F8R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F8R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F8R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F8R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F8R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F8R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F8R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F8R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F8R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F8R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F8R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F8R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F8R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F8R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F8R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F8R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F8R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F8R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F8R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F8R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F8R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F8R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F8R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F8R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F8R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F8R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F8R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R2 register  *******************/
-#define  CAN_F9R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F9R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F9R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F9R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F9R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F9R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F9R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F9R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F9R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F9R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F9R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F9R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F9R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F9R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F9R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F9R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F9R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F9R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F9R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F9R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F9R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F9R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F9R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F9R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F9R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F9R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F9R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F9R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F9R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F9R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F9R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F9R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R2 register  ******************/
-#define  CAN_F10R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F10R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F10R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F10R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F10R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F10R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F10R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F10R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F10R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F10R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F10R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F10R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F10R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F10R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F10R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F10R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F10R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F10R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F10R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F10R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F10R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F10R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F10R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F10R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F10R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F10R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F10R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F10R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F10R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F10R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F10R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F10R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R2 register  ******************/
-#define  CAN_F11R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F11R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F11R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F11R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F11R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F11R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F11R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F11R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F11R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F11R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F11R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F11R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F11R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F11R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F11R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F11R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F11R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F11R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F11R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F11R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F11R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F11R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F11R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F11R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F11R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F11R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F11R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F11R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F11R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F11R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F11R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F11R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R2 register  ******************/
-#define  CAN_F12R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F12R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F12R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F12R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F12R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F12R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F12R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F12R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F12R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F12R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F12R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F12R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F12R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F12R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F12R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F12R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F12R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F12R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F12R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F12R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F12R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F12R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F12R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F12R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F12R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F12R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F12R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F12R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F12R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F12R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F12R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F12R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R2 register  ******************/
-#define  CAN_F13R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F13R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F13R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F13R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F13R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F13R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F13R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F13R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F13R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F13R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F13R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F13R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F13R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F13R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F13R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F13R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F13R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F13R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F13R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F13R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F13R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F13R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F13R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F13R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F13R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F13R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F13R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F13R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F13R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F13R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F13R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F13R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRC calculation unit                              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           0xFFFFFFFFU /*!< Data register bits */
-
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         0xFFU        /*!< General-purpose 8-bit data register bits */
-
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        0x01U        /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Crypto Processor                                */
-/*                                                                            */
-/******************************************************************************/
-/******************* Bits definition for CRYP_CR register  ********************/
-#define CRYP_CR_ALGODIR                      0x00000004U
-
-#define CRYP_CR_ALGOMODE                     0x00080038U
-#define CRYP_CR_ALGOMODE_0                   0x00000008U
-#define CRYP_CR_ALGOMODE_1                   0x00000010U
-#define CRYP_CR_ALGOMODE_2                   0x00000020U
-#define CRYP_CR_ALGOMODE_TDES_ECB            0x00000000U
-#define CRYP_CR_ALGOMODE_TDES_CBC            0x00000008U
-#define CRYP_CR_ALGOMODE_DES_ECB             0x00000010U
-#define CRYP_CR_ALGOMODE_DES_CBC             0x00000018U
-#define CRYP_CR_ALGOMODE_AES_ECB             0x00000020U
-#define CRYP_CR_ALGOMODE_AES_CBC             0x00000028U
-#define CRYP_CR_ALGOMODE_AES_CTR             0x00000030U
-#define CRYP_CR_ALGOMODE_AES_KEY             0x00000038U
-
-#define CRYP_CR_DATATYPE                     0x000000C0U
-#define CRYP_CR_DATATYPE_0                   0x00000040U
-#define CRYP_CR_DATATYPE_1                   0x00000080U
-#define CRYP_CR_KEYSIZE                      0x00000300U
-#define CRYP_CR_KEYSIZE_0                    0x00000100U
-#define CRYP_CR_KEYSIZE_1                    0x00000200U
-#define CRYP_CR_FFLUSH                       0x00004000U
-#define CRYP_CR_CRYPEN                       0x00008000U
-
-#define CRYP_CR_GCM_CCMPH                    0x00030000U
-#define CRYP_CR_GCM_CCMPH_0                  0x00010000U
-#define CRYP_CR_GCM_CCMPH_1                  0x00020000U
-#define CRYP_CR_ALGOMODE_3                   0x00080000U 
-
-/****************** Bits definition for CRYP_SR register  *********************/
-#define CRYP_SR_IFEM                         0x00000001U
-#define CRYP_SR_IFNF                         0x00000002U
-#define CRYP_SR_OFNE                         0x00000004U
-#define CRYP_SR_OFFU                         0x00000008U
-#define CRYP_SR_BUSY                         0x00000010U
-/****************** Bits definition for CRYP_DMACR register  ******************/
-#define CRYP_DMACR_DIEN                      0x00000001U
-#define CRYP_DMACR_DOEN                      0x00000002U
-/*****************  Bits definition for CRYP_IMSCR register  ******************/
-#define CRYP_IMSCR_INIM                      0x00000001U
-#define CRYP_IMSCR_OUTIM                     0x00000002U
-/****************** Bits definition for CRYP_RISR register  *******************/
-#define CRYP_RISR_OUTRIS                     0x00000001U
-#define CRYP_RISR_INRIS                      0x00000002U
-/****************** Bits definition for CRYP_MISR register  *******************/
-#define CRYP_MISR_INMIS                      0x00000001U
-#define CRYP_MISR_OUTMIS                     0x00000002U
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Digital to Analog Converter                           */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DAC_CR register  ********************/
-#define  DAC_CR_EN1                          0x00000001U        /*!<DAC channel1 enable */
-#define  DAC_CR_BOFF1                        0x00000002U        /*!<DAC channel1 output buffer disable */
-#define  DAC_CR_TEN1                         0x00000004U        /*!<DAC channel1 Trigger enable */
-
-#define  DAC_CR_TSEL1                        0x00000038U        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define  DAC_CR_TSEL1_0                      0x00000008U        /*!<Bit 0 */
-#define  DAC_CR_TSEL1_1                      0x00000010U        /*!<Bit 1 */
-#define  DAC_CR_TSEL1_2                      0x00000020U        /*!<Bit 2 */
-
-#define  DAC_CR_WAVE1                        0x000000C0U        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE1_0                      0x00000040U        /*!<Bit 0 */
-#define  DAC_CR_WAVE1_1                      0x00000080U        /*!<Bit 1 */
-
-#define  DAC_CR_MAMP1                        0x00000F00U        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP1_0                      0x00000100U        /*!<Bit 0 */
-#define  DAC_CR_MAMP1_1                      0x00000200U        /*!<Bit 1 */
-#define  DAC_CR_MAMP1_2                      0x00000400U        /*!<Bit 2 */
-#define  DAC_CR_MAMP1_3                      0x00000800U        /*!<Bit 3 */
-
-#define  DAC_CR_DMAEN1                       0x00001000U        /*!<DAC channel1 DMA enable */
-#define  DAC_CR_DMAUDRIE1                    0x00002000U        /*!<DAC channel1 DMA underrun interrupt enable*/
-#define  DAC_CR_EN2                          0x00010000U        /*!<DAC channel2 enable */
-#define  DAC_CR_BOFF2                        0x00020000U        /*!<DAC channel2 output buffer disable */
-#define  DAC_CR_TEN2                         0x00040000U        /*!<DAC channel2 Trigger enable */
-
-#define  DAC_CR_TSEL2                        0x00380000U        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define  DAC_CR_TSEL2_0                      0x00080000U        /*!<Bit 0 */
-#define  DAC_CR_TSEL2_1                      0x00100000U        /*!<Bit 1 */
-#define  DAC_CR_TSEL2_2                      0x00200000U        /*!<Bit 2 */
-
-#define  DAC_CR_WAVE2                        0x00C00000U        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE2_0                      0x00400000U        /*!<Bit 0 */
-#define  DAC_CR_WAVE2_1                      0x00800000U        /*!<Bit 1 */
-
-#define  DAC_CR_MAMP2                        0x0F000000U        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP2_0                      0x01000000U        /*!<Bit 0 */
-#define  DAC_CR_MAMP2_1                      0x02000000U        /*!<Bit 1 */
-#define  DAC_CR_MAMP2_2                      0x04000000U        /*!<Bit 2 */
-#define  DAC_CR_MAMP2_3                      0x08000000U        /*!<Bit 3 */
-
-#define  DAC_CR_DMAEN2                       0x10000000U        /*!<DAC channel2 DMA enabled */
-#define  DAC_CR_DMAUDRIE2                    0x20000000U        /*!<DAC channel2 DMA underrun interrupt enable*/
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define  DAC_SWTRIGR_SWTRIG1                 0x01U               /*!<DAC channel1 software trigger */
-#define  DAC_SWTRIGR_SWTRIG2                 0x02U               /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define  DAC_DHR12R1_DACC1DHR                0x0FFFU            /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define  DAC_DHR12L1_DACC1DHR                0xFFF0U            /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define  DAC_DHR8R1_DACC1DHR                 0xFFU               /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define  DAC_DHR12R2_DACC2DHR                0x0FFFU            /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define  DAC_DHR12L2_DACC2DHR                0xFFF0U            /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define  DAC_DHR8R2_DACC2DHR                 0xFFU               /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define  DAC_DHR12RD_DACC1DHR                0x00000FFFU        /*!<DAC channel1 12-bit Right aligned data */
-#define  DAC_DHR12RD_DACC2DHR                0x0FFF0000U        /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define  DAC_DHR12LD_DACC1DHR                0x0000FFF0U        /*!<DAC channel1 12-bit Left aligned data */
-#define  DAC_DHR12LD_DACC2DHR                0xFFF00000U        /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define  DAC_DHR8RD_DACC1DHR                 0x00FFU            /*!<DAC channel1 8-bit Right aligned data */
-#define  DAC_DHR8RD_DACC2DHR                 0xFF00U            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define  DAC_DOR1_DACC1DOR                   0x0FFFU            /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define  DAC_DOR2_DACC2DOR                   0x0FFFU            /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define  DAC_SR_DMAUDR1                      0x00002000U        /*!<DAC channel1 DMA underrun flag */
-#define  DAC_SR_DMAUDR2                      0x20000000U        /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 Debug MCU                                  */
-/*                                                                            */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    DCMI                                    */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DCMI_CR register  ******************/
-#define DCMI_CR_CAPTURE                      0x00000001U
-#define DCMI_CR_CM                           0x00000002U
-#define DCMI_CR_CROP                         0x00000004U
-#define DCMI_CR_JPEG                         0x00000008U
-#define DCMI_CR_ESS                          0x00000010U
-#define DCMI_CR_PCKPOL                       0x00000020U
-#define DCMI_CR_HSPOL                        0x00000040U
-#define DCMI_CR_VSPOL                        0x00000080U
-#define DCMI_CR_FCRC_0                       0x00000100U
-#define DCMI_CR_FCRC_1                       0x00000200U
-#define DCMI_CR_EDM_0                        0x00000400U
-#define DCMI_CR_EDM_1                        0x00000800U
-#define DCMI_CR_CRE                          0x00001000U
-#define DCMI_CR_ENABLE                       0x00004000U
-
-/********************  Bits definition for DCMI_SR register  ******************/
-#define DCMI_SR_HSYNC                        0x00000001U
-#define DCMI_SR_VSYNC                        0x00000002U
-#define DCMI_SR_FNE                          0x00000004U
-
-/********************  Bits definition for DCMI_RIS register  ****************/
-#define DCMI_RIS_FRAME_RIS                   0x00000001U
-#define DCMI_RIS_OVR_RIS                     0x00000002U
-#define DCMI_RIS_ERR_RIS                     0x00000004U
-#define DCMI_RIS_VSYNC_RIS                   0x00000008U
-#define DCMI_RIS_LINE_RIS                    0x00000010U
-/* Legacy defines */
-#define DCMI_RISR_FRAME_RIS                  DCMI_RIS_FRAME_RIS
-#define DCMI_RISR_OVR_RIS                    DCMI_RIS_OVR_RIS
-#define DCMI_RISR_ERR_RIS                    DCMI_RIS_ERR_RIS
-#define DCMI_RISR_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS
-#define DCMI_RISR_LINE_RIS                   DCMI_RIS_LINE_RIS
-#define DCMI_RISR_OVF_RIS                    DCMI_RIS_OVR_RIS
-
-/********************  Bits definition for DCMI_IER register  *****************/
-#define DCMI_IER_FRAME_IE                    0x00000001U
-#define DCMI_IER_OVR_IE                      0x00000002U
-#define DCMI_IER_ERR_IE                      0x00000004U
-#define DCMI_IER_VSYNC_IE                    0x00000008U
-#define DCMI_IER_LINE_IE                     0x00000010U
-/* Legacy defines */
-#define DCMI_IER_OVF_IE                      DCMI_IER_OVR_IE
-
-/********************  Bits definition for DCMI_MIS register  *****************/
-#define DCMI_MIS_FRAME_MIS                   0x00000001U
-#define DCMI_MIS_OVR_MIS                     0x00000002U
-#define DCMI_MIS_ERR_MIS                     0x00000004U
-#define DCMI_MIS_VSYNC_MIS                   0x00000008U
-#define DCMI_MIS_LINE_MIS                    0x00000010U
-
-/* Legacy defines */
-#define DCMI_MISR_FRAME_MIS                  DCMI_MIS_FRAME_MIS
-#define DCMI_MISR_OVF_MIS                    DCMI_MIS_OVR_MIS
-#define DCMI_MISR_ERR_MIS                    DCMI_MIS_ERR_MIS
-#define DCMI_MISR_VSYNC_MIS                  DCMI_MIS_VSYNC_MIS
-#define DCMI_MISR_LINE_MIS                   DCMI_MIS_LINE_MIS
-
-/********************  Bits definition for DCMI_ICR register  *****************/
-#define DCMI_ICR_FRAME_ISC                   0x00000001U
-#define DCMI_ICR_OVR_ISC                     0x00000002U
-#define DCMI_ICR_ERR_ISC                     0x00000004U
-#define DCMI_ICR_VSYNC_ISC                   0x00000008U
-#define DCMI_ICR_LINE_ISC                    0x00000010U
-
-/* Legacy defines */
-#define DCMI_ICR_OVF_ISC                     DCMI_ICR_OVR_ISC
-
-/********************  Bits definition for DCMI_ESCR register  ******************/
-#define DCMI_ESCR_FSC                        0x000000FFU
-#define DCMI_ESCR_LSC                        0x0000FF00U
-#define DCMI_ESCR_LEC                        0x00FF0000U
-#define DCMI_ESCR_FEC                        0xFF000000U
-
-/********************  Bits definition for DCMI_ESUR register  ******************/
-#define DCMI_ESUR_FSU                        0x000000FFU
-#define DCMI_ESUR_LSU                        0x0000FF00U
-#define DCMI_ESUR_LEU                        0x00FF0000U
-#define DCMI_ESUR_FEU                        0xFF000000U
-
-/********************  Bits definition for DCMI_CWSTRT register  ******************/
-#define DCMI_CWSTRT_HOFFCNT                  0x00003FFFU
-#define DCMI_CWSTRT_VST                      0x1FFF0000U
-
-/********************  Bits definition for DCMI_CWSIZE register  ******************/
-#define DCMI_CWSIZE_CAPCNT                   0x00003FFFU
-#define DCMI_CWSIZE_VLINE                    0x3FFF0000U
-
-/********************  Bits definition for DCMI_DR register  ******************/
-#define DCMI_DR_BYTE0                        0x000000FFU
-#define DCMI_DR_BYTE1                        0x0000FF00U
-#define DCMI_DR_BYTE2                        0x00FF0000U
-#define DCMI_DR_BYTE3                        0xFF000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                             DMA Controller                                 */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DMA_SxCR register  *****************/
-#define DMA_SxCR_CHSEL                       0x0E000000U
-#define DMA_SxCR_CHSEL_0                     0x02000000U
-#define DMA_SxCR_CHSEL_1                     0x04000000U
-#define DMA_SxCR_CHSEL_2                     0x08000000U
-#define DMA_SxCR_MBURST                      0x01800000U
-#define DMA_SxCR_MBURST_0                    0x00800000U
-#define DMA_SxCR_MBURST_1                    0x01000000U
-#define DMA_SxCR_PBURST                      0x00600000U
-#define DMA_SxCR_PBURST_0                    0x00200000U
-#define DMA_SxCR_PBURST_1                    0x00400000U
-#define DMA_SxCR_CT                          0x00080000U
-#define DMA_SxCR_DBM                         0x00040000U
-#define DMA_SxCR_PL                          0x00030000U
-#define DMA_SxCR_PL_0                        0x00010000U
-#define DMA_SxCR_PL_1                        0x00020000U
-#define DMA_SxCR_PINCOS                      0x00008000U
-#define DMA_SxCR_MSIZE                       0x00006000U
-#define DMA_SxCR_MSIZE_0                     0x00002000U
-#define DMA_SxCR_MSIZE_1                     0x00004000U
-#define DMA_SxCR_PSIZE                       0x00001800U
-#define DMA_SxCR_PSIZE_0                     0x00000800U
-#define DMA_SxCR_PSIZE_1                     0x00001000U
-#define DMA_SxCR_MINC                        0x00000400U
-#define DMA_SxCR_PINC                        0x00000200U
-#define DMA_SxCR_CIRC                        0x00000100U
-#define DMA_SxCR_DIR                         0x000000C0U
-#define DMA_SxCR_DIR_0                       0x00000040U
-#define DMA_SxCR_DIR_1                       0x00000080U
-#define DMA_SxCR_PFCTRL                      0x00000020U
-#define DMA_SxCR_TCIE                        0x00000010U
-#define DMA_SxCR_HTIE                        0x00000008U
-#define DMA_SxCR_TEIE                        0x00000004U
-#define DMA_SxCR_DMEIE                       0x00000002U
-#define DMA_SxCR_EN                          0x00000001U
-
-/* Legacy defines */
-#define DMA_SxCR_ACK                         0x00100000U
-
-/********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            0x0000FFFFU
-#define DMA_SxNDT_0                          0x00000001U
-#define DMA_SxNDT_1                          0x00000002U
-#define DMA_SxNDT_2                          0x00000004U
-#define DMA_SxNDT_3                          0x00000008U
-#define DMA_SxNDT_4                          0x00000010U
-#define DMA_SxNDT_5                          0x00000020U
-#define DMA_SxNDT_6                          0x00000040U
-#define DMA_SxNDT_7                          0x00000080U
-#define DMA_SxNDT_8                          0x00000100U
-#define DMA_SxNDT_9                          0x00000200U
-#define DMA_SxNDT_10                         0x00000400U
-#define DMA_SxNDT_11                         0x00000800U
-#define DMA_SxNDT_12                         0x00001000U
-#define DMA_SxNDT_13                         0x00002000U
-#define DMA_SxNDT_14                         0x00004000U
-#define DMA_SxNDT_15                         0x00008000U
-
-/********************  Bits definition for DMA_SxFCR register  ****************/ 
-#define DMA_SxFCR_FEIE                       0x00000080U
-#define DMA_SxFCR_FS                         0x00000038U
-#define DMA_SxFCR_FS_0                       0x00000008U
-#define DMA_SxFCR_FS_1                       0x00000010U
-#define DMA_SxFCR_FS_2                       0x00000020U
-#define DMA_SxFCR_DMDIS                      0x00000004U
-#define DMA_SxFCR_FTH                        0x00000003U
-#define DMA_SxFCR_FTH_0                      0x00000001U
-#define DMA_SxFCR_FTH_1                      0x00000002U
-
-/********************  Bits definition for DMA_LISR register  *****************/ 
-#define DMA_LISR_TCIF3                       0x08000000U
-#define DMA_LISR_HTIF3                       0x04000000U
-#define DMA_LISR_TEIF3                       0x02000000U
-#define DMA_LISR_DMEIF3                      0x01000000U
-#define DMA_LISR_FEIF3                       0x00400000U
-#define DMA_LISR_TCIF2                       0x00200000U
-#define DMA_LISR_HTIF2                       0x00100000U
-#define DMA_LISR_TEIF2                       0x00080000U
-#define DMA_LISR_DMEIF2                      0x00040000U
-#define DMA_LISR_FEIF2                       0x00010000U
-#define DMA_LISR_TCIF1                       0x00000800U
-#define DMA_LISR_HTIF1                       0x00000400U
-#define DMA_LISR_TEIF1                       0x00000200U
-#define DMA_LISR_DMEIF1                      0x00000100U
-#define DMA_LISR_FEIF1                       0x00000040U
-#define DMA_LISR_TCIF0                       0x00000020U
-#define DMA_LISR_HTIF0                       0x00000010U
-#define DMA_LISR_TEIF0                       0x00000008U
-#define DMA_LISR_DMEIF0                      0x00000004U
-#define DMA_LISR_FEIF0                       0x00000001U
-
-/********************  Bits definition for DMA_HISR register  *****************/ 
-#define DMA_HISR_TCIF7                       0x08000000U
-#define DMA_HISR_HTIF7                       0x04000000U
-#define DMA_HISR_TEIF7                       0x02000000U
-#define DMA_HISR_DMEIF7                      0x01000000U
-#define DMA_HISR_FEIF7                       0x00400000U
-#define DMA_HISR_TCIF6                       0x00200000U
-#define DMA_HISR_HTIF6                       0x00100000U
-#define DMA_HISR_TEIF6                       0x00080000U
-#define DMA_HISR_DMEIF6                      0x00040000U
-#define DMA_HISR_FEIF6                       0x00010000U
-#define DMA_HISR_TCIF5                       0x00000800U
-#define DMA_HISR_HTIF5                       0x00000400U
-#define DMA_HISR_TEIF5                       0x00000200U
-#define DMA_HISR_DMEIF5                      0x00000100U
-#define DMA_HISR_FEIF5                       0x00000040U
-#define DMA_HISR_TCIF4                       0x00000020U
-#define DMA_HISR_HTIF4                       0x00000010U
-#define DMA_HISR_TEIF4                       0x00000008U
-#define DMA_HISR_DMEIF4                      0x00000004U
-#define DMA_HISR_FEIF4                       0x00000001U
-
-/********************  Bits definition for DMA_LIFCR register  ****************/ 
-#define DMA_LIFCR_CTCIF3                     0x08000000U
-#define DMA_LIFCR_CHTIF3                     0x04000000U
-#define DMA_LIFCR_CTEIF3                     0x02000000U
-#define DMA_LIFCR_CDMEIF3                    0x01000000U
-#define DMA_LIFCR_CFEIF3                     0x00400000U
-#define DMA_LIFCR_CTCIF2                     0x00200000U
-#define DMA_LIFCR_CHTIF2                     0x00100000U
-#define DMA_LIFCR_CTEIF2                     0x00080000U
-#define DMA_LIFCR_CDMEIF2                    0x00040000U
-#define DMA_LIFCR_CFEIF2                     0x00010000U
-#define DMA_LIFCR_CTCIF1                     0x00000800U
-#define DMA_LIFCR_CHTIF1                     0x00000400U
-#define DMA_LIFCR_CTEIF1                     0x00000200U
-#define DMA_LIFCR_CDMEIF1                    0x00000100U
-#define DMA_LIFCR_CFEIF1                     0x00000040U
-#define DMA_LIFCR_CTCIF0                     0x00000020U
-#define DMA_LIFCR_CHTIF0                     0x00000010U
-#define DMA_LIFCR_CTEIF0                     0x00000008U
-#define DMA_LIFCR_CDMEIF0                    0x00000004U
-#define DMA_LIFCR_CFEIF0                     0x00000001U
-
-/********************  Bits definition for DMA_HIFCR  register  ****************/ 
-#define DMA_HIFCR_CTCIF7                     0x08000000U
-#define DMA_HIFCR_CHTIF7                     0x04000000U
-#define DMA_HIFCR_CTEIF7                     0x02000000U
-#define DMA_HIFCR_CDMEIF7                    0x01000000U
-#define DMA_HIFCR_CFEIF7                     0x00400000U
-#define DMA_HIFCR_CTCIF6                     0x00200000U
-#define DMA_HIFCR_CHTIF6                     0x00100000U
-#define DMA_HIFCR_CTEIF6                     0x00080000U
-#define DMA_HIFCR_CDMEIF6                    0x00040000U
-#define DMA_HIFCR_CFEIF6                     0x00010000U
-#define DMA_HIFCR_CTCIF5                     0x00000800U
-#define DMA_HIFCR_CHTIF5                     0x00000400U
-#define DMA_HIFCR_CTEIF5                     0x00000200U
-#define DMA_HIFCR_CDMEIF5                    0x00000100U
-#define DMA_HIFCR_CFEIF5                     0x00000040U
-#define DMA_HIFCR_CTCIF4                     0x00000020U
-#define DMA_HIFCR_CHTIF4                     0x00000010U
-#define DMA_HIFCR_CTEIF4                     0x00000008U
-#define DMA_HIFCR_CDMEIF4                    0x00000004U
-#define DMA_HIFCR_CFEIF4                     0x00000001U
-
-/******************************************************************************/
-/*                                                                            */
-/*                         AHB Master DMA2D Controller (DMA2D)                */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for DMA2D_CR register  ******************/
-
-#define DMA2D_CR_START                     0x00000001U               /*!< Start transfer */
-#define DMA2D_CR_SUSP                      0x00000002U               /*!< Suspend transfer */
-#define DMA2D_CR_ABORT                     0x00000004U               /*!< Abort transfer */
-#define DMA2D_CR_TEIE                      0x00000100U               /*!< Transfer Error Interrupt Enable */
-#define DMA2D_CR_TCIE                      0x00000200U               /*!< Transfer Complete Interrupt Enable */
-#define DMA2D_CR_TWIE                      0x00000400U               /*!< Transfer Watermark Interrupt Enable */
-#define DMA2D_CR_CAEIE                     0x00000800U               /*!< CLUT Access Error Interrupt Enable */
-#define DMA2D_CR_CTCIE                     0x00001000U               /*!< CLUT Transfer Complete Interrupt Enable */
-#define DMA2D_CR_CEIE                      0x00002000U               /*!< Configuration Error Interrupt Enable */
-#define DMA2D_CR_MODE                      0x00030000U               /*!< DMA2D Mode[1:0] */
-#define DMA2D_CR_MODE_0                    0x00010000U               /*!< DMA2D Mode bit 0 */
-#define DMA2D_CR_MODE_1                    0x00020000U               /*!< DMA2D Mode bit 1 */
-
-/********************  Bit definition for DMA2D_ISR register  *****************/
-
-#define DMA2D_ISR_TEIF                     0x00000001U               /*!< Transfer Error Interrupt Flag */
-#define DMA2D_ISR_TCIF                     0x00000002U               /*!< Transfer Complete Interrupt Flag */
-#define DMA2D_ISR_TWIF                     0x00000004U               /*!< Transfer Watermark Interrupt Flag */
-#define DMA2D_ISR_CAEIF                    0x00000008U               /*!< CLUT Access Error Interrupt Flag */
-#define DMA2D_ISR_CTCIF                    0x00000010U               /*!< CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_ISR_CEIF                     0x00000020U               /*!< Configuration Error Interrupt Flag */
-
-/********************  Bit definition for DMA2D_IFCR register  ****************/
-
-#define DMA2D_IFCR_CTEIF                   0x00000001U               /*!< Clears Transfer Error Interrupt Flag         */
-#define DMA2D_IFCR_CTCIF                   0x00000002U               /*!< Clears Transfer Complete Interrupt Flag      */
-#define DMA2D_IFCR_CTWIF                   0x00000004U               /*!< Clears Transfer Watermark Interrupt Flag     */
-#define DMA2D_IFCR_CAECIF                  0x00000008U               /*!< Clears CLUT Access Error Interrupt Flag      */
-#define DMA2D_IFCR_CCTCIF                  0x00000010U               /*!< Clears CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_IFCR_CCEIF                   0x00000020U               /*!< Clears Configuration Error Interrupt Flag    */
-
-/* Legacy defines */
-#define DMA2D_IFSR_CTEIF                   DMA2D_IFCR_CTEIF                     /*!< Clears Transfer Error Interrupt Flag         */
-#define DMA2D_IFSR_CTCIF                   DMA2D_IFCR_CTCIF                     /*!< Clears Transfer Complete Interrupt Flag      */
-#define DMA2D_IFSR_CTWIF                   DMA2D_IFCR_CTWIF                     /*!< Clears Transfer Watermark Interrupt Flag     */
-#define DMA2D_IFSR_CCAEIF                  DMA2D_IFCR_CAECIF                    /*!< Clears CLUT Access Error Interrupt Flag      */
-#define DMA2D_IFSR_CCTCIF                  DMA2D_IFCR_CCTCIF                    /*!< Clears CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_IFSR_CCEIF                   DMA2D_IFCR_CCEIF                     /*!< Clears Configuration Error Interrupt Flag    */
-
-/********************  Bit definition for DMA2D_FGMAR register  ***************/
-
-#define DMA2D_FGMAR_MA                     0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_FGOR register  ****************/
-
-#define DMA2D_FGOR_LO                      0x00003FFFU               /*!< Line Offset */
-
-/********************  Bit definition for DMA2D_BGMAR register  ***************/
-
-#define DMA2D_BGMAR_MA                     0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_BGOR register  ****************/
-
-#define DMA2D_BGOR_LO                      0x00003FFFU               /*!< Line Offset */
-
-/********************  Bit definition for DMA2D_FGPFCCR register  *************/
-
-#define DMA2D_FGPFCCR_CM                   0x0000000FU               /*!< Input color mode CM[3:0] */
-#define DMA2D_FGPFCCR_CM_0                 0x00000001U               /*!< Input color mode CM bit 0 */
-#define DMA2D_FGPFCCR_CM_1                 0x00000002U               /*!< Input color mode CM bit 1 */
-#define DMA2D_FGPFCCR_CM_2                 0x00000004U               /*!< Input color mode CM bit 2 */
-#define DMA2D_FGPFCCR_CM_3                 0x00000008U               /*!< Input color mode CM bit 3 */
-#define DMA2D_FGPFCCR_CCM                  0x00000010U               /*!< CLUT Color mode */
-#define DMA2D_FGPFCCR_START                0x00000020U               /*!< Start */
-#define DMA2D_FGPFCCR_CS                   0x0000FF00U               /*!< CLUT size */
-#define DMA2D_FGPFCCR_AM                   0x00030000U               /*!< Alpha mode AM[1:0] */
-#define DMA2D_FGPFCCR_AM_0                 0x00010000U               /*!< Alpha mode AM bit 0 */
-#define DMA2D_FGPFCCR_AM_1                 0x00020000U               /*!< Alpha mode AM bit 1 */
-#define DMA2D_FGPFCCR_ALPHA                0xFF000000U               /*!< Alpha value */
-
-/********************  Bit definition for DMA2D_FGCOLR register  **************/
-
-#define DMA2D_FGCOLR_BLUE                  0x000000FFU               /*!< Blue Value */
-#define DMA2D_FGCOLR_GREEN                 0x0000FF00U               /*!< Green Value */
-#define DMA2D_FGCOLR_RED                   0x00FF0000U               /*!< Red Value */   
-
-/********************  Bit definition for DMA2D_BGPFCCR register  *************/
-
-#define DMA2D_BGPFCCR_CM                   0x0000000FU               /*!< Input color mode CM[3:0] */
-#define DMA2D_BGPFCCR_CM_0                 0x00000001U               /*!< Input color mode CM bit 0 */
-#define DMA2D_BGPFCCR_CM_1                 0x00000002U               /*!< Input color mode CM bit 1 */
-#define DMA2D_BGPFCCR_CM_2                 0x00000004U               /*!< Input color mode CM bit 2 */
-#define DMA2D_FGPFCCR_CM_3                 0x00000008U               /*!< Input color mode CM bit 3 */
-#define DMA2D_BGPFCCR_CCM                  0x00000010U               /*!< CLUT Color mode */
-#define DMA2D_BGPFCCR_START                0x00000020U               /*!< Start */
-#define DMA2D_BGPFCCR_CS                   0x0000FF00U               /*!< CLUT size */
-#define DMA2D_BGPFCCR_AM                   0x00030000U               /*!< Alpha mode AM[1:0] */
-#define DMA2D_BGPFCCR_AM_0                 0x00010000U               /*!< Alpha mode AM bit 0 */
-#define DMA2D_BGPFCCR_AM_1                 0x00020000U               /*!< Alpha mode AM bit 1 */
-#define DMA2D_BGPFCCR_ALPHA                0xFF000000U               /*!< background Input Alpha value */
-
-/********************  Bit definition for DMA2D_BGCOLR register  **************/
-
-#define DMA2D_BGCOLR_BLUE                  0x000000FFU               /*!< Blue Value */
-#define DMA2D_BGCOLR_GREEN                 0x0000FF00U               /*!< Green Value */
-#define DMA2D_BGCOLR_RED                   0x00FF0000U               /*!< Red Value */
-
-/********************  Bit definition for DMA2D_FGCMAR register  **************/
-
-#define DMA2D_FGCMAR_MA                    0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_BGCMAR register  **************/
-
-#define DMA2D_BGCMAR_MA                    0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_OPFCCR register  **************/
-
-#define DMA2D_OPFCCR_CM                    0x00000007U               /*!< Color mode CM[2:0] */
-#define DMA2D_OPFCCR_CM_0                  0x00000001U               /*!< Color mode CM bit 0 */
-#define DMA2D_OPFCCR_CM_1                  0x00000002U               /*!< Color mode CM bit 1 */
-#define DMA2D_OPFCCR_CM_2                  0x00000004U               /*!< Color mode CM bit 2 */
-
-/********************  Bit definition for DMA2D_OCOLR register  ***************/
-
-/*!<Mode_ARGB8888/RGB888 */
-
-#define DMA2D_OCOLR_BLUE_1                 0x000000FFU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_1                0x0000FF00U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_1                  0x00FF0000U               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_1                0xFF000000U               /*!< Alpha Channel Value */
-
-/*!<Mode_RGB565 */
-#define DMA2D_OCOLR_BLUE_2                 0x0000001FU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_2                0x000007E0U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_2                  0x0000F800U               /*!< Red Value */
-
-/*!<Mode_ARGB1555 */
-#define DMA2D_OCOLR_BLUE_3                 0x0000001FU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_3                0x000003E0U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_3                  0x00007C00U               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_3                0x00008000U               /*!< Alpha Channel Value */
-
-/*!<Mode_ARGB4444 */
-#define DMA2D_OCOLR_BLUE_4                 0x0000000FU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_4                0x000000F0U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_4                  0x00000F00U               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_4                0x0000F000U               /*!< Alpha Channel Value */
-
-/********************  Bit definition for DMA2D_OMAR register  ****************/
-
-#define DMA2D_OMAR_MA                      0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_OOR register  *****************/
-
-#define DMA2D_OOR_LO                       0x00003FFFU               /*!< Line Offset */
-
-/********************  Bit definition for DMA2D_NLR register  *****************/
-
-#define DMA2D_NLR_NL                       0x0000FFFFU               /*!< Number of Lines */
-#define DMA2D_NLR_PL                       0x3FFF0000U               /*!< Pixel per Lines */
-
-/********************  Bit definition for DMA2D_LWR register  *****************/
-
-#define DMA2D_LWR_LW                       0x0000FFFFU               /*!< Line Watermark */
-
-/********************  Bit definition for DMA2D_AMTCR register  ***************/
-
-#define DMA2D_AMTCR_EN                     0x00000001U               /*!< Enable */
-#define DMA2D_AMTCR_DT                     0x0000FF00U               /*!< Dead Time */
-
-
-/********************  Bit definition for DMA2D_FGCLUT register  **************/
-                                                                     
-/********************  Bit definition for DMA2D_BGCLUT register  **************/
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                    External Interrupt/Event Controller                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    FLASH                                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    0x0000000FU
-#define FLASH_ACR_LATENCY_0WS                0x00000000U
-#define FLASH_ACR_LATENCY_1WS                0x00000001U
-#define FLASH_ACR_LATENCY_2WS                0x00000002U
-#define FLASH_ACR_LATENCY_3WS                0x00000003U
-#define FLASH_ACR_LATENCY_4WS                0x00000004U
-#define FLASH_ACR_LATENCY_5WS                0x00000005U
-#define FLASH_ACR_LATENCY_6WS                0x00000006U
-#define FLASH_ACR_LATENCY_7WS                0x00000007U
-#define FLASH_ACR_LATENCY_8WS                0x00000008U
-#define FLASH_ACR_LATENCY_9WS                0x00000009U
-#define FLASH_ACR_LATENCY_10WS               0x0000000AU
-#define FLASH_ACR_LATENCY_11WS               0x0000000BU
-#define FLASH_ACR_LATENCY_12WS               0x0000000CU
-#define FLASH_ACR_LATENCY_13WS               0x0000000DU
-#define FLASH_ACR_LATENCY_14WS               0x0000000EU
-#define FLASH_ACR_LATENCY_15WS               0x0000000FU
-#define FLASH_ACR_PRFTEN                     0x00000100U
-#define FLASH_ACR_ICEN                       0x00000200U
-#define FLASH_ACR_DCEN                       0x00000400U
-#define FLASH_ACR_ICRST                      0x00000800U
-#define FLASH_ACR_DCRST                      0x00001000U
-#define FLASH_ACR_BYTE0_ADDRESS              0x40023C00U
-#define FLASH_ACR_BYTE2_ADDRESS              0x40023C03U
-
-/*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         0x00000001U
-#define FLASH_SR_SOP                         0x00000002U
-#define FLASH_SR_WRPERR                      0x00000010U
-#define FLASH_SR_PGAERR                      0x00000020U
-#define FLASH_SR_PGPERR                      0x00000040U
-#define FLASH_SR_PGSERR                      0x00000080U
-#define FLASH_SR_BSY                         0x00010000U
-
-/*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          0x00000001U
-#define FLASH_CR_SER                         0x00000002U
-#define FLASH_CR_MER                         0x00000004U
-#define FLASH_CR_MER1                        FLASH_CR_MER
-#define FLASH_CR_SNB                         0x000000F8U
-#define FLASH_CR_SNB_0                       0x00000008U
-#define FLASH_CR_SNB_1                       0x00000010U
-#define FLASH_CR_SNB_2                       0x00000020U
-#define FLASH_CR_SNB_3                       0x00000040U
-#define FLASH_CR_SNB_4                       0x00000080U
-#define FLASH_CR_PSIZE                       0x00000300U
-#define FLASH_CR_PSIZE_0                     0x00000100U
-#define FLASH_CR_PSIZE_1                     0x00000200U
-#define FLASH_CR_MER2                        0x00008000U
-#define FLASH_CR_STRT                        0x00010000U
-#define FLASH_CR_EOPIE                       0x01000000U
-#define FLASH_CR_LOCK                        0x80000000U
-
-/*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                 0x00000001U
-#define FLASH_OPTCR_OPTSTRT                 0x00000002U
-#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
-#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
-#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
-#define FLASH_OPTCR_BFB2                    0x00000010U
-#define FLASH_OPTCR_WDG_SW                  0x00000020U
-#define FLASH_OPTCR_nRST_STOP               0x00000040U
-#define FLASH_OPTCR_nRST_STDBY              0x00000080U
-#define FLASH_OPTCR_RDP                     0x0000FF00U
-#define FLASH_OPTCR_RDP_0                   0x00000100U
-#define FLASH_OPTCR_RDP_1                   0x00000200U
-#define FLASH_OPTCR_RDP_2                   0x00000400U
-#define FLASH_OPTCR_RDP_3                   0x00000800U
-#define FLASH_OPTCR_RDP_4                   0x00001000U
-#define FLASH_OPTCR_RDP_5                   0x00002000U
-#define FLASH_OPTCR_RDP_6                   0x00004000U
-#define FLASH_OPTCR_RDP_7                   0x00008000U
-#define FLASH_OPTCR_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR_nWRP_0                  0x00010000U
-#define FLASH_OPTCR_nWRP_1                  0x00020000U
-#define FLASH_OPTCR_nWRP_2                  0x00040000U
-#define FLASH_OPTCR_nWRP_3                  0x00080000U
-#define FLASH_OPTCR_nWRP_4                  0x00100000U
-#define FLASH_OPTCR_nWRP_5                  0x00200000U
-#define FLASH_OPTCR_nWRP_6                  0x00400000U
-#define FLASH_OPTCR_nWRP_7                  0x00800000U
-#define FLASH_OPTCR_nWRP_8                  0x01000000U
-#define FLASH_OPTCR_nWRP_9                  0x02000000U
-#define FLASH_OPTCR_nWRP_10                 0x04000000U
-#define FLASH_OPTCR_nWRP_11                 0x08000000U
-#define FLASH_OPTCR_DB1M                    0x40000000U 
-#define FLASH_OPTCR_SPRMOD                  0x80000000U 
-                                             
-/******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR1_nWRP_0                  0x00010000U
-#define FLASH_OPTCR1_nWRP_1                  0x00020000U
-#define FLASH_OPTCR1_nWRP_2                  0x00040000U
-#define FLASH_OPTCR1_nWRP_3                  0x00080000U
-#define FLASH_OPTCR1_nWRP_4                  0x00100000U
-#define FLASH_OPTCR1_nWRP_5                  0x00200000U
-#define FLASH_OPTCR1_nWRP_6                  0x00400000U
-#define FLASH_OPTCR1_nWRP_7                  0x00800000U
-#define FLASH_OPTCR1_nWRP_8                  0x01000000U
-#define FLASH_OPTCR1_nWRP_9                  0x02000000U
-#define FLASH_OPTCR1_nWRP_10                 0x04000000U
-#define FLASH_OPTCR1_nWRP_11                 0x08000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Flexible Memory Controller                        */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for FMC_BCR1 register  *******************/
-#define  FMC_BCR1_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR1_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FMC_BCR1_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR1_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR1_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FMC_BCR1_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR1_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR1_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_BCR1_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR1_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR1_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR1_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
-#define  FMC_BCR1_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR1_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR1_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR1_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR1_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR1_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FMC_BCR1_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FMC_BCR1_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FMC_BCR1_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FMC_BCR1_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-#define  FMC_BCR1_CCLKEN                    0x00100000U        /*!<Continous clock enable     */
-
-/******************  Bit definition for FMC_BCR2 register  *******************/
-#define  FMC_BCR2_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR2_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FMC_BCR2_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR2_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR2_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FMC_BCR2_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR2_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR2_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_BCR2_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR2_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR2_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR2_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
-#define  FMC_BCR2_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR2_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR2_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR2_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR2_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR2_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FMC_BCR2_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FMC_BCR2_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FMC_BCR2_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FMC_BCR2_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FMC_BCR3 register  *******************/
-#define  FMC_BCR3_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR3_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FMC_BCR3_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR3_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR3_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FMC_BCR3_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR3_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR3_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_BCR3_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR3_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR3_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR3_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
-#define  FMC_BCR3_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR3_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR3_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR3_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR3_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR3_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FMC_BCR3_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FMC_BCR3_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FMC_BCR3_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FMC_BCR3_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FMC_BCR4 register  *******************/
-#define  FMC_BCR4_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR4_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FMC_BCR4_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR4_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR4_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FMC_BCR4_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR4_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR4_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_BCR4_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR4_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR4_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR4_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
-#define  FMC_BCR4_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR4_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR4_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR4_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR4_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR4_CPSIZE                    0x00070000U        /*!<CRAM page size */
-#define  FMC_BCR4_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FMC_BCR4_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FMC_BCR4_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FMC_BCR4_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FMC_BTR1 register  ******************/
-#define  FMC_BTR1_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR1_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR1_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR1_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR1_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BTR1_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
-#define  FMC_BTR1_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR1_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR1_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR1_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BTR1_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR1_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR1_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR1_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR1_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR1_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR1_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR1_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR1_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BTR1_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR1_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR1_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR1_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR1_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BTR1_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR1_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR1_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR1_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR1_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FMC_BTR1_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR1_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR1_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR1_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR1_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FMC_BTR1_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR1_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR1_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BTR2 register  *******************/
-#define  FMC_BTR2_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR2_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR2_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR2_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR2_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BTR2_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR2_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR2_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR2_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR2_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BTR2_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR2_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR2_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR2_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR2_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR2_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR2_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR2_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR2_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BTR2_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR2_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR2_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR2_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR2_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BTR2_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR2_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR2_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR2_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR2_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FMC_BTR2_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR2_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR2_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR2_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR2_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FMC_BTR2_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR2_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR2_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/*******************  Bit definition for FMC_BTR3 register  *******************/
-#define  FMC_BTR3_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR3_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR3_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR3_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR3_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BTR3_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR3_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR3_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR3_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR3_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BTR3_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR3_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR3_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR3_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR3_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR3_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR3_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR3_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR3_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BTR3_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR3_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR3_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR3_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR3_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BTR3_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR3_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR3_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR3_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR3_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FMC_BTR3_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR3_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR3_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR3_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR3_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FMC_BTR3_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR3_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR3_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BTR4 register  *******************/
-#define  FMC_BTR4_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR4_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR4_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR4_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR4_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BTR4_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR4_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR4_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR4_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR4_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BTR4_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR4_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR4_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR4_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR4_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR4_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR4_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR4_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR4_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BTR4_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR4_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR4_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR4_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR4_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BTR4_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR4_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR4_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR4_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR4_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FMC_BTR4_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR4_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR4_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR4_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR4_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FMC_BTR4_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR4_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR4_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR1 register  ******************/
-#define  FMC_BWTR1_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR1_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR1_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR1_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR1_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BWTR1_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR1_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR1_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR1_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR1_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BWTR1_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR1_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR1_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR1_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR1_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR1_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR1_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR1_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR1_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BWTR1_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR1_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR1_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR1_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR1_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BWTR1_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR1_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR1_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR2 register  ******************/
-#define  FMC_BWTR2_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR2_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR2_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR2_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR2_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BWTR2_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR2_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR2_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR2_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR2_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BWTR2_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR2_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR2_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR2_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR2_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR2_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR2_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR2_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR2_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BWTR2_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR2_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR2_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR2_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR2_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BWTR2_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR2_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR2_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR3 register  ******************/
-#define  FMC_BWTR3_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR3_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR3_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR3_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR3_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BWTR3_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR3_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR3_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR3_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR3_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BWTR3_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR3_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR3_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR3_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR3_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR3_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR3_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR3_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR3_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BWTR3_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR3_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR3_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR3_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR3_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BWTR3_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR3_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR3_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR4 register  ******************/
-#define  FMC_BWTR4_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR4_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR4_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR4_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR4_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BWTR4_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR4_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR4_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR4_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR4_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BWTR4_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR4_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR4_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR4_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR4_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR4_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR4_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR4_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR4_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BWTR4_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR4_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR4_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR4_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR4_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BWTR4_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR4_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR4_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_PCR2 register  *******************/
-#define  FMC_PCR2_PWAITEN                   0x00000002U        /*!<Wait feature enable bit                   */
-#define  FMC_PCR2_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FMC_PCR2_PTYP                      0x00000008U        /*!<Memory type                               */
-
-#define  FMC_PCR2_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FMC_PCR2_PWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_PCR2_PWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_PCR2_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit          */
-
-#define  FMC_PCR2_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay)          */
-#define  FMC_PCR2_TCLR_0                    0x00000200U        /*!<Bit 0 */
-#define  FMC_PCR2_TCLR_1                    0x00000400U        /*!<Bit 1 */
-#define  FMC_PCR2_TCLR_2                    0x00000800U        /*!<Bit 2 */
-#define  FMC_PCR2_TCLR_3                    0x00001000U        /*!<Bit 3 */
-
-#define  FMC_PCR2_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay)           */
-#define  FMC_PCR2_TAR_0                     0x00002000U        /*!<Bit 0 */
-#define  FMC_PCR2_TAR_1                     0x00004000U        /*!<Bit 1 */
-#define  FMC_PCR2_TAR_2                     0x00008000U        /*!<Bit 2 */
-#define  FMC_PCR2_TAR_3                     0x00010000U        /*!<Bit 3 */
-
-#define  FMC_PCR2_ECCPS                     0x000E0000U        /*!<ECCPS[1:0] bits (ECC page size)           */
-#define  FMC_PCR2_ECCPS_0                   0x00020000U        /*!<Bit 0 */
-#define  FMC_PCR2_ECCPS_1                   0x00040000U        /*!<Bit 1 */
-#define  FMC_PCR2_ECCPS_2                   0x00080000U        /*!<Bit 2 */
-
-/******************  Bit definition for FMC_PCR3 register  *******************/
-#define  FMC_PCR3_PWAITEN                   0x00000002U        /*!<Wait feature enable bit                   */
-#define  FMC_PCR3_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FMC_PCR3_PTYP                      0x00000008U        /*!<Memory type                               */
-
-#define  FMC_PCR3_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FMC_PCR3_PWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_PCR3_PWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_PCR3_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit          */
-
-#define  FMC_PCR3_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay)          */
-#define  FMC_PCR3_TCLR_0                    0x00000200U        /*!<Bit 0 */
-#define  FMC_PCR3_TCLR_1                    0x00000400U        /*!<Bit 1 */
-#define  FMC_PCR3_TCLR_2                    0x00000800U        /*!<Bit 2 */
-#define  FMC_PCR3_TCLR_3                    0x00001000U        /*!<Bit 3 */
-
-#define  FMC_PCR3_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay)           */
-#define  FMC_PCR3_TAR_0                     0x00002000U        /*!<Bit 0 */
-#define  FMC_PCR3_TAR_1                     0x00004000U        /*!<Bit 1 */
-#define  FMC_PCR3_TAR_2                     0x00008000U        /*!<Bit 2 */
-#define  FMC_PCR3_TAR_3                     0x00010000U        /*!<Bit 3 */
-
-#define  FMC_PCR3_ECCPS                     0x000E0000U        /*!<ECCPS[2:0] bits (ECC page size)           */
-#define  FMC_PCR3_ECCPS_0                   0x00020000U        /*!<Bit 0 */
-#define  FMC_PCR3_ECCPS_1                   0x00040000U        /*!<Bit 1 */
-#define  FMC_PCR3_ECCPS_2                   0x00080000U        /*!<Bit 2 */
-
-/******************  Bit definition for FMC_PCR4 register  *******************/
-#define  FMC_PCR4_PWAITEN                   0x00000002U        /*!<Wait feature enable bit                   */
-#define  FMC_PCR4_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FMC_PCR4_PTYP                      0x00000008U        /*!<Memory type                               */
-
-#define  FMC_PCR4_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FMC_PCR4_PWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_PCR4_PWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_PCR4_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit          */
-
-#define  FMC_PCR4_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay)          */
-#define  FMC_PCR4_TCLR_0                    0x00000200U        /*!<Bit 0 */
-#define  FMC_PCR4_TCLR_1                    0x00000400U        /*!<Bit 1 */
-#define  FMC_PCR4_TCLR_2                    0x00000800U        /*!<Bit 2 */
-#define  FMC_PCR4_TCLR_3                    0x00001000U        /*!<Bit 3 */
-
-#define  FMC_PCR4_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay)           */
-#define  FMC_PCR4_TAR_0                     0x00002000U        /*!<Bit 0 */
-#define  FMC_PCR4_TAR_1                     0x00004000U        /*!<Bit 1 */
-#define  FMC_PCR4_TAR_2                     0x00008000U        /*!<Bit 2 */
-#define  FMC_PCR4_TAR_3                     0x00010000U        /*!<Bit 3 */
-
-#define  FMC_PCR4_ECCPS                     0x000E0000U        /*!<ECCPS[2:0] bits (ECC page size)           */
-#define  FMC_PCR4_ECCPS_0                   0x00020000U        /*!<Bit 0 */
-#define  FMC_PCR4_ECCPS_1                   0x00040000U        /*!<Bit 1 */
-#define  FMC_PCR4_ECCPS_2                   0x00080000U        /*!<Bit 2 */
-
-/*******************  Bit definition for FMC_SR2 register  *******************/
-#define  FMC_SR2_IRS                        0x01U               /*!<Interrupt Rising Edge status                */
-#define  FMC_SR2_ILS                        0x02U               /*!<Interrupt Level status                      */
-#define  FMC_SR2_IFS                        0x04U               /*!<Interrupt Falling Edge status               */
-#define  FMC_SR2_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FMC_SR2_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit        */
-#define  FMC_SR2_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FMC_SR2_FEMPT                      0x40U               /*!<FIFO empty                                  */
-
-/*******************  Bit definition for FMC_SR3 register  *******************/
-#define  FMC_SR3_IRS                        0x01U               /*!<Interrupt Rising Edge status                */
-#define  FMC_SR3_ILS                        0x02U               /*!<Interrupt Level status                      */
-#define  FMC_SR3_IFS                        0x04U               /*!<Interrupt Falling Edge status               */
-#define  FMC_SR3_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FMC_SR3_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit        */
-#define  FMC_SR3_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FMC_SR3_FEMPT                      0x40U               /*!<FIFO empty                                  */
-
-/*******************  Bit definition for FMC_SR4 register  *******************/
-#define  FMC_SR4_IRS                        0x01U               /*!<Interrupt Rising Edge status                */
-#define  FMC_SR4_ILS                        0x02U               /*!<Interrupt Level status                      */
-#define  FMC_SR4_IFS                        0x04U               /*!<Interrupt Falling Edge status               */
-#define  FMC_SR4_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FMC_SR4_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit        */
-#define  FMC_SR4_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FMC_SR4_FEMPT                      0x40U               /*!<FIFO empty                                  */
-
-/******************  Bit definition for FMC_PMEM2 register  ******************/
-#define  FMC_PMEM2_MEMSET2                  0x000000FFU        /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
-#define  FMC_PMEM2_MEMSET2_0                0x00000001U        /*!<Bit 0 */
-#define  FMC_PMEM2_MEMSET2_1                0x00000002U        /*!<Bit 1 */
-#define  FMC_PMEM2_MEMSET2_2                0x00000004U        /*!<Bit 2 */
-#define  FMC_PMEM2_MEMSET2_3                0x00000008U        /*!<Bit 3 */
-#define  FMC_PMEM2_MEMSET2_4                0x00000010U        /*!<Bit 4 */
-#define  FMC_PMEM2_MEMSET2_5                0x00000020U        /*!<Bit 5 */
-#define  FMC_PMEM2_MEMSET2_6                0x00000040U        /*!<Bit 6 */
-#define  FMC_PMEM2_MEMSET2_7                0x00000080U        /*!<Bit 7 */
-
-#define  FMC_PMEM2_MEMWAIT2                 0x0000FF00U        /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
-#define  FMC_PMEM2_MEMWAIT2_0               0x00000100U        /*!<Bit 0 */
-#define  FMC_PMEM2_MEMWAIT2_1               0x00000200U        /*!<Bit 1 */
-#define  FMC_PMEM2_MEMWAIT2_2               0x00000400U        /*!<Bit 2 */
-#define  FMC_PMEM2_MEMWAIT2_3               0x00000800U        /*!<Bit 3 */
-#define  FMC_PMEM2_MEMWAIT2_4               0x00001000U        /*!<Bit 4 */
-#define  FMC_PMEM2_MEMWAIT2_5               0x00002000U        /*!<Bit 5 */
-#define  FMC_PMEM2_MEMWAIT2_6               0x00004000U        /*!<Bit 6 */
-#define  FMC_PMEM2_MEMWAIT2_7               0x00008000U        /*!<Bit 7 */
-
-#define  FMC_PMEM2_MEMHOLD2                 0x00FF0000U        /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
-#define  FMC_PMEM2_MEMHOLD2_0               0x00010000U        /*!<Bit 0 */
-#define  FMC_PMEM2_MEMHOLD2_1               0x00020000U        /*!<Bit 1 */
-#define  FMC_PMEM2_MEMHOLD2_2               0x00040000U        /*!<Bit 2 */
-#define  FMC_PMEM2_MEMHOLD2_3               0x00080000U        /*!<Bit 3 */
-#define  FMC_PMEM2_MEMHOLD2_4               0x00100000U        /*!<Bit 4 */
-#define  FMC_PMEM2_MEMHOLD2_5               0x00200000U        /*!<Bit 5 */
-#define  FMC_PMEM2_MEMHOLD2_6               0x00400000U        /*!<Bit 6 */
-#define  FMC_PMEM2_MEMHOLD2_7               0x00800000U        /*!<Bit 7 */
-
-#define  FMC_PMEM2_MEMHIZ2                  0xFF000000U        /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
-#define  FMC_PMEM2_MEMHIZ2_0                0x01000000U        /*!<Bit 0 */
-#define  FMC_PMEM2_MEMHIZ2_1                0x02000000U        /*!<Bit 1 */
-#define  FMC_PMEM2_MEMHIZ2_2                0x04000000U        /*!<Bit 2 */
-#define  FMC_PMEM2_MEMHIZ2_3                0x08000000U        /*!<Bit 3 */
-#define  FMC_PMEM2_MEMHIZ2_4                0x10000000U        /*!<Bit 4 */
-#define  FMC_PMEM2_MEMHIZ2_5                0x20000000U        /*!<Bit 5 */
-#define  FMC_PMEM2_MEMHIZ2_6                0x40000000U        /*!<Bit 6 */
-#define  FMC_PMEM2_MEMHIZ2_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_PMEM3 register  ******************/
-#define  FMC_PMEM3_MEMSET3                  0x000000FFU        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
-#define  FMC_PMEM3_MEMSET3_0                0x00000001U        /*!<Bit 0 */
-#define  FMC_PMEM3_MEMSET3_1                0x00000002U        /*!<Bit 1 */
-#define  FMC_PMEM3_MEMSET3_2                0x00000004U        /*!<Bit 2 */
-#define  FMC_PMEM3_MEMSET3_3                0x00000008U        /*!<Bit 3 */
-#define  FMC_PMEM3_MEMSET3_4                0x00000010U        /*!<Bit 4 */
-#define  FMC_PMEM3_MEMSET3_5                0x00000020U        /*!<Bit 5 */
-#define  FMC_PMEM3_MEMSET3_6                0x00000040U        /*!<Bit 6 */
-#define  FMC_PMEM3_MEMSET3_7                0x00000080U        /*!<Bit 7 */
-
-#define  FMC_PMEM3_MEMWAIT3                 0x0000FF00U        /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
-#define  FMC_PMEM3_MEMWAIT3_0               0x00000100U        /*!<Bit 0 */
-#define  FMC_PMEM3_MEMWAIT3_1               0x00000200U        /*!<Bit 1 */
-#define  FMC_PMEM3_MEMWAIT3_2               0x00000400U        /*!<Bit 2 */
-#define  FMC_PMEM3_MEMWAIT3_3               0x00000800U        /*!<Bit 3 */
-#define  FMC_PMEM3_MEMWAIT3_4               0x00001000U        /*!<Bit 4 */
-#define  FMC_PMEM3_MEMWAIT3_5               0x00002000U        /*!<Bit 5 */
-#define  FMC_PMEM3_MEMWAIT3_6               0x00004000U        /*!<Bit 6 */
-#define  FMC_PMEM3_MEMWAIT3_7               0x00008000U        /*!<Bit 7 */
-
-#define  FMC_PMEM3_MEMHOLD3                 0x00FF0000U        /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
-#define  FMC_PMEM3_MEMHOLD3_0               0x00010000U        /*!<Bit 0 */
-#define  FMC_PMEM3_MEMHOLD3_1               0x00020000U        /*!<Bit 1 */
-#define  FMC_PMEM3_MEMHOLD3_2               0x00040000U        /*!<Bit 2 */
-#define  FMC_PMEM3_MEMHOLD3_3               0x00080000U        /*!<Bit 3 */
-#define  FMC_PMEM3_MEMHOLD3_4               0x00100000U        /*!<Bit 4 */
-#define  FMC_PMEM3_MEMHOLD3_5               0x00200000U        /*!<Bit 5 */
-#define  FMC_PMEM3_MEMHOLD3_6               0x00400000U        /*!<Bit 6 */
-#define  FMC_PMEM3_MEMHOLD3_7               0x00800000U        /*!<Bit 7 */
-
-#define  FMC_PMEM3_MEMHIZ3                  0xFF000000U        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
-#define  FMC_PMEM3_MEMHIZ3_0                0x01000000U        /*!<Bit 0 */
-#define  FMC_PMEM3_MEMHIZ3_1                0x02000000U        /*!<Bit 1 */
-#define  FMC_PMEM3_MEMHIZ3_2                0x04000000U        /*!<Bit 2 */
-#define  FMC_PMEM3_MEMHIZ3_3                0x08000000U        /*!<Bit 3 */
-#define  FMC_PMEM3_MEMHIZ3_4                0x10000000U        /*!<Bit 4 */
-#define  FMC_PMEM3_MEMHIZ3_5                0x20000000U        /*!<Bit 5 */
-#define  FMC_PMEM3_MEMHIZ3_6                0x40000000U        /*!<Bit 6 */
-#define  FMC_PMEM3_MEMHIZ3_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_PMEM4 register  ******************/
-#define  FMC_PMEM4_MEMSET4                  0x000000FFU        /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
-#define  FMC_PMEM4_MEMSET4_0                0x00000001U        /*!<Bit 0 */
-#define  FMC_PMEM4_MEMSET4_1                0x00000002U        /*!<Bit 1 */
-#define  FMC_PMEM4_MEMSET4_2                0x00000004U        /*!<Bit 2 */
-#define  FMC_PMEM4_MEMSET4_3                0x00000008U        /*!<Bit 3 */
-#define  FMC_PMEM4_MEMSET4_4                0x00000010U        /*!<Bit 4 */
-#define  FMC_PMEM4_MEMSET4_5                0x00000020U        /*!<Bit 5 */
-#define  FMC_PMEM4_MEMSET4_6                0x00000040U        /*!<Bit 6 */
-#define  FMC_PMEM4_MEMSET4_7                0x00000080U        /*!<Bit 7 */
-
-#define  FMC_PMEM4_MEMWAIT4                 0x0000FF00U        /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
-#define  FMC_PMEM4_MEMWAIT4_0               0x00000100U        /*!<Bit 0 */
-#define  FMC_PMEM4_MEMWAIT4_1               0x00000200U        /*!<Bit 1 */
-#define  FMC_PMEM4_MEMWAIT4_2               0x00000400U        /*!<Bit 2 */
-#define  FMC_PMEM4_MEMWAIT4_3               0x00000800U        /*!<Bit 3 */
-#define  FMC_PMEM4_MEMWAIT4_4               0x00001000U        /*!<Bit 4 */
-#define  FMC_PMEM4_MEMWAIT4_5               0x00002000U        /*!<Bit 5 */
-#define  FMC_PMEM4_MEMWAIT4_6               0x00004000U        /*!<Bit 6 */
-#define  FMC_PMEM4_MEMWAIT4_7               0x00008000U        /*!<Bit 7 */
-
-#define  FMC_PMEM4_MEMHOLD4                 0x00FF0000U        /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
-#define  FMC_PMEM4_MEMHOLD4_0               0x00010000U        /*!<Bit 0 */
-#define  FMC_PMEM4_MEMHOLD4_1               0x00020000U        /*!<Bit 1 */
-#define  FMC_PMEM4_MEMHOLD4_2               0x00040000U        /*!<Bit 2 */
-#define  FMC_PMEM4_MEMHOLD4_3               0x00080000U        /*!<Bit 3 */
-#define  FMC_PMEM4_MEMHOLD4_4               0x00100000U        /*!<Bit 4 */
-#define  FMC_PMEM4_MEMHOLD4_5               0x00200000U        /*!<Bit 5 */
-#define  FMC_PMEM4_MEMHOLD4_6               0x00400000U        /*!<Bit 6 */
-#define  FMC_PMEM4_MEMHOLD4_7               0x00800000U        /*!<Bit 7 */
-
-#define  FMC_PMEM4_MEMHIZ4                  0xFF000000U        /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
-#define  FMC_PMEM4_MEMHIZ4_0                0x01000000U        /*!<Bit 0 */
-#define  FMC_PMEM4_MEMHIZ4_1                0x02000000U        /*!<Bit 1 */
-#define  FMC_PMEM4_MEMHIZ4_2                0x04000000U        /*!<Bit 2 */
-#define  FMC_PMEM4_MEMHIZ4_3                0x08000000U        /*!<Bit 3 */
-#define  FMC_PMEM4_MEMHIZ4_4                0x10000000U        /*!<Bit 4 */
-#define  FMC_PMEM4_MEMHIZ4_5                0x20000000U        /*!<Bit 5 */
-#define  FMC_PMEM4_MEMHIZ4_6                0x40000000U        /*!<Bit 6 */
-#define  FMC_PMEM4_MEMHIZ4_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_PATT2 register  ******************/
-#define  FMC_PATT2_ATTSET2                  0x000000FFU        /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
-#define  FMC_PATT2_ATTSET2_0                0x00000001U        /*!<Bit 0 */
-#define  FMC_PATT2_ATTSET2_1                0x00000002U        /*!<Bit 1 */
-#define  FMC_PATT2_ATTSET2_2                0x00000004U        /*!<Bit 2 */
-#define  FMC_PATT2_ATTSET2_3                0x00000008U        /*!<Bit 3 */
-#define  FMC_PATT2_ATTSET2_4                0x00000010U        /*!<Bit 4 */
-#define  FMC_PATT2_ATTSET2_5                0x00000020U        /*!<Bit 5 */
-#define  FMC_PATT2_ATTSET2_6                0x00000040U        /*!<Bit 6 */
-#define  FMC_PATT2_ATTSET2_7                0x00000080U        /*!<Bit 7 */
-
-#define  FMC_PATT2_ATTWAIT2                 0x0000FF00U        /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
-#define  FMC_PATT2_ATTWAIT2_0               0x00000100U        /*!<Bit 0 */
-#define  FMC_PATT2_ATTWAIT2_1               0x00000200U        /*!<Bit 1 */
-#define  FMC_PATT2_ATTWAIT2_2               0x00000400U        /*!<Bit 2 */
-#define  FMC_PATT2_ATTWAIT2_3               0x00000800U        /*!<Bit 3 */
-#define  FMC_PATT2_ATTWAIT2_4               0x00001000U        /*!<Bit 4 */
-#define  FMC_PATT2_ATTWAIT2_5               0x00002000U        /*!<Bit 5 */
-#define  FMC_PATT2_ATTWAIT2_6               0x00004000U        /*!<Bit 6 */
-#define  FMC_PATT2_ATTWAIT2_7               0x00008000U        /*!<Bit 7 */
-
-#define  FMC_PATT2_ATTHOLD2                 0x00FF0000U        /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
-#define  FMC_PATT2_ATTHOLD2_0               0x00010000U        /*!<Bit 0 */
-#define  FMC_PATT2_ATTHOLD2_1               0x00020000U        /*!<Bit 1 */
-#define  FMC_PATT2_ATTHOLD2_2               0x00040000U        /*!<Bit 2 */
-#define  FMC_PATT2_ATTHOLD2_3               0x00080000U        /*!<Bit 3 */
-#define  FMC_PATT2_ATTHOLD2_4               0x00100000U        /*!<Bit 4 */
-#define  FMC_PATT2_ATTHOLD2_5               0x00200000U        /*!<Bit 5 */
-#define  FMC_PATT2_ATTHOLD2_6               0x00400000U        /*!<Bit 6 */
-#define  FMC_PATT2_ATTHOLD2_7               0x00800000U        /*!<Bit 7 */
-
-#define  FMC_PATT2_ATTHIZ2                  0xFF000000U        /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
-#define  FMC_PATT2_ATTHIZ2_0                0x01000000U        /*!<Bit 0 */
-#define  FMC_PATT2_ATTHIZ2_1                0x02000000U        /*!<Bit 1 */
-#define  FMC_PATT2_ATTHIZ2_2                0x04000000U        /*!<Bit 2 */
-#define  FMC_PATT2_ATTHIZ2_3                0x08000000U        /*!<Bit 3 */
-#define  FMC_PATT2_ATTHIZ2_4                0x10000000U        /*!<Bit 4 */
-#define  FMC_PATT2_ATTHIZ2_5                0x20000000U        /*!<Bit 5 */
-#define  FMC_PATT2_ATTHIZ2_6                0x40000000U        /*!<Bit 6 */
-#define  FMC_PATT2_ATTHIZ2_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_PATT3 register  ******************/
-#define  FMC_PATT3_ATTSET3                  0x000000FFU        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
-#define  FMC_PATT3_ATTSET3_0                0x00000001U        /*!<Bit 0 */
-#define  FMC_PATT3_ATTSET3_1                0x00000002U        /*!<Bit 1 */
-#define  FMC_PATT3_ATTSET3_2                0x00000004U        /*!<Bit 2 */
-#define  FMC_PATT3_ATTSET3_3                0x00000008U        /*!<Bit 3 */
-#define  FMC_PATT3_ATTSET3_4                0x00000010U        /*!<Bit 4 */
-#define  FMC_PATT3_ATTSET3_5                0x00000020U        /*!<Bit 5 */
-#define  FMC_PATT3_ATTSET3_6                0x00000040U        /*!<Bit 6 */
-#define  FMC_PATT3_ATTSET3_7                0x00000080U        /*!<Bit 7 */
-
-#define  FMC_PATT3_ATTWAIT3                 0x0000FF00U        /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
-#define  FMC_PATT3_ATTWAIT3_0               0x00000100U        /*!<Bit 0 */
-#define  FMC_PATT3_ATTWAIT3_1               0x00000200U        /*!<Bit 1 */
-#define  FMC_PATT3_ATTWAIT3_2               0x00000400U        /*!<Bit 2 */
-#define  FMC_PATT3_ATTWAIT3_3               0x00000800U        /*!<Bit 3 */
-#define  FMC_PATT3_ATTWAIT3_4               0x00001000U        /*!<Bit 4 */
-#define  FMC_PATT3_ATTWAIT3_5               0x00002000U        /*!<Bit 5 */
-#define  FMC_PATT3_ATTWAIT3_6               0x00004000U        /*!<Bit 6 */
-#define  FMC_PATT3_ATTWAIT3_7               0x00008000U        /*!<Bit 7 */
-
-#define  FMC_PATT3_ATTHOLD3                 0x00FF0000U        /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
-#define  FMC_PATT3_ATTHOLD3_0               0x00010000U        /*!<Bit 0 */
-#define  FMC_PATT3_ATTHOLD3_1               0x00020000U        /*!<Bit 1 */
-#define  FMC_PATT3_ATTHOLD3_2               0x00040000U        /*!<Bit 2 */
-#define  FMC_PATT3_ATTHOLD3_3               0x00080000U        /*!<Bit 3 */
-#define  FMC_PATT3_ATTHOLD3_4               0x00100000U        /*!<Bit 4 */
-#define  FMC_PATT3_ATTHOLD3_5               0x00200000U        /*!<Bit 5 */
-#define  FMC_PATT3_ATTHOLD3_6               0x00400000U        /*!<Bit 6 */
-#define  FMC_PATT3_ATTHOLD3_7               0x00800000U        /*!<Bit 7 */
-
-#define  FMC_PATT3_ATTHIZ3                  0xFF000000U        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
-#define  FMC_PATT3_ATTHIZ3_0                0x01000000U        /*!<Bit 0 */
-#define  FMC_PATT3_ATTHIZ3_1                0x02000000U        /*!<Bit 1 */
-#define  FMC_PATT3_ATTHIZ3_2                0x04000000U        /*!<Bit 2 */
-#define  FMC_PATT3_ATTHIZ3_3                0x08000000U        /*!<Bit 3 */
-#define  FMC_PATT3_ATTHIZ3_4                0x10000000U        /*!<Bit 4 */
-#define  FMC_PATT3_ATTHIZ3_5                0x20000000U        /*!<Bit 5 */
-#define  FMC_PATT3_ATTHIZ3_6                0x40000000U        /*!<Bit 6 */
-#define  FMC_PATT3_ATTHIZ3_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_PATT4 register  ******************/
-#define  FMC_PATT4_ATTSET4                  0x000000FFU        /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
-#define  FMC_PATT4_ATTSET4_0                0x00000001U        /*!<Bit 0 */
-#define  FMC_PATT4_ATTSET4_1                0x00000002U        /*!<Bit 1 */
-#define  FMC_PATT4_ATTSET4_2                0x00000004U        /*!<Bit 2 */
-#define  FMC_PATT4_ATTSET4_3                0x00000008U        /*!<Bit 3 */
-#define  FMC_PATT4_ATTSET4_4                0x00000010U        /*!<Bit 4 */
-#define  FMC_PATT4_ATTSET4_5                0x00000020U        /*!<Bit 5 */
-#define  FMC_PATT4_ATTSET4_6                0x00000040U        /*!<Bit 6 */
-#define  FMC_PATT4_ATTSET4_7                0x00000080U        /*!<Bit 7 */
-
-#define  FMC_PATT4_ATTWAIT4                 0x0000FF00U        /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
-#define  FMC_PATT4_ATTWAIT4_0               0x00000100U        /*!<Bit 0 */
-#define  FMC_PATT4_ATTWAIT4_1               0x00000200U        /*!<Bit 1 */
-#define  FMC_PATT4_ATTWAIT4_2               0x00000400U        /*!<Bit 2 */
-#define  FMC_PATT4_ATTWAIT4_3               0x00000800U        /*!<Bit 3 */
-#define  FMC_PATT4_ATTWAIT4_4               0x00001000U        /*!<Bit 4 */
-#define  FMC_PATT4_ATTWAIT4_5               0x00002000U        /*!<Bit 5 */
-#define  FMC_PATT4_ATTWAIT4_6               0x00004000U        /*!<Bit 6 */
-#define  FMC_PATT4_ATTWAIT4_7               0x00008000U        /*!<Bit 7 */
-
-#define  FMC_PATT4_ATTHOLD4                 0x00FF0000U        /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
-#define  FMC_PATT4_ATTHOLD4_0               0x00010000U        /*!<Bit 0 */
-#define  FMC_PATT4_ATTHOLD4_1               0x00020000U        /*!<Bit 1 */
-#define  FMC_PATT4_ATTHOLD4_2               0x00040000U        /*!<Bit 2 */
-#define  FMC_PATT4_ATTHOLD4_3               0x00080000U        /*!<Bit 3 */
-#define  FMC_PATT4_ATTHOLD4_4               0x00100000U        /*!<Bit 4 */
-#define  FMC_PATT4_ATTHOLD4_5               0x00200000U        /*!<Bit 5 */
-#define  FMC_PATT4_ATTHOLD4_6               0x00400000U        /*!<Bit 6 */
-#define  FMC_PATT4_ATTHOLD4_7               0x00800000U        /*!<Bit 7 */
-
-#define  FMC_PATT4_ATTHIZ4                  0xFF000000U        /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
-#define  FMC_PATT4_ATTHIZ4_0                0x01000000U        /*!<Bit 0 */
-#define  FMC_PATT4_ATTHIZ4_1                0x02000000U        /*!<Bit 1 */
-#define  FMC_PATT4_ATTHIZ4_2                0x04000000U        /*!<Bit 2 */
-#define  FMC_PATT4_ATTHIZ4_3                0x08000000U        /*!<Bit 3 */
-#define  FMC_PATT4_ATTHIZ4_4                0x10000000U        /*!<Bit 4 */
-#define  FMC_PATT4_ATTHIZ4_5                0x20000000U        /*!<Bit 5 */
-#define  FMC_PATT4_ATTHIZ4_6                0x40000000U        /*!<Bit 6 */
-#define  FMC_PATT4_ATTHIZ4_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_PIO4 register  *******************/
-#define  FMC_PIO4_IOSET4                    0x000000FFU        /*!<IOSET4[7:0] bits (I/O 4 setup time) */
-#define  FMC_PIO4_IOSET4_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_PIO4_IOSET4_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_PIO4_IOSET4_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_PIO4_IOSET4_3                  0x00000008U        /*!<Bit 3 */
-#define  FMC_PIO4_IOSET4_4                  0x00000010U        /*!<Bit 4 */
-#define  FMC_PIO4_IOSET4_5                  0x00000020U        /*!<Bit 5 */
-#define  FMC_PIO4_IOSET4_6                  0x00000040U        /*!<Bit 6 */
-#define  FMC_PIO4_IOSET4_7                  0x00000080U        /*!<Bit 7 */
-
-#define  FMC_PIO4_IOWAIT4                   0x0000FF00U        /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
-#define  FMC_PIO4_IOWAIT4_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_PIO4_IOWAIT4_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_PIO4_IOWAIT4_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_PIO4_IOWAIT4_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_PIO4_IOWAIT4_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_PIO4_IOWAIT4_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_PIO4_IOWAIT4_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_PIO4_IOWAIT4_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FMC_PIO4_IOHOLD4                   0x00FF0000U        /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
-#define  FMC_PIO4_IOHOLD4_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_PIO4_IOHOLD4_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_PIO4_IOHOLD4_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_PIO4_IOHOLD4_3                 0x00080000U        /*!<Bit 3 */
-#define  FMC_PIO4_IOHOLD4_4                 0x00100000U        /*!<Bit 4 */
-#define  FMC_PIO4_IOHOLD4_5                 0x00200000U        /*!<Bit 5 */
-#define  FMC_PIO4_IOHOLD4_6                 0x00400000U        /*!<Bit 6 */
-#define  FMC_PIO4_IOHOLD4_7                 0x00800000U        /*!<Bit 7 */
-
-#define  FMC_PIO4_IOHIZ4                    0xFF000000U        /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
-#define  FMC_PIO4_IOHIZ4_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_PIO4_IOHIZ4_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_PIO4_IOHIZ4_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_PIO4_IOHIZ4_3                  0x08000000U        /*!<Bit 3 */
-#define  FMC_PIO4_IOHIZ4_4                  0x10000000U        /*!<Bit 4 */
-#define  FMC_PIO4_IOHIZ4_5                  0x20000000U        /*!<Bit 5 */
-#define  FMC_PIO4_IOHIZ4_6                  0x40000000U        /*!<Bit 6 */
-#define  FMC_PIO4_IOHIZ4_7                  0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_ECCR2 register  ******************/
-#define  FMC_ECCR2_ECC2                     0xFFFFFFFFU        /*!<ECC result */
-
-/******************  Bit definition for FMC_ECCR3 register  ******************/
-#define  FMC_ECCR3_ECC3                     0xFFFFFFFFU        /*!<ECC result */
-
-/******************  Bit definition for FMC_SDCR1 register  ******************/
-#define  FMC_SDCR1_NC                       0x00000003U        /*!<NC[1:0] bits (Number of column bits) */
-#define  FMC_SDCR1_NC_0                     0x00000001U        /*!<Bit 0 */
-#define  FMC_SDCR1_NC_1                     0x00000002U        /*!<Bit 1 */
-
-#define  FMC_SDCR1_NR                       0x0000000CU        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR1_NR_0                     0x00000004U        /*!<Bit 0 */
-#define  FMC_SDCR1_NR_1                     0x00000008U        /*!<Bit 1 */
-
-#define  FMC_SDCR1_MWID                     0x00000030U        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR1_MWID_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDCR1_MWID_1                   0x00000020U        /*!<Bit 1 */
-
-#define  FMC_SDCR1_NB                       0x00000040U        /*!<Number of internal bank */
-
-#define  FMC_SDCR1_CAS                      0x00000180U        /*!<CAS[1:0] bits (CAS latency) */
-#define  FMC_SDCR1_CAS_0                    0x00000080U        /*!<Bit 0 */
-#define  FMC_SDCR1_CAS_1                    0x00000100U        /*!<Bit 1 */
-
-#define  FMC_SDCR1_WP                       0x00000200U        /*!<Write protection */
-
-#define  FMC_SDCR1_SDCLK                    0x00000C00U        /*!<SDRAM clock configuration */
-#define  FMC_SDCR1_SDCLK_0                  0x00000400U        /*!<Bit 0 */
-#define  FMC_SDCR1_SDCLK_1                  0x00000800U        /*!<Bit 1 */
-
-#define  FMC_SDCR1_RBURST                   0x00001000U        /*!<Read burst */
-
-#define  FMC_SDCR1_RPIPE                    0x00006000U        /*!<Write protection */
-#define  FMC_SDCR1_RPIPE_0                  0x00002000U        /*!<Bit 0 */
-#define  FMC_SDCR1_RPIPE_1                  0x00004000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_SDCR2 register  ******************/
-#define  FMC_SDCR2_NC                       0x00000003U        /*!<NC[1:0] bits (Number of column bits) */
-#define  FMC_SDCR2_NC_0                     0x00000001U        /*!<Bit 0 */
-#define  FMC_SDCR2_NC_1                     0x00000002U        /*!<Bit 1 */
-
-#define  FMC_SDCR2_NR                       0x0000000CU        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR2_NR_0                     0x00000004U        /*!<Bit 0 */
-#define  FMC_SDCR2_NR_1                     0x00000008U        /*!<Bit 1 */
-
-#define  FMC_SDCR2_MWID                     0x00000030U        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR2_MWID_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDCR2_MWID_1                   0x00000020U        /*!<Bit 1 */
-
-#define  FMC_SDCR2_NB                       0x00000040U        /*!<Number of internal bank */
-
-#define  FMC_SDCR2_CAS                      0x00000180U        /*!<CAS[1:0] bits (CAS latency) */
-#define  FMC_SDCR2_CAS_0                    0x00000080U        /*!<Bit 0 */
-#define  FMC_SDCR2_CAS_1                    0x00000100U        /*!<Bit 1 */
-
-#define  FMC_SDCR2_WP                       0x00000200U        /*!<Write protection */
-
-#define  FMC_SDCR2_SDCLK                    0x00000C00U        /*!<SDCLK[1:0] (SDRAM clock configuration) */
-#define  FMC_SDCR2_SDCLK_0                  0x00000400U        /*!<Bit 0 */
-#define  FMC_SDCR2_SDCLK_1                  0x00000800U        /*!<Bit 1 */
-
-#define  FMC_SDCR2_RBURST                   0x00001000U        /*!<Read burst */
-
-#define  FMC_SDCR2_RPIPE                    0x00006000U        /*!<RPIPE[1:0](Read pipe) */
-#define  FMC_SDCR2_RPIPE_0                  0x00002000U        /*!<Bit 0 */
-#define  FMC_SDCR2_RPIPE_1                  0x00004000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_SDTR1 register  ******************/
-#define  FMC_SDTR1_TMRD                     0x0000000FU        /*!<TMRD[3:0] bits (Load mode register to active) */
-#define  FMC_SDTR1_TMRD_0                   0x00000001U        /*!<Bit 0 */
-#define  FMC_SDTR1_TMRD_1                   0x00000002U        /*!<Bit 1 */
-#define  FMC_SDTR1_TMRD_2                   0x00000004U        /*!<Bit 2 */
-#define  FMC_SDTR1_TMRD_3                   0x00000008U        /*!<Bit 3 */
-                                            
-#define  FMC_SDTR1_TXSR                     0x000000F0U        /*!<TXSR[3:0] bits (Exit self refresh) */
-#define  FMC_SDTR1_TXSR_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDTR1_TXSR_1                   0x00000020U        /*!<Bit 1 */
-#define  FMC_SDTR1_TXSR_2                   0x00000040U        /*!<Bit 2 */
-#define  FMC_SDTR1_TXSR_3                   0x00000080U        /*!<Bit 3 */
-
-#define  FMC_SDTR1_TRAS                     0x00000F00U        /*!<TRAS[3:0] bits (Self refresh time) */
-#define  FMC_SDTR1_TRAS_0                   0x00000100U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRAS_1                   0x00000200U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRAS_2                   0x00000400U        /*!<Bit 2 */
-#define  FMC_SDTR1_TRAS_3                   0x00000800U        /*!<Bit 3 */
-
-#define  FMC_SDTR1_TRC                      0x0000F000U        /*!<TRC[2:0] bits (Row cycle delay) */
-#define  FMC_SDTR1_TRC_0                    0x00001000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRC_1                    0x00002000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRC_2                    0x00004000U        /*!<Bit 2 */
-
-#define  FMC_SDTR1_TWR                      0x000F0000U        /*!<TRC[2:0] bits (Write recovery delay) */
-#define  FMC_SDTR1_TWR_0                    0x00010000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TWR_1                    0x00020000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TWR_2                    0x00040000U        /*!<Bit 2 */
-
-#define  FMC_SDTR1_TRP                      0x00F00000U        /*!<TRP[2:0] bits (Row precharge delay) */
-#define  FMC_SDTR1_TRP_0                    0x00100000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRP_1                    0x00200000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRP_2                    0x00400000U        /*!<Bit 2 */
-
-#define  FMC_SDTR1_TRCD                     0x0F000000U        /*!<TRP[2:0] bits (Row to column delay) */
-#define  FMC_SDTR1_TRCD_0                   0x01000000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRCD_1                   0x02000000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRCD_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for FMC_SDTR2 register  ******************/
-#define  FMC_SDTR2_TMRD                     0x0000000FU        /*!<TMRD[3:0] bits (Load mode register to active) */
-#define  FMC_SDTR2_TMRD_0                   0x00000001U        /*!<Bit 0 */
-#define  FMC_SDTR2_TMRD_1                   0x00000002U        /*!<Bit 1 */
-#define  FMC_SDTR2_TMRD_2                   0x00000004U        /*!<Bit 2 */
-#define  FMC_SDTR2_TMRD_3                   0x00000008U        /*!<Bit 3 */
-                                            
-#define  FMC_SDTR2_TXSR                     0x000000F0U        /*!<TXSR[3:0] bits (Exit self refresh) */
-#define  FMC_SDTR2_TXSR_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDTR2_TXSR_1                   0x00000020U        /*!<Bit 1 */
-#define  FMC_SDTR2_TXSR_2                   0x00000040U        /*!<Bit 2 */
-#define  FMC_SDTR2_TXSR_3                   0x00000080U        /*!<Bit 3 */
-
-#define  FMC_SDTR2_TRAS                     0x00000F00U        /*!<TRAS[3:0] bits (Self refresh time) */
-#define  FMC_SDTR2_TRAS_0                   0x00000100U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRAS_1                   0x00000200U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRAS_2                   0x00000400U        /*!<Bit 2 */
-#define  FMC_SDTR2_TRAS_3                   0x00000800U        /*!<Bit 3 */
-
-#define  FMC_SDTR2_TRC                      0x0000F000U        /*!<TRC[2:0] bits (Row cycle delay) */
-#define  FMC_SDTR2_TRC_0                    0x00001000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRC_1                    0x00002000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRC_2                    0x00004000U        /*!<Bit 2 */
-
-#define  FMC_SDTR2_TWR                      0x000F0000U        /*!<TRC[2:0] bits (Write recovery delay) */
-#define  FMC_SDTR2_TWR_0                    0x00010000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TWR_1                    0x00020000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TWR_2                    0x00040000U        /*!<Bit 2 */
-
-#define  FMC_SDTR2_TRP                      0x00F00000U        /*!<TRP[2:0] bits (Row precharge delay) */
-#define  FMC_SDTR2_TRP_0                    0x00100000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRP_1                    0x00200000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRP_2                    0x00400000U        /*!<Bit 2 */
-
-#define  FMC_SDTR2_TRCD                     0x0F000000U        /*!<TRP[2:0] bits (Row to column delay) */
-#define  FMC_SDTR2_TRCD_0                   0x01000000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRCD_1                   0x02000000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRCD_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for FMC_SDCMR register  ******************/
-#define  FMC_SDCMR_MODE                     0x00000007U        /*!<MODE[2:0] bits (Command mode) */
-#define  FMC_SDCMR_MODE_0                   0x00000001U        /*!<Bit 0 */
-#define  FMC_SDCMR_MODE_1                   0x00000002U        /*!<Bit 1 */
-#define  FMC_SDCMR_MODE_2                   0x00000004U        /*!<Bit 2 */
-                                            
-#define  FMC_SDCMR_CTB2                     0x00000008U        /*!<Command target 2 */
-
-#define  FMC_SDCMR_CTB1                     0x00000010U        /*!<Command target 1 */
-
-#define  FMC_SDCMR_NRFS                     0x000001E0U        /*!<NRFS[3:0] bits (Number of auto-refresh) */
-#define  FMC_SDCMR_NRFS_0                   0x00000020U        /*!<Bit 0 */
-#define  FMC_SDCMR_NRFS_1                   0x00000040U        /*!<Bit 1 */
-#define  FMC_SDCMR_NRFS_2                   0x00000080U        /*!<Bit 2 */
-#define  FMC_SDCMR_NRFS_3                   0x00000100U        /*!<Bit 3 */
-
-#define  FMC_SDCMR_MRD                      0x003FFE00U        /*!<MRD[12:0] bits (Mode register definition) */
-
-/******************  Bit definition for FMC_SDRTR register  ******************/
-#define  FMC_SDRTR_CRE                      0x00000001U        /*!<Clear refresh error flag */
-
-#define  FMC_SDRTR_COUNT                    0x00003FFEU        /*!<COUNT[12:0] bits (Refresh timer count) */
-
-#define  FMC_SDRTR_REIE                     0x00004000U        /*!<RES interupt enable */
-
-/******************  Bit definition for FMC_SDSR register  ******************/
-#define  FMC_SDSR_RE                        0x00000001U        /*!<Refresh error flag */
-
-#define  FMC_SDSR_MODES1                    0x00000006U        /*!<MODES1[1:0]bits (Status mode for bank 1) */
-#define  FMC_SDSR_MODES1_0                  0x00000002U        /*!<Bit 0 */
-#define  FMC_SDSR_MODES1_1                  0x00000004U        /*!<Bit 1 */
-
-#define  FMC_SDSR_MODES2                    0x00000018U        /*!<MODES2[1:0]bits (Status mode for bank 2) */
-#define  FMC_SDSR_MODES2_0                  0x00000008U        /*!<Bit 0 */
-#define  FMC_SDSR_MODES2_1                  0x00000010U        /*!<Bit 1 */
-#define  FMC_SDSR_BUSY                      0x00000020U        /*!<Busy status */
-
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    0x00000003U
-#define GPIO_MODER_MODER0_0                  0x00000001U
-#define GPIO_MODER_MODER0_1                  0x00000002U
-
-#define GPIO_MODER_MODER1                    0x0000000CU
-#define GPIO_MODER_MODER1_0                  0x00000004U
-#define GPIO_MODER_MODER1_1                  0x00000008U
-
-#define GPIO_MODER_MODER2                    0x00000030U
-#define GPIO_MODER_MODER2_0                  0x00000010U
-#define GPIO_MODER_MODER2_1                  0x00000020U
-
-#define GPIO_MODER_MODER3                    0x000000C0U
-#define GPIO_MODER_MODER3_0                  0x00000040U
-#define GPIO_MODER_MODER3_1                  0x00000080U
-
-#define GPIO_MODER_MODER4                    0x00000300U
-#define GPIO_MODER_MODER4_0                  0x00000100U
-#define GPIO_MODER_MODER4_1                  0x00000200U
-
-#define GPIO_MODER_MODER5                    0x00000C00U
-#define GPIO_MODER_MODER5_0                  0x00000400U
-#define GPIO_MODER_MODER5_1                  0x00000800U
-
-#define GPIO_MODER_MODER6                    0x00003000U
-#define GPIO_MODER_MODER6_0                  0x00001000U
-#define GPIO_MODER_MODER6_1                  0x00002000U
-
-#define GPIO_MODER_MODER7                    0x0000C000U
-#define GPIO_MODER_MODER7_0                  0x00004000U
-#define GPIO_MODER_MODER7_1                  0x00008000U
-
-#define GPIO_MODER_MODER8                    0x00030000U
-#define GPIO_MODER_MODER8_0                  0x00010000U
-#define GPIO_MODER_MODER8_1                  0x00020000U
-
-#define GPIO_MODER_MODER9                    0x000C0000U
-#define GPIO_MODER_MODER9_0                  0x00040000U
-#define GPIO_MODER_MODER9_1                  0x00080000U
-
-#define GPIO_MODER_MODER10                   0x00300000U
-#define GPIO_MODER_MODER10_0                 0x00100000U
-#define GPIO_MODER_MODER10_1                 0x00200000U
-
-#define GPIO_MODER_MODER11                   0x00C00000U
-#define GPIO_MODER_MODER11_0                 0x00400000U
-#define GPIO_MODER_MODER11_1                 0x00800000U
-
-#define GPIO_MODER_MODER12                   0x03000000U
-#define GPIO_MODER_MODER12_0                 0x01000000U
-#define GPIO_MODER_MODER12_1                 0x02000000U
-
-#define GPIO_MODER_MODER13                   0x0C000000U
-#define GPIO_MODER_MODER13_0                 0x04000000U
-#define GPIO_MODER_MODER13_1                 0x08000000U
-
-#define GPIO_MODER_MODER14                   0x30000000U
-#define GPIO_MODER_MODER14_0                 0x10000000U
-#define GPIO_MODER_MODER14_1                 0x20000000U
-
-#define GPIO_MODER_MODER15                   0xC0000000U
-#define GPIO_MODER_MODER15_0                 0x40000000U
-#define GPIO_MODER_MODER15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     0x00000001U
-#define GPIO_OTYPER_OT_1                     0x00000002U
-#define GPIO_OTYPER_OT_2                     0x00000004U
-#define GPIO_OTYPER_OT_3                     0x00000008U
-#define GPIO_OTYPER_OT_4                     0x00000010U
-#define GPIO_OTYPER_OT_5                     0x00000020U
-#define GPIO_OTYPER_OT_6                     0x00000040U
-#define GPIO_OTYPER_OT_7                     0x00000080U
-#define GPIO_OTYPER_OT_8                     0x00000100U
-#define GPIO_OTYPER_OT_9                     0x00000200U
-#define GPIO_OTYPER_OT_10                    0x00000400U
-#define GPIO_OTYPER_OT_11                    0x00000800U
-#define GPIO_OTYPER_OT_12                    0x00001000U
-#define GPIO_OTYPER_OT_13                    0x00002000U
-#define GPIO_OTYPER_OT_14                    0x00004000U
-#define GPIO_OTYPER_OT_15                    0x00008000U
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
-#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
-#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
-
-#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
-#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
-#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
-
-#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
-#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
-#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
-
-#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
-#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
-#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
-
-#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
-#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
-#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
-
-#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
-#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
-#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
-
-#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
-#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
-#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
-
-#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
-#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
-#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
-
-#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
-#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
-#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
-
-#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
-#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
-#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
-
-#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
-#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
-#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
-
-#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
-#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
-#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
-
-#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
-#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
-#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
-
-#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
-#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
-#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
-
-#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
-#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
-#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
-
-#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
-#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
-#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    0x00000003U
-#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
-#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
-
-#define GPIO_PUPDR_PUPDR1                    0x0000000CU
-#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
-#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
-
-#define GPIO_PUPDR_PUPDR2                    0x00000030U
-#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
-#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
-
-#define GPIO_PUPDR_PUPDR3                    0x000000C0U
-#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
-#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
-
-#define GPIO_PUPDR_PUPDR4                    0x00000300U
-#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
-#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
-
-#define GPIO_PUPDR_PUPDR5                    0x00000C00U
-#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
-#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
-
-#define GPIO_PUPDR_PUPDR6                    0x00003000U
-#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
-#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
-
-#define GPIO_PUPDR_PUPDR7                    0x0000C000U
-#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
-#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
-
-#define GPIO_PUPDR_PUPDR8                    0x00030000U
-#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
-#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
-
-#define GPIO_PUPDR_PUPDR9                    0x000C0000U
-#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
-#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
-
-#define GPIO_PUPDR_PUPDR10                   0x00300000U
-#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
-#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
-
-#define GPIO_PUPDR_PUPDR11                   0x00C00000U
-#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
-#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
-
-#define GPIO_PUPDR_PUPDR12                   0x03000000U
-#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
-#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
-
-#define GPIO_PUPDR_PUPDR13                   0x0C000000U
-#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
-#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
-
-#define GPIO_PUPDR_PUPDR14                   0x30000000U
-#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
-#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
-
-#define GPIO_PUPDR_PUPDR15                   0xC0000000U
-#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
-#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       0x00000001U
-#define GPIO_IDR_IDR_1                       0x00000002U
-#define GPIO_IDR_IDR_2                       0x00000004U
-#define GPIO_IDR_IDR_3                       0x00000008U
-#define GPIO_IDR_IDR_4                       0x00000010U
-#define GPIO_IDR_IDR_5                       0x00000020U
-#define GPIO_IDR_IDR_6                       0x00000040U
-#define GPIO_IDR_IDR_7                       0x00000080U
-#define GPIO_IDR_IDR_8                       0x00000100U
-#define GPIO_IDR_IDR_9                       0x00000200U
-#define GPIO_IDR_IDR_10                      0x00000400U
-#define GPIO_IDR_IDR_11                      0x00000800U
-#define GPIO_IDR_IDR_12                      0x00001000U
-#define GPIO_IDR_IDR_13                      0x00002000U
-#define GPIO_IDR_IDR_14                      0x00004000U
-#define GPIO_IDR_IDR_15                      0x00008000U
-/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
-#define GPIO_OTYPER_IDR_0                    GPIO_IDR_IDR_0
-#define GPIO_OTYPER_IDR_1                    GPIO_IDR_IDR_1
-#define GPIO_OTYPER_IDR_2                    GPIO_IDR_IDR_2
-#define GPIO_OTYPER_IDR_3                    GPIO_IDR_IDR_3
-#define GPIO_OTYPER_IDR_4                    GPIO_IDR_IDR_4
-#define GPIO_OTYPER_IDR_5                    GPIO_IDR_IDR_5
-#define GPIO_OTYPER_IDR_6                    GPIO_IDR_IDR_6
-#define GPIO_OTYPER_IDR_7                    GPIO_IDR_IDR_7
-#define GPIO_OTYPER_IDR_8                    GPIO_IDR_IDR_8
-#define GPIO_OTYPER_IDR_9                    GPIO_IDR_IDR_9
-#define GPIO_OTYPER_IDR_10                   GPIO_IDR_IDR_10
-#define GPIO_OTYPER_IDR_11                   GPIO_IDR_IDR_11
-#define GPIO_OTYPER_IDR_12                   GPIO_IDR_IDR_12
-#define GPIO_OTYPER_IDR_13                   GPIO_IDR_IDR_13
-#define GPIO_OTYPER_IDR_14                   GPIO_IDR_IDR_14
-#define GPIO_OTYPER_IDR_15                   GPIO_IDR_IDR_15
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       0x00000001U
-#define GPIO_ODR_ODR_1                       0x00000002U
-#define GPIO_ODR_ODR_2                       0x00000004U
-#define GPIO_ODR_ODR_3                       0x00000008U
-#define GPIO_ODR_ODR_4                       0x00000010U
-#define GPIO_ODR_ODR_5                       0x00000020U
-#define GPIO_ODR_ODR_6                       0x00000040U
-#define GPIO_ODR_ODR_7                       0x00000080U
-#define GPIO_ODR_ODR_8                       0x00000100U
-#define GPIO_ODR_ODR_9                       0x00000200U
-#define GPIO_ODR_ODR_10                      0x00000400U
-#define GPIO_ODR_ODR_11                      0x00000800U
-#define GPIO_ODR_ODR_12                      0x00001000U
-#define GPIO_ODR_ODR_13                      0x00002000U
-#define GPIO_ODR_ODR_14                      0x00004000U
-#define GPIO_ODR_ODR_15                      0x00008000U
-/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
-#define GPIO_OTYPER_ODR_0                    GPIO_ODR_ODR_0
-#define GPIO_OTYPER_ODR_1                    GPIO_ODR_ODR_1
-#define GPIO_OTYPER_ODR_2                    GPIO_ODR_ODR_2
-#define GPIO_OTYPER_ODR_3                    GPIO_ODR_ODR_3
-#define GPIO_OTYPER_ODR_4                    GPIO_ODR_ODR_4
-#define GPIO_OTYPER_ODR_5                    GPIO_ODR_ODR_5
-#define GPIO_OTYPER_ODR_6                    GPIO_ODR_ODR_6
-#define GPIO_OTYPER_ODR_7                    GPIO_ODR_ODR_7
-#define GPIO_OTYPER_ODR_8                    GPIO_ODR_ODR_8
-#define GPIO_OTYPER_ODR_9                    GPIO_ODR_ODR_9
-#define GPIO_OTYPER_ODR_10                   GPIO_ODR_ODR_10
-#define GPIO_OTYPER_ODR_11                   GPIO_ODR_ODR_11
-#define GPIO_OTYPER_ODR_12                   GPIO_ODR_ODR_12
-#define GPIO_OTYPER_ODR_13                   GPIO_ODR_ODR_13
-#define GPIO_OTYPER_ODR_14                   GPIO_ODR_ODR_14
-#define GPIO_OTYPER_ODR_15                   GPIO_ODR_ODR_15
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       0x00000001U
-#define GPIO_BSRR_BS_1                       0x00000002U
-#define GPIO_BSRR_BS_2                       0x00000004U
-#define GPIO_BSRR_BS_3                       0x00000008U
-#define GPIO_BSRR_BS_4                       0x00000010U
-#define GPIO_BSRR_BS_5                       0x00000020U
-#define GPIO_BSRR_BS_6                       0x00000040U
-#define GPIO_BSRR_BS_7                       0x00000080U
-#define GPIO_BSRR_BS_8                       0x00000100U
-#define GPIO_BSRR_BS_9                       0x00000200U
-#define GPIO_BSRR_BS_10                      0x00000400U
-#define GPIO_BSRR_BS_11                      0x00000800U
-#define GPIO_BSRR_BS_12                      0x00001000U
-#define GPIO_BSRR_BS_13                      0x00002000U
-#define GPIO_BSRR_BS_14                      0x00004000U
-#define GPIO_BSRR_BS_15                      0x00008000U
-#define GPIO_BSRR_BR_0                       0x00010000U
-#define GPIO_BSRR_BR_1                       0x00020000U
-#define GPIO_BSRR_BR_2                       0x00040000U
-#define GPIO_BSRR_BR_3                       0x00080000U
-#define GPIO_BSRR_BR_4                       0x00100000U
-#define GPIO_BSRR_BR_5                       0x00200000U
-#define GPIO_BSRR_BR_6                       0x00400000U
-#define GPIO_BSRR_BR_7                       0x00800000U
-#define GPIO_BSRR_BR_8                       0x01000000U
-#define GPIO_BSRR_BR_9                       0x02000000U
-#define GPIO_BSRR_BR_10                      0x04000000U
-#define GPIO_BSRR_BR_11                      0x08000000U
-#define GPIO_BSRR_BR_12                      0x10000000U
-#define GPIO_BSRR_BR_13                      0x20000000U
-#define GPIO_BSRR_BR_14                      0x40000000U
-#define GPIO_BSRR_BR_15                      0x80000000U
-
-/****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0                       0x00000001U
-#define GPIO_LCKR_LCK1                       0x00000002U
-#define GPIO_LCKR_LCK2                       0x00000004U
-#define GPIO_LCKR_LCK3                       0x00000008U
-#define GPIO_LCKR_LCK4                       0x00000010U
-#define GPIO_LCKR_LCK5                       0x00000020U
-#define GPIO_LCKR_LCK6                       0x00000040U
-#define GPIO_LCKR_LCK7                       0x00000080U
-#define GPIO_LCKR_LCK8                       0x00000100U
-#define GPIO_LCKR_LCK9                       0x00000200U
-#define GPIO_LCKR_LCK10                      0x00000400U
-#define GPIO_LCKR_LCK11                      0x00000800U
-#define GPIO_LCKR_LCK12                      0x00001000U
-#define GPIO_LCKR_LCK13                      0x00002000U
-#define GPIO_LCKR_LCK14                      0x00004000U
-#define GPIO_LCKR_LCK15                      0x00008000U
-#define GPIO_LCKR_LCKK                       0x00010000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    HASH                                    */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for HASH_CR register  ********************/
-#define HASH_CR_INIT                         0x00000004U
-#define HASH_CR_DMAE                         0x00000008U
-#define HASH_CR_DATATYPE                     0x00000030U
-#define HASH_CR_DATATYPE_0                   0x00000010U
-#define HASH_CR_DATATYPE_1                   0x00000020U
-#define HASH_CR_MODE                         0x00000040U
-#define HASH_CR_ALGO                         0x00040080U
-#define HASH_CR_ALGO_0                       0x00000080U
-#define HASH_CR_ALGO_1                       0x00040000U
-#define HASH_CR_NBW                          0x00000F00U
-#define HASH_CR_NBW_0                        0x00000100U
-#define HASH_CR_NBW_1                        0x00000200U
-#define HASH_CR_NBW_2                        0x00000400U
-#define HASH_CR_NBW_3                        0x00000800U
-#define HASH_CR_DINNE                        0x00001000U
-#define HASH_CR_MDMAT                        0x00002000U
-#define HASH_CR_LKEY                         0x00010000U
-
-/******************  Bits definition for HASH_STR register  *******************/
-#define HASH_STR_NBLW                        0x0000001FU
-#define HASH_STR_NBLW_0                      0x00000001U
-#define HASH_STR_NBLW_1                      0x00000002U
-#define HASH_STR_NBLW_2                      0x00000004U
-#define HASH_STR_NBLW_3                      0x00000008U
-#define HASH_STR_NBLW_4                      0x00000010U
-#define HASH_STR_DCAL                        0x00000100U
-/* Aliases for HASH_STR register */
-#define HASH_STR_NBW                         HASH_STR_NBLW
-#define HASH_STR_NBW_0                       HASH_STR_NBLW_0
-#define HASH_STR_NBW_1                       HASH_STR_NBLW_1
-#define HASH_STR_NBW_2                       HASH_STR_NBLW_2
-#define HASH_STR_NBW_3                       HASH_STR_NBLW_3
-#define HASH_STR_NBW_4                       HASH_STR_NBLW_4
-
-/******************  Bits definition for HASH_IMR register  *******************/
-#define HASH_IMR_DINIE                       0x00000001U
-#define HASH_IMR_DCIE                        0x00000002U
-/* Aliases for HASH_IMR register */
-#define HASH_IMR_DINIM                       HASH_IMR_DINIE
-#define HASH_IMR_DCIM                        HASH_IMR_DCIE
-
-/******************  Bits definition for HASH_SR register  ********************/
-#define HASH_SR_DINIS                        0x00000001U
-#define HASH_SR_DCIS                         0x00000002U
-#define HASH_SR_DMAS                         0x00000004U
-#define HASH_SR_BUSY                         0x00000008U
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Inter-integrated Circuit Interface                    */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          0x00000001U     /*!<Peripheral Enable                             */
-#define  I2C_CR1_SMBUS                       0x00000002U     /*!<SMBus Mode                                    */
-#define  I2C_CR1_SMBTYPE                     0x00000008U     /*!<SMBus Type                                    */
-#define  I2C_CR1_ENARP                       0x00000010U     /*!<ARP Enable                                    */
-#define  I2C_CR1_ENPEC                       0x00000020U     /*!<PEC Enable                                    */
-#define  I2C_CR1_ENGC                        0x00000040U     /*!<General Call Enable                           */
-#define  I2C_CR1_NOSTRETCH                   0x00000080U     /*!<Clock Stretching Disable (Slave mode)  */
-#define  I2C_CR1_START                       0x00000100U     /*!<Start Generation                              */
-#define  I2C_CR1_STOP                        0x00000200U     /*!<Stop Generation                               */
-#define  I2C_CR1_ACK                         0x00000400U     /*!<Acknowledge Enable                            */
-#define  I2C_CR1_POS                         0x00000800U     /*!<Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         0x00001000U     /*!<Packet Error Checking                         */
-#define  I2C_CR1_ALERT                       0x00002000U     /*!<SMBus Alert                                   */
-#define  I2C_CR1_SWRST                       0x00008000U     /*!<Software Reset                                */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        0x0000003FU     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
-#define  I2C_CR2_FREQ_0                      0x00000001U     /*!<Bit 0 */
-#define  I2C_CR2_FREQ_1                      0x00000002U     /*!<Bit 1 */
-#define  I2C_CR2_FREQ_2                      0x00000004U     /*!<Bit 2 */
-#define  I2C_CR2_FREQ_3                      0x00000008U     /*!<Bit 3 */
-#define  I2C_CR2_FREQ_4                      0x00000010U     /*!<Bit 4 */
-#define  I2C_CR2_FREQ_5                      0x00000020U     /*!<Bit 5 */
-
-#define  I2C_CR2_ITERREN                     0x00000100U     /*!<Error Interrupt Enable  */
-#define  I2C_CR2_ITEVTEN                     0x00000200U     /*!<Event Interrupt Enable  */
-#define  I2C_CR2_ITBUFEN                     0x00000400U     /*!<Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       0x00000800U     /*!<DMA Requests Enable     */
-#define  I2C_CR2_LAST                        0x00001000U     /*!<DMA Last Transfer       */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     0x000000FEU     /*!<Interface Address */
-#define  I2C_OAR1_ADD8_9                     0x00000300U     /*!<Interface Address */
-
-#define  I2C_OAR1_ADD0                       0x00000001U     /*!<Bit 0 */
-#define  I2C_OAR1_ADD1                       0x00000002U     /*!<Bit 1 */
-#define  I2C_OAR1_ADD2                       0x00000004U     /*!<Bit 2 */
-#define  I2C_OAR1_ADD3                       0x00000008U     /*!<Bit 3 */
-#define  I2C_OAR1_ADD4                       0x00000010U     /*!<Bit 4 */
-#define  I2C_OAR1_ADD5                       0x00000020U     /*!<Bit 5 */
-#define  I2C_OAR1_ADD6                       0x00000040U     /*!<Bit 6 */
-#define  I2C_OAR1_ADD7                       0x00000080U     /*!<Bit 7 */
-#define  I2C_OAR1_ADD8                       0x00000100U     /*!<Bit 8 */
-#define  I2C_OAR1_ADD9                       0x00000200U     /*!<Bit 9 */
-
-#define  I2C_OAR1_ADDMODE                    0x00008000U     /*!<Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     0x00000001U        /*!<Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       0x000000FEU        /*!<Interface address           */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           0x000000FFU        /*!<8-bit Data Register         */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          0x00000001U     /*!<Start Bit (Master mode)                  */
-#define  I2C_SR1_ADDR                        0x00000002U     /*!<Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         0x00000004U     /*!<Byte Transfer Finished                          */
-#define  I2C_SR1_ADD10                       0x00000008U     /*!<10-bit header sent (Master mode)         */
-#define  I2C_SR1_STOPF                       0x00000010U     /*!<Stop detection (Slave mode)              */
-#define  I2C_SR1_RXNE                        0x00000040U     /*!<Data Register not Empty (receivers)      */
-#define  I2C_SR1_TXE                         0x00000080U     /*!<Data Register Empty (transmitters)       */
-#define  I2C_SR1_BERR                        0x00000100U     /*!<Bus Error                                       */
-#define  I2C_SR1_ARLO                        0x00000200U     /*!<Arbitration Lost (master mode)           */
-#define  I2C_SR1_AF                          0x00000400U     /*!<Acknowledge Failure                             */
-#define  I2C_SR1_OVR                         0x00000800U     /*!<Overrun/Underrun                                */
-#define  I2C_SR1_PECERR                      0x00001000U     /*!<PEC Error in reception                          */
-#define  I2C_SR1_TIMEOUT                     0x00004000U     /*!<Timeout or Tlow Error                           */
-#define  I2C_SR1_SMBALERT                    0x00008000U     /*!<SMBus Alert                                     */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         0x00000001U     /*!<Master/Slave                              */
-#define  I2C_SR2_BUSY                        0x00000002U     /*!<Bus Busy                                  */
-#define  I2C_SR2_TRA                         0x00000004U     /*!<Transmitter/Receiver                      */
-#define  I2C_SR2_GENCALL                     0x00000010U     /*!<General Call Address (Slave mode)  */
-#define  I2C_SR2_SMBDEFAULT                  0x00000020U     /*!<SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     0x00000040U     /*!<SMBus Host Header (Slave mode)     */
-#define  I2C_SR2_DUALF                       0x00000080U     /*!<Dual Flag (Slave mode)             */
-#define  I2C_SR2_PEC                         0x0000FF00U     /*!<Packet Error Checking Register            */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         0x00000FFFU     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        0x00004000U     /*!<Fast Mode Duty Cycle                                       */
-#define  I2C_CCR_FS                          0x00008000U     /*!<I2C Master Mode Selection                                  */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     0x0000003FU     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************  Bit definition for I2C_FLTR register  *******************/
-#define  I2C_FLTR_DNF                        0x0000000FU     /*!<Digital Noise Filter */
-#define  I2C_FLTR_ANOFF                      0x00000010U     /*!<Analog Noise Filter OFF */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Independent WATCHDOG                             */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         0x01U               /*!<Watchdog prescaler value update      */
-#define  IWDG_SR_RVU                         0x02U               /*!<Watchdog counter reload value update */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                      LCD-TFT Display Controller (LTDC)                     */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for LTDC_SSCR register  *****************/
-
-#define LTDC_SSCR_VSH                       0x000007FFU              /*!< Vertical Synchronization Height */
-#define LTDC_SSCR_HSW                       0x0FFF0000U              /*!< Horizontal Synchronization Width */
-
-/********************  Bit definition for LTDC_BPCR register  *****************/
-
-#define LTDC_BPCR_AVBP                      0x000007FFU              /*!< Accumulated Vertical Back Porch */
-#define LTDC_BPCR_AHBP                      0x0FFF0000U              /*!< Accumulated Horizontal Back Porch */
-
-/********************  Bit definition for LTDC_AWCR register  *****************/
-
-#define LTDC_AWCR_AAH                       0x000007FFU              /*!< Accumulated Active heigh */
-#define LTDC_AWCR_AAW                       0x0FFF0000U              /*!< Accumulated Active Width */
-
-/********************  Bit definition for LTDC_TWCR register  *****************/
-
-#define LTDC_TWCR_TOTALH                    0x000007FFU              /*!< Total Heigh */
-#define LTDC_TWCR_TOTALW                    0x0FFF0000U              /*!< Total Width */
-
-/********************  Bit definition for LTDC_GCR register  ******************/
-
-#define LTDC_GCR_LTDCEN                     0x00000001U              /*!< LCD-TFT controller enable bit */
-#define LTDC_GCR_DBW                        0x00000070U              /*!< Dither Blue Width */
-#define LTDC_GCR_DGW                        0x00000700U              /*!< Dither Green Width */
-#define LTDC_GCR_DRW                        0x00007000U              /*!< Dither Red Width */
-#define LTDC_GCR_DEN                        0x00010000U              /*!< Dither Enable */
-#define LTDC_GCR_PCPOL                      0x10000000U              /*!< Pixel Clock Polarity */
-#define LTDC_GCR_DEPOL                      0x20000000U              /*!< Data Enable Polarity */
-#define LTDC_GCR_VSPOL                      0x40000000U              /*!< Vertical Synchronization Polarity */
-#define LTDC_GCR_HSPOL                      0x80000000U              /*!< Horizontal Synchronization Polarity */
-
-/* Legacy defines */
-#define LTDC_GCR_DTEN                       LTDC_GCR_DEN
-
-/********************  Bit definition for LTDC_SRCR register  *****************/
-
-#define LTDC_SRCR_IMR                      0x00000001U               /*!< Immediate Reload */
-#define LTDC_SRCR_VBR                      0x00000002U               /*!< Vertical Blanking Reload */
-
-/********************  Bit definition for LTDC_BCCR register  *****************/
-
-#define LTDC_BCCR_BCBLUE                    0x000000FFU              /*!< Background Blue value */
-#define LTDC_BCCR_BCGREEN                   0x0000FF00U              /*!< Background Green value */
-#define LTDC_BCCR_BCRED                     0x00FF0000U              /*!< Background Red value */
-
-/********************  Bit definition for LTDC_IER register  ******************/
-
-#define LTDC_IER_LIE                        0x00000001U              /*!< Line Interrupt Enable */
-#define LTDC_IER_FUIE                       0x00000002U              /*!< FIFO Underrun Interrupt Enable */
-#define LTDC_IER_TERRIE                     0x00000004U              /*!< Transfer Error Interrupt Enable */
-#define LTDC_IER_RRIE                       0x00000008U              /*!< Register Reload interrupt enable */
-
-/********************  Bit definition for LTDC_ISR register  ******************/
-
-#define LTDC_ISR_LIF                        0x00000001U              /*!< Line Interrupt Flag */
-#define LTDC_ISR_FUIF                       0x00000002U              /*!< FIFO Underrun Interrupt Flag */
-#define LTDC_ISR_TERRIF                     0x00000004U              /*!< Transfer Error Interrupt Flag */
-#define LTDC_ISR_RRIF                       0x00000008U              /*!< Register Reload interrupt Flag */
-
-/********************  Bit definition for LTDC_ICR register  ******************/
-
-#define LTDC_ICR_CLIF                       0x00000001U              /*!< Clears the Line Interrupt Flag */
-#define LTDC_ICR_CFUIF                      0x00000002U              /*!< Clears the FIFO Underrun Interrupt Flag */
-#define LTDC_ICR_CTERRIF                    0x00000004U              /*!< Clears the Transfer Error Interrupt Flag */
-#define LTDC_ICR_CRRIF                      0x00000008U              /*!< Clears Register Reload interrupt Flag */
-
-/********************  Bit definition for LTDC_LIPCR register  ****************/
-
-#define LTDC_LIPCR_LIPOS                    0x000007FFU              /*!< Line Interrupt Position */
-
-/********************  Bit definition for LTDC_CPSR register  *****************/
-
-#define LTDC_CPSR_CYPOS                     0x0000FFFFU              /*!< Current Y Position */
-#define LTDC_CPSR_CXPOS                     0xFFFF0000U              /*!< Current X Position */
-
-/********************  Bit definition for LTDC_CDSR register  *****************/
-
-#define LTDC_CDSR_VDES                      0x00000001U              /*!< Vertical Data Enable Status */
-#define LTDC_CDSR_HDES                      0x00000002U              /*!< Horizontal Data Enable Status */
-#define LTDC_CDSR_VSYNCS                    0x00000004U              /*!< Vertical Synchronization Status */
-#define LTDC_CDSR_HSYNCS                    0x00000008U              /*!< Horizontal Synchronization Status */
-
-/********************  Bit definition for LTDC_LxCR register  *****************/
-
-#define LTDC_LxCR_LEN                       0x00000001U              /*!< Layer Enable */
-#define LTDC_LxCR_COLKEN                    0x00000002U              /*!< Color Keying Enable */
-#define LTDC_LxCR_CLUTEN                    0x00000010U              /*!< Color Lockup Table Enable */
-
-/********************  Bit definition for LTDC_LxWHPCR register  **************/
-
-#define LTDC_LxWHPCR_WHSTPOS                0x00000FFFU              /*!< Window Horizontal Start Position */
-#define LTDC_LxWHPCR_WHSPPOS                0xFFFF0000U              /*!< Window Horizontal Stop Position */
-
-/********************  Bit definition for LTDC_LxWVPCR register  **************/
-
-#define LTDC_LxWVPCR_WVSTPOS                0x00000FFFU              /*!< Window Vertical Start Position */
-#define LTDC_LxWVPCR_WVSPPOS                0xFFFF0000U              /*!< Window Vertical Stop Position */
-
-/********************  Bit definition for LTDC_LxCKCR register  ***************/
-
-#define LTDC_LxCKCR_CKBLUE                  0x000000FFU              /*!< Color Key Blue value */
-#define LTDC_LxCKCR_CKGREEN                 0x0000FF00U              /*!< Color Key Green value */
-#define LTDC_LxCKCR_CKRED                   0x00FF0000U              /*!< Color Key Red value */
-
-/********************  Bit definition for LTDC_LxPFCR register  ***************/
-
-#define LTDC_LxPFCR_PF                      0x00000007U              /*!< Pixel Format */
-
-/********************  Bit definition for LTDC_LxCACR register  ***************/
-
-#define LTDC_LxCACR_CONSTA                  0x000000FFU              /*!< Constant Alpha */
-
-/********************  Bit definition for LTDC_LxDCCR register  ***************/
-
-#define LTDC_LxDCCR_DCBLUE                  0x000000FFU              /*!< Default Color Blue */
-#define LTDC_LxDCCR_DCGREEN                 0x0000FF00U              /*!< Default Color Green */
-#define LTDC_LxDCCR_DCRED                   0x00FF0000U              /*!< Default Color Red */
-#define LTDC_LxDCCR_DCALPHA                 0xFF000000U              /*!< Default Color Alpha */
-                                
-/********************  Bit definition for LTDC_LxBFCR register  ***************/
-
-#define LTDC_LxBFCR_BF2                     0x00000007U              /*!< Blending Factor 2 */
-#define LTDC_LxBFCR_BF1                     0x00000700U              /*!< Blending Factor 1 */
-
-/********************  Bit definition for LTDC_LxCFBAR register  **************/
-
-#define LTDC_LxCFBAR_CFBADD                 0xFFFFFFFFU              /*!< Color Frame Buffer Start Address */
-
-/********************  Bit definition for LTDC_LxCFBLR register  **************/
-
-#define LTDC_LxCFBLR_CFBLL                  0x00001FFFU              /*!< Color Frame Buffer Line Length */
-#define LTDC_LxCFBLR_CFBP                   0x1FFF0000U              /*!< Color Frame Buffer Pitch in bytes */
-
-/********************  Bit definition for LTDC_LxCFBLNR register  *************/
-
-#define LTDC_LxCFBLNR_CFBLNBR               0x000007FFU              /*!< Frame Buffer Line Number */
-
-/********************  Bit definition for LTDC_LxCLUTWR register  *************/
-
-#define LTDC_LxCLUTWR_BLUE                  0x000000FFU              /*!< Blue value */
-#define LTDC_LxCLUTWR_GREEN                 0x0000FF00U              /*!< Green value */
-#define LTDC_LxCLUTWR_RED                   0x00FF0000U              /*!< Red value */
-#define LTDC_LxCLUTWR_CLUTADD               0xFF000000U              /*!< CLUT address */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                             Power Control                                  */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
-#define  PWR_CR_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
-#define  PWR_CR_CWUF                         0x00000004U     /*!< Clear Wakeup Flag                   */
-#define  PWR_CR_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
-#define  PWR_CR_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
-
-#define  PWR_CR_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        0x00000020U     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        0x00000040U     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        0x00000080U     /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
-#define  PWR_CR_DBP                          0x00000100U     /*!< Disable Backup Domain write protection                     */
-#define  PWR_CR_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                              */
-#define  PWR_CR_LPLVDS                       0x00000400U     /*!< Low-Power Regulator Low Voltage Scaling in Stop mode       */
-#define  PWR_CR_MRLVDS                       0x00000800U     /*!< Main regulator Low Voltage Scaling in Stop mode            */
-#define  PWR_CR_ADCDC1                       0x00002000U     /*!< Refer to AN4073 on how to use this bit */ 
-#define  PWR_CR_VOS                          0x0000C000U     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
-#define  PWR_CR_VOS_0                        0x00004000U     /*!< Bit 0 */
-#define  PWR_CR_VOS_1                        0x00008000U     /*!< Bit 1 */
-#define  PWR_CR_ODEN                         0x00010000U     /*!< Over Drive enable                   */
-#define  PWR_CR_ODSWEN                       0x00020000U     /*!< Over Drive switch enabled           */
-#define  PWR_CR_UDEN                         0x000C0000U     /*!< Under Drive enable in stop mode     */
-#define  PWR_CR_UDEN_0                       0x00040000U     /*!< Bit 0                               */
-#define  PWR_CR_UDEN_1                       0x00080000U     /*!< Bit 1                               */
-
-/* Legacy define */
-#define  PWR_CR_PMODE                        PWR_CR_VOS
-#define  PWR_CR_LPUDS                        PWR_CR_LPLVDS     /*!< Low-Power Regulator in deepsleep under-drive mode          */
-#define  PWR_CR_MRUDS                        PWR_CR_MRLVDS     /*!< Main regulator in deepsleep under-drive mode               */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         0x00000001U     /*!< Wakeup Flag                                      */
-#define  PWR_CSR_SBF                         0x00000002U     /*!< Standby Flag                                     */
-#define  PWR_CSR_PVDO                        0x00000004U     /*!< PVD Output                                       */
-#define  PWR_CSR_BRR                         0x00000008U     /*!< Backup regulator ready                           */
-#define  PWR_CSR_EWUP                        0x00000100U     /*!< Enable WKUP pin                                  */
-#define  PWR_CSR_BRE                         0x00000200U     /*!< Backup regulator enable                          */
-#define  PWR_CSR_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
-#define  PWR_CSR_ODRDY                       0x00010000U     /*!< Over Drive generator ready                       */
-#define  PWR_CSR_ODSWRDY                     0x00020000U     /*!< Over Drive Switch ready                          */
-#define  PWR_CSR_UDSWRDY                     0x000C0000U     /*!< Under Drive ready                                */
-
-/* Legacy define */
-#define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        0x00000001U
-#define  RCC_CR_HSIRDY                       0x00000002U
-
-#define  RCC_CR_HSITRIM                      0x000000F8U
-#define  RCC_CR_HSITRIM_0                    0x00000008U/*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    0x00000010U/*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    0x00000020U/*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    0x00000040U/*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    0x00000080U/*!<Bit 4 */
-
-#define  RCC_CR_HSICAL                       0x0000FF00U
-#define  RCC_CR_HSICAL_0                     0x00000100U/*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     0x00000200U/*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     0x00000400U/*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     0x00000800U/*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     0x00001000U/*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     0x00002000U/*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     0x00004000U/*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     0x00008000U/*!<Bit 7 */
-
-#define  RCC_CR_HSEON                        0x00010000U
-#define  RCC_CR_HSERDY                       0x00020000U
-#define  RCC_CR_HSEBYP                       0x00040000U
-#define  RCC_CR_CSSON                        0x00080000U
-#define  RCC_CR_PLLON                        0x01000000U
-#define  RCC_CR_PLLRDY                       0x02000000U
-#define  RCC_CR_PLLI2SON                     0x04000000U
-#define  RCC_CR_PLLI2SRDY                    0x08000000U
-#define  RCC_CR_PLLSAION                     0x10000000U
-#define  RCC_CR_PLLSAIRDY                    0x20000000U
-
-/********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    0x0000003FU
-#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
-#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
-#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
-#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
-#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
-#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
-
-#define  RCC_PLLCFGR_PLLN                     0x00007FC0U
-#define  RCC_PLLCFGR_PLLN_0                   0x00000040U
-#define  RCC_PLLCFGR_PLLN_1                   0x00000080U
-#define  RCC_PLLCFGR_PLLN_2                   0x00000100U
-#define  RCC_PLLCFGR_PLLN_3                   0x00000200U
-#define  RCC_PLLCFGR_PLLN_4                   0x00000400U
-#define  RCC_PLLCFGR_PLLN_5                   0x00000800U
-#define  RCC_PLLCFGR_PLLN_6                   0x00001000U
-#define  RCC_PLLCFGR_PLLN_7                   0x00002000U
-#define  RCC_PLLCFGR_PLLN_8                   0x00004000U
-
-#define  RCC_PLLCFGR_PLLP                    0x00030000U
-#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
-#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
-
-#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
-
-#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
-#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
-#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
-#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
-#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-/*!< SW configuration */
-#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
-
-#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
-
-#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
-
-#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
-
-/*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     0x001F0000U
-#define  RCC_CFGR_RTCPRE_0                   0x00010000U
-#define  RCC_CFGR_RTCPRE_1                   0x00020000U
-#define  RCC_CFGR_RTCPRE_2                   0x00040000U
-#define  RCC_CFGR_RTCPRE_3                   0x00080000U
-#define  RCC_CFGR_RTCPRE_4                   0x00100000U
-
-/*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       0x00600000U
-#define  RCC_CFGR_MCO1_0                     0x00200000U
-#define  RCC_CFGR_MCO1_1                     0x00400000U
-
-#define  RCC_CFGR_I2SSRC                     0x00800000U
-
-#define  RCC_CFGR_MCO1PRE                    0x07000000U
-#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
-#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
-#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
-
-#define  RCC_CFGR_MCO2PRE                    0x38000000U
-#define  RCC_CFGR_MCO2PRE_0                  0x08000000U
-#define  RCC_CFGR_MCO2PRE_1                  0x10000000U
-#define  RCC_CFGR_MCO2PRE_2                  0x20000000U
-
-#define  RCC_CFGR_MCO2                       0xC0000000U
-#define  RCC_CFGR_MCO2_0                     0x40000000U
-#define  RCC_CFGR_MCO2_1                     0x80000000U
-
-/********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     0x00000001U
-#define  RCC_CIR_LSERDYF                     0x00000002U
-#define  RCC_CIR_HSIRDYF                     0x00000004U
-#define  RCC_CIR_HSERDYF                     0x00000008U
-#define  RCC_CIR_PLLRDYF                     0x00000010U
-#define  RCC_CIR_PLLI2SRDYF                  0x00000020U
-#define  RCC_CIR_PLLSAIRDYF                  0x00000040U
-#define  RCC_CIR_CSSF                        0x00000080U
-#define  RCC_CIR_LSIRDYIE                    0x00000100U
-#define  RCC_CIR_LSERDYIE                    0x00000200U
-#define  RCC_CIR_HSIRDYIE                    0x00000400U
-#define  RCC_CIR_HSERDYIE                    0x00000800U
-#define  RCC_CIR_PLLRDYIE                    0x00001000U
-#define  RCC_CIR_PLLI2SRDYIE                 0x00002000U
-#define  RCC_CIR_PLLSAIRDYIE                 0x00004000U
-#define  RCC_CIR_LSIRDYC                     0x00010000U
-#define  RCC_CIR_LSERDYC                     0x00020000U
-#define  RCC_CIR_HSIRDYC                     0x00040000U
-#define  RCC_CIR_HSERDYC                     0x00080000U
-#define  RCC_CIR_PLLRDYC                     0x00100000U
-#define  RCC_CIR_PLLI2SRDYC                  0x00200000U
-#define  RCC_CIR_PLLSAIRDYC                  0x00400000U
-#define  RCC_CIR_CSSC                        0x00800000U
-
-/********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
-#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
-#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
-#define  RCC_AHB1RSTR_GPIODRST               0x00000008U
-#define  RCC_AHB1RSTR_GPIOERST               0x00000010U
-#define  RCC_AHB1RSTR_GPIOFRST               0x00000020U
-#define  RCC_AHB1RSTR_GPIOGRST               0x00000040U
-#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
-#define  RCC_AHB1RSTR_GPIOIRST               0x00000100U
-#define  RCC_AHB1RSTR_GPIOJRST               0x00000200U
-#define  RCC_AHB1RSTR_GPIOKRST               0x00000400U
-#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
-#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
-#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
-#define  RCC_AHB1RSTR_DMA2DRST               0x00800000U
-#define  RCC_AHB1RSTR_ETHMACRST              0x02000000U
-#define  RCC_AHB1RSTR_OTGHRST                0x20000000U
-
-/********************  Bit definition for RCC_AHB2RSTR register  **************/
-#define  RCC_AHB2RSTR_DCMIRST                0x00000001U
-#define  RCC_AHB2RSTR_CRYPRST                0x00000010U
-#define  RCC_AHB2RSTR_HASHRST                0x00000020U
- /* maintained for legacy purpose */
- #define  RCC_AHB2RSTR_HSAHRST                RCC_AHB2RSTR_HASHRST
-#define  RCC_AHB2RSTR_RNGRST                 0x00000040U
-#define  RCC_AHB2RSTR_OTGFSRST               0x00000080U
-
-/********************  Bit definition for RCC_AHB3RSTR register  **************/
-#define  RCC_AHB3RSTR_FMCRST                0x00000001U
-
-/********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM2RST                0x00000001U
-#define  RCC_APB1RSTR_TIM3RST                0x00000002U
-#define  RCC_APB1RSTR_TIM4RST                0x00000004U
-#define  RCC_APB1RSTR_TIM5RST                0x00000008U
-#define  RCC_APB1RSTR_TIM6RST                0x00000010U
-#define  RCC_APB1RSTR_TIM7RST                0x00000020U
-#define  RCC_APB1RSTR_TIM12RST               0x00000040U
-#define  RCC_APB1RSTR_TIM13RST               0x00000080U
-#define  RCC_APB1RSTR_TIM14RST               0x00000100U
-#define  RCC_APB1RSTR_WWDGRST                0x00000800U
-#define  RCC_APB1RSTR_SPI2RST                0x00004000U
-#define  RCC_APB1RSTR_SPI3RST                0x00008000U
-#define  RCC_APB1RSTR_USART2RST              0x00020000U
-#define  RCC_APB1RSTR_USART3RST              0x00040000U
-#define  RCC_APB1RSTR_UART4RST               0x00080000U
-#define  RCC_APB1RSTR_UART5RST               0x00100000U
-#define  RCC_APB1RSTR_I2C1RST                0x00200000U
-#define  RCC_APB1RSTR_I2C2RST                0x00400000U
-#define  RCC_APB1RSTR_I2C3RST                0x00800000U
-#define  RCC_APB1RSTR_CAN1RST                0x02000000U
-#define  RCC_APB1RSTR_CAN2RST                0x04000000U
-#define  RCC_APB1RSTR_PWRRST                 0x10000000U
-#define  RCC_APB1RSTR_DACRST                 0x20000000U
-#define  RCC_APB1RSTR_UART7RST               0x40000000U
-#define  RCC_APB1RSTR_UART8RST               0x80000000U
-
-/********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                0x00000001U
-#define  RCC_APB2RSTR_TIM8RST                0x00000002U
-#define  RCC_APB2RSTR_USART1RST              0x00000010U
-#define  RCC_APB2RSTR_USART6RST              0x00000020U
-#define  RCC_APB2RSTR_ADCRST                 0x00000100U
-#define  RCC_APB2RSTR_SDIORST                0x00000800U
-#define  RCC_APB2RSTR_SPI1RST                0x00001000U
-#define  RCC_APB2RSTR_SPI4RST                0x00002000U
-#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
-#define  RCC_APB2RSTR_TIM9RST                0x00010000U
-#define  RCC_APB2RSTR_TIM10RST               0x00020000U
-#define  RCC_APB2RSTR_TIM11RST               0x00040000U
-#define  RCC_APB2RSTR_SPI5RST                0x00100000U
-#define  RCC_APB2RSTR_SPI6RST                0x00200000U
-#define  RCC_APB2RSTR_SAI1RST                0x00400000U
-#define  RCC_APB2RSTR_LTDCRST                0x04000000U
-
-/* Old SPI1RST bit definition, maintained for legacy purpose */
-#define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
-
-/********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
-#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
-#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
-#define  RCC_AHB1ENR_GPIODEN                 0x00000008U
-#define  RCC_AHB1ENR_GPIOEEN                 0x00000010U
-#define  RCC_AHB1ENR_GPIOFEN                 0x00000020U
-#define  RCC_AHB1ENR_GPIOGEN                 0x00000040U
-#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
-#define  RCC_AHB1ENR_GPIOIEN                 0x00000100U
-#define  RCC_AHB1ENR_GPIOJEN                 0x00000200U
-#define  RCC_AHB1ENR_GPIOKEN                 0x00000400U
-
-#define  RCC_AHB1ENR_CRCEN                   0x00001000U
-#define  RCC_AHB1ENR_BKPSRAMEN               0x00040000U
-#define  RCC_AHB1ENR_CCMDATARAMEN            0x00100000U
-#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
-#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
-#define  RCC_AHB1ENR_DMA2DEN                 0x00800000U
-
-#define  RCC_AHB1ENR_ETHMACEN                0x02000000U
-#define  RCC_AHB1ENR_ETHMACTXEN              0x04000000U
-#define  RCC_AHB1ENR_ETHMACRXEN              0x08000000U
-#define  RCC_AHB1ENR_ETHMACPTPEN             0x10000000U
-#define  RCC_AHB1ENR_OTGHSEN                 0x20000000U
-#define  RCC_AHB1ENR_OTGHSULPIEN             0x40000000U
-
-/********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define  RCC_AHB2ENR_DCMIEN                  0x00000001U
-#define  RCC_AHB2ENR_CRYPEN                  0x00000010U
-#define  RCC_AHB2ENR_HASHEN                  0x00000020U
-#define  RCC_AHB2ENR_RNGEN                   0x00000040U
-#define  RCC_AHB2ENR_OTGFSEN                 0x00000080U
-
-/********************  Bit definition for RCC_AHB3ENR register  ***************/
-#define  RCC_AHB3ENR_FMCEN                  0x00000001U
-
-/********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM2EN                  0x00000001U
-#define  RCC_APB1ENR_TIM3EN                  0x00000002U
-#define  RCC_APB1ENR_TIM4EN                  0x00000004U
-#define  RCC_APB1ENR_TIM5EN                  0x00000008U
-#define  RCC_APB1ENR_TIM6EN                  0x00000010U
-#define  RCC_APB1ENR_TIM7EN                  0x00000020U
-#define  RCC_APB1ENR_TIM12EN                 0x00000040U
-#define  RCC_APB1ENR_TIM13EN                 0x00000080U
-#define  RCC_APB1ENR_TIM14EN                 0x00000100U
-#define  RCC_APB1ENR_WWDGEN                  0x00000800U
-#define  RCC_APB1ENR_SPI2EN                  0x00004000U
-#define  RCC_APB1ENR_SPI3EN                  0x00008000U
-#define  RCC_APB1ENR_USART2EN                0x00020000U
-#define  RCC_APB1ENR_USART3EN                0x00040000U
-#define  RCC_APB1ENR_UART4EN                 0x00080000U
-#define  RCC_APB1ENR_UART5EN                 0x00100000U
-#define  RCC_APB1ENR_I2C1EN                  0x00200000U
-#define  RCC_APB1ENR_I2C2EN                  0x00400000U
-#define  RCC_APB1ENR_I2C3EN                  0x00800000U
-#define  RCC_APB1ENR_CAN1EN                  0x02000000U
-#define  RCC_APB1ENR_CAN2EN                  0x04000000U
-#define  RCC_APB1ENR_PWREN                   0x10000000U
-#define  RCC_APB1ENR_DACEN                   0x20000000U
-#define  RCC_APB1ENR_UART7EN                 0x40000000U
-#define  RCC_APB1ENR_UART8EN                 0x80000000U
-
-/********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  0x00000001U
-#define  RCC_APB2ENR_TIM8EN                  0x00000002U
-#define  RCC_APB2ENR_USART1EN                0x00000010U
-#define  RCC_APB2ENR_USART6EN                0x00000020U
-#define  RCC_APB2ENR_ADC1EN                  0x00000100U
-#define  RCC_APB2ENR_ADC2EN                  0x00000200U
-#define  RCC_APB2ENR_ADC3EN                  0x00000400U
-#define  RCC_APB2ENR_SDIOEN                  0x00000800U
-#define  RCC_APB2ENR_SPI1EN                  0x00001000U
-#define  RCC_APB2ENR_SPI4EN                  0x00002000U
-#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
-#define  RCC_APB2ENR_TIM9EN                  0x00010000U
-#define  RCC_APB2ENR_TIM10EN                 0x00020000U
-#define  RCC_APB2ENR_TIM11EN                 0x00040000U
-#define  RCC_APB2ENR_SPI5EN                  0x00100000U
-#define  RCC_APB2ENR_SPI6EN                  0x00200000U
-#define  RCC_APB2ENR_SAI1EN                  0x00400000U
-#define  RCC_APB2ENR_LTDCEN                  0x04000000U
-
-/********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
-#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
-#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
-#define  RCC_AHB1LPENR_GPIODLPEN             0x00000008U
-#define  RCC_AHB1LPENR_GPIOELPEN             0x00000010U
-#define  RCC_AHB1LPENR_GPIOFLPEN             0x00000020U
-#define  RCC_AHB1LPENR_GPIOGLPEN             0x00000040U
-#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
-#define  RCC_AHB1LPENR_GPIOILPEN             0x00000100U
-#define  RCC_AHB1LPENR_GPIOJLPEN             0x00000200U
-#define  RCC_AHB1LPENR_GPIOKLPEN             0x00000400U
-
-#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
-#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
-#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
-#define  RCC_AHB1LPENR_SRAM2LPEN             0x00020000U
-#define  RCC_AHB1LPENR_BKPSRAMLPEN           0x00040000U
-#define  RCC_AHB1LPENR_SRAM3LPEN             0x00080000U
-#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
-#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
-#define  RCC_AHB1LPENR_DMA2DLPEN             0x00800000U
-
-#define  RCC_AHB1LPENR_ETHMACLPEN            0x02000000U
-#define  RCC_AHB1LPENR_ETHMACTXLPEN          0x04000000U
-#define  RCC_AHB1LPENR_ETHMACRXLPEN          0x08000000U
-#define  RCC_AHB1LPENR_ETHMACPTPLPEN         0x10000000U
-#define  RCC_AHB1LPENR_OTGHSLPEN             0x20000000U
-#define  RCC_AHB1LPENR_OTGHSULPILPEN         0x40000000U
-
-/********************  Bit definition for RCC_AHB2LPENR register  *************/
-#define  RCC_AHB2LPENR_DCMILPEN              0x00000001U
-#define  RCC_AHB2LPENR_CRYPLPEN              0x00000010U
-#define  RCC_AHB2LPENR_HASHLPEN              0x00000020U
-#define  RCC_AHB2LPENR_RNGLPEN               0x00000040U
-#define  RCC_AHB2LPENR_OTGFSLPEN             0x00000080U
-
-/********************  Bit definition for RCC_AHB3LPENR register  *************/
-#define  RCC_AHB3LPENR_FMCLPEN              0x00000001U
-
-/********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM2LPEN              0x00000001U
-#define  RCC_APB1LPENR_TIM3LPEN              0x00000002U
-#define  RCC_APB1LPENR_TIM4LPEN              0x00000004U
-#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
-#define  RCC_APB1LPENR_TIM6LPEN              0x00000010U
-#define  RCC_APB1LPENR_TIM7LPEN              0x00000020U
-#define  RCC_APB1LPENR_TIM12LPEN             0x00000040U
-#define  RCC_APB1LPENR_TIM13LPEN             0x00000080U
-#define  RCC_APB1LPENR_TIM14LPEN             0x00000100U
-#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
-#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U
-#define  RCC_APB1LPENR_SPI3LPEN              0x00008000U
-#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
-#define  RCC_APB1LPENR_USART3LPEN            0x00040000U
-#define  RCC_APB1LPENR_UART4LPEN             0x00080000U
-#define  RCC_APB1LPENR_UART5LPEN             0x00100000U
-#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
-#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
-#define  RCC_APB1LPENR_I2C3LPEN              0x00800000U
-#define  RCC_APB1LPENR_CAN1LPEN              0x02000000U
-#define  RCC_APB1LPENR_CAN2LPEN              0x04000000U
-#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
-#define  RCC_APB1LPENR_DACLPEN               0x20000000U
-#define  RCC_APB1LPENR_UART7LPEN             0x40000000U
-#define  RCC_APB1LPENR_UART8LPEN             0x80000000U
-
-/********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
-#define  RCC_APB2LPENR_TIM8LPEN              0x00000002U
-#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
-#define  RCC_APB2LPENR_USART6LPEN            0x00000020U
-#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
-#define  RCC_APB2LPENR_ADC2LPEN              0x00000200U
-#define  RCC_APB2LPENR_ADC3LPEN              0x00000400U
-#define  RCC_APB2LPENR_SDIOLPEN              0x00000800U
-#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
-#define  RCC_APB2LPENR_SPI4LPEN              0x00002000U
-#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
-#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
-#define  RCC_APB2LPENR_TIM10LPEN             0x00020000U
-#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
-#define  RCC_APB2LPENR_SPI5LPEN              0x00100000U
-#define  RCC_APB2LPENR_SPI6LPEN              0x00200000U
-#define  RCC_APB2LPENR_SAI1LPEN              0x00400000U
-#define  RCC_APB2LPENR_LTDCLPEN              0x04000000U
-
-/********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      0x00000001U
-#define  RCC_BDCR_LSERDY                     0x00000002U
-#define  RCC_BDCR_LSEBYP                     0x00000004U
-
-#define  RCC_BDCR_RTCSEL                    0x00000300U
-#define  RCC_BDCR_RTCSEL_0                  0x00000100U
-#define  RCC_BDCR_RTCSEL_1                  0x00000200U
-
-#define  RCC_BDCR_RTCEN                      0x00008000U
-#define  RCC_BDCR_BDRST                      0x00010000U
-
-/********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       0x00000001U
-#define  RCC_CSR_LSIRDY                      0x00000002U
-#define  RCC_CSR_RMVF                        0x01000000U
-#define  RCC_CSR_BORRSTF                     0x02000000U
-#define  RCC_CSR_PADRSTF                     0x04000000U
-#define  RCC_CSR_PORRSTF                     0x08000000U
-#define  RCC_CSR_SFTRSTF                     0x10000000U
-#define  RCC_CSR_WDGRSTF                     0x20000000U
-#define  RCC_CSR_WWDGRSTF                    0x40000000U
-#define  RCC_CSR_LPWRRSTF                    0x80000000U
-
-/********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    0x00001FFFU
-#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
-#define  RCC_SSCGR_SPREADSEL                 0x40000000U
-#define  RCC_SSCGR_SSCGEN                    0x80000000U
-
-/********************  Bit definition for RCC_PLLI2SCFGR register  ************/
-#define  RCC_PLLI2SCFGR_PLLI2SN              0x00007FC0U
-#define  RCC_PLLI2SCFGR_PLLI2SN_0            0x00000040U
-#define  RCC_PLLI2SCFGR_PLLI2SN_1            0x00000080U
-#define  RCC_PLLI2SCFGR_PLLI2SN_2            0x00000100U
-#define  RCC_PLLI2SCFGR_PLLI2SN_3            0x00000200U
-#define  RCC_PLLI2SCFGR_PLLI2SN_4            0x00000400U
-#define  RCC_PLLI2SCFGR_PLLI2SN_5            0x00000800U
-#define  RCC_PLLI2SCFGR_PLLI2SN_6            0x00001000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_7            0x00002000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_8            0x00004000U
-
-#define  RCC_PLLI2SCFGR_PLLI2SQ              0x0F000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_0            0x01000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_1            0x02000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_2            0x04000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_3            0x08000000U
-
-#define  RCC_PLLI2SCFGR_PLLI2SR              0x70000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_0            0x10000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_1            0x20000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_2            0x40000000U
-
-
-/********************  Bit definition for RCC_PLLSAICFGR register  ************/
-#define  RCC_PLLSAICFGR_PLLSAIN              0x00007FC0U
-#define  RCC_PLLSAICFGR_PLLSAIN_0            0x00000040U
-#define  RCC_PLLSAICFGR_PLLSAIN_1            0x00000080U
-#define  RCC_PLLSAICFGR_PLLSAIN_2            0x00000100U
-#define  RCC_PLLSAICFGR_PLLSAIN_3            0x00000200U
-#define  RCC_PLLSAICFGR_PLLSAIN_4            0x00000400U
-#define  RCC_PLLSAICFGR_PLLSAIN_5            0x00000800U
-#define  RCC_PLLSAICFGR_PLLSAIN_6            0x00001000U
-#define  RCC_PLLSAICFGR_PLLSAIN_7            0x00002000U
-#define  RCC_PLLSAICFGR_PLLSAIN_8            0x00004000U
-
-#define  RCC_PLLSAICFGR_PLLSAIQ              0x0F000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_0            0x01000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_1            0x02000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_2            0x04000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_3            0x08000000U
-
-#define  RCC_PLLSAICFGR_PLLSAIR              0x70000000U
-#define  RCC_PLLSAICFGR_PLLSAIR_0            0x10000000U
-#define  RCC_PLLSAICFGR_PLLSAIR_1            0x20000000U
-#define  RCC_PLLSAICFGR_PLLSAIR_2            0x40000000U
-
-/********************  Bit definition for RCC_DCKCFGR register  ***************/
-#define  RCC_DCKCFGR_PLLI2SDIVQ              0x0000001FU
-#define  RCC_DCKCFGR_PLLSAIDIVQ              0x00001F00U
-#define  RCC_DCKCFGR_PLLSAIDIVR              0x00030000U
-#define  RCC_DCKCFGR_SAI1ASRC                0x00300000U
-#define  RCC_DCKCFGR_SAI1ASRC_0              0x00100000U
-#define  RCC_DCKCFGR_SAI1ASRC_1              0x00200000U
-#define  RCC_DCKCFGR_SAI1BSRC                0x00C00000U
-#define  RCC_DCKCFGR_SAI1BSRC_0              0x00400000U
-#define  RCC_DCKCFGR_SAI1BSRC_1              0x00800000U
-#define  RCC_DCKCFGR_TIMPRE                  0x01000000U
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    RNG                                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN                         0x00000004U
-#define RNG_CR_IE                            0x00000008U
-
-/********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY                          0x00000001U
-#define RNG_SR_CECS                          0x00000002U
-#define RNG_SR_SECS                          0x00000004U
-#define RNG_SR_CEIS                          0x00000020U
-#define RNG_SR_SEIS                          0x00000040U
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            0x00400000U
-#define RTC_TR_HT                            0x00300000U
-#define RTC_TR_HT_0                          0x00100000U
-#define RTC_TR_HT_1                          0x00200000U
-#define RTC_TR_HU                            0x000F0000U
-#define RTC_TR_HU_0                          0x00010000U
-#define RTC_TR_HU_1                          0x00020000U
-#define RTC_TR_HU_2                          0x00040000U
-#define RTC_TR_HU_3                          0x00080000U
-#define RTC_TR_MNT                           0x00007000U
-#define RTC_TR_MNT_0                         0x00001000U
-#define RTC_TR_MNT_1                         0x00002000U
-#define RTC_TR_MNT_2                         0x00004000U
-#define RTC_TR_MNU                           0x00000F00U
-#define RTC_TR_MNU_0                         0x00000100U
-#define RTC_TR_MNU_1                         0x00000200U
-#define RTC_TR_MNU_2                         0x00000400U
-#define RTC_TR_MNU_3                         0x00000800U
-#define RTC_TR_ST                            0x00000070U
-#define RTC_TR_ST_0                          0x00000010U
-#define RTC_TR_ST_1                          0x00000020U
-#define RTC_TR_ST_2                          0x00000040U
-#define RTC_TR_SU                            0x0000000FU
-#define RTC_TR_SU_0                          0x00000001U
-#define RTC_TR_SU_1                          0x00000002U
-#define RTC_TR_SU_2                          0x00000004U
-#define RTC_TR_SU_3                          0x00000008U
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            0x00F00000U
-#define RTC_DR_YT_0                          0x00100000U
-#define RTC_DR_YT_1                          0x00200000U
-#define RTC_DR_YT_2                          0x00400000U
-#define RTC_DR_YT_3                          0x00800000U
-#define RTC_DR_YU                            0x000F0000U
-#define RTC_DR_YU_0                          0x00010000U
-#define RTC_DR_YU_1                          0x00020000U
-#define RTC_DR_YU_2                          0x00040000U
-#define RTC_DR_YU_3                          0x00080000U
-#define RTC_DR_WDU                           0x0000E000U
-#define RTC_DR_WDU_0                         0x00002000U
-#define RTC_DR_WDU_1                         0x00004000U
-#define RTC_DR_WDU_2                         0x00008000U
-#define RTC_DR_MT                            0x00001000U
-#define RTC_DR_MU                            0x00000F00U
-#define RTC_DR_MU_0                          0x00000100U
-#define RTC_DR_MU_1                          0x00000200U
-#define RTC_DR_MU_2                          0x00000400U
-#define RTC_DR_MU_3                          0x00000800U
-#define RTC_DR_DT                            0x00000030U
-#define RTC_DR_DT_0                          0x00000010U
-#define RTC_DR_DT_1                          0x00000020U
-#define RTC_DR_DU                            0x0000000FU
-#define RTC_DR_DU_0                          0x00000001U
-#define RTC_DR_DU_1                          0x00000002U
-#define RTC_DR_DU_2                          0x00000004U
-#define RTC_DR_DU_3                          0x00000008U
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           0x00800000U
-#define RTC_CR_OSEL                          0x00600000U
-#define RTC_CR_OSEL_0                        0x00200000U
-#define RTC_CR_OSEL_1                        0x00400000U
-#define RTC_CR_POL                           0x00100000U
-#define RTC_CR_COSEL                         0x00080000U
-#define RTC_CR_BCK                           0x00040000U
-#define RTC_CR_SUB1H                         0x00020000U
-#define RTC_CR_ADD1H                         0x00010000U
-#define RTC_CR_TSIE                          0x00008000U
-#define RTC_CR_WUTIE                         0x00004000U
-#define RTC_CR_ALRBIE                        0x00002000U
-#define RTC_CR_ALRAIE                        0x00001000U
-#define RTC_CR_TSE                           0x00000800U
-#define RTC_CR_WUTE                          0x00000400U
-#define RTC_CR_ALRBE                         0x00000200U
-#define RTC_CR_ALRAE                         0x00000100U
-#define RTC_CR_DCE                           0x00000080U
-#define RTC_CR_FMT                           0x00000040U
-#define RTC_CR_BYPSHAD                       0x00000020U
-#define RTC_CR_REFCKON                       0x00000010U
-#define RTC_CR_TSEDGE                        0x00000008U
-#define RTC_CR_WUCKSEL                       0x00000007U
-#define RTC_CR_WUCKSEL_0                     0x00000001U
-#define RTC_CR_WUCKSEL_1                     0x00000002U
-#define RTC_CR_WUCKSEL_2                     0x00000004U
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      0x00010000U
-#define RTC_ISR_TAMP1F                       0x00002000U
-#define RTC_ISR_TAMP2F                       0x00004000U
-#define RTC_ISR_TSOVF                        0x00001000U
-#define RTC_ISR_TSF                          0x00000800U
-#define RTC_ISR_WUTF                         0x00000400U
-#define RTC_ISR_ALRBF                        0x00000200U
-#define RTC_ISR_ALRAF                        0x00000100U
-#define RTC_ISR_INIT                         0x00000080U
-#define RTC_ISR_INITF                        0x00000040U
-#define RTC_ISR_RSF                          0x00000020U
-#define RTC_ISR_INITS                        0x00000010U
-#define RTC_ISR_SHPF                         0x00000008U
-#define RTC_ISR_WUTWF                        0x00000004U
-#define RTC_ISR_ALRBWF                       0x00000002U
-#define RTC_ISR_ALRAWF                       0x00000001U
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    0x007F0000U
-#define RTC_PRER_PREDIV_S                    0x00007FFFU
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS                       0x00000080U
-#define RTC_CALIBR_DC                        0x0000001FU
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      0x80000000U
-#define RTC_ALRMAR_WDSEL                     0x40000000U
-#define RTC_ALRMAR_DT                        0x30000000U
-#define RTC_ALRMAR_DT_0                      0x10000000U
-#define RTC_ALRMAR_DT_1                      0x20000000U
-#define RTC_ALRMAR_DU                        0x0F000000U
-#define RTC_ALRMAR_DU_0                      0x01000000U
-#define RTC_ALRMAR_DU_1                      0x02000000U
-#define RTC_ALRMAR_DU_2                      0x04000000U
-#define RTC_ALRMAR_DU_3                      0x08000000U
-#define RTC_ALRMAR_MSK3                      0x00800000U
-#define RTC_ALRMAR_PM                        0x00400000U
-#define RTC_ALRMAR_HT                        0x00300000U
-#define RTC_ALRMAR_HT_0                      0x00100000U
-#define RTC_ALRMAR_HT_1                      0x00200000U
-#define RTC_ALRMAR_HU                        0x000F0000U
-#define RTC_ALRMAR_HU_0                      0x00010000U
-#define RTC_ALRMAR_HU_1                      0x00020000U
-#define RTC_ALRMAR_HU_2                      0x00040000U
-#define RTC_ALRMAR_HU_3                      0x00080000U
-#define RTC_ALRMAR_MSK2                      0x00008000U
-#define RTC_ALRMAR_MNT                       0x00007000U
-#define RTC_ALRMAR_MNT_0                     0x00001000U
-#define RTC_ALRMAR_MNT_1                     0x00002000U
-#define RTC_ALRMAR_MNT_2                     0x00004000U
-#define RTC_ALRMAR_MNU                       0x00000F00U
-#define RTC_ALRMAR_MNU_0                     0x00000100U
-#define RTC_ALRMAR_MNU_1                     0x00000200U
-#define RTC_ALRMAR_MNU_2                     0x00000400U
-#define RTC_ALRMAR_MNU_3                     0x00000800U
-#define RTC_ALRMAR_MSK1                      0x00000080U
-#define RTC_ALRMAR_ST                        0x00000070U
-#define RTC_ALRMAR_ST_0                      0x00000010U
-#define RTC_ALRMAR_ST_1                      0x00000020U
-#define RTC_ALRMAR_ST_2                      0x00000040U
-#define RTC_ALRMAR_SU                        0x0000000FU
-#define RTC_ALRMAR_SU_0                      0x00000001U
-#define RTC_ALRMAR_SU_1                      0x00000002U
-#define RTC_ALRMAR_SU_2                      0x00000004U
-#define RTC_ALRMAR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      0x80000000U
-#define RTC_ALRMBR_WDSEL                     0x40000000U
-#define RTC_ALRMBR_DT                        0x30000000U
-#define RTC_ALRMBR_DT_0                      0x10000000U
-#define RTC_ALRMBR_DT_1                      0x20000000U
-#define RTC_ALRMBR_DU                        0x0F000000U
-#define RTC_ALRMBR_DU_0                      0x01000000U
-#define RTC_ALRMBR_DU_1                      0x02000000U
-#define RTC_ALRMBR_DU_2                      0x04000000U
-#define RTC_ALRMBR_DU_3                      0x08000000U
-#define RTC_ALRMBR_MSK3                      0x00800000U
-#define RTC_ALRMBR_PM                        0x00400000U
-#define RTC_ALRMBR_HT                        0x00300000U
-#define RTC_ALRMBR_HT_0                      0x00100000U
-#define RTC_ALRMBR_HT_1                      0x00200000U
-#define RTC_ALRMBR_HU                        0x000F0000U
-#define RTC_ALRMBR_HU_0                      0x00010000U
-#define RTC_ALRMBR_HU_1                      0x00020000U
-#define RTC_ALRMBR_HU_2                      0x00040000U
-#define RTC_ALRMBR_HU_3                      0x00080000U
-#define RTC_ALRMBR_MSK2                      0x00008000U
-#define RTC_ALRMBR_MNT                       0x00007000U
-#define RTC_ALRMBR_MNT_0                     0x00001000U
-#define RTC_ALRMBR_MNT_1                     0x00002000U
-#define RTC_ALRMBR_MNT_2                     0x00004000U
-#define RTC_ALRMBR_MNU                       0x00000F00U
-#define RTC_ALRMBR_MNU_0                     0x00000100U
-#define RTC_ALRMBR_MNU_1                     0x00000200U
-#define RTC_ALRMBR_MNU_2                     0x00000400U
-#define RTC_ALRMBR_MNU_3                     0x00000800U
-#define RTC_ALRMBR_MSK1                      0x00000080U
-#define RTC_ALRMBR_ST                        0x00000070U
-#define RTC_ALRMBR_ST_0                      0x00000010U
-#define RTC_ALRMBR_ST_1                      0x00000020U
-#define RTC_ALRMBR_ST_2                      0x00000040U
-#define RTC_ALRMBR_SU                        0x0000000FU
-#define RTC_ALRMBR_SU_0                      0x00000001U
-#define RTC_ALRMBR_SU_1                      0x00000002U
-#define RTC_ALRMBR_SU_2                      0x00000004U
-#define RTC_ALRMBR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          0x000000FFU
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           0x0000FFFFU
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     0x00007FFFU
-#define RTC_SHIFTR_ADD1S                     0x80000000U
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          0x00400000U
-#define RTC_TSTR_HT                          0x00300000U
-#define RTC_TSTR_HT_0                        0x00100000U
-#define RTC_TSTR_HT_1                        0x00200000U
-#define RTC_TSTR_HU                          0x000F0000U
-#define RTC_TSTR_HU_0                        0x00010000U
-#define RTC_TSTR_HU_1                        0x00020000U
-#define RTC_TSTR_HU_2                        0x00040000U
-#define RTC_TSTR_HU_3                        0x00080000U
-#define RTC_TSTR_MNT                         0x00007000U
-#define RTC_TSTR_MNT_0                       0x00001000U
-#define RTC_TSTR_MNT_1                       0x00002000U
-#define RTC_TSTR_MNT_2                       0x00004000U
-#define RTC_TSTR_MNU                         0x00000F00U
-#define RTC_TSTR_MNU_0                       0x00000100U
-#define RTC_TSTR_MNU_1                       0x00000200U
-#define RTC_TSTR_MNU_2                       0x00000400U
-#define RTC_TSTR_MNU_3                       0x00000800U
-#define RTC_TSTR_ST                          0x00000070U
-#define RTC_TSTR_ST_0                        0x00000010U
-#define RTC_TSTR_ST_1                        0x00000020U
-#define RTC_TSTR_ST_2                        0x00000040U
-#define RTC_TSTR_SU                          0x0000000FU
-#define RTC_TSTR_SU_0                        0x00000001U
-#define RTC_TSTR_SU_1                        0x00000002U
-#define RTC_TSTR_SU_2                        0x00000004U
-#define RTC_TSTR_SU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         0x0000E000U
-#define RTC_TSDR_WDU_0                       0x00002000U
-#define RTC_TSDR_WDU_1                       0x00004000U
-#define RTC_TSDR_WDU_2                       0x00008000U
-#define RTC_TSDR_MT                          0x00001000U
-#define RTC_TSDR_MU                          0x00000F00U
-#define RTC_TSDR_MU_0                        0x00000100U
-#define RTC_TSDR_MU_1                        0x00000200U
-#define RTC_TSDR_MU_2                        0x00000400U
-#define RTC_TSDR_MU_3                        0x00000800U
-#define RTC_TSDR_DT                          0x00000030U
-#define RTC_TSDR_DT_0                        0x00000010U
-#define RTC_TSDR_DT_1                        0x00000020U
-#define RTC_TSDR_DU                          0x0000000FU
-#define RTC_TSDR_DU_0                        0x00000001U
-#define RTC_TSDR_DU_1                        0x00000002U
-#define RTC_TSDR_DU_2                        0x00000004U
-#define RTC_TSDR_DU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        0x00008000U
-#define RTC_CALR_CALW8                       0x00004000U
-#define RTC_CALR_CALW16                      0x00002000U
-#define RTC_CALR_CALM                        0x000001FFU
-#define RTC_CALR_CALM_0                      0x00000001U
-#define RTC_CALR_CALM_1                      0x00000002U
-#define RTC_CALR_CALM_2                      0x00000004U
-#define RTC_CALR_CALM_3                      0x00000008U
-#define RTC_CALR_CALM_4                      0x00000010U
-#define RTC_CALR_CALM_5                      0x00000020U
-#define RTC_CALR_CALM_6                      0x00000040U
-#define RTC_CALR_CALM_7                      0x00000080U
-#define RTC_CALR_CALM_8                      0x00000100U
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               0x00040000U
-#define RTC_TAFCR_TSINSEL                    0x00020000U
-#define RTC_TAFCR_TAMPINSEL                  0x00010000U
-#define RTC_TAFCR_TAMPPUDIS                  0x00008000U
-#define RTC_TAFCR_TAMPPRCH                   0x00006000U
-#define RTC_TAFCR_TAMPPRCH_0                 0x00002000U
-#define RTC_TAFCR_TAMPPRCH_1                 0x00004000U
-#define RTC_TAFCR_TAMPFLT                    0x00001800U
-#define RTC_TAFCR_TAMPFLT_0                  0x00000800U
-#define RTC_TAFCR_TAMPFLT_1                  0x00001000U
-#define RTC_TAFCR_TAMPFREQ                   0x00000700U
-#define RTC_TAFCR_TAMPFREQ_0                 0x00000100U
-#define RTC_TAFCR_TAMPFREQ_1                 0x00000200U
-#define RTC_TAFCR_TAMPFREQ_2                 0x00000400U
-#define RTC_TAFCR_TAMPTS                     0x00000080U
-#define RTC_TAFCR_TAMP2TRG                   0x00000010U
-#define RTC_TAFCR_TAMP2E                     0x00000008U
-#define RTC_TAFCR_TAMPIE                     0x00000004U
-#define RTC_TAFCR_TAMP1TRG                   0x00000002U
-#define RTC_TAFCR_TAMP1E                     0x00000001U
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  0x0F000000U
-#define RTC_ALRMASSR_MASKSS_0                0x01000000U
-#define RTC_ALRMASSR_MASKSS_1                0x02000000U
-#define RTC_ALRMASSR_MASKSS_2                0x04000000U
-#define RTC_ALRMASSR_MASKSS_3                0x08000000U
-#define RTC_ALRMASSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
-#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
-#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
-#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
-#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
-#define RTC_ALRMBSSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           0xFFFFFFFFU
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Serial Audio Interface                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for SAI_GCR register  *******************/
-#define  SAI_GCR_SYNCIN                  0x00000003U        /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
-#define  SAI_GCR_SYNCIN_0                0x00000001U        /*!<Bit 0 */
-#define  SAI_GCR_SYNCIN_1                0x00000002U        /*!<Bit 1 */
-
-#define  SAI_GCR_SYNCOUT                 0x00000030U        /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
-#define  SAI_GCR_SYNCOUT_0               0x00000010U        /*!<Bit 0 */
-#define  SAI_GCR_SYNCOUT_1               0x00000020U        /*!<Bit 1 */
-
-/*******************  Bit definition for SAI_xCR1 register  *******************/
-#define  SAI_xCR1_MODE                    0x00000003U        /*!<MODE[1:0] bits (Audio Block Mode)           */
-#define  SAI_xCR1_MODE_0                  0x00000001U        /*!<Bit 0 */
-#define  SAI_xCR1_MODE_1                  0x00000002U        /*!<Bit 1 */
-
-#define  SAI_xCR1_PRTCFG                  0x0000000CU        /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
-#define  SAI_xCR1_PRTCFG_0                0x00000004U        /*!<Bit 0 */
-#define  SAI_xCR1_PRTCFG_1                0x00000008U        /*!<Bit 1 */
-
-#define  SAI_xCR1_DS                      0x000000E0U        /*!<DS[1:0] bits (Data Size) */
-#define  SAI_xCR1_DS_0                    0x00000020U        /*!<Bit 0 */
-#define  SAI_xCR1_DS_1                    0x00000040U        /*!<Bit 1 */
-#define  SAI_xCR1_DS_2                    0x00000080U        /*!<Bit 2 */
-
-#define  SAI_xCR1_LSBFIRST                0x00000100U        /*!<LSB First Configuration  */
-#define  SAI_xCR1_CKSTR                   0x00000200U        /*!<ClocK STRobing edge      */
-
-#define  SAI_xCR1_SYNCEN                  0x00000C00U        /*!<SYNCEN[1:0](SYNChronization ENable) */
-#define  SAI_xCR1_SYNCEN_0                0x00000400U        /*!<Bit 0 */
-#define  SAI_xCR1_SYNCEN_1                0x00000800U        /*!<Bit 1 */
-
-#define  SAI_xCR1_MONO                    0x00001000U        /*!<Mono mode                  */
-#define  SAI_xCR1_OUTDRIV                 0x00002000U        /*!<Output Drive               */
-#define  SAI_xCR1_SAIEN                   0x00010000U        /*!<Audio Block enable         */
-#define  SAI_xCR1_DMAEN                   0x00020000U        /*!<DMA enable                 */
-#define  SAI_xCR1_NODIV                   0x00080000U        /*!<No Divider Configuration   */
-
-#define  SAI_xCR1_MCKDIV                  0x00F00000U        /*!<MCKDIV[3:0] (Master ClocK Divider)  */
-#define  SAI_xCR1_MCKDIV_0                0x00100000U        /*!<Bit 0  */
-#define  SAI_xCR1_MCKDIV_1                0x00200000U        /*!<Bit 1  */
-#define  SAI_xCR1_MCKDIV_2                0x00400000U        /*!<Bit 2  */
-#define  SAI_xCR1_MCKDIV_3                0x00800000U        /*!<Bit 3  */
-
-/*******************  Bit definition for SAI_xCR2 register  *******************/
-#define  SAI_xCR2_FTH                     0x00000007U        /*!<FTH[2:0](Fifo THreshold)  */
-#define  SAI_xCR2_FTH_0                   0x00000001U        /*!<Bit 0 */
-#define  SAI_xCR2_FTH_1                   0x00000002U        /*!<Bit 1 */
-#define  SAI_xCR2_FTH_2                   0x00000004U        /*!<Bit 2 */
-
-#define  SAI_xCR2_FFLUSH                  0x00000008U        /*!<Fifo FLUSH                       */
-#define  SAI_xCR2_TRIS                    0x00000010U        /*!<TRIState Management on data line */
-#define  SAI_xCR2_MUTE                    0x00000020U        /*!<Mute mode                        */
-#define  SAI_xCR2_MUTEVAL                 0x00000040U        /*!<Muate value                      */
-
-#define  SAI_xCR2_MUTECNT                  0x00001F80U       /*!<MUTECNT[5:0] (MUTE counter) */
-#define  SAI_xCR2_MUTECNT_0               0x00000080U        /*!<Bit 0 */
-#define  SAI_xCR2_MUTECNT_1               0x00000100U        /*!<Bit 1 */
-#define  SAI_xCR2_MUTECNT_2               0x00000200U        /*!<Bit 2 */
-#define  SAI_xCR2_MUTECNT_3               0x00000400U        /*!<Bit 3 */
-#define  SAI_xCR2_MUTECNT_4               0x00000800U        /*!<Bit 4 */
-#define  SAI_xCR2_MUTECNT_5               0x00001000U        /*!<Bit 5 */
-
-#define  SAI_xCR2_CPL                     0x00002000U        /*!< Complement Bit             */
-
-#define  SAI_xCR2_COMP                    0x0000C000U        /*!<COMP[1:0] (Companding mode) */
-#define  SAI_xCR2_COMP_0                  0x00004000U        /*!<Bit 0 */
-#define  SAI_xCR2_COMP_1                  0x00008000U        /*!<Bit 1 */
-
-/******************  Bit definition for SAI_xFRCR register  *******************/
-#define  SAI_xFRCR_FRL                    0x000000FFU        /*!<FRL[1:0](Frame length)  */
-#define  SAI_xFRCR_FRL_0                  0x00000001U        /*!<Bit 0 */
-#define  SAI_xFRCR_FRL_1                  0x00000002U        /*!<Bit 1 */
-#define  SAI_xFRCR_FRL_2                  0x00000004U        /*!<Bit 2 */
-#define  SAI_xFRCR_FRL_3                  0x00000008U        /*!<Bit 3 */
-#define  SAI_xFRCR_FRL_4                  0x00000010U        /*!<Bit 4 */
-#define  SAI_xFRCR_FRL_5                  0x00000020U        /*!<Bit 5 */
-#define  SAI_xFRCR_FRL_6                  0x00000040U        /*!<Bit 6 */
-#define  SAI_xFRCR_FRL_7                  0x00000080U        /*!<Bit 7 */
-
-#define  SAI_xFRCR_FSALL                  0x00007F00U        /*!<FRL[1:0] (Frame synchronization active level length)  */
-#define  SAI_xFRCR_FSALL_0                0x00000100U        /*!<Bit 0 */
-#define  SAI_xFRCR_FSALL_1                0x00000200U        /*!<Bit 1 */
-#define  SAI_xFRCR_FSALL_2                0x00000400U        /*!<Bit 2 */
-#define  SAI_xFRCR_FSALL_3                0x00000800U        /*!<Bit 3 */
-#define  SAI_xFRCR_FSALL_4                0x00001000U        /*!<Bit 4 */
-#define  SAI_xFRCR_FSALL_5                0x00002000U        /*!<Bit 5 */
-#define  SAI_xFRCR_FSALL_6                0x00004000U        /*!<Bit 6 */
-
-#define  SAI_xFRCR_FSDEF                  0x00010000U        /*!< Frame Synchronization Definition */
-#define  SAI_xFRCR_FSPOL                  0x00020000U        /*!<Frame Synchronization POLarity    */
-#define  SAI_xFRCR_FSOFF                  0x00040000U        /*!<Frame Synchronization OFFset      */
-/* Legacy defines */
-#define  SAI_xFRCR_FSPO                   SAI_xFRCR_FSPOL
-
-/******************  Bit definition for SAI_xSLOTR register  *******************/
-#define  SAI_xSLOTR_FBOFF                 0x0000001FU        /*!<FRL[4:0](First Bit Offset)  */
-#define  SAI_xSLOTR_FBOFF_0               0x00000001U        /*!<Bit 0 */
-#define  SAI_xSLOTR_FBOFF_1               0x00000002U        /*!<Bit 1 */
-#define  SAI_xSLOTR_FBOFF_2               0x00000004U        /*!<Bit 2 */
-#define  SAI_xSLOTR_FBOFF_3               0x00000008U        /*!<Bit 3 */
-#define  SAI_xSLOTR_FBOFF_4               0x00000010U        /*!<Bit 4 */
-
-#define  SAI_xSLOTR_SLOTSZ                0x000000C0U        /*!<SLOTSZ[1:0] (Slot size)  */
-#define  SAI_xSLOTR_SLOTSZ_0              0x00000040U        /*!<Bit 0 */
-#define  SAI_xSLOTR_SLOTSZ_1              0x00000080U        /*!<Bit 1 */
-
-#define  SAI_xSLOTR_NBSLOT                0x00000F00U        /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
-#define  SAI_xSLOTR_NBSLOT_0              0x00000100U        /*!<Bit 0 */
-#define  SAI_xSLOTR_NBSLOT_1              0x00000200U        /*!<Bit 1 */
-#define  SAI_xSLOTR_NBSLOT_2              0x00000400U        /*!<Bit 2 */
-#define  SAI_xSLOTR_NBSLOT_3              0x00000800U        /*!<Bit 3 */
-
-#define  SAI_xSLOTR_SLOTEN                0xFFFF0000U        /*!<SLOTEN[15:0] (Slot Enable)  */
-
-/*******************  Bit definition for SAI_xIMR register  *******************/
-#define  SAI_xIMR_OVRUDRIE                0x00000001U        /*!<Overrun underrun interrupt enable                              */
-#define  SAI_xIMR_MUTEDETIE               0x00000002U        /*!<Mute detection interrupt enable                                */
-#define  SAI_xIMR_WCKCFGIE                0x00000004U        /*!<Wrong Clock Configuration interrupt enable                     */
-#define  SAI_xIMR_FREQIE                  0x00000008U        /*!<FIFO request interrupt enable                                  */
-#define  SAI_xIMR_CNRDYIE                 0x00000010U        /*!<Codec not ready interrupt enable                               */
-#define  SAI_xIMR_AFSDETIE                0x00000020U        /*!<Anticipated frame synchronization detection interrupt enable   */
-#define  SAI_xIMR_LFSDETIE                0x00000040U        /*!<Late frame synchronization detection interrupt enable          */
-
-/********************  Bit definition for SAI_xSR register  *******************/
-#define  SAI_xSR_OVRUDR                   0x00000001U         /*!<Overrun underrun                               */
-#define  SAI_xSR_MUTEDET                  0x00000002U         /*!<Mute detection                                 */
-#define  SAI_xSR_WCKCFG                   0x00000004U         /*!<Wrong Clock Configuration                      */
-#define  SAI_xSR_FREQ                     0x00000008U         /*!<FIFO request                                   */
-#define  SAI_xSR_CNRDY                    0x00000010U         /*!<Codec not ready                                */
-#define  SAI_xSR_AFSDET                   0x00000020U         /*!<Anticipated frame synchronization detection    */
-#define  SAI_xSR_LFSDET                   0x00000040U         /*!<Late frame synchronization detection           */
-
-#define  SAI_xSR_FLVL                     0x00070000U         /*!<FLVL[2:0] (FIFO Level Threshold)               */
-#define  SAI_xSR_FLVL_0                   0x00010000U         /*!<Bit 0 */
-#define  SAI_xSR_FLVL_1                   0x00020000U         /*!<Bit 1 */
-#define  SAI_xSR_FLVL_2                   0x00040000U         /*!<Bit 2 */
-
-/******************  Bit definition for SAI_xCLRFR register  ******************/
-#define  SAI_xCLRFR_COVRUDR               0x00000001U        /*!<Clear Overrun underrun                               */
-#define  SAI_xCLRFR_CMUTEDET              0x00000002U        /*!<Clear Mute detection                                 */
-#define  SAI_xCLRFR_CWCKCFG               0x00000004U        /*!<Clear Wrong Clock Configuration                      */
-#define  SAI_xCLRFR_CFREQ                 0x00000008U        /*!<Clear FIFO request                                   */
-#define  SAI_xCLRFR_CCNRDY                0x00000010U        /*!<Clear Codec not ready                                */
-#define  SAI_xCLRFR_CAFSDET               0x00000020U        /*!<Clear Anticipated frame synchronization detection    */
-#define  SAI_xCLRFR_CLFSDET               0x00000040U        /*!<Clear Late frame synchronization detection           */
-
-/******************  Bit definition for SAI_xDR register  ******************/
-#define  SAI_xDR_DATA                     0xFFFFFFFFU        
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          SD host Interface                                 */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SDIO_POWER register  ******************/
-#define  SDIO_POWER_PWRCTRL                  0x03U               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDIO_POWER_PWRCTRL_0                0x01U               /*!<Bit 0 */
-#define  SDIO_POWER_PWRCTRL_1                0x02U               /*!<Bit 1 */
-
-/******************  Bit definition for SDIO_CLKCR register  ******************/
-#define  SDIO_CLKCR_CLKDIV                   0x00FFU            /*!<Clock divide factor             */
-#define  SDIO_CLKCR_CLKEN                    0x0100U            /*!<Clock enable bit                */
-#define  SDIO_CLKCR_PWRSAV                   0x0200U            /*!<Power saving configuration bit  */
-#define  SDIO_CLKCR_BYPASS                   0x0400U            /*!<Clock divider bypass enable bit */
-
-#define  SDIO_CLKCR_WIDBUS                   0x1800U            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDIO_CLKCR_WIDBUS_0                 0x0800U            /*!<Bit 0 */
-#define  SDIO_CLKCR_WIDBUS_1                 0x1000U            /*!<Bit 1 */
-
-#define  SDIO_CLKCR_NEGEDGE                  0x2000U            /*!<SDIO_CK dephasing selection bit */
-#define  SDIO_CLKCR_HWFC_EN                  0x4000U            /*!<HW Flow Control enable          */
-
-/*******************  Bit definition for SDIO_ARG register  *******************/
-#define  SDIO_ARG_CMDARG                     0xFFFFFFFFU            /*!<Command argument */
-
-/*******************  Bit definition for SDIO_CMD register  *******************/
-#define  SDIO_CMD_CMDINDEX                   0x003FU            /*!<Command Index                               */
-
-#define  SDIO_CMD_WAITRESP                   0x00C0U            /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDIO_CMD_WAITRESP_0                 0x0040U            /*!< Bit 0 */
-#define  SDIO_CMD_WAITRESP_1                 0x0080U            /*!< Bit 1 */
-
-#define  SDIO_CMD_WAITINT                    0x0100U            /*!<CPSM Waits for Interrupt Request                               */
-#define  SDIO_CMD_WAITPEND                   0x0200U            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDIO_CMD_CPSMEN                     0x0400U            /*!<Command path state machine (CPSM) Enable bit                   */
-#define  SDIO_CMD_SDIOSUSPEND                0x0800U            /*!<SD I/O suspend command                                         */
-#define  SDIO_CMD_ENCMDCOMPL                 0x1000U            /*!<Enable CMD completion                                          */
-#define  SDIO_CMD_NIEN                       0x2000U            /*!<Not Interrupt Enable */
-#define  SDIO_CMD_CEATACMD                   0x4000U            /*!<CE-ATA command       */
-
-/*****************  Bit definition for SDIO_RESPCMD register  *****************/
-#define  SDIO_RESPCMD_RESPCMD                0x3FU               /*!<Response command index */
-
-/******************  Bit definition for SDIO_RESP0 register  ******************/
-#define  SDIO_RESP0_CARDSTATUS0              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP1 register  ******************/
-#define  SDIO_RESP1_CARDSTATUS1              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP2 register  ******************/
-#define  SDIO_RESP2_CARDSTATUS2              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP3 register  ******************/
-#define  SDIO_RESP3_CARDSTATUS3              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP4 register  ******************/
-#define  SDIO_RESP4_CARDSTATUS4              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_DTIMER register  *****************/
-#define  SDIO_DTIMER_DATATIME                0xFFFFFFFFU        /*!<Data timeout period. */
-
-/******************  Bit definition for SDIO_DLEN register  *******************/
-#define  SDIO_DLEN_DATALENGTH                0x01FFFFFFU        /*!<Data length value    */
-
-/******************  Bit definition for SDIO_DCTRL register  ******************/
-#define  SDIO_DCTRL_DTEN                     0x0001U            /*!<Data transfer enabled bit         */
-#define  SDIO_DCTRL_DTDIR                    0x0002U            /*!<Data transfer direction selection */
-#define  SDIO_DCTRL_DTMODE                   0x0004U            /*!<Data transfer mode selection      */
-#define  SDIO_DCTRL_DMAEN                    0x0008U            /*!<DMA enabled bit                   */
-
-#define  SDIO_DCTRL_DBLOCKSIZE               0x00F0U            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDIO_DCTRL_DBLOCKSIZE_0             0x0010U            /*!<Bit 0 */
-#define  SDIO_DCTRL_DBLOCKSIZE_1             0x0020U            /*!<Bit 1 */
-#define  SDIO_DCTRL_DBLOCKSIZE_2             0x0040U            /*!<Bit 2 */
-#define  SDIO_DCTRL_DBLOCKSIZE_3             0x0080U            /*!<Bit 3 */
-
-#define  SDIO_DCTRL_RWSTART                  0x0100U            /*!<Read wait start         */
-#define  SDIO_DCTRL_RWSTOP                   0x0200U            /*!<Read wait stop          */
-#define  SDIO_DCTRL_RWMOD                    0x0400U            /*!<Read wait mode          */
-#define  SDIO_DCTRL_SDIOEN                   0x0800U            /*!<SD I/O enable functions */
-
-/******************  Bit definition for SDIO_DCOUNT register  *****************/
-#define  SDIO_DCOUNT_DATACOUNT               0x01FFFFFFU        /*!<Data count value */
-
-/******************  Bit definition for SDIO_STA register  ********************/
-#define  SDIO_STA_CCRCFAIL                   0x00000001U        /*!<Command response received (CRC check failed)  */
-#define  SDIO_STA_DCRCFAIL                   0x00000002U        /*!<Data block sent/received (CRC check failed)   */
-#define  SDIO_STA_CTIMEOUT                   0x00000004U        /*!<Command response timeout                      */
-#define  SDIO_STA_DTIMEOUT                   0x00000008U        /*!<Data timeout                                  */
-#define  SDIO_STA_TXUNDERR                   0x00000010U        /*!<Transmit FIFO underrun error                  */
-#define  SDIO_STA_RXOVERR                    0x00000020U        /*!<Received FIFO overrun error                   */
-#define  SDIO_STA_CMDREND                    0x00000040U        /*!<Command response received (CRC check passed)  */
-#define  SDIO_STA_CMDSENT                    0x00000080U        /*!<Command sent (no response required)           */
-#define  SDIO_STA_DATAEND                    0x00000100U        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
-#define  SDIO_STA_STBITERR                   0x00000200U        /*!<Start bit not detected on all data signals in wide bus mode */
-#define  SDIO_STA_DBCKEND                    0x00000400U        /*!<Data block sent/received (CRC check passed)   */
-#define  SDIO_STA_CMDACT                     0x00000800U        /*!<Command transfer in progress                  */
-#define  SDIO_STA_TXACT                      0x00001000U        /*!<Data transmit in progress                     */
-#define  SDIO_STA_RXACT                      0x00002000U        /*!<Data receive in progress                      */
-#define  SDIO_STA_TXFIFOHE                   0x00004000U        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDIO_STA_RXFIFOHF                   0x00008000U        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDIO_STA_TXFIFOF                    0x00010000U        /*!<Transmit FIFO full                            */
-#define  SDIO_STA_RXFIFOF                    0x00020000U        /*!<Receive FIFO full                             */
-#define  SDIO_STA_TXFIFOE                    0x00040000U        /*!<Transmit FIFO empty                           */
-#define  SDIO_STA_RXFIFOE                    0x00080000U        /*!<Receive FIFO empty                            */
-#define  SDIO_STA_TXDAVL                     0x00100000U        /*!<Data available in transmit FIFO               */
-#define  SDIO_STA_RXDAVL                     0x00200000U        /*!<Data available in receive FIFO                */
-#define  SDIO_STA_SDIOIT                     0x00400000U        /*!<SDIO interrupt received                       */
-#define  SDIO_STA_CEATAEND                   0x00800000U        /*!<CE-ATA command completion signal received for CMD61 */
-
-/*******************  Bit definition for SDIO_ICR register  *******************/
-#define  SDIO_ICR_CCRCFAILC                  0x00000001U        /*!<CCRCFAIL flag clear bit */
-#define  SDIO_ICR_DCRCFAILC                  0x00000002U        /*!<DCRCFAIL flag clear bit */
-#define  SDIO_ICR_CTIMEOUTC                  0x00000004U        /*!<CTIMEOUT flag clear bit */
-#define  SDIO_ICR_DTIMEOUTC                  0x00000008U        /*!<DTIMEOUT flag clear bit */
-#define  SDIO_ICR_TXUNDERRC                  0x00000010U        /*!<TXUNDERR flag clear bit */
-#define  SDIO_ICR_RXOVERRC                   0x00000020U        /*!<RXOVERR flag clear bit  */
-#define  SDIO_ICR_CMDRENDC                   0x00000040U        /*!<CMDREND flag clear bit  */
-#define  SDIO_ICR_CMDSENTC                   0x00000080U        /*!<CMDSENT flag clear bit  */
-#define  SDIO_ICR_DATAENDC                   0x00000100U        /*!<DATAEND flag clear bit  */
-#define  SDIO_ICR_STBITERRC                  0x00000200U        /*!<STBITERR flag clear bit */
-#define  SDIO_ICR_DBCKENDC                   0x00000400U        /*!<DBCKEND flag clear bit  */
-#define  SDIO_ICR_SDIOITC                    0x00400000U        /*!<SDIOIT flag clear bit   */
-#define  SDIO_ICR_CEATAENDC                  0x00800000U        /*!<CEATAEND flag clear bit */
-
-/******************  Bit definition for SDIO_MASK register  *******************/
-#define  SDIO_MASK_CCRCFAILIE                0x00000001U        /*!<Command CRC Fail Interrupt Enable          */
-#define  SDIO_MASK_DCRCFAILIE                0x00000002U        /*!<Data CRC Fail Interrupt Enable             */
-#define  SDIO_MASK_CTIMEOUTIE                0x00000004U        /*!<Command TimeOut Interrupt Enable           */
-#define  SDIO_MASK_DTIMEOUTIE                0x00000008U        /*!<Data TimeOut Interrupt Enable              */
-#define  SDIO_MASK_TXUNDERRIE                0x00000010U        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
-#define  SDIO_MASK_RXOVERRIE                 0x00000020U        /*!<Rx FIFO OverRun Error Interrupt Enable     */
-#define  SDIO_MASK_CMDRENDIE                 0x00000040U        /*!<Command Response Received Interrupt Enable */
-#define  SDIO_MASK_CMDSENTIE                 0x00000080U        /*!<Command Sent Interrupt Enable              */
-#define  SDIO_MASK_DATAENDIE                 0x00000100U        /*!<Data End Interrupt Enable                  */
-#define  SDIO_MASK_STBITERRIE                0x00000200U        /*!<Start Bit Error Interrupt Enable           */
-#define  SDIO_MASK_DBCKENDIE                 0x00000400U        /*!<Data Block End Interrupt Enable            */
-#define  SDIO_MASK_CMDACTIE                  0x00000800U        /*!<CCommand Acting Interrupt Enable           */
-#define  SDIO_MASK_TXACTIE                   0x00001000U        /*!<Data Transmit Acting Interrupt Enable      */
-#define  SDIO_MASK_RXACTIE                   0x00002000U        /*!<Data receive acting interrupt enabled      */
-#define  SDIO_MASK_TXFIFOHEIE                0x00004000U        /*!<Tx FIFO Half Empty interrupt Enable        */
-#define  SDIO_MASK_RXFIFOHFIE                0x00008000U        /*!<Rx FIFO Half Full interrupt Enable         */
-#define  SDIO_MASK_TXFIFOFIE                 0x00010000U        /*!<Tx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_RXFIFOFIE                 0x00020000U        /*!<Rx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_TXFIFOEIE                 0x00040000U        /*!<Tx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_RXFIFOEIE                 0x00080000U        /*!<Rx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_TXDAVLIE                  0x00100000U        /*!<Data available in Tx FIFO interrupt Enable */
-#define  SDIO_MASK_RXDAVLIE                  0x00200000U        /*!<Data available in Rx FIFO interrupt Enable */
-#define  SDIO_MASK_SDIOITIE                  0x00400000U        /*!<SDIO Mode Interrupt Received interrupt Enable */
-#define  SDIO_MASK_CEATAENDIE                0x00800000U        /*!<CE-ATA command completion signal received Interrupt Enable */
-
-/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
-#define  SDIO_FIFOCNT_FIFOCOUNT              0x00FFFFFFU        /*!<Remaining number of words to be written to or read from the FIFO */
-
-/******************  Bit definition for SDIO_FIFO register  *******************/
-#define  SDIO_FIFO_FIFODATA                  0xFFFFFFFFU        /*!<Receive and transmit FIFO data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        0x00000001U            /*!<Clock Phase      */
-#define  SPI_CR1_CPOL                        0x00000002U            /*!<Clock Polarity   */
-#define  SPI_CR1_MSTR                        0x00000004U            /*!<Master Selection */
-
-#define  SPI_CR1_BR                          0x00000038U            /*!<BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        0x00000008U            /*!<Bit 0 */
-#define  SPI_CR1_BR_1                        0x00000010U            /*!<Bit 1 */
-#define  SPI_CR1_BR_2                        0x00000020U            /*!<Bit 2 */
-
-#define  SPI_CR1_SPE                         0x00000040U            /*!<SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    0x00000080U            /*!<Frame Format                        */
-#define  SPI_CR1_SSI                         0x00000100U            /*!<Internal slave select               */
-#define  SPI_CR1_SSM                         0x00000200U            /*!<Software slave management           */
-#define  SPI_CR1_RXONLY                      0x00000400U            /*!<Receive only                        */
-#define  SPI_CR1_DFF                         0x00000800U            /*!<Data Frame Format                   */
-#define  SPI_CR1_CRCNEXT                     0x00001000U            /*!<Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       0x00002000U            /*!<Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      0x00004000U            /*!<Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    0x00008000U            /*!<Bidirectional data mode enable      */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     0x00000001U               /*!<Rx Buffer DMA Enable                 */
-#define  SPI_CR2_TXDMAEN                     0x00000002U               /*!<Tx Buffer DMA Enable                 */
-#define  SPI_CR2_SSOE                        0x00000004U               /*!<SS Output Enable                     */
-#define  SPI_CR2_FRF                         0x00000010U               /*!<Frame Format                         */
-#define  SPI_CR2_ERRIE                       0x00000020U               /*!<Error Interrupt Enable               */
-#define  SPI_CR2_RXNEIE                      0x00000040U               /*!<RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       0x00000080U               /*!<Tx buffer Empty Interrupt Enable     */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         0x00000001U               /*!<Receive buffer Not Empty */
-#define  SPI_SR_TXE                          0x00000002U               /*!<Transmit buffer Empty    */
-#define  SPI_SR_CHSIDE                       0x00000004U               /*!<Channel side             */
-#define  SPI_SR_UDR                          0x00000008U               /*!<Underrun flag            */
-#define  SPI_SR_CRCERR                       0x00000010U               /*!<CRC Error flag           */
-#define  SPI_SR_MODF                         0x00000020U               /*!<Mode fault               */
-#define  SPI_SR_OVR                          0x00000040U               /*!<Overrun flag             */
-#define  SPI_SR_BSY                          0x00000080U               /*!<Busy flag                */
-#define  SPI_SR_FRE                          0x00000100U               /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           0x0000FFFFU            /*!<Data Register           */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   0x0000FFFFU            /*!<CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    0x0000FFFFU            /*!<Rx CRC Register         */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    0x0000FFFFU            /*!<Tx CRC Register         */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   0x00000001U            /*!<Channel length (number of bits per audio channel) */
-
-#define  SPI_I2SCFGR_DATLEN                  0x00000006U            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define  SPI_I2SCFGR_DATLEN_0                0x00000002U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                0x00000004U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_CKPOL                   0x00000008U            /*!<steady state clock polarity               */
-
-#define  SPI_I2SCFGR_I2SSTD                  0x00000030U            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U            /*!<PCM frame synchronization                 */
-
-#define  SPI_I2SCFGR_I2SCFG                  0x00000300U            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_I2SE                    0x00000400U            /*!<I2S Enable         */
-#define  SPI_I2SCFGR_I2SMOD                  0x00000800U            /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    0x000000FFU            /*!<I2S Linear prescaler         */
-#define  SPI_I2SPR_ODD                       0x00000100U            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     0x00000200U            /*!<Master Clock Output Enable   */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 SYSCFG                                     */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
-#define SYSCFG_MEMRMP_MEM_MODE          0x00000007U /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        0x00000001U
-#define SYSCFG_MEMRMP_MEM_MODE_1        0x00000002U
-#define SYSCFG_MEMRMP_MEM_MODE_2        0x00000004U
-
-#define SYSCFG_MEMRMP_UFB_MODE          0x00000100U /*!< User Flash Bank mode    */
-#define SYSCFG_SWP_FMC                  0x00000C00U /*!< FMC memory mapping swap */
-
-/******************  Bit definition for SYSCFG_PMC register  ******************/
-#define SYSCFG_PMC_ADCxDC2              0x00070000U /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC1DC2              0x00010000U /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC2DC2              0x00020000U /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC3DC2              0x00040000U /*!< Refer to AN4073 on how to use this bit  */
-
-#define SYSCFG_PMC_MII_RMII_SEL         0x00800000U /*!<Ethernet PHY interface selection */
-/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
-#define SYSCFG_PMC_MII_RMII             SYSCFG_PMC_MII_RMII_SEL
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
-/** 
-  * @brief   EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         0x0003U /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         0x0004U /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         0x0005U /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         0x0006U /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PI         0x0008U /*!<PI[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PJ         0x0009U /*!<PJ[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PK         0x000AU /*!<PK[0] pin */
-
-/** 
-  * @brief   EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         0x0030U /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         0x0040U /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         0x0050U /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         0x0060U /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PI         0x0080U /*!<PI[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PJ         0x0090U /*!<PJ[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PK         0x00A0U /*!<PK[1] pin */
-
-
-/** 
-  * @brief   EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         0x0300U /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         0x0400U /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         0x0500U /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         0x0600U /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PI         0x0800U /*!<PI[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PJ         0x0900U /*!<PJ[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PK         0x0A00U /*!<PK[2] pin */
-
-
-/** 
-  * @brief   EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         0x3000U /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         0x4000U /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         0x5000U /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         0x6000U /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PI         0x8000U /*!<PI[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PJ         0x9000U /*!<PJ[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PK         0xA000U /*!<PK[3] pin */
-
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
-/** 
-  * @brief   EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         0x0003U /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         0x0004U /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         0x0005U /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         0x0006U /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PI         0x0008U /*!<PI[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PJ         0x0009U /*!<PJ[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PK         0x000AU /*!<PK[4] pin */
-
-/** 
-  * @brief   EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         0x0030U /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         0x0040U /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         0x0050U /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         0x0060U /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PI         0x0080U /*!<PI[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PJ         0x0090U /*!<PJ[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PK         0x00A0U /*!<PK[5] pin */
-
-/** 
-  * @brief   EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         0x0300U /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         0x0400U /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         0x0500U /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         0x0600U /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PI         0x0800U /*!<PI[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PJ         0x0900U /*!<PJ[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PK         0x0A00U /*!<PK[6] pin */
-
-
-/** 
-  * @brief   EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         0x3000U /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         0x4000U /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         0x5000U /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         0x6000U /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PI         0x8000U /*!<PI[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PJ         0x9000U /*!<PJ[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PK         0xA000U /*!<PK[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
-           
-/** 
-  * @brief   EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         0x0003U /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         0x0004U /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         0x0005U /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         0x0006U /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PI         0x0008U /*!<PI[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PJ         0x0009U /*!<PJ[8] pin */
-
-/** 
-  * @brief   EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         0x0030U /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         0x0040U /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         0x0050U /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         0x0060U /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PI         0x0080U /*!<PI[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PJ         0x0090U /*!<PJ[9] pin */
-
-
-/** 
-  * @brief   EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        0x0300U /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        0x0400U /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        0x0500U /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        0x0600U /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PI        0x0800U /*!<PI[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PJ        0x0900U /*!<PJ[10] pin */
-
-
-/** 
-  * @brief   EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        0x3000U /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        0x4000U /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        0x5000U /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        0x6000U /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PI        0x8000U /*!<PI[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PJ        0x9000U /*!<PJ[11] pin */
-
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
-/** 
-  * @brief   EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        0x0003U /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        0x0004U /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        0x0005U /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        0x0006U /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PI        0x0008U /*!<PI[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PJ        0x0009U /*!<PJ[12] pin */
-
-
-/** 
-  * @brief   EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        0x0030U /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        0x0040U /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        0x0050U /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        0x0060U /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PI        0x0008U /*!<PI[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PJ        0x0009U /*!<PJ[13] pin */
-
-
-/** 
-  * @brief   EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        0x0300U /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        0x0400U /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        0x0500U /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        0x0600U /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PI        0x0800U /*!<PI[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PJ        0x0900U /*!<PJ[14] pin */
-
-
-/** 
-  * @brief   EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        0x3000U /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        0x4000U /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        0x5000U /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        0x6000U /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PI        0x8000U /*!<PI[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PJ        0x9000U /*!<PJ[15] pin */
-
-/******************  Bit definition for SYSCFG_CMPCR register  ****************/  
-#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell ready flag */
-#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell power-down */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    TIM                                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
-#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
-#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
-#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
-#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
-
-#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
-
-#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
-
-#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        0x0001U            /*!<Capture/Compare Preloaded Control        */
-#define  TIM_CR2_CCUS                        0x0004U            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        0x0008U            /*!<Capture/Compare DMA Selection            */
-
-#define  TIM_CR2_MMS                         0x0070U            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
-#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
-#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
-#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        0x0007U            /*!<SMS[2:0] bits (Slave mode selection)    */
-#define  TIM_SMCR_SMS_0                      0x0001U            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      0x0002U            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      0x0004U            /*!<Bit 2 */
-
-#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
-#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
-
-#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
-
-#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
-
-#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
-#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
-#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
-#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
-#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
-#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
-#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
-#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
-#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
-#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
-#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
-#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
-#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
-#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
-#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
-#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
-#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
-#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
-#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          0x01U               /*!<Update Generation                         */
-#define  TIM_EGR_CC1G                        0x02U               /*!<Capture/Compare 1 Generation              */
-#define  TIM_EGR_CC2G                        0x04U               /*!<Capture/Compare 2 Generation              */
-#define  TIM_EGR_CC3G                        0x08U               /*!<Capture/Compare 3 Generation              */
-#define  TIM_EGR_CC4G                        0x10U               /*!<Capture/Compare 4 Generation              */
-#define  TIM_EGR_COMG                        0x20U               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          0x40U               /*!<Trigger Generation                        */
-#define  TIM_EGR_BG                          0x80U               /*!<Break Generation                          */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      0x0003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    0x0001U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    0x0002U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC1FE                     0x0004U            /*!<Output Compare 1 Fast enable                 */
-#define  TIM_CCMR1_OC1PE                     0x0008U            /*!<Output Compare 1 Preload enable              */
-
-#define  TIM_CCMR1_OC1M                      0x0070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define  TIM_CCMR1_OC1M_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    0x0040U            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC1CE                     0x0080U            /*!<Output Compare 1Clear Enable                 */
-
-#define  TIM_CCMR1_CC2S                      0x0300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    0x0100U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    0x0200U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC2FE                     0x0400U            /*!<Output Compare 2 Fast enable                 */
-#define  TIM_CCMR1_OC2PE                     0x0800U            /*!<Output Compare 2 Preload enable              */
-
-#define  TIM_CCMR1_OC2M                      0x7000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define  TIM_CCMR1_OC2M_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    0x4000U            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC2CE                     0x8000U            /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      0x0003U            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define  TIM_CCMR2_CC3S_0                    0x0001U            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    0x0002U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC3FE                     0x0004U            /*!<Output Compare 3 Fast enable           */
-#define  TIM_CCMR2_OC3PE                     0x0008U            /*!<Output Compare 3 Preload enable        */
-
-#define  TIM_CCMR2_OC3M                      0x0070U            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    0x0040U            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC3CE                     0x0080U            /*!<Output Compare 3 Clear Enable */
-
-#define  TIM_CCMR2_CC4S                      0x0300U            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    0x0100U            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    0x0200U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC4FE                     0x0400U            /*!<Output Compare 4 Fast enable    */
-#define  TIM_CCMR2_OC4PE                     0x0800U            /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR2_OC4M                      0x7000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    0x4000U            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       0x0001U            /*!<Capture/Compare 1 output enable                 */
-#define  TIM_CCER_CC1P                       0x0002U            /*!<Capture/Compare 1 output Polarity               */
-#define  TIM_CCER_CC1NE                      0x0004U            /*!<Capture/Compare 1 Complementary output enable   */
-#define  TIM_CCER_CC1NP                      0x0008U            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       0x0010U            /*!<Capture/Compare 2 output enable                 */
-#define  TIM_CCER_CC2P                       0x0020U            /*!<Capture/Compare 2 output Polarity               */
-#define  TIM_CCER_CC2NE                      0x0040U            /*!<Capture/Compare 2 Complementary output enable   */
-#define  TIM_CCER_CC2NP                      0x0080U            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       0x0100U            /*!<Capture/Compare 3 output enable                 */
-#define  TIM_CCER_CC3P                       0x0200U            /*!<Capture/Compare 3 output Polarity               */
-#define  TIM_CCER_CC3NE                      0x0400U            /*!<Capture/Compare 3 Complementary output enable   */
-#define  TIM_CCER_CC3NP                      0x0800U            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       0x1000U            /*!<Capture/Compare 4 output enable                 */
-#define  TIM_CCER_CC4P                       0x2000U            /*!<Capture/Compare 4 output Polarity               */
-#define  TIM_CCER_CC4NP                      0x8000U            /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         0xFFU               /*!<Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
-
-/*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        0x00FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      0x0001U            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      0x0002U            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      0x0004U            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      0x0008U            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      0x0010U            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      0x0020U            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      0x0040U            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      0x0080U            /*!<Bit 7 */
-
-#define  TIM_BDTR_LOCK                       0x0300U            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     0x0100U            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     0x0200U            /*!<Bit 1 */
-
-#define  TIM_BDTR_OSSI                       0x0400U            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       0x0800U            /*!<Off-State Selection for Run mode  */
-#define  TIM_BDTR_BKE                        0x1000U            /*!<Break enable                      */
-#define  TIM_BDTR_BKP                        0x2000U            /*!<Break Polarity                    */
-#define  TIM_BDTR_AOE                        0x4000U            /*!<Automatic Output enable           */
-#define  TIM_BDTR_MOE                        0x8000U            /*!<Main Output enable                */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
-
-#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
-#define TIM_OR_ITR1_RMP                      0x0C00U            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
-#define TIM_OR_ITR1_RMP_0                    0x0400U            /*!<Bit 0 */
-#define TIM_OR_ITR1_RMP_1                    0x0800U            /*!<Bit 1 */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*         Universal Synchronous Asynchronous Receiver Transmitter            */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         0x0001U            /*!<Parity Error                 */
-#define  USART_SR_FE                         0x0002U            /*!<Framing Error                */
-#define  USART_SR_NE                         0x0004U            /*!<Noise Error Flag             */
-#define  USART_SR_ORE                        0x0008U            /*!<OverRun Error                */
-#define  USART_SR_IDLE                       0x0010U            /*!<IDLE line detected           */
-#define  USART_SR_RXNE                       0x0020U            /*!<Read Data Register Not Empty */
-#define  USART_SR_TC                         0x0040U            /*!<Transmission Complete        */
-#define  USART_SR_TXE                        0x0080U            /*!<Transmit Data Register Empty */
-#define  USART_SR_LBD                        0x0100U            /*!<LIN Break Detection Flag     */
-#define  USART_SR_CTS                        0x0200U            /*!<CTS Flag                     */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         0x01FFU            /*!<Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_Fraction              0x000FU            /*!<Fraction of USARTDIV */
-#define  USART_BRR_DIV_Mantissa              0xFFF0U            /*!<Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       0x0001U            /*!<Send Break                             */
-#define  USART_CR1_RWU                       0x0002U            /*!<Receiver wakeup                        */
-#define  USART_CR1_RE                        0x0004U            /*!<Receiver Enable                        */
-#define  USART_CR1_TE                        0x0008U            /*!<Transmitter Enable                     */
-#define  USART_CR1_IDLEIE                    0x0010U            /*!<IDLE Interrupt Enable                  */
-#define  USART_CR1_RXNEIE                    0x0020U            /*!<RXNE Interrupt Enable                  */
-#define  USART_CR1_TCIE                      0x0040U            /*!<Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     0x0080U            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PEIE                      0x0100U            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PS                        0x0200U            /*!<Parity Selection                       */
-#define  USART_CR1_PCE                       0x0400U            /*!<Parity Control Enable                  */
-#define  USART_CR1_WAKE                      0x0800U            /*!<Wakeup method                          */
-#define  USART_CR1_M                         0x1000U            /*!<Word length                            */
-#define  USART_CR1_UE                        0x2000U            /*!<USART Enable                           */
-#define  USART_CR1_OVER8                     0x8000U            /*!<USART Oversampling by 8 enable         */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       0x000FU            /*!<Address of the USART node            */
-#define  USART_CR2_LBDL                      0x0020U            /*!<LIN Break Detection Length           */
-#define  USART_CR2_LBDIE                     0x0040U            /*!<LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      0x0100U            /*!<Last Bit Clock pulse                 */
-#define  USART_CR2_CPHA                      0x0200U            /*!<Clock Phase                          */
-#define  USART_CR2_CPOL                      0x0400U            /*!<Clock Polarity                       */
-#define  USART_CR2_CLKEN                     0x0800U            /*!<Clock Enable                         */
-
-#define  USART_CR2_STOP                      0x3000U            /*!<STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    0x1000U            /*!<Bit 0 */
-#define  USART_CR2_STOP_1                    0x2000U            /*!<Bit 1 */
-
-#define  USART_CR2_LINEN                     0x4000U            /*!<LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       0x0001U            /*!<Error Interrupt Enable      */
-#define  USART_CR3_IREN                      0x0002U            /*!<IrDA mode Enable            */
-#define  USART_CR3_IRLP                      0x0004U            /*!<IrDA Low-Power              */
-#define  USART_CR3_HDSEL                     0x0008U            /*!<Half-Duplex Selection       */
-#define  USART_CR3_NACK                      0x0010U            /*!<Smartcard NACK enable       */
-#define  USART_CR3_SCEN                      0x0020U            /*!<Smartcard mode enable       */
-#define  USART_CR3_DMAR                      0x0040U            /*!<DMA Enable Receiver         */
-#define  USART_CR3_DMAT                      0x0080U            /*!<DMA Enable Transmitter      */
-#define  USART_CR3_RTSE                      0x0100U            /*!<RTS Enable                  */
-#define  USART_CR3_CTSE                      0x0200U            /*!<CTS Enable                  */
-#define  USART_CR3_CTSIE                     0x0400U            /*!<CTS Interrupt Enable        */
-#define  USART_CR3_ONEBIT                    0x0800U            /*!<USART One bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      0x00FFU            /*!<PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    0x0001U            /*!<Bit 0 */
-#define  USART_GTPR_PSC_1                    0x0002U            /*!<Bit 1 */
-#define  USART_GTPR_PSC_2                    0x0004U            /*!<Bit 2 */
-#define  USART_GTPR_PSC_3                    0x0008U            /*!<Bit 3 */
-#define  USART_GTPR_PSC_4                    0x0010U            /*!<Bit 4 */
-#define  USART_GTPR_PSC_5                    0x0020U            /*!<Bit 5 */
-#define  USART_GTPR_PSC_6                    0x0040U            /*!<Bit 6 */
-#define  USART_GTPR_PSC_7                    0x0080U            /*!<Bit 7 */
-
-#define  USART_GTPR_GT                       0xFF00U            /*!<Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Window WATCHDOG                                 */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           0x7FU               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T_0                         0x01U               /*!<Bit 0 */
-#define  WWDG_CR_T_1                         0x02U               /*!<Bit 1 */
-#define  WWDG_CR_T_2                         0x04U               /*!<Bit 2 */
-#define  WWDG_CR_T_3                         0x08U               /*!<Bit 3 */
-#define  WWDG_CR_T_4                         0x10U               /*!<Bit 4 */
-#define  WWDG_CR_T_5                         0x20U               /*!<Bit 5 */
-#define  WWDG_CR_T_6                         0x40U               /*!<Bit 6 */
-/* Legacy defines */
-#define  WWDG_CR_T0                          WWDG_CR_T_0
-#define  WWDG_CR_T1                          WWDG_CR_T_1
-#define  WWDG_CR_T2                          WWDG_CR_T_2
-#define  WWDG_CR_T3                          WWDG_CR_T_3
-#define  WWDG_CR_T4                          WWDG_CR_T_4
-#define  WWDG_CR_T5                          WWDG_CR_T_5
-#define  WWDG_CR_T6                          WWDG_CR_T_6
-
-#define  WWDG_CR_WDGA                        0x80U               /*!<Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          0x007FU            /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W_0                        0x0001U            /*!<Bit 0 */
-#define  WWDG_CFR_W_1                        0x0002U            /*!<Bit 1 */
-#define  WWDG_CFR_W_2                        0x0004U            /*!<Bit 2 */
-#define  WWDG_CFR_W_3                        0x0008U            /*!<Bit 3 */
-#define  WWDG_CFR_W_4                        0x0010U            /*!<Bit 4 */
-#define  WWDG_CFR_W_5                        0x0020U            /*!<Bit 5 */
-#define  WWDG_CFR_W_6                        0x0040U            /*!<Bit 6 */
-/* Legacy defines */
-#define  WWDG_CFR_W0                         WWDG_CFR_W_0
-#define  WWDG_CFR_W1                         WWDG_CFR_W_1
-#define  WWDG_CFR_W2                         WWDG_CFR_W_2
-#define  WWDG_CFR_W3                         WWDG_CFR_W_3
-#define  WWDG_CFR_W4                         WWDG_CFR_W_4
-#define  WWDG_CFR_W5                         WWDG_CFR_W_5
-#define  WWDG_CFR_W6                         WWDG_CFR_W_6
-
-#define  WWDG_CFR_WDGTB                      0x0180U            /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB_0                    0x0080U            /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB_1                    0x0100U            /*!<Bit 1 */
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
-
-#define  WWDG_CFR_EWI                        0x0200U            /*!<Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        0x01U               /*!<Early Wakeup Interrupt Flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                DBG                                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
-#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
-
-/********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
-#define  DBGMCU_CR_DBG_STOP                  0x00000002U
-#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
-#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
-
-#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
-#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U/*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U/*!<Bit 1 */
-
-/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            0x00000001U
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            0x00000002U
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            0x00000004U
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            0x00000020U
-#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           0x00000040U
-#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           0x00000080U
-#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           0x00000100U
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
-#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
-/* Old IWDGSTOP bit definition, maintained for legacy purpose */
-#define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
-
-/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        0x00000001U
-#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        0x00000002U
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        0x00010000U
-#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       0x00020000U
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       0x00040000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                Ethernet MAC Registers bits definitions                     */
-/*                                                                            */
-/******************************************************************************/
-/* Bit definition for Ethernet MAC Control Register register */
-#define ETH_MACCR_WD      0x00800000U  /* Watchdog disable */
-#define ETH_MACCR_JD      0x00400000U  /* Jabber disable */
-#define ETH_MACCR_IFG     0x000E0000U  /* Inter-frame gap */
-#define ETH_MACCR_IFG_96Bit     0x00000000U  /* Minimum IFG between frames during transmission is 96Bit */
-  #define ETH_MACCR_IFG_88Bit     0x00020000U  /* Minimum IFG between frames during transmission is 88Bit */
-  #define ETH_MACCR_IFG_80Bit     0x00040000U  /* Minimum IFG between frames during transmission is 80Bit */
-  #define ETH_MACCR_IFG_72Bit     0x00060000U  /* Minimum IFG between frames during transmission is 72Bit */
-  #define ETH_MACCR_IFG_64Bit     0x00080000U  /* Minimum IFG between frames during transmission is 64Bit */        
-  #define ETH_MACCR_IFG_56Bit     0x000A0000U  /* Minimum IFG between frames during transmission is 56Bit */
-  #define ETH_MACCR_IFG_48Bit     0x000C0000U  /* Minimum IFG between frames during transmission is 48Bit */
-  #define ETH_MACCR_IFG_40Bit     0x000E0000U  /* Minimum IFG between frames during transmission is 40Bit */              
-#define ETH_MACCR_CSD     0x00010000U  /* Carrier sense disable (during transmission) */
-#define ETH_MACCR_FES     0x00004000U  /* Fast ethernet speed */
-#define ETH_MACCR_ROD     0x00002000U  /* Receive own disable */
-#define ETH_MACCR_LM      0x00001000U  /* loopback mode */
-#define ETH_MACCR_DM      0x00000800U  /* Duplex mode */
-#define ETH_MACCR_IPCO    0x00000400U  /* IP Checksum offload */
-#define ETH_MACCR_RD      0x00000200U  /* Retry disable */
-#define ETH_MACCR_APCS    0x00000080U  /* Automatic Pad/CRC stripping */
-#define ETH_MACCR_BL      0x00000060U  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
-                                                       a transmission attempt during retries after a collision: 0 =< r <2^k */
-  #define ETH_MACCR_BL_10    0x00000000U  /* k = min (n, 10) */
-  #define ETH_MACCR_BL_8     0x00000020U  /* k = min (n, 8) */
-  #define ETH_MACCR_BL_4     0x00000040U  /* k = min (n, 4) */
-  #define ETH_MACCR_BL_1     0x00000060U  /* k = min (n, 1) */ 
-#define ETH_MACCR_DC      0x00000010U  /* Defferal check */
-#define ETH_MACCR_TE      0x00000008U  /* Transmitter enable */
-#define ETH_MACCR_RE      0x00000004U  /* Receiver enable */
-
-/* Bit definition for Ethernet MAC Frame Filter Register */
-#define ETH_MACFFR_RA     0x80000000U  /* Receive all */ 
-#define ETH_MACFFR_HPF    0x00000400U  /* Hash or perfect filter */ 
-#define ETH_MACFFR_SAF    0x00000200U  /* Source address filter enable */ 
-#define ETH_MACFFR_SAIF   0x00000100U  /* SA inverse filtering */ 
-#define ETH_MACFFR_PCF    0x000000C0U  /* Pass control frames: 3 cases */
-  #define ETH_MACFFR_PCF_BlockAll                0x00000040U  /* MAC filters all control frames from reaching the application */
-  #define ETH_MACFFR_PCF_ForwardAll              0x00000080U  /* MAC forwards all control frames to application even if they fail the Address Filter */
-  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U  /* MAC forwards control frames that pass the Address Filter. */ 
-#define ETH_MACFFR_BFD    0x00000020U  /* Broadcast frame disable */ 
-#define ETH_MACFFR_PAM    0x00000010U  /* Pass all mutlicast */ 
-#define ETH_MACFFR_DAIF   0x00000008U  /* DA Inverse filtering */ 
-#define ETH_MACFFR_HM     0x00000004U  /* Hash multicast */ 
-#define ETH_MACFFR_HU     0x00000002U  /* Hash unicast */
-#define ETH_MACFFR_PM     0x00000001U  /* Promiscuous mode */
-
-/* Bit definition for Ethernet MAC Hash Table High Register */
-#define ETH_MACHTHR_HTH   0xFFFFFFFFU  /* Hash table high */
-
-/* Bit definition for Ethernet MAC Hash Table Low Register */
-#define ETH_MACHTLR_HTL   0xFFFFFFFFU  /* Hash table low */
-
-/* Bit definition for Ethernet MAC MII Address Register */
-#define ETH_MACMIIAR_PA   0x0000F800U  /* Physical layer address */ 
-#define ETH_MACMIIAR_MR   0x000007C0U  /* MII register in the selected PHY */ 
-#define ETH_MACMIIAR_CR   0x0000001CU  /* CR clock range: 6 cases */ 
-  #define ETH_MACMIIAR_CR_Div42   0x00000000U  /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
-  #define ETH_MACMIIAR_CR_Div62   0x00000004U  /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
-  #define ETH_MACMIIAR_CR_Div16   0x00000008U  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
-  #define ETH_MACMIIAR_CR_Div26   0x0000000CU  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
-  #define ETH_MACMIIAR_CR_Div102  0x00000010U  /* HCLK:150-168 MHz; MDC clock= HCLK/102 */  
-#define ETH_MACMIIAR_MW   0x00000002U  /* MII write */ 
-#define ETH_MACMIIAR_MB   0x00000001U  /* MII busy */ 
-  
-/* Bit definition for Ethernet MAC MII Data Register */
-#define ETH_MACMIIDR_MD   0x0000FFFFU  /* MII data: read/write data from/to PHY */
-
-/* Bit definition for Ethernet MAC Flow Control Register */
-#define ETH_MACFCR_PT     0xFFFF0000U  /* Pause time */
-#define ETH_MACFCR_ZQPD   0x00000080U  /* Zero-quanta pause disable */
-#define ETH_MACFCR_PLT    0x00000030U  /* Pause low threshold: 4 cases */
-  #define ETH_MACFCR_PLT_Minus4   0x00000000U  /* Pause time minus 4 slot times */
-  #define ETH_MACFCR_PLT_Minus28  0x00000010U  /* Pause time minus 28 slot times */
-  #define ETH_MACFCR_PLT_Minus144 0x00000020U  /* Pause time minus 144 slot times */
-  #define ETH_MACFCR_PLT_Minus256 0x00000030U  /* Pause time minus 256 slot times */      
-#define ETH_MACFCR_UPFD   0x00000008U  /* Unicast pause frame detect */
-#define ETH_MACFCR_RFCE   0x00000004U  /* Receive flow control enable */
-#define ETH_MACFCR_TFCE   0x00000002U  /* Transmit flow control enable */
-#define ETH_MACFCR_FCBBPA 0x00000001U  /* Flow control busy/backpressure activate */
-
-/* Bit definition for Ethernet MAC VLAN Tag Register */
-#define ETH_MACVLANTR_VLANTC 0x00010000U  /* 12-bit VLAN tag comparison */
-#define ETH_MACVLANTR_VLANTI 0x0000FFFFU  /* VLAN tag identifier (for receive frames) */
-
-/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ 
-#define ETH_MACRWUFFR_D   0xFFFFFFFFU  /* Wake-up frame filter register data */
-/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
-   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
-/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
-   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
-   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
-   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
-   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - 
-                              RSVD - Filter1 Command - RSVD - Filter0 Command
-   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
-   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
-   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
-
-/* Bit definition for Ethernet MAC PMT Control and Status Register */ 
-#define ETH_MACPMTCSR_WFFRPR 0x80000000U  /* Wake-Up Frame Filter Register Pointer Reset */
-#define ETH_MACPMTCSR_GU     0x00000200U  /* Global Unicast */
-#define ETH_MACPMTCSR_WFR    0x00000040U  /* Wake-Up Frame Received */
-#define ETH_MACPMTCSR_MPR    0x00000020U  /* Magic Packet Received */
-#define ETH_MACPMTCSR_WFE    0x00000004U  /* Wake-Up Frame Enable */
-#define ETH_MACPMTCSR_MPE    0x00000002U  /* Magic Packet Enable */
-#define ETH_MACPMTCSR_PD     0x00000001U  /* Power Down */
-
-/* Bit definition for Ethernet MAC Status Register */
-#define ETH_MACSR_TSTS      0x00000200U  /* Time stamp trigger status */
-#define ETH_MACSR_MMCTS     0x00000040U  /* MMC transmit status */
-#define ETH_MACSR_MMMCRS    0x00000020U  /* MMC receive status */
-#define ETH_MACSR_MMCS      0x00000010U  /* MMC status */
-#define ETH_MACSR_PMTS      0x00000008U  /* PMT status */
-
-/* Bit definition for Ethernet MAC Interrupt Mask Register */
-#define ETH_MACIMR_TSTIM     0x00000200U  /* Time stamp trigger interrupt mask */
-#define ETH_MACIMR_PMTIM     0x00000008U  /* PMT interrupt mask */
-
-/* Bit definition for Ethernet MAC Address0 High Register */
-#define ETH_MACA0HR_MACA0H   0x0000FFFFU  /* MAC address0 high */
-
-/* Bit definition for Ethernet MAC Address0 Low Register */
-#define ETH_MACA0LR_MACA0L   0xFFFFFFFFU  /* MAC address0 low */
-
-/* Bit definition for Ethernet MAC Address1 High Register */
-#define ETH_MACA1HR_AE       0x80000000U  /* Address enable */
-#define ETH_MACA1HR_SA       0x40000000U  /* Source address */
-#define ETH_MACA1HR_MBC      0x3F000000U  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
-  #define ETH_MACA1HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA1HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA1HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA1HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA1HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA1HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [7:0] */ 
-#define ETH_MACA1HR_MACA1H   0x0000FFFFU  /* MAC address1 high */
-
-/* Bit definition for Ethernet MAC Address1 Low Register */
-#define ETH_MACA1LR_MACA1L   0xFFFFFFFFU  /* MAC address1 low */
-
-/* Bit definition for Ethernet MAC Address2 High Register */
-#define ETH_MACA2HR_AE       0x80000000U  /* Address enable */
-#define ETH_MACA2HR_SA       0x40000000U  /* Source address */
-#define ETH_MACA2HR_MBC      0x3F000000U  /* Mask byte control */
-  #define ETH_MACA2HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA2HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA2HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA2HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA2HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA2HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA2HR_MACA2H   0x0000FFFFU  /* MAC address1 high */
-
-/* Bit definition for Ethernet MAC Address2 Low Register */
-#define ETH_MACA2LR_MACA2L   0xFFFFFFFFU  /* MAC address2 low */
-
-/* Bit definition for Ethernet MAC Address3 High Register */
-#define ETH_MACA3HR_AE       0x80000000U  /* Address enable */
-#define ETH_MACA3HR_SA       0x40000000U  /* Source address */
-#define ETH_MACA3HR_MBC      0x3F000000U  /* Mask byte control */
-  #define ETH_MACA3HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA3HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA3HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA3HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA3HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA3HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA3HR_MACA3H   0x0000FFFFU  /* MAC address3 high */
-
-/* Bit definition for Ethernet MAC Address3 Low Register */
-#define ETH_MACA3LR_MACA3L   0xFFFFFFFFU  /* MAC address3 low */
-
-/******************************************************************************/
-/*                Ethernet MMC Registers bits definition                      */
-/******************************************************************************/
-
-/* Bit definition for Ethernet MMC Contol Register */
-#define ETH_MMCCR_MCFHP      0x00000020U  /* MMC counter Full-Half preset */
-#define ETH_MMCCR_MCP        0x00000010U  /* MMC counter preset */
-#define ETH_MMCCR_MCF        0x00000008U  /* MMC Counter Freeze */
-#define ETH_MMCCR_ROR        0x00000004U  /* Reset on Read */
-#define ETH_MMCCR_CSR        0x00000002U  /* Counter Stop Rollover */
-#define ETH_MMCCR_CR         0x00000001U  /* Counters Reset */
-
-/* Bit definition for Ethernet MMC Receive Interrupt Register */
-#define ETH_MMCRIR_RGUFS     0x00020000U  /* Set when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIR_RFAES     0x00000040U  /* Set when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIR_RFCES     0x00000020U  /* Set when Rx crc error counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmit Interrupt Register */
-#define ETH_MMCTIR_TGFS      0x00200000U  /* Set when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFMSCS   0x00008000U  /* Set when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFSCS    0x00004000U  /* Set when Tx good single col counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
-#define ETH_MMCRIMR_RGUFM    0x00020000U  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFAEM    0x00000040U  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFCEM    0x00000020U  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
-#define ETH_MMCTIMR_TGFM     0x00200000U  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFMSCM  0x00008000U  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFSCM   0x00004000U  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
-#define ETH_MMCTGFSCCR_TGFSCC     0xFFFFFFFFU  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
-#define ETH_MMCTGFMSCCR_TGFMSCC   0xFFFFFFFFU  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
-#define ETH_MMCTGFCR_TGFC    0xFFFFFFFFU  /* Number of good frames transmitted. */
-
-/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
-#define ETH_MMCRFCECR_RFCEC  0xFFFFFFFFU  /* Number of frames received with CRC error. */
-
-/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
-#define ETH_MMCRFAECR_RFAEC  0xFFFFFFFFU  /* Number of frames received with alignment (dribble) error */
-
-/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
-#define ETH_MMCRGUFCR_RGUFC  0xFFFFFFFFU  /* Number of good unicast frames received. */
-
-/******************************************************************************/
-/*               Ethernet PTP Registers bits definition                       */
-/******************************************************************************/
-
-/* Bit definition for Ethernet PTP Time Stamp Contol Register */
-#define ETH_PTPTSCR_TSCNT       0x00030000U  /* Time stamp clock node type */
-#define ETH_PTPTSSR_TSSMRME     0x00008000U  /* Time stamp snapshot for message relevant to master enable */
-#define ETH_PTPTSSR_TSSEME      0x00004000U  /* Time stamp snapshot for event message enable */
-#define ETH_PTPTSSR_TSSIPV4FE   0x00002000U  /* Time stamp snapshot for IPv4 frames enable */
-#define ETH_PTPTSSR_TSSIPV6FE   0x00001000U  /* Time stamp snapshot for IPv6 frames enable */
-#define ETH_PTPTSSR_TSSPTPOEFE  0x00000800U  /* Time stamp snapshot for PTP over ethernet frames enable */
-#define ETH_PTPTSSR_TSPTPPSV2E  0x00000400U  /* Time stamp PTP packet snooping for version2 format enable */
-#define ETH_PTPTSSR_TSSSR       0x00000200U  /* Time stamp Sub-seconds rollover */
-#define ETH_PTPTSSR_TSSARFE     0x00000100U  /* Time stamp snapshot for all received frames enable */
-
-#define ETH_PTPTSCR_TSARU    0x00000020U  /* Addend register update */
-#define ETH_PTPTSCR_TSITE    0x00000010U  /* Time stamp interrupt trigger enable */
-#define ETH_PTPTSCR_TSSTU    0x00000008U  /* Time stamp update */
-#define ETH_PTPTSCR_TSSTI    0x00000004U  /* Time stamp initialize */
-#define ETH_PTPTSCR_TSFCU    0x00000002U  /* Time stamp fine or coarse update */
-#define ETH_PTPTSCR_TSE      0x00000001U  /* Time stamp enable */
-
-/* Bit definition for Ethernet PTP Sub-Second Increment Register */
-#define ETH_PTPSSIR_STSSI    0x000000FFU  /* System time Sub-second increment value */
-
-/* Bit definition for Ethernet PTP Time Stamp High Register */
-#define ETH_PTPTSHR_STS      0xFFFFFFFFU  /* System Time second */
-
-/* Bit definition for Ethernet PTP Time Stamp Low Register */
-#define ETH_PTPTSLR_STPNS    0x80000000U  /* System Time Positive or negative time */
-#define ETH_PTPTSLR_STSS     0x7FFFFFFFU  /* System Time sub-seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp High Update Register */
-#define ETH_PTPTSHUR_TSUS    0xFFFFFFFFU  /* Time stamp update seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
-#define ETH_PTPTSLUR_TSUPNS  0x80000000U  /* Time stamp update Positive or negative time */
-#define ETH_PTPTSLUR_TSUSS   0x7FFFFFFFU  /* Time stamp update sub-seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp Addend Register */
-#define ETH_PTPTSAR_TSA      0xFFFFFFFFU  /* Time stamp addend */
-
-/* Bit definition for Ethernet PTP Target Time High Register */
-#define ETH_PTPTTHR_TTSH     0xFFFFFFFFU  /* Target time stamp high */
-
-/* Bit definition for Ethernet PTP Target Time Low Register */
-#define ETH_PTPTTLR_TTSL     0xFFFFFFFFU  /* Target time stamp low */
-
-/* Bit definition for Ethernet PTP Time Stamp Status Register */
-#define ETH_PTPTSSR_TSTTR    0x00000020U  /* Time stamp target time reached */
-#define ETH_PTPTSSR_TSSO     0x00000010U  /* Time stamp seconds overflow */
-
-/******************************************************************************/
-/*                 Ethernet DMA Registers bits definition                     */
-/******************************************************************************/
-
-/* Bit definition for Ethernet DMA Bus Mode Register */
-#define ETH_DMABMR_AAB       0x02000000U  /* Address-Aligned beats */
-#define ETH_DMABMR_FPM        0x01000000U  /* 4xPBL mode */
-#define ETH_DMABMR_USP       0x00800000U  /* Use separate PBL */
-#define ETH_DMABMR_RDP       0x007E0000U  /* RxDMA PBL */
-  #define ETH_DMABMR_RDP_1Beat    0x00020000U  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
-  #define ETH_DMABMR_RDP_2Beat    0x00040000U  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
-  #define ETH_DMABMR_RDP_4Beat    0x00080000U  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-  #define ETH_DMABMR_RDP_8Beat    0x00100000U  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-  #define ETH_DMABMR_RDP_16Beat   0x00200000U  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-  #define ETH_DMABMR_RDP_32Beat   0x00400000U  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */                
-  #define ETH_DMABMR_RDP_4xPBL_4Beat   0x01020000U  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-  #define ETH_DMABMR_RDP_4xPBL_8Beat   0x01040000U  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-  #define ETH_DMABMR_RDP_4xPBL_16Beat  0x01080000U  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-  #define ETH_DMABMR_RDP_4xPBL_32Beat  0x01100000U  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
-  #define ETH_DMABMR_RDP_4xPBL_64Beat  0x01200000U  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
-  #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */  
-#define ETH_DMABMR_FB        0x00010000U  /* Fixed Burst */
-#define ETH_DMABMR_RTPR      0x0000C000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_1_1     0x00000000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_2_1     0x00004000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_3_1     0x00008000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_4_1     0x0000C000U  /* Rx Tx priority ratio */  
-#define ETH_DMABMR_PBL    0x00003F00U  /* Programmable burst length */
-  #define ETH_DMABMR_PBL_1Beat    0x00000100U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
-  #define ETH_DMABMR_PBL_2Beat    0x00000200U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
-  #define ETH_DMABMR_PBL_4Beat    0x00000400U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-  #define ETH_DMABMR_PBL_8Beat    0x00000800U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-  #define ETH_DMABMR_PBL_16Beat   0x00001000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-  #define ETH_DMABMR_PBL_32Beat   0x00002000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
-  #define ETH_DMABMR_PBL_4xPBL_4Beat   0x01000100U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-  #define ETH_DMABMR_PBL_4xPBL_8Beat   0x01000200U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-  #define ETH_DMABMR_PBL_4xPBL_16Beat  0x01000400U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-  #define ETH_DMABMR_PBL_4xPBL_32Beat  0x01000800U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
-  #define ETH_DMABMR_PBL_4xPBL_64Beat  0x01001000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
-  #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
-#define ETH_DMABMR_EDE       0x00000080U  /* Enhanced Descriptor Enable */
-#define ETH_DMABMR_DSL       0x0000007CU  /* Descriptor Skip Length */
-#define ETH_DMABMR_DA        0x00000002U  /* DMA arbitration scheme */
-#define ETH_DMABMR_SR        0x00000001U  /* Software reset */
-
-/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
-#define ETH_DMATPDR_TPD      0xFFFFFFFFU  /* Transmit poll demand */
-
-/* Bit definition for Ethernet DMA Receive Poll Demand Register */
-#define ETH_DMARPDR_RPD      0xFFFFFFFFU  /* Receive poll demand  */
-
-/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
-#define ETH_DMARDLAR_SRL     0xFFFFFFFFU  /* Start of receive list */
-
-/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
-#define ETH_DMATDLAR_STL     0xFFFFFFFFU  /* Start of transmit list */
-
-/* Bit definition for Ethernet DMA Status Register */
-#define ETH_DMASR_TSTS       0x20000000U  /* Time-stamp trigger status */
-#define ETH_DMASR_PMTS       0x10000000U  /* PMT status */
-#define ETH_DMASR_MMCS       0x08000000U  /* MMC status */
-#define ETH_DMASR_EBS        0x03800000U  /* Error bits status */
-  /* combination with EBS[2:0] for GetFlagStatus function */
-  #define ETH_DMASR_EBS_DescAccess      0x02000000U  /* Error bits 0-data buffer, 1-desc. access */
-  #define ETH_DMASR_EBS_ReadTransf      0x01000000U  /* Error bits 0-write trnsf, 1-read transfr */
-  #define ETH_DMASR_EBS_DataTransfTx    0x00800000U  /* Error bits 0-Rx DMA, 1-Tx DMA */
-#define ETH_DMASR_TPS         0x00700000U  /* Transmit process state */
-  #define ETH_DMASR_TPS_Stopped         0x00000000U  /* Stopped - Reset or Stop Tx Command issued  */
-  #define ETH_DMASR_TPS_Fetching        0x00100000U  /* Running - fetching the Tx descriptor */
-  #define ETH_DMASR_TPS_Waiting         0x00200000U  /* Running - waiting for status */
-  #define ETH_DMASR_TPS_Reading         0x00300000U  /* Running - reading the data from host memory */
-  #define ETH_DMASR_TPS_Suspended       0x00600000U  /* Suspended - Tx Descriptor unavailabe */
-  #define ETH_DMASR_TPS_Closing         0x00700000U  /* Running - closing Rx descriptor */
-#define ETH_DMASR_RPS         0x000E0000U  /* Receive process state */
-  #define ETH_DMASR_RPS_Stopped         0x00000000U  /* Stopped - Reset or Stop Rx Command issued */
-  #define ETH_DMASR_RPS_Fetching        0x00020000U  /* Running - fetching the Rx descriptor */
-  #define ETH_DMASR_RPS_Waiting         0x00060000U  /* Running - waiting for packet */
-  #define ETH_DMASR_RPS_Suspended       0x00080000U  /* Suspended - Rx Descriptor unavailable */
-  #define ETH_DMASR_RPS_Closing         0x000A0000U  /* Running - closing descriptor */
-  #define ETH_DMASR_RPS_Queuing         0x000E0000U  /* Running - queuing the recieve frame into host memory */
-#define ETH_DMASR_NIS        0x00010000U  /* Normal interrupt summary */
-#define ETH_DMASR_AIS        0x00008000U  /* Abnormal interrupt summary */
-#define ETH_DMASR_ERS        0x00004000U  /* Early receive status */
-#define ETH_DMASR_FBES       0x00002000U  /* Fatal bus error status */
-#define ETH_DMASR_ETS        0x00000400U  /* Early transmit status */
-#define ETH_DMASR_RWTS       0x00000200U  /* Receive watchdog timeout status */
-#define ETH_DMASR_RPSS       0x00000100U  /* Receive process stopped status */
-#define ETH_DMASR_RBUS       0x00000080U  /* Receive buffer unavailable status */
-#define ETH_DMASR_RS         0x00000040U  /* Receive status */
-#define ETH_DMASR_TUS        0x00000020U  /* Transmit underflow status */
-#define ETH_DMASR_ROS        0x00000010U  /* Receive overflow status */
-#define ETH_DMASR_TJTS       0x00000008U  /* Transmit jabber timeout status */
-#define ETH_DMASR_TBUS       0x00000004U  /* Transmit buffer unavailable status */
-#define ETH_DMASR_TPSS       0x00000002U  /* Transmit process stopped status */
-#define ETH_DMASR_TS         0x00000001U  /* Transmit status */
-
-/* Bit definition for Ethernet DMA Operation Mode Register */
-#define ETH_DMAOMR_DTCEFD    0x04000000U  /* Disable Dropping of TCP/IP checksum error frames */
-#define ETH_DMAOMR_RSF       0x02000000U  /* Receive store and forward */
-#define ETH_DMAOMR_DFRF      0x01000000U  /* Disable flushing of received frames */
-#define ETH_DMAOMR_TSF       0x00200000U  /* Transmit store and forward */
-#define ETH_DMAOMR_FTF       0x00100000U  /* Flush transmit FIFO */
-#define ETH_DMAOMR_TTC       0x0001C000U  /* Transmit threshold control */
-  #define ETH_DMAOMR_TTC_64Bytes       0x00000000U  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
-  #define ETH_DMAOMR_TTC_128Bytes      0x00004000U  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
-  #define ETH_DMAOMR_TTC_192Bytes      0x00008000U  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
-  #define ETH_DMAOMR_TTC_256Bytes      0x0000C000U  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
-  #define ETH_DMAOMR_TTC_40Bytes       0x00010000U  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
-  #define ETH_DMAOMR_TTC_32Bytes       0x00014000U  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
-  #define ETH_DMAOMR_TTC_24Bytes       0x00018000U  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
-  #define ETH_DMAOMR_TTC_16Bytes       0x0001C000U  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
-#define ETH_DMAOMR_ST        0x00002000U  /* Start/stop transmission command */
-#define ETH_DMAOMR_FEF       0x00000080U  /* Forward error frames */
-#define ETH_DMAOMR_FUGF      0x00000040U  /* Forward undersized good frames */
-#define ETH_DMAOMR_RTC       0x00000018U  /* receive threshold control */
-  #define ETH_DMAOMR_RTC_64Bytes       0x00000000U  /* threshold level of the MTL Receive FIFO is 64 Bytes */
-  #define ETH_DMAOMR_RTC_32Bytes       0x00000008U  /* threshold level of the MTL Receive FIFO is 32 Bytes */
-  #define ETH_DMAOMR_RTC_96Bytes       0x00000010U  /* threshold level of the MTL Receive FIFO is 96 Bytes */
-  #define ETH_DMAOMR_RTC_128Bytes      0x00000018U  /* threshold level of the MTL Receive FIFO is 128 Bytes */
-#define ETH_DMAOMR_OSF       0x00000004U  /* operate on second frame */
-#define ETH_DMAOMR_SR        0x00000002U  /* Start/stop receive */
-
-/* Bit definition for Ethernet DMA Interrupt Enable Register */
-#define ETH_DMAIER_NISE      0x00010000U  /* Normal interrupt summary enable */
-#define ETH_DMAIER_AISE      0x00008000U  /* Abnormal interrupt summary enable */
-#define ETH_DMAIER_ERIE      0x00004000U  /* Early receive interrupt enable */
-#define ETH_DMAIER_FBEIE     0x00002000U  /* Fatal bus error interrupt enable */
-#define ETH_DMAIER_ETIE      0x00000400U  /* Early transmit interrupt enable */
-#define ETH_DMAIER_RWTIE     0x00000200U  /* Receive watchdog timeout interrupt enable */
-#define ETH_DMAIER_RPSIE     0x00000100U  /* Receive process stopped interrupt enable */
-#define ETH_DMAIER_RBUIE     0x00000080U  /* Receive buffer unavailable interrupt enable */
-#define ETH_DMAIER_RIE       0x00000040U  /* Receive interrupt enable */
-#define ETH_DMAIER_TUIE      0x00000020U  /* Transmit Underflow interrupt enable */
-#define ETH_DMAIER_ROIE      0x00000010U  /* Receive Overflow interrupt enable */
-#define ETH_DMAIER_TJTIE     0x00000008U  /* Transmit jabber timeout interrupt enable */
-#define ETH_DMAIER_TBUIE     0x00000004U  /* Transmit buffer unavailable interrupt enable */
-#define ETH_DMAIER_TPSIE     0x00000002U  /* Transmit process stopped interrupt enable */
-#define ETH_DMAIER_TIE       0x00000001U  /* Transmit interrupt enable */
-
-/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
-#define ETH_DMAMFBOCR_OFOC   0x10000000U  /* Overflow bit for FIFO overflow counter */
-#define ETH_DMAMFBOCR_MFA    0x0FFE0000U  /* Number of frames missed by the application */
-#define ETH_DMAMFBOCR_OMFC   0x00010000U  /* Overflow bit for missed frame counter */
-#define ETH_DMAMFBOCR_MFC    0x0000FFFFU  /* Number of frames missed by the controller */
-
-/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
-#define ETH_DMACHTDR_HTDAP   0xFFFFFFFFU  /* Host transmit descriptor address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
-#define ETH_DMACHRDR_HRDAP   0xFFFFFFFFU  /* Host receive descriptor address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
-#define ETH_DMACHTBAR_HTBAP  0xFFFFFFFFU  /* Host transmit buffer address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
-#define ETH_DMACHRBAR_HRBAP  0xFFFFFFFFU  /* Host receive buffer address pointer */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                       USB_OTG			                        */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/
-#define USB_OTG_GOTGCTL_SRQSCS                  0x00000001U            /*!< Session request success  */
-#define USB_OTG_GOTGCTL_SRQ                     0x00000002U            /*!< Session request          */
-#define USB_OTG_GOTGCTL_HNGSCS                  0x00000100U            /*!< Host negotiation success */
-#define USB_OTG_GOTGCTL_HNPRQ                   0x00000200U            /*!< HNP request              */
-#define USB_OTG_GOTGCTL_HSHNPEN                 0x00000400U            /*!< Host set HNP enable      */
-#define USB_OTG_GOTGCTL_DHNPEN                  0x00000800U            /*!< Device HNP enabled       */
-#define USB_OTG_GOTGCTL_CIDSTS                  0x00010000U            /*!< Connector ID status      */
-#define USB_OTG_GOTGCTL_DBCT                    0x00020000U            /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD                   0x00040000U            /*!< A-session valid          */
-#define USB_OTG_GOTGCTL_BSVLD                   0x00080000U            /*!< B-session valid          */
-
-/********************  Bit definition forUSB_OTG_HCFG register  ********************/
-
-#define USB_OTG_HCFG_FSLSPCS                 0x00000003U            /*!< FS/LS PHY clock select  */
-#define USB_OTG_HCFG_FSLSPCS_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCFG_FSLSPCS_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCFG_FSLSS                   0x00000004U            /*!< FS- and LS-only support */
-
-/********************  Bit definition forUSB_OTG_DCFG register  ********************/
-
-#define USB_OTG_DCFG_DSPD                    0x00000003U            /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                  0x00000001U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DSPD_1                  0x00000002U            /*!<Bit 1 */
-#define USB_OTG_DCFG_NZLSOHSK                0x00000004U            /*!< Nonzero-length status OUT handshake */
-
-#define USB_OTG_DCFG_DAD                     0x000007F0U            /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                   0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DAD_1                   0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCFG_DAD_2                   0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCFG_DAD_3                   0x00000080U            /*!<Bit 3 */
-#define USB_OTG_DCFG_DAD_4                   0x00000100U            /*!<Bit 4 */
-#define USB_OTG_DCFG_DAD_5                   0x00000200U            /*!<Bit 5 */
-#define USB_OTG_DCFG_DAD_6                   0x00000400U            /*!<Bit 6 */
-
-#define USB_OTG_DCFG_PFIVL                   0x00001800U            /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PFIVL_1                 0x00001000U            /*!<Bit 1 */
-
-#define USB_OTG_DCFG_PERSCHIVL               0x03000000U            /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0             0x01000000U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PERSCHIVL_1             0x02000000U            /*!<Bit 1 */
-
-/********************  Bit definition forUSB_OTG_PCGCR register  ********************/
-#define USB_OTG_PCGCR_STPPCLK                 0x00000001U            /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK                0x00000002U            /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP                 0x00000010U            /*!< PHY suspended */
-
-/********************  Bit definition forUSB_OTG_GOTGINT register  ********************/
-#define USB_OTG_GOTGINT_SEDET                   0x00000004U            /*!< Session end detected                   */
-#define USB_OTG_GOTGINT_SRSSCHG                 0x00000100U            /*!< Session request success status change  */
-#define USB_OTG_GOTGINT_HNSSCHG                 0x00000200U            /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET                  0x00020000U            /*!< Host negotiation detected              */
-#define USB_OTG_GOTGINT_ADTOCHG                 0x00040000U            /*!< A-device timeout change                */
-#define USB_OTG_GOTGINT_DBCDNE                  0x00080000U            /*!< Debounce done                          */
-
-/********************  Bit definition forUSB_OTG_DCTL register  ********************/
-#define USB_OTG_DCTL_RWUSIG                  0x00000001U            /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS                    0x00000002U            /*!< Soft disconnect         */
-#define USB_OTG_DCTL_GINSTS                  0x00000004U            /*!< Global IN NAK status    */
-#define USB_OTG_DCTL_GONSTS                  0x00000008U            /*!< Global OUT NAK status   */
-
-#define USB_OTG_DCTL_TCTL                    0x00000070U            /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                  0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCTL_TCTL_1                  0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCTL_TCTL_2                  0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCTL_SGINAK                  0x00000080U            /*!< Set global IN NAK         */
-#define USB_OTG_DCTL_CGINAK                  0x00000100U            /*!< Clear global IN NAK       */
-#define USB_OTG_DCTL_SGONAK                  0x00000200U            /*!< Set global OUT NAK        */
-#define USB_OTG_DCTL_CGONAK                  0x00000400U            /*!< Clear global OUT NAK      */
-#define USB_OTG_DCTL_POPRGDNE                0x00000800U            /*!< Power-on programming done */
-
-/********************  Bit definition forUSB_OTG_HFIR register  ********************/
-#define USB_OTG_HFIR_FRIVL                   0x0000FFFFU            /*!< Frame interval */
-
-/********************  Bit definition forUSB_OTG_HFNUM register  ********************/
-#define USB_OTG_HFNUM_FRNUM                   0x0000FFFFU            /*!< Frame number         */
-#define USB_OTG_HFNUM_FTREM                   0xFFFF0000U            /*!< Frame time remaining */
-
-/********************  Bit definition forUSB_OTG_DSTS register  ********************/
-#define USB_OTG_DSTS_SUSPSTS                 0x00000001U            /*!< Suspend status   */
-
-#define USB_OTG_DSTS_ENUMSPD                 0x00000006U            /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_DSTS_ENUMSPD_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_DSTS_EERR                    0x00000008U            /*!< Erratic error     */
-#define USB_OTG_DSTS_FNSOF                   0x003FFF00U            /*!< Frame number of the received SOF */
-
-/********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/
-#define USB_OTG_GAHBCFG_GINT                    0x00000001U            /*!< Global interrupt mask */
-
-#define USB_OTG_GAHBCFG_HBSTLEN                 0x0000001EU            /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_GAHBCFG_HBSTLEN_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_GAHBCFG_HBSTLEN_2               0x00000008U            /*!<Bit 2 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3               0x00000010U            /*!<Bit 3 */
-#define USB_OTG_GAHBCFG_DMAEN                   0x00000020U            /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL                 0x00000080U            /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL                0x00000100U            /*!< Periodic TxFIFO empty level */
-
-/********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/
-
-#define USB_OTG_GUSBCFG_TOCAL                   0x00000007U            /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TOCAL_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TOCAL_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_PHYSEL                  0x00000040U            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP                  0x00000100U            /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP                  0x00000200U            /*!< HNP-capable */
-
-#define USB_OTG_GUSBCFG_TRDT                    0x00003C00U            /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                  0x00000400U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TRDT_1                  0x00000800U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TRDT_2                  0x00001000U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_TRDT_3                  0x00002000U            /*!<Bit 3 */
-#define USB_OTG_GUSBCFG_PHYLPCS                 0x00008000U            /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS                0x00020000U            /*!< ULPI FS/LS select               */
-#define USB_OTG_GUSBCFG_ULPIAR                  0x00040000U            /*!< ULPI Auto-resume                */
-#define USB_OTG_GUSBCFG_ULPICSM                 0x00080000U            /*!< ULPI Clock SuspendM             */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD              0x00100000U            /*!< ULPI External VBUS Drive        */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI              0x00200000U            /*!< ULPI external VBUS indicator    */
-#define USB_OTG_GUSBCFG_TSDPS                   0x00400000U            /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI                    0x00800000U            /*!< Indicator complement            */
-#define USB_OTG_GUSBCFG_PTCI                    0x01000000U            /*!< Indicator pass through          */
-#define USB_OTG_GUSBCFG_ULPIIPD                 0x02000000U            /*!< ULPI interface protect disable  */
-#define USB_OTG_GUSBCFG_FHMOD                   0x20000000U            /*!< Forced host mode                */
-#define USB_OTG_GUSBCFG_FDMOD                   0x40000000U            /*!< Forced peripheral mode          */
-#define USB_OTG_GUSBCFG_CTXPKT                  0x80000000U            /*!< Corrupt Tx packet               */
-
-/********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
-#define USB_OTG_GRSTCTL_CSRST                   0x00000001U            /*!< Core soft reset          */
-#define USB_OTG_GRSTCTL_HSRST                   0x00000002U            /*!< HCLK soft reset          */
-#define USB_OTG_GRSTCTL_FCRST                   0x00000004U            /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH                 0x00000010U            /*!< RxFIFO flush             */
-#define USB_OTG_GRSTCTL_TXFFLSH                 0x00000020U            /*!< TxFIFO flush             */
-
-#define USB_OTG_GRSTCTL_TXFNUM                  0x000007C0U            /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                0x00000040U            /*!<Bit 0 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                0x00000080U            /*!<Bit 1 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                0x00000100U            /*!<Bit 2 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                0x00000200U            /*!<Bit 3 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                0x00000400U            /*!<Bit 4 */
-#define USB_OTG_GRSTCTL_DMAREQ                  0x40000000U            /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL                  0x80000000U            /*!< AHB master idle */
-
-/********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/
-#define USB_OTG_DIEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask                 */
-#define USB_OTG_DIEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask                  */
-#define USB_OTG_DIEPMSK_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask          */
-#define USB_OTG_DIEPMSK_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask           */
-#define USB_OTG_DIEPMSK_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask                    */
-#define USB_OTG_DIEPMSK_TXFURM                  0x00000100U            /*!< FIFO underrun mask                                */
-#define USB_OTG_DIEPMSK_BIM                     0x00000200U            /*!< BNA interrupt mask                                */
-
-/********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/
-#define USB_OTG_HPTXSTS_PTXFSAVL                0x0000FFFFU            /*!< Periodic transmit data FIFO space available     */
-
-#define USB_OTG_HPTXSTS_PTXQSAV                 0x00FF0000U            /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0               0x00010000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1               0x00020000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2               0x00040000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3               0x00080000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4               0x00100000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5               0x00200000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6               0x00400000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7               0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_HPTXSTS_PTXQTOP                 0xFF000000U            /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0               0x01000000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1               0x02000000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2               0x04000000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3               0x08000000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4               0x10000000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5               0x20000000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6               0x40000000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7               0x80000000U            /*!<Bit 7 */
-
-/********************  Bit definition forUSB_OTG_HAINT register  ********************/
-#define USB_OTG_HAINT_HAINT                   0x0000FFFFU            /*!< Channel interrupts */
-
-/********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/
-#define USB_OTG_DOEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask               */
-#define USB_OTG_DOEPMSK_STUPM                   0x00000008U            /*!< SETUP phase done mask                          */
-#define USB_OTG_DOEPMSK_OTEPDM                  0x00000010U            /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received mask       */
-#define USB_OTG_DOEPMSK_OPEM                    0x00000100U            /*!< OUT packet error mask                          */
-#define USB_OTG_DOEPMSK_BOIM                    0x00000200U            /*!< BNA interrupt mask                             */
-
-/********************  Bit definition forUSB_OTG_GINTSTS register  ********************/
-#define USB_OTG_GINTSTS_CMOD                    0x00000001U            /*!< Current mode of operation           */
-#define USB_OTG_GINTSTS_MMIS                    0x00000002U            /*!< Mode mismatch interrupt             */
-#define USB_OTG_GINTSTS_OTGINT                  0x00000004U            /*!< OTG interrupt                       */
-#define USB_OTG_GINTSTS_SOF                     0x00000008U            /*!< Start of frame                      */
-#define USB_OTG_GINTSTS_RXFLVL                  0x00000010U            /*!< RxFIFO nonempty                     */
-#define USB_OTG_GINTSTS_NPTXFE                  0x00000020U            /*!< Nonperiodic TxFIFO empty            */
-#define USB_OTG_GINTSTS_GINAKEFF                0x00000040U            /*!< Global IN nonperiodic NAK effective */
-#define USB_OTG_GINTSTS_BOUTNAKEFF              0x00000080U            /*!< Global OUT NAK effective            */
-#define USB_OTG_GINTSTS_ESUSP                   0x00000400U            /*!< Early suspend                            */
-#define USB_OTG_GINTSTS_USBSUSP                 0x00000800U            /*!< USB suspend                              */
-#define USB_OTG_GINTSTS_USBRST                  0x00001000U            /*!< USB reset                                */
-#define USB_OTG_GINTSTS_ENUMDNE                 0x00002000U            /*!< Enumeration done                         */
-#define USB_OTG_GINTSTS_ISOODRP                 0x00004000U            /*!< Isochronous OUT packet dropped interrupt */
-#define USB_OTG_GINTSTS_EOPF                    0x00008000U            /*!< End of periodic frame interrupt          */
-#define USB_OTG_GINTSTS_IEPINT                  0x00040000U            /*!< IN endpoint interrupt                          */
-#define USB_OTG_GINTSTS_OEPINT                  0x00080000U            /*!< OUT endpoint interrupt                         */
-#define USB_OTG_GINTSTS_IISOIXFR                0x00100000U            /*!< Incomplete isochronous IN transfer             */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       0x00200000U            /*!< Incomplete periodic transfer                   */
-#define USB_OTG_GINTSTS_DATAFSUSP               0x00400000U            /*!< Data fetch suspended                           */
-#define USB_OTG_GINTSTS_HPRTINT                 0x01000000U            /*!< Host port interrupt                            */
-#define USB_OTG_GINTSTS_HCINT                   0x02000000U            /*!< Host channels interrupt                        */
-#define USB_OTG_GINTSTS_PTXFE                   0x04000000U            /*!< Periodic TxFIFO empty                          */
-#define USB_OTG_GINTSTS_CIDSCHG                 0x10000000U            /*!< Connector ID status change                     */
-#define USB_OTG_GINTSTS_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt                  */
-#define USB_OTG_GINTSTS_SRQINT                  0x40000000U            /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT                  0x80000000U            /*!< Resume/remote wakeup detected interrupt        */
-
-/********************  Bit definition forUSB_OTG_GINTMSK register  ********************/
-#define USB_OTG_GINTMSK_MMISM                   0x00000002U            /*!< Mode mismatch interrupt mask                        */
-#define USB_OTG_GINTMSK_OTGINT                  0x00000004U            /*!< OTG interrupt mask                                  */
-#define USB_OTG_GINTMSK_SOFM                    0x00000008U            /*!< Start of frame mask                                 */
-#define USB_OTG_GINTMSK_RXFLVLM                 0x00000010U            /*!< Receive FIFO nonempty mask                          */
-#define USB_OTG_GINTMSK_NPTXFEM                 0x00000020U            /*!< Nonperiodic TxFIFO empty mask                       */
-#define USB_OTG_GINTMSK_GINAKEFFM               0x00000040U            /*!< Global nonperiodic IN NAK effective mask            */
-#define USB_OTG_GINTMSK_GONAKEFFM               0x00000080U            /*!< Global OUT NAK effective mask                       */
-#define USB_OTG_GINTMSK_ESUSPM                  0x00000400U            /*!< Early suspend mask                                  */
-#define USB_OTG_GINTMSK_USBSUSPM                0x00000800U            /*!< USB suspend mask                                    */
-#define USB_OTG_GINTMSK_USBRST                  0x00001000U            /*!< USB reset mask                                      */
-#define USB_OTG_GINTMSK_ENUMDNEM                0x00002000U            /*!< Enumeration done mask                               */
-#define USB_OTG_GINTMSK_ISOODRPM                0x00004000U            /*!< Isochronous OUT packet dropped interrupt mask       */
-#define USB_OTG_GINTMSK_EOPFM                   0x00008000U            /*!< End of periodic frame interrupt mask                */
-#define USB_OTG_GINTMSK_EPMISM                  0x00020000U            /*!< Endpoint mismatch interrupt mask                    */
-#define USB_OTG_GINTMSK_IEPINT                  0x00040000U            /*!< IN endpoints interrupt mask                         */
-#define USB_OTG_GINTMSK_OEPINT                  0x00080000U            /*!< OUT endpoints interrupt mask                        */
-#define USB_OTG_GINTMSK_IISOIXFRM               0x00100000U            /*!< Incomplete isochronous IN transfer mask             */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         0x00200000U            /*!< Incomplete periodic transfer mask                   */
-#define USB_OTG_GINTMSK_FSUSPM                  0x00400000U            /*!< Data fetch suspended mask                           */
-#define USB_OTG_GINTMSK_PRTIM                   0x01000000U            /*!< Host port interrupt mask                            */
-#define USB_OTG_GINTMSK_HCIM                    0x02000000U            /*!< Host channels interrupt mask                        */
-#define USB_OTG_GINTMSK_PTXFEM                  0x04000000U            /*!< Periodic TxFIFO empty mask                          */
-#define USB_OTG_GINTMSK_CIDSCHGM                0x10000000U            /*!< Connector ID status change mask                     */
-#define USB_OTG_GINTMSK_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt mask                  */
-#define USB_OTG_GINTMSK_SRQIM                   0x40000000U            /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM                    0x80000000U            /*!< Resume/remote wakeup detected interrupt mask        */
-
-/********************  Bit definition forUSB_OTG_DAINT register  ********************/
-#define USB_OTG_DAINT_IEPINT                  0x0000FFFFU            /*!< IN endpoint interrupt bits  */
-#define USB_OTG_DAINT_OEPINT                  0xFFFF0000U            /*!< OUT endpoint interrupt bits */
-
-/********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/
-#define USB_OTG_HAINTMSK_HAINTM                  0x0000FFFFU            /*!< Channel interrupt mask */
-
-/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
-#define USB_OTG_GRXSTSP_EPNUM                    0x0000000FU            /*!< IN EP interrupt mask bits  */
-#define USB_OTG_GRXSTSP_BCNT                     0x00007FF0U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID                     0x00018000U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS                   0x001E0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/
-#define USB_OTG_DAINTMSK_IEPM                    0x0000FFFFU            /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM                    0xFFFF0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for OTG register  ********************/
-
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition for OTG register  ********************/
-
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/
-#define USB_OTG_GRXFSIZ_RXFD            0x0000FFFFU            /*!< RxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/
-#define USB_OTG_DVBUSDIS_VBUSDT         0x0000FFFFU            /*!< Device VBUS discharge time */
-
-/********************  Bit definition for OTG register  ********************/
-#define USB_OTG_NPTXFSA                 0x0000FFFFU            /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD                  0xFFFF0000U            /*!< Nonperiodic TxFIFO depth               */
-#define USB_OTG_TX0FSA                  0x0000FFFFU            /*!< Endpoint 0 transmit RAM start address  */
-#define USB_OTG_TX0FD                   0xFFFF0000U            /*!< Endpoint 0 TxFIFO depth                */
-
-/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
-#define USB_OTG_DVBUSPULSE_DVBUSP                  0x00000FFFU            /*!< Device VBUS pulsing time */
-
-/********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/
-#define USB_OTG_GNPTXSTS_NPTXFSAV                0x0000FFFFU            /*!< Nonperiodic TxFIFO space available */
-
-#define USB_OTG_GNPTXSTS_NPTQXSAV                0x00FF0000U            /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0              0x00010000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1              0x00020000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2              0x00040000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3              0x00080000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4              0x00100000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5              0x00200000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6              0x00400000U            /*!<Bit 6 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7              0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_GNPTXSTS_NPTXQTOP                0x7F000000U            /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0              0x01000000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1              0x02000000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2              0x04000000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3              0x08000000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4              0x10000000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5              0x20000000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6              0x40000000U            /*!<Bit 6 */
-
-/********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/
-#define USB_OTG_DTHRCTL_NONISOTHREN             0x00000001U            /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN                0x00000002U            /*!< ISO IN endpoint threshold enable */
-
-#define USB_OTG_DTHRCTL_TXTHRLEN                0x000007FCU            /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0              0x00000004U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1              0x00000008U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2              0x00000010U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3              0x00000020U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4              0x00000040U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5              0x00000080U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6              0x00000100U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7              0x00000200U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8              0x00000400U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_RXTHREN                 0x00010000U            /*!< Receive threshold enable */
-
-#define USB_OTG_DTHRCTL_RXTHRLEN                0x03FE0000U            /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0              0x00020000U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1              0x00040000U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2              0x00080000U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3              0x00100000U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4              0x00200000U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5              0x00400000U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6              0x00800000U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7              0x01000000U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8              0x02000000U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_ARPEN                   0x08000000U            /*!< Arbiter parking enable */
-
-/********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM               0x0000FFFFU            /*!< IN EP Tx FIFO empty interrupt mask bits */
-
-/********************  Bit definition forUSB_OTG_DEACHINT register  ********************/
-#define USB_OTG_DEACHINT_IEP1INT                 0x00000002U            /*!< IN endpoint 1interrupt bit   */
-#define USB_OTG_DEACHINT_OEP1INT                 0x00020000U            /*!< OUT endpoint 1 interrupt bit */
-
-/********************  Bit definition forUSB_OTG_GCCFG register  ********************/
-#define USB_OTG_GCCFG_PWRDWN                  0x00010000U            /*!< Power down */
-#define USB_OTG_GCCFG_I2CPADEN                0x00020000U            /*!< Enable I2C bus connection for the external I2C PHY interface */
-#define USB_OTG_GCCFG_VBUSASEN                0x00040000U            /*!< Enable the VBUS sensing device                               */
-#define USB_OTG_GCCFG_VBUSBSEN                0x00080000U            /*!< Enable the VBUS sensing device                               */
-#define USB_OTG_GCCFG_SOFOUTEN                0x00100000U            /*!< SOF output enable                                            */
-#define USB_OTG_GCCFG_NOVBUSSENS              0x00200000U            /*!< VBUS sensing disable option                                  */
-
-/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
-#define USB_OTG_DEACHINTMSK_IEP1INTM                0x00000002U            /*!< IN Endpoint 1 interrupt mask bit  */
-#define USB_OTG_DEACHINTMSK_OEP1INTM                0x00020000U            /*!< OUT Endpoint 1 interrupt mask bit */
-
-/********************  Bit definition forUSB_OTG_CID register  ********************/
-#define USB_OTG_CID_PRODUCT_ID              0xFFFFFFFFU            /*!< Product ID field */
-
-/********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/
-#define USB_OTG_DIEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask                 */
-#define USB_OTG_DIEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask                  */
-#define USB_OTG_DIEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask          */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask           */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask                    */
-#define USB_OTG_DIEPEACHMSK1_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
-
-/********************  Bit definition forUSB_OTG_HPRT register  ********************/
-#define USB_OTG_HPRT_PCSTS                   0x00000001U            /*!< Port connect status        */
-#define USB_OTG_HPRT_PCDET                   0x00000002U            /*!< Port connect detected      */
-#define USB_OTG_HPRT_PENA                    0x00000004U            /*!< Port enable                */
-#define USB_OTG_HPRT_PENCHNG                 0x00000008U            /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA                    0x00000010U            /*!< Port overcurrent active    */
-#define USB_OTG_HPRT_POCCHNG                 0x00000020U            /*!< Port overcurrent change    */
-#define USB_OTG_HPRT_PRES                    0x00000040U            /*!< Port resume   */
-#define USB_OTG_HPRT_PSUSP                   0x00000080U            /*!< Port suspend  */
-#define USB_OTG_HPRT_PRST                    0x00000100U            /*!< Port reset    */
-
-#define USB_OTG_HPRT_PLSTS                   0x00000C00U            /*!< Port line status */
-#define USB_OTG_HPRT_PLSTS_0                 0x00000400U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PLSTS_1                 0x00000800U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PPWR                    0x00001000U            /*!< Port power */
-
-#define USB_OTG_HPRT_PTCTL                   0x0001E000U            /*!< Port test control */
-#define USB_OTG_HPRT_PTCTL_0                 0x00002000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PTCTL_1                 0x00004000U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PTCTL_2                 0x00008000U            /*!<Bit 2 */
-#define USB_OTG_HPRT_PTCTL_3                 0x00010000U            /*!<Bit 3 */
-
-#define USB_OTG_HPRT_PSPD                    0x00060000U            /*!< Port speed */
-#define USB_OTG_HPRT_PSPD_0                  0x00020000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PSPD_1                  0x00040000U            /*!<Bit 1 */
-
-/********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/
-#define USB_OTG_DOEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DOEPEACHMSK1_TXFURM                  0x00000100U            /*!< OUT packet error mask */
-#define USB_OTG_DOEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_BERRM                   0x00001000U            /*!< Bubble error interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NYETM                   0x00004000U            /*!< NYET interrupt mask */
-
-/********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/
-#define USB_OTG_HPTXFSIZ_PTXSA                   0x0000FFFFU            /*!< Host periodic TxFIFO start address */
-#define USB_OTG_HPTXFSIZ_PTXFD                   0xFFFF0000U            /*!< Host periodic TxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/
-#define USB_OTG_DIEPCTL_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
-#define USB_OTG_DIEPCTL_USBAEP                  0x00008000U            /*!< USB active endpoint */
-#define USB_OTG_DIEPCTL_EONUM_DPID              0x00010000U            /*!< Even/odd frame */
-#define USB_OTG_DIEPCTL_NAKSTS                  0x00020000U            /*!< NAK status */
-
-#define USB_OTG_DIEPCTL_EPTYP                   0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_DIEPCTL_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_STALL                   0x00200000U            /*!< STALL handshake */
-
-#define USB_OTG_DIEPCTL_TXFNUM                  0x03C00000U            /*!< TxFIFO number */
-#define USB_OTG_DIEPCTL_TXFNUM_0                0x00400000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                0x00800000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                0x01000000U            /*!<Bit 2 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                0x02000000U            /*!<Bit 3 */
-#define USB_OTG_DIEPCTL_CNAK                    0x04000000U            /*!< Clear NAK */
-#define USB_OTG_DIEPCTL_SNAK                    0x08000000U            /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          0x10000000U            /*!< Set DATA0 PID */
-#define USB_OTG_DIEPCTL_SODDFRM                 0x20000000U            /*!< Set odd frame */
-#define USB_OTG_DIEPCTL_EPDIS                   0x40000000U            /*!< Endpoint disable */
-#define USB_OTG_DIEPCTL_EPENA                   0x80000000U            /*!< Endpoint enable */
-
-/********************  Bit definition forUSB_OTG_HCCHAR register  ********************/
-#define USB_OTG_HCCHAR_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
-
-#define USB_OTG_HCCHAR_EPNUM                   0x00007800U            /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPNUM_1                 0x00001000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_EPNUM_2                 0x00002000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_EPNUM_3                 0x00004000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_EPDIR                   0x00008000U            /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV                   0x00020000U            /*!< Low-speed device */
-
-#define USB_OTG_HCCHAR_EPTYP                   0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_MC                      0x00300000U            /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                    0x00100000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_MC_1                    0x00200000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_DAD                     0x1FC00000U            /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                   0x00400000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_DAD_1                   0x00800000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_DAD_2                   0x01000000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_DAD_3                   0x02000000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_DAD_4                   0x04000000U            /*!<Bit 4 */
-#define USB_OTG_HCCHAR_DAD_5                   0x08000000U            /*!<Bit 5 */
-#define USB_OTG_HCCHAR_DAD_6                   0x10000000U            /*!<Bit 6 */
-#define USB_OTG_HCCHAR_ODDFRM                  0x20000000U            /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS                   0x40000000U            /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA                   0x80000000U            /*!< Channel enable */
-
-/********************  Bit definition forUSB_OTG_HCSPLT register  ********************/
-
-#define USB_OTG_HCSPLT_PRTADDR                 0x0000007FU            /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_PRTADDR_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_PRTADDR_2               0x00000004U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_PRTADDR_3               0x00000008U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_PRTADDR_4               0x00000010U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_PRTADDR_5               0x00000020U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_PRTADDR_6               0x00000040U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_HUBADDR                 0x00003F80U            /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0               0x00000080U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_HUBADDR_1               0x00000100U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_HUBADDR_2               0x00000200U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_HUBADDR_3               0x00000400U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_HUBADDR_4               0x00000800U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_HUBADDR_5               0x00001000U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_HUBADDR_6               0x00002000U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_XACTPOS                 0x0000C000U            /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0               0x00004000U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_XACTPOS_1               0x00008000U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_COMPLSPLT               0x00010000U            /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN                 0x80000000U            /*!< Split enable */
-
-/********************  Bit definition forUSB_OTG_HCINT register  ********************/
-#define USB_OTG_HCINT_XFRC                    0x00000001U            /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH                     0x00000002U            /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINT_STALL                   0x00000008U            /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK                     0x00000010U            /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK                     0x00000020U            /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET                    0x00000040U            /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR                   0x00000080U            /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR                   0x00000100U            /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR                   0x00000200U            /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR                   0x00000400U            /*!< Data toggle error */
-
-/********************  Bit definition forUSB_OTG_DIEPINT register  ********************/
-#define USB_OTG_DIEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_TOC                     0x00000008U            /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE                  0x00000010U            /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNE                  0x00000040U            /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE                    0x00000080U            /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN              0x00000100U            /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA                     0x00000200U            /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS               0x00000800U            /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR                    0x00001000U            /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK                     0x00002000U            /*!< NAK interrupt */
-
-/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
-#define USB_OTG_HCINTMSK_XFRCM                   0x00000001U            /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM                    0x00000002U            /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM                  0x00000008U            /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM                    0x00000010U            /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM                    0x00000020U            /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET                    0x00000040U            /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM                  0x00000080U            /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM                  0x00000100U            /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM                  0x00000200U            /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM                  0x00000400U            /*!< Data toggle error mask */
-
-/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
-
-#define USB_OTG_DIEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT                  0x60000000U            /*!< Packet count */
-/********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/
-#define USB_OTG_HCTSIZ_XFRSIZ                    0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT                    0x1FF80000U            /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING                    0x80000000U            /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID                      0x60000000U            /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                    0x20000000U            /*!<Bit 0 */
-#define USB_OTG_HCTSIZ_DPID_1                    0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/
-#define USB_OTG_DIEPDMA_DMAADDR                  0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition forUSB_OTG_HCDMA register  ********************/
-#define USB_OTG_HCDMA_DMAADDR                    0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/
-#define USB_OTG_DTXFSTS_INEPTFSAV                0x0000FFFFU            /*!< IN endpoint TxFIFO space available */
-
-/********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/
-#define USB_OTG_DIEPTXF_INEPTXSA                 0x0000FFFFU            /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD                 0xFFFF0000U            /*!< IN endpoint TxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/
-
-#define USB_OTG_DOEPCTL_MPSIZ                     0x000007FFU            /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP                    0x00008000U            /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS                    0x00020000U            /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            0x10000000U            /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM                   0x20000000U            /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP                     0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                   0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DOEPCTL_EPTYP_1                   0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_SNPM                      0x00100000U            /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL                     0x00200000U            /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK                      0x04000000U            /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK                      0x08000000U            /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS                     0x40000000U            /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA                     0x80000000U            /*!< Endpoint enable */
-
-/********************  Bit definition forUSB_OTG_DOEPINT register  ********************/
-#define USB_OTG_DOEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_STUP                    0x00000008U            /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS                 0x00000010U            /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_NYET                    0x00004000U            /*!< NYET interrupt */
-
-/********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/
-
-#define USB_OTG_DOEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-
-#define USB_OTG_DOEPTSIZ_STUPCNT                 0x60000000U            /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0               0x20000000U            /*!<Bit 0 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1               0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition for PCGCCTL register  ********************/
-#define USB_OTG_PCGCCTL_STOPCLK                 0x00000001U            /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK                 0x00000002U            /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP                 0x00000010U            /*!<Bit 1 */
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
-                                       ((INSTANCE) == ADC2) || \
-                                       ((INSTANCE) == ADC3))
-
-/******************************* CAN Instances ********************************/
-#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
-                                       ((INSTANCE) == CAN2))
- 
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DAC Instances ********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/******************************* DCMI Instances *******************************/
-#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
-
-/******************************* DMA2D Instances *******************************/
-#define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
-
-/******************************** DMA Instances *******************************/
-#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
-                                              ((INSTANCE) == DMA1_Stream1) || \
-                                              ((INSTANCE) == DMA1_Stream2) || \
-                                              ((INSTANCE) == DMA1_Stream3) || \
-                                              ((INSTANCE) == DMA1_Stream4) || \
-                                              ((INSTANCE) == DMA1_Stream5) || \
-                                              ((INSTANCE) == DMA1_Stream6) || \
-                                              ((INSTANCE) == DMA1_Stream7) || \
-                                              ((INSTANCE) == DMA2_Stream0) || \
-                                              ((INSTANCE) == DMA2_Stream1) || \
-                                              ((INSTANCE) == DMA2_Stream2) || \
-                                              ((INSTANCE) == DMA2_Stream3) || \
-                                              ((INSTANCE) == DMA2_Stream4) || \
-                                              ((INSTANCE) == DMA2_Stream5) || \
-                                              ((INSTANCE) == DMA2_Stream6) || \
-                                              ((INSTANCE) == DMA2_Stream7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOF) || \
-                                        ((INSTANCE) == GPIOG) || \
-                                        ((INSTANCE) == GPIOH) || \
-                                        ((INSTANCE) == GPIOI) || \
-                                        ((INSTANCE) == GPIOJ) || \
-                                        ((INSTANCE) == GPIOK))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2) || \
-                                       ((INSTANCE) == I2C3))
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI2) || \
-                                        ((INSTANCE) == SPI3))
-
-/*************************** I2S Extended Instances ***************************/
-#define IS_I2S_ALL_INSTANCE_EXT(PERIPH)  (((INSTANCE) == SPI2)    || \
-                                          ((INSTANCE) == SPI3)    || \
-                                          ((INSTANCE) == I2S2ext) || \
-                                          ((INSTANCE) == I2S3ext))
-
-/****************************** LTDC Instances ********************************/
-#define IS_LTDC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == LTDC)
-
-/******************************* RNG Instances ********************************/
-#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************* SAI Instances ********************************/
-#define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
-                                     ((PERIPH) == SAI1_Block_B))
-/* Legacy define */
-#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3) || \
-                                       ((INSTANCE) == SPI4) || \
-                                       ((INSTANCE) == SPI5) || \
-                                       ((INSTANCE) == SPI6))
-
-/*************************** SPI Extended Instances ***************************/
-#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1)    || \
-                                           ((INSTANCE) == SPI2)    || \
-                                           ((INSTANCE) == SPI3)    || \
-                                           ((INSTANCE) == SPI4)    || \
-                                           ((INSTANCE) == SPI5)    || \
-                                           ((INSTANCE) == SPI6)    || \
-                                           ((INSTANCE) == I2S2ext) || \
-                                           ((INSTANCE) == I2S3ext))
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
-                                   ((INSTANCE) == TIM2)   || \
-                                   ((INSTANCE) == TIM3)   || \
-                                   ((INSTANCE) == TIM4)   || \
-                                   ((INSTANCE) == TIM5)   || \
-                                   ((INSTANCE) == TIM6)   || \
-                                   ((INSTANCE) == TIM7)   || \
-                                   ((INSTANCE) == TIM8)   || \
-                                   ((INSTANCE) == TIM9)   || \
-                                   ((INSTANCE) == TIM10)  || \
-                                   ((INSTANCE) == TIM11)  || \
-                                   ((INSTANCE) == TIM12)  || \
-                                   ((INSTANCE) == TIM13)  || \
-                                   ((INSTANCE) == TIM14))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
-                                         ((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM8)  || \
-                                         ((INSTANCE) == TIM9)  || \
-                                         ((INSTANCE) == TIM10) || \
-                                         ((INSTANCE) == TIM11) || \
-                                         ((INSTANCE) == TIM12) || \
-                                         ((INSTANCE) == TIM13) || \
-                                         ((INSTANCE) == TIM14))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM8) || \
-                                       ((INSTANCE) == TIM9) || \
-                                       ((INSTANCE) == TIM12))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8))
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM8))
-
-/******************** TIM Instances : Advanced-control timers *****************/
-#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                            ((INSTANCE) == TIM8))
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8))
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM6) || \
-                                       ((INSTANCE) == TIM7) || \
-                                       ((INSTANCE) == TIM8))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM8))
-
-/************ TIM Instances : DMA requests generation (COMDE) *****************/
-#define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM8)) 
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                             ((INSTANCE) == TIM2) || \
-                                             ((INSTANCE) == TIM3) || \
-                                             ((INSTANCE) == TIM4) || \
-                                             ((INSTANCE) == TIM5) || \
-                                             ((INSTANCE) == TIM8))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM6) || \
-                                          ((INSTANCE) == TIM7) || \
-                                          ((INSTANCE) == TIM8) || \
-                                          ((INSTANCE) == TIM9) || \
-                                          ((INSTANCE) == TIM12))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8) || \
-                                         ((INSTANCE) == TIM9) || \
-                                         ((INSTANCE) == TIM12))
-
-/********************** TIM Instances : 32 bit Counter ************************/
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
-                                              ((INSTANCE) == TIM5))
-
-/***************** TIM Instances : external trigger input availabe ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                        ((INSTANCE) == TIM2) || \
-                                        ((INSTANCE) == TIM3) || \
-                                        ((INSTANCE) == TIM4) || \
-                                        ((INSTANCE) == TIM5) || \
-                                        ((INSTANCE) == TIM8))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM11))
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM1) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM5) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM8) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM12) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM13) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM14) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-/************ TIM Instances : complementary output(s) available ***************/
-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
-   ((((INSTANCE) == TIM1) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3)))            \
-    ||                                          \
-    (((INSTANCE) == TIM8) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3))))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3) || \
-                                     ((INSTANCE) == USART6))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5)  || \
-                                    ((INSTANCE) == USART6) || \
-                                    ((INSTANCE) == UART7)  || \
-                                    ((INSTANCE) == UART8))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3) || \
-                                           ((INSTANCE) == USART6))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3) || \
-                                         ((INSTANCE) == USART6))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5)  || \
-                                    ((INSTANCE) == USART6) || \
-                                    ((INSTANCE) == UART7)  || \
-                                    ((INSTANCE) == UART8))     
-
-/*********************** PCD Instances ****************************************/
-#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
-                                        ((INSTANCE) == USB_OTG_HS))
-
-/*********************** HCD Instances ****************************************/
-#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
-                                       ((INSTANCE) == USB_OTG_HS))
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/****************************** SDIO Instances ********************************/
-#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
-
-/****************************** USB Exported Constants ************************/
-#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                8U
-#define USB_OTG_FS_MAX_IN_ENDPOINTS                    4U    /* Including EP0 */
-#define USB_OTG_FS_MAX_OUT_ENDPOINTS                   4U    /* Including EP0 */
-#define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */
-
-#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR                12U
-#define USB_OTG_HS_MAX_IN_ENDPOINTS                    6U    /* Including EP0 */
-#define USB_OTG_HS_MAX_OUT_ENDPOINTS                   6U    /* Including EP0 */
-#define USB_OTG_HS_TOTAL_FIFO_SIZE                     4096U /* in Bytes */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32F4xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */
-/*  product lines within the same STM32F4 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-#define FSMC_IRQn              FMC_IRQn
-
-/* Aliases for __IRQHandler */
-#define FSMC_IRQHandler        FMC_IRQHandler
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32F439xx_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/cmsis/stm32f446xx.h b/stmhal/cmsis/stm32f446xx.h
deleted file mode 100644
index d6aab7e3c2..0000000000
--- a/stmhal/cmsis/stm32f446xx.h
+++ /dev/null
@@ -1,8301 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f446xx.h
-  * @author  MCD Application Team
-  * @version V2.5.1
-  * @date    28-June-2016
-  * @brief   CMSIS STM32F446xx Device Peripheral Access Layer Header File.
-  *
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - peripherals registers declarations and bits definition
-  *           - Macros to access peripheral’s registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS_Device
-  * @{
-  */
-
-/** @addtogroup stm32f446xx
-  * @{
-  */
-    
-#ifndef __STM32F446xx_H
-#define __STM32F446xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-  
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-
-/**
-  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
-  */
-#define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */
-#define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */
-#define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1U       /*!< FPU present                                   */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32F4XX Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-typedef enum
-{
-/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
-  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
-/******  STM32 specific Interrupt Numbers **********************************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
-  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
-  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
-  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
-  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
-  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
-  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
-  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
-  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
-  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
-  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
-  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
-  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
-  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
-  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
-  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
-  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
-  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */    
-  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
-  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
-  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
-  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare global interrupt                             */
-  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
-  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
-  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
-  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
-  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
-  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
-  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
-  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
-  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
-  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
-  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
-  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
-  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
-  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
-  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
-  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
-  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
-  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
-  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
-  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
-  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
-  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
-  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
-  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
-  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
-  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
-  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
-  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
-  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
-  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
-  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
-  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
-  SAI2_IRQn                   = 91,     /*!< SAI2 global Interrupt                                             */
-  QUADSPI_IRQn                = 92,     /*!< QuadSPI global Interrupt                                          */
-  CEC_IRQn                    = 93,     /*!< CEC global Interrupt                                              */
-  SPDIF_RX_IRQn               = 94,     /*!< SPDIF-RX global Interrupt                                          */
-  FMPI2C1_EV_IRQn             = 95,     /*!< FMPI2C1 Event Interrupt                                           */
-  FMPI2C1_ER_IRQn             = 96      /*!< FMPI2C1 Error Interrupt                                           */  
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
-#include "system_stm32f4xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */      
-  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
-  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
-  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
-  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
-  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
-  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
-  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
-  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
-  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
-  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
-  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
-  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
-  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
-  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
-  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
-                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
-} ADC_Common_TypeDef;
-
-
-/** 
-  * @brief Controller Area Network TxMailBox 
-  */
-
-typedef struct
-{
-  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
-  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
-  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
-  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
-} CAN_TxMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FIFOMailBox 
-  */
-  
-typedef struct
-{
-  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
-  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
-  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
-  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
-} CAN_FIFOMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FilterRegister 
-  */
-  
-typedef struct
-{
-  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
-  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
-} CAN_FilterRegister_TypeDef;
-
-/** 
-  * @brief Controller Area Network 
-  */
-  
-typedef struct
-{
-  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
-  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
-  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
-  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
-  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
-  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
-  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
-  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
-  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
-  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
-  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
-  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
-  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
-  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
-  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
-  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
-  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
-  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
-  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
-  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
-  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */ 
-  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
-} CAN_TypeDef;
-
-/**
-  * @brief Consumer Electronics Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< CEC control register,              Address offset:0x00 */
-  __IO uint32_t CFGR;         /*!< CEC configuration register,        Address offset:0x04 */
-  __IO uint32_t TXDR;         /*!< CEC Tx data register ,             Address offset:0x08 */
-  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,              Address offset:0x0C */
-  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register, Address offset:0x10 */
-  __IO uint32_t IER;          /*!< CEC interrupt enable register,     Address offset:0x14 */
-}CEC_TypeDef;
-
-/** 
-  * @brief CRC calculation unit 
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
-  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */
-  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
-  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
-  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
-  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
-  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
-  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
-  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
-  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
-  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
-  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
-  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
-  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
-  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
-  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
-  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
-  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
-  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
-  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DCMI
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
-  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
-  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
-  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
-  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
-  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
-  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
-  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
-  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
-  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
-  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
-} DCMI_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
-  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
-  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
-  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
-  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
-  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
-} DMA_Stream_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
-  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
-  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
-  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
-} DMA_TypeDef;
-
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
-  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
-  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
-  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
-  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
-  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-
-typedef struct
-{
-  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */
-  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */
-  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */
-  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */
-  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */
-  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief Flexible Memory Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */   
-} FMC_Bank1_TypeDef; 
-
-/** 
-  * @brief Flexible Memory Controller Bank1E
-  */
-  
-typedef struct
-{
-  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
-} FMC_Bank1E_TypeDef;
-
-/** 
-  * @brief Flexible Memory Controller Bank3
-  */
- 
-typedef struct
-{
-  __IO uint32_t PCR;       /*!< NAND Flash control register,                       Address offset: 0x80 */
-  __IO uint32_t SR;        /*!< NAND Flash FIFO status and interrupt register,     Address offset: 0x84 */
-  __IO uint32_t PMEM;      /*!< NAND Flash Common memory space timing register,    Address offset: 0x88 */
-  __IO uint32_t PATT;      /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
-  uint32_t      RESERVED;  /*!< Reserved, 0x90                                                          */
-  __IO uint32_t ECCR;      /*!< NAND Flash ECC result registers,                   Address offset: 0x94 */
-} FMC_Bank3_TypeDef;
-
-/** 
-  * @brief Flexible Memory Controller Bank5_6
-  */
-  
-typedef struct
-{
-  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */
-  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */
-  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */
-  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */
-  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */
-} FMC_Bank5_6_TypeDef; 
-
-/** 
-  * @brief General Purpose I/O
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
-  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
-  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
-  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
-  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
-  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
-  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
-  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/** 
-  * @brief System configuration controller
-  */
-  
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */ 
-  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
-  uint32_t      RESERVED1[2]; /*!< Reserved, 0x24-0x28                                                          */ 
-  __IO uint32_t CFGR;         /*!< SYSCFG Configuration register,                     Address offset: 0x2C      */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */
-  __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */
-  __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */
-  __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */
-  __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */
-  __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
-  __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
-  __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
-  __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */
-} I2C_TypeDef;
-
-/**
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< FMPI2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< FMPI2C Control register 2,            Address offset: 0x04 */
-  __IO uint32_t OAR1;        /*!< FMPI2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;        /*!< FMPI2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;     /*!< FMPI2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR;    /*!< FMPI2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;         /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;         /*!< FMPI2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;        /*!< FMPI2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;        /*!< FMPI2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;        /*!< FMPI2C Transmit data register,        Address offset: 0x28 */
-} FMPI2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
-  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
-  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
-  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
-  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
-  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
-  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
-  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
-  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
-  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
-  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
-  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
-  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
-  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
-  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
-  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
-  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
-  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
-  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
-  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
-  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
-  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
-  __IO uint32_t PLLSAICFGR;    /*!< RCC PLLSAI configuration register,                           Address offset: 0x88 */
-  __IO uint32_t DCKCFGR;       /*!< RCC Dedicated Clocks configuration register,                 Address offset: 0x8C */
-  __IO uint32_t CKGATENR;       /*!< RCC Clocks Gated ENable Register,                           Address offset: 0x90 */
-  __IO uint32_t DCKCFGR2;      /*!< RCC Dedicated Clocks configuration register 2,               Address offset: 0x94 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-
-typedef struct
-{
-  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
-  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
-  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
-  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
-  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
-  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
-  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */
-  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
-  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */
-  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
-  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */
-  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */
-  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */
-  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */
-  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
-  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */
-  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
-  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
-  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
-  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
-  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
-  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
-  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
-  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
-  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
-  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
-  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
-  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
-  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
-  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
-  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
-  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
-  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
-  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
-  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
-  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
-  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
-} RTC_TypeDef;
-
-/** 
-  * @brief Serial Audio Interface
-  */
-  
-typedef struct
-{
-  __IO uint32_t GCR;      /*!< SAI global configuration register,        Address offset: 0x00 */
-} SAI_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */
-  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */
-  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */
-  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */
-  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
-  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */
-  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */
-  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */
-} SAI_Block_TypeDef;
-
-/** 
-  * @brief SD host Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t POWER;          /*!< SDIO power control register,    Address offset: 0x00 */
-  __IO uint32_t CLKCR;          /*!< SDI clock control register,     Address offset: 0x04 */
-  __IO uint32_t ARG;            /*!< SDIO argument register,         Address offset: 0x08 */
-  __IO uint32_t CMD;            /*!< SDIO command register,          Address offset: 0x0C */
-  __I uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */
-  __I uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */
-  __I uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */
-  __I uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */
-  __I uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */
-  __IO uint32_t DTIMER;         /*!< SDIO data timer register,       Address offset: 0x24 */
-  __IO uint32_t DLEN;           /*!< SDIO data length register,      Address offset: 0x28 */
-  __IO uint32_t DCTRL;          /*!< SDIO data control register,     Address offset: 0x2C */
-  __I uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */
-  __I uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */
-  __IO uint32_t ICR;            /*!< SDIO interrupt clear register,  Address offset: 0x38 */
-  __IO uint32_t MASK;           /*!< SDIO mask register,             Address offset: 0x3C */
-  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
-  __I uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */
-  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
-  __IO uint32_t FIFO;           /*!< SDIO data FIFO register,        Address offset: 0x80 */
-} SDIO_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief QUAD Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */
-  __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
-  __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */
-  __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
-  __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
-  __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
-  __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */
-  __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
-  __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */
-  __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
-  __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */                  
-  __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
-  __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */    
-} QUADSPI_TypeDef;
-
-/** 
-  * @brief SPDIFRX Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t   CR;           /*!< Control register,                   Address offset: 0x00 */
-  __IO uint16_t   IMR;          /*!< Interrupt mask register,            Address offset: 0x04 */
-  uint16_t        RESERVED0;    /*!< Reserved,  0x06                                          */  
-  __IO uint32_t   SR;           /*!< Status register,                    Address offset: 0x08 */
-  __IO uint16_t   IFCR;         /*!< Interrupt Flag Clear register,      Address offset: 0x0C */
-  uint16_t        RESERVED1;    /*!< Reserved,  0x0E                                          */   
-  __IO uint32_t   DR;           /*!< Data input register,                Address offset: 0x10 */
-  __IO uint32_t   CSR;          /*!< Channel Status register,            Address offset: 0x14 */
-   __IO uint32_t  DIR;          /*!< Debug Information register,         Address offset: 0x18 */
-  uint16_t        RESERVED2;    /*!< Reserved,  0x1A                                          */   
-} SPDIFRX_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
-  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
-  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
-  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
- 
-/** 
-  * @brief USB_OTG_Core_Registers
-  */
-typedef struct
-{
- __IO uint32_t GOTGCTL;               /*!< USB_OTG Control and Status Register          000h */
-  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */
-  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */
-  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */
-  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */
-  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */
-  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */
-  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */
-  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */
-  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */
-  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */
-  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */
-  uint32_t Reserved30[2];             /*!< Reserved                                     030h */
-  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */
-  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */
-  uint32_t  Reserved5[3];             /*!< Reserved                                040h-048h */
-  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */
-  uint32_t  Reserved6;                /*!< Reserved                                     050h */ 
-  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */
-  uint32_t  Reserved;                 /*!< Reserved                                     058h */
-  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */
-  uint32_t  Reserved43[40];           /*!< Reserved                                058h-0FFh */
-  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */
-  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */
-} USB_OTG_GlobalTypeDef;
-
-/** 
-  * @brief USB_OTG_device_Registers
-  */
-typedef struct 
-{
-  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */
-  __IO uint32_t DCTL;            /*!< dev Control Register         804h */
-  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */
-  uint32_t Reserved0C;           /*!< Reserved                     80Ch */
-  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */
-  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */
-  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */
-  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */
-  uint32_t  Reserved20;          /*!< Reserved                     820h */
-  uint32_t Reserved9;            /*!< Reserved                     824h */
-  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */
-  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */
-  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */
-  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */
-  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */
-  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */  
-  uint32_t Reserved40;           /*!< dedicated EP mask            840h */
-  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */
-  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */
-  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */   
-} USB_OTG_DeviceTypeDef;
-
-/** 
-  * @brief USB_OTG_IN_Endpoint-Specific_Register
-  */
-typedef struct 
-{
-  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */
-  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */
-  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */
-  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */
-  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */
-  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */
-  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
-  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
-} USB_OTG_INEndpointTypeDef;
-
-/** 
-  * @brief USB_OTG_OUT_Endpoint-Specific_Registers
-  */
-typedef struct 
-{
-  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */
-  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */
-  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */
-  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */
-  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */
-  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */
-  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
-} USB_OTG_OUTEndpointTypeDef;
-
-/** 
-  * @brief USB_OTG_Host_Mode_Register_Structures
-  */
-typedef struct 
-{
-  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */
-  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */
-  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */
-  uint32_t Reserved40C;           /*!< Reserved                             40Ch */
-  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */
-  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */
-  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */
-} USB_OTG_HostTypeDef;
-
-/** 
-  * @brief USB_OTG_Host_Channel_Specific_Registers
-  */
-typedef struct
-{
-  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */
-  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */
-  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */
-  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */
-  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */
-  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */
-  uint32_t Reserved[2];           /*!< Reserved                                      */
-} USB_OTG_HostChannelTypeDef;
-
-/**
-  * @}
-  */
-    
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-#define FLASH_BASE            0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region                         */
-#define SRAM1_BASE            0x20000000U /*!< SRAM1(112 KB) base address in the alias region                             */
-#define SRAM2_BASE            0x2001C000U /*!< SRAM2(16 KB) base address in the alias region                              */
-#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region                                */
-#define BKPSRAM_BASE          0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region                         */
-#define FMC_R_BASE            0xA0000000U /*!< FMC registers base address                                                 */
-#define QSPI_R_BASE            0xA0001000U /*!< QuadSPI registers base address                                            */
-
-#define SRAM1_BB_BASE         0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region                          */
-#define SRAM2_BB_BASE         0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region                           */
-#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region                             */
-#define BKPSRAM_BB_BASE       0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region                      */
-#define FLASH_END             0x0807FFFFU /*!< FLASH end address                                                          */
-
-/* Legacy defines */
-#define SRAM_BASE             SRAM1_BASE
-#define SRAM_BB_BASE          SRAM1_BB_BASE
-
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000U)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)
-#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800U)
-#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00U)
-#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000U)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)
-#define SPDIFRX_BASE          (APB1PERIPH_BASE + 0x4000U)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800U)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00U)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x5000U)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)
-#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)
-#define FMPI2C1_BASE          (APB1PERIPH_BASE + 0x6000U)
-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)
-#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800U)
-#define CEC_BASE              (APB1PERIPH_BASE + 0x6C00U)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)
-
-/*!< APB2 peripherals */
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000U)
-#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400U)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x1000U)
-#define USART6_BASE           (APB2PERIPH_BASE + 0x1400U)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000U)
-#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100U)
-#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200U)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x2300U)
-#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00U)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)
-#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400U)
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800U)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00U)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000U)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400U)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800U)
-#define SAI1_BASE             (APB2PERIPH_BASE + 0x5800U)
-#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004U)
-#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024U)
-#define SAI2_BASE             (APB2PERIPH_BASE + 0x5C00U)
-#define SAI2_Block_A_BASE     (SAI2_BASE + 0x004U)
-#define SAI2_Block_B_BASE     (SAI2_BASE + 0x024U)
-
-/*!< AHB1 peripherals */
-#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000U)
-#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400U)
-#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800U)
-#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00U)
-#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000U)
-#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400U)
-#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800U)
-#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00U)
-#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)
-#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800U)
-#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00U)
-#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000U)
-#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010U)
-#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028U)
-#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040U)
-#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058U)
-#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070U)
-#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088U)
-#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0U)
-#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8U)
-#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400U)
-#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010U)
-#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028U)
-#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040U)
-#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058U)
-#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070U)
-#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088U)
-#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0U)
-#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)
-
-/*!< AHB2 peripherals */
-#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000U)
-
-/*!< FMC Bankx registers base address */
-#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000U)
-#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104U)
-#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080U)
-#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140U)
-
-/*!< Debug MCU registers base address */
-#define DBGMCU_BASE           0xE0042000U
-
-/*!< USB registers base address */
-#define USB_OTG_HS_PERIPH_BASE               0x40040000U
-#define USB_OTG_FS_PERIPH_BASE               0x50000000U
-
-#define USB_OTG_GLOBAL_BASE                  0x000U
-#define USB_OTG_DEVICE_BASE                  0x800U
-#define USB_OTG_IN_ENDPOINT_BASE             0x900U
-#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U
-#define USB_OTG_EP_REG_SIZE                  0x20U
-#define USB_OTG_HOST_BASE                    0x400U
-#define USB_OTG_HOST_PORT_BASE               0x440U
-#define USB_OTG_HOST_CHANNEL_BASE            0x500U
-#define USB_OTG_HOST_CHANNEL_SIZE            0x20U
-#define USB_OTG_PCGCCTL_BASE                 0xE00U
-#define USB_OTG_FIFO_BASE                    0x1000U
-#define USB_OTG_FIFO_SIZE                    0x1000U
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
-#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
-#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define SPDIFRX             ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define UART4               ((USART_TypeDef *) UART4_BASE)
-#define UART5               ((USART_TypeDef *) UART5_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
-#define FMPI2C1             ((FMPI2C_TypeDef *) FMPI2C1_BASE)
-#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
-#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
-#define CEC                 ((CEC_TypeDef *) CEC_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
-#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define USART6              ((USART_TypeDef *) USART6_BASE)
-#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
-#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
-#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE) 
-#define SPI4                ((SPI_TypeDef *) SPI4_BASE)
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-#define SAI1                ((SAI_TypeDef *) SAI1_BASE)
-#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
-#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
-#define SAI2                ((SAI_TypeDef *) SAI2_BASE)
-#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
-#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
-
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
-#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
-#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
-#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
-#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
-#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
-#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
-#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
-#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
-#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
-#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
-#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
-#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
-#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
-#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
-#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
-#define FMC_Bank1           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
-#define FMC_Bank1E          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
-#define FMC_Bank3           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
-#define FMC_Bank5_6         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
-#define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)
-
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
-#define USB_OTG_HS          ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers_Bits_Definition               */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Analog to Digital Converter                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          0x00000001U        /*!<Analog watchdog flag */
-#define  ADC_SR_EOC                          0x00000002U        /*!<End of conversion */
-#define  ADC_SR_JEOC                         0x00000004U        /*!<Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        0x00000008U        /*!<Injected channel Start flag */
-#define  ADC_SR_STRT                         0x00000010U        /*!<Regular channel Start flag */
-#define  ADC_SR_OVR                          0x00000020U        /*!<Overrun flag */
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
-#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels */
-#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels */
-#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution) */
-#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
-  
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion */
-#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode */
-#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC) */
-#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection */
-#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment */
-#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      0xFFFFU            /*!<Injected data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag */
-#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion */
-#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag */
-#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag */
-#define  ADC_CSR_OVR1                        0x00000020U        /*!<ADC1 DMA overrun  flag */
-#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag */
-#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion */
-#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag */
-#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag */
-#define  ADC_CSR_OVR2                        0x00002000U        /*!<ADC2 DMA overrun  flag */
-#define  ADC_CSR_AWD3                        0x00010000U        /*!<ADC3 Analog watchdog flag */
-#define  ADC_CSR_EOC3                        0x00020000U        /*!<ADC3 End of conversion */
-#define  ADC_CSR_JEOC3                       0x00040000U        /*!<ADC3 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT3                      0x00080000U        /*!<ADC3 Injected channel Start flag */
-#define  ADC_CSR_STRT3                       0x00100000U        /*!<ADC3 Regular channel Start flag */
-#define  ADC_CSR_OVR3                        0x00200000U        /*!<ADC3 DMA overrun  flag */
-
-/* Legacy defines */
-#define  ADC_CSR_DOVR1                        ADC_CSR_OVR1
-#define  ADC_CSR_DOVR2                        ADC_CSR_OVR2
-#define  ADC_CSR_DOVR3                        ADC_CSR_OVR3
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
-#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
-#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
-#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
-#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
-
-/*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                      0x0000FFFFU         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                      0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Controller Area Network                            */
-/*                                                                            */
-/******************************************************************************/
-/*!<CAN control and status registers */
-/*******************  Bit definition for CAN_MCR register  ********************/
-#define  CAN_MCR_INRQ                        0x00000001U        /*!<Initialization Request */
-#define  CAN_MCR_SLEEP                       0x00000002U        /*!<Sleep Mode Request */
-#define  CAN_MCR_TXFP                        0x00000004U        /*!<Transmit FIFO Priority */
-#define  CAN_MCR_RFLM                        0x00000008U        /*!<Receive FIFO Locked Mode */
-#define  CAN_MCR_NART                        0x00000010U        /*!<No Automatic Retransmission */
-#define  CAN_MCR_AWUM                        0x00000020U        /*!<Automatic Wakeup Mode */
-#define  CAN_MCR_ABOM                        0x00000040U        /*!<Automatic Bus-Off Management */
-#define  CAN_MCR_TTCM                        0x00000080U        /*!<Time Triggered Communication Mode */
-#define  CAN_MCR_RESET                       0x00008000U        /*!<bxCAN software master reset */
-#define  CAN_MCR_DBF                         0x00010000U        /*!<bxCAN Debug freeze */
-/*******************  Bit definition for CAN_MSR register  ********************/
-#define  CAN_MSR_INAK                        0x0001U            /*!<Initialization Acknowledge */
-#define  CAN_MSR_SLAK                        0x0002U            /*!<Sleep Acknowledge */
-#define  CAN_MSR_ERRI                        0x0004U            /*!<Error Interrupt */
-#define  CAN_MSR_WKUI                        0x0008U            /*!<Wakeup Interrupt */
-#define  CAN_MSR_SLAKI                       0x0010U            /*!<Sleep Acknowledge Interrupt */
-#define  CAN_MSR_TXM                         0x0100U            /*!<Transmit Mode */
-#define  CAN_MSR_RXM                         0x0200U            /*!<Receive Mode */
-#define  CAN_MSR_SAMP                        0x0400U            /*!<Last Sample Point */
-#define  CAN_MSR_RX                          0x0800U            /*!<CAN Rx Signal */
-
-/*******************  Bit definition for CAN_TSR register  ********************/
-#define  CAN_TSR_RQCP0                       0x00000001U        /*!<Request Completed Mailbox0 */
-#define  CAN_TSR_TXOK0                       0x00000002U        /*!<Transmission OK of Mailbox0 */
-#define  CAN_TSR_ALST0                       0x00000004U        /*!<Arbitration Lost for Mailbox0 */
-#define  CAN_TSR_TERR0                       0x00000008U        /*!<Transmission Error of Mailbox0 */
-#define  CAN_TSR_ABRQ0                       0x00000080U        /*!<Abort Request for Mailbox0 */
-#define  CAN_TSR_RQCP1                       0x00000100U        /*!<Request Completed Mailbox1 */
-#define  CAN_TSR_TXOK1                       0x00000200U        /*!<Transmission OK of Mailbox1 */
-#define  CAN_TSR_ALST1                       0x00000400U        /*!<Arbitration Lost for Mailbox1 */
-#define  CAN_TSR_TERR1                       0x00000800U        /*!<Transmission Error of Mailbox1 */
-#define  CAN_TSR_ABRQ1                       0x00008000U        /*!<Abort Request for Mailbox 1 */
-#define  CAN_TSR_RQCP2                       0x00010000U        /*!<Request Completed Mailbox2 */
-#define  CAN_TSR_TXOK2                       0x00020000U        /*!<Transmission OK of Mailbox 2 */
-#define  CAN_TSR_ALST2                       0x00040000U        /*!<Arbitration Lost for mailbox 2 */
-#define  CAN_TSR_TERR2                       0x00080000U        /*!<Transmission Error of Mailbox 2 */
-#define  CAN_TSR_ABRQ2                       0x00800000U        /*!<Abort Request for Mailbox 2 */
-#define  CAN_TSR_CODE                        0x03000000U        /*!<Mailbox Code */
-
-#define  CAN_TSR_TME                         0x1C000000U        /*!<TME[2:0] bits */
-#define  CAN_TSR_TME0                        0x04000000U        /*!<Transmit Mailbox 0 Empty */
-#define  CAN_TSR_TME1                        0x08000000U        /*!<Transmit Mailbox 1 Empty */
-#define  CAN_TSR_TME2                        0x10000000U        /*!<Transmit Mailbox 2 Empty */
-
-#define  CAN_TSR_LOW                         0xE0000000U        /*!<LOW[2:0] bits */
-#define  CAN_TSR_LOW0                        0x20000000U        /*!<Lowest Priority Flag for Mailbox 0 */
-#define  CAN_TSR_LOW1                        0x40000000U        /*!<Lowest Priority Flag for Mailbox 1 */
-#define  CAN_TSR_LOW2                        0x80000000U        /*!<Lowest Priority Flag for Mailbox 2 */
-
-/*******************  Bit definition for CAN_RF0R register  *******************/
-#define  CAN_RF0R_FMP0                       0x03U               /*!<FIFO 0 Message Pending */
-#define  CAN_RF0R_FULL0                      0x08U               /*!<FIFO 0 Full */
-#define  CAN_RF0R_FOVR0                      0x10U               /*!<FIFO 0 Overrun */
-#define  CAN_RF0R_RFOM0                      0x20U               /*!<Release FIFO 0 Output Mailbox */
-
-/*******************  Bit definition for CAN_RF1R register  *******************/
-#define  CAN_RF1R_FMP1                       0x03U               /*!<FIFO 1 Message Pending */
-#define  CAN_RF1R_FULL1                      0x08U               /*!<FIFO 1 Full */
-#define  CAN_RF1R_FOVR1                      0x10U               /*!<FIFO 1 Overrun */
-#define  CAN_RF1R_RFOM1                      0x20U               /*!<Release FIFO 1 Output Mailbox */
-
-/********************  Bit definition for CAN_IER register  *******************/
-#define  CAN_IER_TMEIE                       0x00000001U        /*!<Transmit Mailbox Empty Interrupt Enable */
-#define  CAN_IER_FMPIE0                      0x00000002U        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE0                       0x00000004U        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE0                      0x00000008U        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_FMPIE1                      0x00000010U        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE1                       0x00000020U        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE1                      0x00000040U        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error Warning Interrupt Enable */
-#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error Passive Interrupt Enable */
-#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-Off Interrupt Enable */
-#define  CAN_IER_LECIE                       0x00000800U        /*!<Last Error Code Interrupt Enable */
-#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error Interrupt Enable */
-#define  CAN_IER_WKUIE                       0x00010000U        /*!<Wakeup Interrupt Enable */
-#define  CAN_IER_SLKIE                       0x00020000U        /*!<Sleep Interrupt Enable */
-#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error warning interrupt enable */
-#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error passive interrupt enable */
-#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-off interrupt enable */
-#define  CAN_IER_LECIE                       0x00000800U        /*!<Last error code interrupt enable */
-#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error interrupt enable */
-
-
-/********************  Bit definition for CAN_ESR register  *******************/
-#define  CAN_ESR_EWGF                        0x00000001U        /*!<Error Warning Flag */
-#define  CAN_ESR_EPVF                        0x00000002U        /*!<Error Passive Flag */
-#define  CAN_ESR_BOFF                        0x00000004U        /*!<Bus-Off Flag */
-
-#define  CAN_ESR_LEC                         0x00000070U        /*!<LEC[2:0] bits (Last Error Code) */
-#define  CAN_ESR_LEC_0                       0x00000010U        /*!<Bit 0 */
-#define  CAN_ESR_LEC_1                       0x00000020U        /*!<Bit 1 */
-#define  CAN_ESR_LEC_2                       0x00000040U        /*!<Bit 2 */
-
-#define  CAN_ESR_TEC                         0x00FF0000U        /*!<Least significant byte of the 9-bit Transmit Error Counter */
-#define  CAN_ESR_REC                         0xFF000000U        /*!<Receive Error Counter */
-
-/*******************  Bit definition for CAN_BTR register  ********************/
-#define  CAN_BTR_BRP                         0x000003FFU        /*!<Baud Rate Prescaler */
-#define  CAN_BTR_TS1                         0x000F0000U        /*!<Time Segment 1 */
-#define  CAN_BTR_TS1_0                       0x00010000U        /*!<Bit 0 */
-#define  CAN_BTR_TS1_1                       0x00020000U        /*!<Bit 1 */
-#define  CAN_BTR_TS1_2                       0x00040000U        /*!<Bit 2 */
-#define  CAN_BTR_TS1_3                       0x00080000U        /*!<Bit 3 */
-#define  CAN_BTR_TS2                         0x00700000U        /*!<Time Segment 2 */
-#define  CAN_BTR_TS2_0                       0x00100000U        /*!<Bit 0 */
-#define  CAN_BTR_TS2_1                       0x00200000U        /*!<Bit 1 */
-#define  CAN_BTR_TS2_2                       0x00400000U        /*!<Bit 2 */
-#define  CAN_BTR_SJW                         0x03000000U        /*!<Resynchronization Jump Width */
-#define  CAN_BTR_SJW_0                       0x01000000U        /*!<Bit 0 */
-#define  CAN_BTR_SJW_1                       0x02000000U        /*!<Bit 1 */
-#define  CAN_BTR_LBKM                        0x40000000U        /*!<Loop Back Mode (Debug) */
-#define  CAN_BTR_SILM                        0x80000000U        /*!<Silent Mode */
-
-
-/*!<Mailbox registers */
-/******************  Bit definition for CAN_TI0R register  ********************/
-#define  CAN_TI0R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI0R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_TI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/******************  Bit definition for CAN_TDT0R register  *******************/
-#define  CAN_TDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT0R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/******************  Bit definition for CAN_TDL0R register  *******************/
-#define  CAN_TDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/******************  Bit definition for CAN_TDH0R register  *******************/
-#define  CAN_TDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI1R register  *******************/
-#define  CAN_TI1R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI1R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI1R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_TI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT1R register  ******************/
-#define  CAN_TDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT1R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL1R register  ******************/
-#define  CAN_TDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH1R register  ******************/
-#define  CAN_TDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI2R register  *******************/
-#define  CAN_TI2R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI2R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI2R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI2R_EXID                       0x001FFFF8U        /*!<Extended identifier */
-#define  CAN_TI2R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT2R register  ******************/  
-#define  CAN_TDT2R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT2R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT2R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL2R register  ******************/
-#define  CAN_TDL2R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL2R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL2R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL2R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH2R register  ******************/
-#define  CAN_TDH2R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH2R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH2R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH2R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI0R register  *******************/
-#define  CAN_RI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_RI0R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_RI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_RI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT0R register  ******************/
-#define  CAN_RDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_RDT0R_FMI                       0x0000FF00U        /*!<Filter Match Index */
-#define  CAN_RDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL0R register  ******************/
-#define  CAN_RDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_RDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_RDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_RDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH0R register  ******************/
-#define  CAN_RDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_RDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_RDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_RDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI1R register  *******************/
-#define  CAN_RI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_RI1R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_RI1R_EXID                       0x001FFFF8U        /*!<Extended identifier */
-#define  CAN_RI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT1R register  ******************/
-#define  CAN_RDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_RDT1R_FMI                       0x0000FF00U        /*!<Filter Match Index */
-#define  CAN_RDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL1R register  ******************/
-#define  CAN_RDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_RDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_RDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_RDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH1R register  ******************/
-#define  CAN_RDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_RDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_RDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_RDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*!<CAN filter registers */
-/*******************  Bit definition for CAN_FMR register  ********************/
-#define  CAN_FMR_FINIT                       0x01U               /*!<Filter Init Mode */
-#define  CAN_FMR_CAN2SB                      0x00003F00U        /*!<CAN2 start bank */
-
-/*******************  Bit definition for CAN_FM1R register  *******************/
-#define  CAN_FM1R_FBM                        0x0FFFFFFFU        /*!<Filter Mode */
-#define  CAN_FM1R_FBM0                       0x00000001U        /*!<Filter Init Mode bit 0 */
-#define  CAN_FM1R_FBM1                       0x00000002U        /*!<Filter Init Mode bit 1 */
-#define  CAN_FM1R_FBM2                       0x00000004U        /*!<Filter Init Mode bit 2 */
-#define  CAN_FM1R_FBM3                       0x00000008U        /*!<Filter Init Mode bit 3 */
-#define  CAN_FM1R_FBM4                       0x00000010U        /*!<Filter Init Mode bit 4 */
-#define  CAN_FM1R_FBM5                       0x00000020U        /*!<Filter Init Mode bit 5 */
-#define  CAN_FM1R_FBM6                       0x00000040U        /*!<Filter Init Mode bit 6 */
-#define  CAN_FM1R_FBM7                       0x00000080U        /*!<Filter Init Mode bit 7 */
-#define  CAN_FM1R_FBM8                       0x00000100U        /*!<Filter Init Mode bit 8 */
-#define  CAN_FM1R_FBM9                       0x00000200U        /*!<Filter Init Mode bit 9 */
-#define  CAN_FM1R_FBM10                      0x00000400U        /*!<Filter Init Mode bit 10 */
-#define  CAN_FM1R_FBM11                      0x00000800U        /*!<Filter Init Mode bit 11 */
-#define  CAN_FM1R_FBM12                      0x00001000U        /*!<Filter Init Mode bit 12 */
-#define  CAN_FM1R_FBM13                      0x00002000U        /*!<Filter Init Mode bit 13 */
-#define  CAN_FM1R_FBM14                      0x00004000U        /*!<Filter Init Mode bit 14 */
-#define  CAN_FM1R_FBM15                      0x00008000U        /*!<Filter Init Mode bit 15 */
-#define  CAN_FM1R_FBM16                      0x00010000U        /*!<Filter Init Mode bit 16 */
-#define  CAN_FM1R_FBM17                      0x00020000U        /*!<Filter Init Mode bit 17 */
-#define  CAN_FM1R_FBM18                      0x00040000U        /*!<Filter Init Mode bit 18 */
-#define  CAN_FM1R_FBM19                      0x00080000U        /*!<Filter Init Mode bit 19 */
-#define  CAN_FM1R_FBM20                      0x00100000U        /*!<Filter Init Mode bit 20 */
-#define  CAN_FM1R_FBM21                      0x00200000U        /*!<Filter Init Mode bit 21 */
-#define  CAN_FM1R_FBM22                      0x00400000U        /*!<Filter Init Mode bit 22 */
-#define  CAN_FM1R_FBM23                      0x00800000U        /*!<Filter Init Mode bit 23 */
-#define  CAN_FM1R_FBM24                      0x01000000U        /*!<Filter Init Mode bit 24 */
-#define  CAN_FM1R_FBM25                      0x02000000U        /*!<Filter Init Mode bit 25 */
-#define  CAN_FM1R_FBM26                      0x04000000U        /*!<Filter Init Mode bit 26 */
-#define  CAN_FM1R_FBM27                      0x08000000U        /*!<Filter Init Mode bit 27 */
-
-/*******************  Bit definition for CAN_FS1R register  *******************/
-#define  CAN_FS1R_FSC                        0x0FFFFFFFU        /*!<Filter Scale Configuration */
-#define  CAN_FS1R_FSC0                       0x00000001U        /*!<Filter Scale Configuration bit 0 */
-#define  CAN_FS1R_FSC1                       0x00000002U        /*!<Filter Scale Configuration bit 1 */
-#define  CAN_FS1R_FSC2                       0x00000004U        /*!<Filter Scale Configuration bit 2 */
-#define  CAN_FS1R_FSC3                       0x00000008U        /*!<Filter Scale Configuration bit 3 */
-#define  CAN_FS1R_FSC4                       0x00000010U        /*!<Filter Scale Configuration bit 4 */
-#define  CAN_FS1R_FSC5                       0x00000020U        /*!<Filter Scale Configuration bit 5 */
-#define  CAN_FS1R_FSC6                       0x00000040U        /*!<Filter Scale Configuration bit 6 */
-#define  CAN_FS1R_FSC7                       0x00000080U        /*!<Filter Scale Configuration bit 7 */
-#define  CAN_FS1R_FSC8                       0x00000100U        /*!<Filter Scale Configuration bit 8 */
-#define  CAN_FS1R_FSC9                       0x00000200U        /*!<Filter Scale Configuration bit 9 */
-#define  CAN_FS1R_FSC10                      0x00000400U        /*!<Filter Scale Configuration bit 10 */
-#define  CAN_FS1R_FSC11                      0x00000800U        /*!<Filter Scale Configuration bit 11 */
-#define  CAN_FS1R_FSC12                      0x00001000U        /*!<Filter Scale Configuration bit 12 */
-#define  CAN_FS1R_FSC13                      0x00002000U        /*!<Filter Scale Configuration bit 13 */
-#define  CAN_FS1R_FSC14                      0x00004000U        /*!<Filter Scale Configuration bit 14 */
-#define  CAN_FS1R_FSC15                      0x00008000U        /*!<Filter Scale Configuration bit 15 */
-#define  CAN_FS1R_FSC16                      0x00010000U        /*!<Filter Scale Configuration bit 16 */
-#define  CAN_FS1R_FSC17                      0x00020000U        /*!<Filter Scale Configuration bit 17 */
-#define  CAN_FS1R_FSC18                      0x00040000U        /*!<Filter Scale Configuration bit 18 */
-#define  CAN_FS1R_FSC19                      0x00080000U        /*!<Filter Scale Configuration bit 19 */
-#define  CAN_FS1R_FSC20                      0x00100000U        /*!<Filter Scale Configuration bit 20 */
-#define  CAN_FS1R_FSC21                      0x00200000U        /*!<Filter Scale Configuration bit 21 */
-#define  CAN_FS1R_FSC22                      0x00400000U        /*!<Filter Scale Configuration bit 22 */
-#define  CAN_FS1R_FSC23                      0x00800000U        /*!<Filter Scale Configuration bit 23 */
-#define  CAN_FS1R_FSC24                      0x01000000U        /*!<Filter Scale Configuration bit 24 */
-#define  CAN_FS1R_FSC25                      0x02000000U        /*!<Filter Scale Configuration bit 25 */
-#define  CAN_FS1R_FSC26                      0x04000000U        /*!<Filter Scale Configuration bit 26 */
-#define  CAN_FS1R_FSC27                      0x08000000U        /*!<Filter Scale Configuration bit 27 */
-
-/******************  Bit definition for CAN_FFA1R register  *******************/
-#define  CAN_FFA1R_FFA                        0x0FFFFFFFU        /*!<Filter FIFO Assignment */
-#define  CAN_FFA1R_FFA0                       0x00000001U        /*!<Filter FIFO Assignment bit 0 */
-#define  CAN_FFA1R_FFA1                       0x00000002U        /*!<Filter FIFO Assignment bit 1 */
-#define  CAN_FFA1R_FFA2                       0x00000004U        /*!<Filter FIFO Assignment bit 2 */
-#define  CAN_FFA1R_FFA3                       0x00000008U        /*!<Filter FIFO Assignment bit 3 */
-#define  CAN_FFA1R_FFA4                       0x00000010U        /*!<Filter FIFO Assignment bit 4 */
-#define  CAN_FFA1R_FFA5                       0x00000020U        /*!<Filter FIFO Assignment bit 5 */
-#define  CAN_FFA1R_FFA6                       0x00000040U        /*!<Filter FIFO Assignment bit 6 */
-#define  CAN_FFA1R_FFA7                       0x00000080U        /*!<Filter FIFO Assignment bit 7 */
-#define  CAN_FFA1R_FFA8                       0x00000100U        /*!<Filter FIFO Assignment bit 8 */
-#define  CAN_FFA1R_FFA9                       0x00000200U        /*!<Filter FIFO Assignment bit 9 */
-#define  CAN_FFA1R_FFA10                      0x00000400U        /*!<Filter FIFO Assignment bit 10 */
-#define  CAN_FFA1R_FFA11                      0x00000800U        /*!<Filter FIFO Assignment bit 11 */
-#define  CAN_FFA1R_FFA12                      0x00001000U        /*!<Filter FIFO Assignment bit 12 */
-#define  CAN_FFA1R_FFA13                      0x00002000U        /*!<Filter FIFO Assignment bit 13 */
-#define  CAN_FFA1R_FFA14                      0x00004000U        /*!<Filter FIFO Assignment bit 14 */
-#define  CAN_FFA1R_FFA15                      0x00008000U        /*!<Filter FIFO Assignment bit 15 */
-#define  CAN_FFA1R_FFA16                      0x00010000U        /*!<Filter FIFO Assignment bit 16 */
-#define  CAN_FFA1R_FFA17                      0x00020000U        /*!<Filter FIFO Assignment bit 17 */
-#define  CAN_FFA1R_FFA18                      0x00040000U        /*!<Filter FIFO Assignment bit 18 */
-#define  CAN_FFA1R_FFA19                      0x00080000U        /*!<Filter FIFO Assignment bit 19 */
-#define  CAN_FFA1R_FFA20                      0x00100000U        /*!<Filter FIFO Assignment bit 20 */
-#define  CAN_FFA1R_FFA21                      0x00200000U        /*!<Filter FIFO Assignment bit 21 */
-#define  CAN_FFA1R_FFA22                      0x00400000U        /*!<Filter FIFO Assignment bit 22 */
-#define  CAN_FFA1R_FFA23                      0x00800000U        /*!<Filter FIFO Assignment bit 23 */
-#define  CAN_FFA1R_FFA24                      0x01000000U        /*!<Filter FIFO Assignment bit 24 */
-#define  CAN_FFA1R_FFA25                      0x02000000U        /*!<Filter FIFO Assignment bit 25 */
-#define  CAN_FFA1R_FFA26                      0x04000000U        /*!<Filter FIFO Assignment bit 26 */
-#define  CAN_FFA1R_FFA27                      0x08000000U        /*!<Filter FIFO Assignment bit 27 */
-
-/*******************  Bit definition for CAN_FA1R register  *******************/
-#define  CAN_FA1R_FACT                        0x0FFFFFFFU        /*!<Filter Active */
-#define  CAN_FA1R_FACT0                       0x00000001U        /*!<Filter Active bit 0 */
-#define  CAN_FA1R_FACT1                       0x00000002U        /*!<Filter Active bit 1 */
-#define  CAN_FA1R_FACT2                       0x00000004U        /*!<Filter Active bit 2 */
-#define  CAN_FA1R_FACT3                       0x00000008U        /*!<Filter Active bit 3 */
-#define  CAN_FA1R_FACT4                       0x00000010U        /*!<Filter Active bit 4 */
-#define  CAN_FA1R_FACT5                       0x00000020U        /*!<Filter Active bit 5 */
-#define  CAN_FA1R_FACT6                       0x00000040U        /*!<Filter Active bit 6 */
-#define  CAN_FA1R_FACT7                       0x00000080U        /*!<Filter Active bit 7 */
-#define  CAN_FA1R_FACT8                       0x00000100U        /*!<Filter Active bit 8 */
-#define  CAN_FA1R_FACT9                       0x00000200U        /*!<Filter Active bit 9 */
-#define  CAN_FA1R_FACT10                      0x00000400U        /*!<Filter Active bit 10 */
-#define  CAN_FA1R_FACT11                      0x00000800U        /*!<Filter Active bit 11 */
-#define  CAN_FA1R_FACT12                      0x00001000U        /*!<Filter Active bit 12 */
-#define  CAN_FA1R_FACT13                      0x00002000U        /*!<Filter Active bit 13 */
-#define  CAN_FA1R_FACT14                      0x00004000U        /*!<Filter Active bit 14 */
-#define  CAN_FA1R_FACT15                      0x00008000U        /*!<Filter Active bit 15 */
-#define  CAN_FA1R_FACT16                      0x00010000U        /*!<Filter Active bit 16 */
-#define  CAN_FA1R_FACT17                      0x00020000U        /*!<Filter Active bit 17 */
-#define  CAN_FA1R_FACT18                      0x00040000U        /*!<Filter Active bit 18 */
-#define  CAN_FA1R_FACT19                      0x00080000U        /*!<Filter Active bit 19 */
-#define  CAN_FA1R_FACT20                      0x00100000U        /*!<Filter Active bit 20 */
-#define  CAN_FA1R_FACT21                      0x00200000U        /*!<Filter Active bit 21 */
-#define  CAN_FA1R_FACT22                      0x00400000U        /*!<Filter Active bit 22 */
-#define  CAN_FA1R_FACT23                      0x00800000U        /*!<Filter Active bit 23 */
-#define  CAN_FA1R_FACT24                      0x01000000U        /*!<Filter Active bit 24 */
-#define  CAN_FA1R_FACT25                      0x02000000U        /*!<Filter Active bit 25 */
-#define  CAN_FA1R_FACT26                      0x04000000U        /*!<Filter Active bit 26 */
-#define  CAN_FA1R_FACT27                      0x08000000U        /*!<Filter Active bit 27 */
-
-
-/*******************  Bit definition for CAN_F0R1 register  *******************/
-#define  CAN_F0R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F0R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F0R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F0R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F0R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F0R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F0R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F0R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F0R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F0R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F0R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F0R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F0R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F0R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F0R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F0R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F0R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F0R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F0R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F0R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F0R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F0R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F0R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F0R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F0R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F0R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F0R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F0R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F0R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F0R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F0R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F0R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R1 register  *******************/
-#define  CAN_F1R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F1R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F1R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F1R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F1R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F1R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F1R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F1R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F1R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F1R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F1R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F1R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F1R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F1R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F1R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F1R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F1R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F1R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F1R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F1R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F1R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F1R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F1R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F1R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F1R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F1R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F1R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F1R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F1R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F1R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F1R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F1R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R1 register  *******************/
-#define  CAN_F2R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F2R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F2R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F2R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F2R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F2R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F2R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F2R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F2R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F2R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F2R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F2R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F2R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F2R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F2R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F2R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F2R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F2R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F2R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F2R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F2R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F2R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F2R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F2R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F2R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F2R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F2R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F2R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F2R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F2R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F2R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F2R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R1 register  *******************/
-#define  CAN_F3R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F3R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F3R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F3R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F3R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F3R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F3R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F3R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F3R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F3R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F3R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F3R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F3R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F3R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F3R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F3R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F3R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F3R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F3R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F3R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F3R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F3R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F3R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F3R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F3R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F3R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F3R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F3R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F3R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F3R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F3R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F3R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R1 register  *******************/
-#define  CAN_F4R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F4R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F4R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F4R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F4R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F4R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F4R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F4R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F4R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F4R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F4R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F4R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F4R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F4R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F4R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F4R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F4R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F4R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F4R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F4R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F4R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F4R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F4R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F4R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F4R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F4R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F4R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F4R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F4R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F4R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F4R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F4R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R1 register  *******************/
-#define  CAN_F5R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F5R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F5R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F5R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F5R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F5R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F5R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F5R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F5R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F5R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F5R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F5R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F5R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F5R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F5R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F5R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F5R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F5R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F5R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F5R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F5R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F5R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F5R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F5R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F5R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F5R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F5R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F5R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F5R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F5R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F5R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F5R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R1 register  *******************/
-#define  CAN_F6R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F6R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F6R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F6R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F6R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F6R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F6R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F6R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F6R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F6R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F6R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F6R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F6R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F6R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F6R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F6R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F6R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F6R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F6R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F6R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F6R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F6R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F6R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F6R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F6R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F6R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F6R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F6R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F6R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F6R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F6R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F6R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R1 register  *******************/
-#define  CAN_F7R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F7R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F7R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F7R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F7R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F7R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F7R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F7R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F7R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F7R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F7R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F7R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F7R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F7R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F7R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F7R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F7R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F7R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F7R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F7R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F7R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F7R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F7R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F7R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F7R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F7R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F7R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F7R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F7R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F7R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F7R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F7R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R1 register  *******************/
-#define  CAN_F8R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F8R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F8R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F8R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F8R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F8R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F8R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F8R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F8R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F8R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F8R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F8R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F8R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F8R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F8R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F8R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F8R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F8R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F8R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F8R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F8R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F8R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F8R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F8R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F8R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F8R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F8R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F8R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F8R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F8R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F8R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F8R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R1 register  *******************/
-#define  CAN_F9R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F9R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F9R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F9R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F9R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F9R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F9R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F9R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F9R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F9R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F9R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F9R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F9R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F9R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F9R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F9R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F9R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F9R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F9R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F9R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F9R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F9R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F9R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F9R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F9R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F9R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F9R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F9R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F9R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F9R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F9R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F9R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R1 register  ******************/
-#define  CAN_F10R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F10R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F10R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F10R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F10R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F10R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F10R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F10R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F10R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F10R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F10R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F10R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F10R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F10R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F10R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F10R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F10R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F10R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F10R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F10R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F10R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F10R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F10R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F10R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F10R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F10R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F10R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F10R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F10R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F10R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F10R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F10R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R1 register  ******************/
-#define  CAN_F11R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F11R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F11R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F11R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F11R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F11R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F11R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F11R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F11R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F11R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F11R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F11R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F11R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F11R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F11R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F11R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F11R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F11R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F11R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F11R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F11R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F11R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F11R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F11R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F11R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F11R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F11R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F11R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F11R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F11R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F11R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F11R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R1 register  ******************/
-#define  CAN_F12R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F12R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F12R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F12R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F12R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F12R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F12R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F12R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F12R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F12R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F12R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F12R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F12R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F12R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F12R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F12R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F12R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F12R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F12R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F12R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F12R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F12R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F12R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F12R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F12R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F12R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F12R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F12R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F12R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F12R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F12R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F12R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R1 register  ******************/
-#define  CAN_F13R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F13R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F13R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F13R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F13R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F13R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F13R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F13R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F13R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F13R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F13R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F13R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F13R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F13R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F13R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F13R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F13R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F13R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F13R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F13R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F13R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F13R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F13R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F13R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F13R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F13R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F13R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F13R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F13R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F13R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F13R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F13R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F0R2 register  *******************/
-#define  CAN_F0R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F0R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F0R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F0R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F0R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F0R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F0R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F0R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F0R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F0R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F0R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F0R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F0R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F0R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F0R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F0R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F0R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F0R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F0R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F0R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F0R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F0R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F0R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F0R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F0R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F0R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F0R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F0R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F0R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F0R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F0R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F0R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R2 register  *******************/
-#define  CAN_F1R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F1R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F1R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F1R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F1R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F1R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F1R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F1R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F1R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F1R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F1R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F1R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F1R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F1R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F1R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F1R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F1R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F1R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F1R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F1R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F1R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F1R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F1R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F1R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F1R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F1R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F1R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F1R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F1R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F1R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F1R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F1R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R2 register  *******************/
-#define  CAN_F2R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F2R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F2R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F2R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F2R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F2R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F2R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F2R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F2R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F2R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F2R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F2R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F2R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F2R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F2R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F2R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F2R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F2R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F2R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F2R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F2R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F2R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F2R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F2R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F2R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F2R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F2R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F2R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F2R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F2R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F2R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F2R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R2 register  *******************/
-#define  CAN_F3R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F3R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F3R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F3R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F3R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F3R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F3R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F3R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F3R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F3R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F3R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F3R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F3R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F3R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F3R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F3R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F3R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F3R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F3R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F3R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F3R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F3R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F3R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F3R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F3R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F3R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F3R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F3R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F3R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F3R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F3R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F3R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R2 register  *******************/
-#define  CAN_F4R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F4R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F4R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F4R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F4R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F4R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F4R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F4R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F4R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F4R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F4R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F4R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F4R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F4R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F4R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F4R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F4R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F4R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F4R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F4R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F4R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F4R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F4R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F4R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F4R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F4R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F4R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F4R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F4R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F4R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F4R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F4R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R2 register  *******************/
-#define  CAN_F5R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F5R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F5R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F5R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F5R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F5R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F5R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F5R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F5R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F5R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F5R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F5R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F5R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F5R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F5R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F5R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F5R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F5R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F5R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F5R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F5R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F5R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F5R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F5R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F5R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F5R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F5R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F5R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F5R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F5R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F5R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F5R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R2 register  *******************/
-#define  CAN_F6R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F6R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F6R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F6R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F6R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F6R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F6R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F6R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F6R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F6R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F6R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F6R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F6R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F6R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F6R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F6R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F6R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F6R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F6R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F6R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F6R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F6R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F6R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F6R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F6R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F6R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F6R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F6R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F6R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F6R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F6R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F6R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R2 register  *******************/
-#define  CAN_F7R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F7R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F7R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F7R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F7R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F7R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F7R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F7R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F7R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F7R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F7R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F7R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F7R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F7R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F7R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F7R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F7R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F7R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F7R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F7R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F7R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F7R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F7R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F7R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F7R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F7R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F7R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F7R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F7R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F7R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F7R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F7R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R2 register  *******************/
-#define  CAN_F8R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F8R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F8R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F8R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F8R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F8R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F8R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F8R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F8R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F8R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F8R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F8R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F8R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F8R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F8R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F8R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F8R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F8R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F8R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F8R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F8R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F8R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F8R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F8R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F8R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F8R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F8R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F8R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F8R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F8R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F8R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F8R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R2 register  *******************/
-#define  CAN_F9R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F9R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F9R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F9R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F9R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F9R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F9R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F9R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F9R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F9R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F9R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F9R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F9R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F9R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F9R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F9R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F9R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F9R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F9R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F9R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F9R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F9R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F9R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F9R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F9R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F9R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F9R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F9R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F9R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F9R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F9R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F9R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R2 register  ******************/
-#define  CAN_F10R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F10R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F10R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F10R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F10R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F10R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F10R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F10R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F10R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F10R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F10R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F10R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F10R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F10R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F10R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F10R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F10R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F10R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F10R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F10R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F10R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F10R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F10R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F10R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F10R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F10R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F10R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F10R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F10R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F10R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F10R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F10R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R2 register  ******************/
-#define  CAN_F11R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F11R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F11R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F11R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F11R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F11R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F11R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F11R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F11R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F11R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F11R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F11R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F11R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F11R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F11R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F11R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F11R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F11R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F11R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F11R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F11R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F11R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F11R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F11R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F11R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F11R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F11R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F11R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F11R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F11R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F11R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F11R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R2 register  ******************/
-#define  CAN_F12R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F12R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F12R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F12R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F12R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F12R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F12R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F12R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F12R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F12R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F12R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F12R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F12R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F12R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F12R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F12R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F12R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F12R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F12R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F12R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F12R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F12R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F12R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F12R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F12R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F12R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F12R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F12R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F12R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F12R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F12R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F12R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R2 register  ******************/
-#define  CAN_F13R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F13R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F13R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F13R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F13R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F13R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F13R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F13R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F13R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F13R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F13R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F13R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F13R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F13R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F13R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F13R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F13R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F13R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F13R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F13R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F13R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F13R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F13R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F13R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F13R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F13R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F13R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F13R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F13R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F13R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F13R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F13R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          HDMI-CEC (CEC)                                    */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CEC_CR register  *********************/
-#define  CEC_CR_CECEN                        0x00000001U       /*!< CEC Enable                              */
-#define  CEC_CR_TXSOM                        0x00000002U       /*!< CEC Tx Start Of Message                 */
-#define  CEC_CR_TXEOM                        0x00000004U       /*!< CEC Tx End Of Message                   */
-
-/*******************  Bit definition for CEC_CFGR register  *******************/
-#define  CEC_CFGR_SFT                        0x00000007U       /*!< CEC Signal Free Time                    */
-#define  CEC_CFGR_RXTOL                      0x00000008U       /*!< CEC Tolerance                           */
-#define  CEC_CFGR_BRESTP                     0x00000010U       /*!< CEC Rx Stop                             */
-#define  CEC_CFGR_BREGEN                     0x00000020U       /*!< CEC Bit Rising Error generation         */
-#define  CEC_CFGR_LBPEGEN                    0x00000040U       /*!< CEC Long Bit Period Error generation    */
-#define  CEC_CFGR_SFTOPT                     0x00000100U       /*!< CEC Signal Free Time optional           */
-#define  CEC_CFGR_BRDNOGEN                   0x00000080U       /*!< CEC Broadcast No error generation       */
-#define  CEC_CFGR_OAR                        0x7FFF0000U       /*!< CEC Own Address                         */
-#define  CEC_CFGR_LSTN                       0x80000000U       /*!< CEC Listen mode                         */
-
-/*******************  Bit definition for CEC_TXDR register  *******************/
-#define  CEC_TXDR_TXD                        0x000000FFU       /*!< CEC Tx Data                              */
-
-/*******************  Bit definition for CEC_RXDR register  *******************/
-#define  CEC_TXDR_RXD                        0x000000FFU       /*!< CEC Rx Data                              */
-
-/*******************  Bit definition for CEC_ISR register  ********************/
-#define  CEC_ISR_RXBR                        0x00000001U       /*!< CEC Rx-Byte Received                      */
-#define  CEC_ISR_RXEND                       0x00000002U       /*!< CEC End Of Reception                      */
-#define  CEC_ISR_RXOVR                       0x00000004U       /*!< CEC Rx-Overrun                            */
-#define  CEC_ISR_BRE                         0x00000008U       /*!< CEC Rx Bit Rising Error                   */
-#define  CEC_ISR_SBPE                        0x00000010U       /*!< CEC Rx Short Bit period Error             */
-#define  CEC_ISR_LBPE                        0x00000020U       /*!< CEC Rx Long Bit period Error              */
-#define  CEC_ISR_RXACKE                      0x00000040U       /*!< CEC Rx Missing Acknowledge                */
-#define  CEC_ISR_ARBLST                      0x00000080U       /*!< CEC Arbitration Lost                      */
-#define  CEC_ISR_TXBR                        0x00000100U       /*!< CEC Tx Byte Request                       */
-#define  CEC_ISR_TXEND                       0x00000200U       /*!< CEC End of Transmission                   */
-#define  CEC_ISR_TXUDR                       0x00000400U       /*!< CEC Tx-Buffer Underrun                    */
-#define  CEC_ISR_TXERR                       0x00000800U       /*!< CEC Tx-Error                              */
-#define  CEC_ISR_TXACKE                      0x00001000U       /*!< CEC Tx Missing Acknowledge                */
-
-/*******************  Bit definition for CEC_IER register  ********************/
-#define  CEC_IER_RXBRIE                      0x00000001U       /*!< CEC Rx-Byte Received IT Enable            */
-#define  CEC_IER_RXENDIE                     0x00000002U       /*!< CEC End Of Reception IT Enable            */
-#define  CEC_IER_RXOVRIE                     0x00000004U       /*!< CEC Rx-Overrun IT Enable                  */
-#define  CEC_IER_BREIE                       0x00000008U       /*!< CEC Rx Bit Rising Error IT Enable         */
-#define  CEC_IER_SBPEIE                      0x00000010U       /*!< CEC Rx Short Bit period Error IT Enable   */
-#define  CEC_IER_LBPEIE                      0x00000020U       /*!< CEC Rx Long Bit period Error IT Enable    */
-#define  CEC_IER_RXACKEIE                    0x00000040U       /*!< CEC Rx Missing Acknowledge IT Enable      */
-#define  CEC_IER_ARBLSTIE                    0x00000080U       /*!< CEC Arbitration Lost IT Enable            */
-#define  CEC_IER_TXBRIE                      0x00000100U       /*!< CEC Tx Byte Request  IT Enable            */
-#define  CEC_IER_TXENDIE                     0x00000200U       /*!< CEC End of Transmission IT Enable         */
-#define  CEC_IER_TXUDRIE                     0x00000400U       /*!< CEC Tx-Buffer Underrun IT Enable          */
-#define  CEC_IER_TXERRIE                     0x00000800U       /*!< CEC Tx-Error IT Enable                    */
-#define  CEC_IER_TXACKEIE                    0x00001000U       /*!< CEC Tx Missing Acknowledge IT Enable      */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRC calculation unit                              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           0xFFFFFFFFU /*!< Data register bits */
-
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         0xFFU        /*!< General-purpose 8-bit data register bits */
-
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        0x01U        /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Digital to Analog Converter                           */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DAC_CR register  ********************/
-#define  DAC_CR_EN1                          0x00000001U        /*!<DAC channel1 enable */
-#define  DAC_CR_BOFF1                        0x00000002U        /*!<DAC channel1 output buffer disable */
-#define  DAC_CR_TEN1                         0x00000004U        /*!<DAC channel1 Trigger enable */
-
-#define  DAC_CR_TSEL1                        0x00000038U        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define  DAC_CR_TSEL1_0                      0x00000008U        /*!<Bit 0 */
-#define  DAC_CR_TSEL1_1                      0x00000010U        /*!<Bit 1 */
-#define  DAC_CR_TSEL1_2                      0x00000020U        /*!<Bit 2 */
-
-#define  DAC_CR_WAVE1                        0x000000C0U        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE1_0                      0x00000040U        /*!<Bit 0 */
-#define  DAC_CR_WAVE1_1                      0x00000080U        /*!<Bit 1 */
-
-#define  DAC_CR_MAMP1                        0x00000F00U        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP1_0                      0x00000100U        /*!<Bit 0 */
-#define  DAC_CR_MAMP1_1                      0x00000200U        /*!<Bit 1 */
-#define  DAC_CR_MAMP1_2                      0x00000400U        /*!<Bit 2 */
-#define  DAC_CR_MAMP1_3                      0x00000800U        /*!<Bit 3 */
-
-#define  DAC_CR_DMAEN1                       0x00001000U        /*!<DAC channel1 DMA enable */
-#define  DAC_CR_DMAUDRIE1                    0x00002000U        /*!<DAC channel1 DMA underrun interrupt enable*/
-#define  DAC_CR_EN2                          0x00010000U        /*!<DAC channel2 enable */
-#define  DAC_CR_BOFF2                        0x00020000U        /*!<DAC channel2 output buffer disable */
-#define  DAC_CR_TEN2                         0x00040000U        /*!<DAC channel2 Trigger enable */
-
-#define  DAC_CR_TSEL2                        0x00380000U        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define  DAC_CR_TSEL2_0                      0x00080000U        /*!<Bit 0 */
-#define  DAC_CR_TSEL2_1                      0x00100000U        /*!<Bit 1 */
-#define  DAC_CR_TSEL2_2                      0x00200000U        /*!<Bit 2 */
-
-#define  DAC_CR_WAVE2                        0x00C00000U        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE2_0                      0x00400000U        /*!<Bit 0 */
-#define  DAC_CR_WAVE2_1                      0x00800000U        /*!<Bit 1 */
-
-#define  DAC_CR_MAMP2                        0x0F000000U        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP2_0                      0x01000000U        /*!<Bit 0 */
-#define  DAC_CR_MAMP2_1                      0x02000000U        /*!<Bit 1 */
-#define  DAC_CR_MAMP2_2                      0x04000000U        /*!<Bit 2 */
-#define  DAC_CR_MAMP2_3                      0x08000000U        /*!<Bit 3 */
-
-#define  DAC_CR_DMAEN2                       0x10000000U        /*!<DAC channel2 DMA enabled */
-#define  DAC_CR_DMAUDRIE2                    0x20000000U        /*!<DAC channel2 DMA underrun interrupt enable*/
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define  DAC_SWTRIGR_SWTRIG1                 0x01U               /*!<DAC channel1 software trigger */
-#define  DAC_SWTRIGR_SWTRIG2                 0x02U               /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define  DAC_DHR12R1_DACC1DHR                0x0FFFU            /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define  DAC_DHR12L1_DACC1DHR                0xFFF0U            /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define  DAC_DHR8R1_DACC1DHR                 0xFFU               /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define  DAC_DHR12R2_DACC2DHR                0x0FFFU            /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define  DAC_DHR12L2_DACC2DHR                0xFFF0U            /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define  DAC_DHR8R2_DACC2DHR                 0xFFU               /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define  DAC_DHR12RD_DACC1DHR                0x00000FFFU        /*!<DAC channel1 12-bit Right aligned data */
-#define  DAC_DHR12RD_DACC2DHR                0x0FFF0000U        /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define  DAC_DHR12LD_DACC1DHR                0x0000FFF0U        /*!<DAC channel1 12-bit Left aligned data */
-#define  DAC_DHR12LD_DACC2DHR                0xFFF00000U        /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define  DAC_DHR8RD_DACC1DHR                 0x00FFU            /*!<DAC channel1 8-bit Right aligned data */
-#define  DAC_DHR8RD_DACC2DHR                 0xFF00U            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define  DAC_DOR1_DACC1DOR                   0x0FFFU            /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define  DAC_DOR2_DACC2DOR                   0x0FFFU            /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define  DAC_SR_DMAUDR1                      0x00002000U        /*!<DAC channel1 DMA underrun flag */
-#define  DAC_SR_DMAUDR2                      0x20000000U        /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 Debug MCU                                  */
-/*                                                                            */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    DCMI                                    */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DCMI_CR register  ******************/
-#define DCMI_CR_CAPTURE                      0x00000001U
-#define DCMI_CR_CM                           0x00000002U
-#define DCMI_CR_CROP                         0x00000004U
-#define DCMI_CR_JPEG                         0x00000008U
-#define DCMI_CR_ESS                          0x00000010U
-#define DCMI_CR_PCKPOL                       0x00000020U
-#define DCMI_CR_HSPOL                        0x00000040U
-#define DCMI_CR_VSPOL                        0x00000080U
-#define DCMI_CR_FCRC_0                       0x00000100U
-#define DCMI_CR_FCRC_1                       0x00000200U
-#define DCMI_CR_EDM_0                        0x00000400U
-#define DCMI_CR_EDM_1                        0x00000800U
-#define DCMI_CR_OUTEN                        0x00002000U
-#define DCMI_CR_ENABLE                       0x00004000U
-#define DCMI_CR_BSM_0                        0x00010000U
-#define DCMI_CR_BSM_1                        0x00020000U
-#define DCMI_CR_OEBS                         0x00040000U
-#define DCMI_CR_LSM                          0x00080000U
-#define DCMI_CR_OELS                         0x00100000U
-
-/********************  Bits definition for DCMI_SR register  ******************/
-#define DCMI_SR_HSYNC                        0x00000001U
-#define DCMI_SR_VSYNC                        0x00000002U
-#define DCMI_SR_FNE                          0x00000004U
-
-/********************  Bits definition for DCMI_RIS register  ****************/
-#define DCMI_RIS_FRAME_RIS                   0x00000001U
-#define DCMI_RIS_OVR_RIS                     0x00000002U
-#define DCMI_RIS_ERR_RIS                     0x00000004U
-#define DCMI_RIS_VSYNC_RIS                   0x00000008U
-#define DCMI_RIS_LINE_RIS                    0x00000010U
-/* Legacy defines */
-#define DCMI_RISR_FRAME_RIS                  DCMI_RIS_FRAME_RIS
-#define DCMI_RISR_OVR_RIS                    DCMI_RIS_OVR_RIS
-#define DCMI_RISR_ERR_RIS                    DCMI_RIS_ERR_RIS
-#define DCMI_RISR_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS
-#define DCMI_RISR_LINE_RIS                   DCMI_RIS_LINE_RIS
-#define DCMI_RISR_OVF_RIS                    DCMI_RIS_OVR_RIS
-
-/********************  Bits definition for DCMI_IER register  *****************/
-#define DCMI_IER_FRAME_IE                    0x00000001U
-#define DCMI_IER_OVR_IE                      0x00000002U
-#define DCMI_IER_ERR_IE                      0x00000004U
-#define DCMI_IER_VSYNC_IE                    0x00000008U
-#define DCMI_IER_LINE_IE                     0x00000010U
-/* Legacy defines */
-#define DCMI_IER_OVF_IE                      DCMI_IER_OVR_IE
-
-/********************  Bits definition for DCMI_MIS register  *****************/
-#define DCMI_MIS_FRAME_MIS                   0x00000001U
-#define DCMI_MIS_OVR_MIS                     0x00000002U
-#define DCMI_MIS_ERR_MIS                     0x00000004U
-#define DCMI_MIS_VSYNC_MIS                   0x00000008U
-#define DCMI_MIS_LINE_MIS                    0x00000010U
-
-/* Legacy defines */
-#define DCMI_MISR_FRAME_MIS                  DCMI_MIS_FRAME_MIS
-#define DCMI_MISR_OVF_MIS                    DCMI_MIS_OVR_MIS
-#define DCMI_MISR_ERR_MIS                    DCMI_MIS_ERR_MIS
-#define DCMI_MISR_VSYNC_MIS                  DCMI_MIS_VSYNC_MIS
-#define DCMI_MISR_LINE_MIS                   DCMI_MIS_LINE_MIS
-
-/********************  Bits definition for DCMI_ICR register  *****************/
-#define DCMI_ICR_FRAME_ISC                   0x00000001U
-#define DCMI_ICR_OVR_ISC                     0x00000002U
-#define DCMI_ICR_ERR_ISC                     0x00000004U
-#define DCMI_ICR_VSYNC_ISC                   0x00000008U
-#define DCMI_ICR_LINE_ISC                    0x00000010U
-
-/* Legacy defines */
-#define DCMI_ICR_OVF_ISC                     DCMI_ICR_OVR_ISC
-
-/********************  Bits definition for DCMI_ESCR register  ******************/
-#define DCMI_ESCR_FSC                        0x000000FFU
-#define DCMI_ESCR_LSC                        0x0000FF00U
-#define DCMI_ESCR_LEC                        0x00FF0000U
-#define DCMI_ESCR_FEC                        0xFF000000U
-
-/********************  Bits definition for DCMI_ESUR register  ******************/
-#define DCMI_ESUR_FSU                        0x000000FFU
-#define DCMI_ESUR_LSU                        0x0000FF00U
-#define DCMI_ESUR_LEU                        0x00FF0000U
-#define DCMI_ESUR_FEU                        0xFF000000U
-
-/********************  Bits definition for DCMI_CWSTRT register  ******************/
-#define DCMI_CWSTRT_HOFFCNT                  0x00003FFFU
-#define DCMI_CWSTRT_VST                      0x1FFF0000U
-
-/********************  Bits definition for DCMI_CWSIZE register  ******************/
-#define DCMI_CWSIZE_CAPCNT                   0x00003FFFU
-#define DCMI_CWSIZE_VLINE                    0x3FFF0000U
-
-/********************  Bits definition for DCMI_DR register  ******************/
-#define DCMI_DR_BYTE0                        0x000000FFU
-#define DCMI_DR_BYTE1                        0x0000FF00U
-#define DCMI_DR_BYTE2                        0x00FF0000U
-#define DCMI_DR_BYTE3                        0xFF000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                             DMA Controller                                 */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DMA_SxCR register  *****************/
-#define DMA_SxCR_CHSEL                       0x0E000000U
-#define DMA_SxCR_CHSEL_0                     0x02000000U
-#define DMA_SxCR_CHSEL_1                     0x04000000U
-#define DMA_SxCR_CHSEL_2                     0x08000000U
-#define DMA_SxCR_MBURST                      0x01800000U
-#define DMA_SxCR_MBURST_0                    0x00800000U
-#define DMA_SxCR_MBURST_1                    0x01000000U
-#define DMA_SxCR_PBURST                      0x00600000U
-#define DMA_SxCR_PBURST_0                    0x00200000U
-#define DMA_SxCR_PBURST_1                    0x00400000U
-#define DMA_SxCR_CT                          0x00080000U
-#define DMA_SxCR_DBM                         0x00040000U
-#define DMA_SxCR_PL                          0x00030000U
-#define DMA_SxCR_PL_0                        0x00010000U
-#define DMA_SxCR_PL_1                        0x00020000U
-#define DMA_SxCR_PINCOS                      0x00008000U
-#define DMA_SxCR_MSIZE                       0x00006000U
-#define DMA_SxCR_MSIZE_0                     0x00002000U
-#define DMA_SxCR_MSIZE_1                     0x00004000U
-#define DMA_SxCR_PSIZE                       0x00001800U
-#define DMA_SxCR_PSIZE_0                     0x00000800U
-#define DMA_SxCR_PSIZE_1                     0x00001000U
-#define DMA_SxCR_MINC                        0x00000400U
-#define DMA_SxCR_PINC                        0x00000200U
-#define DMA_SxCR_CIRC                        0x00000100U
-#define DMA_SxCR_DIR                         0x000000C0U
-#define DMA_SxCR_DIR_0                       0x00000040U
-#define DMA_SxCR_DIR_1                       0x00000080U
-#define DMA_SxCR_PFCTRL                      0x00000020U
-#define DMA_SxCR_TCIE                        0x00000010U
-#define DMA_SxCR_HTIE                        0x00000008U
-#define DMA_SxCR_TEIE                        0x00000004U
-#define DMA_SxCR_DMEIE                       0x00000002U
-#define DMA_SxCR_EN                          0x00000001U
-
-/* Legacy defines */
-#define DMA_SxCR_ACK                         0x00100000U
-
-/********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            0x0000FFFFU
-#define DMA_SxNDT_0                          0x00000001U
-#define DMA_SxNDT_1                          0x00000002U
-#define DMA_SxNDT_2                          0x00000004U
-#define DMA_SxNDT_3                          0x00000008U
-#define DMA_SxNDT_4                          0x00000010U
-#define DMA_SxNDT_5                          0x00000020U
-#define DMA_SxNDT_6                          0x00000040U
-#define DMA_SxNDT_7                          0x00000080U
-#define DMA_SxNDT_8                          0x00000100U
-#define DMA_SxNDT_9                          0x00000200U
-#define DMA_SxNDT_10                         0x00000400U
-#define DMA_SxNDT_11                         0x00000800U
-#define DMA_SxNDT_12                         0x00001000U
-#define DMA_SxNDT_13                         0x00002000U
-#define DMA_SxNDT_14                         0x00004000U
-#define DMA_SxNDT_15                         0x00008000U
-
-/********************  Bits definition for DMA_SxFCR register  ****************/ 
-#define DMA_SxFCR_FEIE                       0x00000080U
-#define DMA_SxFCR_FS                         0x00000038U
-#define DMA_SxFCR_FS_0                       0x00000008U
-#define DMA_SxFCR_FS_1                       0x00000010U
-#define DMA_SxFCR_FS_2                       0x00000020U
-#define DMA_SxFCR_DMDIS                      0x00000004U
-#define DMA_SxFCR_FTH                        0x00000003U
-#define DMA_SxFCR_FTH_0                      0x00000001U
-#define DMA_SxFCR_FTH_1                      0x00000002U
-
-/********************  Bits definition for DMA_LISR register  *****************/ 
-#define DMA_LISR_TCIF3                       0x08000000U
-#define DMA_LISR_HTIF3                       0x04000000U
-#define DMA_LISR_TEIF3                       0x02000000U
-#define DMA_LISR_DMEIF3                      0x01000000U
-#define DMA_LISR_FEIF3                       0x00400000U
-#define DMA_LISR_TCIF2                       0x00200000U
-#define DMA_LISR_HTIF2                       0x00100000U
-#define DMA_LISR_TEIF2                       0x00080000U
-#define DMA_LISR_DMEIF2                      0x00040000U
-#define DMA_LISR_FEIF2                       0x00010000U
-#define DMA_LISR_TCIF1                       0x00000800U
-#define DMA_LISR_HTIF1                       0x00000400U
-#define DMA_LISR_TEIF1                       0x00000200U
-#define DMA_LISR_DMEIF1                      0x00000100U
-#define DMA_LISR_FEIF1                       0x00000040U
-#define DMA_LISR_TCIF0                       0x00000020U
-#define DMA_LISR_HTIF0                       0x00000010U
-#define DMA_LISR_TEIF0                       0x00000008U
-#define DMA_LISR_DMEIF0                      0x00000004U
-#define DMA_LISR_FEIF0                       0x00000001U
-
-/********************  Bits definition for DMA_HISR register  *****************/ 
-#define DMA_HISR_TCIF7                       0x08000000U
-#define DMA_HISR_HTIF7                       0x04000000U
-#define DMA_HISR_TEIF7                       0x02000000U
-#define DMA_HISR_DMEIF7                      0x01000000U
-#define DMA_HISR_FEIF7                       0x00400000U
-#define DMA_HISR_TCIF6                       0x00200000U
-#define DMA_HISR_HTIF6                       0x00100000U
-#define DMA_HISR_TEIF6                       0x00080000U
-#define DMA_HISR_DMEIF6                      0x00040000U
-#define DMA_HISR_FEIF6                       0x00010000U
-#define DMA_HISR_TCIF5                       0x00000800U
-#define DMA_HISR_HTIF5                       0x00000400U
-#define DMA_HISR_TEIF5                       0x00000200U
-#define DMA_HISR_DMEIF5                      0x00000100U
-#define DMA_HISR_FEIF5                       0x00000040U
-#define DMA_HISR_TCIF4                       0x00000020U
-#define DMA_HISR_HTIF4                       0x00000010U
-#define DMA_HISR_TEIF4                       0x00000008U
-#define DMA_HISR_DMEIF4                      0x00000004U
-#define DMA_HISR_FEIF4                       0x00000001U
-
-/********************  Bits definition for DMA_LIFCR register  ****************/ 
-#define DMA_LIFCR_CTCIF3                     0x08000000U
-#define DMA_LIFCR_CHTIF3                     0x04000000U
-#define DMA_LIFCR_CTEIF3                     0x02000000U
-#define DMA_LIFCR_CDMEIF3                    0x01000000U
-#define DMA_LIFCR_CFEIF3                     0x00400000U
-#define DMA_LIFCR_CTCIF2                     0x00200000U
-#define DMA_LIFCR_CHTIF2                     0x00100000U
-#define DMA_LIFCR_CTEIF2                     0x00080000U
-#define DMA_LIFCR_CDMEIF2                    0x00040000U
-#define DMA_LIFCR_CFEIF2                     0x00010000U
-#define DMA_LIFCR_CTCIF1                     0x00000800U
-#define DMA_LIFCR_CHTIF1                     0x00000400U
-#define DMA_LIFCR_CTEIF1                     0x00000200U
-#define DMA_LIFCR_CDMEIF1                    0x00000100U
-#define DMA_LIFCR_CFEIF1                     0x00000040U
-#define DMA_LIFCR_CTCIF0                     0x00000020U
-#define DMA_LIFCR_CHTIF0                     0x00000010U
-#define DMA_LIFCR_CTEIF0                     0x00000008U
-#define DMA_LIFCR_CDMEIF0                    0x00000004U
-#define DMA_LIFCR_CFEIF0                     0x00000001U
-
-/********************  Bits definition for DMA_HIFCR  register  ****************/ 
-#define DMA_HIFCR_CTCIF7                     0x08000000U
-#define DMA_HIFCR_CHTIF7                     0x04000000U
-#define DMA_HIFCR_CTEIF7                     0x02000000U
-#define DMA_HIFCR_CDMEIF7                    0x01000000U
-#define DMA_HIFCR_CFEIF7                     0x00400000U
-#define DMA_HIFCR_CTCIF6                     0x00200000U
-#define DMA_HIFCR_CHTIF6                     0x00100000U
-#define DMA_HIFCR_CTEIF6                     0x00080000U
-#define DMA_HIFCR_CDMEIF6                    0x00040000U
-#define DMA_HIFCR_CFEIF6                     0x00010000U
-#define DMA_HIFCR_CTCIF5                     0x00000800U
-#define DMA_HIFCR_CHTIF5                     0x00000400U
-#define DMA_HIFCR_CTEIF5                     0x00000200U
-#define DMA_HIFCR_CDMEIF5                    0x00000100U
-#define DMA_HIFCR_CFEIF5                     0x00000040U
-#define DMA_HIFCR_CTCIF4                     0x00000020U
-#define DMA_HIFCR_CHTIF4                     0x00000010U
-#define DMA_HIFCR_CTEIF4                     0x00000008U
-#define DMA_HIFCR_CDMEIF4                    0x00000004U
-#define DMA_HIFCR_CFEIF4                     0x00000001U
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                    External Interrupt/Event Controller                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    FLASH                                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    0x0000000FU
-#define FLASH_ACR_LATENCY_0WS                0x00000000U
-#define FLASH_ACR_LATENCY_1WS                0x00000001U
-#define FLASH_ACR_LATENCY_2WS                0x00000002U
-#define FLASH_ACR_LATENCY_3WS                0x00000003U
-#define FLASH_ACR_LATENCY_4WS                0x00000004U
-#define FLASH_ACR_LATENCY_5WS                0x00000005U
-#define FLASH_ACR_LATENCY_6WS                0x00000006U
-#define FLASH_ACR_LATENCY_7WS                0x00000007U
-#define FLASH_ACR_LATENCY_8WS                0x00000008U
-#define FLASH_ACR_LATENCY_9WS                0x00000009U
-#define FLASH_ACR_LATENCY_10WS               0x0000000AU
-#define FLASH_ACR_LATENCY_11WS               0x0000000BU
-#define FLASH_ACR_LATENCY_12WS               0x0000000CU
-#define FLASH_ACR_LATENCY_13WS               0x0000000DU
-#define FLASH_ACR_LATENCY_14WS               0x0000000EU
-#define FLASH_ACR_LATENCY_15WS               0x0000000FU
-#define FLASH_ACR_PRFTEN                     0x00000100U
-#define FLASH_ACR_ICEN                       0x00000200U
-#define FLASH_ACR_DCEN                       0x00000400U
-#define FLASH_ACR_ICRST                      0x00000800U
-#define FLASH_ACR_DCRST                      0x00001000U
-#define FLASH_ACR_BYTE0_ADDRESS              0x40023C00U
-#define FLASH_ACR_BYTE2_ADDRESS              0x40023C03U
-
-/*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         0x00000001U
-#define FLASH_SR_SOP                         0x00000002U
-#define FLASH_SR_WRPERR                      0x00000010U
-#define FLASH_SR_PGAERR                      0x00000020U
-#define FLASH_SR_PGPERR                      0x00000040U
-#define FLASH_SR_PGSERR                      0x00000080U
-#define FLASH_SR_BSY                         0x00010000U
-
-/*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          0x00000001U
-#define FLASH_CR_SER                         0x00000002U
-#define FLASH_CR_MER                         0x00000004U
-#define FLASH_CR_MER1                        FLASH_CR_MER
-#define FLASH_CR_SNB                         0x000000F8U
-#define FLASH_CR_SNB_0                       0x00000008U
-#define FLASH_CR_SNB_1                       0x00000010U
-#define FLASH_CR_SNB_2                       0x00000020U
-#define FLASH_CR_SNB_3                       0x00000040U
-#define FLASH_CR_SNB_4                       0x00000080U
-#define FLASH_CR_PSIZE                       0x00000300U
-#define FLASH_CR_PSIZE_0                     0x00000100U
-#define FLASH_CR_PSIZE_1                     0x00000200U
-#define FLASH_CR_MER2                        0x00008000U
-#define FLASH_CR_STRT                        0x00010000U
-#define FLASH_CR_EOPIE                       0x01000000U
-#define FLASH_CR_LOCK                        0x80000000U
-
-/*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                 0x00000001U
-#define FLASH_OPTCR_OPTSTRT                 0x00000002U
-#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
-#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
-#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
-#define FLASH_OPTCR_BFB2                    0x00000010U
-#define FLASH_OPTCR_WDG_SW                  0x00000020U
-#define FLASH_OPTCR_nRST_STOP               0x00000040U
-#define FLASH_OPTCR_nRST_STDBY              0x00000080U
-#define FLASH_OPTCR_RDP                     0x0000FF00U
-#define FLASH_OPTCR_RDP_0                   0x00000100U
-#define FLASH_OPTCR_RDP_1                   0x00000200U
-#define FLASH_OPTCR_RDP_2                   0x00000400U
-#define FLASH_OPTCR_RDP_3                   0x00000800U
-#define FLASH_OPTCR_RDP_4                   0x00001000U
-#define FLASH_OPTCR_RDP_5                   0x00002000U
-#define FLASH_OPTCR_RDP_6                   0x00004000U
-#define FLASH_OPTCR_RDP_7                   0x00008000U
-#define FLASH_OPTCR_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR_nWRP_0                  0x00010000U
-#define FLASH_OPTCR_nWRP_1                  0x00020000U
-#define FLASH_OPTCR_nWRP_2                  0x00040000U
-#define FLASH_OPTCR_nWRP_3                  0x00080000U
-#define FLASH_OPTCR_nWRP_4                  0x00100000U
-#define FLASH_OPTCR_nWRP_5                  0x00200000U
-#define FLASH_OPTCR_nWRP_6                  0x00400000U
-#define FLASH_OPTCR_nWRP_7                  0x00800000U
-#define FLASH_OPTCR_nWRP_8                  0x01000000U
-#define FLASH_OPTCR_nWRP_9                  0x02000000U
-#define FLASH_OPTCR_nWRP_10                 0x04000000U
-#define FLASH_OPTCR_nWRP_11                 0x08000000U
-#define FLASH_OPTCR_DB1M                    0x40000000U 
-#define FLASH_OPTCR_SPRMOD                  0x80000000U 
-                                             
-/******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR1_nWRP_0                  0x00010000U
-#define FLASH_OPTCR1_nWRP_1                  0x00020000U
-#define FLASH_OPTCR1_nWRP_2                  0x00040000U
-#define FLASH_OPTCR1_nWRP_3                  0x00080000U
-#define FLASH_OPTCR1_nWRP_4                  0x00100000U
-#define FLASH_OPTCR1_nWRP_5                  0x00200000U
-#define FLASH_OPTCR1_nWRP_6                  0x00400000U
-#define FLASH_OPTCR1_nWRP_7                  0x00800000U
-#define FLASH_OPTCR1_nWRP_8                  0x01000000U
-#define FLASH_OPTCR1_nWRP_9                  0x02000000U
-#define FLASH_OPTCR1_nWRP_10                 0x04000000U
-#define FLASH_OPTCR1_nWRP_11                 0x08000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Flexible Memory Controller                        */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for FMC_BCR1 register  *******************/
-#define  FMC_BCR1_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR1_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FMC_BCR1_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR1_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR1_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FMC_BCR1_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR1_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR1_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_BCR1_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR1_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR1_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR1_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR1_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR1_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR1_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR1_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR1_CPSIZE                    0x00070000U        /*!<CRAM page size             */
-#define  FMC_BCR1_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FMC_BCR1_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FMC_BCR1_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FMC_BCR1_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-#define  FMC_BCR1_CCLKEN                    0x00100000U        /*!<Continous clock enable     */
-#define  FMC_BCR1_WFDIS                     0x00200000U        /*!<Write FIFO Disable         */
-
-/******************  Bit definition for FMC_BCR2 register  *******************/
-#define  FMC_BCR2_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR2_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FMC_BCR2_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR2_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR2_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FMC_BCR2_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR2_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR2_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_BCR2_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR2_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR2_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR2_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR2_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR2_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR2_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR2_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR2_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FMC_BCR3 register  *******************/
-#define  FMC_BCR3_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR3_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FMC_BCR3_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR3_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR3_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FMC_BCR3_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR3_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR3_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_BCR3_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR3_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR3_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR3_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR3_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR3_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR3_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR3_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR3_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FMC_BCR4 register  *******************/
-#define  FMC_BCR4_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR4_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FMC_BCR4_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR4_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR4_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FMC_BCR4_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR4_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR4_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_BCR4_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR4_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR4_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR4_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR4_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR4_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR4_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR4_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR4_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FMC_BTR1 register  ******************/
-#define  FMC_BTR1_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR1_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR1_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR1_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR1_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BTR1_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
-#define  FMC_BTR1_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR1_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR1_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR1_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BTR1_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR1_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR1_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR1_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR1_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR1_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR1_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR1_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR1_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BTR1_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR1_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR1_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR1_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR1_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BTR1_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR1_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR1_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR1_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR1_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FMC_BTR1_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR1_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR1_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR1_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR1_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FMC_BTR1_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR1_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR1_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BTR2 register  *******************/
-#define  FMC_BTR2_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR2_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR2_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR2_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR2_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BTR2_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR2_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR2_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR2_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR2_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BTR2_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR2_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR2_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR2_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR2_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR2_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR2_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR2_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR2_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BTR2_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR2_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR2_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR2_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR2_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BTR2_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR2_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR2_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR2_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR2_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FMC_BTR2_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR2_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR2_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR2_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR2_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FMC_BTR2_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR2_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR2_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/*******************  Bit definition for FMC_BTR3 register  *******************/
-#define  FMC_BTR3_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR3_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR3_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR3_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR3_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BTR3_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR3_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR3_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR3_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR3_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BTR3_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR3_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR3_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR3_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR3_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR3_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR3_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR3_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR3_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BTR3_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR3_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR3_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR3_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR3_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BTR3_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR3_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR3_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR3_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR3_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FMC_BTR3_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR3_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR3_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR3_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR3_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FMC_BTR3_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR3_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR3_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BTR4 register  *******************/
-#define  FMC_BTR4_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR4_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR4_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR4_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR4_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BTR4_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR4_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR4_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR4_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR4_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BTR4_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR4_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR4_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR4_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR4_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR4_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR4_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR4_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR4_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BTR4_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR4_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR4_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR4_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR4_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BTR4_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR4_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR4_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR4_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR4_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FMC_BTR4_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR4_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR4_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR4_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR4_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FMC_BTR4_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR4_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR4_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR1 register  ******************/
-#define  FMC_BWTR1_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR1_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR1_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR1_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR1_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BWTR1_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR1_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR1_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR1_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR1_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BWTR1_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR1_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR1_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR1_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR1_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR1_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR1_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR1_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR1_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BWTR1_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR1_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR1_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR1_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR1_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BWTR1_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR1_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR1_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR2 register  ******************/
-#define  FMC_BWTR2_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR2_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR2_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR2_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR2_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BWTR2_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR2_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR2_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR2_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR2_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BWTR2_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR2_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR2_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR2_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR2_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR2_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR2_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR2_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR2_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BWTR2_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR2_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR2_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR2_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR2_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BWTR2_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR2_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR2_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR3 register  ******************/
-#define  FMC_BWTR3_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR3_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR3_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR3_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR3_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BWTR3_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR3_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR3_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR3_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR3_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BWTR3_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR3_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR3_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR3_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR3_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR3_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR3_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR3_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR3_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BWTR3_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR3_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR3_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR3_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR3_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BWTR3_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR3_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR3_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR4 register  ******************/
-#define  FMC_BWTR4_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR4_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR4_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR4_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR4_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BWTR4_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR4_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR4_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR4_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR4_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BWTR4_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR4_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR4_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR4_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR4_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR4_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR4_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR4_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR4_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BWTR4_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR4_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR4_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR4_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR4_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BWTR4_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR4_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR4_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_PCR register  *******************/
-#define  FMC_PCR_PWAITEN                   0x00000002U        /*!<Wait feature enable bit                   */
-#define  FMC_PCR_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FMC_PCR_PTYP                      0x00000008U        /*!<Memory type                               */
-
-#define  FMC_PCR_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FMC_PCR_PWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_PCR_PWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_PCR_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit          */
-
-#define  FMC_PCR_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay)          */
-#define  FMC_PCR_TCLR_0                    0x00000200U        /*!<Bit 0 */
-#define  FMC_PCR_TCLR_1                    0x00000400U        /*!<Bit 1 */
-#define  FMC_PCR_TCLR_2                    0x00000800U        /*!<Bit 2 */
-#define  FMC_PCR_TCLR_3                    0x00001000U        /*!<Bit 3 */
-
-#define  FMC_PCR_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay)           */
-#define  FMC_PCR_TAR_0                     0x00002000U        /*!<Bit 0 */
-#define  FMC_PCR_TAR_1                     0x00004000U        /*!<Bit 1 */
-#define  FMC_PCR_TAR_2                     0x00008000U        /*!<Bit 2 */
-#define  FMC_PCR_TAR_3                     0x00010000U        /*!<Bit 3 */
-
-#define  FMC_PCR_ECCPS                     0x000E0000U        /*!<ECCPS[1:0] bits (ECC page size)           */
-#define  FMC_PCR_ECCPS_0                   0x00020000U        /*!<Bit 0 */
-#define  FMC_PCR_ECCPS_1                   0x00040000U        /*!<Bit 1 */
-#define  FMC_PCR_ECCPS_2                   0x00080000U        /*!<Bit 2 */
-
-/*******************  Bit definition for FMC_SR register  *******************/
-#define  FMC_SR_IRS                        0x01U               /*!<Interrupt Rising Edge status                */
-#define  FMC_SR_ILS                        0x02U               /*!<Interrupt Level status                      */
-#define  FMC_SR_IFS                        0x04U               /*!<Interrupt Falling Edge status               */
-#define  FMC_SR_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FMC_SR_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit        */
-#define  FMC_SR_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FMC_SR_FEMPT                      0x40U               /*!<FIFO empty                                  */
-
-/******************  Bit definition for FMC_PMEM register  ******************/
-#define  FMC_PMEM_MEMSET2                  0x000000FFU        /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
-#define  FMC_PMEM_MEMSET2_0                0x00000001U        /*!<Bit 0 */
-#define  FMC_PMEM_MEMSET2_1                0x00000002U        /*!<Bit 1 */
-#define  FMC_PMEM_MEMSET2_2                0x00000004U        /*!<Bit 2 */
-#define  FMC_PMEM_MEMSET2_3                0x00000008U        /*!<Bit 3 */
-#define  FMC_PMEM_MEMSET2_4                0x00000010U        /*!<Bit 4 */
-#define  FMC_PMEM_MEMSET2_5                0x00000020U        /*!<Bit 5 */
-#define  FMC_PMEM_MEMSET2_6                0x00000040U        /*!<Bit 6 */
-#define  FMC_PMEM_MEMSET2_7                0x00000080U        /*!<Bit 7 */
-
-#define  FMC_PMEM_MEMWAIT2                 0x0000FF00U        /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
-#define  FMC_PMEM_MEMWAIT2_0               0x00000100U        /*!<Bit 0 */
-#define  FMC_PMEM_MEMWAIT2_1               0x00000200U        /*!<Bit 1 */
-#define  FMC_PMEM_MEMWAIT2_2               0x00000400U        /*!<Bit 2 */
-#define  FMC_PMEM_MEMWAIT2_3               0x00000800U        /*!<Bit 3 */
-#define  FMC_PMEM_MEMWAIT2_4               0x00001000U        /*!<Bit 4 */
-#define  FMC_PMEM_MEMWAIT2_5               0x00002000U        /*!<Bit 5 */
-#define  FMC_PMEM_MEMWAIT2_6               0x00004000U        /*!<Bit 6 */
-#define  FMC_PMEM_MEMWAIT2_7               0x00008000U        /*!<Bit 7 */
-
-#define  FMC_PMEM_MEMHOLD2                 0x00FF0000U        /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
-#define  FMC_PMEM_MEMHOLD2_0               0x00010000U        /*!<Bit 0 */
-#define  FMC_PMEM_MEMHOLD2_1               0x00020000U        /*!<Bit 1 */
-#define  FMC_PMEM_MEMHOLD2_2               0x00040000U        /*!<Bit 2 */
-#define  FMC_PMEM_MEMHOLD2_3               0x00080000U        /*!<Bit 3 */
-#define  FMC_PMEM_MEMHOLD2_4               0x00100000U        /*!<Bit 4 */
-#define  FMC_PMEM_MEMHOLD2_5               0x00200000U        /*!<Bit 5 */
-#define  FMC_PMEM_MEMHOLD2_6               0x00400000U        /*!<Bit 6 */
-#define  FMC_PMEM_MEMHOLD2_7               0x00800000U        /*!<Bit 7 */
-
-#define  FMC_PMEM_MEMHIZ2                  0xFF000000U        /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
-#define  FMC_PMEM_MEMHIZ2_0                0x01000000U        /*!<Bit 0 */
-#define  FMC_PMEM_MEMHIZ2_1                0x02000000U        /*!<Bit 1 */
-#define  FMC_PMEM_MEMHIZ2_2                0x04000000U        /*!<Bit 2 */
-#define  FMC_PMEM_MEMHIZ2_3                0x08000000U        /*!<Bit 3 */
-#define  FMC_PMEM_MEMHIZ2_4                0x10000000U        /*!<Bit 4 */
-#define  FMC_PMEM_MEMHIZ2_5                0x20000000U        /*!<Bit 5 */
-#define  FMC_PMEM_MEMHIZ2_6                0x40000000U        /*!<Bit 6 */
-#define  FMC_PMEM_MEMHIZ2_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_PATT register  ******************/
-#define  FMC_PATT_ATTSET2                  0x000000FFU        /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
-#define  FMC_PATT_ATTSET2_0                0x00000001U        /*!<Bit 0 */
-#define  FMC_PATT_ATTSET2_1                0x00000002U        /*!<Bit 1 */
-#define  FMC_PATT_ATTSET2_2                0x00000004U        /*!<Bit 2 */
-#define  FMC_PATT_ATTSET2_3                0x00000008U        /*!<Bit 3 */
-#define  FMC_PATT_ATTSET2_4                0x00000010U        /*!<Bit 4 */
-#define  FMC_PATT_ATTSET2_5                0x00000020U        /*!<Bit 5 */
-#define  FMC_PATT_ATTSET2_6                0x00000040U        /*!<Bit 6 */
-#define  FMC_PATT_ATTSET2_7                0x00000080U        /*!<Bit 7 */
-
-#define  FMC_PATT_ATTWAIT2                 0x0000FF00U        /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
-#define  FMC_PATT_ATTWAIT2_0               0x00000100U        /*!<Bit 0 */
-#define  FMC_PATT_ATTWAIT2_1               0x00000200U        /*!<Bit 1 */
-#define  FMC_PATT_ATTWAIT2_2               0x00000400U        /*!<Bit 2 */
-#define  FMC_PATT_ATTWAIT2_3               0x00000800U        /*!<Bit 3 */
-#define  FMC_PATT_ATTWAIT2_4               0x00001000U        /*!<Bit 4 */
-#define  FMC_PATT_ATTWAIT2_5               0x00002000U        /*!<Bit 5 */
-#define  FMC_PATT_ATTWAIT2_6               0x00004000U        /*!<Bit 6 */
-#define  FMC_PATT_ATTWAIT2_7               0x00008000U        /*!<Bit 7 */
-
-#define  FMC_PATT_ATTHOLD2                 0x00FF0000U        /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
-#define  FMC_PATT_ATTHOLD2_0               0x00010000U        /*!<Bit 0 */
-#define  FMC_PATT_ATTHOLD2_1               0x00020000U        /*!<Bit 1 */
-#define  FMC_PATT_ATTHOLD2_2               0x00040000U        /*!<Bit 2 */
-#define  FMC_PATT_ATTHOLD2_3               0x00080000U        /*!<Bit 3 */
-#define  FMC_PATT_ATTHOLD2_4               0x00100000U        /*!<Bit 4 */
-#define  FMC_PATT_ATTHOLD2_5               0x00200000U        /*!<Bit 5 */
-#define  FMC_PATT_ATTHOLD2_6               0x00400000U        /*!<Bit 6 */
-#define  FMC_PATT_ATTHOLD2_7               0x00800000U        /*!<Bit 7 */
-
-#define  FMC_PATT_ATTHIZ2                  0xFF000000U        /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
-#define  FMC_PATT_ATTHIZ2_0                0x01000000U        /*!<Bit 0 */
-#define  FMC_PATT_ATTHIZ2_1                0x02000000U        /*!<Bit 1 */
-#define  FMC_PATT_ATTHIZ2_2                0x04000000U        /*!<Bit 2 */
-#define  FMC_PATT_ATTHIZ2_3                0x08000000U        /*!<Bit 3 */
-#define  FMC_PATT_ATTHIZ2_4                0x10000000U        /*!<Bit 4 */
-#define  FMC_PATT_ATTHIZ2_5                0x20000000U        /*!<Bit 5 */
-#define  FMC_PATT_ATTHIZ2_6                0x40000000U        /*!<Bit 6 */
-#define  FMC_PATT_ATTHIZ2_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_ECCR register  ******************/
-#define  FMC_ECCR_ECC2                     0xFFFFFFFFU        /*!<ECC result */
-
-/******************  Bit definition for FMC_SDCR1 register  ******************/
-#define  FMC_SDCR1_NC                       0x00000003U        /*!<NC[1:0] bits (Number of column bits) */
-#define  FMC_SDCR1_NC_0                     0x00000001U        /*!<Bit 0 */
-#define  FMC_SDCR1_NC_1                     0x00000002U        /*!<Bit 1 */
-
-#define  FMC_SDCR1_NR                       0x0000000CU        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR1_NR_0                     0x00000004U        /*!<Bit 0 */
-#define  FMC_SDCR1_NR_1                     0x00000008U        /*!<Bit 1 */
-
-#define  FMC_SDCR1_MWID                     0x00000030U        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR1_MWID_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDCR1_MWID_1                   0x00000020U        /*!<Bit 1 */
-
-#define  FMC_SDCR1_NB                       0x00000040U        /*!<Number of internal bank */
-
-#define  FMC_SDCR1_CAS                      0x00000180U        /*!<CAS[1:0] bits (CAS latency) */
-#define  FMC_SDCR1_CAS_0                    0x00000080U        /*!<Bit 0 */
-#define  FMC_SDCR1_CAS_1                    0x00000100U        /*!<Bit 1 */
-
-#define  FMC_SDCR1_WP                       0x00000200U        /*!<Write protection */
-
-#define  FMC_SDCR1_SDCLK                    0x00000C00U        /*!<SDRAM clock configuration */
-#define  FMC_SDCR1_SDCLK_0                  0x00000400U        /*!<Bit 0 */
-#define  FMC_SDCR1_SDCLK_1                  0x00000800U        /*!<Bit 1 */
-
-#define  FMC_SDCR1_RBURST                   0x00001000U        /*!<Read burst */
-
-#define  FMC_SDCR1_RPIPE                    0x00006000U        /*!<Write protection */
-#define  FMC_SDCR1_RPIPE_0                  0x00002000U        /*!<Bit 0 */
-#define  FMC_SDCR1_RPIPE_1                  0x00004000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_SDCR2 register  ******************/
-#define  FMC_SDCR2_NC                       0x00000003U        /*!<NC[1:0] bits (Number of column bits) */
-#define  FMC_SDCR2_NC_0                     0x00000001U        /*!<Bit 0 */
-#define  FMC_SDCR2_NC_1                     0x00000002U        /*!<Bit 1 */
-
-#define  FMC_SDCR2_NR                       0x0000000CU        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR2_NR_0                     0x00000004U        /*!<Bit 0 */
-#define  FMC_SDCR2_NR_1                     0x00000008U        /*!<Bit 1 */
-
-#define  FMC_SDCR2_MWID                     0x00000030U        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR2_MWID_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDCR2_MWID_1                   0x00000020U        /*!<Bit 1 */
-
-#define  FMC_SDCR2_NB                       0x00000040U        /*!<Number of internal bank */
-
-#define  FMC_SDCR2_CAS                      0x00000180U        /*!<CAS[1:0] bits (CAS latency) */
-#define  FMC_SDCR2_CAS_0                    0x00000080U        /*!<Bit 0 */
-#define  FMC_SDCR2_CAS_1                    0x00000100U        /*!<Bit 1 */
-
-#define  FMC_SDCR2_WP                       0x00000200U        /*!<Write protection */
-
-#define  FMC_SDCR2_SDCLK                    0x00000C00U        /*!<SDCLK[1:0] (SDRAM clock configuration) */
-#define  FMC_SDCR2_SDCLK_0                  0x00000400U        /*!<Bit 0 */
-#define  FMC_SDCR2_SDCLK_1                  0x00000800U        /*!<Bit 1 */
-
-#define  FMC_SDCR2_RBURST                   0x00001000U        /*!<Read burst */
-
-#define  FMC_SDCR2_RPIPE                    0x00006000U        /*!<RPIPE[1:0](Read pipe) */
-#define  FMC_SDCR2_RPIPE_0                  0x00002000U        /*!<Bit 0 */
-#define  FMC_SDCR2_RPIPE_1                  0x00004000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_SDTR1 register  ******************/
-#define  FMC_SDTR1_TMRD                     0x0000000FU        /*!<TMRD[3:0] bits (Load mode register to active) */
-#define  FMC_SDTR1_TMRD_0                   0x00000001U        /*!<Bit 0 */
-#define  FMC_SDTR1_TMRD_1                   0x00000002U        /*!<Bit 1 */
-#define  FMC_SDTR1_TMRD_2                   0x00000004U        /*!<Bit 2 */
-#define  FMC_SDTR1_TMRD_3                   0x00000008U        /*!<Bit 3 */
-                                            
-#define  FMC_SDTR1_TXSR                     0x000000F0U        /*!<TXSR[3:0] bits (Exit self refresh) */
-#define  FMC_SDTR1_TXSR_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDTR1_TXSR_1                   0x00000020U        /*!<Bit 1 */
-#define  FMC_SDTR1_TXSR_2                   0x00000040U        /*!<Bit 2 */
-#define  FMC_SDTR1_TXSR_3                   0x00000080U        /*!<Bit 3 */
-
-#define  FMC_SDTR1_TRAS                     0x00000F00U        /*!<TRAS[3:0] bits (Self refresh time) */
-#define  FMC_SDTR1_TRAS_0                   0x00000100U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRAS_1                   0x00000200U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRAS_2                   0x00000400U        /*!<Bit 2 */
-#define  FMC_SDTR1_TRAS_3                   0x00000800U        /*!<Bit 3 */
-
-#define  FMC_SDTR1_TRC                      0x0000F000U        /*!<TRC[2:0] bits (Row cycle delay) */
-#define  FMC_SDTR1_TRC_0                    0x00001000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRC_1                    0x00002000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRC_2                    0x00004000U        /*!<Bit 2 */
-
-#define  FMC_SDTR1_TWR                      0x000F0000U        /*!<TRC[2:0] bits (Write recovery delay) */
-#define  FMC_SDTR1_TWR_0                    0x00010000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TWR_1                    0x00020000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TWR_2                    0x00040000U        /*!<Bit 2 */
-
-#define  FMC_SDTR1_TRP                      0x00F00000U        /*!<TRP[2:0] bits (Row precharge delay) */
-#define  FMC_SDTR1_TRP_0                    0x00100000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRP_1                    0x00200000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRP_2                    0x00400000U        /*!<Bit 2 */
-
-#define  FMC_SDTR1_TRCD                     0x0F000000U        /*!<TRP[2:0] bits (Row to column delay) */
-#define  FMC_SDTR1_TRCD_0                   0x01000000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRCD_1                   0x02000000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRCD_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for FMC_SDTR2 register  ******************/
-#define  FMC_SDTR2_TMRD                     0x0000000FU        /*!<TMRD[3:0] bits (Load mode register to active) */
-#define  FMC_SDTR2_TMRD_0                   0x00000001U        /*!<Bit 0 */
-#define  FMC_SDTR2_TMRD_1                   0x00000002U        /*!<Bit 1 */
-#define  FMC_SDTR2_TMRD_2                   0x00000004U        /*!<Bit 2 */
-#define  FMC_SDTR2_TMRD_3                   0x00000008U        /*!<Bit 3 */
-                                            
-#define  FMC_SDTR2_TXSR                     0x000000F0U        /*!<TXSR[3:0] bits (Exit self refresh) */
-#define  FMC_SDTR2_TXSR_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDTR2_TXSR_1                   0x00000020U        /*!<Bit 1 */
-#define  FMC_SDTR2_TXSR_2                   0x00000040U        /*!<Bit 2 */
-#define  FMC_SDTR2_TXSR_3                   0x00000080U        /*!<Bit 3 */
-
-#define  FMC_SDTR2_TRAS                     0x00000F00U        /*!<TRAS[3:0] bits (Self refresh time) */
-#define  FMC_SDTR2_TRAS_0                   0x00000100U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRAS_1                   0x00000200U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRAS_2                   0x00000400U        /*!<Bit 2 */
-#define  FMC_SDTR2_TRAS_3                   0x00000800U        /*!<Bit 3 */
-
-#define  FMC_SDTR2_TRC                      0x0000F000U        /*!<TRC[2:0] bits (Row cycle delay) */
-#define  FMC_SDTR2_TRC_0                    0x00001000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRC_1                    0x00002000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRC_2                    0x00004000U        /*!<Bit 2 */
-
-#define  FMC_SDTR2_TWR                      0x000F0000U        /*!<TRC[2:0] bits (Write recovery delay) */
-#define  FMC_SDTR2_TWR_0                    0x00010000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TWR_1                    0x00020000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TWR_2                    0x00040000U        /*!<Bit 2 */
-
-#define  FMC_SDTR2_TRP                      0x00F00000U        /*!<TRP[2:0] bits (Row precharge delay) */
-#define  FMC_SDTR2_TRP_0                    0x00100000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRP_1                    0x00200000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRP_2                    0x00400000U        /*!<Bit 2 */
-
-#define  FMC_SDTR2_TRCD                     0x0F000000U        /*!<TRP[2:0] bits (Row to column delay) */
-#define  FMC_SDTR2_TRCD_0                   0x01000000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRCD_1                   0x02000000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRCD_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for FMC_SDCMR register  ******************/
-#define  FMC_SDCMR_MODE                     0x00000007U        /*!<MODE[2:0] bits (Command mode) */
-#define  FMC_SDCMR_MODE_0                   0x00000001U        /*!<Bit 0 */
-#define  FMC_SDCMR_MODE_1                   0x00000002U        /*!<Bit 1 */
-#define  FMC_SDCMR_MODE_2                   0x00000004U        /*!<Bit 2 */
-                                            
-#define  FMC_SDCMR_CTB2                     0x00000008U        /*!<Command target 2 */
-
-#define  FMC_SDCMR_CTB1                     0x00000010U        /*!<Command target 1 */
-
-#define  FMC_SDCMR_NRFS                     0x000001E0U        /*!<NRFS[3:0] bits (Number of auto-refresh) */
-#define  FMC_SDCMR_NRFS_0                   0x00000020U        /*!<Bit 0 */
-#define  FMC_SDCMR_NRFS_1                   0x00000040U        /*!<Bit 1 */
-#define  FMC_SDCMR_NRFS_2                   0x00000080U        /*!<Bit 2 */
-#define  FMC_SDCMR_NRFS_3                   0x00000100U        /*!<Bit 3 */
-
-#define  FMC_SDCMR_MRD                      0x003FFE00U        /*!<MRD[12:0] bits (Mode register definition) */
-
-/******************  Bit definition for FMC_SDRTR register  ******************/
-#define  FMC_SDRTR_CRE                      0x00000001U        /*!<Clear refresh error flag */
-
-#define  FMC_SDRTR_COUNT                    0x00003FFEU        /*!<COUNT[12:0] bits (Refresh timer count) */
-
-#define  FMC_SDRTR_REIE                     0x00004000U        /*!<RES interupt enable */
-
-/******************  Bit definition for FMC_SDSR register  ******************/
-#define  FMC_SDSR_RE                        0x00000001U        /*!<Refresh error flag */
-
-#define  FMC_SDSR_MODES1                    0x00000006U        /*!<MODES1[1:0]bits (Status mode for bank 1) */
-#define  FMC_SDSR_MODES1_0                  0x00000002U        /*!<Bit 0 */
-#define  FMC_SDSR_MODES1_1                  0x00000004U        /*!<Bit 1 */
-
-#define  FMC_SDSR_MODES2                    0x00000018U        /*!<MODES2[1:0]bits (Status mode for bank 2) */
-#define  FMC_SDSR_MODES2_0                  0x00000008U        /*!<Bit 0 */
-#define  FMC_SDSR_MODES2_1                  0x00000010U        /*!<Bit 1 */
-#define  FMC_SDSR_BUSY                      0x00000020U        /*!<Busy status */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    0x00000003U
-#define GPIO_MODER_MODER0_0                  0x00000001U
-#define GPIO_MODER_MODER0_1                  0x00000002U
-
-#define GPIO_MODER_MODER1                    0x0000000CU
-#define GPIO_MODER_MODER1_0                  0x00000004U
-#define GPIO_MODER_MODER1_1                  0x00000008U
-
-#define GPIO_MODER_MODER2                    0x00000030U
-#define GPIO_MODER_MODER2_0                  0x00000010U
-#define GPIO_MODER_MODER2_1                  0x00000020U
-
-#define GPIO_MODER_MODER3                    0x000000C0U
-#define GPIO_MODER_MODER3_0                  0x00000040U
-#define GPIO_MODER_MODER3_1                  0x00000080U
-
-#define GPIO_MODER_MODER4                    0x00000300U
-#define GPIO_MODER_MODER4_0                  0x00000100U
-#define GPIO_MODER_MODER4_1                  0x00000200U
-
-#define GPIO_MODER_MODER5                    0x00000C00U
-#define GPIO_MODER_MODER5_0                  0x00000400U
-#define GPIO_MODER_MODER5_1                  0x00000800U
-
-#define GPIO_MODER_MODER6                    0x00003000U
-#define GPIO_MODER_MODER6_0                  0x00001000U
-#define GPIO_MODER_MODER6_1                  0x00002000U
-
-#define GPIO_MODER_MODER7                    0x0000C000U
-#define GPIO_MODER_MODER7_0                  0x00004000U
-#define GPIO_MODER_MODER7_1                  0x00008000U
-
-#define GPIO_MODER_MODER8                    0x00030000U
-#define GPIO_MODER_MODER8_0                  0x00010000U
-#define GPIO_MODER_MODER8_1                  0x00020000U
-
-#define GPIO_MODER_MODER9                    0x000C0000U
-#define GPIO_MODER_MODER9_0                  0x00040000U
-#define GPIO_MODER_MODER9_1                  0x00080000U
-
-#define GPIO_MODER_MODER10                   0x00300000U
-#define GPIO_MODER_MODER10_0                 0x00100000U
-#define GPIO_MODER_MODER10_1                 0x00200000U
-
-#define GPIO_MODER_MODER11                   0x00C00000U
-#define GPIO_MODER_MODER11_0                 0x00400000U
-#define GPIO_MODER_MODER11_1                 0x00800000U
-
-#define GPIO_MODER_MODER12                   0x03000000U
-#define GPIO_MODER_MODER12_0                 0x01000000U
-#define GPIO_MODER_MODER12_1                 0x02000000U
-
-#define GPIO_MODER_MODER13                   0x0C000000U
-#define GPIO_MODER_MODER13_0                 0x04000000U
-#define GPIO_MODER_MODER13_1                 0x08000000U
-
-#define GPIO_MODER_MODER14                   0x30000000U
-#define GPIO_MODER_MODER14_0                 0x10000000U
-#define GPIO_MODER_MODER14_1                 0x20000000U
-
-#define GPIO_MODER_MODER15                   0xC0000000U
-#define GPIO_MODER_MODER15_0                 0x40000000U
-#define GPIO_MODER_MODER15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     0x00000001U
-#define GPIO_OTYPER_OT_1                     0x00000002U
-#define GPIO_OTYPER_OT_2                     0x00000004U
-#define GPIO_OTYPER_OT_3                     0x00000008U
-#define GPIO_OTYPER_OT_4                     0x00000010U
-#define GPIO_OTYPER_OT_5                     0x00000020U
-#define GPIO_OTYPER_OT_6                     0x00000040U
-#define GPIO_OTYPER_OT_7                     0x00000080U
-#define GPIO_OTYPER_OT_8                     0x00000100U
-#define GPIO_OTYPER_OT_9                     0x00000200U
-#define GPIO_OTYPER_OT_10                    0x00000400U
-#define GPIO_OTYPER_OT_11                    0x00000800U
-#define GPIO_OTYPER_OT_12                    0x00001000U
-#define GPIO_OTYPER_OT_13                    0x00002000U
-#define GPIO_OTYPER_OT_14                    0x00004000U
-#define GPIO_OTYPER_OT_15                    0x00008000U
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
-#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
-#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
-
-#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
-#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
-#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
-
-#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
-#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
-#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
-
-#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
-#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
-#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
-
-#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
-#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
-#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
-
-#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
-#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
-#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
-
-#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
-#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
-#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
-
-#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
-#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
-#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
-
-#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
-#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
-#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
-
-#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
-#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
-#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
-
-#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
-#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
-#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
-
-#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
-#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
-#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
-
-#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
-#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
-#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
-
-#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
-#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
-#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
-
-#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
-#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
-#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
-
-#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
-#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
-#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    0x00000003U
-#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
-#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
-
-#define GPIO_PUPDR_PUPDR1                    0x0000000CU
-#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
-#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
-
-#define GPIO_PUPDR_PUPDR2                    0x00000030U
-#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
-#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
-
-#define GPIO_PUPDR_PUPDR3                    0x000000C0U
-#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
-#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
-
-#define GPIO_PUPDR_PUPDR4                    0x00000300U
-#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
-#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
-
-#define GPIO_PUPDR_PUPDR5                    0x00000C00U
-#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
-#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
-
-#define GPIO_PUPDR_PUPDR6                    0x00003000U
-#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
-#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
-
-#define GPIO_PUPDR_PUPDR7                    0x0000C000U
-#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
-#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
-
-#define GPIO_PUPDR_PUPDR8                    0x00030000U
-#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
-#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
-
-#define GPIO_PUPDR_PUPDR9                    0x000C0000U
-#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
-#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
-
-#define GPIO_PUPDR_PUPDR10                   0x00300000U
-#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
-#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
-
-#define GPIO_PUPDR_PUPDR11                   0x00C00000U
-#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
-#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
-
-#define GPIO_PUPDR_PUPDR12                   0x03000000U
-#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
-#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
-
-#define GPIO_PUPDR_PUPDR13                   0x0C000000U
-#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
-#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
-
-#define GPIO_PUPDR_PUPDR14                   0x30000000U
-#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
-#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
-
-#define GPIO_PUPDR_PUPDR15                   0xC0000000U
-#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
-#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       0x00000001U
-#define GPIO_IDR_IDR_1                       0x00000002U
-#define GPIO_IDR_IDR_2                       0x00000004U
-#define GPIO_IDR_IDR_3                       0x00000008U
-#define GPIO_IDR_IDR_4                       0x00000010U
-#define GPIO_IDR_IDR_5                       0x00000020U
-#define GPIO_IDR_IDR_6                       0x00000040U
-#define GPIO_IDR_IDR_7                       0x00000080U
-#define GPIO_IDR_IDR_8                       0x00000100U
-#define GPIO_IDR_IDR_9                       0x00000200U
-#define GPIO_IDR_IDR_10                      0x00000400U
-#define GPIO_IDR_IDR_11                      0x00000800U
-#define GPIO_IDR_IDR_12                      0x00001000U
-#define GPIO_IDR_IDR_13                      0x00002000U
-#define GPIO_IDR_IDR_14                      0x00004000U
-#define GPIO_IDR_IDR_15                      0x00008000U
-/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
-#define GPIO_OTYPER_IDR_0                    GPIO_IDR_IDR_0
-#define GPIO_OTYPER_IDR_1                    GPIO_IDR_IDR_1
-#define GPIO_OTYPER_IDR_2                    GPIO_IDR_IDR_2
-#define GPIO_OTYPER_IDR_3                    GPIO_IDR_IDR_3
-#define GPIO_OTYPER_IDR_4                    GPIO_IDR_IDR_4
-#define GPIO_OTYPER_IDR_5                    GPIO_IDR_IDR_5
-#define GPIO_OTYPER_IDR_6                    GPIO_IDR_IDR_6
-#define GPIO_OTYPER_IDR_7                    GPIO_IDR_IDR_7
-#define GPIO_OTYPER_IDR_8                    GPIO_IDR_IDR_8
-#define GPIO_OTYPER_IDR_9                    GPIO_IDR_IDR_9
-#define GPIO_OTYPER_IDR_10                   GPIO_IDR_IDR_10
-#define GPIO_OTYPER_IDR_11                   GPIO_IDR_IDR_11
-#define GPIO_OTYPER_IDR_12                   GPIO_IDR_IDR_12
-#define GPIO_OTYPER_IDR_13                   GPIO_IDR_IDR_13
-#define GPIO_OTYPER_IDR_14                   GPIO_IDR_IDR_14
-#define GPIO_OTYPER_IDR_15                   GPIO_IDR_IDR_15
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       0x00000001U
-#define GPIO_ODR_ODR_1                       0x00000002U
-#define GPIO_ODR_ODR_2                       0x00000004U
-#define GPIO_ODR_ODR_3                       0x00000008U
-#define GPIO_ODR_ODR_4                       0x00000010U
-#define GPIO_ODR_ODR_5                       0x00000020U
-#define GPIO_ODR_ODR_6                       0x00000040U
-#define GPIO_ODR_ODR_7                       0x00000080U
-#define GPIO_ODR_ODR_8                       0x00000100U
-#define GPIO_ODR_ODR_9                       0x00000200U
-#define GPIO_ODR_ODR_10                      0x00000400U
-#define GPIO_ODR_ODR_11                      0x00000800U
-#define GPIO_ODR_ODR_12                      0x00001000U
-#define GPIO_ODR_ODR_13                      0x00002000U
-#define GPIO_ODR_ODR_14                      0x00004000U
-#define GPIO_ODR_ODR_15                      0x00008000U
-/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
-#define GPIO_OTYPER_ODR_0                    GPIO_ODR_ODR_0
-#define GPIO_OTYPER_ODR_1                    GPIO_ODR_ODR_1
-#define GPIO_OTYPER_ODR_2                    GPIO_ODR_ODR_2
-#define GPIO_OTYPER_ODR_3                    GPIO_ODR_ODR_3
-#define GPIO_OTYPER_ODR_4                    GPIO_ODR_ODR_4
-#define GPIO_OTYPER_ODR_5                    GPIO_ODR_ODR_5
-#define GPIO_OTYPER_ODR_6                    GPIO_ODR_ODR_6
-#define GPIO_OTYPER_ODR_7                    GPIO_ODR_ODR_7
-#define GPIO_OTYPER_ODR_8                    GPIO_ODR_ODR_8
-#define GPIO_OTYPER_ODR_9                    GPIO_ODR_ODR_9
-#define GPIO_OTYPER_ODR_10                   GPIO_ODR_ODR_10
-#define GPIO_OTYPER_ODR_11                   GPIO_ODR_ODR_11
-#define GPIO_OTYPER_ODR_12                   GPIO_ODR_ODR_12
-#define GPIO_OTYPER_ODR_13                   GPIO_ODR_ODR_13
-#define GPIO_OTYPER_ODR_14                   GPIO_ODR_ODR_14
-#define GPIO_OTYPER_ODR_15                   GPIO_ODR_ODR_15
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       0x00000001U
-#define GPIO_BSRR_BS_1                       0x00000002U
-#define GPIO_BSRR_BS_2                       0x00000004U
-#define GPIO_BSRR_BS_3                       0x00000008U
-#define GPIO_BSRR_BS_4                       0x00000010U
-#define GPIO_BSRR_BS_5                       0x00000020U
-#define GPIO_BSRR_BS_6                       0x00000040U
-#define GPIO_BSRR_BS_7                       0x00000080U
-#define GPIO_BSRR_BS_8                       0x00000100U
-#define GPIO_BSRR_BS_9                       0x00000200U
-#define GPIO_BSRR_BS_10                      0x00000400U
-#define GPIO_BSRR_BS_11                      0x00000800U
-#define GPIO_BSRR_BS_12                      0x00001000U
-#define GPIO_BSRR_BS_13                      0x00002000U
-#define GPIO_BSRR_BS_14                      0x00004000U
-#define GPIO_BSRR_BS_15                      0x00008000U
-#define GPIO_BSRR_BR_0                       0x00010000U
-#define GPIO_BSRR_BR_1                       0x00020000U
-#define GPIO_BSRR_BR_2                       0x00040000U
-#define GPIO_BSRR_BR_3                       0x00080000U
-#define GPIO_BSRR_BR_4                       0x00100000U
-#define GPIO_BSRR_BR_5                       0x00200000U
-#define GPIO_BSRR_BR_6                       0x00400000U
-#define GPIO_BSRR_BR_7                       0x00800000U
-#define GPIO_BSRR_BR_8                       0x01000000U
-#define GPIO_BSRR_BR_9                       0x02000000U
-#define GPIO_BSRR_BR_10                      0x04000000U
-#define GPIO_BSRR_BR_11                      0x08000000U
-#define GPIO_BSRR_BR_12                      0x10000000U
-#define GPIO_BSRR_BR_13                      0x20000000U
-#define GPIO_BSRR_BR_14                      0x40000000U
-#define GPIO_BSRR_BR_15                      0x80000000U
-
-/****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0                       0x00000001U
-#define GPIO_LCKR_LCK1                       0x00000002U
-#define GPIO_LCKR_LCK2                       0x00000004U
-#define GPIO_LCKR_LCK3                       0x00000008U
-#define GPIO_LCKR_LCK4                       0x00000010U
-#define GPIO_LCKR_LCK5                       0x00000020U
-#define GPIO_LCKR_LCK6                       0x00000040U
-#define GPIO_LCKR_LCK7                       0x00000080U
-#define GPIO_LCKR_LCK8                       0x00000100U
-#define GPIO_LCKR_LCK9                       0x00000200U
-#define GPIO_LCKR_LCK10                      0x00000400U
-#define GPIO_LCKR_LCK11                      0x00000800U
-#define GPIO_LCKR_LCK12                      0x00001000U
-#define GPIO_LCKR_LCK13                      0x00002000U
-#define GPIO_LCKR_LCK14                      0x00004000U
-#define GPIO_LCKR_LCK15                      0x00008000U
-#define GPIO_LCKR_LCKK                       0x00010000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Inter-integrated Circuit Interface                    */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          0x00000001U     /*!<Peripheral Enable                             */
-#define  I2C_CR1_SMBUS                       0x00000002U     /*!<SMBus Mode                                    */
-#define  I2C_CR1_SMBTYPE                     0x00000008U     /*!<SMBus Type                                    */
-#define  I2C_CR1_ENARP                       0x00000010U     /*!<ARP Enable                                    */
-#define  I2C_CR1_ENPEC                       0x00000020U     /*!<PEC Enable                                    */
-#define  I2C_CR1_ENGC                        0x00000040U     /*!<General Call Enable                           */
-#define  I2C_CR1_NOSTRETCH                   0x00000080U     /*!<Clock Stretching Disable (Slave mode)  */
-#define  I2C_CR1_START                       0x00000100U     /*!<Start Generation                              */
-#define  I2C_CR1_STOP                        0x00000200U     /*!<Stop Generation                               */
-#define  I2C_CR1_ACK                         0x00000400U     /*!<Acknowledge Enable                            */
-#define  I2C_CR1_POS                         0x00000800U     /*!<Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         0x00001000U     /*!<Packet Error Checking                         */
-#define  I2C_CR1_ALERT                       0x00002000U     /*!<SMBus Alert                                   */
-#define  I2C_CR1_SWRST                       0x00008000U     /*!<Software Reset                                */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        0x0000003FU     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
-#define  I2C_CR2_FREQ_0                      0x00000001U     /*!<Bit 0 */
-#define  I2C_CR2_FREQ_1                      0x00000002U     /*!<Bit 1 */
-#define  I2C_CR2_FREQ_2                      0x00000004U     /*!<Bit 2 */
-#define  I2C_CR2_FREQ_3                      0x00000008U     /*!<Bit 3 */
-#define  I2C_CR2_FREQ_4                      0x00000010U     /*!<Bit 4 */
-#define  I2C_CR2_FREQ_5                      0x00000020U     /*!<Bit 5 */
-
-#define  I2C_CR2_ITERREN                     0x00000100U     /*!<Error Interrupt Enable  */
-#define  I2C_CR2_ITEVTEN                     0x00000200U     /*!<Event Interrupt Enable  */
-#define  I2C_CR2_ITBUFEN                     0x00000400U     /*!<Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       0x00000800U     /*!<DMA Requests Enable     */
-#define  I2C_CR2_LAST                        0x00001000U     /*!<DMA Last Transfer       */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     0x000000FEU     /*!<Interface Address */
-#define  I2C_OAR1_ADD8_9                     0x00000300U     /*!<Interface Address */
-
-#define  I2C_OAR1_ADD0                       0x00000001U     /*!<Bit 0 */
-#define  I2C_OAR1_ADD1                       0x00000002U     /*!<Bit 1 */
-#define  I2C_OAR1_ADD2                       0x00000004U     /*!<Bit 2 */
-#define  I2C_OAR1_ADD3                       0x00000008U     /*!<Bit 3 */
-#define  I2C_OAR1_ADD4                       0x00000010U     /*!<Bit 4 */
-#define  I2C_OAR1_ADD5                       0x00000020U     /*!<Bit 5 */
-#define  I2C_OAR1_ADD6                       0x00000040U     /*!<Bit 6 */
-#define  I2C_OAR1_ADD7                       0x00000080U     /*!<Bit 7 */
-#define  I2C_OAR1_ADD8                       0x00000100U     /*!<Bit 8 */
-#define  I2C_OAR1_ADD9                       0x00000200U     /*!<Bit 9 */
-
-#define  I2C_OAR1_ADDMODE                    0x00008000U     /*!<Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     0x00000001U        /*!<Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       0x000000FEU        /*!<Interface address           */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           0x000000FFU        /*!<8-bit Data Register         */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          0x00000001U     /*!<Start Bit (Master mode)                  */
-#define  I2C_SR1_ADDR                        0x00000002U     /*!<Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         0x00000004U     /*!<Byte Transfer Finished                          */
-#define  I2C_SR1_ADD10                       0x00000008U     /*!<10-bit header sent (Master mode)         */
-#define  I2C_SR1_STOPF                       0x00000010U     /*!<Stop detection (Slave mode)              */
-#define  I2C_SR1_RXNE                        0x00000040U     /*!<Data Register not Empty (receivers)      */
-#define  I2C_SR1_TXE                         0x00000080U     /*!<Data Register Empty (transmitters)       */
-#define  I2C_SR1_BERR                        0x00000100U     /*!<Bus Error                                       */
-#define  I2C_SR1_ARLO                        0x00000200U     /*!<Arbitration Lost (master mode)           */
-#define  I2C_SR1_AF                          0x00000400U     /*!<Acknowledge Failure                             */
-#define  I2C_SR1_OVR                         0x00000800U     /*!<Overrun/Underrun                                */
-#define  I2C_SR1_PECERR                      0x00001000U     /*!<PEC Error in reception                          */
-#define  I2C_SR1_TIMEOUT                     0x00004000U     /*!<Timeout or Tlow Error                           */
-#define  I2C_SR1_SMBALERT                    0x00008000U     /*!<SMBus Alert                                     */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         0x00000001U     /*!<Master/Slave                              */
-#define  I2C_SR2_BUSY                        0x00000002U     /*!<Bus Busy                                  */
-#define  I2C_SR2_TRA                         0x00000004U     /*!<Transmitter/Receiver                      */
-#define  I2C_SR2_GENCALL                     0x00000010U     /*!<General Call Address (Slave mode)  */
-#define  I2C_SR2_SMBDEFAULT                  0x00000020U     /*!<SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     0x00000040U     /*!<SMBus Host Header (Slave mode)     */
-#define  I2C_SR2_DUALF                       0x00000080U     /*!<Dual Flag (Slave mode)             */
-#define  I2C_SR2_PEC                         0x0000FF00U     /*!<Packet Error Checking Register            */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         0x00000FFFU     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        0x00004000U     /*!<Fast Mode Duty Cycle                                       */
-#define  I2C_CCR_FS                          0x00008000U     /*!<I2C Master Mode Selection                                  */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     0x0000003FU     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************  Bit definition for I2C_FLTR register  *******************/
-#define  I2C_FLTR_DNF                        0x0000000FU     /*!<Digital Noise Filter */
-#define  I2C_FLTR_ANOFF                      0x00000010U     /*!<Analog Noise Filter OFF */
-
-/******************************************************************************/
-/*                                                                            */
-/*        Fast Mode Plus Inter-integrated Circuit Interface (I2C)             */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define  FMPI2C_CR1_PE                        0x00000001U        /*!< Peripheral enable                   */
-#define  FMPI2C_CR1_TXIE                      0x00000002U        /*!< TX interrupt enable                 */
-#define  FMPI2C_CR1_RXIE                      0x00000004U        /*!< RX interrupt enable                 */
-#define  FMPI2C_CR1_ADDRIE                    0x00000008U        /*!< Address match interrupt enable      */
-#define  FMPI2C_CR1_NACKIE                    0x00000010U        /*!< NACK received interrupt enable      */
-#define  FMPI2C_CR1_STOPIE                    0x00000020U        /*!< STOP detection interrupt enable     */
-#define  FMPI2C_CR1_TCIE                      0x00000040U        /*!< Transfer complete interrupt enable  */
-#define  FMPI2C_CR1_ERRIE                     0x00000080U        /*!< Errors interrupt enable             */
-#define  FMPI2C_CR1_DFN                       0x00000F00U        /*!< Digital noise filter                */
-#define  FMPI2C_CR1_ANFOFF                    0x00001000U        /*!< Analog noise filter OFF             */
-#define  FMPI2C_CR1_TXDMAEN                   0x00004000U        /*!< DMA transmission requests enable    */
-#define  FMPI2C_CR1_RXDMAEN                   0x00008000U        /*!< DMA reception requests enable       */
-#define  FMPI2C_CR1_SBC                       0x00010000U        /*!< Slave byte control                  */
-#define  FMPI2C_CR1_NOSTRETCH                 0x00020000U        /*!< Clock stretching disable            */
-#define  FMPI2C_CR1_GCEN                      0x00080000U        /*!< General call enable                 */
-#define  FMPI2C_CR1_SMBHEN                    0x00100000U        /*!< SMBus host address enable           */
-#define  FMPI2C_CR1_SMBDEN                    0x00200000U        /*!< SMBus device default address enable */
-#define  FMPI2C_CR1_ALERTEN                   0x00400000U        /*!< SMBus alert enable                  */
-#define  FMPI2C_CR1_PECEN                     0x00800000U        /*!< PEC enable                          */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define  FMPI2C_CR2_SADD                      0x000003FFU        /*!< Slave address (master mode)                             */
-#define  FMPI2C_CR2_RD_WRN                    0x00000400U        /*!< Transfer direction (master mode)                        */
-#define  FMPI2C_CR2_ADD10                     0x00000800U        /*!< 10-bit addressing mode (master mode)                    */
-#define  FMPI2C_CR2_HEAD10R                   0x00001000U        /*!< 10-bit address header only read direction (master mode) */
-#define  FMPI2C_CR2_START                     0x00002000U        /*!< START generation                                        */
-#define  FMPI2C_CR2_STOP                      0x00004000U        /*!< STOP generation (master mode)                           */
-#define  FMPI2C_CR2_NACK                      0x00008000U        /*!< NACK generation (slave mode)                            */
-#define  FMPI2C_CR2_NBYTES                    0x00FF0000U        /*!< Number of bytes                                         */
-#define  FMPI2C_CR2_RELOAD                    0x01000000U        /*!< NBYTES reload mode                                      */
-#define  FMPI2C_CR2_AUTOEND                   0x02000000U        /*!< Automatic end mode (master mode)                        */
-#define  FMPI2C_CR2_PECBYTE                   0x04000000U        /*!< Packet error checking byte                              */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define  FMPI2C_OAR1_OA1                      0x000003FFU        /*!< Interface own address 1   */
-#define  FMPI2C_OAR1_OA1MODE                  0x00000400U        /*!< Own address 1 10-bit mode */
-#define  FMPI2C_OAR1_OA1EN                    0x00008000U        /*!< Own address 1 enable      */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define  FMPI2C_OAR2_OA2                      0x000000FEU        /*!< Interface own address 2 */
-#define  FMPI2C_OAR2_OA2MSK                   0x00000700U        /*!< Own address 2 masks     */
-#define  FMPI2C_OAR2_OA2EN                    0x00008000U        /*!< Own address 2 enable    */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define  FMPI2C_TIMINGR_SCLL                  0x000000FFU        /*!< SCL low period (master mode)  */
-#define  FMPI2C_TIMINGR_SCLH                  0x0000FF00U        /*!< SCL high period (master mode) */
-#define  FMPI2C_TIMINGR_SDADEL                0x000F0000U        /*!< Data hold time                */
-#define  FMPI2C_TIMINGR_SCLDEL                0x00F00000U        /*!< Data setup time               */
-#define  FMPI2C_TIMINGR_PRESC                 0xF0000000U        /*!< Timings prescaler             */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define  FMPI2C_TIMEOUTR_TIMEOUTA             0x00000FFFU        /*!< Bus timeout A                 */
-#define  FMPI2C_TIMEOUTR_TIDLE                0x00001000U        /*!< Idle clock timeout detection  */
-#define  FMPI2C_TIMEOUTR_TIMOUTEN             0x00008000U        /*!< Clock timeout enable          */
-#define  FMPI2C_TIMEOUTR_TIMEOUTB             0x0FFF0000U        /*!< Bus timeout B                 */
-#define  FMPI2C_TIMEOUTR_TEXTEN               0x80000000U        /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define  FMPI2C_ISR_TXE                       0x00000001U        /*!< Transmit data register empty     */
-#define  FMPI2C_ISR_TXIS                      0x00000002U        /*!< Transmit interrupt status        */
-#define  FMPI2C_ISR_RXNE                      0x00000004U        /*!< Receive data register not empty  */
-#define  FMPI2C_ISR_ADDR                      0x00000008U        /*!< Address matched (slave mode)     */
-#define  FMPI2C_ISR_NACKF                     0x00000010U        /*!< NACK received flag               */
-#define  FMPI2C_ISR_STOPF                     0x00000020U        /*!< STOP detection flag              */
-#define  FMPI2C_ISR_TC                        0x00000040U        /*!< Transfer complete (master mode)  */
-#define  FMPI2C_ISR_TCR                       0x00000080U        /*!< Transfer complete reload         */
-#define  FMPI2C_ISR_BERR                      0x00000100U        /*!< Bus error                        */
-#define  FMPI2C_ISR_ARLO                      0x00000200U        /*!< Arbitration lost                 */
-#define  FMPI2C_ISR_OVR                       0x00000400U        /*!< Overrun/Underrun                 */
-#define  FMPI2C_ISR_PECERR                    0x00000800U        /*!< PEC error in reception           */
-#define  FMPI2C_ISR_TIMEOUT                   0x00001000U        /*!< Timeout or Tlow detection flag   */
-#define  FMPI2C_ISR_ALERT                     0x00002000U        /*!< SMBus alert                      */
-#define  FMPI2C_ISR_BUSY                      0x00008000U        /*!< Bus busy                         */
-#define  FMPI2C_ISR_DIR                       0x00010000U        /*!< Transfer direction (slave mode)  */
-#define  FMPI2C_ISR_ADDCODE                   0x00FE0000U        /*!< Address match code (slave mode)  */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define  FMPI2C_ICR_ADDRCF                    0x00000008U        /*!< Address matched clear flag  */
-#define  FMPI2C_ICR_NACKCF                    0x00000010U        /*!< NACK clear flag             */
-#define  FMPI2C_ICR_STOPCF                    0x00000020U        /*!< STOP detection clear flag   */
-#define  FMPI2C_ICR_BERRCF                    0x00000100U        /*!< Bus error clear flag        */
-#define  FMPI2C_ICR_ARLOCF                    0x00000200U        /*!< Arbitration lost clear flag */
-#define  FMPI2C_ICR_OVRCF                     0x00000400U        /*!< Overrun/Underrun clear flag */
-#define  FMPI2C_ICR_PECCF                     0x00000800U        /*!< PAC error clear flag        */
-#define  FMPI2C_ICR_TIMOUTCF                  0x00001000U        /*!< Timeout clear flag          */
-#define  FMPI2C_ICR_ALERTCF                   0x00002000U        /*!< Alert clear flag            */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define  FMPI2C_PECR_PEC                      0x000000FFU        /*!< PEC register */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define  FMPI2C_RXDR_RXDATA                   0x000000FFU        /*!< 8-bit receive data */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define  FMPI2C_TXDR_TXDATA                   0x000000FFU        /*!< 8-bit transmit data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Independent WATCHDOG                             */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         0x01U               /*!<Watchdog prescaler value update      */
-#define  IWDG_SR_RVU                         0x02U               /*!<Watchdog counter reload value update */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                             Power Control                                  */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
-#define  PWR_CR_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
-#define  PWR_CR_CWUF                         0x00000004U     /*!< Clear Wakeup Flag                   */
-#define  PWR_CR_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
-#define  PWR_CR_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
-
-#define  PWR_CR_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        0x00000020U     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        0x00000040U     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        0x00000080U     /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
-#define  PWR_CR_DBP                          0x00000100U     /*!< Disable Backup Domain write protection                     */
-#define  PWR_CR_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                              */
-#define  PWR_CR_LPLVDS                       0x00000400U     /*!< Low-Power Regulator Low Voltage Scaling in Stop mode       */
-#define  PWR_CR_MRLVDS                       0x00000800U     /*!< Main regulator Low Voltage Scaling in Stop mode            */
-#define  PWR_CR_ADCDC1                       0x00002000U     /*!< Refer to AN4073 on how to use this bit */ 
-#define  PWR_CR_VOS                          0x0000C000U     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
-#define  PWR_CR_VOS_0                        0x00004000U     /*!< Bit 0 */
-#define  PWR_CR_VOS_1                        0x00008000U     /*!< Bit 1 */
-#define  PWR_CR_ODEN                         0x00010000U     /*!< Over Drive enable                     */
-#define  PWR_CR_ODSWEN                       0x00020000U     /*!< Over Drive switch enabled             */
-#define  PWR_CR_UDEN                         0x000C0000U     /*!< Under Drive enable in stop mode       */
-#define  PWR_CR_UDEN_0                       0x00040000U     /*!< Bit 0                                 */
-#define  PWR_CR_UDEN_1                       0x00080000U     /*!< Bit 1                                 */
-#define  PWR_CR_FMSSR                        0x00100000U     /*!< Flash Memory Sleep System Run         */
-#define  PWR_CR_FISSR                        0x00200000U     /*!< Flash Interface Stop while System Run */
-
-/* Legacy define */
-#define  PWR_CR_PMODE                        PWR_CR_VOS
-#define  PWR_CR_LPUDS                        PWR_CR_LPLVDS     /*!< Low-Power Regulator in deepsleep under-drive mode        */
-#define  PWR_CR_MRUDS                        PWR_CR_MRLVDS     /*!< Main regulator in deepsleep under-drive mode             */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         0x00000001U     /*!< Wakeup Flag                                      */
-#define  PWR_CSR_SBF                         0x00000002U     /*!< Standby Flag                                     */
-#define  PWR_CSR_PVDO                        0x00000004U     /*!< PVD Output                                       */
-#define  PWR_CSR_BRR                         0x00000008U     /*!< Backup regulator ready                           */
-#define  PWR_CSR_EWUP2                       0x00000080U     /*!< Enable WKUP pin 2                                */
-#define  PWR_CSR_EWUP1                       0x00000100U     /*!< Enable WKUP pin 1                                */
-#define  PWR_CSR_BRE                         0x00000200U     /*!< Backup regulator enable                          */
-#define  PWR_CSR_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
-#define  PWR_CSR_ODRDY                       0x00010000U     /*!< Over Drive generator ready                       */
-#define  PWR_CSR_ODSWRDY                     0x00020000U     /*!< Over Drive Switch ready                          */
-#define  PWR_CSR_UDSWRDY                     0x000C0000U     /*!< Under Drive ready                                */
-
-/* Legacy define */
-#define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    QUADSPI                                 */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for QUADSPI_CR register  *******************/
-#define  QUADSPI_CR_EN                           0x00000001U            /*!< Enable                             */
-#define  QUADSPI_CR_ABORT                        0x00000002U            /*!< Abort request                      */
-#define  QUADSPI_CR_DMAEN                        0x00000004U            /*!< DMA Enable                         */
-#define  QUADSPI_CR_TCEN                         0x00000008U            /*!< Timeout Counter Enable             */
-#define  QUADSPI_CR_SSHIFT                       0x00000010U            /*!< SSHIFT Sample Shift                */
-#define  QUADSPI_CR_DFM                          0x00000040U            /*!< Dual Flash Mode                    */
-#define  QUADSPI_CR_FSEL                         0x00000080U            /*!< Flash Select                       */
-#define  QUADSPI_CR_FTHRES                       0x00001F00U            /*!< FTHRES[3:0] FIFO Level             */
-#define  QUADSPI_CR_FTHRES_0                     0x00000100U            /*!< Bit 0 */
-#define  QUADSPI_CR_FTHRES_1                     0x00000200U            /*!< Bit 1 */
-#define  QUADSPI_CR_FTHRES_2                     0x00000400U            /*!< Bit 2 */
-#define  QUADSPI_CR_FTHRES_3                     0x00000800U            /*!< Bit 3 */
-#define  QUADSPI_CR_FTHRES_4                     0x00001000U            /*!< Bit 4 */
-#define  QUADSPI_CR_TEIE                         0x00010000U            /*!< Transfer Error Interrupt Enable    */
-#define  QUADSPI_CR_TCIE                         0x00020000U            /*!< Transfer Complete Interrupt Enable */
-#define  QUADSPI_CR_FTIE                         0x00040000U            /*!< FIFO Threshold Interrupt Enable    */
-#define  QUADSPI_CR_SMIE                         0x00080000U            /*!< Status Match Interrupt Enable      */
-#define  QUADSPI_CR_TOIE                         0x00100000U            /*!< TimeOut Interrupt Enable           */
-#define  QUADSPI_CR_APMS                         0x00400000U            /*!< Bit 1 */
-#define  QUADSPI_CR_PMM                          0x00800000U            /*!< Polling Match Mode                 */
-#define  QUADSPI_CR_PRESCALER                    0xFF000000U            /*!< PRESCALER[7:0] Clock prescaler     */
-#define  QUADSPI_CR_PRESCALER_0                  0x01000000U            /*!< Bit 0 */
-#define  QUADSPI_CR_PRESCALER_1                  0x02000000U            /*!< Bit 1 */
-#define  QUADSPI_CR_PRESCALER_2                  0x04000000U            /*!< Bit 2 */
-#define  QUADSPI_CR_PRESCALER_3                  0x08000000U            /*!< Bit 3 */
-#define  QUADSPI_CR_PRESCALER_4                  0x10000000U            /*!< Bit 4 */
-#define  QUADSPI_CR_PRESCALER_5                  0x20000000U            /*!< Bit 5 */
-#define  QUADSPI_CR_PRESCALER_6                  0x40000000U            /*!< Bit 6 */
-#define  QUADSPI_CR_PRESCALER_7                  0x80000000U            /*!< Bit 7 */
-
-/*****************  Bit definition for QUADSPI_DCR register  ******************/
-#define  QUADSPI_DCR_CKMODE                      0x00000001U            /*!< Mode 0 / Mode 3                 */
-#define  QUADSPI_DCR_CSHT                        0x00000700U            /*!< CSHT[2:0]: ChipSelect High Time */
-#define  QUADSPI_DCR_CSHT_0                      0x00000100U            /*!< Bit 0 */
-#define  QUADSPI_DCR_CSHT_1                      0x00000200U            /*!< Bit 1 */
-#define  QUADSPI_DCR_CSHT_2                      0x00000400U            /*!< Bit 2 */
-#define  QUADSPI_DCR_FSIZE                       0x001F0000U            /*!< FSIZE[4:0]: Flash Size          */
-#define  QUADSPI_DCR_FSIZE_0                     0x00010000U            /*!< Bit 0 */
-#define  QUADSPI_DCR_FSIZE_1                     0x00020000U            /*!< Bit 1 */
-#define  QUADSPI_DCR_FSIZE_2                     0x00040000U            /*!< Bit 2 */
-#define  QUADSPI_DCR_FSIZE_3                     0x00080000U            /*!< Bit 3 */
-#define  QUADSPI_DCR_FSIZE_4                     0x00100000U            /*!< Bit 4 */
-
-/******************  Bit definition for QUADSPI_SR register  *******************/
-#define  QUADSPI_SR_TEF                          0x00000001U             /*!< Transfer Error Flag    */
-#define  QUADSPI_SR_TCF                          0x00000002U             /*!< Transfer Complete Flag */
-#define  QUADSPI_SR_FTF                          0x00000004U             /*!< FIFO Threshlod Flag    */
-#define  QUADSPI_SR_SMF                          0x00000008U             /*!< Status Match Flag      */
-#define  QUADSPI_SR_TOF                          0x00000010U             /*!< Timeout Flag           */
-#define  QUADSPI_SR_BUSY                         0x00000020U             /*!< Busy                   */
-#define  QUADSPI_SR_FLEVEL                       0x00003F00U             /*!< FIFO Threshlod Flag    */
-#define  QUADSPI_SR_FLEVEL_0                     0x00000100U             /*!< Bit 0 */
-#define  QUADSPI_SR_FLEVEL_1                     0x00000200U             /*!< Bit 1 */
-#define  QUADSPI_SR_FLEVEL_2                     0x00000400U             /*!< Bit 2 */
-#define  QUADSPI_SR_FLEVEL_3                     0x00000800U             /*!< Bit 3 */
-#define  QUADSPI_SR_FLEVEL_4                     0x00001000U             /*!< Bit 4 */
-#define  QUADSPI_SR_FLEVEL_5                     0x00002000U             /*!< Bit 5 */
-
-/******************  Bit definition for QUADSPI_FCR register  ******************/
-#define  QUADSPI_FCR_CTEF                        0x00000001U             /*!< Clear Transfer Error Flag    */
-#define  QUADSPI_FCR_CTCF                        0x00000002U             /*!< Clear Transfer Complete Flag */
-#define  QUADSPI_FCR_CSMF                        0x00000008U             /*!< Clear Status Match Flag      */
-#define  QUADSPI_FCR_CTOF                        0x00000010U             /*!< Clear Timeout Flag           */
-
-/******************  Bit definition for QUADSPI_DLR register  ******************/
-#define  QUADSPI_DLR_DL                        0xFFFFFFFFU               /*!< DL[31:0]: Data Length */
-
-/******************  Bit definition for QUADSPI_CCR register  ******************/
-#define  QUADSPI_CCR_INSTRUCTION                  0x000000FFU            /*!< INSTRUCTION[7:0]: Instruction */
-#define  QUADSPI_CCR_INSTRUCTION_0                0x00000001U            /*!< Bit 0 */
-#define  QUADSPI_CCR_INSTRUCTION_1                0x00000002U            /*!< Bit 1 */
-#define  QUADSPI_CCR_INSTRUCTION_2                0x00000004U            /*!< Bit 2 */
-#define  QUADSPI_CCR_INSTRUCTION_3                0x00000008U            /*!< Bit 3 */
-#define  QUADSPI_CCR_INSTRUCTION_4                0x00000010U            /*!< Bit 4 */
-#define  QUADSPI_CCR_INSTRUCTION_5                0x00000020U            /*!< Bit 5 */
-#define  QUADSPI_CCR_INSTRUCTION_6                0x00000040U            /*!< Bit 6 */
-#define  QUADSPI_CCR_INSTRUCTION_7                0x00000080U            /*!< Bit 7 */
-#define  QUADSPI_CCR_IMODE                        0x00000300U            /*!< IMODE[1:0]: Instruction Mode     */
-#define  QUADSPI_CCR_IMODE_0                      0x00000100U            /*!< Bit 0 */
-#define  QUADSPI_CCR_IMODE_1                      0x00000200U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ADMODE                       0x00000C00U            /*!< ADMODE[1:0]: Address Mode         */
-#define  QUADSPI_CCR_ADMODE_0                     0x00000400U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ADMODE_1                     0x00000800U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ADSIZE                       0x00003000U            /*!< ADSIZE[1:0]: Address Size         */
-#define  QUADSPI_CCR_ADSIZE_0                     0x00001000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ADSIZE_1                     0x00002000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ABMODE                       0x0000C000U            /*!< ABMODE[1:0]: Alternate Bytes Mode */
-#define  QUADSPI_CCR_ABMODE_0                     0x00004000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ABMODE_1                     0x00008000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ABSIZE                       0x00030000U            /*!< ABSIZE[1:0]: Instruction Mode     */
-#define  QUADSPI_CCR_ABSIZE_0                     0x00010000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ABSIZE_1                     0x00020000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_DCYC                         0x007C0000U            /*!< DCYC[4:0]: Dummy Cycles           */
-#define  QUADSPI_CCR_DCYC_0                       0x00040000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_DCYC_1                       0x00080000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_DCYC_2                       0x00100000U            /*!< Bit 2 */
-#define  QUADSPI_CCR_DCYC_3                       0x00200000U            /*!< Bit 3 */
-#define  QUADSPI_CCR_DCYC_4                       0x00400000U            /*!< Bit 4 */
-#define  QUADSPI_CCR_DMODE                        0x03000000U            /*!< DMODE[1:0]: Data Mode                */
-#define  QUADSPI_CCR_DMODE_0                      0x01000000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_DMODE_1                      0x02000000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_FMODE                        0x0C000000U            /*!< FMODE[1:0]: Functional Mode           */
-#define  QUADSPI_CCR_FMODE_0                      0x04000000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_FMODE_1                      0x08000000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_SIOO                         0x10000000U            /*!< SIOO: Send Instruction Only Once Mode */
-#define  QUADSPI_CCR_DHHC                         0x40000000U            /*!< DHHC: Delay Half Hclk Cycle           */
-#define  QUADSPI_CCR_DDRM                         0x80000000U            /*!< DDRM: Double Data Rate Mode           */ 
-/******************  Bit definition for QUADSPI_AR register  *******************/
-#define  QUADSPI_AR_ADDRESS                       0xFFFFFFFFU            /*!< ADDRESS[31:0]: Address                */
-
-/******************  Bit definition for QUADSPI_ABR register  ******************/
-#define  QUADSPI_ABR_ALTERNATE                    0xFFFFFFFFU            /*!< ALTERNATE[31:0]: Alternate Bytes      */
-
-/******************  Bit definition for QUADSPI_DR register  *******************/
-#define  QUADSPI_DR_DATA                          0xFFFFFFFFU            /*!< DATA[31:0]: Data                      */
-
-/******************  Bit definition for QUADSPI_PSMKR register  ****************/
-#define  QUADSPI_PSMKR_MASK                       0xFFFFFFFFU            /*!< MASK[31:0]: Status Mask               */
-
-/******************  Bit definition for QUADSPI_PSMAR register  ****************/
-#define  QUADSPI_PSMAR_MATCH                      0xFFFFFFFFU            /*!< MATCH[31:0]: Status Match             */
-
-/******************  Bit definition for QUADSPI_PIR register  *****************/
-#define  QUADSPI_PIR_INTERVAL                     0x0000FFFFU            /*!< INTERVAL[15:0]: Polling Interval      */
-
-/******************  Bit definition for QUADSPI_LPTR register  *****************/
-#define  QUADSPI_LPTR_TIMEOUT                     0x0000FFFFU            /*!< TIMEOUT[15:0]: Timeout period         */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        0x00000001U
-#define  RCC_CR_HSIRDY                       0x00000002U
-
-#define  RCC_CR_HSITRIM                      0x000000F8U
-#define  RCC_CR_HSITRIM_0                    0x00000008U/*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    0x00000010U/*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    0x00000020U/*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    0x00000040U/*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    0x00000080U/*!<Bit 4 */
-
-#define  RCC_CR_HSICAL                       0x0000FF00U
-#define  RCC_CR_HSICAL_0                     0x00000100U/*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     0x00000200U/*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     0x00000400U/*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     0x00000800U/*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     0x00001000U/*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     0x00002000U/*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     0x00004000U/*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     0x00008000U/*!<Bit 7 */
-
-#define  RCC_CR_HSEON                        0x00010000U
-#define  RCC_CR_HSERDY                       0x00020000U
-#define  RCC_CR_HSEBYP                       0x00040000U
-#define  RCC_CR_CSSON                        0x00080000U
-#define  RCC_CR_PLLON                        0x01000000U
-#define  RCC_CR_PLLRDY                       0x02000000U
-#define  RCC_CR_PLLI2SON                     0x04000000U
-#define  RCC_CR_PLLI2SRDY                    0x08000000U
-#define  RCC_CR_PLLSAION                     0x10000000U
-#define  RCC_CR_PLLSAIRDY                    0x20000000U
-
-/********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    0x0000003FU
-#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
-#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
-#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
-#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
-#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
-#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
-
-#define  RCC_PLLCFGR_PLLN                     0x00007FC0U
-#define  RCC_PLLCFGR_PLLN_0                   0x00000040U
-#define  RCC_PLLCFGR_PLLN_1                   0x00000080U
-#define  RCC_PLLCFGR_PLLN_2                   0x00000100U
-#define  RCC_PLLCFGR_PLLN_3                   0x00000200U
-#define  RCC_PLLCFGR_PLLN_4                   0x00000400U
-#define  RCC_PLLCFGR_PLLN_5                   0x00000800U
-#define  RCC_PLLCFGR_PLLN_6                   0x00001000U
-#define  RCC_PLLCFGR_PLLN_7                   0x00002000U
-#define  RCC_PLLCFGR_PLLN_8                   0x00004000U
-
-#define  RCC_PLLCFGR_PLLP                    0x00030000U
-#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
-#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
-
-#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
-
-#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
-#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
-#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
-#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
-#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
-
-#define  RCC_PLLCFGR_PLLR                    0x70000000U
-#define  RCC_PLLCFGR_PLLR_0                  0x10000000U
-#define  RCC_PLLCFGR_PLLR_1                  0x20000000U
-#define  RCC_PLLCFGR_PLLR_2                  0x40000000U
-
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-/*!< SW configuration */
-#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
-
-#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock      */
-#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock      */
-#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL/PLLP selected as system clock */
-#define  RCC_CFGR_SW_PLLR                    0x00000003U        /*!< PLL/PLLR selected as system clock */
-
-/*!< SWS configuration */
-#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
-
-#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL/PLLP used as system clock       */
-#define  RCC_CFGR_SWS_PLLR                   0x0000000CU        /*!< PLL/PLLR used as system clock       */
-
-/*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
-
-#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
-
-/*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     0x001F0000U
-#define  RCC_CFGR_RTCPRE_0                   0x00010000U
-#define  RCC_CFGR_RTCPRE_1                   0x00020000U
-#define  RCC_CFGR_RTCPRE_2                   0x00040000U
-#define  RCC_CFGR_RTCPRE_3                   0x00080000U
-#define  RCC_CFGR_RTCPRE_4                   0x00100000U
-
-/*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       0x00600000U
-#define  RCC_CFGR_MCO1_0                     0x00200000U
-#define  RCC_CFGR_MCO1_1                     0x00400000U
-
-#define  RCC_CFGR_I2SSRC                     0x00800000U
-
-#define  RCC_CFGR_MCO1PRE                    0x07000000U
-#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
-#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
-#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
-
-#define  RCC_CFGR_MCO2PRE                    0x38000000U
-#define  RCC_CFGR_MCO2PRE_0                  0x08000000U
-#define  RCC_CFGR_MCO2PRE_1                  0x10000000U
-#define  RCC_CFGR_MCO2PRE_2                  0x20000000U
-
-#define  RCC_CFGR_MCO2                       0xC0000000U
-#define  RCC_CFGR_MCO2_0                     0x40000000U
-#define  RCC_CFGR_MCO2_1                     0x80000000U
-
-/********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     0x00000001U
-#define  RCC_CIR_LSERDYF                     0x00000002U
-#define  RCC_CIR_HSIRDYF                     0x00000004U
-#define  RCC_CIR_HSERDYF                     0x00000008U
-#define  RCC_CIR_PLLRDYF                     0x00000010U
-#define  RCC_CIR_PLLI2SRDYF                  0x00000020U
-#define  RCC_CIR_PLLSAIRDYF                  0x00000040U
-#define  RCC_CIR_CSSF                        0x00000080U
-#define  RCC_CIR_LSIRDYIE                    0x00000100U
-#define  RCC_CIR_LSERDYIE                    0x00000200U
-#define  RCC_CIR_HSIRDYIE                    0x00000400U
-#define  RCC_CIR_HSERDYIE                    0x00000800U
-#define  RCC_CIR_PLLRDYIE                    0x00001000U
-#define  RCC_CIR_PLLI2SRDYIE                 0x00002000U
-#define  RCC_CIR_PLLSAIRDYIE                 0x00004000U
-#define  RCC_CIR_LSIRDYC                     0x00010000U
-#define  RCC_CIR_LSERDYC                     0x00020000U
-#define  RCC_CIR_HSIRDYC                     0x00040000U
-#define  RCC_CIR_HSERDYC                     0x00080000U
-#define  RCC_CIR_PLLRDYC                     0x00100000U
-#define  RCC_CIR_PLLI2SRDYC                  0x00200000U
-#define  RCC_CIR_PLLSAIRDYC                  0x00400000U
-#define  RCC_CIR_CSSC                        0x00800000U
-
-/********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
-#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
-#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
-#define  RCC_AHB1RSTR_GPIODRST               0x00000008U
-#define  RCC_AHB1RSTR_GPIOERST               0x00000010U
-#define  RCC_AHB1RSTR_GPIOFRST               0x00000020U
-#define  RCC_AHB1RSTR_GPIOGRST               0x00000040U
-#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
-#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
-#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
-#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
-#define  RCC_AHB1RSTR_OTGHRST                0x20000000U
-
-/********************  Bit definition for RCC_AHB2RSTR register  **************/
-#define  RCC_AHB2RSTR_DCMIRST                0x00000001U
-#define  RCC_AHB2RSTR_OTGFSRST               0x00000080U
-
-/********************  Bit definition for RCC_AHB3RSTR register  **************/
-#define  RCC_AHB3RSTR_FMCRST                0x00000001U
-#define  RCC_AHB3RSTR_QSPIRST               0x00000002U
-
-/********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM2RST                0x00000001U
-#define  RCC_APB1RSTR_TIM3RST                0x00000002U
-#define  RCC_APB1RSTR_TIM4RST                0x00000004U
-#define  RCC_APB1RSTR_TIM5RST                0x00000008U
-#define  RCC_APB1RSTR_TIM6RST                0x00000010U
-#define  RCC_APB1RSTR_TIM7RST                0x00000020U
-#define  RCC_APB1RSTR_TIM12RST               0x00000040U
-#define  RCC_APB1RSTR_TIM13RST               0x00000080U
-#define  RCC_APB1RSTR_TIM14RST               0x00000100U
-#define  RCC_APB1RSTR_WWDGRST                0x00000800U
-#define  RCC_APB1RSTR_SPI2RST                0x00004000U
-#define  RCC_APB1RSTR_SPI3RST                0x00008000U
-#define  RCC_APB1RSTR_SPDIFRXRST             0x00010000U
-#define  RCC_APB1RSTR_USART2RST              0x00020000U
-#define  RCC_APB1RSTR_USART3RST              0x00040000U
-#define  RCC_APB1RSTR_UART4RST               0x00080000U
-#define  RCC_APB1RSTR_UART5RST               0x00100000U
-#define  RCC_APB1RSTR_I2C1RST                0x00200000U
-#define  RCC_APB1RSTR_I2C2RST                0x00400000U
-#define  RCC_APB1RSTR_I2C3RST                0x00800000U
-#define  RCC_APB1RSTR_FMPI2C1RST             0x01000000U
-#define  RCC_APB1RSTR_CAN1RST                0x02000000U
-#define  RCC_APB1RSTR_CAN2RST                0x04000000U
-#define  RCC_APB1RSTR_CECRST                 0x08000000U
-#define  RCC_APB1RSTR_PWRRST                 0x10000000U
-#define  RCC_APB1RSTR_DACRST                 0x20000000U
-
-/********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                0x00000001U
-#define  RCC_APB2RSTR_TIM8RST                0x00000002U
-#define  RCC_APB2RSTR_USART1RST              0x00000010U
-#define  RCC_APB2RSTR_USART6RST              0x00000020U
-#define  RCC_APB2RSTR_ADCRST                 0x00000100U
-#define  RCC_APB2RSTR_SDIORST                0x00000800U
-#define  RCC_APB2RSTR_SPI1RST                0x00001000U
-#define  RCC_APB2RSTR_SPI4RST                0x00002000U
-#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
-#define  RCC_APB2RSTR_TIM9RST                0x00010000U
-#define  RCC_APB2RSTR_TIM10RST               0x00020000U
-#define  RCC_APB2RSTR_TIM11RST               0x00040000U
-#define  RCC_APB2RSTR_SAI1RST                0x00400000U
-#define  RCC_APB2RSTR_SAI2RST                0x00800000U
-
-/* Old SPI1RST bit definition, maintained for legacy purpose */
-#define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
-
-/********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
-#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
-#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
-#define  RCC_AHB1ENR_GPIODEN                 0x00000008U
-#define  RCC_AHB1ENR_GPIOEEN                 0x00000010U
-#define  RCC_AHB1ENR_GPIOFEN                 0x00000020U
-#define  RCC_AHB1ENR_GPIOGEN                 0x00000040U
-#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
-
-#define  RCC_AHB1ENR_CRCEN                   0x00001000U
-#define  RCC_AHB1ENR_BKPSRAMEN               0x00040000U
-#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
-#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
-
-#define  RCC_AHB1ENR_OTGHSEN                 0x20000000U
-#define  RCC_AHB1ENR_OTGHSULPIEN             0x40000000U
-
-/********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define  RCC_AHB2ENR_DCMIEN                  0x00000001U
-#define  RCC_AHB2ENR_OTGFSEN                 0x00000080U
-
-/********************  Bit definition for RCC_AHB3ENR register  ***************/
-#define  RCC_AHB3ENR_FMCEN                  0x00000001U
-#define  RCC_AHB3ENR_QSPIEN                 0x00000002U
-
-/********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM2EN                  0x00000001U
-#define  RCC_APB1ENR_TIM3EN                  0x00000002U
-#define  RCC_APB1ENR_TIM4EN                  0x00000004U
-#define  RCC_APB1ENR_TIM5EN                  0x00000008U
-#define  RCC_APB1ENR_TIM6EN                  0x00000010U
-#define  RCC_APB1ENR_TIM7EN                  0x00000020U
-#define  RCC_APB1ENR_TIM12EN                 0x00000040U
-#define  RCC_APB1ENR_TIM13EN                 0x00000080U
-#define  RCC_APB1ENR_TIM14EN                 0x00000100U
-#define  RCC_APB1ENR_WWDGEN                  0x00000800U
-#define  RCC_APB1ENR_SPI2EN                  0x00004000U
-#define  RCC_APB1ENR_SPI3EN                  0x00008000U
-#define  RCC_APB1ENR_SPDIFRXEN               0x00010000U
-#define  RCC_APB1ENR_USART2EN                0x00020000U
-#define  RCC_APB1ENR_USART3EN                0x00040000U
-#define  RCC_APB1ENR_UART4EN                 0x00080000U
-#define  RCC_APB1ENR_UART5EN                 0x00100000U
-#define  RCC_APB1ENR_I2C1EN                  0x00200000U
-#define  RCC_APB1ENR_I2C2EN                  0x00400000U
-#define  RCC_APB1ENR_I2C3EN                  0x00800000U
-#define  RCC_APB1ENR_FMPI2C1EN               0x01000000U
-#define  RCC_APB1ENR_CAN1EN                  0x02000000U
-#define  RCC_APB1ENR_CAN2EN                  0x04000000U
-#define  RCC_APB1ENR_CECEN                   0x08000000U
-#define  RCC_APB1ENR_PWREN                   0x10000000U
-#define  RCC_APB1ENR_DACEN                   0x20000000U
-
-/********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  0x00000001U
-#define  RCC_APB2ENR_TIM8EN                  0x00000002U
-#define  RCC_APB2ENR_USART1EN                0x00000010U
-#define  RCC_APB2ENR_USART6EN                0x00000020U
-#define  RCC_APB2ENR_ADC1EN                  0x00000100U
-#define  RCC_APB2ENR_ADC2EN                  0x00000200U
-#define  RCC_APB2ENR_ADC3EN                  0x00000400U
-#define  RCC_APB2ENR_SDIOEN                  0x00000800U
-#define  RCC_APB2ENR_SPI1EN                  0x00001000U
-#define  RCC_APB2ENR_SPI4EN                  0x00002000U
-#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
-#define  RCC_APB2ENR_TIM9EN                  0x00010000U
-#define  RCC_APB2ENR_TIM10EN                 0x00020000U
-#define  RCC_APB2ENR_TIM11EN                 0x00040000U
-#define  RCC_APB2ENR_SAI1EN                  0x00400000U
-#define  RCC_APB2ENR_SAI2EN                  0x00800000U
-
-/********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
-#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
-#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
-#define  RCC_AHB1LPENR_GPIODLPEN             0x00000008U
-#define  RCC_AHB1LPENR_GPIOELPEN             0x00000010U
-#define  RCC_AHB1LPENR_GPIOFLPEN             0x00000020U
-#define  RCC_AHB1LPENR_GPIOGLPEN             0x00000040U
-#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
-#define  RCC_AHB1LPENR_GPIOILPEN             0x00000100U
-#define  RCC_AHB1LPENR_GPIOJLPEN             0x00000200U
-#define  RCC_AHB1LPENR_GPIOKLPEN             0x00000400U
-
-#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
-#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
-#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
-#define  RCC_AHB1LPENR_SRAM2LPEN             0x00020000U
-#define  RCC_AHB1LPENR_BKPSRAMLPEN           0x00040000U
-#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
-#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
-
-#define  RCC_AHB1LPENR_OTGHSLPEN             0x20000000U
-#define  RCC_AHB1LPENR_OTGHSULPILPEN         0x40000000U
-
-/********************  Bit definition for RCC_AHB2LPENR register  *************/
-#define  RCC_AHB2LPENR_DCMILPEN              0x00000001U
-#define  RCC_AHB2LPENR_OTGFSLPEN             0x00000080U
-
-/********************  Bit definition for RCC_AHB3LPENR register  *************/
-#define  RCC_AHB3LPENR_FMCLPEN              0x00000001U
-#define  RCC_AHB3LPENR_QSPILPEN             0x00000002U
-
-/********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM2LPEN              0x00000001U
-#define  RCC_APB1LPENR_TIM3LPEN              0x00000002U
-#define  RCC_APB1LPENR_TIM4LPEN              0x00000004U
-#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
-#define  RCC_APB1LPENR_TIM6LPEN              0x00000010U
-#define  RCC_APB1LPENR_TIM7LPEN              0x00000020U
-#define  RCC_APB1LPENR_TIM12LPEN             0x00000040U
-#define  RCC_APB1LPENR_TIM13LPEN             0x00000080U
-#define  RCC_APB1LPENR_TIM14LPEN             0x00000100U
-#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
-#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U
-#define  RCC_APB1LPENR_SPI3LPEN              0x00008000U
-#define  RCC_APB1LPENR_SPDIFRXLPEN           0x00010000U
-#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
-#define  RCC_APB1LPENR_USART3LPEN            0x00040000U
-#define  RCC_APB1LPENR_UART4LPEN             0x00080000U
-#define  RCC_APB1LPENR_UART5LPEN             0x00100000U
-#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
-#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
-#define  RCC_APB1LPENR_I2C3LPEN              0x00800000U
-#define  RCC_APB1LPENR_FMPI2C1LPEN           0x01000000U
-#define  RCC_APB1LPENR_CAN1LPEN              0x02000000U
-#define  RCC_APB1LPENR_CAN2LPEN              0x04000000U
-#define  RCC_APB1LPENR_CECLPEN               0x08000000U
-#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
-#define  RCC_APB1LPENR_DACLPEN               0x20000000U
-
-/********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
-#define  RCC_APB2LPENR_TIM8LPEN              0x00000002U
-#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
-#define  RCC_APB2LPENR_USART6LPEN            0x00000020U
-#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
-#define  RCC_APB2LPENR_ADC2LPEN              0x00000200U
-#define  RCC_APB2LPENR_ADC3LPEN              0x00000400U
-#define  RCC_APB2LPENR_SDIOLPEN              0x00000800U
-#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
-#define  RCC_APB2LPENR_SPI4LPEN              0x00002000U
-#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
-#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
-#define  RCC_APB2LPENR_TIM10LPEN             0x00020000U
-#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
-#define  RCC_APB2LPENR_SAI1LPEN              0x00400000U
-#define  RCC_APB2LPENR_SAI2LPEN              0x00800000U
-
-/********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      0x00000001U
-#define  RCC_BDCR_LSERDY                     0x00000002U
-#define  RCC_BDCR_LSEBYP                     0x00000004U
-#define  RCC_BDCR_LSEMOD                     0x00000008U
-
-#define  RCC_BDCR_RTCSEL                    0x00000300U
-#define  RCC_BDCR_RTCSEL_0                  0x00000100U
-#define  RCC_BDCR_RTCSEL_1                  0x00000200U
-
-#define  RCC_BDCR_RTCEN                      0x00008000U
-#define  RCC_BDCR_BDRST                      0x00010000U
-
-/********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       0x00000001U
-#define  RCC_CSR_LSIRDY                      0x00000002U
-#define  RCC_CSR_RMVF                        0x01000000U
-#define  RCC_CSR_BORRSTF                     0x02000000U
-#define  RCC_CSR_PADRSTF                     0x04000000U
-#define  RCC_CSR_PORRSTF                     0x08000000U
-#define  RCC_CSR_SFTRSTF                     0x10000000U
-#define  RCC_CSR_WDGRSTF                     0x20000000U
-#define  RCC_CSR_WWDGRSTF                    0x40000000U
-#define  RCC_CSR_LPWRRSTF                    0x80000000U
-
-/********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    0x00001FFFU
-#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
-#define  RCC_SSCGR_SPREADSEL                 0x40000000U
-#define  RCC_SSCGR_SSCGEN                    0x80000000U
-
-/********************  Bit definition for RCC_PLLI2SCFGR register  ************/
-#define  RCC_PLLI2SCFGR_PLLI2SM              0x0000003FU
-#define  RCC_PLLI2SCFGR_PLLI2SM_0            0x00000001U
-#define  RCC_PLLI2SCFGR_PLLI2SM_1            0x00000002U
-#define  RCC_PLLI2SCFGR_PLLI2SM_2            0x00000004U
-#define  RCC_PLLI2SCFGR_PLLI2SM_3            0x00000008U
-#define  RCC_PLLI2SCFGR_PLLI2SM_4            0x00000010U
-#define  RCC_PLLI2SCFGR_PLLI2SM_5            0x00000020U
-
-#define  RCC_PLLI2SCFGR_PLLI2SN              0x00007FC0U
-#define  RCC_PLLI2SCFGR_PLLI2SN_0            0x00000040U
-#define  RCC_PLLI2SCFGR_PLLI2SN_1            0x00000080U
-#define  RCC_PLLI2SCFGR_PLLI2SN_2            0x00000100U
-#define  RCC_PLLI2SCFGR_PLLI2SN_3            0x00000200U
-#define  RCC_PLLI2SCFGR_PLLI2SN_4            0x00000400U
-#define  RCC_PLLI2SCFGR_PLLI2SN_5            0x00000800U
-#define  RCC_PLLI2SCFGR_PLLI2SN_6            0x00001000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_7            0x00002000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_8            0x00004000U
-
-#define  RCC_PLLI2SCFGR_PLLI2SP              0x00030000U
-#define  RCC_PLLI2SCFGR_PLLI2SP_0            0x00010000U
-#define  RCC_PLLI2SCFGR_PLLI2SP_1            0x00020000U
-
-#define  RCC_PLLI2SCFGR_PLLI2SQ              0x0F000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_0            0x01000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_1            0x02000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_2            0x04000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_3            0x08000000U
-
-#define  RCC_PLLI2SCFGR_PLLI2SR              0x70000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_0            0x10000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_1            0x20000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_2            0x40000000U
-
-
-/********************  Bit definition for RCC_PLLSAICFGR register  ************/
-#define  RCC_PLLSAICFGR_PLLSAIM              0x0000003FU
-#define  RCC_PLLSAICFGR_PLLSAIM_0            0x00000001U
-#define  RCC_PLLSAICFGR_PLLSAIM_1            0x00000002U
-#define  RCC_PLLSAICFGR_PLLSAIM_2            0x00000004U
-#define  RCC_PLLSAICFGR_PLLSAIM_3            0x00000008U
-#define  RCC_PLLSAICFGR_PLLSAIM_4            0x00000010U
-#define  RCC_PLLSAICFGR_PLLSAIM_5            0x00000020U
-
-#define  RCC_PLLSAICFGR_PLLSAIN              0x00007FC0U
-#define  RCC_PLLSAICFGR_PLLSAIN_0            0x00000040U
-#define  RCC_PLLSAICFGR_PLLSAIN_1            0x00000080U
-#define  RCC_PLLSAICFGR_PLLSAIN_2            0x00000100U
-#define  RCC_PLLSAICFGR_PLLSAIN_3            0x00000200U
-#define  RCC_PLLSAICFGR_PLLSAIN_4            0x00000400U
-#define  RCC_PLLSAICFGR_PLLSAIN_5            0x00000800U
-#define  RCC_PLLSAICFGR_PLLSAIN_6            0x00001000U
-#define  RCC_PLLSAICFGR_PLLSAIN_7            0x00002000U
-#define  RCC_PLLSAICFGR_PLLSAIN_8            0x00004000U
-
-#define  RCC_PLLSAICFGR_PLLSAIP              0x00030000U
-#define  RCC_PLLSAICFGR_PLLSAIP_0            0x00010000U
-#define  RCC_PLLSAICFGR_PLLSAIP_1            0x00020000U
-
-#define  RCC_PLLSAICFGR_PLLSAIQ              0x0F000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_0            0x01000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_1            0x02000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_2            0x04000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_3            0x08000000U
-
-/********************  Bit definition for RCC_DCKCFGR register  ***************/
-#define  RCC_DCKCFGR_PLLI2SDIVQ              0x0000001FU
-#define  RCC_DCKCFGR_PLLSAIDIVQ              0x00001F00U
-#define  RCC_DCKCFGR_SAI1SRC                 0x00300000U
-#define  RCC_DCKCFGR_SAI1SRC_0               0x00100000U
-#define  RCC_DCKCFGR_SAI1SRC_1               0x00200000U
-#define  RCC_DCKCFGR_SAI2SRC                 0x00C00000U
-#define  RCC_DCKCFGR_SAI2SRC_0               0x00400000U
-#define  RCC_DCKCFGR_SAI2SRC_1               0x00800000U
-#define  RCC_DCKCFGR_TIMPRE                  0x01000000U
-#define  RCC_DCKCFGR_I2S1SRC                 0x06000000U
-#define  RCC_DCKCFGR_I2S1SRC_0               0x02000000U
-#define  RCC_DCKCFGR_I2S1SRC_1               0x04000000U
-#define  RCC_DCKCFGR_I2S2SRC                 0x18000000U
-#define  RCC_DCKCFGR_I2S2SRC_0               0x08000000U
-#define  RCC_DCKCFGR_I2S2SRC_1               0x10000000U
-
-/********************  Bit definition for RCC_CKGATENR register  ***************/
-#define  RCC_CKGATENR_AHB2APB1_CKEN          0x00000001U
-#define  RCC_CKGATENR_AHB2APB2_CKEN          0x00000002U
-#define  RCC_CKGATENR_CM4DBG_CKEN            0x00000004U
-#define  RCC_CKGATENR_SPARE_CKEN             0x00000008U
-#define  RCC_CKGATENR_SRAM_CKEN              0x00000010U
-#define  RCC_CKGATENR_FLITF_CKEN             0x00000020U
-#define  RCC_CKGATENR_RCC_CKEN               0x00000040U
-
-/********************  Bit definition for RCC_DCKCFGR2 register  ***************/
-#define  RCC_DCKCFGR2_FMPI2C1SEL             0x00C00000U
-#define  RCC_DCKCFGR2_FMPI2C1SEL_0           0x00400000U
-#define  RCC_DCKCFGR2_FMPI2C1SEL_1           0x00800000U
-#define  RCC_DCKCFGR2_CECSEL                 0x04000000U
-#define  RCC_DCKCFGR2_CK48MSEL               0x08000000U
-#define  RCC_DCKCFGR2_SDIOSEL                0x10000000U
-#define  RCC_DCKCFGR2_SPDIFRXSEL             0x20000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            0x00400000U
-#define RTC_TR_HT                            0x00300000U
-#define RTC_TR_HT_0                          0x00100000U
-#define RTC_TR_HT_1                          0x00200000U
-#define RTC_TR_HU                            0x000F0000U
-#define RTC_TR_HU_0                          0x00010000U
-#define RTC_TR_HU_1                          0x00020000U
-#define RTC_TR_HU_2                          0x00040000U
-#define RTC_TR_HU_3                          0x00080000U
-#define RTC_TR_MNT                           0x00007000U
-#define RTC_TR_MNT_0                         0x00001000U
-#define RTC_TR_MNT_1                         0x00002000U
-#define RTC_TR_MNT_2                         0x00004000U
-#define RTC_TR_MNU                           0x00000F00U
-#define RTC_TR_MNU_0                         0x00000100U
-#define RTC_TR_MNU_1                         0x00000200U
-#define RTC_TR_MNU_2                         0x00000400U
-#define RTC_TR_MNU_3                         0x00000800U
-#define RTC_TR_ST                            0x00000070U
-#define RTC_TR_ST_0                          0x00000010U
-#define RTC_TR_ST_1                          0x00000020U
-#define RTC_TR_ST_2                          0x00000040U
-#define RTC_TR_SU                            0x0000000FU
-#define RTC_TR_SU_0                          0x00000001U
-#define RTC_TR_SU_1                          0x00000002U
-#define RTC_TR_SU_2                          0x00000004U
-#define RTC_TR_SU_3                          0x00000008U
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            0x00F00000U
-#define RTC_DR_YT_0                          0x00100000U
-#define RTC_DR_YT_1                          0x00200000U
-#define RTC_DR_YT_2                          0x00400000U
-#define RTC_DR_YT_3                          0x00800000U
-#define RTC_DR_YU                            0x000F0000U
-#define RTC_DR_YU_0                          0x00010000U
-#define RTC_DR_YU_1                          0x00020000U
-#define RTC_DR_YU_2                          0x00040000U
-#define RTC_DR_YU_3                          0x00080000U
-#define RTC_DR_WDU                           0x0000E000U
-#define RTC_DR_WDU_0                         0x00002000U
-#define RTC_DR_WDU_1                         0x00004000U
-#define RTC_DR_WDU_2                         0x00008000U
-#define RTC_DR_MT                            0x00001000U
-#define RTC_DR_MU                            0x00000F00U
-#define RTC_DR_MU_0                          0x00000100U
-#define RTC_DR_MU_1                          0x00000200U
-#define RTC_DR_MU_2                          0x00000400U
-#define RTC_DR_MU_3                          0x00000800U
-#define RTC_DR_DT                            0x00000030U
-#define RTC_DR_DT_0                          0x00000010U
-#define RTC_DR_DT_1                          0x00000020U
-#define RTC_DR_DU                            0x0000000FU
-#define RTC_DR_DU_0                          0x00000001U
-#define RTC_DR_DU_1                          0x00000002U
-#define RTC_DR_DU_2                          0x00000004U
-#define RTC_DR_DU_3                          0x00000008U
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           0x00800000U
-#define RTC_CR_OSEL                          0x00600000U
-#define RTC_CR_OSEL_0                        0x00200000U
-#define RTC_CR_OSEL_1                        0x00400000U
-#define RTC_CR_POL                           0x00100000U
-#define RTC_CR_COSEL                         0x00080000U
-#define RTC_CR_BCK                           0x00040000U
-#define RTC_CR_SUB1H                         0x00020000U
-#define RTC_CR_ADD1H                         0x00010000U
-#define RTC_CR_TSIE                          0x00008000U
-#define RTC_CR_WUTIE                         0x00004000U
-#define RTC_CR_ALRBIE                        0x00002000U
-#define RTC_CR_ALRAIE                        0x00001000U
-#define RTC_CR_TSE                           0x00000800U
-#define RTC_CR_WUTE                          0x00000400U
-#define RTC_CR_ALRBE                         0x00000200U
-#define RTC_CR_ALRAE                         0x00000100U
-#define RTC_CR_DCE                           0x00000080U
-#define RTC_CR_FMT                           0x00000040U
-#define RTC_CR_BYPSHAD                       0x00000020U
-#define RTC_CR_REFCKON                       0x00000010U
-#define RTC_CR_TSEDGE                        0x00000008U
-#define RTC_CR_WUCKSEL                       0x00000007U
-#define RTC_CR_WUCKSEL_0                     0x00000001U
-#define RTC_CR_WUCKSEL_1                     0x00000002U
-#define RTC_CR_WUCKSEL_2                     0x00000004U
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      0x00010000U
-#define RTC_ISR_TAMP1F                       0x00002000U
-#define RTC_ISR_TAMP2F                       0x00004000U
-#define RTC_ISR_TSOVF                        0x00001000U
-#define RTC_ISR_TSF                          0x00000800U
-#define RTC_ISR_WUTF                         0x00000400U
-#define RTC_ISR_ALRBF                        0x00000200U
-#define RTC_ISR_ALRAF                        0x00000100U
-#define RTC_ISR_INIT                         0x00000080U
-#define RTC_ISR_INITF                        0x00000040U
-#define RTC_ISR_RSF                          0x00000020U
-#define RTC_ISR_INITS                        0x00000010U
-#define RTC_ISR_SHPF                         0x00000008U
-#define RTC_ISR_WUTWF                        0x00000004U
-#define RTC_ISR_ALRBWF                       0x00000002U
-#define RTC_ISR_ALRAWF                       0x00000001U
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    0x007F0000U
-#define RTC_PRER_PREDIV_S                    0x00007FFFU
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS                       0x00000080U
-#define RTC_CALIBR_DC                        0x0000001FU
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      0x80000000U
-#define RTC_ALRMAR_WDSEL                     0x40000000U
-#define RTC_ALRMAR_DT                        0x30000000U
-#define RTC_ALRMAR_DT_0                      0x10000000U
-#define RTC_ALRMAR_DT_1                      0x20000000U
-#define RTC_ALRMAR_DU                        0x0F000000U
-#define RTC_ALRMAR_DU_0                      0x01000000U
-#define RTC_ALRMAR_DU_1                      0x02000000U
-#define RTC_ALRMAR_DU_2                      0x04000000U
-#define RTC_ALRMAR_DU_3                      0x08000000U
-#define RTC_ALRMAR_MSK3                      0x00800000U
-#define RTC_ALRMAR_PM                        0x00400000U
-#define RTC_ALRMAR_HT                        0x00300000U
-#define RTC_ALRMAR_HT_0                      0x00100000U
-#define RTC_ALRMAR_HT_1                      0x00200000U
-#define RTC_ALRMAR_HU                        0x000F0000U
-#define RTC_ALRMAR_HU_0                      0x00010000U
-#define RTC_ALRMAR_HU_1                      0x00020000U
-#define RTC_ALRMAR_HU_2                      0x00040000U
-#define RTC_ALRMAR_HU_3                      0x00080000U
-#define RTC_ALRMAR_MSK2                      0x00008000U
-#define RTC_ALRMAR_MNT                       0x00007000U
-#define RTC_ALRMAR_MNT_0                     0x00001000U
-#define RTC_ALRMAR_MNT_1                     0x00002000U
-#define RTC_ALRMAR_MNT_2                     0x00004000U
-#define RTC_ALRMAR_MNU                       0x00000F00U
-#define RTC_ALRMAR_MNU_0                     0x00000100U
-#define RTC_ALRMAR_MNU_1                     0x00000200U
-#define RTC_ALRMAR_MNU_2                     0x00000400U
-#define RTC_ALRMAR_MNU_3                     0x00000800U
-#define RTC_ALRMAR_MSK1                      0x00000080U
-#define RTC_ALRMAR_ST                        0x00000070U
-#define RTC_ALRMAR_ST_0                      0x00000010U
-#define RTC_ALRMAR_ST_1                      0x00000020U
-#define RTC_ALRMAR_ST_2                      0x00000040U
-#define RTC_ALRMAR_SU                        0x0000000FU
-#define RTC_ALRMAR_SU_0                      0x00000001U
-#define RTC_ALRMAR_SU_1                      0x00000002U
-#define RTC_ALRMAR_SU_2                      0x00000004U
-#define RTC_ALRMAR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      0x80000000U
-#define RTC_ALRMBR_WDSEL                     0x40000000U
-#define RTC_ALRMBR_DT                        0x30000000U
-#define RTC_ALRMBR_DT_0                      0x10000000U
-#define RTC_ALRMBR_DT_1                      0x20000000U
-#define RTC_ALRMBR_DU                        0x0F000000U
-#define RTC_ALRMBR_DU_0                      0x01000000U
-#define RTC_ALRMBR_DU_1                      0x02000000U
-#define RTC_ALRMBR_DU_2                      0x04000000U
-#define RTC_ALRMBR_DU_3                      0x08000000U
-#define RTC_ALRMBR_MSK3                      0x00800000U
-#define RTC_ALRMBR_PM                        0x00400000U
-#define RTC_ALRMBR_HT                        0x00300000U
-#define RTC_ALRMBR_HT_0                      0x00100000U
-#define RTC_ALRMBR_HT_1                      0x00200000U
-#define RTC_ALRMBR_HU                        0x000F0000U
-#define RTC_ALRMBR_HU_0                      0x00010000U
-#define RTC_ALRMBR_HU_1                      0x00020000U
-#define RTC_ALRMBR_HU_2                      0x00040000U
-#define RTC_ALRMBR_HU_3                      0x00080000U
-#define RTC_ALRMBR_MSK2                      0x00008000U
-#define RTC_ALRMBR_MNT                       0x00007000U
-#define RTC_ALRMBR_MNT_0                     0x00001000U
-#define RTC_ALRMBR_MNT_1                     0x00002000U
-#define RTC_ALRMBR_MNT_2                     0x00004000U
-#define RTC_ALRMBR_MNU                       0x00000F00U
-#define RTC_ALRMBR_MNU_0                     0x00000100U
-#define RTC_ALRMBR_MNU_1                     0x00000200U
-#define RTC_ALRMBR_MNU_2                     0x00000400U
-#define RTC_ALRMBR_MNU_3                     0x00000800U
-#define RTC_ALRMBR_MSK1                      0x00000080U
-#define RTC_ALRMBR_ST                        0x00000070U
-#define RTC_ALRMBR_ST_0                      0x00000010U
-#define RTC_ALRMBR_ST_1                      0x00000020U
-#define RTC_ALRMBR_ST_2                      0x00000040U
-#define RTC_ALRMBR_SU                        0x0000000FU
-#define RTC_ALRMBR_SU_0                      0x00000001U
-#define RTC_ALRMBR_SU_1                      0x00000002U
-#define RTC_ALRMBR_SU_2                      0x00000004U
-#define RTC_ALRMBR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          0x000000FFU
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           0x0000FFFFU
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     0x00007FFFU
-#define RTC_SHIFTR_ADD1S                     0x80000000U
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          0x00400000U
-#define RTC_TSTR_HT                          0x00300000U
-#define RTC_TSTR_HT_0                        0x00100000U
-#define RTC_TSTR_HT_1                        0x00200000U
-#define RTC_TSTR_HU                          0x000F0000U
-#define RTC_TSTR_HU_0                        0x00010000U
-#define RTC_TSTR_HU_1                        0x00020000U
-#define RTC_TSTR_HU_2                        0x00040000U
-#define RTC_TSTR_HU_3                        0x00080000U
-#define RTC_TSTR_MNT                         0x00007000U
-#define RTC_TSTR_MNT_0                       0x00001000U
-#define RTC_TSTR_MNT_1                       0x00002000U
-#define RTC_TSTR_MNT_2                       0x00004000U
-#define RTC_TSTR_MNU                         0x00000F00U
-#define RTC_TSTR_MNU_0                       0x00000100U
-#define RTC_TSTR_MNU_1                       0x00000200U
-#define RTC_TSTR_MNU_2                       0x00000400U
-#define RTC_TSTR_MNU_3                       0x00000800U
-#define RTC_TSTR_ST                          0x00000070U
-#define RTC_TSTR_ST_0                        0x00000010U
-#define RTC_TSTR_ST_1                        0x00000020U
-#define RTC_TSTR_ST_2                        0x00000040U
-#define RTC_TSTR_SU                          0x0000000FU
-#define RTC_TSTR_SU_0                        0x00000001U
-#define RTC_TSTR_SU_1                        0x00000002U
-#define RTC_TSTR_SU_2                        0x00000004U
-#define RTC_TSTR_SU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         0x0000E000U
-#define RTC_TSDR_WDU_0                       0x00002000U
-#define RTC_TSDR_WDU_1                       0x00004000U
-#define RTC_TSDR_WDU_2                       0x00008000U
-#define RTC_TSDR_MT                          0x00001000U
-#define RTC_TSDR_MU                          0x00000F00U
-#define RTC_TSDR_MU_0                        0x00000100U
-#define RTC_TSDR_MU_1                        0x00000200U
-#define RTC_TSDR_MU_2                        0x00000400U
-#define RTC_TSDR_MU_3                        0x00000800U
-#define RTC_TSDR_DT                          0x00000030U
-#define RTC_TSDR_DT_0                        0x00000010U
-#define RTC_TSDR_DT_1                        0x00000020U
-#define RTC_TSDR_DU                          0x0000000FU
-#define RTC_TSDR_DU_0                        0x00000001U
-#define RTC_TSDR_DU_1                        0x00000002U
-#define RTC_TSDR_DU_2                        0x00000004U
-#define RTC_TSDR_DU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        0x00008000U
-#define RTC_CALR_CALW8                       0x00004000U
-#define RTC_CALR_CALW16                      0x00002000U
-#define RTC_CALR_CALM                        0x000001FFU
-#define RTC_CALR_CALM_0                      0x00000001U
-#define RTC_CALR_CALM_1                      0x00000002U
-#define RTC_CALR_CALM_2                      0x00000004U
-#define RTC_CALR_CALM_3                      0x00000008U
-#define RTC_CALR_CALM_4                      0x00000010U
-#define RTC_CALR_CALM_5                      0x00000020U
-#define RTC_CALR_CALM_6                      0x00000040U
-#define RTC_CALR_CALM_7                      0x00000080U
-#define RTC_CALR_CALM_8                      0x00000100U
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               0x00040000U
-#define RTC_TAFCR_TSINSEL                    0x00020000U
-#define RTC_TAFCR_TAMPINSEL                  0x00010000U
-#define RTC_TAFCR_TAMPPUDIS                  0x00008000U
-#define RTC_TAFCR_TAMPPRCH                   0x00006000U
-#define RTC_TAFCR_TAMPPRCH_0                 0x00002000U
-#define RTC_TAFCR_TAMPPRCH_1                 0x00004000U
-#define RTC_TAFCR_TAMPFLT                    0x00001800U
-#define RTC_TAFCR_TAMPFLT_0                  0x00000800U
-#define RTC_TAFCR_TAMPFLT_1                  0x00001000U
-#define RTC_TAFCR_TAMPFREQ                   0x00000700U
-#define RTC_TAFCR_TAMPFREQ_0                 0x00000100U
-#define RTC_TAFCR_TAMPFREQ_1                 0x00000200U
-#define RTC_TAFCR_TAMPFREQ_2                 0x00000400U
-#define RTC_TAFCR_TAMPTS                     0x00000080U
-#define RTC_TAFCR_TAMP2TRG                   0x00000010U
-#define RTC_TAFCR_TAMP2E                     0x00000008U
-#define RTC_TAFCR_TAMPIE                     0x00000004U
-#define RTC_TAFCR_TAMP1TRG                   0x00000002U
-#define RTC_TAFCR_TAMP1E                     0x00000001U
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  0x0F000000U
-#define RTC_ALRMASSR_MASKSS_0                0x01000000U
-#define RTC_ALRMASSR_MASKSS_1                0x02000000U
-#define RTC_ALRMASSR_MASKSS_2                0x04000000U
-#define RTC_ALRMASSR_MASKSS_3                0x08000000U
-#define RTC_ALRMASSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
-#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
-#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
-#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
-#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
-#define RTC_ALRMBSSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           0xFFFFFFFFU
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Serial Audio Interface                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for SAI_GCR register  *******************/
-#define  SAI_GCR_SYNCIN                  0x00000003U        /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
-#define  SAI_GCR_SYNCIN_0                0x00000001U        /*!<Bit 0 */
-#define  SAI_GCR_SYNCIN_1                0x00000002U        /*!<Bit 1 */
-
-#define  SAI_GCR_SYNCOUT                 0x00000030U        /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
-#define  SAI_GCR_SYNCOUT_0               0x00000010U        /*!<Bit 0 */
-#define  SAI_GCR_SYNCOUT_1               0x00000020U        /*!<Bit 1 */
-
-/*******************  Bit definition for SAI_xCR1 register  *******************/
-#define  SAI_xCR1_MODE                    0x00000003U        /*!<MODE[1:0] bits (Audio Block Mode)           */
-#define  SAI_xCR1_MODE_0                  0x00000001U        /*!<Bit 0 */
-#define  SAI_xCR1_MODE_1                  0x00000002U        /*!<Bit 1 */
-
-#define  SAI_xCR1_PRTCFG                  0x0000000CU        /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
-#define  SAI_xCR1_PRTCFG_0                0x00000004U        /*!<Bit 0 */
-#define  SAI_xCR1_PRTCFG_1                0x00000008U        /*!<Bit 1 */
-
-#define  SAI_xCR1_DS                      0x000000E0U        /*!<DS[1:0] bits (Data Size) */
-#define  SAI_xCR1_DS_0                    0x00000020U        /*!<Bit 0 */
-#define  SAI_xCR1_DS_1                    0x00000040U        /*!<Bit 1 */
-#define  SAI_xCR1_DS_2                    0x00000080U        /*!<Bit 2 */
-
-#define  SAI_xCR1_LSBFIRST                0x00000100U        /*!<LSB First Configuration  */
-#define  SAI_xCR1_CKSTR                   0x00000200U        /*!<ClocK STRobing edge      */
-
-#define  SAI_xCR1_SYNCEN                  0x00000C00U        /*!<SYNCEN[1:0](SYNChronization ENable) */
-#define  SAI_xCR1_SYNCEN_0                0x00000400U        /*!<Bit 0 */
-#define  SAI_xCR1_SYNCEN_1                0x00000800U        /*!<Bit 1 */
-
-#define  SAI_xCR1_MONO                    0x00001000U        /*!<Mono mode                  */
-#define  SAI_xCR1_OUTDRIV                 0x00002000U        /*!<Output Drive               */
-#define  SAI_xCR1_SAIEN                   0x00010000U        /*!<Audio Block enable         */
-#define  SAI_xCR1_DMAEN                   0x00020000U        /*!<DMA enable                 */
-#define  SAI_xCR1_NODIV                   0x00080000U        /*!<No Divider Configuration   */
-
-#define  SAI_xCR1_MCKDIV                  0x00F00000U        /*!<MCKDIV[3:0] (Master ClocK Divider)  */
-#define  SAI_xCR1_MCKDIV_0                0x00100000U        /*!<Bit 0  */
-#define  SAI_xCR1_MCKDIV_1                0x00200000U        /*!<Bit 1  */
-#define  SAI_xCR1_MCKDIV_2                0x00400000U        /*!<Bit 2  */
-#define  SAI_xCR1_MCKDIV_3                0x00800000U        /*!<Bit 3  */
-
-/*******************  Bit definition for SAI_xCR2 register  *******************/
-#define  SAI_xCR2_FTH                     0x00000007U        /*!<FTH[2:0](Fifo THreshold)  */
-#define  SAI_xCR2_FTH_0                   0x00000001U        /*!<Bit 0 */
-#define  SAI_xCR2_FTH_1                   0x00000002U        /*!<Bit 1 */
-#define  SAI_xCR2_FTH_2                   0x00000004U        /*!<Bit 2 */
-
-#define  SAI_xCR2_FFLUSH                  0x00000008U        /*!<Fifo FLUSH                       */
-#define  SAI_xCR2_TRIS                    0x00000010U        /*!<TRIState Management on data line */
-#define  SAI_xCR2_MUTE                    0x00000020U        /*!<Mute mode                        */
-#define  SAI_xCR2_MUTEVAL                 0x00000040U        /*!<Muate value                      */
-
-#define  SAI_xCR2_MUTECNT                  0x00001F80U       /*!<MUTECNT[5:0] (MUTE counter) */
-#define  SAI_xCR2_MUTECNT_0               0x00000080U        /*!<Bit 0 */
-#define  SAI_xCR2_MUTECNT_1               0x00000100U        /*!<Bit 1 */
-#define  SAI_xCR2_MUTECNT_2               0x00000200U        /*!<Bit 2 */
-#define  SAI_xCR2_MUTECNT_3               0x00000400U        /*!<Bit 3 */
-#define  SAI_xCR2_MUTECNT_4               0x00000800U        /*!<Bit 4 */
-#define  SAI_xCR2_MUTECNT_5               0x00001000U        /*!<Bit 5 */
-
-#define  SAI_xCR2_CPL                     0x00002000U        /*!< Complement Bit             */
-
-#define  SAI_xCR2_COMP                    0x0000C000U        /*!<COMP[1:0] (Companding mode) */
-#define  SAI_xCR2_COMP_0                  0x00004000U        /*!<Bit 0 */
-#define  SAI_xCR2_COMP_1                  0x00008000U        /*!<Bit 1 */
-
-/******************  Bit definition for SAI_xFRCR register  *******************/
-#define  SAI_xFRCR_FRL                    0x000000FFU        /*!<FRL[1:0](Frame length)  */
-#define  SAI_xFRCR_FRL_0                  0x00000001U        /*!<Bit 0 */
-#define  SAI_xFRCR_FRL_1                  0x00000002U        /*!<Bit 1 */
-#define  SAI_xFRCR_FRL_2                  0x00000004U        /*!<Bit 2 */
-#define  SAI_xFRCR_FRL_3                  0x00000008U        /*!<Bit 3 */
-#define  SAI_xFRCR_FRL_4                  0x00000010U        /*!<Bit 4 */
-#define  SAI_xFRCR_FRL_5                  0x00000020U        /*!<Bit 5 */
-#define  SAI_xFRCR_FRL_6                  0x00000040U        /*!<Bit 6 */
-#define  SAI_xFRCR_FRL_7                  0x00000080U        /*!<Bit 7 */
-
-#define  SAI_xFRCR_FSALL                  0x00007F00U        /*!<FRL[1:0] (Frame synchronization active level length)  */
-#define  SAI_xFRCR_FSALL_0                0x00000100U        /*!<Bit 0 */
-#define  SAI_xFRCR_FSALL_1                0x00000200U        /*!<Bit 1 */
-#define  SAI_xFRCR_FSALL_2                0x00000400U        /*!<Bit 2 */
-#define  SAI_xFRCR_FSALL_3                0x00000800U        /*!<Bit 3 */
-#define  SAI_xFRCR_FSALL_4                0x00001000U        /*!<Bit 4 */
-#define  SAI_xFRCR_FSALL_5                0x00002000U        /*!<Bit 5 */
-#define  SAI_xFRCR_FSALL_6                0x00004000U        /*!<Bit 6 */
-
-#define  SAI_xFRCR_FSDEF                  0x00010000U        /*!< Frame Synchronization Definition */
-#define  SAI_xFRCR_FSPOL                  0x00020000U        /*!<Frame Synchronization POLarity    */
-#define  SAI_xFRCR_FSOFF                  0x00040000U        /*!<Frame Synchronization OFFset      */
-/* Legacy defines */
-#define  SAI_xFRCR_FSPO                   SAI_xFRCR_FSPOL
-
-/******************  Bit definition for SAI_xSLOTR register  *******************/
-#define  SAI_xSLOTR_FBOFF                 0x0000001FU        /*!<FRL[4:0](First Bit Offset)  */
-#define  SAI_xSLOTR_FBOFF_0               0x00000001U        /*!<Bit 0 */
-#define  SAI_xSLOTR_FBOFF_1               0x00000002U        /*!<Bit 1 */
-#define  SAI_xSLOTR_FBOFF_2               0x00000004U        /*!<Bit 2 */
-#define  SAI_xSLOTR_FBOFF_3               0x00000008U        /*!<Bit 3 */
-#define  SAI_xSLOTR_FBOFF_4               0x00000010U        /*!<Bit 4 */
-
-#define  SAI_xSLOTR_SLOTSZ                0x000000C0U        /*!<SLOTSZ[1:0] (Slot size)  */
-#define  SAI_xSLOTR_SLOTSZ_0              0x00000040U        /*!<Bit 0 */
-#define  SAI_xSLOTR_SLOTSZ_1              0x00000080U        /*!<Bit 1 */
-
-#define  SAI_xSLOTR_NBSLOT                0x00000F00U        /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
-#define  SAI_xSLOTR_NBSLOT_0              0x00000100U        /*!<Bit 0 */
-#define  SAI_xSLOTR_NBSLOT_1              0x00000200U        /*!<Bit 1 */
-#define  SAI_xSLOTR_NBSLOT_2              0x00000400U        /*!<Bit 2 */
-#define  SAI_xSLOTR_NBSLOT_3              0x00000800U        /*!<Bit 3 */
-
-#define  SAI_xSLOTR_SLOTEN                0xFFFF0000U        /*!<SLOTEN[15:0] (Slot Enable)  */
-
-/*******************  Bit definition for SAI_xIMR register  *******************/
-#define  SAI_xIMR_OVRUDRIE                0x00000001U        /*!<Overrun underrun interrupt enable                              */
-#define  SAI_xIMR_MUTEDETIE               0x00000002U        /*!<Mute detection interrupt enable                                */
-#define  SAI_xIMR_WCKCFGIE                0x00000004U        /*!<Wrong Clock Configuration interrupt enable                     */
-#define  SAI_xIMR_FREQIE                  0x00000008U        /*!<FIFO request interrupt enable                                  */
-#define  SAI_xIMR_CNRDYIE                 0x00000010U        /*!<Codec not ready interrupt enable                               */
-#define  SAI_xIMR_AFSDETIE                0x00000020U        /*!<Anticipated frame synchronization detection interrupt enable   */
-#define  SAI_xIMR_LFSDETIE                0x00000040U        /*!<Late frame synchronization detection interrupt enable          */
-
-/********************  Bit definition for SAI_xSR register  *******************/
-#define  SAI_xSR_OVRUDR                   0x00000001U         /*!<Overrun underrun                               */
-#define  SAI_xSR_MUTEDET                  0x00000002U         /*!<Mute detection                                 */
-#define  SAI_xSR_WCKCFG                   0x00000004U         /*!<Wrong Clock Configuration                      */
-#define  SAI_xSR_FREQ                     0x00000008U         /*!<FIFO request                                   */
-#define  SAI_xSR_CNRDY                    0x00000010U         /*!<Codec not ready                                */
-#define  SAI_xSR_AFSDET                   0x00000020U         /*!<Anticipated frame synchronization detection    */
-#define  SAI_xSR_LFSDET                   0x00000040U         /*!<Late frame synchronization detection           */
-
-#define  SAI_xSR_FLVL                     0x00070000U         /*!<FLVL[2:0] (FIFO Level Threshold)               */
-#define  SAI_xSR_FLVL_0                   0x00010000U         /*!<Bit 0 */
-#define  SAI_xSR_FLVL_1                   0x00020000U         /*!<Bit 1 */
-#define  SAI_xSR_FLVL_2                   0x00040000U         /*!<Bit 2 */
-
-/******************  Bit definition for SAI_xCLRFR register  ******************/
-#define  SAI_xCLRFR_COVRUDR               0x00000001U        /*!<Clear Overrun underrun                               */
-#define  SAI_xCLRFR_CMUTEDET              0x00000002U        /*!<Clear Mute detection                                 */
-#define  SAI_xCLRFR_CWCKCFG               0x00000004U        /*!<Clear Wrong Clock Configuration                      */
-#define  SAI_xCLRFR_CFREQ                 0x00000008U        /*!<Clear FIFO request                                   */
-#define  SAI_xCLRFR_CCNRDY                0x00000010U        /*!<Clear Codec not ready                                */
-#define  SAI_xCLRFR_CAFSDET               0x00000020U        /*!<Clear Anticipated frame synchronization detection    */
-#define  SAI_xCLRFR_CLFSDET               0x00000040U        /*!<Clear Late frame synchronization detection           */
-
-/******************  Bit definition for SAI_xDR register  ******************/
-#define  SAI_xDR_DATA                     0xFFFFFFFFU        
-
-/******************************************************************************/
-/*                                                                            */
-/*                              SPDIF-RX Interface                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for SPDIFRX_CR register  *******************/
-#define  SPDIFRX_CR_SPDIFEN                  0x00000003U        /*!<Peripheral Block Enable                      */
-#define  SPDIFRX_CR_RXDMAEN                  0x00000004U        /*!<Receiver DMA Enable for data flow            */
-#define  SPDIFRX_CR_RXSTEO                   0x00000008U        /*!<Stereo Mode                                  */
-#define  SPDIFRX_CR_DRFMT                    0x00000030U        /*!<RX Data format                               */
-#define  SPDIFRX_CR_PMSK                     0x00000040U        /*!<Mask Parity error bit                        */
-#define  SPDIFRX_CR_VMSK                     0x00000080U        /*!<Mask of Validity bit                         */
-#define  SPDIFRX_CR_CUMSK                    0x00000100U        /*!<Mask of channel status and user bits         */
-#define  SPDIFRX_CR_PTMSK                    0x00000200U        /*!<Mask of Preamble Type bits                   */
-#define  SPDIFRX_CR_CBDMAEN                  0x00000400U        /*!<Control Buffer DMA ENable for control flow   */
-#define  SPDIFRX_CR_CHSEL                    0x00000800U        /*!<Channel Selection                            */
-#define  SPDIFRX_CR_NBTR                     0x00003000U        /*!<Maximum allowed re-tries during synchronization phase */
-#define  SPDIFRX_CR_WFA                      0x00004000U        /*!<Wait For Activity     */
-#define  SPDIFRX_CR_INSEL                    0x00070000U        /*!<SPDIFRX input selection */
-
-/*******************  Bit definition for SPDIFRX_IMR register  *******************/
-#define  SPDIFRX_IMR_RXNEIE                   0x00000001U        /*!<RXNE interrupt enable                              */
-#define  SPDIFRX_IMR_CSRNEIE                  0x00000002U        /*!<Control Buffer Ready Interrupt Enable              */
-#define  SPDIFRX_IMR_PERRIE                   0x00000004U        /*!<Parity error interrupt enable                      */
-#define  SPDIFRX_IMR_OVRIE                    0x00000008U        /*!<Overrun error Interrupt Enable                     */
-#define  SPDIFRX_IMR_SBLKIE                   0x00000010U        /*!<Synchronization Block Detected Interrupt Enable    */
-#define  SPDIFRX_IMR_SYNCDIE                  0x00000020U        /*!<Synchronization Done                               */
-#define  SPDIFRX_IMR_IFEIE                    0x00000040U        /*!<Serial Interface Error Interrupt Enable            */
-
-/*******************  Bit definition for SPDIFRX_SR register  *******************/
-#define  SPDIFRX_SR_RXNE                   0x00000001U       /*!<Read data register not empty                          */
-#define  SPDIFRX_SR_CSRNE                  0x00000002U       /*!<The Control Buffer register is not empty              */
-#define  SPDIFRX_SR_PERR                   0x00000004U       /*!<Parity error                                          */
-#define  SPDIFRX_SR_OVR                    0x00000008U       /*!<Overrun error                                         */
-#define  SPDIFRX_SR_SBD                    0x00000010U       /*!<Synchronization Block Detected                        */
-#define  SPDIFRX_SR_SYNCD                  0x00000020U       /*!<Synchronization Done                                  */
-#define  SPDIFRX_SR_FERR                   0x00000040U       /*!<Framing error                                         */
-#define  SPDIFRX_SR_SERR                   0x00000080U       /*!<Synchronization error                                 */
-#define  SPDIFRX_SR_TERR                   0x00000100U       /*!<Time-out error                                        */
-#define  SPDIFRX_SR_WIDTH5                 0x7FFF0000U       /*!<Duration of 5 symbols counted with SPDIFRX_clk          */
-
-/*******************  Bit definition for SPDIFRX_IFCR register  *******************/
-#define  SPDIFRX_IFCR_PERRCF               0x00000004U       /*!<Clears the Parity error flag                         */
-#define  SPDIFRX_IFCR_OVRCF                0x00000008U       /*!<Clears the Overrun error flag                        */
-#define  SPDIFRX_IFCR_SBDCF                0x00000010U       /*!<Clears the Synchronization Block Detected flag       */
-#define  SPDIFRX_IFCR_SYNCDCF              0x00000020U       /*!<Clears the Synchronization Done flag                 */
-
-/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/
-#define  SPDIFRX_DR0_DR                    0x00FFFFFFU        /*!<Data value            */
-#define  SPDIFRX_DR0_PE                    0x01000000U        /*!<Parity Error bit      */
-#define  SPDIFRX_DR0_V                     0x02000000U        /*!<Validity bit          */
-#define  SPDIFRX_DR0_U                     0x04000000U        /*!<User bit              */
-#define  SPDIFRX_DR0_C                     0x08000000U        /*!<Channel Status bit    */
-#define  SPDIFRX_DR0_PT                    0x30000000U        /*!<Preamble Type         */
-
-/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/
-#define  SPDIFRX_DR1_DR                    0xFFFFFF00U        /*!<Data value            */
-#define  SPDIFRX_DR1_PT                    0x00000030U        /*!<Preamble Type         */
-#define  SPDIFRX_DR1_C                     0x00000008U        /*!<Channel Status bit    */
-#define  SPDIFRX_DR1_U                     0x00000004U        /*!<User bit              */
-#define  SPDIFRX_DR1_V                     0x00000002U        /*!<Validity bit          */
-#define  SPDIFRX_DR1_PE                    0x00000001U        /*!<Parity Error bit      */
-
-/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/
-#define  SPDIFRX_DR1_DRNL1                 0xFFFF0000U        /*!<Data value Channel B      */
-#define  SPDIFRX_DR1_DRNL2                 0x0000FFFFU        /*!<Data value Channel A      */
-
-/*******************  Bit definition for SPDIFRX_CSR register   *******************/
-#define  SPDIFRX_CSR_USR                     0x0000FFFFU        /*!<User data information           */
-#define  SPDIFRX_CSR_CS                      0x00FF0000U        /*!<Channel A status information    */
-#define  SPDIFRX_CSR_SOB                     0x01000000U        /*!<Start Of Block                  */
-
-/*******************  Bit definition for SPDIFRX_DIR register    *******************/
-#define  SPDIFRX_DIR_THI                 0x000013FFU        /*!<Threshold LOW      */
-#define  SPDIFRX_DIR_TLO                 0x1FFF0000U        /*!<Threshold HIGH     */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          SD host Interface                                 */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SDIO_POWER register  ******************/
-#define  SDIO_POWER_PWRCTRL                  0x03U               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDIO_POWER_PWRCTRL_0                0x01U               /*!<Bit 0 */
-#define  SDIO_POWER_PWRCTRL_1                0x02U               /*!<Bit 1 */
-
-/******************  Bit definition for SDIO_CLKCR register  ******************/
-#define  SDIO_CLKCR_CLKDIV                   0x00FFU            /*!<Clock divide factor             */
-#define  SDIO_CLKCR_CLKEN                    0x0100U            /*!<Clock enable bit                */
-#define  SDIO_CLKCR_PWRSAV                   0x0200U            /*!<Power saving configuration bit  */
-#define  SDIO_CLKCR_BYPASS                   0x0400U            /*!<Clock divider bypass enable bit */
-
-#define  SDIO_CLKCR_WIDBUS                   0x1800U            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDIO_CLKCR_WIDBUS_0                 0x0800U            /*!<Bit 0 */
-#define  SDIO_CLKCR_WIDBUS_1                 0x1000U            /*!<Bit 1 */
-
-#define  SDIO_CLKCR_NEGEDGE                  0x2000U            /*!<SDIO_CK dephasing selection bit */
-#define  SDIO_CLKCR_HWFC_EN                  0x4000U            /*!<HW Flow Control enable          */
-
-/*******************  Bit definition for SDIO_ARG register  *******************/
-#define  SDIO_ARG_CMDARG                     0xFFFFFFFFU            /*!<Command argument */
-
-/*******************  Bit definition for SDIO_CMD register  *******************/
-#define  SDIO_CMD_CMDINDEX                   0x003FU            /*!<Command Index                               */
-
-#define  SDIO_CMD_WAITRESP                   0x00C0U            /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDIO_CMD_WAITRESP_0                 0x0040U            /*!< Bit 0 */
-#define  SDIO_CMD_WAITRESP_1                 0x0080U            /*!< Bit 1 */
-
-#define  SDIO_CMD_WAITINT                    0x0100U            /*!<CPSM Waits for Interrupt Request                               */
-#define  SDIO_CMD_WAITPEND                   0x0200U            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDIO_CMD_CPSMEN                     0x0400U            /*!<Command path state machine (CPSM) Enable bit                   */
-#define  SDIO_CMD_SDIOSUSPEND                0x0800U            /*!<SD I/O suspend command                                         */
-
-/*****************  Bit definition for SDIO_RESPCMD register  *****************/
-#define  SDIO_RESPCMD_RESPCMD                0x3FU               /*!<Response command index */
-
-/******************  Bit definition for SDIO_RESP0 register  ******************/
-#define  SDIO_RESP0_CARDSTATUS0              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP1 register  ******************/
-#define  SDIO_RESP1_CARDSTATUS1              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP2 register  ******************/
-#define  SDIO_RESP2_CARDSTATUS2              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP3 register  ******************/
-#define  SDIO_RESP3_CARDSTATUS3              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP4 register  ******************/
-#define  SDIO_RESP4_CARDSTATUS4              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_DTIMER register  *****************/
-#define  SDIO_DTIMER_DATATIME                0xFFFFFFFFU        /*!<Data timeout period. */
-
-/******************  Bit definition for SDIO_DLEN register  *******************/
-#define  SDIO_DLEN_DATALENGTH                0x01FFFFFFU        /*!<Data length value    */
-
-/******************  Bit definition for SDIO_DCTRL register  ******************/
-#define  SDIO_DCTRL_DTEN                     0x0001U            /*!<Data transfer enabled bit         */
-#define  SDIO_DCTRL_DTDIR                    0x0002U            /*!<Data transfer direction selection */
-#define  SDIO_DCTRL_DTMODE                   0x0004U            /*!<Data transfer mode selection      */
-#define  SDIO_DCTRL_DMAEN                    0x0008U            /*!<DMA enabled bit                   */
-
-#define  SDIO_DCTRL_DBLOCKSIZE               0x00F0U            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDIO_DCTRL_DBLOCKSIZE_0             0x0010U            /*!<Bit 0 */
-#define  SDIO_DCTRL_DBLOCKSIZE_1             0x0020U            /*!<Bit 1 */
-#define  SDIO_DCTRL_DBLOCKSIZE_2             0x0040U            /*!<Bit 2 */
-#define  SDIO_DCTRL_DBLOCKSIZE_3             0x0080U            /*!<Bit 3 */
-
-#define  SDIO_DCTRL_RWSTART                  0x0100U            /*!<Read wait start         */
-#define  SDIO_DCTRL_RWSTOP                   0x0200U            /*!<Read wait stop          */
-#define  SDIO_DCTRL_RWMOD                    0x0400U            /*!<Read wait mode          */
-#define  SDIO_DCTRL_SDIOEN                   0x0800U            /*!<SD I/O enable functions */
-
-/******************  Bit definition for SDIO_DCOUNT register  *****************/
-#define  SDIO_DCOUNT_DATACOUNT               0x01FFFFFFU        /*!<Data count value */
-
-/******************  Bit definition for SDIO_STA register  ********************/
-#define  SDIO_STA_CCRCFAIL                   0x00000001U        /*!<Command response received (CRC check failed)  */
-#define  SDIO_STA_DCRCFAIL                   0x00000002U        /*!<Data block sent/received (CRC check failed)   */
-#define  SDIO_STA_CTIMEOUT                   0x00000004U        /*!<Command response timeout                      */
-#define  SDIO_STA_DTIMEOUT                   0x00000008U        /*!<Data timeout                                  */
-#define  SDIO_STA_TXUNDERR                   0x00000010U        /*!<Transmit FIFO underrun error                  */
-#define  SDIO_STA_RXOVERR                    0x00000020U        /*!<Received FIFO overrun error                   */
-#define  SDIO_STA_CMDREND                    0x00000040U        /*!<Command response received (CRC check passed)  */
-#define  SDIO_STA_CMDSENT                    0x00000080U        /*!<Command sent (no response required)           */
-#define  SDIO_STA_DATAEND                    0x00000100U        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
-#define  SDIO_STA_DBCKEND                    0x00000400U        /*!<Data block sent/received (CRC check passed)   */
-#define  SDIO_STA_CMDACT                     0x00000800U        /*!<Command transfer in progress                  */
-#define  SDIO_STA_TXACT                      0x00001000U        /*!<Data transmit in progress                     */
-#define  SDIO_STA_RXACT                      0x00002000U        /*!<Data receive in progress                      */
-#define  SDIO_STA_TXFIFOHE                   0x00004000U        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDIO_STA_RXFIFOHF                   0x00008000U        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDIO_STA_TXFIFOF                    0x00010000U        /*!<Transmit FIFO full                            */
-#define  SDIO_STA_RXFIFOF                    0x00020000U        /*!<Receive FIFO full                             */
-#define  SDIO_STA_TXFIFOE                    0x00040000U        /*!<Transmit FIFO empty                           */
-#define  SDIO_STA_RXFIFOE                    0x00080000U        /*!<Receive FIFO empty                            */
-#define  SDIO_STA_TXDAVL                     0x00100000U        /*!<Data available in transmit FIFO               */
-#define  SDIO_STA_RXDAVL                     0x00200000U        /*!<Data available in receive FIFO                */
-#define  SDIO_STA_SDIOIT                     0x00400000U        /*!<SDIO interrupt received                       */
-
-/*******************  Bit definition for SDIO_ICR register  *******************/
-#define  SDIO_ICR_CCRCFAILC                  0x00000001U        /*!<CCRCFAIL flag clear bit */
-#define  SDIO_ICR_DCRCFAILC                  0x00000002U        /*!<DCRCFAIL flag clear bit */
-#define  SDIO_ICR_CTIMEOUTC                  0x00000004U        /*!<CTIMEOUT flag clear bit */
-#define  SDIO_ICR_DTIMEOUTC                  0x00000008U        /*!<DTIMEOUT flag clear bit */
-#define  SDIO_ICR_TXUNDERRC                  0x00000010U        /*!<TXUNDERR flag clear bit */
-#define  SDIO_ICR_RXOVERRC                   0x00000020U        /*!<RXOVERR flag clear bit  */
-#define  SDIO_ICR_CMDRENDC                   0x00000040U        /*!<CMDREND flag clear bit  */
-#define  SDIO_ICR_CMDSENTC                   0x00000080U        /*!<CMDSENT flag clear bit  */
-#define  SDIO_ICR_DATAENDC                   0x00000100U        /*!<DATAEND flag clear bit  */
-#define  SDIO_ICR_DBCKENDC                   0x00000400U        /*!<DBCKEND flag clear bit  */
-#define  SDIO_ICR_SDIOITC                    0x00400000U        /*!<SDIOIT flag clear bit   */
-
-/******************  Bit definition for SDIO_MASK register  *******************/
-#define  SDIO_MASK_CCRCFAILIE                0x00000001U        /*!<Command CRC Fail Interrupt Enable          */
-#define  SDIO_MASK_DCRCFAILIE                0x00000002U        /*!<Data CRC Fail Interrupt Enable             */
-#define  SDIO_MASK_CTIMEOUTIE                0x00000004U        /*!<Command TimeOut Interrupt Enable           */
-#define  SDIO_MASK_DTIMEOUTIE                0x00000008U        /*!<Data TimeOut Interrupt Enable              */
-#define  SDIO_MASK_TXUNDERRIE                0x00000010U        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
-#define  SDIO_MASK_RXOVERRIE                 0x00000020U        /*!<Rx FIFO OverRun Error Interrupt Enable     */
-#define  SDIO_MASK_CMDRENDIE                 0x00000040U        /*!<Command Response Received Interrupt Enable */
-#define  SDIO_MASK_CMDSENTIE                 0x00000080U        /*!<Command Sent Interrupt Enable              */
-#define  SDIO_MASK_DATAENDIE                 0x00000100U        /*!<Data End Interrupt Enable                  */
-#define  SDIO_MASK_DBCKENDIE                 0x00000400U        /*!<Data Block End Interrupt Enable            */
-#define  SDIO_MASK_CMDACTIE                  0x00000800U        /*!<CCommand Acting Interrupt Enable           */
-#define  SDIO_MASK_TXACTIE                   0x00001000U        /*!<Data Transmit Acting Interrupt Enable      */
-#define  SDIO_MASK_RXACTIE                   0x00002000U        /*!<Data receive acting interrupt enabled      */
-#define  SDIO_MASK_TXFIFOHEIE                0x00004000U        /*!<Tx FIFO Half Empty interrupt Enable        */
-#define  SDIO_MASK_RXFIFOHFIE                0x00008000U        /*!<Rx FIFO Half Full interrupt Enable         */
-#define  SDIO_MASK_TXFIFOFIE                 0x00010000U        /*!<Tx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_RXFIFOFIE                 0x00020000U        /*!<Rx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_TXFIFOEIE                 0x00040000U        /*!<Tx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_RXFIFOEIE                 0x00080000U        /*!<Rx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_TXDAVLIE                  0x00100000U        /*!<Data available in Tx FIFO interrupt Enable */
-#define  SDIO_MASK_RXDAVLIE                  0x00200000U        /*!<Data available in Rx FIFO interrupt Enable */
-#define  SDIO_MASK_SDIOITIE                  0x00400000U        /*!<SDIO Mode Interrupt Received interrupt Enable */
-
-/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
-#define  SDIO_FIFOCNT_FIFOCOUNT              0x00FFFFFFU        /*!<Remaining number of words to be written to or read from the FIFO */
-
-/******************  Bit definition for SDIO_FIFO register  *******************/
-#define  SDIO_FIFO_FIFODATA                  0xFFFFFFFFU        /*!<Receive and transmit FIFO data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        0x00000001U            /*!<Clock Phase      */
-#define  SPI_CR1_CPOL                        0x00000002U            /*!<Clock Polarity   */
-#define  SPI_CR1_MSTR                        0x00000004U            /*!<Master Selection */
-
-#define  SPI_CR1_BR                          0x00000038U            /*!<BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        0x00000008U            /*!<Bit 0 */
-#define  SPI_CR1_BR_1                        0x00000010U            /*!<Bit 1 */
-#define  SPI_CR1_BR_2                        0x00000020U            /*!<Bit 2 */
-
-#define  SPI_CR1_SPE                         0x00000040U            /*!<SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    0x00000080U            /*!<Frame Format                        */
-#define  SPI_CR1_SSI                         0x00000100U            /*!<Internal slave select               */
-#define  SPI_CR1_SSM                         0x00000200U            /*!<Software slave management           */
-#define  SPI_CR1_RXONLY                      0x00000400U            /*!<Receive only                        */
-#define  SPI_CR1_DFF                         0x00000800U            /*!<Data Frame Format                   */
-#define  SPI_CR1_CRCNEXT                     0x00001000U            /*!<Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       0x00002000U            /*!<Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      0x00004000U            /*!<Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    0x00008000U            /*!<Bidirectional data mode enable      */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     0x00000001U               /*!<Rx Buffer DMA Enable                 */
-#define  SPI_CR2_TXDMAEN                     0x00000002U               /*!<Tx Buffer DMA Enable                 */
-#define  SPI_CR2_SSOE                        0x00000004U               /*!<SS Output Enable                     */
-#define  SPI_CR2_FRF                         0x00000010U               /*!<Frame Format                         */
-#define  SPI_CR2_ERRIE                       0x00000020U               /*!<Error Interrupt Enable               */
-#define  SPI_CR2_RXNEIE                      0x00000040U               /*!<RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       0x00000080U               /*!<Tx buffer Empty Interrupt Enable     */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         0x00000001U               /*!<Receive buffer Not Empty */
-#define  SPI_SR_TXE                          0x00000002U               /*!<Transmit buffer Empty    */
-#define  SPI_SR_CHSIDE                       0x00000004U               /*!<Channel side             */
-#define  SPI_SR_UDR                          0x00000008U               /*!<Underrun flag            */
-#define  SPI_SR_CRCERR                       0x00000010U               /*!<CRC Error flag           */
-#define  SPI_SR_MODF                         0x00000020U               /*!<Mode fault               */
-#define  SPI_SR_OVR                          0x00000040U               /*!<Overrun flag             */
-#define  SPI_SR_BSY                          0x00000080U               /*!<Busy flag                */
-#define  SPI_SR_FRE                          0x00000100U               /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           0x0000FFFFU            /*!<Data Register           */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   0x0000FFFFU            /*!<CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    0x0000FFFFU            /*!<Rx CRC Register         */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    0x0000FFFFU            /*!<Tx CRC Register         */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   0x00000001U            /*!<Channel length (number of bits per audio channel) */
-
-#define  SPI_I2SCFGR_DATLEN                  0x00000006U            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define  SPI_I2SCFGR_DATLEN_0                0x00000002U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                0x00000004U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_CKPOL                   0x00000008U            /*!<steady state clock polarity               */
-
-#define  SPI_I2SCFGR_I2SSTD                  0x00000030U            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U            /*!<PCM frame synchronization                 */
-
-#define  SPI_I2SCFGR_I2SCFG                  0x00000300U            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_I2SE                    0x00000400U            /*!<I2S Enable         */
-#define  SPI_I2SCFGR_I2SMOD                  0x00000800U            /*!<I2S mode selection */
-#define  SPI_I2SCFGR_ASTRTEN                 0x00001000U            /*!<Asynchronous start enable */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    0x000000FFU            /*!<I2S Linear prescaler         */
-#define  SPI_I2SPR_ODD                       0x00000100U            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     0x00000200U            /*!<Master Clock Output Enable   */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 SYSCFG                                     */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
-#define SYSCFG_MEMRMP_MEM_MODE          0x00000007U /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        0x00000001U
-#define SYSCFG_MEMRMP_MEM_MODE_1        0x00000002U
-#define SYSCFG_MEMRMP_MEM_MODE_2        0x00000004U
-
-#define SYSCFG_MEMRMP_UFB_MODE          0x00000100U /*!< User Flash Bank mode    */
-#define SYSCFG_SWP_FMC                  0x00000C00U /*!< FMC memory mapping swap */
-
-/******************  Bit definition for SYSCFG_PMC register  ******************/
-#define SYSCFG_PMC_ADCxDC2              0x00070000U /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC1DC2              0x00010000U /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC2DC2              0x00020000U /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC3DC2              0x00040000U /*!< Refer to AN4073 on how to use this bit  */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
-/** 
-  * @brief   EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         0x0003U /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         0x0004U /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         0x0005U /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         0x0006U /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PI         0x0008U /*!<PI[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PJ         0x0009U /*!<PJ[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PK         0x000AU /*!<PK[0] pin */
-
-/** 
-  * @brief   EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         0x0030U /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         0x0040U /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         0x0050U /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         0x0060U /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PI         0x0080U /*!<PI[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PJ         0x0090U /*!<PJ[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PK         0x00A0U /*!<PK[1] pin */
-
-
-/** 
-  * @brief   EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         0x0300U /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         0x0400U /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         0x0500U /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         0x0600U /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PI         0x0800U /*!<PI[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PJ         0x0900U /*!<PJ[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PK         0x0A00U /*!<PK[2] pin */
-
-
-/** 
-  * @brief   EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         0x3000U /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         0x4000U /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         0x5000U /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         0x6000U /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PI         0x8000U /*!<PI[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PJ         0x9000U /*!<PJ[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PK         0xA000U /*!<PK[3] pin */
-
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
-/** 
-  * @brief   EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         0x0003U /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         0x0004U /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         0x0005U /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         0x0006U /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PI         0x0008U /*!<PI[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PJ         0x0009U /*!<PJ[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PK         0x000AU /*!<PK[4] pin */
-
-/** 
-  * @brief   EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         0x0030U /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         0x0040U /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         0x0050U /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         0x0060U /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PI         0x0080U /*!<PI[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PJ         0x0090U /*!<PJ[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PK         0x00A0U /*!<PK[5] pin */
-
-/** 
-  * @brief   EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         0x0300U /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         0x0400U /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         0x0500U /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         0x0600U /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PI         0x0800U /*!<PI[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PJ         0x0900U /*!<PJ[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PK         0x0A00U /*!<PK[6] pin */
-
-
-/** 
-  * @brief   EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         0x3000U /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         0x4000U /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         0x5000U /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         0x6000U /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PI         0x8000U /*!<PI[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PJ         0x9000U /*!<PJ[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PK         0xA000U /*!<PK[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
-           
-/** 
-  * @brief   EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         0x0003U /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         0x0004U /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         0x0005U /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         0x0006U /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PI         0x0008U /*!<PI[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PJ         0x0009U /*!<PJ[8] pin */
-
-/** 
-  * @brief   EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         0x0030U /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         0x0040U /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         0x0050U /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         0x0060U /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PI         0x0080U /*!<PI[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PJ         0x0090U /*!<PJ[9] pin */
-
-
-/** 
-  * @brief   EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        0x0300U /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        0x0400U /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        0x0500U /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        0x0600U /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PI        0x0800U /*!<PI[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PJ        0x0900U /*!<PJ[10] pin */
-
-
-/** 
-  * @brief   EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        0x3000U /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        0x4000U /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        0x5000U /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        0x6000U /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PI        0x8000U /*!<PI[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PJ        0x9000U /*!<PJ[11] pin */
-
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
-/** 
-  * @brief   EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        0x0003U /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        0x0004U /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        0x0005U /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        0x0006U /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PI        0x0008U /*!<PI[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PJ        0x0009U /*!<PJ[12] pin */
-
-
-/** 
-  * @brief   EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        0x0030U /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        0x0040U /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        0x0050U /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        0x0060U /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PI        0x0008U /*!<PI[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PJ        0x0009U /*!<PJ[13] pin */
-
-
-/** 
-  * @brief   EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        0x0300U /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        0x0400U /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        0x0500U /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        0x0600U /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PI        0x0800U /*!<PI[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PJ        0x0900U /*!<PJ[14] pin */
-
-
-/** 
-  * @brief   EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        0x3000U /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        0x4000U /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        0x5000U /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        0x6000U /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PI        0x8000U /*!<PI[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PJ        0x9000U /*!<PJ[15] pin */
-
-/******************  Bit definition for SYSCFG_CMPCR register  ****************/  
-#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell ready flag */
-#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell power-down */
-
-/******************  Bit definition for SYSCFG_CFGR register  ****************/  
-#define SYSCFG_CFGR_FMPI2C1_SCL         0x00000001U /*!<FM+ drive capability for FMPI2C1_SCL pin */
-#define SYSCFG_CFGR_FMPI2C1_SDA         0x00000002U /*!<FM+ drive capability for FMPI2C1_SDA pin */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    TIM                                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
-#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
-#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
-#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
-#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
-
-#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
-
-#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
-
-#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        0x0001U            /*!<Capture/Compare Preloaded Control        */
-#define  TIM_CR2_CCUS                        0x0004U            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        0x0008U            /*!<Capture/Compare DMA Selection            */
-
-#define  TIM_CR2_MMS                         0x0070U            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
-#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
-#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
-#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        0x0007U            /*!<SMS[2:0] bits (Slave mode selection)    */
-#define  TIM_SMCR_SMS_0                      0x0001U            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      0x0002U            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      0x0004U            /*!<Bit 2 */
-
-#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
-#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
-
-#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
-
-#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
-
-#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
-#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
-#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
-#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
-#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
-#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
-#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
-#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
-#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
-#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
-#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
-#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
-#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
-#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
-#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
-#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
-#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
-#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
-#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          0x01U               /*!<Update Generation                         */
-#define  TIM_EGR_CC1G                        0x02U               /*!<Capture/Compare 1 Generation              */
-#define  TIM_EGR_CC2G                        0x04U               /*!<Capture/Compare 2 Generation              */
-#define  TIM_EGR_CC3G                        0x08U               /*!<Capture/Compare 3 Generation              */
-#define  TIM_EGR_CC4G                        0x10U               /*!<Capture/Compare 4 Generation              */
-#define  TIM_EGR_COMG                        0x20U               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          0x40U               /*!<Trigger Generation                        */
-#define  TIM_EGR_BG                          0x80U               /*!<Break Generation                          */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      0x0003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    0x0001U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    0x0002U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC1FE                     0x0004U            /*!<Output Compare 1 Fast enable                 */
-#define  TIM_CCMR1_OC1PE                     0x0008U            /*!<Output Compare 1 Preload enable              */
-
-#define  TIM_CCMR1_OC1M                      0x0070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define  TIM_CCMR1_OC1M_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    0x0040U            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC1CE                     0x0080U            /*!<Output Compare 1Clear Enable                 */
-
-#define  TIM_CCMR1_CC2S                      0x0300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    0x0100U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    0x0200U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC2FE                     0x0400U            /*!<Output Compare 2 Fast enable                 */
-#define  TIM_CCMR1_OC2PE                     0x0800U            /*!<Output Compare 2 Preload enable              */
-
-#define  TIM_CCMR1_OC2M                      0x7000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define  TIM_CCMR1_OC2M_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    0x4000U            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC2CE                     0x8000U            /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      0x0003U            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define  TIM_CCMR2_CC3S_0                    0x0001U            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    0x0002U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC3FE                     0x0004U            /*!<Output Compare 3 Fast enable           */
-#define  TIM_CCMR2_OC3PE                     0x0008U            /*!<Output Compare 3 Preload enable        */
-
-#define  TIM_CCMR2_OC3M                      0x0070U            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    0x0040U            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC3CE                     0x0080U            /*!<Output Compare 3 Clear Enable */
-
-#define  TIM_CCMR2_CC4S                      0x0300U            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    0x0100U            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    0x0200U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC4FE                     0x0400U            /*!<Output Compare 4 Fast enable    */
-#define  TIM_CCMR2_OC4PE                     0x0800U            /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR2_OC4M                      0x7000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    0x4000U            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       0x0001U            /*!<Capture/Compare 1 output enable                 */
-#define  TIM_CCER_CC1P                       0x0002U            /*!<Capture/Compare 1 output Polarity               */
-#define  TIM_CCER_CC1NE                      0x0004U            /*!<Capture/Compare 1 Complementary output enable   */
-#define  TIM_CCER_CC1NP                      0x0008U            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       0x0010U            /*!<Capture/Compare 2 output enable                 */
-#define  TIM_CCER_CC2P                       0x0020U            /*!<Capture/Compare 2 output Polarity               */
-#define  TIM_CCER_CC2NE                      0x0040U            /*!<Capture/Compare 2 Complementary output enable   */
-#define  TIM_CCER_CC2NP                      0x0080U            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       0x0100U            /*!<Capture/Compare 3 output enable                 */
-#define  TIM_CCER_CC3P                       0x0200U            /*!<Capture/Compare 3 output Polarity               */
-#define  TIM_CCER_CC3NE                      0x0400U            /*!<Capture/Compare 3 Complementary output enable   */
-#define  TIM_CCER_CC3NP                      0x0800U            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       0x1000U            /*!<Capture/Compare 4 output enable                 */
-#define  TIM_CCER_CC4P                       0x2000U            /*!<Capture/Compare 4 output Polarity               */
-#define  TIM_CCER_CC4NP                      0x8000U            /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         0xFFU               /*!<Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
-
-/*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        0x00FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      0x0001U            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      0x0002U            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      0x0004U            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      0x0008U            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      0x0010U            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      0x0020U            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      0x0040U            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      0x0080U            /*!<Bit 7 */
-
-#define  TIM_BDTR_LOCK                       0x0300U            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     0x0100U            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     0x0200U            /*!<Bit 1 */
-
-#define  TIM_BDTR_OSSI                       0x0400U            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       0x0800U            /*!<Off-State Selection for Run mode  */
-#define  TIM_BDTR_BKE                        0x1000U            /*!<Break enable                      */
-#define  TIM_BDTR_BKP                        0x2000U            /*!<Break Polarity                    */
-#define  TIM_BDTR_AOE                        0x4000U            /*!<Automatic Output enable           */
-#define  TIM_BDTR_MOE                        0x8000U            /*!<Main Output enable                */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
-
-#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
-#define TIM_OR_ITR1_RMP                      0x0C00U            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
-#define TIM_OR_ITR1_RMP_0                    0x0400U            /*!<Bit 0 */
-#define TIM_OR_ITR1_RMP_1                    0x0800U            /*!<Bit 1 */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*         Universal Synchronous Asynchronous Receiver Transmitter            */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         0x0001U            /*!<Parity Error                 */
-#define  USART_SR_FE                         0x0002U            /*!<Framing Error                */
-#define  USART_SR_NE                         0x0004U            /*!<Noise Error Flag             */
-#define  USART_SR_ORE                        0x0008U            /*!<OverRun Error                */
-#define  USART_SR_IDLE                       0x0010U            /*!<IDLE line detected           */
-#define  USART_SR_RXNE                       0x0020U            /*!<Read Data Register Not Empty */
-#define  USART_SR_TC                         0x0040U            /*!<Transmission Complete        */
-#define  USART_SR_TXE                        0x0080U            /*!<Transmit Data Register Empty */
-#define  USART_SR_LBD                        0x0100U            /*!<LIN Break Detection Flag     */
-#define  USART_SR_CTS                        0x0200U            /*!<CTS Flag                     */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         0x01FFU            /*!<Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_Fraction              0x000FU            /*!<Fraction of USARTDIV */
-#define  USART_BRR_DIV_Mantissa              0xFFF0U            /*!<Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       0x0001U            /*!<Send Break                             */
-#define  USART_CR1_RWU                       0x0002U            /*!<Receiver wakeup                        */
-#define  USART_CR1_RE                        0x0004U            /*!<Receiver Enable                        */
-#define  USART_CR1_TE                        0x0008U            /*!<Transmitter Enable                     */
-#define  USART_CR1_IDLEIE                    0x0010U            /*!<IDLE Interrupt Enable                  */
-#define  USART_CR1_RXNEIE                    0x0020U            /*!<RXNE Interrupt Enable                  */
-#define  USART_CR1_TCIE                      0x0040U            /*!<Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     0x0080U            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PEIE                      0x0100U            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PS                        0x0200U            /*!<Parity Selection                       */
-#define  USART_CR1_PCE                       0x0400U            /*!<Parity Control Enable                  */
-#define  USART_CR1_WAKE                      0x0800U            /*!<Wakeup method                          */
-#define  USART_CR1_M                         0x1000U            /*!<Word length                            */
-#define  USART_CR1_UE                        0x2000U            /*!<USART Enable                           */
-#define  USART_CR1_OVER8                     0x8000U            /*!<USART Oversampling by 8 enable         */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       0x000FU            /*!<Address of the USART node            */
-#define  USART_CR2_LBDL                      0x0020U            /*!<LIN Break Detection Length           */
-#define  USART_CR2_LBDIE                     0x0040U            /*!<LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      0x0100U            /*!<Last Bit Clock pulse                 */
-#define  USART_CR2_CPHA                      0x0200U            /*!<Clock Phase                          */
-#define  USART_CR2_CPOL                      0x0400U            /*!<Clock Polarity                       */
-#define  USART_CR2_CLKEN                     0x0800U            /*!<Clock Enable                         */
-
-#define  USART_CR2_STOP                      0x3000U            /*!<STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    0x1000U            /*!<Bit 0 */
-#define  USART_CR2_STOP_1                    0x2000U            /*!<Bit 1 */
-
-#define  USART_CR2_LINEN                     0x4000U            /*!<LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       0x0001U            /*!<Error Interrupt Enable      */
-#define  USART_CR3_IREN                      0x0002U            /*!<IrDA mode Enable            */
-#define  USART_CR3_IRLP                      0x0004U            /*!<IrDA Low-Power              */
-#define  USART_CR3_HDSEL                     0x0008U            /*!<Half-Duplex Selection       */
-#define  USART_CR3_NACK                      0x0010U            /*!<Smartcard NACK enable       */
-#define  USART_CR3_SCEN                      0x0020U            /*!<Smartcard mode enable       */
-#define  USART_CR3_DMAR                      0x0040U            /*!<DMA Enable Receiver         */
-#define  USART_CR3_DMAT                      0x0080U            /*!<DMA Enable Transmitter      */
-#define  USART_CR3_RTSE                      0x0100U            /*!<RTS Enable                  */
-#define  USART_CR3_CTSE                      0x0200U            /*!<CTS Enable                  */
-#define  USART_CR3_CTSIE                     0x0400U            /*!<CTS Interrupt Enable        */
-#define  USART_CR3_ONEBIT                    0x0800U            /*!<USART One bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      0x00FFU            /*!<PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    0x0001U            /*!<Bit 0 */
-#define  USART_GTPR_PSC_1                    0x0002U            /*!<Bit 1 */
-#define  USART_GTPR_PSC_2                    0x0004U            /*!<Bit 2 */
-#define  USART_GTPR_PSC_3                    0x0008U            /*!<Bit 3 */
-#define  USART_GTPR_PSC_4                    0x0010U            /*!<Bit 4 */
-#define  USART_GTPR_PSC_5                    0x0020U            /*!<Bit 5 */
-#define  USART_GTPR_PSC_6                    0x0040U            /*!<Bit 6 */
-#define  USART_GTPR_PSC_7                    0x0080U            /*!<Bit 7 */
-
-#define  USART_GTPR_GT                       0xFF00U            /*!<Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Window WATCHDOG                                 */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           0x7FU               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T_0                         0x01U               /*!<Bit 0 */
-#define  WWDG_CR_T_1                         0x02U               /*!<Bit 1 */
-#define  WWDG_CR_T_2                         0x04U               /*!<Bit 2 */
-#define  WWDG_CR_T_3                         0x08U               /*!<Bit 3 */
-#define  WWDG_CR_T_4                         0x10U               /*!<Bit 4 */
-#define  WWDG_CR_T_5                         0x20U               /*!<Bit 5 */
-#define  WWDG_CR_T_6                         0x40U               /*!<Bit 6 */
-/* Legacy defines */
-#define  WWDG_CR_T0                          WWDG_CR_T_0
-#define  WWDG_CR_T1                          WWDG_CR_T_1
-#define  WWDG_CR_T2                          WWDG_CR_T_2
-#define  WWDG_CR_T3                          WWDG_CR_T_3
-#define  WWDG_CR_T4                          WWDG_CR_T_4
-#define  WWDG_CR_T5                          WWDG_CR_T_5
-#define  WWDG_CR_T6                          WWDG_CR_T_6
-
-#define  WWDG_CR_WDGA                        0x80U               /*!<Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          0x007FU            /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W_0                        0x0001U            /*!<Bit 0 */
-#define  WWDG_CFR_W_1                        0x0002U            /*!<Bit 1 */
-#define  WWDG_CFR_W_2                        0x0004U            /*!<Bit 2 */
-#define  WWDG_CFR_W_3                        0x0008U            /*!<Bit 3 */
-#define  WWDG_CFR_W_4                        0x0010U            /*!<Bit 4 */
-#define  WWDG_CFR_W_5                        0x0020U            /*!<Bit 5 */
-#define  WWDG_CFR_W_6                        0x0040U            /*!<Bit 6 */
-/* Legacy defines */
-#define  WWDG_CFR_W0                         WWDG_CFR_W_0
-#define  WWDG_CFR_W1                         WWDG_CFR_W_1
-#define  WWDG_CFR_W2                         WWDG_CFR_W_2
-#define  WWDG_CFR_W3                         WWDG_CFR_W_3
-#define  WWDG_CFR_W4                         WWDG_CFR_W_4
-#define  WWDG_CFR_W5                         WWDG_CFR_W_5
-#define  WWDG_CFR_W6                         WWDG_CFR_W_6
-
-#define  WWDG_CFR_WDGTB                      0x0180U            /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB_0                    0x0080U            /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB_1                    0x0100U            /*!<Bit 1 */
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
-
-#define  WWDG_CFR_EWI                        0x0200U            /*!<Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        0x01U               /*!<Early Wakeup Interrupt Flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                DBG                                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
-#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
-
-/********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
-#define  DBGMCU_CR_DBG_STOP                  0x00000002U
-#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
-#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
-
-#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
-#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U/*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U/*!<Bit 1 */
-
-/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            0x00000001U
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            0x00000002U
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            0x00000004U
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            0x00000020U
-#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           0x00000040U
-#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           0x00000080U
-#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           0x00000100U
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
-#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
-/* Old IWDGSTOP bit definition, maintained for legacy purpose */
-#define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
-
-/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        0x00000001U
-#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        0x00000002U
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        0x00010000U
-#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       0x00020000U
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       0x00040000U
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                       USB_OTG                              */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for USB_OTG_GOTGCTL register  ********************/
-#define USB_OTG_GOTGCTL_SRQSCS                  0x00000001U         /*!< Session request success */
-#define USB_OTG_GOTGCTL_SRQ                     0x00000002U         /*!< Session request */
-#define USB_OTG_GOTGCTL_VBVALOEN                0x00000004U         /*!< VBUS valid override enable */
-#define USB_OTG_GOTGCTL_VBVALOVAL               0x00000008U         /*!< VBUS valid override value */
-#define USB_OTG_GOTGCTL_AVALOEN                 0x00000010U         /*!< A-peripheral session valid override enable */
-#define USB_OTG_GOTGCTL_AVALOVAL                0x00000020U         /*!< A-peripheral session valid override value */
-#define USB_OTG_GOTGCTL_BVALOEN                 0x00000040U         /*!< B-peripheral session valid override enable */
-#define USB_OTG_GOTGCTL_BVALOVAL                0x00000080U         /*!< B-peripheral session valid override value  */
-#define USB_OTG_GOTGCTL_HNGSCS                  0x00000100U         /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_HNPRQ                   0x00000200U         /*!< HNP request */
-#define USB_OTG_GOTGCTL_HSHNPEN                 0x00000400U         /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_DHNPEN                  0x00000800U         /*!< Device HNP enabled */
-#define USB_OTG_GOTGCTL_EHEN                    0x00001000U         /*!< Embedded host enable */
-#define USB_OTG_GOTGCTL_CIDSTS                  0x00010000U         /*!< Connector ID status */
-#define USB_OTG_GOTGCTL_DBCT                    0x00020000U         /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD                   0x00040000U         /*!< A-session valid  */
-#define USB_OTG_GOTGCTL_BSESVLD                 0x00080000U         /*!< B-session valid */
-#define USB_OTG_GOTGCTL_OTGVER                  0x00100000U         /*!< OTG version  */
-
-/********************  Bit definition for USB_OTG_HCFG register  ********************/
-
-#define USB_OTG_HCFG_FSLSPCS                 0x00000003U            /*!< FS/LS PHY clock select  */
-#define USB_OTG_HCFG_FSLSPCS_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCFG_FSLSPCS_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCFG_FSLSS                   0x00000004U            /*!< FS- and LS-only support */
-
-/********************  Bit definition for USB_OTG_DCFG register  ********************/
-
-#define USB_OTG_DCFG_DSPD                    0x00000003U            /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                  0x00000001U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DSPD_1                  0x00000002U            /*!<Bit 1 */
-#define USB_OTG_DCFG_NZLSOHSK                0x00000004U            /*!< Nonzero-length status OUT handshake */
-
-#define USB_OTG_DCFG_DAD                     0x000007F0U            /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                   0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DAD_1                   0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCFG_DAD_2                   0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCFG_DAD_3                   0x00000080U            /*!<Bit 3 */
-#define USB_OTG_DCFG_DAD_4                   0x00000100U            /*!<Bit 4 */
-#define USB_OTG_DCFG_DAD_5                   0x00000200U            /*!<Bit 5 */
-#define USB_OTG_DCFG_DAD_6                   0x00000400U            /*!<Bit 6 */
-
-#define USB_OTG_DCFG_PFIVL                   0x00001800U            /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PFIVL_1                 0x00001000U            /*!<Bit 1 */
-
-#define USB_OTG_DCFG_PERSCHIVL               0x03000000U            /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0             0x01000000U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PERSCHIVL_1             0x02000000U            /*!<Bit 1 */
-
-/********************  Bit definition for USB_OTG_PCGCR register  ********************/
-#define USB_OTG_PCGCR_STPPCLK                 0x00000001U            /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK                0x00000002U            /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP                 0x00000010U            /*!< PHY suspended */
-
-/********************  Bit definition for USB_OTG_GOTGINT register  ********************/
-#define USB_OTG_GOTGINT_SEDET                   0x00000004U            /*!< Session end detected                   */
-#define USB_OTG_GOTGINT_SRSSCHG                 0x00000100U            /*!< Session request success status change  */
-#define USB_OTG_GOTGINT_HNSSCHG                 0x00000200U            /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET                  0x00020000U            /*!< Host negotiation detected              */
-#define USB_OTG_GOTGINT_ADTOCHG                 0x00040000U            /*!< A-device timeout change                */
-#define USB_OTG_GOTGINT_DBCDNE                  0x00080000U            /*!< Debounce done                          */
-#define USB_OTG_GOTGINT_IDCHNG                  0x00100000U            /*!< Change in ID pin input value           */
-
-/********************  Bit definition for USB_OTG_DCTL register  ********************/
-#define USB_OTG_DCTL_RWUSIG                  0x00000001U            /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS                    0x00000002U            /*!< Soft disconnect         */
-#define USB_OTG_DCTL_GINSTS                  0x00000004U            /*!< Global IN NAK status    */
-#define USB_OTG_DCTL_GONSTS                  0x00000008U            /*!< Global OUT NAK status   */
-
-#define USB_OTG_DCTL_TCTL                    0x00000070U            /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                  0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCTL_TCTL_1                  0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCTL_TCTL_2                  0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCTL_SGINAK                  0x00000080U            /*!< Set global IN NAK         */
-#define USB_OTG_DCTL_CGINAK                  0x00000100U            /*!< Clear global IN NAK       */
-#define USB_OTG_DCTL_SGONAK                  0x00000200U            /*!< Set global OUT NAK        */
-#define USB_OTG_DCTL_CGONAK                  0x00000400U            /*!< Clear global OUT NAK      */
-#define USB_OTG_DCTL_POPRGDNE                0x00000800U            /*!< Power-on programming done */
-
-/********************  Bit definition for USB_OTG_HFIR register  ********************/
-#define USB_OTG_HFIR_FRIVL                   0x0000FFFFU            /*!< Frame interval */
-
-/********************  Bit definition for USB_OTG_HFNUM register  ********************/
-#define USB_OTG_HFNUM_FRNUM                   0x0000FFFFU            /*!< Frame number         */
-#define USB_OTG_HFNUM_FTREM                   0xFFFF0000U            /*!< Frame time remaining */
-
-/********************  Bit definition for USB_OTG_DSTS register  ********************/
-#define USB_OTG_DSTS_SUSPSTS                 0x00000001U            /*!< Suspend status   */
-
-#define USB_OTG_DSTS_ENUMSPD                 0x00000006U            /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_DSTS_ENUMSPD_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_DSTS_EERR                    0x00000008U            /*!< Erratic error     */
-#define USB_OTG_DSTS_FNSOF                   0x003FFF00U            /*!< Frame number of the received SOF */
-
-/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
-#define USB_OTG_GAHBCFG_GINT                    0x00000001U            /*!< Global interrupt mask */
-#define USB_OTG_GAHBCFG_HBSTLEN                 0x0000001EU            /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_GAHBCFG_HBSTLEN_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_GAHBCFG_HBSTLEN_2               0x00000008U            /*!<Bit 2 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3               0x00000010U            /*!<Bit 3 */
-#define USB_OTG_GAHBCFG_DMAEN                   0x00000020U            /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL                 0x00000080U            /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL                0x00000100U            /*!< Periodic TxFIFO empty level */
-
-/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
-
-#define USB_OTG_GUSBCFG_TOCAL                   0x00000007U            /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TOCAL_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TOCAL_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_PHYSEL                  0x00000040U            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP                  0x00000100U            /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP                  0x00000200U            /*!< HNP-capable */
-#define USB_OTG_GUSBCFG_TRDT                    0x00003C00U            /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                  0x00000400U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TRDT_1                  0x00000800U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TRDT_2                  0x00001000U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_TRDT_3                  0x00002000U            /*!<Bit 3 */
-#define USB_OTG_GUSBCFG_PHYLPCS                 0x00008000U            /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS                0x00020000U            /*!< ULPI FS/LS select               */
-#define USB_OTG_GUSBCFG_ULPIAR                  0x00040000U            /*!< ULPI Auto-resume                */
-#define USB_OTG_GUSBCFG_ULPICSM                 0x00080000U            /*!< ULPI Clock SuspendM             */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD              0x00100000U            /*!< ULPI External VBUS Drive        */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI              0x00200000U            /*!< ULPI external VBUS indicator    */
-#define USB_OTG_GUSBCFG_TSDPS                   0x00400000U            /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI                    0x00800000U            /*!< Indicator complement            */
-#define USB_OTG_GUSBCFG_PTCI                    0x01000000U            /*!< Indicator pass through          */
-#define USB_OTG_GUSBCFG_ULPIIPD                 0x02000000U            /*!< ULPI interface protect disable  */
-#define USB_OTG_GUSBCFG_FHMOD                   0x20000000U            /*!< Forced host mode                */
-#define USB_OTG_GUSBCFG_FDMOD                   0x40000000U            /*!< Forced peripheral mode          */
-#define USB_OTG_GUSBCFG_CTXPKT                  0x80000000U            /*!< Corrupt Tx packet               */
-
-/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
-#define USB_OTG_GRSTCTL_CSRST                   0x00000001U            /*!< Core soft reset          */
-#define USB_OTG_GRSTCTL_HSRST                   0x00000002U            /*!< HCLK soft reset          */
-#define USB_OTG_GRSTCTL_FCRST                   0x00000004U            /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH                 0x00000010U            /*!< RxFIFO flush             */
-#define USB_OTG_GRSTCTL_TXFFLSH                 0x00000020U            /*!< TxFIFO flush             */
-#define USB_OTG_GRSTCTL_TXFNUM                  0x000007C0U            /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                0x00000040U            /*!<Bit 0 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                0x00000080U            /*!<Bit 1 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                0x00000100U            /*!<Bit 2 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                0x00000200U            /*!<Bit 3 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                0x00000400U            /*!<Bit 4 */
-#define USB_OTG_GRSTCTL_DMAREQ                  0x40000000U            /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL                  0x80000000U            /*!< AHB master idle */
-
-/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
-#define USB_OTG_DIEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask                 */
-#define USB_OTG_DIEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask                  */
-#define USB_OTG_DIEPMSK_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask          */
-#define USB_OTG_DIEPMSK_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask           */
-#define USB_OTG_DIEPMSK_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask                    */
-#define USB_OTG_DIEPMSK_TXFURM                  0x00000100U            /*!< FIFO underrun mask                                */
-#define USB_OTG_DIEPMSK_BIM                     0x00000200U            /*!< BNA interrupt mask                                */
-
-/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
-#define USB_OTG_HPTXSTS_PTXFSAVL                0x0000FFFFU            /*!< Periodic transmit data FIFO space available     */
-#define USB_OTG_HPTXSTS_PTXQSAV                 0x00FF0000U            /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0               0x00010000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1               0x00020000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2               0x00040000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3               0x00080000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4               0x00100000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5               0x00200000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6               0x00400000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7               0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_HPTXSTS_PTXQTOP                 0xFF000000U            /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0               0x01000000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1               0x02000000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2               0x04000000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3               0x08000000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4               0x10000000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5               0x20000000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6               0x40000000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7               0x80000000U            /*!<Bit 7 */
-
-/********************  Bit definition for USB_OTG_HAINT register  ********************/
-#define USB_OTG_HAINT_HAINT                   0x0000FFFFU            /*!< Channel interrupts */
-
-/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
-#define USB_OTG_DOEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask               */
-#define USB_OTG_DOEPMSK_STUPM                   0x00000008U            /*!< SETUP phase done mask                          */
-#define USB_OTG_DOEPMSK_OTEPDM                  0x00000010U            /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_OTEPSPRM                0x00000020U            /*!< Status Phase Received mask                     */
-#define USB_OTG_DOEPMSK_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received mask */
-#define USB_OTG_DOEPMSK_OPEM                    0x00000100U            /*!< OUT packet error mask                          */
-#define USB_OTG_DOEPMSK_BOIM                    0x00000200U            /*!< BNA interrupt mask                             */
-
-/********************  Bit definition for USB_OTG_GINTSTS register  ********************/
-#define USB_OTG_GINTSTS_CMOD                    0x00000001U            /*!< Current mode of operation                      */
-#define USB_OTG_GINTSTS_MMIS                    0x00000002U            /*!< Mode mismatch interrupt                        */
-#define USB_OTG_GINTSTS_OTGINT                  0x00000004U            /*!< OTG interrupt                                  */
-#define USB_OTG_GINTSTS_SOF                     0x00000008U            /*!< Start of frame                                 */
-#define USB_OTG_GINTSTS_RXFLVL                  0x00000010U            /*!< RxFIFO nonempty                                */
-#define USB_OTG_GINTSTS_NPTXFE                  0x00000020U            /*!< Nonperiodic TxFIFO empty                       */
-#define USB_OTG_GINTSTS_GINAKEFF                0x00000040U            /*!< Global IN nonperiodic NAK effective            */
-#define USB_OTG_GINTSTS_BOUTNAKEFF              0x00000080U            /*!< Global OUT NAK effective                       */
-#define USB_OTG_GINTSTS_ESUSP                   0x00000400U            /*!< Early suspend                                  */
-#define USB_OTG_GINTSTS_USBSUSP                 0x00000800U            /*!< USB suspend                                    */
-#define USB_OTG_GINTSTS_USBRST                  0x00001000U            /*!< USB reset                                      */
-#define USB_OTG_GINTSTS_ENUMDNE                 0x00002000U            /*!< Enumeration done                               */
-#define USB_OTG_GINTSTS_ISOODRP                 0x00004000U            /*!< Isochronous OUT packet dropped interrupt       */
-#define USB_OTG_GINTSTS_EOPF                    0x00008000U            /*!< End of periodic frame interrupt                */
-#define USB_OTG_GINTSTS_IEPINT                  0x00040000U            /*!< IN endpoint interrupt                          */
-#define USB_OTG_GINTSTS_OEPINT                  0x00080000U            /*!< OUT endpoint interrupt                         */
-#define USB_OTG_GINTSTS_IISOIXFR                0x00100000U            /*!< Incomplete isochronous IN transfer             */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       0x00200000U            /*!< Incomplete periodic transfer                   */
-#define USB_OTG_GINTSTS_DATAFSUSP               0x00400000U            /*!< Data fetch suspended                           */
-#define USB_OTG_GINTSTS_RSTDET                  0x00800000U            /*!< Reset detected interrupt                       */
-#define USB_OTG_GINTSTS_HPRTINT                 0x01000000U            /*!< Host port interrupt                            */
-#define USB_OTG_GINTSTS_HCINT                   0x02000000U            /*!< Host channels interrupt                        */
-#define USB_OTG_GINTSTS_PTXFE                   0x04000000U            /*!< Periodic TxFIFO empty                          */
-#define USB_OTG_GINTSTS_LPMINT                  0x08000000U            /*!< LPM interrupt                                  */
-#define USB_OTG_GINTSTS_CIDSCHG                 0x10000000U            /*!< Connector ID status change                     */
-#define USB_OTG_GINTSTS_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt                  */
-#define USB_OTG_GINTSTS_SRQINT                  0x40000000U            /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT                  0x80000000U            /*!< Resume/remote wakeup detected interrupt        */
-
-/********************  Bit definition for USB_OTG_GINTMSK register  ********************/
-#define USB_OTG_GINTMSK_MMISM                   0x00000002U            /*!< Mode mismatch interrupt mask                        */
-#define USB_OTG_GINTMSK_OTGINT                  0x00000004U            /*!< OTG interrupt mask                                  */
-#define USB_OTG_GINTMSK_SOFM                    0x00000008U            /*!< Start of frame mask                                 */
-#define USB_OTG_GINTMSK_RXFLVLM                 0x00000010U            /*!< Receive FIFO nonempty mask                          */
-#define USB_OTG_GINTMSK_NPTXFEM                 0x00000020U            /*!< Nonperiodic TxFIFO empty mask                       */
-#define USB_OTG_GINTMSK_GINAKEFFM               0x00000040U            /*!< Global nonperiodic IN NAK effective mask            */
-#define USB_OTG_GINTMSK_GONAKEFFM               0x00000080U            /*!< Global OUT NAK effective mask                       */
-#define USB_OTG_GINTMSK_ESUSPM                  0x00000400U            /*!< Early suspend mask                                  */
-#define USB_OTG_GINTMSK_USBSUSPM                0x00000800U            /*!< USB suspend mask                                    */
-#define USB_OTG_GINTMSK_USBRST                  0x00001000U            /*!< USB reset mask                                      */
-#define USB_OTG_GINTMSK_ENUMDNEM                0x00002000U            /*!< Enumeration done mask                               */
-#define USB_OTG_GINTMSK_ISOODRPM                0x00004000U            /*!< Isochronous OUT packet dropped interrupt mask       */
-#define USB_OTG_GINTMSK_EOPFM                   0x00008000U            /*!< End of periodic frame interrupt mask                */
-#define USB_OTG_GINTMSK_EPMISM                  0x00020000U            /*!< Endpoint mismatch interrupt mask                    */
-#define USB_OTG_GINTMSK_IEPINT                  0x00040000U            /*!< IN endpoints interrupt mask                         */
-#define USB_OTG_GINTMSK_OEPINT                  0x00080000U            /*!< OUT endpoints interrupt mask                        */
-#define USB_OTG_GINTMSK_IISOIXFRM               0x00100000U            /*!< Incomplete isochronous IN transfer mask             */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         0x00200000U            /*!< Incomplete periodic transfer mask                   */
-#define USB_OTG_GINTMSK_FSUSPM                  0x00400000U            /*!< Data fetch suspended mask                           */
-#define USB_OTG_GINTMSK_RSTDEM                  0x00800000U            /*!< Reset detected interrupt mask                      */
-#define USB_OTG_GINTMSK_PRTIM                   0x01000000U            /*!< Host port interrupt mask                            */
-#define USB_OTG_GINTMSK_HCIM                    0x02000000U            /*!< Host channels interrupt mask                        */
-#define USB_OTG_GINTMSK_PTXFEM                  0x04000000U            /*!< Periodic TxFIFO empty mask                          */
-#define USB_OTG_GINTMSK_LPMINTM                 0x08000000U            /*!< LPM interrupt Mask                                  */
-#define USB_OTG_GINTMSK_CIDSCHGM                0x10000000U            /*!< Connector ID status change mask                     */
-#define USB_OTG_GINTMSK_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt mask                  */
-#define USB_OTG_GINTMSK_SRQIM                   0x40000000U            /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM                    0x80000000U            /*!< Resume/remote wakeup detected interrupt mask        */
-
-/********************  Bit definition for USB_OTG_DAINT register  ********************/
-#define USB_OTG_DAINT_IEPINT                  0x0000FFFFU            /*!< IN endpoint interrupt bits  */
-#define USB_OTG_DAINT_OEPINT                  0xFFFF0000U            /*!< OUT endpoint interrupt bits */
-
-/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
-#define USB_OTG_HAINTMSK_HAINTM                  0x0000FFFFU            /*!< Channel interrupt mask */
-
-/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
-#define USB_OTG_GRXSTSP_EPNUM                    0x0000000FU            /*!< IN EP interrupt mask bits  */
-#define USB_OTG_GRXSTSP_BCNT                     0x00007FF0U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID                     0x00018000U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS                   0x001E0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
-#define USB_OTG_DAINTMSK_IEPM                    0x0000FFFFU            /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM                    0xFFFF0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for OTG register  ********************/
-
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition for OTG register  ********************/
-
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
-#define USB_OTG_GRXFSIZ_RXFD            0x0000FFFFU            /*!< RxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
-#define USB_OTG_DVBUSDIS_VBUSDT         0x0000FFFFU            /*!< Device VBUS discharge time */
-
-/********************  Bit definition for OTG register  ********************/
-#define USB_OTG_NPTXFSA                 0x0000FFFFU            /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD                  0xFFFF0000U            /*!< Nonperiodic TxFIFO depth               */
-#define USB_OTG_TX0FSA                  0x0000FFFFU            /*!< Endpoint 0 transmit RAM start address  */
-#define USB_OTG_TX0FD                   0xFFFF0000U            /*!< Endpoint 0 TxFIFO depth                */
-
-/********************  Bit definition for USB_OTG_DVBUSPULSE register  ********************/
-#define USB_OTG_DVBUSPULSE_DVBUSP                  0x00000FFFU            /*!< Device VBUS pulsing time */
-
-/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
-#define USB_OTG_GNPTXSTS_NPTXFSAV                0x0000FFFFU            /*!< Nonperiodic TxFIFO space available */
-
-#define USB_OTG_GNPTXSTS_NPTQXSAV                0x00FF0000U            /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0              0x00010000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1              0x00020000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2              0x00040000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3              0x00080000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4              0x00100000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5              0x00200000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6              0x00400000U            /*!<Bit 6 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7              0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_GNPTXSTS_NPTXQTOP                0x7F000000U            /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0              0x01000000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1              0x02000000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2              0x04000000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3              0x08000000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4              0x10000000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5              0x20000000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6              0x40000000U            /*!<Bit 6 */
-
-/********************  Bit definition for USB_OTG_DTHRCTL register  ********************/
-#define USB_OTG_DTHRCTL_NONISOTHREN             0x00000001U            /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN                0x00000002U            /*!< ISO IN endpoint threshold enable */
-
-#define USB_OTG_DTHRCTL_TXTHRLEN                0x000007FCU            /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0              0x00000004U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1              0x00000008U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2              0x00000010U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3              0x00000020U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4              0x00000040U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5              0x00000080U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6              0x00000100U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7              0x00000200U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8              0x00000400U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_RXTHREN                 0x00010000U            /*!< Receive threshold enable */
-
-#define USB_OTG_DTHRCTL_RXTHRLEN                0x03FE0000U            /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0              0x00020000U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1              0x00040000U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2              0x00080000U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3              0x00100000U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4              0x00200000U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5              0x00400000U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6              0x00800000U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7              0x01000000U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8              0x02000000U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_ARPEN                   0x08000000U            /*!< Arbiter parking enable */
-
-/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM               0x0000FFFFU         /*!< IN EP Tx FIFO empty interrupt mask bits */
-
-/********************  Bit definition for USB_OTG_DEACHINT register  ********************/
-#define USB_OTG_DEACHINT_IEP1INT                 0x00000002U           /*!< IN endpoint 1interrupt bit   */
-#define USB_OTG_DEACHINT_OEP1INT                 0x00020000U           /*!< OUT endpoint 1 interrupt bit */
-
-/********************  Bit definition for USB_OTG_GCCFG register  ********************/
-#define USB_OTG_GCCFG_PWRDWN                 0x00010000U              /*!< Power down */
-#define USB_OTG_GCCFG_VBDEN                  0x00200000U              /*!< USB VBUS Detection Enable */
-
-/********************  Bit definition for USB_OTG_DEACHINTMSK register  ********************/
-#define USB_OTG_DEACHINTMSK_IEP1INTM          0x00000002U            /*!< IN Endpoint 1 interrupt mask bit  */
-#define USB_OTG_DEACHINTMSK_OEP1INTM          0x00020000U            /*!< OUT Endpoint 1 interrupt mask bit */
- 
-/********************  Bit definition for USB_OTG_CID register  ********************/
-#define USB_OTG_CID_PRODUCT_ID               0xFFFFFFFFU            /*!< Product ID field */
-
-/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/
-#define  USB_OTG_GLPMCFG_LPMEN               0x00000001U            /*!< LPM support enable                                     */
-#define  USB_OTG_GLPMCFG_LPMACK              0x00000002U            /*!< LPM Token acknowledge enable                           */
-#define  USB_OTG_GLPMCFG_BESL                0x0000003CU            /*!< BESL value received with last ACKed LPM Token          */
-#define  USB_OTG_GLPMCFG_REMWAKE             0x00000040U            /*!< bRemoteWake value received with last ACKed LPM Token   */
-#define  USB_OTG_GLPMCFG_L1SSEN              0x00000080U            /*!< L1 shallow sleep enable                                */
-#define  USB_OTG_GLPMCFG_BESLTHRS            0x00000F00U            /*!< BESL threshold                                         */
-#define  USB_OTG_GLPMCFG_L1DSEN              0x00001000U            /*!< L1 deep sleep enable                                   */
-#define  USB_OTG_GLPMCFG_LPMRSP              0x00006000U            /*!< LPM response                                           */
-#define  USB_OTG_GLPMCFG_SLPSTS              0x00008000U            /*!< Port sleep status                                      */
-#define  USB_OTG_GLPMCFG_L1RSMOK             0x00010000U            /*!< Sleep State Resume OK                                  */
-#define  USB_OTG_GLPMCFG_LPMCHIDX            0x001E0000U            /*!< LPM Channel Index                                      */
-#define  USB_OTG_GLPMCFG_LPMRCNT             0x00E00000U            /*!< LPM retry count                                        */
-#define  USB_OTG_GLPMCFG_SNDLPM              0x01000000U            /*!< Send LPM transaction                                   */
-#define  USB_OTG_GLPMCFG_LPMRCNTSTS          0x0E000000U            /*!< LPM retry count status                                 */
-#define  USB_OTG_GLPMCFG_ENBESL              0x10000000U            /*!< Enable best effort service latency                     */
-
-/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
-#define USB_OTG_DIEPEACHMSK1_XFRCM           0x00000001U            /*!< Transfer completed interrupt mask                 */
-#define USB_OTG_DIEPEACHMSK1_EPDM            0x00000002U            /*!< Endpoint disabled interrupt mask                  */
-#define USB_OTG_DIEPEACHMSK1_TOM             0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK       0x00000010U            /*!< IN token received when TxFIFO empty mask          */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM         0x00000020U            /*!< IN token received with EP mismatch mask           */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM         0x00000040U            /*!< IN endpoint NAK effective mask                    */
-#define USB_OTG_DIEPEACHMSK1_TXFURM          0x00000100U            /*!< FIFO underrun mask                                */
-#define USB_OTG_DIEPEACHMSK1_BIM             0x00000200U            /*!< BNA interrupt mask                                */
-#define USB_OTG_DIEPEACHMSK1_NAKM            0x00002000U            /*!< NAK interrupt mask                                */
-
-/********************  Bit definition for USB_OTG_HPRT register  ********************/
-#define USB_OTG_HPRT_PCSTS                   0x00000001U            /*!< Port connect status        */
-#define USB_OTG_HPRT_PCDET                   0x00000002U            /*!< Port connect detected      */
-#define USB_OTG_HPRT_PENA                    0x00000004U            /*!< Port enable                */
-#define USB_OTG_HPRT_PENCHNG                 0x00000008U            /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA                    0x00000010U            /*!< Port overcurrent active    */
-#define USB_OTG_HPRT_POCCHNG                 0x00000020U            /*!< Port overcurrent change    */
-#define USB_OTG_HPRT_PRES                    0x00000040U            /*!< Port resume                */
-#define USB_OTG_HPRT_PSUSP                   0x00000080U            /*!< Port suspend               */
-#define USB_OTG_HPRT_PRST                    0x00000100U            /*!< Port reset                 */
-
-#define USB_OTG_HPRT_PLSTS                   0x00000C00U            /*!< Port line status           */
-#define USB_OTG_HPRT_PLSTS_0                 0x00000400U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PLSTS_1                 0x00000800U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PPWR                    0x00001000U            /*!< Port power                 */
-
-#define USB_OTG_HPRT_PTCTL                   0x0001E000U            /*!< Port test control          */
-#define USB_OTG_HPRT_PTCTL_0                 0x00002000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PTCTL_1                 0x00004000U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PTCTL_2                 0x00008000U            /*!<Bit 2 */
-#define USB_OTG_HPRT_PTCTL_3                 0x00010000U            /*!<Bit 3 */
-
-#define USB_OTG_HPRT_PSPD                    0x00060000U            /*!< Port speed                 */
-#define USB_OTG_HPRT_PSPD_0                  0x00020000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PSPD_1                  0x00040000U            /*!<Bit 1 */
-
-/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
-#define USB_OTG_DOEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask         */
-#define USB_OTG_DOEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask          */
-#define USB_OTG_DOEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask                    */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask  */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask   */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask            */
-#define USB_OTG_DOEPEACHMSK1_TXFURM                  0x00000100U            /*!< OUT packet error mask                     */
-#define USB_OTG_DOEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask                        */
-#define USB_OTG_DOEPEACHMSK1_BERRM                   0x00001000U            /*!< Bubble error interrupt mask               */
-#define USB_OTG_DOEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask                        */
-#define USB_OTG_DOEPEACHMSK1_NYETM                   0x00004000U            /*!< NYET interrupt mask                       */
-
-/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
-#define USB_OTG_HPTXFSIZ_PTXSA                   0x0000FFFFU            /*!< Host periodic TxFIFO start address            */
-#define USB_OTG_HPTXFSIZ_PTXFD                   0xFFFF0000U            /*!< Host periodic TxFIFO depth                    */
-
-/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
-#define USB_OTG_DIEPCTL_MPSIZ                   0x000007FFU            /*!< Maximum packet size              */
-#define USB_OTG_DIEPCTL_USBAEP                  0x00008000U            /*!< USB active endpoint              */
-#define USB_OTG_DIEPCTL_EONUM_DPID              0x00010000U            /*!< Even/odd frame                   */
-#define USB_OTG_DIEPCTL_NAKSTS                  0x00020000U            /*!< NAK status                       */
-
-#define USB_OTG_DIEPCTL_EPTYP                   0x000C0000U            /*!< Endpoint type                    */
-#define USB_OTG_DIEPCTL_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_STALL                   0x00200000U            /*!< STALL handshake                  */
-
-#define USB_OTG_DIEPCTL_TXFNUM                  0x03C00000U            /*!< TxFIFO number                    */
-#define USB_OTG_DIEPCTL_TXFNUM_0                0x00400000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                0x00800000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                0x01000000U            /*!<Bit 2 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                0x02000000U            /*!<Bit 3 */
-#define USB_OTG_DIEPCTL_CNAK                    0x04000000U            /*!< Clear NAK                        */
-#define USB_OTG_DIEPCTL_SNAK                    0x08000000U            /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          0x10000000U            /*!< Set DATA0 PID                    */
-#define USB_OTG_DIEPCTL_SODDFRM                 0x20000000U            /*!< Set odd frame                    */
-#define USB_OTG_DIEPCTL_EPDIS                   0x40000000U            /*!< Endpoint disable                 */
-#define USB_OTG_DIEPCTL_EPENA                   0x80000000U            /*!< Endpoint enable                  */
-
-/********************  Bit definition for USB_OTG_HCCHAR register  ********************/
-#define USB_OTG_HCCHAR_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
-
-#define USB_OTG_HCCHAR_EPNUM                   0x00007800U            /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPNUM_1                 0x00001000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_EPNUM_2                 0x00002000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_EPNUM_3                 0x00004000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_EPDIR                   0x00008000U            /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV                   0x00020000U            /*!< Low-speed device */
-
-#define USB_OTG_HCCHAR_EPTYP                   0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_MC                      0x00300000U            /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                    0x00100000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_MC_1                    0x00200000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_DAD                     0x1FC00000U            /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                   0x00400000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_DAD_1                   0x00800000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_DAD_2                   0x01000000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_DAD_3                   0x02000000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_DAD_4                   0x04000000U            /*!<Bit 4 */
-#define USB_OTG_HCCHAR_DAD_5                   0x08000000U            /*!<Bit 5 */
-#define USB_OTG_HCCHAR_DAD_6                   0x10000000U            /*!<Bit 6 */
-#define USB_OTG_HCCHAR_ODDFRM                  0x20000000U            /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS                   0x40000000U            /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA                   0x80000000U            /*!< Channel enable */
-
-/********************  Bit definition for USB_OTG_HCSPLT register  ********************/
-
-#define USB_OTG_HCSPLT_PRTADDR                 0x0000007FU            /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_PRTADDR_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_PRTADDR_2               0x00000004U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_PRTADDR_3               0x00000008U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_PRTADDR_4               0x00000010U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_PRTADDR_5               0x00000020U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_PRTADDR_6               0x00000040U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_HUBADDR                 0x00003F80U            /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0               0x00000080U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_HUBADDR_1               0x00000100U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_HUBADDR_2               0x00000200U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_HUBADDR_3               0x00000400U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_HUBADDR_4               0x00000800U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_HUBADDR_5               0x00001000U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_HUBADDR_6               0x00002000U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_XACTPOS                 0x0000C000U            /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0               0x00004000U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_XACTPOS_1               0x00008000U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_COMPLSPLT               0x00010000U            /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN                 0x80000000U            /*!< Split enable */
-
-/********************  Bit definition for USB_OTG_HCINT register  ********************/
-#define USB_OTG_HCINT_XFRC                    0x00000001U            /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH                     0x00000002U            /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINT_STALL                   0x00000008U            /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK                     0x00000010U            /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK                     0x00000020U            /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET                    0x00000040U            /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR                   0x00000080U            /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR                   0x00000100U            /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR                   0x00000200U            /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR                   0x00000400U            /*!< Data toggle error */
-
-/********************  Bit definition for USB_OTG_DIEPINT register  ********************/
-#define USB_OTG_DIEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_TOC                     0x00000008U            /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE                  0x00000010U            /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNE                  0x00000040U            /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE                    0x00000080U            /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN              0x00000100U            /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA                     0x00000200U            /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS               0x00000800U            /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR                    0x00001000U            /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK                     0x00002000U            /*!< NAK interrupt */
-
-/********************  Bit definition for USB_OTG_HCINTMSK register  ********************/
-#define USB_OTG_HCINTMSK_XFRCM                   0x00000001U            /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM                    0x00000002U            /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM                  0x00000008U            /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM                    0x00000010U            /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM                    0x00000020U            /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET                    0x00000040U            /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM                  0x00000080U            /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM                  0x00000100U            /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM                  0x00000200U            /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM                  0x00000400U            /*!< Data toggle error mask */
-
-/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
-
-#define USB_OTG_DIEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT                  0x60000000U            /*!< Packet count */
-/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
-#define USB_OTG_HCTSIZ_XFRSIZ                    0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT                    0x1FF80000U            /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING                    0x80000000U            /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID                      0x60000000U            /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                    0x20000000U            /*!<Bit 0 */
-#define USB_OTG_HCTSIZ_DPID_1                    0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
-#define USB_OTG_DIEPDMA_DMAADDR                  0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition for USB_OTG_HCDMA register  ********************/
-#define USB_OTG_HCDMA_DMAADDR                    0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
-#define USB_OTG_DTXFSTS_INEPTFSAV                0x0000FFFFU            /*!< IN endpoint TxFIFO space available */
-
-/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
-#define USB_OTG_DIEPTXF_INEPTXSA                 0x0000FFFFU            /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD                 0xFFFF0000U            /*!< IN endpoint TxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
-
-#define USB_OTG_DOEPCTL_MPSIZ                     0x000007FFU            /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP                    0x00008000U            /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS                    0x00020000U            /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            0x10000000U            /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM                   0x20000000U            /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP                     0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                   0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DOEPCTL_EPTYP_1                   0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_SNPM                      0x00100000U            /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL                     0x00200000U            /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK                      0x04000000U            /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK                      0x08000000U            /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS                     0x40000000U            /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA                     0x80000000U            /*!< Endpoint enable */
-
-/********************  Bit definition for USB_OTG_DOEPINT register  ********************/
-#define USB_OTG_DOEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_STUP                    0x00000008U            /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS                 0x00000010U            /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_OTEPSPR                 0x00000020U            /*!< Status Phase Received For Control Write */
-#define USB_OTG_DOEPINT_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_NYET                    0x00004000U            /*!< NYET interrupt */
-
-/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
-
-#define USB_OTG_DOEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-
-#define USB_OTG_DOEPTSIZ_STUPCNT                 0x60000000U            /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0               0x20000000U            /*!<Bit 0 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1               0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition for PCGCCTL register  ********************/
-#define USB_OTG_PCGCCTL_STOPCLK                 0x00000001U            /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK                 0x00000002U            /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP                 0x00000010U            /*!<Bit 1 */
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
-                                       ((INSTANCE) == ADC2) || \
-                                       ((INSTANCE) == ADC3))
-
-/******************************* CAN Instances ********************************/
-#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
-                                       ((INSTANCE) == CAN2))
- 
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DAC Instances ********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/******************************* DCMI Instances *******************************/
-#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
-
-/******************************** DMA Instances *******************************/
-#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
-                                              ((INSTANCE) == DMA1_Stream1) || \
-                                              ((INSTANCE) == DMA1_Stream2) || \
-                                              ((INSTANCE) == DMA1_Stream3) || \
-                                              ((INSTANCE) == DMA1_Stream4) || \
-                                              ((INSTANCE) == DMA1_Stream5) || \
-                                              ((INSTANCE) == DMA1_Stream6) || \
-                                              ((INSTANCE) == DMA1_Stream7) || \
-                                              ((INSTANCE) == DMA2_Stream0) || \
-                                              ((INSTANCE) == DMA2_Stream1) || \
-                                              ((INSTANCE) == DMA2_Stream2) || \
-                                              ((INSTANCE) == DMA2_Stream3) || \
-                                              ((INSTANCE) == DMA2_Stream4) || \
-                                              ((INSTANCE) == DMA2_Stream5) || \
-                                              ((INSTANCE) == DMA2_Stream6) || \
-                                              ((INSTANCE) == DMA2_Stream7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOF) || \
-                                        ((INSTANCE) == GPIOG) || \
-                                        ((INSTANCE) == GPIOH))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2) || \
-                                       ((INSTANCE) == I2C3))
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI1) || \
-                                        ((INSTANCE) == SPI2) || \
-                                        ((INSTANCE) == SPI3))
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************* SAI Instances ********************************/
-#define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
-                                     ((PERIPH) == SAI1_Block_B) || \
-                                     ((PERIPH) == SAI2_Block_A) || \
-                                     ((PERIPH) == SAI2_Block_B))
-/* Legacy define */
-#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3) || \
-                                       ((INSTANCE) == SPI4))
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
-                                   ((INSTANCE) == TIM2)   || \
-                                   ((INSTANCE) == TIM3)   || \
-                                   ((INSTANCE) == TIM4)   || \
-                                   ((INSTANCE) == TIM5)   || \
-                                   ((INSTANCE) == TIM6)   || \
-                                   ((INSTANCE) == TIM7)   || \
-                                   ((INSTANCE) == TIM8)   || \
-                                   ((INSTANCE) == TIM9)   || \
-                                   ((INSTANCE) == TIM10)  || \
-                                   ((INSTANCE) == TIM11)  || \
-                                   ((INSTANCE) == TIM12)  || \
-                                   ((INSTANCE) == TIM13)  || \
-                                   ((INSTANCE) == TIM14))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
-                                         ((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM8)  || \
-                                         ((INSTANCE) == TIM9)  || \
-                                         ((INSTANCE) == TIM10) || \
-                                         ((INSTANCE) == TIM11) || \
-                                         ((INSTANCE) == TIM12) || \
-                                         ((INSTANCE) == TIM13) || \
-                                         ((INSTANCE) == TIM14))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM8) || \
-                                       ((INSTANCE) == TIM9) || \
-                                       ((INSTANCE) == TIM12))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8))
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM8))
-
-/******************** TIM Instances : Advanced-control timers *****************/
-#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                            ((INSTANCE) == TIM8))
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8))
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM6) || \
-                                       ((INSTANCE) == TIM7) || \
-                                       ((INSTANCE) == TIM8))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM8))
-
-/************ TIM Instances : DMA requests generation (COMDE) *****************/
-#define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM8)) 
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                             ((INSTANCE) == TIM2) || \
-                                             ((INSTANCE) == TIM3) || \
-                                             ((INSTANCE) == TIM4) || \
-                                             ((INSTANCE) == TIM5) || \
-                                             ((INSTANCE) == TIM8))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM6) || \
-                                          ((INSTANCE) == TIM7) || \
-                                          ((INSTANCE) == TIM8) || \
-                                          ((INSTANCE) == TIM9) || \
-                                          ((INSTANCE) == TIM12))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8) || \
-                                         ((INSTANCE) == TIM9) || \
-                                         ((INSTANCE) == TIM12))
-
-/********************** TIM Instances : 32 bit Counter ************************/
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
-                                              ((INSTANCE) == TIM5))
-
-/***************** TIM Instances : external trigger input availabe ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                        ((INSTANCE) == TIM2) || \
-                                        ((INSTANCE) == TIM3) || \
-                                        ((INSTANCE) == TIM4) || \
-                                        ((INSTANCE) == TIM5) || \
-                                        ((INSTANCE) == TIM8))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM11))
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM1) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM5) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM8) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM12) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM13) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM14) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-/************ TIM Instances : complementary output(s) available ***************/
-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
-   ((((INSTANCE) == TIM1) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3)))            \
-    ||                                          \
-    (((INSTANCE) == TIM8) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3))))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3) || \
-                                     ((INSTANCE) == USART6))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5)  || \
-                                    ((INSTANCE) == USART6))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3) || \
-                                           ((INSTANCE) == USART6))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3) || \
-                                         ((INSTANCE) == USART6))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5)  || \
-                                    ((INSTANCE) == USART6))
-                                    
-/*********************** PCD Instances ****************************************/
-#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
-                                        ((INSTANCE) == USB_OTG_HS))
-
-/*********************** HCD Instances ****************************************/
-#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
-                                       ((INSTANCE) == USB_OTG_HS))
-
-/****************************** SDIO Instances ********************************/
-#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/****************************** QSPI Instances ********************************/
-#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
-
-/******************************* CEC Instances ********************************/
-#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
-
-/***************************** FMPI2C Instances *******************************/
-#define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
-
-/******************************* SPDIFRX Instances ********************************/
-#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)
-
-/****************************** USB Exported Constants ************************/
-#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                8U
-#define USB_OTG_FS_MAX_IN_ENDPOINTS                    5U    /* Including EP0 */
-#define USB_OTG_FS_MAX_OUT_ENDPOINTS                   5U    /* Including EP0 */
-#define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */
-
-#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR                16U
-#define USB_OTG_HS_MAX_IN_ENDPOINTS                    8U    /* Including EP0 */
-#define USB_OTG_HS_MAX_OUT_ENDPOINTS                   8U    /* Including EP0 */
-#define USB_OTG_HS_TOTAL_FIFO_SIZE                     4096U /* in Bytes */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32F4xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */
-/*  product lines within the same STM32F4 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQHandler */
-#define QuadSPI_IRQHandler              QUADSPI_IRQHandler
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32F446xx_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/cmsis/stm32f469xx.h b/stmhal/cmsis/stm32f469xx.h
deleted file mode 100644
index d37f32a6af..0000000000
--- a/stmhal/cmsis/stm32f469xx.h
+++ /dev/null
@@ -1,10250 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f469xx.h
-  * @author  MCD Application Team
-  * @version V2.5.1
-  * @date    28-June-2016
-  * @brief   CMSIS STM32F469xx Device Peripheral Access Layer Header File.
-  *
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - peripherals registers declarations and bits definition
-  *           - Macros to access peripheral’s registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS_Device
-  * @{
-  */
-
-/** @addtogroup stm32f469xx
-  * @{
-  */
-    
-#ifndef __STM32F469xx_H
-#define __STM32F469xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-  
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-
-/**
-  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
-  */
-#define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */
-#define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */
-#define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1U       /*!< FPU present                                   */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32F4XX Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-typedef enum
-{
-/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
-  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
-/******  STM32 specific Interrupt Numbers **********************************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
-  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
-  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
-  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
-  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
-  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
-  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
-  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
-  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
-  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
-  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
-  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
-  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
-  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
-  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
-  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
-  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
-  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */    
-  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
-  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
-  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
-  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare global interrupt                             */
-  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
-  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
-  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
-  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
-  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
-  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
-  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
-  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
-  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
-  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
-  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
-  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
-  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
-  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
-  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
-  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
-  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
-  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
-  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
-  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
-  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
-  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
-  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
-  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
-  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
-  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
-  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
-  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
-  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
-  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
-  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
-  HASH_RNG_IRQn               = 80,     /*!< Hash and Rng global interrupt                                     */
-  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
-  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */
-  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */
-  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
-  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */
-  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */
-  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
-  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                              */
-  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                        */
-  DMA2D_IRQn                  = 90,     /*!< DMA2D global Interrupt                                            */
-  QUADSPI_IRQn                = 91,     /*!< QUADSPI global Interrupt                                          */
-  DSI_IRQn                    = 92      /*!< DSI global Interrupt                                              */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
-#include "system_stm32f4xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */      
-  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
-  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
-  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
-  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
-  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
-  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
-  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
-  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
-  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
-  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
-  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
-  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
-  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
-  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
-  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
-                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
-} ADC_Common_TypeDef;
-
-
-/** 
-  * @brief Controller Area Network TxMailBox 
-  */
-
-typedef struct
-{
-  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
-  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
-  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
-  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
-} CAN_TxMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FIFOMailBox 
-  */
-  
-typedef struct
-{
-  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
-  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
-  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
-  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
-} CAN_FIFOMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FilterRegister 
-  */
-  
-typedef struct
-{
-  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
-  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
-} CAN_FilterRegister_TypeDef;
-
-/** 
-  * @brief Controller Area Network 
-  */
-  
-typedef struct
-{
-  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
-  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
-  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
-  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
-  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
-  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
-  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
-  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
-  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
-  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
-  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
-  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
-  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
-  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
-  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
-  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
-  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
-  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
-  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
-  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
-  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */ 
-  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
-} CAN_TypeDef;
-
-/** 
-  * @brief CRC calculation unit 
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
-  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */
-  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
-  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
-  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
-  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
-  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
-  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
-  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
-  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
-  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
-  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
-  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
-  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
-  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
-  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
-  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
-  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
-  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
-  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DCMI
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
-  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
-  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
-  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
-  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
-  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
-  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
-  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
-  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
-  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
-  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
-} DCMI_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
-  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
-  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
-  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
-  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
-  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
-} DMA_Stream_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
-  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
-  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
-  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
-} DMA_TypeDef;
-
-/** 
-  * @brief DMA2D Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
-  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
-  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
-  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
-  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
-  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
-  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
-  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
-  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
-  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
-  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
-  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
-  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
-  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
-  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
-  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
-  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
-  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
-  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
-  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
-  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
-  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */
-  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */
-} DMA2D_TypeDef;
-
-/** 
-  * @brief DSI Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t VR;            /*!< DSI Host Version Register,                                 Address offset: 0x00      */
-  __IO uint32_t CR;            /*!< DSI Host Control Register,                                 Address offset: 0x04      */
-  __IO uint32_t CCR;           /*!< DSI HOST Clock Control Register,                           Address offset: 0x08      */
-  __IO uint32_t LVCIDR;        /*!< DSI Host LTDC VCID Register,                               Address offset: 0x0C      */
-  __IO uint32_t LCOLCR;        /*!< DSI Host LTDC Color Coding Register,                       Address offset: 0x10      */ 
-  __IO uint32_t LPCR;          /*!< DSI Host LTDC Polarity Configuration Register,             Address offset: 0x14      */
-  __IO uint32_t LPMCR;         /*!< DSI Host Low-Power Mode Configuration Register,            Address offset: 0x18      */
-  uint32_t      RESERVED0[4];  /*!< Reserved, 0x1C - 0x2B                                                                */
-  __IO uint32_t PCR;           /*!< DSI Host Protocol Configuration Register,                  Address offset: 0x2C      */ 
-  __IO uint32_t GVCIDR;        /*!< DSI Host Generic VCID Register,                            Address offset: 0x30      */
-  __IO uint32_t MCR;           /*!< DSI Host Mode Configuration Register,                      Address offset: 0x34      */
-  __IO uint32_t VMCR;          /*!< DSI Host Video Mode Configuration Register,                Address offset: 0x38      */
-  __IO uint32_t VPCR;          /*!< DSI Host Video Packet Configuration Register,              Address offset: 0x3C      */
-  __IO uint32_t VCCR;          /*!< DSI Host Video Chunks Configuration Register,              Address offset: 0x40      */
-  __IO uint32_t VNPCR;         /*!< DSI Host Video Null Packet Configuration Register,         Address offset: 0x44      */
-  __IO uint32_t VHSACR;        /*!< DSI Host Video HSA Configuration Register,                 Address offset: 0x48      */
-  __IO uint32_t VHBPCR;        /*!< DSI Host Video HBP Configuration Register,                 Address offset: 0x4C      */
-  __IO uint32_t VLCR;          /*!< DSI Host Video Line Configuration Register,                Address offset: 0x50      */
-  __IO uint32_t VVSACR;        /*!< DSI Host Video VSA Configuration Register,                 Address offset: 0x54      */
-  __IO uint32_t VVBPCR;        /*!< DSI Host Video VBP Configuration Register,                 Address offset: 0x58      */
-  __IO uint32_t VVFPCR;        /*!< DSI Host Video VFP Configuration Register,                 Address offset: 0x5C      */
-  __IO uint32_t VVACR;         /*!< DSI Host Video VA Configuration Register,                  Address offset: 0x60      */
-  __IO uint32_t LCCR;          /*!< DSI Host LTDC Command Configuration Register,              Address offset: 0x64      */ 
-  __IO uint32_t CMCR;          /*!< DSI Host Command Mode Configuration Register,              Address offset: 0x68      */
-  __IO uint32_t GHCR;          /*!< DSI Host Generic Header Configuration Register,            Address offset: 0x6C      */
-  __IO uint32_t GPDR;          /*!< DSI Host Generic Payload Data Register,                    Address offset: 0x70      */
-  __IO uint32_t GPSR;          /*!< DSI Host Generic Packet Status Register,                   Address offset: 0x74      */
-  __IO uint32_t TCCR[6];       /*!< DSI Host Timeout Counter Configuration Register,           Address offset: 0x78-0x8F */
-  __IO uint32_t TDCR;          /*!< DSI Host 3D Configuration Register,                        Address offset: 0x90      */ 
-  __IO uint32_t CLCR;          /*!< DSI Host Clock Lane Configuration Register,                Address offset: 0x94      */
-  __IO uint32_t CLTCR;         /*!< DSI Host Clock Lane Timer Configuration Register,          Address offset: 0x98      */
-  __IO uint32_t DLTCR;         /*!< DSI Host Data Lane Timer Configuration Register,           Address offset: 0x9C      */
-  __IO uint32_t PCTLR;         /*!< DSI Host PHY Control Register,                             Address offset: 0xA0      */ 
-  __IO uint32_t PCONFR;        /*!< DSI Host PHY Configuration Register,                       Address offset: 0xA4      */ 
-  __IO uint32_t PUCR;          /*!< DSI Host PHY ULPS Control Register,                        Address offset: 0xA8      */
-  __IO uint32_t PTTCR;         /*!< DSI Host PHY TX Triggers Configuration Register,           Address offset: 0xAC      */
-  __IO uint32_t PSR;           /*!< DSI Host PHY Status Register,                              Address offset: 0xB0      */
-  uint32_t      RESERVED1[2];  /*!< Reserved, 0xB4 - 0xBB                                                                */
-  __IO uint32_t ISR[2];        /*!< DSI Host Interrupt & Status Register,                      Address offset: 0xBC-0xC3 */
-  __IO uint32_t IER[2];        /*!< DSI Host Interrupt Enable Register,                        Address offset: 0xC4-0xCB */
-  uint32_t      RESERVED2[3];  /*!< Reserved, 0xD0 - 0xD7                                                                */
-  __IO uint32_t FIR[2];        /*!< DSI Host Force Interrupt Register,                         Address offset: 0xD8-0xDF */
-  uint32_t      RESERVED3[8];  /*!< Reserved, 0xE0 - 0xFF                                                                */
-  __IO uint32_t VSCR;          /*!< DSI Host Video Shadow Control Register,                    Address offset: 0x100     */
-  uint32_t      RESERVED4[2];  /*!< Reserved, 0x104 - 0x10B                                                              */
-  __IO uint32_t LCVCIDR;       /*!< DSI Host LTDC Current VCID Register,                       Address offset: 0x10C     */
-  __IO uint32_t LCCCR;         /*!< DSI Host LTDC Current Color Coding Register,               Address offset: 0x110     */
-  uint32_t      RESERVED5;     /*!< Reserved, 0x114                                                                      */
-  __IO uint32_t LPMCCR;        /*!< DSI Host Low-power Mode Current Configuration Register,    Address offset: 0x118     */
-  uint32_t      RESERVED6[7];  /*!< Reserved, 0x11C - 0x137                                                              */
-  __IO uint32_t VMCCR;         /*!< DSI Host Video Mode Current Configuration Register,        Address offset: 0x138     */
-  __IO uint32_t VPCCR;         /*!< DSI Host Video Packet Current Configuration Register,      Address offset: 0x13C     */
-  __IO uint32_t VCCCR;         /*!< DSI Host Video Chuncks Current Configuration Register,     Address offset: 0x140     */
-  __IO uint32_t VNPCCR;        /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144     */
-  __IO uint32_t VHSACCR;       /*!< DSI Host Video HSA Current Configuration Register,         Address offset: 0x148     */
-  __IO uint32_t VHBPCCR;       /*!< DSI Host Video HBP Current Configuration Register,         Address offset: 0x14C     */
-  __IO uint32_t VLCCR;         /*!< DSI Host Video Line Current Configuration Register,        Address offset: 0x150     */
-  __IO uint32_t VVSACCR;       /*!< DSI Host Video VSA Current Configuration Register,         Address offset: 0x154     */ 
-  __IO uint32_t VVBPCCR;       /*!< DSI Host Video VBP Current Configuration Register,         Address offset: 0x158     */
-  __IO uint32_t VVFPCCR;       /*!< DSI Host Video VFP Current Configuration Register,         Address offset: 0x15C     */
-  __IO uint32_t VVACCR;        /*!< DSI Host Video VA Current Configuration Register,          Address offset: 0x160     */
-  uint32_t      RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F                                                              */
-  __IO uint32_t TDCCR;         /*!< DSI Host 3D Current Configuration Register,                Address offset: 0x190     */ 
-  uint32_t      RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF                                                               */
-  __IO uint32_t WCFGR;          /*!< DSI Wrapper Configuration Register,                       Address offset: 0x400       */
-  __IO uint32_t WCR;            /*!< DSI Wrapper Control Register,                             Address offset: 0x404       */
-  __IO uint32_t WIER;           /*!< DSI Wrapper Interrupt Enable Register,                    Address offset: 0x408       */
-  __IO uint32_t WISR;           /*!< DSI Wrapper Interrupt and Status Register,                Address offset: 0x40C       */
-  __IO uint32_t WIFCR;          /*!< DSI Wrapper Interrupt Flag Clear Register,                Address offset: 0x410       */
-  uint32_t      RESERVED9;      /*!< Reserved, 0x414                                                                       */
-  __IO uint32_t WPCR[5];        /*!< DSI Wrapper PHY Configuration Register,                   Address offset: 0x418-0x42B */
-  uint32_t      RESERVED10;     /*!< Reserved, 0x42C                                                                       */
-  __IO uint32_t WRPCR;          /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430                 */
-} DSI_TypeDef;
-
-/** 
-  * @brief Ethernet MAC
-  */
-
-typedef struct
-{
-  __IO uint32_t MACCR;
-  __IO uint32_t MACFFR;
-  __IO uint32_t MACHTHR;
-  __IO uint32_t MACHTLR;
-  __IO uint32_t MACMIIAR;
-  __IO uint32_t MACMIIDR;
-  __IO uint32_t MACFCR;
-  __IO uint32_t MACVLANTR;             /*    8 */
-  uint32_t      RESERVED0[2];
-  __IO uint32_t MACRWUFFR;             /*   11 */
-  __IO uint32_t MACPMTCSR;
-  uint32_t      RESERVED1[2];
-  __IO uint32_t MACSR;                 /*   15 */
-  __IO uint32_t MACIMR;
-  __IO uint32_t MACA0HR;
-  __IO uint32_t MACA0LR;
-  __IO uint32_t MACA1HR;
-  __IO uint32_t MACA1LR;
-  __IO uint32_t MACA2HR;
-  __IO uint32_t MACA2LR;
-  __IO uint32_t MACA3HR;
-  __IO uint32_t MACA3LR;               /*   24 */
-  uint32_t      RESERVED2[40];
-  __IO uint32_t MMCCR;                 /*   65 */
-  __IO uint32_t MMCRIR;
-  __IO uint32_t MMCTIR;
-  __IO uint32_t MMCRIMR;
-  __IO uint32_t MMCTIMR;               /*   69 */
-  uint32_t      RESERVED3[14];
-  __IO uint32_t MMCTGFSCCR;            /*   84 */
-  __IO uint32_t MMCTGFMSCCR;
-  uint32_t      RESERVED4[5];
-  __IO uint32_t MMCTGFCR;
-  uint32_t      RESERVED5[10];
-  __IO uint32_t MMCRFCECR;
-  __IO uint32_t MMCRFAECR;
-  uint32_t      RESERVED6[10];
-  __IO uint32_t MMCRGUFCR;
-  uint32_t      RESERVED7[334];
-  __IO uint32_t PTPTSCR;
-  __IO uint32_t PTPSSIR;
-  __IO uint32_t PTPTSHR;
-  __IO uint32_t PTPTSLR;
-  __IO uint32_t PTPTSHUR;
-  __IO uint32_t PTPTSLUR;
-  __IO uint32_t PTPTSAR;
-  __IO uint32_t PTPTTHR;
-  __IO uint32_t PTPTTLR;
-  __IO uint32_t RESERVED8;
-  __IO uint32_t PTPTSSR;
-  uint32_t      RESERVED9[565];
-  __IO uint32_t DMABMR;
-  __IO uint32_t DMATPDR;
-  __IO uint32_t DMARPDR;
-  __IO uint32_t DMARDLAR;
-  __IO uint32_t DMATDLAR;
-  __IO uint32_t DMASR;
-  __IO uint32_t DMAOMR;
-  __IO uint32_t DMAIER;
-  __IO uint32_t DMAMFBOCR;
-  __IO uint32_t DMARSWTR;
-  uint32_t      RESERVED10[8];
-  __IO uint32_t DMACHTDR;
-  __IO uint32_t DMACHRDR;
-  __IO uint32_t DMACHTBAR;
-  __IO uint32_t DMACHRBAR;
-} ETH_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
-  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
-  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
-  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
-  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
-  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-
-typedef struct
-{
-  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */
-  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */
-  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */
-  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */
-  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */
-  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief Flexible Memory Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */   
-} FMC_Bank1_TypeDef; 
-
-/** 
-  * @brief Flexible Memory Controller Bank1E
-  */
-  
-typedef struct
-{
-  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
-} FMC_Bank1E_TypeDef;
-
-/** 
-  * @brief Flexible Memory Controller Bank3
-  */
- 
-typedef struct
-{
-  __IO uint32_t PCR;       /*!< NAND Flash control register,                       Address offset: 0x80 */
-  __IO uint32_t SR;        /*!< NAND Flash FIFO status and interrupt register,     Address offset: 0x84 */
-  __IO uint32_t PMEM;      /*!< NAND Flash Common memory space timing register,    Address offset: 0x88 */
-  __IO uint32_t PATT;      /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
-  uint32_t      RESERVED;  /*!< Reserved, 0x90                                                          */
-  __IO uint32_t ECCR;      /*!< NAND Flash ECC result registers,                   Address offset: 0x94 */
-} FMC_Bank3_TypeDef;
-
-/** 
-  * @brief Flexible Memory Controller Bank5_6
-  */
-  
-typedef struct
-{
-  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */
-  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */
-  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */
-  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */
-  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */
-} FMC_Bank5_6_TypeDef; 
-
-/** 
-  * @brief General Purpose I/O
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
-  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
-  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
-  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
-  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
-  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
-  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
-  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/** 
-  * @brief System configuration controller
-  */
-  
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */ 
-  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */
-  __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */
-  __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */
-  __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */
-  __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */
-  __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
-  __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
-  __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
-  __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief LCD-TFT Display Controller
-  */
-  
-typedef struct
-{
-  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04 */
-  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */
-  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */
-  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */
-  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */
-  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */
-  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20 */
-  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */
-  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28 */
-  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */
-  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30 */
-  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */
-  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */
-  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */
-  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
-  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */
-  __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                       Address offset: 0x48 */
-} LTDC_TypeDef;  
-
-/** 
-  * @brief LCD-TFT Display layer x Controller
-  */
-  
-typedef struct
-{  
-  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */
-  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
-  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */
-  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */
-  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */
-  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */
-  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */
-  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */
-  uint32_t      RESERVED0[2];  /*!< Reserved */
-  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */
-  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */
-  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */
-  uint32_t      RESERVED1[3];  /*!< Reserved */
-  __IO uint32_t CLUTWR;         /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */
-
-} LTDC_Layer_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
-  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
-  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
-  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
-  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
-  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
-  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
-  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
-  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
-  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
-  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
-  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
-  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
-  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
-  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
-  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
-  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
-  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
-  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
-  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
-  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
-  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
-  __IO uint32_t PLLSAICFGR;    /*!< RCC PLLSAI configuration register,                           Address offset: 0x88 */
-  __IO uint32_t DCKCFGR;       /*!< RCC Dedicated Clocks configuration register,                 Address offset: 0x8C */
-
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-
-typedef struct
-{
-  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
-  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
-  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
-  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
-  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
-  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
-  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */
-  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
-  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */
-  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
-  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */
-  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */
-  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */
-  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */
-  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
-  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */
-  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
-  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
-  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
-  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
-  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
-  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
-  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
-  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
-  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
-  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
-  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
-  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
-  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
-  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
-  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
-  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
-  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
-  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
-  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
-  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
-  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
-} RTC_TypeDef;
-
-/** 
-  * @brief Serial Audio Interface
-  */
-  
-typedef struct
-{
-  __IO uint32_t GCR;      /*!< SAI global configuration register,        Address offset: 0x00 */
-} SAI_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */
-  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */
-  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */
-  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */
-  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
-  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */
-  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */
-  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */
-} SAI_Block_TypeDef;
-
-/** 
-  * @brief SD host Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t POWER;          /*!< SDIO power control register,    Address offset: 0x00 */
-  __IO uint32_t CLKCR;          /*!< SDI clock control register,     Address offset: 0x04 */
-  __IO uint32_t ARG;            /*!< SDIO argument register,         Address offset: 0x08 */
-  __IO uint32_t CMD;            /*!< SDIO command register,          Address offset: 0x0C */
-  __I uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */
-  __I uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */
-  __I uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */
-  __I uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */
-  __I uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */
-  __IO uint32_t DTIMER;         /*!< SDIO data timer register,       Address offset: 0x24 */
-  __IO uint32_t DLEN;           /*!< SDIO data length register,      Address offset: 0x28 */
-  __IO uint32_t DCTRL;          /*!< SDIO data control register,     Address offset: 0x2C */
-  __I uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */
-  __I uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */
-  __IO uint32_t ICR;            /*!< SDIO interrupt clear register,  Address offset: 0x38 */
-  __IO uint32_t MASK;           /*!< SDIO mask register,             Address offset: 0x3C */
-  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
-  __I uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */
-  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
-  __IO uint32_t FIFO;           /*!< SDIO data FIFO register,        Address offset: 0x80 */
-} SDIO_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief QUAD Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */
-  __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
-  __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */
-  __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
-  __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
-  __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
-  __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */
-  __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
-  __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */
-  __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
-  __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */                  
-  __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
-  __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */    
-} QUADSPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
-  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
-  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
-  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief RNG
-  */
-  
-typedef struct 
-{
-  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
-  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
-  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
-} RNG_TypeDef;
-
- 
-/** 
-  * @brief USB_OTG_Core_Registers
-  */
-typedef struct
-{
- __IO uint32_t GOTGCTL;               /*!< USB_OTG Control and Status Register          000h */
-  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */
-  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */
-  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */
-  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */
-  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */
-  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */
-  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */
-  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */
-  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */
-  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */
-  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */
-  uint32_t Reserved30[2];             /*!< Reserved                                     030h */
-  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */
-  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */
-  uint32_t  Reserved5[3];             /*!< Reserved                                040h-048h */
-  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */
-  uint32_t  Reserved6;                /*!< Reserved                                     050h */ 
-  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */
-  uint32_t  Reserved;                 /*!< Reserved                                     058h */
-  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */
-  uint32_t  Reserved43[40];           /*!< Reserved                                058h-0FFh */
-  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */
-  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */
-} USB_OTG_GlobalTypeDef;
-
-/** 
-  * @brief USB_OTG_device_Registers
-  */
-typedef struct 
-{
-  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */
-  __IO uint32_t DCTL;            /*!< dev Control Register         804h */
-  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */
-  uint32_t Reserved0C;           /*!< Reserved                     80Ch */
-  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */
-  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */
-  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */
-  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */
-  uint32_t  Reserved20;          /*!< Reserved                     820h */
-  uint32_t Reserved9;            /*!< Reserved                     824h */
-  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */
-  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */
-  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */
-  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */
-  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */
-  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */  
-  uint32_t Reserved40;           /*!< dedicated EP mask            840h */
-  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */
-  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */
-  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */   
-} USB_OTG_DeviceTypeDef;
-
-/** 
-  * @brief USB_OTG_IN_Endpoint-Specific_Register
-  */
-typedef struct 
-{
-  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */
-  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */
-  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */
-  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */
-  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */
-  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */
-  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
-  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
-} USB_OTG_INEndpointTypeDef;
-
-/** 
-  * @brief USB_OTG_OUT_Endpoint-Specific_Registers
-  */
-typedef struct 
-{
-  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */
-  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */
-  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */
-  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */
-  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */
-  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */
-  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
-} USB_OTG_OUTEndpointTypeDef;
-
-/** 
-  * @brief USB_OTG_Host_Mode_Register_Structures
-  */
-typedef struct 
-{
-  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */
-  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */
-  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */
-  uint32_t Reserved40C;           /*!< Reserved                             40Ch */
-  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */
-  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */
-  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */
-} USB_OTG_HostTypeDef;
-
-/** 
-  * @brief USB_OTG_Host_Channel_Specific_Registers
-  */
-typedef struct
-{
-  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */
-  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */
-  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */
-  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */
-  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */
-  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */
-  uint32_t Reserved[2];           /*!< Reserved                                      */
-} USB_OTG_HostChannelTypeDef;
-
-/**
-  * @}
-  */
-    
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-#define FLASH_BASE            0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region                         */
-#define CCMDATARAM_BASE       0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
-#define SRAM1_BASE            0x20000000U /*!< SRAM1(160 KB) base address in the alias region                             */
-#define SRAM2_BASE            0x20028000U /*!< SRAM2(32 KB) base address in the alias region                              */
-#define SRAM3_BASE            0x20030000U /*!< SRAM3(128 KB) base address in the alias region                              */
-#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region                                */
-#define BKPSRAM_BASE          0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region                         */
-#define FMC_R_BASE            0xA0000000U /*!< FMC registers base address                                                 */
-#define QSPI_R_BASE           0xA0001000U /*!< QuadSPI registers base address                                            */
-#define SRAM1_BB_BASE         0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region                             */
-#define SRAM2_BB_BASE         0x22500000U /*!< SRAM2(16 KB) base address in the bit-band region                              */
-#define SRAM3_BB_BASE         0x22600000U /*!< SRAM3(64 KB) base address in the bit-band region                              */
-#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region                                */
-#define BKPSRAM_BB_BASE       0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region                         */
-#define FLASH_END             0x081FFFFFU /*!< FLASH end address */
-#define CCMDATARAM_END        0x1000FFFFU /*!< CCM data RAM end address */
-
-/* Legacy defines */
-#define SRAM_BASE             SRAM1_BASE
-#define SRAM_BB_BASE          SRAM1_BB_BASE
-
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000U)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)
-#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800U)
-#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00U)
-#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000U)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)
-#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400U)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)
-#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000U)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800U)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00U)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x5000U)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)
-#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)
-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)
-#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800U)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)
-#define UART7_BASE            (APB1PERIPH_BASE + 0x7800U)
-#define UART8_BASE            (APB1PERIPH_BASE + 0x7C00U)
-
-/*!< APB2 peripherals */
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000U)
-#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400U)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x1000U)
-#define USART6_BASE           (APB2PERIPH_BASE + 0x1400U)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000U)
-#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100U)
-#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200U)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x2300U)
-#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00U)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)
-#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400U)
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800U)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00U)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000U)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400U)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800U)
-#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000U)
-#define SPI6_BASE             (APB2PERIPH_BASE + 0x5400U)
-#define SAI1_BASE             (APB2PERIPH_BASE + 0x5800U)
-#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004U)
-#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024U)
-#define LTDC_BASE             (APB2PERIPH_BASE + 0x6800U)
-#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84U)
-#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104U)
-#define DSI_BASE              (APB2PERIPH_BASE + 0x6C00U)
-
-/*!< AHB1 peripherals */
-#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000U)
-#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400U)
-#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800U)
-#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00U)
-#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000U)
-#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400U)
-#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800U)
-#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00U)
-#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000U)
-#define GPIOJ_BASE            (AHB1PERIPH_BASE + 0x2400U)
-#define GPIOK_BASE            (AHB1PERIPH_BASE + 0x2800U)
-#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)
-#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800U)
-#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00U)
-#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000U)
-#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010U)
-#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028U)
-#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040U)
-#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058U)
-#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070U)
-#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088U)
-#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0U)
-#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8U)
-#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400U)
-#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010U)
-#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028U)
-#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040U)
-#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058U)
-#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070U)
-#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088U)
-#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0U)
-#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)
-#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000U)
-#define ETH_MAC_BASE          (ETH_BASE)
-#define ETH_MMC_BASE          (ETH_BASE + 0x0100U)
-#define ETH_PTP_BASE          (ETH_BASE + 0x0700U)
-#define ETH_DMA_BASE          (ETH_BASE + 0x1000U)
-#define DMA2D_BASE            (AHB1PERIPH_BASE + 0xB000U)
-
-/*!< AHB2 peripherals */
-#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000U)
-#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800U)
-
-/*!< FMC Bankx registers base address */
-#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000U)
-#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104U)
-#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080U)
-#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140U)
-
-/*!< Debug MCU registers base address */
-#define DBGMCU_BASE           0xE0042000U
-
-/*!< USB registers base address */
-#define USB_OTG_HS_PERIPH_BASE               0x40040000U
-#define USB_OTG_FS_PERIPH_BASE               0x50000000U
-
-#define USB_OTG_GLOBAL_BASE                  0x000U
-#define USB_OTG_DEVICE_BASE                  0x800U
-#define USB_OTG_IN_ENDPOINT_BASE             0x900U
-#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U
-#define USB_OTG_EP_REG_SIZE                  0x20U
-#define USB_OTG_HOST_BASE                    0x400U
-#define USB_OTG_HOST_PORT_BASE               0x440U
-#define USB_OTG_HOST_CHANNEL_BASE            0x500U
-#define USB_OTG_HOST_CHANNEL_SIZE            0x20U
-#define USB_OTG_PCGCCTL_BASE                 0xE00U
-#define USB_OTG_FIFO_BASE                    0x1000U
-#define USB_OTG_FIFO_SIZE                    0x1000U
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
-#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
-#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define UART4               ((USART_TypeDef *) UART4_BASE)
-#define UART5               ((USART_TypeDef *) UART5_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
-#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
-#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
-#define UART7               ((USART_TypeDef *) UART7_BASE)
-#define UART8               ((USART_TypeDef *) UART8_BASE)
-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
-#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define USART6              ((USART_TypeDef *) USART6_BASE)
-#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
-#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
-#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE) 
-#define SPI4                ((SPI_TypeDef *) SPI4_BASE)
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-#define SPI5                ((SPI_TypeDef *) SPI5_BASE)
-#define SPI6                ((SPI_TypeDef *) SPI6_BASE)
-#define SAI1                ((SAI_TypeDef *) SAI1_BASE)
-#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
-#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
-#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)
-#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
-#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
-#define DSI                 ((DSI_TypeDef *)DSI_BASE)
-
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
-#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)
-#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
-#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
-#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
-#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
-#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
-#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
-#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
-#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
-#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
-#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
-#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
-#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
-#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
-#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
-#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
-#define ETH                 ((ETH_TypeDef *) ETH_BASE)  
-#define DMA2D               ((DMA2D_TypeDef *)DMA2D_BASE)
-#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
-#define RNG                 ((RNG_TypeDef *) RNG_BASE)
-#define FMC_Bank1           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
-#define FMC_Bank1E          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
-#define FMC_Bank3           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
-#define FMC_Bank5_6         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
-#define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)
-
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
-#define USB_OTG_HS          ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers_Bits_Definition               */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Analog to Digital Converter                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          0x00000001U        /*!<Analog watchdog flag */
-#define  ADC_SR_EOC                          0x00000002U        /*!<End of conversion */
-#define  ADC_SR_JEOC                         0x00000004U        /*!<Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        0x00000008U        /*!<Injected channel Start flag */
-#define  ADC_SR_STRT                         0x00000010U        /*!<Regular channel Start flag */
-#define  ADC_SR_OVR                          0x00000020U        /*!<Overrun flag */
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
-#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels */
-#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels */
-#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution) */
-#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
-  
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion */
-#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode */
-#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC) */
-#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection */
-#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment */
-#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      0xFFFFU            /*!<Injected data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag */
-#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion */
-#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag */
-#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag */
-#define  ADC_CSR_OVR1                        0x00000020U        /*!<ADC1 DMA overrun  flag */
-#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag */
-#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion */
-#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag */
-#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag */
-#define  ADC_CSR_OVR2                        0x00002000U        /*!<ADC2 DMA overrun  flag */
-#define  ADC_CSR_AWD3                        0x00010000U        /*!<ADC3 Analog watchdog flag */
-#define  ADC_CSR_EOC3                        0x00020000U        /*!<ADC3 End of conversion */
-#define  ADC_CSR_JEOC3                       0x00040000U        /*!<ADC3 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT3                      0x00080000U        /*!<ADC3 Injected channel Start flag */
-#define  ADC_CSR_STRT3                       0x00100000U        /*!<ADC3 Regular channel Start flag */
-#define  ADC_CSR_OVR3                        0x00200000U        /*!<ADC3 DMA overrun  flag */
-
-/* Legacy defines */
-#define  ADC_CSR_DOVR1                        ADC_CSR_OVR1
-#define  ADC_CSR_DOVR2                        ADC_CSR_OVR2
-#define  ADC_CSR_DOVR3                        ADC_CSR_OVR3
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
-#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
-#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
-#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
-#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
-
-/*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                      0x0000FFFFU         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                      0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Controller Area Network                            */
-/*                                                                            */
-/******************************************************************************/
-/*!<CAN control and status registers */
-/*******************  Bit definition for CAN_MCR register  ********************/
-#define  CAN_MCR_INRQ                        0x00000001U        /*!<Initialization Request */
-#define  CAN_MCR_SLEEP                       0x00000002U        /*!<Sleep Mode Request */
-#define  CAN_MCR_TXFP                        0x00000004U        /*!<Transmit FIFO Priority */
-#define  CAN_MCR_RFLM                        0x00000008U        /*!<Receive FIFO Locked Mode */
-#define  CAN_MCR_NART                        0x00000010U        /*!<No Automatic Retransmission */
-#define  CAN_MCR_AWUM                        0x00000020U        /*!<Automatic Wakeup Mode */
-#define  CAN_MCR_ABOM                        0x00000040U        /*!<Automatic Bus-Off Management */
-#define  CAN_MCR_TTCM                        0x00000080U        /*!<Time Triggered Communication Mode */
-#define  CAN_MCR_RESET                       0x00008000U        /*!<bxCAN software master reset */
-#define  CAN_MCR_DBF                         0x00010000U        /*!<bxCAN Debug freeze */
-/*******************  Bit definition for CAN_MSR register  ********************/
-#define  CAN_MSR_INAK                        0x0001U            /*!<Initialization Acknowledge */
-#define  CAN_MSR_SLAK                        0x0002U            /*!<Sleep Acknowledge */
-#define  CAN_MSR_ERRI                        0x0004U            /*!<Error Interrupt */
-#define  CAN_MSR_WKUI                        0x0008U            /*!<Wakeup Interrupt */
-#define  CAN_MSR_SLAKI                       0x0010U            /*!<Sleep Acknowledge Interrupt */
-#define  CAN_MSR_TXM                         0x0100U            /*!<Transmit Mode */
-#define  CAN_MSR_RXM                         0x0200U            /*!<Receive Mode */
-#define  CAN_MSR_SAMP                        0x0400U            /*!<Last Sample Point */
-#define  CAN_MSR_RX                          0x0800U            /*!<CAN Rx Signal */
-
-/*******************  Bit definition for CAN_TSR register  ********************/
-#define  CAN_TSR_RQCP0                       0x00000001U        /*!<Request Completed Mailbox0 */
-#define  CAN_TSR_TXOK0                       0x00000002U        /*!<Transmission OK of Mailbox0 */
-#define  CAN_TSR_ALST0                       0x00000004U        /*!<Arbitration Lost for Mailbox0 */
-#define  CAN_TSR_TERR0                       0x00000008U        /*!<Transmission Error of Mailbox0 */
-#define  CAN_TSR_ABRQ0                       0x00000080U        /*!<Abort Request for Mailbox0 */
-#define  CAN_TSR_RQCP1                       0x00000100U        /*!<Request Completed Mailbox1 */
-#define  CAN_TSR_TXOK1                       0x00000200U        /*!<Transmission OK of Mailbox1 */
-#define  CAN_TSR_ALST1                       0x00000400U        /*!<Arbitration Lost for Mailbox1 */
-#define  CAN_TSR_TERR1                       0x00000800U        /*!<Transmission Error of Mailbox1 */
-#define  CAN_TSR_ABRQ1                       0x00008000U        /*!<Abort Request for Mailbox 1 */
-#define  CAN_TSR_RQCP2                       0x00010000U        /*!<Request Completed Mailbox2 */
-#define  CAN_TSR_TXOK2                       0x00020000U        /*!<Transmission OK of Mailbox 2 */
-#define  CAN_TSR_ALST2                       0x00040000U        /*!<Arbitration Lost for mailbox 2 */
-#define  CAN_TSR_TERR2                       0x00080000U        /*!<Transmission Error of Mailbox 2 */
-#define  CAN_TSR_ABRQ2                       0x00800000U        /*!<Abort Request for Mailbox 2 */
-#define  CAN_TSR_CODE                        0x03000000U        /*!<Mailbox Code */
-
-#define  CAN_TSR_TME                         0x1C000000U        /*!<TME[2:0] bits */
-#define  CAN_TSR_TME0                        0x04000000U        /*!<Transmit Mailbox 0 Empty */
-#define  CAN_TSR_TME1                        0x08000000U        /*!<Transmit Mailbox 1 Empty */
-#define  CAN_TSR_TME2                        0x10000000U        /*!<Transmit Mailbox 2 Empty */
-
-#define  CAN_TSR_LOW                         0xE0000000U        /*!<LOW[2:0] bits */
-#define  CAN_TSR_LOW0                        0x20000000U        /*!<Lowest Priority Flag for Mailbox 0 */
-#define  CAN_TSR_LOW1                        0x40000000U        /*!<Lowest Priority Flag for Mailbox 1 */
-#define  CAN_TSR_LOW2                        0x80000000U        /*!<Lowest Priority Flag for Mailbox 2 */
-
-/*******************  Bit definition for CAN_RF0R register  *******************/
-#define  CAN_RF0R_FMP0                       0x03U               /*!<FIFO 0 Message Pending */
-#define  CAN_RF0R_FULL0                      0x08U               /*!<FIFO 0 Full */
-#define  CAN_RF0R_FOVR0                      0x10U               /*!<FIFO 0 Overrun */
-#define  CAN_RF0R_RFOM0                      0x20U               /*!<Release FIFO 0 Output Mailbox */
-
-/*******************  Bit definition for CAN_RF1R register  *******************/
-#define  CAN_RF1R_FMP1                       0x03U               /*!<FIFO 1 Message Pending */
-#define  CAN_RF1R_FULL1                      0x08U               /*!<FIFO 1 Full */
-#define  CAN_RF1R_FOVR1                      0x10U               /*!<FIFO 1 Overrun */
-#define  CAN_RF1R_RFOM1                      0x20U               /*!<Release FIFO 1 Output Mailbox */
-
-/********************  Bit definition for CAN_IER register  *******************/
-#define  CAN_IER_TMEIE                       0x00000001U        /*!<Transmit Mailbox Empty Interrupt Enable */
-#define  CAN_IER_FMPIE0                      0x00000002U        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE0                       0x00000004U        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE0                      0x00000008U        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_FMPIE1                      0x00000010U        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE1                       0x00000020U        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE1                      0x00000040U        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error Warning Interrupt Enable */
-#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error Passive Interrupt Enable */
-#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-Off Interrupt Enable */
-#define  CAN_IER_LECIE                       0x00000800U        /*!<Last Error Code Interrupt Enable */
-#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error Interrupt Enable */
-#define  CAN_IER_WKUIE                       0x00010000U        /*!<Wakeup Interrupt Enable */
-#define  CAN_IER_SLKIE                       0x00020000U        /*!<Sleep Interrupt Enable */
-#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error warning interrupt enable */
-#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error passive interrupt enable */
-#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-off interrupt enable */
-#define  CAN_IER_LECIE                       0x00000800U        /*!<Last error code interrupt enable */
-#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error interrupt enable */
-
-
-/********************  Bit definition for CAN_ESR register  *******************/
-#define  CAN_ESR_EWGF                        0x00000001U        /*!<Error Warning Flag */
-#define  CAN_ESR_EPVF                        0x00000002U        /*!<Error Passive Flag */
-#define  CAN_ESR_BOFF                        0x00000004U        /*!<Bus-Off Flag */
-
-#define  CAN_ESR_LEC                         0x00000070U        /*!<LEC[2:0] bits (Last Error Code) */
-#define  CAN_ESR_LEC_0                       0x00000010U        /*!<Bit 0 */
-#define  CAN_ESR_LEC_1                       0x00000020U        /*!<Bit 1 */
-#define  CAN_ESR_LEC_2                       0x00000040U        /*!<Bit 2 */
-
-#define  CAN_ESR_TEC                         0x00FF0000U        /*!<Least significant byte of the 9-bit Transmit Error Counter */
-#define  CAN_ESR_REC                         0xFF000000U        /*!<Receive Error Counter */
-
-/*******************  Bit definition for CAN_BTR register  ********************/
-#define  CAN_BTR_BRP                         0x000003FFU        /*!<Baud Rate Prescaler */
-#define  CAN_BTR_TS1                         0x000F0000U        /*!<Time Segment 1 */
-#define  CAN_BTR_TS1_0                       0x00010000U        /*!<Bit 0 */
-#define  CAN_BTR_TS1_1                       0x00020000U        /*!<Bit 1 */
-#define  CAN_BTR_TS1_2                       0x00040000U        /*!<Bit 2 */
-#define  CAN_BTR_TS1_3                       0x00080000U        /*!<Bit 3 */
-#define  CAN_BTR_TS2                         0x00700000U        /*!<Time Segment 2 */
-#define  CAN_BTR_TS2_0                       0x00100000U        /*!<Bit 0 */
-#define  CAN_BTR_TS2_1                       0x00200000U        /*!<Bit 1 */
-#define  CAN_BTR_TS2_2                       0x00400000U        /*!<Bit 2 */
-#define  CAN_BTR_SJW                         0x03000000U        /*!<Resynchronization Jump Width */
-#define  CAN_BTR_SJW_0                       0x01000000U        /*!<Bit 0 */
-#define  CAN_BTR_SJW_1                       0x02000000U        /*!<Bit 1 */
-#define  CAN_BTR_LBKM                        0x40000000U        /*!<Loop Back Mode (Debug) */
-#define  CAN_BTR_SILM                        0x80000000U        /*!<Silent Mode */
-
-
-/*!<Mailbox registers */
-/******************  Bit definition for CAN_TI0R register  ********************/
-#define  CAN_TI0R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI0R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_TI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/******************  Bit definition for CAN_TDT0R register  *******************/
-#define  CAN_TDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT0R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/******************  Bit definition for CAN_TDL0R register  *******************/
-#define  CAN_TDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/******************  Bit definition for CAN_TDH0R register  *******************/
-#define  CAN_TDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI1R register  *******************/
-#define  CAN_TI1R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI1R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI1R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_TI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT1R register  ******************/
-#define  CAN_TDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT1R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL1R register  ******************/
-#define  CAN_TDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH1R register  ******************/
-#define  CAN_TDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI2R register  *******************/
-#define  CAN_TI2R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI2R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI2R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI2R_EXID                       0x001FFFF8U        /*!<Extended identifier */
-#define  CAN_TI2R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT2R register  ******************/  
-#define  CAN_TDT2R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT2R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT2R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL2R register  ******************/
-#define  CAN_TDL2R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL2R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL2R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL2R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH2R register  ******************/
-#define  CAN_TDH2R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH2R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH2R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH2R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI0R register  *******************/
-#define  CAN_RI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_RI0R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_RI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_RI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT0R register  ******************/
-#define  CAN_RDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_RDT0R_FMI                       0x0000FF00U        /*!<Filter Match Index */
-#define  CAN_RDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL0R register  ******************/
-#define  CAN_RDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_RDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_RDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_RDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH0R register  ******************/
-#define  CAN_RDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_RDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_RDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_RDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI1R register  *******************/
-#define  CAN_RI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_RI1R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_RI1R_EXID                       0x001FFFF8U        /*!<Extended identifier */
-#define  CAN_RI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT1R register  ******************/
-#define  CAN_RDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_RDT1R_FMI                       0x0000FF00U        /*!<Filter Match Index */
-#define  CAN_RDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL1R register  ******************/
-#define  CAN_RDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_RDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_RDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_RDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH1R register  ******************/
-#define  CAN_RDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_RDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_RDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_RDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*!<CAN filter registers */
-/*******************  Bit definition for CAN_FMR register  ********************/
-#define  CAN_FMR_FINIT                       0x01U               /*!<Filter Init Mode */
-#define  CAN_FMR_CAN2SB                      0x00003F00U        /*!<CAN2 start bank */
-
-/*******************  Bit definition for CAN_FM1R register  *******************/
-#define  CAN_FM1R_FBM                        0x0FFFFFFFU        /*!<Filter Mode */
-#define  CAN_FM1R_FBM0                       0x00000001U        /*!<Filter Init Mode bit 0 */
-#define  CAN_FM1R_FBM1                       0x00000002U        /*!<Filter Init Mode bit 1 */
-#define  CAN_FM1R_FBM2                       0x00000004U        /*!<Filter Init Mode bit 2 */
-#define  CAN_FM1R_FBM3                       0x00000008U        /*!<Filter Init Mode bit 3 */
-#define  CAN_FM1R_FBM4                       0x00000010U        /*!<Filter Init Mode bit 4 */
-#define  CAN_FM1R_FBM5                       0x00000020U        /*!<Filter Init Mode bit 5 */
-#define  CAN_FM1R_FBM6                       0x00000040U        /*!<Filter Init Mode bit 6 */
-#define  CAN_FM1R_FBM7                       0x00000080U        /*!<Filter Init Mode bit 7 */
-#define  CAN_FM1R_FBM8                       0x00000100U        /*!<Filter Init Mode bit 8 */
-#define  CAN_FM1R_FBM9                       0x00000200U        /*!<Filter Init Mode bit 9 */
-#define  CAN_FM1R_FBM10                      0x00000400U        /*!<Filter Init Mode bit 10 */
-#define  CAN_FM1R_FBM11                      0x00000800U        /*!<Filter Init Mode bit 11 */
-#define  CAN_FM1R_FBM12                      0x00001000U        /*!<Filter Init Mode bit 12 */
-#define  CAN_FM1R_FBM13                      0x00002000U        /*!<Filter Init Mode bit 13 */
-#define  CAN_FM1R_FBM14                      0x00004000U        /*!<Filter Init Mode bit 14 */
-#define  CAN_FM1R_FBM15                      0x00008000U        /*!<Filter Init Mode bit 15 */
-#define  CAN_FM1R_FBM16                      0x00010000U        /*!<Filter Init Mode bit 16 */
-#define  CAN_FM1R_FBM17                      0x00020000U        /*!<Filter Init Mode bit 17 */
-#define  CAN_FM1R_FBM18                      0x00040000U        /*!<Filter Init Mode bit 18 */
-#define  CAN_FM1R_FBM19                      0x00080000U        /*!<Filter Init Mode bit 19 */
-#define  CAN_FM1R_FBM20                      0x00100000U        /*!<Filter Init Mode bit 20 */
-#define  CAN_FM1R_FBM21                      0x00200000U        /*!<Filter Init Mode bit 21 */
-#define  CAN_FM1R_FBM22                      0x00400000U        /*!<Filter Init Mode bit 22 */
-#define  CAN_FM1R_FBM23                      0x00800000U        /*!<Filter Init Mode bit 23 */
-#define  CAN_FM1R_FBM24                      0x01000000U        /*!<Filter Init Mode bit 24 */
-#define  CAN_FM1R_FBM25                      0x02000000U        /*!<Filter Init Mode bit 25 */
-#define  CAN_FM1R_FBM26                      0x04000000U        /*!<Filter Init Mode bit 26 */
-#define  CAN_FM1R_FBM27                      0x08000000U        /*!<Filter Init Mode bit 27 */
-
-/*******************  Bit definition for CAN_FS1R register  *******************/
-#define  CAN_FS1R_FSC                        0x0FFFFFFFU        /*!<Filter Scale Configuration */
-#define  CAN_FS1R_FSC0                       0x00000001U        /*!<Filter Scale Configuration bit 0 */
-#define  CAN_FS1R_FSC1                       0x00000002U        /*!<Filter Scale Configuration bit 1 */
-#define  CAN_FS1R_FSC2                       0x00000004U        /*!<Filter Scale Configuration bit 2 */
-#define  CAN_FS1R_FSC3                       0x00000008U        /*!<Filter Scale Configuration bit 3 */
-#define  CAN_FS1R_FSC4                       0x00000010U        /*!<Filter Scale Configuration bit 4 */
-#define  CAN_FS1R_FSC5                       0x00000020U        /*!<Filter Scale Configuration bit 5 */
-#define  CAN_FS1R_FSC6                       0x00000040U        /*!<Filter Scale Configuration bit 6 */
-#define  CAN_FS1R_FSC7                       0x00000080U        /*!<Filter Scale Configuration bit 7 */
-#define  CAN_FS1R_FSC8                       0x00000100U        /*!<Filter Scale Configuration bit 8 */
-#define  CAN_FS1R_FSC9                       0x00000200U        /*!<Filter Scale Configuration bit 9 */
-#define  CAN_FS1R_FSC10                      0x00000400U        /*!<Filter Scale Configuration bit 10 */
-#define  CAN_FS1R_FSC11                      0x00000800U        /*!<Filter Scale Configuration bit 11 */
-#define  CAN_FS1R_FSC12                      0x00001000U        /*!<Filter Scale Configuration bit 12 */
-#define  CAN_FS1R_FSC13                      0x00002000U        /*!<Filter Scale Configuration bit 13 */
-#define  CAN_FS1R_FSC14                      0x00004000U        /*!<Filter Scale Configuration bit 14 */
-#define  CAN_FS1R_FSC15                      0x00008000U        /*!<Filter Scale Configuration bit 15 */
-#define  CAN_FS1R_FSC16                      0x00010000U        /*!<Filter Scale Configuration bit 16 */
-#define  CAN_FS1R_FSC17                      0x00020000U        /*!<Filter Scale Configuration bit 17 */
-#define  CAN_FS1R_FSC18                      0x00040000U        /*!<Filter Scale Configuration bit 18 */
-#define  CAN_FS1R_FSC19                      0x00080000U        /*!<Filter Scale Configuration bit 19 */
-#define  CAN_FS1R_FSC20                      0x00100000U        /*!<Filter Scale Configuration bit 20 */
-#define  CAN_FS1R_FSC21                      0x00200000U        /*!<Filter Scale Configuration bit 21 */
-#define  CAN_FS1R_FSC22                      0x00400000U        /*!<Filter Scale Configuration bit 22 */
-#define  CAN_FS1R_FSC23                      0x00800000U        /*!<Filter Scale Configuration bit 23 */
-#define  CAN_FS1R_FSC24                      0x01000000U        /*!<Filter Scale Configuration bit 24 */
-#define  CAN_FS1R_FSC25                      0x02000000U        /*!<Filter Scale Configuration bit 25 */
-#define  CAN_FS1R_FSC26                      0x04000000U        /*!<Filter Scale Configuration bit 26 */
-#define  CAN_FS1R_FSC27                      0x08000000U        /*!<Filter Scale Configuration bit 27 */
-
-/******************  Bit definition for CAN_FFA1R register  *******************/
-#define  CAN_FFA1R_FFA                        0x0FFFFFFFU        /*!<Filter FIFO Assignment */
-#define  CAN_FFA1R_FFA0                       0x00000001U        /*!<Filter FIFO Assignment bit 0 */
-#define  CAN_FFA1R_FFA1                       0x00000002U        /*!<Filter FIFO Assignment bit 1 */
-#define  CAN_FFA1R_FFA2                       0x00000004U        /*!<Filter FIFO Assignment bit 2 */
-#define  CAN_FFA1R_FFA3                       0x00000008U        /*!<Filter FIFO Assignment bit 3 */
-#define  CAN_FFA1R_FFA4                       0x00000010U        /*!<Filter FIFO Assignment bit 4 */
-#define  CAN_FFA1R_FFA5                       0x00000020U        /*!<Filter FIFO Assignment bit 5 */
-#define  CAN_FFA1R_FFA6                       0x00000040U        /*!<Filter FIFO Assignment bit 6 */
-#define  CAN_FFA1R_FFA7                       0x00000080U        /*!<Filter FIFO Assignment bit 7 */
-#define  CAN_FFA1R_FFA8                       0x00000100U        /*!<Filter FIFO Assignment bit 8 */
-#define  CAN_FFA1R_FFA9                       0x00000200U        /*!<Filter FIFO Assignment bit 9 */
-#define  CAN_FFA1R_FFA10                      0x00000400U        /*!<Filter FIFO Assignment bit 10 */
-#define  CAN_FFA1R_FFA11                      0x00000800U        /*!<Filter FIFO Assignment bit 11 */
-#define  CAN_FFA1R_FFA12                      0x00001000U        /*!<Filter FIFO Assignment bit 12 */
-#define  CAN_FFA1R_FFA13                      0x00002000U        /*!<Filter FIFO Assignment bit 13 */
-#define  CAN_FFA1R_FFA14                      0x00004000U        /*!<Filter FIFO Assignment bit 14 */
-#define  CAN_FFA1R_FFA15                      0x00008000U        /*!<Filter FIFO Assignment bit 15 */
-#define  CAN_FFA1R_FFA16                      0x00010000U        /*!<Filter FIFO Assignment bit 16 */
-#define  CAN_FFA1R_FFA17                      0x00020000U        /*!<Filter FIFO Assignment bit 17 */
-#define  CAN_FFA1R_FFA18                      0x00040000U        /*!<Filter FIFO Assignment bit 18 */
-#define  CAN_FFA1R_FFA19                      0x00080000U        /*!<Filter FIFO Assignment bit 19 */
-#define  CAN_FFA1R_FFA20                      0x00100000U        /*!<Filter FIFO Assignment bit 20 */
-#define  CAN_FFA1R_FFA21                      0x00200000U        /*!<Filter FIFO Assignment bit 21 */
-#define  CAN_FFA1R_FFA22                      0x00400000U        /*!<Filter FIFO Assignment bit 22 */
-#define  CAN_FFA1R_FFA23                      0x00800000U        /*!<Filter FIFO Assignment bit 23 */
-#define  CAN_FFA1R_FFA24                      0x01000000U        /*!<Filter FIFO Assignment bit 24 */
-#define  CAN_FFA1R_FFA25                      0x02000000U        /*!<Filter FIFO Assignment bit 25 */
-#define  CAN_FFA1R_FFA26                      0x04000000U        /*!<Filter FIFO Assignment bit 26 */
-#define  CAN_FFA1R_FFA27                      0x08000000U        /*!<Filter FIFO Assignment bit 27 */
-
-/*******************  Bit definition for CAN_FA1R register  *******************/
-#define  CAN_FA1R_FACT                        0x0FFFFFFFU        /*!<Filter Active */
-#define  CAN_FA1R_FACT0                       0x00000001U        /*!<Filter Active bit 0 */
-#define  CAN_FA1R_FACT1                       0x00000002U        /*!<Filter Active bit 1 */
-#define  CAN_FA1R_FACT2                       0x00000004U        /*!<Filter Active bit 2 */
-#define  CAN_FA1R_FACT3                       0x00000008U        /*!<Filter Active bit 3 */
-#define  CAN_FA1R_FACT4                       0x00000010U        /*!<Filter Active bit 4 */
-#define  CAN_FA1R_FACT5                       0x00000020U        /*!<Filter Active bit 5 */
-#define  CAN_FA1R_FACT6                       0x00000040U        /*!<Filter Active bit 6 */
-#define  CAN_FA1R_FACT7                       0x00000080U        /*!<Filter Active bit 7 */
-#define  CAN_FA1R_FACT8                       0x00000100U        /*!<Filter Active bit 8 */
-#define  CAN_FA1R_FACT9                       0x00000200U        /*!<Filter Active bit 9 */
-#define  CAN_FA1R_FACT10                      0x00000400U        /*!<Filter Active bit 10 */
-#define  CAN_FA1R_FACT11                      0x00000800U        /*!<Filter Active bit 11 */
-#define  CAN_FA1R_FACT12                      0x00001000U        /*!<Filter Active bit 12 */
-#define  CAN_FA1R_FACT13                      0x00002000U        /*!<Filter Active bit 13 */
-#define  CAN_FA1R_FACT14                      0x00004000U        /*!<Filter Active bit 14 */
-#define  CAN_FA1R_FACT15                      0x00008000U        /*!<Filter Active bit 15 */
-#define  CAN_FA1R_FACT16                      0x00010000U        /*!<Filter Active bit 16 */
-#define  CAN_FA1R_FACT17                      0x00020000U        /*!<Filter Active bit 17 */
-#define  CAN_FA1R_FACT18                      0x00040000U        /*!<Filter Active bit 18 */
-#define  CAN_FA1R_FACT19                      0x00080000U        /*!<Filter Active bit 19 */
-#define  CAN_FA1R_FACT20                      0x00100000U        /*!<Filter Active bit 20 */
-#define  CAN_FA1R_FACT21                      0x00200000U        /*!<Filter Active bit 21 */
-#define  CAN_FA1R_FACT22                      0x00400000U        /*!<Filter Active bit 22 */
-#define  CAN_FA1R_FACT23                      0x00800000U        /*!<Filter Active bit 23 */
-#define  CAN_FA1R_FACT24                      0x01000000U        /*!<Filter Active bit 24 */
-#define  CAN_FA1R_FACT25                      0x02000000U        /*!<Filter Active bit 25 */
-#define  CAN_FA1R_FACT26                      0x04000000U        /*!<Filter Active bit 26 */
-#define  CAN_FA1R_FACT27                      0x08000000U        /*!<Filter Active bit 27 */
-
-
-/*******************  Bit definition for CAN_F0R1 register  *******************/
-#define  CAN_F0R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F0R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F0R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F0R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F0R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F0R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F0R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F0R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F0R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F0R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F0R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F0R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F0R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F0R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F0R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F0R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F0R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F0R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F0R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F0R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F0R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F0R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F0R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F0R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F0R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F0R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F0R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F0R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F0R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F0R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F0R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F0R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R1 register  *******************/
-#define  CAN_F1R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F1R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F1R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F1R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F1R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F1R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F1R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F1R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F1R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F1R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F1R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F1R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F1R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F1R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F1R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F1R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F1R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F1R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F1R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F1R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F1R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F1R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F1R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F1R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F1R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F1R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F1R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F1R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F1R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F1R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F1R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F1R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R1 register  *******************/
-#define  CAN_F2R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F2R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F2R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F2R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F2R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F2R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F2R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F2R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F2R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F2R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F2R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F2R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F2R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F2R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F2R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F2R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F2R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F2R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F2R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F2R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F2R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F2R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F2R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F2R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F2R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F2R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F2R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F2R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F2R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F2R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F2R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F2R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R1 register  *******************/
-#define  CAN_F3R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F3R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F3R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F3R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F3R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F3R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F3R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F3R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F3R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F3R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F3R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F3R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F3R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F3R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F3R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F3R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F3R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F3R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F3R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F3R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F3R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F3R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F3R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F3R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F3R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F3R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F3R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F3R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F3R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F3R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F3R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F3R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R1 register  *******************/
-#define  CAN_F4R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F4R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F4R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F4R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F4R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F4R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F4R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F4R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F4R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F4R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F4R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F4R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F4R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F4R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F4R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F4R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F4R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F4R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F4R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F4R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F4R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F4R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F4R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F4R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F4R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F4R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F4R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F4R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F4R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F4R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F4R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F4R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R1 register  *******************/
-#define  CAN_F5R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F5R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F5R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F5R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F5R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F5R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F5R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F5R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F5R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F5R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F5R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F5R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F5R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F5R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F5R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F5R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F5R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F5R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F5R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F5R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F5R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F5R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F5R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F5R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F5R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F5R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F5R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F5R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F5R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F5R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F5R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F5R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R1 register  *******************/
-#define  CAN_F6R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F6R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F6R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F6R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F6R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F6R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F6R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F6R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F6R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F6R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F6R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F6R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F6R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F6R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F6R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F6R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F6R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F6R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F6R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F6R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F6R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F6R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F6R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F6R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F6R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F6R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F6R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F6R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F6R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F6R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F6R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F6R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R1 register  *******************/
-#define  CAN_F7R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F7R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F7R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F7R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F7R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F7R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F7R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F7R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F7R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F7R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F7R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F7R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F7R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F7R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F7R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F7R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F7R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F7R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F7R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F7R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F7R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F7R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F7R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F7R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F7R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F7R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F7R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F7R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F7R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F7R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F7R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F7R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R1 register  *******************/
-#define  CAN_F8R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F8R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F8R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F8R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F8R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F8R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F8R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F8R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F8R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F8R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F8R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F8R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F8R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F8R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F8R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F8R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F8R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F8R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F8R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F8R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F8R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F8R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F8R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F8R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F8R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F8R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F8R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F8R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F8R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F8R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F8R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F8R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R1 register  *******************/
-#define  CAN_F9R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F9R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F9R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F9R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F9R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F9R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F9R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F9R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F9R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F9R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F9R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F9R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F9R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F9R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F9R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F9R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F9R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F9R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F9R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F9R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F9R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F9R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F9R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F9R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F9R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F9R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F9R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F9R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F9R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F9R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F9R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F9R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R1 register  ******************/
-#define  CAN_F10R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F10R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F10R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F10R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F10R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F10R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F10R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F10R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F10R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F10R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F10R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F10R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F10R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F10R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F10R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F10R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F10R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F10R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F10R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F10R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F10R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F10R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F10R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F10R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F10R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F10R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F10R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F10R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F10R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F10R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F10R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F10R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R1 register  ******************/
-#define  CAN_F11R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F11R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F11R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F11R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F11R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F11R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F11R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F11R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F11R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F11R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F11R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F11R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F11R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F11R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F11R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F11R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F11R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F11R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F11R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F11R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F11R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F11R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F11R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F11R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F11R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F11R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F11R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F11R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F11R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F11R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F11R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F11R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R1 register  ******************/
-#define  CAN_F12R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F12R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F12R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F12R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F12R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F12R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F12R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F12R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F12R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F12R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F12R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F12R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F12R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F12R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F12R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F12R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F12R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F12R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F12R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F12R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F12R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F12R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F12R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F12R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F12R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F12R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F12R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F12R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F12R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F12R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F12R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F12R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R1 register  ******************/
-#define  CAN_F13R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F13R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F13R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F13R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F13R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F13R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F13R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F13R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F13R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F13R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F13R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F13R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F13R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F13R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F13R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F13R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F13R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F13R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F13R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F13R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F13R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F13R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F13R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F13R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F13R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F13R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F13R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F13R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F13R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F13R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F13R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F13R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F0R2 register  *******************/
-#define  CAN_F0R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F0R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F0R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F0R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F0R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F0R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F0R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F0R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F0R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F0R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F0R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F0R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F0R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F0R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F0R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F0R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F0R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F0R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F0R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F0R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F0R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F0R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F0R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F0R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F0R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F0R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F0R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F0R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F0R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F0R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F0R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F0R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R2 register  *******************/
-#define  CAN_F1R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F1R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F1R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F1R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F1R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F1R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F1R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F1R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F1R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F1R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F1R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F1R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F1R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F1R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F1R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F1R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F1R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F1R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F1R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F1R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F1R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F1R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F1R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F1R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F1R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F1R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F1R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F1R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F1R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F1R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F1R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F1R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R2 register  *******************/
-#define  CAN_F2R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F2R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F2R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F2R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F2R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F2R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F2R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F2R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F2R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F2R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F2R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F2R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F2R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F2R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F2R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F2R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F2R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F2R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F2R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F2R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F2R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F2R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F2R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F2R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F2R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F2R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F2R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F2R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F2R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F2R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F2R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F2R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R2 register  *******************/
-#define  CAN_F3R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F3R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F3R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F3R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F3R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F3R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F3R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F3R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F3R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F3R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F3R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F3R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F3R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F3R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F3R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F3R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F3R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F3R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F3R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F3R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F3R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F3R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F3R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F3R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F3R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F3R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F3R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F3R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F3R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F3R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F3R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F3R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R2 register  *******************/
-#define  CAN_F4R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F4R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F4R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F4R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F4R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F4R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F4R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F4R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F4R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F4R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F4R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F4R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F4R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F4R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F4R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F4R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F4R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F4R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F4R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F4R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F4R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F4R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F4R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F4R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F4R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F4R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F4R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F4R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F4R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F4R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F4R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F4R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R2 register  *******************/
-#define  CAN_F5R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F5R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F5R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F5R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F5R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F5R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F5R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F5R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F5R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F5R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F5R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F5R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F5R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F5R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F5R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F5R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F5R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F5R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F5R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F5R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F5R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F5R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F5R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F5R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F5R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F5R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F5R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F5R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F5R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F5R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F5R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F5R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R2 register  *******************/
-#define  CAN_F6R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F6R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F6R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F6R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F6R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F6R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F6R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F6R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F6R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F6R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F6R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F6R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F6R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F6R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F6R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F6R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F6R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F6R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F6R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F6R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F6R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F6R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F6R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F6R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F6R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F6R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F6R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F6R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F6R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F6R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F6R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F6R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R2 register  *******************/
-#define  CAN_F7R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F7R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F7R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F7R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F7R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F7R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F7R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F7R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F7R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F7R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F7R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F7R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F7R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F7R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F7R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F7R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F7R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F7R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F7R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F7R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F7R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F7R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F7R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F7R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F7R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F7R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F7R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F7R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F7R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F7R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F7R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F7R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R2 register  *******************/
-#define  CAN_F8R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F8R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F8R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F8R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F8R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F8R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F8R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F8R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F8R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F8R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F8R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F8R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F8R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F8R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F8R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F8R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F8R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F8R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F8R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F8R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F8R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F8R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F8R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F8R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F8R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F8R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F8R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F8R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F8R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F8R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F8R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F8R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R2 register  *******************/
-#define  CAN_F9R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F9R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F9R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F9R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F9R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F9R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F9R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F9R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F9R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F9R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F9R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F9R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F9R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F9R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F9R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F9R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F9R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F9R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F9R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F9R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F9R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F9R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F9R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F9R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F9R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F9R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F9R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F9R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F9R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F9R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F9R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F9R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R2 register  ******************/
-#define  CAN_F10R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F10R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F10R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F10R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F10R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F10R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F10R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F10R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F10R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F10R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F10R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F10R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F10R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F10R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F10R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F10R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F10R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F10R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F10R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F10R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F10R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F10R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F10R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F10R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F10R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F10R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F10R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F10R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F10R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F10R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F10R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F10R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R2 register  ******************/
-#define  CAN_F11R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F11R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F11R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F11R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F11R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F11R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F11R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F11R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F11R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F11R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F11R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F11R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F11R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F11R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F11R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F11R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F11R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F11R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F11R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F11R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F11R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F11R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F11R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F11R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F11R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F11R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F11R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F11R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F11R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F11R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F11R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F11R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R2 register  ******************/
-#define  CAN_F12R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F12R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F12R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F12R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F12R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F12R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F12R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F12R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F12R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F12R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F12R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F12R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F12R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F12R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F12R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F12R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F12R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F12R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F12R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F12R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F12R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F12R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F12R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F12R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F12R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F12R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F12R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F12R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F12R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F12R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F12R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F12R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R2 register  ******************/
-#define  CAN_F13R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F13R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F13R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F13R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F13R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F13R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F13R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F13R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F13R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F13R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F13R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F13R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F13R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F13R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F13R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F13R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F13R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F13R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F13R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F13R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F13R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F13R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F13R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F13R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F13R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F13R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F13R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F13R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F13R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F13R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F13R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F13R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRC calculation unit                              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           0xFFFFFFFFU /*!< Data register bits */
-
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         0xFFU        /*!< General-purpose 8-bit data register bits */
-
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        0x01U        /*!< RESET bit */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Digital to Analog Converter                           */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DAC_CR register  ********************/
-#define  DAC_CR_EN1                          0x00000001U        /*!<DAC channel1 enable */
-#define  DAC_CR_BOFF1                        0x00000002U        /*!<DAC channel1 output buffer disable */
-#define  DAC_CR_TEN1                         0x00000004U        /*!<DAC channel1 Trigger enable */
-
-#define  DAC_CR_TSEL1                        0x00000038U        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define  DAC_CR_TSEL1_0                      0x00000008U        /*!<Bit 0 */
-#define  DAC_CR_TSEL1_1                      0x00000010U        /*!<Bit 1 */
-#define  DAC_CR_TSEL1_2                      0x00000020U        /*!<Bit 2 */
-
-#define  DAC_CR_WAVE1                        0x000000C0U        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE1_0                      0x00000040U        /*!<Bit 0 */
-#define  DAC_CR_WAVE1_1                      0x00000080U        /*!<Bit 1 */
-
-#define  DAC_CR_MAMP1                        0x00000F00U        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP1_0                      0x00000100U        /*!<Bit 0 */
-#define  DAC_CR_MAMP1_1                      0x00000200U        /*!<Bit 1 */
-#define  DAC_CR_MAMP1_2                      0x00000400U        /*!<Bit 2 */
-#define  DAC_CR_MAMP1_3                      0x00000800U        /*!<Bit 3 */
-
-#define  DAC_CR_DMAEN1                       0x00001000U        /*!<DAC channel1 DMA enable */
-#define  DAC_CR_DMAUDRIE1                    0x00002000U        /*!<DAC channel1 DMA underrun interrupt enable*/
-#define  DAC_CR_EN2                          0x00010000U        /*!<DAC channel2 enable */
-#define  DAC_CR_BOFF2                        0x00020000U        /*!<DAC channel2 output buffer disable */
-#define  DAC_CR_TEN2                         0x00040000U        /*!<DAC channel2 Trigger enable */
-
-#define  DAC_CR_TSEL2                        0x00380000U        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define  DAC_CR_TSEL2_0                      0x00080000U        /*!<Bit 0 */
-#define  DAC_CR_TSEL2_1                      0x00100000U        /*!<Bit 1 */
-#define  DAC_CR_TSEL2_2                      0x00200000U        /*!<Bit 2 */
-
-#define  DAC_CR_WAVE2                        0x00C00000U        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE2_0                      0x00400000U        /*!<Bit 0 */
-#define  DAC_CR_WAVE2_1                      0x00800000U        /*!<Bit 1 */
-
-#define  DAC_CR_MAMP2                        0x0F000000U        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP2_0                      0x01000000U        /*!<Bit 0 */
-#define  DAC_CR_MAMP2_1                      0x02000000U        /*!<Bit 1 */
-#define  DAC_CR_MAMP2_2                      0x04000000U        /*!<Bit 2 */
-#define  DAC_CR_MAMP2_3                      0x08000000U        /*!<Bit 3 */
-
-#define  DAC_CR_DMAEN2                       0x10000000U        /*!<DAC channel2 DMA enabled */
-#define  DAC_CR_DMAUDRIE2                    0x20000000U        /*!<DAC channel2 DMA underrun interrupt enable*/
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define  DAC_SWTRIGR_SWTRIG1                 0x01U               /*!<DAC channel1 software trigger */
-#define  DAC_SWTRIGR_SWTRIG2                 0x02U               /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define  DAC_DHR12R1_DACC1DHR                0x0FFFU            /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define  DAC_DHR12L1_DACC1DHR                0xFFF0U            /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define  DAC_DHR8R1_DACC1DHR                 0xFFU               /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define  DAC_DHR12R2_DACC2DHR                0x0FFFU            /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define  DAC_DHR12L2_DACC2DHR                0xFFF0U            /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define  DAC_DHR8R2_DACC2DHR                 0xFFU               /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define  DAC_DHR12RD_DACC1DHR                0x00000FFFU        /*!<DAC channel1 12-bit Right aligned data */
-#define  DAC_DHR12RD_DACC2DHR                0x0FFF0000U        /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define  DAC_DHR12LD_DACC1DHR                0x0000FFF0U        /*!<DAC channel1 12-bit Left aligned data */
-#define  DAC_DHR12LD_DACC2DHR                0xFFF00000U        /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define  DAC_DHR8RD_DACC1DHR                 0x00FFU            /*!<DAC channel1 8-bit Right aligned data */
-#define  DAC_DHR8RD_DACC2DHR                 0xFF00U            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define  DAC_DOR1_DACC1DOR                   0x0FFFU            /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define  DAC_DOR2_DACC2DOR                   0x0FFFU            /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define  DAC_SR_DMAUDR1                      0x00002000U        /*!<DAC channel1 DMA underrun flag */
-#define  DAC_SR_DMAUDR2                      0x20000000U        /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 Debug MCU                                  */
-/*                                                                            */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    DCMI                                    */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DCMI_CR register  ******************/
-#define DCMI_CR_CAPTURE                      0x00000001U
-#define DCMI_CR_CM                           0x00000002U
-#define DCMI_CR_CROP                         0x00000004U
-#define DCMI_CR_JPEG                         0x00000008U
-#define DCMI_CR_ESS                          0x00000010U
-#define DCMI_CR_PCKPOL                       0x00000020U
-#define DCMI_CR_HSPOL                        0x00000040U
-#define DCMI_CR_VSPOL                        0x00000080U
-#define DCMI_CR_FCRC_0                       0x00000100U
-#define DCMI_CR_FCRC_1                       0x00000200U
-#define DCMI_CR_EDM_0                        0x00000400U
-#define DCMI_CR_EDM_1                        0x00000800U
-#define DCMI_CR_OUTEN                        0x00002000U
-#define DCMI_CR_ENABLE                       0x00004000U
-#define DCMI_CR_BSM_0                        0x00010000U
-#define DCMI_CR_BSM_1                        0x00020000U
-#define DCMI_CR_OEBS                         0x00040000U
-#define DCMI_CR_LSM                          0x00080000U
-#define DCMI_CR_OELS                         0x00100000U
-
-/********************  Bits definition for DCMI_SR register  ******************/
-#define DCMI_SR_HSYNC                        0x00000001U
-#define DCMI_SR_VSYNC                        0x00000002U
-#define DCMI_SR_FNE                          0x00000004U
-
-/********************  Bits definition for DCMI_RIS register  *****************/
-#define DCMI_RIS_FRAME_RIS                   0x00000001U
-#define DCMI_RIS_OVR_RIS                     0x00000002U
-#define DCMI_RIS_ERR_RIS                     0x00000004U
-#define DCMI_RIS_VSYNC_RIS                   0x00000008U
-#define DCMI_RIS_LINE_RIS                    0x00000010U
-/* Legacy defines */
-#define DCMI_RISR_FRAME_RIS                  DCMI_RIS_FRAME_RIS
-#define DCMI_RISR_OVR_RIS                    DCMI_RIS_OVR_RIS
-#define DCMI_RISR_ERR_RIS                    DCMI_RIS_ERR_RIS
-#define DCMI_RISR_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS
-#define DCMI_RISR_LINE_RIS                   DCMI_RIS_LINE_RIS
-#define DCMI_RISR_OVF_RIS                    DCMI_RIS_OVR_RIS
-
-/********************  Bits definition for DCMI_IER register  *****************/
-#define DCMI_IER_FRAME_IE                    0x00000001U
-#define DCMI_IER_OVR_IE                      0x00000002U
-#define DCMI_IER_ERR_IE                      0x00000004U
-#define DCMI_IER_VSYNC_IE                    0x00000008U
-#define DCMI_IER_LINE_IE                     0x00000010U
-/* Legacy defines */
-#define DCMI_IER_OVF_IE                      DCMI_IER_OVR_IE
-/********************  Bits definition for DCMI_MIS register  *****************/
-#define DCMI_MIS_FRAME_MIS                   0x00000001U
-#define DCMI_MIS_OVR_MIS                     0x00000002U
-#define DCMI_MIS_ERR_MIS                     0x00000004U
-#define DCMI_MIS_VSYNC_MIS                   0x00000008U
-#define DCMI_MIS_LINE_MIS                    0x00000010U
-
-/* Legacy defines */
-#define DCMI_MISR_FRAME_MIS                  DCMI_MIS_FRAME_MIS
-#define DCMI_MISR_OVF_MIS                    DCMI_MIS_OVR_MIS
-#define DCMI_MISR_ERR_MIS                    DCMI_MIS_ERR_MIS
-#define DCMI_MISR_VSYNC_MIS                  DCMI_MIS_VSYNC_MIS
-#define DCMI_MISR_LINE_MIS                   DCMI_MIS_LINE_MIS
-
-/********************  Bits definition for DCMI_ICR register  *****************/
-#define DCMI_ICR_FRAME_ISC                   0x00000001U
-#define DCMI_ICR_OVR_ISC                     0x00000002U
-#define DCMI_ICR_ERR_ISC                     0x00000004U
-#define DCMI_ICR_VSYNC_ISC                   0x00000008U
-#define DCMI_ICR_LINE_ISC                    0x00000010U
-
-/* Legacy defines */
-#define DCMI_ICR_OVF_ISC                     DCMI_ICR_OVR_ISC
-
-/********************  Bits definition for DCMI_ESCR register  ******************/
-#define DCMI_ESCR_FSC                        0x000000FFU
-#define DCMI_ESCR_LSC                        0x0000FF00U
-#define DCMI_ESCR_LEC                        0x00FF0000U
-#define DCMI_ESCR_FEC                        0xFF000000U
-
-/********************  Bits definition for DCMI_ESUR register  ******************/
-#define DCMI_ESUR_FSU                        0x000000FFU
-#define DCMI_ESUR_LSU                        0x0000FF00U
-#define DCMI_ESUR_LEU                        0x00FF0000U
-#define DCMI_ESUR_FEU                        0xFF000000U
-
-/********************  Bits definition for DCMI_CWSTRT register  ******************/
-#define DCMI_CWSTRT_HOFFCNT                  0x00003FFFU
-#define DCMI_CWSTRT_VST                      0x1FFF0000U
-
-/********************  Bits definition for DCMI_CWSIZE register  ******************/
-#define DCMI_CWSIZE_CAPCNT                   0x00003FFFU
-#define DCMI_CWSIZE_VLINE                    0x3FFF0000U
-
-/********************  Bits definition for DCMI_DR register  ******************/
-#define DCMI_DR_BYTE0                        0x000000FFU
-#define DCMI_DR_BYTE1                        0x0000FF00U
-#define DCMI_DR_BYTE2                        0x00FF0000U
-#define DCMI_DR_BYTE3                        0xFF000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                             DMA Controller                                 */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DMA_SxCR register  *****************/
-#define DMA_SxCR_CHSEL                       0x0E000000U
-#define DMA_SxCR_CHSEL_0                     0x02000000U
-#define DMA_SxCR_CHSEL_1                     0x04000000U
-#define DMA_SxCR_CHSEL_2                     0x08000000U
-#define DMA_SxCR_MBURST                      0x01800000U
-#define DMA_SxCR_MBURST_0                    0x00800000U
-#define DMA_SxCR_MBURST_1                    0x01000000U
-#define DMA_SxCR_PBURST                      0x00600000U
-#define DMA_SxCR_PBURST_0                    0x00200000U
-#define DMA_SxCR_PBURST_1                    0x00400000U
-#define DMA_SxCR_CT                          0x00080000U
-#define DMA_SxCR_DBM                         0x00040000U
-#define DMA_SxCR_PL                          0x00030000U
-#define DMA_SxCR_PL_0                        0x00010000U
-#define DMA_SxCR_PL_1                        0x00020000U
-#define DMA_SxCR_PINCOS                      0x00008000U
-#define DMA_SxCR_MSIZE                       0x00006000U
-#define DMA_SxCR_MSIZE_0                     0x00002000U
-#define DMA_SxCR_MSIZE_1                     0x00004000U
-#define DMA_SxCR_PSIZE                       0x00001800U
-#define DMA_SxCR_PSIZE_0                     0x00000800U
-#define DMA_SxCR_PSIZE_1                     0x00001000U
-#define DMA_SxCR_MINC                        0x00000400U
-#define DMA_SxCR_PINC                        0x00000200U
-#define DMA_SxCR_CIRC                        0x00000100U
-#define DMA_SxCR_DIR                         0x000000C0U
-#define DMA_SxCR_DIR_0                       0x00000040U
-#define DMA_SxCR_DIR_1                       0x00000080U
-#define DMA_SxCR_PFCTRL                      0x00000020U
-#define DMA_SxCR_TCIE                        0x00000010U
-#define DMA_SxCR_HTIE                        0x00000008U
-#define DMA_SxCR_TEIE                        0x00000004U
-#define DMA_SxCR_DMEIE                       0x00000002U
-#define DMA_SxCR_EN                          0x00000001U
-
-/* Legacy defines */
-#define DMA_SxCR_ACK                         0x00100000U
-
-/********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            0x0000FFFFU
-#define DMA_SxNDT_0                          0x00000001U
-#define DMA_SxNDT_1                          0x00000002U
-#define DMA_SxNDT_2                          0x00000004U
-#define DMA_SxNDT_3                          0x00000008U
-#define DMA_SxNDT_4                          0x00000010U
-#define DMA_SxNDT_5                          0x00000020U
-#define DMA_SxNDT_6                          0x00000040U
-#define DMA_SxNDT_7                          0x00000080U
-#define DMA_SxNDT_8                          0x00000100U
-#define DMA_SxNDT_9                          0x00000200U
-#define DMA_SxNDT_10                         0x00000400U
-#define DMA_SxNDT_11                         0x00000800U
-#define DMA_SxNDT_12                         0x00001000U
-#define DMA_SxNDT_13                         0x00002000U
-#define DMA_SxNDT_14                         0x00004000U
-#define DMA_SxNDT_15                         0x00008000U
-
-/********************  Bits definition for DMA_SxFCR register  ****************/ 
-#define DMA_SxFCR_FEIE                       0x00000080U
-#define DMA_SxFCR_FS                         0x00000038U
-#define DMA_SxFCR_FS_0                       0x00000008U
-#define DMA_SxFCR_FS_1                       0x00000010U
-#define DMA_SxFCR_FS_2                       0x00000020U
-#define DMA_SxFCR_DMDIS                      0x00000004U
-#define DMA_SxFCR_FTH                        0x00000003U
-#define DMA_SxFCR_FTH_0                      0x00000001U
-#define DMA_SxFCR_FTH_1                      0x00000002U
-
-/********************  Bits definition for DMA_LISR register  *****************/ 
-#define DMA_LISR_TCIF3                       0x08000000U
-#define DMA_LISR_HTIF3                       0x04000000U
-#define DMA_LISR_TEIF3                       0x02000000U
-#define DMA_LISR_DMEIF3                      0x01000000U
-#define DMA_LISR_FEIF3                       0x00400000U
-#define DMA_LISR_TCIF2                       0x00200000U
-#define DMA_LISR_HTIF2                       0x00100000U
-#define DMA_LISR_TEIF2                       0x00080000U
-#define DMA_LISR_DMEIF2                      0x00040000U
-#define DMA_LISR_FEIF2                       0x00010000U
-#define DMA_LISR_TCIF1                       0x00000800U
-#define DMA_LISR_HTIF1                       0x00000400U
-#define DMA_LISR_TEIF1                       0x00000200U
-#define DMA_LISR_DMEIF1                      0x00000100U
-#define DMA_LISR_FEIF1                       0x00000040U
-#define DMA_LISR_TCIF0                       0x00000020U
-#define DMA_LISR_HTIF0                       0x00000010U
-#define DMA_LISR_TEIF0                       0x00000008U
-#define DMA_LISR_DMEIF0                      0x00000004U
-#define DMA_LISR_FEIF0                       0x00000001U
-
-/********************  Bits definition for DMA_HISR register  *****************/ 
-#define DMA_HISR_TCIF7                       0x08000000U
-#define DMA_HISR_HTIF7                       0x04000000U
-#define DMA_HISR_TEIF7                       0x02000000U
-#define DMA_HISR_DMEIF7                      0x01000000U
-#define DMA_HISR_FEIF7                       0x00400000U
-#define DMA_HISR_TCIF6                       0x00200000U
-#define DMA_HISR_HTIF6                       0x00100000U
-#define DMA_HISR_TEIF6                       0x00080000U
-#define DMA_HISR_DMEIF6                      0x00040000U
-#define DMA_HISR_FEIF6                       0x00010000U
-#define DMA_HISR_TCIF5                       0x00000800U
-#define DMA_HISR_HTIF5                       0x00000400U
-#define DMA_HISR_TEIF5                       0x00000200U
-#define DMA_HISR_DMEIF5                      0x00000100U
-#define DMA_HISR_FEIF5                       0x00000040U
-#define DMA_HISR_TCIF4                       0x00000020U
-#define DMA_HISR_HTIF4                       0x00000010U
-#define DMA_HISR_TEIF4                       0x00000008U
-#define DMA_HISR_DMEIF4                      0x00000004U
-#define DMA_HISR_FEIF4                       0x00000001U
-
-/********************  Bits definition for DMA_LIFCR register  ****************/ 
-#define DMA_LIFCR_CTCIF3                     0x08000000U
-#define DMA_LIFCR_CHTIF3                     0x04000000U
-#define DMA_LIFCR_CTEIF3                     0x02000000U
-#define DMA_LIFCR_CDMEIF3                    0x01000000U
-#define DMA_LIFCR_CFEIF3                     0x00400000U
-#define DMA_LIFCR_CTCIF2                     0x00200000U
-#define DMA_LIFCR_CHTIF2                     0x00100000U
-#define DMA_LIFCR_CTEIF2                     0x00080000U
-#define DMA_LIFCR_CDMEIF2                    0x00040000U
-#define DMA_LIFCR_CFEIF2                     0x00010000U
-#define DMA_LIFCR_CTCIF1                     0x00000800U
-#define DMA_LIFCR_CHTIF1                     0x00000400U
-#define DMA_LIFCR_CTEIF1                     0x00000200U
-#define DMA_LIFCR_CDMEIF1                    0x00000100U
-#define DMA_LIFCR_CFEIF1                     0x00000040U
-#define DMA_LIFCR_CTCIF0                     0x00000020U
-#define DMA_LIFCR_CHTIF0                     0x00000010U
-#define DMA_LIFCR_CTEIF0                     0x00000008U
-#define DMA_LIFCR_CDMEIF0                    0x00000004U
-#define DMA_LIFCR_CFEIF0                     0x00000001U
-
-/********************  Bits definition for DMA_HIFCR  register  ****************/ 
-#define DMA_HIFCR_CTCIF7                     0x08000000U
-#define DMA_HIFCR_CHTIF7                     0x04000000U
-#define DMA_HIFCR_CTEIF7                     0x02000000U
-#define DMA_HIFCR_CDMEIF7                    0x01000000U
-#define DMA_HIFCR_CFEIF7                     0x00400000U
-#define DMA_HIFCR_CTCIF6                     0x00200000U
-#define DMA_HIFCR_CHTIF6                     0x00100000U
-#define DMA_HIFCR_CTEIF6                     0x00080000U
-#define DMA_HIFCR_CDMEIF6                    0x00040000U
-#define DMA_HIFCR_CFEIF6                     0x00010000U
-#define DMA_HIFCR_CTCIF5                     0x00000800U
-#define DMA_HIFCR_CHTIF5                     0x00000400U
-#define DMA_HIFCR_CTEIF5                     0x00000200U
-#define DMA_HIFCR_CDMEIF5                    0x00000100U
-#define DMA_HIFCR_CFEIF5                     0x00000040U
-#define DMA_HIFCR_CTCIF4                     0x00000020U
-#define DMA_HIFCR_CHTIF4                     0x00000010U
-#define DMA_HIFCR_CTEIF4                     0x00000008U
-#define DMA_HIFCR_CDMEIF4                    0x00000004U
-#define DMA_HIFCR_CFEIF4                     0x00000001U
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                         AHB Master DMA2D Controller (DMA2D)                */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for DMA2D_CR register  ******************/
-
-#define DMA2D_CR_START                     0x00000001U               /*!< Start transfer */
-#define DMA2D_CR_SUSP                      0x00000002U               /*!< Suspend transfer */
-#define DMA2D_CR_ABORT                     0x00000004U               /*!< Abort transfer */
-#define DMA2D_CR_TEIE                      0x00000100U               /*!< Transfer Error Interrupt Enable */
-#define DMA2D_CR_TCIE                      0x00000200U               /*!< Transfer Complete Interrupt Enable */
-#define DMA2D_CR_TWIE                      0x00000400U               /*!< Transfer Watermark Interrupt Enable */
-#define DMA2D_CR_CAEIE                     0x00000800U               /*!< CLUT Access Error Interrupt Enable */
-#define DMA2D_CR_CTCIE                     0x00001000U               /*!< CLUT Transfer Complete Interrupt Enable */
-#define DMA2D_CR_CEIE                      0x00002000U               /*!< Configuration Error Interrupt Enable */
-#define DMA2D_CR_MODE                      0x00030000U               /*!< DMA2D Mode[1:0] */
-#define DMA2D_CR_MODE_0                    0x00010000U               /*!< DMA2D Mode bit 0 */
-#define DMA2D_CR_MODE_1                    0x00020000U               /*!< DMA2D Mode bit 1 */
-
-/********************  Bit definition for DMA2D_ISR register  *****************/
-
-#define DMA2D_ISR_TEIF                     0x00000001U               /*!< Transfer Error Interrupt Flag */
-#define DMA2D_ISR_TCIF                     0x00000002U               /*!< Transfer Complete Interrupt Flag */
-#define DMA2D_ISR_TWIF                     0x00000004U               /*!< Transfer Watermark Interrupt Flag */
-#define DMA2D_ISR_CAEIF                    0x00000008U               /*!< CLUT Access Error Interrupt Flag */
-#define DMA2D_ISR_CTCIF                    0x00000010U               /*!< CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_ISR_CEIF                     0x00000020U               /*!< Configuration Error Interrupt Flag */
-
-/********************  Bit definition for DMA2D_IFCR register  ****************/
-
-#define DMA2D_IFCR_CTEIF                   0x00000001U               /*!< Clears Transfer Error Interrupt Flag         */
-#define DMA2D_IFCR_CTCIF                   0x00000002U               /*!< Clears Transfer Complete Interrupt Flag      */
-#define DMA2D_IFCR_CTWIF                   0x00000004U               /*!< Clears Transfer Watermark Interrupt Flag     */
-#define DMA2D_IFCR_CAECIF                  0x00000008U               /*!< Clears CLUT Access Error Interrupt Flag      */
-#define DMA2D_IFCR_CCTCIF                  0x00000010U               /*!< Clears CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_IFCR_CCEIF                   0x00000020U               /*!< Clears Configuration Error Interrupt Flag    */
-
-/* Legacy defines */
-#define DMA2D_IFSR_CTEIF                   DMA2D_IFCR_CTEIF                     /*!< Clears Transfer Error Interrupt Flag         */
-#define DMA2D_IFSR_CTCIF                   DMA2D_IFCR_CTCIF                     /*!< Clears Transfer Complete Interrupt Flag      */
-#define DMA2D_IFSR_CTWIF                   DMA2D_IFCR_CTWIF                     /*!< Clears Transfer Watermark Interrupt Flag     */
-#define DMA2D_IFSR_CCAEIF                  DMA2D_IFCR_CAECIF                    /*!< Clears CLUT Access Error Interrupt Flag      */
-#define DMA2D_IFSR_CCTCIF                  DMA2D_IFCR_CCTCIF                    /*!< Clears CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_IFSR_CCEIF                   DMA2D_IFCR_CCEIF                     /*!< Clears Configuration Error Interrupt Flag    */
-
-/********************  Bit definition for DMA2D_FGMAR register  ***************/
-
-#define DMA2D_FGMAR_MA                     0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_FGOR register  ****************/
-
-#define DMA2D_FGOR_LO                      0x00003FFFU               /*!< Line Offset */
-
-/********************  Bit definition for DMA2D_BGMAR register  ***************/
-
-#define DMA2D_BGMAR_MA                     0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_BGOR register  ****************/
-
-#define DMA2D_BGOR_LO                      0x00003FFFU               /*!< Line Offset */
-
-/********************  Bit definition for DMA2D_FGPFCCR register  *************/
-
-#define DMA2D_FGPFCCR_CM                   0x0000000FU               /*!< Input color mode CM[3:0] */
-#define DMA2D_FGPFCCR_CM_0                 0x00000001U               /*!< Input color mode CM bit 0 */
-#define DMA2D_FGPFCCR_CM_1                 0x00000002U               /*!< Input color mode CM bit 1 */
-#define DMA2D_FGPFCCR_CM_2                 0x00000004U               /*!< Input color mode CM bit 2 */
-#define DMA2D_FGPFCCR_CM_3                 0x00000008U               /*!< Input color mode CM bit 3 */
-#define DMA2D_FGPFCCR_CCM                  0x00000010U               /*!< CLUT Color mode */
-#define DMA2D_FGPFCCR_START                0x00000020U               /*!< Start */
-#define DMA2D_FGPFCCR_CS                   0x0000FF00U               /*!< CLUT size */
-#define DMA2D_FGPFCCR_AM                   0x00030000U               /*!< Alpha mode AM[1:0] */
-#define DMA2D_FGPFCCR_AM_0                 0x00010000U               /*!< Alpha mode AM bit 0 */
-#define DMA2D_FGPFCCR_AM_1                 0x00020000U               /*!< Alpha mode AM bit 1 */
-#define DMA2D_FGPFCCR_ALPHA                0xFF000000U               /*!< Alpha value */
-
-/********************  Bit definition for DMA2D_FGCOLR register  **************/
-
-#define DMA2D_FGCOLR_BLUE                  0x000000FFU               /*!< Blue Value */
-#define DMA2D_FGCOLR_GREEN                 0x0000FF00U               /*!< Green Value */
-#define DMA2D_FGCOLR_RED                   0x00FF0000U               /*!< Red Value */   
-
-/********************  Bit definition for DMA2D_BGPFCCR register  *************/
-
-#define DMA2D_BGPFCCR_CM                   0x0000000FU               /*!< Input color mode CM[3:0] */
-#define DMA2D_BGPFCCR_CM_0                 0x00000001U               /*!< Input color mode CM bit 0 */
-#define DMA2D_BGPFCCR_CM_1                 0x00000002U               /*!< Input color mode CM bit 1 */
-#define DMA2D_BGPFCCR_CM_2                 0x00000004U               /*!< Input color mode CM bit 2 */
-#define DMA2D_FGPFCCR_CM_3                 0x00000008U               /*!< Input color mode CM bit 3 */
-#define DMA2D_BGPFCCR_CCM                  0x00000010U               /*!< CLUT Color mode */
-#define DMA2D_BGPFCCR_START                0x00000020U               /*!< Start */
-#define DMA2D_BGPFCCR_CS                   0x0000FF00U               /*!< CLUT size */
-#define DMA2D_BGPFCCR_AM                   0x00030000U               /*!< Alpha mode AM[1:0] */
-#define DMA2D_BGPFCCR_AM_0                 0x00010000U               /*!< Alpha mode AM bit 0 */
-#define DMA2D_BGPFCCR_AM_1                 0x00020000U               /*!< Alpha mode AM bit 1 */
-#define DMA2D_BGPFCCR_ALPHA                0xFF000000U               /*!< background Input Alpha value */
-
-/********************  Bit definition for DMA2D_BGCOLR register  **************/
-
-#define DMA2D_BGCOLR_BLUE                  0x000000FFU               /*!< Blue Value */
-#define DMA2D_BGCOLR_GREEN                 0x0000FF00U               /*!< Green Value */
-#define DMA2D_BGCOLR_RED                   0x00FF0000U               /*!< Red Value */
-
-/********************  Bit definition for DMA2D_FGCMAR register  **************/
-
-#define DMA2D_FGCMAR_MA                    0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_BGCMAR register  **************/
-
-#define DMA2D_BGCMAR_MA                    0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_OPFCCR register  **************/
-
-#define DMA2D_OPFCCR_CM                    0x00000007U               /*!< Color mode CM[2:0] */
-#define DMA2D_OPFCCR_CM_0                  0x00000001U               /*!< Color mode CM bit 0 */
-#define DMA2D_OPFCCR_CM_1                  0x00000002U               /*!< Color mode CM bit 1 */
-#define DMA2D_OPFCCR_CM_2                  0x00000004U               /*!< Color mode CM bit 2 */
-
-/********************  Bit definition for DMA2D_OCOLR register  ***************/
-
-/*!<Mode_ARGB8888/RGB888 */
-
-#define DMA2D_OCOLR_BLUE_1                 0x000000FFU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_1                0x0000FF00U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_1                  0x00FF0000U               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_1                0xFF000000U               /*!< Alpha Channel Value */
-
-/*!<Mode_RGB565 */
-#define DMA2D_OCOLR_BLUE_2                 0x0000001FU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_2                0x000007E0U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_2                  0x0000F800U               /*!< Red Value */
-
-/*!<Mode_ARGB1555 */
-#define DMA2D_OCOLR_BLUE_3                 0x0000001FU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_3                0x000003E0U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_3                  0x00007C00U               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_3                0x00008000U               /*!< Alpha Channel Value */
-
-/*!<Mode_ARGB4444 */
-#define DMA2D_OCOLR_BLUE_4                 0x0000000FU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_4                0x000000F0U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_4                  0x00000F00U               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_4                0x0000F000U               /*!< Alpha Channel Value */
-
-/********************  Bit definition for DMA2D_OMAR register  ****************/
-
-#define DMA2D_OMAR_MA                      0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_OOR register  *****************/
-
-#define DMA2D_OOR_LO                       0x00003FFFU               /*!< Line Offset */
-
-/********************  Bit definition for DMA2D_NLR register  *****************/
-
-#define DMA2D_NLR_NL                       0x0000FFFFU               /*!< Number of Lines */
-#define DMA2D_NLR_PL                       0x3FFF0000U               /*!< Pixel per Lines */
-
-/********************  Bit definition for DMA2D_LWR register  *****************/
-
-#define DMA2D_LWR_LW                       0x0000FFFFU               /*!< Line Watermark */
-
-/********************  Bit definition for DMA2D_AMTCR register  ***************/
-
-#define DMA2D_AMTCR_EN                     0x00000001U               /*!< Enable */
-#define DMA2D_AMTCR_DT                     0x0000FF00U               /*!< Dead Time */
-
-/********************  Bit definition for DMA2D_FGCLUT register  **************/
-                                                                     
-/********************  Bit definition for DMA2D_BGCLUT register  **************/
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Display Serial Interface (DSI)                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for DSI_VR register  *****************/
-#define DSI_VR                         0x3133302AU               /*!< DSI Host Version */
-
-/*******************  Bit definition for DSI_CR register  *****************/
-#define DSI_CR_EN                      0x00000001U               /*!< DSI Host power up and reset */
-
-/*******************  Bit definition for DSI_CCR register  ****************/
-#define DSI_CCR_TXECKDIV               0x000000FFU               /*!< TX Escape Clock Division */
-#define DSI_CCR_TXECKDIV0              0x00000001U
-#define DSI_CCR_TXECKDIV1              0x00000002U
-#define DSI_CCR_TXECKDIV2              0x00000004U
-#define DSI_CCR_TXECKDIV3              0x00000008U
-#define DSI_CCR_TXECKDIV4              0x00000010U
-#define DSI_CCR_TXECKDIV5              0x00000020U
-#define DSI_CCR_TXECKDIV6              0x00000040U
-#define DSI_CCR_TXECKDIV7              0x00000080U
-
-#define DSI_CCR_TOCKDIV                0x0000FF00U               /*!< Timeout Clock Division */
-#define DSI_CCR_TOCKDIV0               0x00000100U
-#define DSI_CCR_TOCKDIV1               0x00000200U
-#define DSI_CCR_TOCKDIV2               0x00000400U
-#define DSI_CCR_TOCKDIV3               0x00000800U
-#define DSI_CCR_TOCKDIV4               0x00001000U
-#define DSI_CCR_TOCKDIV5               0x00002000U
-#define DSI_CCR_TOCKDIV6               0x00004000U
-#define DSI_CCR_TOCKDIV7               0x00008000U
-
-/*******************  Bit definition for DSI_LVCIDR register  *************/
-#define DSI_LVCIDR_VCID                0x00000003U               /*!< Virtual Channel ID */
-#define DSI_LVCIDR_VCID0               0x00000001U
-#define DSI_LVCIDR_VCID1               0x00000002U
-
-/*******************  Bit definition for DSI_LCOLCR register  *************/
-#define DSI_LCOLCR_COLC                0x0000000FU               /*!< Color Coding */
-#define DSI_LCOLCR_COLC0               0x00000001U
-#define DSI_LCOLCR_COLC1               0x00000020U
-#define DSI_LCOLCR_COLC2               0x00000040U
-#define DSI_LCOLCR_COLC3               0x00000080U
-
-#define DSI_LCOLCR_LPE                 0x00000100U               /*!< Loosly Packet Enable */
-
-/*******************  Bit definition for DSI_LPCR register  ***************/
-#define DSI_LPCR_DEP                   0x00000001U               /*!< Data Enable Polarity */
-#define DSI_LPCR_VSP                   0x00000002U               /*!< VSYNC Polarity */
-#define DSI_LPCR_HSP                   0x00000004U               /*!< HSYNC Polarity */
-
-/*******************  Bit definition for DSI_LPMCR register  **************/
-#define DSI_LPMCR_VLPSIZE              0x000000FFU               /*!< VACT Largest Packet Size */
-#define DSI_LPMCR_VLPSIZE0             0x00000001U
-#define DSI_LPMCR_VLPSIZE1             0x00000002U
-#define DSI_LPMCR_VLPSIZE2             0x00000004U
-#define DSI_LPMCR_VLPSIZE3             0x00000008U
-#define DSI_LPMCR_VLPSIZE4             0x00000010U
-#define DSI_LPMCR_VLPSIZE5             0x00000020U
-#define DSI_LPMCR_VLPSIZE6             0x00000040U
-#define DSI_LPMCR_VLPSIZE7             0x00000080U
-
-#define DSI_LPMCR_LPSIZE               0x00FF0000U               /*!< Largest Packet Size */
-#define DSI_LPMCR_LPSIZE0              0x00010000U
-#define DSI_LPMCR_LPSIZE1              0x00020000U
-#define DSI_LPMCR_LPSIZE2              0x00040000U
-#define DSI_LPMCR_LPSIZE3              0x00080000U
-#define DSI_LPMCR_LPSIZE4              0x00100000U
-#define DSI_LPMCR_LPSIZE5              0x00200000U
-#define DSI_LPMCR_LPSIZE6              0x00400000U
-#define DSI_LPMCR_LPSIZE7              0x00800000U
-
-/*******************  Bit definition for DSI_PCR register  ****************/
-#define DSI_PCR_ETTXE                  0x00000001U               /*!< EoTp Transmission Enable */
-#define DSI_PCR_ETRXE                  0x00000002U               /*!< EoTp Reception Enable */
-#define DSI_PCR_BTAE                   0x00000004U               /*!< Bus Turn Around Enable */
-#define DSI_PCR_ECCRXE                 0x00000008U               /*!< ECC Reception Enable */
-#define DSI_PCR_CRCRXE                 0x00000010U               /*!< CRC Reception Enable */
-
-/*******************  Bit definition for DSI_GVCIDR register  *************/
-#define DSI_GVCIDR_VCID                0x00000003U               /*!< Virtual Channel ID */
-#define DSI_GVCIDR_VCID0               0x00000001U
-#define DSI_GVCIDR_VCID1               0x00000002U
-
-/*******************  Bit definition for DSI_MCR register  ****************/
-#define DSI_MCR_CMDM                   0x00000001U               /*!< Command Mode */
-
-/*******************  Bit definition for DSI_VMCR register  ***************/
-#define DSI_VMCR_VMT                   0x00000003U               /*!< Video Mode Type */
-#define DSI_VMCR_VMT0                  0x00000001U
-#define DSI_VMCR_VMT1                  0x00000002U
-
-#define DSI_VMCR_LPVSAE                0x00000100U               /*!< Low-Power Vertical Sync Active Enable */
-#define DSI_VMCR_LPVBPE                0x00000200U               /*!< Low-power Vertical Back-Porch Enable */
-#define DSI_VMCR_LPVFPE                0x00000400U               /*!< Low-power Vertical Front-porch Enable */
-#define DSI_VMCR_LPVAE                 0x00000800U               /*!< Low-Power Vertical Active Enable */
-#define DSI_VMCR_LPHBPE                0x00001000U               /*!< Low-Power Horizontal Back-Porch Enable */
-#define DSI_VMCR_LPHFPE                0x00002000U               /*!< Low-Power Horizontal Front-Porch Enable */
-#define DSI_VMCR_FBTAAE                0x00004000U               /*!< Frame Bus-Turn-Around Acknowledge Enable */
-#define DSI_VMCR_LPCE                  0x00008000U               /*!< Low-Power Command Enable */
-#define DSI_VMCR_PGE                   0x00010000U               /*!< Pattern Generator Enable */
-#define DSI_VMCR_PGM                   0x00100000U               /*!< Pattern Generator Mode */
-#define DSI_VMCR_PGO                   0x01000000U               /*!< Pattern Generator Orientation */
-
-/*******************  Bit definition for DSI_VPCR register  ***************/
-#define DSI_VPCR_VPSIZE                0x00003FFFU               /*!< Video Packet Size */
-#define DSI_VPCR_VPSIZE0               0x00000001U
-#define DSI_VPCR_VPSIZE1               0x00000002U
-#define DSI_VPCR_VPSIZE2               0x00000004U
-#define DSI_VPCR_VPSIZE3               0x00000008U
-#define DSI_VPCR_VPSIZE4               0x00000010U
-#define DSI_VPCR_VPSIZE5               0x00000020U
-#define DSI_VPCR_VPSIZE6               0x00000040U
-#define DSI_VPCR_VPSIZE7               0x00000080U
-#define DSI_VPCR_VPSIZE8               0x00000100U
-#define DSI_VPCR_VPSIZE9               0x00000200U
-#define DSI_VPCR_VPSIZE10              0x00000400U
-#define DSI_VPCR_VPSIZE11              0x00000800U
-#define DSI_VPCR_VPSIZE12              0x00001000U
-#define DSI_VPCR_VPSIZE13              0x00002000U
-
-/*******************  Bit definition for DSI_VCCR register  ***************/
-#define DSI_VCCR_NUMC                  0x00001FFFU               /*!< Number of Chunks */
-#define DSI_VCCR_NUMC0                 0x00000001U
-#define DSI_VCCR_NUMC1                 0x00000002U
-#define DSI_VCCR_NUMC2                 0x00000004U
-#define DSI_VCCR_NUMC3                 0x00000008U
-#define DSI_VCCR_NUMC4                 0x00000010U
-#define DSI_VCCR_NUMC5                 0x00000020U
-#define DSI_VCCR_NUMC6                 0x00000040U
-#define DSI_VCCR_NUMC7                 0x00000080U
-#define DSI_VCCR_NUMC8                 0x00000100U
-#define DSI_VCCR_NUMC9                 0x00000200U
-#define DSI_VCCR_NUMC10                0x00000400U
-#define DSI_VCCR_NUMC11                0x00000800U
-#define DSI_VCCR_NUMC12                0x00001000U
-
-/*******************  Bit definition for DSI_VNPCR register  **************/
-#define DSI_VNPCR_NPSIZE               0x00001FFFU               /*!< Null Packet Size */
-#define DSI_VNPCR_NPSIZE0              0x00000001U
-#define DSI_VNPCR_NPSIZE1              0x00000002U
-#define DSI_VNPCR_NPSIZE2              0x00000004U
-#define DSI_VNPCR_NPSIZE3              0x00000008U
-#define DSI_VNPCR_NPSIZE4              0x00000010U
-#define DSI_VNPCR_NPSIZE5              0x00000020U
-#define DSI_VNPCR_NPSIZE6              0x00000040U
-#define DSI_VNPCR_NPSIZE7              0x00000080U
-#define DSI_VNPCR_NPSIZE8              0x00000100U
-#define DSI_VNPCR_NPSIZE9              0x00000200U
-#define DSI_VNPCR_NPSIZE10             0x00000400U
-#define DSI_VNPCR_NPSIZE11             0x00000800U
-#define DSI_VNPCR_NPSIZE12             0x00001000U
-
-/*******************  Bit definition for DSI_VHSACR register  *************/
-#define DSI_VHSACR_HSA                 0x00000FFFU               /*!< Horizontal Synchronism Active duration */
-#define DSI_VHSACR_HSA0                0x00000001U
-#define DSI_VHSACR_HSA1                0x00000002U
-#define DSI_VHSACR_HSA2                0x00000004U
-#define DSI_VHSACR_HSA3                0x00000008U
-#define DSI_VHSACR_HSA4                0x00000010U
-#define DSI_VHSACR_HSA5                0x00000020U
-#define DSI_VHSACR_HSA6                0x00000040U
-#define DSI_VHSACR_HSA7                0x00000080U
-#define DSI_VHSACR_HSA8                0x00000100U
-#define DSI_VHSACR_HSA9                0x00000200U
-#define DSI_VHSACR_HSA10               0x00000400U
-#define DSI_VHSACR_HSA11               0x00000800U
-
-/*******************  Bit definition for DSI_VHBPCR register  *************/
-#define DSI_VHBPCR_HBP                 0x00000FFFU               /*!< Horizontal Back-Porch duration */
-#define DSI_VHBPCR_HBP0                0x00000001U
-#define DSI_VHBPCR_HBP1                0x00000002U
-#define DSI_VHBPCR_HBP2                0x00000004U
-#define DSI_VHBPCR_HBP3                0x00000008U
-#define DSI_VHBPCR_HBP4                0x00000010U
-#define DSI_VHBPCR_HBP5                0x00000020U
-#define DSI_VHBPCR_HBP6                0x00000040U
-#define DSI_VHBPCR_HBP7                0x00000080U
-#define DSI_VHBPCR_HBP8                0x00000100U
-#define DSI_VHBPCR_HBP9                0x00000200U
-#define DSI_VHBPCR_HBP10               0x00000400U
-#define DSI_VHBPCR_HBP11               0x00000800U
-
-/*******************  Bit definition for DSI_VLCR register  ***************/
-#define DSI_VLCR_HLINE                 0x00007FFFU               /*!< Horizontal Line duration */
-#define DSI_VLCR_HLINE0                0x00000001U
-#define DSI_VLCR_HLINE1                0x00000002U
-#define DSI_VLCR_HLINE2                0x00000004U
-#define DSI_VLCR_HLINE3                0x00000008U
-#define DSI_VLCR_HLINE4                0x00000010U
-#define DSI_VLCR_HLINE5                0x00000020U
-#define DSI_VLCR_HLINE6                0x00000040U
-#define DSI_VLCR_HLINE7                0x00000080U
-#define DSI_VLCR_HLINE8                0x00000100U
-#define DSI_VLCR_HLINE9                0x00000200U
-#define DSI_VLCR_HLINE10               0x00000400U
-#define DSI_VLCR_HLINE11               0x00000800U
-#define DSI_VLCR_HLINE12               0x00001000U
-#define DSI_VLCR_HLINE13               0x00002000U
-#define DSI_VLCR_HLINE14               0x00004000U
-
-/*******************  Bit definition for DSI_VVSACR register  *************/
-#define DSI_VVSACR_VSA                 0x000003FFU               /*!< Vertical Synchronism Active duration */
-#define DSI_VVSACR_VSA0                0x00000001U
-#define DSI_VVSACR_VSA1                0x00000002U
-#define DSI_VVSACR_VSA2                0x00000004U
-#define DSI_VVSACR_VSA3                0x00000008U
-#define DSI_VVSACR_VSA4                0x00000010U
-#define DSI_VVSACR_VSA5                0x00000020U
-#define DSI_VVSACR_VSA6                0x00000040U
-#define DSI_VVSACR_VSA7                0x00000080U
-#define DSI_VVSACR_VSA8                0x00000100U
-#define DSI_VVSACR_VSA9                0x00000200U
-
-/*******************  Bit definition for DSI_VVBPCR register  *************/
-#define DSI_VVBPCR_VBP                 0x000003FFU               /*!< Vertical Back-Porch duration */
-#define DSI_VVBPCR_VBP0                0x00000001U
-#define DSI_VVBPCR_VBP1                0x00000002U
-#define DSI_VVBPCR_VBP2                0x00000004U
-#define DSI_VVBPCR_VBP3                0x00000008U
-#define DSI_VVBPCR_VBP4                0x00000010U
-#define DSI_VVBPCR_VBP5                0x00000020U
-#define DSI_VVBPCR_VBP6                0x00000040U
-#define DSI_VVBPCR_VBP7                0x00000080U
-#define DSI_VVBPCR_VBP8                0x00000100U
-#define DSI_VVBPCR_VBP9                0x00000200U
-
-/*******************  Bit definition for DSI_VVFPCR register  *************/
-#define DSI_VVFPCR_VFP                 0x000003FFU               /*!< Vertical Front-Porch duration */
-#define DSI_VVFPCR_VFP0                0x00000001U
-#define DSI_VVFPCR_VFP1                0x00000002U
-#define DSI_VVFPCR_VFP2                0x00000004U
-#define DSI_VVFPCR_VFP3                0x00000008U
-#define DSI_VVFPCR_VFP4                0x00000010U
-#define DSI_VVFPCR_VFP5                0x00000020U
-#define DSI_VVFPCR_VFP6                0x00000040U
-#define DSI_VVFPCR_VFP7                0x00000080U
-#define DSI_VVFPCR_VFP8                0x00000100U
-#define DSI_VVFPCR_VFP9                0x00000200U
-
-/*******************  Bit definition for DSI_VVACR register  **************/
-#define DSI_VVACR_VA                   0x00003FFFU               /*!< Vertical Active duration */
-#define DSI_VVACR_VA0                  0x00000001U
-#define DSI_VVACR_VA1                  0x00000002U
-#define DSI_VVACR_VA2                  0x00000004U
-#define DSI_VVACR_VA3                  0x00000008U
-#define DSI_VVACR_VA4                  0x00000010U
-#define DSI_VVACR_VA5                  0x00000020U
-#define DSI_VVACR_VA6                  0x00000040U
-#define DSI_VVACR_VA7                  0x00000080U
-#define DSI_VVACR_VA8                  0x00000100U
-#define DSI_VVACR_VA9                  0x00000200U
-#define DSI_VVACR_VA10                 0x00000400U
-#define DSI_VVACR_VA11                 0x00000800U
-#define DSI_VVACR_VA12                 0x00001000U
-#define DSI_VVACR_VA13                 0x00002000U
-
-/*******************  Bit definition for DSI_LCCR register  ***************/
-#define DSI_LCCR_CMDSIZE               0x0000FFFFU               /*!< Command Size */
-#define DSI_LCCR_CMDSIZE0              0x00000001U
-#define DSI_LCCR_CMDSIZE1              0x00000002U
-#define DSI_LCCR_CMDSIZE2              0x00000004U
-#define DSI_LCCR_CMDSIZE3              0x00000008U
-#define DSI_LCCR_CMDSIZE4              0x00000010U
-#define DSI_LCCR_CMDSIZE5              0x00000020U
-#define DSI_LCCR_CMDSIZE6              0x00000040U
-#define DSI_LCCR_CMDSIZE7              0x00000080U
-#define DSI_LCCR_CMDSIZE8              0x00000100U
-#define DSI_LCCR_CMDSIZE9              0x00000200U
-#define DSI_LCCR_CMDSIZE10             0x00000400U
-#define DSI_LCCR_CMDSIZE11             0x00000800U
-#define DSI_LCCR_CMDSIZE12             0x00001000U
-#define DSI_LCCR_CMDSIZE13             0x00002000U
-#define DSI_LCCR_CMDSIZE14             0x00004000U
-#define DSI_LCCR_CMDSIZE15             0x00008000U
-
-/*******************  Bit definition for DSI_CMCR register  ***************/
-#define DSI_CMCR_TEARE                 0x00000001U               /*!< Tearing Effect Acknowledge Request Enable */
-#define DSI_CMCR_ARE                   0x00000002U               /*!< Acknowledge Request Enable */
-#define DSI_CMCR_GSW0TX                0x00000100U               /*!< Generic Short Write Zero parameters Transmission */
-#define DSI_CMCR_GSW1TX                0x00000200U               /*!< Generic Short Write One parameters Transmission */
-#define DSI_CMCR_GSW2TX                0x00000400U               /*!< Generic Short Write Two parameters Transmission */
-#define DSI_CMCR_GSR0TX                0x00000800U               /*!< Generic Short Read Zero parameters Transmission */
-#define DSI_CMCR_GSR1TX                0x00001000U               /*!< Generic Short Read One parameters Transmission */
-#define DSI_CMCR_GSR2TX                0x00002000U               /*!< Generic Short Read Two parameters Transmission */
-#define DSI_CMCR_GLWTX                 0x00004000U               /*!< Generic Long Write Transmission */
-#define DSI_CMCR_DSW0TX                0x00010000U               /*!< DCS Short Write Zero parameter Transmission */
-#define DSI_CMCR_DSW1TX                0x00020000U               /*!< DCS Short Read One parameter Transmission */
-#define DSI_CMCR_DSR0TX                0x00040000U               /*!< DCS Short Read Zero parameter Transmission */
-#define DSI_CMCR_DLWTX                 0x00080000U               /*!< DCS Long Write Transmission */
-#define DSI_CMCR_MRDPS                 0x01000000U               /*!< Maximum Read Packet Size */
-
-/*******************  Bit definition for DSI_GHCR register  ***************/
-#define DSI_GHCR_DT                    0x0000003FU               /*!< Type */
-#define DSI_GHCR_DT0                   0x00000001U
-#define DSI_GHCR_DT1                   0x00000002U
-#define DSI_GHCR_DT2                   0x00000004U
-#define DSI_GHCR_DT3                   0x00000008U
-#define DSI_GHCR_DT4                   0x00000010U
-#define DSI_GHCR_DT5                   0x00000020U
-
-#define DSI_GHCR_VCID                  0x000000C0U               /*!< Channel */
-#define DSI_GHCR_VCID0                 0x00000040U
-#define DSI_GHCR_VCID1                 0x00000080U
-
-#define DSI_GHCR_WCLSB                 0x0000FF00U               /*!< WordCount LSB */
-#define DSI_GHCR_WCLSB0                0x00000100U
-#define DSI_GHCR_WCLSB1                0x00000200U
-#define DSI_GHCR_WCLSB2                0x00000400U
-#define DSI_GHCR_WCLSB3                0x00000800U
-#define DSI_GHCR_WCLSB4                0x00001000U
-#define DSI_GHCR_WCLSB5                0x00002000U
-#define DSI_GHCR_WCLSB6                0x00004000U
-#define DSI_GHCR_WCLSB7                0x00008000U
-
-#define DSI_GHCR_WCMSB                 0x00FF0000U               /*!< WordCount MSB */
-#define DSI_GHCR_WCMSB0                0x00010000U
-#define DSI_GHCR_WCMSB1                0x00020000U
-#define DSI_GHCR_WCMSB2                0x00040000U
-#define DSI_GHCR_WCMSB3                0x00080000U
-#define DSI_GHCR_WCMSB4                0x00100000U
-#define DSI_GHCR_WCMSB5                0x00200000U
-#define DSI_GHCR_WCMSB6                0x00400000U
-#define DSI_GHCR_WCMSB7                0x00800000U
-
-/*******************  Bit definition for DSI_GPDR register  ***************/
-#define DSI_GPDR_DATA1                 0x000000FFU               /*!< Payload Byte 1 */
-#define DSI_GPDR_DATA1_0               0x00000001U
-#define DSI_GPDR_DATA1_1               0x00000002U
-#define DSI_GPDR_DATA1_2               0x00000004U
-#define DSI_GPDR_DATA1_3               0x00000008U
-#define DSI_GPDR_DATA1_4               0x00000010U
-#define DSI_GPDR_DATA1_5               0x00000020U
-#define DSI_GPDR_DATA1_6               0x00000040U
-#define DSI_GPDR_DATA1_7               0x00000080U
-
-#define DSI_GPDR_DATA2                 0x0000FF00U               /*!< Payload Byte 2 */
-#define DSI_GPDR_DATA2_0               0x00000100U
-#define DSI_GPDR_DATA2_1               0x00000200U
-#define DSI_GPDR_DATA2_2               0x00000400U
-#define DSI_GPDR_DATA2_3               0x00000800U
-#define DSI_GPDR_DATA2_4               0x00001000U
-#define DSI_GPDR_DATA2_5               0x00002000U
-#define DSI_GPDR_DATA2_6               0x00004000U
-#define DSI_GPDR_DATA2_7               0x00008000U
-
-#define DSI_GPDR_DATA3                 0x00FF0000U               /*!< Payload Byte 3 */
-#define DSI_GPDR_DATA3_0               0x00010000U
-#define DSI_GPDR_DATA3_1               0x00020000U
-#define DSI_GPDR_DATA3_2               0x00040000U
-#define DSI_GPDR_DATA3_3               0x00080000U
-#define DSI_GPDR_DATA3_4               0x00100000U
-#define DSI_GPDR_DATA3_5               0x00200000U
-#define DSI_GPDR_DATA3_6               0x00400000U
-#define DSI_GPDR_DATA3_7               0x00800000U
-
-#define DSI_GPDR_DATA4                 0xFF000000U               /*!< Payload Byte 4 */
-#define DSI_GPDR_DATA4_0               0x01000000U
-#define DSI_GPDR_DATA4_1               0x02000000U
-#define DSI_GPDR_DATA4_2               0x04000000U
-#define DSI_GPDR_DATA4_3               0x08000000U
-#define DSI_GPDR_DATA4_4               0x10000000U
-#define DSI_GPDR_DATA4_5               0x20000000U
-#define DSI_GPDR_DATA4_6               0x40000000U
-#define DSI_GPDR_DATA4_7               0x80000000U
-
-/*******************  Bit definition for DSI_GPSR register  ***************/
-#define DSI_GPSR_CMDFE                 0x00000001U               /*!< Command FIFO Empty */
-#define DSI_GPSR_CMDFF                 0x00000002U               /*!< Command FIFO Full */
-#define DSI_GPSR_PWRFE                 0x00000004U               /*!< Payload Write FIFO Empty */
-#define DSI_GPSR_PWRFF                 0x00000008U               /*!< Payload Write FIFO Full */
-#define DSI_GPSR_PRDFE                 0x00000010U               /*!< Payload Read FIFO Empty */
-#define DSI_GPSR_PRDFF                 0x00000020U               /*!< Payload Read FIFO Full */
-#define DSI_GPSR_RCB                   0x00000040U               /*!< Read Command Busy */
-
-/*******************  Bit definition for DSI_TCCR0 register  **************/
-#define DSI_TCCR0_LPRX_TOCNT           0x0000FFFFU               /*!< Low-power Reception Timeout Counter */
-#define DSI_TCCR0_LPRX_TOCNT0          0x00000001U
-#define DSI_TCCR0_LPRX_TOCNT1          0x00000002U
-#define DSI_TCCR0_LPRX_TOCNT2          0x00000004U
-#define DSI_TCCR0_LPRX_TOCNT3          0x00000008U
-#define DSI_TCCR0_LPRX_TOCNT4          0x00000010U
-#define DSI_TCCR0_LPRX_TOCNT5          0x00000020U
-#define DSI_TCCR0_LPRX_TOCNT6          0x00000040U
-#define DSI_TCCR0_LPRX_TOCNT7          0x00000080U
-#define DSI_TCCR0_LPRX_TOCNT8          0x00000100U
-#define DSI_TCCR0_LPRX_TOCNT9          0x00000200U
-#define DSI_TCCR0_LPRX_TOCNT10         0x00000400U
-#define DSI_TCCR0_LPRX_TOCNT11         0x00000800U
-#define DSI_TCCR0_LPRX_TOCNT12         0x00001000U
-#define DSI_TCCR0_LPRX_TOCNT13         0x00002000U
-#define DSI_TCCR0_LPRX_TOCNT14         0x00004000U
-#define DSI_TCCR0_LPRX_TOCNT15         0x00008000U
-
-#define DSI_TCCR0_HSTX_TOCNT           0xFFFF0000U               /*!< High-Speed Transmission Timeout Counter */
-#define DSI_TCCR0_HSTX_TOCNT0          0x00010000U
-#define DSI_TCCR0_HSTX_TOCNT1          0x00020000U
-#define DSI_TCCR0_HSTX_TOCNT2          0x00040000U
-#define DSI_TCCR0_HSTX_TOCNT3          0x00080000U
-#define DSI_TCCR0_HSTX_TOCNT4          0x00100000U
-#define DSI_TCCR0_HSTX_TOCNT5          0x00200000U
-#define DSI_TCCR0_HSTX_TOCNT6          0x00400000U
-#define DSI_TCCR0_HSTX_TOCNT7          0x00800000U
-#define DSI_TCCR0_HSTX_TOCNT8          0x01000000U
-#define DSI_TCCR0_HSTX_TOCNT9          0x02000000U
-#define DSI_TCCR0_HSTX_TOCNT10         0x04000000U
-#define DSI_TCCR0_HSTX_TOCNT11         0x08000000U
-#define DSI_TCCR0_HSTX_TOCNT12         0x10000000U
-#define DSI_TCCR0_HSTX_TOCNT13         0x20000000U
-#define DSI_TCCR0_HSTX_TOCNT14         0x40000000U
-#define DSI_TCCR0_HSTX_TOCNT15         0x80000000U
-
-/*******************  Bit definition for DSI_TCCR1 register  **************/
-#define DSI_TCCR1_HSRD_TOCNT           0x0000FFFFU               /*!< High-Speed Read Timeout Counter */
-#define DSI_TCCR1_HSRD_TOCNT0          0x00000001U
-#define DSI_TCCR1_HSRD_TOCNT1          0x00000002U
-#define DSI_TCCR1_HSRD_TOCNT2          0x00000004U
-#define DSI_TCCR1_HSRD_TOCNT3          0x00000008U
-#define DSI_TCCR1_HSRD_TOCNT4          0x00000010U
-#define DSI_TCCR1_HSRD_TOCNT5          0x00000020U
-#define DSI_TCCR1_HSRD_TOCNT6          0x00000040U
-#define DSI_TCCR1_HSRD_TOCNT7          0x00000080U
-#define DSI_TCCR1_HSRD_TOCNT8          0x00000100U
-#define DSI_TCCR1_HSRD_TOCNT9          0x00000200U
-#define DSI_TCCR1_HSRD_TOCNT10         0x00000400U
-#define DSI_TCCR1_HSRD_TOCNT11         0x00000800U
-#define DSI_TCCR1_HSRD_TOCNT12         0x00001000U
-#define DSI_TCCR1_HSRD_TOCNT13         0x00002000U
-#define DSI_TCCR1_HSRD_TOCNT14         0x00004000U
-#define DSI_TCCR1_HSRD_TOCNT15         0x00008000U
-
-/*******************  Bit definition for DSI_TCCR2 register  **************/
-#define DSI_TCCR2_LPRD_TOCNT           0x0000FFFFU               /*!< Low-Power Read Timeout Counter */
-#define DSI_TCCR2_LPRD_TOCNT0          0x00000001U
-#define DSI_TCCR2_LPRD_TOCNT1          0x00000002U
-#define DSI_TCCR2_LPRD_TOCNT2          0x00000004U
-#define DSI_TCCR2_LPRD_TOCNT3          0x00000008U
-#define DSI_TCCR2_LPRD_TOCNT4          0x00000010U
-#define DSI_TCCR2_LPRD_TOCNT5          0x00000020U
-#define DSI_TCCR2_LPRD_TOCNT6          0x00000040U
-#define DSI_TCCR2_LPRD_TOCNT7          0x00000080U
-#define DSI_TCCR2_LPRD_TOCNT8          0x00000100U
-#define DSI_TCCR2_LPRD_TOCNT9          0x00000200U
-#define DSI_TCCR2_LPRD_TOCNT10         0x00000400U
-#define DSI_TCCR2_LPRD_TOCNT11         0x00000800U
-#define DSI_TCCR2_LPRD_TOCNT12         0x00001000U
-#define DSI_TCCR2_LPRD_TOCNT13         0x00002000U
-#define DSI_TCCR2_LPRD_TOCNT14         0x00004000U
-#define DSI_TCCR2_LPRD_TOCNT15         0x00008000U
-
-/*******************  Bit definition for DSI_TCCR3 register  **************/
-#define DSI_TCCR3_HSWR_TOCNT           0x0000FFFFU               /*!< High-Speed Write Timeout Counter */
-#define DSI_TCCR3_HSWR_TOCNT0          0x00000001U
-#define DSI_TCCR3_HSWR_TOCNT1          0x00000002U
-#define DSI_TCCR3_HSWR_TOCNT2          0x00000004U
-#define DSI_TCCR3_HSWR_TOCNT3          0x00000008U
-#define DSI_TCCR3_HSWR_TOCNT4          0x00000010U
-#define DSI_TCCR3_HSWR_TOCNT5          0x00000020U
-#define DSI_TCCR3_HSWR_TOCNT6          0x00000040U
-#define DSI_TCCR3_HSWR_TOCNT7          0x00000080U
-#define DSI_TCCR3_HSWR_TOCNT8          0x00000100U
-#define DSI_TCCR3_HSWR_TOCNT9          0x00000200U
-#define DSI_TCCR3_HSWR_TOCNT10         0x00000400U
-#define DSI_TCCR3_HSWR_TOCNT11         0x00000800U
-#define DSI_TCCR3_HSWR_TOCNT12         0x00001000U
-#define DSI_TCCR3_HSWR_TOCNT13         0x00002000U
-#define DSI_TCCR3_HSWR_TOCNT14         0x00004000U
-#define DSI_TCCR3_HSWR_TOCNT15         0x00008000U
-
-#define DSI_TCCR3_PM                   0x01000000U               /*!< Presp Mode */
-
-/*******************  Bit definition for DSI_TCCR4 register  **************/
-#define DSI_TCCR4_LPWR_TOCNT           0x0000FFFFU               /*!< Low-Power Write Timeout Counter */
-#define DSI_TCCR4_LPWR_TOCNT0          0x00000001U
-#define DSI_TCCR4_LPWR_TOCNT1          0x00000002U
-#define DSI_TCCR4_LPWR_TOCNT2          0x00000004U
-#define DSI_TCCR4_LPWR_TOCNT3          0x00000008U
-#define DSI_TCCR4_LPWR_TOCNT4          0x00000010U
-#define DSI_TCCR4_LPWR_TOCNT5          0x00000020U
-#define DSI_TCCR4_LPWR_TOCNT6          0x00000040U
-#define DSI_TCCR4_LPWR_TOCNT7          0x00000080U
-#define DSI_TCCR4_LPWR_TOCNT8          0x00000100U
-#define DSI_TCCR4_LPWR_TOCNT9          0x00000200U
-#define DSI_TCCR4_LPWR_TOCNT10         0x00000400U
-#define DSI_TCCR4_LPWR_TOCNT11         0x00000800U
-#define DSI_TCCR4_LPWR_TOCNT12         0x00001000U
-#define DSI_TCCR4_LPWR_TOCNT13         0x00002000U
-#define DSI_TCCR4_LPWR_TOCNT14         0x00004000U
-#define DSI_TCCR4_LPWR_TOCNT15         0x00008000U
-
-/*******************  Bit definition for DSI_TCCR5 register  **************/
-#define DSI_TCCR5_BTA_TOCNT            0x0000FFFFU               /*!< Bus-Turn-Around Timeout Counter */
-#define DSI_TCCR5_BTA_TOCNT0           0x00000001U
-#define DSI_TCCR5_BTA_TOCNT1           0x00000002U
-#define DSI_TCCR5_BTA_TOCNT2           0x00000004U
-#define DSI_TCCR5_BTA_TOCNT3           0x00000008U
-#define DSI_TCCR5_BTA_TOCNT4           0x00000010U
-#define DSI_TCCR5_BTA_TOCNT5           0x00000020U
-#define DSI_TCCR5_BTA_TOCNT6           0x00000040U
-#define DSI_TCCR5_BTA_TOCNT7           0x00000080U
-#define DSI_TCCR5_BTA_TOCNT8           0x00000100U
-#define DSI_TCCR5_BTA_TOCNT9           0x00000200U
-#define DSI_TCCR5_BTA_TOCNT10          0x00000400U
-#define DSI_TCCR5_BTA_TOCNT11          0x00000800U
-#define DSI_TCCR5_BTA_TOCNT12          0x00001000U
-#define DSI_TCCR5_BTA_TOCNT13          0x00002000U
-#define DSI_TCCR5_BTA_TOCNT14          0x00004000U
-#define DSI_TCCR5_BTA_TOCNT15          0x00008000U
-
-/*******************  Bit definition for DSI_TDCR register  ***************/
-#define DSI_TDCR_3DM                   0x00000003U               /*!< 3D Mode */
-#define DSI_TDCR_3DM0                  0x00000001U
-#define DSI_TDCR_3DM1                  0x00000002U
-
-#define DSI_TDCR_3DF                   0x0000000CU               /*!< 3D Format */
-#define DSI_TDCR_3DF0                  0x00000004U
-#define DSI_TDCR_3DF1                  0x00000008U
-
-#define DSI_TDCR_SVS                   0x00000010U               /*!< Second VSYNC */
-#define DSI_TDCR_RF                    0x00000020U               /*!< Right First */
-#define DSI_TDCR_S3DC                  0x00010000U               /*!< Send 3D Control */
-
-/*******************  Bit definition for DSI_CLCR register  ***************/
-#define DSI_CLCR_DPCC                  0x00000001U               /*!< D-PHY Clock Control */
-#define DSI_CLCR_ACR                   0x00000002U               /*!< Automatic Clocklane Control */
-
-/*******************  Bit definition for DSI_CLTCR register  **************/
-#define DSI_CLTCR_LP2HS_TIME           0x000003FFU               /*!< Low-Power to High-Speed Time */
-#define DSI_CLTCR_LP2HS_TIME0          0x00000001U
-#define DSI_CLTCR_LP2HS_TIME1          0x00000002U
-#define DSI_CLTCR_LP2HS_TIME2          0x00000004U
-#define DSI_CLTCR_LP2HS_TIME3          0x00000008U
-#define DSI_CLTCR_LP2HS_TIME4          0x00000010U
-#define DSI_CLTCR_LP2HS_TIME5          0x00000020U
-#define DSI_CLTCR_LP2HS_TIME6          0x00000040U
-#define DSI_CLTCR_LP2HS_TIME7          0x00000080U
-#define DSI_CLTCR_LP2HS_TIME8          0x00000100U
-#define DSI_CLTCR_LP2HS_TIME9          0x00000200U
-
-#define DSI_CLTCR_HS2LP_TIME           0x03FF0000U               /*!< High-Speed to Low-Power Time */
-#define DSI_CLTCR_HS2LP_TIME0          0x00010000U
-#define DSI_CLTCR_HS2LP_TIME1          0x00020000U
-#define DSI_CLTCR_HS2LP_TIME2          0x00040000U
-#define DSI_CLTCR_HS2LP_TIME3          0x00080000U
-#define DSI_CLTCR_HS2LP_TIME4          0x00100000U
-#define DSI_CLTCR_HS2LP_TIME5          0x00200000U
-#define DSI_CLTCR_HS2LP_TIME6          0x00400000U
-#define DSI_CLTCR_HS2LP_TIME7          0x00800000U
-#define DSI_CLTCR_HS2LP_TIME8          0x01000000U
-#define DSI_CLTCR_HS2LP_TIME9          0x02000000U
-
-/*******************  Bit definition for DSI_DLTCR register  **************/
-#define DSI_DLTCR_MRD_TIME             0x00007FFFU               /*!< Maximum Read Time */
-#define DSI_DLTCR_MRD_TIME0            0x00000001U
-#define DSI_DLTCR_MRD_TIME1            0x00000002U
-#define DSI_DLTCR_MRD_TIME2            0x00000004U
-#define DSI_DLTCR_MRD_TIME3            0x00000008U
-#define DSI_DLTCR_MRD_TIME4            0x00000010U
-#define DSI_DLTCR_MRD_TIME5            0x00000020U
-#define DSI_DLTCR_MRD_TIME6            0x00000040U
-#define DSI_DLTCR_MRD_TIME7            0x00000080U
-#define DSI_DLTCR_MRD_TIME8            0x00000100U
-#define DSI_DLTCR_MRD_TIME9            0x00000200U
-#define DSI_DLTCR_MRD_TIME10           0x00000400U
-#define DSI_DLTCR_MRD_TIME11           0x00000800U
-#define DSI_DLTCR_MRD_TIME12           0x00001000U
-#define DSI_DLTCR_MRD_TIME13           0x00002000U
-#define DSI_DLTCR_MRD_TIME14           0x00004000U
-
-#define DSI_DLTCR_LP2HS_TIME           0x00FF0000U               /*!< Low-Power To High-Speed Time */
-#define DSI_DLTCR_LP2HS_TIME0          0x00010000U
-#define DSI_DLTCR_LP2HS_TIME1          0x00020000U
-#define DSI_DLTCR_LP2HS_TIME2          0x00040000U
-#define DSI_DLTCR_LP2HS_TIME3          0x00080000U
-#define DSI_DLTCR_LP2HS_TIME4          0x00100000U
-#define DSI_DLTCR_LP2HS_TIME5          0x00200000U
-#define DSI_DLTCR_LP2HS_TIME6          0x00400000U
-#define DSI_DLTCR_LP2HS_TIME7          0x00800000U
-
-#define DSI_DLTCR_HS2LP_TIME           0xFF000000U               /*!< High-Speed To Low-Power Time */
-#define DSI_DLTCR_HS2LP_TIME0          0x01000000U
-#define DSI_DLTCR_HS2LP_TIME1          0x02000000U
-#define DSI_DLTCR_HS2LP_TIME2          0x04000000U
-#define DSI_DLTCR_HS2LP_TIME3          0x08000000U
-#define DSI_DLTCR_HS2LP_TIME4          0x10000000U
-#define DSI_DLTCR_HS2LP_TIME5          0x20000000U
-#define DSI_DLTCR_HS2LP_TIME6          0x40000000U
-#define DSI_DLTCR_HS2LP_TIME7          0x80000000U
-
-/*******************  Bit definition for DSI_PCTLR register  **************/
-#define DSI_PCTLR_DEN                  0x00000002U               /*!< Digital Enable */
-#define DSI_PCTLR_CKE                  0x00000004U               /*!< Clock Enable */
-
-/*******************  Bit definition for DSI_PCONFR register  *************/
-#define DSI_PCONFR_NL                  0x00000003U               /*!< Number of Lanes */
-#define DSI_PCONFR_NL0                 0x00000001U
-#define DSI_PCONFR_NL1                 0x00000002U
-
-#define DSI_PCONFR_SW_TIME             0x0000FF00U               /*!< Stop Wait Time */
-#define DSI_PCONFR_SW_TIME0            0x00000100U
-#define DSI_PCONFR_SW_TIME1            0x00000200U
-#define DSI_PCONFR_SW_TIME2            0x00000400U
-#define DSI_PCONFR_SW_TIME3            0x00000800U
-#define DSI_PCONFR_SW_TIME4            0x00001000U
-#define DSI_PCONFR_SW_TIME5            0x00002000U
-#define DSI_PCONFR_SW_TIME6            0x00004000U
-#define DSI_PCONFR_SW_TIME7            0x00008000U
-
-/*******************  Bit definition for DSI_PUCR register  ***************/
-#define DSI_PUCR_URCL                  0x00000001U               /*!< ULPS Request on Clock Lane */
-#define DSI_PUCR_UECL                  0x00000002U               /*!< ULPS Exit on Clock Lane */
-#define DSI_PUCR_URDL                  0x00000004U               /*!< ULPS Request on Data Lane */
-#define DSI_PUCR_UEDL                  0x00000008U               /*!< ULPS Exit on Data Lane */
-
-/*******************  Bit definition for DSI_PTTCR register  **************/
-#define DSI_PTTCR_TX_TRIG              0x0000000FU               /*!< Transmission Trigger */
-#define DSI_PTTCR_TX_TRIG0             0x00000001U
-#define DSI_PTTCR_TX_TRIG1             0x00000002U
-#define DSI_PTTCR_TX_TRIG2             0x00000004U
-#define DSI_PTTCR_TX_TRIG3             0x00000008U
-
-/*******************  Bit definition for DSI_PSR register  ****************/
-#define DSI_PSR_PD                     0x00000002U               /*!< PHY Direction */
-#define DSI_PSR_PSSC                   0x00000004U               /*!< PHY Stop State Clock lane */
-#define DSI_PSR_UANC                   0x00000008U               /*!< ULPS Active Not Clock lane */
-#define DSI_PSR_PSS0                   0x00000010U               /*!< PHY Stop State lane 0 */
-#define DSI_PSR_UAN0                   0x00000020U               /*!< ULPS Active Not lane 0 */
-#define DSI_PSR_RUE0                   0x00000040U               /*!< RX ULPS Escape lane 0 */
-#define DSI_PSR_PSS1                   0x00000080U               /*!< PHY Stop State lane 1 */
-#define DSI_PSR_UAN1                   0x00000100U               /*!< ULPS Active Not lane 1 */
-
-/*******************  Bit definition for DSI_ISR0 register  ***************/
-#define DSI_ISR0_AE0                   0x00000001U               /*!< Acknowledge Error 0 */
-#define DSI_ISR0_AE1                   0x00000002U               /*!< Acknowledge Error 1 */
-#define DSI_ISR0_AE2                   0x00000004U               /*!< Acknowledge Error 2 */
-#define DSI_ISR0_AE3                   0x00000008U               /*!< Acknowledge Error 3 */
-#define DSI_ISR0_AE4                   0x00000010U               /*!< Acknowledge Error 4 */
-#define DSI_ISR0_AE5                   0x00000020U               /*!< Acknowledge Error 5 */
-#define DSI_ISR0_AE6                   0x00000040U               /*!< Acknowledge Error 6 */
-#define DSI_ISR0_AE7                   0x00000080U               /*!< Acknowledge Error 7 */
-#define DSI_ISR0_AE8                   0x00000100U               /*!< Acknowledge Error 8 */
-#define DSI_ISR0_AE9                   0x00000200U               /*!< Acknowledge Error 9 */
-#define DSI_ISR0_AE10                  0x00000400U               /*!< Acknowledge Error 10 */
-#define DSI_ISR0_AE11                  0x00000800U               /*!< Acknowledge Error 11 */
-#define DSI_ISR0_AE12                  0x00001000U               /*!< Acknowledge Error 12 */
-#define DSI_ISR0_AE13                  0x00002000U               /*!< Acknowledge Error 13 */
-#define DSI_ISR0_AE14                  0x00004000U               /*!< Acknowledge Error 14 */
-#define DSI_ISR0_AE15                  0x00008000U               /*!< Acknowledge Error 15 */
-#define DSI_ISR0_PE0                   0x00010000U               /*!< PHY Error 0 */
-#define DSI_ISR0_PE1                   0x00020000U               /*!< PHY Error 1 */
-#define DSI_ISR0_PE2                   0x00040000U               /*!< PHY Error 2 */
-#define DSI_ISR0_PE3                   0x00080000U               /*!< PHY Error 3 */
-#define DSI_ISR0_PE4                   0x00100000U               /*!< PHY Error 4 */
-
-/*******************  Bit definition for DSI_ISR1 register  ***************/
-#define DSI_ISR1_TOHSTX                0x00000001U               /*!< Timeout High-Speed Transmission */
-#define DSI_ISR1_TOLPRX                0x00000002U               /*!< Timeout Low-Power Reception */
-#define DSI_ISR1_ECCSE                 0x00000004U               /*!< ECC Single-bit Error */
-#define DSI_ISR1_ECCME                 0x00000008U               /*!< ECC Multi-bit Error */
-#define DSI_ISR1_CRCE                  0x00000010U               /*!< CRC Error */
-#define DSI_ISR1_PSE                   0x00000020U               /*!< Packet Size Error */
-#define DSI_ISR1_EOTPE                 0x00000040U               /*!< EoTp Error */
-#define DSI_ISR1_LPWRE                 0x00000080U               /*!< LTDC Payload Write Error */
-#define DSI_ISR1_GCWRE                 0x00000100U               /*!< Generic Command Write Error */
-#define DSI_ISR1_GPWRE                 0x00000200U               /*!< Generic Payload Write Error */
-#define DSI_ISR1_GPTXE                 0x00000400U               /*!< Generic Payload Transmit Error */
-#define DSI_ISR1_GPRDE                 0x00000800U               /*!< Generic Payload Read Error */
-#define DSI_ISR1_GPRXE                 0x00001000U               /*!< Generic Payload Receive Error */
-
-/*******************  Bit definition for DSI_IER0 register  ***************/
-#define DSI_IER0_AE0IE                 0x00000001U               /*!< Acknowledge Error 0 Interrupt Enable */
-#define DSI_IER0_AE1IE                 0x00000002U               /*!< Acknowledge Error 1 Interrupt Enable */
-#define DSI_IER0_AE2IE                 0x00000004U               /*!< Acknowledge Error 2 Interrupt Enable */
-#define DSI_IER0_AE3IE                 0x00000008U               /*!< Acknowledge Error 3 Interrupt Enable */
-#define DSI_IER0_AE4IE                 0x00000010U               /*!< Acknowledge Error 4 Interrupt Enable */
-#define DSI_IER0_AE5IE                 0x00000020U               /*!< Acknowledge Error 5 Interrupt Enable */
-#define DSI_IER0_AE6IE                 0x00000040U               /*!< Acknowledge Error 6 Interrupt Enable */
-#define DSI_IER0_AE7IE                 0x00000080U               /*!< Acknowledge Error 7 Interrupt Enable */
-#define DSI_IER0_AE8IE                 0x00000100U               /*!< Acknowledge Error 8 Interrupt Enable */
-#define DSI_IER0_AE9IE                 0x00000200U               /*!< Acknowledge Error 9 Interrupt Enable */
-#define DSI_IER0_AE10IE                0x00000400U               /*!< Acknowledge Error 10 Interrupt Enable */
-#define DSI_IER0_AE11IE                0x00000800U               /*!< Acknowledge Error 11 Interrupt Enable */
-#define DSI_IER0_AE12IE                0x00001000U               /*!< Acknowledge Error 12 Interrupt Enable */
-#define DSI_IER0_AE13IE                0x00002000U               /*!< Acknowledge Error 13 Interrupt Enable */
-#define DSI_IER0_AE14IE                0x00004000U               /*!< Acknowledge Error 14 Interrupt Enable */
-#define DSI_IER0_AE15IE                0x00008000U               /*!< Acknowledge Error 15 Interrupt Enable */
-#define DSI_IER0_PE0IE                 0x00010000U               /*!< PHY Error 0 Interrupt Enable */
-#define DSI_IER0_PE1IE                 0x00020000U               /*!< PHY Error 1 Interrupt Enable */
-#define DSI_IER0_PE2IE                 0x00040000U               /*!< PHY Error 2 Interrupt Enable */
-#define DSI_IER0_PE3IE                 0x00080000U               /*!< PHY Error 3 Interrupt Enable */
-#define DSI_IER0_PE4IE                 0x00100000U               /*!< PHY Error 4 Interrupt Enable */
-
-/*******************  Bit definition for DSI_IER1 register  ***************/
-#define DSI_IER1_TOHSTXIE              0x00000001U               /*!< Timeout High-Speed Transmission Interrupt Enable */
-#define DSI_IER1_TOLPRXIE              0x00000002U               /*!< Timeout Low-Power Reception Interrupt Enable */
-#define DSI_IER1_ECCSEIE               0x00000004U               /*!< ECC Single-bit Error Interrupt Enable */
-#define DSI_IER1_ECCMEIE               0x00000008U               /*!< ECC Multi-bit Error Interrupt Enable */
-#define DSI_IER1_CRCEIE                0x00000010U               /*!< CRC Error Interrupt Enable */
-#define DSI_IER1_PSEIE                 0x00000020U               /*!< Packet Size Error Interrupt Enable */
-#define DSI_IER1_EOTPEIE               0x00000040U               /*!< EoTp Error Interrupt Enable */
-#define DSI_IER1_LPWREIE               0x00000080U               /*!< LTDC Payload Write Error Interrupt Enable */
-#define DSI_IER1_GCWREIE               0x00000100U               /*!< Generic Command Write Error Interrupt Enable */
-#define DSI_IER1_GPWREIE               0x00000200U               /*!< Generic Payload Write Error Interrupt Enable */
-#define DSI_IER1_GPTXEIE               0x00000400U               /*!< Generic Payload Transmit Error Interrupt Enable */
-#define DSI_IER1_GPRDEIE               0x00000800U               /*!< Generic Payload Read Error Interrupt Enable */
-#define DSI_IER1_GPRXEIE               0x00001000U               /*!< Generic Payload Receive Error Interrupt Enable */
-
-/*******************  Bit definition for DSI_FIR0 register  ***************/
-#define DSI_FIR0_FAE0                  0x00000001U               /*!< Force Acknowledge Error 0 */
-#define DSI_FIR0_FAE1                  0x00000002U               /*!< Force Acknowledge Error 1 */
-#define DSI_FIR0_FAE2                  0x00000004U               /*!< Force Acknowledge Error 2 */
-#define DSI_FIR0_FAE3                  0x00000008U               /*!< Force Acknowledge Error 3 */
-#define DSI_FIR0_FAE4                  0x00000010U               /*!< Force Acknowledge Error 4 */
-#define DSI_FIR0_FAE5                  0x00000020U               /*!< Force Acknowledge Error 5 */
-#define DSI_FIR0_FAE6                  0x00000040U               /*!< Force Acknowledge Error 6 */
-#define DSI_FIR0_FAE7                  0x00000080U               /*!< Force Acknowledge Error 7 */
-#define DSI_FIR0_FAE8                  0x00000100U               /*!< Force Acknowledge Error 8 */
-#define DSI_FIR0_FAE9                  0x00000200U               /*!< Force Acknowledge Error 9 */
-#define DSI_FIR0_FAE10                 0x00000400U               /*!< Force Acknowledge Error 10 */
-#define DSI_FIR0_FAE11                 0x00000800U               /*!< Force Acknowledge Error 11 */
-#define DSI_FIR0_FAE12                 0x00001000U               /*!< Force Acknowledge Error 12 */
-#define DSI_FIR0_FAE13                 0x00002000U               /*!< Force Acknowledge Error 13 */
-#define DSI_FIR0_FAE14                 0x00004000U               /*!< Force Acknowledge Error 14 */
-#define DSI_FIR0_FAE15                 0x00008000U               /*!< Force Acknowledge Error 15 */
-#define DSI_FIR0_FPE0                  0x00010000U               /*!< Force PHY Error 0 */
-#define DSI_FIR0_FPE1                  0x00020000U               /*!< Force PHY Error 1 */
-#define DSI_FIR0_FPE2                  0x00040000U               /*!< Force PHY Error 2 */
-#define DSI_FIR0_FPE3                  0x00080000U               /*!< Force PHY Error 3 */
-#define DSI_FIR0_FPE4                  0x00100000U               /*!< Force PHY Error 4 */
-
-/*******************  Bit definition for DSI_FIR1 register  ***************/
-#define DSI_FIR1_FTOHSTX               0x00000001U               /*!< Force Timeout High-Speed Transmission */
-#define DSI_FIR1_FTOLPRX               0x00000002U               /*!< Force Timeout Low-Power Reception */
-#define DSI_FIR1_FECCSE                0x00000004U               /*!< Force ECC Single-bit Error */
-#define DSI_FIR1_FECCME                0x00000008U               /*!< Force ECC Multi-bit Error */
-#define DSI_FIR1_FCRCE                 0x00000010U               /*!< Force CRC Error */
-#define DSI_FIR1_FPSE                  0x00000020U               /*!< Force Packet Size Error */
-#define DSI_FIR1_FEOTPE                0x00000040U               /*!< Force EoTp Error */
-#define DSI_FIR1_FLPWRE                0x00000080U               /*!< Force LTDC Payload Write Error */
-#define DSI_FIR1_FGCWRE                0x00000100U               /*!< Force Generic Command Write Error */
-#define DSI_FIR1_FGPWRE                0x00000200U               /*!< Force Generic Payload Write Error */
-#define DSI_FIR1_FGPTXE                0x00000400U               /*!< Force Generic Payload Transmit Error */
-#define DSI_FIR1_FGPRDE                0x00000800U               /*!< Force Generic Payload Read Error */
-#define DSI_FIR1_FGPRXE                0x00001000U               /*!< Force Generic Payload Receive Error */
-
-/*******************  Bit definition for DSI_VSCR register  ***************/
-#define DSI_VSCR_EN                    0x00000001U               /*!< Enable */
-#define DSI_VSCR_UR                    0x00000100U               /*!< Update Register */
-
-/*******************  Bit definition for DSI_LCVCIDR register  ************/
-#define DSI_LCVCIDR_VCID               0x00000003U               /*!< Virtual Channel ID */
-#define DSI_LCVCIDR_VCID0              0x00000001U
-#define DSI_LCVCIDR_VCID1              0x00000002U
-
-/*******************  Bit definition for DSI_LCCCR register  **************/
-#define DSI_LCCCR_COLC                 0x0000000FU               /*!< Color Coding */
-#define DSI_LCCCR_COLC0                0x00000001U
-#define DSI_LCCCR_COLC1                0x00000002U
-#define DSI_LCCCR_COLC2                0x00000004U
-#define DSI_LCCCR_COLC3                0x00000008U
-
-#define DSI_LCCCR_LPE                  0x00000100U               /*!< Loosely Packed Enable */
-
-/*******************  Bit definition for DSI_LPMCCR register  *************/
-#define DSI_LPMCCR_VLPSIZE             0x000000FFU               /*!< VACT Largest Packet Size */
-#define DSI_LPMCCR_VLPSIZE0            0x00000001U
-#define DSI_LPMCCR_VLPSIZE1            0x00000002U
-#define DSI_LPMCCR_VLPSIZE2            0x00000004U
-#define DSI_LPMCCR_VLPSIZE3            0x00000008U
-#define DSI_LPMCCR_VLPSIZE4            0x00000010U
-#define DSI_LPMCCR_VLPSIZE5            0x00000020U
-#define DSI_LPMCCR_VLPSIZE6            0x00000040U
-#define DSI_LPMCCR_VLPSIZE7            0x00000080U
-
-#define DSI_LPMCCR_LPSIZE              0x00FF0000U               /*!< Largest Packet Size */
-#define DSI_LPMCCR_LPSIZE0             0x00010000U
-#define DSI_LPMCCR_LPSIZE1             0x00020000U
-#define DSI_LPMCCR_LPSIZE2             0x00040000U
-#define DSI_LPMCCR_LPSIZE3             0x00080000U
-#define DSI_LPMCCR_LPSIZE4             0x00100000U
-#define DSI_LPMCCR_LPSIZE5             0x00200000U
-#define DSI_LPMCCR_LPSIZE6             0x00400000U
-#define DSI_LPMCCR_LPSIZE7             0x00800000U
-
-/*******************  Bit definition for DSI_VMCCR register  **************/
-#define DSI_VMCCR_VMT                  0x00000003U               /*!< Video Mode Type */
-#define DSI_VMCCR_VMT0                 0x00000001U
-#define DSI_VMCCR_VMT1                 0x00000002U
-
-#define DSI_VMCCR_LPVSAE               0x00000100U               /*!< Low-power Vertical Sync time Enable */
-#define DSI_VMCCR_LPVBPE               0x00000200U               /*!< Low-power Vertical Back-porch Enable */
-#define DSI_VMCCR_LPVFPE               0x00000400U               /*!< Low-power Vertical Front-porch Enable */
-#define DSI_VMCCR_LPVAE                0x00000800U               /*!< Low-power Vertical Active Enable */
-#define DSI_VMCCR_LPHBPE               0x00001000U               /*!< Low-power Horizontal Back-porch Enable */
-#define DSI_VMCCR_LPHFE                0x00002000U               /*!< Low-power Horizontal Front-porch Enable */
-#define DSI_VMCCR_FBTAAE               0x00004000U               /*!< Frame BTA Acknowledge Enable */
-#define DSI_VMCCR_LPCE                 0x00008000U               /*!< Low-power Command Enable */
-
-/*******************  Bit definition for DSI_VPCCR register  **************/
-#define DSI_VPCCR_VPSIZE               0x00003FFFU               /*!< Video Packet Size */
-#define DSI_VPCCR_VPSIZE0              0x00000001U
-#define DSI_VPCCR_VPSIZE1              0x00000002U
-#define DSI_VPCCR_VPSIZE2              0x00000004U
-#define DSI_VPCCR_VPSIZE3              0x00000008U
-#define DSI_VPCCR_VPSIZE4              0x00000010U
-#define DSI_VPCCR_VPSIZE5              0x00000020U
-#define DSI_VPCCR_VPSIZE6              0x00000040U
-#define DSI_VPCCR_VPSIZE7              0x00000080U
-#define DSI_VPCCR_VPSIZE8              0x00000100U
-#define DSI_VPCCR_VPSIZE9              0x00000200U
-#define DSI_VPCCR_VPSIZE10             0x00000400U
-#define DSI_VPCCR_VPSIZE11             0x00000800U
-#define DSI_VPCCR_VPSIZE12             0x00001000U
-#define DSI_VPCCR_VPSIZE13             0x00002000U
-
-/*******************  Bit definition for DSI_VCCCR register  **************/
-#define DSI_VCCCR_NUMC                 0x00001FFFU               /*!< Number of Chunks */
-#define DSI_VCCCR_NUMC0                0x00000001U
-#define DSI_VCCCR_NUMC1                0x00000002U
-#define DSI_VCCCR_NUMC2                0x00000004U
-#define DSI_VCCCR_NUMC3                0x00000008U
-#define DSI_VCCCR_NUMC4                0x00000010U
-#define DSI_VCCCR_NUMC5                0x00000020U
-#define DSI_VCCCR_NUMC6                0x00000040U
-#define DSI_VCCCR_NUMC7                0x00000080U
-#define DSI_VCCCR_NUMC8                0x00000100U
-#define DSI_VCCCR_NUMC9                0x00000200U
-#define DSI_VCCCR_NUMC10               0x00000400U
-#define DSI_VCCCR_NUMC11               0x00000800U
-#define DSI_VCCCR_NUMC12               0x00001000U
-
-/*******************  Bit definition for DSI_VNPCCR register  *************/
-#define DSI_VNPCCR_NPSIZE              0x00001FFFU               /*!< Number of Chunks */
-#define DSI_VNPCCR_NPSIZE0             0x00000001U
-#define DSI_VNPCCR_NPSIZE1             0x00000002U
-#define DSI_VNPCCR_NPSIZE2             0x00000004U
-#define DSI_VNPCCR_NPSIZE3             0x00000008U
-#define DSI_VNPCCR_NPSIZE4             0x00000010U
-#define DSI_VNPCCR_NPSIZE5             0x00000020U
-#define DSI_VNPCCR_NPSIZE6             0x00000040U
-#define DSI_VNPCCR_NPSIZE7             0x00000080U
-#define DSI_VNPCCR_NPSIZE8             0x00000100U
-#define DSI_VNPCCR_NPSIZE9             0x00000200U
-#define DSI_VNPCCR_NPSIZE10            0x00000400U
-#define DSI_VNPCCR_NPSIZE11            0x00000800U
-#define DSI_VNPCCR_NPSIZE12            0x00001000U
-
-/*******************  Bit definition for DSI_VHSACCR register  ************/
-#define DSI_VHSACCR_HSA                0x00000FFFU               /*!< Horizontal Synchronism Active duration */
-#define DSI_VHSACCR_HSA0               0x00000001U
-#define DSI_VHSACCR_HSA1               0x00000002U
-#define DSI_VHSACCR_HSA2               0x00000004U
-#define DSI_VHSACCR_HSA3               0x00000008U
-#define DSI_VHSACCR_HSA4               0x00000010U
-#define DSI_VHSACCR_HSA5               0x00000020U
-#define DSI_VHSACCR_HSA6               0x00000040U
-#define DSI_VHSACCR_HSA7               0x00000080U
-#define DSI_VHSACCR_HSA8               0x00000100U
-#define DSI_VHSACCR_HSA9               0x00000200U
-#define DSI_VHSACCR_HSA10              0x00000400U
-#define DSI_VHSACCR_HSA11              0x00000800U
-
-/*******************  Bit definition for DSI_VHBPCCR register  ************/
-#define DSI_VHBPCCR_HBP                0x00000FFFU               /*!< Horizontal Back-Porch duration */
-#define DSI_VHBPCCR_HBP0               0x00000001U
-#define DSI_VHBPCCR_HBP1               0x00000002U
-#define DSI_VHBPCCR_HBP2               0x00000004U
-#define DSI_VHBPCCR_HBP3               0x00000008U
-#define DSI_VHBPCCR_HBP4               0x00000010U
-#define DSI_VHBPCCR_HBP5               0x00000020U
-#define DSI_VHBPCCR_HBP6               0x00000040U
-#define DSI_VHBPCCR_HBP7               0x00000080U
-#define DSI_VHBPCCR_HBP8               0x00000100U
-#define DSI_VHBPCCR_HBP9               0x00000200U
-#define DSI_VHBPCCR_HBP10              0x00000400U
-#define DSI_VHBPCCR_HBP11              0x00000800U
-
-/*******************  Bit definition for DSI_VLCCR register  **************/
-#define DSI_VLCCR_HLINE                0x00007FFFU               /*!< Horizontal Line duration */
-#define DSI_VLCCR_HLINE0               0x00000001U
-#define DSI_VLCCR_HLINE1               0x00000002U
-#define DSI_VLCCR_HLINE2               0x00000004U
-#define DSI_VLCCR_HLINE3               0x00000008U
-#define DSI_VLCCR_HLINE4               0x00000010U
-#define DSI_VLCCR_HLINE5               0x00000020U
-#define DSI_VLCCR_HLINE6               0x00000040U
-#define DSI_VLCCR_HLINE7               0x00000080U
-#define DSI_VLCCR_HLINE8               0x00000100U
-#define DSI_VLCCR_HLINE9               0x00000200U
-#define DSI_VLCCR_HLINE10              0x00000400U
-#define DSI_VLCCR_HLINE11              0x00000800U
-#define DSI_VLCCR_HLINE12              0x00001000U
-#define DSI_VLCCR_HLINE13              0x00002000U
-#define DSI_VLCCR_HLINE14              0x00004000U
-
-/*******************  Bit definition for DSI_VVSACCR register  ***************/
-#define DSI_VVSACCR_VSA                   0x000003FFU               /*!< Vertical Synchronism Active duration */
-#define DSI_VVSACCR_VSA0                  0x00000001U
-#define DSI_VVSACCR_VSA1                  0x00000002U
-#define DSI_VVSACCR_VSA2                  0x00000004U
-#define DSI_VVSACCR_VSA3                  0x00000008U
-#define DSI_VVSACCR_VSA4                  0x00000010U
-#define DSI_VVSACCR_VSA5                  0x00000020U
-#define DSI_VVSACCR_VSA6                  0x00000040U
-#define DSI_VVSACCR_VSA7                  0x00000080U
-#define DSI_VVSACCR_VSA8                  0x00000100U
-#define DSI_VVSACCR_VSA9                  0x00000200U
-
-/*******************  Bit definition for DSI_VVBPCCR register  ************/
-#define DSI_VVBPCCR_VBP                0x000003FFU               /*!< Vertical Back-Porch duration */
-#define DSI_VVBPCCR_VBP0               0x00000001U
-#define DSI_VVBPCCR_VBP1               0x00000002U
-#define DSI_VVBPCCR_VBP2               0x00000004U
-#define DSI_VVBPCCR_VBP3               0x00000008U
-#define DSI_VVBPCCR_VBP4               0x00000010U
-#define DSI_VVBPCCR_VBP5               0x00000020U
-#define DSI_VVBPCCR_VBP6               0x00000040U
-#define DSI_VVBPCCR_VBP7               0x00000080U
-#define DSI_VVBPCCR_VBP8               0x00000100U
-#define DSI_VVBPCCR_VBP9               0x00000200U
-
-/*******************  Bit definition for DSI_VVFPCCR register  ************/
-#define DSI_VVFPCCR_VFP                0x000003FFU               /*!< Vertical Front-Porch duration */
-#define DSI_VVFPCCR_VFP0               0x00000001U
-#define DSI_VVFPCCR_VFP1               0x00000002U
-#define DSI_VVFPCCR_VFP2               0x00000004U
-#define DSI_VVFPCCR_VFP3               0x00000008U
-#define DSI_VVFPCCR_VFP4               0x00000010U
-#define DSI_VVFPCCR_VFP5               0x00000020U
-#define DSI_VVFPCCR_VFP6               0x00000040U
-#define DSI_VVFPCCR_VFP7               0x00000080U
-#define DSI_VVFPCCR_VFP8               0x00000100U
-#define DSI_VVFPCCR_VFP9               0x00000200U
-
-/*******************  Bit definition for DSI_VVACCR register  *************/
-#define DSI_VVACCR_VA                  0x00003FFFU               /*!< Vertical Active duration */
-#define DSI_VVACCR_VA0                 0x00000001U
-#define DSI_VVACCR_VA1                 0x00000002U
-#define DSI_VVACCR_VA2                 0x00000004U
-#define DSI_VVACCR_VA3                 0x00000008U
-#define DSI_VVACCR_VA4                 0x00000010U
-#define DSI_VVACCR_VA5                 0x00000020U
-#define DSI_VVACCR_VA6                 0x00000040U
-#define DSI_VVACCR_VA7                 0x00000080U
-#define DSI_VVACCR_VA8                 0x00000100U
-#define DSI_VVACCR_VA9                 0x00000200U
-#define DSI_VVACCR_VA10                0x00000400U
-#define DSI_VVACCR_VA11                0x00000800U
-#define DSI_VVACCR_VA12                0x00001000U
-#define DSI_VVACCR_VA13                0x00002000U
-
-/*******************  Bit definition for DSI_TDCCR register  **************/
-#define DSI_TDCCR_3DM                  0x00000003U               /*!< 3D Mode */
-#define DSI_TDCCR_3DM0                 0x00000001U
-#define DSI_TDCCR_3DM1                 0x00000002U
-
-#define DSI_TDCCR_3DF                  0x0000000CU               /*!< 3D Format */
-#define DSI_TDCCR_3DF0                 0x00000004U
-#define DSI_TDCCR_3DF1                 0x00000008U
-
-#define DSI_TDCCR_SVS                  0x00000010U               /*!< Second VSYNC */
-#define DSI_TDCCR_RF                   0x00000020U               /*!< Right First */
-#define DSI_TDCCR_S3DC                 0x00010000U               /*!< Send 3D Control */
-
-/*******************  Bit definition for DSI_WCFGR register  ***************/
-#define DSI_WCFGR_DSIM                   0x00000001U              /*!< DSI Mode */
-#define DSI_WCFGR_COLMUX                 0x0000000EU              /*!< Color Multiplexing */
-#define DSI_WCFGR_COLMUX0                0x00000002U
-#define DSI_WCFGR_COLMUX1                0x00000004U
-#define DSI_WCFGR_COLMUX2                0x00000008U
-
-#define DSI_WCFGR_TESRC                  0x00000010U              /*!< Tearing Effect Source */
-#define DSI_WCFGR_TEPOL                  0x00000020U              /*!< Tearing Effect Polarity */
-#define DSI_WCFGR_AR                     0x00000040U              /*!< Automatic Refresh */
-#define DSI_WCFGR_VSPOL                  0x00000080U              /*!< VSync Polarity */
-
-/*******************  Bit definition for DSI_WCR register  *****************/
-#define DSI_WCR_COLM                     0x00000001U              /*!< Color Mode */
-#define DSI_WCR_SHTDN                    0x00000002U              /*!< Shutdown */
-#define DSI_WCR_LTDCEN                   0x00000004U              /*!< LTDC Enable */
-#define DSI_WCR_DSIEN                    0x00000008U              /*!< DSI Enable */
-
-/*******************  Bit definition for DSI_WIER register  ****************/
-#define DSI_WIER_TEIE                    0x00000001U              /*!< Tearing Effect Interrupt Enable */
-#define DSI_WIER_ERIE                    0x00000002U              /*!< End of Refresh Interrupt Enable */
-#define DSI_WIER_PLLLIE                  0x00000200U              /*!< PLL Lock Interrupt Enable */
-#define DSI_WIER_PLLUIE                  0x00000400U              /*!< PLL Unlock Interrupt Enable */
-#define DSI_WIER_RRIE                    0x00002000U              /*!< Regulator Ready Interrupt Enable */
-
-/*******************  Bit definition for DSI_WISR register  ****************/
-#define DSI_WISR_TEIF                    0x00000001U              /*!< Tearing Effect Interrupt Flag */
-#define DSI_WISR_ERIF                    0x00000002U              /*!< End of Refresh Interrupt Flag */
-#define DSI_WISR_BUSY                    0x00000004U              /*!< Busy Flag */
-#define DSI_WISR_PLLLS                   0x00000100U              /*!< PLL Lock Status */
-#define DSI_WISR_PLLLIF                  0x00000200U              /*!< PLL Lock Interrupt Flag */
-#define DSI_WISR_PLLUIF                  0x00000400U              /*!< PLL Unlock Interrupt Flag */
-#define DSI_WISR_RRS                     0x00001000U              /*!< Regulator Ready Flag */
-#define DSI_WISR_RRIF                    0x00002000U              /*!< Regulator Ready Interrupt Flag */
-
-/*******************  Bit definition for DSI_WIFCR register  ***************/
-#define DSI_WIFCR_CTEIF                  0x00000001U              /*!< Clear Tearing Effect Interrupt Flag */
-#define DSI_WIFCR_CERIF                  0x00000002U              /*!< Clear End of Refresh Interrupt Flag */
-#define DSI_WIFCR_CPLLLIF                0x00000200U              /*!< Clear PLL Lock Interrupt Flag */
-#define DSI_WIFCR_CPLLUIF                0x00000400U              /*!< Clear PLL Unlock Interrupt Flag */
-#define DSI_WIFCR_CRRIF                  0x00002000U              /*!< Clear Regulator Ready Interrupt Flag */
-
-/*******************  Bit definition for DSI_WPCR0 register  ***************/
-#define DSI_WPCR0_UIX4                   0x0000003FU              /*!< Unit Interval multiplied by 4 */
-#define DSI_WPCR0_UIX4_0                 0x00000001U
-#define DSI_WPCR0_UIX4_1                 0x00000002U
-#define DSI_WPCR0_UIX4_2                 0x00000004U
-#define DSI_WPCR0_UIX4_3                 0x00000008U
-#define DSI_WPCR0_UIX4_4                 0x00000010U
-#define DSI_WPCR0_UIX4_5                 0x00000020U
-
-#define DSI_WPCR0_SWCL                   0x00000040U              /*!< Swap pins on clock lane */
-#define DSI_WPCR0_SWDL0                  0x00000080U              /*!< Swap pins on data lane 1 */
-#define DSI_WPCR0_SWDL1                  0x00000100U              /*!< Swap pins on data lane 2 */
-#define DSI_WPCR0_HSICL                  0x00000200U              /*!< Invert the high-speed data signal on clock lane */
-#define DSI_WPCR0_HSIDL0                 0x00000400U              /*!< Invert the high-speed data signal on lane 1 */
-#define DSI_WPCR0_HSIDL1                 0x00000800U              /*!< Invert the high-speed data signal on lane 2 */
-#define DSI_WPCR0_FTXSMCL                0x00001000U              /*!< Force clock lane in TX stop mode */
-#define DSI_WPCR0_FTXSMDL                0x00002000U              /*!< Force data lanes in TX stop mode */
-#define DSI_WPCR0_CDOFFDL                0x00004000U              /*!< Contention detection OFF */
-#define DSI_WPCR0_TDDL                   0x00010000U              /*!< Turn Disable Data Lanes */
-#define DSI_WPCR0_PDEN                   0x00040000U              /*!< Pull-Down Enable */
-#define DSI_WPCR0_TCLKPREPEN             0x00080000U              /*!< Timer for t-CLKPREP Enable */
-#define DSI_WPCR0_TCLKZEROEN             0x00100000U              /*!< Timer for t-CLKZERO Enable */
-#define DSI_WPCR0_THSPREPEN              0x00200000U              /*!< Timer for t-HSPREP Enable */
-#define DSI_WPCR0_THSTRAILEN             0x00400000U              /*!< Timer for t-HSTRAIL Enable */
-#define DSI_WPCR0_THSZEROEN              0x00800000U              /*!< Timer for t-HSZERO Enable */
-#define DSI_WPCR0_TLPXDEN                0x01000000U              /*!< Timer for t-LPXD Enable */
-#define DSI_WPCR0_THSEXITEN              0x02000000U              /*!< Timer for t-HSEXIT Enable */
-#define DSI_WPCR0_TLPXCEN                0x04000000U              /*!< Timer for t-LPXC Enable */
-#define DSI_WPCR0_TCLKPOSTEN             0x08000000U              /*!< Timer for t-CLKPOST Enable */
-
-/*******************  Bit definition for DSI_WPCR1 register  ***************/
-#define DSI_WPCR1_HSTXDCL                0x00000003U              /*!< High-Speed Transmission Delay on Clock Lane */
-#define DSI_WPCR1_HSTXDCL0               0x00000001U
-#define DSI_WPCR1_HSTXDCL1               0x00000002U
-
-#define DSI_WPCR1_HSTXDDL                0x0000000CU              /*!< High-Speed Transmission Delay on Data Lane */
-#define DSI_WPCR1_HSTXDDL0               0x00000004U
-#define DSI_WPCR1_HSTXDDL1               0x00000008U
-
-#define DSI_WPCR1_LPSRCCL                0x000000C0U              /*!< Low-Power transmission Slew Rate Compensation on Clock Lane */
-#define DSI_WPCR1_LPSRCCL0               0x00000040U
-#define DSI_WPCR1_LPSRCCL1               0x00000080U
-
-#define DSI_WPCR1_LPSRCDL                0x00000300U              /*!< Low-Power transmission Slew Rate Compensation on Data Lane */
-#define DSI_WPCR1_LPSRCDL0               0x00000100U
-#define DSI_WPCR1_LPSRCDL1               0x00000200U
-
-#define DSI_WPCR1_SDDC                   0x00001000U              /*!< SDD Control */
-
-#define DSI_WPCR1_LPRXVCDL               0x0000C000U              /*!< Low-Power Reception V-IL Compensation on Data Lanes */
-#define DSI_WPCR1_LPRXVCDL0              0x00004000U
-#define DSI_WPCR1_LPRXVCDL1              0x00008000U
-
-#define DSI_WPCR1_HSTXSRCCL              0x00030000U              /*!< High-Speed Transmission Delay on Clock Lane */
-#define DSI_WPCR1_HSTXSRCCL0             0x00010000U
-#define DSI_WPCR1_HSTXSRCCL1             0x00020000U
-
-#define DSI_WPCR1_HSTXSRCDL              0x000C0000U              /*!< High-Speed Transmission Delay on Data Lane */
-#define DSI_WPCR1_HSTXSRCDL0             0x00040000U
-#define DSI_WPCR1_HSTXSRCDL1             0x00080000U
-
-#define DSI_WPCR1_FLPRXLPM               0x00400000U              /*!< Forces LP Receiver in Low-Power Mode */
-
-#define DSI_WPCR1_LPRXFT                 0x06000000U              /*!< Low-Power RX low-pass Filtering Tuning */
-#define DSI_WPCR1_LPRXFT0                0x02000000U
-#define DSI_WPCR1_LPRXFT1                0x04000000U
-
-/*******************  Bit definition for DSI_WPCR2 register  ***************/
-#define DSI_WPCR2_TCLKPREP               0x000000FFU              /*!< t-CLKPREP */
-#define DSI_WPCR2_TCLKPREP0              0x00000001U
-#define DSI_WPCR2_TCLKPREP1              0x00000002U
-#define DSI_WPCR2_TCLKPREP2              0x00000004U
-#define DSI_WPCR2_TCLKPREP3              0x00000008U
-#define DSI_WPCR2_TCLKPREP4              0x00000010U
-#define DSI_WPCR2_TCLKPREP5              0x00000020U
-#define DSI_WPCR2_TCLKPREP6              0x00000040U
-#define DSI_WPCR2_TCLKPREP7              0x00000080U
-
-#define DSI_WPCR2_TCLKZERO               0x0000FF00U              /*!< t-CLKZERO */
-#define DSI_WPCR2_TCLKZERO0              0x00000100U
-#define DSI_WPCR2_TCLKZERO1              0x00000200U
-#define DSI_WPCR2_TCLKZERO2              0x00000400U
-#define DSI_WPCR2_TCLKZERO3              0x00000800U
-#define DSI_WPCR2_TCLKZERO4              0x00001000U
-#define DSI_WPCR2_TCLKZERO5              0x00002000U
-#define DSI_WPCR2_TCLKZERO6              0x00004000U
-#define DSI_WPCR2_TCLKZERO7              0x00008000U
-
-#define DSI_WPCR2_THSPREP                0x00FF0000U              /*!< t-HSPREP */
-#define DSI_WPCR2_THSPREP0               0x00010000U
-#define DSI_WPCR2_THSPREP1               0x00020000U
-#define DSI_WPCR2_THSPREP2               0x00040000U
-#define DSI_WPCR2_THSPREP3               0x00080000U
-#define DSI_WPCR2_THSPREP4               0x00100000U
-#define DSI_WPCR2_THSPREP5               0x00200000U
-#define DSI_WPCR2_THSPREP6               0x00400000U
-#define DSI_WPCR2_THSPREP7               0x00800000U
-
-#define DSI_WPCR2_THSTRAIL               0xFF000000U              /*!< t-HSTRAIL */
-#define DSI_WPCR2_THSTRAIL0              0x01000000U
-#define DSI_WPCR2_THSTRAIL1              0x02000000U
-#define DSI_WPCR2_THSTRAIL2              0x04000000U
-#define DSI_WPCR2_THSTRAIL3              0x08000000U
-#define DSI_WPCR2_THSTRAIL4              0x10000000U
-#define DSI_WPCR2_THSTRAIL5              0x20000000U
-#define DSI_WPCR2_THSTRAIL6              0x40000000U
-#define DSI_WPCR2_THSTRAIL7              0x80000000U
-
-/*******************  Bit definition for DSI_WPCR3 register  ***************/
-#define DSI_WPCR3_THSZERO                0x000000FFU              /*!< t-HSZERO */
-#define DSI_WPCR3_THSZERO0               0x00000001U
-#define DSI_WPCR3_THSZERO1               0x00000002U
-#define DSI_WPCR3_THSZERO2               0x00000004U
-#define DSI_WPCR3_THSZERO3               0x00000008U
-#define DSI_WPCR3_THSZERO4               0x00000010U
-#define DSI_WPCR3_THSZERO5               0x00000020U
-#define DSI_WPCR3_THSZERO6               0x00000040U
-#define DSI_WPCR3_THSZERO7               0x00000080U
-
-#define DSI_WPCR3_TLPXD                  0x0000FF00U              /*!< t-LPXD */
-#define DSI_WPCR3_TLPXD0                 0x00000100U
-#define DSI_WPCR3_TLPXD1                 0x00000200U
-#define DSI_WPCR3_TLPXD2                 0x00000400U
-#define DSI_WPCR3_TLPXD3                 0x00000800U
-#define DSI_WPCR3_TLPXD4                 0x00001000U
-#define DSI_WPCR3_TLPXD5                 0x00002000U
-#define DSI_WPCR3_TLPXD6                 0x00004000U
-#define DSI_WPCR3_TLPXD7                 0x00008000U
-
-#define DSI_WPCR3_THSEXIT                0x00FF0000U              /*!< t-HSEXIT */
-#define DSI_WPCR3_THSEXIT0               0x00010000U
-#define DSI_WPCR3_THSEXIT1               0x00020000U
-#define DSI_WPCR3_THSEXIT2               0x00040000U
-#define DSI_WPCR3_THSEXIT3               0x00080000U
-#define DSI_WPCR3_THSEXIT4               0x00100000U
-#define DSI_WPCR3_THSEXIT5               0x00200000U
-#define DSI_WPCR3_THSEXIT6               0x00400000U
-#define DSI_WPCR3_THSEXIT7               0x00800000U
-
-#define DSI_WPCR3_TLPXC                  0xFF000000U              /*!< t-LPXC */
-#define DSI_WPCR3_TLPXC0                 0x01000000U
-#define DSI_WPCR3_TLPXC1                 0x02000000U
-#define DSI_WPCR3_TLPXC2                 0x04000000U
-#define DSI_WPCR3_TLPXC3                 0x08000000U
-#define DSI_WPCR3_TLPXC4                 0x10000000U
-#define DSI_WPCR3_TLPXC5                 0x20000000U
-#define DSI_WPCR3_TLPXC6                 0x40000000U
-#define DSI_WPCR3_TLPXC7                 0x80000000U
-
-/*******************  Bit definition for DSI_WPCR4 register  ***************/
-#define DSI_WPCR4_TCLKPOST               0x000000FFU              /*!< t-CLKPOST */
-#define DSI_WPCR4_TCLKPOST0              0x00000001U
-#define DSI_WPCR4_TCLKPOST1              0x00000002U
-#define DSI_WPCR4_TCLKPOST2              0x00000004U
-#define DSI_WPCR4_TCLKPOST3              0x00000008U
-#define DSI_WPCR4_TCLKPOST4              0x00000010U
-#define DSI_WPCR4_TCLKPOST5              0x00000020U
-#define DSI_WPCR4_TCLKPOST6              0x00000040U
-#define DSI_WPCR4_TCLKPOST7              0x00000080U
-
-/*******************  Bit definition for DSI_WRPCR register  ***************/
-#define DSI_WRPCR_PLLEN                  0x00000001U              /*!< PLL Enable */
-#define DSI_WRPCR_PLL_NDIV               0x000001FCU              /*!< PLL Loop Division Factor */
-#define DSI_WRPCR_PLL_NDIV0              0x00000004U
-#define DSI_WRPCR_PLL_NDIV1              0x00000008U
-#define DSI_WRPCR_PLL_NDIV2              0x00000010U
-#define DSI_WRPCR_PLL_NDIV3              0x00000020U
-#define DSI_WRPCR_PLL_NDIV4              0x00000040U
-#define DSI_WRPCR_PLL_NDIV5              0x00000080U
-#define DSI_WRPCR_PLL_NDIV6              0x00000100U
-
-#define DSI_WRPCR_PLL_IDF                0x00007800U              /*!< PLL Input Division Factor */
-#define DSI_WRPCR_PLL_IDF0               0x00000800U
-#define DSI_WRPCR_PLL_IDF1               0x00001000U
-#define DSI_WRPCR_PLL_IDF2               0x00002000U
-#define DSI_WRPCR_PLL_IDF3               0x00004000U
-
-#define DSI_WRPCR_PLL_ODF                0x00030000U              /*!< PLL Output Division Factor */
-#define DSI_WRPCR_PLL_ODF0               0x00010000U
-#define DSI_WRPCR_PLL_ODF1               0x00020000U
-
-#define DSI_WRPCR_REGEN                  0x01000000U              /*!< Regulator Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                    External Interrupt/Event Controller                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    FLASH                                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    0x0000000FU
-#define FLASH_ACR_LATENCY_0WS                0x00000000U
-#define FLASH_ACR_LATENCY_1WS                0x00000001U
-#define FLASH_ACR_LATENCY_2WS                0x00000002U
-#define FLASH_ACR_LATENCY_3WS                0x00000003U
-#define FLASH_ACR_LATENCY_4WS                0x00000004U
-#define FLASH_ACR_LATENCY_5WS                0x00000005U
-#define FLASH_ACR_LATENCY_6WS                0x00000006U
-#define FLASH_ACR_LATENCY_7WS                0x00000007U
-#define FLASH_ACR_LATENCY_8WS                0x00000008U
-#define FLASH_ACR_LATENCY_9WS                0x00000009U
-#define FLASH_ACR_LATENCY_10WS               0x0000000AU
-#define FLASH_ACR_LATENCY_11WS               0x0000000BU
-#define FLASH_ACR_LATENCY_12WS               0x0000000CU
-#define FLASH_ACR_LATENCY_13WS               0x0000000DU
-#define FLASH_ACR_LATENCY_14WS               0x0000000EU
-#define FLASH_ACR_LATENCY_15WS               0x0000000FU
-#define FLASH_ACR_PRFTEN                     0x00000100U
-#define FLASH_ACR_ICEN                       0x00000200U
-#define FLASH_ACR_DCEN                       0x00000400U
-#define FLASH_ACR_ICRST                      0x00000800U
-#define FLASH_ACR_DCRST                      0x00001000U
-#define FLASH_ACR_BYTE0_ADDRESS              0x40023C00U
-#define FLASH_ACR_BYTE2_ADDRESS              0x40023C03U
-
-/*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         0x00000001U
-#define FLASH_SR_SOP                         0x00000002U
-#define FLASH_SR_WRPERR                      0x00000010U
-#define FLASH_SR_PGAERR                      0x00000020U
-#define FLASH_SR_PGPERR                      0x00000040U
-#define FLASH_SR_PGSERR                      0x00000080U
-#define FLASH_SR_BSY                         0x00010000U
-
-/*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          0x00000001U
-#define FLASH_CR_SER                         0x00000002U
-#define FLASH_CR_MER                         0x00000004U
-#define FLASH_CR_MER1                        FLASH_CR_MER
-#define FLASH_CR_SNB                         0x000000F8U
-#define FLASH_CR_SNB_0                       0x00000008U
-#define FLASH_CR_SNB_1                       0x00000010U
-#define FLASH_CR_SNB_2                       0x00000020U
-#define FLASH_CR_SNB_3                       0x00000040U
-#define FLASH_CR_SNB_4                       0x00000080U
-#define FLASH_CR_PSIZE                       0x00000300U
-#define FLASH_CR_PSIZE_0                     0x00000100U
-#define FLASH_CR_PSIZE_1                     0x00000200U
-#define FLASH_CR_MER2                        0x00008000U
-#define FLASH_CR_STRT                        0x00010000U
-#define FLASH_CR_EOPIE                       0x01000000U
-#define FLASH_CR_LOCK                        0x80000000U
-
-/*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                 0x00000001U
-#define FLASH_OPTCR_OPTSTRT                 0x00000002U
-#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
-#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
-#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
-#define FLASH_OPTCR_BFB2                    0x00000010U
-#define FLASH_OPTCR_WDG_SW                  0x00000020U
-#define FLASH_OPTCR_nRST_STOP               0x00000040U
-#define FLASH_OPTCR_nRST_STDBY              0x00000080U
-#define FLASH_OPTCR_RDP                     0x0000FF00U
-#define FLASH_OPTCR_RDP_0                   0x00000100U
-#define FLASH_OPTCR_RDP_1                   0x00000200U
-#define FLASH_OPTCR_RDP_2                   0x00000400U
-#define FLASH_OPTCR_RDP_3                   0x00000800U
-#define FLASH_OPTCR_RDP_4                   0x00001000U
-#define FLASH_OPTCR_RDP_5                   0x00002000U
-#define FLASH_OPTCR_RDP_6                   0x00004000U
-#define FLASH_OPTCR_RDP_7                   0x00008000U
-#define FLASH_OPTCR_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR_nWRP_0                  0x00010000U
-#define FLASH_OPTCR_nWRP_1                  0x00020000U
-#define FLASH_OPTCR_nWRP_2                  0x00040000U
-#define FLASH_OPTCR_nWRP_3                  0x00080000U
-#define FLASH_OPTCR_nWRP_4                  0x00100000U
-#define FLASH_OPTCR_nWRP_5                  0x00200000U
-#define FLASH_OPTCR_nWRP_6                  0x00400000U
-#define FLASH_OPTCR_nWRP_7                  0x00800000U
-#define FLASH_OPTCR_nWRP_8                  0x01000000U
-#define FLASH_OPTCR_nWRP_9                  0x02000000U
-#define FLASH_OPTCR_nWRP_10                 0x04000000U
-#define FLASH_OPTCR_nWRP_11                 0x08000000U
-#define FLASH_OPTCR_DB1M                    0x40000000U 
-#define FLASH_OPTCR_SPRMOD                  0x80000000U 
-                                             
-/******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR1_nWRP_0                  0x00010000U
-#define FLASH_OPTCR1_nWRP_1                  0x00020000U
-#define FLASH_OPTCR1_nWRP_2                  0x00040000U
-#define FLASH_OPTCR1_nWRP_3                  0x00080000U
-#define FLASH_OPTCR1_nWRP_4                  0x00100000U
-#define FLASH_OPTCR1_nWRP_5                  0x00200000U
-#define FLASH_OPTCR1_nWRP_6                  0x00400000U
-#define FLASH_OPTCR1_nWRP_7                  0x00800000U
-#define FLASH_OPTCR1_nWRP_8                  0x01000000U
-#define FLASH_OPTCR1_nWRP_9                  0x02000000U
-#define FLASH_OPTCR1_nWRP_10                 0x04000000U
-#define FLASH_OPTCR1_nWRP_11                 0x08000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Flexible Memory Controller                        */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for FMC_BCR1 register  *******************/
-#define  FMC_BCR1_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR1_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FMC_BCR1_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR1_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR1_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FMC_BCR1_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR1_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR1_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_BCR1_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR1_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR1_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR1_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR1_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR1_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR1_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR1_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR1_CPSIZE                    0x00070000U        /*!<CRAM page size             */
-#define  FMC_BCR1_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FMC_BCR1_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FMC_BCR1_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FMC_BCR1_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-#define  FMC_BCR1_CCLKEN                    0x00100000U        /*!<Continous clock enable     */
-#define  FMC_BCR1_WFDIS                     0x00200000U        /*!<Write FIFO Disable         */
-
-/******************  Bit definition for FMC_BCR2 register  *******************/
-#define  FMC_BCR2_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR2_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FMC_BCR2_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR2_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR2_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FMC_BCR2_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR2_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR2_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_BCR2_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR2_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR2_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR2_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR2_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR2_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR2_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR2_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR2_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FMC_BCR3 register  *******************/
-#define  FMC_BCR3_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR3_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FMC_BCR3_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR3_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR3_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FMC_BCR3_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR3_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR3_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_BCR3_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR3_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR3_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR3_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR3_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR3_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR3_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR3_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR3_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FMC_BCR4 register  *******************/
-#define  FMC_BCR4_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR4_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FMC_BCR4_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR4_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR4_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FMC_BCR4_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR4_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR4_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_BCR4_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR4_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR4_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR4_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR4_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR4_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR4_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR4_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR4_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FMC_BTR1 register  ******************/
-#define  FMC_BTR1_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR1_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR1_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR1_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR1_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BTR1_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
-#define  FMC_BTR1_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR1_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR1_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR1_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BTR1_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR1_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR1_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR1_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR1_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR1_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR1_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR1_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR1_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BTR1_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR1_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR1_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR1_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR1_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BTR1_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR1_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR1_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR1_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR1_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FMC_BTR1_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR1_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR1_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR1_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR1_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FMC_BTR1_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR1_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR1_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BTR2 register  *******************/
-#define  FMC_BTR2_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR2_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR2_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR2_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR2_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BTR2_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR2_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR2_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR2_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR2_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BTR2_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR2_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR2_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR2_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR2_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR2_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR2_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR2_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR2_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BTR2_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR2_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR2_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR2_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR2_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BTR2_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR2_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR2_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR2_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR2_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FMC_BTR2_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR2_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR2_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR2_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR2_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FMC_BTR2_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR2_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR2_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/*******************  Bit definition for FMC_BTR3 register  *******************/
-#define  FMC_BTR3_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR3_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR3_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR3_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR3_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BTR3_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR3_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR3_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR3_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR3_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BTR3_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR3_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR3_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR3_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR3_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR3_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR3_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR3_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR3_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BTR3_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR3_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR3_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR3_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR3_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BTR3_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR3_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR3_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR3_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR3_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FMC_BTR3_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR3_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR3_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR3_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR3_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FMC_BTR3_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR3_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR3_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BTR4 register  *******************/
-#define  FMC_BTR4_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR4_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR4_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR4_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR4_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BTR4_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR4_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR4_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR4_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR4_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BTR4_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR4_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR4_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR4_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR4_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR4_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR4_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR4_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR4_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BTR4_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR4_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR4_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR4_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR4_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BTR4_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR4_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR4_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR4_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR4_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FMC_BTR4_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR4_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR4_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR4_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR4_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FMC_BTR4_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR4_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR4_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR1 register  ******************/
-#define  FMC_BWTR1_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR1_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR1_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR1_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR1_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BWTR1_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR1_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR1_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR1_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR1_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BWTR1_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR1_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR1_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR1_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR1_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR1_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR1_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR1_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR1_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BWTR1_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR1_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR1_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR1_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR1_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BWTR1_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR1_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR1_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR2 register  ******************/
-#define  FMC_BWTR2_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR2_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR2_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR2_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR2_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BWTR2_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR2_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR2_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR2_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR2_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BWTR2_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR2_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR2_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR2_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR2_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR2_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR2_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR2_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR2_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BWTR2_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR2_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR2_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR2_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR2_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BWTR2_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR2_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR2_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR3 register  ******************/
-#define  FMC_BWTR3_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR3_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR3_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR3_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR3_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BWTR3_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR3_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR3_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR3_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR3_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BWTR3_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR3_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR3_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR3_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR3_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR3_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR3_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR3_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR3_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BWTR3_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR3_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR3_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR3_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR3_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BWTR3_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR3_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR3_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR4 register  ******************/
-#define  FMC_BWTR4_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR4_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR4_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR4_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR4_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BWTR4_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR4_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR4_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR4_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR4_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BWTR4_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR4_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR4_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR4_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR4_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR4_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR4_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR4_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR4_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BWTR4_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR4_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR4_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR4_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR4_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BWTR4_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR4_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR4_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_PCR register  *******************/
-#define  FMC_PCR_PWAITEN                   0x00000002U        /*!<Wait feature enable bit                   */
-#define  FMC_PCR_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FMC_PCR_PTYP                      0x00000008U        /*!<Memory type                               */
-
-#define  FMC_PCR_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FMC_PCR_PWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_PCR_PWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_PCR_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit          */
-
-#define  FMC_PCR_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay)          */
-#define  FMC_PCR_TCLR_0                    0x00000200U        /*!<Bit 0 */
-#define  FMC_PCR_TCLR_1                    0x00000400U        /*!<Bit 1 */
-#define  FMC_PCR_TCLR_2                    0x00000800U        /*!<Bit 2 */
-#define  FMC_PCR_TCLR_3                    0x00001000U        /*!<Bit 3 */
-
-#define  FMC_PCR_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay)           */
-#define  FMC_PCR_TAR_0                     0x00002000U        /*!<Bit 0 */
-#define  FMC_PCR_TAR_1                     0x00004000U        /*!<Bit 1 */
-#define  FMC_PCR_TAR_2                     0x00008000U        /*!<Bit 2 */
-#define  FMC_PCR_TAR_3                     0x00010000U        /*!<Bit 3 */
-
-#define  FMC_PCR_ECCPS                     0x000E0000U        /*!<ECCPS[1:0] bits (ECC page size)           */
-#define  FMC_PCR_ECCPS_0                   0x00020000U        /*!<Bit 0 */
-#define  FMC_PCR_ECCPS_1                   0x00040000U        /*!<Bit 1 */
-#define  FMC_PCR_ECCPS_2                   0x00080000U        /*!<Bit 2 */
-
-/*******************  Bit definition for FMC_SR register  *******************/
-#define  FMC_SR_IRS                        0x01U               /*!<Interrupt Rising Edge status                */
-#define  FMC_SR_ILS                        0x02U               /*!<Interrupt Level status                      */
-#define  FMC_SR_IFS                        0x04U               /*!<Interrupt Falling Edge status               */
-#define  FMC_SR_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FMC_SR_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit        */
-#define  FMC_SR_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FMC_SR_FEMPT                      0x40U               /*!<FIFO empty                                  */
-
-/******************  Bit definition for FMC_PMEM register  ******************/
-#define  FMC_PMEM_MEMSET2                  0x000000FFU        /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
-#define  FMC_PMEM_MEMSET2_0                0x00000001U        /*!<Bit 0 */
-#define  FMC_PMEM_MEMSET2_1                0x00000002U        /*!<Bit 1 */
-#define  FMC_PMEM_MEMSET2_2                0x00000004U        /*!<Bit 2 */
-#define  FMC_PMEM_MEMSET2_3                0x00000008U        /*!<Bit 3 */
-#define  FMC_PMEM_MEMSET2_4                0x00000010U        /*!<Bit 4 */
-#define  FMC_PMEM_MEMSET2_5                0x00000020U        /*!<Bit 5 */
-#define  FMC_PMEM_MEMSET2_6                0x00000040U        /*!<Bit 6 */
-#define  FMC_PMEM_MEMSET2_7                0x00000080U        /*!<Bit 7 */
-
-#define  FMC_PMEM_MEMWAIT2                 0x0000FF00U        /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
-#define  FMC_PMEM_MEMWAIT2_0               0x00000100U        /*!<Bit 0 */
-#define  FMC_PMEM_MEMWAIT2_1               0x00000200U        /*!<Bit 1 */
-#define  FMC_PMEM_MEMWAIT2_2               0x00000400U        /*!<Bit 2 */
-#define  FMC_PMEM_MEMWAIT2_3               0x00000800U        /*!<Bit 3 */
-#define  FMC_PMEM_MEMWAIT2_4               0x00001000U        /*!<Bit 4 */
-#define  FMC_PMEM_MEMWAIT2_5               0x00002000U        /*!<Bit 5 */
-#define  FMC_PMEM_MEMWAIT2_6               0x00004000U        /*!<Bit 6 */
-#define  FMC_PMEM_MEMWAIT2_7               0x00008000U        /*!<Bit 7 */
-
-#define  FMC_PMEM_MEMHOLD2                 0x00FF0000U        /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
-#define  FMC_PMEM_MEMHOLD2_0               0x00010000U        /*!<Bit 0 */
-#define  FMC_PMEM_MEMHOLD2_1               0x00020000U        /*!<Bit 1 */
-#define  FMC_PMEM_MEMHOLD2_2               0x00040000U        /*!<Bit 2 */
-#define  FMC_PMEM_MEMHOLD2_3               0x00080000U        /*!<Bit 3 */
-#define  FMC_PMEM_MEMHOLD2_4               0x00100000U        /*!<Bit 4 */
-#define  FMC_PMEM_MEMHOLD2_5               0x00200000U        /*!<Bit 5 */
-#define  FMC_PMEM_MEMHOLD2_6               0x00400000U        /*!<Bit 6 */
-#define  FMC_PMEM_MEMHOLD2_7               0x00800000U        /*!<Bit 7 */
-
-#define  FMC_PMEM_MEMHIZ2                  0xFF000000U        /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
-#define  FMC_PMEM_MEMHIZ2_0                0x01000000U        /*!<Bit 0 */
-#define  FMC_PMEM_MEMHIZ2_1                0x02000000U        /*!<Bit 1 */
-#define  FMC_PMEM_MEMHIZ2_2                0x04000000U        /*!<Bit 2 */
-#define  FMC_PMEM_MEMHIZ2_3                0x08000000U        /*!<Bit 3 */
-#define  FMC_PMEM_MEMHIZ2_4                0x10000000U        /*!<Bit 4 */
-#define  FMC_PMEM_MEMHIZ2_5                0x20000000U        /*!<Bit 5 */
-#define  FMC_PMEM_MEMHIZ2_6                0x40000000U        /*!<Bit 6 */
-#define  FMC_PMEM_MEMHIZ2_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_PATT register  ******************/
-#define  FMC_PATT_ATTSET2                  0x000000FFU        /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
-#define  FMC_PATT_ATTSET2_0                0x00000001U        /*!<Bit 0 */
-#define  FMC_PATT_ATTSET2_1                0x00000002U        /*!<Bit 1 */
-#define  FMC_PATT_ATTSET2_2                0x00000004U        /*!<Bit 2 */
-#define  FMC_PATT_ATTSET2_3                0x00000008U        /*!<Bit 3 */
-#define  FMC_PATT_ATTSET2_4                0x00000010U        /*!<Bit 4 */
-#define  FMC_PATT_ATTSET2_5                0x00000020U        /*!<Bit 5 */
-#define  FMC_PATT_ATTSET2_6                0x00000040U        /*!<Bit 6 */
-#define  FMC_PATT_ATTSET2_7                0x00000080U        /*!<Bit 7 */
-
-#define  FMC_PATT_ATTWAIT2                 0x0000FF00U        /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
-#define  FMC_PATT_ATTWAIT2_0               0x00000100U        /*!<Bit 0 */
-#define  FMC_PATT_ATTWAIT2_1               0x00000200U        /*!<Bit 1 */
-#define  FMC_PATT_ATTWAIT2_2               0x00000400U        /*!<Bit 2 */
-#define  FMC_PATT_ATTWAIT2_3               0x00000800U        /*!<Bit 3 */
-#define  FMC_PATT_ATTWAIT2_4               0x00001000U        /*!<Bit 4 */
-#define  FMC_PATT_ATTWAIT2_5               0x00002000U        /*!<Bit 5 */
-#define  FMC_PATT_ATTWAIT2_6               0x00004000U        /*!<Bit 6 */
-#define  FMC_PATT_ATTWAIT2_7               0x00008000U        /*!<Bit 7 */
-
-#define  FMC_PATT_ATTHOLD2                 0x00FF0000U        /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
-#define  FMC_PATT_ATTHOLD2_0               0x00010000U        /*!<Bit 0 */
-#define  FMC_PATT_ATTHOLD2_1               0x00020000U        /*!<Bit 1 */
-#define  FMC_PATT_ATTHOLD2_2               0x00040000U        /*!<Bit 2 */
-#define  FMC_PATT_ATTHOLD2_3               0x00080000U        /*!<Bit 3 */
-#define  FMC_PATT_ATTHOLD2_4               0x00100000U        /*!<Bit 4 */
-#define  FMC_PATT_ATTHOLD2_5               0x00200000U        /*!<Bit 5 */
-#define  FMC_PATT_ATTHOLD2_6               0x00400000U        /*!<Bit 6 */
-#define  FMC_PATT_ATTHOLD2_7               0x00800000U        /*!<Bit 7 */
-
-#define  FMC_PATT_ATTHIZ2                  0xFF000000U        /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
-#define  FMC_PATT_ATTHIZ2_0                0x01000000U        /*!<Bit 0 */
-#define  FMC_PATT_ATTHIZ2_1                0x02000000U        /*!<Bit 1 */
-#define  FMC_PATT_ATTHIZ2_2                0x04000000U        /*!<Bit 2 */
-#define  FMC_PATT_ATTHIZ2_3                0x08000000U        /*!<Bit 3 */
-#define  FMC_PATT_ATTHIZ2_4                0x10000000U        /*!<Bit 4 */
-#define  FMC_PATT_ATTHIZ2_5                0x20000000U        /*!<Bit 5 */
-#define  FMC_PATT_ATTHIZ2_6                0x40000000U        /*!<Bit 6 */
-#define  FMC_PATT_ATTHIZ2_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_ECCR register  ******************/
-#define  FMC_ECCR_ECC2                     0xFFFFFFFFU        /*!<ECC result */
-
-/******************  Bit definition for FMC_SDCR1 register  ******************/
-#define  FMC_SDCR1_NC                       0x00000003U        /*!<NC[1:0] bits (Number of column bits) */
-#define  FMC_SDCR1_NC_0                     0x00000001U        /*!<Bit 0 */
-#define  FMC_SDCR1_NC_1                     0x00000002U        /*!<Bit 1 */
-
-#define  FMC_SDCR1_NR                       0x0000000CU        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR1_NR_0                     0x00000004U        /*!<Bit 0 */
-#define  FMC_SDCR1_NR_1                     0x00000008U        /*!<Bit 1 */
-
-#define  FMC_SDCR1_MWID                     0x00000030U        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR1_MWID_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDCR1_MWID_1                   0x00000020U        /*!<Bit 1 */
-
-#define  FMC_SDCR1_NB                       0x00000040U        /*!<Number of internal bank */
-
-#define  FMC_SDCR1_CAS                      0x00000180U        /*!<CAS[1:0] bits (CAS latency) */
-#define  FMC_SDCR1_CAS_0                    0x00000080U        /*!<Bit 0 */
-#define  FMC_SDCR1_CAS_1                    0x00000100U        /*!<Bit 1 */
-
-#define  FMC_SDCR1_WP                       0x00000200U        /*!<Write protection */
-
-#define  FMC_SDCR1_SDCLK                    0x00000C00U        /*!<SDRAM clock configuration */
-#define  FMC_SDCR1_SDCLK_0                  0x00000400U        /*!<Bit 0 */
-#define  FMC_SDCR1_SDCLK_1                  0x00000800U        /*!<Bit 1 */
-
-#define  FMC_SDCR1_RBURST                   0x00001000U        /*!<Read burst */
-
-#define  FMC_SDCR1_RPIPE                    0x00006000U        /*!<Write protection */
-#define  FMC_SDCR1_RPIPE_0                  0x00002000U        /*!<Bit 0 */
-#define  FMC_SDCR1_RPIPE_1                  0x00004000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_SDCR2 register  ******************/
-#define  FMC_SDCR2_NC                       0x00000003U        /*!<NC[1:0] bits (Number of column bits) */
-#define  FMC_SDCR2_NC_0                     0x00000001U        /*!<Bit 0 */
-#define  FMC_SDCR2_NC_1                     0x00000002U        /*!<Bit 1 */
-
-#define  FMC_SDCR2_NR                       0x0000000CU        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR2_NR_0                     0x00000004U        /*!<Bit 0 */
-#define  FMC_SDCR2_NR_1                     0x00000008U        /*!<Bit 1 */
-
-#define  FMC_SDCR2_MWID                     0x00000030U        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR2_MWID_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDCR2_MWID_1                   0x00000020U        /*!<Bit 1 */
-
-#define  FMC_SDCR2_NB                       0x00000040U        /*!<Number of internal bank */
-
-#define  FMC_SDCR2_CAS                      0x00000180U        /*!<CAS[1:0] bits (CAS latency) */
-#define  FMC_SDCR2_CAS_0                    0x00000080U        /*!<Bit 0 */
-#define  FMC_SDCR2_CAS_1                    0x00000100U        /*!<Bit 1 */
-
-#define  FMC_SDCR2_WP                       0x00000200U        /*!<Write protection */
-
-#define  FMC_SDCR2_SDCLK                    0x00000C00U        /*!<SDCLK[1:0] (SDRAM clock configuration) */
-#define  FMC_SDCR2_SDCLK_0                  0x00000400U        /*!<Bit 0 */
-#define  FMC_SDCR2_SDCLK_1                  0x00000800U        /*!<Bit 1 */
-
-#define  FMC_SDCR2_RBURST                   0x00001000U        /*!<Read burst */
-
-#define  FMC_SDCR2_RPIPE                    0x00006000U        /*!<RPIPE[1:0](Read pipe) */
-#define  FMC_SDCR2_RPIPE_0                  0x00002000U        /*!<Bit 0 */
-#define  FMC_SDCR2_RPIPE_1                  0x00004000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_SDTR1 register  ******************/
-#define  FMC_SDTR1_TMRD                     0x0000000FU        /*!<TMRD[3:0] bits (Load mode register to active) */
-#define  FMC_SDTR1_TMRD_0                   0x00000001U        /*!<Bit 0 */
-#define  FMC_SDTR1_TMRD_1                   0x00000002U        /*!<Bit 1 */
-#define  FMC_SDTR1_TMRD_2                   0x00000004U        /*!<Bit 2 */
-#define  FMC_SDTR1_TMRD_3                   0x00000008U        /*!<Bit 3 */
-                                            
-#define  FMC_SDTR1_TXSR                     0x000000F0U        /*!<TXSR[3:0] bits (Exit self refresh) */
-#define  FMC_SDTR1_TXSR_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDTR1_TXSR_1                   0x00000020U        /*!<Bit 1 */
-#define  FMC_SDTR1_TXSR_2                   0x00000040U        /*!<Bit 2 */
-#define  FMC_SDTR1_TXSR_3                   0x00000080U        /*!<Bit 3 */
-
-#define  FMC_SDTR1_TRAS                     0x00000F00U        /*!<TRAS[3:0] bits (Self refresh time) */
-#define  FMC_SDTR1_TRAS_0                   0x00000100U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRAS_1                   0x00000200U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRAS_2                   0x00000400U        /*!<Bit 2 */
-#define  FMC_SDTR1_TRAS_3                   0x00000800U        /*!<Bit 3 */
-
-#define  FMC_SDTR1_TRC                      0x0000F000U        /*!<TRC[2:0] bits (Row cycle delay) */
-#define  FMC_SDTR1_TRC_0                    0x00001000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRC_1                    0x00002000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRC_2                    0x00004000U        /*!<Bit 2 */
-
-#define  FMC_SDTR1_TWR                      0x000F0000U        /*!<TRC[2:0] bits (Write recovery delay) */
-#define  FMC_SDTR1_TWR_0                    0x00010000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TWR_1                    0x00020000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TWR_2                    0x00040000U        /*!<Bit 2 */
-
-#define  FMC_SDTR1_TRP                      0x00F00000U        /*!<TRP[2:0] bits (Row precharge delay) */
-#define  FMC_SDTR1_TRP_0                    0x00100000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRP_1                    0x00200000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRP_2                    0x00400000U        /*!<Bit 2 */
-
-#define  FMC_SDTR1_TRCD                     0x0F000000U        /*!<TRP[2:0] bits (Row to column delay) */
-#define  FMC_SDTR1_TRCD_0                   0x01000000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRCD_1                   0x02000000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRCD_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for FMC_SDTR2 register  ******************/
-#define  FMC_SDTR2_TMRD                     0x0000000FU        /*!<TMRD[3:0] bits (Load mode register to active) */
-#define  FMC_SDTR2_TMRD_0                   0x00000001U        /*!<Bit 0 */
-#define  FMC_SDTR2_TMRD_1                   0x00000002U        /*!<Bit 1 */
-#define  FMC_SDTR2_TMRD_2                   0x00000004U        /*!<Bit 2 */
-#define  FMC_SDTR2_TMRD_3                   0x00000008U        /*!<Bit 3 */
-                                            
-#define  FMC_SDTR2_TXSR                     0x000000F0U        /*!<TXSR[3:0] bits (Exit self refresh) */
-#define  FMC_SDTR2_TXSR_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDTR2_TXSR_1                   0x00000020U        /*!<Bit 1 */
-#define  FMC_SDTR2_TXSR_2                   0x00000040U        /*!<Bit 2 */
-#define  FMC_SDTR2_TXSR_3                   0x00000080U        /*!<Bit 3 */
-
-#define  FMC_SDTR2_TRAS                     0x00000F00U        /*!<TRAS[3:0] bits (Self refresh time) */
-#define  FMC_SDTR2_TRAS_0                   0x00000100U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRAS_1                   0x00000200U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRAS_2                   0x00000400U        /*!<Bit 2 */
-#define  FMC_SDTR2_TRAS_3                   0x00000800U        /*!<Bit 3 */
-
-#define  FMC_SDTR2_TRC                      0x0000F000U        /*!<TRC[2:0] bits (Row cycle delay) */
-#define  FMC_SDTR2_TRC_0                    0x00001000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRC_1                    0x00002000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRC_2                    0x00004000U        /*!<Bit 2 */
-
-#define  FMC_SDTR2_TWR                      0x000F0000U        /*!<TRC[2:0] bits (Write recovery delay) */
-#define  FMC_SDTR2_TWR_0                    0x00010000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TWR_1                    0x00020000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TWR_2                    0x00040000U        /*!<Bit 2 */
-
-#define  FMC_SDTR2_TRP                      0x00F00000U        /*!<TRP[2:0] bits (Row precharge delay) */
-#define  FMC_SDTR2_TRP_0                    0x00100000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRP_1                    0x00200000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRP_2                    0x00400000U        /*!<Bit 2 */
-
-#define  FMC_SDTR2_TRCD                     0x0F000000U        /*!<TRP[2:0] bits (Row to column delay) */
-#define  FMC_SDTR2_TRCD_0                   0x01000000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRCD_1                   0x02000000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRCD_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for FMC_SDCMR register  ******************/
-#define  FMC_SDCMR_MODE                     0x00000007U        /*!<MODE[2:0] bits (Command mode) */
-#define  FMC_SDCMR_MODE_0                   0x00000001U        /*!<Bit 0 */
-#define  FMC_SDCMR_MODE_1                   0x00000002U        /*!<Bit 1 */
-#define  FMC_SDCMR_MODE_2                   0x00000004U        /*!<Bit 2 */
-                                            
-#define  FMC_SDCMR_CTB2                     0x00000008U        /*!<Command target 2 */
-
-#define  FMC_SDCMR_CTB1                     0x00000010U        /*!<Command target 1 */
-
-#define  FMC_SDCMR_NRFS                     0x000001E0U        /*!<NRFS[3:0] bits (Number of auto-refresh) */
-#define  FMC_SDCMR_NRFS_0                   0x00000020U        /*!<Bit 0 */
-#define  FMC_SDCMR_NRFS_1                   0x00000040U        /*!<Bit 1 */
-#define  FMC_SDCMR_NRFS_2                   0x00000080U        /*!<Bit 2 */
-#define  FMC_SDCMR_NRFS_3                   0x00000100U        /*!<Bit 3 */
-
-#define  FMC_SDCMR_MRD                      0x003FFE00U        /*!<MRD[12:0] bits (Mode register definition) */
-
-/******************  Bit definition for FMC_SDRTR register  ******************/
-#define  FMC_SDRTR_CRE                      0x00000001U        /*!<Clear refresh error flag */
-
-#define  FMC_SDRTR_COUNT                    0x00003FFEU        /*!<COUNT[12:0] bits (Refresh timer count) */
-
-#define  FMC_SDRTR_REIE                     0x00004000U        /*!<RES interupt enable */
-
-/******************  Bit definition for FMC_SDSR register  ******************/
-#define  FMC_SDSR_RE                        0x00000001U        /*!<Refresh error flag */
-
-#define  FMC_SDSR_MODES1                    0x00000006U        /*!<MODES1[1:0]bits (Status mode for bank 1) */
-#define  FMC_SDSR_MODES1_0                  0x00000002U        /*!<Bit 0 */
-#define  FMC_SDSR_MODES1_1                  0x00000004U        /*!<Bit 1 */
-
-#define  FMC_SDSR_MODES2                    0x00000018U        /*!<MODES2[1:0]bits (Status mode for bank 2) */
-#define  FMC_SDSR_MODES2_0                  0x00000008U        /*!<Bit 0 */
-#define  FMC_SDSR_MODES2_1                  0x00000010U        /*!<Bit 1 */
-#define  FMC_SDSR_BUSY                      0x00000020U        /*!<Busy status */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    0x00000003U
-#define GPIO_MODER_MODER0_0                  0x00000001U
-#define GPIO_MODER_MODER0_1                  0x00000002U
-
-#define GPIO_MODER_MODER1                    0x0000000CU
-#define GPIO_MODER_MODER1_0                  0x00000004U
-#define GPIO_MODER_MODER1_1                  0x00000008U
-
-#define GPIO_MODER_MODER2                    0x00000030U
-#define GPIO_MODER_MODER2_0                  0x00000010U
-#define GPIO_MODER_MODER2_1                  0x00000020U
-
-#define GPIO_MODER_MODER3                    0x000000C0U
-#define GPIO_MODER_MODER3_0                  0x00000040U
-#define GPIO_MODER_MODER3_1                  0x00000080U
-
-#define GPIO_MODER_MODER4                    0x00000300U
-#define GPIO_MODER_MODER4_0                  0x00000100U
-#define GPIO_MODER_MODER4_1                  0x00000200U
-
-#define GPIO_MODER_MODER5                    0x00000C00U
-#define GPIO_MODER_MODER5_0                  0x00000400U
-#define GPIO_MODER_MODER5_1                  0x00000800U
-
-#define GPIO_MODER_MODER6                    0x00003000U
-#define GPIO_MODER_MODER6_0                  0x00001000U
-#define GPIO_MODER_MODER6_1                  0x00002000U
-
-#define GPIO_MODER_MODER7                    0x0000C000U
-#define GPIO_MODER_MODER7_0                  0x00004000U
-#define GPIO_MODER_MODER7_1                  0x00008000U
-
-#define GPIO_MODER_MODER8                    0x00030000U
-#define GPIO_MODER_MODER8_0                  0x00010000U
-#define GPIO_MODER_MODER8_1                  0x00020000U
-
-#define GPIO_MODER_MODER9                    0x000C0000U
-#define GPIO_MODER_MODER9_0                  0x00040000U
-#define GPIO_MODER_MODER9_1                  0x00080000U
-
-#define GPIO_MODER_MODER10                   0x00300000U
-#define GPIO_MODER_MODER10_0                 0x00100000U
-#define GPIO_MODER_MODER10_1                 0x00200000U
-
-#define GPIO_MODER_MODER11                   0x00C00000U
-#define GPIO_MODER_MODER11_0                 0x00400000U
-#define GPIO_MODER_MODER11_1                 0x00800000U
-
-#define GPIO_MODER_MODER12                   0x03000000U
-#define GPIO_MODER_MODER12_0                 0x01000000U
-#define GPIO_MODER_MODER12_1                 0x02000000U
-
-#define GPIO_MODER_MODER13                   0x0C000000U
-#define GPIO_MODER_MODER13_0                 0x04000000U
-#define GPIO_MODER_MODER13_1                 0x08000000U
-
-#define GPIO_MODER_MODER14                   0x30000000U
-#define GPIO_MODER_MODER14_0                 0x10000000U
-#define GPIO_MODER_MODER14_1                 0x20000000U
-
-#define GPIO_MODER_MODER15                   0xC0000000U
-#define GPIO_MODER_MODER15_0                 0x40000000U
-#define GPIO_MODER_MODER15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     0x00000001U
-#define GPIO_OTYPER_OT_1                     0x00000002U
-#define GPIO_OTYPER_OT_2                     0x00000004U
-#define GPIO_OTYPER_OT_3                     0x00000008U
-#define GPIO_OTYPER_OT_4                     0x00000010U
-#define GPIO_OTYPER_OT_5                     0x00000020U
-#define GPIO_OTYPER_OT_6                     0x00000040U
-#define GPIO_OTYPER_OT_7                     0x00000080U
-#define GPIO_OTYPER_OT_8                     0x00000100U
-#define GPIO_OTYPER_OT_9                     0x00000200U
-#define GPIO_OTYPER_OT_10                    0x00000400U
-#define GPIO_OTYPER_OT_11                    0x00000800U
-#define GPIO_OTYPER_OT_12                    0x00001000U
-#define GPIO_OTYPER_OT_13                    0x00002000U
-#define GPIO_OTYPER_OT_14                    0x00004000U
-#define GPIO_OTYPER_OT_15                    0x00008000U
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
-#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
-#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
-
-#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
-#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
-#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
-
-#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
-#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
-#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
-
-#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
-#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
-#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
-
-#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
-#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
-#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
-
-#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
-#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
-#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
-
-#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
-#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
-#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
-
-#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
-#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
-#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
-
-#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
-#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
-#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
-
-#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
-#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
-#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
-
-#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
-#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
-#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
-
-#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
-#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
-#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
-
-#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
-#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
-#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
-
-#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
-#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
-#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
-
-#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
-#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
-#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
-
-#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
-#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
-#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    0x00000003U
-#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
-#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
-
-#define GPIO_PUPDR_PUPDR1                    0x0000000CU
-#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
-#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
-
-#define GPIO_PUPDR_PUPDR2                    0x00000030U
-#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
-#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
-
-#define GPIO_PUPDR_PUPDR3                    0x000000C0U
-#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
-#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
-
-#define GPIO_PUPDR_PUPDR4                    0x00000300U
-#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
-#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
-
-#define GPIO_PUPDR_PUPDR5                    0x00000C00U
-#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
-#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
-
-#define GPIO_PUPDR_PUPDR6                    0x00003000U
-#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
-#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
-
-#define GPIO_PUPDR_PUPDR7                    0x0000C000U
-#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
-#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
-
-#define GPIO_PUPDR_PUPDR8                    0x00030000U
-#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
-#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
-
-#define GPIO_PUPDR_PUPDR9                    0x000C0000U
-#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
-#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
-
-#define GPIO_PUPDR_PUPDR10                   0x00300000U
-#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
-#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
-
-#define GPIO_PUPDR_PUPDR11                   0x00C00000U
-#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
-#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
-
-#define GPIO_PUPDR_PUPDR12                   0x03000000U
-#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
-#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
-
-#define GPIO_PUPDR_PUPDR13                   0x0C000000U
-#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
-#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
-
-#define GPIO_PUPDR_PUPDR14                   0x30000000U
-#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
-#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
-
-#define GPIO_PUPDR_PUPDR15                   0xC0000000U
-#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
-#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       0x00000001U
-#define GPIO_IDR_IDR_1                       0x00000002U
-#define GPIO_IDR_IDR_2                       0x00000004U
-#define GPIO_IDR_IDR_3                       0x00000008U
-#define GPIO_IDR_IDR_4                       0x00000010U
-#define GPIO_IDR_IDR_5                       0x00000020U
-#define GPIO_IDR_IDR_6                       0x00000040U
-#define GPIO_IDR_IDR_7                       0x00000080U
-#define GPIO_IDR_IDR_8                       0x00000100U
-#define GPIO_IDR_IDR_9                       0x00000200U
-#define GPIO_IDR_IDR_10                      0x00000400U
-#define GPIO_IDR_IDR_11                      0x00000800U
-#define GPIO_IDR_IDR_12                      0x00001000U
-#define GPIO_IDR_IDR_13                      0x00002000U
-#define GPIO_IDR_IDR_14                      0x00004000U
-#define GPIO_IDR_IDR_15                      0x00008000U
-/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
-#define GPIO_OTYPER_IDR_0                    GPIO_IDR_IDR_0
-#define GPIO_OTYPER_IDR_1                    GPIO_IDR_IDR_1
-#define GPIO_OTYPER_IDR_2                    GPIO_IDR_IDR_2
-#define GPIO_OTYPER_IDR_3                    GPIO_IDR_IDR_3
-#define GPIO_OTYPER_IDR_4                    GPIO_IDR_IDR_4
-#define GPIO_OTYPER_IDR_5                    GPIO_IDR_IDR_5
-#define GPIO_OTYPER_IDR_6                    GPIO_IDR_IDR_6
-#define GPIO_OTYPER_IDR_7                    GPIO_IDR_IDR_7
-#define GPIO_OTYPER_IDR_8                    GPIO_IDR_IDR_8
-#define GPIO_OTYPER_IDR_9                    GPIO_IDR_IDR_9
-#define GPIO_OTYPER_IDR_10                   GPIO_IDR_IDR_10
-#define GPIO_OTYPER_IDR_11                   GPIO_IDR_IDR_11
-#define GPIO_OTYPER_IDR_12                   GPIO_IDR_IDR_12
-#define GPIO_OTYPER_IDR_13                   GPIO_IDR_IDR_13
-#define GPIO_OTYPER_IDR_14                   GPIO_IDR_IDR_14
-#define GPIO_OTYPER_IDR_15                   GPIO_IDR_IDR_15
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       0x00000001U
-#define GPIO_ODR_ODR_1                       0x00000002U
-#define GPIO_ODR_ODR_2                       0x00000004U
-#define GPIO_ODR_ODR_3                       0x00000008U
-#define GPIO_ODR_ODR_4                       0x00000010U
-#define GPIO_ODR_ODR_5                       0x00000020U
-#define GPIO_ODR_ODR_6                       0x00000040U
-#define GPIO_ODR_ODR_7                       0x00000080U
-#define GPIO_ODR_ODR_8                       0x00000100U
-#define GPIO_ODR_ODR_9                       0x00000200U
-#define GPIO_ODR_ODR_10                      0x00000400U
-#define GPIO_ODR_ODR_11                      0x00000800U
-#define GPIO_ODR_ODR_12                      0x00001000U
-#define GPIO_ODR_ODR_13                      0x00002000U
-#define GPIO_ODR_ODR_14                      0x00004000U
-#define GPIO_ODR_ODR_15                      0x00008000U
-/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
-#define GPIO_OTYPER_ODR_0                    GPIO_ODR_ODR_0
-#define GPIO_OTYPER_ODR_1                    GPIO_ODR_ODR_1
-#define GPIO_OTYPER_ODR_2                    GPIO_ODR_ODR_2
-#define GPIO_OTYPER_ODR_3                    GPIO_ODR_ODR_3
-#define GPIO_OTYPER_ODR_4                    GPIO_ODR_ODR_4
-#define GPIO_OTYPER_ODR_5                    GPIO_ODR_ODR_5
-#define GPIO_OTYPER_ODR_6                    GPIO_ODR_ODR_6
-#define GPIO_OTYPER_ODR_7                    GPIO_ODR_ODR_7
-#define GPIO_OTYPER_ODR_8                    GPIO_ODR_ODR_8
-#define GPIO_OTYPER_ODR_9                    GPIO_ODR_ODR_9
-#define GPIO_OTYPER_ODR_10                   GPIO_ODR_ODR_10
-#define GPIO_OTYPER_ODR_11                   GPIO_ODR_ODR_11
-#define GPIO_OTYPER_ODR_12                   GPIO_ODR_ODR_12
-#define GPIO_OTYPER_ODR_13                   GPIO_ODR_ODR_13
-#define GPIO_OTYPER_ODR_14                   GPIO_ODR_ODR_14
-#define GPIO_OTYPER_ODR_15                   GPIO_ODR_ODR_15
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       0x00000001U
-#define GPIO_BSRR_BS_1                       0x00000002U
-#define GPIO_BSRR_BS_2                       0x00000004U
-#define GPIO_BSRR_BS_3                       0x00000008U
-#define GPIO_BSRR_BS_4                       0x00000010U
-#define GPIO_BSRR_BS_5                       0x00000020U
-#define GPIO_BSRR_BS_6                       0x00000040U
-#define GPIO_BSRR_BS_7                       0x00000080U
-#define GPIO_BSRR_BS_8                       0x00000100U
-#define GPIO_BSRR_BS_9                       0x00000200U
-#define GPIO_BSRR_BS_10                      0x00000400U
-#define GPIO_BSRR_BS_11                      0x00000800U
-#define GPIO_BSRR_BS_12                      0x00001000U
-#define GPIO_BSRR_BS_13                      0x00002000U
-#define GPIO_BSRR_BS_14                      0x00004000U
-#define GPIO_BSRR_BS_15                      0x00008000U
-#define GPIO_BSRR_BR_0                       0x00010000U
-#define GPIO_BSRR_BR_1                       0x00020000U
-#define GPIO_BSRR_BR_2                       0x00040000U
-#define GPIO_BSRR_BR_3                       0x00080000U
-#define GPIO_BSRR_BR_4                       0x00100000U
-#define GPIO_BSRR_BR_5                       0x00200000U
-#define GPIO_BSRR_BR_6                       0x00400000U
-#define GPIO_BSRR_BR_7                       0x00800000U
-#define GPIO_BSRR_BR_8                       0x01000000U
-#define GPIO_BSRR_BR_9                       0x02000000U
-#define GPIO_BSRR_BR_10                      0x04000000U
-#define GPIO_BSRR_BR_11                      0x08000000U
-#define GPIO_BSRR_BR_12                      0x10000000U
-#define GPIO_BSRR_BR_13                      0x20000000U
-#define GPIO_BSRR_BR_14                      0x40000000U
-#define GPIO_BSRR_BR_15                      0x80000000U
-
-/****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0                       0x00000001U
-#define GPIO_LCKR_LCK1                       0x00000002U
-#define GPIO_LCKR_LCK2                       0x00000004U
-#define GPIO_LCKR_LCK3                       0x00000008U
-#define GPIO_LCKR_LCK4                       0x00000010U
-#define GPIO_LCKR_LCK5                       0x00000020U
-#define GPIO_LCKR_LCK6                       0x00000040U
-#define GPIO_LCKR_LCK7                       0x00000080U
-#define GPIO_LCKR_LCK8                       0x00000100U
-#define GPIO_LCKR_LCK9                       0x00000200U
-#define GPIO_LCKR_LCK10                      0x00000400U
-#define GPIO_LCKR_LCK11                      0x00000800U
-#define GPIO_LCKR_LCK12                      0x00001000U
-#define GPIO_LCKR_LCK13                      0x00002000U
-#define GPIO_LCKR_LCK14                      0x00004000U
-#define GPIO_LCKR_LCK15                      0x00008000U
-#define GPIO_LCKR_LCKK                       0x00010000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Inter-integrated Circuit Interface                    */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          0x00000001U     /*!<Peripheral Enable                             */
-#define  I2C_CR1_SMBUS                       0x00000002U     /*!<SMBus Mode                                    */
-#define  I2C_CR1_SMBTYPE                     0x00000008U     /*!<SMBus Type                                    */
-#define  I2C_CR1_ENARP                       0x00000010U     /*!<ARP Enable                                    */
-#define  I2C_CR1_ENPEC                       0x00000020U     /*!<PEC Enable                                    */
-#define  I2C_CR1_ENGC                        0x00000040U     /*!<General Call Enable                           */
-#define  I2C_CR1_NOSTRETCH                   0x00000080U     /*!<Clock Stretching Disable (Slave mode)  */
-#define  I2C_CR1_START                       0x00000100U     /*!<Start Generation                              */
-#define  I2C_CR1_STOP                        0x00000200U     /*!<Stop Generation                               */
-#define  I2C_CR1_ACK                         0x00000400U     /*!<Acknowledge Enable                            */
-#define  I2C_CR1_POS                         0x00000800U     /*!<Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         0x00001000U     /*!<Packet Error Checking                         */
-#define  I2C_CR1_ALERT                       0x00002000U     /*!<SMBus Alert                                   */
-#define  I2C_CR1_SWRST                       0x00008000U     /*!<Software Reset                                */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        0x0000003FU     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
-#define  I2C_CR2_FREQ_0                      0x00000001U     /*!<Bit 0 */
-#define  I2C_CR2_FREQ_1                      0x00000002U     /*!<Bit 1 */
-#define  I2C_CR2_FREQ_2                      0x00000004U     /*!<Bit 2 */
-#define  I2C_CR2_FREQ_3                      0x00000008U     /*!<Bit 3 */
-#define  I2C_CR2_FREQ_4                      0x00000010U     /*!<Bit 4 */
-#define  I2C_CR2_FREQ_5                      0x00000020U     /*!<Bit 5 */
-
-#define  I2C_CR2_ITERREN                     0x00000100U     /*!<Error Interrupt Enable  */
-#define  I2C_CR2_ITEVTEN                     0x00000200U     /*!<Event Interrupt Enable  */
-#define  I2C_CR2_ITBUFEN                     0x00000400U     /*!<Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       0x00000800U     /*!<DMA Requests Enable     */
-#define  I2C_CR2_LAST                        0x00001000U     /*!<DMA Last Transfer       */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     0x000000FEU     /*!<Interface Address */
-#define  I2C_OAR1_ADD8_9                     0x00000300U     /*!<Interface Address */
-
-#define  I2C_OAR1_ADD0                       0x00000001U     /*!<Bit 0 */
-#define  I2C_OAR1_ADD1                       0x00000002U     /*!<Bit 1 */
-#define  I2C_OAR1_ADD2                       0x00000004U     /*!<Bit 2 */
-#define  I2C_OAR1_ADD3                       0x00000008U     /*!<Bit 3 */
-#define  I2C_OAR1_ADD4                       0x00000010U     /*!<Bit 4 */
-#define  I2C_OAR1_ADD5                       0x00000020U     /*!<Bit 5 */
-#define  I2C_OAR1_ADD6                       0x00000040U     /*!<Bit 6 */
-#define  I2C_OAR1_ADD7                       0x00000080U     /*!<Bit 7 */
-#define  I2C_OAR1_ADD8                       0x00000100U     /*!<Bit 8 */
-#define  I2C_OAR1_ADD9                       0x00000200U     /*!<Bit 9 */
-
-#define  I2C_OAR1_ADDMODE                    0x00008000U     /*!<Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     0x00000001U        /*!<Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       0x000000FEU        /*!<Interface address           */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           0x000000FFU        /*!<8-bit Data Register         */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          0x00000001U     /*!<Start Bit (Master mode)                  */
-#define  I2C_SR1_ADDR                        0x00000002U     /*!<Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         0x00000004U     /*!<Byte Transfer Finished                          */
-#define  I2C_SR1_ADD10                       0x00000008U     /*!<10-bit header sent (Master mode)         */
-#define  I2C_SR1_STOPF                       0x00000010U     /*!<Stop detection (Slave mode)              */
-#define  I2C_SR1_RXNE                        0x00000040U     /*!<Data Register not Empty (receivers)      */
-#define  I2C_SR1_TXE                         0x00000080U     /*!<Data Register Empty (transmitters)       */
-#define  I2C_SR1_BERR                        0x00000100U     /*!<Bus Error                                       */
-#define  I2C_SR1_ARLO                        0x00000200U     /*!<Arbitration Lost (master mode)           */
-#define  I2C_SR1_AF                          0x00000400U     /*!<Acknowledge Failure                             */
-#define  I2C_SR1_OVR                         0x00000800U     /*!<Overrun/Underrun                                */
-#define  I2C_SR1_PECERR                      0x00001000U     /*!<PEC Error in reception                          */
-#define  I2C_SR1_TIMEOUT                     0x00004000U     /*!<Timeout or Tlow Error                           */
-#define  I2C_SR1_SMBALERT                    0x00008000U     /*!<SMBus Alert                                     */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         0x00000001U     /*!<Master/Slave                              */
-#define  I2C_SR2_BUSY                        0x00000002U     /*!<Bus Busy                                  */
-#define  I2C_SR2_TRA                         0x00000004U     /*!<Transmitter/Receiver                      */
-#define  I2C_SR2_GENCALL                     0x00000010U     /*!<General Call Address (Slave mode)  */
-#define  I2C_SR2_SMBDEFAULT                  0x00000020U     /*!<SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     0x00000040U     /*!<SMBus Host Header (Slave mode)     */
-#define  I2C_SR2_DUALF                       0x00000080U     /*!<Dual Flag (Slave mode)             */
-#define  I2C_SR2_PEC                         0x0000FF00U     /*!<Packet Error Checking Register            */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         0x00000FFFU     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        0x00004000U     /*!<Fast Mode Duty Cycle                                       */
-#define  I2C_CCR_FS                          0x00008000U     /*!<I2C Master Mode Selection                                  */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     0x0000003FU     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************  Bit definition for I2C_FLTR register  *******************/
-#define  I2C_FLTR_DNF                        0x0000000FU     /*!<Digital Noise Filter */
-#define  I2C_FLTR_ANOFF                      0x00000010U     /*!<Analog Noise Filter OFF */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Independent WATCHDOG                             */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         0x01U               /*!<Watchdog prescaler value update      */
-#define  IWDG_SR_RVU                         0x02U               /*!<Watchdog counter reload value update */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                      LCD-TFT Display Controller (LTDC)                     */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for LTDC_SSCR register  *****************/
-
-#define LTDC_SSCR_VSH                       0x000007FFU              /*!< Vertical Synchronization Height */
-#define LTDC_SSCR_HSW                       0x0FFF0000U              /*!< Horizontal Synchronization Width */
-
-/********************  Bit definition for LTDC_BPCR register  *****************/
-
-#define LTDC_BPCR_AVBP                      0x000007FFU              /*!< Accumulated Vertical Back Porch */
-#define LTDC_BPCR_AHBP                      0x0FFF0000U              /*!< Accumulated Horizontal Back Porch */
-
-/********************  Bit definition for LTDC_AWCR register  *****************/
-
-#define LTDC_AWCR_AAH                       0x000007FFU              /*!< Accumulated Active heigh */
-#define LTDC_AWCR_AAW                       0x0FFF0000U              /*!< Accumulated Active Width */
-
-/********************  Bit definition for LTDC_TWCR register  *****************/
-
-#define LTDC_TWCR_TOTALH                    0x000007FFU              /*!< Total Heigh */
-#define LTDC_TWCR_TOTALW                    0x0FFF0000U              /*!< Total Width */
-
-/********************  Bit definition for LTDC_GCR register  ******************/
-
-#define LTDC_GCR_LTDCEN                     0x00000001U              /*!< LCD-TFT controller enable bit */
-#define LTDC_GCR_DBW                        0x00000070U              /*!< Dither Blue Width */
-#define LTDC_GCR_DGW                        0x00000700U              /*!< Dither Green Width */
-#define LTDC_GCR_DRW                        0x00007000U              /*!< Dither Red Width */
-#define LTDC_GCR_DEN                        0x00010000U              /*!< Dither Enable */
-#define LTDC_GCR_PCPOL                      0x10000000U              /*!< Pixel Clock Polarity */
-#define LTDC_GCR_DEPOL                      0x20000000U              /*!< Data Enable Polarity */
-#define LTDC_GCR_VSPOL                      0x40000000U              /*!< Vertical Synchronization Polarity */
-#define LTDC_GCR_HSPOL                      0x80000000U              /*!< Horizontal Synchronization Polarity */
-
-/* Legacy defines */
-#define LTDC_GCR_DTEN                       LTDC_GCR_DEN
-
-/********************  Bit definition for LTDC_SRCR register  *****************/
-
-#define LTDC_SRCR_IMR                      0x00000001U               /*!< Immediate Reload */
-#define LTDC_SRCR_VBR                      0x00000002U               /*!< Vertical Blanking Reload */
-
-/********************  Bit definition for LTDC_BCCR register  *****************/
-
-#define LTDC_BCCR_BCBLUE                    0x000000FFU              /*!< Background Blue value */
-#define LTDC_BCCR_BCGREEN                   0x0000FF00U              /*!< Background Green value */
-#define LTDC_BCCR_BCRED                     0x00FF0000U              /*!< Background Red value */
-
-/********************  Bit definition for LTDC_IER register  ******************/
-
-#define LTDC_IER_LIE                        0x00000001U              /*!< Line Interrupt Enable */
-#define LTDC_IER_FUIE                       0x00000002U              /*!< FIFO Underrun Interrupt Enable */
-#define LTDC_IER_TERRIE                     0x00000004U              /*!< Transfer Error Interrupt Enable */
-#define LTDC_IER_RRIE                       0x00000008U              /*!< Register Reload interrupt enable */
-
-/********************  Bit definition for LTDC_ISR register  ******************/
-
-#define LTDC_ISR_LIF                        0x00000001U              /*!< Line Interrupt Flag */
-#define LTDC_ISR_FUIF                       0x00000002U              /*!< FIFO Underrun Interrupt Flag */
-#define LTDC_ISR_TERRIF                     0x00000004U              /*!< Transfer Error Interrupt Flag */
-#define LTDC_ISR_RRIF                       0x00000008U              /*!< Register Reload interrupt Flag */
-
-/********************  Bit definition for LTDC_ICR register  ******************/
-
-#define LTDC_ICR_CLIF                       0x00000001U              /*!< Clears the Line Interrupt Flag */
-#define LTDC_ICR_CFUIF                      0x00000002U              /*!< Clears the FIFO Underrun Interrupt Flag */
-#define LTDC_ICR_CTERRIF                    0x00000004U              /*!< Clears the Transfer Error Interrupt Flag */
-#define LTDC_ICR_CRRIF                      0x00000008U              /*!< Clears Register Reload interrupt Flag */
-
-/********************  Bit definition for LTDC_LIPCR register  ****************/
-
-#define LTDC_LIPCR_LIPOS                    0x000007FFU              /*!< Line Interrupt Position */
-
-/********************  Bit definition for LTDC_CPSR register  *****************/
-
-#define LTDC_CPSR_CYPOS                     0x0000FFFFU              /*!< Current Y Position */
-#define LTDC_CPSR_CXPOS                     0xFFFF0000U              /*!< Current X Position */
-
-/********************  Bit definition for LTDC_CDSR register  *****************/
-
-#define LTDC_CDSR_VDES                      0x00000001U              /*!< Vertical Data Enable Status */
-#define LTDC_CDSR_HDES                      0x00000002U              /*!< Horizontal Data Enable Status */
-#define LTDC_CDSR_VSYNCS                    0x00000004U              /*!< Vertical Synchronization Status */
-#define LTDC_CDSR_HSYNCS                    0x00000008U              /*!< Horizontal Synchronization Status */
-
-/********************  Bit definition for LTDC_LxCR register  *****************/
-
-#define LTDC_LxCR_LEN                       0x00000001U              /*!< Layer Enable */
-#define LTDC_LxCR_COLKEN                    0x00000002U              /*!< Color Keying Enable */
-#define LTDC_LxCR_CLUTEN                    0x00000010U              /*!< Color Lockup Table Enable */
-
-/********************  Bit definition for LTDC_LxWHPCR register  **************/
-
-#define LTDC_LxWHPCR_WHSTPOS                0x00000FFFU              /*!< Window Horizontal Start Position */
-#define LTDC_LxWHPCR_WHSPPOS                0xFFFF0000U              /*!< Window Horizontal Stop Position */
-
-/********************  Bit definition for LTDC_LxWVPCR register  **************/
-
-#define LTDC_LxWVPCR_WVSTPOS                0x00000FFFU              /*!< Window Vertical Start Position */
-#define LTDC_LxWVPCR_WVSPPOS                0xFFFF0000U              /*!< Window Vertical Stop Position */
-
-/********************  Bit definition for LTDC_LxCKCR register  ***************/
-
-#define LTDC_LxCKCR_CKBLUE                  0x000000FFU              /*!< Color Key Blue value */
-#define LTDC_LxCKCR_CKGREEN                 0x0000FF00U              /*!< Color Key Green value */
-#define LTDC_LxCKCR_CKRED                   0x00FF0000U              /*!< Color Key Red value */
-
-/********************  Bit definition for LTDC_LxPFCR register  ***************/
-
-#define LTDC_LxPFCR_PF                      0x00000007U              /*!< Pixel Format */
-
-/********************  Bit definition for LTDC_LxCACR register  ***************/
-
-#define LTDC_LxCACR_CONSTA                  0x000000FFU              /*!< Constant Alpha */
-
-/********************  Bit definition for LTDC_LxDCCR register  ***************/
-
-#define LTDC_LxDCCR_DCBLUE                  0x000000FFU              /*!< Default Color Blue */
-#define LTDC_LxDCCR_DCGREEN                 0x0000FF00U              /*!< Default Color Green */
-#define LTDC_LxDCCR_DCRED                   0x00FF0000U              /*!< Default Color Red */
-#define LTDC_LxDCCR_DCALPHA                 0xFF000000U              /*!< Default Color Alpha */
-                                
-/********************  Bit definition for LTDC_LxBFCR register  ***************/
-
-#define LTDC_LxBFCR_BF2                     0x00000007U              /*!< Blending Factor 2 */
-#define LTDC_LxBFCR_BF1                     0x00000700U              /*!< Blending Factor 1 */
-
-/********************  Bit definition for LTDC_LxCFBAR register  **************/
-
-#define LTDC_LxCFBAR_CFBADD                 0xFFFFFFFFU              /*!< Color Frame Buffer Start Address */
-
-/********************  Bit definition for LTDC_LxCFBLR register  **************/
-
-#define LTDC_LxCFBLR_CFBLL                  0x00001FFFU              /*!< Color Frame Buffer Line Length */
-#define LTDC_LxCFBLR_CFBP                   0x1FFF0000U              /*!< Color Frame Buffer Pitch in bytes */
-
-/********************  Bit definition for LTDC_LxCFBLNR register  *************/
-
-#define LTDC_LxCFBLNR_CFBLNBR               0x000007FFU              /*!< Frame Buffer Line Number */
-
-/********************  Bit definition for LTDC_LxCLUTWR register  *************/
-
-#define LTDC_LxCLUTWR_BLUE                  0x000000FFU              /*!< Blue value */
-#define LTDC_LxCLUTWR_GREEN                 0x0000FF00U              /*!< Green value */
-#define LTDC_LxCLUTWR_RED                   0x00FF0000U              /*!< Red value */
-#define LTDC_LxCLUTWR_CLUTADD               0xFF000000U              /*!< CLUT address */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                             Power Control                                  */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
-#define  PWR_CR_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
-#define  PWR_CR_CWUF                         0x00000004U     /*!< Clear Wakeup Flag                   */
-#define  PWR_CR_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
-#define  PWR_CR_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
-
-#define  PWR_CR_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        0x00000020U     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        0x00000040U     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        0x00000080U     /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
-#define  PWR_CR_DBP                          0x00000100U     /*!< Disable Backup Domain write protection                     */
-#define  PWR_CR_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                              */
-#define  PWR_CR_LPLVDS                       0x00000400U     /*!< Low-Power Regulator Low Voltage Scaling in Stop mode       */
-#define  PWR_CR_MRLVDS                       0x00000800U     /*!< Main regulator Low Voltage Scaling in Stop mode            */
-#define  PWR_CR_ADCDC1                       0x00002000U     /*!< Refer to AN4073 on how to use this bit */ 
-#define  PWR_CR_VOS                          0x0000C000U     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
-#define  PWR_CR_VOS_0                        0x00004000U     /*!< Bit 0 */
-#define  PWR_CR_VOS_1                        0x00008000U     /*!< Bit 1 */
-#define  PWR_CR_ODEN                         0x00010000U     /*!< Over Drive enable                   */
-#define  PWR_CR_ODSWEN                       0x00020000U     /*!< Over Drive switch enabled           */
-#define  PWR_CR_UDEN                         0x000C0000U     /*!< Under Drive enable in stop mode     */
-#define  PWR_CR_UDEN_0                       0x00040000U     /*!< Bit 0                               */
-#define  PWR_CR_UDEN_1                       0x00080000U     /*!< Bit 1                               */
-
-/* Legacy define */
-#define  PWR_CR_PMODE                        PWR_CR_VOS
-#define  PWR_CR_LPUDS                        PWR_CR_LPLVDS     /*!< Low-Power Regulator in deepsleep under-drive mode        */
-#define  PWR_CR_MRUDS                        PWR_CR_MRLVDS     /*!< Main regulator in deepsleep under-drive mode             */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         0x00000001U     /*!< Wakeup Flag                                      */
-#define  PWR_CSR_SBF                         0x00000002U     /*!< Standby Flag                                     */
-#define  PWR_CSR_PVDO                        0x00000004U     /*!< PVD Output                                       */
-#define  PWR_CSR_BRR                         0x00000008U     /*!< Backup regulator ready                           */
-#define  PWR_CSR_WUPP                        0x00000080U     /*!< WKUP pin Polarity                                */
-#define  PWR_CSR_EWUP                        0x00000100U     /*!< Enable WKUP pin                                  */
-#define  PWR_CSR_BRE                         0x00000200U     /*!< Backup regulator enable                          */
-#define  PWR_CSR_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
-#define  PWR_CSR_ODRDY                       0x00010000U     /*!< Over Drive generator ready                       */
-#define  PWR_CSR_ODSWRDY                     0x00020000U     /*!< Over Drive Switch ready                          */
-#define  PWR_CSR_UDSWRDY                     0x000C0000U     /*!< Under Drive ready                                */
-
-/* Legacy define */
-#define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    QUADSPI                                 */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for QUADSPI_CR register  *******************/
-#define  QUADSPI_CR_EN                           0x00000001U            /*!< Enable                             */
-#define  QUADSPI_CR_ABORT                        0x00000002U            /*!< Abort request                      */
-#define  QUADSPI_CR_DMAEN                        0x00000004U            /*!< DMA Enable                         */
-#define  QUADSPI_CR_TCEN                         0x00000008U            /*!< Timeout Counter Enable             */
-#define  QUADSPI_CR_SSHIFT                       0x00000010U            /*!< SSHIFT Sample Shift                */
-#define  QUADSPI_CR_DFM                          0x00000040U            /*!< Dual Flash Mode                    */
-#define  QUADSPI_CR_FSEL                         0x00000080U            /*!< Flash Select                       */
-#define  QUADSPI_CR_FTHRES                       0x00001F00U            /*!< FTHRES[3:0] FIFO Level             */
-#define  QUADSPI_CR_FTHRES_0                     0x00000100U            /*!< Bit 0 */
-#define  QUADSPI_CR_FTHRES_1                     0x00000200U            /*!< Bit 1 */
-#define  QUADSPI_CR_FTHRES_2                     0x00000400U            /*!< Bit 2 */
-#define  QUADSPI_CR_FTHRES_3                     0x00000800U            /*!< Bit 3 */
-#define  QUADSPI_CR_FTHRES_4                     0x00001000U            /*!< Bit 4 */
-#define  QUADSPI_CR_TEIE                         0x00010000U            /*!< Transfer Error Interrupt Enable    */
-#define  QUADSPI_CR_TCIE                         0x00020000U            /*!< Transfer Complete Interrupt Enable */
-#define  QUADSPI_CR_FTIE                         0x00040000U            /*!< FIFO Threshold Interrupt Enable    */
-#define  QUADSPI_CR_SMIE                         0x00080000U            /*!< Status Match Interrupt Enable      */
-#define  QUADSPI_CR_TOIE                         0x00100000U            /*!< TimeOut Interrupt Enable           */
-#define  QUADSPI_CR_APMS                         0x00400000U            /*!< Bit 1 */
-#define  QUADSPI_CR_PMM                          0x00800000U            /*!< Polling Match Mode                 */
-#define  QUADSPI_CR_PRESCALER                    0xFF000000U            /*!< PRESCALER[7:0] Clock prescaler     */
-#define  QUADSPI_CR_PRESCALER_0                  0x01000000U            /*!< Bit 0 */
-#define  QUADSPI_CR_PRESCALER_1                  0x02000000U            /*!< Bit 1 */
-#define  QUADSPI_CR_PRESCALER_2                  0x04000000U            /*!< Bit 2 */
-#define  QUADSPI_CR_PRESCALER_3                  0x08000000U            /*!< Bit 3 */
-#define  QUADSPI_CR_PRESCALER_4                  0x10000000U            /*!< Bit 4 */
-#define  QUADSPI_CR_PRESCALER_5                  0x20000000U            /*!< Bit 5 */
-#define  QUADSPI_CR_PRESCALER_6                  0x40000000U            /*!< Bit 6 */
-#define  QUADSPI_CR_PRESCALER_7                  0x80000000U            /*!< Bit 7 */
-
-/*****************  Bit definition for QUADSPI_DCR register  ******************/
-#define  QUADSPI_DCR_CKMODE                      0x00000001U            /*!< Mode 0 / Mode 3                 */
-#define  QUADSPI_DCR_CSHT                        0x00000700U            /*!< CSHT[2:0]: ChipSelect High Time */
-#define  QUADSPI_DCR_CSHT_0                      0x00000100U            /*!< Bit 0 */
-#define  QUADSPI_DCR_CSHT_1                      0x00000200U            /*!< Bit 1 */
-#define  QUADSPI_DCR_CSHT_2                      0x00000400U            /*!< Bit 2 */
-#define  QUADSPI_DCR_FSIZE                       0x001F0000U            /*!< FSIZE[4:0]: Flash Size          */
-#define  QUADSPI_DCR_FSIZE_0                     0x00010000U            /*!< Bit 0 */
-#define  QUADSPI_DCR_FSIZE_1                     0x00020000U            /*!< Bit 1 */
-#define  QUADSPI_DCR_FSIZE_2                     0x00040000U            /*!< Bit 2 */
-#define  QUADSPI_DCR_FSIZE_3                     0x00080000U            /*!< Bit 3 */
-#define  QUADSPI_DCR_FSIZE_4                     0x00100000U            /*!< Bit 4 */
-
-/******************  Bit definition for QUADSPI_SR register  *******************/
-#define  QUADSPI_SR_TEF                          0x00000001U             /*!< Transfer Error Flag    */
-#define  QUADSPI_SR_TCF                          0x00000002U             /*!< Transfer Complete Flag */
-#define  QUADSPI_SR_FTF                          0x00000004U             /*!< FIFO Threshlod Flag    */
-#define  QUADSPI_SR_SMF                          0x00000008U             /*!< Status Match Flag      */
-#define  QUADSPI_SR_TOF                          0x00000010U             /*!< Timeout Flag           */
-#define  QUADSPI_SR_BUSY                         0x00000020U             /*!< Busy                   */
-#define  QUADSPI_SR_FLEVEL                       0x00003F00U             /*!< FIFO Threshlod Flag    */
-#define  QUADSPI_SR_FLEVEL_0                     0x00000100U             /*!< Bit 0 */
-#define  QUADSPI_SR_FLEVEL_1                     0x00000200U             /*!< Bit 1 */
-#define  QUADSPI_SR_FLEVEL_2                     0x00000400U             /*!< Bit 2 */
-#define  QUADSPI_SR_FLEVEL_3                     0x00000800U             /*!< Bit 3 */
-#define  QUADSPI_SR_FLEVEL_4                     0x00001000U             /*!< Bit 4 */
-#define  QUADSPI_SR_FLEVEL_5                     0x00002000U             /*!< Bit 5 */
-
-/******************  Bit definition for QUADSPI_FCR register  ******************/
-#define  QUADSPI_FCR_CTEF                        0x00000001U             /*!< Clear Transfer Error Flag    */
-#define  QUADSPI_FCR_CTCF                        0x00000002U             /*!< Clear Transfer Complete Flag */
-#define  QUADSPI_FCR_CSMF                        0x00000008U             /*!< Clear Status Match Flag      */
-#define  QUADSPI_FCR_CTOF                        0x00000010U             /*!< Clear Timeout Flag           */
-
-/******************  Bit definition for QUADSPI_DLR register  ******************/
-#define  QUADSPI_DLR_DL                        0xFFFFFFFFU               /*!< DL[31:0]: Data Length */
-
-/******************  Bit definition for QUADSPI_CCR register  ******************/
-#define  QUADSPI_CCR_INSTRUCTION                  0x000000FFU            /*!< INSTRUCTION[7:0]: Instruction */
-#define  QUADSPI_CCR_INSTRUCTION_0                0x00000001U            /*!< Bit 0 */
-#define  QUADSPI_CCR_INSTRUCTION_1                0x00000002U            /*!< Bit 1 */
-#define  QUADSPI_CCR_INSTRUCTION_2                0x00000004U            /*!< Bit 2 */
-#define  QUADSPI_CCR_INSTRUCTION_3                0x00000008U            /*!< Bit 3 */
-#define  QUADSPI_CCR_INSTRUCTION_4                0x00000010U            /*!< Bit 4 */
-#define  QUADSPI_CCR_INSTRUCTION_5                0x00000020U            /*!< Bit 5 */
-#define  QUADSPI_CCR_INSTRUCTION_6                0x00000040U            /*!< Bit 6 */
-#define  QUADSPI_CCR_INSTRUCTION_7                0x00000080U            /*!< Bit 7 */
-#define  QUADSPI_CCR_IMODE                        0x00000300U            /*!< IMODE[1:0]: Instruction Mode     */
-#define  QUADSPI_CCR_IMODE_0                      0x00000100U            /*!< Bit 0 */
-#define  QUADSPI_CCR_IMODE_1                      0x00000200U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ADMODE                       0x00000C00U            /*!< ADMODE[1:0]: Address Mode         */
-#define  QUADSPI_CCR_ADMODE_0                     0x00000400U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ADMODE_1                     0x00000800U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ADSIZE                       0x00003000U            /*!< ADSIZE[1:0]: Address Size         */
-#define  QUADSPI_CCR_ADSIZE_0                     0x00001000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ADSIZE_1                     0x00002000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ABMODE                       0x0000C000U            /*!< ABMODE[1:0]: Alternate Bytes Mode */
-#define  QUADSPI_CCR_ABMODE_0                     0x00004000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ABMODE_1                     0x00008000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ABSIZE                       0x00030000U            /*!< ABSIZE[1:0]: Instruction Mode     */
-#define  QUADSPI_CCR_ABSIZE_0                     0x00010000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ABSIZE_1                     0x00020000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_DCYC                         0x007C0000U            /*!< DCYC[4:0]: Dummy Cycles           */
-#define  QUADSPI_CCR_DCYC_0                       0x00040000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_DCYC_1                       0x00080000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_DCYC_2                       0x00100000U            /*!< Bit 2 */
-#define  QUADSPI_CCR_DCYC_3                       0x00200000U            /*!< Bit 3 */
-#define  QUADSPI_CCR_DCYC_4                       0x00400000U            /*!< Bit 4 */
-#define  QUADSPI_CCR_DMODE                        0x03000000U            /*!< DMODE[1:0]: Data Mode                */
-#define  QUADSPI_CCR_DMODE_0                      0x01000000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_DMODE_1                      0x02000000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_FMODE                        0x0C000000U            /*!< FMODE[1:0]: Functional Mode           */
-#define  QUADSPI_CCR_FMODE_0                      0x04000000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_FMODE_1                      0x08000000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_SIOO                         0x10000000U            /*!< SIOO: Send Instruction Only Once Mode */
-#define  QUADSPI_CCR_DHHC                         0x40000000U            /*!< DHHC: Delay Half Hclk Cycle           */
-#define  QUADSPI_CCR_DDRM                         0x80000000U            /*!< DDRM: Double Data Rate Mode           */ 
-/******************  Bit definition for QUADSPI_AR register  *******************/
-#define  QUADSPI_AR_ADDRESS                       0xFFFFFFFFU            /*!< ADDRESS[31:0]: Address                */
-
-/******************  Bit definition for QUADSPI_ABR register  ******************/
-#define  QUADSPI_ABR_ALTERNATE                    0xFFFFFFFFU            /*!< ALTERNATE[31:0]: Alternate Bytes      */
-
-/******************  Bit definition for QUADSPI_DR register  *******************/
-#define  QUADSPI_DR_DATA                          0xFFFFFFFFU            /*!< DATA[31:0]: Data                      */
-
-/******************  Bit definition for QUADSPI_PSMKR register  ****************/
-#define  QUADSPI_PSMKR_MASK                       0xFFFFFFFFU            /*!< MASK[31:0]: Status Mask               */
-
-/******************  Bit definition for QUADSPI_PSMAR register  ****************/
-#define  QUADSPI_PSMAR_MATCH                      0xFFFFFFFFU            /*!< MATCH[31:0]: Status Match             */
-
-/******************  Bit definition for QUADSPI_PIR register  *****************/
-#define  QUADSPI_PIR_INTERVAL                     0x0000FFFFU            /*!< INTERVAL[15:0]: Polling Interval      */
-
-/******************  Bit definition for QUADSPI_LPTR register  *****************/
-#define  QUADSPI_LPTR_TIMEOUT                     0x0000FFFFU            /*!< TIMEOUT[15:0]: Timeout period         */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        0x00000001U
-#define  RCC_CR_HSIRDY                       0x00000002U
-
-#define  RCC_CR_HSITRIM                      0x000000F8U
-#define  RCC_CR_HSITRIM_0                    0x00000008U/*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    0x00000010U/*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    0x00000020U/*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    0x00000040U/*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    0x00000080U/*!<Bit 4 */
-
-#define  RCC_CR_HSICAL                       0x0000FF00U
-#define  RCC_CR_HSICAL_0                     0x00000100U/*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     0x00000200U/*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     0x00000400U/*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     0x00000800U/*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     0x00001000U/*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     0x00002000U/*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     0x00004000U/*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     0x00008000U/*!<Bit 7 */
-
-#define  RCC_CR_HSEON                        0x00010000U
-#define  RCC_CR_HSERDY                       0x00020000U
-#define  RCC_CR_HSEBYP                       0x00040000U
-#define  RCC_CR_CSSON                        0x00080000U
-#define  RCC_CR_PLLON                        0x01000000U
-#define  RCC_CR_PLLRDY                       0x02000000U
-#define  RCC_CR_PLLI2SON                     0x04000000U
-#define  RCC_CR_PLLI2SRDY                    0x08000000U
-#define  RCC_CR_PLLSAION                     0x10000000U
-#define  RCC_CR_PLLSAIRDY                    0x20000000U
-
-/********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    0x0000003FU
-#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
-#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
-#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
-#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
-#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
-#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
-
-#define  RCC_PLLCFGR_PLLN                     0x00007FC0U
-#define  RCC_PLLCFGR_PLLN_0                   0x00000040U
-#define  RCC_PLLCFGR_PLLN_1                   0x00000080U
-#define  RCC_PLLCFGR_PLLN_2                   0x00000100U
-#define  RCC_PLLCFGR_PLLN_3                   0x00000200U
-#define  RCC_PLLCFGR_PLLN_4                   0x00000400U
-#define  RCC_PLLCFGR_PLLN_5                   0x00000800U
-#define  RCC_PLLCFGR_PLLN_6                   0x00001000U
-#define  RCC_PLLCFGR_PLLN_7                   0x00002000U
-#define  RCC_PLLCFGR_PLLN_8                   0x00004000U
-
-#define  RCC_PLLCFGR_PLLP                    0x00030000U
-#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
-#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
-
-#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
-
-#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
-#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
-#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
-#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
-#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
-
-#define  RCC_PLLCFGR_PLLR                    0x70000000U
-#define  RCC_PLLCFGR_PLLR_0                  0x10000000U
-#define  RCC_PLLCFGR_PLLR_1                  0x20000000U
-#define  RCC_PLLCFGR_PLLR_2                  0x40000000U
-
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-/*!< SW configuration */
-#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
-
-#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
-
-#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
-
-#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
-
-/*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     0x001F0000U
-#define  RCC_CFGR_RTCPRE_0                   0x00010000U
-#define  RCC_CFGR_RTCPRE_1                   0x00020000U
-#define  RCC_CFGR_RTCPRE_2                   0x00040000U
-#define  RCC_CFGR_RTCPRE_3                   0x00080000U
-#define  RCC_CFGR_RTCPRE_4                   0x00100000U
-
-/*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       0x00600000U
-#define  RCC_CFGR_MCO1_0                     0x00200000U
-#define  RCC_CFGR_MCO1_1                     0x00400000U
-
-#define  RCC_CFGR_I2SSRC                     0x00800000U
-
-#define  RCC_CFGR_MCO1PRE                    0x07000000U
-#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
-#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
-#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
-
-#define  RCC_CFGR_MCO2PRE                    0x38000000U
-#define  RCC_CFGR_MCO2PRE_0                  0x08000000U
-#define  RCC_CFGR_MCO2PRE_1                  0x10000000U
-#define  RCC_CFGR_MCO2PRE_2                  0x20000000U
-
-#define  RCC_CFGR_MCO2                       0xC0000000U
-#define  RCC_CFGR_MCO2_0                     0x40000000U
-#define  RCC_CFGR_MCO2_1                     0x80000000U
-
-/********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     0x00000001U
-#define  RCC_CIR_LSERDYF                     0x00000002U
-#define  RCC_CIR_HSIRDYF                     0x00000004U
-#define  RCC_CIR_HSERDYF                     0x00000008U
-#define  RCC_CIR_PLLRDYF                     0x00000010U
-#define  RCC_CIR_PLLI2SRDYF                  0x00000020U
-#define  RCC_CIR_PLLSAIRDYF                  0x00000040U
-#define  RCC_CIR_CSSF                        0x00000080U
-#define  RCC_CIR_LSIRDYIE                    0x00000100U
-#define  RCC_CIR_LSERDYIE                    0x00000200U
-#define  RCC_CIR_HSIRDYIE                    0x00000400U
-#define  RCC_CIR_HSERDYIE                    0x00000800U
-#define  RCC_CIR_PLLRDYIE                    0x00001000U
-#define  RCC_CIR_PLLI2SRDYIE                 0x00002000U
-#define  RCC_CIR_PLLSAIRDYIE                 0x00004000U
-#define  RCC_CIR_LSIRDYC                     0x00010000U
-#define  RCC_CIR_LSERDYC                     0x00020000U
-#define  RCC_CIR_HSIRDYC                     0x00040000U
-#define  RCC_CIR_HSERDYC                     0x00080000U
-#define  RCC_CIR_PLLRDYC                     0x00100000U
-#define  RCC_CIR_PLLI2SRDYC                  0x00200000U
-#define  RCC_CIR_PLLSAIRDYC                  0x00400000U
-#define  RCC_CIR_CSSC                        0x00800000U
-
-/********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
-#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
-#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
-#define  RCC_AHB1RSTR_GPIODRST               0x00000008U
-#define  RCC_AHB1RSTR_GPIOERST               0x00000010U
-#define  RCC_AHB1RSTR_GPIOFRST               0x00000020U
-#define  RCC_AHB1RSTR_GPIOGRST               0x00000040U
-#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
-#define  RCC_AHB1RSTR_GPIOIRST               0x00000100U
-#define  RCC_AHB1RSTR_GPIOJRST               0x00000200U
-#define  RCC_AHB1RSTR_GPIOKRST               0x00000400U
-#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
-#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
-#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
-#define  RCC_AHB1RSTR_DMA2DRST               0x00800000U
-#define  RCC_AHB1RSTR_ETHMACRST              0x02000000U
-#define  RCC_AHB1RSTR_OTGHRST                0x20000000U
-
-/********************  Bit definition for RCC_AHB2RSTR register  **************/
-#define  RCC_AHB2RSTR_DCMIRST                0x00000001U
-#define  RCC_AHB2RSTR_RNGRST                 0x00000040U
-#define  RCC_AHB2RSTR_OTGFSRST               0x00000080U
-
-/********************  Bit definition for RCC_AHB3RSTR register  **************/
-#define  RCC_AHB3RSTR_FMCRST                0x00000001U
-#define  RCC_AHB3RSTR_QSPIRST               0x00000002U
-
-/********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM2RST                0x00000001U
-#define  RCC_APB1RSTR_TIM3RST                0x00000002U
-#define  RCC_APB1RSTR_TIM4RST                0x00000004U
-#define  RCC_APB1RSTR_TIM5RST                0x00000008U
-#define  RCC_APB1RSTR_TIM6RST                0x00000010U
-#define  RCC_APB1RSTR_TIM7RST                0x00000020U
-#define  RCC_APB1RSTR_TIM12RST               0x00000040U
-#define  RCC_APB1RSTR_TIM13RST               0x00000080U
-#define  RCC_APB1RSTR_TIM14RST               0x00000100U
-#define  RCC_APB1RSTR_WWDGRST                0x00000800U
-#define  RCC_APB1RSTR_SPI2RST                0x00004000U
-#define  RCC_APB1RSTR_SPI3RST                0x00008000U
-#define  RCC_APB1RSTR_USART2RST              0x00020000U
-#define  RCC_APB1RSTR_USART3RST              0x00040000U
-#define  RCC_APB1RSTR_UART4RST               0x00080000U
-#define  RCC_APB1RSTR_UART5RST               0x00100000U
-#define  RCC_APB1RSTR_I2C1RST                0x00200000U
-#define  RCC_APB1RSTR_I2C2RST                0x00400000U
-#define  RCC_APB1RSTR_I2C3RST                0x00800000U
-#define  RCC_APB1RSTR_CAN1RST                0x02000000U
-#define  RCC_APB1RSTR_CAN2RST                0x04000000U
-#define  RCC_APB1RSTR_PWRRST                 0x10000000U
-#define  RCC_APB1RSTR_DACRST                 0x20000000U
-#define  RCC_APB1RSTR_UART7RST               0x40000000U
-#define  RCC_APB1RSTR_UART8RST               0x80000000U
-
-/********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                0x00000001U
-#define  RCC_APB2RSTR_TIM8RST                0x00000002U
-#define  RCC_APB2RSTR_USART1RST              0x00000010U
-#define  RCC_APB2RSTR_USART6RST              0x00000020U
-#define  RCC_APB2RSTR_ADCRST                 0x00000100U
-#define  RCC_APB2RSTR_SDIORST                0x00000800U
-#define  RCC_APB2RSTR_SPI1RST                0x00001000U
-#define  RCC_APB2RSTR_SPI4RST                0x00002000U
-#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
-#define  RCC_APB2RSTR_TIM9RST                0x00010000U
-#define  RCC_APB2RSTR_TIM10RST               0x00020000U
-#define  RCC_APB2RSTR_TIM11RST               0x00040000U
-#define  RCC_APB2RSTR_SPI5RST                0x00100000U
-#define  RCC_APB2RSTR_SPI6RST                0x00200000U
-#define  RCC_APB2RSTR_SAI1RST                0x00400000U
-#define  RCC_APB2RSTR_LTDCRST                0x04000000U
-#define  RCC_APB2RSTR_DSIRST                 0x08000000U
-
-/* Old SPI1RST bit definition, maintained for legacy purpose */
-#define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
-
-/********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
-#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
-#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
-#define  RCC_AHB1ENR_GPIODEN                 0x00000008U
-#define  RCC_AHB1ENR_GPIOEEN                 0x00000010U
-#define  RCC_AHB1ENR_GPIOFEN                 0x00000020U
-#define  RCC_AHB1ENR_GPIOGEN                 0x00000040U
-#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
-#define  RCC_AHB1ENR_GPIOIEN                 0x00000100U
-#define  RCC_AHB1ENR_GPIOJEN                 0x00000200U
-#define  RCC_AHB1ENR_GPIOKEN                 0x00000400U
-
-#define  RCC_AHB1ENR_CRCEN                   0x00001000U
-#define  RCC_AHB1ENR_BKPSRAMEN               0x00040000U
-#define  RCC_AHB1ENR_CCMDATARAMEN            0x00100000U
-#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
-#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
-#define  RCC_AHB1ENR_DMA2DEN                 0x00800000U
-
-#define  RCC_AHB1ENR_ETHMACEN                0x02000000U
-#define  RCC_AHB1ENR_ETHMACTXEN              0x04000000U
-#define  RCC_AHB1ENR_ETHMACRXEN              0x08000000U
-#define  RCC_AHB1ENR_ETHMACPTPEN             0x10000000U
-#define  RCC_AHB1ENR_OTGHSEN                 0x20000000U
-#define  RCC_AHB1ENR_OTGHSULPIEN             0x40000000U
-
-/********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define  RCC_AHB2ENR_DCMIEN                  0x00000001U
-#define  RCC_AHB2ENR_RNGEN                   0x00000040U
-#define  RCC_AHB2ENR_OTGFSEN                 0x00000080U
-
-/********************  Bit definition for RCC_AHB3ENR register  ***************/
-#define  RCC_AHB3ENR_FMCEN                  0x00000001U
-#define  RCC_AHB3ENR_QSPIEN                 0x00000002U
-
-/********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM2EN                  0x00000001U
-#define  RCC_APB1ENR_TIM3EN                  0x00000002U
-#define  RCC_APB1ENR_TIM4EN                  0x00000004U
-#define  RCC_APB1ENR_TIM5EN                  0x00000008U
-#define  RCC_APB1ENR_TIM6EN                  0x00000010U
-#define  RCC_APB1ENR_TIM7EN                  0x00000020U
-#define  RCC_APB1ENR_TIM12EN                 0x00000040U
-#define  RCC_APB1ENR_TIM13EN                 0x00000080U
-#define  RCC_APB1ENR_TIM14EN                 0x00000100U
-#define  RCC_APB1ENR_WWDGEN                  0x00000800U
-#define  RCC_APB1ENR_SPI2EN                  0x00004000U
-#define  RCC_APB1ENR_SPI3EN                  0x00008000U
-#define  RCC_APB1ENR_USART2EN                0x00020000U
-#define  RCC_APB1ENR_USART3EN                0x00040000U
-#define  RCC_APB1ENR_UART4EN                 0x00080000U
-#define  RCC_APB1ENR_UART5EN                 0x00100000U
-#define  RCC_APB1ENR_I2C1EN                  0x00200000U
-#define  RCC_APB1ENR_I2C2EN                  0x00400000U
-#define  RCC_APB1ENR_I2C3EN                  0x00800000U
-#define  RCC_APB1ENR_CAN1EN                  0x02000000U
-#define  RCC_APB1ENR_CAN2EN                  0x04000000U
-#define  RCC_APB1ENR_PWREN                   0x10000000U
-#define  RCC_APB1ENR_DACEN                   0x20000000U
-#define  RCC_APB1ENR_UART7EN                 0x40000000U
-#define  RCC_APB1ENR_UART8EN                 0x80000000U
-
-/********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  0x00000001U
-#define  RCC_APB2ENR_TIM8EN                  0x00000002U
-#define  RCC_APB2ENR_USART1EN                0x00000010U
-#define  RCC_APB2ENR_USART6EN                0x00000020U
-#define  RCC_APB2ENR_ADC1EN                  0x00000100U
-#define  RCC_APB2ENR_ADC2EN                  0x00000200U
-#define  RCC_APB2ENR_ADC3EN                  0x00000400U
-#define  RCC_APB2ENR_SDIOEN                  0x00000800U
-#define  RCC_APB2ENR_SPI1EN                  0x00001000U
-#define  RCC_APB2ENR_SPI4EN                  0x00002000U
-#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
-#define  RCC_APB2ENR_TIM9EN                  0x00010000U
-#define  RCC_APB2ENR_TIM10EN                 0x00020000U
-#define  RCC_APB2ENR_TIM11EN                 0x00040000U
-#define  RCC_APB2ENR_SPI5EN                  0x00100000U
-#define  RCC_APB2ENR_SPI6EN                  0x00200000U
-#define  RCC_APB2ENR_SAI1EN                  0x00400000U
-#define  RCC_APB2ENR_LTDCEN                  0x04000000U
-#define  RCC_APB2ENR_DSIEN                   0x08000000U
-
-/********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
-#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
-#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
-#define  RCC_AHB1LPENR_GPIODLPEN             0x00000008U
-#define  RCC_AHB1LPENR_GPIOELPEN             0x00000010U
-#define  RCC_AHB1LPENR_GPIOFLPEN             0x00000020U
-#define  RCC_AHB1LPENR_GPIOGLPEN             0x00000040U
-#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
-#define  RCC_AHB1LPENR_GPIOILPEN             0x00000100U
-#define  RCC_AHB1LPENR_GPIOJLPEN             0x00000200U
-#define  RCC_AHB1LPENR_GPIOKLPEN             0x00000400U
-
-#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
-#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
-#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
-#define  RCC_AHB1LPENR_SRAM2LPEN             0x00020000U
-#define  RCC_AHB1LPENR_BKPSRAMLPEN           0x00040000U
-#define  RCC_AHB1LPENR_SRAM3LPEN             0x00080000U
-#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
-#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
-#define  RCC_AHB1LPENR_DMA2DLPEN             0x00800000U
-
-#define  RCC_AHB1LPENR_ETHMACLPEN            0x02000000U
-#define  RCC_AHB1LPENR_ETHMACTXLPEN          0x04000000U
-#define  RCC_AHB1LPENR_ETHMACRXLPEN          0x08000000U
-#define  RCC_AHB1LPENR_ETHMACPTPLPEN         0x10000000U
-#define  RCC_AHB1LPENR_OTGHSLPEN             0x20000000U
-#define  RCC_AHB1LPENR_OTGHSULPILPEN         0x40000000U
-
-/********************  Bit definition for RCC_AHB2LPENR register  *************/
-#define  RCC_AHB2LPENR_DCMILPEN              0x00000001U
-#define  RCC_AHB2LPENR_RNGLPEN               0x00000040U
-#define  RCC_AHB2LPENR_OTGFSLPEN             0x00000080U
-
-/********************  Bit definition for RCC_AHB3LPENR register  *************/
-#define  RCC_AHB3LPENR_FMCLPEN              0x00000001U
-#define  RCC_AHB3LPENR_QSPILPEN             0x00000002U
-
-/********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM2LPEN              0x00000001U
-#define  RCC_APB1LPENR_TIM3LPEN              0x00000002U
-#define  RCC_APB1LPENR_TIM4LPEN              0x00000004U
-#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
-#define  RCC_APB1LPENR_TIM6LPEN              0x00000010U
-#define  RCC_APB1LPENR_TIM7LPEN              0x00000020U
-#define  RCC_APB1LPENR_TIM12LPEN             0x00000040U
-#define  RCC_APB1LPENR_TIM13LPEN             0x00000080U
-#define  RCC_APB1LPENR_TIM14LPEN             0x00000100U
-#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
-#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U
-#define  RCC_APB1LPENR_SPI3LPEN              0x00008000U
-#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
-#define  RCC_APB1LPENR_USART3LPEN            0x00040000U
-#define  RCC_APB1LPENR_UART4LPEN             0x00080000U
-#define  RCC_APB1LPENR_UART5LPEN             0x00100000U
-#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
-#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
-#define  RCC_APB1LPENR_I2C3LPEN              0x00800000U
-#define  RCC_APB1LPENR_CAN1LPEN              0x02000000U
-#define  RCC_APB1LPENR_CAN2LPEN              0x04000000U
-#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
-#define  RCC_APB1LPENR_DACLPEN               0x20000000U
-#define  RCC_APB1LPENR_UART7LPEN             0x40000000U
-#define  RCC_APB1LPENR_UART8LPEN             0x80000000U
-
-/********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
-#define  RCC_APB2LPENR_TIM8LPEN              0x00000002U
-#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
-#define  RCC_APB2LPENR_USART6LPEN            0x00000020U
-#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
-#define  RCC_APB2LPENR_ADC2LPEN              0x00000200U
-#define  RCC_APB2LPENR_ADC3LPEN              0x00000400U
-#define  RCC_APB2LPENR_SDIOLPEN              0x00000800U
-#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
-#define  RCC_APB2LPENR_SPI4LPEN              0x00002000U
-#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
-#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
-#define  RCC_APB2LPENR_TIM10LPEN             0x00020000U
-#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
-#define  RCC_APB2LPENR_SPI5LPEN              0x00100000U
-#define  RCC_APB2LPENR_SPI6LPEN              0x00200000U
-#define  RCC_APB2LPENR_SAI1LPEN              0x00400000U
-#define  RCC_APB2LPENR_LTDCLPEN              0x04000000U
-#define  RCC_APB2LPENR_DSILPEN               0x08000000U
-
-/********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      0x00000001U
-#define  RCC_BDCR_LSERDY                     0x00000002U
-#define  RCC_BDCR_LSEBYP                     0x00000004U
-#define  RCC_BDCR_LSEMOD                     0x00000008U
-
-#define  RCC_BDCR_RTCSEL                    0x00000300U
-#define  RCC_BDCR_RTCSEL_0                  0x00000100U
-#define  RCC_BDCR_RTCSEL_1                  0x00000200U
-
-#define  RCC_BDCR_RTCEN                      0x00008000U
-#define  RCC_BDCR_BDRST                      0x00010000U
-
-/********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       0x00000001U
-#define  RCC_CSR_LSIRDY                      0x00000002U
-#define  RCC_CSR_RMVF                        0x01000000U
-#define  RCC_CSR_BORRSTF                     0x02000000U
-#define  RCC_CSR_PADRSTF                     0x04000000U
-#define  RCC_CSR_PORRSTF                     0x08000000U
-#define  RCC_CSR_SFTRSTF                     0x10000000U
-#define  RCC_CSR_WDGRSTF                     0x20000000U
-#define  RCC_CSR_WWDGRSTF                    0x40000000U
-#define  RCC_CSR_LPWRRSTF                    0x80000000U
-
-/********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    0x00001FFFU
-#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
-#define  RCC_SSCGR_SPREADSEL                 0x40000000U
-#define  RCC_SSCGR_SSCGEN                    0x80000000U
-
-/********************  Bit definition for RCC_PLLI2SCFGR register  ************/
-#define  RCC_PLLI2SCFGR_PLLI2SN              0x00007FC0U
-#define  RCC_PLLI2SCFGR_PLLI2SN_0            0x00000040U
-#define  RCC_PLLI2SCFGR_PLLI2SN_1            0x00000080U
-#define  RCC_PLLI2SCFGR_PLLI2SN_2            0x00000100U
-#define  RCC_PLLI2SCFGR_PLLI2SN_3            0x00000200U
-#define  RCC_PLLI2SCFGR_PLLI2SN_4            0x00000400U
-#define  RCC_PLLI2SCFGR_PLLI2SN_5            0x00000800U
-#define  RCC_PLLI2SCFGR_PLLI2SN_6            0x00001000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_7            0x00002000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_8            0x00004000U
-
-#define  RCC_PLLI2SCFGR_PLLI2SQ              0x0F000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_0            0x01000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_1            0x02000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_2            0x04000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_3            0x08000000U
-
-#define  RCC_PLLI2SCFGR_PLLI2SR              0x70000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_0            0x10000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_1            0x20000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_2            0x40000000U
-
-
-/********************  Bit definition for RCC_PLLSAICFGR register  ************/
-#define  RCC_PLLSAICFGR_PLLSAIN              0x00007FC0U
-#define  RCC_PLLSAICFGR_PLLSAIN_0            0x00000040U
-#define  RCC_PLLSAICFGR_PLLSAIN_1            0x00000080U
-#define  RCC_PLLSAICFGR_PLLSAIN_2            0x00000100U
-#define  RCC_PLLSAICFGR_PLLSAIN_3            0x00000200U
-#define  RCC_PLLSAICFGR_PLLSAIN_4            0x00000400U
-#define  RCC_PLLSAICFGR_PLLSAIN_5            0x00000800U
-#define  RCC_PLLSAICFGR_PLLSAIN_6            0x00001000U
-#define  RCC_PLLSAICFGR_PLLSAIN_7            0x00002000U
-#define  RCC_PLLSAICFGR_PLLSAIN_8            0x00004000U
-
-#define  RCC_PLLSAICFGR_PLLSAIP              0x00030000U
-#define  RCC_PLLSAICFGR_PLLSAIP_0            0x00010000U
-#define  RCC_PLLSAICFGR_PLLSAIP_1            0x00020000U
-
-#define  RCC_PLLSAICFGR_PLLSAIQ              0x0F000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_0            0x01000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_1            0x02000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_2            0x04000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_3            0x08000000U
-
-#define  RCC_PLLSAICFGR_PLLSAIR              0x70000000U
-#define  RCC_PLLSAICFGR_PLLSAIR_0            0x10000000U
-#define  RCC_PLLSAICFGR_PLLSAIR_1            0x20000000U
-#define  RCC_PLLSAICFGR_PLLSAIR_2            0x40000000U
-
-/********************  Bit definition for RCC_DCKCFGR register  ***************/
-#define  RCC_DCKCFGR_PLLI2SDIVQ              0x0000001FU
-#define  RCC_DCKCFGR_PLLSAIDIVQ              0x00001F00U
-#define  RCC_DCKCFGR_PLLSAIDIVR              0x00030000U
-#define  RCC_DCKCFGR_SAI1ASRC                0x00300000U
-#define  RCC_DCKCFGR_SAI1ASRC_0              0x00100000U
-#define  RCC_DCKCFGR_SAI1ASRC_1              0x00200000U
-#define  RCC_DCKCFGR_SAI1BSRC                0x00C00000U
-#define  RCC_DCKCFGR_SAI1BSRC_0              0x00400000U
-#define  RCC_DCKCFGR_SAI1BSRC_1              0x00800000U
-#define  RCC_DCKCFGR_TIMPRE                  0x01000000U
-#define  RCC_DCKCFGR_CK48MSEL                0x08000000U
-#define  RCC_DCKCFGR_SDIOSEL                 0x10000000U
-#define  RCC_DCKCFGR_DSISEL                  0x20000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    RNG                                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN                         0x00000004U
-#define RNG_CR_IE                            0x00000008U
-
-/********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY                          0x00000001U
-#define RNG_SR_CECS                          0x00000002U
-#define RNG_SR_SECS                          0x00000004U
-#define RNG_SR_CEIS                          0x00000020U
-#define RNG_SR_SEIS                          0x00000040U
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            0x00400000U
-#define RTC_TR_HT                            0x00300000U
-#define RTC_TR_HT_0                          0x00100000U
-#define RTC_TR_HT_1                          0x00200000U
-#define RTC_TR_HU                            0x000F0000U
-#define RTC_TR_HU_0                          0x00010000U
-#define RTC_TR_HU_1                          0x00020000U
-#define RTC_TR_HU_2                          0x00040000U
-#define RTC_TR_HU_3                          0x00080000U
-#define RTC_TR_MNT                           0x00007000U
-#define RTC_TR_MNT_0                         0x00001000U
-#define RTC_TR_MNT_1                         0x00002000U
-#define RTC_TR_MNT_2                         0x00004000U
-#define RTC_TR_MNU                           0x00000F00U
-#define RTC_TR_MNU_0                         0x00000100U
-#define RTC_TR_MNU_1                         0x00000200U
-#define RTC_TR_MNU_2                         0x00000400U
-#define RTC_TR_MNU_3                         0x00000800U
-#define RTC_TR_ST                            0x00000070U
-#define RTC_TR_ST_0                          0x00000010U
-#define RTC_TR_ST_1                          0x00000020U
-#define RTC_TR_ST_2                          0x00000040U
-#define RTC_TR_SU                            0x0000000FU
-#define RTC_TR_SU_0                          0x00000001U
-#define RTC_TR_SU_1                          0x00000002U
-#define RTC_TR_SU_2                          0x00000004U
-#define RTC_TR_SU_3                          0x00000008U
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            0x00F00000U
-#define RTC_DR_YT_0                          0x00100000U
-#define RTC_DR_YT_1                          0x00200000U
-#define RTC_DR_YT_2                          0x00400000U
-#define RTC_DR_YT_3                          0x00800000U
-#define RTC_DR_YU                            0x000F0000U
-#define RTC_DR_YU_0                          0x00010000U
-#define RTC_DR_YU_1                          0x00020000U
-#define RTC_DR_YU_2                          0x00040000U
-#define RTC_DR_YU_3                          0x00080000U
-#define RTC_DR_WDU                           0x0000E000U
-#define RTC_DR_WDU_0                         0x00002000U
-#define RTC_DR_WDU_1                         0x00004000U
-#define RTC_DR_WDU_2                         0x00008000U
-#define RTC_DR_MT                            0x00001000U
-#define RTC_DR_MU                            0x00000F00U
-#define RTC_DR_MU_0                          0x00000100U
-#define RTC_DR_MU_1                          0x00000200U
-#define RTC_DR_MU_2                          0x00000400U
-#define RTC_DR_MU_3                          0x00000800U
-#define RTC_DR_DT                            0x00000030U
-#define RTC_DR_DT_0                          0x00000010U
-#define RTC_DR_DT_1                          0x00000020U
-#define RTC_DR_DU                            0x0000000FU
-#define RTC_DR_DU_0                          0x00000001U
-#define RTC_DR_DU_1                          0x00000002U
-#define RTC_DR_DU_2                          0x00000004U
-#define RTC_DR_DU_3                          0x00000008U
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           0x00800000U
-#define RTC_CR_OSEL                          0x00600000U
-#define RTC_CR_OSEL_0                        0x00200000U
-#define RTC_CR_OSEL_1                        0x00400000U
-#define RTC_CR_POL                           0x00100000U
-#define RTC_CR_COSEL                         0x00080000U
-#define RTC_CR_BCK                           0x00040000U
-#define RTC_CR_SUB1H                         0x00020000U
-#define RTC_CR_ADD1H                         0x00010000U
-#define RTC_CR_TSIE                          0x00008000U
-#define RTC_CR_WUTIE                         0x00004000U
-#define RTC_CR_ALRBIE                        0x00002000U
-#define RTC_CR_ALRAIE                        0x00001000U
-#define RTC_CR_TSE                           0x00000800U
-#define RTC_CR_WUTE                          0x00000400U
-#define RTC_CR_ALRBE                         0x00000200U
-#define RTC_CR_ALRAE                         0x00000100U
-#define RTC_CR_DCE                           0x00000080U
-#define RTC_CR_FMT                           0x00000040U
-#define RTC_CR_BYPSHAD                       0x00000020U
-#define RTC_CR_REFCKON                       0x00000010U
-#define RTC_CR_TSEDGE                        0x00000008U
-#define RTC_CR_WUCKSEL                       0x00000007U
-#define RTC_CR_WUCKSEL_0                     0x00000001U
-#define RTC_CR_WUCKSEL_1                     0x00000002U
-#define RTC_CR_WUCKSEL_2                     0x00000004U
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      0x00010000U
-#define RTC_ISR_TAMP1F                       0x00002000U
-#define RTC_ISR_TAMP2F                       0x00004000U
-#define RTC_ISR_TSOVF                        0x00001000U
-#define RTC_ISR_TSF                          0x00000800U
-#define RTC_ISR_WUTF                         0x00000400U
-#define RTC_ISR_ALRBF                        0x00000200U
-#define RTC_ISR_ALRAF                        0x00000100U
-#define RTC_ISR_INIT                         0x00000080U
-#define RTC_ISR_INITF                        0x00000040U
-#define RTC_ISR_RSF                          0x00000020U
-#define RTC_ISR_INITS                        0x00000010U
-#define RTC_ISR_SHPF                         0x00000008U
-#define RTC_ISR_WUTWF                        0x00000004U
-#define RTC_ISR_ALRBWF                       0x00000002U
-#define RTC_ISR_ALRAWF                       0x00000001U
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    0x007F0000U
-#define RTC_PRER_PREDIV_S                    0x00007FFFU
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS                       0x00000080U
-#define RTC_CALIBR_DC                        0x0000001FU
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      0x80000000U
-#define RTC_ALRMAR_WDSEL                     0x40000000U
-#define RTC_ALRMAR_DT                        0x30000000U
-#define RTC_ALRMAR_DT_0                      0x10000000U
-#define RTC_ALRMAR_DT_1                      0x20000000U
-#define RTC_ALRMAR_DU                        0x0F000000U
-#define RTC_ALRMAR_DU_0                      0x01000000U
-#define RTC_ALRMAR_DU_1                      0x02000000U
-#define RTC_ALRMAR_DU_2                      0x04000000U
-#define RTC_ALRMAR_DU_3                      0x08000000U
-#define RTC_ALRMAR_MSK3                      0x00800000U
-#define RTC_ALRMAR_PM                        0x00400000U
-#define RTC_ALRMAR_HT                        0x00300000U
-#define RTC_ALRMAR_HT_0                      0x00100000U
-#define RTC_ALRMAR_HT_1                      0x00200000U
-#define RTC_ALRMAR_HU                        0x000F0000U
-#define RTC_ALRMAR_HU_0                      0x00010000U
-#define RTC_ALRMAR_HU_1                      0x00020000U
-#define RTC_ALRMAR_HU_2                      0x00040000U
-#define RTC_ALRMAR_HU_3                      0x00080000U
-#define RTC_ALRMAR_MSK2                      0x00008000U
-#define RTC_ALRMAR_MNT                       0x00007000U
-#define RTC_ALRMAR_MNT_0                     0x00001000U
-#define RTC_ALRMAR_MNT_1                     0x00002000U
-#define RTC_ALRMAR_MNT_2                     0x00004000U
-#define RTC_ALRMAR_MNU                       0x00000F00U
-#define RTC_ALRMAR_MNU_0                     0x00000100U
-#define RTC_ALRMAR_MNU_1                     0x00000200U
-#define RTC_ALRMAR_MNU_2                     0x00000400U
-#define RTC_ALRMAR_MNU_3                     0x00000800U
-#define RTC_ALRMAR_MSK1                      0x00000080U
-#define RTC_ALRMAR_ST                        0x00000070U
-#define RTC_ALRMAR_ST_0                      0x00000010U
-#define RTC_ALRMAR_ST_1                      0x00000020U
-#define RTC_ALRMAR_ST_2                      0x00000040U
-#define RTC_ALRMAR_SU                        0x0000000FU
-#define RTC_ALRMAR_SU_0                      0x00000001U
-#define RTC_ALRMAR_SU_1                      0x00000002U
-#define RTC_ALRMAR_SU_2                      0x00000004U
-#define RTC_ALRMAR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      0x80000000U
-#define RTC_ALRMBR_WDSEL                     0x40000000U
-#define RTC_ALRMBR_DT                        0x30000000U
-#define RTC_ALRMBR_DT_0                      0x10000000U
-#define RTC_ALRMBR_DT_1                      0x20000000U
-#define RTC_ALRMBR_DU                        0x0F000000U
-#define RTC_ALRMBR_DU_0                      0x01000000U
-#define RTC_ALRMBR_DU_1                      0x02000000U
-#define RTC_ALRMBR_DU_2                      0x04000000U
-#define RTC_ALRMBR_DU_3                      0x08000000U
-#define RTC_ALRMBR_MSK3                      0x00800000U
-#define RTC_ALRMBR_PM                        0x00400000U
-#define RTC_ALRMBR_HT                        0x00300000U
-#define RTC_ALRMBR_HT_0                      0x00100000U
-#define RTC_ALRMBR_HT_1                      0x00200000U
-#define RTC_ALRMBR_HU                        0x000F0000U
-#define RTC_ALRMBR_HU_0                      0x00010000U
-#define RTC_ALRMBR_HU_1                      0x00020000U
-#define RTC_ALRMBR_HU_2                      0x00040000U
-#define RTC_ALRMBR_HU_3                      0x00080000U
-#define RTC_ALRMBR_MSK2                      0x00008000U
-#define RTC_ALRMBR_MNT                       0x00007000U
-#define RTC_ALRMBR_MNT_0                     0x00001000U
-#define RTC_ALRMBR_MNT_1                     0x00002000U
-#define RTC_ALRMBR_MNT_2                     0x00004000U
-#define RTC_ALRMBR_MNU                       0x00000F00U
-#define RTC_ALRMBR_MNU_0                     0x00000100U
-#define RTC_ALRMBR_MNU_1                     0x00000200U
-#define RTC_ALRMBR_MNU_2                     0x00000400U
-#define RTC_ALRMBR_MNU_3                     0x00000800U
-#define RTC_ALRMBR_MSK1                      0x00000080U
-#define RTC_ALRMBR_ST                        0x00000070U
-#define RTC_ALRMBR_ST_0                      0x00000010U
-#define RTC_ALRMBR_ST_1                      0x00000020U
-#define RTC_ALRMBR_ST_2                      0x00000040U
-#define RTC_ALRMBR_SU                        0x0000000FU
-#define RTC_ALRMBR_SU_0                      0x00000001U
-#define RTC_ALRMBR_SU_1                      0x00000002U
-#define RTC_ALRMBR_SU_2                      0x00000004U
-#define RTC_ALRMBR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          0x000000FFU
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           0x0000FFFFU
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     0x00007FFFU
-#define RTC_SHIFTR_ADD1S                     0x80000000U
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          0x00400000U
-#define RTC_TSTR_HT                          0x00300000U
-#define RTC_TSTR_HT_0                        0x00100000U
-#define RTC_TSTR_HT_1                        0x00200000U
-#define RTC_TSTR_HU                          0x000F0000U
-#define RTC_TSTR_HU_0                        0x00010000U
-#define RTC_TSTR_HU_1                        0x00020000U
-#define RTC_TSTR_HU_2                        0x00040000U
-#define RTC_TSTR_HU_3                        0x00080000U
-#define RTC_TSTR_MNT                         0x00007000U
-#define RTC_TSTR_MNT_0                       0x00001000U
-#define RTC_TSTR_MNT_1                       0x00002000U
-#define RTC_TSTR_MNT_2                       0x00004000U
-#define RTC_TSTR_MNU                         0x00000F00U
-#define RTC_TSTR_MNU_0                       0x00000100U
-#define RTC_TSTR_MNU_1                       0x00000200U
-#define RTC_TSTR_MNU_2                       0x00000400U
-#define RTC_TSTR_MNU_3                       0x00000800U
-#define RTC_TSTR_ST                          0x00000070U
-#define RTC_TSTR_ST_0                        0x00000010U
-#define RTC_TSTR_ST_1                        0x00000020U
-#define RTC_TSTR_ST_2                        0x00000040U
-#define RTC_TSTR_SU                          0x0000000FU
-#define RTC_TSTR_SU_0                        0x00000001U
-#define RTC_TSTR_SU_1                        0x00000002U
-#define RTC_TSTR_SU_2                        0x00000004U
-#define RTC_TSTR_SU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         0x0000E000U
-#define RTC_TSDR_WDU_0                       0x00002000U
-#define RTC_TSDR_WDU_1                       0x00004000U
-#define RTC_TSDR_WDU_2                       0x00008000U
-#define RTC_TSDR_MT                          0x00001000U
-#define RTC_TSDR_MU                          0x00000F00U
-#define RTC_TSDR_MU_0                        0x00000100U
-#define RTC_TSDR_MU_1                        0x00000200U
-#define RTC_TSDR_MU_2                        0x00000400U
-#define RTC_TSDR_MU_3                        0x00000800U
-#define RTC_TSDR_DT                          0x00000030U
-#define RTC_TSDR_DT_0                        0x00000010U
-#define RTC_TSDR_DT_1                        0x00000020U
-#define RTC_TSDR_DU                          0x0000000FU
-#define RTC_TSDR_DU_0                        0x00000001U
-#define RTC_TSDR_DU_1                        0x00000002U
-#define RTC_TSDR_DU_2                        0x00000004U
-#define RTC_TSDR_DU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        0x00008000U
-#define RTC_CALR_CALW8                       0x00004000U
-#define RTC_CALR_CALW16                      0x00002000U
-#define RTC_CALR_CALM                        0x000001FFU
-#define RTC_CALR_CALM_0                      0x00000001U
-#define RTC_CALR_CALM_1                      0x00000002U
-#define RTC_CALR_CALM_2                      0x00000004U
-#define RTC_CALR_CALM_3                      0x00000008U
-#define RTC_CALR_CALM_4                      0x00000010U
-#define RTC_CALR_CALM_5                      0x00000020U
-#define RTC_CALR_CALM_6                      0x00000040U
-#define RTC_CALR_CALM_7                      0x00000080U
-#define RTC_CALR_CALM_8                      0x00000100U
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               0x00040000U
-#define RTC_TAFCR_TSINSEL                    0x00020000U
-#define RTC_TAFCR_TAMPINSEL                  0x00010000U
-#define RTC_TAFCR_TAMPPUDIS                  0x00008000U
-#define RTC_TAFCR_TAMPPRCH                   0x00006000U
-#define RTC_TAFCR_TAMPPRCH_0                 0x00002000U
-#define RTC_TAFCR_TAMPPRCH_1                 0x00004000U
-#define RTC_TAFCR_TAMPFLT                    0x00001800U
-#define RTC_TAFCR_TAMPFLT_0                  0x00000800U
-#define RTC_TAFCR_TAMPFLT_1                  0x00001000U
-#define RTC_TAFCR_TAMPFREQ                   0x00000700U
-#define RTC_TAFCR_TAMPFREQ_0                 0x00000100U
-#define RTC_TAFCR_TAMPFREQ_1                 0x00000200U
-#define RTC_TAFCR_TAMPFREQ_2                 0x00000400U
-#define RTC_TAFCR_TAMPTS                     0x00000080U
-#define RTC_TAFCR_TAMP2TRG                   0x00000010U
-#define RTC_TAFCR_TAMP2E                     0x00000008U
-#define RTC_TAFCR_TAMPIE                     0x00000004U
-#define RTC_TAFCR_TAMP1TRG                   0x00000002U
-#define RTC_TAFCR_TAMP1E                     0x00000001U
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  0x0F000000U
-#define RTC_ALRMASSR_MASKSS_0                0x01000000U
-#define RTC_ALRMASSR_MASKSS_1                0x02000000U
-#define RTC_ALRMASSR_MASKSS_2                0x04000000U
-#define RTC_ALRMASSR_MASKSS_3                0x08000000U
-#define RTC_ALRMASSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
-#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
-#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
-#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
-#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
-#define RTC_ALRMBSSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           0xFFFFFFFFU
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Serial Audio Interface                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for SAI_GCR register  *******************/
-#define  SAI_GCR_SYNCIN                  0x00000003U        /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
-#define  SAI_GCR_SYNCIN_0                0x00000001U        /*!<Bit 0 */
-#define  SAI_GCR_SYNCIN_1                0x00000002U        /*!<Bit 1 */
-
-#define  SAI_GCR_SYNCOUT                 0x00000030U        /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
-#define  SAI_GCR_SYNCOUT_0               0x00000010U        /*!<Bit 0 */
-#define  SAI_GCR_SYNCOUT_1               0x00000020U        /*!<Bit 1 */
-
-/*******************  Bit definition for SAI_xCR1 register  *******************/
-#define  SAI_xCR1_MODE                    0x00000003U        /*!<MODE[1:0] bits (Audio Block Mode)           */
-#define  SAI_xCR1_MODE_0                  0x00000001U        /*!<Bit 0 */
-#define  SAI_xCR1_MODE_1                  0x00000002U        /*!<Bit 1 */
-
-#define  SAI_xCR1_PRTCFG                  0x0000000CU        /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
-#define  SAI_xCR1_PRTCFG_0                0x00000004U        /*!<Bit 0 */
-#define  SAI_xCR1_PRTCFG_1                0x00000008U        /*!<Bit 1 */
-
-#define  SAI_xCR1_DS                      0x000000E0U        /*!<DS[1:0] bits (Data Size) */
-#define  SAI_xCR1_DS_0                    0x00000020U        /*!<Bit 0 */
-#define  SAI_xCR1_DS_1                    0x00000040U        /*!<Bit 1 */
-#define  SAI_xCR1_DS_2                    0x00000080U        /*!<Bit 2 */
-
-#define  SAI_xCR1_LSBFIRST                0x00000100U        /*!<LSB First Configuration  */
-#define  SAI_xCR1_CKSTR                   0x00000200U        /*!<ClocK STRobing edge      */
-
-#define  SAI_xCR1_SYNCEN                  0x00000C00U        /*!<SYNCEN[1:0](SYNChronization ENable) */
-#define  SAI_xCR1_SYNCEN_0                0x00000400U        /*!<Bit 0 */
-#define  SAI_xCR1_SYNCEN_1                0x00000800U        /*!<Bit 1 */
-
-#define  SAI_xCR1_MONO                    0x00001000U        /*!<Mono mode                  */
-#define  SAI_xCR1_OUTDRIV                 0x00002000U        /*!<Output Drive               */
-#define  SAI_xCR1_SAIEN                   0x00010000U        /*!<Audio Block enable         */
-#define  SAI_xCR1_DMAEN                   0x00020000U        /*!<DMA enable                 */
-#define  SAI_xCR1_NODIV                   0x00080000U        /*!<No Divider Configuration   */
-
-#define  SAI_xCR1_MCKDIV                  0x00F00000U        /*!<MCKDIV[3:0] (Master ClocK Divider)  */
-#define  SAI_xCR1_MCKDIV_0                0x00100000U        /*!<Bit 0  */
-#define  SAI_xCR1_MCKDIV_1                0x00200000U        /*!<Bit 1  */
-#define  SAI_xCR1_MCKDIV_2                0x00400000U        /*!<Bit 2  */
-#define  SAI_xCR1_MCKDIV_3                0x00800000U        /*!<Bit 3  */
-
-/*******************  Bit definition for SAI_xCR2 register  *******************/
-#define  SAI_xCR2_FTH                     0x00000007U        /*!<FTH[2:0](Fifo THreshold)  */
-#define  SAI_xCR2_FTH_0                   0x00000001U        /*!<Bit 0 */
-#define  SAI_xCR2_FTH_1                   0x00000002U        /*!<Bit 1 */
-#define  SAI_xCR2_FTH_2                   0x00000004U        /*!<Bit 2 */
-
-#define  SAI_xCR2_FFLUSH                  0x00000008U        /*!<Fifo FLUSH                       */
-#define  SAI_xCR2_TRIS                    0x00000010U        /*!<TRIState Management on data line */
-#define  SAI_xCR2_MUTE                    0x00000020U        /*!<Mute mode                        */
-#define  SAI_xCR2_MUTEVAL                 0x00000040U        /*!<Muate value                      */
-
-#define  SAI_xCR2_MUTECNT                  0x00001F80U       /*!<MUTECNT[5:0] (MUTE counter) */
-#define  SAI_xCR2_MUTECNT_0               0x00000080U        /*!<Bit 0 */
-#define  SAI_xCR2_MUTECNT_1               0x00000100U        /*!<Bit 1 */
-#define  SAI_xCR2_MUTECNT_2               0x00000200U        /*!<Bit 2 */
-#define  SAI_xCR2_MUTECNT_3               0x00000400U        /*!<Bit 3 */
-#define  SAI_xCR2_MUTECNT_4               0x00000800U        /*!<Bit 4 */
-#define  SAI_xCR2_MUTECNT_5               0x00001000U        /*!<Bit 5 */
-
-#define  SAI_xCR2_CPL                     0x00002000U        /*!< Complement Bit             */
-
-#define  SAI_xCR2_COMP                    0x0000C000U        /*!<COMP[1:0] (Companding mode) */
-#define  SAI_xCR2_COMP_0                  0x00004000U        /*!<Bit 0 */
-#define  SAI_xCR2_COMP_1                  0x00008000U        /*!<Bit 1 */
-
-/******************  Bit definition for SAI_xFRCR register  *******************/
-#define  SAI_xFRCR_FRL                    0x000000FFU        /*!<FRL[1:0](Frame length)  */
-#define  SAI_xFRCR_FRL_0                  0x00000001U        /*!<Bit 0 */
-#define  SAI_xFRCR_FRL_1                  0x00000002U        /*!<Bit 1 */
-#define  SAI_xFRCR_FRL_2                  0x00000004U        /*!<Bit 2 */
-#define  SAI_xFRCR_FRL_3                  0x00000008U        /*!<Bit 3 */
-#define  SAI_xFRCR_FRL_4                  0x00000010U        /*!<Bit 4 */
-#define  SAI_xFRCR_FRL_5                  0x00000020U        /*!<Bit 5 */
-#define  SAI_xFRCR_FRL_6                  0x00000040U        /*!<Bit 6 */
-#define  SAI_xFRCR_FRL_7                  0x00000080U        /*!<Bit 7 */
-
-#define  SAI_xFRCR_FSALL                  0x00007F00U        /*!<FRL[1:0] (Frame synchronization active level length)  */
-#define  SAI_xFRCR_FSALL_0                0x00000100U        /*!<Bit 0 */
-#define  SAI_xFRCR_FSALL_1                0x00000200U        /*!<Bit 1 */
-#define  SAI_xFRCR_FSALL_2                0x00000400U        /*!<Bit 2 */
-#define  SAI_xFRCR_FSALL_3                0x00000800U        /*!<Bit 3 */
-#define  SAI_xFRCR_FSALL_4                0x00001000U        /*!<Bit 4 */
-#define  SAI_xFRCR_FSALL_5                0x00002000U        /*!<Bit 5 */
-#define  SAI_xFRCR_FSALL_6                0x00004000U        /*!<Bit 6 */
-
-#define  SAI_xFRCR_FSDEF                  0x00010000U        /*!< Frame Synchronization Definition */
-#define  SAI_xFRCR_FSPOL                  0x00020000U        /*!<Frame Synchronization POLarity    */
-#define  SAI_xFRCR_FSOFF                  0x00040000U        /*!<Frame Synchronization OFFset      */
-/* Legacy defines */
-#define  SAI_xFRCR_FSPO                   SAI_xFRCR_FSPOL
-
-/******************  Bit definition for SAI_xSLOTR register  *******************/
-#define  SAI_xSLOTR_FBOFF                 0x0000001FU        /*!<FRL[4:0](First Bit Offset)  */
-#define  SAI_xSLOTR_FBOFF_0               0x00000001U        /*!<Bit 0 */
-#define  SAI_xSLOTR_FBOFF_1               0x00000002U        /*!<Bit 1 */
-#define  SAI_xSLOTR_FBOFF_2               0x00000004U        /*!<Bit 2 */
-#define  SAI_xSLOTR_FBOFF_3               0x00000008U        /*!<Bit 3 */
-#define  SAI_xSLOTR_FBOFF_4               0x00000010U        /*!<Bit 4 */
-
-#define  SAI_xSLOTR_SLOTSZ                0x000000C0U        /*!<SLOTSZ[1:0] (Slot size)  */
-#define  SAI_xSLOTR_SLOTSZ_0              0x00000040U        /*!<Bit 0 */
-#define  SAI_xSLOTR_SLOTSZ_1              0x00000080U        /*!<Bit 1 */
-
-#define  SAI_xSLOTR_NBSLOT                0x00000F00U        /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
-#define  SAI_xSLOTR_NBSLOT_0              0x00000100U        /*!<Bit 0 */
-#define  SAI_xSLOTR_NBSLOT_1              0x00000200U        /*!<Bit 1 */
-#define  SAI_xSLOTR_NBSLOT_2              0x00000400U        /*!<Bit 2 */
-#define  SAI_xSLOTR_NBSLOT_3              0x00000800U        /*!<Bit 3 */
-
-#define  SAI_xSLOTR_SLOTEN                0xFFFF0000U        /*!<SLOTEN[15:0] (Slot Enable)  */
-
-/*******************  Bit definition for SAI_xIMR register  *******************/
-#define  SAI_xIMR_OVRUDRIE                0x00000001U        /*!<Overrun underrun interrupt enable                              */
-#define  SAI_xIMR_MUTEDETIE               0x00000002U        /*!<Mute detection interrupt enable                                */
-#define  SAI_xIMR_WCKCFGIE                0x00000004U        /*!<Wrong Clock Configuration interrupt enable                     */
-#define  SAI_xIMR_FREQIE                  0x00000008U        /*!<FIFO request interrupt enable                                  */
-#define  SAI_xIMR_CNRDYIE                 0x00000010U        /*!<Codec not ready interrupt enable                               */
-#define  SAI_xIMR_AFSDETIE                0x00000020U        /*!<Anticipated frame synchronization detection interrupt enable   */
-#define  SAI_xIMR_LFSDETIE                0x00000040U        /*!<Late frame synchronization detection interrupt enable          */
-
-/********************  Bit definition for SAI_xSR register  *******************/
-#define  SAI_xSR_OVRUDR                   0x00000001U         /*!<Overrun underrun                               */
-#define  SAI_xSR_MUTEDET                  0x00000002U         /*!<Mute detection                                 */
-#define  SAI_xSR_WCKCFG                   0x00000004U         /*!<Wrong Clock Configuration                      */
-#define  SAI_xSR_FREQ                     0x00000008U         /*!<FIFO request                                   */
-#define  SAI_xSR_CNRDY                    0x00000010U         /*!<Codec not ready                                */
-#define  SAI_xSR_AFSDET                   0x00000020U         /*!<Anticipated frame synchronization detection    */
-#define  SAI_xSR_LFSDET                   0x00000040U         /*!<Late frame synchronization detection           */
-
-#define  SAI_xSR_FLVL                     0x00070000U         /*!<FLVL[2:0] (FIFO Level Threshold)               */
-#define  SAI_xSR_FLVL_0                   0x00010000U         /*!<Bit 0 */
-#define  SAI_xSR_FLVL_1                   0x00020000U         /*!<Bit 1 */
-#define  SAI_xSR_FLVL_2                   0x00040000U         /*!<Bit 2 */
-
-/******************  Bit definition for SAI_xCLRFR register  ******************/
-#define  SAI_xCLRFR_COVRUDR               0x00000001U        /*!<Clear Overrun underrun                               */
-#define  SAI_xCLRFR_CMUTEDET              0x00000002U        /*!<Clear Mute detection                                 */
-#define  SAI_xCLRFR_CWCKCFG               0x00000004U        /*!<Clear Wrong Clock Configuration                      */
-#define  SAI_xCLRFR_CFREQ                 0x00000008U        /*!<Clear FIFO request                                   */
-#define  SAI_xCLRFR_CCNRDY                0x00000010U        /*!<Clear Codec not ready                                */
-#define  SAI_xCLRFR_CAFSDET               0x00000020U        /*!<Clear Anticipated frame synchronization detection    */
-#define  SAI_xCLRFR_CLFSDET               0x00000040U        /*!<Clear Late frame synchronization detection           */
-
-/******************  Bit definition for SAI_xDR register  ******************/
-#define  SAI_xDR_DATA                     0xFFFFFFFFU        
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          SD host Interface                                 */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SDIO_POWER register  ******************/
-#define  SDIO_POWER_PWRCTRL                  0x03U               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDIO_POWER_PWRCTRL_0                0x01U               /*!<Bit 0 */
-#define  SDIO_POWER_PWRCTRL_1                0x02U               /*!<Bit 1 */
-
-/******************  Bit definition for SDIO_CLKCR register  ******************/
-#define  SDIO_CLKCR_CLKDIV                   0x00FFU            /*!<Clock divide factor             */
-#define  SDIO_CLKCR_CLKEN                    0x0100U            /*!<Clock enable bit                */
-#define  SDIO_CLKCR_PWRSAV                   0x0200U            /*!<Power saving configuration bit  */
-#define  SDIO_CLKCR_BYPASS                   0x0400U            /*!<Clock divider bypass enable bit */
-
-#define  SDIO_CLKCR_WIDBUS                   0x1800U            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDIO_CLKCR_WIDBUS_0                 0x0800U            /*!<Bit 0 */
-#define  SDIO_CLKCR_WIDBUS_1                 0x1000U            /*!<Bit 1 */
-
-#define  SDIO_CLKCR_NEGEDGE                  0x2000U            /*!<SDIO_CK dephasing selection bit */
-#define  SDIO_CLKCR_HWFC_EN                  0x4000U            /*!<HW Flow Control enable          */
-
-/*******************  Bit definition for SDIO_ARG register  *******************/
-#define  SDIO_ARG_CMDARG                     0xFFFFFFFFU            /*!<Command argument */
-
-/*******************  Bit definition for SDIO_CMD register  *******************/
-#define  SDIO_CMD_CMDINDEX                   0x003FU            /*!<Command Index                               */
-
-#define  SDIO_CMD_WAITRESP                   0x00C0U            /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDIO_CMD_WAITRESP_0                 0x0040U            /*!< Bit 0 */
-#define  SDIO_CMD_WAITRESP_1                 0x0080U            /*!< Bit 1 */
-
-#define  SDIO_CMD_WAITINT                    0x0100U            /*!<CPSM Waits for Interrupt Request                               */
-#define  SDIO_CMD_WAITPEND                   0x0200U            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDIO_CMD_CPSMEN                     0x0400U            /*!<Command path state machine (CPSM) Enable bit                   */
-#define  SDIO_CMD_SDIOSUSPEND                0x0800U            /*!<SD I/O suspend command                                         */
-
-/*****************  Bit definition for SDIO_RESPCMD register  *****************/
-#define  SDIO_RESPCMD_RESPCMD                0x3FU               /*!<Response command index */
-
-/******************  Bit definition for SDIO_RESP0 register  ******************/
-#define  SDIO_RESP0_CARDSTATUS0              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP1 register  ******************/
-#define  SDIO_RESP1_CARDSTATUS1              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP2 register  ******************/
-#define  SDIO_RESP2_CARDSTATUS2              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP3 register  ******************/
-#define  SDIO_RESP3_CARDSTATUS3              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP4 register  ******************/
-#define  SDIO_RESP4_CARDSTATUS4              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_DTIMER register  *****************/
-#define  SDIO_DTIMER_DATATIME                0xFFFFFFFFU        /*!<Data timeout period. */
-
-/******************  Bit definition for SDIO_DLEN register  *******************/
-#define  SDIO_DLEN_DATALENGTH                0x01FFFFFFU        /*!<Data length value    */
-
-/******************  Bit definition for SDIO_DCTRL register  ******************/
-#define  SDIO_DCTRL_DTEN                     0x0001U            /*!<Data transfer enabled bit         */
-#define  SDIO_DCTRL_DTDIR                    0x0002U            /*!<Data transfer direction selection */
-#define  SDIO_DCTRL_DTMODE                   0x0004U            /*!<Data transfer mode selection      */
-#define  SDIO_DCTRL_DMAEN                    0x0008U            /*!<DMA enabled bit                   */
-
-#define  SDIO_DCTRL_DBLOCKSIZE               0x00F0U            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDIO_DCTRL_DBLOCKSIZE_0             0x0010U            /*!<Bit 0 */
-#define  SDIO_DCTRL_DBLOCKSIZE_1             0x0020U            /*!<Bit 1 */
-#define  SDIO_DCTRL_DBLOCKSIZE_2             0x0040U            /*!<Bit 2 */
-#define  SDIO_DCTRL_DBLOCKSIZE_3             0x0080U            /*!<Bit 3 */
-
-#define  SDIO_DCTRL_RWSTART                  0x0100U            /*!<Read wait start         */
-#define  SDIO_DCTRL_RWSTOP                   0x0200U            /*!<Read wait stop          */
-#define  SDIO_DCTRL_RWMOD                    0x0400U            /*!<Read wait mode          */
-#define  SDIO_DCTRL_SDIOEN                   0x0800U            /*!<SD I/O enable functions */
-
-/******************  Bit definition for SDIO_DCOUNT register  *****************/
-#define  SDIO_DCOUNT_DATACOUNT               0x01FFFFFFU        /*!<Data count value */
-
-/******************  Bit definition for SDIO_STA register  ********************/
-#define  SDIO_STA_CCRCFAIL                   0x00000001U        /*!<Command response received (CRC check failed)  */
-#define  SDIO_STA_DCRCFAIL                   0x00000002U        /*!<Data block sent/received (CRC check failed)   */
-#define  SDIO_STA_CTIMEOUT                   0x00000004U        /*!<Command response timeout                      */
-#define  SDIO_STA_DTIMEOUT                   0x00000008U        /*!<Data timeout                                  */
-#define  SDIO_STA_TXUNDERR                   0x00000010U        /*!<Transmit FIFO underrun error                  */
-#define  SDIO_STA_RXOVERR                    0x00000020U        /*!<Received FIFO overrun error                   */
-#define  SDIO_STA_CMDREND                    0x00000040U        /*!<Command response received (CRC check passed)  */
-#define  SDIO_STA_CMDSENT                    0x00000080U        /*!<Command sent (no response required)           */
-#define  SDIO_STA_DATAEND                    0x00000100U        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
-#define  SDIO_STA_DBCKEND                    0x00000400U        /*!<Data block sent/received (CRC check passed)   */
-#define  SDIO_STA_CMDACT                     0x00000800U        /*!<Command transfer in progress                  */
-#define  SDIO_STA_TXACT                      0x00001000U        /*!<Data transmit in progress                     */
-#define  SDIO_STA_RXACT                      0x00002000U        /*!<Data receive in progress                      */
-#define  SDIO_STA_TXFIFOHE                   0x00004000U        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDIO_STA_RXFIFOHF                   0x00008000U        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDIO_STA_TXFIFOF                    0x00010000U        /*!<Transmit FIFO full                            */
-#define  SDIO_STA_RXFIFOF                    0x00020000U        /*!<Receive FIFO full                             */
-#define  SDIO_STA_TXFIFOE                    0x00040000U        /*!<Transmit FIFO empty                           */
-#define  SDIO_STA_RXFIFOE                    0x00080000U        /*!<Receive FIFO empty                            */
-#define  SDIO_STA_TXDAVL                     0x00100000U        /*!<Data available in transmit FIFO               */
-#define  SDIO_STA_RXDAVL                     0x00200000U        /*!<Data available in receive FIFO                */
-#define  SDIO_STA_SDIOIT                     0x00400000U        /*!<SDIO interrupt received                       */
-
-/*******************  Bit definition for SDIO_ICR register  *******************/
-#define  SDIO_ICR_CCRCFAILC                  0x00000001U        /*!<CCRCFAIL flag clear bit */
-#define  SDIO_ICR_DCRCFAILC                  0x00000002U        /*!<DCRCFAIL flag clear bit */
-#define  SDIO_ICR_CTIMEOUTC                  0x00000004U        /*!<CTIMEOUT flag clear bit */
-#define  SDIO_ICR_DTIMEOUTC                  0x00000008U        /*!<DTIMEOUT flag clear bit */
-#define  SDIO_ICR_TXUNDERRC                  0x00000010U        /*!<TXUNDERR flag clear bit */
-#define  SDIO_ICR_RXOVERRC                   0x00000020U        /*!<RXOVERR flag clear bit  */
-#define  SDIO_ICR_CMDRENDC                   0x00000040U        /*!<CMDREND flag clear bit  */
-#define  SDIO_ICR_CMDSENTC                   0x00000080U        /*!<CMDSENT flag clear bit  */
-#define  SDIO_ICR_DATAENDC                   0x00000100U        /*!<DATAEND flag clear bit  */
-#define  SDIO_ICR_DBCKENDC                   0x00000400U        /*!<DBCKEND flag clear bit  */
-#define  SDIO_ICR_SDIOITC                    0x00400000U        /*!<SDIOIT flag clear bit   */
-
-/******************  Bit definition for SDIO_MASK register  *******************/
-#define  SDIO_MASK_CCRCFAILIE                0x00000001U        /*!<Command CRC Fail Interrupt Enable          */
-#define  SDIO_MASK_DCRCFAILIE                0x00000002U        /*!<Data CRC Fail Interrupt Enable             */
-#define  SDIO_MASK_CTIMEOUTIE                0x00000004U        /*!<Command TimeOut Interrupt Enable           */
-#define  SDIO_MASK_DTIMEOUTIE                0x00000008U        /*!<Data TimeOut Interrupt Enable              */
-#define  SDIO_MASK_TXUNDERRIE                0x00000010U        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
-#define  SDIO_MASK_RXOVERRIE                 0x00000020U        /*!<Rx FIFO OverRun Error Interrupt Enable     */
-#define  SDIO_MASK_CMDRENDIE                 0x00000040U        /*!<Command Response Received Interrupt Enable */
-#define  SDIO_MASK_CMDSENTIE                 0x00000080U        /*!<Command Sent Interrupt Enable              */
-#define  SDIO_MASK_DATAENDIE                 0x00000100U        /*!<Data End Interrupt Enable                  */
-#define  SDIO_MASK_DBCKENDIE                 0x00000400U        /*!<Data Block End Interrupt Enable            */
-#define  SDIO_MASK_CMDACTIE                  0x00000800U        /*!<CCommand Acting Interrupt Enable           */
-#define  SDIO_MASK_TXACTIE                   0x00001000U        /*!<Data Transmit Acting Interrupt Enable      */
-#define  SDIO_MASK_RXACTIE                   0x00002000U        /*!<Data receive acting interrupt enabled      */
-#define  SDIO_MASK_TXFIFOHEIE                0x00004000U        /*!<Tx FIFO Half Empty interrupt Enable        */
-#define  SDIO_MASK_RXFIFOHFIE                0x00008000U        /*!<Rx FIFO Half Full interrupt Enable         */
-#define  SDIO_MASK_TXFIFOFIE                 0x00010000U        /*!<Tx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_RXFIFOFIE                 0x00020000U        /*!<Rx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_TXFIFOEIE                 0x00040000U        /*!<Tx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_RXFIFOEIE                 0x00080000U        /*!<Rx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_TXDAVLIE                  0x00100000U        /*!<Data available in Tx FIFO interrupt Enable */
-#define  SDIO_MASK_RXDAVLIE                  0x00200000U        /*!<Data available in Rx FIFO interrupt Enable */
-#define  SDIO_MASK_SDIOITIE                  0x00400000U        /*!<SDIO Mode Interrupt Received interrupt Enable */
-
-/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
-#define  SDIO_FIFOCNT_FIFOCOUNT              0x00FFFFFFU        /*!<Remaining number of words to be written to or read from the FIFO */
-
-/******************  Bit definition for SDIO_FIFO register  *******************/
-#define  SDIO_FIFO_FIFODATA                  0xFFFFFFFFU        /*!<Receive and transmit FIFO data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        0x00000001U            /*!<Clock Phase      */
-#define  SPI_CR1_CPOL                        0x00000002U            /*!<Clock Polarity   */
-#define  SPI_CR1_MSTR                        0x00000004U            /*!<Master Selection */
-
-#define  SPI_CR1_BR                          0x00000038U            /*!<BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        0x00000008U            /*!<Bit 0 */
-#define  SPI_CR1_BR_1                        0x00000010U            /*!<Bit 1 */
-#define  SPI_CR1_BR_2                        0x00000020U            /*!<Bit 2 */
-
-#define  SPI_CR1_SPE                         0x00000040U            /*!<SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    0x00000080U            /*!<Frame Format                        */
-#define  SPI_CR1_SSI                         0x00000100U            /*!<Internal slave select               */
-#define  SPI_CR1_SSM                         0x00000200U            /*!<Software slave management           */
-#define  SPI_CR1_RXONLY                      0x00000400U            /*!<Receive only                        */
-#define  SPI_CR1_DFF                         0x00000800U            /*!<Data Frame Format                   */
-#define  SPI_CR1_CRCNEXT                     0x00001000U            /*!<Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       0x00002000U            /*!<Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      0x00004000U            /*!<Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    0x00008000U            /*!<Bidirectional data mode enable      */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     0x00000001U               /*!<Rx Buffer DMA Enable                 */
-#define  SPI_CR2_TXDMAEN                     0x00000002U               /*!<Tx Buffer DMA Enable                 */
-#define  SPI_CR2_SSOE                        0x00000004U               /*!<SS Output Enable                     */
-#define  SPI_CR2_FRF                         0x00000010U               /*!<Frame Format                         */
-#define  SPI_CR2_ERRIE                       0x00000020U               /*!<Error Interrupt Enable               */
-#define  SPI_CR2_RXNEIE                      0x00000040U               /*!<RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       0x00000080U               /*!<Tx buffer Empty Interrupt Enable     */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         0x00000001U               /*!<Receive buffer Not Empty */
-#define  SPI_SR_TXE                          0x00000002U               /*!<Transmit buffer Empty    */
-#define  SPI_SR_CHSIDE                       0x00000004U               /*!<Channel side             */
-#define  SPI_SR_UDR                          0x00000008U               /*!<Underrun flag            */
-#define  SPI_SR_CRCERR                       0x00000010U               /*!<CRC Error flag           */
-#define  SPI_SR_MODF                         0x00000020U               /*!<Mode fault               */
-#define  SPI_SR_OVR                          0x00000040U               /*!<Overrun flag             */
-#define  SPI_SR_BSY                          0x00000080U               /*!<Busy flag                */
-#define  SPI_SR_FRE                          0x00000100U               /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           0x0000FFFFU            /*!<Data Register           */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   0x0000FFFFU            /*!<CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    0x0000FFFFU            /*!<Rx CRC Register         */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    0x0000FFFFU            /*!<Tx CRC Register         */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   0x00000001U            /*!<Channel length (number of bits per audio channel) */
-
-#define  SPI_I2SCFGR_DATLEN                  0x00000006U            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define  SPI_I2SCFGR_DATLEN_0                0x00000002U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                0x00000004U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_CKPOL                   0x00000008U            /*!<steady state clock polarity               */
-
-#define  SPI_I2SCFGR_I2SSTD                  0x00000030U            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U            /*!<PCM frame synchronization                 */
-
-#define  SPI_I2SCFGR_I2SCFG                  0x00000300U            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_I2SE                    0x00000400U            /*!<I2S Enable         */
-#define  SPI_I2SCFGR_I2SMOD                  0x00000800U            /*!<I2S mode selection */
-#define  SPI_I2SCFGR_ASTRTEN                 0x00001000U            /*!<Asynchronous start enable */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    0x000000FFU            /*!<I2S Linear prescaler         */
-#define  SPI_I2SPR_ODD                       0x00000100U            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     0x00000200U            /*!<Master Clock Output Enable   */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 SYSCFG                                     */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
-#define SYSCFG_MEMRMP_MEM_MODE          0x00000007U /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        0x00000001U
-#define SYSCFG_MEMRMP_MEM_MODE_1        0x00000002U
-#define SYSCFG_MEMRMP_MEM_MODE_2        0x00000004U
-
-#define SYSCFG_MEMRMP_UFB_MODE          0x00000100U /*!< User Flash Bank mode    */
-#define SYSCFG_SWP_FMC                  0x00000C00U /*!< FMC memory mapping swap */
-
-/******************  Bit definition for SYSCFG_PMC register  ******************/
-#define SYSCFG_PMC_ADCxDC2              0x00070000U /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC1DC2              0x00010000U /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC2DC2              0x00020000U /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC3DC2              0x00040000U /*!< Refer to AN4073 on how to use this bit  */
-
-#define SYSCFG_PMC_MII_RMII_SEL         0x00800000U /*!<Ethernet PHY interface selection */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
-/** 
-  * @brief   EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         0x0003U /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         0x0004U /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         0x0005U /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         0x0006U /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PI         0x0008U /*!<PI[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PJ         0x0009U /*!<PJ[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PK         0x000AU /*!<PK[0] pin */
-
-/** 
-  * @brief   EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         0x0030U /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         0x0040U /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         0x0050U /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         0x0060U /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PI         0x0080U /*!<PI[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PJ         0x0090U /*!<PJ[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PK         0x00A0U /*!<PK[1] pin */
-
-
-/** 
-  * @brief   EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         0x0300U /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         0x0400U /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         0x0500U /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         0x0600U /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PI         0x0800U /*!<PI[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PJ         0x0900U /*!<PJ[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PK         0x0A00U /*!<PK[2] pin */
-
-
-/** 
-  * @brief   EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         0x3000U /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         0x4000U /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         0x5000U /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         0x6000U /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PI         0x8000U /*!<PI[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PJ         0x9000U /*!<PJ[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PK         0xA000U /*!<PK[3] pin */
-
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
-/** 
-  * @brief   EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         0x0003U /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         0x0004U /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         0x0005U /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         0x0006U /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PI         0x0008U /*!<PI[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PJ         0x0009U /*!<PJ[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PK         0x000AU /*!<PK[4] pin */
-
-/** 
-  * @brief   EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         0x0030U /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         0x0040U /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         0x0050U /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         0x0060U /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PI         0x0080U /*!<PI[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PJ         0x0090U /*!<PJ[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PK         0x00A0U /*!<PK[5] pin */
-
-/** 
-  * @brief   EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         0x0300U /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         0x0400U /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         0x0500U /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         0x0600U /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PI         0x0800U /*!<PI[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PJ         0x0900U /*!<PJ[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PK         0x0A00U /*!<PK[6] pin */
-
-
-/** 
-  * @brief   EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         0x3000U /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         0x4000U /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         0x5000U /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         0x6000U /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PI         0x8000U /*!<PI[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PJ         0x9000U /*!<PJ[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PK         0xA000U /*!<PK[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
-           
-/** 
-  * @brief   EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         0x0003U /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         0x0004U /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         0x0005U /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         0x0006U /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PI         0x0008U /*!<PI[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PJ         0x0009U /*!<PJ[8] pin */
-
-/** 
-  * @brief   EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         0x0030U /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         0x0040U /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         0x0050U /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         0x0060U /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PI         0x0080U /*!<PI[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PJ         0x0090U /*!<PJ[9] pin */
-
-
-/** 
-  * @brief   EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        0x0300U /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        0x0400U /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        0x0500U /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        0x0600U /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PI        0x0800U /*!<PI[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PJ        0x0900U /*!<PJ[10] pin */
-
-
-/** 
-  * @brief   EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        0x3000U /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        0x4000U /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        0x5000U /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        0x6000U /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PI        0x8000U /*!<PI[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PJ        0x9000U /*!<PJ[11] pin */
-
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
-/** 
-  * @brief   EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        0x0003U /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        0x0004U /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        0x0005U /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        0x0006U /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PI        0x0008U /*!<PI[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PJ        0x0009U /*!<PJ[12] pin */
-
-
-/** 
-  * @brief   EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        0x0030U /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        0x0040U /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        0x0050U /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        0x0060U /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PI        0x0008U /*!<PI[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PJ        0x0009U /*!<PJ[13] pin */
-
-
-/** 
-  * @brief   EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        0x0300U /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        0x0400U /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        0x0500U /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        0x0600U /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PI        0x0800U /*!<PI[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PJ        0x0900U /*!<PJ[14] pin */
-
-
-/** 
-  * @brief   EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        0x3000U /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        0x4000U /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        0x5000U /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        0x6000U /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PI        0x8000U /*!<PI[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PJ        0x9000U /*!<PJ[15] pin */
-
-/******************  Bit definition for SYSCFG_CMPCR register  ****************/  
-#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell ready flag */
-#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell power-down */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    TIM                                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
-#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
-#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
-#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
-#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
-
-#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
-
-#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
-
-#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        0x0001U            /*!<Capture/Compare Preloaded Control        */
-#define  TIM_CR2_CCUS                        0x0004U            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        0x0008U            /*!<Capture/Compare DMA Selection            */
-
-#define  TIM_CR2_MMS                         0x0070U            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
-#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
-#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
-#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        0x0007U            /*!<SMS[2:0] bits (Slave mode selection)    */
-#define  TIM_SMCR_SMS_0                      0x0001U            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      0x0002U            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      0x0004U            /*!<Bit 2 */
-
-#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
-#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
-
-#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
-
-#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
-
-#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
-#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
-#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
-#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
-#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
-#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
-#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
-#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
-#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
-#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
-#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
-#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
-#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
-#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
-#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
-#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
-#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
-#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
-#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          0x01U               /*!<Update Generation                         */
-#define  TIM_EGR_CC1G                        0x02U               /*!<Capture/Compare 1 Generation              */
-#define  TIM_EGR_CC2G                        0x04U               /*!<Capture/Compare 2 Generation              */
-#define  TIM_EGR_CC3G                        0x08U               /*!<Capture/Compare 3 Generation              */
-#define  TIM_EGR_CC4G                        0x10U               /*!<Capture/Compare 4 Generation              */
-#define  TIM_EGR_COMG                        0x20U               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          0x40U               /*!<Trigger Generation                        */
-#define  TIM_EGR_BG                          0x80U               /*!<Break Generation                          */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      0x0003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    0x0001U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    0x0002U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC1FE                     0x0004U            /*!<Output Compare 1 Fast enable                 */
-#define  TIM_CCMR1_OC1PE                     0x0008U            /*!<Output Compare 1 Preload enable              */
-
-#define  TIM_CCMR1_OC1M                      0x0070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define  TIM_CCMR1_OC1M_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    0x0040U            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC1CE                     0x0080U            /*!<Output Compare 1Clear Enable                 */
-
-#define  TIM_CCMR1_CC2S                      0x0300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    0x0100U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    0x0200U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC2FE                     0x0400U            /*!<Output Compare 2 Fast enable                 */
-#define  TIM_CCMR1_OC2PE                     0x0800U            /*!<Output Compare 2 Preload enable              */
-
-#define  TIM_CCMR1_OC2M                      0x7000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define  TIM_CCMR1_OC2M_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    0x4000U            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC2CE                     0x8000U            /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      0x0003U            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define  TIM_CCMR2_CC3S_0                    0x0001U            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    0x0002U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC3FE                     0x0004U            /*!<Output Compare 3 Fast enable           */
-#define  TIM_CCMR2_OC3PE                     0x0008U            /*!<Output Compare 3 Preload enable        */
-
-#define  TIM_CCMR2_OC3M                      0x0070U            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    0x0040U            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC3CE                     0x0080U            /*!<Output Compare 3 Clear Enable */
-
-#define  TIM_CCMR2_CC4S                      0x0300U            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    0x0100U            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    0x0200U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC4FE                     0x0400U            /*!<Output Compare 4 Fast enable    */
-#define  TIM_CCMR2_OC4PE                     0x0800U            /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR2_OC4M                      0x7000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    0x4000U            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       0x0001U            /*!<Capture/Compare 1 output enable                 */
-#define  TIM_CCER_CC1P                       0x0002U            /*!<Capture/Compare 1 output Polarity               */
-#define  TIM_CCER_CC1NE                      0x0004U            /*!<Capture/Compare 1 Complementary output enable   */
-#define  TIM_CCER_CC1NP                      0x0008U            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       0x0010U            /*!<Capture/Compare 2 output enable                 */
-#define  TIM_CCER_CC2P                       0x0020U            /*!<Capture/Compare 2 output Polarity               */
-#define  TIM_CCER_CC2NE                      0x0040U            /*!<Capture/Compare 2 Complementary output enable   */
-#define  TIM_CCER_CC2NP                      0x0080U            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       0x0100U            /*!<Capture/Compare 3 output enable                 */
-#define  TIM_CCER_CC3P                       0x0200U            /*!<Capture/Compare 3 output Polarity               */
-#define  TIM_CCER_CC3NE                      0x0400U            /*!<Capture/Compare 3 Complementary output enable   */
-#define  TIM_CCER_CC3NP                      0x0800U            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       0x1000U            /*!<Capture/Compare 4 output enable                 */
-#define  TIM_CCER_CC4P                       0x2000U            /*!<Capture/Compare 4 output Polarity               */
-#define  TIM_CCER_CC4NP                      0x8000U            /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         0xFFU               /*!<Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
-
-/*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        0x00FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      0x0001U            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      0x0002U            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      0x0004U            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      0x0008U            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      0x0010U            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      0x0020U            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      0x0040U            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      0x0080U            /*!<Bit 7 */
-
-#define  TIM_BDTR_LOCK                       0x0300U            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     0x0100U            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     0x0200U            /*!<Bit 1 */
-
-#define  TIM_BDTR_OSSI                       0x0400U            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       0x0800U            /*!<Off-State Selection for Run mode  */
-#define  TIM_BDTR_BKE                        0x1000U            /*!<Break enable                      */
-#define  TIM_BDTR_BKP                        0x2000U            /*!<Break Polarity                    */
-#define  TIM_BDTR_AOE                        0x4000U            /*!<Automatic Output enable           */
-#define  TIM_BDTR_MOE                        0x8000U            /*!<Main Output enable                */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
-
-#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
-#define TIM_OR_ITR1_RMP                      0x0C00U            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
-#define TIM_OR_ITR1_RMP_0                    0x0400U            /*!<Bit 0 */
-#define TIM_OR_ITR1_RMP_1                    0x0800U            /*!<Bit 1 */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*         Universal Synchronous Asynchronous Receiver Transmitter            */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         0x0001U            /*!<Parity Error                 */
-#define  USART_SR_FE                         0x0002U            /*!<Framing Error                */
-#define  USART_SR_NE                         0x0004U            /*!<Noise Error Flag             */
-#define  USART_SR_ORE                        0x0008U            /*!<OverRun Error                */
-#define  USART_SR_IDLE                       0x0010U            /*!<IDLE line detected           */
-#define  USART_SR_RXNE                       0x0020U            /*!<Read Data Register Not Empty */
-#define  USART_SR_TC                         0x0040U            /*!<Transmission Complete        */
-#define  USART_SR_TXE                        0x0080U            /*!<Transmit Data Register Empty */
-#define  USART_SR_LBD                        0x0100U            /*!<LIN Break Detection Flag     */
-#define  USART_SR_CTS                        0x0200U            /*!<CTS Flag                     */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         0x01FFU            /*!<Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_Fraction              0x000FU            /*!<Fraction of USARTDIV */
-#define  USART_BRR_DIV_Mantissa              0xFFF0U            /*!<Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       0x0001U            /*!<Send Break                             */
-#define  USART_CR1_RWU                       0x0002U            /*!<Receiver wakeup                        */
-#define  USART_CR1_RE                        0x0004U            /*!<Receiver Enable                        */
-#define  USART_CR1_TE                        0x0008U            /*!<Transmitter Enable                     */
-#define  USART_CR1_IDLEIE                    0x0010U            /*!<IDLE Interrupt Enable                  */
-#define  USART_CR1_RXNEIE                    0x0020U            /*!<RXNE Interrupt Enable                  */
-#define  USART_CR1_TCIE                      0x0040U            /*!<Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     0x0080U            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PEIE                      0x0100U            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PS                        0x0200U            /*!<Parity Selection                       */
-#define  USART_CR1_PCE                       0x0400U            /*!<Parity Control Enable                  */
-#define  USART_CR1_WAKE                      0x0800U            /*!<Wakeup method                          */
-#define  USART_CR1_M                         0x1000U            /*!<Word length                            */
-#define  USART_CR1_UE                        0x2000U            /*!<USART Enable                           */
-#define  USART_CR1_OVER8                     0x8000U            /*!<USART Oversampling by 8 enable         */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       0x000FU            /*!<Address of the USART node            */
-#define  USART_CR2_LBDL                      0x0020U            /*!<LIN Break Detection Length           */
-#define  USART_CR2_LBDIE                     0x0040U            /*!<LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      0x0100U            /*!<Last Bit Clock pulse                 */
-#define  USART_CR2_CPHA                      0x0200U            /*!<Clock Phase                          */
-#define  USART_CR2_CPOL                      0x0400U            /*!<Clock Polarity                       */
-#define  USART_CR2_CLKEN                     0x0800U            /*!<Clock Enable                         */
-
-#define  USART_CR2_STOP                      0x3000U            /*!<STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    0x1000U            /*!<Bit 0 */
-#define  USART_CR2_STOP_1                    0x2000U            /*!<Bit 1 */
-
-#define  USART_CR2_LINEN                     0x4000U            /*!<LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       0x0001U            /*!<Error Interrupt Enable      */
-#define  USART_CR3_IREN                      0x0002U            /*!<IrDA mode Enable            */
-#define  USART_CR3_IRLP                      0x0004U            /*!<IrDA Low-Power              */
-#define  USART_CR3_HDSEL                     0x0008U            /*!<Half-Duplex Selection       */
-#define  USART_CR3_NACK                      0x0010U            /*!<Smartcard NACK enable       */
-#define  USART_CR3_SCEN                      0x0020U            /*!<Smartcard mode enable       */
-#define  USART_CR3_DMAR                      0x0040U            /*!<DMA Enable Receiver         */
-#define  USART_CR3_DMAT                      0x0080U            /*!<DMA Enable Transmitter      */
-#define  USART_CR3_RTSE                      0x0100U            /*!<RTS Enable                  */
-#define  USART_CR3_CTSE                      0x0200U            /*!<CTS Enable                  */
-#define  USART_CR3_CTSIE                     0x0400U            /*!<CTS Interrupt Enable        */
-#define  USART_CR3_ONEBIT                    0x0800U            /*!<USART One bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      0x00FFU            /*!<PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    0x0001U            /*!<Bit 0 */
-#define  USART_GTPR_PSC_1                    0x0002U            /*!<Bit 1 */
-#define  USART_GTPR_PSC_2                    0x0004U            /*!<Bit 2 */
-#define  USART_GTPR_PSC_3                    0x0008U            /*!<Bit 3 */
-#define  USART_GTPR_PSC_4                    0x0010U            /*!<Bit 4 */
-#define  USART_GTPR_PSC_5                    0x0020U            /*!<Bit 5 */
-#define  USART_GTPR_PSC_6                    0x0040U            /*!<Bit 6 */
-#define  USART_GTPR_PSC_7                    0x0080U            /*!<Bit 7 */
-
-#define  USART_GTPR_GT                       0xFF00U            /*!<Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Window WATCHDOG                                 */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           0x7FU               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T_0                         0x01U               /*!<Bit 0 */
-#define  WWDG_CR_T_1                         0x02U               /*!<Bit 1 */
-#define  WWDG_CR_T_2                         0x04U               /*!<Bit 2 */
-#define  WWDG_CR_T_3                         0x08U               /*!<Bit 3 */
-#define  WWDG_CR_T_4                         0x10U               /*!<Bit 4 */
-#define  WWDG_CR_T_5                         0x20U               /*!<Bit 5 */
-#define  WWDG_CR_T_6                         0x40U               /*!<Bit 6 */
-/* Legacy defines */
-#define  WWDG_CR_T0                          WWDG_CR_T_0
-#define  WWDG_CR_T1                          WWDG_CR_T_1
-#define  WWDG_CR_T2                          WWDG_CR_T_2
-#define  WWDG_CR_T3                          WWDG_CR_T_3
-#define  WWDG_CR_T4                          WWDG_CR_T_4
-#define  WWDG_CR_T5                          WWDG_CR_T_5
-#define  WWDG_CR_T6                          WWDG_CR_T_6
-
-#define  WWDG_CR_WDGA                        0x80U               /*!<Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          0x007FU            /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W_0                        0x0001U            /*!<Bit 0 */
-#define  WWDG_CFR_W_1                        0x0002U            /*!<Bit 1 */
-#define  WWDG_CFR_W_2                        0x0004U            /*!<Bit 2 */
-#define  WWDG_CFR_W_3                        0x0008U            /*!<Bit 3 */
-#define  WWDG_CFR_W_4                        0x0010U            /*!<Bit 4 */
-#define  WWDG_CFR_W_5                        0x0020U            /*!<Bit 5 */
-#define  WWDG_CFR_W_6                        0x0040U            /*!<Bit 6 */
-/* Legacy defines */
-#define  WWDG_CFR_W0                         WWDG_CFR_W_0
-#define  WWDG_CFR_W1                         WWDG_CFR_W_1
-#define  WWDG_CFR_W2                         WWDG_CFR_W_2
-#define  WWDG_CFR_W3                         WWDG_CFR_W_3
-#define  WWDG_CFR_W4                         WWDG_CFR_W_4
-#define  WWDG_CFR_W5                         WWDG_CFR_W_5
-#define  WWDG_CFR_W6                         WWDG_CFR_W_6
-
-#define  WWDG_CFR_WDGTB                      0x0180U            /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB_0                    0x0080U            /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB_1                    0x0100U            /*!<Bit 1 */
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
-
-#define  WWDG_CFR_EWI                        0x0200U            /*!<Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        0x01U               /*!<Early Wakeup Interrupt Flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                DBG                                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
-#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
-
-/********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
-#define  DBGMCU_CR_DBG_STOP                  0x00000002U
-#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
-#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
-
-#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
-#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U/*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U/*!<Bit 1 */
-
-/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            0x00000001U
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            0x00000002U
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            0x00000004U
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            0x00000020U
-#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           0x00000040U
-#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           0x00000080U
-#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           0x00000100U
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
-#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
-/* Old IWDGSTOP bit definition, maintained for legacy purpose */
-#define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
-
-/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        0x00000001U
-#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        0x00000002U
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        0x00010000U
-#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       0x00020000U
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       0x00040000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                Ethernet MAC Registers bits definitions                     */
-/*                                                                            */
-/******************************************************************************/
-/* Bit definition for Ethernet MAC Control Register register */
-#define ETH_MACCR_WD      0x00800000U  /* Watchdog disable */
-#define ETH_MACCR_JD      0x00400000U  /* Jabber disable */
-#define ETH_MACCR_IFG     0x000E0000U  /* Inter-frame gap */
-#define ETH_MACCR_IFG_96Bit     0x00000000U  /* Minimum IFG between frames during transmission is 96Bit */
-  #define ETH_MACCR_IFG_88Bit     0x00020000U  /* Minimum IFG between frames during transmission is 88Bit */
-  #define ETH_MACCR_IFG_80Bit     0x00040000U  /* Minimum IFG between frames during transmission is 80Bit */
-  #define ETH_MACCR_IFG_72Bit     0x00060000U  /* Minimum IFG between frames during transmission is 72Bit */
-  #define ETH_MACCR_IFG_64Bit     0x00080000U  /* Minimum IFG between frames during transmission is 64Bit */        
-  #define ETH_MACCR_IFG_56Bit     0x000A0000U  /* Minimum IFG between frames during transmission is 56Bit */
-  #define ETH_MACCR_IFG_48Bit     0x000C0000U  /* Minimum IFG between frames during transmission is 48Bit */
-  #define ETH_MACCR_IFG_40Bit     0x000E0000U  /* Minimum IFG between frames during transmission is 40Bit */              
-#define ETH_MACCR_CSD     0x00010000U  /* Carrier sense disable (during transmission) */
-#define ETH_MACCR_FES     0x00004000U  /* Fast ethernet speed */
-#define ETH_MACCR_ROD     0x00002000U  /* Receive own disable */
-#define ETH_MACCR_LM      0x00001000U  /* loopback mode */
-#define ETH_MACCR_DM      0x00000800U  /* Duplex mode */
-#define ETH_MACCR_IPCO    0x00000400U  /* IP Checksum offload */
-#define ETH_MACCR_RD      0x00000200U  /* Retry disable */
-#define ETH_MACCR_APCS    0x00000080U  /* Automatic Pad/CRC stripping */
-#define ETH_MACCR_BL      0x00000060U  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
-                                                       a transmission attempt during retries after a collision: 0 =< r <2^k */
-  #define ETH_MACCR_BL_10    0x00000000U  /* k = min (n, 10) */
-  #define ETH_MACCR_BL_8     0x00000020U  /* k = min (n, 8) */
-  #define ETH_MACCR_BL_4     0x00000040U  /* k = min (n, 4) */
-  #define ETH_MACCR_BL_1     0x00000060U  /* k = min (n, 1) */ 
-#define ETH_MACCR_DC      0x00000010U  /* Defferal check */
-#define ETH_MACCR_TE      0x00000008U  /* Transmitter enable */
-#define ETH_MACCR_RE      0x00000004U  /* Receiver enable */
-
-/* Bit definition for Ethernet MAC Frame Filter Register */
-#define ETH_MACFFR_RA     0x80000000U  /* Receive all */ 
-#define ETH_MACFFR_HPF    0x00000400U  /* Hash or perfect filter */ 
-#define ETH_MACFFR_SAF    0x00000200U  /* Source address filter enable */ 
-#define ETH_MACFFR_SAIF   0x00000100U  /* SA inverse filtering */ 
-#define ETH_MACFFR_PCF    0x000000C0U  /* Pass control frames: 3 cases */
-  #define ETH_MACFFR_PCF_BlockAll                0x00000040U  /* MAC filters all control frames from reaching the application */
-  #define ETH_MACFFR_PCF_ForwardAll              0x00000080U  /* MAC forwards all control frames to application even if they fail the Address Filter */
-  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U  /* MAC forwards control frames that pass the Address Filter. */ 
-#define ETH_MACFFR_BFD    0x00000020U  /* Broadcast frame disable */ 
-#define ETH_MACFFR_PAM    0x00000010U  /* Pass all mutlicast */ 
-#define ETH_MACFFR_DAIF   0x00000008U  /* DA Inverse filtering */ 
-#define ETH_MACFFR_HM     0x00000004U  /* Hash multicast */ 
-#define ETH_MACFFR_HU     0x00000002U  /* Hash unicast */
-#define ETH_MACFFR_PM     0x00000001U  /* Promiscuous mode */
-
-/* Bit definition for Ethernet MAC Hash Table High Register */
-#define ETH_MACHTHR_HTH   0xFFFFFFFFU  /* Hash table high */
-
-/* Bit definition for Ethernet MAC Hash Table Low Register */
-#define ETH_MACHTLR_HTL   0xFFFFFFFFU  /* Hash table low */
-
-/* Bit definition for Ethernet MAC MII Address Register */
-#define ETH_MACMIIAR_PA   0x0000F800U  /* Physical layer address */ 
-#define ETH_MACMIIAR_MR   0x000007C0U  /* MII register in the selected PHY */ 
-#define ETH_MACMIIAR_CR   0x0000001CU  /* CR clock range: 6 cases */ 
-  #define ETH_MACMIIAR_CR_Div42   0x00000000U  /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
-  #define ETH_MACMIIAR_CR_Div62   0x00000004U  /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
-  #define ETH_MACMIIAR_CR_Div16   0x00000008U  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
-  #define ETH_MACMIIAR_CR_Div26   0x0000000CU  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
-  #define ETH_MACMIIAR_CR_Div102  0x00000010U  /* HCLK:150-168 MHz; MDC clock= HCLK/102 */  
-#define ETH_MACMIIAR_MW   0x00000002U  /* MII write */ 
-#define ETH_MACMIIAR_MB   0x00000001U  /* MII busy */ 
-  
-/* Bit definition for Ethernet MAC MII Data Register */
-#define ETH_MACMIIDR_MD   0x0000FFFFU  /* MII data: read/write data from/to PHY */
-
-/* Bit definition for Ethernet MAC Flow Control Register */
-#define ETH_MACFCR_PT     0xFFFF0000U  /* Pause time */
-#define ETH_MACFCR_ZQPD   0x00000080U  /* Zero-quanta pause disable */
-#define ETH_MACFCR_PLT    0x00000030U  /* Pause low threshold: 4 cases */
-  #define ETH_MACFCR_PLT_Minus4   0x00000000U  /* Pause time minus 4 slot times */
-  #define ETH_MACFCR_PLT_Minus28  0x00000010U  /* Pause time minus 28 slot times */
-  #define ETH_MACFCR_PLT_Minus144 0x00000020U  /* Pause time minus 144 slot times */
-  #define ETH_MACFCR_PLT_Minus256 0x00000030U  /* Pause time minus 256 slot times */      
-#define ETH_MACFCR_UPFD   0x00000008U  /* Unicast pause frame detect */
-#define ETH_MACFCR_RFCE   0x00000004U  /* Receive flow control enable */
-#define ETH_MACFCR_TFCE   0x00000002U  /* Transmit flow control enable */
-#define ETH_MACFCR_FCBBPA 0x00000001U  /* Flow control busy/backpressure activate */
-
-/* Bit definition for Ethernet MAC VLAN Tag Register */
-#define ETH_MACVLANTR_VLANTC 0x00010000U  /* 12-bit VLAN tag comparison */
-#define ETH_MACVLANTR_VLANTI 0x0000FFFFU  /* VLAN tag identifier (for receive frames) */
-
-/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ 
-#define ETH_MACRWUFFR_D   0xFFFFFFFFU  /* Wake-up frame filter register data */
-/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
-   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
-/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
-   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
-   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
-   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
-   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - 
-                              RSVD - Filter1 Command - RSVD - Filter0 Command
-   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
-   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
-   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
-
-/* Bit definition for Ethernet MAC PMT Control and Status Register */ 
-#define ETH_MACPMTCSR_WFFRPR 0x80000000U  /* Wake-Up Frame Filter Register Pointer Reset */
-#define ETH_MACPMTCSR_GU     0x00000200U  /* Global Unicast */
-#define ETH_MACPMTCSR_WFR    0x00000040U  /* Wake-Up Frame Received */
-#define ETH_MACPMTCSR_MPR    0x00000020U  /* Magic Packet Received */
-#define ETH_MACPMTCSR_WFE    0x00000004U  /* Wake-Up Frame Enable */
-#define ETH_MACPMTCSR_MPE    0x00000002U  /* Magic Packet Enable */
-#define ETH_MACPMTCSR_PD     0x00000001U  /* Power Down */
-
-/* Bit definition for Ethernet MAC Status Register */
-#define ETH_MACSR_TSTS      0x00000200U  /* Time stamp trigger status */
-#define ETH_MACSR_MMCTS     0x00000040U  /* MMC transmit status */
-#define ETH_MACSR_MMMCRS    0x00000020U  /* MMC receive status */
-#define ETH_MACSR_MMCS      0x00000010U  /* MMC status */
-#define ETH_MACSR_PMTS      0x00000008U  /* PMT status */
-
-/* Bit definition for Ethernet MAC Interrupt Mask Register */
-#define ETH_MACIMR_TSTIM     0x00000200U  /* Time stamp trigger interrupt mask */
-#define ETH_MACIMR_PMTIM     0x00000008U  /* PMT interrupt mask */
-
-/* Bit definition for Ethernet MAC Address0 High Register */
-#define ETH_MACA0HR_MACA0H   0x0000FFFFU  /* MAC address0 high */
-
-/* Bit definition for Ethernet MAC Address0 Low Register */
-#define ETH_MACA0LR_MACA0L   0xFFFFFFFFU  /* MAC address0 low */
-
-/* Bit definition for Ethernet MAC Address1 High Register */
-#define ETH_MACA1HR_AE       0x80000000U  /* Address enable */
-#define ETH_MACA1HR_SA       0x40000000U  /* Source address */
-#define ETH_MACA1HR_MBC      0x3F000000U  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
-  #define ETH_MACA1HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA1HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA1HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA1HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA1HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA1HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [7:0] */ 
-#define ETH_MACA1HR_MACA1H   0x0000FFFFU  /* MAC address1 high */
-
-/* Bit definition for Ethernet MAC Address1 Low Register */
-#define ETH_MACA1LR_MACA1L   0xFFFFFFFFU  /* MAC address1 low */
-
-/* Bit definition for Ethernet MAC Address2 High Register */
-#define ETH_MACA2HR_AE       0x80000000U  /* Address enable */
-#define ETH_MACA2HR_SA       0x40000000U  /* Source address */
-#define ETH_MACA2HR_MBC      0x3F000000U  /* Mask byte control */
-  #define ETH_MACA2HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA2HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA2HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA2HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA2HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA2HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA2HR_MACA2H   0x0000FFFFU  /* MAC address1 high */
-
-/* Bit definition for Ethernet MAC Address2 Low Register */
-#define ETH_MACA2LR_MACA2L   0xFFFFFFFFU  /* MAC address2 low */
-
-/* Bit definition for Ethernet MAC Address3 High Register */
-#define ETH_MACA3HR_AE       0x80000000U  /* Address enable */
-#define ETH_MACA3HR_SA       0x40000000U  /* Source address */
-#define ETH_MACA3HR_MBC      0x3F000000U  /* Mask byte control */
-  #define ETH_MACA3HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA3HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA3HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA3HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA3HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA3HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA3HR_MACA3H   0x0000FFFFU  /* MAC address3 high */
-
-/* Bit definition for Ethernet MAC Address3 Low Register */
-#define ETH_MACA3LR_MACA3L   0xFFFFFFFFU  /* MAC address3 low */
-
-/******************************************************************************/
-/*                Ethernet MMC Registers bits definition                      */
-/******************************************************************************/
-
-/* Bit definition for Ethernet MMC Contol Register */
-#define ETH_MMCCR_MCFHP      0x00000020U  /* MMC counter Full-Half preset */
-#define ETH_MMCCR_MCP        0x00000010U  /* MMC counter preset */
-#define ETH_MMCCR_MCF        0x00000008U  /* MMC Counter Freeze */
-#define ETH_MMCCR_ROR        0x00000004U  /* Reset on Read */
-#define ETH_MMCCR_CSR        0x00000002U  /* Counter Stop Rollover */
-#define ETH_MMCCR_CR         0x00000001U  /* Counters Reset */
-
-/* Bit definition for Ethernet MMC Receive Interrupt Register */
-#define ETH_MMCRIR_RGUFS     0x00020000U  /* Set when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIR_RFAES     0x00000040U  /* Set when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIR_RFCES     0x00000020U  /* Set when Rx crc error counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmit Interrupt Register */
-#define ETH_MMCTIR_TGFS      0x00200000U  /* Set when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFMSCS   0x00008000U  /* Set when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFSCS    0x00004000U  /* Set when Tx good single col counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
-#define ETH_MMCRIMR_RGUFM    0x00020000U  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFAEM    0x00000040U  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFCEM    0x00000020U  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
-#define ETH_MMCTIMR_TGFM     0x00200000U  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFMSCM  0x00008000U  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFSCM   0x00004000U  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
-#define ETH_MMCTGFSCCR_TGFSCC     0xFFFFFFFFU  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
-#define ETH_MMCTGFMSCCR_TGFMSCC   0xFFFFFFFFU  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
-#define ETH_MMCTGFCR_TGFC    0xFFFFFFFFU  /* Number of good frames transmitted. */
-
-/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
-#define ETH_MMCRFCECR_RFCEC  0xFFFFFFFFU  /* Number of frames received with CRC error. */
-
-/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
-#define ETH_MMCRFAECR_RFAEC  0xFFFFFFFFU  /* Number of frames received with alignment (dribble) error */
-
-/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
-#define ETH_MMCRGUFCR_RGUFC  0xFFFFFFFFU  /* Number of good unicast frames received. */
-
-/******************************************************************************/
-/*               Ethernet PTP Registers bits definition                       */
-/******************************************************************************/
-
-/* Bit definition for Ethernet PTP Time Stamp Contol Register */
-#define ETH_PTPTSCR_TSCNT       0x00030000U  /* Time stamp clock node type */
-#define ETH_PTPTSSR_TSSMRME     0x00008000U  /* Time stamp snapshot for message relevant to master enable */
-#define ETH_PTPTSSR_TSSEME      0x00004000U  /* Time stamp snapshot for event message enable */
-#define ETH_PTPTSSR_TSSIPV4FE   0x00002000U  /* Time stamp snapshot for IPv4 frames enable */
-#define ETH_PTPTSSR_TSSIPV6FE   0x00001000U  /* Time stamp snapshot for IPv6 frames enable */
-#define ETH_PTPTSSR_TSSPTPOEFE  0x00000800U  /* Time stamp snapshot for PTP over ethernet frames enable */
-#define ETH_PTPTSSR_TSPTPPSV2E  0x00000400U  /* Time stamp PTP packet snooping for version2 format enable */
-#define ETH_PTPTSSR_TSSSR       0x00000200U  /* Time stamp Sub-seconds rollover */
-#define ETH_PTPTSSR_TSSARFE     0x00000100U  /* Time stamp snapshot for all received frames enable */
-
-#define ETH_PTPTSCR_TSARU    0x00000020U  /* Addend register update */
-#define ETH_PTPTSCR_TSITE    0x00000010U  /* Time stamp interrupt trigger enable */
-#define ETH_PTPTSCR_TSSTU    0x00000008U  /* Time stamp update */
-#define ETH_PTPTSCR_TSSTI    0x00000004U  /* Time stamp initialize */
-#define ETH_PTPTSCR_TSFCU    0x00000002U  /* Time stamp fine or coarse update */
-#define ETH_PTPTSCR_TSE      0x00000001U  /* Time stamp enable */
-
-/* Bit definition for Ethernet PTP Sub-Second Increment Register */
-#define ETH_PTPSSIR_STSSI    0x000000FFU  /* System time Sub-second increment value */
-
-/* Bit definition for Ethernet PTP Time Stamp High Register */
-#define ETH_PTPTSHR_STS      0xFFFFFFFFU  /* System Time second */
-
-/* Bit definition for Ethernet PTP Time Stamp Low Register */
-#define ETH_PTPTSLR_STPNS    0x80000000U  /* System Time Positive or negative time */
-#define ETH_PTPTSLR_STSS     0x7FFFFFFFU  /* System Time sub-seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp High Update Register */
-#define ETH_PTPTSHUR_TSUS    0xFFFFFFFFU  /* Time stamp update seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
-#define ETH_PTPTSLUR_TSUPNS  0x80000000U  /* Time stamp update Positive or negative time */
-#define ETH_PTPTSLUR_TSUSS   0x7FFFFFFFU  /* Time stamp update sub-seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp Addend Register */
-#define ETH_PTPTSAR_TSA      0xFFFFFFFFU  /* Time stamp addend */
-
-/* Bit definition for Ethernet PTP Target Time High Register */
-#define ETH_PTPTTHR_TTSH     0xFFFFFFFFU  /* Target time stamp high */
-
-/* Bit definition for Ethernet PTP Target Time Low Register */
-#define ETH_PTPTTLR_TTSL     0xFFFFFFFFU  /* Target time stamp low */
-
-/* Bit definition for Ethernet PTP Time Stamp Status Register */
-#define ETH_PTPTSSR_TSTTR    0x00000020U  /* Time stamp target time reached */
-#define ETH_PTPTSSR_TSSO     0x00000010U  /* Time stamp seconds overflow */
-
-/******************************************************************************/
-/*                 Ethernet DMA Registers bits definition                     */
-/******************************************************************************/
-
-/* Bit definition for Ethernet DMA Bus Mode Register */
-#define ETH_DMABMR_AAB       0x02000000U  /* Address-Aligned beats */
-#define ETH_DMABMR_FPM        0x01000000U  /* 4xPBL mode */
-#define ETH_DMABMR_USP       0x00800000U  /* Use separate PBL */
-#define ETH_DMABMR_RDP       0x007E0000U  /* RxDMA PBL */
-  #define ETH_DMABMR_RDP_1Beat    0x00020000U  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
-  #define ETH_DMABMR_RDP_2Beat    0x00040000U  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
-  #define ETH_DMABMR_RDP_4Beat    0x00080000U  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-  #define ETH_DMABMR_RDP_8Beat    0x00100000U  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-  #define ETH_DMABMR_RDP_16Beat   0x00200000U  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-  #define ETH_DMABMR_RDP_32Beat   0x00400000U  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */                
-  #define ETH_DMABMR_RDP_4xPBL_4Beat   0x01020000U  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-  #define ETH_DMABMR_RDP_4xPBL_8Beat   0x01040000U  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-  #define ETH_DMABMR_RDP_4xPBL_16Beat  0x01080000U  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-  #define ETH_DMABMR_RDP_4xPBL_32Beat  0x01100000U  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
-  #define ETH_DMABMR_RDP_4xPBL_64Beat  0x01200000U  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
-  #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */  
-#define ETH_DMABMR_FB        0x00010000U  /* Fixed Burst */
-#define ETH_DMABMR_RTPR      0x0000C000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_1_1     0x00000000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_2_1     0x00004000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_3_1     0x00008000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_4_1     0x0000C000U  /* Rx Tx priority ratio */  
-#define ETH_DMABMR_PBL    0x00003F00U  /* Programmable burst length */
-  #define ETH_DMABMR_PBL_1Beat    0x00000100U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
-  #define ETH_DMABMR_PBL_2Beat    0x00000200U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
-  #define ETH_DMABMR_PBL_4Beat    0x00000400U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-  #define ETH_DMABMR_PBL_8Beat    0x00000800U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-  #define ETH_DMABMR_PBL_16Beat   0x00001000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-  #define ETH_DMABMR_PBL_32Beat   0x00002000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
-  #define ETH_DMABMR_PBL_4xPBL_4Beat   0x01000100U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-  #define ETH_DMABMR_PBL_4xPBL_8Beat   0x01000200U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-  #define ETH_DMABMR_PBL_4xPBL_16Beat  0x01000400U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-  #define ETH_DMABMR_PBL_4xPBL_32Beat  0x01000800U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
-  #define ETH_DMABMR_PBL_4xPBL_64Beat  0x01001000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
-  #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
-#define ETH_DMABMR_EDE       0x00000080U  /* Enhanced Descriptor Enable */
-#define ETH_DMABMR_DSL       0x0000007CU  /* Descriptor Skip Length */
-#define ETH_DMABMR_DA        0x00000002U  /* DMA arbitration scheme */
-#define ETH_DMABMR_SR        0x00000001U  /* Software reset */
-
-/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
-#define ETH_DMATPDR_TPD      0xFFFFFFFFU  /* Transmit poll demand */
-
-/* Bit definition for Ethernet DMA Receive Poll Demand Register */
-#define ETH_DMARPDR_RPD      0xFFFFFFFFU  /* Receive poll demand  */
-
-/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
-#define ETH_DMARDLAR_SRL     0xFFFFFFFFU  /* Start of receive list */
-
-/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
-#define ETH_DMATDLAR_STL     0xFFFFFFFFU  /* Start of transmit list */
-
-/* Bit definition for Ethernet DMA Status Register */
-#define ETH_DMASR_TSTS       0x20000000U  /* Time-stamp trigger status */
-#define ETH_DMASR_PMTS       0x10000000U  /* PMT status */
-#define ETH_DMASR_MMCS       0x08000000U  /* MMC status */
-#define ETH_DMASR_EBS        0x03800000U  /* Error bits status */
-  /* combination with EBS[2:0] for GetFlagStatus function */
-  #define ETH_DMASR_EBS_DescAccess      0x02000000U  /* Error bits 0-data buffer, 1-desc. access */
-  #define ETH_DMASR_EBS_ReadTransf      0x01000000U  /* Error bits 0-write trnsf, 1-read transfr */
-  #define ETH_DMASR_EBS_DataTransfTx    0x00800000U  /* Error bits 0-Rx DMA, 1-Tx DMA */
-#define ETH_DMASR_TPS         0x00700000U  /* Transmit process state */
-  #define ETH_DMASR_TPS_Stopped         0x00000000U  /* Stopped - Reset or Stop Tx Command issued  */
-  #define ETH_DMASR_TPS_Fetching        0x00100000U  /* Running - fetching the Tx descriptor */
-  #define ETH_DMASR_TPS_Waiting         0x00200000U  /* Running - waiting for status */
-  #define ETH_DMASR_TPS_Reading         0x00300000U  /* Running - reading the data from host memory */
-  #define ETH_DMASR_TPS_Suspended       0x00600000U  /* Suspended - Tx Descriptor unavailabe */
-  #define ETH_DMASR_TPS_Closing         0x00700000U  /* Running - closing Rx descriptor */
-#define ETH_DMASR_RPS         0x000E0000U  /* Receive process state */
-  #define ETH_DMASR_RPS_Stopped         0x00000000U  /* Stopped - Reset or Stop Rx Command issued */
-  #define ETH_DMASR_RPS_Fetching        0x00020000U  /* Running - fetching the Rx descriptor */
-  #define ETH_DMASR_RPS_Waiting         0x00060000U  /* Running - waiting for packet */
-  #define ETH_DMASR_RPS_Suspended       0x00080000U  /* Suspended - Rx Descriptor unavailable */
-  #define ETH_DMASR_RPS_Closing         0x000A0000U  /* Running - closing descriptor */
-  #define ETH_DMASR_RPS_Queuing         0x000E0000U  /* Running - queuing the recieve frame into host memory */
-#define ETH_DMASR_NIS        0x00010000U  /* Normal interrupt summary */
-#define ETH_DMASR_AIS        0x00008000U  /* Abnormal interrupt summary */
-#define ETH_DMASR_ERS        0x00004000U  /* Early receive status */
-#define ETH_DMASR_FBES       0x00002000U  /* Fatal bus error status */
-#define ETH_DMASR_ETS        0x00000400U  /* Early transmit status */
-#define ETH_DMASR_RWTS       0x00000200U  /* Receive watchdog timeout status */
-#define ETH_DMASR_RPSS       0x00000100U  /* Receive process stopped status */
-#define ETH_DMASR_RBUS       0x00000080U  /* Receive buffer unavailable status */
-#define ETH_DMASR_RS         0x00000040U  /* Receive status */
-#define ETH_DMASR_TUS        0x00000020U  /* Transmit underflow status */
-#define ETH_DMASR_ROS        0x00000010U  /* Receive overflow status */
-#define ETH_DMASR_TJTS       0x00000008U  /* Transmit jabber timeout status */
-#define ETH_DMASR_TBUS       0x00000004U  /* Transmit buffer unavailable status */
-#define ETH_DMASR_TPSS       0x00000002U  /* Transmit process stopped status */
-#define ETH_DMASR_TS         0x00000001U  /* Transmit status */
-
-/* Bit definition for Ethernet DMA Operation Mode Register */
-#define ETH_DMAOMR_DTCEFD    0x04000000U  /* Disable Dropping of TCP/IP checksum error frames */
-#define ETH_DMAOMR_RSF       0x02000000U  /* Receive store and forward */
-#define ETH_DMAOMR_DFRF      0x01000000U  /* Disable flushing of received frames */
-#define ETH_DMAOMR_TSF       0x00200000U  /* Transmit store and forward */
-#define ETH_DMAOMR_FTF       0x00100000U  /* Flush transmit FIFO */
-#define ETH_DMAOMR_TTC       0x0001C000U  /* Transmit threshold control */
-  #define ETH_DMAOMR_TTC_64Bytes       0x00000000U  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
-  #define ETH_DMAOMR_TTC_128Bytes      0x00004000U  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
-  #define ETH_DMAOMR_TTC_192Bytes      0x00008000U  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
-  #define ETH_DMAOMR_TTC_256Bytes      0x0000C000U  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
-  #define ETH_DMAOMR_TTC_40Bytes       0x00010000U  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
-  #define ETH_DMAOMR_TTC_32Bytes       0x00014000U  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
-  #define ETH_DMAOMR_TTC_24Bytes       0x00018000U  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
-  #define ETH_DMAOMR_TTC_16Bytes       0x0001C000U  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
-#define ETH_DMAOMR_ST        0x00002000U  /* Start/stop transmission command */
-#define ETH_DMAOMR_FEF       0x00000080U  /* Forward error frames */
-#define ETH_DMAOMR_FUGF      0x00000040U  /* Forward undersized good frames */
-#define ETH_DMAOMR_RTC       0x00000018U  /* receive threshold control */
-  #define ETH_DMAOMR_RTC_64Bytes       0x00000000U  /* threshold level of the MTL Receive FIFO is 64 Bytes */
-  #define ETH_DMAOMR_RTC_32Bytes       0x00000008U  /* threshold level of the MTL Receive FIFO is 32 Bytes */
-  #define ETH_DMAOMR_RTC_96Bytes       0x00000010U  /* threshold level of the MTL Receive FIFO is 96 Bytes */
-  #define ETH_DMAOMR_RTC_128Bytes      0x00000018U  /* threshold level of the MTL Receive FIFO is 128 Bytes */
-#define ETH_DMAOMR_OSF       0x00000004U  /* operate on second frame */
-#define ETH_DMAOMR_SR        0x00000002U  /* Start/stop receive */
-
-/* Bit definition for Ethernet DMA Interrupt Enable Register */
-#define ETH_DMAIER_NISE      0x00010000U  /* Normal interrupt summary enable */
-#define ETH_DMAIER_AISE      0x00008000U  /* Abnormal interrupt summary enable */
-#define ETH_DMAIER_ERIE      0x00004000U  /* Early receive interrupt enable */
-#define ETH_DMAIER_FBEIE     0x00002000U  /* Fatal bus error interrupt enable */
-#define ETH_DMAIER_ETIE      0x00000400U  /* Early transmit interrupt enable */
-#define ETH_DMAIER_RWTIE     0x00000200U  /* Receive watchdog timeout interrupt enable */
-#define ETH_DMAIER_RPSIE     0x00000100U  /* Receive process stopped interrupt enable */
-#define ETH_DMAIER_RBUIE     0x00000080U  /* Receive buffer unavailable interrupt enable */
-#define ETH_DMAIER_RIE       0x00000040U  /* Receive interrupt enable */
-#define ETH_DMAIER_TUIE      0x00000020U  /* Transmit Underflow interrupt enable */
-#define ETH_DMAIER_ROIE      0x00000010U  /* Receive Overflow interrupt enable */
-#define ETH_DMAIER_TJTIE     0x00000008U  /* Transmit jabber timeout interrupt enable */
-#define ETH_DMAIER_TBUIE     0x00000004U  /* Transmit buffer unavailable interrupt enable */
-#define ETH_DMAIER_TPSIE     0x00000002U  /* Transmit process stopped interrupt enable */
-#define ETH_DMAIER_TIE       0x00000001U  /* Transmit interrupt enable */
-
-/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
-#define ETH_DMAMFBOCR_OFOC   0x10000000U  /* Overflow bit for FIFO overflow counter */
-#define ETH_DMAMFBOCR_MFA    0x0FFE0000U  /* Number of frames missed by the application */
-#define ETH_DMAMFBOCR_OMFC   0x00010000U  /* Overflow bit for missed frame counter */
-#define ETH_DMAMFBOCR_MFC    0x0000FFFFU  /* Number of frames missed by the controller */
-
-/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
-#define ETH_DMACHTDR_HTDAP   0xFFFFFFFFU  /* Host transmit descriptor address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
-#define ETH_DMACHRDR_HRDAP   0xFFFFFFFFU  /* Host receive descriptor address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
-#define ETH_DMACHTBAR_HTBAP  0xFFFFFFFFU  /* Host transmit buffer address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
-#define ETH_DMACHRBAR_HRBAP  0xFFFFFFFFU  /* Host receive buffer address pointer */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                       USB_OTG                              */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/
-#define USB_OTG_GOTGCTL_SRQSCS                  0x00000001U         /*!< Session request success */
-#define USB_OTG_GOTGCTL_SRQ                     0x00000002U         /*!< Session request */
-#define USB_OTG_GOTGCTL_VBVALOEN                0x00000004U         /*!< VBUS valid override enable */
-#define USB_OTG_GOTGCTL_VBVALOVAL               0x00000008U         /*!< VBUS valid override value */
-#define USB_OTG_GOTGCTL_AVALOEN                 0x00000010U         /*!< A-peripheral session valid override enable */
-#define USB_OTG_GOTGCTL_AVALOVAL                0x00000020U         /*!< A-peripheral session valid override value */
-#define USB_OTG_GOTGCTL_BVALOEN                 0x00000040U         /*!< B-peripheral session valid override enable */
-#define USB_OTG_GOTGCTL_BVALOVAL                0x00000080U         /*!< B-peripheral session valid override value  */
-#define USB_OTG_GOTGCTL_HNGSCS                  0x00000100U         /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_HNPRQ                   0x00000200U         /*!< HNP request */
-#define USB_OTG_GOTGCTL_HSHNPEN                 0x00000400U         /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_DHNPEN                  0x00000800U         /*!< Device HNP enabled */
-#define USB_OTG_GOTGCTL_EHEN                    0x00001000U         /*!< Embedded host enable */
-#define USB_OTG_GOTGCTL_CIDSTS                  0x00010000U         /*!< Connector ID status */
-#define USB_OTG_GOTGCTL_DBCT                    0x00020000U         /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD                   0x00040000U         /*!< A-session valid  */
-#define USB_OTG_GOTGCTL_BSESVLD                 0x00080000U         /*!< B-session valid */
-#define USB_OTG_GOTGCTL_OTGVER                  0x00100000U         /*!< OTG version  */
-
-/********************  Bit definition forUSB_OTG_HCFG register  ********************/
-
-#define USB_OTG_HCFG_FSLSPCS                 0x00000003U            /*!< FS/LS PHY clock select  */
-#define USB_OTG_HCFG_FSLSPCS_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCFG_FSLSPCS_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCFG_FSLSS                   0x00000004U            /*!< FS- and LS-only support */
-
-/********************  Bit definition forUSB_OTG_DCFG register  ********************/
-
-#define USB_OTG_DCFG_DSPD                    0x00000003U            /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                  0x00000001U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DSPD_1                  0x00000002U            /*!<Bit 1 */
-#define USB_OTG_DCFG_NZLSOHSK                0x00000004U            /*!< Nonzero-length status OUT handshake */
-
-#define USB_OTG_DCFG_DAD                     0x000007F0U            /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                   0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DAD_1                   0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCFG_DAD_2                   0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCFG_DAD_3                   0x00000080U            /*!<Bit 3 */
-#define USB_OTG_DCFG_DAD_4                   0x00000100U            /*!<Bit 4 */
-#define USB_OTG_DCFG_DAD_5                   0x00000200U            /*!<Bit 5 */
-#define USB_OTG_DCFG_DAD_6                   0x00000400U            /*!<Bit 6 */
-
-#define USB_OTG_DCFG_PFIVL                   0x00001800U            /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PFIVL_1                 0x00001000U            /*!<Bit 1 */
-
-#define USB_OTG_DCFG_PERSCHIVL               0x03000000U            /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0             0x01000000U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PERSCHIVL_1             0x02000000U            /*!<Bit 1 */
-
-/********************  Bit definition forUSB_OTG_PCGCR register  ********************/
-#define USB_OTG_PCGCR_STPPCLK                 0x00000001U            /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK                0x00000002U            /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP                 0x00000010U            /*!< PHY suspended */
-
-/********************  Bit definition forUSB_OTG_GOTGINT register  ********************/
-#define USB_OTG_GOTGINT_SEDET                   0x00000004U            /*!< Session end detected                   */
-#define USB_OTG_GOTGINT_SRSSCHG                 0x00000100U            /*!< Session request success status change  */
-#define USB_OTG_GOTGINT_HNSSCHG                 0x00000200U            /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET                  0x00020000U            /*!< Host negotiation detected              */
-#define USB_OTG_GOTGINT_ADTOCHG                 0x00040000U            /*!< A-device timeout change                */
-#define USB_OTG_GOTGINT_DBCDNE                  0x00080000U            /*!< Debounce done                          */
-#define USB_OTG_GOTGINT_IDCHNG                  0x00100000U            /*!< Change in ID pin input value           */
-
-/********************  Bit definition forUSB_OTG_DCTL register  ********************/
-#define USB_OTG_DCTL_RWUSIG                  0x00000001U            /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS                    0x00000002U            /*!< Soft disconnect         */
-#define USB_OTG_DCTL_GINSTS                  0x00000004U            /*!< Global IN NAK status    */
-#define USB_OTG_DCTL_GONSTS                  0x00000008U            /*!< Global OUT NAK status   */
-
-#define USB_OTG_DCTL_TCTL                    0x00000070U            /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                  0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCTL_TCTL_1                  0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCTL_TCTL_2                  0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCTL_SGINAK                  0x00000080U            /*!< Set global IN NAK         */
-#define USB_OTG_DCTL_CGINAK                  0x00000100U            /*!< Clear global IN NAK       */
-#define USB_OTG_DCTL_SGONAK                  0x00000200U            /*!< Set global OUT NAK        */
-#define USB_OTG_DCTL_CGONAK                  0x00000400U            /*!< Clear global OUT NAK      */
-#define USB_OTG_DCTL_POPRGDNE                0x00000800U            /*!< Power-on programming done */
-
-/********************  Bit definition forUSB_OTG_HFIR register  ********************/
-#define USB_OTG_HFIR_FRIVL                   0x0000FFFFU            /*!< Frame interval */
-
-/********************  Bit definition forUSB_OTG_HFNUM register  ********************/
-#define USB_OTG_HFNUM_FRNUM                   0x0000FFFFU            /*!< Frame number         */
-#define USB_OTG_HFNUM_FTREM                   0xFFFF0000U            /*!< Frame time remaining */
-
-/********************  Bit definition forUSB_OTG_DSTS register  ********************/
-#define USB_OTG_DSTS_SUSPSTS                 0x00000001U            /*!< Suspend status   */
-
-#define USB_OTG_DSTS_ENUMSPD                 0x00000006U            /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_DSTS_ENUMSPD_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_DSTS_EERR                    0x00000008U            /*!< Erratic error     */
-#define USB_OTG_DSTS_FNSOF                   0x003FFF00U            /*!< Frame number of the received SOF */
-
-/********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/
-#define USB_OTG_GAHBCFG_GINT                    0x00000001U            /*!< Global interrupt mask */
-#define USB_OTG_GAHBCFG_HBSTLEN                 0x0000001EU            /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_GAHBCFG_HBSTLEN_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_GAHBCFG_HBSTLEN_2               0x00000008U            /*!<Bit 2 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3               0x00000010U            /*!<Bit 3 */
-#define USB_OTG_GAHBCFG_DMAEN                   0x00000020U            /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL                 0x00000080U            /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL                0x00000100U            /*!< Periodic TxFIFO empty level */
-
-/********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/
-
-#define USB_OTG_GUSBCFG_TOCAL                   0x00000007U            /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TOCAL_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TOCAL_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_PHYSEL                  0x00000040U            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP                  0x00000100U            /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP                  0x00000200U            /*!< HNP-capable */
-#define USB_OTG_GUSBCFG_TRDT                    0x00003C00U            /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                  0x00000400U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TRDT_1                  0x00000800U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TRDT_2                  0x00001000U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_TRDT_3                  0x00002000U            /*!<Bit 3 */
-#define USB_OTG_GUSBCFG_PHYLPCS                 0x00008000U            /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS                0x00020000U            /*!< ULPI FS/LS select               */
-#define USB_OTG_GUSBCFG_ULPIAR                  0x00040000U            /*!< ULPI Auto-resume                */
-#define USB_OTG_GUSBCFG_ULPICSM                 0x00080000U            /*!< ULPI Clock SuspendM             */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD              0x00100000U            /*!< ULPI External VBUS Drive        */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI              0x00200000U            /*!< ULPI external VBUS indicator    */
-#define USB_OTG_GUSBCFG_TSDPS                   0x00400000U            /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI                    0x00800000U            /*!< Indicator complement            */
-#define USB_OTG_GUSBCFG_PTCI                    0x01000000U            /*!< Indicator pass through          */
-#define USB_OTG_GUSBCFG_ULPIIPD                 0x02000000U            /*!< ULPI interface protect disable  */
-#define USB_OTG_GUSBCFG_FHMOD                   0x20000000U            /*!< Forced host mode                */
-#define USB_OTG_GUSBCFG_FDMOD                   0x40000000U            /*!< Forced peripheral mode          */
-#define USB_OTG_GUSBCFG_CTXPKT                  0x80000000U            /*!< Corrupt Tx packet               */
-
-/********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
-#define USB_OTG_GRSTCTL_CSRST                   0x00000001U            /*!< Core soft reset          */
-#define USB_OTG_GRSTCTL_HSRST                   0x00000002U            /*!< HCLK soft reset          */
-#define USB_OTG_GRSTCTL_FCRST                   0x00000004U            /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH                 0x00000010U            /*!< RxFIFO flush             */
-#define USB_OTG_GRSTCTL_TXFFLSH                 0x00000020U            /*!< TxFIFO flush             */
-#define USB_OTG_GRSTCTL_TXFNUM                  0x000007C0U            /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                0x00000040U            /*!<Bit 0 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                0x00000080U            /*!<Bit 1 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                0x00000100U            /*!<Bit 2 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                0x00000200U            /*!<Bit 3 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                0x00000400U            /*!<Bit 4 */
-#define USB_OTG_GRSTCTL_DMAREQ                  0x40000000U            /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL                  0x80000000U            /*!< AHB master idle */
-
-/********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/
-#define USB_OTG_DIEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask                 */
-#define USB_OTG_DIEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask                  */
-#define USB_OTG_DIEPMSK_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask          */
-#define USB_OTG_DIEPMSK_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask           */
-#define USB_OTG_DIEPMSK_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask                    */
-#define USB_OTG_DIEPMSK_TXFURM                  0x00000100U            /*!< FIFO underrun mask                                */
-#define USB_OTG_DIEPMSK_BIM                     0x00000200U            /*!< BNA interrupt mask                                */
-
-/********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/
-#define USB_OTG_HPTXSTS_PTXFSAVL                0x0000FFFFU            /*!< Periodic transmit data FIFO space available     */
-#define USB_OTG_HPTXSTS_PTXQSAV                 0x00FF0000U            /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0               0x00010000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1               0x00020000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2               0x00040000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3               0x00080000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4               0x00100000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5               0x00200000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6               0x00400000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7               0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_HPTXSTS_PTXQTOP                 0xFF000000U            /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0               0x01000000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1               0x02000000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2               0x04000000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3               0x08000000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4               0x10000000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5               0x20000000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6               0x40000000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7               0x80000000U            /*!<Bit 7 */
-
-/********************  Bit definition forUSB_OTG_HAINT register  ********************/
-#define USB_OTG_HAINT_HAINT                   0x0000FFFFU            /*!< Channel interrupts */
-
-/********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/
-#define USB_OTG_DOEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask               */
-#define USB_OTG_DOEPMSK_STUPM                   0x00000008U            /*!< SETUP phase done mask                          */
-#define USB_OTG_DOEPMSK_OTEPDM                  0x00000010U            /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_OTEPSPRM                0x00000020U            /*!< Status Phase Received mask                     */
-#define USB_OTG_DOEPMSK_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received mask */
-#define USB_OTG_DOEPMSK_OPEM                    0x00000100U            /*!< OUT packet error mask                          */
-#define USB_OTG_DOEPMSK_BOIM                    0x00000200U            /*!< BNA interrupt mask                             */
-
-/********************  Bit definition forUSB_OTG_GINTSTS register  ********************/
-#define USB_OTG_GINTSTS_CMOD                    0x00000001U            /*!< Current mode of operation                      */
-#define USB_OTG_GINTSTS_MMIS                    0x00000002U            /*!< Mode mismatch interrupt                        */
-#define USB_OTG_GINTSTS_OTGINT                  0x00000004U            /*!< OTG interrupt                                  */
-#define USB_OTG_GINTSTS_SOF                     0x00000008U            /*!< Start of frame                                 */
-#define USB_OTG_GINTSTS_RXFLVL                  0x00000010U            /*!< RxFIFO nonempty                                */
-#define USB_OTG_GINTSTS_NPTXFE                  0x00000020U            /*!< Nonperiodic TxFIFO empty                       */
-#define USB_OTG_GINTSTS_GINAKEFF                0x00000040U            /*!< Global IN nonperiodic NAK effective            */
-#define USB_OTG_GINTSTS_BOUTNAKEFF              0x00000080U            /*!< Global OUT NAK effective                       */
-#define USB_OTG_GINTSTS_ESUSP                   0x00000400U            /*!< Early suspend                                  */
-#define USB_OTG_GINTSTS_USBSUSP                 0x00000800U            /*!< USB suspend                                    */
-#define USB_OTG_GINTSTS_USBRST                  0x00001000U            /*!< USB reset                                      */
-#define USB_OTG_GINTSTS_ENUMDNE                 0x00002000U            /*!< Enumeration done                               */
-#define USB_OTG_GINTSTS_ISOODRP                 0x00004000U            /*!< Isochronous OUT packet dropped interrupt       */
-#define USB_OTG_GINTSTS_EOPF                    0x00008000U            /*!< End of periodic frame interrupt                */
-#define USB_OTG_GINTSTS_IEPINT                  0x00040000U            /*!< IN endpoint interrupt                          */
-#define USB_OTG_GINTSTS_OEPINT                  0x00080000U            /*!< OUT endpoint interrupt                         */
-#define USB_OTG_GINTSTS_IISOIXFR                0x00100000U            /*!< Incomplete isochronous IN transfer             */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       0x00200000U            /*!< Incomplete periodic transfer                   */
-#define USB_OTG_GINTSTS_DATAFSUSP               0x00400000U            /*!< Data fetch suspended                           */
-#define USB_OTG_GINTSTS_RSTDET                  0x00800000U            /*!< Reset detected interrupt                       */
-#define USB_OTG_GINTSTS_HPRTINT                 0x01000000U            /*!< Host port interrupt                            */
-#define USB_OTG_GINTSTS_HCINT                   0x02000000U            /*!< Host channels interrupt                        */
-#define USB_OTG_GINTSTS_PTXFE                   0x04000000U            /*!< Periodic TxFIFO empty                          */
-#define USB_OTG_GINTSTS_LPMINT                  0x08000000U            /*!< LPM interrupt                                  */
-#define USB_OTG_GINTSTS_CIDSCHG                 0x10000000U            /*!< Connector ID status change                     */
-#define USB_OTG_GINTSTS_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt                  */
-#define USB_OTG_GINTSTS_SRQINT                  0x40000000U            /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT                  0x80000000U            /*!< Resume/remote wakeup detected interrupt        */
-
-/********************  Bit definition forUSB_OTG_GINTMSK register  ********************/
-#define USB_OTG_GINTMSK_MMISM                   0x00000002U            /*!< Mode mismatch interrupt mask                        */
-#define USB_OTG_GINTMSK_OTGINT                  0x00000004U            /*!< OTG interrupt mask                                  */
-#define USB_OTG_GINTMSK_SOFM                    0x00000008U            /*!< Start of frame mask                                 */
-#define USB_OTG_GINTMSK_RXFLVLM                 0x00000010U            /*!< Receive FIFO nonempty mask                          */
-#define USB_OTG_GINTMSK_NPTXFEM                 0x00000020U            /*!< Nonperiodic TxFIFO empty mask                       */
-#define USB_OTG_GINTMSK_GINAKEFFM               0x00000040U            /*!< Global nonperiodic IN NAK effective mask            */
-#define USB_OTG_GINTMSK_GONAKEFFM               0x00000080U            /*!< Global OUT NAK effective mask                       */
-#define USB_OTG_GINTMSK_ESUSPM                  0x00000400U            /*!< Early suspend mask                                  */
-#define USB_OTG_GINTMSK_USBSUSPM                0x00000800U            /*!< USB suspend mask                                    */
-#define USB_OTG_GINTMSK_USBRST                  0x00001000U            /*!< USB reset mask                                      */
-#define USB_OTG_GINTMSK_ENUMDNEM                0x00002000U            /*!< Enumeration done mask                               */
-#define USB_OTG_GINTMSK_ISOODRPM                0x00004000U            /*!< Isochronous OUT packet dropped interrupt mask       */
-#define USB_OTG_GINTMSK_EOPFM                   0x00008000U            /*!< End of periodic frame interrupt mask                */
-#define USB_OTG_GINTMSK_EPMISM                  0x00020000U            /*!< Endpoint mismatch interrupt mask                    */
-#define USB_OTG_GINTMSK_IEPINT                  0x00040000U            /*!< IN endpoints interrupt mask                         */
-#define USB_OTG_GINTMSK_OEPINT                  0x00080000U            /*!< OUT endpoints interrupt mask                        */
-#define USB_OTG_GINTMSK_IISOIXFRM               0x00100000U            /*!< Incomplete isochronous IN transfer mask             */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         0x00200000U            /*!< Incomplete periodic transfer mask                   */
-#define USB_OTG_GINTMSK_FSUSPM                  0x00400000U            /*!< Data fetch suspended mask                           */
-#define USB_OTG_GINTMSK_RSTDEM                  0x00800000U            /*!< Reset detected interrupt mask                      */
-#define USB_OTG_GINTMSK_PRTIM                   0x01000000U            /*!< Host port interrupt mask                            */
-#define USB_OTG_GINTMSK_HCIM                    0x02000000U            /*!< Host channels interrupt mask                        */
-#define USB_OTG_GINTMSK_PTXFEM                  0x04000000U            /*!< Periodic TxFIFO empty mask                          */
-#define USB_OTG_GINTMSK_LPMINTM                 0x08000000U            /*!< LPM interrupt Mask                                  */
-#define USB_OTG_GINTMSK_CIDSCHGM                0x10000000U            /*!< Connector ID status change mask                     */
-#define USB_OTG_GINTMSK_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt mask                  */
-#define USB_OTG_GINTMSK_SRQIM                   0x40000000U            /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM                    0x80000000U            /*!< Resume/remote wakeup detected interrupt mask        */
-
-/********************  Bit definition forUSB_OTG_DAINT register  ********************/
-#define USB_OTG_DAINT_IEPINT                  0x0000FFFFU            /*!< IN endpoint interrupt bits  */
-#define USB_OTG_DAINT_OEPINT                  0xFFFF0000U            /*!< OUT endpoint interrupt bits */
-
-/********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/
-#define USB_OTG_HAINTMSK_HAINTM                  0x0000FFFFU            /*!< Channel interrupt mask */
-
-/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
-#define USB_OTG_GRXSTSP_EPNUM                    0x0000000FU            /*!< IN EP interrupt mask bits  */
-#define USB_OTG_GRXSTSP_BCNT                     0x00007FF0U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID                     0x00018000U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS                   0x001E0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/
-#define USB_OTG_DAINTMSK_IEPM                    0x0000FFFFU            /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM                    0xFFFF0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for OTG register  ********************/
-
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition for OTG register  ********************/
-
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/
-#define USB_OTG_GRXFSIZ_RXFD            0x0000FFFFU            /*!< RxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/
-#define USB_OTG_DVBUSDIS_VBUSDT         0x0000FFFFU            /*!< Device VBUS discharge time */
-
-/********************  Bit definition for OTG register  ********************/
-#define USB_OTG_NPTXFSA                 0x0000FFFFU            /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD                  0xFFFF0000U            /*!< Nonperiodic TxFIFO depth               */
-#define USB_OTG_TX0FSA                  0x0000FFFFU            /*!< Endpoint 0 transmit RAM start address  */
-#define USB_OTG_TX0FD                   0xFFFF0000U            /*!< Endpoint 0 TxFIFO depth                */
-
-/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
-#define USB_OTG_DVBUSPULSE_DVBUSP                  0x00000FFFU            /*!< Device VBUS pulsing time */
-
-/********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/
-#define USB_OTG_GNPTXSTS_NPTXFSAV                0x0000FFFFU            /*!< Nonperiodic TxFIFO space available */
-
-#define USB_OTG_GNPTXSTS_NPTQXSAV                0x00FF0000U            /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0              0x00010000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1              0x00020000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2              0x00040000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3              0x00080000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4              0x00100000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5              0x00200000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6              0x00400000U            /*!<Bit 6 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7              0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_GNPTXSTS_NPTXQTOP                0x7F000000U            /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0              0x01000000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1              0x02000000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2              0x04000000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3              0x08000000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4              0x10000000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5              0x20000000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6              0x40000000U            /*!<Bit 6 */
-
-/********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/
-#define USB_OTG_DTHRCTL_NONISOTHREN             0x00000001U            /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN                0x00000002U            /*!< ISO IN endpoint threshold enable */
-
-#define USB_OTG_DTHRCTL_TXTHRLEN                0x000007FCU            /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0              0x00000004U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1              0x00000008U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2              0x00000010U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3              0x00000020U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4              0x00000040U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5              0x00000080U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6              0x00000100U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7              0x00000200U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8              0x00000400U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_RXTHREN                 0x00010000U            /*!< Receive threshold enable */
-
-#define USB_OTG_DTHRCTL_RXTHRLEN                0x03FE0000U            /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0              0x00020000U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1              0x00040000U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2              0x00080000U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3              0x00100000U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4              0x00200000U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5              0x00400000U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6              0x00800000U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7              0x01000000U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8              0x02000000U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_ARPEN                   0x08000000U            /*!< Arbiter parking enable */
-
-/********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM               0x0000FFFFU         /*!< IN EP Tx FIFO empty interrupt mask bits */
-
-/********************  Bit definition forUSB_OTG_DEACHINT register  ********************/
-#define USB_OTG_DEACHINT_IEP1INT                 0x00000002U           /*!< IN endpoint 1interrupt bit   */
-#define USB_OTG_DEACHINT_OEP1INT                 0x00020000U           /*!< OUT endpoint 1 interrupt bit */
-
-/********************  Bit definition forUSB_OTG_GCCFG register  ********************/
-#define USB_OTG_GCCFG_PWRDWN                 0x00010000U              /*!< Power down */
-#define USB_OTG_GCCFG_VBDEN                  0x00200000U              /*!< USB VBUS Detection Enable */
-
-/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
-#define USB_OTG_DEACHINTMSK_IEP1INTM          0x00000002U            /*!< IN Endpoint 1 interrupt mask bit  */
-#define USB_OTG_DEACHINTMSK_OEP1INTM          0x00020000U            /*!< OUT Endpoint 1 interrupt mask bit */
- 
-/********************  Bit definition forUSB_OTG_CID register  ********************/
-#define USB_OTG_CID_PRODUCT_ID               0xFFFFFFFFU            /*!< Product ID field */
-
-/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/
-#define  USB_OTG_GLPMCFG_LPMEN               0x00000001U            /*!< LPM support enable                                     */
-#define  USB_OTG_GLPMCFG_LPMACK              0x00000002U            /*!< LPM Token acknowledge enable                           */
-#define  USB_OTG_GLPMCFG_BESL                0x0000003CU            /*!< BESL value received with last ACKed LPM Token          */
-#define  USB_OTG_GLPMCFG_REMWAKE             0x00000040U            /*!< bRemoteWake value received with last ACKed LPM Token   */
-#define  USB_OTG_GLPMCFG_L1SSEN              0x00000080U            /*!< L1 shallow sleep enable                                */
-#define  USB_OTG_GLPMCFG_BESLTHRS            0x00000F00U            /*!< BESL threshold                                         */
-#define  USB_OTG_GLPMCFG_L1DSEN              0x00001000U            /*!< L1 deep sleep enable                                   */
-#define  USB_OTG_GLPMCFG_LPMRSP              0x00006000U            /*!< LPM response                                           */
-#define  USB_OTG_GLPMCFG_SLPSTS              0x00008000U            /*!< Port sleep status                                      */
-#define  USB_OTG_GLPMCFG_L1RSMOK             0x00010000U            /*!< Sleep State Resume OK                                  */
-#define  USB_OTG_GLPMCFG_LPMCHIDX            0x001E0000U            /*!< LPM Channel Index                                      */
-#define  USB_OTG_GLPMCFG_LPMRCNT             0x00E00000U            /*!< LPM retry count                                        */
-#define  USB_OTG_GLPMCFG_SNDLPM              0x01000000U            /*!< Send LPM transaction                                   */
-#define  USB_OTG_GLPMCFG_LPMRCNTSTS          0x0E000000U            /*!< LPM retry count status                                 */
-#define  USB_OTG_GLPMCFG_ENBESL              0x10000000U            /*!< Enable best effort service latency                     */
-
-/********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/
-#define USB_OTG_DIEPEACHMSK1_XFRCM           0x00000001U            /*!< Transfer completed interrupt mask                 */
-#define USB_OTG_DIEPEACHMSK1_EPDM            0x00000002U            /*!< Endpoint disabled interrupt mask                  */
-#define USB_OTG_DIEPEACHMSK1_TOM             0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK       0x00000010U            /*!< IN token received when TxFIFO empty mask          */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM         0x00000020U            /*!< IN token received with EP mismatch mask           */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM         0x00000040U            /*!< IN endpoint NAK effective mask                    */
-#define USB_OTG_DIEPEACHMSK1_TXFURM          0x00000100U            /*!< FIFO underrun mask                                */
-#define USB_OTG_DIEPEACHMSK1_BIM             0x00000200U            /*!< BNA interrupt mask                                */
-#define USB_OTG_DIEPEACHMSK1_NAKM            0x00002000U            /*!< NAK interrupt mask                                */
-
-/********************  Bit definition forUSB_OTG_HPRT register  ********************/
-#define USB_OTG_HPRT_PCSTS                   0x00000001U            /*!< Port connect status        */
-#define USB_OTG_HPRT_PCDET                   0x00000002U            /*!< Port connect detected      */
-#define USB_OTG_HPRT_PENA                    0x00000004U            /*!< Port enable                */
-#define USB_OTG_HPRT_PENCHNG                 0x00000008U            /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA                    0x00000010U            /*!< Port overcurrent active    */
-#define USB_OTG_HPRT_POCCHNG                 0x00000020U            /*!< Port overcurrent change    */
-#define USB_OTG_HPRT_PRES                    0x00000040U            /*!< Port resume                */
-#define USB_OTG_HPRT_PSUSP                   0x00000080U            /*!< Port suspend               */
-#define USB_OTG_HPRT_PRST                    0x00000100U            /*!< Port reset                 */
-
-#define USB_OTG_HPRT_PLSTS                   0x00000C00U            /*!< Port line status           */
-#define USB_OTG_HPRT_PLSTS_0                 0x00000400U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PLSTS_1                 0x00000800U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PPWR                    0x00001000U            /*!< Port power                 */
-
-#define USB_OTG_HPRT_PTCTL                   0x0001E000U            /*!< Port test control          */
-#define USB_OTG_HPRT_PTCTL_0                 0x00002000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PTCTL_1                 0x00004000U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PTCTL_2                 0x00008000U            /*!<Bit 2 */
-#define USB_OTG_HPRT_PTCTL_3                 0x00010000U            /*!<Bit 3 */
-
-#define USB_OTG_HPRT_PSPD                    0x00060000U            /*!< Port speed                 */
-#define USB_OTG_HPRT_PSPD_0                  0x00020000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PSPD_1                  0x00040000U            /*!<Bit 1 */
-
-/********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/
-#define USB_OTG_DOEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask         */
-#define USB_OTG_DOEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask          */
-#define USB_OTG_DOEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask                    */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask  */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask   */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask            */
-#define USB_OTG_DOEPEACHMSK1_TXFURM                  0x00000100U            /*!< OUT packet error mask                     */
-#define USB_OTG_DOEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask                        */
-#define USB_OTG_DOEPEACHMSK1_BERRM                   0x00001000U            /*!< Bubble error interrupt mask               */
-#define USB_OTG_DOEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask                        */
-#define USB_OTG_DOEPEACHMSK1_NYETM                   0x00004000U            /*!< NYET interrupt mask                       */
-
-/********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/
-#define USB_OTG_HPTXFSIZ_PTXSA                   0x0000FFFFU            /*!< Host periodic TxFIFO start address            */
-#define USB_OTG_HPTXFSIZ_PTXFD                   0xFFFF0000U            /*!< Host periodic TxFIFO depth                    */
-
-/********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/
-#define USB_OTG_DIEPCTL_MPSIZ                   0x000007FFU            /*!< Maximum packet size              */
-#define USB_OTG_DIEPCTL_USBAEP                  0x00008000U            /*!< USB active endpoint              */
-#define USB_OTG_DIEPCTL_EONUM_DPID              0x00010000U            /*!< Even/odd frame                   */
-#define USB_OTG_DIEPCTL_NAKSTS                  0x00020000U            /*!< NAK status                       */
-
-#define USB_OTG_DIEPCTL_EPTYP                   0x000C0000U            /*!< Endpoint type                    */
-#define USB_OTG_DIEPCTL_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_STALL                   0x00200000U            /*!< STALL handshake                  */
-
-#define USB_OTG_DIEPCTL_TXFNUM                  0x03C00000U            /*!< TxFIFO number                    */
-#define USB_OTG_DIEPCTL_TXFNUM_0                0x00400000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                0x00800000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                0x01000000U            /*!<Bit 2 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                0x02000000U            /*!<Bit 3 */
-#define USB_OTG_DIEPCTL_CNAK                    0x04000000U            /*!< Clear NAK                        */
-#define USB_OTG_DIEPCTL_SNAK                    0x08000000U            /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          0x10000000U            /*!< Set DATA0 PID                    */
-#define USB_OTG_DIEPCTL_SODDFRM                 0x20000000U            /*!< Set odd frame                    */
-#define USB_OTG_DIEPCTL_EPDIS                   0x40000000U            /*!< Endpoint disable                 */
-#define USB_OTG_DIEPCTL_EPENA                   0x80000000U            /*!< Endpoint enable                  */
-
-/********************  Bit definition forUSB_OTG_HCCHAR register  ********************/
-#define USB_OTG_HCCHAR_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
-
-#define USB_OTG_HCCHAR_EPNUM                   0x00007800U            /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPNUM_1                 0x00001000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_EPNUM_2                 0x00002000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_EPNUM_3                 0x00004000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_EPDIR                   0x00008000U            /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV                   0x00020000U            /*!< Low-speed device */
-
-#define USB_OTG_HCCHAR_EPTYP                   0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_MC                      0x00300000U            /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                    0x00100000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_MC_1                    0x00200000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_DAD                     0x1FC00000U            /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                   0x00400000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_DAD_1                   0x00800000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_DAD_2                   0x01000000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_DAD_3                   0x02000000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_DAD_4                   0x04000000U            /*!<Bit 4 */
-#define USB_OTG_HCCHAR_DAD_5                   0x08000000U            /*!<Bit 5 */
-#define USB_OTG_HCCHAR_DAD_6                   0x10000000U            /*!<Bit 6 */
-#define USB_OTG_HCCHAR_ODDFRM                  0x20000000U            /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS                   0x40000000U            /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA                   0x80000000U            /*!< Channel enable */
-
-/********************  Bit definition forUSB_OTG_HCSPLT register  ********************/
-
-#define USB_OTG_HCSPLT_PRTADDR                 0x0000007FU            /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_PRTADDR_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_PRTADDR_2               0x00000004U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_PRTADDR_3               0x00000008U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_PRTADDR_4               0x00000010U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_PRTADDR_5               0x00000020U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_PRTADDR_6               0x00000040U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_HUBADDR                 0x00003F80U            /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0               0x00000080U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_HUBADDR_1               0x00000100U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_HUBADDR_2               0x00000200U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_HUBADDR_3               0x00000400U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_HUBADDR_4               0x00000800U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_HUBADDR_5               0x00001000U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_HUBADDR_6               0x00002000U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_XACTPOS                 0x0000C000U            /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0               0x00004000U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_XACTPOS_1               0x00008000U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_COMPLSPLT               0x00010000U            /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN                 0x80000000U            /*!< Split enable */
-
-/********************  Bit definition forUSB_OTG_HCINT register  ********************/
-#define USB_OTG_HCINT_XFRC                    0x00000001U            /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH                     0x00000002U            /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINT_STALL                   0x00000008U            /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK                     0x00000010U            /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK                     0x00000020U            /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET                    0x00000040U            /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR                   0x00000080U            /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR                   0x00000100U            /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR                   0x00000200U            /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR                   0x00000400U            /*!< Data toggle error */
-
-/********************  Bit definition forUSB_OTG_DIEPINT register  ********************/
-#define USB_OTG_DIEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_TOC                     0x00000008U            /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE                  0x00000010U            /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNE                  0x00000040U            /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE                    0x00000080U            /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN              0x00000100U            /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA                     0x00000200U            /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS               0x00000800U            /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR                    0x00001000U            /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK                     0x00002000U            /*!< NAK interrupt */
-
-/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
-#define USB_OTG_HCINTMSK_XFRCM                   0x00000001U            /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM                    0x00000002U            /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM                  0x00000008U            /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM                    0x00000010U            /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM                    0x00000020U            /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET                    0x00000040U            /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM                  0x00000080U            /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM                  0x00000100U            /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM                  0x00000200U            /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM                  0x00000400U            /*!< Data toggle error mask */
-
-/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
-
-#define USB_OTG_DIEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT                  0x60000000U            /*!< Packet count */
-/********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/
-#define USB_OTG_HCTSIZ_XFRSIZ                    0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT                    0x1FF80000U            /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING                    0x80000000U            /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID                      0x60000000U            /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                    0x20000000U            /*!<Bit 0 */
-#define USB_OTG_HCTSIZ_DPID_1                    0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/
-#define USB_OTG_DIEPDMA_DMAADDR                  0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition forUSB_OTG_HCDMA register  ********************/
-#define USB_OTG_HCDMA_DMAADDR                    0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/
-#define USB_OTG_DTXFSTS_INEPTFSAV                0x0000FFFFU            /*!< IN endpoint TxFIFO space available */
-
-/********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/
-#define USB_OTG_DIEPTXF_INEPTXSA                 0x0000FFFFU            /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD                 0xFFFF0000U            /*!< IN endpoint TxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/
-
-#define USB_OTG_DOEPCTL_MPSIZ                     0x000007FFU            /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP                    0x00008000U            /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS                    0x00020000U            /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            0x10000000U            /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM                   0x20000000U            /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP                     0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                   0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DOEPCTL_EPTYP_1                   0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_SNPM                      0x00100000U            /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL                     0x00200000U            /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK                      0x04000000U            /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK                      0x08000000U            /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS                     0x40000000U            /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA                     0x80000000U            /*!< Endpoint enable */
-
-/********************  Bit definition forUSB_OTG_DOEPINT register  ********************/
-#define USB_OTG_DOEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_STUP                    0x00000008U            /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS                 0x00000010U            /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_OTEPSPR                 0x00000020U            /*!< Status Phase Received For Control Write */
-#define USB_OTG_DOEPINT_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_NYET                    0x00004000U            /*!< NYET interrupt */
-
-/********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/
-
-#define USB_OTG_DOEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-
-#define USB_OTG_DOEPTSIZ_STUPCNT                 0x60000000U            /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0               0x20000000U            /*!<Bit 0 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1               0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition for PCGCCTL register  ********************/
-#define USB_OTG_PCGCCTL_STOPCLK                 0x00000001U            /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK                 0x00000002U            /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP                 0x00000010U            /*!<Bit 1 */
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
-                                       ((INSTANCE) == ADC2) || \
-                                       ((INSTANCE) == ADC3))
-
-/******************************* CAN Instances ********************************/
-#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
-                                       ((INSTANCE) == CAN2))
- 
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DAC Instances ********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/******************************* DCMI Instances *******************************/
-#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
-
-/******************************* DMA2D Instances *******************************/
-#define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
-
-/******************************** DMA Instances *******************************/
-#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
-                                              ((INSTANCE) == DMA1_Stream1) || \
-                                              ((INSTANCE) == DMA1_Stream2) || \
-                                              ((INSTANCE) == DMA1_Stream3) || \
-                                              ((INSTANCE) == DMA1_Stream4) || \
-                                              ((INSTANCE) == DMA1_Stream5) || \
-                                              ((INSTANCE) == DMA1_Stream6) || \
-                                              ((INSTANCE) == DMA1_Stream7) || \
-                                              ((INSTANCE) == DMA2_Stream0) || \
-                                              ((INSTANCE) == DMA2_Stream1) || \
-                                              ((INSTANCE) == DMA2_Stream2) || \
-                                              ((INSTANCE) == DMA2_Stream3) || \
-                                              ((INSTANCE) == DMA2_Stream4) || \
-                                              ((INSTANCE) == DMA2_Stream5) || \
-                                              ((INSTANCE) == DMA2_Stream6) || \
-                                              ((INSTANCE) == DMA2_Stream7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOF) || \
-                                        ((INSTANCE) == GPIOG) || \
-                                        ((INSTANCE) == GPIOH) || \
-                                        ((INSTANCE) == GPIOI) || \
-                                        ((INSTANCE) == GPIOJ) || \
-                                        ((INSTANCE) == GPIOK))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2) || \
-                                       ((INSTANCE) == I2C3))
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI2) || \
-                                    ((INSTANCE) == SPI3))
-
-/*************************** I2S Extended Instances ***************************/
-#define IS_I2S_ALL_INSTANCE_EXT(PERIPH)  (((INSTANCE) == SPI2)    || \
-                                      ((INSTANCE) == SPI3)    || \
-                                      ((INSTANCE) == I2S2ext) || \
-                                      ((INSTANCE) == I2S3ext))
-
-/****************************** LTDC Instances ********************************/
-#define IS_LTDC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == LTDC)
-
-/******************************* RNG Instances ********************************/
-#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************* SAI Instances ********************************/
-#define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
-                                     ((PERIPH) == SAI1_Block_B))
-/* Legacy define */
-#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3) || \
-                                       ((INSTANCE) == SPI4) || \
-                                       ((INSTANCE) == SPI5) || \
-                                       ((INSTANCE) == SPI6))
-
-/*************************** SPI Extended Instances ***************************/
-#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1)    || \
-                                           ((INSTANCE) == SPI2)    || \
-                                           ((INSTANCE) == SPI3)    || \
-                                           ((INSTANCE) == SPI4)    || \
-                                           ((INSTANCE) == SPI5)    || \
-                                           ((INSTANCE) == SPI6)    || \
-                                           ((INSTANCE) == I2S2ext) || \
-                                           ((INSTANCE) == I2S3ext))
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
-                                   ((INSTANCE) == TIM2)   || \
-                                   ((INSTANCE) == TIM3)   || \
-                                   ((INSTANCE) == TIM4)   || \
-                                   ((INSTANCE) == TIM5)   || \
-                                   ((INSTANCE) == TIM6)   || \
-                                   ((INSTANCE) == TIM7)   || \
-                                   ((INSTANCE) == TIM8)   || \
-                                   ((INSTANCE) == TIM9)   || \
-                                   ((INSTANCE) == TIM10)  || \
-                                   ((INSTANCE) == TIM11)  || \
-                                   ((INSTANCE) == TIM12)  || \
-                                   ((INSTANCE) == TIM13)  || \
-                                   ((INSTANCE) == TIM14))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
-                                         ((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM8)  || \
-                                         ((INSTANCE) == TIM9)  || \
-                                         ((INSTANCE) == TIM10) || \
-                                         ((INSTANCE) == TIM11) || \
-                                         ((INSTANCE) == TIM12) || \
-                                         ((INSTANCE) == TIM13) || \
-                                         ((INSTANCE) == TIM14))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM8) || \
-                                       ((INSTANCE) == TIM9) || \
-                                       ((INSTANCE) == TIM12))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8))
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM8))
-
-/******************** TIM Instances : Advanced-control timers *****************/
-#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                            ((INSTANCE) == TIM8))
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8))
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM6) || \
-                                       ((INSTANCE) == TIM7) || \
-                                       ((INSTANCE) == TIM8))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM8))
-
-/************ TIM Instances : DMA requests generation (COMDE) *****************/
-#define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM8)) 
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                             ((INSTANCE) == TIM2) || \
-                                             ((INSTANCE) == TIM3) || \
-                                             ((INSTANCE) == TIM4) || \
-                                             ((INSTANCE) == TIM5) || \
-                                             ((INSTANCE) == TIM8))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM6) || \
-                                          ((INSTANCE) == TIM7) || \
-                                          ((INSTANCE) == TIM8) || \
-                                          ((INSTANCE) == TIM9) || \
-                                          ((INSTANCE) == TIM12))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8) || \
-                                         ((INSTANCE) == TIM9) || \
-                                         ((INSTANCE) == TIM12))
-
-/********************** TIM Instances : 32 bit Counter ************************/
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
-                                              ((INSTANCE) == TIM5))
-
-/***************** TIM Instances : external trigger input availabe ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                        ((INSTANCE) == TIM2) || \
-                                        ((INSTANCE) == TIM3) || \
-                                        ((INSTANCE) == TIM4) || \
-                                        ((INSTANCE) == TIM5) || \
-                                        ((INSTANCE) == TIM8))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM11))
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM1) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM5) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM8) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM12) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM13) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM14) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-/************ TIM Instances : complementary output(s) available ***************/
-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
-   ((((INSTANCE) == TIM1) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3)))            \
-    ||                                          \
-    (((INSTANCE) == TIM8) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3))))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3) || \
-                                     ((INSTANCE) == USART6))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5)  || \
-                                    ((INSTANCE) == USART6) || \
-                                    ((INSTANCE) == UART7)  || \
-                                    ((INSTANCE) == UART8))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3) || \
-                                           ((INSTANCE) == USART6))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3) || \
-                                         ((INSTANCE) == USART6))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5)  || \
-                                    ((INSTANCE) == USART6) || \
-                                    ((INSTANCE) == UART7)  || \
-                                    ((INSTANCE) == UART8))
-    
-/*********************** PCD Instances ****************************************/
-#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
-                                        ((INSTANCE) == USB_OTG_HS))
-
-/*********************** HCD Instances ****************************************/
-#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
-                                       ((INSTANCE) == USB_OTG_HS))
-
-/****************************** SDIO Instances ********************************/
-#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/****************************** QSPI Instances ********************************/
-#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
-
-/****************************** USB Exported Constants ************************/
-#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                12U
-#define USB_OTG_FS_MAX_IN_ENDPOINTS                    6U    /* Including EP0 */
-#define USB_OTG_FS_MAX_OUT_ENDPOINTS                   6U    /* Including EP0 */
-#define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */
-
-#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR                16U
-#define USB_OTG_HS_MAX_IN_ENDPOINTS                    8U    /* Including EP0 */
-#define USB_OTG_HS_MAX_OUT_ENDPOINTS                   8U    /* Including EP0 */
-#define USB_OTG_HS_TOTAL_FIFO_SIZE                     4096U /* in Bytes */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32F469xx_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/cmsis/stm32f479xx.h b/stmhal/cmsis/stm32f479xx.h
deleted file mode 100644
index c26a2cce1d..0000000000
--- a/stmhal/cmsis/stm32f479xx.h
+++ /dev/null
@@ -1,10441 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f479xx.h
-  * @author  MCD Application Team
-  * @version V2.5.1
-  * @date    28-June-2016
-  * @brief   CMSIS STM32F479xx Device Peripheral Access Layer Header File.
-  *
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - peripherals registers declarations and bits definition
-  *           - Macros to access peripheral’s registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS_Device
-  * @{
-  */
-
-/** @addtogroup stm32f479xx
-  * @{
-  */
-    
-#ifndef __STM32F479xx_H
-#define __STM32F479xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-  
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-
-/**
-  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
-  */
-#define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */
-#define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */
-#define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1U       /*!< FPU present                                   */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32F4XX Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-typedef enum
-{
-/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
-  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
-/******  STM32 specific Interrupt Numbers **********************************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
-  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
-  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
-  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
-  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
-  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
-  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
-  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
-  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
-  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
-  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
-  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
-  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
-  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
-  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
-  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
-  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
-  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */    
-  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
-  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
-  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
-  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare global interrupt                             */
-  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
-  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
-  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
-  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
-  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
-  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
-  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
-  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
-  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
-  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
-  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
-  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
-  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
-  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
-  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
-  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
-  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
-  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
-  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
-  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
-  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
-  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
-  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
-  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
-  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
-  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
-  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
-  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
-  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
-  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
-  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
-  CRYP_IRQn                   = 79,     /*!< CRYP crypto global interrupt                                      */
-  HASH_RNG_IRQn               = 80,     /*!< Hash and Rng global interrupt                                     */
-  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
-  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */
-  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */
-  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
-  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */
-  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */
-  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
-  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                              */
-  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                        */
-  DMA2D_IRQn                  = 90,     /*!< DMA2D global Interrupt                                            */
-  QUADSPI_IRQn                = 91,     /*!< QUADSPI global Interrupt                                          */
-  DSI_IRQn                    = 92      /*!< DSI global Interrupt                                              */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
-#include "system_stm32f4xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */      
-  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
-  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
-  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
-  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
-  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
-  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
-  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
-  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
-  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
-  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
-  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
-  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
-  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
-  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
-  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
-                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
-} ADC_Common_TypeDef;
-
-
-/** 
-  * @brief Controller Area Network TxMailBox 
-  */
-
-typedef struct
-{
-  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
-  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
-  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
-  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
-} CAN_TxMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FIFOMailBox 
-  */
-  
-typedef struct
-{
-  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
-  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
-  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
-  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
-} CAN_FIFOMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FilterRegister 
-  */
-  
-typedef struct
-{
-  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
-  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
-} CAN_FilterRegister_TypeDef;
-
-/** 
-  * @brief Controller Area Network 
-  */
-  
-typedef struct
-{
-  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
-  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
-  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
-  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
-  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
-  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
-  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
-  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
-  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
-  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
-  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
-  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
-  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
-  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
-  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
-  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
-  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
-  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
-  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
-  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
-  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */ 
-  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
-} CAN_TypeDef;
-
-/** 
-  * @brief CRC calculation unit 
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
-  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */
-  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
-  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
-  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
-  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
-  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
-  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
-  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
-  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
-  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
-  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
-  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
-  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
-  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
-  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
-  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
-  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
-  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
-  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DCMI
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
-  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
-  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
-  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
-  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
-  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
-  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
-  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
-  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
-  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
-  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
-} DCMI_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
-  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
-  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
-  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
-  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
-  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
-} DMA_Stream_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
-  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
-  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
-  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
-} DMA_TypeDef;
-
-/** 
-  * @brief DMA2D Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
-  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
-  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
-  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
-  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
-  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
-  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
-  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
-  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
-  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
-  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
-  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
-  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
-  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
-  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
-  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
-  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
-  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
-  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
-  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
-  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
-  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */
-  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */
-} DMA2D_TypeDef;
-
-/** 
-  * @brief DSI Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t VR;            /*!< DSI Host Version Register,                                 Address offset: 0x00      */
-  __IO uint32_t CR;            /*!< DSI Host Control Register,                                 Address offset: 0x04      */
-  __IO uint32_t CCR;           /*!< DSI HOST Clock Control Register,                           Address offset: 0x08      */
-  __IO uint32_t LVCIDR;        /*!< DSI Host LTDC VCID Register,                               Address offset: 0x0C      */
-  __IO uint32_t LCOLCR;        /*!< DSI Host LTDC Color Coding Register,                       Address offset: 0x10      */ 
-  __IO uint32_t LPCR;          /*!< DSI Host LTDC Polarity Configuration Register,             Address offset: 0x14      */
-  __IO uint32_t LPMCR;         /*!< DSI Host Low-Power Mode Configuration Register,            Address offset: 0x18      */
-  uint32_t      RESERVED0[4];  /*!< Reserved, 0x1C - 0x2B                                                                */
-  __IO uint32_t PCR;           /*!< DSI Host Protocol Configuration Register,                  Address offset: 0x2C      */ 
-  __IO uint32_t GVCIDR;        /*!< DSI Host Generic VCID Register,                            Address offset: 0x30      */
-  __IO uint32_t MCR;           /*!< DSI Host Mode Configuration Register,                      Address offset: 0x34      */
-  __IO uint32_t VMCR;          /*!< DSI Host Video Mode Configuration Register,                Address offset: 0x38      */
-  __IO uint32_t VPCR;          /*!< DSI Host Video Packet Configuration Register,              Address offset: 0x3C      */
-  __IO uint32_t VCCR;          /*!< DSI Host Video Chunks Configuration Register,              Address offset: 0x40      */
-  __IO uint32_t VNPCR;         /*!< DSI Host Video Null Packet Configuration Register,         Address offset: 0x44      */
-  __IO uint32_t VHSACR;        /*!< DSI Host Video HSA Configuration Register,                 Address offset: 0x48      */
-  __IO uint32_t VHBPCR;        /*!< DSI Host Video HBP Configuration Register,                 Address offset: 0x4C      */
-  __IO uint32_t VLCR;          /*!< DSI Host Video Line Configuration Register,                Address offset: 0x50      */
-  __IO uint32_t VVSACR;        /*!< DSI Host Video VSA Configuration Register,                 Address offset: 0x54      */
-  __IO uint32_t VVBPCR;        /*!< DSI Host Video VBP Configuration Register,                 Address offset: 0x58      */
-  __IO uint32_t VVFPCR;        /*!< DSI Host Video VFP Configuration Register,                 Address offset: 0x5C      */
-  __IO uint32_t VVACR;         /*!< DSI Host Video VA Configuration Register,                  Address offset: 0x60      */
-  __IO uint32_t LCCR;          /*!< DSI Host LTDC Command Configuration Register,              Address offset: 0x64      */ 
-  __IO uint32_t CMCR;          /*!< DSI Host Command Mode Configuration Register,              Address offset: 0x68      */
-  __IO uint32_t GHCR;          /*!< DSI Host Generic Header Configuration Register,            Address offset: 0x6C      */
-  __IO uint32_t GPDR;          /*!< DSI Host Generic Payload Data Register,                    Address offset: 0x70      */
-  __IO uint32_t GPSR;          /*!< DSI Host Generic Packet Status Register,                   Address offset: 0x74      */
-  __IO uint32_t TCCR[6];       /*!< DSI Host Timeout Counter Configuration Register,           Address offset: 0x78-0x8F */
-  __IO uint32_t TDCR;          /*!< DSI Host 3D Configuration Register,                        Address offset: 0x90      */ 
-  __IO uint32_t CLCR;          /*!< DSI Host Clock Lane Configuration Register,                Address offset: 0x94      */
-  __IO uint32_t CLTCR;         /*!< DSI Host Clock Lane Timer Configuration Register,          Address offset: 0x98      */
-  __IO uint32_t DLTCR;         /*!< DSI Host Data Lane Timer Configuration Register,           Address offset: 0x9C      */
-  __IO uint32_t PCTLR;         /*!< DSI Host PHY Control Register,                             Address offset: 0xA0      */ 
-  __IO uint32_t PCONFR;        /*!< DSI Host PHY Configuration Register,                       Address offset: 0xA4      */ 
-  __IO uint32_t PUCR;          /*!< DSI Host PHY ULPS Control Register,                        Address offset: 0xA8      */
-  __IO uint32_t PTTCR;         /*!< DSI Host PHY TX Triggers Configuration Register,           Address offset: 0xAC      */
-  __IO uint32_t PSR;           /*!< DSI Host PHY Status Register,                              Address offset: 0xB0      */
-  uint32_t      RESERVED1[2];  /*!< Reserved, 0xB4 - 0xBB                                                                */
-  __IO uint32_t ISR[2];        /*!< DSI Host Interrupt & Status Register,                      Address offset: 0xBC-0xC3 */
-  __IO uint32_t IER[2];        /*!< DSI Host Interrupt Enable Register,                        Address offset: 0xC4-0xCB */
-  uint32_t      RESERVED2[3];  /*!< Reserved, 0xD0 - 0xD7                                                                */
-  __IO uint32_t FIR[2];        /*!< DSI Host Force Interrupt Register,                         Address offset: 0xD8-0xDF */
-  uint32_t      RESERVED3[8];  /*!< Reserved, 0xE0 - 0xFF                                                                */
-  __IO uint32_t VSCR;          /*!< DSI Host Video Shadow Control Register,                    Address offset: 0x100     */
-  uint32_t      RESERVED4[2];  /*!< Reserved, 0x104 - 0x10B                                                              */
-  __IO uint32_t LCVCIDR;       /*!< DSI Host LTDC Current VCID Register,                       Address offset: 0x10C     */
-  __IO uint32_t LCCCR;         /*!< DSI Host LTDC Current Color Coding Register,               Address offset: 0x110     */
-  uint32_t      RESERVED5;     /*!< Reserved, 0x114                                                                      */
-  __IO uint32_t LPMCCR;        /*!< DSI Host Low-power Mode Current Configuration Register,    Address offset: 0x118     */
-  uint32_t      RESERVED6[7];  /*!< Reserved, 0x11C - 0x137                                                              */
-  __IO uint32_t VMCCR;         /*!< DSI Host Video Mode Current Configuration Register,        Address offset: 0x138     */
-  __IO uint32_t VPCCR;         /*!< DSI Host Video Packet Current Configuration Register,      Address offset: 0x13C     */
-  __IO uint32_t VCCCR;         /*!< DSI Host Video Chuncks Current Configuration Register,     Address offset: 0x140     */
-  __IO uint32_t VNPCCR;        /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144     */
-  __IO uint32_t VHSACCR;       /*!< DSI Host Video HSA Current Configuration Register,         Address offset: 0x148     */
-  __IO uint32_t VHBPCCR;       /*!< DSI Host Video HBP Current Configuration Register,         Address offset: 0x14C     */
-  __IO uint32_t VLCCR;         /*!< DSI Host Video Line Current Configuration Register,        Address offset: 0x150     */
-  __IO uint32_t VVSACCR;       /*!< DSI Host Video VSA Current Configuration Register,         Address offset: 0x154     */ 
-  __IO uint32_t VVBPCCR;       /*!< DSI Host Video VBP Current Configuration Register,         Address offset: 0x158     */
-  __IO uint32_t VVFPCCR;       /*!< DSI Host Video VFP Current Configuration Register,         Address offset: 0x15C     */
-  __IO uint32_t VVACCR;        /*!< DSI Host Video VA Current Configuration Register,          Address offset: 0x160     */
-  uint32_t      RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F                                                              */
-  __IO uint32_t TDCCR;         /*!< DSI Host 3D Current Configuration Register,                Address offset: 0x190     */ 
-  uint32_t      RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF                                                               */
-  __IO uint32_t WCFGR;          /*!< DSI Wrapper Configuration Register,                       Address offset: 0x400       */
-  __IO uint32_t WCR;            /*!< DSI Wrapper Control Register,                             Address offset: 0x404       */
-  __IO uint32_t WIER;           /*!< DSI Wrapper Interrupt Enable Register,                    Address offset: 0x408       */
-  __IO uint32_t WISR;           /*!< DSI Wrapper Interrupt and Status Register,                Address offset: 0x40C       */
-  __IO uint32_t WIFCR;          /*!< DSI Wrapper Interrupt Flag Clear Register,                Address offset: 0x410       */
-  uint32_t      RESERVED9;      /*!< Reserved, 0x414                                                                       */
-  __IO uint32_t WPCR[5];        /*!< DSI Wrapper PHY Configuration Register,                   Address offset: 0x418-0x42B */
-  uint32_t      RESERVED10;     /*!< Reserved, 0x42C                                                                       */
-  __IO uint32_t WRPCR;          /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430                 */
-} DSI_TypeDef;
-
-/** 
-  * @brief Ethernet MAC
-  */
-
-typedef struct
-{
-  __IO uint32_t MACCR;
-  __IO uint32_t MACFFR;
-  __IO uint32_t MACHTHR;
-  __IO uint32_t MACHTLR;
-  __IO uint32_t MACMIIAR;
-  __IO uint32_t MACMIIDR;
-  __IO uint32_t MACFCR;
-  __IO uint32_t MACVLANTR;             /*    8 */
-  uint32_t      RESERVED0[2];
-  __IO uint32_t MACRWUFFR;             /*   11 */
-  __IO uint32_t MACPMTCSR;
-  uint32_t      RESERVED1[2];
-  __IO uint32_t MACSR;                 /*   15 */
-  __IO uint32_t MACIMR;
-  __IO uint32_t MACA0HR;
-  __IO uint32_t MACA0LR;
-  __IO uint32_t MACA1HR;
-  __IO uint32_t MACA1LR;
-  __IO uint32_t MACA2HR;
-  __IO uint32_t MACA2LR;
-  __IO uint32_t MACA3HR;
-  __IO uint32_t MACA3LR;               /*   24 */
-  uint32_t      RESERVED2[40];
-  __IO uint32_t MMCCR;                 /*   65 */
-  __IO uint32_t MMCRIR;
-  __IO uint32_t MMCTIR;
-  __IO uint32_t MMCRIMR;
-  __IO uint32_t MMCTIMR;               /*   69 */
-  uint32_t      RESERVED3[14];
-  __IO uint32_t MMCTGFSCCR;            /*   84 */
-  __IO uint32_t MMCTGFMSCCR;
-  uint32_t      RESERVED4[5];
-  __IO uint32_t MMCTGFCR;
-  uint32_t      RESERVED5[10];
-  __IO uint32_t MMCRFCECR;
-  __IO uint32_t MMCRFAECR;
-  uint32_t      RESERVED6[10];
-  __IO uint32_t MMCRGUFCR;
-  uint32_t      RESERVED7[334];
-  __IO uint32_t PTPTSCR;
-  __IO uint32_t PTPSSIR;
-  __IO uint32_t PTPTSHR;
-  __IO uint32_t PTPTSLR;
-  __IO uint32_t PTPTSHUR;
-  __IO uint32_t PTPTSLUR;
-  __IO uint32_t PTPTSAR;
-  __IO uint32_t PTPTTHR;
-  __IO uint32_t PTPTTLR;
-  __IO uint32_t RESERVED8;
-  __IO uint32_t PTPTSSR;
-  uint32_t      RESERVED9[565];
-  __IO uint32_t DMABMR;
-  __IO uint32_t DMATPDR;
-  __IO uint32_t DMARPDR;
-  __IO uint32_t DMARDLAR;
-  __IO uint32_t DMATDLAR;
-  __IO uint32_t DMASR;
-  __IO uint32_t DMAOMR;
-  __IO uint32_t DMAIER;
-  __IO uint32_t DMAMFBOCR;
-  __IO uint32_t DMARSWTR;
-  uint32_t      RESERVED10[8];
-  __IO uint32_t DMACHTDR;
-  __IO uint32_t DMACHRDR;
-  __IO uint32_t DMACHTBAR;
-  __IO uint32_t DMACHRBAR;
-} ETH_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
-  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
-  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
-  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
-  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
-  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-
-typedef struct
-{
-  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */
-  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */
-  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */
-  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */
-  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */
-  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief Flexible Memory Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */   
-} FMC_Bank1_TypeDef; 
-
-/** 
-  * @brief Flexible Memory Controller Bank1E
-  */
-  
-typedef struct
-{
-  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
-} FMC_Bank1E_TypeDef;
-
-/** 
-  * @brief Flexible Memory Controller Bank3
-  */
- 
-typedef struct
-{
-  __IO uint32_t PCR;       /*!< NAND Flash control register,                       Address offset: 0x80 */
-  __IO uint32_t SR;        /*!< NAND Flash FIFO status and interrupt register,     Address offset: 0x84 */
-  __IO uint32_t PMEM;      /*!< NAND Flash Common memory space timing register,    Address offset: 0x88 */
-  __IO uint32_t PATT;      /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
-  uint32_t      RESERVED;  /*!< Reserved, 0x90                                                          */
-  __IO uint32_t ECCR;      /*!< NAND Flash ECC result registers,                   Address offset: 0x94 */
-} FMC_Bank3_TypeDef;
-
-/** 
-  * @brief Flexible Memory Controller Bank5_6
-  */
-  
-typedef struct
-{
-  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */
-  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */
-  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */
-  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */
-  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */
-} FMC_Bank5_6_TypeDef; 
-
-/** 
-  * @brief General Purpose I/O
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
-  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
-  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
-  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
-  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
-  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
-  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
-  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/** 
-  * @brief System configuration controller
-  */
-  
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */ 
-  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */
-  __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */
-  __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */
-  __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */
-  __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */
-  __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
-  __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
-  __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
-  __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief LCD-TFT Display Controller
-  */
-  
-typedef struct
-{
-  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04 */
-  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */
-  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */
-  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */
-  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */
-  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */
-  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20 */
-  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */
-  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28 */
-  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */
-  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30 */
-  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */
-  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */
-  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */
-  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
-  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */
-  __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                       Address offset: 0x48 */
-} LTDC_TypeDef;  
-
-/** 
-  * @brief LCD-TFT Display layer x Controller
-  */
-  
-typedef struct
-{  
-  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */
-  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
-  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */
-  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */
-  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */
-  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */
-  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */
-  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */
-  uint32_t      RESERVED0[2];  /*!< Reserved */
-  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */
-  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */
-  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */
-  uint32_t      RESERVED1[3];  /*!< Reserved */
-  __IO uint32_t CLUTWR;         /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */
-
-} LTDC_Layer_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
-  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
-  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
-  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
-  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
-  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
-  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
-  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
-  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
-  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
-  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
-  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
-  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
-  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
-  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
-  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
-  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
-  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
-  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
-  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
-  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
-  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
-  __IO uint32_t PLLSAICFGR;    /*!< RCC PLLSAI configuration register,                           Address offset: 0x88 */
-  __IO uint32_t DCKCFGR;       /*!< RCC Dedicated Clocks configuration register,                 Address offset: 0x8C */
-
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-
-typedef struct
-{
-  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
-  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
-  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
-  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
-  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
-  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
-  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */
-  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
-  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */
-  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
-  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */
-  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */
-  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */
-  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */
-  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
-  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */
-  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
-  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
-  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
-  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
-  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
-  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
-  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
-  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
-  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
-  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
-  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
-  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
-  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
-  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
-  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
-  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
-  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
-  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
-  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
-  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
-  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
-} RTC_TypeDef;
-
-/** 
-  * @brief Serial Audio Interface
-  */
-  
-typedef struct
-{
-  __IO uint32_t GCR;      /*!< SAI global configuration register,        Address offset: 0x00 */
-} SAI_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */
-  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */
-  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */
-  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */
-  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
-  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */
-  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */
-  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */
-} SAI_Block_TypeDef;
-
-/** 
-  * @brief SD host Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t POWER;          /*!< SDIO power control register,    Address offset: 0x00 */
-  __IO uint32_t CLKCR;          /*!< SDI clock control register,     Address offset: 0x04 */
-  __IO uint32_t ARG;            /*!< SDIO argument register,         Address offset: 0x08 */
-  __IO uint32_t CMD;            /*!< SDIO command register,          Address offset: 0x0C */
-  __I uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */
-  __I uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */
-  __I uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */
-  __I uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */
-  __I uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */
-  __IO uint32_t DTIMER;         /*!< SDIO data timer register,       Address offset: 0x24 */
-  __IO uint32_t DLEN;           /*!< SDIO data length register,      Address offset: 0x28 */
-  __IO uint32_t DCTRL;          /*!< SDIO data control register,     Address offset: 0x2C */
-  __I uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */
-  __I uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */
-  __IO uint32_t ICR;            /*!< SDIO interrupt clear register,  Address offset: 0x38 */
-  __IO uint32_t MASK;           /*!< SDIO mask register,             Address offset: 0x3C */
-  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
-  __I uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */
-  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
-  __IO uint32_t FIFO;           /*!< SDIO data FIFO register,        Address offset: 0x80 */
-} SDIO_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief QUAD Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */
-  __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
-  __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */
-  __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
-  __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
-  __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
-  __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */
-  __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
-  __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */
-  __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
-  __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */                  
-  __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
-  __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */    
-} QUADSPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
-  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
-  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
-  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Crypto Processor
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;         /*!< CRYP control register,                                    Address offset: 0x00 */
-  __IO uint32_t SR;         /*!< CRYP status register,                                     Address offset: 0x04 */
-  __IO uint32_t DR;         /*!< CRYP data input register,                                 Address offset: 0x08 */
-  __IO uint32_t DOUT;       /*!< CRYP data output register,                                Address offset: 0x0C */
-  __IO uint32_t DMACR;      /*!< CRYP DMA control register,                                Address offset: 0x10 */
-  __IO uint32_t IMSCR;      /*!< CRYP interrupt mask set/clear register,                   Address offset: 0x14 */
-  __IO uint32_t RISR;       /*!< CRYP raw interrupt status register,                       Address offset: 0x18 */
-  __IO uint32_t MISR;       /*!< CRYP masked interrupt status register,                    Address offset: 0x1C */
-  __IO uint32_t K0LR;       /*!< CRYP key left  register 0,                                Address offset: 0x20 */
-  __IO uint32_t K0RR;       /*!< CRYP key right register 0,                                Address offset: 0x24 */
-  __IO uint32_t K1LR;       /*!< CRYP key left  register 1,                                Address offset: 0x28 */
-  __IO uint32_t K1RR;       /*!< CRYP key right register 1,                                Address offset: 0x2C */
-  __IO uint32_t K2LR;       /*!< CRYP key left  register 2,                                Address offset: 0x30 */
-  __IO uint32_t K2RR;       /*!< CRYP key right register 2,                                Address offset: 0x34 */
-  __IO uint32_t K3LR;       /*!< CRYP key left  register 3,                                Address offset: 0x38 */
-  __IO uint32_t K3RR;       /*!< CRYP key right register 3,                                Address offset: 0x3C */
-  __IO uint32_t IV0LR;      /*!< CRYP initialization vector left-word  register 0,         Address offset: 0x40 */
-  __IO uint32_t IV0RR;      /*!< CRYP initialization vector right-word register 0,         Address offset: 0x44 */
-  __IO uint32_t IV1LR;      /*!< CRYP initialization vector left-word  register 1,         Address offset: 0x48 */
-  __IO uint32_t IV1RR;      /*!< CRYP initialization vector right-word register 1,         Address offset: 0x4C */
-  __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0,        Address offset: 0x50 */
-  __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1,        Address offset: 0x54 */
-  __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2,        Address offset: 0x58 */
-  __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3,        Address offset: 0x5C */
-  __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4,        Address offset: 0x60 */
-  __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5,        Address offset: 0x64 */
-  __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6,        Address offset: 0x68 */
-  __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7,        Address offset: 0x6C */
-  __IO uint32_t CSGCM0R;    /*!< CRYP GCM/GMAC context swap register 0,                    Address offset: 0x70 */
-  __IO uint32_t CSGCM1R;    /*!< CRYP GCM/GMAC context swap register 1,                    Address offset: 0x74 */
-  __IO uint32_t CSGCM2R;    /*!< CRYP GCM/GMAC context swap register 2,                    Address offset: 0x78 */
-  __IO uint32_t CSGCM3R;    /*!< CRYP GCM/GMAC context swap register 3,                    Address offset: 0x7C */
-  __IO uint32_t CSGCM4R;    /*!< CRYP GCM/GMAC context swap register 4,                    Address offset: 0x80 */
-  __IO uint32_t CSGCM5R;    /*!< CRYP GCM/GMAC context swap register 5,                    Address offset: 0x84 */
-  __IO uint32_t CSGCM6R;    /*!< CRYP GCM/GMAC context swap register 6,                    Address offset: 0x88 */
-  __IO uint32_t CSGCM7R;    /*!< CRYP GCM/GMAC context swap register 7,                    Address offset: 0x8C */
-} CRYP_TypeDef;
-
-/** 
-  * @brief HASH
-  */
-  
-typedef struct 
-{
-  __IO uint32_t CR;               /*!< HASH control register,          Address offset: 0x00        */
-  __IO uint32_t DIN;              /*!< HASH data input register,       Address offset: 0x04        */
-  __IO uint32_t STR;              /*!< HASH start register,            Address offset: 0x08        */
-  __IO uint32_t HR[5];            /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */
-  __IO uint32_t IMR;              /*!< HASH interrupt enable register, Address offset: 0x20        */
-  __IO uint32_t SR;               /*!< HASH status register,           Address offset: 0x24        */
-       uint32_t RESERVED[52];     /*!< Reserved, 0x28-0xF4                                         */
-  __IO uint32_t CSR[54];          /*!< HASH context swap registers,    Address offset: 0x0F8-0x1CC */
-} HASH_TypeDef;
-
-/** 
-  * @brief HASH_DIGEST
-  */
-
-typedef struct 
-{
-  __IO uint32_t HR[8];     /*!< HASH digest registers,          Address offset: 0x310-0x32C */ 
-} HASH_DIGEST_TypeDef;
-
-/** 
-  * @brief RNG
-  */
-  
-typedef struct 
-{
-  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
-  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
-  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
-} RNG_TypeDef;
-
- 
-/** 
-  * @brief USB_OTG_Core_Registers
-  */
-typedef struct
-{
- __IO uint32_t GOTGCTL;               /*!< USB_OTG Control and Status Register          000h */
-  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */
-  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */
-  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */
-  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */
-  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */
-  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */
-  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */
-  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */
-  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */
-  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */
-  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */
-  uint32_t Reserved30[2];             /*!< Reserved                                     030h */
-  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */
-  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */
-  uint32_t  Reserved5[3];             /*!< Reserved                                040h-048h */
-  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */
-  uint32_t  Reserved6;                /*!< Reserved                                     050h */ 
-  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */
-  uint32_t  Reserved;                 /*!< Reserved                                     058h */
-  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */
-  uint32_t  Reserved43[40];           /*!< Reserved                                058h-0FFh */
-  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */
-  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */
-} USB_OTG_GlobalTypeDef;
-
-/** 
-  * @brief USB_OTG_device_Registers
-  */
-typedef struct 
-{
-  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */
-  __IO uint32_t DCTL;            /*!< dev Control Register         804h */
-  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */
-  uint32_t Reserved0C;           /*!< Reserved                     80Ch */
-  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */
-  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */
-  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */
-  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */
-  uint32_t  Reserved20;          /*!< Reserved                     820h */
-  uint32_t Reserved9;            /*!< Reserved                     824h */
-  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */
-  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */
-  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */
-  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */
-  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */
-  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */  
-  uint32_t Reserved40;           /*!< dedicated EP mask            840h */
-  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */
-  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */
-  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */   
-} USB_OTG_DeviceTypeDef;
-
-/** 
-  * @brief USB_OTG_IN_Endpoint-Specific_Register
-  */
-typedef struct 
-{
-  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */
-  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */
-  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */
-  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */
-  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */
-  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */
-  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
-  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
-} USB_OTG_INEndpointTypeDef;
-
-/** 
-  * @brief USB_OTG_OUT_Endpoint-Specific_Registers
-  */
-typedef struct 
-{
-  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */
-  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */
-  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */
-  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */
-  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */
-  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */
-  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
-} USB_OTG_OUTEndpointTypeDef;
-
-/** 
-  * @brief USB_OTG_Host_Mode_Register_Structures
-  */
-typedef struct 
-{
-  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */
-  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */
-  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */
-  uint32_t Reserved40C;           /*!< Reserved                             40Ch */
-  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */
-  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */
-  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */
-} USB_OTG_HostTypeDef;
-
-/** 
-  * @brief USB_OTG_Host_Channel_Specific_Registers
-  */
-typedef struct
-{
-  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */
-  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */
-  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */
-  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */
-  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */
-  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */
-  uint32_t Reserved[2];           /*!< Reserved                                      */
-} USB_OTG_HostChannelTypeDef;
-
-/**
-  * @}
-  */
-    
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-#define FLASH_BASE            0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region                         */
-#define CCMDATARAM_BASE       0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
-#define SRAM1_BASE            0x20000000U /*!< SRAM1(160 KB) base address in the alias region                             */
-#define SRAM2_BASE            0x20028000U /*!< SRAM2(32 KB) base address in the alias region                              */
-#define SRAM3_BASE            0x20030000U /*!< SRAM3(128 KB) base address in the alias region                              */
-#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region                                */
-#define BKPSRAM_BASE          0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region                         */
-#define FMC_R_BASE            0xA0000000U /*!< FMC registers base address                                                 */
-#define QSPI_R_BASE           0xA0001000U /*!< QuadSPI registers base address                                            */
-#define SRAM1_BB_BASE         0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region                             */
-#define SRAM2_BB_BASE         0x22500000U /*!< SRAM2(16 KB) base address in the bit-band region                              */
-#define SRAM3_BB_BASE         0x22600000U /*!< SRAM3(64 KB) base address in the bit-band region                              */
-#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region                                */
-#define BKPSRAM_BB_BASE       0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region                         */
-#define FLASH_END             0x081FFFFFU /*!< FLASH end address */
-#define CCMDATARAM_END        0x1000FFFFU /*!< CCM data RAM end address */
-
-/* Legacy defines */
-#define SRAM_BASE             SRAM1_BASE
-#define SRAM_BB_BASE          SRAM1_BB_BASE
-
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000U)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)
-#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800U)
-#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00U)
-#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000U)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)
-#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400U)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)
-#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000U)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800U)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00U)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x5000U)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)
-#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)
-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)
-#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800U)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)
-#define UART7_BASE            (APB1PERIPH_BASE + 0x7800U)
-#define UART8_BASE            (APB1PERIPH_BASE + 0x7C00U)
-
-/*!< APB2 peripherals */
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000U)
-#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400U)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x1000U)
-#define USART6_BASE           (APB2PERIPH_BASE + 0x1400U)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000U)
-#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100U)
-#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200U)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x2300U)
-#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00U)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)
-#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400U)
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800U)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00U)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000U)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400U)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800U)
-#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000U)
-#define SPI6_BASE             (APB2PERIPH_BASE + 0x5400U)
-#define SAI1_BASE             (APB2PERIPH_BASE + 0x5800U)
-#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004U)
-#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024U)
-#define LTDC_BASE             (APB2PERIPH_BASE + 0x6800U)
-#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84U)
-#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104U)
-#define DSI_BASE              (APB2PERIPH_BASE + 0x6C00U)
-
-/*!< AHB1 peripherals */
-#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000U)
-#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400U)
-#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800U)
-#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00U)
-#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000U)
-#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400U)
-#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800U)
-#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00U)
-#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000U)
-#define GPIOJ_BASE            (AHB1PERIPH_BASE + 0x2400U)
-#define GPIOK_BASE            (AHB1PERIPH_BASE + 0x2800U)
-#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)
-#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800U)
-#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00U)
-#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000U)
-#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010U)
-#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028U)
-#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040U)
-#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058U)
-#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070U)
-#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088U)
-#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0U)
-#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8U)
-#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400U)
-#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010U)
-#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028U)
-#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040U)
-#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058U)
-#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070U)
-#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088U)
-#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0U)
-#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)
-#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000U)
-#define ETH_MAC_BASE          (ETH_BASE)
-#define ETH_MMC_BASE          (ETH_BASE + 0x0100U)
-#define ETH_PTP_BASE          (ETH_BASE + 0x0700U)
-#define ETH_DMA_BASE          (ETH_BASE + 0x1000U)
-#define DMA2D_BASE            (AHB1PERIPH_BASE + 0xB000U)
-
-/*!< AHB2 peripherals */
-#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000U)
-#define CRYP_BASE             (AHB2PERIPH_BASE + 0x60000U)
-#define HASH_BASE             (AHB2PERIPH_BASE + 0x60400U)
-#define HASH_DIGEST_BASE      (AHB2PERIPH_BASE + 0x60710U)
-#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800U)
-
-/*!< FMC Bankx registers base address */
-#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000U)
-#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104U)
-#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080U)
-#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140U)
-
-/*!< Debug MCU registers base address */
-#define DBGMCU_BASE           0xE0042000U
-
-/*!< USB registers base address */
-#define USB_OTG_HS_PERIPH_BASE               0x40040000U
-#define USB_OTG_FS_PERIPH_BASE               0x50000000U
-
-#define USB_OTG_GLOBAL_BASE                  0x000U
-#define USB_OTG_DEVICE_BASE                  0x800U
-#define USB_OTG_IN_ENDPOINT_BASE             0x900U
-#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U
-#define USB_OTG_EP_REG_SIZE                  0x20U
-#define USB_OTG_HOST_BASE                    0x400U
-#define USB_OTG_HOST_PORT_BASE               0x440U
-#define USB_OTG_HOST_CHANNEL_BASE            0x500U
-#define USB_OTG_HOST_CHANNEL_SIZE            0x20U
-#define USB_OTG_PCGCCTL_BASE                 0xE00U
-#define USB_OTG_FIFO_BASE                    0x1000U
-#define USB_OTG_FIFO_SIZE                    0x1000U
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
-#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
-#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define UART4               ((USART_TypeDef *) UART4_BASE)
-#define UART5               ((USART_TypeDef *) UART5_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
-#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
-#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
-#define UART7               ((USART_TypeDef *) UART7_BASE)
-#define UART8               ((USART_TypeDef *) UART8_BASE)
-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
-#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define USART6              ((USART_TypeDef *) USART6_BASE)
-#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
-#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
-#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE) 
-#define SPI4                ((SPI_TypeDef *) SPI4_BASE)
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-#define SPI5                ((SPI_TypeDef *) SPI5_BASE)
-#define SPI6                ((SPI_TypeDef *) SPI6_BASE)
-#define SAI1                ((SAI_TypeDef *) SAI1_BASE)
-#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
-#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
-#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)
-#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
-#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
-#define DSI                 ((DSI_TypeDef *)DSI_BASE)
-
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
-#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)
-#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
-#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
-#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
-#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
-#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
-#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
-#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
-#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
-#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
-#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
-#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
-#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
-#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
-#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
-#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
-#define ETH                 ((ETH_TypeDef *) ETH_BASE)  
-#define DMA2D               ((DMA2D_TypeDef *)DMA2D_BASE)
-#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
-#define CRYP                ((CRYP_TypeDef *) CRYP_BASE)
-#define HASH                ((HASH_TypeDef *) HASH_BASE)
-#define HASH_DIGEST         ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
-#define RNG                 ((RNG_TypeDef *) RNG_BASE)
-#define FMC_Bank1           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
-#define FMC_Bank1E          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
-#define FMC_Bank3           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
-#define FMC_Bank5_6         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
-#define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)
-
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
-#define USB_OTG_HS          ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers_Bits_Definition               */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Analog to Digital Converter                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          0x00000001U        /*!<Analog watchdog flag */
-#define  ADC_SR_EOC                          0x00000002U        /*!<End of conversion */
-#define  ADC_SR_JEOC                         0x00000004U        /*!<Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        0x00000008U        /*!<Injected channel Start flag */
-#define  ADC_SR_STRT                         0x00000010U        /*!<Regular channel Start flag */
-#define  ADC_SR_OVR                          0x00000020U        /*!<Overrun flag */
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
-#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels */
-#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels */
-#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution) */
-#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
-  
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion */
-#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode */
-#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC) */
-#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection */
-#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment */
-#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      0xFFFFU            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      0xFFFFU            /*!<Injected data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag */
-#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion */
-#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag */
-#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag */
-#define  ADC_CSR_OVR1                        0x00000020U        /*!<ADC1 DMA overrun  flag */
-#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag */
-#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion */
-#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag */
-#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag */
-#define  ADC_CSR_OVR2                        0x00002000U        /*!<ADC2 DMA overrun  flag */
-#define  ADC_CSR_AWD3                        0x00010000U        /*!<ADC3 Analog watchdog flag */
-#define  ADC_CSR_EOC3                        0x00020000U        /*!<ADC3 End of conversion */
-#define  ADC_CSR_JEOC3                       0x00040000U        /*!<ADC3 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT3                      0x00080000U        /*!<ADC3 Injected channel Start flag */
-#define  ADC_CSR_STRT3                       0x00100000U        /*!<ADC3 Regular channel Start flag */
-#define  ADC_CSR_OVR3                        0x00200000U        /*!<ADC3 DMA overrun  flag */
-
-/* Legacy defines */
-#define  ADC_CSR_DOVR1                        ADC_CSR_OVR1
-#define  ADC_CSR_DOVR2                        ADC_CSR_OVR2
-#define  ADC_CSR_DOVR3                        ADC_CSR_OVR3
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
-#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
-#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
-#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
-#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
-
-/*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                      0x0000FFFFU         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                      0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Controller Area Network                            */
-/*                                                                            */
-/******************************************************************************/
-/*!<CAN control and status registers */
-/*******************  Bit definition for CAN_MCR register  ********************/
-#define  CAN_MCR_INRQ                        0x00000001U        /*!<Initialization Request */
-#define  CAN_MCR_SLEEP                       0x00000002U        /*!<Sleep Mode Request */
-#define  CAN_MCR_TXFP                        0x00000004U        /*!<Transmit FIFO Priority */
-#define  CAN_MCR_RFLM                        0x00000008U        /*!<Receive FIFO Locked Mode */
-#define  CAN_MCR_NART                        0x00000010U        /*!<No Automatic Retransmission */
-#define  CAN_MCR_AWUM                        0x00000020U        /*!<Automatic Wakeup Mode */
-#define  CAN_MCR_ABOM                        0x00000040U        /*!<Automatic Bus-Off Management */
-#define  CAN_MCR_TTCM                        0x00000080U        /*!<Time Triggered Communication Mode */
-#define  CAN_MCR_RESET                       0x00008000U        /*!<bxCAN software master reset */
-#define  CAN_MCR_DBF                         0x00010000U        /*!<bxCAN Debug freeze */
-/*******************  Bit definition for CAN_MSR register  ********************/
-#define  CAN_MSR_INAK                        0x0001U            /*!<Initialization Acknowledge */
-#define  CAN_MSR_SLAK                        0x0002U            /*!<Sleep Acknowledge */
-#define  CAN_MSR_ERRI                        0x0004U            /*!<Error Interrupt */
-#define  CAN_MSR_WKUI                        0x0008U            /*!<Wakeup Interrupt */
-#define  CAN_MSR_SLAKI                       0x0010U            /*!<Sleep Acknowledge Interrupt */
-#define  CAN_MSR_TXM                         0x0100U            /*!<Transmit Mode */
-#define  CAN_MSR_RXM                         0x0200U            /*!<Receive Mode */
-#define  CAN_MSR_SAMP                        0x0400U            /*!<Last Sample Point */
-#define  CAN_MSR_RX                          0x0800U            /*!<CAN Rx Signal */
-
-/*******************  Bit definition for CAN_TSR register  ********************/
-#define  CAN_TSR_RQCP0                       0x00000001U        /*!<Request Completed Mailbox0 */
-#define  CAN_TSR_TXOK0                       0x00000002U        /*!<Transmission OK of Mailbox0 */
-#define  CAN_TSR_ALST0                       0x00000004U        /*!<Arbitration Lost for Mailbox0 */
-#define  CAN_TSR_TERR0                       0x00000008U        /*!<Transmission Error of Mailbox0 */
-#define  CAN_TSR_ABRQ0                       0x00000080U        /*!<Abort Request for Mailbox0 */
-#define  CAN_TSR_RQCP1                       0x00000100U        /*!<Request Completed Mailbox1 */
-#define  CAN_TSR_TXOK1                       0x00000200U        /*!<Transmission OK of Mailbox1 */
-#define  CAN_TSR_ALST1                       0x00000400U        /*!<Arbitration Lost for Mailbox1 */
-#define  CAN_TSR_TERR1                       0x00000800U        /*!<Transmission Error of Mailbox1 */
-#define  CAN_TSR_ABRQ1                       0x00008000U        /*!<Abort Request for Mailbox 1 */
-#define  CAN_TSR_RQCP2                       0x00010000U        /*!<Request Completed Mailbox2 */
-#define  CAN_TSR_TXOK2                       0x00020000U        /*!<Transmission OK of Mailbox 2 */
-#define  CAN_TSR_ALST2                       0x00040000U        /*!<Arbitration Lost for mailbox 2 */
-#define  CAN_TSR_TERR2                       0x00080000U        /*!<Transmission Error of Mailbox 2 */
-#define  CAN_TSR_ABRQ2                       0x00800000U        /*!<Abort Request for Mailbox 2 */
-#define  CAN_TSR_CODE                        0x03000000U        /*!<Mailbox Code */
-
-#define  CAN_TSR_TME                         0x1C000000U        /*!<TME[2:0] bits */
-#define  CAN_TSR_TME0                        0x04000000U        /*!<Transmit Mailbox 0 Empty */
-#define  CAN_TSR_TME1                        0x08000000U        /*!<Transmit Mailbox 1 Empty */
-#define  CAN_TSR_TME2                        0x10000000U        /*!<Transmit Mailbox 2 Empty */
-
-#define  CAN_TSR_LOW                         0xE0000000U        /*!<LOW[2:0] bits */
-#define  CAN_TSR_LOW0                        0x20000000U        /*!<Lowest Priority Flag for Mailbox 0 */
-#define  CAN_TSR_LOW1                        0x40000000U        /*!<Lowest Priority Flag for Mailbox 1 */
-#define  CAN_TSR_LOW2                        0x80000000U        /*!<Lowest Priority Flag for Mailbox 2 */
-
-/*******************  Bit definition for CAN_RF0R register  *******************/
-#define  CAN_RF0R_FMP0                       0x03U               /*!<FIFO 0 Message Pending */
-#define  CAN_RF0R_FULL0                      0x08U               /*!<FIFO 0 Full */
-#define  CAN_RF0R_FOVR0                      0x10U               /*!<FIFO 0 Overrun */
-#define  CAN_RF0R_RFOM0                      0x20U               /*!<Release FIFO 0 Output Mailbox */
-
-/*******************  Bit definition for CAN_RF1R register  *******************/
-#define  CAN_RF1R_FMP1                       0x03U               /*!<FIFO 1 Message Pending */
-#define  CAN_RF1R_FULL1                      0x08U               /*!<FIFO 1 Full */
-#define  CAN_RF1R_FOVR1                      0x10U               /*!<FIFO 1 Overrun */
-#define  CAN_RF1R_RFOM1                      0x20U               /*!<Release FIFO 1 Output Mailbox */
-
-/********************  Bit definition for CAN_IER register  *******************/
-#define  CAN_IER_TMEIE                       0x00000001U        /*!<Transmit Mailbox Empty Interrupt Enable */
-#define  CAN_IER_FMPIE0                      0x00000002U        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE0                       0x00000004U        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE0                      0x00000008U        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_FMPIE1                      0x00000010U        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE1                       0x00000020U        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE1                      0x00000040U        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error Warning Interrupt Enable */
-#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error Passive Interrupt Enable */
-#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-Off Interrupt Enable */
-#define  CAN_IER_LECIE                       0x00000800U        /*!<Last Error Code Interrupt Enable */
-#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error Interrupt Enable */
-#define  CAN_IER_WKUIE                       0x00010000U        /*!<Wakeup Interrupt Enable */
-#define  CAN_IER_SLKIE                       0x00020000U        /*!<Sleep Interrupt Enable */
-#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error warning interrupt enable */
-#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error passive interrupt enable */
-#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-off interrupt enable */
-#define  CAN_IER_LECIE                       0x00000800U        /*!<Last error code interrupt enable */
-#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error interrupt enable */
-
-
-/********************  Bit definition for CAN_ESR register  *******************/
-#define  CAN_ESR_EWGF                        0x00000001U        /*!<Error Warning Flag */
-#define  CAN_ESR_EPVF                        0x00000002U        /*!<Error Passive Flag */
-#define  CAN_ESR_BOFF                        0x00000004U        /*!<Bus-Off Flag */
-
-#define  CAN_ESR_LEC                         0x00000070U        /*!<LEC[2:0] bits (Last Error Code) */
-#define  CAN_ESR_LEC_0                       0x00000010U        /*!<Bit 0 */
-#define  CAN_ESR_LEC_1                       0x00000020U        /*!<Bit 1 */
-#define  CAN_ESR_LEC_2                       0x00000040U        /*!<Bit 2 */
-
-#define  CAN_ESR_TEC                         0x00FF0000U        /*!<Least significant byte of the 9-bit Transmit Error Counter */
-#define  CAN_ESR_REC                         0xFF000000U        /*!<Receive Error Counter */
-
-/*******************  Bit definition for CAN_BTR register  ********************/
-#define  CAN_BTR_BRP                         0x000003FFU        /*!<Baud Rate Prescaler */
-#define  CAN_BTR_TS1                         0x000F0000U        /*!<Time Segment 1 */
-#define  CAN_BTR_TS1_0                       0x00010000U        /*!<Bit 0 */
-#define  CAN_BTR_TS1_1                       0x00020000U        /*!<Bit 1 */
-#define  CAN_BTR_TS1_2                       0x00040000U        /*!<Bit 2 */
-#define  CAN_BTR_TS1_3                       0x00080000U        /*!<Bit 3 */
-#define  CAN_BTR_TS2                         0x00700000U        /*!<Time Segment 2 */
-#define  CAN_BTR_TS2_0                       0x00100000U        /*!<Bit 0 */
-#define  CAN_BTR_TS2_1                       0x00200000U        /*!<Bit 1 */
-#define  CAN_BTR_TS2_2                       0x00400000U        /*!<Bit 2 */
-#define  CAN_BTR_SJW                         0x03000000U        /*!<Resynchronization Jump Width */
-#define  CAN_BTR_SJW_0                       0x01000000U        /*!<Bit 0 */
-#define  CAN_BTR_SJW_1                       0x02000000U        /*!<Bit 1 */
-#define  CAN_BTR_LBKM                        0x40000000U        /*!<Loop Back Mode (Debug) */
-#define  CAN_BTR_SILM                        0x80000000U        /*!<Silent Mode */
-
-
-/*!<Mailbox registers */
-/******************  Bit definition for CAN_TI0R register  ********************/
-#define  CAN_TI0R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI0R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_TI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/******************  Bit definition for CAN_TDT0R register  *******************/
-#define  CAN_TDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT0R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/******************  Bit definition for CAN_TDL0R register  *******************/
-#define  CAN_TDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/******************  Bit definition for CAN_TDH0R register  *******************/
-#define  CAN_TDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI1R register  *******************/
-#define  CAN_TI1R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI1R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI1R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_TI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT1R register  ******************/
-#define  CAN_TDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT1R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL1R register  ******************/
-#define  CAN_TDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH1R register  ******************/
-#define  CAN_TDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI2R register  *******************/
-#define  CAN_TI2R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
-#define  CAN_TI2R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_TI2R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_TI2R_EXID                       0x001FFFF8U        /*!<Extended identifier */
-#define  CAN_TI2R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT2R register  ******************/  
-#define  CAN_TDT2R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_TDT2R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT2R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL2R register  ******************/
-#define  CAN_TDL2R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL2R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL2R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL2R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH2R register  ******************/
-#define  CAN_TDH2R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH2R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH2R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH2R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI0R register  *******************/
-#define  CAN_RI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_RI0R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_RI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
-#define  CAN_RI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT0R register  ******************/
-#define  CAN_RDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_RDT0R_FMI                       0x0000FF00U        /*!<Filter Match Index */
-#define  CAN_RDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL0R register  ******************/
-#define  CAN_RDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_RDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_RDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_RDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH0R register  ******************/
-#define  CAN_RDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_RDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_RDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_RDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI1R register  *******************/
-#define  CAN_RI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
-#define  CAN_RI1R_IDE                        0x00000004U        /*!<Identifier Extension */
-#define  CAN_RI1R_EXID                       0x001FFFF8U        /*!<Extended identifier */
-#define  CAN_RI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT1R register  ******************/
-#define  CAN_RDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_RDT1R_FMI                       0x0000FF00U        /*!<Filter Match Index */
-#define  CAN_RDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL1R register  ******************/
-#define  CAN_RDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_RDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_RDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_RDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH1R register  ******************/
-#define  CAN_RDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_RDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_RDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_RDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*!<CAN filter registers */
-/*******************  Bit definition for CAN_FMR register  ********************/
-#define  CAN_FMR_FINIT                       0x01U               /*!<Filter Init Mode */
-#define  CAN_FMR_CAN2SB                      0x00003F00U        /*!<CAN2 start bank */
-
-/*******************  Bit definition for CAN_FM1R register  *******************/
-#define  CAN_FM1R_FBM                        0x0FFFFFFFU        /*!<Filter Mode */
-#define  CAN_FM1R_FBM0                       0x00000001U        /*!<Filter Init Mode bit 0 */
-#define  CAN_FM1R_FBM1                       0x00000002U        /*!<Filter Init Mode bit 1 */
-#define  CAN_FM1R_FBM2                       0x00000004U        /*!<Filter Init Mode bit 2 */
-#define  CAN_FM1R_FBM3                       0x00000008U        /*!<Filter Init Mode bit 3 */
-#define  CAN_FM1R_FBM4                       0x00000010U        /*!<Filter Init Mode bit 4 */
-#define  CAN_FM1R_FBM5                       0x00000020U        /*!<Filter Init Mode bit 5 */
-#define  CAN_FM1R_FBM6                       0x00000040U        /*!<Filter Init Mode bit 6 */
-#define  CAN_FM1R_FBM7                       0x00000080U        /*!<Filter Init Mode bit 7 */
-#define  CAN_FM1R_FBM8                       0x00000100U        /*!<Filter Init Mode bit 8 */
-#define  CAN_FM1R_FBM9                       0x00000200U        /*!<Filter Init Mode bit 9 */
-#define  CAN_FM1R_FBM10                      0x00000400U        /*!<Filter Init Mode bit 10 */
-#define  CAN_FM1R_FBM11                      0x00000800U        /*!<Filter Init Mode bit 11 */
-#define  CAN_FM1R_FBM12                      0x00001000U        /*!<Filter Init Mode bit 12 */
-#define  CAN_FM1R_FBM13                      0x00002000U        /*!<Filter Init Mode bit 13 */
-#define  CAN_FM1R_FBM14                      0x00004000U        /*!<Filter Init Mode bit 14 */
-#define  CAN_FM1R_FBM15                      0x00008000U        /*!<Filter Init Mode bit 15 */
-#define  CAN_FM1R_FBM16                      0x00010000U        /*!<Filter Init Mode bit 16 */
-#define  CAN_FM1R_FBM17                      0x00020000U        /*!<Filter Init Mode bit 17 */
-#define  CAN_FM1R_FBM18                      0x00040000U        /*!<Filter Init Mode bit 18 */
-#define  CAN_FM1R_FBM19                      0x00080000U        /*!<Filter Init Mode bit 19 */
-#define  CAN_FM1R_FBM20                      0x00100000U        /*!<Filter Init Mode bit 20 */
-#define  CAN_FM1R_FBM21                      0x00200000U        /*!<Filter Init Mode bit 21 */
-#define  CAN_FM1R_FBM22                      0x00400000U        /*!<Filter Init Mode bit 22 */
-#define  CAN_FM1R_FBM23                      0x00800000U        /*!<Filter Init Mode bit 23 */
-#define  CAN_FM1R_FBM24                      0x01000000U        /*!<Filter Init Mode bit 24 */
-#define  CAN_FM1R_FBM25                      0x02000000U        /*!<Filter Init Mode bit 25 */
-#define  CAN_FM1R_FBM26                      0x04000000U        /*!<Filter Init Mode bit 26 */
-#define  CAN_FM1R_FBM27                      0x08000000U        /*!<Filter Init Mode bit 27 */
-
-/*******************  Bit definition for CAN_FS1R register  *******************/
-#define  CAN_FS1R_FSC                        0x0FFFFFFFU        /*!<Filter Scale Configuration */
-#define  CAN_FS1R_FSC0                       0x00000001U        /*!<Filter Scale Configuration bit 0 */
-#define  CAN_FS1R_FSC1                       0x00000002U        /*!<Filter Scale Configuration bit 1 */
-#define  CAN_FS1R_FSC2                       0x00000004U        /*!<Filter Scale Configuration bit 2 */
-#define  CAN_FS1R_FSC3                       0x00000008U        /*!<Filter Scale Configuration bit 3 */
-#define  CAN_FS1R_FSC4                       0x00000010U        /*!<Filter Scale Configuration bit 4 */
-#define  CAN_FS1R_FSC5                       0x00000020U        /*!<Filter Scale Configuration bit 5 */
-#define  CAN_FS1R_FSC6                       0x00000040U        /*!<Filter Scale Configuration bit 6 */
-#define  CAN_FS1R_FSC7                       0x00000080U        /*!<Filter Scale Configuration bit 7 */
-#define  CAN_FS1R_FSC8                       0x00000100U        /*!<Filter Scale Configuration bit 8 */
-#define  CAN_FS1R_FSC9                       0x00000200U        /*!<Filter Scale Configuration bit 9 */
-#define  CAN_FS1R_FSC10                      0x00000400U        /*!<Filter Scale Configuration bit 10 */
-#define  CAN_FS1R_FSC11                      0x00000800U        /*!<Filter Scale Configuration bit 11 */
-#define  CAN_FS1R_FSC12                      0x00001000U        /*!<Filter Scale Configuration bit 12 */
-#define  CAN_FS1R_FSC13                      0x00002000U        /*!<Filter Scale Configuration bit 13 */
-#define  CAN_FS1R_FSC14                      0x00004000U        /*!<Filter Scale Configuration bit 14 */
-#define  CAN_FS1R_FSC15                      0x00008000U        /*!<Filter Scale Configuration bit 15 */
-#define  CAN_FS1R_FSC16                      0x00010000U        /*!<Filter Scale Configuration bit 16 */
-#define  CAN_FS1R_FSC17                      0x00020000U        /*!<Filter Scale Configuration bit 17 */
-#define  CAN_FS1R_FSC18                      0x00040000U        /*!<Filter Scale Configuration bit 18 */
-#define  CAN_FS1R_FSC19                      0x00080000U        /*!<Filter Scale Configuration bit 19 */
-#define  CAN_FS1R_FSC20                      0x00100000U        /*!<Filter Scale Configuration bit 20 */
-#define  CAN_FS1R_FSC21                      0x00200000U        /*!<Filter Scale Configuration bit 21 */
-#define  CAN_FS1R_FSC22                      0x00400000U        /*!<Filter Scale Configuration bit 22 */
-#define  CAN_FS1R_FSC23                      0x00800000U        /*!<Filter Scale Configuration bit 23 */
-#define  CAN_FS1R_FSC24                      0x01000000U        /*!<Filter Scale Configuration bit 24 */
-#define  CAN_FS1R_FSC25                      0x02000000U        /*!<Filter Scale Configuration bit 25 */
-#define  CAN_FS1R_FSC26                      0x04000000U        /*!<Filter Scale Configuration bit 26 */
-#define  CAN_FS1R_FSC27                      0x08000000U        /*!<Filter Scale Configuration bit 27 */
-
-/******************  Bit definition for CAN_FFA1R register  *******************/
-#define  CAN_FFA1R_FFA                        0x0FFFFFFFU        /*!<Filter FIFO Assignment */
-#define  CAN_FFA1R_FFA0                       0x00000001U        /*!<Filter FIFO Assignment bit 0 */
-#define  CAN_FFA1R_FFA1                       0x00000002U        /*!<Filter FIFO Assignment bit 1 */
-#define  CAN_FFA1R_FFA2                       0x00000004U        /*!<Filter FIFO Assignment bit 2 */
-#define  CAN_FFA1R_FFA3                       0x00000008U        /*!<Filter FIFO Assignment bit 3 */
-#define  CAN_FFA1R_FFA4                       0x00000010U        /*!<Filter FIFO Assignment bit 4 */
-#define  CAN_FFA1R_FFA5                       0x00000020U        /*!<Filter FIFO Assignment bit 5 */
-#define  CAN_FFA1R_FFA6                       0x00000040U        /*!<Filter FIFO Assignment bit 6 */
-#define  CAN_FFA1R_FFA7                       0x00000080U        /*!<Filter FIFO Assignment bit 7 */
-#define  CAN_FFA1R_FFA8                       0x00000100U        /*!<Filter FIFO Assignment bit 8 */
-#define  CAN_FFA1R_FFA9                       0x00000200U        /*!<Filter FIFO Assignment bit 9 */
-#define  CAN_FFA1R_FFA10                      0x00000400U        /*!<Filter FIFO Assignment bit 10 */
-#define  CAN_FFA1R_FFA11                      0x00000800U        /*!<Filter FIFO Assignment bit 11 */
-#define  CAN_FFA1R_FFA12                      0x00001000U        /*!<Filter FIFO Assignment bit 12 */
-#define  CAN_FFA1R_FFA13                      0x00002000U        /*!<Filter FIFO Assignment bit 13 */
-#define  CAN_FFA1R_FFA14                      0x00004000U        /*!<Filter FIFO Assignment bit 14 */
-#define  CAN_FFA1R_FFA15                      0x00008000U        /*!<Filter FIFO Assignment bit 15 */
-#define  CAN_FFA1R_FFA16                      0x00010000U        /*!<Filter FIFO Assignment bit 16 */
-#define  CAN_FFA1R_FFA17                      0x00020000U        /*!<Filter FIFO Assignment bit 17 */
-#define  CAN_FFA1R_FFA18                      0x00040000U        /*!<Filter FIFO Assignment bit 18 */
-#define  CAN_FFA1R_FFA19                      0x00080000U        /*!<Filter FIFO Assignment bit 19 */
-#define  CAN_FFA1R_FFA20                      0x00100000U        /*!<Filter FIFO Assignment bit 20 */
-#define  CAN_FFA1R_FFA21                      0x00200000U        /*!<Filter FIFO Assignment bit 21 */
-#define  CAN_FFA1R_FFA22                      0x00400000U        /*!<Filter FIFO Assignment bit 22 */
-#define  CAN_FFA1R_FFA23                      0x00800000U        /*!<Filter FIFO Assignment bit 23 */
-#define  CAN_FFA1R_FFA24                      0x01000000U        /*!<Filter FIFO Assignment bit 24 */
-#define  CAN_FFA1R_FFA25                      0x02000000U        /*!<Filter FIFO Assignment bit 25 */
-#define  CAN_FFA1R_FFA26                      0x04000000U        /*!<Filter FIFO Assignment bit 26 */
-#define  CAN_FFA1R_FFA27                      0x08000000U        /*!<Filter FIFO Assignment bit 27 */
-
-/*******************  Bit definition for CAN_FA1R register  *******************/
-#define  CAN_FA1R_FACT                        0x0FFFFFFFU        /*!<Filter Active */
-#define  CAN_FA1R_FACT0                       0x00000001U        /*!<Filter Active bit 0 */
-#define  CAN_FA1R_FACT1                       0x00000002U        /*!<Filter Active bit 1 */
-#define  CAN_FA1R_FACT2                       0x00000004U        /*!<Filter Active bit 2 */
-#define  CAN_FA1R_FACT3                       0x00000008U        /*!<Filter Active bit 3 */
-#define  CAN_FA1R_FACT4                       0x00000010U        /*!<Filter Active bit 4 */
-#define  CAN_FA1R_FACT5                       0x00000020U        /*!<Filter Active bit 5 */
-#define  CAN_FA1R_FACT6                       0x00000040U        /*!<Filter Active bit 6 */
-#define  CAN_FA1R_FACT7                       0x00000080U        /*!<Filter Active bit 7 */
-#define  CAN_FA1R_FACT8                       0x00000100U        /*!<Filter Active bit 8 */
-#define  CAN_FA1R_FACT9                       0x00000200U        /*!<Filter Active bit 9 */
-#define  CAN_FA1R_FACT10                      0x00000400U        /*!<Filter Active bit 10 */
-#define  CAN_FA1R_FACT11                      0x00000800U        /*!<Filter Active bit 11 */
-#define  CAN_FA1R_FACT12                      0x00001000U        /*!<Filter Active bit 12 */
-#define  CAN_FA1R_FACT13                      0x00002000U        /*!<Filter Active bit 13 */
-#define  CAN_FA1R_FACT14                      0x00004000U        /*!<Filter Active bit 14 */
-#define  CAN_FA1R_FACT15                      0x00008000U        /*!<Filter Active bit 15 */
-#define  CAN_FA1R_FACT16                      0x00010000U        /*!<Filter Active bit 16 */
-#define  CAN_FA1R_FACT17                      0x00020000U        /*!<Filter Active bit 17 */
-#define  CAN_FA1R_FACT18                      0x00040000U        /*!<Filter Active bit 18 */
-#define  CAN_FA1R_FACT19                      0x00080000U        /*!<Filter Active bit 19 */
-#define  CAN_FA1R_FACT20                      0x00100000U        /*!<Filter Active bit 20 */
-#define  CAN_FA1R_FACT21                      0x00200000U        /*!<Filter Active bit 21 */
-#define  CAN_FA1R_FACT22                      0x00400000U        /*!<Filter Active bit 22 */
-#define  CAN_FA1R_FACT23                      0x00800000U        /*!<Filter Active bit 23 */
-#define  CAN_FA1R_FACT24                      0x01000000U        /*!<Filter Active bit 24 */
-#define  CAN_FA1R_FACT25                      0x02000000U        /*!<Filter Active bit 25 */
-#define  CAN_FA1R_FACT26                      0x04000000U        /*!<Filter Active bit 26 */
-#define  CAN_FA1R_FACT27                      0x08000000U        /*!<Filter Active bit 27 */
-
-
-/*******************  Bit definition for CAN_F0R1 register  *******************/
-#define  CAN_F0R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F0R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F0R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F0R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F0R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F0R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F0R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F0R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F0R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F0R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F0R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F0R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F0R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F0R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F0R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F0R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F0R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F0R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F0R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F0R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F0R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F0R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F0R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F0R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F0R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F0R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F0R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F0R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F0R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F0R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F0R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F0R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R1 register  *******************/
-#define  CAN_F1R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F1R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F1R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F1R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F1R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F1R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F1R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F1R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F1R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F1R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F1R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F1R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F1R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F1R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F1R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F1R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F1R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F1R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F1R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F1R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F1R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F1R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F1R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F1R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F1R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F1R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F1R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F1R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F1R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F1R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F1R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F1R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R1 register  *******************/
-#define  CAN_F2R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F2R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F2R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F2R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F2R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F2R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F2R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F2R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F2R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F2R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F2R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F2R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F2R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F2R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F2R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F2R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F2R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F2R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F2R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F2R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F2R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F2R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F2R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F2R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F2R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F2R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F2R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F2R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F2R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F2R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F2R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F2R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R1 register  *******************/
-#define  CAN_F3R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F3R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F3R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F3R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F3R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F3R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F3R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F3R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F3R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F3R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F3R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F3R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F3R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F3R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F3R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F3R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F3R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F3R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F3R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F3R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F3R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F3R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F3R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F3R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F3R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F3R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F3R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F3R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F3R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F3R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F3R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F3R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R1 register  *******************/
-#define  CAN_F4R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F4R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F4R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F4R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F4R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F4R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F4R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F4R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F4R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F4R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F4R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F4R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F4R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F4R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F4R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F4R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F4R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F4R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F4R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F4R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F4R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F4R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F4R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F4R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F4R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F4R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F4R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F4R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F4R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F4R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F4R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F4R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R1 register  *******************/
-#define  CAN_F5R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F5R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F5R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F5R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F5R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F5R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F5R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F5R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F5R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F5R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F5R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F5R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F5R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F5R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F5R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F5R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F5R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F5R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F5R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F5R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F5R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F5R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F5R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F5R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F5R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F5R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F5R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F5R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F5R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F5R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F5R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F5R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R1 register  *******************/
-#define  CAN_F6R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F6R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F6R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F6R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F6R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F6R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F6R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F6R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F6R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F6R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F6R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F6R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F6R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F6R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F6R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F6R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F6R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F6R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F6R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F6R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F6R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F6R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F6R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F6R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F6R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F6R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F6R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F6R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F6R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F6R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F6R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F6R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R1 register  *******************/
-#define  CAN_F7R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F7R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F7R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F7R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F7R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F7R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F7R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F7R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F7R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F7R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F7R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F7R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F7R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F7R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F7R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F7R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F7R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F7R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F7R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F7R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F7R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F7R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F7R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F7R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F7R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F7R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F7R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F7R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F7R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F7R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F7R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F7R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R1 register  *******************/
-#define  CAN_F8R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F8R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F8R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F8R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F8R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F8R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F8R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F8R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F8R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F8R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F8R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F8R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F8R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F8R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F8R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F8R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F8R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F8R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F8R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F8R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F8R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F8R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F8R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F8R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F8R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F8R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F8R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F8R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F8R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F8R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F8R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F8R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R1 register  *******************/
-#define  CAN_F9R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F9R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F9R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F9R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F9R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F9R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F9R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F9R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F9R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F9R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F9R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F9R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F9R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F9R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F9R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F9R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F9R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F9R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F9R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F9R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F9R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F9R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F9R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F9R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F9R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F9R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F9R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F9R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F9R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F9R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F9R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F9R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R1 register  ******************/
-#define  CAN_F10R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F10R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F10R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F10R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F10R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F10R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F10R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F10R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F10R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F10R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F10R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F10R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F10R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F10R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F10R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F10R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F10R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F10R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F10R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F10R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F10R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F10R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F10R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F10R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F10R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F10R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F10R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F10R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F10R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F10R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F10R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F10R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R1 register  ******************/
-#define  CAN_F11R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F11R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F11R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F11R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F11R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F11R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F11R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F11R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F11R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F11R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F11R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F11R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F11R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F11R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F11R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F11R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F11R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F11R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F11R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F11R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F11R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F11R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F11R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F11R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F11R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F11R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F11R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F11R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F11R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F11R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F11R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F11R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R1 register  ******************/
-#define  CAN_F12R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F12R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F12R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F12R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F12R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F12R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F12R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F12R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F12R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F12R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F12R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F12R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F12R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F12R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F12R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F12R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F12R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F12R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F12R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F12R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F12R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F12R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F12R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F12R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F12R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F12R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F12R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F12R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F12R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F12R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F12R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F12R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R1 register  ******************/
-#define  CAN_F13R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F13R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F13R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F13R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F13R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F13R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F13R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F13R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F13R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F13R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F13R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F13R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F13R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F13R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F13R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F13R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F13R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F13R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F13R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F13R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F13R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F13R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F13R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F13R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F13R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F13R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F13R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F13R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F13R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F13R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F13R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F13R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F0R2 register  *******************/
-#define  CAN_F0R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F0R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F0R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F0R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F0R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F0R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F0R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F0R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F0R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F0R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F0R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F0R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F0R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F0R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F0R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F0R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F0R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F0R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F0R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F0R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F0R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F0R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F0R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F0R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F0R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F0R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F0R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F0R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F0R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F0R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F0R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F0R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R2 register  *******************/
-#define  CAN_F1R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F1R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F1R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F1R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F1R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F1R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F1R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F1R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F1R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F1R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F1R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F1R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F1R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F1R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F1R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F1R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F1R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F1R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F1R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F1R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F1R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F1R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F1R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F1R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F1R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F1R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F1R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F1R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F1R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F1R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F1R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F1R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R2 register  *******************/
-#define  CAN_F2R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F2R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F2R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F2R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F2R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F2R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F2R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F2R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F2R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F2R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F2R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F2R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F2R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F2R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F2R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F2R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F2R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F2R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F2R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F2R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F2R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F2R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F2R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F2R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F2R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F2R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F2R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F2R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F2R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F2R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F2R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F2R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R2 register  *******************/
-#define  CAN_F3R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F3R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F3R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F3R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F3R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F3R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F3R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F3R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F3R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F3R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F3R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F3R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F3R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F3R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F3R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F3R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F3R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F3R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F3R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F3R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F3R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F3R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F3R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F3R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F3R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F3R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F3R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F3R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F3R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F3R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F3R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F3R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R2 register  *******************/
-#define  CAN_F4R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F4R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F4R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F4R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F4R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F4R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F4R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F4R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F4R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F4R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F4R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F4R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F4R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F4R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F4R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F4R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F4R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F4R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F4R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F4R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F4R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F4R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F4R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F4R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F4R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F4R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F4R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F4R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F4R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F4R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F4R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F4R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R2 register  *******************/
-#define  CAN_F5R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F5R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F5R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F5R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F5R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F5R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F5R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F5R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F5R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F5R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F5R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F5R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F5R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F5R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F5R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F5R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F5R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F5R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F5R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F5R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F5R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F5R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F5R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F5R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F5R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F5R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F5R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F5R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F5R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F5R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F5R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F5R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R2 register  *******************/
-#define  CAN_F6R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F6R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F6R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F6R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F6R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F6R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F6R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F6R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F6R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F6R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F6R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F6R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F6R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F6R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F6R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F6R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F6R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F6R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F6R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F6R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F6R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F6R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F6R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F6R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F6R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F6R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F6R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F6R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F6R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F6R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F6R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F6R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R2 register  *******************/
-#define  CAN_F7R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F7R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F7R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F7R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F7R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F7R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F7R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F7R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F7R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F7R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F7R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F7R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F7R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F7R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F7R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F7R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F7R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F7R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F7R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F7R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F7R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F7R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F7R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F7R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F7R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F7R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F7R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F7R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F7R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F7R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F7R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F7R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R2 register  *******************/
-#define  CAN_F8R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F8R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F8R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F8R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F8R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F8R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F8R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F8R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F8R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F8R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F8R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F8R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F8R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F8R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F8R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F8R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F8R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F8R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F8R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F8R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F8R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F8R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F8R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F8R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F8R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F8R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F8R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F8R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F8R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F8R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F8R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F8R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R2 register  *******************/
-#define  CAN_F9R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F9R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F9R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F9R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F9R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F9R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F9R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F9R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F9R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F9R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F9R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F9R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F9R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F9R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F9R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F9R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F9R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F9R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F9R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F9R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F9R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F9R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F9R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F9R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F9R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F9R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F9R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F9R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F9R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F9R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F9R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F9R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R2 register  ******************/
-#define  CAN_F10R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F10R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F10R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F10R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F10R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F10R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F10R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F10R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F10R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F10R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F10R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F10R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F10R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F10R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F10R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F10R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F10R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F10R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F10R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F10R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F10R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F10R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F10R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F10R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F10R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F10R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F10R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F10R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F10R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F10R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F10R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F10R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R2 register  ******************/
-#define  CAN_F11R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F11R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F11R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F11R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F11R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F11R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F11R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F11R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F11R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F11R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F11R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F11R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F11R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F11R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F11R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F11R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F11R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F11R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F11R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F11R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F11R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F11R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F11R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F11R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F11R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F11R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F11R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F11R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F11R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F11R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F11R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F11R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R2 register  ******************/
-#define  CAN_F12R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F12R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F12R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F12R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F12R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F12R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F12R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F12R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F12R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F12R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F12R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F12R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F12R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F12R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F12R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F12R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F12R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F12R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F12R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F12R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F12R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F12R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F12R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F12R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F12R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F12R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F12R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F12R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F12R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F12R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F12R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F12R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R2 register  ******************/
-#define  CAN_F13R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F13R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F13R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F13R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F13R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F13R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F13R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F13R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F13R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F13R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F13R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F13R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F13R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F13R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F13R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F13R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F13R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F13R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F13R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F13R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F13R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F13R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F13R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F13R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F13R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F13R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F13R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F13R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F13R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F13R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F13R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F13R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRC calculation unit                              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           0xFFFFFFFFU /*!< Data register bits */
-
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         0xFFU        /*!< General-purpose 8-bit data register bits */
-
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        0x01U        /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Crypto Processor                                */
-/*                                                                            */
-/******************************************************************************/
-/******************* Bits definition for CRYP_CR register  ********************/
-#define CRYP_CR_ALGODIR                      0x00000004U
-
-#define CRYP_CR_ALGOMODE                     0x00080038U
-#define CRYP_CR_ALGOMODE_0                   0x00000008U
-#define CRYP_CR_ALGOMODE_1                   0x00000010U
-#define CRYP_CR_ALGOMODE_2                   0x00000020U
-#define CRYP_CR_ALGOMODE_TDES_ECB            0x00000000U
-#define CRYP_CR_ALGOMODE_TDES_CBC            0x00000008U
-#define CRYP_CR_ALGOMODE_DES_ECB             0x00000010U
-#define CRYP_CR_ALGOMODE_DES_CBC             0x00000018U
-#define CRYP_CR_ALGOMODE_AES_ECB             0x00000020U
-#define CRYP_CR_ALGOMODE_AES_CBC             0x00000028U
-#define CRYP_CR_ALGOMODE_AES_CTR             0x00000030U
-#define CRYP_CR_ALGOMODE_AES_KEY             0x00000038U
-
-#define CRYP_CR_DATATYPE                     0x000000C0U
-#define CRYP_CR_DATATYPE_0                   0x00000040U
-#define CRYP_CR_DATATYPE_1                   0x00000080U
-#define CRYP_CR_KEYSIZE                      0x00000300U
-#define CRYP_CR_KEYSIZE_0                    0x00000100U
-#define CRYP_CR_KEYSIZE_1                    0x00000200U
-#define CRYP_CR_FFLUSH                       0x00004000U
-#define CRYP_CR_CRYPEN                       0x00008000U
-
-#define CRYP_CR_GCM_CCMPH                    0x00030000U
-#define CRYP_CR_GCM_CCMPH_0                  0x00010000U
-#define CRYP_CR_GCM_CCMPH_1                  0x00020000U
-#define CRYP_CR_ALGOMODE_3                   0x00080000U 
-
-/****************** Bits definition for CRYP_SR register  *********************/
-#define CRYP_SR_IFEM                         0x00000001U
-#define CRYP_SR_IFNF                         0x00000002U
-#define CRYP_SR_OFNE                         0x00000004U
-#define CRYP_SR_OFFU                         0x00000008U
-#define CRYP_SR_BUSY                         0x00000010U
-/****************** Bits definition for CRYP_DMACR register  ******************/
-#define CRYP_DMACR_DIEN                      0x00000001U
-#define CRYP_DMACR_DOEN                      0x00000002U
-/*****************  Bits definition for CRYP_IMSCR register  ******************/
-#define CRYP_IMSCR_INIM                      0x00000001U
-#define CRYP_IMSCR_OUTIM                     0x00000002U
-/****************** Bits definition for CRYP_RISR register  *******************/
-#define CRYP_RISR_OUTRIS                     0x00000001U
-#define CRYP_RISR_INRIS                      0x00000002U
-/****************** Bits definition for CRYP_MISR register  *******************/
-#define CRYP_MISR_INMIS                      0x00000001U
-#define CRYP_MISR_OUTMIS                     0x00000002U
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Digital to Analog Converter                           */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DAC_CR register  ********************/
-#define  DAC_CR_EN1                          0x00000001U        /*!<DAC channel1 enable */
-#define  DAC_CR_BOFF1                        0x00000002U        /*!<DAC channel1 output buffer disable */
-#define  DAC_CR_TEN1                         0x00000004U        /*!<DAC channel1 Trigger enable */
-
-#define  DAC_CR_TSEL1                        0x00000038U        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define  DAC_CR_TSEL1_0                      0x00000008U        /*!<Bit 0 */
-#define  DAC_CR_TSEL1_1                      0x00000010U        /*!<Bit 1 */
-#define  DAC_CR_TSEL1_2                      0x00000020U        /*!<Bit 2 */
-
-#define  DAC_CR_WAVE1                        0x000000C0U        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE1_0                      0x00000040U        /*!<Bit 0 */
-#define  DAC_CR_WAVE1_1                      0x00000080U        /*!<Bit 1 */
-
-#define  DAC_CR_MAMP1                        0x00000F00U        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP1_0                      0x00000100U        /*!<Bit 0 */
-#define  DAC_CR_MAMP1_1                      0x00000200U        /*!<Bit 1 */
-#define  DAC_CR_MAMP1_2                      0x00000400U        /*!<Bit 2 */
-#define  DAC_CR_MAMP1_3                      0x00000800U        /*!<Bit 3 */
-
-#define  DAC_CR_DMAEN1                       0x00001000U        /*!<DAC channel1 DMA enable */
-#define  DAC_CR_DMAUDRIE1                    0x00002000U        /*!<DAC channel1 DMA underrun interrupt enable*/
-#define  DAC_CR_EN2                          0x00010000U        /*!<DAC channel2 enable */
-#define  DAC_CR_BOFF2                        0x00020000U        /*!<DAC channel2 output buffer disable */
-#define  DAC_CR_TEN2                         0x00040000U        /*!<DAC channel2 Trigger enable */
-
-#define  DAC_CR_TSEL2                        0x00380000U        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define  DAC_CR_TSEL2_0                      0x00080000U        /*!<Bit 0 */
-#define  DAC_CR_TSEL2_1                      0x00100000U        /*!<Bit 1 */
-#define  DAC_CR_TSEL2_2                      0x00200000U        /*!<Bit 2 */
-
-#define  DAC_CR_WAVE2                        0x00C00000U        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE2_0                      0x00400000U        /*!<Bit 0 */
-#define  DAC_CR_WAVE2_1                      0x00800000U        /*!<Bit 1 */
-
-#define  DAC_CR_MAMP2                        0x0F000000U        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP2_0                      0x01000000U        /*!<Bit 0 */
-#define  DAC_CR_MAMP2_1                      0x02000000U        /*!<Bit 1 */
-#define  DAC_CR_MAMP2_2                      0x04000000U        /*!<Bit 2 */
-#define  DAC_CR_MAMP2_3                      0x08000000U        /*!<Bit 3 */
-
-#define  DAC_CR_DMAEN2                       0x10000000U        /*!<DAC channel2 DMA enabled */
-#define  DAC_CR_DMAUDRIE2                    0x20000000U        /*!<DAC channel2 DMA underrun interrupt enable*/
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define  DAC_SWTRIGR_SWTRIG1                 0x01U               /*!<DAC channel1 software trigger */
-#define  DAC_SWTRIGR_SWTRIG2                 0x02U               /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define  DAC_DHR12R1_DACC1DHR                0x0FFFU            /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define  DAC_DHR12L1_DACC1DHR                0xFFF0U            /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define  DAC_DHR8R1_DACC1DHR                 0xFFU               /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define  DAC_DHR12R2_DACC2DHR                0x0FFFU            /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define  DAC_DHR12L2_DACC2DHR                0xFFF0U            /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define  DAC_DHR8R2_DACC2DHR                 0xFFU               /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define  DAC_DHR12RD_DACC1DHR                0x00000FFFU        /*!<DAC channel1 12-bit Right aligned data */
-#define  DAC_DHR12RD_DACC2DHR                0x0FFF0000U        /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define  DAC_DHR12LD_DACC1DHR                0x0000FFF0U        /*!<DAC channel1 12-bit Left aligned data */
-#define  DAC_DHR12LD_DACC2DHR                0xFFF00000U        /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define  DAC_DHR8RD_DACC1DHR                 0x00FFU            /*!<DAC channel1 8-bit Right aligned data */
-#define  DAC_DHR8RD_DACC2DHR                 0xFF00U            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define  DAC_DOR1_DACC1DOR                   0x0FFFU            /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define  DAC_DOR2_DACC2DOR                   0x0FFFU            /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define  DAC_SR_DMAUDR1                      0x00002000U        /*!<DAC channel1 DMA underrun flag */
-#define  DAC_SR_DMAUDR2                      0x20000000U        /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 Debug MCU                                  */
-/*                                                                            */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    DCMI                                    */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DCMI_CR register  ******************/
-#define DCMI_CR_CAPTURE                      0x00000001U
-#define DCMI_CR_CM                           0x00000002U
-#define DCMI_CR_CROP                         0x00000004U
-#define DCMI_CR_JPEG                         0x00000008U
-#define DCMI_CR_ESS                          0x00000010U
-#define DCMI_CR_PCKPOL                       0x00000020U
-#define DCMI_CR_HSPOL                        0x00000040U
-#define DCMI_CR_VSPOL                        0x00000080U
-#define DCMI_CR_FCRC_0                       0x00000100U
-#define DCMI_CR_FCRC_1                       0x00000200U
-#define DCMI_CR_EDM_0                        0x00000400U
-#define DCMI_CR_EDM_1                        0x00000800U
-#define DCMI_CR_OUTEN                        0x00002000U
-#define DCMI_CR_ENABLE                       0x00004000U
-#define DCMI_CR_BSM_0                        0x00010000U
-#define DCMI_CR_BSM_1                        0x00020000U
-#define DCMI_CR_OEBS                         0x00040000U
-#define DCMI_CR_LSM                          0x00080000U
-#define DCMI_CR_OELS                         0x00100000U
-
-/********************  Bits definition for DCMI_SR register  ******************/
-#define DCMI_SR_HSYNC                        0x00000001U
-#define DCMI_SR_VSYNC                        0x00000002U
-#define DCMI_SR_FNE                          0x00000004U
-
-/********************  Bits definition for DCMI_RIS register  *****************/
-#define DCMI_RIS_FRAME_RIS                   0x00000001U
-#define DCMI_RIS_OVR_RIS                     0x00000002U
-#define DCMI_RIS_ERR_RIS                     0x00000004U
-#define DCMI_RIS_VSYNC_RIS                   0x00000008U
-#define DCMI_RIS_LINE_RIS                    0x00000010U
-/* Legacy defines */
-#define DCMI_RISR_FRAME_RIS                  DCMI_RIS_FRAME_RIS
-#define DCMI_RISR_OVR_RIS                    DCMI_RIS_OVR_RIS
-#define DCMI_RISR_ERR_RIS                    DCMI_RIS_ERR_RIS
-#define DCMI_RISR_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS
-#define DCMI_RISR_LINE_RIS                   DCMI_RIS_LINE_RIS
-#define DCMI_RISR_OVF_RIS                    DCMI_RIS_OVR_RIS
-
-/********************  Bits definition for DCMI_IER register  *****************/
-#define DCMI_IER_FRAME_IE                    0x00000001U
-#define DCMI_IER_OVR_IE                      0x00000002U
-#define DCMI_IER_ERR_IE                      0x00000004U
-#define DCMI_IER_VSYNC_IE                    0x00000008U
-#define DCMI_IER_LINE_IE                     0x00000010U
-/* Legacy defines */
-#define DCMI_IER_OVF_IE                      DCMI_IER_OVR_IE
-
-/********************  Bits definition for DCMI_MIS register  *****************/
-#define DCMI_MIS_FRAME_MIS                   0x00000001U
-#define DCMI_MIS_OVR_MIS                     0x00000002U
-#define DCMI_MIS_ERR_MIS                     0x00000004U
-#define DCMI_MIS_VSYNC_MIS                   0x00000008U
-#define DCMI_MIS_LINE_MIS                    0x00000010U
-
-/* Legacy defines */
-#define DCMI_MISR_FRAME_MIS                  DCMI_MIS_FRAME_MIS
-#define DCMI_MISR_OVF_MIS                    DCMI_MIS_OVR_MIS
-#define DCMI_MISR_ERR_MIS                    DCMI_MIS_ERR_MIS
-#define DCMI_MISR_VSYNC_MIS                  DCMI_MIS_VSYNC_MIS
-#define DCMI_MISR_LINE_MIS                   DCMI_MIS_LINE_MIS
-
-/********************  Bits definition for DCMI_ICR register  *****************/
-#define DCMI_ICR_FRAME_ISC                   0x00000001U
-#define DCMI_ICR_OVR_ISC                     0x00000002U
-#define DCMI_ICR_ERR_ISC                     0x00000004U
-#define DCMI_ICR_VSYNC_ISC                   0x00000008U
-#define DCMI_ICR_LINE_ISC                    0x00000010U
-
-/* Legacy defines */
-#define DCMI_ICR_OVF_ISC                     DCMI_ICR_OVR_ISC
-
-/********************  Bits definition for DCMI_ESCR register  ******************/
-#define DCMI_ESCR_FSC                        0x000000FFU
-#define DCMI_ESCR_LSC                        0x0000FF00U
-#define DCMI_ESCR_LEC                        0x00FF0000U
-#define DCMI_ESCR_FEC                        0xFF000000U
-
-/********************  Bits definition for DCMI_ESUR register  ******************/
-#define DCMI_ESUR_FSU                        0x000000FFU
-#define DCMI_ESUR_LSU                        0x0000FF00U
-#define DCMI_ESUR_LEU                        0x00FF0000U
-#define DCMI_ESUR_FEU                        0xFF000000U
-
-/********************  Bits definition for DCMI_CWSTRT register  ******************/
-#define DCMI_CWSTRT_HOFFCNT                  0x00003FFFU
-#define DCMI_CWSTRT_VST                      0x1FFF0000U
-
-/********************  Bits definition for DCMI_CWSIZE register  ******************/
-#define DCMI_CWSIZE_CAPCNT                   0x00003FFFU
-#define DCMI_CWSIZE_VLINE                    0x3FFF0000U
-
-/********************  Bits definition for DCMI_DR register  *********************/
-#define DCMI_DR_BYTE0                        0x000000FFU
-#define DCMI_DR_BYTE1                        0x0000FF00U
-#define DCMI_DR_BYTE2                        0x00FF0000U
-#define DCMI_DR_BYTE3                        0xFF000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                             DMA Controller                                 */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DMA_SxCR register  *****************/
-#define DMA_SxCR_CHSEL                       0x0E000000U
-#define DMA_SxCR_CHSEL_0                     0x02000000U
-#define DMA_SxCR_CHSEL_1                     0x04000000U
-#define DMA_SxCR_CHSEL_2                     0x08000000U
-#define DMA_SxCR_MBURST                      0x01800000U
-#define DMA_SxCR_MBURST_0                    0x00800000U
-#define DMA_SxCR_MBURST_1                    0x01000000U
-#define DMA_SxCR_PBURST                      0x00600000U
-#define DMA_SxCR_PBURST_0                    0x00200000U
-#define DMA_SxCR_PBURST_1                    0x00400000U
-#define DMA_SxCR_CT                          0x00080000U
-#define DMA_SxCR_DBM                         0x00040000U
-#define DMA_SxCR_PL                          0x00030000U
-#define DMA_SxCR_PL_0                        0x00010000U
-#define DMA_SxCR_PL_1                        0x00020000U
-#define DMA_SxCR_PINCOS                      0x00008000U
-#define DMA_SxCR_MSIZE                       0x00006000U
-#define DMA_SxCR_MSIZE_0                     0x00002000U
-#define DMA_SxCR_MSIZE_1                     0x00004000U
-#define DMA_SxCR_PSIZE                       0x00001800U
-#define DMA_SxCR_PSIZE_0                     0x00000800U
-#define DMA_SxCR_PSIZE_1                     0x00001000U
-#define DMA_SxCR_MINC                        0x00000400U
-#define DMA_SxCR_PINC                        0x00000200U
-#define DMA_SxCR_CIRC                        0x00000100U
-#define DMA_SxCR_DIR                         0x000000C0U
-#define DMA_SxCR_DIR_0                       0x00000040U
-#define DMA_SxCR_DIR_1                       0x00000080U
-#define DMA_SxCR_PFCTRL                      0x00000020U
-#define DMA_SxCR_TCIE                        0x00000010U
-#define DMA_SxCR_HTIE                        0x00000008U
-#define DMA_SxCR_TEIE                        0x00000004U
-#define DMA_SxCR_DMEIE                       0x00000002U
-#define DMA_SxCR_EN                          0x00000001U
-
-/* Legacy defines */
-#define DMA_SxCR_ACK                         0x00100000U
-
-/********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            0x0000FFFFU
-#define DMA_SxNDT_0                          0x00000001U
-#define DMA_SxNDT_1                          0x00000002U
-#define DMA_SxNDT_2                          0x00000004U
-#define DMA_SxNDT_3                          0x00000008U
-#define DMA_SxNDT_4                          0x00000010U
-#define DMA_SxNDT_5                          0x00000020U
-#define DMA_SxNDT_6                          0x00000040U
-#define DMA_SxNDT_7                          0x00000080U
-#define DMA_SxNDT_8                          0x00000100U
-#define DMA_SxNDT_9                          0x00000200U
-#define DMA_SxNDT_10                         0x00000400U
-#define DMA_SxNDT_11                         0x00000800U
-#define DMA_SxNDT_12                         0x00001000U
-#define DMA_SxNDT_13                         0x00002000U
-#define DMA_SxNDT_14                         0x00004000U
-#define DMA_SxNDT_15                         0x00008000U
-
-/********************  Bits definition for DMA_SxFCR register  ****************/ 
-#define DMA_SxFCR_FEIE                       0x00000080U
-#define DMA_SxFCR_FS                         0x00000038U
-#define DMA_SxFCR_FS_0                       0x00000008U
-#define DMA_SxFCR_FS_1                       0x00000010U
-#define DMA_SxFCR_FS_2                       0x00000020U
-#define DMA_SxFCR_DMDIS                      0x00000004U
-#define DMA_SxFCR_FTH                        0x00000003U
-#define DMA_SxFCR_FTH_0                      0x00000001U
-#define DMA_SxFCR_FTH_1                      0x00000002U
-
-/********************  Bits definition for DMA_LISR register  *****************/ 
-#define DMA_LISR_TCIF3                       0x08000000U
-#define DMA_LISR_HTIF3                       0x04000000U
-#define DMA_LISR_TEIF3                       0x02000000U
-#define DMA_LISR_DMEIF3                      0x01000000U
-#define DMA_LISR_FEIF3                       0x00400000U
-#define DMA_LISR_TCIF2                       0x00200000U
-#define DMA_LISR_HTIF2                       0x00100000U
-#define DMA_LISR_TEIF2                       0x00080000U
-#define DMA_LISR_DMEIF2                      0x00040000U
-#define DMA_LISR_FEIF2                       0x00010000U
-#define DMA_LISR_TCIF1                       0x00000800U
-#define DMA_LISR_HTIF1                       0x00000400U
-#define DMA_LISR_TEIF1                       0x00000200U
-#define DMA_LISR_DMEIF1                      0x00000100U
-#define DMA_LISR_FEIF1                       0x00000040U
-#define DMA_LISR_TCIF0                       0x00000020U
-#define DMA_LISR_HTIF0                       0x00000010U
-#define DMA_LISR_TEIF0                       0x00000008U
-#define DMA_LISR_DMEIF0                      0x00000004U
-#define DMA_LISR_FEIF0                       0x00000001U
-
-/********************  Bits definition for DMA_HISR register  *****************/ 
-#define DMA_HISR_TCIF7                       0x08000000U
-#define DMA_HISR_HTIF7                       0x04000000U
-#define DMA_HISR_TEIF7                       0x02000000U
-#define DMA_HISR_DMEIF7                      0x01000000U
-#define DMA_HISR_FEIF7                       0x00400000U
-#define DMA_HISR_TCIF6                       0x00200000U
-#define DMA_HISR_HTIF6                       0x00100000U
-#define DMA_HISR_TEIF6                       0x00080000U
-#define DMA_HISR_DMEIF6                      0x00040000U
-#define DMA_HISR_FEIF6                       0x00010000U
-#define DMA_HISR_TCIF5                       0x00000800U
-#define DMA_HISR_HTIF5                       0x00000400U
-#define DMA_HISR_TEIF5                       0x00000200U
-#define DMA_HISR_DMEIF5                      0x00000100U
-#define DMA_HISR_FEIF5                       0x00000040U
-#define DMA_HISR_TCIF4                       0x00000020U
-#define DMA_HISR_HTIF4                       0x00000010U
-#define DMA_HISR_TEIF4                       0x00000008U
-#define DMA_HISR_DMEIF4                      0x00000004U
-#define DMA_HISR_FEIF4                       0x00000001U
-
-/********************  Bits definition for DMA_LIFCR register  ****************/ 
-#define DMA_LIFCR_CTCIF3                     0x08000000U
-#define DMA_LIFCR_CHTIF3                     0x04000000U
-#define DMA_LIFCR_CTEIF3                     0x02000000U
-#define DMA_LIFCR_CDMEIF3                    0x01000000U
-#define DMA_LIFCR_CFEIF3                     0x00400000U
-#define DMA_LIFCR_CTCIF2                     0x00200000U
-#define DMA_LIFCR_CHTIF2                     0x00100000U
-#define DMA_LIFCR_CTEIF2                     0x00080000U
-#define DMA_LIFCR_CDMEIF2                    0x00040000U
-#define DMA_LIFCR_CFEIF2                     0x00010000U
-#define DMA_LIFCR_CTCIF1                     0x00000800U
-#define DMA_LIFCR_CHTIF1                     0x00000400U
-#define DMA_LIFCR_CTEIF1                     0x00000200U
-#define DMA_LIFCR_CDMEIF1                    0x00000100U
-#define DMA_LIFCR_CFEIF1                     0x00000040U
-#define DMA_LIFCR_CTCIF0                     0x00000020U
-#define DMA_LIFCR_CHTIF0                     0x00000010U
-#define DMA_LIFCR_CTEIF0                     0x00000008U
-#define DMA_LIFCR_CDMEIF0                    0x00000004U
-#define DMA_LIFCR_CFEIF0                     0x00000001U
-
-/********************  Bits definition for DMA_HIFCR  register  ****************/ 
-#define DMA_HIFCR_CTCIF7                     0x08000000U
-#define DMA_HIFCR_CHTIF7                     0x04000000U
-#define DMA_HIFCR_CTEIF7                     0x02000000U
-#define DMA_HIFCR_CDMEIF7                    0x01000000U
-#define DMA_HIFCR_CFEIF7                     0x00400000U
-#define DMA_HIFCR_CTCIF6                     0x00200000U
-#define DMA_HIFCR_CHTIF6                     0x00100000U
-#define DMA_HIFCR_CTEIF6                     0x00080000U
-#define DMA_HIFCR_CDMEIF6                    0x00040000U
-#define DMA_HIFCR_CFEIF6                     0x00010000U
-#define DMA_HIFCR_CTCIF5                     0x00000800U
-#define DMA_HIFCR_CHTIF5                     0x00000400U
-#define DMA_HIFCR_CTEIF5                     0x00000200U
-#define DMA_HIFCR_CDMEIF5                    0x00000100U
-#define DMA_HIFCR_CFEIF5                     0x00000040U
-#define DMA_HIFCR_CTCIF4                     0x00000020U
-#define DMA_HIFCR_CHTIF4                     0x00000010U
-#define DMA_HIFCR_CTEIF4                     0x00000008U
-#define DMA_HIFCR_CDMEIF4                    0x00000004U
-#define DMA_HIFCR_CFEIF4                     0x00000001U
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                         AHB Master DMA2D Controller (DMA2D)                */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for DMA2D_CR register  ******************/
-
-#define DMA2D_CR_START                     0x00000001U               /*!< Start transfer */
-#define DMA2D_CR_SUSP                      0x00000002U               /*!< Suspend transfer */
-#define DMA2D_CR_ABORT                     0x00000004U               /*!< Abort transfer */
-#define DMA2D_CR_TEIE                      0x00000100U               /*!< Transfer Error Interrupt Enable */
-#define DMA2D_CR_TCIE                      0x00000200U               /*!< Transfer Complete Interrupt Enable */
-#define DMA2D_CR_TWIE                      0x00000400U               /*!< Transfer Watermark Interrupt Enable */
-#define DMA2D_CR_CAEIE                     0x00000800U               /*!< CLUT Access Error Interrupt Enable */
-#define DMA2D_CR_CTCIE                     0x00001000U               /*!< CLUT Transfer Complete Interrupt Enable */
-#define DMA2D_CR_CEIE                      0x00002000U               /*!< Configuration Error Interrupt Enable */
-#define DMA2D_CR_MODE                      0x00030000U               /*!< DMA2D Mode[1:0] */
-#define DMA2D_CR_MODE_0                    0x00010000U               /*!< DMA2D Mode bit 0 */
-#define DMA2D_CR_MODE_1                    0x00020000U               /*!< DMA2D Mode bit 1 */
-
-/********************  Bit definition for DMA2D_ISR register  *****************/
-
-#define DMA2D_ISR_TEIF                     0x00000001U               /*!< Transfer Error Interrupt Flag */
-#define DMA2D_ISR_TCIF                     0x00000002U               /*!< Transfer Complete Interrupt Flag */
-#define DMA2D_ISR_TWIF                     0x00000004U               /*!< Transfer Watermark Interrupt Flag */
-#define DMA2D_ISR_CAEIF                    0x00000008U               /*!< CLUT Access Error Interrupt Flag */
-#define DMA2D_ISR_CTCIF                    0x00000010U               /*!< CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_ISR_CEIF                     0x00000020U               /*!< Configuration Error Interrupt Flag */
-
-/********************  Bit definition for DMA2D_IFCR register  ****************/
-
-#define DMA2D_IFCR_CTEIF                   0x00000001U               /*!< Clears Transfer Error Interrupt Flag         */
-#define DMA2D_IFCR_CTCIF                   0x00000002U               /*!< Clears Transfer Complete Interrupt Flag      */
-#define DMA2D_IFCR_CTWIF                   0x00000004U               /*!< Clears Transfer Watermark Interrupt Flag     */
-#define DMA2D_IFCR_CAECIF                  0x00000008U               /*!< Clears CLUT Access Error Interrupt Flag      */
-#define DMA2D_IFCR_CCTCIF                  0x00000010U               /*!< Clears CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_IFCR_CCEIF                   0x00000020U               /*!< Clears Configuration Error Interrupt Flag    */
-
-/* Legacy defines */
-#define DMA2D_IFSR_CTEIF                   DMA2D_IFCR_CTEIF                     /*!< Clears Transfer Error Interrupt Flag         */
-#define DMA2D_IFSR_CTCIF                   DMA2D_IFCR_CTCIF                     /*!< Clears Transfer Complete Interrupt Flag      */
-#define DMA2D_IFSR_CTWIF                   DMA2D_IFCR_CTWIF                     /*!< Clears Transfer Watermark Interrupt Flag     */
-#define DMA2D_IFSR_CCAEIF                  DMA2D_IFCR_CAECIF                    /*!< Clears CLUT Access Error Interrupt Flag      */
-#define DMA2D_IFSR_CCTCIF                  DMA2D_IFCR_CCTCIF                    /*!< Clears CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_IFSR_CCEIF                   DMA2D_IFCR_CCEIF                     /*!< Clears Configuration Error Interrupt Flag    */
-
-/********************  Bit definition for DMA2D_FGMAR register  ***************/
-
-#define DMA2D_FGMAR_MA                     0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_FGOR register  ****************/
-
-#define DMA2D_FGOR_LO                      0x00003FFFU               /*!< Line Offset */
-
-/********************  Bit definition for DMA2D_BGMAR register  ***************/
-
-#define DMA2D_BGMAR_MA                     0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_BGOR register  ****************/
-
-#define DMA2D_BGOR_LO                      0x00003FFFU               /*!< Line Offset */
-
-/********************  Bit definition for DMA2D_FGPFCCR register  *************/
-
-#define DMA2D_FGPFCCR_CM                   0x0000000FU               /*!< Input color mode CM[3:0] */
-#define DMA2D_FGPFCCR_CM_0                 0x00000001U               /*!< Input color mode CM bit 0 */
-#define DMA2D_FGPFCCR_CM_1                 0x00000002U               /*!< Input color mode CM bit 1 */
-#define DMA2D_FGPFCCR_CM_2                 0x00000004U               /*!< Input color mode CM bit 2 */
-#define DMA2D_FGPFCCR_CM_3                 0x00000008U               /*!< Input color mode CM bit 3 */
-#define DMA2D_FGPFCCR_CCM                  0x00000010U               /*!< CLUT Color mode */
-#define DMA2D_FGPFCCR_START                0x00000020U               /*!< Start */
-#define DMA2D_FGPFCCR_CS                   0x0000FF00U               /*!< CLUT size */
-#define DMA2D_FGPFCCR_AM                   0x00030000U               /*!< Alpha mode AM[1:0] */
-#define DMA2D_FGPFCCR_AM_0                 0x00010000U               /*!< Alpha mode AM bit 0 */
-#define DMA2D_FGPFCCR_AM_1                 0x00020000U               /*!< Alpha mode AM bit 1 */
-#define DMA2D_FGPFCCR_ALPHA                0xFF000000U               /*!< Alpha value */
-
-/********************  Bit definition for DMA2D_FGCOLR register  **************/
-
-#define DMA2D_FGCOLR_BLUE                  0x000000FFU               /*!< Blue Value */
-#define DMA2D_FGCOLR_GREEN                 0x0000FF00U               /*!< Green Value */
-#define DMA2D_FGCOLR_RED                   0x00FF0000U               /*!< Red Value */   
-
-/********************  Bit definition for DMA2D_BGPFCCR register  *************/
-
-#define DMA2D_BGPFCCR_CM                   0x0000000FU               /*!< Input color mode CM[3:0] */
-#define DMA2D_BGPFCCR_CM_0                 0x00000001U               /*!< Input color mode CM bit 0 */
-#define DMA2D_BGPFCCR_CM_1                 0x00000002U               /*!< Input color mode CM bit 1 */
-#define DMA2D_BGPFCCR_CM_2                 0x00000004U               /*!< Input color mode CM bit 2 */
-#define DMA2D_FGPFCCR_CM_3                 0x00000008U               /*!< Input color mode CM bit 3 */
-#define DMA2D_BGPFCCR_CCM                  0x00000010U               /*!< CLUT Color mode */
-#define DMA2D_BGPFCCR_START                0x00000020U               /*!< Start */
-#define DMA2D_BGPFCCR_CS                   0x0000FF00U               /*!< CLUT size */
-#define DMA2D_BGPFCCR_AM                   0x00030000U               /*!< Alpha mode AM[1:0] */
-#define DMA2D_BGPFCCR_AM_0                 0x00010000U               /*!< Alpha mode AM bit 0 */
-#define DMA2D_BGPFCCR_AM_1                 0x00020000U               /*!< Alpha mode AM bit 1 */
-#define DMA2D_BGPFCCR_ALPHA                0xFF000000U               /*!< background Input Alpha value */
-
-/********************  Bit definition for DMA2D_BGCOLR register  **************/
-
-#define DMA2D_BGCOLR_BLUE                  0x000000FFU               /*!< Blue Value */
-#define DMA2D_BGCOLR_GREEN                 0x0000FF00U               /*!< Green Value */
-#define DMA2D_BGCOLR_RED                   0x00FF0000U               /*!< Red Value */
-
-/********************  Bit definition for DMA2D_FGCMAR register  **************/
-
-#define DMA2D_FGCMAR_MA                    0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_BGCMAR register  **************/
-
-#define DMA2D_BGCMAR_MA                    0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_OPFCCR register  **************/
-
-#define DMA2D_OPFCCR_CM                    0x00000007U               /*!< Color mode CM[2:0] */
-#define DMA2D_OPFCCR_CM_0                  0x00000001U               /*!< Color mode CM bit 0 */
-#define DMA2D_OPFCCR_CM_1                  0x00000002U               /*!< Color mode CM bit 1 */
-#define DMA2D_OPFCCR_CM_2                  0x00000004U               /*!< Color mode CM bit 2 */
-
-/********************  Bit definition for DMA2D_OCOLR register  ***************/
-
-/*!<Mode_ARGB8888/RGB888 */
-
-#define DMA2D_OCOLR_BLUE_1                 0x000000FFU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_1                0x0000FF00U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_1                  0x00FF0000U               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_1                0xFF000000U               /*!< Alpha Channel Value */
-
-/*!<Mode_RGB565 */
-#define DMA2D_OCOLR_BLUE_2                 0x0000001FU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_2                0x000007E0U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_2                  0x0000F800U               /*!< Red Value */
-
-/*!<Mode_ARGB1555 */
-#define DMA2D_OCOLR_BLUE_3                 0x0000001FU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_3                0x000003E0U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_3                  0x00007C00U               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_3                0x00008000U               /*!< Alpha Channel Value */
-
-/*!<Mode_ARGB4444 */
-#define DMA2D_OCOLR_BLUE_4                 0x0000000FU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_4                0x000000F0U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_4                  0x00000F00U               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_4                0x0000F000U               /*!< Alpha Channel Value */
-
-/********************  Bit definition for DMA2D_OMAR register  ****************/
-
-#define DMA2D_OMAR_MA                      0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_OOR register  *****************/
-
-#define DMA2D_OOR_LO                       0x00003FFFU               /*!< Line Offset */
-
-/********************  Bit definition for DMA2D_NLR register  *****************/
-
-#define DMA2D_NLR_NL                       0x0000FFFFU               /*!< Number of Lines */
-#define DMA2D_NLR_PL                       0x3FFF0000U               /*!< Pixel per Lines */
-
-/********************  Bit definition for DMA2D_LWR register  *****************/
-
-#define DMA2D_LWR_LW                       0x0000FFFFU               /*!< Line Watermark */
-
-/********************  Bit definition for DMA2D_AMTCR register  ***************/
-
-#define DMA2D_AMTCR_EN                     0x00000001U               /*!< Enable */
-#define DMA2D_AMTCR_DT                     0x0000FF00U               /*!< Dead Time */
-
-/********************  Bit definition for DMA2D_FGCLUT register  **************/
-                                                                     
-/********************  Bit definition for DMA2D_BGCLUT register  **************/
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Display Serial Interface (DSI)                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for DSI_VR register  *****************/
-#define DSI_VR                         0x3133302AU               /*!< DSI Host Version */
-
-/*******************  Bit definition for DSI_CR register  *****************/
-#define DSI_CR_EN                      0x00000001U               /*!< DSI Host power up and reset */
-
-/*******************  Bit definition for DSI_CCR register  ****************/
-#define DSI_CCR_TXECKDIV               0x000000FFU               /*!< TX Escape Clock Division */
-#define DSI_CCR_TXECKDIV0              0x00000001U
-#define DSI_CCR_TXECKDIV1              0x00000002U
-#define DSI_CCR_TXECKDIV2              0x00000004U
-#define DSI_CCR_TXECKDIV3              0x00000008U
-#define DSI_CCR_TXECKDIV4              0x00000010U
-#define DSI_CCR_TXECKDIV5              0x00000020U
-#define DSI_CCR_TXECKDIV6              0x00000040U
-#define DSI_CCR_TXECKDIV7              0x00000080U
-
-#define DSI_CCR_TOCKDIV                0x0000FF00U               /*!< Timeout Clock Division */
-#define DSI_CCR_TOCKDIV0               0x00000100U
-#define DSI_CCR_TOCKDIV1               0x00000200U
-#define DSI_CCR_TOCKDIV2               0x00000400U
-#define DSI_CCR_TOCKDIV3               0x00000800U
-#define DSI_CCR_TOCKDIV4               0x00001000U
-#define DSI_CCR_TOCKDIV5               0x00002000U
-#define DSI_CCR_TOCKDIV6               0x00004000U
-#define DSI_CCR_TOCKDIV7               0x00008000U
-
-/*******************  Bit definition for DSI_LVCIDR register  *************/
-#define DSI_LVCIDR_VCID                0x00000003U               /*!< Virtual Channel ID */
-#define DSI_LVCIDR_VCID0               0x00000001U
-#define DSI_LVCIDR_VCID1               0x00000002U
-
-/*******************  Bit definition for DSI_LCOLCR register  *************/
-#define DSI_LCOLCR_COLC                0x0000000FU               /*!< Color Coding */
-#define DSI_LCOLCR_COLC0               0x00000001U
-#define DSI_LCOLCR_COLC1               0x00000020U
-#define DSI_LCOLCR_COLC2               0x00000040U
-#define DSI_LCOLCR_COLC3               0x00000080U
-
-#define DSI_LCOLCR_LPE                 0x00000100U               /*!< Loosly Packet Enable */
-
-/*******************  Bit definition for DSI_LPCR register  ***************/
-#define DSI_LPCR_DEP                   0x00000001U               /*!< Data Enable Polarity */
-#define DSI_LPCR_VSP                   0x00000002U               /*!< VSYNC Polarity */
-#define DSI_LPCR_HSP                   0x00000004U               /*!< HSYNC Polarity */
-
-/*******************  Bit definition for DSI_LPMCR register  **************/
-#define DSI_LPMCR_VLPSIZE              0x000000FFU               /*!< VACT Largest Packet Size */
-#define DSI_LPMCR_VLPSIZE0             0x00000001U
-#define DSI_LPMCR_VLPSIZE1             0x00000002U
-#define DSI_LPMCR_VLPSIZE2             0x00000004U
-#define DSI_LPMCR_VLPSIZE3             0x00000008U
-#define DSI_LPMCR_VLPSIZE4             0x00000010U
-#define DSI_LPMCR_VLPSIZE5             0x00000020U
-#define DSI_LPMCR_VLPSIZE6             0x00000040U
-#define DSI_LPMCR_VLPSIZE7             0x00000080U
-
-#define DSI_LPMCR_LPSIZE               0x00FF0000U               /*!< Largest Packet Size */
-#define DSI_LPMCR_LPSIZE0              0x00010000U
-#define DSI_LPMCR_LPSIZE1              0x00020000U
-#define DSI_LPMCR_LPSIZE2              0x00040000U
-#define DSI_LPMCR_LPSIZE3              0x00080000U
-#define DSI_LPMCR_LPSIZE4              0x00100000U
-#define DSI_LPMCR_LPSIZE5              0x00200000U
-#define DSI_LPMCR_LPSIZE6              0x00400000U
-#define DSI_LPMCR_LPSIZE7              0x00800000U
-
-/*******************  Bit definition for DSI_PCR register  ****************/
-#define DSI_PCR_ETTXE                  0x00000001U               /*!< EoTp Transmission Enable */
-#define DSI_PCR_ETRXE                  0x00000002U               /*!< EoTp Reception Enable */
-#define DSI_PCR_BTAE                   0x00000004U               /*!< Bus Turn Around Enable */
-#define DSI_PCR_ECCRXE                 0x00000008U               /*!< ECC Reception Enable */
-#define DSI_PCR_CRCRXE                 0x00000010U               /*!< CRC Reception Enable */
-
-/*******************  Bit definition for DSI_GVCIDR register  *************/
-#define DSI_GVCIDR_VCID                0x00000003U               /*!< Virtual Channel ID */
-#define DSI_GVCIDR_VCID0               0x00000001U
-#define DSI_GVCIDR_VCID1               0x00000002U
-
-/*******************  Bit definition for DSI_MCR register  ****************/
-#define DSI_MCR_CMDM                   0x00000001U               /*!< Command Mode */
-
-/*******************  Bit definition for DSI_VMCR register  ***************/
-#define DSI_VMCR_VMT                   0x00000003U               /*!< Video Mode Type */
-#define DSI_VMCR_VMT0                  0x00000001U
-#define DSI_VMCR_VMT1                  0x00000002U
-
-#define DSI_VMCR_LPVSAE                0x00000100U               /*!< Low-Power Vertical Sync Active Enable */
-#define DSI_VMCR_LPVBPE                0x00000200U               /*!< Low-power Vertical Back-Porch Enable */
-#define DSI_VMCR_LPVFPE                0x00000400U               /*!< Low-power Vertical Front-porch Enable */
-#define DSI_VMCR_LPVAE                 0x00000800U               /*!< Low-Power Vertical Active Enable */
-#define DSI_VMCR_LPHBPE                0x00001000U               /*!< Low-Power Horizontal Back-Porch Enable */
-#define DSI_VMCR_LPHFPE                0x00002000U               /*!< Low-Power Horizontal Front-Porch Enable */
-#define DSI_VMCR_FBTAAE                0x00004000U               /*!< Frame Bus-Turn-Around Acknowledge Enable */
-#define DSI_VMCR_LPCE                  0x00008000U               /*!< Low-Power Command Enable */
-#define DSI_VMCR_PGE                   0x00010000U               /*!< Pattern Generator Enable */
-#define DSI_VMCR_PGM                   0x00100000U               /*!< Pattern Generator Mode */
-#define DSI_VMCR_PGO                   0x01000000U               /*!< Pattern Generator Orientation */
-
-/*******************  Bit definition for DSI_VPCR register  ***************/
-#define DSI_VPCR_VPSIZE                0x00003FFFU               /*!< Video Packet Size */
-#define DSI_VPCR_VPSIZE0               0x00000001U
-#define DSI_VPCR_VPSIZE1               0x00000002U
-#define DSI_VPCR_VPSIZE2               0x00000004U
-#define DSI_VPCR_VPSIZE3               0x00000008U
-#define DSI_VPCR_VPSIZE4               0x00000010U
-#define DSI_VPCR_VPSIZE5               0x00000020U
-#define DSI_VPCR_VPSIZE6               0x00000040U
-#define DSI_VPCR_VPSIZE7               0x00000080U
-#define DSI_VPCR_VPSIZE8               0x00000100U
-#define DSI_VPCR_VPSIZE9               0x00000200U
-#define DSI_VPCR_VPSIZE10              0x00000400U
-#define DSI_VPCR_VPSIZE11              0x00000800U
-#define DSI_VPCR_VPSIZE12              0x00001000U
-#define DSI_VPCR_VPSIZE13              0x00002000U
-
-/*******************  Bit definition for DSI_VCCR register  ***************/
-#define DSI_VCCR_NUMC                  0x00001FFFU               /*!< Number of Chunks */
-#define DSI_VCCR_NUMC0                 0x00000001U
-#define DSI_VCCR_NUMC1                 0x00000002U
-#define DSI_VCCR_NUMC2                 0x00000004U
-#define DSI_VCCR_NUMC3                 0x00000008U
-#define DSI_VCCR_NUMC4                 0x00000010U
-#define DSI_VCCR_NUMC5                 0x00000020U
-#define DSI_VCCR_NUMC6                 0x00000040U
-#define DSI_VCCR_NUMC7                 0x00000080U
-#define DSI_VCCR_NUMC8                 0x00000100U
-#define DSI_VCCR_NUMC9                 0x00000200U
-#define DSI_VCCR_NUMC10                0x00000400U
-#define DSI_VCCR_NUMC11                0x00000800U
-#define DSI_VCCR_NUMC12                0x00001000U
-
-/*******************  Bit definition for DSI_VNPCR register  **************/
-#define DSI_VNPCR_NPSIZE               0x00001FFFU               /*!< Null Packet Size */
-#define DSI_VNPCR_NPSIZE0              0x00000001U
-#define DSI_VNPCR_NPSIZE1              0x00000002U
-#define DSI_VNPCR_NPSIZE2              0x00000004U
-#define DSI_VNPCR_NPSIZE3              0x00000008U
-#define DSI_VNPCR_NPSIZE4              0x00000010U
-#define DSI_VNPCR_NPSIZE5              0x00000020U
-#define DSI_VNPCR_NPSIZE6              0x00000040U
-#define DSI_VNPCR_NPSIZE7              0x00000080U
-#define DSI_VNPCR_NPSIZE8              0x00000100U
-#define DSI_VNPCR_NPSIZE9              0x00000200U
-#define DSI_VNPCR_NPSIZE10             0x00000400U
-#define DSI_VNPCR_NPSIZE11             0x00000800U
-#define DSI_VNPCR_NPSIZE12             0x00001000U
-
-/*******************  Bit definition for DSI_VHSACR register  *************/
-#define DSI_VHSACR_HSA                 0x00000FFFU               /*!< Horizontal Synchronism Active duration */
-#define DSI_VHSACR_HSA0                0x00000001U
-#define DSI_VHSACR_HSA1                0x00000002U
-#define DSI_VHSACR_HSA2                0x00000004U
-#define DSI_VHSACR_HSA3                0x00000008U
-#define DSI_VHSACR_HSA4                0x00000010U
-#define DSI_VHSACR_HSA5                0x00000020U
-#define DSI_VHSACR_HSA6                0x00000040U
-#define DSI_VHSACR_HSA7                0x00000080U
-#define DSI_VHSACR_HSA8                0x00000100U
-#define DSI_VHSACR_HSA9                0x00000200U
-#define DSI_VHSACR_HSA10               0x00000400U
-#define DSI_VHSACR_HSA11               0x00000800U
-
-/*******************  Bit definition for DSI_VHBPCR register  *************/
-#define DSI_VHBPCR_HBP                 0x00000FFFU               /*!< Horizontal Back-Porch duration */
-#define DSI_VHBPCR_HBP0                0x00000001U
-#define DSI_VHBPCR_HBP1                0x00000002U
-#define DSI_VHBPCR_HBP2                0x00000004U
-#define DSI_VHBPCR_HBP3                0x00000008U
-#define DSI_VHBPCR_HBP4                0x00000010U
-#define DSI_VHBPCR_HBP5                0x00000020U
-#define DSI_VHBPCR_HBP6                0x00000040U
-#define DSI_VHBPCR_HBP7                0x00000080U
-#define DSI_VHBPCR_HBP8                0x00000100U
-#define DSI_VHBPCR_HBP9                0x00000200U
-#define DSI_VHBPCR_HBP10               0x00000400U
-#define DSI_VHBPCR_HBP11               0x00000800U
-
-/*******************  Bit definition for DSI_VLCR register  ***************/
-#define DSI_VLCR_HLINE                 0x00007FFFU               /*!< Horizontal Line duration */
-#define DSI_VLCR_HLINE0                0x00000001U
-#define DSI_VLCR_HLINE1                0x00000002U
-#define DSI_VLCR_HLINE2                0x00000004U
-#define DSI_VLCR_HLINE3                0x00000008U
-#define DSI_VLCR_HLINE4                0x00000010U
-#define DSI_VLCR_HLINE5                0x00000020U
-#define DSI_VLCR_HLINE6                0x00000040U
-#define DSI_VLCR_HLINE7                0x00000080U
-#define DSI_VLCR_HLINE8                0x00000100U
-#define DSI_VLCR_HLINE9                0x00000200U
-#define DSI_VLCR_HLINE10               0x00000400U
-#define DSI_VLCR_HLINE11               0x00000800U
-#define DSI_VLCR_HLINE12               0x00001000U
-#define DSI_VLCR_HLINE13               0x00002000U
-#define DSI_VLCR_HLINE14               0x00004000U
-
-/*******************  Bit definition for DSI_VVSACR register  *************/
-#define DSI_VVSACR_VSA                 0x000003FFU               /*!< Vertical Synchronism Active duration */
-#define DSI_VVSACR_VSA0                0x00000001U
-#define DSI_VVSACR_VSA1                0x00000002U
-#define DSI_VVSACR_VSA2                0x00000004U
-#define DSI_VVSACR_VSA3                0x00000008U
-#define DSI_VVSACR_VSA4                0x00000010U
-#define DSI_VVSACR_VSA5                0x00000020U
-#define DSI_VVSACR_VSA6                0x00000040U
-#define DSI_VVSACR_VSA7                0x00000080U
-#define DSI_VVSACR_VSA8                0x00000100U
-#define DSI_VVSACR_VSA9                0x00000200U
-
-/*******************  Bit definition for DSI_VVBPCR register  *************/
-#define DSI_VVBPCR_VBP                 0x000003FFU               /*!< Vertical Back-Porch duration */
-#define DSI_VVBPCR_VBP0                0x00000001U
-#define DSI_VVBPCR_VBP1                0x00000002U
-#define DSI_VVBPCR_VBP2                0x00000004U
-#define DSI_VVBPCR_VBP3                0x00000008U
-#define DSI_VVBPCR_VBP4                0x00000010U
-#define DSI_VVBPCR_VBP5                0x00000020U
-#define DSI_VVBPCR_VBP6                0x00000040U
-#define DSI_VVBPCR_VBP7                0x00000080U
-#define DSI_VVBPCR_VBP8                0x00000100U
-#define DSI_VVBPCR_VBP9                0x00000200U
-
-/*******************  Bit definition for DSI_VVFPCR register  *************/
-#define DSI_VVFPCR_VFP                 0x000003FFU               /*!< Vertical Front-Porch duration */
-#define DSI_VVFPCR_VFP0                0x00000001U
-#define DSI_VVFPCR_VFP1                0x00000002U
-#define DSI_VVFPCR_VFP2                0x00000004U
-#define DSI_VVFPCR_VFP3                0x00000008U
-#define DSI_VVFPCR_VFP4                0x00000010U
-#define DSI_VVFPCR_VFP5                0x00000020U
-#define DSI_VVFPCR_VFP6                0x00000040U
-#define DSI_VVFPCR_VFP7                0x00000080U
-#define DSI_VVFPCR_VFP8                0x00000100U
-#define DSI_VVFPCR_VFP9                0x00000200U
-
-/*******************  Bit definition for DSI_VVACR register  **************/
-#define DSI_VVACR_VA                   0x00003FFFU               /*!< Vertical Active duration */
-#define DSI_VVACR_VA0                  0x00000001U
-#define DSI_VVACR_VA1                  0x00000002U
-#define DSI_VVACR_VA2                  0x00000004U
-#define DSI_VVACR_VA3                  0x00000008U
-#define DSI_VVACR_VA4                  0x00000010U
-#define DSI_VVACR_VA5                  0x00000020U
-#define DSI_VVACR_VA6                  0x00000040U
-#define DSI_VVACR_VA7                  0x00000080U
-#define DSI_VVACR_VA8                  0x00000100U
-#define DSI_VVACR_VA9                  0x00000200U
-#define DSI_VVACR_VA10                 0x00000400U
-#define DSI_VVACR_VA11                 0x00000800U
-#define DSI_VVACR_VA12                 0x00001000U
-#define DSI_VVACR_VA13                 0x00002000U
-
-/*******************  Bit definition for DSI_LCCR register  ***************/
-#define DSI_LCCR_CMDSIZE               0x0000FFFFU               /*!< Command Size */
-#define DSI_LCCR_CMDSIZE0              0x00000001U
-#define DSI_LCCR_CMDSIZE1              0x00000002U
-#define DSI_LCCR_CMDSIZE2              0x00000004U
-#define DSI_LCCR_CMDSIZE3              0x00000008U
-#define DSI_LCCR_CMDSIZE4              0x00000010U
-#define DSI_LCCR_CMDSIZE5              0x00000020U
-#define DSI_LCCR_CMDSIZE6              0x00000040U
-#define DSI_LCCR_CMDSIZE7              0x00000080U
-#define DSI_LCCR_CMDSIZE8              0x00000100U
-#define DSI_LCCR_CMDSIZE9              0x00000200U
-#define DSI_LCCR_CMDSIZE10             0x00000400U
-#define DSI_LCCR_CMDSIZE11             0x00000800U
-#define DSI_LCCR_CMDSIZE12             0x00001000U
-#define DSI_LCCR_CMDSIZE13             0x00002000U
-#define DSI_LCCR_CMDSIZE14             0x00004000U
-#define DSI_LCCR_CMDSIZE15             0x00008000U
-
-/*******************  Bit definition for DSI_CMCR register  ***************/
-#define DSI_CMCR_TEARE                 0x00000001U               /*!< Tearing Effect Acknowledge Request Enable */
-#define DSI_CMCR_ARE                   0x00000002U               /*!< Acknowledge Request Enable */
-#define DSI_CMCR_GSW0TX                0x00000100U               /*!< Generic Short Write Zero parameters Transmission */
-#define DSI_CMCR_GSW1TX                0x00000200U               /*!< Generic Short Write One parameters Transmission */
-#define DSI_CMCR_GSW2TX                0x00000400U               /*!< Generic Short Write Two parameters Transmission */
-#define DSI_CMCR_GSR0TX                0x00000800U               /*!< Generic Short Read Zero parameters Transmission */
-#define DSI_CMCR_GSR1TX                0x00001000U               /*!< Generic Short Read One parameters Transmission */
-#define DSI_CMCR_GSR2TX                0x00002000U               /*!< Generic Short Read Two parameters Transmission */
-#define DSI_CMCR_GLWTX                 0x00004000U               /*!< Generic Long Write Transmission */
-#define DSI_CMCR_DSW0TX                0x00010000U               /*!< DCS Short Write Zero parameter Transmission */
-#define DSI_CMCR_DSW1TX                0x00020000U               /*!< DCS Short Read One parameter Transmission */
-#define DSI_CMCR_DSR0TX                0x00040000U               /*!< DCS Short Read Zero parameter Transmission */
-#define DSI_CMCR_DLWTX                 0x00080000U               /*!< DCS Long Write Transmission */
-#define DSI_CMCR_MRDPS                 0x01000000U               /*!< Maximum Read Packet Size */
-
-/*******************  Bit definition for DSI_GHCR register  ***************/
-#define DSI_GHCR_DT                    0x0000003FU               /*!< Type */
-#define DSI_GHCR_DT0                   0x00000001U
-#define DSI_GHCR_DT1                   0x00000002U
-#define DSI_GHCR_DT2                   0x00000004U
-#define DSI_GHCR_DT3                   0x00000008U
-#define DSI_GHCR_DT4                   0x00000010U
-#define DSI_GHCR_DT5                   0x00000020U
-
-#define DSI_GHCR_VCID                  0x000000C0U               /*!< Channel */
-#define DSI_GHCR_VCID0                 0x00000040U
-#define DSI_GHCR_VCID1                 0x00000080U
-
-#define DSI_GHCR_WCLSB                 0x0000FF00U               /*!< WordCount LSB */
-#define DSI_GHCR_WCLSB0                0x00000100U
-#define DSI_GHCR_WCLSB1                0x00000200U
-#define DSI_GHCR_WCLSB2                0x00000400U
-#define DSI_GHCR_WCLSB3                0x00000800U
-#define DSI_GHCR_WCLSB4                0x00001000U
-#define DSI_GHCR_WCLSB5                0x00002000U
-#define DSI_GHCR_WCLSB6                0x00004000U
-#define DSI_GHCR_WCLSB7                0x00008000U
-
-#define DSI_GHCR_WCMSB                 0x00FF0000U               /*!< WordCount MSB */
-#define DSI_GHCR_WCMSB0                0x00010000U
-#define DSI_GHCR_WCMSB1                0x00020000U
-#define DSI_GHCR_WCMSB2                0x00040000U
-#define DSI_GHCR_WCMSB3                0x00080000U
-#define DSI_GHCR_WCMSB4                0x00100000U
-#define DSI_GHCR_WCMSB5                0x00200000U
-#define DSI_GHCR_WCMSB6                0x00400000U
-#define DSI_GHCR_WCMSB7                0x00800000U
-
-/*******************  Bit definition for DSI_GPDR register  ***************/
-#define DSI_GPDR_DATA1                 0x000000FFU               /*!< Payload Byte 1 */
-#define DSI_GPDR_DATA1_0               0x00000001U
-#define DSI_GPDR_DATA1_1               0x00000002U
-#define DSI_GPDR_DATA1_2               0x00000004U
-#define DSI_GPDR_DATA1_3               0x00000008U
-#define DSI_GPDR_DATA1_4               0x00000010U
-#define DSI_GPDR_DATA1_5               0x00000020U
-#define DSI_GPDR_DATA1_6               0x00000040U
-#define DSI_GPDR_DATA1_7               0x00000080U
-
-#define DSI_GPDR_DATA2                 0x0000FF00U               /*!< Payload Byte 2 */
-#define DSI_GPDR_DATA2_0               0x00000100U
-#define DSI_GPDR_DATA2_1               0x00000200U
-#define DSI_GPDR_DATA2_2               0x00000400U
-#define DSI_GPDR_DATA2_3               0x00000800U
-#define DSI_GPDR_DATA2_4               0x00001000U
-#define DSI_GPDR_DATA2_5               0x00002000U
-#define DSI_GPDR_DATA2_6               0x00004000U
-#define DSI_GPDR_DATA2_7               0x00008000U
-
-#define DSI_GPDR_DATA3                 0x00FF0000U               /*!< Payload Byte 3 */
-#define DSI_GPDR_DATA3_0               0x00010000U
-#define DSI_GPDR_DATA3_1               0x00020000U
-#define DSI_GPDR_DATA3_2               0x00040000U
-#define DSI_GPDR_DATA3_3               0x00080000U
-#define DSI_GPDR_DATA3_4               0x00100000U
-#define DSI_GPDR_DATA3_5               0x00200000U
-#define DSI_GPDR_DATA3_6               0x00400000U
-#define DSI_GPDR_DATA3_7               0x00800000U
-
-#define DSI_GPDR_DATA4                 0xFF000000U               /*!< Payload Byte 4 */
-#define DSI_GPDR_DATA4_0               0x01000000U
-#define DSI_GPDR_DATA4_1               0x02000000U
-#define DSI_GPDR_DATA4_2               0x04000000U
-#define DSI_GPDR_DATA4_3               0x08000000U
-#define DSI_GPDR_DATA4_4               0x10000000U
-#define DSI_GPDR_DATA4_5               0x20000000U
-#define DSI_GPDR_DATA4_6               0x40000000U
-#define DSI_GPDR_DATA4_7               0x80000000U
-
-/*******************  Bit definition for DSI_GPSR register  ***************/
-#define DSI_GPSR_CMDFE                 0x00000001U               /*!< Command FIFO Empty */
-#define DSI_GPSR_CMDFF                 0x00000002U               /*!< Command FIFO Full */
-#define DSI_GPSR_PWRFE                 0x00000004U               /*!< Payload Write FIFO Empty */
-#define DSI_GPSR_PWRFF                 0x00000008U               /*!< Payload Write FIFO Full */
-#define DSI_GPSR_PRDFE                 0x00000010U               /*!< Payload Read FIFO Empty */
-#define DSI_GPSR_PRDFF                 0x00000020U               /*!< Payload Read FIFO Full */
-#define DSI_GPSR_RCB                   0x00000040U               /*!< Read Command Busy */
-
-/*******************  Bit definition for DSI_TCCR0 register  **************/
-#define DSI_TCCR0_LPRX_TOCNT           0x0000FFFFU               /*!< Low-power Reception Timeout Counter */
-#define DSI_TCCR0_LPRX_TOCNT0          0x00000001U
-#define DSI_TCCR0_LPRX_TOCNT1          0x00000002U
-#define DSI_TCCR0_LPRX_TOCNT2          0x00000004U
-#define DSI_TCCR0_LPRX_TOCNT3          0x00000008U
-#define DSI_TCCR0_LPRX_TOCNT4          0x00000010U
-#define DSI_TCCR0_LPRX_TOCNT5          0x00000020U
-#define DSI_TCCR0_LPRX_TOCNT6          0x00000040U
-#define DSI_TCCR0_LPRX_TOCNT7          0x00000080U
-#define DSI_TCCR0_LPRX_TOCNT8          0x00000100U
-#define DSI_TCCR0_LPRX_TOCNT9          0x00000200U
-#define DSI_TCCR0_LPRX_TOCNT10         0x00000400U
-#define DSI_TCCR0_LPRX_TOCNT11         0x00000800U
-#define DSI_TCCR0_LPRX_TOCNT12         0x00001000U
-#define DSI_TCCR0_LPRX_TOCNT13         0x00002000U
-#define DSI_TCCR0_LPRX_TOCNT14         0x00004000U
-#define DSI_TCCR0_LPRX_TOCNT15         0x00008000U
-
-#define DSI_TCCR0_HSTX_TOCNT           0xFFFF0000U               /*!< High-Speed Transmission Timeout Counter */
-#define DSI_TCCR0_HSTX_TOCNT0          0x00010000U
-#define DSI_TCCR0_HSTX_TOCNT1          0x00020000U
-#define DSI_TCCR0_HSTX_TOCNT2          0x00040000U
-#define DSI_TCCR0_HSTX_TOCNT3          0x00080000U
-#define DSI_TCCR0_HSTX_TOCNT4          0x00100000U
-#define DSI_TCCR0_HSTX_TOCNT5          0x00200000U
-#define DSI_TCCR0_HSTX_TOCNT6          0x00400000U
-#define DSI_TCCR0_HSTX_TOCNT7          0x00800000U
-#define DSI_TCCR0_HSTX_TOCNT8          0x01000000U
-#define DSI_TCCR0_HSTX_TOCNT9          0x02000000U
-#define DSI_TCCR0_HSTX_TOCNT10         0x04000000U
-#define DSI_TCCR0_HSTX_TOCNT11         0x08000000U
-#define DSI_TCCR0_HSTX_TOCNT12         0x10000000U
-#define DSI_TCCR0_HSTX_TOCNT13         0x20000000U
-#define DSI_TCCR0_HSTX_TOCNT14         0x40000000U
-#define DSI_TCCR0_HSTX_TOCNT15         0x80000000U
-
-/*******************  Bit definition for DSI_TCCR1 register  **************/
-#define DSI_TCCR1_HSRD_TOCNT           0x0000FFFFU               /*!< High-Speed Read Timeout Counter */
-#define DSI_TCCR1_HSRD_TOCNT0          0x00000001U
-#define DSI_TCCR1_HSRD_TOCNT1          0x00000002U
-#define DSI_TCCR1_HSRD_TOCNT2          0x00000004U
-#define DSI_TCCR1_HSRD_TOCNT3          0x00000008U
-#define DSI_TCCR1_HSRD_TOCNT4          0x00000010U
-#define DSI_TCCR1_HSRD_TOCNT5          0x00000020U
-#define DSI_TCCR1_HSRD_TOCNT6          0x00000040U
-#define DSI_TCCR1_HSRD_TOCNT7          0x00000080U
-#define DSI_TCCR1_HSRD_TOCNT8          0x00000100U
-#define DSI_TCCR1_HSRD_TOCNT9          0x00000200U
-#define DSI_TCCR1_HSRD_TOCNT10         0x00000400U
-#define DSI_TCCR1_HSRD_TOCNT11         0x00000800U
-#define DSI_TCCR1_HSRD_TOCNT12         0x00001000U
-#define DSI_TCCR1_HSRD_TOCNT13         0x00002000U
-#define DSI_TCCR1_HSRD_TOCNT14         0x00004000U
-#define DSI_TCCR1_HSRD_TOCNT15         0x00008000U
-
-/*******************  Bit definition for DSI_TCCR2 register  **************/
-#define DSI_TCCR2_LPRD_TOCNT           0x0000FFFFU               /*!< Low-Power Read Timeout Counter */
-#define DSI_TCCR2_LPRD_TOCNT0          0x00000001U
-#define DSI_TCCR2_LPRD_TOCNT1          0x00000002U
-#define DSI_TCCR2_LPRD_TOCNT2          0x00000004U
-#define DSI_TCCR2_LPRD_TOCNT3          0x00000008U
-#define DSI_TCCR2_LPRD_TOCNT4          0x00000010U
-#define DSI_TCCR2_LPRD_TOCNT5          0x00000020U
-#define DSI_TCCR2_LPRD_TOCNT6          0x00000040U
-#define DSI_TCCR2_LPRD_TOCNT7          0x00000080U
-#define DSI_TCCR2_LPRD_TOCNT8          0x00000100U
-#define DSI_TCCR2_LPRD_TOCNT9          0x00000200U
-#define DSI_TCCR2_LPRD_TOCNT10         0x00000400U
-#define DSI_TCCR2_LPRD_TOCNT11         0x00000800U
-#define DSI_TCCR2_LPRD_TOCNT12         0x00001000U
-#define DSI_TCCR2_LPRD_TOCNT13         0x00002000U
-#define DSI_TCCR2_LPRD_TOCNT14         0x00004000U
-#define DSI_TCCR2_LPRD_TOCNT15         0x00008000U
-
-/*******************  Bit definition for DSI_TCCR3 register  **************/
-#define DSI_TCCR3_HSWR_TOCNT           0x0000FFFFU               /*!< High-Speed Write Timeout Counter */
-#define DSI_TCCR3_HSWR_TOCNT0          0x00000001U
-#define DSI_TCCR3_HSWR_TOCNT1          0x00000002U
-#define DSI_TCCR3_HSWR_TOCNT2          0x00000004U
-#define DSI_TCCR3_HSWR_TOCNT3          0x00000008U
-#define DSI_TCCR3_HSWR_TOCNT4          0x00000010U
-#define DSI_TCCR3_HSWR_TOCNT5          0x00000020U
-#define DSI_TCCR3_HSWR_TOCNT6          0x00000040U
-#define DSI_TCCR3_HSWR_TOCNT7          0x00000080U
-#define DSI_TCCR3_HSWR_TOCNT8          0x00000100U
-#define DSI_TCCR3_HSWR_TOCNT9          0x00000200U
-#define DSI_TCCR3_HSWR_TOCNT10         0x00000400U
-#define DSI_TCCR3_HSWR_TOCNT11         0x00000800U
-#define DSI_TCCR3_HSWR_TOCNT12         0x00001000U
-#define DSI_TCCR3_HSWR_TOCNT13         0x00002000U
-#define DSI_TCCR3_HSWR_TOCNT14         0x00004000U
-#define DSI_TCCR3_HSWR_TOCNT15         0x00008000U
-
-#define DSI_TCCR3_PM                   0x01000000U               /*!< Presp Mode */
-
-/*******************  Bit definition for DSI_TCCR4 register  **************/
-#define DSI_TCCR4_LPWR_TOCNT           0x0000FFFFU               /*!< Low-Power Write Timeout Counter */
-#define DSI_TCCR4_LPWR_TOCNT0          0x00000001U
-#define DSI_TCCR4_LPWR_TOCNT1          0x00000002U
-#define DSI_TCCR4_LPWR_TOCNT2          0x00000004U
-#define DSI_TCCR4_LPWR_TOCNT3          0x00000008U
-#define DSI_TCCR4_LPWR_TOCNT4          0x00000010U
-#define DSI_TCCR4_LPWR_TOCNT5          0x00000020U
-#define DSI_TCCR4_LPWR_TOCNT6          0x00000040U
-#define DSI_TCCR4_LPWR_TOCNT7          0x00000080U
-#define DSI_TCCR4_LPWR_TOCNT8          0x00000100U
-#define DSI_TCCR4_LPWR_TOCNT9          0x00000200U
-#define DSI_TCCR4_LPWR_TOCNT10         0x00000400U
-#define DSI_TCCR4_LPWR_TOCNT11         0x00000800U
-#define DSI_TCCR4_LPWR_TOCNT12         0x00001000U
-#define DSI_TCCR4_LPWR_TOCNT13         0x00002000U
-#define DSI_TCCR4_LPWR_TOCNT14         0x00004000U
-#define DSI_TCCR4_LPWR_TOCNT15         0x00008000U
-
-/*******************  Bit definition for DSI_TCCR5 register  **************/
-#define DSI_TCCR5_BTA_TOCNT            0x0000FFFFU               /*!< Bus-Turn-Around Timeout Counter */
-#define DSI_TCCR5_BTA_TOCNT0           0x00000001U
-#define DSI_TCCR5_BTA_TOCNT1           0x00000002U
-#define DSI_TCCR5_BTA_TOCNT2           0x00000004U
-#define DSI_TCCR5_BTA_TOCNT3           0x00000008U
-#define DSI_TCCR5_BTA_TOCNT4           0x00000010U
-#define DSI_TCCR5_BTA_TOCNT5           0x00000020U
-#define DSI_TCCR5_BTA_TOCNT6           0x00000040U
-#define DSI_TCCR5_BTA_TOCNT7           0x00000080U
-#define DSI_TCCR5_BTA_TOCNT8           0x00000100U
-#define DSI_TCCR5_BTA_TOCNT9           0x00000200U
-#define DSI_TCCR5_BTA_TOCNT10          0x00000400U
-#define DSI_TCCR5_BTA_TOCNT11          0x00000800U
-#define DSI_TCCR5_BTA_TOCNT12          0x00001000U
-#define DSI_TCCR5_BTA_TOCNT13          0x00002000U
-#define DSI_TCCR5_BTA_TOCNT14          0x00004000U
-#define DSI_TCCR5_BTA_TOCNT15          0x00008000U
-
-/*******************  Bit definition for DSI_TDCR register  ***************/
-#define DSI_TDCR_3DM                   0x00000003U               /*!< 3D Mode */
-#define DSI_TDCR_3DM0                  0x00000001U
-#define DSI_TDCR_3DM1                  0x00000002U
-
-#define DSI_TDCR_3DF                   0x0000000CU               /*!< 3D Format */
-#define DSI_TDCR_3DF0                  0x00000004U
-#define DSI_TDCR_3DF1                  0x00000008U
-
-#define DSI_TDCR_SVS                   0x00000010U               /*!< Second VSYNC */
-#define DSI_TDCR_RF                    0x00000020U               /*!< Right First */
-#define DSI_TDCR_S3DC                  0x00010000U               /*!< Send 3D Control */
-
-/*******************  Bit definition for DSI_CLCR register  ***************/
-#define DSI_CLCR_DPCC                  0x00000001U               /*!< D-PHY Clock Control */
-#define DSI_CLCR_ACR                   0x00000002U               /*!< Automatic Clocklane Control */
-
-/*******************  Bit definition for DSI_CLTCR register  **************/
-#define DSI_CLTCR_LP2HS_TIME           0x000003FFU               /*!< Low-Power to High-Speed Time */
-#define DSI_CLTCR_LP2HS_TIME0          0x00000001U
-#define DSI_CLTCR_LP2HS_TIME1          0x00000002U
-#define DSI_CLTCR_LP2HS_TIME2          0x00000004U
-#define DSI_CLTCR_LP2HS_TIME3          0x00000008U
-#define DSI_CLTCR_LP2HS_TIME4          0x00000010U
-#define DSI_CLTCR_LP2HS_TIME5          0x00000020U
-#define DSI_CLTCR_LP2HS_TIME6          0x00000040U
-#define DSI_CLTCR_LP2HS_TIME7          0x00000080U
-#define DSI_CLTCR_LP2HS_TIME8          0x00000100U
-#define DSI_CLTCR_LP2HS_TIME9          0x00000200U
-
-#define DSI_CLTCR_HS2LP_TIME           0x03FF0000U               /*!< High-Speed to Low-Power Time */
-#define DSI_CLTCR_HS2LP_TIME0          0x00010000U
-#define DSI_CLTCR_HS2LP_TIME1          0x00020000U
-#define DSI_CLTCR_HS2LP_TIME2          0x00040000U
-#define DSI_CLTCR_HS2LP_TIME3          0x00080000U
-#define DSI_CLTCR_HS2LP_TIME4          0x00100000U
-#define DSI_CLTCR_HS2LP_TIME5          0x00200000U
-#define DSI_CLTCR_HS2LP_TIME6          0x00400000U
-#define DSI_CLTCR_HS2LP_TIME7          0x00800000U
-#define DSI_CLTCR_HS2LP_TIME8          0x01000000U
-#define DSI_CLTCR_HS2LP_TIME9          0x02000000U
-
-/*******************  Bit definition for DSI_DLTCR register  **************/
-#define DSI_DLTCR_MRD_TIME             0x00007FFFU               /*!< Maximum Read Time */
-#define DSI_DLTCR_MRD_TIME0            0x00000001U
-#define DSI_DLTCR_MRD_TIME1            0x00000002U
-#define DSI_DLTCR_MRD_TIME2            0x00000004U
-#define DSI_DLTCR_MRD_TIME3            0x00000008U
-#define DSI_DLTCR_MRD_TIME4            0x00000010U
-#define DSI_DLTCR_MRD_TIME5            0x00000020U
-#define DSI_DLTCR_MRD_TIME6            0x00000040U
-#define DSI_DLTCR_MRD_TIME7            0x00000080U
-#define DSI_DLTCR_MRD_TIME8            0x00000100U
-#define DSI_DLTCR_MRD_TIME9            0x00000200U
-#define DSI_DLTCR_MRD_TIME10           0x00000400U
-#define DSI_DLTCR_MRD_TIME11           0x00000800U
-#define DSI_DLTCR_MRD_TIME12           0x00001000U
-#define DSI_DLTCR_MRD_TIME13           0x00002000U
-#define DSI_DLTCR_MRD_TIME14           0x00004000U
-
-#define DSI_DLTCR_LP2HS_TIME           0x00FF0000U               /*!< Low-Power To High-Speed Time */
-#define DSI_DLTCR_LP2HS_TIME0          0x00010000U
-#define DSI_DLTCR_LP2HS_TIME1          0x00020000U
-#define DSI_DLTCR_LP2HS_TIME2          0x00040000U
-#define DSI_DLTCR_LP2HS_TIME3          0x00080000U
-#define DSI_DLTCR_LP2HS_TIME4          0x00100000U
-#define DSI_DLTCR_LP2HS_TIME5          0x00200000U
-#define DSI_DLTCR_LP2HS_TIME6          0x00400000U
-#define DSI_DLTCR_LP2HS_TIME7          0x00800000U
-
-#define DSI_DLTCR_HS2LP_TIME           0xFF000000U               /*!< High-Speed To Low-Power Time */
-#define DSI_DLTCR_HS2LP_TIME0          0x01000000U
-#define DSI_DLTCR_HS2LP_TIME1          0x02000000U
-#define DSI_DLTCR_HS2LP_TIME2          0x04000000U
-#define DSI_DLTCR_HS2LP_TIME3          0x08000000U
-#define DSI_DLTCR_HS2LP_TIME4          0x10000000U
-#define DSI_DLTCR_HS2LP_TIME5          0x20000000U
-#define DSI_DLTCR_HS2LP_TIME6          0x40000000U
-#define DSI_DLTCR_HS2LP_TIME7          0x80000000U
-
-/*******************  Bit definition for DSI_PCTLR register  **************/
-#define DSI_PCTLR_DEN                  0x00000002U               /*!< Digital Enable */
-#define DSI_PCTLR_CKE                  0x00000004U               /*!< Clock Enable */
-
-/*******************  Bit definition for DSI_PCONFR register  *************/
-#define DSI_PCONFR_NL                  0x00000003U               /*!< Number of Lanes */
-#define DSI_PCONFR_NL0                 0x00000001U
-#define DSI_PCONFR_NL1                 0x00000002U
-
-#define DSI_PCONFR_SW_TIME             0x0000FF00U               /*!< Stop Wait Time */
-#define DSI_PCONFR_SW_TIME0            0x00000100U
-#define DSI_PCONFR_SW_TIME1            0x00000200U
-#define DSI_PCONFR_SW_TIME2            0x00000400U
-#define DSI_PCONFR_SW_TIME3            0x00000800U
-#define DSI_PCONFR_SW_TIME4            0x00001000U
-#define DSI_PCONFR_SW_TIME5            0x00002000U
-#define DSI_PCONFR_SW_TIME6            0x00004000U
-#define DSI_PCONFR_SW_TIME7            0x00008000U
-
-/*******************  Bit definition for DSI_PUCR register  ***************/
-#define DSI_PUCR_URCL                  0x00000001U               /*!< ULPS Request on Clock Lane */
-#define DSI_PUCR_UECL                  0x00000002U               /*!< ULPS Exit on Clock Lane */
-#define DSI_PUCR_URDL                  0x00000004U               /*!< ULPS Request on Data Lane */
-#define DSI_PUCR_UEDL                  0x00000008U               /*!< ULPS Exit on Data Lane */
-
-/*******************  Bit definition for DSI_PTTCR register  **************/
-#define DSI_PTTCR_TX_TRIG              0x0000000FU               /*!< Transmission Trigger */
-#define DSI_PTTCR_TX_TRIG0             0x00000001U
-#define DSI_PTTCR_TX_TRIG1             0x00000002U
-#define DSI_PTTCR_TX_TRIG2             0x00000004U
-#define DSI_PTTCR_TX_TRIG3             0x00000008U
-
-/*******************  Bit definition for DSI_PSR register  ****************/
-#define DSI_PSR_PD                     0x00000002U               /*!< PHY Direction */
-#define DSI_PSR_PSSC                   0x00000004U               /*!< PHY Stop State Clock lane */
-#define DSI_PSR_UANC                   0x00000008U               /*!< ULPS Active Not Clock lane */
-#define DSI_PSR_PSS0                   0x00000010U               /*!< PHY Stop State lane 0 */
-#define DSI_PSR_UAN0                   0x00000020U               /*!< ULPS Active Not lane 0 */
-#define DSI_PSR_RUE0                   0x00000040U               /*!< RX ULPS Escape lane 0 */
-#define DSI_PSR_PSS1                   0x00000080U               /*!< PHY Stop State lane 1 */
-#define DSI_PSR_UAN1                   0x00000100U               /*!< ULPS Active Not lane 1 */
-
-/*******************  Bit definition for DSI_ISR0 register  ***************/
-#define DSI_ISR0_AE0                   0x00000001U               /*!< Acknowledge Error 0 */
-#define DSI_ISR0_AE1                   0x00000002U               /*!< Acknowledge Error 1 */
-#define DSI_ISR0_AE2                   0x00000004U               /*!< Acknowledge Error 2 */
-#define DSI_ISR0_AE3                   0x00000008U               /*!< Acknowledge Error 3 */
-#define DSI_ISR0_AE4                   0x00000010U               /*!< Acknowledge Error 4 */
-#define DSI_ISR0_AE5                   0x00000020U               /*!< Acknowledge Error 5 */
-#define DSI_ISR0_AE6                   0x00000040U               /*!< Acknowledge Error 6 */
-#define DSI_ISR0_AE7                   0x00000080U               /*!< Acknowledge Error 7 */
-#define DSI_ISR0_AE8                   0x00000100U               /*!< Acknowledge Error 8 */
-#define DSI_ISR0_AE9                   0x00000200U               /*!< Acknowledge Error 9 */
-#define DSI_ISR0_AE10                  0x00000400U               /*!< Acknowledge Error 10 */
-#define DSI_ISR0_AE11                  0x00000800U               /*!< Acknowledge Error 11 */
-#define DSI_ISR0_AE12                  0x00001000U               /*!< Acknowledge Error 12 */
-#define DSI_ISR0_AE13                  0x00002000U               /*!< Acknowledge Error 13 */
-#define DSI_ISR0_AE14                  0x00004000U               /*!< Acknowledge Error 14 */
-#define DSI_ISR0_AE15                  0x00008000U               /*!< Acknowledge Error 15 */
-#define DSI_ISR0_PE0                   0x00010000U               /*!< PHY Error 0 */
-#define DSI_ISR0_PE1                   0x00020000U               /*!< PHY Error 1 */
-#define DSI_ISR0_PE2                   0x00040000U               /*!< PHY Error 2 */
-#define DSI_ISR0_PE3                   0x00080000U               /*!< PHY Error 3 */
-#define DSI_ISR0_PE4                   0x00100000U               /*!< PHY Error 4 */
-
-/*******************  Bit definition for DSI_ISR1 register  ***************/
-#define DSI_ISR1_TOHSTX                0x00000001U               /*!< Timeout High-Speed Transmission */
-#define DSI_ISR1_TOLPRX                0x00000002U               /*!< Timeout Low-Power Reception */
-#define DSI_ISR1_ECCSE                 0x00000004U               /*!< ECC Single-bit Error */
-#define DSI_ISR1_ECCME                 0x00000008U               /*!< ECC Multi-bit Error */
-#define DSI_ISR1_CRCE                  0x00000010U               /*!< CRC Error */
-#define DSI_ISR1_PSE                   0x00000020U               /*!< Packet Size Error */
-#define DSI_ISR1_EOTPE                 0x00000040U               /*!< EoTp Error */
-#define DSI_ISR1_LPWRE                 0x00000080U               /*!< LTDC Payload Write Error */
-#define DSI_ISR1_GCWRE                 0x00000100U               /*!< Generic Command Write Error */
-#define DSI_ISR1_GPWRE                 0x00000200U               /*!< Generic Payload Write Error */
-#define DSI_ISR1_GPTXE                 0x00000400U               /*!< Generic Payload Transmit Error */
-#define DSI_ISR1_GPRDE                 0x00000800U               /*!< Generic Payload Read Error */
-#define DSI_ISR1_GPRXE                 0x00001000U               /*!< Generic Payload Receive Error */
-
-/*******************  Bit definition for DSI_IER0 register  ***************/
-#define DSI_IER0_AE0IE                 0x00000001U               /*!< Acknowledge Error 0 Interrupt Enable */
-#define DSI_IER0_AE1IE                 0x00000002U               /*!< Acknowledge Error 1 Interrupt Enable */
-#define DSI_IER0_AE2IE                 0x00000004U               /*!< Acknowledge Error 2 Interrupt Enable */
-#define DSI_IER0_AE3IE                 0x00000008U               /*!< Acknowledge Error 3 Interrupt Enable */
-#define DSI_IER0_AE4IE                 0x00000010U               /*!< Acknowledge Error 4 Interrupt Enable */
-#define DSI_IER0_AE5IE                 0x00000020U               /*!< Acknowledge Error 5 Interrupt Enable */
-#define DSI_IER0_AE6IE                 0x00000040U               /*!< Acknowledge Error 6 Interrupt Enable */
-#define DSI_IER0_AE7IE                 0x00000080U               /*!< Acknowledge Error 7 Interrupt Enable */
-#define DSI_IER0_AE8IE                 0x00000100U               /*!< Acknowledge Error 8 Interrupt Enable */
-#define DSI_IER0_AE9IE                 0x00000200U               /*!< Acknowledge Error 9 Interrupt Enable */
-#define DSI_IER0_AE10IE                0x00000400U               /*!< Acknowledge Error 10 Interrupt Enable */
-#define DSI_IER0_AE11IE                0x00000800U               /*!< Acknowledge Error 11 Interrupt Enable */
-#define DSI_IER0_AE12IE                0x00001000U               /*!< Acknowledge Error 12 Interrupt Enable */
-#define DSI_IER0_AE13IE                0x00002000U               /*!< Acknowledge Error 13 Interrupt Enable */
-#define DSI_IER0_AE14IE                0x00004000U               /*!< Acknowledge Error 14 Interrupt Enable */
-#define DSI_IER0_AE15IE                0x00008000U               /*!< Acknowledge Error 15 Interrupt Enable */
-#define DSI_IER0_PE0IE                 0x00010000U               /*!< PHY Error 0 Interrupt Enable */
-#define DSI_IER0_PE1IE                 0x00020000U               /*!< PHY Error 1 Interrupt Enable */
-#define DSI_IER0_PE2IE                 0x00040000U               /*!< PHY Error 2 Interrupt Enable */
-#define DSI_IER0_PE3IE                 0x00080000U               /*!< PHY Error 3 Interrupt Enable */
-#define DSI_IER0_PE4IE                 0x00100000U               /*!< PHY Error 4 Interrupt Enable */
-
-/*******************  Bit definition for DSI_IER1 register  ***************/
-#define DSI_IER1_TOHSTXIE              0x00000001U               /*!< Timeout High-Speed Transmission Interrupt Enable */
-#define DSI_IER1_TOLPRXIE              0x00000002U               /*!< Timeout Low-Power Reception Interrupt Enable */
-#define DSI_IER1_ECCSEIE               0x00000004U               /*!< ECC Single-bit Error Interrupt Enable */
-#define DSI_IER1_ECCMEIE               0x00000008U               /*!< ECC Multi-bit Error Interrupt Enable */
-#define DSI_IER1_CRCEIE                0x00000010U               /*!< CRC Error Interrupt Enable */
-#define DSI_IER1_PSEIE                 0x00000020U               /*!< Packet Size Error Interrupt Enable */
-#define DSI_IER1_EOTPEIE               0x00000040U               /*!< EoTp Error Interrupt Enable */
-#define DSI_IER1_LPWREIE               0x00000080U               /*!< LTDC Payload Write Error Interrupt Enable */
-#define DSI_IER1_GCWREIE               0x00000100U               /*!< Generic Command Write Error Interrupt Enable */
-#define DSI_IER1_GPWREIE               0x00000200U               /*!< Generic Payload Write Error Interrupt Enable */
-#define DSI_IER1_GPTXEIE               0x00000400U               /*!< Generic Payload Transmit Error Interrupt Enable */
-#define DSI_IER1_GPRDEIE               0x00000800U               /*!< Generic Payload Read Error Interrupt Enable */
-#define DSI_IER1_GPRXEIE               0x00001000U               /*!< Generic Payload Receive Error Interrupt Enable */
-
-/*******************  Bit definition for DSI_FIR0 register  ***************/
-#define DSI_FIR0_FAE0                  0x00000001U               /*!< Force Acknowledge Error 0 */
-#define DSI_FIR0_FAE1                  0x00000002U               /*!< Force Acknowledge Error 1 */
-#define DSI_FIR0_FAE2                  0x00000004U               /*!< Force Acknowledge Error 2 */
-#define DSI_FIR0_FAE3                  0x00000008U               /*!< Force Acknowledge Error 3 */
-#define DSI_FIR0_FAE4                  0x00000010U               /*!< Force Acknowledge Error 4 */
-#define DSI_FIR0_FAE5                  0x00000020U               /*!< Force Acknowledge Error 5 */
-#define DSI_FIR0_FAE6                  0x00000040U               /*!< Force Acknowledge Error 6 */
-#define DSI_FIR0_FAE7                  0x00000080U               /*!< Force Acknowledge Error 7 */
-#define DSI_FIR0_FAE8                  0x00000100U               /*!< Force Acknowledge Error 8 */
-#define DSI_FIR0_FAE9                  0x00000200U               /*!< Force Acknowledge Error 9 */
-#define DSI_FIR0_FAE10                 0x00000400U               /*!< Force Acknowledge Error 10 */
-#define DSI_FIR0_FAE11                 0x00000800U               /*!< Force Acknowledge Error 11 */
-#define DSI_FIR0_FAE12                 0x00001000U               /*!< Force Acknowledge Error 12 */
-#define DSI_FIR0_FAE13                 0x00002000U               /*!< Force Acknowledge Error 13 */
-#define DSI_FIR0_FAE14                 0x00004000U               /*!< Force Acknowledge Error 14 */
-#define DSI_FIR0_FAE15                 0x00008000U               /*!< Force Acknowledge Error 15 */
-#define DSI_FIR0_FPE0                  0x00010000U               /*!< Force PHY Error 0 */
-#define DSI_FIR0_FPE1                  0x00020000U               /*!< Force PHY Error 1 */
-#define DSI_FIR0_FPE2                  0x00040000U               /*!< Force PHY Error 2 */
-#define DSI_FIR0_FPE3                  0x00080000U               /*!< Force PHY Error 3 */
-#define DSI_FIR0_FPE4                  0x00100000U               /*!< Force PHY Error 4 */
-
-/*******************  Bit definition for DSI_FIR1 register  ***************/
-#define DSI_FIR1_FTOHSTX               0x00000001U               /*!< Force Timeout High-Speed Transmission */
-#define DSI_FIR1_FTOLPRX               0x00000002U               /*!< Force Timeout Low-Power Reception */
-#define DSI_FIR1_FECCSE                0x00000004U               /*!< Force ECC Single-bit Error */
-#define DSI_FIR1_FECCME                0x00000008U               /*!< Force ECC Multi-bit Error */
-#define DSI_FIR1_FCRCE                 0x00000010U               /*!< Force CRC Error */
-#define DSI_FIR1_FPSE                  0x00000020U               /*!< Force Packet Size Error */
-#define DSI_FIR1_FEOTPE                0x00000040U               /*!< Force EoTp Error */
-#define DSI_FIR1_FLPWRE                0x00000080U               /*!< Force LTDC Payload Write Error */
-#define DSI_FIR1_FGCWRE                0x00000100U               /*!< Force Generic Command Write Error */
-#define DSI_FIR1_FGPWRE                0x00000200U               /*!< Force Generic Payload Write Error */
-#define DSI_FIR1_FGPTXE                0x00000400U               /*!< Force Generic Payload Transmit Error */
-#define DSI_FIR1_FGPRDE                0x00000800U               /*!< Force Generic Payload Read Error */
-#define DSI_FIR1_FGPRXE                0x00001000U               /*!< Force Generic Payload Receive Error */
-
-/*******************  Bit definition for DSI_VSCR register  ***************/
-#define DSI_VSCR_EN                    0x00000001U               /*!< Enable */
-#define DSI_VSCR_UR                    0x00000100U               /*!< Update Register */
-
-/*******************  Bit definition for DSI_LCVCIDR register  ************/
-#define DSI_LCVCIDR_VCID               0x00000003U               /*!< Virtual Channel ID */
-#define DSI_LCVCIDR_VCID0              0x00000001U
-#define DSI_LCVCIDR_VCID1              0x00000002U
-
-/*******************  Bit definition for DSI_LCCCR register  **************/
-#define DSI_LCCCR_COLC                 0x0000000FU               /*!< Color Coding */
-#define DSI_LCCCR_COLC0                0x00000001U
-#define DSI_LCCCR_COLC1                0x00000002U
-#define DSI_LCCCR_COLC2                0x00000004U
-#define DSI_LCCCR_COLC3                0x00000008U
-
-#define DSI_LCCCR_LPE                  0x00000100U               /*!< Loosely Packed Enable */
-
-/*******************  Bit definition for DSI_LPMCCR register  *************/
-#define DSI_LPMCCR_VLPSIZE             0x000000FFU               /*!< VACT Largest Packet Size */
-#define DSI_LPMCCR_VLPSIZE0            0x00000001U
-#define DSI_LPMCCR_VLPSIZE1            0x00000002U
-#define DSI_LPMCCR_VLPSIZE2            0x00000004U
-#define DSI_LPMCCR_VLPSIZE3            0x00000008U
-#define DSI_LPMCCR_VLPSIZE4            0x00000010U
-#define DSI_LPMCCR_VLPSIZE5            0x00000020U
-#define DSI_LPMCCR_VLPSIZE6            0x00000040U
-#define DSI_LPMCCR_VLPSIZE7            0x00000080U
-
-#define DSI_LPMCCR_LPSIZE              0x00FF0000U               /*!< Largest Packet Size */
-#define DSI_LPMCCR_LPSIZE0             0x00010000U
-#define DSI_LPMCCR_LPSIZE1             0x00020000U
-#define DSI_LPMCCR_LPSIZE2             0x00040000U
-#define DSI_LPMCCR_LPSIZE3             0x00080000U
-#define DSI_LPMCCR_LPSIZE4             0x00100000U
-#define DSI_LPMCCR_LPSIZE5             0x00200000U
-#define DSI_LPMCCR_LPSIZE6             0x00400000U
-#define DSI_LPMCCR_LPSIZE7             0x00800000U
-
-/*******************  Bit definition for DSI_VMCCR register  **************/
-#define DSI_VMCCR_VMT                  0x00000003U               /*!< Video Mode Type */
-#define DSI_VMCCR_VMT0                 0x00000001U
-#define DSI_VMCCR_VMT1                 0x00000002U
-
-#define DSI_VMCCR_LPVSAE               0x00000100U               /*!< Low-power Vertical Sync time Enable */
-#define DSI_VMCCR_LPVBPE               0x00000200U               /*!< Low-power Vertical Back-porch Enable */
-#define DSI_VMCCR_LPVFPE               0x00000400U               /*!< Low-power Vertical Front-porch Enable */
-#define DSI_VMCCR_LPVAE                0x00000800U               /*!< Low-power Vertical Active Enable */
-#define DSI_VMCCR_LPHBPE               0x00001000U               /*!< Low-power Horizontal Back-porch Enable */
-#define DSI_VMCCR_LPHFE                0x00002000U               /*!< Low-power Horizontal Front-porch Enable */
-#define DSI_VMCCR_FBTAAE               0x00004000U               /*!< Frame BTA Acknowledge Enable */
-#define DSI_VMCCR_LPCE                 0x00008000U               /*!< Low-power Command Enable */
-
-/*******************  Bit definition for DSI_VPCCR register  **************/
-#define DSI_VPCCR_VPSIZE               0x00003FFFU               /*!< Video Packet Size */
-#define DSI_VPCCR_VPSIZE0              0x00000001U
-#define DSI_VPCCR_VPSIZE1              0x00000002U
-#define DSI_VPCCR_VPSIZE2              0x00000004U
-#define DSI_VPCCR_VPSIZE3              0x00000008U
-#define DSI_VPCCR_VPSIZE4              0x00000010U
-#define DSI_VPCCR_VPSIZE5              0x00000020U
-#define DSI_VPCCR_VPSIZE6              0x00000040U
-#define DSI_VPCCR_VPSIZE7              0x00000080U
-#define DSI_VPCCR_VPSIZE8              0x00000100U
-#define DSI_VPCCR_VPSIZE9              0x00000200U
-#define DSI_VPCCR_VPSIZE10             0x00000400U
-#define DSI_VPCCR_VPSIZE11             0x00000800U
-#define DSI_VPCCR_VPSIZE12             0x00001000U
-#define DSI_VPCCR_VPSIZE13             0x00002000U
-
-/*******************  Bit definition for DSI_VCCCR register  **************/
-#define DSI_VCCCR_NUMC                 0x00001FFFU               /*!< Number of Chunks */
-#define DSI_VCCCR_NUMC0                0x00000001U
-#define DSI_VCCCR_NUMC1                0x00000002U
-#define DSI_VCCCR_NUMC2                0x00000004U
-#define DSI_VCCCR_NUMC3                0x00000008U
-#define DSI_VCCCR_NUMC4                0x00000010U
-#define DSI_VCCCR_NUMC5                0x00000020U
-#define DSI_VCCCR_NUMC6                0x00000040U
-#define DSI_VCCCR_NUMC7                0x00000080U
-#define DSI_VCCCR_NUMC8                0x00000100U
-#define DSI_VCCCR_NUMC9                0x00000200U
-#define DSI_VCCCR_NUMC10               0x00000400U
-#define DSI_VCCCR_NUMC11               0x00000800U
-#define DSI_VCCCR_NUMC12               0x00001000U
-
-/*******************  Bit definition for DSI_VNPCCR register  *************/
-#define DSI_VNPCCR_NPSIZE              0x00001FFFU               /*!< Number of Chunks */
-#define DSI_VNPCCR_NPSIZE0             0x00000001U
-#define DSI_VNPCCR_NPSIZE1             0x00000002U
-#define DSI_VNPCCR_NPSIZE2             0x00000004U
-#define DSI_VNPCCR_NPSIZE3             0x00000008U
-#define DSI_VNPCCR_NPSIZE4             0x00000010U
-#define DSI_VNPCCR_NPSIZE5             0x00000020U
-#define DSI_VNPCCR_NPSIZE6             0x00000040U
-#define DSI_VNPCCR_NPSIZE7             0x00000080U
-#define DSI_VNPCCR_NPSIZE8             0x00000100U
-#define DSI_VNPCCR_NPSIZE9             0x00000200U
-#define DSI_VNPCCR_NPSIZE10            0x00000400U
-#define DSI_VNPCCR_NPSIZE11            0x00000800U
-#define DSI_VNPCCR_NPSIZE12            0x00001000U
-
-/*******************  Bit definition for DSI_VHSACCR register  ************/
-#define DSI_VHSACCR_HSA                0x00000FFFU               /*!< Horizontal Synchronism Active duration */
-#define DSI_VHSACCR_HSA0               0x00000001U
-#define DSI_VHSACCR_HSA1               0x00000002U
-#define DSI_VHSACCR_HSA2               0x00000004U
-#define DSI_VHSACCR_HSA3               0x00000008U
-#define DSI_VHSACCR_HSA4               0x00000010U
-#define DSI_VHSACCR_HSA5               0x00000020U
-#define DSI_VHSACCR_HSA6               0x00000040U
-#define DSI_VHSACCR_HSA7               0x00000080U
-#define DSI_VHSACCR_HSA8               0x00000100U
-#define DSI_VHSACCR_HSA9               0x00000200U
-#define DSI_VHSACCR_HSA10              0x00000400U
-#define DSI_VHSACCR_HSA11              0x00000800U
-
-/*******************  Bit definition for DSI_VHBPCCR register  ************/
-#define DSI_VHBPCCR_HBP                0x00000FFFU               /*!< Horizontal Back-Porch duration */
-#define DSI_VHBPCCR_HBP0               0x00000001U
-#define DSI_VHBPCCR_HBP1               0x00000002U
-#define DSI_VHBPCCR_HBP2               0x00000004U
-#define DSI_VHBPCCR_HBP3               0x00000008U
-#define DSI_VHBPCCR_HBP4               0x00000010U
-#define DSI_VHBPCCR_HBP5               0x00000020U
-#define DSI_VHBPCCR_HBP6               0x00000040U
-#define DSI_VHBPCCR_HBP7               0x00000080U
-#define DSI_VHBPCCR_HBP8               0x00000100U
-#define DSI_VHBPCCR_HBP9               0x00000200U
-#define DSI_VHBPCCR_HBP10              0x00000400U
-#define DSI_VHBPCCR_HBP11              0x00000800U
-
-/*******************  Bit definition for DSI_VLCCR register  **************/
-#define DSI_VLCCR_HLINE                0x00007FFFU               /*!< Horizontal Line duration */
-#define DSI_VLCCR_HLINE0               0x00000001U
-#define DSI_VLCCR_HLINE1               0x00000002U
-#define DSI_VLCCR_HLINE2               0x00000004U
-#define DSI_VLCCR_HLINE3               0x00000008U
-#define DSI_VLCCR_HLINE4               0x00000010U
-#define DSI_VLCCR_HLINE5               0x00000020U
-#define DSI_VLCCR_HLINE6               0x00000040U
-#define DSI_VLCCR_HLINE7               0x00000080U
-#define DSI_VLCCR_HLINE8               0x00000100U
-#define DSI_VLCCR_HLINE9               0x00000200U
-#define DSI_VLCCR_HLINE10              0x00000400U
-#define DSI_VLCCR_HLINE11              0x00000800U
-#define DSI_VLCCR_HLINE12              0x00001000U
-#define DSI_VLCCR_HLINE13              0x00002000U
-#define DSI_VLCCR_HLINE14              0x00004000U
-
-/*******************  Bit definition for DSI_VVSACCR register  ***************/
-#define DSI_VVSACCR_VSA                   0x000003FFU               /*!< Vertical Synchronism Active duration */
-#define DSI_VVSACCR_VSA0                  0x00000001U
-#define DSI_VVSACCR_VSA1                  0x00000002U
-#define DSI_VVSACCR_VSA2                  0x00000004U
-#define DSI_VVSACCR_VSA3                  0x00000008U
-#define DSI_VVSACCR_VSA4                  0x00000010U
-#define DSI_VVSACCR_VSA5                  0x00000020U
-#define DSI_VVSACCR_VSA6                  0x00000040U
-#define DSI_VVSACCR_VSA7                  0x00000080U
-#define DSI_VVSACCR_VSA8                  0x00000100U
-#define DSI_VVSACCR_VSA9                  0x00000200U
-
-/*******************  Bit definition for DSI_VVBPCCR register  ************/
-#define DSI_VVBPCCR_VBP                0x000003FFU               /*!< Vertical Back-Porch duration */
-#define DSI_VVBPCCR_VBP0               0x00000001U
-#define DSI_VVBPCCR_VBP1               0x00000002U
-#define DSI_VVBPCCR_VBP2               0x00000004U
-#define DSI_VVBPCCR_VBP3               0x00000008U
-#define DSI_VVBPCCR_VBP4               0x00000010U
-#define DSI_VVBPCCR_VBP5               0x00000020U
-#define DSI_VVBPCCR_VBP6               0x00000040U
-#define DSI_VVBPCCR_VBP7               0x00000080U
-#define DSI_VVBPCCR_VBP8               0x00000100U
-#define DSI_VVBPCCR_VBP9               0x00000200U
-
-/*******************  Bit definition for DSI_VVFPCCR register  ************/
-#define DSI_VVFPCCR_VFP                0x000003FFU               /*!< Vertical Front-Porch duration */
-#define DSI_VVFPCCR_VFP0               0x00000001U
-#define DSI_VVFPCCR_VFP1               0x00000002U
-#define DSI_VVFPCCR_VFP2               0x00000004U
-#define DSI_VVFPCCR_VFP3               0x00000008U
-#define DSI_VVFPCCR_VFP4               0x00000010U
-#define DSI_VVFPCCR_VFP5               0x00000020U
-#define DSI_VVFPCCR_VFP6               0x00000040U
-#define DSI_VVFPCCR_VFP7               0x00000080U
-#define DSI_VVFPCCR_VFP8               0x00000100U
-#define DSI_VVFPCCR_VFP9               0x00000200U
-
-/*******************  Bit definition for DSI_VVACCR register  *************/
-#define DSI_VVACCR_VA                  0x00003FFFU               /*!< Vertical Active duration */
-#define DSI_VVACCR_VA0                 0x00000001U
-#define DSI_VVACCR_VA1                 0x00000002U
-#define DSI_VVACCR_VA2                 0x00000004U
-#define DSI_VVACCR_VA3                 0x00000008U
-#define DSI_VVACCR_VA4                 0x00000010U
-#define DSI_VVACCR_VA5                 0x00000020U
-#define DSI_VVACCR_VA6                 0x00000040U
-#define DSI_VVACCR_VA7                 0x00000080U
-#define DSI_VVACCR_VA8                 0x00000100U
-#define DSI_VVACCR_VA9                 0x00000200U
-#define DSI_VVACCR_VA10                0x00000400U
-#define DSI_VVACCR_VA11                0x00000800U
-#define DSI_VVACCR_VA12                0x00001000U
-#define DSI_VVACCR_VA13                0x00002000U
-
-/*******************  Bit definition for DSI_TDCCR register  **************/
-#define DSI_TDCCR_3DM                  0x00000003U               /*!< 3D Mode */
-#define DSI_TDCCR_3DM0                 0x00000001U
-#define DSI_TDCCR_3DM1                 0x00000002U
-
-#define DSI_TDCCR_3DF                  0x0000000CU               /*!< 3D Format */
-#define DSI_TDCCR_3DF0                 0x00000004U
-#define DSI_TDCCR_3DF1                 0x00000008U
-
-#define DSI_TDCCR_SVS                  0x00000010U               /*!< Second VSYNC */
-#define DSI_TDCCR_RF                   0x00000020U               /*!< Right First */
-#define DSI_TDCCR_S3DC                 0x00010000U               /*!< Send 3D Control */
-
-/*******************  Bit definition for DSI_WCFGR register  ***************/
-#define DSI_WCFGR_DSIM                   0x00000001U              /*!< DSI Mode */
-#define DSI_WCFGR_COLMUX                 0x0000000EU              /*!< Color Multiplexing */
-#define DSI_WCFGR_COLMUX0                0x00000002U
-#define DSI_WCFGR_COLMUX1                0x00000004U
-#define DSI_WCFGR_COLMUX2                0x00000008U
-
-#define DSI_WCFGR_TESRC                  0x00000010U              /*!< Tearing Effect Source */
-#define DSI_WCFGR_TEPOL                  0x00000020U              /*!< Tearing Effect Polarity */
-#define DSI_WCFGR_AR                     0x00000040U              /*!< Automatic Refresh */
-#define DSI_WCFGR_VSPOL                  0x00000080U              /*!< VSync Polarity */
-
-/*******************  Bit definition for DSI_WCR register  *****************/
-#define DSI_WCR_COLM                     0x00000001U              /*!< Color Mode */
-#define DSI_WCR_SHTDN                    0x00000002U              /*!< Shutdown */
-#define DSI_WCR_LTDCEN                   0x00000004U              /*!< LTDC Enable */
-#define DSI_WCR_DSIEN                    0x00000008U              /*!< DSI Enable */
-
-/*******************  Bit definition for DSI_WIER register  ****************/
-#define DSI_WIER_TEIE                    0x00000001U              /*!< Tearing Effect Interrupt Enable */
-#define DSI_WIER_ERIE                    0x00000002U              /*!< End of Refresh Interrupt Enable */
-#define DSI_WIER_PLLLIE                  0x00000200U              /*!< PLL Lock Interrupt Enable */
-#define DSI_WIER_PLLUIE                  0x00000400U              /*!< PLL Unlock Interrupt Enable */
-#define DSI_WIER_RRIE                    0x00002000U              /*!< Regulator Ready Interrupt Enable */
-
-/*******************  Bit definition for DSI_WISR register  ****************/
-#define DSI_WISR_TEIF                    0x00000001U              /*!< Tearing Effect Interrupt Flag */
-#define DSI_WISR_ERIF                    0x00000002U              /*!< End of Refresh Interrupt Flag */
-#define DSI_WISR_BUSY                    0x00000004U              /*!< Busy Flag */
-#define DSI_WISR_PLLLS                   0x00000100U              /*!< PLL Lock Status */
-#define DSI_WISR_PLLLIF                  0x00000200U              /*!< PLL Lock Interrupt Flag */
-#define DSI_WISR_PLLUIF                  0x00000400U              /*!< PLL Unlock Interrupt Flag */
-#define DSI_WISR_RRS                     0x00001000U              /*!< Regulator Ready Flag */
-#define DSI_WISR_RRIF                    0x00002000U              /*!< Regulator Ready Interrupt Flag */
-
-/*******************  Bit definition for DSI_WIFCR register  ***************/
-#define DSI_WIFCR_CTEIF                  0x00000001U              /*!< Clear Tearing Effect Interrupt Flag */
-#define DSI_WIFCR_CERIF                  0x00000002U              /*!< Clear End of Refresh Interrupt Flag */
-#define DSI_WIFCR_CPLLLIF                0x00000200U              /*!< Clear PLL Lock Interrupt Flag */
-#define DSI_WIFCR_CPLLUIF                0x00000400U              /*!< Clear PLL Unlock Interrupt Flag */
-#define DSI_WIFCR_CRRIF                  0x00002000U              /*!< Clear Regulator Ready Interrupt Flag */
-
-/*******************  Bit definition for DSI_WPCR0 register  ***************/
-#define DSI_WPCR0_UIX4                   0x0000003FU              /*!< Unit Interval multiplied by 4 */
-#define DSI_WPCR0_UIX4_0                 0x00000001U
-#define DSI_WPCR0_UIX4_1                 0x00000002U
-#define DSI_WPCR0_UIX4_2                 0x00000004U
-#define DSI_WPCR0_UIX4_3                 0x00000008U
-#define DSI_WPCR0_UIX4_4                 0x00000010U
-#define DSI_WPCR0_UIX4_5                 0x00000020U
-
-#define DSI_WPCR0_SWCL                   0x00000040U              /*!< Swap pins on clock lane */
-#define DSI_WPCR0_SWDL0                  0x00000080U              /*!< Swap pins on data lane 1 */
-#define DSI_WPCR0_SWDL1                  0x00000100U              /*!< Swap pins on data lane 2 */
-#define DSI_WPCR0_HSICL                  0x00000200U              /*!< Invert the high-speed data signal on clock lane */
-#define DSI_WPCR0_HSIDL0                 0x00000400U              /*!< Invert the high-speed data signal on lane 1 */
-#define DSI_WPCR0_HSIDL1                 0x00000800U              /*!< Invert the high-speed data signal on lane 2 */
-#define DSI_WPCR0_FTXSMCL                0x00001000U              /*!< Force clock lane in TX stop mode */
-#define DSI_WPCR0_FTXSMDL                0x00002000U              /*!< Force data lanes in TX stop mode */
-#define DSI_WPCR0_CDOFFDL                0x00004000U              /*!< Contention detection OFF */
-#define DSI_WPCR0_TDDL                   0x00010000U              /*!< Turn Disable Data Lanes */
-#define DSI_WPCR0_PDEN                   0x00040000U              /*!< Pull-Down Enable */
-#define DSI_WPCR0_TCLKPREPEN             0x00080000U              /*!< Timer for t-CLKPREP Enable */
-#define DSI_WPCR0_TCLKZEROEN             0x00100000U              /*!< Timer for t-CLKZERO Enable */
-#define DSI_WPCR0_THSPREPEN              0x00200000U              /*!< Timer for t-HSPREP Enable */
-#define DSI_WPCR0_THSTRAILEN             0x00400000U              /*!< Timer for t-HSTRAIL Enable */
-#define DSI_WPCR0_THSZEROEN              0x00800000U              /*!< Timer for t-HSZERO Enable */
-#define DSI_WPCR0_TLPXDEN                0x01000000U              /*!< Timer for t-LPXD Enable */
-#define DSI_WPCR0_THSEXITEN              0x02000000U              /*!< Timer for t-HSEXIT Enable */
-#define DSI_WPCR0_TLPXCEN                0x04000000U              /*!< Timer for t-LPXC Enable */
-#define DSI_WPCR0_TCLKPOSTEN             0x08000000U              /*!< Timer for t-CLKPOST Enable */
-
-/*******************  Bit definition for DSI_WPCR1 register  ***************/
-#define DSI_WPCR1_HSTXDCL                0x00000003U              /*!< High-Speed Transmission Delay on Clock Lane */
-#define DSI_WPCR1_HSTXDCL0               0x00000001U
-#define DSI_WPCR1_HSTXDCL1               0x00000002U
-
-#define DSI_WPCR1_HSTXDDL                0x0000000CU              /*!< High-Speed Transmission Delay on Data Lane */
-#define DSI_WPCR1_HSTXDDL0               0x00000004U
-#define DSI_WPCR1_HSTXDDL1               0x00000008U
-
-#define DSI_WPCR1_LPSRCCL                0x000000C0U              /*!< Low-Power transmission Slew Rate Compensation on Clock Lane */
-#define DSI_WPCR1_LPSRCCL0               0x00000040U
-#define DSI_WPCR1_LPSRCCL1               0x00000080U
-
-#define DSI_WPCR1_LPSRCDL                0x00000300U              /*!< Low-Power transmission Slew Rate Compensation on Data Lane */
-#define DSI_WPCR1_LPSRCDL0               0x00000100U
-#define DSI_WPCR1_LPSRCDL1               0x00000200U
-
-#define DSI_WPCR1_SDDC                   0x00001000U              /*!< SDD Control */
-
-#define DSI_WPCR1_LPRXVCDL               0x0000C000U              /*!< Low-Power Reception V-IL Compensation on Data Lanes */
-#define DSI_WPCR1_LPRXVCDL0              0x00004000U
-#define DSI_WPCR1_LPRXVCDL1              0x00008000U
-
-#define DSI_WPCR1_HSTXSRCCL              0x00030000U              /*!< High-Speed Transmission Delay on Clock Lane */
-#define DSI_WPCR1_HSTXSRCCL0             0x00010000U
-#define DSI_WPCR1_HSTXSRCCL1             0x00020000U
-
-#define DSI_WPCR1_HSTXSRCDL              0x000C0000U              /*!< High-Speed Transmission Delay on Data Lane */
-#define DSI_WPCR1_HSTXSRCDL0             0x00040000U
-#define DSI_WPCR1_HSTXSRCDL1             0x00080000U
-
-#define DSI_WPCR1_FLPRXLPM               0x00400000U              /*!< Forces LP Receiver in Low-Power Mode */
-
-#define DSI_WPCR1_LPRXFT                 0x06000000U              /*!< Low-Power RX low-pass Filtering Tuning */
-#define DSI_WPCR1_LPRXFT0                0x02000000U
-#define DSI_WPCR1_LPRXFT1                0x04000000U
-
-/*******************  Bit definition for DSI_WPCR2 register  ***************/
-#define DSI_WPCR2_TCLKPREP               0x000000FFU              /*!< t-CLKPREP */
-#define DSI_WPCR2_TCLKPREP0              0x00000001U
-#define DSI_WPCR2_TCLKPREP1              0x00000002U
-#define DSI_WPCR2_TCLKPREP2              0x00000004U
-#define DSI_WPCR2_TCLKPREP3              0x00000008U
-#define DSI_WPCR2_TCLKPREP4              0x00000010U
-#define DSI_WPCR2_TCLKPREP5              0x00000020U
-#define DSI_WPCR2_TCLKPREP6              0x00000040U
-#define DSI_WPCR2_TCLKPREP7              0x00000080U
-
-#define DSI_WPCR2_TCLKZERO               0x0000FF00U              /*!< t-CLKZERO */
-#define DSI_WPCR2_TCLKZERO0              0x00000100U
-#define DSI_WPCR2_TCLKZERO1              0x00000200U
-#define DSI_WPCR2_TCLKZERO2              0x00000400U
-#define DSI_WPCR2_TCLKZERO3              0x00000800U
-#define DSI_WPCR2_TCLKZERO4              0x00001000U
-#define DSI_WPCR2_TCLKZERO5              0x00002000U
-#define DSI_WPCR2_TCLKZERO6              0x00004000U
-#define DSI_WPCR2_TCLKZERO7              0x00008000U
-
-#define DSI_WPCR2_THSPREP                0x00FF0000U              /*!< t-HSPREP */
-#define DSI_WPCR2_THSPREP0               0x00010000U
-#define DSI_WPCR2_THSPREP1               0x00020000U
-#define DSI_WPCR2_THSPREP2               0x00040000U
-#define DSI_WPCR2_THSPREP3               0x00080000U
-#define DSI_WPCR2_THSPREP4               0x00100000U
-#define DSI_WPCR2_THSPREP5               0x00200000U
-#define DSI_WPCR2_THSPREP6               0x00400000U
-#define DSI_WPCR2_THSPREP7               0x00800000U
-
-#define DSI_WPCR2_THSTRAIL               0xFF000000U              /*!< t-HSTRAIL */
-#define DSI_WPCR2_THSTRAIL0              0x01000000U
-#define DSI_WPCR2_THSTRAIL1              0x02000000U
-#define DSI_WPCR2_THSTRAIL2              0x04000000U
-#define DSI_WPCR2_THSTRAIL3              0x08000000U
-#define DSI_WPCR2_THSTRAIL4              0x10000000U
-#define DSI_WPCR2_THSTRAIL5              0x20000000U
-#define DSI_WPCR2_THSTRAIL6              0x40000000U
-#define DSI_WPCR2_THSTRAIL7              0x80000000U
-
-/*******************  Bit definition for DSI_WPCR3 register  ***************/
-#define DSI_WPCR3_THSZERO                0x000000FFU              /*!< t-HSZERO */
-#define DSI_WPCR3_THSZERO0               0x00000001U
-#define DSI_WPCR3_THSZERO1               0x00000002U
-#define DSI_WPCR3_THSZERO2               0x00000004U
-#define DSI_WPCR3_THSZERO3               0x00000008U
-#define DSI_WPCR3_THSZERO4               0x00000010U
-#define DSI_WPCR3_THSZERO5               0x00000020U
-#define DSI_WPCR3_THSZERO6               0x00000040U
-#define DSI_WPCR3_THSZERO7               0x00000080U
-
-#define DSI_WPCR3_TLPXD                  0x0000FF00U              /*!< t-LPXD */
-#define DSI_WPCR3_TLPXD0                 0x00000100U
-#define DSI_WPCR3_TLPXD1                 0x00000200U
-#define DSI_WPCR3_TLPXD2                 0x00000400U
-#define DSI_WPCR3_TLPXD3                 0x00000800U
-#define DSI_WPCR3_TLPXD4                 0x00001000U
-#define DSI_WPCR3_TLPXD5                 0x00002000U
-#define DSI_WPCR3_TLPXD6                 0x00004000U
-#define DSI_WPCR3_TLPXD7                 0x00008000U
-
-#define DSI_WPCR3_THSEXIT                0x00FF0000U              /*!< t-HSEXIT */
-#define DSI_WPCR3_THSEXIT0               0x00010000U
-#define DSI_WPCR3_THSEXIT1               0x00020000U
-#define DSI_WPCR3_THSEXIT2               0x00040000U
-#define DSI_WPCR3_THSEXIT3               0x00080000U
-#define DSI_WPCR3_THSEXIT4               0x00100000U
-#define DSI_WPCR3_THSEXIT5               0x00200000U
-#define DSI_WPCR3_THSEXIT6               0x00400000U
-#define DSI_WPCR3_THSEXIT7               0x00800000U
-
-#define DSI_WPCR3_TLPXC                  0xFF000000U              /*!< t-LPXC */
-#define DSI_WPCR3_TLPXC0                 0x01000000U
-#define DSI_WPCR3_TLPXC1                 0x02000000U
-#define DSI_WPCR3_TLPXC2                 0x04000000U
-#define DSI_WPCR3_TLPXC3                 0x08000000U
-#define DSI_WPCR3_TLPXC4                 0x10000000U
-#define DSI_WPCR3_TLPXC5                 0x20000000U
-#define DSI_WPCR3_TLPXC6                 0x40000000U
-#define DSI_WPCR3_TLPXC7                 0x80000000U
-
-/*******************  Bit definition for DSI_WPCR4 register  ***************/
-#define DSI_WPCR4_TCLKPOST               0x000000FFU              /*!< t-CLKPOST */
-#define DSI_WPCR4_TCLKPOST0              0x00000001U
-#define DSI_WPCR4_TCLKPOST1              0x00000002U
-#define DSI_WPCR4_TCLKPOST2              0x00000004U
-#define DSI_WPCR4_TCLKPOST3              0x00000008U
-#define DSI_WPCR4_TCLKPOST4              0x00000010U
-#define DSI_WPCR4_TCLKPOST5              0x00000020U
-#define DSI_WPCR4_TCLKPOST6              0x00000040U
-#define DSI_WPCR4_TCLKPOST7              0x00000080U
-
-/*******************  Bit definition for DSI_WRPCR register  ***************/
-#define DSI_WRPCR_PLLEN                  0x00000001U              /*!< PLL Enable */
-#define DSI_WRPCR_PLL_NDIV               0x000001FCU              /*!< PLL Loop Division Factor */
-#define DSI_WRPCR_PLL_NDIV0              0x00000004U
-#define DSI_WRPCR_PLL_NDIV1              0x00000008U
-#define DSI_WRPCR_PLL_NDIV2              0x00000010U
-#define DSI_WRPCR_PLL_NDIV3              0x00000020U
-#define DSI_WRPCR_PLL_NDIV4              0x00000040U
-#define DSI_WRPCR_PLL_NDIV5              0x00000080U
-#define DSI_WRPCR_PLL_NDIV6              0x00000100U
-
-#define DSI_WRPCR_PLL_IDF                0x00007800U              /*!< PLL Input Division Factor */
-#define DSI_WRPCR_PLL_IDF0               0x00000800U
-#define DSI_WRPCR_PLL_IDF1               0x00001000U
-#define DSI_WRPCR_PLL_IDF2               0x00002000U
-#define DSI_WRPCR_PLL_IDF3               0x00004000U
-
-#define DSI_WRPCR_PLL_ODF                0x00030000U              /*!< PLL Output Division Factor */
-#define DSI_WRPCR_PLL_ODF0               0x00010000U
-#define DSI_WRPCR_PLL_ODF1               0x00020000U
-
-#define DSI_WRPCR_REGEN                  0x01000000U              /*!< Regulator Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                    External Interrupt/Event Controller                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    FLASH                                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    0x0000000FU
-#define FLASH_ACR_LATENCY_0WS                0x00000000U
-#define FLASH_ACR_LATENCY_1WS                0x00000001U
-#define FLASH_ACR_LATENCY_2WS                0x00000002U
-#define FLASH_ACR_LATENCY_3WS                0x00000003U
-#define FLASH_ACR_LATENCY_4WS                0x00000004U
-#define FLASH_ACR_LATENCY_5WS                0x00000005U
-#define FLASH_ACR_LATENCY_6WS                0x00000006U
-#define FLASH_ACR_LATENCY_7WS                0x00000007U
-#define FLASH_ACR_LATENCY_8WS                0x00000008U
-#define FLASH_ACR_LATENCY_9WS                0x00000009U
-#define FLASH_ACR_LATENCY_10WS               0x0000000AU
-#define FLASH_ACR_LATENCY_11WS               0x0000000BU
-#define FLASH_ACR_LATENCY_12WS               0x0000000CU
-#define FLASH_ACR_LATENCY_13WS               0x0000000DU
-#define FLASH_ACR_LATENCY_14WS               0x0000000EU
-#define FLASH_ACR_LATENCY_15WS               0x0000000FU
-#define FLASH_ACR_PRFTEN                     0x00000100U
-#define FLASH_ACR_ICEN                       0x00000200U
-#define FLASH_ACR_DCEN                       0x00000400U
-#define FLASH_ACR_ICRST                      0x00000800U
-#define FLASH_ACR_DCRST                      0x00001000U
-#define FLASH_ACR_BYTE0_ADDRESS              0x40023C00U
-#define FLASH_ACR_BYTE2_ADDRESS              0x40023C03U
-
-/*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         0x00000001U
-#define FLASH_SR_SOP                         0x00000002U
-#define FLASH_SR_WRPERR                      0x00000010U
-#define FLASH_SR_PGAERR                      0x00000020U
-#define FLASH_SR_PGPERR                      0x00000040U
-#define FLASH_SR_PGSERR                      0x00000080U
-#define FLASH_SR_BSY                         0x00010000U
-
-/*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          0x00000001U
-#define FLASH_CR_SER                         0x00000002U
-#define FLASH_CR_MER                         0x00000004U
-#define FLASH_CR_MER1                        FLASH_CR_MER
-#define FLASH_CR_SNB                         0x000000F8U
-#define FLASH_CR_SNB_0                       0x00000008U
-#define FLASH_CR_SNB_1                       0x00000010U
-#define FLASH_CR_SNB_2                       0x00000020U
-#define FLASH_CR_SNB_3                       0x00000040U
-#define FLASH_CR_SNB_4                       0x00000080U
-#define FLASH_CR_PSIZE                       0x00000300U
-#define FLASH_CR_PSIZE_0                     0x00000100U
-#define FLASH_CR_PSIZE_1                     0x00000200U
-#define FLASH_CR_MER2                        0x00008000U
-#define FLASH_CR_STRT                        0x00010000U
-#define FLASH_CR_EOPIE                       0x01000000U
-#define FLASH_CR_LOCK                        0x80000000U
-
-/*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                 0x00000001U
-#define FLASH_OPTCR_OPTSTRT                 0x00000002U
-#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
-#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
-#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
-#define FLASH_OPTCR_BFB2                    0x00000010U
-#define FLASH_OPTCR_WDG_SW                  0x00000020U
-#define FLASH_OPTCR_nRST_STOP               0x00000040U
-#define FLASH_OPTCR_nRST_STDBY              0x00000080U
-#define FLASH_OPTCR_RDP                     0x0000FF00U
-#define FLASH_OPTCR_RDP_0                   0x00000100U
-#define FLASH_OPTCR_RDP_1                   0x00000200U
-#define FLASH_OPTCR_RDP_2                   0x00000400U
-#define FLASH_OPTCR_RDP_3                   0x00000800U
-#define FLASH_OPTCR_RDP_4                   0x00001000U
-#define FLASH_OPTCR_RDP_5                   0x00002000U
-#define FLASH_OPTCR_RDP_6                   0x00004000U
-#define FLASH_OPTCR_RDP_7                   0x00008000U
-#define FLASH_OPTCR_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR_nWRP_0                  0x00010000U
-#define FLASH_OPTCR_nWRP_1                  0x00020000U
-#define FLASH_OPTCR_nWRP_2                  0x00040000U
-#define FLASH_OPTCR_nWRP_3                  0x00080000U
-#define FLASH_OPTCR_nWRP_4                  0x00100000U
-#define FLASH_OPTCR_nWRP_5                  0x00200000U
-#define FLASH_OPTCR_nWRP_6                  0x00400000U
-#define FLASH_OPTCR_nWRP_7                  0x00800000U
-#define FLASH_OPTCR_nWRP_8                  0x01000000U
-#define FLASH_OPTCR_nWRP_9                  0x02000000U
-#define FLASH_OPTCR_nWRP_10                 0x04000000U
-#define FLASH_OPTCR_nWRP_11                 0x08000000U
-#define FLASH_OPTCR_DB1M                    0x40000000U 
-#define FLASH_OPTCR_SPRMOD                  0x80000000U 
-                                             
-/******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR1_nWRP_0                  0x00010000U
-#define FLASH_OPTCR1_nWRP_1                  0x00020000U
-#define FLASH_OPTCR1_nWRP_2                  0x00040000U
-#define FLASH_OPTCR1_nWRP_3                  0x00080000U
-#define FLASH_OPTCR1_nWRP_4                  0x00100000U
-#define FLASH_OPTCR1_nWRP_5                  0x00200000U
-#define FLASH_OPTCR1_nWRP_6                  0x00400000U
-#define FLASH_OPTCR1_nWRP_7                  0x00800000U
-#define FLASH_OPTCR1_nWRP_8                  0x01000000U
-#define FLASH_OPTCR1_nWRP_9                  0x02000000U
-#define FLASH_OPTCR1_nWRP_10                 0x04000000U
-#define FLASH_OPTCR1_nWRP_11                 0x08000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Flexible Memory Controller                        */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for FMC_BCR1 register  *******************/
-#define  FMC_BCR1_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR1_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FMC_BCR1_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR1_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR1_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FMC_BCR1_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR1_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR1_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_BCR1_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR1_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR1_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR1_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR1_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR1_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR1_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR1_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR1_CPSIZE                    0x00070000U        /*!<CRAM page size             */
-#define  FMC_BCR1_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FMC_BCR1_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FMC_BCR1_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FMC_BCR1_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-#define  FMC_BCR1_CCLKEN                    0x00100000U        /*!<Continous clock enable     */
-#define  FMC_BCR1_WFDIS                     0x00200000U        /*!<Write FIFO Disable         */
-
-/******************  Bit definition for FMC_BCR2 register  *******************/
-#define  FMC_BCR2_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR2_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FMC_BCR2_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR2_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR2_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FMC_BCR2_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR2_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR2_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_BCR2_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR2_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR2_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR2_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR2_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR2_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR2_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR2_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR2_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FMC_BCR3 register  *******************/
-#define  FMC_BCR3_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR3_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FMC_BCR3_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR3_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR3_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FMC_BCR3_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR3_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR3_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_BCR3_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR3_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR3_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR3_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR3_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR3_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR3_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR3_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR3_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FMC_BCR4 register  *******************/
-#define  FMC_BCR4_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR4_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-
-#define  FMC_BCR4_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR4_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR4_MTYP_1                    0x00000008U        /*!<Bit 1 */
-
-#define  FMC_BCR4_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR4_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR4_MWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_BCR4_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR4_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR4_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR4_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR4_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR4_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR4_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR4_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR4_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FMC_BTR1 register  ******************/
-#define  FMC_BTR1_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR1_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR1_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR1_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR1_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BTR1_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
-#define  FMC_BTR1_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR1_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR1_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR1_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BTR1_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR1_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR1_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR1_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR1_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR1_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR1_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR1_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR1_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BTR1_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR1_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR1_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR1_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR1_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BTR1_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR1_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR1_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR1_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR1_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FMC_BTR1_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR1_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR1_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR1_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR1_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FMC_BTR1_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR1_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR1_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BTR2 register  *******************/
-#define  FMC_BTR2_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR2_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR2_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR2_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR2_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BTR2_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR2_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR2_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR2_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR2_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BTR2_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR2_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR2_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR2_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR2_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR2_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR2_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR2_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR2_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BTR2_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR2_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR2_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR2_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR2_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BTR2_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR2_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR2_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR2_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR2_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FMC_BTR2_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR2_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR2_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR2_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR2_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FMC_BTR2_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR2_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR2_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/*******************  Bit definition for FMC_BTR3 register  *******************/
-#define  FMC_BTR3_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR3_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR3_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR3_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR3_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BTR3_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR3_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR3_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR3_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR3_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BTR3_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR3_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR3_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR3_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR3_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR3_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR3_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR3_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR3_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BTR3_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR3_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR3_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR3_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR3_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BTR3_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR3_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR3_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR3_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR3_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FMC_BTR3_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR3_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR3_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR3_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR3_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FMC_BTR3_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR3_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR3_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BTR4 register  *******************/
-#define  FMC_BTR4_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR4_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR4_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR4_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR4_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BTR4_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR4_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR4_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR4_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR4_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BTR4_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR4_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR4_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR4_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR4_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR4_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR4_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR4_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR4_DATAST_7                  0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BTR4_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR4_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR4_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR4_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR4_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BTR4_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR4_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR4_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR4_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR4_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-
-#define  FMC_BTR4_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR4_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR4_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR4_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR4_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-
-#define  FMC_BTR4_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR4_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR4_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR1 register  ******************/
-#define  FMC_BWTR1_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR1_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR1_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR1_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR1_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BWTR1_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR1_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR1_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR1_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR1_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BWTR1_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR1_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR1_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR1_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR1_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR1_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR1_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR1_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR1_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BWTR1_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR1_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR1_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR1_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR1_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BWTR1_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR1_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR1_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR2 register  ******************/
-#define  FMC_BWTR2_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR2_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR2_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR2_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR2_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BWTR2_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR2_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR2_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR2_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR2_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BWTR2_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR2_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR2_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR2_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR2_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR2_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR2_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR2_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR2_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BWTR2_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR2_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR2_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR2_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR2_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BWTR2_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR2_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR2_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR3 register  ******************/
-#define  FMC_BWTR3_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR3_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR3_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR3_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR3_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BWTR3_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR3_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR3_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR3_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR3_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BWTR3_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR3_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR3_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR3_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR3_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR3_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR3_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR3_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR3_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BWTR3_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR3_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR3_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR3_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR3_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BWTR3_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR3_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR3_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR4 register  ******************/
-#define  FMC_BWTR4_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR4_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR4_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR4_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR4_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-
-#define  FMC_BWTR4_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR4_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR4_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR4_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR4_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-
-#define  FMC_BWTR4_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR4_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR4_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR4_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR4_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR4_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR4_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR4_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR4_DATAST_7                 0x00008000U        /*!<Bit 7 */
-
-#define  FMC_BWTR4_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR4_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR4_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR4_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR4_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-
-#define  FMC_BWTR4_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR4_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR4_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_PCR register  *******************/
-#define  FMC_PCR_PWAITEN                   0x00000002U        /*!<Wait feature enable bit                   */
-#define  FMC_PCR_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FMC_PCR_PTYP                      0x00000008U        /*!<Memory type                               */
-
-#define  FMC_PCR_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FMC_PCR_PWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_PCR_PWID_1                    0x00000020U        /*!<Bit 1 */
-
-#define  FMC_PCR_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit          */
-
-#define  FMC_PCR_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay)          */
-#define  FMC_PCR_TCLR_0                    0x00000200U        /*!<Bit 0 */
-#define  FMC_PCR_TCLR_1                    0x00000400U        /*!<Bit 1 */
-#define  FMC_PCR_TCLR_2                    0x00000800U        /*!<Bit 2 */
-#define  FMC_PCR_TCLR_3                    0x00001000U        /*!<Bit 3 */
-
-#define  FMC_PCR_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay)           */
-#define  FMC_PCR_TAR_0                     0x00002000U        /*!<Bit 0 */
-#define  FMC_PCR_TAR_1                     0x00004000U        /*!<Bit 1 */
-#define  FMC_PCR_TAR_2                     0x00008000U        /*!<Bit 2 */
-#define  FMC_PCR_TAR_3                     0x00010000U        /*!<Bit 3 */
-
-#define  FMC_PCR_ECCPS                     0x000E0000U        /*!<ECCPS[1:0] bits (ECC page size)           */
-#define  FMC_PCR_ECCPS_0                   0x00020000U        /*!<Bit 0 */
-#define  FMC_PCR_ECCPS_1                   0x00040000U        /*!<Bit 1 */
-#define  FMC_PCR_ECCPS_2                   0x00080000U        /*!<Bit 2 */
-
-/*******************  Bit definition for FMC_SR register  *******************/
-#define  FMC_SR_IRS                        0x01U               /*!<Interrupt Rising Edge status                */
-#define  FMC_SR_ILS                        0x02U               /*!<Interrupt Level status                      */
-#define  FMC_SR_IFS                        0x04U               /*!<Interrupt Falling Edge status               */
-#define  FMC_SR_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FMC_SR_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit        */
-#define  FMC_SR_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FMC_SR_FEMPT                      0x40U               /*!<FIFO empty                                  */
-
-/******************  Bit definition for FMC_PMEM register  ******************/
-#define  FMC_PMEM_MEMSET2                  0x000000FFU        /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
-#define  FMC_PMEM_MEMSET2_0                0x00000001U        /*!<Bit 0 */
-#define  FMC_PMEM_MEMSET2_1                0x00000002U        /*!<Bit 1 */
-#define  FMC_PMEM_MEMSET2_2                0x00000004U        /*!<Bit 2 */
-#define  FMC_PMEM_MEMSET2_3                0x00000008U        /*!<Bit 3 */
-#define  FMC_PMEM_MEMSET2_4                0x00000010U        /*!<Bit 4 */
-#define  FMC_PMEM_MEMSET2_5                0x00000020U        /*!<Bit 5 */
-#define  FMC_PMEM_MEMSET2_6                0x00000040U        /*!<Bit 6 */
-#define  FMC_PMEM_MEMSET2_7                0x00000080U        /*!<Bit 7 */
-
-#define  FMC_PMEM_MEMWAIT2                 0x0000FF00U        /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
-#define  FMC_PMEM_MEMWAIT2_0               0x00000100U        /*!<Bit 0 */
-#define  FMC_PMEM_MEMWAIT2_1               0x00000200U        /*!<Bit 1 */
-#define  FMC_PMEM_MEMWAIT2_2               0x00000400U        /*!<Bit 2 */
-#define  FMC_PMEM_MEMWAIT2_3               0x00000800U        /*!<Bit 3 */
-#define  FMC_PMEM_MEMWAIT2_4               0x00001000U        /*!<Bit 4 */
-#define  FMC_PMEM_MEMWAIT2_5               0x00002000U        /*!<Bit 5 */
-#define  FMC_PMEM_MEMWAIT2_6               0x00004000U        /*!<Bit 6 */
-#define  FMC_PMEM_MEMWAIT2_7               0x00008000U        /*!<Bit 7 */
-
-#define  FMC_PMEM_MEMHOLD2                 0x00FF0000U        /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
-#define  FMC_PMEM_MEMHOLD2_0               0x00010000U        /*!<Bit 0 */
-#define  FMC_PMEM_MEMHOLD2_1               0x00020000U        /*!<Bit 1 */
-#define  FMC_PMEM_MEMHOLD2_2               0x00040000U        /*!<Bit 2 */
-#define  FMC_PMEM_MEMHOLD2_3               0x00080000U        /*!<Bit 3 */
-#define  FMC_PMEM_MEMHOLD2_4               0x00100000U        /*!<Bit 4 */
-#define  FMC_PMEM_MEMHOLD2_5               0x00200000U        /*!<Bit 5 */
-#define  FMC_PMEM_MEMHOLD2_6               0x00400000U        /*!<Bit 6 */
-#define  FMC_PMEM_MEMHOLD2_7               0x00800000U        /*!<Bit 7 */
-
-#define  FMC_PMEM_MEMHIZ2                  0xFF000000U        /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
-#define  FMC_PMEM_MEMHIZ2_0                0x01000000U        /*!<Bit 0 */
-#define  FMC_PMEM_MEMHIZ2_1                0x02000000U        /*!<Bit 1 */
-#define  FMC_PMEM_MEMHIZ2_2                0x04000000U        /*!<Bit 2 */
-#define  FMC_PMEM_MEMHIZ2_3                0x08000000U        /*!<Bit 3 */
-#define  FMC_PMEM_MEMHIZ2_4                0x10000000U        /*!<Bit 4 */
-#define  FMC_PMEM_MEMHIZ2_5                0x20000000U        /*!<Bit 5 */
-#define  FMC_PMEM_MEMHIZ2_6                0x40000000U        /*!<Bit 6 */
-#define  FMC_PMEM_MEMHIZ2_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_PATT register  ******************/
-#define  FMC_PATT_ATTSET2                  0x000000FFU        /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
-#define  FMC_PATT_ATTSET2_0                0x00000001U        /*!<Bit 0 */
-#define  FMC_PATT_ATTSET2_1                0x00000002U        /*!<Bit 1 */
-#define  FMC_PATT_ATTSET2_2                0x00000004U        /*!<Bit 2 */
-#define  FMC_PATT_ATTSET2_3                0x00000008U        /*!<Bit 3 */
-#define  FMC_PATT_ATTSET2_4                0x00000010U        /*!<Bit 4 */
-#define  FMC_PATT_ATTSET2_5                0x00000020U        /*!<Bit 5 */
-#define  FMC_PATT_ATTSET2_6                0x00000040U        /*!<Bit 6 */
-#define  FMC_PATT_ATTSET2_7                0x00000080U        /*!<Bit 7 */
-
-#define  FMC_PATT_ATTWAIT2                 0x0000FF00U        /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
-#define  FMC_PATT_ATTWAIT2_0               0x00000100U        /*!<Bit 0 */
-#define  FMC_PATT_ATTWAIT2_1               0x00000200U        /*!<Bit 1 */
-#define  FMC_PATT_ATTWAIT2_2               0x00000400U        /*!<Bit 2 */
-#define  FMC_PATT_ATTWAIT2_3               0x00000800U        /*!<Bit 3 */
-#define  FMC_PATT_ATTWAIT2_4               0x00001000U        /*!<Bit 4 */
-#define  FMC_PATT_ATTWAIT2_5               0x00002000U        /*!<Bit 5 */
-#define  FMC_PATT_ATTWAIT2_6               0x00004000U        /*!<Bit 6 */
-#define  FMC_PATT_ATTWAIT2_7               0x00008000U        /*!<Bit 7 */
-
-#define  FMC_PATT_ATTHOLD2                 0x00FF0000U        /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
-#define  FMC_PATT_ATTHOLD2_0               0x00010000U        /*!<Bit 0 */
-#define  FMC_PATT_ATTHOLD2_1               0x00020000U        /*!<Bit 1 */
-#define  FMC_PATT_ATTHOLD2_2               0x00040000U        /*!<Bit 2 */
-#define  FMC_PATT_ATTHOLD2_3               0x00080000U        /*!<Bit 3 */
-#define  FMC_PATT_ATTHOLD2_4               0x00100000U        /*!<Bit 4 */
-#define  FMC_PATT_ATTHOLD2_5               0x00200000U        /*!<Bit 5 */
-#define  FMC_PATT_ATTHOLD2_6               0x00400000U        /*!<Bit 6 */
-#define  FMC_PATT_ATTHOLD2_7               0x00800000U        /*!<Bit 7 */
-
-#define  FMC_PATT_ATTHIZ2                  0xFF000000U        /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
-#define  FMC_PATT_ATTHIZ2_0                0x01000000U        /*!<Bit 0 */
-#define  FMC_PATT_ATTHIZ2_1                0x02000000U        /*!<Bit 1 */
-#define  FMC_PATT_ATTHIZ2_2                0x04000000U        /*!<Bit 2 */
-#define  FMC_PATT_ATTHIZ2_3                0x08000000U        /*!<Bit 3 */
-#define  FMC_PATT_ATTHIZ2_4                0x10000000U        /*!<Bit 4 */
-#define  FMC_PATT_ATTHIZ2_5                0x20000000U        /*!<Bit 5 */
-#define  FMC_PATT_ATTHIZ2_6                0x40000000U        /*!<Bit 6 */
-#define  FMC_PATT_ATTHIZ2_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_ECCR register  ******************/
-#define  FMC_ECCR_ECC2                     0xFFFFFFFFU        /*!<ECC result */
-
-/******************  Bit definition for FMC_SDCR1 register  ******************/
-#define  FMC_SDCR1_NC                       0x00000003U        /*!<NC[1:0] bits (Number of column bits) */
-#define  FMC_SDCR1_NC_0                     0x00000001U        /*!<Bit 0 */
-#define  FMC_SDCR1_NC_1                     0x00000002U        /*!<Bit 1 */
-
-#define  FMC_SDCR1_NR                       0x0000000CU        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR1_NR_0                     0x00000004U        /*!<Bit 0 */
-#define  FMC_SDCR1_NR_1                     0x00000008U        /*!<Bit 1 */
-
-#define  FMC_SDCR1_MWID                     0x00000030U        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR1_MWID_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDCR1_MWID_1                   0x00000020U        /*!<Bit 1 */
-
-#define  FMC_SDCR1_NB                       0x00000040U        /*!<Number of internal bank */
-
-#define  FMC_SDCR1_CAS                      0x00000180U        /*!<CAS[1:0] bits (CAS latency) */
-#define  FMC_SDCR1_CAS_0                    0x00000080U        /*!<Bit 0 */
-#define  FMC_SDCR1_CAS_1                    0x00000100U        /*!<Bit 1 */
-
-#define  FMC_SDCR1_WP                       0x00000200U        /*!<Write protection */
-
-#define  FMC_SDCR1_SDCLK                    0x00000C00U        /*!<SDRAM clock configuration */
-#define  FMC_SDCR1_SDCLK_0                  0x00000400U        /*!<Bit 0 */
-#define  FMC_SDCR1_SDCLK_1                  0x00000800U        /*!<Bit 1 */
-
-#define  FMC_SDCR1_RBURST                   0x00001000U        /*!<Read burst */
-
-#define  FMC_SDCR1_RPIPE                    0x00006000U        /*!<Write protection */
-#define  FMC_SDCR1_RPIPE_0                  0x00002000U        /*!<Bit 0 */
-#define  FMC_SDCR1_RPIPE_1                  0x00004000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_SDCR2 register  ******************/
-#define  FMC_SDCR2_NC                       0x00000003U        /*!<NC[1:0] bits (Number of column bits) */
-#define  FMC_SDCR2_NC_0                     0x00000001U        /*!<Bit 0 */
-#define  FMC_SDCR2_NC_1                     0x00000002U        /*!<Bit 1 */
-
-#define  FMC_SDCR2_NR                       0x0000000CU        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR2_NR_0                     0x00000004U        /*!<Bit 0 */
-#define  FMC_SDCR2_NR_1                     0x00000008U        /*!<Bit 1 */
-
-#define  FMC_SDCR2_MWID                     0x00000030U        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR2_MWID_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDCR2_MWID_1                   0x00000020U        /*!<Bit 1 */
-
-#define  FMC_SDCR2_NB                       0x00000040U        /*!<Number of internal bank */
-
-#define  FMC_SDCR2_CAS                      0x00000180U        /*!<CAS[1:0] bits (CAS latency) */
-#define  FMC_SDCR2_CAS_0                    0x00000080U        /*!<Bit 0 */
-#define  FMC_SDCR2_CAS_1                    0x00000100U        /*!<Bit 1 */
-
-#define  FMC_SDCR2_WP                       0x00000200U        /*!<Write protection */
-
-#define  FMC_SDCR2_SDCLK                    0x00000C00U        /*!<SDCLK[1:0] (SDRAM clock configuration) */
-#define  FMC_SDCR2_SDCLK_0                  0x00000400U        /*!<Bit 0 */
-#define  FMC_SDCR2_SDCLK_1                  0x00000800U        /*!<Bit 1 */
-
-#define  FMC_SDCR2_RBURST                   0x00001000U        /*!<Read burst */
-
-#define  FMC_SDCR2_RPIPE                    0x00006000U        /*!<RPIPE[1:0](Read pipe) */
-#define  FMC_SDCR2_RPIPE_0                  0x00002000U        /*!<Bit 0 */
-#define  FMC_SDCR2_RPIPE_1                  0x00004000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_SDTR1 register  ******************/
-#define  FMC_SDTR1_TMRD                     0x0000000FU        /*!<TMRD[3:0] bits (Load mode register to active) */
-#define  FMC_SDTR1_TMRD_0                   0x00000001U        /*!<Bit 0 */
-#define  FMC_SDTR1_TMRD_1                   0x00000002U        /*!<Bit 1 */
-#define  FMC_SDTR1_TMRD_2                   0x00000004U        /*!<Bit 2 */
-#define  FMC_SDTR1_TMRD_3                   0x00000008U        /*!<Bit 3 */
-                                            
-#define  FMC_SDTR1_TXSR                     0x000000F0U        /*!<TXSR[3:0] bits (Exit self refresh) */
-#define  FMC_SDTR1_TXSR_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDTR1_TXSR_1                   0x00000020U        /*!<Bit 1 */
-#define  FMC_SDTR1_TXSR_2                   0x00000040U        /*!<Bit 2 */
-#define  FMC_SDTR1_TXSR_3                   0x00000080U        /*!<Bit 3 */
-
-#define  FMC_SDTR1_TRAS                     0x00000F00U        /*!<TRAS[3:0] bits (Self refresh time) */
-#define  FMC_SDTR1_TRAS_0                   0x00000100U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRAS_1                   0x00000200U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRAS_2                   0x00000400U        /*!<Bit 2 */
-#define  FMC_SDTR1_TRAS_3                   0x00000800U        /*!<Bit 3 */
-
-#define  FMC_SDTR1_TRC                      0x0000F000U        /*!<TRC[2:0] bits (Row cycle delay) */
-#define  FMC_SDTR1_TRC_0                    0x00001000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRC_1                    0x00002000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRC_2                    0x00004000U        /*!<Bit 2 */
-
-#define  FMC_SDTR1_TWR                      0x000F0000U        /*!<TRC[2:0] bits (Write recovery delay) */
-#define  FMC_SDTR1_TWR_0                    0x00010000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TWR_1                    0x00020000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TWR_2                    0x00040000U        /*!<Bit 2 */
-
-#define  FMC_SDTR1_TRP                      0x00F00000U        /*!<TRP[2:0] bits (Row precharge delay) */
-#define  FMC_SDTR1_TRP_0                    0x00100000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRP_1                    0x00200000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRP_2                    0x00400000U        /*!<Bit 2 */
-
-#define  FMC_SDTR1_TRCD                     0x0F000000U        /*!<TRP[2:0] bits (Row to column delay) */
-#define  FMC_SDTR1_TRCD_0                   0x01000000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRCD_1                   0x02000000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRCD_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for FMC_SDTR2 register  ******************/
-#define  FMC_SDTR2_TMRD                     0x0000000FU        /*!<TMRD[3:0] bits (Load mode register to active) */
-#define  FMC_SDTR2_TMRD_0                   0x00000001U        /*!<Bit 0 */
-#define  FMC_SDTR2_TMRD_1                   0x00000002U        /*!<Bit 1 */
-#define  FMC_SDTR2_TMRD_2                   0x00000004U        /*!<Bit 2 */
-#define  FMC_SDTR2_TMRD_3                   0x00000008U        /*!<Bit 3 */
-                                            
-#define  FMC_SDTR2_TXSR                     0x000000F0U        /*!<TXSR[3:0] bits (Exit self refresh) */
-#define  FMC_SDTR2_TXSR_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDTR2_TXSR_1                   0x00000020U        /*!<Bit 1 */
-#define  FMC_SDTR2_TXSR_2                   0x00000040U        /*!<Bit 2 */
-#define  FMC_SDTR2_TXSR_3                   0x00000080U        /*!<Bit 3 */
-
-#define  FMC_SDTR2_TRAS                     0x00000F00U        /*!<TRAS[3:0] bits (Self refresh time) */
-#define  FMC_SDTR2_TRAS_0                   0x00000100U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRAS_1                   0x00000200U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRAS_2                   0x00000400U        /*!<Bit 2 */
-#define  FMC_SDTR2_TRAS_3                   0x00000800U        /*!<Bit 3 */
-
-#define  FMC_SDTR2_TRC                      0x0000F000U        /*!<TRC[2:0] bits (Row cycle delay) */
-#define  FMC_SDTR2_TRC_0                    0x00001000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRC_1                    0x00002000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRC_2                    0x00004000U        /*!<Bit 2 */
-
-#define  FMC_SDTR2_TWR                      0x000F0000U        /*!<TRC[2:0] bits (Write recovery delay) */
-#define  FMC_SDTR2_TWR_0                    0x00010000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TWR_1                    0x00020000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TWR_2                    0x00040000U        /*!<Bit 2 */
-
-#define  FMC_SDTR2_TRP                      0x00F00000U        /*!<TRP[2:0] bits (Row precharge delay) */
-#define  FMC_SDTR2_TRP_0                    0x00100000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRP_1                    0x00200000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRP_2                    0x00400000U        /*!<Bit 2 */
-
-#define  FMC_SDTR2_TRCD                     0x0F000000U        /*!<TRP[2:0] bits (Row to column delay) */
-#define  FMC_SDTR2_TRCD_0                   0x01000000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRCD_1                   0x02000000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRCD_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for FMC_SDCMR register  ******************/
-#define  FMC_SDCMR_MODE                     0x00000007U        /*!<MODE[2:0] bits (Command mode) */
-#define  FMC_SDCMR_MODE_0                   0x00000001U        /*!<Bit 0 */
-#define  FMC_SDCMR_MODE_1                   0x00000002U        /*!<Bit 1 */
-#define  FMC_SDCMR_MODE_2                   0x00000004U        /*!<Bit 2 */
-                                            
-#define  FMC_SDCMR_CTB2                     0x00000008U        /*!<Command target 2 */
-
-#define  FMC_SDCMR_CTB1                     0x00000010U        /*!<Command target 1 */
-
-#define  FMC_SDCMR_NRFS                     0x000001E0U        /*!<NRFS[3:0] bits (Number of auto-refresh) */
-#define  FMC_SDCMR_NRFS_0                   0x00000020U        /*!<Bit 0 */
-#define  FMC_SDCMR_NRFS_1                   0x00000040U        /*!<Bit 1 */
-#define  FMC_SDCMR_NRFS_2                   0x00000080U        /*!<Bit 2 */
-#define  FMC_SDCMR_NRFS_3                   0x00000100U        /*!<Bit 3 */
-
-#define  FMC_SDCMR_MRD                      0x003FFE00U        /*!<MRD[12:0] bits (Mode register definition) */
-
-/******************  Bit definition for FMC_SDRTR register  ******************/
-#define  FMC_SDRTR_CRE                      0x00000001U        /*!<Clear refresh error flag */
-
-#define  FMC_SDRTR_COUNT                    0x00003FFEU        /*!<COUNT[12:0] bits (Refresh timer count) */
-
-#define  FMC_SDRTR_REIE                     0x00004000U        /*!<RES interupt enable */
-
-/******************  Bit definition for FMC_SDSR register  ******************/
-#define  FMC_SDSR_RE                        0x00000001U        /*!<Refresh error flag */
-
-#define  FMC_SDSR_MODES1                    0x00000006U        /*!<MODES1[1:0]bits (Status mode for bank 1) */
-#define  FMC_SDSR_MODES1_0                  0x00000002U        /*!<Bit 0 */
-#define  FMC_SDSR_MODES1_1                  0x00000004U        /*!<Bit 1 */
-
-#define  FMC_SDSR_MODES2                    0x00000018U        /*!<MODES2[1:0]bits (Status mode for bank 2) */
-#define  FMC_SDSR_MODES2_0                  0x00000008U        /*!<Bit 0 */
-#define  FMC_SDSR_MODES2_1                  0x00000010U        /*!<Bit 1 */
-#define  FMC_SDSR_BUSY                      0x00000020U        /*!<Busy status */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    0x00000003U
-#define GPIO_MODER_MODER0_0                  0x00000001U
-#define GPIO_MODER_MODER0_1                  0x00000002U
-
-#define GPIO_MODER_MODER1                    0x0000000CU
-#define GPIO_MODER_MODER1_0                  0x00000004U
-#define GPIO_MODER_MODER1_1                  0x00000008U
-
-#define GPIO_MODER_MODER2                    0x00000030U
-#define GPIO_MODER_MODER2_0                  0x00000010U
-#define GPIO_MODER_MODER2_1                  0x00000020U
-
-#define GPIO_MODER_MODER3                    0x000000C0U
-#define GPIO_MODER_MODER3_0                  0x00000040U
-#define GPIO_MODER_MODER3_1                  0x00000080U
-
-#define GPIO_MODER_MODER4                    0x00000300U
-#define GPIO_MODER_MODER4_0                  0x00000100U
-#define GPIO_MODER_MODER4_1                  0x00000200U
-
-#define GPIO_MODER_MODER5                    0x00000C00U
-#define GPIO_MODER_MODER5_0                  0x00000400U
-#define GPIO_MODER_MODER5_1                  0x00000800U
-
-#define GPIO_MODER_MODER6                    0x00003000U
-#define GPIO_MODER_MODER6_0                  0x00001000U
-#define GPIO_MODER_MODER6_1                  0x00002000U
-
-#define GPIO_MODER_MODER7                    0x0000C000U
-#define GPIO_MODER_MODER7_0                  0x00004000U
-#define GPIO_MODER_MODER7_1                  0x00008000U
-
-#define GPIO_MODER_MODER8                    0x00030000U
-#define GPIO_MODER_MODER8_0                  0x00010000U
-#define GPIO_MODER_MODER8_1                  0x00020000U
-
-#define GPIO_MODER_MODER9                    0x000C0000U
-#define GPIO_MODER_MODER9_0                  0x00040000U
-#define GPIO_MODER_MODER9_1                  0x00080000U
-
-#define GPIO_MODER_MODER10                   0x00300000U
-#define GPIO_MODER_MODER10_0                 0x00100000U
-#define GPIO_MODER_MODER10_1                 0x00200000U
-
-#define GPIO_MODER_MODER11                   0x00C00000U
-#define GPIO_MODER_MODER11_0                 0x00400000U
-#define GPIO_MODER_MODER11_1                 0x00800000U
-
-#define GPIO_MODER_MODER12                   0x03000000U
-#define GPIO_MODER_MODER12_0                 0x01000000U
-#define GPIO_MODER_MODER12_1                 0x02000000U
-
-#define GPIO_MODER_MODER13                   0x0C000000U
-#define GPIO_MODER_MODER13_0                 0x04000000U
-#define GPIO_MODER_MODER13_1                 0x08000000U
-
-#define GPIO_MODER_MODER14                   0x30000000U
-#define GPIO_MODER_MODER14_0                 0x10000000U
-#define GPIO_MODER_MODER14_1                 0x20000000U
-
-#define GPIO_MODER_MODER15                   0xC0000000U
-#define GPIO_MODER_MODER15_0                 0x40000000U
-#define GPIO_MODER_MODER15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     0x00000001U
-#define GPIO_OTYPER_OT_1                     0x00000002U
-#define GPIO_OTYPER_OT_2                     0x00000004U
-#define GPIO_OTYPER_OT_3                     0x00000008U
-#define GPIO_OTYPER_OT_4                     0x00000010U
-#define GPIO_OTYPER_OT_5                     0x00000020U
-#define GPIO_OTYPER_OT_6                     0x00000040U
-#define GPIO_OTYPER_OT_7                     0x00000080U
-#define GPIO_OTYPER_OT_8                     0x00000100U
-#define GPIO_OTYPER_OT_9                     0x00000200U
-#define GPIO_OTYPER_OT_10                    0x00000400U
-#define GPIO_OTYPER_OT_11                    0x00000800U
-#define GPIO_OTYPER_OT_12                    0x00001000U
-#define GPIO_OTYPER_OT_13                    0x00002000U
-#define GPIO_OTYPER_OT_14                    0x00004000U
-#define GPIO_OTYPER_OT_15                    0x00008000U
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
-#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
-#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
-
-#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
-#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
-#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
-
-#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
-#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
-#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
-
-#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
-#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
-#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
-
-#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
-#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
-#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
-
-#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
-#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
-#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
-
-#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
-#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
-#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
-
-#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
-#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
-#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
-
-#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
-#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
-#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
-
-#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
-#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
-#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
-
-#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
-#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
-#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
-
-#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
-#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
-#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
-
-#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
-#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
-#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
-
-#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
-#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
-#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
-
-#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
-#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
-#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
-
-#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
-#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
-#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    0x00000003U
-#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
-#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
-
-#define GPIO_PUPDR_PUPDR1                    0x0000000CU
-#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
-#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
-
-#define GPIO_PUPDR_PUPDR2                    0x00000030U
-#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
-#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
-
-#define GPIO_PUPDR_PUPDR3                    0x000000C0U
-#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
-#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
-
-#define GPIO_PUPDR_PUPDR4                    0x00000300U
-#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
-#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
-
-#define GPIO_PUPDR_PUPDR5                    0x00000C00U
-#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
-#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
-
-#define GPIO_PUPDR_PUPDR6                    0x00003000U
-#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
-#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
-
-#define GPIO_PUPDR_PUPDR7                    0x0000C000U
-#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
-#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
-
-#define GPIO_PUPDR_PUPDR8                    0x00030000U
-#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
-#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
-
-#define GPIO_PUPDR_PUPDR9                    0x000C0000U
-#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
-#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
-
-#define GPIO_PUPDR_PUPDR10                   0x00300000U
-#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
-#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
-
-#define GPIO_PUPDR_PUPDR11                   0x00C00000U
-#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
-#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
-
-#define GPIO_PUPDR_PUPDR12                   0x03000000U
-#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
-#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
-
-#define GPIO_PUPDR_PUPDR13                   0x0C000000U
-#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
-#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
-
-#define GPIO_PUPDR_PUPDR14                   0x30000000U
-#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
-#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
-
-#define GPIO_PUPDR_PUPDR15                   0xC0000000U
-#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
-#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       0x00000001U
-#define GPIO_IDR_IDR_1                       0x00000002U
-#define GPIO_IDR_IDR_2                       0x00000004U
-#define GPIO_IDR_IDR_3                       0x00000008U
-#define GPIO_IDR_IDR_4                       0x00000010U
-#define GPIO_IDR_IDR_5                       0x00000020U
-#define GPIO_IDR_IDR_6                       0x00000040U
-#define GPIO_IDR_IDR_7                       0x00000080U
-#define GPIO_IDR_IDR_8                       0x00000100U
-#define GPIO_IDR_IDR_9                       0x00000200U
-#define GPIO_IDR_IDR_10                      0x00000400U
-#define GPIO_IDR_IDR_11                      0x00000800U
-#define GPIO_IDR_IDR_12                      0x00001000U
-#define GPIO_IDR_IDR_13                      0x00002000U
-#define GPIO_IDR_IDR_14                      0x00004000U
-#define GPIO_IDR_IDR_15                      0x00008000U
-/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
-#define GPIO_OTYPER_IDR_0                    GPIO_IDR_IDR_0
-#define GPIO_OTYPER_IDR_1                    GPIO_IDR_IDR_1
-#define GPIO_OTYPER_IDR_2                    GPIO_IDR_IDR_2
-#define GPIO_OTYPER_IDR_3                    GPIO_IDR_IDR_3
-#define GPIO_OTYPER_IDR_4                    GPIO_IDR_IDR_4
-#define GPIO_OTYPER_IDR_5                    GPIO_IDR_IDR_5
-#define GPIO_OTYPER_IDR_6                    GPIO_IDR_IDR_6
-#define GPIO_OTYPER_IDR_7                    GPIO_IDR_IDR_7
-#define GPIO_OTYPER_IDR_8                    GPIO_IDR_IDR_8
-#define GPIO_OTYPER_IDR_9                    GPIO_IDR_IDR_9
-#define GPIO_OTYPER_IDR_10                   GPIO_IDR_IDR_10
-#define GPIO_OTYPER_IDR_11                   GPIO_IDR_IDR_11
-#define GPIO_OTYPER_IDR_12                   GPIO_IDR_IDR_12
-#define GPIO_OTYPER_IDR_13                   GPIO_IDR_IDR_13
-#define GPIO_OTYPER_IDR_14                   GPIO_IDR_IDR_14
-#define GPIO_OTYPER_IDR_15                   GPIO_IDR_IDR_15
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       0x00000001U
-#define GPIO_ODR_ODR_1                       0x00000002U
-#define GPIO_ODR_ODR_2                       0x00000004U
-#define GPIO_ODR_ODR_3                       0x00000008U
-#define GPIO_ODR_ODR_4                       0x00000010U
-#define GPIO_ODR_ODR_5                       0x00000020U
-#define GPIO_ODR_ODR_6                       0x00000040U
-#define GPIO_ODR_ODR_7                       0x00000080U
-#define GPIO_ODR_ODR_8                       0x00000100U
-#define GPIO_ODR_ODR_9                       0x00000200U
-#define GPIO_ODR_ODR_10                      0x00000400U
-#define GPIO_ODR_ODR_11                      0x00000800U
-#define GPIO_ODR_ODR_12                      0x00001000U
-#define GPIO_ODR_ODR_13                      0x00002000U
-#define GPIO_ODR_ODR_14                      0x00004000U
-#define GPIO_ODR_ODR_15                      0x00008000U
-/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
-#define GPIO_OTYPER_ODR_0                    GPIO_ODR_ODR_0
-#define GPIO_OTYPER_ODR_1                    GPIO_ODR_ODR_1
-#define GPIO_OTYPER_ODR_2                    GPIO_ODR_ODR_2
-#define GPIO_OTYPER_ODR_3                    GPIO_ODR_ODR_3
-#define GPIO_OTYPER_ODR_4                    GPIO_ODR_ODR_4
-#define GPIO_OTYPER_ODR_5                    GPIO_ODR_ODR_5
-#define GPIO_OTYPER_ODR_6                    GPIO_ODR_ODR_6
-#define GPIO_OTYPER_ODR_7                    GPIO_ODR_ODR_7
-#define GPIO_OTYPER_ODR_8                    GPIO_ODR_ODR_8
-#define GPIO_OTYPER_ODR_9                    GPIO_ODR_ODR_9
-#define GPIO_OTYPER_ODR_10                   GPIO_ODR_ODR_10
-#define GPIO_OTYPER_ODR_11                   GPIO_ODR_ODR_11
-#define GPIO_OTYPER_ODR_12                   GPIO_ODR_ODR_12
-#define GPIO_OTYPER_ODR_13                   GPIO_ODR_ODR_13
-#define GPIO_OTYPER_ODR_14                   GPIO_ODR_ODR_14
-#define GPIO_OTYPER_ODR_15                   GPIO_ODR_ODR_15
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       0x00000001U
-#define GPIO_BSRR_BS_1                       0x00000002U
-#define GPIO_BSRR_BS_2                       0x00000004U
-#define GPIO_BSRR_BS_3                       0x00000008U
-#define GPIO_BSRR_BS_4                       0x00000010U
-#define GPIO_BSRR_BS_5                       0x00000020U
-#define GPIO_BSRR_BS_6                       0x00000040U
-#define GPIO_BSRR_BS_7                       0x00000080U
-#define GPIO_BSRR_BS_8                       0x00000100U
-#define GPIO_BSRR_BS_9                       0x00000200U
-#define GPIO_BSRR_BS_10                      0x00000400U
-#define GPIO_BSRR_BS_11                      0x00000800U
-#define GPIO_BSRR_BS_12                      0x00001000U
-#define GPIO_BSRR_BS_13                      0x00002000U
-#define GPIO_BSRR_BS_14                      0x00004000U
-#define GPIO_BSRR_BS_15                      0x00008000U
-#define GPIO_BSRR_BR_0                       0x00010000U
-#define GPIO_BSRR_BR_1                       0x00020000U
-#define GPIO_BSRR_BR_2                       0x00040000U
-#define GPIO_BSRR_BR_3                       0x00080000U
-#define GPIO_BSRR_BR_4                       0x00100000U
-#define GPIO_BSRR_BR_5                       0x00200000U
-#define GPIO_BSRR_BR_6                       0x00400000U
-#define GPIO_BSRR_BR_7                       0x00800000U
-#define GPIO_BSRR_BR_8                       0x01000000U
-#define GPIO_BSRR_BR_9                       0x02000000U
-#define GPIO_BSRR_BR_10                      0x04000000U
-#define GPIO_BSRR_BR_11                      0x08000000U
-#define GPIO_BSRR_BR_12                      0x10000000U
-#define GPIO_BSRR_BR_13                      0x20000000U
-#define GPIO_BSRR_BR_14                      0x40000000U
-#define GPIO_BSRR_BR_15                      0x80000000U
-
-/****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0                       0x00000001U
-#define GPIO_LCKR_LCK1                       0x00000002U
-#define GPIO_LCKR_LCK2                       0x00000004U
-#define GPIO_LCKR_LCK3                       0x00000008U
-#define GPIO_LCKR_LCK4                       0x00000010U
-#define GPIO_LCKR_LCK5                       0x00000020U
-#define GPIO_LCKR_LCK6                       0x00000040U
-#define GPIO_LCKR_LCK7                       0x00000080U
-#define GPIO_LCKR_LCK8                       0x00000100U
-#define GPIO_LCKR_LCK9                       0x00000200U
-#define GPIO_LCKR_LCK10                      0x00000400U
-#define GPIO_LCKR_LCK11                      0x00000800U
-#define GPIO_LCKR_LCK12                      0x00001000U
-#define GPIO_LCKR_LCK13                      0x00002000U
-#define GPIO_LCKR_LCK14                      0x00004000U
-#define GPIO_LCKR_LCK15                      0x00008000U
-#define GPIO_LCKR_LCKK                       0x00010000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    HASH                                    */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for HASH_CR register  ********************/
-#define HASH_CR_INIT                         0x00000004U
-#define HASH_CR_DMAE                         0x00000008U
-#define HASH_CR_DATATYPE                     0x00000030U
-#define HASH_CR_DATATYPE_0                   0x00000010U
-#define HASH_CR_DATATYPE_1                   0x00000020U
-#define HASH_CR_MODE                         0x00000040U
-#define HASH_CR_ALGO                         0x00040080U
-#define HASH_CR_ALGO_0                       0x00000080U
-#define HASH_CR_ALGO_1                       0x00040000U
-#define HASH_CR_NBW                          0x00000F00U
-#define HASH_CR_NBW_0                        0x00000100U
-#define HASH_CR_NBW_1                        0x00000200U
-#define HASH_CR_NBW_2                        0x00000400U
-#define HASH_CR_NBW_3                        0x00000800U
-#define HASH_CR_DINNE                        0x00001000U
-#define HASH_CR_MDMAT                        0x00002000U
-#define HASH_CR_LKEY                         0x00010000U
-
-/******************  Bits definition for HASH_STR register  *******************/
-#define HASH_STR_NBLW                        0x0000001FU
-#define HASH_STR_NBLW_0                      0x00000001U
-#define HASH_STR_NBLW_1                      0x00000002U
-#define HASH_STR_NBLW_2                      0x00000004U
-#define HASH_STR_NBLW_3                      0x00000008U
-#define HASH_STR_NBLW_4                      0x00000010U
-#define HASH_STR_DCAL                        0x00000100U
-/* Aliases for HASH_STR register */
-#define HASH_STR_NBW                         HASH_STR_NBLW
-#define HASH_STR_NBW_0                       HASH_STR_NBLW_0
-#define HASH_STR_NBW_1                       HASH_STR_NBLW_1
-#define HASH_STR_NBW_2                       HASH_STR_NBLW_2
-#define HASH_STR_NBW_3                       HASH_STR_NBLW_3
-#define HASH_STR_NBW_4                       HASH_STR_NBLW_4
-
-/******************  Bits definition for HASH_IMR register  *******************/
-#define HASH_IMR_DINIE                       0x00000001U
-#define HASH_IMR_DCIE                        0x00000002U
-/* Aliases for HASH_IMR register */
-#define HASH_IMR_DINIM                       HASH_IMR_DINIE
-#define HASH_IMR_DCIM                        HASH_IMR_DCIE
-
-/******************  Bits definition for HASH_SR register  ********************/
-#define HASH_SR_DINIS                        0x00000001U
-#define HASH_SR_DCIS                         0x00000002U
-#define HASH_SR_DMAS                         0x00000004U
-#define HASH_SR_BUSY                         0x00000008U
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Inter-integrated Circuit Interface                    */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          0x00000001U     /*!<Peripheral Enable                             */
-#define  I2C_CR1_SMBUS                       0x00000002U     /*!<SMBus Mode                                    */
-#define  I2C_CR1_SMBTYPE                     0x00000008U     /*!<SMBus Type                                    */
-#define  I2C_CR1_ENARP                       0x00000010U     /*!<ARP Enable                                    */
-#define  I2C_CR1_ENPEC                       0x00000020U     /*!<PEC Enable                                    */
-#define  I2C_CR1_ENGC                        0x00000040U     /*!<General Call Enable                           */
-#define  I2C_CR1_NOSTRETCH                   0x00000080U     /*!<Clock Stretching Disable (Slave mode)  */
-#define  I2C_CR1_START                       0x00000100U     /*!<Start Generation                              */
-#define  I2C_CR1_STOP                        0x00000200U     /*!<Stop Generation                               */
-#define  I2C_CR1_ACK                         0x00000400U     /*!<Acknowledge Enable                            */
-#define  I2C_CR1_POS                         0x00000800U     /*!<Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         0x00001000U     /*!<Packet Error Checking                         */
-#define  I2C_CR1_ALERT                       0x00002000U     /*!<SMBus Alert                                   */
-#define  I2C_CR1_SWRST                       0x00008000U     /*!<Software Reset                                */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        0x0000003FU     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
-#define  I2C_CR2_FREQ_0                      0x00000001U     /*!<Bit 0 */
-#define  I2C_CR2_FREQ_1                      0x00000002U     /*!<Bit 1 */
-#define  I2C_CR2_FREQ_2                      0x00000004U     /*!<Bit 2 */
-#define  I2C_CR2_FREQ_3                      0x00000008U     /*!<Bit 3 */
-#define  I2C_CR2_FREQ_4                      0x00000010U     /*!<Bit 4 */
-#define  I2C_CR2_FREQ_5                      0x00000020U     /*!<Bit 5 */
-
-#define  I2C_CR2_ITERREN                     0x00000100U     /*!<Error Interrupt Enable  */
-#define  I2C_CR2_ITEVTEN                     0x00000200U     /*!<Event Interrupt Enable  */
-#define  I2C_CR2_ITBUFEN                     0x00000400U     /*!<Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       0x00000800U     /*!<DMA Requests Enable     */
-#define  I2C_CR2_LAST                        0x00001000U     /*!<DMA Last Transfer       */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     0x000000FEU     /*!<Interface Address */
-#define  I2C_OAR1_ADD8_9                     0x00000300U     /*!<Interface Address */
-
-#define  I2C_OAR1_ADD0                       0x00000001U     /*!<Bit 0 */
-#define  I2C_OAR1_ADD1                       0x00000002U     /*!<Bit 1 */
-#define  I2C_OAR1_ADD2                       0x00000004U     /*!<Bit 2 */
-#define  I2C_OAR1_ADD3                       0x00000008U     /*!<Bit 3 */
-#define  I2C_OAR1_ADD4                       0x00000010U     /*!<Bit 4 */
-#define  I2C_OAR1_ADD5                       0x00000020U     /*!<Bit 5 */
-#define  I2C_OAR1_ADD6                       0x00000040U     /*!<Bit 6 */
-#define  I2C_OAR1_ADD7                       0x00000080U     /*!<Bit 7 */
-#define  I2C_OAR1_ADD8                       0x00000100U     /*!<Bit 8 */
-#define  I2C_OAR1_ADD9                       0x00000200U     /*!<Bit 9 */
-
-#define  I2C_OAR1_ADDMODE                    0x00008000U     /*!<Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     0x00000001U        /*!<Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       0x000000FEU        /*!<Interface address           */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           0x000000FFU        /*!<8-bit Data Register         */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          0x00000001U     /*!<Start Bit (Master mode)                  */
-#define  I2C_SR1_ADDR                        0x00000002U     /*!<Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         0x00000004U     /*!<Byte Transfer Finished                          */
-#define  I2C_SR1_ADD10                       0x00000008U     /*!<10-bit header sent (Master mode)         */
-#define  I2C_SR1_STOPF                       0x00000010U     /*!<Stop detection (Slave mode)              */
-#define  I2C_SR1_RXNE                        0x00000040U     /*!<Data Register not Empty (receivers)      */
-#define  I2C_SR1_TXE                         0x00000080U     /*!<Data Register Empty (transmitters)       */
-#define  I2C_SR1_BERR                        0x00000100U     /*!<Bus Error                                       */
-#define  I2C_SR1_ARLO                        0x00000200U     /*!<Arbitration Lost (master mode)           */
-#define  I2C_SR1_AF                          0x00000400U     /*!<Acknowledge Failure                             */
-#define  I2C_SR1_OVR                         0x00000800U     /*!<Overrun/Underrun                                */
-#define  I2C_SR1_PECERR                      0x00001000U     /*!<PEC Error in reception                          */
-#define  I2C_SR1_TIMEOUT                     0x00004000U     /*!<Timeout or Tlow Error                           */
-#define  I2C_SR1_SMBALERT                    0x00008000U     /*!<SMBus Alert                                     */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         0x00000001U     /*!<Master/Slave                              */
-#define  I2C_SR2_BUSY                        0x00000002U     /*!<Bus Busy                                  */
-#define  I2C_SR2_TRA                         0x00000004U     /*!<Transmitter/Receiver                      */
-#define  I2C_SR2_GENCALL                     0x00000010U     /*!<General Call Address (Slave mode)  */
-#define  I2C_SR2_SMBDEFAULT                  0x00000020U     /*!<SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     0x00000040U     /*!<SMBus Host Header (Slave mode)     */
-#define  I2C_SR2_DUALF                       0x00000080U     /*!<Dual Flag (Slave mode)             */
-#define  I2C_SR2_PEC                         0x0000FF00U     /*!<Packet Error Checking Register            */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         0x00000FFFU     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        0x00004000U     /*!<Fast Mode Duty Cycle                                       */
-#define  I2C_CCR_FS                          0x00008000U     /*!<I2C Master Mode Selection                                  */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     0x0000003FU     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************  Bit definition for I2C_FLTR register  *******************/
-#define  I2C_FLTR_DNF                        0x0000000FU     /*!<Digital Noise Filter */
-#define  I2C_FLTR_ANOFF                      0x00000010U     /*!<Analog Noise Filter OFF */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Independent WATCHDOG                             */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         0x01U               /*!<Watchdog prescaler value update      */
-#define  IWDG_SR_RVU                         0x02U               /*!<Watchdog counter reload value update */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                      LCD-TFT Display Controller (LTDC)                     */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for LTDC_SSCR register  *****************/
-
-#define LTDC_SSCR_VSH                       0x000007FFU              /*!< Vertical Synchronization Height */
-#define LTDC_SSCR_HSW                       0x0FFF0000U              /*!< Horizontal Synchronization Width */
-
-/********************  Bit definition for LTDC_BPCR register  *****************/
-
-#define LTDC_BPCR_AVBP                      0x000007FFU              /*!< Accumulated Vertical Back Porch */
-#define LTDC_BPCR_AHBP                      0x0FFF0000U              /*!< Accumulated Horizontal Back Porch */
-
-/********************  Bit definition for LTDC_AWCR register  *****************/
-
-#define LTDC_AWCR_AAH                       0x000007FFU              /*!< Accumulated Active heigh */
-#define LTDC_AWCR_AAW                       0x0FFF0000U              /*!< Accumulated Active Width */
-
-/********************  Bit definition for LTDC_TWCR register  *****************/
-
-#define LTDC_TWCR_TOTALH                    0x000007FFU              /*!< Total Heigh */
-#define LTDC_TWCR_TOTALW                    0x0FFF0000U              /*!< Total Width */
-
-/********************  Bit definition for LTDC_GCR register  ******************/
-
-#define LTDC_GCR_LTDCEN                     0x00000001U              /*!< LCD-TFT controller enable bit */
-#define LTDC_GCR_DBW                        0x00000070U              /*!< Dither Blue Width */
-#define LTDC_GCR_DGW                        0x00000700U              /*!< Dither Green Width */
-#define LTDC_GCR_DRW                        0x00007000U              /*!< Dither Red Width */
-#define LTDC_GCR_DEN                        0x00010000U              /*!< Dither Enable */
-#define LTDC_GCR_PCPOL                      0x10000000U              /*!< Pixel Clock Polarity */
-#define LTDC_GCR_DEPOL                      0x20000000U              /*!< Data Enable Polarity */
-#define LTDC_GCR_VSPOL                      0x40000000U              /*!< Vertical Synchronization Polarity */
-#define LTDC_GCR_HSPOL                      0x80000000U              /*!< Horizontal Synchronization Polarity */
-
-/* Legacy defines */
-#define LTDC_GCR_DTEN                       LTDC_GCR_DEN
-
-/********************  Bit definition for LTDC_SRCR register  *****************/
-
-#define LTDC_SRCR_IMR                      0x00000001U               /*!< Immediate Reload */
-#define LTDC_SRCR_VBR                      0x00000002U               /*!< Vertical Blanking Reload */
-
-/********************  Bit definition for LTDC_BCCR register  *****************/
-
-#define LTDC_BCCR_BCBLUE                    0x000000FFU              /*!< Background Blue value */
-#define LTDC_BCCR_BCGREEN                   0x0000FF00U              /*!< Background Green value */
-#define LTDC_BCCR_BCRED                     0x00FF0000U              /*!< Background Red value */
-
-/********************  Bit definition for LTDC_IER register  ******************/
-
-#define LTDC_IER_LIE                        0x00000001U              /*!< Line Interrupt Enable */
-#define LTDC_IER_FUIE                       0x00000002U              /*!< FIFO Underrun Interrupt Enable */
-#define LTDC_IER_TERRIE                     0x00000004U              /*!< Transfer Error Interrupt Enable */
-#define LTDC_IER_RRIE                       0x00000008U              /*!< Register Reload interrupt enable */
-
-/********************  Bit definition for LTDC_ISR register  ******************/
-
-#define LTDC_ISR_LIF                        0x00000001U              /*!< Line Interrupt Flag */
-#define LTDC_ISR_FUIF                       0x00000002U              /*!< FIFO Underrun Interrupt Flag */
-#define LTDC_ISR_TERRIF                     0x00000004U              /*!< Transfer Error Interrupt Flag */
-#define LTDC_ISR_RRIF                       0x00000008U              /*!< Register Reload interrupt Flag */
-
-/********************  Bit definition for LTDC_ICR register  ******************/
-
-#define LTDC_ICR_CLIF                       0x00000001U              /*!< Clears the Line Interrupt Flag */
-#define LTDC_ICR_CFUIF                      0x00000002U              /*!< Clears the FIFO Underrun Interrupt Flag */
-#define LTDC_ICR_CTERRIF                    0x00000004U              /*!< Clears the Transfer Error Interrupt Flag */
-#define LTDC_ICR_CRRIF                      0x00000008U              /*!< Clears Register Reload interrupt Flag */
-
-/********************  Bit definition for LTDC_LIPCR register  ****************/
-
-#define LTDC_LIPCR_LIPOS                    0x000007FFU              /*!< Line Interrupt Position */
-
-/********************  Bit definition for LTDC_CPSR register  *****************/
-
-#define LTDC_CPSR_CYPOS                     0x0000FFFFU              /*!< Current Y Position */
-#define LTDC_CPSR_CXPOS                     0xFFFF0000U              /*!< Current X Position */
-
-/********************  Bit definition for LTDC_CDSR register  *****************/
-
-#define LTDC_CDSR_VDES                      0x00000001U              /*!< Vertical Data Enable Status */
-#define LTDC_CDSR_HDES                      0x00000002U              /*!< Horizontal Data Enable Status */
-#define LTDC_CDSR_VSYNCS                    0x00000004U              /*!< Vertical Synchronization Status */
-#define LTDC_CDSR_HSYNCS                    0x00000008U              /*!< Horizontal Synchronization Status */
-
-/********************  Bit definition for LTDC_LxCR register  *****************/
-
-#define LTDC_LxCR_LEN                       0x00000001U              /*!< Layer Enable */
-#define LTDC_LxCR_COLKEN                    0x00000002U              /*!< Color Keying Enable */
-#define LTDC_LxCR_CLUTEN                    0x00000010U              /*!< Color Lockup Table Enable */
-
-/********************  Bit definition for LTDC_LxWHPCR register  **************/
-
-#define LTDC_LxWHPCR_WHSTPOS                0x00000FFFU              /*!< Window Horizontal Start Position */
-#define LTDC_LxWHPCR_WHSPPOS                0xFFFF0000U              /*!< Window Horizontal Stop Position */
-
-/********************  Bit definition for LTDC_LxWVPCR register  **************/
-
-#define LTDC_LxWVPCR_WVSTPOS                0x00000FFFU              /*!< Window Vertical Start Position */
-#define LTDC_LxWVPCR_WVSPPOS                0xFFFF0000U              /*!< Window Vertical Stop Position */
-
-/********************  Bit definition for LTDC_LxCKCR register  ***************/
-
-#define LTDC_LxCKCR_CKBLUE                  0x000000FFU              /*!< Color Key Blue value */
-#define LTDC_LxCKCR_CKGREEN                 0x0000FF00U              /*!< Color Key Green value */
-#define LTDC_LxCKCR_CKRED                   0x00FF0000U              /*!< Color Key Red value */
-
-/********************  Bit definition for LTDC_LxPFCR register  ***************/
-
-#define LTDC_LxPFCR_PF                      0x00000007U              /*!< Pixel Format */
-
-/********************  Bit definition for LTDC_LxCACR register  ***************/
-
-#define LTDC_LxCACR_CONSTA                  0x000000FFU              /*!< Constant Alpha */
-
-/********************  Bit definition for LTDC_LxDCCR register  ***************/
-
-#define LTDC_LxDCCR_DCBLUE                  0x000000FFU              /*!< Default Color Blue */
-#define LTDC_LxDCCR_DCGREEN                 0x0000FF00U              /*!< Default Color Green */
-#define LTDC_LxDCCR_DCRED                   0x00FF0000U              /*!< Default Color Red */
-#define LTDC_LxDCCR_DCALPHA                 0xFF000000U              /*!< Default Color Alpha */
-                                
-/********************  Bit definition for LTDC_LxBFCR register  ***************/
-
-#define LTDC_LxBFCR_BF2                     0x00000007U              /*!< Blending Factor 2 */
-#define LTDC_LxBFCR_BF1                     0x00000700U              /*!< Blending Factor 1 */
-
-/********************  Bit definition for LTDC_LxCFBAR register  **************/
-
-#define LTDC_LxCFBAR_CFBADD                 0xFFFFFFFFU              /*!< Color Frame Buffer Start Address */
-
-/********************  Bit definition for LTDC_LxCFBLR register  **************/
-
-#define LTDC_LxCFBLR_CFBLL                  0x00001FFFU              /*!< Color Frame Buffer Line Length */
-#define LTDC_LxCFBLR_CFBP                   0x1FFF0000U              /*!< Color Frame Buffer Pitch in bytes */
-
-/********************  Bit definition for LTDC_LxCFBLNR register  *************/
-
-#define LTDC_LxCFBLNR_CFBLNBR               0x000007FFU              /*!< Frame Buffer Line Number */
-
-/********************  Bit definition for LTDC_LxCLUTWR register  *************/
-
-#define LTDC_LxCLUTWR_BLUE                  0x000000FFU              /*!< Blue value */
-#define LTDC_LxCLUTWR_GREEN                 0x0000FF00U              /*!< Green value */
-#define LTDC_LxCLUTWR_RED                   0x00FF0000U              /*!< Red value */
-#define LTDC_LxCLUTWR_CLUTADD               0xFF000000U              /*!< CLUT address */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                             Power Control                                  */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
-#define  PWR_CR_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
-#define  PWR_CR_CWUF                         0x00000004U     /*!< Clear Wakeup Flag                   */
-#define  PWR_CR_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
-#define  PWR_CR_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
-
-#define  PWR_CR_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        0x00000020U     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        0x00000040U     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        0x00000080U     /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
-#define  PWR_CR_DBP                          0x00000100U     /*!< Disable Backup Domain write protection                     */
-#define  PWR_CR_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                              */
-#define  PWR_CR_LPLVDS                       0x00000400U     /*!< Low-Power Regulator Low Voltage Scaling in Stop mode       */
-#define  PWR_CR_MRLVDS                       0x00000800U     /*!< Main regulator Low Voltage Scaling in Stop mode            */
-#define  PWR_CR_ADCDC1                       0x00002000U     /*!< Refer to AN4073 on how to use this bit */ 
-#define  PWR_CR_VOS                          0x0000C000U     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
-#define  PWR_CR_VOS_0                        0x00004000U     /*!< Bit 0 */
-#define  PWR_CR_VOS_1                        0x00008000U     /*!< Bit 1 */
-#define  PWR_CR_ODEN                         0x00010000U     /*!< Over Drive enable                   */
-#define  PWR_CR_ODSWEN                       0x00020000U     /*!< Over Drive switch enabled           */
-#define  PWR_CR_UDEN                         0x000C0000U     /*!< Under Drive enable in stop mode     */
-#define  PWR_CR_UDEN_0                       0x00040000U     /*!< Bit 0                               */
-#define  PWR_CR_UDEN_1                       0x00080000U     /*!< Bit 1                               */
-
-/* Legacy define */
-#define  PWR_CR_PMODE                        PWR_CR_VOS
-#define  PWR_CR_LPUDS                        PWR_CR_LPLVDS     /*!< Low-Power Regulator in deepsleep under-drive mode        */
-#define  PWR_CR_MRUDS                        PWR_CR_MRLVDS     /*!< Main regulator in deepsleep under-drive mode             */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         0x00000001U     /*!< Wakeup Flag                                      */
-#define  PWR_CSR_SBF                         0x00000002U     /*!< Standby Flag                                     */
-#define  PWR_CSR_PVDO                        0x00000004U     /*!< PVD Output                                       */
-#define  PWR_CSR_BRR                         0x00000008U     /*!< Backup regulator ready                           */
-#define  PWR_CSR_WUPP                        0x00000080U     /*!< WKUP pin Polarity                                */
-#define  PWR_CSR_EWUP                        0x00000100U     /*!< Enable WKUP pin                                  */
-#define  PWR_CSR_BRE                         0x00000200U     /*!< Backup regulator enable                          */
-#define  PWR_CSR_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
-#define  PWR_CSR_ODRDY                       0x00010000U     /*!< Over Drive generator ready                       */
-#define  PWR_CSR_ODSWRDY                     0x00020000U     /*!< Over Drive Switch ready                          */
-#define  PWR_CSR_UDSWRDY                     0x000C0000U     /*!< Under Drive ready                                */
-
-/* Legacy define */
-#define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    QUADSPI                                 */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for QUADSPI_CR register  *******************/
-#define  QUADSPI_CR_EN                           0x00000001U            /*!< Enable                             */
-#define  QUADSPI_CR_ABORT                        0x00000002U            /*!< Abort request                      */
-#define  QUADSPI_CR_DMAEN                        0x00000004U            /*!< DMA Enable                         */
-#define  QUADSPI_CR_TCEN                         0x00000008U            /*!< Timeout Counter Enable             */
-#define  QUADSPI_CR_SSHIFT                       0x00000010U            /*!< SSHIFT Sample Shift                */
-#define  QUADSPI_CR_DFM                          0x00000040U            /*!< Dual Flash Mode                    */
-#define  QUADSPI_CR_FSEL                         0x00000080U            /*!< Flash Select                       */
-#define  QUADSPI_CR_FTHRES                       0x00001F00U            /*!< FTHRES[3:0] FIFO Level             */
-#define  QUADSPI_CR_FTHRES_0                     0x00000100U            /*!< Bit 0 */
-#define  QUADSPI_CR_FTHRES_1                     0x00000200U            /*!< Bit 1 */
-#define  QUADSPI_CR_FTHRES_2                     0x00000400U            /*!< Bit 2 */
-#define  QUADSPI_CR_FTHRES_3                     0x00000800U            /*!< Bit 3 */
-#define  QUADSPI_CR_FTHRES_4                     0x00001000U            /*!< Bit 4 */
-#define  QUADSPI_CR_TEIE                         0x00010000U            /*!< Transfer Error Interrupt Enable    */
-#define  QUADSPI_CR_TCIE                         0x00020000U            /*!< Transfer Complete Interrupt Enable */
-#define  QUADSPI_CR_FTIE                         0x00040000U            /*!< FIFO Threshold Interrupt Enable    */
-#define  QUADSPI_CR_SMIE                         0x00080000U            /*!< Status Match Interrupt Enable      */
-#define  QUADSPI_CR_TOIE                         0x00100000U            /*!< TimeOut Interrupt Enable           */
-#define  QUADSPI_CR_APMS                         0x00400000U            /*!< Bit 1 */
-#define  QUADSPI_CR_PMM                          0x00800000U            /*!< Polling Match Mode                 */
-#define  QUADSPI_CR_PRESCALER                    0xFF000000U            /*!< PRESCALER[7:0] Clock prescaler     */
-#define  QUADSPI_CR_PRESCALER_0                  0x01000000U            /*!< Bit 0 */
-#define  QUADSPI_CR_PRESCALER_1                  0x02000000U            /*!< Bit 1 */
-#define  QUADSPI_CR_PRESCALER_2                  0x04000000U            /*!< Bit 2 */
-#define  QUADSPI_CR_PRESCALER_3                  0x08000000U            /*!< Bit 3 */
-#define  QUADSPI_CR_PRESCALER_4                  0x10000000U            /*!< Bit 4 */
-#define  QUADSPI_CR_PRESCALER_5                  0x20000000U            /*!< Bit 5 */
-#define  QUADSPI_CR_PRESCALER_6                  0x40000000U            /*!< Bit 6 */
-#define  QUADSPI_CR_PRESCALER_7                  0x80000000U            /*!< Bit 7 */
-
-/*****************  Bit definition for QUADSPI_DCR register  ******************/
-#define  QUADSPI_DCR_CKMODE                      0x00000001U            /*!< Mode 0 / Mode 3                 */
-#define  QUADSPI_DCR_CSHT                        0x00000700U            /*!< CSHT[2:0]: ChipSelect High Time */
-#define  QUADSPI_DCR_CSHT_0                      0x00000100U            /*!< Bit 0 */
-#define  QUADSPI_DCR_CSHT_1                      0x00000200U            /*!< Bit 1 */
-#define  QUADSPI_DCR_CSHT_2                      0x00000400U            /*!< Bit 2 */
-#define  QUADSPI_DCR_FSIZE                       0x001F0000U            /*!< FSIZE[4:0]: Flash Size          */
-#define  QUADSPI_DCR_FSIZE_0                     0x00010000U            /*!< Bit 0 */
-#define  QUADSPI_DCR_FSIZE_1                     0x00020000U            /*!< Bit 1 */
-#define  QUADSPI_DCR_FSIZE_2                     0x00040000U            /*!< Bit 2 */
-#define  QUADSPI_DCR_FSIZE_3                     0x00080000U            /*!< Bit 3 */
-#define  QUADSPI_DCR_FSIZE_4                     0x00100000U            /*!< Bit 4 */
-
-/******************  Bit definition for QUADSPI_SR register  *******************/
-#define  QUADSPI_SR_TEF                          0x00000001U             /*!< Transfer Error Flag    */
-#define  QUADSPI_SR_TCF                          0x00000002U             /*!< Transfer Complete Flag */
-#define  QUADSPI_SR_FTF                          0x00000004U             /*!< FIFO Threshlod Flag    */
-#define  QUADSPI_SR_SMF                          0x00000008U             /*!< Status Match Flag      */
-#define  QUADSPI_SR_TOF                          0x00000010U             /*!< Timeout Flag           */
-#define  QUADSPI_SR_BUSY                         0x00000020U             /*!< Busy                   */
-#define  QUADSPI_SR_FLEVEL                       0x00003F00U             /*!< FIFO Threshlod Flag    */
-#define  QUADSPI_SR_FLEVEL_0                     0x00000100U             /*!< Bit 0 */
-#define  QUADSPI_SR_FLEVEL_1                     0x00000200U             /*!< Bit 1 */
-#define  QUADSPI_SR_FLEVEL_2                     0x00000400U             /*!< Bit 2 */
-#define  QUADSPI_SR_FLEVEL_3                     0x00000800U             /*!< Bit 3 */
-#define  QUADSPI_SR_FLEVEL_4                     0x00001000U             /*!< Bit 4 */
-#define  QUADSPI_SR_FLEVEL_5                     0x00002000U             /*!< Bit 5 */
-
-/******************  Bit definition for QUADSPI_FCR register  ******************/
-#define  QUADSPI_FCR_CTEF                        0x00000001U             /*!< Clear Transfer Error Flag    */
-#define  QUADSPI_FCR_CTCF                        0x00000002U             /*!< Clear Transfer Complete Flag */
-#define  QUADSPI_FCR_CSMF                        0x00000008U             /*!< Clear Status Match Flag      */
-#define  QUADSPI_FCR_CTOF                        0x00000010U             /*!< Clear Timeout Flag           */
-
-/******************  Bit definition for QUADSPI_DLR register  ******************/
-#define  QUADSPI_DLR_DL                        0xFFFFFFFFU               /*!< DL[31:0]: Data Length */
-
-/******************  Bit definition for QUADSPI_CCR register  ******************/
-#define  QUADSPI_CCR_INSTRUCTION                  0x000000FFU            /*!< INSTRUCTION[7:0]: Instruction */
-#define  QUADSPI_CCR_INSTRUCTION_0                0x00000001U            /*!< Bit 0 */
-#define  QUADSPI_CCR_INSTRUCTION_1                0x00000002U            /*!< Bit 1 */
-#define  QUADSPI_CCR_INSTRUCTION_2                0x00000004U            /*!< Bit 2 */
-#define  QUADSPI_CCR_INSTRUCTION_3                0x00000008U            /*!< Bit 3 */
-#define  QUADSPI_CCR_INSTRUCTION_4                0x00000010U            /*!< Bit 4 */
-#define  QUADSPI_CCR_INSTRUCTION_5                0x00000020U            /*!< Bit 5 */
-#define  QUADSPI_CCR_INSTRUCTION_6                0x00000040U            /*!< Bit 6 */
-#define  QUADSPI_CCR_INSTRUCTION_7                0x00000080U            /*!< Bit 7 */
-#define  QUADSPI_CCR_IMODE                        0x00000300U            /*!< IMODE[1:0]: Instruction Mode     */
-#define  QUADSPI_CCR_IMODE_0                      0x00000100U            /*!< Bit 0 */
-#define  QUADSPI_CCR_IMODE_1                      0x00000200U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ADMODE                       0x00000C00U            /*!< ADMODE[1:0]: Address Mode         */
-#define  QUADSPI_CCR_ADMODE_0                     0x00000400U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ADMODE_1                     0x00000800U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ADSIZE                       0x00003000U            /*!< ADSIZE[1:0]: Address Size         */
-#define  QUADSPI_CCR_ADSIZE_0                     0x00001000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ADSIZE_1                     0x00002000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ABMODE                       0x0000C000U            /*!< ABMODE[1:0]: Alternate Bytes Mode */
-#define  QUADSPI_CCR_ABMODE_0                     0x00004000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ABMODE_1                     0x00008000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ABSIZE                       0x00030000U            /*!< ABSIZE[1:0]: Instruction Mode     */
-#define  QUADSPI_CCR_ABSIZE_0                     0x00010000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ABSIZE_1                     0x00020000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_DCYC                         0x007C0000U            /*!< DCYC[4:0]: Dummy Cycles           */
-#define  QUADSPI_CCR_DCYC_0                       0x00040000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_DCYC_1                       0x00080000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_DCYC_2                       0x00100000U            /*!< Bit 2 */
-#define  QUADSPI_CCR_DCYC_3                       0x00200000U            /*!< Bit 3 */
-#define  QUADSPI_CCR_DCYC_4                       0x00400000U            /*!< Bit 4 */
-#define  QUADSPI_CCR_DMODE                        0x03000000U            /*!< DMODE[1:0]: Data Mode                */
-#define  QUADSPI_CCR_DMODE_0                      0x01000000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_DMODE_1                      0x02000000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_FMODE                        0x0C000000U            /*!< FMODE[1:0]: Functional Mode           */
-#define  QUADSPI_CCR_FMODE_0                      0x04000000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_FMODE_1                      0x08000000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_SIOO                         0x10000000U            /*!< SIOO: Send Instruction Only Once Mode */
-#define  QUADSPI_CCR_DHHC                         0x40000000U            /*!< DHHC: Delay Half Hclk Cycle           */
-#define  QUADSPI_CCR_DDRM                         0x80000000U            /*!< DDRM: Double Data Rate Mode           */ 
-/******************  Bit definition for QUADSPI_AR register  *******************/
-#define  QUADSPI_AR_ADDRESS                       0xFFFFFFFFU            /*!< ADDRESS[31:0]: Address                */
-
-/******************  Bit definition for QUADSPI_ABR register  ******************/
-#define  QUADSPI_ABR_ALTERNATE                    0xFFFFFFFFU            /*!< ALTERNATE[31:0]: Alternate Bytes      */
-
-/******************  Bit definition for QUADSPI_DR register  *******************/
-#define  QUADSPI_DR_DATA                          0xFFFFFFFFU            /*!< DATA[31:0]: Data                      */
-
-/******************  Bit definition for QUADSPI_PSMKR register  ****************/
-#define  QUADSPI_PSMKR_MASK                       0xFFFFFFFFU            /*!< MASK[31:0]: Status Mask               */
-
-/******************  Bit definition for QUADSPI_PSMAR register  ****************/
-#define  QUADSPI_PSMAR_MATCH                      0xFFFFFFFFU            /*!< MATCH[31:0]: Status Match             */
-
-/******************  Bit definition for QUADSPI_PIR register  *****************/
-#define  QUADSPI_PIR_INTERVAL                     0x0000FFFFU            /*!< INTERVAL[15:0]: Polling Interval      */
-
-/******************  Bit definition for QUADSPI_LPTR register  *****************/
-#define  QUADSPI_LPTR_TIMEOUT                     0x0000FFFFU            /*!< TIMEOUT[15:0]: Timeout period         */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        0x00000001U
-#define  RCC_CR_HSIRDY                       0x00000002U
-
-#define  RCC_CR_HSITRIM                      0x000000F8U
-#define  RCC_CR_HSITRIM_0                    0x00000008U/*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    0x00000010U/*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    0x00000020U/*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    0x00000040U/*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    0x00000080U/*!<Bit 4 */
-
-#define  RCC_CR_HSICAL                       0x0000FF00U
-#define  RCC_CR_HSICAL_0                     0x00000100U/*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     0x00000200U/*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     0x00000400U/*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     0x00000800U/*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     0x00001000U/*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     0x00002000U/*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     0x00004000U/*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     0x00008000U/*!<Bit 7 */
-
-#define  RCC_CR_HSEON                        0x00010000U
-#define  RCC_CR_HSERDY                       0x00020000U
-#define  RCC_CR_HSEBYP                       0x00040000U
-#define  RCC_CR_CSSON                        0x00080000U
-#define  RCC_CR_PLLON                        0x01000000U
-#define  RCC_CR_PLLRDY                       0x02000000U
-#define  RCC_CR_PLLI2SON                     0x04000000U
-#define  RCC_CR_PLLI2SRDY                    0x08000000U
-#define  RCC_CR_PLLSAION                     0x10000000U
-#define  RCC_CR_PLLSAIRDY                    0x20000000U
-
-/********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    0x0000003FU
-#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
-#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
-#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
-#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
-#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
-#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
-
-#define  RCC_PLLCFGR_PLLN                     0x00007FC0U
-#define  RCC_PLLCFGR_PLLN_0                   0x00000040U
-#define  RCC_PLLCFGR_PLLN_1                   0x00000080U
-#define  RCC_PLLCFGR_PLLN_2                   0x00000100U
-#define  RCC_PLLCFGR_PLLN_3                   0x00000200U
-#define  RCC_PLLCFGR_PLLN_4                   0x00000400U
-#define  RCC_PLLCFGR_PLLN_5                   0x00000800U
-#define  RCC_PLLCFGR_PLLN_6                   0x00001000U
-#define  RCC_PLLCFGR_PLLN_7                   0x00002000U
-#define  RCC_PLLCFGR_PLLN_8                   0x00004000U
-
-#define  RCC_PLLCFGR_PLLP                    0x00030000U
-#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
-#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
-
-#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
-
-#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
-#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
-#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
-#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
-#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
-
-#define  RCC_PLLCFGR_PLLR                    0x70000000U
-#define  RCC_PLLCFGR_PLLR_0                  0x10000000U
-#define  RCC_PLLCFGR_PLLR_1                  0x20000000U
-#define  RCC_PLLCFGR_PLLR_2                  0x40000000U
-
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-/*!< SW configuration */
-#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
-
-#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
-
-#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
-
-#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
-
-/*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     0x001F0000U
-#define  RCC_CFGR_RTCPRE_0                   0x00010000U
-#define  RCC_CFGR_RTCPRE_1                   0x00020000U
-#define  RCC_CFGR_RTCPRE_2                   0x00040000U
-#define  RCC_CFGR_RTCPRE_3                   0x00080000U
-#define  RCC_CFGR_RTCPRE_4                   0x00100000U
-
-/*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       0x00600000U
-#define  RCC_CFGR_MCO1_0                     0x00200000U
-#define  RCC_CFGR_MCO1_1                     0x00400000U
-
-#define  RCC_CFGR_I2SSRC                     0x00800000U
-
-#define  RCC_CFGR_MCO1PRE                    0x07000000U
-#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
-#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
-#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
-
-#define  RCC_CFGR_MCO2PRE                    0x38000000U
-#define  RCC_CFGR_MCO2PRE_0                  0x08000000U
-#define  RCC_CFGR_MCO2PRE_1                  0x10000000U
-#define  RCC_CFGR_MCO2PRE_2                  0x20000000U
-
-#define  RCC_CFGR_MCO2                       0xC0000000U
-#define  RCC_CFGR_MCO2_0                     0x40000000U
-#define  RCC_CFGR_MCO2_1                     0x80000000U
-
-/********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     0x00000001U
-#define  RCC_CIR_LSERDYF                     0x00000002U
-#define  RCC_CIR_HSIRDYF                     0x00000004U
-#define  RCC_CIR_HSERDYF                     0x00000008U
-#define  RCC_CIR_PLLRDYF                     0x00000010U
-#define  RCC_CIR_PLLI2SRDYF                  0x00000020U
-#define  RCC_CIR_PLLSAIRDYF                  0x00000040U
-#define  RCC_CIR_CSSF                        0x00000080U
-#define  RCC_CIR_LSIRDYIE                    0x00000100U
-#define  RCC_CIR_LSERDYIE                    0x00000200U
-#define  RCC_CIR_HSIRDYIE                    0x00000400U
-#define  RCC_CIR_HSERDYIE                    0x00000800U
-#define  RCC_CIR_PLLRDYIE                    0x00001000U
-#define  RCC_CIR_PLLI2SRDYIE                 0x00002000U
-#define  RCC_CIR_PLLSAIRDYIE                 0x00004000U
-#define  RCC_CIR_LSIRDYC                     0x00010000U
-#define  RCC_CIR_LSERDYC                     0x00020000U
-#define  RCC_CIR_HSIRDYC                     0x00040000U
-#define  RCC_CIR_HSERDYC                     0x00080000U
-#define  RCC_CIR_PLLRDYC                     0x00100000U
-#define  RCC_CIR_PLLI2SRDYC                  0x00200000U
-#define  RCC_CIR_PLLSAIRDYC                  0x00400000U
-#define  RCC_CIR_CSSC                        0x00800000U
-
-/********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
-#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
-#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
-#define  RCC_AHB1RSTR_GPIODRST               0x00000008U
-#define  RCC_AHB1RSTR_GPIOERST               0x00000010U
-#define  RCC_AHB1RSTR_GPIOFRST               0x00000020U
-#define  RCC_AHB1RSTR_GPIOGRST               0x00000040U
-#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
-#define  RCC_AHB1RSTR_GPIOIRST               0x00000100U
-#define  RCC_AHB1RSTR_GPIOJRST               0x00000200U
-#define  RCC_AHB1RSTR_GPIOKRST               0x00000400U
-#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
-#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
-#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
-#define  RCC_AHB1RSTR_DMA2DRST               0x00800000U
-#define  RCC_AHB1RSTR_ETHMACRST              0x02000000U
-#define  RCC_AHB1RSTR_OTGHRST                0x20000000U
-
-/********************  Bit definition for RCC_AHB2RSTR register  **************/
-#define  RCC_AHB2RSTR_DCMIRST                0x00000001U
-#define  RCC_AHB2RSTR_CRYPRST                0x00000010U
-#define  RCC_AHB2RSTR_HASHRST                0x00000020U
- /* maintained for legacy purpose */
-#define  RCC_AHB2RSTR_HSAHRST                RCC_AHB2RSTR_HASHRST
-#define  RCC_AHB2RSTR_RNGRST                 0x00000040U
-#define  RCC_AHB2RSTR_OTGFSRST               0x00000080U
-
-/********************  Bit definition for RCC_AHB3RSTR register  **************/
-#define  RCC_AHB3RSTR_FMCRST                0x00000001U
-#define  RCC_AHB3RSTR_QSPIRST               0x00000002U
-
-/********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM2RST                0x00000001U
-#define  RCC_APB1RSTR_TIM3RST                0x00000002U
-#define  RCC_APB1RSTR_TIM4RST                0x00000004U
-#define  RCC_APB1RSTR_TIM5RST                0x00000008U
-#define  RCC_APB1RSTR_TIM6RST                0x00000010U
-#define  RCC_APB1RSTR_TIM7RST                0x00000020U
-#define  RCC_APB1RSTR_TIM12RST               0x00000040U
-#define  RCC_APB1RSTR_TIM13RST               0x00000080U
-#define  RCC_APB1RSTR_TIM14RST               0x00000100U
-#define  RCC_APB1RSTR_WWDGRST                0x00000800U
-#define  RCC_APB1RSTR_SPI2RST                0x00004000U
-#define  RCC_APB1RSTR_SPI3RST                0x00008000U
-#define  RCC_APB1RSTR_USART2RST              0x00020000U
-#define  RCC_APB1RSTR_USART3RST              0x00040000U
-#define  RCC_APB1RSTR_UART4RST               0x00080000U
-#define  RCC_APB1RSTR_UART5RST               0x00100000U
-#define  RCC_APB1RSTR_I2C1RST                0x00200000U
-#define  RCC_APB1RSTR_I2C2RST                0x00400000U
-#define  RCC_APB1RSTR_I2C3RST                0x00800000U
-#define  RCC_APB1RSTR_CAN1RST                0x02000000U
-#define  RCC_APB1RSTR_CAN2RST                0x04000000U
-#define  RCC_APB1RSTR_PWRRST                 0x10000000U
-#define  RCC_APB1RSTR_DACRST                 0x20000000U
-#define  RCC_APB1RSTR_UART7RST               0x40000000U
-#define  RCC_APB1RSTR_UART8RST               0x80000000U
-
-/********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                0x00000001U
-#define  RCC_APB2RSTR_TIM8RST                0x00000002U
-#define  RCC_APB2RSTR_USART1RST              0x00000010U
-#define  RCC_APB2RSTR_USART6RST              0x00000020U
-#define  RCC_APB2RSTR_ADCRST                 0x00000100U
-#define  RCC_APB2RSTR_SDIORST                0x00000800U
-#define  RCC_APB2RSTR_SPI1RST                0x00001000U
-#define  RCC_APB2RSTR_SPI4RST                0x00002000U
-#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
-#define  RCC_APB2RSTR_TIM9RST                0x00010000U
-#define  RCC_APB2RSTR_TIM10RST               0x00020000U
-#define  RCC_APB2RSTR_TIM11RST               0x00040000U
-#define  RCC_APB2RSTR_SPI5RST                0x00100000U
-#define  RCC_APB2RSTR_SPI6RST                0x00200000U
-#define  RCC_APB2RSTR_SAI1RST                0x00400000U
-#define  RCC_APB2RSTR_LTDCRST                0x04000000U
-#define  RCC_APB2RSTR_DSIRST                 0x08000000U
-
-/* Old SPI1RST bit definition, maintained for legacy purpose */
-#define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
-
-/********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
-#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
-#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
-#define  RCC_AHB1ENR_GPIODEN                 0x00000008U
-#define  RCC_AHB1ENR_GPIOEEN                 0x00000010U
-#define  RCC_AHB1ENR_GPIOFEN                 0x00000020U
-#define  RCC_AHB1ENR_GPIOGEN                 0x00000040U
-#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
-#define  RCC_AHB1ENR_GPIOIEN                 0x00000100U
-#define  RCC_AHB1ENR_GPIOJEN                 0x00000200U
-#define  RCC_AHB1ENR_GPIOKEN                 0x00000400U
-
-#define  RCC_AHB1ENR_CRCEN                   0x00001000U
-#define  RCC_AHB1ENR_BKPSRAMEN               0x00040000U
-#define  RCC_AHB1ENR_CCMDATARAMEN            0x00100000U
-#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
-#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
-#define  RCC_AHB1ENR_DMA2DEN                 0x00800000U
-
-#define  RCC_AHB1ENR_ETHMACEN                0x02000000U
-#define  RCC_AHB1ENR_ETHMACTXEN              0x04000000U
-#define  RCC_AHB1ENR_ETHMACRXEN              0x08000000U
-#define  RCC_AHB1ENR_ETHMACPTPEN             0x10000000U
-#define  RCC_AHB1ENR_OTGHSEN                 0x20000000U
-#define  RCC_AHB1ENR_OTGHSULPIEN             0x40000000U
-
-/********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define  RCC_AHB2ENR_DCMIEN                  0x00000001U
-#define  RCC_AHB2ENR_CRYPEN                  0x00000010U
-#define  RCC_AHB2ENR_HASHEN                  0x00000020U
-#define  RCC_AHB2ENR_RNGEN                   0x00000040U
-#define  RCC_AHB2ENR_OTGFSEN                 0x00000080U
-
-/********************  Bit definition for RCC_AHB3ENR register  ***************/
-#define  RCC_AHB3ENR_FMCEN                  0x00000001U
-#define  RCC_AHB3ENR_QSPIEN                 0x00000002U
-
-/********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM2EN                  0x00000001U
-#define  RCC_APB1ENR_TIM3EN                  0x00000002U
-#define  RCC_APB1ENR_TIM4EN                  0x00000004U
-#define  RCC_APB1ENR_TIM5EN                  0x00000008U
-#define  RCC_APB1ENR_TIM6EN                  0x00000010U
-#define  RCC_APB1ENR_TIM7EN                  0x00000020U
-#define  RCC_APB1ENR_TIM12EN                 0x00000040U
-#define  RCC_APB1ENR_TIM13EN                 0x00000080U
-#define  RCC_APB1ENR_TIM14EN                 0x00000100U
-#define  RCC_APB1ENR_WWDGEN                  0x00000800U
-#define  RCC_APB1ENR_SPI2EN                  0x00004000U
-#define  RCC_APB1ENR_SPI3EN                  0x00008000U
-#define  RCC_APB1ENR_USART2EN                0x00020000U
-#define  RCC_APB1ENR_USART3EN                0x00040000U
-#define  RCC_APB1ENR_UART4EN                 0x00080000U
-#define  RCC_APB1ENR_UART5EN                 0x00100000U
-#define  RCC_APB1ENR_I2C1EN                  0x00200000U
-#define  RCC_APB1ENR_I2C2EN                  0x00400000U
-#define  RCC_APB1ENR_I2C3EN                  0x00800000U
-#define  RCC_APB1ENR_CAN1EN                  0x02000000U
-#define  RCC_APB1ENR_CAN2EN                  0x04000000U
-#define  RCC_APB1ENR_PWREN                   0x10000000U
-#define  RCC_APB1ENR_DACEN                   0x20000000U
-#define  RCC_APB1ENR_UART7EN                 0x40000000U
-#define  RCC_APB1ENR_UART8EN                 0x80000000U
-
-/********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  0x00000001U
-#define  RCC_APB2ENR_TIM8EN                  0x00000002U
-#define  RCC_APB2ENR_USART1EN                0x00000010U
-#define  RCC_APB2ENR_USART6EN                0x00000020U
-#define  RCC_APB2ENR_ADC1EN                  0x00000100U
-#define  RCC_APB2ENR_ADC2EN                  0x00000200U
-#define  RCC_APB2ENR_ADC3EN                  0x00000400U
-#define  RCC_APB2ENR_SDIOEN                  0x00000800U
-#define  RCC_APB2ENR_SPI1EN                  0x00001000U
-#define  RCC_APB2ENR_SPI4EN                  0x00002000U
-#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
-#define  RCC_APB2ENR_TIM9EN                  0x00010000U
-#define  RCC_APB2ENR_TIM10EN                 0x00020000U
-#define  RCC_APB2ENR_TIM11EN                 0x00040000U
-#define  RCC_APB2ENR_SPI5EN                  0x00100000U
-#define  RCC_APB2ENR_SPI6EN                  0x00200000U
-#define  RCC_APB2ENR_SAI1EN                  0x00400000U
-#define  RCC_APB2ENR_LTDCEN                  0x04000000U
-#define  RCC_APB2ENR_DSIEN                   0x08000000U
-
-/********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
-#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
-#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
-#define  RCC_AHB1LPENR_GPIODLPEN             0x00000008U
-#define  RCC_AHB1LPENR_GPIOELPEN             0x00000010U
-#define  RCC_AHB1LPENR_GPIOFLPEN             0x00000020U
-#define  RCC_AHB1LPENR_GPIOGLPEN             0x00000040U
-#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
-#define  RCC_AHB1LPENR_GPIOILPEN             0x00000100U
-#define  RCC_AHB1LPENR_GPIOJLPEN             0x00000200U
-#define  RCC_AHB1LPENR_GPIOKLPEN             0x00000400U
-
-#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
-#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
-#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
-#define  RCC_AHB1LPENR_SRAM2LPEN             0x00020000U
-#define  RCC_AHB1LPENR_BKPSRAMLPEN           0x00040000U
-#define  RCC_AHB1LPENR_SRAM3LPEN             0x00080000U
-#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
-#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
-#define  RCC_AHB1LPENR_DMA2DLPEN             0x00800000U
-
-#define  RCC_AHB1LPENR_ETHMACLPEN            0x02000000U
-#define  RCC_AHB1LPENR_ETHMACTXLPEN          0x04000000U
-#define  RCC_AHB1LPENR_ETHMACRXLPEN          0x08000000U
-#define  RCC_AHB1LPENR_ETHMACPTPLPEN         0x10000000U
-#define  RCC_AHB1LPENR_OTGHSLPEN             0x20000000U
-#define  RCC_AHB1LPENR_OTGHSULPILPEN         0x40000000U
-
-/********************  Bit definition for RCC_AHB2LPENR register  *************/
-#define  RCC_AHB2LPENR_DCMILPEN              0x00000001U
-#define  RCC_AHB2LPENR_CRYPLPEN              0x00000010U
-#define  RCC_AHB2LPENR_HASHLPEN              0x00000020U
-#define  RCC_AHB2LPENR_RNGLPEN               0x00000040U
-#define  RCC_AHB2LPENR_OTGFSLPEN             0x00000080U
-
-/********************  Bit definition for RCC_AHB3LPENR register  *************/
-#define  RCC_AHB3LPENR_FMCLPEN              0x00000001U
-#define  RCC_AHB3LPENR_QSPILPEN             0x00000002U
-
-/********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM2LPEN              0x00000001U
-#define  RCC_APB1LPENR_TIM3LPEN              0x00000002U
-#define  RCC_APB1LPENR_TIM4LPEN              0x00000004U
-#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
-#define  RCC_APB1LPENR_TIM6LPEN              0x00000010U
-#define  RCC_APB1LPENR_TIM7LPEN              0x00000020U
-#define  RCC_APB1LPENR_TIM12LPEN             0x00000040U
-#define  RCC_APB1LPENR_TIM13LPEN             0x00000080U
-#define  RCC_APB1LPENR_TIM14LPEN             0x00000100U
-#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
-#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U
-#define  RCC_APB1LPENR_SPI3LPEN              0x00008000U
-#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
-#define  RCC_APB1LPENR_USART3LPEN            0x00040000U
-#define  RCC_APB1LPENR_UART4LPEN             0x00080000U
-#define  RCC_APB1LPENR_UART5LPEN             0x00100000U
-#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
-#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
-#define  RCC_APB1LPENR_I2C3LPEN              0x00800000U
-#define  RCC_APB1LPENR_CAN1LPEN              0x02000000U
-#define  RCC_APB1LPENR_CAN2LPEN              0x04000000U
-#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
-#define  RCC_APB1LPENR_DACLPEN               0x20000000U
-#define  RCC_APB1LPENR_UART7LPEN             0x40000000U
-#define  RCC_APB1LPENR_UART8LPEN             0x80000000U
-
-/********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
-#define  RCC_APB2LPENR_TIM8LPEN              0x00000002U
-#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
-#define  RCC_APB2LPENR_USART6LPEN            0x00000020U
-#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
-#define  RCC_APB2LPENR_ADC2LPEN              0x00000200U
-#define  RCC_APB2LPENR_ADC3LPEN              0x00000400U
-#define  RCC_APB2LPENR_SDIOLPEN              0x00000800U
-#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
-#define  RCC_APB2LPENR_SPI4LPEN              0x00002000U
-#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
-#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
-#define  RCC_APB2LPENR_TIM10LPEN             0x00020000U
-#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
-#define  RCC_APB2LPENR_SPI5LPEN              0x00100000U
-#define  RCC_APB2LPENR_SPI6LPEN              0x00200000U
-#define  RCC_APB2LPENR_SAI1LPEN              0x00400000U
-#define  RCC_APB2LPENR_LTDCLPEN              0x04000000U
-#define  RCC_APB2LPENR_DSILPEN               0x08000000U
-
-/********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      0x00000001U
-#define  RCC_BDCR_LSERDY                     0x00000002U
-#define  RCC_BDCR_LSEBYP                     0x00000004U
-#define  RCC_BDCR_LSEMOD                     0x00000008U
-
-#define  RCC_BDCR_RTCSEL                    0x00000300U
-#define  RCC_BDCR_RTCSEL_0                  0x00000100U
-#define  RCC_BDCR_RTCSEL_1                  0x00000200U
-
-#define  RCC_BDCR_RTCEN                      0x00008000U
-#define  RCC_BDCR_BDRST                      0x00010000U
-
-/********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       0x00000001U
-#define  RCC_CSR_LSIRDY                      0x00000002U
-#define  RCC_CSR_RMVF                        0x01000000U
-#define  RCC_CSR_BORRSTF                     0x02000000U
-#define  RCC_CSR_PADRSTF                     0x04000000U
-#define  RCC_CSR_PORRSTF                     0x08000000U
-#define  RCC_CSR_SFTRSTF                     0x10000000U
-#define  RCC_CSR_WDGRSTF                     0x20000000U
-#define  RCC_CSR_WWDGRSTF                    0x40000000U
-#define  RCC_CSR_LPWRRSTF                    0x80000000U
-
-/********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    0x00001FFFU
-#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
-#define  RCC_SSCGR_SPREADSEL                 0x40000000U
-#define  RCC_SSCGR_SSCGEN                    0x80000000U
-
-/********************  Bit definition for RCC_PLLI2SCFGR register  ************/
-#define  RCC_PLLI2SCFGR_PLLI2SN              0x00007FC0U
-#define  RCC_PLLI2SCFGR_PLLI2SN_0            0x00000040U
-#define  RCC_PLLI2SCFGR_PLLI2SN_1            0x00000080U
-#define  RCC_PLLI2SCFGR_PLLI2SN_2            0x00000100U
-#define  RCC_PLLI2SCFGR_PLLI2SN_3            0x00000200U
-#define  RCC_PLLI2SCFGR_PLLI2SN_4            0x00000400U
-#define  RCC_PLLI2SCFGR_PLLI2SN_5            0x00000800U
-#define  RCC_PLLI2SCFGR_PLLI2SN_6            0x00001000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_7            0x00002000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_8            0x00004000U
-
-#define  RCC_PLLI2SCFGR_PLLI2SQ              0x0F000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_0            0x01000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_1            0x02000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_2            0x04000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_3            0x08000000U
-
-#define  RCC_PLLI2SCFGR_PLLI2SR              0x70000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_0            0x10000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_1            0x20000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_2            0x40000000U
-
-
-/********************  Bit definition for RCC_PLLSAICFGR register  ************/
-#define  RCC_PLLSAICFGR_PLLSAIN              0x00007FC0U
-#define  RCC_PLLSAICFGR_PLLSAIN_0            0x00000040U
-#define  RCC_PLLSAICFGR_PLLSAIN_1            0x00000080U
-#define  RCC_PLLSAICFGR_PLLSAIN_2            0x00000100U
-#define  RCC_PLLSAICFGR_PLLSAIN_3            0x00000200U
-#define  RCC_PLLSAICFGR_PLLSAIN_4            0x00000400U
-#define  RCC_PLLSAICFGR_PLLSAIN_5            0x00000800U
-#define  RCC_PLLSAICFGR_PLLSAIN_6            0x00001000U
-#define  RCC_PLLSAICFGR_PLLSAIN_7            0x00002000U
-#define  RCC_PLLSAICFGR_PLLSAIN_8            0x00004000U
-
-#define  RCC_PLLSAICFGR_PLLSAIP              0x00030000U
-#define  RCC_PLLSAICFGR_PLLSAIP_0            0x00010000U
-#define  RCC_PLLSAICFGR_PLLSAIP_1            0x00020000U
-
-#define  RCC_PLLSAICFGR_PLLSAIQ              0x0F000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_0            0x01000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_1            0x02000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_2            0x04000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_3            0x08000000U
-
-#define  RCC_PLLSAICFGR_PLLSAIR              0x70000000U
-#define  RCC_PLLSAICFGR_PLLSAIR_0            0x10000000U
-#define  RCC_PLLSAICFGR_PLLSAIR_1            0x20000000U
-#define  RCC_PLLSAICFGR_PLLSAIR_2            0x40000000U
-
-/********************  Bit definition for RCC_DCKCFGR register  ***************/
-#define  RCC_DCKCFGR_PLLI2SDIVQ              0x0000001FU
-#define  RCC_DCKCFGR_PLLSAIDIVQ              0x00001F00U
-#define  RCC_DCKCFGR_PLLSAIDIVR              0x00030000U
-#define  RCC_DCKCFGR_SAI1ASRC                0x00300000U
-#define  RCC_DCKCFGR_SAI1ASRC_0              0x00100000U
-#define  RCC_DCKCFGR_SAI1ASRC_1              0x00200000U
-#define  RCC_DCKCFGR_SAI1BSRC                0x00C00000U
-#define  RCC_DCKCFGR_SAI1BSRC_0              0x00400000U
-#define  RCC_DCKCFGR_SAI1BSRC_1              0x00800000U
-#define  RCC_DCKCFGR_TIMPRE                  0x01000000U
-#define  RCC_DCKCFGR_CK48MSEL                0x08000000U
-#define  RCC_DCKCFGR_SDIOSEL                 0x10000000U
-#define  RCC_DCKCFGR_DSISEL                  0x20000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    RNG                                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN                         0x00000004U
-#define RNG_CR_IE                            0x00000008U
-
-/********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY                          0x00000001U
-#define RNG_SR_CECS                          0x00000002U
-#define RNG_SR_SECS                          0x00000004U
-#define RNG_SR_CEIS                          0x00000020U
-#define RNG_SR_SEIS                          0x00000040U
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            0x00400000U
-#define RTC_TR_HT                            0x00300000U
-#define RTC_TR_HT_0                          0x00100000U
-#define RTC_TR_HT_1                          0x00200000U
-#define RTC_TR_HU                            0x000F0000U
-#define RTC_TR_HU_0                          0x00010000U
-#define RTC_TR_HU_1                          0x00020000U
-#define RTC_TR_HU_2                          0x00040000U
-#define RTC_TR_HU_3                          0x00080000U
-#define RTC_TR_MNT                           0x00007000U
-#define RTC_TR_MNT_0                         0x00001000U
-#define RTC_TR_MNT_1                         0x00002000U
-#define RTC_TR_MNT_2                         0x00004000U
-#define RTC_TR_MNU                           0x00000F00U
-#define RTC_TR_MNU_0                         0x00000100U
-#define RTC_TR_MNU_1                         0x00000200U
-#define RTC_TR_MNU_2                         0x00000400U
-#define RTC_TR_MNU_3                         0x00000800U
-#define RTC_TR_ST                            0x00000070U
-#define RTC_TR_ST_0                          0x00000010U
-#define RTC_TR_ST_1                          0x00000020U
-#define RTC_TR_ST_2                          0x00000040U
-#define RTC_TR_SU                            0x0000000FU
-#define RTC_TR_SU_0                          0x00000001U
-#define RTC_TR_SU_1                          0x00000002U
-#define RTC_TR_SU_2                          0x00000004U
-#define RTC_TR_SU_3                          0x00000008U
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            0x00F00000U
-#define RTC_DR_YT_0                          0x00100000U
-#define RTC_DR_YT_1                          0x00200000U
-#define RTC_DR_YT_2                          0x00400000U
-#define RTC_DR_YT_3                          0x00800000U
-#define RTC_DR_YU                            0x000F0000U
-#define RTC_DR_YU_0                          0x00010000U
-#define RTC_DR_YU_1                          0x00020000U
-#define RTC_DR_YU_2                          0x00040000U
-#define RTC_DR_YU_3                          0x00080000U
-#define RTC_DR_WDU                           0x0000E000U
-#define RTC_DR_WDU_0                         0x00002000U
-#define RTC_DR_WDU_1                         0x00004000U
-#define RTC_DR_WDU_2                         0x00008000U
-#define RTC_DR_MT                            0x00001000U
-#define RTC_DR_MU                            0x00000F00U
-#define RTC_DR_MU_0                          0x00000100U
-#define RTC_DR_MU_1                          0x00000200U
-#define RTC_DR_MU_2                          0x00000400U
-#define RTC_DR_MU_3                          0x00000800U
-#define RTC_DR_DT                            0x00000030U
-#define RTC_DR_DT_0                          0x00000010U
-#define RTC_DR_DT_1                          0x00000020U
-#define RTC_DR_DU                            0x0000000FU
-#define RTC_DR_DU_0                          0x00000001U
-#define RTC_DR_DU_1                          0x00000002U
-#define RTC_DR_DU_2                          0x00000004U
-#define RTC_DR_DU_3                          0x00000008U
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           0x00800000U
-#define RTC_CR_OSEL                          0x00600000U
-#define RTC_CR_OSEL_0                        0x00200000U
-#define RTC_CR_OSEL_1                        0x00400000U
-#define RTC_CR_POL                           0x00100000U
-#define RTC_CR_COSEL                         0x00080000U
-#define RTC_CR_BCK                           0x00040000U
-#define RTC_CR_SUB1H                         0x00020000U
-#define RTC_CR_ADD1H                         0x00010000U
-#define RTC_CR_TSIE                          0x00008000U
-#define RTC_CR_WUTIE                         0x00004000U
-#define RTC_CR_ALRBIE                        0x00002000U
-#define RTC_CR_ALRAIE                        0x00001000U
-#define RTC_CR_TSE                           0x00000800U
-#define RTC_CR_WUTE                          0x00000400U
-#define RTC_CR_ALRBE                         0x00000200U
-#define RTC_CR_ALRAE                         0x00000100U
-#define RTC_CR_DCE                           0x00000080U
-#define RTC_CR_FMT                           0x00000040U
-#define RTC_CR_BYPSHAD                       0x00000020U
-#define RTC_CR_REFCKON                       0x00000010U
-#define RTC_CR_TSEDGE                        0x00000008U
-#define RTC_CR_WUCKSEL                       0x00000007U
-#define RTC_CR_WUCKSEL_0                     0x00000001U
-#define RTC_CR_WUCKSEL_1                     0x00000002U
-#define RTC_CR_WUCKSEL_2                     0x00000004U
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      0x00010000U
-#define RTC_ISR_TAMP1F                       0x00002000U
-#define RTC_ISR_TAMP2F                       0x00004000U
-#define RTC_ISR_TSOVF                        0x00001000U
-#define RTC_ISR_TSF                          0x00000800U
-#define RTC_ISR_WUTF                         0x00000400U
-#define RTC_ISR_ALRBF                        0x00000200U
-#define RTC_ISR_ALRAF                        0x00000100U
-#define RTC_ISR_INIT                         0x00000080U
-#define RTC_ISR_INITF                        0x00000040U
-#define RTC_ISR_RSF                          0x00000020U
-#define RTC_ISR_INITS                        0x00000010U
-#define RTC_ISR_SHPF                         0x00000008U
-#define RTC_ISR_WUTWF                        0x00000004U
-#define RTC_ISR_ALRBWF                       0x00000002U
-#define RTC_ISR_ALRAWF                       0x00000001U
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    0x007F0000U
-#define RTC_PRER_PREDIV_S                    0x00007FFFU
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS                       0x00000080U
-#define RTC_CALIBR_DC                        0x0000001FU
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      0x80000000U
-#define RTC_ALRMAR_WDSEL                     0x40000000U
-#define RTC_ALRMAR_DT                        0x30000000U
-#define RTC_ALRMAR_DT_0                      0x10000000U
-#define RTC_ALRMAR_DT_1                      0x20000000U
-#define RTC_ALRMAR_DU                        0x0F000000U
-#define RTC_ALRMAR_DU_0                      0x01000000U
-#define RTC_ALRMAR_DU_1                      0x02000000U
-#define RTC_ALRMAR_DU_2                      0x04000000U
-#define RTC_ALRMAR_DU_3                      0x08000000U
-#define RTC_ALRMAR_MSK3                      0x00800000U
-#define RTC_ALRMAR_PM                        0x00400000U
-#define RTC_ALRMAR_HT                        0x00300000U
-#define RTC_ALRMAR_HT_0                      0x00100000U
-#define RTC_ALRMAR_HT_1                      0x00200000U
-#define RTC_ALRMAR_HU                        0x000F0000U
-#define RTC_ALRMAR_HU_0                      0x00010000U
-#define RTC_ALRMAR_HU_1                      0x00020000U
-#define RTC_ALRMAR_HU_2                      0x00040000U
-#define RTC_ALRMAR_HU_3                      0x00080000U
-#define RTC_ALRMAR_MSK2                      0x00008000U
-#define RTC_ALRMAR_MNT                       0x00007000U
-#define RTC_ALRMAR_MNT_0                     0x00001000U
-#define RTC_ALRMAR_MNT_1                     0x00002000U
-#define RTC_ALRMAR_MNT_2                     0x00004000U
-#define RTC_ALRMAR_MNU                       0x00000F00U
-#define RTC_ALRMAR_MNU_0                     0x00000100U
-#define RTC_ALRMAR_MNU_1                     0x00000200U
-#define RTC_ALRMAR_MNU_2                     0x00000400U
-#define RTC_ALRMAR_MNU_3                     0x00000800U
-#define RTC_ALRMAR_MSK1                      0x00000080U
-#define RTC_ALRMAR_ST                        0x00000070U
-#define RTC_ALRMAR_ST_0                      0x00000010U
-#define RTC_ALRMAR_ST_1                      0x00000020U
-#define RTC_ALRMAR_ST_2                      0x00000040U
-#define RTC_ALRMAR_SU                        0x0000000FU
-#define RTC_ALRMAR_SU_0                      0x00000001U
-#define RTC_ALRMAR_SU_1                      0x00000002U
-#define RTC_ALRMAR_SU_2                      0x00000004U
-#define RTC_ALRMAR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      0x80000000U
-#define RTC_ALRMBR_WDSEL                     0x40000000U
-#define RTC_ALRMBR_DT                        0x30000000U
-#define RTC_ALRMBR_DT_0                      0x10000000U
-#define RTC_ALRMBR_DT_1                      0x20000000U
-#define RTC_ALRMBR_DU                        0x0F000000U
-#define RTC_ALRMBR_DU_0                      0x01000000U
-#define RTC_ALRMBR_DU_1                      0x02000000U
-#define RTC_ALRMBR_DU_2                      0x04000000U
-#define RTC_ALRMBR_DU_3                      0x08000000U
-#define RTC_ALRMBR_MSK3                      0x00800000U
-#define RTC_ALRMBR_PM                        0x00400000U
-#define RTC_ALRMBR_HT                        0x00300000U
-#define RTC_ALRMBR_HT_0                      0x00100000U
-#define RTC_ALRMBR_HT_1                      0x00200000U
-#define RTC_ALRMBR_HU                        0x000F0000U
-#define RTC_ALRMBR_HU_0                      0x00010000U
-#define RTC_ALRMBR_HU_1                      0x00020000U
-#define RTC_ALRMBR_HU_2                      0x00040000U
-#define RTC_ALRMBR_HU_3                      0x00080000U
-#define RTC_ALRMBR_MSK2                      0x00008000U
-#define RTC_ALRMBR_MNT                       0x00007000U
-#define RTC_ALRMBR_MNT_0                     0x00001000U
-#define RTC_ALRMBR_MNT_1                     0x00002000U
-#define RTC_ALRMBR_MNT_2                     0x00004000U
-#define RTC_ALRMBR_MNU                       0x00000F00U
-#define RTC_ALRMBR_MNU_0                     0x00000100U
-#define RTC_ALRMBR_MNU_1                     0x00000200U
-#define RTC_ALRMBR_MNU_2                     0x00000400U
-#define RTC_ALRMBR_MNU_3                     0x00000800U
-#define RTC_ALRMBR_MSK1                      0x00000080U
-#define RTC_ALRMBR_ST                        0x00000070U
-#define RTC_ALRMBR_ST_0                      0x00000010U
-#define RTC_ALRMBR_ST_1                      0x00000020U
-#define RTC_ALRMBR_ST_2                      0x00000040U
-#define RTC_ALRMBR_SU                        0x0000000FU
-#define RTC_ALRMBR_SU_0                      0x00000001U
-#define RTC_ALRMBR_SU_1                      0x00000002U
-#define RTC_ALRMBR_SU_2                      0x00000004U
-#define RTC_ALRMBR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          0x000000FFU
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           0x0000FFFFU
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     0x00007FFFU
-#define RTC_SHIFTR_ADD1S                     0x80000000U
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          0x00400000U
-#define RTC_TSTR_HT                          0x00300000U
-#define RTC_TSTR_HT_0                        0x00100000U
-#define RTC_TSTR_HT_1                        0x00200000U
-#define RTC_TSTR_HU                          0x000F0000U
-#define RTC_TSTR_HU_0                        0x00010000U
-#define RTC_TSTR_HU_1                        0x00020000U
-#define RTC_TSTR_HU_2                        0x00040000U
-#define RTC_TSTR_HU_3                        0x00080000U
-#define RTC_TSTR_MNT                         0x00007000U
-#define RTC_TSTR_MNT_0                       0x00001000U
-#define RTC_TSTR_MNT_1                       0x00002000U
-#define RTC_TSTR_MNT_2                       0x00004000U
-#define RTC_TSTR_MNU                         0x00000F00U
-#define RTC_TSTR_MNU_0                       0x00000100U
-#define RTC_TSTR_MNU_1                       0x00000200U
-#define RTC_TSTR_MNU_2                       0x00000400U
-#define RTC_TSTR_MNU_3                       0x00000800U
-#define RTC_TSTR_ST                          0x00000070U
-#define RTC_TSTR_ST_0                        0x00000010U
-#define RTC_TSTR_ST_1                        0x00000020U
-#define RTC_TSTR_ST_2                        0x00000040U
-#define RTC_TSTR_SU                          0x0000000FU
-#define RTC_TSTR_SU_0                        0x00000001U
-#define RTC_TSTR_SU_1                        0x00000002U
-#define RTC_TSTR_SU_2                        0x00000004U
-#define RTC_TSTR_SU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         0x0000E000U
-#define RTC_TSDR_WDU_0                       0x00002000U
-#define RTC_TSDR_WDU_1                       0x00004000U
-#define RTC_TSDR_WDU_2                       0x00008000U
-#define RTC_TSDR_MT                          0x00001000U
-#define RTC_TSDR_MU                          0x00000F00U
-#define RTC_TSDR_MU_0                        0x00000100U
-#define RTC_TSDR_MU_1                        0x00000200U
-#define RTC_TSDR_MU_2                        0x00000400U
-#define RTC_TSDR_MU_3                        0x00000800U
-#define RTC_TSDR_DT                          0x00000030U
-#define RTC_TSDR_DT_0                        0x00000010U
-#define RTC_TSDR_DT_1                        0x00000020U
-#define RTC_TSDR_DU                          0x0000000FU
-#define RTC_TSDR_DU_0                        0x00000001U
-#define RTC_TSDR_DU_1                        0x00000002U
-#define RTC_TSDR_DU_2                        0x00000004U
-#define RTC_TSDR_DU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        0x00008000U
-#define RTC_CALR_CALW8                       0x00004000U
-#define RTC_CALR_CALW16                      0x00002000U
-#define RTC_CALR_CALM                        0x000001FFU
-#define RTC_CALR_CALM_0                      0x00000001U
-#define RTC_CALR_CALM_1                      0x00000002U
-#define RTC_CALR_CALM_2                      0x00000004U
-#define RTC_CALR_CALM_3                      0x00000008U
-#define RTC_CALR_CALM_4                      0x00000010U
-#define RTC_CALR_CALM_5                      0x00000020U
-#define RTC_CALR_CALM_6                      0x00000040U
-#define RTC_CALR_CALM_7                      0x00000080U
-#define RTC_CALR_CALM_8                      0x00000100U
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               0x00040000U
-#define RTC_TAFCR_TSINSEL                    0x00020000U
-#define RTC_TAFCR_TAMPINSEL                  0x00010000U
-#define RTC_TAFCR_TAMPPUDIS                  0x00008000U
-#define RTC_TAFCR_TAMPPRCH                   0x00006000U
-#define RTC_TAFCR_TAMPPRCH_0                 0x00002000U
-#define RTC_TAFCR_TAMPPRCH_1                 0x00004000U
-#define RTC_TAFCR_TAMPFLT                    0x00001800U
-#define RTC_TAFCR_TAMPFLT_0                  0x00000800U
-#define RTC_TAFCR_TAMPFLT_1                  0x00001000U
-#define RTC_TAFCR_TAMPFREQ                   0x00000700U
-#define RTC_TAFCR_TAMPFREQ_0                 0x00000100U
-#define RTC_TAFCR_TAMPFREQ_1                 0x00000200U
-#define RTC_TAFCR_TAMPFREQ_2                 0x00000400U
-#define RTC_TAFCR_TAMPTS                     0x00000080U
-#define RTC_TAFCR_TAMP2TRG                   0x00000010U
-#define RTC_TAFCR_TAMP2E                     0x00000008U
-#define RTC_TAFCR_TAMPIE                     0x00000004U
-#define RTC_TAFCR_TAMP1TRG                   0x00000002U
-#define RTC_TAFCR_TAMP1E                     0x00000001U
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  0x0F000000U
-#define RTC_ALRMASSR_MASKSS_0                0x01000000U
-#define RTC_ALRMASSR_MASKSS_1                0x02000000U
-#define RTC_ALRMASSR_MASKSS_2                0x04000000U
-#define RTC_ALRMASSR_MASKSS_3                0x08000000U
-#define RTC_ALRMASSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
-#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
-#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
-#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
-#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
-#define RTC_ALRMBSSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           0xFFFFFFFFU
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Serial Audio Interface                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for SAI_GCR register  *******************/
-#define  SAI_GCR_SYNCIN                  0x00000003U        /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
-#define  SAI_GCR_SYNCIN_0                0x00000001U        /*!<Bit 0 */
-#define  SAI_GCR_SYNCIN_1                0x00000002U        /*!<Bit 1 */
-
-#define  SAI_GCR_SYNCOUT                 0x00000030U        /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
-#define  SAI_GCR_SYNCOUT_0               0x00000010U        /*!<Bit 0 */
-#define  SAI_GCR_SYNCOUT_1               0x00000020U        /*!<Bit 1 */
-
-/*******************  Bit definition for SAI_xCR1 register  *******************/
-#define  SAI_xCR1_MODE                    0x00000003U        /*!<MODE[1:0] bits (Audio Block Mode)           */
-#define  SAI_xCR1_MODE_0                  0x00000001U        /*!<Bit 0 */
-#define  SAI_xCR1_MODE_1                  0x00000002U        /*!<Bit 1 */
-
-#define  SAI_xCR1_PRTCFG                  0x0000000CU        /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
-#define  SAI_xCR1_PRTCFG_0                0x00000004U        /*!<Bit 0 */
-#define  SAI_xCR1_PRTCFG_1                0x00000008U        /*!<Bit 1 */
-
-#define  SAI_xCR1_DS                      0x000000E0U        /*!<DS[1:0] bits (Data Size) */
-#define  SAI_xCR1_DS_0                    0x00000020U        /*!<Bit 0 */
-#define  SAI_xCR1_DS_1                    0x00000040U        /*!<Bit 1 */
-#define  SAI_xCR1_DS_2                    0x00000080U        /*!<Bit 2 */
-
-#define  SAI_xCR1_LSBFIRST                0x00000100U        /*!<LSB First Configuration  */
-#define  SAI_xCR1_CKSTR                   0x00000200U        /*!<ClocK STRobing edge      */
-
-#define  SAI_xCR1_SYNCEN                  0x00000C00U        /*!<SYNCEN[1:0](SYNChronization ENable) */
-#define  SAI_xCR1_SYNCEN_0                0x00000400U        /*!<Bit 0 */
-#define  SAI_xCR1_SYNCEN_1                0x00000800U        /*!<Bit 1 */
-
-#define  SAI_xCR1_MONO                    0x00001000U        /*!<Mono mode                  */
-#define  SAI_xCR1_OUTDRIV                 0x00002000U        /*!<Output Drive               */
-#define  SAI_xCR1_SAIEN                   0x00010000U        /*!<Audio Block enable         */
-#define  SAI_xCR1_DMAEN                   0x00020000U        /*!<DMA enable                 */
-#define  SAI_xCR1_NODIV                   0x00080000U        /*!<No Divider Configuration   */
-
-#define  SAI_xCR1_MCKDIV                  0x00F00000U        /*!<MCKDIV[3:0] (Master ClocK Divider)  */
-#define  SAI_xCR1_MCKDIV_0                0x00100000U        /*!<Bit 0  */
-#define  SAI_xCR1_MCKDIV_1                0x00200000U        /*!<Bit 1  */
-#define  SAI_xCR1_MCKDIV_2                0x00400000U        /*!<Bit 2  */
-#define  SAI_xCR1_MCKDIV_3                0x00800000U        /*!<Bit 3  */
-
-/*******************  Bit definition for SAI_xCR2 register  *******************/
-#define  SAI_xCR2_FTH                     0x00000007U        /*!<FTH[2:0](Fifo THreshold)  */
-#define  SAI_xCR2_FTH_0                   0x00000001U        /*!<Bit 0 */
-#define  SAI_xCR2_FTH_1                   0x00000002U        /*!<Bit 1 */
-#define  SAI_xCR2_FTH_2                   0x00000004U        /*!<Bit 2 */
-
-#define  SAI_xCR2_FFLUSH                  0x00000008U        /*!<Fifo FLUSH                       */
-#define  SAI_xCR2_TRIS                    0x00000010U        /*!<TRIState Management on data line */
-#define  SAI_xCR2_MUTE                    0x00000020U        /*!<Mute mode                        */
-#define  SAI_xCR2_MUTEVAL                 0x00000040U        /*!<Muate value                      */
-
-#define  SAI_xCR2_MUTECNT                  0x00001F80U       /*!<MUTECNT[5:0] (MUTE counter) */
-#define  SAI_xCR2_MUTECNT_0               0x00000080U        /*!<Bit 0 */
-#define  SAI_xCR2_MUTECNT_1               0x00000100U        /*!<Bit 1 */
-#define  SAI_xCR2_MUTECNT_2               0x00000200U        /*!<Bit 2 */
-#define  SAI_xCR2_MUTECNT_3               0x00000400U        /*!<Bit 3 */
-#define  SAI_xCR2_MUTECNT_4               0x00000800U        /*!<Bit 4 */
-#define  SAI_xCR2_MUTECNT_5               0x00001000U        /*!<Bit 5 */
-
-#define  SAI_xCR2_CPL                     0x00002000U        /*!< Complement Bit             */
-
-#define  SAI_xCR2_COMP                    0x0000C000U        /*!<COMP[1:0] (Companding mode) */
-#define  SAI_xCR2_COMP_0                  0x00004000U        /*!<Bit 0 */
-#define  SAI_xCR2_COMP_1                  0x00008000U        /*!<Bit 1 */
-
-/******************  Bit definition for SAI_xFRCR register  *******************/
-#define  SAI_xFRCR_FRL                    0x000000FFU        /*!<FRL[1:0](Frame length)  */
-#define  SAI_xFRCR_FRL_0                  0x00000001U        /*!<Bit 0 */
-#define  SAI_xFRCR_FRL_1                  0x00000002U        /*!<Bit 1 */
-#define  SAI_xFRCR_FRL_2                  0x00000004U        /*!<Bit 2 */
-#define  SAI_xFRCR_FRL_3                  0x00000008U        /*!<Bit 3 */
-#define  SAI_xFRCR_FRL_4                  0x00000010U        /*!<Bit 4 */
-#define  SAI_xFRCR_FRL_5                  0x00000020U        /*!<Bit 5 */
-#define  SAI_xFRCR_FRL_6                  0x00000040U        /*!<Bit 6 */
-#define  SAI_xFRCR_FRL_7                  0x00000080U        /*!<Bit 7 */
-
-#define  SAI_xFRCR_FSALL                  0x00007F00U        /*!<FRL[1:0] (Frame synchronization active level length)  */
-#define  SAI_xFRCR_FSALL_0                0x00000100U        /*!<Bit 0 */
-#define  SAI_xFRCR_FSALL_1                0x00000200U        /*!<Bit 1 */
-#define  SAI_xFRCR_FSALL_2                0x00000400U        /*!<Bit 2 */
-#define  SAI_xFRCR_FSALL_3                0x00000800U        /*!<Bit 3 */
-#define  SAI_xFRCR_FSALL_4                0x00001000U        /*!<Bit 4 */
-#define  SAI_xFRCR_FSALL_5                0x00002000U        /*!<Bit 5 */
-#define  SAI_xFRCR_FSALL_6                0x00004000U        /*!<Bit 6 */
-
-#define  SAI_xFRCR_FSDEF                  0x00010000U        /*!< Frame Synchronization Definition */
-#define  SAI_xFRCR_FSPOL                  0x00020000U        /*!<Frame Synchronization POLarity    */
-#define  SAI_xFRCR_FSOFF                  0x00040000U        /*!<Frame Synchronization OFFset      */
-/* Legacy defines */
-#define  SAI_xFRCR_FSPO                   SAI_xFRCR_FSPOL
-
-/******************  Bit definition for SAI_xSLOTR register  *******************/
-#define  SAI_xSLOTR_FBOFF                 0x0000001FU        /*!<FRL[4:0](First Bit Offset)  */
-#define  SAI_xSLOTR_FBOFF_0               0x00000001U        /*!<Bit 0 */
-#define  SAI_xSLOTR_FBOFF_1               0x00000002U        /*!<Bit 1 */
-#define  SAI_xSLOTR_FBOFF_2               0x00000004U        /*!<Bit 2 */
-#define  SAI_xSLOTR_FBOFF_3               0x00000008U        /*!<Bit 3 */
-#define  SAI_xSLOTR_FBOFF_4               0x00000010U        /*!<Bit 4 */
-
-#define  SAI_xSLOTR_SLOTSZ                0x000000C0U        /*!<SLOTSZ[1:0] (Slot size)  */
-#define  SAI_xSLOTR_SLOTSZ_0              0x00000040U        /*!<Bit 0 */
-#define  SAI_xSLOTR_SLOTSZ_1              0x00000080U        /*!<Bit 1 */
-
-#define  SAI_xSLOTR_NBSLOT                0x00000F00U        /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
-#define  SAI_xSLOTR_NBSLOT_0              0x00000100U        /*!<Bit 0 */
-#define  SAI_xSLOTR_NBSLOT_1              0x00000200U        /*!<Bit 1 */
-#define  SAI_xSLOTR_NBSLOT_2              0x00000400U        /*!<Bit 2 */
-#define  SAI_xSLOTR_NBSLOT_3              0x00000800U        /*!<Bit 3 */
-
-#define  SAI_xSLOTR_SLOTEN                0xFFFF0000U        /*!<SLOTEN[15:0] (Slot Enable)  */
-
-/*******************  Bit definition for SAI_xIMR register  *******************/
-#define  SAI_xIMR_OVRUDRIE                0x00000001U        /*!<Overrun underrun interrupt enable                              */
-#define  SAI_xIMR_MUTEDETIE               0x00000002U        /*!<Mute detection interrupt enable                                */
-#define  SAI_xIMR_WCKCFGIE                0x00000004U        /*!<Wrong Clock Configuration interrupt enable                     */
-#define  SAI_xIMR_FREQIE                  0x00000008U        /*!<FIFO request interrupt enable                                  */
-#define  SAI_xIMR_CNRDYIE                 0x00000010U        /*!<Codec not ready interrupt enable                               */
-#define  SAI_xIMR_AFSDETIE                0x00000020U        /*!<Anticipated frame synchronization detection interrupt enable   */
-#define  SAI_xIMR_LFSDETIE                0x00000040U        /*!<Late frame synchronization detection interrupt enable          */
-
-/********************  Bit definition for SAI_xSR register  *******************/
-#define  SAI_xSR_OVRUDR                   0x00000001U         /*!<Overrun underrun                               */
-#define  SAI_xSR_MUTEDET                  0x00000002U         /*!<Mute detection                                 */
-#define  SAI_xSR_WCKCFG                   0x00000004U         /*!<Wrong Clock Configuration                      */
-#define  SAI_xSR_FREQ                     0x00000008U         /*!<FIFO request                                   */
-#define  SAI_xSR_CNRDY                    0x00000010U         /*!<Codec not ready                                */
-#define  SAI_xSR_AFSDET                   0x00000020U         /*!<Anticipated frame synchronization detection    */
-#define  SAI_xSR_LFSDET                   0x00000040U         /*!<Late frame synchronization detection           */
-
-#define  SAI_xSR_FLVL                     0x00070000U         /*!<FLVL[2:0] (FIFO Level Threshold)               */
-#define  SAI_xSR_FLVL_0                   0x00010000U         /*!<Bit 0 */
-#define  SAI_xSR_FLVL_1                   0x00020000U         /*!<Bit 1 */
-#define  SAI_xSR_FLVL_2                   0x00040000U         /*!<Bit 2 */
-
-/******************  Bit definition for SAI_xCLRFR register  ******************/
-#define  SAI_xCLRFR_COVRUDR               0x00000001U        /*!<Clear Overrun underrun                               */
-#define  SAI_xCLRFR_CMUTEDET              0x00000002U        /*!<Clear Mute detection                                 */
-#define  SAI_xCLRFR_CWCKCFG               0x00000004U        /*!<Clear Wrong Clock Configuration                      */
-#define  SAI_xCLRFR_CFREQ                 0x00000008U        /*!<Clear FIFO request                                   */
-#define  SAI_xCLRFR_CCNRDY                0x00000010U        /*!<Clear Codec not ready                                */
-#define  SAI_xCLRFR_CAFSDET               0x00000020U        /*!<Clear Anticipated frame synchronization detection    */
-#define  SAI_xCLRFR_CLFSDET               0x00000040U        /*!<Clear Late frame synchronization detection           */
-
-/******************  Bit definition for SAI_xDR register  ******************/
-#define  SAI_xDR_DATA                     0xFFFFFFFFU        
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          SD host Interface                                 */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SDIO_POWER register  ******************/
-#define  SDIO_POWER_PWRCTRL                  0x03U               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDIO_POWER_PWRCTRL_0                0x01U               /*!<Bit 0 */
-#define  SDIO_POWER_PWRCTRL_1                0x02U               /*!<Bit 1 */
-
-/******************  Bit definition for SDIO_CLKCR register  ******************/
-#define  SDIO_CLKCR_CLKDIV                   0x00FFU            /*!<Clock divide factor             */
-#define  SDIO_CLKCR_CLKEN                    0x0100U            /*!<Clock enable bit                */
-#define  SDIO_CLKCR_PWRSAV                   0x0200U            /*!<Power saving configuration bit  */
-#define  SDIO_CLKCR_BYPASS                   0x0400U            /*!<Clock divider bypass enable bit */
-
-#define  SDIO_CLKCR_WIDBUS                   0x1800U            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDIO_CLKCR_WIDBUS_0                 0x0800U            /*!<Bit 0 */
-#define  SDIO_CLKCR_WIDBUS_1                 0x1000U            /*!<Bit 1 */
-
-#define  SDIO_CLKCR_NEGEDGE                  0x2000U            /*!<SDIO_CK dephasing selection bit */
-#define  SDIO_CLKCR_HWFC_EN                  0x4000U            /*!<HW Flow Control enable          */
-
-/*******************  Bit definition for SDIO_ARG register  *******************/
-#define  SDIO_ARG_CMDARG                     0xFFFFFFFFU            /*!<Command argument */
-
-/*******************  Bit definition for SDIO_CMD register  *******************/
-#define  SDIO_CMD_CMDINDEX                   0x003FU            /*!<Command Index                               */
-
-#define  SDIO_CMD_WAITRESP                   0x00C0U            /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDIO_CMD_WAITRESP_0                 0x0040U            /*!< Bit 0 */
-#define  SDIO_CMD_WAITRESP_1                 0x0080U            /*!< Bit 1 */
-
-#define  SDIO_CMD_WAITINT                    0x0100U            /*!<CPSM Waits for Interrupt Request                               */
-#define  SDIO_CMD_WAITPEND                   0x0200U            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDIO_CMD_CPSMEN                     0x0400U            /*!<Command path state machine (CPSM) Enable bit                   */
-#define  SDIO_CMD_SDIOSUSPEND                0x0800U            /*!<SD I/O suspend command                                         */
-
-/*****************  Bit definition for SDIO_RESPCMD register  *****************/
-#define  SDIO_RESPCMD_RESPCMD                0x3FU               /*!<Response command index */
-
-/******************  Bit definition for SDIO_RESP0 register  ******************/
-#define  SDIO_RESP0_CARDSTATUS0              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP1 register  ******************/
-#define  SDIO_RESP1_CARDSTATUS1              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP2 register  ******************/
-#define  SDIO_RESP2_CARDSTATUS2              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP3 register  ******************/
-#define  SDIO_RESP3_CARDSTATUS3              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP4 register  ******************/
-#define  SDIO_RESP4_CARDSTATUS4              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDIO_DTIMER register  *****************/
-#define  SDIO_DTIMER_DATATIME                0xFFFFFFFFU        /*!<Data timeout period. */
-
-/******************  Bit definition for SDIO_DLEN register  *******************/
-#define  SDIO_DLEN_DATALENGTH                0x01FFFFFFU        /*!<Data length value    */
-
-/******************  Bit definition for SDIO_DCTRL register  ******************/
-#define  SDIO_DCTRL_DTEN                     0x0001U            /*!<Data transfer enabled bit         */
-#define  SDIO_DCTRL_DTDIR                    0x0002U            /*!<Data transfer direction selection */
-#define  SDIO_DCTRL_DTMODE                   0x0004U            /*!<Data transfer mode selection      */
-#define  SDIO_DCTRL_DMAEN                    0x0008U            /*!<DMA enabled bit                   */
-
-#define  SDIO_DCTRL_DBLOCKSIZE               0x00F0U            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDIO_DCTRL_DBLOCKSIZE_0             0x0010U            /*!<Bit 0 */
-#define  SDIO_DCTRL_DBLOCKSIZE_1             0x0020U            /*!<Bit 1 */
-#define  SDIO_DCTRL_DBLOCKSIZE_2             0x0040U            /*!<Bit 2 */
-#define  SDIO_DCTRL_DBLOCKSIZE_3             0x0080U            /*!<Bit 3 */
-
-#define  SDIO_DCTRL_RWSTART                  0x0100U            /*!<Read wait start         */
-#define  SDIO_DCTRL_RWSTOP                   0x0200U            /*!<Read wait stop          */
-#define  SDIO_DCTRL_RWMOD                    0x0400U            /*!<Read wait mode          */
-#define  SDIO_DCTRL_SDIOEN                   0x0800U            /*!<SD I/O enable functions */
-
-/******************  Bit definition for SDIO_DCOUNT register  *****************/
-#define  SDIO_DCOUNT_DATACOUNT               0x01FFFFFFU        /*!<Data count value */
-
-/******************  Bit definition for SDIO_STA register  ********************/
-#define  SDIO_STA_CCRCFAIL                   0x00000001U        /*!<Command response received (CRC check failed)  */
-#define  SDIO_STA_DCRCFAIL                   0x00000002U        /*!<Data block sent/received (CRC check failed)   */
-#define  SDIO_STA_CTIMEOUT                   0x00000004U        /*!<Command response timeout                      */
-#define  SDIO_STA_DTIMEOUT                   0x00000008U        /*!<Data timeout                                  */
-#define  SDIO_STA_TXUNDERR                   0x00000010U        /*!<Transmit FIFO underrun error                  */
-#define  SDIO_STA_RXOVERR                    0x00000020U        /*!<Received FIFO overrun error                   */
-#define  SDIO_STA_CMDREND                    0x00000040U        /*!<Command response received (CRC check passed)  */
-#define  SDIO_STA_CMDSENT                    0x00000080U        /*!<Command sent (no response required)           */
-#define  SDIO_STA_DATAEND                    0x00000100U        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
-#define  SDIO_STA_DBCKEND                    0x00000400U        /*!<Data block sent/received (CRC check passed)   */
-#define  SDIO_STA_CMDACT                     0x00000800U        /*!<Command transfer in progress                  */
-#define  SDIO_STA_TXACT                      0x00001000U        /*!<Data transmit in progress                     */
-#define  SDIO_STA_RXACT                      0x00002000U        /*!<Data receive in progress                      */
-#define  SDIO_STA_TXFIFOHE                   0x00004000U        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDIO_STA_RXFIFOHF                   0x00008000U        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDIO_STA_TXFIFOF                    0x00010000U        /*!<Transmit FIFO full                            */
-#define  SDIO_STA_RXFIFOF                    0x00020000U        /*!<Receive FIFO full                             */
-#define  SDIO_STA_TXFIFOE                    0x00040000U        /*!<Transmit FIFO empty                           */
-#define  SDIO_STA_RXFIFOE                    0x00080000U        /*!<Receive FIFO empty                            */
-#define  SDIO_STA_TXDAVL                     0x00100000U        /*!<Data available in transmit FIFO               */
-#define  SDIO_STA_RXDAVL                     0x00200000U        /*!<Data available in receive FIFO                */
-#define  SDIO_STA_SDIOIT                     0x00400000U        /*!<SDIO interrupt received                       */
-
-/*******************  Bit definition for SDIO_ICR register  *******************/
-#define  SDIO_ICR_CCRCFAILC                  0x00000001U        /*!<CCRCFAIL flag clear bit */
-#define  SDIO_ICR_DCRCFAILC                  0x00000002U        /*!<DCRCFAIL flag clear bit */
-#define  SDIO_ICR_CTIMEOUTC                  0x00000004U        /*!<CTIMEOUT flag clear bit */
-#define  SDIO_ICR_DTIMEOUTC                  0x00000008U        /*!<DTIMEOUT flag clear bit */
-#define  SDIO_ICR_TXUNDERRC                  0x00000010U        /*!<TXUNDERR flag clear bit */
-#define  SDIO_ICR_RXOVERRC                   0x00000020U        /*!<RXOVERR flag clear bit  */
-#define  SDIO_ICR_CMDRENDC                   0x00000040U        /*!<CMDREND flag clear bit  */
-#define  SDIO_ICR_CMDSENTC                   0x00000080U        /*!<CMDSENT flag clear bit  */
-#define  SDIO_ICR_DATAENDC                   0x00000100U        /*!<DATAEND flag clear bit  */
-#define  SDIO_ICR_DBCKENDC                   0x00000400U        /*!<DBCKEND flag clear bit  */
-#define  SDIO_ICR_SDIOITC                    0x00400000U        /*!<SDIOIT flag clear bit   */
-
-/******************  Bit definition for SDIO_MASK register  *******************/
-#define  SDIO_MASK_CCRCFAILIE                0x00000001U        /*!<Command CRC Fail Interrupt Enable          */
-#define  SDIO_MASK_DCRCFAILIE                0x00000002U        /*!<Data CRC Fail Interrupt Enable             */
-#define  SDIO_MASK_CTIMEOUTIE                0x00000004U        /*!<Command TimeOut Interrupt Enable           */
-#define  SDIO_MASK_DTIMEOUTIE                0x00000008U        /*!<Data TimeOut Interrupt Enable              */
-#define  SDIO_MASK_TXUNDERRIE                0x00000010U        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
-#define  SDIO_MASK_RXOVERRIE                 0x00000020U        /*!<Rx FIFO OverRun Error Interrupt Enable     */
-#define  SDIO_MASK_CMDRENDIE                 0x00000040U        /*!<Command Response Received Interrupt Enable */
-#define  SDIO_MASK_CMDSENTIE                 0x00000080U        /*!<Command Sent Interrupt Enable              */
-#define  SDIO_MASK_DATAENDIE                 0x00000100U        /*!<Data End Interrupt Enable                  */
-#define  SDIO_MASK_DBCKENDIE                 0x00000400U        /*!<Data Block End Interrupt Enable            */
-#define  SDIO_MASK_CMDACTIE                  0x00000800U        /*!<CCommand Acting Interrupt Enable           */
-#define  SDIO_MASK_TXACTIE                   0x00001000U        /*!<Data Transmit Acting Interrupt Enable      */
-#define  SDIO_MASK_RXACTIE                   0x00002000U        /*!<Data receive acting interrupt enabled      */
-#define  SDIO_MASK_TXFIFOHEIE                0x00004000U        /*!<Tx FIFO Half Empty interrupt Enable        */
-#define  SDIO_MASK_RXFIFOHFIE                0x00008000U        /*!<Rx FIFO Half Full interrupt Enable         */
-#define  SDIO_MASK_TXFIFOFIE                 0x00010000U        /*!<Tx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_RXFIFOFIE                 0x00020000U        /*!<Rx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_TXFIFOEIE                 0x00040000U        /*!<Tx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_RXFIFOEIE                 0x00080000U        /*!<Rx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_TXDAVLIE                  0x00100000U        /*!<Data available in Tx FIFO interrupt Enable */
-#define  SDIO_MASK_RXDAVLIE                  0x00200000U        /*!<Data available in Rx FIFO interrupt Enable */
-#define  SDIO_MASK_SDIOITIE                  0x00400000U        /*!<SDIO Mode Interrupt Received interrupt Enable */
-
-/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
-#define  SDIO_FIFOCNT_FIFOCOUNT              0x00FFFFFFU        /*!<Remaining number of words to be written to or read from the FIFO */
-
-/******************  Bit definition for SDIO_FIFO register  *******************/
-#define  SDIO_FIFO_FIFODATA                  0xFFFFFFFFU        /*!<Receive and transmit FIFO data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        0x00000001U            /*!<Clock Phase      */
-#define  SPI_CR1_CPOL                        0x00000002U            /*!<Clock Polarity   */
-#define  SPI_CR1_MSTR                        0x00000004U            /*!<Master Selection */
-
-#define  SPI_CR1_BR                          0x00000038U            /*!<BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        0x00000008U            /*!<Bit 0 */
-#define  SPI_CR1_BR_1                        0x00000010U            /*!<Bit 1 */
-#define  SPI_CR1_BR_2                        0x00000020U            /*!<Bit 2 */
-
-#define  SPI_CR1_SPE                         0x00000040U            /*!<SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    0x00000080U            /*!<Frame Format                        */
-#define  SPI_CR1_SSI                         0x00000100U            /*!<Internal slave select               */
-#define  SPI_CR1_SSM                         0x00000200U            /*!<Software slave management           */
-#define  SPI_CR1_RXONLY                      0x00000400U            /*!<Receive only                        */
-#define  SPI_CR1_DFF                         0x00000800U            /*!<Data Frame Format                   */
-#define  SPI_CR1_CRCNEXT                     0x00001000U            /*!<Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       0x00002000U            /*!<Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      0x00004000U            /*!<Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    0x00008000U            /*!<Bidirectional data mode enable      */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     0x00000001U               /*!<Rx Buffer DMA Enable                 */
-#define  SPI_CR2_TXDMAEN                     0x00000002U               /*!<Tx Buffer DMA Enable                 */
-#define  SPI_CR2_SSOE                        0x00000004U               /*!<SS Output Enable                     */
-#define  SPI_CR2_FRF                         0x00000010U               /*!<Frame Format                         */
-#define  SPI_CR2_ERRIE                       0x00000020U               /*!<Error Interrupt Enable               */
-#define  SPI_CR2_RXNEIE                      0x00000040U               /*!<RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       0x00000080U               /*!<Tx buffer Empty Interrupt Enable     */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         0x00000001U               /*!<Receive buffer Not Empty */
-#define  SPI_SR_TXE                          0x00000002U               /*!<Transmit buffer Empty    */
-#define  SPI_SR_CHSIDE                       0x00000004U               /*!<Channel side             */
-#define  SPI_SR_UDR                          0x00000008U               /*!<Underrun flag            */
-#define  SPI_SR_CRCERR                       0x00000010U               /*!<CRC Error flag           */
-#define  SPI_SR_MODF                         0x00000020U               /*!<Mode fault               */
-#define  SPI_SR_OVR                          0x00000040U               /*!<Overrun flag             */
-#define  SPI_SR_BSY                          0x00000080U               /*!<Busy flag                */
-#define  SPI_SR_FRE                          0x00000100U               /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           0x0000FFFFU            /*!<Data Register           */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   0x0000FFFFU            /*!<CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    0x0000FFFFU            /*!<Rx CRC Register         */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    0x0000FFFFU            /*!<Tx CRC Register         */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   0x00000001U            /*!<Channel length (number of bits per audio channel) */
-
-#define  SPI_I2SCFGR_DATLEN                  0x00000006U            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define  SPI_I2SCFGR_DATLEN_0                0x00000002U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                0x00000004U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_CKPOL                   0x00000008U            /*!<steady state clock polarity               */
-
-#define  SPI_I2SCFGR_I2SSTD                  0x00000030U            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U            /*!<PCM frame synchronization                 */
-
-#define  SPI_I2SCFGR_I2SCFG                  0x00000300U            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_I2SE                    0x00000400U            /*!<I2S Enable         */
-#define  SPI_I2SCFGR_I2SMOD                  0x00000800U            /*!<I2S mode selection */
-#define  SPI_I2SCFGR_ASTRTEN                 0x00001000U            /*!<Asynchronous start enable */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    0x000000FFU            /*!<I2S Linear prescaler         */
-#define  SPI_I2SPR_ODD                       0x00000100U            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     0x00000200U            /*!<Master Clock Output Enable   */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 SYSCFG                                     */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
-#define SYSCFG_MEMRMP_MEM_MODE          0x00000007U /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        0x00000001U
-#define SYSCFG_MEMRMP_MEM_MODE_1        0x00000002U
-#define SYSCFG_MEMRMP_MEM_MODE_2        0x00000004U
-
-#define SYSCFG_MEMRMP_UFB_MODE          0x00000100U /*!< User Flash Bank mode    */
-#define SYSCFG_SWP_FMC                  0x00000C00U /*!< FMC memory mapping swap */
-
-/******************  Bit definition for SYSCFG_PMC register  ******************/
-#define SYSCFG_PMC_ADCxDC2              0x00070000U /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC1DC2              0x00010000U /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC2DC2              0x00020000U /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC3DC2              0x00040000U /*!< Refer to AN4073 on how to use this bit  */
-
-#define SYSCFG_PMC_MII_RMII_SEL         0x00800000U /*!<Ethernet PHY interface selection */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
-/** 
-  * @brief   EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         0x0003U /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         0x0004U /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         0x0005U /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         0x0006U /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PI         0x0008U /*!<PI[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PJ         0x0009U /*!<PJ[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PK         0x000AU /*!<PK[0] pin */
-
-/** 
-  * @brief   EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         0x0030U /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         0x0040U /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         0x0050U /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         0x0060U /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PI         0x0080U /*!<PI[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PJ         0x0090U /*!<PJ[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PK         0x00A0U /*!<PK[1] pin */
-
-
-/** 
-  * @brief   EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         0x0300U /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         0x0400U /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         0x0500U /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         0x0600U /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PI         0x0800U /*!<PI[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PJ         0x0900U /*!<PJ[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PK         0x0A00U /*!<PK[2] pin */
-
-
-/** 
-  * @brief   EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         0x3000U /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         0x4000U /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         0x5000U /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         0x6000U /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PI         0x8000U /*!<PI[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PJ         0x9000U /*!<PJ[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PK         0xA000U /*!<PK[3] pin */
-
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
-/** 
-  * @brief   EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         0x0003U /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         0x0004U /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         0x0005U /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         0x0006U /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PI         0x0008U /*!<PI[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PJ         0x0009U /*!<PJ[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PK         0x000AU /*!<PK[4] pin */
-
-/** 
-  * @brief   EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         0x0030U /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         0x0040U /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         0x0050U /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         0x0060U /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PI         0x0080U /*!<PI[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PJ         0x0090U /*!<PJ[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PK         0x00A0U /*!<PK[5] pin */
-
-/** 
-  * @brief   EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         0x0300U /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         0x0400U /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         0x0500U /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         0x0600U /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PI         0x0800U /*!<PI[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PJ         0x0900U /*!<PJ[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PK         0x0A00U /*!<PK[6] pin */
-
-
-/** 
-  * @brief   EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         0x3000U /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         0x4000U /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         0x5000U /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         0x6000U /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PI         0x8000U /*!<PI[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PJ         0x9000U /*!<PJ[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PK         0xA000U /*!<PK[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
-           
-/** 
-  * @brief   EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         0x0003U /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         0x0004U /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         0x0005U /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         0x0006U /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PI         0x0008U /*!<PI[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PJ         0x0009U /*!<PJ[8] pin */
-
-/** 
-  * @brief   EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         0x0030U /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         0x0040U /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         0x0050U /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         0x0060U /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PI         0x0080U /*!<PI[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PJ         0x0090U /*!<PJ[9] pin */
-
-
-/** 
-  * @brief   EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        0x0300U /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        0x0400U /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        0x0500U /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        0x0600U /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PI        0x0800U /*!<PI[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PJ        0x0900U /*!<PJ[10] pin */
-
-
-/** 
-  * @brief   EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        0x3000U /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        0x4000U /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        0x5000U /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        0x6000U /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PI        0x8000U /*!<PI[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PJ        0x9000U /*!<PJ[11] pin */
-
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
-/** 
-  * @brief   EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        0x0003U /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        0x0004U /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        0x0005U /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        0x0006U /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PI        0x0008U /*!<PI[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PJ        0x0009U /*!<PJ[12] pin */
-
-
-/** 
-  * @brief   EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        0x0030U /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        0x0040U /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        0x0050U /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        0x0060U /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PI        0x0008U /*!<PI[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PJ        0x0009U /*!<PJ[13] pin */
-
-
-/** 
-  * @brief   EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        0x0300U /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        0x0400U /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        0x0500U /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        0x0600U /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PI        0x0800U /*!<PI[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PJ        0x0900U /*!<PJ[14] pin */
-
-
-/** 
-  * @brief   EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        0x3000U /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        0x4000U /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        0x5000U /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        0x6000U /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PI        0x8000U /*!<PI[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PJ        0x9000U /*!<PJ[15] pin */
-
-/******************  Bit definition for SYSCFG_CMPCR register  ****************/  
-#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell ready flag */
-#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell power-down */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    TIM                                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
-#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
-#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
-#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
-#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
-
-#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
-
-#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
-
-#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        0x0001U            /*!<Capture/Compare Preloaded Control        */
-#define  TIM_CR2_CCUS                        0x0004U            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        0x0008U            /*!<Capture/Compare DMA Selection            */
-
-#define  TIM_CR2_MMS                         0x0070U            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
-#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
-#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
-#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        0x0007U            /*!<SMS[2:0] bits (Slave mode selection)    */
-#define  TIM_SMCR_SMS_0                      0x0001U            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      0x0002U            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      0x0004U            /*!<Bit 2 */
-
-#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
-#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
-
-#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
-
-#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
-
-#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
-#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
-#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
-#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
-#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
-#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
-#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
-#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
-#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
-#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
-#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
-#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
-#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
-#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
-#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
-#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
-#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
-#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
-#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          0x01U               /*!<Update Generation                         */
-#define  TIM_EGR_CC1G                        0x02U               /*!<Capture/Compare 1 Generation              */
-#define  TIM_EGR_CC2G                        0x04U               /*!<Capture/Compare 2 Generation              */
-#define  TIM_EGR_CC3G                        0x08U               /*!<Capture/Compare 3 Generation              */
-#define  TIM_EGR_CC4G                        0x10U               /*!<Capture/Compare 4 Generation              */
-#define  TIM_EGR_COMG                        0x20U               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          0x40U               /*!<Trigger Generation                        */
-#define  TIM_EGR_BG                          0x80U               /*!<Break Generation                          */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      0x0003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    0x0001U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    0x0002U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC1FE                     0x0004U            /*!<Output Compare 1 Fast enable                 */
-#define  TIM_CCMR1_OC1PE                     0x0008U            /*!<Output Compare 1 Preload enable              */
-
-#define  TIM_CCMR1_OC1M                      0x0070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define  TIM_CCMR1_OC1M_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    0x0040U            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC1CE                     0x0080U            /*!<Output Compare 1Clear Enable                 */
-
-#define  TIM_CCMR1_CC2S                      0x0300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    0x0100U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    0x0200U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC2FE                     0x0400U            /*!<Output Compare 2 Fast enable                 */
-#define  TIM_CCMR1_OC2PE                     0x0800U            /*!<Output Compare 2 Preload enable              */
-
-#define  TIM_CCMR1_OC2M                      0x7000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define  TIM_CCMR1_OC2M_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    0x4000U            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC2CE                     0x8000U            /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      0x0003U            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define  TIM_CCMR2_CC3S_0                    0x0001U            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    0x0002U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC3FE                     0x0004U            /*!<Output Compare 3 Fast enable           */
-#define  TIM_CCMR2_OC3PE                     0x0008U            /*!<Output Compare 3 Preload enable        */
-
-#define  TIM_CCMR2_OC3M                      0x0070U            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    0x0040U            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC3CE                     0x0080U            /*!<Output Compare 3 Clear Enable */
-
-#define  TIM_CCMR2_CC4S                      0x0300U            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    0x0100U            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    0x0200U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC4FE                     0x0400U            /*!<Output Compare 4 Fast enable    */
-#define  TIM_CCMR2_OC4PE                     0x0800U            /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR2_OC4M                      0x7000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    0x4000U            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       0x0001U            /*!<Capture/Compare 1 output enable                 */
-#define  TIM_CCER_CC1P                       0x0002U            /*!<Capture/Compare 1 output Polarity               */
-#define  TIM_CCER_CC1NE                      0x0004U            /*!<Capture/Compare 1 Complementary output enable   */
-#define  TIM_CCER_CC1NP                      0x0008U            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       0x0010U            /*!<Capture/Compare 2 output enable                 */
-#define  TIM_CCER_CC2P                       0x0020U            /*!<Capture/Compare 2 output Polarity               */
-#define  TIM_CCER_CC2NE                      0x0040U            /*!<Capture/Compare 2 Complementary output enable   */
-#define  TIM_CCER_CC2NP                      0x0080U            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       0x0100U            /*!<Capture/Compare 3 output enable                 */
-#define  TIM_CCER_CC3P                       0x0200U            /*!<Capture/Compare 3 output Polarity               */
-#define  TIM_CCER_CC3NE                      0x0400U            /*!<Capture/Compare 3 Complementary output enable   */
-#define  TIM_CCER_CC3NP                      0x0800U            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       0x1000U            /*!<Capture/Compare 4 output enable                 */
-#define  TIM_CCER_CC4P                       0x2000U            /*!<Capture/Compare 4 output Polarity               */
-#define  TIM_CCER_CC4NP                      0x8000U            /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         0xFFU               /*!<Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
-
-/*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        0x00FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      0x0001U            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      0x0002U            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      0x0004U            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      0x0008U            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      0x0010U            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      0x0020U            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      0x0040U            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      0x0080U            /*!<Bit 7 */
-
-#define  TIM_BDTR_LOCK                       0x0300U            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     0x0100U            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     0x0200U            /*!<Bit 1 */
-
-#define  TIM_BDTR_OSSI                       0x0400U            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       0x0800U            /*!<Off-State Selection for Run mode  */
-#define  TIM_BDTR_BKE                        0x1000U            /*!<Break enable                      */
-#define  TIM_BDTR_BKP                        0x2000U            /*!<Break Polarity                    */
-#define  TIM_BDTR_AOE                        0x4000U            /*!<Automatic Output enable           */
-#define  TIM_BDTR_MOE                        0x8000U            /*!<Main Output enable                */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
-
-#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
-#define TIM_OR_ITR1_RMP                      0x0C00U            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
-#define TIM_OR_ITR1_RMP_0                    0x0400U            /*!<Bit 0 */
-#define TIM_OR_ITR1_RMP_1                    0x0800U            /*!<Bit 1 */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*         Universal Synchronous Asynchronous Receiver Transmitter            */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         0x0001U            /*!<Parity Error                 */
-#define  USART_SR_FE                         0x0002U            /*!<Framing Error                */
-#define  USART_SR_NE                         0x0004U            /*!<Noise Error Flag             */
-#define  USART_SR_ORE                        0x0008U            /*!<OverRun Error                */
-#define  USART_SR_IDLE                       0x0010U            /*!<IDLE line detected           */
-#define  USART_SR_RXNE                       0x0020U            /*!<Read Data Register Not Empty */
-#define  USART_SR_TC                         0x0040U            /*!<Transmission Complete        */
-#define  USART_SR_TXE                        0x0080U            /*!<Transmit Data Register Empty */
-#define  USART_SR_LBD                        0x0100U            /*!<LIN Break Detection Flag     */
-#define  USART_SR_CTS                        0x0200U            /*!<CTS Flag                     */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         0x01FFU            /*!<Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_Fraction              0x000FU            /*!<Fraction of USARTDIV */
-#define  USART_BRR_DIV_Mantissa              0xFFF0U            /*!<Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       0x0001U            /*!<Send Break                             */
-#define  USART_CR1_RWU                       0x0002U            /*!<Receiver wakeup                        */
-#define  USART_CR1_RE                        0x0004U            /*!<Receiver Enable                        */
-#define  USART_CR1_TE                        0x0008U            /*!<Transmitter Enable                     */
-#define  USART_CR1_IDLEIE                    0x0010U            /*!<IDLE Interrupt Enable                  */
-#define  USART_CR1_RXNEIE                    0x0020U            /*!<RXNE Interrupt Enable                  */
-#define  USART_CR1_TCIE                      0x0040U            /*!<Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     0x0080U            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PEIE                      0x0100U            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PS                        0x0200U            /*!<Parity Selection                       */
-#define  USART_CR1_PCE                       0x0400U            /*!<Parity Control Enable                  */
-#define  USART_CR1_WAKE                      0x0800U            /*!<Wakeup method                          */
-#define  USART_CR1_M                         0x1000U            /*!<Word length                            */
-#define  USART_CR1_UE                        0x2000U            /*!<USART Enable                           */
-#define  USART_CR1_OVER8                     0x8000U            /*!<USART Oversampling by 8 enable         */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       0x000FU            /*!<Address of the USART node            */
-#define  USART_CR2_LBDL                      0x0020U            /*!<LIN Break Detection Length           */
-#define  USART_CR2_LBDIE                     0x0040U            /*!<LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      0x0100U            /*!<Last Bit Clock pulse                 */
-#define  USART_CR2_CPHA                      0x0200U            /*!<Clock Phase                          */
-#define  USART_CR2_CPOL                      0x0400U            /*!<Clock Polarity                       */
-#define  USART_CR2_CLKEN                     0x0800U            /*!<Clock Enable                         */
-
-#define  USART_CR2_STOP                      0x3000U            /*!<STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    0x1000U            /*!<Bit 0 */
-#define  USART_CR2_STOP_1                    0x2000U            /*!<Bit 1 */
-
-#define  USART_CR2_LINEN                     0x4000U            /*!<LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       0x0001U            /*!<Error Interrupt Enable      */
-#define  USART_CR3_IREN                      0x0002U            /*!<IrDA mode Enable            */
-#define  USART_CR3_IRLP                      0x0004U            /*!<IrDA Low-Power              */
-#define  USART_CR3_HDSEL                     0x0008U            /*!<Half-Duplex Selection       */
-#define  USART_CR3_NACK                      0x0010U            /*!<Smartcard NACK enable       */
-#define  USART_CR3_SCEN                      0x0020U            /*!<Smartcard mode enable       */
-#define  USART_CR3_DMAR                      0x0040U            /*!<DMA Enable Receiver         */
-#define  USART_CR3_DMAT                      0x0080U            /*!<DMA Enable Transmitter      */
-#define  USART_CR3_RTSE                      0x0100U            /*!<RTS Enable                  */
-#define  USART_CR3_CTSE                      0x0200U            /*!<CTS Enable                  */
-#define  USART_CR3_CTSIE                     0x0400U            /*!<CTS Interrupt Enable        */
-#define  USART_CR3_ONEBIT                    0x0800U            /*!<USART One bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      0x00FFU            /*!<PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    0x0001U            /*!<Bit 0 */
-#define  USART_GTPR_PSC_1                    0x0002U            /*!<Bit 1 */
-#define  USART_GTPR_PSC_2                    0x0004U            /*!<Bit 2 */
-#define  USART_GTPR_PSC_3                    0x0008U            /*!<Bit 3 */
-#define  USART_GTPR_PSC_4                    0x0010U            /*!<Bit 4 */
-#define  USART_GTPR_PSC_5                    0x0020U            /*!<Bit 5 */
-#define  USART_GTPR_PSC_6                    0x0040U            /*!<Bit 6 */
-#define  USART_GTPR_PSC_7                    0x0080U            /*!<Bit 7 */
-
-#define  USART_GTPR_GT                       0xFF00U            /*!<Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Window WATCHDOG                                 */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           0x7FU               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T_0                         0x01U               /*!<Bit 0 */
-#define  WWDG_CR_T_1                         0x02U               /*!<Bit 1 */
-#define  WWDG_CR_T_2                         0x04U               /*!<Bit 2 */
-#define  WWDG_CR_T_3                         0x08U               /*!<Bit 3 */
-#define  WWDG_CR_T_4                         0x10U               /*!<Bit 4 */
-#define  WWDG_CR_T_5                         0x20U               /*!<Bit 5 */
-#define  WWDG_CR_T_6                         0x40U               /*!<Bit 6 */
-/* Legacy defines */
-#define  WWDG_CR_T0                          WWDG_CR_T_0
-#define  WWDG_CR_T1                          WWDG_CR_T_1
-#define  WWDG_CR_T2                          WWDG_CR_T_2
-#define  WWDG_CR_T3                          WWDG_CR_T_3
-#define  WWDG_CR_T4                          WWDG_CR_T_4
-#define  WWDG_CR_T5                          WWDG_CR_T_5
-#define  WWDG_CR_T6                          WWDG_CR_T_6
-
-#define  WWDG_CR_WDGA                        0x80U               /*!<Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          0x007FU            /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W_0                        0x0001U            /*!<Bit 0 */
-#define  WWDG_CFR_W_1                        0x0002U            /*!<Bit 1 */
-#define  WWDG_CFR_W_2                        0x0004U            /*!<Bit 2 */
-#define  WWDG_CFR_W_3                        0x0008U            /*!<Bit 3 */
-#define  WWDG_CFR_W_4                        0x0010U            /*!<Bit 4 */
-#define  WWDG_CFR_W_5                        0x0020U            /*!<Bit 5 */
-#define  WWDG_CFR_W_6                        0x0040U            /*!<Bit 6 */
-/* Legacy defines */
-#define  WWDG_CFR_W0                         WWDG_CFR_W_0
-#define  WWDG_CFR_W1                         WWDG_CFR_W_1
-#define  WWDG_CFR_W2                         WWDG_CFR_W_2
-#define  WWDG_CFR_W3                         WWDG_CFR_W_3
-#define  WWDG_CFR_W4                         WWDG_CFR_W_4
-#define  WWDG_CFR_W5                         WWDG_CFR_W_5
-#define  WWDG_CFR_W6                         WWDG_CFR_W_6
-
-#define  WWDG_CFR_WDGTB                      0x0180U            /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB_0                    0x0080U            /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB_1                    0x0100U            /*!<Bit 1 */
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
-
-#define  WWDG_CFR_EWI                        0x0200U            /*!<Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        0x01U               /*!<Early Wakeup Interrupt Flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                DBG                                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
-#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
-
-/********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
-#define  DBGMCU_CR_DBG_STOP                  0x00000002U
-#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
-#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
-
-#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
-#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U/*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U/*!<Bit 1 */
-
-/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            0x00000001U
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            0x00000002U
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            0x00000004U
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            0x00000020U
-#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           0x00000040U
-#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           0x00000080U
-#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           0x00000100U
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
-#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
-/* Old IWDGSTOP bit definition, maintained for legacy purpose */
-#define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
-
-/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        0x00000001U
-#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        0x00000002U
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        0x00010000U
-#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       0x00020000U
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       0x00040000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                Ethernet MAC Registers bits definitions                     */
-/*                                                                            */
-/******************************************************************************/
-/* Bit definition for Ethernet MAC Control Register register */
-#define ETH_MACCR_WD      0x00800000U  /* Watchdog disable */
-#define ETH_MACCR_JD      0x00400000U  /* Jabber disable */
-#define ETH_MACCR_IFG     0x000E0000U  /* Inter-frame gap */
-#define ETH_MACCR_IFG_96Bit     0x00000000U  /* Minimum IFG between frames during transmission is 96Bit */
-  #define ETH_MACCR_IFG_88Bit     0x00020000U  /* Minimum IFG between frames during transmission is 88Bit */
-  #define ETH_MACCR_IFG_80Bit     0x00040000U  /* Minimum IFG between frames during transmission is 80Bit */
-  #define ETH_MACCR_IFG_72Bit     0x00060000U  /* Minimum IFG between frames during transmission is 72Bit */
-  #define ETH_MACCR_IFG_64Bit     0x00080000U  /* Minimum IFG between frames during transmission is 64Bit */        
-  #define ETH_MACCR_IFG_56Bit     0x000A0000U  /* Minimum IFG between frames during transmission is 56Bit */
-  #define ETH_MACCR_IFG_48Bit     0x000C0000U  /* Minimum IFG between frames during transmission is 48Bit */
-  #define ETH_MACCR_IFG_40Bit     0x000E0000U  /* Minimum IFG between frames during transmission is 40Bit */              
-#define ETH_MACCR_CSD     0x00010000U  /* Carrier sense disable (during transmission) */
-#define ETH_MACCR_FES     0x00004000U  /* Fast ethernet speed */
-#define ETH_MACCR_ROD     0x00002000U  /* Receive own disable */
-#define ETH_MACCR_LM      0x00001000U  /* loopback mode */
-#define ETH_MACCR_DM      0x00000800U  /* Duplex mode */
-#define ETH_MACCR_IPCO    0x00000400U  /* IP Checksum offload */
-#define ETH_MACCR_RD      0x00000200U  /* Retry disable */
-#define ETH_MACCR_APCS    0x00000080U  /* Automatic Pad/CRC stripping */
-#define ETH_MACCR_BL      0x00000060U  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
-                                                       a transmission attempt during retries after a collision: 0 =< r <2^k */
-  #define ETH_MACCR_BL_10    0x00000000U  /* k = min (n, 10) */
-  #define ETH_MACCR_BL_8     0x00000020U  /* k = min (n, 8) */
-  #define ETH_MACCR_BL_4     0x00000040U  /* k = min (n, 4) */
-  #define ETH_MACCR_BL_1     0x00000060U  /* k = min (n, 1) */ 
-#define ETH_MACCR_DC      0x00000010U  /* Defferal check */
-#define ETH_MACCR_TE      0x00000008U  /* Transmitter enable */
-#define ETH_MACCR_RE      0x00000004U  /* Receiver enable */
-
-/* Bit definition for Ethernet MAC Frame Filter Register */
-#define ETH_MACFFR_RA     0x80000000U  /* Receive all */ 
-#define ETH_MACFFR_HPF    0x00000400U  /* Hash or perfect filter */ 
-#define ETH_MACFFR_SAF    0x00000200U  /* Source address filter enable */ 
-#define ETH_MACFFR_SAIF   0x00000100U  /* SA inverse filtering */ 
-#define ETH_MACFFR_PCF    0x000000C0U  /* Pass control frames: 3 cases */
-  #define ETH_MACFFR_PCF_BlockAll                0x00000040U  /* MAC filters all control frames from reaching the application */
-  #define ETH_MACFFR_PCF_ForwardAll              0x00000080U  /* MAC forwards all control frames to application even if they fail the Address Filter */
-  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U  /* MAC forwards control frames that pass the Address Filter. */ 
-#define ETH_MACFFR_BFD    0x00000020U  /* Broadcast frame disable */ 
-#define ETH_MACFFR_PAM    0x00000010U  /* Pass all mutlicast */ 
-#define ETH_MACFFR_DAIF   0x00000008U  /* DA Inverse filtering */ 
-#define ETH_MACFFR_HM     0x00000004U  /* Hash multicast */ 
-#define ETH_MACFFR_HU     0x00000002U  /* Hash unicast */
-#define ETH_MACFFR_PM     0x00000001U  /* Promiscuous mode */
-
-/* Bit definition for Ethernet MAC Hash Table High Register */
-#define ETH_MACHTHR_HTH   0xFFFFFFFFU  /* Hash table high */
-
-/* Bit definition for Ethernet MAC Hash Table Low Register */
-#define ETH_MACHTLR_HTL   0xFFFFFFFFU  /* Hash table low */
-
-/* Bit definition for Ethernet MAC MII Address Register */
-#define ETH_MACMIIAR_PA   0x0000F800U  /* Physical layer address */ 
-#define ETH_MACMIIAR_MR   0x000007C0U  /* MII register in the selected PHY */ 
-#define ETH_MACMIIAR_CR   0x0000001CU  /* CR clock range: 6 cases */ 
-  #define ETH_MACMIIAR_CR_Div42   0x00000000U  /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
-  #define ETH_MACMIIAR_CR_Div62   0x00000004U  /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
-  #define ETH_MACMIIAR_CR_Div16   0x00000008U  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
-  #define ETH_MACMIIAR_CR_Div26   0x0000000CU  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
-  #define ETH_MACMIIAR_CR_Div102  0x00000010U  /* HCLK:150-168 MHz; MDC clock= HCLK/102 */  
-#define ETH_MACMIIAR_MW   0x00000002U  /* MII write */ 
-#define ETH_MACMIIAR_MB   0x00000001U  /* MII busy */ 
-  
-/* Bit definition for Ethernet MAC MII Data Register */
-#define ETH_MACMIIDR_MD   0x0000FFFFU  /* MII data: read/write data from/to PHY */
-
-/* Bit definition for Ethernet MAC Flow Control Register */
-#define ETH_MACFCR_PT     0xFFFF0000U  /* Pause time */
-#define ETH_MACFCR_ZQPD   0x00000080U  /* Zero-quanta pause disable */
-#define ETH_MACFCR_PLT    0x00000030U  /* Pause low threshold: 4 cases */
-  #define ETH_MACFCR_PLT_Minus4   0x00000000U  /* Pause time minus 4 slot times */
-  #define ETH_MACFCR_PLT_Minus28  0x00000010U  /* Pause time minus 28 slot times */
-  #define ETH_MACFCR_PLT_Minus144 0x00000020U  /* Pause time minus 144 slot times */
-  #define ETH_MACFCR_PLT_Minus256 0x00000030U  /* Pause time minus 256 slot times */      
-#define ETH_MACFCR_UPFD   0x00000008U  /* Unicast pause frame detect */
-#define ETH_MACFCR_RFCE   0x00000004U  /* Receive flow control enable */
-#define ETH_MACFCR_TFCE   0x00000002U  /* Transmit flow control enable */
-#define ETH_MACFCR_FCBBPA 0x00000001U  /* Flow control busy/backpressure activate */
-
-/* Bit definition for Ethernet MAC VLAN Tag Register */
-#define ETH_MACVLANTR_VLANTC 0x00010000U  /* 12-bit VLAN tag comparison */
-#define ETH_MACVLANTR_VLANTI 0x0000FFFFU  /* VLAN tag identifier (for receive frames) */
-
-/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ 
-#define ETH_MACRWUFFR_D   0xFFFFFFFFU  /* Wake-up frame filter register data */
-/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
-   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
-/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
-   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
-   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
-   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
-   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - 
-                              RSVD - Filter1 Command - RSVD - Filter0 Command
-   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
-   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
-   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
-
-/* Bit definition for Ethernet MAC PMT Control and Status Register */ 
-#define ETH_MACPMTCSR_WFFRPR 0x80000000U  /* Wake-Up Frame Filter Register Pointer Reset */
-#define ETH_MACPMTCSR_GU     0x00000200U  /* Global Unicast */
-#define ETH_MACPMTCSR_WFR    0x00000040U  /* Wake-Up Frame Received */
-#define ETH_MACPMTCSR_MPR    0x00000020U  /* Magic Packet Received */
-#define ETH_MACPMTCSR_WFE    0x00000004U  /* Wake-Up Frame Enable */
-#define ETH_MACPMTCSR_MPE    0x00000002U  /* Magic Packet Enable */
-#define ETH_MACPMTCSR_PD     0x00000001U  /* Power Down */
-
-/* Bit definition for Ethernet MAC Status Register */
-#define ETH_MACSR_TSTS      0x00000200U  /* Time stamp trigger status */
-#define ETH_MACSR_MMCTS     0x00000040U  /* MMC transmit status */
-#define ETH_MACSR_MMMCRS    0x00000020U  /* MMC receive status */
-#define ETH_MACSR_MMCS      0x00000010U  /* MMC status */
-#define ETH_MACSR_PMTS      0x00000008U  /* PMT status */
-
-/* Bit definition for Ethernet MAC Interrupt Mask Register */
-#define ETH_MACIMR_TSTIM     0x00000200U  /* Time stamp trigger interrupt mask */
-#define ETH_MACIMR_PMTIM     0x00000008U  /* PMT interrupt mask */
-
-/* Bit definition for Ethernet MAC Address0 High Register */
-#define ETH_MACA0HR_MACA0H   0x0000FFFFU  /* MAC address0 high */
-
-/* Bit definition for Ethernet MAC Address0 Low Register */
-#define ETH_MACA0LR_MACA0L   0xFFFFFFFFU  /* MAC address0 low */
-
-/* Bit definition for Ethernet MAC Address1 High Register */
-#define ETH_MACA1HR_AE       0x80000000U  /* Address enable */
-#define ETH_MACA1HR_SA       0x40000000U  /* Source address */
-#define ETH_MACA1HR_MBC      0x3F000000U  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
-  #define ETH_MACA1HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA1HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA1HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA1HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA1HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA1HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [7:0] */ 
-#define ETH_MACA1HR_MACA1H   0x0000FFFFU  /* MAC address1 high */
-
-/* Bit definition for Ethernet MAC Address1 Low Register */
-#define ETH_MACA1LR_MACA1L   0xFFFFFFFFU  /* MAC address1 low */
-
-/* Bit definition for Ethernet MAC Address2 High Register */
-#define ETH_MACA2HR_AE       0x80000000U  /* Address enable */
-#define ETH_MACA2HR_SA       0x40000000U  /* Source address */
-#define ETH_MACA2HR_MBC      0x3F000000U  /* Mask byte control */
-  #define ETH_MACA2HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA2HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA2HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA2HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA2HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA2HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA2HR_MACA2H   0x0000FFFFU  /* MAC address1 high */
-
-/* Bit definition for Ethernet MAC Address2 Low Register */
-#define ETH_MACA2LR_MACA2L   0xFFFFFFFFU  /* MAC address2 low */
-
-/* Bit definition for Ethernet MAC Address3 High Register */
-#define ETH_MACA3HR_AE       0x80000000U  /* Address enable */
-#define ETH_MACA3HR_SA       0x40000000U  /* Source address */
-#define ETH_MACA3HR_MBC      0x3F000000U  /* Mask byte control */
-  #define ETH_MACA3HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA3HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA3HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA3HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA3HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA3HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA3HR_MACA3H   0x0000FFFFU  /* MAC address3 high */
-
-/* Bit definition for Ethernet MAC Address3 Low Register */
-#define ETH_MACA3LR_MACA3L   0xFFFFFFFFU  /* MAC address3 low */
-
-/******************************************************************************/
-/*                Ethernet MMC Registers bits definition                      */
-/******************************************************************************/
-
-/* Bit definition for Ethernet MMC Contol Register */
-#define ETH_MMCCR_MCFHP      0x00000020U  /* MMC counter Full-Half preset */
-#define ETH_MMCCR_MCP        0x00000010U  /* MMC counter preset */
-#define ETH_MMCCR_MCF        0x00000008U  /* MMC Counter Freeze */
-#define ETH_MMCCR_ROR        0x00000004U  /* Reset on Read */
-#define ETH_MMCCR_CSR        0x00000002U  /* Counter Stop Rollover */
-#define ETH_MMCCR_CR         0x00000001U  /* Counters Reset */
-
-/* Bit definition for Ethernet MMC Receive Interrupt Register */
-#define ETH_MMCRIR_RGUFS     0x00020000U  /* Set when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIR_RFAES     0x00000040U  /* Set when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIR_RFCES     0x00000020U  /* Set when Rx crc error counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmit Interrupt Register */
-#define ETH_MMCTIR_TGFS      0x00200000U  /* Set when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFMSCS   0x00008000U  /* Set when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFSCS    0x00004000U  /* Set when Tx good single col counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
-#define ETH_MMCRIMR_RGUFM    0x00020000U  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFAEM    0x00000040U  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFCEM    0x00000020U  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
-#define ETH_MMCTIMR_TGFM     0x00200000U  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFMSCM  0x00008000U  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFSCM   0x00004000U  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
-#define ETH_MMCTGFSCCR_TGFSCC     0xFFFFFFFFU  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
-#define ETH_MMCTGFMSCCR_TGFMSCC   0xFFFFFFFFU  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
-#define ETH_MMCTGFCR_TGFC    0xFFFFFFFFU  /* Number of good frames transmitted. */
-
-/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
-#define ETH_MMCRFCECR_RFCEC  0xFFFFFFFFU  /* Number of frames received with CRC error. */
-
-/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
-#define ETH_MMCRFAECR_RFAEC  0xFFFFFFFFU  /* Number of frames received with alignment (dribble) error */
-
-/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
-#define ETH_MMCRGUFCR_RGUFC  0xFFFFFFFFU  /* Number of good unicast frames received. */
-
-/******************************************************************************/
-/*               Ethernet PTP Registers bits definition                       */
-/******************************************************************************/
-
-/* Bit definition for Ethernet PTP Time Stamp Contol Register */
-#define ETH_PTPTSCR_TSCNT       0x00030000U  /* Time stamp clock node type */
-#define ETH_PTPTSSR_TSSMRME     0x00008000U  /* Time stamp snapshot for message relevant to master enable */
-#define ETH_PTPTSSR_TSSEME      0x00004000U  /* Time stamp snapshot for event message enable */
-#define ETH_PTPTSSR_TSSIPV4FE   0x00002000U  /* Time stamp snapshot for IPv4 frames enable */
-#define ETH_PTPTSSR_TSSIPV6FE   0x00001000U  /* Time stamp snapshot for IPv6 frames enable */
-#define ETH_PTPTSSR_TSSPTPOEFE  0x00000800U  /* Time stamp snapshot for PTP over ethernet frames enable */
-#define ETH_PTPTSSR_TSPTPPSV2E  0x00000400U  /* Time stamp PTP packet snooping for version2 format enable */
-#define ETH_PTPTSSR_TSSSR       0x00000200U  /* Time stamp Sub-seconds rollover */
-#define ETH_PTPTSSR_TSSARFE     0x00000100U  /* Time stamp snapshot for all received frames enable */
-
-#define ETH_PTPTSCR_TSARU    0x00000020U  /* Addend register update */
-#define ETH_PTPTSCR_TSITE    0x00000010U  /* Time stamp interrupt trigger enable */
-#define ETH_PTPTSCR_TSSTU    0x00000008U  /* Time stamp update */
-#define ETH_PTPTSCR_TSSTI    0x00000004U  /* Time stamp initialize */
-#define ETH_PTPTSCR_TSFCU    0x00000002U  /* Time stamp fine or coarse update */
-#define ETH_PTPTSCR_TSE      0x00000001U  /* Time stamp enable */
-
-/* Bit definition for Ethernet PTP Sub-Second Increment Register */
-#define ETH_PTPSSIR_STSSI    0x000000FFU  /* System time Sub-second increment value */
-
-/* Bit definition for Ethernet PTP Time Stamp High Register */
-#define ETH_PTPTSHR_STS      0xFFFFFFFFU  /* System Time second */
-
-/* Bit definition for Ethernet PTP Time Stamp Low Register */
-#define ETH_PTPTSLR_STPNS    0x80000000U  /* System Time Positive or negative time */
-#define ETH_PTPTSLR_STSS     0x7FFFFFFFU  /* System Time sub-seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp High Update Register */
-#define ETH_PTPTSHUR_TSUS    0xFFFFFFFFU  /* Time stamp update seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
-#define ETH_PTPTSLUR_TSUPNS  0x80000000U  /* Time stamp update Positive or negative time */
-#define ETH_PTPTSLUR_TSUSS   0x7FFFFFFFU  /* Time stamp update sub-seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp Addend Register */
-#define ETH_PTPTSAR_TSA      0xFFFFFFFFU  /* Time stamp addend */
-
-/* Bit definition for Ethernet PTP Target Time High Register */
-#define ETH_PTPTTHR_TTSH     0xFFFFFFFFU  /* Target time stamp high */
-
-/* Bit definition for Ethernet PTP Target Time Low Register */
-#define ETH_PTPTTLR_TTSL     0xFFFFFFFFU  /* Target time stamp low */
-
-/* Bit definition for Ethernet PTP Time Stamp Status Register */
-#define ETH_PTPTSSR_TSTTR    0x00000020U  /* Time stamp target time reached */
-#define ETH_PTPTSSR_TSSO     0x00000010U  /* Time stamp seconds overflow */
-
-/******************************************************************************/
-/*                 Ethernet DMA Registers bits definition                     */
-/******************************************************************************/
-
-/* Bit definition for Ethernet DMA Bus Mode Register */
-#define ETH_DMABMR_AAB       0x02000000U  /* Address-Aligned beats */
-#define ETH_DMABMR_FPM        0x01000000U  /* 4xPBL mode */
-#define ETH_DMABMR_USP       0x00800000U  /* Use separate PBL */
-#define ETH_DMABMR_RDP       0x007E0000U  /* RxDMA PBL */
-  #define ETH_DMABMR_RDP_1Beat    0x00020000U  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
-  #define ETH_DMABMR_RDP_2Beat    0x00040000U  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
-  #define ETH_DMABMR_RDP_4Beat    0x00080000U  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-  #define ETH_DMABMR_RDP_8Beat    0x00100000U  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-  #define ETH_DMABMR_RDP_16Beat   0x00200000U  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-  #define ETH_DMABMR_RDP_32Beat   0x00400000U  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */                
-  #define ETH_DMABMR_RDP_4xPBL_4Beat   0x01020000U  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-  #define ETH_DMABMR_RDP_4xPBL_8Beat   0x01040000U  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-  #define ETH_DMABMR_RDP_4xPBL_16Beat  0x01080000U  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-  #define ETH_DMABMR_RDP_4xPBL_32Beat  0x01100000U  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
-  #define ETH_DMABMR_RDP_4xPBL_64Beat  0x01200000U  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
-  #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */  
-#define ETH_DMABMR_FB        0x00010000U  /* Fixed Burst */
-#define ETH_DMABMR_RTPR      0x0000C000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_1_1     0x00000000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_2_1     0x00004000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_3_1     0x00008000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_4_1     0x0000C000U  /* Rx Tx priority ratio */  
-#define ETH_DMABMR_PBL    0x00003F00U  /* Programmable burst length */
-  #define ETH_DMABMR_PBL_1Beat    0x00000100U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
-  #define ETH_DMABMR_PBL_2Beat    0x00000200U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
-  #define ETH_DMABMR_PBL_4Beat    0x00000400U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-  #define ETH_DMABMR_PBL_8Beat    0x00000800U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-  #define ETH_DMABMR_PBL_16Beat   0x00001000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-  #define ETH_DMABMR_PBL_32Beat   0x00002000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
-  #define ETH_DMABMR_PBL_4xPBL_4Beat   0x01000100U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-  #define ETH_DMABMR_PBL_4xPBL_8Beat   0x01000200U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-  #define ETH_DMABMR_PBL_4xPBL_16Beat  0x01000400U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-  #define ETH_DMABMR_PBL_4xPBL_32Beat  0x01000800U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
-  #define ETH_DMABMR_PBL_4xPBL_64Beat  0x01001000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
-  #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
-#define ETH_DMABMR_EDE       0x00000080U  /* Enhanced Descriptor Enable */
-#define ETH_DMABMR_DSL       0x0000007CU  /* Descriptor Skip Length */
-#define ETH_DMABMR_DA        0x00000002U  /* DMA arbitration scheme */
-#define ETH_DMABMR_SR        0x00000001U  /* Software reset */
-
-/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
-#define ETH_DMATPDR_TPD      0xFFFFFFFFU  /* Transmit poll demand */
-
-/* Bit definition for Ethernet DMA Receive Poll Demand Register */
-#define ETH_DMARPDR_RPD      0xFFFFFFFFU  /* Receive poll demand  */
-
-/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
-#define ETH_DMARDLAR_SRL     0xFFFFFFFFU  /* Start of receive list */
-
-/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
-#define ETH_DMATDLAR_STL     0xFFFFFFFFU  /* Start of transmit list */
-
-/* Bit definition for Ethernet DMA Status Register */
-#define ETH_DMASR_TSTS       0x20000000U  /* Time-stamp trigger status */
-#define ETH_DMASR_PMTS       0x10000000U  /* PMT status */
-#define ETH_DMASR_MMCS       0x08000000U  /* MMC status */
-#define ETH_DMASR_EBS        0x03800000U  /* Error bits status */
-  /* combination with EBS[2:0] for GetFlagStatus function */
-  #define ETH_DMASR_EBS_DescAccess      0x02000000U  /* Error bits 0-data buffer, 1-desc. access */
-  #define ETH_DMASR_EBS_ReadTransf      0x01000000U  /* Error bits 0-write trnsf, 1-read transfr */
-  #define ETH_DMASR_EBS_DataTransfTx    0x00800000U  /* Error bits 0-Rx DMA, 1-Tx DMA */
-#define ETH_DMASR_TPS         0x00700000U  /* Transmit process state */
-  #define ETH_DMASR_TPS_Stopped         0x00000000U  /* Stopped - Reset or Stop Tx Command issued  */
-  #define ETH_DMASR_TPS_Fetching        0x00100000U  /* Running - fetching the Tx descriptor */
-  #define ETH_DMASR_TPS_Waiting         0x00200000U  /* Running - waiting for status */
-  #define ETH_DMASR_TPS_Reading         0x00300000U  /* Running - reading the data from host memory */
-  #define ETH_DMASR_TPS_Suspended       0x00600000U  /* Suspended - Tx Descriptor unavailabe */
-  #define ETH_DMASR_TPS_Closing         0x00700000U  /* Running - closing Rx descriptor */
-#define ETH_DMASR_RPS         0x000E0000U  /* Receive process state */
-  #define ETH_DMASR_RPS_Stopped         0x00000000U  /* Stopped - Reset or Stop Rx Command issued */
-  #define ETH_DMASR_RPS_Fetching        0x00020000U  /* Running - fetching the Rx descriptor */
-  #define ETH_DMASR_RPS_Waiting         0x00060000U  /* Running - waiting for packet */
-  #define ETH_DMASR_RPS_Suspended       0x00080000U  /* Suspended - Rx Descriptor unavailable */
-  #define ETH_DMASR_RPS_Closing         0x000A0000U  /* Running - closing descriptor */
-  #define ETH_DMASR_RPS_Queuing         0x000E0000U  /* Running - queuing the recieve frame into host memory */
-#define ETH_DMASR_NIS        0x00010000U  /* Normal interrupt summary */
-#define ETH_DMASR_AIS        0x00008000U  /* Abnormal interrupt summary */
-#define ETH_DMASR_ERS        0x00004000U  /* Early receive status */
-#define ETH_DMASR_FBES       0x00002000U  /* Fatal bus error status */
-#define ETH_DMASR_ETS        0x00000400U  /* Early transmit status */
-#define ETH_DMASR_RWTS       0x00000200U  /* Receive watchdog timeout status */
-#define ETH_DMASR_RPSS       0x00000100U  /* Receive process stopped status */
-#define ETH_DMASR_RBUS       0x00000080U  /* Receive buffer unavailable status */
-#define ETH_DMASR_RS         0x00000040U  /* Receive status */
-#define ETH_DMASR_TUS        0x00000020U  /* Transmit underflow status */
-#define ETH_DMASR_ROS        0x00000010U  /* Receive overflow status */
-#define ETH_DMASR_TJTS       0x00000008U  /* Transmit jabber timeout status */
-#define ETH_DMASR_TBUS       0x00000004U  /* Transmit buffer unavailable status */
-#define ETH_DMASR_TPSS       0x00000002U  /* Transmit process stopped status */
-#define ETH_DMASR_TS         0x00000001U  /* Transmit status */
-
-/* Bit definition for Ethernet DMA Operation Mode Register */
-#define ETH_DMAOMR_DTCEFD    0x04000000U  /* Disable Dropping of TCP/IP checksum error frames */
-#define ETH_DMAOMR_RSF       0x02000000U  /* Receive store and forward */
-#define ETH_DMAOMR_DFRF      0x01000000U  /* Disable flushing of received frames */
-#define ETH_DMAOMR_TSF       0x00200000U  /* Transmit store and forward */
-#define ETH_DMAOMR_FTF       0x00100000U  /* Flush transmit FIFO */
-#define ETH_DMAOMR_TTC       0x0001C000U  /* Transmit threshold control */
-  #define ETH_DMAOMR_TTC_64Bytes       0x00000000U  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
-  #define ETH_DMAOMR_TTC_128Bytes      0x00004000U  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
-  #define ETH_DMAOMR_TTC_192Bytes      0x00008000U  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
-  #define ETH_DMAOMR_TTC_256Bytes      0x0000C000U  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
-  #define ETH_DMAOMR_TTC_40Bytes       0x00010000U  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
-  #define ETH_DMAOMR_TTC_32Bytes       0x00014000U  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
-  #define ETH_DMAOMR_TTC_24Bytes       0x00018000U  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
-  #define ETH_DMAOMR_TTC_16Bytes       0x0001C000U  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
-#define ETH_DMAOMR_ST        0x00002000U  /* Start/stop transmission command */
-#define ETH_DMAOMR_FEF       0x00000080U  /* Forward error frames */
-#define ETH_DMAOMR_FUGF      0x00000040U  /* Forward undersized good frames */
-#define ETH_DMAOMR_RTC       0x00000018U  /* receive threshold control */
-  #define ETH_DMAOMR_RTC_64Bytes       0x00000000U  /* threshold level of the MTL Receive FIFO is 64 Bytes */
-  #define ETH_DMAOMR_RTC_32Bytes       0x00000008U  /* threshold level of the MTL Receive FIFO is 32 Bytes */
-  #define ETH_DMAOMR_RTC_96Bytes       0x00000010U  /* threshold level of the MTL Receive FIFO is 96 Bytes */
-  #define ETH_DMAOMR_RTC_128Bytes      0x00000018U  /* threshold level of the MTL Receive FIFO is 128 Bytes */
-#define ETH_DMAOMR_OSF       0x00000004U  /* operate on second frame */
-#define ETH_DMAOMR_SR        0x00000002U  /* Start/stop receive */
-
-/* Bit definition for Ethernet DMA Interrupt Enable Register */
-#define ETH_DMAIER_NISE      0x00010000U  /* Normal interrupt summary enable */
-#define ETH_DMAIER_AISE      0x00008000U  /* Abnormal interrupt summary enable */
-#define ETH_DMAIER_ERIE      0x00004000U  /* Early receive interrupt enable */
-#define ETH_DMAIER_FBEIE     0x00002000U  /* Fatal bus error interrupt enable */
-#define ETH_DMAIER_ETIE      0x00000400U  /* Early transmit interrupt enable */
-#define ETH_DMAIER_RWTIE     0x00000200U  /* Receive watchdog timeout interrupt enable */
-#define ETH_DMAIER_RPSIE     0x00000100U  /* Receive process stopped interrupt enable */
-#define ETH_DMAIER_RBUIE     0x00000080U  /* Receive buffer unavailable interrupt enable */
-#define ETH_DMAIER_RIE       0x00000040U  /* Receive interrupt enable */
-#define ETH_DMAIER_TUIE      0x00000020U  /* Transmit Underflow interrupt enable */
-#define ETH_DMAIER_ROIE      0x00000010U  /* Receive Overflow interrupt enable */
-#define ETH_DMAIER_TJTIE     0x00000008U  /* Transmit jabber timeout interrupt enable */
-#define ETH_DMAIER_TBUIE     0x00000004U  /* Transmit buffer unavailable interrupt enable */
-#define ETH_DMAIER_TPSIE     0x00000002U  /* Transmit process stopped interrupt enable */
-#define ETH_DMAIER_TIE       0x00000001U  /* Transmit interrupt enable */
-
-/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
-#define ETH_DMAMFBOCR_OFOC   0x10000000U  /* Overflow bit for FIFO overflow counter */
-#define ETH_DMAMFBOCR_MFA    0x0FFE0000U  /* Number of frames missed by the application */
-#define ETH_DMAMFBOCR_OMFC   0x00010000U  /* Overflow bit for missed frame counter */
-#define ETH_DMAMFBOCR_MFC    0x0000FFFFU  /* Number of frames missed by the controller */
-
-/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
-#define ETH_DMACHTDR_HTDAP   0xFFFFFFFFU  /* Host transmit descriptor address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
-#define ETH_DMACHRDR_HRDAP   0xFFFFFFFFU  /* Host receive descriptor address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
-#define ETH_DMACHTBAR_HTBAP  0xFFFFFFFFU  /* Host transmit buffer address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
-#define ETH_DMACHRBAR_HRBAP  0xFFFFFFFFU  /* Host receive buffer address pointer */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                       USB_OTG                              */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/
-#define USB_OTG_GOTGCTL_SRQSCS                  0x00000001U         /*!< Session request success */
-#define USB_OTG_GOTGCTL_SRQ                     0x00000002U         /*!< Session request */
-#define USB_OTG_GOTGCTL_VBVALOEN                0x00000004U         /*!< VBUS valid override enable */
-#define USB_OTG_GOTGCTL_VBVALOVAL               0x00000008U         /*!< VBUS valid override value */
-#define USB_OTG_GOTGCTL_AVALOEN                 0x00000010U         /*!< A-peripheral session valid override enable */
-#define USB_OTG_GOTGCTL_AVALOVAL                0x00000020U         /*!< A-peripheral session valid override value */
-#define USB_OTG_GOTGCTL_BVALOEN                 0x00000040U         /*!< B-peripheral session valid override enable */
-#define USB_OTG_GOTGCTL_BVALOVAL                0x00000080U         /*!< B-peripheral session valid override value  */
-#define USB_OTG_GOTGCTL_HNGSCS                  0x00000100U         /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_HNPRQ                   0x00000200U         /*!< HNP request */
-#define USB_OTG_GOTGCTL_HSHNPEN                 0x00000400U         /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_DHNPEN                  0x00000800U         /*!< Device HNP enabled */
-#define USB_OTG_GOTGCTL_EHEN                    0x00001000U         /*!< Embedded host enable */
-#define USB_OTG_GOTGCTL_CIDSTS                  0x00010000U         /*!< Connector ID status */
-#define USB_OTG_GOTGCTL_DBCT                    0x00020000U         /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD                   0x00040000U         /*!< A-session valid  */
-#define USB_OTG_GOTGCTL_BSESVLD                 0x00080000U         /*!< B-session valid */
-#define USB_OTG_GOTGCTL_OTGVER                  0x00100000U         /*!< OTG version  */
-
-/********************  Bit definition forUSB_OTG_HCFG register  ********************/
-
-#define USB_OTG_HCFG_FSLSPCS                 0x00000003U            /*!< FS/LS PHY clock select  */
-#define USB_OTG_HCFG_FSLSPCS_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCFG_FSLSPCS_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCFG_FSLSS                   0x00000004U            /*!< FS- and LS-only support */
-
-/********************  Bit definition forUSB_OTG_DCFG register  ********************/
-
-#define USB_OTG_DCFG_DSPD                    0x00000003U            /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                  0x00000001U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DSPD_1                  0x00000002U            /*!<Bit 1 */
-#define USB_OTG_DCFG_NZLSOHSK                0x00000004U            /*!< Nonzero-length status OUT handshake */
-
-#define USB_OTG_DCFG_DAD                     0x000007F0U            /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                   0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DAD_1                   0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCFG_DAD_2                   0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCFG_DAD_3                   0x00000080U            /*!<Bit 3 */
-#define USB_OTG_DCFG_DAD_4                   0x00000100U            /*!<Bit 4 */
-#define USB_OTG_DCFG_DAD_5                   0x00000200U            /*!<Bit 5 */
-#define USB_OTG_DCFG_DAD_6                   0x00000400U            /*!<Bit 6 */
-
-#define USB_OTG_DCFG_PFIVL                   0x00001800U            /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PFIVL_1                 0x00001000U            /*!<Bit 1 */
-
-#define USB_OTG_DCFG_PERSCHIVL               0x03000000U            /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0             0x01000000U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PERSCHIVL_1             0x02000000U            /*!<Bit 1 */
-
-/********************  Bit definition forUSB_OTG_PCGCR register  ********************/
-#define USB_OTG_PCGCR_STPPCLK                 0x00000001U            /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK                0x00000002U            /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP                 0x00000010U            /*!< PHY suspended */
-
-/********************  Bit definition forUSB_OTG_GOTGINT register  ********************/
-#define USB_OTG_GOTGINT_SEDET                   0x00000004U            /*!< Session end detected                   */
-#define USB_OTG_GOTGINT_SRSSCHG                 0x00000100U            /*!< Session request success status change  */
-#define USB_OTG_GOTGINT_HNSSCHG                 0x00000200U            /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET                  0x00020000U            /*!< Host negotiation detected              */
-#define USB_OTG_GOTGINT_ADTOCHG                 0x00040000U            /*!< A-device timeout change                */
-#define USB_OTG_GOTGINT_DBCDNE                  0x00080000U            /*!< Debounce done                          */
-#define USB_OTG_GOTGINT_IDCHNG                  0x00100000U            /*!< Change in ID pin input value           */
-
-/********************  Bit definition forUSB_OTG_DCTL register  ********************/
-#define USB_OTG_DCTL_RWUSIG                  0x00000001U            /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS                    0x00000002U            /*!< Soft disconnect         */
-#define USB_OTG_DCTL_GINSTS                  0x00000004U            /*!< Global IN NAK status    */
-#define USB_OTG_DCTL_GONSTS                  0x00000008U            /*!< Global OUT NAK status   */
-
-#define USB_OTG_DCTL_TCTL                    0x00000070U            /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                  0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCTL_TCTL_1                  0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCTL_TCTL_2                  0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCTL_SGINAK                  0x00000080U            /*!< Set global IN NAK         */
-#define USB_OTG_DCTL_CGINAK                  0x00000100U            /*!< Clear global IN NAK       */
-#define USB_OTG_DCTL_SGONAK                  0x00000200U            /*!< Set global OUT NAK        */
-#define USB_OTG_DCTL_CGONAK                  0x00000400U            /*!< Clear global OUT NAK      */
-#define USB_OTG_DCTL_POPRGDNE                0x00000800U            /*!< Power-on programming done */
-
-/********************  Bit definition forUSB_OTG_HFIR register  ********************/
-#define USB_OTG_HFIR_FRIVL                   0x0000FFFFU            /*!< Frame interval */
-
-/********************  Bit definition forUSB_OTG_HFNUM register  ********************/
-#define USB_OTG_HFNUM_FRNUM                   0x0000FFFFU            /*!< Frame number         */
-#define USB_OTG_HFNUM_FTREM                   0xFFFF0000U            /*!< Frame time remaining */
-
-/********************  Bit definition forUSB_OTG_DSTS register  ********************/
-#define USB_OTG_DSTS_SUSPSTS                 0x00000001U            /*!< Suspend status   */
-
-#define USB_OTG_DSTS_ENUMSPD                 0x00000006U            /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_DSTS_ENUMSPD_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_DSTS_EERR                    0x00000008U            /*!< Erratic error     */
-#define USB_OTG_DSTS_FNSOF                   0x003FFF00U            /*!< Frame number of the received SOF */
-
-/********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/
-#define USB_OTG_GAHBCFG_GINT                    0x00000001U            /*!< Global interrupt mask */
-#define USB_OTG_GAHBCFG_HBSTLEN                 0x0000001EU            /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_GAHBCFG_HBSTLEN_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_GAHBCFG_HBSTLEN_2               0x00000008U            /*!<Bit 2 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3               0x00000010U            /*!<Bit 3 */
-#define USB_OTG_GAHBCFG_DMAEN                   0x00000020U            /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL                 0x00000080U            /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL                0x00000100U            /*!< Periodic TxFIFO empty level */
-
-/********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/
-
-#define USB_OTG_GUSBCFG_TOCAL                   0x00000007U            /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TOCAL_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TOCAL_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_PHYSEL                  0x00000040U            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP                  0x00000100U            /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP                  0x00000200U            /*!< HNP-capable */
-#define USB_OTG_GUSBCFG_TRDT                    0x00003C00U            /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                  0x00000400U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TRDT_1                  0x00000800U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TRDT_2                  0x00001000U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_TRDT_3                  0x00002000U            /*!<Bit 3 */
-#define USB_OTG_GUSBCFG_PHYLPCS                 0x00008000U            /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS                0x00020000U            /*!< ULPI FS/LS select               */
-#define USB_OTG_GUSBCFG_ULPIAR                  0x00040000U            /*!< ULPI Auto-resume                */
-#define USB_OTG_GUSBCFG_ULPICSM                 0x00080000U            /*!< ULPI Clock SuspendM             */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD              0x00100000U            /*!< ULPI External VBUS Drive        */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI              0x00200000U            /*!< ULPI external VBUS indicator    */
-#define USB_OTG_GUSBCFG_TSDPS                   0x00400000U            /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI                    0x00800000U            /*!< Indicator complement            */
-#define USB_OTG_GUSBCFG_PTCI                    0x01000000U            /*!< Indicator pass through          */
-#define USB_OTG_GUSBCFG_ULPIIPD                 0x02000000U            /*!< ULPI interface protect disable  */
-#define USB_OTG_GUSBCFG_FHMOD                   0x20000000U            /*!< Forced host mode                */
-#define USB_OTG_GUSBCFG_FDMOD                   0x40000000U            /*!< Forced peripheral mode          */
-#define USB_OTG_GUSBCFG_CTXPKT                  0x80000000U            /*!< Corrupt Tx packet               */
-
-/********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
-#define USB_OTG_GRSTCTL_CSRST                   0x00000001U            /*!< Core soft reset          */
-#define USB_OTG_GRSTCTL_HSRST                   0x00000002U            /*!< HCLK soft reset          */
-#define USB_OTG_GRSTCTL_FCRST                   0x00000004U            /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH                 0x00000010U            /*!< RxFIFO flush             */
-#define USB_OTG_GRSTCTL_TXFFLSH                 0x00000020U            /*!< TxFIFO flush             */
-#define USB_OTG_GRSTCTL_TXFNUM                  0x000007C0U            /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                0x00000040U            /*!<Bit 0 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                0x00000080U            /*!<Bit 1 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                0x00000100U            /*!<Bit 2 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                0x00000200U            /*!<Bit 3 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                0x00000400U            /*!<Bit 4 */
-#define USB_OTG_GRSTCTL_DMAREQ                  0x40000000U            /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL                  0x80000000U            /*!< AHB master idle */
-
-/********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/
-#define USB_OTG_DIEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask                 */
-#define USB_OTG_DIEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask                  */
-#define USB_OTG_DIEPMSK_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask          */
-#define USB_OTG_DIEPMSK_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask           */
-#define USB_OTG_DIEPMSK_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask                    */
-#define USB_OTG_DIEPMSK_TXFURM                  0x00000100U            /*!< FIFO underrun mask                                */
-#define USB_OTG_DIEPMSK_BIM                     0x00000200U            /*!< BNA interrupt mask                                */
-
-/********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/
-#define USB_OTG_HPTXSTS_PTXFSAVL                0x0000FFFFU            /*!< Periodic transmit data FIFO space available     */
-#define USB_OTG_HPTXSTS_PTXQSAV                 0x00FF0000U            /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0               0x00010000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1               0x00020000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2               0x00040000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3               0x00080000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4               0x00100000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5               0x00200000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6               0x00400000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7               0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_HPTXSTS_PTXQTOP                 0xFF000000U            /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0               0x01000000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1               0x02000000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2               0x04000000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3               0x08000000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4               0x10000000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5               0x20000000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6               0x40000000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7               0x80000000U            /*!<Bit 7 */
-
-/********************  Bit definition forUSB_OTG_HAINT register  ********************/
-#define USB_OTG_HAINT_HAINT                   0x0000FFFFU            /*!< Channel interrupts */
-
-/********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/
-#define USB_OTG_DOEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask               */
-#define USB_OTG_DOEPMSK_STUPM                   0x00000008U            /*!< SETUP phase done mask                          */
-#define USB_OTG_DOEPMSK_OTEPDM                  0x00000010U            /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_OTEPSPRM                0x00000020U            /*!< Status Phase Received mask                     */
-#define USB_OTG_DOEPMSK_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received mask */
-#define USB_OTG_DOEPMSK_OPEM                    0x00000100U            /*!< OUT packet error mask                          */
-#define USB_OTG_DOEPMSK_BOIM                    0x00000200U            /*!< BNA interrupt mask                             */
-
-/********************  Bit definition forUSB_OTG_GINTSTS register  ********************/
-#define USB_OTG_GINTSTS_CMOD                    0x00000001U            /*!< Current mode of operation                      */
-#define USB_OTG_GINTSTS_MMIS                    0x00000002U            /*!< Mode mismatch interrupt                        */
-#define USB_OTG_GINTSTS_OTGINT                  0x00000004U            /*!< OTG interrupt                                  */
-#define USB_OTG_GINTSTS_SOF                     0x00000008U            /*!< Start of frame                                 */
-#define USB_OTG_GINTSTS_RXFLVL                  0x00000010U            /*!< RxFIFO nonempty                                */
-#define USB_OTG_GINTSTS_NPTXFE                  0x00000020U            /*!< Nonperiodic TxFIFO empty                       */
-#define USB_OTG_GINTSTS_GINAKEFF                0x00000040U            /*!< Global IN nonperiodic NAK effective            */
-#define USB_OTG_GINTSTS_BOUTNAKEFF              0x00000080U            /*!< Global OUT NAK effective                       */
-#define USB_OTG_GINTSTS_ESUSP                   0x00000400U            /*!< Early suspend                                  */
-#define USB_OTG_GINTSTS_USBSUSP                 0x00000800U            /*!< USB suspend                                    */
-#define USB_OTG_GINTSTS_USBRST                  0x00001000U            /*!< USB reset                                      */
-#define USB_OTG_GINTSTS_ENUMDNE                 0x00002000U            /*!< Enumeration done                               */
-#define USB_OTG_GINTSTS_ISOODRP                 0x00004000U            /*!< Isochronous OUT packet dropped interrupt       */
-#define USB_OTG_GINTSTS_EOPF                    0x00008000U            /*!< End of periodic frame interrupt                */
-#define USB_OTG_GINTSTS_IEPINT                  0x00040000U            /*!< IN endpoint interrupt                          */
-#define USB_OTG_GINTSTS_OEPINT                  0x00080000U            /*!< OUT endpoint interrupt                         */
-#define USB_OTG_GINTSTS_IISOIXFR                0x00100000U            /*!< Incomplete isochronous IN transfer             */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       0x00200000U            /*!< Incomplete periodic transfer                   */
-#define USB_OTG_GINTSTS_DATAFSUSP               0x00400000U            /*!< Data fetch suspended                           */
-#define USB_OTG_GINTSTS_RSTDET                  0x00800000U            /*!< Reset detected interrupt                       */
-#define USB_OTG_GINTSTS_HPRTINT                 0x01000000U            /*!< Host port interrupt                            */
-#define USB_OTG_GINTSTS_HCINT                   0x02000000U            /*!< Host channels interrupt                        */
-#define USB_OTG_GINTSTS_PTXFE                   0x04000000U            /*!< Periodic TxFIFO empty                          */
-#define USB_OTG_GINTSTS_LPMINT                  0x08000000U            /*!< LPM interrupt                                  */
-#define USB_OTG_GINTSTS_CIDSCHG                 0x10000000U            /*!< Connector ID status change                     */
-#define USB_OTG_GINTSTS_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt                  */
-#define USB_OTG_GINTSTS_SRQINT                  0x40000000U            /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT                  0x80000000U            /*!< Resume/remote wakeup detected interrupt        */
-
-/********************  Bit definition forUSB_OTG_GINTMSK register  ********************/
-#define USB_OTG_GINTMSK_MMISM                   0x00000002U            /*!< Mode mismatch interrupt mask                        */
-#define USB_OTG_GINTMSK_OTGINT                  0x00000004U            /*!< OTG interrupt mask                                  */
-#define USB_OTG_GINTMSK_SOFM                    0x00000008U            /*!< Start of frame mask                                 */
-#define USB_OTG_GINTMSK_RXFLVLM                 0x00000010U            /*!< Receive FIFO nonempty mask                          */
-#define USB_OTG_GINTMSK_NPTXFEM                 0x00000020U            /*!< Nonperiodic TxFIFO empty mask                       */
-#define USB_OTG_GINTMSK_GINAKEFFM               0x00000040U            /*!< Global nonperiodic IN NAK effective mask            */
-#define USB_OTG_GINTMSK_GONAKEFFM               0x00000080U            /*!< Global OUT NAK effective mask                       */
-#define USB_OTG_GINTMSK_ESUSPM                  0x00000400U            /*!< Early suspend mask                                  */
-#define USB_OTG_GINTMSK_USBSUSPM                0x00000800U            /*!< USB suspend mask                                    */
-#define USB_OTG_GINTMSK_USBRST                  0x00001000U            /*!< USB reset mask                                      */
-#define USB_OTG_GINTMSK_ENUMDNEM                0x00002000U            /*!< Enumeration done mask                               */
-#define USB_OTG_GINTMSK_ISOODRPM                0x00004000U            /*!< Isochronous OUT packet dropped interrupt mask       */
-#define USB_OTG_GINTMSK_EOPFM                   0x00008000U            /*!< End of periodic frame interrupt mask                */
-#define USB_OTG_GINTMSK_EPMISM                  0x00020000U            /*!< Endpoint mismatch interrupt mask                    */
-#define USB_OTG_GINTMSK_IEPINT                  0x00040000U            /*!< IN endpoints interrupt mask                         */
-#define USB_OTG_GINTMSK_OEPINT                  0x00080000U            /*!< OUT endpoints interrupt mask                        */
-#define USB_OTG_GINTMSK_IISOIXFRM               0x00100000U            /*!< Incomplete isochronous IN transfer mask             */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         0x00200000U            /*!< Incomplete periodic transfer mask                   */
-#define USB_OTG_GINTMSK_FSUSPM                  0x00400000U            /*!< Data fetch suspended mask                           */
-#define USB_OTG_GINTMSK_RSTDEM                  0x00800000U            /*!< Reset detected interrupt mask                      */
-#define USB_OTG_GINTMSK_PRTIM                   0x01000000U            /*!< Host port interrupt mask                            */
-#define USB_OTG_GINTMSK_HCIM                    0x02000000U            /*!< Host channels interrupt mask                        */
-#define USB_OTG_GINTMSK_PTXFEM                  0x04000000U            /*!< Periodic TxFIFO empty mask                          */
-#define USB_OTG_GINTMSK_LPMINTM                 0x08000000U            /*!< LPM interrupt Mask                                  */
-#define USB_OTG_GINTMSK_CIDSCHGM                0x10000000U            /*!< Connector ID status change mask                     */
-#define USB_OTG_GINTMSK_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt mask                  */
-#define USB_OTG_GINTMSK_SRQIM                   0x40000000U            /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM                    0x80000000U            /*!< Resume/remote wakeup detected interrupt mask        */
-
-/********************  Bit definition forUSB_OTG_DAINT register  ********************/
-#define USB_OTG_DAINT_IEPINT                  0x0000FFFFU            /*!< IN endpoint interrupt bits  */
-#define USB_OTG_DAINT_OEPINT                  0xFFFF0000U            /*!< OUT endpoint interrupt bits */
-
-/********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/
-#define USB_OTG_HAINTMSK_HAINTM                  0x0000FFFFU            /*!< Channel interrupt mask */
-
-/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
-#define USB_OTG_GRXSTSP_EPNUM                    0x0000000FU            /*!< IN EP interrupt mask bits  */
-#define USB_OTG_GRXSTSP_BCNT                     0x00007FF0U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID                     0x00018000U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS                   0x001E0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/
-#define USB_OTG_DAINTMSK_IEPM                    0x0000FFFFU            /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM                    0xFFFF0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for OTG register  ********************/
-
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition for OTG register  ********************/
-
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/
-#define USB_OTG_GRXFSIZ_RXFD            0x0000FFFFU            /*!< RxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/
-#define USB_OTG_DVBUSDIS_VBUSDT         0x0000FFFFU            /*!< Device VBUS discharge time */
-
-/********************  Bit definition for OTG register  ********************/
-#define USB_OTG_NPTXFSA                 0x0000FFFFU            /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD                  0xFFFF0000U            /*!< Nonperiodic TxFIFO depth               */
-#define USB_OTG_TX0FSA                  0x0000FFFFU            /*!< Endpoint 0 transmit RAM start address  */
-#define USB_OTG_TX0FD                   0xFFFF0000U            /*!< Endpoint 0 TxFIFO depth                */
-
-/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
-#define USB_OTG_DVBUSPULSE_DVBUSP                  0x00000FFFU            /*!< Device VBUS pulsing time */
-
-/********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/
-#define USB_OTG_GNPTXSTS_NPTXFSAV                0x0000FFFFU            /*!< Nonperiodic TxFIFO space available */
-
-#define USB_OTG_GNPTXSTS_NPTQXSAV                0x00FF0000U            /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0              0x00010000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1              0x00020000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2              0x00040000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3              0x00080000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4              0x00100000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5              0x00200000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6              0x00400000U            /*!<Bit 6 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7              0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_GNPTXSTS_NPTXQTOP                0x7F000000U            /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0              0x01000000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1              0x02000000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2              0x04000000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3              0x08000000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4              0x10000000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5              0x20000000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6              0x40000000U            /*!<Bit 6 */
-
-/********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/
-#define USB_OTG_DTHRCTL_NONISOTHREN             0x00000001U            /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN                0x00000002U            /*!< ISO IN endpoint threshold enable */
-
-#define USB_OTG_DTHRCTL_TXTHRLEN                0x000007FCU            /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0              0x00000004U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1              0x00000008U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2              0x00000010U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3              0x00000020U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4              0x00000040U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5              0x00000080U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6              0x00000100U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7              0x00000200U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8              0x00000400U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_RXTHREN                 0x00010000U            /*!< Receive threshold enable */
-
-#define USB_OTG_DTHRCTL_RXTHRLEN                0x03FE0000U            /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0              0x00020000U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1              0x00040000U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2              0x00080000U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3              0x00100000U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4              0x00200000U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5              0x00400000U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6              0x00800000U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7              0x01000000U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8              0x02000000U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_ARPEN                   0x08000000U            /*!< Arbiter parking enable */
-
-/********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM               0x0000FFFFU         /*!< IN EP Tx FIFO empty interrupt mask bits */
-
-/********************  Bit definition forUSB_OTG_DEACHINT register  ********************/
-#define USB_OTG_DEACHINT_IEP1INT                 0x00000002U           /*!< IN endpoint 1interrupt bit   */
-#define USB_OTG_DEACHINT_OEP1INT                 0x00020000U           /*!< OUT endpoint 1 interrupt bit */
-
-/********************  Bit definition forUSB_OTG_GCCFG register  ********************/
-#define USB_OTG_GCCFG_PWRDWN                 0x00010000U              /*!< Power down */
-#define USB_OTG_GCCFG_VBDEN                  0x00200000U              /*!< USB VBUS Detection Enable */
-
-/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
-#define USB_OTG_DEACHINTMSK_IEP1INTM          0x00000002U            /*!< IN Endpoint 1 interrupt mask bit  */
-#define USB_OTG_DEACHINTMSK_OEP1INTM          0x00020000U            /*!< OUT Endpoint 1 interrupt mask bit */
- 
-/********************  Bit definition forUSB_OTG_CID register  ********************/
-#define USB_OTG_CID_PRODUCT_ID               0xFFFFFFFFU            /*!< Product ID field */
-
-/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/
-#define  USB_OTG_GLPMCFG_LPMEN               0x00000001U            /*!< LPM support enable                                     */
-#define  USB_OTG_GLPMCFG_LPMACK              0x00000002U            /*!< LPM Token acknowledge enable                           */
-#define  USB_OTG_GLPMCFG_BESL                0x0000003CU            /*!< BESL value received with last ACKed LPM Token          */
-#define  USB_OTG_GLPMCFG_REMWAKE             0x00000040U            /*!< bRemoteWake value received with last ACKed LPM Token   */
-#define  USB_OTG_GLPMCFG_L1SSEN              0x00000080U            /*!< L1 shallow sleep enable                                */
-#define  USB_OTG_GLPMCFG_BESLTHRS            0x00000F00U            /*!< BESL threshold                                         */
-#define  USB_OTG_GLPMCFG_L1DSEN              0x00001000U            /*!< L1 deep sleep enable                                   */
-#define  USB_OTG_GLPMCFG_LPMRSP              0x00006000U            /*!< LPM response                                           */
-#define  USB_OTG_GLPMCFG_SLPSTS              0x00008000U            /*!< Port sleep status                                      */
-#define  USB_OTG_GLPMCFG_L1RSMOK             0x00010000U            /*!< Sleep State Resume OK                                  */
-#define  USB_OTG_GLPMCFG_LPMCHIDX            0x001E0000U            /*!< LPM Channel Index                                      */
-#define  USB_OTG_GLPMCFG_LPMRCNT             0x00E00000U            /*!< LPM retry count                                        */
-#define  USB_OTG_GLPMCFG_SNDLPM              0x01000000U            /*!< Send LPM transaction                                   */
-#define  USB_OTG_GLPMCFG_LPMRCNTSTS          0x0E000000U            /*!< LPM retry count status                                 */
-#define  USB_OTG_GLPMCFG_ENBESL              0x10000000U            /*!< Enable best effort service latency                     */
-
-/********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/
-#define USB_OTG_DIEPEACHMSK1_XFRCM           0x00000001U            /*!< Transfer completed interrupt mask                 */
-#define USB_OTG_DIEPEACHMSK1_EPDM            0x00000002U            /*!< Endpoint disabled interrupt mask                  */
-#define USB_OTG_DIEPEACHMSK1_TOM             0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK       0x00000010U            /*!< IN token received when TxFIFO empty mask          */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM         0x00000020U            /*!< IN token received with EP mismatch mask           */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM         0x00000040U            /*!< IN endpoint NAK effective mask                    */
-#define USB_OTG_DIEPEACHMSK1_TXFURM          0x00000100U            /*!< FIFO underrun mask                                */
-#define USB_OTG_DIEPEACHMSK1_BIM             0x00000200U            /*!< BNA interrupt mask                                */
-#define USB_OTG_DIEPEACHMSK1_NAKM            0x00002000U            /*!< NAK interrupt mask                                */
-
-/********************  Bit definition forUSB_OTG_HPRT register  ********************/
-#define USB_OTG_HPRT_PCSTS                   0x00000001U            /*!< Port connect status        */
-#define USB_OTG_HPRT_PCDET                   0x00000002U            /*!< Port connect detected      */
-#define USB_OTG_HPRT_PENA                    0x00000004U            /*!< Port enable                */
-#define USB_OTG_HPRT_PENCHNG                 0x00000008U            /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA                    0x00000010U            /*!< Port overcurrent active    */
-#define USB_OTG_HPRT_POCCHNG                 0x00000020U            /*!< Port overcurrent change    */
-#define USB_OTG_HPRT_PRES                    0x00000040U            /*!< Port resume                */
-#define USB_OTG_HPRT_PSUSP                   0x00000080U            /*!< Port suspend               */
-#define USB_OTG_HPRT_PRST                    0x00000100U            /*!< Port reset                 */
-
-#define USB_OTG_HPRT_PLSTS                   0x00000C00U            /*!< Port line status           */
-#define USB_OTG_HPRT_PLSTS_0                 0x00000400U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PLSTS_1                 0x00000800U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PPWR                    0x00001000U            /*!< Port power                 */
-
-#define USB_OTG_HPRT_PTCTL                   0x0001E000U            /*!< Port test control          */
-#define USB_OTG_HPRT_PTCTL_0                 0x00002000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PTCTL_1                 0x00004000U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PTCTL_2                 0x00008000U            /*!<Bit 2 */
-#define USB_OTG_HPRT_PTCTL_3                 0x00010000U            /*!<Bit 3 */
-
-#define USB_OTG_HPRT_PSPD                    0x00060000U            /*!< Port speed                 */
-#define USB_OTG_HPRT_PSPD_0                  0x00020000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PSPD_1                  0x00040000U            /*!<Bit 1 */
-
-/********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/
-#define USB_OTG_DOEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask         */
-#define USB_OTG_DOEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask          */
-#define USB_OTG_DOEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask                    */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask  */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask   */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask            */
-#define USB_OTG_DOEPEACHMSK1_TXFURM                  0x00000100U            /*!< OUT packet error mask                     */
-#define USB_OTG_DOEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask                        */
-#define USB_OTG_DOEPEACHMSK1_BERRM                   0x00001000U            /*!< Bubble error interrupt mask               */
-#define USB_OTG_DOEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask                        */
-#define USB_OTG_DOEPEACHMSK1_NYETM                   0x00004000U            /*!< NYET interrupt mask                       */
-
-/********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/
-#define USB_OTG_HPTXFSIZ_PTXSA                   0x0000FFFFU            /*!< Host periodic TxFIFO start address            */
-#define USB_OTG_HPTXFSIZ_PTXFD                   0xFFFF0000U            /*!< Host periodic TxFIFO depth                    */
-
-/********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/
-#define USB_OTG_DIEPCTL_MPSIZ                   0x000007FFU            /*!< Maximum packet size              */
-#define USB_OTG_DIEPCTL_USBAEP                  0x00008000U            /*!< USB active endpoint              */
-#define USB_OTG_DIEPCTL_EONUM_DPID              0x00010000U            /*!< Even/odd frame                   */
-#define USB_OTG_DIEPCTL_NAKSTS                  0x00020000U            /*!< NAK status                       */
-
-#define USB_OTG_DIEPCTL_EPTYP                   0x000C0000U            /*!< Endpoint type                    */
-#define USB_OTG_DIEPCTL_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_STALL                   0x00200000U            /*!< STALL handshake                  */
-
-#define USB_OTG_DIEPCTL_TXFNUM                  0x03C00000U            /*!< TxFIFO number                    */
-#define USB_OTG_DIEPCTL_TXFNUM_0                0x00400000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                0x00800000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                0x01000000U            /*!<Bit 2 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                0x02000000U            /*!<Bit 3 */
-#define USB_OTG_DIEPCTL_CNAK                    0x04000000U            /*!< Clear NAK                        */
-#define USB_OTG_DIEPCTL_SNAK                    0x08000000U            /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          0x10000000U            /*!< Set DATA0 PID                    */
-#define USB_OTG_DIEPCTL_SODDFRM                 0x20000000U            /*!< Set odd frame                    */
-#define USB_OTG_DIEPCTL_EPDIS                   0x40000000U            /*!< Endpoint disable                 */
-#define USB_OTG_DIEPCTL_EPENA                   0x80000000U            /*!< Endpoint enable                  */
-
-/********************  Bit definition forUSB_OTG_HCCHAR register  ********************/
-#define USB_OTG_HCCHAR_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
-
-#define USB_OTG_HCCHAR_EPNUM                   0x00007800U            /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPNUM_1                 0x00001000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_EPNUM_2                 0x00002000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_EPNUM_3                 0x00004000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_EPDIR                   0x00008000U            /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV                   0x00020000U            /*!< Low-speed device */
-
-#define USB_OTG_HCCHAR_EPTYP                   0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_MC                      0x00300000U            /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                    0x00100000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_MC_1                    0x00200000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_DAD                     0x1FC00000U            /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                   0x00400000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_DAD_1                   0x00800000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_DAD_2                   0x01000000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_DAD_3                   0x02000000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_DAD_4                   0x04000000U            /*!<Bit 4 */
-#define USB_OTG_HCCHAR_DAD_5                   0x08000000U            /*!<Bit 5 */
-#define USB_OTG_HCCHAR_DAD_6                   0x10000000U            /*!<Bit 6 */
-#define USB_OTG_HCCHAR_ODDFRM                  0x20000000U            /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS                   0x40000000U            /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA                   0x80000000U            /*!< Channel enable */
-
-/********************  Bit definition forUSB_OTG_HCSPLT register  ********************/
-
-#define USB_OTG_HCSPLT_PRTADDR                 0x0000007FU            /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_PRTADDR_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_PRTADDR_2               0x00000004U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_PRTADDR_3               0x00000008U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_PRTADDR_4               0x00000010U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_PRTADDR_5               0x00000020U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_PRTADDR_6               0x00000040U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_HUBADDR                 0x00003F80U            /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0               0x00000080U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_HUBADDR_1               0x00000100U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_HUBADDR_2               0x00000200U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_HUBADDR_3               0x00000400U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_HUBADDR_4               0x00000800U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_HUBADDR_5               0x00001000U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_HUBADDR_6               0x00002000U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_XACTPOS                 0x0000C000U            /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0               0x00004000U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_XACTPOS_1               0x00008000U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_COMPLSPLT               0x00010000U            /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN                 0x80000000U            /*!< Split enable */
-
-/********************  Bit definition forUSB_OTG_HCINT register  ********************/
-#define USB_OTG_HCINT_XFRC                    0x00000001U            /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH                     0x00000002U            /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINT_STALL                   0x00000008U            /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK                     0x00000010U            /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK                     0x00000020U            /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET                    0x00000040U            /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR                   0x00000080U            /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR                   0x00000100U            /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR                   0x00000200U            /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR                   0x00000400U            /*!< Data toggle error */
-
-/********************  Bit definition forUSB_OTG_DIEPINT register  ********************/
-#define USB_OTG_DIEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_TOC                     0x00000008U            /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE                  0x00000010U            /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNE                  0x00000040U            /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE                    0x00000080U            /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN              0x00000100U            /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA                     0x00000200U            /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS               0x00000800U            /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR                    0x00001000U            /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK                     0x00002000U            /*!< NAK interrupt */
-
-/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
-#define USB_OTG_HCINTMSK_XFRCM                   0x00000001U            /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM                    0x00000002U            /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM                  0x00000008U            /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM                    0x00000010U            /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM                    0x00000020U            /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET                    0x00000040U            /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM                  0x00000080U            /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM                  0x00000100U            /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM                  0x00000200U            /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM                  0x00000400U            /*!< Data toggle error mask */
-
-/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
-
-#define USB_OTG_DIEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT                  0x60000000U            /*!< Packet count */
-/********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/
-#define USB_OTG_HCTSIZ_XFRSIZ                    0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT                    0x1FF80000U            /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING                    0x80000000U            /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID                      0x60000000U            /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                    0x20000000U            /*!<Bit 0 */
-#define USB_OTG_HCTSIZ_DPID_1                    0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/
-#define USB_OTG_DIEPDMA_DMAADDR                  0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition forUSB_OTG_HCDMA register  ********************/
-#define USB_OTG_HCDMA_DMAADDR                    0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/
-#define USB_OTG_DTXFSTS_INEPTFSAV                0x0000FFFFU            /*!< IN endpoint TxFIFO space available */
-
-/********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/
-#define USB_OTG_DIEPTXF_INEPTXSA                 0x0000FFFFU            /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD                 0xFFFF0000U            /*!< IN endpoint TxFIFO depth */
-
-/********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/
-
-#define USB_OTG_DOEPCTL_MPSIZ                     0x000007FFU            /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP                    0x00008000U            /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS                    0x00020000U            /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            0x10000000U            /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM                   0x20000000U            /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP                     0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                   0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DOEPCTL_EPTYP_1                   0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_SNPM                      0x00100000U            /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL                     0x00200000U            /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK                      0x04000000U            /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK                      0x08000000U            /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS                     0x40000000U            /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA                     0x80000000U            /*!< Endpoint enable */
-
-/********************  Bit definition forUSB_OTG_DOEPINT register  ********************/
-#define USB_OTG_DOEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_STUP                    0x00000008U            /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS                 0x00000010U            /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_OTEPSPR                 0x00000020U            /*!< Status Phase Received For Control Write */
-#define USB_OTG_DOEPINT_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_NYET                    0x00004000U            /*!< NYET interrupt */
-
-/********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/
-
-#define USB_OTG_DOEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-
-#define USB_OTG_DOEPTSIZ_STUPCNT                 0x60000000U            /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0               0x20000000U            /*!<Bit 0 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1               0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition for PCGCCTL register  ********************/
-#define USB_OTG_PCGCCTL_STOPCLK                 0x00000001U            /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK                 0x00000002U            /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP                 0x00000010U            /*!<Bit 1 */
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
-                                       ((INSTANCE) == ADC2) || \
-                                       ((INSTANCE) == ADC3))
-
-/******************************* CAN Instances ********************************/
-#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
-                                       ((INSTANCE) == CAN2))
- 
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DAC Instances ********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/******************************* DCMI Instances *******************************/
-#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
-
-/******************************* DMA2D Instances *******************************/
-#define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
-
-/******************************** DMA Instances *******************************/
-#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
-                                              ((INSTANCE) == DMA1_Stream1) || \
-                                              ((INSTANCE) == DMA1_Stream2) || \
-                                              ((INSTANCE) == DMA1_Stream3) || \
-                                              ((INSTANCE) == DMA1_Stream4) || \
-                                              ((INSTANCE) == DMA1_Stream5) || \
-                                              ((INSTANCE) == DMA1_Stream6) || \
-                                              ((INSTANCE) == DMA1_Stream7) || \
-                                              ((INSTANCE) == DMA2_Stream0) || \
-                                              ((INSTANCE) == DMA2_Stream1) || \
-                                              ((INSTANCE) == DMA2_Stream2) || \
-                                              ((INSTANCE) == DMA2_Stream3) || \
-                                              ((INSTANCE) == DMA2_Stream4) || \
-                                              ((INSTANCE) == DMA2_Stream5) || \
-                                              ((INSTANCE) == DMA2_Stream6) || \
-                                              ((INSTANCE) == DMA2_Stream7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOF) || \
-                                        ((INSTANCE) == GPIOG) || \
-                                        ((INSTANCE) == GPIOH) || \
-                                        ((INSTANCE) == GPIOI) || \
-                                        ((INSTANCE) == GPIOJ) || \
-                                        ((INSTANCE) == GPIOK))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2) || \
-                                       ((INSTANCE) == I2C3))
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI2) || \
-                                    ((INSTANCE) == SPI3))
-
-/*************************** I2S Extended Instances ***************************/
-#define IS_I2S_ALL_INSTANCE_EXT(PERIPH)  (((INSTANCE) == SPI2)    || \
-                                      ((INSTANCE) == SPI3)    || \
-                                      ((INSTANCE) == I2S2ext) || \
-                                      ((INSTANCE) == I2S3ext))
-
-/****************************** LTDC Instances ********************************/
-#define IS_LTDC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == LTDC)
-
-/******************************* RNG Instances ********************************/
-#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************* SAI Instances ********************************/
-#define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
-                                     ((PERIPH) == SAI1_Block_B))
-/* Legacy define */
-#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3) || \
-                                       ((INSTANCE) == SPI4) || \
-                                       ((INSTANCE) == SPI5) || \
-                                       ((INSTANCE) == SPI6))
-
-/*************************** SPI Extended Instances ***************************/
-#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1)    || \
-                                           ((INSTANCE) == SPI2)    || \
-                                           ((INSTANCE) == SPI3)    || \
-                                           ((INSTANCE) == SPI4)    || \
-                                           ((INSTANCE) == SPI5)    || \
-                                           ((INSTANCE) == SPI6)    || \
-                                           ((INSTANCE) == I2S2ext) || \
-                                           ((INSTANCE) == I2S3ext))
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
-                                   ((INSTANCE) == TIM2)   || \
-                                   ((INSTANCE) == TIM3)   || \
-                                   ((INSTANCE) == TIM4)   || \
-                                   ((INSTANCE) == TIM5)   || \
-                                   ((INSTANCE) == TIM6)   || \
-                                   ((INSTANCE) == TIM7)   || \
-                                   ((INSTANCE) == TIM8)   || \
-                                   ((INSTANCE) == TIM9)   || \
-                                   ((INSTANCE) == TIM10)  || \
-                                   ((INSTANCE) == TIM11)  || \
-                                   ((INSTANCE) == TIM12)  || \
-                                   ((INSTANCE) == TIM13)  || \
-                                   ((INSTANCE) == TIM14))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
-                                         ((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM8)  || \
-                                         ((INSTANCE) == TIM9)  || \
-                                         ((INSTANCE) == TIM10) || \
-                                         ((INSTANCE) == TIM11) || \
-                                         ((INSTANCE) == TIM12) || \
-                                         ((INSTANCE) == TIM13) || \
-                                         ((INSTANCE) == TIM14))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM8) || \
-                                       ((INSTANCE) == TIM9) || \
-                                       ((INSTANCE) == TIM12))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8))
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM8))
-
-/******************** TIM Instances : Advanced-control timers *****************/
-#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                            ((INSTANCE) == TIM8))
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8))
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM6) || \
-                                       ((INSTANCE) == TIM7) || \
-                                       ((INSTANCE) == TIM8))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM8))
-
-/************ TIM Instances : DMA requests generation (COMDE) *****************/
-#define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM8)) 
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                             ((INSTANCE) == TIM2) || \
-                                             ((INSTANCE) == TIM3) || \
-                                             ((INSTANCE) == TIM4) || \
-                                             ((INSTANCE) == TIM5) || \
-                                             ((INSTANCE) == TIM8))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM6) || \
-                                          ((INSTANCE) == TIM7) || \
-                                          ((INSTANCE) == TIM8) || \
-                                          ((INSTANCE) == TIM9) || \
-                                          ((INSTANCE) == TIM12))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8) || \
-                                         ((INSTANCE) == TIM9) || \
-                                         ((INSTANCE) == TIM12))
-
-/********************** TIM Instances : 32 bit Counter ************************/
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
-                                              ((INSTANCE) == TIM5))
-
-/***************** TIM Instances : external trigger input availabe ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                        ((INSTANCE) == TIM2) || \
-                                        ((INSTANCE) == TIM3) || \
-                                        ((INSTANCE) == TIM4) || \
-                                        ((INSTANCE) == TIM5) || \
-                                        ((INSTANCE) == TIM8))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM11))
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM1) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM5) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM8) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM12) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM13) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM14) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-/************ TIM Instances : complementary output(s) available ***************/
-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
-   ((((INSTANCE) == TIM1) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3)))            \
-    ||                                          \
-    (((INSTANCE) == TIM8) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3))))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3) || \
-                                     ((INSTANCE) == USART6))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5)  || \
-                                    ((INSTANCE) == USART6) || \
-                                    ((INSTANCE) == UART7)  || \
-                                    ((INSTANCE) == UART8))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3) || \
-                                           ((INSTANCE) == USART6))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3) || \
-                                         ((INSTANCE) == USART6))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5)  || \
-                                    ((INSTANCE) == USART6) || \
-                                    ((INSTANCE) == UART7)  || \
-                                    ((INSTANCE) == UART8))
-    
-/*********************** PCD Instances ****************************************/
-#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
-                                        ((INSTANCE) == USB_OTG_HS))
-
-/*********************** HCD Instances ****************************************/
-#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
-                                       ((INSTANCE) == USB_OTG_HS))
-
-/****************************** SDIO Instances ********************************/
-#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/****************************** QSPI Instances ********************************/
-#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
-
-/****************************** USB Exported Constants ************************/
-#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                12U
-#define USB_OTG_FS_MAX_IN_ENDPOINTS                    6U    /* Including EP0 */
-#define USB_OTG_FS_MAX_OUT_ENDPOINTS                   6U    /* Including EP0 */
-#define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */
-
-#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR                16U
-#define USB_OTG_HS_MAX_IN_ENDPOINTS                    8U    /* Including EP0 */
-#define USB_OTG_HS_MAX_OUT_ENDPOINTS                   8U    /* Including EP0 */
-#define USB_OTG_HS_TOTAL_FIFO_SIZE                     4096U /* in Bytes */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32F479xx_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/cmsis/stm32f4xx.h b/stmhal/cmsis/stm32f4xx.h
deleted file mode 100644
index 23812d4986..0000000000
--- a/stmhal/cmsis/stm32f4xx.h
+++ /dev/null
@@ -1,264 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx.h
-  * @author  MCD Application Team
-  * @version V2.5.1
-  * @date    28-June-2016
-  * @brief   CMSIS STM32F4xx Device Peripheral Access Layer Header File.
-  *            
-  *          The file is the unique include file that the application programmer
-  *          is using in the C source code, usually in main.c. This file contains:
-  *           - Configuration section that allows to select:
-  *              - The STM32F4xx device used in the target application
-  *              - To use or not the peripheral’s drivers in application code(i.e. 
-  *                code will be based on direct access to peripheral’s registers 
-  *                rather than drivers API), this option is controlled by 
-  *                "#define USE_HAL_DRIVER"
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f4xx
-  * @{
-  */
-    
-#ifndef __STM32F4xx_H
-#define __STM32F4xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-   
-/** @addtogroup Library_configuration_section
-  * @{
-  */
-  
-/**
-  * @brief STM32 Family
-  */
-#if !defined  (STM32F4)
-#define STM32F4
-#endif /* STM32F4 */
-
-/* Uncomment the line below according to the target STM32 device used in your
-   application 
-  */
-#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
-    !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
-    !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
-    !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
-    !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
-    !defined (STM32F412Zx)
-  /* #define STM32F405xx */   /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
-  /* #define STM32F415xx */   /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
-  /* #define STM32F407xx */   /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG  and STM32F407IE Devices */
-  /* #define STM32F417xx */   /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
-  /* #define STM32F427xx */   /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */
-  /* #define STM32F437xx */   /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */
-  /* #define STM32F429xx */   /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG, 
-                                   STM32F439NI, STM32F429IG  and STM32F429II Devices */
-  /* #define STM32F439xx */   /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, 
-                                   STM32F439NI, STM32F439IG and STM32F439II Devices */
-  /* #define STM32F401xC */   /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
-  /* #define STM32F401xE */   /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
-  /* #define STM32F410Tx */   /*!< STM32F410T8 and STM32F410TB Devices */
-  /* #define STM32F410Cx */   /*!< STM32F410C8 and STM32F410CB Devices */
-  /* #define STM32F410Rx */   /*!< STM32F410R8 and STM32F410RB Devices */
-  /* #define STM32F411xE */   /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */
-  /* #define STM32F446xx */   /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC, 
-                                   and STM32F446ZE Devices */
-  /* #define STM32F469xx */   /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG, 
-                                   STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
-  /* #define STM32F479xx */   /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG 
-                                   and STM32F479NG Devices */
-  /* #define STM32F412Cx */   /*!< STM32F412CEU and STM32F412CGU Devices */
-  /* #define STM32F412Zx */   /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
-  /* #define STM32F412Vx */   /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
-  /* #define STM32F412Rx */   /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
-#endif
-   
-/*  Tip: To avoid modifying this file each time you need to switch between these
-        devices, you can define the device in your toolchain compiler preprocessor.
-  */
-#if !defined  (USE_HAL_DRIVER)
-/**
- * @brief Comment the line below if you will not use the peripherals drivers.
-   In this case, these drivers will not be included and the application code will 
-   be based on direct access to peripherals registers 
-   */
-  /*#define USE_HAL_DRIVER */
-#endif /* USE_HAL_DRIVER */
-
-/**
-  * @brief CMSIS version number V2.5.1
-  */
-#define __STM32F4xx_CMSIS_VERSION_MAIN   (0x02U) /*!< [31:24] main version */
-#define __STM32F4xx_CMSIS_VERSION_SUB1   (0x05U) /*!< [23:16] sub1 version */
-#define __STM32F4xx_CMSIS_VERSION_SUB2   (0x01U) /*!< [15:8]  sub2 version */
-#define __STM32F4xx_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
-#define __STM32F4xx_CMSIS_VERSION        ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
-                                         |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
-                                         |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\
-                                         |(__STM32F4xx_CMSIS_VERSION))
-
-/**
-  * @}
-  */
-
-/** @addtogroup Device_Included
-  * @{
-  */
-
-#if defined(STM32F405xx)
-  #include "stm32f405xx.h"
-#elif defined(STM32F415xx)
-  #include "stm32f415xx.h"
-#elif defined(STM32F407xx)
-  #include "stm32f407xx.h"
-#elif defined(STM32F417xx)
-  #include "stm32f417xx.h"
-#elif defined(STM32F427xx)
-  #include "stm32f427xx.h"
-#elif defined(STM32F437xx)
-  #include "stm32f437xx.h"
-#elif defined(STM32F429xx)
-  #include "stm32f429xx.h"
-#elif defined(STM32F439xx)
-  #include "stm32f439xx.h"
-#elif defined(STM32F401xC)
-  #include "stm32f401xc.h"
-#elif defined(STM32F401xE)
-  #include "stm32f401xe.h"
-#elif defined(STM32F410Tx)
-  #include "stm32f410tx.h"
-#elif defined(STM32F410Cx)
-  #include "stm32f410cx.h"
-#elif defined(STM32F410Rx)
-  #include "stm32f410rx.h"
-#elif defined(STM32F411xE)
-  #include "stm32f411xe.h"
-#elif defined(STM32F446xx)
-  #include "stm32f446xx.h"
-#elif defined(STM32F469xx)
-  #include "stm32f469xx.h"
-#elif defined(STM32F479xx)
-  #include "stm32f479xx.h"
-#elif defined(STM32F412Cx)
-  #include "stm32f412cx.h"
-#elif defined(STM32F412Zx)
-  #include "stm32f412zx.h"
-#elif defined(STM32F412Rx)
-  #include "stm32f412rx.h"
-#elif defined(STM32F412Vx)
-  #include "stm32f412vx.h"
-#else
- #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
-#endif
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_types
-  * @{
-  */ 
-typedef enum 
-{
-  RESET = 0U, 
-  SET = !RESET
-} FlagStatus, ITStatus;
-
-typedef enum 
-{
-  DISABLE = 0U, 
-  ENABLE = !DISABLE
-} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum 
-{
-  ERROR = 0U, 
-  SUCCESS = !ERROR
-} ErrorStatus;
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup Exported_macro
-  * @{
-  */
-#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
-
-#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
-
-#define READ_BIT(REG, BIT)    ((REG) & (BIT))
-
-#define CLEAR_REG(REG)        ((REG) = (0x0))
-
-#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
-
-#define READ_REG(REG)         ((REG))
-
-#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
-
-#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL))) 
-
-
-/**
-  * @}
-  */
-
-#if defined (USE_HAL_DRIVER)
- #include "stm32f4xx_hal.h"
-#endif /* USE_HAL_DRIVER */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32F4xx_H */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/cmsis/stm32f745xx.h b/stmhal/cmsis/stm32f745xx.h
deleted file mode 100644
index 5de4eacb01..0000000000
--- a/stmhal/cmsis/stm32f745xx.h
+++ /dev/null
@@ -1,9263 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f745xx.h
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   CMSIS Cortex-M7 Device Peripheral Access Layer Header File.
-  *
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral's registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS_Device
-  * @{
-  */
-
-/** @addtogroup stm32f745xx
-  * @{
-  */
-
-#ifndef __STM32F745xx_H
-#define __STM32F745xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-
-/**
- * @brief STM32F7xx Interrupt Number Definition, according to the selected device
- *        in @ref Library_configuration_section
- */
-typedef enum
-{
-/******  Cortex-M7 Processor Exceptions Numbers ****************************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M7 Memory Management Interrupt                           */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M7 Bus Fault Interrupt                                   */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M7 Usage Fault Interrupt                                 */
-  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M7 SV Call Interrupt                                    */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M7 Debug Monitor Interrupt                              */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M7 Pend SV Interrupt                                    */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M7 System Tick Interrupt                                */
-/******  STM32 specific Interrupt Numbers **********************************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
-  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
-  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
-  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
-  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
-  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
-  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
-  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
-  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
-  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
-  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
-  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
-  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
-  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
-  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
-  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
-  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
-  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */
-  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
-  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
-  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
-  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
-  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
-  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
-  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
-  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
-  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
-  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
-  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
-  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
-  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
-  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
-  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
-  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
-  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
-  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
-  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
-  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
-  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
-  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
-  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
-  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
-  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
-  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
-  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
-  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
-  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
-  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
-  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
-  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
-  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
-  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
-  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
-  RNG_IRQn                    = 80,     /*!< RNG global interrupt                                              */
-  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
-  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */
-  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */
-  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
-  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */
-  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */
-  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
-  DMA2D_IRQn                  = 90,     /*!< DMA2D global Interrupt                                            */
-  SAI2_IRQn                   = 91,     /*!< SAI2 global Interrupt                                             */
-  QUADSPI_IRQn                = 92,     /*!< Quad SPI global interrupt                                         */
-  LPTIM1_IRQn                 = 93,     /*!< LP TIM1 interrupt                                                 */
-  CEC_IRQn                    = 94,     /*!< HDMI-CEC global Interrupt                                         */
-  I2C4_EV_IRQn                = 95,     /*!< I2C4 Event Interrupt                                              */
-  I2C4_ER_IRQn                = 96,     /*!< I2C4 Error Interrupt                                              */
-  SPDIF_RX_IRQn               = 97,     /*!< SPDIF-RX global Interrupt                                         */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-/**
- * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
- */
-#define __CM7_REV                 0x0001U  /*!< Cortex-M7 revision r0p1                       */
-#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */
-#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */
-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1       /*!< FPU present                                   */
-#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */
-#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */
-#include "core_cm7.h"                     /*!< Cortex-M7 processor and core peripherals      */
-
-
-#include "system_stm32f7xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */
-
-/**
-  * @brief Analog to Digital Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */
-  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
-  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
-  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
-  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
-  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
-  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
-  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
-  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
-  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
-  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
-  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
-  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
-  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
-  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
-  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
-                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
-} ADC_Common_TypeDef;
-
-
-/**
-  * @brief Controller Area Network TxMailBox
-  */
-
-typedef struct
-{
-  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
-  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
-  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
-  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
-} CAN_TxMailBox_TypeDef;
-
-/**
-  * @brief Controller Area Network FIFOMailBox
-  */
-
-typedef struct
-{
-  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
-  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
-  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
-  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
-} CAN_FIFOMailBox_TypeDef;
-
-/**
-  * @brief Controller Area Network FilterRegister
-  */
-
-typedef struct
-{
-  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
-  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
-} CAN_FilterRegister_TypeDef;
-
-/**
-  * @brief Controller Area Network
-  */
-
-typedef struct
-{
-  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
-  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
-  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
-  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
-  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
-  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
-  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
-  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
-  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
-  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
-  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
-  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
-  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
-  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
-  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
-  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
-  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
-  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
-  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
-  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
-  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */
-  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
-} CAN_TypeDef;
-
-/**
-  * @brief HDMI-CEC
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< CEC control register,                                       Address offset:0x00 */
-  __IO uint32_t CFGR;         /*!< CEC configuration register,                                 Address offset:0x04 */
-  __IO uint32_t TXDR;         /*!< CEC Tx data register ,                                      Address offset:0x08 */
-  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,                                       Address offset:0x0C */
-  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register,                          Address offset:0x10 */
-  __IO uint32_t IER;          /*!< CEC interrupt enable register,                              Address offset:0x14 */
-}CEC_TypeDef;
-
-/**
-  * @brief CRC calculation unit
-  */
-
-typedef struct
-{
-  __IO uint32_t  DR;          /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint8_t   IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
-  uint8_t        RESERVED0;   /*!< Reserved, 0x05                                                    */
-  uint16_t       RESERVED1;   /*!< Reserved, 0x06                                                    */
-  __IO uint32_t  CR;          /*!< CRC Control register,                        Address offset: 0x08 */
-  uint32_t       RESERVED2;   /*!< Reserved,                                                    0x0C */
-  __IO uint32_t  INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
-  __IO uint32_t  POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
-} CRC_TypeDef;
-
-/**
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
-  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
-  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
-  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
-  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
-  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
-  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
-  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
-  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
-  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
-  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
-  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
-  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
-} DAC_TypeDef;
-
-
-/**
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
-  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
-  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
-  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/**
-  * @brief DCMI
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
-  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
-  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
-  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
-  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
-  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
-  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
-  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
-  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
-  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
-  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
-} DCMI_TypeDef;
-
-/**
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
-  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
-  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
-  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
-  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
-  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
-} DMA_Stream_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
-  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
-  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
-  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
-} DMA_TypeDef;
-
-/**
-  * @brief DMA2D Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
-  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
-  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
-  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
-  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
-  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
-  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
-  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
-  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
-  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
-  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
-  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
-  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
-  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
-  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
-  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
-  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
-  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
-  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
-  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
-  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
-  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */
-  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */
-} DMA2D_TypeDef;
-
-
-/**
-  * @brief Ethernet MAC
-  */
-
-typedef struct
-{
-  __IO uint32_t MACCR;
-  __IO uint32_t MACFFR;
-  __IO uint32_t MACHTHR;
-  __IO uint32_t MACHTLR;
-  __IO uint32_t MACMIIAR;
-  __IO uint32_t MACMIIDR;
-  __IO uint32_t MACFCR;
-  __IO uint32_t MACVLANTR;             /*    8 */
-  uint32_t      RESERVED0[2];
-  __IO uint32_t MACRWUFFR;             /*   11 */
-  __IO uint32_t MACPMTCSR;
-  uint32_t      RESERVED1[2];
-  __IO uint32_t MACSR;                 /*   15 */
-  __IO uint32_t MACIMR;
-  __IO uint32_t MACA0HR;
-  __IO uint32_t MACA0LR;
-  __IO uint32_t MACA1HR;
-  __IO uint32_t MACA1LR;
-  __IO uint32_t MACA2HR;
-  __IO uint32_t MACA2LR;
-  __IO uint32_t MACA3HR;
-  __IO uint32_t MACA3LR;               /*   24 */
-  uint32_t      RESERVED2[40];
-  __IO uint32_t MMCCR;                 /*   65 */
-  __IO uint32_t MMCRIR;
-  __IO uint32_t MMCTIR;
-  __IO uint32_t MMCRIMR;
-  __IO uint32_t MMCTIMR;               /*   69 */
-  uint32_t      RESERVED3[14];
-  __IO uint32_t MMCTGFSCCR;            /*   84 */
-  __IO uint32_t MMCTGFMSCCR;
-  uint32_t      RESERVED4[5];
-  __IO uint32_t MMCTGFCR;
-  uint32_t      RESERVED5[10];
-  __IO uint32_t MMCRFCECR;
-  __IO uint32_t MMCRFAECR;
-  uint32_t      RESERVED6[10];
-  __IO uint32_t MMCRGUFCR;
-  uint32_t      RESERVED7[334];
-  __IO uint32_t PTPTSCR;
-  __IO uint32_t PTPSSIR;
-  __IO uint32_t PTPTSHR;
-  __IO uint32_t PTPTSLR;
-  __IO uint32_t PTPTSHUR;
-  __IO uint32_t PTPTSLUR;
-  __IO uint32_t PTPTSAR;
-  __IO uint32_t PTPTTHR;
-  __IO uint32_t PTPTTLR;
-  __IO uint32_t RESERVED8;
-  __IO uint32_t PTPTSSR;
-  uint32_t      RESERVED9[565];
-  __IO uint32_t DMABMR;
-  __IO uint32_t DMATPDR;
-  __IO uint32_t DMARPDR;
-  __IO uint32_t DMARDLAR;
-  __IO uint32_t DMATDLAR;
-  __IO uint32_t DMASR;
-  __IO uint32_t DMAOMR;
-  __IO uint32_t DMAIER;
-  __IO uint32_t DMAMFBOCR;
-  __IO uint32_t DMARSWTR;
-  uint32_t      RESERVED10[8];
-  __IO uint32_t DMACHTDR;
-  __IO uint32_t DMACHRDR;
-  __IO uint32_t DMACHTBAR;
-  __IO uint32_t DMACHRBAR;
-} ETH_TypeDef;
-
-/**
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
-  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
-  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
-  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
-  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
-  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/**
-  * @brief FLASH Registers
-  */
-
-typedef struct
-{
-  __IO uint32_t ACR;      /*!< FLASH access control register,     Address offset: 0x00 */
-  __IO uint32_t KEYR;     /*!< FLASH key register,                Address offset: 0x04 */
-  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,         Address offset: 0x08 */
-  __IO uint32_t SR;       /*!< FLASH status register,             Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< FLASH control register,            Address offset: 0x10 */
-  __IO uint32_t OPTCR;    /*!< FLASH option control register ,    Address offset: 0x14 */
-  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1 ,  Address offset: 0x18 */
-} FLASH_TypeDef;
-
-
-
-/**
-  * @brief Flexible Memory Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
-} FMC_Bank1_TypeDef;
-
-/**
-  * @brief Flexible Memory Controller Bank1E
-  */
-
-typedef struct
-{
-  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
-} FMC_Bank1E_TypeDef;
-
-/**
-  * @brief Flexible Memory Controller Bank3
-  */
-
-typedef struct
-{
-  __IO uint32_t PCR;        /*!< NAND Flash control register,                       Address offset: 0x80 */
-  __IO uint32_t SR;         /*!< NAND Flash FIFO status and interrupt register,     Address offset: 0x84 */
-  __IO uint32_t PMEM;       /*!< NAND Flash Common memory space timing register,    Address offset: 0x88 */
-  __IO uint32_t PATT;       /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
-  uint32_t      RESERVED0;  /*!< Reserved, 0x90                                                          */
-  __IO uint32_t ECCR;       /*!< NAND Flash ECC result registers,                   Address offset: 0x94 */
-} FMC_Bank3_TypeDef;
-
-/**
-  * @brief Flexible Memory Controller Bank5_6
-  */
-
-typedef struct
-{
-  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */
-  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */
-  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */
-  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */
-  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */
-} FMC_Bank5_6_TypeDef;
-
-
-/**
-  * @brief General Purpose I/O
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
-  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
-  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
-  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
-  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
-  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
-  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
-  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/**
-  * @brief System configuration controller
-  */
-
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */
-  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
-} SYSCFG_TypeDef;
-
-/**
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
-  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
-} I2C_TypeDef;
-
-/**
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
-} IWDG_TypeDef;
-
-
-
-/**
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;   /*!< PWR power control register 1,        Address offset: 0x00 */
-  __IO uint32_t CSR1;  /*!< PWR power control/status register 2, Address offset: 0x04 */
-  __IO uint32_t CR2;   /*!< PWR power control register 2,        Address offset: 0x08 */
-  __IO uint32_t CSR2;  /*!< PWR power control/status register 2, Address offset: 0x0C */
-} PWR_TypeDef;
-
-
-/**
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
-  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
-  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
-  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
-  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
-  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
-  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
-  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
-  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
-  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
-  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
-  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
-  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
-  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
-  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
-  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
-  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
-  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
-  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
-  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
-  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
-  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
-  __IO uint32_t PLLSAICFGR;    /*!< RCC PLLSAI configuration register,                           Address offset: 0x88 */
-  __IO uint32_t DCKCFGR1;      /*!< RCC Dedicated Clocks configuration register1,                 Address offset: 0x8C */
-  __IO uint32_t DCKCFGR2;      /*!< RCC Dedicated Clocks configuration register 2,               Address offset: 0x90 */
-
-} RCC_TypeDef;
-
-/**
-  * @brief Real-Time Clock
-  */
-
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-       uint32_t reserved;   /*!< Reserved  */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
-  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset: 0x4C */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
-  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
-  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
-  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
-  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
-  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
-  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
-  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
-  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
-  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
-  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
-  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
-  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
-  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
-  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
-  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */
-  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */
-  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */
-  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */
-  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */
-  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */
-  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */
-  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */
-  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */
-  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */
-  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */
-  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */
-} RTC_TypeDef;
-
-
-/**
-  * @brief Serial Audio Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t GCR;      /*!< SAI global configuration register,        Address offset: 0x00 */
-} SAI_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */
-  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */
-  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */
-  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */
-  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
-  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */
-  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */
-  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */
-} SAI_Block_TypeDef;
-
-/**
-  * @brief SPDIF-RX Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t   CR;           /*!< Control register,                   Address offset: 0x00 */
-  __IO uint32_t   IMR;          /*!< Interrupt mask register,            Address offset: 0x04 */
-  __IO uint32_t   SR;           /*!< Status register,                    Address offset: 0x08 */
-  __IO uint32_t   IFCR;         /*!< Interrupt Flag Clear register,      Address offset: 0x0C */
-  __IO uint32_t   DR;           /*!< Data input register,                Address offset: 0x10 */
-  __IO uint32_t   CSR;          /*!< Channel Status register,            Address offset: 0x14 */
-  __IO uint32_t   DIR;          /*!< Debug Information register,         Address offset: 0x18 */
-} SPDIFRX_TypeDef;
-
-/**
-  * @brief SD host Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t POWER;          /*!< SDMMC power control register,    Address offset: 0x00 */
-  __IO uint32_t CLKCR;          /*!< SDMMClock control register,     Address offset: 0x04 */
-  __IO uint32_t ARG;            /*!< SDMMC argument register,         Address offset: 0x08 */
-  __IO uint32_t CMD;            /*!< SDMMC command register,          Address offset: 0x0C */
-  __I uint32_t  RESPCMD;        /*!< SDMMC command response register, Address offset: 0x10 */
-  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,       Address offset: 0x14 */
-  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,       Address offset: 0x18 */
-  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,       Address offset: 0x1C */
-  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,       Address offset: 0x20 */
-  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,       Address offset: 0x24 */
-  __IO uint32_t DLEN;           /*!< SDMMC data length register,      Address offset: 0x28 */
-  __IO uint32_t DCTRL;          /*!< SDMMC data control register,     Address offset: 0x2C */
-  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,     Address offset: 0x30 */
-  __I uint32_t  STA;            /*!< SDMMC status register,           Address offset: 0x34 */
-  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,  Address offset: 0x38 */
-  __IO uint32_t MASK;           /*!< SDMMC mask register,             Address offset: 0x3C */
-  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
-  __I uint32_t  FIFOCNT;        /*!< SDMMC FIFO counter register,     Address offset: 0x48 */
-  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
-  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,        Address offset: 0x80 */
-} SDMMC_TypeDef;
-
-/**
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/**
-  * @brief QUAD Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */
-  __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
-  __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */
-  __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
-  __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
-  __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
-  __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */
-  __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
-  __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */
-  __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
-  __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */
-  __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
-  __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */
-} QUADSPI_TypeDef;
-
-/**
-  * @brief TIM
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
-  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
-  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
-  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
-  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */
-  __IO uint32_t CCR5;        /*!< TIM capture/compare mode register5,       Address offset: 0x58 */
-  __IO uint32_t CCR6;        /*!< TIM capture/compare mode register6,       Address offset: 0x5C */
-
-} TIM_TypeDef;
-
-/**
-  * @brief LPTIMIMER
-  */
-typedef struct
-{
-  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */
-  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */
-  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */
-  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                       Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< LPTIM Control register,                             Address offset: 0x10 */
-  __IO uint32_t CMP;      /*!< LPTIM Compare register,                             Address offset: 0x14 */
-  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
-  __IO uint32_t CNT;      /*!< LPTIM Counter register,                             Address offset: 0x1C */
-} LPTIM_TypeDef;
-
-
-/**
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */
-  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */
-  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
-  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */
-  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
-  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */
-  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
-  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
-  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
-  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
-  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
-} USART_TypeDef;
-
-
-/**
-  * @brief Window WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-
-/**
-  * @brief RNG
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
-  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
-  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
-} RNG_TypeDef;
-
-/**
-  * @}
-  */
-
-/**
-  * @brief USB_OTG_Core_Registers
-  */
-typedef struct
-{
- __IO uint32_t GOTGCTL;               /*!< USB_OTG Control and Status Register          000h */
-  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */
-  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */
-  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */
-  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */
-  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */
-  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */
-  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */
-  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */
-  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */
-  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */
-  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */
-  uint32_t Reserved30[2];             /*!< Reserved                                     030h */
-  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */
-  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */
-  uint32_t  Reserved5[3];             /*!< Reserved                                040h-048h */
-  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */
-  uint32_t  Reserved6;                /*!< Reserved                                     050h */
-  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */
-  __IO uint32_t GPWRDN;               /*!< Power Down Register                          058h */
-  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */
-   __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register       60Ch */
-    uint32_t  Reserved43[39];         /*!< Reserved                                058h-0FFh */
-  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */
-  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */
-} USB_OTG_GlobalTypeDef;
-
-
-/**
-  * @brief USB_OTG_device_Registers
-  */
-typedef struct
-{
-  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */
-  __IO uint32_t DCTL;            /*!< dev Control Register         804h */
-  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */
-  uint32_t Reserved0C;           /*!< Reserved                     80Ch */
-  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */
-  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */
-  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */
-  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */
-  uint32_t  Reserved20;          /*!< Reserved                     820h */
-  uint32_t Reserved9;            /*!< Reserved                     824h */
-  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */
-  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */
-  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */
-  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */
-  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */
-  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */
-  uint32_t Reserved40;           /*!< dedicated EP mask            840h */
-  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */
-  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */
-  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */
-} USB_OTG_DeviceTypeDef;
-
-
-/**
-  * @brief USB_OTG_IN_Endpoint-Specific_Register
-  */
-typedef struct
-{
-  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */
-  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */
-  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */
-  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */
-  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */
-  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */
-  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
-  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
-} USB_OTG_INEndpointTypeDef;
-
-
-/**
-  * @brief USB_OTG_OUT_Endpoint-Specific_Registers
-  */
-typedef struct
-{
-  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */
-  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */
-  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */
-  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */
-  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */
-  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */
-  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
-} USB_OTG_OUTEndpointTypeDef;
-
-
-/**
-  * @brief USB_OTG_Host_Mode_Register_Structures
-  */
-typedef struct
-{
-  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */
-  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */
-  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */
-  uint32_t Reserved40C;           /*!< Reserved                             40Ch */
-  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */
-  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */
-  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */
-} USB_OTG_HostTypeDef;
-
-/**
-  * @brief USB_OTG_Host_Channel_Specific_Registers
-  */
-typedef struct
-{
-  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */
-  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */
-  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */
-  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */
-  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */
-  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */
-  uint32_t Reserved[2];           /*!< Reserved                                      */
-} USB_OTG_HostChannelTypeDef;
-/**
-  * @}
-  */
-
-
-
-
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-#define RAMITCM_BASE           0x00000000U /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM  */
-#define FLASHITCM_BASE         0x00200000U /*!< Base address of : (up to 1 MB) embedded FLASH memory  accessible over ITCM              */
-#define FLASHAXI_BASE          0x08000000U /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI                */
-#define RAMDTCM_BASE           0x20000000U /*!< Base address of : 64KB system data RAM accessible over DTCM                             */
-#define PERIPH_BASE            0x40000000U /*!< Base address of : AHB/ABP Peripherals                                                   */
-#define BKPSRAM_BASE           0x40024000U /*!< Base address of : Backup SRAM(4 KB)                                                     */
-#define QSPI_BASE              0x90000000U /*!< Base address of : QSPI memories  accessible over AXI                                    */
-#define FMC_R_BASE             0xA0000000U /*!< Base address of : FMC Control registers                                                 */
-#define QSPI_R_BASE            0xA0001000U /*!< Base address of : QSPI Control  registers                                               */
-#define SRAM1_BASE             0x20010000U /*!< Base address of : 240KB RAM1 accessible over AXI/AHB                                    */
-#define SRAM2_BASE             0x2004C000U /*!< Base address of : 16KB RAM2 accessible over AXI/AHB                                     */
-#define FLASH_END              0x080FFFFFU /*!< FLASH end address */
-
-/* Legacy define */
-#define FLASH_BASE     FLASHAXI_BASE
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE        PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000U)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)
-#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800U)
-#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00U)
-#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000U)
-#define LPTIM1_BASE           (APB1PERIPH_BASE + 0x2400U)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)
-#define SPDIFRX_BASE          (APB1PERIPH_BASE + 0x4000U)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800U)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00U)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x5000U)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)
-#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)
-#define I2C4_BASE             (APB1PERIPH_BASE + 0x6000U)
-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)
-#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800U)
-#define CEC_BASE              (APB1PERIPH_BASE + 0x6C00U)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)
-#define UART7_BASE            (APB1PERIPH_BASE + 0x7800U)
-#define UART8_BASE            (APB1PERIPH_BASE + 0x7C00U)
-
-/*!< APB2 peripherals */
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000U)
-#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400U)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x1000U)
-#define USART6_BASE           (APB2PERIPH_BASE + 0x1400U)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000U)
-#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100U)
-#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200U)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x2300U)
-#define SDMMC1_BASE           (APB2PERIPH_BASE + 0x2C00U)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)
-#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400U)
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800U)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00U)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000U)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400U)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800U)
-#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000U)
-#define SPI6_BASE             (APB2PERIPH_BASE + 0x5400U)
-#define SAI1_BASE             (APB2PERIPH_BASE + 0x5800U)
-#define SAI2_BASE             (APB2PERIPH_BASE + 0x5C00U)
-#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004U)
-#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024U)
-#define SAI2_Block_A_BASE     (SAI2_BASE + 0x004U)
-#define SAI2_Block_B_BASE     (SAI2_BASE + 0x024U)
-/*!< AHB1 peripherals */
-#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000U)
-#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400U)
-#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800U)
-#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00U)
-#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000U)
-#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400U)
-#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800U)
-#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00U)
-#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000U)
-#define GPIOJ_BASE            (AHB1PERIPH_BASE + 0x2400U)
-#define GPIOK_BASE            (AHB1PERIPH_BASE + 0x2800U)
-#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)
-#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800U)
-#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00U)
-#define UID_BASE              0x1FF0F420U                   /*!< Unique device ID register base address */
-#define FLASHSIZE_BASE        0x1FF0F442U                   /*!< FLASH Size register base address */
-#define PACKAGESIZE_BASE      0x1FFF7BF0U                   /*!< Package size register base address */
-#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000U)
-#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010U)
-#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028U)
-#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040U)
-#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058U)
-#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070U)
-#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088U)
-#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0U)
-#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8U)
-#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400U)
-#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010U)
-#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028U)
-#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040U)
-#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058U)
-#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070U)
-#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088U)
-#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0U)
-#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)
-#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000U)
-#define ETH_MAC_BASE          (ETH_BASE)
-#define ETH_MMC_BASE          (ETH_BASE + 0x0100U)
-#define ETH_PTP_BASE          (ETH_BASE + 0x0700U)
-#define ETH_DMA_BASE          (ETH_BASE + 0x1000U)
-#define DMA2D_BASE            (AHB1PERIPH_BASE + 0xB000U)
-/*!< AHB2 peripherals */
-#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000U)
-#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800U)
-/*!< FMC Bankx registers base address */
-#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000U)
-#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104U)
-#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080U)
-#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140U)
-
-/* Debug MCU registers base address */
-#define DBGMCU_BASE           0xE0042000U
-
-/*!< USB registers base address */
-#define USB_OTG_HS_PERIPH_BASE               0x40040000U
-#define USB_OTG_FS_PERIPH_BASE               0x50000000U
-
-#define USB_OTG_GLOBAL_BASE                  0x000U
-#define USB_OTG_DEVICE_BASE                  0x800U
-#define USB_OTG_IN_ENDPOINT_BASE             0x900U
-#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U
-#define USB_OTG_EP_REG_SIZE                  0x20U
-#define USB_OTG_HOST_BASE                    0x400U
-#define USB_OTG_HOST_PORT_BASE               0x440U
-#define USB_OTG_HOST_CHANNEL_BASE            0x500U
-#define USB_OTG_HOST_CHANNEL_SIZE            0x20U
-#define USB_OTG_PCGCCTL_BASE                 0xE00U
-#define USB_OTG_FIFO_BASE                    0x1000U
-#define USB_OTG_FIFO_SIZE                    0x1000U
-
-/**
-  * @}
-  */
-
-/** @addtogroup Peripheral_declaration
-  * @{
-  */
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
-#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
-#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
-#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define SPDIFRX             ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define UART4               ((USART_TypeDef *) UART4_BASE)
-#define UART5               ((USART_TypeDef *) UART5_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
-#define I2C4                ((I2C_TypeDef *) I2C4_BASE)
-#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
-#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
-#define CEC                 ((CEC_TypeDef *) CEC_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
-#define UART7               ((USART_TypeDef *) UART7_BASE)
-#define UART8               ((USART_TypeDef *) UART8_BASE)
-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
-#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define USART6              ((USART_TypeDef *) USART6_BASE)
-#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
-#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
-#define SDMMC1              ((SDMMC_TypeDef *) SDMMC1_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define SPI4                ((SPI_TypeDef *) SPI4_BASE)
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-#define SPI5                ((SPI_TypeDef *) SPI5_BASE)
-#define SPI6                ((SPI_TypeDef *) SPI6_BASE)
-#define SAI1                ((SAI_TypeDef *) SAI1_BASE)
-#define SAI2                ((SAI_TypeDef *) SAI2_BASE)
-#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
-#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
-#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
-#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
-#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)
-#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
-#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
-#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
-#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
-#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
-#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
-#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
-#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
-#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
-#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
-#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
-#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
-#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
-#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
-#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
-#define ETH                 ((ETH_TypeDef *) ETH_BASE)
-#define DMA2D               ((DMA2D_TypeDef *)DMA2D_BASE)
-#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
-#define RNG                 ((RNG_TypeDef *) RNG_BASE)
-#define FMC_Bank1           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
-#define FMC_Bank1E          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
-#define FMC_Bank3           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
-#define FMC_Bank5_6         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
-#define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
-#define USB_OTG_HS          ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-
-/******************************************************************************/
-/*                         Peripheral Registers_Bits_Definition               */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Analog to Digital Converter                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          0x00000001U        /*!<Analog watchdog flag                                 */
-#define  ADC_SR_EOC                          0x00000002U        /*!<End of conversion                                    */
-#define  ADC_SR_JEOC                         0x00000004U        /*!<Injected channel end of conversion                   */
-#define  ADC_SR_JSTRT                        0x00000008U        /*!<Injected channel Start flag                          */
-#define  ADC_SR_STRT                         0x00000010U        /*!<Regular channel Start flag                           */
-#define  ADC_SR_OVR                          0x00000020U        /*!<Overrun flag                                         */
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC                             */
-#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable                    */
-#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels               */
-#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
-#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion                  */
-#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels               */
-#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels              */
-#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels          */
-#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels           */
-#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution)                           */
-#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
-
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF                                       */
-#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion                                        */
-#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode                                    */
-#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC)                           */
-#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection                                  */
-#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment                                               */
-#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
-#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      ((uint16_t)0xFFFFU)            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      ((uint16_t)0xFFFFU)            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      ((uint16_t)0xFFFFU)            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      ((uint16_t)0xFFFFU)            /*!<Injected data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag               */
-#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion                  */
-#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag        */
-#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag         */
-#define  ADC_CSR_OVR1                        0x00000020U        /*!<ADC1 Overrun flag                       */
-#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag               */
-#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion                  */
-#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag        */
-#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag         */
-#define  ADC_CSR_OVR2                        0x00002000U        /*!<ADC2 Overrun flag                       */
-#define  ADC_CSR_AWD3                        0x00010000U        /*!<ADC3 Analog watchdog flag               */
-#define  ADC_CSR_EOC3                        0x00020000U        /*!<ADC3 End of conversion                  */
-#define  ADC_CSR_JEOC3                       0x00040000U        /*!<ADC3 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT3                      0x00080000U        /*!<ADC3 Injected channel Start flag        */
-#define  ADC_CSR_STRT3                       0x00100000U        /*!<ADC3 Regular channel Start flag         */
-#define  ADC_CSR_OVR3                        0x00200000U        /*!<ADC3 Overrun flag                       */
-
-/* Legacy defines */
-#define  ADC_CSR_DOVR1                       ADC_CSR_OVR1
-#define  ADC_CSR_DOVR2                       ADC_CSR_OVR2
-#define  ADC_CSR_DOVR3                       ADC_CSR_OVR3
-
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
-#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
-#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
-#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */
-#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
-
-/*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                       0x0000FFFFU         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                       0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Controller Area Network                            */
-/*                                                                            */
-/******************************************************************************/
-/*!<CAN control and status registers */
-/*******************  Bit definition for CAN_MCR register  ********************/
-#define  CAN_MCR_INRQ                        0x00000001U        /*!<Initialization Request            */
-#define  CAN_MCR_SLEEP                       0x00000002U        /*!<Sleep Mode Request                */
-#define  CAN_MCR_TXFP                        0x00000004U        /*!<Transmit FIFO Priority            */
-#define  CAN_MCR_RFLM                        0x00000008U        /*!<Receive FIFO Locked Mode          */
-#define  CAN_MCR_NART                        0x00000010U        /*!<No Automatic Retransmission       */
-#define  CAN_MCR_AWUM                        0x00000020U        /*!<Automatic Wakeup Mode             */
-#define  CAN_MCR_ABOM                        0x00000040U        /*!<Automatic Bus-Off Management      */
-#define  CAN_MCR_TTCM                        0x00000080U        /*!<Time Triggered Communication Mode */
-#define  CAN_MCR_RESET                       0x00008000U        /*!<bxCAN software master reset       */
-
-/*******************  Bit definition for CAN_MSR register  ********************/
-#define  CAN_MSR_INAK                        0x00000001U        /*!<Initialization Acknowledge  */
-#define  CAN_MSR_SLAK                        0x00000002U        /*!<Sleep Acknowledge           */
-#define  CAN_MSR_ERRI                        0x00000004U        /*!<Error Interrupt             */
-#define  CAN_MSR_WKUI                        0x00000008U        /*!<Wakeup Interrupt            */
-#define  CAN_MSR_SLAKI                       0x00000010U        /*!<Sleep Acknowledge Interrupt */
-#define  CAN_MSR_TXM                         0x00000100U        /*!<Transmit Mode               */
-#define  CAN_MSR_RXM                         0x00000200U        /*!<Receive Mode                */
-#define  CAN_MSR_SAMP                        0x00000400U        /*!<Last Sample Point           */
-#define  CAN_MSR_RX                          0x00000800U        /*!<CAN Rx Signal               */
-
-/*******************  Bit definition for CAN_TSR register  ********************/
-#define  CAN_TSR_RQCP0                       0x00000001U        /*!<Request Completed Mailbox0      */
-#define  CAN_TSR_TXOK0                       0x00000002U        /*!<Transmission OK of Mailbox0     */
-#define  CAN_TSR_ALST0                       0x00000004U        /*!<Arbitration Lost for Mailbox0   */
-#define  CAN_TSR_TERR0                       0x00000008U        /*!<Transmission Error of Mailbox0  */
-#define  CAN_TSR_ABRQ0                       0x00000080U        /*!<Abort Request for Mailbox0      */
-#define  CAN_TSR_RQCP1                       0x00000100U        /*!<Request Completed Mailbox1      */
-#define  CAN_TSR_TXOK1                       0x00000200U        /*!<Transmission OK of Mailbox1     */
-#define  CAN_TSR_ALST1                       0x00000400U        /*!<Arbitration Lost for Mailbox1   */
-#define  CAN_TSR_TERR1                       0x00000800U        /*!<Transmission Error of Mailbox1  */
-#define  CAN_TSR_ABRQ1                       0x00008000U        /*!<Abort Request for Mailbox 1     */
-#define  CAN_TSR_RQCP2                       0x00010000U        /*!<Request Completed Mailbox2      */
-#define  CAN_TSR_TXOK2                       0x00020000U        /*!<Transmission OK of Mailbox 2    */
-#define  CAN_TSR_ALST2                       0x00040000U        /*!<Arbitration Lost for mailbox 2  */
-#define  CAN_TSR_TERR2                       0x00080000U        /*!<Transmission Error of Mailbox 2 */
-#define  CAN_TSR_ABRQ2                       0x00800000U        /*!<Abort Request for Mailbox 2     */
-#define  CAN_TSR_CODE                        0x03000000U        /*!<Mailbox Code                    */
-
-#define  CAN_TSR_TME                         0x1C000000U        /*!<TME[2:0] bits */
-#define  CAN_TSR_TME0                        0x04000000U        /*!<Transmit Mailbox 0 Empty */
-#define  CAN_TSR_TME1                        0x08000000U        /*!<Transmit Mailbox 1 Empty */
-#define  CAN_TSR_TME2                        0x10000000U        /*!<Transmit Mailbox 2 Empty */
-
-#define  CAN_TSR_LOW                         0xE0000000U        /*!<LOW[2:0] bits */
-#define  CAN_TSR_LOW0                        0x20000000U        /*!<Lowest Priority Flag for Mailbox 0 */
-#define  CAN_TSR_LOW1                        0x40000000U        /*!<Lowest Priority Flag for Mailbox 1 */
-#define  CAN_TSR_LOW2                        0x80000000U        /*!<Lowest Priority Flag for Mailbox 2 */
-
-/*******************  Bit definition for CAN_RF0R register  *******************/
-#define  CAN_RF0R_FMP0                       0x00000003U        /*!<FIFO 0 Message Pending        */
-#define  CAN_RF0R_FULL0                      0x00000008U        /*!<FIFO 0 Full                   */
-#define  CAN_RF0R_FOVR0                      0x00000010U        /*!<FIFO 0 Overrun                */
-#define  CAN_RF0R_RFOM0                      0x00000020U        /*!<Release FIFO 0 Output Mailbox */
-
-/*******************  Bit definition for CAN_RF1R register  *******************/
-#define  CAN_RF1R_FMP1                       0x00000003U        /*!<FIFO 1 Message Pending        */
-#define  CAN_RF1R_FULL1                      0x00000008U        /*!<FIFO 1 Full                   */
-#define  CAN_RF1R_FOVR1                      0x00000010U        /*!<FIFO 1 Overrun                */
-#define  CAN_RF1R_RFOM1                      0x00000020U        /*!<Release FIFO 1 Output Mailbox */
-
-/********************  Bit definition for CAN_IER register  *******************/
-#define  CAN_IER_TMEIE                       0x00000001U        /*!<Transmit Mailbox Empty Interrupt Enable */
-#define  CAN_IER_FMPIE0                      0x00000002U        /*!<FIFO Message Pending Interrupt Enable   */
-#define  CAN_IER_FFIE0                       0x00000004U        /*!<FIFO Full Interrupt Enable              */
-#define  CAN_IER_FOVIE0                      0x00000008U        /*!<FIFO Overrun Interrupt Enable           */
-#define  CAN_IER_FMPIE1                      0x00000010U        /*!<FIFO Message Pending Interrupt Enable   */
-#define  CAN_IER_FFIE1                       0x00000020U        /*!<FIFO Full Interrupt Enable              */
-#define  CAN_IER_FOVIE1                      0x00000040U        /*!<FIFO Overrun Interrupt Enable           */
-#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error Warning Interrupt Enable          */
-#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error Passive Interrupt Enable          */
-#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-Off Interrupt Enable                */
-#define  CAN_IER_LECIE                       0x00000800U        /*!<Last Error Code Interrupt Enable        */
-#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error Interrupt Enable                  */
-#define  CAN_IER_WKUIE                       0x00010000U        /*!<Wakeup Interrupt Enable                 */
-#define  CAN_IER_SLKIE                       0x00020000U        /*!<Sleep Interrupt Enable                  */
-
-/********************  Bit definition for CAN_ESR register  *******************/
-#define  CAN_ESR_EWGF                        0x00000001U        /*!<Error Warning Flag */
-#define  CAN_ESR_EPVF                        0x00000002U        /*!<Error Passive Flag */
-#define  CAN_ESR_BOFF                        0x00000004U        /*!<Bus-Off Flag */
-
-#define  CAN_ESR_LEC                         0x00000070U        /*!<LEC[2:0] bits (Last Error Code) */
-#define  CAN_ESR_LEC_0                       0x00000010U        /*!<Bit 0 */
-#define  CAN_ESR_LEC_1                       0x00000020U        /*!<Bit 1 */
-#define  CAN_ESR_LEC_2                       0x00000040U        /*!<Bit 2 */
-
-#define  CAN_ESR_TEC                         0x00FF0000U        /*!<Least significant byte of the 9-bit Transmit Error Counter */
-#define  CAN_ESR_REC                         0xFF000000U        /*!<Receive Error Counter */
-
-/*******************  Bit definition for CAN_BTR register  ********************/
-#define  CAN_BTR_BRP                         0x000003FFU        /*!<Baud Rate Prescaler           */
-#define  CAN_BTR_TS1                         0x000F0000U        /*!<Time Segment 1                */
-#define  CAN_BTR_TS1_0                       0x00010000U        /*!<Bit 0 */
-#define  CAN_BTR_TS1_1                       0x00020000U        /*!<Bit 1 */
-#define  CAN_BTR_TS1_2                       0x00040000U        /*!<Bit 2 */
-#define  CAN_BTR_TS1_3                       0x00080000U        /*!<Bit 3 */
-#define  CAN_BTR_TS2                         0x00700000U        /*!<Time Segment 2                */
-#define  CAN_BTR_TS2_0                       0x00100000U        /*!<Bit 0 */
-#define  CAN_BTR_TS2_1                       0x00200000U        /*!<Bit 1 */
-#define  CAN_BTR_TS2_2                       0x00400000U        /*!<Bit 2 */
-#define  CAN_BTR_SJW                         0x03000000U        /*!<Resynchronization Jump Width  */
-#define  CAN_BTR_SJW_0                       0x01000000U        /*!<Bit 0 */
-#define  CAN_BTR_SJW_1                       0x02000000U        /*!<Bit 1 */
-#define  CAN_BTR_LBKM                        0x40000000U        /*!<Loop Back Mode (Debug)        */
-#define  CAN_BTR_SILM                        0x80000000U        /*!<Silent Mode                   */
-
-/*!<Mailbox registers */
-/******************  Bit definition for CAN_TI0R register  ********************/
-#define  CAN_TI0R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request                   */
-#define  CAN_TI0R_RTR                        0x00000002U        /*!<Remote Transmission Request                */
-#define  CAN_TI0R_IDE                        0x00000004U        /*!<Identifier Extension                       */
-#define  CAN_TI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier                        */
-#define  CAN_TI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/******************  Bit definition for CAN_TDT0R register  *******************/
-#define  CAN_TDT0R_DLC                       0x0000000FU        /*!<Data Length Code     */
-#define  CAN_TDT0R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp   */
-
-/******************  Bit definition for CAN_TDL0R register  *******************/
-#define  CAN_TDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/******************  Bit definition for CAN_TDH0R register  *******************/
-#define  CAN_TDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI1R register  *******************/
-#define  CAN_TI1R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request                   */
-#define  CAN_TI1R_RTR                        0x00000002U        /*!<Remote Transmission Request                */
-#define  CAN_TI1R_IDE                        0x00000004U        /*!<Identifier Extension                       */
-#define  CAN_TI1R_EXID                       0x001FFFF8U        /*!<Extended Identifier                        */
-#define  CAN_TI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT1R register  ******************/
-#define  CAN_TDT1R_DLC                       0x0000000FU        /*!<Data Length Code     */
-#define  CAN_TDT1R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp   */
-
-/*******************  Bit definition for CAN_TDL1R register  ******************/
-#define  CAN_TDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH1R register  ******************/
-#define  CAN_TDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI2R register  *******************/
-#define  CAN_TI2R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request                   */
-#define  CAN_TI2R_RTR                        0x00000002U        /*!<Remote Transmission Request                */
-#define  CAN_TI2R_IDE                        0x00000004U        /*!<Identifier Extension                       */
-#define  CAN_TI2R_EXID                       0x001FFFF8U        /*!<Extended identifier                        */
-#define  CAN_TI2R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT2R register  ******************/
-#define  CAN_TDT2R_DLC                       0x0000000FU        /*!<Data Length Code      */
-#define  CAN_TDT2R_TGT                       0x00000100U        /*!<Transmit Global Time  */
-#define  CAN_TDT2R_TIME                      0xFFFF0000U        /*!<Message Time Stamp    */
-
-/*******************  Bit definition for CAN_TDL2R register  ******************/
-#define  CAN_TDL2R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL2R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL2R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL2R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH2R register  ******************/
-#define  CAN_TDH2R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH2R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH2R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH2R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI0R register  *******************/
-#define  CAN_RI0R_RTR                        0x00000002U        /*!<Remote Transmission Request                */
-#define  CAN_RI0R_IDE                        0x00000004U        /*!<Identifier Extension                       */
-#define  CAN_RI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier                        */
-#define  CAN_RI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT0R register  ******************/
-#define  CAN_RDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_RDT0R_FMI                       0x0000FF00U        /*!<Filter Match Index */
-#define  CAN_RDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL0R register  ******************/
-#define  CAN_RDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_RDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_RDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_RDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH0R register  ******************/
-#define  CAN_RDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_RDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_RDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_RDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI1R register  *******************/
-#define  CAN_RI1R_RTR                        0x00000002U        /*!<Remote Transmission Request                */
-#define  CAN_RI1R_IDE                        0x00000004U        /*!<Identifier Extension                       */
-#define  CAN_RI1R_EXID                       0x001FFFF8U        /*!<Extended identifier                        */
-#define  CAN_RI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT1R register  ******************/
-#define  CAN_RDT1R_DLC                       0x0000000FU        /*!<Data Length Code   */
-#define  CAN_RDT1R_FMI                       0x0000FF00U        /*!<Filter Match Index */
-#define  CAN_RDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL1R register  ******************/
-#define  CAN_RDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_RDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_RDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_RDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH1R register  ******************/
-#define  CAN_RDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_RDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_RDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_RDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*!<CAN filter registers */
-/*******************  Bit definition for CAN_FMR register  ********************/
-#define  CAN_FMR_FINIT                       ((uint8_t)0x01U)               /*!<Filter Init Mode */
-#define  CAN_FMR_CAN2SB                      0x00003F00U        /*!<CAN2 start bank */
-
-/*******************  Bit definition for CAN_FM1R register  *******************/
-#define  CAN_FM1R_FBM                        0x3FFFU            /*!<Filter Mode */
-#define  CAN_FM1R_FBM0                       0x0001U            /*!<Filter Init Mode bit 0  */
-#define  CAN_FM1R_FBM1                       0x0002U            /*!<Filter Init Mode bit 1  */
-#define  CAN_FM1R_FBM2                       0x0004U            /*!<Filter Init Mode bit 2  */
-#define  CAN_FM1R_FBM3                       0x0008U            /*!<Filter Init Mode bit 3  */
-#define  CAN_FM1R_FBM4                       0x0010U            /*!<Filter Init Mode bit 4  */
-#define  CAN_FM1R_FBM5                       0x0020U            /*!<Filter Init Mode bit 5  */
-#define  CAN_FM1R_FBM6                       0x0040U            /*!<Filter Init Mode bit 6  */
-#define  CAN_FM1R_FBM7                       0x0080U            /*!<Filter Init Mode bit 7  */
-#define  CAN_FM1R_FBM8                       0x0100U            /*!<Filter Init Mode bit 8  */
-#define  CAN_FM1R_FBM9                       0x0200U            /*!<Filter Init Mode bit 9  */
-#define  CAN_FM1R_FBM10                      0x0400U            /*!<Filter Init Mode bit 10 */
-#define  CAN_FM1R_FBM11                      0x0800U            /*!<Filter Init Mode bit 11 */
-#define  CAN_FM1R_FBM12                      0x1000U            /*!<Filter Init Mode bit 12 */
-#define  CAN_FM1R_FBM13                      0x2000U            /*!<Filter Init Mode bit 13 */
-
-/*******************  Bit definition for CAN_FS1R register  *******************/
-#define  CAN_FS1R_FSC                        0x00003FFFU        /*!<Filter Scale Configuration        */
-#define  CAN_FS1R_FSC0                       0x00000001U        /*!<Filter Scale Configuration bit 0  */
-#define  CAN_FS1R_FSC1                       0x00000002U        /*!<Filter Scale Configuration bit 1  */
-#define  CAN_FS1R_FSC2                       0x00000004U        /*!<Filter Scale Configuration bit 2  */
-#define  CAN_FS1R_FSC3                       0x00000008U        /*!<Filter Scale Configuration bit 3  */
-#define  CAN_FS1R_FSC4                       0x00000010U        /*!<Filter Scale Configuration bit 4  */
-#define  CAN_FS1R_FSC5                       0x00000020U        /*!<Filter Scale Configuration bit 5  */
-#define  CAN_FS1R_FSC6                       0x00000040U        /*!<Filter Scale Configuration bit 6  */
-#define  CAN_FS1R_FSC7                       0x00000080U        /*!<Filter Scale Configuration bit 7  */
-#define  CAN_FS1R_FSC8                       0x00000100U        /*!<Filter Scale Configuration bit 8  */
-#define  CAN_FS1R_FSC9                       0x00000200U        /*!<Filter Scale Configuration bit 9  */
-#define  CAN_FS1R_FSC10                      0x00000400U        /*!<Filter Scale Configuration bit 10 */
-#define  CAN_FS1R_FSC11                      0x00000800U        /*!<Filter Scale Configuration bit 11 */
-#define  CAN_FS1R_FSC12                      0x00001000U        /*!<Filter Scale Configuration bit 12 */
-#define  CAN_FS1R_FSC13                      0x00002000U        /*!<Filter Scale Configuration bit 13 */
-
-/******************  Bit definition for CAN_FFA1R register  *******************/
-#define  CAN_FFA1R_FFA                       0x00003FFFU        /*!<Filter FIFO Assignment */
-#define  CAN_FFA1R_FFA0                      0x00000001U        /*!<Filter FIFO Assignment for Filter 0 */
-#define  CAN_FFA1R_FFA1                      0x00000002U        /*!<Filter FIFO Assignment for Filter 1 */
-#define  CAN_FFA1R_FFA2                      0x00000004U        /*!<Filter FIFO Assignment for Filter 2 */
-#define  CAN_FFA1R_FFA3                      0x00000008U        /*!<Filter FIFO Assignment for Filter 3 */
-#define  CAN_FFA1R_FFA4                      0x00000010U        /*!<Filter FIFO Assignment for Filter 4 */
-#define  CAN_FFA1R_FFA5                      0x00000020U        /*!<Filter FIFO Assignment for Filter 5 */
-#define  CAN_FFA1R_FFA6                      0x00000040U        /*!<Filter FIFO Assignment for Filter 6 */
-#define  CAN_FFA1R_FFA7                      0x00000080U        /*!<Filter FIFO Assignment for Filter 7 */
-#define  CAN_FFA1R_FFA8                      0x00000100U        /*!<Filter FIFO Assignment for Filter 8 */
-#define  CAN_FFA1R_FFA9                      0x00000200U        /*!<Filter FIFO Assignment for Filter 9 */
-#define  CAN_FFA1R_FFA10                     0x00000400U        /*!<Filter FIFO Assignment for Filter 10 */
-#define  CAN_FFA1R_FFA11                     0x00000800U        /*!<Filter FIFO Assignment for Filter 11 */
-#define  CAN_FFA1R_FFA12                     0x00001000U        /*!<Filter FIFO Assignment for Filter 12 */
-#define  CAN_FFA1R_FFA13                     0x00002000U        /*!<Filter FIFO Assignment for Filter 13 */
-
-/*******************  Bit definition for CAN_FA1R register  *******************/
-#define  CAN_FA1R_FACT                       0x00003FFFU        /*!<Filter Active    */
-#define  CAN_FA1R_FACT0                      0x00000001U        /*!<Filter 0 Active  */
-#define  CAN_FA1R_FACT1                      0x00000002U        /*!<Filter 1 Active  */
-#define  CAN_FA1R_FACT2                      0x00000004U        /*!<Filter 2 Active  */
-#define  CAN_FA1R_FACT3                      0x00000008U        /*!<Filter 3 Active  */
-#define  CAN_FA1R_FACT4                      0x00000010U        /*!<Filter 4 Active  */
-#define  CAN_FA1R_FACT5                      0x00000020U        /*!<Filter 5 Active  */
-#define  CAN_FA1R_FACT6                      0x00000040U        /*!<Filter 6 Active  */
-#define  CAN_FA1R_FACT7                      0x00000080U        /*!<Filter 7 Active  */
-#define  CAN_FA1R_FACT8                      0x00000100U        /*!<Filter 8 Active  */
-#define  CAN_FA1R_FACT9                      0x00000200U        /*!<Filter 9 Active  */
-#define  CAN_FA1R_FACT10                     0x00000400U        /*!<Filter 10 Active */
-#define  CAN_FA1R_FACT11                     0x00000800U        /*!<Filter 11 Active */
-#define  CAN_FA1R_FACT12                     0x00001000U        /*!<Filter 12 Active */
-#define  CAN_FA1R_FACT13                     0x00002000U        /*!<Filter 13 Active */
-
-/*******************  Bit definition for CAN_F0R1 register  *******************/
-#define  CAN_F0R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F0R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F0R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F0R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F0R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F0R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F0R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F0R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F0R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F0R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F0R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F0R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F0R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F0R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F0R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F0R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F0R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F0R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F0R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F0R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F0R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F0R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F0R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F0R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F0R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F0R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F0R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F0R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F0R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F0R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F0R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F0R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R1 register  *******************/
-#define  CAN_F1R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F1R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F1R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F1R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F1R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F1R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F1R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F1R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F1R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F1R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F1R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F1R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F1R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F1R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F1R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F1R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F1R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F1R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F1R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F1R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F1R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F1R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F1R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F1R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F1R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F1R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F1R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F1R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F1R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F1R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F1R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F1R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R1 register  *******************/
-#define  CAN_F2R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F2R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F2R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F2R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F2R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F2R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F2R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F2R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F2R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F2R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F2R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F2R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F2R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F2R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F2R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F2R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F2R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F2R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F2R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F2R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F2R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F2R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F2R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F2R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F2R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F2R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F2R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F2R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F2R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F2R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F2R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F2R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R1 register  *******************/
-#define  CAN_F3R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F3R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F3R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F3R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F3R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F3R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F3R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F3R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F3R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F3R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F3R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F3R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F3R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F3R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F3R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F3R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F3R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F3R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F3R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F3R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F3R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F3R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F3R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F3R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F3R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F3R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F3R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F3R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F3R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F3R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F3R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F3R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R1 register  *******************/
-#define  CAN_F4R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F4R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F4R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F4R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F4R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F4R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F4R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F4R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F4R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F4R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F4R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F4R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F4R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F4R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F4R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F4R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F4R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F4R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F4R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F4R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F4R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F4R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F4R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F4R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F4R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F4R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F4R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F4R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F4R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F4R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F4R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F4R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R1 register  *******************/
-#define  CAN_F5R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F5R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F5R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F5R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F5R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F5R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F5R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F5R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F5R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F5R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F5R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F5R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F5R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F5R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F5R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F5R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F5R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F5R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F5R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F5R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F5R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F5R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F5R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F5R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F5R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F5R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F5R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F5R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F5R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F5R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F5R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F5R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R1 register  *******************/
-#define  CAN_F6R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F6R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F6R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F6R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F6R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F6R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F6R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F6R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F6R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F6R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F6R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F6R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F6R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F6R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F6R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F6R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F6R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F6R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F6R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F6R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F6R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F6R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F6R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F6R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F6R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F6R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F6R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F6R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F6R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F6R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F6R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F6R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R1 register  *******************/
-#define  CAN_F7R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F7R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F7R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F7R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F7R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F7R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F7R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F7R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F7R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F7R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F7R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F7R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F7R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F7R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F7R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F7R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F7R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F7R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F7R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F7R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F7R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F7R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F7R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F7R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F7R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F7R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F7R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F7R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F7R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F7R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F7R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F7R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R1 register  *******************/
-#define  CAN_F8R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F8R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F8R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F8R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F8R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F8R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F8R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F8R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F8R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F8R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F8R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F8R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F8R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F8R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F8R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F8R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F8R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F8R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F8R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F8R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F8R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F8R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F8R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F8R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F8R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F8R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F8R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F8R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F8R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F8R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F8R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F8R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R1 register  *******************/
-#define  CAN_F9R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F9R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F9R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F9R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F9R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F9R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F9R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F9R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F9R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F9R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F9R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F9R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F9R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F9R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F9R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F9R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F9R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F9R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F9R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F9R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F9R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F9R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F9R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F9R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F9R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F9R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F9R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F9R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F9R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F9R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F9R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F9R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R1 register  ******************/
-#define  CAN_F10R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F10R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F10R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F10R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F10R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F10R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F10R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F10R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F10R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F10R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F10R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F10R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F10R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F10R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F10R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F10R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F10R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F10R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F10R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F10R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F10R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F10R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F10R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F10R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F10R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F10R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F10R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F10R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F10R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F10R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F10R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F10R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R1 register  ******************/
-#define  CAN_F11R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F11R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F11R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F11R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F11R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F11R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F11R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F11R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F11R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F11R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F11R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F11R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F11R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F11R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F11R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F11R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F11R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F11R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F11R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F11R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F11R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F11R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F11R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F11R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F11R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F11R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F11R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F11R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F11R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F11R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F11R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F11R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R1 register  ******************/
-#define  CAN_F12R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F12R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F12R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F12R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F12R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F12R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F12R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F12R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F12R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F12R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F12R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F12R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F12R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F12R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F12R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F12R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F12R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F12R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F12R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F12R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F12R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F12R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F12R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F12R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F12R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F12R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F12R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F12R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F12R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F12R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F12R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F12R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R1 register  ******************/
-#define  CAN_F13R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F13R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F13R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F13R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F13R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F13R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F13R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F13R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F13R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F13R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F13R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F13R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F13R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F13R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F13R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F13R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F13R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F13R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F13R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F13R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F13R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F13R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F13R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F13R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F13R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F13R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F13R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F13R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F13R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F13R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F13R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F13R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F0R2 register  *******************/
-#define  CAN_F0R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F0R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F0R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F0R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F0R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F0R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F0R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F0R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F0R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F0R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F0R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F0R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F0R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F0R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F0R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F0R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F0R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F0R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F0R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F0R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F0R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F0R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F0R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F0R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F0R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F0R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F0R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F0R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F0R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F0R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F0R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F0R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R2 register  *******************/
-#define  CAN_F1R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F1R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F1R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F1R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F1R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F1R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F1R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F1R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F1R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F1R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F1R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F1R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F1R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F1R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F1R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F1R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F1R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F1R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F1R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F1R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F1R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F1R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F1R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F1R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F1R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F1R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F1R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F1R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F1R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F1R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F1R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F1R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R2 register  *******************/
-#define  CAN_F2R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F2R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F2R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F2R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F2R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F2R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F2R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F2R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F2R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F2R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F2R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F2R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F2R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F2R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F2R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F2R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F2R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F2R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F2R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F2R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F2R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F2R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F2R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F2R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F2R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F2R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F2R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F2R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F2R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F2R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F2R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F2R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R2 register  *******************/
-#define  CAN_F3R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F3R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F3R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F3R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F3R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F3R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F3R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F3R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F3R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F3R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F3R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F3R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F3R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F3R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F3R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F3R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F3R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F3R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F3R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F3R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F3R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F3R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F3R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F3R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F3R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F3R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F3R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F3R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F3R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F3R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F3R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F3R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R2 register  *******************/
-#define  CAN_F4R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F4R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F4R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F4R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F4R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F4R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F4R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F4R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F4R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F4R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F4R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F4R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F4R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F4R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F4R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F4R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F4R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F4R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F4R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F4R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F4R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F4R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F4R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F4R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F4R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F4R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F4R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F4R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F4R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F4R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F4R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F4R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R2 register  *******************/
-#define  CAN_F5R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F5R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F5R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F5R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F5R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F5R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F5R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F5R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F5R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F5R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F5R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F5R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F5R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F5R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F5R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F5R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F5R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F5R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F5R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F5R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F5R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F5R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F5R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F5R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F5R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F5R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F5R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F5R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F5R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F5R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F5R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F5R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R2 register  *******************/
-#define  CAN_F6R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F6R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F6R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F6R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F6R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F6R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F6R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F6R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F6R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F6R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F6R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F6R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F6R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F6R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F6R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F6R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F6R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F6R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F6R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F6R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F6R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F6R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F6R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F6R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F6R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F6R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F6R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F6R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F6R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F6R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F6R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F6R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R2 register  *******************/
-#define  CAN_F7R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F7R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F7R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F7R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F7R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F7R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F7R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F7R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F7R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F7R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F7R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F7R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F7R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F7R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F7R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F7R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F7R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F7R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F7R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F7R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F7R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F7R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F7R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F7R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F7R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F7R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F7R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F7R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F7R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F7R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F7R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F7R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R2 register  *******************/
-#define  CAN_F8R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F8R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F8R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F8R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F8R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F8R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F8R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F8R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F8R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F8R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F8R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F8R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F8R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F8R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F8R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F8R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F8R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F8R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F8R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F8R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F8R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F8R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F8R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F8R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F8R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F8R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F8R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F8R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F8R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F8R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F8R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F8R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R2 register  *******************/
-#define  CAN_F9R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F9R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F9R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F9R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F9R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F9R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F9R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F9R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F9R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F9R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F9R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F9R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F9R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F9R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F9R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F9R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F9R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F9R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F9R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F9R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F9R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F9R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F9R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F9R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F9R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F9R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F9R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F9R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F9R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F9R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F9R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F9R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R2 register  ******************/
-#define  CAN_F10R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F10R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F10R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F10R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F10R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F10R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F10R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F10R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F10R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F10R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F10R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F10R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F10R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F10R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F10R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F10R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F10R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F10R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F10R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F10R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F10R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F10R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F10R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F10R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F10R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F10R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F10R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F10R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F10R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F10R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F10R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F10R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R2 register  ******************/
-#define  CAN_F11R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F11R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F11R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F11R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F11R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F11R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F11R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F11R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F11R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F11R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F11R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F11R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F11R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F11R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F11R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F11R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F11R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F11R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F11R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F11R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F11R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F11R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F11R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F11R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F11R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F11R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F11R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F11R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F11R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F11R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F11R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F11R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R2 register  ******************/
-#define  CAN_F12R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F12R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F12R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F12R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F12R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F12R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F12R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F12R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F12R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F12R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F12R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F12R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F12R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F12R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F12R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F12R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F12R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F12R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F12R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F12R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F12R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F12R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F12R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F12R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F12R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F12R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F12R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F12R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F12R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F12R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F12R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F12R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R2 register  ******************/
-#define  CAN_F13R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F13R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F13R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F13R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F13R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F13R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F13R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F13R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F13R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F13R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F13R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F13R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F13R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F13R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F13R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F13R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F13R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F13R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F13R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F13R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F13R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F13R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F13R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F13R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F13R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F13R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F13R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F13R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F13R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F13R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F13R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F13R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 HDMI-CEC (CEC)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CEC_CR register  *********************/
-#define  CEC_CR_CECEN                        0x00000001U       /*!< CEC Enable                         */
-#define  CEC_CR_TXSOM                        0x00000002U       /*!< CEC Tx Start Of Message            */
-#define  CEC_CR_TXEOM                        0x00000004U       /*!< CEC Tx End Of Message              */
-
-/*******************  Bit definition for CEC_CFGR register  *******************/
-#define  CEC_CFGR_SFT                        0x00000007U       /*!< CEC Signal Free Time               */
-#define  CEC_CFGR_RXTOL                      0x00000008U       /*!< CEC Tolerance                      */
-#define  CEC_CFGR_BRESTP                     0x00000010U       /*!< CEC Rx Stop                        */
-#define  CEC_CFGR_BREGEN                     0x00000020U       /*!< CEC Bit Rising Error generation    */
-#define  CEC_CFGR_LBPEGEN                    0x00000040U       /*!< CEC Long Period Error generation   */
-#define  CEC_CFGR_BRDNOGEN                   0x00000080U       /*!< CEC Broadcast no Error generation  */
-#define  CEC_CFGR_SFTOPT                     0x00000100U       /*!< CEC Signal Free Time optional      */
-#define  CEC_CFGR_OAR                        0x7FFF0000U       /*!< CEC Own Address                    */
-#define  CEC_CFGR_LSTN                       0x80000000U       /*!< CEC Listen mode                    */
-
-/*******************  Bit definition for CEC_TXDR register  *******************/
-#define  CEC_TXDR_TXD                        0x000000FFU       /*!< CEC Tx Data                        */
-
-/*******************  Bit definition for CEC_RXDR register  *******************/
-#define  CEC_TXDR_RXD                        0x000000FFU       /*!< CEC Rx Data                        */
-
-/*******************  Bit definition for CEC_ISR register  ********************/
-#define  CEC_ISR_RXBR                        0x00000001U       /*!< CEC Rx-Byte Received                   */
-#define  CEC_ISR_RXEND                       0x00000002U       /*!< CEC End Of Reception                   */
-#define  CEC_ISR_RXOVR                       0x00000004U       /*!< CEC Rx-Overrun                         */
-#define  CEC_ISR_BRE                         0x00000008U       /*!< CEC Rx Bit Rising Error                */
-#define  CEC_ISR_SBPE                        0x00000010U       /*!< CEC Rx Short Bit period Error          */
-#define  CEC_ISR_LBPE                        0x00000020U       /*!< CEC Rx Long Bit period Error           */
-#define  CEC_ISR_RXACKE                      0x00000040U       /*!< CEC Rx Missing Acknowledge             */
-#define  CEC_ISR_ARBLST                      0x00000080U       /*!< CEC Arbitration Lost                   */
-#define  CEC_ISR_TXBR                        0x00000100U       /*!< CEC Tx Byte Request                    */
-#define  CEC_ISR_TXEND                       0x00000200U       /*!< CEC End of Transmission                */
-#define  CEC_ISR_TXUDR                       0x00000400U       /*!< CEC Tx-Buffer Underrun                 */
-#define  CEC_ISR_TXERR                       0x00000800U       /*!< CEC Tx-Error                           */
-#define  CEC_ISR_TXACKE                      0x00001000U       /*!< CEC Tx Missing Acknowledge             */
-
-/*******************  Bit definition for CEC_IER register  ********************/
-#define  CEC_IER_RXBRIE                      0x00000001U       /*!< CEC Rx-Byte Received IT Enable         */
-#define  CEC_IER_RXENDIE                     0x00000002U       /*!< CEC End Of Reception IT Enable         */
-#define  CEC_IER_RXOVRIE                     0x00000004U       /*!< CEC Rx-Overrun IT Enable               */
-#define  CEC_IER_BREIE                       0x00000008U       /*!< CEC Rx Bit Rising Error IT Enable      */
-#define  CEC_IER_SBPEIE                      0x00000010U       /*!< CEC Rx Short Bit period Error IT Enable*/
-#define  CEC_IER_LBPEIE                      0x00000020U       /*!< CEC Rx Long Bit period Error IT Enable */
-#define  CEC_IER_RXACKEIE                    0x00000040U       /*!< CEC Rx Missing Acknowledge IT Enable   */
-#define  CEC_IER_ARBLSTIE                    0x00000080U       /*!< CEC Arbitration Lost IT Enable         */
-#define  CEC_IER_TXBRIE                      0x00000100U       /*!< CEC Tx Byte Request  IT Enable         */
-#define  CEC_IER_TXENDIE                     0x00000200U       /*!< CEC End of Transmission IT Enable      */
-#define  CEC_IER_TXUDRIE                     0x00000400U       /*!< CEC Tx-Buffer Underrun IT Enable       */
-#define  CEC_IER_TXERRIE                     0x00000800U       /*!< CEC Tx-Error IT Enable                 */
-#define  CEC_IER_TXACKEIE                    0x00001000U       /*!< CEC Tx Missing Acknowledge IT Enable   */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRC calculation unit                              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           0xFFFFFFFFU     /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         0x000000FFU     /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        0x00000001U     /*!< RESET the CRC computation unit bit */
-#define  CRC_CR_POLYSIZE                     0x00000018U     /*!< Polynomial size bits               */
-#define  CRC_CR_POLYSIZE_0                   0x00000008U     /*!< Polynomial size bit 0              */
-#define  CRC_CR_POLYSIZE_1                   0x00000010U     /*!< Polynomial size bit 1              */
-#define  CRC_CR_REV_IN                       0x00000060U     /*!< REV_IN Reverse Input Data bits     */
-#define  CRC_CR_REV_IN_0                     0x00000020U     /*!< Bit 0 */
-#define  CRC_CR_REV_IN_1                     0x00000040U     /*!< Bit 1 */
-#define  CRC_CR_REV_OUT                      0x00000080U     /*!< REV_OUT Reverse Output Data bits   */
-
-/*******************  Bit definition for CRC_INIT register  *******************/
-#define  CRC_INIT_INIT                       0xFFFFFFFFU     /*!< Initial CRC value bits         */
-
-/*******************  Bit definition for CRC_POL register  ********************/
-#define  CRC_POL_POL                         0xFFFFFFFFU     /*!< Coefficients of the polynomial */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Digital to Analog Converter                           */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DAC_CR register  ********************/
-#define  DAC_CR_EN1                          0x00000001U        /*!<DAC channel1 enable                         */
-#define  DAC_CR_BOFF1                        0x00000002U        /*!<DAC channel1 output buffer disable          */
-#define  DAC_CR_TEN1                         0x00000004U        /*!<DAC channel1 Trigger enable                 */
-#define  DAC_CR_TSEL1                        0x00000038U        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define  DAC_CR_TSEL1_0                      0x00000008U        /*!<Bit 0 */
-#define  DAC_CR_TSEL1_1                      0x00000010U        /*!<Bit 1 */
-#define  DAC_CR_TSEL1_2                      0x00000020U        /*!<Bit 2 */
-#define  DAC_CR_WAVE1                        0x000000C0U        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enablEU) */
-#define  DAC_CR_WAVE1_0                      0x00000040U        /*!<Bit 0 */
-#define  DAC_CR_WAVE1_1                      0x00000080U        /*!<Bit 1 */
-#define  DAC_CR_MAMP1                        0x00000F00U        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP1_0                      0x00000100U        /*!<Bit 0 */
-#define  DAC_CR_MAMP1_1                      0x00000200U        /*!<Bit 1 */
-#define  DAC_CR_MAMP1_2                      0x00000400U        /*!<Bit 2 */
-#define  DAC_CR_MAMP1_3                      0x00000800U        /*!<Bit 3 */
-#define  DAC_CR_DMAEN1                       0x00001000U        /*!<DAC channel1 DMA enable                     */
-#define  DAC_CR_DMAUDRIE1                    0x00002000U        /*!<DAC channel1 DMA underrun interrupt enable  */
-#define  DAC_CR_EN2                          0x00010000U        /*!<DAC channel2 enable                         */
-#define  DAC_CR_BOFF2                        0x00020000U        /*!<DAC channel2 output buffer disable          */
-#define  DAC_CR_TEN2                         0x00040000U        /*!<DAC channel2 Trigger enable                 */
-#define  DAC_CR_TSEL2                        0x00380000U        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define  DAC_CR_TSEL2_0                      0x00080000U        /*!<Bit 0 */
-#define  DAC_CR_TSEL2_1                      0x00100000U        /*!<Bit 1 */
-#define  DAC_CR_TSEL2_2                      0x00200000U        /*!<Bit 2 */
-#define  DAC_CR_WAVE2                        0x00C00000U        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE2_0                      0x00400000U        /*!<Bit 0 */
-#define  DAC_CR_WAVE2_1                      0x00800000U        /*!<Bit 1 */
-#define  DAC_CR_MAMP2                        0x0F000000U        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP2_0                      0x01000000U        /*!<Bit 0 */
-#define  DAC_CR_MAMP2_1                      0x02000000U        /*!<Bit 1 */
-#define  DAC_CR_MAMP2_2                      0x04000000U        /*!<Bit 2 */
-#define  DAC_CR_MAMP2_3                      0x08000000U        /*!<Bit 3 */
-#define  DAC_CR_DMAEN2                       0x10000000U        /*!<DAC channel2 DMA enable                    */
-#define  DAC_CR_DMAUDRIE2                    0x20000000U        /*!<DAC channel2 DMA underrun interrupt enable */
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define  DAC_SWTRIGR_SWTRIG1                 0x01U               /*!<DAC channel1 software trigger */
-#define  DAC_SWTRIGR_SWTRIG2                 0x02U               /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define  DAC_DHR12R1_DACC1DHR                0x0FFFU            /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define  DAC_DHR12L1_DACC1DHR                0xFFF0U            /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define  DAC_DHR8R1_DACC1DHR                 0xFFU               /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define  DAC_DHR12R2_DACC2DHR                0x0FFFU            /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define  DAC_DHR12L2_DACC2DHR                0xFFF0U            /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define  DAC_DHR8R2_DACC2DHR                 0xFFU               /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define  DAC_DHR12RD_DACC1DHR                0x00000FFFU        /*!<DAC channel1 12-bit Right aligned data */
-#define  DAC_DHR12RD_DACC2DHR                0x0FFF0000U        /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define  DAC_DHR12LD_DACC1DHR                0x0000FFF0U        /*!<DAC channel1 12-bit Left aligned data */
-#define  DAC_DHR12LD_DACC2DHR                0xFFF00000U        /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define  DAC_DHR8RD_DACC1DHR                 0x00FFU            /*!<DAC channel1 8-bit Right aligned data */
-#define  DAC_DHR8RD_DACC2DHR                 0xFF00U            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define  DAC_DOR1_DACC1DOR                   0x0FFFU            /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define  DAC_DOR2_DACC2DOR                   0x0FFFU            /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define  DAC_SR_DMAUDR1                      0x00002000U        /*!<DAC channel1 DMA underrun flag */
-#define  DAC_SR_DMAUDR2                      0x20000000U        /*!<DAC channel2 DMA underrun flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 Debug MCU                                  */
-/*                                                                            */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    DCMI                                    */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DCMI_CR register  ******************/
-#define DCMI_CR_CAPTURE                      0x00000001U
-#define DCMI_CR_CM                           0x00000002U
-#define DCMI_CR_CROP                         0x00000004U
-#define DCMI_CR_JPEG                         0x00000008U
-#define DCMI_CR_ESS                          0x00000010U
-#define DCMI_CR_PCKPOL                       0x00000020U
-#define DCMI_CR_HSPOL                        0x00000040U
-#define DCMI_CR_VSPOL                        0x00000080U
-#define DCMI_CR_FCRC_0                       0x00000100U
-#define DCMI_CR_FCRC_1                       0x00000200U
-#define DCMI_CR_EDM_0                        0x00000400U
-#define DCMI_CR_EDM_1                        0x00000800U
-#define DCMI_CR_CRE                          0x00001000U
-#define DCMI_CR_ENABLE                       0x00004000U
-#define DCMI_CR_BSM                          0x00030000U
-#define DCMI_CR_BSM_0                        0x00010000U
-#define DCMI_CR_BSM_1                        0x00020000U
-#define DCMI_CR_OEBS                         0x00040000U
-#define DCMI_CR_LSM                          0x00080000U
-#define DCMI_CR_OELS                         0x00100000U
-
-/********************  Bits definition for DCMI_SR register  ******************/
-#define DCMI_SR_HSYNC                        0x00000001U
-#define DCMI_SR_VSYNC                        0x00000002U
-#define DCMI_SR_FNE                          0x00000004U
-
-/********************  Bits definition for DCMI_RIS register   ****************/
-#define DCMI_RIS_FRAME_RIS                   0x00000001U
-#define DCMI_RIS_OVR_RIS                     0x00000002U
-#define DCMI_RIS_ERR_RIS                     0x00000004U
-#define DCMI_RIS_VSYNC_RIS                   0x00000008U
-#define DCMI_RIS_LINE_RIS                    0x00000010U
-
-/* Legacy defines */
-#define DCMI_RISR_FRAME_RIS                  DCMI_RIS_FRAME_RIS
-#define DCMI_RISR_OVF_RIS                    DCMI_RIS_OVR_RIS
-#define DCMI_RISR_ERR_RIS                    DCMI_RIS_ERR_RIS
-#define DCMI_RISR_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS
-#define DCMI_RISR_LINE_RIS                   DCMI_RIS_LINE_RIS
-
-/********************  Bits definition for DCMI_IER register  *****************/
-#define DCMI_IER_FRAME_IE                    0x00000001U
-#define DCMI_IER_OVR_IE                      0x00000002U
-#define DCMI_IER_ERR_IE                      0x00000004U
-#define DCMI_IER_VSYNC_IE                    0x00000008U
-#define DCMI_IER_LINE_IE                     0x00000010U
-
-/* Legacy define */
-#define DCMI_IER_OVF_IE                      DCMI_IER_OVR_IE
-
-/********************  Bits definition for DCMI_MIS register  *****************/
-#define DCMI_MIS_FRAME_MIS                   0x00000001U
-#define DCMI_MIS_OVR_MIS                     0x00000002U
-#define DCMI_MIS_ERR_MIS                     0x00000004U
-#define DCMI_MIS_VSYNC_MIS                   0x00000008U
-#define DCMI_MIS_LINE_MIS                    0x00000010U
-
-/* Legacy defines */
-#define DCMI_MISR_FRAME_MIS                  DCMI_MIS_FRAME_MIS
-#define DCMI_MISR_OVF_MIS                    DCMI_MIS_OVR_MIS
-#define DCMI_MISR_ERR_MIS                    DCMI_MIS_ERR_MIS
-#define DCMI_MISR_VSYNC_MIS                  DCMI_MIS_VSYNC_MIS
-#define DCMI_MISR_LINE_MIS                   DCMI_MIS_LINE_MIS
-
-/********************  Bits definition for DCMI_ICR register  *****************/
-#define DCMI_ICR_FRAME_ISC                   0x00000001U
-#define DCMI_ICR_OVR_ISC                     0x00000002U
-#define DCMI_ICR_ERR_ISC                     0x00000004U
-#define DCMI_ICR_VSYNC_ISC                   0x00000008U
-#define DCMI_ICR_LINE_ISC                    0x00000010U
-
-/* Legacy defines */
-#define DCMI_ICR_OVF_ISC                     DCMI_ICR_OVR_ISC
-
-/********************  Bits definition for DCMI_ESCR register  ******************/
-#define DCMI_ESCR_FSC                        0x000000FFU
-#define DCMI_ESCR_LSC                        0x0000FF00U
-#define DCMI_ESCR_LEC                        0x00FF0000U
-#define DCMI_ESCR_FEC                        0xFF000000U
-
-/********************  Bits definition for DCMI_ESUR register  ******************/
-#define DCMI_ESUR_FSU                        0x000000FFU
-#define DCMI_ESUR_LSU                        0x0000FF00U
-#define DCMI_ESUR_LEU                        0x00FF0000U
-#define DCMI_ESUR_FEU                        0xFF000000U
-
-/********************  Bits definition for DCMI_CWSTRT register  ******************/
-#define DCMI_CWSTRT_HOFFCNT                  0x00003FFFU
-#define DCMI_CWSTRT_VST                      0x1FFF0000U
-
-/********************  Bits definition for DCMI_CWSIZE register  ******************/
-#define DCMI_CWSIZE_CAPCNT                   0x00003FFFU
-#define DCMI_CWSIZE_VLINE                    0x3FFF0000U
-
-/********************  Bits definition for DCMI_DR register  ******************/
-#define DCMI_DR_BYTE0                        0x000000FFU
-#define DCMI_DR_BYTE1                        0x0000FF00U
-#define DCMI_DR_BYTE2                        0x00FF0000U
-#define DCMI_DR_BYTE3                        0xFF000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                             DMA Controller                                 */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DMA_SxCR register  *****************/
-#define DMA_SxCR_CHSEL                       0x0E000000U
-#define DMA_SxCR_CHSEL_0                     0x02000000U
-#define DMA_SxCR_CHSEL_1                     0x04000000U
-#define DMA_SxCR_CHSEL_2                     0x08000000U
-#define DMA_SxCR_MBURST                      0x01800000U
-#define DMA_SxCR_MBURST_0                    0x00800000U
-#define DMA_SxCR_MBURST_1                    0x01000000U
-#define DMA_SxCR_PBURST                      0x00600000U
-#define DMA_SxCR_PBURST_0                    0x00200000U
-#define DMA_SxCR_PBURST_1                    0x00400000U
-#define DMA_SxCR_CT                          0x00080000U
-#define DMA_SxCR_DBM                         0x00040000U
-#define DMA_SxCR_PL                          0x00030000U
-#define DMA_SxCR_PL_0                        0x00010000U
-#define DMA_SxCR_PL_1                        0x00020000U
-#define DMA_SxCR_PINCOS                      0x00008000U
-#define DMA_SxCR_MSIZE                       0x00006000U
-#define DMA_SxCR_MSIZE_0                     0x00002000U
-#define DMA_SxCR_MSIZE_1                     0x00004000U
-#define DMA_SxCR_PSIZE                       0x00001800U
-#define DMA_SxCR_PSIZE_0                     0x00000800U
-#define DMA_SxCR_PSIZE_1                     0x00001000U
-#define DMA_SxCR_MINC                        0x00000400U
-#define DMA_SxCR_PINC                        0x00000200U
-#define DMA_SxCR_CIRC                        0x00000100U
-#define DMA_SxCR_DIR                         0x000000C0U
-#define DMA_SxCR_DIR_0                       0x00000040U
-#define DMA_SxCR_DIR_1                       0x00000080U
-#define DMA_SxCR_PFCTRL                      0x00000020U
-#define DMA_SxCR_TCIE                        0x00000010U
-#define DMA_SxCR_HTIE                        0x00000008U
-#define DMA_SxCR_TEIE                        0x00000004U
-#define DMA_SxCR_DMEIE                       0x00000002U
-#define DMA_SxCR_EN                          0x00000001U
-
-/********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            0x0000FFFFU
-#define DMA_SxNDT_0                          0x00000001U
-#define DMA_SxNDT_1                          0x00000002U
-#define DMA_SxNDT_2                          0x00000004U
-#define DMA_SxNDT_3                          0x00000008U
-#define DMA_SxNDT_4                          0x00000010U
-#define DMA_SxNDT_5                          0x00000020U
-#define DMA_SxNDT_6                          0x00000040U
-#define DMA_SxNDT_7                          0x00000080U
-#define DMA_SxNDT_8                          0x00000100U
-#define DMA_SxNDT_9                          0x00000200U
-#define DMA_SxNDT_10                         0x00000400U
-#define DMA_SxNDT_11                         0x00000800U
-#define DMA_SxNDT_12                         0x00001000U
-#define DMA_SxNDT_13                         0x00002000U
-#define DMA_SxNDT_14                         0x00004000U
-#define DMA_SxNDT_15                         0x00008000U
-
-/********************  Bits definition for DMA_SxFCR register  ****************/
-#define DMA_SxFCR_FEIE                       0x00000080U
-#define DMA_SxFCR_FS                         0x00000038U
-#define DMA_SxFCR_FS_0                       0x00000008U
-#define DMA_SxFCR_FS_1                       0x00000010U
-#define DMA_SxFCR_FS_2                       0x00000020U
-#define DMA_SxFCR_DMDIS                      0x00000004U
-#define DMA_SxFCR_FTH                        0x00000003U
-#define DMA_SxFCR_FTH_0                      0x00000001U
-#define DMA_SxFCR_FTH_1                      0x00000002U
-
-/********************  Bits definition for DMA_LISR register  *****************/
-#define DMA_LISR_TCIF3                       0x08000000U
-#define DMA_LISR_HTIF3                       0x04000000U
-#define DMA_LISR_TEIF3                       0x02000000U
-#define DMA_LISR_DMEIF3                      0x01000000U
-#define DMA_LISR_FEIF3                       0x00400000U
-#define DMA_LISR_TCIF2                       0x00200000U
-#define DMA_LISR_HTIF2                       0x00100000U
-#define DMA_LISR_TEIF2                       0x00080000U
-#define DMA_LISR_DMEIF2                      0x00040000U
-#define DMA_LISR_FEIF2                       0x00010000U
-#define DMA_LISR_TCIF1                       0x00000800U
-#define DMA_LISR_HTIF1                       0x00000400U
-#define DMA_LISR_TEIF1                       0x00000200U
-#define DMA_LISR_DMEIF1                      0x00000100U
-#define DMA_LISR_FEIF1                       0x00000040U
-#define DMA_LISR_TCIF0                       0x00000020U
-#define DMA_LISR_HTIF0                       0x00000010U
-#define DMA_LISR_TEIF0                       0x00000008U
-#define DMA_LISR_DMEIF0                      0x00000004U
-#define DMA_LISR_FEIF0                       0x00000001U
-
-/********************  Bits definition for DMA_HISR register  *****************/
-#define DMA_HISR_TCIF7                       0x08000000U
-#define DMA_HISR_HTIF7                       0x04000000U
-#define DMA_HISR_TEIF7                       0x02000000U
-#define DMA_HISR_DMEIF7                      0x01000000U
-#define DMA_HISR_FEIF7                       0x00400000U
-#define DMA_HISR_TCIF6                       0x00200000U
-#define DMA_HISR_HTIF6                       0x00100000U
-#define DMA_HISR_TEIF6                       0x00080000U
-#define DMA_HISR_DMEIF6                      0x00040000U
-#define DMA_HISR_FEIF6                       0x00010000U
-#define DMA_HISR_TCIF5                       0x00000800U
-#define DMA_HISR_HTIF5                       0x00000400U
-#define DMA_HISR_TEIF5                       0x00000200U
-#define DMA_HISR_DMEIF5                      0x00000100U
-#define DMA_HISR_FEIF5                       0x00000040U
-#define DMA_HISR_TCIF4                       0x00000020U
-#define DMA_HISR_HTIF4                       0x00000010U
-#define DMA_HISR_TEIF4                       0x00000008U
-#define DMA_HISR_DMEIF4                      0x00000004U
-#define DMA_HISR_FEIF4                       0x00000001U
-
-/********************  Bits definition for DMA_LIFCR register  ****************/
-#define DMA_LIFCR_CTCIF3                     0x08000000U
-#define DMA_LIFCR_CHTIF3                     0x04000000U
-#define DMA_LIFCR_CTEIF3                     0x02000000U
-#define DMA_LIFCR_CDMEIF3                    0x01000000U
-#define DMA_LIFCR_CFEIF3                     0x00400000U
-#define DMA_LIFCR_CTCIF2                     0x00200000U
-#define DMA_LIFCR_CHTIF2                     0x00100000U
-#define DMA_LIFCR_CTEIF2                     0x00080000U
-#define DMA_LIFCR_CDMEIF2                    0x00040000U
-#define DMA_LIFCR_CFEIF2                     0x00010000U
-#define DMA_LIFCR_CTCIF1                     0x00000800U
-#define DMA_LIFCR_CHTIF1                     0x00000400U
-#define DMA_LIFCR_CTEIF1                     0x00000200U
-#define DMA_LIFCR_CDMEIF1                    0x00000100U
-#define DMA_LIFCR_CFEIF1                     0x00000040U
-#define DMA_LIFCR_CTCIF0                     0x00000020U
-#define DMA_LIFCR_CHTIF0                     0x00000010U
-#define DMA_LIFCR_CTEIF0                     0x00000008U
-#define DMA_LIFCR_CDMEIF0                    0x00000004U
-#define DMA_LIFCR_CFEIF0                     0x00000001U
-
-/********************  Bits definition for DMA_HIFCR  register  ****************/
-#define DMA_HIFCR_CTCIF7                     0x08000000U
-#define DMA_HIFCR_CHTIF7                     0x04000000U
-#define DMA_HIFCR_CTEIF7                     0x02000000U
-#define DMA_HIFCR_CDMEIF7                    0x01000000U
-#define DMA_HIFCR_CFEIF7                     0x00400000U
-#define DMA_HIFCR_CTCIF6                     0x00200000U
-#define DMA_HIFCR_CHTIF6                     0x00100000U
-#define DMA_HIFCR_CTEIF6                     0x00080000U
-#define DMA_HIFCR_CDMEIF6                    0x00040000U
-#define DMA_HIFCR_CFEIF6                     0x00010000U
-#define DMA_HIFCR_CTCIF5                     0x00000800U
-#define DMA_HIFCR_CHTIF5                     0x00000400U
-#define DMA_HIFCR_CTEIF5                     0x00000200U
-#define DMA_HIFCR_CDMEIF5                    0x00000100U
-#define DMA_HIFCR_CFEIF5                     0x00000040U
-#define DMA_HIFCR_CTCIF4                     0x00000020U
-#define DMA_HIFCR_CHTIF4                     0x00000010U
-#define DMA_HIFCR_CTEIF4                     0x00000008U
-#define DMA_HIFCR_CDMEIF4                    0x00000004U
-#define DMA_HIFCR_CFEIF4                     0x00000001U
-
-/******************************************************************************/
-/*                                                                            */
-/*                         AHB Master DMA2D Controller (DMA2D)                */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for DMA2D_CR register  ******************/
-
-#define DMA2D_CR_START                     0x00000001U               /*!< Start transfer                          */
-#define DMA2D_CR_SUSP                      0x00000002U               /*!< Suspend transfer                        */
-#define DMA2D_CR_ABORT                     0x00000004U               /*!< Abort transfer                          */
-#define DMA2D_CR_TEIE                      0x00000100U               /*!< Transfer Error Interrupt Enable         */
-#define DMA2D_CR_TCIE                      0x00000200U               /*!< Transfer Complete Interrupt Enable      */
-#define DMA2D_CR_TWIE                      0x00000400U               /*!< Transfer Watermark Interrupt Enable     */
-#define DMA2D_CR_CAEIE                     0x00000800U               /*!< CLUT Access Error Interrupt Enable      */
-#define DMA2D_CR_CTCIE                     0x00001000U               /*!< CLUT Transfer Complete Interrupt Enable */
-#define DMA2D_CR_CEIE                      0x00002000U               /*!< Configuration Error Interrupt Enable    */
-#define DMA2D_CR_MODE                      0x00030000U               /*!< DMA2D Mode[1:0]                         */
-#define DMA2D_CR_MODE_0                    0x00010000U               /*!< DMA2D Mode bit 0                        */
-#define DMA2D_CR_MODE_1                    0x00020000U               /*!< DMA2D Mode bit 1                        */
-
-/********************  Bit definition for DMA2D_ISR register  *****************/
-
-#define DMA2D_ISR_TEIF                     0x00000001U               /*!< Transfer Error Interrupt Flag         */
-#define DMA2D_ISR_TCIF                     0x00000002U               /*!< Transfer Complete Interrupt Flag      */
-#define DMA2D_ISR_TWIF                     0x00000004U               /*!< Transfer Watermark Interrupt Flag     */
-#define DMA2D_ISR_CAEIF                    0x00000008U               /*!< CLUT Access Error Interrupt Flag      */
-#define DMA2D_ISR_CTCIF                    0x00000010U               /*!< CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_ISR_CEIF                     0x00000020U               /*!< Configuration Error Interrupt Flag    */
-
-/********************  Bit definition for DMA2D_IFCR register  ****************/
-
-#define DMA2D_IFCR_CTEIF                   0x00000001U               /*!< Clears Transfer Error Interrupt Flag         */
-#define DMA2D_IFCR_CTCIF                   0x00000002U               /*!< Clears Transfer Complete Interrupt Flag      */
-#define DMA2D_IFCR_CTWIF                   0x00000004U               /*!< Clears Transfer Watermark Interrupt Flag     */
-#define DMA2D_IFCR_CAECIF                  0x00000008U               /*!< Clears CLUT Access Error Interrupt Flag      */
-#define DMA2D_IFCR_CCTCIF                  0x00000010U               /*!< Clears CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_IFCR_CCEIF                   0x00000020U               /*!< Clears Configuration Error Interrupt Flag    */
-
-/* Legacy defines */
-#define DMA2D_IFSR_CTEIF                   DMA2D_IFCR_CTEIF                     /*!< Clears Transfer Error Interrupt Flag         */
-#define DMA2D_IFSR_CTCIF                   DMA2D_IFCR_CTCIF                     /*!< Clears Transfer Complete Interrupt Flag      */
-#define DMA2D_IFSR_CTWIF                   DMA2D_IFCR_CTWIF                     /*!< Clears Transfer Watermark Interrupt Flag     */
-#define DMA2D_IFSR_CCAEIF                  DMA2D_IFCR_CAECIF                    /*!< Clears CLUT Access Error Interrupt Flag      */
-#define DMA2D_IFSR_CCTCIF                  DMA2D_IFCR_CCTCIF                    /*!< Clears CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_IFSR_CCEIF                   DMA2D_IFCR_CCEIF                     /*!< Clears Configuration Error Interrupt Flag    */
-
-/********************  Bit definition for DMA2D_FGMAR register  ***************/
-
-#define DMA2D_FGMAR_MA                     0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_FGOR register  ****************/
-
-#define DMA2D_FGOR_LO                      0x00003FFFU               /*!< Line Offset */
-
-/********************  Bit definition for DMA2D_BGMAR register  ***************/
-
-#define DMA2D_BGMAR_MA                     0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_BGOR register  ****************/
-
-#define DMA2D_BGOR_LO                      0x00003FFFU               /*!< Line Offset */
-
-/********************  Bit definition for DMA2D_FGPFCCR register  *************/
-
-#define DMA2D_FGPFCCR_CM                   0x0000000FU               /*!< Input color mode CM[3:0] */
-#define DMA2D_FGPFCCR_CM_0                 0x00000001U               /*!< Input color mode CM bit 0 */
-#define DMA2D_FGPFCCR_CM_1                 0x00000002U               /*!< Input color mode CM bit 1 */
-#define DMA2D_FGPFCCR_CM_2                 0x00000004U               /*!< Input color mode CM bit 2 */
-#define DMA2D_FGPFCCR_CM_3                 0x00000008U               /*!< Input color mode CM bit 3 */
-#define DMA2D_FGPFCCR_CCM                  0x00000010U               /*!< CLUT Color mode */
-#define DMA2D_FGPFCCR_START                0x00000020U               /*!< Start */
-#define DMA2D_FGPFCCR_CS                   0x0000FF00U               /*!< CLUT size */
-#define DMA2D_FGPFCCR_AM                   0x00030000U               /*!< Alpha mode AM[1:0] */
-#define DMA2D_FGPFCCR_AM_0                 0x00010000U               /*!< Alpha mode AM bit 0 */
-#define DMA2D_FGPFCCR_AM_1                 0x00020000U               /*!< Alpha mode AM bit 1 */
-#define DMA2D_FGPFCCR_ALPHA                0xFF000000U               /*!< Alpha value */
-
-/********************  Bit definition for DMA2D_FGCOLR register  **************/
-
-#define DMA2D_FGCOLR_BLUE                  0x000000FFU               /*!< Blue Value */
-#define DMA2D_FGCOLR_GREEN                 0x0000FF00U               /*!< Green Value */
-#define DMA2D_FGCOLR_RED                   0x00FF0000U               /*!< Red Value */
-
-/********************  Bit definition for DMA2D_BGPFCCR register  *************/
-
-#define DMA2D_BGPFCCR_CM                   0x0000000FU               /*!< Input color mode CM[3:0] */
-#define DMA2D_BGPFCCR_CM_0                 0x00000001U               /*!< Input color mode CM bit 0 */
-#define DMA2D_BGPFCCR_CM_1                 0x00000002U               /*!< Input color mode CM bit 1 */
-#define DMA2D_BGPFCCR_CM_2                 0x00000004U               /*!< Input color mode CM bit 2 */
-#define DMA2D_FGPFCCR_CM_3                 0x00000008U               /*!< Input color mode CM bit 3 */
-#define DMA2D_BGPFCCR_CCM                  0x00000010U               /*!< CLUT Color mode */
-#define DMA2D_BGPFCCR_START                0x00000020U               /*!< Start */
-#define DMA2D_BGPFCCR_CS                   0x0000FF00U               /*!< CLUT size */
-#define DMA2D_BGPFCCR_AM                   0x00030000U               /*!< Alpha mode AM[1:0] */
-#define DMA2D_BGPFCCR_AM_0                 0x00010000U               /*!< Alpha mode AM bit 0 */
-#define DMA2D_BGPFCCR_AM_1                 0x00020000U               /*!< Alpha mode AM bit 1 */
-#define DMA2D_BGPFCCR_ALPHA                0xFF000000U               /*!< background Input Alpha value */
-
-/********************  Bit definition for DMA2D_BGCOLR register  **************/
-
-#define DMA2D_BGCOLR_BLUE                  0x000000FFU               /*!< Blue Value */
-#define DMA2D_BGCOLR_GREEN                 0x0000FF00U               /*!< Green Value */
-#define DMA2D_BGCOLR_RED                   0x00FF0000U               /*!< Red Value */
-
-/********************  Bit definition for DMA2D_FGCMAR register  **************/
-
-#define DMA2D_FGCMAR_MA                    0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_BGCMAR register  **************/
-
-#define DMA2D_BGCMAR_MA                    0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_OPFCCR register  **************/
-
-#define DMA2D_OPFCCR_CM                    0x00000007U               /*!< Color mode CM[2:0] */
-#define DMA2D_OPFCCR_CM_0                  0x00000001U               /*!< Color mode CM bit 0 */
-#define DMA2D_OPFCCR_CM_1                  0x00000002U               /*!< Color mode CM bit 1 */
-#define DMA2D_OPFCCR_CM_2                  0x00000004U               /*!< Color mode CM bit 2 */
-
-/********************  Bit definition for DMA2D_OCOLR register  ***************/
-
-/*!<Mode_ARGB8888/RGB888 */
-
-#define DMA2D_OCOLR_BLUE_1                 0x000000FFU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_1                0x0000FF00U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_1                  0x00FF0000U               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_1                0xFF000000U               /*!< Alpha Channel Value */
-
-/*!<Mode_RGB565 */
-#define DMA2D_OCOLR_BLUE_2                 0x0000001FU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_2                0x000007E0U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_2                  0x0000F800U               /*!< Red Value */
-
-/*!<Mode_ARGB1555 */
-#define DMA2D_OCOLR_BLUE_3                 0x0000001FU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_3                0x000003E0U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_3                  0x00007C00U               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_3                0x00008000U               /*!< Alpha Channel Value */
-
-/*!<Mode_ARGB4444 */
-#define DMA2D_OCOLR_BLUE_4                 0x0000000FU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_4                0x000000F0U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_4                  0x00000F00U               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_4                0x0000F000U               /*!< Alpha Channel Value */
-
-/********************  Bit definition for DMA2D_OMAR register  ****************/
-
-#define DMA2D_OMAR_MA                      0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_OOR register  *****************/
-
-#define DMA2D_OOR_LO                       0x00003FFFU               /*!< Line Offset */
-
-/********************  Bit definition for DMA2D_NLR register  *****************/
-
-#define DMA2D_NLR_NL                       0x0000FFFFU               /*!< Number of Lines */
-#define DMA2D_NLR_PL                       0x3FFF0000U               /*!< Pixel per Lines */
-
-/********************  Bit definition for DMA2D_LWR register  *****************/
-
-#define DMA2D_LWR_LW                       0x0000FFFFU               /*!< Line Watermark */
-
-/********************  Bit definition for DMA2D_AMTCR register  ***************/
-
-#define DMA2D_AMTCR_EN                     0x00000001U               /*!< Enable */
-#define DMA2D_AMTCR_DT                     0x0000FF00U               /*!< Dead Time */
-
-
-/********************  Bit definition for DMA2D_FGCLUT register  **************/
-
-/********************  Bit definition for DMA2D_BGCLUT register  **************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                    External Interrupt/Event Controller                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
-#define  EXTI_IMR_MR23                       0x00800000U        /*!< Interrupt Mask on line 23 */
-
-/* Reference Defines */
-#define  EXTI_IMR_IM0                        EXTI_IMR_MR0
-#define  EXTI_IMR_IM1                        EXTI_IMR_MR1
-#define  EXTI_IMR_IM2                        EXTI_IMR_MR2
-#define  EXTI_IMR_IM3                        EXTI_IMR_MR3
-#define  EXTI_IMR_IM4                        EXTI_IMR_MR4
-#define  EXTI_IMR_IM5                        EXTI_IMR_MR5
-#define  EXTI_IMR_IM6                        EXTI_IMR_MR6
-#define  EXTI_IMR_IM7                        EXTI_IMR_MR7
-#define  EXTI_IMR_IM8                        EXTI_IMR_MR8
-#define  EXTI_IMR_IM9                        EXTI_IMR_MR9
-#define  EXTI_IMR_IM10                       EXTI_IMR_MR10
-#define  EXTI_IMR_IM11                       EXTI_IMR_MR11
-#define  EXTI_IMR_IM12                       EXTI_IMR_MR12
-#define  EXTI_IMR_IM13                       EXTI_IMR_MR13
-#define  EXTI_IMR_IM14                       EXTI_IMR_MR14
-#define  EXTI_IMR_IM15                       EXTI_IMR_MR15
-#define  EXTI_IMR_IM16                       EXTI_IMR_MR16
-#define  EXTI_IMR_IM17                       EXTI_IMR_MR17
-#define  EXTI_IMR_IM18                       EXTI_IMR_MR18
-#define  EXTI_IMR_IM19                       EXTI_IMR_MR19
-#define  EXTI_IMR_IM20                       EXTI_IMR_MR20
-#define  EXTI_IMR_IM21                       EXTI_IMR_MR21
-#define  EXTI_IMR_IM22                       EXTI_IMR_MR22
-#define  EXTI_IMR_IM23                       EXTI_IMR_MR23
-
-#define  EXTI_IMR_IM                         0x00FFFFFFU        /*!< Interrupt Mask All */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
-#define  EXTI_EMR_MR23                       0x00800000U        /*!< Event Mask on line 23 */
-
-/* Reference Defines */
-#define  EXTI_EMR_EM0                        EXTI_EMR_MR0
-#define  EXTI_EMR_EM1                        EXTI_EMR_MR1
-#define  EXTI_EMR_EM2                        EXTI_EMR_MR2
-#define  EXTI_EMR_EM3                        EXTI_EMR_MR3
-#define  EXTI_EMR_EM4                        EXTI_EMR_MR4
-#define  EXTI_EMR_EM5                        EXTI_EMR_MR5
-#define  EXTI_EMR_EM6                        EXTI_EMR_MR6
-#define  EXTI_EMR_EM7                        EXTI_EMR_MR7
-#define  EXTI_EMR_EM8                        EXTI_EMR_MR8
-#define  EXTI_EMR_EM9                        EXTI_EMR_MR9
-#define  EXTI_EMR_EM10                       EXTI_EMR_MR10
-#define  EXTI_EMR_EM11                       EXTI_EMR_MR11
-#define  EXTI_EMR_EM12                       EXTI_EMR_MR12
-#define  EXTI_EMR_EM13                       EXTI_EMR_MR13
-#define  EXTI_EMR_EM14                       EXTI_EMR_MR14
-#define  EXTI_EMR_EM15                       EXTI_EMR_MR15
-#define  EXTI_EMR_EM16                       EXTI_EMR_MR16
-#define  EXTI_EMR_EM17                       EXTI_EMR_MR17
-#define  EXTI_EMR_EM18                       EXTI_EMR_MR18
-#define  EXTI_EMR_EM19                       EXTI_EMR_MR19
-#define  EXTI_EMR_EM20                       EXTI_EMR_MR20
-#define  EXTI_EMR_EM21                       EXTI_EMR_MR21
-#define  EXTI_EMR_EM22                       EXTI_EMR_MR22
-#define  EXTI_EMR_EM23                       EXTI_EMR_MR23
-
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
-#define  EXTI_RTSR_TR23                      0x00800000U        /*!< Rising trigger event configuration bit of line 23 */
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
-#define  EXTI_FTSR_TR23                      0x00800000U        /*!< Falling trigger event configuration bit of line 23 */
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
-#define  EXTI_SWIER_SWIER23                  0x00800000U        /*!< Software Interrupt on line 23 */
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
-#define  EXTI_PR_PR23                        0x00800000U        /*!< Pending bit for line 23 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    FLASH                                   */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief FLASH Total Sectors Number
-*/
-#define FLASH_SECTOR_TOTAL  8
-
-/*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    0x0000000FU
-#define FLASH_ACR_LATENCY_0WS                0x00000000U
-#define FLASH_ACR_LATENCY_1WS                0x00000001U
-#define FLASH_ACR_LATENCY_2WS                0x00000002U
-#define FLASH_ACR_LATENCY_3WS                0x00000003U
-#define FLASH_ACR_LATENCY_4WS                0x00000004U
-#define FLASH_ACR_LATENCY_5WS                0x00000005U
-#define FLASH_ACR_LATENCY_6WS                0x00000006U
-#define FLASH_ACR_LATENCY_7WS                0x00000007U
-#define FLASH_ACR_LATENCY_8WS                0x00000008U
-#define FLASH_ACR_LATENCY_9WS                0x00000009U
-#define FLASH_ACR_LATENCY_10WS               0x0000000AU
-#define FLASH_ACR_LATENCY_11WS               0x0000000BU
-#define FLASH_ACR_LATENCY_12WS               0x0000000CU
-#define FLASH_ACR_LATENCY_13WS               0x0000000DU
-#define FLASH_ACR_LATENCY_14WS               0x0000000EU
-#define FLASH_ACR_LATENCY_15WS               0x0000000FU
-#define FLASH_ACR_PRFTEN                     0x00000100U
-#define FLASH_ACR_ARTEN                      0x00000200U
-#define FLASH_ACR_ARTRST                     0x00000800U
-
-/*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         0x00000001U
-#define FLASH_SR_OPERR                       0x00000002U
-#define FLASH_SR_WRPERR                      0x00000010U
-#define FLASH_SR_PGAERR                      0x00000020U
-#define FLASH_SR_PGPERR                      0x00000040U
-#define FLASH_SR_ERSERR                      0x00000080U
-#define FLASH_SR_BSY                         0x00010000U
-
-/*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          0x00000001U
-#define FLASH_CR_SER                         0x00000002U
-#define FLASH_CR_MER                         0x00000004U
-#define FLASH_CR_SNB                         0x00000078U
-#define FLASH_CR_SNB_0                       0x00000008U
-#define FLASH_CR_SNB_1                       0x00000010U
-#define FLASH_CR_SNB_2                       0x00000020U
-#define FLASH_CR_SNB_3                       0x00000040U
-#define FLASH_CR_PSIZE                       0x00000300U
-#define FLASH_CR_PSIZE_0                     0x00000100U
-#define FLASH_CR_PSIZE_1                     0x00000200U
-#define FLASH_CR_STRT                        0x00010000U
-#define FLASH_CR_EOPIE                       0x01000000U
-#define FLASH_CR_ERRIE                       0x02000000U
-#define FLASH_CR_LOCK                        0x80000000U
-
-/*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                 0x00000001U
-#define FLASH_OPTCR_OPTSTRT                 0x00000002U
-#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
-#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
-#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
-#define FLASH_OPTCR_WWDG_SW                 0x00000010U
-#define FLASH_OPTCR_IWDG_SW                 0x00000020U
-#define FLASH_OPTCR_nRST_STOP               0x00000040U
-#define FLASH_OPTCR_nRST_STDBY              0x00000080U
-#define FLASH_OPTCR_RDP                     0x0000FF00U
-#define FLASH_OPTCR_RDP_0                   0x00000100U
-#define FLASH_OPTCR_RDP_1                   0x00000200U
-#define FLASH_OPTCR_RDP_2                   0x00000400U
-#define FLASH_OPTCR_RDP_3                   0x00000800U
-#define FLASH_OPTCR_RDP_4                   0x00001000U
-#define FLASH_OPTCR_RDP_5                   0x00002000U
-#define FLASH_OPTCR_RDP_6                   0x00004000U
-#define FLASH_OPTCR_RDP_7                   0x00008000U
-#define FLASH_OPTCR_nWRP                    0x00FF0000U
-#define FLASH_OPTCR_nWRP_0                  0x00010000U
-#define FLASH_OPTCR_nWRP_1                  0x00020000U
-#define FLASH_OPTCR_nWRP_2                  0x00040000U
-#define FLASH_OPTCR_nWRP_3                  0x00080000U
-#define FLASH_OPTCR_nWRP_4                  0x00100000U
-#define FLASH_OPTCR_nWRP_5                  0x00200000U
-#define FLASH_OPTCR_nWRP_6                  0x00400000U
-#define FLASH_OPTCR_nWRP_7                  0x00800000U
-#define FLASH_OPTCR_IWDG_STDBY              0x40000000U
-#define FLASH_OPTCR_IWDG_STOP               0x80000000U
-
-/*******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_BOOT_ADD0              0x0000FFFFU
-#define FLASH_OPTCR1_BOOT_ADD1              0xFFFF0000U
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Flexible Memory Controller                        */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for FMC_BCR1 register  *******************/
-#define  FMC_BCR1_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR1_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-#define  FMC_BCR1_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR1_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR1_MTYP_1                    0x00000008U        /*!<Bit 1 */
-#define  FMC_BCR1_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR1_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR1_MWID_1                    0x00000020U        /*!<Bit 1 */
-#define  FMC_BCR1_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR1_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR1_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR1_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
-#define  FMC_BCR1_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR1_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR1_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR1_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR1_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR1_CPSIZE                    0x00070000U        /*!<CRAM page size             */
-#define  FMC_BCR1_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FMC_BCR1_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FMC_BCR1_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FMC_BCR1_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-#define  FMC_BCR1_CCLKEN                    0x00100000U        /*!<Continous clock enable     */
-#define  FMC_BCR1_WFDIS                     0x00200000U        /*!<Write FIFO Disable         */
-
-/******************  Bit definition for FMC_BCR2 register  *******************/
-#define  FMC_BCR2_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR2_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-#define  FMC_BCR2_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR2_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR2_MTYP_1                    0x00000008U        /*!<Bit 1 */
-#define  FMC_BCR2_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR2_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR2_MWID_1                    0x00000020U        /*!<Bit 1 */
-#define  FMC_BCR2_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR2_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR2_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR2_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
-#define  FMC_BCR2_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR2_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR2_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR2_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR2_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR2_CPSIZE                    0x00070000U        /*!<CRAM page size             */
-#define  FMC_BCR2_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FMC_BCR2_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FMC_BCR2_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FMC_BCR2_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FMC_BCR3 register  *******************/
-#define  FMC_BCR3_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR3_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-#define  FMC_BCR3_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR3_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR3_MTYP_1                    0x00000008U        /*!<Bit 1 */
-#define  FMC_BCR3_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR3_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR3_MWID_1                    0x00000020U        /*!<Bit 1 */
-#define  FMC_BCR3_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR3_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR3_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR3_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
-#define  FMC_BCR3_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR3_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR3_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR3_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR3_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR3_CPSIZE                    0x00070000U        /*!<CRAM page size             */
-#define  FMC_BCR3_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FMC_BCR3_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FMC_BCR3_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FMC_BCR3_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FMC_BCR4 register  *******************/
-#define  FMC_BCR4_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR4_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-#define  FMC_BCR4_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR4_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR4_MTYP_1                    0x00000008U        /*!<Bit 1 */
-#define  FMC_BCR4_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR4_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR4_MWID_1                    0x00000020U        /*!<Bit 1 */
-#define  FMC_BCR4_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR4_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR4_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR4_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
-#define  FMC_BCR4_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR4_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR4_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR4_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR4_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR4_CPSIZE                    0x00070000U        /*!<CRAM page size             */
-#define  FMC_BCR4_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FMC_BCR4_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FMC_BCR4_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FMC_BCR4_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FMC_BTR1 register  ******************/
-#define  FMC_BTR1_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR1_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR1_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR1_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR1_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-#define  FMC_BTR1_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
-#define  FMC_BTR1_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR1_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR1_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR1_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-#define  FMC_BTR1_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR1_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR1_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR1_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR1_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR1_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR1_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR1_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR1_DATAST_7                  0x00008000U        /*!<Bit 7 */
-#define  FMC_BTR1_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR1_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR1_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR1_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR1_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-#define  FMC_BTR1_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR1_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR1_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR1_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR1_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-#define  FMC_BTR1_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR1_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR1_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR1_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR1_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-#define  FMC_BTR1_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR1_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR1_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BTR2 register  *******************/
-#define  FMC_BTR2_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR2_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR2_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR2_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR2_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-#define  FMC_BTR2_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR2_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR2_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR2_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR2_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-#define  FMC_BTR2_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR2_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR2_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR2_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR2_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR2_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR2_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR2_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR2_DATAST_7                  0x00008000U        /*!<Bit 7 */
-#define  FMC_BTR2_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR2_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR2_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR2_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR2_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-#define  FMC_BTR2_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR2_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR2_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR2_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR2_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-#define  FMC_BTR2_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR2_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR2_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR2_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR2_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-#define  FMC_BTR2_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR2_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR2_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/*******************  Bit definition for FMC_BTR3 register  *******************/
-#define  FMC_BTR3_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR3_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR3_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR3_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR3_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-#define  FMC_BTR3_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR3_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR3_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR3_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR3_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-#define  FMC_BTR3_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR3_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR3_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR3_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR3_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR3_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR3_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR3_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR3_DATAST_7                  0x00008000U        /*!<Bit 7 */
-#define  FMC_BTR3_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR3_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR3_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR3_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR3_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-#define  FMC_BTR3_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR3_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR3_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR3_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR3_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-#define  FMC_BTR3_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR3_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR3_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR3_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR3_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-#define  FMC_BTR3_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR3_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR3_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BTR4 register  *******************/
-#define  FMC_BTR4_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR4_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR4_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR4_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR4_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-#define  FMC_BTR4_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR4_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR4_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR4_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR4_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-#define  FMC_BTR4_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR4_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR4_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR4_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR4_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR4_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR4_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR4_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR4_DATAST_7                  0x00008000U        /*!<Bit 7 */
-#define  FMC_BTR4_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR4_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR4_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR4_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR4_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-#define  FMC_BTR4_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR4_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR4_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR4_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR4_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-#define  FMC_BTR4_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR4_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR4_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR4_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR4_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-#define  FMC_BTR4_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR4_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR4_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR1 register  ******************/
-#define  FMC_BWTR1_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR1_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR1_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR1_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR1_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-#define  FMC_BWTR1_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR1_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR1_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR1_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR1_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-#define  FMC_BWTR1_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR1_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR1_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR1_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR1_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR1_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR1_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR1_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR1_DATAST_7                 0x00008000U        /*!<Bit 7 */
-#define  FMC_BWTR1_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BWTR1_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR1_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR1_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR1_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-#define  FMC_BWTR1_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR1_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR1_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR2 register  ******************/
-#define  FMC_BWTR2_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR2_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR2_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR2_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR2_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-#define  FMC_BWTR2_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR2_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR2_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR2_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR2_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-#define  FMC_BWTR2_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR2_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR2_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR2_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR2_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR2_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR2_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR2_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR2_DATAST_7                 0x00008000U        /*!<Bit 7 */
-#define  FMC_BWTR2_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BWTR2_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR2_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR2_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR2_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-#define  FMC_BWTR2_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR2_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR2_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR3 register  ******************/
-#define  FMC_BWTR3_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR3_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR3_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR3_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR3_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-#define  FMC_BWTR3_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR3_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR3_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR3_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR3_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-#define  FMC_BWTR3_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR3_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR3_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR3_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR3_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR3_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR3_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR3_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR3_DATAST_7                 0x00008000U        /*!<Bit 7 */
-#define  FMC_BWTR3_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BWTR3_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR3_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR3_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR3_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-#define  FMC_BWTR3_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR3_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR3_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR4 register  ******************/
-#define  FMC_BWTR4_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR4_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR4_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR4_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR4_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-#define  FMC_BWTR4_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR4_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR4_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR4_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR4_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-#define  FMC_BWTR4_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR4_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR4_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR4_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR4_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR4_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR4_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR4_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR4_DATAST_7                 0x00008000U        /*!<Bit 7 */
-#define  FMC_BWTR4_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BWTR4_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR4_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR4_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR4_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-#define  FMC_BWTR4_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR4_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR4_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_PCR register  *******************/
-#define  FMC_PCR_PWAITEN                   0x00000002U        /*!<Wait feature enable bit                   */
-#define  FMC_PCR_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FMC_PCR_PTYP                      0x00000008U        /*!<Memory type                               */
-#define  FMC_PCR_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FMC_PCR_PWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_PCR_PWID_1                    0x00000020U        /*!<Bit 1 */
-#define  FMC_PCR_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit          */
-#define  FMC_PCR_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay)          */
-#define  FMC_PCR_TCLR_0                    0x00000200U        /*!<Bit 0 */
-#define  FMC_PCR_TCLR_1                    0x00000400U        /*!<Bit 1 */
-#define  FMC_PCR_TCLR_2                    0x00000800U        /*!<Bit 2 */
-#define  FMC_PCR_TCLR_3                    0x00001000U        /*!<Bit 3 */
-#define  FMC_PCR_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay)           */
-#define  FMC_PCR_TAR_0                     0x00002000U        /*!<Bit 0 */
-#define  FMC_PCR_TAR_1                     0x00004000U        /*!<Bit 1 */
-#define  FMC_PCR_TAR_2                     0x00008000U        /*!<Bit 2 */
-#define  FMC_PCR_TAR_3                     0x00010000U        /*!<Bit 3 */
-#define  FMC_PCR_ECCPS                     0x000E0000U        /*!<ECCPS[2:0] bits (ECC page size)           */
-#define  FMC_PCR_ECCPS_0                   0x00020000U        /*!<Bit 0 */
-#define  FMC_PCR_ECCPS_1                   0x00040000U        /*!<Bit 1 */
-#define  FMC_PCR_ECCPS_2                   0x00080000U        /*!<Bit 2 */
-
-/*******************  Bit definition for FMC_SR register  *******************/
-#define  FMC_SR_IRS                        0x01U              /*!<Interrupt Rising Edge status                */
-#define  FMC_SR_ILS                        0x02U              /*!<Interrupt Level status                      */
-#define  FMC_SR_IFS                        0x04U              /*!<Interrupt Falling Edge status               */
-#define  FMC_SR_IREN                       0x08U              /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FMC_SR_ILEN                       0x10U              /*!<Interrupt Level detection Enable bit        */
-#define  FMC_SR_IFEN                       0x20U              /*!<Interrupt Falling Edge detection Enable bit */
-#define  FMC_SR_FEMPT                      0x40U              /*!<FIFO empty                                  */
-
-/******************  Bit definition for FMC_PMEM register  ******************/
-#define  FMC_PMEM_MEMSET3                  0x000000FFU        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
-#define  FMC_PMEM_MEMSET3_0                0x00000001U        /*!<Bit 0 */
-#define  FMC_PMEM_MEMSET3_1                0x00000002U        /*!<Bit 1 */
-#define  FMC_PMEM_MEMSET3_2                0x00000004U        /*!<Bit 2 */
-#define  FMC_PMEM_MEMSET3_3                0x00000008U        /*!<Bit 3 */
-#define  FMC_PMEM_MEMSET3_4                0x00000010U        /*!<Bit 4 */
-#define  FMC_PMEM_MEMSET3_5                0x00000020U        /*!<Bit 5 */
-#define  FMC_PMEM_MEMSET3_6                0x00000040U        /*!<Bit 6 */
-#define  FMC_PMEM_MEMSET3_7                0x00000080U        /*!<Bit 7 */
-#define  FMC_PMEM_MEMWAIT3                 0x0000FF00U        /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
-#define  FMC_PMEM_MEMWAIT3_0               0x00000100U        /*!<Bit 0 */
-#define  FMC_PMEM_MEMWAIT3_1               0x00000200U        /*!<Bit 1 */
-#define  FMC_PMEM_MEMWAIT3_2               0x00000400U        /*!<Bit 2 */
-#define  FMC_PMEM_MEMWAIT3_3               0x00000800U        /*!<Bit 3 */
-#define  FMC_PMEM_MEMWAIT3_4               0x00001000U        /*!<Bit 4 */
-#define  FMC_PMEM_MEMWAIT3_5               0x00002000U        /*!<Bit 5 */
-#define  FMC_PMEM_MEMWAIT3_6               0x00004000U        /*!<Bit 6 */
-#define  FMC_PMEM_MEMWAIT3_7               0x00008000U        /*!<Bit 7 */
-#define  FMC_PMEM_MEMHOLD3                 0x00FF0000U        /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
-#define  FMC_PMEM_MEMHOLD3_0               0x00010000U        /*!<Bit 0 */
-#define  FMC_PMEM_MEMHOLD3_1               0x00020000U        /*!<Bit 1 */
-#define  FMC_PMEM_MEMHOLD3_2               0x00040000U        /*!<Bit 2 */
-#define  FMC_PMEM_MEMHOLD3_3               0x00080000U        /*!<Bit 3 */
-#define  FMC_PMEM_MEMHOLD3_4               0x00100000U        /*!<Bit 4 */
-#define  FMC_PMEM_MEMHOLD3_5               0x00200000U        /*!<Bit 5 */
-#define  FMC_PMEM_MEMHOLD3_6               0x00400000U        /*!<Bit 6 */
-#define  FMC_PMEM_MEMHOLD3_7               0x00800000U        /*!<Bit 7 */
-#define  FMC_PMEM_MEMHIZ3                  0xFF000000U        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
-#define  FMC_PMEM_MEMHIZ3_0                0x01000000U        /*!<Bit 0 */
-#define  FMC_PMEM_MEMHIZ3_1                0x02000000U        /*!<Bit 1 */
-#define  FMC_PMEM_MEMHIZ3_2                0x04000000U        /*!<Bit 2 */
-#define  FMC_PMEM_MEMHIZ3_3                0x08000000U        /*!<Bit 3 */
-#define  FMC_PMEM_MEMHIZ3_4                0x10000000U        /*!<Bit 4 */
-#define  FMC_PMEM_MEMHIZ3_5                0x20000000U        /*!<Bit 5 */
-#define  FMC_PMEM_MEMHIZ3_6                0x40000000U        /*!<Bit 6 */
-#define  FMC_PMEM_MEMHIZ3_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_PATT register  ******************/
-#define  FMC_PATT_ATTSET3                  0x000000FFU        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
-#define  FMC_PATT_ATTSET3_0                0x00000001U        /*!<Bit 0 */
-#define  FMC_PATT_ATTSET3_1                0x00000002U        /*!<Bit 1 */
-#define  FMC_PATT_ATTSET3_2                0x00000004U        /*!<Bit 2 */
-#define  FMC_PATT_ATTSET3_3                0x00000008U        /*!<Bit 3 */
-#define  FMC_PATT_ATTSET3_4                0x00000010U        /*!<Bit 4 */
-#define  FMC_PATT_ATTSET3_5                0x00000020U        /*!<Bit 5 */
-#define  FMC_PATT_ATTSET3_6                0x00000040U        /*!<Bit 6 */
-#define  FMC_PATT_ATTSET3_7                0x00000080U        /*!<Bit 7 */
-#define  FMC_PATT_ATTWAIT3                 0x0000FF00U        /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
-#define  FMC_PATT_ATTWAIT3_0               0x00000100U        /*!<Bit 0 */
-#define  FMC_PATT_ATTWAIT3_1               0x00000200U        /*!<Bit 1 */
-#define  FMC_PATT_ATTWAIT3_2               0x00000400U        /*!<Bit 2 */
-#define  FMC_PATT_ATTWAIT3_3               0x00000800U        /*!<Bit 3 */
-#define  FMC_PATT_ATTWAIT3_4               0x00001000U        /*!<Bit 4 */
-#define  FMC_PATT_ATTWAIT3_5               0x00002000U        /*!<Bit 5 */
-#define  FMC_PATT_ATTWAIT3_6               0x00004000U        /*!<Bit 6 */
-#define  FMC_PATT_ATTWAIT3_7               0x00008000U        /*!<Bit 7 */
-#define  FMC_PATT_ATTHOLD3                 0x00FF0000U        /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
-#define  FMC_PATT_ATTHOLD3_0               0x00010000U        /*!<Bit 0 */
-#define  FMC_PATT_ATTHOLD3_1               0x00020000U        /*!<Bit 1 */
-#define  FMC_PATT_ATTHOLD3_2               0x00040000U        /*!<Bit 2 */
-#define  FMC_PATT_ATTHOLD3_3               0x00080000U        /*!<Bit 3 */
-#define  FMC_PATT_ATTHOLD3_4               0x00100000U        /*!<Bit 4 */
-#define  FMC_PATT_ATTHOLD3_5               0x00200000U        /*!<Bit 5 */
-#define  FMC_PATT_ATTHOLD3_6               0x00400000U        /*!<Bit 6 */
-#define  FMC_PATT_ATTHOLD3_7               0x00800000U        /*!<Bit 7 */
-#define  FMC_PATT_ATTHIZ3                  0xFF000000U        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
-#define  FMC_PATT_ATTHIZ3_0                0x01000000U        /*!<Bit 0 */
-#define  FMC_PATT_ATTHIZ3_1                0x02000000U        /*!<Bit 1 */
-#define  FMC_PATT_ATTHIZ3_2                0x04000000U        /*!<Bit 2 */
-#define  FMC_PATT_ATTHIZ3_3                0x08000000U        /*!<Bit 3 */
-#define  FMC_PATT_ATTHIZ3_4                0x10000000U        /*!<Bit 4 */
-#define  FMC_PATT_ATTHIZ3_5                0x20000000U        /*!<Bit 5 */
-#define  FMC_PATT_ATTHIZ3_6                0x40000000U        /*!<Bit 6 */
-#define  FMC_PATT_ATTHIZ3_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_ECCR register  ******************/
-#define  FMC_ECCR_ECC3                     0xFFFFFFFFU        /*!<ECC result */
-
-/******************  Bit definition for FMC_SDCR1 register  ******************/
-#define  FMC_SDCR1_NC                       0x00000003U        /*!<NC[1:0] bits (Number of column bits) */
-#define  FMC_SDCR1_NC_0                     0x00000001U        /*!<Bit 0 */
-#define  FMC_SDCR1_NC_1                     0x00000002U        /*!<Bit 1 */
-#define  FMC_SDCR1_NR                       0x0000000CU        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR1_NR_0                     0x00000004U        /*!<Bit 0 */
-#define  FMC_SDCR1_NR_1                     0x00000008U        /*!<Bit 1 */
-#define  FMC_SDCR1_MWID                     0x00000030U        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR1_MWID_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDCR1_MWID_1                   0x00000020U        /*!<Bit 1 */
-#define  FMC_SDCR1_NB                       0x00000040U        /*!<Number of internal bank */
-#define  FMC_SDCR1_CAS                      0x00000180U        /*!<CAS[1:0] bits (CAS latency) */
-#define  FMC_SDCR1_CAS_0                    0x00000080U        /*!<Bit 0 */
-#define  FMC_SDCR1_CAS_1                    0x00000100U        /*!<Bit 1 */
-#define  FMC_SDCR1_WP                       0x00000200U        /*!<Write protection */
-#define  FMC_SDCR1_SDCLK                    0x00000C00U        /*!<SDRAM clock configuration */
-#define  FMC_SDCR1_SDCLK_0                  0x00000400U        /*!<Bit 0 */
-#define  FMC_SDCR1_SDCLK_1                  0x00000800U        /*!<Bit 1 */
-#define  FMC_SDCR1_RBURST                   0x00001000U        /*!<Read burst */
-#define  FMC_SDCR1_RPIPE                    0x00006000U        /*!<Write protection */
-#define  FMC_SDCR1_RPIPE_0                  0x00002000U        /*!<Bit 0 */
-#define  FMC_SDCR1_RPIPE_1                  0x00004000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_SDCR2 register  ******************/
-#define  FMC_SDCR2_NC                       0x00000003U        /*!<NC[1:0] bits (Number of column bits) */
-#define  FMC_SDCR2_NC_0                     0x00000001U        /*!<Bit 0 */
-#define  FMC_SDCR2_NC_1                     0x00000002U        /*!<Bit 1 */
-#define  FMC_SDCR2_NR                       0x0000000CU        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR2_NR_0                     0x00000004U        /*!<Bit 0 */
-#define  FMC_SDCR2_NR_1                     0x00000008U        /*!<Bit 1 */
-#define  FMC_SDCR2_MWID                     0x00000030U        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR2_MWID_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDCR2_MWID_1                   0x00000020U        /*!<Bit 1 */
-#define  FMC_SDCR2_NB                       0x00000040U        /*!<Number of internal bank */
-#define  FMC_SDCR2_CAS                      0x00000180U        /*!<CAS[1:0] bits (CAS latency) */
-#define  FMC_SDCR2_CAS_0                    0x00000080U        /*!<Bit 0 */
-#define  FMC_SDCR2_CAS_1                    0x00000100U        /*!<Bit 1 */
-#define  FMC_SDCR2_WP                       0x00000200U        /*!<Write protection */
-#define  FMC_SDCR2_SDCLK                    0x00000C00U        /*!<SDCLK[1:0] (SDRAM clock configuration) */
-#define  FMC_SDCR2_SDCLK_0                  0x00000400U        /*!<Bit 0 */
-#define  FMC_SDCR2_SDCLK_1                  0x00000800U        /*!<Bit 1 */
-#define  FMC_SDCR2_RBURST                   0x00001000U        /*!<Read burst */
-#define  FMC_SDCR2_RPIPE                    0x00006000U        /*!<RPIPE[1:0](Read pipe) */
-#define  FMC_SDCR2_RPIPE_0                  0x00002000U        /*!<Bit 0 */
-#define  FMC_SDCR2_RPIPE_1                  0x00004000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_SDTR1 register  ******************/
-#define  FMC_SDTR1_TMRD                     0x0000000FU        /*!<TMRD[3:0] bits (Load mode register to active) */
-#define  FMC_SDTR1_TMRD_0                   0x00000001U        /*!<Bit 0 */
-#define  FMC_SDTR1_TMRD_1                   0x00000002U        /*!<Bit 1 */
-#define  FMC_SDTR1_TMRD_2                   0x00000004U        /*!<Bit 2 */
-#define  FMC_SDTR1_TMRD_3                   0x00000008U        /*!<Bit 3 */
-#define  FMC_SDTR1_TXSR                     0x000000F0U        /*!<TXSR[3:0] bits (Exit self refresh) */
-#define  FMC_SDTR1_TXSR_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDTR1_TXSR_1                   0x00000020U        /*!<Bit 1 */
-#define  FMC_SDTR1_TXSR_2                   0x00000040U        /*!<Bit 2 */
-#define  FMC_SDTR1_TXSR_3                   0x00000080U        /*!<Bit 3 */
-#define  FMC_SDTR1_TRAS                     0x00000F00U        /*!<TRAS[3:0] bits (Self refresh time) */
-#define  FMC_SDTR1_TRAS_0                   0x00000100U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRAS_1                   0x00000200U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRAS_2                   0x00000400U        /*!<Bit 2 */
-#define  FMC_SDTR1_TRAS_3                   0x00000800U        /*!<Bit 3 */
-#define  FMC_SDTR1_TRC                      0x0000F000U        /*!<TRC[2:0] bits (Row cycle delay) */
-#define  FMC_SDTR1_TRC_0                    0x00001000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRC_1                    0x00002000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRC_2                    0x00004000U        /*!<Bit 2 */
-#define  FMC_SDTR1_TWR                      0x000F0000U        /*!<TRC[2:0] bits (Write recovery delay) */
-#define  FMC_SDTR1_TWR_0                    0x00010000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TWR_1                    0x00020000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TWR_2                    0x00040000U        /*!<Bit 2 */
-#define  FMC_SDTR1_TRP                      0x00F00000U        /*!<TRP[2:0] bits (Row precharge delay) */
-#define  FMC_SDTR1_TRP_0                    0x00100000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRP_1                    0x00200000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRP_2                    0x00400000U        /*!<Bit 2 */
-#define  FMC_SDTR1_TRCD                     0x0F000000U        /*!<TRP[2:0] bits (Row to column delay) */
-#define  FMC_SDTR1_TRCD_0                   0x01000000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRCD_1                   0x02000000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRCD_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for FMC_SDTR2 register  ******************/
-#define  FMC_SDTR2_TMRD                     0x0000000FU        /*!<TMRD[3:0] bits (Load mode register to active) */
-#define  FMC_SDTR2_TMRD_0                   0x00000001U        /*!<Bit 0 */
-#define  FMC_SDTR2_TMRD_1                   0x00000002U        /*!<Bit 1 */
-#define  FMC_SDTR2_TMRD_2                   0x00000004U        /*!<Bit 2 */
-#define  FMC_SDTR2_TMRD_3                   0x00000008U        /*!<Bit 3 */
-#define  FMC_SDTR2_TXSR                     0x000000F0U        /*!<TXSR[3:0] bits (Exit self refresh) */
-#define  FMC_SDTR2_TXSR_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDTR2_TXSR_1                   0x00000020U        /*!<Bit 1 */
-#define  FMC_SDTR2_TXSR_2                   0x00000040U        /*!<Bit 2 */
-#define  FMC_SDTR2_TXSR_3                   0x00000080U        /*!<Bit 3 */
-#define  FMC_SDTR2_TRAS                     0x00000F00U        /*!<TRAS[3:0] bits (Self refresh time) */
-#define  FMC_SDTR2_TRAS_0                   0x00000100U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRAS_1                   0x00000200U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRAS_2                   0x00000400U        /*!<Bit 2 */
-#define  FMC_SDTR2_TRAS_3                   0x00000800U        /*!<Bit 3 */
-#define  FMC_SDTR2_TRC                      0x0000F000U        /*!<TRC[2:0] bits (Row cycle delay) */
-#define  FMC_SDTR2_TRC_0                    0x00001000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRC_1                    0x00002000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRC_2                    0x00004000U        /*!<Bit 2 */
-#define  FMC_SDTR2_TWR                      0x000F0000U        /*!<TRC[2:0] bits (Write recovery delay) */
-#define  FMC_SDTR2_TWR_0                    0x00010000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TWR_1                    0x00020000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TWR_2                    0x00040000U        /*!<Bit 2 */
-#define  FMC_SDTR2_TRP                      0x00F00000U        /*!<TRP[2:0] bits (Row precharge delay) */
-#define  FMC_SDTR2_TRP_0                    0x00100000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRP_1                    0x00200000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRP_2                    0x00400000U        /*!<Bit 2 */
-#define  FMC_SDTR2_TRCD                     0x0F000000U        /*!<TRP[2:0] bits (Row to column delay) */
-#define  FMC_SDTR2_TRCD_0                   0x01000000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRCD_1                   0x02000000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRCD_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for FMC_SDCMR register  ******************/
-#define  FMC_SDCMR_MODE                     0x00000007U        /*!<MODE[2:0] bits (Command mode) */
-#define  FMC_SDCMR_MODE_0                   0x00000001U        /*!<Bit 0 */
-#define  FMC_SDCMR_MODE_1                   0x00000002U        /*!<Bit 1 */
-#define  FMC_SDCMR_MODE_2                   0x00000003U        /*!<Bit 2 */
-#define  FMC_SDCMR_CTB2                     0x00000008U        /*!<Command target 2 */
-#define  FMC_SDCMR_CTB1                     0x00000010U        /*!<Command target 1 */
-#define  FMC_SDCMR_NRFS                     0x000001E0U        /*!<NRFS[3:0] bits (Number of auto-refresh) */
-#define  FMC_SDCMR_NRFS_0                   0x00000020U        /*!<Bit 0 */
-#define  FMC_SDCMR_NRFS_1                   0x00000040U        /*!<Bit 1 */
-#define  FMC_SDCMR_NRFS_2                   0x00000080U        /*!<Bit 2 */
-#define  FMC_SDCMR_NRFS_3                   0x00000100U        /*!<Bit 3 */
-#define  FMC_SDCMR_MRD                      0x003FFE00U        /*!<MRD[12:0] bits (Mode register definition) */
-
-/******************  Bit definition for FMC_SDRTR register  ******************/
-#define  FMC_SDRTR_CRE                      0x00000001U        /*!<Clear refresh error flag */
-#define  FMC_SDRTR_COUNT                    0x00003FFEU        /*!<COUNT[12:0] bits (Refresh timer count) */
-#define  FMC_SDRTR_REIE                     0x00004000U        /*!<RES interupt enable */
-
-/******************  Bit definition for FMC_SDSR register  ******************/
-#define  FMC_SDSR_RE                        0x00000001U        /*!<Refresh error flag */
-#define  FMC_SDSR_MODES1                    0x00000006U        /*!<MODES1[1:0]bits (Status mode for bank 1) */
-#define  FMC_SDSR_MODES1_0                  0x00000002U        /*!<Bit 0 */
-#define  FMC_SDSR_MODES1_1                  0x00000004U        /*!<Bit 1 */
-#define  FMC_SDSR_MODES2                    0x00000018U        /*!<MODES2[1:0]bits (Status mode for bank 2) */
-#define  FMC_SDSR_MODES2_0                  0x00000008U        /*!<Bit 0 */
-#define  FMC_SDSR_MODES2_1                  0x00000010U        /*!<Bit 1 */
-#define  FMC_SDSR_BUSY                      0x00000020U        /*!<Busy status */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    0x00000003U
-#define GPIO_MODER_MODER0_0                  0x00000001U
-#define GPIO_MODER_MODER0_1                  0x00000002U
-#define GPIO_MODER_MODER1                    0x0000000CU
-#define GPIO_MODER_MODER1_0                  0x00000004U
-#define GPIO_MODER_MODER1_1                  0x00000008U
-#define GPIO_MODER_MODER2                    0x00000030U
-#define GPIO_MODER_MODER2_0                  0x00000010U
-#define GPIO_MODER_MODER2_1                  0x00000020U
-#define GPIO_MODER_MODER3                    0x000000C0U
-#define GPIO_MODER_MODER3_0                  0x00000040U
-#define GPIO_MODER_MODER3_1                  0x00000080U
-#define GPIO_MODER_MODER4                    0x00000300U
-#define GPIO_MODER_MODER4_0                  0x00000100U
-#define GPIO_MODER_MODER4_1                  0x00000200U
-#define GPIO_MODER_MODER5                    0x00000C00U
-#define GPIO_MODER_MODER5_0                  0x00000400U
-#define GPIO_MODER_MODER5_1                  0x00000800U
-#define GPIO_MODER_MODER6                    0x00003000U
-#define GPIO_MODER_MODER6_0                  0x00001000U
-#define GPIO_MODER_MODER6_1                  0x00002000U
-#define GPIO_MODER_MODER7                    0x0000C000U
-#define GPIO_MODER_MODER7_0                  0x00004000U
-#define GPIO_MODER_MODER7_1                  0x00008000U
-#define GPIO_MODER_MODER8                    0x00030000U
-#define GPIO_MODER_MODER8_0                  0x00010000U
-#define GPIO_MODER_MODER8_1                  0x00020000U
-#define GPIO_MODER_MODER9                    0x000C0000U
-#define GPIO_MODER_MODER9_0                  0x00040000U
-#define GPIO_MODER_MODER9_1                  0x00080000U
-#define GPIO_MODER_MODER10                   0x00300000U
-#define GPIO_MODER_MODER10_0                 0x00100000U
-#define GPIO_MODER_MODER10_1                 0x00200000U
-#define GPIO_MODER_MODER11                   0x00C00000U
-#define GPIO_MODER_MODER11_0                 0x00400000U
-#define GPIO_MODER_MODER11_1                 0x00800000U
-#define GPIO_MODER_MODER12                   0x03000000U
-#define GPIO_MODER_MODER12_0                 0x01000000U
-#define GPIO_MODER_MODER12_1                 0x02000000U
-#define GPIO_MODER_MODER13                   0x0C000000U
-#define GPIO_MODER_MODER13_0                 0x04000000U
-#define GPIO_MODER_MODER13_1                 0x08000000U
-#define GPIO_MODER_MODER14                   0x30000000U
-#define GPIO_MODER_MODER14_0                 0x10000000U
-#define GPIO_MODER_MODER14_1                 0x20000000U
-#define GPIO_MODER_MODER15                   0xC0000000U
-#define GPIO_MODER_MODER15_0                 0x40000000U
-#define GPIO_MODER_MODER15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     0x00000001U
-#define GPIO_OTYPER_OT_1                     0x00000002U
-#define GPIO_OTYPER_OT_2                     0x00000004U
-#define GPIO_OTYPER_OT_3                     0x00000008U
-#define GPIO_OTYPER_OT_4                     0x00000010U
-#define GPIO_OTYPER_OT_5                     0x00000020U
-#define GPIO_OTYPER_OT_6                     0x00000040U
-#define GPIO_OTYPER_OT_7                     0x00000080U
-#define GPIO_OTYPER_OT_8                     0x00000100U
-#define GPIO_OTYPER_OT_9                     0x00000200U
-#define GPIO_OTYPER_OT_10                    0x00000400U
-#define GPIO_OTYPER_OT_11                    0x00000800U
-#define GPIO_OTYPER_OT_12                    0x00001000U
-#define GPIO_OTYPER_OT_13                    0x00002000U
-#define GPIO_OTYPER_OT_14                    0x00004000U
-#define GPIO_OTYPER_OT_15                    0x00008000U
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
-#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
-#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
-#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
-#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
-#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
-#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
-#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
-#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
-#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
-#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
-#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
-#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
-#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
-#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
-#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
-#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
-#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
-#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
-#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
-#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
-#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
-#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
-#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
-#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
-#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
-#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
-#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
-#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
-#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
-#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
-#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
-#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
-#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
-#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
-#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
-#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
-#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
-#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
-#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
-#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
-#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
-#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
-#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
-#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
-#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
-#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
-#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    0x00000003U
-#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
-#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
-#define GPIO_PUPDR_PUPDR1                    0x0000000CU
-#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
-#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
-#define GPIO_PUPDR_PUPDR2                    0x00000030U
-#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
-#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
-#define GPIO_PUPDR_PUPDR3                    0x000000C0U
-#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
-#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
-#define GPIO_PUPDR_PUPDR4                    0x00000300U
-#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
-#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
-#define GPIO_PUPDR_PUPDR5                    0x00000C00U
-#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
-#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
-#define GPIO_PUPDR_PUPDR6                    0x00003000U
-#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
-#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
-#define GPIO_PUPDR_PUPDR7                    0x0000C000U
-#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
-#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
-#define GPIO_PUPDR_PUPDR8                    0x00030000U
-#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
-#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
-#define GPIO_PUPDR_PUPDR9                    0x000C0000U
-#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
-#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
-#define GPIO_PUPDR_PUPDR10                   0x00300000U
-#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
-#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
-#define GPIO_PUPDR_PUPDR11                   0x00C00000U
-#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
-#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
-#define GPIO_PUPDR_PUPDR12                   0x03000000U
-#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
-#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
-#define GPIO_PUPDR_PUPDR13                   0x0C000000U
-#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
-#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
-#define GPIO_PUPDR_PUPDR14                   0x30000000U
-#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
-#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
-#define GPIO_PUPDR_PUPDR15                   0xC0000000U
-#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
-#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       0x00000001U
-#define GPIO_IDR_IDR_1                       0x00000002U
-#define GPIO_IDR_IDR_2                       0x00000004U
-#define GPIO_IDR_IDR_3                       0x00000008U
-#define GPIO_IDR_IDR_4                       0x00000010U
-#define GPIO_IDR_IDR_5                       0x00000020U
-#define GPIO_IDR_IDR_6                       0x00000040U
-#define GPIO_IDR_IDR_7                       0x00000080U
-#define GPIO_IDR_IDR_8                       0x00000100U
-#define GPIO_IDR_IDR_9                       0x00000200U
-#define GPIO_IDR_IDR_10                      0x00000400U
-#define GPIO_IDR_IDR_11                      0x00000800U
-#define GPIO_IDR_IDR_12                      0x00001000U
-#define GPIO_IDR_IDR_13                      0x00002000U
-#define GPIO_IDR_IDR_14                      0x00004000U
-#define GPIO_IDR_IDR_15                      0x00008000U
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       0x00000001U
-#define GPIO_ODR_ODR_1                       0x00000002U
-#define GPIO_ODR_ODR_2                       0x00000004U
-#define GPIO_ODR_ODR_3                       0x00000008U
-#define GPIO_ODR_ODR_4                       0x00000010U
-#define GPIO_ODR_ODR_5                       0x00000020U
-#define GPIO_ODR_ODR_6                       0x00000040U
-#define GPIO_ODR_ODR_7                       0x00000080U
-#define GPIO_ODR_ODR_8                       0x00000100U
-#define GPIO_ODR_ODR_9                       0x00000200U
-#define GPIO_ODR_ODR_10                      0x00000400U
-#define GPIO_ODR_ODR_11                      0x00000800U
-#define GPIO_ODR_ODR_12                      0x00001000U
-#define GPIO_ODR_ODR_13                      0x00002000U
-#define GPIO_ODR_ODR_14                      0x00004000U
-#define GPIO_ODR_ODR_15                      0x00008000U
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       0x00000001U
-#define GPIO_BSRR_BS_1                       0x00000002U
-#define GPIO_BSRR_BS_2                       0x00000004U
-#define GPIO_BSRR_BS_3                       0x00000008U
-#define GPIO_BSRR_BS_4                       0x00000010U
-#define GPIO_BSRR_BS_5                       0x00000020U
-#define GPIO_BSRR_BS_6                       0x00000040U
-#define GPIO_BSRR_BS_7                       0x00000080U
-#define GPIO_BSRR_BS_8                       0x00000100U
-#define GPIO_BSRR_BS_9                       0x00000200U
-#define GPIO_BSRR_BS_10                      0x00000400U
-#define GPIO_BSRR_BS_11                      0x00000800U
-#define GPIO_BSRR_BS_12                      0x00001000U
-#define GPIO_BSRR_BS_13                      0x00002000U
-#define GPIO_BSRR_BS_14                      0x00004000U
-#define GPIO_BSRR_BS_15                      0x00008000U
-#define GPIO_BSRR_BR_0                       0x00010000U
-#define GPIO_BSRR_BR_1                       0x00020000U
-#define GPIO_BSRR_BR_2                       0x00040000U
-#define GPIO_BSRR_BR_3                       0x00080000U
-#define GPIO_BSRR_BR_4                       0x00100000U
-#define GPIO_BSRR_BR_5                       0x00200000U
-#define GPIO_BSRR_BR_6                       0x00400000U
-#define GPIO_BSRR_BR_7                       0x00800000U
-#define GPIO_BSRR_BR_8                       0x01000000U
-#define GPIO_BSRR_BR_9                       0x02000000U
-#define GPIO_BSRR_BR_10                      0x04000000U
-#define GPIO_BSRR_BR_11                      0x08000000U
-#define GPIO_BSRR_BR_12                      0x10000000U
-#define GPIO_BSRR_BR_13                      0x20000000U
-#define GPIO_BSRR_BR_14                      0x40000000U
-#define GPIO_BSRR_BR_15                      0x80000000U
-
-/****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0                       0x00000001U
-#define GPIO_LCKR_LCK1                       0x00000002U
-#define GPIO_LCKR_LCK2                       0x00000004U
-#define GPIO_LCKR_LCK3                       0x00000008U
-#define GPIO_LCKR_LCK4                       0x00000010U
-#define GPIO_LCKR_LCK5                       0x00000020U
-#define GPIO_LCKR_LCK6                       0x00000040U
-#define GPIO_LCKR_LCK7                       0x00000080U
-#define GPIO_LCKR_LCK8                       0x00000100U
-#define GPIO_LCKR_LCK9                       0x00000200U
-#define GPIO_LCKR_LCK10                      0x00000400U
-#define GPIO_LCKR_LCK11                      0x00000800U
-#define GPIO_LCKR_LCK12                      0x00001000U
-#define GPIO_LCKR_LCK13                      0x00002000U
-#define GPIO_LCKR_LCK14                      0x00004000U
-#define GPIO_LCKR_LCK15                      0x00008000U
-#define GPIO_LCKR_LCKK                       0x00010000U
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Inter-integrated Circuit Interface (I2C)              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define  I2C_CR1_PE                          0x00000001U        /*!< Peripheral enable                   */
-#define  I2C_CR1_TXIE                        0x00000002U        /*!< TX interrupt enable                 */
-#define  I2C_CR1_RXIE                        0x00000004U        /*!< RX interrupt enable                 */
-#define  I2C_CR1_ADDRIE                      0x00000008U        /*!< Address match interrupt enable      */
-#define  I2C_CR1_NACKIE                      0x00000010U        /*!< NACK received interrupt enable      */
-#define  I2C_CR1_STOPIE                      0x00000020U        /*!< STOP detection interrupt enable     */
-#define  I2C_CR1_TCIE                        0x00000040U        /*!< Transfer complete interrupt enable  */
-#define  I2C_CR1_ERRIE                       0x00000080U        /*!< Errors interrupt enable             */
-#define  I2C_CR1_DNF                         0x00000F00U        /*!< Digital noise filter                */
-#define  I2C_CR1_ANFOFF                      0x00001000U        /*!< Analog noise filter OFF             */
-#define  I2C_CR1_TXDMAEN                     0x00004000U        /*!< DMA transmission requests enable    */
-#define  I2C_CR1_RXDMAEN                     0x00008000U        /*!< DMA reception requests enable       */
-#define  I2C_CR1_SBC                         0x00010000U        /*!< Slave byte control                  */
-#define  I2C_CR1_NOSTRETCH                   0x00020000U        /*!< Clock stretching disable            */
-#define  I2C_CR1_GCEN                        0x00080000U        /*!< General call enable                 */
-#define  I2C_CR1_SMBHEN                      0x00100000U        /*!< SMBus host address enable           */
-#define  I2C_CR1_SMBDEN                      0x00200000U        /*!< SMBus device default address enable */
-#define  I2C_CR1_ALERTEN                     0x00400000U        /*!< SMBus alert enable                  */
-#define  I2C_CR1_PECEN                       0x00800000U        /*!< PEC enable                          */
-
-/* Legacy define */
-#define  I2C_CR1_DFN                         I2C_CR1_DNF                   /*!< Digital noise filter                */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_SADD                        0x000003FFU        /*!< Slave address (master mode)                             */
-#define  I2C_CR2_RD_WRN                      0x00000400U        /*!< Transfer direction (master mode)                        */
-#define  I2C_CR2_ADD10                       0x00000800U        /*!< 10-bit addressing mode (master mode)                    */
-#define  I2C_CR2_HEAD10R                     0x00001000U        /*!< 10-bit address header only read direction (master mode) */
-#define  I2C_CR2_START                       0x00002000U        /*!< START generation                                        */
-#define  I2C_CR2_STOP                        0x00004000U        /*!< STOP generation (master mode)                           */
-#define  I2C_CR2_NACK                        0x00008000U        /*!< NACK generation (slave mode)                            */
-#define  I2C_CR2_NBYTES                      0x00FF0000U        /*!< Number of bytes                                         */
-#define  I2C_CR2_RELOAD                      0x01000000U        /*!< NBYTES reload mode                                      */
-#define  I2C_CR2_AUTOEND                     0x02000000U        /*!< Automatic end mode (master mode)                        */
-#define  I2C_CR2_PECBYTE                     0x04000000U        /*!< Packet error checking byte                              */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define  I2C_OAR1_OA1                        0x000003FFU        /*!< Interface own address 1   */
-#define  I2C_OAR1_OA1MODE                    0x00000400U        /*!< Own address 1 10-bit mode */
-#define  I2C_OAR1_OA1EN                      0x00008000U        /*!< Own address 1 enable      */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define  I2C_OAR2_OA2                        0x000000FEU        /*!< Interface own address 2 */
-#define  I2C_OAR2_OA2MSK                     0x00000700U        /*!< Own address 2 masks     */
-#define  I2C_OAR2_OA2NOMASK                  0x00000000U        /*!< No mask */
-#define  I2C_OAR2_OA2MASK01                  0x00000100U        /*!< OA2[1] is masked, Only OA2[7:2] are compared */
-#define  I2C_OAR2_OA2MASK02                  0x00000200U        /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
-#define  I2C_OAR2_OA2MASK03                  0x00000300U        /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
-#define  I2C_OAR2_OA2MASK04                  0x00000400U        /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
-#define  I2C_OAR2_OA2MASK05                  0x00000500U        /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
-#define  I2C_OAR2_OA2MASK06                  0x00000600U        /*!< OA2[6:1] is masked, Only OA2[7] are compared */
-#define  I2C_OAR2_OA2MASK07                  0x00000700U        /*!< OA2[7:1] is masked, No comparison is done */
-#define  I2C_OAR2_OA2EN                      0x00008000U        /*!< Own address 2 enable    */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define  I2C_TIMINGR_SCLL                    0x000000FFU        /*!< SCL low period (master mode)  */
-#define  I2C_TIMINGR_SCLH                    0x0000FF00U        /*!< SCL high period (master mode) */
-#define  I2C_TIMINGR_SDADEL                  0x000F0000U        /*!< Data hold time                */
-#define  I2C_TIMINGR_SCLDEL                  0x00F00000U        /*!< Data setup time               */
-#define  I2C_TIMINGR_PRESC                   0xF0000000U        /*!< Timings prescaler             */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define  I2C_TIMEOUTR_TIMEOUTA               0x00000FFFU        /*!< Bus timeout A                 */
-#define  I2C_TIMEOUTR_TIDLE                  0x00001000U        /*!< Idle clock timeout detection  */
-#define  I2C_TIMEOUTR_TIMOUTEN               0x00008000U        /*!< Clock timeout enable          */
-#define  I2C_TIMEOUTR_TIMEOUTB               0x0FFF0000U        /*!< Bus timeout B                 */
-#define  I2C_TIMEOUTR_TEXTEN                 0x80000000U        /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define  I2C_ISR_TXE                         0x00000001U        /*!< Transmit data register empty    */
-#define  I2C_ISR_TXIS                        0x00000002U        /*!< Transmit interrupt status       */
-#define  I2C_ISR_RXNE                        0x00000004U        /*!< Receive data register not empty */
-#define  I2C_ISR_ADDR                        0x00000008U        /*!< Address matched (slave mode)    */
-#define  I2C_ISR_NACKF                       0x00000010U        /*!< NACK received flag              */
-#define  I2C_ISR_STOPF                       0x00000020U        /*!< STOP detection flag             */
-#define  I2C_ISR_TC                          0x00000040U        /*!< Transfer complete (master mode) */
-#define  I2C_ISR_TCR                         0x00000080U        /*!< Transfer complete reload        */
-#define  I2C_ISR_BERR                        0x00000100U        /*!< Bus error                       */
-#define  I2C_ISR_ARLO                        0x00000200U        /*!< Arbitration lost                */
-#define  I2C_ISR_OVR                         0x00000400U        /*!< Overrun/Underrun                */
-#define  I2C_ISR_PECERR                      0x00000800U        /*!< PEC error in reception          */
-#define  I2C_ISR_TIMEOUT                     0x00001000U        /*!< Timeout or Tlow detection flag  */
-#define  I2C_ISR_ALERT                       0x00002000U        /*!< SMBus alert                     */
-#define  I2C_ISR_BUSY                        0x00008000U        /*!< Bus busy                        */
-#define  I2C_ISR_DIR                         0x00010000U        /*!< Transfer direction (slave mode) */
-#define  I2C_ISR_ADDCODE                     0x00FE0000U        /*!< Address match code (slave mode) */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define  I2C_ICR_ADDRCF                      0x00000008U        /*!< Address matched clear flag      */
-#define  I2C_ICR_NACKCF                      0x00000010U        /*!< NACK clear flag                 */
-#define  I2C_ICR_STOPCF                      0x00000020U        /*!< STOP detection clear flag       */
-#define  I2C_ICR_BERRCF                      0x00000100U        /*!< Bus error clear flag            */
-#define  I2C_ICR_ARLOCF                      0x00000200U        /*!< Arbitration lost clear flag     */
-#define  I2C_ICR_OVRCF                       0x00000400U        /*!< Overrun/Underrun clear flag     */
-#define  I2C_ICR_PECCF                       0x00000800U        /*!< PAC error clear flag            */
-#define  I2C_ICR_TIMOUTCF                    0x00001000U        /*!< Timeout clear flag              */
-#define  I2C_ICR_ALERTCF                     0x00002000U        /*!< Alert clear flag                */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define  I2C_PECR_PEC                        0x000000FFU        /*!< PEC register        */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define  I2C_RXDR_RXDATA                     0x000000FFU        /*!< 8-bit receive data  */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define  I2C_TXDR_TXDATA                     0x000000FFU        /*!< 8-bit transmit data */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Independent WATCHDOG                             */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         0x01U               /*!< Watchdog prescaler value update */
-#define  IWDG_SR_RVU                         0x02U               /*!< Watchdog counter reload value update */
-#define  IWDG_SR_WVU                         0x04U               /*!< Watchdog counter window value update */
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_WINR_WIN                       0x0FFFU             /*!< Watchdog counter window value */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                             Power Control                                  */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for PWR_CR1 register  ********************/
-#define  PWR_CR1_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
-#define  PWR_CR1_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
-#define  PWR_CR1_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
-#define  PWR_CR1_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
-#define  PWR_CR1_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR1_PLS_0                        0x00000020U     /*!< Bit 0 */
-#define  PWR_CR1_PLS_1                        0x00000040U     /*!< Bit 1 */
-#define  PWR_CR1_PLS_2                        0x00000080U     /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define  PWR_CR1_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
-#define  PWR_CR1_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
-#define  PWR_CR1_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
-#define  PWR_CR1_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
-#define  PWR_CR1_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
-#define  PWR_CR1_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
-#define  PWR_CR1_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
-#define  PWR_CR1_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
-#define  PWR_CR1_DBP                          0x00000100U     /*!< Disable Backup Domain write protection                     */
-#define  PWR_CR1_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                              */
-#define  PWR_CR1_LPUDS                        0x00000400U     /*!< Low-power regulator in deepsleep under-drive mode          */
-#define  PWR_CR1_MRUDS                        0x00000800U     /*!< Main regulator in deepsleep under-drive mode               */
-#define  PWR_CR1_ADCDC1                       0x00002000U     /*!< Refer to AN4073 on how to use this bit */
-#define  PWR_CR1_VOS                          0x0000C000U     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
-#define  PWR_CR1_VOS_0                        0x00004000U     /*!< Bit 0 */
-#define  PWR_CR1_VOS_1                        0x00008000U     /*!< Bit 1 */
-#define  PWR_CR1_ODEN                         0x00010000U     /*!< Over Drive enable                   */
-#define  PWR_CR1_ODSWEN                       0x00020000U     /*!< Over Drive switch enabled           */
-#define  PWR_CR1_UDEN                         0x000C0000U     /*!< Under Drive enable in stop mode     */
-#define  PWR_CR1_UDEN_0                       0x00040000U     /*!< Bit 0                               */
-#define  PWR_CR1_UDEN_1                       0x00080000U     /*!< Bit 1                               */
-
-/*******************  Bit definition for PWR_CSR1 register  ********************/
-#define  PWR_CSR1_WUIF                        0x00000001U     /*!< Wake up internal Flag                            */
-#define  PWR_CSR1_SBF                         0x00000002U     /*!< Standby Flag                                     */
-#define  PWR_CSR1_PVDO                        0x00000004U     /*!< PVD Output                                       */
-#define  PWR_CSR1_BRR                         0x00000008U     /*!< Backup regulator ready                           */
-#define  PWR_CSR1_EIWUP                       0x00000100U     /*!< Enable internal wakeup                           */
-#define  PWR_CSR1_BRE                         0x00000200U     /*!< Backup regulator enable                          */
-#define  PWR_CSR1_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
-#define  PWR_CSR1_ODRDY                       0x00010000U     /*!< Over Drive generator ready                       */
-#define  PWR_CSR1_ODSWRDY                     0x00020000U     /*!< Over Drive Switch ready                          */
-#define  PWR_CSR1_UDRDY                       0x000C0000U     /*!< Under Drive ready                                */
-
-/* Legacy define */
-#define  PWR_CSR1_UDSWRDY                     PWR_CSR1_UDRDY
-
-/********************  Bit definition for PWR_CR2 register  ********************/
-#define  PWR_CR2_CWUPF1                         0x00000001U     /*!< Clear Wakeup Pin Flag for PA0      */
-#define  PWR_CR2_CWUPF2                         0x00000002U     /*!< Clear Wakeup Pin Flag for PA2      */
-#define  PWR_CR2_CWUPF3                         0x00000004U     /*!< Clear Wakeup Pin Flag for PC1      */
-#define  PWR_CR2_CWUPF4                         0x00000008U     /*!< Clear Wakeup Pin Flag for PC13     */
-#define  PWR_CR2_CWUPF5                         0x00000010U     /*!< Clear Wakeup Pin Flag for PI8      */
-#define  PWR_CR2_CWUPF6                         0x00000020U     /*!< Clear Wakeup Pin Flag for PI11     */
-#define  PWR_CR2_WUPP1                          0x00000100U     /*!< Wakeup Pin Polarity bit for PA0    */
-#define  PWR_CR2_WUPP2                          0x00000200U     /*!< Wakeup Pin Polarity bit for PA2    */
-#define  PWR_CR2_WUPP3                          0x00000400U     /*!< Wakeup Pin Polarity bit for PC1    */
-#define  PWR_CR2_WUPP4                          0x00000800U     /*!< Wakeup Pin Polarity bit for PC13   */
-#define  PWR_CR2_WUPP5                          0x00001000U     /*!< Wakeup Pin Polarity bit for PI8    */
-#define  PWR_CR2_WUPP6                          0x00002000U     /*!< Wakeup Pin Polarity bit for PI11   */
-
-/*******************  Bit definition for PWR_CSR2 register  ********************/
-#define  PWR_CSR2_WUPF1                         0x00000001U     /*!< Wakeup Pin Flag for PA0            */
-#define  PWR_CSR2_WUPF2                         0x00000002U     /*!< Wakeup Pin Flag for PA2            */
-#define  PWR_CSR2_WUPF3                         0x00000004U     /*!< Wakeup Pin Flag for PC1            */
-#define  PWR_CSR2_WUPF4                         0x00000008U     /*!< Wakeup Pin Flag for PC13           */
-#define  PWR_CSR2_WUPF5                         0x00000010U     /*!< Wakeup Pin Flag for PI8            */
-#define  PWR_CSR2_WUPF6                         0x00000020U     /*!< Wakeup Pin Flag for PI11           */
-#define  PWR_CSR2_EWUP1                         0x00000100U     /*!< Enable Wakeup Pin PA0              */
-#define  PWR_CSR2_EWUP2                         0x00000200U     /*!< Enable Wakeup Pin PA2              */
-#define  PWR_CSR2_EWUP3                         0x00000400U     /*!< Enable Wakeup Pin PC1              */
-#define  PWR_CSR2_EWUP4                         0x00000800U     /*!< Enable Wakeup Pin PC13             */
-#define  PWR_CSR2_EWUP5                         0x00001000U     /*!< Enable Wakeup Pin PI8              */
-#define  PWR_CSR2_EWUP6                         0x00002000U     /*!< Enable Wakeup Pin PI11             */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    QUADSPI                                 */
-/*                                                                            */
-/******************************************************************************/
-/* QUADSPI IP version */
-#define QSPI1_V1_0
-/*****************  Bit definition for QUADSPI_CR register  *******************/
-#define  QUADSPI_CR_EN                           0x00000001U            /*!< Enable                            */
-#define  QUADSPI_CR_ABORT                        0x00000002U            /*!< Abort request                     */
-#define  QUADSPI_CR_DMAEN                        0x00000004U            /*!< DMA Enable                        */
-#define  QUADSPI_CR_TCEN                         0x00000008U            /*!< Timeout Counter Enable            */
-#define  QUADSPI_CR_SSHIFT                       0x00000010U            /*!< Sample Shift                      */
-#define  QUADSPI_CR_DFM                          0x00000040U            /*!< Dual Flash Mode                   */
-#define  QUADSPI_CR_FSEL                         0x00000080U            /*!< Flash Select                      */
-#define  QUADSPI_CR_FTHRES                       0x00001F00U            /*!< FTHRES[4:0] FIFO Level            */
-#define  QUADSPI_CR_FTHRES_0                     0x00000100U            /*!< Bit 0 */
-#define  QUADSPI_CR_FTHRES_1                     0x00000200U            /*!< Bit 1 */
-#define  QUADSPI_CR_FTHRES_2                     0x00000400U            /*!< Bit 2 */
-#define  QUADSPI_CR_FTHRES_3                     0x00000800U            /*!< Bit 3 */
-#define  QUADSPI_CR_FTHRES_4                     0x00001000U            /*!< Bit 4 */
-#define  QUADSPI_CR_TEIE                         0x00010000U            /*!< Transfer Error Interrupt Enable    */
-#define  QUADSPI_CR_TCIE                         0x00020000U            /*!< Transfer Complete Interrupt Enable */
-#define  QUADSPI_CR_FTIE                         0x00040000U            /*!< FIFO Threshold Interrupt Enable    */
-#define  QUADSPI_CR_SMIE                         0x00080000U            /*!< Status Match Interrupt Enable      */
-#define  QUADSPI_CR_TOIE                         0x00100000U            /*!< TimeOut Interrupt Enable           */
-#define  QUADSPI_CR_APMS                         0x00400000U            /*!< Bit 1                              */
-#define  QUADSPI_CR_PMM                          0x00800000U            /*!< Polling Match Mode                 */
-#define  QUADSPI_CR_PRESCALER                    0xFF000000U            /*!< PRESCALER[7:0] Clock prescaler     */
-#define  QUADSPI_CR_PRESCALER_0                  0x01000000U            /*!< Bit 0 */
-#define  QUADSPI_CR_PRESCALER_1                  0x02000000U            /*!< Bit 1 */
-#define  QUADSPI_CR_PRESCALER_2                  0x04000000U            /*!< Bit 2 */
-#define  QUADSPI_CR_PRESCALER_3                  0x08000000U            /*!< Bit 3 */
-#define  QUADSPI_CR_PRESCALER_4                  0x10000000U            /*!< Bit 4 */
-#define  QUADSPI_CR_PRESCALER_5                  0x20000000U            /*!< Bit 5 */
-#define  QUADSPI_CR_PRESCALER_6                  0x40000000U            /*!< Bit 6 */
-#define  QUADSPI_CR_PRESCALER_7                  0x80000000U            /*!< Bit 7 */
-
-/*****************  Bit definition for QUADSPI_DCR register  ******************/
-#define  QUADSPI_DCR_CKMODE                      0x00000001U            /*!< Mode 0 / Mode 3                 */
-#define  QUADSPI_DCR_CSHT                        0x00000700U            /*!< CSHT[2:0]: ChipSelect High Time */
-#define  QUADSPI_DCR_CSHT_0                      0x00000100U            /*!< Bit 0 */
-#define  QUADSPI_DCR_CSHT_1                      0x00000200U            /*!< Bit 1 */
-#define  QUADSPI_DCR_CSHT_2                      0x00000400U            /*!< Bit 2 */
-#define  QUADSPI_DCR_FSIZE                       0x001F0000U            /*!< FSIZE[4:0]: Flash Size          */
-#define  QUADSPI_DCR_FSIZE_0                     0x00010000U            /*!< Bit 0 */
-#define  QUADSPI_DCR_FSIZE_1                     0x00020000U            /*!< Bit 1 */
-#define  QUADSPI_DCR_FSIZE_2                     0x00040000U            /*!< Bit 2 */
-#define  QUADSPI_DCR_FSIZE_3                     0x00080000U            /*!< Bit 3 */
-#define  QUADSPI_DCR_FSIZE_4                     0x00100000U            /*!< Bit 4 */
-
-/******************  Bit definition for QUADSPI_SR register  *******************/
-#define  QUADSPI_SR_TEF                          0x00000001U             /*!< Transfer Error Flag    */
-#define  QUADSPI_SR_TCF                          0x00000002U             /*!< Transfer Complete Flag */
-#define  QUADSPI_SR_FTF                          0x00000004U             /*!< FIFO Threshlod Flag    */
-#define  QUADSPI_SR_SMF                          0x00000008U             /*!< Status Match Flag      */
-#define  QUADSPI_SR_TOF                          0x00000010U             /*!< Timeout Flag           */
-#define  QUADSPI_SR_BUSY                         0x00000020U             /*!< Busy                   */
-#define  QUADSPI_SR_FLEVEL                       0x00001F00U             /*!< FIFO Threshlod Flag    */
-#define  QUADSPI_SR_FLEVEL_0                     0x00000100U             /*!< Bit 0 */
-#define  QUADSPI_SR_FLEVEL_1                     0x00000200U             /*!< Bit 1 */
-#define  QUADSPI_SR_FLEVEL_2                     0x00000400U             /*!< Bit 2 */
-#define  QUADSPI_SR_FLEVEL_3                     0x00000800U             /*!< Bit 3 */
-#define  QUADSPI_SR_FLEVEL_4                     0x00001000U             /*!< Bit 4 */
-
-/******************  Bit definition for QUADSPI_FCR register  ******************/
-#define  QUADSPI_FCR_CTEF                        0x00000001U             /*!< Clear Transfer Error Flag    */
-#define  QUADSPI_FCR_CTCF                        0x00000002U             /*!< Clear Transfer Complete Flag */
-#define  QUADSPI_FCR_CSMF                        0x00000008U             /*!< Clear Status Match Flag      */
-#define  QUADSPI_FCR_CTOF                        0x00000010U             /*!< Clear Timeout Flag           */
-
-/******************  Bit definition for QUADSPI_DLR register  ******************/
-#define  QUADSPI_DLR_DL                          0xFFFFFFFFU             /*!< DL[31:0]: Data Length */
-
-/******************  Bit definition for QUADSPI_CCR register  ******************/
-#define  QUADSPI_CCR_INSTRUCTION                  0x000000FFU            /*!< INSTRUCTION[7:0]: Instruction    */
-#define  QUADSPI_CCR_INSTRUCTION_0                0x00000001U            /*!< Bit 0 */
-#define  QUADSPI_CCR_INSTRUCTION_1                0x00000002U            /*!< Bit 1 */
-#define  QUADSPI_CCR_INSTRUCTION_2                0x00000004U            /*!< Bit 2 */
-#define  QUADSPI_CCR_INSTRUCTION_3                0x00000008U            /*!< Bit 3 */
-#define  QUADSPI_CCR_INSTRUCTION_4                0x00000010U            /*!< Bit 4 */
-#define  QUADSPI_CCR_INSTRUCTION_5                0x00000020U            /*!< Bit 5 */
-#define  QUADSPI_CCR_INSTRUCTION_6                0x00000040U            /*!< Bit 6 */
-#define  QUADSPI_CCR_INSTRUCTION_7                0x00000080U            /*!< Bit 7 */
-#define  QUADSPI_CCR_IMODE                        0x00000300U            /*!< IMODE[1:0]: Instruction Mode      */
-#define  QUADSPI_CCR_IMODE_0                      0x00000100U            /*!< Bit 0 */
-#define  QUADSPI_CCR_IMODE_1                      0x00000200U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ADMODE                       0x00000C00U            /*!< ADMODE[1:0]: Address Mode         */
-#define  QUADSPI_CCR_ADMODE_0                     0x00000400U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ADMODE_1                     0x00000800U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ADSIZE                       0x00003000U            /*!< ADSIZE[1:0]: Address Size         */
-#define  QUADSPI_CCR_ADSIZE_0                     0x00001000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ADSIZE_1                     0x00002000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ABMODE                       0x0000C000U            /*!< ABMODE[1:0]: Alternate Bytes Mode */
-#define  QUADSPI_CCR_ABMODE_0                     0x00004000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ABMODE_1                     0x00008000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ABSIZE                       0x00030000U            /*!< ABSIZE[1:0]: Instruction Mode     */
-#define  QUADSPI_CCR_ABSIZE_0                     0x00010000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ABSIZE_1                     0x00020000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_DCYC                         0x007C0000U            /*!< DCYC[4:0]: Dummy Cycles           */
-#define  QUADSPI_CCR_DCYC_0                       0x00040000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_DCYC_1                       0x00080000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_DCYC_2                       0x00100000U            /*!< Bit 2 */
-#define  QUADSPI_CCR_DCYC_3                       0x00200000U            /*!< Bit 3 */
-#define  QUADSPI_CCR_DCYC_4                       0x00400000U            /*!< Bit 4 */
-#define  QUADSPI_CCR_DMODE                        0x03000000U            /*!< DMODE[1:0]: Data Mode              */
-#define  QUADSPI_CCR_DMODE_0                      0x01000000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_DMODE_1                      0x02000000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_FMODE                        0x0C000000U            /*!< FMODE[1:0]: Functional Mode        */
-#define  QUADSPI_CCR_FMODE_0                      0x04000000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_FMODE_1                      0x08000000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_SIOO                         0x10000000U            /*!< SIOO: Send Instruction Only Once Mode */
-#define  QUADSPI_CCR_DHHC                         0x40000000U            /*!< DHHC: Delay Half Hclk Cycle           */
-#define  QUADSPI_CCR_DDRM                         0x80000000U            /*!< DDRM: Double Data Rate Mode           */
-/******************  Bit definition for QUADSPI_AR register  *******************/
-#define  QUADSPI_AR_ADDRESS                       0xFFFFFFFFU            /*!< ADDRESS[31:0]: Address */
-
-/******************  Bit definition for QUADSPI_ABR register  ******************/
-#define  QUADSPI_ABR_ALTERNATE                    0xFFFFFFFFU            /*!< ALTERNATE[31:0]: Alternate Bytes */
-
-/******************  Bit definition for QUADSPI_DR register  *******************/
-#define  QUADSPI_DR_DATA                          0xFFFFFFFFU            /*!< DATA[31:0]: Data */
-
-/******************  Bit definition for QUADSPI_PSMKR register  ****************/
-#define  QUADSPI_PSMKR_MASK                       0xFFFFFFFFU            /*!< MASK[31:0]: Status Mask */
-
-/******************  Bit definition for QUADSPI_PSMAR register  ****************/
-#define  QUADSPI_PSMAR_MATCH                      0xFFFFFFFFU            /*!< MATCH[31:0]: Status Match */
-
-/******************  Bit definition for QUADSPI_PIR register  *****************/
-#define  QUADSPI_PIR_INTERVAL                     0x0000FFFFU            /*!< INTERVAL[15:0]: Polling Interval */
-
-/******************  Bit definition for QUADSPI_LPTR register  *****************/
-#define  QUADSPI_LPTR_TIMEOUT                     0x0000FFFFU            /*!< TIMEOUT[15:0]: Timeout period */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        0x00000001U
-#define  RCC_CR_HSIRDY                       0x00000002U
-#define  RCC_CR_HSITRIM                      0x000000F8U
-#define  RCC_CR_HSITRIM_0                    0x00000008U /*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    0x00000010U /*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    0x00000020U /*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    0x00000040U /*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    0x00000080U /*!<Bit 4 */
-#define  RCC_CR_HSICAL                       0x0000FF00U
-#define  RCC_CR_HSICAL_0                     0x00000100U /*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     0x00000200U /*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     0x00000400U /*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     0x00000800U /*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     0x00001000U /*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     0x00002000U /*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     0x00004000U /*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     0x00008000U /*!<Bit 7 */
-#define  RCC_CR_HSEON                        0x00010000U
-#define  RCC_CR_HSERDY                       0x00020000U
-#define  RCC_CR_HSEBYP                       0x00040000U
-#define  RCC_CR_CSSON                        0x00080000U
-#define  RCC_CR_PLLON                        0x01000000U
-#define  RCC_CR_PLLRDY                       0x02000000U
-#define  RCC_CR_PLLI2SON                     0x04000000U
-#define  RCC_CR_PLLI2SRDY                    0x08000000U
-#define  RCC_CR_PLLSAION                     0x10000000U
-#define  RCC_CR_PLLSAIRDY                    0x20000000U
-
-/********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    0x0000003FU
-#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
-#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
-#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
-#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
-#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
-#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
-#define  RCC_PLLCFGR_PLLN                    0x00007FC0U
-#define  RCC_PLLCFGR_PLLN_0                  0x00000040U
-#define  RCC_PLLCFGR_PLLN_1                  0x00000080U
-#define  RCC_PLLCFGR_PLLN_2                  0x00000100U
-#define  RCC_PLLCFGR_PLLN_3                  0x00000200U
-#define  RCC_PLLCFGR_PLLN_4                  0x00000400U
-#define  RCC_PLLCFGR_PLLN_5                  0x00000800U
-#define  RCC_PLLCFGR_PLLN_6                  0x00001000U
-#define  RCC_PLLCFGR_PLLN_7                  0x00002000U
-#define  RCC_PLLCFGR_PLLN_8                  0x00004000U
-#define  RCC_PLLCFGR_PLLP                    0x00030000U
-#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
-#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
-#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
-#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
-#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
-#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
-#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
-#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
-
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-/*!< SW configuration */
-#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
-#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
-#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
-
-#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
-
-/*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     0x001F0000U
-#define  RCC_CFGR_RTCPRE_0                   0x00010000U
-#define  RCC_CFGR_RTCPRE_1                   0x00020000U
-#define  RCC_CFGR_RTCPRE_2                   0x00040000U
-#define  RCC_CFGR_RTCPRE_3                   0x00080000U
-#define  RCC_CFGR_RTCPRE_4                   0x00100000U
-
-/*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       0x00600000U
-#define  RCC_CFGR_MCO1_0                     0x00200000U
-#define  RCC_CFGR_MCO1_1                     0x00400000U
-
-#define  RCC_CFGR_I2SSRC                     0x00800000U
-
-#define  RCC_CFGR_MCO1PRE                    0x07000000U
-#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
-#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
-#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
-
-#define  RCC_CFGR_MCO2PRE                    0x38000000U
-#define  RCC_CFGR_MCO2PRE_0                  0x08000000U
-#define  RCC_CFGR_MCO2PRE_1                  0x10000000U
-#define  RCC_CFGR_MCO2PRE_2                  0x20000000U
-
-#define  RCC_CFGR_MCO2                       0xC0000000U
-#define  RCC_CFGR_MCO2_0                     0x40000000U
-#define  RCC_CFGR_MCO2_1                     0x80000000U
-
-/********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     0x00000001U
-#define  RCC_CIR_LSERDYF                     0x00000002U
-#define  RCC_CIR_HSIRDYF                     0x00000004U
-#define  RCC_CIR_HSERDYF                     0x00000008U
-#define  RCC_CIR_PLLRDYF                     0x00000010U
-#define  RCC_CIR_PLLI2SRDYF                  0x00000020U
-#define  RCC_CIR_PLLSAIRDYF                  0x00000040U
-#define  RCC_CIR_CSSF                        0x00000080U
-#define  RCC_CIR_LSIRDYIE                    0x00000100U
-#define  RCC_CIR_LSERDYIE                    0x00000200U
-#define  RCC_CIR_HSIRDYIE                    0x00000400U
-#define  RCC_CIR_HSERDYIE                    0x00000800U
-#define  RCC_CIR_PLLRDYIE                    0x00001000U
-#define  RCC_CIR_PLLI2SRDYIE                 0x00002000U
-#define  RCC_CIR_PLLSAIRDYIE                 0x00004000U
-#define  RCC_CIR_LSIRDYC                     0x00010000U
-#define  RCC_CIR_LSERDYC                     0x00020000U
-#define  RCC_CIR_HSIRDYC                     0x00040000U
-#define  RCC_CIR_HSERDYC                     0x00080000U
-#define  RCC_CIR_PLLRDYC                     0x00100000U
-#define  RCC_CIR_PLLI2SRDYC                  0x00200000U
-#define  RCC_CIR_PLLSAIRDYC                  0x00400000U
-#define  RCC_CIR_CSSC                        0x00800000U
-
-/********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
-#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
-#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
-#define  RCC_AHB1RSTR_GPIODRST               0x00000008U
-#define  RCC_AHB1RSTR_GPIOERST               0x00000010U
-#define  RCC_AHB1RSTR_GPIOFRST               0x00000020U
-#define  RCC_AHB1RSTR_GPIOGRST               0x00000040U
-#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
-#define  RCC_AHB1RSTR_GPIOIRST               0x00000100U
-#define  RCC_AHB1RSTR_GPIOJRST               0x00000200U
-#define  RCC_AHB1RSTR_GPIOKRST               0x00000400U
-#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
-#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
-#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
-#define  RCC_AHB1RSTR_DMA2DRST               0x00800000U
-#define  RCC_AHB1RSTR_ETHMACRST              0x02000000U
-#define  RCC_AHB1RSTR_OTGHRST                0x20000000U
-
-/********************  Bit definition for RCC_AHB2RSTR register  **************/
-#define  RCC_AHB2RSTR_DCMIRST                0x00000001U
-#define  RCC_AHB2RSTR_RNGRST                 0x00000040U
-#define  RCC_AHB2RSTR_OTGFSRST               0x00000080U
-
-/********************  Bit definition for RCC_AHB3RSTR register  **************/
-
-#define  RCC_AHB3RSTR_FMCRST                 0x00000001U
-#define  RCC_AHB3RSTR_QSPIRST                0x00000002U
-
-/********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM2RST                0x00000001U
-#define  RCC_APB1RSTR_TIM3RST                0x00000002U
-#define  RCC_APB1RSTR_TIM4RST                0x00000004U
-#define  RCC_APB1RSTR_TIM5RST                0x00000008U
-#define  RCC_APB1RSTR_TIM6RST                0x00000010U
-#define  RCC_APB1RSTR_TIM7RST                0x00000020U
-#define  RCC_APB1RSTR_TIM12RST               0x00000040U
-#define  RCC_APB1RSTR_TIM13RST               0x00000080U
-#define  RCC_APB1RSTR_TIM14RST               0x00000100U
-#define  RCC_APB1RSTR_LPTIM1RST              0x00000200U
-#define  RCC_APB1RSTR_WWDGRST                0x00000800U
-#define  RCC_APB1RSTR_SPI2RST                0x00004000U
-#define  RCC_APB1RSTR_SPI3RST                0x00008000U
-#define  RCC_APB1RSTR_SPDIFRXRST             0x00010000U
-#define  RCC_APB1RSTR_USART2RST              0x00020000U
-#define  RCC_APB1RSTR_USART3RST              0x00040000U
-#define  RCC_APB1RSTR_UART4RST               0x00080000U
-#define  RCC_APB1RSTR_UART5RST               0x00100000U
-#define  RCC_APB1RSTR_I2C1RST                0x00200000U
-#define  RCC_APB1RSTR_I2C2RST                0x00400000U
-#define  RCC_APB1RSTR_I2C3RST                0x00800000U
-#define  RCC_APB1RSTR_I2C4RST                0x01000000U
-#define  RCC_APB1RSTR_CAN1RST                0x02000000U
-#define  RCC_APB1RSTR_CAN2RST                0x04000000U
-#define  RCC_APB1RSTR_CECRST                 0x08000000U
-#define  RCC_APB1RSTR_PWRRST                 0x10000000U
-#define  RCC_APB1RSTR_DACRST                 0x20000000U
-#define  RCC_APB1RSTR_UART7RST               0x40000000U
-#define  RCC_APB1RSTR_UART8RST               0x80000000U
-
-/********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                0x00000001U
-#define  RCC_APB2RSTR_TIM8RST                0x00000002U
-#define  RCC_APB2RSTR_USART1RST              0x00000010U
-#define  RCC_APB2RSTR_USART6RST              0x00000020U
-#define  RCC_APB2RSTR_ADCRST                 0x00000100U
-#define  RCC_APB2RSTR_SDMMC1RST              0x00000800U
-#define  RCC_APB2RSTR_SPI1RST                0x00001000U
-#define  RCC_APB2RSTR_SPI4RST                0x00002000U
-#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
-#define  RCC_APB2RSTR_TIM9RST                0x00010000U
-#define  RCC_APB2RSTR_TIM10RST               0x00020000U
-#define  RCC_APB2RSTR_TIM11RST               0x00040000U
-#define  RCC_APB2RSTR_SPI5RST                0x00100000U
-#define  RCC_APB2RSTR_SPI6RST                0x00200000U
-#define  RCC_APB2RSTR_SAI1RST                0x00400000U
-#define  RCC_APB2RSTR_SAI2RST                0x00800000U
-
-/********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
-#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
-#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
-#define  RCC_AHB1ENR_GPIODEN                 0x00000008U
-#define  RCC_AHB1ENR_GPIOEEN                 0x00000010U
-#define  RCC_AHB1ENR_GPIOFEN                 0x00000020U
-#define  RCC_AHB1ENR_GPIOGEN                 0x00000040U
-#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
-#define  RCC_AHB1ENR_GPIOIEN                 0x00000100U
-#define  RCC_AHB1ENR_GPIOJEN                 0x00000200U
-#define  RCC_AHB1ENR_GPIOKEN                 0x00000400U
-#define  RCC_AHB1ENR_CRCEN                   0x00001000U
-#define  RCC_AHB1ENR_BKPSRAMEN               0x00040000U
-#define  RCC_AHB1ENR_DTCMRAMEN               0x00100000U
-#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
-#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
-#define  RCC_AHB1ENR_DMA2DEN                 0x00800000U
-#define  RCC_AHB1ENR_ETHMACEN                0x02000000U
-#define  RCC_AHB1ENR_ETHMACTXEN              0x04000000U
-#define  RCC_AHB1ENR_ETHMACRXEN              0x08000000U
-#define  RCC_AHB1ENR_ETHMACPTPEN             0x10000000U
-#define  RCC_AHB1ENR_OTGHSEN                 0x20000000U
-#define  RCC_AHB1ENR_OTGHSULPIEN             0x40000000U
-
-/********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define  RCC_AHB2ENR_DCMIEN                  0x00000001U
-#define  RCC_AHB2ENR_RNGEN                   0x00000040U
-#define  RCC_AHB2ENR_OTGFSEN                 0x00000080U
-
-/********************  Bit definition for RCC_AHB3ENR register  ***************/
-#define  RCC_AHB3ENR_FMCEN                  0x00000001U
-#define  RCC_AHB3ENR_QSPIEN                 0x00000002U
-
-/********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM2EN                  0x00000001U
-#define  RCC_APB1ENR_TIM3EN                  0x00000002U
-#define  RCC_APB1ENR_TIM4EN                  0x00000004U
-#define  RCC_APB1ENR_TIM5EN                  0x00000008U
-#define  RCC_APB1ENR_TIM6EN                  0x00000010U
-#define  RCC_APB1ENR_TIM7EN                  0x00000020U
-#define  RCC_APB1ENR_TIM12EN                 0x00000040U
-#define  RCC_APB1ENR_TIM13EN                 0x00000080U
-#define  RCC_APB1ENR_TIM14EN                 0x00000100U
-#define  RCC_APB1ENR_LPTIM1EN                0x00000200U
-#define  RCC_APB1ENR_WWDGEN                  0x00000800U
-#define  RCC_APB1ENR_SPI2EN                  0x00004000U
-#define  RCC_APB1ENR_SPI3EN                  0x00008000U
-#define  RCC_APB1ENR_SPDIFRXEN               0x00010000U
-#define  RCC_APB1ENR_USART2EN                0x00020000U
-#define  RCC_APB1ENR_USART3EN                0x00040000U
-#define  RCC_APB1ENR_UART4EN                 0x00080000U
-#define  RCC_APB1ENR_UART5EN                 0x00100000U
-#define  RCC_APB1ENR_I2C1EN                  0x00200000U
-#define  RCC_APB1ENR_I2C2EN                  0x00400000U
-#define  RCC_APB1ENR_I2C3EN                  0x00800000U
-#define  RCC_APB1ENR_I2C4EN                  0x01000000U
-#define  RCC_APB1ENR_CAN1EN                  0x02000000U
-#define  RCC_APB1ENR_CAN2EN                  0x04000000U
-#define  RCC_APB1ENR_CECEN                   0x08000000U
-#define  RCC_APB1ENR_PWREN                   0x10000000U
-#define  RCC_APB1ENR_DACEN                   0x20000000U
-#define  RCC_APB1ENR_UART7EN                 0x40000000U
-#define  RCC_APB1ENR_UART8EN                 0x80000000U
-
-/********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  0x00000001U
-#define  RCC_APB2ENR_TIM8EN                  0x00000002U
-#define  RCC_APB2ENR_USART1EN                0x00000010U
-#define  RCC_APB2ENR_USART6EN                0x00000020U
-#define  RCC_APB2ENR_ADC1EN                  0x00000100U
-#define  RCC_APB2ENR_ADC2EN                  0x00000200U
-#define  RCC_APB2ENR_ADC3EN                  0x00000400U
-#define  RCC_APB2ENR_SDMMC1EN                0x00000800U
-#define  RCC_APB2ENR_SPI1EN                  0x00001000U
-#define  RCC_APB2ENR_SPI4EN                  0x00002000U
-#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
-#define  RCC_APB2ENR_TIM9EN                  0x00010000U
-#define  RCC_APB2ENR_TIM10EN                 0x00020000U
-#define  RCC_APB2ENR_TIM11EN                 0x00040000U
-#define  RCC_APB2ENR_SPI5EN                  0x00100000U
-#define  RCC_APB2ENR_SPI6EN                  0x00200000U
-#define  RCC_APB2ENR_SAI1EN                  0x00400000U
-#define  RCC_APB2ENR_SAI2EN                  0x00800000U
-
-/********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
-#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
-#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
-#define  RCC_AHB1LPENR_GPIODLPEN             0x00000008U
-#define  RCC_AHB1LPENR_GPIOELPEN             0x00000010U
-#define  RCC_AHB1LPENR_GPIOFLPEN             0x00000020U
-#define  RCC_AHB1LPENR_GPIOGLPEN             0x00000040U
-#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
-#define  RCC_AHB1LPENR_GPIOILPEN             0x00000100U
-#define  RCC_AHB1LPENR_GPIOJLPEN             0x00000200U
-#define  RCC_AHB1LPENR_GPIOKLPEN             0x00000400U
-#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
-#define  RCC_AHB1LPENR_AXILPEN               0x00002000U
-#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
-#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
-#define  RCC_AHB1LPENR_SRAM2LPEN             0x00020000U
-#define  RCC_AHB1LPENR_BKPSRAMLPEN           0x00040000U
-#define  RCC_AHB1LPENR_DTCMLPEN              0x00100000U
-#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
-#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
-#define  RCC_AHB1LPENR_DMA2DLPEN             0x00800000U
-#define  RCC_AHB1LPENR_ETHMACLPEN            0x02000000U
-#define  RCC_AHB1LPENR_ETHMACTXLPEN          0x04000000U
-#define  RCC_AHB1LPENR_ETHMACRXLPEN          0x08000000U
-#define  RCC_AHB1LPENR_ETHMACPTPLPEN         0x10000000U
-#define  RCC_AHB1LPENR_OTGHSLPEN             0x20000000U
-#define  RCC_AHB1LPENR_OTGHSULPILPEN         0x40000000U
-
-/********************  Bit definition for RCC_AHB2LPENR register  *************/
-#define  RCC_AHB2LPENR_DCMILPEN              0x00000001U
-#define  RCC_AHB2LPENR_RNGLPEN               0x00000040U
-#define  RCC_AHB2LPENR_OTGFSLPEN             0x00000080U
-
-/********************  Bit definition for RCC_AHB3LPENR register  *************/
-#define  RCC_AHB3LPENR_FMCLPEN               0x00000001U
-#define  RCC_AHB3LPENR_QSPILPEN              0x00000002U
-/********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM2LPEN              0x00000001U
-#define  RCC_APB1LPENR_TIM3LPEN              0x00000002U
-#define  RCC_APB1LPENR_TIM4LPEN              0x00000004U
-#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
-#define  RCC_APB1LPENR_TIM6LPEN              0x00000010U
-#define  RCC_APB1LPENR_TIM7LPEN              0x00000020U
-#define  RCC_APB1LPENR_TIM12LPEN             0x00000040U
-#define  RCC_APB1LPENR_TIM13LPEN             0x00000080U
-#define  RCC_APB1LPENR_TIM14LPEN             0x00000100U
-#define  RCC_APB1LPENR_LPTIM1LPEN            0x00000200U
-#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
-#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U
-#define  RCC_APB1LPENR_SPI3LPEN              0x00008000U
-#define  RCC_APB1LPENR_SPDIFRXLPEN           0x00010000U
-#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
-#define  RCC_APB1LPENR_USART3LPEN            0x00040000U
-#define  RCC_APB1LPENR_UART4LPEN             0x00080000U
-#define  RCC_APB1LPENR_UART5LPEN             0x00100000U
-#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
-#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
-#define  RCC_APB1LPENR_I2C3LPEN              0x00800000U
-#define  RCC_APB1LPENR_I2C4LPEN              0x01000000U
-#define  RCC_APB1LPENR_CAN1LPEN              0x02000000U
-#define  RCC_APB1LPENR_CAN2LPEN              0x04000000U
-#define  RCC_APB1LPENR_CECLPEN               0x08000000U
-#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
-#define  RCC_APB1LPENR_DACLPEN               0x20000000U
-#define  RCC_APB1LPENR_UART7LPEN             0x40000000U
-#define  RCC_APB1LPENR_UART8LPEN             0x80000000U
-
-/********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
-#define  RCC_APB2LPENR_TIM8LPEN              0x00000002U
-#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
-#define  RCC_APB2LPENR_USART6LPEN            0x00000020U
-#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
-#define  RCC_APB2LPENR_ADC2LPEN              0x00000200U
-#define  RCC_APB2LPENR_ADC3LPEN              0x00000400U
-#define  RCC_APB2LPENR_SDMMC1LPEN            0x00000800U
-#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
-#define  RCC_APB2LPENR_SPI4LPEN              0x00002000U
-#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
-#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
-#define  RCC_APB2LPENR_TIM10LPEN             0x00020000U
-#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
-#define  RCC_APB2LPENR_SPI5LPEN              0x00100000U
-#define  RCC_APB2LPENR_SPI6LPEN              0x00200000U
-#define  RCC_APB2LPENR_SAI1LPEN              0x00400000U
-#define  RCC_APB2LPENR_SAI2LPEN              0x00800000U
-
-/********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      0x00000001U
-#define  RCC_BDCR_LSERDY                     0x00000002U
-#define  RCC_BDCR_LSEBYP                     0x00000004U
-#define  RCC_BDCR_LSEDRV                     0x00000018U
-#define  RCC_BDCR_LSEDRV_0                   0x00000008U
-#define  RCC_BDCR_LSEDRV_1                   0x00000010U
-#define  RCC_BDCR_RTCSEL                     0x00000300U
-#define  RCC_BDCR_RTCSEL_0                   0x00000100U
-#define  RCC_BDCR_RTCSEL_1                   0x00000200U
-#define  RCC_BDCR_RTCEN                      0x00008000U
-#define  RCC_BDCR_BDRST                      0x00010000U
-
-/********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       0x00000001U
-#define  RCC_CSR_LSIRDY                      0x00000002U
-#define  RCC_CSR_RMVF                        0x01000000U
-#define  RCC_CSR_BORRSTF                     0x02000000U
-#define  RCC_CSR_PINRSTF                     0x04000000U
-#define  RCC_CSR_PORRSTF                     0x08000000U
-#define  RCC_CSR_SFTRSTF                     0x10000000U
-#define  RCC_CSR_IWDGRSTF                    0x20000000U
-#define  RCC_CSR_WWDGRSTF                    0x40000000U
-#define  RCC_CSR_LPWRRSTF                    0x80000000U
-
-/********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    0x00001FFFU
-#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
-#define  RCC_SSCGR_SPREADSEL                 0x40000000U
-#define  RCC_SSCGR_SSCGEN                    0x80000000U
-
-/********************  Bit definition for RCC_PLLI2SCFGR register  ************/
-#define  RCC_PLLI2SCFGR_PLLI2SN              0x00007FC0U
-#define  RCC_PLLI2SCFGR_PLLI2SN_0            0x00000040U
-#define  RCC_PLLI2SCFGR_PLLI2SN_1            0x00000080U
-#define  RCC_PLLI2SCFGR_PLLI2SN_2            0x00000100U
-#define  RCC_PLLI2SCFGR_PLLI2SN_3            0x00000200U
-#define  RCC_PLLI2SCFGR_PLLI2SN_4            0x00000400U
-#define  RCC_PLLI2SCFGR_PLLI2SN_5            0x00000800U
-#define  RCC_PLLI2SCFGR_PLLI2SN_6            0x00001000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_7            0x00002000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_8            0x00004000U
-#define  RCC_PLLI2SCFGR_PLLI2SP              0x00030000U
-#define  RCC_PLLI2SCFGR_PLLI2SP_0            0x00010000U
-#define  RCC_PLLI2SCFGR_PLLI2SP_1            0x00020000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ              0x0F000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_0            0x01000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_1            0x02000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_2            0x04000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_3            0x08000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR              0x70000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_0            0x10000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_1            0x20000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_2            0x40000000U
-
-/********************  Bit definition for RCC_PLLSAICFGR register  ************/
-#define  RCC_PLLSAICFGR_PLLSAIN              0x00007FC0U
-#define  RCC_PLLSAICFGR_PLLSAIN_0            0x00000040U
-#define  RCC_PLLSAICFGR_PLLSAIN_1            0x00000080U
-#define  RCC_PLLSAICFGR_PLLSAIN_2            0x00000100U
-#define  RCC_PLLSAICFGR_PLLSAIN_3            0x00000200U
-#define  RCC_PLLSAICFGR_PLLSAIN_4            0x00000400U
-#define  RCC_PLLSAICFGR_PLLSAIN_5            0x00000800U
-#define  RCC_PLLSAICFGR_PLLSAIN_6            0x00001000U
-#define  RCC_PLLSAICFGR_PLLSAIN_7            0x00002000U
-#define  RCC_PLLSAICFGR_PLLSAIN_8            0x00004000U
-#define  RCC_PLLSAICFGR_PLLSAIP              0x00030000U
-#define  RCC_PLLSAICFGR_PLLSAIP_0            0x00010000U
-#define  RCC_PLLSAICFGR_PLLSAIP_1            0x00020000U
-#define  RCC_PLLSAICFGR_PLLSAIQ              0x0F000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_0            0x01000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_1            0x02000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_2            0x04000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_3            0x08000000U
-#define  RCC_PLLSAICFGR_PLLSAIR              0x70000000U
-#define  RCC_PLLSAICFGR_PLLSAIR_0            0x10000000U
-#define  RCC_PLLSAICFGR_PLLSAIR_1            0x20000000U
-#define  RCC_PLLSAICFGR_PLLSAIR_2            0x40000000U
-
-/********************  Bit definition for RCC_DCKCFGR1 register  ***************/
-#define  RCC_DCKCFGR1_PLLI2SDIVQ             0x0000001FU
-#define  RCC_DCKCFGR1_PLLI2SDIVQ_0           0x00000001U
-#define  RCC_DCKCFGR1_PLLI2SDIVQ_1           0x00000002U
-#define  RCC_DCKCFGR1_PLLI2SDIVQ_2           0x00000004U
-#define  RCC_DCKCFGR1_PLLI2SDIVQ_3           0x00000008U
-#define  RCC_DCKCFGR1_PLLI2SDIVQ_4           0x00000010U
-
-#define  RCC_DCKCFGR1_PLLSAIDIVQ             0x00001F00U
-#define  RCC_DCKCFGR1_PLLSAIDIVQ_0           0x00000100U
-#define  RCC_DCKCFGR1_PLLSAIDIVQ_1           0x00000200U
-#define  RCC_DCKCFGR1_PLLSAIDIVQ_2           0x00000400U
-#define  RCC_DCKCFGR1_PLLSAIDIVQ_3           0x00000800U
-#define  RCC_DCKCFGR1_PLLSAIDIVQ_4           0x00001000U
-
-#define  RCC_DCKCFGR1_PLLSAIDIVR             0x00030000U
-#define  RCC_DCKCFGR1_PLLSAIDIVR_0           0x00010000U
-#define  RCC_DCKCFGR1_PLLSAIDIVR_1           0x00020000U
-
-#define  RCC_DCKCFGR1_SAI1SEL                0x00300000U
-#define  RCC_DCKCFGR1_SAI1SEL_0              0x00100000U
-#define  RCC_DCKCFGR1_SAI1SEL_1              0x00200000U
-
-#define  RCC_DCKCFGR1_SAI2SEL                0x00C00000U
-#define  RCC_DCKCFGR1_SAI2SEL_0              0x00400000U
-#define  RCC_DCKCFGR1_SAI2SEL_1              0x00800000U
-
-#define  RCC_DCKCFGR1_TIMPRE                 0x01000000U
-
-/********************  Bit definition for RCC_DCKCFGR2 register  ***************/
-#define  RCC_DCKCFGR2_USART1SEL              0x00000003U
-#define  RCC_DCKCFGR2_USART1SEL_0            0x00000001U
-#define  RCC_DCKCFGR2_USART1SEL_1            0x00000002U
-#define  RCC_DCKCFGR2_USART2SEL              0x0000000CU
-#define  RCC_DCKCFGR2_USART2SEL_0            0x00000004U
-#define  RCC_DCKCFGR2_USART2SEL_1            0x00000008U
-#define  RCC_DCKCFGR2_USART3SEL              0x00000030U
-#define  RCC_DCKCFGR2_USART3SEL_0            0x00000010U
-#define  RCC_DCKCFGR2_USART3SEL_1            0x00000020U
-#define  RCC_DCKCFGR2_UART4SEL               0x000000C0U
-#define  RCC_DCKCFGR2_UART4SEL_0             0x00000040U
-#define  RCC_DCKCFGR2_UART4SEL_1             0x00000080U
-#define  RCC_DCKCFGR2_UART5SEL               0x00000300U
-#define  RCC_DCKCFGR2_UART5SEL_0             0x00000100U
-#define  RCC_DCKCFGR2_UART5SEL_1             0x00000200U
-#define  RCC_DCKCFGR2_USART6SEL              0x00000C00U
-#define  RCC_DCKCFGR2_USART6SEL_0            0x00000400U
-#define  RCC_DCKCFGR2_USART6SEL_1            0x00000800U
-#define  RCC_DCKCFGR2_UART7SEL               0x00003000U
-#define  RCC_DCKCFGR2_UART7SEL_0             0x00001000U
-#define  RCC_DCKCFGR2_UART7SEL_1             0x00002000U
-#define  RCC_DCKCFGR2_UART8SEL               0x0000C000U
-#define  RCC_DCKCFGR2_UART8SEL_0             0x00004000U
-#define  RCC_DCKCFGR2_UART8SEL_1             0x00008000U
-#define  RCC_DCKCFGR2_I2C1SEL                0x00030000U
-#define  RCC_DCKCFGR2_I2C1SEL_0              0x00010000U
-#define  RCC_DCKCFGR2_I2C1SEL_1              0x00020000U
-#define  RCC_DCKCFGR2_I2C2SEL                0x000C0000U
-#define  RCC_DCKCFGR2_I2C2SEL_0              0x00040000U
-#define  RCC_DCKCFGR2_I2C2SEL_1              0x00080000U
-#define  RCC_DCKCFGR2_I2C3SEL                0x00300000U
-#define  RCC_DCKCFGR2_I2C3SEL_0              0x00100000U
-#define  RCC_DCKCFGR2_I2C3SEL_1              0x00200000U
-#define  RCC_DCKCFGR2_I2C4SEL                0x00C00000U
-#define  RCC_DCKCFGR2_I2C4SEL_0              0x00400000U
-#define  RCC_DCKCFGR2_I2C4SEL_1              0x00800000U
-#define  RCC_DCKCFGR2_LPTIM1SEL              0x03000000U
-#define  RCC_DCKCFGR2_LPTIM1SEL_0            0x01000000U
-#define  RCC_DCKCFGR2_LPTIM1SEL_1            0x02000000U
-#define  RCC_DCKCFGR2_CECSEL                 0x04000000U
-#define  RCC_DCKCFGR2_CK48MSEL               0x08000000U
-#define  RCC_DCKCFGR2_SDMMC1SEL              0x10000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    RNG                                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN                         0x00000004U
-#define RNG_CR_IE                            0x00000008U
-
-/********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY                          0x00000001U
-#define RNG_SR_CECS                          0x00000002U
-#define RNG_SR_SECS                          0x00000004U
-#define RNG_SR_CEIS                          0x00000020U
-#define RNG_SR_SEIS                          0x00000040U
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            0x00400000U
-#define RTC_TR_HT                            0x00300000U
-#define RTC_TR_HT_0                          0x00100000U
-#define RTC_TR_HT_1                          0x00200000U
-#define RTC_TR_HU                            0x000F0000U
-#define RTC_TR_HU_0                          0x00010000U
-#define RTC_TR_HU_1                          0x00020000U
-#define RTC_TR_HU_2                          0x00040000U
-#define RTC_TR_HU_3                          0x00080000U
-#define RTC_TR_MNT                           0x00007000U
-#define RTC_TR_MNT_0                         0x00001000U
-#define RTC_TR_MNT_1                         0x00002000U
-#define RTC_TR_MNT_2                         0x00004000U
-#define RTC_TR_MNU                           0x00000F00U
-#define RTC_TR_MNU_0                         0x00000100U
-#define RTC_TR_MNU_1                         0x00000200U
-#define RTC_TR_MNU_2                         0x00000400U
-#define RTC_TR_MNU_3                         0x00000800U
-#define RTC_TR_ST                            0x00000070U
-#define RTC_TR_ST_0                          0x00000010U
-#define RTC_TR_ST_1                          0x00000020U
-#define RTC_TR_ST_2                          0x00000040U
-#define RTC_TR_SU                            0x0000000FU
-#define RTC_TR_SU_0                          0x00000001U
-#define RTC_TR_SU_1                          0x00000002U
-#define RTC_TR_SU_2                          0x00000004U
-#define RTC_TR_SU_3                          0x00000008U
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            0x00F00000U
-#define RTC_DR_YT_0                          0x00100000U
-#define RTC_DR_YT_1                          0x00200000U
-#define RTC_DR_YT_2                          0x00400000U
-#define RTC_DR_YT_3                          0x00800000U
-#define RTC_DR_YU                            0x000F0000U
-#define RTC_DR_YU_0                          0x00010000U
-#define RTC_DR_YU_1                          0x00020000U
-#define RTC_DR_YU_2                          0x00040000U
-#define RTC_DR_YU_3                          0x00080000U
-#define RTC_DR_WDU                           0x0000E000U
-#define RTC_DR_WDU_0                         0x00002000U
-#define RTC_DR_WDU_1                         0x00004000U
-#define RTC_DR_WDU_2                         0x00008000U
-#define RTC_DR_MT                            0x00001000U
-#define RTC_DR_MU                            0x00000F00U
-#define RTC_DR_MU_0                          0x00000100U
-#define RTC_DR_MU_1                          0x00000200U
-#define RTC_DR_MU_2                          0x00000400U
-#define RTC_DR_MU_3                          0x00000800U
-#define RTC_DR_DT                            0x00000030U
-#define RTC_DR_DT_0                          0x00000010U
-#define RTC_DR_DT_1                          0x00000020U
-#define RTC_DR_DU                            0x0000000FU
-#define RTC_DR_DU_0                          0x00000001U
-#define RTC_DR_DU_1                          0x00000002U
-#define RTC_DR_DU_2                          0x00000004U
-#define RTC_DR_DU_3                          0x00000008U
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_ITSE                          0x01000000U
-#define RTC_CR_COE                           0x00800000U
-#define RTC_CR_OSEL                          0x00600000U
-#define RTC_CR_OSEL_0                        0x00200000U
-#define RTC_CR_OSEL_1                        0x00400000U
-#define RTC_CR_POL                           0x00100000U
-#define RTC_CR_COSEL                         0x00080000U
-#define RTC_CR_BKP                           0x00040000U
-#define RTC_CR_SUB1H                         0x00020000U
-#define RTC_CR_ADD1H                         0x00010000U
-#define RTC_CR_TSIE                          0x00008000U
-#define RTC_CR_WUTIE                         0x00004000U
-#define RTC_CR_ALRBIE                        0x00002000U
-#define RTC_CR_ALRAIE                        0x00001000U
-#define RTC_CR_TSE                           0x00000800U
-#define RTC_CR_WUTE                          0x00000400U
-#define RTC_CR_ALRBE                         0x00000200U
-#define RTC_CR_ALRAE                         0x00000100U
-#define RTC_CR_FMT                           0x00000040U
-#define RTC_CR_BYPSHAD                       0x00000020U
-#define RTC_CR_REFCKON                       0x00000010U
-#define RTC_CR_TSEDGE                        0x00000008U
-#define RTC_CR_WUCKSEL                       0x00000007U
-#define RTC_CR_WUCKSEL_0                     0x00000001U
-#define RTC_CR_WUCKSEL_1                     0x00000002U
-#define RTC_CR_WUCKSEL_2                     0x00000004U
-
-/* Legacy define */
-#define RTC_CR_BCK                           RTC_CR_BKP
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_ITSF                         0x00020000U
-#define RTC_ISR_RECALPF                      0x00010000U
-#define RTC_ISR_TAMP3F                       0x00008000U
-#define RTC_ISR_TAMP2F                       0x00004000U
-#define RTC_ISR_TAMP1F                       0x00002000U
-#define RTC_ISR_TSOVF                        0x00001000U
-#define RTC_ISR_TSF                          0x00000800U
-#define RTC_ISR_WUTF                         0x00000400U
-#define RTC_ISR_ALRBF                        0x00000200U
-#define RTC_ISR_ALRAF                        0x00000100U
-#define RTC_ISR_INIT                         0x00000080U
-#define RTC_ISR_INITF                        0x00000040U
-#define RTC_ISR_RSF                          0x00000020U
-#define RTC_ISR_INITS                        0x00000010U
-#define RTC_ISR_SHPF                         0x00000008U
-#define RTC_ISR_WUTWF                        0x00000004U
-#define RTC_ISR_ALRBWF                       0x00000002U
-#define RTC_ISR_ALRAWF                       0x00000001U
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    0x007F0000U
-#define RTC_PRER_PREDIV_S                    0x00007FFFU
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         0x0000FFFFU
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      0x80000000U
-#define RTC_ALRMAR_WDSEL                     0x40000000U
-#define RTC_ALRMAR_DT                        0x30000000U
-#define RTC_ALRMAR_DT_0                      0x10000000U
-#define RTC_ALRMAR_DT_1                      0x20000000U
-#define RTC_ALRMAR_DU                        0x0F000000U
-#define RTC_ALRMAR_DU_0                      0x01000000U
-#define RTC_ALRMAR_DU_1                      0x02000000U
-#define RTC_ALRMAR_DU_2                      0x04000000U
-#define RTC_ALRMAR_DU_3                      0x08000000U
-#define RTC_ALRMAR_MSK3                      0x00800000U
-#define RTC_ALRMAR_PM                        0x00400000U
-#define RTC_ALRMAR_HT                        0x00300000U
-#define RTC_ALRMAR_HT_0                      0x00100000U
-#define RTC_ALRMAR_HT_1                      0x00200000U
-#define RTC_ALRMAR_HU                        0x000F0000U
-#define RTC_ALRMAR_HU_0                      0x00010000U
-#define RTC_ALRMAR_HU_1                      0x00020000U
-#define RTC_ALRMAR_HU_2                      0x00040000U
-#define RTC_ALRMAR_HU_3                      0x00080000U
-#define RTC_ALRMAR_MSK2                      0x00008000U
-#define RTC_ALRMAR_MNT                       0x00007000U
-#define RTC_ALRMAR_MNT_0                     0x00001000U
-#define RTC_ALRMAR_MNT_1                     0x00002000U
-#define RTC_ALRMAR_MNT_2                     0x00004000U
-#define RTC_ALRMAR_MNU                       0x00000F00U
-#define RTC_ALRMAR_MNU_0                     0x00000100U
-#define RTC_ALRMAR_MNU_1                     0x00000200U
-#define RTC_ALRMAR_MNU_2                     0x00000400U
-#define RTC_ALRMAR_MNU_3                     0x00000800U
-#define RTC_ALRMAR_MSK1                      0x00000080U
-#define RTC_ALRMAR_ST                        0x00000070U
-#define RTC_ALRMAR_ST_0                      0x00000010U
-#define RTC_ALRMAR_ST_1                      0x00000020U
-#define RTC_ALRMAR_ST_2                      0x00000040U
-#define RTC_ALRMAR_SU                        0x0000000FU
-#define RTC_ALRMAR_SU_0                      0x00000001U
-#define RTC_ALRMAR_SU_1                      0x00000002U
-#define RTC_ALRMAR_SU_2                      0x00000004U
-#define RTC_ALRMAR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      0x80000000U
-#define RTC_ALRMBR_WDSEL                     0x40000000U
-#define RTC_ALRMBR_DT                        0x30000000U
-#define RTC_ALRMBR_DT_0                      0x10000000U
-#define RTC_ALRMBR_DT_1                      0x20000000U
-#define RTC_ALRMBR_DU                        0x0F000000U
-#define RTC_ALRMBR_DU_0                      0x01000000U
-#define RTC_ALRMBR_DU_1                      0x02000000U
-#define RTC_ALRMBR_DU_2                      0x04000000U
-#define RTC_ALRMBR_DU_3                      0x08000000U
-#define RTC_ALRMBR_MSK3                      0x00800000U
-#define RTC_ALRMBR_PM                        0x00400000U
-#define RTC_ALRMBR_HT                        0x00300000U
-#define RTC_ALRMBR_HT_0                      0x00100000U
-#define RTC_ALRMBR_HT_1                      0x00200000U
-#define RTC_ALRMBR_HU                        0x000F0000U
-#define RTC_ALRMBR_HU_0                      0x00010000U
-#define RTC_ALRMBR_HU_1                      0x00020000U
-#define RTC_ALRMBR_HU_2                      0x00040000U
-#define RTC_ALRMBR_HU_3                      0x00080000U
-#define RTC_ALRMBR_MSK2                      0x00008000U
-#define RTC_ALRMBR_MNT                       0x00007000U
-#define RTC_ALRMBR_MNT_0                     0x00001000U
-#define RTC_ALRMBR_MNT_1                     0x00002000U
-#define RTC_ALRMBR_MNT_2                     0x00004000U
-#define RTC_ALRMBR_MNU                       0x00000F00U
-#define RTC_ALRMBR_MNU_0                     0x00000100U
-#define RTC_ALRMBR_MNU_1                     0x00000200U
-#define RTC_ALRMBR_MNU_2                     0x00000400U
-#define RTC_ALRMBR_MNU_3                     0x00000800U
-#define RTC_ALRMBR_MSK1                      0x00000080U
-#define RTC_ALRMBR_ST                        0x00000070U
-#define RTC_ALRMBR_ST_0                      0x00000010U
-#define RTC_ALRMBR_ST_1                      0x00000020U
-#define RTC_ALRMBR_ST_2                      0x00000040U
-#define RTC_ALRMBR_SU                        0x0000000FU
-#define RTC_ALRMBR_SU_0                      0x00000001U
-#define RTC_ALRMBR_SU_1                      0x00000002U
-#define RTC_ALRMBR_SU_2                      0x00000004U
-#define RTC_ALRMBR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          0x000000FFU
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           0x0000FFFFU
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     0x00007FFFU
-#define RTC_SHIFTR_ADD1S                     0x80000000U
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          0x00400000U
-#define RTC_TSTR_HT                          0x00300000U
-#define RTC_TSTR_HT_0                        0x00100000U
-#define RTC_TSTR_HT_1                        0x00200000U
-#define RTC_TSTR_HU                          0x000F0000U
-#define RTC_TSTR_HU_0                        0x00010000U
-#define RTC_TSTR_HU_1                        0x00020000U
-#define RTC_TSTR_HU_2                        0x00040000U
-#define RTC_TSTR_HU_3                        0x00080000U
-#define RTC_TSTR_MNT                         0x00007000U
-#define RTC_TSTR_MNT_0                       0x00001000U
-#define RTC_TSTR_MNT_1                       0x00002000U
-#define RTC_TSTR_MNT_2                       0x00004000U
-#define RTC_TSTR_MNU                         0x00000F00U
-#define RTC_TSTR_MNU_0                       0x00000100U
-#define RTC_TSTR_MNU_1                       0x00000200U
-#define RTC_TSTR_MNU_2                       0x00000400U
-#define RTC_TSTR_MNU_3                       0x00000800U
-#define RTC_TSTR_ST                          0x00000070U
-#define RTC_TSTR_ST_0                        0x00000010U
-#define RTC_TSTR_ST_1                        0x00000020U
-#define RTC_TSTR_ST_2                        0x00000040U
-#define RTC_TSTR_SU                          0x0000000FU
-#define RTC_TSTR_SU_0                        0x00000001U
-#define RTC_TSTR_SU_1                        0x00000002U
-#define RTC_TSTR_SU_2                        0x00000004U
-#define RTC_TSTR_SU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         0x0000E000U
-#define RTC_TSDR_WDU_0                       0x00002000U
-#define RTC_TSDR_WDU_1                       0x00004000U
-#define RTC_TSDR_WDU_2                       0x00008000U
-#define RTC_TSDR_MT                          0x00001000U
-#define RTC_TSDR_MU                          0x00000F00U
-#define RTC_TSDR_MU_0                        0x00000100U
-#define RTC_TSDR_MU_1                        0x00000200U
-#define RTC_TSDR_MU_2                        0x00000400U
-#define RTC_TSDR_MU_3                        0x00000800U
-#define RTC_TSDR_DT                          0x00000030U
-#define RTC_TSDR_DT_0                        0x00000010U
-#define RTC_TSDR_DT_1                        0x00000020U
-#define RTC_TSDR_DU                          0x0000000FU
-#define RTC_TSDR_DU_0                        0x00000001U
-#define RTC_TSDR_DU_1                        0x00000002U
-#define RTC_TSDR_DU_2                        0x00000004U
-#define RTC_TSDR_DU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        0x00008000U
-#define RTC_CALR_CALW8                       0x00004000U
-#define RTC_CALR_CALW16                      0x00002000U
-#define RTC_CALR_CALM                        0x000001FFU
-#define RTC_CALR_CALM_0                      0x00000001U
-#define RTC_CALR_CALM_1                      0x00000002U
-#define RTC_CALR_CALM_2                      0x00000004U
-#define RTC_CALR_CALM_3                      0x00000008U
-#define RTC_CALR_CALM_4                      0x00000010U
-#define RTC_CALR_CALM_5                      0x00000020U
-#define RTC_CALR_CALM_6                      0x00000040U
-#define RTC_CALR_CALM_7                      0x00000080U
-#define RTC_CALR_CALM_8                      0x00000100U
-
-/********************  Bits definition for RTC_TAMPCR register  ****************/
-#define RTC_TAMPCR_TAMP3MF                   0x01000000U
-#define RTC_TAMPCR_TAMP3NOERASE              0x00800000U
-#define RTC_TAMPCR_TAMP3IE                   0x00400000U
-#define RTC_TAMPCR_TAMP2MF                   0x00200000U
-#define RTC_TAMPCR_TAMP2NOERASE              0x00100000U
-#define RTC_TAMPCR_TAMP2IE                   0x00080000U
-#define RTC_TAMPCR_TAMP1MF                   0x00040000U
-#define RTC_TAMPCR_TAMP1NOERASE              0x00020000U
-#define RTC_TAMPCR_TAMP1IE                   0x00010000U
-#define RTC_TAMPCR_TAMPPUDIS                 0x00008000U
-#define RTC_TAMPCR_TAMPPRCH                  0x00006000U
-#define RTC_TAMPCR_TAMPPRCH_0                0x00002000U
-#define RTC_TAMPCR_TAMPPRCH_1                0x00004000U
-#define RTC_TAMPCR_TAMPFLT                   0x00001800U
-#define RTC_TAMPCR_TAMPFLT_0                 0x00000800U
-#define RTC_TAMPCR_TAMPFLT_1                 0x00001000U
-#define RTC_TAMPCR_TAMPFREQ                  0x00000700U
-#define RTC_TAMPCR_TAMPFREQ_0                0x00000100U
-#define RTC_TAMPCR_TAMPFREQ_1                0x00000200U
-#define RTC_TAMPCR_TAMPFREQ_2                0x00000400U
-#define RTC_TAMPCR_TAMPTS                    0x00000080U
-#define RTC_TAMPCR_TAMP3TRG                  0x00000040U
-#define RTC_TAMPCR_TAMP3E                    0x00000020U
-#define RTC_TAMPCR_TAMP2TRG                  0x00000010U
-#define RTC_TAMPCR_TAMP2E                    0x00000008U
-#define RTC_TAMPCR_TAMPIE                    0x00000004U
-#define RTC_TAMPCR_TAMP1TRG                  0x00000002U
-#define RTC_TAMPCR_TAMP1E                    0x00000001U
-
-/* Legacy defines */
-#define RTC_TAMPCR_TAMP3_TRG                  RTC_TAMPCR_TAMP3TRG
-#define RTC_TAMPCR_TAMP2_TRG                  RTC_TAMPCR_TAMP2TRG
-#define RTC_TAMPCR_TAMP1_TRG                  RTC_TAMPCR_TAMP1TRG
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  0x0F000000U
-#define RTC_ALRMASSR_MASKSS_0                0x01000000U
-#define RTC_ALRMASSR_MASKSS_1                0x02000000U
-#define RTC_ALRMASSR_MASKSS_2                0x04000000U
-#define RTC_ALRMASSR_MASKSS_3                0x08000000U
-#define RTC_ALRMASSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
-#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
-#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
-#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
-#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
-#define RTC_ALRMBSSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_OR register  ****************/
-#define RTC_OR_TSINSEL                       0x00000006U
-#define RTC_OR_TSINSEL_0                     0x00000002U
-#define RTC_OR_TSINSEL_1                     0x00000004U
-#define RTC_OR_ALARMTYPE                     0x00000008U
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP20R register  ***************/
-#define RTC_BKP20R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP21R register  ***************/
-#define RTC_BKP21R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP22R register  ***************/
-#define RTC_BKP22R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP23R register  ***************/
-#define RTC_BKP23R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP24R register  ***************/
-#define RTC_BKP24R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP25R register  ***************/
-#define RTC_BKP25R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP26R register  ***************/
-#define RTC_BKP26R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP27R register  ***************/
-#define RTC_BKP27R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP28R register  ***************/
-#define RTC_BKP28R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP29R register  ***************/
-#define RTC_BKP29R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP30R register  ***************/
-#define RTC_BKP30R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP31R register  ***************/
-#define RTC_BKP31R                           0xFFFFFFFFU
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER                       0x00000020U
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Serial Audio Interface                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for SAI_GCR register  *******************/
-#define  SAI_GCR_SYNCIN                      0x00000003U        /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
-#define  SAI_GCR_SYNCIN_0                    0x00000001U        /*!<Bit 0 */
-#define  SAI_GCR_SYNCIN_1                    0x00000002U        /*!<Bit 1 */
-
-#define  SAI_GCR_SYNCOUT                     0x00000030U        /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
-#define  SAI_GCR_SYNCOUT_0                   0x00000010U        /*!<Bit 0 */
-#define  SAI_GCR_SYNCOUT_1                   0x00000020U        /*!<Bit 1 */
-
-/*******************  Bit definition for SAI_xCR1 register  *******************/
-#define  SAI_xCR1_MODE                       0x00000003U        /*!<MODE[1:0] bits (Audio Block Mode)           */
-#define  SAI_xCR1_MODE_0                     0x00000001U        /*!<Bit 0 */
-#define  SAI_xCR1_MODE_1                     0x00000002U        /*!<Bit 1 */
-
-#define  SAI_xCR1_PRTCFG                     0x0000000CU        /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
-#define  SAI_xCR1_PRTCFG_0                   0x00000004U        /*!<Bit 0 */
-#define  SAI_xCR1_PRTCFG_1                   0x00000008U        /*!<Bit 1 */
-
-#define  SAI_xCR1_DS                         0x000000E0U        /*!<DS[1:0] bits (Data Size) */
-#define  SAI_xCR1_DS_0                       0x00000020U        /*!<Bit 0 */
-#define  SAI_xCR1_DS_1                       0x00000040U        /*!<Bit 1 */
-#define  SAI_xCR1_DS_2                       0x00000080U        /*!<Bit 2 */
-
-#define  SAI_xCR1_LSBFIRST                   0x00000100U        /*!<LSB First Configuration  */
-#define  SAI_xCR1_CKSTR                      0x00000200U        /*!<ClocK STRobing edge      */
-
-#define  SAI_xCR1_SYNCEN                     0x00000C00U        /*!<SYNCEN[1:0](SYNChronization ENable) */
-#define  SAI_xCR1_SYNCEN_0                   0x00000400U        /*!<Bit 0 */
-#define  SAI_xCR1_SYNCEN_1                   0x00000800U        /*!<Bit 1 */
-
-#define  SAI_xCR1_MONO                       0x00001000U        /*!<Mono mode                  */
-#define  SAI_xCR1_OUTDRIV                    0x00002000U        /*!<Output Drive               */
-#define  SAI_xCR1_SAIEN                      0x00010000U        /*!<Audio Block enable         */
-#define  SAI_xCR1_DMAEN                      0x00020000U        /*!<DMA enable                 */
-#define  SAI_xCR1_NODIV                      0x00080000U        /*!<No Divider Configuration   */
-
-#define  SAI_xCR1_MCKDIV                     0x00F00000U        /*!<MCKDIV[3:0] (Master ClocK Divider)  */
-#define  SAI_xCR1_MCKDIV_0                   0x00100000U        /*!<Bit 0  */
-#define  SAI_xCR1_MCKDIV_1                   0x00200000U        /*!<Bit 1  */
-#define  SAI_xCR1_MCKDIV_2                   0x00400000U        /*!<Bit 2  */
-#define  SAI_xCR1_MCKDIV_3                   0x00800000U        /*!<Bit 3  */
-
-/*******************  Bit definition for SAI_xCR2 register  *******************/
-#define  SAI_xCR2_FTH                        0x00000007U        /*!<FTH[2:0](Fifo THreshold)  */
-#define  SAI_xCR2_FTH_0                      0x00000001U        /*!<Bit 0 */
-#define  SAI_xCR2_FTH_1                      0x00000002U        /*!<Bit 1 */
-#define  SAI_xCR2_FTH_2                      0x00000004U        /*!<Bit 2 */
-
-#define  SAI_xCR2_FFLUSH                     0x00000008U        /*!<Fifo FLUSH                       */
-#define  SAI_xCR2_TRIS                       0x00000010U        /*!<TRIState Management on data line */
-#define  SAI_xCR2_MUTE                       0x00000020U        /*!<Mute mode                        */
-#define  SAI_xCR2_MUTEVAL                    0x00000040U        /*!<Muate value                      */
-
-#define  SAI_xCR2_MUTECNT                    0x00001F80U       /*!<MUTECNT[5:0] (MUTE counter) */
-#define  SAI_xCR2_MUTECNT_0                  0x00000080U        /*!<Bit 0 */
-#define  SAI_xCR2_MUTECNT_1                  0x00000100U        /*!<Bit 1 */
-#define  SAI_xCR2_MUTECNT_2                  0x00000200U        /*!<Bit 2 */
-#define  SAI_xCR2_MUTECNT_3                  0x00000400U        /*!<Bit 3 */
-#define  SAI_xCR2_MUTECNT_4                  0x00000800U        /*!<Bit 4 */
-#define  SAI_xCR2_MUTECNT_5                  0x00001000U        /*!<Bit 5 */
-
-#define  SAI_xCR2_CPL                        0x00002000U        /*!< Complement Bit             */
-
-#define  SAI_xCR2_COMP                       0x0000C000U        /*!<COMP[1:0] (Companding mode) */
-#define  SAI_xCR2_COMP_0                     0x00004000U        /*!<Bit 0 */
-#define  SAI_xCR2_COMP_1                     0x00008000U        /*!<Bit 1 */
-
-/******************  Bit definition for SAI_xFRCR register  *******************/
-#define  SAI_xFRCR_FRL                       0x000000FFU        /*!<FRL[1:0](Frame length)  */
-#define  SAI_xFRCR_FRL_0                     0x00000001U        /*!<Bit 0 */
-#define  SAI_xFRCR_FRL_1                     0x00000002U        /*!<Bit 1 */
-#define  SAI_xFRCR_FRL_2                     0x00000004U        /*!<Bit 2 */
-#define  SAI_xFRCR_FRL_3                     0x00000008U        /*!<Bit 3 */
-#define  SAI_xFRCR_FRL_4                     0x00000010U        /*!<Bit 4 */
-#define  SAI_xFRCR_FRL_5                     0x00000020U        /*!<Bit 5 */
-#define  SAI_xFRCR_FRL_6                     0x00000040U        /*!<Bit 6 */
-#define  SAI_xFRCR_FRL_7                     0x00000080U        /*!<Bit 7 */
-
-#define  SAI_xFRCR_FSALL                     0x00007F00U        /*!<FRL[1:0] (Frame synchronization active level length)  */
-#define  SAI_xFRCR_FSALL_0                   0x00000100U        /*!<Bit 0 */
-#define  SAI_xFRCR_FSALL_1                   0x00000200U        /*!<Bit 1 */
-#define  SAI_xFRCR_FSALL_2                   0x00000400U        /*!<Bit 2 */
-#define  SAI_xFRCR_FSALL_3                   0x00000800U        /*!<Bit 3 */
-#define  SAI_xFRCR_FSALL_4                   0x00001000U        /*!<Bit 4 */
-#define  SAI_xFRCR_FSALL_5                   0x00002000U        /*!<Bit 5 */
-#define  SAI_xFRCR_FSALL_6                   0x00004000U        /*!<Bit 6 */
-
-#define  SAI_xFRCR_FSDEF                     0x00010000U        /*!<Frame Synchronization Definition  */
-#define  SAI_xFRCR_FSPOL                     0x00020000U        /*!<Frame Synchronization POLarity    */
-#define  SAI_xFRCR_FSOFF                     0x00040000U        /*!<Frame Synchronization OFFset      */
-
-/* Legacy define */
-#define  SAI_xFRCR_FSPO                      SAI_xFRCR_FSPOL
-
-/******************  Bit definition for SAI_xSLOTR register  *******************/
-#define  SAI_xSLOTR_FBOFF                    0x0000001FU        /*!<FRL[4:0](First Bit Offset)  */
-#define  SAI_xSLOTR_FBOFF_0                  0x00000001U        /*!<Bit 0 */
-#define  SAI_xSLOTR_FBOFF_1                  0x00000002U        /*!<Bit 1 */
-#define  SAI_xSLOTR_FBOFF_2                  0x00000004U        /*!<Bit 2 */
-#define  SAI_xSLOTR_FBOFF_3                  0x00000008U        /*!<Bit 3 */
-#define  SAI_xSLOTR_FBOFF_4                  0x00000010U        /*!<Bit 4 */
-
-#define  SAI_xSLOTR_SLOTSZ                   0x000000C0U        /*!<SLOTSZ[1:0] (Slot size)  */
-#define  SAI_xSLOTR_SLOTSZ_0                 0x00000040U        /*!<Bit 0 */
-#define  SAI_xSLOTR_SLOTSZ_1                 0x00000080U        /*!<Bit 1 */
-
-#define  SAI_xSLOTR_NBSLOT                   0x00000F00U        /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
-#define  SAI_xSLOTR_NBSLOT_0                 0x00000100U        /*!<Bit 0 */
-#define  SAI_xSLOTR_NBSLOT_1                 0x00000200U        /*!<Bit 1 */
-#define  SAI_xSLOTR_NBSLOT_2                 0x00000400U        /*!<Bit 2 */
-#define  SAI_xSLOTR_NBSLOT_3                 0x00000800U        /*!<Bit 3 */
-
-#define  SAI_xSLOTR_SLOTEN                   0xFFFF0000U        /*!<SLOTEN[15:0] (Slot Enable)  */
-
-/*******************  Bit definition for SAI_xIMR register  *******************/
-#define  SAI_xIMR_OVRUDRIE                   0x00000001U        /*!<Overrun underrun interrupt enable                              */
-#define  SAI_xIMR_MUTEDETIE                  0x00000002U        /*!<Mute detection interrupt enable                                */
-#define  SAI_xIMR_WCKCFGIE                   0x00000004U        /*!<Wrong Clock Configuration interrupt enable                     */
-#define  SAI_xIMR_FREQIE                     0x00000008U        /*!<FIFO request interrupt enable                                  */
-#define  SAI_xIMR_CNRDYIE                    0x00000010U        /*!<Codec not ready interrupt enable                               */
-#define  SAI_xIMR_AFSDETIE                   0x00000020U        /*!<Anticipated frame synchronization detection interrupt enable   */
-#define  SAI_xIMR_LFSDETIE                   0x00000040U        /*!<Late frame synchronization detection interrupt enable          */
-
-/********************  Bit definition for SAI_xSR register  *******************/
-#define  SAI_xSR_OVRUDR                      0x00000001U         /*!<Overrun underrun                               */
-#define  SAI_xSR_MUTEDET                     0x00000002U         /*!<Mute detection                                 */
-#define  SAI_xSR_WCKCFG                      0x00000004U         /*!<Wrong Clock Configuration                      */
-#define  SAI_xSR_FREQ                        0x00000008U         /*!<FIFO request                                   */
-#define  SAI_xSR_CNRDY                       0x00000010U         /*!<Codec not ready                                */
-#define  SAI_xSR_AFSDET                      0x00000020U         /*!<Anticipated frame synchronization detection    */
-#define  SAI_xSR_LFSDET                      0x00000040U         /*!<Late frame synchronization detection           */
-
-#define  SAI_xSR_FLVL                        0x00070000U         /*!<FLVL[2:0] (FIFO Level Threshold)               */
-#define  SAI_xSR_FLVL_0                      0x00010000U         /*!<Bit 0 */
-#define  SAI_xSR_FLVL_1                      0x00020000U         /*!<Bit 1 */
-#define  SAI_xSR_FLVL_2                      0x00040000U         /*!<Bit 2 */
-
-/******************  Bit definition for SAI_xCLRFR register  ******************/
-#define  SAI_xCLRFR_COVRUDR                  0x00000001U        /*!<Clear Overrun underrun                               */
-#define  SAI_xCLRFR_CMUTEDET                 0x00000002U        /*!<Clear Mute detection                                 */
-#define  SAI_xCLRFR_CWCKCFG                  0x00000004U        /*!<Clear Wrong Clock Configuration                      */
-#define  SAI_xCLRFR_CFREQ                    0x00000008U        /*!<Clear FIFO request                                   */
-#define  SAI_xCLRFR_CCNRDY                   0x00000010U        /*!<Clear Codec not ready                                */
-#define  SAI_xCLRFR_CAFSDET                  0x00000020U        /*!<Clear Anticipated frame synchronization detection    */
-#define  SAI_xCLRFR_CLFSDET                  0x00000040U        /*!<Clear Late frame synchronization detection           */
-
-/******************  Bit definition for SAI_xDR register  *********************/
-#define  SAI_xDR_DATA                        0xFFFFFFFFU
-
-/******************************************************************************/
-/*                                                                            */
-/*                              SPDIF-RX Interface                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for SPDIF_CR register  *******************/
-#define  SPDIFRX_CR_SPDIFEN                0x00000003U        /*!<Peripheral Block Enable                      */
-#define  SPDIFRX_CR_RXDMAEN                0x00000004U        /*!<Receiver DMA Enable for data flow            */
-#define  SPDIFRX_CR_RXSTEO                 0x00000008U        /*!<Stereo Mode                                  */
-#define  SPDIFRX_CR_DRFMT                  0x00000030U        /*!<RX Data format                               */
-#define  SPDIFRX_CR_PMSK                   0x00000040U        /*!<Mask Parity error bit                        */
-#define  SPDIFRX_CR_VMSK                   0x00000080U        /*!<Mask of Validity bit                         */
-#define  SPDIFRX_CR_CUMSK                  0x00000100U        /*!<Mask of channel status and user bits         */
-#define  SPDIFRX_CR_PTMSK                  0x00000200U        /*!<Mask of Preamble Type bits                   */
-#define  SPDIFRX_CR_CBDMAEN                0x00000400U        /*!<Control Buffer DMA ENable for control flow   */
-#define  SPDIFRX_CR_CHSEL                  0x00000800U        /*!<Channel Selection                            */
-#define  SPDIFRX_CR_NBTR                   0x00003000U        /*!<Maximum allowed re-tries during synchronization phase */
-#define  SPDIFRX_CR_WFA                    0x00004000U        /*!<Wait For Activity     */
-#define  SPDIFRX_CR_INSEL                  0x00070000U        /*!<SPDIF input selection */
-
-/*******************  Bit definition for SPDIFRX_IMR register  *******************/
-#define  SPDIFRX_IMR_RXNEIE                0x00000001U        /*!<RXNE interrupt enable                              */
-#define  SPDIFRX_IMR_CSRNEIE               0x00000002U        /*!<Control Buffer Ready Interrupt Enable              */
-#define  SPDIFRX_IMR_PERRIE                0x00000004U        /*!<Parity error interrupt enable                      */
-#define  SPDIFRX_IMR_OVRIE                 0x00000008U        /*!<Overrun error Interrupt Enable                     */
-#define  SPDIFRX_IMR_SBLKIE                0x00000010U        /*!<Synchronization Block Detected Interrupt Enable    */
-#define  SPDIFRX_IMR_SYNCDIE               0x00000020U        /*!<Synchronization Done                               */
-#define  SPDIFRX_IMR_IFEIE                 0x00000040U        /*!<Serial Interface Error Interrupt Enable            */
-
-/*******************  Bit definition for SPDIFRX_SR register  *******************/
-#define  SPDIFRX_SR_RXNE                   0x00000001U       /*!<Read data register not empty                          */
-#define  SPDIFRX_SR_CSRNE                  0x00000002U       /*!<The Control Buffer register is not empty              */
-#define  SPDIFRX_SR_PERR                   0x00000004U       /*!<Parity error                                          */
-#define  SPDIFRX_SR_OVR                    0x00000008U       /*!<Overrun error                                         */
-#define  SPDIFRX_SR_SBD                    0x00000010U       /*!<Synchronization Block Detected                        */
-#define  SPDIFRX_SR_SYNCD                  0x00000020U       /*!<Synchronization Done                                  */
-#define  SPDIFRX_SR_FERR                   0x00000040U       /*!<Framing error                                         */
-#define  SPDIFRX_SR_SERR                   0x00000080U       /*!<Synchronization error                                 */
-#define  SPDIFRX_SR_TERR                   0x00000100U       /*!<Time-out error                                        */
-#define  SPDIFRX_SR_WIDTH5                 0x7FFF0000U       /*!<Duration of 5 symbols counted with spdif_clk          */
-
-/*******************  Bit definition for SPDIFRX_IFCR register  *******************/
-#define  SPDIFRX_IFCR_PERRCF               0x00000004U       /*!<Clears the Parity error flag                         */
-#define  SPDIFRX_IFCR_OVRCF                0x00000008U       /*!<Clears the Overrun error flag                        */
-#define  SPDIFRX_IFCR_SBDCF                0x00000010U       /*!<Clears the Synchronization Block Detected flag       */
-#define  SPDIFRX_IFCR_SYNCDCF              0x00000020U       /*!<Clears the Synchronization Done flag                 */
-
-/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/
-#define  SPDIFRX_DR0_DR                    0x00FFFFFFU        /*!<Data value            */
-#define  SPDIFRX_DR0_PE                    0x01000000U        /*!<Parity Error bit      */
-#define  SPDIFRX_DR0_V                     0x02000000U        /*!<Validity bit          */
-#define  SPDIFRX_DR0_U                     0x04000000U        /*!<User bit              */
-#define  SPDIFRX_DR0_C                     0x08000000U        /*!<Channel Status bit    */
-#define  SPDIFRX_DR0_PT                    0x30000000U        /*!<Preamble Type         */
-
-/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/
-#define  SPDIFRX_DR1_DR                    0xFFFFFF00U        /*!<Data value            */
-#define  SPDIFRX_DR1_PT                    0x00000030U        /*!<Preamble Type         */
-#define  SPDIFRX_DR1_C                     0x00000008U        /*!<Channel Status bit    */
-#define  SPDIFRX_DR1_U                     0x00000004U        /*!<User bit              */
-#define  SPDIFRX_DR1_V                     0x00000002U        /*!<Validity bit          */
-#define  SPDIFRX_DR1_PE                    0x00000001U        /*!<Parity Error bit      */
-
-/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/
-#define  SPDIFRX_DR1_DRNL1                 0xFFFF0000U        /*!<Data value Channel B      */
-#define  SPDIFRX_DR1_DRNL2                 0x0000FFFFU        /*!<Data value Channel A      */
-
-/*******************  Bit definition for SPDIFRX_CSR register   *******************/
-#define  SPDIFRX_CSR_USR                   0x0000FFFFU        /*!<User data information           */
-#define  SPDIFRX_CSR_CS                    0x00FF0000U        /*!<Channel A status information    */
-#define  SPDIFRX_CSR_SOB                   0x01000000U        /*!<Start Of Block                  */
-
-/*******************  Bit definition for SPDIFRX_DIR register    *******************/
-#define  SPDIFRX_DIR_THI                   0x000013FFU        /*!<Threshold LOW      */
-#define  SPDIFRX_DIR_TLO                   0x1FFF0000U        /*!<Threshold HIGH     */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          SD host Interface                                 */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SDMMC_POWER register  ******************/
-#define  SDMMC_POWER_PWRCTRL                  0x03U               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDMMC_POWER_PWRCTRL_0                0x01U               /*!<Bit 0 */
-#define  SDMMC_POWER_PWRCTRL_1                0x02U               /*!<Bit 1 */
-
-/******************  Bit definition for SDMMC_CLKCR register  ******************/
-#define  SDMMC_CLKCR_CLKDIV                   0x00FFU            /*!<Clock divide factor             */
-#define  SDMMC_CLKCR_CLKEN                    0x0100U            /*!<Clock enable bit                */
-#define  SDMMC_CLKCR_PWRSAV                   0x0200U            /*!<Power saving configuration bit  */
-#define  SDMMC_CLKCR_BYPASS                   0x0400U            /*!<Clock divider bypass enable bit */
-
-#define  SDMMC_CLKCR_WIDBUS                   0x1800U            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDMMC_CLKCR_WIDBUS_0                 0x0800U            /*!<Bit 0 */
-#define  SDMMC_CLKCR_WIDBUS_1                 0x1000U            /*!<Bit 1 */
-
-#define  SDMMC_CLKCR_NEGEDGE                  0x2000U            /*!<SDMMC_CK dephasing selection bit */
-#define  SDMMC_CLKCR_HWFC_EN                  0x4000U            /*!<HW Flow Control enable          */
-
-/*******************  Bit definition for SDMMC_ARG register  *******************/
-#define  SDMMC_ARG_CMDARG                     0xFFFFFFFFU            /*!<Command argument */
-
-/*******************  Bit definition for SDMMC_CMD register  *******************/
-#define  SDMMC_CMD_CMDINDEX                   0x003FU            /*!<Command Index                               */
-
-#define  SDMMC_CMD_WAITRESP                   0x00C0U            /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDMMC_CMD_WAITRESP_0                 0x0040U            /*!< Bit 0 */
-#define  SDMMC_CMD_WAITRESP_1                 0x0080U            /*!< Bit 1 */
-
-#define  SDMMC_CMD_WAITINT                    0x0100U            /*!<CPSM Waits for Interrupt Request                               */
-#define  SDMMC_CMD_WAITPEND                   0x0200U            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDMMC_CMD_CPSMEN                     0x0400U            /*!<Command path state machine (CPSM) Enable bit                   */
-#define  SDMMC_CMD_SDIOSUSPEND                0x0800U            /*!<SD I/O suspend command                                         */
-
-/*****************  Bit definition for SDMMC_RESPCMD register  *****************/
-#define  SDMMC_RESPCMD_RESPCMD                0x3FU               /*!<Response command index */
-
-/******************  Bit definition for SDMMC_RESP0 register  ******************/
-#define  SDMMC_RESP0_CARDSTATUS0              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDMMC_RESP1 register  ******************/
-#define  SDMMC_RESP1_CARDSTATUS1              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDMMC_RESP2 register  ******************/
-#define  SDMMC_RESP2_CARDSTATUS2              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDMMC_RESP3 register  ******************/
-#define  SDMMC_RESP3_CARDSTATUS3              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDMMC_RESP4 register  ******************/
-#define  SDMMC_RESP4_CARDSTATUS4              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDMMC_DTIMER register  *****************/
-#define  SDMMC_DTIMER_DATATIME                0xFFFFFFFFU        /*!<Data timeout period. */
-
-/******************  Bit definition for SDMMC_DLEN register  *******************/
-#define  SDMMC_DLEN_DATALENGTH                0x01FFFFFFU        /*!<Data length value    */
-
-/******************  Bit definition for SDMMC_DCTRL register  ******************/
-#define  SDMMC_DCTRL_DTEN                     0x0001U            /*!<Data transfer enabled bit         */
-#define  SDMMC_DCTRL_DTDIR                    0x0002U            /*!<Data transfer direction selection */
-#define  SDMMC_DCTRL_DTMODE                   0x0004U            /*!<Data transfer mode selection      */
-#define  SDMMC_DCTRL_DMAEN                    0x0008U            /*!<DMA enabled bit                   */
-
-#define  SDMMC_DCTRL_DBLOCKSIZE               0x00F0U            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDMMC_DCTRL_DBLOCKSIZE_0             0x0010U            /*!<Bit 0 */
-#define  SDMMC_DCTRL_DBLOCKSIZE_1             0x0020U            /*!<Bit 1 */
-#define  SDMMC_DCTRL_DBLOCKSIZE_2             0x0040U            /*!<Bit 2 */
-#define  SDMMC_DCTRL_DBLOCKSIZE_3             0x0080U            /*!<Bit 3 */
-
-#define  SDMMC_DCTRL_RWSTART                  0x0100U            /*!<Read wait start         */
-#define  SDMMC_DCTRL_RWSTOP                   0x0200U            /*!<Read wait stop          */
-#define  SDMMC_DCTRL_RWMOD                    0x0400U            /*!<Read wait mode          */
-#define  SDMMC_DCTRL_SDIOEN                   0x0800U            /*!<SD I/O enable functions */
-
-/******************  Bit definition for SDMMC_DCOUNT register  *****************/
-#define  SDMMC_DCOUNT_DATACOUNT               0x01FFFFFFU        /*!<Data count value */
-
-/******************  Bit definition for SDMMC_STA registe  ********************/
-#define  SDMMC_STA_CCRCFAIL                   0x00000001U        /*!<Command response received (CRC check failed)  */
-#define  SDMMC_STA_DCRCFAIL                   0x00000002U        /*!<Data block sent/received (CRC check failed)   */
-#define  SDMMC_STA_CTIMEOUT                   0x00000004U        /*!<Command response timeout                      */
-#define  SDMMC_STA_DTIMEOUT                   0x00000008U        /*!<Data timeout                                  */
-#define  SDMMC_STA_TXUNDERR                   0x00000010U        /*!<Transmit FIFO underrun error                  */
-#define  SDMMC_STA_RXOVERR                    0x00000020U        /*!<Received FIFO overrun error                   */
-#define  SDMMC_STA_CMDREND                    0x00000040U        /*!<Command response received (CRC check passed)  */
-#define  SDMMC_STA_CMDSENT                    0x00000080U        /*!<Command sent (no response required)           */
-#define  SDMMC_STA_DATAEND                    0x00000100U        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
-#define  SDMMC_STA_DBCKEND                    0x00000400U        /*!<Data block sent/received (CRC check passed)   */
-#define  SDMMC_STA_CMDACT                     0x00000800U        /*!<Command transfer in progress                  */
-#define  SDMMC_STA_TXACT                      0x00001000U        /*!<Data transmit in progress                     */
-#define  SDMMC_STA_RXACT                      0x00002000U        /*!<Data receive in progress                      */
-#define  SDMMC_STA_TXFIFOHE                   0x00004000U        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDMMC_STA_RXFIFOHF                   0x00008000U        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDMMC_STA_TXFIFOF                    0x00010000U        /*!<Transmit FIFO full                            */
-#define  SDMMC_STA_RXFIFOF                    0x00020000U        /*!<Receive FIFO full                             */
-#define  SDMMC_STA_TXFIFOE                    0x00040000U        /*!<Transmit FIFO empty                           */
-#define  SDMMC_STA_RXFIFOE                    0x00080000U        /*!<Receive FIFO empty                            */
-#define  SDMMC_STA_TXDAVL                     0x00100000U        /*!<Data available in transmit FIFO               */
-#define  SDMMC_STA_RXDAVL                     0x00200000U        /*!<Data available in receive FIFO                */
-#define  SDMMC_STA_SDIOIT                     0x00400000U        /*!<SDMMC interrupt received                       */
-
-/*******************  Bit definition for SDMMC_ICR register  *******************/
-#define  SDMMC_ICR_CCRCFAILC                  0x00000001U        /*!<CCRCFAIL flag clear bit */
-#define  SDMMC_ICR_DCRCFAILC                  0x00000002U        /*!<DCRCFAIL flag clear bit */
-#define  SDMMC_ICR_CTIMEOUTC                  0x00000004U        /*!<CTIMEOUT flag clear bit */
-#define  SDMMC_ICR_DTIMEOUTC                  0x00000008U        /*!<DTIMEOUT flag clear bit */
-#define  SDMMC_ICR_TXUNDERRC                  0x00000010U        /*!<TXUNDERR flag clear bit */
-#define  SDMMC_ICR_RXOVERRC                   0x00000020U        /*!<RXOVERR flag clear bit  */
-#define  SDMMC_ICR_CMDRENDC                   0x00000040U        /*!<CMDREND flag clear bit  */
-#define  SDMMC_ICR_CMDSENTC                   0x00000080U        /*!<CMDSENT flag clear bit  */
-#define  SDMMC_ICR_DATAENDC                   0x00000100U        /*!<DATAEND flag clear bit  */
-#define  SDMMC_ICR_DBCKENDC                   0x00000400U        /*!<DBCKEND flag clear bit  */
-#define  SDMMC_ICR_SDIOITC                    0x00400000U        /*!<SDMMCIT flag clear bit   */
-
-/******************  Bit definition for SDMMC_MASK register  *******************/
-#define  SDMMC_MASK_CCRCFAILIE                0x00000001U        /*!<Command CRC Fail Interrupt Enable          */
-#define  SDMMC_MASK_DCRCFAILIE                0x00000002U        /*!<Data CRC Fail Interrupt Enable             */
-#define  SDMMC_MASK_CTIMEOUTIE                0x00000004U        /*!<Command TimeOut Interrupt Enable           */
-#define  SDMMC_MASK_DTIMEOUTIE                0x00000008U        /*!<Data TimeOut Interrupt Enable              */
-#define  SDMMC_MASK_TXUNDERRIE                0x00000010U        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
-#define  SDMMC_MASK_RXOVERRIE                 0x00000020U        /*!<Rx FIFO OverRun Error Interrupt Enable     */
-#define  SDMMC_MASK_CMDRENDIE                 0x00000040U        /*!<Command Response Received Interrupt Enable */
-#define  SDMMC_MASK_CMDSENTIE                 0x00000080U        /*!<Command Sent Interrupt Enable              */
-#define  SDMMC_MASK_DATAENDIE                 0x00000100U        /*!<Data End Interrupt Enable                  */
-#define  SDMMC_MASK_DBCKENDIE                 0x00000400U        /*!<Data Block End Interrupt Enable            */
-#define  SDMMC_MASK_CMDACTIE                  0x00000800U        /*!<CCommand Acting Interrupt Enable           */
-#define  SDMMC_MASK_TXACTIE                   0x00001000U        /*!<Data Transmit Acting Interrupt Enable      */
-#define  SDMMC_MASK_RXACTIE                   0x00002000U        /*!<Data receive acting interrupt enabled      */
-#define  SDMMC_MASK_TXFIFOHEIE                0x00004000U        /*!<Tx FIFO Half Empty interrupt Enable        */
-#define  SDMMC_MASK_RXFIFOHFIE                0x00008000U        /*!<Rx FIFO Half Full interrupt Enable         */
-#define  SDMMC_MASK_TXFIFOFIE                 0x00010000U        /*!<Tx FIFO Full interrupt Enable              */
-#define  SDMMC_MASK_RXFIFOFIE                 0x00020000U        /*!<Rx FIFO Full interrupt Enable              */
-#define  SDMMC_MASK_TXFIFOEIE                 0x00040000U        /*!<Tx FIFO Empty interrupt Enable             */
-#define  SDMMC_MASK_RXFIFOEIE                 0x00080000U        /*!<Rx FIFO Empty interrupt Enable             */
-#define  SDMMC_MASK_TXDAVLIE                  0x00100000U        /*!<Data available in Tx FIFO interrupt Enable */
-#define  SDMMC_MASK_RXDAVLIE                  0x00200000U        /*!<Data available in Rx FIFO interrupt Enable */
-#define  SDMMC_MASK_SDIOITIE                  0x00400000U        /*!<SDMMC Mode Interrupt Received interrupt Enable */
-
-/*****************  Bit definition for SDMMC_FIFOCNT register  *****************/
-#define  SDMMC_FIFOCNT_FIFOCOUNT              0x00FFFFFFU        /*!<Remaining number of words to be written to or read from the FIFO */
-
-/******************  Bit definition for SDMMC_FIFO register  *******************/
-#define  SDMMC_FIFO_FIFODATA                  0xFFFFFFFFU        /*!<Receive and transmit FIFO data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface (SPI)                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        0x00000001U        /*!< Clock Phase                        */
-#define  SPI_CR1_CPOL                        0x00000002U        /*!< Clock Polarity                     */
-#define  SPI_CR1_MSTR                        0x00000004U        /*!< Master Selection                   */
-#define  SPI_CR1_BR                          0x00000038U        /*!< BR[2:0] bits (Baud Rate Control)   */
-#define  SPI_CR1_BR_0                        0x00000008U        /*!< Bit 0 */
-#define  SPI_CR1_BR_1                        0x00000010U        /*!< Bit 1 */
-#define  SPI_CR1_BR_2                        0x00000020U        /*!< Bit 2 */
-#define  SPI_CR1_SPE                         0x00000040U        /*!< SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    0x00000080U        /*!< Frame Format                        */
-#define  SPI_CR1_SSI                         0x00000100U        /*!< Internal slave select               */
-#define  SPI_CR1_SSM                         0x00000200U        /*!< Software slave management           */
-#define  SPI_CR1_RXONLY                      0x00000400U        /*!< Receive only                        */
-#define  SPI_CR1_CRCL                        0x00000800U        /*!< CRC Length                          */
-#define  SPI_CR1_CRCNEXT                     0x00001000U        /*!< Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       0x00002000U        /*!< Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      0x00004000U        /*!< Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    0x00008000U        /*!< Bidirectional data mode enable      */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     0x00000001U        /*!< Rx Buffer DMA Enable                 */
-#define  SPI_CR2_TXDMAEN                     0x00000002U        /*!< Tx Buffer DMA Enable                 */
-#define  SPI_CR2_SSOE                        0x00000004U        /*!< SS Output Enable                     */
-#define  SPI_CR2_NSSP                        0x00000008U        /*!< NSS pulse management Enable          */
-#define  SPI_CR2_FRF                         0x00000010U        /*!< Frame Format Enable                  */
-#define  SPI_CR2_ERRIE                       0x00000020U        /*!< Error Interrupt Enable               */
-#define  SPI_CR2_RXNEIE                      0x00000040U        /*!< RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       0x00000080U        /*!< Tx buffer Empty Interrupt Enable     */
-#define  SPI_CR2_DS                          0x00000F00U        /*!< DS[3:0] Data Size                    */
-#define  SPI_CR2_DS_0                        0x00000100U        /*!< Bit 0 */
-#define  SPI_CR2_DS_1                        0x00000200U        /*!< Bit 1 */
-#define  SPI_CR2_DS_2                        0x00000400U        /*!< Bit 2 */
-#define  SPI_CR2_DS_3                        0x00000800U        /*!< Bit 3 */
-#define  SPI_CR2_FRXTH                       0x00001000U        /*!< FIFO reception Threshold           */
-#define  SPI_CR2_LDMARX                      0x00002000U        /*!< Last DMA transfer for reception    */
-#define  SPI_CR2_LDMATX                      0x00004000U        /*!< Last DMA transfer for transmission */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         0x00000001U        /*!< Receive buffer Not Empty  */
-#define  SPI_SR_TXE                          0x00000002U        /*!< Transmit buffer Empty     */
-#define  SPI_SR_CHSIDE                       0x00000004U        /*!< Channel side              */
-#define  SPI_SR_UDR                          0x00000008U        /*!< Underrun flag             */
-#define  SPI_SR_CRCERR                       0x00000010U        /*!< CRC Error flag            */
-#define  SPI_SR_MODF                         0x00000020U        /*!< Mode fault                */
-#define  SPI_SR_OVR                          0x00000040U        /*!< Overrun flag              */
-#define  SPI_SR_BSY                          0x00000080U        /*!< Busy flag                 */
-#define  SPI_SR_FRE                          0x00000100U        /*!< TI frame format error     */
-#define  SPI_SR_FRLVL                        0x00000600U        /*!< FIFO Reception Level      */
-#define  SPI_SR_FRLVL_0                      0x00000200U        /*!< Bit 0 */
-#define  SPI_SR_FRLVL_1                      0x00000400U        /*!< Bit 1 */
-#define  SPI_SR_FTLVL                        0x00001800U        /*!< FIFO Transmission Level   */
-#define  SPI_SR_FTLVL_0                      0x00000800U        /*!< Bit 0 */
-#define  SPI_SR_FTLVL_1                      0x00001000U        /*!< Bit 1 */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           0xFFFFU            /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   0xFFFFU            /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    0xFFFFU            /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    0xFFFFU            /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   0x00000001U        /*!<Channel length (number of bits per audio channel) */
-#define  SPI_I2SCFGR_DATLEN                  0x00000006U        /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define  SPI_I2SCFGR_DATLEN_0                0x00000002U        /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                0x00000004U        /*!<Bit 1 */
-#define  SPI_I2SCFGR_CKPOL                   0x00000008U        /*!<steady state clock polarity                       */
-#define  SPI_I2SCFGR_I2SSTD                  0x00000030U        /*!<I2SSTD[1:0] bits (I2S standard selection)         */
-#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U        /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U        /*!<Bit 1 */
-#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U        /*!<PCM frame synchronization                         */
-#define  SPI_I2SCFGR_I2SCFG                  0x00000300U        /*!<I2SCFG[1:0] bits (I2S configuration mode)         */
-#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U        /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U        /*!<Bit 1 */
-#define  SPI_I2SCFGR_I2SE                    0x00000400U        /*!<I2S Enable                                        */
-#define  SPI_I2SCFGR_I2SMOD                  0x00000800U        /*!<I2S mode selection                                */
-#define  SPI_I2SCFGR_ASTRTEN                 0x00001000U        /*!<Asynchronous start enable                        */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    0x00FFU            /*!<I2S Linear prescaler         */
-#define  SPI_I2SPR_ODD                       0x0100U            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     0x0200U            /*!<Master Clock Output Enable   */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 SYSCFG                                     */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SYSCFG_MEMRMP register  ***************/
-#define SYSCFG_MEMRMP_MEM_BOOT         0x00000001U /*!< Boot information after Reset */
-
-
-#define SYSCFG_MEMRMP_SWP_FMC          0x00000C00U /*!< FMC Memory Mapping swapping */
-#define SYSCFG_MEMRMP_SWP_FMC_0        0x00000400U
-#define SYSCFG_MEMRMP_SWP_FMC_1        0x00000800U
-
-/******************  Bit definition for SYSCFG_PMC register  ******************/
-
-#define SYSCFG_PMC_ADCxDC2              0x00070000U /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC1DC2              0x00010000U /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC2DC2              0x00020000U /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC3DC2              0x00040000U /*!< Refer to AN4073 on how to use this bit  */
-
-#define SYSCFG_PMC_MII_RMII_SEL         0x00800000U /*!<Ethernet PHY interface selection */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
-/**
-  * @brief   EXTI0 configuration
-  */
-#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         0x0003U /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         0x0004U /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         0x0005U /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         0x0006U /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PI         0x0008U /*!<PI[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PJ         0x0009U /*!<PJ[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PK         0x000AU /*!<PK[0] pin */
-
-/**
-  * @brief   EXTI1 configuration
-  */
-#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         0x0030U /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         0x0040U /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         0x0050U /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         0x0060U /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PI         0x0080U /*!<PI[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PJ         0x0090U /*!<PJ[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PK         0x00A0U /*!<PK[1] pin */
-
-/**
-  * @brief   EXTI2 configuration
-  */
-#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         0x0300U /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         0x0400U /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         0x0500U /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         0x0600U /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PI         0x0800U /*!<PI[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PJ         0x0900U /*!<PJ[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PK         0x0A00U /*!<PK[2] pin */
-
-/**
-  * @brief   EXTI3 configuration
-  */
-#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         0x3000U /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         0x4000U /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         0x5000U /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         0x6000U /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PI         0x8000U /*!<PI[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PJ         0x9000U /*!<PJ[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PK         0xA000U /*!<PK[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
-/**
-  * @brief   EXTI4 configuration
-  */
-#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         0x0003U /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         0x0004U /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         0x0005U /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         0x0006U /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PI         0x0008U /*!<PI[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PJ         0x0009U /*!<PJ[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PK         0x000AU /*!<PK[4] pin */
-
-/**
-  * @brief   EXTI5 configuration
-  */
-#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         0x0030U /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         0x0040U /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         0x0050U /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         0x0060U /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PI         0x0080U /*!<PI[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PJ         0x0090U /*!<PJ[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PK         0x00A0U /*!<PK[5] pin */
-
-/**
-  * @brief   EXTI6 configuration
-  */
-#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         0x0300U /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         0x0400U /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         0x0500U /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         0x0600U /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PI         0x0800U /*!<PI[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PJ         0x0900U /*!<PJ[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PK         0x0A00U /*!<PK[6] pin */
-
-/**
-  * @brief   EXTI7 configuration
-  */
-#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         0x3000U /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         0x4000U /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         0x5000U /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         0x6000U /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PI         0x8000U /*!<PI[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PJ         0x9000U /*!<PJ[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PK         0xA000U /*!<PK[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
-
-/**
-  * @brief   EXTI8 configuration
-  */
-#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         0x0003U /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         0x0004U /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         0x0005U /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         0x0006U /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PI         0x0008U /*!<PI[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PJ         0x0009U /*!<PJ[8] pin */
-
-/**
-  * @brief   EXTI9 configuration
-  */
-#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         0x0030U /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         0x0040U /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         0x0050U /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         0x0060U /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PI         0x0080U /*!<PI[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PJ         0x0090U /*!<PJ[9] pin */
-
-/**
-  * @brief   EXTI10 configuration
-  */
-#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        0x0300U /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        0x0400U /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        0x0500U /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        0x0600U /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PI        0x0800U /*!<PI[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PJ        0x0900U /*!<PJ[10] pin */
-
-/**
-  * @brief   EXTI11 configuration
-  */
-#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        0x3000U /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        0x4000U /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        0x5000U /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        0x6000U /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PI        0x8000U /*!<PI[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PJ        0x9000U /*!<PJ[11] pin */
-
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
-/**
-  * @brief   EXTI12 configuration
-  */
-#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        0x0003U /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        0x0004U /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        0x0005U /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        0x0006U /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PI        0x0008U /*!<PI[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PJ        0x0009U /*!<PJ[12] pin */
-
-/**
-  * @brief   EXTI13 configuration
-  */
-#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        0x0030U /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        0x0040U /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        0x0050U /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        0x0060U /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PI        0x0080U /*!<PI[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PJ        0x0090U /*!<PJ[13] pin */
-
-/**
-  * @brief   EXTI14 configuration
-  */
-#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        0x0300U /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        0x0400U /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        0x0500U /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        0x0600U /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PI        0x0800U /*!<PI[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PJ        0x0900U /*!<PJ[14] pin */
-
-/**
-  * @brief   EXTI15 configuration
-  */
-#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        0x3000U /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        0x4000U /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        0x5000U /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        0x6000U /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PI        0x8000U /*!<PI[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PJ        0x9000U /*!<PJ[15] pin */
-
-
-/******************  Bit definition for SYSCFG_CMPCR register  ****************/
-#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell power-down */
-#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell ready flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    TIM                                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
-#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
-#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
-#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
-#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
-
-#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
-
-#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
-
-#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
-#define  TIM_CR1_UIFREMAP                    0x0800U            /*!<UIF status bit */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        0x00000001U            /*!<Capture/Compare Preloaded Control        */
-#define  TIM_CR2_CCUS                        0x00000004U            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        0x00000008U            /*!<Capture/Compare DMA Selection            */
-
-#define  TIM_CR2_OIS5                        0x00010000U            /*!<Output Idle state 4 (OC4 output) */
-#define  TIM_CR2_OIS6                        0x00040000U            /*!<Output Idle state 4 (OC4 output) */
-
-#define  TIM_CR2_MMS                         0x0070U           /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       0x0010U           /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       0x0020U           /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       0x0040U           /*!<Bit 2 */
-
-#define  TIM_CR2_MMS2                        0x00F00000U            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS2_0                      0x00100000U            /*!<Bit 0 */
-#define  TIM_CR2_MMS2_1                      0x00200000U            /*!<Bit 1 */
-#define  TIM_CR2_MMS2_2                      0x00400000U            /*!<Bit 2 */
-#define  TIM_CR2_MMS2_3                      0x00800000U            /*!<Bit 2 */
-
-#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
-#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
-#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
-#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        0x00010007U            /*!<SMS[2:0] bits (Slave mode selection)    */
-#define  TIM_SMCR_SMS_0                      0x00000001U            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      0x00000002U            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      0x00000004U            /*!<Bit 2 */
-#define  TIM_SMCR_SMS_3                      0x00010000U            /*!<Bit 3 */
-#define  TIM_SMCR_OCCS                       0x00000008U            /*!< OCREF clear selection */
-
-#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
-#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
-
-#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
-
-#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
-
-#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
-#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
-#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
-#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
-#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
-#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
-#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
-#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
-#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
-#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
-#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
-#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
-#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
-#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
-#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
-#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
-#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
-#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
-#define  TIM_SR_B2IF                         0x0100U            /*!<Break2 interrupt Flag               */
-#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          0x00000001U               /*!<Update Generation                         */
-#define  TIM_EGR_CC1G                        0x00000002U               /*!<Capture/Compare 1 Generation              */
-#define  TIM_EGR_CC2G                        0x00000004U               /*!<Capture/Compare 2 Generation              */
-#define  TIM_EGR_CC3G                        0x00000008U               /*!<Capture/Compare 3 Generation              */
-#define  TIM_EGR_CC4G                        0x00000010U               /*!<Capture/Compare 4 Generation              */
-#define  TIM_EGR_COMG                        0x00000020U               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          0x00000040U               /*!<Trigger Generation                        */
-#define  TIM_EGR_BG                          0x00000080U               /*!<Break Generation                          */
-#define  TIM_EGR_B2G                         0x00000100U              /*!<Break2 Generation                          */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      0x00000003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    0x00000001U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    0x00000002U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC1FE                     0x00000004U            /*!<Output Compare 1 Fast enable                 */
-#define  TIM_CCMR1_OC1PE                     0x00000008U            /*!<Output Compare 1 Preload enable              */
-
-#define  TIM_CCMR1_OC1M                      0x00010070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define  TIM_CCMR1_OC1M_0                    0x00000010U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    0x00000020U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    0x00000040U            /*!<Bit 2 */
-#define  TIM_CCMR1_OC1M_3                    0x00010000U            /*!<Bit 3 */
-
-#define  TIM_CCMR1_OC1CE                     0x00000080U            /*!<Output Compare 1Clear Enable                 */
-
-#define  TIM_CCMR1_CC2S                      0x00000300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    0x00000100U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    0x00000200U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC2FE                     0x00000400U            /*!<Output Compare 2 Fast enable                 */
-#define  TIM_CCMR1_OC2PE                     0x00000800U            /*!<Output Compare 2 Preload enable              */
-
-#define  TIM_CCMR1_OC2M                      0x01007000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define  TIM_CCMR1_OC2M_0                    0x00001000U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    0x00002000U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    0x00004000U            /*!<Bit 2 */
-#define  TIM_CCMR1_OC2M_3                    0x01000000U            /*!<Bit 3 */
-
-#define  TIM_CCMR1_OC2CE                     0x00008000U            /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      0x00000003U        /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define  TIM_CCMR2_CC3S_0                    0x00000001U        /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    0x00000002U        /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC3FE                     0x00000004U        /*!<Output Compare 3 Fast enable           */
-#define  TIM_CCMR2_OC3PE                     0x00000008U        /*!<Output Compare 3 Preload enable        */
-
-#define  TIM_CCMR2_OC3M                      0x00010070U        /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    0x00000010U        /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    0x00000020U        /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    0x00000040U        /*!<Bit 2 */
-#define  TIM_CCMR2_OC3M_3                    0x00010000U        /*!<Bit 3 */
-
-
-
-#define  TIM_CCMR2_OC3CE                     0x00000080U        /*!<Output Compare 3 Clear Enable */
-
-#define  TIM_CCMR2_CC4S                      0x00000300U        /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    0x00000100U        /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    0x00000200U        /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC4FE                     0x00000400U        /*!<Output Compare 4 Fast enable    */
-#define  TIM_CCMR2_OC4PE                     0x00000800U        /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR2_OC4M                      0x01007000U        /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    0x00001000U        /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    0x00002000U        /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    0x00004000U        /*!<Bit 2 */
-#define  TIM_CCMR2_OC4M_3                    0x01000000U        /*!<Bit 3 */
-
-#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       0x00000001U            /*!<Capture/Compare 1 output enable */
-#define  TIM_CCER_CC1P                       0x00000002U            /*!<Capture/Compare 1 output Polarity */
-#define  TIM_CCER_CC1NE                      0x00000004U            /*!<Capture/Compare 1 Complementary output enable */
-#define  TIM_CCER_CC1NP                      0x00000008U            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       0x00000010U            /*!<Capture/Compare 2 output enable */
-#define  TIM_CCER_CC2P                       0x00000020U            /*!<Capture/Compare 2 output Polarity */
-#define  TIM_CCER_CC2NE                      0x00000040U            /*!<Capture/Compare 2 Complementary output enable */
-#define  TIM_CCER_CC2NP                      0x00000080U            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       0x00000100U            /*!<Capture/Compare 3 output enable */
-#define  TIM_CCER_CC3P                       0x00000200U            /*!<Capture/Compare 3 output Polarity */
-#define  TIM_CCER_CC3NE                      0x00000400U            /*!<Capture/Compare 3 Complementary output enable */
-#define  TIM_CCER_CC3NP                      0x00000800U            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       0x00001000U            /*!<Capture/Compare 4 output enable */
-#define  TIM_CCER_CC4P                       0x00002000U            /*!<Capture/Compare 4 output Polarity */
-#define  TIM_CCER_CC4NP                      0x00008000U            /*!<Capture/Compare 4 Complementary output Polarity */
-#define  TIM_CCER_CC5E                       0x00010000U            /*!<Capture/Compare 5 output enable */
-#define  TIM_CCER_CC5P                       0x00020000U            /*!<Capture/Compare 5 output Polarity */
-#define  TIM_CCER_CC6E                       0x00100000U            /*!<Capture/Compare 6 output enable */
-#define  TIM_CCER_CC6P                       0x00200000U            /*!<Capture/Compare 6 output Polarity */
-
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         ((uint8_t)0xFFU)               /*!<Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
-
-/*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        0x000000FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      0x00000001U            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      0x00000002U            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      0x00000004U            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      0x00000008U            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      0x00000010U            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      0x00000020U            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      0x00000040U            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      0x00000080U            /*!<Bit 7 */
-
-#define  TIM_BDTR_LOCK                       0x00000300U            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     0x00000100U            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     0x00000200U            /*!<Bit 1 */
-
-#define  TIM_BDTR_OSSI                       0x00000400U            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       0x00000800U            /*!<Off-State Selection for Run mode  */
-#define  TIM_BDTR_BKE                        0x00001000U            /*!<Break enable                      */
-#define  TIM_BDTR_BKP                        0x00002000U            /*!<Break Polarity                    */
-#define  TIM_BDTR_AOE                        0x00004000U            /*!<Automatic Output enable           */
-#define  TIM_BDTR_MOE                        0x00008000U            /*!<Main Output enable                */
-#define  TIM_BDTR_BKF                        0x000F0000U            /*!<Break Filter for Break1 */
-#define  TIM_BDTR_BK2F                       0x00F00000U            /*!<Break Filter for Break2 */
-#define  TIM_BDTR_BK2E                       0x01000000U            /*!<Break enable for Break2 */
-#define  TIM_BDTR_BK2P                       0x02000000U            /*!<Break Polarity for Break2 */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
-
-#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
-
-/*******************  Bit definition for TIM_OR regiter  *********************/
-#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
-#define TIM_OR_ITR1_RMP                      0x0C00U            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
-#define TIM_OR_ITR1_RMP_0                    0x0400U            /*!<Bit 0 */
-#define TIM_OR_ITR1_RMP_1                    0x0800U            /*!<Bit 1 */
-
-/******************  Bit definition for TIM_CCMR3 register  *******************/
-#define  TIM_CCMR3_OC5FE                     0x00000004U            /*!<Output Compare 5 Fast enable */
-#define  TIM_CCMR3_OC5PE                     0x00000008U            /*!<Output Compare 5 Preload enable */
-
-#define  TIM_CCMR3_OC5M                      0x00010070U            /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
-#define  TIM_CCMR3_OC5M_0                    0x00000010U            /*!<Bit 0 */
-#define  TIM_CCMR3_OC5M_1                    0x00000020U            /*!<Bit 1 */
-#define  TIM_CCMR3_OC5M_2                    0x00000040U            /*!<Bit 2 */
-#define  TIM_CCMR3_OC5M_3                    0x00010000U            /*!<Bit 3 */
-
-#define  TIM_CCMR3_OC5CE                     0x00000080U            /*!<Output Compare 5 Clear Enable */
-
-#define  TIM_CCMR3_OC6FE                     0x00000400U            /*!<Output Compare 4 Fast enable */
-#define  TIM_CCMR3_OC6PE                     0x00000800U            /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR3_OC6M                      0x01007000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR3_OC6M_0                    0x00001000U            /*!<Bit 0 */
-#define  TIM_CCMR3_OC6M_1                    0x00002000U            /*!<Bit 1 */
-#define  TIM_CCMR3_OC6M_2                    0x00004000U            /*!<Bit 2 */
-#define  TIM_CCMR3_OC6M_3                    0x01000000U            /*!<Bit 3 */
-
-#define  TIM_CCMR3_OC6CE                     0x00008000U            /*!<Output Compare 4 Clear Enable */
-
-/*******************  Bit definition for TIM_CCR5 register  *******************/
-#define  TIM_CCR5_CCR5                       0xFFFFFFFFU        /*!<Capture/Compare 5 Value */
-#define  TIM_CCR5_GC5C1                      0x20000000U        /*!<Group Channel 5 and Channel 1 */
-#define  TIM_CCR5_GC5C2                      0x40000000U        /*!<Group Channel 5 and Channel 2 */
-#define  TIM_CCR5_GC5C3                      0x80000000U        /*!<Group Channel 5 and Channel 3 */
-
-/*******************  Bit definition for TIM_CCR6 register  *******************/
-#define  TIM_CCR6_CCR6                       ((uint16_t)0xFFFFU)            /*!<Capture/Compare 6 Value */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Low Power Timer (LPTIM)                            */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for LPTIM_ISR register  *******************/
-#define  LPTIM_ISR_CMPM                         0x00000001U            /*!< Compare match                       */
-#define  LPTIM_ISR_ARRM                         0x00000002U            /*!< Autoreload match                    */
-#define  LPTIM_ISR_EXTTRIG                      0x00000004U            /*!< External trigger edge event         */
-#define  LPTIM_ISR_CMPOK                        0x00000008U            /*!< Compare register update OK          */
-#define  LPTIM_ISR_ARROK                        0x00000010U            /*!< Autoreload register update OK       */
-#define  LPTIM_ISR_UP                           0x00000020U            /*!< Counter direction change down to up */
-#define  LPTIM_ISR_DOWN                         0x00000040U            /*!< Counter direction change up to down */
-
-/******************  Bit definition for LPTIM_ICR register  *******************/
-#define  LPTIM_ICR_CMPMCF                       0x00000001U            /*!< Compare match Clear Flag                       */
-#define  LPTIM_ICR_ARRMCF                       0x00000002U            /*!< Autoreload match Clear Flag                    */
-#define  LPTIM_ICR_EXTTRIGCF                    0x00000004U            /*!< External trigger edge event Clear Flag         */
-#define  LPTIM_ICR_CMPOKCF                      0x00000008U            /*!< Compare register update OK Clear Flag          */
-#define  LPTIM_ICR_ARROKCF                      0x00000010U            /*!< Autoreload register update OK Clear Flag       */
-#define  LPTIM_ICR_UPCF                         0x00000020U            /*!< Counter direction change down to up Clear Flag */
-#define  LPTIM_ICR_DOWNCF                       0x00000040U            /*!< Counter direction change up to down Clear Flag */
-
-/******************  Bit definition for LPTIM_IER register *******************/
-#define  LPTIM_IER_CMPMIE                       0x00000001U            /*!< Compare match Interrupt Enable                       */
-#define  LPTIM_IER_ARRMIE                       0x00000002U            /*!< Autoreload match Interrupt Enable                    */
-#define  LPTIM_IER_EXTTRIGIE                    0x00000004U            /*!< External trigger edge event Interrupt Enable         */
-#define  LPTIM_IER_CMPOKIE                      0x00000008U            /*!< Compare register update OK Interrupt Enable          */
-#define  LPTIM_IER_ARROKIE                      0x00000010U            /*!< Autoreload register update OK Interrupt Enable       */
-#define  LPTIM_IER_UPIE                         0x00000020U            /*!< Counter direction change down to up Interrupt Enable */
-#define  LPTIM_IER_DOWNIE                       0x00000040U            /*!< Counter direction change up to down Interrupt Enable */
-
-/******************  Bit definition for LPTIM_CFGR register*******************/
-#define  LPTIM_CFGR_CKSEL                       0x00000001U             /*!< Clock selector */
-
-#define  LPTIM_CFGR_CKPOL                       0x00000006U             /*!< CKPOL[1:0] bits (Clock polarity) */
-#define  LPTIM_CFGR_CKPOL_0                     0x00000002U             /*!< Bit 0 */
-#define  LPTIM_CFGR_CKPOL_1                     0x00000004U             /*!< Bit 1 */
-
-#define  LPTIM_CFGR_CKFLT                       0x00000018U             /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
-#define  LPTIM_CFGR_CKFLT_0                     0x00000008U             /*!< Bit 0 */
-#define  LPTIM_CFGR_CKFLT_1                     0x00000010U             /*!< Bit 1 */
-
-#define  LPTIM_CFGR_TRGFLT                      0x000000C0U             /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
-#define  LPTIM_CFGR_TRGFLT_0                    0x00000040U             /*!< Bit 0 */
-#define  LPTIM_CFGR_TRGFLT_1                    0x00000080U             /*!< Bit 1 */
-
-#define  LPTIM_CFGR_PRESC                       0x00000E00U             /*!< PRESC[2:0] bits (Clock prescaler) */
-#define  LPTIM_CFGR_PRESC_0                     0x00000200U             /*!< Bit 0 */
-#define  LPTIM_CFGR_PRESC_1                     0x00000400U             /*!< Bit 1 */
-#define  LPTIM_CFGR_PRESC_2                     0x00000800U             /*!< Bit 2 */
-
-#define  LPTIM_CFGR_TRIGSEL                     0x0000E000U             /*!< TRIGSEL[2:0]] bits (Trigger selector) */
-#define  LPTIM_CFGR_TRIGSEL_0                   0x00002000U             /*!< Bit 0 */
-#define  LPTIM_CFGR_TRIGSEL_1                   0x00004000U             /*!< Bit 1 */
-#define  LPTIM_CFGR_TRIGSEL_2                   0x00008000U             /*!< Bit 2 */
-
-#define  LPTIM_CFGR_TRIGEN                      0x00060000U             /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
-#define  LPTIM_CFGR_TRIGEN_0                    0x00020000U             /*!< Bit 0 */
-#define  LPTIM_CFGR_TRIGEN_1                    0x00040000U             /*!< Bit 1 */
-
-#define  LPTIM_CFGR_TIMOUT                      0x00080000U             /*!< Timout enable           */
-#define  LPTIM_CFGR_WAVE                        0x00100000U             /*!< Waveform shape          */
-#define  LPTIM_CFGR_WAVPOL                      0x00200000U             /*!< Waveform shape polarity */
-#define  LPTIM_CFGR_PRELOAD                     0x00400000U             /*!< Reg update mode         */
-#define  LPTIM_CFGR_COUNTMODE                   0x00800000U             /*!< Counter mode enable     */
-#define  LPTIM_CFGR_ENC                         0x01000000U             /*!< Encoder mode enable     */
-
-/******************  Bit definition for LPTIM_CR register  ********************/
-#define  LPTIM_CR_ENABLE                        0x00000001U             /*!< LPTIMer enable                 */
-#define  LPTIM_CR_SNGSTRT                       0x00000002U             /*!< Timer start in single mode     */
-#define  LPTIM_CR_CNTSTRT                       0x00000004U             /*!< Timer start in continuous mode */
-
-/******************  Bit definition for LPTIM_CMP register *******************/
-#define  LPTIM_CMP_CMP                          0x0000FFFFU             /*!< Compare register     */
-
-/******************  Bit definition for LPTIM_ARR register *******************/
-#define  LPTIM_ARR_ARR                          0x0000FFFFU             /*!< Auto reload register */
-
-/******************  Bit definition for LPTIM_CNT register *******************/
-#define  LPTIM_CNT_CNT                          0x0000FFFFU             /*!< Counter register     */
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_UE                        0x00000001U            /*!< USART Enable                                    */
-#define  USART_CR1_RE                        0x00000004U            /*!< Receiver Enable                                 */
-#define  USART_CR1_TE                        0x00000008U            /*!< Transmitter Enable                              */
-#define  USART_CR1_IDLEIE                    0x00000010U            /*!< IDLE Interrupt Enable                           */
-#define  USART_CR1_RXNEIE                    0x00000020U            /*!< RXNE Interrupt Enable                           */
-#define  USART_CR1_TCIE                      0x00000040U            /*!< Transmission Complete Interrupt Enable          */
-#define  USART_CR1_TXEIE                     0x00000080U            /*!< TXE Interrupt Enable                            */
-#define  USART_CR1_PEIE                      0x00000100U            /*!< PE Interrupt Enable                             */
-#define  USART_CR1_PS                        0x00000200U            /*!< Parity Selection                                */
-#define  USART_CR1_PCE                       0x00000400U            /*!< Parity Control Enable                           */
-#define  USART_CR1_WAKE                      0x00000800U            /*!< Receiver Wakeup method                          */
-#define  USART_CR1_M                         0x10001000U            /*!< Word length                                     */
-#define  USART_CR1_M_0                       0x00001000U            /*!< Word length - Bit 0                             */
-#define  USART_CR1_MME                       0x00002000U            /*!< Mute Mode Enable                                */
-#define  USART_CR1_CMIE                      0x00004000U            /*!< Character match interrupt enable                */
-#define  USART_CR1_OVER8                     0x00008000U            /*!< Oversampling by 8-bit or 16-bit mode            */
-#define  USART_CR1_DEDT                      0x001F0000U            /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
-#define  USART_CR1_DEDT_0                    0x00010000U            /*!< Bit 0 */
-#define  USART_CR1_DEDT_1                    0x00020000U            /*!< Bit 1 */
-#define  USART_CR1_DEDT_2                    0x00040000U            /*!< Bit 2 */
-#define  USART_CR1_DEDT_3                    0x00080000U            /*!< Bit 3 */
-#define  USART_CR1_DEDT_4                    0x00100000U            /*!< Bit 4 */
-#define  USART_CR1_DEAT                      0x03E00000U            /*!< DEAT[4:0] bits (Driver Enable Assertion Time)   */
-#define  USART_CR1_DEAT_0                    0x00200000U            /*!< Bit 0 */
-#define  USART_CR1_DEAT_1                    0x00400000U            /*!< Bit 1 */
-#define  USART_CR1_DEAT_2                    0x00800000U            /*!< Bit 2 */
-#define  USART_CR1_DEAT_3                    0x01000000U            /*!< Bit 3 */
-#define  USART_CR1_DEAT_4                    0x02000000U            /*!< Bit 4 */
-#define  USART_CR1_RTOIE                     0x04000000U            /*!< Receive Time Out interrupt enable */
-#define  USART_CR1_EOBIE                     0x08000000U            /*!< End of Block interrupt enable     */
-#define  USART_CR1_M_1                       0x10000000U            /*!< Word length - Bit 1               */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADDM7                     0x00000010U            /*!< 7-bit or 4-bit Address Detection       */
-#define  USART_CR2_LBDL                      0x00000020U            /*!< LIN Break Detection Length             */
-#define  USART_CR2_LBDIE                     0x00000040U            /*!< LIN Break Detection Interrupt Enable   */
-#define  USART_CR2_LBCL                      0x00000100U            /*!< Last Bit Clock pulse                   */
-#define  USART_CR2_CPHA                      0x00000200U            /*!< Clock Phase                            */
-#define  USART_CR2_CPOL                      0x00000400U            /*!< Clock Polarity                         */
-#define  USART_CR2_CLKEN                     0x00000800U            /*!< Clock Enable                           */
-#define  USART_CR2_STOP                      0x00003000U            /*!< STOP[1:0] bits (STOP bits)             */
-#define  USART_CR2_STOP_0                    0x00001000U            /*!< Bit 0 */
-#define  USART_CR2_STOP_1                    0x00002000U            /*!< Bit 1 */
-#define  USART_CR2_LINEN                     0x00004000U            /*!< LIN mode enable                        */
-#define  USART_CR2_SWAP                      0x00008000U            /*!< SWAP TX/RX pins                        */
-#define  USART_CR2_RXINV                     0x00010000U            /*!< RX pin active level inversion          */
-#define  USART_CR2_TXINV                     0x00020000U            /*!< TX pin active level inversion          */
-#define  USART_CR2_DATAINV                   0x00040000U            /*!< Binary data inversion                  */
-#define  USART_CR2_MSBFIRST                  0x00080000U            /*!< Most Significant Bit First             */
-#define  USART_CR2_ABREN                     0x00100000U            /*!< Auto Baud-Rate Enable                  */
-#define  USART_CR2_ABRMODE                   0x00600000U            /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
-#define  USART_CR2_ABRMODE_0                 0x00200000U            /*!< Bit 0 */
-#define  USART_CR2_ABRMODE_1                 0x00400000U            /*!< Bit 1 */
-#define  USART_CR2_RTOEN                     0x00800000U            /*!< Receiver Time-Out enable  */
-#define  USART_CR2_ADD                       0xFF000000U            /*!< Address of the USART node */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       0x00000001U            /*!< Error Interrupt Enable                         */
-#define  USART_CR3_IREN                      0x00000002U            /*!< IrDA mode Enable                               */
-#define  USART_CR3_IRLP                      0x00000004U            /*!< IrDA Low-Power                                 */
-#define  USART_CR3_HDSEL                     0x00000008U            /*!< Half-Duplex Selection                          */
-#define  USART_CR3_NACK                      0x00000010U            /*!< SmartCard NACK enable                          */
-#define  USART_CR3_SCEN                      0x00000020U            /*!< SmartCard mode enable                          */
-#define  USART_CR3_DMAR                      0x00000040U            /*!< DMA Enable Receiver                            */
-#define  USART_CR3_DMAT                      0x00000080U            /*!< DMA Enable Transmitter                         */
-#define  USART_CR3_RTSE                      0x00000100U            /*!< RTS Enable                                     */
-#define  USART_CR3_CTSE                      0x00000200U            /*!< CTS Enable                                     */
-#define  USART_CR3_CTSIE                     0x00000400U            /*!< CTS Interrupt Enable                           */
-#define  USART_CR3_ONEBIT                    0x00000800U            /*!< One sample bit method enable                   */
-#define  USART_CR3_OVRDIS                    0x00001000U            /*!< Overrun Disable                                */
-#define  USART_CR3_DDRE                      0x00002000U            /*!< DMA Disable on Reception Error                 */
-#define  USART_CR3_DEM                       0x00004000U            /*!< Driver Enable Mode                             */
-#define  USART_CR3_DEP                       0x00008000U            /*!< Driver Enable Polarity Selection               */
-#define  USART_CR3_SCARCNT                   0x000E0000U            /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
-#define  USART_CR3_SCARCNT_0                 0x00020000U            /*!< Bit 0 */
-#define  USART_CR3_SCARCNT_1                 0x00040000U            /*!< Bit 1 */
-#define  USART_CR3_SCARCNT_2                 0x00080000U            /*!< Bit 2 */
-
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_FRACTION              0x000FU                /*!< Fraction of USARTDIV */
-#define  USART_BRR_DIV_MANTISSA              0xFFF0U                /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      0x00FFU                /*!< PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_GT                       0xFF00U                /*!< GT[7:0] bits (Guard time value) */
-
-
-/*******************  Bit definition for USART_RTOR register  *****************/
-#define  USART_RTOR_RTO                      0x00FFFFFFU            /*!< Receiver Time Out Value */
-#define  USART_RTOR_BLEN                     0xFF000000U            /*!< Block Length */
-
-/*******************  Bit definition for USART_RQR register  ******************/
-#define  USART_RQR_ABRRQ                     0x0001U                /*!< Auto-Baud Rate Request      */
-#define  USART_RQR_SBKRQ                     0x0002U                /*!< Send Break Request          */
-#define  USART_RQR_MMRQ                      0x0004U                /*!< Mute Mode Request           */
-#define  USART_RQR_RXFRQ                     0x0008U                /*!< Receive Data flush Request  */
-#define  USART_RQR_TXFRQ                     0x0010U                /*!< Transmit data flush Request */
-
-/*******************  Bit definition for USART_ISR register  ******************/
-#define  USART_ISR_PE                        0x00000001U            /*!< Parity Error                        */
-#define  USART_ISR_FE                        0x00000002U            /*!< Framing Error                       */
-#define  USART_ISR_NE                        0x00000004U            /*!< Noise detected Flag                 */
-#define  USART_ISR_ORE                       0x00000008U            /*!< OverRun Error                       */
-#define  USART_ISR_IDLE                      0x00000010U            /*!< IDLE line detected                  */
-#define  USART_ISR_RXNE                      0x00000020U            /*!< Read Data Register Not Empty        */
-#define  USART_ISR_TC                        0x00000040U            /*!< Transmission Complete               */
-#define  USART_ISR_TXE                       0x00000080U            /*!< Transmit Data Register Empty        */
-#define  USART_ISR_LBDF                      0x00000100U            /*!< LIN Break Detection Flag            */
-#define  USART_ISR_CTSIF                     0x00000200U            /*!< CTS interrupt flag                  */
-#define  USART_ISR_CTS                       0x00000400U            /*!< CTS flag                            */
-#define  USART_ISR_RTOF                      0x00000800U            /*!< Receiver Time Out                   */
-#define  USART_ISR_EOBF                      0x00001000U            /*!< End Of Block Flag                   */
-#define  USART_ISR_ABRE                      0x00004000U            /*!< Auto-Baud Rate Error                */
-#define  USART_ISR_ABRF                      0x00008000U            /*!< Auto-Baud Rate Flag                 */
-#define  USART_ISR_BUSY                      0x00010000U            /*!< Busy Flag                           */
-#define  USART_ISR_CMF                       0x00020000U            /*!< Character Match Flag                */
-#define  USART_ISR_SBKF                      0x00040000U            /*!< Send Break Flag                     */
-#define  USART_ISR_RWU                       0x00080000U            /*!< Receive Wake Up from mute mode Flag */
-#define  USART_ISR_WUF                       0x00100000U            /*!< Wake Up from stop mode Flag         */
-#define  USART_ISR_TEACK                     0x00200000U            /*!< Transmit Enable Acknowledge Flag    */
-#define  USART_ISR_REACK                     0x00400000U            /*!< Receive Enable Acknowledge Flag     */
-
-/* Legacy define */
-#define  USART_ISR_LBD                       USART_ISR_LBDF
-
-/*******************  Bit definition for USART_ICR register  ******************/
-#define  USART_ICR_PECF                      0x00000001U            /*!< Parity Error Clear Flag             */
-#define  USART_ICR_FECF                      0x00000002U            /*!< Framing Error Clear Flag            */
-#define  USART_ICR_NCF                       0x00000004U            /*!< Noise detected Clear Flag           */
-#define  USART_ICR_ORECF                     0x00000008U            /*!< OverRun Error Clear Flag            */
-#define  USART_ICR_IDLECF                    0x00000010U            /*!< IDLE line detected Clear Flag       */
-#define  USART_ICR_TCCF                      0x00000040U            /*!< Transmission Complete Clear Flag    */
-#define  USART_ICR_LBDCF                     0x00000100U            /*!< LIN Break Detection Clear Flag      */
-#define  USART_ICR_CTSCF                     0x00000200U            /*!< CTS Interrupt Clear Flag            */
-#define  USART_ICR_RTOCF                     0x00000800U            /*!< Receiver Time Out Clear Flag        */
-#define  USART_ICR_EOBCF                     0x00001000U            /*!< End Of Block Clear Flag             */
-#define  USART_ICR_CMCF                      0x00020000U            /*!< Character Match Clear Flag          */
-#define  USART_ICR_WUCF                      0x00100000U            /*!< Wake Up from stop mode Clear Flag   */
-
-/*******************  Bit definition for USART_RDR register  ******************/
-#define  USART_RDR_RDR                       0x01FFU                /*!< RDR[8:0] bits (Receive Data value) */
-
-/*******************  Bit definition for USART_TDR register  ******************/
-#define  USART_TDR_TDR                       0x01FFU                /*!< TDR[8:0] bits (Transmit Data value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Window WATCHDOG                                 */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                            0x7FU                 /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T_0                          0x01U                 /*!<Bit 0 */
-#define  WWDG_CR_T_1                          0x02U                 /*!<Bit 1 */
-#define  WWDG_CR_T_2                          0x04U                 /*!<Bit 2 */
-#define  WWDG_CR_T_3                          0x08U                 /*!<Bit 3 */
-#define  WWDG_CR_T_4                          0x10U                 /*!<Bit 4 */
-#define  WWDG_CR_T_5                          0x20U                 /*!<Bit 5 */
-#define  WWDG_CR_T_6                          0x40U                 /*!<Bit 6 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0                           WWDG_CR_T_0                      /*!<Bit 0 */
-#define  WWDG_CR_T1                           WWDG_CR_T_1                      /*!<Bit 1 */
-#define  WWDG_CR_T2                           WWDG_CR_T_2                      /*!<Bit 2 */
-#define  WWDG_CR_T3                           WWDG_CR_T_3                      /*!<Bit 3 */
-#define  WWDG_CR_T4                           WWDG_CR_T_4                      /*!<Bit 4 */
-#define  WWDG_CR_T5                           WWDG_CR_T_5                      /*!<Bit 5 */
-#define  WWDG_CR_T6                           WWDG_CR_T_6                      /*!<Bit 6 */
-
-#define  WWDG_CR_WDGA                        0x80U                  /*!<Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          0x007FU                /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W_0                        0x0001U                /*!<Bit 0 */
-#define  WWDG_CFR_W_1                        0x0002U                /*!<Bit 1 */
-#define  WWDG_CFR_W_2                        0x0004U                /*!<Bit 2 */
-#define  WWDG_CFR_W_3                        0x0008U                /*!<Bit 3 */
-#define  WWDG_CFR_W_4                        0x0010U                /*!<Bit 4 */
-#define  WWDG_CFR_W_5                        0x0020U                /*!<Bit 5 */
-#define  WWDG_CFR_W_6                        0x0040U                /*!<Bit 6 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0                         WWDG_CFR_W_0                      /*!<Bit 0 */
-#define  WWDG_CFR_W1                         WWDG_CFR_W_1                      /*!<Bit 1 */
-#define  WWDG_CFR_W2                         WWDG_CFR_W_2                      /*!<Bit 2 */
-#define  WWDG_CFR_W3                         WWDG_CFR_W_3                      /*!<Bit 3 */
-#define  WWDG_CFR_W4                         WWDG_CFR_W_4                      /*!<Bit 4 */
-#define  WWDG_CFR_W5                         WWDG_CFR_W_5                      /*!<Bit 5 */
-#define  WWDG_CFR_W6                         WWDG_CFR_W_6                      /*!<Bit 6 */
-
-#define  WWDG_CFR_WDGTB                      0x0180U                /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB_0                    0x0080U                /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB_1                    0x0100U                /*!<Bit 1 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0                  /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1                  /*!<Bit 1 */
-
-#define  WWDG_CFR_EWI                        0x0200U               /*!<Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        0x01U                  /*!<Early Wakeup Interrupt Flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                DBG                                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
-#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
-
-/********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
-#define  DBGMCU_CR_DBG_STOP                  0x00000002U
-#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
-#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
-
-#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
-#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U /*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U /*!<Bit 1 */
-
-/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            0x00000001U
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            0x00000002U
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            0x00000004U
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            0x00000020U
-#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           0x00000040U
-#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           0x00000080U
-#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           0x00000100U
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
-#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
-
-/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP            0x00000001U
-#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP            0x00000002U
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP            0x00010000U
-#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP           0x00020000U
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP           0x00040000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                Ethernet MAC Registers bits definitions                     */
-/*                                                                            */
-/******************************************************************************/
-/* Bit definition for Ethernet MAC Control Register register */
-#define ETH_MACCR_WD              0x00800000U  /* Watchdog disable */
-#define ETH_MACCR_JD              0x00400000U  /* Jabber disable */
-#define ETH_MACCR_IFG             0x000E0000U  /* Inter-frame gap */
-#define ETH_MACCR_IFG_96Bit       0x00000000U  /* Minimum IFG between frames during transmission is 96Bit */
-#define ETH_MACCR_IFG_88Bit       0x00020000U  /* Minimum IFG between frames during transmission is 88Bit */
-#define ETH_MACCR_IFG_80Bit       0x00040000U  /* Minimum IFG between frames during transmission is 80Bit */
-#define ETH_MACCR_IFG_72Bit       0x00060000U  /* Minimum IFG between frames during transmission is 72Bit */
-#define ETH_MACCR_IFG_64Bit       0x00080000U  /* Minimum IFG between frames during transmission is 64Bit */
-#define ETH_MACCR_IFG_56Bit       0x000A0000U  /* Minimum IFG between frames during transmission is 56Bit */
-#define ETH_MACCR_IFG_48Bit       0x000C0000U  /* Minimum IFG between frames during transmission is 48Bit */
-#define ETH_MACCR_IFG_40Bit       0x000E0000U  /* Minimum IFG between frames during transmission is 40Bit */
-#define ETH_MACCR_CSD             0x00010000U  /* Carrier sense disable (during transmission) */
-#define ETH_MACCR_FES             0x00004000U  /* Fast ethernet speed */
-#define ETH_MACCR_ROD             0x00002000U  /* Receive own disable */
-#define ETH_MACCR_LM              0x00001000U  /* loopback mode */
-#define ETH_MACCR_DM              0x00000800U  /* Duplex mode */
-#define ETH_MACCR_IPCO            0x00000400U  /* IP Checksum offload */
-#define ETH_MACCR_RD              0x00000200U  /* Retry disable */
-#define ETH_MACCR_APCS            0x00000080U  /* Automatic Pad/CRC stripping */
-#define ETH_MACCR_BL              0x00000060U  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
-                                                       a transmission attempt during retries after a collision: 0 =< r <2^k */
-#define ETH_MACCR_BL_10           0x00000000U  /* k = min (n, 10) */
-#define ETH_MACCR_BL_8            0x00000020U  /* k = min (n, 8) */
-#define ETH_MACCR_BL_4            0x00000040U  /* k = min (n, 4) */
-#define ETH_MACCR_BL_1            0x00000060U  /* k = min (n, 1) */
-#define ETH_MACCR_DC              0x00000010U  /* Defferal check */
-#define ETH_MACCR_TE              0x00000008U  /* Transmitter enable */
-#define ETH_MACCR_RE              0x00000004U  /* Receiver enable */
-
-/* Bit definition for Ethernet MAC Frame Filter Register */
-#define ETH_MACFFR_RA             0x80000000U  /* Receive all */
-#define ETH_MACFFR_HPF            0x00000400U  /* Hash or perfect filter */
-#define ETH_MACFFR_SAF            0x00000200U  /* Source address filter enable */
-#define ETH_MACFFR_SAIF           0x00000100U  /* SA inverse filtering */
-#define ETH_MACFFR_PCF            0x000000C0U  /* Pass control frames: 3 cases */
-#define ETH_MACFFR_PCF_BlockAll                0x00000040U  /* MAC filters all control frames from reaching the application */
-#define ETH_MACFFR_PCF_ForwardAll              0x00000080U  /* MAC forwards all control frames to application even if they fail the Address Filter */
-#define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U  /* MAC forwards control frames that pass the Address Filter. */
-#define ETH_MACFFR_BFD             0x00000020U  /* Broadcast frame disable */
-#define ETH_MACFFR_PAM             0x00000010U  /* Pass all mutlicast */
-#define ETH_MACFFR_DAIF            0x00000008U  /* DA Inverse filtering */
-#define ETH_MACFFR_HM              0x00000004U  /* Hash multicast */
-#define ETH_MACFFR_HU              0x00000002U  /* Hash unicast */
-#define ETH_MACFFR_PM              0x00000001U  /* Promiscuous mode */
-
-/* Bit definition for Ethernet MAC Hash Table High Register */
-#define ETH_MACHTHR_HTH            0xFFFFFFFFU  /* Hash table high */
-
-/* Bit definition for Ethernet MAC Hash Table Low Register */
-#define ETH_MACHTLR_HTL            0xFFFFFFFFU  /* Hash table low */
-
-/* Bit definition for Ethernet MAC MII Address Register */
-#define ETH_MACMIIAR_PA            0x0000F800U  /* Physical layer address */
-#define ETH_MACMIIAR_MR            0x000007C0U  /* MII register in the selected PHY */
-#define ETH_MACMIIAR_CR            0x0000001CU  /* CR clock range: 6 cases */
-#define ETH_MACMIIAR_CR_Div42      0x00000000U  /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
-#define ETH_MACMIIAR_CR_Div62      0x00000004U  /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
-#define ETH_MACMIIAR_CR_Div16      0x00000008U  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
-#define ETH_MACMIIAR_CR_Div26      0x0000000CU  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
-#define ETH_MACMIIAR_CR_Div102     0x00000010U  /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
-#define ETH_MACMIIAR_MW            0x00000002U  /* MII write */
-#define ETH_MACMIIAR_MB            0x00000001U  /* MII busy */
-
-/* Bit definition for Ethernet MAC MII Data Register */
-#define ETH_MACMIIDR_MD            0x0000FFFFU  /* MII data: read/write data from/to PHY */
-
-/* Bit definition for Ethernet MAC Flow Control Register */
-#define ETH_MACFCR_PT              0xFFFF0000U  /* Pause time */
-#define ETH_MACFCR_ZQPD            0x00000080U  /* Zero-quanta pause disable */
-#define ETH_MACFCR_PLT             0x00000030U  /* Pause low threshold: 4 cases */
-#define ETH_MACFCR_PLT_Minus4      0x00000000U  /* Pause time minus 4 slot times */
-#define ETH_MACFCR_PLT_Minus28     0x00000010U  /* Pause time minus 28 slot times */
-#define ETH_MACFCR_PLT_Minus144    0x00000020U  /* Pause time minus 144 slot times */
-#define ETH_MACFCR_PLT_Minus256    0x00000030U  /* Pause time minus 256 slot times */
-#define ETH_MACFCR_UPFD            0x00000008U  /* Unicast pause frame detect */
-#define ETH_MACFCR_RFCE            0x00000004U  /* Receive flow control enable */
-#define ETH_MACFCR_TFCE            0x00000002U  /* Transmit flow control enable */
-#define ETH_MACFCR_FCBBPA          0x00000001U  /* Flow control busy/backpressure activate */
-
-/* Bit definition for Ethernet MAC VLAN Tag Register */
-#define ETH_MACVLANTR_VLANTC       0x00010000U  /* 12-bit VLAN tag comparison */
-#define ETH_MACVLANTR_VLANTI       0x0000FFFFU  /* VLAN tag identifier (for receive frames) */
-
-/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
-#define ETH_MACRWUFFR_D            0xFFFFFFFFU  /* Wake-up frame filter register data */
-/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
-   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
-/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
-   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
-   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
-   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
-   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
-                              RSVD - Filter1 Command - RSVD - Filter0 Command
-   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
-   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
-   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
-
-/* Bit definition for Ethernet MAC PMT Control and Status Register */
-#define ETH_MACPMTCSR_WFFRPR       0x80000000U  /* Wake-Up Frame Filter Register Pointer Reset */
-#define ETH_MACPMTCSR_GU           0x00000200U  /* Global Unicast */
-#define ETH_MACPMTCSR_WFR          0x00000040U  /* Wake-Up Frame Received */
-#define ETH_MACPMTCSR_MPR          0x00000020U  /* Magic Packet Received */
-#define ETH_MACPMTCSR_WFE          0x00000004U  /* Wake-Up Frame Enable */
-#define ETH_MACPMTCSR_MPE          0x00000002U  /* Magic Packet Enable */
-#define ETH_MACPMTCSR_PD           0x00000001U  /* Power Down */
-
-/* Bit definition for Ethernet MAC Status Register */
-#define ETH_MACSR_TSTS      0x00000200U  /* Time stamp trigger status */
-#define ETH_MACSR_MMCTS     0x00000040U  /* MMC transmit status */
-#define ETH_MACSR_MMMCRS    0x00000020U  /* MMC receive status */
-#define ETH_MACSR_MMCS      0x00000010U  /* MMC status */
-#define ETH_MACSR_PMTS      0x00000008U  /* PMT status */
-
-/* Bit definition for Ethernet MAC Interrupt Mask Register */
-#define ETH_MACIMR_TSTIM     0x00000200U  /* Time stamp trigger interrupt mask */
-#define ETH_MACIMR_PMTIM     0x00000008U  /* PMT interrupt mask */
-
-/* Bit definition for Ethernet MAC Address0 High Register */
-#define ETH_MACA0HR_MACA0H   0x0000FFFFU  /* MAC address0 high */
-
-/* Bit definition for Ethernet MAC Address0 Low Register */
-#define ETH_MACA0LR_MACA0L   0xFFFFFFFFU  /* MAC address0 low */
-
-/* Bit definition for Ethernet MAC Address1 High Register */
-#define ETH_MACA1HR_AE       0x80000000U  /* Address enable */
-#define ETH_MACA1HR_SA       0x40000000U  /* Source address */
-#define ETH_MACA1HR_MBC      0x3F000000U  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
-  #define ETH_MACA1HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA1HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA1HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA1HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA1HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA1HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [7:0] */
-#define ETH_MACA1HR_MACA1H            0x0000FFFFU  /* MAC address1 high */
-
-/* Bit definition for Ethernet MAC Address1 Low Register */
-#define ETH_MACA1LR_MACA1L   0xFFFFFFFFU  /* MAC address1 low */
-
-/* Bit definition for Ethernet MAC Address2 High Register */
-#define ETH_MACA2HR_AE       0x80000000U  /* Address enable */
-#define ETH_MACA2HR_SA       0x40000000U  /* Source address */
-#define ETH_MACA2HR_MBC      0x3F000000U  /* Mask byte control */
-  #define ETH_MACA2HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA2HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA2HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA2HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA2HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA2HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA2HR_MACA2H   0x0000FFFFU  /* MAC address1 high */
-
-/* Bit definition for Ethernet MAC Address2 Low Register */
-#define ETH_MACA2LR_MACA2L   0xFFFFFFFFU  /* MAC address2 low */
-
-/* Bit definition for Ethernet MAC Address3 High Register */
-#define ETH_MACA3HR_AE       0x80000000U  /* Address enable */
-#define ETH_MACA3HR_SA       0x40000000U  /* Source address */
-#define ETH_MACA3HR_MBC      0x3F000000U  /* Mask byte control */
-  #define ETH_MACA3HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA3HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA3HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA3HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA3HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA3HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA3HR_MACA3H   0x0000FFFFU  /* MAC address3 high */
-
-/* Bit definition for Ethernet MAC Address3 Low Register */
-#define ETH_MACA3LR_MACA3L   0xFFFFFFFFU  /* MAC address3 low */
-
-/******************************************************************************/
-/*                Ethernet MMC Registers bits definition                      */
-/******************************************************************************/
-
-/* Bit definition for Ethernet MMC Contol Register */
-#define ETH_MMCCR_MCFHP      0x00000020U  /* MMC counter Full-Half preset */
-#define ETH_MMCCR_MCP        0x00000010U  /* MMC counter preset */
-#define ETH_MMCCR_MCF        0x00000008U  /* MMC Counter Freeze */
-#define ETH_MMCCR_ROR        0x00000004U  /* Reset on Read */
-#define ETH_MMCCR_CSR        0x00000002U  /* Counter Stop Rollover */
-#define ETH_MMCCR_CR         0x00000001U  /* Counters Reset */
-
-/* Bit definition for Ethernet MMC Receive Interrupt Register */
-#define ETH_MMCRIR_RGUFS     0x00020000U  /* Set when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIR_RFAES     0x00000040U  /* Set when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIR_RFCES     0x00000020U  /* Set when Rx crc error counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmit Interrupt Register */
-#define ETH_MMCTIR_TGFS      0x00200000U  /* Set when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFMSCS   0x00008000U  /* Set when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFSCS    0x00004000U  /* Set when Tx good single col counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
-#define ETH_MMCRIMR_RGUFM    0x00020000U  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFAEM    0x00000040U  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFCEM    0x00000020U  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
-#define ETH_MMCTIMR_TGFM     0x00200000U  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFMSCM  0x00008000U  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFSCM   0x00004000U  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
-#define ETH_MMCTGFSCCR_TGFSCC     0xFFFFFFFFU  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
-#define ETH_MMCTGFMSCCR_TGFMSCC   0xFFFFFFFFU  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
-#define ETH_MMCTGFCR_TGFC    0xFFFFFFFFU  /* Number of good frames transmitted. */
-
-/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
-#define ETH_MMCRFCECR_RFCEC  0xFFFFFFFFU  /* Number of frames received with CRC error. */
-
-/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
-#define ETH_MMCRFAECR_RFAEC  0xFFFFFFFFU  /* Number of frames received with alignment (dribble) error */
-
-/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
-#define ETH_MMCRGUFCR_RGUFC  0xFFFFFFFFU  /* Number of good unicast frames received. */
-
-/******************************************************************************/
-/*               Ethernet PTP Registers bits definition                       */
-/******************************************************************************/
-
-/* Bit definition for Ethernet PTP Time Stamp Contol Register */
-#define ETH_PTPTSCR_TSCNT       0x00030000U  /* Time stamp clock node type */
-#define ETH_PTPTSSR_TSSMRME     0x00008000U  /* Time stamp snapshot for message relevant to master enable */
-#define ETH_PTPTSSR_TSSEME      0x00004000U  /* Time stamp snapshot for event message enable */
-#define ETH_PTPTSSR_TSSIPV4FE   0x00002000U  /* Time stamp snapshot for IPv4 frames enable */
-#define ETH_PTPTSSR_TSSIPV6FE   0x00001000U  /* Time stamp snapshot for IPv6 frames enable */
-#define ETH_PTPTSSR_TSSPTPOEFE  0x00000800U  /* Time stamp snapshot for PTP over ethernet frames enable */
-#define ETH_PTPTSSR_TSPTPPSV2E  0x00000400U  /* Time stamp PTP packet snooping for version2 format enable */
-#define ETH_PTPTSSR_TSSSR       0x00000200U  /* Time stamp Sub-seconds rollover */
-#define ETH_PTPTSSR_TSSARFE     0x00000100U  /* Time stamp snapshot for all received frames enable */
-
-#define ETH_PTPTSCR_TSARU       0x00000020U  /* Addend register update */
-#define ETH_PTPTSCR_TSITE       0x00000010U  /* Time stamp interrupt trigger enable */
-#define ETH_PTPTSCR_TSSTU       0x00000008U  /* Time stamp update */
-#define ETH_PTPTSCR_TSSTI       0x00000004U  /* Time stamp initialize */
-#define ETH_PTPTSCR_TSFCU       0x00000002U  /* Time stamp fine or coarse update */
-#define ETH_PTPTSCR_TSE         0x00000001U  /* Time stamp enable */
-
-/* Bit definition for Ethernet PTP Sub-Second Increment Register */
-#define ETH_PTPSSIR_STSSI      0x000000FFU   /* System time Sub-second increment value */
-
-/* Bit definition for Ethernet PTP Time Stamp High Register */
-#define ETH_PTPTSHR_STS        0xFFFFFFFFU   /* System Time second */
-
-/* Bit definition for Ethernet PTP Time Stamp Low Register */
-#define ETH_PTPTSLR_STPNS      0x80000000U  /* System Time Positive or negative time */
-#define ETH_PTPTSLR_STSS       0x7FFFFFFFU  /* System Time sub-seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp High Update Register */
-#define ETH_PTPTSHUR_TSUS      0xFFFFFFFFU  /* Time stamp update seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
-#define ETH_PTPTSLUR_TSUPNS    0x80000000U  /* Time stamp update Positive or negative time */
-#define ETH_PTPTSLUR_TSUSS     0x7FFFFFFFU  /* Time stamp update sub-seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp Addend Register */
-#define ETH_PTPTSAR_TSA        0xFFFFFFFFU  /* Time stamp addend */
-
-/* Bit definition for Ethernet PTP Target Time High Register */
-#define ETH_PTPTTHR_TTSH       0xFFFFFFFFU  /* Target time stamp high */
-
-/* Bit definition for Ethernet PTP Target Time Low Register */
-#define ETH_PTPTTLR_TTSL       0xFFFFFFFFU  /* Target time stamp low */
-
-/* Bit definition for Ethernet PTP Time Stamp Status Register */
-#define ETH_PTPTSSR_TSTTR      0x00000020U  /* Time stamp target time reached */
-#define ETH_PTPTSSR_TSSO       0x00000010U  /* Time stamp seconds overflow */
-
-/******************************************************************************/
-/*                 Ethernet DMA Registers bits definition                     */
-/******************************************************************************/
-
-/* Bit definition for Ethernet DMA Bus Mode Register */
-#define ETH_DMABMR_AAB        0x02000000U  /* Address-Aligned beats */
-#define ETH_DMABMR_FPM        0x01000000U  /* 4xPBL mode */
-#define ETH_DMABMR_USP        0x00800000U  /* Use separate PBL */
-#define ETH_DMABMR_RDP        0x007E0000U  /* RxDMA PBL */
-  #define ETH_DMABMR_RDP_1Beat    0x00020000U  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
-  #define ETH_DMABMR_RDP_2Beat    0x00040000U  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
-  #define ETH_DMABMR_RDP_4Beat    0x00080000U  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-  #define ETH_DMABMR_RDP_8Beat    0x00100000U  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-  #define ETH_DMABMR_RDP_16Beat   0x00200000U  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-  #define ETH_DMABMR_RDP_32Beat   0x00400000U  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
-  #define ETH_DMABMR_RDP_4xPBL_4Beat   0x01020000U  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-  #define ETH_DMABMR_RDP_4xPBL_8Beat   0x01040000U  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-  #define ETH_DMABMR_RDP_4xPBL_16Beat  0x01080000U  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-  #define ETH_DMABMR_RDP_4xPBL_32Beat  0x01100000U  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
-  #define ETH_DMABMR_RDP_4xPBL_64Beat  0x01200000U  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
-  #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
-#define ETH_DMABMR_FB        0x00010000U  /* Fixed Burst */
-#define ETH_DMABMR_RTPR      0x0000C000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_1_1     0x00000000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_2_1     0x00004000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_3_1     0x00008000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_4_1     0x0000C000U  /* Rx Tx priority ratio */
-#define ETH_DMABMR_PBL    0x00003F00U  /* Programmable burst length */
-  #define ETH_DMABMR_PBL_1Beat    0x00000100U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
-  #define ETH_DMABMR_PBL_2Beat    0x00000200U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
-  #define ETH_DMABMR_PBL_4Beat    0x00000400U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-  #define ETH_DMABMR_PBL_8Beat    0x00000800U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-  #define ETH_DMABMR_PBL_16Beat   0x00001000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-  #define ETH_DMABMR_PBL_32Beat   0x00002000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
-  #define ETH_DMABMR_PBL_4xPBL_4Beat   0x01000100U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-  #define ETH_DMABMR_PBL_4xPBL_8Beat   0x01000200U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-  #define ETH_DMABMR_PBL_4xPBL_16Beat  0x01000400U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-  #define ETH_DMABMR_PBL_4xPBL_32Beat  0x01000800U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
-  #define ETH_DMABMR_PBL_4xPBL_64Beat  0x01001000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
-  #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
-#define ETH_DMABMR_EDE       0x00000080U  /* Enhanced Descriptor Enable */
-#define ETH_DMABMR_DSL       0x0000007CU  /* Descriptor Skip Length */
-#define ETH_DMABMR_DA        0x00000002U  /* DMA arbitration scheme */
-#define ETH_DMABMR_SR        0x00000001U  /* Software reset */
-
-/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
-#define ETH_DMATPDR_TPD      0xFFFFFFFFU  /* Transmit poll demand */
-
-/* Bit definition for Ethernet DMA Receive Poll Demand Register */
-#define ETH_DMARPDR_RPD      0xFFFFFFFFU  /* Receive poll demand  */
-
-/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
-#define ETH_DMARDLAR_SRL     0xFFFFFFFFU  /* Start of receive list */
-
-/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
-#define ETH_DMATDLAR_STL     0xFFFFFFFFU  /* Start of transmit list */
-
-/* Bit definition for Ethernet DMA Status Register */
-#define ETH_DMASR_TSTS       0x20000000U  /* Time-stamp trigger status */
-#define ETH_DMASR_PMTS       0x10000000U  /* PMT status */
-#define ETH_DMASR_MMCS       0x08000000U  /* MMC status */
-#define ETH_DMASR_EBS        0x03800000U  /* Error bits status */
-  /* combination with EBS[2:0] for GetFlagStatus function */
-  #define ETH_DMASR_EBS_DescAccess      0x02000000U  /* Error bits 0-data buffer, 1-desc. access */
-  #define ETH_DMASR_EBS_ReadTransf      0x01000000U  /* Error bits 0-write trnsf, 1-read transfr */
-  #define ETH_DMASR_EBS_DataTransfTx    0x00800000U  /* Error bits 0-Rx DMA, 1-Tx DMA */
-#define ETH_DMASR_TPS         0x00700000U  /* Transmit process state */
-  #define ETH_DMASR_TPS_Stopped         0x00000000U  /* Stopped - Reset or Stop Tx Command issued  */
-  #define ETH_DMASR_TPS_Fetching        0x00100000U  /* Running - fetching the Tx descriptor */
-  #define ETH_DMASR_TPS_Waiting         0x00200000U  /* Running - waiting for status */
-  #define ETH_DMASR_TPS_Reading         0x00300000U  /* Running - reading the data from host memory */
-  #define ETH_DMASR_TPS_Suspended       0x00600000U  /* Suspended - Tx Descriptor unavailabe */
-  #define ETH_DMASR_TPS_Closing         0x00700000U  /* Running - closing Rx descriptor */
-#define ETH_DMASR_RPS         0x000E0000U  /* Receive process state */
-  #define ETH_DMASR_RPS_Stopped         0x00000000U  /* Stopped - Reset or Stop Rx Command issued */
-  #define ETH_DMASR_RPS_Fetching        0x00020000U  /* Running - fetching the Rx descriptor */
-  #define ETH_DMASR_RPS_Waiting         0x00060000U  /* Running - waiting for packet */
-  #define ETH_DMASR_RPS_Suspended       0x00080000U  /* Suspended - Rx Descriptor unavailable */
-  #define ETH_DMASR_RPS_Closing         0x000A0000U  /* Running - closing descriptor */
-  #define ETH_DMASR_RPS_Queuing         0x000E0000U  /* Running - queuing the recieve frame into host memory */
-#define ETH_DMASR_NIS        0x00010000U  /* Normal interrupt summary */
-#define ETH_DMASR_AIS        0x00008000U  /* Abnormal interrupt summary */
-#define ETH_DMASR_ERS        0x00004000U  /* Early receive status */
-#define ETH_DMASR_FBES       0x00002000U  /* Fatal bus error status */
-#define ETH_DMASR_ETS        0x00000400U  /* Early transmit status */
-#define ETH_DMASR_RWTS       0x00000200U  /* Receive watchdog timeout status */
-#define ETH_DMASR_RPSS       0x00000100U  /* Receive process stopped status */
-#define ETH_DMASR_RBUS       0x00000080U  /* Receive buffer unavailable status */
-#define ETH_DMASR_RS         0x00000040U  /* Receive status */
-#define ETH_DMASR_TUS        0x00000020U  /* Transmit underflow status */
-#define ETH_DMASR_ROS        0x00000010U  /* Receive overflow status */
-#define ETH_DMASR_TJTS       0x00000008U  /* Transmit jabber timeout status */
-#define ETH_DMASR_TBUS       0x00000004U  /* Transmit buffer unavailable status */
-#define ETH_DMASR_TPSS       0x00000002U  /* Transmit process stopped status */
-#define ETH_DMASR_TS         0x00000001U  /* Transmit status */
-
-/* Bit definition for Ethernet DMA Operation Mode Register */
-#define ETH_DMAOMR_DTCEFD    0x04000000U  /* Disable Dropping of TCP/IP checksum error frames */
-#define ETH_DMAOMR_RSF       0x02000000U  /* Receive store and forward */
-#define ETH_DMAOMR_DFRF      0x01000000U  /* Disable flushing of received frames */
-#define ETH_DMAOMR_TSF       0x00200000U  /* Transmit store and forward */
-#define ETH_DMAOMR_FTF       0x00100000U  /* Flush transmit FIFO */
-#define ETH_DMAOMR_TTC       0x0001C000U  /* Transmit threshold control */
-  #define ETH_DMAOMR_TTC_64Bytes       0x00000000U  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
-  #define ETH_DMAOMR_TTC_128Bytes      0x00004000U  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
-  #define ETH_DMAOMR_TTC_192Bytes      0x00008000U  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
-  #define ETH_DMAOMR_TTC_256Bytes      0x0000C000U  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
-  #define ETH_DMAOMR_TTC_40Bytes       0x00010000U  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
-  #define ETH_DMAOMR_TTC_32Bytes       0x00014000U  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
-  #define ETH_DMAOMR_TTC_24Bytes       0x00018000U  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
-  #define ETH_DMAOMR_TTC_16Bytes       0x0001C000U  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
-#define ETH_DMAOMR_ST        0x00002000U  /* Start/stop transmission command */
-#define ETH_DMAOMR_FEF       0x00000080U  /* Forward error frames */
-#define ETH_DMAOMR_FUGF      0x00000040U  /* Forward undersized good frames */
-#define ETH_DMAOMR_RTC       0x00000018U  /* receive threshold control */
-  #define ETH_DMAOMR_RTC_64Bytes       0x00000000U  /* threshold level of the MTL Receive FIFO is 64 Bytes */
-  #define ETH_DMAOMR_RTC_32Bytes       0x00000008U  /* threshold level of the MTL Receive FIFO is 32 Bytes */
-  #define ETH_DMAOMR_RTC_96Bytes       0x00000010U  /* threshold level of the MTL Receive FIFO is 96 Bytes */
-  #define ETH_DMAOMR_RTC_128Bytes      0x00000018U  /* threshold level of the MTL Receive FIFO is 128 Bytes */
-#define ETH_DMAOMR_OSF       0x00000004U  /* operate on second frame */
-#define ETH_DMAOMR_SR        0x00000002U  /* Start/stop receive */
-
-/* Bit definition for Ethernet DMA Interrupt Enable Register */
-#define ETH_DMAIER_NISE      0x00010000U  /* Normal interrupt summary enable */
-#define ETH_DMAIER_AISE      0x00008000U  /* Abnormal interrupt summary enable */
-#define ETH_DMAIER_ERIE      0x00004000U  /* Early receive interrupt enable */
-#define ETH_DMAIER_FBEIE     0x00002000U  /* Fatal bus error interrupt enable */
-#define ETH_DMAIER_ETIE      0x00000400U  /* Early transmit interrupt enable */
-#define ETH_DMAIER_RWTIE     0x00000200U  /* Receive watchdog timeout interrupt enable */
-#define ETH_DMAIER_RPSIE     0x00000100U  /* Receive process stopped interrupt enable */
-#define ETH_DMAIER_RBUIE     0x00000080U  /* Receive buffer unavailable interrupt enable */
-#define ETH_DMAIER_RIE       0x00000040U  /* Receive interrupt enable */
-#define ETH_DMAIER_TUIE      0x00000020U  /* Transmit Underflow interrupt enable */
-#define ETH_DMAIER_ROIE      0x00000010U  /* Receive Overflow interrupt enable */
-#define ETH_DMAIER_TJTIE     0x00000008U  /* Transmit jabber timeout interrupt enable */
-#define ETH_DMAIER_TBUIE     0x00000004U  /* Transmit buffer unavailable interrupt enable */
-#define ETH_DMAIER_TPSIE     0x00000002U  /* Transmit process stopped interrupt enable */
-#define ETH_DMAIER_TIE       0x00000001U  /* Transmit interrupt enable */
-
-/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
-#define ETH_DMAMFBOCR_OFOC   0x10000000U  /* Overflow bit for FIFO overflow counter */
-#define ETH_DMAMFBOCR_MFA    0x0FFE0000U  /* Number of frames missed by the application */
-#define ETH_DMAMFBOCR_OMFC   0x00010000U  /* Overflow bit for missed frame counter */
-#define ETH_DMAMFBOCR_MFC    0x0000FFFFU  /* Number of frames missed by the controller */
-
-/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
-#define ETH_DMACHTDR_HTDAP   0xFFFFFFFFU  /* Host transmit descriptor address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
-#define ETH_DMACHRDR_HRDAP   0xFFFFFFFFU  /* Host receive descriptor address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
-#define ETH_DMACHTBAR_HTBAP  0xFFFFFFFFU  /* Host transmit buffer address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
-#define ETH_DMACHRBAR_HRBAP  0xFFFFFFFFU  /* Host receive buffer address pointer */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                       USB_OTG                              */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for USB_OTG_GOTGCTL register  ********************/
-#define USB_OTG_GOTGCTL_SRQSCS                  0x00000001U         /*!< Session request success */
-#define USB_OTG_GOTGCTL_SRQ                     0x00000002U         /*!< Session request */
-#define USB_OTG_GOTGCTL_VBVALOEN                0x00000004U         /*!< VBUS valid override enable */
-#define USB_OTG_GOTGCTL_VBVALOVAL               0x00000008U         /*!< VBUS valid override value */
-#define USB_OTG_GOTGCTL_AVALOEN                 0x00000010U         /*!< A-peripheral session valid override enable */
-#define USB_OTG_GOTGCTL_AVALOVAL                0x00000020U         /*!< A-peripheral session valid override value */
-#define USB_OTG_GOTGCTL_BVALOEN                 0x00000040U         /*!< B-peripheral session valid override enable */
-#define USB_OTG_GOTGCTL_BVALOVAL                0x00000080U         /*!< B-peripheral session valid override value  */
-#define USB_OTG_GOTGCTL_HNGSCS                  0x00000100U         /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_HNPRQ                   0x00000200U         /*!< HNP request */
-#define USB_OTG_GOTGCTL_HSHNPEN                 0x00000400U         /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_DHNPEN                  0x00000800U         /*!< Device HNP enabled */
-#define USB_OTG_GOTGCTL_EHEN                    0x00001000U         /*!< Embedded host enable */
-#define USB_OTG_GOTGCTL_CIDSTS                  0x00010000U         /*!< Connector ID status */
-#define USB_OTG_GOTGCTL_DBCT                    0x00020000U         /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD                   0x00040000U         /*!< A-session valid  */
-#define USB_OTG_GOTGCTL_BSESVLD                 0x00080000U         /*!< B-session valid */
-#define USB_OTG_GOTGCTL_OTGVER                  0x00100000U         /*!< OTG version  */
-
-/********************  Bit definition for USB_OTG_HCFG register  ********************/
-#define USB_OTG_HCFG_FSLSPCS                 0x00000003U            /*!< FS/LS PHY clock select  */
-#define USB_OTG_HCFG_FSLSPCS_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCFG_FSLSPCS_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCFG_FSLSS                   0x00000004U            /*!< FS- and LS-only support */
-
-/********************  Bit definition for USB_OTG_DCFG register  ********************/
-#define USB_OTG_DCFG_DSPD                    0x00000003U            /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                  0x00000001U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DSPD_1                  0x00000002U            /*!<Bit 1 */
-#define USB_OTG_DCFG_NZLSOHSK                0x00000004U            /*!< Nonzero-length status OUT handshake */
-
-#define USB_OTG_DCFG_DAD                     0x000007F0U            /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                   0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DAD_1                   0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCFG_DAD_2                   0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCFG_DAD_3                   0x00000080U            /*!<Bit 3 */
-#define USB_OTG_DCFG_DAD_4                   0x00000100U            /*!<Bit 4 */
-#define USB_OTG_DCFG_DAD_5                   0x00000200U            /*!<Bit 5 */
-#define USB_OTG_DCFG_DAD_6                   0x00000400U            /*!<Bit 6 */
-
-#define USB_OTG_DCFG_PFIVL                   0x00001800U            /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PFIVL_1                 0x00001000U            /*!<Bit 1 */
-
-#define USB_OTG_DCFG_PERSCHIVL               0x03000000U            /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0             0x01000000U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PERSCHIVL_1             0x02000000U            /*!<Bit 1 */
-
-/********************  Bit definition for USB_OTG_PCGCR register  ********************/
-#define USB_OTG_PCGCR_STPPCLK                 0x00000001U            /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK                0x00000002U            /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP                 0x00000010U            /*!< PHY suspended */
-
-/********************  Bit definition for USB_OTG_GOTGINT register  ********************/
-#define USB_OTG_GOTGINT_SEDET                   0x00000004U            /*!< Session end detected                   */
-#define USB_OTG_GOTGINT_SRSSCHG                 0x00000100U            /*!< Session request success status change  */
-#define USB_OTG_GOTGINT_HNSSCHG                 0x00000200U            /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET                  0x00020000U            /*!< Host negotiation detected              */
-#define USB_OTG_GOTGINT_ADTOCHG                 0x00040000U            /*!< A-device timeout change                */
-#define USB_OTG_GOTGINT_DBCDNE                  0x00080000U            /*!< Debounce done                          */
-#define USB_OTG_GOTGINT_IDCHNG                  0x00100000U            /*!< Change in ID pin input value           */
-
-/********************  Bit definition for USB_OTG_DCTL register  ********************/
-#define USB_OTG_DCTL_RWUSIG                  0x00000001U            /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS                    0x00000002U            /*!< Soft disconnect         */
-#define USB_OTG_DCTL_GINSTS                  0x00000004U            /*!< Global IN NAK status    */
-#define USB_OTG_DCTL_GONSTS                  0x00000008U            /*!< Global OUT NAK status   */
-
-#define USB_OTG_DCTL_TCTL                    0x00000070U            /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                  0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCTL_TCTL_1                  0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCTL_TCTL_2                  0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCTL_SGINAK                  0x00000080U            /*!< Set global IN NAK         */
-#define USB_OTG_DCTL_CGINAK                  0x00000100U            /*!< Clear global IN NAK       */
-#define USB_OTG_DCTL_SGONAK                  0x00000200U            /*!< Set global OUT NAK        */
-#define USB_OTG_DCTL_CGONAK                  0x00000400U            /*!< Clear global OUT NAK      */
-#define USB_OTG_DCTL_POPRGDNE                0x00000800U            /*!< Power-on programming done */
-
-/********************  Bit definition for USB_OTG_HFIR register  ********************/
-#define USB_OTG_HFIR_FRIVL                   0x0000FFFFU            /*!< Frame interval */
-
-/********************  Bit definition for USB_OTG_HFNUM register  ********************/
-#define USB_OTG_HFNUM_FRNUM                   0x0000FFFFU            /*!< Frame number         */
-#define USB_OTG_HFNUM_FTREM                   0xFFFF0000U            /*!< Frame time remaining */
-
-/********************  Bit definition for USB_OTG_DSTS register  ********************/
-#define USB_OTG_DSTS_SUSPSTS                 0x00000001U            /*!< Suspend status   */
-
-#define USB_OTG_DSTS_ENUMSPD                 0x00000006U            /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_DSTS_ENUMSPD_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_DSTS_EERR                    0x00000008U            /*!< Erratic error     */
-#define USB_OTG_DSTS_FNSOF                   0x003FFF00U            /*!< Frame number of the received SOF */
-
-/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
-#define USB_OTG_GAHBCFG_GINT                    0x00000001U            /*!< Global interrupt mask */
-#define USB_OTG_GAHBCFG_HBSTLEN                 0x0000001EU            /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_GAHBCFG_HBSTLEN_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_GAHBCFG_HBSTLEN_2               0x00000008U            /*!<Bit 2 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3               0x00000010U            /*!<Bit 3 */
-#define USB_OTG_GAHBCFG_DMAEN                   0x00000020U            /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL                 0x00000080U            /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL                0x00000100U            /*!< Periodic TxFIFO empty level */
-
-/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
-#define USB_OTG_GUSBCFG_TOCAL                   0x00000007U            /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TOCAL_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TOCAL_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_PHYSEL                  0x00000040U            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP                  0x00000100U            /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP                  0x00000200U            /*!< HNP-capable */
-#define USB_OTG_GUSBCFG_TRDT                    0x00003C00U            /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                  0x00000400U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TRDT_1                  0x00000800U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TRDT_2                  0x00001000U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_TRDT_3                  0x00002000U            /*!<Bit 3 */
-#define USB_OTG_GUSBCFG_PHYLPCS                 0x00008000U            /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS                0x00020000U            /*!< ULPI FS/LS select               */
-#define USB_OTG_GUSBCFG_ULPIAR                  0x00040000U            /*!< ULPI Auto-resume                */
-#define USB_OTG_GUSBCFG_ULPICSM                 0x00080000U            /*!< ULPI Clock SuspendM             */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD              0x00100000U            /*!< ULPI External VBUS Drive        */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI              0x00200000U            /*!< ULPI external VBUS indicator    */
-#define USB_OTG_GUSBCFG_TSDPS                   0x00400000U            /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI                    0x00800000U            /*!< Indicator complement            */
-#define USB_OTG_GUSBCFG_PTCI                    0x01000000U            /*!< Indicator pass through          */
-#define USB_OTG_GUSBCFG_ULPIIPD                 0x02000000U            /*!< ULPI interface protect disable  */
-#define USB_OTG_GUSBCFG_FHMOD                   0x20000000U            /*!< Forced host mode                */
-#define USB_OTG_GUSBCFG_FDMOD                   0x40000000U            /*!< Forced peripheral mode          */
-#define USB_OTG_GUSBCFG_CTXPKT                  0x80000000U            /*!< Corrupt Tx packet               */
-
-/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
-#define USB_OTG_GRSTCTL_CSRST                   0x00000001U            /*!< Core soft reset          */
-#define USB_OTG_GRSTCTL_HSRST                   0x00000002U            /*!< HCLK soft reset          */
-#define USB_OTG_GRSTCTL_FCRST                   0x00000004U            /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH                 0x00000010U            /*!< RxFIFO flush             */
-#define USB_OTG_GRSTCTL_TXFFLSH                 0x00000020U            /*!< TxFIFO flush             */
-#define USB_OTG_GRSTCTL_TXFNUM                  0x000007C0U            /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                0x00000040U            /*!<Bit 0 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                0x00000080U            /*!<Bit 1 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                0x00000100U            /*!<Bit 2 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                0x00000200U            /*!<Bit 3 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                0x00000400U            /*!<Bit 4 */
-#define USB_OTG_GRSTCTL_DMAREQ                  0x40000000U            /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL                  0x80000000U            /*!< AHB master idle */
-
-/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
-#define USB_OTG_DIEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask                 */
-#define USB_OTG_DIEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask                  */
-#define USB_OTG_DIEPMSK_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask          */
-#define USB_OTG_DIEPMSK_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask           */
-#define USB_OTG_DIEPMSK_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask                    */
-#define USB_OTG_DIEPMSK_TXFURM                  0x00000100U            /*!< FIFO underrun mask                                */
-#define USB_OTG_DIEPMSK_BIM                     0x00000200U            /*!< BNA interrupt mask                                */
-
-/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
-#define USB_OTG_HPTXSTS_PTXFSAVL                0x0000FFFFU            /*!< Periodic transmit data FIFO space available     */
-#define USB_OTG_HPTXSTS_PTXQSAV                 0x00FF0000U            /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0               0x00010000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1               0x00020000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2               0x00040000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3               0x00080000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4               0x00100000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5               0x00200000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6               0x00400000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7               0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_HPTXSTS_PTXQTOP                 0xFF000000U            /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0               0x01000000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1               0x02000000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2               0x04000000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3               0x08000000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4               0x10000000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5               0x20000000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6               0x40000000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7               0x80000000U            /*!<Bit 7 */
-
-/********************  Bit definition for USB_OTG_HAINT register  ********************/
-#define USB_OTG_HAINT_HAINT                     0x0000FFFFU            /*!< Channel interrupts */
-
-/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
-#define USB_OTG_DOEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask               */
-#define USB_OTG_DOEPMSK_STUPM                   0x00000008U            /*!< SETUP phase done mask                          */
-#define USB_OTG_DOEPMSK_OTEPDM                  0x00000010U            /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_OTEPSPRM                0x00000020U            /*!< Status Phase Received mask                     */
-#define USB_OTG_DOEPMSK_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received mask       */
-#define USB_OTG_DOEPMSK_OPEM                    0x00000100U            /*!< OUT packet error mask                          */
-#define USB_OTG_DOEPMSK_BOIM                    0x00000200U            /*!< BNA interrupt mask                             */
-
-/********************  Bit definition for USB_OTG_GINTSTS register  ********************/
-#define USB_OTG_GINTSTS_CMOD                    0x00000001U            /*!< Current mode of operation                      */
-#define USB_OTG_GINTSTS_MMIS                    0x00000002U            /*!< Mode mismatch interrupt                        */
-#define USB_OTG_GINTSTS_OTGINT                  0x00000004U            /*!< OTG interrupt                                  */
-#define USB_OTG_GINTSTS_SOF                     0x00000008U            /*!< Start of frame                                 */
-#define USB_OTG_GINTSTS_RXFLVL                  0x00000010U            /*!< RxFIFO nonempty                                */
-#define USB_OTG_GINTSTS_NPTXFE                  0x00000020U            /*!< Nonperiodic TxFIFO empty                       */
-#define USB_OTG_GINTSTS_GINAKEFF                0x00000040U            /*!< Global IN nonperiodic NAK effective            */
-#define USB_OTG_GINTSTS_BOUTNAKEFF              0x00000080U            /*!< Global OUT NAK effective                       */
-#define USB_OTG_GINTSTS_ESUSP                   0x00000400U            /*!< Early suspend                                  */
-#define USB_OTG_GINTSTS_USBSUSP                 0x00000800U            /*!< USB suspend                                    */
-#define USB_OTG_GINTSTS_USBRST                  0x00001000U            /*!< USB reset                                      */
-#define USB_OTG_GINTSTS_ENUMDNE                 0x00002000U            /*!< Enumeration done                               */
-#define USB_OTG_GINTSTS_ISOODRP                 0x00004000U            /*!< Isochronous OUT packet dropped interrupt       */
-#define USB_OTG_GINTSTS_EOPF                    0x00008000U            /*!< End of periodic frame interrupt                */
-#define USB_OTG_GINTSTS_IEPINT                  0x00040000U            /*!< IN endpoint interrupt                          */
-#define USB_OTG_GINTSTS_OEPINT                  0x00080000U            /*!< OUT endpoint interrupt                         */
-#define USB_OTG_GINTSTS_IISOIXFR                0x00100000U            /*!< Incomplete isochronous IN transfer             */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       0x00200000U            /*!< Incomplete periodic transfer                   */
-#define USB_OTG_GINTSTS_DATAFSUSP               0x00400000U            /*!< Data fetch suspended                           */
-#define USB_OTG_GINTSTS_RSTDET                  0x00800000U            /*!< Reset detected interrupt                       */
-#define USB_OTG_GINTSTS_HPRTINT                 0x01000000U            /*!< Host port interrupt                            */
-#define USB_OTG_GINTSTS_HCINT                   0x02000000U            /*!< Host channels interrupt                        */
-#define USB_OTG_GINTSTS_PTXFE                   0x04000000U            /*!< Periodic TxFIFO empty                          */
-#define USB_OTG_GINTSTS_LPMINT                  0x08000000U            /*!< LPM interrupt                                  */
-#define USB_OTG_GINTSTS_CIDSCHG                 0x10000000U            /*!< Connector ID status change                     */
-#define USB_OTG_GINTSTS_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt                  */
-#define USB_OTG_GINTSTS_SRQINT                  0x40000000U            /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT                  0x80000000U            /*!< Resume/remote wakeup detected interrupt        */
-
-/********************  Bit definition for USB_OTG_GINTMSK register  ********************/
-#define USB_OTG_GINTMSK_MMISM                   0x00000002U            /*!< Mode mismatch interrupt mask                        */
-#define USB_OTG_GINTMSK_OTGINT                  0x00000004U            /*!< OTG interrupt mask                                  */
-#define USB_OTG_GINTMSK_SOFM                    0x00000008U            /*!< Start of frame mask                                 */
-#define USB_OTG_GINTMSK_RXFLVLM                 0x00000010U            /*!< Receive FIFO nonempty mask                          */
-#define USB_OTG_GINTMSK_NPTXFEM                 0x00000020U            /*!< Nonperiodic TxFIFO empty mask                       */
-#define USB_OTG_GINTMSK_GINAKEFFM               0x00000040U            /*!< Global nonperiodic IN NAK effective mask            */
-#define USB_OTG_GINTMSK_GONAKEFFM               0x00000080U            /*!< Global OUT NAK effective mask                       */
-#define USB_OTG_GINTMSK_ESUSPM                  0x00000400U            /*!< Early suspend mask                                  */
-#define USB_OTG_GINTMSK_USBSUSPM                0x00000800U            /*!< USB suspend mask                                    */
-#define USB_OTG_GINTMSK_USBRST                  0x00001000U            /*!< USB reset mask                                      */
-#define USB_OTG_GINTMSK_ENUMDNEM                0x00002000U            /*!< Enumeration done mask                               */
-#define USB_OTG_GINTMSK_ISOODRPM                0x00004000U            /*!< Isochronous OUT packet dropped interrupt mask       */
-#define USB_OTG_GINTMSK_EOPFM                   0x00008000U            /*!< End of periodic frame interrupt mask                */
-#define USB_OTG_GINTMSK_EPMISM                  0x00020000U            /*!< Endpoint mismatch interrupt mask                    */
-#define USB_OTG_GINTMSK_IEPINT                  0x00040000U            /*!< IN endpoints interrupt mask                         */
-#define USB_OTG_GINTMSK_OEPINT                  0x00080000U            /*!< OUT endpoints interrupt mask                        */
-#define USB_OTG_GINTMSK_IISOIXFRM               0x00100000U            /*!< Incomplete isochronous IN transfer mask             */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         0x00200000U            /*!< Incomplete periodic transfer mask                   */
-#define USB_OTG_GINTMSK_FSUSPM                  0x00400000U            /*!< Data fetch suspended mask                           */
-#define USB_OTG_GINTMSK_RSTDEM                  0x00800000U            /*!< Reset detected interrupt mask                       */
-#define USB_OTG_GINTMSK_PRTIM                   0x01000000U            /*!< Host port interrupt mask                            */
-#define USB_OTG_GINTMSK_HCIM                    0x02000000U            /*!< Host channels interrupt mask                        */
-#define USB_OTG_GINTMSK_PTXFEM                  0x04000000U            /*!< Periodic TxFIFO empty mask                          */
-#define USB_OTG_GINTMSK_LPMINTM                 0x08000000U            /*!< LPM interrupt Mask                                  */
-#define USB_OTG_GINTMSK_CIDSCHGM                0x10000000U            /*!< Connector ID status change mask                     */
-#define USB_OTG_GINTMSK_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt mask                  */
-#define USB_OTG_GINTMSK_SRQIM                   0x40000000U            /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM                    0x80000000U            /*!< Resume/remote wakeup detected interrupt mask        */
-
-/********************  Bit definition for USB_OTG_DAINT register  ********************/
-#define USB_OTG_DAINT_IEPINT                  0x0000FFFFU            /*!< IN endpoint interrupt bits  */
-#define USB_OTG_DAINT_OEPINT                  0xFFFF0000U            /*!< OUT endpoint interrupt bits */
-
-/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
-#define USB_OTG_HAINTMSK_HAINTM                  0x0000FFFFU            /*!< Channel interrupt mask */
-
-/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
-#define USB_OTG_GRXSTSP_EPNUM                    0x0000000FU            /*!< IN EP interrupt mask bits  */
-#define USB_OTG_GRXSTSP_BCNT                     0x00007FF0U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID                     0x00018000U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS                   0x001E0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
-#define USB_OTG_DAINTMSK_IEPM                    0x0000FFFFU            /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM                    0xFFFF0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for OTG register  ********************/
-
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition for OTG register  ********************/
-
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
-#define USB_OTG_GRXFSIZ_RXFD            0x0000FFFFU            /*!< RxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
-#define USB_OTG_DVBUSDIS_VBUSDT         0x0000FFFFU            /*!< Device VBUS discharge time */
-
-/********************  Bit definition for OTG register  ********************/
-#define USB_OTG_NPTXFSA                 0x0000FFFFU            /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD                  0xFFFF0000U            /*!< Nonperiodic TxFIFO depth               */
-#define USB_OTG_TX0FSA                  0x0000FFFFU            /*!< Endpoint 0 transmit RAM start address  */
-#define USB_OTG_TX0FD                   0xFFFF0000U            /*!< Endpoint 0 TxFIFO depth                */
-
-/********************  Bit definition for USB_OTG_DVBUSPULSE register  ********************/
-#define USB_OTG_DVBUSPULSE_DVBUSP                0x00000FFFU            /*!< Device VBUS pulsing time */
-
-/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
-#define USB_OTG_GNPTXSTS_NPTXFSAV                0x0000FFFFU            /*!< Nonperiodic TxFIFO space available */
-
-#define USB_OTG_GNPTXSTS_NPTQXSAV                0x00FF0000U            /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0              0x00010000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1              0x00020000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2              0x00040000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3              0x00080000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4              0x00100000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5              0x00200000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6              0x00400000U            /*!<Bit 6 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7              0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_GNPTXSTS_NPTXQTOP                0x7F000000U            /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0              0x01000000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1              0x02000000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2              0x04000000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3              0x08000000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4              0x10000000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5              0x20000000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6              0x40000000U            /*!<Bit 6 */
-
-/********************  Bit definition for USB_OTG_DTHRCTL register  ********************/
-#define USB_OTG_DTHRCTL_NONISOTHREN             0x00000001U            /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN                0x00000002U            /*!< ISO IN endpoint threshold enable */
-
-#define USB_OTG_DTHRCTL_TXTHRLEN                0x000007FCU            /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0              0x00000004U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1              0x00000008U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2              0x00000010U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3              0x00000020U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4              0x00000040U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5              0x00000080U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6              0x00000100U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7              0x00000200U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8              0x00000400U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_RXTHREN                 0x00010000U            /*!< Receive threshold enable */
-
-#define USB_OTG_DTHRCTL_RXTHRLEN                0x03FE0000U            /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0              0x00020000U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1              0x00040000U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2              0x00080000U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3              0x00100000U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4              0x00200000U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5              0x00400000U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6              0x00800000U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7              0x01000000U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8              0x02000000U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_ARPEN                   0x08000000U            /*!< Arbiter parking enable */
-
-/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM            0x0000FFFFU         /*!< IN EP Tx FIFO empty interrupt mask bits */
-
-/********************  Bit definition for USB_OTG_DEACHINT register  ********************/
-#define USB_OTG_DEACHINT_IEP1INT                0x00000002U           /*!< IN endpoint 1interrupt bit   */
-#define USB_OTG_DEACHINT_OEP1INT                0x00020000U           /*!< OUT endpoint 1 interrupt bit */
-
-/********************  Bit definition for USB_OTG_GCCFG register  ********************/
-#define USB_OTG_GCCFG_PWRDWN                 0x00010000U              /*!< Power down */
-#define USB_OTG_GCCFG_VBDEN                  0x00200000U              /*!< USB VBUS Detection Enable */
-
-/********************  Bit definition for USB_OTG_GPWRDN) register  ********************/
-#define USB_OTG_GPWRDN_ADPMEN                 0x00000001U             /*!< ADP module enable */
-#define USB_OTG_GPWRDN_ADPIF                  0x00800000U             /*!< ADP Interrupt flag */
-
-/********************  Bit definition for USB_OTG_DEACHINTMSK register  ********************/
-#define USB_OTG_DEACHINTMSK_IEP1INTM          0x00000002U            /*!< IN Endpoint 1 interrupt mask bit  */
-#define USB_OTG_DEACHINTMSK_OEP1INTM          0x00020000U            /*!< OUT Endpoint 1 interrupt mask bit */
-
-/********************  Bit definition for USB_OTG_CID register  ********************/
-#define USB_OTG_CID_PRODUCT_ID               0xFFFFFFFFU            /*!< Product ID field */
-
-/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/
-#define  USB_OTG_GLPMCFG_LPMEN               0x00000001U            /*!< LPM support enable                                     */
-#define  USB_OTG_GLPMCFG_LPMACK              0x00000002U            /*!< LPM Token acknowledge enable                           */
-#define  USB_OTG_GLPMCFG_BESL                0x0000003CU            /*!< BESL value received with last ACKed LPM Token          */
-#define  USB_OTG_GLPMCFG_REMWAKE             0x00000040U            /*!< bRemoteWake value received with last ACKed LPM Token   */
-#define  USB_OTG_GLPMCFG_L1SSEN              0x00000080U            /*!< L1 shallow sleep enable                                */
-#define  USB_OTG_GLPMCFG_BESLTHRS            0x00000F00U            /*!< BESL threshold                                         */
-#define  USB_OTG_GLPMCFG_L1DSEN              0x00001000U            /*!< L1 deep sleep enable                                   */
-#define  USB_OTG_GLPMCFG_LPMRSP              0x00006000U            /*!< LPM response                                           */
-#define  USB_OTG_GLPMCFG_SLPSTS              0x00008000U            /*!< Port sleep status                                      */
-#define  USB_OTG_GLPMCFG_L1RSMOK             0x00010000U            /*!< Sleep State Resume OK                                  */
-#define  USB_OTG_GLPMCFG_LPMCHIDX            0x001E0000U            /*!< LPM Channel Index                                      */
-#define  USB_OTG_GLPMCFG_LPMRCNT             0x00E00000U            /*!< LPM retry count                                        */
-#define  USB_OTG_GLPMCFG_SNDLPM              0x01000000U            /*!< Send LPM transaction                                   */
-#define  USB_OTG_GLPMCFG_LPMRCNTSTS          0x0E000000U            /*!< LPM retry count status                                 */
-#define  USB_OTG_GLPMCFG_ENBESL              0x10000000U            /*!< Enable best effort service latency                     */
-
-/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
-#define USB_OTG_DIEPEACHMSK1_XFRCM           0x00000001U            /*!< Transfer completed interrupt mask                 */
-#define USB_OTG_DIEPEACHMSK1_EPDM            0x00000002U            /*!< Endpoint disabled interrupt mask                  */
-#define USB_OTG_DIEPEACHMSK1_TOM             0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK       0x00000010U            /*!< IN token received when TxFIFO empty mask          */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM         0x00000020U            /*!< IN token received with EP mismatch mask           */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM         0x00000040U            /*!< IN endpoint NAK effective mask                    */
-#define USB_OTG_DIEPEACHMSK1_TXFURM          0x00000100U            /*!< FIFO underrun mask                                */
-#define USB_OTG_DIEPEACHMSK1_BIM             0x00000200U            /*!< BNA interrupt mask                                */
-#define USB_OTG_DIEPEACHMSK1_NAKM            0x00002000U            /*!< NAK interrupt mask                                */
-
-/********************  Bit definition for USB_OTG_HPRT register  ********************/
-#define USB_OTG_HPRT_PCSTS                   0x00000001U            /*!< Port connect status        */
-#define USB_OTG_HPRT_PCDET                   0x00000002U            /*!< Port connect detected      */
-#define USB_OTG_HPRT_PENA                    0x00000004U            /*!< Port enable                */
-#define USB_OTG_HPRT_PENCHNG                 0x00000008U            /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA                    0x00000010U            /*!< Port overcurrent active    */
-#define USB_OTG_HPRT_POCCHNG                 0x00000020U            /*!< Port overcurrent change    */
-#define USB_OTG_HPRT_PRES                    0x00000040U            /*!< Port resume                */
-#define USB_OTG_HPRT_PSUSP                   0x00000080U            /*!< Port suspend               */
-#define USB_OTG_HPRT_PRST                    0x00000100U            /*!< Port reset                 */
-
-#define USB_OTG_HPRT_PLSTS                   0x00000C00U            /*!< Port line status           */
-#define USB_OTG_HPRT_PLSTS_0                 0x00000400U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PLSTS_1                 0x00000800U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PPWR                    0x00001000U            /*!< Port power                 */
-
-#define USB_OTG_HPRT_PTCTL                   0x0001E000U            /*!< Port test control          */
-#define USB_OTG_HPRT_PTCTL_0                 0x00002000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PTCTL_1                 0x00004000U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PTCTL_2                 0x00008000U            /*!<Bit 2 */
-#define USB_OTG_HPRT_PTCTL_3                 0x00010000U            /*!<Bit 3 */
-
-#define USB_OTG_HPRT_PSPD                    0x00060000U            /*!< Port speed                 */
-#define USB_OTG_HPRT_PSPD_0                  0x00020000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PSPD_1                  0x00040000U            /*!<Bit 1 */
-
-/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
-#define USB_OTG_DOEPEACHMSK1_XFRCM               0x00000001U            /*!< Transfer completed interrupt mask         */
-#define USB_OTG_DOEPEACHMSK1_EPDM                0x00000002U            /*!< Endpoint disabled interrupt mask          */
-#define USB_OTG_DOEPEACHMSK1_TOM                 0x00000008U            /*!< Timeout condition mask                    */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           0x00000010U            /*!< IN token received when TxFIFO empty mask  */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM             0x00000020U            /*!< IN token received with EP mismatch mask   */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM             0x00000040U            /*!< IN endpoint NAK effective mask            */
-#define USB_OTG_DOEPEACHMSK1_TXFURM              0x00000100U            /*!< OUT packet error mask                     */
-#define USB_OTG_DOEPEACHMSK1_BIM                 0x00000200U            /*!< BNA interrupt mask                        */
-#define USB_OTG_DOEPEACHMSK1_BERRM               0x00001000U            /*!< Bubble error interrupt mask               */
-#define USB_OTG_DOEPEACHMSK1_NAKM                0x00002000U            /*!< NAK interrupt mask                        */
-#define USB_OTG_DOEPEACHMSK1_NYETM               0x00004000U            /*!< NYET interrupt mask                       */
-
-/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
-#define USB_OTG_HPTXFSIZ_PTXSA                   0x0000FFFFU            /*!< Host periodic TxFIFO start address            */
-#define USB_OTG_HPTXFSIZ_PTXFD                   0xFFFF0000U            /*!< Host periodic TxFIFO depth                    */
-
-/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
-#define USB_OTG_DIEPCTL_MPSIZ                   0x000007FFU            /*!< Maximum packet size              */
-#define USB_OTG_DIEPCTL_USBAEP                  0x00008000U            /*!< USB active endpoint              */
-#define USB_OTG_DIEPCTL_EONUM_DPID              0x00010000U            /*!< Even/odd frame                   */
-#define USB_OTG_DIEPCTL_NAKSTS                  0x00020000U            /*!< NAK status                       */
-
-#define USB_OTG_DIEPCTL_EPTYP                   0x000C0000U            /*!< Endpoint type                    */
-#define USB_OTG_DIEPCTL_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_STALL                   0x00200000U            /*!< STALL handshake                  */
-
-#define USB_OTG_DIEPCTL_TXFNUM                  0x03C00000U            /*!< TxFIFO number                    */
-#define USB_OTG_DIEPCTL_TXFNUM_0                0x00400000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                0x00800000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                0x01000000U            /*!<Bit 2 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                0x02000000U            /*!<Bit 3 */
-#define USB_OTG_DIEPCTL_CNAK                    0x04000000U            /*!< Clear NAK                        */
-#define USB_OTG_DIEPCTL_SNAK                    0x08000000U            /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          0x10000000U            /*!< Set DATA0 PID                    */
-#define USB_OTG_DIEPCTL_SODDFRM                 0x20000000U            /*!< Set odd frame                    */
-#define USB_OTG_DIEPCTL_EPDIS                   0x40000000U            /*!< Endpoint disable                 */
-#define USB_OTG_DIEPCTL_EPENA                   0x80000000U            /*!< Endpoint enable                  */
-
-/********************  Bit definition for USB_OTG_HCCHAR register  ********************/
-#define USB_OTG_HCCHAR_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
-
-#define USB_OTG_HCCHAR_EPNUM                   0x00007800U            /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPNUM_1                 0x00001000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_EPNUM_2                 0x00002000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_EPNUM_3                 0x00004000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_EPDIR                   0x00008000U            /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV                   0x00020000U            /*!< Low-speed device */
-
-#define USB_OTG_HCCHAR_EPTYP                   0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_MC                      0x00300000U            /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                    0x00100000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_MC_1                    0x00200000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_DAD                     0x1FC00000U            /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                   0x00400000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_DAD_1                   0x00800000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_DAD_2                   0x01000000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_DAD_3                   0x02000000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_DAD_4                   0x04000000U            /*!<Bit 4 */
-#define USB_OTG_HCCHAR_DAD_5                   0x08000000U            /*!<Bit 5 */
-#define USB_OTG_HCCHAR_DAD_6                   0x10000000U            /*!<Bit 6 */
-#define USB_OTG_HCCHAR_ODDFRM                  0x20000000U            /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS                   0x40000000U            /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA                   0x80000000U            /*!< Channel enable */
-
-/********************  Bit definition for USB_OTG_HCSPLT register  ********************/
-
-#define USB_OTG_HCSPLT_PRTADDR                 0x0000007FU            /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_PRTADDR_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_PRTADDR_2               0x00000004U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_PRTADDR_3               0x00000008U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_PRTADDR_4               0x00000010U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_PRTADDR_5               0x00000020U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_PRTADDR_6               0x00000040U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_HUBADDR                 0x00003F80U            /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0               0x00000080U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_HUBADDR_1               0x00000100U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_HUBADDR_2               0x00000200U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_HUBADDR_3               0x00000400U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_HUBADDR_4               0x00000800U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_HUBADDR_5               0x00001000U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_HUBADDR_6               0x00002000U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_XACTPOS                 0x0000C000U            /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0               0x00004000U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_XACTPOS_1               0x00008000U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_COMPLSPLT               0x00010000U            /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN                 0x80000000U            /*!< Split enable */
-
-/********************  Bit definition for USB_OTG_HCINT register  ********************/
-#define USB_OTG_HCINT_XFRC                    0x00000001U            /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH                     0x00000002U            /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINT_STALL                   0x00000008U            /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK                     0x00000010U            /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK                     0x00000020U            /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET                    0x00000040U            /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR                   0x00000080U            /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR                   0x00000100U            /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR                   0x00000200U            /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR                   0x00000400U            /*!< Data toggle error */
-
-/********************  Bit definition for USB_OTG_DIEPINT register  ********************/
-#define USB_OTG_DIEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_TOC                     0x00000008U            /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE                  0x00000010U            /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNE                  0x00000040U            /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE                    0x00000080U            /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN              0x00000100U            /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA                     0x00000200U            /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS               0x00000800U            /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR                    0x00001000U            /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK                     0x00002000U            /*!< NAK interrupt */
-
-/********************  Bit definition for USB_OTG_HCINTMSK register  ********************/
-#define USB_OTG_HCINTMSK_XFRCM                   0x00000001U            /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM                    0x00000002U            /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM                  0x00000008U            /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM                    0x00000010U            /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM                    0x00000020U            /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET                    0x00000040U            /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM                  0x00000080U            /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM                  0x00000100U            /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM                  0x00000200U            /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM                  0x00000400U            /*!< Data toggle error mask */
-
-/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
-
-#define USB_OTG_DIEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT                  0x60000000U            /*!< Packet count */
-/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
-#define USB_OTG_HCTSIZ_XFRSIZ                    0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT                    0x1FF80000U            /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING                    0x80000000U            /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID                      0x60000000U            /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                    0x20000000U            /*!<Bit 0 */
-#define USB_OTG_HCTSIZ_DPID_1                    0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
-#define USB_OTG_DIEPDMA_DMAADDR                  0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition for USB_OTG_HCDMA register  ********************/
-#define USB_OTG_HCDMA_DMAADDR                    0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
-#define USB_OTG_DTXFSTS_INEPTFSAV                0x0000FFFFU            /*!< IN endpoint TxFIFO space available */
-
-/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
-#define USB_OTG_DIEPTXF_INEPTXSA                 0x0000FFFFU            /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD                 0xFFFF0000U            /*!< IN endpoint TxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
-#define USB_OTG_DOEPCTL_MPSIZ                     0x000007FFU            /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP                    0x00008000U            /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS                    0x00020000U            /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            0x10000000U            /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM                   0x20000000U            /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP                     0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                   0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DOEPCTL_EPTYP_1                   0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_SNPM                      0x00100000U            /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL                     0x00200000U            /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK                      0x04000000U            /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK                      0x08000000U            /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS                     0x40000000U            /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA                     0x80000000U            /*!< Endpoint enable */
-
-/********************  Bit definition for USB_OTG_DOEPINT register  ********************/
-#define USB_OTG_DOEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_STUP                    0x00000008U            /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS                 0x00000010U            /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_OTEPSPR                 0x00000020U            /*!< Status Phase Received For Control Write */
-#define USB_OTG_DOEPINT_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_NYET                    0x00004000U            /*!< NYET interrupt */
-
-/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
-#define USB_OTG_DOEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-
-#define USB_OTG_DOEPTSIZ_STUPCNT                 0x60000000U            /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0               0x20000000U            /*!<Bit 0 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1               0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition for PCGCCTL register  ********************/
-#define USB_OTG_PCGCCTL_STOPCLK                 0x00000001U            /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK                 0x00000002U            /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP                 0x00000010U            /*!<Bit 1 */
-
-
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || \
-                                       ((__INSTANCE__) == ADC2) || \
-                                       ((__INSTANCE__) == ADC3))
-
-/******************************* CAN Instances ********************************/
-#define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) || \
-                                           ((__INSTANCE__) == CAN2))
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)
-
-/******************************* DAC Instances ********************************/
-#define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC)
-
-/******************************* DCMI Instances *******************************/
-#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
-
-
-/******************************* DMA2D Instances *******************************/
-#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
-
-/******************************** DMA Instances *******************************/
-#define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) || \
-                                              ((__INSTANCE__) == DMA1_Stream1) || \
-                                              ((__INSTANCE__) == DMA1_Stream2) || \
-                                              ((__INSTANCE__) == DMA1_Stream3) || \
-                                              ((__INSTANCE__) == DMA1_Stream4) || \
-                                              ((__INSTANCE__) == DMA1_Stream5) || \
-                                              ((__INSTANCE__) == DMA1_Stream6) || \
-                                              ((__INSTANCE__) == DMA1_Stream7) || \
-                                              ((__INSTANCE__) == DMA2_Stream0) || \
-                                              ((__INSTANCE__) == DMA2_Stream1) || \
-                                              ((__INSTANCE__) == DMA2_Stream2) || \
-                                              ((__INSTANCE__) == DMA2_Stream3) || \
-                                              ((__INSTANCE__) == DMA2_Stream4) || \
-                                              ((__INSTANCE__) == DMA2_Stream5) || \
-                                              ((__INSTANCE__) == DMA2_Stream6) || \
-                                              ((__INSTANCE__) == DMA2_Stream7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
-                                            ((__INSTANCE__) == GPIOB) || \
-                                            ((__INSTANCE__) == GPIOC) || \
-                                            ((__INSTANCE__) == GPIOD) || \
-                                            ((__INSTANCE__) == GPIOE) || \
-                                            ((__INSTANCE__) == GPIOF) || \
-                                            ((__INSTANCE__) == GPIOG) || \
-                                            ((__INSTANCE__) == GPIOH) || \
-                                            ((__INSTANCE__) == GPIOI) || \
-                                            ((__INSTANCE__) == GPIOJ) || \
-                                            ((__INSTANCE__) == GPIOK))
-
-#define IS_GPIO_AF_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == GPIOA) || \
-                                             ((__INSTANCE__) == GPIOB) || \
-                                             ((__INSTANCE__) == GPIOC) || \
-                                             ((__INSTANCE__) == GPIOD) || \
-                                             ((__INSTANCE__) == GPIOE) || \
-                                             ((__INSTANCE__) == GPIOF) || \
-                                             ((__INSTANCE__) == GPIOG) || \
-                                             ((__INSTANCE__) == GPIOH) || \
-                                             ((__INSTANCE__) == GPIOI) || \
-                                             ((__INSTANCE__) == GPIOJ) || \
-                                             ((__INSTANCE__) == GPIOK))
-
-/****************************** CEC Instances *********************************/
-#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
-
-/****************************** QSPI Instances *********************************/
-#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
-
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
-                                           ((__INSTANCE__) == I2C2) || \
-                                           ((__INSTANCE__) == I2C3) || \
-                                           ((__INSTANCE__) == I2C4))
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == SPI1) || \
-                                            ((__INSTANCE__) == SPI2) || \
-                                            ((__INSTANCE__) == SPI3))
-
-/******************************* LPTIM Instances ********************************/
-#define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
-
-
-
-
-
-/******************************* RNG Instances ********************************/
-#define IS_RNG_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == RNG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == RTC)
-
-/******************************* SAI Instances ********************************/
-#define IS_SAI_ALL_INSTANCE(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) || \
-                                         ((__PERIPH__) == SAI1_Block_B) || \
-                                         ((__PERIPH__) == SAI2_Block_A) || \
-                                         ((__PERIPH__) == SAI2_Block_B))
-/* Legacy define */
-#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
-
-/******************************** SDMMC Instances *******************************/
-#define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SDMMC1)
-
-/****************************** SPDIFRX Instances *********************************/
-#define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
-                                           ((__INSTANCE__) == SPI2) || \
-                                           ((__INSTANCE__) == SPI3) || \
-                                           ((__INSTANCE__) == SPI4) || \
-                                           ((__INSTANCE__) == SPI5) || \
-                                           ((__INSTANCE__) == SPI6))
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1)   || \
-                                   ((__INSTANCE__) == TIM2)   || \
-                                   ((__INSTANCE__) == TIM3)   || \
-                                   ((__INSTANCE__) == TIM4)   || \
-                                   ((__INSTANCE__) == TIM5)   || \
-                                   ((__INSTANCE__) == TIM6)   || \
-                                   ((__INSTANCE__) == TIM7)   || \
-                                   ((__INSTANCE__) == TIM8)   || \
-                                   ((__INSTANCE__) == TIM9)   || \
-                                   ((__INSTANCE__) == TIM10)  || \
-                                   ((__INSTANCE__) == TIM11)  || \
-                                   ((__INSTANCE__) == TIM12)  || \
-                                   ((__INSTANCE__) == TIM13)  || \
-                                   ((__INSTANCE__) == TIM14))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1)  || \
-                                         ((__INSTANCE__) == TIM2)  || \
-                                         ((__INSTANCE__) == TIM3)  || \
-                                         ((__INSTANCE__) == TIM4)  || \
-                                         ((__INSTANCE__) == TIM5)  || \
-                                         ((__INSTANCE__) == TIM8)  || \
-                                         ((__INSTANCE__) == TIM9)  || \
-                                         ((__INSTANCE__) == TIM10) || \
-                                         ((__INSTANCE__) == TIM11) || \
-                                         ((__INSTANCE__) == TIM12) || \
-                                         ((__INSTANCE__) == TIM13) || \
-                                         ((__INSTANCE__) == TIM14))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1)  || \
-                                         ((__INSTANCE__) == TIM2)  || \
-                                         ((__INSTANCE__) == TIM3)  || \
-                                         ((__INSTANCE__) == TIM4)  || \
-                                         ((__INSTANCE__) == TIM5)  || \
-                                         ((__INSTANCE__) == TIM8)  || \
-                                         ((__INSTANCE__) == TIM9)  || \
-                                         ((__INSTANCE__) == TIM12))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1) || \
-                                         ((__INSTANCE__) == TIM2) || \
-                                         ((__INSTANCE__) == TIM3) || \
-                                         ((__INSTANCE__) == TIM4) || \
-                                         ((__INSTANCE__) == TIM5) || \
-                                         ((__INSTANCE__) == TIM8))
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
-                                       ((__INSTANCE__) == TIM2) || \
-                                       ((__INSTANCE__) == TIM3) || \
-                                       ((__INSTANCE__) == TIM4) || \
-                                       ((__INSTANCE__) == TIM5) || \
-                                       ((__INSTANCE__) == TIM8))
-
-/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
-#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \
-                                       (((__INSTANCE__) == TIM1)    || \
-                                        ((__INSTANCE__) == TIM8))
-
-/****************** TIM Instances : supporting OCxREF clear *******************/
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\
-                                  (((__INSTANCE__) == TIM1)    || \
-                                   ((__INSTANCE__) == TIM2)    || \
-                                   ((__INSTANCE__) == TIM3)    || \
-                                   ((__INSTANCE__) == TIM4)    || \
-                                   ((__INSTANCE__) == TIM8))
-
-/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\
-                                                 (((__INSTANCE__) == TIM1)    || \
-                                                  ((__INSTANCE__) == TIM2)    || \
-                                                  ((__INSTANCE__) == TIM3)    || \
-                                                  ((__INSTANCE__) == TIM4)    || \
-                                                  ((__INSTANCE__) == TIM5)    || \
-                                                  ((__INSTANCE__) == TIM8))
-
-/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\
-                                                   (((__INSTANCE__) == TIM1)    || \
-                                                    ((__INSTANCE__) == TIM2)    || \
-                                                    ((__INSTANCE__) == TIM3)    || \
-                                                    ((__INSTANCE__) == TIM4)    || \
-                                                    ((__INSTANCE__) == TIM5)    || \
-                                                    ((__INSTANCE__) == TIM8))
-/****************** TIM Instances : at least 5 capture/compare channels *******/
-#define IS_TIM_CC5_INSTANCE(__INSTANCE__)\
-  (((__INSTANCE__) == TIM1)    || \
-   ((__INSTANCE__) == TIM8) )
-
-/****************** TIM Instances : at least 6 capture/compare channels *******/
-#define IS_TIM_CC6_INSTANCE(__INSTANCE__)\
-  (((__INSTANCE__) == TIM1)    || \
-   ((__INSTANCE__) == TIM8))
-
-
-/******************** TIM Instances : Advanced-control timers *****************/
-#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
-                                            ((__INSTANCE__) == TIM8))
-
-/****************** TIM Instances : supporting 2 break inputs *****************/
-#define IS_TIM_BREAK_INSTANCE(__INSTANCE__)\
-  (((__INSTANCE__) == TIM1)    || \
-   ((__INSTANCE__) == TIM8))
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1) || \
-                                         ((__INSTANCE__) == TIM2) || \
-                                         ((__INSTANCE__) == TIM3) || \
-                                         ((__INSTANCE__) == TIM4) || \
-                                         ((__INSTANCE__) == TIM5) || \
-                                         ((__INSTANCE__) == TIM8))
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
-                                       ((__INSTANCE__) == TIM2) || \
-                                       ((__INSTANCE__) == TIM3) || \
-                                       ((__INSTANCE__) == TIM4) || \
-                                       ((__INSTANCE__) == TIM5) || \
-                                       ((__INSTANCE__) == TIM6) || \
-                                       ((__INSTANCE__) == TIM7) || \
-                                       ((__INSTANCE__) == TIM8))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
-                                          ((__INSTANCE__) == TIM2) || \
-                                          ((__INSTANCE__) == TIM3) || \
-                                          ((__INSTANCE__) == TIM4) || \
-                                          ((__INSTANCE__) == TIM5) || \
-                                          ((__INSTANCE__) == TIM8))
-
-/************ TIM Instances : DMA requests generation (COMDE) *****************/
-#define IS_TIM_CCDMA_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1) || \
-                                          ((__INSTANCE__) == TIM2) || \
-                                          ((__INSTANCE__) == TIM3) || \
-                                          ((__INSTANCE__) == TIM4) || \
-                                          ((__INSTANCE__) == TIM5) || \
-                                          ((__INSTANCE__) == TIM8))
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1) || \
-                                             ((__INSTANCE__) == TIM2) || \
-                                             ((__INSTANCE__) == TIM3) || \
-                                             ((__INSTANCE__) == TIM4) || \
-                                             ((__INSTANCE__) == TIM5) || \
-                                             ((__INSTANCE__) == TIM8))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
-                                          ((__INSTANCE__) == TIM2) || \
-                                          ((__INSTANCE__) == TIM3) || \
-                                          ((__INSTANCE__) == TIM4) || \
-                                          ((__INSTANCE__) == TIM5) || \
-                                          ((__INSTANCE__) == TIM6) || \
-                                          ((__INSTANCE__) == TIM7) || \
-                                          ((__INSTANCE__) == TIM8) || \
-                                          ((__INSTANCE__) == TIM13) || \
-                                          ((__INSTANCE__) == TIM14))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
-                                         ((__INSTANCE__) == TIM2) || \
-                                         ((__INSTANCE__) == TIM3) || \
-                                         ((__INSTANCE__) == TIM4) || \
-                                         ((__INSTANCE__) == TIM5) || \
-                                         ((__INSTANCE__) == TIM8) || \
-                                         ((__INSTANCE__) == TIM9) || \
-                                         ((__INSTANCE__) == TIM12))
-
-/********************** TIM Instances : 32 bit Counter ************************/
-#define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__)(((__INSTANCE__) == TIM2) || \
-                                              ((__INSTANCE__) == TIM5))
-
-/***************** TIM Instances : external trigger input available ************/
-#define IS_TIM_ETR_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1) || \
-                                        ((__INSTANCE__) == TIM2) || \
-                                        ((__INSTANCE__) == TIM3) || \
-                                        ((__INSTANCE__) == TIM4) || \
-                                        ((__INSTANCE__) == TIM5) || \
-                                        ((__INSTANCE__) == TIM8))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2)  || \
-                                         ((__INSTANCE__) == TIM5)  || \
-                                         ((__INSTANCE__) == TIM11))
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \
-    ((((__INSTANCE__) == TIM1) &&                  \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM2) &&                   \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM3) &&                   \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM4) &&                   \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM5) &&                   \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM8) &&                   \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM9) &&                   \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM10) &&                  \
-     (((__CHANNEL__) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM11) &&                  \
-     (((__CHANNEL__) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM12) &&                  \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM13) &&                  \
-     (((__CHANNEL__) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM14) &&                  \
-     (((__CHANNEL__) == TIM_CHANNEL_1))))
-
-/************ TIM Instances : complementary output(s) available ***************/
-#define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \
-   ((((__INSTANCE__) == TIM1) &&                    \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||           \
-      ((__CHANNEL__) == TIM_CHANNEL_2) ||           \
-      ((__CHANNEL__) == TIM_CHANNEL_3)))            \
-    ||                                          \
-    (((__INSTANCE__) == TIM8) &&                    \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||           \
-      ((__CHANNEL__) == TIM_CHANNEL_2) ||           \
-      ((__CHANNEL__) == TIM_CHANNEL_3))))
-
-/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
-#define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\
-  (((__INSTANCE__) == TIM1)    || \
-   ((__INSTANCE__) == TIM8) )
-
-/****************** TIM Instances : supporting synchronization ****************/
-#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
-    (((__INSTANCE__) == TIM1)    || \
-     ((__INSTANCE__) == TIM2)    || \
-     ((__INSTANCE__) == TIM3)    || \
-     ((__INSTANCE__) == TIM4)    || \
-     ((__INSTANCE__) == TIM5)    || \
-     ((__INSTANCE__) == TIM6)    || \
-     ((__INSTANCE__) == TIM7)    || \
-     ((__INSTANCE__) == TIM8))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
-                                     ((__INSTANCE__) == USART2) || \
-                                     ((__INSTANCE__) == USART3) || \
-                                     ((__INSTANCE__) == USART6))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
-                                    ((__INSTANCE__) == USART2) || \
-                                    ((__INSTANCE__) == USART3) || \
-                                    ((__INSTANCE__) == UART4)  || \
-                                    ((__INSTANCE__) == UART5)  || \
-                                    ((__INSTANCE__) == USART6) || \
-                                    ((__INSTANCE__) == UART7)  || \
-                                    ((__INSTANCE__) == UART8))
-
-/****************** UART Instances : Driver Enable *****************/
-#define IS_UART_DRIVER_ENABLE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
-                                    ((__INSTANCE__) == USART2) || \
-                                    ((__INSTANCE__) == USART3) || \
-                                    ((__INSTANCE__) == UART4)  || \
-                                    ((__INSTANCE__) == UART5)  || \
-                                    ((__INSTANCE__) == USART6) || \
-                                    ((__INSTANCE__) == UART7)  || \
-                                    ((__INSTANCE__) == UART8))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
-                                    ((__INSTANCE__) == USART2) || \
-                                    ((__INSTANCE__) == USART3) || \
-                                    ((__INSTANCE__) == UART4)  || \
-                                    ((__INSTANCE__) == UART5)  || \
-                                    ((__INSTANCE__) == USART6) || \
-                                    ((__INSTANCE__) == UART7)  || \
-                                    ((__INSTANCE__) == UART8))
-
-/********************* UART Instances : Smart card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
-                                         ((__INSTANCE__) == USART2) || \
-                                         ((__INSTANCE__) == USART3) || \
-                                         ((__INSTANCE__) == USART6))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
-                                    ((__INSTANCE__) == USART2) || \
-                                    ((__INSTANCE__) == USART3) || \
-                                    ((__INSTANCE__) == UART4)  || \
-                                    ((__INSTANCE__) == UART5)  || \
-                                    ((__INSTANCE__) == USART6) || \
-                                    ((__INSTANCE__) == UART7)  || \
-                                    ((__INSTANCE__) == UART8))
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == WWDG)
-
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32F7xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */
-/*  product lines within the same STM32F7 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-#define HASH_RNG_IRQn              RNG_IRQn
-
-/* Aliases for __IRQHandler */
-#define HASH_RNG_IRQHandler        RNG_IRQHandler
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32F745xx_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/cmsis/stm32f746xx.h b/stmhal/cmsis/stm32f746xx.h
deleted file mode 100644
index d13e4b6225..0000000000
--- a/stmhal/cmsis/stm32f746xx.h
+++ /dev/null
@@ -1,9473 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f746xx.h
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   CMSIS Cortex-M7 Device Peripheral Access Layer Header File.
-  *
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral's registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS_Device
-  * @{
-  */
-
-/** @addtogroup stm32f746xx
-  * @{
-  */
-
-#ifndef __STM32F746xx_H
-#define __STM32F746xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-
-/**
- * @brief STM32F7xx Interrupt Number Definition, according to the selected device
- *        in @ref Library_configuration_section
- */
-typedef enum
-{
-/******  Cortex-M7 Processor Exceptions Numbers ****************************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M7 Memory Management Interrupt                           */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M7 Bus Fault Interrupt                                   */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M7 Usage Fault Interrupt                                 */
-  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M7 SV Call Interrupt                                    */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M7 Debug Monitor Interrupt                              */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M7 Pend SV Interrupt                                    */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M7 System Tick Interrupt                                */
-/******  STM32 specific Interrupt Numbers **********************************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
-  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
-  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
-  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
-  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
-  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
-  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
-  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
-  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
-  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
-  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
-  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
-  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
-  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
-  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
-  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
-  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
-  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */
-  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
-  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
-  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
-  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
-  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
-  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
-  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
-  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
-  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
-  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
-  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
-  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
-  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
-  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
-  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
-  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
-  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
-  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
-  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
-  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
-  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
-  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
-  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
-  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
-  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
-  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
-  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
-  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
-  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
-  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
-  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
-  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
-  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
-  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
-  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
-  RNG_IRQn                    = 80,     /*!< RNG global interrupt                                              */
-  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
-  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */
-  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */
-  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
-  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */
-  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */
-  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
-  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                             */
-  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                       */
-  DMA2D_IRQn                  = 90,     /*!< DMA2D global Interrupt                                            */
-  SAI2_IRQn                   = 91,     /*!< SAI2 global Interrupt                                             */
-  QUADSPI_IRQn                = 92,     /*!< Quad SPI global interrupt                                         */
-  LPTIM1_IRQn                 = 93,     /*!< LP TIM1 interrupt                                                 */
-  CEC_IRQn                    = 94,     /*!< HDMI-CEC global Interrupt                                         */
-  I2C4_EV_IRQn                = 95,     /*!< I2C4 Event Interrupt                                              */
-  I2C4_ER_IRQn                = 96,     /*!< I2C4 Error Interrupt                                              */
-  SPDIF_RX_IRQn               = 97,     /*!< SPDIF-RX global Interrupt                                         */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-/**
- * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
- */
-#define __CM7_REV                 0x0001U  /*!< Cortex-M7 revision r0p1                       */
-#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */
-#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */
-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1       /*!< FPU present                                   */
-#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */
-#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */
-#include "core_cm7.h"                     /*!< Cortex-M7 processor and core peripherals      */
-
-
-#include "system_stm32f7xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */
-
-/**
-  * @brief Analog to Digital Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */
-  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
-  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
-  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
-  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
-  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
-  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
-  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
-  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
-  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
-  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
-  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
-  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
-  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
-  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
-  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
-                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
-} ADC_Common_TypeDef;
-
-
-/**
-  * @brief Controller Area Network TxMailBox
-  */
-
-typedef struct
-{
-  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
-  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
-  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
-  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
-} CAN_TxMailBox_TypeDef;
-
-/**
-  * @brief Controller Area Network FIFOMailBox
-  */
-
-typedef struct
-{
-  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
-  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
-  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
-  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
-} CAN_FIFOMailBox_TypeDef;
-
-/**
-  * @brief Controller Area Network FilterRegister
-  */
-
-typedef struct
-{
-  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
-  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
-} CAN_FilterRegister_TypeDef;
-
-/**
-  * @brief Controller Area Network
-  */
-
-typedef struct
-{
-  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
-  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
-  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
-  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
-  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
-  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
-  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
-  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
-  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
-  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
-  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
-  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
-  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
-  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
-  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
-  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
-  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
-  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
-  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
-  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
-  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */
-  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
-} CAN_TypeDef;
-
-/**
-  * @brief HDMI-CEC
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< CEC control register,                                       Address offset:0x00 */
-  __IO uint32_t CFGR;         /*!< CEC configuration register,                                 Address offset:0x04 */
-  __IO uint32_t TXDR;         /*!< CEC Tx data register ,                                      Address offset:0x08 */
-  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,                                       Address offset:0x0C */
-  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register,                          Address offset:0x10 */
-  __IO uint32_t IER;          /*!< CEC interrupt enable register,                              Address offset:0x14 */
-}CEC_TypeDef;
-
-/**
-  * @brief CRC calculation unit
-  */
-
-typedef struct
-{
-  __IO uint32_t  DR;          /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint8_t   IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
-  uint8_t        RESERVED0;   /*!< Reserved, 0x05                                                    */
-  uint16_t       RESERVED1;   /*!< Reserved, 0x06                                                    */
-  __IO uint32_t  CR;          /*!< CRC Control register,                        Address offset: 0x08 */
-  uint32_t       RESERVED2;   /*!< Reserved,                                                    0x0C */
-  __IO uint32_t  INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
-  __IO uint32_t  POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
-} CRC_TypeDef;
-
-/**
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
-  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
-  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
-  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
-  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
-  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
-  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
-  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
-  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
-  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
-  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
-  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
-  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
-} DAC_TypeDef;
-
-
-/**
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
-  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
-  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
-  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/**
-  * @brief DCMI
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
-  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
-  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
-  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
-  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
-  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
-  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
-  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
-  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
-  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
-  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
-} DCMI_TypeDef;
-
-/**
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
-  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
-  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
-  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
-  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
-  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
-} DMA_Stream_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
-  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
-  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
-  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
-} DMA_TypeDef;
-
-/**
-  * @brief DMA2D Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
-  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
-  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
-  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
-  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
-  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
-  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
-  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
-  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
-  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
-  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
-  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
-  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
-  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
-  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
-  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
-  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
-  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
-  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
-  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
-  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
-  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */
-  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */
-} DMA2D_TypeDef;
-
-
-/**
-  * @brief Ethernet MAC
-  */
-
-typedef struct
-{
-  __IO uint32_t MACCR;
-  __IO uint32_t MACFFR;
-  __IO uint32_t MACHTHR;
-  __IO uint32_t MACHTLR;
-  __IO uint32_t MACMIIAR;
-  __IO uint32_t MACMIIDR;
-  __IO uint32_t MACFCR;
-  __IO uint32_t MACVLANTR;             /*    8 */
-  uint32_t      RESERVED0[2];
-  __IO uint32_t MACRWUFFR;             /*   11 */
-  __IO uint32_t MACPMTCSR;
-  uint32_t      RESERVED1[2];
-  __IO uint32_t MACSR;                 /*   15 */
-  __IO uint32_t MACIMR;
-  __IO uint32_t MACA0HR;
-  __IO uint32_t MACA0LR;
-  __IO uint32_t MACA1HR;
-  __IO uint32_t MACA1LR;
-  __IO uint32_t MACA2HR;
-  __IO uint32_t MACA2LR;
-  __IO uint32_t MACA3HR;
-  __IO uint32_t MACA3LR;               /*   24 */
-  uint32_t      RESERVED2[40];
-  __IO uint32_t MMCCR;                 /*   65 */
-  __IO uint32_t MMCRIR;
-  __IO uint32_t MMCTIR;
-  __IO uint32_t MMCRIMR;
-  __IO uint32_t MMCTIMR;               /*   69 */
-  uint32_t      RESERVED3[14];
-  __IO uint32_t MMCTGFSCCR;            /*   84 */
-  __IO uint32_t MMCTGFMSCCR;
-  uint32_t      RESERVED4[5];
-  __IO uint32_t MMCTGFCR;
-  uint32_t      RESERVED5[10];
-  __IO uint32_t MMCRFCECR;
-  __IO uint32_t MMCRFAECR;
-  uint32_t      RESERVED6[10];
-  __IO uint32_t MMCRGUFCR;
-  uint32_t      RESERVED7[334];
-  __IO uint32_t PTPTSCR;
-  __IO uint32_t PTPSSIR;
-  __IO uint32_t PTPTSHR;
-  __IO uint32_t PTPTSLR;
-  __IO uint32_t PTPTSHUR;
-  __IO uint32_t PTPTSLUR;
-  __IO uint32_t PTPTSAR;
-  __IO uint32_t PTPTTHR;
-  __IO uint32_t PTPTTLR;
-  __IO uint32_t RESERVED8;
-  __IO uint32_t PTPTSSR;
-  uint32_t      RESERVED9[565];
-  __IO uint32_t DMABMR;
-  __IO uint32_t DMATPDR;
-  __IO uint32_t DMARPDR;
-  __IO uint32_t DMARDLAR;
-  __IO uint32_t DMATDLAR;
-  __IO uint32_t DMASR;
-  __IO uint32_t DMAOMR;
-  __IO uint32_t DMAIER;
-  __IO uint32_t DMAMFBOCR;
-  __IO uint32_t DMARSWTR;
-  uint32_t      RESERVED10[8];
-  __IO uint32_t DMACHTDR;
-  __IO uint32_t DMACHRDR;
-  __IO uint32_t DMACHTBAR;
-  __IO uint32_t DMACHRBAR;
-} ETH_TypeDef;
-
-/**
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
-  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
-  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
-  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
-  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
-  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/**
-  * @brief FLASH Registers
-  */
-
-typedef struct
-{
-  __IO uint32_t ACR;      /*!< FLASH access control register,     Address offset: 0x00 */
-  __IO uint32_t KEYR;     /*!< FLASH key register,                Address offset: 0x04 */
-  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,         Address offset: 0x08 */
-  __IO uint32_t SR;       /*!< FLASH status register,             Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< FLASH control register,            Address offset: 0x10 */
-  __IO uint32_t OPTCR;    /*!< FLASH option control register ,    Address offset: 0x14 */
-  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1 ,  Address offset: 0x18 */
-} FLASH_TypeDef;
-
-
-
-/**
-  * @brief Flexible Memory Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
-} FMC_Bank1_TypeDef;
-
-/**
-  * @brief Flexible Memory Controller Bank1E
-  */
-
-typedef struct
-{
-  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
-} FMC_Bank1E_TypeDef;
-
-/**
-  * @brief Flexible Memory Controller Bank3
-  */
-
-typedef struct
-{
-  __IO uint32_t PCR;        /*!< NAND Flash control register,                       Address offset: 0x80 */
-  __IO uint32_t SR;         /*!< NAND Flash FIFO status and interrupt register,     Address offset: 0x84 */
-  __IO uint32_t PMEM;       /*!< NAND Flash Common memory space timing register,    Address offset: 0x88 */
-  __IO uint32_t PATT;       /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
-  uint32_t      RESERVED0;  /*!< Reserved, 0x90                                                          */
-  __IO uint32_t ECCR;       /*!< NAND Flash ECC result registers,                   Address offset: 0x94 */
-} FMC_Bank3_TypeDef;
-
-/**
-  * @brief Flexible Memory Controller Bank5_6
-  */
-
-typedef struct
-{
-  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */
-  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */
-  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */
-  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */
-  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */
-} FMC_Bank5_6_TypeDef;
-
-
-/**
-  * @brief General Purpose I/O
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
-  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
-  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
-  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
-  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
-  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
-  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
-  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/**
-  * @brief System configuration controller
-  */
-
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */
-  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
-} SYSCFG_TypeDef;
-
-/**
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
-  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
-} I2C_TypeDef;
-
-/**
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
-} IWDG_TypeDef;
-
-
-/**
-  * @brief LCD-TFT Display Controller
-  */
-
-typedef struct
-{
-  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04 */
-  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */
-  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */
-  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */
-  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */
-  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */
-  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20 */
-  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */
-  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28 */
-  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */
-  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30 */
-  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */
-  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */
-  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */
-  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
-  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */
-  __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                 Address offset: 0x48 */
-} LTDC_TypeDef;
-
-/**
-  * @brief LCD-TFT Display layer x Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */
-  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
-  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */
-  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */
-  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */
-  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */
-  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */
-  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */
-  uint32_t      RESERVED0[2];  /*!< Reserved */
-  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */
-  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */
-  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */
-  uint32_t      RESERVED1[3];  /*!< Reserved */
-  __IO uint32_t CLUTWR;        /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */
-
-} LTDC_Layer_TypeDef;
-
-/**
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;   /*!< PWR power control register 1,        Address offset: 0x00 */
-  __IO uint32_t CSR1;  /*!< PWR power control/status register 2, Address offset: 0x04 */
-  __IO uint32_t CR2;   /*!< PWR power control register 2,        Address offset: 0x08 */
-  __IO uint32_t CSR2;  /*!< PWR power control/status register 2, Address offset: 0x0C */
-} PWR_TypeDef;
-
-
-/**
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
-  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
-  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
-  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
-  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
-  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
-  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
-  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
-  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
-  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
-  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
-  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
-  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
-  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
-  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
-  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
-  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
-  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
-  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
-  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
-  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
-  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
-  __IO uint32_t PLLSAICFGR;    /*!< RCC PLLSAI configuration register,                           Address offset: 0x88 */
-  __IO uint32_t DCKCFGR1;      /*!< RCC Dedicated Clocks configuration register1,                 Address offset: 0x8C */
-  __IO uint32_t DCKCFGR2;      /*!< RCC Dedicated Clocks configuration register 2,               Address offset: 0x90 */
-
-} RCC_TypeDef;
-
-/**
-  * @brief Real-Time Clock
-  */
-
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-       uint32_t reserved;   /*!< Reserved  */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
-  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset: 0x4C */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
-  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
-  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
-  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
-  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
-  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
-  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
-  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
-  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
-  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
-  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
-  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
-  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
-  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
-  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
-  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */
-  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */
-  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */
-  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */
-  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */
-  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */
-  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */
-  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */
-  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */
-  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */
-  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */
-  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */
-} RTC_TypeDef;
-
-
-/**
-  * @brief Serial Audio Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t GCR;      /*!< SAI global configuration register,        Address offset: 0x00 */
-} SAI_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */
-  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */
-  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */
-  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */
-  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
-  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */
-  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */
-  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */
-} SAI_Block_TypeDef;
-
-/**
-  * @brief SPDIF-RX Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t   CR;           /*!< Control register,                   Address offset: 0x00 */
-  __IO uint32_t   IMR;          /*!< Interrupt mask register,            Address offset: 0x04 */
-  __IO uint32_t   SR;           /*!< Status register,                    Address offset: 0x08 */
-  __IO uint32_t   IFCR;         /*!< Interrupt Flag Clear register,      Address offset: 0x0C */
-  __IO uint32_t   DR;           /*!< Data input register,                Address offset: 0x10 */
-  __IO uint32_t   CSR;          /*!< Channel Status register,            Address offset: 0x14 */
-  __IO uint32_t   DIR;          /*!< Debug Information register,         Address offset: 0x18 */
-} SPDIFRX_TypeDef;
-
-/**
-  * @brief SD host Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t POWER;          /*!< SDMMC power control register,    Address offset: 0x00 */
-  __IO uint32_t CLKCR;          /*!< SDMMClock control register,     Address offset: 0x04 */
-  __IO uint32_t ARG;            /*!< SDMMC argument register,         Address offset: 0x08 */
-  __IO uint32_t CMD;            /*!< SDMMC command register,          Address offset: 0x0C */
-  __I uint32_t  RESPCMD;        /*!< SDMMC command response register, Address offset: 0x10 */
-  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,       Address offset: 0x14 */
-  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,       Address offset: 0x18 */
-  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,       Address offset: 0x1C */
-  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,       Address offset: 0x20 */
-  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,       Address offset: 0x24 */
-  __IO uint32_t DLEN;           /*!< SDMMC data length register,      Address offset: 0x28 */
-  __IO uint32_t DCTRL;          /*!< SDMMC data control register,     Address offset: 0x2C */
-  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,     Address offset: 0x30 */
-  __I uint32_t  STA;            /*!< SDMMC status register,           Address offset: 0x34 */
-  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,  Address offset: 0x38 */
-  __IO uint32_t MASK;           /*!< SDMMC mask register,             Address offset: 0x3C */
-  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
-  __I uint32_t  FIFOCNT;        /*!< SDMMC FIFO counter register,     Address offset: 0x48 */
-  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
-  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,        Address offset: 0x80 */
-} SDMMC_TypeDef;
-
-/**
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/**
-  * @brief QUAD Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */
-  __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
-  __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */
-  __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
-  __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
-  __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
-  __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */
-  __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
-  __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */
-  __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
-  __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */
-  __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
-  __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */
-} QUADSPI_TypeDef;
-
-/**
-  * @brief TIM
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
-  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
-  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
-  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
-  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */
-  __IO uint32_t CCR5;        /*!< TIM capture/compare mode register5,       Address offset: 0x58 */
-  __IO uint32_t CCR6;        /*!< TIM capture/compare mode register6,       Address offset: 0x5C */
-
-} TIM_TypeDef;
-
-/**
-  * @brief LPTIMIMER
-  */
-typedef struct
-{
-  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */
-  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */
-  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */
-  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                       Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< LPTIM Control register,                             Address offset: 0x10 */
-  __IO uint32_t CMP;      /*!< LPTIM Compare register,                             Address offset: 0x14 */
-  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
-  __IO uint32_t CNT;      /*!< LPTIM Counter register,                             Address offset: 0x1C */
-} LPTIM_TypeDef;
-
-
-/**
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */
-  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */
-  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
-  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */
-  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
-  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */
-  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
-  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
-  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
-  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
-  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
-} USART_TypeDef;
-
-
-/**
-  * @brief Window WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-
-/**
-  * @brief RNG
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
-  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
-  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
-} RNG_TypeDef;
-
-/**
-  * @}
-  */
-
-/**
-  * @brief USB_OTG_Core_Registers
-  */
-typedef struct
-{
- __IO uint32_t GOTGCTL;               /*!< USB_OTG Control and Status Register          000h */
-  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */
-  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */
-  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */
-  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */
-  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */
-  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */
-  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */
-  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */
-  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */
-  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */
-  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */
-  uint32_t Reserved30[2];             /*!< Reserved                                     030h */
-  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */
-  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */
-  uint32_t  Reserved5[3];             /*!< Reserved                                040h-048h */
-  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */
-  uint32_t  Reserved6;                /*!< Reserved                                     050h */
-  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */
-  __IO uint32_t GPWRDN;               /*!< Power Down Register                          058h */
-  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */
-   __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register       60Ch */
-    uint32_t  Reserved43[39];         /*!< Reserved                                058h-0FFh */
-  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */
-  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */
-} USB_OTG_GlobalTypeDef;
-
-
-/**
-  * @brief USB_OTG_device_Registers
-  */
-typedef struct
-{
-  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */
-  __IO uint32_t DCTL;            /*!< dev Control Register         804h */
-  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */
-  uint32_t Reserved0C;           /*!< Reserved                     80Ch */
-  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */
-  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */
-  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */
-  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */
-  uint32_t  Reserved20;          /*!< Reserved                     820h */
-  uint32_t Reserved9;            /*!< Reserved                     824h */
-  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */
-  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */
-  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */
-  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */
-  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */
-  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */
-  uint32_t Reserved40;           /*!< dedicated EP mask            840h */
-  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */
-  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */
-  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */
-} USB_OTG_DeviceTypeDef;
-
-
-/**
-  * @brief USB_OTG_IN_Endpoint-Specific_Register
-  */
-typedef struct
-{
-  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */
-  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */
-  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */
-  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */
-  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */
-  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */
-  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
-  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
-} USB_OTG_INEndpointTypeDef;
-
-
-/**
-  * @brief USB_OTG_OUT_Endpoint-Specific_Registers
-  */
-typedef struct
-{
-  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */
-  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */
-  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */
-  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */
-  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */
-  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */
-  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
-} USB_OTG_OUTEndpointTypeDef;
-
-
-/**
-  * @brief USB_OTG_Host_Mode_Register_Structures
-  */
-typedef struct
-{
-  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */
-  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */
-  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */
-  uint32_t Reserved40C;           /*!< Reserved                             40Ch */
-  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */
-  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */
-  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */
-} USB_OTG_HostTypeDef;
-
-/**
-  * @brief USB_OTG_Host_Channel_Specific_Registers
-  */
-typedef struct
-{
-  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */
-  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */
-  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */
-  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */
-  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */
-  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */
-  uint32_t Reserved[2];           /*!< Reserved                                      */
-} USB_OTG_HostChannelTypeDef;
-/**
-  * @}
-  */
-
-
-
-
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-#define RAMITCM_BASE           0x00000000U /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM  */
-#define FLASHITCM_BASE         0x00200000U /*!< Base address of : (up to 1 MB) embedded FLASH memory  accessible over ITCM              */
-#define FLASHAXI_BASE          0x08000000U /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI                */
-#define RAMDTCM_BASE           0x20000000U /*!< Base address of : 64KB system data RAM accessible over DTCM                             */
-#define PERIPH_BASE            0x40000000U /*!< Base address of : AHB/ABP Peripherals                                                   */
-#define BKPSRAM_BASE           0x40024000U /*!< Base address of : Backup SRAM(4 KB)                                                     */
-#define QSPI_BASE              0x90000000U /*!< Base address of : QSPI memories  accessible over AXI                                    */
-#define FMC_R_BASE             0xA0000000U /*!< Base address of : FMC Control registers                                                 */
-#define QSPI_R_BASE            0xA0001000U /*!< Base address of : QSPI Control  registers                                               */
-#define SRAM1_BASE             0x20010000U /*!< Base address of : 240KB RAM1 accessible over AXI/AHB                                    */
-#define SRAM2_BASE             0x2004C000U /*!< Base address of : 16KB RAM2 accessible over AXI/AHB                                     */
-#define FLASH_END              0x080FFFFFU /*!< FLASH end address */
-
-/* Legacy define */
-#define FLASH_BASE     FLASHAXI_BASE
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE        PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000U)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)
-#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800U)
-#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00U)
-#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000U)
-#define LPTIM1_BASE           (APB1PERIPH_BASE + 0x2400U)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)
-#define SPDIFRX_BASE          (APB1PERIPH_BASE + 0x4000U)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800U)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00U)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x5000U)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)
-#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)
-#define I2C4_BASE             (APB1PERIPH_BASE + 0x6000U)
-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)
-#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800U)
-#define CEC_BASE              (APB1PERIPH_BASE + 0x6C00U)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)
-#define UART7_BASE            (APB1PERIPH_BASE + 0x7800U)
-#define UART8_BASE            (APB1PERIPH_BASE + 0x7C00U)
-
-/*!< APB2 peripherals */
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000U)
-#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400U)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x1000U)
-#define USART6_BASE           (APB2PERIPH_BASE + 0x1400U)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000U)
-#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100U)
-#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200U)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x2300U)
-#define SDMMC1_BASE           (APB2PERIPH_BASE + 0x2C00U)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)
-#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400U)
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800U)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00U)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000U)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400U)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800U)
-#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000U)
-#define SPI6_BASE             (APB2PERIPH_BASE + 0x5400U)
-#define SAI1_BASE             (APB2PERIPH_BASE + 0x5800U)
-#define SAI2_BASE             (APB2PERIPH_BASE + 0x5C00U)
-#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004U)
-#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024U)
-#define SAI2_Block_A_BASE     (SAI2_BASE + 0x004U)
-#define SAI2_Block_B_BASE     (SAI2_BASE + 0x024U)
-#define LTDC_BASE             (APB2PERIPH_BASE + 0x6800U)
-#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84U)
-#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104U)
-/*!< AHB1 peripherals */
-#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000U)
-#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400U)
-#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800U)
-#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00U)
-#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000U)
-#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400U)
-#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800U)
-#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00U)
-#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000U)
-#define GPIOJ_BASE            (AHB1PERIPH_BASE + 0x2400U)
-#define GPIOK_BASE            (AHB1PERIPH_BASE + 0x2800U)
-#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)
-#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800U)
-#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00U)
-#define UID_BASE              0x1FF0F420U                   /*!< Unique device ID register base address */
-#define FLASHSIZE_BASE        0x1FF0F442U                   /*!< FLASH Size register base address */
-#define PACKAGESIZE_BASE      0x1FFF7BF0U                   /*!< Package size register base address */
-#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000U)
-#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010U)
-#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028U)
-#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040U)
-#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058U)
-#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070U)
-#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088U)
-#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0U)
-#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8U)
-#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400U)
-#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010U)
-#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028U)
-#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040U)
-#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058U)
-#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070U)
-#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088U)
-#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0U)
-#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)
-#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000U)
-#define ETH_MAC_BASE          (ETH_BASE)
-#define ETH_MMC_BASE          (ETH_BASE + 0x0100U)
-#define ETH_PTP_BASE          (ETH_BASE + 0x0700U)
-#define ETH_DMA_BASE          (ETH_BASE + 0x1000U)
-#define DMA2D_BASE            (AHB1PERIPH_BASE + 0xB000U)
-/*!< AHB2 peripherals */
-#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000U)
-#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800U)
-/*!< FMC Bankx registers base address */
-#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000U)
-#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104U)
-#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080U)
-#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140U)
-
-/* Debug MCU registers base address */
-#define DBGMCU_BASE           0xE0042000U
-
-/*!< USB registers base address */
-#define USB_OTG_HS_PERIPH_BASE               0x40040000U
-#define USB_OTG_FS_PERIPH_BASE               0x50000000U
-
-#define USB_OTG_GLOBAL_BASE                  0x000U
-#define USB_OTG_DEVICE_BASE                  0x800U
-#define USB_OTG_IN_ENDPOINT_BASE             0x900U
-#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U
-#define USB_OTG_EP_REG_SIZE                  0x20U
-#define USB_OTG_HOST_BASE                    0x400U
-#define USB_OTG_HOST_PORT_BASE               0x440U
-#define USB_OTG_HOST_CHANNEL_BASE            0x500U
-#define USB_OTG_HOST_CHANNEL_SIZE            0x20U
-#define USB_OTG_PCGCCTL_BASE                 0xE00U
-#define USB_OTG_FIFO_BASE                    0x1000U
-#define USB_OTG_FIFO_SIZE                    0x1000U
-
-/**
-  * @}
-  */
-
-/** @addtogroup Peripheral_declaration
-  * @{
-  */
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
-#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
-#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
-#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define SPDIFRX             ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define UART4               ((USART_TypeDef *) UART4_BASE)
-#define UART5               ((USART_TypeDef *) UART5_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
-#define I2C4                ((I2C_TypeDef *) I2C4_BASE)
-#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
-#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
-#define CEC                 ((CEC_TypeDef *) CEC_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
-#define UART7               ((USART_TypeDef *) UART7_BASE)
-#define UART8               ((USART_TypeDef *) UART8_BASE)
-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
-#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define USART6              ((USART_TypeDef *) USART6_BASE)
-#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
-#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
-#define SDMMC1              ((SDMMC_TypeDef *) SDMMC1_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define SPI4                ((SPI_TypeDef *) SPI4_BASE)
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-#define SPI5                ((SPI_TypeDef *) SPI5_BASE)
-#define SPI6                ((SPI_TypeDef *) SPI6_BASE)
-#define SAI1                ((SAI_TypeDef *) SAI1_BASE)
-#define SAI2                ((SAI_TypeDef *) SAI2_BASE)
-#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
-#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
-#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
-#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
-#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)
-#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
-#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
-#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)
-#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
-#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
-#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
-#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
-#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
-#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
-#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
-#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
-#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
-#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
-#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
-#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
-#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
-#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
-#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
-#define ETH                 ((ETH_TypeDef *) ETH_BASE)
-#define DMA2D               ((DMA2D_TypeDef *)DMA2D_BASE)
-#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
-#define RNG                 ((RNG_TypeDef *) RNG_BASE)
-#define FMC_Bank1           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
-#define FMC_Bank1E          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
-#define FMC_Bank3           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
-#define FMC_Bank5_6         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
-#define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
-#define USB_OTG_HS          ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-
-/******************************************************************************/
-/*                         Peripheral Registers_Bits_Definition               */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Analog to Digital Converter                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          0x00000001U        /*!<Analog watchdog flag                                 */
-#define  ADC_SR_EOC                          0x00000002U        /*!<End of conversion                                    */
-#define  ADC_SR_JEOC                         0x00000004U        /*!<Injected channel end of conversion                   */
-#define  ADC_SR_JSTRT                        0x00000008U        /*!<Injected channel Start flag                          */
-#define  ADC_SR_STRT                         0x00000010U        /*!<Regular channel Start flag                           */
-#define  ADC_SR_OVR                          0x00000020U        /*!<Overrun flag                                         */
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC                             */
-#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable                    */
-#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels               */
-#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
-#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion                  */
-#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels               */
-#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels              */
-#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels          */
-#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels           */
-#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution)                           */
-#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
-
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF                                       */
-#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion                                        */
-#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode                                    */
-#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC)                           */
-#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection                                  */
-#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment                                               */
-#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
-#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      ((uint16_t)0xFFFFU)            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      ((uint16_t)0xFFFFU)            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      ((uint16_t)0xFFFFU)            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      ((uint16_t)0xFFFFU)            /*!<Injected data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag               */
-#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion                  */
-#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag        */
-#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag         */
-#define  ADC_CSR_OVR1                        0x00000020U        /*!<ADC1 Overrun flag                       */
-#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag               */
-#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion                  */
-#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag        */
-#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag         */
-#define  ADC_CSR_OVR2                        0x00002000U        /*!<ADC2 Overrun flag                       */
-#define  ADC_CSR_AWD3                        0x00010000U        /*!<ADC3 Analog watchdog flag               */
-#define  ADC_CSR_EOC3                        0x00020000U        /*!<ADC3 End of conversion                  */
-#define  ADC_CSR_JEOC3                       0x00040000U        /*!<ADC3 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT3                      0x00080000U        /*!<ADC3 Injected channel Start flag        */
-#define  ADC_CSR_STRT3                       0x00100000U        /*!<ADC3 Regular channel Start flag         */
-#define  ADC_CSR_OVR3                        0x00200000U        /*!<ADC3 Overrun flag                       */
-
-/* Legacy defines */
-#define  ADC_CSR_DOVR1                       ADC_CSR_OVR1
-#define  ADC_CSR_DOVR2                       ADC_CSR_OVR2
-#define  ADC_CSR_DOVR3                       ADC_CSR_OVR3
-
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
-#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
-#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
-#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */
-#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
-
-/*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                       0x0000FFFFU         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                       0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Controller Area Network                            */
-/*                                                                            */
-/******************************************************************************/
-/*!<CAN control and status registers */
-/*******************  Bit definition for CAN_MCR register  ********************/
-#define  CAN_MCR_INRQ                        0x00000001U        /*!<Initialization Request            */
-#define  CAN_MCR_SLEEP                       0x00000002U        /*!<Sleep Mode Request                */
-#define  CAN_MCR_TXFP                        0x00000004U        /*!<Transmit FIFO Priority            */
-#define  CAN_MCR_RFLM                        0x00000008U        /*!<Receive FIFO Locked Mode          */
-#define  CAN_MCR_NART                        0x00000010U        /*!<No Automatic Retransmission       */
-#define  CAN_MCR_AWUM                        0x00000020U        /*!<Automatic Wakeup Mode             */
-#define  CAN_MCR_ABOM                        0x00000040U        /*!<Automatic Bus-Off Management      */
-#define  CAN_MCR_TTCM                        0x00000080U        /*!<Time Triggered Communication Mode */
-#define  CAN_MCR_RESET                       0x00008000U        /*!<bxCAN software master reset       */
-
-/*******************  Bit definition for CAN_MSR register  ********************/
-#define  CAN_MSR_INAK                        0x00000001U        /*!<Initialization Acknowledge  */
-#define  CAN_MSR_SLAK                        0x00000002U        /*!<Sleep Acknowledge           */
-#define  CAN_MSR_ERRI                        0x00000004U        /*!<Error Interrupt             */
-#define  CAN_MSR_WKUI                        0x00000008U        /*!<Wakeup Interrupt            */
-#define  CAN_MSR_SLAKI                       0x00000010U        /*!<Sleep Acknowledge Interrupt */
-#define  CAN_MSR_TXM                         0x00000100U        /*!<Transmit Mode               */
-#define  CAN_MSR_RXM                         0x00000200U        /*!<Receive Mode                */
-#define  CAN_MSR_SAMP                        0x00000400U        /*!<Last Sample Point           */
-#define  CAN_MSR_RX                          0x00000800U        /*!<CAN Rx Signal               */
-
-/*******************  Bit definition for CAN_TSR register  ********************/
-#define  CAN_TSR_RQCP0                       0x00000001U        /*!<Request Completed Mailbox0      */
-#define  CAN_TSR_TXOK0                       0x00000002U        /*!<Transmission OK of Mailbox0     */
-#define  CAN_TSR_ALST0                       0x00000004U        /*!<Arbitration Lost for Mailbox0   */
-#define  CAN_TSR_TERR0                       0x00000008U        /*!<Transmission Error of Mailbox0  */
-#define  CAN_TSR_ABRQ0                       0x00000080U        /*!<Abort Request for Mailbox0      */
-#define  CAN_TSR_RQCP1                       0x00000100U        /*!<Request Completed Mailbox1      */
-#define  CAN_TSR_TXOK1                       0x00000200U        /*!<Transmission OK of Mailbox1     */
-#define  CAN_TSR_ALST1                       0x00000400U        /*!<Arbitration Lost for Mailbox1   */
-#define  CAN_TSR_TERR1                       0x00000800U        /*!<Transmission Error of Mailbox1  */
-#define  CAN_TSR_ABRQ1                       0x00008000U        /*!<Abort Request for Mailbox 1     */
-#define  CAN_TSR_RQCP2                       0x00010000U        /*!<Request Completed Mailbox2      */
-#define  CAN_TSR_TXOK2                       0x00020000U        /*!<Transmission OK of Mailbox 2    */
-#define  CAN_TSR_ALST2                       0x00040000U        /*!<Arbitration Lost for mailbox 2  */
-#define  CAN_TSR_TERR2                       0x00080000U        /*!<Transmission Error of Mailbox 2 */
-#define  CAN_TSR_ABRQ2                       0x00800000U        /*!<Abort Request for Mailbox 2     */
-#define  CAN_TSR_CODE                        0x03000000U        /*!<Mailbox Code                    */
-
-#define  CAN_TSR_TME                         0x1C000000U        /*!<TME[2:0] bits */
-#define  CAN_TSR_TME0                        0x04000000U        /*!<Transmit Mailbox 0 Empty */
-#define  CAN_TSR_TME1                        0x08000000U        /*!<Transmit Mailbox 1 Empty */
-#define  CAN_TSR_TME2                        0x10000000U        /*!<Transmit Mailbox 2 Empty */
-
-#define  CAN_TSR_LOW                         0xE0000000U        /*!<LOW[2:0] bits */
-#define  CAN_TSR_LOW0                        0x20000000U        /*!<Lowest Priority Flag for Mailbox 0 */
-#define  CAN_TSR_LOW1                        0x40000000U        /*!<Lowest Priority Flag for Mailbox 1 */
-#define  CAN_TSR_LOW2                        0x80000000U        /*!<Lowest Priority Flag for Mailbox 2 */
-
-/*******************  Bit definition for CAN_RF0R register  *******************/
-#define  CAN_RF0R_FMP0                       0x00000003U        /*!<FIFO 0 Message Pending        */
-#define  CAN_RF0R_FULL0                      0x00000008U        /*!<FIFO 0 Full                   */
-#define  CAN_RF0R_FOVR0                      0x00000010U        /*!<FIFO 0 Overrun                */
-#define  CAN_RF0R_RFOM0                      0x00000020U        /*!<Release FIFO 0 Output Mailbox */
-
-/*******************  Bit definition for CAN_RF1R register  *******************/
-#define  CAN_RF1R_FMP1                       0x00000003U        /*!<FIFO 1 Message Pending        */
-#define  CAN_RF1R_FULL1                      0x00000008U        /*!<FIFO 1 Full                   */
-#define  CAN_RF1R_FOVR1                      0x00000010U        /*!<FIFO 1 Overrun                */
-#define  CAN_RF1R_RFOM1                      0x00000020U        /*!<Release FIFO 1 Output Mailbox */
-
-/********************  Bit definition for CAN_IER register  *******************/
-#define  CAN_IER_TMEIE                       0x00000001U        /*!<Transmit Mailbox Empty Interrupt Enable */
-#define  CAN_IER_FMPIE0                      0x00000002U        /*!<FIFO Message Pending Interrupt Enable   */
-#define  CAN_IER_FFIE0                       0x00000004U        /*!<FIFO Full Interrupt Enable              */
-#define  CAN_IER_FOVIE0                      0x00000008U        /*!<FIFO Overrun Interrupt Enable           */
-#define  CAN_IER_FMPIE1                      0x00000010U        /*!<FIFO Message Pending Interrupt Enable   */
-#define  CAN_IER_FFIE1                       0x00000020U        /*!<FIFO Full Interrupt Enable              */
-#define  CAN_IER_FOVIE1                      0x00000040U        /*!<FIFO Overrun Interrupt Enable           */
-#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error Warning Interrupt Enable          */
-#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error Passive Interrupt Enable          */
-#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-Off Interrupt Enable                */
-#define  CAN_IER_LECIE                       0x00000800U        /*!<Last Error Code Interrupt Enable        */
-#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error Interrupt Enable                  */
-#define  CAN_IER_WKUIE                       0x00010000U        /*!<Wakeup Interrupt Enable                 */
-#define  CAN_IER_SLKIE                       0x00020000U        /*!<Sleep Interrupt Enable                  */
-
-/********************  Bit definition for CAN_ESR register  *******************/
-#define  CAN_ESR_EWGF                        0x00000001U        /*!<Error Warning Flag */
-#define  CAN_ESR_EPVF                        0x00000002U        /*!<Error Passive Flag */
-#define  CAN_ESR_BOFF                        0x00000004U        /*!<Bus-Off Flag */
-
-#define  CAN_ESR_LEC                         0x00000070U        /*!<LEC[2:0] bits (Last Error Code) */
-#define  CAN_ESR_LEC_0                       0x00000010U        /*!<Bit 0 */
-#define  CAN_ESR_LEC_1                       0x00000020U        /*!<Bit 1 */
-#define  CAN_ESR_LEC_2                       0x00000040U        /*!<Bit 2 */
-
-#define  CAN_ESR_TEC                         0x00FF0000U        /*!<Least significant byte of the 9-bit Transmit Error Counter */
-#define  CAN_ESR_REC                         0xFF000000U        /*!<Receive Error Counter */
-
-/*******************  Bit definition for CAN_BTR register  ********************/
-#define  CAN_BTR_BRP                         0x000003FFU        /*!<Baud Rate Prescaler           */
-#define  CAN_BTR_TS1                         0x000F0000U        /*!<Time Segment 1                */
-#define  CAN_BTR_TS1_0                       0x00010000U        /*!<Bit 0 */
-#define  CAN_BTR_TS1_1                       0x00020000U        /*!<Bit 1 */
-#define  CAN_BTR_TS1_2                       0x00040000U        /*!<Bit 2 */
-#define  CAN_BTR_TS1_3                       0x00080000U        /*!<Bit 3 */
-#define  CAN_BTR_TS2                         0x00700000U        /*!<Time Segment 2                */
-#define  CAN_BTR_TS2_0                       0x00100000U        /*!<Bit 0 */
-#define  CAN_BTR_TS2_1                       0x00200000U        /*!<Bit 1 */
-#define  CAN_BTR_TS2_2                       0x00400000U        /*!<Bit 2 */
-#define  CAN_BTR_SJW                         0x03000000U        /*!<Resynchronization Jump Width  */
-#define  CAN_BTR_SJW_0                       0x01000000U        /*!<Bit 0 */
-#define  CAN_BTR_SJW_1                       0x02000000U        /*!<Bit 1 */
-#define  CAN_BTR_LBKM                        0x40000000U        /*!<Loop Back Mode (Debug)        */
-#define  CAN_BTR_SILM                        0x80000000U        /*!<Silent Mode                   */
-
-/*!<Mailbox registers */
-/******************  Bit definition for CAN_TI0R register  ********************/
-#define  CAN_TI0R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request                   */
-#define  CAN_TI0R_RTR                        0x00000002U        /*!<Remote Transmission Request                */
-#define  CAN_TI0R_IDE                        0x00000004U        /*!<Identifier Extension                       */
-#define  CAN_TI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier                        */
-#define  CAN_TI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/******************  Bit definition for CAN_TDT0R register  *******************/
-#define  CAN_TDT0R_DLC                       0x0000000FU        /*!<Data Length Code     */
-#define  CAN_TDT0R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp   */
-
-/******************  Bit definition for CAN_TDL0R register  *******************/
-#define  CAN_TDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/******************  Bit definition for CAN_TDH0R register  *******************/
-#define  CAN_TDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI1R register  *******************/
-#define  CAN_TI1R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request                   */
-#define  CAN_TI1R_RTR                        0x00000002U        /*!<Remote Transmission Request                */
-#define  CAN_TI1R_IDE                        0x00000004U        /*!<Identifier Extension                       */
-#define  CAN_TI1R_EXID                       0x001FFFF8U        /*!<Extended Identifier                        */
-#define  CAN_TI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT1R register  ******************/
-#define  CAN_TDT1R_DLC                       0x0000000FU        /*!<Data Length Code     */
-#define  CAN_TDT1R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp   */
-
-/*******************  Bit definition for CAN_TDL1R register  ******************/
-#define  CAN_TDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH1R register  ******************/
-#define  CAN_TDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI2R register  *******************/
-#define  CAN_TI2R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request                   */
-#define  CAN_TI2R_RTR                        0x00000002U        /*!<Remote Transmission Request                */
-#define  CAN_TI2R_IDE                        0x00000004U        /*!<Identifier Extension                       */
-#define  CAN_TI2R_EXID                       0x001FFFF8U        /*!<Extended identifier                        */
-#define  CAN_TI2R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT2R register  ******************/
-#define  CAN_TDT2R_DLC                       0x0000000FU        /*!<Data Length Code      */
-#define  CAN_TDT2R_TGT                       0x00000100U        /*!<Transmit Global Time  */
-#define  CAN_TDT2R_TIME                      0xFFFF0000U        /*!<Message Time Stamp    */
-
-/*******************  Bit definition for CAN_TDL2R register  ******************/
-#define  CAN_TDL2R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL2R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL2R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL2R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH2R register  ******************/
-#define  CAN_TDH2R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH2R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH2R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH2R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI0R register  *******************/
-#define  CAN_RI0R_RTR                        0x00000002U        /*!<Remote Transmission Request                */
-#define  CAN_RI0R_IDE                        0x00000004U        /*!<Identifier Extension                       */
-#define  CAN_RI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier                        */
-#define  CAN_RI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT0R register  ******************/
-#define  CAN_RDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_RDT0R_FMI                       0x0000FF00U        /*!<Filter Match Index */
-#define  CAN_RDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL0R register  ******************/
-#define  CAN_RDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_RDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_RDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_RDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH0R register  ******************/
-#define  CAN_RDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_RDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_RDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_RDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI1R register  *******************/
-#define  CAN_RI1R_RTR                        0x00000002U        /*!<Remote Transmission Request                */
-#define  CAN_RI1R_IDE                        0x00000004U        /*!<Identifier Extension                       */
-#define  CAN_RI1R_EXID                       0x001FFFF8U        /*!<Extended identifier                        */
-#define  CAN_RI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT1R register  ******************/
-#define  CAN_RDT1R_DLC                       0x0000000FU        /*!<Data Length Code   */
-#define  CAN_RDT1R_FMI                       0x0000FF00U        /*!<Filter Match Index */
-#define  CAN_RDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL1R register  ******************/
-#define  CAN_RDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_RDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_RDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_RDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH1R register  ******************/
-#define  CAN_RDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_RDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_RDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_RDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*!<CAN filter registers */
-/*******************  Bit definition for CAN_FMR register  ********************/
-#define  CAN_FMR_FINIT                       ((uint8_t)0x01U)               /*!<Filter Init Mode */
-#define  CAN_FMR_CAN2SB                      0x00003F00U        /*!<CAN2 start bank */
-
-/*******************  Bit definition for CAN_FM1R register  *******************/
-#define  CAN_FM1R_FBM                        0x3FFFU            /*!<Filter Mode */
-#define  CAN_FM1R_FBM0                       0x0001U            /*!<Filter Init Mode bit 0  */
-#define  CAN_FM1R_FBM1                       0x0002U            /*!<Filter Init Mode bit 1  */
-#define  CAN_FM1R_FBM2                       0x0004U            /*!<Filter Init Mode bit 2  */
-#define  CAN_FM1R_FBM3                       0x0008U            /*!<Filter Init Mode bit 3  */
-#define  CAN_FM1R_FBM4                       0x0010U            /*!<Filter Init Mode bit 4  */
-#define  CAN_FM1R_FBM5                       0x0020U            /*!<Filter Init Mode bit 5  */
-#define  CAN_FM1R_FBM6                       0x0040U            /*!<Filter Init Mode bit 6  */
-#define  CAN_FM1R_FBM7                       0x0080U            /*!<Filter Init Mode bit 7  */
-#define  CAN_FM1R_FBM8                       0x0100U            /*!<Filter Init Mode bit 8  */
-#define  CAN_FM1R_FBM9                       0x0200U            /*!<Filter Init Mode bit 9  */
-#define  CAN_FM1R_FBM10                      0x0400U            /*!<Filter Init Mode bit 10 */
-#define  CAN_FM1R_FBM11                      0x0800U            /*!<Filter Init Mode bit 11 */
-#define  CAN_FM1R_FBM12                      0x1000U            /*!<Filter Init Mode bit 12 */
-#define  CAN_FM1R_FBM13                      0x2000U            /*!<Filter Init Mode bit 13 */
-
-/*******************  Bit definition for CAN_FS1R register  *******************/
-#define  CAN_FS1R_FSC                        0x00003FFFU        /*!<Filter Scale Configuration        */
-#define  CAN_FS1R_FSC0                       0x00000001U        /*!<Filter Scale Configuration bit 0  */
-#define  CAN_FS1R_FSC1                       0x00000002U        /*!<Filter Scale Configuration bit 1  */
-#define  CAN_FS1R_FSC2                       0x00000004U        /*!<Filter Scale Configuration bit 2  */
-#define  CAN_FS1R_FSC3                       0x00000008U        /*!<Filter Scale Configuration bit 3  */
-#define  CAN_FS1R_FSC4                       0x00000010U        /*!<Filter Scale Configuration bit 4  */
-#define  CAN_FS1R_FSC5                       0x00000020U        /*!<Filter Scale Configuration bit 5  */
-#define  CAN_FS1R_FSC6                       0x00000040U        /*!<Filter Scale Configuration bit 6  */
-#define  CAN_FS1R_FSC7                       0x00000080U        /*!<Filter Scale Configuration bit 7  */
-#define  CAN_FS1R_FSC8                       0x00000100U        /*!<Filter Scale Configuration bit 8  */
-#define  CAN_FS1R_FSC9                       0x00000200U        /*!<Filter Scale Configuration bit 9  */
-#define  CAN_FS1R_FSC10                      0x00000400U        /*!<Filter Scale Configuration bit 10 */
-#define  CAN_FS1R_FSC11                      0x00000800U        /*!<Filter Scale Configuration bit 11 */
-#define  CAN_FS1R_FSC12                      0x00001000U        /*!<Filter Scale Configuration bit 12 */
-#define  CAN_FS1R_FSC13                      0x00002000U        /*!<Filter Scale Configuration bit 13 */
-
-/******************  Bit definition for CAN_FFA1R register  *******************/
-#define  CAN_FFA1R_FFA                       0x00003FFFU        /*!<Filter FIFO Assignment */
-#define  CAN_FFA1R_FFA0                      0x00000001U        /*!<Filter FIFO Assignment for Filter 0 */
-#define  CAN_FFA1R_FFA1                      0x00000002U        /*!<Filter FIFO Assignment for Filter 1 */
-#define  CAN_FFA1R_FFA2                      0x00000004U        /*!<Filter FIFO Assignment for Filter 2 */
-#define  CAN_FFA1R_FFA3                      0x00000008U        /*!<Filter FIFO Assignment for Filter 3 */
-#define  CAN_FFA1R_FFA4                      0x00000010U        /*!<Filter FIFO Assignment for Filter 4 */
-#define  CAN_FFA1R_FFA5                      0x00000020U        /*!<Filter FIFO Assignment for Filter 5 */
-#define  CAN_FFA1R_FFA6                      0x00000040U        /*!<Filter FIFO Assignment for Filter 6 */
-#define  CAN_FFA1R_FFA7                      0x00000080U        /*!<Filter FIFO Assignment for Filter 7 */
-#define  CAN_FFA1R_FFA8                      0x00000100U        /*!<Filter FIFO Assignment for Filter 8 */
-#define  CAN_FFA1R_FFA9                      0x00000200U        /*!<Filter FIFO Assignment for Filter 9 */
-#define  CAN_FFA1R_FFA10                     0x00000400U        /*!<Filter FIFO Assignment for Filter 10 */
-#define  CAN_FFA1R_FFA11                     0x00000800U        /*!<Filter FIFO Assignment for Filter 11 */
-#define  CAN_FFA1R_FFA12                     0x00001000U        /*!<Filter FIFO Assignment for Filter 12 */
-#define  CAN_FFA1R_FFA13                     0x00002000U        /*!<Filter FIFO Assignment for Filter 13 */
-
-/*******************  Bit definition for CAN_FA1R register  *******************/
-#define  CAN_FA1R_FACT                       0x00003FFFU        /*!<Filter Active    */
-#define  CAN_FA1R_FACT0                      0x00000001U        /*!<Filter 0 Active  */
-#define  CAN_FA1R_FACT1                      0x00000002U        /*!<Filter 1 Active  */
-#define  CAN_FA1R_FACT2                      0x00000004U        /*!<Filter 2 Active  */
-#define  CAN_FA1R_FACT3                      0x00000008U        /*!<Filter 3 Active  */
-#define  CAN_FA1R_FACT4                      0x00000010U        /*!<Filter 4 Active  */
-#define  CAN_FA1R_FACT5                      0x00000020U        /*!<Filter 5 Active  */
-#define  CAN_FA1R_FACT6                      0x00000040U        /*!<Filter 6 Active  */
-#define  CAN_FA1R_FACT7                      0x00000080U        /*!<Filter 7 Active  */
-#define  CAN_FA1R_FACT8                      0x00000100U        /*!<Filter 8 Active  */
-#define  CAN_FA1R_FACT9                      0x00000200U        /*!<Filter 9 Active  */
-#define  CAN_FA1R_FACT10                     0x00000400U        /*!<Filter 10 Active */
-#define  CAN_FA1R_FACT11                     0x00000800U        /*!<Filter 11 Active */
-#define  CAN_FA1R_FACT12                     0x00001000U        /*!<Filter 12 Active */
-#define  CAN_FA1R_FACT13                     0x00002000U        /*!<Filter 13 Active */
-
-/*******************  Bit definition for CAN_F0R1 register  *******************/
-#define  CAN_F0R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F0R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F0R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F0R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F0R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F0R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F0R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F0R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F0R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F0R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F0R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F0R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F0R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F0R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F0R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F0R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F0R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F0R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F0R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F0R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F0R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F0R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F0R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F0R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F0R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F0R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F0R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F0R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F0R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F0R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F0R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F0R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R1 register  *******************/
-#define  CAN_F1R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F1R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F1R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F1R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F1R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F1R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F1R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F1R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F1R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F1R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F1R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F1R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F1R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F1R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F1R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F1R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F1R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F1R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F1R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F1R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F1R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F1R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F1R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F1R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F1R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F1R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F1R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F1R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F1R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F1R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F1R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F1R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R1 register  *******************/
-#define  CAN_F2R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F2R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F2R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F2R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F2R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F2R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F2R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F2R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F2R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F2R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F2R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F2R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F2R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F2R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F2R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F2R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F2R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F2R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F2R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F2R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F2R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F2R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F2R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F2R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F2R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F2R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F2R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F2R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F2R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F2R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F2R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F2R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R1 register  *******************/
-#define  CAN_F3R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F3R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F3R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F3R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F3R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F3R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F3R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F3R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F3R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F3R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F3R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F3R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F3R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F3R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F3R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F3R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F3R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F3R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F3R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F3R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F3R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F3R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F3R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F3R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F3R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F3R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F3R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F3R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F3R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F3R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F3R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F3R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R1 register  *******************/
-#define  CAN_F4R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F4R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F4R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F4R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F4R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F4R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F4R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F4R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F4R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F4R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F4R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F4R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F4R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F4R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F4R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F4R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F4R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F4R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F4R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F4R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F4R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F4R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F4R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F4R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F4R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F4R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F4R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F4R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F4R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F4R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F4R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F4R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R1 register  *******************/
-#define  CAN_F5R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F5R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F5R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F5R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F5R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F5R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F5R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F5R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F5R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F5R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F5R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F5R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F5R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F5R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F5R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F5R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F5R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F5R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F5R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F5R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F5R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F5R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F5R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F5R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F5R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F5R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F5R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F5R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F5R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F5R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F5R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F5R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R1 register  *******************/
-#define  CAN_F6R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F6R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F6R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F6R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F6R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F6R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F6R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F6R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F6R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F6R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F6R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F6R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F6R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F6R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F6R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F6R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F6R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F6R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F6R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F6R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F6R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F6R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F6R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F6R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F6R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F6R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F6R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F6R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F6R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F6R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F6R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F6R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R1 register  *******************/
-#define  CAN_F7R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F7R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F7R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F7R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F7R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F7R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F7R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F7R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F7R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F7R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F7R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F7R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F7R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F7R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F7R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F7R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F7R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F7R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F7R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F7R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F7R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F7R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F7R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F7R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F7R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F7R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F7R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F7R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F7R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F7R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F7R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F7R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R1 register  *******************/
-#define  CAN_F8R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F8R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F8R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F8R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F8R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F8R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F8R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F8R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F8R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F8R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F8R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F8R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F8R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F8R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F8R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F8R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F8R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F8R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F8R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F8R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F8R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F8R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F8R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F8R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F8R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F8R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F8R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F8R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F8R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F8R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F8R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F8R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R1 register  *******************/
-#define  CAN_F9R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F9R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F9R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F9R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F9R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F9R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F9R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F9R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F9R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F9R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F9R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F9R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F9R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F9R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F9R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F9R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F9R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F9R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F9R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F9R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F9R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F9R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F9R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F9R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F9R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F9R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F9R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F9R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F9R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F9R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F9R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F9R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R1 register  ******************/
-#define  CAN_F10R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F10R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F10R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F10R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F10R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F10R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F10R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F10R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F10R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F10R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F10R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F10R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F10R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F10R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F10R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F10R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F10R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F10R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F10R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F10R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F10R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F10R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F10R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F10R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F10R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F10R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F10R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F10R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F10R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F10R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F10R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F10R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R1 register  ******************/
-#define  CAN_F11R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F11R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F11R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F11R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F11R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F11R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F11R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F11R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F11R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F11R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F11R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F11R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F11R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F11R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F11R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F11R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F11R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F11R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F11R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F11R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F11R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F11R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F11R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F11R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F11R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F11R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F11R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F11R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F11R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F11R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F11R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F11R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R1 register  ******************/
-#define  CAN_F12R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F12R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F12R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F12R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F12R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F12R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F12R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F12R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F12R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F12R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F12R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F12R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F12R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F12R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F12R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F12R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F12R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F12R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F12R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F12R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F12R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F12R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F12R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F12R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F12R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F12R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F12R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F12R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F12R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F12R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F12R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F12R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R1 register  ******************/
-#define  CAN_F13R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F13R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F13R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F13R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F13R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F13R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F13R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F13R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F13R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F13R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F13R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F13R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F13R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F13R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F13R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F13R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F13R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F13R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F13R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F13R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F13R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F13R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F13R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F13R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F13R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F13R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F13R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F13R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F13R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F13R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F13R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F13R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F0R2 register  *******************/
-#define  CAN_F0R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F0R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F0R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F0R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F0R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F0R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F0R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F0R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F0R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F0R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F0R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F0R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F0R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F0R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F0R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F0R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F0R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F0R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F0R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F0R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F0R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F0R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F0R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F0R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F0R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F0R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F0R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F0R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F0R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F0R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F0R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F0R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R2 register  *******************/
-#define  CAN_F1R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F1R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F1R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F1R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F1R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F1R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F1R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F1R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F1R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F1R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F1R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F1R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F1R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F1R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F1R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F1R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F1R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F1R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F1R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F1R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F1R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F1R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F1R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F1R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F1R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F1R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F1R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F1R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F1R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F1R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F1R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F1R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R2 register  *******************/
-#define  CAN_F2R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F2R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F2R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F2R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F2R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F2R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F2R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F2R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F2R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F2R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F2R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F2R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F2R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F2R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F2R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F2R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F2R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F2R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F2R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F2R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F2R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F2R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F2R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F2R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F2R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F2R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F2R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F2R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F2R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F2R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F2R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F2R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R2 register  *******************/
-#define  CAN_F3R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F3R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F3R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F3R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F3R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F3R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F3R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F3R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F3R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F3R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F3R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F3R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F3R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F3R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F3R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F3R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F3R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F3R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F3R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F3R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F3R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F3R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F3R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F3R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F3R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F3R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F3R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F3R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F3R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F3R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F3R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F3R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R2 register  *******************/
-#define  CAN_F4R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F4R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F4R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F4R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F4R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F4R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F4R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F4R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F4R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F4R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F4R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F4R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F4R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F4R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F4R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F4R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F4R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F4R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F4R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F4R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F4R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F4R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F4R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F4R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F4R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F4R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F4R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F4R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F4R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F4R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F4R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F4R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R2 register  *******************/
-#define  CAN_F5R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F5R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F5R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F5R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F5R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F5R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F5R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F5R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F5R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F5R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F5R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F5R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F5R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F5R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F5R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F5R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F5R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F5R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F5R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F5R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F5R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F5R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F5R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F5R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F5R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F5R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F5R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F5R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F5R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F5R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F5R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F5R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R2 register  *******************/
-#define  CAN_F6R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F6R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F6R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F6R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F6R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F6R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F6R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F6R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F6R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F6R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F6R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F6R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F6R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F6R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F6R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F6R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F6R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F6R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F6R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F6R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F6R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F6R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F6R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F6R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F6R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F6R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F6R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F6R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F6R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F6R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F6R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F6R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R2 register  *******************/
-#define  CAN_F7R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F7R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F7R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F7R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F7R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F7R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F7R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F7R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F7R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F7R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F7R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F7R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F7R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F7R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F7R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F7R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F7R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F7R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F7R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F7R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F7R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F7R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F7R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F7R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F7R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F7R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F7R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F7R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F7R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F7R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F7R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F7R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R2 register  *******************/
-#define  CAN_F8R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F8R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F8R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F8R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F8R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F8R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F8R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F8R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F8R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F8R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F8R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F8R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F8R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F8R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F8R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F8R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F8R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F8R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F8R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F8R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F8R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F8R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F8R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F8R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F8R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F8R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F8R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F8R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F8R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F8R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F8R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F8R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R2 register  *******************/
-#define  CAN_F9R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F9R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F9R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F9R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F9R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F9R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F9R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F9R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F9R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F9R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F9R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F9R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F9R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F9R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F9R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F9R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F9R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F9R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F9R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F9R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F9R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F9R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F9R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F9R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F9R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F9R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F9R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F9R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F9R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F9R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F9R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F9R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R2 register  ******************/
-#define  CAN_F10R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F10R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F10R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F10R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F10R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F10R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F10R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F10R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F10R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F10R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F10R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F10R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F10R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F10R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F10R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F10R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F10R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F10R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F10R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F10R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F10R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F10R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F10R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F10R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F10R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F10R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F10R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F10R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F10R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F10R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F10R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F10R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R2 register  ******************/
-#define  CAN_F11R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F11R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F11R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F11R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F11R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F11R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F11R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F11R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F11R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F11R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F11R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F11R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F11R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F11R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F11R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F11R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F11R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F11R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F11R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F11R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F11R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F11R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F11R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F11R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F11R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F11R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F11R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F11R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F11R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F11R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F11R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F11R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R2 register  ******************/
-#define  CAN_F12R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F12R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F12R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F12R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F12R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F12R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F12R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F12R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F12R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F12R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F12R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F12R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F12R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F12R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F12R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F12R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F12R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F12R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F12R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F12R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F12R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F12R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F12R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F12R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F12R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F12R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F12R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F12R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F12R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F12R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F12R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F12R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R2 register  ******************/
-#define  CAN_F13R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F13R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F13R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F13R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F13R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F13R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F13R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F13R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F13R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F13R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F13R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F13R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F13R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F13R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F13R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F13R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F13R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F13R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F13R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F13R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F13R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F13R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F13R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F13R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F13R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F13R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F13R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F13R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F13R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F13R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F13R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F13R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 HDMI-CEC (CEC)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CEC_CR register  *********************/
-#define  CEC_CR_CECEN                        0x00000001U       /*!< CEC Enable                         */
-#define  CEC_CR_TXSOM                        0x00000002U       /*!< CEC Tx Start Of Message            */
-#define  CEC_CR_TXEOM                        0x00000004U       /*!< CEC Tx End Of Message              */
-
-/*******************  Bit definition for CEC_CFGR register  *******************/
-#define  CEC_CFGR_SFT                        0x00000007U       /*!< CEC Signal Free Time               */
-#define  CEC_CFGR_RXTOL                      0x00000008U       /*!< CEC Tolerance                      */
-#define  CEC_CFGR_BRESTP                     0x00000010U       /*!< CEC Rx Stop                        */
-#define  CEC_CFGR_BREGEN                     0x00000020U       /*!< CEC Bit Rising Error generation    */
-#define  CEC_CFGR_LBPEGEN                    0x00000040U       /*!< CEC Long Period Error generation   */
-#define  CEC_CFGR_BRDNOGEN                   0x00000080U       /*!< CEC Broadcast no Error generation  */
-#define  CEC_CFGR_SFTOPT                     0x00000100U       /*!< CEC Signal Free Time optional      */
-#define  CEC_CFGR_OAR                        0x7FFF0000U       /*!< CEC Own Address                    */
-#define  CEC_CFGR_LSTN                       0x80000000U       /*!< CEC Listen mode                    */
-
-/*******************  Bit definition for CEC_TXDR register  *******************/
-#define  CEC_TXDR_TXD                        0x000000FFU       /*!< CEC Tx Data                        */
-
-/*******************  Bit definition for CEC_RXDR register  *******************/
-#define  CEC_TXDR_RXD                        0x000000FFU       /*!< CEC Rx Data                        */
-
-/*******************  Bit definition for CEC_ISR register  ********************/
-#define  CEC_ISR_RXBR                        0x00000001U       /*!< CEC Rx-Byte Received                   */
-#define  CEC_ISR_RXEND                       0x00000002U       /*!< CEC End Of Reception                   */
-#define  CEC_ISR_RXOVR                       0x00000004U       /*!< CEC Rx-Overrun                         */
-#define  CEC_ISR_BRE                         0x00000008U       /*!< CEC Rx Bit Rising Error                */
-#define  CEC_ISR_SBPE                        0x00000010U       /*!< CEC Rx Short Bit period Error          */
-#define  CEC_ISR_LBPE                        0x00000020U       /*!< CEC Rx Long Bit period Error           */
-#define  CEC_ISR_RXACKE                      0x00000040U       /*!< CEC Rx Missing Acknowledge             */
-#define  CEC_ISR_ARBLST                      0x00000080U       /*!< CEC Arbitration Lost                   */
-#define  CEC_ISR_TXBR                        0x00000100U       /*!< CEC Tx Byte Request                    */
-#define  CEC_ISR_TXEND                       0x00000200U       /*!< CEC End of Transmission                */
-#define  CEC_ISR_TXUDR                       0x00000400U       /*!< CEC Tx-Buffer Underrun                 */
-#define  CEC_ISR_TXERR                       0x00000800U       /*!< CEC Tx-Error                           */
-#define  CEC_ISR_TXACKE                      0x00001000U       /*!< CEC Tx Missing Acknowledge             */
-
-/*******************  Bit definition for CEC_IER register  ********************/
-#define  CEC_IER_RXBRIE                      0x00000001U       /*!< CEC Rx-Byte Received IT Enable         */
-#define  CEC_IER_RXENDIE                     0x00000002U       /*!< CEC End Of Reception IT Enable         */
-#define  CEC_IER_RXOVRIE                     0x00000004U       /*!< CEC Rx-Overrun IT Enable               */
-#define  CEC_IER_BREIE                       0x00000008U       /*!< CEC Rx Bit Rising Error IT Enable      */
-#define  CEC_IER_SBPEIE                      0x00000010U       /*!< CEC Rx Short Bit period Error IT Enable*/
-#define  CEC_IER_LBPEIE                      0x00000020U       /*!< CEC Rx Long Bit period Error IT Enable */
-#define  CEC_IER_RXACKEIE                    0x00000040U       /*!< CEC Rx Missing Acknowledge IT Enable   */
-#define  CEC_IER_ARBLSTIE                    0x00000080U       /*!< CEC Arbitration Lost IT Enable         */
-#define  CEC_IER_TXBRIE                      0x00000100U       /*!< CEC Tx Byte Request  IT Enable         */
-#define  CEC_IER_TXENDIE                     0x00000200U       /*!< CEC End of Transmission IT Enable      */
-#define  CEC_IER_TXUDRIE                     0x00000400U       /*!< CEC Tx-Buffer Underrun IT Enable       */
-#define  CEC_IER_TXERRIE                     0x00000800U       /*!< CEC Tx-Error IT Enable                 */
-#define  CEC_IER_TXACKEIE                    0x00001000U       /*!< CEC Tx Missing Acknowledge IT Enable   */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRC calculation unit                              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           0xFFFFFFFFU     /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         0x000000FFU     /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        0x00000001U     /*!< RESET the CRC computation unit bit */
-#define  CRC_CR_POLYSIZE                     0x00000018U     /*!< Polynomial size bits               */
-#define  CRC_CR_POLYSIZE_0                   0x00000008U     /*!< Polynomial size bit 0              */
-#define  CRC_CR_POLYSIZE_1                   0x00000010U     /*!< Polynomial size bit 1              */
-#define  CRC_CR_REV_IN                       0x00000060U     /*!< REV_IN Reverse Input Data bits     */
-#define  CRC_CR_REV_IN_0                     0x00000020U     /*!< Bit 0 */
-#define  CRC_CR_REV_IN_1                     0x00000040U     /*!< Bit 1 */
-#define  CRC_CR_REV_OUT                      0x00000080U     /*!< REV_OUT Reverse Output Data bits   */
-
-/*******************  Bit definition for CRC_INIT register  *******************/
-#define  CRC_INIT_INIT                       0xFFFFFFFFU     /*!< Initial CRC value bits         */
-
-/*******************  Bit definition for CRC_POL register  ********************/
-#define  CRC_POL_POL                         0xFFFFFFFFU     /*!< Coefficients of the polynomial */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Digital to Analog Converter                           */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DAC_CR register  ********************/
-#define  DAC_CR_EN1                          0x00000001U        /*!<DAC channel1 enable                         */
-#define  DAC_CR_BOFF1                        0x00000002U        /*!<DAC channel1 output buffer disable          */
-#define  DAC_CR_TEN1                         0x00000004U        /*!<DAC channel1 Trigger enable                 */
-#define  DAC_CR_TSEL1                        0x00000038U        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define  DAC_CR_TSEL1_0                      0x00000008U        /*!<Bit 0 */
-#define  DAC_CR_TSEL1_1                      0x00000010U        /*!<Bit 1 */
-#define  DAC_CR_TSEL1_2                      0x00000020U        /*!<Bit 2 */
-#define  DAC_CR_WAVE1                        0x000000C0U        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enablEU) */
-#define  DAC_CR_WAVE1_0                      0x00000040U        /*!<Bit 0 */
-#define  DAC_CR_WAVE1_1                      0x00000080U        /*!<Bit 1 */
-#define  DAC_CR_MAMP1                        0x00000F00U        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP1_0                      0x00000100U        /*!<Bit 0 */
-#define  DAC_CR_MAMP1_1                      0x00000200U        /*!<Bit 1 */
-#define  DAC_CR_MAMP1_2                      0x00000400U        /*!<Bit 2 */
-#define  DAC_CR_MAMP1_3                      0x00000800U        /*!<Bit 3 */
-#define  DAC_CR_DMAEN1                       0x00001000U        /*!<DAC channel1 DMA enable                     */
-#define  DAC_CR_DMAUDRIE1                    0x00002000U        /*!<DAC channel1 DMA underrun interrupt enable  */
-#define  DAC_CR_EN2                          0x00010000U        /*!<DAC channel2 enable                         */
-#define  DAC_CR_BOFF2                        0x00020000U        /*!<DAC channel2 output buffer disable          */
-#define  DAC_CR_TEN2                         0x00040000U        /*!<DAC channel2 Trigger enable                 */
-#define  DAC_CR_TSEL2                        0x00380000U        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define  DAC_CR_TSEL2_0                      0x00080000U        /*!<Bit 0 */
-#define  DAC_CR_TSEL2_1                      0x00100000U        /*!<Bit 1 */
-#define  DAC_CR_TSEL2_2                      0x00200000U        /*!<Bit 2 */
-#define  DAC_CR_WAVE2                        0x00C00000U        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE2_0                      0x00400000U        /*!<Bit 0 */
-#define  DAC_CR_WAVE2_1                      0x00800000U        /*!<Bit 1 */
-#define  DAC_CR_MAMP2                        0x0F000000U        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP2_0                      0x01000000U        /*!<Bit 0 */
-#define  DAC_CR_MAMP2_1                      0x02000000U        /*!<Bit 1 */
-#define  DAC_CR_MAMP2_2                      0x04000000U        /*!<Bit 2 */
-#define  DAC_CR_MAMP2_3                      0x08000000U        /*!<Bit 3 */
-#define  DAC_CR_DMAEN2                       0x10000000U        /*!<DAC channel2 DMA enable                    */
-#define  DAC_CR_DMAUDRIE2                    0x20000000U        /*!<DAC channel2 DMA underrun interrupt enable */
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define  DAC_SWTRIGR_SWTRIG1                 0x01U               /*!<DAC channel1 software trigger */
-#define  DAC_SWTRIGR_SWTRIG2                 0x02U               /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define  DAC_DHR12R1_DACC1DHR                0x0FFFU            /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define  DAC_DHR12L1_DACC1DHR                0xFFF0U            /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define  DAC_DHR8R1_DACC1DHR                 0xFFU               /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define  DAC_DHR12R2_DACC2DHR                0x0FFFU            /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define  DAC_DHR12L2_DACC2DHR                0xFFF0U            /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define  DAC_DHR8R2_DACC2DHR                 0xFFU               /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define  DAC_DHR12RD_DACC1DHR                0x00000FFFU        /*!<DAC channel1 12-bit Right aligned data */
-#define  DAC_DHR12RD_DACC2DHR                0x0FFF0000U        /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define  DAC_DHR12LD_DACC1DHR                0x0000FFF0U        /*!<DAC channel1 12-bit Left aligned data */
-#define  DAC_DHR12LD_DACC2DHR                0xFFF00000U        /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define  DAC_DHR8RD_DACC1DHR                 0x00FFU            /*!<DAC channel1 8-bit Right aligned data */
-#define  DAC_DHR8RD_DACC2DHR                 0xFF00U            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define  DAC_DOR1_DACC1DOR                   0x0FFFU            /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define  DAC_DOR2_DACC2DOR                   0x0FFFU            /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define  DAC_SR_DMAUDR1                      0x00002000U        /*!<DAC channel1 DMA underrun flag */
-#define  DAC_SR_DMAUDR2                      0x20000000U        /*!<DAC channel2 DMA underrun flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 Debug MCU                                  */
-/*                                                                            */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    DCMI                                    */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DCMI_CR register  ******************/
-#define DCMI_CR_CAPTURE                      0x00000001U
-#define DCMI_CR_CM                           0x00000002U
-#define DCMI_CR_CROP                         0x00000004U
-#define DCMI_CR_JPEG                         0x00000008U
-#define DCMI_CR_ESS                          0x00000010U
-#define DCMI_CR_PCKPOL                       0x00000020U
-#define DCMI_CR_HSPOL                        0x00000040U
-#define DCMI_CR_VSPOL                        0x00000080U
-#define DCMI_CR_FCRC_0                       0x00000100U
-#define DCMI_CR_FCRC_1                       0x00000200U
-#define DCMI_CR_EDM_0                        0x00000400U
-#define DCMI_CR_EDM_1                        0x00000800U
-#define DCMI_CR_CRE                          0x00001000U
-#define DCMI_CR_ENABLE                       0x00004000U
-#define DCMI_CR_BSM                          0x00030000U
-#define DCMI_CR_BSM_0                        0x00010000U
-#define DCMI_CR_BSM_1                        0x00020000U
-#define DCMI_CR_OEBS                         0x00040000U
-#define DCMI_CR_LSM                          0x00080000U
-#define DCMI_CR_OELS                         0x00100000U
-
-/********************  Bits definition for DCMI_SR register  ******************/
-#define DCMI_SR_HSYNC                        0x00000001U
-#define DCMI_SR_VSYNC                        0x00000002U
-#define DCMI_SR_FNE                          0x00000004U
-
-/********************  Bits definition for DCMI_RIS register   ****************/
-#define DCMI_RIS_FRAME_RIS                   0x00000001U
-#define DCMI_RIS_OVR_RIS                     0x00000002U
-#define DCMI_RIS_ERR_RIS                     0x00000004U
-#define DCMI_RIS_VSYNC_RIS                   0x00000008U
-#define DCMI_RIS_LINE_RIS                    0x00000010U
-
-/* Legacy defines */
-#define DCMI_RISR_FRAME_RIS                  DCMI_RIS_FRAME_RIS
-#define DCMI_RISR_OVF_RIS                    DCMI_RIS_OVR_RIS
-#define DCMI_RISR_ERR_RIS                    DCMI_RIS_ERR_RIS
-#define DCMI_RISR_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS
-#define DCMI_RISR_LINE_RIS                   DCMI_RIS_LINE_RIS
-
-/********************  Bits definition for DCMI_IER register  *****************/
-#define DCMI_IER_FRAME_IE                    0x00000001U
-#define DCMI_IER_OVR_IE                      0x00000002U
-#define DCMI_IER_ERR_IE                      0x00000004U
-#define DCMI_IER_VSYNC_IE                    0x00000008U
-#define DCMI_IER_LINE_IE                     0x00000010U
-
-/* Legacy define */
-#define DCMI_IER_OVF_IE                      DCMI_IER_OVR_IE
-
-/********************  Bits definition for DCMI_MIS register  *****************/
-#define DCMI_MIS_FRAME_MIS                   0x00000001U
-#define DCMI_MIS_OVR_MIS                     0x00000002U
-#define DCMI_MIS_ERR_MIS                     0x00000004U
-#define DCMI_MIS_VSYNC_MIS                   0x00000008U
-#define DCMI_MIS_LINE_MIS                    0x00000010U
-
-/* Legacy defines */
-#define DCMI_MISR_FRAME_MIS                  DCMI_MIS_FRAME_MIS
-#define DCMI_MISR_OVF_MIS                    DCMI_MIS_OVR_MIS
-#define DCMI_MISR_ERR_MIS                    DCMI_MIS_ERR_MIS
-#define DCMI_MISR_VSYNC_MIS                  DCMI_MIS_VSYNC_MIS
-#define DCMI_MISR_LINE_MIS                   DCMI_MIS_LINE_MIS
-
-/********************  Bits definition for DCMI_ICR register  *****************/
-#define DCMI_ICR_FRAME_ISC                   0x00000001U
-#define DCMI_ICR_OVR_ISC                     0x00000002U
-#define DCMI_ICR_ERR_ISC                     0x00000004U
-#define DCMI_ICR_VSYNC_ISC                   0x00000008U
-#define DCMI_ICR_LINE_ISC                    0x00000010U
-
-/* Legacy defines */
-#define DCMI_ICR_OVF_ISC                     DCMI_ICR_OVR_ISC
-
-/********************  Bits definition for DCMI_ESCR register  ******************/
-#define DCMI_ESCR_FSC                        0x000000FFU
-#define DCMI_ESCR_LSC                        0x0000FF00U
-#define DCMI_ESCR_LEC                        0x00FF0000U
-#define DCMI_ESCR_FEC                        0xFF000000U
-
-/********************  Bits definition for DCMI_ESUR register  ******************/
-#define DCMI_ESUR_FSU                        0x000000FFU
-#define DCMI_ESUR_LSU                        0x0000FF00U
-#define DCMI_ESUR_LEU                        0x00FF0000U
-#define DCMI_ESUR_FEU                        0xFF000000U
-
-/********************  Bits definition for DCMI_CWSTRT register  ******************/
-#define DCMI_CWSTRT_HOFFCNT                  0x00003FFFU
-#define DCMI_CWSTRT_VST                      0x1FFF0000U
-
-/********************  Bits definition for DCMI_CWSIZE register  ******************/
-#define DCMI_CWSIZE_CAPCNT                   0x00003FFFU
-#define DCMI_CWSIZE_VLINE                    0x3FFF0000U
-
-/********************  Bits definition for DCMI_DR register  ******************/
-#define DCMI_DR_BYTE0                        0x000000FFU
-#define DCMI_DR_BYTE1                        0x0000FF00U
-#define DCMI_DR_BYTE2                        0x00FF0000U
-#define DCMI_DR_BYTE3                        0xFF000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                             DMA Controller                                 */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DMA_SxCR register  *****************/
-#define DMA_SxCR_CHSEL                       0x0E000000U
-#define DMA_SxCR_CHSEL_0                     0x02000000U
-#define DMA_SxCR_CHSEL_1                     0x04000000U
-#define DMA_SxCR_CHSEL_2                     0x08000000U
-#define DMA_SxCR_MBURST                      0x01800000U
-#define DMA_SxCR_MBURST_0                    0x00800000U
-#define DMA_SxCR_MBURST_1                    0x01000000U
-#define DMA_SxCR_PBURST                      0x00600000U
-#define DMA_SxCR_PBURST_0                    0x00200000U
-#define DMA_SxCR_PBURST_1                    0x00400000U
-#define DMA_SxCR_CT                          0x00080000U
-#define DMA_SxCR_DBM                         0x00040000U
-#define DMA_SxCR_PL                          0x00030000U
-#define DMA_SxCR_PL_0                        0x00010000U
-#define DMA_SxCR_PL_1                        0x00020000U
-#define DMA_SxCR_PINCOS                      0x00008000U
-#define DMA_SxCR_MSIZE                       0x00006000U
-#define DMA_SxCR_MSIZE_0                     0x00002000U
-#define DMA_SxCR_MSIZE_1                     0x00004000U
-#define DMA_SxCR_PSIZE                       0x00001800U
-#define DMA_SxCR_PSIZE_0                     0x00000800U
-#define DMA_SxCR_PSIZE_1                     0x00001000U
-#define DMA_SxCR_MINC                        0x00000400U
-#define DMA_SxCR_PINC                        0x00000200U
-#define DMA_SxCR_CIRC                        0x00000100U
-#define DMA_SxCR_DIR                         0x000000C0U
-#define DMA_SxCR_DIR_0                       0x00000040U
-#define DMA_SxCR_DIR_1                       0x00000080U
-#define DMA_SxCR_PFCTRL                      0x00000020U
-#define DMA_SxCR_TCIE                        0x00000010U
-#define DMA_SxCR_HTIE                        0x00000008U
-#define DMA_SxCR_TEIE                        0x00000004U
-#define DMA_SxCR_DMEIE                       0x00000002U
-#define DMA_SxCR_EN                          0x00000001U
-
-/********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            0x0000FFFFU
-#define DMA_SxNDT_0                          0x00000001U
-#define DMA_SxNDT_1                          0x00000002U
-#define DMA_SxNDT_2                          0x00000004U
-#define DMA_SxNDT_3                          0x00000008U
-#define DMA_SxNDT_4                          0x00000010U
-#define DMA_SxNDT_5                          0x00000020U
-#define DMA_SxNDT_6                          0x00000040U
-#define DMA_SxNDT_7                          0x00000080U
-#define DMA_SxNDT_8                          0x00000100U
-#define DMA_SxNDT_9                          0x00000200U
-#define DMA_SxNDT_10                         0x00000400U
-#define DMA_SxNDT_11                         0x00000800U
-#define DMA_SxNDT_12                         0x00001000U
-#define DMA_SxNDT_13                         0x00002000U
-#define DMA_SxNDT_14                         0x00004000U
-#define DMA_SxNDT_15                         0x00008000U
-
-/********************  Bits definition for DMA_SxFCR register  ****************/
-#define DMA_SxFCR_FEIE                       0x00000080U
-#define DMA_SxFCR_FS                         0x00000038U
-#define DMA_SxFCR_FS_0                       0x00000008U
-#define DMA_SxFCR_FS_1                       0x00000010U
-#define DMA_SxFCR_FS_2                       0x00000020U
-#define DMA_SxFCR_DMDIS                      0x00000004U
-#define DMA_SxFCR_FTH                        0x00000003U
-#define DMA_SxFCR_FTH_0                      0x00000001U
-#define DMA_SxFCR_FTH_1                      0x00000002U
-
-/********************  Bits definition for DMA_LISR register  *****************/
-#define DMA_LISR_TCIF3                       0x08000000U
-#define DMA_LISR_HTIF3                       0x04000000U
-#define DMA_LISR_TEIF3                       0x02000000U
-#define DMA_LISR_DMEIF3                      0x01000000U
-#define DMA_LISR_FEIF3                       0x00400000U
-#define DMA_LISR_TCIF2                       0x00200000U
-#define DMA_LISR_HTIF2                       0x00100000U
-#define DMA_LISR_TEIF2                       0x00080000U
-#define DMA_LISR_DMEIF2                      0x00040000U
-#define DMA_LISR_FEIF2                       0x00010000U
-#define DMA_LISR_TCIF1                       0x00000800U
-#define DMA_LISR_HTIF1                       0x00000400U
-#define DMA_LISR_TEIF1                       0x00000200U
-#define DMA_LISR_DMEIF1                      0x00000100U
-#define DMA_LISR_FEIF1                       0x00000040U
-#define DMA_LISR_TCIF0                       0x00000020U
-#define DMA_LISR_HTIF0                       0x00000010U
-#define DMA_LISR_TEIF0                       0x00000008U
-#define DMA_LISR_DMEIF0                      0x00000004U
-#define DMA_LISR_FEIF0                       0x00000001U
-
-/********************  Bits definition for DMA_HISR register  *****************/
-#define DMA_HISR_TCIF7                       0x08000000U
-#define DMA_HISR_HTIF7                       0x04000000U
-#define DMA_HISR_TEIF7                       0x02000000U
-#define DMA_HISR_DMEIF7                      0x01000000U
-#define DMA_HISR_FEIF7                       0x00400000U
-#define DMA_HISR_TCIF6                       0x00200000U
-#define DMA_HISR_HTIF6                       0x00100000U
-#define DMA_HISR_TEIF6                       0x00080000U
-#define DMA_HISR_DMEIF6                      0x00040000U
-#define DMA_HISR_FEIF6                       0x00010000U
-#define DMA_HISR_TCIF5                       0x00000800U
-#define DMA_HISR_HTIF5                       0x00000400U
-#define DMA_HISR_TEIF5                       0x00000200U
-#define DMA_HISR_DMEIF5                      0x00000100U
-#define DMA_HISR_FEIF5                       0x00000040U
-#define DMA_HISR_TCIF4                       0x00000020U
-#define DMA_HISR_HTIF4                       0x00000010U
-#define DMA_HISR_TEIF4                       0x00000008U
-#define DMA_HISR_DMEIF4                      0x00000004U
-#define DMA_HISR_FEIF4                       0x00000001U
-
-/********************  Bits definition for DMA_LIFCR register  ****************/
-#define DMA_LIFCR_CTCIF3                     0x08000000U
-#define DMA_LIFCR_CHTIF3                     0x04000000U
-#define DMA_LIFCR_CTEIF3                     0x02000000U
-#define DMA_LIFCR_CDMEIF3                    0x01000000U
-#define DMA_LIFCR_CFEIF3                     0x00400000U
-#define DMA_LIFCR_CTCIF2                     0x00200000U
-#define DMA_LIFCR_CHTIF2                     0x00100000U
-#define DMA_LIFCR_CTEIF2                     0x00080000U
-#define DMA_LIFCR_CDMEIF2                    0x00040000U
-#define DMA_LIFCR_CFEIF2                     0x00010000U
-#define DMA_LIFCR_CTCIF1                     0x00000800U
-#define DMA_LIFCR_CHTIF1                     0x00000400U
-#define DMA_LIFCR_CTEIF1                     0x00000200U
-#define DMA_LIFCR_CDMEIF1                    0x00000100U
-#define DMA_LIFCR_CFEIF1                     0x00000040U
-#define DMA_LIFCR_CTCIF0                     0x00000020U
-#define DMA_LIFCR_CHTIF0                     0x00000010U
-#define DMA_LIFCR_CTEIF0                     0x00000008U
-#define DMA_LIFCR_CDMEIF0                    0x00000004U
-#define DMA_LIFCR_CFEIF0                     0x00000001U
-
-/********************  Bits definition for DMA_HIFCR  register  ****************/
-#define DMA_HIFCR_CTCIF7                     0x08000000U
-#define DMA_HIFCR_CHTIF7                     0x04000000U
-#define DMA_HIFCR_CTEIF7                     0x02000000U
-#define DMA_HIFCR_CDMEIF7                    0x01000000U
-#define DMA_HIFCR_CFEIF7                     0x00400000U
-#define DMA_HIFCR_CTCIF6                     0x00200000U
-#define DMA_HIFCR_CHTIF6                     0x00100000U
-#define DMA_HIFCR_CTEIF6                     0x00080000U
-#define DMA_HIFCR_CDMEIF6                    0x00040000U
-#define DMA_HIFCR_CFEIF6                     0x00010000U
-#define DMA_HIFCR_CTCIF5                     0x00000800U
-#define DMA_HIFCR_CHTIF5                     0x00000400U
-#define DMA_HIFCR_CTEIF5                     0x00000200U
-#define DMA_HIFCR_CDMEIF5                    0x00000100U
-#define DMA_HIFCR_CFEIF5                     0x00000040U
-#define DMA_HIFCR_CTCIF4                     0x00000020U
-#define DMA_HIFCR_CHTIF4                     0x00000010U
-#define DMA_HIFCR_CTEIF4                     0x00000008U
-#define DMA_HIFCR_CDMEIF4                    0x00000004U
-#define DMA_HIFCR_CFEIF4                     0x00000001U
-
-/******************************************************************************/
-/*                                                                            */
-/*                         AHB Master DMA2D Controller (DMA2D)                */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for DMA2D_CR register  ******************/
-
-#define DMA2D_CR_START                     0x00000001U               /*!< Start transfer                          */
-#define DMA2D_CR_SUSP                      0x00000002U               /*!< Suspend transfer                        */
-#define DMA2D_CR_ABORT                     0x00000004U               /*!< Abort transfer                          */
-#define DMA2D_CR_TEIE                      0x00000100U               /*!< Transfer Error Interrupt Enable         */
-#define DMA2D_CR_TCIE                      0x00000200U               /*!< Transfer Complete Interrupt Enable      */
-#define DMA2D_CR_TWIE                      0x00000400U               /*!< Transfer Watermark Interrupt Enable     */
-#define DMA2D_CR_CAEIE                     0x00000800U               /*!< CLUT Access Error Interrupt Enable      */
-#define DMA2D_CR_CTCIE                     0x00001000U               /*!< CLUT Transfer Complete Interrupt Enable */
-#define DMA2D_CR_CEIE                      0x00002000U               /*!< Configuration Error Interrupt Enable    */
-#define DMA2D_CR_MODE                      0x00030000U               /*!< DMA2D Mode[1:0]                         */
-#define DMA2D_CR_MODE_0                    0x00010000U               /*!< DMA2D Mode bit 0                        */
-#define DMA2D_CR_MODE_1                    0x00020000U               /*!< DMA2D Mode bit 1                        */
-
-/********************  Bit definition for DMA2D_ISR register  *****************/
-
-#define DMA2D_ISR_TEIF                     0x00000001U               /*!< Transfer Error Interrupt Flag         */
-#define DMA2D_ISR_TCIF                     0x00000002U               /*!< Transfer Complete Interrupt Flag      */
-#define DMA2D_ISR_TWIF                     0x00000004U               /*!< Transfer Watermark Interrupt Flag     */
-#define DMA2D_ISR_CAEIF                    0x00000008U               /*!< CLUT Access Error Interrupt Flag      */
-#define DMA2D_ISR_CTCIF                    0x00000010U               /*!< CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_ISR_CEIF                     0x00000020U               /*!< Configuration Error Interrupt Flag    */
-
-/********************  Bit definition for DMA2D_IFCR register  ****************/
-
-#define DMA2D_IFCR_CTEIF                   0x00000001U               /*!< Clears Transfer Error Interrupt Flag         */
-#define DMA2D_IFCR_CTCIF                   0x00000002U               /*!< Clears Transfer Complete Interrupt Flag      */
-#define DMA2D_IFCR_CTWIF                   0x00000004U               /*!< Clears Transfer Watermark Interrupt Flag     */
-#define DMA2D_IFCR_CAECIF                  0x00000008U               /*!< Clears CLUT Access Error Interrupt Flag      */
-#define DMA2D_IFCR_CCTCIF                  0x00000010U               /*!< Clears CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_IFCR_CCEIF                   0x00000020U               /*!< Clears Configuration Error Interrupt Flag    */
-
-/* Legacy defines */
-#define DMA2D_IFSR_CTEIF                   DMA2D_IFCR_CTEIF                     /*!< Clears Transfer Error Interrupt Flag         */
-#define DMA2D_IFSR_CTCIF                   DMA2D_IFCR_CTCIF                     /*!< Clears Transfer Complete Interrupt Flag      */
-#define DMA2D_IFSR_CTWIF                   DMA2D_IFCR_CTWIF                     /*!< Clears Transfer Watermark Interrupt Flag     */
-#define DMA2D_IFSR_CCAEIF                  DMA2D_IFCR_CAECIF                    /*!< Clears CLUT Access Error Interrupt Flag      */
-#define DMA2D_IFSR_CCTCIF                  DMA2D_IFCR_CCTCIF                    /*!< Clears CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_IFSR_CCEIF                   DMA2D_IFCR_CCEIF                     /*!< Clears Configuration Error Interrupt Flag    */
-
-/********************  Bit definition for DMA2D_FGMAR register  ***************/
-
-#define DMA2D_FGMAR_MA                     0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_FGOR register  ****************/
-
-#define DMA2D_FGOR_LO                      0x00003FFFU               /*!< Line Offset */
-
-/********************  Bit definition for DMA2D_BGMAR register  ***************/
-
-#define DMA2D_BGMAR_MA                     0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_BGOR register  ****************/
-
-#define DMA2D_BGOR_LO                      0x00003FFFU               /*!< Line Offset */
-
-/********************  Bit definition for DMA2D_FGPFCCR register  *************/
-
-#define DMA2D_FGPFCCR_CM                   0x0000000FU               /*!< Input color mode CM[3:0] */
-#define DMA2D_FGPFCCR_CM_0                 0x00000001U               /*!< Input color mode CM bit 0 */
-#define DMA2D_FGPFCCR_CM_1                 0x00000002U               /*!< Input color mode CM bit 1 */
-#define DMA2D_FGPFCCR_CM_2                 0x00000004U               /*!< Input color mode CM bit 2 */
-#define DMA2D_FGPFCCR_CM_3                 0x00000008U               /*!< Input color mode CM bit 3 */
-#define DMA2D_FGPFCCR_CCM                  0x00000010U               /*!< CLUT Color mode */
-#define DMA2D_FGPFCCR_START                0x00000020U               /*!< Start */
-#define DMA2D_FGPFCCR_CS                   0x0000FF00U               /*!< CLUT size */
-#define DMA2D_FGPFCCR_AM                   0x00030000U               /*!< Alpha mode AM[1:0] */
-#define DMA2D_FGPFCCR_AM_0                 0x00010000U               /*!< Alpha mode AM bit 0 */
-#define DMA2D_FGPFCCR_AM_1                 0x00020000U               /*!< Alpha mode AM bit 1 */
-#define DMA2D_FGPFCCR_ALPHA                0xFF000000U               /*!< Alpha value */
-
-/********************  Bit definition for DMA2D_FGCOLR register  **************/
-
-#define DMA2D_FGCOLR_BLUE                  0x000000FFU               /*!< Blue Value */
-#define DMA2D_FGCOLR_GREEN                 0x0000FF00U               /*!< Green Value */
-#define DMA2D_FGCOLR_RED                   0x00FF0000U               /*!< Red Value */
-
-/********************  Bit definition for DMA2D_BGPFCCR register  *************/
-
-#define DMA2D_BGPFCCR_CM                   0x0000000FU               /*!< Input color mode CM[3:0] */
-#define DMA2D_BGPFCCR_CM_0                 0x00000001U               /*!< Input color mode CM bit 0 */
-#define DMA2D_BGPFCCR_CM_1                 0x00000002U               /*!< Input color mode CM bit 1 */
-#define DMA2D_BGPFCCR_CM_2                 0x00000004U               /*!< Input color mode CM bit 2 */
-#define DMA2D_FGPFCCR_CM_3                 0x00000008U               /*!< Input color mode CM bit 3 */
-#define DMA2D_BGPFCCR_CCM                  0x00000010U               /*!< CLUT Color mode */
-#define DMA2D_BGPFCCR_START                0x00000020U               /*!< Start */
-#define DMA2D_BGPFCCR_CS                   0x0000FF00U               /*!< CLUT size */
-#define DMA2D_BGPFCCR_AM                   0x00030000U               /*!< Alpha mode AM[1:0] */
-#define DMA2D_BGPFCCR_AM_0                 0x00010000U               /*!< Alpha mode AM bit 0 */
-#define DMA2D_BGPFCCR_AM_1                 0x00020000U               /*!< Alpha mode AM bit 1 */
-#define DMA2D_BGPFCCR_ALPHA                0xFF000000U               /*!< background Input Alpha value */
-
-/********************  Bit definition for DMA2D_BGCOLR register  **************/
-
-#define DMA2D_BGCOLR_BLUE                  0x000000FFU               /*!< Blue Value */
-#define DMA2D_BGCOLR_GREEN                 0x0000FF00U               /*!< Green Value */
-#define DMA2D_BGCOLR_RED                   0x00FF0000U               /*!< Red Value */
-
-/********************  Bit definition for DMA2D_FGCMAR register  **************/
-
-#define DMA2D_FGCMAR_MA                    0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_BGCMAR register  **************/
-
-#define DMA2D_BGCMAR_MA                    0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_OPFCCR register  **************/
-
-#define DMA2D_OPFCCR_CM                    0x00000007U               /*!< Color mode CM[2:0] */
-#define DMA2D_OPFCCR_CM_0                  0x00000001U               /*!< Color mode CM bit 0 */
-#define DMA2D_OPFCCR_CM_1                  0x00000002U               /*!< Color mode CM bit 1 */
-#define DMA2D_OPFCCR_CM_2                  0x00000004U               /*!< Color mode CM bit 2 */
-
-/********************  Bit definition for DMA2D_OCOLR register  ***************/
-
-/*!<Mode_ARGB8888/RGB888 */
-
-#define DMA2D_OCOLR_BLUE_1                 0x000000FFU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_1                0x0000FF00U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_1                  0x00FF0000U               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_1                0xFF000000U               /*!< Alpha Channel Value */
-
-/*!<Mode_RGB565 */
-#define DMA2D_OCOLR_BLUE_2                 0x0000001FU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_2                0x000007E0U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_2                  0x0000F800U               /*!< Red Value */
-
-/*!<Mode_ARGB1555 */
-#define DMA2D_OCOLR_BLUE_3                 0x0000001FU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_3                0x000003E0U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_3                  0x00007C00U               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_3                0x00008000U               /*!< Alpha Channel Value */
-
-/*!<Mode_ARGB4444 */
-#define DMA2D_OCOLR_BLUE_4                 0x0000000FU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_4                0x000000F0U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_4                  0x00000F00U               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_4                0x0000F000U               /*!< Alpha Channel Value */
-
-/********************  Bit definition for DMA2D_OMAR register  ****************/
-
-#define DMA2D_OMAR_MA                      0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_OOR register  *****************/
-
-#define DMA2D_OOR_LO                       0x00003FFFU               /*!< Line Offset */
-
-/********************  Bit definition for DMA2D_NLR register  *****************/
-
-#define DMA2D_NLR_NL                       0x0000FFFFU               /*!< Number of Lines */
-#define DMA2D_NLR_PL                       0x3FFF0000U               /*!< Pixel per Lines */
-
-/********************  Bit definition for DMA2D_LWR register  *****************/
-
-#define DMA2D_LWR_LW                       0x0000FFFFU               /*!< Line Watermark */
-
-/********************  Bit definition for DMA2D_AMTCR register  ***************/
-
-#define DMA2D_AMTCR_EN                     0x00000001U               /*!< Enable */
-#define DMA2D_AMTCR_DT                     0x0000FF00U               /*!< Dead Time */
-
-
-/********************  Bit definition for DMA2D_FGCLUT register  **************/
-
-/********************  Bit definition for DMA2D_BGCLUT register  **************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                    External Interrupt/Event Controller                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
-#define  EXTI_IMR_MR23                       0x00800000U        /*!< Interrupt Mask on line 23 */
-
-/* Reference Defines */
-#define  EXTI_IMR_IM0                        EXTI_IMR_MR0
-#define  EXTI_IMR_IM1                        EXTI_IMR_MR1
-#define  EXTI_IMR_IM2                        EXTI_IMR_MR2
-#define  EXTI_IMR_IM3                        EXTI_IMR_MR3
-#define  EXTI_IMR_IM4                        EXTI_IMR_MR4
-#define  EXTI_IMR_IM5                        EXTI_IMR_MR5
-#define  EXTI_IMR_IM6                        EXTI_IMR_MR6
-#define  EXTI_IMR_IM7                        EXTI_IMR_MR7
-#define  EXTI_IMR_IM8                        EXTI_IMR_MR8
-#define  EXTI_IMR_IM9                        EXTI_IMR_MR9
-#define  EXTI_IMR_IM10                       EXTI_IMR_MR10
-#define  EXTI_IMR_IM11                       EXTI_IMR_MR11
-#define  EXTI_IMR_IM12                       EXTI_IMR_MR12
-#define  EXTI_IMR_IM13                       EXTI_IMR_MR13
-#define  EXTI_IMR_IM14                       EXTI_IMR_MR14
-#define  EXTI_IMR_IM15                       EXTI_IMR_MR15
-#define  EXTI_IMR_IM16                       EXTI_IMR_MR16
-#define  EXTI_IMR_IM17                       EXTI_IMR_MR17
-#define  EXTI_IMR_IM18                       EXTI_IMR_MR18
-#define  EXTI_IMR_IM19                       EXTI_IMR_MR19
-#define  EXTI_IMR_IM20                       EXTI_IMR_MR20
-#define  EXTI_IMR_IM21                       EXTI_IMR_MR21
-#define  EXTI_IMR_IM22                       EXTI_IMR_MR22
-#define  EXTI_IMR_IM23                       EXTI_IMR_MR23
-
-#define  EXTI_IMR_IM                         0x00FFFFFFU        /*!< Interrupt Mask All */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
-#define  EXTI_EMR_MR23                       0x00800000U        /*!< Event Mask on line 23 */
-
-/* Reference Defines */
-#define  EXTI_EMR_EM0                        EXTI_EMR_MR0
-#define  EXTI_EMR_EM1                        EXTI_EMR_MR1
-#define  EXTI_EMR_EM2                        EXTI_EMR_MR2
-#define  EXTI_EMR_EM3                        EXTI_EMR_MR3
-#define  EXTI_EMR_EM4                        EXTI_EMR_MR4
-#define  EXTI_EMR_EM5                        EXTI_EMR_MR5
-#define  EXTI_EMR_EM6                        EXTI_EMR_MR6
-#define  EXTI_EMR_EM7                        EXTI_EMR_MR7
-#define  EXTI_EMR_EM8                        EXTI_EMR_MR8
-#define  EXTI_EMR_EM9                        EXTI_EMR_MR9
-#define  EXTI_EMR_EM10                       EXTI_EMR_MR10
-#define  EXTI_EMR_EM11                       EXTI_EMR_MR11
-#define  EXTI_EMR_EM12                       EXTI_EMR_MR12
-#define  EXTI_EMR_EM13                       EXTI_EMR_MR13
-#define  EXTI_EMR_EM14                       EXTI_EMR_MR14
-#define  EXTI_EMR_EM15                       EXTI_EMR_MR15
-#define  EXTI_EMR_EM16                       EXTI_EMR_MR16
-#define  EXTI_EMR_EM17                       EXTI_EMR_MR17
-#define  EXTI_EMR_EM18                       EXTI_EMR_MR18
-#define  EXTI_EMR_EM19                       EXTI_EMR_MR19
-#define  EXTI_EMR_EM20                       EXTI_EMR_MR20
-#define  EXTI_EMR_EM21                       EXTI_EMR_MR21
-#define  EXTI_EMR_EM22                       EXTI_EMR_MR22
-#define  EXTI_EMR_EM23                       EXTI_EMR_MR23
-
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
-#define  EXTI_RTSR_TR23                      0x00800000U        /*!< Rising trigger event configuration bit of line 23 */
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
-#define  EXTI_FTSR_TR23                      0x00800000U        /*!< Falling trigger event configuration bit of line 23 */
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
-#define  EXTI_SWIER_SWIER23                  0x00800000U        /*!< Software Interrupt on line 23 */
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
-#define  EXTI_PR_PR23                        0x00800000U        /*!< Pending bit for line 23 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    FLASH                                   */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief FLASH Total Sectors Number
-*/
-#define FLASH_SECTOR_TOTAL  8
-
-/*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    0x0000000FU
-#define FLASH_ACR_LATENCY_0WS                0x00000000U
-#define FLASH_ACR_LATENCY_1WS                0x00000001U
-#define FLASH_ACR_LATENCY_2WS                0x00000002U
-#define FLASH_ACR_LATENCY_3WS                0x00000003U
-#define FLASH_ACR_LATENCY_4WS                0x00000004U
-#define FLASH_ACR_LATENCY_5WS                0x00000005U
-#define FLASH_ACR_LATENCY_6WS                0x00000006U
-#define FLASH_ACR_LATENCY_7WS                0x00000007U
-#define FLASH_ACR_LATENCY_8WS                0x00000008U
-#define FLASH_ACR_LATENCY_9WS                0x00000009U
-#define FLASH_ACR_LATENCY_10WS               0x0000000AU
-#define FLASH_ACR_LATENCY_11WS               0x0000000BU
-#define FLASH_ACR_LATENCY_12WS               0x0000000CU
-#define FLASH_ACR_LATENCY_13WS               0x0000000DU
-#define FLASH_ACR_LATENCY_14WS               0x0000000EU
-#define FLASH_ACR_LATENCY_15WS               0x0000000FU
-#define FLASH_ACR_PRFTEN                     0x00000100U
-#define FLASH_ACR_ARTEN                      0x00000200U
-#define FLASH_ACR_ARTRST                     0x00000800U
-
-/*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         0x00000001U
-#define FLASH_SR_OPERR                       0x00000002U
-#define FLASH_SR_WRPERR                      0x00000010U
-#define FLASH_SR_PGAERR                      0x00000020U
-#define FLASH_SR_PGPERR                      0x00000040U
-#define FLASH_SR_ERSERR                      0x00000080U
-#define FLASH_SR_BSY                         0x00010000U
-
-/*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          0x00000001U
-#define FLASH_CR_SER                         0x00000002U
-#define FLASH_CR_MER                         0x00000004U
-#define FLASH_CR_SNB                         0x00000078U
-#define FLASH_CR_SNB_0                       0x00000008U
-#define FLASH_CR_SNB_1                       0x00000010U
-#define FLASH_CR_SNB_2                       0x00000020U
-#define FLASH_CR_SNB_3                       0x00000040U
-#define FLASH_CR_PSIZE                       0x00000300U
-#define FLASH_CR_PSIZE_0                     0x00000100U
-#define FLASH_CR_PSIZE_1                     0x00000200U
-#define FLASH_CR_STRT                        0x00010000U
-#define FLASH_CR_EOPIE                       0x01000000U
-#define FLASH_CR_ERRIE                       0x02000000U
-#define FLASH_CR_LOCK                        0x80000000U
-
-/*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                 0x00000001U
-#define FLASH_OPTCR_OPTSTRT                 0x00000002U
-#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
-#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
-#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
-#define FLASH_OPTCR_WWDG_SW                 0x00000010U
-#define FLASH_OPTCR_IWDG_SW                 0x00000020U
-#define FLASH_OPTCR_nRST_STOP               0x00000040U
-#define FLASH_OPTCR_nRST_STDBY              0x00000080U
-#define FLASH_OPTCR_RDP                     0x0000FF00U
-#define FLASH_OPTCR_RDP_0                   0x00000100U
-#define FLASH_OPTCR_RDP_1                   0x00000200U
-#define FLASH_OPTCR_RDP_2                   0x00000400U
-#define FLASH_OPTCR_RDP_3                   0x00000800U
-#define FLASH_OPTCR_RDP_4                   0x00001000U
-#define FLASH_OPTCR_RDP_5                   0x00002000U
-#define FLASH_OPTCR_RDP_6                   0x00004000U
-#define FLASH_OPTCR_RDP_7                   0x00008000U
-#define FLASH_OPTCR_nWRP                    0x00FF0000U
-#define FLASH_OPTCR_nWRP_0                  0x00010000U
-#define FLASH_OPTCR_nWRP_1                  0x00020000U
-#define FLASH_OPTCR_nWRP_2                  0x00040000U
-#define FLASH_OPTCR_nWRP_3                  0x00080000U
-#define FLASH_OPTCR_nWRP_4                  0x00100000U
-#define FLASH_OPTCR_nWRP_5                  0x00200000U
-#define FLASH_OPTCR_nWRP_6                  0x00400000U
-#define FLASH_OPTCR_nWRP_7                  0x00800000U
-#define FLASH_OPTCR_IWDG_STDBY              0x40000000U
-#define FLASH_OPTCR_IWDG_STOP               0x80000000U
-
-/*******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_BOOT_ADD0              0x0000FFFFU
-#define FLASH_OPTCR1_BOOT_ADD1              0xFFFF0000U
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Flexible Memory Controller                        */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for FMC_BCR1 register  *******************/
-#define  FMC_BCR1_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR1_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-#define  FMC_BCR1_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR1_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR1_MTYP_1                    0x00000008U        /*!<Bit 1 */
-#define  FMC_BCR1_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR1_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR1_MWID_1                    0x00000020U        /*!<Bit 1 */
-#define  FMC_BCR1_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR1_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR1_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR1_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
-#define  FMC_BCR1_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR1_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR1_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR1_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR1_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR1_CPSIZE                    0x00070000U        /*!<CRAM page size             */
-#define  FMC_BCR1_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FMC_BCR1_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FMC_BCR1_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FMC_BCR1_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-#define  FMC_BCR1_CCLKEN                    0x00100000U        /*!<Continous clock enable     */
-#define  FMC_BCR1_WFDIS                     0x00200000U        /*!<Write FIFO Disable         */
-
-/******************  Bit definition for FMC_BCR2 register  *******************/
-#define  FMC_BCR2_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR2_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-#define  FMC_BCR2_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR2_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR2_MTYP_1                    0x00000008U        /*!<Bit 1 */
-#define  FMC_BCR2_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR2_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR2_MWID_1                    0x00000020U        /*!<Bit 1 */
-#define  FMC_BCR2_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR2_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR2_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR2_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
-#define  FMC_BCR2_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR2_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR2_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR2_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR2_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR2_CPSIZE                    0x00070000U        /*!<CRAM page size             */
-#define  FMC_BCR2_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FMC_BCR2_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FMC_BCR2_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FMC_BCR2_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FMC_BCR3 register  *******************/
-#define  FMC_BCR3_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR3_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-#define  FMC_BCR3_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR3_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR3_MTYP_1                    0x00000008U        /*!<Bit 1 */
-#define  FMC_BCR3_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR3_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR3_MWID_1                    0x00000020U        /*!<Bit 1 */
-#define  FMC_BCR3_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR3_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR3_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR3_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
-#define  FMC_BCR3_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR3_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR3_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR3_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR3_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR3_CPSIZE                    0x00070000U        /*!<CRAM page size             */
-#define  FMC_BCR3_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FMC_BCR3_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FMC_BCR3_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FMC_BCR3_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FMC_BCR4 register  *******************/
-#define  FMC_BCR4_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR4_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-#define  FMC_BCR4_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR4_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR4_MTYP_1                    0x00000008U        /*!<Bit 1 */
-#define  FMC_BCR4_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR4_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR4_MWID_1                    0x00000020U        /*!<Bit 1 */
-#define  FMC_BCR4_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR4_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR4_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR4_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
-#define  FMC_BCR4_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR4_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR4_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR4_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR4_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR4_CPSIZE                    0x00070000U        /*!<CRAM page size             */
-#define  FMC_BCR4_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FMC_BCR4_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FMC_BCR4_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FMC_BCR4_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FMC_BTR1 register  ******************/
-#define  FMC_BTR1_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR1_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR1_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR1_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR1_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-#define  FMC_BTR1_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
-#define  FMC_BTR1_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR1_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR1_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR1_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-#define  FMC_BTR1_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR1_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR1_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR1_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR1_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR1_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR1_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR1_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR1_DATAST_7                  0x00008000U        /*!<Bit 7 */
-#define  FMC_BTR1_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR1_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR1_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR1_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR1_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-#define  FMC_BTR1_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR1_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR1_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR1_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR1_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-#define  FMC_BTR1_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR1_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR1_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR1_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR1_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-#define  FMC_BTR1_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR1_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR1_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BTR2 register  *******************/
-#define  FMC_BTR2_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR2_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR2_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR2_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR2_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-#define  FMC_BTR2_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR2_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR2_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR2_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR2_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-#define  FMC_BTR2_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR2_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR2_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR2_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR2_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR2_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR2_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR2_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR2_DATAST_7                  0x00008000U        /*!<Bit 7 */
-#define  FMC_BTR2_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR2_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR2_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR2_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR2_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-#define  FMC_BTR2_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR2_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR2_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR2_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR2_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-#define  FMC_BTR2_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR2_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR2_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR2_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR2_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-#define  FMC_BTR2_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR2_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR2_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/*******************  Bit definition for FMC_BTR3 register  *******************/
-#define  FMC_BTR3_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR3_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR3_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR3_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR3_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-#define  FMC_BTR3_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR3_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR3_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR3_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR3_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-#define  FMC_BTR3_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR3_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR3_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR3_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR3_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR3_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR3_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR3_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR3_DATAST_7                  0x00008000U        /*!<Bit 7 */
-#define  FMC_BTR3_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR3_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR3_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR3_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR3_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-#define  FMC_BTR3_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR3_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR3_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR3_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR3_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-#define  FMC_BTR3_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR3_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR3_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR3_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR3_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-#define  FMC_BTR3_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR3_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR3_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BTR4 register  *******************/
-#define  FMC_BTR4_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR4_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR4_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR4_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR4_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-#define  FMC_BTR4_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR4_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR4_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR4_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR4_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-#define  FMC_BTR4_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR4_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR4_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR4_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR4_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR4_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR4_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR4_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR4_DATAST_7                  0x00008000U        /*!<Bit 7 */
-#define  FMC_BTR4_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR4_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR4_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR4_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR4_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-#define  FMC_BTR4_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR4_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR4_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR4_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR4_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-#define  FMC_BTR4_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR4_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR4_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR4_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR4_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-#define  FMC_BTR4_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR4_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR4_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR1 register  ******************/
-#define  FMC_BWTR1_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR1_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR1_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR1_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR1_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-#define  FMC_BWTR1_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR1_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR1_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR1_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR1_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-#define  FMC_BWTR1_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR1_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR1_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR1_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR1_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR1_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR1_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR1_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR1_DATAST_7                 0x00008000U        /*!<Bit 7 */
-#define  FMC_BWTR1_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BWTR1_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR1_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR1_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR1_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-#define  FMC_BWTR1_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR1_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR1_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR2 register  ******************/
-#define  FMC_BWTR2_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR2_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR2_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR2_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR2_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-#define  FMC_BWTR2_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR2_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR2_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR2_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR2_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-#define  FMC_BWTR2_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR2_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR2_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR2_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR2_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR2_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR2_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR2_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR2_DATAST_7                 0x00008000U        /*!<Bit 7 */
-#define  FMC_BWTR2_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BWTR2_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR2_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR2_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR2_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-#define  FMC_BWTR2_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR2_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR2_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR3 register  ******************/
-#define  FMC_BWTR3_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR3_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR3_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR3_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR3_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-#define  FMC_BWTR3_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR3_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR3_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR3_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR3_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-#define  FMC_BWTR3_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR3_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR3_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR3_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR3_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR3_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR3_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR3_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR3_DATAST_7                 0x00008000U        /*!<Bit 7 */
-#define  FMC_BWTR3_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BWTR3_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR3_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR3_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR3_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-#define  FMC_BWTR3_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR3_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR3_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR4 register  ******************/
-#define  FMC_BWTR4_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR4_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR4_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR4_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR4_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-#define  FMC_BWTR4_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR4_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR4_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR4_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR4_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-#define  FMC_BWTR4_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR4_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR4_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR4_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR4_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR4_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR4_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR4_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR4_DATAST_7                 0x00008000U        /*!<Bit 7 */
-#define  FMC_BWTR4_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BWTR4_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR4_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR4_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR4_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-#define  FMC_BWTR4_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR4_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR4_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_PCR register  *******************/
-#define  FMC_PCR_PWAITEN                   0x00000002U        /*!<Wait feature enable bit                   */
-#define  FMC_PCR_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FMC_PCR_PTYP                      0x00000008U        /*!<Memory type                               */
-#define  FMC_PCR_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FMC_PCR_PWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_PCR_PWID_1                    0x00000020U        /*!<Bit 1 */
-#define  FMC_PCR_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit          */
-#define  FMC_PCR_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay)          */
-#define  FMC_PCR_TCLR_0                    0x00000200U        /*!<Bit 0 */
-#define  FMC_PCR_TCLR_1                    0x00000400U        /*!<Bit 1 */
-#define  FMC_PCR_TCLR_2                    0x00000800U        /*!<Bit 2 */
-#define  FMC_PCR_TCLR_3                    0x00001000U        /*!<Bit 3 */
-#define  FMC_PCR_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay)           */
-#define  FMC_PCR_TAR_0                     0x00002000U        /*!<Bit 0 */
-#define  FMC_PCR_TAR_1                     0x00004000U        /*!<Bit 1 */
-#define  FMC_PCR_TAR_2                     0x00008000U        /*!<Bit 2 */
-#define  FMC_PCR_TAR_3                     0x00010000U        /*!<Bit 3 */
-#define  FMC_PCR_ECCPS                     0x000E0000U        /*!<ECCPS[2:0] bits (ECC page size)           */
-#define  FMC_PCR_ECCPS_0                   0x00020000U        /*!<Bit 0 */
-#define  FMC_PCR_ECCPS_1                   0x00040000U        /*!<Bit 1 */
-#define  FMC_PCR_ECCPS_2                   0x00080000U        /*!<Bit 2 */
-
-/*******************  Bit definition for FMC_SR register  *******************/
-#define  FMC_SR_IRS                        0x01U              /*!<Interrupt Rising Edge status                */
-#define  FMC_SR_ILS                        0x02U              /*!<Interrupt Level status                      */
-#define  FMC_SR_IFS                        0x04U              /*!<Interrupt Falling Edge status               */
-#define  FMC_SR_IREN                       0x08U              /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FMC_SR_ILEN                       0x10U              /*!<Interrupt Level detection Enable bit        */
-#define  FMC_SR_IFEN                       0x20U              /*!<Interrupt Falling Edge detection Enable bit */
-#define  FMC_SR_FEMPT                      0x40U              /*!<FIFO empty                                  */
-
-/******************  Bit definition for FMC_PMEM register  ******************/
-#define  FMC_PMEM_MEMSET3                  0x000000FFU        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
-#define  FMC_PMEM_MEMSET3_0                0x00000001U        /*!<Bit 0 */
-#define  FMC_PMEM_MEMSET3_1                0x00000002U        /*!<Bit 1 */
-#define  FMC_PMEM_MEMSET3_2                0x00000004U        /*!<Bit 2 */
-#define  FMC_PMEM_MEMSET3_3                0x00000008U        /*!<Bit 3 */
-#define  FMC_PMEM_MEMSET3_4                0x00000010U        /*!<Bit 4 */
-#define  FMC_PMEM_MEMSET3_5                0x00000020U        /*!<Bit 5 */
-#define  FMC_PMEM_MEMSET3_6                0x00000040U        /*!<Bit 6 */
-#define  FMC_PMEM_MEMSET3_7                0x00000080U        /*!<Bit 7 */
-#define  FMC_PMEM_MEMWAIT3                 0x0000FF00U        /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
-#define  FMC_PMEM_MEMWAIT3_0               0x00000100U        /*!<Bit 0 */
-#define  FMC_PMEM_MEMWAIT3_1               0x00000200U        /*!<Bit 1 */
-#define  FMC_PMEM_MEMWAIT3_2               0x00000400U        /*!<Bit 2 */
-#define  FMC_PMEM_MEMWAIT3_3               0x00000800U        /*!<Bit 3 */
-#define  FMC_PMEM_MEMWAIT3_4               0x00001000U        /*!<Bit 4 */
-#define  FMC_PMEM_MEMWAIT3_5               0x00002000U        /*!<Bit 5 */
-#define  FMC_PMEM_MEMWAIT3_6               0x00004000U        /*!<Bit 6 */
-#define  FMC_PMEM_MEMWAIT3_7               0x00008000U        /*!<Bit 7 */
-#define  FMC_PMEM_MEMHOLD3                 0x00FF0000U        /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
-#define  FMC_PMEM_MEMHOLD3_0               0x00010000U        /*!<Bit 0 */
-#define  FMC_PMEM_MEMHOLD3_1               0x00020000U        /*!<Bit 1 */
-#define  FMC_PMEM_MEMHOLD3_2               0x00040000U        /*!<Bit 2 */
-#define  FMC_PMEM_MEMHOLD3_3               0x00080000U        /*!<Bit 3 */
-#define  FMC_PMEM_MEMHOLD3_4               0x00100000U        /*!<Bit 4 */
-#define  FMC_PMEM_MEMHOLD3_5               0x00200000U        /*!<Bit 5 */
-#define  FMC_PMEM_MEMHOLD3_6               0x00400000U        /*!<Bit 6 */
-#define  FMC_PMEM_MEMHOLD3_7               0x00800000U        /*!<Bit 7 */
-#define  FMC_PMEM_MEMHIZ3                  0xFF000000U        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
-#define  FMC_PMEM_MEMHIZ3_0                0x01000000U        /*!<Bit 0 */
-#define  FMC_PMEM_MEMHIZ3_1                0x02000000U        /*!<Bit 1 */
-#define  FMC_PMEM_MEMHIZ3_2                0x04000000U        /*!<Bit 2 */
-#define  FMC_PMEM_MEMHIZ3_3                0x08000000U        /*!<Bit 3 */
-#define  FMC_PMEM_MEMHIZ3_4                0x10000000U        /*!<Bit 4 */
-#define  FMC_PMEM_MEMHIZ3_5                0x20000000U        /*!<Bit 5 */
-#define  FMC_PMEM_MEMHIZ3_6                0x40000000U        /*!<Bit 6 */
-#define  FMC_PMEM_MEMHIZ3_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_PATT register  ******************/
-#define  FMC_PATT_ATTSET3                  0x000000FFU        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
-#define  FMC_PATT_ATTSET3_0                0x00000001U        /*!<Bit 0 */
-#define  FMC_PATT_ATTSET3_1                0x00000002U        /*!<Bit 1 */
-#define  FMC_PATT_ATTSET3_2                0x00000004U        /*!<Bit 2 */
-#define  FMC_PATT_ATTSET3_3                0x00000008U        /*!<Bit 3 */
-#define  FMC_PATT_ATTSET3_4                0x00000010U        /*!<Bit 4 */
-#define  FMC_PATT_ATTSET3_5                0x00000020U        /*!<Bit 5 */
-#define  FMC_PATT_ATTSET3_6                0x00000040U        /*!<Bit 6 */
-#define  FMC_PATT_ATTSET3_7                0x00000080U        /*!<Bit 7 */
-#define  FMC_PATT_ATTWAIT3                 0x0000FF00U        /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
-#define  FMC_PATT_ATTWAIT3_0               0x00000100U        /*!<Bit 0 */
-#define  FMC_PATT_ATTWAIT3_1               0x00000200U        /*!<Bit 1 */
-#define  FMC_PATT_ATTWAIT3_2               0x00000400U        /*!<Bit 2 */
-#define  FMC_PATT_ATTWAIT3_3               0x00000800U        /*!<Bit 3 */
-#define  FMC_PATT_ATTWAIT3_4               0x00001000U        /*!<Bit 4 */
-#define  FMC_PATT_ATTWAIT3_5               0x00002000U        /*!<Bit 5 */
-#define  FMC_PATT_ATTWAIT3_6               0x00004000U        /*!<Bit 6 */
-#define  FMC_PATT_ATTWAIT3_7               0x00008000U        /*!<Bit 7 */
-#define  FMC_PATT_ATTHOLD3                 0x00FF0000U        /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
-#define  FMC_PATT_ATTHOLD3_0               0x00010000U        /*!<Bit 0 */
-#define  FMC_PATT_ATTHOLD3_1               0x00020000U        /*!<Bit 1 */
-#define  FMC_PATT_ATTHOLD3_2               0x00040000U        /*!<Bit 2 */
-#define  FMC_PATT_ATTHOLD3_3               0x00080000U        /*!<Bit 3 */
-#define  FMC_PATT_ATTHOLD3_4               0x00100000U        /*!<Bit 4 */
-#define  FMC_PATT_ATTHOLD3_5               0x00200000U        /*!<Bit 5 */
-#define  FMC_PATT_ATTHOLD3_6               0x00400000U        /*!<Bit 6 */
-#define  FMC_PATT_ATTHOLD3_7               0x00800000U        /*!<Bit 7 */
-#define  FMC_PATT_ATTHIZ3                  0xFF000000U        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
-#define  FMC_PATT_ATTHIZ3_0                0x01000000U        /*!<Bit 0 */
-#define  FMC_PATT_ATTHIZ3_1                0x02000000U        /*!<Bit 1 */
-#define  FMC_PATT_ATTHIZ3_2                0x04000000U        /*!<Bit 2 */
-#define  FMC_PATT_ATTHIZ3_3                0x08000000U        /*!<Bit 3 */
-#define  FMC_PATT_ATTHIZ3_4                0x10000000U        /*!<Bit 4 */
-#define  FMC_PATT_ATTHIZ3_5                0x20000000U        /*!<Bit 5 */
-#define  FMC_PATT_ATTHIZ3_6                0x40000000U        /*!<Bit 6 */
-#define  FMC_PATT_ATTHIZ3_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_ECCR register  ******************/
-#define  FMC_ECCR_ECC3                     0xFFFFFFFFU        /*!<ECC result */
-
-/******************  Bit definition for FMC_SDCR1 register  ******************/
-#define  FMC_SDCR1_NC                       0x00000003U        /*!<NC[1:0] bits (Number of column bits) */
-#define  FMC_SDCR1_NC_0                     0x00000001U        /*!<Bit 0 */
-#define  FMC_SDCR1_NC_1                     0x00000002U        /*!<Bit 1 */
-#define  FMC_SDCR1_NR                       0x0000000CU        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR1_NR_0                     0x00000004U        /*!<Bit 0 */
-#define  FMC_SDCR1_NR_1                     0x00000008U        /*!<Bit 1 */
-#define  FMC_SDCR1_MWID                     0x00000030U        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR1_MWID_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDCR1_MWID_1                   0x00000020U        /*!<Bit 1 */
-#define  FMC_SDCR1_NB                       0x00000040U        /*!<Number of internal bank */
-#define  FMC_SDCR1_CAS                      0x00000180U        /*!<CAS[1:0] bits (CAS latency) */
-#define  FMC_SDCR1_CAS_0                    0x00000080U        /*!<Bit 0 */
-#define  FMC_SDCR1_CAS_1                    0x00000100U        /*!<Bit 1 */
-#define  FMC_SDCR1_WP                       0x00000200U        /*!<Write protection */
-#define  FMC_SDCR1_SDCLK                    0x00000C00U        /*!<SDRAM clock configuration */
-#define  FMC_SDCR1_SDCLK_0                  0x00000400U        /*!<Bit 0 */
-#define  FMC_SDCR1_SDCLK_1                  0x00000800U        /*!<Bit 1 */
-#define  FMC_SDCR1_RBURST                   0x00001000U        /*!<Read burst */
-#define  FMC_SDCR1_RPIPE                    0x00006000U        /*!<Write protection */
-#define  FMC_SDCR1_RPIPE_0                  0x00002000U        /*!<Bit 0 */
-#define  FMC_SDCR1_RPIPE_1                  0x00004000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_SDCR2 register  ******************/
-#define  FMC_SDCR2_NC                       0x00000003U        /*!<NC[1:0] bits (Number of column bits) */
-#define  FMC_SDCR2_NC_0                     0x00000001U        /*!<Bit 0 */
-#define  FMC_SDCR2_NC_1                     0x00000002U        /*!<Bit 1 */
-#define  FMC_SDCR2_NR                       0x0000000CU        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR2_NR_0                     0x00000004U        /*!<Bit 0 */
-#define  FMC_SDCR2_NR_1                     0x00000008U        /*!<Bit 1 */
-#define  FMC_SDCR2_MWID                     0x00000030U        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR2_MWID_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDCR2_MWID_1                   0x00000020U        /*!<Bit 1 */
-#define  FMC_SDCR2_NB                       0x00000040U        /*!<Number of internal bank */
-#define  FMC_SDCR2_CAS                      0x00000180U        /*!<CAS[1:0] bits (CAS latency) */
-#define  FMC_SDCR2_CAS_0                    0x00000080U        /*!<Bit 0 */
-#define  FMC_SDCR2_CAS_1                    0x00000100U        /*!<Bit 1 */
-#define  FMC_SDCR2_WP                       0x00000200U        /*!<Write protection */
-#define  FMC_SDCR2_SDCLK                    0x00000C00U        /*!<SDCLK[1:0] (SDRAM clock configuration) */
-#define  FMC_SDCR2_SDCLK_0                  0x00000400U        /*!<Bit 0 */
-#define  FMC_SDCR2_SDCLK_1                  0x00000800U        /*!<Bit 1 */
-#define  FMC_SDCR2_RBURST                   0x00001000U        /*!<Read burst */
-#define  FMC_SDCR2_RPIPE                    0x00006000U        /*!<RPIPE[1:0](Read pipe) */
-#define  FMC_SDCR2_RPIPE_0                  0x00002000U        /*!<Bit 0 */
-#define  FMC_SDCR2_RPIPE_1                  0x00004000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_SDTR1 register  ******************/
-#define  FMC_SDTR1_TMRD                     0x0000000FU        /*!<TMRD[3:0] bits (Load mode register to active) */
-#define  FMC_SDTR1_TMRD_0                   0x00000001U        /*!<Bit 0 */
-#define  FMC_SDTR1_TMRD_1                   0x00000002U        /*!<Bit 1 */
-#define  FMC_SDTR1_TMRD_2                   0x00000004U        /*!<Bit 2 */
-#define  FMC_SDTR1_TMRD_3                   0x00000008U        /*!<Bit 3 */
-#define  FMC_SDTR1_TXSR                     0x000000F0U        /*!<TXSR[3:0] bits (Exit self refresh) */
-#define  FMC_SDTR1_TXSR_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDTR1_TXSR_1                   0x00000020U        /*!<Bit 1 */
-#define  FMC_SDTR1_TXSR_2                   0x00000040U        /*!<Bit 2 */
-#define  FMC_SDTR1_TXSR_3                   0x00000080U        /*!<Bit 3 */
-#define  FMC_SDTR1_TRAS                     0x00000F00U        /*!<TRAS[3:0] bits (Self refresh time) */
-#define  FMC_SDTR1_TRAS_0                   0x00000100U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRAS_1                   0x00000200U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRAS_2                   0x00000400U        /*!<Bit 2 */
-#define  FMC_SDTR1_TRAS_3                   0x00000800U        /*!<Bit 3 */
-#define  FMC_SDTR1_TRC                      0x0000F000U        /*!<TRC[2:0] bits (Row cycle delay) */
-#define  FMC_SDTR1_TRC_0                    0x00001000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRC_1                    0x00002000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRC_2                    0x00004000U        /*!<Bit 2 */
-#define  FMC_SDTR1_TWR                      0x000F0000U        /*!<TRC[2:0] bits (Write recovery delay) */
-#define  FMC_SDTR1_TWR_0                    0x00010000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TWR_1                    0x00020000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TWR_2                    0x00040000U        /*!<Bit 2 */
-#define  FMC_SDTR1_TRP                      0x00F00000U        /*!<TRP[2:0] bits (Row precharge delay) */
-#define  FMC_SDTR1_TRP_0                    0x00100000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRP_1                    0x00200000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRP_2                    0x00400000U        /*!<Bit 2 */
-#define  FMC_SDTR1_TRCD                     0x0F000000U        /*!<TRP[2:0] bits (Row to column delay) */
-#define  FMC_SDTR1_TRCD_0                   0x01000000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRCD_1                   0x02000000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRCD_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for FMC_SDTR2 register  ******************/
-#define  FMC_SDTR2_TMRD                     0x0000000FU        /*!<TMRD[3:0] bits (Load mode register to active) */
-#define  FMC_SDTR2_TMRD_0                   0x00000001U        /*!<Bit 0 */
-#define  FMC_SDTR2_TMRD_1                   0x00000002U        /*!<Bit 1 */
-#define  FMC_SDTR2_TMRD_2                   0x00000004U        /*!<Bit 2 */
-#define  FMC_SDTR2_TMRD_3                   0x00000008U        /*!<Bit 3 */
-#define  FMC_SDTR2_TXSR                     0x000000F0U        /*!<TXSR[3:0] bits (Exit self refresh) */
-#define  FMC_SDTR2_TXSR_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDTR2_TXSR_1                   0x00000020U        /*!<Bit 1 */
-#define  FMC_SDTR2_TXSR_2                   0x00000040U        /*!<Bit 2 */
-#define  FMC_SDTR2_TXSR_3                   0x00000080U        /*!<Bit 3 */
-#define  FMC_SDTR2_TRAS                     0x00000F00U        /*!<TRAS[3:0] bits (Self refresh time) */
-#define  FMC_SDTR2_TRAS_0                   0x00000100U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRAS_1                   0x00000200U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRAS_2                   0x00000400U        /*!<Bit 2 */
-#define  FMC_SDTR2_TRAS_3                   0x00000800U        /*!<Bit 3 */
-#define  FMC_SDTR2_TRC                      0x0000F000U        /*!<TRC[2:0] bits (Row cycle delay) */
-#define  FMC_SDTR2_TRC_0                    0x00001000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRC_1                    0x00002000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRC_2                    0x00004000U        /*!<Bit 2 */
-#define  FMC_SDTR2_TWR                      0x000F0000U        /*!<TRC[2:0] bits (Write recovery delay) */
-#define  FMC_SDTR2_TWR_0                    0x00010000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TWR_1                    0x00020000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TWR_2                    0x00040000U        /*!<Bit 2 */
-#define  FMC_SDTR2_TRP                      0x00F00000U        /*!<TRP[2:0] bits (Row precharge delay) */
-#define  FMC_SDTR2_TRP_0                    0x00100000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRP_1                    0x00200000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRP_2                    0x00400000U        /*!<Bit 2 */
-#define  FMC_SDTR2_TRCD                     0x0F000000U        /*!<TRP[2:0] bits (Row to column delay) */
-#define  FMC_SDTR2_TRCD_0                   0x01000000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRCD_1                   0x02000000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRCD_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for FMC_SDCMR register  ******************/
-#define  FMC_SDCMR_MODE                     0x00000007U        /*!<MODE[2:0] bits (Command mode) */
-#define  FMC_SDCMR_MODE_0                   0x00000001U        /*!<Bit 0 */
-#define  FMC_SDCMR_MODE_1                   0x00000002U        /*!<Bit 1 */
-#define  FMC_SDCMR_MODE_2                   0x00000003U        /*!<Bit 2 */
-#define  FMC_SDCMR_CTB2                     0x00000008U        /*!<Command target 2 */
-#define  FMC_SDCMR_CTB1                     0x00000010U        /*!<Command target 1 */
-#define  FMC_SDCMR_NRFS                     0x000001E0U        /*!<NRFS[3:0] bits (Number of auto-refresh) */
-#define  FMC_SDCMR_NRFS_0                   0x00000020U        /*!<Bit 0 */
-#define  FMC_SDCMR_NRFS_1                   0x00000040U        /*!<Bit 1 */
-#define  FMC_SDCMR_NRFS_2                   0x00000080U        /*!<Bit 2 */
-#define  FMC_SDCMR_NRFS_3                   0x00000100U        /*!<Bit 3 */
-#define  FMC_SDCMR_MRD                      0x003FFE00U        /*!<MRD[12:0] bits (Mode register definition) */
-
-/******************  Bit definition for FMC_SDRTR register  ******************/
-#define  FMC_SDRTR_CRE                      0x00000001U        /*!<Clear refresh error flag */
-#define  FMC_SDRTR_COUNT                    0x00003FFEU        /*!<COUNT[12:0] bits (Refresh timer count) */
-#define  FMC_SDRTR_REIE                     0x00004000U        /*!<RES interupt enable */
-
-/******************  Bit definition for FMC_SDSR register  ******************/
-#define  FMC_SDSR_RE                        0x00000001U        /*!<Refresh error flag */
-#define  FMC_SDSR_MODES1                    0x00000006U        /*!<MODES1[1:0]bits (Status mode for bank 1) */
-#define  FMC_SDSR_MODES1_0                  0x00000002U        /*!<Bit 0 */
-#define  FMC_SDSR_MODES1_1                  0x00000004U        /*!<Bit 1 */
-#define  FMC_SDSR_MODES2                    0x00000018U        /*!<MODES2[1:0]bits (Status mode for bank 2) */
-#define  FMC_SDSR_MODES2_0                  0x00000008U        /*!<Bit 0 */
-#define  FMC_SDSR_MODES2_1                  0x00000010U        /*!<Bit 1 */
-#define  FMC_SDSR_BUSY                      0x00000020U        /*!<Busy status */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    0x00000003U
-#define GPIO_MODER_MODER0_0                  0x00000001U
-#define GPIO_MODER_MODER0_1                  0x00000002U
-#define GPIO_MODER_MODER1                    0x0000000CU
-#define GPIO_MODER_MODER1_0                  0x00000004U
-#define GPIO_MODER_MODER1_1                  0x00000008U
-#define GPIO_MODER_MODER2                    0x00000030U
-#define GPIO_MODER_MODER2_0                  0x00000010U
-#define GPIO_MODER_MODER2_1                  0x00000020U
-#define GPIO_MODER_MODER3                    0x000000C0U
-#define GPIO_MODER_MODER3_0                  0x00000040U
-#define GPIO_MODER_MODER3_1                  0x00000080U
-#define GPIO_MODER_MODER4                    0x00000300U
-#define GPIO_MODER_MODER4_0                  0x00000100U
-#define GPIO_MODER_MODER4_1                  0x00000200U
-#define GPIO_MODER_MODER5                    0x00000C00U
-#define GPIO_MODER_MODER5_0                  0x00000400U
-#define GPIO_MODER_MODER5_1                  0x00000800U
-#define GPIO_MODER_MODER6                    0x00003000U
-#define GPIO_MODER_MODER6_0                  0x00001000U
-#define GPIO_MODER_MODER6_1                  0x00002000U
-#define GPIO_MODER_MODER7                    0x0000C000U
-#define GPIO_MODER_MODER7_0                  0x00004000U
-#define GPIO_MODER_MODER7_1                  0x00008000U
-#define GPIO_MODER_MODER8                    0x00030000U
-#define GPIO_MODER_MODER8_0                  0x00010000U
-#define GPIO_MODER_MODER8_1                  0x00020000U
-#define GPIO_MODER_MODER9                    0x000C0000U
-#define GPIO_MODER_MODER9_0                  0x00040000U
-#define GPIO_MODER_MODER9_1                  0x00080000U
-#define GPIO_MODER_MODER10                   0x00300000U
-#define GPIO_MODER_MODER10_0                 0x00100000U
-#define GPIO_MODER_MODER10_1                 0x00200000U
-#define GPIO_MODER_MODER11                   0x00C00000U
-#define GPIO_MODER_MODER11_0                 0x00400000U
-#define GPIO_MODER_MODER11_1                 0x00800000U
-#define GPIO_MODER_MODER12                   0x03000000U
-#define GPIO_MODER_MODER12_0                 0x01000000U
-#define GPIO_MODER_MODER12_1                 0x02000000U
-#define GPIO_MODER_MODER13                   0x0C000000U
-#define GPIO_MODER_MODER13_0                 0x04000000U
-#define GPIO_MODER_MODER13_1                 0x08000000U
-#define GPIO_MODER_MODER14                   0x30000000U
-#define GPIO_MODER_MODER14_0                 0x10000000U
-#define GPIO_MODER_MODER14_1                 0x20000000U
-#define GPIO_MODER_MODER15                   0xC0000000U
-#define GPIO_MODER_MODER15_0                 0x40000000U
-#define GPIO_MODER_MODER15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     0x00000001U
-#define GPIO_OTYPER_OT_1                     0x00000002U
-#define GPIO_OTYPER_OT_2                     0x00000004U
-#define GPIO_OTYPER_OT_3                     0x00000008U
-#define GPIO_OTYPER_OT_4                     0x00000010U
-#define GPIO_OTYPER_OT_5                     0x00000020U
-#define GPIO_OTYPER_OT_6                     0x00000040U
-#define GPIO_OTYPER_OT_7                     0x00000080U
-#define GPIO_OTYPER_OT_8                     0x00000100U
-#define GPIO_OTYPER_OT_9                     0x00000200U
-#define GPIO_OTYPER_OT_10                    0x00000400U
-#define GPIO_OTYPER_OT_11                    0x00000800U
-#define GPIO_OTYPER_OT_12                    0x00001000U
-#define GPIO_OTYPER_OT_13                    0x00002000U
-#define GPIO_OTYPER_OT_14                    0x00004000U
-#define GPIO_OTYPER_OT_15                    0x00008000U
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
-#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
-#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
-#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
-#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
-#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
-#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
-#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
-#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
-#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
-#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
-#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
-#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
-#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
-#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
-#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
-#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
-#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
-#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
-#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
-#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
-#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
-#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
-#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
-#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
-#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
-#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
-#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
-#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
-#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
-#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
-#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
-#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
-#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
-#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
-#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
-#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
-#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
-#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
-#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
-#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
-#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
-#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
-#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
-#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
-#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
-#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
-#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    0x00000003U
-#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
-#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
-#define GPIO_PUPDR_PUPDR1                    0x0000000CU
-#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
-#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
-#define GPIO_PUPDR_PUPDR2                    0x00000030U
-#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
-#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
-#define GPIO_PUPDR_PUPDR3                    0x000000C0U
-#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
-#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
-#define GPIO_PUPDR_PUPDR4                    0x00000300U
-#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
-#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
-#define GPIO_PUPDR_PUPDR5                    0x00000C00U
-#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
-#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
-#define GPIO_PUPDR_PUPDR6                    0x00003000U
-#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
-#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
-#define GPIO_PUPDR_PUPDR7                    0x0000C000U
-#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
-#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
-#define GPIO_PUPDR_PUPDR8                    0x00030000U
-#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
-#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
-#define GPIO_PUPDR_PUPDR9                    0x000C0000U
-#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
-#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
-#define GPIO_PUPDR_PUPDR10                   0x00300000U
-#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
-#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
-#define GPIO_PUPDR_PUPDR11                   0x00C00000U
-#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
-#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
-#define GPIO_PUPDR_PUPDR12                   0x03000000U
-#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
-#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
-#define GPIO_PUPDR_PUPDR13                   0x0C000000U
-#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
-#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
-#define GPIO_PUPDR_PUPDR14                   0x30000000U
-#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
-#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
-#define GPIO_PUPDR_PUPDR15                   0xC0000000U
-#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
-#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       0x00000001U
-#define GPIO_IDR_IDR_1                       0x00000002U
-#define GPIO_IDR_IDR_2                       0x00000004U
-#define GPIO_IDR_IDR_3                       0x00000008U
-#define GPIO_IDR_IDR_4                       0x00000010U
-#define GPIO_IDR_IDR_5                       0x00000020U
-#define GPIO_IDR_IDR_6                       0x00000040U
-#define GPIO_IDR_IDR_7                       0x00000080U
-#define GPIO_IDR_IDR_8                       0x00000100U
-#define GPIO_IDR_IDR_9                       0x00000200U
-#define GPIO_IDR_IDR_10                      0x00000400U
-#define GPIO_IDR_IDR_11                      0x00000800U
-#define GPIO_IDR_IDR_12                      0x00001000U
-#define GPIO_IDR_IDR_13                      0x00002000U
-#define GPIO_IDR_IDR_14                      0x00004000U
-#define GPIO_IDR_IDR_15                      0x00008000U
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       0x00000001U
-#define GPIO_ODR_ODR_1                       0x00000002U
-#define GPIO_ODR_ODR_2                       0x00000004U
-#define GPIO_ODR_ODR_3                       0x00000008U
-#define GPIO_ODR_ODR_4                       0x00000010U
-#define GPIO_ODR_ODR_5                       0x00000020U
-#define GPIO_ODR_ODR_6                       0x00000040U
-#define GPIO_ODR_ODR_7                       0x00000080U
-#define GPIO_ODR_ODR_8                       0x00000100U
-#define GPIO_ODR_ODR_9                       0x00000200U
-#define GPIO_ODR_ODR_10                      0x00000400U
-#define GPIO_ODR_ODR_11                      0x00000800U
-#define GPIO_ODR_ODR_12                      0x00001000U
-#define GPIO_ODR_ODR_13                      0x00002000U
-#define GPIO_ODR_ODR_14                      0x00004000U
-#define GPIO_ODR_ODR_15                      0x00008000U
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       0x00000001U
-#define GPIO_BSRR_BS_1                       0x00000002U
-#define GPIO_BSRR_BS_2                       0x00000004U
-#define GPIO_BSRR_BS_3                       0x00000008U
-#define GPIO_BSRR_BS_4                       0x00000010U
-#define GPIO_BSRR_BS_5                       0x00000020U
-#define GPIO_BSRR_BS_6                       0x00000040U
-#define GPIO_BSRR_BS_7                       0x00000080U
-#define GPIO_BSRR_BS_8                       0x00000100U
-#define GPIO_BSRR_BS_9                       0x00000200U
-#define GPIO_BSRR_BS_10                      0x00000400U
-#define GPIO_BSRR_BS_11                      0x00000800U
-#define GPIO_BSRR_BS_12                      0x00001000U
-#define GPIO_BSRR_BS_13                      0x00002000U
-#define GPIO_BSRR_BS_14                      0x00004000U
-#define GPIO_BSRR_BS_15                      0x00008000U
-#define GPIO_BSRR_BR_0                       0x00010000U
-#define GPIO_BSRR_BR_1                       0x00020000U
-#define GPIO_BSRR_BR_2                       0x00040000U
-#define GPIO_BSRR_BR_3                       0x00080000U
-#define GPIO_BSRR_BR_4                       0x00100000U
-#define GPIO_BSRR_BR_5                       0x00200000U
-#define GPIO_BSRR_BR_6                       0x00400000U
-#define GPIO_BSRR_BR_7                       0x00800000U
-#define GPIO_BSRR_BR_8                       0x01000000U
-#define GPIO_BSRR_BR_9                       0x02000000U
-#define GPIO_BSRR_BR_10                      0x04000000U
-#define GPIO_BSRR_BR_11                      0x08000000U
-#define GPIO_BSRR_BR_12                      0x10000000U
-#define GPIO_BSRR_BR_13                      0x20000000U
-#define GPIO_BSRR_BR_14                      0x40000000U
-#define GPIO_BSRR_BR_15                      0x80000000U
-
-/****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0                       0x00000001U
-#define GPIO_LCKR_LCK1                       0x00000002U
-#define GPIO_LCKR_LCK2                       0x00000004U
-#define GPIO_LCKR_LCK3                       0x00000008U
-#define GPIO_LCKR_LCK4                       0x00000010U
-#define GPIO_LCKR_LCK5                       0x00000020U
-#define GPIO_LCKR_LCK6                       0x00000040U
-#define GPIO_LCKR_LCK7                       0x00000080U
-#define GPIO_LCKR_LCK8                       0x00000100U
-#define GPIO_LCKR_LCK9                       0x00000200U
-#define GPIO_LCKR_LCK10                      0x00000400U
-#define GPIO_LCKR_LCK11                      0x00000800U
-#define GPIO_LCKR_LCK12                      0x00001000U
-#define GPIO_LCKR_LCK13                      0x00002000U
-#define GPIO_LCKR_LCK14                      0x00004000U
-#define GPIO_LCKR_LCK15                      0x00008000U
-#define GPIO_LCKR_LCKK                       0x00010000U
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Inter-integrated Circuit Interface (I2C)              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define  I2C_CR1_PE                          0x00000001U        /*!< Peripheral enable                   */
-#define  I2C_CR1_TXIE                        0x00000002U        /*!< TX interrupt enable                 */
-#define  I2C_CR1_RXIE                        0x00000004U        /*!< RX interrupt enable                 */
-#define  I2C_CR1_ADDRIE                      0x00000008U        /*!< Address match interrupt enable      */
-#define  I2C_CR1_NACKIE                      0x00000010U        /*!< NACK received interrupt enable      */
-#define  I2C_CR1_STOPIE                      0x00000020U        /*!< STOP detection interrupt enable     */
-#define  I2C_CR1_TCIE                        0x00000040U        /*!< Transfer complete interrupt enable  */
-#define  I2C_CR1_ERRIE                       0x00000080U        /*!< Errors interrupt enable             */
-#define  I2C_CR1_DNF                         0x00000F00U        /*!< Digital noise filter                */
-#define  I2C_CR1_ANFOFF                      0x00001000U        /*!< Analog noise filter OFF             */
-#define  I2C_CR1_TXDMAEN                     0x00004000U        /*!< DMA transmission requests enable    */
-#define  I2C_CR1_RXDMAEN                     0x00008000U        /*!< DMA reception requests enable       */
-#define  I2C_CR1_SBC                         0x00010000U        /*!< Slave byte control                  */
-#define  I2C_CR1_NOSTRETCH                   0x00020000U        /*!< Clock stretching disable            */
-#define  I2C_CR1_GCEN                        0x00080000U        /*!< General call enable                 */
-#define  I2C_CR1_SMBHEN                      0x00100000U        /*!< SMBus host address enable           */
-#define  I2C_CR1_SMBDEN                      0x00200000U        /*!< SMBus device default address enable */
-#define  I2C_CR1_ALERTEN                     0x00400000U        /*!< SMBus alert enable                  */
-#define  I2C_CR1_PECEN                       0x00800000U        /*!< PEC enable                          */
-
-/* Legacy define */
-#define  I2C_CR1_DFN                         I2C_CR1_DNF                   /*!< Digital noise filter                */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_SADD                        0x000003FFU        /*!< Slave address (master mode)                             */
-#define  I2C_CR2_RD_WRN                      0x00000400U        /*!< Transfer direction (master mode)                        */
-#define  I2C_CR2_ADD10                       0x00000800U        /*!< 10-bit addressing mode (master mode)                    */
-#define  I2C_CR2_HEAD10R                     0x00001000U        /*!< 10-bit address header only read direction (master mode) */
-#define  I2C_CR2_START                       0x00002000U        /*!< START generation                                        */
-#define  I2C_CR2_STOP                        0x00004000U        /*!< STOP generation (master mode)                           */
-#define  I2C_CR2_NACK                        0x00008000U        /*!< NACK generation (slave mode)                            */
-#define  I2C_CR2_NBYTES                      0x00FF0000U        /*!< Number of bytes                                         */
-#define  I2C_CR2_RELOAD                      0x01000000U        /*!< NBYTES reload mode                                      */
-#define  I2C_CR2_AUTOEND                     0x02000000U        /*!< Automatic end mode (master mode)                        */
-#define  I2C_CR2_PECBYTE                     0x04000000U        /*!< Packet error checking byte                              */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define  I2C_OAR1_OA1                        0x000003FFU        /*!< Interface own address 1   */
-#define  I2C_OAR1_OA1MODE                    0x00000400U        /*!< Own address 1 10-bit mode */
-#define  I2C_OAR1_OA1EN                      0x00008000U        /*!< Own address 1 enable      */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define  I2C_OAR2_OA2                        0x000000FEU        /*!< Interface own address 2 */
-#define  I2C_OAR2_OA2MSK                     0x00000700U        /*!< Own address 2 masks     */
-#define  I2C_OAR2_OA2NOMASK                  0x00000000U        /*!< No mask */
-#define  I2C_OAR2_OA2MASK01                  0x00000100U        /*!< OA2[1] is masked, Only OA2[7:2] are compared */
-#define  I2C_OAR2_OA2MASK02                  0x00000200U        /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
-#define  I2C_OAR2_OA2MASK03                  0x00000300U        /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
-#define  I2C_OAR2_OA2MASK04                  0x00000400U        /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
-#define  I2C_OAR2_OA2MASK05                  0x00000500U        /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
-#define  I2C_OAR2_OA2MASK06                  0x00000600U        /*!< OA2[6:1] is masked, Only OA2[7] are compared */
-#define  I2C_OAR2_OA2MASK07                  0x00000700U        /*!< OA2[7:1] is masked, No comparison is done */
-#define  I2C_OAR2_OA2EN                      0x00008000U        /*!< Own address 2 enable    */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define  I2C_TIMINGR_SCLL                    0x000000FFU        /*!< SCL low period (master mode)  */
-#define  I2C_TIMINGR_SCLH                    0x0000FF00U        /*!< SCL high period (master mode) */
-#define  I2C_TIMINGR_SDADEL                  0x000F0000U        /*!< Data hold time                */
-#define  I2C_TIMINGR_SCLDEL                  0x00F00000U        /*!< Data setup time               */
-#define  I2C_TIMINGR_PRESC                   0xF0000000U        /*!< Timings prescaler             */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define  I2C_TIMEOUTR_TIMEOUTA               0x00000FFFU        /*!< Bus timeout A                 */
-#define  I2C_TIMEOUTR_TIDLE                  0x00001000U        /*!< Idle clock timeout detection  */
-#define  I2C_TIMEOUTR_TIMOUTEN               0x00008000U        /*!< Clock timeout enable          */
-#define  I2C_TIMEOUTR_TIMEOUTB               0x0FFF0000U        /*!< Bus timeout B                 */
-#define  I2C_TIMEOUTR_TEXTEN                 0x80000000U        /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define  I2C_ISR_TXE                         0x00000001U        /*!< Transmit data register empty    */
-#define  I2C_ISR_TXIS                        0x00000002U        /*!< Transmit interrupt status       */
-#define  I2C_ISR_RXNE                        0x00000004U        /*!< Receive data register not empty */
-#define  I2C_ISR_ADDR                        0x00000008U        /*!< Address matched (slave mode)    */
-#define  I2C_ISR_NACKF                       0x00000010U        /*!< NACK received flag              */
-#define  I2C_ISR_STOPF                       0x00000020U        /*!< STOP detection flag             */
-#define  I2C_ISR_TC                          0x00000040U        /*!< Transfer complete (master mode) */
-#define  I2C_ISR_TCR                         0x00000080U        /*!< Transfer complete reload        */
-#define  I2C_ISR_BERR                        0x00000100U        /*!< Bus error                       */
-#define  I2C_ISR_ARLO                        0x00000200U        /*!< Arbitration lost                */
-#define  I2C_ISR_OVR                         0x00000400U        /*!< Overrun/Underrun                */
-#define  I2C_ISR_PECERR                      0x00000800U        /*!< PEC error in reception          */
-#define  I2C_ISR_TIMEOUT                     0x00001000U        /*!< Timeout or Tlow detection flag  */
-#define  I2C_ISR_ALERT                       0x00002000U        /*!< SMBus alert                     */
-#define  I2C_ISR_BUSY                        0x00008000U        /*!< Bus busy                        */
-#define  I2C_ISR_DIR                         0x00010000U        /*!< Transfer direction (slave mode) */
-#define  I2C_ISR_ADDCODE                     0x00FE0000U        /*!< Address match code (slave mode) */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define  I2C_ICR_ADDRCF                      0x00000008U        /*!< Address matched clear flag      */
-#define  I2C_ICR_NACKCF                      0x00000010U        /*!< NACK clear flag                 */
-#define  I2C_ICR_STOPCF                      0x00000020U        /*!< STOP detection clear flag       */
-#define  I2C_ICR_BERRCF                      0x00000100U        /*!< Bus error clear flag            */
-#define  I2C_ICR_ARLOCF                      0x00000200U        /*!< Arbitration lost clear flag     */
-#define  I2C_ICR_OVRCF                       0x00000400U        /*!< Overrun/Underrun clear flag     */
-#define  I2C_ICR_PECCF                       0x00000800U        /*!< PAC error clear flag            */
-#define  I2C_ICR_TIMOUTCF                    0x00001000U        /*!< Timeout clear flag              */
-#define  I2C_ICR_ALERTCF                     0x00002000U        /*!< Alert clear flag                */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define  I2C_PECR_PEC                        0x000000FFU        /*!< PEC register        */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define  I2C_RXDR_RXDATA                     0x000000FFU        /*!< 8-bit receive data  */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define  I2C_TXDR_TXDATA                     0x000000FFU        /*!< 8-bit transmit data */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Independent WATCHDOG                             */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         0x01U               /*!< Watchdog prescaler value update */
-#define  IWDG_SR_RVU                         0x02U               /*!< Watchdog counter reload value update */
-#define  IWDG_SR_WVU                         0x04U               /*!< Watchdog counter window value update */
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_WINR_WIN                       0x0FFFU             /*!< Watchdog counter window value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      LCD-TFT Display Controller (LTDC)                     */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for LTDC_SSCR register  *****************/
-
-#define LTDC_SSCR_VSH                       0x000007FFU              /*!< Vertical Synchronization Height  */
-#define LTDC_SSCR_HSW                       0x0FFF0000U              /*!< Horizontal Synchronization Width */
-
-/********************  Bit definition for LTDC_BPCR register  *****************/
-
-#define LTDC_BPCR_AVBP                      0x000007FFU              /*!< Accumulated Vertical Back Porch   */
-#define LTDC_BPCR_AHBP                      0x0FFF0000U              /*!< Accumulated Horizontal Back Porch */
-
-/********************  Bit definition for LTDC_AWCR register  *****************/
-
-#define LTDC_AWCR_AAH                       0x000007FFU              /*!< Accumulated Active heigh */
-#define LTDC_AWCR_AAW                       0x0FFF0000U              /*!< Accumulated Active Width */
-
-/********************  Bit definition for LTDC_TWCR register  *****************/
-
-#define LTDC_TWCR_TOTALH                    0x000007FFU              /*!< Total Heigh */
-#define LTDC_TWCR_TOTALW                    0x0FFF0000U              /*!< Total Width */
-
-/********************  Bit definition for LTDC_GCR register  ******************/
-
-#define LTDC_GCR_LTDCEN                     0x00000001U              /*!< LCD-TFT controller enable bit       */
-#define LTDC_GCR_DBW                        0x00000070U              /*!< Dither Blue Width                   */
-#define LTDC_GCR_DGW                        0x00000700U              /*!< Dither Green Width                  */
-#define LTDC_GCR_DRW                        0x00007000U              /*!< Dither Red Width                    */
-#define LTDC_GCR_DEN                        0x00010000U              /*!< Dither Enable                       */
-#define LTDC_GCR_PCPOL                      0x10000000U              /*!< Pixel Clock Polarity                */
-#define LTDC_GCR_DEPOL                      0x20000000U              /*!< Data Enable Polarity                */
-#define LTDC_GCR_VSPOL                      0x40000000U              /*!< Vertical Synchronization Polarity   */
-#define LTDC_GCR_HSPOL                      0x80000000U              /*!< Horizontal Synchronization Polarity */
-
-/* Legacy define */
-#define LTDC_GCR_DTEN                       LTDC_GCR_DEN
-
-/********************  Bit definition for LTDC_SRCR register  *****************/
-
-#define LTDC_SRCR_IMR                      0x00000001U               /*!< Immediate Reload         */
-#define LTDC_SRCR_VBR                      0x00000002U               /*!< Vertical Blanking Reload */
-
-/********************  Bit definition for LTDC_BCCR register  *****************/
-
-#define LTDC_BCCR_BCBLUE                    0x000000FFU              /*!< Background Blue value  */
-#define LTDC_BCCR_BCGREEN                   0x0000FF00U              /*!< Background Green value */
-#define LTDC_BCCR_BCRED                     0x00FF0000U              /*!< Background Red value   */
-
-/********************  Bit definition for LTDC_IER register  ******************/
-
-#define LTDC_IER_LIE                        0x00000001U              /*!< Line Interrupt Enable            */
-#define LTDC_IER_FUIE                       0x00000002U              /*!< FIFO Underrun Interrupt Enable   */
-#define LTDC_IER_TERRIE                     0x00000004U              /*!< Transfer Error Interrupt Enable  */
-#define LTDC_IER_RRIE                       0x00000008U              /*!< Register Reload interrupt enable */
-
-/********************  Bit definition for LTDC_ISR register  ******************/
-
-#define LTDC_ISR_LIF                        0x00000001U              /*!< Line Interrupt Flag */
-#define LTDC_ISR_FUIF                       0x00000002U              /*!< FIFO Underrun Interrupt Flag */
-#define LTDC_ISR_TERRIF                     0x00000004U              /*!< Transfer Error Interrupt Flag */
-#define LTDC_ISR_RRIF                       0x00000008U              /*!< Register Reload interrupt Flag */
-
-/********************  Bit definition for LTDC_ICR register  ******************/
-
-#define LTDC_ICR_CLIF                       0x00000001U              /*!< Clears the Line Interrupt Flag */
-#define LTDC_ICR_CFUIF                      0x00000002U              /*!< Clears the FIFO Underrun Interrupt Flag */
-#define LTDC_ICR_CTERRIF                    0x00000004U              /*!< Clears the Transfer Error Interrupt Flag */
-#define LTDC_ICR_CRRIF                      0x00000008U              /*!< Clears Register Reload interrupt Flag */
-
-/********************  Bit definition for LTDC_LIPCR register  ****************/
-
-#define LTDC_LIPCR_LIPOS                    0x000007FFU              /*!< Line Interrupt Position */
-
-/********************  Bit definition for LTDC_CPSR register  *****************/
-
-#define LTDC_CPSR_CYPOS                     0x0000FFFFU              /*!< Current Y Position */
-#define LTDC_CPSR_CXPOS                     0xFFFF0000U              /*!< Current X Position */
-
-/********************  Bit definition for LTDC_CDSR register  *****************/
-
-#define LTDC_CDSR_VDES                      0x00000001U              /*!< Vertical Data Enable Status       */
-#define LTDC_CDSR_HDES                      0x00000002U              /*!< Horizontal Data Enable Status     */
-#define LTDC_CDSR_VSYNCS                    0x00000004U              /*!< Vertical Synchronization Status   */
-#define LTDC_CDSR_HSYNCS                    0x00000008U              /*!< Horizontal Synchronization Status */
-
-/********************  Bit definition for LTDC_LxCR register  *****************/
-
-#define LTDC_LxCR_LEN                       0x00000001U              /*!< Layer Enable              */
-#define LTDC_LxCR_COLKEN                    0x00000002U              /*!< Color Keying Enable       */
-#define LTDC_LxCR_CLUTEN                    0x00000010U              /*!< Color Lockup Table Enable */
-
-/********************  Bit definition for LTDC_LxWHPCR register  **************/
-
-#define LTDC_LxWHPCR_WHSTPOS                0x00000FFFU              /*!< Window Horizontal Start Position */
-#define LTDC_LxWHPCR_WHSPPOS                0xFFFF0000U              /*!< Window Horizontal Stop Position  */
-
-/********************  Bit definition for LTDC_LxWVPCR register  **************/
-
-#define LTDC_LxWVPCR_WVSTPOS                0x00000FFFU              /*!< Window Vertical Start Position */
-#define LTDC_LxWVPCR_WVSPPOS                0xFFFF0000U              /*!< Window Vertical Stop Position  */
-
-/********************  Bit definition for LTDC_LxCKCR register  ***************/
-
-#define LTDC_LxCKCR_CKBLUE                  0x000000FFU              /*!< Color Key Blue value  */
-#define LTDC_LxCKCR_CKGREEN                 0x0000FF00U              /*!< Color Key Green value */
-#define LTDC_LxCKCR_CKRED                   0x00FF0000U              /*!< Color Key Red value   */
-
-/********************  Bit definition for LTDC_LxPFCR register  ***************/
-
-#define LTDC_LxPFCR_PF                      0x00000007U              /*!< Pixel Format */
-
-/********************  Bit definition for LTDC_LxCACR register  ***************/
-
-#define LTDC_LxCACR_CONSTA                  0x000000FFU              /*!< Constant Alpha */
-
-/********************  Bit definition for LTDC_LxDCCR register  ***************/
-
-#define LTDC_LxDCCR_DCBLUE                  0x000000FFU              /*!< Default Color Blue  */
-#define LTDC_LxDCCR_DCGREEN                 0x0000FF00U              /*!< Default Color Green */
-#define LTDC_LxDCCR_DCRED                   0x00FF0000U              /*!< Default Color Red   */
-#define LTDC_LxDCCR_DCALPHA                 0xFF000000U              /*!< Default Color Alpha */
-
-/********************  Bit definition for LTDC_LxBFCR register  ***************/
-
-#define LTDC_LxBFCR_BF2                     0x00000007U              /*!< Blending Factor 2 */
-#define LTDC_LxBFCR_BF1                     0x00000700U              /*!< Blending Factor 1 */
-
-/********************  Bit definition for LTDC_LxCFBAR register  **************/
-
-#define LTDC_LxCFBAR_CFBADD                 0xFFFFFFFFU              /*!< Color Frame Buffer Start Address */
-
-/********************  Bit definition for LTDC_LxCFBLR register  **************/
-
-#define LTDC_LxCFBLR_CFBLL                  0x00001FFFU              /*!< Color Frame Buffer Line Length    */
-#define LTDC_LxCFBLR_CFBP                   0x1FFF0000U              /*!< Color Frame Buffer Pitch in bytes */
-
-/********************  Bit definition for LTDC_LxCFBLNR register  *************/
-
-#define LTDC_LxCFBLNR_CFBLNBR               0x000007FFU              /*!< Frame Buffer Line Number */
-
-/********************  Bit definition for LTDC_LxCLUTWR register  *************/
-
-#define LTDC_LxCLUTWR_BLUE                  0x000000FFU              /*!< Blue value   */
-#define LTDC_LxCLUTWR_GREEN                 0x0000FF00U              /*!< Green value  */
-#define LTDC_LxCLUTWR_RED                   0x00FF0000U              /*!< Red value    */
-#define LTDC_LxCLUTWR_CLUTADD               0xFF000000U              /*!< CLUT address */
-
-/******************************************************************************/
-/*                                                                            */
-/*                             Power Control                                  */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for PWR_CR1 register  ********************/
-#define  PWR_CR1_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
-#define  PWR_CR1_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
-#define  PWR_CR1_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
-#define  PWR_CR1_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
-#define  PWR_CR1_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR1_PLS_0                        0x00000020U     /*!< Bit 0 */
-#define  PWR_CR1_PLS_1                        0x00000040U     /*!< Bit 1 */
-#define  PWR_CR1_PLS_2                        0x00000080U     /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define  PWR_CR1_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
-#define  PWR_CR1_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
-#define  PWR_CR1_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
-#define  PWR_CR1_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
-#define  PWR_CR1_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
-#define  PWR_CR1_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
-#define  PWR_CR1_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
-#define  PWR_CR1_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
-#define  PWR_CR1_DBP                          0x00000100U     /*!< Disable Backup Domain write protection                     */
-#define  PWR_CR1_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                              */
-#define  PWR_CR1_LPUDS                        0x00000400U     /*!< Low-power regulator in deepsleep under-drive mode          */
-#define  PWR_CR1_MRUDS                        0x00000800U     /*!< Main regulator in deepsleep under-drive mode               */
-#define  PWR_CR1_ADCDC1                       0x00002000U     /*!< Refer to AN4073 on how to use this bit */
-#define  PWR_CR1_VOS                          0x0000C000U     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
-#define  PWR_CR1_VOS_0                        0x00004000U     /*!< Bit 0 */
-#define  PWR_CR1_VOS_1                        0x00008000U     /*!< Bit 1 */
-#define  PWR_CR1_ODEN                         0x00010000U     /*!< Over Drive enable                   */
-#define  PWR_CR1_ODSWEN                       0x00020000U     /*!< Over Drive switch enabled           */
-#define  PWR_CR1_UDEN                         0x000C0000U     /*!< Under Drive enable in stop mode     */
-#define  PWR_CR1_UDEN_0                       0x00040000U     /*!< Bit 0                               */
-#define  PWR_CR1_UDEN_1                       0x00080000U     /*!< Bit 1                               */
-
-/*******************  Bit definition for PWR_CSR1 register  ********************/
-#define  PWR_CSR1_WUIF                        0x00000001U     /*!< Wake up internal Flag                            */
-#define  PWR_CSR1_SBF                         0x00000002U     /*!< Standby Flag                                     */
-#define  PWR_CSR1_PVDO                        0x00000004U     /*!< PVD Output                                       */
-#define  PWR_CSR1_BRR                         0x00000008U     /*!< Backup regulator ready                           */
-#define  PWR_CSR1_EIWUP                       0x00000100U     /*!< Enable internal wakeup                           */
-#define  PWR_CSR1_BRE                         0x00000200U     /*!< Backup regulator enable                          */
-#define  PWR_CSR1_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
-#define  PWR_CSR1_ODRDY                       0x00010000U     /*!< Over Drive generator ready                       */
-#define  PWR_CSR1_ODSWRDY                     0x00020000U     /*!< Over Drive Switch ready                          */
-#define  PWR_CSR1_UDRDY                       0x000C0000U     /*!< Under Drive ready                                */
-
-/* Legacy define */
-#define  PWR_CSR1_UDSWRDY                     PWR_CSR1_UDRDY
-
-/********************  Bit definition for PWR_CR2 register  ********************/
-#define  PWR_CR2_CWUPF1                         0x00000001U     /*!< Clear Wakeup Pin Flag for PA0      */
-#define  PWR_CR2_CWUPF2                         0x00000002U     /*!< Clear Wakeup Pin Flag for PA2      */
-#define  PWR_CR2_CWUPF3                         0x00000004U     /*!< Clear Wakeup Pin Flag for PC1      */
-#define  PWR_CR2_CWUPF4                         0x00000008U     /*!< Clear Wakeup Pin Flag for PC13     */
-#define  PWR_CR2_CWUPF5                         0x00000010U     /*!< Clear Wakeup Pin Flag for PI8      */
-#define  PWR_CR2_CWUPF6                         0x00000020U     /*!< Clear Wakeup Pin Flag for PI11     */
-#define  PWR_CR2_WUPP1                          0x00000100U     /*!< Wakeup Pin Polarity bit for PA0    */
-#define  PWR_CR2_WUPP2                          0x00000200U     /*!< Wakeup Pin Polarity bit for PA2    */
-#define  PWR_CR2_WUPP3                          0x00000400U     /*!< Wakeup Pin Polarity bit for PC1    */
-#define  PWR_CR2_WUPP4                          0x00000800U     /*!< Wakeup Pin Polarity bit for PC13   */
-#define  PWR_CR2_WUPP5                          0x00001000U     /*!< Wakeup Pin Polarity bit for PI8    */
-#define  PWR_CR2_WUPP6                          0x00002000U     /*!< Wakeup Pin Polarity bit for PI11   */
-
-/*******************  Bit definition for PWR_CSR2 register  ********************/
-#define  PWR_CSR2_WUPF1                         0x00000001U     /*!< Wakeup Pin Flag for PA0            */
-#define  PWR_CSR2_WUPF2                         0x00000002U     /*!< Wakeup Pin Flag for PA2            */
-#define  PWR_CSR2_WUPF3                         0x00000004U     /*!< Wakeup Pin Flag for PC1            */
-#define  PWR_CSR2_WUPF4                         0x00000008U     /*!< Wakeup Pin Flag for PC13           */
-#define  PWR_CSR2_WUPF5                         0x00000010U     /*!< Wakeup Pin Flag for PI8            */
-#define  PWR_CSR2_WUPF6                         0x00000020U     /*!< Wakeup Pin Flag for PI11           */
-#define  PWR_CSR2_EWUP1                         0x00000100U     /*!< Enable Wakeup Pin PA0              */
-#define  PWR_CSR2_EWUP2                         0x00000200U     /*!< Enable Wakeup Pin PA2              */
-#define  PWR_CSR2_EWUP3                         0x00000400U     /*!< Enable Wakeup Pin PC1              */
-#define  PWR_CSR2_EWUP4                         0x00000800U     /*!< Enable Wakeup Pin PC13             */
-#define  PWR_CSR2_EWUP5                         0x00001000U     /*!< Enable Wakeup Pin PI8              */
-#define  PWR_CSR2_EWUP6                         0x00002000U     /*!< Enable Wakeup Pin PI11             */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    QUADSPI                                 */
-/*                                                                            */
-/******************************************************************************/
-/* QUADSPI IP version */
-#define QSPI1_V1_0
-/*****************  Bit definition for QUADSPI_CR register  *******************/
-#define  QUADSPI_CR_EN                           0x00000001U            /*!< Enable                            */
-#define  QUADSPI_CR_ABORT                        0x00000002U            /*!< Abort request                     */
-#define  QUADSPI_CR_DMAEN                        0x00000004U            /*!< DMA Enable                        */
-#define  QUADSPI_CR_TCEN                         0x00000008U            /*!< Timeout Counter Enable            */
-#define  QUADSPI_CR_SSHIFT                       0x00000010U            /*!< Sample Shift                      */
-#define  QUADSPI_CR_DFM                          0x00000040U            /*!< Dual Flash Mode                   */
-#define  QUADSPI_CR_FSEL                         0x00000080U            /*!< Flash Select                      */
-#define  QUADSPI_CR_FTHRES                       0x00001F00U            /*!< FTHRES[4:0] FIFO Level            */
-#define  QUADSPI_CR_FTHRES_0                     0x00000100U            /*!< Bit 0 */
-#define  QUADSPI_CR_FTHRES_1                     0x00000200U            /*!< Bit 1 */
-#define  QUADSPI_CR_FTHRES_2                     0x00000400U            /*!< Bit 2 */
-#define  QUADSPI_CR_FTHRES_3                     0x00000800U            /*!< Bit 3 */
-#define  QUADSPI_CR_FTHRES_4                     0x00001000U            /*!< Bit 4 */
-#define  QUADSPI_CR_TEIE                         0x00010000U            /*!< Transfer Error Interrupt Enable    */
-#define  QUADSPI_CR_TCIE                         0x00020000U            /*!< Transfer Complete Interrupt Enable */
-#define  QUADSPI_CR_FTIE                         0x00040000U            /*!< FIFO Threshold Interrupt Enable    */
-#define  QUADSPI_CR_SMIE                         0x00080000U            /*!< Status Match Interrupt Enable      */
-#define  QUADSPI_CR_TOIE                         0x00100000U            /*!< TimeOut Interrupt Enable           */
-#define  QUADSPI_CR_APMS                         0x00400000U            /*!< Bit 1                              */
-#define  QUADSPI_CR_PMM                          0x00800000U            /*!< Polling Match Mode                 */
-#define  QUADSPI_CR_PRESCALER                    0xFF000000U            /*!< PRESCALER[7:0] Clock prescaler     */
-#define  QUADSPI_CR_PRESCALER_0                  0x01000000U            /*!< Bit 0 */
-#define  QUADSPI_CR_PRESCALER_1                  0x02000000U            /*!< Bit 1 */
-#define  QUADSPI_CR_PRESCALER_2                  0x04000000U            /*!< Bit 2 */
-#define  QUADSPI_CR_PRESCALER_3                  0x08000000U            /*!< Bit 3 */
-#define  QUADSPI_CR_PRESCALER_4                  0x10000000U            /*!< Bit 4 */
-#define  QUADSPI_CR_PRESCALER_5                  0x20000000U            /*!< Bit 5 */
-#define  QUADSPI_CR_PRESCALER_6                  0x40000000U            /*!< Bit 6 */
-#define  QUADSPI_CR_PRESCALER_7                  0x80000000U            /*!< Bit 7 */
-
-/*****************  Bit definition for QUADSPI_DCR register  ******************/
-#define  QUADSPI_DCR_CKMODE                      0x00000001U            /*!< Mode 0 / Mode 3                 */
-#define  QUADSPI_DCR_CSHT                        0x00000700U            /*!< CSHT[2:0]: ChipSelect High Time */
-#define  QUADSPI_DCR_CSHT_0                      0x00000100U            /*!< Bit 0 */
-#define  QUADSPI_DCR_CSHT_1                      0x00000200U            /*!< Bit 1 */
-#define  QUADSPI_DCR_CSHT_2                      0x00000400U            /*!< Bit 2 */
-#define  QUADSPI_DCR_FSIZE                       0x001F0000U            /*!< FSIZE[4:0]: Flash Size          */
-#define  QUADSPI_DCR_FSIZE_0                     0x00010000U            /*!< Bit 0 */
-#define  QUADSPI_DCR_FSIZE_1                     0x00020000U            /*!< Bit 1 */
-#define  QUADSPI_DCR_FSIZE_2                     0x00040000U            /*!< Bit 2 */
-#define  QUADSPI_DCR_FSIZE_3                     0x00080000U            /*!< Bit 3 */
-#define  QUADSPI_DCR_FSIZE_4                     0x00100000U            /*!< Bit 4 */
-
-/******************  Bit definition for QUADSPI_SR register  *******************/
-#define  QUADSPI_SR_TEF                          0x00000001U             /*!< Transfer Error Flag    */
-#define  QUADSPI_SR_TCF                          0x00000002U             /*!< Transfer Complete Flag */
-#define  QUADSPI_SR_FTF                          0x00000004U             /*!< FIFO Threshlod Flag    */
-#define  QUADSPI_SR_SMF                          0x00000008U             /*!< Status Match Flag      */
-#define  QUADSPI_SR_TOF                          0x00000010U             /*!< Timeout Flag           */
-#define  QUADSPI_SR_BUSY                         0x00000020U             /*!< Busy                   */
-#define  QUADSPI_SR_FLEVEL                       0x00001F00U             /*!< FIFO Threshlod Flag    */
-#define  QUADSPI_SR_FLEVEL_0                     0x00000100U             /*!< Bit 0 */
-#define  QUADSPI_SR_FLEVEL_1                     0x00000200U             /*!< Bit 1 */
-#define  QUADSPI_SR_FLEVEL_2                     0x00000400U             /*!< Bit 2 */
-#define  QUADSPI_SR_FLEVEL_3                     0x00000800U             /*!< Bit 3 */
-#define  QUADSPI_SR_FLEVEL_4                     0x00001000U             /*!< Bit 4 */
-
-/******************  Bit definition for QUADSPI_FCR register  ******************/
-#define  QUADSPI_FCR_CTEF                        0x00000001U             /*!< Clear Transfer Error Flag    */
-#define  QUADSPI_FCR_CTCF                        0x00000002U             /*!< Clear Transfer Complete Flag */
-#define  QUADSPI_FCR_CSMF                        0x00000008U             /*!< Clear Status Match Flag      */
-#define  QUADSPI_FCR_CTOF                        0x00000010U             /*!< Clear Timeout Flag           */
-
-/******************  Bit definition for QUADSPI_DLR register  ******************/
-#define  QUADSPI_DLR_DL                          0xFFFFFFFFU             /*!< DL[31:0]: Data Length */
-
-/******************  Bit definition for QUADSPI_CCR register  ******************/
-#define  QUADSPI_CCR_INSTRUCTION                  0x000000FFU            /*!< INSTRUCTION[7:0]: Instruction    */
-#define  QUADSPI_CCR_INSTRUCTION_0                0x00000001U            /*!< Bit 0 */
-#define  QUADSPI_CCR_INSTRUCTION_1                0x00000002U            /*!< Bit 1 */
-#define  QUADSPI_CCR_INSTRUCTION_2                0x00000004U            /*!< Bit 2 */
-#define  QUADSPI_CCR_INSTRUCTION_3                0x00000008U            /*!< Bit 3 */
-#define  QUADSPI_CCR_INSTRUCTION_4                0x00000010U            /*!< Bit 4 */
-#define  QUADSPI_CCR_INSTRUCTION_5                0x00000020U            /*!< Bit 5 */
-#define  QUADSPI_CCR_INSTRUCTION_6                0x00000040U            /*!< Bit 6 */
-#define  QUADSPI_CCR_INSTRUCTION_7                0x00000080U            /*!< Bit 7 */
-#define  QUADSPI_CCR_IMODE                        0x00000300U            /*!< IMODE[1:0]: Instruction Mode      */
-#define  QUADSPI_CCR_IMODE_0                      0x00000100U            /*!< Bit 0 */
-#define  QUADSPI_CCR_IMODE_1                      0x00000200U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ADMODE                       0x00000C00U            /*!< ADMODE[1:0]: Address Mode         */
-#define  QUADSPI_CCR_ADMODE_0                     0x00000400U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ADMODE_1                     0x00000800U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ADSIZE                       0x00003000U            /*!< ADSIZE[1:0]: Address Size         */
-#define  QUADSPI_CCR_ADSIZE_0                     0x00001000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ADSIZE_1                     0x00002000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ABMODE                       0x0000C000U            /*!< ABMODE[1:0]: Alternate Bytes Mode */
-#define  QUADSPI_CCR_ABMODE_0                     0x00004000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ABMODE_1                     0x00008000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ABSIZE                       0x00030000U            /*!< ABSIZE[1:0]: Instruction Mode     */
-#define  QUADSPI_CCR_ABSIZE_0                     0x00010000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ABSIZE_1                     0x00020000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_DCYC                         0x007C0000U            /*!< DCYC[4:0]: Dummy Cycles           */
-#define  QUADSPI_CCR_DCYC_0                       0x00040000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_DCYC_1                       0x00080000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_DCYC_2                       0x00100000U            /*!< Bit 2 */
-#define  QUADSPI_CCR_DCYC_3                       0x00200000U            /*!< Bit 3 */
-#define  QUADSPI_CCR_DCYC_4                       0x00400000U            /*!< Bit 4 */
-#define  QUADSPI_CCR_DMODE                        0x03000000U            /*!< DMODE[1:0]: Data Mode              */
-#define  QUADSPI_CCR_DMODE_0                      0x01000000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_DMODE_1                      0x02000000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_FMODE                        0x0C000000U            /*!< FMODE[1:0]: Functional Mode        */
-#define  QUADSPI_CCR_FMODE_0                      0x04000000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_FMODE_1                      0x08000000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_SIOO                         0x10000000U            /*!< SIOO: Send Instruction Only Once Mode */
-#define  QUADSPI_CCR_DHHC                         0x40000000U            /*!< DHHC: Delay Half Hclk Cycle           */
-#define  QUADSPI_CCR_DDRM                         0x80000000U            /*!< DDRM: Double Data Rate Mode           */
-/******************  Bit definition for QUADSPI_AR register  *******************/
-#define  QUADSPI_AR_ADDRESS                       0xFFFFFFFFU            /*!< ADDRESS[31:0]: Address */
-
-/******************  Bit definition for QUADSPI_ABR register  ******************/
-#define  QUADSPI_ABR_ALTERNATE                    0xFFFFFFFFU            /*!< ALTERNATE[31:0]: Alternate Bytes */
-
-/******************  Bit definition for QUADSPI_DR register  *******************/
-#define  QUADSPI_DR_DATA                          0xFFFFFFFFU            /*!< DATA[31:0]: Data */
-
-/******************  Bit definition for QUADSPI_PSMKR register  ****************/
-#define  QUADSPI_PSMKR_MASK                       0xFFFFFFFFU            /*!< MASK[31:0]: Status Mask */
-
-/******************  Bit definition for QUADSPI_PSMAR register  ****************/
-#define  QUADSPI_PSMAR_MATCH                      0xFFFFFFFFU            /*!< MATCH[31:0]: Status Match */
-
-/******************  Bit definition for QUADSPI_PIR register  *****************/
-#define  QUADSPI_PIR_INTERVAL                     0x0000FFFFU            /*!< INTERVAL[15:0]: Polling Interval */
-
-/******************  Bit definition for QUADSPI_LPTR register  *****************/
-#define  QUADSPI_LPTR_TIMEOUT                     0x0000FFFFU            /*!< TIMEOUT[15:0]: Timeout period */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        0x00000001U
-#define  RCC_CR_HSIRDY                       0x00000002U
-#define  RCC_CR_HSITRIM                      0x000000F8U
-#define  RCC_CR_HSITRIM_0                    0x00000008U /*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    0x00000010U /*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    0x00000020U /*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    0x00000040U /*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    0x00000080U /*!<Bit 4 */
-#define  RCC_CR_HSICAL                       0x0000FF00U
-#define  RCC_CR_HSICAL_0                     0x00000100U /*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     0x00000200U /*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     0x00000400U /*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     0x00000800U /*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     0x00001000U /*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     0x00002000U /*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     0x00004000U /*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     0x00008000U /*!<Bit 7 */
-#define  RCC_CR_HSEON                        0x00010000U
-#define  RCC_CR_HSERDY                       0x00020000U
-#define  RCC_CR_HSEBYP                       0x00040000U
-#define  RCC_CR_CSSON                        0x00080000U
-#define  RCC_CR_PLLON                        0x01000000U
-#define  RCC_CR_PLLRDY                       0x02000000U
-#define  RCC_CR_PLLI2SON                     0x04000000U
-#define  RCC_CR_PLLI2SRDY                    0x08000000U
-#define  RCC_CR_PLLSAION                     0x10000000U
-#define  RCC_CR_PLLSAIRDY                    0x20000000U
-
-/********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    0x0000003FU
-#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
-#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
-#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
-#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
-#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
-#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
-#define  RCC_PLLCFGR_PLLN                    0x00007FC0U
-#define  RCC_PLLCFGR_PLLN_0                  0x00000040U
-#define  RCC_PLLCFGR_PLLN_1                  0x00000080U
-#define  RCC_PLLCFGR_PLLN_2                  0x00000100U
-#define  RCC_PLLCFGR_PLLN_3                  0x00000200U
-#define  RCC_PLLCFGR_PLLN_4                  0x00000400U
-#define  RCC_PLLCFGR_PLLN_5                  0x00000800U
-#define  RCC_PLLCFGR_PLLN_6                  0x00001000U
-#define  RCC_PLLCFGR_PLLN_7                  0x00002000U
-#define  RCC_PLLCFGR_PLLN_8                  0x00004000U
-#define  RCC_PLLCFGR_PLLP                    0x00030000U
-#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
-#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
-#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
-#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
-#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
-#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
-#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
-#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
-
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-/*!< SW configuration */
-#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
-#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
-#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
-
-#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
-
-/*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     0x001F0000U
-#define  RCC_CFGR_RTCPRE_0                   0x00010000U
-#define  RCC_CFGR_RTCPRE_1                   0x00020000U
-#define  RCC_CFGR_RTCPRE_2                   0x00040000U
-#define  RCC_CFGR_RTCPRE_3                   0x00080000U
-#define  RCC_CFGR_RTCPRE_4                   0x00100000U
-
-/*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       0x00600000U
-#define  RCC_CFGR_MCO1_0                     0x00200000U
-#define  RCC_CFGR_MCO1_1                     0x00400000U
-
-#define  RCC_CFGR_I2SSRC                     0x00800000U
-
-#define  RCC_CFGR_MCO1PRE                    0x07000000U
-#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
-#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
-#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
-
-#define  RCC_CFGR_MCO2PRE                    0x38000000U
-#define  RCC_CFGR_MCO2PRE_0                  0x08000000U
-#define  RCC_CFGR_MCO2PRE_1                  0x10000000U
-#define  RCC_CFGR_MCO2PRE_2                  0x20000000U
-
-#define  RCC_CFGR_MCO2                       0xC0000000U
-#define  RCC_CFGR_MCO2_0                     0x40000000U
-#define  RCC_CFGR_MCO2_1                     0x80000000U
-
-/********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     0x00000001U
-#define  RCC_CIR_LSERDYF                     0x00000002U
-#define  RCC_CIR_HSIRDYF                     0x00000004U
-#define  RCC_CIR_HSERDYF                     0x00000008U
-#define  RCC_CIR_PLLRDYF                     0x00000010U
-#define  RCC_CIR_PLLI2SRDYF                  0x00000020U
-#define  RCC_CIR_PLLSAIRDYF                  0x00000040U
-#define  RCC_CIR_CSSF                        0x00000080U
-#define  RCC_CIR_LSIRDYIE                    0x00000100U
-#define  RCC_CIR_LSERDYIE                    0x00000200U
-#define  RCC_CIR_HSIRDYIE                    0x00000400U
-#define  RCC_CIR_HSERDYIE                    0x00000800U
-#define  RCC_CIR_PLLRDYIE                    0x00001000U
-#define  RCC_CIR_PLLI2SRDYIE                 0x00002000U
-#define  RCC_CIR_PLLSAIRDYIE                 0x00004000U
-#define  RCC_CIR_LSIRDYC                     0x00010000U
-#define  RCC_CIR_LSERDYC                     0x00020000U
-#define  RCC_CIR_HSIRDYC                     0x00040000U
-#define  RCC_CIR_HSERDYC                     0x00080000U
-#define  RCC_CIR_PLLRDYC                     0x00100000U
-#define  RCC_CIR_PLLI2SRDYC                  0x00200000U
-#define  RCC_CIR_PLLSAIRDYC                  0x00400000U
-#define  RCC_CIR_CSSC                        0x00800000U
-
-/********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
-#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
-#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
-#define  RCC_AHB1RSTR_GPIODRST               0x00000008U
-#define  RCC_AHB1RSTR_GPIOERST               0x00000010U
-#define  RCC_AHB1RSTR_GPIOFRST               0x00000020U
-#define  RCC_AHB1RSTR_GPIOGRST               0x00000040U
-#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
-#define  RCC_AHB1RSTR_GPIOIRST               0x00000100U
-#define  RCC_AHB1RSTR_GPIOJRST               0x00000200U
-#define  RCC_AHB1RSTR_GPIOKRST               0x00000400U
-#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
-#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
-#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
-#define  RCC_AHB1RSTR_DMA2DRST               0x00800000U
-#define  RCC_AHB1RSTR_ETHMACRST              0x02000000U
-#define  RCC_AHB1RSTR_OTGHRST                0x20000000U
-
-/********************  Bit definition for RCC_AHB2RSTR register  **************/
-#define  RCC_AHB2RSTR_DCMIRST                0x00000001U
-#define  RCC_AHB2RSTR_RNGRST                 0x00000040U
-#define  RCC_AHB2RSTR_OTGFSRST               0x00000080U
-
-/********************  Bit definition for RCC_AHB3RSTR register  **************/
-
-#define  RCC_AHB3RSTR_FMCRST                 0x00000001U
-#define  RCC_AHB3RSTR_QSPIRST                0x00000002U
-
-/********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM2RST                0x00000001U
-#define  RCC_APB1RSTR_TIM3RST                0x00000002U
-#define  RCC_APB1RSTR_TIM4RST                0x00000004U
-#define  RCC_APB1RSTR_TIM5RST                0x00000008U
-#define  RCC_APB1RSTR_TIM6RST                0x00000010U
-#define  RCC_APB1RSTR_TIM7RST                0x00000020U
-#define  RCC_APB1RSTR_TIM12RST               0x00000040U
-#define  RCC_APB1RSTR_TIM13RST               0x00000080U
-#define  RCC_APB1RSTR_TIM14RST               0x00000100U
-#define  RCC_APB1RSTR_LPTIM1RST              0x00000200U
-#define  RCC_APB1RSTR_WWDGRST                0x00000800U
-#define  RCC_APB1RSTR_SPI2RST                0x00004000U
-#define  RCC_APB1RSTR_SPI3RST                0x00008000U
-#define  RCC_APB1RSTR_SPDIFRXRST             0x00010000U
-#define  RCC_APB1RSTR_USART2RST              0x00020000U
-#define  RCC_APB1RSTR_USART3RST              0x00040000U
-#define  RCC_APB1RSTR_UART4RST               0x00080000U
-#define  RCC_APB1RSTR_UART5RST               0x00100000U
-#define  RCC_APB1RSTR_I2C1RST                0x00200000U
-#define  RCC_APB1RSTR_I2C2RST                0x00400000U
-#define  RCC_APB1RSTR_I2C3RST                0x00800000U
-#define  RCC_APB1RSTR_I2C4RST                0x01000000U
-#define  RCC_APB1RSTR_CAN1RST                0x02000000U
-#define  RCC_APB1RSTR_CAN2RST                0x04000000U
-#define  RCC_APB1RSTR_CECRST                 0x08000000U
-#define  RCC_APB1RSTR_PWRRST                 0x10000000U
-#define  RCC_APB1RSTR_DACRST                 0x20000000U
-#define  RCC_APB1RSTR_UART7RST               0x40000000U
-#define  RCC_APB1RSTR_UART8RST               0x80000000U
-
-/********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                0x00000001U
-#define  RCC_APB2RSTR_TIM8RST                0x00000002U
-#define  RCC_APB2RSTR_USART1RST              0x00000010U
-#define  RCC_APB2RSTR_USART6RST              0x00000020U
-#define  RCC_APB2RSTR_ADCRST                 0x00000100U
-#define  RCC_APB2RSTR_SDMMC1RST              0x00000800U
-#define  RCC_APB2RSTR_SPI1RST                0x00001000U
-#define  RCC_APB2RSTR_SPI4RST                0x00002000U
-#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
-#define  RCC_APB2RSTR_TIM9RST                0x00010000U
-#define  RCC_APB2RSTR_TIM10RST               0x00020000U
-#define  RCC_APB2RSTR_TIM11RST               0x00040000U
-#define  RCC_APB2RSTR_SPI5RST                0x00100000U
-#define  RCC_APB2RSTR_SPI6RST                0x00200000U
-#define  RCC_APB2RSTR_SAI1RST                0x00400000U
-#define  RCC_APB2RSTR_SAI2RST                0x00800000U
-#define  RCC_APB2RSTR_LTDCRST                0x04000000U
-
-/********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
-#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
-#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
-#define  RCC_AHB1ENR_GPIODEN                 0x00000008U
-#define  RCC_AHB1ENR_GPIOEEN                 0x00000010U
-#define  RCC_AHB1ENR_GPIOFEN                 0x00000020U
-#define  RCC_AHB1ENR_GPIOGEN                 0x00000040U
-#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
-#define  RCC_AHB1ENR_GPIOIEN                 0x00000100U
-#define  RCC_AHB1ENR_GPIOJEN                 0x00000200U
-#define  RCC_AHB1ENR_GPIOKEN                 0x00000400U
-#define  RCC_AHB1ENR_CRCEN                   0x00001000U
-#define  RCC_AHB1ENR_BKPSRAMEN               0x00040000U
-#define  RCC_AHB1ENR_DTCMRAMEN               0x00100000U
-#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
-#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
-#define  RCC_AHB1ENR_DMA2DEN                 0x00800000U
-#define  RCC_AHB1ENR_ETHMACEN                0x02000000U
-#define  RCC_AHB1ENR_ETHMACTXEN              0x04000000U
-#define  RCC_AHB1ENR_ETHMACRXEN              0x08000000U
-#define  RCC_AHB1ENR_ETHMACPTPEN             0x10000000U
-#define  RCC_AHB1ENR_OTGHSEN                 0x20000000U
-#define  RCC_AHB1ENR_OTGHSULPIEN             0x40000000U
-
-/********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define  RCC_AHB2ENR_DCMIEN                  0x00000001U
-#define  RCC_AHB2ENR_RNGEN                   0x00000040U
-#define  RCC_AHB2ENR_OTGFSEN                 0x00000080U
-
-/********************  Bit definition for RCC_AHB3ENR register  ***************/
-#define  RCC_AHB3ENR_FMCEN                  0x00000001U
-#define  RCC_AHB3ENR_QSPIEN                 0x00000002U
-
-/********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM2EN                  0x00000001U
-#define  RCC_APB1ENR_TIM3EN                  0x00000002U
-#define  RCC_APB1ENR_TIM4EN                  0x00000004U
-#define  RCC_APB1ENR_TIM5EN                  0x00000008U
-#define  RCC_APB1ENR_TIM6EN                  0x00000010U
-#define  RCC_APB1ENR_TIM7EN                  0x00000020U
-#define  RCC_APB1ENR_TIM12EN                 0x00000040U
-#define  RCC_APB1ENR_TIM13EN                 0x00000080U
-#define  RCC_APB1ENR_TIM14EN                 0x00000100U
-#define  RCC_APB1ENR_LPTIM1EN                0x00000200U
-#define  RCC_APB1ENR_WWDGEN                  0x00000800U
-#define  RCC_APB1ENR_SPI2EN                  0x00004000U
-#define  RCC_APB1ENR_SPI3EN                  0x00008000U
-#define  RCC_APB1ENR_SPDIFRXEN               0x00010000U
-#define  RCC_APB1ENR_USART2EN                0x00020000U
-#define  RCC_APB1ENR_USART3EN                0x00040000U
-#define  RCC_APB1ENR_UART4EN                 0x00080000U
-#define  RCC_APB1ENR_UART5EN                 0x00100000U
-#define  RCC_APB1ENR_I2C1EN                  0x00200000U
-#define  RCC_APB1ENR_I2C2EN                  0x00400000U
-#define  RCC_APB1ENR_I2C3EN                  0x00800000U
-#define  RCC_APB1ENR_I2C4EN                  0x01000000U
-#define  RCC_APB1ENR_CAN1EN                  0x02000000U
-#define  RCC_APB1ENR_CAN2EN                  0x04000000U
-#define  RCC_APB1ENR_CECEN                   0x08000000U
-#define  RCC_APB1ENR_PWREN                   0x10000000U
-#define  RCC_APB1ENR_DACEN                   0x20000000U
-#define  RCC_APB1ENR_UART7EN                 0x40000000U
-#define  RCC_APB1ENR_UART8EN                 0x80000000U
-
-/********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  0x00000001U
-#define  RCC_APB2ENR_TIM8EN                  0x00000002U
-#define  RCC_APB2ENR_USART1EN                0x00000010U
-#define  RCC_APB2ENR_USART6EN                0x00000020U
-#define  RCC_APB2ENR_ADC1EN                  0x00000100U
-#define  RCC_APB2ENR_ADC2EN                  0x00000200U
-#define  RCC_APB2ENR_ADC3EN                  0x00000400U
-#define  RCC_APB2ENR_SDMMC1EN                0x00000800U
-#define  RCC_APB2ENR_SPI1EN                  0x00001000U
-#define  RCC_APB2ENR_SPI4EN                  0x00002000U
-#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
-#define  RCC_APB2ENR_TIM9EN                  0x00010000U
-#define  RCC_APB2ENR_TIM10EN                 0x00020000U
-#define  RCC_APB2ENR_TIM11EN                 0x00040000U
-#define  RCC_APB2ENR_SPI5EN                  0x00100000U
-#define  RCC_APB2ENR_SPI6EN                  0x00200000U
-#define  RCC_APB2ENR_SAI1EN                  0x00400000U
-#define  RCC_APB2ENR_SAI2EN                  0x00800000U
-#define  RCC_APB2ENR_LTDCEN                  0x04000000U
-
-/********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
-#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
-#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
-#define  RCC_AHB1LPENR_GPIODLPEN             0x00000008U
-#define  RCC_AHB1LPENR_GPIOELPEN             0x00000010U
-#define  RCC_AHB1LPENR_GPIOFLPEN             0x00000020U
-#define  RCC_AHB1LPENR_GPIOGLPEN             0x00000040U
-#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
-#define  RCC_AHB1LPENR_GPIOILPEN             0x00000100U
-#define  RCC_AHB1LPENR_GPIOJLPEN             0x00000200U
-#define  RCC_AHB1LPENR_GPIOKLPEN             0x00000400U
-#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
-#define  RCC_AHB1LPENR_AXILPEN               0x00002000U
-#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
-#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
-#define  RCC_AHB1LPENR_SRAM2LPEN             0x00020000U
-#define  RCC_AHB1LPENR_BKPSRAMLPEN           0x00040000U
-#define  RCC_AHB1LPENR_DTCMLPEN              0x00100000U
-#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
-#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
-#define  RCC_AHB1LPENR_DMA2DLPEN             0x00800000U
-#define  RCC_AHB1LPENR_ETHMACLPEN            0x02000000U
-#define  RCC_AHB1LPENR_ETHMACTXLPEN          0x04000000U
-#define  RCC_AHB1LPENR_ETHMACRXLPEN          0x08000000U
-#define  RCC_AHB1LPENR_ETHMACPTPLPEN         0x10000000U
-#define  RCC_AHB1LPENR_OTGHSLPEN             0x20000000U
-#define  RCC_AHB1LPENR_OTGHSULPILPEN         0x40000000U
-
-/********************  Bit definition for RCC_AHB2LPENR register  *************/
-#define  RCC_AHB2LPENR_DCMILPEN              0x00000001U
-#define  RCC_AHB2LPENR_RNGLPEN               0x00000040U
-#define  RCC_AHB2LPENR_OTGFSLPEN             0x00000080U
-
-/********************  Bit definition for RCC_AHB3LPENR register  *************/
-#define  RCC_AHB3LPENR_FMCLPEN               0x00000001U
-#define  RCC_AHB3LPENR_QSPILPEN              0x00000002U
-/********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM2LPEN              0x00000001U
-#define  RCC_APB1LPENR_TIM3LPEN              0x00000002U
-#define  RCC_APB1LPENR_TIM4LPEN              0x00000004U
-#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
-#define  RCC_APB1LPENR_TIM6LPEN              0x00000010U
-#define  RCC_APB1LPENR_TIM7LPEN              0x00000020U
-#define  RCC_APB1LPENR_TIM12LPEN             0x00000040U
-#define  RCC_APB1LPENR_TIM13LPEN             0x00000080U
-#define  RCC_APB1LPENR_TIM14LPEN             0x00000100U
-#define  RCC_APB1LPENR_LPTIM1LPEN            0x00000200U
-#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
-#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U
-#define  RCC_APB1LPENR_SPI3LPEN              0x00008000U
-#define  RCC_APB1LPENR_SPDIFRXLPEN           0x00010000U
-#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
-#define  RCC_APB1LPENR_USART3LPEN            0x00040000U
-#define  RCC_APB1LPENR_UART4LPEN             0x00080000U
-#define  RCC_APB1LPENR_UART5LPEN             0x00100000U
-#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
-#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
-#define  RCC_APB1LPENR_I2C3LPEN              0x00800000U
-#define  RCC_APB1LPENR_I2C4LPEN              0x01000000U
-#define  RCC_APB1LPENR_CAN1LPEN              0x02000000U
-#define  RCC_APB1LPENR_CAN2LPEN              0x04000000U
-#define  RCC_APB1LPENR_CECLPEN               0x08000000U
-#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
-#define  RCC_APB1LPENR_DACLPEN               0x20000000U
-#define  RCC_APB1LPENR_UART7LPEN             0x40000000U
-#define  RCC_APB1LPENR_UART8LPEN             0x80000000U
-
-/********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
-#define  RCC_APB2LPENR_TIM8LPEN              0x00000002U
-#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
-#define  RCC_APB2LPENR_USART6LPEN            0x00000020U
-#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
-#define  RCC_APB2LPENR_ADC2LPEN              0x00000200U
-#define  RCC_APB2LPENR_ADC3LPEN              0x00000400U
-#define  RCC_APB2LPENR_SDMMC1LPEN            0x00000800U
-#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
-#define  RCC_APB2LPENR_SPI4LPEN              0x00002000U
-#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
-#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
-#define  RCC_APB2LPENR_TIM10LPEN             0x00020000U
-#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
-#define  RCC_APB2LPENR_SPI5LPEN              0x00100000U
-#define  RCC_APB2LPENR_SPI6LPEN              0x00200000U
-#define  RCC_APB2LPENR_SAI1LPEN              0x00400000U
-#define  RCC_APB2LPENR_SAI2LPEN              0x00800000U
-#define  RCC_APB2LPENR_LTDCLPEN              0x04000000U
-
-/********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      0x00000001U
-#define  RCC_BDCR_LSERDY                     0x00000002U
-#define  RCC_BDCR_LSEBYP                     0x00000004U
-#define  RCC_BDCR_LSEDRV                     0x00000018U
-#define  RCC_BDCR_LSEDRV_0                   0x00000008U
-#define  RCC_BDCR_LSEDRV_1                   0x00000010U
-#define  RCC_BDCR_RTCSEL                     0x00000300U
-#define  RCC_BDCR_RTCSEL_0                   0x00000100U
-#define  RCC_BDCR_RTCSEL_1                   0x00000200U
-#define  RCC_BDCR_RTCEN                      0x00008000U
-#define  RCC_BDCR_BDRST                      0x00010000U
-
-/********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       0x00000001U
-#define  RCC_CSR_LSIRDY                      0x00000002U
-#define  RCC_CSR_RMVF                        0x01000000U
-#define  RCC_CSR_BORRSTF                     0x02000000U
-#define  RCC_CSR_PINRSTF                     0x04000000U
-#define  RCC_CSR_PORRSTF                     0x08000000U
-#define  RCC_CSR_SFTRSTF                     0x10000000U
-#define  RCC_CSR_IWDGRSTF                    0x20000000U
-#define  RCC_CSR_WWDGRSTF                    0x40000000U
-#define  RCC_CSR_LPWRRSTF                    0x80000000U
-
-/********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    0x00001FFFU
-#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
-#define  RCC_SSCGR_SPREADSEL                 0x40000000U
-#define  RCC_SSCGR_SSCGEN                    0x80000000U
-
-/********************  Bit definition for RCC_PLLI2SCFGR register  ************/
-#define  RCC_PLLI2SCFGR_PLLI2SN              0x00007FC0U
-#define  RCC_PLLI2SCFGR_PLLI2SN_0            0x00000040U
-#define  RCC_PLLI2SCFGR_PLLI2SN_1            0x00000080U
-#define  RCC_PLLI2SCFGR_PLLI2SN_2            0x00000100U
-#define  RCC_PLLI2SCFGR_PLLI2SN_3            0x00000200U
-#define  RCC_PLLI2SCFGR_PLLI2SN_4            0x00000400U
-#define  RCC_PLLI2SCFGR_PLLI2SN_5            0x00000800U
-#define  RCC_PLLI2SCFGR_PLLI2SN_6            0x00001000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_7            0x00002000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_8            0x00004000U
-#define  RCC_PLLI2SCFGR_PLLI2SP              0x00030000U
-#define  RCC_PLLI2SCFGR_PLLI2SP_0            0x00010000U
-#define  RCC_PLLI2SCFGR_PLLI2SP_1            0x00020000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ              0x0F000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_0            0x01000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_1            0x02000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_2            0x04000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_3            0x08000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR              0x70000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_0            0x10000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_1            0x20000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_2            0x40000000U
-
-/********************  Bit definition for RCC_PLLSAICFGR register  ************/
-#define  RCC_PLLSAICFGR_PLLSAIN              0x00007FC0U
-#define  RCC_PLLSAICFGR_PLLSAIN_0            0x00000040U
-#define  RCC_PLLSAICFGR_PLLSAIN_1            0x00000080U
-#define  RCC_PLLSAICFGR_PLLSAIN_2            0x00000100U
-#define  RCC_PLLSAICFGR_PLLSAIN_3            0x00000200U
-#define  RCC_PLLSAICFGR_PLLSAIN_4            0x00000400U
-#define  RCC_PLLSAICFGR_PLLSAIN_5            0x00000800U
-#define  RCC_PLLSAICFGR_PLLSAIN_6            0x00001000U
-#define  RCC_PLLSAICFGR_PLLSAIN_7            0x00002000U
-#define  RCC_PLLSAICFGR_PLLSAIN_8            0x00004000U
-#define  RCC_PLLSAICFGR_PLLSAIP              0x00030000U
-#define  RCC_PLLSAICFGR_PLLSAIP_0            0x00010000U
-#define  RCC_PLLSAICFGR_PLLSAIP_1            0x00020000U
-#define  RCC_PLLSAICFGR_PLLSAIQ              0x0F000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_0            0x01000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_1            0x02000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_2            0x04000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_3            0x08000000U
-#define  RCC_PLLSAICFGR_PLLSAIR              0x70000000U
-#define  RCC_PLLSAICFGR_PLLSAIR_0            0x10000000U
-#define  RCC_PLLSAICFGR_PLLSAIR_1            0x20000000U
-#define  RCC_PLLSAICFGR_PLLSAIR_2            0x40000000U
-
-/********************  Bit definition for RCC_DCKCFGR1 register  ***************/
-#define  RCC_DCKCFGR1_PLLI2SDIVQ             0x0000001FU
-#define  RCC_DCKCFGR1_PLLI2SDIVQ_0           0x00000001U
-#define  RCC_DCKCFGR1_PLLI2SDIVQ_1           0x00000002U
-#define  RCC_DCKCFGR1_PLLI2SDIVQ_2           0x00000004U
-#define  RCC_DCKCFGR1_PLLI2SDIVQ_3           0x00000008U
-#define  RCC_DCKCFGR1_PLLI2SDIVQ_4           0x00000010U
-
-#define  RCC_DCKCFGR1_PLLSAIDIVQ             0x00001F00U
-#define  RCC_DCKCFGR1_PLLSAIDIVQ_0           0x00000100U
-#define  RCC_DCKCFGR1_PLLSAIDIVQ_1           0x00000200U
-#define  RCC_DCKCFGR1_PLLSAIDIVQ_2           0x00000400U
-#define  RCC_DCKCFGR1_PLLSAIDIVQ_3           0x00000800U
-#define  RCC_DCKCFGR1_PLLSAIDIVQ_4           0x00001000U
-
-#define  RCC_DCKCFGR1_PLLSAIDIVR             0x00030000U
-#define  RCC_DCKCFGR1_PLLSAIDIVR_0           0x00010000U
-#define  RCC_DCKCFGR1_PLLSAIDIVR_1           0x00020000U
-
-#define  RCC_DCKCFGR1_SAI1SEL                0x00300000U
-#define  RCC_DCKCFGR1_SAI1SEL_0              0x00100000U
-#define  RCC_DCKCFGR1_SAI1SEL_1              0x00200000U
-
-#define  RCC_DCKCFGR1_SAI2SEL                0x00C00000U
-#define  RCC_DCKCFGR1_SAI2SEL_0              0x00400000U
-#define  RCC_DCKCFGR1_SAI2SEL_1              0x00800000U
-
-#define  RCC_DCKCFGR1_TIMPRE                 0x01000000U
-
-/********************  Bit definition for RCC_DCKCFGR2 register  ***************/
-#define  RCC_DCKCFGR2_USART1SEL              0x00000003U
-#define  RCC_DCKCFGR2_USART1SEL_0            0x00000001U
-#define  RCC_DCKCFGR2_USART1SEL_1            0x00000002U
-#define  RCC_DCKCFGR2_USART2SEL              0x0000000CU
-#define  RCC_DCKCFGR2_USART2SEL_0            0x00000004U
-#define  RCC_DCKCFGR2_USART2SEL_1            0x00000008U
-#define  RCC_DCKCFGR2_USART3SEL              0x00000030U
-#define  RCC_DCKCFGR2_USART3SEL_0            0x00000010U
-#define  RCC_DCKCFGR2_USART3SEL_1            0x00000020U
-#define  RCC_DCKCFGR2_UART4SEL               0x000000C0U
-#define  RCC_DCKCFGR2_UART4SEL_0             0x00000040U
-#define  RCC_DCKCFGR2_UART4SEL_1             0x00000080U
-#define  RCC_DCKCFGR2_UART5SEL               0x00000300U
-#define  RCC_DCKCFGR2_UART5SEL_0             0x00000100U
-#define  RCC_DCKCFGR2_UART5SEL_1             0x00000200U
-#define  RCC_DCKCFGR2_USART6SEL              0x00000C00U
-#define  RCC_DCKCFGR2_USART6SEL_0            0x00000400U
-#define  RCC_DCKCFGR2_USART6SEL_1            0x00000800U
-#define  RCC_DCKCFGR2_UART7SEL               0x00003000U
-#define  RCC_DCKCFGR2_UART7SEL_0             0x00001000U
-#define  RCC_DCKCFGR2_UART7SEL_1             0x00002000U
-#define  RCC_DCKCFGR2_UART8SEL               0x0000C000U
-#define  RCC_DCKCFGR2_UART8SEL_0             0x00004000U
-#define  RCC_DCKCFGR2_UART8SEL_1             0x00008000U
-#define  RCC_DCKCFGR2_I2C1SEL                0x00030000U
-#define  RCC_DCKCFGR2_I2C1SEL_0              0x00010000U
-#define  RCC_DCKCFGR2_I2C1SEL_1              0x00020000U
-#define  RCC_DCKCFGR2_I2C2SEL                0x000C0000U
-#define  RCC_DCKCFGR2_I2C2SEL_0              0x00040000U
-#define  RCC_DCKCFGR2_I2C2SEL_1              0x00080000U
-#define  RCC_DCKCFGR2_I2C3SEL                0x00300000U
-#define  RCC_DCKCFGR2_I2C3SEL_0              0x00100000U
-#define  RCC_DCKCFGR2_I2C3SEL_1              0x00200000U
-#define  RCC_DCKCFGR2_I2C4SEL                0x00C00000U
-#define  RCC_DCKCFGR2_I2C4SEL_0              0x00400000U
-#define  RCC_DCKCFGR2_I2C4SEL_1              0x00800000U
-#define  RCC_DCKCFGR2_LPTIM1SEL              0x03000000U
-#define  RCC_DCKCFGR2_LPTIM1SEL_0            0x01000000U
-#define  RCC_DCKCFGR2_LPTIM1SEL_1            0x02000000U
-#define  RCC_DCKCFGR2_CECSEL                 0x04000000U
-#define  RCC_DCKCFGR2_CK48MSEL               0x08000000U
-#define  RCC_DCKCFGR2_SDMMC1SEL              0x10000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    RNG                                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN                         0x00000004U
-#define RNG_CR_IE                            0x00000008U
-
-/********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY                          0x00000001U
-#define RNG_SR_CECS                          0x00000002U
-#define RNG_SR_SECS                          0x00000004U
-#define RNG_SR_CEIS                          0x00000020U
-#define RNG_SR_SEIS                          0x00000040U
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            0x00400000U
-#define RTC_TR_HT                            0x00300000U
-#define RTC_TR_HT_0                          0x00100000U
-#define RTC_TR_HT_1                          0x00200000U
-#define RTC_TR_HU                            0x000F0000U
-#define RTC_TR_HU_0                          0x00010000U
-#define RTC_TR_HU_1                          0x00020000U
-#define RTC_TR_HU_2                          0x00040000U
-#define RTC_TR_HU_3                          0x00080000U
-#define RTC_TR_MNT                           0x00007000U
-#define RTC_TR_MNT_0                         0x00001000U
-#define RTC_TR_MNT_1                         0x00002000U
-#define RTC_TR_MNT_2                         0x00004000U
-#define RTC_TR_MNU                           0x00000F00U
-#define RTC_TR_MNU_0                         0x00000100U
-#define RTC_TR_MNU_1                         0x00000200U
-#define RTC_TR_MNU_2                         0x00000400U
-#define RTC_TR_MNU_3                         0x00000800U
-#define RTC_TR_ST                            0x00000070U
-#define RTC_TR_ST_0                          0x00000010U
-#define RTC_TR_ST_1                          0x00000020U
-#define RTC_TR_ST_2                          0x00000040U
-#define RTC_TR_SU                            0x0000000FU
-#define RTC_TR_SU_0                          0x00000001U
-#define RTC_TR_SU_1                          0x00000002U
-#define RTC_TR_SU_2                          0x00000004U
-#define RTC_TR_SU_3                          0x00000008U
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            0x00F00000U
-#define RTC_DR_YT_0                          0x00100000U
-#define RTC_DR_YT_1                          0x00200000U
-#define RTC_DR_YT_2                          0x00400000U
-#define RTC_DR_YT_3                          0x00800000U
-#define RTC_DR_YU                            0x000F0000U
-#define RTC_DR_YU_0                          0x00010000U
-#define RTC_DR_YU_1                          0x00020000U
-#define RTC_DR_YU_2                          0x00040000U
-#define RTC_DR_YU_3                          0x00080000U
-#define RTC_DR_WDU                           0x0000E000U
-#define RTC_DR_WDU_0                         0x00002000U
-#define RTC_DR_WDU_1                         0x00004000U
-#define RTC_DR_WDU_2                         0x00008000U
-#define RTC_DR_MT                            0x00001000U
-#define RTC_DR_MU                            0x00000F00U
-#define RTC_DR_MU_0                          0x00000100U
-#define RTC_DR_MU_1                          0x00000200U
-#define RTC_DR_MU_2                          0x00000400U
-#define RTC_DR_MU_3                          0x00000800U
-#define RTC_DR_DT                            0x00000030U
-#define RTC_DR_DT_0                          0x00000010U
-#define RTC_DR_DT_1                          0x00000020U
-#define RTC_DR_DU                            0x0000000FU
-#define RTC_DR_DU_0                          0x00000001U
-#define RTC_DR_DU_1                          0x00000002U
-#define RTC_DR_DU_2                          0x00000004U
-#define RTC_DR_DU_3                          0x00000008U
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_ITSE                          0x01000000U
-#define RTC_CR_COE                           0x00800000U
-#define RTC_CR_OSEL                          0x00600000U
-#define RTC_CR_OSEL_0                        0x00200000U
-#define RTC_CR_OSEL_1                        0x00400000U
-#define RTC_CR_POL                           0x00100000U
-#define RTC_CR_COSEL                         0x00080000U
-#define RTC_CR_BKP                           0x00040000U
-#define RTC_CR_SUB1H                         0x00020000U
-#define RTC_CR_ADD1H                         0x00010000U
-#define RTC_CR_TSIE                          0x00008000U
-#define RTC_CR_WUTIE                         0x00004000U
-#define RTC_CR_ALRBIE                        0x00002000U
-#define RTC_CR_ALRAIE                        0x00001000U
-#define RTC_CR_TSE                           0x00000800U
-#define RTC_CR_WUTE                          0x00000400U
-#define RTC_CR_ALRBE                         0x00000200U
-#define RTC_CR_ALRAE                         0x00000100U
-#define RTC_CR_FMT                           0x00000040U
-#define RTC_CR_BYPSHAD                       0x00000020U
-#define RTC_CR_REFCKON                       0x00000010U
-#define RTC_CR_TSEDGE                        0x00000008U
-#define RTC_CR_WUCKSEL                       0x00000007U
-#define RTC_CR_WUCKSEL_0                     0x00000001U
-#define RTC_CR_WUCKSEL_1                     0x00000002U
-#define RTC_CR_WUCKSEL_2                     0x00000004U
-
-/* Legacy define */
-#define RTC_CR_BCK                           RTC_CR_BKP
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_ITSF                         0x00020000U
-#define RTC_ISR_RECALPF                      0x00010000U
-#define RTC_ISR_TAMP3F                       0x00008000U
-#define RTC_ISR_TAMP2F                       0x00004000U
-#define RTC_ISR_TAMP1F                       0x00002000U
-#define RTC_ISR_TSOVF                        0x00001000U
-#define RTC_ISR_TSF                          0x00000800U
-#define RTC_ISR_WUTF                         0x00000400U
-#define RTC_ISR_ALRBF                        0x00000200U
-#define RTC_ISR_ALRAF                        0x00000100U
-#define RTC_ISR_INIT                         0x00000080U
-#define RTC_ISR_INITF                        0x00000040U
-#define RTC_ISR_RSF                          0x00000020U
-#define RTC_ISR_INITS                        0x00000010U
-#define RTC_ISR_SHPF                         0x00000008U
-#define RTC_ISR_WUTWF                        0x00000004U
-#define RTC_ISR_ALRBWF                       0x00000002U
-#define RTC_ISR_ALRAWF                       0x00000001U
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    0x007F0000U
-#define RTC_PRER_PREDIV_S                    0x00007FFFU
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         0x0000FFFFU
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      0x80000000U
-#define RTC_ALRMAR_WDSEL                     0x40000000U
-#define RTC_ALRMAR_DT                        0x30000000U
-#define RTC_ALRMAR_DT_0                      0x10000000U
-#define RTC_ALRMAR_DT_1                      0x20000000U
-#define RTC_ALRMAR_DU                        0x0F000000U
-#define RTC_ALRMAR_DU_0                      0x01000000U
-#define RTC_ALRMAR_DU_1                      0x02000000U
-#define RTC_ALRMAR_DU_2                      0x04000000U
-#define RTC_ALRMAR_DU_3                      0x08000000U
-#define RTC_ALRMAR_MSK3                      0x00800000U
-#define RTC_ALRMAR_PM                        0x00400000U
-#define RTC_ALRMAR_HT                        0x00300000U
-#define RTC_ALRMAR_HT_0                      0x00100000U
-#define RTC_ALRMAR_HT_1                      0x00200000U
-#define RTC_ALRMAR_HU                        0x000F0000U
-#define RTC_ALRMAR_HU_0                      0x00010000U
-#define RTC_ALRMAR_HU_1                      0x00020000U
-#define RTC_ALRMAR_HU_2                      0x00040000U
-#define RTC_ALRMAR_HU_3                      0x00080000U
-#define RTC_ALRMAR_MSK2                      0x00008000U
-#define RTC_ALRMAR_MNT                       0x00007000U
-#define RTC_ALRMAR_MNT_0                     0x00001000U
-#define RTC_ALRMAR_MNT_1                     0x00002000U
-#define RTC_ALRMAR_MNT_2                     0x00004000U
-#define RTC_ALRMAR_MNU                       0x00000F00U
-#define RTC_ALRMAR_MNU_0                     0x00000100U
-#define RTC_ALRMAR_MNU_1                     0x00000200U
-#define RTC_ALRMAR_MNU_2                     0x00000400U
-#define RTC_ALRMAR_MNU_3                     0x00000800U
-#define RTC_ALRMAR_MSK1                      0x00000080U
-#define RTC_ALRMAR_ST                        0x00000070U
-#define RTC_ALRMAR_ST_0                      0x00000010U
-#define RTC_ALRMAR_ST_1                      0x00000020U
-#define RTC_ALRMAR_ST_2                      0x00000040U
-#define RTC_ALRMAR_SU                        0x0000000FU
-#define RTC_ALRMAR_SU_0                      0x00000001U
-#define RTC_ALRMAR_SU_1                      0x00000002U
-#define RTC_ALRMAR_SU_2                      0x00000004U
-#define RTC_ALRMAR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      0x80000000U
-#define RTC_ALRMBR_WDSEL                     0x40000000U
-#define RTC_ALRMBR_DT                        0x30000000U
-#define RTC_ALRMBR_DT_0                      0x10000000U
-#define RTC_ALRMBR_DT_1                      0x20000000U
-#define RTC_ALRMBR_DU                        0x0F000000U
-#define RTC_ALRMBR_DU_0                      0x01000000U
-#define RTC_ALRMBR_DU_1                      0x02000000U
-#define RTC_ALRMBR_DU_2                      0x04000000U
-#define RTC_ALRMBR_DU_3                      0x08000000U
-#define RTC_ALRMBR_MSK3                      0x00800000U
-#define RTC_ALRMBR_PM                        0x00400000U
-#define RTC_ALRMBR_HT                        0x00300000U
-#define RTC_ALRMBR_HT_0                      0x00100000U
-#define RTC_ALRMBR_HT_1                      0x00200000U
-#define RTC_ALRMBR_HU                        0x000F0000U
-#define RTC_ALRMBR_HU_0                      0x00010000U
-#define RTC_ALRMBR_HU_1                      0x00020000U
-#define RTC_ALRMBR_HU_2                      0x00040000U
-#define RTC_ALRMBR_HU_3                      0x00080000U
-#define RTC_ALRMBR_MSK2                      0x00008000U
-#define RTC_ALRMBR_MNT                       0x00007000U
-#define RTC_ALRMBR_MNT_0                     0x00001000U
-#define RTC_ALRMBR_MNT_1                     0x00002000U
-#define RTC_ALRMBR_MNT_2                     0x00004000U
-#define RTC_ALRMBR_MNU                       0x00000F00U
-#define RTC_ALRMBR_MNU_0                     0x00000100U
-#define RTC_ALRMBR_MNU_1                     0x00000200U
-#define RTC_ALRMBR_MNU_2                     0x00000400U
-#define RTC_ALRMBR_MNU_3                     0x00000800U
-#define RTC_ALRMBR_MSK1                      0x00000080U
-#define RTC_ALRMBR_ST                        0x00000070U
-#define RTC_ALRMBR_ST_0                      0x00000010U
-#define RTC_ALRMBR_ST_1                      0x00000020U
-#define RTC_ALRMBR_ST_2                      0x00000040U
-#define RTC_ALRMBR_SU                        0x0000000FU
-#define RTC_ALRMBR_SU_0                      0x00000001U
-#define RTC_ALRMBR_SU_1                      0x00000002U
-#define RTC_ALRMBR_SU_2                      0x00000004U
-#define RTC_ALRMBR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          0x000000FFU
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           0x0000FFFFU
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     0x00007FFFU
-#define RTC_SHIFTR_ADD1S                     0x80000000U
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          0x00400000U
-#define RTC_TSTR_HT                          0x00300000U
-#define RTC_TSTR_HT_0                        0x00100000U
-#define RTC_TSTR_HT_1                        0x00200000U
-#define RTC_TSTR_HU                          0x000F0000U
-#define RTC_TSTR_HU_0                        0x00010000U
-#define RTC_TSTR_HU_1                        0x00020000U
-#define RTC_TSTR_HU_2                        0x00040000U
-#define RTC_TSTR_HU_3                        0x00080000U
-#define RTC_TSTR_MNT                         0x00007000U
-#define RTC_TSTR_MNT_0                       0x00001000U
-#define RTC_TSTR_MNT_1                       0x00002000U
-#define RTC_TSTR_MNT_2                       0x00004000U
-#define RTC_TSTR_MNU                         0x00000F00U
-#define RTC_TSTR_MNU_0                       0x00000100U
-#define RTC_TSTR_MNU_1                       0x00000200U
-#define RTC_TSTR_MNU_2                       0x00000400U
-#define RTC_TSTR_MNU_3                       0x00000800U
-#define RTC_TSTR_ST                          0x00000070U
-#define RTC_TSTR_ST_0                        0x00000010U
-#define RTC_TSTR_ST_1                        0x00000020U
-#define RTC_TSTR_ST_2                        0x00000040U
-#define RTC_TSTR_SU                          0x0000000FU
-#define RTC_TSTR_SU_0                        0x00000001U
-#define RTC_TSTR_SU_1                        0x00000002U
-#define RTC_TSTR_SU_2                        0x00000004U
-#define RTC_TSTR_SU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         0x0000E000U
-#define RTC_TSDR_WDU_0                       0x00002000U
-#define RTC_TSDR_WDU_1                       0x00004000U
-#define RTC_TSDR_WDU_2                       0x00008000U
-#define RTC_TSDR_MT                          0x00001000U
-#define RTC_TSDR_MU                          0x00000F00U
-#define RTC_TSDR_MU_0                        0x00000100U
-#define RTC_TSDR_MU_1                        0x00000200U
-#define RTC_TSDR_MU_2                        0x00000400U
-#define RTC_TSDR_MU_3                        0x00000800U
-#define RTC_TSDR_DT                          0x00000030U
-#define RTC_TSDR_DT_0                        0x00000010U
-#define RTC_TSDR_DT_1                        0x00000020U
-#define RTC_TSDR_DU                          0x0000000FU
-#define RTC_TSDR_DU_0                        0x00000001U
-#define RTC_TSDR_DU_1                        0x00000002U
-#define RTC_TSDR_DU_2                        0x00000004U
-#define RTC_TSDR_DU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        0x00008000U
-#define RTC_CALR_CALW8                       0x00004000U
-#define RTC_CALR_CALW16                      0x00002000U
-#define RTC_CALR_CALM                        0x000001FFU
-#define RTC_CALR_CALM_0                      0x00000001U
-#define RTC_CALR_CALM_1                      0x00000002U
-#define RTC_CALR_CALM_2                      0x00000004U
-#define RTC_CALR_CALM_3                      0x00000008U
-#define RTC_CALR_CALM_4                      0x00000010U
-#define RTC_CALR_CALM_5                      0x00000020U
-#define RTC_CALR_CALM_6                      0x00000040U
-#define RTC_CALR_CALM_7                      0x00000080U
-#define RTC_CALR_CALM_8                      0x00000100U
-
-/********************  Bits definition for RTC_TAMPCR register  ****************/
-#define RTC_TAMPCR_TAMP3MF                   0x01000000U
-#define RTC_TAMPCR_TAMP3NOERASE              0x00800000U
-#define RTC_TAMPCR_TAMP3IE                   0x00400000U
-#define RTC_TAMPCR_TAMP2MF                   0x00200000U
-#define RTC_TAMPCR_TAMP2NOERASE              0x00100000U
-#define RTC_TAMPCR_TAMP2IE                   0x00080000U
-#define RTC_TAMPCR_TAMP1MF                   0x00040000U
-#define RTC_TAMPCR_TAMP1NOERASE              0x00020000U
-#define RTC_TAMPCR_TAMP1IE                   0x00010000U
-#define RTC_TAMPCR_TAMPPUDIS                 0x00008000U
-#define RTC_TAMPCR_TAMPPRCH                  0x00006000U
-#define RTC_TAMPCR_TAMPPRCH_0                0x00002000U
-#define RTC_TAMPCR_TAMPPRCH_1                0x00004000U
-#define RTC_TAMPCR_TAMPFLT                   0x00001800U
-#define RTC_TAMPCR_TAMPFLT_0                 0x00000800U
-#define RTC_TAMPCR_TAMPFLT_1                 0x00001000U
-#define RTC_TAMPCR_TAMPFREQ                  0x00000700U
-#define RTC_TAMPCR_TAMPFREQ_0                0x00000100U
-#define RTC_TAMPCR_TAMPFREQ_1                0x00000200U
-#define RTC_TAMPCR_TAMPFREQ_2                0x00000400U
-#define RTC_TAMPCR_TAMPTS                    0x00000080U
-#define RTC_TAMPCR_TAMP3TRG                  0x00000040U
-#define RTC_TAMPCR_TAMP3E                    0x00000020U
-#define RTC_TAMPCR_TAMP2TRG                  0x00000010U
-#define RTC_TAMPCR_TAMP2E                    0x00000008U
-#define RTC_TAMPCR_TAMPIE                    0x00000004U
-#define RTC_TAMPCR_TAMP1TRG                  0x00000002U
-#define RTC_TAMPCR_TAMP1E                    0x00000001U
-
-/* Legacy defines */
-#define RTC_TAMPCR_TAMP3_TRG                  RTC_TAMPCR_TAMP3TRG
-#define RTC_TAMPCR_TAMP2_TRG                  RTC_TAMPCR_TAMP2TRG
-#define RTC_TAMPCR_TAMP1_TRG                  RTC_TAMPCR_TAMP1TRG
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  0x0F000000U
-#define RTC_ALRMASSR_MASKSS_0                0x01000000U
-#define RTC_ALRMASSR_MASKSS_1                0x02000000U
-#define RTC_ALRMASSR_MASKSS_2                0x04000000U
-#define RTC_ALRMASSR_MASKSS_3                0x08000000U
-#define RTC_ALRMASSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
-#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
-#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
-#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
-#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
-#define RTC_ALRMBSSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_OR register  ****************/
-#define RTC_OR_TSINSEL                       0x00000006U
-#define RTC_OR_TSINSEL_0                     0x00000002U
-#define RTC_OR_TSINSEL_1                     0x00000004U
-#define RTC_OR_ALARMTYPE                     0x00000008U
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP20R register  ***************/
-#define RTC_BKP20R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP21R register  ***************/
-#define RTC_BKP21R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP22R register  ***************/
-#define RTC_BKP22R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP23R register  ***************/
-#define RTC_BKP23R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP24R register  ***************/
-#define RTC_BKP24R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP25R register  ***************/
-#define RTC_BKP25R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP26R register  ***************/
-#define RTC_BKP26R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP27R register  ***************/
-#define RTC_BKP27R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP28R register  ***************/
-#define RTC_BKP28R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP29R register  ***************/
-#define RTC_BKP29R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP30R register  ***************/
-#define RTC_BKP30R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP31R register  ***************/
-#define RTC_BKP31R                           0xFFFFFFFFU
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER                       0x00000020U
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Serial Audio Interface                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for SAI_GCR register  *******************/
-#define  SAI_GCR_SYNCIN                      0x00000003U        /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
-#define  SAI_GCR_SYNCIN_0                    0x00000001U        /*!<Bit 0 */
-#define  SAI_GCR_SYNCIN_1                    0x00000002U        /*!<Bit 1 */
-
-#define  SAI_GCR_SYNCOUT                     0x00000030U        /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
-#define  SAI_GCR_SYNCOUT_0                   0x00000010U        /*!<Bit 0 */
-#define  SAI_GCR_SYNCOUT_1                   0x00000020U        /*!<Bit 1 */
-
-/*******************  Bit definition for SAI_xCR1 register  *******************/
-#define  SAI_xCR1_MODE                       0x00000003U        /*!<MODE[1:0] bits (Audio Block Mode)           */
-#define  SAI_xCR1_MODE_0                     0x00000001U        /*!<Bit 0 */
-#define  SAI_xCR1_MODE_1                     0x00000002U        /*!<Bit 1 */
-
-#define  SAI_xCR1_PRTCFG                     0x0000000CU        /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
-#define  SAI_xCR1_PRTCFG_0                   0x00000004U        /*!<Bit 0 */
-#define  SAI_xCR1_PRTCFG_1                   0x00000008U        /*!<Bit 1 */
-
-#define  SAI_xCR1_DS                         0x000000E0U        /*!<DS[1:0] bits (Data Size) */
-#define  SAI_xCR1_DS_0                       0x00000020U        /*!<Bit 0 */
-#define  SAI_xCR1_DS_1                       0x00000040U        /*!<Bit 1 */
-#define  SAI_xCR1_DS_2                       0x00000080U        /*!<Bit 2 */
-
-#define  SAI_xCR1_LSBFIRST                   0x00000100U        /*!<LSB First Configuration  */
-#define  SAI_xCR1_CKSTR                      0x00000200U        /*!<ClocK STRobing edge      */
-
-#define  SAI_xCR1_SYNCEN                     0x00000C00U        /*!<SYNCEN[1:0](SYNChronization ENable) */
-#define  SAI_xCR1_SYNCEN_0                   0x00000400U        /*!<Bit 0 */
-#define  SAI_xCR1_SYNCEN_1                   0x00000800U        /*!<Bit 1 */
-
-#define  SAI_xCR1_MONO                       0x00001000U        /*!<Mono mode                  */
-#define  SAI_xCR1_OUTDRIV                    0x00002000U        /*!<Output Drive               */
-#define  SAI_xCR1_SAIEN                      0x00010000U        /*!<Audio Block enable         */
-#define  SAI_xCR1_DMAEN                      0x00020000U        /*!<DMA enable                 */
-#define  SAI_xCR1_NODIV                      0x00080000U        /*!<No Divider Configuration   */
-
-#define  SAI_xCR1_MCKDIV                     0x00F00000U        /*!<MCKDIV[3:0] (Master ClocK Divider)  */
-#define  SAI_xCR1_MCKDIV_0                   0x00100000U        /*!<Bit 0  */
-#define  SAI_xCR1_MCKDIV_1                   0x00200000U        /*!<Bit 1  */
-#define  SAI_xCR1_MCKDIV_2                   0x00400000U        /*!<Bit 2  */
-#define  SAI_xCR1_MCKDIV_3                   0x00800000U        /*!<Bit 3  */
-
-/*******************  Bit definition for SAI_xCR2 register  *******************/
-#define  SAI_xCR2_FTH                        0x00000007U        /*!<FTH[2:0](Fifo THreshold)  */
-#define  SAI_xCR2_FTH_0                      0x00000001U        /*!<Bit 0 */
-#define  SAI_xCR2_FTH_1                      0x00000002U        /*!<Bit 1 */
-#define  SAI_xCR2_FTH_2                      0x00000004U        /*!<Bit 2 */
-
-#define  SAI_xCR2_FFLUSH                     0x00000008U        /*!<Fifo FLUSH                       */
-#define  SAI_xCR2_TRIS                       0x00000010U        /*!<TRIState Management on data line */
-#define  SAI_xCR2_MUTE                       0x00000020U        /*!<Mute mode                        */
-#define  SAI_xCR2_MUTEVAL                    0x00000040U        /*!<Muate value                      */
-
-#define  SAI_xCR2_MUTECNT                    0x00001F80U       /*!<MUTECNT[5:0] (MUTE counter) */
-#define  SAI_xCR2_MUTECNT_0                  0x00000080U        /*!<Bit 0 */
-#define  SAI_xCR2_MUTECNT_1                  0x00000100U        /*!<Bit 1 */
-#define  SAI_xCR2_MUTECNT_2                  0x00000200U        /*!<Bit 2 */
-#define  SAI_xCR2_MUTECNT_3                  0x00000400U        /*!<Bit 3 */
-#define  SAI_xCR2_MUTECNT_4                  0x00000800U        /*!<Bit 4 */
-#define  SAI_xCR2_MUTECNT_5                  0x00001000U        /*!<Bit 5 */
-
-#define  SAI_xCR2_CPL                        0x00002000U        /*!< Complement Bit             */
-
-#define  SAI_xCR2_COMP                       0x0000C000U        /*!<COMP[1:0] (Companding mode) */
-#define  SAI_xCR2_COMP_0                     0x00004000U        /*!<Bit 0 */
-#define  SAI_xCR2_COMP_1                     0x00008000U        /*!<Bit 1 */
-
-/******************  Bit definition for SAI_xFRCR register  *******************/
-#define  SAI_xFRCR_FRL                       0x000000FFU        /*!<FRL[1:0](Frame length)  */
-#define  SAI_xFRCR_FRL_0                     0x00000001U        /*!<Bit 0 */
-#define  SAI_xFRCR_FRL_1                     0x00000002U        /*!<Bit 1 */
-#define  SAI_xFRCR_FRL_2                     0x00000004U        /*!<Bit 2 */
-#define  SAI_xFRCR_FRL_3                     0x00000008U        /*!<Bit 3 */
-#define  SAI_xFRCR_FRL_4                     0x00000010U        /*!<Bit 4 */
-#define  SAI_xFRCR_FRL_5                     0x00000020U        /*!<Bit 5 */
-#define  SAI_xFRCR_FRL_6                     0x00000040U        /*!<Bit 6 */
-#define  SAI_xFRCR_FRL_7                     0x00000080U        /*!<Bit 7 */
-
-#define  SAI_xFRCR_FSALL                     0x00007F00U        /*!<FRL[1:0] (Frame synchronization active level length)  */
-#define  SAI_xFRCR_FSALL_0                   0x00000100U        /*!<Bit 0 */
-#define  SAI_xFRCR_FSALL_1                   0x00000200U        /*!<Bit 1 */
-#define  SAI_xFRCR_FSALL_2                   0x00000400U        /*!<Bit 2 */
-#define  SAI_xFRCR_FSALL_3                   0x00000800U        /*!<Bit 3 */
-#define  SAI_xFRCR_FSALL_4                   0x00001000U        /*!<Bit 4 */
-#define  SAI_xFRCR_FSALL_5                   0x00002000U        /*!<Bit 5 */
-#define  SAI_xFRCR_FSALL_6                   0x00004000U        /*!<Bit 6 */
-
-#define  SAI_xFRCR_FSDEF                     0x00010000U        /*!<Frame Synchronization Definition  */
-#define  SAI_xFRCR_FSPOL                     0x00020000U        /*!<Frame Synchronization POLarity    */
-#define  SAI_xFRCR_FSOFF                     0x00040000U        /*!<Frame Synchronization OFFset      */
-
-/* Legacy define */
-#define  SAI_xFRCR_FSPO                      SAI_xFRCR_FSPOL
-
-/******************  Bit definition for SAI_xSLOTR register  *******************/
-#define  SAI_xSLOTR_FBOFF                    0x0000001FU        /*!<FRL[4:0](First Bit Offset)  */
-#define  SAI_xSLOTR_FBOFF_0                  0x00000001U        /*!<Bit 0 */
-#define  SAI_xSLOTR_FBOFF_1                  0x00000002U        /*!<Bit 1 */
-#define  SAI_xSLOTR_FBOFF_2                  0x00000004U        /*!<Bit 2 */
-#define  SAI_xSLOTR_FBOFF_3                  0x00000008U        /*!<Bit 3 */
-#define  SAI_xSLOTR_FBOFF_4                  0x00000010U        /*!<Bit 4 */
-
-#define  SAI_xSLOTR_SLOTSZ                   0x000000C0U        /*!<SLOTSZ[1:0] (Slot size)  */
-#define  SAI_xSLOTR_SLOTSZ_0                 0x00000040U        /*!<Bit 0 */
-#define  SAI_xSLOTR_SLOTSZ_1                 0x00000080U        /*!<Bit 1 */
-
-#define  SAI_xSLOTR_NBSLOT                   0x00000F00U        /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
-#define  SAI_xSLOTR_NBSLOT_0                 0x00000100U        /*!<Bit 0 */
-#define  SAI_xSLOTR_NBSLOT_1                 0x00000200U        /*!<Bit 1 */
-#define  SAI_xSLOTR_NBSLOT_2                 0x00000400U        /*!<Bit 2 */
-#define  SAI_xSLOTR_NBSLOT_3                 0x00000800U        /*!<Bit 3 */
-
-#define  SAI_xSLOTR_SLOTEN                   0xFFFF0000U        /*!<SLOTEN[15:0] (Slot Enable)  */
-
-/*******************  Bit definition for SAI_xIMR register  *******************/
-#define  SAI_xIMR_OVRUDRIE                   0x00000001U        /*!<Overrun underrun interrupt enable                              */
-#define  SAI_xIMR_MUTEDETIE                  0x00000002U        /*!<Mute detection interrupt enable                                */
-#define  SAI_xIMR_WCKCFGIE                   0x00000004U        /*!<Wrong Clock Configuration interrupt enable                     */
-#define  SAI_xIMR_FREQIE                     0x00000008U        /*!<FIFO request interrupt enable                                  */
-#define  SAI_xIMR_CNRDYIE                    0x00000010U        /*!<Codec not ready interrupt enable                               */
-#define  SAI_xIMR_AFSDETIE                   0x00000020U        /*!<Anticipated frame synchronization detection interrupt enable   */
-#define  SAI_xIMR_LFSDETIE                   0x00000040U        /*!<Late frame synchronization detection interrupt enable          */
-
-/********************  Bit definition for SAI_xSR register  *******************/
-#define  SAI_xSR_OVRUDR                      0x00000001U         /*!<Overrun underrun                               */
-#define  SAI_xSR_MUTEDET                     0x00000002U         /*!<Mute detection                                 */
-#define  SAI_xSR_WCKCFG                      0x00000004U         /*!<Wrong Clock Configuration                      */
-#define  SAI_xSR_FREQ                        0x00000008U         /*!<FIFO request                                   */
-#define  SAI_xSR_CNRDY                       0x00000010U         /*!<Codec not ready                                */
-#define  SAI_xSR_AFSDET                      0x00000020U         /*!<Anticipated frame synchronization detection    */
-#define  SAI_xSR_LFSDET                      0x00000040U         /*!<Late frame synchronization detection           */
-
-#define  SAI_xSR_FLVL                        0x00070000U         /*!<FLVL[2:0] (FIFO Level Threshold)               */
-#define  SAI_xSR_FLVL_0                      0x00010000U         /*!<Bit 0 */
-#define  SAI_xSR_FLVL_1                      0x00020000U         /*!<Bit 1 */
-#define  SAI_xSR_FLVL_2                      0x00040000U         /*!<Bit 2 */
-
-/******************  Bit definition for SAI_xCLRFR register  ******************/
-#define  SAI_xCLRFR_COVRUDR                  0x00000001U        /*!<Clear Overrun underrun                               */
-#define  SAI_xCLRFR_CMUTEDET                 0x00000002U        /*!<Clear Mute detection                                 */
-#define  SAI_xCLRFR_CWCKCFG                  0x00000004U        /*!<Clear Wrong Clock Configuration                      */
-#define  SAI_xCLRFR_CFREQ                    0x00000008U        /*!<Clear FIFO request                                   */
-#define  SAI_xCLRFR_CCNRDY                   0x00000010U        /*!<Clear Codec not ready                                */
-#define  SAI_xCLRFR_CAFSDET                  0x00000020U        /*!<Clear Anticipated frame synchronization detection    */
-#define  SAI_xCLRFR_CLFSDET                  0x00000040U        /*!<Clear Late frame synchronization detection           */
-
-/******************  Bit definition for SAI_xDR register  *********************/
-#define  SAI_xDR_DATA                        0xFFFFFFFFU
-
-/******************************************************************************/
-/*                                                                            */
-/*                              SPDIF-RX Interface                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for SPDIF_CR register  *******************/
-#define  SPDIFRX_CR_SPDIFEN                0x00000003U        /*!<Peripheral Block Enable                      */
-#define  SPDIFRX_CR_RXDMAEN                0x00000004U        /*!<Receiver DMA Enable for data flow            */
-#define  SPDIFRX_CR_RXSTEO                 0x00000008U        /*!<Stereo Mode                                  */
-#define  SPDIFRX_CR_DRFMT                  0x00000030U        /*!<RX Data format                               */
-#define  SPDIFRX_CR_PMSK                   0x00000040U        /*!<Mask Parity error bit                        */
-#define  SPDIFRX_CR_VMSK                   0x00000080U        /*!<Mask of Validity bit                         */
-#define  SPDIFRX_CR_CUMSK                  0x00000100U        /*!<Mask of channel status and user bits         */
-#define  SPDIFRX_CR_PTMSK                  0x00000200U        /*!<Mask of Preamble Type bits                   */
-#define  SPDIFRX_CR_CBDMAEN                0x00000400U        /*!<Control Buffer DMA ENable for control flow   */
-#define  SPDIFRX_CR_CHSEL                  0x00000800U        /*!<Channel Selection                            */
-#define  SPDIFRX_CR_NBTR                   0x00003000U        /*!<Maximum allowed re-tries during synchronization phase */
-#define  SPDIFRX_CR_WFA                    0x00004000U        /*!<Wait For Activity     */
-#define  SPDIFRX_CR_INSEL                  0x00070000U        /*!<SPDIF input selection */
-
-/*******************  Bit definition for SPDIFRX_IMR register  *******************/
-#define  SPDIFRX_IMR_RXNEIE                0x00000001U        /*!<RXNE interrupt enable                              */
-#define  SPDIFRX_IMR_CSRNEIE               0x00000002U        /*!<Control Buffer Ready Interrupt Enable              */
-#define  SPDIFRX_IMR_PERRIE                0x00000004U        /*!<Parity error interrupt enable                      */
-#define  SPDIFRX_IMR_OVRIE                 0x00000008U        /*!<Overrun error Interrupt Enable                     */
-#define  SPDIFRX_IMR_SBLKIE                0x00000010U        /*!<Synchronization Block Detected Interrupt Enable    */
-#define  SPDIFRX_IMR_SYNCDIE               0x00000020U        /*!<Synchronization Done                               */
-#define  SPDIFRX_IMR_IFEIE                 0x00000040U        /*!<Serial Interface Error Interrupt Enable            */
-
-/*******************  Bit definition for SPDIFRX_SR register  *******************/
-#define  SPDIFRX_SR_RXNE                   0x00000001U       /*!<Read data register not empty                          */
-#define  SPDIFRX_SR_CSRNE                  0x00000002U       /*!<The Control Buffer register is not empty              */
-#define  SPDIFRX_SR_PERR                   0x00000004U       /*!<Parity error                                          */
-#define  SPDIFRX_SR_OVR                    0x00000008U       /*!<Overrun error                                         */
-#define  SPDIFRX_SR_SBD                    0x00000010U       /*!<Synchronization Block Detected                        */
-#define  SPDIFRX_SR_SYNCD                  0x00000020U       /*!<Synchronization Done                                  */
-#define  SPDIFRX_SR_FERR                   0x00000040U       /*!<Framing error                                         */
-#define  SPDIFRX_SR_SERR                   0x00000080U       /*!<Synchronization error                                 */
-#define  SPDIFRX_SR_TERR                   0x00000100U       /*!<Time-out error                                        */
-#define  SPDIFRX_SR_WIDTH5                 0x7FFF0000U       /*!<Duration of 5 symbols counted with spdif_clk          */
-
-/*******************  Bit definition for SPDIFRX_IFCR register  *******************/
-#define  SPDIFRX_IFCR_PERRCF               0x00000004U       /*!<Clears the Parity error flag                         */
-#define  SPDIFRX_IFCR_OVRCF                0x00000008U       /*!<Clears the Overrun error flag                        */
-#define  SPDIFRX_IFCR_SBDCF                0x00000010U       /*!<Clears the Synchronization Block Detected flag       */
-#define  SPDIFRX_IFCR_SYNCDCF              0x00000020U       /*!<Clears the Synchronization Done flag                 */
-
-/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/
-#define  SPDIFRX_DR0_DR                    0x00FFFFFFU        /*!<Data value            */
-#define  SPDIFRX_DR0_PE                    0x01000000U        /*!<Parity Error bit      */
-#define  SPDIFRX_DR0_V                     0x02000000U        /*!<Validity bit          */
-#define  SPDIFRX_DR0_U                     0x04000000U        /*!<User bit              */
-#define  SPDIFRX_DR0_C                     0x08000000U        /*!<Channel Status bit    */
-#define  SPDIFRX_DR0_PT                    0x30000000U        /*!<Preamble Type         */
-
-/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/
-#define  SPDIFRX_DR1_DR                    0xFFFFFF00U        /*!<Data value            */
-#define  SPDIFRX_DR1_PT                    0x00000030U        /*!<Preamble Type         */
-#define  SPDIFRX_DR1_C                     0x00000008U        /*!<Channel Status bit    */
-#define  SPDIFRX_DR1_U                     0x00000004U        /*!<User bit              */
-#define  SPDIFRX_DR1_V                     0x00000002U        /*!<Validity bit          */
-#define  SPDIFRX_DR1_PE                    0x00000001U        /*!<Parity Error bit      */
-
-/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/
-#define  SPDIFRX_DR1_DRNL1                 0xFFFF0000U        /*!<Data value Channel B      */
-#define  SPDIFRX_DR1_DRNL2                 0x0000FFFFU        /*!<Data value Channel A      */
-
-/*******************  Bit definition for SPDIFRX_CSR register   *******************/
-#define  SPDIFRX_CSR_USR                   0x0000FFFFU        /*!<User data information           */
-#define  SPDIFRX_CSR_CS                    0x00FF0000U        /*!<Channel A status information    */
-#define  SPDIFRX_CSR_SOB                   0x01000000U        /*!<Start Of Block                  */
-
-/*******************  Bit definition for SPDIFRX_DIR register    *******************/
-#define  SPDIFRX_DIR_THI                   0x000013FFU        /*!<Threshold LOW      */
-#define  SPDIFRX_DIR_TLO                   0x1FFF0000U        /*!<Threshold HIGH     */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          SD host Interface                                 */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SDMMC_POWER register  ******************/
-#define  SDMMC_POWER_PWRCTRL                  0x03U               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDMMC_POWER_PWRCTRL_0                0x01U               /*!<Bit 0 */
-#define  SDMMC_POWER_PWRCTRL_1                0x02U               /*!<Bit 1 */
-
-/******************  Bit definition for SDMMC_CLKCR register  ******************/
-#define  SDMMC_CLKCR_CLKDIV                   0x00FFU            /*!<Clock divide factor             */
-#define  SDMMC_CLKCR_CLKEN                    0x0100U            /*!<Clock enable bit                */
-#define  SDMMC_CLKCR_PWRSAV                   0x0200U            /*!<Power saving configuration bit  */
-#define  SDMMC_CLKCR_BYPASS                   0x0400U            /*!<Clock divider bypass enable bit */
-
-#define  SDMMC_CLKCR_WIDBUS                   0x1800U            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDMMC_CLKCR_WIDBUS_0                 0x0800U            /*!<Bit 0 */
-#define  SDMMC_CLKCR_WIDBUS_1                 0x1000U            /*!<Bit 1 */
-
-#define  SDMMC_CLKCR_NEGEDGE                  0x2000U            /*!<SDMMC_CK dephasing selection bit */
-#define  SDMMC_CLKCR_HWFC_EN                  0x4000U            /*!<HW Flow Control enable          */
-
-/*******************  Bit definition for SDMMC_ARG register  *******************/
-#define  SDMMC_ARG_CMDARG                     0xFFFFFFFFU            /*!<Command argument */
-
-/*******************  Bit definition for SDMMC_CMD register  *******************/
-#define  SDMMC_CMD_CMDINDEX                   0x003FU            /*!<Command Index                               */
-
-#define  SDMMC_CMD_WAITRESP                   0x00C0U            /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDMMC_CMD_WAITRESP_0                 0x0040U            /*!< Bit 0 */
-#define  SDMMC_CMD_WAITRESP_1                 0x0080U            /*!< Bit 1 */
-
-#define  SDMMC_CMD_WAITINT                    0x0100U            /*!<CPSM Waits for Interrupt Request                               */
-#define  SDMMC_CMD_WAITPEND                   0x0200U            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDMMC_CMD_CPSMEN                     0x0400U            /*!<Command path state machine (CPSM) Enable bit                   */
-#define  SDMMC_CMD_SDIOSUSPEND                0x0800U            /*!<SD I/O suspend command                                         */
-
-/*****************  Bit definition for SDMMC_RESPCMD register  *****************/
-#define  SDMMC_RESPCMD_RESPCMD                0x3FU               /*!<Response command index */
-
-/******************  Bit definition for SDMMC_RESP0 register  ******************/
-#define  SDMMC_RESP0_CARDSTATUS0              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDMMC_RESP1 register  ******************/
-#define  SDMMC_RESP1_CARDSTATUS1              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDMMC_RESP2 register  ******************/
-#define  SDMMC_RESP2_CARDSTATUS2              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDMMC_RESP3 register  ******************/
-#define  SDMMC_RESP3_CARDSTATUS3              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDMMC_RESP4 register  ******************/
-#define  SDMMC_RESP4_CARDSTATUS4              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDMMC_DTIMER register  *****************/
-#define  SDMMC_DTIMER_DATATIME                0xFFFFFFFFU        /*!<Data timeout period. */
-
-/******************  Bit definition for SDMMC_DLEN register  *******************/
-#define  SDMMC_DLEN_DATALENGTH                0x01FFFFFFU        /*!<Data length value    */
-
-/******************  Bit definition for SDMMC_DCTRL register  ******************/
-#define  SDMMC_DCTRL_DTEN                     0x0001U            /*!<Data transfer enabled bit         */
-#define  SDMMC_DCTRL_DTDIR                    0x0002U            /*!<Data transfer direction selection */
-#define  SDMMC_DCTRL_DTMODE                   0x0004U            /*!<Data transfer mode selection      */
-#define  SDMMC_DCTRL_DMAEN                    0x0008U            /*!<DMA enabled bit                   */
-
-#define  SDMMC_DCTRL_DBLOCKSIZE               0x00F0U            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDMMC_DCTRL_DBLOCKSIZE_0             0x0010U            /*!<Bit 0 */
-#define  SDMMC_DCTRL_DBLOCKSIZE_1             0x0020U            /*!<Bit 1 */
-#define  SDMMC_DCTRL_DBLOCKSIZE_2             0x0040U            /*!<Bit 2 */
-#define  SDMMC_DCTRL_DBLOCKSIZE_3             0x0080U            /*!<Bit 3 */
-
-#define  SDMMC_DCTRL_RWSTART                  0x0100U            /*!<Read wait start         */
-#define  SDMMC_DCTRL_RWSTOP                   0x0200U            /*!<Read wait stop          */
-#define  SDMMC_DCTRL_RWMOD                    0x0400U            /*!<Read wait mode          */
-#define  SDMMC_DCTRL_SDIOEN                   0x0800U            /*!<SD I/O enable functions */
-
-/******************  Bit definition for SDMMC_DCOUNT register  *****************/
-#define  SDMMC_DCOUNT_DATACOUNT               0x01FFFFFFU        /*!<Data count value */
-
-/******************  Bit definition for SDMMC_STA registe  ********************/
-#define  SDMMC_STA_CCRCFAIL                   0x00000001U        /*!<Command response received (CRC check failed)  */
-#define  SDMMC_STA_DCRCFAIL                   0x00000002U        /*!<Data block sent/received (CRC check failed)   */
-#define  SDMMC_STA_CTIMEOUT                   0x00000004U        /*!<Command response timeout                      */
-#define  SDMMC_STA_DTIMEOUT                   0x00000008U        /*!<Data timeout                                  */
-#define  SDMMC_STA_TXUNDERR                   0x00000010U        /*!<Transmit FIFO underrun error                  */
-#define  SDMMC_STA_RXOVERR                    0x00000020U        /*!<Received FIFO overrun error                   */
-#define  SDMMC_STA_CMDREND                    0x00000040U        /*!<Command response received (CRC check passed)  */
-#define  SDMMC_STA_CMDSENT                    0x00000080U        /*!<Command sent (no response required)           */
-#define  SDMMC_STA_DATAEND                    0x00000100U        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
-#define  SDMMC_STA_DBCKEND                    0x00000400U        /*!<Data block sent/received (CRC check passed)   */
-#define  SDMMC_STA_CMDACT                     0x00000800U        /*!<Command transfer in progress                  */
-#define  SDMMC_STA_TXACT                      0x00001000U        /*!<Data transmit in progress                     */
-#define  SDMMC_STA_RXACT                      0x00002000U        /*!<Data receive in progress                      */
-#define  SDMMC_STA_TXFIFOHE                   0x00004000U        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDMMC_STA_RXFIFOHF                   0x00008000U        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDMMC_STA_TXFIFOF                    0x00010000U        /*!<Transmit FIFO full                            */
-#define  SDMMC_STA_RXFIFOF                    0x00020000U        /*!<Receive FIFO full                             */
-#define  SDMMC_STA_TXFIFOE                    0x00040000U        /*!<Transmit FIFO empty                           */
-#define  SDMMC_STA_RXFIFOE                    0x00080000U        /*!<Receive FIFO empty                            */
-#define  SDMMC_STA_TXDAVL                     0x00100000U        /*!<Data available in transmit FIFO               */
-#define  SDMMC_STA_RXDAVL                     0x00200000U        /*!<Data available in receive FIFO                */
-#define  SDMMC_STA_SDIOIT                     0x00400000U        /*!<SDMMC interrupt received                       */
-
-/*******************  Bit definition for SDMMC_ICR register  *******************/
-#define  SDMMC_ICR_CCRCFAILC                  0x00000001U        /*!<CCRCFAIL flag clear bit */
-#define  SDMMC_ICR_DCRCFAILC                  0x00000002U        /*!<DCRCFAIL flag clear bit */
-#define  SDMMC_ICR_CTIMEOUTC                  0x00000004U        /*!<CTIMEOUT flag clear bit */
-#define  SDMMC_ICR_DTIMEOUTC                  0x00000008U        /*!<DTIMEOUT flag clear bit */
-#define  SDMMC_ICR_TXUNDERRC                  0x00000010U        /*!<TXUNDERR flag clear bit */
-#define  SDMMC_ICR_RXOVERRC                   0x00000020U        /*!<RXOVERR flag clear bit  */
-#define  SDMMC_ICR_CMDRENDC                   0x00000040U        /*!<CMDREND flag clear bit  */
-#define  SDMMC_ICR_CMDSENTC                   0x00000080U        /*!<CMDSENT flag clear bit  */
-#define  SDMMC_ICR_DATAENDC                   0x00000100U        /*!<DATAEND flag clear bit  */
-#define  SDMMC_ICR_DBCKENDC                   0x00000400U        /*!<DBCKEND flag clear bit  */
-#define  SDMMC_ICR_SDIOITC                    0x00400000U        /*!<SDMMCIT flag clear bit   */
-
-/******************  Bit definition for SDMMC_MASK register  *******************/
-#define  SDMMC_MASK_CCRCFAILIE                0x00000001U        /*!<Command CRC Fail Interrupt Enable          */
-#define  SDMMC_MASK_DCRCFAILIE                0x00000002U        /*!<Data CRC Fail Interrupt Enable             */
-#define  SDMMC_MASK_CTIMEOUTIE                0x00000004U        /*!<Command TimeOut Interrupt Enable           */
-#define  SDMMC_MASK_DTIMEOUTIE                0x00000008U        /*!<Data TimeOut Interrupt Enable              */
-#define  SDMMC_MASK_TXUNDERRIE                0x00000010U        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
-#define  SDMMC_MASK_RXOVERRIE                 0x00000020U        /*!<Rx FIFO OverRun Error Interrupt Enable     */
-#define  SDMMC_MASK_CMDRENDIE                 0x00000040U        /*!<Command Response Received Interrupt Enable */
-#define  SDMMC_MASK_CMDSENTIE                 0x00000080U        /*!<Command Sent Interrupt Enable              */
-#define  SDMMC_MASK_DATAENDIE                 0x00000100U        /*!<Data End Interrupt Enable                  */
-#define  SDMMC_MASK_DBCKENDIE                 0x00000400U        /*!<Data Block End Interrupt Enable            */
-#define  SDMMC_MASK_CMDACTIE                  0x00000800U        /*!<CCommand Acting Interrupt Enable           */
-#define  SDMMC_MASK_TXACTIE                   0x00001000U        /*!<Data Transmit Acting Interrupt Enable      */
-#define  SDMMC_MASK_RXACTIE                   0x00002000U        /*!<Data receive acting interrupt enabled      */
-#define  SDMMC_MASK_TXFIFOHEIE                0x00004000U        /*!<Tx FIFO Half Empty interrupt Enable        */
-#define  SDMMC_MASK_RXFIFOHFIE                0x00008000U        /*!<Rx FIFO Half Full interrupt Enable         */
-#define  SDMMC_MASK_TXFIFOFIE                 0x00010000U        /*!<Tx FIFO Full interrupt Enable              */
-#define  SDMMC_MASK_RXFIFOFIE                 0x00020000U        /*!<Rx FIFO Full interrupt Enable              */
-#define  SDMMC_MASK_TXFIFOEIE                 0x00040000U        /*!<Tx FIFO Empty interrupt Enable             */
-#define  SDMMC_MASK_RXFIFOEIE                 0x00080000U        /*!<Rx FIFO Empty interrupt Enable             */
-#define  SDMMC_MASK_TXDAVLIE                  0x00100000U        /*!<Data available in Tx FIFO interrupt Enable */
-#define  SDMMC_MASK_RXDAVLIE                  0x00200000U        /*!<Data available in Rx FIFO interrupt Enable */
-#define  SDMMC_MASK_SDIOITIE                  0x00400000U        /*!<SDMMC Mode Interrupt Received interrupt Enable */
-
-/*****************  Bit definition for SDMMC_FIFOCNT register  *****************/
-#define  SDMMC_FIFOCNT_FIFOCOUNT              0x00FFFFFFU        /*!<Remaining number of words to be written to or read from the FIFO */
-
-/******************  Bit definition for SDMMC_FIFO register  *******************/
-#define  SDMMC_FIFO_FIFODATA                  0xFFFFFFFFU        /*!<Receive and transmit FIFO data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface (SPI)                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        0x00000001U        /*!< Clock Phase                        */
-#define  SPI_CR1_CPOL                        0x00000002U        /*!< Clock Polarity                     */
-#define  SPI_CR1_MSTR                        0x00000004U        /*!< Master Selection                   */
-#define  SPI_CR1_BR                          0x00000038U        /*!< BR[2:0] bits (Baud Rate Control)   */
-#define  SPI_CR1_BR_0                        0x00000008U        /*!< Bit 0 */
-#define  SPI_CR1_BR_1                        0x00000010U        /*!< Bit 1 */
-#define  SPI_CR1_BR_2                        0x00000020U        /*!< Bit 2 */
-#define  SPI_CR1_SPE                         0x00000040U        /*!< SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    0x00000080U        /*!< Frame Format                        */
-#define  SPI_CR1_SSI                         0x00000100U        /*!< Internal slave select               */
-#define  SPI_CR1_SSM                         0x00000200U        /*!< Software slave management           */
-#define  SPI_CR1_RXONLY                      0x00000400U        /*!< Receive only                        */
-#define  SPI_CR1_CRCL                        0x00000800U        /*!< CRC Length                          */
-#define  SPI_CR1_CRCNEXT                     0x00001000U        /*!< Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       0x00002000U        /*!< Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      0x00004000U        /*!< Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    0x00008000U        /*!< Bidirectional data mode enable      */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     0x00000001U        /*!< Rx Buffer DMA Enable                 */
-#define  SPI_CR2_TXDMAEN                     0x00000002U        /*!< Tx Buffer DMA Enable                 */
-#define  SPI_CR2_SSOE                        0x00000004U        /*!< SS Output Enable                     */
-#define  SPI_CR2_NSSP                        0x00000008U        /*!< NSS pulse management Enable          */
-#define  SPI_CR2_FRF                         0x00000010U        /*!< Frame Format Enable                  */
-#define  SPI_CR2_ERRIE                       0x00000020U        /*!< Error Interrupt Enable               */
-#define  SPI_CR2_RXNEIE                      0x00000040U        /*!< RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       0x00000080U        /*!< Tx buffer Empty Interrupt Enable     */
-#define  SPI_CR2_DS                          0x00000F00U        /*!< DS[3:0] Data Size                    */
-#define  SPI_CR2_DS_0                        0x00000100U        /*!< Bit 0 */
-#define  SPI_CR2_DS_1                        0x00000200U        /*!< Bit 1 */
-#define  SPI_CR2_DS_2                        0x00000400U        /*!< Bit 2 */
-#define  SPI_CR2_DS_3                        0x00000800U        /*!< Bit 3 */
-#define  SPI_CR2_FRXTH                       0x00001000U        /*!< FIFO reception Threshold           */
-#define  SPI_CR2_LDMARX                      0x00002000U        /*!< Last DMA transfer for reception    */
-#define  SPI_CR2_LDMATX                      0x00004000U        /*!< Last DMA transfer for transmission */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         0x00000001U        /*!< Receive buffer Not Empty  */
-#define  SPI_SR_TXE                          0x00000002U        /*!< Transmit buffer Empty     */
-#define  SPI_SR_CHSIDE                       0x00000004U        /*!< Channel side              */
-#define  SPI_SR_UDR                          0x00000008U        /*!< Underrun flag             */
-#define  SPI_SR_CRCERR                       0x00000010U        /*!< CRC Error flag            */
-#define  SPI_SR_MODF                         0x00000020U        /*!< Mode fault                */
-#define  SPI_SR_OVR                          0x00000040U        /*!< Overrun flag              */
-#define  SPI_SR_BSY                          0x00000080U        /*!< Busy flag                 */
-#define  SPI_SR_FRE                          0x00000100U        /*!< TI frame format error     */
-#define  SPI_SR_FRLVL                        0x00000600U        /*!< FIFO Reception Level      */
-#define  SPI_SR_FRLVL_0                      0x00000200U        /*!< Bit 0 */
-#define  SPI_SR_FRLVL_1                      0x00000400U        /*!< Bit 1 */
-#define  SPI_SR_FTLVL                        0x00001800U        /*!< FIFO Transmission Level   */
-#define  SPI_SR_FTLVL_0                      0x00000800U        /*!< Bit 0 */
-#define  SPI_SR_FTLVL_1                      0x00001000U        /*!< Bit 1 */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           0xFFFFU            /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   0xFFFFU            /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    0xFFFFU            /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    0xFFFFU            /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   0x00000001U        /*!<Channel length (number of bits per audio channel) */
-#define  SPI_I2SCFGR_DATLEN                  0x00000006U        /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define  SPI_I2SCFGR_DATLEN_0                0x00000002U        /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                0x00000004U        /*!<Bit 1 */
-#define  SPI_I2SCFGR_CKPOL                   0x00000008U        /*!<steady state clock polarity                       */
-#define  SPI_I2SCFGR_I2SSTD                  0x00000030U        /*!<I2SSTD[1:0] bits (I2S standard selection)         */
-#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U        /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U        /*!<Bit 1 */
-#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U        /*!<PCM frame synchronization                         */
-#define  SPI_I2SCFGR_I2SCFG                  0x00000300U        /*!<I2SCFG[1:0] bits (I2S configuration mode)         */
-#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U        /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U        /*!<Bit 1 */
-#define  SPI_I2SCFGR_I2SE                    0x00000400U        /*!<I2S Enable                                        */
-#define  SPI_I2SCFGR_I2SMOD                  0x00000800U        /*!<I2S mode selection                                */
-#define  SPI_I2SCFGR_ASTRTEN                 0x00001000U        /*!<Asynchronous start enable                        */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    0x00FFU            /*!<I2S Linear prescaler         */
-#define  SPI_I2SPR_ODD                       0x0100U            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     0x0200U            /*!<Master Clock Output Enable   */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 SYSCFG                                     */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SYSCFG_MEMRMP register  ***************/
-#define SYSCFG_MEMRMP_MEM_BOOT         0x00000001U /*!< Boot information after Reset */
-
-
-#define SYSCFG_MEMRMP_SWP_FMC          0x00000C00U /*!< FMC Memory Mapping swapping */
-#define SYSCFG_MEMRMP_SWP_FMC_0        0x00000400U
-#define SYSCFG_MEMRMP_SWP_FMC_1        0x00000800U
-
-/******************  Bit definition for SYSCFG_PMC register  ******************/
-
-#define SYSCFG_PMC_ADCxDC2              0x00070000U /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC1DC2              0x00010000U /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC2DC2              0x00020000U /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC3DC2              0x00040000U /*!< Refer to AN4073 on how to use this bit  */
-
-#define SYSCFG_PMC_MII_RMII_SEL         0x00800000U /*!<Ethernet PHY interface selection */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
-/**
-  * @brief   EXTI0 configuration
-  */
-#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         0x0003U /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         0x0004U /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         0x0005U /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         0x0006U /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PI         0x0008U /*!<PI[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PJ         0x0009U /*!<PJ[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PK         0x000AU /*!<PK[0] pin */
-
-/**
-  * @brief   EXTI1 configuration
-  */
-#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         0x0030U /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         0x0040U /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         0x0050U /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         0x0060U /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PI         0x0080U /*!<PI[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PJ         0x0090U /*!<PJ[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PK         0x00A0U /*!<PK[1] pin */
-
-/**
-  * @brief   EXTI2 configuration
-  */
-#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         0x0300U /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         0x0400U /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         0x0500U /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         0x0600U /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PI         0x0800U /*!<PI[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PJ         0x0900U /*!<PJ[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PK         0x0A00U /*!<PK[2] pin */
-
-/**
-  * @brief   EXTI3 configuration
-  */
-#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         0x3000U /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         0x4000U /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         0x5000U /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         0x6000U /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PI         0x8000U /*!<PI[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PJ         0x9000U /*!<PJ[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PK         0xA000U /*!<PK[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
-/**
-  * @brief   EXTI4 configuration
-  */
-#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         0x0003U /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         0x0004U /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         0x0005U /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         0x0006U /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PI         0x0008U /*!<PI[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PJ         0x0009U /*!<PJ[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PK         0x000AU /*!<PK[4] pin */
-
-/**
-  * @brief   EXTI5 configuration
-  */
-#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         0x0030U /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         0x0040U /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         0x0050U /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         0x0060U /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PI         0x0080U /*!<PI[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PJ         0x0090U /*!<PJ[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PK         0x00A0U /*!<PK[5] pin */
-
-/**
-  * @brief   EXTI6 configuration
-  */
-#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         0x0300U /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         0x0400U /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         0x0500U /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         0x0600U /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PI         0x0800U /*!<PI[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PJ         0x0900U /*!<PJ[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PK         0x0A00U /*!<PK[6] pin */
-
-/**
-  * @brief   EXTI7 configuration
-  */
-#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         0x3000U /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         0x4000U /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         0x5000U /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         0x6000U /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PI         0x8000U /*!<PI[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PJ         0x9000U /*!<PJ[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PK         0xA000U /*!<PK[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
-
-/**
-  * @brief   EXTI8 configuration
-  */
-#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         0x0003U /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         0x0004U /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         0x0005U /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         0x0006U /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PI         0x0008U /*!<PI[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PJ         0x0009U /*!<PJ[8] pin */
-
-/**
-  * @brief   EXTI9 configuration
-  */
-#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         0x0030U /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         0x0040U /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         0x0050U /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         0x0060U /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PI         0x0080U /*!<PI[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PJ         0x0090U /*!<PJ[9] pin */
-
-/**
-  * @brief   EXTI10 configuration
-  */
-#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        0x0300U /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        0x0400U /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        0x0500U /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        0x0600U /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PI        0x0800U /*!<PI[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PJ        0x0900U /*!<PJ[10] pin */
-
-/**
-  * @brief   EXTI11 configuration
-  */
-#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        0x3000U /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        0x4000U /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        0x5000U /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        0x6000U /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PI        0x8000U /*!<PI[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PJ        0x9000U /*!<PJ[11] pin */
-
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
-/**
-  * @brief   EXTI12 configuration
-  */
-#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        0x0003U /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        0x0004U /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        0x0005U /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        0x0006U /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PI        0x0008U /*!<PI[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PJ        0x0009U /*!<PJ[12] pin */
-
-/**
-  * @brief   EXTI13 configuration
-  */
-#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        0x0030U /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        0x0040U /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        0x0050U /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        0x0060U /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PI        0x0080U /*!<PI[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PJ        0x0090U /*!<PJ[13] pin */
-
-/**
-  * @brief   EXTI14 configuration
-  */
-#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        0x0300U /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        0x0400U /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        0x0500U /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        0x0600U /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PI        0x0800U /*!<PI[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PJ        0x0900U /*!<PJ[14] pin */
-
-/**
-  * @brief   EXTI15 configuration
-  */
-#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        0x3000U /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        0x4000U /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        0x5000U /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        0x6000U /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PI        0x8000U /*!<PI[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PJ        0x9000U /*!<PJ[15] pin */
-
-
-/******************  Bit definition for SYSCFG_CMPCR register  ****************/
-#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell power-down */
-#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell ready flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    TIM                                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
-#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
-#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
-#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
-#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
-
-#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
-
-#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
-
-#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
-#define  TIM_CR1_UIFREMAP                    0x0800U            /*!<UIF status bit */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        0x00000001U            /*!<Capture/Compare Preloaded Control        */
-#define  TIM_CR2_CCUS                        0x00000004U            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        0x00000008U            /*!<Capture/Compare DMA Selection            */
-
-#define  TIM_CR2_OIS5                        0x00010000U            /*!<Output Idle state 4 (OC4 output) */
-#define  TIM_CR2_OIS6                        0x00040000U            /*!<Output Idle state 4 (OC4 output) */
-
-#define  TIM_CR2_MMS                         0x0070U           /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       0x0010U           /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       0x0020U           /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       0x0040U           /*!<Bit 2 */
-
-#define  TIM_CR2_MMS2                        0x00F00000U            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS2_0                      0x00100000U            /*!<Bit 0 */
-#define  TIM_CR2_MMS2_1                      0x00200000U            /*!<Bit 1 */
-#define  TIM_CR2_MMS2_2                      0x00400000U            /*!<Bit 2 */
-#define  TIM_CR2_MMS2_3                      0x00800000U            /*!<Bit 2 */
-
-#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
-#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
-#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
-#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        0x00010007U            /*!<SMS[2:0] bits (Slave mode selection)    */
-#define  TIM_SMCR_SMS_0                      0x00000001U            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      0x00000002U            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      0x00000004U            /*!<Bit 2 */
-#define  TIM_SMCR_SMS_3                      0x00010000U            /*!<Bit 3 */
-#define  TIM_SMCR_OCCS                       0x00000008U            /*!< OCREF clear selection */
-
-#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
-#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
-
-#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
-
-#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
-
-#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
-#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
-#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
-#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
-#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
-#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
-#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
-#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
-#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
-#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
-#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
-#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
-#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
-#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
-#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
-#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
-#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
-#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
-#define  TIM_SR_B2IF                         0x0100U            /*!<Break2 interrupt Flag               */
-#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          0x00000001U               /*!<Update Generation                         */
-#define  TIM_EGR_CC1G                        0x00000002U               /*!<Capture/Compare 1 Generation              */
-#define  TIM_EGR_CC2G                        0x00000004U               /*!<Capture/Compare 2 Generation              */
-#define  TIM_EGR_CC3G                        0x00000008U               /*!<Capture/Compare 3 Generation              */
-#define  TIM_EGR_CC4G                        0x00000010U               /*!<Capture/Compare 4 Generation              */
-#define  TIM_EGR_COMG                        0x00000020U               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          0x00000040U               /*!<Trigger Generation                        */
-#define  TIM_EGR_BG                          0x00000080U               /*!<Break Generation                          */
-#define  TIM_EGR_B2G                         0x00000100U              /*!<Break2 Generation                          */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      0x00000003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    0x00000001U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    0x00000002U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC1FE                     0x00000004U            /*!<Output Compare 1 Fast enable                 */
-#define  TIM_CCMR1_OC1PE                     0x00000008U            /*!<Output Compare 1 Preload enable              */
-
-#define  TIM_CCMR1_OC1M                      0x00010070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define  TIM_CCMR1_OC1M_0                    0x00000010U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    0x00000020U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    0x00000040U            /*!<Bit 2 */
-#define  TIM_CCMR1_OC1M_3                    0x00010000U            /*!<Bit 3 */
-
-#define  TIM_CCMR1_OC1CE                     0x00000080U            /*!<Output Compare 1Clear Enable                 */
-
-#define  TIM_CCMR1_CC2S                      0x00000300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    0x00000100U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    0x00000200U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC2FE                     0x00000400U            /*!<Output Compare 2 Fast enable                 */
-#define  TIM_CCMR1_OC2PE                     0x00000800U            /*!<Output Compare 2 Preload enable              */
-
-#define  TIM_CCMR1_OC2M                      0x01007000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define  TIM_CCMR1_OC2M_0                    0x00001000U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    0x00002000U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    0x00004000U            /*!<Bit 2 */
-#define  TIM_CCMR1_OC2M_3                    0x01000000U            /*!<Bit 3 */
-
-#define  TIM_CCMR1_OC2CE                     0x00008000U            /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      0x00000003U        /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define  TIM_CCMR2_CC3S_0                    0x00000001U        /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    0x00000002U        /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC3FE                     0x00000004U        /*!<Output Compare 3 Fast enable           */
-#define  TIM_CCMR2_OC3PE                     0x00000008U        /*!<Output Compare 3 Preload enable        */
-
-#define  TIM_CCMR2_OC3M                      0x00010070U        /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    0x00000010U        /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    0x00000020U        /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    0x00000040U        /*!<Bit 2 */
-#define  TIM_CCMR2_OC3M_3                    0x00010000U        /*!<Bit 3 */
-
-
-
-#define  TIM_CCMR2_OC3CE                     0x00000080U        /*!<Output Compare 3 Clear Enable */
-
-#define  TIM_CCMR2_CC4S                      0x00000300U        /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    0x00000100U        /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    0x00000200U        /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC4FE                     0x00000400U        /*!<Output Compare 4 Fast enable    */
-#define  TIM_CCMR2_OC4PE                     0x00000800U        /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR2_OC4M                      0x01007000U        /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    0x00001000U        /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    0x00002000U        /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    0x00004000U        /*!<Bit 2 */
-#define  TIM_CCMR2_OC4M_3                    0x01000000U        /*!<Bit 3 */
-
-#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       0x00000001U            /*!<Capture/Compare 1 output enable */
-#define  TIM_CCER_CC1P                       0x00000002U            /*!<Capture/Compare 1 output Polarity */
-#define  TIM_CCER_CC1NE                      0x00000004U            /*!<Capture/Compare 1 Complementary output enable */
-#define  TIM_CCER_CC1NP                      0x00000008U            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       0x00000010U            /*!<Capture/Compare 2 output enable */
-#define  TIM_CCER_CC2P                       0x00000020U            /*!<Capture/Compare 2 output Polarity */
-#define  TIM_CCER_CC2NE                      0x00000040U            /*!<Capture/Compare 2 Complementary output enable */
-#define  TIM_CCER_CC2NP                      0x00000080U            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       0x00000100U            /*!<Capture/Compare 3 output enable */
-#define  TIM_CCER_CC3P                       0x00000200U            /*!<Capture/Compare 3 output Polarity */
-#define  TIM_CCER_CC3NE                      0x00000400U            /*!<Capture/Compare 3 Complementary output enable */
-#define  TIM_CCER_CC3NP                      0x00000800U            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       0x00001000U            /*!<Capture/Compare 4 output enable */
-#define  TIM_CCER_CC4P                       0x00002000U            /*!<Capture/Compare 4 output Polarity */
-#define  TIM_CCER_CC4NP                      0x00008000U            /*!<Capture/Compare 4 Complementary output Polarity */
-#define  TIM_CCER_CC5E                       0x00010000U            /*!<Capture/Compare 5 output enable */
-#define  TIM_CCER_CC5P                       0x00020000U            /*!<Capture/Compare 5 output Polarity */
-#define  TIM_CCER_CC6E                       0x00100000U            /*!<Capture/Compare 6 output enable */
-#define  TIM_CCER_CC6P                       0x00200000U            /*!<Capture/Compare 6 output Polarity */
-
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         ((uint8_t)0xFFU)               /*!<Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
-
-/*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        0x000000FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      0x00000001U            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      0x00000002U            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      0x00000004U            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      0x00000008U            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      0x00000010U            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      0x00000020U            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      0x00000040U            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      0x00000080U            /*!<Bit 7 */
-
-#define  TIM_BDTR_LOCK                       0x00000300U            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     0x00000100U            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     0x00000200U            /*!<Bit 1 */
-
-#define  TIM_BDTR_OSSI                       0x00000400U            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       0x00000800U            /*!<Off-State Selection for Run mode  */
-#define  TIM_BDTR_BKE                        0x00001000U            /*!<Break enable                      */
-#define  TIM_BDTR_BKP                        0x00002000U            /*!<Break Polarity                    */
-#define  TIM_BDTR_AOE                        0x00004000U            /*!<Automatic Output enable           */
-#define  TIM_BDTR_MOE                        0x00008000U            /*!<Main Output enable                */
-#define  TIM_BDTR_BKF                        0x000F0000U            /*!<Break Filter for Break1 */
-#define  TIM_BDTR_BK2F                       0x00F00000U            /*!<Break Filter for Break2 */
-#define  TIM_BDTR_BK2E                       0x01000000U            /*!<Break enable for Break2 */
-#define  TIM_BDTR_BK2P                       0x02000000U            /*!<Break Polarity for Break2 */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
-
-#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
-
-/*******************  Bit definition for TIM_OR regiter  *********************/
-#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
-#define TIM_OR_ITR1_RMP                      0x0C00U            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
-#define TIM_OR_ITR1_RMP_0                    0x0400U            /*!<Bit 0 */
-#define TIM_OR_ITR1_RMP_1                    0x0800U            /*!<Bit 1 */
-
-/******************  Bit definition for TIM_CCMR3 register  *******************/
-#define  TIM_CCMR3_OC5FE                     0x00000004U            /*!<Output Compare 5 Fast enable */
-#define  TIM_CCMR3_OC5PE                     0x00000008U            /*!<Output Compare 5 Preload enable */
-
-#define  TIM_CCMR3_OC5M                      0x00010070U            /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
-#define  TIM_CCMR3_OC5M_0                    0x00000010U            /*!<Bit 0 */
-#define  TIM_CCMR3_OC5M_1                    0x00000020U            /*!<Bit 1 */
-#define  TIM_CCMR3_OC5M_2                    0x00000040U            /*!<Bit 2 */
-#define  TIM_CCMR3_OC5M_3                    0x00010000U            /*!<Bit 3 */
-
-#define  TIM_CCMR3_OC5CE                     0x00000080U            /*!<Output Compare 5 Clear Enable */
-
-#define  TIM_CCMR3_OC6FE                     0x00000400U            /*!<Output Compare 4 Fast enable */
-#define  TIM_CCMR3_OC6PE                     0x00000800U            /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR3_OC6M                      0x01007000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR3_OC6M_0                    0x00001000U            /*!<Bit 0 */
-#define  TIM_CCMR3_OC6M_1                    0x00002000U            /*!<Bit 1 */
-#define  TIM_CCMR3_OC6M_2                    0x00004000U            /*!<Bit 2 */
-#define  TIM_CCMR3_OC6M_3                    0x01000000U            /*!<Bit 3 */
-
-#define  TIM_CCMR3_OC6CE                     0x00008000U            /*!<Output Compare 4 Clear Enable */
-
-/*******************  Bit definition for TIM_CCR5 register  *******************/
-#define  TIM_CCR5_CCR5                       0xFFFFFFFFU        /*!<Capture/Compare 5 Value */
-#define  TIM_CCR5_GC5C1                      0x20000000U        /*!<Group Channel 5 and Channel 1 */
-#define  TIM_CCR5_GC5C2                      0x40000000U        /*!<Group Channel 5 and Channel 2 */
-#define  TIM_CCR5_GC5C3                      0x80000000U        /*!<Group Channel 5 and Channel 3 */
-
-/*******************  Bit definition for TIM_CCR6 register  *******************/
-#define  TIM_CCR6_CCR6                       ((uint16_t)0xFFFFU)            /*!<Capture/Compare 6 Value */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Low Power Timer (LPTIM)                            */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for LPTIM_ISR register  *******************/
-#define  LPTIM_ISR_CMPM                         0x00000001U            /*!< Compare match                       */
-#define  LPTIM_ISR_ARRM                         0x00000002U            /*!< Autoreload match                    */
-#define  LPTIM_ISR_EXTTRIG                      0x00000004U            /*!< External trigger edge event         */
-#define  LPTIM_ISR_CMPOK                        0x00000008U            /*!< Compare register update OK          */
-#define  LPTIM_ISR_ARROK                        0x00000010U            /*!< Autoreload register update OK       */
-#define  LPTIM_ISR_UP                           0x00000020U            /*!< Counter direction change down to up */
-#define  LPTIM_ISR_DOWN                         0x00000040U            /*!< Counter direction change up to down */
-
-/******************  Bit definition for LPTIM_ICR register  *******************/
-#define  LPTIM_ICR_CMPMCF                       0x00000001U            /*!< Compare match Clear Flag                       */
-#define  LPTIM_ICR_ARRMCF                       0x00000002U            /*!< Autoreload match Clear Flag                    */
-#define  LPTIM_ICR_EXTTRIGCF                    0x00000004U            /*!< External trigger edge event Clear Flag         */
-#define  LPTIM_ICR_CMPOKCF                      0x00000008U            /*!< Compare register update OK Clear Flag          */
-#define  LPTIM_ICR_ARROKCF                      0x00000010U            /*!< Autoreload register update OK Clear Flag       */
-#define  LPTIM_ICR_UPCF                         0x00000020U            /*!< Counter direction change down to up Clear Flag */
-#define  LPTIM_ICR_DOWNCF                       0x00000040U            /*!< Counter direction change up to down Clear Flag */
-
-/******************  Bit definition for LPTIM_IER register *******************/
-#define  LPTIM_IER_CMPMIE                       0x00000001U            /*!< Compare match Interrupt Enable                       */
-#define  LPTIM_IER_ARRMIE                       0x00000002U            /*!< Autoreload match Interrupt Enable                    */
-#define  LPTIM_IER_EXTTRIGIE                    0x00000004U            /*!< External trigger edge event Interrupt Enable         */
-#define  LPTIM_IER_CMPOKIE                      0x00000008U            /*!< Compare register update OK Interrupt Enable          */
-#define  LPTIM_IER_ARROKIE                      0x00000010U            /*!< Autoreload register update OK Interrupt Enable       */
-#define  LPTIM_IER_UPIE                         0x00000020U            /*!< Counter direction change down to up Interrupt Enable */
-#define  LPTIM_IER_DOWNIE                       0x00000040U            /*!< Counter direction change up to down Interrupt Enable */
-
-/******************  Bit definition for LPTIM_CFGR register*******************/
-#define  LPTIM_CFGR_CKSEL                       0x00000001U             /*!< Clock selector */
-
-#define  LPTIM_CFGR_CKPOL                       0x00000006U             /*!< CKPOL[1:0] bits (Clock polarity) */
-#define  LPTIM_CFGR_CKPOL_0                     0x00000002U             /*!< Bit 0 */
-#define  LPTIM_CFGR_CKPOL_1                     0x00000004U             /*!< Bit 1 */
-
-#define  LPTIM_CFGR_CKFLT                       0x00000018U             /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
-#define  LPTIM_CFGR_CKFLT_0                     0x00000008U             /*!< Bit 0 */
-#define  LPTIM_CFGR_CKFLT_1                     0x00000010U             /*!< Bit 1 */
-
-#define  LPTIM_CFGR_TRGFLT                      0x000000C0U             /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
-#define  LPTIM_CFGR_TRGFLT_0                    0x00000040U             /*!< Bit 0 */
-#define  LPTIM_CFGR_TRGFLT_1                    0x00000080U             /*!< Bit 1 */
-
-#define  LPTIM_CFGR_PRESC                       0x00000E00U             /*!< PRESC[2:0] bits (Clock prescaler) */
-#define  LPTIM_CFGR_PRESC_0                     0x00000200U             /*!< Bit 0 */
-#define  LPTIM_CFGR_PRESC_1                     0x00000400U             /*!< Bit 1 */
-#define  LPTIM_CFGR_PRESC_2                     0x00000800U             /*!< Bit 2 */
-
-#define  LPTIM_CFGR_TRIGSEL                     0x0000E000U             /*!< TRIGSEL[2:0]] bits (Trigger selector) */
-#define  LPTIM_CFGR_TRIGSEL_0                   0x00002000U             /*!< Bit 0 */
-#define  LPTIM_CFGR_TRIGSEL_1                   0x00004000U             /*!< Bit 1 */
-#define  LPTIM_CFGR_TRIGSEL_2                   0x00008000U             /*!< Bit 2 */
-
-#define  LPTIM_CFGR_TRIGEN                      0x00060000U             /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
-#define  LPTIM_CFGR_TRIGEN_0                    0x00020000U             /*!< Bit 0 */
-#define  LPTIM_CFGR_TRIGEN_1                    0x00040000U             /*!< Bit 1 */
-
-#define  LPTIM_CFGR_TIMOUT                      0x00080000U             /*!< Timout enable           */
-#define  LPTIM_CFGR_WAVE                        0x00100000U             /*!< Waveform shape          */
-#define  LPTIM_CFGR_WAVPOL                      0x00200000U             /*!< Waveform shape polarity */
-#define  LPTIM_CFGR_PRELOAD                     0x00400000U             /*!< Reg update mode         */
-#define  LPTIM_CFGR_COUNTMODE                   0x00800000U             /*!< Counter mode enable     */
-#define  LPTIM_CFGR_ENC                         0x01000000U             /*!< Encoder mode enable     */
-
-/******************  Bit definition for LPTIM_CR register  ********************/
-#define  LPTIM_CR_ENABLE                        0x00000001U             /*!< LPTIMer enable                 */
-#define  LPTIM_CR_SNGSTRT                       0x00000002U             /*!< Timer start in single mode     */
-#define  LPTIM_CR_CNTSTRT                       0x00000004U             /*!< Timer start in continuous mode */
-
-/******************  Bit definition for LPTIM_CMP register *******************/
-#define  LPTIM_CMP_CMP                          0x0000FFFFU             /*!< Compare register     */
-
-/******************  Bit definition for LPTIM_ARR register *******************/
-#define  LPTIM_ARR_ARR                          0x0000FFFFU             /*!< Auto reload register */
-
-/******************  Bit definition for LPTIM_CNT register *******************/
-#define  LPTIM_CNT_CNT                          0x0000FFFFU             /*!< Counter register     */
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_UE                        0x00000001U            /*!< USART Enable                                    */
-#define  USART_CR1_RE                        0x00000004U            /*!< Receiver Enable                                 */
-#define  USART_CR1_TE                        0x00000008U            /*!< Transmitter Enable                              */
-#define  USART_CR1_IDLEIE                    0x00000010U            /*!< IDLE Interrupt Enable                           */
-#define  USART_CR1_RXNEIE                    0x00000020U            /*!< RXNE Interrupt Enable                           */
-#define  USART_CR1_TCIE                      0x00000040U            /*!< Transmission Complete Interrupt Enable          */
-#define  USART_CR1_TXEIE                     0x00000080U            /*!< TXE Interrupt Enable                            */
-#define  USART_CR1_PEIE                      0x00000100U            /*!< PE Interrupt Enable                             */
-#define  USART_CR1_PS                        0x00000200U            /*!< Parity Selection                                */
-#define  USART_CR1_PCE                       0x00000400U            /*!< Parity Control Enable                           */
-#define  USART_CR1_WAKE                      0x00000800U            /*!< Receiver Wakeup method                          */
-#define  USART_CR1_M                         0x10001000U            /*!< Word length                                     */
-#define  USART_CR1_M_0                       0x00001000U            /*!< Word length - Bit 0                             */
-#define  USART_CR1_MME                       0x00002000U            /*!< Mute Mode Enable                                */
-#define  USART_CR1_CMIE                      0x00004000U            /*!< Character match interrupt enable                */
-#define  USART_CR1_OVER8                     0x00008000U            /*!< Oversampling by 8-bit or 16-bit mode            */
-#define  USART_CR1_DEDT                      0x001F0000U            /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
-#define  USART_CR1_DEDT_0                    0x00010000U            /*!< Bit 0 */
-#define  USART_CR1_DEDT_1                    0x00020000U            /*!< Bit 1 */
-#define  USART_CR1_DEDT_2                    0x00040000U            /*!< Bit 2 */
-#define  USART_CR1_DEDT_3                    0x00080000U            /*!< Bit 3 */
-#define  USART_CR1_DEDT_4                    0x00100000U            /*!< Bit 4 */
-#define  USART_CR1_DEAT                      0x03E00000U            /*!< DEAT[4:0] bits (Driver Enable Assertion Time)   */
-#define  USART_CR1_DEAT_0                    0x00200000U            /*!< Bit 0 */
-#define  USART_CR1_DEAT_1                    0x00400000U            /*!< Bit 1 */
-#define  USART_CR1_DEAT_2                    0x00800000U            /*!< Bit 2 */
-#define  USART_CR1_DEAT_3                    0x01000000U            /*!< Bit 3 */
-#define  USART_CR1_DEAT_4                    0x02000000U            /*!< Bit 4 */
-#define  USART_CR1_RTOIE                     0x04000000U            /*!< Receive Time Out interrupt enable */
-#define  USART_CR1_EOBIE                     0x08000000U            /*!< End of Block interrupt enable     */
-#define  USART_CR1_M_1                       0x10000000U            /*!< Word length - Bit 1               */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADDM7                     0x00000010U            /*!< 7-bit or 4-bit Address Detection       */
-#define  USART_CR2_LBDL                      0x00000020U            /*!< LIN Break Detection Length             */
-#define  USART_CR2_LBDIE                     0x00000040U            /*!< LIN Break Detection Interrupt Enable   */
-#define  USART_CR2_LBCL                      0x00000100U            /*!< Last Bit Clock pulse                   */
-#define  USART_CR2_CPHA                      0x00000200U            /*!< Clock Phase                            */
-#define  USART_CR2_CPOL                      0x00000400U            /*!< Clock Polarity                         */
-#define  USART_CR2_CLKEN                     0x00000800U            /*!< Clock Enable                           */
-#define  USART_CR2_STOP                      0x00003000U            /*!< STOP[1:0] bits (STOP bits)             */
-#define  USART_CR2_STOP_0                    0x00001000U            /*!< Bit 0 */
-#define  USART_CR2_STOP_1                    0x00002000U            /*!< Bit 1 */
-#define  USART_CR2_LINEN                     0x00004000U            /*!< LIN mode enable                        */
-#define  USART_CR2_SWAP                      0x00008000U            /*!< SWAP TX/RX pins                        */
-#define  USART_CR2_RXINV                     0x00010000U            /*!< RX pin active level inversion          */
-#define  USART_CR2_TXINV                     0x00020000U            /*!< TX pin active level inversion          */
-#define  USART_CR2_DATAINV                   0x00040000U            /*!< Binary data inversion                  */
-#define  USART_CR2_MSBFIRST                  0x00080000U            /*!< Most Significant Bit First             */
-#define  USART_CR2_ABREN                     0x00100000U            /*!< Auto Baud-Rate Enable                  */
-#define  USART_CR2_ABRMODE                   0x00600000U            /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
-#define  USART_CR2_ABRMODE_0                 0x00200000U            /*!< Bit 0 */
-#define  USART_CR2_ABRMODE_1                 0x00400000U            /*!< Bit 1 */
-#define  USART_CR2_RTOEN                     0x00800000U            /*!< Receiver Time-Out enable  */
-#define  USART_CR2_ADD                       0xFF000000U            /*!< Address of the USART node */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       0x00000001U            /*!< Error Interrupt Enable                         */
-#define  USART_CR3_IREN                      0x00000002U            /*!< IrDA mode Enable                               */
-#define  USART_CR3_IRLP                      0x00000004U            /*!< IrDA Low-Power                                 */
-#define  USART_CR3_HDSEL                     0x00000008U            /*!< Half-Duplex Selection                          */
-#define  USART_CR3_NACK                      0x00000010U            /*!< SmartCard NACK enable                          */
-#define  USART_CR3_SCEN                      0x00000020U            /*!< SmartCard mode enable                          */
-#define  USART_CR3_DMAR                      0x00000040U            /*!< DMA Enable Receiver                            */
-#define  USART_CR3_DMAT                      0x00000080U            /*!< DMA Enable Transmitter                         */
-#define  USART_CR3_RTSE                      0x00000100U            /*!< RTS Enable                                     */
-#define  USART_CR3_CTSE                      0x00000200U            /*!< CTS Enable                                     */
-#define  USART_CR3_CTSIE                     0x00000400U            /*!< CTS Interrupt Enable                           */
-#define  USART_CR3_ONEBIT                    0x00000800U            /*!< One sample bit method enable                   */
-#define  USART_CR3_OVRDIS                    0x00001000U            /*!< Overrun Disable                                */
-#define  USART_CR3_DDRE                      0x00002000U            /*!< DMA Disable on Reception Error                 */
-#define  USART_CR3_DEM                       0x00004000U            /*!< Driver Enable Mode                             */
-#define  USART_CR3_DEP                       0x00008000U            /*!< Driver Enable Polarity Selection               */
-#define  USART_CR3_SCARCNT                   0x000E0000U            /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
-#define  USART_CR3_SCARCNT_0                 0x00020000U            /*!< Bit 0 */
-#define  USART_CR3_SCARCNT_1                 0x00040000U            /*!< Bit 1 */
-#define  USART_CR3_SCARCNT_2                 0x00080000U            /*!< Bit 2 */
-
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_FRACTION              0x000FU                /*!< Fraction of USARTDIV */
-#define  USART_BRR_DIV_MANTISSA              0xFFF0U                /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      0x00FFU                /*!< PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_GT                       0xFF00U                /*!< GT[7:0] bits (Guard time value) */
-
-
-/*******************  Bit definition for USART_RTOR register  *****************/
-#define  USART_RTOR_RTO                      0x00FFFFFFU            /*!< Receiver Time Out Value */
-#define  USART_RTOR_BLEN                     0xFF000000U            /*!< Block Length */
-
-/*******************  Bit definition for USART_RQR register  ******************/
-#define  USART_RQR_ABRRQ                     0x0001U                /*!< Auto-Baud Rate Request      */
-#define  USART_RQR_SBKRQ                     0x0002U                /*!< Send Break Request          */
-#define  USART_RQR_MMRQ                      0x0004U                /*!< Mute Mode Request           */
-#define  USART_RQR_RXFRQ                     0x0008U                /*!< Receive Data flush Request  */
-#define  USART_RQR_TXFRQ                     0x0010U                /*!< Transmit data flush Request */
-
-/*******************  Bit definition for USART_ISR register  ******************/
-#define  USART_ISR_PE                        0x00000001U            /*!< Parity Error                        */
-#define  USART_ISR_FE                        0x00000002U            /*!< Framing Error                       */
-#define  USART_ISR_NE                        0x00000004U            /*!< Noise detected Flag                 */
-#define  USART_ISR_ORE                       0x00000008U            /*!< OverRun Error                       */
-#define  USART_ISR_IDLE                      0x00000010U            /*!< IDLE line detected                  */
-#define  USART_ISR_RXNE                      0x00000020U            /*!< Read Data Register Not Empty        */
-#define  USART_ISR_TC                        0x00000040U            /*!< Transmission Complete               */
-#define  USART_ISR_TXE                       0x00000080U            /*!< Transmit Data Register Empty        */
-#define  USART_ISR_LBDF                      0x00000100U            /*!< LIN Break Detection Flag            */
-#define  USART_ISR_CTSIF                     0x00000200U            /*!< CTS interrupt flag                  */
-#define  USART_ISR_CTS                       0x00000400U            /*!< CTS flag                            */
-#define  USART_ISR_RTOF                      0x00000800U            /*!< Receiver Time Out                   */
-#define  USART_ISR_EOBF                      0x00001000U            /*!< End Of Block Flag                   */
-#define  USART_ISR_ABRE                      0x00004000U            /*!< Auto-Baud Rate Error                */
-#define  USART_ISR_ABRF                      0x00008000U            /*!< Auto-Baud Rate Flag                 */
-#define  USART_ISR_BUSY                      0x00010000U            /*!< Busy Flag                           */
-#define  USART_ISR_CMF                       0x00020000U            /*!< Character Match Flag                */
-#define  USART_ISR_SBKF                      0x00040000U            /*!< Send Break Flag                     */
-#define  USART_ISR_RWU                       0x00080000U            /*!< Receive Wake Up from mute mode Flag */
-#define  USART_ISR_WUF                       0x00100000U            /*!< Wake Up from stop mode Flag         */
-#define  USART_ISR_TEACK                     0x00200000U            /*!< Transmit Enable Acknowledge Flag    */
-#define  USART_ISR_REACK                     0x00400000U            /*!< Receive Enable Acknowledge Flag     */
-
-/* Legacy define */
-#define  USART_ISR_LBD                       USART_ISR_LBDF
-
-/*******************  Bit definition for USART_ICR register  ******************/
-#define  USART_ICR_PECF                      0x00000001U            /*!< Parity Error Clear Flag             */
-#define  USART_ICR_FECF                      0x00000002U            /*!< Framing Error Clear Flag            */
-#define  USART_ICR_NCF                       0x00000004U            /*!< Noise detected Clear Flag           */
-#define  USART_ICR_ORECF                     0x00000008U            /*!< OverRun Error Clear Flag            */
-#define  USART_ICR_IDLECF                    0x00000010U            /*!< IDLE line detected Clear Flag       */
-#define  USART_ICR_TCCF                      0x00000040U            /*!< Transmission Complete Clear Flag    */
-#define  USART_ICR_LBDCF                     0x00000100U            /*!< LIN Break Detection Clear Flag      */
-#define  USART_ICR_CTSCF                     0x00000200U            /*!< CTS Interrupt Clear Flag            */
-#define  USART_ICR_RTOCF                     0x00000800U            /*!< Receiver Time Out Clear Flag        */
-#define  USART_ICR_EOBCF                     0x00001000U            /*!< End Of Block Clear Flag             */
-#define  USART_ICR_CMCF                      0x00020000U            /*!< Character Match Clear Flag          */
-#define  USART_ICR_WUCF                      0x00100000U            /*!< Wake Up from stop mode Clear Flag   */
-
-/*******************  Bit definition for USART_RDR register  ******************/
-#define  USART_RDR_RDR                       0x01FFU                /*!< RDR[8:0] bits (Receive Data value) */
-
-/*******************  Bit definition for USART_TDR register  ******************/
-#define  USART_TDR_TDR                       0x01FFU                /*!< TDR[8:0] bits (Transmit Data value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Window WATCHDOG                                 */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                            0x7FU                 /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T_0                          0x01U                 /*!<Bit 0 */
-#define  WWDG_CR_T_1                          0x02U                 /*!<Bit 1 */
-#define  WWDG_CR_T_2                          0x04U                 /*!<Bit 2 */
-#define  WWDG_CR_T_3                          0x08U                 /*!<Bit 3 */
-#define  WWDG_CR_T_4                          0x10U                 /*!<Bit 4 */
-#define  WWDG_CR_T_5                          0x20U                 /*!<Bit 5 */
-#define  WWDG_CR_T_6                          0x40U                 /*!<Bit 6 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0                           WWDG_CR_T_0                      /*!<Bit 0 */
-#define  WWDG_CR_T1                           WWDG_CR_T_1                      /*!<Bit 1 */
-#define  WWDG_CR_T2                           WWDG_CR_T_2                      /*!<Bit 2 */
-#define  WWDG_CR_T3                           WWDG_CR_T_3                      /*!<Bit 3 */
-#define  WWDG_CR_T4                           WWDG_CR_T_4                      /*!<Bit 4 */
-#define  WWDG_CR_T5                           WWDG_CR_T_5                      /*!<Bit 5 */
-#define  WWDG_CR_T6                           WWDG_CR_T_6                      /*!<Bit 6 */
-
-#define  WWDG_CR_WDGA                        0x80U                  /*!<Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          0x007FU                /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W_0                        0x0001U                /*!<Bit 0 */
-#define  WWDG_CFR_W_1                        0x0002U                /*!<Bit 1 */
-#define  WWDG_CFR_W_2                        0x0004U                /*!<Bit 2 */
-#define  WWDG_CFR_W_3                        0x0008U                /*!<Bit 3 */
-#define  WWDG_CFR_W_4                        0x0010U                /*!<Bit 4 */
-#define  WWDG_CFR_W_5                        0x0020U                /*!<Bit 5 */
-#define  WWDG_CFR_W_6                        0x0040U                /*!<Bit 6 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0                         WWDG_CFR_W_0                      /*!<Bit 0 */
-#define  WWDG_CFR_W1                         WWDG_CFR_W_1                      /*!<Bit 1 */
-#define  WWDG_CFR_W2                         WWDG_CFR_W_2                      /*!<Bit 2 */
-#define  WWDG_CFR_W3                         WWDG_CFR_W_3                      /*!<Bit 3 */
-#define  WWDG_CFR_W4                         WWDG_CFR_W_4                      /*!<Bit 4 */
-#define  WWDG_CFR_W5                         WWDG_CFR_W_5                      /*!<Bit 5 */
-#define  WWDG_CFR_W6                         WWDG_CFR_W_6                      /*!<Bit 6 */
-
-#define  WWDG_CFR_WDGTB                      0x0180U                /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB_0                    0x0080U                /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB_1                    0x0100U                /*!<Bit 1 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0                  /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1                  /*!<Bit 1 */
-
-#define  WWDG_CFR_EWI                        0x0200U               /*!<Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        0x01U                  /*!<Early Wakeup Interrupt Flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                DBG                                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
-#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
-
-/********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
-#define  DBGMCU_CR_DBG_STOP                  0x00000002U
-#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
-#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
-
-#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
-#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U /*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U /*!<Bit 1 */
-
-/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            0x00000001U
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            0x00000002U
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            0x00000004U
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            0x00000020U
-#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           0x00000040U
-#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           0x00000080U
-#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           0x00000100U
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
-#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
-
-/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP            0x00000001U
-#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP            0x00000002U
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP            0x00010000U
-#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP           0x00020000U
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP           0x00040000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                Ethernet MAC Registers bits definitions                     */
-/*                                                                            */
-/******************************************************************************/
-/* Bit definition for Ethernet MAC Control Register register */
-#define ETH_MACCR_WD              0x00800000U  /* Watchdog disable */
-#define ETH_MACCR_JD              0x00400000U  /* Jabber disable */
-#define ETH_MACCR_IFG             0x000E0000U  /* Inter-frame gap */
-#define ETH_MACCR_IFG_96Bit       0x00000000U  /* Minimum IFG between frames during transmission is 96Bit */
-#define ETH_MACCR_IFG_88Bit       0x00020000U  /* Minimum IFG between frames during transmission is 88Bit */
-#define ETH_MACCR_IFG_80Bit       0x00040000U  /* Minimum IFG between frames during transmission is 80Bit */
-#define ETH_MACCR_IFG_72Bit       0x00060000U  /* Minimum IFG between frames during transmission is 72Bit */
-#define ETH_MACCR_IFG_64Bit       0x00080000U  /* Minimum IFG between frames during transmission is 64Bit */
-#define ETH_MACCR_IFG_56Bit       0x000A0000U  /* Minimum IFG between frames during transmission is 56Bit */
-#define ETH_MACCR_IFG_48Bit       0x000C0000U  /* Minimum IFG between frames during transmission is 48Bit */
-#define ETH_MACCR_IFG_40Bit       0x000E0000U  /* Minimum IFG between frames during transmission is 40Bit */
-#define ETH_MACCR_CSD             0x00010000U  /* Carrier sense disable (during transmission) */
-#define ETH_MACCR_FES             0x00004000U  /* Fast ethernet speed */
-#define ETH_MACCR_ROD             0x00002000U  /* Receive own disable */
-#define ETH_MACCR_LM              0x00001000U  /* loopback mode */
-#define ETH_MACCR_DM              0x00000800U  /* Duplex mode */
-#define ETH_MACCR_IPCO            0x00000400U  /* IP Checksum offload */
-#define ETH_MACCR_RD              0x00000200U  /* Retry disable */
-#define ETH_MACCR_APCS            0x00000080U  /* Automatic Pad/CRC stripping */
-#define ETH_MACCR_BL              0x00000060U  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
-                                                       a transmission attempt during retries after a collision: 0 =< r <2^k */
-#define ETH_MACCR_BL_10           0x00000000U  /* k = min (n, 10) */
-#define ETH_MACCR_BL_8            0x00000020U  /* k = min (n, 8) */
-#define ETH_MACCR_BL_4            0x00000040U  /* k = min (n, 4) */
-#define ETH_MACCR_BL_1            0x00000060U  /* k = min (n, 1) */
-#define ETH_MACCR_DC              0x00000010U  /* Defferal check */
-#define ETH_MACCR_TE              0x00000008U  /* Transmitter enable */
-#define ETH_MACCR_RE              0x00000004U  /* Receiver enable */
-
-/* Bit definition for Ethernet MAC Frame Filter Register */
-#define ETH_MACFFR_RA             0x80000000U  /* Receive all */
-#define ETH_MACFFR_HPF            0x00000400U  /* Hash or perfect filter */
-#define ETH_MACFFR_SAF            0x00000200U  /* Source address filter enable */
-#define ETH_MACFFR_SAIF           0x00000100U  /* SA inverse filtering */
-#define ETH_MACFFR_PCF            0x000000C0U  /* Pass control frames: 3 cases */
-#define ETH_MACFFR_PCF_BlockAll                0x00000040U  /* MAC filters all control frames from reaching the application */
-#define ETH_MACFFR_PCF_ForwardAll              0x00000080U  /* MAC forwards all control frames to application even if they fail the Address Filter */
-#define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U  /* MAC forwards control frames that pass the Address Filter. */
-#define ETH_MACFFR_BFD             0x00000020U  /* Broadcast frame disable */
-#define ETH_MACFFR_PAM             0x00000010U  /* Pass all mutlicast */
-#define ETH_MACFFR_DAIF            0x00000008U  /* DA Inverse filtering */
-#define ETH_MACFFR_HM              0x00000004U  /* Hash multicast */
-#define ETH_MACFFR_HU              0x00000002U  /* Hash unicast */
-#define ETH_MACFFR_PM              0x00000001U  /* Promiscuous mode */
-
-/* Bit definition for Ethernet MAC Hash Table High Register */
-#define ETH_MACHTHR_HTH            0xFFFFFFFFU  /* Hash table high */
-
-/* Bit definition for Ethernet MAC Hash Table Low Register */
-#define ETH_MACHTLR_HTL            0xFFFFFFFFU  /* Hash table low */
-
-/* Bit definition for Ethernet MAC MII Address Register */
-#define ETH_MACMIIAR_PA            0x0000F800U  /* Physical layer address */
-#define ETH_MACMIIAR_MR            0x000007C0U  /* MII register in the selected PHY */
-#define ETH_MACMIIAR_CR            0x0000001CU  /* CR clock range: 6 cases */
-#define ETH_MACMIIAR_CR_Div42      0x00000000U  /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
-#define ETH_MACMIIAR_CR_Div62      0x00000004U  /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
-#define ETH_MACMIIAR_CR_Div16      0x00000008U  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
-#define ETH_MACMIIAR_CR_Div26      0x0000000CU  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
-#define ETH_MACMIIAR_CR_Div102     0x00000010U  /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
-#define ETH_MACMIIAR_MW            0x00000002U  /* MII write */
-#define ETH_MACMIIAR_MB            0x00000001U  /* MII busy */
-
-/* Bit definition for Ethernet MAC MII Data Register */
-#define ETH_MACMIIDR_MD            0x0000FFFFU  /* MII data: read/write data from/to PHY */
-
-/* Bit definition for Ethernet MAC Flow Control Register */
-#define ETH_MACFCR_PT              0xFFFF0000U  /* Pause time */
-#define ETH_MACFCR_ZQPD            0x00000080U  /* Zero-quanta pause disable */
-#define ETH_MACFCR_PLT             0x00000030U  /* Pause low threshold: 4 cases */
-#define ETH_MACFCR_PLT_Minus4      0x00000000U  /* Pause time minus 4 slot times */
-#define ETH_MACFCR_PLT_Minus28     0x00000010U  /* Pause time minus 28 slot times */
-#define ETH_MACFCR_PLT_Minus144    0x00000020U  /* Pause time minus 144 slot times */
-#define ETH_MACFCR_PLT_Minus256    0x00000030U  /* Pause time minus 256 slot times */
-#define ETH_MACFCR_UPFD            0x00000008U  /* Unicast pause frame detect */
-#define ETH_MACFCR_RFCE            0x00000004U  /* Receive flow control enable */
-#define ETH_MACFCR_TFCE            0x00000002U  /* Transmit flow control enable */
-#define ETH_MACFCR_FCBBPA          0x00000001U  /* Flow control busy/backpressure activate */
-
-/* Bit definition for Ethernet MAC VLAN Tag Register */
-#define ETH_MACVLANTR_VLANTC       0x00010000U  /* 12-bit VLAN tag comparison */
-#define ETH_MACVLANTR_VLANTI       0x0000FFFFU  /* VLAN tag identifier (for receive frames) */
-
-/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
-#define ETH_MACRWUFFR_D            0xFFFFFFFFU  /* Wake-up frame filter register data */
-/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
-   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
-/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
-   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
-   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
-   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
-   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
-                              RSVD - Filter1 Command - RSVD - Filter0 Command
-   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
-   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
-   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
-
-/* Bit definition for Ethernet MAC PMT Control and Status Register */
-#define ETH_MACPMTCSR_WFFRPR       0x80000000U  /* Wake-Up Frame Filter Register Pointer Reset */
-#define ETH_MACPMTCSR_GU           0x00000200U  /* Global Unicast */
-#define ETH_MACPMTCSR_WFR          0x00000040U  /* Wake-Up Frame Received */
-#define ETH_MACPMTCSR_MPR          0x00000020U  /* Magic Packet Received */
-#define ETH_MACPMTCSR_WFE          0x00000004U  /* Wake-Up Frame Enable */
-#define ETH_MACPMTCSR_MPE          0x00000002U  /* Magic Packet Enable */
-#define ETH_MACPMTCSR_PD           0x00000001U  /* Power Down */
-
-/* Bit definition for Ethernet MAC Status Register */
-#define ETH_MACSR_TSTS      0x00000200U  /* Time stamp trigger status */
-#define ETH_MACSR_MMCTS     0x00000040U  /* MMC transmit status */
-#define ETH_MACSR_MMMCRS    0x00000020U  /* MMC receive status */
-#define ETH_MACSR_MMCS      0x00000010U  /* MMC status */
-#define ETH_MACSR_PMTS      0x00000008U  /* PMT status */
-
-/* Bit definition for Ethernet MAC Interrupt Mask Register */
-#define ETH_MACIMR_TSTIM     0x00000200U  /* Time stamp trigger interrupt mask */
-#define ETH_MACIMR_PMTIM     0x00000008U  /* PMT interrupt mask */
-
-/* Bit definition for Ethernet MAC Address0 High Register */
-#define ETH_MACA0HR_MACA0H   0x0000FFFFU  /* MAC address0 high */
-
-/* Bit definition for Ethernet MAC Address0 Low Register */
-#define ETH_MACA0LR_MACA0L   0xFFFFFFFFU  /* MAC address0 low */
-
-/* Bit definition for Ethernet MAC Address1 High Register */
-#define ETH_MACA1HR_AE       0x80000000U  /* Address enable */
-#define ETH_MACA1HR_SA       0x40000000U  /* Source address */
-#define ETH_MACA1HR_MBC      0x3F000000U  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
-  #define ETH_MACA1HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA1HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA1HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA1HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA1HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA1HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [7:0] */
-#define ETH_MACA1HR_MACA1H            0x0000FFFFU  /* MAC address1 high */
-
-/* Bit definition for Ethernet MAC Address1 Low Register */
-#define ETH_MACA1LR_MACA1L   0xFFFFFFFFU  /* MAC address1 low */
-
-/* Bit definition for Ethernet MAC Address2 High Register */
-#define ETH_MACA2HR_AE       0x80000000U  /* Address enable */
-#define ETH_MACA2HR_SA       0x40000000U  /* Source address */
-#define ETH_MACA2HR_MBC      0x3F000000U  /* Mask byte control */
-  #define ETH_MACA2HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA2HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA2HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA2HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA2HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA2HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA2HR_MACA2H   0x0000FFFFU  /* MAC address1 high */
-
-/* Bit definition for Ethernet MAC Address2 Low Register */
-#define ETH_MACA2LR_MACA2L   0xFFFFFFFFU  /* MAC address2 low */
-
-/* Bit definition for Ethernet MAC Address3 High Register */
-#define ETH_MACA3HR_AE       0x80000000U  /* Address enable */
-#define ETH_MACA3HR_SA       0x40000000U  /* Source address */
-#define ETH_MACA3HR_MBC      0x3F000000U  /* Mask byte control */
-  #define ETH_MACA3HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA3HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA3HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA3HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA3HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA3HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA3HR_MACA3H   0x0000FFFFU  /* MAC address3 high */
-
-/* Bit definition for Ethernet MAC Address3 Low Register */
-#define ETH_MACA3LR_MACA3L   0xFFFFFFFFU  /* MAC address3 low */
-
-/******************************************************************************/
-/*                Ethernet MMC Registers bits definition                      */
-/******************************************************************************/
-
-/* Bit definition for Ethernet MMC Contol Register */
-#define ETH_MMCCR_MCFHP      0x00000020U  /* MMC counter Full-Half preset */
-#define ETH_MMCCR_MCP        0x00000010U  /* MMC counter preset */
-#define ETH_MMCCR_MCF        0x00000008U  /* MMC Counter Freeze */
-#define ETH_MMCCR_ROR        0x00000004U  /* Reset on Read */
-#define ETH_MMCCR_CSR        0x00000002U  /* Counter Stop Rollover */
-#define ETH_MMCCR_CR         0x00000001U  /* Counters Reset */
-
-/* Bit definition for Ethernet MMC Receive Interrupt Register */
-#define ETH_MMCRIR_RGUFS     0x00020000U  /* Set when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIR_RFAES     0x00000040U  /* Set when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIR_RFCES     0x00000020U  /* Set when Rx crc error counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmit Interrupt Register */
-#define ETH_MMCTIR_TGFS      0x00200000U  /* Set when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFMSCS   0x00008000U  /* Set when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFSCS    0x00004000U  /* Set when Tx good single col counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
-#define ETH_MMCRIMR_RGUFM    0x00020000U  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFAEM    0x00000040U  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFCEM    0x00000020U  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
-#define ETH_MMCTIMR_TGFM     0x00200000U  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFMSCM  0x00008000U  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFSCM   0x00004000U  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
-#define ETH_MMCTGFSCCR_TGFSCC     0xFFFFFFFFU  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
-#define ETH_MMCTGFMSCCR_TGFMSCC   0xFFFFFFFFU  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
-#define ETH_MMCTGFCR_TGFC    0xFFFFFFFFU  /* Number of good frames transmitted. */
-
-/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
-#define ETH_MMCRFCECR_RFCEC  0xFFFFFFFFU  /* Number of frames received with CRC error. */
-
-/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
-#define ETH_MMCRFAECR_RFAEC  0xFFFFFFFFU  /* Number of frames received with alignment (dribble) error */
-
-/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
-#define ETH_MMCRGUFCR_RGUFC  0xFFFFFFFFU  /* Number of good unicast frames received. */
-
-/******************************************************************************/
-/*               Ethernet PTP Registers bits definition                       */
-/******************************************************************************/
-
-/* Bit definition for Ethernet PTP Time Stamp Contol Register */
-#define ETH_PTPTSCR_TSCNT       0x00030000U  /* Time stamp clock node type */
-#define ETH_PTPTSSR_TSSMRME     0x00008000U  /* Time stamp snapshot for message relevant to master enable */
-#define ETH_PTPTSSR_TSSEME      0x00004000U  /* Time stamp snapshot for event message enable */
-#define ETH_PTPTSSR_TSSIPV4FE   0x00002000U  /* Time stamp snapshot for IPv4 frames enable */
-#define ETH_PTPTSSR_TSSIPV6FE   0x00001000U  /* Time stamp snapshot for IPv6 frames enable */
-#define ETH_PTPTSSR_TSSPTPOEFE  0x00000800U  /* Time stamp snapshot for PTP over ethernet frames enable */
-#define ETH_PTPTSSR_TSPTPPSV2E  0x00000400U  /* Time stamp PTP packet snooping for version2 format enable */
-#define ETH_PTPTSSR_TSSSR       0x00000200U  /* Time stamp Sub-seconds rollover */
-#define ETH_PTPTSSR_TSSARFE     0x00000100U  /* Time stamp snapshot for all received frames enable */
-
-#define ETH_PTPTSCR_TSARU       0x00000020U  /* Addend register update */
-#define ETH_PTPTSCR_TSITE       0x00000010U  /* Time stamp interrupt trigger enable */
-#define ETH_PTPTSCR_TSSTU       0x00000008U  /* Time stamp update */
-#define ETH_PTPTSCR_TSSTI       0x00000004U  /* Time stamp initialize */
-#define ETH_PTPTSCR_TSFCU       0x00000002U  /* Time stamp fine or coarse update */
-#define ETH_PTPTSCR_TSE         0x00000001U  /* Time stamp enable */
-
-/* Bit definition for Ethernet PTP Sub-Second Increment Register */
-#define ETH_PTPSSIR_STSSI      0x000000FFU   /* System time Sub-second increment value */
-
-/* Bit definition for Ethernet PTP Time Stamp High Register */
-#define ETH_PTPTSHR_STS        0xFFFFFFFFU   /* System Time second */
-
-/* Bit definition for Ethernet PTP Time Stamp Low Register */
-#define ETH_PTPTSLR_STPNS      0x80000000U  /* System Time Positive or negative time */
-#define ETH_PTPTSLR_STSS       0x7FFFFFFFU  /* System Time sub-seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp High Update Register */
-#define ETH_PTPTSHUR_TSUS      0xFFFFFFFFU  /* Time stamp update seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
-#define ETH_PTPTSLUR_TSUPNS    0x80000000U  /* Time stamp update Positive or negative time */
-#define ETH_PTPTSLUR_TSUSS     0x7FFFFFFFU  /* Time stamp update sub-seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp Addend Register */
-#define ETH_PTPTSAR_TSA        0xFFFFFFFFU  /* Time stamp addend */
-
-/* Bit definition for Ethernet PTP Target Time High Register */
-#define ETH_PTPTTHR_TTSH       0xFFFFFFFFU  /* Target time stamp high */
-
-/* Bit definition for Ethernet PTP Target Time Low Register */
-#define ETH_PTPTTLR_TTSL       0xFFFFFFFFU  /* Target time stamp low */
-
-/* Bit definition for Ethernet PTP Time Stamp Status Register */
-#define ETH_PTPTSSR_TSTTR      0x00000020U  /* Time stamp target time reached */
-#define ETH_PTPTSSR_TSSO       0x00000010U  /* Time stamp seconds overflow */
-
-/******************************************************************************/
-/*                 Ethernet DMA Registers bits definition                     */
-/******************************************************************************/
-
-/* Bit definition for Ethernet DMA Bus Mode Register */
-#define ETH_DMABMR_AAB        0x02000000U  /* Address-Aligned beats */
-#define ETH_DMABMR_FPM        0x01000000U  /* 4xPBL mode */
-#define ETH_DMABMR_USP        0x00800000U  /* Use separate PBL */
-#define ETH_DMABMR_RDP        0x007E0000U  /* RxDMA PBL */
-  #define ETH_DMABMR_RDP_1Beat    0x00020000U  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
-  #define ETH_DMABMR_RDP_2Beat    0x00040000U  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
-  #define ETH_DMABMR_RDP_4Beat    0x00080000U  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-  #define ETH_DMABMR_RDP_8Beat    0x00100000U  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-  #define ETH_DMABMR_RDP_16Beat   0x00200000U  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-  #define ETH_DMABMR_RDP_32Beat   0x00400000U  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
-  #define ETH_DMABMR_RDP_4xPBL_4Beat   0x01020000U  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-  #define ETH_DMABMR_RDP_4xPBL_8Beat   0x01040000U  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-  #define ETH_DMABMR_RDP_4xPBL_16Beat  0x01080000U  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-  #define ETH_DMABMR_RDP_4xPBL_32Beat  0x01100000U  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
-  #define ETH_DMABMR_RDP_4xPBL_64Beat  0x01200000U  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
-  #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
-#define ETH_DMABMR_FB        0x00010000U  /* Fixed Burst */
-#define ETH_DMABMR_RTPR      0x0000C000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_1_1     0x00000000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_2_1     0x00004000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_3_1     0x00008000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_4_1     0x0000C000U  /* Rx Tx priority ratio */
-#define ETH_DMABMR_PBL    0x00003F00U  /* Programmable burst length */
-  #define ETH_DMABMR_PBL_1Beat    0x00000100U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
-  #define ETH_DMABMR_PBL_2Beat    0x00000200U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
-  #define ETH_DMABMR_PBL_4Beat    0x00000400U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-  #define ETH_DMABMR_PBL_8Beat    0x00000800U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-  #define ETH_DMABMR_PBL_16Beat   0x00001000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-  #define ETH_DMABMR_PBL_32Beat   0x00002000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
-  #define ETH_DMABMR_PBL_4xPBL_4Beat   0x01000100U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-  #define ETH_DMABMR_PBL_4xPBL_8Beat   0x01000200U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-  #define ETH_DMABMR_PBL_4xPBL_16Beat  0x01000400U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-  #define ETH_DMABMR_PBL_4xPBL_32Beat  0x01000800U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
-  #define ETH_DMABMR_PBL_4xPBL_64Beat  0x01001000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
-  #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
-#define ETH_DMABMR_EDE       0x00000080U  /* Enhanced Descriptor Enable */
-#define ETH_DMABMR_DSL       0x0000007CU  /* Descriptor Skip Length */
-#define ETH_DMABMR_DA        0x00000002U  /* DMA arbitration scheme */
-#define ETH_DMABMR_SR        0x00000001U  /* Software reset */
-
-/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
-#define ETH_DMATPDR_TPD      0xFFFFFFFFU  /* Transmit poll demand */
-
-/* Bit definition for Ethernet DMA Receive Poll Demand Register */
-#define ETH_DMARPDR_RPD      0xFFFFFFFFU  /* Receive poll demand  */
-
-/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
-#define ETH_DMARDLAR_SRL     0xFFFFFFFFU  /* Start of receive list */
-
-/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
-#define ETH_DMATDLAR_STL     0xFFFFFFFFU  /* Start of transmit list */
-
-/* Bit definition for Ethernet DMA Status Register */
-#define ETH_DMASR_TSTS       0x20000000U  /* Time-stamp trigger status */
-#define ETH_DMASR_PMTS       0x10000000U  /* PMT status */
-#define ETH_DMASR_MMCS       0x08000000U  /* MMC status */
-#define ETH_DMASR_EBS        0x03800000U  /* Error bits status */
-  /* combination with EBS[2:0] for GetFlagStatus function */
-  #define ETH_DMASR_EBS_DescAccess      0x02000000U  /* Error bits 0-data buffer, 1-desc. access */
-  #define ETH_DMASR_EBS_ReadTransf      0x01000000U  /* Error bits 0-write trnsf, 1-read transfr */
-  #define ETH_DMASR_EBS_DataTransfTx    0x00800000U  /* Error bits 0-Rx DMA, 1-Tx DMA */
-#define ETH_DMASR_TPS         0x00700000U  /* Transmit process state */
-  #define ETH_DMASR_TPS_Stopped         0x00000000U  /* Stopped - Reset or Stop Tx Command issued  */
-  #define ETH_DMASR_TPS_Fetching        0x00100000U  /* Running - fetching the Tx descriptor */
-  #define ETH_DMASR_TPS_Waiting         0x00200000U  /* Running - waiting for status */
-  #define ETH_DMASR_TPS_Reading         0x00300000U  /* Running - reading the data from host memory */
-  #define ETH_DMASR_TPS_Suspended       0x00600000U  /* Suspended - Tx Descriptor unavailabe */
-  #define ETH_DMASR_TPS_Closing         0x00700000U  /* Running - closing Rx descriptor */
-#define ETH_DMASR_RPS         0x000E0000U  /* Receive process state */
-  #define ETH_DMASR_RPS_Stopped         0x00000000U  /* Stopped - Reset or Stop Rx Command issued */
-  #define ETH_DMASR_RPS_Fetching        0x00020000U  /* Running - fetching the Rx descriptor */
-  #define ETH_DMASR_RPS_Waiting         0x00060000U  /* Running - waiting for packet */
-  #define ETH_DMASR_RPS_Suspended       0x00080000U  /* Suspended - Rx Descriptor unavailable */
-  #define ETH_DMASR_RPS_Closing         0x000A0000U  /* Running - closing descriptor */
-  #define ETH_DMASR_RPS_Queuing         0x000E0000U  /* Running - queuing the recieve frame into host memory */
-#define ETH_DMASR_NIS        0x00010000U  /* Normal interrupt summary */
-#define ETH_DMASR_AIS        0x00008000U  /* Abnormal interrupt summary */
-#define ETH_DMASR_ERS        0x00004000U  /* Early receive status */
-#define ETH_DMASR_FBES       0x00002000U  /* Fatal bus error status */
-#define ETH_DMASR_ETS        0x00000400U  /* Early transmit status */
-#define ETH_DMASR_RWTS       0x00000200U  /* Receive watchdog timeout status */
-#define ETH_DMASR_RPSS       0x00000100U  /* Receive process stopped status */
-#define ETH_DMASR_RBUS       0x00000080U  /* Receive buffer unavailable status */
-#define ETH_DMASR_RS         0x00000040U  /* Receive status */
-#define ETH_DMASR_TUS        0x00000020U  /* Transmit underflow status */
-#define ETH_DMASR_ROS        0x00000010U  /* Receive overflow status */
-#define ETH_DMASR_TJTS       0x00000008U  /* Transmit jabber timeout status */
-#define ETH_DMASR_TBUS       0x00000004U  /* Transmit buffer unavailable status */
-#define ETH_DMASR_TPSS       0x00000002U  /* Transmit process stopped status */
-#define ETH_DMASR_TS         0x00000001U  /* Transmit status */
-
-/* Bit definition for Ethernet DMA Operation Mode Register */
-#define ETH_DMAOMR_DTCEFD    0x04000000U  /* Disable Dropping of TCP/IP checksum error frames */
-#define ETH_DMAOMR_RSF       0x02000000U  /* Receive store and forward */
-#define ETH_DMAOMR_DFRF      0x01000000U  /* Disable flushing of received frames */
-#define ETH_DMAOMR_TSF       0x00200000U  /* Transmit store and forward */
-#define ETH_DMAOMR_FTF       0x00100000U  /* Flush transmit FIFO */
-#define ETH_DMAOMR_TTC       0x0001C000U  /* Transmit threshold control */
-  #define ETH_DMAOMR_TTC_64Bytes       0x00000000U  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
-  #define ETH_DMAOMR_TTC_128Bytes      0x00004000U  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
-  #define ETH_DMAOMR_TTC_192Bytes      0x00008000U  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
-  #define ETH_DMAOMR_TTC_256Bytes      0x0000C000U  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
-  #define ETH_DMAOMR_TTC_40Bytes       0x00010000U  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
-  #define ETH_DMAOMR_TTC_32Bytes       0x00014000U  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
-  #define ETH_DMAOMR_TTC_24Bytes       0x00018000U  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
-  #define ETH_DMAOMR_TTC_16Bytes       0x0001C000U  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
-#define ETH_DMAOMR_ST        0x00002000U  /* Start/stop transmission command */
-#define ETH_DMAOMR_FEF       0x00000080U  /* Forward error frames */
-#define ETH_DMAOMR_FUGF      0x00000040U  /* Forward undersized good frames */
-#define ETH_DMAOMR_RTC       0x00000018U  /* receive threshold control */
-  #define ETH_DMAOMR_RTC_64Bytes       0x00000000U  /* threshold level of the MTL Receive FIFO is 64 Bytes */
-  #define ETH_DMAOMR_RTC_32Bytes       0x00000008U  /* threshold level of the MTL Receive FIFO is 32 Bytes */
-  #define ETH_DMAOMR_RTC_96Bytes       0x00000010U  /* threshold level of the MTL Receive FIFO is 96 Bytes */
-  #define ETH_DMAOMR_RTC_128Bytes      0x00000018U  /* threshold level of the MTL Receive FIFO is 128 Bytes */
-#define ETH_DMAOMR_OSF       0x00000004U  /* operate on second frame */
-#define ETH_DMAOMR_SR        0x00000002U  /* Start/stop receive */
-
-/* Bit definition for Ethernet DMA Interrupt Enable Register */
-#define ETH_DMAIER_NISE      0x00010000U  /* Normal interrupt summary enable */
-#define ETH_DMAIER_AISE      0x00008000U  /* Abnormal interrupt summary enable */
-#define ETH_DMAIER_ERIE      0x00004000U  /* Early receive interrupt enable */
-#define ETH_DMAIER_FBEIE     0x00002000U  /* Fatal bus error interrupt enable */
-#define ETH_DMAIER_ETIE      0x00000400U  /* Early transmit interrupt enable */
-#define ETH_DMAIER_RWTIE     0x00000200U  /* Receive watchdog timeout interrupt enable */
-#define ETH_DMAIER_RPSIE     0x00000100U  /* Receive process stopped interrupt enable */
-#define ETH_DMAIER_RBUIE     0x00000080U  /* Receive buffer unavailable interrupt enable */
-#define ETH_DMAIER_RIE       0x00000040U  /* Receive interrupt enable */
-#define ETH_DMAIER_TUIE      0x00000020U  /* Transmit Underflow interrupt enable */
-#define ETH_DMAIER_ROIE      0x00000010U  /* Receive Overflow interrupt enable */
-#define ETH_DMAIER_TJTIE     0x00000008U  /* Transmit jabber timeout interrupt enable */
-#define ETH_DMAIER_TBUIE     0x00000004U  /* Transmit buffer unavailable interrupt enable */
-#define ETH_DMAIER_TPSIE     0x00000002U  /* Transmit process stopped interrupt enable */
-#define ETH_DMAIER_TIE       0x00000001U  /* Transmit interrupt enable */
-
-/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
-#define ETH_DMAMFBOCR_OFOC   0x10000000U  /* Overflow bit for FIFO overflow counter */
-#define ETH_DMAMFBOCR_MFA    0x0FFE0000U  /* Number of frames missed by the application */
-#define ETH_DMAMFBOCR_OMFC   0x00010000U  /* Overflow bit for missed frame counter */
-#define ETH_DMAMFBOCR_MFC    0x0000FFFFU  /* Number of frames missed by the controller */
-
-/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
-#define ETH_DMACHTDR_HTDAP   0xFFFFFFFFU  /* Host transmit descriptor address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
-#define ETH_DMACHRDR_HRDAP   0xFFFFFFFFU  /* Host receive descriptor address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
-#define ETH_DMACHTBAR_HTBAP  0xFFFFFFFFU  /* Host transmit buffer address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
-#define ETH_DMACHRBAR_HRBAP  0xFFFFFFFFU  /* Host receive buffer address pointer */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                       USB_OTG                              */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for USB_OTG_GOTGCTL register  ********************/
-#define USB_OTG_GOTGCTL_SRQSCS                  0x00000001U         /*!< Session request success */
-#define USB_OTG_GOTGCTL_SRQ                     0x00000002U         /*!< Session request */
-#define USB_OTG_GOTGCTL_VBVALOEN                0x00000004U         /*!< VBUS valid override enable */
-#define USB_OTG_GOTGCTL_VBVALOVAL               0x00000008U         /*!< VBUS valid override value */
-#define USB_OTG_GOTGCTL_AVALOEN                 0x00000010U         /*!< A-peripheral session valid override enable */
-#define USB_OTG_GOTGCTL_AVALOVAL                0x00000020U         /*!< A-peripheral session valid override value */
-#define USB_OTG_GOTGCTL_BVALOEN                 0x00000040U         /*!< B-peripheral session valid override enable */
-#define USB_OTG_GOTGCTL_BVALOVAL                0x00000080U         /*!< B-peripheral session valid override value  */
-#define USB_OTG_GOTGCTL_HNGSCS                  0x00000100U         /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_HNPRQ                   0x00000200U         /*!< HNP request */
-#define USB_OTG_GOTGCTL_HSHNPEN                 0x00000400U         /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_DHNPEN                  0x00000800U         /*!< Device HNP enabled */
-#define USB_OTG_GOTGCTL_EHEN                    0x00001000U         /*!< Embedded host enable */
-#define USB_OTG_GOTGCTL_CIDSTS                  0x00010000U         /*!< Connector ID status */
-#define USB_OTG_GOTGCTL_DBCT                    0x00020000U         /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD                   0x00040000U         /*!< A-session valid  */
-#define USB_OTG_GOTGCTL_BSESVLD                 0x00080000U         /*!< B-session valid */
-#define USB_OTG_GOTGCTL_OTGVER                  0x00100000U         /*!< OTG version  */
-
-/********************  Bit definition for USB_OTG_HCFG register  ********************/
-#define USB_OTG_HCFG_FSLSPCS                 0x00000003U            /*!< FS/LS PHY clock select  */
-#define USB_OTG_HCFG_FSLSPCS_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCFG_FSLSPCS_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCFG_FSLSS                   0x00000004U            /*!< FS- and LS-only support */
-
-/********************  Bit definition for USB_OTG_DCFG register  ********************/
-#define USB_OTG_DCFG_DSPD                    0x00000003U            /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                  0x00000001U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DSPD_1                  0x00000002U            /*!<Bit 1 */
-#define USB_OTG_DCFG_NZLSOHSK                0x00000004U            /*!< Nonzero-length status OUT handshake */
-
-#define USB_OTG_DCFG_DAD                     0x000007F0U            /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                   0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DAD_1                   0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCFG_DAD_2                   0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCFG_DAD_3                   0x00000080U            /*!<Bit 3 */
-#define USB_OTG_DCFG_DAD_4                   0x00000100U            /*!<Bit 4 */
-#define USB_OTG_DCFG_DAD_5                   0x00000200U            /*!<Bit 5 */
-#define USB_OTG_DCFG_DAD_6                   0x00000400U            /*!<Bit 6 */
-
-#define USB_OTG_DCFG_PFIVL                   0x00001800U            /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PFIVL_1                 0x00001000U            /*!<Bit 1 */
-
-#define USB_OTG_DCFG_PERSCHIVL               0x03000000U            /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0             0x01000000U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PERSCHIVL_1             0x02000000U            /*!<Bit 1 */
-
-/********************  Bit definition for USB_OTG_PCGCR register  ********************/
-#define USB_OTG_PCGCR_STPPCLK                 0x00000001U            /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK                0x00000002U            /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP                 0x00000010U            /*!< PHY suspended */
-
-/********************  Bit definition for USB_OTG_GOTGINT register  ********************/
-#define USB_OTG_GOTGINT_SEDET                   0x00000004U            /*!< Session end detected                   */
-#define USB_OTG_GOTGINT_SRSSCHG                 0x00000100U            /*!< Session request success status change  */
-#define USB_OTG_GOTGINT_HNSSCHG                 0x00000200U            /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET                  0x00020000U            /*!< Host negotiation detected              */
-#define USB_OTG_GOTGINT_ADTOCHG                 0x00040000U            /*!< A-device timeout change                */
-#define USB_OTG_GOTGINT_DBCDNE                  0x00080000U            /*!< Debounce done                          */
-#define USB_OTG_GOTGINT_IDCHNG                  0x00100000U            /*!< Change in ID pin input value           */
-
-/********************  Bit definition for USB_OTG_DCTL register  ********************/
-#define USB_OTG_DCTL_RWUSIG                  0x00000001U            /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS                    0x00000002U            /*!< Soft disconnect         */
-#define USB_OTG_DCTL_GINSTS                  0x00000004U            /*!< Global IN NAK status    */
-#define USB_OTG_DCTL_GONSTS                  0x00000008U            /*!< Global OUT NAK status   */
-
-#define USB_OTG_DCTL_TCTL                    0x00000070U            /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                  0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCTL_TCTL_1                  0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCTL_TCTL_2                  0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCTL_SGINAK                  0x00000080U            /*!< Set global IN NAK         */
-#define USB_OTG_DCTL_CGINAK                  0x00000100U            /*!< Clear global IN NAK       */
-#define USB_OTG_DCTL_SGONAK                  0x00000200U            /*!< Set global OUT NAK        */
-#define USB_OTG_DCTL_CGONAK                  0x00000400U            /*!< Clear global OUT NAK      */
-#define USB_OTG_DCTL_POPRGDNE                0x00000800U            /*!< Power-on programming done */
-
-/********************  Bit definition for USB_OTG_HFIR register  ********************/
-#define USB_OTG_HFIR_FRIVL                   0x0000FFFFU            /*!< Frame interval */
-
-/********************  Bit definition for USB_OTG_HFNUM register  ********************/
-#define USB_OTG_HFNUM_FRNUM                   0x0000FFFFU            /*!< Frame number         */
-#define USB_OTG_HFNUM_FTREM                   0xFFFF0000U            /*!< Frame time remaining */
-
-/********************  Bit definition for USB_OTG_DSTS register  ********************/
-#define USB_OTG_DSTS_SUSPSTS                 0x00000001U            /*!< Suspend status   */
-
-#define USB_OTG_DSTS_ENUMSPD                 0x00000006U            /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_DSTS_ENUMSPD_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_DSTS_EERR                    0x00000008U            /*!< Erratic error     */
-#define USB_OTG_DSTS_FNSOF                   0x003FFF00U            /*!< Frame number of the received SOF */
-
-/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
-#define USB_OTG_GAHBCFG_GINT                    0x00000001U            /*!< Global interrupt mask */
-#define USB_OTG_GAHBCFG_HBSTLEN                 0x0000001EU            /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_GAHBCFG_HBSTLEN_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_GAHBCFG_HBSTLEN_2               0x00000008U            /*!<Bit 2 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3               0x00000010U            /*!<Bit 3 */
-#define USB_OTG_GAHBCFG_DMAEN                   0x00000020U            /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL                 0x00000080U            /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL                0x00000100U            /*!< Periodic TxFIFO empty level */
-
-/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
-#define USB_OTG_GUSBCFG_TOCAL                   0x00000007U            /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TOCAL_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TOCAL_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_PHYSEL                  0x00000040U            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP                  0x00000100U            /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP                  0x00000200U            /*!< HNP-capable */
-#define USB_OTG_GUSBCFG_TRDT                    0x00003C00U            /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                  0x00000400U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TRDT_1                  0x00000800U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TRDT_2                  0x00001000U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_TRDT_3                  0x00002000U            /*!<Bit 3 */
-#define USB_OTG_GUSBCFG_PHYLPCS                 0x00008000U            /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS                0x00020000U            /*!< ULPI FS/LS select               */
-#define USB_OTG_GUSBCFG_ULPIAR                  0x00040000U            /*!< ULPI Auto-resume                */
-#define USB_OTG_GUSBCFG_ULPICSM                 0x00080000U            /*!< ULPI Clock SuspendM             */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD              0x00100000U            /*!< ULPI External VBUS Drive        */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI              0x00200000U            /*!< ULPI external VBUS indicator    */
-#define USB_OTG_GUSBCFG_TSDPS                   0x00400000U            /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI                    0x00800000U            /*!< Indicator complement            */
-#define USB_OTG_GUSBCFG_PTCI                    0x01000000U            /*!< Indicator pass through          */
-#define USB_OTG_GUSBCFG_ULPIIPD                 0x02000000U            /*!< ULPI interface protect disable  */
-#define USB_OTG_GUSBCFG_FHMOD                   0x20000000U            /*!< Forced host mode                */
-#define USB_OTG_GUSBCFG_FDMOD                   0x40000000U            /*!< Forced peripheral mode          */
-#define USB_OTG_GUSBCFG_CTXPKT                  0x80000000U            /*!< Corrupt Tx packet               */
-
-/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
-#define USB_OTG_GRSTCTL_CSRST                   0x00000001U            /*!< Core soft reset          */
-#define USB_OTG_GRSTCTL_HSRST                   0x00000002U            /*!< HCLK soft reset          */
-#define USB_OTG_GRSTCTL_FCRST                   0x00000004U            /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH                 0x00000010U            /*!< RxFIFO flush             */
-#define USB_OTG_GRSTCTL_TXFFLSH                 0x00000020U            /*!< TxFIFO flush             */
-#define USB_OTG_GRSTCTL_TXFNUM                  0x000007C0U            /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                0x00000040U            /*!<Bit 0 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                0x00000080U            /*!<Bit 1 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                0x00000100U            /*!<Bit 2 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                0x00000200U            /*!<Bit 3 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                0x00000400U            /*!<Bit 4 */
-#define USB_OTG_GRSTCTL_DMAREQ                  0x40000000U            /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL                  0x80000000U            /*!< AHB master idle */
-
-/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
-#define USB_OTG_DIEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask                 */
-#define USB_OTG_DIEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask                  */
-#define USB_OTG_DIEPMSK_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask          */
-#define USB_OTG_DIEPMSK_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask           */
-#define USB_OTG_DIEPMSK_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask                    */
-#define USB_OTG_DIEPMSK_TXFURM                  0x00000100U            /*!< FIFO underrun mask                                */
-#define USB_OTG_DIEPMSK_BIM                     0x00000200U            /*!< BNA interrupt mask                                */
-
-/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
-#define USB_OTG_HPTXSTS_PTXFSAVL                0x0000FFFFU            /*!< Periodic transmit data FIFO space available     */
-#define USB_OTG_HPTXSTS_PTXQSAV                 0x00FF0000U            /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0               0x00010000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1               0x00020000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2               0x00040000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3               0x00080000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4               0x00100000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5               0x00200000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6               0x00400000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7               0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_HPTXSTS_PTXQTOP                 0xFF000000U            /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0               0x01000000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1               0x02000000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2               0x04000000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3               0x08000000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4               0x10000000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5               0x20000000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6               0x40000000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7               0x80000000U            /*!<Bit 7 */
-
-/********************  Bit definition for USB_OTG_HAINT register  ********************/
-#define USB_OTG_HAINT_HAINT                     0x0000FFFFU            /*!< Channel interrupts */
-
-/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
-#define USB_OTG_DOEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask               */
-#define USB_OTG_DOEPMSK_STUPM                   0x00000008U            /*!< SETUP phase done mask                          */
-#define USB_OTG_DOEPMSK_OTEPDM                  0x00000010U            /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_OTEPSPRM                0x00000020U            /*!< Status Phase Received mask                     */
-#define USB_OTG_DOEPMSK_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received mask       */
-#define USB_OTG_DOEPMSK_OPEM                    0x00000100U            /*!< OUT packet error mask                          */
-#define USB_OTG_DOEPMSK_BOIM                    0x00000200U            /*!< BNA interrupt mask                             */
-
-/********************  Bit definition for USB_OTG_GINTSTS register  ********************/
-#define USB_OTG_GINTSTS_CMOD                    0x00000001U            /*!< Current mode of operation                      */
-#define USB_OTG_GINTSTS_MMIS                    0x00000002U            /*!< Mode mismatch interrupt                        */
-#define USB_OTG_GINTSTS_OTGINT                  0x00000004U            /*!< OTG interrupt                                  */
-#define USB_OTG_GINTSTS_SOF                     0x00000008U            /*!< Start of frame                                 */
-#define USB_OTG_GINTSTS_RXFLVL                  0x00000010U            /*!< RxFIFO nonempty                                */
-#define USB_OTG_GINTSTS_NPTXFE                  0x00000020U            /*!< Nonperiodic TxFIFO empty                       */
-#define USB_OTG_GINTSTS_GINAKEFF                0x00000040U            /*!< Global IN nonperiodic NAK effective            */
-#define USB_OTG_GINTSTS_BOUTNAKEFF              0x00000080U            /*!< Global OUT NAK effective                       */
-#define USB_OTG_GINTSTS_ESUSP                   0x00000400U            /*!< Early suspend                                  */
-#define USB_OTG_GINTSTS_USBSUSP                 0x00000800U            /*!< USB suspend                                    */
-#define USB_OTG_GINTSTS_USBRST                  0x00001000U            /*!< USB reset                                      */
-#define USB_OTG_GINTSTS_ENUMDNE                 0x00002000U            /*!< Enumeration done                               */
-#define USB_OTG_GINTSTS_ISOODRP                 0x00004000U            /*!< Isochronous OUT packet dropped interrupt       */
-#define USB_OTG_GINTSTS_EOPF                    0x00008000U            /*!< End of periodic frame interrupt                */
-#define USB_OTG_GINTSTS_IEPINT                  0x00040000U            /*!< IN endpoint interrupt                          */
-#define USB_OTG_GINTSTS_OEPINT                  0x00080000U            /*!< OUT endpoint interrupt                         */
-#define USB_OTG_GINTSTS_IISOIXFR                0x00100000U            /*!< Incomplete isochronous IN transfer             */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       0x00200000U            /*!< Incomplete periodic transfer                   */
-#define USB_OTG_GINTSTS_DATAFSUSP               0x00400000U            /*!< Data fetch suspended                           */
-#define USB_OTG_GINTSTS_RSTDET                  0x00800000U            /*!< Reset detected interrupt                       */
-#define USB_OTG_GINTSTS_HPRTINT                 0x01000000U            /*!< Host port interrupt                            */
-#define USB_OTG_GINTSTS_HCINT                   0x02000000U            /*!< Host channels interrupt                        */
-#define USB_OTG_GINTSTS_PTXFE                   0x04000000U            /*!< Periodic TxFIFO empty                          */
-#define USB_OTG_GINTSTS_LPMINT                  0x08000000U            /*!< LPM interrupt                                  */
-#define USB_OTG_GINTSTS_CIDSCHG                 0x10000000U            /*!< Connector ID status change                     */
-#define USB_OTG_GINTSTS_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt                  */
-#define USB_OTG_GINTSTS_SRQINT                  0x40000000U            /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT                  0x80000000U            /*!< Resume/remote wakeup detected interrupt        */
-
-/********************  Bit definition for USB_OTG_GINTMSK register  ********************/
-#define USB_OTG_GINTMSK_MMISM                   0x00000002U            /*!< Mode mismatch interrupt mask                        */
-#define USB_OTG_GINTMSK_OTGINT                  0x00000004U            /*!< OTG interrupt mask                                  */
-#define USB_OTG_GINTMSK_SOFM                    0x00000008U            /*!< Start of frame mask                                 */
-#define USB_OTG_GINTMSK_RXFLVLM                 0x00000010U            /*!< Receive FIFO nonempty mask                          */
-#define USB_OTG_GINTMSK_NPTXFEM                 0x00000020U            /*!< Nonperiodic TxFIFO empty mask                       */
-#define USB_OTG_GINTMSK_GINAKEFFM               0x00000040U            /*!< Global nonperiodic IN NAK effective mask            */
-#define USB_OTG_GINTMSK_GONAKEFFM               0x00000080U            /*!< Global OUT NAK effective mask                       */
-#define USB_OTG_GINTMSK_ESUSPM                  0x00000400U            /*!< Early suspend mask                                  */
-#define USB_OTG_GINTMSK_USBSUSPM                0x00000800U            /*!< USB suspend mask                                    */
-#define USB_OTG_GINTMSK_USBRST                  0x00001000U            /*!< USB reset mask                                      */
-#define USB_OTG_GINTMSK_ENUMDNEM                0x00002000U            /*!< Enumeration done mask                               */
-#define USB_OTG_GINTMSK_ISOODRPM                0x00004000U            /*!< Isochronous OUT packet dropped interrupt mask       */
-#define USB_OTG_GINTMSK_EOPFM                   0x00008000U            /*!< End of periodic frame interrupt mask                */
-#define USB_OTG_GINTMSK_EPMISM                  0x00020000U            /*!< Endpoint mismatch interrupt mask                    */
-#define USB_OTG_GINTMSK_IEPINT                  0x00040000U            /*!< IN endpoints interrupt mask                         */
-#define USB_OTG_GINTMSK_OEPINT                  0x00080000U            /*!< OUT endpoints interrupt mask                        */
-#define USB_OTG_GINTMSK_IISOIXFRM               0x00100000U            /*!< Incomplete isochronous IN transfer mask             */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         0x00200000U            /*!< Incomplete periodic transfer mask                   */
-#define USB_OTG_GINTMSK_FSUSPM                  0x00400000U            /*!< Data fetch suspended mask                           */
-#define USB_OTG_GINTMSK_RSTDEM                  0x00800000U            /*!< Reset detected interrupt mask                       */
-#define USB_OTG_GINTMSK_PRTIM                   0x01000000U            /*!< Host port interrupt mask                            */
-#define USB_OTG_GINTMSK_HCIM                    0x02000000U            /*!< Host channels interrupt mask                        */
-#define USB_OTG_GINTMSK_PTXFEM                  0x04000000U            /*!< Periodic TxFIFO empty mask                          */
-#define USB_OTG_GINTMSK_LPMINTM                 0x08000000U            /*!< LPM interrupt Mask                                  */
-#define USB_OTG_GINTMSK_CIDSCHGM                0x10000000U            /*!< Connector ID status change mask                     */
-#define USB_OTG_GINTMSK_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt mask                  */
-#define USB_OTG_GINTMSK_SRQIM                   0x40000000U            /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM                    0x80000000U            /*!< Resume/remote wakeup detected interrupt mask        */
-
-/********************  Bit definition for USB_OTG_DAINT register  ********************/
-#define USB_OTG_DAINT_IEPINT                  0x0000FFFFU            /*!< IN endpoint interrupt bits  */
-#define USB_OTG_DAINT_OEPINT                  0xFFFF0000U            /*!< OUT endpoint interrupt bits */
-
-/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
-#define USB_OTG_HAINTMSK_HAINTM                  0x0000FFFFU            /*!< Channel interrupt mask */
-
-/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
-#define USB_OTG_GRXSTSP_EPNUM                    0x0000000FU            /*!< IN EP interrupt mask bits  */
-#define USB_OTG_GRXSTSP_BCNT                     0x00007FF0U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID                     0x00018000U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS                   0x001E0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
-#define USB_OTG_DAINTMSK_IEPM                    0x0000FFFFU            /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM                    0xFFFF0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for OTG register  ********************/
-
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition for OTG register  ********************/
-
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
-#define USB_OTG_GRXFSIZ_RXFD            0x0000FFFFU            /*!< RxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
-#define USB_OTG_DVBUSDIS_VBUSDT         0x0000FFFFU            /*!< Device VBUS discharge time */
-
-/********************  Bit definition for OTG register  ********************/
-#define USB_OTG_NPTXFSA                 0x0000FFFFU            /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD                  0xFFFF0000U            /*!< Nonperiodic TxFIFO depth               */
-#define USB_OTG_TX0FSA                  0x0000FFFFU            /*!< Endpoint 0 transmit RAM start address  */
-#define USB_OTG_TX0FD                   0xFFFF0000U            /*!< Endpoint 0 TxFIFO depth                */
-
-/********************  Bit definition for USB_OTG_DVBUSPULSE register  ********************/
-#define USB_OTG_DVBUSPULSE_DVBUSP                0x00000FFFU            /*!< Device VBUS pulsing time */
-
-/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
-#define USB_OTG_GNPTXSTS_NPTXFSAV                0x0000FFFFU            /*!< Nonperiodic TxFIFO space available */
-
-#define USB_OTG_GNPTXSTS_NPTQXSAV                0x00FF0000U            /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0              0x00010000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1              0x00020000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2              0x00040000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3              0x00080000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4              0x00100000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5              0x00200000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6              0x00400000U            /*!<Bit 6 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7              0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_GNPTXSTS_NPTXQTOP                0x7F000000U            /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0              0x01000000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1              0x02000000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2              0x04000000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3              0x08000000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4              0x10000000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5              0x20000000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6              0x40000000U            /*!<Bit 6 */
-
-/********************  Bit definition for USB_OTG_DTHRCTL register  ********************/
-#define USB_OTG_DTHRCTL_NONISOTHREN             0x00000001U            /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN                0x00000002U            /*!< ISO IN endpoint threshold enable */
-
-#define USB_OTG_DTHRCTL_TXTHRLEN                0x000007FCU            /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0              0x00000004U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1              0x00000008U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2              0x00000010U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3              0x00000020U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4              0x00000040U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5              0x00000080U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6              0x00000100U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7              0x00000200U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8              0x00000400U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_RXTHREN                 0x00010000U            /*!< Receive threshold enable */
-
-#define USB_OTG_DTHRCTL_RXTHRLEN                0x03FE0000U            /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0              0x00020000U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1              0x00040000U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2              0x00080000U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3              0x00100000U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4              0x00200000U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5              0x00400000U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6              0x00800000U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7              0x01000000U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8              0x02000000U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_ARPEN                   0x08000000U            /*!< Arbiter parking enable */
-
-/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM            0x0000FFFFU         /*!< IN EP Tx FIFO empty interrupt mask bits */
-
-/********************  Bit definition for USB_OTG_DEACHINT register  ********************/
-#define USB_OTG_DEACHINT_IEP1INT                0x00000002U           /*!< IN endpoint 1interrupt bit   */
-#define USB_OTG_DEACHINT_OEP1INT                0x00020000U           /*!< OUT endpoint 1 interrupt bit */
-
-/********************  Bit definition for USB_OTG_GCCFG register  ********************/
-#define USB_OTG_GCCFG_PWRDWN                 0x00010000U              /*!< Power down */
-#define USB_OTG_GCCFG_VBDEN                  0x00200000U              /*!< USB VBUS Detection Enable */
-
-/********************  Bit definition for USB_OTG_GPWRDN) register  ********************/
-#define USB_OTG_GPWRDN_ADPMEN                 0x00000001U             /*!< ADP module enable */
-#define USB_OTG_GPWRDN_ADPIF                  0x00800000U             /*!< ADP Interrupt flag */
-
-/********************  Bit definition for USB_OTG_DEACHINTMSK register  ********************/
-#define USB_OTG_DEACHINTMSK_IEP1INTM          0x00000002U            /*!< IN Endpoint 1 interrupt mask bit  */
-#define USB_OTG_DEACHINTMSK_OEP1INTM          0x00020000U            /*!< OUT Endpoint 1 interrupt mask bit */
-
-/********************  Bit definition for USB_OTG_CID register  ********************/
-#define USB_OTG_CID_PRODUCT_ID               0xFFFFFFFFU            /*!< Product ID field */
-
-/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/
-#define  USB_OTG_GLPMCFG_LPMEN               0x00000001U            /*!< LPM support enable                                     */
-#define  USB_OTG_GLPMCFG_LPMACK              0x00000002U            /*!< LPM Token acknowledge enable                           */
-#define  USB_OTG_GLPMCFG_BESL                0x0000003CU            /*!< BESL value received with last ACKed LPM Token          */
-#define  USB_OTG_GLPMCFG_REMWAKE             0x00000040U            /*!< bRemoteWake value received with last ACKed LPM Token   */
-#define  USB_OTG_GLPMCFG_L1SSEN              0x00000080U            /*!< L1 shallow sleep enable                                */
-#define  USB_OTG_GLPMCFG_BESLTHRS            0x00000F00U            /*!< BESL threshold                                         */
-#define  USB_OTG_GLPMCFG_L1DSEN              0x00001000U            /*!< L1 deep sleep enable                                   */
-#define  USB_OTG_GLPMCFG_LPMRSP              0x00006000U            /*!< LPM response                                           */
-#define  USB_OTG_GLPMCFG_SLPSTS              0x00008000U            /*!< Port sleep status                                      */
-#define  USB_OTG_GLPMCFG_L1RSMOK             0x00010000U            /*!< Sleep State Resume OK                                  */
-#define  USB_OTG_GLPMCFG_LPMCHIDX            0x001E0000U            /*!< LPM Channel Index                                      */
-#define  USB_OTG_GLPMCFG_LPMRCNT             0x00E00000U            /*!< LPM retry count                                        */
-#define  USB_OTG_GLPMCFG_SNDLPM              0x01000000U            /*!< Send LPM transaction                                   */
-#define  USB_OTG_GLPMCFG_LPMRCNTSTS          0x0E000000U            /*!< LPM retry count status                                 */
-#define  USB_OTG_GLPMCFG_ENBESL              0x10000000U            /*!< Enable best effort service latency                     */
-
-/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
-#define USB_OTG_DIEPEACHMSK1_XFRCM           0x00000001U            /*!< Transfer completed interrupt mask                 */
-#define USB_OTG_DIEPEACHMSK1_EPDM            0x00000002U            /*!< Endpoint disabled interrupt mask                  */
-#define USB_OTG_DIEPEACHMSK1_TOM             0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK       0x00000010U            /*!< IN token received when TxFIFO empty mask          */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM         0x00000020U            /*!< IN token received with EP mismatch mask           */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM         0x00000040U            /*!< IN endpoint NAK effective mask                    */
-#define USB_OTG_DIEPEACHMSK1_TXFURM          0x00000100U            /*!< FIFO underrun mask                                */
-#define USB_OTG_DIEPEACHMSK1_BIM             0x00000200U            /*!< BNA interrupt mask                                */
-#define USB_OTG_DIEPEACHMSK1_NAKM            0x00002000U            /*!< NAK interrupt mask                                */
-
-/********************  Bit definition for USB_OTG_HPRT register  ********************/
-#define USB_OTG_HPRT_PCSTS                   0x00000001U            /*!< Port connect status        */
-#define USB_OTG_HPRT_PCDET                   0x00000002U            /*!< Port connect detected      */
-#define USB_OTG_HPRT_PENA                    0x00000004U            /*!< Port enable                */
-#define USB_OTG_HPRT_PENCHNG                 0x00000008U            /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA                    0x00000010U            /*!< Port overcurrent active    */
-#define USB_OTG_HPRT_POCCHNG                 0x00000020U            /*!< Port overcurrent change    */
-#define USB_OTG_HPRT_PRES                    0x00000040U            /*!< Port resume                */
-#define USB_OTG_HPRT_PSUSP                   0x00000080U            /*!< Port suspend               */
-#define USB_OTG_HPRT_PRST                    0x00000100U            /*!< Port reset                 */
-
-#define USB_OTG_HPRT_PLSTS                   0x00000C00U            /*!< Port line status           */
-#define USB_OTG_HPRT_PLSTS_0                 0x00000400U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PLSTS_1                 0x00000800U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PPWR                    0x00001000U            /*!< Port power                 */
-
-#define USB_OTG_HPRT_PTCTL                   0x0001E000U            /*!< Port test control          */
-#define USB_OTG_HPRT_PTCTL_0                 0x00002000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PTCTL_1                 0x00004000U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PTCTL_2                 0x00008000U            /*!<Bit 2 */
-#define USB_OTG_HPRT_PTCTL_3                 0x00010000U            /*!<Bit 3 */
-
-#define USB_OTG_HPRT_PSPD                    0x00060000U            /*!< Port speed                 */
-#define USB_OTG_HPRT_PSPD_0                  0x00020000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PSPD_1                  0x00040000U            /*!<Bit 1 */
-
-/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
-#define USB_OTG_DOEPEACHMSK1_XFRCM               0x00000001U            /*!< Transfer completed interrupt mask         */
-#define USB_OTG_DOEPEACHMSK1_EPDM                0x00000002U            /*!< Endpoint disabled interrupt mask          */
-#define USB_OTG_DOEPEACHMSK1_TOM                 0x00000008U            /*!< Timeout condition mask                    */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           0x00000010U            /*!< IN token received when TxFIFO empty mask  */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM             0x00000020U            /*!< IN token received with EP mismatch mask   */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM             0x00000040U            /*!< IN endpoint NAK effective mask            */
-#define USB_OTG_DOEPEACHMSK1_TXFURM              0x00000100U            /*!< OUT packet error mask                     */
-#define USB_OTG_DOEPEACHMSK1_BIM                 0x00000200U            /*!< BNA interrupt mask                        */
-#define USB_OTG_DOEPEACHMSK1_BERRM               0x00001000U            /*!< Bubble error interrupt mask               */
-#define USB_OTG_DOEPEACHMSK1_NAKM                0x00002000U            /*!< NAK interrupt mask                        */
-#define USB_OTG_DOEPEACHMSK1_NYETM               0x00004000U            /*!< NYET interrupt mask                       */
-
-/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
-#define USB_OTG_HPTXFSIZ_PTXSA                   0x0000FFFFU            /*!< Host periodic TxFIFO start address            */
-#define USB_OTG_HPTXFSIZ_PTXFD                   0xFFFF0000U            /*!< Host periodic TxFIFO depth                    */
-
-/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
-#define USB_OTG_DIEPCTL_MPSIZ                   0x000007FFU            /*!< Maximum packet size              */
-#define USB_OTG_DIEPCTL_USBAEP                  0x00008000U            /*!< USB active endpoint              */
-#define USB_OTG_DIEPCTL_EONUM_DPID              0x00010000U            /*!< Even/odd frame                   */
-#define USB_OTG_DIEPCTL_NAKSTS                  0x00020000U            /*!< NAK status                       */
-
-#define USB_OTG_DIEPCTL_EPTYP                   0x000C0000U            /*!< Endpoint type                    */
-#define USB_OTG_DIEPCTL_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_STALL                   0x00200000U            /*!< STALL handshake                  */
-
-#define USB_OTG_DIEPCTL_TXFNUM                  0x03C00000U            /*!< TxFIFO number                    */
-#define USB_OTG_DIEPCTL_TXFNUM_0                0x00400000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                0x00800000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                0x01000000U            /*!<Bit 2 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                0x02000000U            /*!<Bit 3 */
-#define USB_OTG_DIEPCTL_CNAK                    0x04000000U            /*!< Clear NAK                        */
-#define USB_OTG_DIEPCTL_SNAK                    0x08000000U            /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          0x10000000U            /*!< Set DATA0 PID                    */
-#define USB_OTG_DIEPCTL_SODDFRM                 0x20000000U            /*!< Set odd frame                    */
-#define USB_OTG_DIEPCTL_EPDIS                   0x40000000U            /*!< Endpoint disable                 */
-#define USB_OTG_DIEPCTL_EPENA                   0x80000000U            /*!< Endpoint enable                  */
-
-/********************  Bit definition for USB_OTG_HCCHAR register  ********************/
-#define USB_OTG_HCCHAR_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
-
-#define USB_OTG_HCCHAR_EPNUM                   0x00007800U            /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPNUM_1                 0x00001000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_EPNUM_2                 0x00002000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_EPNUM_3                 0x00004000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_EPDIR                   0x00008000U            /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV                   0x00020000U            /*!< Low-speed device */
-
-#define USB_OTG_HCCHAR_EPTYP                   0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_MC                      0x00300000U            /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                    0x00100000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_MC_1                    0x00200000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_DAD                     0x1FC00000U            /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                   0x00400000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_DAD_1                   0x00800000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_DAD_2                   0x01000000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_DAD_3                   0x02000000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_DAD_4                   0x04000000U            /*!<Bit 4 */
-#define USB_OTG_HCCHAR_DAD_5                   0x08000000U            /*!<Bit 5 */
-#define USB_OTG_HCCHAR_DAD_6                   0x10000000U            /*!<Bit 6 */
-#define USB_OTG_HCCHAR_ODDFRM                  0x20000000U            /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS                   0x40000000U            /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA                   0x80000000U            /*!< Channel enable */
-
-/********************  Bit definition for USB_OTG_HCSPLT register  ********************/
-
-#define USB_OTG_HCSPLT_PRTADDR                 0x0000007FU            /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_PRTADDR_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_PRTADDR_2               0x00000004U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_PRTADDR_3               0x00000008U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_PRTADDR_4               0x00000010U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_PRTADDR_5               0x00000020U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_PRTADDR_6               0x00000040U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_HUBADDR                 0x00003F80U            /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0               0x00000080U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_HUBADDR_1               0x00000100U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_HUBADDR_2               0x00000200U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_HUBADDR_3               0x00000400U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_HUBADDR_4               0x00000800U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_HUBADDR_5               0x00001000U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_HUBADDR_6               0x00002000U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_XACTPOS                 0x0000C000U            /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0               0x00004000U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_XACTPOS_1               0x00008000U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_COMPLSPLT               0x00010000U            /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN                 0x80000000U            /*!< Split enable */
-
-/********************  Bit definition for USB_OTG_HCINT register  ********************/
-#define USB_OTG_HCINT_XFRC                    0x00000001U            /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH                     0x00000002U            /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINT_STALL                   0x00000008U            /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK                     0x00000010U            /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK                     0x00000020U            /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET                    0x00000040U            /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR                   0x00000080U            /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR                   0x00000100U            /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR                   0x00000200U            /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR                   0x00000400U            /*!< Data toggle error */
-
-/********************  Bit definition for USB_OTG_DIEPINT register  ********************/
-#define USB_OTG_DIEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_TOC                     0x00000008U            /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE                  0x00000010U            /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNE                  0x00000040U            /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE                    0x00000080U            /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN              0x00000100U            /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA                     0x00000200U            /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS               0x00000800U            /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR                    0x00001000U            /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK                     0x00002000U            /*!< NAK interrupt */
-
-/********************  Bit definition for USB_OTG_HCINTMSK register  ********************/
-#define USB_OTG_HCINTMSK_XFRCM                   0x00000001U            /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM                    0x00000002U            /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM                  0x00000008U            /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM                    0x00000010U            /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM                    0x00000020U            /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET                    0x00000040U            /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM                  0x00000080U            /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM                  0x00000100U            /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM                  0x00000200U            /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM                  0x00000400U            /*!< Data toggle error mask */
-
-/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
-
-#define USB_OTG_DIEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT                  0x60000000U            /*!< Packet count */
-/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
-#define USB_OTG_HCTSIZ_XFRSIZ                    0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT                    0x1FF80000U            /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING                    0x80000000U            /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID                      0x60000000U            /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                    0x20000000U            /*!<Bit 0 */
-#define USB_OTG_HCTSIZ_DPID_1                    0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
-#define USB_OTG_DIEPDMA_DMAADDR                  0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition for USB_OTG_HCDMA register  ********************/
-#define USB_OTG_HCDMA_DMAADDR                    0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
-#define USB_OTG_DTXFSTS_INEPTFSAV                0x0000FFFFU            /*!< IN endpoint TxFIFO space available */
-
-/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
-#define USB_OTG_DIEPTXF_INEPTXSA                 0x0000FFFFU            /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD                 0xFFFF0000U            /*!< IN endpoint TxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
-#define USB_OTG_DOEPCTL_MPSIZ                     0x000007FFU            /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP                    0x00008000U            /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS                    0x00020000U            /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            0x10000000U            /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM                   0x20000000U            /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP                     0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                   0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DOEPCTL_EPTYP_1                   0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_SNPM                      0x00100000U            /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL                     0x00200000U            /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK                      0x04000000U            /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK                      0x08000000U            /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS                     0x40000000U            /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA                     0x80000000U            /*!< Endpoint enable */
-
-/********************  Bit definition for USB_OTG_DOEPINT register  ********************/
-#define USB_OTG_DOEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_STUP                    0x00000008U            /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS                 0x00000010U            /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_OTEPSPR                 0x00000020U            /*!< Status Phase Received For Control Write */
-#define USB_OTG_DOEPINT_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_NYET                    0x00004000U            /*!< NYET interrupt */
-
-/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
-#define USB_OTG_DOEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-
-#define USB_OTG_DOEPTSIZ_STUPCNT                 0x60000000U            /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0               0x20000000U            /*!<Bit 0 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1               0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition for PCGCCTL register  ********************/
-#define USB_OTG_PCGCCTL_STOPCLK                 0x00000001U            /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK                 0x00000002U            /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP                 0x00000010U            /*!<Bit 1 */
-
-
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || \
-                                       ((__INSTANCE__) == ADC2) || \
-                                       ((__INSTANCE__) == ADC3))
-
-/******************************* CAN Instances ********************************/
-#define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) || \
-                                           ((__INSTANCE__) == CAN2))
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)
-
-/******************************* DAC Instances ********************************/
-#define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC)
-
-/******************************* DCMI Instances *******************************/
-#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
-
-
-/******************************* DMA2D Instances *******************************/
-#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
-
-/******************************** DMA Instances *******************************/
-#define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) || \
-                                              ((__INSTANCE__) == DMA1_Stream1) || \
-                                              ((__INSTANCE__) == DMA1_Stream2) || \
-                                              ((__INSTANCE__) == DMA1_Stream3) || \
-                                              ((__INSTANCE__) == DMA1_Stream4) || \
-                                              ((__INSTANCE__) == DMA1_Stream5) || \
-                                              ((__INSTANCE__) == DMA1_Stream6) || \
-                                              ((__INSTANCE__) == DMA1_Stream7) || \
-                                              ((__INSTANCE__) == DMA2_Stream0) || \
-                                              ((__INSTANCE__) == DMA2_Stream1) || \
-                                              ((__INSTANCE__) == DMA2_Stream2) || \
-                                              ((__INSTANCE__) == DMA2_Stream3) || \
-                                              ((__INSTANCE__) == DMA2_Stream4) || \
-                                              ((__INSTANCE__) == DMA2_Stream5) || \
-                                              ((__INSTANCE__) == DMA2_Stream6) || \
-                                              ((__INSTANCE__) == DMA2_Stream7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
-                                            ((__INSTANCE__) == GPIOB) || \
-                                            ((__INSTANCE__) == GPIOC) || \
-                                            ((__INSTANCE__) == GPIOD) || \
-                                            ((__INSTANCE__) == GPIOE) || \
-                                            ((__INSTANCE__) == GPIOF) || \
-                                            ((__INSTANCE__) == GPIOG) || \
-                                            ((__INSTANCE__) == GPIOH) || \
-                                            ((__INSTANCE__) == GPIOI) || \
-                                            ((__INSTANCE__) == GPIOJ) || \
-                                            ((__INSTANCE__) == GPIOK))
-
-#define IS_GPIO_AF_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == GPIOA) || \
-                                             ((__INSTANCE__) == GPIOB) || \
-                                             ((__INSTANCE__) == GPIOC) || \
-                                             ((__INSTANCE__) == GPIOD) || \
-                                             ((__INSTANCE__) == GPIOE) || \
-                                             ((__INSTANCE__) == GPIOF) || \
-                                             ((__INSTANCE__) == GPIOG) || \
-                                             ((__INSTANCE__) == GPIOH) || \
-                                             ((__INSTANCE__) == GPIOI) || \
-                                             ((__INSTANCE__) == GPIOJ) || \
-                                             ((__INSTANCE__) == GPIOK))
-
-/****************************** CEC Instances *********************************/
-#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
-
-/****************************** QSPI Instances *********************************/
-#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
-
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
-                                           ((__INSTANCE__) == I2C2) || \
-                                           ((__INSTANCE__) == I2C3) || \
-                                           ((__INSTANCE__) == I2C4))
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == SPI1) || \
-                                            ((__INSTANCE__) == SPI2) || \
-                                            ((__INSTANCE__) == SPI3))
-
-/******************************* LPTIM Instances ********************************/
-#define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
-
-/****************************** LTDC Instances ********************************/
-#define IS_LTDC_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == LTDC)
-
-
-
-
-/******************************* RNG Instances ********************************/
-#define IS_RNG_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == RNG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == RTC)
-
-/******************************* SAI Instances ********************************/
-#define IS_SAI_ALL_INSTANCE(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) || \
-                                         ((__PERIPH__) == SAI1_Block_B) || \
-                                         ((__PERIPH__) == SAI2_Block_A) || \
-                                         ((__PERIPH__) == SAI2_Block_B))
-/* Legacy define */
-#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
-
-/******************************** SDMMC Instances *******************************/
-#define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SDMMC1)
-
-/****************************** SPDIFRX Instances *********************************/
-#define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
-                                           ((__INSTANCE__) == SPI2) || \
-                                           ((__INSTANCE__) == SPI3) || \
-                                           ((__INSTANCE__) == SPI4) || \
-                                           ((__INSTANCE__) == SPI5) || \
-                                           ((__INSTANCE__) == SPI6))
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1)   || \
-                                   ((__INSTANCE__) == TIM2)   || \
-                                   ((__INSTANCE__) == TIM3)   || \
-                                   ((__INSTANCE__) == TIM4)   || \
-                                   ((__INSTANCE__) == TIM5)   || \
-                                   ((__INSTANCE__) == TIM6)   || \
-                                   ((__INSTANCE__) == TIM7)   || \
-                                   ((__INSTANCE__) == TIM8)   || \
-                                   ((__INSTANCE__) == TIM9)   || \
-                                   ((__INSTANCE__) == TIM10)  || \
-                                   ((__INSTANCE__) == TIM11)  || \
-                                   ((__INSTANCE__) == TIM12)  || \
-                                   ((__INSTANCE__) == TIM13)  || \
-                                   ((__INSTANCE__) == TIM14))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1)  || \
-                                         ((__INSTANCE__) == TIM2)  || \
-                                         ((__INSTANCE__) == TIM3)  || \
-                                         ((__INSTANCE__) == TIM4)  || \
-                                         ((__INSTANCE__) == TIM5)  || \
-                                         ((__INSTANCE__) == TIM8)  || \
-                                         ((__INSTANCE__) == TIM9)  || \
-                                         ((__INSTANCE__) == TIM10) || \
-                                         ((__INSTANCE__) == TIM11) || \
-                                         ((__INSTANCE__) == TIM12) || \
-                                         ((__INSTANCE__) == TIM13) || \
-                                         ((__INSTANCE__) == TIM14))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1)  || \
-                                         ((__INSTANCE__) == TIM2)  || \
-                                         ((__INSTANCE__) == TIM3)  || \
-                                         ((__INSTANCE__) == TIM4)  || \
-                                         ((__INSTANCE__) == TIM5)  || \
-                                         ((__INSTANCE__) == TIM8)  || \
-                                         ((__INSTANCE__) == TIM9)  || \
-                                         ((__INSTANCE__) == TIM12))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1) || \
-                                         ((__INSTANCE__) == TIM2) || \
-                                         ((__INSTANCE__) == TIM3) || \
-                                         ((__INSTANCE__) == TIM4) || \
-                                         ((__INSTANCE__) == TIM5) || \
-                                         ((__INSTANCE__) == TIM8))
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
-                                       ((__INSTANCE__) == TIM2) || \
-                                       ((__INSTANCE__) == TIM3) || \
-                                       ((__INSTANCE__) == TIM4) || \
-                                       ((__INSTANCE__) == TIM5) || \
-                                       ((__INSTANCE__) == TIM8))
-
-/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
-#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \
-                                       (((__INSTANCE__) == TIM1)    || \
-                                        ((__INSTANCE__) == TIM8))
-
-/****************** TIM Instances : supporting OCxREF clear *******************/
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\
-                                  (((__INSTANCE__) == TIM1)    || \
-                                   ((__INSTANCE__) == TIM2)    || \
-                                   ((__INSTANCE__) == TIM3)    || \
-                                   ((__INSTANCE__) == TIM4)    || \
-                                   ((__INSTANCE__) == TIM8))
-
-/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\
-                                                 (((__INSTANCE__) == TIM1)    || \
-                                                  ((__INSTANCE__) == TIM2)    || \
-                                                  ((__INSTANCE__) == TIM3)    || \
-                                                  ((__INSTANCE__) == TIM4)    || \
-                                                  ((__INSTANCE__) == TIM5)    || \
-                                                  ((__INSTANCE__) == TIM8))
-
-/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\
-                                                   (((__INSTANCE__) == TIM1)    || \
-                                                    ((__INSTANCE__) == TIM2)    || \
-                                                    ((__INSTANCE__) == TIM3)    || \
-                                                    ((__INSTANCE__) == TIM4)    || \
-                                                    ((__INSTANCE__) == TIM5)    || \
-                                                    ((__INSTANCE__) == TIM8))
-/****************** TIM Instances : at least 5 capture/compare channels *******/
-#define IS_TIM_CC5_INSTANCE(__INSTANCE__)\
-  (((__INSTANCE__) == TIM1)    || \
-   ((__INSTANCE__) == TIM8) )
-
-/****************** TIM Instances : at least 6 capture/compare channels *******/
-#define IS_TIM_CC6_INSTANCE(__INSTANCE__)\
-  (((__INSTANCE__) == TIM1)    || \
-   ((__INSTANCE__) == TIM8))
-
-
-/******************** TIM Instances : Advanced-control timers *****************/
-#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
-                                            ((__INSTANCE__) == TIM8))
-
-/****************** TIM Instances : supporting 2 break inputs *****************/
-#define IS_TIM_BREAK_INSTANCE(__INSTANCE__)\
-  (((__INSTANCE__) == TIM1)    || \
-   ((__INSTANCE__) == TIM8))
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1) || \
-                                         ((__INSTANCE__) == TIM2) || \
-                                         ((__INSTANCE__) == TIM3) || \
-                                         ((__INSTANCE__) == TIM4) || \
-                                         ((__INSTANCE__) == TIM5) || \
-                                         ((__INSTANCE__) == TIM8))
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
-                                       ((__INSTANCE__) == TIM2) || \
-                                       ((__INSTANCE__) == TIM3) || \
-                                       ((__INSTANCE__) == TIM4) || \
-                                       ((__INSTANCE__) == TIM5) || \
-                                       ((__INSTANCE__) == TIM6) || \
-                                       ((__INSTANCE__) == TIM7) || \
-                                       ((__INSTANCE__) == TIM8))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
-                                          ((__INSTANCE__) == TIM2) || \
-                                          ((__INSTANCE__) == TIM3) || \
-                                          ((__INSTANCE__) == TIM4) || \
-                                          ((__INSTANCE__) == TIM5) || \
-                                          ((__INSTANCE__) == TIM8))
-
-/************ TIM Instances : DMA requests generation (COMDE) *****************/
-#define IS_TIM_CCDMA_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1) || \
-                                          ((__INSTANCE__) == TIM2) || \
-                                          ((__INSTANCE__) == TIM3) || \
-                                          ((__INSTANCE__) == TIM4) || \
-                                          ((__INSTANCE__) == TIM5) || \
-                                          ((__INSTANCE__) == TIM8))
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1) || \
-                                             ((__INSTANCE__) == TIM2) || \
-                                             ((__INSTANCE__) == TIM3) || \
-                                             ((__INSTANCE__) == TIM4) || \
-                                             ((__INSTANCE__) == TIM5) || \
-                                             ((__INSTANCE__) == TIM8))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
-                                          ((__INSTANCE__) == TIM2) || \
-                                          ((__INSTANCE__) == TIM3) || \
-                                          ((__INSTANCE__) == TIM4) || \
-                                          ((__INSTANCE__) == TIM5) || \
-                                          ((__INSTANCE__) == TIM6) || \
-                                          ((__INSTANCE__) == TIM7) || \
-                                          ((__INSTANCE__) == TIM8) || \
-                                          ((__INSTANCE__) == TIM13) || \
-                                          ((__INSTANCE__) == TIM14))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
-                                         ((__INSTANCE__) == TIM2) || \
-                                         ((__INSTANCE__) == TIM3) || \
-                                         ((__INSTANCE__) == TIM4) || \
-                                         ((__INSTANCE__) == TIM5) || \
-                                         ((__INSTANCE__) == TIM8) || \
-                                         ((__INSTANCE__) == TIM9) || \
-                                         ((__INSTANCE__) == TIM12))
-
-/********************** TIM Instances : 32 bit Counter ************************/
-#define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__)(((__INSTANCE__) == TIM2) || \
-                                              ((__INSTANCE__) == TIM5))
-
-/***************** TIM Instances : external trigger input available ************/
-#define IS_TIM_ETR_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1) || \
-                                        ((__INSTANCE__) == TIM2) || \
-                                        ((__INSTANCE__) == TIM3) || \
-                                        ((__INSTANCE__) == TIM4) || \
-                                        ((__INSTANCE__) == TIM5) || \
-                                        ((__INSTANCE__) == TIM8))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2)  || \
-                                         ((__INSTANCE__) == TIM5)  || \
-                                         ((__INSTANCE__) == TIM11))
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \
-    ((((__INSTANCE__) == TIM1) &&                  \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM2) &&                   \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM3) &&                   \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM4) &&                   \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM5) &&                   \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM8) &&                   \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM9) &&                   \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM10) &&                  \
-     (((__CHANNEL__) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM11) &&                  \
-     (((__CHANNEL__) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM12) &&                  \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM13) &&                  \
-     (((__CHANNEL__) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM14) &&                  \
-     (((__CHANNEL__) == TIM_CHANNEL_1))))
-
-/************ TIM Instances : complementary output(s) available ***************/
-#define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \
-   ((((__INSTANCE__) == TIM1) &&                    \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||           \
-      ((__CHANNEL__) == TIM_CHANNEL_2) ||           \
-      ((__CHANNEL__) == TIM_CHANNEL_3)))            \
-    ||                                          \
-    (((__INSTANCE__) == TIM8) &&                    \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||           \
-      ((__CHANNEL__) == TIM_CHANNEL_2) ||           \
-      ((__CHANNEL__) == TIM_CHANNEL_3))))
-
-/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
-#define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\
-  (((__INSTANCE__) == TIM1)    || \
-   ((__INSTANCE__) == TIM8) )
-
-/****************** TIM Instances : supporting synchronization ****************/
-#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
-    (((__INSTANCE__) == TIM1)    || \
-     ((__INSTANCE__) == TIM2)    || \
-     ((__INSTANCE__) == TIM3)    || \
-     ((__INSTANCE__) == TIM4)    || \
-     ((__INSTANCE__) == TIM5)    || \
-     ((__INSTANCE__) == TIM6)    || \
-     ((__INSTANCE__) == TIM7)    || \
-     ((__INSTANCE__) == TIM8))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
-                                     ((__INSTANCE__) == USART2) || \
-                                     ((__INSTANCE__) == USART3) || \
-                                     ((__INSTANCE__) == USART6))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
-                                    ((__INSTANCE__) == USART2) || \
-                                    ((__INSTANCE__) == USART3) || \
-                                    ((__INSTANCE__) == UART4)  || \
-                                    ((__INSTANCE__) == UART5)  || \
-                                    ((__INSTANCE__) == USART6) || \
-                                    ((__INSTANCE__) == UART7)  || \
-                                    ((__INSTANCE__) == UART8))
-
-/****************** UART Instances : Driver Enable *****************/
-#define IS_UART_DRIVER_ENABLE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
-                                    ((__INSTANCE__) == USART2) || \
-                                    ((__INSTANCE__) == USART3) || \
-                                    ((__INSTANCE__) == UART4)  || \
-                                    ((__INSTANCE__) == UART5)  || \
-                                    ((__INSTANCE__) == USART6) || \
-                                    ((__INSTANCE__) == UART7)  || \
-                                    ((__INSTANCE__) == UART8))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
-                                    ((__INSTANCE__) == USART2) || \
-                                    ((__INSTANCE__) == USART3) || \
-                                    ((__INSTANCE__) == UART4)  || \
-                                    ((__INSTANCE__) == UART5)  || \
-                                    ((__INSTANCE__) == USART6) || \
-                                    ((__INSTANCE__) == UART7)  || \
-                                    ((__INSTANCE__) == UART8))
-
-/********************* UART Instances : Smart card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
-                                         ((__INSTANCE__) == USART2) || \
-                                         ((__INSTANCE__) == USART3) || \
-                                         ((__INSTANCE__) == USART6))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
-                                    ((__INSTANCE__) == USART2) || \
-                                    ((__INSTANCE__) == USART3) || \
-                                    ((__INSTANCE__) == UART4)  || \
-                                    ((__INSTANCE__) == UART5)  || \
-                                    ((__INSTANCE__) == USART6) || \
-                                    ((__INSTANCE__) == UART7)  || \
-                                    ((__INSTANCE__) == UART8))
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == WWDG)
-
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32F7xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */
-/*  product lines within the same STM32F7 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-#define HASH_RNG_IRQn              RNG_IRQn
-
-/* Aliases for __IRQHandler */
-#define HASH_RNG_IRQHandler        RNG_IRQHandler
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32F746xx_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/cmsis/stm32f756xx.h b/stmhal/cmsis/stm32f756xx.h
deleted file mode 100644
index 80dc9d4376..0000000000
--- a/stmhal/cmsis/stm32f756xx.h
+++ /dev/null
@@ -1,9660 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f756xx.h
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   CMSIS Cortex-M7 Device Peripheral Access Layer Header File.
-  *
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral's registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS_Device
-  * @{
-  */
-
-/** @addtogroup stm32f756xx
-  * @{
-  */
-
-#ifndef __STM32F756xx_H
-#define __STM32F756xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-
-/**
- * @brief STM32F7xx Interrupt Number Definition, according to the selected device
- *        in @ref Library_configuration_section
- */
-typedef enum
-{
-/******  Cortex-M7 Processor Exceptions Numbers ****************************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M7 Memory Management Interrupt                           */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M7 Bus Fault Interrupt                                   */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M7 Usage Fault Interrupt                                 */
-  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M7 SV Call Interrupt                                    */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M7 Debug Monitor Interrupt                              */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M7 Pend SV Interrupt                                    */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M7 System Tick Interrupt                                */
-/******  STM32 specific Interrupt Numbers **********************************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
-  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
-  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
-  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
-  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
-  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
-  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
-  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
-  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
-  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
-  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
-  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
-  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
-  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
-  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
-  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
-  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
-  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */
-  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
-  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
-  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
-  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
-  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
-  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
-  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
-  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
-  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
-  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
-  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
-  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
-  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
-  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
-  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
-  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
-  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
-  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
-  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
-  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
-  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
-  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
-  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
-  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
-  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
-  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
-  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
-  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
-  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
-  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
-  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
-  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
-  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
-  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
-  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
-  CRYP_IRQn                   = 79,     /*!< CRYP crypto global interrupt                                      */
-  HASH_RNG_IRQn               = 80,     /*!< Hash and Rng global interrupt                                     */
-  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
-  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */
-  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */
-  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
-  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */
-  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */
-  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
-  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                             */
-  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                       */
-  DMA2D_IRQn                  = 90,     /*!< DMA2D global Interrupt                                            */
-  SAI2_IRQn                   = 91,     /*!< SAI2 global Interrupt                                             */
-  QUADSPI_IRQn                = 92,     /*!< Quad SPI global interrupt                                         */
-  LPTIM1_IRQn                 = 93,     /*!< LP TIM1 interrupt                                                 */
-  CEC_IRQn                    = 94,     /*!< HDMI-CEC global Interrupt                                         */
-  I2C4_EV_IRQn                = 95,     /*!< I2C4 Event Interrupt                                              */
-  I2C4_ER_IRQn                = 96,     /*!< I2C4 Error Interrupt                                              */
-  SPDIF_RX_IRQn               = 97,     /*!< SPDIF-RX global Interrupt                                         */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-/**
- * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
- */
-#define __CM7_REV                 0x0001U  /*!< Cortex-M7 revision r0p1                       */
-#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */
-#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */
-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1       /*!< FPU present                                   */
-#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */
-#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */
-#include "core_cm7.h"                     /*!< Cortex-M7 processor and core peripherals      */
-
-
-#include "system_stm32f7xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */
-
-/**
-  * @brief Analog to Digital Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */
-  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
-  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
-  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
-  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
-  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
-  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
-  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
-  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
-  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
-  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
-  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
-  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
-  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
-  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
-  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
-                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
-} ADC_Common_TypeDef;
-
-
-/**
-  * @brief Controller Area Network TxMailBox
-  */
-
-typedef struct
-{
-  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
-  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
-  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
-  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
-} CAN_TxMailBox_TypeDef;
-
-/**
-  * @brief Controller Area Network FIFOMailBox
-  */
-
-typedef struct
-{
-  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
-  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
-  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
-  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
-} CAN_FIFOMailBox_TypeDef;
-
-/**
-  * @brief Controller Area Network FilterRegister
-  */
-
-typedef struct
-{
-  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
-  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
-} CAN_FilterRegister_TypeDef;
-
-/**
-  * @brief Controller Area Network
-  */
-
-typedef struct
-{
-  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
-  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
-  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
-  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
-  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
-  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
-  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
-  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
-  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
-  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
-  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
-  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
-  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
-  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
-  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
-  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
-  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
-  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
-  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
-  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
-  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */
-  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
-} CAN_TypeDef;
-
-/**
-  * @brief HDMI-CEC
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< CEC control register,                                       Address offset:0x00 */
-  __IO uint32_t CFGR;         /*!< CEC configuration register,                                 Address offset:0x04 */
-  __IO uint32_t TXDR;         /*!< CEC Tx data register ,                                      Address offset:0x08 */
-  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,                                       Address offset:0x0C */
-  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register,                          Address offset:0x10 */
-  __IO uint32_t IER;          /*!< CEC interrupt enable register,                              Address offset:0x14 */
-}CEC_TypeDef;
-
-/**
-  * @brief CRC calculation unit
-  */
-
-typedef struct
-{
-  __IO uint32_t  DR;          /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint8_t   IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
-  uint8_t        RESERVED0;   /*!< Reserved, 0x05                                                    */
-  uint16_t       RESERVED1;   /*!< Reserved, 0x06                                                    */
-  __IO uint32_t  CR;          /*!< CRC Control register,                        Address offset: 0x08 */
-  uint32_t       RESERVED2;   /*!< Reserved,                                                    0x0C */
-  __IO uint32_t  INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
-  __IO uint32_t  POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
-} CRC_TypeDef;
-
-/**
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
-  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
-  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
-  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
-  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
-  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
-  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
-  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
-  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
-  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
-  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
-  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
-  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
-} DAC_TypeDef;
-
-
-/**
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
-  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
-  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
-  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/**
-  * @brief DCMI
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
-  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
-  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
-  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
-  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
-  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
-  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
-  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
-  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
-  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
-  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
-} DCMI_TypeDef;
-
-/**
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
-  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
-  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
-  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
-  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
-  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
-} DMA_Stream_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
-  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
-  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
-  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
-} DMA_TypeDef;
-
-/**
-  * @brief DMA2D Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
-  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
-  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
-  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
-  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
-  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
-  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
-  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
-  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
-  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
-  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
-  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
-  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
-  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
-  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
-  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
-  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
-  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
-  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
-  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
-  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
-  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */
-  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */
-} DMA2D_TypeDef;
-
-
-/**
-  * @brief Ethernet MAC
-  */
-
-typedef struct
-{
-  __IO uint32_t MACCR;
-  __IO uint32_t MACFFR;
-  __IO uint32_t MACHTHR;
-  __IO uint32_t MACHTLR;
-  __IO uint32_t MACMIIAR;
-  __IO uint32_t MACMIIDR;
-  __IO uint32_t MACFCR;
-  __IO uint32_t MACVLANTR;             /*    8 */
-  uint32_t      RESERVED0[2];
-  __IO uint32_t MACRWUFFR;             /*   11 */
-  __IO uint32_t MACPMTCSR;
-  uint32_t      RESERVED1[2];
-  __IO uint32_t MACSR;                 /*   15 */
-  __IO uint32_t MACIMR;
-  __IO uint32_t MACA0HR;
-  __IO uint32_t MACA0LR;
-  __IO uint32_t MACA1HR;
-  __IO uint32_t MACA1LR;
-  __IO uint32_t MACA2HR;
-  __IO uint32_t MACA2LR;
-  __IO uint32_t MACA3HR;
-  __IO uint32_t MACA3LR;               /*   24 */
-  uint32_t      RESERVED2[40];
-  __IO uint32_t MMCCR;                 /*   65 */
-  __IO uint32_t MMCRIR;
-  __IO uint32_t MMCTIR;
-  __IO uint32_t MMCRIMR;
-  __IO uint32_t MMCTIMR;               /*   69 */
-  uint32_t      RESERVED3[14];
-  __IO uint32_t MMCTGFSCCR;            /*   84 */
-  __IO uint32_t MMCTGFMSCCR;
-  uint32_t      RESERVED4[5];
-  __IO uint32_t MMCTGFCR;
-  uint32_t      RESERVED5[10];
-  __IO uint32_t MMCRFCECR;
-  __IO uint32_t MMCRFAECR;
-  uint32_t      RESERVED6[10];
-  __IO uint32_t MMCRGUFCR;
-  uint32_t      RESERVED7[334];
-  __IO uint32_t PTPTSCR;
-  __IO uint32_t PTPSSIR;
-  __IO uint32_t PTPTSHR;
-  __IO uint32_t PTPTSLR;
-  __IO uint32_t PTPTSHUR;
-  __IO uint32_t PTPTSLUR;
-  __IO uint32_t PTPTSAR;
-  __IO uint32_t PTPTTHR;
-  __IO uint32_t PTPTTLR;
-  __IO uint32_t RESERVED8;
-  __IO uint32_t PTPTSSR;
-  uint32_t      RESERVED9[565];
-  __IO uint32_t DMABMR;
-  __IO uint32_t DMATPDR;
-  __IO uint32_t DMARPDR;
-  __IO uint32_t DMARDLAR;
-  __IO uint32_t DMATDLAR;
-  __IO uint32_t DMASR;
-  __IO uint32_t DMAOMR;
-  __IO uint32_t DMAIER;
-  __IO uint32_t DMAMFBOCR;
-  __IO uint32_t DMARSWTR;
-  uint32_t      RESERVED10[8];
-  __IO uint32_t DMACHTDR;
-  __IO uint32_t DMACHRDR;
-  __IO uint32_t DMACHTBAR;
-  __IO uint32_t DMACHRBAR;
-} ETH_TypeDef;
-
-/**
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
-  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
-  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
-  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
-  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
-  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/**
-  * @brief FLASH Registers
-  */
-
-typedef struct
-{
-  __IO uint32_t ACR;      /*!< FLASH access control register,     Address offset: 0x00 */
-  __IO uint32_t KEYR;     /*!< FLASH key register,                Address offset: 0x04 */
-  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,         Address offset: 0x08 */
-  __IO uint32_t SR;       /*!< FLASH status register,             Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< FLASH control register,            Address offset: 0x10 */
-  __IO uint32_t OPTCR;    /*!< FLASH option control register ,    Address offset: 0x14 */
-  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1 ,  Address offset: 0x18 */
-} FLASH_TypeDef;
-
-
-
-/**
-  * @brief Flexible Memory Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
-} FMC_Bank1_TypeDef;
-
-/**
-  * @brief Flexible Memory Controller Bank1E
-  */
-
-typedef struct
-{
-  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
-} FMC_Bank1E_TypeDef;
-
-/**
-  * @brief Flexible Memory Controller Bank3
-  */
-
-typedef struct
-{
-  __IO uint32_t PCR;        /*!< NAND Flash control register,                       Address offset: 0x80 */
-  __IO uint32_t SR;         /*!< NAND Flash FIFO status and interrupt register,     Address offset: 0x84 */
-  __IO uint32_t PMEM;       /*!< NAND Flash Common memory space timing register,    Address offset: 0x88 */
-  __IO uint32_t PATT;       /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
-  uint32_t      RESERVED0;  /*!< Reserved, 0x90                                                          */
-  __IO uint32_t ECCR;       /*!< NAND Flash ECC result registers,                   Address offset: 0x94 */
-} FMC_Bank3_TypeDef;
-
-/**
-  * @brief Flexible Memory Controller Bank5_6
-  */
-
-typedef struct
-{
-  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */
-  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */
-  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */
-  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */
-  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */
-} FMC_Bank5_6_TypeDef;
-
-
-/**
-  * @brief General Purpose I/O
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
-  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
-  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
-  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
-  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
-  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
-  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
-  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/**
-  * @brief System configuration controller
-  */
-
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */
-  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
-} SYSCFG_TypeDef;
-
-/**
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
-  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
-} I2C_TypeDef;
-
-/**
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
-} IWDG_TypeDef;
-
-
-/**
-  * @brief LCD-TFT Display Controller
-  */
-
-typedef struct
-{
-  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04 */
-  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */
-  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */
-  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */
-  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */
-  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */
-  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20 */
-  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */
-  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28 */
-  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */
-  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30 */
-  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */
-  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */
-  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */
-  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
-  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */
-  __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                 Address offset: 0x48 */
-} LTDC_TypeDef;
-
-/**
-  * @brief LCD-TFT Display layer x Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */
-  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
-  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */
-  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */
-  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */
-  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */
-  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */
-  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */
-  uint32_t      RESERVED0[2];  /*!< Reserved */
-  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */
-  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */
-  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */
-  uint32_t      RESERVED1[3];  /*!< Reserved */
-  __IO uint32_t CLUTWR;        /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */
-
-} LTDC_Layer_TypeDef;
-
-/**
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;   /*!< PWR power control register 1,        Address offset: 0x00 */
-  __IO uint32_t CSR1;  /*!< PWR power control/status register 2, Address offset: 0x04 */
-  __IO uint32_t CR2;   /*!< PWR power control register 2,        Address offset: 0x08 */
-  __IO uint32_t CSR2;  /*!< PWR power control/status register 2, Address offset: 0x0C */
-} PWR_TypeDef;
-
-
-/**
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
-  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
-  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
-  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
-  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
-  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
-  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
-  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
-  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
-  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
-  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
-  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
-  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
-  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
-  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
-  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
-  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
-  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
-  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
-  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
-  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
-  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
-  __IO uint32_t PLLSAICFGR;    /*!< RCC PLLSAI configuration register,                           Address offset: 0x88 */
-  __IO uint32_t DCKCFGR1;      /*!< RCC Dedicated Clocks configuration register1,                 Address offset: 0x8C */
-  __IO uint32_t DCKCFGR2;      /*!< RCC Dedicated Clocks configuration register 2,               Address offset: 0x90 */
-
-} RCC_TypeDef;
-
-/**
-  * @brief Real-Time Clock
-  */
-
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-       uint32_t reserved;   /*!< Reserved  */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
-  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset: 0x4C */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
-  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
-  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
-  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
-  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
-  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
-  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
-  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
-  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
-  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
-  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
-  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
-  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
-  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
-  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
-  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */
-  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */
-  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */
-  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */
-  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */
-  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */
-  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */
-  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */
-  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */
-  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */
-  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */
-  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */
-} RTC_TypeDef;
-
-
-/**
-  * @brief Serial Audio Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t GCR;      /*!< SAI global configuration register,        Address offset: 0x00 */
-} SAI_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */
-  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */
-  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */
-  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */
-  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
-  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */
-  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */
-  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */
-} SAI_Block_TypeDef;
-
-/**
-  * @brief SPDIF-RX Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t   CR;           /*!< Control register,                   Address offset: 0x00 */
-  __IO uint32_t   IMR;          /*!< Interrupt mask register,            Address offset: 0x04 */
-  __IO uint32_t   SR;           /*!< Status register,                    Address offset: 0x08 */
-  __IO uint32_t   IFCR;         /*!< Interrupt Flag Clear register,      Address offset: 0x0C */
-  __IO uint32_t   DR;           /*!< Data input register,                Address offset: 0x10 */
-  __IO uint32_t   CSR;          /*!< Channel Status register,            Address offset: 0x14 */
-  __IO uint32_t   DIR;          /*!< Debug Information register,         Address offset: 0x18 */
-} SPDIFRX_TypeDef;
-
-/**
-  * @brief SD host Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t POWER;          /*!< SDMMC power control register,    Address offset: 0x00 */
-  __IO uint32_t CLKCR;          /*!< SDMMClock control register,     Address offset: 0x04 */
-  __IO uint32_t ARG;            /*!< SDMMC argument register,         Address offset: 0x08 */
-  __IO uint32_t CMD;            /*!< SDMMC command register,          Address offset: 0x0C */
-  __I uint32_t  RESPCMD;        /*!< SDMMC command response register, Address offset: 0x10 */
-  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,       Address offset: 0x14 */
-  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,       Address offset: 0x18 */
-  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,       Address offset: 0x1C */
-  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,       Address offset: 0x20 */
-  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,       Address offset: 0x24 */
-  __IO uint32_t DLEN;           /*!< SDMMC data length register,      Address offset: 0x28 */
-  __IO uint32_t DCTRL;          /*!< SDMMC data control register,     Address offset: 0x2C */
-  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,     Address offset: 0x30 */
-  __I uint32_t  STA;            /*!< SDMMC status register,           Address offset: 0x34 */
-  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,  Address offset: 0x38 */
-  __IO uint32_t MASK;           /*!< SDMMC mask register,             Address offset: 0x3C */
-  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
-  __I uint32_t  FIFOCNT;        /*!< SDMMC FIFO counter register,     Address offset: 0x48 */
-  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
-  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,        Address offset: 0x80 */
-} SDMMC_TypeDef;
-
-/**
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/**
-  * @brief QUAD Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */
-  __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
-  __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */
-  __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
-  __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
-  __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
-  __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */
-  __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
-  __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */
-  __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
-  __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */
-  __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
-  __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */
-} QUADSPI_TypeDef;
-
-/**
-  * @brief TIM
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
-  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
-  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
-  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
-  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */
-  __IO uint32_t CCR5;        /*!< TIM capture/compare mode register5,       Address offset: 0x58 */
-  __IO uint32_t CCR6;        /*!< TIM capture/compare mode register6,       Address offset: 0x5C */
-
-} TIM_TypeDef;
-
-/**
-  * @brief LPTIMIMER
-  */
-typedef struct
-{
-  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */
-  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */
-  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */
-  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                       Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< LPTIM Control register,                             Address offset: 0x10 */
-  __IO uint32_t CMP;      /*!< LPTIM Compare register,                             Address offset: 0x14 */
-  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
-  __IO uint32_t CNT;      /*!< LPTIM Counter register,                             Address offset: 0x1C */
-} LPTIM_TypeDef;
-
-
-/**
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */
-  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */
-  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
-  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */
-  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
-  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */
-  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
-  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
-  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
-  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
-  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
-} USART_TypeDef;
-
-
-/**
-  * @brief Window WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/**
-  * @brief Crypto Processor
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;         /*!< CRYP control register,                                    Address offset: 0x00 */
-  __IO uint32_t SR;         /*!< CRYP status register,                                     Address offset: 0x04 */
-  __IO uint32_t DR;         /*!< CRYP data input register,                                 Address offset: 0x08 */
-  __IO uint32_t DOUT;       /*!< CRYP data output register,                                Address offset: 0x0C */
-  __IO uint32_t DMACR;      /*!< CRYP DMA control register,                                Address offset: 0x10 */
-  __IO uint32_t IMSCR;      /*!< CRYP interrupt mask set/clear register,                   Address offset: 0x14 */
-  __IO uint32_t RISR;       /*!< CRYP raw interrupt status register,                       Address offset: 0x18 */
-  __IO uint32_t MISR;       /*!< CRYP masked interrupt status register,                    Address offset: 0x1C */
-  __IO uint32_t K0LR;       /*!< CRYP key left  register 0,                                Address offset: 0x20 */
-  __IO uint32_t K0RR;       /*!< CRYP key right register 0,                                Address offset: 0x24 */
-  __IO uint32_t K1LR;       /*!< CRYP key left  register 1,                                Address offset: 0x28 */
-  __IO uint32_t K1RR;       /*!< CRYP key right register 1,                                Address offset: 0x2C */
-  __IO uint32_t K2LR;       /*!< CRYP key left  register 2,                                Address offset: 0x30 */
-  __IO uint32_t K2RR;       /*!< CRYP key right register 2,                                Address offset: 0x34 */
-  __IO uint32_t K3LR;       /*!< CRYP key left  register 3,                                Address offset: 0x38 */
-  __IO uint32_t K3RR;       /*!< CRYP key right register 3,                                Address offset: 0x3C */
-  __IO uint32_t IV0LR;      /*!< CRYP initialization vector left-word  register 0,         Address offset: 0x40 */
-  __IO uint32_t IV0RR;      /*!< CRYP initialization vector right-word register 0,         Address offset: 0x44 */
-  __IO uint32_t IV1LR;      /*!< CRYP initialization vector left-word  register 1,         Address offset: 0x48 */
-  __IO uint32_t IV1RR;      /*!< CRYP initialization vector right-word register 1,         Address offset: 0x4C */
-  __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0,        Address offset: 0x50 */
-  __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1,        Address offset: 0x54 */
-  __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2,        Address offset: 0x58 */
-  __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3,        Address offset: 0x5C */
-  __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4,        Address offset: 0x60 */
-  __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5,        Address offset: 0x64 */
-  __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6,        Address offset: 0x68 */
-  __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7,        Address offset: 0x6C */
-  __IO uint32_t CSGCM0R;    /*!< CRYP GCM/GMAC context swap register 0,                    Address offset: 0x70 */
-  __IO uint32_t CSGCM1R;    /*!< CRYP GCM/GMAC context swap register 1,                    Address offset: 0x74 */
-  __IO uint32_t CSGCM2R;    /*!< CRYP GCM/GMAC context swap register 2,                    Address offset: 0x78 */
-  __IO uint32_t CSGCM3R;    /*!< CRYP GCM/GMAC context swap register 3,                    Address offset: 0x7C */
-  __IO uint32_t CSGCM4R;    /*!< CRYP GCM/GMAC context swap register 4,                    Address offset: 0x80 */
-  __IO uint32_t CSGCM5R;    /*!< CRYP GCM/GMAC context swap register 5,                    Address offset: 0x84 */
-  __IO uint32_t CSGCM6R;    /*!< CRYP GCM/GMAC context swap register 6,                    Address offset: 0x88 */
-  __IO uint32_t CSGCM7R;    /*!< CRYP GCM/GMAC context swap register 7,                    Address offset: 0x8C */
-} CRYP_TypeDef;
-
-/**
-  * @brief HASH
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;               /*!< HASH control register,          Address offset: 0x00        */
-  __IO uint32_t DIN;              /*!< HASH data input register,       Address offset: 0x04        */
-  __IO uint32_t STR;              /*!< HASH start register,            Address offset: 0x08        */
-  __IO uint32_t HR[5];            /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */
-  __IO uint32_t IMR;              /*!< HASH interrupt enable register, Address offset: 0x20        */
-  __IO uint32_t SR;               /*!< HASH status register,           Address offset: 0x24        */
-  uint32_t      RESERVED[52];     /*!< Reserved, 0x28-0xF4                                         */
-  __IO uint32_t CSR[54];          /*!< HASH context swap registers,    Address offset: 0x0F8-0x1CC */
-} HASH_TypeDef;
-
-/**
-  * @brief HASH_DIGEST
-  */
-
-typedef struct
-{
-  __IO uint32_t HR[8];     /*!< HASH digest registers,          Address offset: 0x310-0x32C */
-} HASH_DIGEST_TypeDef;
-
-/**
-  * @brief RNG
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
-  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
-  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
-} RNG_TypeDef;
-
-/**
-  * @}
-  */
-
-/**
-  * @brief USB_OTG_Core_Registers
-  */
-typedef struct
-{
- __IO uint32_t GOTGCTL;               /*!< USB_OTG Control and Status Register          000h */
-  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */
-  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */
-  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */
-  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */
-  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */
-  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */
-  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */
-  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */
-  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */
-  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */
-  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */
-  uint32_t Reserved30[2];             /*!< Reserved                                     030h */
-  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */
-  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */
-  uint32_t  Reserved5[3];             /*!< Reserved                                040h-048h */
-  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */
-  uint32_t  Reserved6;                /*!< Reserved                                     050h */
-  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */
-  __IO uint32_t GPWRDN;               /*!< Power Down Register                          058h */
-  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */
-   __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register       60Ch */
-    uint32_t  Reserved43[39];         /*!< Reserved                                058h-0FFh */
-  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */
-  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */
-} USB_OTG_GlobalTypeDef;
-
-
-/**
-  * @brief USB_OTG_device_Registers
-  */
-typedef struct
-{
-  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */
-  __IO uint32_t DCTL;            /*!< dev Control Register         804h */
-  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */
-  uint32_t Reserved0C;           /*!< Reserved                     80Ch */
-  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */
-  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */
-  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */
-  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */
-  uint32_t  Reserved20;          /*!< Reserved                     820h */
-  uint32_t Reserved9;            /*!< Reserved                     824h */
-  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */
-  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */
-  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */
-  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */
-  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */
-  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */
-  uint32_t Reserved40;           /*!< dedicated EP mask            840h */
-  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */
-  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */
-  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */
-} USB_OTG_DeviceTypeDef;
-
-
-/**
-  * @brief USB_OTG_IN_Endpoint-Specific_Register
-  */
-typedef struct
-{
-  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */
-  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */
-  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */
-  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */
-  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */
-  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */
-  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
-  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
-} USB_OTG_INEndpointTypeDef;
-
-
-/**
-  * @brief USB_OTG_OUT_Endpoint-Specific_Registers
-  */
-typedef struct
-{
-  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */
-  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */
-  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */
-  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */
-  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */
-  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */
-  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
-} USB_OTG_OUTEndpointTypeDef;
-
-
-/**
-  * @brief USB_OTG_Host_Mode_Register_Structures
-  */
-typedef struct
-{
-  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */
-  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */
-  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */
-  uint32_t Reserved40C;           /*!< Reserved                             40Ch */
-  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */
-  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */
-  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */
-} USB_OTG_HostTypeDef;
-
-/**
-  * @brief USB_OTG_Host_Channel_Specific_Registers
-  */
-typedef struct
-{
-  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */
-  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */
-  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */
-  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */
-  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */
-  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */
-  uint32_t Reserved[2];           /*!< Reserved                                      */
-} USB_OTG_HostChannelTypeDef;
-/**
-  * @}
-  */
-
-
-
-
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-#define RAMITCM_BASE           0x00000000U /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM  */
-#define FLASHITCM_BASE         0x00200000U /*!< Base address of : (up to 1 MB) embedded FLASH memory  accessible over ITCM              */
-#define FLASHAXI_BASE          0x08000000U /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI                */
-#define RAMDTCM_BASE           0x20000000U /*!< Base address of : 64KB system data RAM accessible over DTCM                             */
-#define PERIPH_BASE            0x40000000U /*!< Base address of : AHB/ABP Peripherals                                                   */
-#define BKPSRAM_BASE           0x40024000U /*!< Base address of : Backup SRAM(4 KB)                                                     */
-#define QSPI_BASE              0x90000000U /*!< Base address of : QSPI memories  accessible over AXI                                    */
-#define FMC_R_BASE             0xA0000000U /*!< Base address of : FMC Control registers                                                 */
-#define QSPI_R_BASE            0xA0001000U /*!< Base address of : QSPI Control  registers                                               */
-#define SRAM1_BASE             0x20010000U /*!< Base address of : 240KB RAM1 accessible over AXI/AHB                                    */
-#define SRAM2_BASE             0x2004C000U /*!< Base address of : 16KB RAM2 accessible over AXI/AHB                                     */
-#define FLASH_END              0x080FFFFFU /*!< FLASH end address */
-
-/* Legacy define */
-#define FLASH_BASE     FLASHAXI_BASE
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE        PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000U)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)
-#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800U)
-#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00U)
-#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000U)
-#define LPTIM1_BASE           (APB1PERIPH_BASE + 0x2400U)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)
-#define SPDIFRX_BASE          (APB1PERIPH_BASE + 0x4000U)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800U)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00U)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x5000U)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)
-#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)
-#define I2C4_BASE             (APB1PERIPH_BASE + 0x6000U)
-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)
-#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800U)
-#define CEC_BASE              (APB1PERIPH_BASE + 0x6C00U)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)
-#define UART7_BASE            (APB1PERIPH_BASE + 0x7800U)
-#define UART8_BASE            (APB1PERIPH_BASE + 0x7C00U)
-
-/*!< APB2 peripherals */
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000U)
-#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400U)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x1000U)
-#define USART6_BASE           (APB2PERIPH_BASE + 0x1400U)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000U)
-#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100U)
-#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200U)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x2300U)
-#define SDMMC1_BASE           (APB2PERIPH_BASE + 0x2C00U)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)
-#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400U)
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800U)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00U)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000U)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400U)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800U)
-#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000U)
-#define SPI6_BASE             (APB2PERIPH_BASE + 0x5400U)
-#define SAI1_BASE             (APB2PERIPH_BASE + 0x5800U)
-#define SAI2_BASE             (APB2PERIPH_BASE + 0x5C00U)
-#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004U)
-#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024U)
-#define SAI2_Block_A_BASE     (SAI2_BASE + 0x004U)
-#define SAI2_Block_B_BASE     (SAI2_BASE + 0x024U)
-#define LTDC_BASE             (APB2PERIPH_BASE + 0x6800U)
-#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84U)
-#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104U)
-/*!< AHB1 peripherals */
-#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000U)
-#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400U)
-#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800U)
-#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00U)
-#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000U)
-#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400U)
-#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800U)
-#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00U)
-#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000U)
-#define GPIOJ_BASE            (AHB1PERIPH_BASE + 0x2400U)
-#define GPIOK_BASE            (AHB1PERIPH_BASE + 0x2800U)
-#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)
-#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800U)
-#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00U)
-#define UID_BASE              0x1FF0F420U                   /*!< Unique device ID register base address */
-#define FLASHSIZE_BASE        0x1FF0F442U                   /*!< FLASH Size register base address */
-#define PACKAGESIZE_BASE      0x1FFF7BF0U                   /*!< Package size register base address */
-#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000U)
-#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010U)
-#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028U)
-#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040U)
-#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058U)
-#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070U)
-#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088U)
-#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0U)
-#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8U)
-#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400U)
-#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010U)
-#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028U)
-#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040U)
-#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058U)
-#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070U)
-#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088U)
-#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0U)
-#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)
-#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000U)
-#define ETH_MAC_BASE          (ETH_BASE)
-#define ETH_MMC_BASE          (ETH_BASE + 0x0100U)
-#define ETH_PTP_BASE          (ETH_BASE + 0x0700U)
-#define ETH_DMA_BASE          (ETH_BASE + 0x1000U)
-#define DMA2D_BASE            (AHB1PERIPH_BASE + 0xB000U)
-/*!< AHB2 peripherals */
-#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000U)
-#define CRYP_BASE             (AHB2PERIPH_BASE + 0x60000U)
-#define HASH_BASE             (AHB2PERIPH_BASE + 0x60400U)
-#define HASH_DIGEST_BASE      (AHB2PERIPH_BASE + 0x60710U)
-#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800U)
-/*!< FMC Bankx registers base address */
-#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000U)
-#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104U)
-#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080U)
-#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140U)
-
-/* Debug MCU registers base address */
-#define DBGMCU_BASE           0xE0042000U
-
-/*!< USB registers base address */
-#define USB_OTG_HS_PERIPH_BASE               0x40040000U
-#define USB_OTG_FS_PERIPH_BASE               0x50000000U
-
-#define USB_OTG_GLOBAL_BASE                  0x000U
-#define USB_OTG_DEVICE_BASE                  0x800U
-#define USB_OTG_IN_ENDPOINT_BASE             0x900U
-#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U
-#define USB_OTG_EP_REG_SIZE                  0x20U
-#define USB_OTG_HOST_BASE                    0x400U
-#define USB_OTG_HOST_PORT_BASE               0x440U
-#define USB_OTG_HOST_CHANNEL_BASE            0x500U
-#define USB_OTG_HOST_CHANNEL_SIZE            0x20U
-#define USB_OTG_PCGCCTL_BASE                 0xE00U
-#define USB_OTG_FIFO_BASE                    0x1000U
-#define USB_OTG_FIFO_SIZE                    0x1000U
-
-/**
-  * @}
-  */
-
-/** @addtogroup Peripheral_declaration
-  * @{
-  */
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
-#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
-#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
-#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define SPDIFRX             ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define UART4               ((USART_TypeDef *) UART4_BASE)
-#define UART5               ((USART_TypeDef *) UART5_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
-#define I2C4                ((I2C_TypeDef *) I2C4_BASE)
-#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
-#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
-#define CEC                 ((CEC_TypeDef *) CEC_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
-#define UART7               ((USART_TypeDef *) UART7_BASE)
-#define UART8               ((USART_TypeDef *) UART8_BASE)
-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
-#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define USART6              ((USART_TypeDef *) USART6_BASE)
-#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
-#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
-#define SDMMC1              ((SDMMC_TypeDef *) SDMMC1_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define SPI4                ((SPI_TypeDef *) SPI4_BASE)
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-#define SPI5                ((SPI_TypeDef *) SPI5_BASE)
-#define SPI6                ((SPI_TypeDef *) SPI6_BASE)
-#define SAI1                ((SAI_TypeDef *) SAI1_BASE)
-#define SAI2                ((SAI_TypeDef *) SAI2_BASE)
-#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
-#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
-#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
-#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
-#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)
-#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
-#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
-#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)
-#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
-#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
-#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
-#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
-#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
-#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
-#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
-#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
-#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
-#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
-#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
-#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
-#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
-#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
-#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
-#define ETH                 ((ETH_TypeDef *) ETH_BASE)
-#define DMA2D               ((DMA2D_TypeDef *)DMA2D_BASE)
-#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
-#define CRYP                ((CRYP_TypeDef *) CRYP_BASE)
-#define HASH                ((HASH_TypeDef *) HASH_BASE)
-#define HASH_DIGEST         ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
-#define RNG                 ((RNG_TypeDef *) RNG_BASE)
-#define FMC_Bank1           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
-#define FMC_Bank1E          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
-#define FMC_Bank3           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
-#define FMC_Bank5_6         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
-#define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
-#define USB_OTG_HS          ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-
-/******************************************************************************/
-/*                         Peripheral Registers_Bits_Definition               */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Analog to Digital Converter                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          0x00000001U        /*!<Analog watchdog flag                                 */
-#define  ADC_SR_EOC                          0x00000002U        /*!<End of conversion                                    */
-#define  ADC_SR_JEOC                         0x00000004U        /*!<Injected channel end of conversion                   */
-#define  ADC_SR_JSTRT                        0x00000008U        /*!<Injected channel Start flag                          */
-#define  ADC_SR_STRT                         0x00000010U        /*!<Regular channel Start flag                           */
-#define  ADC_SR_OVR                          0x00000020U        /*!<Overrun flag                                         */
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC                             */
-#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable                    */
-#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels               */
-#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
-#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion                  */
-#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels               */
-#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels              */
-#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels          */
-#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels           */
-#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution)                           */
-#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
-
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF                                       */
-#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion                                        */
-#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode                                    */
-#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC)                           */
-#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection                                  */
-#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment                                               */
-#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
-#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      ((uint16_t)0xFFFFU)            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      ((uint16_t)0xFFFFU)            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      ((uint16_t)0xFFFFU)            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      ((uint16_t)0xFFFFU)            /*!<Injected data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag               */
-#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion                  */
-#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag        */
-#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag         */
-#define  ADC_CSR_OVR1                        0x00000020U        /*!<ADC1 Overrun flag                       */
-#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag               */
-#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion                  */
-#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag        */
-#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag         */
-#define  ADC_CSR_OVR2                        0x00002000U        /*!<ADC2 Overrun flag                       */
-#define  ADC_CSR_AWD3                        0x00010000U        /*!<ADC3 Analog watchdog flag               */
-#define  ADC_CSR_EOC3                        0x00020000U        /*!<ADC3 End of conversion                  */
-#define  ADC_CSR_JEOC3                       0x00040000U        /*!<ADC3 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT3                      0x00080000U        /*!<ADC3 Injected channel Start flag        */
-#define  ADC_CSR_STRT3                       0x00100000U        /*!<ADC3 Regular channel Start flag         */
-#define  ADC_CSR_OVR3                        0x00200000U        /*!<ADC3 Overrun flag                       */
-
-/* Legacy defines */
-#define  ADC_CSR_DOVR1                       ADC_CSR_OVR1
-#define  ADC_CSR_DOVR2                       ADC_CSR_OVR2
-#define  ADC_CSR_DOVR3                       ADC_CSR_OVR3
-
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
-#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
-#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
-#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */
-#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
-
-/*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                       0x0000FFFFU         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                       0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Controller Area Network                            */
-/*                                                                            */
-/******************************************************************************/
-/*!<CAN control and status registers */
-/*******************  Bit definition for CAN_MCR register  ********************/
-#define  CAN_MCR_INRQ                        0x00000001U        /*!<Initialization Request            */
-#define  CAN_MCR_SLEEP                       0x00000002U        /*!<Sleep Mode Request                */
-#define  CAN_MCR_TXFP                        0x00000004U        /*!<Transmit FIFO Priority            */
-#define  CAN_MCR_RFLM                        0x00000008U        /*!<Receive FIFO Locked Mode          */
-#define  CAN_MCR_NART                        0x00000010U        /*!<No Automatic Retransmission       */
-#define  CAN_MCR_AWUM                        0x00000020U        /*!<Automatic Wakeup Mode             */
-#define  CAN_MCR_ABOM                        0x00000040U        /*!<Automatic Bus-Off Management      */
-#define  CAN_MCR_TTCM                        0x00000080U        /*!<Time Triggered Communication Mode */
-#define  CAN_MCR_RESET                       0x00008000U        /*!<bxCAN software master reset       */
-
-/*******************  Bit definition for CAN_MSR register  ********************/
-#define  CAN_MSR_INAK                        0x00000001U        /*!<Initialization Acknowledge  */
-#define  CAN_MSR_SLAK                        0x00000002U        /*!<Sleep Acknowledge           */
-#define  CAN_MSR_ERRI                        0x00000004U        /*!<Error Interrupt             */
-#define  CAN_MSR_WKUI                        0x00000008U        /*!<Wakeup Interrupt            */
-#define  CAN_MSR_SLAKI                       0x00000010U        /*!<Sleep Acknowledge Interrupt */
-#define  CAN_MSR_TXM                         0x00000100U        /*!<Transmit Mode               */
-#define  CAN_MSR_RXM                         0x00000200U        /*!<Receive Mode                */
-#define  CAN_MSR_SAMP                        0x00000400U        /*!<Last Sample Point           */
-#define  CAN_MSR_RX                          0x00000800U        /*!<CAN Rx Signal               */
-
-/*******************  Bit definition for CAN_TSR register  ********************/
-#define  CAN_TSR_RQCP0                       0x00000001U        /*!<Request Completed Mailbox0      */
-#define  CAN_TSR_TXOK0                       0x00000002U        /*!<Transmission OK of Mailbox0     */
-#define  CAN_TSR_ALST0                       0x00000004U        /*!<Arbitration Lost for Mailbox0   */
-#define  CAN_TSR_TERR0                       0x00000008U        /*!<Transmission Error of Mailbox0  */
-#define  CAN_TSR_ABRQ0                       0x00000080U        /*!<Abort Request for Mailbox0      */
-#define  CAN_TSR_RQCP1                       0x00000100U        /*!<Request Completed Mailbox1      */
-#define  CAN_TSR_TXOK1                       0x00000200U        /*!<Transmission OK of Mailbox1     */
-#define  CAN_TSR_ALST1                       0x00000400U        /*!<Arbitration Lost for Mailbox1   */
-#define  CAN_TSR_TERR1                       0x00000800U        /*!<Transmission Error of Mailbox1  */
-#define  CAN_TSR_ABRQ1                       0x00008000U        /*!<Abort Request for Mailbox 1     */
-#define  CAN_TSR_RQCP2                       0x00010000U        /*!<Request Completed Mailbox2      */
-#define  CAN_TSR_TXOK2                       0x00020000U        /*!<Transmission OK of Mailbox 2    */
-#define  CAN_TSR_ALST2                       0x00040000U        /*!<Arbitration Lost for mailbox 2  */
-#define  CAN_TSR_TERR2                       0x00080000U        /*!<Transmission Error of Mailbox 2 */
-#define  CAN_TSR_ABRQ2                       0x00800000U        /*!<Abort Request for Mailbox 2     */
-#define  CAN_TSR_CODE                        0x03000000U        /*!<Mailbox Code                    */
-
-#define  CAN_TSR_TME                         0x1C000000U        /*!<TME[2:0] bits */
-#define  CAN_TSR_TME0                        0x04000000U        /*!<Transmit Mailbox 0 Empty */
-#define  CAN_TSR_TME1                        0x08000000U        /*!<Transmit Mailbox 1 Empty */
-#define  CAN_TSR_TME2                        0x10000000U        /*!<Transmit Mailbox 2 Empty */
-
-#define  CAN_TSR_LOW                         0xE0000000U        /*!<LOW[2:0] bits */
-#define  CAN_TSR_LOW0                        0x20000000U        /*!<Lowest Priority Flag for Mailbox 0 */
-#define  CAN_TSR_LOW1                        0x40000000U        /*!<Lowest Priority Flag for Mailbox 1 */
-#define  CAN_TSR_LOW2                        0x80000000U        /*!<Lowest Priority Flag for Mailbox 2 */
-
-/*******************  Bit definition for CAN_RF0R register  *******************/
-#define  CAN_RF0R_FMP0                       0x00000003U        /*!<FIFO 0 Message Pending        */
-#define  CAN_RF0R_FULL0                      0x00000008U        /*!<FIFO 0 Full                   */
-#define  CAN_RF0R_FOVR0                      0x00000010U        /*!<FIFO 0 Overrun                */
-#define  CAN_RF0R_RFOM0                      0x00000020U        /*!<Release FIFO 0 Output Mailbox */
-
-/*******************  Bit definition for CAN_RF1R register  *******************/
-#define  CAN_RF1R_FMP1                       0x00000003U        /*!<FIFO 1 Message Pending        */
-#define  CAN_RF1R_FULL1                      0x00000008U        /*!<FIFO 1 Full                   */
-#define  CAN_RF1R_FOVR1                      0x00000010U        /*!<FIFO 1 Overrun                */
-#define  CAN_RF1R_RFOM1                      0x00000020U        /*!<Release FIFO 1 Output Mailbox */
-
-/********************  Bit definition for CAN_IER register  *******************/
-#define  CAN_IER_TMEIE                       0x00000001U        /*!<Transmit Mailbox Empty Interrupt Enable */
-#define  CAN_IER_FMPIE0                      0x00000002U        /*!<FIFO Message Pending Interrupt Enable   */
-#define  CAN_IER_FFIE0                       0x00000004U        /*!<FIFO Full Interrupt Enable              */
-#define  CAN_IER_FOVIE0                      0x00000008U        /*!<FIFO Overrun Interrupt Enable           */
-#define  CAN_IER_FMPIE1                      0x00000010U        /*!<FIFO Message Pending Interrupt Enable   */
-#define  CAN_IER_FFIE1                       0x00000020U        /*!<FIFO Full Interrupt Enable              */
-#define  CAN_IER_FOVIE1                      0x00000040U        /*!<FIFO Overrun Interrupt Enable           */
-#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error Warning Interrupt Enable          */
-#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error Passive Interrupt Enable          */
-#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-Off Interrupt Enable                */
-#define  CAN_IER_LECIE                       0x00000800U        /*!<Last Error Code Interrupt Enable        */
-#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error Interrupt Enable                  */
-#define  CAN_IER_WKUIE                       0x00010000U        /*!<Wakeup Interrupt Enable                 */
-#define  CAN_IER_SLKIE                       0x00020000U        /*!<Sleep Interrupt Enable                  */
-
-/********************  Bit definition for CAN_ESR register  *******************/
-#define  CAN_ESR_EWGF                        0x00000001U        /*!<Error Warning Flag */
-#define  CAN_ESR_EPVF                        0x00000002U        /*!<Error Passive Flag */
-#define  CAN_ESR_BOFF                        0x00000004U        /*!<Bus-Off Flag */
-
-#define  CAN_ESR_LEC                         0x00000070U        /*!<LEC[2:0] bits (Last Error Code) */
-#define  CAN_ESR_LEC_0                       0x00000010U        /*!<Bit 0 */
-#define  CAN_ESR_LEC_1                       0x00000020U        /*!<Bit 1 */
-#define  CAN_ESR_LEC_2                       0x00000040U        /*!<Bit 2 */
-
-#define  CAN_ESR_TEC                         0x00FF0000U        /*!<Least significant byte of the 9-bit Transmit Error Counter */
-#define  CAN_ESR_REC                         0xFF000000U        /*!<Receive Error Counter */
-
-/*******************  Bit definition for CAN_BTR register  ********************/
-#define  CAN_BTR_BRP                         0x000003FFU        /*!<Baud Rate Prescaler           */
-#define  CAN_BTR_TS1                         0x000F0000U        /*!<Time Segment 1                */
-#define  CAN_BTR_TS1_0                       0x00010000U        /*!<Bit 0 */
-#define  CAN_BTR_TS1_1                       0x00020000U        /*!<Bit 1 */
-#define  CAN_BTR_TS1_2                       0x00040000U        /*!<Bit 2 */
-#define  CAN_BTR_TS1_3                       0x00080000U        /*!<Bit 3 */
-#define  CAN_BTR_TS2                         0x00700000U        /*!<Time Segment 2                */
-#define  CAN_BTR_TS2_0                       0x00100000U        /*!<Bit 0 */
-#define  CAN_BTR_TS2_1                       0x00200000U        /*!<Bit 1 */
-#define  CAN_BTR_TS2_2                       0x00400000U        /*!<Bit 2 */
-#define  CAN_BTR_SJW                         0x03000000U        /*!<Resynchronization Jump Width  */
-#define  CAN_BTR_SJW_0                       0x01000000U        /*!<Bit 0 */
-#define  CAN_BTR_SJW_1                       0x02000000U        /*!<Bit 1 */
-#define  CAN_BTR_LBKM                        0x40000000U        /*!<Loop Back Mode (Debug)        */
-#define  CAN_BTR_SILM                        0x80000000U        /*!<Silent Mode                   */
-
-/*!<Mailbox registers */
-/******************  Bit definition for CAN_TI0R register  ********************/
-#define  CAN_TI0R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request                   */
-#define  CAN_TI0R_RTR                        0x00000002U        /*!<Remote Transmission Request                */
-#define  CAN_TI0R_IDE                        0x00000004U        /*!<Identifier Extension                       */
-#define  CAN_TI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier                        */
-#define  CAN_TI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/******************  Bit definition for CAN_TDT0R register  *******************/
-#define  CAN_TDT0R_DLC                       0x0000000FU        /*!<Data Length Code     */
-#define  CAN_TDT0R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp   */
-
-/******************  Bit definition for CAN_TDL0R register  *******************/
-#define  CAN_TDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/******************  Bit definition for CAN_TDH0R register  *******************/
-#define  CAN_TDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI1R register  *******************/
-#define  CAN_TI1R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request                   */
-#define  CAN_TI1R_RTR                        0x00000002U        /*!<Remote Transmission Request                */
-#define  CAN_TI1R_IDE                        0x00000004U        /*!<Identifier Extension                       */
-#define  CAN_TI1R_EXID                       0x001FFFF8U        /*!<Extended Identifier                        */
-#define  CAN_TI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT1R register  ******************/
-#define  CAN_TDT1R_DLC                       0x0000000FU        /*!<Data Length Code     */
-#define  CAN_TDT1R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp   */
-
-/*******************  Bit definition for CAN_TDL1R register  ******************/
-#define  CAN_TDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH1R register  ******************/
-#define  CAN_TDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI2R register  *******************/
-#define  CAN_TI2R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request                   */
-#define  CAN_TI2R_RTR                        0x00000002U        /*!<Remote Transmission Request                */
-#define  CAN_TI2R_IDE                        0x00000004U        /*!<Identifier Extension                       */
-#define  CAN_TI2R_EXID                       0x001FFFF8U        /*!<Extended identifier                        */
-#define  CAN_TI2R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT2R register  ******************/
-#define  CAN_TDT2R_DLC                       0x0000000FU        /*!<Data Length Code      */
-#define  CAN_TDT2R_TGT                       0x00000100U        /*!<Transmit Global Time  */
-#define  CAN_TDT2R_TIME                      0xFFFF0000U        /*!<Message Time Stamp    */
-
-/*******************  Bit definition for CAN_TDL2R register  ******************/
-#define  CAN_TDL2R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL2R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL2R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL2R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH2R register  ******************/
-#define  CAN_TDH2R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH2R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH2R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH2R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI0R register  *******************/
-#define  CAN_RI0R_RTR                        0x00000002U        /*!<Remote Transmission Request                */
-#define  CAN_RI0R_IDE                        0x00000004U        /*!<Identifier Extension                       */
-#define  CAN_RI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier                        */
-#define  CAN_RI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT0R register  ******************/
-#define  CAN_RDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_RDT0R_FMI                       0x0000FF00U        /*!<Filter Match Index */
-#define  CAN_RDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL0R register  ******************/
-#define  CAN_RDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_RDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_RDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_RDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH0R register  ******************/
-#define  CAN_RDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_RDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_RDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_RDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI1R register  *******************/
-#define  CAN_RI1R_RTR                        0x00000002U        /*!<Remote Transmission Request                */
-#define  CAN_RI1R_IDE                        0x00000004U        /*!<Identifier Extension                       */
-#define  CAN_RI1R_EXID                       0x001FFFF8U        /*!<Extended identifier                        */
-#define  CAN_RI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT1R register  ******************/
-#define  CAN_RDT1R_DLC                       0x0000000FU        /*!<Data Length Code   */
-#define  CAN_RDT1R_FMI                       0x0000FF00U        /*!<Filter Match Index */
-#define  CAN_RDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL1R register  ******************/
-#define  CAN_RDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_RDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_RDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_RDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH1R register  ******************/
-#define  CAN_RDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_RDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_RDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_RDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*!<CAN filter registers */
-/*******************  Bit definition for CAN_FMR register  ********************/
-#define  CAN_FMR_FINIT                       ((uint8_t)0x01U)               /*!<Filter Init Mode */
-#define  CAN_FMR_CAN2SB                      0x00003F00U        /*!<CAN2 start bank */
-
-/*******************  Bit definition for CAN_FM1R register  *******************/
-#define  CAN_FM1R_FBM                        0x3FFFU            /*!<Filter Mode */
-#define  CAN_FM1R_FBM0                       0x0001U            /*!<Filter Init Mode bit 0  */
-#define  CAN_FM1R_FBM1                       0x0002U            /*!<Filter Init Mode bit 1  */
-#define  CAN_FM1R_FBM2                       0x0004U            /*!<Filter Init Mode bit 2  */
-#define  CAN_FM1R_FBM3                       0x0008U            /*!<Filter Init Mode bit 3  */
-#define  CAN_FM1R_FBM4                       0x0010U            /*!<Filter Init Mode bit 4  */
-#define  CAN_FM1R_FBM5                       0x0020U            /*!<Filter Init Mode bit 5  */
-#define  CAN_FM1R_FBM6                       0x0040U            /*!<Filter Init Mode bit 6  */
-#define  CAN_FM1R_FBM7                       0x0080U            /*!<Filter Init Mode bit 7  */
-#define  CAN_FM1R_FBM8                       0x0100U            /*!<Filter Init Mode bit 8  */
-#define  CAN_FM1R_FBM9                       0x0200U            /*!<Filter Init Mode bit 9  */
-#define  CAN_FM1R_FBM10                      0x0400U            /*!<Filter Init Mode bit 10 */
-#define  CAN_FM1R_FBM11                      0x0800U            /*!<Filter Init Mode bit 11 */
-#define  CAN_FM1R_FBM12                      0x1000U            /*!<Filter Init Mode bit 12 */
-#define  CAN_FM1R_FBM13                      0x2000U            /*!<Filter Init Mode bit 13 */
-
-/*******************  Bit definition for CAN_FS1R register  *******************/
-#define  CAN_FS1R_FSC                        0x00003FFFU        /*!<Filter Scale Configuration        */
-#define  CAN_FS1R_FSC0                       0x00000001U        /*!<Filter Scale Configuration bit 0  */
-#define  CAN_FS1R_FSC1                       0x00000002U        /*!<Filter Scale Configuration bit 1  */
-#define  CAN_FS1R_FSC2                       0x00000004U        /*!<Filter Scale Configuration bit 2  */
-#define  CAN_FS1R_FSC3                       0x00000008U        /*!<Filter Scale Configuration bit 3  */
-#define  CAN_FS1R_FSC4                       0x00000010U        /*!<Filter Scale Configuration bit 4  */
-#define  CAN_FS1R_FSC5                       0x00000020U        /*!<Filter Scale Configuration bit 5  */
-#define  CAN_FS1R_FSC6                       0x00000040U        /*!<Filter Scale Configuration bit 6  */
-#define  CAN_FS1R_FSC7                       0x00000080U        /*!<Filter Scale Configuration bit 7  */
-#define  CAN_FS1R_FSC8                       0x00000100U        /*!<Filter Scale Configuration bit 8  */
-#define  CAN_FS1R_FSC9                       0x00000200U        /*!<Filter Scale Configuration bit 9  */
-#define  CAN_FS1R_FSC10                      0x00000400U        /*!<Filter Scale Configuration bit 10 */
-#define  CAN_FS1R_FSC11                      0x00000800U        /*!<Filter Scale Configuration bit 11 */
-#define  CAN_FS1R_FSC12                      0x00001000U        /*!<Filter Scale Configuration bit 12 */
-#define  CAN_FS1R_FSC13                      0x00002000U        /*!<Filter Scale Configuration bit 13 */
-
-/******************  Bit definition for CAN_FFA1R register  *******************/
-#define  CAN_FFA1R_FFA                       0x00003FFFU        /*!<Filter FIFO Assignment */
-#define  CAN_FFA1R_FFA0                      0x00000001U        /*!<Filter FIFO Assignment for Filter 0 */
-#define  CAN_FFA1R_FFA1                      0x00000002U        /*!<Filter FIFO Assignment for Filter 1 */
-#define  CAN_FFA1R_FFA2                      0x00000004U        /*!<Filter FIFO Assignment for Filter 2 */
-#define  CAN_FFA1R_FFA3                      0x00000008U        /*!<Filter FIFO Assignment for Filter 3 */
-#define  CAN_FFA1R_FFA4                      0x00000010U        /*!<Filter FIFO Assignment for Filter 4 */
-#define  CAN_FFA1R_FFA5                      0x00000020U        /*!<Filter FIFO Assignment for Filter 5 */
-#define  CAN_FFA1R_FFA6                      0x00000040U        /*!<Filter FIFO Assignment for Filter 6 */
-#define  CAN_FFA1R_FFA7                      0x00000080U        /*!<Filter FIFO Assignment for Filter 7 */
-#define  CAN_FFA1R_FFA8                      0x00000100U        /*!<Filter FIFO Assignment for Filter 8 */
-#define  CAN_FFA1R_FFA9                      0x00000200U        /*!<Filter FIFO Assignment for Filter 9 */
-#define  CAN_FFA1R_FFA10                     0x00000400U        /*!<Filter FIFO Assignment for Filter 10 */
-#define  CAN_FFA1R_FFA11                     0x00000800U        /*!<Filter FIFO Assignment for Filter 11 */
-#define  CAN_FFA1R_FFA12                     0x00001000U        /*!<Filter FIFO Assignment for Filter 12 */
-#define  CAN_FFA1R_FFA13                     0x00002000U        /*!<Filter FIFO Assignment for Filter 13 */
-
-/*******************  Bit definition for CAN_FA1R register  *******************/
-#define  CAN_FA1R_FACT                       0x00003FFFU        /*!<Filter Active    */
-#define  CAN_FA1R_FACT0                      0x00000001U        /*!<Filter 0 Active  */
-#define  CAN_FA1R_FACT1                      0x00000002U        /*!<Filter 1 Active  */
-#define  CAN_FA1R_FACT2                      0x00000004U        /*!<Filter 2 Active  */
-#define  CAN_FA1R_FACT3                      0x00000008U        /*!<Filter 3 Active  */
-#define  CAN_FA1R_FACT4                      0x00000010U        /*!<Filter 4 Active  */
-#define  CAN_FA1R_FACT5                      0x00000020U        /*!<Filter 5 Active  */
-#define  CAN_FA1R_FACT6                      0x00000040U        /*!<Filter 6 Active  */
-#define  CAN_FA1R_FACT7                      0x00000080U        /*!<Filter 7 Active  */
-#define  CAN_FA1R_FACT8                      0x00000100U        /*!<Filter 8 Active  */
-#define  CAN_FA1R_FACT9                      0x00000200U        /*!<Filter 9 Active  */
-#define  CAN_FA1R_FACT10                     0x00000400U        /*!<Filter 10 Active */
-#define  CAN_FA1R_FACT11                     0x00000800U        /*!<Filter 11 Active */
-#define  CAN_FA1R_FACT12                     0x00001000U        /*!<Filter 12 Active */
-#define  CAN_FA1R_FACT13                     0x00002000U        /*!<Filter 13 Active */
-
-/*******************  Bit definition for CAN_F0R1 register  *******************/
-#define  CAN_F0R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F0R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F0R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F0R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F0R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F0R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F0R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F0R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F0R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F0R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F0R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F0R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F0R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F0R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F0R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F0R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F0R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F0R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F0R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F0R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F0R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F0R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F0R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F0R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F0R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F0R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F0R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F0R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F0R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F0R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F0R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F0R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R1 register  *******************/
-#define  CAN_F1R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F1R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F1R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F1R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F1R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F1R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F1R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F1R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F1R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F1R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F1R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F1R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F1R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F1R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F1R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F1R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F1R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F1R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F1R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F1R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F1R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F1R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F1R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F1R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F1R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F1R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F1R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F1R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F1R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F1R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F1R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F1R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R1 register  *******************/
-#define  CAN_F2R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F2R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F2R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F2R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F2R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F2R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F2R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F2R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F2R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F2R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F2R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F2R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F2R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F2R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F2R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F2R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F2R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F2R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F2R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F2R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F2R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F2R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F2R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F2R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F2R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F2R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F2R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F2R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F2R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F2R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F2R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F2R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R1 register  *******************/
-#define  CAN_F3R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F3R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F3R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F3R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F3R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F3R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F3R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F3R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F3R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F3R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F3R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F3R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F3R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F3R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F3R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F3R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F3R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F3R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F3R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F3R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F3R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F3R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F3R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F3R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F3R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F3R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F3R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F3R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F3R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F3R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F3R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F3R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R1 register  *******************/
-#define  CAN_F4R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F4R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F4R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F4R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F4R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F4R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F4R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F4R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F4R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F4R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F4R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F4R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F4R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F4R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F4R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F4R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F4R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F4R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F4R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F4R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F4R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F4R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F4R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F4R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F4R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F4R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F4R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F4R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F4R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F4R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F4R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F4R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R1 register  *******************/
-#define  CAN_F5R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F5R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F5R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F5R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F5R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F5R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F5R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F5R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F5R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F5R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F5R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F5R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F5R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F5R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F5R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F5R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F5R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F5R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F5R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F5R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F5R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F5R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F5R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F5R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F5R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F5R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F5R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F5R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F5R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F5R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F5R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F5R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R1 register  *******************/
-#define  CAN_F6R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F6R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F6R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F6R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F6R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F6R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F6R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F6R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F6R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F6R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F6R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F6R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F6R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F6R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F6R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F6R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F6R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F6R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F6R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F6R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F6R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F6R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F6R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F6R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F6R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F6R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F6R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F6R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F6R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F6R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F6R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F6R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R1 register  *******************/
-#define  CAN_F7R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F7R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F7R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F7R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F7R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F7R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F7R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F7R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F7R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F7R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F7R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F7R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F7R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F7R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F7R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F7R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F7R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F7R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F7R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F7R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F7R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F7R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F7R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F7R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F7R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F7R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F7R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F7R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F7R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F7R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F7R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F7R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R1 register  *******************/
-#define  CAN_F8R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F8R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F8R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F8R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F8R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F8R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F8R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F8R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F8R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F8R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F8R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F8R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F8R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F8R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F8R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F8R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F8R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F8R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F8R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F8R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F8R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F8R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F8R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F8R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F8R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F8R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F8R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F8R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F8R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F8R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F8R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F8R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R1 register  *******************/
-#define  CAN_F9R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F9R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F9R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F9R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F9R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F9R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F9R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F9R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F9R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F9R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F9R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F9R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F9R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F9R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F9R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F9R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F9R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F9R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F9R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F9R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F9R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F9R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F9R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F9R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F9R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F9R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F9R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F9R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F9R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F9R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F9R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F9R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R1 register  ******************/
-#define  CAN_F10R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F10R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F10R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F10R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F10R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F10R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F10R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F10R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F10R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F10R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F10R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F10R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F10R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F10R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F10R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F10R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F10R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F10R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F10R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F10R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F10R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F10R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F10R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F10R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F10R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F10R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F10R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F10R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F10R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F10R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F10R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F10R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R1 register  ******************/
-#define  CAN_F11R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F11R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F11R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F11R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F11R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F11R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F11R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F11R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F11R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F11R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F11R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F11R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F11R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F11R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F11R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F11R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F11R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F11R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F11R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F11R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F11R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F11R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F11R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F11R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F11R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F11R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F11R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F11R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F11R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F11R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F11R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F11R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R1 register  ******************/
-#define  CAN_F12R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F12R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F12R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F12R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F12R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F12R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F12R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F12R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F12R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F12R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F12R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F12R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F12R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F12R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F12R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F12R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F12R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F12R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F12R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F12R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F12R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F12R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F12R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F12R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F12R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F12R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F12R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F12R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F12R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F12R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F12R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F12R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R1 register  ******************/
-#define  CAN_F13R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F13R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F13R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F13R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F13R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F13R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F13R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F13R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F13R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F13R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F13R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F13R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F13R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F13R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F13R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F13R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F13R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F13R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F13R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F13R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F13R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F13R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F13R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F13R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F13R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F13R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F13R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F13R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F13R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F13R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F13R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F13R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F0R2 register  *******************/
-#define  CAN_F0R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F0R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F0R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F0R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F0R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F0R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F0R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F0R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F0R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F0R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F0R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F0R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F0R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F0R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F0R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F0R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F0R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F0R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F0R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F0R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F0R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F0R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F0R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F0R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F0R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F0R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F0R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F0R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F0R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F0R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F0R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F0R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R2 register  *******************/
-#define  CAN_F1R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F1R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F1R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F1R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F1R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F1R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F1R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F1R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F1R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F1R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F1R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F1R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F1R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F1R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F1R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F1R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F1R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F1R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F1R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F1R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F1R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F1R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F1R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F1R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F1R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F1R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F1R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F1R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F1R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F1R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F1R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F1R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R2 register  *******************/
-#define  CAN_F2R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F2R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F2R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F2R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F2R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F2R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F2R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F2R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F2R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F2R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F2R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F2R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F2R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F2R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F2R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F2R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F2R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F2R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F2R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F2R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F2R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F2R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F2R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F2R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F2R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F2R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F2R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F2R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F2R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F2R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F2R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F2R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R2 register  *******************/
-#define  CAN_F3R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F3R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F3R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F3R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F3R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F3R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F3R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F3R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F3R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F3R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F3R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F3R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F3R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F3R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F3R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F3R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F3R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F3R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F3R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F3R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F3R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F3R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F3R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F3R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F3R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F3R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F3R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F3R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F3R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F3R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F3R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F3R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R2 register  *******************/
-#define  CAN_F4R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F4R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F4R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F4R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F4R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F4R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F4R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F4R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F4R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F4R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F4R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F4R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F4R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F4R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F4R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F4R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F4R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F4R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F4R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F4R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F4R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F4R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F4R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F4R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F4R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F4R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F4R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F4R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F4R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F4R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F4R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F4R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R2 register  *******************/
-#define  CAN_F5R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F5R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F5R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F5R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F5R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F5R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F5R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F5R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F5R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F5R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F5R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F5R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F5R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F5R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F5R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F5R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F5R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F5R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F5R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F5R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F5R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F5R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F5R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F5R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F5R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F5R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F5R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F5R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F5R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F5R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F5R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F5R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R2 register  *******************/
-#define  CAN_F6R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F6R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F6R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F6R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F6R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F6R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F6R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F6R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F6R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F6R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F6R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F6R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F6R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F6R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F6R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F6R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F6R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F6R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F6R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F6R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F6R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F6R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F6R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F6R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F6R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F6R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F6R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F6R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F6R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F6R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F6R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F6R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R2 register  *******************/
-#define  CAN_F7R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F7R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F7R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F7R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F7R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F7R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F7R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F7R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F7R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F7R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F7R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F7R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F7R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F7R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F7R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F7R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F7R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F7R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F7R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F7R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F7R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F7R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F7R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F7R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F7R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F7R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F7R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F7R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F7R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F7R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F7R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F7R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R2 register  *******************/
-#define  CAN_F8R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F8R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F8R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F8R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F8R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F8R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F8R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F8R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F8R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F8R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F8R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F8R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F8R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F8R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F8R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F8R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F8R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F8R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F8R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F8R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F8R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F8R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F8R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F8R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F8R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F8R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F8R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F8R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F8R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F8R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F8R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F8R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R2 register  *******************/
-#define  CAN_F9R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F9R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F9R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F9R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F9R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F9R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F9R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F9R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F9R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F9R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F9R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F9R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F9R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F9R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F9R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F9R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F9R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F9R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F9R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F9R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F9R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F9R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F9R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F9R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F9R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F9R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F9R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F9R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F9R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F9R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F9R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F9R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R2 register  ******************/
-#define  CAN_F10R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F10R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F10R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F10R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F10R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F10R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F10R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F10R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F10R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F10R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F10R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F10R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F10R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F10R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F10R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F10R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F10R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F10R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F10R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F10R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F10R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F10R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F10R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F10R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F10R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F10R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F10R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F10R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F10R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F10R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F10R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F10R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R2 register  ******************/
-#define  CAN_F11R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F11R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F11R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F11R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F11R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F11R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F11R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F11R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F11R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F11R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F11R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F11R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F11R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F11R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F11R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F11R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F11R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F11R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F11R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F11R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F11R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F11R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F11R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F11R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F11R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F11R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F11R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F11R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F11R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F11R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F11R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F11R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R2 register  ******************/
-#define  CAN_F12R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F12R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F12R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F12R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F12R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F12R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F12R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F12R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F12R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F12R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F12R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F12R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F12R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F12R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F12R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F12R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F12R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F12R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F12R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F12R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F12R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F12R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F12R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F12R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F12R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F12R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F12R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F12R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F12R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F12R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F12R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F12R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R2 register  ******************/
-#define  CAN_F13R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F13R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F13R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F13R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F13R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F13R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F13R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F13R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F13R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F13R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F13R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F13R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F13R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F13R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F13R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F13R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F13R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F13R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F13R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F13R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F13R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F13R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F13R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F13R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F13R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F13R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F13R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F13R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F13R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F13R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F13R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F13R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 HDMI-CEC (CEC)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CEC_CR register  *********************/
-#define  CEC_CR_CECEN                        0x00000001U       /*!< CEC Enable                         */
-#define  CEC_CR_TXSOM                        0x00000002U       /*!< CEC Tx Start Of Message            */
-#define  CEC_CR_TXEOM                        0x00000004U       /*!< CEC Tx End Of Message              */
-
-/*******************  Bit definition for CEC_CFGR register  *******************/
-#define  CEC_CFGR_SFT                        0x00000007U       /*!< CEC Signal Free Time               */
-#define  CEC_CFGR_RXTOL                      0x00000008U       /*!< CEC Tolerance                      */
-#define  CEC_CFGR_BRESTP                     0x00000010U       /*!< CEC Rx Stop                        */
-#define  CEC_CFGR_BREGEN                     0x00000020U       /*!< CEC Bit Rising Error generation    */
-#define  CEC_CFGR_LBPEGEN                    0x00000040U       /*!< CEC Long Period Error generation   */
-#define  CEC_CFGR_BRDNOGEN                   0x00000080U       /*!< CEC Broadcast no Error generation  */
-#define  CEC_CFGR_SFTOPT                     0x00000100U       /*!< CEC Signal Free Time optional      */
-#define  CEC_CFGR_OAR                        0x7FFF0000U       /*!< CEC Own Address                    */
-#define  CEC_CFGR_LSTN                       0x80000000U       /*!< CEC Listen mode                    */
-
-/*******************  Bit definition for CEC_TXDR register  *******************/
-#define  CEC_TXDR_TXD                        0x000000FFU       /*!< CEC Tx Data                        */
-
-/*******************  Bit definition for CEC_RXDR register  *******************/
-#define  CEC_TXDR_RXD                        0x000000FFU       /*!< CEC Rx Data                        */
-
-/*******************  Bit definition for CEC_ISR register  ********************/
-#define  CEC_ISR_RXBR                        0x00000001U       /*!< CEC Rx-Byte Received                   */
-#define  CEC_ISR_RXEND                       0x00000002U       /*!< CEC End Of Reception                   */
-#define  CEC_ISR_RXOVR                       0x00000004U       /*!< CEC Rx-Overrun                         */
-#define  CEC_ISR_BRE                         0x00000008U       /*!< CEC Rx Bit Rising Error                */
-#define  CEC_ISR_SBPE                        0x00000010U       /*!< CEC Rx Short Bit period Error          */
-#define  CEC_ISR_LBPE                        0x00000020U       /*!< CEC Rx Long Bit period Error           */
-#define  CEC_ISR_RXACKE                      0x00000040U       /*!< CEC Rx Missing Acknowledge             */
-#define  CEC_ISR_ARBLST                      0x00000080U       /*!< CEC Arbitration Lost                   */
-#define  CEC_ISR_TXBR                        0x00000100U       /*!< CEC Tx Byte Request                    */
-#define  CEC_ISR_TXEND                       0x00000200U       /*!< CEC End of Transmission                */
-#define  CEC_ISR_TXUDR                       0x00000400U       /*!< CEC Tx-Buffer Underrun                 */
-#define  CEC_ISR_TXERR                       0x00000800U       /*!< CEC Tx-Error                           */
-#define  CEC_ISR_TXACKE                      0x00001000U       /*!< CEC Tx Missing Acknowledge             */
-
-/*******************  Bit definition for CEC_IER register  ********************/
-#define  CEC_IER_RXBRIE                      0x00000001U       /*!< CEC Rx-Byte Received IT Enable         */
-#define  CEC_IER_RXENDIE                     0x00000002U       /*!< CEC End Of Reception IT Enable         */
-#define  CEC_IER_RXOVRIE                     0x00000004U       /*!< CEC Rx-Overrun IT Enable               */
-#define  CEC_IER_BREIE                       0x00000008U       /*!< CEC Rx Bit Rising Error IT Enable      */
-#define  CEC_IER_SBPEIE                      0x00000010U       /*!< CEC Rx Short Bit period Error IT Enable*/
-#define  CEC_IER_LBPEIE                      0x00000020U       /*!< CEC Rx Long Bit period Error IT Enable */
-#define  CEC_IER_RXACKEIE                    0x00000040U       /*!< CEC Rx Missing Acknowledge IT Enable   */
-#define  CEC_IER_ARBLSTIE                    0x00000080U       /*!< CEC Arbitration Lost IT Enable         */
-#define  CEC_IER_TXBRIE                      0x00000100U       /*!< CEC Tx Byte Request  IT Enable         */
-#define  CEC_IER_TXENDIE                     0x00000200U       /*!< CEC End of Transmission IT Enable      */
-#define  CEC_IER_TXUDRIE                     0x00000400U       /*!< CEC Tx-Buffer Underrun IT Enable       */
-#define  CEC_IER_TXERRIE                     0x00000800U       /*!< CEC Tx-Error IT Enable                 */
-#define  CEC_IER_TXACKEIE                    0x00001000U       /*!< CEC Tx Missing Acknowledge IT Enable   */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRC calculation unit                              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           0xFFFFFFFFU     /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         0x000000FFU     /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        0x00000001U     /*!< RESET the CRC computation unit bit */
-#define  CRC_CR_POLYSIZE                     0x00000018U     /*!< Polynomial size bits               */
-#define  CRC_CR_POLYSIZE_0                   0x00000008U     /*!< Polynomial size bit 0              */
-#define  CRC_CR_POLYSIZE_1                   0x00000010U     /*!< Polynomial size bit 1              */
-#define  CRC_CR_REV_IN                       0x00000060U     /*!< REV_IN Reverse Input Data bits     */
-#define  CRC_CR_REV_IN_0                     0x00000020U     /*!< Bit 0 */
-#define  CRC_CR_REV_IN_1                     0x00000040U     /*!< Bit 1 */
-#define  CRC_CR_REV_OUT                      0x00000080U     /*!< REV_OUT Reverse Output Data bits   */
-
-/*******************  Bit definition for CRC_INIT register  *******************/
-#define  CRC_INIT_INIT                       0xFFFFFFFFU     /*!< Initial CRC value bits         */
-
-/*******************  Bit definition for CRC_POL register  ********************/
-#define  CRC_POL_POL                         0xFFFFFFFFU     /*!< Coefficients of the polynomial */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Crypto Processor                                */
-/*                                                                            */
-/******************************************************************************/
-/******************* Bits definition for CRYP_CR register  ********************/
-#define CRYP_CR_ALGODIR                      0x00000004U
-
-#define CRYP_CR_ALGOMODE                     0x00080038U
-#define CRYP_CR_ALGOMODE_0                   0x00000008U
-#define CRYP_CR_ALGOMODE_1                   0x00000010U
-#define CRYP_CR_ALGOMODE_2                   0x00000020U
-#define CRYP_CR_ALGOMODE_TDES_ECB            0x00000000U
-#define CRYP_CR_ALGOMODE_TDES_CBC            0x00000008U
-#define CRYP_CR_ALGOMODE_DES_ECB             0x00000010U
-#define CRYP_CR_ALGOMODE_DES_CBC             0x00000018U
-#define CRYP_CR_ALGOMODE_AES_ECB             0x00000020U
-#define CRYP_CR_ALGOMODE_AES_CBC             0x00000028U
-#define CRYP_CR_ALGOMODE_AES_CTR             0x00000030U
-#define CRYP_CR_ALGOMODE_AES_KEY             0x00000038U
-
-#define CRYP_CR_DATATYPE                     0x000000C0U
-#define CRYP_CR_DATATYPE_0                   0x00000040U
-#define CRYP_CR_DATATYPE_1                   0x00000080U
-#define CRYP_CR_KEYSIZE                      0x00000300U
-#define CRYP_CR_KEYSIZE_0                    0x00000100U
-#define CRYP_CR_KEYSIZE_1                    0x00000200U
-#define CRYP_CR_FFLUSH                       0x00004000U
-#define CRYP_CR_CRYPEN                       0x00008000U
-
-#define CRYP_CR_GCM_CCMPH                    0x00030000U
-#define CRYP_CR_GCM_CCMPH_0                  0x00010000U
-#define CRYP_CR_GCM_CCMPH_1                  0x00020000U
-#define CRYP_CR_ALGOMODE_3                   0x00080000U
-
-/****************** Bits definition for CRYP_SR register  *********************/
-#define CRYP_SR_IFEM                         0x00000001U
-#define CRYP_SR_IFNF                         0x00000002U
-#define CRYP_SR_OFNE                         0x00000004U
-#define CRYP_SR_OFFU                         0x00000008U
-#define CRYP_SR_BUSY                         0x00000010U
-/****************** Bits definition for CRYP_DMACR register  ******************/
-#define CRYP_DMACR_DIEN                      0x00000001U
-#define CRYP_DMACR_DOEN                      0x00000002U
-/*****************  Bits definition for CRYP_IMSCR register  ******************/
-#define CRYP_IMSCR_INIM                      0x00000001U
-#define CRYP_IMSCR_OUTIM                     0x00000002U
-/****************** Bits definition for CRYP_RISR register  *******************/
-#define CRYP_RISR_OUTRIS                     0x00000001U
-#define CRYP_RISR_INRIS                      0x00000002U
-/****************** Bits definition for CRYP_MISR register  *******************/
-#define CRYP_MISR_INMIS                      0x00000001U
-#define CRYP_MISR_OUTMIS                     0x00000002U
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Digital to Analog Converter                           */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DAC_CR register  ********************/
-#define  DAC_CR_EN1                          0x00000001U        /*!<DAC channel1 enable                         */
-#define  DAC_CR_BOFF1                        0x00000002U        /*!<DAC channel1 output buffer disable          */
-#define  DAC_CR_TEN1                         0x00000004U        /*!<DAC channel1 Trigger enable                 */
-#define  DAC_CR_TSEL1                        0x00000038U        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define  DAC_CR_TSEL1_0                      0x00000008U        /*!<Bit 0 */
-#define  DAC_CR_TSEL1_1                      0x00000010U        /*!<Bit 1 */
-#define  DAC_CR_TSEL1_2                      0x00000020U        /*!<Bit 2 */
-#define  DAC_CR_WAVE1                        0x000000C0U        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enablEU) */
-#define  DAC_CR_WAVE1_0                      0x00000040U        /*!<Bit 0 */
-#define  DAC_CR_WAVE1_1                      0x00000080U        /*!<Bit 1 */
-#define  DAC_CR_MAMP1                        0x00000F00U        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP1_0                      0x00000100U        /*!<Bit 0 */
-#define  DAC_CR_MAMP1_1                      0x00000200U        /*!<Bit 1 */
-#define  DAC_CR_MAMP1_2                      0x00000400U        /*!<Bit 2 */
-#define  DAC_CR_MAMP1_3                      0x00000800U        /*!<Bit 3 */
-#define  DAC_CR_DMAEN1                       0x00001000U        /*!<DAC channel1 DMA enable                     */
-#define  DAC_CR_DMAUDRIE1                    0x00002000U        /*!<DAC channel1 DMA underrun interrupt enable  */
-#define  DAC_CR_EN2                          0x00010000U        /*!<DAC channel2 enable                         */
-#define  DAC_CR_BOFF2                        0x00020000U        /*!<DAC channel2 output buffer disable          */
-#define  DAC_CR_TEN2                         0x00040000U        /*!<DAC channel2 Trigger enable                 */
-#define  DAC_CR_TSEL2                        0x00380000U        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define  DAC_CR_TSEL2_0                      0x00080000U        /*!<Bit 0 */
-#define  DAC_CR_TSEL2_1                      0x00100000U        /*!<Bit 1 */
-#define  DAC_CR_TSEL2_2                      0x00200000U        /*!<Bit 2 */
-#define  DAC_CR_WAVE2                        0x00C00000U        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE2_0                      0x00400000U        /*!<Bit 0 */
-#define  DAC_CR_WAVE2_1                      0x00800000U        /*!<Bit 1 */
-#define  DAC_CR_MAMP2                        0x0F000000U        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP2_0                      0x01000000U        /*!<Bit 0 */
-#define  DAC_CR_MAMP2_1                      0x02000000U        /*!<Bit 1 */
-#define  DAC_CR_MAMP2_2                      0x04000000U        /*!<Bit 2 */
-#define  DAC_CR_MAMP2_3                      0x08000000U        /*!<Bit 3 */
-#define  DAC_CR_DMAEN2                       0x10000000U        /*!<DAC channel2 DMA enable                    */
-#define  DAC_CR_DMAUDRIE2                    0x20000000U        /*!<DAC channel2 DMA underrun interrupt enable */
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define  DAC_SWTRIGR_SWTRIG1                 0x01U               /*!<DAC channel1 software trigger */
-#define  DAC_SWTRIGR_SWTRIG2                 0x02U               /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define  DAC_DHR12R1_DACC1DHR                0x0FFFU            /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define  DAC_DHR12L1_DACC1DHR                0xFFF0U            /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define  DAC_DHR8R1_DACC1DHR                 0xFFU               /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define  DAC_DHR12R2_DACC2DHR                0x0FFFU            /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define  DAC_DHR12L2_DACC2DHR                0xFFF0U            /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define  DAC_DHR8R2_DACC2DHR                 0xFFU               /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define  DAC_DHR12RD_DACC1DHR                0x00000FFFU        /*!<DAC channel1 12-bit Right aligned data */
-#define  DAC_DHR12RD_DACC2DHR                0x0FFF0000U        /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define  DAC_DHR12LD_DACC1DHR                0x0000FFF0U        /*!<DAC channel1 12-bit Left aligned data */
-#define  DAC_DHR12LD_DACC2DHR                0xFFF00000U        /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define  DAC_DHR8RD_DACC1DHR                 0x00FFU            /*!<DAC channel1 8-bit Right aligned data */
-#define  DAC_DHR8RD_DACC2DHR                 0xFF00U            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define  DAC_DOR1_DACC1DOR                   0x0FFFU            /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define  DAC_DOR2_DACC2DOR                   0x0FFFU            /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define  DAC_SR_DMAUDR1                      0x00002000U        /*!<DAC channel1 DMA underrun flag */
-#define  DAC_SR_DMAUDR2                      0x20000000U        /*!<DAC channel2 DMA underrun flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 Debug MCU                                  */
-/*                                                                            */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    DCMI                                    */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DCMI_CR register  ******************/
-#define DCMI_CR_CAPTURE                      0x00000001U
-#define DCMI_CR_CM                           0x00000002U
-#define DCMI_CR_CROP                         0x00000004U
-#define DCMI_CR_JPEG                         0x00000008U
-#define DCMI_CR_ESS                          0x00000010U
-#define DCMI_CR_PCKPOL                       0x00000020U
-#define DCMI_CR_HSPOL                        0x00000040U
-#define DCMI_CR_VSPOL                        0x00000080U
-#define DCMI_CR_FCRC_0                       0x00000100U
-#define DCMI_CR_FCRC_1                       0x00000200U
-#define DCMI_CR_EDM_0                        0x00000400U
-#define DCMI_CR_EDM_1                        0x00000800U
-#define DCMI_CR_CRE                          0x00001000U
-#define DCMI_CR_ENABLE                       0x00004000U
-#define DCMI_CR_BSM                          0x00030000U
-#define DCMI_CR_BSM_0                        0x00010000U
-#define DCMI_CR_BSM_1                        0x00020000U
-#define DCMI_CR_OEBS                         0x00040000U
-#define DCMI_CR_LSM                          0x00080000U
-#define DCMI_CR_OELS                         0x00100000U
-
-/********************  Bits definition for DCMI_SR register  ******************/
-#define DCMI_SR_HSYNC                        0x00000001U
-#define DCMI_SR_VSYNC                        0x00000002U
-#define DCMI_SR_FNE                          0x00000004U
-
-/********************  Bits definition for DCMI_RIS register   ****************/
-#define DCMI_RIS_FRAME_RIS                   0x00000001U
-#define DCMI_RIS_OVR_RIS                     0x00000002U
-#define DCMI_RIS_ERR_RIS                     0x00000004U
-#define DCMI_RIS_VSYNC_RIS                   0x00000008U
-#define DCMI_RIS_LINE_RIS                    0x00000010U
-
-/* Legacy defines */
-#define DCMI_RISR_FRAME_RIS                  DCMI_RIS_FRAME_RIS
-#define DCMI_RISR_OVF_RIS                    DCMI_RIS_OVR_RIS
-#define DCMI_RISR_ERR_RIS                    DCMI_RIS_ERR_RIS
-#define DCMI_RISR_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS
-#define DCMI_RISR_LINE_RIS                   DCMI_RIS_LINE_RIS
-
-/********************  Bits definition for DCMI_IER register  *****************/
-#define DCMI_IER_FRAME_IE                    0x00000001U
-#define DCMI_IER_OVR_IE                      0x00000002U
-#define DCMI_IER_ERR_IE                      0x00000004U
-#define DCMI_IER_VSYNC_IE                    0x00000008U
-#define DCMI_IER_LINE_IE                     0x00000010U
-
-/* Legacy define */
-#define DCMI_IER_OVF_IE                      DCMI_IER_OVR_IE
-
-/********************  Bits definition for DCMI_MIS register  *****************/
-#define DCMI_MIS_FRAME_MIS                   0x00000001U
-#define DCMI_MIS_OVR_MIS                     0x00000002U
-#define DCMI_MIS_ERR_MIS                     0x00000004U
-#define DCMI_MIS_VSYNC_MIS                   0x00000008U
-#define DCMI_MIS_LINE_MIS                    0x00000010U
-
-/* Legacy defines */
-#define DCMI_MISR_FRAME_MIS                  DCMI_MIS_FRAME_MIS
-#define DCMI_MISR_OVF_MIS                    DCMI_MIS_OVR_MIS
-#define DCMI_MISR_ERR_MIS                    DCMI_MIS_ERR_MIS
-#define DCMI_MISR_VSYNC_MIS                  DCMI_MIS_VSYNC_MIS
-#define DCMI_MISR_LINE_MIS                   DCMI_MIS_LINE_MIS
-
-/********************  Bits definition for DCMI_ICR register  *****************/
-#define DCMI_ICR_FRAME_ISC                   0x00000001U
-#define DCMI_ICR_OVR_ISC                     0x00000002U
-#define DCMI_ICR_ERR_ISC                     0x00000004U
-#define DCMI_ICR_VSYNC_ISC                   0x00000008U
-#define DCMI_ICR_LINE_ISC                    0x00000010U
-
-/* Legacy defines */
-#define DCMI_ICR_OVF_ISC                     DCMI_ICR_OVR_ISC
-
-/********************  Bits definition for DCMI_ESCR register  ******************/
-#define DCMI_ESCR_FSC                        0x000000FFU
-#define DCMI_ESCR_LSC                        0x0000FF00U
-#define DCMI_ESCR_LEC                        0x00FF0000U
-#define DCMI_ESCR_FEC                        0xFF000000U
-
-/********************  Bits definition for DCMI_ESUR register  ******************/
-#define DCMI_ESUR_FSU                        0x000000FFU
-#define DCMI_ESUR_LSU                        0x0000FF00U
-#define DCMI_ESUR_LEU                        0x00FF0000U
-#define DCMI_ESUR_FEU                        0xFF000000U
-
-/********************  Bits definition for DCMI_CWSTRT register  ******************/
-#define DCMI_CWSTRT_HOFFCNT                  0x00003FFFU
-#define DCMI_CWSTRT_VST                      0x1FFF0000U
-
-/********************  Bits definition for DCMI_CWSIZE register  ******************/
-#define DCMI_CWSIZE_CAPCNT                   0x00003FFFU
-#define DCMI_CWSIZE_VLINE                    0x3FFF0000U
-
-/********************  Bits definition for DCMI_DR register  ******************/
-#define DCMI_DR_BYTE0                        0x000000FFU
-#define DCMI_DR_BYTE1                        0x0000FF00U
-#define DCMI_DR_BYTE2                        0x00FF0000U
-#define DCMI_DR_BYTE3                        0xFF000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                             DMA Controller                                 */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DMA_SxCR register  *****************/
-#define DMA_SxCR_CHSEL                       0x0E000000U
-#define DMA_SxCR_CHSEL_0                     0x02000000U
-#define DMA_SxCR_CHSEL_1                     0x04000000U
-#define DMA_SxCR_CHSEL_2                     0x08000000U
-#define DMA_SxCR_MBURST                      0x01800000U
-#define DMA_SxCR_MBURST_0                    0x00800000U
-#define DMA_SxCR_MBURST_1                    0x01000000U
-#define DMA_SxCR_PBURST                      0x00600000U
-#define DMA_SxCR_PBURST_0                    0x00200000U
-#define DMA_SxCR_PBURST_1                    0x00400000U
-#define DMA_SxCR_CT                          0x00080000U
-#define DMA_SxCR_DBM                         0x00040000U
-#define DMA_SxCR_PL                          0x00030000U
-#define DMA_SxCR_PL_0                        0x00010000U
-#define DMA_SxCR_PL_1                        0x00020000U
-#define DMA_SxCR_PINCOS                      0x00008000U
-#define DMA_SxCR_MSIZE                       0x00006000U
-#define DMA_SxCR_MSIZE_0                     0x00002000U
-#define DMA_SxCR_MSIZE_1                     0x00004000U
-#define DMA_SxCR_PSIZE                       0x00001800U
-#define DMA_SxCR_PSIZE_0                     0x00000800U
-#define DMA_SxCR_PSIZE_1                     0x00001000U
-#define DMA_SxCR_MINC                        0x00000400U
-#define DMA_SxCR_PINC                        0x00000200U
-#define DMA_SxCR_CIRC                        0x00000100U
-#define DMA_SxCR_DIR                         0x000000C0U
-#define DMA_SxCR_DIR_0                       0x00000040U
-#define DMA_SxCR_DIR_1                       0x00000080U
-#define DMA_SxCR_PFCTRL                      0x00000020U
-#define DMA_SxCR_TCIE                        0x00000010U
-#define DMA_SxCR_HTIE                        0x00000008U
-#define DMA_SxCR_TEIE                        0x00000004U
-#define DMA_SxCR_DMEIE                       0x00000002U
-#define DMA_SxCR_EN                          0x00000001U
-
-/********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            0x0000FFFFU
-#define DMA_SxNDT_0                          0x00000001U
-#define DMA_SxNDT_1                          0x00000002U
-#define DMA_SxNDT_2                          0x00000004U
-#define DMA_SxNDT_3                          0x00000008U
-#define DMA_SxNDT_4                          0x00000010U
-#define DMA_SxNDT_5                          0x00000020U
-#define DMA_SxNDT_6                          0x00000040U
-#define DMA_SxNDT_7                          0x00000080U
-#define DMA_SxNDT_8                          0x00000100U
-#define DMA_SxNDT_9                          0x00000200U
-#define DMA_SxNDT_10                         0x00000400U
-#define DMA_SxNDT_11                         0x00000800U
-#define DMA_SxNDT_12                         0x00001000U
-#define DMA_SxNDT_13                         0x00002000U
-#define DMA_SxNDT_14                         0x00004000U
-#define DMA_SxNDT_15                         0x00008000U
-
-/********************  Bits definition for DMA_SxFCR register  ****************/
-#define DMA_SxFCR_FEIE                       0x00000080U
-#define DMA_SxFCR_FS                         0x00000038U
-#define DMA_SxFCR_FS_0                       0x00000008U
-#define DMA_SxFCR_FS_1                       0x00000010U
-#define DMA_SxFCR_FS_2                       0x00000020U
-#define DMA_SxFCR_DMDIS                      0x00000004U
-#define DMA_SxFCR_FTH                        0x00000003U
-#define DMA_SxFCR_FTH_0                      0x00000001U
-#define DMA_SxFCR_FTH_1                      0x00000002U
-
-/********************  Bits definition for DMA_LISR register  *****************/
-#define DMA_LISR_TCIF3                       0x08000000U
-#define DMA_LISR_HTIF3                       0x04000000U
-#define DMA_LISR_TEIF3                       0x02000000U
-#define DMA_LISR_DMEIF3                      0x01000000U
-#define DMA_LISR_FEIF3                       0x00400000U
-#define DMA_LISR_TCIF2                       0x00200000U
-#define DMA_LISR_HTIF2                       0x00100000U
-#define DMA_LISR_TEIF2                       0x00080000U
-#define DMA_LISR_DMEIF2                      0x00040000U
-#define DMA_LISR_FEIF2                       0x00010000U
-#define DMA_LISR_TCIF1                       0x00000800U
-#define DMA_LISR_HTIF1                       0x00000400U
-#define DMA_LISR_TEIF1                       0x00000200U
-#define DMA_LISR_DMEIF1                      0x00000100U
-#define DMA_LISR_FEIF1                       0x00000040U
-#define DMA_LISR_TCIF0                       0x00000020U
-#define DMA_LISR_HTIF0                       0x00000010U
-#define DMA_LISR_TEIF0                       0x00000008U
-#define DMA_LISR_DMEIF0                      0x00000004U
-#define DMA_LISR_FEIF0                       0x00000001U
-
-/********************  Bits definition for DMA_HISR register  *****************/
-#define DMA_HISR_TCIF7                       0x08000000U
-#define DMA_HISR_HTIF7                       0x04000000U
-#define DMA_HISR_TEIF7                       0x02000000U
-#define DMA_HISR_DMEIF7                      0x01000000U
-#define DMA_HISR_FEIF7                       0x00400000U
-#define DMA_HISR_TCIF6                       0x00200000U
-#define DMA_HISR_HTIF6                       0x00100000U
-#define DMA_HISR_TEIF6                       0x00080000U
-#define DMA_HISR_DMEIF6                      0x00040000U
-#define DMA_HISR_FEIF6                       0x00010000U
-#define DMA_HISR_TCIF5                       0x00000800U
-#define DMA_HISR_HTIF5                       0x00000400U
-#define DMA_HISR_TEIF5                       0x00000200U
-#define DMA_HISR_DMEIF5                      0x00000100U
-#define DMA_HISR_FEIF5                       0x00000040U
-#define DMA_HISR_TCIF4                       0x00000020U
-#define DMA_HISR_HTIF4                       0x00000010U
-#define DMA_HISR_TEIF4                       0x00000008U
-#define DMA_HISR_DMEIF4                      0x00000004U
-#define DMA_HISR_FEIF4                       0x00000001U
-
-/********************  Bits definition for DMA_LIFCR register  ****************/
-#define DMA_LIFCR_CTCIF3                     0x08000000U
-#define DMA_LIFCR_CHTIF3                     0x04000000U
-#define DMA_LIFCR_CTEIF3                     0x02000000U
-#define DMA_LIFCR_CDMEIF3                    0x01000000U
-#define DMA_LIFCR_CFEIF3                     0x00400000U
-#define DMA_LIFCR_CTCIF2                     0x00200000U
-#define DMA_LIFCR_CHTIF2                     0x00100000U
-#define DMA_LIFCR_CTEIF2                     0x00080000U
-#define DMA_LIFCR_CDMEIF2                    0x00040000U
-#define DMA_LIFCR_CFEIF2                     0x00010000U
-#define DMA_LIFCR_CTCIF1                     0x00000800U
-#define DMA_LIFCR_CHTIF1                     0x00000400U
-#define DMA_LIFCR_CTEIF1                     0x00000200U
-#define DMA_LIFCR_CDMEIF1                    0x00000100U
-#define DMA_LIFCR_CFEIF1                     0x00000040U
-#define DMA_LIFCR_CTCIF0                     0x00000020U
-#define DMA_LIFCR_CHTIF0                     0x00000010U
-#define DMA_LIFCR_CTEIF0                     0x00000008U
-#define DMA_LIFCR_CDMEIF0                    0x00000004U
-#define DMA_LIFCR_CFEIF0                     0x00000001U
-
-/********************  Bits definition for DMA_HIFCR  register  ****************/
-#define DMA_HIFCR_CTCIF7                     0x08000000U
-#define DMA_HIFCR_CHTIF7                     0x04000000U
-#define DMA_HIFCR_CTEIF7                     0x02000000U
-#define DMA_HIFCR_CDMEIF7                    0x01000000U
-#define DMA_HIFCR_CFEIF7                     0x00400000U
-#define DMA_HIFCR_CTCIF6                     0x00200000U
-#define DMA_HIFCR_CHTIF6                     0x00100000U
-#define DMA_HIFCR_CTEIF6                     0x00080000U
-#define DMA_HIFCR_CDMEIF6                    0x00040000U
-#define DMA_HIFCR_CFEIF6                     0x00010000U
-#define DMA_HIFCR_CTCIF5                     0x00000800U
-#define DMA_HIFCR_CHTIF5                     0x00000400U
-#define DMA_HIFCR_CTEIF5                     0x00000200U
-#define DMA_HIFCR_CDMEIF5                    0x00000100U
-#define DMA_HIFCR_CFEIF5                     0x00000040U
-#define DMA_HIFCR_CTCIF4                     0x00000020U
-#define DMA_HIFCR_CHTIF4                     0x00000010U
-#define DMA_HIFCR_CTEIF4                     0x00000008U
-#define DMA_HIFCR_CDMEIF4                    0x00000004U
-#define DMA_HIFCR_CFEIF4                     0x00000001U
-
-/******************************************************************************/
-/*                                                                            */
-/*                         AHB Master DMA2D Controller (DMA2D)                */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for DMA2D_CR register  ******************/
-
-#define DMA2D_CR_START                     0x00000001U               /*!< Start transfer                          */
-#define DMA2D_CR_SUSP                      0x00000002U               /*!< Suspend transfer                        */
-#define DMA2D_CR_ABORT                     0x00000004U               /*!< Abort transfer                          */
-#define DMA2D_CR_TEIE                      0x00000100U               /*!< Transfer Error Interrupt Enable         */
-#define DMA2D_CR_TCIE                      0x00000200U               /*!< Transfer Complete Interrupt Enable      */
-#define DMA2D_CR_TWIE                      0x00000400U               /*!< Transfer Watermark Interrupt Enable     */
-#define DMA2D_CR_CAEIE                     0x00000800U               /*!< CLUT Access Error Interrupt Enable      */
-#define DMA2D_CR_CTCIE                     0x00001000U               /*!< CLUT Transfer Complete Interrupt Enable */
-#define DMA2D_CR_CEIE                      0x00002000U               /*!< Configuration Error Interrupt Enable    */
-#define DMA2D_CR_MODE                      0x00030000U               /*!< DMA2D Mode[1:0]                         */
-#define DMA2D_CR_MODE_0                    0x00010000U               /*!< DMA2D Mode bit 0                        */
-#define DMA2D_CR_MODE_1                    0x00020000U               /*!< DMA2D Mode bit 1                        */
-
-/********************  Bit definition for DMA2D_ISR register  *****************/
-
-#define DMA2D_ISR_TEIF                     0x00000001U               /*!< Transfer Error Interrupt Flag         */
-#define DMA2D_ISR_TCIF                     0x00000002U               /*!< Transfer Complete Interrupt Flag      */
-#define DMA2D_ISR_TWIF                     0x00000004U               /*!< Transfer Watermark Interrupt Flag     */
-#define DMA2D_ISR_CAEIF                    0x00000008U               /*!< CLUT Access Error Interrupt Flag      */
-#define DMA2D_ISR_CTCIF                    0x00000010U               /*!< CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_ISR_CEIF                     0x00000020U               /*!< Configuration Error Interrupt Flag    */
-
-/********************  Bit definition for DMA2D_IFCR register  ****************/
-
-#define DMA2D_IFCR_CTEIF                   0x00000001U               /*!< Clears Transfer Error Interrupt Flag         */
-#define DMA2D_IFCR_CTCIF                   0x00000002U               /*!< Clears Transfer Complete Interrupt Flag      */
-#define DMA2D_IFCR_CTWIF                   0x00000004U               /*!< Clears Transfer Watermark Interrupt Flag     */
-#define DMA2D_IFCR_CAECIF                  0x00000008U               /*!< Clears CLUT Access Error Interrupt Flag      */
-#define DMA2D_IFCR_CCTCIF                  0x00000010U               /*!< Clears CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_IFCR_CCEIF                   0x00000020U               /*!< Clears Configuration Error Interrupt Flag    */
-
-/* Legacy defines */
-#define DMA2D_IFSR_CTEIF                   DMA2D_IFCR_CTEIF                     /*!< Clears Transfer Error Interrupt Flag         */
-#define DMA2D_IFSR_CTCIF                   DMA2D_IFCR_CTCIF                     /*!< Clears Transfer Complete Interrupt Flag      */
-#define DMA2D_IFSR_CTWIF                   DMA2D_IFCR_CTWIF                     /*!< Clears Transfer Watermark Interrupt Flag     */
-#define DMA2D_IFSR_CCAEIF                  DMA2D_IFCR_CAECIF                    /*!< Clears CLUT Access Error Interrupt Flag      */
-#define DMA2D_IFSR_CCTCIF                  DMA2D_IFCR_CCTCIF                    /*!< Clears CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_IFSR_CCEIF                   DMA2D_IFCR_CCEIF                     /*!< Clears Configuration Error Interrupt Flag    */
-
-/********************  Bit definition for DMA2D_FGMAR register  ***************/
-
-#define DMA2D_FGMAR_MA                     0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_FGOR register  ****************/
-
-#define DMA2D_FGOR_LO                      0x00003FFFU               /*!< Line Offset */
-
-/********************  Bit definition for DMA2D_BGMAR register  ***************/
-
-#define DMA2D_BGMAR_MA                     0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_BGOR register  ****************/
-
-#define DMA2D_BGOR_LO                      0x00003FFFU               /*!< Line Offset */
-
-/********************  Bit definition for DMA2D_FGPFCCR register  *************/
-
-#define DMA2D_FGPFCCR_CM                   0x0000000FU               /*!< Input color mode CM[3:0] */
-#define DMA2D_FGPFCCR_CM_0                 0x00000001U               /*!< Input color mode CM bit 0 */
-#define DMA2D_FGPFCCR_CM_1                 0x00000002U               /*!< Input color mode CM bit 1 */
-#define DMA2D_FGPFCCR_CM_2                 0x00000004U               /*!< Input color mode CM bit 2 */
-#define DMA2D_FGPFCCR_CM_3                 0x00000008U               /*!< Input color mode CM bit 3 */
-#define DMA2D_FGPFCCR_CCM                  0x00000010U               /*!< CLUT Color mode */
-#define DMA2D_FGPFCCR_START                0x00000020U               /*!< Start */
-#define DMA2D_FGPFCCR_CS                   0x0000FF00U               /*!< CLUT size */
-#define DMA2D_FGPFCCR_AM                   0x00030000U               /*!< Alpha mode AM[1:0] */
-#define DMA2D_FGPFCCR_AM_0                 0x00010000U               /*!< Alpha mode AM bit 0 */
-#define DMA2D_FGPFCCR_AM_1                 0x00020000U               /*!< Alpha mode AM bit 1 */
-#define DMA2D_FGPFCCR_ALPHA                0xFF000000U               /*!< Alpha value */
-
-/********************  Bit definition for DMA2D_FGCOLR register  **************/
-
-#define DMA2D_FGCOLR_BLUE                  0x000000FFU               /*!< Blue Value */
-#define DMA2D_FGCOLR_GREEN                 0x0000FF00U               /*!< Green Value */
-#define DMA2D_FGCOLR_RED                   0x00FF0000U               /*!< Red Value */
-
-/********************  Bit definition for DMA2D_BGPFCCR register  *************/
-
-#define DMA2D_BGPFCCR_CM                   0x0000000FU               /*!< Input color mode CM[3:0] */
-#define DMA2D_BGPFCCR_CM_0                 0x00000001U               /*!< Input color mode CM bit 0 */
-#define DMA2D_BGPFCCR_CM_1                 0x00000002U               /*!< Input color mode CM bit 1 */
-#define DMA2D_BGPFCCR_CM_2                 0x00000004U               /*!< Input color mode CM bit 2 */
-#define DMA2D_FGPFCCR_CM_3                 0x00000008U               /*!< Input color mode CM bit 3 */
-#define DMA2D_BGPFCCR_CCM                  0x00000010U               /*!< CLUT Color mode */
-#define DMA2D_BGPFCCR_START                0x00000020U               /*!< Start */
-#define DMA2D_BGPFCCR_CS                   0x0000FF00U               /*!< CLUT size */
-#define DMA2D_BGPFCCR_AM                   0x00030000U               /*!< Alpha mode AM[1:0] */
-#define DMA2D_BGPFCCR_AM_0                 0x00010000U               /*!< Alpha mode AM bit 0 */
-#define DMA2D_BGPFCCR_AM_1                 0x00020000U               /*!< Alpha mode AM bit 1 */
-#define DMA2D_BGPFCCR_ALPHA                0xFF000000U               /*!< background Input Alpha value */
-
-/********************  Bit definition for DMA2D_BGCOLR register  **************/
-
-#define DMA2D_BGCOLR_BLUE                  0x000000FFU               /*!< Blue Value */
-#define DMA2D_BGCOLR_GREEN                 0x0000FF00U               /*!< Green Value */
-#define DMA2D_BGCOLR_RED                   0x00FF0000U               /*!< Red Value */
-
-/********************  Bit definition for DMA2D_FGCMAR register  **************/
-
-#define DMA2D_FGCMAR_MA                    0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_BGCMAR register  **************/
-
-#define DMA2D_BGCMAR_MA                    0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_OPFCCR register  **************/
-
-#define DMA2D_OPFCCR_CM                    0x00000007U               /*!< Color mode CM[2:0] */
-#define DMA2D_OPFCCR_CM_0                  0x00000001U               /*!< Color mode CM bit 0 */
-#define DMA2D_OPFCCR_CM_1                  0x00000002U               /*!< Color mode CM bit 1 */
-#define DMA2D_OPFCCR_CM_2                  0x00000004U               /*!< Color mode CM bit 2 */
-
-/********************  Bit definition for DMA2D_OCOLR register  ***************/
-
-/*!<Mode_ARGB8888/RGB888 */
-
-#define DMA2D_OCOLR_BLUE_1                 0x000000FFU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_1                0x0000FF00U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_1                  0x00FF0000U               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_1                0xFF000000U               /*!< Alpha Channel Value */
-
-/*!<Mode_RGB565 */
-#define DMA2D_OCOLR_BLUE_2                 0x0000001FU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_2                0x000007E0U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_2                  0x0000F800U               /*!< Red Value */
-
-/*!<Mode_ARGB1555 */
-#define DMA2D_OCOLR_BLUE_3                 0x0000001FU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_3                0x000003E0U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_3                  0x00007C00U               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_3                0x00008000U               /*!< Alpha Channel Value */
-
-/*!<Mode_ARGB4444 */
-#define DMA2D_OCOLR_BLUE_4                 0x0000000FU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_4                0x000000F0U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_4                  0x00000F00U               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_4                0x0000F000U               /*!< Alpha Channel Value */
-
-/********************  Bit definition for DMA2D_OMAR register  ****************/
-
-#define DMA2D_OMAR_MA                      0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_OOR register  *****************/
-
-#define DMA2D_OOR_LO                       0x00003FFFU               /*!< Line Offset */
-
-/********************  Bit definition for DMA2D_NLR register  *****************/
-
-#define DMA2D_NLR_NL                       0x0000FFFFU               /*!< Number of Lines */
-#define DMA2D_NLR_PL                       0x3FFF0000U               /*!< Pixel per Lines */
-
-/********************  Bit definition for DMA2D_LWR register  *****************/
-
-#define DMA2D_LWR_LW                       0x0000FFFFU               /*!< Line Watermark */
-
-/********************  Bit definition for DMA2D_AMTCR register  ***************/
-
-#define DMA2D_AMTCR_EN                     0x00000001U               /*!< Enable */
-#define DMA2D_AMTCR_DT                     0x0000FF00U               /*!< Dead Time */
-
-
-/********************  Bit definition for DMA2D_FGCLUT register  **************/
-
-/********************  Bit definition for DMA2D_BGCLUT register  **************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                    External Interrupt/Event Controller                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
-#define  EXTI_IMR_MR23                       0x00800000U        /*!< Interrupt Mask on line 23 */
-
-/* Reference Defines */
-#define  EXTI_IMR_IM0                        EXTI_IMR_MR0
-#define  EXTI_IMR_IM1                        EXTI_IMR_MR1
-#define  EXTI_IMR_IM2                        EXTI_IMR_MR2
-#define  EXTI_IMR_IM3                        EXTI_IMR_MR3
-#define  EXTI_IMR_IM4                        EXTI_IMR_MR4
-#define  EXTI_IMR_IM5                        EXTI_IMR_MR5
-#define  EXTI_IMR_IM6                        EXTI_IMR_MR6
-#define  EXTI_IMR_IM7                        EXTI_IMR_MR7
-#define  EXTI_IMR_IM8                        EXTI_IMR_MR8
-#define  EXTI_IMR_IM9                        EXTI_IMR_MR9
-#define  EXTI_IMR_IM10                       EXTI_IMR_MR10
-#define  EXTI_IMR_IM11                       EXTI_IMR_MR11
-#define  EXTI_IMR_IM12                       EXTI_IMR_MR12
-#define  EXTI_IMR_IM13                       EXTI_IMR_MR13
-#define  EXTI_IMR_IM14                       EXTI_IMR_MR14
-#define  EXTI_IMR_IM15                       EXTI_IMR_MR15
-#define  EXTI_IMR_IM16                       EXTI_IMR_MR16
-#define  EXTI_IMR_IM17                       EXTI_IMR_MR17
-#define  EXTI_IMR_IM18                       EXTI_IMR_MR18
-#define  EXTI_IMR_IM19                       EXTI_IMR_MR19
-#define  EXTI_IMR_IM20                       EXTI_IMR_MR20
-#define  EXTI_IMR_IM21                       EXTI_IMR_MR21
-#define  EXTI_IMR_IM22                       EXTI_IMR_MR22
-#define  EXTI_IMR_IM23                       EXTI_IMR_MR23
-
-#define  EXTI_IMR_IM                         0x00FFFFFFU        /*!< Interrupt Mask All */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
-#define  EXTI_EMR_MR23                       0x00800000U        /*!< Event Mask on line 23 */
-
-/* Reference Defines */
-#define  EXTI_EMR_EM0                        EXTI_EMR_MR0
-#define  EXTI_EMR_EM1                        EXTI_EMR_MR1
-#define  EXTI_EMR_EM2                        EXTI_EMR_MR2
-#define  EXTI_EMR_EM3                        EXTI_EMR_MR3
-#define  EXTI_EMR_EM4                        EXTI_EMR_MR4
-#define  EXTI_EMR_EM5                        EXTI_EMR_MR5
-#define  EXTI_EMR_EM6                        EXTI_EMR_MR6
-#define  EXTI_EMR_EM7                        EXTI_EMR_MR7
-#define  EXTI_EMR_EM8                        EXTI_EMR_MR8
-#define  EXTI_EMR_EM9                        EXTI_EMR_MR9
-#define  EXTI_EMR_EM10                       EXTI_EMR_MR10
-#define  EXTI_EMR_EM11                       EXTI_EMR_MR11
-#define  EXTI_EMR_EM12                       EXTI_EMR_MR12
-#define  EXTI_EMR_EM13                       EXTI_EMR_MR13
-#define  EXTI_EMR_EM14                       EXTI_EMR_MR14
-#define  EXTI_EMR_EM15                       EXTI_EMR_MR15
-#define  EXTI_EMR_EM16                       EXTI_EMR_MR16
-#define  EXTI_EMR_EM17                       EXTI_EMR_MR17
-#define  EXTI_EMR_EM18                       EXTI_EMR_MR18
-#define  EXTI_EMR_EM19                       EXTI_EMR_MR19
-#define  EXTI_EMR_EM20                       EXTI_EMR_MR20
-#define  EXTI_EMR_EM21                       EXTI_EMR_MR21
-#define  EXTI_EMR_EM22                       EXTI_EMR_MR22
-#define  EXTI_EMR_EM23                       EXTI_EMR_MR23
-
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
-#define  EXTI_RTSR_TR23                      0x00800000U        /*!< Rising trigger event configuration bit of line 23 */
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
-#define  EXTI_FTSR_TR23                      0x00800000U        /*!< Falling trigger event configuration bit of line 23 */
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
-#define  EXTI_SWIER_SWIER23                  0x00800000U        /*!< Software Interrupt on line 23 */
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
-#define  EXTI_PR_PR23                        0x00800000U        /*!< Pending bit for line 23 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    FLASH                                   */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief FLASH Total Sectors Number
-*/
-#define FLASH_SECTOR_TOTAL  8
-
-/*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    0x0000000FU
-#define FLASH_ACR_LATENCY_0WS                0x00000000U
-#define FLASH_ACR_LATENCY_1WS                0x00000001U
-#define FLASH_ACR_LATENCY_2WS                0x00000002U
-#define FLASH_ACR_LATENCY_3WS                0x00000003U
-#define FLASH_ACR_LATENCY_4WS                0x00000004U
-#define FLASH_ACR_LATENCY_5WS                0x00000005U
-#define FLASH_ACR_LATENCY_6WS                0x00000006U
-#define FLASH_ACR_LATENCY_7WS                0x00000007U
-#define FLASH_ACR_LATENCY_8WS                0x00000008U
-#define FLASH_ACR_LATENCY_9WS                0x00000009U
-#define FLASH_ACR_LATENCY_10WS               0x0000000AU
-#define FLASH_ACR_LATENCY_11WS               0x0000000BU
-#define FLASH_ACR_LATENCY_12WS               0x0000000CU
-#define FLASH_ACR_LATENCY_13WS               0x0000000DU
-#define FLASH_ACR_LATENCY_14WS               0x0000000EU
-#define FLASH_ACR_LATENCY_15WS               0x0000000FU
-#define FLASH_ACR_PRFTEN                     0x00000100U
-#define FLASH_ACR_ARTEN                      0x00000200U
-#define FLASH_ACR_ARTRST                     0x00000800U
-
-/*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         0x00000001U
-#define FLASH_SR_OPERR                       0x00000002U
-#define FLASH_SR_WRPERR                      0x00000010U
-#define FLASH_SR_PGAERR                      0x00000020U
-#define FLASH_SR_PGPERR                      0x00000040U
-#define FLASH_SR_ERSERR                      0x00000080U
-#define FLASH_SR_BSY                         0x00010000U
-
-/*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          0x00000001U
-#define FLASH_CR_SER                         0x00000002U
-#define FLASH_CR_MER                         0x00000004U
-#define FLASH_CR_SNB                         0x00000078U
-#define FLASH_CR_SNB_0                       0x00000008U
-#define FLASH_CR_SNB_1                       0x00000010U
-#define FLASH_CR_SNB_2                       0x00000020U
-#define FLASH_CR_SNB_3                       0x00000040U
-#define FLASH_CR_PSIZE                       0x00000300U
-#define FLASH_CR_PSIZE_0                     0x00000100U
-#define FLASH_CR_PSIZE_1                     0x00000200U
-#define FLASH_CR_STRT                        0x00010000U
-#define FLASH_CR_EOPIE                       0x01000000U
-#define FLASH_CR_ERRIE                       0x02000000U
-#define FLASH_CR_LOCK                        0x80000000U
-
-/*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                 0x00000001U
-#define FLASH_OPTCR_OPTSTRT                 0x00000002U
-#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
-#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
-#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
-#define FLASH_OPTCR_WWDG_SW                 0x00000010U
-#define FLASH_OPTCR_IWDG_SW                 0x00000020U
-#define FLASH_OPTCR_nRST_STOP               0x00000040U
-#define FLASH_OPTCR_nRST_STDBY              0x00000080U
-#define FLASH_OPTCR_RDP                     0x0000FF00U
-#define FLASH_OPTCR_RDP_0                   0x00000100U
-#define FLASH_OPTCR_RDP_1                   0x00000200U
-#define FLASH_OPTCR_RDP_2                   0x00000400U
-#define FLASH_OPTCR_RDP_3                   0x00000800U
-#define FLASH_OPTCR_RDP_4                   0x00001000U
-#define FLASH_OPTCR_RDP_5                   0x00002000U
-#define FLASH_OPTCR_RDP_6                   0x00004000U
-#define FLASH_OPTCR_RDP_7                   0x00008000U
-#define FLASH_OPTCR_nWRP                    0x00FF0000U
-#define FLASH_OPTCR_nWRP_0                  0x00010000U
-#define FLASH_OPTCR_nWRP_1                  0x00020000U
-#define FLASH_OPTCR_nWRP_2                  0x00040000U
-#define FLASH_OPTCR_nWRP_3                  0x00080000U
-#define FLASH_OPTCR_nWRP_4                  0x00100000U
-#define FLASH_OPTCR_nWRP_5                  0x00200000U
-#define FLASH_OPTCR_nWRP_6                  0x00400000U
-#define FLASH_OPTCR_nWRP_7                  0x00800000U
-#define FLASH_OPTCR_IWDG_STDBY              0x40000000U
-#define FLASH_OPTCR_IWDG_STOP               0x80000000U
-
-/*******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_BOOT_ADD0              0x0000FFFFU
-#define FLASH_OPTCR1_BOOT_ADD1              0xFFFF0000U
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Flexible Memory Controller                        */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for FMC_BCR1 register  *******************/
-#define  FMC_BCR1_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR1_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-#define  FMC_BCR1_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR1_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR1_MTYP_1                    0x00000008U        /*!<Bit 1 */
-#define  FMC_BCR1_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR1_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR1_MWID_1                    0x00000020U        /*!<Bit 1 */
-#define  FMC_BCR1_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR1_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR1_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR1_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
-#define  FMC_BCR1_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR1_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR1_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR1_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR1_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR1_CPSIZE                    0x00070000U        /*!<CRAM page size             */
-#define  FMC_BCR1_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FMC_BCR1_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FMC_BCR1_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FMC_BCR1_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-#define  FMC_BCR1_CCLKEN                    0x00100000U        /*!<Continous clock enable     */
-#define  FMC_BCR1_WFDIS                     0x00200000U        /*!<Write FIFO Disable         */
-
-/******************  Bit definition for FMC_BCR2 register  *******************/
-#define  FMC_BCR2_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR2_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-#define  FMC_BCR2_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR2_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR2_MTYP_1                    0x00000008U        /*!<Bit 1 */
-#define  FMC_BCR2_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR2_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR2_MWID_1                    0x00000020U        /*!<Bit 1 */
-#define  FMC_BCR2_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR2_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR2_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR2_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
-#define  FMC_BCR2_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR2_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR2_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR2_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR2_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR2_CPSIZE                    0x00070000U        /*!<CRAM page size             */
-#define  FMC_BCR2_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FMC_BCR2_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FMC_BCR2_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FMC_BCR2_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FMC_BCR3 register  *******************/
-#define  FMC_BCR3_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR3_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-#define  FMC_BCR3_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR3_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR3_MTYP_1                    0x00000008U        /*!<Bit 1 */
-#define  FMC_BCR3_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR3_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR3_MWID_1                    0x00000020U        /*!<Bit 1 */
-#define  FMC_BCR3_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR3_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR3_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR3_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
-#define  FMC_BCR3_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR3_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR3_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR3_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR3_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR3_CPSIZE                    0x00070000U        /*!<CRAM page size             */
-#define  FMC_BCR3_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FMC_BCR3_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FMC_BCR3_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FMC_BCR3_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FMC_BCR4 register  *******************/
-#define  FMC_BCR4_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR4_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-#define  FMC_BCR4_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR4_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR4_MTYP_1                    0x00000008U        /*!<Bit 1 */
-#define  FMC_BCR4_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR4_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR4_MWID_1                    0x00000020U        /*!<Bit 1 */
-#define  FMC_BCR4_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR4_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR4_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR4_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
-#define  FMC_BCR4_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR4_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR4_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR4_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR4_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR4_CPSIZE                    0x00070000U        /*!<CRAM page size             */
-#define  FMC_BCR4_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FMC_BCR4_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FMC_BCR4_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FMC_BCR4_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FMC_BTR1 register  ******************/
-#define  FMC_BTR1_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR1_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR1_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR1_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR1_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-#define  FMC_BTR1_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
-#define  FMC_BTR1_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR1_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR1_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR1_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-#define  FMC_BTR1_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR1_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR1_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR1_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR1_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR1_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR1_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR1_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR1_DATAST_7                  0x00008000U        /*!<Bit 7 */
-#define  FMC_BTR1_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR1_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR1_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR1_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR1_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-#define  FMC_BTR1_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR1_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR1_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR1_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR1_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-#define  FMC_BTR1_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR1_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR1_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR1_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR1_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-#define  FMC_BTR1_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR1_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR1_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BTR2 register  *******************/
-#define  FMC_BTR2_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR2_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR2_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR2_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR2_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-#define  FMC_BTR2_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR2_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR2_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR2_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR2_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-#define  FMC_BTR2_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR2_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR2_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR2_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR2_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR2_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR2_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR2_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR2_DATAST_7                  0x00008000U        /*!<Bit 7 */
-#define  FMC_BTR2_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR2_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR2_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR2_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR2_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-#define  FMC_BTR2_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR2_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR2_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR2_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR2_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-#define  FMC_BTR2_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR2_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR2_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR2_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR2_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-#define  FMC_BTR2_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR2_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR2_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/*******************  Bit definition for FMC_BTR3 register  *******************/
-#define  FMC_BTR3_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR3_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR3_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR3_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR3_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-#define  FMC_BTR3_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR3_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR3_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR3_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR3_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-#define  FMC_BTR3_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR3_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR3_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR3_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR3_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR3_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR3_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR3_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR3_DATAST_7                  0x00008000U        /*!<Bit 7 */
-#define  FMC_BTR3_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR3_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR3_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR3_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR3_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-#define  FMC_BTR3_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR3_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR3_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR3_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR3_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-#define  FMC_BTR3_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR3_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR3_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR3_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR3_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-#define  FMC_BTR3_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR3_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR3_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BTR4 register  *******************/
-#define  FMC_BTR4_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR4_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR4_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR4_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR4_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-#define  FMC_BTR4_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR4_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR4_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR4_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR4_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-#define  FMC_BTR4_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR4_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR4_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR4_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR4_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR4_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR4_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR4_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR4_DATAST_7                  0x00008000U        /*!<Bit 7 */
-#define  FMC_BTR4_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR4_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR4_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR4_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR4_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-#define  FMC_BTR4_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR4_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR4_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR4_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR4_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-#define  FMC_BTR4_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR4_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR4_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR4_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR4_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-#define  FMC_BTR4_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR4_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR4_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR1 register  ******************/
-#define  FMC_BWTR1_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR1_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR1_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR1_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR1_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-#define  FMC_BWTR1_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR1_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR1_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR1_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR1_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-#define  FMC_BWTR1_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR1_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR1_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR1_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR1_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR1_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR1_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR1_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR1_DATAST_7                 0x00008000U        /*!<Bit 7 */
-#define  FMC_BWTR1_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BWTR1_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR1_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR1_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR1_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-#define  FMC_BWTR1_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR1_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR1_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR2 register  ******************/
-#define  FMC_BWTR2_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR2_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR2_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR2_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR2_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-#define  FMC_BWTR2_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR2_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR2_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR2_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR2_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-#define  FMC_BWTR2_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR2_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR2_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR2_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR2_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR2_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR2_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR2_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR2_DATAST_7                 0x00008000U        /*!<Bit 7 */
-#define  FMC_BWTR2_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BWTR2_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR2_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR2_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR2_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-#define  FMC_BWTR2_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR2_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR2_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR3 register  ******************/
-#define  FMC_BWTR3_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR3_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR3_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR3_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR3_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-#define  FMC_BWTR3_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR3_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR3_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR3_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR3_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-#define  FMC_BWTR3_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR3_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR3_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR3_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR3_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR3_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR3_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR3_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR3_DATAST_7                 0x00008000U        /*!<Bit 7 */
-#define  FMC_BWTR3_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BWTR3_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR3_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR3_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR3_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-#define  FMC_BWTR3_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR3_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR3_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR4 register  ******************/
-#define  FMC_BWTR4_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR4_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR4_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR4_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR4_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-#define  FMC_BWTR4_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR4_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR4_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR4_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR4_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-#define  FMC_BWTR4_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR4_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR4_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR4_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR4_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR4_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR4_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR4_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR4_DATAST_7                 0x00008000U        /*!<Bit 7 */
-#define  FMC_BWTR4_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BWTR4_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR4_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR4_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR4_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-#define  FMC_BWTR4_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR4_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR4_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_PCR register  *******************/
-#define  FMC_PCR_PWAITEN                   0x00000002U        /*!<Wait feature enable bit                   */
-#define  FMC_PCR_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FMC_PCR_PTYP                      0x00000008U        /*!<Memory type                               */
-#define  FMC_PCR_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FMC_PCR_PWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_PCR_PWID_1                    0x00000020U        /*!<Bit 1 */
-#define  FMC_PCR_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit          */
-#define  FMC_PCR_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay)          */
-#define  FMC_PCR_TCLR_0                    0x00000200U        /*!<Bit 0 */
-#define  FMC_PCR_TCLR_1                    0x00000400U        /*!<Bit 1 */
-#define  FMC_PCR_TCLR_2                    0x00000800U        /*!<Bit 2 */
-#define  FMC_PCR_TCLR_3                    0x00001000U        /*!<Bit 3 */
-#define  FMC_PCR_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay)           */
-#define  FMC_PCR_TAR_0                     0x00002000U        /*!<Bit 0 */
-#define  FMC_PCR_TAR_1                     0x00004000U        /*!<Bit 1 */
-#define  FMC_PCR_TAR_2                     0x00008000U        /*!<Bit 2 */
-#define  FMC_PCR_TAR_3                     0x00010000U        /*!<Bit 3 */
-#define  FMC_PCR_ECCPS                     0x000E0000U        /*!<ECCPS[2:0] bits (ECC page size)           */
-#define  FMC_PCR_ECCPS_0                   0x00020000U        /*!<Bit 0 */
-#define  FMC_PCR_ECCPS_1                   0x00040000U        /*!<Bit 1 */
-#define  FMC_PCR_ECCPS_2                   0x00080000U        /*!<Bit 2 */
-
-/*******************  Bit definition for FMC_SR register  *******************/
-#define  FMC_SR_IRS                        0x01U              /*!<Interrupt Rising Edge status                */
-#define  FMC_SR_ILS                        0x02U              /*!<Interrupt Level status                      */
-#define  FMC_SR_IFS                        0x04U              /*!<Interrupt Falling Edge status               */
-#define  FMC_SR_IREN                       0x08U              /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FMC_SR_ILEN                       0x10U              /*!<Interrupt Level detection Enable bit        */
-#define  FMC_SR_IFEN                       0x20U              /*!<Interrupt Falling Edge detection Enable bit */
-#define  FMC_SR_FEMPT                      0x40U              /*!<FIFO empty                                  */
-
-/******************  Bit definition for FMC_PMEM register  ******************/
-#define  FMC_PMEM_MEMSET3                  0x000000FFU        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
-#define  FMC_PMEM_MEMSET3_0                0x00000001U        /*!<Bit 0 */
-#define  FMC_PMEM_MEMSET3_1                0x00000002U        /*!<Bit 1 */
-#define  FMC_PMEM_MEMSET3_2                0x00000004U        /*!<Bit 2 */
-#define  FMC_PMEM_MEMSET3_3                0x00000008U        /*!<Bit 3 */
-#define  FMC_PMEM_MEMSET3_4                0x00000010U        /*!<Bit 4 */
-#define  FMC_PMEM_MEMSET3_5                0x00000020U        /*!<Bit 5 */
-#define  FMC_PMEM_MEMSET3_6                0x00000040U        /*!<Bit 6 */
-#define  FMC_PMEM_MEMSET3_7                0x00000080U        /*!<Bit 7 */
-#define  FMC_PMEM_MEMWAIT3                 0x0000FF00U        /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
-#define  FMC_PMEM_MEMWAIT3_0               0x00000100U        /*!<Bit 0 */
-#define  FMC_PMEM_MEMWAIT3_1               0x00000200U        /*!<Bit 1 */
-#define  FMC_PMEM_MEMWAIT3_2               0x00000400U        /*!<Bit 2 */
-#define  FMC_PMEM_MEMWAIT3_3               0x00000800U        /*!<Bit 3 */
-#define  FMC_PMEM_MEMWAIT3_4               0x00001000U        /*!<Bit 4 */
-#define  FMC_PMEM_MEMWAIT3_5               0x00002000U        /*!<Bit 5 */
-#define  FMC_PMEM_MEMWAIT3_6               0x00004000U        /*!<Bit 6 */
-#define  FMC_PMEM_MEMWAIT3_7               0x00008000U        /*!<Bit 7 */
-#define  FMC_PMEM_MEMHOLD3                 0x00FF0000U        /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
-#define  FMC_PMEM_MEMHOLD3_0               0x00010000U        /*!<Bit 0 */
-#define  FMC_PMEM_MEMHOLD3_1               0x00020000U        /*!<Bit 1 */
-#define  FMC_PMEM_MEMHOLD3_2               0x00040000U        /*!<Bit 2 */
-#define  FMC_PMEM_MEMHOLD3_3               0x00080000U        /*!<Bit 3 */
-#define  FMC_PMEM_MEMHOLD3_4               0x00100000U        /*!<Bit 4 */
-#define  FMC_PMEM_MEMHOLD3_5               0x00200000U        /*!<Bit 5 */
-#define  FMC_PMEM_MEMHOLD3_6               0x00400000U        /*!<Bit 6 */
-#define  FMC_PMEM_MEMHOLD3_7               0x00800000U        /*!<Bit 7 */
-#define  FMC_PMEM_MEMHIZ3                  0xFF000000U        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
-#define  FMC_PMEM_MEMHIZ3_0                0x01000000U        /*!<Bit 0 */
-#define  FMC_PMEM_MEMHIZ3_1                0x02000000U        /*!<Bit 1 */
-#define  FMC_PMEM_MEMHIZ3_2                0x04000000U        /*!<Bit 2 */
-#define  FMC_PMEM_MEMHIZ3_3                0x08000000U        /*!<Bit 3 */
-#define  FMC_PMEM_MEMHIZ3_4                0x10000000U        /*!<Bit 4 */
-#define  FMC_PMEM_MEMHIZ3_5                0x20000000U        /*!<Bit 5 */
-#define  FMC_PMEM_MEMHIZ3_6                0x40000000U        /*!<Bit 6 */
-#define  FMC_PMEM_MEMHIZ3_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_PATT register  ******************/
-#define  FMC_PATT_ATTSET3                  0x000000FFU        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
-#define  FMC_PATT_ATTSET3_0                0x00000001U        /*!<Bit 0 */
-#define  FMC_PATT_ATTSET3_1                0x00000002U        /*!<Bit 1 */
-#define  FMC_PATT_ATTSET3_2                0x00000004U        /*!<Bit 2 */
-#define  FMC_PATT_ATTSET3_3                0x00000008U        /*!<Bit 3 */
-#define  FMC_PATT_ATTSET3_4                0x00000010U        /*!<Bit 4 */
-#define  FMC_PATT_ATTSET3_5                0x00000020U        /*!<Bit 5 */
-#define  FMC_PATT_ATTSET3_6                0x00000040U        /*!<Bit 6 */
-#define  FMC_PATT_ATTSET3_7                0x00000080U        /*!<Bit 7 */
-#define  FMC_PATT_ATTWAIT3                 0x0000FF00U        /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
-#define  FMC_PATT_ATTWAIT3_0               0x00000100U        /*!<Bit 0 */
-#define  FMC_PATT_ATTWAIT3_1               0x00000200U        /*!<Bit 1 */
-#define  FMC_PATT_ATTWAIT3_2               0x00000400U        /*!<Bit 2 */
-#define  FMC_PATT_ATTWAIT3_3               0x00000800U        /*!<Bit 3 */
-#define  FMC_PATT_ATTWAIT3_4               0x00001000U        /*!<Bit 4 */
-#define  FMC_PATT_ATTWAIT3_5               0x00002000U        /*!<Bit 5 */
-#define  FMC_PATT_ATTWAIT3_6               0x00004000U        /*!<Bit 6 */
-#define  FMC_PATT_ATTWAIT3_7               0x00008000U        /*!<Bit 7 */
-#define  FMC_PATT_ATTHOLD3                 0x00FF0000U        /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
-#define  FMC_PATT_ATTHOLD3_0               0x00010000U        /*!<Bit 0 */
-#define  FMC_PATT_ATTHOLD3_1               0x00020000U        /*!<Bit 1 */
-#define  FMC_PATT_ATTHOLD3_2               0x00040000U        /*!<Bit 2 */
-#define  FMC_PATT_ATTHOLD3_3               0x00080000U        /*!<Bit 3 */
-#define  FMC_PATT_ATTHOLD3_4               0x00100000U        /*!<Bit 4 */
-#define  FMC_PATT_ATTHOLD3_5               0x00200000U        /*!<Bit 5 */
-#define  FMC_PATT_ATTHOLD3_6               0x00400000U        /*!<Bit 6 */
-#define  FMC_PATT_ATTHOLD3_7               0x00800000U        /*!<Bit 7 */
-#define  FMC_PATT_ATTHIZ3                  0xFF000000U        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
-#define  FMC_PATT_ATTHIZ3_0                0x01000000U        /*!<Bit 0 */
-#define  FMC_PATT_ATTHIZ3_1                0x02000000U        /*!<Bit 1 */
-#define  FMC_PATT_ATTHIZ3_2                0x04000000U        /*!<Bit 2 */
-#define  FMC_PATT_ATTHIZ3_3                0x08000000U        /*!<Bit 3 */
-#define  FMC_PATT_ATTHIZ3_4                0x10000000U        /*!<Bit 4 */
-#define  FMC_PATT_ATTHIZ3_5                0x20000000U        /*!<Bit 5 */
-#define  FMC_PATT_ATTHIZ3_6                0x40000000U        /*!<Bit 6 */
-#define  FMC_PATT_ATTHIZ3_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_ECCR register  ******************/
-#define  FMC_ECCR_ECC3                     0xFFFFFFFFU        /*!<ECC result */
-
-/******************  Bit definition for FMC_SDCR1 register  ******************/
-#define  FMC_SDCR1_NC                       0x00000003U        /*!<NC[1:0] bits (Number of column bits) */
-#define  FMC_SDCR1_NC_0                     0x00000001U        /*!<Bit 0 */
-#define  FMC_SDCR1_NC_1                     0x00000002U        /*!<Bit 1 */
-#define  FMC_SDCR1_NR                       0x0000000CU        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR1_NR_0                     0x00000004U        /*!<Bit 0 */
-#define  FMC_SDCR1_NR_1                     0x00000008U        /*!<Bit 1 */
-#define  FMC_SDCR1_MWID                     0x00000030U        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR1_MWID_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDCR1_MWID_1                   0x00000020U        /*!<Bit 1 */
-#define  FMC_SDCR1_NB                       0x00000040U        /*!<Number of internal bank */
-#define  FMC_SDCR1_CAS                      0x00000180U        /*!<CAS[1:0] bits (CAS latency) */
-#define  FMC_SDCR1_CAS_0                    0x00000080U        /*!<Bit 0 */
-#define  FMC_SDCR1_CAS_1                    0x00000100U        /*!<Bit 1 */
-#define  FMC_SDCR1_WP                       0x00000200U        /*!<Write protection */
-#define  FMC_SDCR1_SDCLK                    0x00000C00U        /*!<SDRAM clock configuration */
-#define  FMC_SDCR1_SDCLK_0                  0x00000400U        /*!<Bit 0 */
-#define  FMC_SDCR1_SDCLK_1                  0x00000800U        /*!<Bit 1 */
-#define  FMC_SDCR1_RBURST                   0x00001000U        /*!<Read burst */
-#define  FMC_SDCR1_RPIPE                    0x00006000U        /*!<Write protection */
-#define  FMC_SDCR1_RPIPE_0                  0x00002000U        /*!<Bit 0 */
-#define  FMC_SDCR1_RPIPE_1                  0x00004000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_SDCR2 register  ******************/
-#define  FMC_SDCR2_NC                       0x00000003U        /*!<NC[1:0] bits (Number of column bits) */
-#define  FMC_SDCR2_NC_0                     0x00000001U        /*!<Bit 0 */
-#define  FMC_SDCR2_NC_1                     0x00000002U        /*!<Bit 1 */
-#define  FMC_SDCR2_NR                       0x0000000CU        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR2_NR_0                     0x00000004U        /*!<Bit 0 */
-#define  FMC_SDCR2_NR_1                     0x00000008U        /*!<Bit 1 */
-#define  FMC_SDCR2_MWID                     0x00000030U        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR2_MWID_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDCR2_MWID_1                   0x00000020U        /*!<Bit 1 */
-#define  FMC_SDCR2_NB                       0x00000040U        /*!<Number of internal bank */
-#define  FMC_SDCR2_CAS                      0x00000180U        /*!<CAS[1:0] bits (CAS latency) */
-#define  FMC_SDCR2_CAS_0                    0x00000080U        /*!<Bit 0 */
-#define  FMC_SDCR2_CAS_1                    0x00000100U        /*!<Bit 1 */
-#define  FMC_SDCR2_WP                       0x00000200U        /*!<Write protection */
-#define  FMC_SDCR2_SDCLK                    0x00000C00U        /*!<SDCLK[1:0] (SDRAM clock configuration) */
-#define  FMC_SDCR2_SDCLK_0                  0x00000400U        /*!<Bit 0 */
-#define  FMC_SDCR2_SDCLK_1                  0x00000800U        /*!<Bit 1 */
-#define  FMC_SDCR2_RBURST                   0x00001000U        /*!<Read burst */
-#define  FMC_SDCR2_RPIPE                    0x00006000U        /*!<RPIPE[1:0](Read pipe) */
-#define  FMC_SDCR2_RPIPE_0                  0x00002000U        /*!<Bit 0 */
-#define  FMC_SDCR2_RPIPE_1                  0x00004000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_SDTR1 register  ******************/
-#define  FMC_SDTR1_TMRD                     0x0000000FU        /*!<TMRD[3:0] bits (Load mode register to active) */
-#define  FMC_SDTR1_TMRD_0                   0x00000001U        /*!<Bit 0 */
-#define  FMC_SDTR1_TMRD_1                   0x00000002U        /*!<Bit 1 */
-#define  FMC_SDTR1_TMRD_2                   0x00000004U        /*!<Bit 2 */
-#define  FMC_SDTR1_TMRD_3                   0x00000008U        /*!<Bit 3 */
-#define  FMC_SDTR1_TXSR                     0x000000F0U        /*!<TXSR[3:0] bits (Exit self refresh) */
-#define  FMC_SDTR1_TXSR_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDTR1_TXSR_1                   0x00000020U        /*!<Bit 1 */
-#define  FMC_SDTR1_TXSR_2                   0x00000040U        /*!<Bit 2 */
-#define  FMC_SDTR1_TXSR_3                   0x00000080U        /*!<Bit 3 */
-#define  FMC_SDTR1_TRAS                     0x00000F00U        /*!<TRAS[3:0] bits (Self refresh time) */
-#define  FMC_SDTR1_TRAS_0                   0x00000100U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRAS_1                   0x00000200U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRAS_2                   0x00000400U        /*!<Bit 2 */
-#define  FMC_SDTR1_TRAS_3                   0x00000800U        /*!<Bit 3 */
-#define  FMC_SDTR1_TRC                      0x0000F000U        /*!<TRC[2:0] bits (Row cycle delay) */
-#define  FMC_SDTR1_TRC_0                    0x00001000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRC_1                    0x00002000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRC_2                    0x00004000U        /*!<Bit 2 */
-#define  FMC_SDTR1_TWR                      0x000F0000U        /*!<TRC[2:0] bits (Write recovery delay) */
-#define  FMC_SDTR1_TWR_0                    0x00010000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TWR_1                    0x00020000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TWR_2                    0x00040000U        /*!<Bit 2 */
-#define  FMC_SDTR1_TRP                      0x00F00000U        /*!<TRP[2:0] bits (Row precharge delay) */
-#define  FMC_SDTR1_TRP_0                    0x00100000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRP_1                    0x00200000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRP_2                    0x00400000U        /*!<Bit 2 */
-#define  FMC_SDTR1_TRCD                     0x0F000000U        /*!<TRP[2:0] bits (Row to column delay) */
-#define  FMC_SDTR1_TRCD_0                   0x01000000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRCD_1                   0x02000000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRCD_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for FMC_SDTR2 register  ******************/
-#define  FMC_SDTR2_TMRD                     0x0000000FU        /*!<TMRD[3:0] bits (Load mode register to active) */
-#define  FMC_SDTR2_TMRD_0                   0x00000001U        /*!<Bit 0 */
-#define  FMC_SDTR2_TMRD_1                   0x00000002U        /*!<Bit 1 */
-#define  FMC_SDTR2_TMRD_2                   0x00000004U        /*!<Bit 2 */
-#define  FMC_SDTR2_TMRD_3                   0x00000008U        /*!<Bit 3 */
-#define  FMC_SDTR2_TXSR                     0x000000F0U        /*!<TXSR[3:0] bits (Exit self refresh) */
-#define  FMC_SDTR2_TXSR_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDTR2_TXSR_1                   0x00000020U        /*!<Bit 1 */
-#define  FMC_SDTR2_TXSR_2                   0x00000040U        /*!<Bit 2 */
-#define  FMC_SDTR2_TXSR_3                   0x00000080U        /*!<Bit 3 */
-#define  FMC_SDTR2_TRAS                     0x00000F00U        /*!<TRAS[3:0] bits (Self refresh time) */
-#define  FMC_SDTR2_TRAS_0                   0x00000100U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRAS_1                   0x00000200U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRAS_2                   0x00000400U        /*!<Bit 2 */
-#define  FMC_SDTR2_TRAS_3                   0x00000800U        /*!<Bit 3 */
-#define  FMC_SDTR2_TRC                      0x0000F000U        /*!<TRC[2:0] bits (Row cycle delay) */
-#define  FMC_SDTR2_TRC_0                    0x00001000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRC_1                    0x00002000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRC_2                    0x00004000U        /*!<Bit 2 */
-#define  FMC_SDTR2_TWR                      0x000F0000U        /*!<TRC[2:0] bits (Write recovery delay) */
-#define  FMC_SDTR2_TWR_0                    0x00010000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TWR_1                    0x00020000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TWR_2                    0x00040000U        /*!<Bit 2 */
-#define  FMC_SDTR2_TRP                      0x00F00000U        /*!<TRP[2:0] bits (Row precharge delay) */
-#define  FMC_SDTR2_TRP_0                    0x00100000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRP_1                    0x00200000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRP_2                    0x00400000U        /*!<Bit 2 */
-#define  FMC_SDTR2_TRCD                     0x0F000000U        /*!<TRP[2:0] bits (Row to column delay) */
-#define  FMC_SDTR2_TRCD_0                   0x01000000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRCD_1                   0x02000000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRCD_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for FMC_SDCMR register  ******************/
-#define  FMC_SDCMR_MODE                     0x00000007U        /*!<MODE[2:0] bits (Command mode) */
-#define  FMC_SDCMR_MODE_0                   0x00000001U        /*!<Bit 0 */
-#define  FMC_SDCMR_MODE_1                   0x00000002U        /*!<Bit 1 */
-#define  FMC_SDCMR_MODE_2                   0x00000003U        /*!<Bit 2 */
-#define  FMC_SDCMR_CTB2                     0x00000008U        /*!<Command target 2 */
-#define  FMC_SDCMR_CTB1                     0x00000010U        /*!<Command target 1 */
-#define  FMC_SDCMR_NRFS                     0x000001E0U        /*!<NRFS[3:0] bits (Number of auto-refresh) */
-#define  FMC_SDCMR_NRFS_0                   0x00000020U        /*!<Bit 0 */
-#define  FMC_SDCMR_NRFS_1                   0x00000040U        /*!<Bit 1 */
-#define  FMC_SDCMR_NRFS_2                   0x00000080U        /*!<Bit 2 */
-#define  FMC_SDCMR_NRFS_3                   0x00000100U        /*!<Bit 3 */
-#define  FMC_SDCMR_MRD                      0x003FFE00U        /*!<MRD[12:0] bits (Mode register definition) */
-
-/******************  Bit definition for FMC_SDRTR register  ******************/
-#define  FMC_SDRTR_CRE                      0x00000001U        /*!<Clear refresh error flag */
-#define  FMC_SDRTR_COUNT                    0x00003FFEU        /*!<COUNT[12:0] bits (Refresh timer count) */
-#define  FMC_SDRTR_REIE                     0x00004000U        /*!<RES interupt enable */
-
-/******************  Bit definition for FMC_SDSR register  ******************/
-#define  FMC_SDSR_RE                        0x00000001U        /*!<Refresh error flag */
-#define  FMC_SDSR_MODES1                    0x00000006U        /*!<MODES1[1:0]bits (Status mode for bank 1) */
-#define  FMC_SDSR_MODES1_0                  0x00000002U        /*!<Bit 0 */
-#define  FMC_SDSR_MODES1_1                  0x00000004U        /*!<Bit 1 */
-#define  FMC_SDSR_MODES2                    0x00000018U        /*!<MODES2[1:0]bits (Status mode for bank 2) */
-#define  FMC_SDSR_MODES2_0                  0x00000008U        /*!<Bit 0 */
-#define  FMC_SDSR_MODES2_1                  0x00000010U        /*!<Bit 1 */
-#define  FMC_SDSR_BUSY                      0x00000020U        /*!<Busy status */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    0x00000003U
-#define GPIO_MODER_MODER0_0                  0x00000001U
-#define GPIO_MODER_MODER0_1                  0x00000002U
-#define GPIO_MODER_MODER1                    0x0000000CU
-#define GPIO_MODER_MODER1_0                  0x00000004U
-#define GPIO_MODER_MODER1_1                  0x00000008U
-#define GPIO_MODER_MODER2                    0x00000030U
-#define GPIO_MODER_MODER2_0                  0x00000010U
-#define GPIO_MODER_MODER2_1                  0x00000020U
-#define GPIO_MODER_MODER3                    0x000000C0U
-#define GPIO_MODER_MODER3_0                  0x00000040U
-#define GPIO_MODER_MODER3_1                  0x00000080U
-#define GPIO_MODER_MODER4                    0x00000300U
-#define GPIO_MODER_MODER4_0                  0x00000100U
-#define GPIO_MODER_MODER4_1                  0x00000200U
-#define GPIO_MODER_MODER5                    0x00000C00U
-#define GPIO_MODER_MODER5_0                  0x00000400U
-#define GPIO_MODER_MODER5_1                  0x00000800U
-#define GPIO_MODER_MODER6                    0x00003000U
-#define GPIO_MODER_MODER6_0                  0x00001000U
-#define GPIO_MODER_MODER6_1                  0x00002000U
-#define GPIO_MODER_MODER7                    0x0000C000U
-#define GPIO_MODER_MODER7_0                  0x00004000U
-#define GPIO_MODER_MODER7_1                  0x00008000U
-#define GPIO_MODER_MODER8                    0x00030000U
-#define GPIO_MODER_MODER8_0                  0x00010000U
-#define GPIO_MODER_MODER8_1                  0x00020000U
-#define GPIO_MODER_MODER9                    0x000C0000U
-#define GPIO_MODER_MODER9_0                  0x00040000U
-#define GPIO_MODER_MODER9_1                  0x00080000U
-#define GPIO_MODER_MODER10                   0x00300000U
-#define GPIO_MODER_MODER10_0                 0x00100000U
-#define GPIO_MODER_MODER10_1                 0x00200000U
-#define GPIO_MODER_MODER11                   0x00C00000U
-#define GPIO_MODER_MODER11_0                 0x00400000U
-#define GPIO_MODER_MODER11_1                 0x00800000U
-#define GPIO_MODER_MODER12                   0x03000000U
-#define GPIO_MODER_MODER12_0                 0x01000000U
-#define GPIO_MODER_MODER12_1                 0x02000000U
-#define GPIO_MODER_MODER13                   0x0C000000U
-#define GPIO_MODER_MODER13_0                 0x04000000U
-#define GPIO_MODER_MODER13_1                 0x08000000U
-#define GPIO_MODER_MODER14                   0x30000000U
-#define GPIO_MODER_MODER14_0                 0x10000000U
-#define GPIO_MODER_MODER14_1                 0x20000000U
-#define GPIO_MODER_MODER15                   0xC0000000U
-#define GPIO_MODER_MODER15_0                 0x40000000U
-#define GPIO_MODER_MODER15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     0x00000001U
-#define GPIO_OTYPER_OT_1                     0x00000002U
-#define GPIO_OTYPER_OT_2                     0x00000004U
-#define GPIO_OTYPER_OT_3                     0x00000008U
-#define GPIO_OTYPER_OT_4                     0x00000010U
-#define GPIO_OTYPER_OT_5                     0x00000020U
-#define GPIO_OTYPER_OT_6                     0x00000040U
-#define GPIO_OTYPER_OT_7                     0x00000080U
-#define GPIO_OTYPER_OT_8                     0x00000100U
-#define GPIO_OTYPER_OT_9                     0x00000200U
-#define GPIO_OTYPER_OT_10                    0x00000400U
-#define GPIO_OTYPER_OT_11                    0x00000800U
-#define GPIO_OTYPER_OT_12                    0x00001000U
-#define GPIO_OTYPER_OT_13                    0x00002000U
-#define GPIO_OTYPER_OT_14                    0x00004000U
-#define GPIO_OTYPER_OT_15                    0x00008000U
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
-#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
-#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
-#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
-#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
-#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
-#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
-#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
-#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
-#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
-#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
-#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
-#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
-#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
-#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
-#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
-#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
-#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
-#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
-#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
-#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
-#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
-#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
-#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
-#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
-#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
-#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
-#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
-#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
-#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
-#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
-#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
-#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
-#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
-#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
-#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
-#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
-#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
-#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
-#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
-#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
-#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
-#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
-#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
-#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
-#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
-#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
-#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    0x00000003U
-#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
-#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
-#define GPIO_PUPDR_PUPDR1                    0x0000000CU
-#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
-#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
-#define GPIO_PUPDR_PUPDR2                    0x00000030U
-#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
-#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
-#define GPIO_PUPDR_PUPDR3                    0x000000C0U
-#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
-#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
-#define GPIO_PUPDR_PUPDR4                    0x00000300U
-#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
-#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
-#define GPIO_PUPDR_PUPDR5                    0x00000C00U
-#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
-#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
-#define GPIO_PUPDR_PUPDR6                    0x00003000U
-#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
-#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
-#define GPIO_PUPDR_PUPDR7                    0x0000C000U
-#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
-#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
-#define GPIO_PUPDR_PUPDR8                    0x00030000U
-#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
-#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
-#define GPIO_PUPDR_PUPDR9                    0x000C0000U
-#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
-#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
-#define GPIO_PUPDR_PUPDR10                   0x00300000U
-#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
-#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
-#define GPIO_PUPDR_PUPDR11                   0x00C00000U
-#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
-#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
-#define GPIO_PUPDR_PUPDR12                   0x03000000U
-#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
-#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
-#define GPIO_PUPDR_PUPDR13                   0x0C000000U
-#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
-#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
-#define GPIO_PUPDR_PUPDR14                   0x30000000U
-#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
-#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
-#define GPIO_PUPDR_PUPDR15                   0xC0000000U
-#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
-#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       0x00000001U
-#define GPIO_IDR_IDR_1                       0x00000002U
-#define GPIO_IDR_IDR_2                       0x00000004U
-#define GPIO_IDR_IDR_3                       0x00000008U
-#define GPIO_IDR_IDR_4                       0x00000010U
-#define GPIO_IDR_IDR_5                       0x00000020U
-#define GPIO_IDR_IDR_6                       0x00000040U
-#define GPIO_IDR_IDR_7                       0x00000080U
-#define GPIO_IDR_IDR_8                       0x00000100U
-#define GPIO_IDR_IDR_9                       0x00000200U
-#define GPIO_IDR_IDR_10                      0x00000400U
-#define GPIO_IDR_IDR_11                      0x00000800U
-#define GPIO_IDR_IDR_12                      0x00001000U
-#define GPIO_IDR_IDR_13                      0x00002000U
-#define GPIO_IDR_IDR_14                      0x00004000U
-#define GPIO_IDR_IDR_15                      0x00008000U
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       0x00000001U
-#define GPIO_ODR_ODR_1                       0x00000002U
-#define GPIO_ODR_ODR_2                       0x00000004U
-#define GPIO_ODR_ODR_3                       0x00000008U
-#define GPIO_ODR_ODR_4                       0x00000010U
-#define GPIO_ODR_ODR_5                       0x00000020U
-#define GPIO_ODR_ODR_6                       0x00000040U
-#define GPIO_ODR_ODR_7                       0x00000080U
-#define GPIO_ODR_ODR_8                       0x00000100U
-#define GPIO_ODR_ODR_9                       0x00000200U
-#define GPIO_ODR_ODR_10                      0x00000400U
-#define GPIO_ODR_ODR_11                      0x00000800U
-#define GPIO_ODR_ODR_12                      0x00001000U
-#define GPIO_ODR_ODR_13                      0x00002000U
-#define GPIO_ODR_ODR_14                      0x00004000U
-#define GPIO_ODR_ODR_15                      0x00008000U
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       0x00000001U
-#define GPIO_BSRR_BS_1                       0x00000002U
-#define GPIO_BSRR_BS_2                       0x00000004U
-#define GPIO_BSRR_BS_3                       0x00000008U
-#define GPIO_BSRR_BS_4                       0x00000010U
-#define GPIO_BSRR_BS_5                       0x00000020U
-#define GPIO_BSRR_BS_6                       0x00000040U
-#define GPIO_BSRR_BS_7                       0x00000080U
-#define GPIO_BSRR_BS_8                       0x00000100U
-#define GPIO_BSRR_BS_9                       0x00000200U
-#define GPIO_BSRR_BS_10                      0x00000400U
-#define GPIO_BSRR_BS_11                      0x00000800U
-#define GPIO_BSRR_BS_12                      0x00001000U
-#define GPIO_BSRR_BS_13                      0x00002000U
-#define GPIO_BSRR_BS_14                      0x00004000U
-#define GPIO_BSRR_BS_15                      0x00008000U
-#define GPIO_BSRR_BR_0                       0x00010000U
-#define GPIO_BSRR_BR_1                       0x00020000U
-#define GPIO_BSRR_BR_2                       0x00040000U
-#define GPIO_BSRR_BR_3                       0x00080000U
-#define GPIO_BSRR_BR_4                       0x00100000U
-#define GPIO_BSRR_BR_5                       0x00200000U
-#define GPIO_BSRR_BR_6                       0x00400000U
-#define GPIO_BSRR_BR_7                       0x00800000U
-#define GPIO_BSRR_BR_8                       0x01000000U
-#define GPIO_BSRR_BR_9                       0x02000000U
-#define GPIO_BSRR_BR_10                      0x04000000U
-#define GPIO_BSRR_BR_11                      0x08000000U
-#define GPIO_BSRR_BR_12                      0x10000000U
-#define GPIO_BSRR_BR_13                      0x20000000U
-#define GPIO_BSRR_BR_14                      0x40000000U
-#define GPIO_BSRR_BR_15                      0x80000000U
-
-/****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0                       0x00000001U
-#define GPIO_LCKR_LCK1                       0x00000002U
-#define GPIO_LCKR_LCK2                       0x00000004U
-#define GPIO_LCKR_LCK3                       0x00000008U
-#define GPIO_LCKR_LCK4                       0x00000010U
-#define GPIO_LCKR_LCK5                       0x00000020U
-#define GPIO_LCKR_LCK6                       0x00000040U
-#define GPIO_LCKR_LCK7                       0x00000080U
-#define GPIO_LCKR_LCK8                       0x00000100U
-#define GPIO_LCKR_LCK9                       0x00000200U
-#define GPIO_LCKR_LCK10                      0x00000400U
-#define GPIO_LCKR_LCK11                      0x00000800U
-#define GPIO_LCKR_LCK12                      0x00001000U
-#define GPIO_LCKR_LCK13                      0x00002000U
-#define GPIO_LCKR_LCK14                      0x00004000U
-#define GPIO_LCKR_LCK15                      0x00008000U
-#define GPIO_LCKR_LCKK                       0x00010000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    HASH                                    */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for HASH_CR register  ********************/
-#define HASH_CR_INIT                         0x00000004U
-#define HASH_CR_DMAE                         0x00000008U
-#define HASH_CR_DATATYPE                     0x00000030U
-#define HASH_CR_DATATYPE_0                   0x00000010U
-#define HASH_CR_DATATYPE_1                   0x00000020U
-#define HASH_CR_MODE                         0x00000040U
-#define HASH_CR_ALGO                         0x00040080U
-#define HASH_CR_ALGO_0                       0x00000080U
-#define HASH_CR_ALGO_1                       0x00040000U
-#define HASH_CR_NBW                          0x00000F00U
-#define HASH_CR_NBW_0                        0x00000100U
-#define HASH_CR_NBW_1                        0x00000200U
-#define HASH_CR_NBW_2                        0x00000400U
-#define HASH_CR_NBW_3                        0x00000800U
-#define HASH_CR_DINNE                        0x00001000U
-#define HASH_CR_MDMAT                        0x00002000U
-#define HASH_CR_LKEY                         0x00010000U
-
-/******************  Bits definition for HASH_STR register  *******************/
-#define HASH_STR_NBLW                        0x0000001FU
-#define HASH_STR_NBLW_0                      0x00000001U
-#define HASH_STR_NBLW_1                      0x00000002U
-#define HASH_STR_NBLW_2                      0x00000004U
-#define HASH_STR_NBLW_3                      0x00000008U
-#define HASH_STR_NBLW_4                      0x00000010U
-#define HASH_STR_DCAL                        0x00000100U
-
-/* legacy defines */
-#define HASH_STR_NBW                         HASH_STR_NBLW
-#define HASH_STR_NBW_0                       HASH_STR_NBLW_0
-#define HASH_STR_NBW_1                       HASH_STR_NBLW_1
-#define HASH_STR_NBW_2                       HASH_STR_NBLW_2
-#define HASH_STR_NBW_3                       HASH_STR_NBLW_3
-#define HASH_STR_NBW_4                       HASH_STR_NBLW_4
-
-/******************  Bits definition for HASH_IMR register  *******************/
-#define HASH_IMR_DINIE                       0x00000001U
-#define HASH_IMR_DCIE                        0x00000002U
-
-/* legacy defines */
-#define HASH_IMR_DINIM                       HASH_IMR_DINIE
-#define HASH_IMR_DCIM                        HASH_IMR_DCIE
-/******************  Bits definition for HASH_SR register  ********************/
-#define HASH_SR_DINIS                        0x00000001U
-#define HASH_SR_DCIS                         0x00000002U
-#define HASH_SR_DMAS                         0x00000004U
-#define HASH_SR_BUSY                         0x00000008U
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Inter-integrated Circuit Interface (I2C)              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define  I2C_CR1_PE                          0x00000001U        /*!< Peripheral enable                   */
-#define  I2C_CR1_TXIE                        0x00000002U        /*!< TX interrupt enable                 */
-#define  I2C_CR1_RXIE                        0x00000004U        /*!< RX interrupt enable                 */
-#define  I2C_CR1_ADDRIE                      0x00000008U        /*!< Address match interrupt enable      */
-#define  I2C_CR1_NACKIE                      0x00000010U        /*!< NACK received interrupt enable      */
-#define  I2C_CR1_STOPIE                      0x00000020U        /*!< STOP detection interrupt enable     */
-#define  I2C_CR1_TCIE                        0x00000040U        /*!< Transfer complete interrupt enable  */
-#define  I2C_CR1_ERRIE                       0x00000080U        /*!< Errors interrupt enable             */
-#define  I2C_CR1_DNF                         0x00000F00U        /*!< Digital noise filter                */
-#define  I2C_CR1_ANFOFF                      0x00001000U        /*!< Analog noise filter OFF             */
-#define  I2C_CR1_TXDMAEN                     0x00004000U        /*!< DMA transmission requests enable    */
-#define  I2C_CR1_RXDMAEN                     0x00008000U        /*!< DMA reception requests enable       */
-#define  I2C_CR1_SBC                         0x00010000U        /*!< Slave byte control                  */
-#define  I2C_CR1_NOSTRETCH                   0x00020000U        /*!< Clock stretching disable            */
-#define  I2C_CR1_GCEN                        0x00080000U        /*!< General call enable                 */
-#define  I2C_CR1_SMBHEN                      0x00100000U        /*!< SMBus host address enable           */
-#define  I2C_CR1_SMBDEN                      0x00200000U        /*!< SMBus device default address enable */
-#define  I2C_CR1_ALERTEN                     0x00400000U        /*!< SMBus alert enable                  */
-#define  I2C_CR1_PECEN                       0x00800000U        /*!< PEC enable                          */
-
-/* Legacy define */
-#define  I2C_CR1_DFN                         I2C_CR1_DNF                   /*!< Digital noise filter                */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_SADD                        0x000003FFU        /*!< Slave address (master mode)                             */
-#define  I2C_CR2_RD_WRN                      0x00000400U        /*!< Transfer direction (master mode)                        */
-#define  I2C_CR2_ADD10                       0x00000800U        /*!< 10-bit addressing mode (master mode)                    */
-#define  I2C_CR2_HEAD10R                     0x00001000U        /*!< 10-bit address header only read direction (master mode) */
-#define  I2C_CR2_START                       0x00002000U        /*!< START generation                                        */
-#define  I2C_CR2_STOP                        0x00004000U        /*!< STOP generation (master mode)                           */
-#define  I2C_CR2_NACK                        0x00008000U        /*!< NACK generation (slave mode)                            */
-#define  I2C_CR2_NBYTES                      0x00FF0000U        /*!< Number of bytes                                         */
-#define  I2C_CR2_RELOAD                      0x01000000U        /*!< NBYTES reload mode                                      */
-#define  I2C_CR2_AUTOEND                     0x02000000U        /*!< Automatic end mode (master mode)                        */
-#define  I2C_CR2_PECBYTE                     0x04000000U        /*!< Packet error checking byte                              */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define  I2C_OAR1_OA1                        0x000003FFU        /*!< Interface own address 1   */
-#define  I2C_OAR1_OA1MODE                    0x00000400U        /*!< Own address 1 10-bit mode */
-#define  I2C_OAR1_OA1EN                      0x00008000U        /*!< Own address 1 enable      */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define  I2C_OAR2_OA2                        0x000000FEU        /*!< Interface own address 2 */
-#define  I2C_OAR2_OA2MSK                     0x00000700U        /*!< Own address 2 masks     */
-#define  I2C_OAR2_OA2NOMASK                  0x00000000U        /*!< No mask */
-#define  I2C_OAR2_OA2MASK01                  0x00000100U        /*!< OA2[1] is masked, Only OA2[7:2] are compared */
-#define  I2C_OAR2_OA2MASK02                  0x00000200U        /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
-#define  I2C_OAR2_OA2MASK03                  0x00000300U        /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
-#define  I2C_OAR2_OA2MASK04                  0x00000400U        /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
-#define  I2C_OAR2_OA2MASK05                  0x00000500U        /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
-#define  I2C_OAR2_OA2MASK06                  0x00000600U        /*!< OA2[6:1] is masked, Only OA2[7] are compared */
-#define  I2C_OAR2_OA2MASK07                  0x00000700U        /*!< OA2[7:1] is masked, No comparison is done */
-#define  I2C_OAR2_OA2EN                      0x00008000U        /*!< Own address 2 enable    */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define  I2C_TIMINGR_SCLL                    0x000000FFU        /*!< SCL low period (master mode)  */
-#define  I2C_TIMINGR_SCLH                    0x0000FF00U        /*!< SCL high period (master mode) */
-#define  I2C_TIMINGR_SDADEL                  0x000F0000U        /*!< Data hold time                */
-#define  I2C_TIMINGR_SCLDEL                  0x00F00000U        /*!< Data setup time               */
-#define  I2C_TIMINGR_PRESC                   0xF0000000U        /*!< Timings prescaler             */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define  I2C_TIMEOUTR_TIMEOUTA               0x00000FFFU        /*!< Bus timeout A                 */
-#define  I2C_TIMEOUTR_TIDLE                  0x00001000U        /*!< Idle clock timeout detection  */
-#define  I2C_TIMEOUTR_TIMOUTEN               0x00008000U        /*!< Clock timeout enable          */
-#define  I2C_TIMEOUTR_TIMEOUTB               0x0FFF0000U        /*!< Bus timeout B                 */
-#define  I2C_TIMEOUTR_TEXTEN                 0x80000000U        /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define  I2C_ISR_TXE                         0x00000001U        /*!< Transmit data register empty    */
-#define  I2C_ISR_TXIS                        0x00000002U        /*!< Transmit interrupt status       */
-#define  I2C_ISR_RXNE                        0x00000004U        /*!< Receive data register not empty */
-#define  I2C_ISR_ADDR                        0x00000008U        /*!< Address matched (slave mode)    */
-#define  I2C_ISR_NACKF                       0x00000010U        /*!< NACK received flag              */
-#define  I2C_ISR_STOPF                       0x00000020U        /*!< STOP detection flag             */
-#define  I2C_ISR_TC                          0x00000040U        /*!< Transfer complete (master mode) */
-#define  I2C_ISR_TCR                         0x00000080U        /*!< Transfer complete reload        */
-#define  I2C_ISR_BERR                        0x00000100U        /*!< Bus error                       */
-#define  I2C_ISR_ARLO                        0x00000200U        /*!< Arbitration lost                */
-#define  I2C_ISR_OVR                         0x00000400U        /*!< Overrun/Underrun                */
-#define  I2C_ISR_PECERR                      0x00000800U        /*!< PEC error in reception          */
-#define  I2C_ISR_TIMEOUT                     0x00001000U        /*!< Timeout or Tlow detection flag  */
-#define  I2C_ISR_ALERT                       0x00002000U        /*!< SMBus alert                     */
-#define  I2C_ISR_BUSY                        0x00008000U        /*!< Bus busy                        */
-#define  I2C_ISR_DIR                         0x00010000U        /*!< Transfer direction (slave mode) */
-#define  I2C_ISR_ADDCODE                     0x00FE0000U        /*!< Address match code (slave mode) */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define  I2C_ICR_ADDRCF                      0x00000008U        /*!< Address matched clear flag      */
-#define  I2C_ICR_NACKCF                      0x00000010U        /*!< NACK clear flag                 */
-#define  I2C_ICR_STOPCF                      0x00000020U        /*!< STOP detection clear flag       */
-#define  I2C_ICR_BERRCF                      0x00000100U        /*!< Bus error clear flag            */
-#define  I2C_ICR_ARLOCF                      0x00000200U        /*!< Arbitration lost clear flag     */
-#define  I2C_ICR_OVRCF                       0x00000400U        /*!< Overrun/Underrun clear flag     */
-#define  I2C_ICR_PECCF                       0x00000800U        /*!< PAC error clear flag            */
-#define  I2C_ICR_TIMOUTCF                    0x00001000U        /*!< Timeout clear flag              */
-#define  I2C_ICR_ALERTCF                     0x00002000U        /*!< Alert clear flag                */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define  I2C_PECR_PEC                        0x000000FFU        /*!< PEC register        */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define  I2C_RXDR_RXDATA                     0x000000FFU        /*!< 8-bit receive data  */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define  I2C_TXDR_TXDATA                     0x000000FFU        /*!< 8-bit transmit data */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Independent WATCHDOG                             */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         0x01U               /*!< Watchdog prescaler value update */
-#define  IWDG_SR_RVU                         0x02U               /*!< Watchdog counter reload value update */
-#define  IWDG_SR_WVU                         0x04U               /*!< Watchdog counter window value update */
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_WINR_WIN                       0x0FFFU             /*!< Watchdog counter window value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      LCD-TFT Display Controller (LTDC)                     */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for LTDC_SSCR register  *****************/
-
-#define LTDC_SSCR_VSH                       0x000007FFU              /*!< Vertical Synchronization Height  */
-#define LTDC_SSCR_HSW                       0x0FFF0000U              /*!< Horizontal Synchronization Width */
-
-/********************  Bit definition for LTDC_BPCR register  *****************/
-
-#define LTDC_BPCR_AVBP                      0x000007FFU              /*!< Accumulated Vertical Back Porch   */
-#define LTDC_BPCR_AHBP                      0x0FFF0000U              /*!< Accumulated Horizontal Back Porch */
-
-/********************  Bit definition for LTDC_AWCR register  *****************/
-
-#define LTDC_AWCR_AAH                       0x000007FFU              /*!< Accumulated Active heigh */
-#define LTDC_AWCR_AAW                       0x0FFF0000U              /*!< Accumulated Active Width */
-
-/********************  Bit definition for LTDC_TWCR register  *****************/
-
-#define LTDC_TWCR_TOTALH                    0x000007FFU              /*!< Total Heigh */
-#define LTDC_TWCR_TOTALW                    0x0FFF0000U              /*!< Total Width */
-
-/********************  Bit definition for LTDC_GCR register  ******************/
-
-#define LTDC_GCR_LTDCEN                     0x00000001U              /*!< LCD-TFT controller enable bit       */
-#define LTDC_GCR_DBW                        0x00000070U              /*!< Dither Blue Width                   */
-#define LTDC_GCR_DGW                        0x00000700U              /*!< Dither Green Width                  */
-#define LTDC_GCR_DRW                        0x00007000U              /*!< Dither Red Width                    */
-#define LTDC_GCR_DEN                        0x00010000U              /*!< Dither Enable                       */
-#define LTDC_GCR_PCPOL                      0x10000000U              /*!< Pixel Clock Polarity                */
-#define LTDC_GCR_DEPOL                      0x20000000U              /*!< Data Enable Polarity                */
-#define LTDC_GCR_VSPOL                      0x40000000U              /*!< Vertical Synchronization Polarity   */
-#define LTDC_GCR_HSPOL                      0x80000000U              /*!< Horizontal Synchronization Polarity */
-
-/* Legacy define */
-#define LTDC_GCR_DTEN                       LTDC_GCR_DEN
-
-/********************  Bit definition for LTDC_SRCR register  *****************/
-
-#define LTDC_SRCR_IMR                      0x00000001U               /*!< Immediate Reload         */
-#define LTDC_SRCR_VBR                      0x00000002U               /*!< Vertical Blanking Reload */
-
-/********************  Bit definition for LTDC_BCCR register  *****************/
-
-#define LTDC_BCCR_BCBLUE                    0x000000FFU              /*!< Background Blue value  */
-#define LTDC_BCCR_BCGREEN                   0x0000FF00U              /*!< Background Green value */
-#define LTDC_BCCR_BCRED                     0x00FF0000U              /*!< Background Red value   */
-
-/********************  Bit definition for LTDC_IER register  ******************/
-
-#define LTDC_IER_LIE                        0x00000001U              /*!< Line Interrupt Enable            */
-#define LTDC_IER_FUIE                       0x00000002U              /*!< FIFO Underrun Interrupt Enable   */
-#define LTDC_IER_TERRIE                     0x00000004U              /*!< Transfer Error Interrupt Enable  */
-#define LTDC_IER_RRIE                       0x00000008U              /*!< Register Reload interrupt enable */
-
-/********************  Bit definition for LTDC_ISR register  ******************/
-
-#define LTDC_ISR_LIF                        0x00000001U              /*!< Line Interrupt Flag */
-#define LTDC_ISR_FUIF                       0x00000002U              /*!< FIFO Underrun Interrupt Flag */
-#define LTDC_ISR_TERRIF                     0x00000004U              /*!< Transfer Error Interrupt Flag */
-#define LTDC_ISR_RRIF                       0x00000008U              /*!< Register Reload interrupt Flag */
-
-/********************  Bit definition for LTDC_ICR register  ******************/
-
-#define LTDC_ICR_CLIF                       0x00000001U              /*!< Clears the Line Interrupt Flag */
-#define LTDC_ICR_CFUIF                      0x00000002U              /*!< Clears the FIFO Underrun Interrupt Flag */
-#define LTDC_ICR_CTERRIF                    0x00000004U              /*!< Clears the Transfer Error Interrupt Flag */
-#define LTDC_ICR_CRRIF                      0x00000008U              /*!< Clears Register Reload interrupt Flag */
-
-/********************  Bit definition for LTDC_LIPCR register  ****************/
-
-#define LTDC_LIPCR_LIPOS                    0x000007FFU              /*!< Line Interrupt Position */
-
-/********************  Bit definition for LTDC_CPSR register  *****************/
-
-#define LTDC_CPSR_CYPOS                     0x0000FFFFU              /*!< Current Y Position */
-#define LTDC_CPSR_CXPOS                     0xFFFF0000U              /*!< Current X Position */
-
-/********************  Bit definition for LTDC_CDSR register  *****************/
-
-#define LTDC_CDSR_VDES                      0x00000001U              /*!< Vertical Data Enable Status       */
-#define LTDC_CDSR_HDES                      0x00000002U              /*!< Horizontal Data Enable Status     */
-#define LTDC_CDSR_VSYNCS                    0x00000004U              /*!< Vertical Synchronization Status   */
-#define LTDC_CDSR_HSYNCS                    0x00000008U              /*!< Horizontal Synchronization Status */
-
-/********************  Bit definition for LTDC_LxCR register  *****************/
-
-#define LTDC_LxCR_LEN                       0x00000001U              /*!< Layer Enable              */
-#define LTDC_LxCR_COLKEN                    0x00000002U              /*!< Color Keying Enable       */
-#define LTDC_LxCR_CLUTEN                    0x00000010U              /*!< Color Lockup Table Enable */
-
-/********************  Bit definition for LTDC_LxWHPCR register  **************/
-
-#define LTDC_LxWHPCR_WHSTPOS                0x00000FFFU              /*!< Window Horizontal Start Position */
-#define LTDC_LxWHPCR_WHSPPOS                0xFFFF0000U              /*!< Window Horizontal Stop Position  */
-
-/********************  Bit definition for LTDC_LxWVPCR register  **************/
-
-#define LTDC_LxWVPCR_WVSTPOS                0x00000FFFU              /*!< Window Vertical Start Position */
-#define LTDC_LxWVPCR_WVSPPOS                0xFFFF0000U              /*!< Window Vertical Stop Position  */
-
-/********************  Bit definition for LTDC_LxCKCR register  ***************/
-
-#define LTDC_LxCKCR_CKBLUE                  0x000000FFU              /*!< Color Key Blue value  */
-#define LTDC_LxCKCR_CKGREEN                 0x0000FF00U              /*!< Color Key Green value */
-#define LTDC_LxCKCR_CKRED                   0x00FF0000U              /*!< Color Key Red value   */
-
-/********************  Bit definition for LTDC_LxPFCR register  ***************/
-
-#define LTDC_LxPFCR_PF                      0x00000007U              /*!< Pixel Format */
-
-/********************  Bit definition for LTDC_LxCACR register  ***************/
-
-#define LTDC_LxCACR_CONSTA                  0x000000FFU              /*!< Constant Alpha */
-
-/********************  Bit definition for LTDC_LxDCCR register  ***************/
-
-#define LTDC_LxDCCR_DCBLUE                  0x000000FFU              /*!< Default Color Blue  */
-#define LTDC_LxDCCR_DCGREEN                 0x0000FF00U              /*!< Default Color Green */
-#define LTDC_LxDCCR_DCRED                   0x00FF0000U              /*!< Default Color Red   */
-#define LTDC_LxDCCR_DCALPHA                 0xFF000000U              /*!< Default Color Alpha */
-
-/********************  Bit definition for LTDC_LxBFCR register  ***************/
-
-#define LTDC_LxBFCR_BF2                     0x00000007U              /*!< Blending Factor 2 */
-#define LTDC_LxBFCR_BF1                     0x00000700U              /*!< Blending Factor 1 */
-
-/********************  Bit definition for LTDC_LxCFBAR register  **************/
-
-#define LTDC_LxCFBAR_CFBADD                 0xFFFFFFFFU              /*!< Color Frame Buffer Start Address */
-
-/********************  Bit definition for LTDC_LxCFBLR register  **************/
-
-#define LTDC_LxCFBLR_CFBLL                  0x00001FFFU              /*!< Color Frame Buffer Line Length    */
-#define LTDC_LxCFBLR_CFBP                   0x1FFF0000U              /*!< Color Frame Buffer Pitch in bytes */
-
-/********************  Bit definition for LTDC_LxCFBLNR register  *************/
-
-#define LTDC_LxCFBLNR_CFBLNBR               0x000007FFU              /*!< Frame Buffer Line Number */
-
-/********************  Bit definition for LTDC_LxCLUTWR register  *************/
-
-#define LTDC_LxCLUTWR_BLUE                  0x000000FFU              /*!< Blue value   */
-#define LTDC_LxCLUTWR_GREEN                 0x0000FF00U              /*!< Green value  */
-#define LTDC_LxCLUTWR_RED                   0x00FF0000U              /*!< Red value    */
-#define LTDC_LxCLUTWR_CLUTADD               0xFF000000U              /*!< CLUT address */
-
-/******************************************************************************/
-/*                                                                            */
-/*                             Power Control                                  */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for PWR_CR1 register  ********************/
-#define  PWR_CR1_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
-#define  PWR_CR1_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
-#define  PWR_CR1_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
-#define  PWR_CR1_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
-#define  PWR_CR1_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR1_PLS_0                        0x00000020U     /*!< Bit 0 */
-#define  PWR_CR1_PLS_1                        0x00000040U     /*!< Bit 1 */
-#define  PWR_CR1_PLS_2                        0x00000080U     /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define  PWR_CR1_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
-#define  PWR_CR1_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
-#define  PWR_CR1_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
-#define  PWR_CR1_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
-#define  PWR_CR1_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
-#define  PWR_CR1_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
-#define  PWR_CR1_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
-#define  PWR_CR1_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
-#define  PWR_CR1_DBP                          0x00000100U     /*!< Disable Backup Domain write protection                     */
-#define  PWR_CR1_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                              */
-#define  PWR_CR1_LPUDS                        0x00000400U     /*!< Low-power regulator in deepsleep under-drive mode          */
-#define  PWR_CR1_MRUDS                        0x00000800U     /*!< Main regulator in deepsleep under-drive mode               */
-#define  PWR_CR1_ADCDC1                       0x00002000U     /*!< Refer to AN4073 on how to use this bit */
-#define  PWR_CR1_VOS                          0x0000C000U     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
-#define  PWR_CR1_VOS_0                        0x00004000U     /*!< Bit 0 */
-#define  PWR_CR1_VOS_1                        0x00008000U     /*!< Bit 1 */
-#define  PWR_CR1_ODEN                         0x00010000U     /*!< Over Drive enable                   */
-#define  PWR_CR1_ODSWEN                       0x00020000U     /*!< Over Drive switch enabled           */
-#define  PWR_CR1_UDEN                         0x000C0000U     /*!< Under Drive enable in stop mode     */
-#define  PWR_CR1_UDEN_0                       0x00040000U     /*!< Bit 0                               */
-#define  PWR_CR1_UDEN_1                       0x00080000U     /*!< Bit 1                               */
-
-/*******************  Bit definition for PWR_CSR1 register  ********************/
-#define  PWR_CSR1_WUIF                        0x00000001U     /*!< Wake up internal Flag                            */
-#define  PWR_CSR1_SBF                         0x00000002U     /*!< Standby Flag                                     */
-#define  PWR_CSR1_PVDO                        0x00000004U     /*!< PVD Output                                       */
-#define  PWR_CSR1_BRR                         0x00000008U     /*!< Backup regulator ready                           */
-#define  PWR_CSR1_EIWUP                       0x00000100U     /*!< Enable internal wakeup                           */
-#define  PWR_CSR1_BRE                         0x00000200U     /*!< Backup regulator enable                          */
-#define  PWR_CSR1_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
-#define  PWR_CSR1_ODRDY                       0x00010000U     /*!< Over Drive generator ready                       */
-#define  PWR_CSR1_ODSWRDY                     0x00020000U     /*!< Over Drive Switch ready                          */
-#define  PWR_CSR1_UDRDY                       0x000C0000U     /*!< Under Drive ready                                */
-
-/* Legacy define */
-#define  PWR_CSR1_UDSWRDY                     PWR_CSR1_UDRDY
-
-/********************  Bit definition for PWR_CR2 register  ********************/
-#define  PWR_CR2_CWUPF1                         0x00000001U     /*!< Clear Wakeup Pin Flag for PA0      */
-#define  PWR_CR2_CWUPF2                         0x00000002U     /*!< Clear Wakeup Pin Flag for PA2      */
-#define  PWR_CR2_CWUPF3                         0x00000004U     /*!< Clear Wakeup Pin Flag for PC1      */
-#define  PWR_CR2_CWUPF4                         0x00000008U     /*!< Clear Wakeup Pin Flag for PC13     */
-#define  PWR_CR2_CWUPF5                         0x00000010U     /*!< Clear Wakeup Pin Flag for PI8      */
-#define  PWR_CR2_CWUPF6                         0x00000020U     /*!< Clear Wakeup Pin Flag for PI11     */
-#define  PWR_CR2_WUPP1                          0x00000100U     /*!< Wakeup Pin Polarity bit for PA0    */
-#define  PWR_CR2_WUPP2                          0x00000200U     /*!< Wakeup Pin Polarity bit for PA2    */
-#define  PWR_CR2_WUPP3                          0x00000400U     /*!< Wakeup Pin Polarity bit for PC1    */
-#define  PWR_CR2_WUPP4                          0x00000800U     /*!< Wakeup Pin Polarity bit for PC13   */
-#define  PWR_CR2_WUPP5                          0x00001000U     /*!< Wakeup Pin Polarity bit for PI8    */
-#define  PWR_CR2_WUPP6                          0x00002000U     /*!< Wakeup Pin Polarity bit for PI11   */
-
-/*******************  Bit definition for PWR_CSR2 register  ********************/
-#define  PWR_CSR2_WUPF1                         0x00000001U     /*!< Wakeup Pin Flag for PA0            */
-#define  PWR_CSR2_WUPF2                         0x00000002U     /*!< Wakeup Pin Flag for PA2            */
-#define  PWR_CSR2_WUPF3                         0x00000004U     /*!< Wakeup Pin Flag for PC1            */
-#define  PWR_CSR2_WUPF4                         0x00000008U     /*!< Wakeup Pin Flag for PC13           */
-#define  PWR_CSR2_WUPF5                         0x00000010U     /*!< Wakeup Pin Flag for PI8            */
-#define  PWR_CSR2_WUPF6                         0x00000020U     /*!< Wakeup Pin Flag for PI11           */
-#define  PWR_CSR2_EWUP1                         0x00000100U     /*!< Enable Wakeup Pin PA0              */
-#define  PWR_CSR2_EWUP2                         0x00000200U     /*!< Enable Wakeup Pin PA2              */
-#define  PWR_CSR2_EWUP3                         0x00000400U     /*!< Enable Wakeup Pin PC1              */
-#define  PWR_CSR2_EWUP4                         0x00000800U     /*!< Enable Wakeup Pin PC13             */
-#define  PWR_CSR2_EWUP5                         0x00001000U     /*!< Enable Wakeup Pin PI8              */
-#define  PWR_CSR2_EWUP6                         0x00002000U     /*!< Enable Wakeup Pin PI11             */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    QUADSPI                                 */
-/*                                                                            */
-/******************************************************************************/
-/* QUADSPI IP version */
-#define QSPI1_V1_0
-/*****************  Bit definition for QUADSPI_CR register  *******************/
-#define  QUADSPI_CR_EN                           0x00000001U            /*!< Enable                            */
-#define  QUADSPI_CR_ABORT                        0x00000002U            /*!< Abort request                     */
-#define  QUADSPI_CR_DMAEN                        0x00000004U            /*!< DMA Enable                        */
-#define  QUADSPI_CR_TCEN                         0x00000008U            /*!< Timeout Counter Enable            */
-#define  QUADSPI_CR_SSHIFT                       0x00000010U            /*!< Sample Shift                      */
-#define  QUADSPI_CR_DFM                          0x00000040U            /*!< Dual Flash Mode                   */
-#define  QUADSPI_CR_FSEL                         0x00000080U            /*!< Flash Select                      */
-#define  QUADSPI_CR_FTHRES                       0x00001F00U            /*!< FTHRES[4:0] FIFO Level            */
-#define  QUADSPI_CR_FTHRES_0                     0x00000100U            /*!< Bit 0 */
-#define  QUADSPI_CR_FTHRES_1                     0x00000200U            /*!< Bit 1 */
-#define  QUADSPI_CR_FTHRES_2                     0x00000400U            /*!< Bit 2 */
-#define  QUADSPI_CR_FTHRES_3                     0x00000800U            /*!< Bit 3 */
-#define  QUADSPI_CR_FTHRES_4                     0x00001000U            /*!< Bit 4 */
-#define  QUADSPI_CR_TEIE                         0x00010000U            /*!< Transfer Error Interrupt Enable    */
-#define  QUADSPI_CR_TCIE                         0x00020000U            /*!< Transfer Complete Interrupt Enable */
-#define  QUADSPI_CR_FTIE                         0x00040000U            /*!< FIFO Threshold Interrupt Enable    */
-#define  QUADSPI_CR_SMIE                         0x00080000U            /*!< Status Match Interrupt Enable      */
-#define  QUADSPI_CR_TOIE                         0x00100000U            /*!< TimeOut Interrupt Enable           */
-#define  QUADSPI_CR_APMS                         0x00400000U            /*!< Bit 1                              */
-#define  QUADSPI_CR_PMM                          0x00800000U            /*!< Polling Match Mode                 */
-#define  QUADSPI_CR_PRESCALER                    0xFF000000U            /*!< PRESCALER[7:0] Clock prescaler     */
-#define  QUADSPI_CR_PRESCALER_0                  0x01000000U            /*!< Bit 0 */
-#define  QUADSPI_CR_PRESCALER_1                  0x02000000U            /*!< Bit 1 */
-#define  QUADSPI_CR_PRESCALER_2                  0x04000000U            /*!< Bit 2 */
-#define  QUADSPI_CR_PRESCALER_3                  0x08000000U            /*!< Bit 3 */
-#define  QUADSPI_CR_PRESCALER_4                  0x10000000U            /*!< Bit 4 */
-#define  QUADSPI_CR_PRESCALER_5                  0x20000000U            /*!< Bit 5 */
-#define  QUADSPI_CR_PRESCALER_6                  0x40000000U            /*!< Bit 6 */
-#define  QUADSPI_CR_PRESCALER_7                  0x80000000U            /*!< Bit 7 */
-
-/*****************  Bit definition for QUADSPI_DCR register  ******************/
-#define  QUADSPI_DCR_CKMODE                      0x00000001U            /*!< Mode 0 / Mode 3                 */
-#define  QUADSPI_DCR_CSHT                        0x00000700U            /*!< CSHT[2:0]: ChipSelect High Time */
-#define  QUADSPI_DCR_CSHT_0                      0x00000100U            /*!< Bit 0 */
-#define  QUADSPI_DCR_CSHT_1                      0x00000200U            /*!< Bit 1 */
-#define  QUADSPI_DCR_CSHT_2                      0x00000400U            /*!< Bit 2 */
-#define  QUADSPI_DCR_FSIZE                       0x001F0000U            /*!< FSIZE[4:0]: Flash Size          */
-#define  QUADSPI_DCR_FSIZE_0                     0x00010000U            /*!< Bit 0 */
-#define  QUADSPI_DCR_FSIZE_1                     0x00020000U            /*!< Bit 1 */
-#define  QUADSPI_DCR_FSIZE_2                     0x00040000U            /*!< Bit 2 */
-#define  QUADSPI_DCR_FSIZE_3                     0x00080000U            /*!< Bit 3 */
-#define  QUADSPI_DCR_FSIZE_4                     0x00100000U            /*!< Bit 4 */
-
-/******************  Bit definition for QUADSPI_SR register  *******************/
-#define  QUADSPI_SR_TEF                          0x00000001U             /*!< Transfer Error Flag    */
-#define  QUADSPI_SR_TCF                          0x00000002U             /*!< Transfer Complete Flag */
-#define  QUADSPI_SR_FTF                          0x00000004U             /*!< FIFO Threshlod Flag    */
-#define  QUADSPI_SR_SMF                          0x00000008U             /*!< Status Match Flag      */
-#define  QUADSPI_SR_TOF                          0x00000010U             /*!< Timeout Flag           */
-#define  QUADSPI_SR_BUSY                         0x00000020U             /*!< Busy                   */
-#define  QUADSPI_SR_FLEVEL                       0x00001F00U             /*!< FIFO Threshlod Flag    */
-#define  QUADSPI_SR_FLEVEL_0                     0x00000100U             /*!< Bit 0 */
-#define  QUADSPI_SR_FLEVEL_1                     0x00000200U             /*!< Bit 1 */
-#define  QUADSPI_SR_FLEVEL_2                     0x00000400U             /*!< Bit 2 */
-#define  QUADSPI_SR_FLEVEL_3                     0x00000800U             /*!< Bit 3 */
-#define  QUADSPI_SR_FLEVEL_4                     0x00001000U             /*!< Bit 4 */
-
-/******************  Bit definition for QUADSPI_FCR register  ******************/
-#define  QUADSPI_FCR_CTEF                        0x00000001U             /*!< Clear Transfer Error Flag    */
-#define  QUADSPI_FCR_CTCF                        0x00000002U             /*!< Clear Transfer Complete Flag */
-#define  QUADSPI_FCR_CSMF                        0x00000008U             /*!< Clear Status Match Flag      */
-#define  QUADSPI_FCR_CTOF                        0x00000010U             /*!< Clear Timeout Flag           */
-
-/******************  Bit definition for QUADSPI_DLR register  ******************/
-#define  QUADSPI_DLR_DL                          0xFFFFFFFFU             /*!< DL[31:0]: Data Length */
-
-/******************  Bit definition for QUADSPI_CCR register  ******************/
-#define  QUADSPI_CCR_INSTRUCTION                  0x000000FFU            /*!< INSTRUCTION[7:0]: Instruction    */
-#define  QUADSPI_CCR_INSTRUCTION_0                0x00000001U            /*!< Bit 0 */
-#define  QUADSPI_CCR_INSTRUCTION_1                0x00000002U            /*!< Bit 1 */
-#define  QUADSPI_CCR_INSTRUCTION_2                0x00000004U            /*!< Bit 2 */
-#define  QUADSPI_CCR_INSTRUCTION_3                0x00000008U            /*!< Bit 3 */
-#define  QUADSPI_CCR_INSTRUCTION_4                0x00000010U            /*!< Bit 4 */
-#define  QUADSPI_CCR_INSTRUCTION_5                0x00000020U            /*!< Bit 5 */
-#define  QUADSPI_CCR_INSTRUCTION_6                0x00000040U            /*!< Bit 6 */
-#define  QUADSPI_CCR_INSTRUCTION_7                0x00000080U            /*!< Bit 7 */
-#define  QUADSPI_CCR_IMODE                        0x00000300U            /*!< IMODE[1:0]: Instruction Mode      */
-#define  QUADSPI_CCR_IMODE_0                      0x00000100U            /*!< Bit 0 */
-#define  QUADSPI_CCR_IMODE_1                      0x00000200U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ADMODE                       0x00000C00U            /*!< ADMODE[1:0]: Address Mode         */
-#define  QUADSPI_CCR_ADMODE_0                     0x00000400U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ADMODE_1                     0x00000800U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ADSIZE                       0x00003000U            /*!< ADSIZE[1:0]: Address Size         */
-#define  QUADSPI_CCR_ADSIZE_0                     0x00001000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ADSIZE_1                     0x00002000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ABMODE                       0x0000C000U            /*!< ABMODE[1:0]: Alternate Bytes Mode */
-#define  QUADSPI_CCR_ABMODE_0                     0x00004000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ABMODE_1                     0x00008000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ABSIZE                       0x00030000U            /*!< ABSIZE[1:0]: Instruction Mode     */
-#define  QUADSPI_CCR_ABSIZE_0                     0x00010000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ABSIZE_1                     0x00020000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_DCYC                         0x007C0000U            /*!< DCYC[4:0]: Dummy Cycles           */
-#define  QUADSPI_CCR_DCYC_0                       0x00040000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_DCYC_1                       0x00080000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_DCYC_2                       0x00100000U            /*!< Bit 2 */
-#define  QUADSPI_CCR_DCYC_3                       0x00200000U            /*!< Bit 3 */
-#define  QUADSPI_CCR_DCYC_4                       0x00400000U            /*!< Bit 4 */
-#define  QUADSPI_CCR_DMODE                        0x03000000U            /*!< DMODE[1:0]: Data Mode              */
-#define  QUADSPI_CCR_DMODE_0                      0x01000000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_DMODE_1                      0x02000000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_FMODE                        0x0C000000U            /*!< FMODE[1:0]: Functional Mode        */
-#define  QUADSPI_CCR_FMODE_0                      0x04000000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_FMODE_1                      0x08000000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_SIOO                         0x10000000U            /*!< SIOO: Send Instruction Only Once Mode */
-#define  QUADSPI_CCR_DHHC                         0x40000000U            /*!< DHHC: Delay Half Hclk Cycle           */
-#define  QUADSPI_CCR_DDRM                         0x80000000U            /*!< DDRM: Double Data Rate Mode           */
-/******************  Bit definition for QUADSPI_AR register  *******************/
-#define  QUADSPI_AR_ADDRESS                       0xFFFFFFFFU            /*!< ADDRESS[31:0]: Address */
-
-/******************  Bit definition for QUADSPI_ABR register  ******************/
-#define  QUADSPI_ABR_ALTERNATE                    0xFFFFFFFFU            /*!< ALTERNATE[31:0]: Alternate Bytes */
-
-/******************  Bit definition for QUADSPI_DR register  *******************/
-#define  QUADSPI_DR_DATA                          0xFFFFFFFFU            /*!< DATA[31:0]: Data */
-
-/******************  Bit definition for QUADSPI_PSMKR register  ****************/
-#define  QUADSPI_PSMKR_MASK                       0xFFFFFFFFU            /*!< MASK[31:0]: Status Mask */
-
-/******************  Bit definition for QUADSPI_PSMAR register  ****************/
-#define  QUADSPI_PSMAR_MATCH                      0xFFFFFFFFU            /*!< MATCH[31:0]: Status Match */
-
-/******************  Bit definition for QUADSPI_PIR register  *****************/
-#define  QUADSPI_PIR_INTERVAL                     0x0000FFFFU            /*!< INTERVAL[15:0]: Polling Interval */
-
-/******************  Bit definition for QUADSPI_LPTR register  *****************/
-#define  QUADSPI_LPTR_TIMEOUT                     0x0000FFFFU            /*!< TIMEOUT[15:0]: Timeout period */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        0x00000001U
-#define  RCC_CR_HSIRDY                       0x00000002U
-#define  RCC_CR_HSITRIM                      0x000000F8U
-#define  RCC_CR_HSITRIM_0                    0x00000008U /*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    0x00000010U /*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    0x00000020U /*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    0x00000040U /*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    0x00000080U /*!<Bit 4 */
-#define  RCC_CR_HSICAL                       0x0000FF00U
-#define  RCC_CR_HSICAL_0                     0x00000100U /*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     0x00000200U /*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     0x00000400U /*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     0x00000800U /*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     0x00001000U /*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     0x00002000U /*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     0x00004000U /*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     0x00008000U /*!<Bit 7 */
-#define  RCC_CR_HSEON                        0x00010000U
-#define  RCC_CR_HSERDY                       0x00020000U
-#define  RCC_CR_HSEBYP                       0x00040000U
-#define  RCC_CR_CSSON                        0x00080000U
-#define  RCC_CR_PLLON                        0x01000000U
-#define  RCC_CR_PLLRDY                       0x02000000U
-#define  RCC_CR_PLLI2SON                     0x04000000U
-#define  RCC_CR_PLLI2SRDY                    0x08000000U
-#define  RCC_CR_PLLSAION                     0x10000000U
-#define  RCC_CR_PLLSAIRDY                    0x20000000U
-
-/********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    0x0000003FU
-#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
-#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
-#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
-#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
-#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
-#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
-#define  RCC_PLLCFGR_PLLN                    0x00007FC0U
-#define  RCC_PLLCFGR_PLLN_0                  0x00000040U
-#define  RCC_PLLCFGR_PLLN_1                  0x00000080U
-#define  RCC_PLLCFGR_PLLN_2                  0x00000100U
-#define  RCC_PLLCFGR_PLLN_3                  0x00000200U
-#define  RCC_PLLCFGR_PLLN_4                  0x00000400U
-#define  RCC_PLLCFGR_PLLN_5                  0x00000800U
-#define  RCC_PLLCFGR_PLLN_6                  0x00001000U
-#define  RCC_PLLCFGR_PLLN_7                  0x00002000U
-#define  RCC_PLLCFGR_PLLN_8                  0x00004000U
-#define  RCC_PLLCFGR_PLLP                    0x00030000U
-#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
-#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
-#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
-#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
-#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
-#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
-#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
-#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
-
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-/*!< SW configuration */
-#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
-#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
-#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
-
-#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
-
-/*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     0x001F0000U
-#define  RCC_CFGR_RTCPRE_0                   0x00010000U
-#define  RCC_CFGR_RTCPRE_1                   0x00020000U
-#define  RCC_CFGR_RTCPRE_2                   0x00040000U
-#define  RCC_CFGR_RTCPRE_3                   0x00080000U
-#define  RCC_CFGR_RTCPRE_4                   0x00100000U
-
-/*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       0x00600000U
-#define  RCC_CFGR_MCO1_0                     0x00200000U
-#define  RCC_CFGR_MCO1_1                     0x00400000U
-
-#define  RCC_CFGR_I2SSRC                     0x00800000U
-
-#define  RCC_CFGR_MCO1PRE                    0x07000000U
-#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
-#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
-#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
-
-#define  RCC_CFGR_MCO2PRE                    0x38000000U
-#define  RCC_CFGR_MCO2PRE_0                  0x08000000U
-#define  RCC_CFGR_MCO2PRE_1                  0x10000000U
-#define  RCC_CFGR_MCO2PRE_2                  0x20000000U
-
-#define  RCC_CFGR_MCO2                       0xC0000000U
-#define  RCC_CFGR_MCO2_0                     0x40000000U
-#define  RCC_CFGR_MCO2_1                     0x80000000U
-
-/********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     0x00000001U
-#define  RCC_CIR_LSERDYF                     0x00000002U
-#define  RCC_CIR_HSIRDYF                     0x00000004U
-#define  RCC_CIR_HSERDYF                     0x00000008U
-#define  RCC_CIR_PLLRDYF                     0x00000010U
-#define  RCC_CIR_PLLI2SRDYF                  0x00000020U
-#define  RCC_CIR_PLLSAIRDYF                  0x00000040U
-#define  RCC_CIR_CSSF                        0x00000080U
-#define  RCC_CIR_LSIRDYIE                    0x00000100U
-#define  RCC_CIR_LSERDYIE                    0x00000200U
-#define  RCC_CIR_HSIRDYIE                    0x00000400U
-#define  RCC_CIR_HSERDYIE                    0x00000800U
-#define  RCC_CIR_PLLRDYIE                    0x00001000U
-#define  RCC_CIR_PLLI2SRDYIE                 0x00002000U
-#define  RCC_CIR_PLLSAIRDYIE                 0x00004000U
-#define  RCC_CIR_LSIRDYC                     0x00010000U
-#define  RCC_CIR_LSERDYC                     0x00020000U
-#define  RCC_CIR_HSIRDYC                     0x00040000U
-#define  RCC_CIR_HSERDYC                     0x00080000U
-#define  RCC_CIR_PLLRDYC                     0x00100000U
-#define  RCC_CIR_PLLI2SRDYC                  0x00200000U
-#define  RCC_CIR_PLLSAIRDYC                  0x00400000U
-#define  RCC_CIR_CSSC                        0x00800000U
-
-/********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
-#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
-#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
-#define  RCC_AHB1RSTR_GPIODRST               0x00000008U
-#define  RCC_AHB1RSTR_GPIOERST               0x00000010U
-#define  RCC_AHB1RSTR_GPIOFRST               0x00000020U
-#define  RCC_AHB1RSTR_GPIOGRST               0x00000040U
-#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
-#define  RCC_AHB1RSTR_GPIOIRST               0x00000100U
-#define  RCC_AHB1RSTR_GPIOJRST               0x00000200U
-#define  RCC_AHB1RSTR_GPIOKRST               0x00000400U
-#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
-#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
-#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
-#define  RCC_AHB1RSTR_DMA2DRST               0x00800000U
-#define  RCC_AHB1RSTR_ETHMACRST              0x02000000U
-#define  RCC_AHB1RSTR_OTGHRST                0x20000000U
-
-/********************  Bit definition for RCC_AHB2RSTR register  **************/
-#define  RCC_AHB2RSTR_DCMIRST                0x00000001U
-#define  RCC_AHB2RSTR_CRYPRST                0x00000010U
-#define  RCC_AHB2RSTR_HASHRST                0x00000020U
-#define  RCC_AHB2RSTR_RNGRST                 0x00000040U
-#define  RCC_AHB2RSTR_OTGFSRST               0x00000080U
-
-/********************  Bit definition for RCC_AHB3RSTR register  **************/
-
-#define  RCC_AHB3RSTR_FMCRST                 0x00000001U
-#define  RCC_AHB3RSTR_QSPIRST                0x00000002U
-
-/********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM2RST                0x00000001U
-#define  RCC_APB1RSTR_TIM3RST                0x00000002U
-#define  RCC_APB1RSTR_TIM4RST                0x00000004U
-#define  RCC_APB1RSTR_TIM5RST                0x00000008U
-#define  RCC_APB1RSTR_TIM6RST                0x00000010U
-#define  RCC_APB1RSTR_TIM7RST                0x00000020U
-#define  RCC_APB1RSTR_TIM12RST               0x00000040U
-#define  RCC_APB1RSTR_TIM13RST               0x00000080U
-#define  RCC_APB1RSTR_TIM14RST               0x00000100U
-#define  RCC_APB1RSTR_LPTIM1RST              0x00000200U
-#define  RCC_APB1RSTR_WWDGRST                0x00000800U
-#define  RCC_APB1RSTR_SPI2RST                0x00004000U
-#define  RCC_APB1RSTR_SPI3RST                0x00008000U
-#define  RCC_APB1RSTR_SPDIFRXRST             0x00010000U
-#define  RCC_APB1RSTR_USART2RST              0x00020000U
-#define  RCC_APB1RSTR_USART3RST              0x00040000U
-#define  RCC_APB1RSTR_UART4RST               0x00080000U
-#define  RCC_APB1RSTR_UART5RST               0x00100000U
-#define  RCC_APB1RSTR_I2C1RST                0x00200000U
-#define  RCC_APB1RSTR_I2C2RST                0x00400000U
-#define  RCC_APB1RSTR_I2C3RST                0x00800000U
-#define  RCC_APB1RSTR_I2C4RST                0x01000000U
-#define  RCC_APB1RSTR_CAN1RST                0x02000000U
-#define  RCC_APB1RSTR_CAN2RST                0x04000000U
-#define  RCC_APB1RSTR_CECRST                 0x08000000U
-#define  RCC_APB1RSTR_PWRRST                 0x10000000U
-#define  RCC_APB1RSTR_DACRST                 0x20000000U
-#define  RCC_APB1RSTR_UART7RST               0x40000000U
-#define  RCC_APB1RSTR_UART8RST               0x80000000U
-
-/********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                0x00000001U
-#define  RCC_APB2RSTR_TIM8RST                0x00000002U
-#define  RCC_APB2RSTR_USART1RST              0x00000010U
-#define  RCC_APB2RSTR_USART6RST              0x00000020U
-#define  RCC_APB2RSTR_ADCRST                 0x00000100U
-#define  RCC_APB2RSTR_SDMMC1RST              0x00000800U
-#define  RCC_APB2RSTR_SPI1RST                0x00001000U
-#define  RCC_APB2RSTR_SPI4RST                0x00002000U
-#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
-#define  RCC_APB2RSTR_TIM9RST                0x00010000U
-#define  RCC_APB2RSTR_TIM10RST               0x00020000U
-#define  RCC_APB2RSTR_TIM11RST               0x00040000U
-#define  RCC_APB2RSTR_SPI5RST                0x00100000U
-#define  RCC_APB2RSTR_SPI6RST                0x00200000U
-#define  RCC_APB2RSTR_SAI1RST                0x00400000U
-#define  RCC_APB2RSTR_SAI2RST                0x00800000U
-#define  RCC_APB2RSTR_LTDCRST                0x04000000U
-
-/********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
-#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
-#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
-#define  RCC_AHB1ENR_GPIODEN                 0x00000008U
-#define  RCC_AHB1ENR_GPIOEEN                 0x00000010U
-#define  RCC_AHB1ENR_GPIOFEN                 0x00000020U
-#define  RCC_AHB1ENR_GPIOGEN                 0x00000040U
-#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
-#define  RCC_AHB1ENR_GPIOIEN                 0x00000100U
-#define  RCC_AHB1ENR_GPIOJEN                 0x00000200U
-#define  RCC_AHB1ENR_GPIOKEN                 0x00000400U
-#define  RCC_AHB1ENR_CRCEN                   0x00001000U
-#define  RCC_AHB1ENR_BKPSRAMEN               0x00040000U
-#define  RCC_AHB1ENR_DTCMRAMEN               0x00100000U
-#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
-#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
-#define  RCC_AHB1ENR_DMA2DEN                 0x00800000U
-#define  RCC_AHB1ENR_ETHMACEN                0x02000000U
-#define  RCC_AHB1ENR_ETHMACTXEN              0x04000000U
-#define  RCC_AHB1ENR_ETHMACRXEN              0x08000000U
-#define  RCC_AHB1ENR_ETHMACPTPEN             0x10000000U
-#define  RCC_AHB1ENR_OTGHSEN                 0x20000000U
-#define  RCC_AHB1ENR_OTGHSULPIEN             0x40000000U
-
-/********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define  RCC_AHB2ENR_DCMIEN                  0x00000001U
-#define  RCC_AHB2ENR_CRYPEN                  0x00000010U
-#define  RCC_AHB2ENR_HASHEN                  0x00000020U
-#define  RCC_AHB2ENR_RNGEN                   0x00000040U
-#define  RCC_AHB2ENR_OTGFSEN                 0x00000080U
-
-/********************  Bit definition for RCC_AHB3ENR register  ***************/
-#define  RCC_AHB3ENR_FMCEN                  0x00000001U
-#define  RCC_AHB3ENR_QSPIEN                 0x00000002U
-
-/********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM2EN                  0x00000001U
-#define  RCC_APB1ENR_TIM3EN                  0x00000002U
-#define  RCC_APB1ENR_TIM4EN                  0x00000004U
-#define  RCC_APB1ENR_TIM5EN                  0x00000008U
-#define  RCC_APB1ENR_TIM6EN                  0x00000010U
-#define  RCC_APB1ENR_TIM7EN                  0x00000020U
-#define  RCC_APB1ENR_TIM12EN                 0x00000040U
-#define  RCC_APB1ENR_TIM13EN                 0x00000080U
-#define  RCC_APB1ENR_TIM14EN                 0x00000100U
-#define  RCC_APB1ENR_LPTIM1EN                0x00000200U
-#define  RCC_APB1ENR_WWDGEN                  0x00000800U
-#define  RCC_APB1ENR_SPI2EN                  0x00004000U
-#define  RCC_APB1ENR_SPI3EN                  0x00008000U
-#define  RCC_APB1ENR_SPDIFRXEN               0x00010000U
-#define  RCC_APB1ENR_USART2EN                0x00020000U
-#define  RCC_APB1ENR_USART3EN                0x00040000U
-#define  RCC_APB1ENR_UART4EN                 0x00080000U
-#define  RCC_APB1ENR_UART5EN                 0x00100000U
-#define  RCC_APB1ENR_I2C1EN                  0x00200000U
-#define  RCC_APB1ENR_I2C2EN                  0x00400000U
-#define  RCC_APB1ENR_I2C3EN                  0x00800000U
-#define  RCC_APB1ENR_I2C4EN                  0x01000000U
-#define  RCC_APB1ENR_CAN1EN                  0x02000000U
-#define  RCC_APB1ENR_CAN2EN                  0x04000000U
-#define  RCC_APB1ENR_CECEN                   0x08000000U
-#define  RCC_APB1ENR_PWREN                   0x10000000U
-#define  RCC_APB1ENR_DACEN                   0x20000000U
-#define  RCC_APB1ENR_UART7EN                 0x40000000U
-#define  RCC_APB1ENR_UART8EN                 0x80000000U
-
-/********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  0x00000001U
-#define  RCC_APB2ENR_TIM8EN                  0x00000002U
-#define  RCC_APB2ENR_USART1EN                0x00000010U
-#define  RCC_APB2ENR_USART6EN                0x00000020U
-#define  RCC_APB2ENR_ADC1EN                  0x00000100U
-#define  RCC_APB2ENR_ADC2EN                  0x00000200U
-#define  RCC_APB2ENR_ADC3EN                  0x00000400U
-#define  RCC_APB2ENR_SDMMC1EN                0x00000800U
-#define  RCC_APB2ENR_SPI1EN                  0x00001000U
-#define  RCC_APB2ENR_SPI4EN                  0x00002000U
-#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
-#define  RCC_APB2ENR_TIM9EN                  0x00010000U
-#define  RCC_APB2ENR_TIM10EN                 0x00020000U
-#define  RCC_APB2ENR_TIM11EN                 0x00040000U
-#define  RCC_APB2ENR_SPI5EN                  0x00100000U
-#define  RCC_APB2ENR_SPI6EN                  0x00200000U
-#define  RCC_APB2ENR_SAI1EN                  0x00400000U
-#define  RCC_APB2ENR_SAI2EN                  0x00800000U
-#define  RCC_APB2ENR_LTDCEN                  0x04000000U
-
-/********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
-#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
-#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
-#define  RCC_AHB1LPENR_GPIODLPEN             0x00000008U
-#define  RCC_AHB1LPENR_GPIOELPEN             0x00000010U
-#define  RCC_AHB1LPENR_GPIOFLPEN             0x00000020U
-#define  RCC_AHB1LPENR_GPIOGLPEN             0x00000040U
-#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
-#define  RCC_AHB1LPENR_GPIOILPEN             0x00000100U
-#define  RCC_AHB1LPENR_GPIOJLPEN             0x00000200U
-#define  RCC_AHB1LPENR_GPIOKLPEN             0x00000400U
-#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
-#define  RCC_AHB1LPENR_AXILPEN               0x00002000U
-#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
-#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
-#define  RCC_AHB1LPENR_SRAM2LPEN             0x00020000U
-#define  RCC_AHB1LPENR_BKPSRAMLPEN           0x00040000U
-#define  RCC_AHB1LPENR_DTCMLPEN              0x00100000U
-#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
-#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
-#define  RCC_AHB1LPENR_DMA2DLPEN             0x00800000U
-#define  RCC_AHB1LPENR_ETHMACLPEN            0x02000000U
-#define  RCC_AHB1LPENR_ETHMACTXLPEN          0x04000000U
-#define  RCC_AHB1LPENR_ETHMACRXLPEN          0x08000000U
-#define  RCC_AHB1LPENR_ETHMACPTPLPEN         0x10000000U
-#define  RCC_AHB1LPENR_OTGHSLPEN             0x20000000U
-#define  RCC_AHB1LPENR_OTGHSULPILPEN         0x40000000U
-
-/********************  Bit definition for RCC_AHB2LPENR register  *************/
-#define  RCC_AHB2LPENR_DCMILPEN              0x00000001U
-#define  RCC_AHB2LPENR_CRYPLPEN              0x00000010U
-#define  RCC_AHB2LPENR_HASHLPEN              0x00000020U
-#define  RCC_AHB2LPENR_RNGLPEN               0x00000040U
-#define  RCC_AHB2LPENR_OTGFSLPEN             0x00000080U
-
-/********************  Bit definition for RCC_AHB3LPENR register  *************/
-#define  RCC_AHB3LPENR_FMCLPEN               0x00000001U
-#define  RCC_AHB3LPENR_QSPILPEN              0x00000002U
-/********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM2LPEN              0x00000001U
-#define  RCC_APB1LPENR_TIM3LPEN              0x00000002U
-#define  RCC_APB1LPENR_TIM4LPEN              0x00000004U
-#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
-#define  RCC_APB1LPENR_TIM6LPEN              0x00000010U
-#define  RCC_APB1LPENR_TIM7LPEN              0x00000020U
-#define  RCC_APB1LPENR_TIM12LPEN             0x00000040U
-#define  RCC_APB1LPENR_TIM13LPEN             0x00000080U
-#define  RCC_APB1LPENR_TIM14LPEN             0x00000100U
-#define  RCC_APB1LPENR_LPTIM1LPEN            0x00000200U
-#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
-#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U
-#define  RCC_APB1LPENR_SPI3LPEN              0x00008000U
-#define  RCC_APB1LPENR_SPDIFRXLPEN           0x00010000U
-#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
-#define  RCC_APB1LPENR_USART3LPEN            0x00040000U
-#define  RCC_APB1LPENR_UART4LPEN             0x00080000U
-#define  RCC_APB1LPENR_UART5LPEN             0x00100000U
-#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
-#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
-#define  RCC_APB1LPENR_I2C3LPEN              0x00800000U
-#define  RCC_APB1LPENR_I2C4LPEN              0x01000000U
-#define  RCC_APB1LPENR_CAN1LPEN              0x02000000U
-#define  RCC_APB1LPENR_CAN2LPEN              0x04000000U
-#define  RCC_APB1LPENR_CECLPEN               0x08000000U
-#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
-#define  RCC_APB1LPENR_DACLPEN               0x20000000U
-#define  RCC_APB1LPENR_UART7LPEN             0x40000000U
-#define  RCC_APB1LPENR_UART8LPEN             0x80000000U
-
-/********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
-#define  RCC_APB2LPENR_TIM8LPEN              0x00000002U
-#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
-#define  RCC_APB2LPENR_USART6LPEN            0x00000020U
-#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
-#define  RCC_APB2LPENR_ADC2LPEN              0x00000200U
-#define  RCC_APB2LPENR_ADC3LPEN              0x00000400U
-#define  RCC_APB2LPENR_SDMMC1LPEN            0x00000800U
-#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
-#define  RCC_APB2LPENR_SPI4LPEN              0x00002000U
-#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
-#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
-#define  RCC_APB2LPENR_TIM10LPEN             0x00020000U
-#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
-#define  RCC_APB2LPENR_SPI5LPEN              0x00100000U
-#define  RCC_APB2LPENR_SPI6LPEN              0x00200000U
-#define  RCC_APB2LPENR_SAI1LPEN              0x00400000U
-#define  RCC_APB2LPENR_SAI2LPEN              0x00800000U
-#define  RCC_APB2LPENR_LTDCLPEN              0x04000000U
-
-/********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      0x00000001U
-#define  RCC_BDCR_LSERDY                     0x00000002U
-#define  RCC_BDCR_LSEBYP                     0x00000004U
-#define  RCC_BDCR_LSEDRV                     0x00000018U
-#define  RCC_BDCR_LSEDRV_0                   0x00000008U
-#define  RCC_BDCR_LSEDRV_1                   0x00000010U
-#define  RCC_BDCR_RTCSEL                     0x00000300U
-#define  RCC_BDCR_RTCSEL_0                   0x00000100U
-#define  RCC_BDCR_RTCSEL_1                   0x00000200U
-#define  RCC_BDCR_RTCEN                      0x00008000U
-#define  RCC_BDCR_BDRST                      0x00010000U
-
-/********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       0x00000001U
-#define  RCC_CSR_LSIRDY                      0x00000002U
-#define  RCC_CSR_RMVF                        0x01000000U
-#define  RCC_CSR_BORRSTF                     0x02000000U
-#define  RCC_CSR_PINRSTF                     0x04000000U
-#define  RCC_CSR_PORRSTF                     0x08000000U
-#define  RCC_CSR_SFTRSTF                     0x10000000U
-#define  RCC_CSR_IWDGRSTF                    0x20000000U
-#define  RCC_CSR_WWDGRSTF                    0x40000000U
-#define  RCC_CSR_LPWRRSTF                    0x80000000U
-
-/********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    0x00001FFFU
-#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
-#define  RCC_SSCGR_SPREADSEL                 0x40000000U
-#define  RCC_SSCGR_SSCGEN                    0x80000000U
-
-/********************  Bit definition for RCC_PLLI2SCFGR register  ************/
-#define  RCC_PLLI2SCFGR_PLLI2SN              0x00007FC0U
-#define  RCC_PLLI2SCFGR_PLLI2SN_0            0x00000040U
-#define  RCC_PLLI2SCFGR_PLLI2SN_1            0x00000080U
-#define  RCC_PLLI2SCFGR_PLLI2SN_2            0x00000100U
-#define  RCC_PLLI2SCFGR_PLLI2SN_3            0x00000200U
-#define  RCC_PLLI2SCFGR_PLLI2SN_4            0x00000400U
-#define  RCC_PLLI2SCFGR_PLLI2SN_5            0x00000800U
-#define  RCC_PLLI2SCFGR_PLLI2SN_6            0x00001000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_7            0x00002000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_8            0x00004000U
-#define  RCC_PLLI2SCFGR_PLLI2SP              0x00030000U
-#define  RCC_PLLI2SCFGR_PLLI2SP_0            0x00010000U
-#define  RCC_PLLI2SCFGR_PLLI2SP_1            0x00020000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ              0x0F000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_0            0x01000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_1            0x02000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_2            0x04000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_3            0x08000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR              0x70000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_0            0x10000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_1            0x20000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_2            0x40000000U
-
-/********************  Bit definition for RCC_PLLSAICFGR register  ************/
-#define  RCC_PLLSAICFGR_PLLSAIN              0x00007FC0U
-#define  RCC_PLLSAICFGR_PLLSAIN_0            0x00000040U
-#define  RCC_PLLSAICFGR_PLLSAIN_1            0x00000080U
-#define  RCC_PLLSAICFGR_PLLSAIN_2            0x00000100U
-#define  RCC_PLLSAICFGR_PLLSAIN_3            0x00000200U
-#define  RCC_PLLSAICFGR_PLLSAIN_4            0x00000400U
-#define  RCC_PLLSAICFGR_PLLSAIN_5            0x00000800U
-#define  RCC_PLLSAICFGR_PLLSAIN_6            0x00001000U
-#define  RCC_PLLSAICFGR_PLLSAIN_7            0x00002000U
-#define  RCC_PLLSAICFGR_PLLSAIN_8            0x00004000U
-#define  RCC_PLLSAICFGR_PLLSAIP              0x00030000U
-#define  RCC_PLLSAICFGR_PLLSAIP_0            0x00010000U
-#define  RCC_PLLSAICFGR_PLLSAIP_1            0x00020000U
-#define  RCC_PLLSAICFGR_PLLSAIQ              0x0F000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_0            0x01000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_1            0x02000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_2            0x04000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_3            0x08000000U
-#define  RCC_PLLSAICFGR_PLLSAIR              0x70000000U
-#define  RCC_PLLSAICFGR_PLLSAIR_0            0x10000000U
-#define  RCC_PLLSAICFGR_PLLSAIR_1            0x20000000U
-#define  RCC_PLLSAICFGR_PLLSAIR_2            0x40000000U
-
-/********************  Bit definition for RCC_DCKCFGR1 register  ***************/
-#define  RCC_DCKCFGR1_PLLI2SDIVQ             0x0000001FU
-#define  RCC_DCKCFGR1_PLLI2SDIVQ_0           0x00000001U
-#define  RCC_DCKCFGR1_PLLI2SDIVQ_1           0x00000002U
-#define  RCC_DCKCFGR1_PLLI2SDIVQ_2           0x00000004U
-#define  RCC_DCKCFGR1_PLLI2SDIVQ_3           0x00000008U
-#define  RCC_DCKCFGR1_PLLI2SDIVQ_4           0x00000010U
-
-#define  RCC_DCKCFGR1_PLLSAIDIVQ             0x00001F00U
-#define  RCC_DCKCFGR1_PLLSAIDIVQ_0           0x00000100U
-#define  RCC_DCKCFGR1_PLLSAIDIVQ_1           0x00000200U
-#define  RCC_DCKCFGR1_PLLSAIDIVQ_2           0x00000400U
-#define  RCC_DCKCFGR1_PLLSAIDIVQ_3           0x00000800U
-#define  RCC_DCKCFGR1_PLLSAIDIVQ_4           0x00001000U
-
-#define  RCC_DCKCFGR1_PLLSAIDIVR             0x00030000U
-#define  RCC_DCKCFGR1_PLLSAIDIVR_0           0x00010000U
-#define  RCC_DCKCFGR1_PLLSAIDIVR_1           0x00020000U
-
-#define  RCC_DCKCFGR1_SAI1SEL                0x00300000U
-#define  RCC_DCKCFGR1_SAI1SEL_0              0x00100000U
-#define  RCC_DCKCFGR1_SAI1SEL_1              0x00200000U
-
-#define  RCC_DCKCFGR1_SAI2SEL                0x00C00000U
-#define  RCC_DCKCFGR1_SAI2SEL_0              0x00400000U
-#define  RCC_DCKCFGR1_SAI2SEL_1              0x00800000U
-
-#define  RCC_DCKCFGR1_TIMPRE                 0x01000000U
-
-/********************  Bit definition for RCC_DCKCFGR2 register  ***************/
-#define  RCC_DCKCFGR2_USART1SEL              0x00000003U
-#define  RCC_DCKCFGR2_USART1SEL_0            0x00000001U
-#define  RCC_DCKCFGR2_USART1SEL_1            0x00000002U
-#define  RCC_DCKCFGR2_USART2SEL              0x0000000CU
-#define  RCC_DCKCFGR2_USART2SEL_0            0x00000004U
-#define  RCC_DCKCFGR2_USART2SEL_1            0x00000008U
-#define  RCC_DCKCFGR2_USART3SEL              0x00000030U
-#define  RCC_DCKCFGR2_USART3SEL_0            0x00000010U
-#define  RCC_DCKCFGR2_USART3SEL_1            0x00000020U
-#define  RCC_DCKCFGR2_UART4SEL               0x000000C0U
-#define  RCC_DCKCFGR2_UART4SEL_0             0x00000040U
-#define  RCC_DCKCFGR2_UART4SEL_1             0x00000080U
-#define  RCC_DCKCFGR2_UART5SEL               0x00000300U
-#define  RCC_DCKCFGR2_UART5SEL_0             0x00000100U
-#define  RCC_DCKCFGR2_UART5SEL_1             0x00000200U
-#define  RCC_DCKCFGR2_USART6SEL              0x00000C00U
-#define  RCC_DCKCFGR2_USART6SEL_0            0x00000400U
-#define  RCC_DCKCFGR2_USART6SEL_1            0x00000800U
-#define  RCC_DCKCFGR2_UART7SEL               0x00003000U
-#define  RCC_DCKCFGR2_UART7SEL_0             0x00001000U
-#define  RCC_DCKCFGR2_UART7SEL_1             0x00002000U
-#define  RCC_DCKCFGR2_UART8SEL               0x0000C000U
-#define  RCC_DCKCFGR2_UART8SEL_0             0x00004000U
-#define  RCC_DCKCFGR2_UART8SEL_1             0x00008000U
-#define  RCC_DCKCFGR2_I2C1SEL                0x00030000U
-#define  RCC_DCKCFGR2_I2C1SEL_0              0x00010000U
-#define  RCC_DCKCFGR2_I2C1SEL_1              0x00020000U
-#define  RCC_DCKCFGR2_I2C2SEL                0x000C0000U
-#define  RCC_DCKCFGR2_I2C2SEL_0              0x00040000U
-#define  RCC_DCKCFGR2_I2C2SEL_1              0x00080000U
-#define  RCC_DCKCFGR2_I2C3SEL                0x00300000U
-#define  RCC_DCKCFGR2_I2C3SEL_0              0x00100000U
-#define  RCC_DCKCFGR2_I2C3SEL_1              0x00200000U
-#define  RCC_DCKCFGR2_I2C4SEL                0x00C00000U
-#define  RCC_DCKCFGR2_I2C4SEL_0              0x00400000U
-#define  RCC_DCKCFGR2_I2C4SEL_1              0x00800000U
-#define  RCC_DCKCFGR2_LPTIM1SEL              0x03000000U
-#define  RCC_DCKCFGR2_LPTIM1SEL_0            0x01000000U
-#define  RCC_DCKCFGR2_LPTIM1SEL_1            0x02000000U
-#define  RCC_DCKCFGR2_CECSEL                 0x04000000U
-#define  RCC_DCKCFGR2_CK48MSEL               0x08000000U
-#define  RCC_DCKCFGR2_SDMMC1SEL              0x10000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    RNG                                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN                         0x00000004U
-#define RNG_CR_IE                            0x00000008U
-
-/********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY                          0x00000001U
-#define RNG_SR_CECS                          0x00000002U
-#define RNG_SR_SECS                          0x00000004U
-#define RNG_SR_CEIS                          0x00000020U
-#define RNG_SR_SEIS                          0x00000040U
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            0x00400000U
-#define RTC_TR_HT                            0x00300000U
-#define RTC_TR_HT_0                          0x00100000U
-#define RTC_TR_HT_1                          0x00200000U
-#define RTC_TR_HU                            0x000F0000U
-#define RTC_TR_HU_0                          0x00010000U
-#define RTC_TR_HU_1                          0x00020000U
-#define RTC_TR_HU_2                          0x00040000U
-#define RTC_TR_HU_3                          0x00080000U
-#define RTC_TR_MNT                           0x00007000U
-#define RTC_TR_MNT_0                         0x00001000U
-#define RTC_TR_MNT_1                         0x00002000U
-#define RTC_TR_MNT_2                         0x00004000U
-#define RTC_TR_MNU                           0x00000F00U
-#define RTC_TR_MNU_0                         0x00000100U
-#define RTC_TR_MNU_1                         0x00000200U
-#define RTC_TR_MNU_2                         0x00000400U
-#define RTC_TR_MNU_3                         0x00000800U
-#define RTC_TR_ST                            0x00000070U
-#define RTC_TR_ST_0                          0x00000010U
-#define RTC_TR_ST_1                          0x00000020U
-#define RTC_TR_ST_2                          0x00000040U
-#define RTC_TR_SU                            0x0000000FU
-#define RTC_TR_SU_0                          0x00000001U
-#define RTC_TR_SU_1                          0x00000002U
-#define RTC_TR_SU_2                          0x00000004U
-#define RTC_TR_SU_3                          0x00000008U
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            0x00F00000U
-#define RTC_DR_YT_0                          0x00100000U
-#define RTC_DR_YT_1                          0x00200000U
-#define RTC_DR_YT_2                          0x00400000U
-#define RTC_DR_YT_3                          0x00800000U
-#define RTC_DR_YU                            0x000F0000U
-#define RTC_DR_YU_0                          0x00010000U
-#define RTC_DR_YU_1                          0x00020000U
-#define RTC_DR_YU_2                          0x00040000U
-#define RTC_DR_YU_3                          0x00080000U
-#define RTC_DR_WDU                           0x0000E000U
-#define RTC_DR_WDU_0                         0x00002000U
-#define RTC_DR_WDU_1                         0x00004000U
-#define RTC_DR_WDU_2                         0x00008000U
-#define RTC_DR_MT                            0x00001000U
-#define RTC_DR_MU                            0x00000F00U
-#define RTC_DR_MU_0                          0x00000100U
-#define RTC_DR_MU_1                          0x00000200U
-#define RTC_DR_MU_2                          0x00000400U
-#define RTC_DR_MU_3                          0x00000800U
-#define RTC_DR_DT                            0x00000030U
-#define RTC_DR_DT_0                          0x00000010U
-#define RTC_DR_DT_1                          0x00000020U
-#define RTC_DR_DU                            0x0000000FU
-#define RTC_DR_DU_0                          0x00000001U
-#define RTC_DR_DU_1                          0x00000002U
-#define RTC_DR_DU_2                          0x00000004U
-#define RTC_DR_DU_3                          0x00000008U
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_ITSE                          0x01000000U
-#define RTC_CR_COE                           0x00800000U
-#define RTC_CR_OSEL                          0x00600000U
-#define RTC_CR_OSEL_0                        0x00200000U
-#define RTC_CR_OSEL_1                        0x00400000U
-#define RTC_CR_POL                           0x00100000U
-#define RTC_CR_COSEL                         0x00080000U
-#define RTC_CR_BKP                           0x00040000U
-#define RTC_CR_SUB1H                         0x00020000U
-#define RTC_CR_ADD1H                         0x00010000U
-#define RTC_CR_TSIE                          0x00008000U
-#define RTC_CR_WUTIE                         0x00004000U
-#define RTC_CR_ALRBIE                        0x00002000U
-#define RTC_CR_ALRAIE                        0x00001000U
-#define RTC_CR_TSE                           0x00000800U
-#define RTC_CR_WUTE                          0x00000400U
-#define RTC_CR_ALRBE                         0x00000200U
-#define RTC_CR_ALRAE                         0x00000100U
-#define RTC_CR_FMT                           0x00000040U
-#define RTC_CR_BYPSHAD                       0x00000020U
-#define RTC_CR_REFCKON                       0x00000010U
-#define RTC_CR_TSEDGE                        0x00000008U
-#define RTC_CR_WUCKSEL                       0x00000007U
-#define RTC_CR_WUCKSEL_0                     0x00000001U
-#define RTC_CR_WUCKSEL_1                     0x00000002U
-#define RTC_CR_WUCKSEL_2                     0x00000004U
-
-/* Legacy define */
-#define RTC_CR_BCK                           RTC_CR_BKP
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_ITSF                         0x00020000U
-#define RTC_ISR_RECALPF                      0x00010000U
-#define RTC_ISR_TAMP3F                       0x00008000U
-#define RTC_ISR_TAMP2F                       0x00004000U
-#define RTC_ISR_TAMP1F                       0x00002000U
-#define RTC_ISR_TSOVF                        0x00001000U
-#define RTC_ISR_TSF                          0x00000800U
-#define RTC_ISR_WUTF                         0x00000400U
-#define RTC_ISR_ALRBF                        0x00000200U
-#define RTC_ISR_ALRAF                        0x00000100U
-#define RTC_ISR_INIT                         0x00000080U
-#define RTC_ISR_INITF                        0x00000040U
-#define RTC_ISR_RSF                          0x00000020U
-#define RTC_ISR_INITS                        0x00000010U
-#define RTC_ISR_SHPF                         0x00000008U
-#define RTC_ISR_WUTWF                        0x00000004U
-#define RTC_ISR_ALRBWF                       0x00000002U
-#define RTC_ISR_ALRAWF                       0x00000001U
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    0x007F0000U
-#define RTC_PRER_PREDIV_S                    0x00007FFFU
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         0x0000FFFFU
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      0x80000000U
-#define RTC_ALRMAR_WDSEL                     0x40000000U
-#define RTC_ALRMAR_DT                        0x30000000U
-#define RTC_ALRMAR_DT_0                      0x10000000U
-#define RTC_ALRMAR_DT_1                      0x20000000U
-#define RTC_ALRMAR_DU                        0x0F000000U
-#define RTC_ALRMAR_DU_0                      0x01000000U
-#define RTC_ALRMAR_DU_1                      0x02000000U
-#define RTC_ALRMAR_DU_2                      0x04000000U
-#define RTC_ALRMAR_DU_3                      0x08000000U
-#define RTC_ALRMAR_MSK3                      0x00800000U
-#define RTC_ALRMAR_PM                        0x00400000U
-#define RTC_ALRMAR_HT                        0x00300000U
-#define RTC_ALRMAR_HT_0                      0x00100000U
-#define RTC_ALRMAR_HT_1                      0x00200000U
-#define RTC_ALRMAR_HU                        0x000F0000U
-#define RTC_ALRMAR_HU_0                      0x00010000U
-#define RTC_ALRMAR_HU_1                      0x00020000U
-#define RTC_ALRMAR_HU_2                      0x00040000U
-#define RTC_ALRMAR_HU_3                      0x00080000U
-#define RTC_ALRMAR_MSK2                      0x00008000U
-#define RTC_ALRMAR_MNT                       0x00007000U
-#define RTC_ALRMAR_MNT_0                     0x00001000U
-#define RTC_ALRMAR_MNT_1                     0x00002000U
-#define RTC_ALRMAR_MNT_2                     0x00004000U
-#define RTC_ALRMAR_MNU                       0x00000F00U
-#define RTC_ALRMAR_MNU_0                     0x00000100U
-#define RTC_ALRMAR_MNU_1                     0x00000200U
-#define RTC_ALRMAR_MNU_2                     0x00000400U
-#define RTC_ALRMAR_MNU_3                     0x00000800U
-#define RTC_ALRMAR_MSK1                      0x00000080U
-#define RTC_ALRMAR_ST                        0x00000070U
-#define RTC_ALRMAR_ST_0                      0x00000010U
-#define RTC_ALRMAR_ST_1                      0x00000020U
-#define RTC_ALRMAR_ST_2                      0x00000040U
-#define RTC_ALRMAR_SU                        0x0000000FU
-#define RTC_ALRMAR_SU_0                      0x00000001U
-#define RTC_ALRMAR_SU_1                      0x00000002U
-#define RTC_ALRMAR_SU_2                      0x00000004U
-#define RTC_ALRMAR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      0x80000000U
-#define RTC_ALRMBR_WDSEL                     0x40000000U
-#define RTC_ALRMBR_DT                        0x30000000U
-#define RTC_ALRMBR_DT_0                      0x10000000U
-#define RTC_ALRMBR_DT_1                      0x20000000U
-#define RTC_ALRMBR_DU                        0x0F000000U
-#define RTC_ALRMBR_DU_0                      0x01000000U
-#define RTC_ALRMBR_DU_1                      0x02000000U
-#define RTC_ALRMBR_DU_2                      0x04000000U
-#define RTC_ALRMBR_DU_3                      0x08000000U
-#define RTC_ALRMBR_MSK3                      0x00800000U
-#define RTC_ALRMBR_PM                        0x00400000U
-#define RTC_ALRMBR_HT                        0x00300000U
-#define RTC_ALRMBR_HT_0                      0x00100000U
-#define RTC_ALRMBR_HT_1                      0x00200000U
-#define RTC_ALRMBR_HU                        0x000F0000U
-#define RTC_ALRMBR_HU_0                      0x00010000U
-#define RTC_ALRMBR_HU_1                      0x00020000U
-#define RTC_ALRMBR_HU_2                      0x00040000U
-#define RTC_ALRMBR_HU_3                      0x00080000U
-#define RTC_ALRMBR_MSK2                      0x00008000U
-#define RTC_ALRMBR_MNT                       0x00007000U
-#define RTC_ALRMBR_MNT_0                     0x00001000U
-#define RTC_ALRMBR_MNT_1                     0x00002000U
-#define RTC_ALRMBR_MNT_2                     0x00004000U
-#define RTC_ALRMBR_MNU                       0x00000F00U
-#define RTC_ALRMBR_MNU_0                     0x00000100U
-#define RTC_ALRMBR_MNU_1                     0x00000200U
-#define RTC_ALRMBR_MNU_2                     0x00000400U
-#define RTC_ALRMBR_MNU_3                     0x00000800U
-#define RTC_ALRMBR_MSK1                      0x00000080U
-#define RTC_ALRMBR_ST                        0x00000070U
-#define RTC_ALRMBR_ST_0                      0x00000010U
-#define RTC_ALRMBR_ST_1                      0x00000020U
-#define RTC_ALRMBR_ST_2                      0x00000040U
-#define RTC_ALRMBR_SU                        0x0000000FU
-#define RTC_ALRMBR_SU_0                      0x00000001U
-#define RTC_ALRMBR_SU_1                      0x00000002U
-#define RTC_ALRMBR_SU_2                      0x00000004U
-#define RTC_ALRMBR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          0x000000FFU
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           0x0000FFFFU
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     0x00007FFFU
-#define RTC_SHIFTR_ADD1S                     0x80000000U
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          0x00400000U
-#define RTC_TSTR_HT                          0x00300000U
-#define RTC_TSTR_HT_0                        0x00100000U
-#define RTC_TSTR_HT_1                        0x00200000U
-#define RTC_TSTR_HU                          0x000F0000U
-#define RTC_TSTR_HU_0                        0x00010000U
-#define RTC_TSTR_HU_1                        0x00020000U
-#define RTC_TSTR_HU_2                        0x00040000U
-#define RTC_TSTR_HU_3                        0x00080000U
-#define RTC_TSTR_MNT                         0x00007000U
-#define RTC_TSTR_MNT_0                       0x00001000U
-#define RTC_TSTR_MNT_1                       0x00002000U
-#define RTC_TSTR_MNT_2                       0x00004000U
-#define RTC_TSTR_MNU                         0x00000F00U
-#define RTC_TSTR_MNU_0                       0x00000100U
-#define RTC_TSTR_MNU_1                       0x00000200U
-#define RTC_TSTR_MNU_2                       0x00000400U
-#define RTC_TSTR_MNU_3                       0x00000800U
-#define RTC_TSTR_ST                          0x00000070U
-#define RTC_TSTR_ST_0                        0x00000010U
-#define RTC_TSTR_ST_1                        0x00000020U
-#define RTC_TSTR_ST_2                        0x00000040U
-#define RTC_TSTR_SU                          0x0000000FU
-#define RTC_TSTR_SU_0                        0x00000001U
-#define RTC_TSTR_SU_1                        0x00000002U
-#define RTC_TSTR_SU_2                        0x00000004U
-#define RTC_TSTR_SU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         0x0000E000U
-#define RTC_TSDR_WDU_0                       0x00002000U
-#define RTC_TSDR_WDU_1                       0x00004000U
-#define RTC_TSDR_WDU_2                       0x00008000U
-#define RTC_TSDR_MT                          0x00001000U
-#define RTC_TSDR_MU                          0x00000F00U
-#define RTC_TSDR_MU_0                        0x00000100U
-#define RTC_TSDR_MU_1                        0x00000200U
-#define RTC_TSDR_MU_2                        0x00000400U
-#define RTC_TSDR_MU_3                        0x00000800U
-#define RTC_TSDR_DT                          0x00000030U
-#define RTC_TSDR_DT_0                        0x00000010U
-#define RTC_TSDR_DT_1                        0x00000020U
-#define RTC_TSDR_DU                          0x0000000FU
-#define RTC_TSDR_DU_0                        0x00000001U
-#define RTC_TSDR_DU_1                        0x00000002U
-#define RTC_TSDR_DU_2                        0x00000004U
-#define RTC_TSDR_DU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        0x00008000U
-#define RTC_CALR_CALW8                       0x00004000U
-#define RTC_CALR_CALW16                      0x00002000U
-#define RTC_CALR_CALM                        0x000001FFU
-#define RTC_CALR_CALM_0                      0x00000001U
-#define RTC_CALR_CALM_1                      0x00000002U
-#define RTC_CALR_CALM_2                      0x00000004U
-#define RTC_CALR_CALM_3                      0x00000008U
-#define RTC_CALR_CALM_4                      0x00000010U
-#define RTC_CALR_CALM_5                      0x00000020U
-#define RTC_CALR_CALM_6                      0x00000040U
-#define RTC_CALR_CALM_7                      0x00000080U
-#define RTC_CALR_CALM_8                      0x00000100U
-
-/********************  Bits definition for RTC_TAMPCR register  ****************/
-#define RTC_TAMPCR_TAMP3MF                   0x01000000U
-#define RTC_TAMPCR_TAMP3NOERASE              0x00800000U
-#define RTC_TAMPCR_TAMP3IE                   0x00400000U
-#define RTC_TAMPCR_TAMP2MF                   0x00200000U
-#define RTC_TAMPCR_TAMP2NOERASE              0x00100000U
-#define RTC_TAMPCR_TAMP2IE                   0x00080000U
-#define RTC_TAMPCR_TAMP1MF                   0x00040000U
-#define RTC_TAMPCR_TAMP1NOERASE              0x00020000U
-#define RTC_TAMPCR_TAMP1IE                   0x00010000U
-#define RTC_TAMPCR_TAMPPUDIS                 0x00008000U
-#define RTC_TAMPCR_TAMPPRCH                  0x00006000U
-#define RTC_TAMPCR_TAMPPRCH_0                0x00002000U
-#define RTC_TAMPCR_TAMPPRCH_1                0x00004000U
-#define RTC_TAMPCR_TAMPFLT                   0x00001800U
-#define RTC_TAMPCR_TAMPFLT_0                 0x00000800U
-#define RTC_TAMPCR_TAMPFLT_1                 0x00001000U
-#define RTC_TAMPCR_TAMPFREQ                  0x00000700U
-#define RTC_TAMPCR_TAMPFREQ_0                0x00000100U
-#define RTC_TAMPCR_TAMPFREQ_1                0x00000200U
-#define RTC_TAMPCR_TAMPFREQ_2                0x00000400U
-#define RTC_TAMPCR_TAMPTS                    0x00000080U
-#define RTC_TAMPCR_TAMP3TRG                  0x00000040U
-#define RTC_TAMPCR_TAMP3E                    0x00000020U
-#define RTC_TAMPCR_TAMP2TRG                  0x00000010U
-#define RTC_TAMPCR_TAMP2E                    0x00000008U
-#define RTC_TAMPCR_TAMPIE                    0x00000004U
-#define RTC_TAMPCR_TAMP1TRG                  0x00000002U
-#define RTC_TAMPCR_TAMP1E                    0x00000001U
-
-/* Legacy defines */
-#define RTC_TAMPCR_TAMP3_TRG                  RTC_TAMPCR_TAMP3TRG
-#define RTC_TAMPCR_TAMP2_TRG                  RTC_TAMPCR_TAMP2TRG
-#define RTC_TAMPCR_TAMP1_TRG                  RTC_TAMPCR_TAMP1TRG
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  0x0F000000U
-#define RTC_ALRMASSR_MASKSS_0                0x01000000U
-#define RTC_ALRMASSR_MASKSS_1                0x02000000U
-#define RTC_ALRMASSR_MASKSS_2                0x04000000U
-#define RTC_ALRMASSR_MASKSS_3                0x08000000U
-#define RTC_ALRMASSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
-#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
-#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
-#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
-#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
-#define RTC_ALRMBSSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_OR register  ****************/
-#define RTC_OR_TSINSEL                       0x00000006U
-#define RTC_OR_TSINSEL_0                     0x00000002U
-#define RTC_OR_TSINSEL_1                     0x00000004U
-#define RTC_OR_ALARMTYPE                     0x00000008U
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP20R register  ***************/
-#define RTC_BKP20R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP21R register  ***************/
-#define RTC_BKP21R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP22R register  ***************/
-#define RTC_BKP22R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP23R register  ***************/
-#define RTC_BKP23R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP24R register  ***************/
-#define RTC_BKP24R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP25R register  ***************/
-#define RTC_BKP25R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP26R register  ***************/
-#define RTC_BKP26R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP27R register  ***************/
-#define RTC_BKP27R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP28R register  ***************/
-#define RTC_BKP28R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP29R register  ***************/
-#define RTC_BKP29R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP30R register  ***************/
-#define RTC_BKP30R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP31R register  ***************/
-#define RTC_BKP31R                           0xFFFFFFFFU
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER                       0x00000020U
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Serial Audio Interface                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for SAI_GCR register  *******************/
-#define  SAI_GCR_SYNCIN                      0x00000003U        /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
-#define  SAI_GCR_SYNCIN_0                    0x00000001U        /*!<Bit 0 */
-#define  SAI_GCR_SYNCIN_1                    0x00000002U        /*!<Bit 1 */
-
-#define  SAI_GCR_SYNCOUT                     0x00000030U        /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
-#define  SAI_GCR_SYNCOUT_0                   0x00000010U        /*!<Bit 0 */
-#define  SAI_GCR_SYNCOUT_1                   0x00000020U        /*!<Bit 1 */
-
-/*******************  Bit definition for SAI_xCR1 register  *******************/
-#define  SAI_xCR1_MODE                       0x00000003U        /*!<MODE[1:0] bits (Audio Block Mode)           */
-#define  SAI_xCR1_MODE_0                     0x00000001U        /*!<Bit 0 */
-#define  SAI_xCR1_MODE_1                     0x00000002U        /*!<Bit 1 */
-
-#define  SAI_xCR1_PRTCFG                     0x0000000CU        /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
-#define  SAI_xCR1_PRTCFG_0                   0x00000004U        /*!<Bit 0 */
-#define  SAI_xCR1_PRTCFG_1                   0x00000008U        /*!<Bit 1 */
-
-#define  SAI_xCR1_DS                         0x000000E0U        /*!<DS[1:0] bits (Data Size) */
-#define  SAI_xCR1_DS_0                       0x00000020U        /*!<Bit 0 */
-#define  SAI_xCR1_DS_1                       0x00000040U        /*!<Bit 1 */
-#define  SAI_xCR1_DS_2                       0x00000080U        /*!<Bit 2 */
-
-#define  SAI_xCR1_LSBFIRST                   0x00000100U        /*!<LSB First Configuration  */
-#define  SAI_xCR1_CKSTR                      0x00000200U        /*!<ClocK STRobing edge      */
-
-#define  SAI_xCR1_SYNCEN                     0x00000C00U        /*!<SYNCEN[1:0](SYNChronization ENable) */
-#define  SAI_xCR1_SYNCEN_0                   0x00000400U        /*!<Bit 0 */
-#define  SAI_xCR1_SYNCEN_1                   0x00000800U        /*!<Bit 1 */
-
-#define  SAI_xCR1_MONO                       0x00001000U        /*!<Mono mode                  */
-#define  SAI_xCR1_OUTDRIV                    0x00002000U        /*!<Output Drive               */
-#define  SAI_xCR1_SAIEN                      0x00010000U        /*!<Audio Block enable         */
-#define  SAI_xCR1_DMAEN                      0x00020000U        /*!<DMA enable                 */
-#define  SAI_xCR1_NODIV                      0x00080000U        /*!<No Divider Configuration   */
-
-#define  SAI_xCR1_MCKDIV                     0x00F00000U        /*!<MCKDIV[3:0] (Master ClocK Divider)  */
-#define  SAI_xCR1_MCKDIV_0                   0x00100000U        /*!<Bit 0  */
-#define  SAI_xCR1_MCKDIV_1                   0x00200000U        /*!<Bit 1  */
-#define  SAI_xCR1_MCKDIV_2                   0x00400000U        /*!<Bit 2  */
-#define  SAI_xCR1_MCKDIV_3                   0x00800000U        /*!<Bit 3  */
-
-/*******************  Bit definition for SAI_xCR2 register  *******************/
-#define  SAI_xCR2_FTH                        0x00000007U        /*!<FTH[2:0](Fifo THreshold)  */
-#define  SAI_xCR2_FTH_0                      0x00000001U        /*!<Bit 0 */
-#define  SAI_xCR2_FTH_1                      0x00000002U        /*!<Bit 1 */
-#define  SAI_xCR2_FTH_2                      0x00000004U        /*!<Bit 2 */
-
-#define  SAI_xCR2_FFLUSH                     0x00000008U        /*!<Fifo FLUSH                       */
-#define  SAI_xCR2_TRIS                       0x00000010U        /*!<TRIState Management on data line */
-#define  SAI_xCR2_MUTE                       0x00000020U        /*!<Mute mode                        */
-#define  SAI_xCR2_MUTEVAL                    0x00000040U        /*!<Muate value                      */
-
-#define  SAI_xCR2_MUTECNT                    0x00001F80U       /*!<MUTECNT[5:0] (MUTE counter) */
-#define  SAI_xCR2_MUTECNT_0                  0x00000080U        /*!<Bit 0 */
-#define  SAI_xCR2_MUTECNT_1                  0x00000100U        /*!<Bit 1 */
-#define  SAI_xCR2_MUTECNT_2                  0x00000200U        /*!<Bit 2 */
-#define  SAI_xCR2_MUTECNT_3                  0x00000400U        /*!<Bit 3 */
-#define  SAI_xCR2_MUTECNT_4                  0x00000800U        /*!<Bit 4 */
-#define  SAI_xCR2_MUTECNT_5                  0x00001000U        /*!<Bit 5 */
-
-#define  SAI_xCR2_CPL                        0x00002000U        /*!< Complement Bit             */
-
-#define  SAI_xCR2_COMP                       0x0000C000U        /*!<COMP[1:0] (Companding mode) */
-#define  SAI_xCR2_COMP_0                     0x00004000U        /*!<Bit 0 */
-#define  SAI_xCR2_COMP_1                     0x00008000U        /*!<Bit 1 */
-
-/******************  Bit definition for SAI_xFRCR register  *******************/
-#define  SAI_xFRCR_FRL                       0x000000FFU        /*!<FRL[1:0](Frame length)  */
-#define  SAI_xFRCR_FRL_0                     0x00000001U        /*!<Bit 0 */
-#define  SAI_xFRCR_FRL_1                     0x00000002U        /*!<Bit 1 */
-#define  SAI_xFRCR_FRL_2                     0x00000004U        /*!<Bit 2 */
-#define  SAI_xFRCR_FRL_3                     0x00000008U        /*!<Bit 3 */
-#define  SAI_xFRCR_FRL_4                     0x00000010U        /*!<Bit 4 */
-#define  SAI_xFRCR_FRL_5                     0x00000020U        /*!<Bit 5 */
-#define  SAI_xFRCR_FRL_6                     0x00000040U        /*!<Bit 6 */
-#define  SAI_xFRCR_FRL_7                     0x00000080U        /*!<Bit 7 */
-
-#define  SAI_xFRCR_FSALL                     0x00007F00U        /*!<FRL[1:0] (Frame synchronization active level length)  */
-#define  SAI_xFRCR_FSALL_0                   0x00000100U        /*!<Bit 0 */
-#define  SAI_xFRCR_FSALL_1                   0x00000200U        /*!<Bit 1 */
-#define  SAI_xFRCR_FSALL_2                   0x00000400U        /*!<Bit 2 */
-#define  SAI_xFRCR_FSALL_3                   0x00000800U        /*!<Bit 3 */
-#define  SAI_xFRCR_FSALL_4                   0x00001000U        /*!<Bit 4 */
-#define  SAI_xFRCR_FSALL_5                   0x00002000U        /*!<Bit 5 */
-#define  SAI_xFRCR_FSALL_6                   0x00004000U        /*!<Bit 6 */
-
-#define  SAI_xFRCR_FSDEF                     0x00010000U        /*!<Frame Synchronization Definition  */
-#define  SAI_xFRCR_FSPOL                     0x00020000U        /*!<Frame Synchronization POLarity    */
-#define  SAI_xFRCR_FSOFF                     0x00040000U        /*!<Frame Synchronization OFFset      */
-
-/* Legacy define */
-#define  SAI_xFRCR_FSPO                      SAI_xFRCR_FSPOL
-
-/******************  Bit definition for SAI_xSLOTR register  *******************/
-#define  SAI_xSLOTR_FBOFF                    0x0000001FU        /*!<FRL[4:0](First Bit Offset)  */
-#define  SAI_xSLOTR_FBOFF_0                  0x00000001U        /*!<Bit 0 */
-#define  SAI_xSLOTR_FBOFF_1                  0x00000002U        /*!<Bit 1 */
-#define  SAI_xSLOTR_FBOFF_2                  0x00000004U        /*!<Bit 2 */
-#define  SAI_xSLOTR_FBOFF_3                  0x00000008U        /*!<Bit 3 */
-#define  SAI_xSLOTR_FBOFF_4                  0x00000010U        /*!<Bit 4 */
-
-#define  SAI_xSLOTR_SLOTSZ                   0x000000C0U        /*!<SLOTSZ[1:0] (Slot size)  */
-#define  SAI_xSLOTR_SLOTSZ_0                 0x00000040U        /*!<Bit 0 */
-#define  SAI_xSLOTR_SLOTSZ_1                 0x00000080U        /*!<Bit 1 */
-
-#define  SAI_xSLOTR_NBSLOT                   0x00000F00U        /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
-#define  SAI_xSLOTR_NBSLOT_0                 0x00000100U        /*!<Bit 0 */
-#define  SAI_xSLOTR_NBSLOT_1                 0x00000200U        /*!<Bit 1 */
-#define  SAI_xSLOTR_NBSLOT_2                 0x00000400U        /*!<Bit 2 */
-#define  SAI_xSLOTR_NBSLOT_3                 0x00000800U        /*!<Bit 3 */
-
-#define  SAI_xSLOTR_SLOTEN                   0xFFFF0000U        /*!<SLOTEN[15:0] (Slot Enable)  */
-
-/*******************  Bit definition for SAI_xIMR register  *******************/
-#define  SAI_xIMR_OVRUDRIE                   0x00000001U        /*!<Overrun underrun interrupt enable                              */
-#define  SAI_xIMR_MUTEDETIE                  0x00000002U        /*!<Mute detection interrupt enable                                */
-#define  SAI_xIMR_WCKCFGIE                   0x00000004U        /*!<Wrong Clock Configuration interrupt enable                     */
-#define  SAI_xIMR_FREQIE                     0x00000008U        /*!<FIFO request interrupt enable                                  */
-#define  SAI_xIMR_CNRDYIE                    0x00000010U        /*!<Codec not ready interrupt enable                               */
-#define  SAI_xIMR_AFSDETIE                   0x00000020U        /*!<Anticipated frame synchronization detection interrupt enable   */
-#define  SAI_xIMR_LFSDETIE                   0x00000040U        /*!<Late frame synchronization detection interrupt enable          */
-
-/********************  Bit definition for SAI_xSR register  *******************/
-#define  SAI_xSR_OVRUDR                      0x00000001U         /*!<Overrun underrun                               */
-#define  SAI_xSR_MUTEDET                     0x00000002U         /*!<Mute detection                                 */
-#define  SAI_xSR_WCKCFG                      0x00000004U         /*!<Wrong Clock Configuration                      */
-#define  SAI_xSR_FREQ                        0x00000008U         /*!<FIFO request                                   */
-#define  SAI_xSR_CNRDY                       0x00000010U         /*!<Codec not ready                                */
-#define  SAI_xSR_AFSDET                      0x00000020U         /*!<Anticipated frame synchronization detection    */
-#define  SAI_xSR_LFSDET                      0x00000040U         /*!<Late frame synchronization detection           */
-
-#define  SAI_xSR_FLVL                        0x00070000U         /*!<FLVL[2:0] (FIFO Level Threshold)               */
-#define  SAI_xSR_FLVL_0                      0x00010000U         /*!<Bit 0 */
-#define  SAI_xSR_FLVL_1                      0x00020000U         /*!<Bit 1 */
-#define  SAI_xSR_FLVL_2                      0x00040000U         /*!<Bit 2 */
-
-/******************  Bit definition for SAI_xCLRFR register  ******************/
-#define  SAI_xCLRFR_COVRUDR                  0x00000001U        /*!<Clear Overrun underrun                               */
-#define  SAI_xCLRFR_CMUTEDET                 0x00000002U        /*!<Clear Mute detection                                 */
-#define  SAI_xCLRFR_CWCKCFG                  0x00000004U        /*!<Clear Wrong Clock Configuration                      */
-#define  SAI_xCLRFR_CFREQ                    0x00000008U        /*!<Clear FIFO request                                   */
-#define  SAI_xCLRFR_CCNRDY                   0x00000010U        /*!<Clear Codec not ready                                */
-#define  SAI_xCLRFR_CAFSDET                  0x00000020U        /*!<Clear Anticipated frame synchronization detection    */
-#define  SAI_xCLRFR_CLFSDET                  0x00000040U        /*!<Clear Late frame synchronization detection           */
-
-/******************  Bit definition for SAI_xDR register  *********************/
-#define  SAI_xDR_DATA                        0xFFFFFFFFU
-
-/******************************************************************************/
-/*                                                                            */
-/*                              SPDIF-RX Interface                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for SPDIF_CR register  *******************/
-#define  SPDIFRX_CR_SPDIFEN                0x00000003U        /*!<Peripheral Block Enable                      */
-#define  SPDIFRX_CR_RXDMAEN                0x00000004U        /*!<Receiver DMA Enable for data flow            */
-#define  SPDIFRX_CR_RXSTEO                 0x00000008U        /*!<Stereo Mode                                  */
-#define  SPDIFRX_CR_DRFMT                  0x00000030U        /*!<RX Data format                               */
-#define  SPDIFRX_CR_PMSK                   0x00000040U        /*!<Mask Parity error bit                        */
-#define  SPDIFRX_CR_VMSK                   0x00000080U        /*!<Mask of Validity bit                         */
-#define  SPDIFRX_CR_CUMSK                  0x00000100U        /*!<Mask of channel status and user bits         */
-#define  SPDIFRX_CR_PTMSK                  0x00000200U        /*!<Mask of Preamble Type bits                   */
-#define  SPDIFRX_CR_CBDMAEN                0x00000400U        /*!<Control Buffer DMA ENable for control flow   */
-#define  SPDIFRX_CR_CHSEL                  0x00000800U        /*!<Channel Selection                            */
-#define  SPDIFRX_CR_NBTR                   0x00003000U        /*!<Maximum allowed re-tries during synchronization phase */
-#define  SPDIFRX_CR_WFA                    0x00004000U        /*!<Wait For Activity     */
-#define  SPDIFRX_CR_INSEL                  0x00070000U        /*!<SPDIF input selection */
-
-/*******************  Bit definition for SPDIFRX_IMR register  *******************/
-#define  SPDIFRX_IMR_RXNEIE                0x00000001U        /*!<RXNE interrupt enable                              */
-#define  SPDIFRX_IMR_CSRNEIE               0x00000002U        /*!<Control Buffer Ready Interrupt Enable              */
-#define  SPDIFRX_IMR_PERRIE                0x00000004U        /*!<Parity error interrupt enable                      */
-#define  SPDIFRX_IMR_OVRIE                 0x00000008U        /*!<Overrun error Interrupt Enable                     */
-#define  SPDIFRX_IMR_SBLKIE                0x00000010U        /*!<Synchronization Block Detected Interrupt Enable    */
-#define  SPDIFRX_IMR_SYNCDIE               0x00000020U        /*!<Synchronization Done                               */
-#define  SPDIFRX_IMR_IFEIE                 0x00000040U        /*!<Serial Interface Error Interrupt Enable            */
-
-/*******************  Bit definition for SPDIFRX_SR register  *******************/
-#define  SPDIFRX_SR_RXNE                   0x00000001U       /*!<Read data register not empty                          */
-#define  SPDIFRX_SR_CSRNE                  0x00000002U       /*!<The Control Buffer register is not empty              */
-#define  SPDIFRX_SR_PERR                   0x00000004U       /*!<Parity error                                          */
-#define  SPDIFRX_SR_OVR                    0x00000008U       /*!<Overrun error                                         */
-#define  SPDIFRX_SR_SBD                    0x00000010U       /*!<Synchronization Block Detected                        */
-#define  SPDIFRX_SR_SYNCD                  0x00000020U       /*!<Synchronization Done                                  */
-#define  SPDIFRX_SR_FERR                   0x00000040U       /*!<Framing error                                         */
-#define  SPDIFRX_SR_SERR                   0x00000080U       /*!<Synchronization error                                 */
-#define  SPDIFRX_SR_TERR                   0x00000100U       /*!<Time-out error                                        */
-#define  SPDIFRX_SR_WIDTH5                 0x7FFF0000U       /*!<Duration of 5 symbols counted with spdif_clk          */
-
-/*******************  Bit definition for SPDIFRX_IFCR register  *******************/
-#define  SPDIFRX_IFCR_PERRCF               0x00000004U       /*!<Clears the Parity error flag                         */
-#define  SPDIFRX_IFCR_OVRCF                0x00000008U       /*!<Clears the Overrun error flag                        */
-#define  SPDIFRX_IFCR_SBDCF                0x00000010U       /*!<Clears the Synchronization Block Detected flag       */
-#define  SPDIFRX_IFCR_SYNCDCF              0x00000020U       /*!<Clears the Synchronization Done flag                 */
-
-/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/
-#define  SPDIFRX_DR0_DR                    0x00FFFFFFU        /*!<Data value            */
-#define  SPDIFRX_DR0_PE                    0x01000000U        /*!<Parity Error bit      */
-#define  SPDIFRX_DR0_V                     0x02000000U        /*!<Validity bit          */
-#define  SPDIFRX_DR0_U                     0x04000000U        /*!<User bit              */
-#define  SPDIFRX_DR0_C                     0x08000000U        /*!<Channel Status bit    */
-#define  SPDIFRX_DR0_PT                    0x30000000U        /*!<Preamble Type         */
-
-/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/
-#define  SPDIFRX_DR1_DR                    0xFFFFFF00U        /*!<Data value            */
-#define  SPDIFRX_DR1_PT                    0x00000030U        /*!<Preamble Type         */
-#define  SPDIFRX_DR1_C                     0x00000008U        /*!<Channel Status bit    */
-#define  SPDIFRX_DR1_U                     0x00000004U        /*!<User bit              */
-#define  SPDIFRX_DR1_V                     0x00000002U        /*!<Validity bit          */
-#define  SPDIFRX_DR1_PE                    0x00000001U        /*!<Parity Error bit      */
-
-/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/
-#define  SPDIFRX_DR1_DRNL1                 0xFFFF0000U        /*!<Data value Channel B      */
-#define  SPDIFRX_DR1_DRNL2                 0x0000FFFFU        /*!<Data value Channel A      */
-
-/*******************  Bit definition for SPDIFRX_CSR register   *******************/
-#define  SPDIFRX_CSR_USR                   0x0000FFFFU        /*!<User data information           */
-#define  SPDIFRX_CSR_CS                    0x00FF0000U        /*!<Channel A status information    */
-#define  SPDIFRX_CSR_SOB                   0x01000000U        /*!<Start Of Block                  */
-
-/*******************  Bit definition for SPDIFRX_DIR register    *******************/
-#define  SPDIFRX_DIR_THI                   0x000013FFU        /*!<Threshold LOW      */
-#define  SPDIFRX_DIR_TLO                   0x1FFF0000U        /*!<Threshold HIGH     */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          SD host Interface                                 */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SDMMC_POWER register  ******************/
-#define  SDMMC_POWER_PWRCTRL                  0x03U               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDMMC_POWER_PWRCTRL_0                0x01U               /*!<Bit 0 */
-#define  SDMMC_POWER_PWRCTRL_1                0x02U               /*!<Bit 1 */
-
-/******************  Bit definition for SDMMC_CLKCR register  ******************/
-#define  SDMMC_CLKCR_CLKDIV                   0x00FFU            /*!<Clock divide factor             */
-#define  SDMMC_CLKCR_CLKEN                    0x0100U            /*!<Clock enable bit                */
-#define  SDMMC_CLKCR_PWRSAV                   0x0200U            /*!<Power saving configuration bit  */
-#define  SDMMC_CLKCR_BYPASS                   0x0400U            /*!<Clock divider bypass enable bit */
-
-#define  SDMMC_CLKCR_WIDBUS                   0x1800U            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDMMC_CLKCR_WIDBUS_0                 0x0800U            /*!<Bit 0 */
-#define  SDMMC_CLKCR_WIDBUS_1                 0x1000U            /*!<Bit 1 */
-
-#define  SDMMC_CLKCR_NEGEDGE                  0x2000U            /*!<SDMMC_CK dephasing selection bit */
-#define  SDMMC_CLKCR_HWFC_EN                  0x4000U            /*!<HW Flow Control enable          */
-
-/*******************  Bit definition for SDMMC_ARG register  *******************/
-#define  SDMMC_ARG_CMDARG                     0xFFFFFFFFU            /*!<Command argument */
-
-/*******************  Bit definition for SDMMC_CMD register  *******************/
-#define  SDMMC_CMD_CMDINDEX                   0x003FU            /*!<Command Index                               */
-
-#define  SDMMC_CMD_WAITRESP                   0x00C0U            /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDMMC_CMD_WAITRESP_0                 0x0040U            /*!< Bit 0 */
-#define  SDMMC_CMD_WAITRESP_1                 0x0080U            /*!< Bit 1 */
-
-#define  SDMMC_CMD_WAITINT                    0x0100U            /*!<CPSM Waits for Interrupt Request                               */
-#define  SDMMC_CMD_WAITPEND                   0x0200U            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDMMC_CMD_CPSMEN                     0x0400U            /*!<Command path state machine (CPSM) Enable bit                   */
-#define  SDMMC_CMD_SDIOSUSPEND                0x0800U            /*!<SD I/O suspend command                                         */
-
-/*****************  Bit definition for SDMMC_RESPCMD register  *****************/
-#define  SDMMC_RESPCMD_RESPCMD                0x3FU               /*!<Response command index */
-
-/******************  Bit definition for SDMMC_RESP0 register  ******************/
-#define  SDMMC_RESP0_CARDSTATUS0              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDMMC_RESP1 register  ******************/
-#define  SDMMC_RESP1_CARDSTATUS1              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDMMC_RESP2 register  ******************/
-#define  SDMMC_RESP2_CARDSTATUS2              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDMMC_RESP3 register  ******************/
-#define  SDMMC_RESP3_CARDSTATUS3              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDMMC_RESP4 register  ******************/
-#define  SDMMC_RESP4_CARDSTATUS4              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDMMC_DTIMER register  *****************/
-#define  SDMMC_DTIMER_DATATIME                0xFFFFFFFFU        /*!<Data timeout period. */
-
-/******************  Bit definition for SDMMC_DLEN register  *******************/
-#define  SDMMC_DLEN_DATALENGTH                0x01FFFFFFU        /*!<Data length value    */
-
-/******************  Bit definition for SDMMC_DCTRL register  ******************/
-#define  SDMMC_DCTRL_DTEN                     0x0001U            /*!<Data transfer enabled bit         */
-#define  SDMMC_DCTRL_DTDIR                    0x0002U            /*!<Data transfer direction selection */
-#define  SDMMC_DCTRL_DTMODE                   0x0004U            /*!<Data transfer mode selection      */
-#define  SDMMC_DCTRL_DMAEN                    0x0008U            /*!<DMA enabled bit                   */
-
-#define  SDMMC_DCTRL_DBLOCKSIZE               0x00F0U            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDMMC_DCTRL_DBLOCKSIZE_0             0x0010U            /*!<Bit 0 */
-#define  SDMMC_DCTRL_DBLOCKSIZE_1             0x0020U            /*!<Bit 1 */
-#define  SDMMC_DCTRL_DBLOCKSIZE_2             0x0040U            /*!<Bit 2 */
-#define  SDMMC_DCTRL_DBLOCKSIZE_3             0x0080U            /*!<Bit 3 */
-
-#define  SDMMC_DCTRL_RWSTART                  0x0100U            /*!<Read wait start         */
-#define  SDMMC_DCTRL_RWSTOP                   0x0200U            /*!<Read wait stop          */
-#define  SDMMC_DCTRL_RWMOD                    0x0400U            /*!<Read wait mode          */
-#define  SDMMC_DCTRL_SDIOEN                   0x0800U            /*!<SD I/O enable functions */
-
-/******************  Bit definition for SDMMC_DCOUNT register  *****************/
-#define  SDMMC_DCOUNT_DATACOUNT               0x01FFFFFFU        /*!<Data count value */
-
-/******************  Bit definition for SDMMC_STA registe  ********************/
-#define  SDMMC_STA_CCRCFAIL                   0x00000001U        /*!<Command response received (CRC check failed)  */
-#define  SDMMC_STA_DCRCFAIL                   0x00000002U        /*!<Data block sent/received (CRC check failed)   */
-#define  SDMMC_STA_CTIMEOUT                   0x00000004U        /*!<Command response timeout                      */
-#define  SDMMC_STA_DTIMEOUT                   0x00000008U        /*!<Data timeout                                  */
-#define  SDMMC_STA_TXUNDERR                   0x00000010U        /*!<Transmit FIFO underrun error                  */
-#define  SDMMC_STA_RXOVERR                    0x00000020U        /*!<Received FIFO overrun error                   */
-#define  SDMMC_STA_CMDREND                    0x00000040U        /*!<Command response received (CRC check passed)  */
-#define  SDMMC_STA_CMDSENT                    0x00000080U        /*!<Command sent (no response required)           */
-#define  SDMMC_STA_DATAEND                    0x00000100U        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
-#define  SDMMC_STA_DBCKEND                    0x00000400U        /*!<Data block sent/received (CRC check passed)   */
-#define  SDMMC_STA_CMDACT                     0x00000800U        /*!<Command transfer in progress                  */
-#define  SDMMC_STA_TXACT                      0x00001000U        /*!<Data transmit in progress                     */
-#define  SDMMC_STA_RXACT                      0x00002000U        /*!<Data receive in progress                      */
-#define  SDMMC_STA_TXFIFOHE                   0x00004000U        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDMMC_STA_RXFIFOHF                   0x00008000U        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDMMC_STA_TXFIFOF                    0x00010000U        /*!<Transmit FIFO full                            */
-#define  SDMMC_STA_RXFIFOF                    0x00020000U        /*!<Receive FIFO full                             */
-#define  SDMMC_STA_TXFIFOE                    0x00040000U        /*!<Transmit FIFO empty                           */
-#define  SDMMC_STA_RXFIFOE                    0x00080000U        /*!<Receive FIFO empty                            */
-#define  SDMMC_STA_TXDAVL                     0x00100000U        /*!<Data available in transmit FIFO               */
-#define  SDMMC_STA_RXDAVL                     0x00200000U        /*!<Data available in receive FIFO                */
-#define  SDMMC_STA_SDIOIT                     0x00400000U        /*!<SDMMC interrupt received                       */
-
-/*******************  Bit definition for SDMMC_ICR register  *******************/
-#define  SDMMC_ICR_CCRCFAILC                  0x00000001U        /*!<CCRCFAIL flag clear bit */
-#define  SDMMC_ICR_DCRCFAILC                  0x00000002U        /*!<DCRCFAIL flag clear bit */
-#define  SDMMC_ICR_CTIMEOUTC                  0x00000004U        /*!<CTIMEOUT flag clear bit */
-#define  SDMMC_ICR_DTIMEOUTC                  0x00000008U        /*!<DTIMEOUT flag clear bit */
-#define  SDMMC_ICR_TXUNDERRC                  0x00000010U        /*!<TXUNDERR flag clear bit */
-#define  SDMMC_ICR_RXOVERRC                   0x00000020U        /*!<RXOVERR flag clear bit  */
-#define  SDMMC_ICR_CMDRENDC                   0x00000040U        /*!<CMDREND flag clear bit  */
-#define  SDMMC_ICR_CMDSENTC                   0x00000080U        /*!<CMDSENT flag clear bit  */
-#define  SDMMC_ICR_DATAENDC                   0x00000100U        /*!<DATAEND flag clear bit  */
-#define  SDMMC_ICR_DBCKENDC                   0x00000400U        /*!<DBCKEND flag clear bit  */
-#define  SDMMC_ICR_SDIOITC                    0x00400000U        /*!<SDMMCIT flag clear bit   */
-
-/******************  Bit definition for SDMMC_MASK register  *******************/
-#define  SDMMC_MASK_CCRCFAILIE                0x00000001U        /*!<Command CRC Fail Interrupt Enable          */
-#define  SDMMC_MASK_DCRCFAILIE                0x00000002U        /*!<Data CRC Fail Interrupt Enable             */
-#define  SDMMC_MASK_CTIMEOUTIE                0x00000004U        /*!<Command TimeOut Interrupt Enable           */
-#define  SDMMC_MASK_DTIMEOUTIE                0x00000008U        /*!<Data TimeOut Interrupt Enable              */
-#define  SDMMC_MASK_TXUNDERRIE                0x00000010U        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
-#define  SDMMC_MASK_RXOVERRIE                 0x00000020U        /*!<Rx FIFO OverRun Error Interrupt Enable     */
-#define  SDMMC_MASK_CMDRENDIE                 0x00000040U        /*!<Command Response Received Interrupt Enable */
-#define  SDMMC_MASK_CMDSENTIE                 0x00000080U        /*!<Command Sent Interrupt Enable              */
-#define  SDMMC_MASK_DATAENDIE                 0x00000100U        /*!<Data End Interrupt Enable                  */
-#define  SDMMC_MASK_DBCKENDIE                 0x00000400U        /*!<Data Block End Interrupt Enable            */
-#define  SDMMC_MASK_CMDACTIE                  0x00000800U        /*!<CCommand Acting Interrupt Enable           */
-#define  SDMMC_MASK_TXACTIE                   0x00001000U        /*!<Data Transmit Acting Interrupt Enable      */
-#define  SDMMC_MASK_RXACTIE                   0x00002000U        /*!<Data receive acting interrupt enabled      */
-#define  SDMMC_MASK_TXFIFOHEIE                0x00004000U        /*!<Tx FIFO Half Empty interrupt Enable        */
-#define  SDMMC_MASK_RXFIFOHFIE                0x00008000U        /*!<Rx FIFO Half Full interrupt Enable         */
-#define  SDMMC_MASK_TXFIFOFIE                 0x00010000U        /*!<Tx FIFO Full interrupt Enable              */
-#define  SDMMC_MASK_RXFIFOFIE                 0x00020000U        /*!<Rx FIFO Full interrupt Enable              */
-#define  SDMMC_MASK_TXFIFOEIE                 0x00040000U        /*!<Tx FIFO Empty interrupt Enable             */
-#define  SDMMC_MASK_RXFIFOEIE                 0x00080000U        /*!<Rx FIFO Empty interrupt Enable             */
-#define  SDMMC_MASK_TXDAVLIE                  0x00100000U        /*!<Data available in Tx FIFO interrupt Enable */
-#define  SDMMC_MASK_RXDAVLIE                  0x00200000U        /*!<Data available in Rx FIFO interrupt Enable */
-#define  SDMMC_MASK_SDIOITIE                  0x00400000U        /*!<SDMMC Mode Interrupt Received interrupt Enable */
-
-/*****************  Bit definition for SDMMC_FIFOCNT register  *****************/
-#define  SDMMC_FIFOCNT_FIFOCOUNT              0x00FFFFFFU        /*!<Remaining number of words to be written to or read from the FIFO */
-
-/******************  Bit definition for SDMMC_FIFO register  *******************/
-#define  SDMMC_FIFO_FIFODATA                  0xFFFFFFFFU        /*!<Receive and transmit FIFO data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface (SPI)                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        0x00000001U        /*!< Clock Phase                        */
-#define  SPI_CR1_CPOL                        0x00000002U        /*!< Clock Polarity                     */
-#define  SPI_CR1_MSTR                        0x00000004U        /*!< Master Selection                   */
-#define  SPI_CR1_BR                          0x00000038U        /*!< BR[2:0] bits (Baud Rate Control)   */
-#define  SPI_CR1_BR_0                        0x00000008U        /*!< Bit 0 */
-#define  SPI_CR1_BR_1                        0x00000010U        /*!< Bit 1 */
-#define  SPI_CR1_BR_2                        0x00000020U        /*!< Bit 2 */
-#define  SPI_CR1_SPE                         0x00000040U        /*!< SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    0x00000080U        /*!< Frame Format                        */
-#define  SPI_CR1_SSI                         0x00000100U        /*!< Internal slave select               */
-#define  SPI_CR1_SSM                         0x00000200U        /*!< Software slave management           */
-#define  SPI_CR1_RXONLY                      0x00000400U        /*!< Receive only                        */
-#define  SPI_CR1_CRCL                        0x00000800U        /*!< CRC Length                          */
-#define  SPI_CR1_CRCNEXT                     0x00001000U        /*!< Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       0x00002000U        /*!< Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      0x00004000U        /*!< Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    0x00008000U        /*!< Bidirectional data mode enable      */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     0x00000001U        /*!< Rx Buffer DMA Enable                 */
-#define  SPI_CR2_TXDMAEN                     0x00000002U        /*!< Tx Buffer DMA Enable                 */
-#define  SPI_CR2_SSOE                        0x00000004U        /*!< SS Output Enable                     */
-#define  SPI_CR2_NSSP                        0x00000008U        /*!< NSS pulse management Enable          */
-#define  SPI_CR2_FRF                         0x00000010U        /*!< Frame Format Enable                  */
-#define  SPI_CR2_ERRIE                       0x00000020U        /*!< Error Interrupt Enable               */
-#define  SPI_CR2_RXNEIE                      0x00000040U        /*!< RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       0x00000080U        /*!< Tx buffer Empty Interrupt Enable     */
-#define  SPI_CR2_DS                          0x00000F00U        /*!< DS[3:0] Data Size                    */
-#define  SPI_CR2_DS_0                        0x00000100U        /*!< Bit 0 */
-#define  SPI_CR2_DS_1                        0x00000200U        /*!< Bit 1 */
-#define  SPI_CR2_DS_2                        0x00000400U        /*!< Bit 2 */
-#define  SPI_CR2_DS_3                        0x00000800U        /*!< Bit 3 */
-#define  SPI_CR2_FRXTH                       0x00001000U        /*!< FIFO reception Threshold           */
-#define  SPI_CR2_LDMARX                      0x00002000U        /*!< Last DMA transfer for reception    */
-#define  SPI_CR2_LDMATX                      0x00004000U        /*!< Last DMA transfer for transmission */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         0x00000001U        /*!< Receive buffer Not Empty  */
-#define  SPI_SR_TXE                          0x00000002U        /*!< Transmit buffer Empty     */
-#define  SPI_SR_CHSIDE                       0x00000004U        /*!< Channel side              */
-#define  SPI_SR_UDR                          0x00000008U        /*!< Underrun flag             */
-#define  SPI_SR_CRCERR                       0x00000010U        /*!< CRC Error flag            */
-#define  SPI_SR_MODF                         0x00000020U        /*!< Mode fault                */
-#define  SPI_SR_OVR                          0x00000040U        /*!< Overrun flag              */
-#define  SPI_SR_BSY                          0x00000080U        /*!< Busy flag                 */
-#define  SPI_SR_FRE                          0x00000100U        /*!< TI frame format error     */
-#define  SPI_SR_FRLVL                        0x00000600U        /*!< FIFO Reception Level      */
-#define  SPI_SR_FRLVL_0                      0x00000200U        /*!< Bit 0 */
-#define  SPI_SR_FRLVL_1                      0x00000400U        /*!< Bit 1 */
-#define  SPI_SR_FTLVL                        0x00001800U        /*!< FIFO Transmission Level   */
-#define  SPI_SR_FTLVL_0                      0x00000800U        /*!< Bit 0 */
-#define  SPI_SR_FTLVL_1                      0x00001000U        /*!< Bit 1 */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           0xFFFFU            /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   0xFFFFU            /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    0xFFFFU            /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    0xFFFFU            /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   0x00000001U        /*!<Channel length (number of bits per audio channel) */
-#define  SPI_I2SCFGR_DATLEN                  0x00000006U        /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define  SPI_I2SCFGR_DATLEN_0                0x00000002U        /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                0x00000004U        /*!<Bit 1 */
-#define  SPI_I2SCFGR_CKPOL                   0x00000008U        /*!<steady state clock polarity                       */
-#define  SPI_I2SCFGR_I2SSTD                  0x00000030U        /*!<I2SSTD[1:0] bits (I2S standard selection)         */
-#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U        /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U        /*!<Bit 1 */
-#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U        /*!<PCM frame synchronization                         */
-#define  SPI_I2SCFGR_I2SCFG                  0x00000300U        /*!<I2SCFG[1:0] bits (I2S configuration mode)         */
-#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U        /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U        /*!<Bit 1 */
-#define  SPI_I2SCFGR_I2SE                    0x00000400U        /*!<I2S Enable                                        */
-#define  SPI_I2SCFGR_I2SMOD                  0x00000800U        /*!<I2S mode selection                                */
-#define  SPI_I2SCFGR_ASTRTEN                 0x00001000U        /*!<Asynchronous start enable                        */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    0x00FFU            /*!<I2S Linear prescaler         */
-#define  SPI_I2SPR_ODD                       0x0100U            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     0x0200U            /*!<Master Clock Output Enable   */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 SYSCFG                                     */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SYSCFG_MEMRMP register  ***************/
-#define SYSCFG_MEMRMP_MEM_BOOT         0x00000001U /*!< Boot information after Reset */
-
-
-#define SYSCFG_MEMRMP_SWP_FMC          0x00000C00U /*!< FMC Memory Mapping swapping */
-#define SYSCFG_MEMRMP_SWP_FMC_0        0x00000400U
-#define SYSCFG_MEMRMP_SWP_FMC_1        0x00000800U
-
-/******************  Bit definition for SYSCFG_PMC register  ******************/
-
-#define SYSCFG_PMC_ADCxDC2              0x00070000U /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC1DC2              0x00010000U /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC2DC2              0x00020000U /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC3DC2              0x00040000U /*!< Refer to AN4073 on how to use this bit  */
-
-#define SYSCFG_PMC_MII_RMII_SEL         0x00800000U /*!<Ethernet PHY interface selection */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
-/**
-  * @brief   EXTI0 configuration
-  */
-#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         0x0003U /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         0x0004U /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         0x0005U /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         0x0006U /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PI         0x0008U /*!<PI[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PJ         0x0009U /*!<PJ[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PK         0x000AU /*!<PK[0] pin */
-
-/**
-  * @brief   EXTI1 configuration
-  */
-#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         0x0030U /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         0x0040U /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         0x0050U /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         0x0060U /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PI         0x0080U /*!<PI[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PJ         0x0090U /*!<PJ[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PK         0x00A0U /*!<PK[1] pin */
-
-/**
-  * @brief   EXTI2 configuration
-  */
-#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         0x0300U /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         0x0400U /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         0x0500U /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         0x0600U /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PI         0x0800U /*!<PI[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PJ         0x0900U /*!<PJ[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PK         0x0A00U /*!<PK[2] pin */
-
-/**
-  * @brief   EXTI3 configuration
-  */
-#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         0x3000U /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         0x4000U /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         0x5000U /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         0x6000U /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PI         0x8000U /*!<PI[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PJ         0x9000U /*!<PJ[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PK         0xA000U /*!<PK[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
-/**
-  * @brief   EXTI4 configuration
-  */
-#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         0x0003U /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         0x0004U /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         0x0005U /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         0x0006U /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PI         0x0008U /*!<PI[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PJ         0x0009U /*!<PJ[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PK         0x000AU /*!<PK[4] pin */
-
-/**
-  * @brief   EXTI5 configuration
-  */
-#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         0x0030U /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         0x0040U /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         0x0050U /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         0x0060U /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PI         0x0080U /*!<PI[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PJ         0x0090U /*!<PJ[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PK         0x00A0U /*!<PK[5] pin */
-
-/**
-  * @brief   EXTI6 configuration
-  */
-#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         0x0300U /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         0x0400U /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         0x0500U /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         0x0600U /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PI         0x0800U /*!<PI[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PJ         0x0900U /*!<PJ[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PK         0x0A00U /*!<PK[6] pin */
-
-/**
-  * @brief   EXTI7 configuration
-  */
-#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         0x3000U /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         0x4000U /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         0x5000U /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         0x6000U /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PI         0x8000U /*!<PI[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PJ         0x9000U /*!<PJ[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PK         0xA000U /*!<PK[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
-
-/**
-  * @brief   EXTI8 configuration
-  */
-#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         0x0003U /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         0x0004U /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         0x0005U /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         0x0006U /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PI         0x0008U /*!<PI[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PJ         0x0009U /*!<PJ[8] pin */
-
-/**
-  * @brief   EXTI9 configuration
-  */
-#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         0x0030U /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         0x0040U /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         0x0050U /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         0x0060U /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PI         0x0080U /*!<PI[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PJ         0x0090U /*!<PJ[9] pin */
-
-/**
-  * @brief   EXTI10 configuration
-  */
-#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        0x0300U /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        0x0400U /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        0x0500U /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        0x0600U /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PI        0x0800U /*!<PI[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PJ        0x0900U /*!<PJ[10] pin */
-
-/**
-  * @brief   EXTI11 configuration
-  */
-#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        0x3000U /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        0x4000U /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        0x5000U /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        0x6000U /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PI        0x8000U /*!<PI[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PJ        0x9000U /*!<PJ[11] pin */
-
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
-/**
-  * @brief   EXTI12 configuration
-  */
-#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        0x0003U /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        0x0004U /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        0x0005U /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        0x0006U /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PI        0x0008U /*!<PI[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PJ        0x0009U /*!<PJ[12] pin */
-
-/**
-  * @brief   EXTI13 configuration
-  */
-#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        0x0030U /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        0x0040U /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        0x0050U /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        0x0060U /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PI        0x0080U /*!<PI[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PJ        0x0090U /*!<PJ[13] pin */
-
-/**
-  * @brief   EXTI14 configuration
-  */
-#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        0x0300U /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        0x0400U /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        0x0500U /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        0x0600U /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PI        0x0800U /*!<PI[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PJ        0x0900U /*!<PJ[14] pin */
-
-/**
-  * @brief   EXTI15 configuration
-  */
-#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        0x3000U /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        0x4000U /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        0x5000U /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        0x6000U /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PI        0x8000U /*!<PI[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PJ        0x9000U /*!<PJ[15] pin */
-
-
-/******************  Bit definition for SYSCFG_CMPCR register  ****************/
-#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell power-down */
-#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell ready flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    TIM                                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
-#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
-#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
-#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
-#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
-
-#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
-
-#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
-
-#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
-#define  TIM_CR1_UIFREMAP                    0x0800U            /*!<UIF status bit */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        0x00000001U            /*!<Capture/Compare Preloaded Control        */
-#define  TIM_CR2_CCUS                        0x00000004U            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        0x00000008U            /*!<Capture/Compare DMA Selection            */
-
-#define  TIM_CR2_OIS5                        0x00010000U            /*!<Output Idle state 4 (OC4 output) */
-#define  TIM_CR2_OIS6                        0x00040000U            /*!<Output Idle state 4 (OC4 output) */
-
-#define  TIM_CR2_MMS                         0x0070U           /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       0x0010U           /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       0x0020U           /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       0x0040U           /*!<Bit 2 */
-
-#define  TIM_CR2_MMS2                        0x00F00000U            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS2_0                      0x00100000U            /*!<Bit 0 */
-#define  TIM_CR2_MMS2_1                      0x00200000U            /*!<Bit 1 */
-#define  TIM_CR2_MMS2_2                      0x00400000U            /*!<Bit 2 */
-#define  TIM_CR2_MMS2_3                      0x00800000U            /*!<Bit 2 */
-
-#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
-#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
-#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
-#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        0x00010007U            /*!<SMS[2:0] bits (Slave mode selection)    */
-#define  TIM_SMCR_SMS_0                      0x00000001U            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      0x00000002U            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      0x00000004U            /*!<Bit 2 */
-#define  TIM_SMCR_SMS_3                      0x00010000U            /*!<Bit 3 */
-#define  TIM_SMCR_OCCS                       0x00000008U            /*!< OCREF clear selection */
-
-#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
-#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
-
-#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
-
-#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
-
-#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
-#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
-#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
-#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
-#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
-#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
-#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
-#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
-#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
-#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
-#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
-#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
-#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
-#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
-#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
-#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
-#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
-#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
-#define  TIM_SR_B2IF                         0x0100U            /*!<Break2 interrupt Flag               */
-#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          0x00000001U               /*!<Update Generation                         */
-#define  TIM_EGR_CC1G                        0x00000002U               /*!<Capture/Compare 1 Generation              */
-#define  TIM_EGR_CC2G                        0x00000004U               /*!<Capture/Compare 2 Generation              */
-#define  TIM_EGR_CC3G                        0x00000008U               /*!<Capture/Compare 3 Generation              */
-#define  TIM_EGR_CC4G                        0x00000010U               /*!<Capture/Compare 4 Generation              */
-#define  TIM_EGR_COMG                        0x00000020U               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          0x00000040U               /*!<Trigger Generation                        */
-#define  TIM_EGR_BG                          0x00000080U               /*!<Break Generation                          */
-#define  TIM_EGR_B2G                         0x00000100U              /*!<Break2 Generation                          */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      0x00000003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    0x00000001U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    0x00000002U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC1FE                     0x00000004U            /*!<Output Compare 1 Fast enable                 */
-#define  TIM_CCMR1_OC1PE                     0x00000008U            /*!<Output Compare 1 Preload enable              */
-
-#define  TIM_CCMR1_OC1M                      0x00010070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define  TIM_CCMR1_OC1M_0                    0x00000010U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    0x00000020U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    0x00000040U            /*!<Bit 2 */
-#define  TIM_CCMR1_OC1M_3                    0x00010000U            /*!<Bit 3 */
-
-#define  TIM_CCMR1_OC1CE                     0x00000080U            /*!<Output Compare 1Clear Enable                 */
-
-#define  TIM_CCMR1_CC2S                      0x00000300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    0x00000100U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    0x00000200U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC2FE                     0x00000400U            /*!<Output Compare 2 Fast enable                 */
-#define  TIM_CCMR1_OC2PE                     0x00000800U            /*!<Output Compare 2 Preload enable              */
-
-#define  TIM_CCMR1_OC2M                      0x01007000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define  TIM_CCMR1_OC2M_0                    0x00001000U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    0x00002000U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    0x00004000U            /*!<Bit 2 */
-#define  TIM_CCMR1_OC2M_3                    0x01000000U            /*!<Bit 3 */
-
-#define  TIM_CCMR1_OC2CE                     0x00008000U            /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      0x00000003U        /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define  TIM_CCMR2_CC3S_0                    0x00000001U        /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    0x00000002U        /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC3FE                     0x00000004U        /*!<Output Compare 3 Fast enable           */
-#define  TIM_CCMR2_OC3PE                     0x00000008U        /*!<Output Compare 3 Preload enable        */
-
-#define  TIM_CCMR2_OC3M                      0x00010070U        /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    0x00000010U        /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    0x00000020U        /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    0x00000040U        /*!<Bit 2 */
-#define  TIM_CCMR2_OC3M_3                    0x00010000U        /*!<Bit 3 */
-
-
-
-#define  TIM_CCMR2_OC3CE                     0x00000080U        /*!<Output Compare 3 Clear Enable */
-
-#define  TIM_CCMR2_CC4S                      0x00000300U        /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    0x00000100U        /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    0x00000200U        /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC4FE                     0x00000400U        /*!<Output Compare 4 Fast enable    */
-#define  TIM_CCMR2_OC4PE                     0x00000800U        /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR2_OC4M                      0x01007000U        /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    0x00001000U        /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    0x00002000U        /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    0x00004000U        /*!<Bit 2 */
-#define  TIM_CCMR2_OC4M_3                    0x01000000U        /*!<Bit 3 */
-
-#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       0x00000001U            /*!<Capture/Compare 1 output enable */
-#define  TIM_CCER_CC1P                       0x00000002U            /*!<Capture/Compare 1 output Polarity */
-#define  TIM_CCER_CC1NE                      0x00000004U            /*!<Capture/Compare 1 Complementary output enable */
-#define  TIM_CCER_CC1NP                      0x00000008U            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       0x00000010U            /*!<Capture/Compare 2 output enable */
-#define  TIM_CCER_CC2P                       0x00000020U            /*!<Capture/Compare 2 output Polarity */
-#define  TIM_CCER_CC2NE                      0x00000040U            /*!<Capture/Compare 2 Complementary output enable */
-#define  TIM_CCER_CC2NP                      0x00000080U            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       0x00000100U            /*!<Capture/Compare 3 output enable */
-#define  TIM_CCER_CC3P                       0x00000200U            /*!<Capture/Compare 3 output Polarity */
-#define  TIM_CCER_CC3NE                      0x00000400U            /*!<Capture/Compare 3 Complementary output enable */
-#define  TIM_CCER_CC3NP                      0x00000800U            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       0x00001000U            /*!<Capture/Compare 4 output enable */
-#define  TIM_CCER_CC4P                       0x00002000U            /*!<Capture/Compare 4 output Polarity */
-#define  TIM_CCER_CC4NP                      0x00008000U            /*!<Capture/Compare 4 Complementary output Polarity */
-#define  TIM_CCER_CC5E                       0x00010000U            /*!<Capture/Compare 5 output enable */
-#define  TIM_CCER_CC5P                       0x00020000U            /*!<Capture/Compare 5 output Polarity */
-#define  TIM_CCER_CC6E                       0x00100000U            /*!<Capture/Compare 6 output enable */
-#define  TIM_CCER_CC6P                       0x00200000U            /*!<Capture/Compare 6 output Polarity */
-
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         ((uint8_t)0xFFU)               /*!<Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
-
-/*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        0x000000FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      0x00000001U            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      0x00000002U            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      0x00000004U            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      0x00000008U            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      0x00000010U            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      0x00000020U            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      0x00000040U            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      0x00000080U            /*!<Bit 7 */
-
-#define  TIM_BDTR_LOCK                       0x00000300U            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     0x00000100U            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     0x00000200U            /*!<Bit 1 */
-
-#define  TIM_BDTR_OSSI                       0x00000400U            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       0x00000800U            /*!<Off-State Selection for Run mode  */
-#define  TIM_BDTR_BKE                        0x00001000U            /*!<Break enable                      */
-#define  TIM_BDTR_BKP                        0x00002000U            /*!<Break Polarity                    */
-#define  TIM_BDTR_AOE                        0x00004000U            /*!<Automatic Output enable           */
-#define  TIM_BDTR_MOE                        0x00008000U            /*!<Main Output enable                */
-#define  TIM_BDTR_BKF                        0x000F0000U            /*!<Break Filter for Break1 */
-#define  TIM_BDTR_BK2F                       0x00F00000U            /*!<Break Filter for Break2 */
-#define  TIM_BDTR_BK2E                       0x01000000U            /*!<Break enable for Break2 */
-#define  TIM_BDTR_BK2P                       0x02000000U            /*!<Break Polarity for Break2 */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
-
-#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
-
-/*******************  Bit definition for TIM_OR regiter  *********************/
-#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
-#define TIM_OR_ITR1_RMP                      0x0C00U            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
-#define TIM_OR_ITR1_RMP_0                    0x0400U            /*!<Bit 0 */
-#define TIM_OR_ITR1_RMP_1                    0x0800U            /*!<Bit 1 */
-
-/******************  Bit definition for TIM_CCMR3 register  *******************/
-#define  TIM_CCMR3_OC5FE                     0x00000004U            /*!<Output Compare 5 Fast enable */
-#define  TIM_CCMR3_OC5PE                     0x00000008U            /*!<Output Compare 5 Preload enable */
-
-#define  TIM_CCMR3_OC5M                      0x00010070U            /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
-#define  TIM_CCMR3_OC5M_0                    0x00000010U            /*!<Bit 0 */
-#define  TIM_CCMR3_OC5M_1                    0x00000020U            /*!<Bit 1 */
-#define  TIM_CCMR3_OC5M_2                    0x00000040U            /*!<Bit 2 */
-#define  TIM_CCMR3_OC5M_3                    0x00010000U            /*!<Bit 3 */
-
-#define  TIM_CCMR3_OC5CE                     0x00000080U            /*!<Output Compare 5 Clear Enable */
-
-#define  TIM_CCMR3_OC6FE                     0x00000400U            /*!<Output Compare 4 Fast enable */
-#define  TIM_CCMR3_OC6PE                     0x00000800U            /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR3_OC6M                      0x01007000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR3_OC6M_0                    0x00001000U            /*!<Bit 0 */
-#define  TIM_CCMR3_OC6M_1                    0x00002000U            /*!<Bit 1 */
-#define  TIM_CCMR3_OC6M_2                    0x00004000U            /*!<Bit 2 */
-#define  TIM_CCMR3_OC6M_3                    0x01000000U            /*!<Bit 3 */
-
-#define  TIM_CCMR3_OC6CE                     0x00008000U            /*!<Output Compare 4 Clear Enable */
-
-/*******************  Bit definition for TIM_CCR5 register  *******************/
-#define  TIM_CCR5_CCR5                       0xFFFFFFFFU        /*!<Capture/Compare 5 Value */
-#define  TIM_CCR5_GC5C1                      0x20000000U        /*!<Group Channel 5 and Channel 1 */
-#define  TIM_CCR5_GC5C2                      0x40000000U        /*!<Group Channel 5 and Channel 2 */
-#define  TIM_CCR5_GC5C3                      0x80000000U        /*!<Group Channel 5 and Channel 3 */
-
-/*******************  Bit definition for TIM_CCR6 register  *******************/
-#define  TIM_CCR6_CCR6                       ((uint16_t)0xFFFFU)            /*!<Capture/Compare 6 Value */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Low Power Timer (LPTIM)                            */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for LPTIM_ISR register  *******************/
-#define  LPTIM_ISR_CMPM                         0x00000001U            /*!< Compare match                       */
-#define  LPTIM_ISR_ARRM                         0x00000002U            /*!< Autoreload match                    */
-#define  LPTIM_ISR_EXTTRIG                      0x00000004U            /*!< External trigger edge event         */
-#define  LPTIM_ISR_CMPOK                        0x00000008U            /*!< Compare register update OK          */
-#define  LPTIM_ISR_ARROK                        0x00000010U            /*!< Autoreload register update OK       */
-#define  LPTIM_ISR_UP                           0x00000020U            /*!< Counter direction change down to up */
-#define  LPTIM_ISR_DOWN                         0x00000040U            /*!< Counter direction change up to down */
-
-/******************  Bit definition for LPTIM_ICR register  *******************/
-#define  LPTIM_ICR_CMPMCF                       0x00000001U            /*!< Compare match Clear Flag                       */
-#define  LPTIM_ICR_ARRMCF                       0x00000002U            /*!< Autoreload match Clear Flag                    */
-#define  LPTIM_ICR_EXTTRIGCF                    0x00000004U            /*!< External trigger edge event Clear Flag         */
-#define  LPTIM_ICR_CMPOKCF                      0x00000008U            /*!< Compare register update OK Clear Flag          */
-#define  LPTIM_ICR_ARROKCF                      0x00000010U            /*!< Autoreload register update OK Clear Flag       */
-#define  LPTIM_ICR_UPCF                         0x00000020U            /*!< Counter direction change down to up Clear Flag */
-#define  LPTIM_ICR_DOWNCF                       0x00000040U            /*!< Counter direction change up to down Clear Flag */
-
-/******************  Bit definition for LPTIM_IER register *******************/
-#define  LPTIM_IER_CMPMIE                       0x00000001U            /*!< Compare match Interrupt Enable                       */
-#define  LPTIM_IER_ARRMIE                       0x00000002U            /*!< Autoreload match Interrupt Enable                    */
-#define  LPTIM_IER_EXTTRIGIE                    0x00000004U            /*!< External trigger edge event Interrupt Enable         */
-#define  LPTIM_IER_CMPOKIE                      0x00000008U            /*!< Compare register update OK Interrupt Enable          */
-#define  LPTIM_IER_ARROKIE                      0x00000010U            /*!< Autoreload register update OK Interrupt Enable       */
-#define  LPTIM_IER_UPIE                         0x00000020U            /*!< Counter direction change down to up Interrupt Enable */
-#define  LPTIM_IER_DOWNIE                       0x00000040U            /*!< Counter direction change up to down Interrupt Enable */
-
-/******************  Bit definition for LPTIM_CFGR register*******************/
-#define  LPTIM_CFGR_CKSEL                       0x00000001U             /*!< Clock selector */
-
-#define  LPTIM_CFGR_CKPOL                       0x00000006U             /*!< CKPOL[1:0] bits (Clock polarity) */
-#define  LPTIM_CFGR_CKPOL_0                     0x00000002U             /*!< Bit 0 */
-#define  LPTIM_CFGR_CKPOL_1                     0x00000004U             /*!< Bit 1 */
-
-#define  LPTIM_CFGR_CKFLT                       0x00000018U             /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
-#define  LPTIM_CFGR_CKFLT_0                     0x00000008U             /*!< Bit 0 */
-#define  LPTIM_CFGR_CKFLT_1                     0x00000010U             /*!< Bit 1 */
-
-#define  LPTIM_CFGR_TRGFLT                      0x000000C0U             /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
-#define  LPTIM_CFGR_TRGFLT_0                    0x00000040U             /*!< Bit 0 */
-#define  LPTIM_CFGR_TRGFLT_1                    0x00000080U             /*!< Bit 1 */
-
-#define  LPTIM_CFGR_PRESC                       0x00000E00U             /*!< PRESC[2:0] bits (Clock prescaler) */
-#define  LPTIM_CFGR_PRESC_0                     0x00000200U             /*!< Bit 0 */
-#define  LPTIM_CFGR_PRESC_1                     0x00000400U             /*!< Bit 1 */
-#define  LPTIM_CFGR_PRESC_2                     0x00000800U             /*!< Bit 2 */
-
-#define  LPTIM_CFGR_TRIGSEL                     0x0000E000U             /*!< TRIGSEL[2:0]] bits (Trigger selector) */
-#define  LPTIM_CFGR_TRIGSEL_0                   0x00002000U             /*!< Bit 0 */
-#define  LPTIM_CFGR_TRIGSEL_1                   0x00004000U             /*!< Bit 1 */
-#define  LPTIM_CFGR_TRIGSEL_2                   0x00008000U             /*!< Bit 2 */
-
-#define  LPTIM_CFGR_TRIGEN                      0x00060000U             /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
-#define  LPTIM_CFGR_TRIGEN_0                    0x00020000U             /*!< Bit 0 */
-#define  LPTIM_CFGR_TRIGEN_1                    0x00040000U             /*!< Bit 1 */
-
-#define  LPTIM_CFGR_TIMOUT                      0x00080000U             /*!< Timout enable           */
-#define  LPTIM_CFGR_WAVE                        0x00100000U             /*!< Waveform shape          */
-#define  LPTIM_CFGR_WAVPOL                      0x00200000U             /*!< Waveform shape polarity */
-#define  LPTIM_CFGR_PRELOAD                     0x00400000U             /*!< Reg update mode         */
-#define  LPTIM_CFGR_COUNTMODE                   0x00800000U             /*!< Counter mode enable     */
-#define  LPTIM_CFGR_ENC                         0x01000000U             /*!< Encoder mode enable     */
-
-/******************  Bit definition for LPTIM_CR register  ********************/
-#define  LPTIM_CR_ENABLE                        0x00000001U             /*!< LPTIMer enable                 */
-#define  LPTIM_CR_SNGSTRT                       0x00000002U             /*!< Timer start in single mode     */
-#define  LPTIM_CR_CNTSTRT                       0x00000004U             /*!< Timer start in continuous mode */
-
-/******************  Bit definition for LPTIM_CMP register *******************/
-#define  LPTIM_CMP_CMP                          0x0000FFFFU             /*!< Compare register     */
-
-/******************  Bit definition for LPTIM_ARR register *******************/
-#define  LPTIM_ARR_ARR                          0x0000FFFFU             /*!< Auto reload register */
-
-/******************  Bit definition for LPTIM_CNT register *******************/
-#define  LPTIM_CNT_CNT                          0x0000FFFFU             /*!< Counter register     */
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_UE                        0x00000001U            /*!< USART Enable                                    */
-#define  USART_CR1_RE                        0x00000004U            /*!< Receiver Enable                                 */
-#define  USART_CR1_TE                        0x00000008U            /*!< Transmitter Enable                              */
-#define  USART_CR1_IDLEIE                    0x00000010U            /*!< IDLE Interrupt Enable                           */
-#define  USART_CR1_RXNEIE                    0x00000020U            /*!< RXNE Interrupt Enable                           */
-#define  USART_CR1_TCIE                      0x00000040U            /*!< Transmission Complete Interrupt Enable          */
-#define  USART_CR1_TXEIE                     0x00000080U            /*!< TXE Interrupt Enable                            */
-#define  USART_CR1_PEIE                      0x00000100U            /*!< PE Interrupt Enable                             */
-#define  USART_CR1_PS                        0x00000200U            /*!< Parity Selection                                */
-#define  USART_CR1_PCE                       0x00000400U            /*!< Parity Control Enable                           */
-#define  USART_CR1_WAKE                      0x00000800U            /*!< Receiver Wakeup method                          */
-#define  USART_CR1_M                         0x10001000U            /*!< Word length                                     */
-#define  USART_CR1_M_0                       0x00001000U            /*!< Word length - Bit 0                             */
-#define  USART_CR1_MME                       0x00002000U            /*!< Mute Mode Enable                                */
-#define  USART_CR1_CMIE                      0x00004000U            /*!< Character match interrupt enable                */
-#define  USART_CR1_OVER8                     0x00008000U            /*!< Oversampling by 8-bit or 16-bit mode            */
-#define  USART_CR1_DEDT                      0x001F0000U            /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
-#define  USART_CR1_DEDT_0                    0x00010000U            /*!< Bit 0 */
-#define  USART_CR1_DEDT_1                    0x00020000U            /*!< Bit 1 */
-#define  USART_CR1_DEDT_2                    0x00040000U            /*!< Bit 2 */
-#define  USART_CR1_DEDT_3                    0x00080000U            /*!< Bit 3 */
-#define  USART_CR1_DEDT_4                    0x00100000U            /*!< Bit 4 */
-#define  USART_CR1_DEAT                      0x03E00000U            /*!< DEAT[4:0] bits (Driver Enable Assertion Time)   */
-#define  USART_CR1_DEAT_0                    0x00200000U            /*!< Bit 0 */
-#define  USART_CR1_DEAT_1                    0x00400000U            /*!< Bit 1 */
-#define  USART_CR1_DEAT_2                    0x00800000U            /*!< Bit 2 */
-#define  USART_CR1_DEAT_3                    0x01000000U            /*!< Bit 3 */
-#define  USART_CR1_DEAT_4                    0x02000000U            /*!< Bit 4 */
-#define  USART_CR1_RTOIE                     0x04000000U            /*!< Receive Time Out interrupt enable */
-#define  USART_CR1_EOBIE                     0x08000000U            /*!< End of Block interrupt enable     */
-#define  USART_CR1_M_1                       0x10000000U            /*!< Word length - Bit 1               */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADDM7                     0x00000010U            /*!< 7-bit or 4-bit Address Detection       */
-#define  USART_CR2_LBDL                      0x00000020U            /*!< LIN Break Detection Length             */
-#define  USART_CR2_LBDIE                     0x00000040U            /*!< LIN Break Detection Interrupt Enable   */
-#define  USART_CR2_LBCL                      0x00000100U            /*!< Last Bit Clock pulse                   */
-#define  USART_CR2_CPHA                      0x00000200U            /*!< Clock Phase                            */
-#define  USART_CR2_CPOL                      0x00000400U            /*!< Clock Polarity                         */
-#define  USART_CR2_CLKEN                     0x00000800U            /*!< Clock Enable                           */
-#define  USART_CR2_STOP                      0x00003000U            /*!< STOP[1:0] bits (STOP bits)             */
-#define  USART_CR2_STOP_0                    0x00001000U            /*!< Bit 0 */
-#define  USART_CR2_STOP_1                    0x00002000U            /*!< Bit 1 */
-#define  USART_CR2_LINEN                     0x00004000U            /*!< LIN mode enable                        */
-#define  USART_CR2_SWAP                      0x00008000U            /*!< SWAP TX/RX pins                        */
-#define  USART_CR2_RXINV                     0x00010000U            /*!< RX pin active level inversion          */
-#define  USART_CR2_TXINV                     0x00020000U            /*!< TX pin active level inversion          */
-#define  USART_CR2_DATAINV                   0x00040000U            /*!< Binary data inversion                  */
-#define  USART_CR2_MSBFIRST                  0x00080000U            /*!< Most Significant Bit First             */
-#define  USART_CR2_ABREN                     0x00100000U            /*!< Auto Baud-Rate Enable                  */
-#define  USART_CR2_ABRMODE                   0x00600000U            /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
-#define  USART_CR2_ABRMODE_0                 0x00200000U            /*!< Bit 0 */
-#define  USART_CR2_ABRMODE_1                 0x00400000U            /*!< Bit 1 */
-#define  USART_CR2_RTOEN                     0x00800000U            /*!< Receiver Time-Out enable  */
-#define  USART_CR2_ADD                       0xFF000000U            /*!< Address of the USART node */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       0x00000001U            /*!< Error Interrupt Enable                         */
-#define  USART_CR3_IREN                      0x00000002U            /*!< IrDA mode Enable                               */
-#define  USART_CR3_IRLP                      0x00000004U            /*!< IrDA Low-Power                                 */
-#define  USART_CR3_HDSEL                     0x00000008U            /*!< Half-Duplex Selection                          */
-#define  USART_CR3_NACK                      0x00000010U            /*!< SmartCard NACK enable                          */
-#define  USART_CR3_SCEN                      0x00000020U            /*!< SmartCard mode enable                          */
-#define  USART_CR3_DMAR                      0x00000040U            /*!< DMA Enable Receiver                            */
-#define  USART_CR3_DMAT                      0x00000080U            /*!< DMA Enable Transmitter                         */
-#define  USART_CR3_RTSE                      0x00000100U            /*!< RTS Enable                                     */
-#define  USART_CR3_CTSE                      0x00000200U            /*!< CTS Enable                                     */
-#define  USART_CR3_CTSIE                     0x00000400U            /*!< CTS Interrupt Enable                           */
-#define  USART_CR3_ONEBIT                    0x00000800U            /*!< One sample bit method enable                   */
-#define  USART_CR3_OVRDIS                    0x00001000U            /*!< Overrun Disable                                */
-#define  USART_CR3_DDRE                      0x00002000U            /*!< DMA Disable on Reception Error                 */
-#define  USART_CR3_DEM                       0x00004000U            /*!< Driver Enable Mode                             */
-#define  USART_CR3_DEP                       0x00008000U            /*!< Driver Enable Polarity Selection               */
-#define  USART_CR3_SCARCNT                   0x000E0000U            /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
-#define  USART_CR3_SCARCNT_0                 0x00020000U            /*!< Bit 0 */
-#define  USART_CR3_SCARCNT_1                 0x00040000U            /*!< Bit 1 */
-#define  USART_CR3_SCARCNT_2                 0x00080000U            /*!< Bit 2 */
-
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_FRACTION              0x000FU                /*!< Fraction of USARTDIV */
-#define  USART_BRR_DIV_MANTISSA              0xFFF0U                /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      0x00FFU                /*!< PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_GT                       0xFF00U                /*!< GT[7:0] bits (Guard time value) */
-
-
-/*******************  Bit definition for USART_RTOR register  *****************/
-#define  USART_RTOR_RTO                      0x00FFFFFFU            /*!< Receiver Time Out Value */
-#define  USART_RTOR_BLEN                     0xFF000000U            /*!< Block Length */
-
-/*******************  Bit definition for USART_RQR register  ******************/
-#define  USART_RQR_ABRRQ                     0x0001U                /*!< Auto-Baud Rate Request      */
-#define  USART_RQR_SBKRQ                     0x0002U                /*!< Send Break Request          */
-#define  USART_RQR_MMRQ                      0x0004U                /*!< Mute Mode Request           */
-#define  USART_RQR_RXFRQ                     0x0008U                /*!< Receive Data flush Request  */
-#define  USART_RQR_TXFRQ                     0x0010U                /*!< Transmit data flush Request */
-
-/*******************  Bit definition for USART_ISR register  ******************/
-#define  USART_ISR_PE                        0x00000001U            /*!< Parity Error                        */
-#define  USART_ISR_FE                        0x00000002U            /*!< Framing Error                       */
-#define  USART_ISR_NE                        0x00000004U            /*!< Noise detected Flag                 */
-#define  USART_ISR_ORE                       0x00000008U            /*!< OverRun Error                       */
-#define  USART_ISR_IDLE                      0x00000010U            /*!< IDLE line detected                  */
-#define  USART_ISR_RXNE                      0x00000020U            /*!< Read Data Register Not Empty        */
-#define  USART_ISR_TC                        0x00000040U            /*!< Transmission Complete               */
-#define  USART_ISR_TXE                       0x00000080U            /*!< Transmit Data Register Empty        */
-#define  USART_ISR_LBDF                      0x00000100U            /*!< LIN Break Detection Flag            */
-#define  USART_ISR_CTSIF                     0x00000200U            /*!< CTS interrupt flag                  */
-#define  USART_ISR_CTS                       0x00000400U            /*!< CTS flag                            */
-#define  USART_ISR_RTOF                      0x00000800U            /*!< Receiver Time Out                   */
-#define  USART_ISR_EOBF                      0x00001000U            /*!< End Of Block Flag                   */
-#define  USART_ISR_ABRE                      0x00004000U            /*!< Auto-Baud Rate Error                */
-#define  USART_ISR_ABRF                      0x00008000U            /*!< Auto-Baud Rate Flag                 */
-#define  USART_ISR_BUSY                      0x00010000U            /*!< Busy Flag                           */
-#define  USART_ISR_CMF                       0x00020000U            /*!< Character Match Flag                */
-#define  USART_ISR_SBKF                      0x00040000U            /*!< Send Break Flag                     */
-#define  USART_ISR_RWU                       0x00080000U            /*!< Receive Wake Up from mute mode Flag */
-#define  USART_ISR_WUF                       0x00100000U            /*!< Wake Up from stop mode Flag         */
-#define  USART_ISR_TEACK                     0x00200000U            /*!< Transmit Enable Acknowledge Flag    */
-#define  USART_ISR_REACK                     0x00400000U            /*!< Receive Enable Acknowledge Flag     */
-
-/* Legacy define */
-#define  USART_ISR_LBD                       USART_ISR_LBDF
-
-/*******************  Bit definition for USART_ICR register  ******************/
-#define  USART_ICR_PECF                      0x00000001U            /*!< Parity Error Clear Flag             */
-#define  USART_ICR_FECF                      0x00000002U            /*!< Framing Error Clear Flag            */
-#define  USART_ICR_NCF                       0x00000004U            /*!< Noise detected Clear Flag           */
-#define  USART_ICR_ORECF                     0x00000008U            /*!< OverRun Error Clear Flag            */
-#define  USART_ICR_IDLECF                    0x00000010U            /*!< IDLE line detected Clear Flag       */
-#define  USART_ICR_TCCF                      0x00000040U            /*!< Transmission Complete Clear Flag    */
-#define  USART_ICR_LBDCF                     0x00000100U            /*!< LIN Break Detection Clear Flag      */
-#define  USART_ICR_CTSCF                     0x00000200U            /*!< CTS Interrupt Clear Flag            */
-#define  USART_ICR_RTOCF                     0x00000800U            /*!< Receiver Time Out Clear Flag        */
-#define  USART_ICR_EOBCF                     0x00001000U            /*!< End Of Block Clear Flag             */
-#define  USART_ICR_CMCF                      0x00020000U            /*!< Character Match Clear Flag          */
-#define  USART_ICR_WUCF                      0x00100000U            /*!< Wake Up from stop mode Clear Flag   */
-
-/*******************  Bit definition for USART_RDR register  ******************/
-#define  USART_RDR_RDR                       0x01FFU                /*!< RDR[8:0] bits (Receive Data value) */
-
-/*******************  Bit definition for USART_TDR register  ******************/
-#define  USART_TDR_TDR                       0x01FFU                /*!< TDR[8:0] bits (Transmit Data value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Window WATCHDOG                                 */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                            0x7FU                 /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T_0                          0x01U                 /*!<Bit 0 */
-#define  WWDG_CR_T_1                          0x02U                 /*!<Bit 1 */
-#define  WWDG_CR_T_2                          0x04U                 /*!<Bit 2 */
-#define  WWDG_CR_T_3                          0x08U                 /*!<Bit 3 */
-#define  WWDG_CR_T_4                          0x10U                 /*!<Bit 4 */
-#define  WWDG_CR_T_5                          0x20U                 /*!<Bit 5 */
-#define  WWDG_CR_T_6                          0x40U                 /*!<Bit 6 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0                           WWDG_CR_T_0                      /*!<Bit 0 */
-#define  WWDG_CR_T1                           WWDG_CR_T_1                      /*!<Bit 1 */
-#define  WWDG_CR_T2                           WWDG_CR_T_2                      /*!<Bit 2 */
-#define  WWDG_CR_T3                           WWDG_CR_T_3                      /*!<Bit 3 */
-#define  WWDG_CR_T4                           WWDG_CR_T_4                      /*!<Bit 4 */
-#define  WWDG_CR_T5                           WWDG_CR_T_5                      /*!<Bit 5 */
-#define  WWDG_CR_T6                           WWDG_CR_T_6                      /*!<Bit 6 */
-
-#define  WWDG_CR_WDGA                        0x80U                  /*!<Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          0x007FU                /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W_0                        0x0001U                /*!<Bit 0 */
-#define  WWDG_CFR_W_1                        0x0002U                /*!<Bit 1 */
-#define  WWDG_CFR_W_2                        0x0004U                /*!<Bit 2 */
-#define  WWDG_CFR_W_3                        0x0008U                /*!<Bit 3 */
-#define  WWDG_CFR_W_4                        0x0010U                /*!<Bit 4 */
-#define  WWDG_CFR_W_5                        0x0020U                /*!<Bit 5 */
-#define  WWDG_CFR_W_6                        0x0040U                /*!<Bit 6 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0                         WWDG_CFR_W_0                      /*!<Bit 0 */
-#define  WWDG_CFR_W1                         WWDG_CFR_W_1                      /*!<Bit 1 */
-#define  WWDG_CFR_W2                         WWDG_CFR_W_2                      /*!<Bit 2 */
-#define  WWDG_CFR_W3                         WWDG_CFR_W_3                      /*!<Bit 3 */
-#define  WWDG_CFR_W4                         WWDG_CFR_W_4                      /*!<Bit 4 */
-#define  WWDG_CFR_W5                         WWDG_CFR_W_5                      /*!<Bit 5 */
-#define  WWDG_CFR_W6                         WWDG_CFR_W_6                      /*!<Bit 6 */
-
-#define  WWDG_CFR_WDGTB                      0x0180U                /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB_0                    0x0080U                /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB_1                    0x0100U                /*!<Bit 1 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0                  /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1                  /*!<Bit 1 */
-
-#define  WWDG_CFR_EWI                        0x0200U               /*!<Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        0x01U                  /*!<Early Wakeup Interrupt Flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                DBG                                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
-#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
-
-/********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
-#define  DBGMCU_CR_DBG_STOP                  0x00000002U
-#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
-#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
-
-#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
-#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U /*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U /*!<Bit 1 */
-
-/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            0x00000001U
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            0x00000002U
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            0x00000004U
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            0x00000020U
-#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           0x00000040U
-#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           0x00000080U
-#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           0x00000100U
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
-#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
-
-/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP            0x00000001U
-#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP            0x00000002U
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP            0x00010000U
-#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP           0x00020000U
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP           0x00040000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                Ethernet MAC Registers bits definitions                     */
-/*                                                                            */
-/******************************************************************************/
-/* Bit definition for Ethernet MAC Control Register register */
-#define ETH_MACCR_WD              0x00800000U  /* Watchdog disable */
-#define ETH_MACCR_JD              0x00400000U  /* Jabber disable */
-#define ETH_MACCR_IFG             0x000E0000U  /* Inter-frame gap */
-#define ETH_MACCR_IFG_96Bit       0x00000000U  /* Minimum IFG between frames during transmission is 96Bit */
-#define ETH_MACCR_IFG_88Bit       0x00020000U  /* Minimum IFG between frames during transmission is 88Bit */
-#define ETH_MACCR_IFG_80Bit       0x00040000U  /* Minimum IFG between frames during transmission is 80Bit */
-#define ETH_MACCR_IFG_72Bit       0x00060000U  /* Minimum IFG between frames during transmission is 72Bit */
-#define ETH_MACCR_IFG_64Bit       0x00080000U  /* Minimum IFG between frames during transmission is 64Bit */
-#define ETH_MACCR_IFG_56Bit       0x000A0000U  /* Minimum IFG between frames during transmission is 56Bit */
-#define ETH_MACCR_IFG_48Bit       0x000C0000U  /* Minimum IFG between frames during transmission is 48Bit */
-#define ETH_MACCR_IFG_40Bit       0x000E0000U  /* Minimum IFG between frames during transmission is 40Bit */
-#define ETH_MACCR_CSD             0x00010000U  /* Carrier sense disable (during transmission) */
-#define ETH_MACCR_FES             0x00004000U  /* Fast ethernet speed */
-#define ETH_MACCR_ROD             0x00002000U  /* Receive own disable */
-#define ETH_MACCR_LM              0x00001000U  /* loopback mode */
-#define ETH_MACCR_DM              0x00000800U  /* Duplex mode */
-#define ETH_MACCR_IPCO            0x00000400U  /* IP Checksum offload */
-#define ETH_MACCR_RD              0x00000200U  /* Retry disable */
-#define ETH_MACCR_APCS            0x00000080U  /* Automatic Pad/CRC stripping */
-#define ETH_MACCR_BL              0x00000060U  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
-                                                       a transmission attempt during retries after a collision: 0 =< r <2^k */
-#define ETH_MACCR_BL_10           0x00000000U  /* k = min (n, 10) */
-#define ETH_MACCR_BL_8            0x00000020U  /* k = min (n, 8) */
-#define ETH_MACCR_BL_4            0x00000040U  /* k = min (n, 4) */
-#define ETH_MACCR_BL_1            0x00000060U  /* k = min (n, 1) */
-#define ETH_MACCR_DC              0x00000010U  /* Defferal check */
-#define ETH_MACCR_TE              0x00000008U  /* Transmitter enable */
-#define ETH_MACCR_RE              0x00000004U  /* Receiver enable */
-
-/* Bit definition for Ethernet MAC Frame Filter Register */
-#define ETH_MACFFR_RA             0x80000000U  /* Receive all */
-#define ETH_MACFFR_HPF            0x00000400U  /* Hash or perfect filter */
-#define ETH_MACFFR_SAF            0x00000200U  /* Source address filter enable */
-#define ETH_MACFFR_SAIF           0x00000100U  /* SA inverse filtering */
-#define ETH_MACFFR_PCF            0x000000C0U  /* Pass control frames: 3 cases */
-#define ETH_MACFFR_PCF_BlockAll                0x00000040U  /* MAC filters all control frames from reaching the application */
-#define ETH_MACFFR_PCF_ForwardAll              0x00000080U  /* MAC forwards all control frames to application even if they fail the Address Filter */
-#define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U  /* MAC forwards control frames that pass the Address Filter. */
-#define ETH_MACFFR_BFD             0x00000020U  /* Broadcast frame disable */
-#define ETH_MACFFR_PAM             0x00000010U  /* Pass all mutlicast */
-#define ETH_MACFFR_DAIF            0x00000008U  /* DA Inverse filtering */
-#define ETH_MACFFR_HM              0x00000004U  /* Hash multicast */
-#define ETH_MACFFR_HU              0x00000002U  /* Hash unicast */
-#define ETH_MACFFR_PM              0x00000001U  /* Promiscuous mode */
-
-/* Bit definition for Ethernet MAC Hash Table High Register */
-#define ETH_MACHTHR_HTH            0xFFFFFFFFU  /* Hash table high */
-
-/* Bit definition for Ethernet MAC Hash Table Low Register */
-#define ETH_MACHTLR_HTL            0xFFFFFFFFU  /* Hash table low */
-
-/* Bit definition for Ethernet MAC MII Address Register */
-#define ETH_MACMIIAR_PA            0x0000F800U  /* Physical layer address */
-#define ETH_MACMIIAR_MR            0x000007C0U  /* MII register in the selected PHY */
-#define ETH_MACMIIAR_CR            0x0000001CU  /* CR clock range: 6 cases */
-#define ETH_MACMIIAR_CR_Div42      0x00000000U  /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
-#define ETH_MACMIIAR_CR_Div62      0x00000004U  /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
-#define ETH_MACMIIAR_CR_Div16      0x00000008U  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
-#define ETH_MACMIIAR_CR_Div26      0x0000000CU  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
-#define ETH_MACMIIAR_CR_Div102     0x00000010U  /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
-#define ETH_MACMIIAR_MW            0x00000002U  /* MII write */
-#define ETH_MACMIIAR_MB            0x00000001U  /* MII busy */
-
-/* Bit definition for Ethernet MAC MII Data Register */
-#define ETH_MACMIIDR_MD            0x0000FFFFU  /* MII data: read/write data from/to PHY */
-
-/* Bit definition for Ethernet MAC Flow Control Register */
-#define ETH_MACFCR_PT              0xFFFF0000U  /* Pause time */
-#define ETH_MACFCR_ZQPD            0x00000080U  /* Zero-quanta pause disable */
-#define ETH_MACFCR_PLT             0x00000030U  /* Pause low threshold: 4 cases */
-#define ETH_MACFCR_PLT_Minus4      0x00000000U  /* Pause time minus 4 slot times */
-#define ETH_MACFCR_PLT_Minus28     0x00000010U  /* Pause time minus 28 slot times */
-#define ETH_MACFCR_PLT_Minus144    0x00000020U  /* Pause time minus 144 slot times */
-#define ETH_MACFCR_PLT_Minus256    0x00000030U  /* Pause time minus 256 slot times */
-#define ETH_MACFCR_UPFD            0x00000008U  /* Unicast pause frame detect */
-#define ETH_MACFCR_RFCE            0x00000004U  /* Receive flow control enable */
-#define ETH_MACFCR_TFCE            0x00000002U  /* Transmit flow control enable */
-#define ETH_MACFCR_FCBBPA          0x00000001U  /* Flow control busy/backpressure activate */
-
-/* Bit definition for Ethernet MAC VLAN Tag Register */
-#define ETH_MACVLANTR_VLANTC       0x00010000U  /* 12-bit VLAN tag comparison */
-#define ETH_MACVLANTR_VLANTI       0x0000FFFFU  /* VLAN tag identifier (for receive frames) */
-
-/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
-#define ETH_MACRWUFFR_D            0xFFFFFFFFU  /* Wake-up frame filter register data */
-/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
-   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
-/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
-   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
-   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
-   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
-   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
-                              RSVD - Filter1 Command - RSVD - Filter0 Command
-   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
-   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
-   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
-
-/* Bit definition for Ethernet MAC PMT Control and Status Register */
-#define ETH_MACPMTCSR_WFFRPR       0x80000000U  /* Wake-Up Frame Filter Register Pointer Reset */
-#define ETH_MACPMTCSR_GU           0x00000200U  /* Global Unicast */
-#define ETH_MACPMTCSR_WFR          0x00000040U  /* Wake-Up Frame Received */
-#define ETH_MACPMTCSR_MPR          0x00000020U  /* Magic Packet Received */
-#define ETH_MACPMTCSR_WFE          0x00000004U  /* Wake-Up Frame Enable */
-#define ETH_MACPMTCSR_MPE          0x00000002U  /* Magic Packet Enable */
-#define ETH_MACPMTCSR_PD           0x00000001U  /* Power Down */
-
-/* Bit definition for Ethernet MAC Status Register */
-#define ETH_MACSR_TSTS      0x00000200U  /* Time stamp trigger status */
-#define ETH_MACSR_MMCTS     0x00000040U  /* MMC transmit status */
-#define ETH_MACSR_MMMCRS    0x00000020U  /* MMC receive status */
-#define ETH_MACSR_MMCS      0x00000010U  /* MMC status */
-#define ETH_MACSR_PMTS      0x00000008U  /* PMT status */
-
-/* Bit definition for Ethernet MAC Interrupt Mask Register */
-#define ETH_MACIMR_TSTIM     0x00000200U  /* Time stamp trigger interrupt mask */
-#define ETH_MACIMR_PMTIM     0x00000008U  /* PMT interrupt mask */
-
-/* Bit definition for Ethernet MAC Address0 High Register */
-#define ETH_MACA0HR_MACA0H   0x0000FFFFU  /* MAC address0 high */
-
-/* Bit definition for Ethernet MAC Address0 Low Register */
-#define ETH_MACA0LR_MACA0L   0xFFFFFFFFU  /* MAC address0 low */
-
-/* Bit definition for Ethernet MAC Address1 High Register */
-#define ETH_MACA1HR_AE       0x80000000U  /* Address enable */
-#define ETH_MACA1HR_SA       0x40000000U  /* Source address */
-#define ETH_MACA1HR_MBC      0x3F000000U  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
-  #define ETH_MACA1HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA1HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA1HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA1HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA1HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA1HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [7:0] */
-#define ETH_MACA1HR_MACA1H            0x0000FFFFU  /* MAC address1 high */
-
-/* Bit definition for Ethernet MAC Address1 Low Register */
-#define ETH_MACA1LR_MACA1L   0xFFFFFFFFU  /* MAC address1 low */
-
-/* Bit definition for Ethernet MAC Address2 High Register */
-#define ETH_MACA2HR_AE       0x80000000U  /* Address enable */
-#define ETH_MACA2HR_SA       0x40000000U  /* Source address */
-#define ETH_MACA2HR_MBC      0x3F000000U  /* Mask byte control */
-  #define ETH_MACA2HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA2HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA2HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA2HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA2HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA2HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA2HR_MACA2H   0x0000FFFFU  /* MAC address1 high */
-
-/* Bit definition for Ethernet MAC Address2 Low Register */
-#define ETH_MACA2LR_MACA2L   0xFFFFFFFFU  /* MAC address2 low */
-
-/* Bit definition for Ethernet MAC Address3 High Register */
-#define ETH_MACA3HR_AE       0x80000000U  /* Address enable */
-#define ETH_MACA3HR_SA       0x40000000U  /* Source address */
-#define ETH_MACA3HR_MBC      0x3F000000U  /* Mask byte control */
-  #define ETH_MACA3HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA3HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA3HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA3HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA3HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA3HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA3HR_MACA3H   0x0000FFFFU  /* MAC address3 high */
-
-/* Bit definition for Ethernet MAC Address3 Low Register */
-#define ETH_MACA3LR_MACA3L   0xFFFFFFFFU  /* MAC address3 low */
-
-/******************************************************************************/
-/*                Ethernet MMC Registers bits definition                      */
-/******************************************************************************/
-
-/* Bit definition for Ethernet MMC Contol Register */
-#define ETH_MMCCR_MCFHP      0x00000020U  /* MMC counter Full-Half preset */
-#define ETH_MMCCR_MCP        0x00000010U  /* MMC counter preset */
-#define ETH_MMCCR_MCF        0x00000008U  /* MMC Counter Freeze */
-#define ETH_MMCCR_ROR        0x00000004U  /* Reset on Read */
-#define ETH_MMCCR_CSR        0x00000002U  /* Counter Stop Rollover */
-#define ETH_MMCCR_CR         0x00000001U  /* Counters Reset */
-
-/* Bit definition for Ethernet MMC Receive Interrupt Register */
-#define ETH_MMCRIR_RGUFS     0x00020000U  /* Set when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIR_RFAES     0x00000040U  /* Set when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIR_RFCES     0x00000020U  /* Set when Rx crc error counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmit Interrupt Register */
-#define ETH_MMCTIR_TGFS      0x00200000U  /* Set when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFMSCS   0x00008000U  /* Set when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFSCS    0x00004000U  /* Set when Tx good single col counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
-#define ETH_MMCRIMR_RGUFM    0x00020000U  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFAEM    0x00000040U  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFCEM    0x00000020U  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
-#define ETH_MMCTIMR_TGFM     0x00200000U  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFMSCM  0x00008000U  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFSCM   0x00004000U  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
-#define ETH_MMCTGFSCCR_TGFSCC     0xFFFFFFFFU  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
-#define ETH_MMCTGFMSCCR_TGFMSCC   0xFFFFFFFFU  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
-#define ETH_MMCTGFCR_TGFC    0xFFFFFFFFU  /* Number of good frames transmitted. */
-
-/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
-#define ETH_MMCRFCECR_RFCEC  0xFFFFFFFFU  /* Number of frames received with CRC error. */
-
-/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
-#define ETH_MMCRFAECR_RFAEC  0xFFFFFFFFU  /* Number of frames received with alignment (dribble) error */
-
-/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
-#define ETH_MMCRGUFCR_RGUFC  0xFFFFFFFFU  /* Number of good unicast frames received. */
-
-/******************************************************************************/
-/*               Ethernet PTP Registers bits definition                       */
-/******************************************************************************/
-
-/* Bit definition for Ethernet PTP Time Stamp Contol Register */
-#define ETH_PTPTSCR_TSCNT       0x00030000U  /* Time stamp clock node type */
-#define ETH_PTPTSSR_TSSMRME     0x00008000U  /* Time stamp snapshot for message relevant to master enable */
-#define ETH_PTPTSSR_TSSEME      0x00004000U  /* Time stamp snapshot for event message enable */
-#define ETH_PTPTSSR_TSSIPV4FE   0x00002000U  /* Time stamp snapshot for IPv4 frames enable */
-#define ETH_PTPTSSR_TSSIPV6FE   0x00001000U  /* Time stamp snapshot for IPv6 frames enable */
-#define ETH_PTPTSSR_TSSPTPOEFE  0x00000800U  /* Time stamp snapshot for PTP over ethernet frames enable */
-#define ETH_PTPTSSR_TSPTPPSV2E  0x00000400U  /* Time stamp PTP packet snooping for version2 format enable */
-#define ETH_PTPTSSR_TSSSR       0x00000200U  /* Time stamp Sub-seconds rollover */
-#define ETH_PTPTSSR_TSSARFE     0x00000100U  /* Time stamp snapshot for all received frames enable */
-
-#define ETH_PTPTSCR_TSARU       0x00000020U  /* Addend register update */
-#define ETH_PTPTSCR_TSITE       0x00000010U  /* Time stamp interrupt trigger enable */
-#define ETH_PTPTSCR_TSSTU       0x00000008U  /* Time stamp update */
-#define ETH_PTPTSCR_TSSTI       0x00000004U  /* Time stamp initialize */
-#define ETH_PTPTSCR_TSFCU       0x00000002U  /* Time stamp fine or coarse update */
-#define ETH_PTPTSCR_TSE         0x00000001U  /* Time stamp enable */
-
-/* Bit definition for Ethernet PTP Sub-Second Increment Register */
-#define ETH_PTPSSIR_STSSI      0x000000FFU   /* System time Sub-second increment value */
-
-/* Bit definition for Ethernet PTP Time Stamp High Register */
-#define ETH_PTPTSHR_STS        0xFFFFFFFFU   /* System Time second */
-
-/* Bit definition for Ethernet PTP Time Stamp Low Register */
-#define ETH_PTPTSLR_STPNS      0x80000000U  /* System Time Positive or negative time */
-#define ETH_PTPTSLR_STSS       0x7FFFFFFFU  /* System Time sub-seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp High Update Register */
-#define ETH_PTPTSHUR_TSUS      0xFFFFFFFFU  /* Time stamp update seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
-#define ETH_PTPTSLUR_TSUPNS    0x80000000U  /* Time stamp update Positive or negative time */
-#define ETH_PTPTSLUR_TSUSS     0x7FFFFFFFU  /* Time stamp update sub-seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp Addend Register */
-#define ETH_PTPTSAR_TSA        0xFFFFFFFFU  /* Time stamp addend */
-
-/* Bit definition for Ethernet PTP Target Time High Register */
-#define ETH_PTPTTHR_TTSH       0xFFFFFFFFU  /* Target time stamp high */
-
-/* Bit definition for Ethernet PTP Target Time Low Register */
-#define ETH_PTPTTLR_TTSL       0xFFFFFFFFU  /* Target time stamp low */
-
-/* Bit definition for Ethernet PTP Time Stamp Status Register */
-#define ETH_PTPTSSR_TSTTR      0x00000020U  /* Time stamp target time reached */
-#define ETH_PTPTSSR_TSSO       0x00000010U  /* Time stamp seconds overflow */
-
-/******************************************************************************/
-/*                 Ethernet DMA Registers bits definition                     */
-/******************************************************************************/
-
-/* Bit definition for Ethernet DMA Bus Mode Register */
-#define ETH_DMABMR_AAB        0x02000000U  /* Address-Aligned beats */
-#define ETH_DMABMR_FPM        0x01000000U  /* 4xPBL mode */
-#define ETH_DMABMR_USP        0x00800000U  /* Use separate PBL */
-#define ETH_DMABMR_RDP        0x007E0000U  /* RxDMA PBL */
-  #define ETH_DMABMR_RDP_1Beat    0x00020000U  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
-  #define ETH_DMABMR_RDP_2Beat    0x00040000U  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
-  #define ETH_DMABMR_RDP_4Beat    0x00080000U  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-  #define ETH_DMABMR_RDP_8Beat    0x00100000U  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-  #define ETH_DMABMR_RDP_16Beat   0x00200000U  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-  #define ETH_DMABMR_RDP_32Beat   0x00400000U  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
-  #define ETH_DMABMR_RDP_4xPBL_4Beat   0x01020000U  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-  #define ETH_DMABMR_RDP_4xPBL_8Beat   0x01040000U  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-  #define ETH_DMABMR_RDP_4xPBL_16Beat  0x01080000U  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-  #define ETH_DMABMR_RDP_4xPBL_32Beat  0x01100000U  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
-  #define ETH_DMABMR_RDP_4xPBL_64Beat  0x01200000U  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
-  #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
-#define ETH_DMABMR_FB        0x00010000U  /* Fixed Burst */
-#define ETH_DMABMR_RTPR      0x0000C000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_1_1     0x00000000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_2_1     0x00004000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_3_1     0x00008000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_4_1     0x0000C000U  /* Rx Tx priority ratio */
-#define ETH_DMABMR_PBL    0x00003F00U  /* Programmable burst length */
-  #define ETH_DMABMR_PBL_1Beat    0x00000100U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
-  #define ETH_DMABMR_PBL_2Beat    0x00000200U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
-  #define ETH_DMABMR_PBL_4Beat    0x00000400U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-  #define ETH_DMABMR_PBL_8Beat    0x00000800U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-  #define ETH_DMABMR_PBL_16Beat   0x00001000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-  #define ETH_DMABMR_PBL_32Beat   0x00002000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
-  #define ETH_DMABMR_PBL_4xPBL_4Beat   0x01000100U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-  #define ETH_DMABMR_PBL_4xPBL_8Beat   0x01000200U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-  #define ETH_DMABMR_PBL_4xPBL_16Beat  0x01000400U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-  #define ETH_DMABMR_PBL_4xPBL_32Beat  0x01000800U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
-  #define ETH_DMABMR_PBL_4xPBL_64Beat  0x01001000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
-  #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
-#define ETH_DMABMR_EDE       0x00000080U  /* Enhanced Descriptor Enable */
-#define ETH_DMABMR_DSL       0x0000007CU  /* Descriptor Skip Length */
-#define ETH_DMABMR_DA        0x00000002U  /* DMA arbitration scheme */
-#define ETH_DMABMR_SR        0x00000001U  /* Software reset */
-
-/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
-#define ETH_DMATPDR_TPD      0xFFFFFFFFU  /* Transmit poll demand */
-
-/* Bit definition for Ethernet DMA Receive Poll Demand Register */
-#define ETH_DMARPDR_RPD      0xFFFFFFFFU  /* Receive poll demand  */
-
-/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
-#define ETH_DMARDLAR_SRL     0xFFFFFFFFU  /* Start of receive list */
-
-/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
-#define ETH_DMATDLAR_STL     0xFFFFFFFFU  /* Start of transmit list */
-
-/* Bit definition for Ethernet DMA Status Register */
-#define ETH_DMASR_TSTS       0x20000000U  /* Time-stamp trigger status */
-#define ETH_DMASR_PMTS       0x10000000U  /* PMT status */
-#define ETH_DMASR_MMCS       0x08000000U  /* MMC status */
-#define ETH_DMASR_EBS        0x03800000U  /* Error bits status */
-  /* combination with EBS[2:0] for GetFlagStatus function */
-  #define ETH_DMASR_EBS_DescAccess      0x02000000U  /* Error bits 0-data buffer, 1-desc. access */
-  #define ETH_DMASR_EBS_ReadTransf      0x01000000U  /* Error bits 0-write trnsf, 1-read transfr */
-  #define ETH_DMASR_EBS_DataTransfTx    0x00800000U  /* Error bits 0-Rx DMA, 1-Tx DMA */
-#define ETH_DMASR_TPS         0x00700000U  /* Transmit process state */
-  #define ETH_DMASR_TPS_Stopped         0x00000000U  /* Stopped - Reset or Stop Tx Command issued  */
-  #define ETH_DMASR_TPS_Fetching        0x00100000U  /* Running - fetching the Tx descriptor */
-  #define ETH_DMASR_TPS_Waiting         0x00200000U  /* Running - waiting for status */
-  #define ETH_DMASR_TPS_Reading         0x00300000U  /* Running - reading the data from host memory */
-  #define ETH_DMASR_TPS_Suspended       0x00600000U  /* Suspended - Tx Descriptor unavailabe */
-  #define ETH_DMASR_TPS_Closing         0x00700000U  /* Running - closing Rx descriptor */
-#define ETH_DMASR_RPS         0x000E0000U  /* Receive process state */
-  #define ETH_DMASR_RPS_Stopped         0x00000000U  /* Stopped - Reset or Stop Rx Command issued */
-  #define ETH_DMASR_RPS_Fetching        0x00020000U  /* Running - fetching the Rx descriptor */
-  #define ETH_DMASR_RPS_Waiting         0x00060000U  /* Running - waiting for packet */
-  #define ETH_DMASR_RPS_Suspended       0x00080000U  /* Suspended - Rx Descriptor unavailable */
-  #define ETH_DMASR_RPS_Closing         0x000A0000U  /* Running - closing descriptor */
-  #define ETH_DMASR_RPS_Queuing         0x000E0000U  /* Running - queuing the recieve frame into host memory */
-#define ETH_DMASR_NIS        0x00010000U  /* Normal interrupt summary */
-#define ETH_DMASR_AIS        0x00008000U  /* Abnormal interrupt summary */
-#define ETH_DMASR_ERS        0x00004000U  /* Early receive status */
-#define ETH_DMASR_FBES       0x00002000U  /* Fatal bus error status */
-#define ETH_DMASR_ETS        0x00000400U  /* Early transmit status */
-#define ETH_DMASR_RWTS       0x00000200U  /* Receive watchdog timeout status */
-#define ETH_DMASR_RPSS       0x00000100U  /* Receive process stopped status */
-#define ETH_DMASR_RBUS       0x00000080U  /* Receive buffer unavailable status */
-#define ETH_DMASR_RS         0x00000040U  /* Receive status */
-#define ETH_DMASR_TUS        0x00000020U  /* Transmit underflow status */
-#define ETH_DMASR_ROS        0x00000010U  /* Receive overflow status */
-#define ETH_DMASR_TJTS       0x00000008U  /* Transmit jabber timeout status */
-#define ETH_DMASR_TBUS       0x00000004U  /* Transmit buffer unavailable status */
-#define ETH_DMASR_TPSS       0x00000002U  /* Transmit process stopped status */
-#define ETH_DMASR_TS         0x00000001U  /* Transmit status */
-
-/* Bit definition for Ethernet DMA Operation Mode Register */
-#define ETH_DMAOMR_DTCEFD    0x04000000U  /* Disable Dropping of TCP/IP checksum error frames */
-#define ETH_DMAOMR_RSF       0x02000000U  /* Receive store and forward */
-#define ETH_DMAOMR_DFRF      0x01000000U  /* Disable flushing of received frames */
-#define ETH_DMAOMR_TSF       0x00200000U  /* Transmit store and forward */
-#define ETH_DMAOMR_FTF       0x00100000U  /* Flush transmit FIFO */
-#define ETH_DMAOMR_TTC       0x0001C000U  /* Transmit threshold control */
-  #define ETH_DMAOMR_TTC_64Bytes       0x00000000U  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
-  #define ETH_DMAOMR_TTC_128Bytes      0x00004000U  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
-  #define ETH_DMAOMR_TTC_192Bytes      0x00008000U  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
-  #define ETH_DMAOMR_TTC_256Bytes      0x0000C000U  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
-  #define ETH_DMAOMR_TTC_40Bytes       0x00010000U  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
-  #define ETH_DMAOMR_TTC_32Bytes       0x00014000U  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
-  #define ETH_DMAOMR_TTC_24Bytes       0x00018000U  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
-  #define ETH_DMAOMR_TTC_16Bytes       0x0001C000U  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
-#define ETH_DMAOMR_ST        0x00002000U  /* Start/stop transmission command */
-#define ETH_DMAOMR_FEF       0x00000080U  /* Forward error frames */
-#define ETH_DMAOMR_FUGF      0x00000040U  /* Forward undersized good frames */
-#define ETH_DMAOMR_RTC       0x00000018U  /* receive threshold control */
-  #define ETH_DMAOMR_RTC_64Bytes       0x00000000U  /* threshold level of the MTL Receive FIFO is 64 Bytes */
-  #define ETH_DMAOMR_RTC_32Bytes       0x00000008U  /* threshold level of the MTL Receive FIFO is 32 Bytes */
-  #define ETH_DMAOMR_RTC_96Bytes       0x00000010U  /* threshold level of the MTL Receive FIFO is 96 Bytes */
-  #define ETH_DMAOMR_RTC_128Bytes      0x00000018U  /* threshold level of the MTL Receive FIFO is 128 Bytes */
-#define ETH_DMAOMR_OSF       0x00000004U  /* operate on second frame */
-#define ETH_DMAOMR_SR        0x00000002U  /* Start/stop receive */
-
-/* Bit definition for Ethernet DMA Interrupt Enable Register */
-#define ETH_DMAIER_NISE      0x00010000U  /* Normal interrupt summary enable */
-#define ETH_DMAIER_AISE      0x00008000U  /* Abnormal interrupt summary enable */
-#define ETH_DMAIER_ERIE      0x00004000U  /* Early receive interrupt enable */
-#define ETH_DMAIER_FBEIE     0x00002000U  /* Fatal bus error interrupt enable */
-#define ETH_DMAIER_ETIE      0x00000400U  /* Early transmit interrupt enable */
-#define ETH_DMAIER_RWTIE     0x00000200U  /* Receive watchdog timeout interrupt enable */
-#define ETH_DMAIER_RPSIE     0x00000100U  /* Receive process stopped interrupt enable */
-#define ETH_DMAIER_RBUIE     0x00000080U  /* Receive buffer unavailable interrupt enable */
-#define ETH_DMAIER_RIE       0x00000040U  /* Receive interrupt enable */
-#define ETH_DMAIER_TUIE      0x00000020U  /* Transmit Underflow interrupt enable */
-#define ETH_DMAIER_ROIE      0x00000010U  /* Receive Overflow interrupt enable */
-#define ETH_DMAIER_TJTIE     0x00000008U  /* Transmit jabber timeout interrupt enable */
-#define ETH_DMAIER_TBUIE     0x00000004U  /* Transmit buffer unavailable interrupt enable */
-#define ETH_DMAIER_TPSIE     0x00000002U  /* Transmit process stopped interrupt enable */
-#define ETH_DMAIER_TIE       0x00000001U  /* Transmit interrupt enable */
-
-/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
-#define ETH_DMAMFBOCR_OFOC   0x10000000U  /* Overflow bit for FIFO overflow counter */
-#define ETH_DMAMFBOCR_MFA    0x0FFE0000U  /* Number of frames missed by the application */
-#define ETH_DMAMFBOCR_OMFC   0x00010000U  /* Overflow bit for missed frame counter */
-#define ETH_DMAMFBOCR_MFC    0x0000FFFFU  /* Number of frames missed by the controller */
-
-/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
-#define ETH_DMACHTDR_HTDAP   0xFFFFFFFFU  /* Host transmit descriptor address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
-#define ETH_DMACHRDR_HRDAP   0xFFFFFFFFU  /* Host receive descriptor address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
-#define ETH_DMACHTBAR_HTBAP  0xFFFFFFFFU  /* Host transmit buffer address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
-#define ETH_DMACHRBAR_HRBAP  0xFFFFFFFFU  /* Host receive buffer address pointer */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                       USB_OTG                              */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for USB_OTG_GOTGCTL register  ********************/
-#define USB_OTG_GOTGCTL_SRQSCS                  0x00000001U         /*!< Session request success */
-#define USB_OTG_GOTGCTL_SRQ                     0x00000002U         /*!< Session request */
-#define USB_OTG_GOTGCTL_VBVALOEN                0x00000004U         /*!< VBUS valid override enable */
-#define USB_OTG_GOTGCTL_VBVALOVAL               0x00000008U         /*!< VBUS valid override value */
-#define USB_OTG_GOTGCTL_AVALOEN                 0x00000010U         /*!< A-peripheral session valid override enable */
-#define USB_OTG_GOTGCTL_AVALOVAL                0x00000020U         /*!< A-peripheral session valid override value */
-#define USB_OTG_GOTGCTL_BVALOEN                 0x00000040U         /*!< B-peripheral session valid override enable */
-#define USB_OTG_GOTGCTL_BVALOVAL                0x00000080U         /*!< B-peripheral session valid override value  */
-#define USB_OTG_GOTGCTL_HNGSCS                  0x00000100U         /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_HNPRQ                   0x00000200U         /*!< HNP request */
-#define USB_OTG_GOTGCTL_HSHNPEN                 0x00000400U         /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_DHNPEN                  0x00000800U         /*!< Device HNP enabled */
-#define USB_OTG_GOTGCTL_EHEN                    0x00001000U         /*!< Embedded host enable */
-#define USB_OTG_GOTGCTL_CIDSTS                  0x00010000U         /*!< Connector ID status */
-#define USB_OTG_GOTGCTL_DBCT                    0x00020000U         /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD                   0x00040000U         /*!< A-session valid  */
-#define USB_OTG_GOTGCTL_BSESVLD                 0x00080000U         /*!< B-session valid */
-#define USB_OTG_GOTGCTL_OTGVER                  0x00100000U         /*!< OTG version  */
-
-/********************  Bit definition for USB_OTG_HCFG register  ********************/
-#define USB_OTG_HCFG_FSLSPCS                 0x00000003U            /*!< FS/LS PHY clock select  */
-#define USB_OTG_HCFG_FSLSPCS_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCFG_FSLSPCS_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCFG_FSLSS                   0x00000004U            /*!< FS- and LS-only support */
-
-/********************  Bit definition for USB_OTG_DCFG register  ********************/
-#define USB_OTG_DCFG_DSPD                    0x00000003U            /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                  0x00000001U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DSPD_1                  0x00000002U            /*!<Bit 1 */
-#define USB_OTG_DCFG_NZLSOHSK                0x00000004U            /*!< Nonzero-length status OUT handshake */
-
-#define USB_OTG_DCFG_DAD                     0x000007F0U            /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                   0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DAD_1                   0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCFG_DAD_2                   0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCFG_DAD_3                   0x00000080U            /*!<Bit 3 */
-#define USB_OTG_DCFG_DAD_4                   0x00000100U            /*!<Bit 4 */
-#define USB_OTG_DCFG_DAD_5                   0x00000200U            /*!<Bit 5 */
-#define USB_OTG_DCFG_DAD_6                   0x00000400U            /*!<Bit 6 */
-
-#define USB_OTG_DCFG_PFIVL                   0x00001800U            /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PFIVL_1                 0x00001000U            /*!<Bit 1 */
-
-#define USB_OTG_DCFG_PERSCHIVL               0x03000000U            /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0             0x01000000U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PERSCHIVL_1             0x02000000U            /*!<Bit 1 */
-
-/********************  Bit definition for USB_OTG_PCGCR register  ********************/
-#define USB_OTG_PCGCR_STPPCLK                 0x00000001U            /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK                0x00000002U            /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP                 0x00000010U            /*!< PHY suspended */
-
-/********************  Bit definition for USB_OTG_GOTGINT register  ********************/
-#define USB_OTG_GOTGINT_SEDET                   0x00000004U            /*!< Session end detected                   */
-#define USB_OTG_GOTGINT_SRSSCHG                 0x00000100U            /*!< Session request success status change  */
-#define USB_OTG_GOTGINT_HNSSCHG                 0x00000200U            /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET                  0x00020000U            /*!< Host negotiation detected              */
-#define USB_OTG_GOTGINT_ADTOCHG                 0x00040000U            /*!< A-device timeout change                */
-#define USB_OTG_GOTGINT_DBCDNE                  0x00080000U            /*!< Debounce done                          */
-#define USB_OTG_GOTGINT_IDCHNG                  0x00100000U            /*!< Change in ID pin input value           */
-
-/********************  Bit definition for USB_OTG_DCTL register  ********************/
-#define USB_OTG_DCTL_RWUSIG                  0x00000001U            /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS                    0x00000002U            /*!< Soft disconnect         */
-#define USB_OTG_DCTL_GINSTS                  0x00000004U            /*!< Global IN NAK status    */
-#define USB_OTG_DCTL_GONSTS                  0x00000008U            /*!< Global OUT NAK status   */
-
-#define USB_OTG_DCTL_TCTL                    0x00000070U            /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                  0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCTL_TCTL_1                  0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCTL_TCTL_2                  0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCTL_SGINAK                  0x00000080U            /*!< Set global IN NAK         */
-#define USB_OTG_DCTL_CGINAK                  0x00000100U            /*!< Clear global IN NAK       */
-#define USB_OTG_DCTL_SGONAK                  0x00000200U            /*!< Set global OUT NAK        */
-#define USB_OTG_DCTL_CGONAK                  0x00000400U            /*!< Clear global OUT NAK      */
-#define USB_OTG_DCTL_POPRGDNE                0x00000800U            /*!< Power-on programming done */
-
-/********************  Bit definition for USB_OTG_HFIR register  ********************/
-#define USB_OTG_HFIR_FRIVL                   0x0000FFFFU            /*!< Frame interval */
-
-/********************  Bit definition for USB_OTG_HFNUM register  ********************/
-#define USB_OTG_HFNUM_FRNUM                   0x0000FFFFU            /*!< Frame number         */
-#define USB_OTG_HFNUM_FTREM                   0xFFFF0000U            /*!< Frame time remaining */
-
-/********************  Bit definition for USB_OTG_DSTS register  ********************/
-#define USB_OTG_DSTS_SUSPSTS                 0x00000001U            /*!< Suspend status   */
-
-#define USB_OTG_DSTS_ENUMSPD                 0x00000006U            /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_DSTS_ENUMSPD_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_DSTS_EERR                    0x00000008U            /*!< Erratic error     */
-#define USB_OTG_DSTS_FNSOF                   0x003FFF00U            /*!< Frame number of the received SOF */
-
-/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
-#define USB_OTG_GAHBCFG_GINT                    0x00000001U            /*!< Global interrupt mask */
-#define USB_OTG_GAHBCFG_HBSTLEN                 0x0000001EU            /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_GAHBCFG_HBSTLEN_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_GAHBCFG_HBSTLEN_2               0x00000008U            /*!<Bit 2 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3               0x00000010U            /*!<Bit 3 */
-#define USB_OTG_GAHBCFG_DMAEN                   0x00000020U            /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL                 0x00000080U            /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL                0x00000100U            /*!< Periodic TxFIFO empty level */
-
-/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
-#define USB_OTG_GUSBCFG_TOCAL                   0x00000007U            /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TOCAL_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TOCAL_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_PHYSEL                  0x00000040U            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP                  0x00000100U            /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP                  0x00000200U            /*!< HNP-capable */
-#define USB_OTG_GUSBCFG_TRDT                    0x00003C00U            /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                  0x00000400U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TRDT_1                  0x00000800U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TRDT_2                  0x00001000U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_TRDT_3                  0x00002000U            /*!<Bit 3 */
-#define USB_OTG_GUSBCFG_PHYLPCS                 0x00008000U            /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS                0x00020000U            /*!< ULPI FS/LS select               */
-#define USB_OTG_GUSBCFG_ULPIAR                  0x00040000U            /*!< ULPI Auto-resume                */
-#define USB_OTG_GUSBCFG_ULPICSM                 0x00080000U            /*!< ULPI Clock SuspendM             */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD              0x00100000U            /*!< ULPI External VBUS Drive        */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI              0x00200000U            /*!< ULPI external VBUS indicator    */
-#define USB_OTG_GUSBCFG_TSDPS                   0x00400000U            /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI                    0x00800000U            /*!< Indicator complement            */
-#define USB_OTG_GUSBCFG_PTCI                    0x01000000U            /*!< Indicator pass through          */
-#define USB_OTG_GUSBCFG_ULPIIPD                 0x02000000U            /*!< ULPI interface protect disable  */
-#define USB_OTG_GUSBCFG_FHMOD                   0x20000000U            /*!< Forced host mode                */
-#define USB_OTG_GUSBCFG_FDMOD                   0x40000000U            /*!< Forced peripheral mode          */
-#define USB_OTG_GUSBCFG_CTXPKT                  0x80000000U            /*!< Corrupt Tx packet               */
-
-/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
-#define USB_OTG_GRSTCTL_CSRST                   0x00000001U            /*!< Core soft reset          */
-#define USB_OTG_GRSTCTL_HSRST                   0x00000002U            /*!< HCLK soft reset          */
-#define USB_OTG_GRSTCTL_FCRST                   0x00000004U            /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH                 0x00000010U            /*!< RxFIFO flush             */
-#define USB_OTG_GRSTCTL_TXFFLSH                 0x00000020U            /*!< TxFIFO flush             */
-#define USB_OTG_GRSTCTL_TXFNUM                  0x000007C0U            /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                0x00000040U            /*!<Bit 0 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                0x00000080U            /*!<Bit 1 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                0x00000100U            /*!<Bit 2 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                0x00000200U            /*!<Bit 3 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                0x00000400U            /*!<Bit 4 */
-#define USB_OTG_GRSTCTL_DMAREQ                  0x40000000U            /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL                  0x80000000U            /*!< AHB master idle */
-
-/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
-#define USB_OTG_DIEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask                 */
-#define USB_OTG_DIEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask                  */
-#define USB_OTG_DIEPMSK_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask          */
-#define USB_OTG_DIEPMSK_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask           */
-#define USB_OTG_DIEPMSK_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask                    */
-#define USB_OTG_DIEPMSK_TXFURM                  0x00000100U            /*!< FIFO underrun mask                                */
-#define USB_OTG_DIEPMSK_BIM                     0x00000200U            /*!< BNA interrupt mask                                */
-
-/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
-#define USB_OTG_HPTXSTS_PTXFSAVL                0x0000FFFFU            /*!< Periodic transmit data FIFO space available     */
-#define USB_OTG_HPTXSTS_PTXQSAV                 0x00FF0000U            /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0               0x00010000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1               0x00020000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2               0x00040000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3               0x00080000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4               0x00100000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5               0x00200000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6               0x00400000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7               0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_HPTXSTS_PTXQTOP                 0xFF000000U            /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0               0x01000000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1               0x02000000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2               0x04000000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3               0x08000000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4               0x10000000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5               0x20000000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6               0x40000000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7               0x80000000U            /*!<Bit 7 */
-
-/********************  Bit definition for USB_OTG_HAINT register  ********************/
-#define USB_OTG_HAINT_HAINT                     0x0000FFFFU            /*!< Channel interrupts */
-
-/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
-#define USB_OTG_DOEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask               */
-#define USB_OTG_DOEPMSK_STUPM                   0x00000008U            /*!< SETUP phase done mask                          */
-#define USB_OTG_DOEPMSK_OTEPDM                  0x00000010U            /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_OTEPSPRM                0x00000020U            /*!< Status Phase Received mask                     */
-#define USB_OTG_DOEPMSK_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received mask       */
-#define USB_OTG_DOEPMSK_OPEM                    0x00000100U            /*!< OUT packet error mask                          */
-#define USB_OTG_DOEPMSK_BOIM                    0x00000200U            /*!< BNA interrupt mask                             */
-
-/********************  Bit definition for USB_OTG_GINTSTS register  ********************/
-#define USB_OTG_GINTSTS_CMOD                    0x00000001U            /*!< Current mode of operation                      */
-#define USB_OTG_GINTSTS_MMIS                    0x00000002U            /*!< Mode mismatch interrupt                        */
-#define USB_OTG_GINTSTS_OTGINT                  0x00000004U            /*!< OTG interrupt                                  */
-#define USB_OTG_GINTSTS_SOF                     0x00000008U            /*!< Start of frame                                 */
-#define USB_OTG_GINTSTS_RXFLVL                  0x00000010U            /*!< RxFIFO nonempty                                */
-#define USB_OTG_GINTSTS_NPTXFE                  0x00000020U            /*!< Nonperiodic TxFIFO empty                       */
-#define USB_OTG_GINTSTS_GINAKEFF                0x00000040U            /*!< Global IN nonperiodic NAK effective            */
-#define USB_OTG_GINTSTS_BOUTNAKEFF              0x00000080U            /*!< Global OUT NAK effective                       */
-#define USB_OTG_GINTSTS_ESUSP                   0x00000400U            /*!< Early suspend                                  */
-#define USB_OTG_GINTSTS_USBSUSP                 0x00000800U            /*!< USB suspend                                    */
-#define USB_OTG_GINTSTS_USBRST                  0x00001000U            /*!< USB reset                                      */
-#define USB_OTG_GINTSTS_ENUMDNE                 0x00002000U            /*!< Enumeration done                               */
-#define USB_OTG_GINTSTS_ISOODRP                 0x00004000U            /*!< Isochronous OUT packet dropped interrupt       */
-#define USB_OTG_GINTSTS_EOPF                    0x00008000U            /*!< End of periodic frame interrupt                */
-#define USB_OTG_GINTSTS_IEPINT                  0x00040000U            /*!< IN endpoint interrupt                          */
-#define USB_OTG_GINTSTS_OEPINT                  0x00080000U            /*!< OUT endpoint interrupt                         */
-#define USB_OTG_GINTSTS_IISOIXFR                0x00100000U            /*!< Incomplete isochronous IN transfer             */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       0x00200000U            /*!< Incomplete periodic transfer                   */
-#define USB_OTG_GINTSTS_DATAFSUSP               0x00400000U            /*!< Data fetch suspended                           */
-#define USB_OTG_GINTSTS_RSTDET                  0x00800000U            /*!< Reset detected interrupt                       */
-#define USB_OTG_GINTSTS_HPRTINT                 0x01000000U            /*!< Host port interrupt                            */
-#define USB_OTG_GINTSTS_HCINT                   0x02000000U            /*!< Host channels interrupt                        */
-#define USB_OTG_GINTSTS_PTXFE                   0x04000000U            /*!< Periodic TxFIFO empty                          */
-#define USB_OTG_GINTSTS_LPMINT                  0x08000000U            /*!< LPM interrupt                                  */
-#define USB_OTG_GINTSTS_CIDSCHG                 0x10000000U            /*!< Connector ID status change                     */
-#define USB_OTG_GINTSTS_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt                  */
-#define USB_OTG_GINTSTS_SRQINT                  0x40000000U            /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT                  0x80000000U            /*!< Resume/remote wakeup detected interrupt        */
-
-/********************  Bit definition for USB_OTG_GINTMSK register  ********************/
-#define USB_OTG_GINTMSK_MMISM                   0x00000002U            /*!< Mode mismatch interrupt mask                        */
-#define USB_OTG_GINTMSK_OTGINT                  0x00000004U            /*!< OTG interrupt mask                                  */
-#define USB_OTG_GINTMSK_SOFM                    0x00000008U            /*!< Start of frame mask                                 */
-#define USB_OTG_GINTMSK_RXFLVLM                 0x00000010U            /*!< Receive FIFO nonempty mask                          */
-#define USB_OTG_GINTMSK_NPTXFEM                 0x00000020U            /*!< Nonperiodic TxFIFO empty mask                       */
-#define USB_OTG_GINTMSK_GINAKEFFM               0x00000040U            /*!< Global nonperiodic IN NAK effective mask            */
-#define USB_OTG_GINTMSK_GONAKEFFM               0x00000080U            /*!< Global OUT NAK effective mask                       */
-#define USB_OTG_GINTMSK_ESUSPM                  0x00000400U            /*!< Early suspend mask                                  */
-#define USB_OTG_GINTMSK_USBSUSPM                0x00000800U            /*!< USB suspend mask                                    */
-#define USB_OTG_GINTMSK_USBRST                  0x00001000U            /*!< USB reset mask                                      */
-#define USB_OTG_GINTMSK_ENUMDNEM                0x00002000U            /*!< Enumeration done mask                               */
-#define USB_OTG_GINTMSK_ISOODRPM                0x00004000U            /*!< Isochronous OUT packet dropped interrupt mask       */
-#define USB_OTG_GINTMSK_EOPFM                   0x00008000U            /*!< End of periodic frame interrupt mask                */
-#define USB_OTG_GINTMSK_EPMISM                  0x00020000U            /*!< Endpoint mismatch interrupt mask                    */
-#define USB_OTG_GINTMSK_IEPINT                  0x00040000U            /*!< IN endpoints interrupt mask                         */
-#define USB_OTG_GINTMSK_OEPINT                  0x00080000U            /*!< OUT endpoints interrupt mask                        */
-#define USB_OTG_GINTMSK_IISOIXFRM               0x00100000U            /*!< Incomplete isochronous IN transfer mask             */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         0x00200000U            /*!< Incomplete periodic transfer mask                   */
-#define USB_OTG_GINTMSK_FSUSPM                  0x00400000U            /*!< Data fetch suspended mask                           */
-#define USB_OTG_GINTMSK_RSTDEM                  0x00800000U            /*!< Reset detected interrupt mask                       */
-#define USB_OTG_GINTMSK_PRTIM                   0x01000000U            /*!< Host port interrupt mask                            */
-#define USB_OTG_GINTMSK_HCIM                    0x02000000U            /*!< Host channels interrupt mask                        */
-#define USB_OTG_GINTMSK_PTXFEM                  0x04000000U            /*!< Periodic TxFIFO empty mask                          */
-#define USB_OTG_GINTMSK_LPMINTM                 0x08000000U            /*!< LPM interrupt Mask                                  */
-#define USB_OTG_GINTMSK_CIDSCHGM                0x10000000U            /*!< Connector ID status change mask                     */
-#define USB_OTG_GINTMSK_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt mask                  */
-#define USB_OTG_GINTMSK_SRQIM                   0x40000000U            /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM                    0x80000000U            /*!< Resume/remote wakeup detected interrupt mask        */
-
-/********************  Bit definition for USB_OTG_DAINT register  ********************/
-#define USB_OTG_DAINT_IEPINT                  0x0000FFFFU            /*!< IN endpoint interrupt bits  */
-#define USB_OTG_DAINT_OEPINT                  0xFFFF0000U            /*!< OUT endpoint interrupt bits */
-
-/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
-#define USB_OTG_HAINTMSK_HAINTM                  0x0000FFFFU            /*!< Channel interrupt mask */
-
-/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
-#define USB_OTG_GRXSTSP_EPNUM                    0x0000000FU            /*!< IN EP interrupt mask bits  */
-#define USB_OTG_GRXSTSP_BCNT                     0x00007FF0U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID                     0x00018000U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS                   0x001E0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
-#define USB_OTG_DAINTMSK_IEPM                    0x0000FFFFU            /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM                    0xFFFF0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for OTG register  ********************/
-
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition for OTG register  ********************/
-
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
-#define USB_OTG_GRXFSIZ_RXFD            0x0000FFFFU            /*!< RxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
-#define USB_OTG_DVBUSDIS_VBUSDT         0x0000FFFFU            /*!< Device VBUS discharge time */
-
-/********************  Bit definition for OTG register  ********************/
-#define USB_OTG_NPTXFSA                 0x0000FFFFU            /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD                  0xFFFF0000U            /*!< Nonperiodic TxFIFO depth               */
-#define USB_OTG_TX0FSA                  0x0000FFFFU            /*!< Endpoint 0 transmit RAM start address  */
-#define USB_OTG_TX0FD                   0xFFFF0000U            /*!< Endpoint 0 TxFIFO depth                */
-
-/********************  Bit definition for USB_OTG_DVBUSPULSE register  ********************/
-#define USB_OTG_DVBUSPULSE_DVBUSP                0x00000FFFU            /*!< Device VBUS pulsing time */
-
-/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
-#define USB_OTG_GNPTXSTS_NPTXFSAV                0x0000FFFFU            /*!< Nonperiodic TxFIFO space available */
-
-#define USB_OTG_GNPTXSTS_NPTQXSAV                0x00FF0000U            /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0              0x00010000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1              0x00020000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2              0x00040000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3              0x00080000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4              0x00100000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5              0x00200000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6              0x00400000U            /*!<Bit 6 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7              0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_GNPTXSTS_NPTXQTOP                0x7F000000U            /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0              0x01000000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1              0x02000000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2              0x04000000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3              0x08000000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4              0x10000000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5              0x20000000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6              0x40000000U            /*!<Bit 6 */
-
-/********************  Bit definition for USB_OTG_DTHRCTL register  ********************/
-#define USB_OTG_DTHRCTL_NONISOTHREN             0x00000001U            /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN                0x00000002U            /*!< ISO IN endpoint threshold enable */
-
-#define USB_OTG_DTHRCTL_TXTHRLEN                0x000007FCU            /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0              0x00000004U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1              0x00000008U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2              0x00000010U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3              0x00000020U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4              0x00000040U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5              0x00000080U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6              0x00000100U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7              0x00000200U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8              0x00000400U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_RXTHREN                 0x00010000U            /*!< Receive threshold enable */
-
-#define USB_OTG_DTHRCTL_RXTHRLEN                0x03FE0000U            /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0              0x00020000U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1              0x00040000U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2              0x00080000U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3              0x00100000U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4              0x00200000U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5              0x00400000U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6              0x00800000U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7              0x01000000U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8              0x02000000U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_ARPEN                   0x08000000U            /*!< Arbiter parking enable */
-
-/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM            0x0000FFFFU         /*!< IN EP Tx FIFO empty interrupt mask bits */
-
-/********************  Bit definition for USB_OTG_DEACHINT register  ********************/
-#define USB_OTG_DEACHINT_IEP1INT                0x00000002U           /*!< IN endpoint 1interrupt bit   */
-#define USB_OTG_DEACHINT_OEP1INT                0x00020000U           /*!< OUT endpoint 1 interrupt bit */
-
-/********************  Bit definition for USB_OTG_GCCFG register  ********************/
-#define USB_OTG_GCCFG_PWRDWN                 0x00010000U              /*!< Power down */
-#define USB_OTG_GCCFG_VBDEN                  0x00200000U              /*!< USB VBUS Detection Enable */
-
-/********************  Bit definition for USB_OTG_GPWRDN) register  ********************/
-#define USB_OTG_GPWRDN_ADPMEN                 0x00000001U             /*!< ADP module enable */
-#define USB_OTG_GPWRDN_ADPIF                  0x00800000U             /*!< ADP Interrupt flag */
-
-/********************  Bit definition for USB_OTG_DEACHINTMSK register  ********************/
-#define USB_OTG_DEACHINTMSK_IEP1INTM          0x00000002U            /*!< IN Endpoint 1 interrupt mask bit  */
-#define USB_OTG_DEACHINTMSK_OEP1INTM          0x00020000U            /*!< OUT Endpoint 1 interrupt mask bit */
-
-/********************  Bit definition for USB_OTG_CID register  ********************/
-#define USB_OTG_CID_PRODUCT_ID               0xFFFFFFFFU            /*!< Product ID field */
-
-/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/
-#define  USB_OTG_GLPMCFG_LPMEN               0x00000001U            /*!< LPM support enable                                     */
-#define  USB_OTG_GLPMCFG_LPMACK              0x00000002U            /*!< LPM Token acknowledge enable                           */
-#define  USB_OTG_GLPMCFG_BESL                0x0000003CU            /*!< BESL value received with last ACKed LPM Token          */
-#define  USB_OTG_GLPMCFG_REMWAKE             0x00000040U            /*!< bRemoteWake value received with last ACKed LPM Token   */
-#define  USB_OTG_GLPMCFG_L1SSEN              0x00000080U            /*!< L1 shallow sleep enable                                */
-#define  USB_OTG_GLPMCFG_BESLTHRS            0x00000F00U            /*!< BESL threshold                                         */
-#define  USB_OTG_GLPMCFG_L1DSEN              0x00001000U            /*!< L1 deep sleep enable                                   */
-#define  USB_OTG_GLPMCFG_LPMRSP              0x00006000U            /*!< LPM response                                           */
-#define  USB_OTG_GLPMCFG_SLPSTS              0x00008000U            /*!< Port sleep status                                      */
-#define  USB_OTG_GLPMCFG_L1RSMOK             0x00010000U            /*!< Sleep State Resume OK                                  */
-#define  USB_OTG_GLPMCFG_LPMCHIDX            0x001E0000U            /*!< LPM Channel Index                                      */
-#define  USB_OTG_GLPMCFG_LPMRCNT             0x00E00000U            /*!< LPM retry count                                        */
-#define  USB_OTG_GLPMCFG_SNDLPM              0x01000000U            /*!< Send LPM transaction                                   */
-#define  USB_OTG_GLPMCFG_LPMRCNTSTS          0x0E000000U            /*!< LPM retry count status                                 */
-#define  USB_OTG_GLPMCFG_ENBESL              0x10000000U            /*!< Enable best effort service latency                     */
-
-/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
-#define USB_OTG_DIEPEACHMSK1_XFRCM           0x00000001U            /*!< Transfer completed interrupt mask                 */
-#define USB_OTG_DIEPEACHMSK1_EPDM            0x00000002U            /*!< Endpoint disabled interrupt mask                  */
-#define USB_OTG_DIEPEACHMSK1_TOM             0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK       0x00000010U            /*!< IN token received when TxFIFO empty mask          */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM         0x00000020U            /*!< IN token received with EP mismatch mask           */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM         0x00000040U            /*!< IN endpoint NAK effective mask                    */
-#define USB_OTG_DIEPEACHMSK1_TXFURM          0x00000100U            /*!< FIFO underrun mask                                */
-#define USB_OTG_DIEPEACHMSK1_BIM             0x00000200U            /*!< BNA interrupt mask                                */
-#define USB_OTG_DIEPEACHMSK1_NAKM            0x00002000U            /*!< NAK interrupt mask                                */
-
-/********************  Bit definition for USB_OTG_HPRT register  ********************/
-#define USB_OTG_HPRT_PCSTS                   0x00000001U            /*!< Port connect status        */
-#define USB_OTG_HPRT_PCDET                   0x00000002U            /*!< Port connect detected      */
-#define USB_OTG_HPRT_PENA                    0x00000004U            /*!< Port enable                */
-#define USB_OTG_HPRT_PENCHNG                 0x00000008U            /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA                    0x00000010U            /*!< Port overcurrent active    */
-#define USB_OTG_HPRT_POCCHNG                 0x00000020U            /*!< Port overcurrent change    */
-#define USB_OTG_HPRT_PRES                    0x00000040U            /*!< Port resume                */
-#define USB_OTG_HPRT_PSUSP                   0x00000080U            /*!< Port suspend               */
-#define USB_OTG_HPRT_PRST                    0x00000100U            /*!< Port reset                 */
-
-#define USB_OTG_HPRT_PLSTS                   0x00000C00U            /*!< Port line status           */
-#define USB_OTG_HPRT_PLSTS_0                 0x00000400U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PLSTS_1                 0x00000800U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PPWR                    0x00001000U            /*!< Port power                 */
-
-#define USB_OTG_HPRT_PTCTL                   0x0001E000U            /*!< Port test control          */
-#define USB_OTG_HPRT_PTCTL_0                 0x00002000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PTCTL_1                 0x00004000U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PTCTL_2                 0x00008000U            /*!<Bit 2 */
-#define USB_OTG_HPRT_PTCTL_3                 0x00010000U            /*!<Bit 3 */
-
-#define USB_OTG_HPRT_PSPD                    0x00060000U            /*!< Port speed                 */
-#define USB_OTG_HPRT_PSPD_0                  0x00020000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PSPD_1                  0x00040000U            /*!<Bit 1 */
-
-/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
-#define USB_OTG_DOEPEACHMSK1_XFRCM               0x00000001U            /*!< Transfer completed interrupt mask         */
-#define USB_OTG_DOEPEACHMSK1_EPDM                0x00000002U            /*!< Endpoint disabled interrupt mask          */
-#define USB_OTG_DOEPEACHMSK1_TOM                 0x00000008U            /*!< Timeout condition mask                    */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           0x00000010U            /*!< IN token received when TxFIFO empty mask  */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM             0x00000020U            /*!< IN token received with EP mismatch mask   */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM             0x00000040U            /*!< IN endpoint NAK effective mask            */
-#define USB_OTG_DOEPEACHMSK1_TXFURM              0x00000100U            /*!< OUT packet error mask                     */
-#define USB_OTG_DOEPEACHMSK1_BIM                 0x00000200U            /*!< BNA interrupt mask                        */
-#define USB_OTG_DOEPEACHMSK1_BERRM               0x00001000U            /*!< Bubble error interrupt mask               */
-#define USB_OTG_DOEPEACHMSK1_NAKM                0x00002000U            /*!< NAK interrupt mask                        */
-#define USB_OTG_DOEPEACHMSK1_NYETM               0x00004000U            /*!< NYET interrupt mask                       */
-
-/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
-#define USB_OTG_HPTXFSIZ_PTXSA                   0x0000FFFFU            /*!< Host periodic TxFIFO start address            */
-#define USB_OTG_HPTXFSIZ_PTXFD                   0xFFFF0000U            /*!< Host periodic TxFIFO depth                    */
-
-/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
-#define USB_OTG_DIEPCTL_MPSIZ                   0x000007FFU            /*!< Maximum packet size              */
-#define USB_OTG_DIEPCTL_USBAEP                  0x00008000U            /*!< USB active endpoint              */
-#define USB_OTG_DIEPCTL_EONUM_DPID              0x00010000U            /*!< Even/odd frame                   */
-#define USB_OTG_DIEPCTL_NAKSTS                  0x00020000U            /*!< NAK status                       */
-
-#define USB_OTG_DIEPCTL_EPTYP                   0x000C0000U            /*!< Endpoint type                    */
-#define USB_OTG_DIEPCTL_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_STALL                   0x00200000U            /*!< STALL handshake                  */
-
-#define USB_OTG_DIEPCTL_TXFNUM                  0x03C00000U            /*!< TxFIFO number                    */
-#define USB_OTG_DIEPCTL_TXFNUM_0                0x00400000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                0x00800000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                0x01000000U            /*!<Bit 2 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                0x02000000U            /*!<Bit 3 */
-#define USB_OTG_DIEPCTL_CNAK                    0x04000000U            /*!< Clear NAK                        */
-#define USB_OTG_DIEPCTL_SNAK                    0x08000000U            /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          0x10000000U            /*!< Set DATA0 PID                    */
-#define USB_OTG_DIEPCTL_SODDFRM                 0x20000000U            /*!< Set odd frame                    */
-#define USB_OTG_DIEPCTL_EPDIS                   0x40000000U            /*!< Endpoint disable                 */
-#define USB_OTG_DIEPCTL_EPENA                   0x80000000U            /*!< Endpoint enable                  */
-
-/********************  Bit definition for USB_OTG_HCCHAR register  ********************/
-#define USB_OTG_HCCHAR_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
-
-#define USB_OTG_HCCHAR_EPNUM                   0x00007800U            /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPNUM_1                 0x00001000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_EPNUM_2                 0x00002000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_EPNUM_3                 0x00004000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_EPDIR                   0x00008000U            /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV                   0x00020000U            /*!< Low-speed device */
-
-#define USB_OTG_HCCHAR_EPTYP                   0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_MC                      0x00300000U            /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                    0x00100000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_MC_1                    0x00200000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_DAD                     0x1FC00000U            /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                   0x00400000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_DAD_1                   0x00800000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_DAD_2                   0x01000000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_DAD_3                   0x02000000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_DAD_4                   0x04000000U            /*!<Bit 4 */
-#define USB_OTG_HCCHAR_DAD_5                   0x08000000U            /*!<Bit 5 */
-#define USB_OTG_HCCHAR_DAD_6                   0x10000000U            /*!<Bit 6 */
-#define USB_OTG_HCCHAR_ODDFRM                  0x20000000U            /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS                   0x40000000U            /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA                   0x80000000U            /*!< Channel enable */
-
-/********************  Bit definition for USB_OTG_HCSPLT register  ********************/
-
-#define USB_OTG_HCSPLT_PRTADDR                 0x0000007FU            /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_PRTADDR_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_PRTADDR_2               0x00000004U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_PRTADDR_3               0x00000008U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_PRTADDR_4               0x00000010U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_PRTADDR_5               0x00000020U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_PRTADDR_6               0x00000040U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_HUBADDR                 0x00003F80U            /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0               0x00000080U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_HUBADDR_1               0x00000100U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_HUBADDR_2               0x00000200U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_HUBADDR_3               0x00000400U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_HUBADDR_4               0x00000800U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_HUBADDR_5               0x00001000U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_HUBADDR_6               0x00002000U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_XACTPOS                 0x0000C000U            /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0               0x00004000U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_XACTPOS_1               0x00008000U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_COMPLSPLT               0x00010000U            /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN                 0x80000000U            /*!< Split enable */
-
-/********************  Bit definition for USB_OTG_HCINT register  ********************/
-#define USB_OTG_HCINT_XFRC                    0x00000001U            /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH                     0x00000002U            /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINT_STALL                   0x00000008U            /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK                     0x00000010U            /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK                     0x00000020U            /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET                    0x00000040U            /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR                   0x00000080U            /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR                   0x00000100U            /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR                   0x00000200U            /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR                   0x00000400U            /*!< Data toggle error */
-
-/********************  Bit definition for USB_OTG_DIEPINT register  ********************/
-#define USB_OTG_DIEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_TOC                     0x00000008U            /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE                  0x00000010U            /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNE                  0x00000040U            /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE                    0x00000080U            /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN              0x00000100U            /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA                     0x00000200U            /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS               0x00000800U            /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR                    0x00001000U            /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK                     0x00002000U            /*!< NAK interrupt */
-
-/********************  Bit definition for USB_OTG_HCINTMSK register  ********************/
-#define USB_OTG_HCINTMSK_XFRCM                   0x00000001U            /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM                    0x00000002U            /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM                  0x00000008U            /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM                    0x00000010U            /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM                    0x00000020U            /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET                    0x00000040U            /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM                  0x00000080U            /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM                  0x00000100U            /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM                  0x00000200U            /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM                  0x00000400U            /*!< Data toggle error mask */
-
-/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
-
-#define USB_OTG_DIEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT                  0x60000000U            /*!< Packet count */
-/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
-#define USB_OTG_HCTSIZ_XFRSIZ                    0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT                    0x1FF80000U            /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING                    0x80000000U            /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID                      0x60000000U            /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                    0x20000000U            /*!<Bit 0 */
-#define USB_OTG_HCTSIZ_DPID_1                    0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
-#define USB_OTG_DIEPDMA_DMAADDR                  0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition for USB_OTG_HCDMA register  ********************/
-#define USB_OTG_HCDMA_DMAADDR                    0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
-#define USB_OTG_DTXFSTS_INEPTFSAV                0x0000FFFFU            /*!< IN endpoint TxFIFO space available */
-
-/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
-#define USB_OTG_DIEPTXF_INEPTXSA                 0x0000FFFFU            /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD                 0xFFFF0000U            /*!< IN endpoint TxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
-#define USB_OTG_DOEPCTL_MPSIZ                     0x000007FFU            /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP                    0x00008000U            /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS                    0x00020000U            /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            0x10000000U            /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM                   0x20000000U            /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP                     0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                   0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DOEPCTL_EPTYP_1                   0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_SNPM                      0x00100000U            /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL                     0x00200000U            /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK                      0x04000000U            /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK                      0x08000000U            /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS                     0x40000000U            /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA                     0x80000000U            /*!< Endpoint enable */
-
-/********************  Bit definition for USB_OTG_DOEPINT register  ********************/
-#define USB_OTG_DOEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_STUP                    0x00000008U            /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS                 0x00000010U            /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_OTEPSPR                 0x00000020U            /*!< Status Phase Received For Control Write */
-#define USB_OTG_DOEPINT_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_NYET                    0x00004000U            /*!< NYET interrupt */
-
-/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
-#define USB_OTG_DOEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-
-#define USB_OTG_DOEPTSIZ_STUPCNT                 0x60000000U            /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0               0x20000000U            /*!<Bit 0 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1               0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition for PCGCCTL register  ********************/
-#define USB_OTG_PCGCCTL_STOPCLK                 0x00000001U            /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK                 0x00000002U            /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP                 0x00000010U            /*!<Bit 1 */
-
-
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || \
-                                       ((__INSTANCE__) == ADC2) || \
-                                       ((__INSTANCE__) == ADC3))
-
-/******************************* CAN Instances ********************************/
-#define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) || \
-                                           ((__INSTANCE__) == CAN2))
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)
-
-/******************************* DAC Instances ********************************/
-#define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC)
-
-/******************************* DCMI Instances *******************************/
-#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
-
-
-/******************************* DMA2D Instances *******************************/
-#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
-
-/******************************** DMA Instances *******************************/
-#define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) || \
-                                              ((__INSTANCE__) == DMA1_Stream1) || \
-                                              ((__INSTANCE__) == DMA1_Stream2) || \
-                                              ((__INSTANCE__) == DMA1_Stream3) || \
-                                              ((__INSTANCE__) == DMA1_Stream4) || \
-                                              ((__INSTANCE__) == DMA1_Stream5) || \
-                                              ((__INSTANCE__) == DMA1_Stream6) || \
-                                              ((__INSTANCE__) == DMA1_Stream7) || \
-                                              ((__INSTANCE__) == DMA2_Stream0) || \
-                                              ((__INSTANCE__) == DMA2_Stream1) || \
-                                              ((__INSTANCE__) == DMA2_Stream2) || \
-                                              ((__INSTANCE__) == DMA2_Stream3) || \
-                                              ((__INSTANCE__) == DMA2_Stream4) || \
-                                              ((__INSTANCE__) == DMA2_Stream5) || \
-                                              ((__INSTANCE__) == DMA2_Stream6) || \
-                                              ((__INSTANCE__) == DMA2_Stream7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
-                                            ((__INSTANCE__) == GPIOB) || \
-                                            ((__INSTANCE__) == GPIOC) || \
-                                            ((__INSTANCE__) == GPIOD) || \
-                                            ((__INSTANCE__) == GPIOE) || \
-                                            ((__INSTANCE__) == GPIOF) || \
-                                            ((__INSTANCE__) == GPIOG) || \
-                                            ((__INSTANCE__) == GPIOH) || \
-                                            ((__INSTANCE__) == GPIOI) || \
-                                            ((__INSTANCE__) == GPIOJ) || \
-                                            ((__INSTANCE__) == GPIOK))
-
-#define IS_GPIO_AF_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == GPIOA) || \
-                                             ((__INSTANCE__) == GPIOB) || \
-                                             ((__INSTANCE__) == GPIOC) || \
-                                             ((__INSTANCE__) == GPIOD) || \
-                                             ((__INSTANCE__) == GPIOE) || \
-                                             ((__INSTANCE__) == GPIOF) || \
-                                             ((__INSTANCE__) == GPIOG) || \
-                                             ((__INSTANCE__) == GPIOH) || \
-                                             ((__INSTANCE__) == GPIOI) || \
-                                             ((__INSTANCE__) == GPIOJ) || \
-                                             ((__INSTANCE__) == GPIOK))
-
-/****************************** CEC Instances *********************************/
-#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
-
-/****************************** QSPI Instances *********************************/
-#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
-
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
-                                           ((__INSTANCE__) == I2C2) || \
-                                           ((__INSTANCE__) == I2C3) || \
-                                           ((__INSTANCE__) == I2C4))
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == SPI1) || \
-                                            ((__INSTANCE__) == SPI2) || \
-                                            ((__INSTANCE__) == SPI3))
-
-/******************************* LPTIM Instances ********************************/
-#define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
-
-/****************************** LTDC Instances ********************************/
-#define IS_LTDC_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == LTDC)
-
-
-
-
-/******************************* RNG Instances ********************************/
-#define IS_RNG_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == RNG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == RTC)
-
-/******************************* SAI Instances ********************************/
-#define IS_SAI_ALL_INSTANCE(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) || \
-                                         ((__PERIPH__) == SAI1_Block_B) || \
-                                         ((__PERIPH__) == SAI2_Block_A) || \
-                                         ((__PERIPH__) == SAI2_Block_B))
-/* Legacy define */
-#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
-
-/******************************** SDMMC Instances *******************************/
-#define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SDMMC1)
-
-/****************************** SPDIFRX Instances *********************************/
-#define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
-                                           ((__INSTANCE__) == SPI2) || \
-                                           ((__INSTANCE__) == SPI3) || \
-                                           ((__INSTANCE__) == SPI4) || \
-                                           ((__INSTANCE__) == SPI5) || \
-                                           ((__INSTANCE__) == SPI6))
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1)   || \
-                                   ((__INSTANCE__) == TIM2)   || \
-                                   ((__INSTANCE__) == TIM3)   || \
-                                   ((__INSTANCE__) == TIM4)   || \
-                                   ((__INSTANCE__) == TIM5)   || \
-                                   ((__INSTANCE__) == TIM6)   || \
-                                   ((__INSTANCE__) == TIM7)   || \
-                                   ((__INSTANCE__) == TIM8)   || \
-                                   ((__INSTANCE__) == TIM9)   || \
-                                   ((__INSTANCE__) == TIM10)  || \
-                                   ((__INSTANCE__) == TIM11)  || \
-                                   ((__INSTANCE__) == TIM12)  || \
-                                   ((__INSTANCE__) == TIM13)  || \
-                                   ((__INSTANCE__) == TIM14))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1)  || \
-                                         ((__INSTANCE__) == TIM2)  || \
-                                         ((__INSTANCE__) == TIM3)  || \
-                                         ((__INSTANCE__) == TIM4)  || \
-                                         ((__INSTANCE__) == TIM5)  || \
-                                         ((__INSTANCE__) == TIM8)  || \
-                                         ((__INSTANCE__) == TIM9)  || \
-                                         ((__INSTANCE__) == TIM10) || \
-                                         ((__INSTANCE__) == TIM11) || \
-                                         ((__INSTANCE__) == TIM12) || \
-                                         ((__INSTANCE__) == TIM13) || \
-                                         ((__INSTANCE__) == TIM14))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1)  || \
-                                         ((__INSTANCE__) == TIM2)  || \
-                                         ((__INSTANCE__) == TIM3)  || \
-                                         ((__INSTANCE__) == TIM4)  || \
-                                         ((__INSTANCE__) == TIM5)  || \
-                                         ((__INSTANCE__) == TIM8)  || \
-                                         ((__INSTANCE__) == TIM9)  || \
-                                         ((__INSTANCE__) == TIM12))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1) || \
-                                         ((__INSTANCE__) == TIM2) || \
-                                         ((__INSTANCE__) == TIM3) || \
-                                         ((__INSTANCE__) == TIM4) || \
-                                         ((__INSTANCE__) == TIM5) || \
-                                         ((__INSTANCE__) == TIM8))
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
-                                       ((__INSTANCE__) == TIM2) || \
-                                       ((__INSTANCE__) == TIM3) || \
-                                       ((__INSTANCE__) == TIM4) || \
-                                       ((__INSTANCE__) == TIM5) || \
-                                       ((__INSTANCE__) == TIM8))
-
-/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
-#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \
-                                       (((__INSTANCE__) == TIM1)    || \
-                                        ((__INSTANCE__) == TIM8))
-
-/****************** TIM Instances : supporting OCxREF clear *******************/
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\
-                                  (((__INSTANCE__) == TIM1)    || \
-                                   ((__INSTANCE__) == TIM2)    || \
-                                   ((__INSTANCE__) == TIM3)    || \
-                                   ((__INSTANCE__) == TIM4)    || \
-                                   ((__INSTANCE__) == TIM8))
-
-/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\
-                                                 (((__INSTANCE__) == TIM1)    || \
-                                                  ((__INSTANCE__) == TIM2)    || \
-                                                  ((__INSTANCE__) == TIM3)    || \
-                                                  ((__INSTANCE__) == TIM4)    || \
-                                                  ((__INSTANCE__) == TIM5)    || \
-                                                  ((__INSTANCE__) == TIM8))
-
-/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\
-                                                   (((__INSTANCE__) == TIM1)    || \
-                                                    ((__INSTANCE__) == TIM2)    || \
-                                                    ((__INSTANCE__) == TIM3)    || \
-                                                    ((__INSTANCE__) == TIM4)    || \
-                                                    ((__INSTANCE__) == TIM5)    || \
-                                                    ((__INSTANCE__) == TIM8))
-/****************** TIM Instances : at least 5 capture/compare channels *******/
-#define IS_TIM_CC5_INSTANCE(__INSTANCE__)\
-  (((__INSTANCE__) == TIM1)    || \
-   ((__INSTANCE__) == TIM8) )
-
-/****************** TIM Instances : at least 6 capture/compare channels *******/
-#define IS_TIM_CC6_INSTANCE(__INSTANCE__)\
-  (((__INSTANCE__) == TIM1)    || \
-   ((__INSTANCE__) == TIM8))
-
-
-/******************** TIM Instances : Advanced-control timers *****************/
-#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
-                                            ((__INSTANCE__) == TIM8))
-
-/****************** TIM Instances : supporting 2 break inputs *****************/
-#define IS_TIM_BREAK_INSTANCE(__INSTANCE__)\
-  (((__INSTANCE__) == TIM1)    || \
-   ((__INSTANCE__) == TIM8))
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1) || \
-                                         ((__INSTANCE__) == TIM2) || \
-                                         ((__INSTANCE__) == TIM3) || \
-                                         ((__INSTANCE__) == TIM4) || \
-                                         ((__INSTANCE__) == TIM5) || \
-                                         ((__INSTANCE__) == TIM8))
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
-                                       ((__INSTANCE__) == TIM2) || \
-                                       ((__INSTANCE__) == TIM3) || \
-                                       ((__INSTANCE__) == TIM4) || \
-                                       ((__INSTANCE__) == TIM5) || \
-                                       ((__INSTANCE__) == TIM6) || \
-                                       ((__INSTANCE__) == TIM7) || \
-                                       ((__INSTANCE__) == TIM8))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
-                                          ((__INSTANCE__) == TIM2) || \
-                                          ((__INSTANCE__) == TIM3) || \
-                                          ((__INSTANCE__) == TIM4) || \
-                                          ((__INSTANCE__) == TIM5) || \
-                                          ((__INSTANCE__) == TIM8))
-
-/************ TIM Instances : DMA requests generation (COMDE) *****************/
-#define IS_TIM_CCDMA_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1) || \
-                                          ((__INSTANCE__) == TIM2) || \
-                                          ((__INSTANCE__) == TIM3) || \
-                                          ((__INSTANCE__) == TIM4) || \
-                                          ((__INSTANCE__) == TIM5) || \
-                                          ((__INSTANCE__) == TIM8))
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1) || \
-                                             ((__INSTANCE__) == TIM2) || \
-                                             ((__INSTANCE__) == TIM3) || \
-                                             ((__INSTANCE__) == TIM4) || \
-                                             ((__INSTANCE__) == TIM5) || \
-                                             ((__INSTANCE__) == TIM8))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
-                                          ((__INSTANCE__) == TIM2) || \
-                                          ((__INSTANCE__) == TIM3) || \
-                                          ((__INSTANCE__) == TIM4) || \
-                                          ((__INSTANCE__) == TIM5) || \
-                                          ((__INSTANCE__) == TIM6) || \
-                                          ((__INSTANCE__) == TIM7) || \
-                                          ((__INSTANCE__) == TIM8) || \
-                                          ((__INSTANCE__) == TIM13) || \
-                                          ((__INSTANCE__) == TIM14))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
-                                         ((__INSTANCE__) == TIM2) || \
-                                         ((__INSTANCE__) == TIM3) || \
-                                         ((__INSTANCE__) == TIM4) || \
-                                         ((__INSTANCE__) == TIM5) || \
-                                         ((__INSTANCE__) == TIM8) || \
-                                         ((__INSTANCE__) == TIM9) || \
-                                         ((__INSTANCE__) == TIM12))
-
-/********************** TIM Instances : 32 bit Counter ************************/
-#define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__)(((__INSTANCE__) == TIM2) || \
-                                              ((__INSTANCE__) == TIM5))
-
-/***************** TIM Instances : external trigger input available ************/
-#define IS_TIM_ETR_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1) || \
-                                        ((__INSTANCE__) == TIM2) || \
-                                        ((__INSTANCE__) == TIM3) || \
-                                        ((__INSTANCE__) == TIM4) || \
-                                        ((__INSTANCE__) == TIM5) || \
-                                        ((__INSTANCE__) == TIM8))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2)  || \
-                                         ((__INSTANCE__) == TIM5)  || \
-                                         ((__INSTANCE__) == TIM11))
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \
-    ((((__INSTANCE__) == TIM1) &&                  \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM2) &&                   \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM3) &&                   \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM4) &&                   \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM5) &&                   \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM8) &&                   \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM9) &&                   \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM10) &&                  \
-     (((__CHANNEL__) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM11) &&                  \
-     (((__CHANNEL__) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM12) &&                  \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM13) &&                  \
-     (((__CHANNEL__) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM14) &&                  \
-     (((__CHANNEL__) == TIM_CHANNEL_1))))
-
-/************ TIM Instances : complementary output(s) available ***************/
-#define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \
-   ((((__INSTANCE__) == TIM1) &&                    \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||           \
-      ((__CHANNEL__) == TIM_CHANNEL_2) ||           \
-      ((__CHANNEL__) == TIM_CHANNEL_3)))            \
-    ||                                          \
-    (((__INSTANCE__) == TIM8) &&                    \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||           \
-      ((__CHANNEL__) == TIM_CHANNEL_2) ||           \
-      ((__CHANNEL__) == TIM_CHANNEL_3))))
-
-/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
-#define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\
-  (((__INSTANCE__) == TIM1)    || \
-   ((__INSTANCE__) == TIM8) )
-
-/****************** TIM Instances : supporting synchronization ****************/
-#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
-    (((__INSTANCE__) == TIM1)    || \
-     ((__INSTANCE__) == TIM2)    || \
-     ((__INSTANCE__) == TIM3)    || \
-     ((__INSTANCE__) == TIM4)    || \
-     ((__INSTANCE__) == TIM5)    || \
-     ((__INSTANCE__) == TIM6)    || \
-     ((__INSTANCE__) == TIM7)    || \
-     ((__INSTANCE__) == TIM8))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
-                                     ((__INSTANCE__) == USART2) || \
-                                     ((__INSTANCE__) == USART3) || \
-                                     ((__INSTANCE__) == USART6))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
-                                    ((__INSTANCE__) == USART2) || \
-                                    ((__INSTANCE__) == USART3) || \
-                                    ((__INSTANCE__) == UART4)  || \
-                                    ((__INSTANCE__) == UART5)  || \
-                                    ((__INSTANCE__) == USART6) || \
-                                    ((__INSTANCE__) == UART7)  || \
-                                    ((__INSTANCE__) == UART8))
-
-/****************** UART Instances : Driver Enable *****************/
-#define IS_UART_DRIVER_ENABLE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
-                                    ((__INSTANCE__) == USART2) || \
-                                    ((__INSTANCE__) == USART3) || \
-                                    ((__INSTANCE__) == UART4)  || \
-                                    ((__INSTANCE__) == UART5)  || \
-                                    ((__INSTANCE__) == USART6) || \
-                                    ((__INSTANCE__) == UART7)  || \
-                                    ((__INSTANCE__) == UART8))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
-                                    ((__INSTANCE__) == USART2) || \
-                                    ((__INSTANCE__) == USART3) || \
-                                    ((__INSTANCE__) == UART4)  || \
-                                    ((__INSTANCE__) == UART5)  || \
-                                    ((__INSTANCE__) == USART6) || \
-                                    ((__INSTANCE__) == UART7)  || \
-                                    ((__INSTANCE__) == UART8))
-
-/********************* UART Instances : Smart card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
-                                         ((__INSTANCE__) == USART2) || \
-                                         ((__INSTANCE__) == USART3) || \
-                                         ((__INSTANCE__) == USART6))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
-                                    ((__INSTANCE__) == USART2) || \
-                                    ((__INSTANCE__) == USART3) || \
-                                    ((__INSTANCE__) == UART4)  || \
-                                    ((__INSTANCE__) == UART5)  || \
-                                    ((__INSTANCE__) == USART6) || \
-                                    ((__INSTANCE__) == UART7)  || \
-                                    ((__INSTANCE__) == UART8))
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == WWDG)
-
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32F7xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */
-/*  product lines within the same STM32F7 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-#define RNG_IRQn              HASH_RNG_IRQn
-
-/* Aliases for __IRQHandler */
-#define RNG_IRQHandler        HASH_RNG_IRQHandler
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32F756xx_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/cmsis/stm32f767xx.h b/stmhal/cmsis/stm32f767xx.h
deleted file mode 100644
index bbe634fe85..0000000000
--- a/stmhal/cmsis/stm32f767xx.h
+++ /dev/null
@@ -1,10057 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f767xx.h
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   CMSIS Cortex-M7 Device Peripheral Access Layer Header File.
-  *
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral's registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS_Device
-  * @{
-  */
-
-/** @addtogroup stm32f767xx
-  * @{
-  */
-
-#ifndef __STM32F767xx_H
-#define __STM32F767xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-
-/**
- * @brief STM32F7xx Interrupt Number Definition, according to the selected device
- *        in @ref Library_configuration_section
- */
-typedef enum
-{
-/******  Cortex-M7 Processor Exceptions Numbers ****************************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M7 Memory Management Interrupt                           */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M7 Bus Fault Interrupt                                   */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M7 Usage Fault Interrupt                                 */
-  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M7 SV Call Interrupt                                    */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M7 Debug Monitor Interrupt                              */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M7 Pend SV Interrupt                                    */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M7 System Tick Interrupt                                */
-/******  STM32 specific Interrupt Numbers **********************************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
-  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
-  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
-  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
-  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
-  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
-  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
-  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
-  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
-  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
-  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
-  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
-  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
-  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
-  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
-  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
-  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
-  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */
-  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
-  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
-  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
-  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
-  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
-  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
-  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
-  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
-  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
-  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
-  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
-  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
-  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
-  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
-  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
-  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
-  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
-  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
-  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
-  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
-  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
-  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
-  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
-  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
-  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
-  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
-  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
-  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
-  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
-  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
-  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
-  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
-  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
-  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
-  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
-  RNG_IRQn                    = 80,     /*!< RNG global interrupt                                              */
-  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
-  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */
-  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */
-  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
-  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */
-  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */
-  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
-  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                             */
-  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                       */
-  DMA2D_IRQn                  = 90,     /*!< DMA2D global Interrupt                                            */
-  SAI2_IRQn                   = 91,     /*!< SAI2 global Interrupt                                             */
-  QUADSPI_IRQn                = 92,     /*!< Quad SPI global interrupt                                         */
-  LPTIM1_IRQn                 = 93,     /*!< LP TIM1 interrupt                                                 */
-  CEC_IRQn                    = 94,     /*!< HDMI-CEC global Interrupt                                         */
-  I2C4_EV_IRQn                = 95,     /*!< I2C4 Event Interrupt                                              */
-  I2C4_ER_IRQn                = 96,     /*!< I2C4 Error Interrupt                                              */
-  SPDIF_RX_IRQn               = 97,     /*!< SPDIF-RX global Interrupt                                         */
-  DFSDM1_FLT0_IRQn	          = 99,     /*!< DFSDM1 Filter 0 global Interrupt                                  */
-  DFSDM1_FLT1_IRQn	          = 100,    /*!< DFSDM1 Filter 1 global Interrupt                                  */
-  DFSDM1_FLT2_IRQn	          = 101,    /*!< DFSDM1 Filter 2 global Interrupt                                  */
-  DFSDM1_FLT3_IRQn	          = 102,    /*!< DFSDM1 Filter 3 global Interrupt                                  */
-  SDMMC2_IRQn                 = 103,    /*!< SDMMC2 global Interrupt                                           */
-  CAN3_TX_IRQn                = 104,    /*!< CAN3 TX Interrupt                                                 */
-  CAN3_RX0_IRQn               = 105,    /*!< CAN3 RX0 Interrupt                                                */
-  CAN3_RX1_IRQn               = 106,    /*!< CAN3 RX1 Interrupt                                                */
-  CAN3_SCE_IRQn               = 107,    /*!< CAN3 SCE Interrupt                                                */
-  JPEG_IRQn                   = 108,    /*!< JPEG global Interrupt                                             */
-  MDIOS_IRQn                  = 109     /*!< MDIO Slave global Interrupt                                       */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-/**
- * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
- */
-#define __CM7_REV                 0x0100U  /*!< Cortex-M7 revision r1p0                       */
-#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */
-#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */
-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1       /*!< FPU present                                   */
-#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */
-#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */
-#include "core_cm7.h"                     /*!< Cortex-M7 processor and core peripherals      */
-
-
-#include "system_stm32f7xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */
-
-/**
-  * @brief Analog to Digital Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */
-  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
-  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
-  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
-  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
-  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
-  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
-  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
-  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
-  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
-  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
-  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
-  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
-  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
-  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
-  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
-                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
-} ADC_Common_TypeDef;
-
-
-/**
-  * @brief Controller Area Network TxMailBox
-  */
-
-typedef struct
-{
-  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
-  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
-  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
-  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
-} CAN_TxMailBox_TypeDef;
-
-/**
-  * @brief Controller Area Network FIFOMailBox
-  */
-
-typedef struct
-{
-  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
-  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
-  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
-  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
-} CAN_FIFOMailBox_TypeDef;
-
-/**
-  * @brief Controller Area Network FilterRegister
-  */
-
-typedef struct
-{
-  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
-  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
-} CAN_FilterRegister_TypeDef;
-
-/**
-  * @brief Controller Area Network
-  */
-
-typedef struct
-{
-  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
-  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
-  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
-  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
-  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
-  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
-  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
-  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
-  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
-  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
-  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
-  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
-  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
-  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
-  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
-  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
-  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
-  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
-  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
-  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
-  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */
-  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
-} CAN_TypeDef;
-
-/**
-  * @brief HDMI-CEC
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< CEC control register,                                       Address offset:0x00 */
-  __IO uint32_t CFGR;         /*!< CEC configuration register,                                 Address offset:0x04 */
-  __IO uint32_t TXDR;         /*!< CEC Tx data register ,                                      Address offset:0x08 */
-  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,                                       Address offset:0x0C */
-  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register,                          Address offset:0x10 */
-  __IO uint32_t IER;          /*!< CEC interrupt enable register,                              Address offset:0x14 */
-}CEC_TypeDef;
-
-/**
-  * @brief CRC calculation unit
-  */
-
-typedef struct
-{
-  __IO uint32_t  DR;          /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint8_t   IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
-  uint8_t        RESERVED0;   /*!< Reserved, 0x05                                                    */
-  uint16_t       RESERVED1;   /*!< Reserved, 0x06                                                    */
-  __IO uint32_t  CR;          /*!< CRC Control register,                        Address offset: 0x08 */
-  uint32_t       RESERVED2;   /*!< Reserved,                                                    0x0C */
-  __IO uint32_t  INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
-  __IO uint32_t  POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
-} CRC_TypeDef;
-
-/**
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
-  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
-  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
-  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
-  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
-  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
-  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
-  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
-  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
-  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
-  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
-  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
-  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
-} DAC_TypeDef;
-
-/**
-  * @brief DFSDM module registers
-  */
-typedef struct
-{
-  __IO uint32_t FLTCR1;         /*!< DFSDM control register1,                          Address offset: 0x100 */
-  __IO uint32_t FLTCR2;         /*!< DFSDM control register2,                          Address offset: 0x104 */
-  __IO uint32_t FLTISR;         /*!< DFSDM interrupt and status register,              Address offset: 0x108 */
-  __IO uint32_t FLTICR;         /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */
-  __IO uint32_t FLTJCHGR;       /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */
-  __IO uint32_t FLTFCR;         /*!< DFSDM filter control register,                    Address offset: 0x114 */
-  __IO uint32_t FLTJDATAR;      /*!< DFSDM data register for injected group,           Address offset: 0x118 */
-  __IO uint32_t FLTRDATAR;      /*!< DFSDM data register for regular group,            Address offset: 0x11C */
-  __IO uint32_t FLTAWHTR;       /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */
-  __IO uint32_t FLTAWLTR;       /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */
-  __IO uint32_t FLTAWSR;        /*!< DFSDM analog watchdog status register             Address offset: 0x128 */
-  __IO uint32_t FLTAWCFR;       /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */
-  __IO uint32_t FLTEXMAX;       /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */
-  __IO uint32_t FLTEXMIN;       /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */
-  __IO uint32_t FLTCNVTIMR;     /*!< DFSDM conversion timer,                           Address offset: 0x138 */
-} DFSDM_Filter_TypeDef;
-
-/**
-  * @brief DFSDM channel configuration registers
-  */
-typedef struct
-{
-  __IO uint32_t CHCFGR1;     /*!< DFSDM channel configuration register1,            Address offset: 0x00 */
-  __IO uint32_t CHCFGR2;     /*!< DFSDM channel configuration register2,            Address offset: 0x04 */
-  __IO uint32_t CHAWSCDR;    /*!< DFSDM channel analog watchdog and
-                                  short circuit detector register,                  Address offset: 0x08 */
-  __IO uint32_t CHWDATAR;    /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */
-  __IO uint32_t CHDATINR;    /*!< DFSDM channel data input register,                Address offset: 0x10 */
-} DFSDM_Channel_TypeDef;
-
-/**
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
-  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
-  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
-  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/**
-  * @brief DCMI
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
-  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
-  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
-  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
-  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
-  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
-  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
-  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
-  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
-  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
-  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
-} DCMI_TypeDef;
-
-/**
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
-  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
-  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
-  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
-  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
-  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
-} DMA_Stream_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
-  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
-  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
-  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
-} DMA_TypeDef;
-
-/**
-  * @brief DMA2D Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
-  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
-  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
-  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
-  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
-  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
-  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
-  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
-  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
-  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
-  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
-  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
-  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
-  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
-  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
-  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
-  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
-  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
-  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
-  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
-  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
-  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */
-  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */
-} DMA2D_TypeDef;
-
-
-/**
-  * @brief Ethernet MAC
-  */
-
-typedef struct
-{
-  __IO uint32_t MACCR;
-  __IO uint32_t MACFFR;
-  __IO uint32_t MACHTHR;
-  __IO uint32_t MACHTLR;
-  __IO uint32_t MACMIIAR;
-  __IO uint32_t MACMIIDR;
-  __IO uint32_t MACFCR;
-  __IO uint32_t MACVLANTR;             /*    8 */
-  uint32_t      RESERVED0[2];
-  __IO uint32_t MACRWUFFR;             /*   11 */
-  __IO uint32_t MACPMTCSR;
-  uint32_t      RESERVED1[2];
-  __IO uint32_t MACSR;                 /*   15 */
-  __IO uint32_t MACIMR;
-  __IO uint32_t MACA0HR;
-  __IO uint32_t MACA0LR;
-  __IO uint32_t MACA1HR;
-  __IO uint32_t MACA1LR;
-  __IO uint32_t MACA2HR;
-  __IO uint32_t MACA2LR;
-  __IO uint32_t MACA3HR;
-  __IO uint32_t MACA3LR;               /*   24 */
-  uint32_t      RESERVED2[40];
-  __IO uint32_t MMCCR;                 /*   65 */
-  __IO uint32_t MMCRIR;
-  __IO uint32_t MMCTIR;
-  __IO uint32_t MMCRIMR;
-  __IO uint32_t MMCTIMR;               /*   69 */
-  uint32_t      RESERVED3[14];
-  __IO uint32_t MMCTGFSCCR;            /*   84 */
-  __IO uint32_t MMCTGFMSCCR;
-  uint32_t      RESERVED4[5];
-  __IO uint32_t MMCTGFCR;
-  uint32_t      RESERVED5[10];
-  __IO uint32_t MMCRFCECR;
-  __IO uint32_t MMCRFAECR;
-  uint32_t      RESERVED6[10];
-  __IO uint32_t MMCRGUFCR;
-  uint32_t      RESERVED7[334];
-  __IO uint32_t PTPTSCR;
-  __IO uint32_t PTPSSIR;
-  __IO uint32_t PTPTSHR;
-  __IO uint32_t PTPTSLR;
-  __IO uint32_t PTPTSHUR;
-  __IO uint32_t PTPTSLUR;
-  __IO uint32_t PTPTSAR;
-  __IO uint32_t PTPTTHR;
-  __IO uint32_t PTPTTLR;
-  __IO uint32_t RESERVED8;
-  __IO uint32_t PTPTSSR;
-  uint32_t      RESERVED9[565];
-  __IO uint32_t DMABMR;
-  __IO uint32_t DMATPDR;
-  __IO uint32_t DMARPDR;
-  __IO uint32_t DMARDLAR;
-  __IO uint32_t DMATDLAR;
-  __IO uint32_t DMASR;
-  __IO uint32_t DMAOMR;
-  __IO uint32_t DMAIER;
-  __IO uint32_t DMAMFBOCR;
-  __IO uint32_t DMARSWTR;
-  uint32_t      RESERVED10[8];
-  __IO uint32_t DMACHTDR;
-  __IO uint32_t DMACHRDR;
-  __IO uint32_t DMACHTBAR;
-  __IO uint32_t DMACHRBAR;
-} ETH_TypeDef;
-
-/**
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
-  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
-  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
-  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
-  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
-  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/**
-  * @brief FLASH Registers
-  */
-
-typedef struct
-{
-  __IO uint32_t ACR;      /*!< FLASH access control register,     Address offset: 0x00 */
-  __IO uint32_t KEYR;     /*!< FLASH key register,                Address offset: 0x04 */
-  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,         Address offset: 0x08 */
-  __IO uint32_t SR;       /*!< FLASH status register,             Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< FLASH control register,            Address offset: 0x10 */
-  __IO uint32_t OPTCR;    /*!< FLASH option control register ,    Address offset: 0x14 */
-  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1 ,  Address offset: 0x18 */
-} FLASH_TypeDef;
-
-
-
-/**
-  * @brief Flexible Memory Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
-} FMC_Bank1_TypeDef;
-
-/**
-  * @brief Flexible Memory Controller Bank1E
-  */
-
-typedef struct
-{
-  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
-} FMC_Bank1E_TypeDef;
-
-/**
-  * @brief Flexible Memory Controller Bank3
-  */
-
-typedef struct
-{
-  __IO uint32_t PCR;        /*!< NAND Flash control register,                       Address offset: 0x80 */
-  __IO uint32_t SR;         /*!< NAND Flash FIFO status and interrupt register,     Address offset: 0x84 */
-  __IO uint32_t PMEM;       /*!< NAND Flash Common memory space timing register,    Address offset: 0x88 */
-  __IO uint32_t PATT;       /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
-  uint32_t      RESERVED0;  /*!< Reserved, 0x90                                                          */
-  __IO uint32_t ECCR;       /*!< NAND Flash ECC result registers,                   Address offset: 0x94 */
-} FMC_Bank3_TypeDef;
-
-/**
-  * @brief Flexible Memory Controller Bank5_6
-  */
-
-typedef struct
-{
-  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */
-  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */
-  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */
-  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */
-  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */
-} FMC_Bank5_6_TypeDef;
-
-
-/**
-  * @brief General Purpose I/O
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
-  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
-  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
-  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
-  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
-  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
-  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
-  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/**
-  * @brief System configuration controller
-  */
-
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-  uint32_t      RESERVED;     /*!< Reserved, 0x18                                                               */
-  __IO uint32_t CBR;          /*!< SYSCFG Class B register,                           Address offset: 0x1C      */
-  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
-} SYSCFG_TypeDef;
-
-/**
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
-  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
-} I2C_TypeDef;
-
-/**
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
-} IWDG_TypeDef;
-
-
-/**
-  * @brief LCD-TFT Display Controller
-  */
-
-typedef struct
-{
-  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04 */
-  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */
-  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */
-  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */
-  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */
-  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */
-  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20 */
-  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */
-  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28 */
-  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */
-  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30 */
-  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */
-  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */
-  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */
-  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
-  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */
-  __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                 Address offset: 0x48 */
-} LTDC_TypeDef;
-
-/**
-  * @brief LCD-TFT Display layer x Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */
-  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
-  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */
-  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */
-  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */
-  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */
-  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */
-  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */
-  uint32_t      RESERVED0[2];  /*!< Reserved */
-  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */
-  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */
-  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */
-  uint32_t      RESERVED1[3];  /*!< Reserved */
-  __IO uint32_t CLUTWR;        /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */
-
-} LTDC_Layer_TypeDef;
-
-/**
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;   /*!< PWR power control register 1,        Address offset: 0x00 */
-  __IO uint32_t CSR1;  /*!< PWR power control/status register 2, Address offset: 0x04 */
-  __IO uint32_t CR2;   /*!< PWR power control register 2,        Address offset: 0x08 */
-  __IO uint32_t CSR2;  /*!< PWR power control/status register 2, Address offset: 0x0C */
-} PWR_TypeDef;
-
-
-/**
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
-  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
-  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
-  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
-  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
-  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
-  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
-  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
-  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
-  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
-  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
-  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
-  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
-  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
-  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
-  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
-  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
-  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
-  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
-  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
-  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
-  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
-  __IO uint32_t PLLSAICFGR;    /*!< RCC PLLSAI configuration register,                           Address offset: 0x88 */
-  __IO uint32_t DCKCFGR1;      /*!< RCC Dedicated Clocks configuration register1,                 Address offset: 0x8C */
-  __IO uint32_t DCKCFGR2;      /*!< RCC Dedicated Clocks configuration register 2,               Address offset: 0x90 */
-
-} RCC_TypeDef;
-
-/**
-  * @brief Real-Time Clock
-  */
-
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-       uint32_t reserved;   /*!< Reserved  */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
-  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset: 0x4C */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
-  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
-  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
-  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
-  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
-  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
-  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
-  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
-  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
-  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
-  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
-  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
-  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
-  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
-  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
-  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */
-  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */
-  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */
-  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */
-  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */
-  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */
-  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */
-  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */
-  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */
-  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */
-  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */
-  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */
-} RTC_TypeDef;
-
-
-/**
-  * @brief Serial Audio Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t GCR;      /*!< SAI global configuration register,        Address offset: 0x00 */
-} SAI_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */
-  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */
-  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */
-  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */
-  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
-  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */
-  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */
-  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */
-} SAI_Block_TypeDef;
-
-/**
-  * @brief SPDIF-RX Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t   CR;           /*!< Control register,                   Address offset: 0x00 */
-  __IO uint32_t   IMR;          /*!< Interrupt mask register,            Address offset: 0x04 */
-  __IO uint32_t   SR;           /*!< Status register,                    Address offset: 0x08 */
-  __IO uint32_t   IFCR;         /*!< Interrupt Flag Clear register,      Address offset: 0x0C */
-  __IO uint32_t   DR;           /*!< Data input register,                Address offset: 0x10 */
-  __IO uint32_t   CSR;          /*!< Channel Status register,            Address offset: 0x14 */
-  __IO uint32_t   DIR;          /*!< Debug Information register,         Address offset: 0x18 */
-} SPDIFRX_TypeDef;
-
-/**
-  * @brief SD host Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t POWER;          /*!< SDMMC power control register,    Address offset: 0x00 */
-  __IO uint32_t CLKCR;          /*!< SDMMClock control register,     Address offset: 0x04 */
-  __IO uint32_t ARG;            /*!< SDMMC argument register,         Address offset: 0x08 */
-  __IO uint32_t CMD;            /*!< SDMMC command register,          Address offset: 0x0C */
-  __I uint32_t  RESPCMD;        /*!< SDMMC command response register, Address offset: 0x10 */
-  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,       Address offset: 0x14 */
-  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,       Address offset: 0x18 */
-  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,       Address offset: 0x1C */
-  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,       Address offset: 0x20 */
-  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,       Address offset: 0x24 */
-  __IO uint32_t DLEN;           /*!< SDMMC data length register,      Address offset: 0x28 */
-  __IO uint32_t DCTRL;          /*!< SDMMC data control register,     Address offset: 0x2C */
-  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,     Address offset: 0x30 */
-  __I uint32_t  STA;            /*!< SDMMC status register,           Address offset: 0x34 */
-  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,  Address offset: 0x38 */
-  __IO uint32_t MASK;           /*!< SDMMC mask register,             Address offset: 0x3C */
-  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
-  __I uint32_t  FIFOCNT;        /*!< SDMMC FIFO counter register,     Address offset: 0x48 */
-  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
-  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,        Address offset: 0x80 */
-} SDMMC_TypeDef;
-
-/**
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/**
-  * @brief QUAD Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */
-  __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
-  __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */
-  __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
-  __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
-  __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
-  __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */
-  __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
-  __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */
-  __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
-  __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */
-  __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
-  __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */
-} QUADSPI_TypeDef;
-
-/**
-  * @brief TIM
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
-  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
-  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
-  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
-  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */
-  __IO uint32_t CCR5;        /*!< TIM capture/compare mode register5,       Address offset: 0x58 */
-  __IO uint32_t CCR6;        /*!< TIM capture/compare mode register6,       Address offset: 0x5C */
-  __IO uint32_t AF1;         /*!< TIM Alternate function option register 1, Address offset: 0x60 */
-  __IO uint32_t AF2;         /*!< TIM Alternate function option register 2, Address offset: 0x64 */
-
-} TIM_TypeDef;
-
-/**
-  * @brief LPTIMIMER
-  */
-typedef struct
-{
-  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */
-  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */
-  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */
-  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                       Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< LPTIM Control register,                             Address offset: 0x10 */
-  __IO uint32_t CMP;      /*!< LPTIM Compare register,                             Address offset: 0x14 */
-  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
-  __IO uint32_t CNT;      /*!< LPTIM Counter register,                             Address offset: 0x1C */
-} LPTIM_TypeDef;
-
-
-/**
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */
-  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */
-  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
-  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */
-  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
-  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */
-  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
-  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
-  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
-  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
-  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
-} USART_TypeDef;
-
-
-/**
-  * @brief Window WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-
-/**
-  * @brief RNG
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
-  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
-  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
-} RNG_TypeDef;
-
-/**
-  * @}
-  */
-
-/**
-  * @brief USB_OTG_Core_Registers
-  */
-typedef struct
-{
- __IO uint32_t GOTGCTL;               /*!< USB_OTG Control and Status Register          000h */
-  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */
-  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */
-  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */
-  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */
-  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */
-  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */
-  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */
-  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */
-  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */
-  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */
-  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */
-  uint32_t Reserved30[2];             /*!< Reserved                                     030h */
-  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */
-  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */
-  uint32_t  Reserved5[3];             /*!< Reserved                                040h-048h */
-  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */
-  uint32_t  Reserved6;                /*!< Reserved                                     050h */
-  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */
-  __IO uint32_t GPWRDN;               /*!< Power Down Register                          058h */
-  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */
-   __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register       60Ch */
-    uint32_t  Reserved43[39];         /*!< Reserved                                058h-0FFh */
-  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */
-  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */
-} USB_OTG_GlobalTypeDef;
-
-
-/**
-  * @brief USB_OTG_device_Registers
-  */
-typedef struct
-{
-  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */
-  __IO uint32_t DCTL;            /*!< dev Control Register         804h */
-  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */
-  uint32_t Reserved0C;           /*!< Reserved                     80Ch */
-  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */
-  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */
-  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */
-  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */
-  uint32_t  Reserved20;          /*!< Reserved                     820h */
-  uint32_t Reserved9;            /*!< Reserved                     824h */
-  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */
-  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */
-  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */
-  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */
-  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */
-  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */
-  uint32_t Reserved40;           /*!< dedicated EP mask            840h */
-  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */
-  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */
-  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */
-} USB_OTG_DeviceTypeDef;
-
-
-/**
-  * @brief USB_OTG_IN_Endpoint-Specific_Register
-  */
-typedef struct
-{
-  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */
-  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */
-  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */
-  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */
-  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */
-  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */
-  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
-  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
-} USB_OTG_INEndpointTypeDef;
-
-
-/**
-  * @brief USB_OTG_OUT_Endpoint-Specific_Registers
-  */
-typedef struct
-{
-  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */
-  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */
-  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */
-  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */
-  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */
-  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */
-  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
-} USB_OTG_OUTEndpointTypeDef;
-
-
-/**
-  * @brief USB_OTG_Host_Mode_Register_Structures
-  */
-typedef struct
-{
-  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */
-  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */
-  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */
-  uint32_t Reserved40C;           /*!< Reserved                             40Ch */
-  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */
-  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */
-  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */
-} USB_OTG_HostTypeDef;
-
-/**
-  * @brief USB_OTG_Host_Channel_Specific_Registers
-  */
-typedef struct
-{
-  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */
-  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */
-  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */
-  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */
-  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */
-  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */
-  uint32_t Reserved[2];           /*!< Reserved                                      */
-} USB_OTG_HostChannelTypeDef;
-/**
-  * @}
-  */
-
-/**
-  * @brief JPEG Codec
-  */
-typedef struct
-{
-  __IO uint32_t CONFR0;          /*!< JPEG Codec Control Register (JPEG_CONFR0),        Address offset: 00h       */
-  __IO uint32_t CONFR1;          /*!< JPEG Codec Control Register (JPEG_CONFR1),        Address offset: 04h       */
-  __IO uint32_t CONFR2;          /*!< JPEG Codec Control Register (JPEG_CONFR2),        Address offset: 08h       */
-  __IO uint32_t CONFR3;          /*!< JPEG Codec Control Register (JPEG_CONFR3),        Address offset: 0Ch       */
-  __IO uint32_t CONFR4;          /*!< JPEG Codec Control Register (JPEG_CONFR4),        Address offset: 10h       */
-  __IO uint32_t CONFR5;          /*!< JPEG Codec Control Register (JPEG_CONFR5),        Address offset: 14h       */
-  __IO uint32_t CONFR6;          /*!< JPEG Codec Control Register (JPEG_CONFR6),        Address offset: 18h       */
-  __IO uint32_t CONFR7;          /*!< JPEG Codec Control Register (JPEG_CONFR7),        Address offset: 1Ch       */
-  uint32_t  Reserved20[4];       /* Reserved                                            Address offset: 20h-2Ch   */
-  __IO uint32_t CR;              /*!< JPEG Control Register (JPEG_CR),                  Address offset: 30h       */
-  __IO uint32_t SR;              /*!< JPEG Status Register (JPEG_SR),                   Address offset: 34h       */
-  __IO uint32_t CFR;             /*!< JPEG Clear Flag Register (JPEG_CFR),              Address offset: 38h       */
-  uint32_t  Reserved3c;          /* Reserved                                            Address offset: 3Ch       */
-  __IO uint32_t DIR;             /*!< JPEG Data Input Register (JPEG_DIR),              Address offset: 40h       */
-  __IO uint32_t DOR;             /*!< JPEG Data Output Register (JPEG_DOR),             Address offset: 44h       */
-  uint32_t  Reserved48[2];       /* Reserved                                            Address offset: 48h-4Ch   */
-  __IO uint32_t QMEM0[16];       /*!< JPEG quantization tables 0,                       Address offset: 50h-8Ch   */
-  __IO uint32_t QMEM1[16];       /*!< JPEG quantization tables 1,                       Address offset: 90h-CCh   */
-  __IO uint32_t QMEM2[16];       /*!< JPEG quantization tables 2,                       Address offset: D0h-10Ch  */
-  __IO uint32_t QMEM3[16];       /*!< JPEG quantization tables 3,                       Address offset: 110h-14Ch */
-  __IO uint32_t HUFFMIN[16];     /*!< JPEG HuffMin tables,                              Address offset: 150h-18Ch */
-  __IO uint32_t HUFFBASE[32];    /*!< JPEG HuffSymb tables,                             Address offset: 190h-20Ch */
-  __IO uint32_t HUFFSYMB[84];    /*!< JPEG HUFFSYMB tables,                             Address offset: 210h-35Ch */
-  __IO uint32_t DHTMEM[103];     /*!< JPEG DHTMem tables,                               Address offset: 360h-4F8h */
-  uint32_t  Reserved4FC;         /* Reserved                                            Address offset: 4FCh      */
-  __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encoder, AC Huffman table 0,                 Address offset: 500h-65Ch */
-  __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encoder, AC Huffman table 1,                 Address offset: 660h-7BCh */
-  __IO uint32_t HUFFENC_DC0[8];  /*!< JPEG encoder, DC Huffman table 0,                 Address offset: 7C0h-7DCh */
-  __IO uint32_t HUFFENC_DC1[8];  /*!< JPEG encoder, DC Huffman table 1,                 Address offset: 7E0h-7FCh */
-
-} JPEG_TypeDef;
-
-/**
-  * @brief MDIOS
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;               /*!< MDIOS Configuration Register (MDIOS_CR),        Address offset: 00h       */
-  __IO uint32_t WRFR;             /*!< MDIOS Configuration Register (MDIOS_CR),        Address offset: 04h       */
-  __IO uint32_t CWRFR;            /*!< MDIOS Configuration Register (MDIOS_CR),        Address offset: 08h       */
-  __IO uint32_t RDFR;             /*!< MDIOS Configuration Register (MDIOS_CR),        Address offset: 0Ch       */
-  __IO uint32_t CRDFR;            /*!< MDIOS Configuration Register (MDIOS_CR),        Address offset: 10h       */
-  __IO uint32_t SR;               /*!< MDIOS Configuration Register (MDIOS_CR),        Address offset: 14h       */
-  __IO uint32_t CLRFR;            /*!< MDIOS Configuration Register (MDIOS_CR),        Address offset: 18h       */
-  uint32_t RESERVED0[57];         /* Reserved                                          Address offset: 1Ch       */
-  __IO uint32_t DINR0;            /*!< MDIOS Input Data Register (MDIOS_DINR0),        Address offset: 100h      */
-  __IO uint32_t DINR1;            /*!< MDIOS Input Data Register (MDIOS_DINR1),        Address offset: 104h      */
-  __IO uint32_t DINR2;            /*!< MDIOS Input Data Register (MDIOS_DINR2),        Address offset: 108h      */
-  __IO uint32_t DINR3;            /*!< MDIOS Input Data Register (MDIOS_DINR3),        Address offset: 10Ch      */
-  __IO uint32_t DINR4;            /*!< MDIOS Input Data Register (MDIOS_DINR4),        Address offset: 110h      */
-  __IO uint32_t DINR5;            /*!< MDIOS Input Data Register (MDIOS_DINR5),        Address offset: 114h      */
-  __IO uint32_t DINR6;            /*!< MDIOS Input Data Register (MDIOS_DINR6),        Address offset: 118h      */
-  __IO uint32_t DINR7;            /*!< MDIOS Input Data Register (MDIOS_DINR7),        Address offset: 11Ch      */
-  __IO uint32_t DINR8;            /*!< MDIOS Input Data Register (MDIOS_DINR8),        Address offset: 120h      */
-  __IO uint32_t DINR9;            /*!< MDIOS Input Data Register (MDIOS_DINR9),        Address offset: 124h      */
-  __IO uint32_t DINR10;           /*!< MDIOS Input Data Register (MDIOS_DINR10),       Address offset: 128h      */
-  __IO uint32_t DINR11;           /*!< MDIOS Input Data Register (MDIOS_DINR11),       Address offset: 12Ch      */
-  __IO uint32_t DINR12;           /*!< MDIOS Input Data Register (MDIOS_DINR12),       Address offset: 130h      */
-  __IO uint32_t DINR13;           /*!< MDIOS Input Data Register (MDIOS_DINR13),       Address offset: 134h      */
-  __IO uint32_t DINR14;           /*!< MDIOS Input Data Register (MDIOS_DINR14),       Address offset: 138h      */
-  __IO uint32_t DINR15;           /*!< MDIOS Input Data Register (MDIOS_DINR15),       Address offset: 13Ch      */
-  __IO uint32_t DINR16;           /*!< MDIOS Input Data Register (MDIOS_DINR16),       Address offset: 140h      */
-  __IO uint32_t DINR17;           /*!< MDIOS Input Data Register (MDIOS_DINR17),       Address offset: 144h      */
-  __IO uint32_t DINR18;           /*!< MDIOS Input Data Register (MDIOS_DINR18),       Address offset: 148h      */
-  __IO uint32_t DINR19;           /*!< MDIOS Input Data Register (MDIOS_DINR19),       Address offset: 14Ch      */
-  __IO uint32_t DINR20;           /*!< MDIOS Input Data Register (MDIOS_DINR20),       Address offset: 150h      */
-  __IO uint32_t DINR21;           /*!< MDIOS Input Data Register (MDIOS_DINR21),       Address offset: 154h      */
-  __IO uint32_t DINR22;           /*!< MDIOS Input Data Register (MDIOS_DINR22),       Address offset: 158h      */
-  __IO uint32_t DINR23;           /*!< MDIOS Input Data Register (MDIOS_DINR23),       Address offset: 15Ch      */
-  __IO uint32_t DINR24;           /*!< MDIOS Input Data Register (MDIOS_DINR24),       Address offset: 160h      */
-  __IO uint32_t DINR25;           /*!< MDIOS Input Data Register (MDIOS_DINR25),       Address offset: 164h      */
-  __IO uint32_t DINR26;           /*!< MDIOS Input Data Register (MDIOS_DINR26),       Address offset: 168h      */
-  __IO uint32_t DINR27;           /*!< MDIOS Input Data Register (MDIOS_DINR27),       Address offset: 16Ch      */
-  __IO uint32_t DINR28;           /*!< MDIOS Input Data Register (MDIOS_DINR28),       Address offset: 170h      */
-  __IO uint32_t DINR29;           /*!< MDIOS Input Data Register (MDIOS_DINR29),       Address offset: 174h      */
-  __IO uint32_t DINR30;           /*!< MDIOS Input Data Register (MDIOS_DINR30),       Address offset: 178h      */
-  __IO uint32_t DINR31;           /*!< MDIOS Input Data Register (MDIOS_DINR31),       Address offset: 17Ch      */
-  __IO uint32_t DOUTR0;           /*!< MDIOS Output Data Register (MDIOS_DOUTR0),      Address offset: 180h      */
-  __IO uint32_t DOUTR1;           /*!< MDIOS Output Data Register (MDIOS_DOUTR1),      Address offset: 184h      */
-  __IO uint32_t DOUTR2;           /*!< MDIOS Output Data Register (MDIOS_DOUTR2),      Address offset: 188h      */
-  __IO uint32_t DOUTR3;           /*!< MDIOS Output Data Register (MDIOS_DOUTR3),      Address offset: 18Ch      */
-  __IO uint32_t DOUTR4;           /*!< MDIOS Output Data Register (MDIOS_DOUTR4),      Address offset: 190h      */
-  __IO uint32_t DOUTR5;           /*!< MDIOS Output Data Register (MDIOS_DOUTR5),      Address offset: 194h      */
-  __IO uint32_t DOUTR6;           /*!< MDIOS Output Data Register (MDIOS_DOUTR6),      Address offset: 198h      */
-  __IO uint32_t DOUTR7;           /*!< MDIOS Output Data Register (MDIOS_DOUTR7),      Address offset: 19Ch      */
-  __IO uint32_t DOUTR8;           /*!< MDIOS Output Data Register (MDIOS_DOUTR8),      Address offset: 1A0h      */
-  __IO uint32_t DOUTR9;           /*!< MDIOS Output Data Register (MDIOS_DOUTR9),      Address offset: 1A4h      */
-  __IO uint32_t DOUTR10;          /*!< MDIOS Output Data Register (MDIOS_DOUTR10),     Address offset: 1A8h      */
-  __IO uint32_t DOUTR11;          /*!< MDIOS Output Data Register (MDIOS_DOUTR11),     Address offset: 1ACh      */
-  __IO uint32_t DOUTR12;          /*!< MDIOS Output Data Register (MDIOS_DOUTR12),     Address offset: 1B0h      */
-  __IO uint32_t DOUTR13;          /*!< MDIOS Output Data Register (MDIOS_DOUTR13),     Address offset: 1B4h      */
-  __IO uint32_t DOUTR14;          /*!< MDIOS Output Data Register (MDIOS_DOUTR14),     Address offset: 1B8h      */
-  __IO uint32_t DOUTR15;          /*!< MDIOS Output Data Register (MDIOS_DOUTR15),     Address offset: 1BCh      */
-  __IO uint32_t DOUTR16;          /*!< MDIOS Output Data Register (MDIOS_DOUTR16),     Address offset: 1C0h      */
-  __IO uint32_t DOUTR17;          /*!< MDIOS Output Data Register (MDIOS_DOUTR17),     Address offset: 1C4h      */
-  __IO uint32_t DOUTR18;          /*!< MDIOS Output Data Register (MDIOS_DOUTR18),     Address offset: 1C8h      */
-  __IO uint32_t DOUTR19;          /*!< MDIOS Output Data Register (MDIOS_DOUTR19),     Address offset: 1CCh      */
-  __IO uint32_t DOUTR20;          /*!< MDIOS Output Data Register (MDIOS_DOUTR20),     Address offset: 1D0h      */
-  __IO uint32_t DOUTR21;          /*!< MDIOS Output Data Register (MDIOS_DOUTR21),     Address offset: 1D4h      */
-  __IO uint32_t DOUTR22;          /*!< MDIOS Output Data Register (MDIOS_DOUTR22),     Address offset: 1D8h      */
-  __IO uint32_t DOUTR23;          /*!< MDIOS Output Data Register (MDIOS_DOUTR23),     Address offset: 1DCh      */
-  __IO uint32_t DOUTR24;          /*!< MDIOS Output Data Register (MDIOS_DOUTR24),     Address offset: 1E0h      */
-  __IO uint32_t DOUTR25;          /*!< MDIOS Output Data Register (MDIOS_DOUTR25),     Address offset: 1E4h      */
-  __IO uint32_t DOUTR26;          /*!< MDIOS Output Data Register (MDIOS_DOUTR26),     Address offset: 1E8h      */
-  __IO uint32_t DOUTR27;          /*!< MDIOS Output Data Register (MDIOS_DOUTR27),     Address offset: 1ECh      */
-  __IO uint32_t DOUTR28;          /*!< MDIOS Output Data Register (MDIOS_DOUTR28),     Address offset: 1F0h      */
-  __IO uint32_t DOUTR29;          /*!< MDIOS Output Data Register (MDIOS_DOUTR29),     Address offset: 1F4h      */
-  __IO uint32_t DOUTR30;          /*!< MDIOS Output Data Register (MDIOS_DOUTR30),     Address offset: 1F8h      */
-  __IO uint32_t DOUTR31;          /*!< MDIOS Output Data Register (MDIOS_DOUTR31),     Address offset: 1FCh      */
-} MDIOS_TypeDef;
-
-
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-#define RAMITCM_BASE           0x00000000U /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM  */
-#define FLASHITCM_BASE         0x00200000U /*!< Base address of : (up to 2 MB) embedded FLASH memory  accessible over ITCM              */
-#define FLASHAXI_BASE          0x08000000U /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI                */
-#define RAMDTCM_BASE           0x20000000U /*!< Base address of : 128KB system data RAM accessible over DTCM                            */
-#define PERIPH_BASE            0x40000000U /*!< Base address of : AHB/ABP Peripherals                                                   */
-#define BKPSRAM_BASE           0x40024000U /*!< Base address of : Backup SRAM(4 KB)                                                     */
-#define QSPI_BASE              0x90000000U /*!< Base address of : QSPI memories  accessible over AXI                                    */
-#define FMC_R_BASE             0xA0000000U /*!< Base address of : FMC Control registers                                                 */
-#define QSPI_R_BASE            0xA0001000U /*!< Base address of : QSPI Control  registers                                               */
-#define SRAM1_BASE             0x20020000U /*!< Base address of : 368KB RAM1 accessible over AXI/AHB                                    */
-#define SRAM2_BASE             0x2007C000U /*!< Base address of : 16KB RAM2 accessible over AXI/AHB                                     */
-#define FLASH_END              0x081FFFFFU /*!< FLASH end address */
-
-/* Legacy define */
-#define FLASH_BASE     FLASHAXI_BASE
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE        PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000U)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)
-#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800U)
-#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00U)
-#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000U)
-#define LPTIM1_BASE           (APB1PERIPH_BASE + 0x2400U)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)
-#define CAN3_BASE             (APB1PERIPH_BASE + 0x3400U)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)
-#define SPDIFRX_BASE          (APB1PERIPH_BASE + 0x4000U)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800U)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00U)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x5000U)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)
-#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)
-#define I2C4_BASE             (APB1PERIPH_BASE + 0x6000U)
-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)
-#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800U)
-#define CEC_BASE              (APB1PERIPH_BASE + 0x6C00U)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)
-#define UART7_BASE            (APB1PERIPH_BASE + 0x7800U)
-#define UART8_BASE            (APB1PERIPH_BASE + 0x7C00U)
-
-/*!< APB2 peripherals */
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000U)
-#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400U)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x1000U)
-#define USART6_BASE           (APB2PERIPH_BASE + 0x1400U)
-#define SDMMC2_BASE           (APB2PERIPH_BASE + 0x1C00U)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000U)
-#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100U)
-#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200U)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x2300U)
-#define SDMMC1_BASE           (APB2PERIPH_BASE + 0x2C00U)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)
-#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400U)
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800U)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00U)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000U)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400U)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800U)
-#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000U)
-#define SPI6_BASE             (APB2PERIPH_BASE + 0x5400U)
-#define SAI1_BASE             (APB2PERIPH_BASE + 0x5800U)
-#define SAI2_BASE             (APB2PERIPH_BASE + 0x5C00U)
-#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004U)
-#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024U)
-#define SAI2_Block_A_BASE     (SAI2_BASE + 0x004U)
-#define SAI2_Block_B_BASE     (SAI2_BASE + 0x024U)
-#define LTDC_BASE             (APB2PERIPH_BASE + 0x6800U)
-#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84U)
-#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104U)
-#define DFSDM1_BASE           (APB2PERIPH_BASE + 0x7400U)
-#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00U)
-#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20U)
-#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40U)
-#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60U)
-#define DFSDM1_Channel4_BASE  (DFSDM1_BASE + 0x80U)
-#define DFSDM1_Channel5_BASE  (DFSDM1_BASE + 0xA0U)
-#define DFSDM1_Channel6_BASE  (DFSDM1_BASE + 0xC0U)
-#define DFSDM1_Channel7_BASE  (DFSDM1_BASE + 0xE0U)
-#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100U)
-#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180U)
-#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200U)
-#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280U)
-#define MDIOS_BASE            (APB2PERIPH_BASE + 0x7800U)
-/*!< AHB1 peripherals */
-#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000U)
-#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400U)
-#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800U)
-#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00U)
-#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000U)
-#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400U)
-#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800U)
-#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00U)
-#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000U)
-#define GPIOJ_BASE            (AHB1PERIPH_BASE + 0x2400U)
-#define GPIOK_BASE            (AHB1PERIPH_BASE + 0x2800U)
-#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)
-#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800U)
-#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00U)
-#define UID_BASE              0x1FF0F420U                   /*!< Unique device ID register base address */
-#define FLASHSIZE_BASE        0x1FF0F442U                   /*!< FLASH Size register base address */
-#define PACKAGESIZE_BASE      0x1FFF7BF0U                   /*!< Package size register base address */
-#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000U)
-#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010U)
-#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028U)
-#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040U)
-#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058U)
-#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070U)
-#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088U)
-#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0U)
-#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8U)
-#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400U)
-#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010U)
-#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028U)
-#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040U)
-#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058U)
-#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070U)
-#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088U)
-#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0U)
-#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)
-#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000U)
-#define ETH_MAC_BASE          (ETH_BASE)
-#define ETH_MMC_BASE          (ETH_BASE + 0x0100U)
-#define ETH_PTP_BASE          (ETH_BASE + 0x0700U)
-#define ETH_DMA_BASE          (ETH_BASE + 0x1000U)
-#define DMA2D_BASE            (AHB1PERIPH_BASE + 0xB000U)
-/*!< AHB2 peripherals */
-#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000U)
-#define JPEG_BASE           (AHB2PERIPH_BASE + 0x51000U)
-#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800U)
-/*!< FMC Bankx registers base address */
-#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000U)
-#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104U)
-#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080U)
-#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140U)
-
-/* Debug MCU registers base address */
-#define DBGMCU_BASE           0xE0042000U
-
-/*!< USB registers base address */
-#define USB_OTG_HS_PERIPH_BASE               0x40040000U
-#define USB_OTG_FS_PERIPH_BASE               0x50000000U
-
-#define USB_OTG_GLOBAL_BASE                  0x000U
-#define USB_OTG_DEVICE_BASE                  0x800U
-#define USB_OTG_IN_ENDPOINT_BASE             0x900U
-#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U
-#define USB_OTG_EP_REG_SIZE                  0x20U
-#define USB_OTG_HOST_BASE                    0x400U
-#define USB_OTG_HOST_PORT_BASE               0x440U
-#define USB_OTG_HOST_CHANNEL_BASE            0x500U
-#define USB_OTG_HOST_CHANNEL_SIZE            0x20U
-#define USB_OTG_PCGCCTL_BASE                 0xE00U
-#define USB_OTG_FIFO_BASE                    0x1000U
-#define USB_OTG_FIFO_SIZE                    0x1000U
-
-/**
-  * @}
-  */
-
-/** @addtogroup Peripheral_declaration
-  * @{
-  */
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
-#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
-#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
-#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define SPDIFRX             ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define UART4               ((USART_TypeDef *) UART4_BASE)
-#define UART5               ((USART_TypeDef *) UART5_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
-#define I2C4                ((I2C_TypeDef *) I2C4_BASE)
-#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
-#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
-#define CEC                 ((CEC_TypeDef *) CEC_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
-#define UART7               ((USART_TypeDef *) UART7_BASE)
-#define UART8               ((USART_TypeDef *) UART8_BASE)
-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
-#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define USART6              ((USART_TypeDef *) USART6_BASE)
-#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
-#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
-#define SDMMC1              ((SDMMC_TypeDef *) SDMMC1_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define SPI4                ((SPI_TypeDef *) SPI4_BASE)
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-#define SPI5                ((SPI_TypeDef *) SPI5_BASE)
-#define SPI6                ((SPI_TypeDef *) SPI6_BASE)
-#define SAI1                ((SAI_TypeDef *) SAI1_BASE)
-#define SAI2                ((SAI_TypeDef *) SAI2_BASE)
-#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
-#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
-#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
-#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
-#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)
-#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
-#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
-#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)
-#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
-#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
-#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
-#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
-#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
-#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
-#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
-#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
-#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
-#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
-#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
-#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
-#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
-#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
-#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
-#define ETH                 ((ETH_TypeDef *) ETH_BASE)
-#define DMA2D               ((DMA2D_TypeDef *)DMA2D_BASE)
-#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
-#define RNG                 ((RNG_TypeDef *) RNG_BASE)
-#define FMC_Bank1           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
-#define FMC_Bank1E          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
-#define FMC_Bank3           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
-#define FMC_Bank5_6         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
-#define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
-#define USB_OTG_HS          ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
-#define CAN3                ((CAN_TypeDef *) CAN3_BASE)
-#define SDMMC2              ((SDMMC_TypeDef *) SDMMC2_BASE)
-#define MDIOS               ((MDIOS_TypeDef *) MDIOS_BASE)
-#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
-#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
-#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
-#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
-#define DFSDM1_Channel4     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
-#define DFSDM1_Channel5     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
-#define DFSDM1_Channel6     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
-#define DFSDM1_Channel7     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
-#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
-#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
-#define DFSDM1_Filter2      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
-#define DFSDM1_Filter3      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
-#define JPEG                ((JPEG_TypeDef *) JPEG_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-
-/******************************************************************************/
-/*                         Peripheral Registers_Bits_Definition               */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Analog to Digital Converter                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          0x00000001U        /*!<Analog watchdog flag                                 */
-#define  ADC_SR_EOC                          0x00000002U        /*!<End of conversion                                    */
-#define  ADC_SR_JEOC                         0x00000004U        /*!<Injected channel end of conversion                   */
-#define  ADC_SR_JSTRT                        0x00000008U        /*!<Injected channel Start flag                          */
-#define  ADC_SR_STRT                         0x00000010U        /*!<Regular channel Start flag                           */
-#define  ADC_SR_OVR                          0x00000020U        /*!<Overrun flag                                         */
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC                             */
-#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable                    */
-#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels               */
-#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
-#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion                  */
-#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels               */
-#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels              */
-#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels          */
-#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels           */
-#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution)                           */
-#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
-
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF                                       */
-#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion                                        */
-#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode                                    */
-#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC)                           */
-#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection                                  */
-#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment                                               */
-#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
-#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      ((uint16_t)0xFFFFU)            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      ((uint16_t)0xFFFFU)            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      ((uint16_t)0xFFFFU)            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      ((uint16_t)0xFFFFU)            /*!<Injected data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag               */
-#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion                  */
-#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag        */
-#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag         */
-#define  ADC_CSR_OVR1                        0x00000020U        /*!<ADC1 Overrun flag                       */
-#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag               */
-#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion                  */
-#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag        */
-#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag         */
-#define  ADC_CSR_OVR2                        0x00002000U        /*!<ADC2 Overrun flag                       */
-#define  ADC_CSR_AWD3                        0x00010000U        /*!<ADC3 Analog watchdog flag               */
-#define  ADC_CSR_EOC3                        0x00020000U        /*!<ADC3 End of conversion                  */
-#define  ADC_CSR_JEOC3                       0x00040000U        /*!<ADC3 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT3                      0x00080000U        /*!<ADC3 Injected channel Start flag        */
-#define  ADC_CSR_STRT3                       0x00100000U        /*!<ADC3 Regular channel Start flag         */
-#define  ADC_CSR_OVR3                        0x00200000U        /*!<ADC3 Overrun flag                       */
-
-/* Legacy defines */
-#define  ADC_CSR_DOVR1                       ADC_CSR_OVR1
-#define  ADC_CSR_DOVR2                       ADC_CSR_OVR2
-#define  ADC_CSR_DOVR3                       ADC_CSR_OVR3
-
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
-#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
-#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
-#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */
-#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
-
-/*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                       0x0000FFFFU         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                       0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Controller Area Network                            */
-/*                                                                            */
-/******************************************************************************/
-/*!<CAN control and status registers */
-/*******************  Bit definition for CAN_MCR register  ********************/
-#define  CAN_MCR_INRQ                        0x00000001U        /*!<Initialization Request            */
-#define  CAN_MCR_SLEEP                       0x00000002U        /*!<Sleep Mode Request                */
-#define  CAN_MCR_TXFP                        0x00000004U        /*!<Transmit FIFO Priority            */
-#define  CAN_MCR_RFLM                        0x00000008U        /*!<Receive FIFO Locked Mode          */
-#define  CAN_MCR_NART                        0x00000010U        /*!<No Automatic Retransmission       */
-#define  CAN_MCR_AWUM                        0x00000020U        /*!<Automatic Wakeup Mode             */
-#define  CAN_MCR_ABOM                        0x00000040U        /*!<Automatic Bus-Off Management      */
-#define  CAN_MCR_TTCM                        0x00000080U        /*!<Time Triggered Communication Mode */
-#define  CAN_MCR_RESET                       0x00008000U        /*!<bxCAN software master reset       */
-
-/*******************  Bit definition for CAN_MSR register  ********************/
-#define  CAN_MSR_INAK                        0x00000001U        /*!<Initialization Acknowledge  */
-#define  CAN_MSR_SLAK                        0x00000002U        /*!<Sleep Acknowledge           */
-#define  CAN_MSR_ERRI                        0x00000004U        /*!<Error Interrupt             */
-#define  CAN_MSR_WKUI                        0x00000008U        /*!<Wakeup Interrupt            */
-#define  CAN_MSR_SLAKI                       0x00000010U        /*!<Sleep Acknowledge Interrupt */
-#define  CAN_MSR_TXM                         0x00000100U        /*!<Transmit Mode               */
-#define  CAN_MSR_RXM                         0x00000200U        /*!<Receive Mode                */
-#define  CAN_MSR_SAMP                        0x00000400U        /*!<Last Sample Point           */
-#define  CAN_MSR_RX                          0x00000800U        /*!<CAN Rx Signal               */
-
-/*******************  Bit definition for CAN_TSR register  ********************/
-#define  CAN_TSR_RQCP0                       0x00000001U        /*!<Request Completed Mailbox0      */
-#define  CAN_TSR_TXOK0                       0x00000002U        /*!<Transmission OK of Mailbox0     */
-#define  CAN_TSR_ALST0                       0x00000004U        /*!<Arbitration Lost for Mailbox0   */
-#define  CAN_TSR_TERR0                       0x00000008U        /*!<Transmission Error of Mailbox0  */
-#define  CAN_TSR_ABRQ0                       0x00000080U        /*!<Abort Request for Mailbox0      */
-#define  CAN_TSR_RQCP1                       0x00000100U        /*!<Request Completed Mailbox1      */
-#define  CAN_TSR_TXOK1                       0x00000200U        /*!<Transmission OK of Mailbox1     */
-#define  CAN_TSR_ALST1                       0x00000400U        /*!<Arbitration Lost for Mailbox1   */
-#define  CAN_TSR_TERR1                       0x00000800U        /*!<Transmission Error of Mailbox1  */
-#define  CAN_TSR_ABRQ1                       0x00008000U        /*!<Abort Request for Mailbox 1     */
-#define  CAN_TSR_RQCP2                       0x00010000U        /*!<Request Completed Mailbox2      */
-#define  CAN_TSR_TXOK2                       0x00020000U        /*!<Transmission OK of Mailbox 2    */
-#define  CAN_TSR_ALST2                       0x00040000U        /*!<Arbitration Lost for mailbox 2  */
-#define  CAN_TSR_TERR2                       0x00080000U        /*!<Transmission Error of Mailbox 2 */
-#define  CAN_TSR_ABRQ2                       0x00800000U        /*!<Abort Request for Mailbox 2     */
-#define  CAN_TSR_CODE                        0x03000000U        /*!<Mailbox Code                    */
-
-#define  CAN_TSR_TME                         0x1C000000U        /*!<TME[2:0] bits */
-#define  CAN_TSR_TME0                        0x04000000U        /*!<Transmit Mailbox 0 Empty */
-#define  CAN_TSR_TME1                        0x08000000U        /*!<Transmit Mailbox 1 Empty */
-#define  CAN_TSR_TME2                        0x10000000U        /*!<Transmit Mailbox 2 Empty */
-
-#define  CAN_TSR_LOW                         0xE0000000U        /*!<LOW[2:0] bits */
-#define  CAN_TSR_LOW0                        0x20000000U        /*!<Lowest Priority Flag for Mailbox 0 */
-#define  CAN_TSR_LOW1                        0x40000000U        /*!<Lowest Priority Flag for Mailbox 1 */
-#define  CAN_TSR_LOW2                        0x80000000U        /*!<Lowest Priority Flag for Mailbox 2 */
-
-/*******************  Bit definition for CAN_RF0R register  *******************/
-#define  CAN_RF0R_FMP0                       0x00000003U        /*!<FIFO 0 Message Pending        */
-#define  CAN_RF0R_FULL0                      0x00000008U        /*!<FIFO 0 Full                   */
-#define  CAN_RF0R_FOVR0                      0x00000010U        /*!<FIFO 0 Overrun                */
-#define  CAN_RF0R_RFOM0                      0x00000020U        /*!<Release FIFO 0 Output Mailbox */
-
-/*******************  Bit definition for CAN_RF1R register  *******************/
-#define  CAN_RF1R_FMP1                       0x00000003U        /*!<FIFO 1 Message Pending        */
-#define  CAN_RF1R_FULL1                      0x00000008U        /*!<FIFO 1 Full                   */
-#define  CAN_RF1R_FOVR1                      0x00000010U        /*!<FIFO 1 Overrun                */
-#define  CAN_RF1R_RFOM1                      0x00000020U        /*!<Release FIFO 1 Output Mailbox */
-
-/********************  Bit definition for CAN_IER register  *******************/
-#define  CAN_IER_TMEIE                       0x00000001U        /*!<Transmit Mailbox Empty Interrupt Enable */
-#define  CAN_IER_FMPIE0                      0x00000002U        /*!<FIFO Message Pending Interrupt Enable   */
-#define  CAN_IER_FFIE0                       0x00000004U        /*!<FIFO Full Interrupt Enable              */
-#define  CAN_IER_FOVIE0                      0x00000008U        /*!<FIFO Overrun Interrupt Enable           */
-#define  CAN_IER_FMPIE1                      0x00000010U        /*!<FIFO Message Pending Interrupt Enable   */
-#define  CAN_IER_FFIE1                       0x00000020U        /*!<FIFO Full Interrupt Enable              */
-#define  CAN_IER_FOVIE1                      0x00000040U        /*!<FIFO Overrun Interrupt Enable           */
-#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error Warning Interrupt Enable          */
-#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error Passive Interrupt Enable          */
-#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-Off Interrupt Enable                */
-#define  CAN_IER_LECIE                       0x00000800U        /*!<Last Error Code Interrupt Enable        */
-#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error Interrupt Enable                  */
-#define  CAN_IER_WKUIE                       0x00010000U        /*!<Wakeup Interrupt Enable                 */
-#define  CAN_IER_SLKIE                       0x00020000U        /*!<Sleep Interrupt Enable                  */
-
-/********************  Bit definition for CAN_ESR register  *******************/
-#define  CAN_ESR_EWGF                        0x00000001U        /*!<Error Warning Flag */
-#define  CAN_ESR_EPVF                        0x00000002U        /*!<Error Passive Flag */
-#define  CAN_ESR_BOFF                        0x00000004U        /*!<Bus-Off Flag */
-
-#define  CAN_ESR_LEC                         0x00000070U        /*!<LEC[2:0] bits (Last Error Code) */
-#define  CAN_ESR_LEC_0                       0x00000010U        /*!<Bit 0 */
-#define  CAN_ESR_LEC_1                       0x00000020U        /*!<Bit 1 */
-#define  CAN_ESR_LEC_2                       0x00000040U        /*!<Bit 2 */
-
-#define  CAN_ESR_TEC                         0x00FF0000U        /*!<Least significant byte of the 9-bit Transmit Error Counter */
-#define  CAN_ESR_REC                         0xFF000000U        /*!<Receive Error Counter */
-
-/*******************  Bit definition for CAN_BTR register  ********************/
-#define  CAN_BTR_BRP                         0x000003FFU        /*!<Baud Rate Prescaler           */
-#define  CAN_BTR_TS1                         0x000F0000U        /*!<Time Segment 1                */
-#define  CAN_BTR_TS1_0                       0x00010000U        /*!<Bit 0 */
-#define  CAN_BTR_TS1_1                       0x00020000U        /*!<Bit 1 */
-#define  CAN_BTR_TS1_2                       0x00040000U        /*!<Bit 2 */
-#define  CAN_BTR_TS1_3                       0x00080000U        /*!<Bit 3 */
-#define  CAN_BTR_TS2                         0x00700000U        /*!<Time Segment 2                */
-#define  CAN_BTR_TS2_0                       0x00100000U        /*!<Bit 0 */
-#define  CAN_BTR_TS2_1                       0x00200000U        /*!<Bit 1 */
-#define  CAN_BTR_TS2_2                       0x00400000U        /*!<Bit 2 */
-#define  CAN_BTR_SJW                         0x03000000U        /*!<Resynchronization Jump Width  */
-#define  CAN_BTR_SJW_0                       0x01000000U        /*!<Bit 0 */
-#define  CAN_BTR_SJW_1                       0x02000000U        /*!<Bit 1 */
-#define  CAN_BTR_LBKM                        0x40000000U        /*!<Loop Back Mode (Debug)        */
-#define  CAN_BTR_SILM                        0x80000000U        /*!<Silent Mode                   */
-
-/*!<Mailbox registers */
-/******************  Bit definition for CAN_TI0R register  ********************/
-#define  CAN_TI0R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request                   */
-#define  CAN_TI0R_RTR                        0x00000002U        /*!<Remote Transmission Request                */
-#define  CAN_TI0R_IDE                        0x00000004U        /*!<Identifier Extension                       */
-#define  CAN_TI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier                        */
-#define  CAN_TI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/******************  Bit definition for CAN_TDT0R register  *******************/
-#define  CAN_TDT0R_DLC                       0x0000000FU        /*!<Data Length Code     */
-#define  CAN_TDT0R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp   */
-
-/******************  Bit definition for CAN_TDL0R register  *******************/
-#define  CAN_TDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/******************  Bit definition for CAN_TDH0R register  *******************/
-#define  CAN_TDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI1R register  *******************/
-#define  CAN_TI1R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request                   */
-#define  CAN_TI1R_RTR                        0x00000002U        /*!<Remote Transmission Request                */
-#define  CAN_TI1R_IDE                        0x00000004U        /*!<Identifier Extension                       */
-#define  CAN_TI1R_EXID                       0x001FFFF8U        /*!<Extended Identifier                        */
-#define  CAN_TI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT1R register  ******************/
-#define  CAN_TDT1R_DLC                       0x0000000FU        /*!<Data Length Code     */
-#define  CAN_TDT1R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp   */
-
-/*******************  Bit definition for CAN_TDL1R register  ******************/
-#define  CAN_TDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH1R register  ******************/
-#define  CAN_TDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI2R register  *******************/
-#define  CAN_TI2R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request                   */
-#define  CAN_TI2R_RTR                        0x00000002U        /*!<Remote Transmission Request                */
-#define  CAN_TI2R_IDE                        0x00000004U        /*!<Identifier Extension                       */
-#define  CAN_TI2R_EXID                       0x001FFFF8U        /*!<Extended identifier                        */
-#define  CAN_TI2R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT2R register  ******************/
-#define  CAN_TDT2R_DLC                       0x0000000FU        /*!<Data Length Code      */
-#define  CAN_TDT2R_TGT                       0x00000100U        /*!<Transmit Global Time  */
-#define  CAN_TDT2R_TIME                      0xFFFF0000U        /*!<Message Time Stamp    */
-
-/*******************  Bit definition for CAN_TDL2R register  ******************/
-#define  CAN_TDL2R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL2R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL2R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL2R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH2R register  ******************/
-#define  CAN_TDH2R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH2R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH2R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH2R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI0R register  *******************/
-#define  CAN_RI0R_RTR                        0x00000002U        /*!<Remote Transmission Request                */
-#define  CAN_RI0R_IDE                        0x00000004U        /*!<Identifier Extension                       */
-#define  CAN_RI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier                        */
-#define  CAN_RI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT0R register  ******************/
-#define  CAN_RDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_RDT0R_FMI                       0x0000FF00U        /*!<Filter Match Index */
-#define  CAN_RDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL0R register  ******************/
-#define  CAN_RDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_RDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_RDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_RDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH0R register  ******************/
-#define  CAN_RDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_RDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_RDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_RDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI1R register  *******************/
-#define  CAN_RI1R_RTR                        0x00000002U        /*!<Remote Transmission Request                */
-#define  CAN_RI1R_IDE                        0x00000004U        /*!<Identifier Extension                       */
-#define  CAN_RI1R_EXID                       0x001FFFF8U        /*!<Extended identifier                        */
-#define  CAN_RI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT1R register  ******************/
-#define  CAN_RDT1R_DLC                       0x0000000FU        /*!<Data Length Code   */
-#define  CAN_RDT1R_FMI                       0x0000FF00U        /*!<Filter Match Index */
-#define  CAN_RDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL1R register  ******************/
-#define  CAN_RDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_RDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_RDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_RDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH1R register  ******************/
-#define  CAN_RDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_RDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_RDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_RDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*!<CAN filter registers */
-/*******************  Bit definition for CAN_FMR register  ********************/
-#define  CAN_FMR_FINIT                       ((uint8_t)0x01U)               /*!<Filter Init Mode */
-#define  CAN_FMR_CAN2SB                      0x00003F00U        /*!<CAN2 start bank */
-
-/*******************  Bit definition for CAN_FM1R register  *******************/
-#define  CAN_FM1R_FBM                        0x3FFFU            /*!<Filter Mode */
-#define  CAN_FM1R_FBM0                       0x0001U            /*!<Filter Init Mode bit 0  */
-#define  CAN_FM1R_FBM1                       0x0002U            /*!<Filter Init Mode bit 1  */
-#define  CAN_FM1R_FBM2                       0x0004U            /*!<Filter Init Mode bit 2  */
-#define  CAN_FM1R_FBM3                       0x0008U            /*!<Filter Init Mode bit 3  */
-#define  CAN_FM1R_FBM4                       0x0010U            /*!<Filter Init Mode bit 4  */
-#define  CAN_FM1R_FBM5                       0x0020U            /*!<Filter Init Mode bit 5  */
-#define  CAN_FM1R_FBM6                       0x0040U            /*!<Filter Init Mode bit 6  */
-#define  CAN_FM1R_FBM7                       0x0080U            /*!<Filter Init Mode bit 7  */
-#define  CAN_FM1R_FBM8                       0x0100U            /*!<Filter Init Mode bit 8  */
-#define  CAN_FM1R_FBM9                       0x0200U            /*!<Filter Init Mode bit 9  */
-#define  CAN_FM1R_FBM10                      0x0400U            /*!<Filter Init Mode bit 10 */
-#define  CAN_FM1R_FBM11                      0x0800U            /*!<Filter Init Mode bit 11 */
-#define  CAN_FM1R_FBM12                      0x1000U            /*!<Filter Init Mode bit 12 */
-#define  CAN_FM1R_FBM13                      0x2000U            /*!<Filter Init Mode bit 13 */
-
-/*******************  Bit definition for CAN_FS1R register  *******************/
-#define  CAN_FS1R_FSC                        0x00003FFFU        /*!<Filter Scale Configuration        */
-#define  CAN_FS1R_FSC0                       0x00000001U        /*!<Filter Scale Configuration bit 0  */
-#define  CAN_FS1R_FSC1                       0x00000002U        /*!<Filter Scale Configuration bit 1  */
-#define  CAN_FS1R_FSC2                       0x00000004U        /*!<Filter Scale Configuration bit 2  */
-#define  CAN_FS1R_FSC3                       0x00000008U        /*!<Filter Scale Configuration bit 3  */
-#define  CAN_FS1R_FSC4                       0x00000010U        /*!<Filter Scale Configuration bit 4  */
-#define  CAN_FS1R_FSC5                       0x00000020U        /*!<Filter Scale Configuration bit 5  */
-#define  CAN_FS1R_FSC6                       0x00000040U        /*!<Filter Scale Configuration bit 6  */
-#define  CAN_FS1R_FSC7                       0x00000080U        /*!<Filter Scale Configuration bit 7  */
-#define  CAN_FS1R_FSC8                       0x00000100U        /*!<Filter Scale Configuration bit 8  */
-#define  CAN_FS1R_FSC9                       0x00000200U        /*!<Filter Scale Configuration bit 9  */
-#define  CAN_FS1R_FSC10                      0x00000400U        /*!<Filter Scale Configuration bit 10 */
-#define  CAN_FS1R_FSC11                      0x00000800U        /*!<Filter Scale Configuration bit 11 */
-#define  CAN_FS1R_FSC12                      0x00001000U        /*!<Filter Scale Configuration bit 12 */
-#define  CAN_FS1R_FSC13                      0x00002000U        /*!<Filter Scale Configuration bit 13 */
-
-/******************  Bit definition for CAN_FFA1R register  *******************/
-#define  CAN_FFA1R_FFA                       0x00003FFFU        /*!<Filter FIFO Assignment */
-#define  CAN_FFA1R_FFA0                      0x00000001U        /*!<Filter FIFO Assignment for Filter 0 */
-#define  CAN_FFA1R_FFA1                      0x00000002U        /*!<Filter FIFO Assignment for Filter 1 */
-#define  CAN_FFA1R_FFA2                      0x00000004U        /*!<Filter FIFO Assignment for Filter 2 */
-#define  CAN_FFA1R_FFA3                      0x00000008U        /*!<Filter FIFO Assignment for Filter 3 */
-#define  CAN_FFA1R_FFA4                      0x00000010U        /*!<Filter FIFO Assignment for Filter 4 */
-#define  CAN_FFA1R_FFA5                      0x00000020U        /*!<Filter FIFO Assignment for Filter 5 */
-#define  CAN_FFA1R_FFA6                      0x00000040U        /*!<Filter FIFO Assignment for Filter 6 */
-#define  CAN_FFA1R_FFA7                      0x00000080U        /*!<Filter FIFO Assignment for Filter 7 */
-#define  CAN_FFA1R_FFA8                      0x00000100U        /*!<Filter FIFO Assignment for Filter 8 */
-#define  CAN_FFA1R_FFA9                      0x00000200U        /*!<Filter FIFO Assignment for Filter 9 */
-#define  CAN_FFA1R_FFA10                     0x00000400U        /*!<Filter FIFO Assignment for Filter 10 */
-#define  CAN_FFA1R_FFA11                     0x00000800U        /*!<Filter FIFO Assignment for Filter 11 */
-#define  CAN_FFA1R_FFA12                     0x00001000U        /*!<Filter FIFO Assignment for Filter 12 */
-#define  CAN_FFA1R_FFA13                     0x00002000U        /*!<Filter FIFO Assignment for Filter 13 */
-
-/*******************  Bit definition for CAN_FA1R register  *******************/
-#define  CAN_FA1R_FACT                       0x00003FFFU        /*!<Filter Active    */
-#define  CAN_FA1R_FACT0                      0x00000001U        /*!<Filter 0 Active  */
-#define  CAN_FA1R_FACT1                      0x00000002U        /*!<Filter 1 Active  */
-#define  CAN_FA1R_FACT2                      0x00000004U        /*!<Filter 2 Active  */
-#define  CAN_FA1R_FACT3                      0x00000008U        /*!<Filter 3 Active  */
-#define  CAN_FA1R_FACT4                      0x00000010U        /*!<Filter 4 Active  */
-#define  CAN_FA1R_FACT5                      0x00000020U        /*!<Filter 5 Active  */
-#define  CAN_FA1R_FACT6                      0x00000040U        /*!<Filter 6 Active  */
-#define  CAN_FA1R_FACT7                      0x00000080U        /*!<Filter 7 Active  */
-#define  CAN_FA1R_FACT8                      0x00000100U        /*!<Filter 8 Active  */
-#define  CAN_FA1R_FACT9                      0x00000200U        /*!<Filter 9 Active  */
-#define  CAN_FA1R_FACT10                     0x00000400U        /*!<Filter 10 Active */
-#define  CAN_FA1R_FACT11                     0x00000800U        /*!<Filter 11 Active */
-#define  CAN_FA1R_FACT12                     0x00001000U        /*!<Filter 12 Active */
-#define  CAN_FA1R_FACT13                     0x00002000U        /*!<Filter 13 Active */
-
-/*******************  Bit definition for CAN_F0R1 register  *******************/
-#define  CAN_F0R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F0R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F0R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F0R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F0R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F0R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F0R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F0R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F0R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F0R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F0R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F0R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F0R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F0R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F0R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F0R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F0R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F0R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F0R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F0R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F0R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F0R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F0R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F0R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F0R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F0R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F0R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F0R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F0R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F0R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F0R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F0R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R1 register  *******************/
-#define  CAN_F1R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F1R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F1R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F1R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F1R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F1R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F1R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F1R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F1R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F1R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F1R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F1R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F1R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F1R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F1R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F1R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F1R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F1R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F1R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F1R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F1R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F1R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F1R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F1R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F1R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F1R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F1R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F1R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F1R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F1R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F1R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F1R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R1 register  *******************/
-#define  CAN_F2R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F2R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F2R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F2R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F2R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F2R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F2R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F2R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F2R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F2R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F2R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F2R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F2R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F2R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F2R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F2R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F2R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F2R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F2R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F2R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F2R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F2R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F2R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F2R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F2R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F2R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F2R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F2R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F2R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F2R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F2R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F2R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R1 register  *******************/
-#define  CAN_F3R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F3R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F3R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F3R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F3R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F3R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F3R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F3R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F3R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F3R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F3R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F3R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F3R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F3R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F3R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F3R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F3R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F3R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F3R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F3R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F3R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F3R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F3R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F3R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F3R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F3R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F3R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F3R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F3R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F3R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F3R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F3R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R1 register  *******************/
-#define  CAN_F4R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F4R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F4R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F4R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F4R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F4R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F4R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F4R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F4R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F4R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F4R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F4R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F4R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F4R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F4R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F4R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F4R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F4R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F4R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F4R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F4R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F4R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F4R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F4R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F4R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F4R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F4R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F4R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F4R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F4R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F4R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F4R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R1 register  *******************/
-#define  CAN_F5R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F5R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F5R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F5R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F5R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F5R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F5R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F5R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F5R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F5R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F5R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F5R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F5R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F5R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F5R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F5R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F5R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F5R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F5R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F5R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F5R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F5R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F5R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F5R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F5R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F5R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F5R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F5R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F5R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F5R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F5R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F5R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R1 register  *******************/
-#define  CAN_F6R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F6R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F6R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F6R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F6R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F6R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F6R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F6R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F6R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F6R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F6R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F6R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F6R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F6R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F6R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F6R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F6R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F6R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F6R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F6R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F6R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F6R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F6R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F6R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F6R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F6R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F6R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F6R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F6R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F6R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F6R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F6R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R1 register  *******************/
-#define  CAN_F7R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F7R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F7R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F7R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F7R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F7R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F7R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F7R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F7R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F7R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F7R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F7R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F7R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F7R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F7R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F7R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F7R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F7R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F7R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F7R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F7R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F7R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F7R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F7R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F7R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F7R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F7R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F7R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F7R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F7R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F7R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F7R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R1 register  *******************/
-#define  CAN_F8R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F8R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F8R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F8R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F8R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F8R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F8R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F8R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F8R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F8R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F8R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F8R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F8R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F8R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F8R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F8R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F8R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F8R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F8R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F8R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F8R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F8R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F8R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F8R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F8R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F8R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F8R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F8R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F8R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F8R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F8R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F8R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R1 register  *******************/
-#define  CAN_F9R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F9R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F9R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F9R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F9R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F9R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F9R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F9R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F9R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F9R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F9R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F9R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F9R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F9R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F9R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F9R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F9R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F9R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F9R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F9R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F9R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F9R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F9R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F9R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F9R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F9R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F9R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F9R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F9R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F9R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F9R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F9R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R1 register  ******************/
-#define  CAN_F10R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F10R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F10R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F10R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F10R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F10R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F10R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F10R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F10R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F10R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F10R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F10R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F10R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F10R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F10R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F10R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F10R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F10R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F10R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F10R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F10R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F10R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F10R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F10R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F10R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F10R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F10R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F10R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F10R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F10R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F10R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F10R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R1 register  ******************/
-#define  CAN_F11R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F11R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F11R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F11R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F11R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F11R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F11R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F11R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F11R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F11R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F11R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F11R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F11R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F11R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F11R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F11R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F11R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F11R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F11R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F11R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F11R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F11R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F11R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F11R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F11R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F11R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F11R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F11R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F11R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F11R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F11R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F11R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R1 register  ******************/
-#define  CAN_F12R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F12R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F12R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F12R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F12R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F12R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F12R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F12R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F12R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F12R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F12R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F12R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F12R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F12R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F12R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F12R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F12R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F12R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F12R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F12R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F12R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F12R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F12R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F12R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F12R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F12R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F12R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F12R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F12R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F12R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F12R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F12R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R1 register  ******************/
-#define  CAN_F13R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F13R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F13R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F13R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F13R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F13R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F13R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F13R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F13R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F13R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F13R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F13R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F13R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F13R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F13R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F13R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F13R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F13R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F13R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F13R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F13R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F13R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F13R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F13R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F13R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F13R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F13R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F13R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F13R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F13R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F13R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F13R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F0R2 register  *******************/
-#define  CAN_F0R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F0R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F0R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F0R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F0R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F0R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F0R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F0R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F0R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F0R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F0R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F0R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F0R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F0R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F0R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F0R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F0R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F0R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F0R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F0R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F0R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F0R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F0R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F0R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F0R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F0R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F0R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F0R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F0R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F0R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F0R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F0R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R2 register  *******************/
-#define  CAN_F1R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F1R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F1R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F1R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F1R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F1R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F1R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F1R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F1R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F1R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F1R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F1R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F1R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F1R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F1R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F1R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F1R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F1R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F1R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F1R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F1R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F1R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F1R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F1R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F1R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F1R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F1R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F1R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F1R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F1R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F1R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F1R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R2 register  *******************/
-#define  CAN_F2R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F2R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F2R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F2R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F2R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F2R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F2R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F2R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F2R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F2R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F2R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F2R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F2R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F2R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F2R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F2R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F2R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F2R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F2R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F2R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F2R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F2R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F2R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F2R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F2R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F2R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F2R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F2R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F2R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F2R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F2R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F2R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R2 register  *******************/
-#define  CAN_F3R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F3R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F3R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F3R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F3R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F3R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F3R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F3R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F3R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F3R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F3R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F3R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F3R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F3R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F3R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F3R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F3R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F3R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F3R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F3R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F3R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F3R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F3R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F3R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F3R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F3R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F3R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F3R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F3R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F3R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F3R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F3R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R2 register  *******************/
-#define  CAN_F4R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F4R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F4R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F4R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F4R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F4R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F4R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F4R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F4R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F4R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F4R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F4R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F4R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F4R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F4R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F4R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F4R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F4R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F4R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F4R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F4R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F4R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F4R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F4R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F4R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F4R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F4R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F4R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F4R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F4R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F4R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F4R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R2 register  *******************/
-#define  CAN_F5R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F5R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F5R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F5R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F5R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F5R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F5R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F5R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F5R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F5R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F5R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F5R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F5R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F5R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F5R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F5R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F5R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F5R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F5R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F5R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F5R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F5R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F5R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F5R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F5R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F5R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F5R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F5R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F5R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F5R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F5R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F5R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R2 register  *******************/
-#define  CAN_F6R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F6R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F6R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F6R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F6R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F6R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F6R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F6R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F6R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F6R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F6R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F6R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F6R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F6R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F6R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F6R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F6R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F6R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F6R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F6R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F6R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F6R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F6R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F6R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F6R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F6R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F6R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F6R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F6R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F6R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F6R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F6R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R2 register  *******************/
-#define  CAN_F7R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F7R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F7R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F7R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F7R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F7R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F7R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F7R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F7R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F7R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F7R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F7R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F7R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F7R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F7R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F7R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F7R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F7R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F7R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F7R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F7R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F7R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F7R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F7R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F7R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F7R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F7R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F7R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F7R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F7R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F7R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F7R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R2 register  *******************/
-#define  CAN_F8R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F8R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F8R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F8R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F8R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F8R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F8R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F8R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F8R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F8R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F8R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F8R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F8R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F8R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F8R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F8R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F8R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F8R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F8R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F8R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F8R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F8R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F8R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F8R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F8R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F8R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F8R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F8R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F8R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F8R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F8R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F8R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R2 register  *******************/
-#define  CAN_F9R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F9R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F9R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F9R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F9R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F9R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F9R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F9R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F9R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F9R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F9R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F9R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F9R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F9R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F9R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F9R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F9R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F9R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F9R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F9R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F9R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F9R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F9R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F9R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F9R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F9R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F9R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F9R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F9R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F9R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F9R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F9R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R2 register  ******************/
-#define  CAN_F10R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F10R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F10R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F10R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F10R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F10R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F10R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F10R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F10R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F10R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F10R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F10R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F10R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F10R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F10R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F10R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F10R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F10R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F10R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F10R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F10R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F10R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F10R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F10R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F10R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F10R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F10R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F10R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F10R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F10R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F10R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F10R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R2 register  ******************/
-#define  CAN_F11R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F11R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F11R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F11R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F11R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F11R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F11R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F11R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F11R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F11R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F11R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F11R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F11R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F11R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F11R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F11R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F11R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F11R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F11R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F11R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F11R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F11R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F11R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F11R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F11R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F11R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F11R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F11R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F11R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F11R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F11R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F11R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R2 register  ******************/
-#define  CAN_F12R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F12R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F12R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F12R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F12R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F12R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F12R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F12R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F12R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F12R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F12R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F12R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F12R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F12R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F12R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F12R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F12R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F12R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F12R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F12R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F12R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F12R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F12R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F12R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F12R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F12R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F12R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F12R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F12R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F12R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F12R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F12R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R2 register  ******************/
-#define  CAN_F13R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F13R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F13R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F13R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F13R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F13R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F13R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F13R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F13R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F13R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F13R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F13R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F13R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F13R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F13R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F13R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F13R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F13R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F13R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F13R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F13R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F13R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F13R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F13R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F13R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F13R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F13R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F13R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F13R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F13R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F13R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F13R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 HDMI-CEC (CEC)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CEC_CR register  *********************/
-#define  CEC_CR_CECEN                        0x00000001U       /*!< CEC Enable                         */
-#define  CEC_CR_TXSOM                        0x00000002U       /*!< CEC Tx Start Of Message            */
-#define  CEC_CR_TXEOM                        0x00000004U       /*!< CEC Tx End Of Message              */
-
-/*******************  Bit definition for CEC_CFGR register  *******************/
-#define  CEC_CFGR_SFT                        0x00000007U       /*!< CEC Signal Free Time               */
-#define  CEC_CFGR_RXTOL                      0x00000008U       /*!< CEC Tolerance                      */
-#define  CEC_CFGR_BRESTP                     0x00000010U       /*!< CEC Rx Stop                        */
-#define  CEC_CFGR_BREGEN                     0x00000020U       /*!< CEC Bit Rising Error generation    */
-#define  CEC_CFGR_LBPEGEN                    0x00000040U       /*!< CEC Long Period Error generation   */
-#define  CEC_CFGR_BRDNOGEN                   0x00000080U       /*!< CEC Broadcast no Error generation  */
-#define  CEC_CFGR_SFTOPT                     0x00000100U       /*!< CEC Signal Free Time optional      */
-#define  CEC_CFGR_OAR                        0x7FFF0000U       /*!< CEC Own Address                    */
-#define  CEC_CFGR_LSTN                       0x80000000U       /*!< CEC Listen mode                    */
-
-/*******************  Bit definition for CEC_TXDR register  *******************/
-#define  CEC_TXDR_TXD                        0x000000FFU       /*!< CEC Tx Data                        */
-
-/*******************  Bit definition for CEC_RXDR register  *******************/
-#define  CEC_TXDR_RXD                        0x000000FFU       /*!< CEC Rx Data                        */
-
-/*******************  Bit definition for CEC_ISR register  ********************/
-#define  CEC_ISR_RXBR                        0x00000001U       /*!< CEC Rx-Byte Received                   */
-#define  CEC_ISR_RXEND                       0x00000002U       /*!< CEC End Of Reception                   */
-#define  CEC_ISR_RXOVR                       0x00000004U       /*!< CEC Rx-Overrun                         */
-#define  CEC_ISR_BRE                         0x00000008U       /*!< CEC Rx Bit Rising Error                */
-#define  CEC_ISR_SBPE                        0x00000010U       /*!< CEC Rx Short Bit period Error          */
-#define  CEC_ISR_LBPE                        0x00000020U       /*!< CEC Rx Long Bit period Error           */
-#define  CEC_ISR_RXACKE                      0x00000040U       /*!< CEC Rx Missing Acknowledge             */
-#define  CEC_ISR_ARBLST                      0x00000080U       /*!< CEC Arbitration Lost                   */
-#define  CEC_ISR_TXBR                        0x00000100U       /*!< CEC Tx Byte Request                    */
-#define  CEC_ISR_TXEND                       0x00000200U       /*!< CEC End of Transmission                */
-#define  CEC_ISR_TXUDR                       0x00000400U       /*!< CEC Tx-Buffer Underrun                 */
-#define  CEC_ISR_TXERR                       0x00000800U       /*!< CEC Tx-Error                           */
-#define  CEC_ISR_TXACKE                      0x00001000U       /*!< CEC Tx Missing Acknowledge             */
-
-/*******************  Bit definition for CEC_IER register  ********************/
-#define  CEC_IER_RXBRIE                      0x00000001U       /*!< CEC Rx-Byte Received IT Enable         */
-#define  CEC_IER_RXENDIE                     0x00000002U       /*!< CEC End Of Reception IT Enable         */
-#define  CEC_IER_RXOVRIE                     0x00000004U       /*!< CEC Rx-Overrun IT Enable               */
-#define  CEC_IER_BREIE                       0x00000008U       /*!< CEC Rx Bit Rising Error IT Enable      */
-#define  CEC_IER_SBPEIE                      0x00000010U       /*!< CEC Rx Short Bit period Error IT Enable*/
-#define  CEC_IER_LBPEIE                      0x00000020U       /*!< CEC Rx Long Bit period Error IT Enable */
-#define  CEC_IER_RXACKEIE                    0x00000040U       /*!< CEC Rx Missing Acknowledge IT Enable   */
-#define  CEC_IER_ARBLSTIE                    0x00000080U       /*!< CEC Arbitration Lost IT Enable         */
-#define  CEC_IER_TXBRIE                      0x00000100U       /*!< CEC Tx Byte Request  IT Enable         */
-#define  CEC_IER_TXENDIE                     0x00000200U       /*!< CEC End of Transmission IT Enable      */
-#define  CEC_IER_TXUDRIE                     0x00000400U       /*!< CEC Tx-Buffer Underrun IT Enable       */
-#define  CEC_IER_TXERRIE                     0x00000800U       /*!< CEC Tx-Error IT Enable                 */
-#define  CEC_IER_TXACKEIE                    0x00001000U       /*!< CEC Tx Missing Acknowledge IT Enable   */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRC calculation unit                              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           0xFFFFFFFFU     /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         0x000000FFU     /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        0x00000001U     /*!< RESET the CRC computation unit bit */
-#define  CRC_CR_POLYSIZE                     0x00000018U     /*!< Polynomial size bits               */
-#define  CRC_CR_POLYSIZE_0                   0x00000008U     /*!< Polynomial size bit 0              */
-#define  CRC_CR_POLYSIZE_1                   0x00000010U     /*!< Polynomial size bit 1              */
-#define  CRC_CR_REV_IN                       0x00000060U     /*!< REV_IN Reverse Input Data bits     */
-#define  CRC_CR_REV_IN_0                     0x00000020U     /*!< Bit 0 */
-#define  CRC_CR_REV_IN_1                     0x00000040U     /*!< Bit 1 */
-#define  CRC_CR_REV_OUT                      0x00000080U     /*!< REV_OUT Reverse Output Data bits   */
-
-/*******************  Bit definition for CRC_INIT register  *******************/
-#define  CRC_INIT_INIT                       0xFFFFFFFFU     /*!< Initial CRC value bits         */
-
-/*******************  Bit definition for CRC_POL register  ********************/
-#define  CRC_POL_POL                         0xFFFFFFFFU     /*!< Coefficients of the polynomial */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Digital to Analog Converter                           */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DAC_CR register  ********************/
-#define  DAC_CR_EN1                          0x00000001U        /*!<DAC channel1 enable                         */
-#define  DAC_CR_BOFF1                        0x00000002U        /*!<DAC channel1 output buffer disable          */
-#define  DAC_CR_TEN1                         0x00000004U        /*!<DAC channel1 Trigger enable                 */
-#define  DAC_CR_TSEL1                        0x00000038U        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define  DAC_CR_TSEL1_0                      0x00000008U        /*!<Bit 0 */
-#define  DAC_CR_TSEL1_1                      0x00000010U        /*!<Bit 1 */
-#define  DAC_CR_TSEL1_2                      0x00000020U        /*!<Bit 2 */
-#define  DAC_CR_WAVE1                        0x000000C0U        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enablEU) */
-#define  DAC_CR_WAVE1_0                      0x00000040U        /*!<Bit 0 */
-#define  DAC_CR_WAVE1_1                      0x00000080U        /*!<Bit 1 */
-#define  DAC_CR_MAMP1                        0x00000F00U        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP1_0                      0x00000100U        /*!<Bit 0 */
-#define  DAC_CR_MAMP1_1                      0x00000200U        /*!<Bit 1 */
-#define  DAC_CR_MAMP1_2                      0x00000400U        /*!<Bit 2 */
-#define  DAC_CR_MAMP1_3                      0x00000800U        /*!<Bit 3 */
-#define  DAC_CR_DMAEN1                       0x00001000U        /*!<DAC channel1 DMA enable                     */
-#define  DAC_CR_DMAUDRIE1                    0x00002000U        /*!<DAC channel1 DMA underrun interrupt enable  */
-#define  DAC_CR_EN2                          0x00010000U        /*!<DAC channel2 enable                         */
-#define  DAC_CR_BOFF2                        0x00020000U        /*!<DAC channel2 output buffer disable          */
-#define  DAC_CR_TEN2                         0x00040000U        /*!<DAC channel2 Trigger enable                 */
-#define  DAC_CR_TSEL2                        0x00380000U        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define  DAC_CR_TSEL2_0                      0x00080000U        /*!<Bit 0 */
-#define  DAC_CR_TSEL2_1                      0x00100000U        /*!<Bit 1 */
-#define  DAC_CR_TSEL2_2                      0x00200000U        /*!<Bit 2 */
-#define  DAC_CR_WAVE2                        0x00C00000U        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE2_0                      0x00400000U        /*!<Bit 0 */
-#define  DAC_CR_WAVE2_1                      0x00800000U        /*!<Bit 1 */
-#define  DAC_CR_MAMP2                        0x0F000000U        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP2_0                      0x01000000U        /*!<Bit 0 */
-#define  DAC_CR_MAMP2_1                      0x02000000U        /*!<Bit 1 */
-#define  DAC_CR_MAMP2_2                      0x04000000U        /*!<Bit 2 */
-#define  DAC_CR_MAMP2_3                      0x08000000U        /*!<Bit 3 */
-#define  DAC_CR_DMAEN2                       0x10000000U        /*!<DAC channel2 DMA enable                    */
-#define  DAC_CR_DMAUDRIE2                    0x20000000U        /*!<DAC channel2 DMA underrun interrupt enable */
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define  DAC_SWTRIGR_SWTRIG1                 0x01U               /*!<DAC channel1 software trigger */
-#define  DAC_SWTRIGR_SWTRIG2                 0x02U               /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define  DAC_DHR12R1_DACC1DHR                0x0FFFU            /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define  DAC_DHR12L1_DACC1DHR                0xFFF0U            /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define  DAC_DHR8R1_DACC1DHR                 0xFFU               /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define  DAC_DHR12R2_DACC2DHR                0x0FFFU            /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define  DAC_DHR12L2_DACC2DHR                0xFFF0U            /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define  DAC_DHR8R2_DACC2DHR                 0xFFU               /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define  DAC_DHR12RD_DACC1DHR                0x00000FFFU        /*!<DAC channel1 12-bit Right aligned data */
-#define  DAC_DHR12RD_DACC2DHR                0x0FFF0000U        /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define  DAC_DHR12LD_DACC1DHR                0x0000FFF0U        /*!<DAC channel1 12-bit Left aligned data */
-#define  DAC_DHR12LD_DACC2DHR                0xFFF00000U        /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define  DAC_DHR8RD_DACC1DHR                 0x00FFU            /*!<DAC channel1 8-bit Right aligned data */
-#define  DAC_DHR8RD_DACC2DHR                 0xFF00U            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define  DAC_DOR1_DACC1DOR                   0x0FFFU            /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define  DAC_DOR2_DACC2DOR                   0x0FFFU            /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define  DAC_SR_DMAUDR1                      0x00002000U        /*!<DAC channel1 DMA underrun flag */
-#define  DAC_SR_DMAUDR2                      0x20000000U        /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                 Digital Filter for Sigma Delta Modulators                  */
-/*                                                                            */
-/******************************************************************************/
-
-/****************   DFSDM channel configuration registers  ********************/
-
-/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/
-#define  DFSDM_CHCFGR1_DFSDMEN                0x80000000U            /*!< Global enable for DFSDM interface */
-#define  DFSDM_CHCFGR1_CKOUTSRC               0x40000000U            /*!< Output serial clock source selection */
-#define  DFSDM_CHCFGR1_CKOUTDIV               0x00FF0000U            /*!< CKOUTDIV[7:0] output serial clock divider */
-#define  DFSDM_CHCFGR1_DATPACK                0x0000C000U            /*!< DATPACK[1:0] Data packing mode */
-#define  DFSDM_CHCFGR1_DATPACK_1              0x00008000U            /*!< Data packing mode, Bit 1 */
-#define  DFSDM_CHCFGR1_DATPACK_0              0x00004000U            /*!< Data packing mode, Bit 0 */
-#define  DFSDM_CHCFGR1_DATMPX                 0x00003000U            /*!< DATMPX[1:0] Input data multiplexer for channel y */
-#define  DFSDM_CHCFGR1_DATMPX_1               0x00002000U            /*!< Input data multiplexer for channel y, Bit 1 */
-#define  DFSDM_CHCFGR1_DATMPX_0               0x00001000U            /*!< Input data multiplexer for channel y, Bit 0 */
-#define  DFSDM_CHCFGR1_CHINSEL                0x00000100U            /*!< Serial inputs selection for channel y */
-#define  DFSDM_CHCFGR1_CHEN                   0x00000080U            /*!< Channel y enable */
-#define  DFSDM_CHCFGR1_CKABEN                 0x00000040U            /*!< Clock absence detector enable on channel y */
-#define  DFSDM_CHCFGR1_SCDEN                  0x00000020U            /*!< Short circuit detector enable on channel y */
-#define  DFSDM_CHCFGR1_SPICKSEL               0x0000000CU            /*!< SPICKSEL[1:0] SPI clock select for channel y */
-#define  DFSDM_CHCFGR1_SPICKSEL_1             0x00000008U            /*!< SPI clock select for channel y, Bit 1 */
-#define  DFSDM_CHCFGR1_SPICKSEL_0             0x00000004U            /*!< SPI clock select for channel y, Bit 0 */
-#define  DFSDM_CHCFGR1_SITP                   0x00000003U            /*!< SITP[1:0] Serial interface type for channel y */
-#define  DFSDM_CHCFGR1_SITP_1                 0x00000002U            /*!< Serial interface type for channel y, Bit 1 */
-#define  DFSDM_CHCFGR1_SITP_0                 0x00000001U            /*!< Serial interface type for channel y, Bit 0 */
-
-/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/
-#define  DFSDM_CHCFGR2_OFFSET                 0xFFFFFF00U            /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
-#define  DFSDM_CHCFGR2_DTRBS                  0x000000F8U            /*!< DTRBS[4:0] Data right bit-shift for channel y */
-
-/******************  Bit definition for DFSDM_CHAWSCDR register *****************/
-#define  DFSDM_CHAWSCDR_AWFORD                0x00C00000U            /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
-#define  DFSDM_CHAWSCDR_AWFORD_1              0x00800000U            /*!< Analog watchdog Sinc filter order on channel y, Bit 1 */
-#define  DFSDM_CHAWSCDR_AWFORD_0              0x00400000U            /*!< Analog watchdog Sinc filter order on channel y, Bit 0 */
-#define  DFSDM_CHAWSCDR_AWFOSR                0x001F0000U            /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
-#define  DFSDM_CHAWSCDR_BKSCD                 0x0000F000U            /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
-#define  DFSDM_CHAWSCDR_SCDT                  0x000000FFU            /*!< SCDT[7:0] Short circuit detector threshold for channel y */
-
-/****************  Bit definition for DFSDM_CHWDATR register *******************/
-#define  DFSDM_CHWDATR_WDATA                  0x0000FFFFU            /*!< WDATA[15:0] Input channel y watchdog data */
-
-/****************  Bit definition for DFSDM_CHDATINR register *****************/
-#define  DFSDM_CHDATINR_INDAT0                0x0000FFFFU            /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
-#define  DFSDM_CHDATINR_INDAT1                0xFFFF0000U            /*!< INDAT0[15:0] Input data for channel y */
-
-/************************   DFSDM module registers  ****************************/
-
-/********************  Bit definition for DFSDM_FLTCR1 register *******************/
-#define  DFSDM_FLTCR1_AWFSEL                  0x40000000U            /*!< Analog watchdog fast mode select */
-#define  DFSDM_FLTCR1_FAST                    0x20000000U            /*!< Fast conversion mode selection */
-#define  DFSDM_FLTCR1_RCH                     0x07000000U            /*!< RCH[2:0] Regular channel selection */
-#define  DFSDM_FLTCR1_RDMAEN                  0x00200000U            /*!< DMA channel enabled to read data for the regular conversion */
-#define  DFSDM_FLTCR1_RSYNC                   0x00080000U            /*!< Launch regular conversion synchronously with DFSDMx */
-#define  DFSDM_FLTCR1_RCONT                   0x00040000U            /*!< Continuous mode selection for regular conversions */
-#define  DFSDM_FLTCR1_RSWSTART                0x00020000U            /*!< Software start of a conversion on the regular channel */
-#define  DFSDM_FLTCR1_JEXTEN                  0x00006000U            /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
-#define  DFSDM_FLTCR1_JEXTEN_1                0x00004000U            /*!< Trigger enable and trigger edge selection for injected conversions, Bit 1 */
-#define  DFSDM_FLTCR1_JEXTEN_0                0x00002000U            /*!< Trigger enable and trigger edge selection for injected conversions, Bit 0 */
-#define  DFSDM_FLTCR1_JEXTSEL                 0x00001F00U            /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */
-#define  DFSDM_FLTCR1_JEXTSEL_0               0x00000100U            /*!< Trigger signal selection for launching injected conversions, Bit 0 */
-#define  DFSDM_FLTCR1_JEXTSEL_1               0x00000200U            /*!< Trigger signal selection for launching injected conversions, Bit 1 */
-#define  DFSDM_FLTCR1_JEXTSEL_2               0x00000400U            /*!< Trigger signal selection for launching injected conversions, Bit 2 */
-#define  DFSDM_FLTCR1_JEXTSEL_3               0x00000800U            /*!< Trigger signal selection for launching injected conversions, Bit 3 */
-#define  DFSDM_FLTCR1_JEXTSEL_4               0x00001000U            /*!< Trigger signal selection for launching injected conversions, Bit 4 */
-#define  DFSDM_FLTCR1_JDMAEN                  0x00000020U            /*!< DMA channel enabled to read data for the injected channel group */
-#define  DFSDM_FLTCR1_JSCAN                   0x00000010U            /*!< Scanning conversion in continuous mode selection for injected conversions */
-#define  DFSDM_FLTCR1_JSYNC                   0x00000008U            /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */
-#define  DFSDM_FLTCR1_JSWSTART                0x00000002U            /*!< Start the conversion of the injected group of channels */
-#define  DFSDM_FLTCR1_DFEN                    0x00000001U            /*!< DFSDM enable */
-
-/********************  Bit definition for DFSDM_FLTCR2 register *******************/
-#define  DFSDM_FLTCR2_AWDCH                   0x00FF0000U            /*!< AWDCH[7:0] Analog watchdog channel selection */
-#define  DFSDM_FLTCR2_EXCH                    0x0000FF00U            /*!< EXCH[7:0] Extreme detector channel selection */
-#define  DFSDM_FLTCR2_CKABIE                  0x00000040U            /*!< Clock absence interrupt enable */
-#define  DFSDM_FLTCR2_SCDIE                   0x00000020U            /*!< Short circuit detector interrupt enable */
-#define  DFSDM_FLTCR2_AWDIE                   0x00000010U            /*!< Analog watchdog interrupt enable */
-#define  DFSDM_FLTCR2_ROVRIE                  0x00000008U            /*!< Regular data overrun interrupt enable */
-#define  DFSDM_FLTCR2_JOVRIE                  0x00000004U            /*!< Injected data overrun interrupt enable */
-#define  DFSDM_FLTCR2_REOCIE                  0x00000002U            /*!< Regular end of conversion interrupt enable */
-#define  DFSDM_FLTCR2_JEOCIE                  0x00000001U            /*!< Injected end of conversion interrupt enable */
-
-/********************  Bit definition for DFSDM_FLTISR register *******************/
-#define  DFSDM_FLTISR_SCDF                    0xFF000000U            /*!< SCDF[7:0] Short circuit detector flag */
-#define  DFSDM_FLTISR_CKABF                   0x00FF0000U            /*!< CKABF[7:0] Clock absence flag */
-#define  DFSDM_FLTISR_RCIP                    0x00004000U            /*!< Regular conversion in progress status */
-#define  DFSDM_FLTISR_JCIP                    0x00002000U            /*!< Injected conversion in progress status */
-#define  DFSDM_FLTISR_AWDF                    0x00000010U            /*!< Analog watchdog */
-#define  DFSDM_FLTISR_ROVRF                   0x00000008U            /*!< Regular conversion overrun flag */
-#define  DFSDM_FLTISR_JOVRF                   0x00000004U            /*!< Injected conversion overrun flag */
-#define  DFSDM_FLTISR_REOCF                   0x00000002U            /*!< End of regular conversion flag */
-#define  DFSDM_FLTISR_JEOCF                   0x00000001U            /*!< End of injected conversion flag */
-
-/********************  Bit definition for DFSDM_FLTICR register *******************/
-#define  DFSDM_FLTICR_CLRSCSDF                0xFF000000U            /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
-#define  DFSDM_FLTICR_CLRCKABF                0x00FF0000U            /*!< CLRCKABF[7:0] Clear the clock absence flag */
-#define  DFSDM_FLTICR_CLRROVRF                0x00000008U            /*!< Clear the regular conversion overrun flag */
-#define  DFSDM_FLTICR_CLRJOVRF                0x00000004U            /*!< Clear the injected conversion overrun flag */
-
-/*******************  Bit definition for DFSDM_FLTJCHGR register ******************/
-#define  DFSDM_FLTJCHGR_JCHG                  0x000000FFU            /*!< JCHG[7:0] Injected channel group selection */
-
-/********************  Bit definition for DFSDM_FLTFCR register *******************/
-#define  DFSDM_FLTFCR_FORD                    0xE0000000U            /*!< FORD[2:0] Sinc filter order */
-#define  DFSDM_FLTFCR_FORD_2                  0x80000000U            /*!< Sinc filter order, Bit 2 */
-#define  DFSDM_FLTFCR_FORD_1                  0x40000000U            /*!< Sinc filter order, Bit 1 */
-#define  DFSDM_FLTFCR_FORD_0                  0x20000000U            /*!< Sinc filter order, Bit 0 */
-#define  DFSDM_FLTFCR_FOSR                    0x03FF0000U            /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
-#define  DFSDM_FLTFCR_IOSR                    0x000000FFU            /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
-
-/******************  Bit definition for DFSDM_FLTJDATAR register *****************/
-#define  DFSDM_FLTJDATAR_JDATA                0xFFFFFF00U            /*!< JDATA[23:0] Injected group conversion data */
-#define  DFSDM_FLTJDATAR_JDATACH              0x00000007U            /*!< JDATACH[2:0] Injected channel most recently converted */
-
-/******************  Bit definition for DFSDM_FLTRDATAR register *****************/
-#define  DFSDM_FLTRDATAR_RDATA                0xFFFFFF00U            /*!< RDATA[23:0] Regular channel conversion data */
-#define  DFSDM_FLTRDATAR_RPEND                0x00000010U            /*!< RPEND Regular channel pending data */
-#define  DFSDM_FLTRDATAR_RDATACH              0x00000007U            /*!< RDATACH[2:0] Regular channel most recently converted */
-
-/******************  Bit definition for DFSDM_FLTAWHTR register ******************/
-#define  DFSDM_FLTAWHTR_AWHT                  0xFFFFFF00U             /*!< AWHT[23:0] Analog watchdog high threshold */
-#define  DFSDM_FLTAWHTR_BKAWH                 0x0000000FU             /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
-
-/******************  Bit definition for DFSDM_FLTAWLTR register ******************/
-#define  DFSDM_FLTAWLTR_AWLT                  0xFFFFFF00U             /*!< AWLT[23:0] Analog watchdog low threshold */
-#define  DFSDM_FLTAWLTR_BKAWL                 0x0000000FU             /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
-
-/******************  Bit definition for DFSDM_FLTAWSR register ******************/
-#define  DFSDM_FLTAWSR_AWHTF                  0x0000FF00U             /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
-#define  DFSDM_FLTAWSR_AWLTF                  0x000000FFU             /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
-
-/******************  Bit definition for DFSDM_FLTAWCFR register *****************/
-#define  DFSDM_FLTAWCFR_CLRAWHTF              0x0000FF00U             /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
-#define  DFSDM_FLTAWCFR_CLRAWLTF              0x000000FFU             /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
-
-/******************  Bit definition for DFSDM_FLTEXMAX register ******************/
-#define  DFSDM_FLTEXMAX_EXMAX                 0xFFFFFF00U             /*!< EXMAX[23:0] Extreme detector maximum value */
-#define  DFSDM_FLTEXMAX_EXMAXCH               0x00000007U             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
-
-/******************  Bit definition for DFSDM_FLTEXMIN register ******************/
-#define  DFSDM_FLTEXMIN_EXMIN                 0xFFFFFF00U             /*!< EXMIN[23:0] Extreme detector minimum value */
-#define  DFSDM_FLTEXMIN_EXMINCH               0x00000007U             /*!< EXMINCH[2:0] Extreme detector minimum data channel */
-
-/******************  Bit definition for DFSDM_FLTCNVTIMR register ******************/
-#define  DFSDM_FLTCNVTIMR_CNVCNT              0xFFFFFFF0U             /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 Debug MCU                                  */
-/*                                                                            */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    DCMI                                    */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DCMI_CR register  ******************/
-#define DCMI_CR_CAPTURE                      0x00000001U
-#define DCMI_CR_CM                           0x00000002U
-#define DCMI_CR_CROP                         0x00000004U
-#define DCMI_CR_JPEG                         0x00000008U
-#define DCMI_CR_ESS                          0x00000010U
-#define DCMI_CR_PCKPOL                       0x00000020U
-#define DCMI_CR_HSPOL                        0x00000040U
-#define DCMI_CR_VSPOL                        0x00000080U
-#define DCMI_CR_FCRC_0                       0x00000100U
-#define DCMI_CR_FCRC_1                       0x00000200U
-#define DCMI_CR_EDM_0                        0x00000400U
-#define DCMI_CR_EDM_1                        0x00000800U
-#define DCMI_CR_CRE                          0x00001000U
-#define DCMI_CR_ENABLE                       0x00004000U
-#define DCMI_CR_BSM                          0x00030000U
-#define DCMI_CR_BSM_0                        0x00010000U
-#define DCMI_CR_BSM_1                        0x00020000U
-#define DCMI_CR_OEBS                         0x00040000U
-#define DCMI_CR_LSM                          0x00080000U
-#define DCMI_CR_OELS                         0x00100000U
-
-/********************  Bits definition for DCMI_SR register  ******************/
-#define DCMI_SR_HSYNC                        0x00000001U
-#define DCMI_SR_VSYNC                        0x00000002U
-#define DCMI_SR_FNE                          0x00000004U
-
-/********************  Bits definition for DCMI_RIS register   ****************/
-#define DCMI_RIS_FRAME_RIS                   0x00000001U
-#define DCMI_RIS_OVR_RIS                     0x00000002U
-#define DCMI_RIS_ERR_RIS                     0x00000004U
-#define DCMI_RIS_VSYNC_RIS                   0x00000008U
-#define DCMI_RIS_LINE_RIS                    0x00000010U
-
-/* Legacy defines */
-#define DCMI_RISR_FRAME_RIS                  DCMI_RIS_FRAME_RIS
-#define DCMI_RISR_OVF_RIS                    DCMI_RIS_OVR_RIS
-#define DCMI_RISR_ERR_RIS                    DCMI_RIS_ERR_RIS
-#define DCMI_RISR_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS
-#define DCMI_RISR_LINE_RIS                   DCMI_RIS_LINE_RIS
-
-/********************  Bits definition for DCMI_IER register  *****************/
-#define DCMI_IER_FRAME_IE                    0x00000001U
-#define DCMI_IER_OVR_IE                      0x00000002U
-#define DCMI_IER_ERR_IE                      0x00000004U
-#define DCMI_IER_VSYNC_IE                    0x00000008U
-#define DCMI_IER_LINE_IE                     0x00000010U
-
-
-/********************  Bits definition for DCMI_MIS register  *****************/
-#define DCMI_MIS_FRAME_MIS                   0x00000001U
-#define DCMI_MIS_OVR_MIS                     0x00000002U
-#define DCMI_MIS_ERR_MIS                     0x00000004U
-#define DCMI_MIS_VSYNC_MIS                   0x00000008U
-#define DCMI_MIS_LINE_MIS                    0x00000010U
-
-
-/********************  Bits definition for DCMI_ICR register  *****************/
-#define DCMI_ICR_FRAME_ISC                   0x00000001U
-#define DCMI_ICR_OVR_ISC                     0x00000002U
-#define DCMI_ICR_ERR_ISC                     0x00000004U
-#define DCMI_ICR_VSYNC_ISC                   0x00000008U
-#define DCMI_ICR_LINE_ISC                    0x00000010U
-
-
-/********************  Bits definition for DCMI_ESCR register  ******************/
-#define DCMI_ESCR_FSC                        0x000000FFU
-#define DCMI_ESCR_LSC                        0x0000FF00U
-#define DCMI_ESCR_LEC                        0x00FF0000U
-#define DCMI_ESCR_FEC                        0xFF000000U
-
-/********************  Bits definition for DCMI_ESUR register  ******************/
-#define DCMI_ESUR_FSU                        0x000000FFU
-#define DCMI_ESUR_LSU                        0x0000FF00U
-#define DCMI_ESUR_LEU                        0x00FF0000U
-#define DCMI_ESUR_FEU                        0xFF000000U
-
-/********************  Bits definition for DCMI_CWSTRT register  ******************/
-#define DCMI_CWSTRT_HOFFCNT                  0x00003FFFU
-#define DCMI_CWSTRT_VST                      0x1FFF0000U
-
-/********************  Bits definition for DCMI_CWSIZE register  ******************/
-#define DCMI_CWSIZE_CAPCNT                   0x00003FFFU
-#define DCMI_CWSIZE_VLINE                    0x3FFF0000U
-
-/********************  Bits definition for DCMI_DR register  ******************/
-#define DCMI_DR_BYTE0                        0x000000FFU
-#define DCMI_DR_BYTE1                        0x0000FF00U
-#define DCMI_DR_BYTE2                        0x00FF0000U
-#define DCMI_DR_BYTE3                        0xFF000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                             DMA Controller                                 */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DMA_SxCR register  *****************/
-#define DMA_SxCR_CHSEL                       0x1E000000U
-#define DMA_SxCR_CHSEL_0                     0x02000000U
-#define DMA_SxCR_CHSEL_1                     0x04000000U
-#define DMA_SxCR_CHSEL_2                     0x08000000U
-#define DMA_SxCR_CHSEL_3                     0x10000000U
-#define DMA_SxCR_MBURST                      0x01800000U
-#define DMA_SxCR_MBURST_0                    0x00800000U
-#define DMA_SxCR_MBURST_1                    0x01000000U
-#define DMA_SxCR_PBURST                      0x00600000U
-#define DMA_SxCR_PBURST_0                    0x00200000U
-#define DMA_SxCR_PBURST_1                    0x00400000U
-#define DMA_SxCR_CT                          0x00080000U
-#define DMA_SxCR_DBM                         0x00040000U
-#define DMA_SxCR_PL                          0x00030000U
-#define DMA_SxCR_PL_0                        0x00010000U
-#define DMA_SxCR_PL_1                        0x00020000U
-#define DMA_SxCR_PINCOS                      0x00008000U
-#define DMA_SxCR_MSIZE                       0x00006000U
-#define DMA_SxCR_MSIZE_0                     0x00002000U
-#define DMA_SxCR_MSIZE_1                     0x00004000U
-#define DMA_SxCR_PSIZE                       0x00001800U
-#define DMA_SxCR_PSIZE_0                     0x00000800U
-#define DMA_SxCR_PSIZE_1                     0x00001000U
-#define DMA_SxCR_MINC                        0x00000400U
-#define DMA_SxCR_PINC                        0x00000200U
-#define DMA_SxCR_CIRC                        0x00000100U
-#define DMA_SxCR_DIR                         0x000000C0U
-#define DMA_SxCR_DIR_0                       0x00000040U
-#define DMA_SxCR_DIR_1                       0x00000080U
-#define DMA_SxCR_PFCTRL                      0x00000020U
-#define DMA_SxCR_TCIE                        0x00000010U
-#define DMA_SxCR_HTIE                        0x00000008U
-#define DMA_SxCR_TEIE                        0x00000004U
-#define DMA_SxCR_DMEIE                       0x00000002U
-#define DMA_SxCR_EN                          0x00000001U
-
-/********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            0x0000FFFFU
-#define DMA_SxNDT_0                          0x00000001U
-#define DMA_SxNDT_1                          0x00000002U
-#define DMA_SxNDT_2                          0x00000004U
-#define DMA_SxNDT_3                          0x00000008U
-#define DMA_SxNDT_4                          0x00000010U
-#define DMA_SxNDT_5                          0x00000020U
-#define DMA_SxNDT_6                          0x00000040U
-#define DMA_SxNDT_7                          0x00000080U
-#define DMA_SxNDT_8                          0x00000100U
-#define DMA_SxNDT_9                          0x00000200U
-#define DMA_SxNDT_10                         0x00000400U
-#define DMA_SxNDT_11                         0x00000800U
-#define DMA_SxNDT_12                         0x00001000U
-#define DMA_SxNDT_13                         0x00002000U
-#define DMA_SxNDT_14                         0x00004000U
-#define DMA_SxNDT_15                         0x00008000U
-
-/********************  Bits definition for DMA_SxFCR register  ****************/
-#define DMA_SxFCR_FEIE                       0x00000080U
-#define DMA_SxFCR_FS                         0x00000038U
-#define DMA_SxFCR_FS_0                       0x00000008U
-#define DMA_SxFCR_FS_1                       0x00000010U
-#define DMA_SxFCR_FS_2                       0x00000020U
-#define DMA_SxFCR_DMDIS                      0x00000004U
-#define DMA_SxFCR_FTH                        0x00000003U
-#define DMA_SxFCR_FTH_0                      0x00000001U
-#define DMA_SxFCR_FTH_1                      0x00000002U
-
-/********************  Bits definition for DMA_LISR register  *****************/
-#define DMA_LISR_TCIF3                       0x08000000U
-#define DMA_LISR_HTIF3                       0x04000000U
-#define DMA_LISR_TEIF3                       0x02000000U
-#define DMA_LISR_DMEIF3                      0x01000000U
-#define DMA_LISR_FEIF3                       0x00400000U
-#define DMA_LISR_TCIF2                       0x00200000U
-#define DMA_LISR_HTIF2                       0x00100000U
-#define DMA_LISR_TEIF2                       0x00080000U
-#define DMA_LISR_DMEIF2                      0x00040000U
-#define DMA_LISR_FEIF2                       0x00010000U
-#define DMA_LISR_TCIF1                       0x00000800U
-#define DMA_LISR_HTIF1                       0x00000400U
-#define DMA_LISR_TEIF1                       0x00000200U
-#define DMA_LISR_DMEIF1                      0x00000100U
-#define DMA_LISR_FEIF1                       0x00000040U
-#define DMA_LISR_TCIF0                       0x00000020U
-#define DMA_LISR_HTIF0                       0x00000010U
-#define DMA_LISR_TEIF0                       0x00000008U
-#define DMA_LISR_DMEIF0                      0x00000004U
-#define DMA_LISR_FEIF0                       0x00000001U
-
-/********************  Bits definition for DMA_HISR register  *****************/
-#define DMA_HISR_TCIF7                       0x08000000U
-#define DMA_HISR_HTIF7                       0x04000000U
-#define DMA_HISR_TEIF7                       0x02000000U
-#define DMA_HISR_DMEIF7                      0x01000000U
-#define DMA_HISR_FEIF7                       0x00400000U
-#define DMA_HISR_TCIF6                       0x00200000U
-#define DMA_HISR_HTIF6                       0x00100000U
-#define DMA_HISR_TEIF6                       0x00080000U
-#define DMA_HISR_DMEIF6                      0x00040000U
-#define DMA_HISR_FEIF6                       0x00010000U
-#define DMA_HISR_TCIF5                       0x00000800U
-#define DMA_HISR_HTIF5                       0x00000400U
-#define DMA_HISR_TEIF5                       0x00000200U
-#define DMA_HISR_DMEIF5                      0x00000100U
-#define DMA_HISR_FEIF5                       0x00000040U
-#define DMA_HISR_TCIF4                       0x00000020U
-#define DMA_HISR_HTIF4                       0x00000010U
-#define DMA_HISR_TEIF4                       0x00000008U
-#define DMA_HISR_DMEIF4                      0x00000004U
-#define DMA_HISR_FEIF4                       0x00000001U
-
-/********************  Bits definition for DMA_LIFCR register  ****************/
-#define DMA_LIFCR_CTCIF3                     0x08000000U
-#define DMA_LIFCR_CHTIF3                     0x04000000U
-#define DMA_LIFCR_CTEIF3                     0x02000000U
-#define DMA_LIFCR_CDMEIF3                    0x01000000U
-#define DMA_LIFCR_CFEIF3                     0x00400000U
-#define DMA_LIFCR_CTCIF2                     0x00200000U
-#define DMA_LIFCR_CHTIF2                     0x00100000U
-#define DMA_LIFCR_CTEIF2                     0x00080000U
-#define DMA_LIFCR_CDMEIF2                    0x00040000U
-#define DMA_LIFCR_CFEIF2                     0x00010000U
-#define DMA_LIFCR_CTCIF1                     0x00000800U
-#define DMA_LIFCR_CHTIF1                     0x00000400U
-#define DMA_LIFCR_CTEIF1                     0x00000200U
-#define DMA_LIFCR_CDMEIF1                    0x00000100U
-#define DMA_LIFCR_CFEIF1                     0x00000040U
-#define DMA_LIFCR_CTCIF0                     0x00000020U
-#define DMA_LIFCR_CHTIF0                     0x00000010U
-#define DMA_LIFCR_CTEIF0                     0x00000008U
-#define DMA_LIFCR_CDMEIF0                    0x00000004U
-#define DMA_LIFCR_CFEIF0                     0x00000001U
-
-/********************  Bits definition for DMA_HIFCR  register  ****************/
-#define DMA_HIFCR_CTCIF7                     0x08000000U
-#define DMA_HIFCR_CHTIF7                     0x04000000U
-#define DMA_HIFCR_CTEIF7                     0x02000000U
-#define DMA_HIFCR_CDMEIF7                    0x01000000U
-#define DMA_HIFCR_CFEIF7                     0x00400000U
-#define DMA_HIFCR_CTCIF6                     0x00200000U
-#define DMA_HIFCR_CHTIF6                     0x00100000U
-#define DMA_HIFCR_CTEIF6                     0x00080000U
-#define DMA_HIFCR_CDMEIF6                    0x00040000U
-#define DMA_HIFCR_CFEIF6                     0x00010000U
-#define DMA_HIFCR_CTCIF5                     0x00000800U
-#define DMA_HIFCR_CHTIF5                     0x00000400U
-#define DMA_HIFCR_CTEIF5                     0x00000200U
-#define DMA_HIFCR_CDMEIF5                    0x00000100U
-#define DMA_HIFCR_CFEIF5                     0x00000040U
-#define DMA_HIFCR_CTCIF4                     0x00000020U
-#define DMA_HIFCR_CHTIF4                     0x00000010U
-#define DMA_HIFCR_CTEIF4                     0x00000008U
-#define DMA_HIFCR_CDMEIF4                    0x00000004U
-#define DMA_HIFCR_CFEIF4                     0x00000001U
-
-/******************************************************************************/
-/*                                                                            */
-/*                         AHB Master DMA2D Controller (DMA2D)                */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for DMA2D_CR register  ******************/
-
-#define DMA2D_CR_START                     0x00000001U               /*!< Start transfer                          */
-#define DMA2D_CR_SUSP                      0x00000002U               /*!< Suspend transfer                        */
-#define DMA2D_CR_ABORT                     0x00000004U               /*!< Abort transfer                          */
-#define DMA2D_CR_TEIE                      0x00000100U               /*!< Transfer Error Interrupt Enable         */
-#define DMA2D_CR_TCIE                      0x00000200U               /*!< Transfer Complete Interrupt Enable      */
-#define DMA2D_CR_TWIE                      0x00000400U               /*!< Transfer Watermark Interrupt Enable     */
-#define DMA2D_CR_CAEIE                     0x00000800U               /*!< CLUT Access Error Interrupt Enable      */
-#define DMA2D_CR_CTCIE                     0x00001000U               /*!< CLUT Transfer Complete Interrupt Enable */
-#define DMA2D_CR_CEIE                      0x00002000U               /*!< Configuration Error Interrupt Enable    */
-#define DMA2D_CR_MODE                      0x00030000U               /*!< DMA2D Mode[1:0]                         */
-#define DMA2D_CR_MODE_0                    0x00010000U               /*!< DMA2D Mode bit 0                        */
-#define DMA2D_CR_MODE_1                    0x00020000U               /*!< DMA2D Mode bit 1                        */
-
-/********************  Bit definition for DMA2D_ISR register  *****************/
-
-#define DMA2D_ISR_TEIF                     0x00000001U               /*!< Transfer Error Interrupt Flag         */
-#define DMA2D_ISR_TCIF                     0x00000002U               /*!< Transfer Complete Interrupt Flag      */
-#define DMA2D_ISR_TWIF                     0x00000004U               /*!< Transfer Watermark Interrupt Flag     */
-#define DMA2D_ISR_CAEIF                    0x00000008U               /*!< CLUT Access Error Interrupt Flag      */
-#define DMA2D_ISR_CTCIF                    0x00000010U               /*!< CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_ISR_CEIF                     0x00000020U               /*!< Configuration Error Interrupt Flag    */
-
-/********************  Bit definition for DMA2D_IFCR register  ****************/
-
-#define DMA2D_IFCR_CTEIF                   0x00000001U               /*!< Clears Transfer Error Interrupt Flag         */
-#define DMA2D_IFCR_CTCIF                   0x00000002U               /*!< Clears Transfer Complete Interrupt Flag      */
-#define DMA2D_IFCR_CTWIF                   0x00000004U               /*!< Clears Transfer Watermark Interrupt Flag     */
-#define DMA2D_IFCR_CAECIF                  0x00000008U               /*!< Clears CLUT Access Error Interrupt Flag      */
-#define DMA2D_IFCR_CCTCIF                  0x00000010U               /*!< Clears CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_IFCR_CCEIF                   0x00000020U               /*!< Clears Configuration Error Interrupt Flag    */
-
-/* Legacy defines */
-#define DMA2D_IFSR_CTEIF                   DMA2D_IFCR_CTEIF                     /*!< Clears Transfer Error Interrupt Flag         */
-#define DMA2D_IFSR_CTCIF                   DMA2D_IFCR_CTCIF                     /*!< Clears Transfer Complete Interrupt Flag      */
-#define DMA2D_IFSR_CTWIF                   DMA2D_IFCR_CTWIF                     /*!< Clears Transfer Watermark Interrupt Flag     */
-#define DMA2D_IFSR_CCAEIF                  DMA2D_IFCR_CAECIF                    /*!< Clears CLUT Access Error Interrupt Flag      */
-#define DMA2D_IFSR_CCTCIF                  DMA2D_IFCR_CCTCIF                    /*!< Clears CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_IFSR_CCEIF                   DMA2D_IFCR_CCEIF                     /*!< Clears Configuration Error Interrupt Flag    */
-
-/********************  Bit definition for DMA2D_FGMAR register  ***************/
-
-#define DMA2D_FGMAR_MA                     0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_FGOR register  ****************/
-
-#define DMA2D_FGOR_LO                      0x00003FFFU               /*!< Line Offset */
-
-/********************  Bit definition for DMA2D_BGMAR register  ***************/
-
-#define DMA2D_BGMAR_MA                     0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_BGOR register  ****************/
-
-#define DMA2D_BGOR_LO                      0x00003FFFU               /*!< Line Offset */
-
-/********************  Bit definition for DMA2D_FGPFCCR register  *************/
-
-#define DMA2D_FGPFCCR_CM                   0x0000000FU               /*!< Input color mode CM[3:0] */
-#define DMA2D_FGPFCCR_CM_0                 0x00000001U               /*!< Input color mode CM bit 0 */
-#define DMA2D_FGPFCCR_CM_1                 0x00000002U               /*!< Input color mode CM bit 1 */
-#define DMA2D_FGPFCCR_CM_2                 0x00000004U               /*!< Input color mode CM bit 2 */
-#define DMA2D_FGPFCCR_CM_3                 0x00000008U               /*!< Input color mode CM bit 3 */
-#define DMA2D_FGPFCCR_CCM                  0x00000010U               /*!< CLUT Color mode */
-#define DMA2D_FGPFCCR_START                0x00000020U               /*!< Start */
-#define DMA2D_FGPFCCR_CS                   0x0000FF00U               /*!< CLUT size */
-#define DMA2D_FGPFCCR_AM                   0x00030000U               /*!< Alpha mode AM[1:0] */
-#define DMA2D_FGPFCCR_AM_0                 0x00010000U               /*!< Alpha mode AM bit 0 */
-#define DMA2D_FGPFCCR_AM_1                 0x00020000U               /*!< Alpha mode AM bit 1 */
-#define DMA2D_FGPFCCR_AI                   0x00100000U               /*!< Foreground Input Alpha Inverted */
-#define DMA2D_FGPFCCR_RBS                  0x00200000U               /*!< Foreground Input Red Blue Swap */
-#define DMA2D_FGPFCCR_ALPHA                0xFF000000U               /*!< Alpha value */
-
-/********************  Bit definition for DMA2D_FGCOLR register  **************/
-
-#define DMA2D_FGCOLR_BLUE                  0x000000FFU               /*!< Blue Value */
-#define DMA2D_FGCOLR_GREEN                 0x0000FF00U               /*!< Green Value */
-#define DMA2D_FGCOLR_RED                   0x00FF0000U               /*!< Red Value */
-
-/********************  Bit definition for DMA2D_BGPFCCR register  *************/
-
-#define DMA2D_BGPFCCR_CM                   0x0000000FU               /*!< Input color mode CM[3:0] */
-#define DMA2D_BGPFCCR_CM_0                 0x00000001U               /*!< Input color mode CM bit 0 */
-#define DMA2D_BGPFCCR_CM_1                 0x00000002U               /*!< Input color mode CM bit 1 */
-#define DMA2D_BGPFCCR_CM_2                 0x00000004U               /*!< Input color mode CM bit 2 */
-#define DMA2D_FGPFCCR_CM_3                 0x00000008U               /*!< Input color mode CM bit 3 */
-#define DMA2D_BGPFCCR_CCM                  0x00000010U               /*!< CLUT Color mode */
-#define DMA2D_BGPFCCR_START                0x00000020U               /*!< Start */
-#define DMA2D_BGPFCCR_CS                   0x0000FF00U               /*!< CLUT size */
-#define DMA2D_BGPFCCR_AM                   0x00030000U               /*!< Alpha mode AM[1:0] */
-#define DMA2D_BGPFCCR_AM_0                 0x00010000U               /*!< Alpha mode AM bit 0 */
-#define DMA2D_BGPFCCR_AM_1                 0x00020000U               /*!< Alpha mode AM bit 1 */
-#define DMA2D_BGPFCCR_AI                   0x00100000U               /*!< background Input Alpha Inverted */
-#define DMA2D_BGPFCCR_RBS                  0x00200000U               /*!< Background Input Red Blue Swap */
-#define DMA2D_BGPFCCR_ALPHA                0xFF000000U               /*!< background Input Alpha value */
-
-/********************  Bit definition for DMA2D_BGCOLR register  **************/
-
-#define DMA2D_BGCOLR_BLUE                  0x000000FFU               /*!< Blue Value */
-#define DMA2D_BGCOLR_GREEN                 0x0000FF00U               /*!< Green Value */
-#define DMA2D_BGCOLR_RED                   0x00FF0000U               /*!< Red Value */
-
-/********************  Bit definition for DMA2D_FGCMAR register  **************/
-
-#define DMA2D_FGCMAR_MA                    0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_BGCMAR register  **************/
-
-#define DMA2D_BGCMAR_MA                    0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_OPFCCR register  **************/
-
-#define DMA2D_OPFCCR_CM                    0x00000007U               /*!< Color mode CM[2:0] */
-#define DMA2D_OPFCCR_CM_0                  0x00000001U               /*!< Color mode CM bit 0 */
-#define DMA2D_OPFCCR_CM_1                  0x00000002U               /*!< Color mode CM bit 1 */
-#define DMA2D_OPFCCR_CM_2                  0x00000004U               /*!< Color mode CM bit 2 */
-#define DMA2D_OPFCCR_AI                    0x00100000U               /*!< Output Alpha Inverted */
-#define DMA2D_OPFCCR_RBS                   0x00200000U               /*!< Output Red Blue Swap */
-
-/********************  Bit definition for DMA2D_OCOLR register  ***************/
-
-/*!<Mode_ARGB8888/RGB888 */
-
-#define DMA2D_OCOLR_BLUE_1                 0x000000FFU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_1                0x0000FF00U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_1                  0x00FF0000U               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_1                0xFF000000U               /*!< Alpha Channel Value */
-
-/*!<Mode_RGB565 */
-#define DMA2D_OCOLR_BLUE_2                 0x0000001FU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_2                0x000007E0U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_2                  0x0000F800U               /*!< Red Value */
-
-/*!<Mode_ARGB1555 */
-#define DMA2D_OCOLR_BLUE_3                 0x0000001FU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_3                0x000003E0U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_3                  0x00007C00U               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_3                0x00008000U               /*!< Alpha Channel Value */
-
-/*!<Mode_ARGB4444 */
-#define DMA2D_OCOLR_BLUE_4                 0x0000000FU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_4                0x000000F0U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_4                  0x00000F00U               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_4                0x0000F000U               /*!< Alpha Channel Value */
-
-/********************  Bit definition for DMA2D_OMAR register  ****************/
-
-#define DMA2D_OMAR_MA                      0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_OOR register  *****************/
-
-#define DMA2D_OOR_LO                       0x00003FFFU               /*!< Line Offset */
-
-/********************  Bit definition for DMA2D_NLR register  *****************/
-
-#define DMA2D_NLR_NL                       0x0000FFFFU               /*!< Number of Lines */
-#define DMA2D_NLR_PL                       0x3FFF0000U               /*!< Pixel per Lines */
-
-/********************  Bit definition for DMA2D_LWR register  *****************/
-
-#define DMA2D_LWR_LW                       0x0000FFFFU               /*!< Line Watermark */
-
-/********************  Bit definition for DMA2D_AMTCR register  ***************/
-
-#define DMA2D_AMTCR_EN                     0x00000001U               /*!< Enable */
-#define DMA2D_AMTCR_DT                     0x0000FF00U               /*!< Dead Time */
-
-
-/********************  Bit definition for DMA2D_FGCLUT register  **************/
-
-/********************  Bit definition for DMA2D_BGCLUT register  **************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                    External Interrupt/Event Controller                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
-#define  EXTI_IMR_MR23                       0x00800000U        /*!< Interrupt Mask on line 23 */
-#define  EXTI_IMR_MR24                       0x01000000U        /*!< Interrupt Mask on line 24 */
-
-/* Reference Defines */
-#define  EXTI_IMR_IM0                        EXTI_IMR_MR0
-#define  EXTI_IMR_IM1                        EXTI_IMR_MR1
-#define  EXTI_IMR_IM2                        EXTI_IMR_MR2
-#define  EXTI_IMR_IM3                        EXTI_IMR_MR3
-#define  EXTI_IMR_IM4                        EXTI_IMR_MR4
-#define  EXTI_IMR_IM5                        EXTI_IMR_MR5
-#define  EXTI_IMR_IM6                        EXTI_IMR_MR6
-#define  EXTI_IMR_IM7                        EXTI_IMR_MR7
-#define  EXTI_IMR_IM8                        EXTI_IMR_MR8
-#define  EXTI_IMR_IM9                        EXTI_IMR_MR9
-#define  EXTI_IMR_IM10                       EXTI_IMR_MR10
-#define  EXTI_IMR_IM11                       EXTI_IMR_MR11
-#define  EXTI_IMR_IM12                       EXTI_IMR_MR12
-#define  EXTI_IMR_IM13                       EXTI_IMR_MR13
-#define  EXTI_IMR_IM14                       EXTI_IMR_MR14
-#define  EXTI_IMR_IM15                       EXTI_IMR_MR15
-#define  EXTI_IMR_IM16                       EXTI_IMR_MR16
-#define  EXTI_IMR_IM17                       EXTI_IMR_MR17
-#define  EXTI_IMR_IM18                       EXTI_IMR_MR18
-#define  EXTI_IMR_IM19                       EXTI_IMR_MR19
-#define  EXTI_IMR_IM20                       EXTI_IMR_MR20
-#define  EXTI_IMR_IM21                       EXTI_IMR_MR21
-#define  EXTI_IMR_IM22                       EXTI_IMR_MR22
-#define  EXTI_IMR_IM23                       EXTI_IMR_MR23
-#define  EXTI_IMR_IM24                       EXTI_IMR_MR24
-
-#define  EXTI_IMR_IM                         0x01FFFFFFU        /*!< Interrupt Mask All */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
-#define  EXTI_EMR_MR23                       0x00800000U        /*!< Event Mask on line 23 */
-#define  EXTI_EMR_MR24                       0x01000000U        /*!< Event Mask on line 24 */
-
-/* Reference Defines */
-#define  EXTI_EMR_EM0                        EXTI_EMR_MR0
-#define  EXTI_EMR_EM1                        EXTI_EMR_MR1
-#define  EXTI_EMR_EM2                        EXTI_EMR_MR2
-#define  EXTI_EMR_EM3                        EXTI_EMR_MR3
-#define  EXTI_EMR_EM4                        EXTI_EMR_MR4
-#define  EXTI_EMR_EM5                        EXTI_EMR_MR5
-#define  EXTI_EMR_EM6                        EXTI_EMR_MR6
-#define  EXTI_EMR_EM7                        EXTI_EMR_MR7
-#define  EXTI_EMR_EM8                        EXTI_EMR_MR8
-#define  EXTI_EMR_EM9                        EXTI_EMR_MR9
-#define  EXTI_EMR_EM10                       EXTI_EMR_MR10
-#define  EXTI_EMR_EM11                       EXTI_EMR_MR11
-#define  EXTI_EMR_EM12                       EXTI_EMR_MR12
-#define  EXTI_EMR_EM13                       EXTI_EMR_MR13
-#define  EXTI_EMR_EM14                       EXTI_EMR_MR14
-#define  EXTI_EMR_EM15                       EXTI_EMR_MR15
-#define  EXTI_EMR_EM16                       EXTI_EMR_MR16
-#define  EXTI_EMR_EM17                       EXTI_EMR_MR17
-#define  EXTI_EMR_EM18                       EXTI_EMR_MR18
-#define  EXTI_EMR_EM19                       EXTI_EMR_MR19
-#define  EXTI_EMR_EM20                       EXTI_EMR_MR20
-#define  EXTI_EMR_EM21                       EXTI_EMR_MR21
-#define  EXTI_EMR_EM22                       EXTI_EMR_MR22
-#define  EXTI_EMR_EM23                       EXTI_EMR_MR23
-#define  EXTI_EMR_EM24                       EXTI_EMR_MR24
-
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
-#define  EXTI_RTSR_TR23                      0x00800000U        /*!< Rising trigger event configuration bit of line 23 */
-#define  EXTI_RTSR_TR24                      0x01000000U        /*!< Rising trigger event configuration bit of line 24 */
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
-#define  EXTI_FTSR_TR23                      0x00800000U        /*!< Falling trigger event configuration bit of line 23 */
-#define  EXTI_FTSR_TR24                      0x01000000U        /*!< Falling trigger event configuration bit of line 24 */
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
-#define  EXTI_SWIER_SWIER23                  0x00800000U        /*!< Software Interrupt on line 23 */
-#define  EXTI_SWIER_SWIER24                  0x01000000U        /*!< Software Interrupt on line 24 */
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
-#define  EXTI_PR_PR23                        0x00800000U        /*!< Pending bit for line 23 */
-#define  EXTI_PR_PR24                        0x01000000U        /*!< Pending bit for line 24 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    FLASH                                   */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief FLASH Total Sectors Number
-*/
-#define FLASH_SECTOR_TOTAL  24
-
-/*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    0x0000000FU
-#define FLASH_ACR_LATENCY_0WS                0x00000000U
-#define FLASH_ACR_LATENCY_1WS                0x00000001U
-#define FLASH_ACR_LATENCY_2WS                0x00000002U
-#define FLASH_ACR_LATENCY_3WS                0x00000003U
-#define FLASH_ACR_LATENCY_4WS                0x00000004U
-#define FLASH_ACR_LATENCY_5WS                0x00000005U
-#define FLASH_ACR_LATENCY_6WS                0x00000006U
-#define FLASH_ACR_LATENCY_7WS                0x00000007U
-#define FLASH_ACR_LATENCY_8WS                0x00000008U
-#define FLASH_ACR_LATENCY_9WS                0x00000009U
-#define FLASH_ACR_LATENCY_10WS               0x0000000AU
-#define FLASH_ACR_LATENCY_11WS               0x0000000BU
-#define FLASH_ACR_LATENCY_12WS               0x0000000CU
-#define FLASH_ACR_LATENCY_13WS               0x0000000DU
-#define FLASH_ACR_LATENCY_14WS               0x0000000EU
-#define FLASH_ACR_LATENCY_15WS               0x0000000FU
-#define FLASH_ACR_PRFTEN                     0x00000100U
-#define FLASH_ACR_ARTEN                      0x00000200U
-#define FLASH_ACR_ARTRST                     0x00000800U
-
-/*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         0x00000001U
-#define FLASH_SR_OPERR                       0x00000002U
-#define FLASH_SR_WRPERR                      0x00000010U
-#define FLASH_SR_PGAERR                      0x00000020U
-#define FLASH_SR_PGPERR                      0x00000040U
-#define FLASH_SR_ERSERR                      0x00000080U
-#define FLASH_SR_BSY                         0x00010000U
-
-/*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          0x00000001U
-#define FLASH_CR_SER                         0x00000002U
-#define FLASH_CR_MER                         0x00000004U
-#define FLASH_CR_MER1                        FLASH_CR_MER
-#define FLASH_CR_SNB                         0x000000F8U
-#define FLASH_CR_SNB_0                       0x00000008U
-#define FLASH_CR_SNB_1                       0x00000010U
-#define FLASH_CR_SNB_2                       0x00000020U
-#define FLASH_CR_SNB_3                       0x00000040U
-#define FLASH_CR_SNB_4                       0x00000080U
-#define FLASH_CR_PSIZE                       0x00000300U
-#define FLASH_CR_PSIZE_0                     0x00000100U
-#define FLASH_CR_PSIZE_1                     0x00000200U
-#define FLASH_CR_MER2                        0x00008000U
-#define FLASH_CR_STRT                        0x00010000U
-#define FLASH_CR_EOPIE                       0x01000000U
-#define FLASH_CR_ERRIE                       0x02000000U
-#define FLASH_CR_LOCK                        0x80000000U
-
-/*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                 0x00000001U
-#define FLASH_OPTCR_OPTSTRT                 0x00000002U
-#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
-#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
-#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
-#define FLASH_OPTCR_WWDG_SW                 0x00000010U
-#define FLASH_OPTCR_IWDG_SW                 0x00000020U
-#define FLASH_OPTCR_nRST_STOP               0x00000040U
-#define FLASH_OPTCR_nRST_STDBY              0x00000080U
-#define FLASH_OPTCR_RDP                     0x0000FF00U
-#define FLASH_OPTCR_RDP_0                   0x00000100U
-#define FLASH_OPTCR_RDP_1                   0x00000200U
-#define FLASH_OPTCR_RDP_2                   0x00000400U
-#define FLASH_OPTCR_RDP_3                   0x00000800U
-#define FLASH_OPTCR_RDP_4                   0x00001000U
-#define FLASH_OPTCR_RDP_5                   0x00002000U
-#define FLASH_OPTCR_RDP_6                   0x00004000U
-#define FLASH_OPTCR_RDP_7                   0x00008000U
-#define FLASH_OPTCR_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR_nWRP_0                  0x00010000U
-#define FLASH_OPTCR_nWRP_1                  0x00020000U
-#define FLASH_OPTCR_nWRP_2                  0x00040000U
-#define FLASH_OPTCR_nWRP_3                  0x00080000U
-#define FLASH_OPTCR_nWRP_4                  0x00100000U
-#define FLASH_OPTCR_nWRP_5                  0x00200000U
-#define FLASH_OPTCR_nWRP_6                  0x00400000U
-#define FLASH_OPTCR_nWRP_7                  0x00800000U
-#define FLASH_OPTCR_nWRP_8                  0x01000000U
-#define FLASH_OPTCR_nWRP_9                  0x02000000U
-#define FLASH_OPTCR_nWRP_10                 0x04000000U
-#define FLASH_OPTCR_nWRP_11                 0x08000000U
-#define FLASH_OPTCR_nDBOOT                  0x10000000U
-#define FLASH_OPTCR_nDBANK                  0x20000000U
-#define FLASH_OPTCR_IWDG_STDBY              0x40000000U
-#define FLASH_OPTCR_IWDG_STOP               0x80000000U
-
-/*******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_BOOT_ADD0              0x0000FFFFU
-#define FLASH_OPTCR1_BOOT_ADD1              0xFFFF0000U
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Flexible Memory Controller                        */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for FMC_BCR1 register  *******************/
-#define  FMC_BCR1_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR1_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-#define  FMC_BCR1_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR1_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR1_MTYP_1                    0x00000008U        /*!<Bit 1 */
-#define  FMC_BCR1_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR1_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR1_MWID_1                    0x00000020U        /*!<Bit 1 */
-#define  FMC_BCR1_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR1_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR1_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR1_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
-#define  FMC_BCR1_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR1_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR1_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR1_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR1_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR1_CPSIZE                    0x00070000U        /*!<CRAM page size             */
-#define  FMC_BCR1_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FMC_BCR1_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FMC_BCR1_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FMC_BCR1_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-#define  FMC_BCR1_CCLKEN                    0x00100000U        /*!<Continous clock enable     */
-#define  FMC_BCR1_WFDIS                     0x00200000U        /*!<Write FIFO Disable         */
-
-/******************  Bit definition for FMC_BCR2 register  *******************/
-#define  FMC_BCR2_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR2_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-#define  FMC_BCR2_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR2_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR2_MTYP_1                    0x00000008U        /*!<Bit 1 */
-#define  FMC_BCR2_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR2_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR2_MWID_1                    0x00000020U        /*!<Bit 1 */
-#define  FMC_BCR2_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR2_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR2_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR2_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
-#define  FMC_BCR2_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR2_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR2_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR2_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR2_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR2_CPSIZE                    0x00070000U        /*!<CRAM page size             */
-#define  FMC_BCR2_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FMC_BCR2_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FMC_BCR2_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FMC_BCR2_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FMC_BCR3 register  *******************/
-#define  FMC_BCR3_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR3_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-#define  FMC_BCR3_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR3_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR3_MTYP_1                    0x00000008U        /*!<Bit 1 */
-#define  FMC_BCR3_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR3_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR3_MWID_1                    0x00000020U        /*!<Bit 1 */
-#define  FMC_BCR3_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR3_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR3_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR3_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
-#define  FMC_BCR3_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR3_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR3_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR3_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR3_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR3_CPSIZE                    0x00070000U        /*!<CRAM page size             */
-#define  FMC_BCR3_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FMC_BCR3_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FMC_BCR3_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FMC_BCR3_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FMC_BCR4 register  *******************/
-#define  FMC_BCR4_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR4_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-#define  FMC_BCR4_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR4_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR4_MTYP_1                    0x00000008U        /*!<Bit 1 */
-#define  FMC_BCR4_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR4_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR4_MWID_1                    0x00000020U        /*!<Bit 1 */
-#define  FMC_BCR4_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR4_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR4_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR4_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
-#define  FMC_BCR4_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR4_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR4_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR4_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR4_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR4_CPSIZE                    0x00070000U        /*!<CRAM page size             */
-#define  FMC_BCR4_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FMC_BCR4_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FMC_BCR4_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FMC_BCR4_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FMC_BTR1 register  ******************/
-#define  FMC_BTR1_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR1_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR1_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR1_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR1_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-#define  FMC_BTR1_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
-#define  FMC_BTR1_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR1_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR1_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR1_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-#define  FMC_BTR1_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR1_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR1_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR1_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR1_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR1_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR1_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR1_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR1_DATAST_7                  0x00008000U        /*!<Bit 7 */
-#define  FMC_BTR1_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR1_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR1_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR1_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR1_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-#define  FMC_BTR1_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR1_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR1_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR1_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR1_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-#define  FMC_BTR1_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR1_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR1_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR1_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR1_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-#define  FMC_BTR1_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR1_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR1_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BTR2 register  *******************/
-#define  FMC_BTR2_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR2_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR2_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR2_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR2_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-#define  FMC_BTR2_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR2_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR2_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR2_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR2_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-#define  FMC_BTR2_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR2_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR2_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR2_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR2_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR2_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR2_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR2_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR2_DATAST_7                  0x00008000U        /*!<Bit 7 */
-#define  FMC_BTR2_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR2_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR2_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR2_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR2_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-#define  FMC_BTR2_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR2_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR2_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR2_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR2_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-#define  FMC_BTR2_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR2_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR2_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR2_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR2_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-#define  FMC_BTR2_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR2_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR2_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/*******************  Bit definition for FMC_BTR3 register  *******************/
-#define  FMC_BTR3_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR3_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR3_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR3_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR3_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-#define  FMC_BTR3_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR3_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR3_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR3_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR3_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-#define  FMC_BTR3_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR3_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR3_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR3_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR3_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR3_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR3_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR3_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR3_DATAST_7                  0x00008000U        /*!<Bit 7 */
-#define  FMC_BTR3_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR3_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR3_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR3_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR3_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-#define  FMC_BTR3_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR3_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR3_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR3_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR3_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-#define  FMC_BTR3_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR3_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR3_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR3_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR3_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-#define  FMC_BTR3_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR3_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR3_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BTR4 register  *******************/
-#define  FMC_BTR4_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR4_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR4_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR4_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR4_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-#define  FMC_BTR4_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR4_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR4_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR4_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR4_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-#define  FMC_BTR4_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR4_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR4_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR4_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR4_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR4_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR4_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR4_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR4_DATAST_7                  0x00008000U        /*!<Bit 7 */
-#define  FMC_BTR4_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR4_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR4_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR4_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR4_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-#define  FMC_BTR4_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR4_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR4_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR4_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR4_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-#define  FMC_BTR4_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR4_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR4_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR4_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR4_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-#define  FMC_BTR4_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR4_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR4_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR1 register  ******************/
-#define  FMC_BWTR1_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR1_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR1_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR1_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR1_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-#define  FMC_BWTR1_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR1_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR1_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR1_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR1_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-#define  FMC_BWTR1_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR1_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR1_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR1_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR1_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR1_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR1_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR1_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR1_DATAST_7                 0x00008000U        /*!<Bit 7 */
-#define  FMC_BWTR1_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BWTR1_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR1_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR1_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR1_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-#define  FMC_BWTR1_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR1_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR1_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR2 register  ******************/
-#define  FMC_BWTR2_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR2_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR2_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR2_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR2_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-#define  FMC_BWTR2_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR2_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR2_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR2_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR2_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-#define  FMC_BWTR2_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR2_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR2_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR2_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR2_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR2_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR2_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR2_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR2_DATAST_7                 0x00008000U        /*!<Bit 7 */
-#define  FMC_BWTR2_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BWTR2_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR2_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR2_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR2_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-#define  FMC_BWTR2_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR2_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR2_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR3 register  ******************/
-#define  FMC_BWTR3_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR3_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR3_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR3_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR3_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-#define  FMC_BWTR3_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR3_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR3_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR3_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR3_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-#define  FMC_BWTR3_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR3_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR3_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR3_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR3_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR3_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR3_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR3_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR3_DATAST_7                 0x00008000U        /*!<Bit 7 */
-#define  FMC_BWTR3_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BWTR3_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR3_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR3_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR3_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-#define  FMC_BWTR3_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR3_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR3_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR4 register  ******************/
-#define  FMC_BWTR4_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR4_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR4_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR4_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR4_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-#define  FMC_BWTR4_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR4_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR4_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR4_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR4_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-#define  FMC_BWTR4_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR4_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR4_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR4_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR4_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR4_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR4_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR4_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR4_DATAST_7                 0x00008000U        /*!<Bit 7 */
-#define  FMC_BWTR4_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BWTR4_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR4_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR4_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR4_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-#define  FMC_BWTR4_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR4_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR4_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_PCR register  *******************/
-#define  FMC_PCR_PWAITEN                   0x00000002U        /*!<Wait feature enable bit                   */
-#define  FMC_PCR_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FMC_PCR_PTYP                      0x00000008U        /*!<Memory type                               */
-#define  FMC_PCR_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FMC_PCR_PWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_PCR_PWID_1                    0x00000020U        /*!<Bit 1 */
-#define  FMC_PCR_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit          */
-#define  FMC_PCR_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay)          */
-#define  FMC_PCR_TCLR_0                    0x00000200U        /*!<Bit 0 */
-#define  FMC_PCR_TCLR_1                    0x00000400U        /*!<Bit 1 */
-#define  FMC_PCR_TCLR_2                    0x00000800U        /*!<Bit 2 */
-#define  FMC_PCR_TCLR_3                    0x00001000U        /*!<Bit 3 */
-#define  FMC_PCR_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay)           */
-#define  FMC_PCR_TAR_0                     0x00002000U        /*!<Bit 0 */
-#define  FMC_PCR_TAR_1                     0x00004000U        /*!<Bit 1 */
-#define  FMC_PCR_TAR_2                     0x00008000U        /*!<Bit 2 */
-#define  FMC_PCR_TAR_3                     0x00010000U        /*!<Bit 3 */
-#define  FMC_PCR_ECCPS                     0x000E0000U        /*!<ECCPS[2:0] bits (ECC page size)           */
-#define  FMC_PCR_ECCPS_0                   0x00020000U        /*!<Bit 0 */
-#define  FMC_PCR_ECCPS_1                   0x00040000U        /*!<Bit 1 */
-#define  FMC_PCR_ECCPS_2                   0x00080000U        /*!<Bit 2 */
-
-/*******************  Bit definition for FMC_SR register  *******************/
-#define  FMC_SR_IRS                        0x01U              /*!<Interrupt Rising Edge status                */
-#define  FMC_SR_ILS                        0x02U              /*!<Interrupt Level status                      */
-#define  FMC_SR_IFS                        0x04U              /*!<Interrupt Falling Edge status               */
-#define  FMC_SR_IREN                       0x08U              /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FMC_SR_ILEN                       0x10U              /*!<Interrupt Level detection Enable bit        */
-#define  FMC_SR_IFEN                       0x20U              /*!<Interrupt Falling Edge detection Enable bit */
-#define  FMC_SR_FEMPT                      0x40U              /*!<FIFO empty                                  */
-
-/******************  Bit definition for FMC_PMEM register  ******************/
-#define  FMC_PMEM_MEMSET3                  0x000000FFU        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
-#define  FMC_PMEM_MEMSET3_0                0x00000001U        /*!<Bit 0 */
-#define  FMC_PMEM_MEMSET3_1                0x00000002U        /*!<Bit 1 */
-#define  FMC_PMEM_MEMSET3_2                0x00000004U        /*!<Bit 2 */
-#define  FMC_PMEM_MEMSET3_3                0x00000008U        /*!<Bit 3 */
-#define  FMC_PMEM_MEMSET3_4                0x00000010U        /*!<Bit 4 */
-#define  FMC_PMEM_MEMSET3_5                0x00000020U        /*!<Bit 5 */
-#define  FMC_PMEM_MEMSET3_6                0x00000040U        /*!<Bit 6 */
-#define  FMC_PMEM_MEMSET3_7                0x00000080U        /*!<Bit 7 */
-#define  FMC_PMEM_MEMWAIT3                 0x0000FF00U        /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
-#define  FMC_PMEM_MEMWAIT3_0               0x00000100U        /*!<Bit 0 */
-#define  FMC_PMEM_MEMWAIT3_1               0x00000200U        /*!<Bit 1 */
-#define  FMC_PMEM_MEMWAIT3_2               0x00000400U        /*!<Bit 2 */
-#define  FMC_PMEM_MEMWAIT3_3               0x00000800U        /*!<Bit 3 */
-#define  FMC_PMEM_MEMWAIT3_4               0x00001000U        /*!<Bit 4 */
-#define  FMC_PMEM_MEMWAIT3_5               0x00002000U        /*!<Bit 5 */
-#define  FMC_PMEM_MEMWAIT3_6               0x00004000U        /*!<Bit 6 */
-#define  FMC_PMEM_MEMWAIT3_7               0x00008000U        /*!<Bit 7 */
-#define  FMC_PMEM_MEMHOLD3                 0x00FF0000U        /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
-#define  FMC_PMEM_MEMHOLD3_0               0x00010000U        /*!<Bit 0 */
-#define  FMC_PMEM_MEMHOLD3_1               0x00020000U        /*!<Bit 1 */
-#define  FMC_PMEM_MEMHOLD3_2               0x00040000U        /*!<Bit 2 */
-#define  FMC_PMEM_MEMHOLD3_3               0x00080000U        /*!<Bit 3 */
-#define  FMC_PMEM_MEMHOLD3_4               0x00100000U        /*!<Bit 4 */
-#define  FMC_PMEM_MEMHOLD3_5               0x00200000U        /*!<Bit 5 */
-#define  FMC_PMEM_MEMHOLD3_6               0x00400000U        /*!<Bit 6 */
-#define  FMC_PMEM_MEMHOLD3_7               0x00800000U        /*!<Bit 7 */
-#define  FMC_PMEM_MEMHIZ3                  0xFF000000U        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
-#define  FMC_PMEM_MEMHIZ3_0                0x01000000U        /*!<Bit 0 */
-#define  FMC_PMEM_MEMHIZ3_1                0x02000000U        /*!<Bit 1 */
-#define  FMC_PMEM_MEMHIZ3_2                0x04000000U        /*!<Bit 2 */
-#define  FMC_PMEM_MEMHIZ3_3                0x08000000U        /*!<Bit 3 */
-#define  FMC_PMEM_MEMHIZ3_4                0x10000000U        /*!<Bit 4 */
-#define  FMC_PMEM_MEMHIZ3_5                0x20000000U        /*!<Bit 5 */
-#define  FMC_PMEM_MEMHIZ3_6                0x40000000U        /*!<Bit 6 */
-#define  FMC_PMEM_MEMHIZ3_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_PATT register  ******************/
-#define  FMC_PATT_ATTSET3                  0x000000FFU        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
-#define  FMC_PATT_ATTSET3_0                0x00000001U        /*!<Bit 0 */
-#define  FMC_PATT_ATTSET3_1                0x00000002U        /*!<Bit 1 */
-#define  FMC_PATT_ATTSET3_2                0x00000004U        /*!<Bit 2 */
-#define  FMC_PATT_ATTSET3_3                0x00000008U        /*!<Bit 3 */
-#define  FMC_PATT_ATTSET3_4                0x00000010U        /*!<Bit 4 */
-#define  FMC_PATT_ATTSET3_5                0x00000020U        /*!<Bit 5 */
-#define  FMC_PATT_ATTSET3_6                0x00000040U        /*!<Bit 6 */
-#define  FMC_PATT_ATTSET3_7                0x00000080U        /*!<Bit 7 */
-#define  FMC_PATT_ATTWAIT3                 0x0000FF00U        /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
-#define  FMC_PATT_ATTWAIT3_0               0x00000100U        /*!<Bit 0 */
-#define  FMC_PATT_ATTWAIT3_1               0x00000200U        /*!<Bit 1 */
-#define  FMC_PATT_ATTWAIT3_2               0x00000400U        /*!<Bit 2 */
-#define  FMC_PATT_ATTWAIT3_3               0x00000800U        /*!<Bit 3 */
-#define  FMC_PATT_ATTWAIT3_4               0x00001000U        /*!<Bit 4 */
-#define  FMC_PATT_ATTWAIT3_5               0x00002000U        /*!<Bit 5 */
-#define  FMC_PATT_ATTWAIT3_6               0x00004000U        /*!<Bit 6 */
-#define  FMC_PATT_ATTWAIT3_7               0x00008000U        /*!<Bit 7 */
-#define  FMC_PATT_ATTHOLD3                 0x00FF0000U        /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
-#define  FMC_PATT_ATTHOLD3_0               0x00010000U        /*!<Bit 0 */
-#define  FMC_PATT_ATTHOLD3_1               0x00020000U        /*!<Bit 1 */
-#define  FMC_PATT_ATTHOLD3_2               0x00040000U        /*!<Bit 2 */
-#define  FMC_PATT_ATTHOLD3_3               0x00080000U        /*!<Bit 3 */
-#define  FMC_PATT_ATTHOLD3_4               0x00100000U        /*!<Bit 4 */
-#define  FMC_PATT_ATTHOLD3_5               0x00200000U        /*!<Bit 5 */
-#define  FMC_PATT_ATTHOLD3_6               0x00400000U        /*!<Bit 6 */
-#define  FMC_PATT_ATTHOLD3_7               0x00800000U        /*!<Bit 7 */
-#define  FMC_PATT_ATTHIZ3                  0xFF000000U        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
-#define  FMC_PATT_ATTHIZ3_0                0x01000000U        /*!<Bit 0 */
-#define  FMC_PATT_ATTHIZ3_1                0x02000000U        /*!<Bit 1 */
-#define  FMC_PATT_ATTHIZ3_2                0x04000000U        /*!<Bit 2 */
-#define  FMC_PATT_ATTHIZ3_3                0x08000000U        /*!<Bit 3 */
-#define  FMC_PATT_ATTHIZ3_4                0x10000000U        /*!<Bit 4 */
-#define  FMC_PATT_ATTHIZ3_5                0x20000000U        /*!<Bit 5 */
-#define  FMC_PATT_ATTHIZ3_6                0x40000000U        /*!<Bit 6 */
-#define  FMC_PATT_ATTHIZ3_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_ECCR register  ******************/
-#define  FMC_ECCR_ECC3                     0xFFFFFFFFU        /*!<ECC result */
-
-/******************  Bit definition for FMC_SDCR1 register  ******************/
-#define  FMC_SDCR1_NC                       0x00000003U        /*!<NC[1:0] bits (Number of column bits) */
-#define  FMC_SDCR1_NC_0                     0x00000001U        /*!<Bit 0 */
-#define  FMC_SDCR1_NC_1                     0x00000002U        /*!<Bit 1 */
-#define  FMC_SDCR1_NR                       0x0000000CU        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR1_NR_0                     0x00000004U        /*!<Bit 0 */
-#define  FMC_SDCR1_NR_1                     0x00000008U        /*!<Bit 1 */
-#define  FMC_SDCR1_MWID                     0x00000030U        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR1_MWID_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDCR1_MWID_1                   0x00000020U        /*!<Bit 1 */
-#define  FMC_SDCR1_NB                       0x00000040U        /*!<Number of internal bank */
-#define  FMC_SDCR1_CAS                      0x00000180U        /*!<CAS[1:0] bits (CAS latency) */
-#define  FMC_SDCR1_CAS_0                    0x00000080U        /*!<Bit 0 */
-#define  FMC_SDCR1_CAS_1                    0x00000100U        /*!<Bit 1 */
-#define  FMC_SDCR1_WP                       0x00000200U        /*!<Write protection */
-#define  FMC_SDCR1_SDCLK                    0x00000C00U        /*!<SDRAM clock configuration */
-#define  FMC_SDCR1_SDCLK_0                  0x00000400U        /*!<Bit 0 */
-#define  FMC_SDCR1_SDCLK_1                  0x00000800U        /*!<Bit 1 */
-#define  FMC_SDCR1_RBURST                   0x00001000U        /*!<Read burst */
-#define  FMC_SDCR1_RPIPE                    0x00006000U        /*!<Write protection */
-#define  FMC_SDCR1_RPIPE_0                  0x00002000U        /*!<Bit 0 */
-#define  FMC_SDCR1_RPIPE_1                  0x00004000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_SDCR2 register  ******************/
-#define  FMC_SDCR2_NC                       0x00000003U        /*!<NC[1:0] bits (Number of column bits) */
-#define  FMC_SDCR2_NC_0                     0x00000001U        /*!<Bit 0 */
-#define  FMC_SDCR2_NC_1                     0x00000002U        /*!<Bit 1 */
-#define  FMC_SDCR2_NR                       0x0000000CU        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR2_NR_0                     0x00000004U        /*!<Bit 0 */
-#define  FMC_SDCR2_NR_1                     0x00000008U        /*!<Bit 1 */
-#define  FMC_SDCR2_MWID                     0x00000030U        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR2_MWID_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDCR2_MWID_1                   0x00000020U        /*!<Bit 1 */
-#define  FMC_SDCR2_NB                       0x00000040U        /*!<Number of internal bank */
-#define  FMC_SDCR2_CAS                      0x00000180U        /*!<CAS[1:0] bits (CAS latency) */
-#define  FMC_SDCR2_CAS_0                    0x00000080U        /*!<Bit 0 */
-#define  FMC_SDCR2_CAS_1                    0x00000100U        /*!<Bit 1 */
-#define  FMC_SDCR2_WP                       0x00000200U        /*!<Write protection */
-#define  FMC_SDCR2_SDCLK                    0x00000C00U        /*!<SDCLK[1:0] (SDRAM clock configuration) */
-#define  FMC_SDCR2_SDCLK_0                  0x00000400U        /*!<Bit 0 */
-#define  FMC_SDCR2_SDCLK_1                  0x00000800U        /*!<Bit 1 */
-#define  FMC_SDCR2_RBURST                   0x00001000U        /*!<Read burst */
-#define  FMC_SDCR2_RPIPE                    0x00006000U        /*!<RPIPE[1:0](Read pipe) */
-#define  FMC_SDCR2_RPIPE_0                  0x00002000U        /*!<Bit 0 */
-#define  FMC_SDCR2_RPIPE_1                  0x00004000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_SDTR1 register  ******************/
-#define  FMC_SDTR1_TMRD                     0x0000000FU        /*!<TMRD[3:0] bits (Load mode register to active) */
-#define  FMC_SDTR1_TMRD_0                   0x00000001U        /*!<Bit 0 */
-#define  FMC_SDTR1_TMRD_1                   0x00000002U        /*!<Bit 1 */
-#define  FMC_SDTR1_TMRD_2                   0x00000004U        /*!<Bit 2 */
-#define  FMC_SDTR1_TMRD_3                   0x00000008U        /*!<Bit 3 */
-#define  FMC_SDTR1_TXSR                     0x000000F0U        /*!<TXSR[3:0] bits (Exit self refresh) */
-#define  FMC_SDTR1_TXSR_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDTR1_TXSR_1                   0x00000020U        /*!<Bit 1 */
-#define  FMC_SDTR1_TXSR_2                   0x00000040U        /*!<Bit 2 */
-#define  FMC_SDTR1_TXSR_3                   0x00000080U        /*!<Bit 3 */
-#define  FMC_SDTR1_TRAS                     0x00000F00U        /*!<TRAS[3:0] bits (Self refresh time) */
-#define  FMC_SDTR1_TRAS_0                   0x00000100U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRAS_1                   0x00000200U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRAS_2                   0x00000400U        /*!<Bit 2 */
-#define  FMC_SDTR1_TRAS_3                   0x00000800U        /*!<Bit 3 */
-#define  FMC_SDTR1_TRC                      0x0000F000U        /*!<TRC[2:0] bits (Row cycle delay) */
-#define  FMC_SDTR1_TRC_0                    0x00001000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRC_1                    0x00002000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRC_2                    0x00004000U        /*!<Bit 2 */
-#define  FMC_SDTR1_TWR                      0x000F0000U        /*!<TRC[2:0] bits (Write recovery delay) */
-#define  FMC_SDTR1_TWR_0                    0x00010000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TWR_1                    0x00020000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TWR_2                    0x00040000U        /*!<Bit 2 */
-#define  FMC_SDTR1_TRP                      0x00F00000U        /*!<TRP[2:0] bits (Row precharge delay) */
-#define  FMC_SDTR1_TRP_0                    0x00100000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRP_1                    0x00200000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRP_2                    0x00400000U        /*!<Bit 2 */
-#define  FMC_SDTR1_TRCD                     0x0F000000U        /*!<TRP[2:0] bits (Row to column delay) */
-#define  FMC_SDTR1_TRCD_0                   0x01000000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRCD_1                   0x02000000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRCD_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for FMC_SDTR2 register  ******************/
-#define  FMC_SDTR2_TMRD                     0x0000000FU        /*!<TMRD[3:0] bits (Load mode register to active) */
-#define  FMC_SDTR2_TMRD_0                   0x00000001U        /*!<Bit 0 */
-#define  FMC_SDTR2_TMRD_1                   0x00000002U        /*!<Bit 1 */
-#define  FMC_SDTR2_TMRD_2                   0x00000004U        /*!<Bit 2 */
-#define  FMC_SDTR2_TMRD_3                   0x00000008U        /*!<Bit 3 */
-#define  FMC_SDTR2_TXSR                     0x000000F0U        /*!<TXSR[3:0] bits (Exit self refresh) */
-#define  FMC_SDTR2_TXSR_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDTR2_TXSR_1                   0x00000020U        /*!<Bit 1 */
-#define  FMC_SDTR2_TXSR_2                   0x00000040U        /*!<Bit 2 */
-#define  FMC_SDTR2_TXSR_3                   0x00000080U        /*!<Bit 3 */
-#define  FMC_SDTR2_TRAS                     0x00000F00U        /*!<TRAS[3:0] bits (Self refresh time) */
-#define  FMC_SDTR2_TRAS_0                   0x00000100U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRAS_1                   0x00000200U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRAS_2                   0x00000400U        /*!<Bit 2 */
-#define  FMC_SDTR2_TRAS_3                   0x00000800U        /*!<Bit 3 */
-#define  FMC_SDTR2_TRC                      0x0000F000U        /*!<TRC[2:0] bits (Row cycle delay) */
-#define  FMC_SDTR2_TRC_0                    0x00001000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRC_1                    0x00002000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRC_2                    0x00004000U        /*!<Bit 2 */
-#define  FMC_SDTR2_TWR                      0x000F0000U        /*!<TRC[2:0] bits (Write recovery delay) */
-#define  FMC_SDTR2_TWR_0                    0x00010000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TWR_1                    0x00020000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TWR_2                    0x00040000U        /*!<Bit 2 */
-#define  FMC_SDTR2_TRP                      0x00F00000U        /*!<TRP[2:0] bits (Row precharge delay) */
-#define  FMC_SDTR2_TRP_0                    0x00100000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRP_1                    0x00200000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRP_2                    0x00400000U        /*!<Bit 2 */
-#define  FMC_SDTR2_TRCD                     0x0F000000U        /*!<TRP[2:0] bits (Row to column delay) */
-#define  FMC_SDTR2_TRCD_0                   0x01000000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRCD_1                   0x02000000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRCD_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for FMC_SDCMR register  ******************/
-#define  FMC_SDCMR_MODE                     0x00000007U        /*!<MODE[2:0] bits (Command mode) */
-#define  FMC_SDCMR_MODE_0                   0x00000001U        /*!<Bit 0 */
-#define  FMC_SDCMR_MODE_1                   0x00000002U        /*!<Bit 1 */
-#define  FMC_SDCMR_MODE_2                   0x00000003U        /*!<Bit 2 */
-#define  FMC_SDCMR_CTB2                     0x00000008U        /*!<Command target 2 */
-#define  FMC_SDCMR_CTB1                     0x00000010U        /*!<Command target 1 */
-#define  FMC_SDCMR_NRFS                     0x000001E0U        /*!<NRFS[3:0] bits (Number of auto-refresh) */
-#define  FMC_SDCMR_NRFS_0                   0x00000020U        /*!<Bit 0 */
-#define  FMC_SDCMR_NRFS_1                   0x00000040U        /*!<Bit 1 */
-#define  FMC_SDCMR_NRFS_2                   0x00000080U        /*!<Bit 2 */
-#define  FMC_SDCMR_NRFS_3                   0x00000100U        /*!<Bit 3 */
-#define  FMC_SDCMR_MRD                      0x003FFE00U        /*!<MRD[12:0] bits (Mode register definition) */
-
-/******************  Bit definition for FMC_SDRTR register  ******************/
-#define  FMC_SDRTR_CRE                      0x00000001U        /*!<Clear refresh error flag */
-#define  FMC_SDRTR_COUNT                    0x00003FFEU        /*!<COUNT[12:0] bits (Refresh timer count) */
-#define  FMC_SDRTR_REIE                     0x00004000U        /*!<RES interupt enable */
-
-/******************  Bit definition for FMC_SDSR register  ******************/
-#define  FMC_SDSR_RE                        0x00000001U        /*!<Refresh error flag */
-#define  FMC_SDSR_MODES1                    0x00000006U        /*!<MODES1[1:0]bits (Status mode for bank 1) */
-#define  FMC_SDSR_MODES1_0                  0x00000002U        /*!<Bit 0 */
-#define  FMC_SDSR_MODES1_1                  0x00000004U        /*!<Bit 1 */
-#define  FMC_SDSR_MODES2                    0x00000018U        /*!<MODES2[1:0]bits (Status mode for bank 2) */
-#define  FMC_SDSR_MODES2_0                  0x00000008U        /*!<Bit 0 */
-#define  FMC_SDSR_MODES2_1                  0x00000010U        /*!<Bit 1 */
-#define  FMC_SDSR_BUSY                      0x00000020U        /*!<Busy status */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    0x00000003U
-#define GPIO_MODER_MODER0_0                  0x00000001U
-#define GPIO_MODER_MODER0_1                  0x00000002U
-#define GPIO_MODER_MODER1                    0x0000000CU
-#define GPIO_MODER_MODER1_0                  0x00000004U
-#define GPIO_MODER_MODER1_1                  0x00000008U
-#define GPIO_MODER_MODER2                    0x00000030U
-#define GPIO_MODER_MODER2_0                  0x00000010U
-#define GPIO_MODER_MODER2_1                  0x00000020U
-#define GPIO_MODER_MODER3                    0x000000C0U
-#define GPIO_MODER_MODER3_0                  0x00000040U
-#define GPIO_MODER_MODER3_1                  0x00000080U
-#define GPIO_MODER_MODER4                    0x00000300U
-#define GPIO_MODER_MODER4_0                  0x00000100U
-#define GPIO_MODER_MODER4_1                  0x00000200U
-#define GPIO_MODER_MODER5                    0x00000C00U
-#define GPIO_MODER_MODER5_0                  0x00000400U
-#define GPIO_MODER_MODER5_1                  0x00000800U
-#define GPIO_MODER_MODER6                    0x00003000U
-#define GPIO_MODER_MODER6_0                  0x00001000U
-#define GPIO_MODER_MODER6_1                  0x00002000U
-#define GPIO_MODER_MODER7                    0x0000C000U
-#define GPIO_MODER_MODER7_0                  0x00004000U
-#define GPIO_MODER_MODER7_1                  0x00008000U
-#define GPIO_MODER_MODER8                    0x00030000U
-#define GPIO_MODER_MODER8_0                  0x00010000U
-#define GPIO_MODER_MODER8_1                  0x00020000U
-#define GPIO_MODER_MODER9                    0x000C0000U
-#define GPIO_MODER_MODER9_0                  0x00040000U
-#define GPIO_MODER_MODER9_1                  0x00080000U
-#define GPIO_MODER_MODER10                   0x00300000U
-#define GPIO_MODER_MODER10_0                 0x00100000U
-#define GPIO_MODER_MODER10_1                 0x00200000U
-#define GPIO_MODER_MODER11                   0x00C00000U
-#define GPIO_MODER_MODER11_0                 0x00400000U
-#define GPIO_MODER_MODER11_1                 0x00800000U
-#define GPIO_MODER_MODER12                   0x03000000U
-#define GPIO_MODER_MODER12_0                 0x01000000U
-#define GPIO_MODER_MODER12_1                 0x02000000U
-#define GPIO_MODER_MODER13                   0x0C000000U
-#define GPIO_MODER_MODER13_0                 0x04000000U
-#define GPIO_MODER_MODER13_1                 0x08000000U
-#define GPIO_MODER_MODER14                   0x30000000U
-#define GPIO_MODER_MODER14_0                 0x10000000U
-#define GPIO_MODER_MODER14_1                 0x20000000U
-#define GPIO_MODER_MODER15                   0xC0000000U
-#define GPIO_MODER_MODER15_0                 0x40000000U
-#define GPIO_MODER_MODER15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     0x00000001U
-#define GPIO_OTYPER_OT_1                     0x00000002U
-#define GPIO_OTYPER_OT_2                     0x00000004U
-#define GPIO_OTYPER_OT_3                     0x00000008U
-#define GPIO_OTYPER_OT_4                     0x00000010U
-#define GPIO_OTYPER_OT_5                     0x00000020U
-#define GPIO_OTYPER_OT_6                     0x00000040U
-#define GPIO_OTYPER_OT_7                     0x00000080U
-#define GPIO_OTYPER_OT_8                     0x00000100U
-#define GPIO_OTYPER_OT_9                     0x00000200U
-#define GPIO_OTYPER_OT_10                    0x00000400U
-#define GPIO_OTYPER_OT_11                    0x00000800U
-#define GPIO_OTYPER_OT_12                    0x00001000U
-#define GPIO_OTYPER_OT_13                    0x00002000U
-#define GPIO_OTYPER_OT_14                    0x00004000U
-#define GPIO_OTYPER_OT_15                    0x00008000U
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
-#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
-#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
-#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
-#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
-#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
-#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
-#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
-#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
-#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
-#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
-#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
-#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
-#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
-#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
-#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
-#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
-#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
-#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
-#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
-#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
-#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
-#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
-#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
-#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
-#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
-#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
-#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
-#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
-#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
-#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
-#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
-#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
-#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
-#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
-#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
-#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
-#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
-#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
-#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
-#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
-#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
-#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
-#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
-#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
-#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
-#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
-#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    0x00000003U
-#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
-#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
-#define GPIO_PUPDR_PUPDR1                    0x0000000CU
-#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
-#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
-#define GPIO_PUPDR_PUPDR2                    0x00000030U
-#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
-#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
-#define GPIO_PUPDR_PUPDR3                    0x000000C0U
-#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
-#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
-#define GPIO_PUPDR_PUPDR4                    0x00000300U
-#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
-#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
-#define GPIO_PUPDR_PUPDR5                    0x00000C00U
-#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
-#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
-#define GPIO_PUPDR_PUPDR6                    0x00003000U
-#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
-#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
-#define GPIO_PUPDR_PUPDR7                    0x0000C000U
-#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
-#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
-#define GPIO_PUPDR_PUPDR8                    0x00030000U
-#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
-#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
-#define GPIO_PUPDR_PUPDR9                    0x000C0000U
-#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
-#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
-#define GPIO_PUPDR_PUPDR10                   0x00300000U
-#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
-#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
-#define GPIO_PUPDR_PUPDR11                   0x00C00000U
-#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
-#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
-#define GPIO_PUPDR_PUPDR12                   0x03000000U
-#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
-#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
-#define GPIO_PUPDR_PUPDR13                   0x0C000000U
-#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
-#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
-#define GPIO_PUPDR_PUPDR14                   0x30000000U
-#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
-#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
-#define GPIO_PUPDR_PUPDR15                   0xC0000000U
-#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
-#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       0x00000001U
-#define GPIO_IDR_IDR_1                       0x00000002U
-#define GPIO_IDR_IDR_2                       0x00000004U
-#define GPIO_IDR_IDR_3                       0x00000008U
-#define GPIO_IDR_IDR_4                       0x00000010U
-#define GPIO_IDR_IDR_5                       0x00000020U
-#define GPIO_IDR_IDR_6                       0x00000040U
-#define GPIO_IDR_IDR_7                       0x00000080U
-#define GPIO_IDR_IDR_8                       0x00000100U
-#define GPIO_IDR_IDR_9                       0x00000200U
-#define GPIO_IDR_IDR_10                      0x00000400U
-#define GPIO_IDR_IDR_11                      0x00000800U
-#define GPIO_IDR_IDR_12                      0x00001000U
-#define GPIO_IDR_IDR_13                      0x00002000U
-#define GPIO_IDR_IDR_14                      0x00004000U
-#define GPIO_IDR_IDR_15                      0x00008000U
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       0x00000001U
-#define GPIO_ODR_ODR_1                       0x00000002U
-#define GPIO_ODR_ODR_2                       0x00000004U
-#define GPIO_ODR_ODR_3                       0x00000008U
-#define GPIO_ODR_ODR_4                       0x00000010U
-#define GPIO_ODR_ODR_5                       0x00000020U
-#define GPIO_ODR_ODR_6                       0x00000040U
-#define GPIO_ODR_ODR_7                       0x00000080U
-#define GPIO_ODR_ODR_8                       0x00000100U
-#define GPIO_ODR_ODR_9                       0x00000200U
-#define GPIO_ODR_ODR_10                      0x00000400U
-#define GPIO_ODR_ODR_11                      0x00000800U
-#define GPIO_ODR_ODR_12                      0x00001000U
-#define GPIO_ODR_ODR_13                      0x00002000U
-#define GPIO_ODR_ODR_14                      0x00004000U
-#define GPIO_ODR_ODR_15                      0x00008000U
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       0x00000001U
-#define GPIO_BSRR_BS_1                       0x00000002U
-#define GPIO_BSRR_BS_2                       0x00000004U
-#define GPIO_BSRR_BS_3                       0x00000008U
-#define GPIO_BSRR_BS_4                       0x00000010U
-#define GPIO_BSRR_BS_5                       0x00000020U
-#define GPIO_BSRR_BS_6                       0x00000040U
-#define GPIO_BSRR_BS_7                       0x00000080U
-#define GPIO_BSRR_BS_8                       0x00000100U
-#define GPIO_BSRR_BS_9                       0x00000200U
-#define GPIO_BSRR_BS_10                      0x00000400U
-#define GPIO_BSRR_BS_11                      0x00000800U
-#define GPIO_BSRR_BS_12                      0x00001000U
-#define GPIO_BSRR_BS_13                      0x00002000U
-#define GPIO_BSRR_BS_14                      0x00004000U
-#define GPIO_BSRR_BS_15                      0x00008000U
-#define GPIO_BSRR_BR_0                       0x00010000U
-#define GPIO_BSRR_BR_1                       0x00020000U
-#define GPIO_BSRR_BR_2                       0x00040000U
-#define GPIO_BSRR_BR_3                       0x00080000U
-#define GPIO_BSRR_BR_4                       0x00100000U
-#define GPIO_BSRR_BR_5                       0x00200000U
-#define GPIO_BSRR_BR_6                       0x00400000U
-#define GPIO_BSRR_BR_7                       0x00800000U
-#define GPIO_BSRR_BR_8                       0x01000000U
-#define GPIO_BSRR_BR_9                       0x02000000U
-#define GPIO_BSRR_BR_10                      0x04000000U
-#define GPIO_BSRR_BR_11                      0x08000000U
-#define GPIO_BSRR_BR_12                      0x10000000U
-#define GPIO_BSRR_BR_13                      0x20000000U
-#define GPIO_BSRR_BR_14                      0x40000000U
-#define GPIO_BSRR_BR_15                      0x80000000U
-
-/****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0                       0x00000001U
-#define GPIO_LCKR_LCK1                       0x00000002U
-#define GPIO_LCKR_LCK2                       0x00000004U
-#define GPIO_LCKR_LCK3                       0x00000008U
-#define GPIO_LCKR_LCK4                       0x00000010U
-#define GPIO_LCKR_LCK5                       0x00000020U
-#define GPIO_LCKR_LCK6                       0x00000040U
-#define GPIO_LCKR_LCK7                       0x00000080U
-#define GPIO_LCKR_LCK8                       0x00000100U
-#define GPIO_LCKR_LCK9                       0x00000200U
-#define GPIO_LCKR_LCK10                      0x00000400U
-#define GPIO_LCKR_LCK11                      0x00000800U
-#define GPIO_LCKR_LCK12                      0x00001000U
-#define GPIO_LCKR_LCK13                      0x00002000U
-#define GPIO_LCKR_LCK14                      0x00004000U
-#define GPIO_LCKR_LCK15                      0x00008000U
-#define GPIO_LCKR_LCKK                       0x00010000U
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Inter-integrated Circuit Interface (I2C)              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define  I2C_CR1_PE                          0x00000001U        /*!< Peripheral enable                   */
-#define  I2C_CR1_TXIE                        0x00000002U        /*!< TX interrupt enable                 */
-#define  I2C_CR1_RXIE                        0x00000004U        /*!< RX interrupt enable                 */
-#define  I2C_CR1_ADDRIE                      0x00000008U        /*!< Address match interrupt enable      */
-#define  I2C_CR1_NACKIE                      0x00000010U        /*!< NACK received interrupt enable      */
-#define  I2C_CR1_STOPIE                      0x00000020U        /*!< STOP detection interrupt enable     */
-#define  I2C_CR1_TCIE                        0x00000040U        /*!< Transfer complete interrupt enable  */
-#define  I2C_CR1_ERRIE                       0x00000080U        /*!< Errors interrupt enable             */
-#define  I2C_CR1_DNF                         0x00000F00U        /*!< Digital noise filter                */
-#define  I2C_CR1_ANFOFF                      0x00001000U        /*!< Analog noise filter OFF             */
-#define  I2C_CR1_TXDMAEN                     0x00004000U        /*!< DMA transmission requests enable    */
-#define  I2C_CR1_RXDMAEN                     0x00008000U        /*!< DMA reception requests enable       */
-#define  I2C_CR1_SBC                         0x00010000U        /*!< Slave byte control                  */
-#define  I2C_CR1_NOSTRETCH                   0x00020000U        /*!< Clock stretching disable            */
-#define  I2C_CR1_GCEN                        0x00080000U        /*!< General call enable                 */
-#define  I2C_CR1_SMBHEN                      0x00100000U        /*!< SMBus host address enable           */
-#define  I2C_CR1_SMBDEN                      0x00200000U        /*!< SMBus device default address enable */
-#define  I2C_CR1_ALERTEN                     0x00400000U        /*!< SMBus alert enable                  */
-#define  I2C_CR1_PECEN                       0x00800000U        /*!< PEC enable                          */
-
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_SADD                        0x000003FFU        /*!< Slave address (master mode)                             */
-#define  I2C_CR2_RD_WRN                      0x00000400U        /*!< Transfer direction (master mode)                        */
-#define  I2C_CR2_ADD10                       0x00000800U        /*!< 10-bit addressing mode (master mode)                    */
-#define  I2C_CR2_HEAD10R                     0x00001000U        /*!< 10-bit address header only read direction (master mode) */
-#define  I2C_CR2_START                       0x00002000U        /*!< START generation                                        */
-#define  I2C_CR2_STOP                        0x00004000U        /*!< STOP generation (master mode)                           */
-#define  I2C_CR2_NACK                        0x00008000U        /*!< NACK generation (slave mode)                            */
-#define  I2C_CR2_NBYTES                      0x00FF0000U        /*!< Number of bytes                                         */
-#define  I2C_CR2_RELOAD                      0x01000000U        /*!< NBYTES reload mode                                      */
-#define  I2C_CR2_AUTOEND                     0x02000000U        /*!< Automatic end mode (master mode)                        */
-#define  I2C_CR2_PECBYTE                     0x04000000U        /*!< Packet error checking byte                              */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define  I2C_OAR1_OA1                        0x000003FFU        /*!< Interface own address 1   */
-#define  I2C_OAR1_OA1MODE                    0x00000400U        /*!< Own address 1 10-bit mode */
-#define  I2C_OAR1_OA1EN                      0x00008000U        /*!< Own address 1 enable      */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define  I2C_OAR2_OA2                        0x000000FEU        /*!< Interface own address 2 */
-#define  I2C_OAR2_OA2MSK                     0x00000700U        /*!< Own address 2 masks     */
-#define  I2C_OAR2_OA2NOMASK                  0x00000000U        /*!< No mask */
-#define  I2C_OAR2_OA2MASK01                  0x00000100U        /*!< OA2[1] is masked, Only OA2[7:2] are compared */
-#define  I2C_OAR2_OA2MASK02                  0x00000200U        /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
-#define  I2C_OAR2_OA2MASK03                  0x00000300U        /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
-#define  I2C_OAR2_OA2MASK04                  0x00000400U        /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
-#define  I2C_OAR2_OA2MASK05                  0x00000500U        /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
-#define  I2C_OAR2_OA2MASK06                  0x00000600U        /*!< OA2[6:1] is masked, Only OA2[7] are compared */
-#define  I2C_OAR2_OA2MASK07                  0x00000700U        /*!< OA2[7:1] is masked, No comparison is done */
-#define  I2C_OAR2_OA2EN                      0x00008000U        /*!< Own address 2 enable    */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define  I2C_TIMINGR_SCLL                    0x000000FFU        /*!< SCL low period (master mode)  */
-#define  I2C_TIMINGR_SCLH                    0x0000FF00U        /*!< SCL high period (master mode) */
-#define  I2C_TIMINGR_SDADEL                  0x000F0000U        /*!< Data hold time                */
-#define  I2C_TIMINGR_SCLDEL                  0x00F00000U        /*!< Data setup time               */
-#define  I2C_TIMINGR_PRESC                   0xF0000000U        /*!< Timings prescaler             */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define  I2C_TIMEOUTR_TIMEOUTA               0x00000FFFU        /*!< Bus timeout A                 */
-#define  I2C_TIMEOUTR_TIDLE                  0x00001000U        /*!< Idle clock timeout detection  */
-#define  I2C_TIMEOUTR_TIMOUTEN               0x00008000U        /*!< Clock timeout enable          */
-#define  I2C_TIMEOUTR_TIMEOUTB               0x0FFF0000U        /*!< Bus timeout B                 */
-#define  I2C_TIMEOUTR_TEXTEN                 0x80000000U        /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define  I2C_ISR_TXE                         0x00000001U        /*!< Transmit data register empty    */
-#define  I2C_ISR_TXIS                        0x00000002U        /*!< Transmit interrupt status       */
-#define  I2C_ISR_RXNE                        0x00000004U        /*!< Receive data register not empty */
-#define  I2C_ISR_ADDR                        0x00000008U        /*!< Address matched (slave mode)    */
-#define  I2C_ISR_NACKF                       0x00000010U        /*!< NACK received flag              */
-#define  I2C_ISR_STOPF                       0x00000020U        /*!< STOP detection flag             */
-#define  I2C_ISR_TC                          0x00000040U        /*!< Transfer complete (master mode) */
-#define  I2C_ISR_TCR                         0x00000080U        /*!< Transfer complete reload        */
-#define  I2C_ISR_BERR                        0x00000100U        /*!< Bus error                       */
-#define  I2C_ISR_ARLO                        0x00000200U        /*!< Arbitration lost                */
-#define  I2C_ISR_OVR                         0x00000400U        /*!< Overrun/Underrun                */
-#define  I2C_ISR_PECERR                      0x00000800U        /*!< PEC error in reception          */
-#define  I2C_ISR_TIMEOUT                     0x00001000U        /*!< Timeout or Tlow detection flag  */
-#define  I2C_ISR_ALERT                       0x00002000U        /*!< SMBus alert                     */
-#define  I2C_ISR_BUSY                        0x00008000U        /*!< Bus busy                        */
-#define  I2C_ISR_DIR                         0x00010000U        /*!< Transfer direction (slave mode) */
-#define  I2C_ISR_ADDCODE                     0x00FE0000U        /*!< Address match code (slave mode) */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define  I2C_ICR_ADDRCF                      0x00000008U        /*!< Address matched clear flag      */
-#define  I2C_ICR_NACKCF                      0x00000010U        /*!< NACK clear flag                 */
-#define  I2C_ICR_STOPCF                      0x00000020U        /*!< STOP detection clear flag       */
-#define  I2C_ICR_BERRCF                      0x00000100U        /*!< Bus error clear flag            */
-#define  I2C_ICR_ARLOCF                      0x00000200U        /*!< Arbitration lost clear flag     */
-#define  I2C_ICR_OVRCF                       0x00000400U        /*!< Overrun/Underrun clear flag     */
-#define  I2C_ICR_PECCF                       0x00000800U        /*!< PAC error clear flag            */
-#define  I2C_ICR_TIMOUTCF                    0x00001000U        /*!< Timeout clear flag              */
-#define  I2C_ICR_ALERTCF                     0x00002000U        /*!< Alert clear flag                */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define  I2C_PECR_PEC                        0x000000FFU        /*!< PEC register        */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define  I2C_RXDR_RXDATA                     0x000000FFU        /*!< 8-bit receive data  */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define  I2C_TXDR_TXDATA                     0x000000FFU        /*!< 8-bit transmit data */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Independent WATCHDOG                             */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         0x01U               /*!< Watchdog prescaler value update */
-#define  IWDG_SR_RVU                         0x02U               /*!< Watchdog counter reload value update */
-#define  IWDG_SR_WVU                         0x04U               /*!< Watchdog counter window value update */
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_WINR_WIN                       0x0FFFU             /*!< Watchdog counter window value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      LCD-TFT Display Controller (LTDC)                     */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for LTDC_SSCR register  *****************/
-
-#define LTDC_SSCR_VSH                       0x000007FFU              /*!< Vertical Synchronization Height  */
-#define LTDC_SSCR_HSW                       0x0FFF0000U              /*!< Horizontal Synchronization Width */
-
-/********************  Bit definition for LTDC_BPCR register  *****************/
-
-#define LTDC_BPCR_AVBP                      0x000007FFU              /*!< Accumulated Vertical Back Porch   */
-#define LTDC_BPCR_AHBP                      0x0FFF0000U              /*!< Accumulated Horizontal Back Porch */
-
-/********************  Bit definition for LTDC_AWCR register  *****************/
-
-#define LTDC_AWCR_AAH                       0x000007FFU              /*!< Accumulated Active heigh */
-#define LTDC_AWCR_AAW                       0x0FFF0000U              /*!< Accumulated Active Width */
-
-/********************  Bit definition for LTDC_TWCR register  *****************/
-
-#define LTDC_TWCR_TOTALH                    0x000007FFU              /*!< Total Heigh */
-#define LTDC_TWCR_TOTALW                    0x0FFF0000U              /*!< Total Width */
-
-/********************  Bit definition for LTDC_GCR register  ******************/
-
-#define LTDC_GCR_LTDCEN                     0x00000001U              /*!< LCD-TFT controller enable bit       */
-#define LTDC_GCR_DBW                        0x00000070U              /*!< Dither Blue Width                   */
-#define LTDC_GCR_DGW                        0x00000700U              /*!< Dither Green Width                  */
-#define LTDC_GCR_DRW                        0x00007000U              /*!< Dither Red Width                    */
-#define LTDC_GCR_DEN                        0x00010000U              /*!< Dither Enable                       */
-#define LTDC_GCR_PCPOL                      0x10000000U              /*!< Pixel Clock Polarity                */
-#define LTDC_GCR_DEPOL                      0x20000000U              /*!< Data Enable Polarity                */
-#define LTDC_GCR_VSPOL                      0x40000000U              /*!< Vertical Synchronization Polarity   */
-#define LTDC_GCR_HSPOL                      0x80000000U              /*!< Horizontal Synchronization Polarity */
-
-
-/********************  Bit definition for LTDC_SRCR register  *****************/
-
-#define LTDC_SRCR_IMR                      0x00000001U               /*!< Immediate Reload         */
-#define LTDC_SRCR_VBR                      0x00000002U               /*!< Vertical Blanking Reload */
-
-/********************  Bit definition for LTDC_BCCR register  *****************/
-
-#define LTDC_BCCR_BCBLUE                    0x000000FFU              /*!< Background Blue value  */
-#define LTDC_BCCR_BCGREEN                   0x0000FF00U              /*!< Background Green value */
-#define LTDC_BCCR_BCRED                     0x00FF0000U              /*!< Background Red value   */
-
-/********************  Bit definition for LTDC_IER register  ******************/
-
-#define LTDC_IER_LIE                        0x00000001U              /*!< Line Interrupt Enable            */
-#define LTDC_IER_FUIE                       0x00000002U              /*!< FIFO Underrun Interrupt Enable   */
-#define LTDC_IER_TERRIE                     0x00000004U              /*!< Transfer Error Interrupt Enable  */
-#define LTDC_IER_RRIE                       0x00000008U              /*!< Register Reload interrupt enable */
-
-/********************  Bit definition for LTDC_ISR register  ******************/
-
-#define LTDC_ISR_LIF                        0x00000001U              /*!< Line Interrupt Flag */
-#define LTDC_ISR_FUIF                       0x00000002U              /*!< FIFO Underrun Interrupt Flag */
-#define LTDC_ISR_TERRIF                     0x00000004U              /*!< Transfer Error Interrupt Flag */
-#define LTDC_ISR_RRIF                       0x00000008U              /*!< Register Reload interrupt Flag */
-
-/********************  Bit definition for LTDC_ICR register  ******************/
-
-#define LTDC_ICR_CLIF                       0x00000001U              /*!< Clears the Line Interrupt Flag */
-#define LTDC_ICR_CFUIF                      0x00000002U              /*!< Clears the FIFO Underrun Interrupt Flag */
-#define LTDC_ICR_CTERRIF                    0x00000004U              /*!< Clears the Transfer Error Interrupt Flag */
-#define LTDC_ICR_CRRIF                      0x00000008U              /*!< Clears Register Reload interrupt Flag */
-
-/********************  Bit definition for LTDC_LIPCR register  ****************/
-
-#define LTDC_LIPCR_LIPOS                    0x000007FFU              /*!< Line Interrupt Position */
-
-/********************  Bit definition for LTDC_CPSR register  *****************/
-
-#define LTDC_CPSR_CYPOS                     0x0000FFFFU              /*!< Current Y Position */
-#define LTDC_CPSR_CXPOS                     0xFFFF0000U              /*!< Current X Position */
-
-/********************  Bit definition for LTDC_CDSR register  *****************/
-
-#define LTDC_CDSR_VDES                      0x00000001U              /*!< Vertical Data Enable Status       */
-#define LTDC_CDSR_HDES                      0x00000002U              /*!< Horizontal Data Enable Status     */
-#define LTDC_CDSR_VSYNCS                    0x00000004U              /*!< Vertical Synchronization Status   */
-#define LTDC_CDSR_HSYNCS                    0x00000008U              /*!< Horizontal Synchronization Status */
-
-/********************  Bit definition for LTDC_LxCR register  *****************/
-
-#define LTDC_LxCR_LEN                       0x00000001U              /*!< Layer Enable              */
-#define LTDC_LxCR_COLKEN                    0x00000002U              /*!< Color Keying Enable       */
-#define LTDC_LxCR_CLUTEN                    0x00000010U              /*!< Color Lockup Table Enable */
-
-/********************  Bit definition for LTDC_LxWHPCR register  **************/
-
-#define LTDC_LxWHPCR_WHSTPOS                0x00000FFFU              /*!< Window Horizontal Start Position */
-#define LTDC_LxWHPCR_WHSPPOS                0xFFFF0000U              /*!< Window Horizontal Stop Position  */
-
-/********************  Bit definition for LTDC_LxWVPCR register  **************/
-
-#define LTDC_LxWVPCR_WVSTPOS                0x00000FFFU              /*!< Window Vertical Start Position */
-#define LTDC_LxWVPCR_WVSPPOS                0xFFFF0000U              /*!< Window Vertical Stop Position  */
-
-/********************  Bit definition for LTDC_LxCKCR register  ***************/
-
-#define LTDC_LxCKCR_CKBLUE                  0x000000FFU              /*!< Color Key Blue value  */
-#define LTDC_LxCKCR_CKGREEN                 0x0000FF00U              /*!< Color Key Green value */
-#define LTDC_LxCKCR_CKRED                   0x00FF0000U              /*!< Color Key Red value   */
-
-/********************  Bit definition for LTDC_LxPFCR register  ***************/
-
-#define LTDC_LxPFCR_PF                      0x00000007U              /*!< Pixel Format */
-
-/********************  Bit definition for LTDC_LxCACR register  ***************/
-
-#define LTDC_LxCACR_CONSTA                  0x000000FFU              /*!< Constant Alpha */
-
-/********************  Bit definition for LTDC_LxDCCR register  ***************/
-
-#define LTDC_LxDCCR_DCBLUE                  0x000000FFU              /*!< Default Color Blue  */
-#define LTDC_LxDCCR_DCGREEN                 0x0000FF00U              /*!< Default Color Green */
-#define LTDC_LxDCCR_DCRED                   0x00FF0000U              /*!< Default Color Red   */
-#define LTDC_LxDCCR_DCALPHA                 0xFF000000U              /*!< Default Color Alpha */
-
-/********************  Bit definition for LTDC_LxBFCR register  ***************/
-
-#define LTDC_LxBFCR_BF2                     0x00000007U              /*!< Blending Factor 2 */
-#define LTDC_LxBFCR_BF1                     0x00000700U              /*!< Blending Factor 1 */
-
-/********************  Bit definition for LTDC_LxCFBAR register  **************/
-
-#define LTDC_LxCFBAR_CFBADD                 0xFFFFFFFFU              /*!< Color Frame Buffer Start Address */
-
-/********************  Bit definition for LTDC_LxCFBLR register  **************/
-
-#define LTDC_LxCFBLR_CFBLL                  0x00001FFFU              /*!< Color Frame Buffer Line Length    */
-#define LTDC_LxCFBLR_CFBP                   0x1FFF0000U              /*!< Color Frame Buffer Pitch in bytes */
-
-/********************  Bit definition for LTDC_LxCFBLNR register  *************/
-
-#define LTDC_LxCFBLNR_CFBLNBR               0x000007FFU              /*!< Frame Buffer Line Number */
-
-/********************  Bit definition for LTDC_LxCLUTWR register  *************/
-
-#define LTDC_LxCLUTWR_BLUE                  0x000000FFU              /*!< Blue value   */
-#define LTDC_LxCLUTWR_GREEN                 0x0000FF00U              /*!< Green value  */
-#define LTDC_LxCLUTWR_RED                   0x00FF0000U              /*!< Red value    */
-#define LTDC_LxCLUTWR_CLUTADD               0xFF000000U              /*!< CLUT address */
-
-/******************************************************************************/
-/*                                                                            */
-/*                             Power Control                                  */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for PWR_CR1 register  ********************/
-#define  PWR_CR1_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
-#define  PWR_CR1_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
-#define  PWR_CR1_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
-#define  PWR_CR1_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
-#define  PWR_CR1_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR1_PLS_0                        0x00000020U     /*!< Bit 0 */
-#define  PWR_CR1_PLS_1                        0x00000040U     /*!< Bit 1 */
-#define  PWR_CR1_PLS_2                        0x00000080U     /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define  PWR_CR1_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
-#define  PWR_CR1_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
-#define  PWR_CR1_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
-#define  PWR_CR1_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
-#define  PWR_CR1_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
-#define  PWR_CR1_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
-#define  PWR_CR1_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
-#define  PWR_CR1_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
-#define  PWR_CR1_DBP                          0x00000100U     /*!< Disable Backup Domain write protection                     */
-#define  PWR_CR1_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                              */
-#define  PWR_CR1_LPUDS                        0x00000400U     /*!< Low-power regulator in deepsleep under-drive mode          */
-#define  PWR_CR1_MRUDS                        0x00000800U     /*!< Main regulator in deepsleep under-drive mode               */
-#define  PWR_CR1_ADCDC1                       0x00002000U     /*!< Refer to AN4073 on how to use this bit */
-#define  PWR_CR1_VOS                          0x0000C000U     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
-#define  PWR_CR1_VOS_0                        0x00004000U     /*!< Bit 0 */
-#define  PWR_CR1_VOS_1                        0x00008000U     /*!< Bit 1 */
-#define  PWR_CR1_ODEN                         0x00010000U     /*!< Over Drive enable                   */
-#define  PWR_CR1_ODSWEN                       0x00020000U     /*!< Over Drive switch enabled           */
-#define  PWR_CR1_UDEN                         0x000C0000U     /*!< Under Drive enable in stop mode     */
-#define  PWR_CR1_UDEN_0                       0x00040000U     /*!< Bit 0                               */
-#define  PWR_CR1_UDEN_1                       0x00080000U     /*!< Bit 1                               */
-
-/*******************  Bit definition for PWR_CSR1 register  ********************/
-#define  PWR_CSR1_WUIF                        0x00000001U     /*!< Wake up internal Flag                            */
-#define  PWR_CSR1_SBF                         0x00000002U     /*!< Standby Flag                                     */
-#define  PWR_CSR1_PVDO                        0x00000004U     /*!< PVD Output                                       */
-#define  PWR_CSR1_BRR                         0x00000008U     /*!< Backup regulator ready                           */
-#define  PWR_CSR1_EIWUP                       0x00000100U     /*!< Enable internal wakeup                           */
-#define  PWR_CSR1_BRE                         0x00000200U     /*!< Backup regulator enable                          */
-#define  PWR_CSR1_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
-#define  PWR_CSR1_ODRDY                       0x00010000U     /*!< Over Drive generator ready                       */
-#define  PWR_CSR1_ODSWRDY                     0x00020000U     /*!< Over Drive Switch ready                          */
-#define  PWR_CSR1_UDRDY                       0x000C0000U     /*!< Under Drive ready                                */
-
-
-/********************  Bit definition for PWR_CR2 register  ********************/
-#define  PWR_CR2_CWUPF1                         0x00000001U     /*!< Clear Wakeup Pin Flag for PA0      */
-#define  PWR_CR2_CWUPF2                         0x00000002U     /*!< Clear Wakeup Pin Flag for PA2      */
-#define  PWR_CR2_CWUPF3                         0x00000004U     /*!< Clear Wakeup Pin Flag for PC1      */
-#define  PWR_CR2_CWUPF4                         0x00000008U     /*!< Clear Wakeup Pin Flag for PC13     */
-#define  PWR_CR2_CWUPF5                         0x00000010U     /*!< Clear Wakeup Pin Flag for PI8      */
-#define  PWR_CR2_CWUPF6                         0x00000020U     /*!< Clear Wakeup Pin Flag for PI11     */
-#define  PWR_CR2_WUPP1                          0x00000100U     /*!< Wakeup Pin Polarity bit for PA0    */
-#define  PWR_CR2_WUPP2                          0x00000200U     /*!< Wakeup Pin Polarity bit for PA2    */
-#define  PWR_CR2_WUPP3                          0x00000400U     /*!< Wakeup Pin Polarity bit for PC1    */
-#define  PWR_CR2_WUPP4                          0x00000800U     /*!< Wakeup Pin Polarity bit for PC13   */
-#define  PWR_CR2_WUPP5                          0x00001000U     /*!< Wakeup Pin Polarity bit for PI8    */
-#define  PWR_CR2_WUPP6                          0x00002000U     /*!< Wakeup Pin Polarity bit for PI11   */
-
-/*******************  Bit definition for PWR_CSR2 register  ********************/
-#define  PWR_CSR2_WUPF1                         0x00000001U     /*!< Wakeup Pin Flag for PA0            */
-#define  PWR_CSR2_WUPF2                         0x00000002U     /*!< Wakeup Pin Flag for PA2            */
-#define  PWR_CSR2_WUPF3                         0x00000004U     /*!< Wakeup Pin Flag for PC1            */
-#define  PWR_CSR2_WUPF4                         0x00000008U     /*!< Wakeup Pin Flag for PC13           */
-#define  PWR_CSR2_WUPF5                         0x00000010U     /*!< Wakeup Pin Flag for PI8            */
-#define  PWR_CSR2_WUPF6                         0x00000020U     /*!< Wakeup Pin Flag for PI11           */
-#define  PWR_CSR2_EWUP1                         0x00000100U     /*!< Enable Wakeup Pin PA0              */
-#define  PWR_CSR2_EWUP2                         0x00000200U     /*!< Enable Wakeup Pin PA2              */
-#define  PWR_CSR2_EWUP3                         0x00000400U     /*!< Enable Wakeup Pin PC1              */
-#define  PWR_CSR2_EWUP4                         0x00000800U     /*!< Enable Wakeup Pin PC13             */
-#define  PWR_CSR2_EWUP5                         0x00001000U     /*!< Enable Wakeup Pin PI8              */
-#define  PWR_CSR2_EWUP6                         0x00002000U     /*!< Enable Wakeup Pin PI11             */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    QUADSPI                                 */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for QUADSPI_CR register  *******************/
-#define  QUADSPI_CR_EN                           0x00000001U            /*!< Enable                            */
-#define  QUADSPI_CR_ABORT                        0x00000002U            /*!< Abort request                     */
-#define  QUADSPI_CR_DMAEN                        0x00000004U            /*!< DMA Enable                        */
-#define  QUADSPI_CR_TCEN                         0x00000008U            /*!< Timeout Counter Enable            */
-#define  QUADSPI_CR_SSHIFT                       0x00000010U            /*!< Sample Shift                      */
-#define  QUADSPI_CR_DFM                          0x00000040U            /*!< Dual Flash Mode                   */
-#define  QUADSPI_CR_FSEL                         0x00000080U            /*!< Flash Select                      */
-#define  QUADSPI_CR_FTHRES                       0x00001F00U            /*!< FTHRES[4:0] FIFO Level            */
-#define  QUADSPI_CR_FTHRES_0                     0x00000100U            /*!< Bit 0 */
-#define  QUADSPI_CR_FTHRES_1                     0x00000200U            /*!< Bit 1 */
-#define  QUADSPI_CR_FTHRES_2                     0x00000400U            /*!< Bit 2 */
-#define  QUADSPI_CR_FTHRES_3                     0x00000800U            /*!< Bit 3 */
-#define  QUADSPI_CR_FTHRES_4                     0x00001000U            /*!< Bit 4 */
-#define  QUADSPI_CR_TEIE                         0x00010000U            /*!< Transfer Error Interrupt Enable    */
-#define  QUADSPI_CR_TCIE                         0x00020000U            /*!< Transfer Complete Interrupt Enable */
-#define  QUADSPI_CR_FTIE                         0x00040000U            /*!< FIFO Threshold Interrupt Enable    */
-#define  QUADSPI_CR_SMIE                         0x00080000U            /*!< Status Match Interrupt Enable      */
-#define  QUADSPI_CR_TOIE                         0x00100000U            /*!< TimeOut Interrupt Enable           */
-#define  QUADSPI_CR_APMS                         0x00400000U            /*!< Bit 1                              */
-#define  QUADSPI_CR_PMM                          0x00800000U            /*!< Polling Match Mode                 */
-#define  QUADSPI_CR_PRESCALER                    0xFF000000U            /*!< PRESCALER[7:0] Clock prescaler     */
-#define  QUADSPI_CR_PRESCALER_0                  0x01000000U            /*!< Bit 0 */
-#define  QUADSPI_CR_PRESCALER_1                  0x02000000U            /*!< Bit 1 */
-#define  QUADSPI_CR_PRESCALER_2                  0x04000000U            /*!< Bit 2 */
-#define  QUADSPI_CR_PRESCALER_3                  0x08000000U            /*!< Bit 3 */
-#define  QUADSPI_CR_PRESCALER_4                  0x10000000U            /*!< Bit 4 */
-#define  QUADSPI_CR_PRESCALER_5                  0x20000000U            /*!< Bit 5 */
-#define  QUADSPI_CR_PRESCALER_6                  0x40000000U            /*!< Bit 6 */
-#define  QUADSPI_CR_PRESCALER_7                  0x80000000U            /*!< Bit 7 */
-
-/*****************  Bit definition for QUADSPI_DCR register  ******************/
-#define  QUADSPI_DCR_CKMODE                      0x00000001U            /*!< Mode 0 / Mode 3                 */
-#define  QUADSPI_DCR_CSHT                        0x00000700U            /*!< CSHT[2:0]: ChipSelect High Time */
-#define  QUADSPI_DCR_CSHT_0                      0x00000100U            /*!< Bit 0 */
-#define  QUADSPI_DCR_CSHT_1                      0x00000200U            /*!< Bit 1 */
-#define  QUADSPI_DCR_CSHT_2                      0x00000400U            /*!< Bit 2 */
-#define  QUADSPI_DCR_FSIZE                       0x001F0000U            /*!< FSIZE[4:0]: Flash Size          */
-#define  QUADSPI_DCR_FSIZE_0                     0x00010000U            /*!< Bit 0 */
-#define  QUADSPI_DCR_FSIZE_1                     0x00020000U            /*!< Bit 1 */
-#define  QUADSPI_DCR_FSIZE_2                     0x00040000U            /*!< Bit 2 */
-#define  QUADSPI_DCR_FSIZE_3                     0x00080000U            /*!< Bit 3 */
-#define  QUADSPI_DCR_FSIZE_4                     0x00100000U            /*!< Bit 4 */
-
-/******************  Bit definition for QUADSPI_SR register  *******************/
-#define  QUADSPI_SR_TEF                          0x00000001U             /*!< Transfer Error Flag    */
-#define  QUADSPI_SR_TCF                          0x00000002U             /*!< Transfer Complete Flag */
-#define  QUADSPI_SR_FTF                          0x00000004U             /*!< FIFO Threshlod Flag    */
-#define  QUADSPI_SR_SMF                          0x00000008U             /*!< Status Match Flag      */
-#define  QUADSPI_SR_TOF                          0x00000010U             /*!< Timeout Flag           */
-#define  QUADSPI_SR_BUSY                         0x00000020U             /*!< Busy                   */
-#define  QUADSPI_SR_FLEVEL                       0x00001F00U             /*!< FIFO Threshlod Flag    */
-#define  QUADSPI_SR_FLEVEL_0                     0x00000100U             /*!< Bit 0 */
-#define  QUADSPI_SR_FLEVEL_1                     0x00000200U             /*!< Bit 1 */
-#define  QUADSPI_SR_FLEVEL_2                     0x00000400U             /*!< Bit 2 */
-#define  QUADSPI_SR_FLEVEL_3                     0x00000800U             /*!< Bit 3 */
-#define  QUADSPI_SR_FLEVEL_4                     0x00001000U             /*!< Bit 4 */
-
-/******************  Bit definition for QUADSPI_FCR register  ******************/
-#define  QUADSPI_FCR_CTEF                        0x00000001U             /*!< Clear Transfer Error Flag    */
-#define  QUADSPI_FCR_CTCF                        0x00000002U             /*!< Clear Transfer Complete Flag */
-#define  QUADSPI_FCR_CSMF                        0x00000008U             /*!< Clear Status Match Flag      */
-#define  QUADSPI_FCR_CTOF                        0x00000010U             /*!< Clear Timeout Flag           */
-
-/******************  Bit definition for QUADSPI_DLR register  ******************/
-#define  QUADSPI_DLR_DL                          0xFFFFFFFFU             /*!< DL[31:0]: Data Length */
-
-/******************  Bit definition for QUADSPI_CCR register  ******************/
-#define  QUADSPI_CCR_INSTRUCTION                  0x000000FFU            /*!< INSTRUCTION[7:0]: Instruction    */
-#define  QUADSPI_CCR_INSTRUCTION_0                0x00000001U            /*!< Bit 0 */
-#define  QUADSPI_CCR_INSTRUCTION_1                0x00000002U            /*!< Bit 1 */
-#define  QUADSPI_CCR_INSTRUCTION_2                0x00000004U            /*!< Bit 2 */
-#define  QUADSPI_CCR_INSTRUCTION_3                0x00000008U            /*!< Bit 3 */
-#define  QUADSPI_CCR_INSTRUCTION_4                0x00000010U            /*!< Bit 4 */
-#define  QUADSPI_CCR_INSTRUCTION_5                0x00000020U            /*!< Bit 5 */
-#define  QUADSPI_CCR_INSTRUCTION_6                0x00000040U            /*!< Bit 6 */
-#define  QUADSPI_CCR_INSTRUCTION_7                0x00000080U            /*!< Bit 7 */
-#define  QUADSPI_CCR_IMODE                        0x00000300U            /*!< IMODE[1:0]: Instruction Mode      */
-#define  QUADSPI_CCR_IMODE_0                      0x00000100U            /*!< Bit 0 */
-#define  QUADSPI_CCR_IMODE_1                      0x00000200U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ADMODE                       0x00000C00U            /*!< ADMODE[1:0]: Address Mode         */
-#define  QUADSPI_CCR_ADMODE_0                     0x00000400U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ADMODE_1                     0x00000800U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ADSIZE                       0x00003000U            /*!< ADSIZE[1:0]: Address Size         */
-#define  QUADSPI_CCR_ADSIZE_0                     0x00001000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ADSIZE_1                     0x00002000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ABMODE                       0x0000C000U            /*!< ABMODE[1:0]: Alternate Bytes Mode */
-#define  QUADSPI_CCR_ABMODE_0                     0x00004000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ABMODE_1                     0x00008000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ABSIZE                       0x00030000U            /*!< ABSIZE[1:0]: Instruction Mode     */
-#define  QUADSPI_CCR_ABSIZE_0                     0x00010000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ABSIZE_1                     0x00020000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_DCYC                         0x007C0000U            /*!< DCYC[4:0]: Dummy Cycles           */
-#define  QUADSPI_CCR_DCYC_0                       0x00040000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_DCYC_1                       0x00080000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_DCYC_2                       0x00100000U            /*!< Bit 2 */
-#define  QUADSPI_CCR_DCYC_3                       0x00200000U            /*!< Bit 3 */
-#define  QUADSPI_CCR_DCYC_4                       0x00400000U            /*!< Bit 4 */
-#define  QUADSPI_CCR_DMODE                        0x03000000U            /*!< DMODE[1:0]: Data Mode              */
-#define  QUADSPI_CCR_DMODE_0                      0x01000000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_DMODE_1                      0x02000000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_FMODE                        0x0C000000U            /*!< FMODE[1:0]: Functional Mode        */
-#define  QUADSPI_CCR_FMODE_0                      0x04000000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_FMODE_1                      0x08000000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_SIOO                         0x10000000U            /*!< SIOO: Send Instruction Only Once Mode */
-#define  QUADSPI_CCR_DHHC                         0x40000000U            /*!< DHHC: Delay Half Hclk Cycle           */
-#define  QUADSPI_CCR_DDRM                         0x80000000U            /*!< DDRM: Double Data Rate Mode           */
-/******************  Bit definition for QUADSPI_AR register  *******************/
-#define  QUADSPI_AR_ADDRESS                       0xFFFFFFFFU            /*!< ADDRESS[31:0]: Address */
-
-/******************  Bit definition for QUADSPI_ABR register  ******************/
-#define  QUADSPI_ABR_ALTERNATE                    0xFFFFFFFFU            /*!< ALTERNATE[31:0]: Alternate Bytes */
-
-/******************  Bit definition for QUADSPI_DR register  *******************/
-#define  QUADSPI_DR_DATA                          0xFFFFFFFFU            /*!< DATA[31:0]: Data */
-
-/******************  Bit definition for QUADSPI_PSMKR register  ****************/
-#define  QUADSPI_PSMKR_MASK                       0xFFFFFFFFU            /*!< MASK[31:0]: Status Mask */
-
-/******************  Bit definition for QUADSPI_PSMAR register  ****************/
-#define  QUADSPI_PSMAR_MATCH                      0xFFFFFFFFU            /*!< MATCH[31:0]: Status Match */
-
-/******************  Bit definition for QUADSPI_PIR register  *****************/
-#define  QUADSPI_PIR_INTERVAL                     0x0000FFFFU            /*!< INTERVAL[15:0]: Polling Interval */
-
-/******************  Bit definition for QUADSPI_LPTR register  *****************/
-#define  QUADSPI_LPTR_TIMEOUT                     0x0000FFFFU            /*!< TIMEOUT[15:0]: Timeout period */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        0x00000001U
-#define  RCC_CR_HSIRDY                       0x00000002U
-#define  RCC_CR_HSITRIM                      0x000000F8U
-#define  RCC_CR_HSITRIM_0                    0x00000008U /*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    0x00000010U /*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    0x00000020U /*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    0x00000040U /*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    0x00000080U /*!<Bit 4 */
-#define  RCC_CR_HSICAL                       0x0000FF00U
-#define  RCC_CR_HSICAL_0                     0x00000100U /*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     0x00000200U /*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     0x00000400U /*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     0x00000800U /*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     0x00001000U /*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     0x00002000U /*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     0x00004000U /*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     0x00008000U /*!<Bit 7 */
-#define  RCC_CR_HSEON                        0x00010000U
-#define  RCC_CR_HSERDY                       0x00020000U
-#define  RCC_CR_HSEBYP                       0x00040000U
-#define  RCC_CR_CSSON                        0x00080000U
-#define  RCC_CR_PLLON                        0x01000000U
-#define  RCC_CR_PLLRDY                       0x02000000U
-#define  RCC_CR_PLLI2SON                     0x04000000U
-#define  RCC_CR_PLLI2SRDY                    0x08000000U
-#define  RCC_CR_PLLSAION                     0x10000000U
-#define  RCC_CR_PLLSAIRDY                    0x20000000U
-
-/********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    0x0000003FU
-#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
-#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
-#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
-#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
-#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
-#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
-#define  RCC_PLLCFGR_PLLN                    0x00007FC0U
-#define  RCC_PLLCFGR_PLLN_0                  0x00000040U
-#define  RCC_PLLCFGR_PLLN_1                  0x00000080U
-#define  RCC_PLLCFGR_PLLN_2                  0x00000100U
-#define  RCC_PLLCFGR_PLLN_3                  0x00000200U
-#define  RCC_PLLCFGR_PLLN_4                  0x00000400U
-#define  RCC_PLLCFGR_PLLN_5                  0x00000800U
-#define  RCC_PLLCFGR_PLLN_6                  0x00001000U
-#define  RCC_PLLCFGR_PLLN_7                  0x00002000U
-#define  RCC_PLLCFGR_PLLN_8                  0x00004000U
-#define  RCC_PLLCFGR_PLLP                    0x00030000U
-#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
-#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
-#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
-#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
-#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
-#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
-#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
-#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
-
-#define  RCC_PLLCFGR_PLLR                    0x70000000U
-#define  RCC_PLLCFGR_PLLR_0                  0x10000000U
-#define  RCC_PLLCFGR_PLLR_1                  0x20000000U
-#define  RCC_PLLCFGR_PLLR_2                  0x40000000U
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-/*!< SW configuration */
-#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
-#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
-#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
-
-#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
-
-/*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     0x001F0000U
-#define  RCC_CFGR_RTCPRE_0                   0x00010000U
-#define  RCC_CFGR_RTCPRE_1                   0x00020000U
-#define  RCC_CFGR_RTCPRE_2                   0x00040000U
-#define  RCC_CFGR_RTCPRE_3                   0x00080000U
-#define  RCC_CFGR_RTCPRE_4                   0x00100000U
-
-/*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       0x00600000U
-#define  RCC_CFGR_MCO1_0                     0x00200000U
-#define  RCC_CFGR_MCO1_1                     0x00400000U
-
-#define  RCC_CFGR_I2SSRC                     0x00800000U
-
-#define  RCC_CFGR_MCO1PRE                    0x07000000U
-#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
-#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
-#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
-
-#define  RCC_CFGR_MCO2PRE                    0x38000000U
-#define  RCC_CFGR_MCO2PRE_0                  0x08000000U
-#define  RCC_CFGR_MCO2PRE_1                  0x10000000U
-#define  RCC_CFGR_MCO2PRE_2                  0x20000000U
-
-#define  RCC_CFGR_MCO2                       0xC0000000U
-#define  RCC_CFGR_MCO2_0                     0x40000000U
-#define  RCC_CFGR_MCO2_1                     0x80000000U
-
-/********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     0x00000001U
-#define  RCC_CIR_LSERDYF                     0x00000002U
-#define  RCC_CIR_HSIRDYF                     0x00000004U
-#define  RCC_CIR_HSERDYF                     0x00000008U
-#define  RCC_CIR_PLLRDYF                     0x00000010U
-#define  RCC_CIR_PLLI2SRDYF                  0x00000020U
-#define  RCC_CIR_PLLSAIRDYF                  0x00000040U
-#define  RCC_CIR_CSSF                        0x00000080U
-#define  RCC_CIR_LSIRDYIE                    0x00000100U
-#define  RCC_CIR_LSERDYIE                    0x00000200U
-#define  RCC_CIR_HSIRDYIE                    0x00000400U
-#define  RCC_CIR_HSERDYIE                    0x00000800U
-#define  RCC_CIR_PLLRDYIE                    0x00001000U
-#define  RCC_CIR_PLLI2SRDYIE                 0x00002000U
-#define  RCC_CIR_PLLSAIRDYIE                 0x00004000U
-#define  RCC_CIR_LSIRDYC                     0x00010000U
-#define  RCC_CIR_LSERDYC                     0x00020000U
-#define  RCC_CIR_HSIRDYC                     0x00040000U
-#define  RCC_CIR_HSERDYC                     0x00080000U
-#define  RCC_CIR_PLLRDYC                     0x00100000U
-#define  RCC_CIR_PLLI2SRDYC                  0x00200000U
-#define  RCC_CIR_PLLSAIRDYC                  0x00400000U
-#define  RCC_CIR_CSSC                        0x00800000U
-
-/********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
-#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
-#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
-#define  RCC_AHB1RSTR_GPIODRST               0x00000008U
-#define  RCC_AHB1RSTR_GPIOERST               0x00000010U
-#define  RCC_AHB1RSTR_GPIOFRST               0x00000020U
-#define  RCC_AHB1RSTR_GPIOGRST               0x00000040U
-#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
-#define  RCC_AHB1RSTR_GPIOIRST               0x00000100U
-#define  RCC_AHB1RSTR_GPIOJRST               0x00000200U
-#define  RCC_AHB1RSTR_GPIOKRST               0x00000400U
-#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
-#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
-#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
-#define  RCC_AHB1RSTR_DMA2DRST               0x00800000U
-#define  RCC_AHB1RSTR_ETHMACRST              0x02000000U
-#define  RCC_AHB1RSTR_OTGHRST                0x20000000U
-
-/********************  Bit definition for RCC_AHB2RSTR register  **************/
-#define  RCC_AHB2RSTR_DCMIRST                0x00000001U
-#define  RCC_AHB2RSTR_JPEGRST                0x00000002U
-#define  RCC_AHB2RSTR_RNGRST                 0x00000040U
-#define  RCC_AHB2RSTR_OTGFSRST               0x00000080U
-
-/********************  Bit definition for RCC_AHB3RSTR register  **************/
-
-#define  RCC_AHB3RSTR_FMCRST                 0x00000001U
-#define  RCC_AHB3RSTR_QSPIRST                0x00000002U
-
-/********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM2RST                0x00000001U
-#define  RCC_APB1RSTR_TIM3RST                0x00000002U
-#define  RCC_APB1RSTR_TIM4RST                0x00000004U
-#define  RCC_APB1RSTR_TIM5RST                0x00000008U
-#define  RCC_APB1RSTR_TIM6RST                0x00000010U
-#define  RCC_APB1RSTR_TIM7RST                0x00000020U
-#define  RCC_APB1RSTR_TIM12RST               0x00000040U
-#define  RCC_APB1RSTR_TIM13RST               0x00000080U
-#define  RCC_APB1RSTR_TIM14RST               0x00000100U
-#define  RCC_APB1RSTR_LPTIM1RST              0x00000200U
-#define  RCC_APB1RSTR_WWDGRST                0x00000800U
-#define  RCC_APB1RSTR_CAN3RST                0x00002000U
-#define  RCC_APB1RSTR_SPI2RST                0x00004000U
-#define  RCC_APB1RSTR_SPI3RST                0x00008000U
-#define  RCC_APB1RSTR_SPDIFRXRST             0x00010000U
-#define  RCC_APB1RSTR_USART2RST              0x00020000U
-#define  RCC_APB1RSTR_USART3RST              0x00040000U
-#define  RCC_APB1RSTR_UART4RST               0x00080000U
-#define  RCC_APB1RSTR_UART5RST               0x00100000U
-#define  RCC_APB1RSTR_I2C1RST                0x00200000U
-#define  RCC_APB1RSTR_I2C2RST                0x00400000U
-#define  RCC_APB1RSTR_I2C3RST                0x00800000U
-#define  RCC_APB1RSTR_I2C4RST                0x01000000U
-#define  RCC_APB1RSTR_CAN1RST                0x02000000U
-#define  RCC_APB1RSTR_CAN2RST                0x04000000U
-#define  RCC_APB1RSTR_CECRST                 0x08000000U
-#define  RCC_APB1RSTR_PWRRST                 0x10000000U
-#define  RCC_APB1RSTR_DACRST                 0x20000000U
-#define  RCC_APB1RSTR_UART7RST               0x40000000U
-#define  RCC_APB1RSTR_UART8RST               0x80000000U
-
-/********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                0x00000001U
-#define  RCC_APB2RSTR_TIM8RST                0x00000002U
-#define  RCC_APB2RSTR_USART1RST              0x00000010U
-#define  RCC_APB2RSTR_USART6RST              0x00000020U
-#define  RCC_APB2RSTR_SDMMC2RST              0x00000080U
-#define  RCC_APB2RSTR_ADCRST                 0x00000100U
-#define  RCC_APB2RSTR_SDMMC1RST              0x00000800U
-#define  RCC_APB2RSTR_SPI1RST                0x00001000U
-#define  RCC_APB2RSTR_SPI4RST                0x00002000U
-#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
-#define  RCC_APB2RSTR_TIM9RST                0x00010000U
-#define  RCC_APB2RSTR_TIM10RST               0x00020000U
-#define  RCC_APB2RSTR_TIM11RST               0x00040000U
-#define  RCC_APB2RSTR_SPI5RST                0x00100000U
-#define  RCC_APB2RSTR_SPI6RST                0x00200000U
-#define  RCC_APB2RSTR_SAI1RST                0x00400000U
-#define  RCC_APB2RSTR_SAI2RST                0x00800000U
-#define  RCC_APB2RSTR_LTDCRST                0x04000000U
-#define  RCC_APB2RSTR_DFSDM1RST              0x20000000U
-#define  RCC_APB2RSTR_MDIORST                0x40000000U
-
-/********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
-#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
-#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
-#define  RCC_AHB1ENR_GPIODEN                 0x00000008U
-#define  RCC_AHB1ENR_GPIOEEN                 0x00000010U
-#define  RCC_AHB1ENR_GPIOFEN                 0x00000020U
-#define  RCC_AHB1ENR_GPIOGEN                 0x00000040U
-#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
-#define  RCC_AHB1ENR_GPIOIEN                 0x00000100U
-#define  RCC_AHB1ENR_GPIOJEN                 0x00000200U
-#define  RCC_AHB1ENR_GPIOKEN                 0x00000400U
-#define  RCC_AHB1ENR_CRCEN                   0x00001000U
-#define  RCC_AHB1ENR_BKPSRAMEN               0x00040000U
-#define  RCC_AHB1ENR_DTCMRAMEN               0x00100000U
-#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
-#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
-#define  RCC_AHB1ENR_DMA2DEN                 0x00800000U
-#define  RCC_AHB1ENR_ETHMACEN                0x02000000U
-#define  RCC_AHB1ENR_ETHMACTXEN              0x04000000U
-#define  RCC_AHB1ENR_ETHMACRXEN              0x08000000U
-#define  RCC_AHB1ENR_ETHMACPTPEN             0x10000000U
-#define  RCC_AHB1ENR_OTGHSEN                 0x20000000U
-#define  RCC_AHB1ENR_OTGHSULPIEN             0x40000000U
-
-/********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define  RCC_AHB2ENR_DCMIEN                  0x00000001U
-#define  RCC_AHB2ENR_JPEGEN                  0x00000002U
-#define  RCC_AHB2ENR_RNGEN                   0x00000040U
-#define  RCC_AHB2ENR_OTGFSEN                 0x00000080U
-
-/********************  Bit definition for RCC_AHB3ENR register  ***************/
-#define  RCC_AHB3ENR_FMCEN                  0x00000001U
-#define  RCC_AHB3ENR_QSPIEN                 0x00000002U
-
-/********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM2EN                  0x00000001U
-#define  RCC_APB1ENR_TIM3EN                  0x00000002U
-#define  RCC_APB1ENR_TIM4EN                  0x00000004U
-#define  RCC_APB1ENR_TIM5EN                  0x00000008U
-#define  RCC_APB1ENR_TIM6EN                  0x00000010U
-#define  RCC_APB1ENR_TIM7EN                  0x00000020U
-#define  RCC_APB1ENR_TIM12EN                 0x00000040U
-#define  RCC_APB1ENR_TIM13EN                 0x00000080U
-#define  RCC_APB1ENR_TIM14EN                 0x00000100U
-#define  RCC_APB1ENR_LPTIM1EN                0x00000200U
-#define  RCC_APB1ENR_RTCEN                   0x00000400U
-#define  RCC_APB1ENR_WWDGEN                  0x00000800U
-#define  RCC_APB1ENR_CAN3EN                  0x00002000U
-#define  RCC_APB1ENR_SPI2EN                  0x00004000U
-#define  RCC_APB1ENR_SPI3EN                  0x00008000U
-#define  RCC_APB1ENR_SPDIFRXEN               0x00010000U
-#define  RCC_APB1ENR_USART2EN                0x00020000U
-#define  RCC_APB1ENR_USART3EN                0x00040000U
-#define  RCC_APB1ENR_UART4EN                 0x00080000U
-#define  RCC_APB1ENR_UART5EN                 0x00100000U
-#define  RCC_APB1ENR_I2C1EN                  0x00200000U
-#define  RCC_APB1ENR_I2C2EN                  0x00400000U
-#define  RCC_APB1ENR_I2C3EN                  0x00800000U
-#define  RCC_APB1ENR_I2C4EN                  0x01000000U
-#define  RCC_APB1ENR_CAN1EN                  0x02000000U
-#define  RCC_APB1ENR_CAN2EN                  0x04000000U
-#define  RCC_APB1ENR_CECEN                   0x08000000U
-#define  RCC_APB1ENR_PWREN                   0x10000000U
-#define  RCC_APB1ENR_DACEN                   0x20000000U
-#define  RCC_APB1ENR_UART7EN                 0x40000000U
-#define  RCC_APB1ENR_UART8EN                 0x80000000U
-
-/********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  0x00000001U
-#define  RCC_APB2ENR_TIM8EN                  0x00000002U
-#define  RCC_APB2ENR_USART1EN                0x00000010U
-#define  RCC_APB2ENR_USART6EN                0x00000020U
-#define  RCC_APB2ENR_SDMMC2EN                0x00000080U
-#define  RCC_APB2ENR_ADC1EN                  0x00000100U
-#define  RCC_APB2ENR_ADC2EN                  0x00000200U
-#define  RCC_APB2ENR_ADC3EN                  0x00000400U
-#define  RCC_APB2ENR_SDMMC1EN                0x00000800U
-#define  RCC_APB2ENR_SPI1EN                  0x00001000U
-#define  RCC_APB2ENR_SPI4EN                  0x00002000U
-#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
-#define  RCC_APB2ENR_TIM9EN                  0x00010000U
-#define  RCC_APB2ENR_TIM10EN                 0x00020000U
-#define  RCC_APB2ENR_TIM11EN                 0x00040000U
-#define  RCC_APB2ENR_SPI5EN                  0x00100000U
-#define  RCC_APB2ENR_SPI6EN                  0x00200000U
-#define  RCC_APB2ENR_SAI1EN                  0x00400000U
-#define  RCC_APB2ENR_SAI2EN                  0x00800000U
-#define  RCC_APB2ENR_LTDCEN                  0x04000000U
-#define  RCC_APB2ENR_DFSDM1EN                0x20000000U
-#define  RCC_APB2ENR_MDIOEN                  0x40000000U
-
-/********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
-#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
-#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
-#define  RCC_AHB1LPENR_GPIODLPEN             0x00000008U
-#define  RCC_AHB1LPENR_GPIOELPEN             0x00000010U
-#define  RCC_AHB1LPENR_GPIOFLPEN             0x00000020U
-#define  RCC_AHB1LPENR_GPIOGLPEN             0x00000040U
-#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
-#define  RCC_AHB1LPENR_GPIOILPEN             0x00000100U
-#define  RCC_AHB1LPENR_GPIOJLPEN             0x00000200U
-#define  RCC_AHB1LPENR_GPIOKLPEN             0x00000400U
-#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
-#define  RCC_AHB1LPENR_AXILPEN               0x00002000U
-#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
-#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
-#define  RCC_AHB1LPENR_SRAM2LPEN             0x00020000U
-#define  RCC_AHB1LPENR_BKPSRAMLPEN           0x00040000U
-#define  RCC_AHB1LPENR_DTCMLPEN              0x00100000U
-#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
-#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
-#define  RCC_AHB1LPENR_DMA2DLPEN             0x00800000U
-#define  RCC_AHB1LPENR_ETHMACLPEN            0x02000000U
-#define  RCC_AHB1LPENR_ETHMACTXLPEN          0x04000000U
-#define  RCC_AHB1LPENR_ETHMACRXLPEN          0x08000000U
-#define  RCC_AHB1LPENR_ETHMACPTPLPEN         0x10000000U
-#define  RCC_AHB1LPENR_OTGHSLPEN             0x20000000U
-#define  RCC_AHB1LPENR_OTGHSULPILPEN         0x40000000U
-
-/********************  Bit definition for RCC_AHB2LPENR register  *************/
-#define  RCC_AHB2LPENR_DCMILPEN              0x00000001U
-#define  RCC_AHB2LPENR_JPEGLPEN              0x00000002U
-#define  RCC_AHB2LPENR_RNGLPEN               0x00000040U
-#define  RCC_AHB2LPENR_OTGFSLPEN             0x00000080U
-
-/********************  Bit definition for RCC_AHB3LPENR register  *************/
-#define  RCC_AHB3LPENR_FMCLPEN               0x00000001U
-#define  RCC_AHB3LPENR_QSPILPEN              0x00000002U
-/********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM2LPEN              0x00000001U
-#define  RCC_APB1LPENR_TIM3LPEN              0x00000002U
-#define  RCC_APB1LPENR_TIM4LPEN              0x00000004U
-#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
-#define  RCC_APB1LPENR_TIM6LPEN              0x00000010U
-#define  RCC_APB1LPENR_TIM7LPEN              0x00000020U
-#define  RCC_APB1LPENR_TIM12LPEN             0x00000040U
-#define  RCC_APB1LPENR_TIM13LPEN             0x00000080U
-#define  RCC_APB1LPENR_TIM14LPEN             0x00000100U
-#define  RCC_APB1LPENR_LPTIM1LPEN            0x00000200U
-#define  RCC_APB1LPENR_RTCLPEN               0x00000400U
-#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
-#define  RCC_APB1LPENR_CAN3LPEN              0x00002000U
-#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U
-#define  RCC_APB1LPENR_SPI3LPEN              0x00008000U
-#define  RCC_APB1LPENR_SPDIFRXLPEN           0x00010000U
-#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
-#define  RCC_APB1LPENR_USART3LPEN            0x00040000U
-#define  RCC_APB1LPENR_UART4LPEN             0x00080000U
-#define  RCC_APB1LPENR_UART5LPEN             0x00100000U
-#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
-#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
-#define  RCC_APB1LPENR_I2C3LPEN              0x00800000U
-#define  RCC_APB1LPENR_I2C4LPEN              0x01000000U
-#define  RCC_APB1LPENR_CAN1LPEN              0x02000000U
-#define  RCC_APB1LPENR_CAN2LPEN              0x04000000U
-#define  RCC_APB1LPENR_CECLPEN               0x08000000U
-#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
-#define  RCC_APB1LPENR_DACLPEN               0x20000000U
-#define  RCC_APB1LPENR_UART7LPEN             0x40000000U
-#define  RCC_APB1LPENR_UART8LPEN             0x80000000U
-
-/********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
-#define  RCC_APB2LPENR_TIM8LPEN              0x00000002U
-#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
-#define  RCC_APB2LPENR_USART6LPEN            0x00000020U
-#define  RCC_APB2LPENR_SDMMC2LPEN            0x00000080U
-#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
-#define  RCC_APB2LPENR_ADC2LPEN              0x00000200U
-#define  RCC_APB2LPENR_ADC3LPEN              0x00000400U
-#define  RCC_APB2LPENR_SDMMC1LPEN            0x00000800U
-#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
-#define  RCC_APB2LPENR_SPI4LPEN              0x00002000U
-#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
-#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
-#define  RCC_APB2LPENR_TIM10LPEN             0x00020000U
-#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
-#define  RCC_APB2LPENR_SPI5LPEN              0x00100000U
-#define  RCC_APB2LPENR_SPI6LPEN              0x00200000U
-#define  RCC_APB2LPENR_SAI1LPEN              0x00400000U
-#define  RCC_APB2LPENR_SAI2LPEN              0x00800000U
-#define  RCC_APB2LPENR_LTDCLPEN              0x04000000U
-#define  RCC_APB2LPENR_DFSDM1LPEN            0x20000000U
-#define  RCC_APB2LPENR_MDIOLPEN              0x40000000U
-
-/********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      0x00000001U
-#define  RCC_BDCR_LSERDY                     0x00000002U
-#define  RCC_BDCR_LSEBYP                     0x00000004U
-#define  RCC_BDCR_LSEDRV                     0x00000018U
-#define  RCC_BDCR_LSEDRV_0                   0x00000008U
-#define  RCC_BDCR_LSEDRV_1                   0x00000010U
-#define  RCC_BDCR_RTCSEL                     0x00000300U
-#define  RCC_BDCR_RTCSEL_0                   0x00000100U
-#define  RCC_BDCR_RTCSEL_1                   0x00000200U
-#define  RCC_BDCR_RTCEN                      0x00008000U
-#define  RCC_BDCR_BDRST                      0x00010000U
-
-/********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       0x00000001U
-#define  RCC_CSR_LSIRDY                      0x00000002U
-#define  RCC_CSR_RMVF                        0x01000000U
-#define  RCC_CSR_BORRSTF                     0x02000000U
-#define  RCC_CSR_PINRSTF                     0x04000000U
-#define  RCC_CSR_PORRSTF                     0x08000000U
-#define  RCC_CSR_SFTRSTF                     0x10000000U
-#define  RCC_CSR_IWDGRSTF                    0x20000000U
-#define  RCC_CSR_WWDGRSTF                    0x40000000U
-#define  RCC_CSR_LPWRRSTF                    0x80000000U
-
-/********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    0x00001FFFU
-#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
-#define  RCC_SSCGR_SPREADSEL                 0x40000000U
-#define  RCC_SSCGR_SSCGEN                    0x80000000U
-
-/********************  Bit definition for RCC_PLLI2SCFGR register  ************/
-#define  RCC_PLLI2SCFGR_PLLI2SN              0x00007FC0U
-#define  RCC_PLLI2SCFGR_PLLI2SN_0            0x00000040U
-#define  RCC_PLLI2SCFGR_PLLI2SN_1            0x00000080U
-#define  RCC_PLLI2SCFGR_PLLI2SN_2            0x00000100U
-#define  RCC_PLLI2SCFGR_PLLI2SN_3            0x00000200U
-#define  RCC_PLLI2SCFGR_PLLI2SN_4            0x00000400U
-#define  RCC_PLLI2SCFGR_PLLI2SN_5            0x00000800U
-#define  RCC_PLLI2SCFGR_PLLI2SN_6            0x00001000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_7            0x00002000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_8            0x00004000U
-#define  RCC_PLLI2SCFGR_PLLI2SP              0x00030000U
-#define  RCC_PLLI2SCFGR_PLLI2SP_0            0x00010000U
-#define  RCC_PLLI2SCFGR_PLLI2SP_1            0x00020000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ              0x0F000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_0            0x01000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_1            0x02000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_2            0x04000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_3            0x08000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR              0x70000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_0            0x10000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_1            0x20000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_2            0x40000000U
-
-/********************  Bit definition for RCC_PLLSAICFGR register  ************/
-#define  RCC_PLLSAICFGR_PLLSAIN              0x00007FC0U
-#define  RCC_PLLSAICFGR_PLLSAIN_0            0x00000040U
-#define  RCC_PLLSAICFGR_PLLSAIN_1            0x00000080U
-#define  RCC_PLLSAICFGR_PLLSAIN_2            0x00000100U
-#define  RCC_PLLSAICFGR_PLLSAIN_3            0x00000200U
-#define  RCC_PLLSAICFGR_PLLSAIN_4            0x00000400U
-#define  RCC_PLLSAICFGR_PLLSAIN_5            0x00000800U
-#define  RCC_PLLSAICFGR_PLLSAIN_6            0x00001000U
-#define  RCC_PLLSAICFGR_PLLSAIN_7            0x00002000U
-#define  RCC_PLLSAICFGR_PLLSAIN_8            0x00004000U
-#define  RCC_PLLSAICFGR_PLLSAIP              0x00030000U
-#define  RCC_PLLSAICFGR_PLLSAIP_0            0x00010000U
-#define  RCC_PLLSAICFGR_PLLSAIP_1            0x00020000U
-#define  RCC_PLLSAICFGR_PLLSAIQ              0x0F000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_0            0x01000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_1            0x02000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_2            0x04000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_3            0x08000000U
-#define  RCC_PLLSAICFGR_PLLSAIR              0x70000000U
-#define  RCC_PLLSAICFGR_PLLSAIR_0            0x10000000U
-#define  RCC_PLLSAICFGR_PLLSAIR_1            0x20000000U
-#define  RCC_PLLSAICFGR_PLLSAIR_2            0x40000000U
-
-/********************  Bit definition for RCC_DCKCFGR1 register  ***************/
-#define  RCC_DCKCFGR1_PLLI2SDIVQ             0x0000001FU
-#define  RCC_DCKCFGR1_PLLI2SDIVQ_0           0x00000001U
-#define  RCC_DCKCFGR1_PLLI2SDIVQ_1           0x00000002U
-#define  RCC_DCKCFGR1_PLLI2SDIVQ_2           0x00000004U
-#define  RCC_DCKCFGR1_PLLI2SDIVQ_3           0x00000008U
-#define  RCC_DCKCFGR1_PLLI2SDIVQ_4           0x00000010U
-
-#define  RCC_DCKCFGR1_PLLSAIDIVQ             0x00001F00U
-#define  RCC_DCKCFGR1_PLLSAIDIVQ_0           0x00000100U
-#define  RCC_DCKCFGR1_PLLSAIDIVQ_1           0x00000200U
-#define  RCC_DCKCFGR1_PLLSAIDIVQ_2           0x00000400U
-#define  RCC_DCKCFGR1_PLLSAIDIVQ_3           0x00000800U
-#define  RCC_DCKCFGR1_PLLSAIDIVQ_4           0x00001000U
-
-#define  RCC_DCKCFGR1_PLLSAIDIVR             0x00030000U
-#define  RCC_DCKCFGR1_PLLSAIDIVR_0           0x00010000U
-#define  RCC_DCKCFGR1_PLLSAIDIVR_1           0x00020000U
-
-#define  RCC_DCKCFGR1_SAI1SEL                0x00300000U
-#define  RCC_DCKCFGR1_SAI1SEL_0              0x00100000U
-#define  RCC_DCKCFGR1_SAI1SEL_1              0x00200000U
-
-#define  RCC_DCKCFGR1_SAI2SEL                0x00C00000U
-#define  RCC_DCKCFGR1_SAI2SEL_0              0x00400000U
-#define  RCC_DCKCFGR1_SAI2SEL_1              0x00800000U
-
-#define  RCC_DCKCFGR1_TIMPRE                 0x01000000U
-#define  RCC_DCKCFGR1_DFSDM1SEL              0x02000000U
-#define  RCC_DCKCFGR1_ADFSDM1SEL             0x04000000U
-
-/********************  Bit definition for RCC_DCKCFGR2 register  ***************/
-#define  RCC_DCKCFGR2_USART1SEL              0x00000003U
-#define  RCC_DCKCFGR2_USART1SEL_0            0x00000001U
-#define  RCC_DCKCFGR2_USART1SEL_1            0x00000002U
-#define  RCC_DCKCFGR2_USART2SEL              0x0000000CU
-#define  RCC_DCKCFGR2_USART2SEL_0            0x00000004U
-#define  RCC_DCKCFGR2_USART2SEL_1            0x00000008U
-#define  RCC_DCKCFGR2_USART3SEL              0x00000030U
-#define  RCC_DCKCFGR2_USART3SEL_0            0x00000010U
-#define  RCC_DCKCFGR2_USART3SEL_1            0x00000020U
-#define  RCC_DCKCFGR2_UART4SEL               0x000000C0U
-#define  RCC_DCKCFGR2_UART4SEL_0             0x00000040U
-#define  RCC_DCKCFGR2_UART4SEL_1             0x00000080U
-#define  RCC_DCKCFGR2_UART5SEL               0x00000300U
-#define  RCC_DCKCFGR2_UART5SEL_0             0x00000100U
-#define  RCC_DCKCFGR2_UART5SEL_1             0x00000200U
-#define  RCC_DCKCFGR2_USART6SEL              0x00000C00U
-#define  RCC_DCKCFGR2_USART6SEL_0            0x00000400U
-#define  RCC_DCKCFGR2_USART6SEL_1            0x00000800U
-#define  RCC_DCKCFGR2_UART7SEL               0x00003000U
-#define  RCC_DCKCFGR2_UART7SEL_0             0x00001000U
-#define  RCC_DCKCFGR2_UART7SEL_1             0x00002000U
-#define  RCC_DCKCFGR2_UART8SEL               0x0000C000U
-#define  RCC_DCKCFGR2_UART8SEL_0             0x00004000U
-#define  RCC_DCKCFGR2_UART8SEL_1             0x00008000U
-#define  RCC_DCKCFGR2_I2C1SEL                0x00030000U
-#define  RCC_DCKCFGR2_I2C1SEL_0              0x00010000U
-#define  RCC_DCKCFGR2_I2C1SEL_1              0x00020000U
-#define  RCC_DCKCFGR2_I2C2SEL                0x000C0000U
-#define  RCC_DCKCFGR2_I2C2SEL_0              0x00040000U
-#define  RCC_DCKCFGR2_I2C2SEL_1              0x00080000U
-#define  RCC_DCKCFGR2_I2C3SEL                0x00300000U
-#define  RCC_DCKCFGR2_I2C3SEL_0              0x00100000U
-#define  RCC_DCKCFGR2_I2C3SEL_1              0x00200000U
-#define  RCC_DCKCFGR2_I2C4SEL                0x00C00000U
-#define  RCC_DCKCFGR2_I2C4SEL_0              0x00400000U
-#define  RCC_DCKCFGR2_I2C4SEL_1              0x00800000U
-#define  RCC_DCKCFGR2_LPTIM1SEL              0x03000000U
-#define  RCC_DCKCFGR2_LPTIM1SEL_0            0x01000000U
-#define  RCC_DCKCFGR2_LPTIM1SEL_1            0x02000000U
-#define  RCC_DCKCFGR2_CECSEL                 0x04000000U
-#define  RCC_DCKCFGR2_CK48MSEL               0x08000000U
-#define  RCC_DCKCFGR2_SDMMC1SEL              0x10000000U
-#define  RCC_DCKCFGR2_SDMMC2SEL              0x20000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    RNG                                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN                         0x00000004U
-#define RNG_CR_IE                            0x00000008U
-
-/********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY                          0x00000001U
-#define RNG_SR_CECS                          0x00000002U
-#define RNG_SR_SECS                          0x00000004U
-#define RNG_SR_CEIS                          0x00000020U
-#define RNG_SR_SEIS                          0x00000040U
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            0x00400000U
-#define RTC_TR_HT                            0x00300000U
-#define RTC_TR_HT_0                          0x00100000U
-#define RTC_TR_HT_1                          0x00200000U
-#define RTC_TR_HU                            0x000F0000U
-#define RTC_TR_HU_0                          0x00010000U
-#define RTC_TR_HU_1                          0x00020000U
-#define RTC_TR_HU_2                          0x00040000U
-#define RTC_TR_HU_3                          0x00080000U
-#define RTC_TR_MNT                           0x00007000U
-#define RTC_TR_MNT_0                         0x00001000U
-#define RTC_TR_MNT_1                         0x00002000U
-#define RTC_TR_MNT_2                         0x00004000U
-#define RTC_TR_MNU                           0x00000F00U
-#define RTC_TR_MNU_0                         0x00000100U
-#define RTC_TR_MNU_1                         0x00000200U
-#define RTC_TR_MNU_2                         0x00000400U
-#define RTC_TR_MNU_3                         0x00000800U
-#define RTC_TR_ST                            0x00000070U
-#define RTC_TR_ST_0                          0x00000010U
-#define RTC_TR_ST_1                          0x00000020U
-#define RTC_TR_ST_2                          0x00000040U
-#define RTC_TR_SU                            0x0000000FU
-#define RTC_TR_SU_0                          0x00000001U
-#define RTC_TR_SU_1                          0x00000002U
-#define RTC_TR_SU_2                          0x00000004U
-#define RTC_TR_SU_3                          0x00000008U
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            0x00F00000U
-#define RTC_DR_YT_0                          0x00100000U
-#define RTC_DR_YT_1                          0x00200000U
-#define RTC_DR_YT_2                          0x00400000U
-#define RTC_DR_YT_3                          0x00800000U
-#define RTC_DR_YU                            0x000F0000U
-#define RTC_DR_YU_0                          0x00010000U
-#define RTC_DR_YU_1                          0x00020000U
-#define RTC_DR_YU_2                          0x00040000U
-#define RTC_DR_YU_3                          0x00080000U
-#define RTC_DR_WDU                           0x0000E000U
-#define RTC_DR_WDU_0                         0x00002000U
-#define RTC_DR_WDU_1                         0x00004000U
-#define RTC_DR_WDU_2                         0x00008000U
-#define RTC_DR_MT                            0x00001000U
-#define RTC_DR_MU                            0x00000F00U
-#define RTC_DR_MU_0                          0x00000100U
-#define RTC_DR_MU_1                          0x00000200U
-#define RTC_DR_MU_2                          0x00000400U
-#define RTC_DR_MU_3                          0x00000800U
-#define RTC_DR_DT                            0x00000030U
-#define RTC_DR_DT_0                          0x00000010U
-#define RTC_DR_DT_1                          0x00000020U
-#define RTC_DR_DU                            0x0000000FU
-#define RTC_DR_DU_0                          0x00000001U
-#define RTC_DR_DU_1                          0x00000002U
-#define RTC_DR_DU_2                          0x00000004U
-#define RTC_DR_DU_3                          0x00000008U
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_ITSE                          0x01000000U
-#define RTC_CR_COE                           0x00800000U
-#define RTC_CR_OSEL                          0x00600000U
-#define RTC_CR_OSEL_0                        0x00200000U
-#define RTC_CR_OSEL_1                        0x00400000U
-#define RTC_CR_POL                           0x00100000U
-#define RTC_CR_COSEL                         0x00080000U
-#define RTC_CR_BKP                           0x00040000U
-#define RTC_CR_SUB1H                         0x00020000U
-#define RTC_CR_ADD1H                         0x00010000U
-#define RTC_CR_TSIE                          0x00008000U
-#define RTC_CR_WUTIE                         0x00004000U
-#define RTC_CR_ALRBIE                        0x00002000U
-#define RTC_CR_ALRAIE                        0x00001000U
-#define RTC_CR_TSE                           0x00000800U
-#define RTC_CR_WUTE                          0x00000400U
-#define RTC_CR_ALRBE                         0x00000200U
-#define RTC_CR_ALRAE                         0x00000100U
-#define RTC_CR_FMT                           0x00000040U
-#define RTC_CR_BYPSHAD                       0x00000020U
-#define RTC_CR_REFCKON                       0x00000010U
-#define RTC_CR_TSEDGE                        0x00000008U
-#define RTC_CR_WUCKSEL                       0x00000007U
-#define RTC_CR_WUCKSEL_0                     0x00000001U
-#define RTC_CR_WUCKSEL_1                     0x00000002U
-#define RTC_CR_WUCKSEL_2                     0x00000004U
-
-/* Legacy define */
-#define RTC_CR_BCK                           RTC_CR_BKP
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_ITSF                         0x00020000U
-#define RTC_ISR_RECALPF                      0x00010000U
-#define RTC_ISR_TAMP3F                       0x00008000U
-#define RTC_ISR_TAMP2F                       0x00004000U
-#define RTC_ISR_TAMP1F                       0x00002000U
-#define RTC_ISR_TSOVF                        0x00001000U
-#define RTC_ISR_TSF                          0x00000800U
-#define RTC_ISR_WUTF                         0x00000400U
-#define RTC_ISR_ALRBF                        0x00000200U
-#define RTC_ISR_ALRAF                        0x00000100U
-#define RTC_ISR_INIT                         0x00000080U
-#define RTC_ISR_INITF                        0x00000040U
-#define RTC_ISR_RSF                          0x00000020U
-#define RTC_ISR_INITS                        0x00000010U
-#define RTC_ISR_SHPF                         0x00000008U
-#define RTC_ISR_WUTWF                        0x00000004U
-#define RTC_ISR_ALRBWF                       0x00000002U
-#define RTC_ISR_ALRAWF                       0x00000001U
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    0x007F0000U
-#define RTC_PRER_PREDIV_S                    0x00007FFFU
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         0x0000FFFFU
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      0x80000000U
-#define RTC_ALRMAR_WDSEL                     0x40000000U
-#define RTC_ALRMAR_DT                        0x30000000U
-#define RTC_ALRMAR_DT_0                      0x10000000U
-#define RTC_ALRMAR_DT_1                      0x20000000U
-#define RTC_ALRMAR_DU                        0x0F000000U
-#define RTC_ALRMAR_DU_0                      0x01000000U
-#define RTC_ALRMAR_DU_1                      0x02000000U
-#define RTC_ALRMAR_DU_2                      0x04000000U
-#define RTC_ALRMAR_DU_3                      0x08000000U
-#define RTC_ALRMAR_MSK3                      0x00800000U
-#define RTC_ALRMAR_PM                        0x00400000U
-#define RTC_ALRMAR_HT                        0x00300000U
-#define RTC_ALRMAR_HT_0                      0x00100000U
-#define RTC_ALRMAR_HT_1                      0x00200000U
-#define RTC_ALRMAR_HU                        0x000F0000U
-#define RTC_ALRMAR_HU_0                      0x00010000U
-#define RTC_ALRMAR_HU_1                      0x00020000U
-#define RTC_ALRMAR_HU_2                      0x00040000U
-#define RTC_ALRMAR_HU_3                      0x00080000U
-#define RTC_ALRMAR_MSK2                      0x00008000U
-#define RTC_ALRMAR_MNT                       0x00007000U
-#define RTC_ALRMAR_MNT_0                     0x00001000U
-#define RTC_ALRMAR_MNT_1                     0x00002000U
-#define RTC_ALRMAR_MNT_2                     0x00004000U
-#define RTC_ALRMAR_MNU                       0x00000F00U
-#define RTC_ALRMAR_MNU_0                     0x00000100U
-#define RTC_ALRMAR_MNU_1                     0x00000200U
-#define RTC_ALRMAR_MNU_2                     0x00000400U
-#define RTC_ALRMAR_MNU_3                     0x00000800U
-#define RTC_ALRMAR_MSK1                      0x00000080U
-#define RTC_ALRMAR_ST                        0x00000070U
-#define RTC_ALRMAR_ST_0                      0x00000010U
-#define RTC_ALRMAR_ST_1                      0x00000020U
-#define RTC_ALRMAR_ST_2                      0x00000040U
-#define RTC_ALRMAR_SU                        0x0000000FU
-#define RTC_ALRMAR_SU_0                      0x00000001U
-#define RTC_ALRMAR_SU_1                      0x00000002U
-#define RTC_ALRMAR_SU_2                      0x00000004U
-#define RTC_ALRMAR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      0x80000000U
-#define RTC_ALRMBR_WDSEL                     0x40000000U
-#define RTC_ALRMBR_DT                        0x30000000U
-#define RTC_ALRMBR_DT_0                      0x10000000U
-#define RTC_ALRMBR_DT_1                      0x20000000U
-#define RTC_ALRMBR_DU                        0x0F000000U
-#define RTC_ALRMBR_DU_0                      0x01000000U
-#define RTC_ALRMBR_DU_1                      0x02000000U
-#define RTC_ALRMBR_DU_2                      0x04000000U
-#define RTC_ALRMBR_DU_3                      0x08000000U
-#define RTC_ALRMBR_MSK3                      0x00800000U
-#define RTC_ALRMBR_PM                        0x00400000U
-#define RTC_ALRMBR_HT                        0x00300000U
-#define RTC_ALRMBR_HT_0                      0x00100000U
-#define RTC_ALRMBR_HT_1                      0x00200000U
-#define RTC_ALRMBR_HU                        0x000F0000U
-#define RTC_ALRMBR_HU_0                      0x00010000U
-#define RTC_ALRMBR_HU_1                      0x00020000U
-#define RTC_ALRMBR_HU_2                      0x00040000U
-#define RTC_ALRMBR_HU_3                      0x00080000U
-#define RTC_ALRMBR_MSK2                      0x00008000U
-#define RTC_ALRMBR_MNT                       0x00007000U
-#define RTC_ALRMBR_MNT_0                     0x00001000U
-#define RTC_ALRMBR_MNT_1                     0x00002000U
-#define RTC_ALRMBR_MNT_2                     0x00004000U
-#define RTC_ALRMBR_MNU                       0x00000F00U
-#define RTC_ALRMBR_MNU_0                     0x00000100U
-#define RTC_ALRMBR_MNU_1                     0x00000200U
-#define RTC_ALRMBR_MNU_2                     0x00000400U
-#define RTC_ALRMBR_MNU_3                     0x00000800U
-#define RTC_ALRMBR_MSK1                      0x00000080U
-#define RTC_ALRMBR_ST                        0x00000070U
-#define RTC_ALRMBR_ST_0                      0x00000010U
-#define RTC_ALRMBR_ST_1                      0x00000020U
-#define RTC_ALRMBR_ST_2                      0x00000040U
-#define RTC_ALRMBR_SU                        0x0000000FU
-#define RTC_ALRMBR_SU_0                      0x00000001U
-#define RTC_ALRMBR_SU_1                      0x00000002U
-#define RTC_ALRMBR_SU_2                      0x00000004U
-#define RTC_ALRMBR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          0x000000FFU
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           0x0000FFFFU
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     0x00007FFFU
-#define RTC_SHIFTR_ADD1S                     0x80000000U
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          0x00400000U
-#define RTC_TSTR_HT                          0x00300000U
-#define RTC_TSTR_HT_0                        0x00100000U
-#define RTC_TSTR_HT_1                        0x00200000U
-#define RTC_TSTR_HU                          0x000F0000U
-#define RTC_TSTR_HU_0                        0x00010000U
-#define RTC_TSTR_HU_1                        0x00020000U
-#define RTC_TSTR_HU_2                        0x00040000U
-#define RTC_TSTR_HU_3                        0x00080000U
-#define RTC_TSTR_MNT                         0x00007000U
-#define RTC_TSTR_MNT_0                       0x00001000U
-#define RTC_TSTR_MNT_1                       0x00002000U
-#define RTC_TSTR_MNT_2                       0x00004000U
-#define RTC_TSTR_MNU                         0x00000F00U
-#define RTC_TSTR_MNU_0                       0x00000100U
-#define RTC_TSTR_MNU_1                       0x00000200U
-#define RTC_TSTR_MNU_2                       0x00000400U
-#define RTC_TSTR_MNU_3                       0x00000800U
-#define RTC_TSTR_ST                          0x00000070U
-#define RTC_TSTR_ST_0                        0x00000010U
-#define RTC_TSTR_ST_1                        0x00000020U
-#define RTC_TSTR_ST_2                        0x00000040U
-#define RTC_TSTR_SU                          0x0000000FU
-#define RTC_TSTR_SU_0                        0x00000001U
-#define RTC_TSTR_SU_1                        0x00000002U
-#define RTC_TSTR_SU_2                        0x00000004U
-#define RTC_TSTR_SU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         0x0000E000U
-#define RTC_TSDR_WDU_0                       0x00002000U
-#define RTC_TSDR_WDU_1                       0x00004000U
-#define RTC_TSDR_WDU_2                       0x00008000U
-#define RTC_TSDR_MT                          0x00001000U
-#define RTC_TSDR_MU                          0x00000F00U
-#define RTC_TSDR_MU_0                        0x00000100U
-#define RTC_TSDR_MU_1                        0x00000200U
-#define RTC_TSDR_MU_2                        0x00000400U
-#define RTC_TSDR_MU_3                        0x00000800U
-#define RTC_TSDR_DT                          0x00000030U
-#define RTC_TSDR_DT_0                        0x00000010U
-#define RTC_TSDR_DT_1                        0x00000020U
-#define RTC_TSDR_DU                          0x0000000FU
-#define RTC_TSDR_DU_0                        0x00000001U
-#define RTC_TSDR_DU_1                        0x00000002U
-#define RTC_TSDR_DU_2                        0x00000004U
-#define RTC_TSDR_DU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        0x00008000U
-#define RTC_CALR_CALW8                       0x00004000U
-#define RTC_CALR_CALW16                      0x00002000U
-#define RTC_CALR_CALM                        0x000001FFU
-#define RTC_CALR_CALM_0                      0x00000001U
-#define RTC_CALR_CALM_1                      0x00000002U
-#define RTC_CALR_CALM_2                      0x00000004U
-#define RTC_CALR_CALM_3                      0x00000008U
-#define RTC_CALR_CALM_4                      0x00000010U
-#define RTC_CALR_CALM_5                      0x00000020U
-#define RTC_CALR_CALM_6                      0x00000040U
-#define RTC_CALR_CALM_7                      0x00000080U
-#define RTC_CALR_CALM_8                      0x00000100U
-
-/********************  Bits definition for RTC_TAMPCR register  ****************/
-#define RTC_TAMPCR_TAMP3MF                   0x01000000U
-#define RTC_TAMPCR_TAMP3NOERASE              0x00800000U
-#define RTC_TAMPCR_TAMP3IE                   0x00400000U
-#define RTC_TAMPCR_TAMP2MF                   0x00200000U
-#define RTC_TAMPCR_TAMP2NOERASE              0x00100000U
-#define RTC_TAMPCR_TAMP2IE                   0x00080000U
-#define RTC_TAMPCR_TAMP1MF                   0x00040000U
-#define RTC_TAMPCR_TAMP1NOERASE              0x00020000U
-#define RTC_TAMPCR_TAMP1IE                   0x00010000U
-#define RTC_TAMPCR_TAMPPUDIS                 0x00008000U
-#define RTC_TAMPCR_TAMPPRCH                  0x00006000U
-#define RTC_TAMPCR_TAMPPRCH_0                0x00002000U
-#define RTC_TAMPCR_TAMPPRCH_1                0x00004000U
-#define RTC_TAMPCR_TAMPFLT                   0x00001800U
-#define RTC_TAMPCR_TAMPFLT_0                 0x00000800U
-#define RTC_TAMPCR_TAMPFLT_1                 0x00001000U
-#define RTC_TAMPCR_TAMPFREQ                  0x00000700U
-#define RTC_TAMPCR_TAMPFREQ_0                0x00000100U
-#define RTC_TAMPCR_TAMPFREQ_1                0x00000200U
-#define RTC_TAMPCR_TAMPFREQ_2                0x00000400U
-#define RTC_TAMPCR_TAMPTS                    0x00000080U
-#define RTC_TAMPCR_TAMP3TRG                  0x00000040U
-#define RTC_TAMPCR_TAMP3E                    0x00000020U
-#define RTC_TAMPCR_TAMP2TRG                  0x00000010U
-#define RTC_TAMPCR_TAMP2E                    0x00000008U
-#define RTC_TAMPCR_TAMPIE                    0x00000004U
-#define RTC_TAMPCR_TAMP1TRG                  0x00000002U
-#define RTC_TAMPCR_TAMP1E                    0x00000001U
-
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  0x0F000000U
-#define RTC_ALRMASSR_MASKSS_0                0x01000000U
-#define RTC_ALRMASSR_MASKSS_1                0x02000000U
-#define RTC_ALRMASSR_MASKSS_2                0x04000000U
-#define RTC_ALRMASSR_MASKSS_3                0x08000000U
-#define RTC_ALRMASSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
-#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
-#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
-#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
-#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
-#define RTC_ALRMBSSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_OR register  ****************/
-#define RTC_OR_TSINSEL                       0x00000006U
-#define RTC_OR_TSINSEL_0                     0x00000002U
-#define RTC_OR_TSINSEL_1                     0x00000004U
-#define RTC_OR_ALARMTYPE                     0x00000008U
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP20R register  ***************/
-#define RTC_BKP20R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP21R register  ***************/
-#define RTC_BKP21R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP22R register  ***************/
-#define RTC_BKP22R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP23R register  ***************/
-#define RTC_BKP23R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP24R register  ***************/
-#define RTC_BKP24R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP25R register  ***************/
-#define RTC_BKP25R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP26R register  ***************/
-#define RTC_BKP26R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP27R register  ***************/
-#define RTC_BKP27R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP28R register  ***************/
-#define RTC_BKP28R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP29R register  ***************/
-#define RTC_BKP29R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP30R register  ***************/
-#define RTC_BKP30R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP31R register  ***************/
-#define RTC_BKP31R                           0xFFFFFFFFU
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER                       0x00000020U
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Serial Audio Interface                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for SAI_GCR register  *******************/
-#define  SAI_GCR_SYNCIN                      0x00000003U        /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
-#define  SAI_GCR_SYNCIN_0                    0x00000001U        /*!<Bit 0 */
-#define  SAI_GCR_SYNCIN_1                    0x00000002U        /*!<Bit 1 */
-
-#define  SAI_GCR_SYNCOUT                     0x00000030U        /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
-#define  SAI_GCR_SYNCOUT_0                   0x00000010U        /*!<Bit 0 */
-#define  SAI_GCR_SYNCOUT_1                   0x00000020U        /*!<Bit 1 */
-
-/*******************  Bit definition for SAI_xCR1 register  *******************/
-#define  SAI_xCR1_MODE                       0x00000003U        /*!<MODE[1:0] bits (Audio Block Mode)           */
-#define  SAI_xCR1_MODE_0                     0x00000001U        /*!<Bit 0 */
-#define  SAI_xCR1_MODE_1                     0x00000002U        /*!<Bit 1 */
-
-#define  SAI_xCR1_PRTCFG                     0x0000000CU        /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
-#define  SAI_xCR1_PRTCFG_0                   0x00000004U        /*!<Bit 0 */
-#define  SAI_xCR1_PRTCFG_1                   0x00000008U        /*!<Bit 1 */
-
-#define  SAI_xCR1_DS                         0x000000E0U        /*!<DS[1:0] bits (Data Size) */
-#define  SAI_xCR1_DS_0                       0x00000020U        /*!<Bit 0 */
-#define  SAI_xCR1_DS_1                       0x00000040U        /*!<Bit 1 */
-#define  SAI_xCR1_DS_2                       0x00000080U        /*!<Bit 2 */
-
-#define  SAI_xCR1_LSBFIRST                   0x00000100U        /*!<LSB First Configuration  */
-#define  SAI_xCR1_CKSTR                      0x00000200U        /*!<ClocK STRobing edge      */
-
-#define  SAI_xCR1_SYNCEN                     0x00000C00U        /*!<SYNCEN[1:0](SYNChronization ENable) */
-#define  SAI_xCR1_SYNCEN_0                   0x00000400U        /*!<Bit 0 */
-#define  SAI_xCR1_SYNCEN_1                   0x00000800U        /*!<Bit 1 */
-
-#define  SAI_xCR1_MONO                       0x00001000U        /*!<Mono mode                  */
-#define  SAI_xCR1_OUTDRIV                    0x00002000U        /*!<Output Drive               */
-#define  SAI_xCR1_SAIEN                      0x00010000U        /*!<Audio Block enable         */
-#define  SAI_xCR1_DMAEN                      0x00020000U        /*!<DMA enable                 */
-#define  SAI_xCR1_NODIV                      0x00080000U        /*!<No Divider Configuration   */
-
-#define  SAI_xCR1_MCKDIV                     0x00F00000U        /*!<MCKDIV[3:0] (Master ClocK Divider)  */
-#define  SAI_xCR1_MCKDIV_0                   0x00100000U        /*!<Bit 0  */
-#define  SAI_xCR1_MCKDIV_1                   0x00200000U        /*!<Bit 1  */
-#define  SAI_xCR1_MCKDIV_2                   0x00400000U        /*!<Bit 2  */
-#define  SAI_xCR1_MCKDIV_3                   0x00800000U        /*!<Bit 3  */
-
-/*******************  Bit definition for SAI_xCR2 register  *******************/
-#define  SAI_xCR2_FTH                        0x00000007U        /*!<FTH[2:0](Fifo THreshold)  */
-#define  SAI_xCR2_FTH_0                      0x00000001U        /*!<Bit 0 */
-#define  SAI_xCR2_FTH_1                      0x00000002U        /*!<Bit 1 */
-#define  SAI_xCR2_FTH_2                      0x00000004U        /*!<Bit 2 */
-
-#define  SAI_xCR2_FFLUSH                     0x00000008U        /*!<Fifo FLUSH                       */
-#define  SAI_xCR2_TRIS                       0x00000010U        /*!<TRIState Management on data line */
-#define  SAI_xCR2_MUTE                       0x00000020U        /*!<Mute mode                        */
-#define  SAI_xCR2_MUTEVAL                    0x00000040U        /*!<Muate value                      */
-
-#define  SAI_xCR2_MUTECNT                    0x00001F80U       /*!<MUTECNT[5:0] (MUTE counter) */
-#define  SAI_xCR2_MUTECNT_0                  0x00000080U        /*!<Bit 0 */
-#define  SAI_xCR2_MUTECNT_1                  0x00000100U        /*!<Bit 1 */
-#define  SAI_xCR2_MUTECNT_2                  0x00000200U        /*!<Bit 2 */
-#define  SAI_xCR2_MUTECNT_3                  0x00000400U        /*!<Bit 3 */
-#define  SAI_xCR2_MUTECNT_4                  0x00000800U        /*!<Bit 4 */
-#define  SAI_xCR2_MUTECNT_5                  0x00001000U        /*!<Bit 5 */
-
-#define  SAI_xCR2_CPL                        0x00002000U        /*!< Complement Bit             */
-
-#define  SAI_xCR2_COMP                       0x0000C000U        /*!<COMP[1:0] (Companding mode) */
-#define  SAI_xCR2_COMP_0                     0x00004000U        /*!<Bit 0 */
-#define  SAI_xCR2_COMP_1                     0x00008000U        /*!<Bit 1 */
-
-/******************  Bit definition for SAI_xFRCR register  *******************/
-#define  SAI_xFRCR_FRL                       0x000000FFU        /*!<FRL[1:0](Frame length)  */
-#define  SAI_xFRCR_FRL_0                     0x00000001U        /*!<Bit 0 */
-#define  SAI_xFRCR_FRL_1                     0x00000002U        /*!<Bit 1 */
-#define  SAI_xFRCR_FRL_2                     0x00000004U        /*!<Bit 2 */
-#define  SAI_xFRCR_FRL_3                     0x00000008U        /*!<Bit 3 */
-#define  SAI_xFRCR_FRL_4                     0x00000010U        /*!<Bit 4 */
-#define  SAI_xFRCR_FRL_5                     0x00000020U        /*!<Bit 5 */
-#define  SAI_xFRCR_FRL_6                     0x00000040U        /*!<Bit 6 */
-#define  SAI_xFRCR_FRL_7                     0x00000080U        /*!<Bit 7 */
-
-#define  SAI_xFRCR_FSALL                     0x00007F00U        /*!<FRL[1:0] (Frame synchronization active level length)  */
-#define  SAI_xFRCR_FSALL_0                   0x00000100U        /*!<Bit 0 */
-#define  SAI_xFRCR_FSALL_1                   0x00000200U        /*!<Bit 1 */
-#define  SAI_xFRCR_FSALL_2                   0x00000400U        /*!<Bit 2 */
-#define  SAI_xFRCR_FSALL_3                   0x00000800U        /*!<Bit 3 */
-#define  SAI_xFRCR_FSALL_4                   0x00001000U        /*!<Bit 4 */
-#define  SAI_xFRCR_FSALL_5                   0x00002000U        /*!<Bit 5 */
-#define  SAI_xFRCR_FSALL_6                   0x00004000U        /*!<Bit 6 */
-
-#define  SAI_xFRCR_FSDEF                     0x00010000U        /*!<Frame Synchronization Definition  */
-#define  SAI_xFRCR_FSPOL                     0x00020000U        /*!<Frame Synchronization POLarity    */
-#define  SAI_xFRCR_FSOFF                     0x00040000U        /*!<Frame Synchronization OFFset      */
-
-/* Legacy define */
-#define  SAI_xFRCR_FSPO                      SAI_xFRCR_FSPOL
-
-/******************  Bit definition for SAI_xSLOTR register  *******************/
-#define  SAI_xSLOTR_FBOFF                    0x0000001FU        /*!<FRL[4:0](First Bit Offset)  */
-#define  SAI_xSLOTR_FBOFF_0                  0x00000001U        /*!<Bit 0 */
-#define  SAI_xSLOTR_FBOFF_1                  0x00000002U        /*!<Bit 1 */
-#define  SAI_xSLOTR_FBOFF_2                  0x00000004U        /*!<Bit 2 */
-#define  SAI_xSLOTR_FBOFF_3                  0x00000008U        /*!<Bit 3 */
-#define  SAI_xSLOTR_FBOFF_4                  0x00000010U        /*!<Bit 4 */
-
-#define  SAI_xSLOTR_SLOTSZ                   0x000000C0U        /*!<SLOTSZ[1:0] (Slot size)  */
-#define  SAI_xSLOTR_SLOTSZ_0                 0x00000040U        /*!<Bit 0 */
-#define  SAI_xSLOTR_SLOTSZ_1                 0x00000080U        /*!<Bit 1 */
-
-#define  SAI_xSLOTR_NBSLOT                   0x00000F00U        /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
-#define  SAI_xSLOTR_NBSLOT_0                 0x00000100U        /*!<Bit 0 */
-#define  SAI_xSLOTR_NBSLOT_1                 0x00000200U        /*!<Bit 1 */
-#define  SAI_xSLOTR_NBSLOT_2                 0x00000400U        /*!<Bit 2 */
-#define  SAI_xSLOTR_NBSLOT_3                 0x00000800U        /*!<Bit 3 */
-
-#define  SAI_xSLOTR_SLOTEN                   0xFFFF0000U        /*!<SLOTEN[15:0] (Slot Enable)  */
-
-/*******************  Bit definition for SAI_xIMR register  *******************/
-#define  SAI_xIMR_OVRUDRIE                   0x00000001U        /*!<Overrun underrun interrupt enable                              */
-#define  SAI_xIMR_MUTEDETIE                  0x00000002U        /*!<Mute detection interrupt enable                                */
-#define  SAI_xIMR_WCKCFGIE                   0x00000004U        /*!<Wrong Clock Configuration interrupt enable                     */
-#define  SAI_xIMR_FREQIE                     0x00000008U        /*!<FIFO request interrupt enable                                  */
-#define  SAI_xIMR_CNRDYIE                    0x00000010U        /*!<Codec not ready interrupt enable                               */
-#define  SAI_xIMR_AFSDETIE                   0x00000020U        /*!<Anticipated frame synchronization detection interrupt enable   */
-#define  SAI_xIMR_LFSDETIE                   0x00000040U        /*!<Late frame synchronization detection interrupt enable          */
-
-/********************  Bit definition for SAI_xSR register  *******************/
-#define  SAI_xSR_OVRUDR                      0x00000001U         /*!<Overrun underrun                               */
-#define  SAI_xSR_MUTEDET                     0x00000002U         /*!<Mute detection                                 */
-#define  SAI_xSR_WCKCFG                      0x00000004U         /*!<Wrong Clock Configuration                      */
-#define  SAI_xSR_FREQ                        0x00000008U         /*!<FIFO request                                   */
-#define  SAI_xSR_CNRDY                       0x00000010U         /*!<Codec not ready                                */
-#define  SAI_xSR_AFSDET                      0x00000020U         /*!<Anticipated frame synchronization detection    */
-#define  SAI_xSR_LFSDET                      0x00000040U         /*!<Late frame synchronization detection           */
-
-#define  SAI_xSR_FLVL                        0x00070000U         /*!<FLVL[2:0] (FIFO Level Threshold)               */
-#define  SAI_xSR_FLVL_0                      0x00010000U         /*!<Bit 0 */
-#define  SAI_xSR_FLVL_1                      0x00020000U         /*!<Bit 1 */
-#define  SAI_xSR_FLVL_2                      0x00040000U         /*!<Bit 2 */
-
-/******************  Bit definition for SAI_xCLRFR register  ******************/
-#define  SAI_xCLRFR_COVRUDR                  0x00000001U        /*!<Clear Overrun underrun                               */
-#define  SAI_xCLRFR_CMUTEDET                 0x00000002U        /*!<Clear Mute detection                                 */
-#define  SAI_xCLRFR_CWCKCFG                  0x00000004U        /*!<Clear Wrong Clock Configuration                      */
-#define  SAI_xCLRFR_CFREQ                    0x00000008U        /*!<Clear FIFO request                                   */
-#define  SAI_xCLRFR_CCNRDY                   0x00000010U        /*!<Clear Codec not ready                                */
-#define  SAI_xCLRFR_CAFSDET                  0x00000020U        /*!<Clear Anticipated frame synchronization detection    */
-#define  SAI_xCLRFR_CLFSDET                  0x00000040U        /*!<Clear Late frame synchronization detection           */
-
-/******************  Bit definition for SAI_xDR register  *********************/
-#define  SAI_xDR_DATA                        0xFFFFFFFFU
-
-/******************************************************************************/
-/*                                                                            */
-/*                              SPDIF-RX Interface                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for SPDIF_CR register  *******************/
-#define  SPDIFRX_CR_SPDIFEN                0x00000003U        /*!<Peripheral Block Enable                      */
-#define  SPDIFRX_CR_RXDMAEN                0x00000004U        /*!<Receiver DMA Enable for data flow            */
-#define  SPDIFRX_CR_RXSTEO                 0x00000008U        /*!<Stereo Mode                                  */
-#define  SPDIFRX_CR_DRFMT                  0x00000030U        /*!<RX Data format                               */
-#define  SPDIFRX_CR_PMSK                   0x00000040U        /*!<Mask Parity error bit                        */
-#define  SPDIFRX_CR_VMSK                   0x00000080U        /*!<Mask of Validity bit                         */
-#define  SPDIFRX_CR_CUMSK                  0x00000100U        /*!<Mask of channel status and user bits         */
-#define  SPDIFRX_CR_PTMSK                  0x00000200U        /*!<Mask of Preamble Type bits                   */
-#define  SPDIFRX_CR_CBDMAEN                0x00000400U        /*!<Control Buffer DMA ENable for control flow   */
-#define  SPDIFRX_CR_CHSEL                  0x00000800U        /*!<Channel Selection                            */
-#define  SPDIFRX_CR_NBTR                   0x00003000U        /*!<Maximum allowed re-tries during synchronization phase */
-#define  SPDIFRX_CR_WFA                    0x00004000U        /*!<Wait For Activity     */
-#define  SPDIFRX_CR_INSEL                  0x00070000U        /*!<SPDIF input selection */
-
-/*******************  Bit definition for SPDIFRX_IMR register  *******************/
-#define  SPDIFRX_IMR_RXNEIE                0x00000001U        /*!<RXNE interrupt enable                              */
-#define  SPDIFRX_IMR_CSRNEIE               0x00000002U        /*!<Control Buffer Ready Interrupt Enable              */
-#define  SPDIFRX_IMR_PERRIE                0x00000004U        /*!<Parity error interrupt enable                      */
-#define  SPDIFRX_IMR_OVRIE                 0x00000008U        /*!<Overrun error Interrupt Enable                     */
-#define  SPDIFRX_IMR_SBLKIE                0x00000010U        /*!<Synchronization Block Detected Interrupt Enable    */
-#define  SPDIFRX_IMR_SYNCDIE               0x00000020U        /*!<Synchronization Done                               */
-#define  SPDIFRX_IMR_IFEIE                 0x00000040U        /*!<Serial Interface Error Interrupt Enable            */
-
-/*******************  Bit definition for SPDIFRX_SR register  *******************/
-#define  SPDIFRX_SR_RXNE                   0x00000001U       /*!<Read data register not empty                          */
-#define  SPDIFRX_SR_CSRNE                  0x00000002U       /*!<The Control Buffer register is not empty              */
-#define  SPDIFRX_SR_PERR                   0x00000004U       /*!<Parity error                                          */
-#define  SPDIFRX_SR_OVR                    0x00000008U       /*!<Overrun error                                         */
-#define  SPDIFRX_SR_SBD                    0x00000010U       /*!<Synchronization Block Detected                        */
-#define  SPDIFRX_SR_SYNCD                  0x00000020U       /*!<Synchronization Done                                  */
-#define  SPDIFRX_SR_FERR                   0x00000040U       /*!<Framing error                                         */
-#define  SPDIFRX_SR_SERR                   0x00000080U       /*!<Synchronization error                                 */
-#define  SPDIFRX_SR_TERR                   0x00000100U       /*!<Time-out error                                        */
-#define  SPDIFRX_SR_WIDTH5                 0x7FFF0000U       /*!<Duration of 5 symbols counted with spdif_clk          */
-
-/*******************  Bit definition for SPDIFRX_IFCR register  *******************/
-#define  SPDIFRX_IFCR_PERRCF               0x00000004U       /*!<Clears the Parity error flag                         */
-#define  SPDIFRX_IFCR_OVRCF                0x00000008U       /*!<Clears the Overrun error flag                        */
-#define  SPDIFRX_IFCR_SBDCF                0x00000010U       /*!<Clears the Synchronization Block Detected flag       */
-#define  SPDIFRX_IFCR_SYNCDCF              0x00000020U       /*!<Clears the Synchronization Done flag                 */
-
-/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/
-#define  SPDIFRX_DR0_DR                    0x00FFFFFFU        /*!<Data value            */
-#define  SPDIFRX_DR0_PE                    0x01000000U        /*!<Parity Error bit      */
-#define  SPDIFRX_DR0_V                     0x02000000U        /*!<Validity bit          */
-#define  SPDIFRX_DR0_U                     0x04000000U        /*!<User bit              */
-#define  SPDIFRX_DR0_C                     0x08000000U        /*!<Channel Status bit    */
-#define  SPDIFRX_DR0_PT                    0x30000000U        /*!<Preamble Type         */
-
-/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/
-#define  SPDIFRX_DR1_DR                    0xFFFFFF00U        /*!<Data value            */
-#define  SPDIFRX_DR1_PT                    0x00000030U        /*!<Preamble Type         */
-#define  SPDIFRX_DR1_C                     0x00000008U        /*!<Channel Status bit    */
-#define  SPDIFRX_DR1_U                     0x00000004U        /*!<User bit              */
-#define  SPDIFRX_DR1_V                     0x00000002U        /*!<Validity bit          */
-#define  SPDIFRX_DR1_PE                    0x00000001U        /*!<Parity Error bit      */
-
-/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/
-#define  SPDIFRX_DR1_DRNL1                 0xFFFF0000U        /*!<Data value Channel B      */
-#define  SPDIFRX_DR1_DRNL2                 0x0000FFFFU        /*!<Data value Channel A      */
-
-/*******************  Bit definition for SPDIFRX_CSR register   *******************/
-#define  SPDIFRX_CSR_USR                   0x0000FFFFU        /*!<User data information           */
-#define  SPDIFRX_CSR_CS                    0x00FF0000U        /*!<Channel A status information    */
-#define  SPDIFRX_CSR_SOB                   0x01000000U        /*!<Start Of Block                  */
-
-/*******************  Bit definition for SPDIFRX_DIR register    *******************/
-#define  SPDIFRX_DIR_THI                   0x000013FFU        /*!<Threshold LOW      */
-#define  SPDIFRX_DIR_TLO                   0x1FFF0000U        /*!<Threshold HIGH     */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          SD host Interface                                 */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SDMMC_POWER register  ******************/
-#define  SDMMC_POWER_PWRCTRL                  0x03U               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDMMC_POWER_PWRCTRL_0                0x01U               /*!<Bit 0 */
-#define  SDMMC_POWER_PWRCTRL_1                0x02U               /*!<Bit 1 */
-
-/******************  Bit definition for SDMMC_CLKCR register  ******************/
-#define  SDMMC_CLKCR_CLKDIV                   0x00FFU            /*!<Clock divide factor             */
-#define  SDMMC_CLKCR_CLKEN                    0x0100U            /*!<Clock enable bit                */
-#define  SDMMC_CLKCR_PWRSAV                   0x0200U            /*!<Power saving configuration bit  */
-#define  SDMMC_CLKCR_BYPASS                   0x0400U            /*!<Clock divider bypass enable bit */
-
-#define  SDMMC_CLKCR_WIDBUS                   0x1800U            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDMMC_CLKCR_WIDBUS_0                 0x0800U            /*!<Bit 0 */
-#define  SDMMC_CLKCR_WIDBUS_1                 0x1000U            /*!<Bit 1 */
-
-#define  SDMMC_CLKCR_NEGEDGE                  0x2000U            /*!<SDMMC_CK dephasing selection bit */
-#define  SDMMC_CLKCR_HWFC_EN                  0x4000U            /*!<HW Flow Control enable          */
-
-/*******************  Bit definition for SDMMC_ARG register  *******************/
-#define  SDMMC_ARG_CMDARG                     0xFFFFFFFFU            /*!<Command argument */
-
-/*******************  Bit definition for SDMMC_CMD register  *******************/
-#define  SDMMC_CMD_CMDINDEX                   0x003FU            /*!<Command Index                               */
-
-#define  SDMMC_CMD_WAITRESP                   0x00C0U            /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDMMC_CMD_WAITRESP_0                 0x0040U            /*!< Bit 0 */
-#define  SDMMC_CMD_WAITRESP_1                 0x0080U            /*!< Bit 1 */
-
-#define  SDMMC_CMD_WAITINT                    0x0100U            /*!<CPSM Waits for Interrupt Request                               */
-#define  SDMMC_CMD_WAITPEND                   0x0200U            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDMMC_CMD_CPSMEN                     0x0400U            /*!<Command path state machine (CPSM) Enable bit                   */
-#define  SDMMC_CMD_SDIOSUSPEND                0x0800U            /*!<SD I/O suspend command                                         */
-
-/*****************  Bit definition for SDMMC_RESPCMD register  *****************/
-#define  SDMMC_RESPCMD_RESPCMD                0x3FU               /*!<Response command index */
-
-/******************  Bit definition for SDMMC_RESP0 register  ******************/
-#define  SDMMC_RESP0_CARDSTATUS0              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDMMC_RESP1 register  ******************/
-#define  SDMMC_RESP1_CARDSTATUS1              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDMMC_RESP2 register  ******************/
-#define  SDMMC_RESP2_CARDSTATUS2              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDMMC_RESP3 register  ******************/
-#define  SDMMC_RESP3_CARDSTATUS3              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDMMC_RESP4 register  ******************/
-#define  SDMMC_RESP4_CARDSTATUS4              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDMMC_DTIMER register  *****************/
-#define  SDMMC_DTIMER_DATATIME                0xFFFFFFFFU        /*!<Data timeout period. */
-
-/******************  Bit definition for SDMMC_DLEN register  *******************/
-#define  SDMMC_DLEN_DATALENGTH                0x01FFFFFFU        /*!<Data length value    */
-
-/******************  Bit definition for SDMMC_DCTRL register  ******************/
-#define  SDMMC_DCTRL_DTEN                     0x0001U            /*!<Data transfer enabled bit         */
-#define  SDMMC_DCTRL_DTDIR                    0x0002U            /*!<Data transfer direction selection */
-#define  SDMMC_DCTRL_DTMODE                   0x0004U            /*!<Data transfer mode selection      */
-#define  SDMMC_DCTRL_DMAEN                    0x0008U            /*!<DMA enabled bit                   */
-
-#define  SDMMC_DCTRL_DBLOCKSIZE               0x00F0U            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDMMC_DCTRL_DBLOCKSIZE_0             0x0010U            /*!<Bit 0 */
-#define  SDMMC_DCTRL_DBLOCKSIZE_1             0x0020U            /*!<Bit 1 */
-#define  SDMMC_DCTRL_DBLOCKSIZE_2             0x0040U            /*!<Bit 2 */
-#define  SDMMC_DCTRL_DBLOCKSIZE_3             0x0080U            /*!<Bit 3 */
-
-#define  SDMMC_DCTRL_RWSTART                  0x0100U            /*!<Read wait start         */
-#define  SDMMC_DCTRL_RWSTOP                   0x0200U            /*!<Read wait stop          */
-#define  SDMMC_DCTRL_RWMOD                    0x0400U            /*!<Read wait mode          */
-#define  SDMMC_DCTRL_SDIOEN                   0x0800U            /*!<SD I/O enable functions */
-
-/******************  Bit definition for SDMMC_DCOUNT register  *****************/
-#define  SDMMC_DCOUNT_DATACOUNT               0x01FFFFFFU        /*!<Data count value */
-
-/******************  Bit definition for SDMMC_STA registe  ********************/
-#define  SDMMC_STA_CCRCFAIL                   0x00000001U        /*!<Command response received (CRC check failed)  */
-#define  SDMMC_STA_DCRCFAIL                   0x00000002U        /*!<Data block sent/received (CRC check failed)   */
-#define  SDMMC_STA_CTIMEOUT                   0x00000004U        /*!<Command response timeout                      */
-#define  SDMMC_STA_DTIMEOUT                   0x00000008U        /*!<Data timeout                                  */
-#define  SDMMC_STA_TXUNDERR                   0x00000010U        /*!<Transmit FIFO underrun error                  */
-#define  SDMMC_STA_RXOVERR                    0x00000020U        /*!<Received FIFO overrun error                   */
-#define  SDMMC_STA_CMDREND                    0x00000040U        /*!<Command response received (CRC check passed)  */
-#define  SDMMC_STA_CMDSENT                    0x00000080U        /*!<Command sent (no response required)           */
-#define  SDMMC_STA_DATAEND                    0x00000100U        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
-#define  SDMMC_STA_DBCKEND                    0x00000400U        /*!<Data block sent/received (CRC check passed)   */
-#define  SDMMC_STA_CMDACT                     0x00000800U        /*!<Command transfer in progress                  */
-#define  SDMMC_STA_TXACT                      0x00001000U        /*!<Data transmit in progress                     */
-#define  SDMMC_STA_RXACT                      0x00002000U        /*!<Data receive in progress                      */
-#define  SDMMC_STA_TXFIFOHE                   0x00004000U        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDMMC_STA_RXFIFOHF                   0x00008000U        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDMMC_STA_TXFIFOF                    0x00010000U        /*!<Transmit FIFO full                            */
-#define  SDMMC_STA_RXFIFOF                    0x00020000U        /*!<Receive FIFO full                             */
-#define  SDMMC_STA_TXFIFOE                    0x00040000U        /*!<Transmit FIFO empty                           */
-#define  SDMMC_STA_RXFIFOE                    0x00080000U        /*!<Receive FIFO empty                            */
-#define  SDMMC_STA_TXDAVL                     0x00100000U        /*!<Data available in transmit FIFO               */
-#define  SDMMC_STA_RXDAVL                     0x00200000U        /*!<Data available in receive FIFO                */
-#define  SDMMC_STA_SDIOIT                     0x00400000U        /*!<SDMMC interrupt received                       */
-
-/*******************  Bit definition for SDMMC_ICR register  *******************/
-#define  SDMMC_ICR_CCRCFAILC                  0x00000001U        /*!<CCRCFAIL flag clear bit */
-#define  SDMMC_ICR_DCRCFAILC                  0x00000002U        /*!<DCRCFAIL flag clear bit */
-#define  SDMMC_ICR_CTIMEOUTC                  0x00000004U        /*!<CTIMEOUT flag clear bit */
-#define  SDMMC_ICR_DTIMEOUTC                  0x00000008U        /*!<DTIMEOUT flag clear bit */
-#define  SDMMC_ICR_TXUNDERRC                  0x00000010U        /*!<TXUNDERR flag clear bit */
-#define  SDMMC_ICR_RXOVERRC                   0x00000020U        /*!<RXOVERR flag clear bit  */
-#define  SDMMC_ICR_CMDRENDC                   0x00000040U        /*!<CMDREND flag clear bit  */
-#define  SDMMC_ICR_CMDSENTC                   0x00000080U        /*!<CMDSENT flag clear bit  */
-#define  SDMMC_ICR_DATAENDC                   0x00000100U        /*!<DATAEND flag clear bit  */
-#define  SDMMC_ICR_DBCKENDC                   0x00000400U        /*!<DBCKEND flag clear bit  */
-#define  SDMMC_ICR_SDIOITC                    0x00400000U        /*!<SDMMCIT flag clear bit   */
-
-/******************  Bit definition for SDMMC_MASK register  *******************/
-#define  SDMMC_MASK_CCRCFAILIE                0x00000001U        /*!<Command CRC Fail Interrupt Enable          */
-#define  SDMMC_MASK_DCRCFAILIE                0x00000002U        /*!<Data CRC Fail Interrupt Enable             */
-#define  SDMMC_MASK_CTIMEOUTIE                0x00000004U        /*!<Command TimeOut Interrupt Enable           */
-#define  SDMMC_MASK_DTIMEOUTIE                0x00000008U        /*!<Data TimeOut Interrupt Enable              */
-#define  SDMMC_MASK_TXUNDERRIE                0x00000010U        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
-#define  SDMMC_MASK_RXOVERRIE                 0x00000020U        /*!<Rx FIFO OverRun Error Interrupt Enable     */
-#define  SDMMC_MASK_CMDRENDIE                 0x00000040U        /*!<Command Response Received Interrupt Enable */
-#define  SDMMC_MASK_CMDSENTIE                 0x00000080U        /*!<Command Sent Interrupt Enable              */
-#define  SDMMC_MASK_DATAENDIE                 0x00000100U        /*!<Data End Interrupt Enable                  */
-#define  SDMMC_MASK_DBCKENDIE                 0x00000400U        /*!<Data Block End Interrupt Enable            */
-#define  SDMMC_MASK_CMDACTIE                  0x00000800U        /*!<CCommand Acting Interrupt Enable           */
-#define  SDMMC_MASK_TXACTIE                   0x00001000U        /*!<Data Transmit Acting Interrupt Enable      */
-#define  SDMMC_MASK_RXACTIE                   0x00002000U        /*!<Data receive acting interrupt enabled      */
-#define  SDMMC_MASK_TXFIFOHEIE                0x00004000U        /*!<Tx FIFO Half Empty interrupt Enable        */
-#define  SDMMC_MASK_RXFIFOHFIE                0x00008000U        /*!<Rx FIFO Half Full interrupt Enable         */
-#define  SDMMC_MASK_TXFIFOFIE                 0x00010000U        /*!<Tx FIFO Full interrupt Enable              */
-#define  SDMMC_MASK_RXFIFOFIE                 0x00020000U        /*!<Rx FIFO Full interrupt Enable              */
-#define  SDMMC_MASK_TXFIFOEIE                 0x00040000U        /*!<Tx FIFO Empty interrupt Enable             */
-#define  SDMMC_MASK_RXFIFOEIE                 0x00080000U        /*!<Rx FIFO Empty interrupt Enable             */
-#define  SDMMC_MASK_TXDAVLIE                  0x00100000U        /*!<Data available in Tx FIFO interrupt Enable */
-#define  SDMMC_MASK_RXDAVLIE                  0x00200000U        /*!<Data available in Rx FIFO interrupt Enable */
-#define  SDMMC_MASK_SDIOITIE                  0x00400000U        /*!<SDMMC Mode Interrupt Received interrupt Enable */
-
-/*****************  Bit definition for SDMMC_FIFOCNT register  *****************/
-#define  SDMMC_FIFOCNT_FIFOCOUNT              0x00FFFFFFU        /*!<Remaining number of words to be written to or read from the FIFO */
-
-/******************  Bit definition for SDMMC_FIFO register  *******************/
-#define  SDMMC_FIFO_FIFODATA                  0xFFFFFFFFU        /*!<Receive and transmit FIFO data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface (SPI)                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        0x00000001U        /*!< Clock Phase                        */
-#define  SPI_CR1_CPOL                        0x00000002U        /*!< Clock Polarity                     */
-#define  SPI_CR1_MSTR                        0x00000004U        /*!< Master Selection                   */
-#define  SPI_CR1_BR                          0x00000038U        /*!< BR[2:0] bits (Baud Rate Control)   */
-#define  SPI_CR1_BR_0                        0x00000008U        /*!< Bit 0 */
-#define  SPI_CR1_BR_1                        0x00000010U        /*!< Bit 1 */
-#define  SPI_CR1_BR_2                        0x00000020U        /*!< Bit 2 */
-#define  SPI_CR1_SPE                         0x00000040U        /*!< SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    0x00000080U        /*!< Frame Format                        */
-#define  SPI_CR1_SSI                         0x00000100U        /*!< Internal slave select               */
-#define  SPI_CR1_SSM                         0x00000200U        /*!< Software slave management           */
-#define  SPI_CR1_RXONLY                      0x00000400U        /*!< Receive only                        */
-#define  SPI_CR1_CRCL                        0x00000800U        /*!< CRC Length                          */
-#define  SPI_CR1_CRCNEXT                     0x00001000U        /*!< Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       0x00002000U        /*!< Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      0x00004000U        /*!< Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    0x00008000U        /*!< Bidirectional data mode enable      */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     0x00000001U        /*!< Rx Buffer DMA Enable                 */
-#define  SPI_CR2_TXDMAEN                     0x00000002U        /*!< Tx Buffer DMA Enable                 */
-#define  SPI_CR2_SSOE                        0x00000004U        /*!< SS Output Enable                     */
-#define  SPI_CR2_NSSP                        0x00000008U        /*!< NSS pulse management Enable          */
-#define  SPI_CR2_FRF                         0x00000010U        /*!< Frame Format Enable                  */
-#define  SPI_CR2_ERRIE                       0x00000020U        /*!< Error Interrupt Enable               */
-#define  SPI_CR2_RXNEIE                      0x00000040U        /*!< RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       0x00000080U        /*!< Tx buffer Empty Interrupt Enable     */
-#define  SPI_CR2_DS                          0x00000F00U        /*!< DS[3:0] Data Size                    */
-#define  SPI_CR2_DS_0                        0x00000100U        /*!< Bit 0 */
-#define  SPI_CR2_DS_1                        0x00000200U        /*!< Bit 1 */
-#define  SPI_CR2_DS_2                        0x00000400U        /*!< Bit 2 */
-#define  SPI_CR2_DS_3                        0x00000800U        /*!< Bit 3 */
-#define  SPI_CR2_FRXTH                       0x00001000U        /*!< FIFO reception Threshold           */
-#define  SPI_CR2_LDMARX                      0x00002000U        /*!< Last DMA transfer for reception    */
-#define  SPI_CR2_LDMATX                      0x00004000U        /*!< Last DMA transfer for transmission */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         0x00000001U        /*!< Receive buffer Not Empty  */
-#define  SPI_SR_TXE                          0x00000002U        /*!< Transmit buffer Empty     */
-#define  SPI_SR_CHSIDE                       0x00000004U        /*!< Channel side              */
-#define  SPI_SR_UDR                          0x00000008U        /*!< Underrun flag             */
-#define  SPI_SR_CRCERR                       0x00000010U        /*!< CRC Error flag            */
-#define  SPI_SR_MODF                         0x00000020U        /*!< Mode fault                */
-#define  SPI_SR_OVR                          0x00000040U        /*!< Overrun flag              */
-#define  SPI_SR_BSY                          0x00000080U        /*!< Busy flag                 */
-#define  SPI_SR_FRE                          0x00000100U        /*!< TI frame format error     */
-#define  SPI_SR_FRLVL                        0x00000600U        /*!< FIFO Reception Level      */
-#define  SPI_SR_FRLVL_0                      0x00000200U        /*!< Bit 0 */
-#define  SPI_SR_FRLVL_1                      0x00000400U        /*!< Bit 1 */
-#define  SPI_SR_FTLVL                        0x00001800U        /*!< FIFO Transmission Level   */
-#define  SPI_SR_FTLVL_0                      0x00000800U        /*!< Bit 0 */
-#define  SPI_SR_FTLVL_1                      0x00001000U        /*!< Bit 1 */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           0xFFFFU            /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   0xFFFFU            /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    0xFFFFU            /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    0xFFFFU            /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   0x00000001U        /*!<Channel length (number of bits per audio channel) */
-#define  SPI_I2SCFGR_DATLEN                  0x00000006U        /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define  SPI_I2SCFGR_DATLEN_0                0x00000002U        /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                0x00000004U        /*!<Bit 1 */
-#define  SPI_I2SCFGR_CKPOL                   0x00000008U        /*!<steady state clock polarity                       */
-#define  SPI_I2SCFGR_I2SSTD                  0x00000030U        /*!<I2SSTD[1:0] bits (I2S standard selection)         */
-#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U        /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U        /*!<Bit 1 */
-#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U        /*!<PCM frame synchronization                         */
-#define  SPI_I2SCFGR_I2SCFG                  0x00000300U        /*!<I2SCFG[1:0] bits (I2S configuration mode)         */
-#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U        /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U        /*!<Bit 1 */
-#define  SPI_I2SCFGR_I2SE                    0x00000400U        /*!<I2S Enable                                        */
-#define  SPI_I2SCFGR_I2SMOD                  0x00000800U        /*!<I2S mode selection                                */
-#define  SPI_I2SCFGR_ASTRTEN                 0x00001000U        /*!<Asynchronous start enable                        */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    0x00FFU            /*!<I2S Linear prescaler         */
-#define  SPI_I2SPR_ODD                       0x0100U            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     0x0200U            /*!<Master Clock Output Enable   */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 SYSCFG                                     */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SYSCFG_MEMRMP register  ***************/
-#define SYSCFG_MEMRMP_MEM_BOOT         0x00000001U /*!< Boot information after Reset */
-
-#define SYSCFG_MEMRMP_SWP_FB           0x00000100U /*!< User Flash Bank swap    */
-
-#define SYSCFG_MEMRMP_SWP_FMC          0x00000C00U /*!< FMC Memory Mapping swapping */
-#define SYSCFG_MEMRMP_SWP_FMC_0        0x00000400U
-#define SYSCFG_MEMRMP_SWP_FMC_1        0x00000800U
-
-/******************  Bit definition for SYSCFG_PMC register  ******************/
-#define SYSCFG_PMC_I2C1_FMP             0x00000001U /*!< I2C1_FMP I2C1 Fast Mode + Enable */
-#define SYSCFG_PMC_I2C2_FMP             0x00000002U /*!< I2C2_FMP I2C2 Fast Mode + Enable */
-#define SYSCFG_PMC_I2C3_FMP             0x00000004U /*!< I2C3_FMP I2C3 Fast Mode + Enable */
-#define SYSCFG_PMC_I2C4_FMP             0x00000008U /*!< I2C4_FMP I2C4 Fast Mode + Enable */
-#define SYSCFG_PMC_I2C_PB6_FMP          0x00000010U /*!< PB6_FMP Fast Mode + Enable */
-#define SYSCFG_PMC_I2C_PB7_FMP          0x00000020U /*!< PB7_FMP Fast Mode + Enable */
-#define SYSCFG_PMC_I2C_PB8_FMP          0x00000040U /*!< PB8_FMP Fast Mode + Enable */
-#define SYSCFG_PMC_I2C_PB9_FMP          0x00000080U /*!< PB9_FMP Fast Mode + Enable */
-
-#define SYSCFG_PMC_ADCxDC2              0x00070000U /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC1DC2              0x00010000U /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC2DC2              0x00020000U /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC3DC2              0x00040000U /*!< Refer to AN4073 on how to use this bit  */
-
-#define SYSCFG_PMC_MII_RMII_SEL         0x00800000U /*!<Ethernet PHY interface selection */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
-/**
-  * @brief   EXTI0 configuration
-  */
-#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         0x0003U /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         0x0004U /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         0x0005U /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         0x0006U /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PI         0x0008U /*!<PI[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PJ         0x0009U /*!<PJ[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PK         0x000AU /*!<PK[0] pin */
-
-/**
-  * @brief   EXTI1 configuration
-  */
-#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         0x0030U /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         0x0040U /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         0x0050U /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         0x0060U /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PI         0x0080U /*!<PI[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PJ         0x0090U /*!<PJ[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PK         0x00A0U /*!<PK[1] pin */
-
-/**
-  * @brief   EXTI2 configuration
-  */
-#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         0x0300U /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         0x0400U /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         0x0500U /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         0x0600U /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PI         0x0800U /*!<PI[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PJ         0x0900U /*!<PJ[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PK         0x0A00U /*!<PK[2] pin */
-
-/**
-  * @brief   EXTI3 configuration
-  */
-#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         0x3000U /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         0x4000U /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         0x5000U /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         0x6000U /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PI         0x8000U /*!<PI[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PJ         0x9000U /*!<PJ[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PK         0xA000U /*!<PK[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
-/**
-  * @brief   EXTI4 configuration
-  */
-#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         0x0003U /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         0x0004U /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         0x0005U /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         0x0006U /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PI         0x0008U /*!<PI[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PJ         0x0009U /*!<PJ[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PK         0x000AU /*!<PK[4] pin */
-
-/**
-  * @brief   EXTI5 configuration
-  */
-#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         0x0030U /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         0x0040U /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         0x0050U /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         0x0060U /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PI         0x0080U /*!<PI[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PJ         0x0090U /*!<PJ[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PK         0x00A0U /*!<PK[5] pin */
-
-/**
-  * @brief   EXTI6 configuration
-  */
-#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         0x0300U /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         0x0400U /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         0x0500U /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         0x0600U /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PI         0x0800U /*!<PI[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PJ         0x0900U /*!<PJ[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PK         0x0A00U /*!<PK[6] pin */
-
-/**
-  * @brief   EXTI7 configuration
-  */
-#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         0x3000U /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         0x4000U /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         0x5000U /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         0x6000U /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PI         0x8000U /*!<PI[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PJ         0x9000U /*!<PJ[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PK         0xA000U /*!<PK[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
-
-/**
-  * @brief   EXTI8 configuration
-  */
-#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         0x0003U /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         0x0004U /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         0x0005U /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         0x0006U /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PI         0x0008U /*!<PI[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PJ         0x0009U /*!<PJ[8] pin */
-
-/**
-  * @brief   EXTI9 configuration
-  */
-#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         0x0030U /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         0x0040U /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         0x0050U /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         0x0060U /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PI         0x0080U /*!<PI[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PJ         0x0090U /*!<PJ[9] pin */
-
-/**
-  * @brief   EXTI10 configuration
-  */
-#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        0x0300U /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        0x0400U /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        0x0500U /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        0x0600U /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PI        0x0800U /*!<PI[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PJ        0x0900U /*!<PJ[10] pin */
-
-/**
-  * @brief   EXTI11 configuration
-  */
-#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        0x3000U /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        0x4000U /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        0x5000U /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        0x6000U /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PI        0x8000U /*!<PI[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PJ        0x9000U /*!<PJ[11] pin */
-
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
-/**
-  * @brief   EXTI12 configuration
-  */
-#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        0x0003U /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        0x0004U /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        0x0005U /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        0x0006U /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PI        0x0008U /*!<PI[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PJ        0x0009U /*!<PJ[12] pin */
-
-/**
-  * @brief   EXTI13 configuration
-  */
-#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        0x0030U /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        0x0040U /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        0x0050U /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        0x0060U /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PI        0x0080U /*!<PI[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PJ        0x0090U /*!<PJ[13] pin */
-
-/**
-  * @brief   EXTI14 configuration
-  */
-#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        0x0300U /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        0x0400U /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        0x0500U /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        0x0600U /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PI        0x0800U /*!<PI[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PJ        0x0900U /*!<PJ[14] pin */
-
-/**
-  * @brief   EXTI15 configuration
-  */
-#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        0x3000U /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        0x4000U /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        0x5000U /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        0x6000U /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PI        0x8000U /*!<PI[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PJ        0x9000U /*!<PJ[15] pin */
-
-/******************  Bit definition for SYSCFG_CBR register  ******************/
-#define SYSCFG_CBR_CLL                  0x00000001U /*!<Core Lockup Lock */
-#define SYSCFG_CBR_PVDL                 0x00000004U /*!<PVD Lock         */
-
-/******************  Bit definition for SYSCFG_CMPCR register  ****************/
-#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell power-down */
-#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell ready flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    TIM                                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
-#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
-#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
-#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
-#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
-
-#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
-
-#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
-
-#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
-#define  TIM_CR1_UIFREMAP                    0x0800U            /*!<UIF status bit */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        0x00000001U            /*!<Capture/Compare Preloaded Control        */
-#define  TIM_CR2_CCUS                        0x00000004U            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        0x00000008U            /*!<Capture/Compare DMA Selection            */
-
-#define  TIM_CR2_OIS5                        0x00010000U            /*!<Output Idle state 4 (OC4 output) */
-#define  TIM_CR2_OIS6                        0x00040000U            /*!<Output Idle state 4 (OC4 output) */
-
-#define  TIM_CR2_MMS                         0x0070U           /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       0x0010U           /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       0x0020U           /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       0x0040U           /*!<Bit 2 */
-
-#define  TIM_CR2_MMS2                        0x00F00000U            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS2_0                      0x00100000U            /*!<Bit 0 */
-#define  TIM_CR2_MMS2_1                      0x00200000U            /*!<Bit 1 */
-#define  TIM_CR2_MMS2_2                      0x00400000U            /*!<Bit 2 */
-#define  TIM_CR2_MMS2_3                      0x00800000U            /*!<Bit 2 */
-
-#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
-#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
-#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
-#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        0x00010007U            /*!<SMS[2:0] bits (Slave mode selection)    */
-#define  TIM_SMCR_SMS_0                      0x00000001U            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      0x00000002U            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      0x00000004U            /*!<Bit 2 */
-#define  TIM_SMCR_SMS_3                      0x00010000U            /*!<Bit 3 */
-#define  TIM_SMCR_OCCS                       0x00000008U            /*!< OCREF clear selection */
-
-#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
-#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
-
-#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
-
-#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
-
-#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
-#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
-#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
-#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
-#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
-#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
-#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
-#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
-#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
-#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
-#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
-#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
-#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
-#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
-#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
-#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
-#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
-#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
-#define  TIM_SR_B2IF                         0x0100U            /*!<Break2 interrupt Flag               */
-#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          0x00000001U               /*!<Update Generation                         */
-#define  TIM_EGR_CC1G                        0x00000002U               /*!<Capture/Compare 1 Generation              */
-#define  TIM_EGR_CC2G                        0x00000004U               /*!<Capture/Compare 2 Generation              */
-#define  TIM_EGR_CC3G                        0x00000008U               /*!<Capture/Compare 3 Generation              */
-#define  TIM_EGR_CC4G                        0x00000010U               /*!<Capture/Compare 4 Generation              */
-#define  TIM_EGR_COMG                        0x00000020U               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          0x00000040U               /*!<Trigger Generation                        */
-#define  TIM_EGR_BG                          0x00000080U               /*!<Break Generation                          */
-#define  TIM_EGR_B2G                         0x00000100U              /*!<Break2 Generation                          */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      0x00000003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    0x00000001U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    0x00000002U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC1FE                     0x00000004U            /*!<Output Compare 1 Fast enable                 */
-#define  TIM_CCMR1_OC1PE                     0x00000008U            /*!<Output Compare 1 Preload enable              */
-
-#define  TIM_CCMR1_OC1M                      0x00010070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define  TIM_CCMR1_OC1M_0                    0x00000010U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    0x00000020U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    0x00000040U            /*!<Bit 2 */
-#define  TIM_CCMR1_OC1M_3                    0x00010000U            /*!<Bit 3 */
-
-#define  TIM_CCMR1_OC1CE                     0x00000080U            /*!<Output Compare 1Clear Enable                 */
-
-#define  TIM_CCMR1_CC2S                      0x00000300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    0x00000100U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    0x00000200U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC2FE                     0x00000400U            /*!<Output Compare 2 Fast enable                 */
-#define  TIM_CCMR1_OC2PE                     0x00000800U            /*!<Output Compare 2 Preload enable              */
-
-#define  TIM_CCMR1_OC2M                      0x01007000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define  TIM_CCMR1_OC2M_0                    0x00001000U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    0x00002000U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    0x00004000U            /*!<Bit 2 */
-#define  TIM_CCMR1_OC2M_3                    0x01000000U            /*!<Bit 3 */
-
-#define  TIM_CCMR1_OC2CE                     0x00008000U            /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      0x00000003U        /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define  TIM_CCMR2_CC3S_0                    0x00000001U        /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    0x00000002U        /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC3FE                     0x00000004U        /*!<Output Compare 3 Fast enable           */
-#define  TIM_CCMR2_OC3PE                     0x00000008U        /*!<Output Compare 3 Preload enable        */
-
-#define  TIM_CCMR2_OC3M                      0x00010070U        /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    0x00000010U        /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    0x00000020U        /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    0x00000040U        /*!<Bit 2 */
-#define  TIM_CCMR2_OC3M_3                    0x00010000U        /*!<Bit 3 */
-
-
-
-#define  TIM_CCMR2_OC3CE                     0x00000080U        /*!<Output Compare 3 Clear Enable */
-
-#define  TIM_CCMR2_CC4S                      0x00000300U        /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    0x00000100U        /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    0x00000200U        /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC4FE                     0x00000400U        /*!<Output Compare 4 Fast enable    */
-#define  TIM_CCMR2_OC4PE                     0x00000800U        /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR2_OC4M                      0x01007000U        /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    0x00001000U        /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    0x00002000U        /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    0x00004000U        /*!<Bit 2 */
-#define  TIM_CCMR2_OC4M_3                    0x01000000U        /*!<Bit 3 */
-
-#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       0x00000001U            /*!<Capture/Compare 1 output enable */
-#define  TIM_CCER_CC1P                       0x00000002U            /*!<Capture/Compare 1 output Polarity */
-#define  TIM_CCER_CC1NE                      0x00000004U            /*!<Capture/Compare 1 Complementary output enable */
-#define  TIM_CCER_CC1NP                      0x00000008U            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       0x00000010U            /*!<Capture/Compare 2 output enable */
-#define  TIM_CCER_CC2P                       0x00000020U            /*!<Capture/Compare 2 output Polarity */
-#define  TIM_CCER_CC2NE                      0x00000040U            /*!<Capture/Compare 2 Complementary output enable */
-#define  TIM_CCER_CC2NP                      0x00000080U            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       0x00000100U            /*!<Capture/Compare 3 output enable */
-#define  TIM_CCER_CC3P                       0x00000200U            /*!<Capture/Compare 3 output Polarity */
-#define  TIM_CCER_CC3NE                      0x00000400U            /*!<Capture/Compare 3 Complementary output enable */
-#define  TIM_CCER_CC3NP                      0x00000800U            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       0x00001000U            /*!<Capture/Compare 4 output enable */
-#define  TIM_CCER_CC4P                       0x00002000U            /*!<Capture/Compare 4 output Polarity */
-#define  TIM_CCER_CC4NP                      0x00008000U            /*!<Capture/Compare 4 Complementary output Polarity */
-#define  TIM_CCER_CC5E                       0x00010000U            /*!<Capture/Compare 5 output enable */
-#define  TIM_CCER_CC5P                       0x00020000U            /*!<Capture/Compare 5 output Polarity */
-#define  TIM_CCER_CC6E                       0x00100000U            /*!<Capture/Compare 6 output enable */
-#define  TIM_CCER_CC6P                       0x00200000U            /*!<Capture/Compare 6 output Polarity */
-
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         ((uint8_t)0xFFU)               /*!<Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
-
-/*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        0x000000FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      0x00000001U            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      0x00000002U            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      0x00000004U            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      0x00000008U            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      0x00000010U            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      0x00000020U            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      0x00000040U            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      0x00000080U            /*!<Bit 7 */
-
-#define  TIM_BDTR_LOCK                       0x00000300U            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     0x00000100U            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     0x00000200U            /*!<Bit 1 */
-
-#define  TIM_BDTR_OSSI                       0x00000400U            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       0x00000800U            /*!<Off-State Selection for Run mode  */
-#define  TIM_BDTR_BKE                        0x00001000U            /*!<Break enable                      */
-#define  TIM_BDTR_BKP                        0x00002000U            /*!<Break Polarity                    */
-#define  TIM_BDTR_AOE                        0x00004000U            /*!<Automatic Output enable           */
-#define  TIM_BDTR_MOE                        0x00008000U            /*!<Main Output enable                */
-#define  TIM_BDTR_BKF                        0x000F0000U            /*!<Break Filter for Break1 */
-#define  TIM_BDTR_BK2F                       0x00F00000U            /*!<Break Filter for Break2 */
-#define  TIM_BDTR_BK2E                       0x01000000U            /*!<Break enable for Break2 */
-#define  TIM_BDTR_BK2P                       0x02000000U            /*!<Break Polarity for Break2 */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
-
-#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
-
-/*******************  Bit definition for TIM_OR regiter  *********************/
-#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
-#define TIM_OR_ITR1_RMP                      0x0C00U            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
-#define TIM_OR_ITR1_RMP_0                    0x0400U            /*!<Bit 0 */
-#define TIM_OR_ITR1_RMP_1                    0x0800U            /*!<Bit 1 */
-
-/******************  Bit definition for TIM_CCMR3 register  *******************/
-#define  TIM_CCMR3_OC5FE                     0x00000004U            /*!<Output Compare 5 Fast enable */
-#define  TIM_CCMR3_OC5PE                     0x00000008U            /*!<Output Compare 5 Preload enable */
-
-#define  TIM_CCMR3_OC5M                      0x00010070U            /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
-#define  TIM_CCMR3_OC5M_0                    0x00000010U            /*!<Bit 0 */
-#define  TIM_CCMR3_OC5M_1                    0x00000020U            /*!<Bit 1 */
-#define  TIM_CCMR3_OC5M_2                    0x00000040U            /*!<Bit 2 */
-#define  TIM_CCMR3_OC5M_3                    0x00010000U            /*!<Bit 3 */
-
-#define  TIM_CCMR3_OC5CE                     0x00000080U            /*!<Output Compare 5 Clear Enable */
-
-#define  TIM_CCMR3_OC6FE                     0x00000400U            /*!<Output Compare 4 Fast enable */
-#define  TIM_CCMR3_OC6PE                     0x00000800U            /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR3_OC6M                      0x01007000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR3_OC6M_0                    0x00001000U            /*!<Bit 0 */
-#define  TIM_CCMR3_OC6M_1                    0x00002000U            /*!<Bit 1 */
-#define  TIM_CCMR3_OC6M_2                    0x00004000U            /*!<Bit 2 */
-#define  TIM_CCMR3_OC6M_3                    0x01000000U            /*!<Bit 3 */
-
-#define  TIM_CCMR3_OC6CE                     0x00008000U            /*!<Output Compare 4 Clear Enable */
-
-/*******************  Bit definition for TIM_CCR5 register  *******************/
-#define  TIM_CCR5_CCR5                       0xFFFFFFFFU        /*!<Capture/Compare 5 Value */
-#define  TIM_CCR5_GC5C1                      0x20000000U        /*!<Group Channel 5 and Channel 1 */
-#define  TIM_CCR5_GC5C2                      0x40000000U        /*!<Group Channel 5 and Channel 2 */
-#define  TIM_CCR5_GC5C3                      0x80000000U        /*!<Group Channel 5 and Channel 3 */
-
-/*******************  Bit definition for TIM_CCR6 register  *******************/
-#define  TIM_CCR6_CCR6                       ((uint16_t)0xFFFFU)            /*!<Capture/Compare 6 Value */
-
-/*******************  Bit definition for TIM1_AF1 register  *******************/
-#define TIM1_AF1_BKINE                       0x00000001U        /*!<BRK BKIN input enable */
-#define TIM1_AF1_BKDF1BKE                    0x00000100U        /*!<BRK DFSDM1_BREAK enable */
-
-/*******************  Bit definition for TIM1_AF2 register  *******************/
-#define TIM1_AF2_BK2INE                      0x00000001U        /*!<BRK2 BKIN input enable */
-#define TIM1_AF2_BK2DF1BKE                   0x00000100U        /*!<BRK2 DFSDM1_BREAK enable */
-
-/*******************  Bit definition for TIM8_AF1 register  *******************/
-#define TIM8_AF1_BKINE                       0x00000001U        /*!<BRK BKIN input enable */
-#define TIM8_AF1_BKDF1BKE                    0x00000100U        /*!<BRK DFSDM1_BREAK enable */
-
-/*******************  Bit definition for TIM8_AF2 register  *******************/
-#define TIM8_AF2_BK2INE                      0x00000001U        /*!<BRK2 BKIN2 input enable */
-#define TIM8_AF2_BK2DF1BKE                   0x00000100U        /*!<BRK2 DFSDM1_BREAK enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Low Power Timer (LPTIM)                            */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for LPTIM_ISR register  *******************/
-#define  LPTIM_ISR_CMPM                         0x00000001U            /*!< Compare match                       */
-#define  LPTIM_ISR_ARRM                         0x00000002U            /*!< Autoreload match                    */
-#define  LPTIM_ISR_EXTTRIG                      0x00000004U            /*!< External trigger edge event         */
-#define  LPTIM_ISR_CMPOK                        0x00000008U            /*!< Compare register update OK          */
-#define  LPTIM_ISR_ARROK                        0x00000010U            /*!< Autoreload register update OK       */
-#define  LPTIM_ISR_UP                           0x00000020U            /*!< Counter direction change down to up */
-#define  LPTIM_ISR_DOWN                         0x00000040U            /*!< Counter direction change up to down */
-
-/******************  Bit definition for LPTIM_ICR register  *******************/
-#define  LPTIM_ICR_CMPMCF                       0x00000001U            /*!< Compare match Clear Flag                       */
-#define  LPTIM_ICR_ARRMCF                       0x00000002U            /*!< Autoreload match Clear Flag                    */
-#define  LPTIM_ICR_EXTTRIGCF                    0x00000004U            /*!< External trigger edge event Clear Flag         */
-#define  LPTIM_ICR_CMPOKCF                      0x00000008U            /*!< Compare register update OK Clear Flag          */
-#define  LPTIM_ICR_ARROKCF                      0x00000010U            /*!< Autoreload register update OK Clear Flag       */
-#define  LPTIM_ICR_UPCF                         0x00000020U            /*!< Counter direction change down to up Clear Flag */
-#define  LPTIM_ICR_DOWNCF                       0x00000040U            /*!< Counter direction change up to down Clear Flag */
-
-/******************  Bit definition for LPTIM_IER register *******************/
-#define  LPTIM_IER_CMPMIE                       0x00000001U            /*!< Compare match Interrupt Enable                       */
-#define  LPTIM_IER_ARRMIE                       0x00000002U            /*!< Autoreload match Interrupt Enable                    */
-#define  LPTIM_IER_EXTTRIGIE                    0x00000004U            /*!< External trigger edge event Interrupt Enable         */
-#define  LPTIM_IER_CMPOKIE                      0x00000008U            /*!< Compare register update OK Interrupt Enable          */
-#define  LPTIM_IER_ARROKIE                      0x00000010U            /*!< Autoreload register update OK Interrupt Enable       */
-#define  LPTIM_IER_UPIE                         0x00000020U            /*!< Counter direction change down to up Interrupt Enable */
-#define  LPTIM_IER_DOWNIE                       0x00000040U            /*!< Counter direction change up to down Interrupt Enable */
-
-/******************  Bit definition for LPTIM_CFGR register*******************/
-#define  LPTIM_CFGR_CKSEL                       0x00000001U             /*!< Clock selector */
-
-#define  LPTIM_CFGR_CKPOL                       0x00000006U             /*!< CKPOL[1:0] bits (Clock polarity) */
-#define  LPTIM_CFGR_CKPOL_0                     0x00000002U             /*!< Bit 0 */
-#define  LPTIM_CFGR_CKPOL_1                     0x00000004U             /*!< Bit 1 */
-
-#define  LPTIM_CFGR_CKFLT                       0x00000018U             /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
-#define  LPTIM_CFGR_CKFLT_0                     0x00000008U             /*!< Bit 0 */
-#define  LPTIM_CFGR_CKFLT_1                     0x00000010U             /*!< Bit 1 */
-
-#define  LPTIM_CFGR_TRGFLT                      0x000000C0U             /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
-#define  LPTIM_CFGR_TRGFLT_0                    0x00000040U             /*!< Bit 0 */
-#define  LPTIM_CFGR_TRGFLT_1                    0x00000080U             /*!< Bit 1 */
-
-#define  LPTIM_CFGR_PRESC                       0x00000E00U             /*!< PRESC[2:0] bits (Clock prescaler) */
-#define  LPTIM_CFGR_PRESC_0                     0x00000200U             /*!< Bit 0 */
-#define  LPTIM_CFGR_PRESC_1                     0x00000400U             /*!< Bit 1 */
-#define  LPTIM_CFGR_PRESC_2                     0x00000800U             /*!< Bit 2 */
-
-#define  LPTIM_CFGR_TRIGSEL                     0x0000E000U             /*!< TRIGSEL[2:0]] bits (Trigger selector) */
-#define  LPTIM_CFGR_TRIGSEL_0                   0x00002000U             /*!< Bit 0 */
-#define  LPTIM_CFGR_TRIGSEL_1                   0x00004000U             /*!< Bit 1 */
-#define  LPTIM_CFGR_TRIGSEL_2                   0x00008000U             /*!< Bit 2 */
-
-#define  LPTIM_CFGR_TRIGEN                      0x00060000U             /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
-#define  LPTIM_CFGR_TRIGEN_0                    0x00020000U             /*!< Bit 0 */
-#define  LPTIM_CFGR_TRIGEN_1                    0x00040000U             /*!< Bit 1 */
-
-#define  LPTIM_CFGR_TIMOUT                      0x00080000U             /*!< Timout enable           */
-#define  LPTIM_CFGR_WAVE                        0x00100000U             /*!< Waveform shape          */
-#define  LPTIM_CFGR_WAVPOL                      0x00200000U             /*!< Waveform shape polarity */
-#define  LPTIM_CFGR_PRELOAD                     0x00400000U             /*!< Reg update mode         */
-#define  LPTIM_CFGR_COUNTMODE                   0x00800000U             /*!< Counter mode enable     */
-#define  LPTIM_CFGR_ENC                         0x01000000U             /*!< Encoder mode enable     */
-
-/******************  Bit definition for LPTIM_CR register  ********************/
-#define  LPTIM_CR_ENABLE                        0x00000001U             /*!< LPTIMer enable                 */
-#define  LPTIM_CR_SNGSTRT                       0x00000002U             /*!< Timer start in single mode     */
-#define  LPTIM_CR_CNTSTRT                       0x00000004U             /*!< Timer start in continuous mode */
-
-/******************  Bit definition for LPTIM_CMP register *******************/
-#define  LPTIM_CMP_CMP                          0x0000FFFFU             /*!< Compare register     */
-
-/******************  Bit definition for LPTIM_ARR register *******************/
-#define  LPTIM_ARR_ARR                          0x0000FFFFU             /*!< Auto reload register */
-
-/******************  Bit definition for LPTIM_CNT register *******************/
-#define  LPTIM_CNT_CNT                          0x0000FFFFU             /*!< Counter register     */
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_UE                        0x00000001U            /*!< USART Enable                                    */
-#define  USART_CR1_RE                        0x00000004U            /*!< Receiver Enable                                 */
-#define  USART_CR1_TE                        0x00000008U            /*!< Transmitter Enable                              */
-#define  USART_CR1_IDLEIE                    0x00000010U            /*!< IDLE Interrupt Enable                           */
-#define  USART_CR1_RXNEIE                    0x00000020U            /*!< RXNE Interrupt Enable                           */
-#define  USART_CR1_TCIE                      0x00000040U            /*!< Transmission Complete Interrupt Enable          */
-#define  USART_CR1_TXEIE                     0x00000080U            /*!< TXE Interrupt Enable                            */
-#define  USART_CR1_PEIE                      0x00000100U            /*!< PE Interrupt Enable                             */
-#define  USART_CR1_PS                        0x00000200U            /*!< Parity Selection                                */
-#define  USART_CR1_PCE                       0x00000400U            /*!< Parity Control Enable                           */
-#define  USART_CR1_WAKE                      0x00000800U            /*!< Receiver Wakeup method                          */
-#define  USART_CR1_M                         0x10001000U            /*!< Word length                                     */
-#define  USART_CR1_M_0                       0x00001000U            /*!< Word length - Bit 0                             */
-#define  USART_CR1_MME                       0x00002000U            /*!< Mute Mode Enable                                */
-#define  USART_CR1_CMIE                      0x00004000U            /*!< Character match interrupt enable                */
-#define  USART_CR1_OVER8                     0x00008000U            /*!< Oversampling by 8-bit or 16-bit mode            */
-#define  USART_CR1_DEDT                      0x001F0000U            /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
-#define  USART_CR1_DEDT_0                    0x00010000U            /*!< Bit 0 */
-#define  USART_CR1_DEDT_1                    0x00020000U            /*!< Bit 1 */
-#define  USART_CR1_DEDT_2                    0x00040000U            /*!< Bit 2 */
-#define  USART_CR1_DEDT_3                    0x00080000U            /*!< Bit 3 */
-#define  USART_CR1_DEDT_4                    0x00100000U            /*!< Bit 4 */
-#define  USART_CR1_DEAT                      0x03E00000U            /*!< DEAT[4:0] bits (Driver Enable Assertion Time)   */
-#define  USART_CR1_DEAT_0                    0x00200000U            /*!< Bit 0 */
-#define  USART_CR1_DEAT_1                    0x00400000U            /*!< Bit 1 */
-#define  USART_CR1_DEAT_2                    0x00800000U            /*!< Bit 2 */
-#define  USART_CR1_DEAT_3                    0x01000000U            /*!< Bit 3 */
-#define  USART_CR1_DEAT_4                    0x02000000U            /*!< Bit 4 */
-#define  USART_CR1_RTOIE                     0x04000000U            /*!< Receive Time Out interrupt enable */
-#define  USART_CR1_EOBIE                     0x08000000U            /*!< End of Block interrupt enable     */
-#define  USART_CR1_M_1                       0x10000000U            /*!< Word length - Bit 1               */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADDM7                     0x00000010U            /*!< 7-bit or 4-bit Address Detection       */
-#define  USART_CR2_LBDL                      0x00000020U            /*!< LIN Break Detection Length             */
-#define  USART_CR2_LBDIE                     0x00000040U            /*!< LIN Break Detection Interrupt Enable   */
-#define  USART_CR2_LBCL                      0x00000100U            /*!< Last Bit Clock pulse                   */
-#define  USART_CR2_CPHA                      0x00000200U            /*!< Clock Phase                            */
-#define  USART_CR2_CPOL                      0x00000400U            /*!< Clock Polarity                         */
-#define  USART_CR2_CLKEN                     0x00000800U            /*!< Clock Enable                           */
-#define  USART_CR2_STOP                      0x00003000U            /*!< STOP[1:0] bits (STOP bits)             */
-#define  USART_CR2_STOP_0                    0x00001000U            /*!< Bit 0 */
-#define  USART_CR2_STOP_1                    0x00002000U            /*!< Bit 1 */
-#define  USART_CR2_LINEN                     0x00004000U            /*!< LIN mode enable                        */
-#define  USART_CR2_SWAP                      0x00008000U            /*!< SWAP TX/RX pins                        */
-#define  USART_CR2_RXINV                     0x00010000U            /*!< RX pin active level inversion          */
-#define  USART_CR2_TXINV                     0x00020000U            /*!< TX pin active level inversion          */
-#define  USART_CR2_DATAINV                   0x00040000U            /*!< Binary data inversion                  */
-#define  USART_CR2_MSBFIRST                  0x00080000U            /*!< Most Significant Bit First             */
-#define  USART_CR2_ABREN                     0x00100000U            /*!< Auto Baud-Rate Enable                  */
-#define  USART_CR2_ABRMODE                   0x00600000U            /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
-#define  USART_CR2_ABRMODE_0                 0x00200000U            /*!< Bit 0 */
-#define  USART_CR2_ABRMODE_1                 0x00400000U            /*!< Bit 1 */
-#define  USART_CR2_RTOEN                     0x00800000U            /*!< Receiver Time-Out enable  */
-#define  USART_CR2_ADD                       0xFF000000U            /*!< Address of the USART node */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       0x00000001U            /*!< Error Interrupt Enable                         */
-#define  USART_CR3_IREN                      0x00000002U            /*!< IrDA mode Enable                               */
-#define  USART_CR3_IRLP                      0x00000004U            /*!< IrDA Low-Power                                 */
-#define  USART_CR3_HDSEL                     0x00000008U            /*!< Half-Duplex Selection                          */
-#define  USART_CR3_NACK                      0x00000010U            /*!< SmartCard NACK enable                          */
-#define  USART_CR3_SCEN                      0x00000020U            /*!< SmartCard mode enable                          */
-#define  USART_CR3_DMAR                      0x00000040U            /*!< DMA Enable Receiver                            */
-#define  USART_CR3_DMAT                      0x00000080U            /*!< DMA Enable Transmitter                         */
-#define  USART_CR3_RTSE                      0x00000100U            /*!< RTS Enable                                     */
-#define  USART_CR3_CTSE                      0x00000200U            /*!< CTS Enable                                     */
-#define  USART_CR3_CTSIE                     0x00000400U            /*!< CTS Interrupt Enable                           */
-#define  USART_CR3_ONEBIT                    0x00000800U            /*!< One sample bit method enable                   */
-#define  USART_CR3_OVRDIS                    0x00001000U            /*!< Overrun Disable                                */
-#define  USART_CR3_DDRE                      0x00002000U            /*!< DMA Disable on Reception Error                 */
-#define  USART_CR3_DEM                       0x00004000U            /*!< Driver Enable Mode                             */
-#define  USART_CR3_DEP                       0x00008000U            /*!< Driver Enable Polarity Selection               */
-#define  USART_CR3_SCARCNT                   0x000E0000U            /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
-#define  USART_CR3_SCARCNT_0                 0x00020000U            /*!< Bit 0 */
-#define  USART_CR3_SCARCNT_1                 0x00040000U            /*!< Bit 1 */
-#define  USART_CR3_SCARCNT_2                 0x00080000U            /*!< Bit 2 */
-
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_FRACTION              0x000FU                /*!< Fraction of USARTDIV */
-#define  USART_BRR_DIV_MANTISSA              0xFFF0U                /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      0x00FFU                /*!< PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_GT                       0xFF00U                /*!< GT[7:0] bits (Guard time value) */
-
-
-/*******************  Bit definition for USART_RTOR register  *****************/
-#define  USART_RTOR_RTO                      0x00FFFFFFU            /*!< Receiver Time Out Value */
-#define  USART_RTOR_BLEN                     0xFF000000U            /*!< Block Length */
-
-/*******************  Bit definition for USART_RQR register  ******************/
-#define  USART_RQR_ABRRQ                     0x0001U                /*!< Auto-Baud Rate Request      */
-#define  USART_RQR_SBKRQ                     0x0002U                /*!< Send Break Request          */
-#define  USART_RQR_MMRQ                      0x0004U                /*!< Mute Mode Request           */
-#define  USART_RQR_RXFRQ                     0x0008U                /*!< Receive Data flush Request  */
-#define  USART_RQR_TXFRQ                     0x0010U                /*!< Transmit data flush Request */
-
-/*******************  Bit definition for USART_ISR register  ******************/
-#define  USART_ISR_PE                        0x00000001U            /*!< Parity Error                        */
-#define  USART_ISR_FE                        0x00000002U            /*!< Framing Error                       */
-#define  USART_ISR_NE                        0x00000004U            /*!< Noise detected Flag                 */
-#define  USART_ISR_ORE                       0x00000008U            /*!< OverRun Error                       */
-#define  USART_ISR_IDLE                      0x00000010U            /*!< IDLE line detected                  */
-#define  USART_ISR_RXNE                      0x00000020U            /*!< Read Data Register Not Empty        */
-#define  USART_ISR_TC                        0x00000040U            /*!< Transmission Complete               */
-#define  USART_ISR_TXE                       0x00000080U            /*!< Transmit Data Register Empty        */
-#define  USART_ISR_LBDF                      0x00000100U            /*!< LIN Break Detection Flag            */
-#define  USART_ISR_CTSIF                     0x00000200U            /*!< CTS interrupt flag                  */
-#define  USART_ISR_CTS                       0x00000400U            /*!< CTS flag                            */
-#define  USART_ISR_RTOF                      0x00000800U            /*!< Receiver Time Out                   */
-#define  USART_ISR_EOBF                      0x00001000U            /*!< End Of Block Flag                   */
-#define  USART_ISR_ABRE                      0x00004000U            /*!< Auto-Baud Rate Error                */
-#define  USART_ISR_ABRF                      0x00008000U            /*!< Auto-Baud Rate Flag                 */
-#define  USART_ISR_BUSY                      0x00010000U            /*!< Busy Flag                           */
-#define  USART_ISR_CMF                       0x00020000U            /*!< Character Match Flag                */
-#define  USART_ISR_SBKF                      0x00040000U            /*!< Send Break Flag                     */
-#define  USART_ISR_RWU                       0x00080000U            /*!< Receive Wake Up from mute mode Flag */
-#define  USART_ISR_WUF                       0x00100000U            /*!< Wake Up from stop mode Flag         */
-#define  USART_ISR_TEACK                     0x00200000U            /*!< Transmit Enable Acknowledge Flag    */
-#define  USART_ISR_REACK                     0x00400000U            /*!< Receive Enable Acknowledge Flag     */
-
-
-/*******************  Bit definition for USART_ICR register  ******************/
-#define  USART_ICR_PECF                      0x00000001U            /*!< Parity Error Clear Flag             */
-#define  USART_ICR_FECF                      0x00000002U            /*!< Framing Error Clear Flag            */
-#define  USART_ICR_NCF                       0x00000004U            /*!< Noise detected Clear Flag           */
-#define  USART_ICR_ORECF                     0x00000008U            /*!< OverRun Error Clear Flag            */
-#define  USART_ICR_IDLECF                    0x00000010U            /*!< IDLE line detected Clear Flag       */
-#define  USART_ICR_TCCF                      0x00000040U            /*!< Transmission Complete Clear Flag    */
-#define  USART_ICR_LBDCF                     0x00000100U            /*!< LIN Break Detection Clear Flag      */
-#define  USART_ICR_CTSCF                     0x00000200U            /*!< CTS Interrupt Clear Flag            */
-#define  USART_ICR_RTOCF                     0x00000800U            /*!< Receiver Time Out Clear Flag        */
-#define  USART_ICR_EOBCF                     0x00001000U            /*!< End Of Block Clear Flag             */
-#define  USART_ICR_CMCF                      0x00020000U            /*!< Character Match Clear Flag          */
-#define  USART_ICR_WUCF                      0x00100000U            /*!< Wake Up from stop mode Clear Flag   */
-
-/*******************  Bit definition for USART_RDR register  ******************/
-#define  USART_RDR_RDR                       0x01FFU                /*!< RDR[8:0] bits (Receive Data value) */
-
-/*******************  Bit definition for USART_TDR register  ******************/
-#define  USART_TDR_TDR                       0x01FFU                /*!< TDR[8:0] bits (Transmit Data value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Window WATCHDOG                                 */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                            0x7FU                 /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T_0                          0x01U                 /*!<Bit 0 */
-#define  WWDG_CR_T_1                          0x02U                 /*!<Bit 1 */
-#define  WWDG_CR_T_2                          0x04U                 /*!<Bit 2 */
-#define  WWDG_CR_T_3                          0x08U                 /*!<Bit 3 */
-#define  WWDG_CR_T_4                          0x10U                 /*!<Bit 4 */
-#define  WWDG_CR_T_5                          0x20U                 /*!<Bit 5 */
-#define  WWDG_CR_T_6                          0x40U                 /*!<Bit 6 */
-
-
-#define  WWDG_CR_WDGA                        0x80U                  /*!<Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          0x007FU                /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W_0                        0x0001U                /*!<Bit 0 */
-#define  WWDG_CFR_W_1                        0x0002U                /*!<Bit 1 */
-#define  WWDG_CFR_W_2                        0x0004U                /*!<Bit 2 */
-#define  WWDG_CFR_W_3                        0x0008U                /*!<Bit 3 */
-#define  WWDG_CFR_W_4                        0x0010U                /*!<Bit 4 */
-#define  WWDG_CFR_W_5                        0x0020U                /*!<Bit 5 */
-#define  WWDG_CFR_W_6                        0x0040U                /*!<Bit 6 */
-
-
-#define  WWDG_CFR_WDGTB                      0x0180U                /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB_0                    0x0080U                /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB_1                    0x0100U                /*!<Bit 1 */
-
-
-#define  WWDG_CFR_EWI                        0x0200U               /*!<Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        0x01U                  /*!<Early Wakeup Interrupt Flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                DBG                                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
-#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
-
-/********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
-#define  DBGMCU_CR_DBG_STOP                  0x00000002U
-#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
-#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
-
-#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
-#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U /*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U /*!<Bit 1 */
-
-/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            0x00000001U
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            0x00000002U
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            0x00000004U
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            0x00000020U
-#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           0x00000040U
-#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           0x00000080U
-#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           0x00000100U
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
-#define  DBGMCU_APB1_FZ_DBG_CAN3_STOP            0x00002000U
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
-#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
-
-/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP            0x00000001U
-#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP            0x00000002U
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP            0x00010000U
-#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP           0x00020000U
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP           0x00040000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                Ethernet MAC Registers bits definitions                     */
-/*                                                                            */
-/******************************************************************************/
-/* Bit definition for Ethernet MAC Control Register register */
-#define ETH_MACCR_WD              0x00800000U  /* Watchdog disable */
-#define ETH_MACCR_JD              0x00400000U  /* Jabber disable */
-#define ETH_MACCR_IFG             0x000E0000U  /* Inter-frame gap */
-#define ETH_MACCR_IFG_96Bit       0x00000000U  /* Minimum IFG between frames during transmission is 96Bit */
-#define ETH_MACCR_IFG_88Bit       0x00020000U  /* Minimum IFG between frames during transmission is 88Bit */
-#define ETH_MACCR_IFG_80Bit       0x00040000U  /* Minimum IFG between frames during transmission is 80Bit */
-#define ETH_MACCR_IFG_72Bit       0x00060000U  /* Minimum IFG between frames during transmission is 72Bit */
-#define ETH_MACCR_IFG_64Bit       0x00080000U  /* Minimum IFG between frames during transmission is 64Bit */
-#define ETH_MACCR_IFG_56Bit       0x000A0000U  /* Minimum IFG between frames during transmission is 56Bit */
-#define ETH_MACCR_IFG_48Bit       0x000C0000U  /* Minimum IFG between frames during transmission is 48Bit */
-#define ETH_MACCR_IFG_40Bit       0x000E0000U  /* Minimum IFG between frames during transmission is 40Bit */
-#define ETH_MACCR_CSD             0x00010000U  /* Carrier sense disable (during transmission) */
-#define ETH_MACCR_FES             0x00004000U  /* Fast ethernet speed */
-#define ETH_MACCR_ROD             0x00002000U  /* Receive own disable */
-#define ETH_MACCR_LM              0x00001000U  /* loopback mode */
-#define ETH_MACCR_DM              0x00000800U  /* Duplex mode */
-#define ETH_MACCR_IPCO            0x00000400U  /* IP Checksum offload */
-#define ETH_MACCR_RD              0x00000200U  /* Retry disable */
-#define ETH_MACCR_APCS            0x00000080U  /* Automatic Pad/CRC stripping */
-#define ETH_MACCR_BL              0x00000060U  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
-                                                       a transmission attempt during retries after a collision: 0 =< r <2^k */
-#define ETH_MACCR_BL_10           0x00000000U  /* k = min (n, 10) */
-#define ETH_MACCR_BL_8            0x00000020U  /* k = min (n, 8) */
-#define ETH_MACCR_BL_4            0x00000040U  /* k = min (n, 4) */
-#define ETH_MACCR_BL_1            0x00000060U  /* k = min (n, 1) */
-#define ETH_MACCR_DC              0x00000010U  /* Defferal check */
-#define ETH_MACCR_TE              0x00000008U  /* Transmitter enable */
-#define ETH_MACCR_RE              0x00000004U  /* Receiver enable */
-
-/* Bit definition for Ethernet MAC Frame Filter Register */
-#define ETH_MACFFR_RA             0x80000000U  /* Receive all */
-#define ETH_MACFFR_HPF            0x00000400U  /* Hash or perfect filter */
-#define ETH_MACFFR_SAF            0x00000200U  /* Source address filter enable */
-#define ETH_MACFFR_SAIF           0x00000100U  /* SA inverse filtering */
-#define ETH_MACFFR_PCF            0x000000C0U  /* Pass control frames: 3 cases */
-#define ETH_MACFFR_PCF_BlockAll                0x00000040U  /* MAC filters all control frames from reaching the application */
-#define ETH_MACFFR_PCF_ForwardAll              0x00000080U  /* MAC forwards all control frames to application even if they fail the Address Filter */
-#define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U  /* MAC forwards control frames that pass the Address Filter. */
-#define ETH_MACFFR_BFD             0x00000020U  /* Broadcast frame disable */
-#define ETH_MACFFR_PAM             0x00000010U  /* Pass all mutlicast */
-#define ETH_MACFFR_DAIF            0x00000008U  /* DA Inverse filtering */
-#define ETH_MACFFR_HM              0x00000004U  /* Hash multicast */
-#define ETH_MACFFR_HU              0x00000002U  /* Hash unicast */
-#define ETH_MACFFR_PM              0x00000001U  /* Promiscuous mode */
-
-/* Bit definition for Ethernet MAC Hash Table High Register */
-#define ETH_MACHTHR_HTH            0xFFFFFFFFU  /* Hash table high */
-
-/* Bit definition for Ethernet MAC Hash Table Low Register */
-#define ETH_MACHTLR_HTL            0xFFFFFFFFU  /* Hash table low */
-
-/* Bit definition for Ethernet MAC MII Address Register */
-#define ETH_MACMIIAR_PA            0x0000F800U  /* Physical layer address */
-#define ETH_MACMIIAR_MR            0x000007C0U  /* MII register in the selected PHY */
-#define ETH_MACMIIAR_CR            0x0000001CU  /* CR clock range: 6 cases */
-#define ETH_MACMIIAR_CR_Div42      0x00000000U  /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
-#define ETH_MACMIIAR_CR_Div62      0x00000004U  /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
-#define ETH_MACMIIAR_CR_Div16      0x00000008U  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
-#define ETH_MACMIIAR_CR_Div26      0x0000000CU  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
-#define ETH_MACMIIAR_CR_Div102     0x00000010U  /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
-#define ETH_MACMIIAR_MW            0x00000002U  /* MII write */
-#define ETH_MACMIIAR_MB            0x00000001U  /* MII busy */
-
-/* Bit definition for Ethernet MAC MII Data Register */
-#define ETH_MACMIIDR_MD            0x0000FFFFU  /* MII data: read/write data from/to PHY */
-
-/* Bit definition for Ethernet MAC Flow Control Register */
-#define ETH_MACFCR_PT              0xFFFF0000U  /* Pause time */
-#define ETH_MACFCR_ZQPD            0x00000080U  /* Zero-quanta pause disable */
-#define ETH_MACFCR_PLT             0x00000030U  /* Pause low threshold: 4 cases */
-#define ETH_MACFCR_PLT_Minus4      0x00000000U  /* Pause time minus 4 slot times */
-#define ETH_MACFCR_PLT_Minus28     0x00000010U  /* Pause time minus 28 slot times */
-#define ETH_MACFCR_PLT_Minus144    0x00000020U  /* Pause time minus 144 slot times */
-#define ETH_MACFCR_PLT_Minus256    0x00000030U  /* Pause time minus 256 slot times */
-#define ETH_MACFCR_UPFD            0x00000008U  /* Unicast pause frame detect */
-#define ETH_MACFCR_RFCE            0x00000004U  /* Receive flow control enable */
-#define ETH_MACFCR_TFCE            0x00000002U  /* Transmit flow control enable */
-#define ETH_MACFCR_FCBBPA          0x00000001U  /* Flow control busy/backpressure activate */
-
-/* Bit definition for Ethernet MAC VLAN Tag Register */
-#define ETH_MACVLANTR_VLANTC       0x00010000U  /* 12-bit VLAN tag comparison */
-#define ETH_MACVLANTR_VLANTI       0x0000FFFFU  /* VLAN tag identifier (for receive frames) */
-
-/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
-#define ETH_MACRWUFFR_D            0xFFFFFFFFU  /* Wake-up frame filter register data */
-/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
-   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
-/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
-   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
-   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
-   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
-   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
-                              RSVD - Filter1 Command - RSVD - Filter0 Command
-   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
-   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
-   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
-
-/* Bit definition for Ethernet MAC PMT Control and Status Register */
-#define ETH_MACPMTCSR_WFFRPR       0x80000000U  /* Wake-Up Frame Filter Register Pointer Reset */
-#define ETH_MACPMTCSR_GU           0x00000200U  /* Global Unicast */
-#define ETH_MACPMTCSR_WFR          0x00000040U  /* Wake-Up Frame Received */
-#define ETH_MACPMTCSR_MPR          0x00000020U  /* Magic Packet Received */
-#define ETH_MACPMTCSR_WFE          0x00000004U  /* Wake-Up Frame Enable */
-#define ETH_MACPMTCSR_MPE          0x00000002U  /* Magic Packet Enable */
-#define ETH_MACPMTCSR_PD           0x00000001U  /* Power Down */
-
-/* Bit definition for Ethernet MAC Status Register */
-#define ETH_MACSR_TSTS      0x00000200U  /* Time stamp trigger status */
-#define ETH_MACSR_MMCTS     0x00000040U  /* MMC transmit status */
-#define ETH_MACSR_MMMCRS    0x00000020U  /* MMC receive status */
-#define ETH_MACSR_MMCS      0x00000010U  /* MMC status */
-#define ETH_MACSR_PMTS      0x00000008U  /* PMT status */
-
-/* Bit definition for Ethernet MAC Interrupt Mask Register */
-#define ETH_MACIMR_TSTIM     0x00000200U  /* Time stamp trigger interrupt mask */
-#define ETH_MACIMR_PMTIM     0x00000008U  /* PMT interrupt mask */
-
-/* Bit definition for Ethernet MAC Address0 High Register */
-#define ETH_MACA0HR_MACA0H   0x0000FFFFU  /* MAC address0 high */
-
-/* Bit definition for Ethernet MAC Address0 Low Register */
-#define ETH_MACA0LR_MACA0L   0xFFFFFFFFU  /* MAC address0 low */
-
-/* Bit definition for Ethernet MAC Address1 High Register */
-#define ETH_MACA1HR_AE       0x80000000U  /* Address enable */
-#define ETH_MACA1HR_SA       0x40000000U  /* Source address */
-#define ETH_MACA1HR_MBC      0x3F000000U  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
-  #define ETH_MACA1HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA1HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA1HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA1HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA1HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA1HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [7:0] */
-#define ETH_MACA1HR_MACA1H            0x0000FFFFU  /* MAC address1 high */
-
-/* Bit definition for Ethernet MAC Address1 Low Register */
-#define ETH_MACA1LR_MACA1L   0xFFFFFFFFU  /* MAC address1 low */
-
-/* Bit definition for Ethernet MAC Address2 High Register */
-#define ETH_MACA2HR_AE       0x80000000U  /* Address enable */
-#define ETH_MACA2HR_SA       0x40000000U  /* Source address */
-#define ETH_MACA2HR_MBC      0x3F000000U  /* Mask byte control */
-  #define ETH_MACA2HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA2HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA2HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA2HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA2HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA2HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA2HR_MACA2H   0x0000FFFFU  /* MAC address1 high */
-
-/* Bit definition for Ethernet MAC Address2 Low Register */
-#define ETH_MACA2LR_MACA2L   0xFFFFFFFFU  /* MAC address2 low */
-
-/* Bit definition for Ethernet MAC Address3 High Register */
-#define ETH_MACA3HR_AE       0x80000000U  /* Address enable */
-#define ETH_MACA3HR_SA       0x40000000U  /* Source address */
-#define ETH_MACA3HR_MBC      0x3F000000U  /* Mask byte control */
-  #define ETH_MACA3HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA3HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA3HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA3HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA3HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA3HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA3HR_MACA3H   0x0000FFFFU  /* MAC address3 high */
-
-/* Bit definition for Ethernet MAC Address3 Low Register */
-#define ETH_MACA3LR_MACA3L   0xFFFFFFFFU  /* MAC address3 low */
-
-/******************************************************************************/
-/*                Ethernet MMC Registers bits definition                      */
-/******************************************************************************/
-
-/* Bit definition for Ethernet MMC Contol Register */
-#define ETH_MMCCR_MCFHP      0x00000020U  /* MMC counter Full-Half preset */
-#define ETH_MMCCR_MCP        0x00000010U  /* MMC counter preset */
-#define ETH_MMCCR_MCF        0x00000008U  /* MMC Counter Freeze */
-#define ETH_MMCCR_ROR        0x00000004U  /* Reset on Read */
-#define ETH_MMCCR_CSR        0x00000002U  /* Counter Stop Rollover */
-#define ETH_MMCCR_CR         0x00000001U  /* Counters Reset */
-
-/* Bit definition for Ethernet MMC Receive Interrupt Register */
-#define ETH_MMCRIR_RGUFS     0x00020000U  /* Set when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIR_RFAES     0x00000040U  /* Set when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIR_RFCES     0x00000020U  /* Set when Rx crc error counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmit Interrupt Register */
-#define ETH_MMCTIR_TGFS      0x00200000U  /* Set when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFMSCS   0x00008000U  /* Set when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFSCS    0x00004000U  /* Set when Tx good single col counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
-#define ETH_MMCRIMR_RGUFM    0x00020000U  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFAEM    0x00000040U  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFCEM    0x00000020U  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
-#define ETH_MMCTIMR_TGFM     0x00200000U  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFMSCM  0x00008000U  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFSCM   0x00004000U  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
-#define ETH_MMCTGFSCCR_TGFSCC     0xFFFFFFFFU  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
-#define ETH_MMCTGFMSCCR_TGFMSCC   0xFFFFFFFFU  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
-#define ETH_MMCTGFCR_TGFC    0xFFFFFFFFU  /* Number of good frames transmitted. */
-
-/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
-#define ETH_MMCRFCECR_RFCEC  0xFFFFFFFFU  /* Number of frames received with CRC error. */
-
-/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
-#define ETH_MMCRFAECR_RFAEC  0xFFFFFFFFU  /* Number of frames received with alignment (dribble) error */
-
-/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
-#define ETH_MMCRGUFCR_RGUFC  0xFFFFFFFFU  /* Number of good unicast frames received. */
-
-/******************************************************************************/
-/*               Ethernet PTP Registers bits definition                       */
-/******************************************************************************/
-
-/* Bit definition for Ethernet PTP Time Stamp Contol Register */
-#define ETH_PTPTSCR_TSCNT       0x00030000U  /* Time stamp clock node type */
-#define ETH_PTPTSSR_TSSMRME     0x00008000U  /* Time stamp snapshot for message relevant to master enable */
-#define ETH_PTPTSSR_TSSEME      0x00004000U  /* Time stamp snapshot for event message enable */
-#define ETH_PTPTSSR_TSSIPV4FE   0x00002000U  /* Time stamp snapshot for IPv4 frames enable */
-#define ETH_PTPTSSR_TSSIPV6FE   0x00001000U  /* Time stamp snapshot for IPv6 frames enable */
-#define ETH_PTPTSSR_TSSPTPOEFE  0x00000800U  /* Time stamp snapshot for PTP over ethernet frames enable */
-#define ETH_PTPTSSR_TSPTPPSV2E  0x00000400U  /* Time stamp PTP packet snooping for version2 format enable */
-#define ETH_PTPTSSR_TSSSR       0x00000200U  /* Time stamp Sub-seconds rollover */
-#define ETH_PTPTSSR_TSSARFE     0x00000100U  /* Time stamp snapshot for all received frames enable */
-
-#define ETH_PTPTSCR_TSARU       0x00000020U  /* Addend register update */
-#define ETH_PTPTSCR_TSITE       0x00000010U  /* Time stamp interrupt trigger enable */
-#define ETH_PTPTSCR_TSSTU       0x00000008U  /* Time stamp update */
-#define ETH_PTPTSCR_TSSTI       0x00000004U  /* Time stamp initialize */
-#define ETH_PTPTSCR_TSFCU       0x00000002U  /* Time stamp fine or coarse update */
-#define ETH_PTPTSCR_TSE         0x00000001U  /* Time stamp enable */
-
-/* Bit definition for Ethernet PTP Sub-Second Increment Register */
-#define ETH_PTPSSIR_STSSI      0x000000FFU   /* System time Sub-second increment value */
-
-/* Bit definition for Ethernet PTP Time Stamp High Register */
-#define ETH_PTPTSHR_STS        0xFFFFFFFFU   /* System Time second */
-
-/* Bit definition for Ethernet PTP Time Stamp Low Register */
-#define ETH_PTPTSLR_STPNS      0x80000000U  /* System Time Positive or negative time */
-#define ETH_PTPTSLR_STSS       0x7FFFFFFFU  /* System Time sub-seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp High Update Register */
-#define ETH_PTPTSHUR_TSUS      0xFFFFFFFFU  /* Time stamp update seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
-#define ETH_PTPTSLUR_TSUPNS    0x80000000U  /* Time stamp update Positive or negative time */
-#define ETH_PTPTSLUR_TSUSS     0x7FFFFFFFU  /* Time stamp update sub-seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp Addend Register */
-#define ETH_PTPTSAR_TSA        0xFFFFFFFFU  /* Time stamp addend */
-
-/* Bit definition for Ethernet PTP Target Time High Register */
-#define ETH_PTPTTHR_TTSH       0xFFFFFFFFU  /* Target time stamp high */
-
-/* Bit definition for Ethernet PTP Target Time Low Register */
-#define ETH_PTPTTLR_TTSL       0xFFFFFFFFU  /* Target time stamp low */
-
-/* Bit definition for Ethernet PTP Time Stamp Status Register */
-#define ETH_PTPTSSR_TSTTR      0x00000020U  /* Time stamp target time reached */
-#define ETH_PTPTSSR_TSSO       0x00000010U  /* Time stamp seconds overflow */
-
-/******************************************************************************/
-/*                 Ethernet DMA Registers bits definition                     */
-/******************************************************************************/
-
-/* Bit definition for Ethernet DMA Bus Mode Register */
-#define ETH_DMABMR_AAB        0x02000000U  /* Address-Aligned beats */
-#define ETH_DMABMR_FPM        0x01000000U  /* 4xPBL mode */
-#define ETH_DMABMR_USP        0x00800000U  /* Use separate PBL */
-#define ETH_DMABMR_RDP        0x007E0000U  /* RxDMA PBL */
-  #define ETH_DMABMR_RDP_1Beat    0x00020000U  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
-  #define ETH_DMABMR_RDP_2Beat    0x00040000U  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
-  #define ETH_DMABMR_RDP_4Beat    0x00080000U  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-  #define ETH_DMABMR_RDP_8Beat    0x00100000U  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-  #define ETH_DMABMR_RDP_16Beat   0x00200000U  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-  #define ETH_DMABMR_RDP_32Beat   0x00400000U  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
-  #define ETH_DMABMR_RDP_4xPBL_4Beat   0x01020000U  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-  #define ETH_DMABMR_RDP_4xPBL_8Beat   0x01040000U  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-  #define ETH_DMABMR_RDP_4xPBL_16Beat  0x01080000U  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-  #define ETH_DMABMR_RDP_4xPBL_32Beat  0x01100000U  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
-  #define ETH_DMABMR_RDP_4xPBL_64Beat  0x01200000U  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
-  #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
-#define ETH_DMABMR_FB        0x00010000U  /* Fixed Burst */
-#define ETH_DMABMR_RTPR      0x0000C000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_1_1     0x00000000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_2_1     0x00004000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_3_1     0x00008000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_4_1     0x0000C000U  /* Rx Tx priority ratio */
-#define ETH_DMABMR_PBL    0x00003F00U  /* Programmable burst length */
-  #define ETH_DMABMR_PBL_1Beat    0x00000100U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
-  #define ETH_DMABMR_PBL_2Beat    0x00000200U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
-  #define ETH_DMABMR_PBL_4Beat    0x00000400U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-  #define ETH_DMABMR_PBL_8Beat    0x00000800U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-  #define ETH_DMABMR_PBL_16Beat   0x00001000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-  #define ETH_DMABMR_PBL_32Beat   0x00002000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
-  #define ETH_DMABMR_PBL_4xPBL_4Beat   0x01000100U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-  #define ETH_DMABMR_PBL_4xPBL_8Beat   0x01000200U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-  #define ETH_DMABMR_PBL_4xPBL_16Beat  0x01000400U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-  #define ETH_DMABMR_PBL_4xPBL_32Beat  0x01000800U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
-  #define ETH_DMABMR_PBL_4xPBL_64Beat  0x01001000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
-  #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
-#define ETH_DMABMR_EDE       0x00000080U  /* Enhanced Descriptor Enable */
-#define ETH_DMABMR_DSL       0x0000007CU  /* Descriptor Skip Length */
-#define ETH_DMABMR_DA        0x00000002U  /* DMA arbitration scheme */
-#define ETH_DMABMR_SR        0x00000001U  /* Software reset */
-
-/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
-#define ETH_DMATPDR_TPD      0xFFFFFFFFU  /* Transmit poll demand */
-
-/* Bit definition for Ethernet DMA Receive Poll Demand Register */
-#define ETH_DMARPDR_RPD      0xFFFFFFFFU  /* Receive poll demand  */
-
-/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
-#define ETH_DMARDLAR_SRL     0xFFFFFFFFU  /* Start of receive list */
-
-/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
-#define ETH_DMATDLAR_STL     0xFFFFFFFFU  /* Start of transmit list */
-
-/* Bit definition for Ethernet DMA Status Register */
-#define ETH_DMASR_TSTS       0x20000000U  /* Time-stamp trigger status */
-#define ETH_DMASR_PMTS       0x10000000U  /* PMT status */
-#define ETH_DMASR_MMCS       0x08000000U  /* MMC status */
-#define ETH_DMASR_EBS        0x03800000U  /* Error bits status */
-  /* combination with EBS[2:0] for GetFlagStatus function */
-  #define ETH_DMASR_EBS_DescAccess      0x02000000U  /* Error bits 0-data buffer, 1-desc. access */
-  #define ETH_DMASR_EBS_ReadTransf      0x01000000U  /* Error bits 0-write trnsf, 1-read transfr */
-  #define ETH_DMASR_EBS_DataTransfTx    0x00800000U  /* Error bits 0-Rx DMA, 1-Tx DMA */
-#define ETH_DMASR_TPS         0x00700000U  /* Transmit process state */
-  #define ETH_DMASR_TPS_Stopped         0x00000000U  /* Stopped - Reset or Stop Tx Command issued  */
-  #define ETH_DMASR_TPS_Fetching        0x00100000U  /* Running - fetching the Tx descriptor */
-  #define ETH_DMASR_TPS_Waiting         0x00200000U  /* Running - waiting for status */
-  #define ETH_DMASR_TPS_Reading         0x00300000U  /* Running - reading the data from host memory */
-  #define ETH_DMASR_TPS_Suspended       0x00600000U  /* Suspended - Tx Descriptor unavailabe */
-  #define ETH_DMASR_TPS_Closing         0x00700000U  /* Running - closing Rx descriptor */
-#define ETH_DMASR_RPS         0x000E0000U  /* Receive process state */
-  #define ETH_DMASR_RPS_Stopped         0x00000000U  /* Stopped - Reset or Stop Rx Command issued */
-  #define ETH_DMASR_RPS_Fetching        0x00020000U  /* Running - fetching the Rx descriptor */
-  #define ETH_DMASR_RPS_Waiting         0x00060000U  /* Running - waiting for packet */
-  #define ETH_DMASR_RPS_Suspended       0x00080000U  /* Suspended - Rx Descriptor unavailable */
-  #define ETH_DMASR_RPS_Closing         0x000A0000U  /* Running - closing descriptor */
-  #define ETH_DMASR_RPS_Queuing         0x000E0000U  /* Running - queuing the recieve frame into host memory */
-#define ETH_DMASR_NIS        0x00010000U  /* Normal interrupt summary */
-#define ETH_DMASR_AIS        0x00008000U  /* Abnormal interrupt summary */
-#define ETH_DMASR_ERS        0x00004000U  /* Early receive status */
-#define ETH_DMASR_FBES       0x00002000U  /* Fatal bus error status */
-#define ETH_DMASR_ETS        0x00000400U  /* Early transmit status */
-#define ETH_DMASR_RWTS       0x00000200U  /* Receive watchdog timeout status */
-#define ETH_DMASR_RPSS       0x00000100U  /* Receive process stopped status */
-#define ETH_DMASR_RBUS       0x00000080U  /* Receive buffer unavailable status */
-#define ETH_DMASR_RS         0x00000040U  /* Receive status */
-#define ETH_DMASR_TUS        0x00000020U  /* Transmit underflow status */
-#define ETH_DMASR_ROS        0x00000010U  /* Receive overflow status */
-#define ETH_DMASR_TJTS       0x00000008U  /* Transmit jabber timeout status */
-#define ETH_DMASR_TBUS       0x00000004U  /* Transmit buffer unavailable status */
-#define ETH_DMASR_TPSS       0x00000002U  /* Transmit process stopped status */
-#define ETH_DMASR_TS         0x00000001U  /* Transmit status */
-
-/* Bit definition for Ethernet DMA Operation Mode Register */
-#define ETH_DMAOMR_DTCEFD    0x04000000U  /* Disable Dropping of TCP/IP checksum error frames */
-#define ETH_DMAOMR_RSF       0x02000000U  /* Receive store and forward */
-#define ETH_DMAOMR_DFRF      0x01000000U  /* Disable flushing of received frames */
-#define ETH_DMAOMR_TSF       0x00200000U  /* Transmit store and forward */
-#define ETH_DMAOMR_FTF       0x00100000U  /* Flush transmit FIFO */
-#define ETH_DMAOMR_TTC       0x0001C000U  /* Transmit threshold control */
-  #define ETH_DMAOMR_TTC_64Bytes       0x00000000U  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
-  #define ETH_DMAOMR_TTC_128Bytes      0x00004000U  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
-  #define ETH_DMAOMR_TTC_192Bytes      0x00008000U  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
-  #define ETH_DMAOMR_TTC_256Bytes      0x0000C000U  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
-  #define ETH_DMAOMR_TTC_40Bytes       0x00010000U  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
-  #define ETH_DMAOMR_TTC_32Bytes       0x00014000U  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
-  #define ETH_DMAOMR_TTC_24Bytes       0x00018000U  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
-  #define ETH_DMAOMR_TTC_16Bytes       0x0001C000U  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
-#define ETH_DMAOMR_ST        0x00002000U  /* Start/stop transmission command */
-#define ETH_DMAOMR_FEF       0x00000080U  /* Forward error frames */
-#define ETH_DMAOMR_FUGF      0x00000040U  /* Forward undersized good frames */
-#define ETH_DMAOMR_RTC       0x00000018U  /* receive threshold control */
-  #define ETH_DMAOMR_RTC_64Bytes       0x00000000U  /* threshold level of the MTL Receive FIFO is 64 Bytes */
-  #define ETH_DMAOMR_RTC_32Bytes       0x00000008U  /* threshold level of the MTL Receive FIFO is 32 Bytes */
-  #define ETH_DMAOMR_RTC_96Bytes       0x00000010U  /* threshold level of the MTL Receive FIFO is 96 Bytes */
-  #define ETH_DMAOMR_RTC_128Bytes      0x00000018U  /* threshold level of the MTL Receive FIFO is 128 Bytes */
-#define ETH_DMAOMR_OSF       0x00000004U  /* operate on second frame */
-#define ETH_DMAOMR_SR        0x00000002U  /* Start/stop receive */
-
-/* Bit definition for Ethernet DMA Interrupt Enable Register */
-#define ETH_DMAIER_NISE      0x00010000U  /* Normal interrupt summary enable */
-#define ETH_DMAIER_AISE      0x00008000U  /* Abnormal interrupt summary enable */
-#define ETH_DMAIER_ERIE      0x00004000U  /* Early receive interrupt enable */
-#define ETH_DMAIER_FBEIE     0x00002000U  /* Fatal bus error interrupt enable */
-#define ETH_DMAIER_ETIE      0x00000400U  /* Early transmit interrupt enable */
-#define ETH_DMAIER_RWTIE     0x00000200U  /* Receive watchdog timeout interrupt enable */
-#define ETH_DMAIER_RPSIE     0x00000100U  /* Receive process stopped interrupt enable */
-#define ETH_DMAIER_RBUIE     0x00000080U  /* Receive buffer unavailable interrupt enable */
-#define ETH_DMAIER_RIE       0x00000040U  /* Receive interrupt enable */
-#define ETH_DMAIER_TUIE      0x00000020U  /* Transmit Underflow interrupt enable */
-#define ETH_DMAIER_ROIE      0x00000010U  /* Receive Overflow interrupt enable */
-#define ETH_DMAIER_TJTIE     0x00000008U  /* Transmit jabber timeout interrupt enable */
-#define ETH_DMAIER_TBUIE     0x00000004U  /* Transmit buffer unavailable interrupt enable */
-#define ETH_DMAIER_TPSIE     0x00000002U  /* Transmit process stopped interrupt enable */
-#define ETH_DMAIER_TIE       0x00000001U  /* Transmit interrupt enable */
-
-/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
-#define ETH_DMAMFBOCR_OFOC   0x10000000U  /* Overflow bit for FIFO overflow counter */
-#define ETH_DMAMFBOCR_MFA    0x0FFE0000U  /* Number of frames missed by the application */
-#define ETH_DMAMFBOCR_OMFC   0x00010000U  /* Overflow bit for missed frame counter */
-#define ETH_DMAMFBOCR_MFC    0x0000FFFFU  /* Number of frames missed by the controller */
-
-/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
-#define ETH_DMACHTDR_HTDAP   0xFFFFFFFFU  /* Host transmit descriptor address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
-#define ETH_DMACHRDR_HRDAP   0xFFFFFFFFU  /* Host receive descriptor address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
-#define ETH_DMACHTBAR_HTBAP  0xFFFFFFFFU  /* Host transmit buffer address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
-#define ETH_DMACHRBAR_HRBAP  0xFFFFFFFFU  /* Host receive buffer address pointer */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                       USB_OTG                              */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for USB_OTG_GOTGCTL register  ********************/
-#define USB_OTG_GOTGCTL_SRQSCS                  0x00000001U         /*!< Session request success */
-#define USB_OTG_GOTGCTL_SRQ                     0x00000002U         /*!< Session request */
-#define USB_OTG_GOTGCTL_VBVALOEN                0x00000004U         /*!< VBUS valid override enable */
-#define USB_OTG_GOTGCTL_VBVALOVAL               0x00000008U         /*!< VBUS valid override value */
-#define USB_OTG_GOTGCTL_AVALOEN                 0x00000010U         /*!< A-peripheral session valid override enable */
-#define USB_OTG_GOTGCTL_AVALOVAL                0x00000020U         /*!< A-peripheral session valid override value */
-#define USB_OTG_GOTGCTL_BVALOEN                 0x00000040U         /*!< B-peripheral session valid override enable */
-#define USB_OTG_GOTGCTL_BVALOVAL                0x00000080U         /*!< B-peripheral session valid override value  */
-#define USB_OTG_GOTGCTL_HNGSCS                  0x00000100U         /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_HNPRQ                   0x00000200U         /*!< HNP request */
-#define USB_OTG_GOTGCTL_HSHNPEN                 0x00000400U         /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_DHNPEN                  0x00000800U         /*!< Device HNP enabled */
-#define USB_OTG_GOTGCTL_EHEN                    0x00001000U         /*!< Embedded host enable */
-#define USB_OTG_GOTGCTL_CIDSTS                  0x00010000U         /*!< Connector ID status */
-#define USB_OTG_GOTGCTL_DBCT                    0x00020000U         /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD                   0x00040000U         /*!< A-session valid  */
-#define USB_OTG_GOTGCTL_BSESVLD                 0x00080000U         /*!< B-session valid */
-#define USB_OTG_GOTGCTL_OTGVER                  0x00100000U         /*!< OTG version  */
-
-/********************  Bit definition for USB_OTG_HCFG register  ********************/
-#define USB_OTG_HCFG_FSLSPCS                 0x00000003U            /*!< FS/LS PHY clock select  */
-#define USB_OTG_HCFG_FSLSPCS_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCFG_FSLSPCS_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCFG_FSLSS                   0x00000004U            /*!< FS- and LS-only support */
-
-/********************  Bit definition for USB_OTG_DCFG register  ********************/
-#define USB_OTG_DCFG_DSPD                    0x00000003U            /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                  0x00000001U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DSPD_1                  0x00000002U            /*!<Bit 1 */
-#define USB_OTG_DCFG_NZLSOHSK                0x00000004U            /*!< Nonzero-length status OUT handshake */
-
-#define USB_OTG_DCFG_DAD                     0x000007F0U            /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                   0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DAD_1                   0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCFG_DAD_2                   0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCFG_DAD_3                   0x00000080U            /*!<Bit 3 */
-#define USB_OTG_DCFG_DAD_4                   0x00000100U            /*!<Bit 4 */
-#define USB_OTG_DCFG_DAD_5                   0x00000200U            /*!<Bit 5 */
-#define USB_OTG_DCFG_DAD_6                   0x00000400U            /*!<Bit 6 */
-
-#define USB_OTG_DCFG_PFIVL                   0x00001800U            /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PFIVL_1                 0x00001000U            /*!<Bit 1 */
-
-#define USB_OTG_DCFG_PERSCHIVL               0x03000000U            /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0             0x01000000U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PERSCHIVL_1             0x02000000U            /*!<Bit 1 */
-
-/********************  Bit definition for USB_OTG_PCGCR register  ********************/
-#define USB_OTG_PCGCR_STPPCLK                 0x00000001U            /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK                0x00000002U            /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP                 0x00000010U            /*!< PHY suspended */
-
-/********************  Bit definition for USB_OTG_GOTGINT register  ********************/
-#define USB_OTG_GOTGINT_SEDET                   0x00000004U            /*!< Session end detected                   */
-#define USB_OTG_GOTGINT_SRSSCHG                 0x00000100U            /*!< Session request success status change  */
-#define USB_OTG_GOTGINT_HNSSCHG                 0x00000200U            /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET                  0x00020000U            /*!< Host negotiation detected              */
-#define USB_OTG_GOTGINT_ADTOCHG                 0x00040000U            /*!< A-device timeout change                */
-#define USB_OTG_GOTGINT_DBCDNE                  0x00080000U            /*!< Debounce done                          */
-#define USB_OTG_GOTGINT_IDCHNG                  0x00100000U            /*!< Change in ID pin input value           */
-
-/********************  Bit definition for USB_OTG_DCTL register  ********************/
-#define USB_OTG_DCTL_RWUSIG                  0x00000001U            /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS                    0x00000002U            /*!< Soft disconnect         */
-#define USB_OTG_DCTL_GINSTS                  0x00000004U            /*!< Global IN NAK status    */
-#define USB_OTG_DCTL_GONSTS                  0x00000008U            /*!< Global OUT NAK status   */
-
-#define USB_OTG_DCTL_TCTL                    0x00000070U            /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                  0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCTL_TCTL_1                  0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCTL_TCTL_2                  0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCTL_SGINAK                  0x00000080U            /*!< Set global IN NAK         */
-#define USB_OTG_DCTL_CGINAK                  0x00000100U            /*!< Clear global IN NAK       */
-#define USB_OTG_DCTL_SGONAK                  0x00000200U            /*!< Set global OUT NAK        */
-#define USB_OTG_DCTL_CGONAK                  0x00000400U            /*!< Clear global OUT NAK      */
-#define USB_OTG_DCTL_POPRGDNE                0x00000800U            /*!< Power-on programming done */
-
-/********************  Bit definition for USB_OTG_HFIR register  ********************/
-#define USB_OTG_HFIR_FRIVL                   0x0000FFFFU            /*!< Frame interval */
-
-/********************  Bit definition for USB_OTG_HFNUM register  ********************/
-#define USB_OTG_HFNUM_FRNUM                   0x0000FFFFU            /*!< Frame number         */
-#define USB_OTG_HFNUM_FTREM                   0xFFFF0000U            /*!< Frame time remaining */
-
-/********************  Bit definition for USB_OTG_DSTS register  ********************/
-#define USB_OTG_DSTS_SUSPSTS                 0x00000001U            /*!< Suspend status   */
-
-#define USB_OTG_DSTS_ENUMSPD                 0x00000006U            /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_DSTS_ENUMSPD_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_DSTS_EERR                    0x00000008U            /*!< Erratic error     */
-#define USB_OTG_DSTS_FNSOF                   0x003FFF00U            /*!< Frame number of the received SOF */
-
-/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
-#define USB_OTG_GAHBCFG_GINT                    0x00000001U            /*!< Global interrupt mask */
-#define USB_OTG_GAHBCFG_HBSTLEN                 0x0000001EU            /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_GAHBCFG_HBSTLEN_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_GAHBCFG_HBSTLEN_2               0x00000008U            /*!<Bit 2 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3               0x00000010U            /*!<Bit 3 */
-#define USB_OTG_GAHBCFG_DMAEN                   0x00000020U            /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL                 0x00000080U            /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL                0x00000100U            /*!< Periodic TxFIFO empty level */
-
-/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
-#define USB_OTG_GUSBCFG_TOCAL                   0x00000007U            /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TOCAL_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TOCAL_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_PHYSEL                  0x00000040U            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP                  0x00000100U            /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP                  0x00000200U            /*!< HNP-capable */
-#define USB_OTG_GUSBCFG_TRDT                    0x00003C00U            /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                  0x00000400U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TRDT_1                  0x00000800U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TRDT_2                  0x00001000U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_TRDT_3                  0x00002000U            /*!<Bit 3 */
-#define USB_OTG_GUSBCFG_PHYLPCS                 0x00008000U            /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS                0x00020000U            /*!< ULPI FS/LS select               */
-#define USB_OTG_GUSBCFG_ULPIAR                  0x00040000U            /*!< ULPI Auto-resume                */
-#define USB_OTG_GUSBCFG_ULPICSM                 0x00080000U            /*!< ULPI Clock SuspendM             */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD              0x00100000U            /*!< ULPI External VBUS Drive        */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI              0x00200000U            /*!< ULPI external VBUS indicator    */
-#define USB_OTG_GUSBCFG_TSDPS                   0x00400000U            /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI                    0x00800000U            /*!< Indicator complement            */
-#define USB_OTG_GUSBCFG_PTCI                    0x01000000U            /*!< Indicator pass through          */
-#define USB_OTG_GUSBCFG_ULPIIPD                 0x02000000U            /*!< ULPI interface protect disable  */
-#define USB_OTG_GUSBCFG_FHMOD                   0x20000000U            /*!< Forced host mode                */
-#define USB_OTG_GUSBCFG_FDMOD                   0x40000000U            /*!< Forced peripheral mode          */
-#define USB_OTG_GUSBCFG_CTXPKT                  0x80000000U            /*!< Corrupt Tx packet               */
-
-/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
-#define USB_OTG_GRSTCTL_CSRST                   0x00000001U            /*!< Core soft reset          */
-#define USB_OTG_GRSTCTL_HSRST                   0x00000002U            /*!< HCLK soft reset          */
-#define USB_OTG_GRSTCTL_FCRST                   0x00000004U            /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH                 0x00000010U            /*!< RxFIFO flush             */
-#define USB_OTG_GRSTCTL_TXFFLSH                 0x00000020U            /*!< TxFIFO flush             */
-#define USB_OTG_GRSTCTL_TXFNUM                  0x000007C0U            /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                0x00000040U            /*!<Bit 0 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                0x00000080U            /*!<Bit 1 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                0x00000100U            /*!<Bit 2 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                0x00000200U            /*!<Bit 3 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                0x00000400U            /*!<Bit 4 */
-#define USB_OTG_GRSTCTL_DMAREQ                  0x40000000U            /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL                  0x80000000U            /*!< AHB master idle */
-
-/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
-#define USB_OTG_DIEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask                 */
-#define USB_OTG_DIEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask                  */
-#define USB_OTG_DIEPMSK_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask          */
-#define USB_OTG_DIEPMSK_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask           */
-#define USB_OTG_DIEPMSK_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask                    */
-#define USB_OTG_DIEPMSK_TXFURM                  0x00000100U            /*!< FIFO underrun mask                                */
-#define USB_OTG_DIEPMSK_BIM                     0x00000200U            /*!< BNA interrupt mask                                */
-
-/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
-#define USB_OTG_HPTXSTS_PTXFSAVL                0x0000FFFFU            /*!< Periodic transmit data FIFO space available     */
-#define USB_OTG_HPTXSTS_PTXQSAV                 0x00FF0000U            /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0               0x00010000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1               0x00020000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2               0x00040000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3               0x00080000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4               0x00100000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5               0x00200000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6               0x00400000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7               0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_HPTXSTS_PTXQTOP                 0xFF000000U            /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0               0x01000000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1               0x02000000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2               0x04000000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3               0x08000000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4               0x10000000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5               0x20000000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6               0x40000000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7               0x80000000U            /*!<Bit 7 */
-
-/********************  Bit definition for USB_OTG_HAINT register  ********************/
-#define USB_OTG_HAINT_HAINT                     0x0000FFFFU            /*!< Channel interrupts */
-
-/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
-#define USB_OTG_DOEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask               */
-#define USB_OTG_DOEPMSK_STUPM                   0x00000008U            /*!< SETUP phase done mask                          */
-#define USB_OTG_DOEPMSK_OTEPDM                  0x00000010U            /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_OTEPSPRM                0x00000020U            /*!< Status Phase Received mask                     */
-#define USB_OTG_DOEPMSK_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received mask       */
-#define USB_OTG_DOEPMSK_OPEM                    0x00000100U            /*!< OUT packet error mask                          */
-#define USB_OTG_DOEPMSK_BOIM                    0x00000200U            /*!< BNA interrupt mask                             */
-
-/********************  Bit definition for USB_OTG_GINTSTS register  ********************/
-#define USB_OTG_GINTSTS_CMOD                    0x00000001U            /*!< Current mode of operation                      */
-#define USB_OTG_GINTSTS_MMIS                    0x00000002U            /*!< Mode mismatch interrupt                        */
-#define USB_OTG_GINTSTS_OTGINT                  0x00000004U            /*!< OTG interrupt                                  */
-#define USB_OTG_GINTSTS_SOF                     0x00000008U            /*!< Start of frame                                 */
-#define USB_OTG_GINTSTS_RXFLVL                  0x00000010U            /*!< RxFIFO nonempty                                */
-#define USB_OTG_GINTSTS_NPTXFE                  0x00000020U            /*!< Nonperiodic TxFIFO empty                       */
-#define USB_OTG_GINTSTS_GINAKEFF                0x00000040U            /*!< Global IN nonperiodic NAK effective            */
-#define USB_OTG_GINTSTS_BOUTNAKEFF              0x00000080U            /*!< Global OUT NAK effective                       */
-#define USB_OTG_GINTSTS_ESUSP                   0x00000400U            /*!< Early suspend                                  */
-#define USB_OTG_GINTSTS_USBSUSP                 0x00000800U            /*!< USB suspend                                    */
-#define USB_OTG_GINTSTS_USBRST                  0x00001000U            /*!< USB reset                                      */
-#define USB_OTG_GINTSTS_ENUMDNE                 0x00002000U            /*!< Enumeration done                               */
-#define USB_OTG_GINTSTS_ISOODRP                 0x00004000U            /*!< Isochronous OUT packet dropped interrupt       */
-#define USB_OTG_GINTSTS_EOPF                    0x00008000U            /*!< End of periodic frame interrupt                */
-#define USB_OTG_GINTSTS_IEPINT                  0x00040000U            /*!< IN endpoint interrupt                          */
-#define USB_OTG_GINTSTS_OEPINT                  0x00080000U            /*!< OUT endpoint interrupt                         */
-#define USB_OTG_GINTSTS_IISOIXFR                0x00100000U            /*!< Incomplete isochronous IN transfer             */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       0x00200000U            /*!< Incomplete periodic transfer                   */
-#define USB_OTG_GINTSTS_DATAFSUSP               0x00400000U            /*!< Data fetch suspended                           */
-#define USB_OTG_GINTSTS_RSTDET                  0x00800000U            /*!< Reset detected interrupt                       */
-#define USB_OTG_GINTSTS_HPRTINT                 0x01000000U            /*!< Host port interrupt                            */
-#define USB_OTG_GINTSTS_HCINT                   0x02000000U            /*!< Host channels interrupt                        */
-#define USB_OTG_GINTSTS_PTXFE                   0x04000000U            /*!< Periodic TxFIFO empty                          */
-#define USB_OTG_GINTSTS_LPMINT                  0x08000000U            /*!< LPM interrupt                                  */
-#define USB_OTG_GINTSTS_CIDSCHG                 0x10000000U            /*!< Connector ID status change                     */
-#define USB_OTG_GINTSTS_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt                  */
-#define USB_OTG_GINTSTS_SRQINT                  0x40000000U            /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT                  0x80000000U            /*!< Resume/remote wakeup detected interrupt        */
-
-/********************  Bit definition for USB_OTG_GINTMSK register  ********************/
-#define USB_OTG_GINTMSK_MMISM                   0x00000002U            /*!< Mode mismatch interrupt mask                        */
-#define USB_OTG_GINTMSK_OTGINT                  0x00000004U            /*!< OTG interrupt mask                                  */
-#define USB_OTG_GINTMSK_SOFM                    0x00000008U            /*!< Start of frame mask                                 */
-#define USB_OTG_GINTMSK_RXFLVLM                 0x00000010U            /*!< Receive FIFO nonempty mask                          */
-#define USB_OTG_GINTMSK_NPTXFEM                 0x00000020U            /*!< Nonperiodic TxFIFO empty mask                       */
-#define USB_OTG_GINTMSK_GINAKEFFM               0x00000040U            /*!< Global nonperiodic IN NAK effective mask            */
-#define USB_OTG_GINTMSK_GONAKEFFM               0x00000080U            /*!< Global OUT NAK effective mask                       */
-#define USB_OTG_GINTMSK_ESUSPM                  0x00000400U            /*!< Early suspend mask                                  */
-#define USB_OTG_GINTMSK_USBSUSPM                0x00000800U            /*!< USB suspend mask                                    */
-#define USB_OTG_GINTMSK_USBRST                  0x00001000U            /*!< USB reset mask                                      */
-#define USB_OTG_GINTMSK_ENUMDNEM                0x00002000U            /*!< Enumeration done mask                               */
-#define USB_OTG_GINTMSK_ISOODRPM                0x00004000U            /*!< Isochronous OUT packet dropped interrupt mask       */
-#define USB_OTG_GINTMSK_EOPFM                   0x00008000U            /*!< End of periodic frame interrupt mask                */
-#define USB_OTG_GINTMSK_EPMISM                  0x00020000U            /*!< Endpoint mismatch interrupt mask                    */
-#define USB_OTG_GINTMSK_IEPINT                  0x00040000U            /*!< IN endpoints interrupt mask                         */
-#define USB_OTG_GINTMSK_OEPINT                  0x00080000U            /*!< OUT endpoints interrupt mask                        */
-#define USB_OTG_GINTMSK_IISOIXFRM               0x00100000U            /*!< Incomplete isochronous IN transfer mask             */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         0x00200000U            /*!< Incomplete periodic transfer mask                   */
-#define USB_OTG_GINTMSK_FSUSPM                  0x00400000U            /*!< Data fetch suspended mask                           */
-#define USB_OTG_GINTMSK_RSTDEM                  0x00800000U            /*!< Reset detected interrupt mask                       */
-#define USB_OTG_GINTMSK_PRTIM                   0x01000000U            /*!< Host port interrupt mask                            */
-#define USB_OTG_GINTMSK_HCIM                    0x02000000U            /*!< Host channels interrupt mask                        */
-#define USB_OTG_GINTMSK_PTXFEM                  0x04000000U            /*!< Periodic TxFIFO empty mask                          */
-#define USB_OTG_GINTMSK_LPMINTM                 0x08000000U            /*!< LPM interrupt Mask                                  */
-#define USB_OTG_GINTMSK_CIDSCHGM                0x10000000U            /*!< Connector ID status change mask                     */
-#define USB_OTG_GINTMSK_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt mask                  */
-#define USB_OTG_GINTMSK_SRQIM                   0x40000000U            /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM                    0x80000000U            /*!< Resume/remote wakeup detected interrupt mask        */
-
-/********************  Bit definition for USB_OTG_DAINT register  ********************/
-#define USB_OTG_DAINT_IEPINT                  0x0000FFFFU            /*!< IN endpoint interrupt bits  */
-#define USB_OTG_DAINT_OEPINT                  0xFFFF0000U            /*!< OUT endpoint interrupt bits */
-
-/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
-#define USB_OTG_HAINTMSK_HAINTM                  0x0000FFFFU            /*!< Channel interrupt mask */
-
-/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
-#define USB_OTG_GRXSTSP_EPNUM                    0x0000000FU            /*!< IN EP interrupt mask bits  */
-#define USB_OTG_GRXSTSP_BCNT                     0x00007FF0U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID                     0x00018000U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS                   0x001E0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
-#define USB_OTG_DAINTMSK_IEPM                    0x0000FFFFU            /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM                    0xFFFF0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for OTG register  ********************/
-
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition for OTG register  ********************/
-
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
-#define USB_OTG_GRXFSIZ_RXFD            0x0000FFFFU            /*!< RxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
-#define USB_OTG_DVBUSDIS_VBUSDT         0x0000FFFFU            /*!< Device VBUS discharge time */
-
-/********************  Bit definition for OTG register  ********************/
-#define USB_OTG_NPTXFSA                 0x0000FFFFU            /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD                  0xFFFF0000U            /*!< Nonperiodic TxFIFO depth               */
-#define USB_OTG_TX0FSA                  0x0000FFFFU            /*!< Endpoint 0 transmit RAM start address  */
-#define USB_OTG_TX0FD                   0xFFFF0000U            /*!< Endpoint 0 TxFIFO depth                */
-
-/********************  Bit definition for USB_OTG_DVBUSPULSE register  ********************/
-#define USB_OTG_DVBUSPULSE_DVBUSP                0x00000FFFU            /*!< Device VBUS pulsing time */
-
-/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
-#define USB_OTG_GNPTXSTS_NPTXFSAV                0x0000FFFFU            /*!< Nonperiodic TxFIFO space available */
-
-#define USB_OTG_GNPTXSTS_NPTQXSAV                0x00FF0000U            /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0              0x00010000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1              0x00020000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2              0x00040000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3              0x00080000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4              0x00100000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5              0x00200000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6              0x00400000U            /*!<Bit 6 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7              0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_GNPTXSTS_NPTXQTOP                0x7F000000U            /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0              0x01000000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1              0x02000000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2              0x04000000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3              0x08000000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4              0x10000000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5              0x20000000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6              0x40000000U            /*!<Bit 6 */
-
-/********************  Bit definition for USB_OTG_DTHRCTL register  ********************/
-#define USB_OTG_DTHRCTL_NONISOTHREN             0x00000001U            /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN                0x00000002U            /*!< ISO IN endpoint threshold enable */
-
-#define USB_OTG_DTHRCTL_TXTHRLEN                0x000007FCU            /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0              0x00000004U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1              0x00000008U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2              0x00000010U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3              0x00000020U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4              0x00000040U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5              0x00000080U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6              0x00000100U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7              0x00000200U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8              0x00000400U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_RXTHREN                 0x00010000U            /*!< Receive threshold enable */
-
-#define USB_OTG_DTHRCTL_RXTHRLEN                0x03FE0000U            /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0              0x00020000U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1              0x00040000U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2              0x00080000U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3              0x00100000U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4              0x00200000U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5              0x00400000U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6              0x00800000U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7              0x01000000U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8              0x02000000U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_ARPEN                   0x08000000U            /*!< Arbiter parking enable */
-
-/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM            0x0000FFFFU         /*!< IN EP Tx FIFO empty interrupt mask bits */
-
-/********************  Bit definition for USB_OTG_DEACHINT register  ********************/
-#define USB_OTG_DEACHINT_IEP1INT                0x00000002U           /*!< IN endpoint 1interrupt bit   */
-#define USB_OTG_DEACHINT_OEP1INT                0x00020000U           /*!< OUT endpoint 1 interrupt bit */
-
-/********************  Bit definition for USB_OTG_GCCFG register  ********************/
-#define USB_OTG_GCCFG_PWRDWN                 0x00010000U              /*!< Power down */
-#define USB_OTG_GCCFG_VBDEN                  0x00200000U              /*!< USB VBUS Detection Enable */
-
-/********************  Bit definition for USB_OTG_GPWRDN) register  ********************/
-#define USB_OTG_GPWRDN_ADPMEN                 0x00000001U             /*!< ADP module enable */
-#define USB_OTG_GPWRDN_ADPIF                  0x00800000U             /*!< ADP Interrupt flag */
-
-/********************  Bit definition for USB_OTG_DEACHINTMSK register  ********************/
-#define USB_OTG_DEACHINTMSK_IEP1INTM          0x00000002U            /*!< IN Endpoint 1 interrupt mask bit  */
-#define USB_OTG_DEACHINTMSK_OEP1INTM          0x00020000U            /*!< OUT Endpoint 1 interrupt mask bit */
-
-/********************  Bit definition for USB_OTG_CID register  ********************/
-#define USB_OTG_CID_PRODUCT_ID               0xFFFFFFFFU            /*!< Product ID field */
-
-/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/
-#define  USB_OTG_GLPMCFG_LPMEN               0x00000001U            /*!< LPM support enable                                     */
-#define  USB_OTG_GLPMCFG_LPMACK              0x00000002U            /*!< LPM Token acknowledge enable                           */
-#define  USB_OTG_GLPMCFG_BESL                0x0000003CU            /*!< BESL value received with last ACKed LPM Token          */
-#define  USB_OTG_GLPMCFG_REMWAKE             0x00000040U            /*!< bRemoteWake value received with last ACKed LPM Token   */
-#define  USB_OTG_GLPMCFG_L1SSEN              0x00000080U            /*!< L1 shallow sleep enable                                */
-#define  USB_OTG_GLPMCFG_BESLTHRS            0x00000F00U            /*!< BESL threshold                                         */
-#define  USB_OTG_GLPMCFG_L1DSEN              0x00001000U            /*!< L1 deep sleep enable                                   */
-#define  USB_OTG_GLPMCFG_LPMRSP              0x00006000U            /*!< LPM response                                           */
-#define  USB_OTG_GLPMCFG_SLPSTS              0x00008000U            /*!< Port sleep status                                      */
-#define  USB_OTG_GLPMCFG_L1RSMOK             0x00010000U            /*!< Sleep State Resume OK                                  */
-#define  USB_OTG_GLPMCFG_LPMCHIDX            0x001E0000U            /*!< LPM Channel Index                                      */
-#define  USB_OTG_GLPMCFG_LPMRCNT             0x00E00000U            /*!< LPM retry count                                        */
-#define  USB_OTG_GLPMCFG_SNDLPM              0x01000000U            /*!< Send LPM transaction                                   */
-#define  USB_OTG_GLPMCFG_LPMRCNTSTS          0x0E000000U            /*!< LPM retry count status                                 */
-#define  USB_OTG_GLPMCFG_ENBESL              0x10000000U            /*!< Enable best effort service latency                     */
-
-/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
-#define USB_OTG_DIEPEACHMSK1_XFRCM           0x00000001U            /*!< Transfer completed interrupt mask                 */
-#define USB_OTG_DIEPEACHMSK1_EPDM            0x00000002U            /*!< Endpoint disabled interrupt mask                  */
-#define USB_OTG_DIEPEACHMSK1_TOM             0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK       0x00000010U            /*!< IN token received when TxFIFO empty mask          */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM         0x00000020U            /*!< IN token received with EP mismatch mask           */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM         0x00000040U            /*!< IN endpoint NAK effective mask                    */
-#define USB_OTG_DIEPEACHMSK1_TXFURM          0x00000100U            /*!< FIFO underrun mask                                */
-#define USB_OTG_DIEPEACHMSK1_BIM             0x00000200U            /*!< BNA interrupt mask                                */
-#define USB_OTG_DIEPEACHMSK1_NAKM            0x00002000U            /*!< NAK interrupt mask                                */
-
-/********************  Bit definition for USB_OTG_HPRT register  ********************/
-#define USB_OTG_HPRT_PCSTS                   0x00000001U            /*!< Port connect status        */
-#define USB_OTG_HPRT_PCDET                   0x00000002U            /*!< Port connect detected      */
-#define USB_OTG_HPRT_PENA                    0x00000004U            /*!< Port enable                */
-#define USB_OTG_HPRT_PENCHNG                 0x00000008U            /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA                    0x00000010U            /*!< Port overcurrent active    */
-#define USB_OTG_HPRT_POCCHNG                 0x00000020U            /*!< Port overcurrent change    */
-#define USB_OTG_HPRT_PRES                    0x00000040U            /*!< Port resume                */
-#define USB_OTG_HPRT_PSUSP                   0x00000080U            /*!< Port suspend               */
-#define USB_OTG_HPRT_PRST                    0x00000100U            /*!< Port reset                 */
-
-#define USB_OTG_HPRT_PLSTS                   0x00000C00U            /*!< Port line status           */
-#define USB_OTG_HPRT_PLSTS_0                 0x00000400U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PLSTS_1                 0x00000800U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PPWR                    0x00001000U            /*!< Port power                 */
-
-#define USB_OTG_HPRT_PTCTL                   0x0001E000U            /*!< Port test control          */
-#define USB_OTG_HPRT_PTCTL_0                 0x00002000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PTCTL_1                 0x00004000U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PTCTL_2                 0x00008000U            /*!<Bit 2 */
-#define USB_OTG_HPRT_PTCTL_3                 0x00010000U            /*!<Bit 3 */
-
-#define USB_OTG_HPRT_PSPD                    0x00060000U            /*!< Port speed                 */
-#define USB_OTG_HPRT_PSPD_0                  0x00020000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PSPD_1                  0x00040000U            /*!<Bit 1 */
-
-/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
-#define USB_OTG_DOEPEACHMSK1_XFRCM               0x00000001U            /*!< Transfer completed interrupt mask         */
-#define USB_OTG_DOEPEACHMSK1_EPDM                0x00000002U            /*!< Endpoint disabled interrupt mask          */
-#define USB_OTG_DOEPEACHMSK1_TOM                 0x00000008U            /*!< Timeout condition mask                    */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           0x00000010U            /*!< IN token received when TxFIFO empty mask  */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM             0x00000020U            /*!< IN token received with EP mismatch mask   */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM             0x00000040U            /*!< IN endpoint NAK effective mask            */
-#define USB_OTG_DOEPEACHMSK1_TXFURM              0x00000100U            /*!< OUT packet error mask                     */
-#define USB_OTG_DOEPEACHMSK1_BIM                 0x00000200U            /*!< BNA interrupt mask                        */
-#define USB_OTG_DOEPEACHMSK1_BERRM               0x00001000U            /*!< Bubble error interrupt mask               */
-#define USB_OTG_DOEPEACHMSK1_NAKM                0x00002000U            /*!< NAK interrupt mask                        */
-#define USB_OTG_DOEPEACHMSK1_NYETM               0x00004000U            /*!< NYET interrupt mask                       */
-
-/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
-#define USB_OTG_HPTXFSIZ_PTXSA                   0x0000FFFFU            /*!< Host periodic TxFIFO start address            */
-#define USB_OTG_HPTXFSIZ_PTXFD                   0xFFFF0000U            /*!< Host periodic TxFIFO depth                    */
-
-/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
-#define USB_OTG_DIEPCTL_MPSIZ                   0x000007FFU            /*!< Maximum packet size              */
-#define USB_OTG_DIEPCTL_USBAEP                  0x00008000U            /*!< USB active endpoint              */
-#define USB_OTG_DIEPCTL_EONUM_DPID              0x00010000U            /*!< Even/odd frame                   */
-#define USB_OTG_DIEPCTL_NAKSTS                  0x00020000U            /*!< NAK status                       */
-
-#define USB_OTG_DIEPCTL_EPTYP                   0x000C0000U            /*!< Endpoint type                    */
-#define USB_OTG_DIEPCTL_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_STALL                   0x00200000U            /*!< STALL handshake                  */
-
-#define USB_OTG_DIEPCTL_TXFNUM                  0x03C00000U            /*!< TxFIFO number                    */
-#define USB_OTG_DIEPCTL_TXFNUM_0                0x00400000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                0x00800000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                0x01000000U            /*!<Bit 2 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                0x02000000U            /*!<Bit 3 */
-#define USB_OTG_DIEPCTL_CNAK                    0x04000000U            /*!< Clear NAK                        */
-#define USB_OTG_DIEPCTL_SNAK                    0x08000000U            /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          0x10000000U            /*!< Set DATA0 PID                    */
-#define USB_OTG_DIEPCTL_SODDFRM                 0x20000000U            /*!< Set odd frame                    */
-#define USB_OTG_DIEPCTL_EPDIS                   0x40000000U            /*!< Endpoint disable                 */
-#define USB_OTG_DIEPCTL_EPENA                   0x80000000U            /*!< Endpoint enable                  */
-
-/********************  Bit definition for USB_OTG_HCCHAR register  ********************/
-#define USB_OTG_HCCHAR_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
-
-#define USB_OTG_HCCHAR_EPNUM                   0x00007800U            /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPNUM_1                 0x00001000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_EPNUM_2                 0x00002000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_EPNUM_3                 0x00004000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_EPDIR                   0x00008000U            /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV                   0x00020000U            /*!< Low-speed device */
-
-#define USB_OTG_HCCHAR_EPTYP                   0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_MC                      0x00300000U            /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                    0x00100000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_MC_1                    0x00200000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_DAD                     0x1FC00000U            /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                   0x00400000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_DAD_1                   0x00800000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_DAD_2                   0x01000000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_DAD_3                   0x02000000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_DAD_4                   0x04000000U            /*!<Bit 4 */
-#define USB_OTG_HCCHAR_DAD_5                   0x08000000U            /*!<Bit 5 */
-#define USB_OTG_HCCHAR_DAD_6                   0x10000000U            /*!<Bit 6 */
-#define USB_OTG_HCCHAR_ODDFRM                  0x20000000U            /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS                   0x40000000U            /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA                   0x80000000U            /*!< Channel enable */
-
-/********************  Bit definition for USB_OTG_HCSPLT register  ********************/
-
-#define USB_OTG_HCSPLT_PRTADDR                 0x0000007FU            /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_PRTADDR_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_PRTADDR_2               0x00000004U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_PRTADDR_3               0x00000008U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_PRTADDR_4               0x00000010U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_PRTADDR_5               0x00000020U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_PRTADDR_6               0x00000040U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_HUBADDR                 0x00003F80U            /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0               0x00000080U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_HUBADDR_1               0x00000100U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_HUBADDR_2               0x00000200U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_HUBADDR_3               0x00000400U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_HUBADDR_4               0x00000800U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_HUBADDR_5               0x00001000U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_HUBADDR_6               0x00002000U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_XACTPOS                 0x0000C000U            /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0               0x00004000U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_XACTPOS_1               0x00008000U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_COMPLSPLT               0x00010000U            /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN                 0x80000000U            /*!< Split enable */
-
-/********************  Bit definition for USB_OTG_HCINT register  ********************/
-#define USB_OTG_HCINT_XFRC                    0x00000001U            /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH                     0x00000002U            /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINT_STALL                   0x00000008U            /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK                     0x00000010U            /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK                     0x00000020U            /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET                    0x00000040U            /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR                   0x00000080U            /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR                   0x00000100U            /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR                   0x00000200U            /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR                   0x00000400U            /*!< Data toggle error */
-
-/********************  Bit definition for USB_OTG_DIEPINT register  ********************/
-#define USB_OTG_DIEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_TOC                     0x00000008U            /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE                  0x00000010U            /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNE                  0x00000040U            /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE                    0x00000080U            /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN              0x00000100U            /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA                     0x00000200U            /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS               0x00000800U            /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR                    0x00001000U            /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK                     0x00002000U            /*!< NAK interrupt */
-
-/********************  Bit definition for USB_OTG_HCINTMSK register  ********************/
-#define USB_OTG_HCINTMSK_XFRCM                   0x00000001U            /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM                    0x00000002U            /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM                  0x00000008U            /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM                    0x00000010U            /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM                    0x00000020U            /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET                    0x00000040U            /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM                  0x00000080U            /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM                  0x00000100U            /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM                  0x00000200U            /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM                  0x00000400U            /*!< Data toggle error mask */
-
-/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
-
-#define USB_OTG_DIEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT                  0x60000000U            /*!< Packet count */
-/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
-#define USB_OTG_HCTSIZ_XFRSIZ                    0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT                    0x1FF80000U            /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING                    0x80000000U            /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID                      0x60000000U            /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                    0x20000000U            /*!<Bit 0 */
-#define USB_OTG_HCTSIZ_DPID_1                    0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
-#define USB_OTG_DIEPDMA_DMAADDR                  0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition for USB_OTG_HCDMA register  ********************/
-#define USB_OTG_HCDMA_DMAADDR                    0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
-#define USB_OTG_DTXFSTS_INEPTFSAV                0x0000FFFFU            /*!< IN endpoint TxFIFO space available */
-
-/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
-#define USB_OTG_DIEPTXF_INEPTXSA                 0x0000FFFFU            /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD                 0xFFFF0000U            /*!< IN endpoint TxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
-#define USB_OTG_DOEPCTL_MPSIZ                     0x000007FFU            /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP                    0x00008000U            /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS                    0x00020000U            /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            0x10000000U            /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM                   0x20000000U            /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP                     0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                   0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DOEPCTL_EPTYP_1                   0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_SNPM                      0x00100000U            /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL                     0x00200000U            /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK                      0x04000000U            /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK                      0x08000000U            /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS                     0x40000000U            /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA                     0x80000000U            /*!< Endpoint enable */
-
-/********************  Bit definition for USB_OTG_DOEPINT register  ********************/
-#define USB_OTG_DOEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_STUP                    0x00000008U            /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS                 0x00000010U            /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_OTEPSPR                 0x00000020U            /*!< Status Phase Received For Control Write */
-#define USB_OTG_DOEPINT_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_NYET                    0x00004000U            /*!< NYET interrupt */
-
-/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
-#define USB_OTG_DOEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-
-#define USB_OTG_DOEPTSIZ_STUPCNT                 0x60000000U            /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0               0x20000000U            /*!<Bit 0 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1               0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition for PCGCCTL register  ********************/
-#define USB_OTG_PCGCCTL_STOPCLK                 0x00000001U            /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK                 0x00000002U            /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP                 0x00000010U            /*!<Bit 1 */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                        JPEG Encoder/Decoder                                */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for CONFR0 register  ********************/
-#define  JPEG_CONFR0_START                       0x00000001U        /*!<Start/Stop bit */
-
-/********************  Bit definition for CONFR1 register  *******************/
-#define  JPEG_CONFR1_NF                          0x00000003U        /*!<Number of color components */
-#define  JPEG_CONFR1_NF_0                        0x00000001U        /*!<Bit 0 */
-#define  JPEG_CONFR1_NF_1                        0x00000002U        /*!<Bit 1 */
-#define  JPEG_CONFR1_RE                          0x00000004U        /*!<Restart maker Enable */
-#define  JPEG_CONFR1_DE                          0x00000008U        /*!<Decoding Enable */
-#define  JPEG_CONFR1_COLORSPACE                  0x00000030U        /*!<Color Space */
-#define  JPEG_CONFR1_COLORSPACE_0                0x00000010U        /*!<Bit 0 */
-#define  JPEG_CONFR1_COLORSPACE_1                0x00000020U        /*!<Bit 1 */
-#define  JPEG_CONFR1_NS                          0x000000C0U        /*!<Number of components for Scan */
-#define  JPEG_CONFR1_NS_0                        0x00000040U        /*!<Bit 0 */
-#define  JPEG_CONFR1_NS_1                        0x00000080U        /*!<Bit 1 */
-#define  JPEG_CONFR1_HDR                         0x00000100U        /*!<Header Processing On/Off */
-#define  JPEG_CONFR1_YSIZE                       0xFFFF0000U        /*!<Number of lines in source image */
-
-/********************  Bit definition for CONFR2 register  *******************/
-#define  JPEG_CONFR2_NMCU                        0x03FFFFFFU        /*!<Number of MCU units minus 1 to encode */
-
-/********************  Bit definition for CONFR3 register  *******************/
-#define  JPEG_CONFR3_NRST                        0x0000FFFFU        /*!<Number of MCU between two restart makers minus 1 */
-#define  JPEG_CONFR3_XSIZE                       0xFFFF0000U        /*!<Number of pixels per line */
-
-/********************  Bit definition for CONFR4 register  *******************/
-#define  JPEG_CONFR4_HD                          0x00000001U        /*!<Selects the Huffman table for encoding the DC coefficients */
-#define  JPEG_CONFR4_HA                          0x00000002U        /*!<Selects the Huffman table for encoding the AC coefficients */
-#define  JPEG_CONFR4_QT                          0x0000000CU        /*!<Selects quantization table associated with a color component */
-#define  JPEG_CONFR4_QT_0                        0x00000004U        /*!<Bit 0 */
-#define  JPEG_CONFR4_QT_1                        0x00000008U        /*!<Bit 1 */
-#define  JPEG_CONFR4_NB                          0x000000F0U        /*!<Number of data units minus 1 that belong to a particular color in the MCU */
-#define  JPEG_CONFR4_NB_0                        0x00000010U        /*!<Bit 0 */
-#define  JPEG_CONFR4_NB_1                        0x00000020U        /*!<Bit 1 */
-#define  JPEG_CONFR4_NB_2                        0x00000040U        /*!<Bit 2 */
-#define  JPEG_CONFR4_NB_3                        0x00000080U        /*!<Bit 3 */
-#define  JPEG_CONFR4_VSF                         0x00000F00U        /*!<Vertical sampling factor for component 1 */
-#define  JPEG_CONFR4_VSF_0                       0x00000100U        /*!<Bit 0 */
-#define  JPEG_CONFR4_VSF_1                       0x00000200U        /*!<Bit 1 */
-#define  JPEG_CONFR4_VSF_2                       0x00000400U        /*!<Bit 2 */
-#define  JPEG_CONFR4_VSF_3                       0x00000800U        /*!<Bit 3 */
-#define  JPEG_CONFR4_HSF                         0x0000F000U        /*!<Horizontal sampling factor for component 1 */
-#define  JPEG_CONFR4_HSF_0                       0x00001000U        /*!<Bit 0 */
-#define  JPEG_CONFR4_HSF_1                       0x00002000U        /*!<Bit 1 */
-#define  JPEG_CONFR4_HSF_2                       0x00004000U        /*!<Bit 2 */
-#define  JPEG_CONFR4_HSF_3                       0x00008000U        /*!<Bit 3 */
-
-/********************  Bit definition for CONFR5 register  *******************/
-#define  JPEG_CONFR5_HD                          0x00000001U        /*!<Selects the Huffman table for encoding the DC coefficients */
-#define  JPEG_CONFR5_HA                          0x00000002U        /*!<Selects the Huffman table for encoding the AC coefficients */
-#define  JPEG_CONFR5_QT                          0x0000000CU        /*!<Selects quantization table associated with a color component */
-#define  JPEG_CONFR5_QT_0                        0x00000004U        /*!<Bit 0 */
-#define  JPEG_CONFR5_QT_1                        0x00000008U        /*!<Bit 1 */
-#define  JPEG_CONFR5_NB                          0x000000F0U        /*!<Number of data units minus 1 that belong to a particular color in the MCU */
-#define  JPEG_CONFR5_NB_0                        0x00000010U        /*!<Bit 0 */
-#define  JPEG_CONFR5_NB_1                        0x00000020U        /*!<Bit 1 */
-#define  JPEG_CONFR5_NB_2                        0x00000040U        /*!<Bit 2 */
-#define  JPEG_CONFR5_NB_3                        0x00000080U        /*!<Bit 3 */
-#define  JPEG_CONFR5_VSF                         0x00000F00U        /*!<Vertical sampling factor for component 2 */
-#define  JPEG_CONFR5_VSF_0                       0x00000100U        /*!<Bit 0 */
-#define  JPEG_CONFR5_VSF_1                       0x00000200U        /*!<Bit 1 */
-#define  JPEG_CONFR5_VSF_2                       0x00000400U        /*!<Bit 2 */
-#define  JPEG_CONFR5_VSF_3                       0x00000800U        /*!<Bit 3 */
-#define  JPEG_CONFR5_HSF                         0x0000F000U        /*!<Horizontal sampling factor for component 2 */
-#define  JPEG_CONFR5_HSF_0                       0x00001000U        /*!<Bit 0 */
-#define  JPEG_CONFR5_HSF_1                       0x00002000U        /*!<Bit 1 */
-#define  JPEG_CONFR5_HSF_2                       0x00004000U        /*!<Bit 2 */
-#define  JPEG_CONFR5_HSF_3                       0x00008000U        /*!<Bit 3 */
-
-/********************  Bit definition for CONFR6 register  *******************/
-#define  JPEG_CONFR6_HD                          0x00000001U        /*!<Selects the Huffman table for encoding the DC coefficients */
-#define  JPEG_CONFR6_HA                          0x00000002U        /*!<Selects the Huffman table for encoding the AC coefficients */
-#define  JPEG_CONFR6_QT                          0x0000000CU        /*!<Selects quantization table associated with a color component */
-#define  JPEG_CONFR6_QT_0                        0x00000004U        /*!<Bit 0 */
-#define  JPEG_CONFR6_QT_1                        0x00000008U        /*!<Bit 1 */
-#define  JPEG_CONFR6_NB                          0x000000F0U        /*!<Number of data units minus 1 that belong to a particular color in the MCU */
-#define  JPEG_CONFR6_NB_0                        0x00000010U        /*!<Bit 0 */
-#define  JPEG_CONFR6_NB_1                        0x00000020U        /*!<Bit 1 */
-#define  JPEG_CONFR6_NB_2                        0x00000040U        /*!<Bit 2 */
-#define  JPEG_CONFR6_NB_3                        0x00000080U        /*!<Bit 3 */
-#define  JPEG_CONFR6_VSF                         0x00000F00U        /*!<Vertical sampling factor for component 2 */
-#define  JPEG_CONFR6_VSF_0                       0x00000100U        /*!<Bit 0 */
-#define  JPEG_CONFR6_VSF_1                       0x00000200U        /*!<Bit 1 */
-#define  JPEG_CONFR6_VSF_2                       0x00000400U        /*!<Bit 2 */
-#define  JPEG_CONFR6_VSF_3                       0x00000800U        /*!<Bit 3 */
-#define  JPEG_CONFR6_HSF                         0x0000F000U        /*!<Horizontal sampling factor for component 2 */
-#define  JPEG_CONFR6_HSF_0                       0x00001000U        /*!<Bit 0 */
-#define  JPEG_CONFR6_HSF_1                       0x00002000U        /*!<Bit 1 */
-#define  JPEG_CONFR6_HSF_2                       0x00004000U        /*!<Bit 2 */
-#define  JPEG_CONFR6_HSF_3                       0x00008000U        /*!<Bit 3 */
-
-/********************  Bit definition for CONFR7 register  *******************/
-#define  JPEG_CONFR7_HD                          0x00000001U        /*!<Selects the Huffman table for encoding the DC coefficients */
-#define  JPEG_CONFR7_HA                          0x00000002U        /*!<Selects the Huffman table for encoding the AC coefficients */
-#define  JPEG_CONFR7_QT                          0x0000000CU        /*!<Selects quantization table associated with a color component */
-#define  JPEG_CONFR7_QT_0                        0x00000004U        /*!<Bit 0 */
-#define  JPEG_CONFR7_QT_1                        0x00000008U        /*!<Bit 1 */
-#define  JPEG_CONFR7_NB                          0x000000F0U        /*!<Number of data units minus 1 that belong to a particular color in the MCU */
-#define  JPEG_CONFR7_NB_0                        0x00000010U        /*!<Bit 0 */
-#define  JPEG_CONFR7_NB_1                        0x00000020U        /*!<Bit 1 */
-#define  JPEG_CONFR7_NB_2                        0x00000040U        /*!<Bit 2 */
-#define  JPEG_CONFR7_NB_3                        0x00000080U        /*!<Bit 3 */
-#define  JPEG_CONFR7_VSF                         0x00000F00U        /*!<Vertical sampling factor for component 2 */
-#define  JPEG_CONFR7_VSF_0                       0x00000100U        /*!<Bit 0 */
-#define  JPEG_CONFR7_VSF_1                       0x00000200U        /*!<Bit 1 */
-#define  JPEG_CONFR7_VSF_2                       0x00000400U        /*!<Bit 2 */
-#define  JPEG_CONFR7_VSF_3                       0x00000800U        /*!<Bit 3 */
-#define  JPEG_CONFR7_HSF                         0x0000F000U        /*!<Horizontal sampling factor for component 2 */
-#define  JPEG_CONFR7_HSF_0                       0x00001000U        /*!<Bit 0 */
-#define  JPEG_CONFR7_HSF_1                       0x00002000U        /*!<Bit 1 */
-#define  JPEG_CONFR7_HSF_2                       0x00004000U        /*!<Bit 2 */
-#define  JPEG_CONFR7_HSF_3                       0x00008000U        /*!<Bit 3 */
-
-/********************  Bit definition for CR register  *******************/
-#define  JPEG_CR_JCEN                            0x00000001U        /*!<Enable the JPEG Codec Core */
-#define  JPEG_CR_IFTIE                           0x00000002U        /*!<Input FIFO Threshold Interrupt Enable */
-#define  JPEG_CR_IFNFIE                          0x00000004U        /*!<Input FIFO Not Full Interrupt Enable */
-#define  JPEG_CR_OFTIE                           0x00000008U        /*!<Output FIFO Threshold Interrupt Enable */
-#define  JPEG_CR_OFNEIE                          0x00000010U        /*!<Output FIFO Not Empty Interrupt Enable */
-#define  JPEG_CR_EOCIE                           0x00000020U        /*!<End of Conversion Interrupt Enable */
-#define  JPEG_CR_HPDIE                           0x00000040U        /*!<Header Parsing Done Interrupt Enable */
-#define  JPEG_CR_IDMAEN                          0x00000800U        /*!<Enable the DMA request generation for the input FIFO */
-#define  JPEG_CR_ODMAEN                          0x00001000U        /*!<Enable the DMA request generation for the output FIFO */
-#define  JPEG_CR_IFF                             0x00002000U        /*!<Flush the input FIFO */
-#define  JPEG_CR_OFF                             0x00004000U        /*!<Flush the output FIFO */
-
-/********************  Bit definition for SR register  *******************/
-#define  JPEG_SR_IFTF                            0x00000002U        /*!<Input FIFO is not full and is bellow its threshold flag */
-#define  JPEG_SR_IFNFF                           0x00000004U        /*!<Input FIFO Not Full Flag, a data can be written */
-#define  JPEG_SR_OFTF                            0x00000008U        /*!<Output FIFO is not empty and has reach its threshold */
-#define  JPEG_SR_OFNEF                           0x000000010U       /*!<Output FIFO is not empty, a data is available */
-#define  JPEG_SR_EOCF                            0x000000020U       /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */
-#define  JPEG_SR_HPDF                            0x000000040U       /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */
-#define  JPEG_SR_COF                             0x000000080U       /*!<JPEG Codec operation on going  flag */
-
-/********************  Bit definition for CFR register  *******************/
-#define  JPEG_CFR_CEOCF                          0x00000020U       /*!<Clear End of Conversion Flag */
-#define  JPEG_CFR_CHPDF                          0x00000040U       /*!<Clear Header Parsing Done Flag */
-
-/********************  Bit definition for DIR register  ********************/
-#define  JPEG_DIR_DATAIN                         0xFFFFFFFFU        /*!<Data Input FIFO */
-
-/********************  Bit definition for DOR register  ********************/
-#define  JPEG_DOR_DATAOUT                        0xFFFFFFFFU        /*!<Data Output FIFO */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                MDIOS                                        */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for MDIOS_CR register  *******************/
-#define MDIOS_CR_EN               0x00000001U    /*!<Peripheral enable */
-#define MDIOS_CR_WRIE             0x00000002U    /*!<Register write interrupt enable */
-#define MDIOS_CR_RDIE             0x00000004U    /*!<Register Read Interrupt Enable */
-#define MDIOS_CR_EIE              0x00000008U    /*!<Error interrupt enable */
-#define MDIOS_CR_DPC              0x00000080U    /*!<Disable Preamble Check */
-#define MDIOS_CR_PORT_ADDRESS     0x00001F00U    /*!<PORT_ADDRESS[4:0] bits */
-#define MDIOS_CR_PORT_ADDRESS_0   0x00000100U    /*!<Bit 0 */
-#define MDIOS_CR_PORT_ADDRESS_1   0x00000200U    /*!<Bit 1 */
-#define MDIOS_CR_PORT_ADDRESS_2   0x00000400U    /*!<Bit 2 */
-#define MDIOS_CR_PORT_ADDRESS_3   0x00000800U    /*!<Bit 3 */
-#define MDIOS_CR_PORT_ADDRESS_4   0x00001000U    /*!<Bit 4 */
-
-/********************  Bit definition for MDIOS_WRFR register  *******************/
-#define MDIOS_WRFR_WRF            0xFFFFFFFFU    /*!<WRF[31:0] bits (Write flags for MDIO register 0 to 31) */
-
-/********************  Bit definition for MDIOS_CWRFR register  *******************/
-#define MDIOS_CWRFR_CWRF           0xFFFFFFFFU    /*!<CWRF[31:0] bits (Clear the write flag for MDIO register 0 to 31) */
-
-/********************  Bit definition for MDIOS_RDFR register  *******************/
-#define MDIOS_RDFR_RDF           0xFFFFFFFFU      /*!<RDF[31:0] bits (Read flags for MDIO registers 0 to 31) */
-
-/********************  Bit definition for MDIOS_CRDFR register  *******************/
-#define MDIOS_CRDFR_CRDF          0xFFFFFFFFU      /*!<CRDF[31:0] bits (Clear the read flag for MDIO registers 0 to 31) */
-
-/********************  Bit definition for MDIOS_SR register  *******************/
-#define MDIOS_SR_PERF             0x00000001U    /*!< Preamble error flag */
-#define MDIOS_SR_SERF             0x00000002U    /*!< Start error flag */
-#define MDIOS_SR_TERF             0x00000004U    /*!< Turnaround error flag */
-
-/********************  Bit definition for MDIOS_CLRFR register  *******************/
-#define MDIOS_CLRFR_CPERF             0x00000001U    /*!< Clear the preamble error flag */
-#define MDIOS_CLRFR_CSERF             0x00000002U    /*!< Clear the start error flag */
-#define MDIOS_CLRFR_CTERF             0x00000004U    /*!< Clear the turnaround error flag */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || \
-                                       ((__INSTANCE__) == ADC2) || \
-                                       ((__INSTANCE__) == ADC3))
-
-/******************************* CAN Instances ********************************/
-#define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) || \
-                                           ((__INSTANCE__) == CAN2) || \
-									       ((__INSTANCE__) == CAN3))
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)
-
-/******************************* DAC Instances ********************************/
-#define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC)
-
-/******************************* DCMI Instances *******************************/
-#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
-
-/****************************** DFSDM Instances *******************************/
-#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
-                                                ((INSTANCE) == DFSDM1_Filter1) || \
-                                                ((INSTANCE) == DFSDM1_Filter2) || \
-                                                ((INSTANCE) == DFSDM1_Filter3))
-
-#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
-                                                 ((INSTANCE) == DFSDM1_Channel1) || \
-                                                 ((INSTANCE) == DFSDM1_Channel2) || \
-                                                 ((INSTANCE) == DFSDM1_Channel3) || \
-                                                 ((INSTANCE) == DFSDM1_Channel4) || \
-                                                 ((INSTANCE) == DFSDM1_Channel5) || \
-                                                 ((INSTANCE) == DFSDM1_Channel6) || \
-                                                 ((INSTANCE) == DFSDM1_Channel7))
-
-/******************************* DMA2D Instances *******************************/
-#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
-
-/******************************** DMA Instances *******************************/
-#define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) || \
-                                              ((__INSTANCE__) == DMA1_Stream1) || \
-                                              ((__INSTANCE__) == DMA1_Stream2) || \
-                                              ((__INSTANCE__) == DMA1_Stream3) || \
-                                              ((__INSTANCE__) == DMA1_Stream4) || \
-                                              ((__INSTANCE__) == DMA1_Stream5) || \
-                                              ((__INSTANCE__) == DMA1_Stream6) || \
-                                              ((__INSTANCE__) == DMA1_Stream7) || \
-                                              ((__INSTANCE__) == DMA2_Stream0) || \
-                                              ((__INSTANCE__) == DMA2_Stream1) || \
-                                              ((__INSTANCE__) == DMA2_Stream2) || \
-                                              ((__INSTANCE__) == DMA2_Stream3) || \
-                                              ((__INSTANCE__) == DMA2_Stream4) || \
-                                              ((__INSTANCE__) == DMA2_Stream5) || \
-                                              ((__INSTANCE__) == DMA2_Stream6) || \
-                                              ((__INSTANCE__) == DMA2_Stream7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
-                                            ((__INSTANCE__) == GPIOB) || \
-                                            ((__INSTANCE__) == GPIOC) || \
-                                            ((__INSTANCE__) == GPIOD) || \
-                                            ((__INSTANCE__) == GPIOE) || \
-                                            ((__INSTANCE__) == GPIOF) || \
-                                            ((__INSTANCE__) == GPIOG) || \
-                                            ((__INSTANCE__) == GPIOH) || \
-                                            ((__INSTANCE__) == GPIOI) || \
-                                            ((__INSTANCE__) == GPIOJ) || \
-                                            ((__INSTANCE__) == GPIOK))
-
-#define IS_GPIO_AF_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == GPIOA) || \
-                                             ((__INSTANCE__) == GPIOB) || \
-                                             ((__INSTANCE__) == GPIOC) || \
-                                             ((__INSTANCE__) == GPIOD) || \
-                                             ((__INSTANCE__) == GPIOE) || \
-                                             ((__INSTANCE__) == GPIOF) || \
-                                             ((__INSTANCE__) == GPIOG) || \
-                                             ((__INSTANCE__) == GPIOH) || \
-                                             ((__INSTANCE__) == GPIOI) || \
-                                             ((__INSTANCE__) == GPIOJ) || \
-                                             ((__INSTANCE__) == GPIOK))
-
-/****************************** CEC Instances *********************************/
-#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
-
-/****************************** QSPI Instances *********************************/
-#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
-
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
-                                           ((__INSTANCE__) == I2C2) || \
-                                           ((__INSTANCE__) == I2C3) || \
-                                           ((__INSTANCE__) == I2C4))
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == SPI1) || \
-                                            ((__INSTANCE__) == SPI2) || \
-                                            ((__INSTANCE__) == SPI3))
-
-/******************************* LPTIM Instances ********************************/
-#define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
-
-/****************************** LTDC Instances ********************************/
-#define IS_LTDC_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == LTDC)
-
-/****************************** MDIOS Instances ********************************/
-#define IS_MDIOS_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == MDIOS)
-
-/****************************** MDIOS Instances ********************************/
-#define IS_JPEG_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == JPEG)
-
-
-/******************************* RNG Instances ********************************/
-#define IS_RNG_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == RNG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == RTC)
-
-/******************************* SAI Instances ********************************/
-#define IS_SAI_ALL_INSTANCE(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) || \
-                                         ((__PERIPH__) == SAI1_Block_B) || \
-                                         ((__PERIPH__) == SAI2_Block_A) || \
-                                         ((__PERIPH__) == SAI2_Block_B))
-/* Legacy define */
-#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
-
-/******************************** SDMMC Instances *******************************/
-#define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SDMMC1) || \
-                                             ((__INSTANCE__) == SDMMC2))
-
-/****************************** SPDIFRX Instances *********************************/
-#define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
-                                           ((__INSTANCE__) == SPI2) || \
-                                           ((__INSTANCE__) == SPI3) || \
-                                           ((__INSTANCE__) == SPI4) || \
-                                           ((__INSTANCE__) == SPI5) || \
-                                           ((__INSTANCE__) == SPI6))
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1)   || \
-                                   ((__INSTANCE__) == TIM2)   || \
-                                   ((__INSTANCE__) == TIM3)   || \
-                                   ((__INSTANCE__) == TIM4)   || \
-                                   ((__INSTANCE__) == TIM5)   || \
-                                   ((__INSTANCE__) == TIM6)   || \
-                                   ((__INSTANCE__) == TIM7)   || \
-                                   ((__INSTANCE__) == TIM8)   || \
-                                   ((__INSTANCE__) == TIM9)   || \
-                                   ((__INSTANCE__) == TIM10)  || \
-                                   ((__INSTANCE__) == TIM11)  || \
-                                   ((__INSTANCE__) == TIM12)  || \
-                                   ((__INSTANCE__) == TIM13)  || \
-                                   ((__INSTANCE__) == TIM14))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1)  || \
-                                         ((__INSTANCE__) == TIM2)  || \
-                                         ((__INSTANCE__) == TIM3)  || \
-                                         ((__INSTANCE__) == TIM4)  || \
-                                         ((__INSTANCE__) == TIM5)  || \
-                                         ((__INSTANCE__) == TIM8)  || \
-                                         ((__INSTANCE__) == TIM9)  || \
-                                         ((__INSTANCE__) == TIM10) || \
-                                         ((__INSTANCE__) == TIM11) || \
-                                         ((__INSTANCE__) == TIM12) || \
-                                         ((__INSTANCE__) == TIM13) || \
-                                         ((__INSTANCE__) == TIM14))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1)  || \
-                                         ((__INSTANCE__) == TIM2)  || \
-                                         ((__INSTANCE__) == TIM3)  || \
-                                         ((__INSTANCE__) == TIM4)  || \
-                                         ((__INSTANCE__) == TIM5)  || \
-                                         ((__INSTANCE__) == TIM8)  || \
-                                         ((__INSTANCE__) == TIM9)  || \
-                                         ((__INSTANCE__) == TIM12))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1) || \
-                                         ((__INSTANCE__) == TIM2) || \
-                                         ((__INSTANCE__) == TIM3) || \
-                                         ((__INSTANCE__) == TIM4) || \
-                                         ((__INSTANCE__) == TIM5) || \
-                                         ((__INSTANCE__) == TIM8))
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
-                                       ((__INSTANCE__) == TIM2) || \
-                                       ((__INSTANCE__) == TIM3) || \
-                                       ((__INSTANCE__) == TIM4) || \
-                                       ((__INSTANCE__) == TIM5) || \
-                                       ((__INSTANCE__) == TIM8))
-
-/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
-#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \
-                                       (((__INSTANCE__) == TIM1)    || \
-                                        ((__INSTANCE__) == TIM8))
-
-/****************** TIM Instances : supporting OCxREF clear *******************/
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\
-                                  (((__INSTANCE__) == TIM1)    || \
-                                   ((__INSTANCE__) == TIM2)    || \
-                                   ((__INSTANCE__) == TIM3)    || \
-                                   ((__INSTANCE__) == TIM4)    || \
-                                   ((__INSTANCE__) == TIM8))
-
-/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\
-                                                 (((__INSTANCE__) == TIM1)    || \
-                                                  ((__INSTANCE__) == TIM2)    || \
-                                                  ((__INSTANCE__) == TIM3)    || \
-                                                  ((__INSTANCE__) == TIM4)    || \
-                                                  ((__INSTANCE__) == TIM5)    || \
-                                                  ((__INSTANCE__) == TIM8))
-
-/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\
-                                                   (((__INSTANCE__) == TIM1)    || \
-                                                    ((__INSTANCE__) == TIM2)    || \
-                                                    ((__INSTANCE__) == TIM3)    || \
-                                                    ((__INSTANCE__) == TIM4)    || \
-                                                    ((__INSTANCE__) == TIM5)    || \
-                                                    ((__INSTANCE__) == TIM8))
-/****************** TIM Instances : at least 5 capture/compare channels *******/
-#define IS_TIM_CC5_INSTANCE(__INSTANCE__)\
-  (((__INSTANCE__) == TIM1)    || \
-   ((__INSTANCE__) == TIM8) )
-
-/****************** TIM Instances : at least 6 capture/compare channels *******/
-#define IS_TIM_CC6_INSTANCE(__INSTANCE__)\
-  (((__INSTANCE__) == TIM1)    || \
-   ((__INSTANCE__) == TIM8))
-
-
-/******************** TIM Instances : Advanced-control timers *****************/
-#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
-                                            ((__INSTANCE__) == TIM8))
-
-/****************** TIM Instances : supporting 2 break inputs *****************/
-#define IS_TIM_BREAK_INSTANCE(__INSTANCE__)\
-  (((__INSTANCE__) == TIM1)    || \
-   ((__INSTANCE__) == TIM8))
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1) || \
-                                         ((__INSTANCE__) == TIM2) || \
-                                         ((__INSTANCE__) == TIM3) || \
-                                         ((__INSTANCE__) == TIM4) || \
-                                         ((__INSTANCE__) == TIM5) || \
-                                         ((__INSTANCE__) == TIM8))
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
-                                       ((__INSTANCE__) == TIM2) || \
-                                       ((__INSTANCE__) == TIM3) || \
-                                       ((__INSTANCE__) == TIM4) || \
-                                       ((__INSTANCE__) == TIM5) || \
-                                       ((__INSTANCE__) == TIM6) || \
-                                       ((__INSTANCE__) == TIM7) || \
-                                       ((__INSTANCE__) == TIM8))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
-                                          ((__INSTANCE__) == TIM2) || \
-                                          ((__INSTANCE__) == TIM3) || \
-                                          ((__INSTANCE__) == TIM4) || \
-                                          ((__INSTANCE__) == TIM5) || \
-                                          ((__INSTANCE__) == TIM8))
-
-/************ TIM Instances : DMA requests generation (COMDE) *****************/
-#define IS_TIM_CCDMA_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1) || \
-                                          ((__INSTANCE__) == TIM2) || \
-                                          ((__INSTANCE__) == TIM3) || \
-                                          ((__INSTANCE__) == TIM4) || \
-                                          ((__INSTANCE__) == TIM5) || \
-                                          ((__INSTANCE__) == TIM8))
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1) || \
-                                             ((__INSTANCE__) == TIM2) || \
-                                             ((__INSTANCE__) == TIM3) || \
-                                             ((__INSTANCE__) == TIM4) || \
-                                             ((__INSTANCE__) == TIM5) || \
-                                             ((__INSTANCE__) == TIM8))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
-                                          ((__INSTANCE__) == TIM2) || \
-                                          ((__INSTANCE__) == TIM3) || \
-                                          ((__INSTANCE__) == TIM4) || \
-                                          ((__INSTANCE__) == TIM5) || \
-                                          ((__INSTANCE__) == TIM6) || \
-                                          ((__INSTANCE__) == TIM7) || \
-                                          ((__INSTANCE__) == TIM8) || \
-                                          ((__INSTANCE__) == TIM13) || \
-                                          ((__INSTANCE__) == TIM14))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
-                                         ((__INSTANCE__) == TIM2) || \
-                                         ((__INSTANCE__) == TIM3) || \
-                                         ((__INSTANCE__) == TIM4) || \
-                                         ((__INSTANCE__) == TIM5) || \
-                                         ((__INSTANCE__) == TIM8) || \
-                                         ((__INSTANCE__) == TIM9) || \
-                                         ((__INSTANCE__) == TIM12))
-
-/********************** TIM Instances : 32 bit Counter ************************/
-#define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__)(((__INSTANCE__) == TIM2) || \
-                                              ((__INSTANCE__) == TIM5))
-
-/***************** TIM Instances : external trigger input available ************/
-#define IS_TIM_ETR_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1) || \
-                                        ((__INSTANCE__) == TIM2) || \
-                                        ((__INSTANCE__) == TIM3) || \
-                                        ((__INSTANCE__) == TIM4) || \
-                                        ((__INSTANCE__) == TIM5) || \
-                                        ((__INSTANCE__) == TIM8))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2)  || \
-                                         ((__INSTANCE__) == TIM5)  || \
-                                         ((__INSTANCE__) == TIM11))
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \
-    ((((__INSTANCE__) == TIM1) &&                  \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM2) &&                   \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM3) &&                   \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM4) &&                   \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM5) &&                   \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM8) &&                   \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM9) &&                   \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM10) &&                  \
-     (((__CHANNEL__) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM11) &&                  \
-     (((__CHANNEL__) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM12) &&                  \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM13) &&                  \
-     (((__CHANNEL__) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM14) &&                  \
-     (((__CHANNEL__) == TIM_CHANNEL_1))))
-
-/************ TIM Instances : complementary output(s) available ***************/
-#define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \
-   ((((__INSTANCE__) == TIM1) &&                    \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||           \
-      ((__CHANNEL__) == TIM_CHANNEL_2) ||           \
-      ((__CHANNEL__) == TIM_CHANNEL_3)))            \
-    ||                                          \
-    (((__INSTANCE__) == TIM8) &&                    \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||           \
-      ((__CHANNEL__) == TIM_CHANNEL_2) ||           \
-      ((__CHANNEL__) == TIM_CHANNEL_3))))
-
-/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
-#define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\
-  (((__INSTANCE__) == TIM1)    || \
-   ((__INSTANCE__) == TIM8) )
-
-/****************** TIM Instances : supporting synchronization ****************/
-#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
-    (((__INSTANCE__) == TIM1)    || \
-     ((__INSTANCE__) == TIM2)    || \
-     ((__INSTANCE__) == TIM3)    || \
-     ((__INSTANCE__) == TIM4)    || \
-     ((__INSTANCE__) == TIM5)    || \
-     ((__INSTANCE__) == TIM6)    || \
-     ((__INSTANCE__) == TIM7)    || \
-     ((__INSTANCE__) == TIM8))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
-                                     ((__INSTANCE__) == USART2) || \
-                                     ((__INSTANCE__) == USART3) || \
-                                     ((__INSTANCE__) == USART6))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
-                                    ((__INSTANCE__) == USART2) || \
-                                    ((__INSTANCE__) == USART3) || \
-                                    ((__INSTANCE__) == UART4)  || \
-                                    ((__INSTANCE__) == UART5)  || \
-                                    ((__INSTANCE__) == USART6) || \
-                                    ((__INSTANCE__) == UART7)  || \
-                                    ((__INSTANCE__) == UART8))
-
-/****************** UART Instances : Driver Enable *****************/
-#define IS_UART_DRIVER_ENABLE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
-                                    ((__INSTANCE__) == USART2) || \
-                                    ((__INSTANCE__) == USART3) || \
-                                    ((__INSTANCE__) == UART4)  || \
-                                    ((__INSTANCE__) == UART5)  || \
-                                    ((__INSTANCE__) == USART6) || \
-                                    ((__INSTANCE__) == UART7)  || \
-                                    ((__INSTANCE__) == UART8))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
-                                    ((__INSTANCE__) == USART2) || \
-                                    ((__INSTANCE__) == USART3) || \
-                                    ((__INSTANCE__) == UART4)  || \
-                                    ((__INSTANCE__) == UART5)  || \
-                                    ((__INSTANCE__) == USART6) || \
-                                    ((__INSTANCE__) == UART7)  || \
-                                    ((__INSTANCE__) == UART8))
-
-/********************* UART Instances : Smart card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
-                                         ((__INSTANCE__) == USART2) || \
-                                         ((__INSTANCE__) == USART3) || \
-                                         ((__INSTANCE__) == USART6))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
-                                    ((__INSTANCE__) == USART2) || \
-                                    ((__INSTANCE__) == USART3) || \
-                                    ((__INSTANCE__) == UART4)  || \
-                                    ((__INSTANCE__) == UART5)  || \
-                                    ((__INSTANCE__) == USART6) || \
-                                    ((__INSTANCE__) == UART7)  || \
-                                    ((__INSTANCE__) == UART8))
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == WWDG)
-
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32F7xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */
-/*  product lines within the same STM32F7 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-#define HASH_RNG_IRQn              RNG_IRQn
-
-/* Aliases for __IRQHandler */
-#define HASH_RNG_IRQHandler        RNG_IRQHandler
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32F767xx_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/cmsis/stm32f769xx.h b/stmhal/cmsis/stm32f769xx.h
deleted file mode 100644
index 7e6321a6f9..0000000000
--- a/stmhal/cmsis/stm32f769xx.h
+++ /dev/null
@@ -1,11333 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f769xx.h
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016 
-  * @brief   CMSIS Cortex-M7 Device Peripheral Access Layer Header File.
-  *
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral's registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS_Device
-  * @{
-  */
-
-/** @addtogroup stm32f769xx
-  * @{
-  */
-    
-#ifndef __STM32F769xx_H
-#define __STM32F769xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-  
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-
-/**
- * @brief STM32F7xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-typedef enum
-{
-/******  Cortex-M7 Processor Exceptions Numbers ****************************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M7 Memory Management Interrupt                           */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M7 Bus Fault Interrupt                                   */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M7 Usage Fault Interrupt                                 */
-  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M7 SV Call Interrupt                                    */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M7 Debug Monitor Interrupt                              */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M7 Pend SV Interrupt                                    */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M7 System Tick Interrupt                                */
-/******  STM32 specific Interrupt Numbers **********************************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
-  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
-  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
-  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
-  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
-  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
-  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
-  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
-  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
-  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
-  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
-  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
-  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
-  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
-  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
-  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
-  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
-  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */    
-  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
-  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
-  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
-  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
-  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
-  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
-  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
-  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
-  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
-  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
-  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
-  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
-  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
-  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
-  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
-  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
-  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
-  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
-  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
-  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
-  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
-  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
-  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
-  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
-  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
-  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
-  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
-  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
-  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
-  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
-  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
-  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
-  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
-  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
-  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
-  RNG_IRQn                    = 80,     /*!< RNG global interrupt                                              */
-  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
-  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */
-  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */
-  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
-  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */
-  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */
-  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
-  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                             */
-  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                       */
-  DMA2D_IRQn                  = 90,     /*!< DMA2D global Interrupt                                            */
-  SAI2_IRQn                   = 91,     /*!< SAI2 global Interrupt                                             */
-  QUADSPI_IRQn                = 92,     /*!< Quad SPI global interrupt                                         */
-  LPTIM1_IRQn                 = 93,     /*!< LP TIM1 interrupt                                                 */
-  CEC_IRQn                    = 94,     /*!< HDMI-CEC global Interrupt                                         */
-  I2C4_EV_IRQn                = 95,     /*!< I2C4 Event Interrupt                                              */
-  I2C4_ER_IRQn                = 96,     /*!< I2C4 Error Interrupt                                              */
-  SPDIF_RX_IRQn               = 97,     /*!< SPDIF-RX global Interrupt                                         */
-  DSI_IRQn                    = 98,     /*!< DSI global Interrupt                                              */
-  DFSDM1_FLT0_IRQn	          = 99,     /*!< DFSDM1 Filter 0 global Interrupt                                  */
-  DFSDM1_FLT1_IRQn	          = 100,    /*!< DFSDM1 Filter 1 global Interrupt                                  */
-  DFSDM1_FLT2_IRQn	          = 101,    /*!< DFSDM1 Filter 2 global Interrupt                                  */
-  DFSDM1_FLT3_IRQn	          = 102,    /*!< DFSDM1 Filter 3 global Interrupt                                  */
-  SDMMC2_IRQn                 = 103,    /*!< SDMMC2 global Interrupt                                           */
-  CAN3_TX_IRQn                = 104,    /*!< CAN3 TX Interrupt                                                 */
-  CAN3_RX0_IRQn               = 105,    /*!< CAN3 RX0 Interrupt                                                */
-  CAN3_RX1_IRQn               = 106,    /*!< CAN3 RX1 Interrupt                                                */
-  CAN3_SCE_IRQn               = 107,    /*!< CAN3 SCE Interrupt                                                */
-  JPEG_IRQn                   = 108,    /*!< JPEG global Interrupt                                             */
-  MDIOS_IRQn                  = 109     /*!< MDIO Slave global Interrupt                                       */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-/**
- * @brief Configuration of the Cortex-M7 Processor and Core Peripherals 
- */
-#define __CM7_REV                 0x0100U  /*!< Cortex-M7 revision r1p0                       */
-#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */
-#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */
-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1       /*!< FPU present                                   */
-#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */
-#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */
-#include "core_cm7.h"                     /*!< Cortex-M7 processor and core peripherals      */
-  
-  
-#include "system_stm32f7xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */      
-  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
-  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
-  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
-  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
-  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
-  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
-  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
-  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
-  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
-  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
-  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
-  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
-  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
-  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
-  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
-                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
-} ADC_Common_TypeDef;
-
-
-/** 
-  * @brief Controller Area Network TxMailBox 
-  */
-
-typedef struct
-{
-  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
-  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
-  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
-  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
-} CAN_TxMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FIFOMailBox 
-  */
-  
-typedef struct
-{
-  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
-  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
-  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
-  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
-} CAN_FIFOMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FilterRegister 
-  */
-  
-typedef struct
-{
-  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
-  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
-} CAN_FilterRegister_TypeDef;
-
-/** 
-  * @brief Controller Area Network 
-  */
-  
-typedef struct
-{
-  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
-  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
-  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
-  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
-  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
-  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
-  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
-  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
-  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
-  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
-  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
-  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
-  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
-  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
-  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
-  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
-  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
-  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
-  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
-  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
-  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */ 
-  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
-} CAN_TypeDef;
-
-/** 
-  * @brief HDMI-CEC 
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< CEC control register,                                       Address offset:0x00 */
-  __IO uint32_t CFGR;         /*!< CEC configuration register,                                 Address offset:0x04 */
-  __IO uint32_t TXDR;         /*!< CEC Tx data register ,                                      Address offset:0x08 */
-  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,                                       Address offset:0x0C */
-  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register,                          Address offset:0x10 */
-  __IO uint32_t IER;          /*!< CEC interrupt enable register,                              Address offset:0x14 */
-}CEC_TypeDef;
-
-/** 
-  * @brief CRC calculation unit 
-  */
-
-typedef struct
-{
-  __IO uint32_t  DR;          /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint8_t   IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
-  uint8_t        RESERVED0;   /*!< Reserved, 0x05                                                    */
-  uint16_t       RESERVED1;   /*!< Reserved, 0x06                                                    */
-  __IO uint32_t  CR;          /*!< CRC Control register,                        Address offset: 0x08 */
-  uint32_t       RESERVED2;   /*!< Reserved,                                                    0x0C */
-  __IO uint32_t  INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
-  __IO uint32_t  POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
-  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
-  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
-  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
-  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
-  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
-  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
-  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
-  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
-  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
-  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
-  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
-  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
-} DAC_TypeDef;
-
-/**
-  * @brief DFSDM module registers
-  */
-typedef struct
-{
-  __IO uint32_t FLTCR1;         /*!< DFSDM control register1,                          Address offset: 0x100 */
-  __IO uint32_t FLTCR2;         /*!< DFSDM control register2,                          Address offset: 0x104 */
-  __IO uint32_t FLTISR;         /*!< DFSDM interrupt and status register,              Address offset: 0x108 */
-  __IO uint32_t FLTICR;         /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */
-  __IO uint32_t FLTJCHGR;       /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */
-  __IO uint32_t FLTFCR;         /*!< DFSDM filter control register,                    Address offset: 0x114 */
-  __IO uint32_t FLTJDATAR;      /*!< DFSDM data register for injected group,           Address offset: 0x118 */
-  __IO uint32_t FLTRDATAR;      /*!< DFSDM data register for regular group,            Address offset: 0x11C */
-  __IO uint32_t FLTAWHTR;       /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */
-  __IO uint32_t FLTAWLTR;       /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */
-  __IO uint32_t FLTAWSR;        /*!< DFSDM analog watchdog status register             Address offset: 0x128 */
-  __IO uint32_t FLTAWCFR;       /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */
-  __IO uint32_t FLTEXMAX;       /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */
-  __IO uint32_t FLTEXMIN;       /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */
-  __IO uint32_t FLTCNVTIMR;     /*!< DFSDM conversion timer,                           Address offset: 0x138 */
-} DFSDM_Filter_TypeDef;
-
-/**
-  * @brief DFSDM channel configuration registers
-  */
-typedef struct
-{
-  __IO uint32_t CHCFGR1;     /*!< DFSDM channel configuration register1,            Address offset: 0x00 */
-  __IO uint32_t CHCFGR2;     /*!< DFSDM channel configuration register2,            Address offset: 0x04 */
-  __IO uint32_t CHAWSCDR;    /*!< DFSDM channel analog watchdog and
-                                  short circuit detector register,                  Address offset: 0x08 */
-  __IO uint32_t CHWDATAR;    /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */
-  __IO uint32_t CHDATINR;    /*!< DFSDM channel data input register,                Address offset: 0x10 */
-} DFSDM_Channel_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
-  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
-  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
-  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DCMI
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
-  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
-  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
-  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
-  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
-  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
-  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
-  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
-  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
-  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
-  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
-} DCMI_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
-  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
-  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
-  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
-  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
-  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
-} DMA_Stream_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
-  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
-  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
-  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
-} DMA_TypeDef;
-
-/** 
-  * @brief DMA2D Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
-  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
-  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
-  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
-  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
-  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
-  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
-  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
-  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
-  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
-  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
-  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
-  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
-  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
-  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
-  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
-  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
-  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
-  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
-  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
-  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
-  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */
-  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */
-} DMA2D_TypeDef;
-
-
-/** 
-  * @brief Ethernet MAC
-  */
-
-typedef struct
-{
-  __IO uint32_t MACCR;
-  __IO uint32_t MACFFR;
-  __IO uint32_t MACHTHR;
-  __IO uint32_t MACHTLR;
-  __IO uint32_t MACMIIAR;
-  __IO uint32_t MACMIIDR;
-  __IO uint32_t MACFCR;
-  __IO uint32_t MACVLANTR;             /*    8 */
-  uint32_t      RESERVED0[2];
-  __IO uint32_t MACRWUFFR;             /*   11 */
-  __IO uint32_t MACPMTCSR;
-  uint32_t      RESERVED1[2];
-  __IO uint32_t MACSR;                 /*   15 */
-  __IO uint32_t MACIMR;
-  __IO uint32_t MACA0HR;
-  __IO uint32_t MACA0LR;
-  __IO uint32_t MACA1HR;
-  __IO uint32_t MACA1LR;
-  __IO uint32_t MACA2HR;
-  __IO uint32_t MACA2LR;
-  __IO uint32_t MACA3HR;
-  __IO uint32_t MACA3LR;               /*   24 */
-  uint32_t      RESERVED2[40];
-  __IO uint32_t MMCCR;                 /*   65 */
-  __IO uint32_t MMCRIR;
-  __IO uint32_t MMCTIR;
-  __IO uint32_t MMCRIMR;
-  __IO uint32_t MMCTIMR;               /*   69 */
-  uint32_t      RESERVED3[14];
-  __IO uint32_t MMCTGFSCCR;            /*   84 */
-  __IO uint32_t MMCTGFMSCCR;
-  uint32_t      RESERVED4[5];
-  __IO uint32_t MMCTGFCR;
-  uint32_t      RESERVED5[10];
-  __IO uint32_t MMCRFCECR;
-  __IO uint32_t MMCRFAECR;
-  uint32_t      RESERVED6[10];
-  __IO uint32_t MMCRGUFCR;
-  uint32_t      RESERVED7[334];
-  __IO uint32_t PTPTSCR;
-  __IO uint32_t PTPSSIR;
-  __IO uint32_t PTPTSHR;
-  __IO uint32_t PTPTSLR;
-  __IO uint32_t PTPTSHUR;
-  __IO uint32_t PTPTSLUR;
-  __IO uint32_t PTPTSAR;
-  __IO uint32_t PTPTTHR;
-  __IO uint32_t PTPTTLR;
-  __IO uint32_t RESERVED8;
-  __IO uint32_t PTPTSSR;
-  uint32_t      RESERVED9[565];
-  __IO uint32_t DMABMR;
-  __IO uint32_t DMATPDR;
-  __IO uint32_t DMARPDR;
-  __IO uint32_t DMARDLAR;
-  __IO uint32_t DMATDLAR;
-  __IO uint32_t DMASR;
-  __IO uint32_t DMAOMR;
-  __IO uint32_t DMAIER;
-  __IO uint32_t DMAMFBOCR;
-  __IO uint32_t DMARSWTR;
-  uint32_t      RESERVED10[8];
-  __IO uint32_t DMACHTDR;
-  __IO uint32_t DMACHRDR;
-  __IO uint32_t DMACHTBAR;
-  __IO uint32_t DMACHRBAR;
-} ETH_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
-  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
-  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
-  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
-  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
-  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-
-typedef struct
-{
-  __IO uint32_t ACR;      /*!< FLASH access control register,     Address offset: 0x00 */
-  __IO uint32_t KEYR;     /*!< FLASH key register,                Address offset: 0x04 */
-  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,         Address offset: 0x08 */
-  __IO uint32_t SR;       /*!< FLASH status register,             Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< FLASH control register,            Address offset: 0x10 */
-  __IO uint32_t OPTCR;    /*!< FLASH option control register ,    Address offset: 0x14 */
-  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1 ,  Address offset: 0x18 */
-} FLASH_TypeDef;
-
-
-
-/** 
-  * @brief Flexible Memory Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */   
-} FMC_Bank1_TypeDef; 
-
-/** 
-  * @brief Flexible Memory Controller Bank1E
-  */
-  
-typedef struct
-{
-  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
-} FMC_Bank1E_TypeDef;
-
-/** 
-  * @brief Flexible Memory Controller Bank3
-  */
-  
-typedef struct
-{
-  __IO uint32_t PCR;        /*!< NAND Flash control register,                       Address offset: 0x80 */
-  __IO uint32_t SR;         /*!< NAND Flash FIFO status and interrupt register,     Address offset: 0x84 */
-  __IO uint32_t PMEM;       /*!< NAND Flash Common memory space timing register,    Address offset: 0x88 */
-  __IO uint32_t PATT;       /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
-  uint32_t      RESERVED0;  /*!< Reserved, 0x90                                                          */
-  __IO uint32_t ECCR;       /*!< NAND Flash ECC result registers,                   Address offset: 0x94 */
-} FMC_Bank3_TypeDef;
- 
-/** 
-  * @brief Flexible Memory Controller Bank5_6
-  */
-  
-typedef struct
-{
-  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */
-  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */
-  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */
-  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */
-  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */
-} FMC_Bank5_6_TypeDef; 
-
-
-/** 
-  * @brief General Purpose I/O
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
-  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
-  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
-  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
-  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
-  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
-  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
-  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/** 
-  * @brief System configuration controller
-  */
-  
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-  uint32_t      RESERVED;     /*!< Reserved, 0x18                                                               */
-  __IO uint32_t CBR;          /*!< SYSCFG Class B register,                           Address offset: 0x1C      */
-  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */  
-  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */  
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
-} IWDG_TypeDef;
-
-
-/** 
-  * @brief LCD-TFT Display Controller
-  */
-  
-typedef struct
-{
-  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04 */
-  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */
-  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */
-  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */
-  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */
-  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */
-  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20 */
-  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */
-  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28 */
-  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */
-  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30 */
-  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */
-  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */
-  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */
-  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
-  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */
-  __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                 Address offset: 0x48 */
-} LTDC_TypeDef;  
-
-/** 
-  * @brief LCD-TFT Display layer x Controller
-  */
-  
-typedef struct
-{  
-  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */
-  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
-  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */
-  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */
-  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */
-  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */
-  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */
-  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */
-  uint32_t      RESERVED0[2];  /*!< Reserved */
-  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */
-  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */
-  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */
-  uint32_t      RESERVED1[3];  /*!< Reserved */
-  __IO uint32_t CLUTWR;        /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */
-
-} LTDC_Layer_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;   /*!< PWR power control register 1,        Address offset: 0x00 */
-  __IO uint32_t CSR1;  /*!< PWR power control/status register 2, Address offset: 0x04 */
-  __IO uint32_t CR2;   /*!< PWR power control register 2,        Address offset: 0x08 */
-  __IO uint32_t CSR2;  /*!< PWR power control/status register 2, Address offset: 0x0C */
-} PWR_TypeDef;
-
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
-  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
-  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
-  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
-  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
-  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
-  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
-  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
-  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
-  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
-  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
-  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
-  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
-  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
-  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
-  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
-  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
-  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
-  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
-  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
-  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
-  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
-  __IO uint32_t PLLSAICFGR;    /*!< RCC PLLSAI configuration register,                           Address offset: 0x88 */
-  __IO uint32_t DCKCFGR1;      /*!< RCC Dedicated Clocks configuration register1,                 Address offset: 0x8C */
-  __IO uint32_t DCKCFGR2;      /*!< RCC Dedicated Clocks configuration register 2,               Address offset: 0x90 */
-
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */                                                                                            
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-       uint32_t reserved;   /*!< Reserved  */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
-  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset: 0x4C */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
-  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
-  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
-  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
-  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
-  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
-  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
-  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
-  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
-  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
-  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
-  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
-  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
-  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
-  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
-  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */
-  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */
-  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */
-  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */
-  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */
-  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */
-  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */
-  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */
-  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */
-  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */
-  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */
-  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */
-} RTC_TypeDef;
-
-
-/** 
-  * @brief Serial Audio Interface
-  */
-  
-typedef struct
-{
-  __IO uint32_t GCR;      /*!< SAI global configuration register,        Address offset: 0x00 */
-} SAI_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */
-  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */
-  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */
-  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */
-  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
-  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */
-  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */
-  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */
-} SAI_Block_TypeDef;
-
-/** 
-  * @brief SPDIF-RX Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t   CR;           /*!< Control register,                   Address offset: 0x00 */
-  __IO uint32_t   IMR;          /*!< Interrupt mask register,            Address offset: 0x04 */  
-  __IO uint32_t   SR;           /*!< Status register,                    Address offset: 0x08 */
-  __IO uint32_t   IFCR;         /*!< Interrupt Flag Clear register,      Address offset: 0x0C */ 
-  __IO uint32_t   DR;           /*!< Data input register,                Address offset: 0x10 */
-  __IO uint32_t   CSR;          /*!< Channel Status register,            Address offset: 0x14 */
-  __IO uint32_t   DIR;          /*!< Debug Information register,         Address offset: 0x18 */
-} SPDIFRX_TypeDef;
-
-/** 
-  * @brief SD host Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t POWER;          /*!< SDMMC power control register,    Address offset: 0x00 */
-  __IO uint32_t CLKCR;          /*!< SDMMClock control register,     Address offset: 0x04 */
-  __IO uint32_t ARG;            /*!< SDMMC argument register,         Address offset: 0x08 */
-  __IO uint32_t CMD;            /*!< SDMMC command register,          Address offset: 0x0C */
-  __I uint32_t  RESPCMD;        /*!< SDMMC command response register, Address offset: 0x10 */
-  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,       Address offset: 0x14 */
-  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,       Address offset: 0x18 */
-  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,       Address offset: 0x1C */
-  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,       Address offset: 0x20 */
-  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,       Address offset: 0x24 */
-  __IO uint32_t DLEN;           /*!< SDMMC data length register,      Address offset: 0x28 */
-  __IO uint32_t DCTRL;          /*!< SDMMC data control register,     Address offset: 0x2C */
-  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,     Address offset: 0x30 */
-  __I uint32_t  STA;            /*!< SDMMC status register,           Address offset: 0x34 */
-  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,  Address offset: 0x38 */
-  __IO uint32_t MASK;           /*!< SDMMC mask register,             Address offset: 0x3C */
-  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
-  __I uint32_t  FIFOCNT;        /*!< SDMMC FIFO counter register,     Address offset: 0x48 */
-  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
-  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,        Address offset: 0x80 */
-} SDMMC_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief QUAD Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */
-  __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
-  __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */
-  __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
-  __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
-  __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
-  __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */
-  __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
-  __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */
-  __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
-  __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */                  
-  __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
-  __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */    
-} QUADSPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
-  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
-  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
-  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
-  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */
-  __IO uint32_t CCR5;        /*!< TIM capture/compare mode register5,       Address offset: 0x58 */
-  __IO uint32_t CCR6;        /*!< TIM capture/compare mode register6,       Address offset: 0x5C */
-  __IO uint32_t AF1;         /*!< TIM Alternate function option register 1, Address offset: 0x60 */
-  __IO uint32_t AF2;         /*!< TIM Alternate function option register 2, Address offset: 0x64 */
-
-} TIM_TypeDef;
-
-/** 
-  * @brief LPTIMIMER
-  */
-typedef struct
-{
-  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */
-  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */
-  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */
-  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                       Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< LPTIM Control register,                             Address offset: 0x10 */
-  __IO uint32_t CMP;      /*!< LPTIM Compare register,                             Address offset: 0x14 */
-  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
-  __IO uint32_t CNT;      /*!< LPTIM Counter register,                             Address offset: 0x1C */
-} LPTIM_TypeDef;
-
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */ 
-  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */ 
-  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
-  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */                                               
-  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
-  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */  
-  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
-  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
-  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
-  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
-  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
-} USART_TypeDef;
-
-
-/** 
-  * @brief Window WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-
-/** 
-  * @brief RNG
-  */
-  
-typedef struct 
-{
-  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
-  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
-  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
-} RNG_TypeDef;
-
-/**
-  * @}
-  */
-
-/** 
-  * @brief USB_OTG_Core_Registers
-  */
-typedef struct
-{
- __IO uint32_t GOTGCTL;               /*!< USB_OTG Control and Status Register          000h */
-  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */
-  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */
-  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */
-  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */
-  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */
-  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */
-  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */
-  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */
-  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */
-  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */
-  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */
-  uint32_t Reserved30[2];             /*!< Reserved                                     030h */
-  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */
-  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */
-  uint32_t  Reserved5[3];             /*!< Reserved                                040h-048h */
-  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */
-  uint32_t  Reserved6;                /*!< Reserved                                     050h */ 
-  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */
-  __IO uint32_t GPWRDN;               /*!< Power Down Register                          058h */
-  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */
-   __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register       60Ch */
-    uint32_t  Reserved43[39];         /*!< Reserved                                058h-0FFh */
-  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */
-  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */
-} USB_OTG_GlobalTypeDef;
-
-
-/** 
-  * @brief USB_OTG_device_Registers
-  */
-typedef struct 
-{
-  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */
-  __IO uint32_t DCTL;            /*!< dev Control Register         804h */
-  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */
-  uint32_t Reserved0C;           /*!< Reserved                     80Ch */
-  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */
-  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */
-  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */
-  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */
-  uint32_t  Reserved20;          /*!< Reserved                     820h */
-  uint32_t Reserved9;            /*!< Reserved                     824h */
-  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */
-  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */
-  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */
-  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */
-  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */
-  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */  
-  uint32_t Reserved40;           /*!< dedicated EP mask            840h */
-  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */
-  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */
-  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */   
-} USB_OTG_DeviceTypeDef;
-
-
-/** 
-  * @brief USB_OTG_IN_Endpoint-Specific_Register
-  */
-typedef struct 
-{
-  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */
-  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */
-  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */
-  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */
-  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */
-  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */
-  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
-  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
-} USB_OTG_INEndpointTypeDef;
-
-
-/** 
-  * @brief USB_OTG_OUT_Endpoint-Specific_Registers
-  */
-typedef struct 
-{
-  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */
-  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */
-  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */
-  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */
-  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */
-  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */
-  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
-} USB_OTG_OUTEndpointTypeDef;
-
-
-/** 
-  * @brief USB_OTG_Host_Mode_Register_Structures
-  */
-typedef struct 
-{
-  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */
-  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */
-  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */
-  uint32_t Reserved40C;           /*!< Reserved                             40Ch */
-  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */
-  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */
-  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */
-} USB_OTG_HostTypeDef;
-
-/** 
-  * @brief USB_OTG_Host_Channel_Specific_Registers
-  */
-typedef struct
-{
-  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */
-  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */
-  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */
-  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */
-  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */
-  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */
-  uint32_t Reserved[2];           /*!< Reserved                                      */
-} USB_OTG_HostChannelTypeDef;
-/**
-  * @}
-  */
-
-/**
-  * @brief JPEG Codec
-  */
-typedef struct
-{
-  __IO uint32_t CONFR0;          /*!< JPEG Codec Control Register (JPEG_CONFR0),        Address offset: 00h       */
-  __IO uint32_t CONFR1;          /*!< JPEG Codec Control Register (JPEG_CONFR1),        Address offset: 04h       */
-  __IO uint32_t CONFR2;          /*!< JPEG Codec Control Register (JPEG_CONFR2),        Address offset: 08h       */
-  __IO uint32_t CONFR3;          /*!< JPEG Codec Control Register (JPEG_CONFR3),        Address offset: 0Ch       */ 
-  __IO uint32_t CONFR4;          /*!< JPEG Codec Control Register (JPEG_CONFR4),        Address offset: 10h       */ 
-  __IO uint32_t CONFR5;          /*!< JPEG Codec Control Register (JPEG_CONFR5),        Address offset: 14h       */ 
-  __IO uint32_t CONFR6;          /*!< JPEG Codec Control Register (JPEG_CONFR6),        Address offset: 18h       */ 
-  __IO uint32_t CONFR7;          /*!< JPEG Codec Control Register (JPEG_CONFR7),        Address offset: 1Ch       */
-  uint32_t  Reserved20[4];       /* Reserved                                            Address offset: 20h-2Ch   */
-  __IO uint32_t CR;              /*!< JPEG Control Register (JPEG_CR),                  Address offset: 30h       */ 
-  __IO uint32_t SR;              /*!< JPEG Status Register (JPEG_SR),                   Address offset: 34h       */ 
-  __IO uint32_t CFR;             /*!< JPEG Clear Flag Register (JPEG_CFR),              Address offset: 38h       */ 
-  uint32_t  Reserved3c;          /* Reserved                                            Address offset: 3Ch       */
-  __IO uint32_t DIR;             /*!< JPEG Data Input Register (JPEG_DIR),              Address offset: 40h       */
-  __IO uint32_t DOR;             /*!< JPEG Data Output Register (JPEG_DOR),             Address offset: 44h       */
-  uint32_t  Reserved48[2];       /* Reserved                                            Address offset: 48h-4Ch   */
-  __IO uint32_t QMEM0[16];       /*!< JPEG quantization tables 0,                       Address offset: 50h-8Ch   */
-  __IO uint32_t QMEM1[16];       /*!< JPEG quantization tables 1,                       Address offset: 90h-CCh   */
-  __IO uint32_t QMEM2[16];       /*!< JPEG quantization tables 2,                       Address offset: D0h-10Ch  */
-  __IO uint32_t QMEM3[16];       /*!< JPEG quantization tables 3,                       Address offset: 110h-14Ch */
-  __IO uint32_t HUFFMIN[16];     /*!< JPEG HuffMin tables,                              Address offset: 150h-18Ch */
-  __IO uint32_t HUFFBASE[32];    /*!< JPEG HuffSymb tables,                             Address offset: 190h-20Ch */
-  __IO uint32_t HUFFSYMB[84];    /*!< JPEG HUFFSYMB tables,                             Address offset: 210h-35Ch */
-  __IO uint32_t DHTMEM[103];     /*!< JPEG DHTMem tables,                               Address offset: 360h-4F8h */
-  uint32_t  Reserved4FC;         /* Reserved                                            Address offset: 4FCh      */
-  __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encoder, AC Huffman table 0,                 Address offset: 500h-65Ch */
-  __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encoder, AC Huffman table 1,                 Address offset: 660h-7BCh */
-  __IO uint32_t HUFFENC_DC0[8];  /*!< JPEG encoder, DC Huffman table 0,                 Address offset: 7C0h-7DCh */
-  __IO uint32_t HUFFENC_DC1[8];  /*!< JPEG encoder, DC Huffman table 1,                 Address offset: 7E0h-7FCh */
-
-} JPEG_TypeDef;
-
-/**
-  * @brief MDIOS
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;               /*!< MDIOS Configuration Register (MDIOS_CR),        Address offset: 00h       */
-  __IO uint32_t WRFR;             /*!< MDIOS Configuration Register (MDIOS_CR),        Address offset: 04h       */
-  __IO uint32_t CWRFR;            /*!< MDIOS Configuration Register (MDIOS_CR),        Address offset: 08h       */
-  __IO uint32_t RDFR;             /*!< MDIOS Configuration Register (MDIOS_CR),        Address offset: 0Ch       */ 
-  __IO uint32_t CRDFR;            /*!< MDIOS Configuration Register (MDIOS_CR),        Address offset: 10h       */   
-  __IO uint32_t SR;               /*!< MDIOS Configuration Register (MDIOS_CR),        Address offset: 14h       */
-  __IO uint32_t CLRFR;            /*!< MDIOS Configuration Register (MDIOS_CR),        Address offset: 18h       */   	
-  uint32_t RESERVED0[57];         /* Reserved                                          Address offset: 1Ch       */	
-  __IO uint32_t DINR0;            /*!< MDIOS Input Data Register (MDIOS_DINR0),        Address offset: 100h      */    
-  __IO uint32_t DINR1;            /*!< MDIOS Input Data Register (MDIOS_DINR1),        Address offset: 104h      */     
-  __IO uint32_t DINR2;            /*!< MDIOS Input Data Register (MDIOS_DINR2),        Address offset: 108h      */    
-  __IO uint32_t DINR3;            /*!< MDIOS Input Data Register (MDIOS_DINR3),        Address offset: 10Ch      */     
-  __IO uint32_t DINR4;            /*!< MDIOS Input Data Register (MDIOS_DINR4),        Address offset: 110h      */     
-  __IO uint32_t DINR5;            /*!< MDIOS Input Data Register (MDIOS_DINR5),        Address offset: 114h      */     
-  __IO uint32_t DINR6;            /*!< MDIOS Input Data Register (MDIOS_DINR6),        Address offset: 118h      */  
-  __IO uint32_t DINR7;            /*!< MDIOS Input Data Register (MDIOS_DINR7),        Address offset: 11Ch      */ 
-  __IO uint32_t DINR8;            /*!< MDIOS Input Data Register (MDIOS_DINR8),        Address offset: 120h      */ 
-  __IO uint32_t DINR9;            /*!< MDIOS Input Data Register (MDIOS_DINR9),        Address offset: 124h      */ 
-  __IO uint32_t DINR10;           /*!< MDIOS Input Data Register (MDIOS_DINR10),       Address offset: 128h      */ 
-  __IO uint32_t DINR11;           /*!< MDIOS Input Data Register (MDIOS_DINR11),       Address offset: 12Ch      */ 
-  __IO uint32_t DINR12;           /*!< MDIOS Input Data Register (MDIOS_DINR12),       Address offset: 130h      */ 
-  __IO uint32_t DINR13;           /*!< MDIOS Input Data Register (MDIOS_DINR13),       Address offset: 134h      */ 
-  __IO uint32_t DINR14;           /*!< MDIOS Input Data Register (MDIOS_DINR14),       Address offset: 138h      */ 
-  __IO uint32_t DINR15;           /*!< MDIOS Input Data Register (MDIOS_DINR15),       Address offset: 13Ch      */ 
-  __IO uint32_t DINR16;           /*!< MDIOS Input Data Register (MDIOS_DINR16),       Address offset: 140h      */ 
-  __IO uint32_t DINR17;           /*!< MDIOS Input Data Register (MDIOS_DINR17),       Address offset: 144h      */ 
-  __IO uint32_t DINR18;           /*!< MDIOS Input Data Register (MDIOS_DINR18),       Address offset: 148h      */ 
-  __IO uint32_t DINR19;           /*!< MDIOS Input Data Register (MDIOS_DINR19),       Address offset: 14Ch      */ 
-  __IO uint32_t DINR20;           /*!< MDIOS Input Data Register (MDIOS_DINR20),       Address offset: 150h      */ 
-  __IO uint32_t DINR21;           /*!< MDIOS Input Data Register (MDIOS_DINR21),       Address offset: 154h      */ 
-  __IO uint32_t DINR22;           /*!< MDIOS Input Data Register (MDIOS_DINR22),       Address offset: 158h      */ 
-  __IO uint32_t DINR23;           /*!< MDIOS Input Data Register (MDIOS_DINR23),       Address offset: 15Ch      */ 
-  __IO uint32_t DINR24;           /*!< MDIOS Input Data Register (MDIOS_DINR24),       Address offset: 160h      */ 
-  __IO uint32_t DINR25;           /*!< MDIOS Input Data Register (MDIOS_DINR25),       Address offset: 164h      */ 
-  __IO uint32_t DINR26;           /*!< MDIOS Input Data Register (MDIOS_DINR26),       Address offset: 168h      */ 
-  __IO uint32_t DINR27;           /*!< MDIOS Input Data Register (MDIOS_DINR27),       Address offset: 16Ch      */ 
-  __IO uint32_t DINR28;           /*!< MDIOS Input Data Register (MDIOS_DINR28),       Address offset: 170h      */ 
-  __IO uint32_t DINR29;           /*!< MDIOS Input Data Register (MDIOS_DINR29),       Address offset: 174h      */ 
-  __IO uint32_t DINR30;           /*!< MDIOS Input Data Register (MDIOS_DINR30),       Address offset: 178h      */ 
-  __IO uint32_t DINR31;           /*!< MDIOS Input Data Register (MDIOS_DINR31),       Address offset: 17Ch      */ 
-  __IO uint32_t DOUTR0;           /*!< MDIOS Output Data Register (MDIOS_DOUTR0),      Address offset: 180h      */   
-  __IO uint32_t DOUTR1;           /*!< MDIOS Output Data Register (MDIOS_DOUTR1),      Address offset: 184h      */   
-  __IO uint32_t DOUTR2;           /*!< MDIOS Output Data Register (MDIOS_DOUTR2),      Address offset: 188h      */    
-  __IO uint32_t DOUTR3;           /*!< MDIOS Output Data Register (MDIOS_DOUTR3),      Address offset: 18Ch      */    
-  __IO uint32_t DOUTR4;           /*!< MDIOS Output Data Register (MDIOS_DOUTR4),      Address offset: 190h      */   
-  __IO uint32_t DOUTR5;           /*!< MDIOS Output Data Register (MDIOS_DOUTR5),      Address offset: 194h      */    
-  __IO uint32_t DOUTR6;           /*!< MDIOS Output Data Register (MDIOS_DOUTR6),      Address offset: 198h      */    
-  __IO uint32_t DOUTR7;           /*!< MDIOS Output Data Register (MDIOS_DOUTR7),      Address offset: 19Ch      */
-  __IO uint32_t DOUTR8;           /*!< MDIOS Output Data Register (MDIOS_DOUTR8),      Address offset: 1A0h      */
-  __IO uint32_t DOUTR9;           /*!< MDIOS Output Data Register (MDIOS_DOUTR9),      Address offset: 1A4h      */
-  __IO uint32_t DOUTR10;          /*!< MDIOS Output Data Register (MDIOS_DOUTR10),     Address offset: 1A8h      */
-  __IO uint32_t DOUTR11;          /*!< MDIOS Output Data Register (MDIOS_DOUTR11),     Address offset: 1ACh      */
-  __IO uint32_t DOUTR12;          /*!< MDIOS Output Data Register (MDIOS_DOUTR12),     Address offset: 1B0h      */
-  __IO uint32_t DOUTR13;          /*!< MDIOS Output Data Register (MDIOS_DOUTR13),     Address offset: 1B4h      */
-  __IO uint32_t DOUTR14;          /*!< MDIOS Output Data Register (MDIOS_DOUTR14),     Address offset: 1B8h      */
-  __IO uint32_t DOUTR15;          /*!< MDIOS Output Data Register (MDIOS_DOUTR15),     Address offset: 1BCh      */
-  __IO uint32_t DOUTR16;          /*!< MDIOS Output Data Register (MDIOS_DOUTR16),     Address offset: 1C0h      */
-  __IO uint32_t DOUTR17;          /*!< MDIOS Output Data Register (MDIOS_DOUTR17),     Address offset: 1C4h      */
-  __IO uint32_t DOUTR18;          /*!< MDIOS Output Data Register (MDIOS_DOUTR18),     Address offset: 1C8h      */
-  __IO uint32_t DOUTR19;          /*!< MDIOS Output Data Register (MDIOS_DOUTR19),     Address offset: 1CCh      */
-  __IO uint32_t DOUTR20;          /*!< MDIOS Output Data Register (MDIOS_DOUTR20),     Address offset: 1D0h      */
-  __IO uint32_t DOUTR21;          /*!< MDIOS Output Data Register (MDIOS_DOUTR21),     Address offset: 1D4h      */
-  __IO uint32_t DOUTR22;          /*!< MDIOS Output Data Register (MDIOS_DOUTR22),     Address offset: 1D8h      */
-  __IO uint32_t DOUTR23;          /*!< MDIOS Output Data Register (MDIOS_DOUTR23),     Address offset: 1DCh      */
-  __IO uint32_t DOUTR24;          /*!< MDIOS Output Data Register (MDIOS_DOUTR24),     Address offset: 1E0h      */
-  __IO uint32_t DOUTR25;          /*!< MDIOS Output Data Register (MDIOS_DOUTR25),     Address offset: 1E4h      */
-  __IO uint32_t DOUTR26;          /*!< MDIOS Output Data Register (MDIOS_DOUTR26),     Address offset: 1E8h      */
-  __IO uint32_t DOUTR27;          /*!< MDIOS Output Data Register (MDIOS_DOUTR27),     Address offset: 1ECh      */
-  __IO uint32_t DOUTR28;          /*!< MDIOS Output Data Register (MDIOS_DOUTR28),     Address offset: 1F0h      */
-  __IO uint32_t DOUTR29;          /*!< MDIOS Output Data Register (MDIOS_DOUTR29),     Address offset: 1F4h      */
-  __IO uint32_t DOUTR30;          /*!< MDIOS Output Data Register (MDIOS_DOUTR30),     Address offset: 1F8h      */
-  __IO uint32_t DOUTR31;          /*!< MDIOS Output Data Register (MDIOS_DOUTR31),     Address offset: 1FCh      */
-} MDIOS_TypeDef;
-
-/** 
-  * @brief DSI Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t VR;            /*!< DSI Host Version Register,                                 Address offset: 0x00      */
-  __IO uint32_t CR;            /*!< DSI Host Control Register,                                 Address offset: 0x04      */
-  __IO uint32_t CCR;           /*!< DSI HOST Clock Control Register,                           Address offset: 0x08      */
-  __IO uint32_t LVCIDR;        /*!< DSI Host LTDC VCID Register,                               Address offset: 0x0C      */
-  __IO uint32_t LCOLCR;        /*!< DSI Host LTDC Color Coding Register,                       Address offset: 0x10      */ 
-  __IO uint32_t LPCR;          /*!< DSI Host LTDC Polarity Configuration Register,             Address offset: 0x14      */
-  __IO uint32_t LPMCR;         /*!< DSI Host Low-Power Mode Configuration Register,            Address offset: 0x18      */
-  uint32_t      RESERVED0[4];  /*!< Reserved, 0x1C - 0x2B                                                                */
-  __IO uint32_t PCR;           /*!< DSI Host Protocol Configuration Register,                  Address offset: 0x2C      */ 
-  __IO uint32_t GVCIDR;        /*!< DSI Host Generic VCID Register,                            Address offset: 0x30      */
-  __IO uint32_t MCR;           /*!< DSI Host Mode Configuration Register,                      Address offset: 0x34      */
-  __IO uint32_t VMCR;          /*!< DSI Host Video Mode Configuration Register,                Address offset: 0x38      */
-  __IO uint32_t VPCR;          /*!< DSI Host Video Packet Configuration Register,              Address offset: 0x3C      */
-  __IO uint32_t VCCR;          /*!< DSI Host Video Chunks Configuration Register,              Address offset: 0x40      */
-  __IO uint32_t VNPCR;         /*!< DSI Host Video Null Packet Configuration Register,         Address offset: 0x44      */
-  __IO uint32_t VHSACR;        /*!< DSI Host Video HSA Configuration Register,                 Address offset: 0x48      */
-  __IO uint32_t VHBPCR;        /*!< DSI Host Video HBP Configuration Register,                 Address offset: 0x4C      */
-  __IO uint32_t VLCR;          /*!< DSI Host Video Line Configuration Register,                Address offset: 0x50      */
-  __IO uint32_t VVSACR;        /*!< DSI Host Video VSA Configuration Register,                 Address offset: 0x54      */
-  __IO uint32_t VVBPCR;        /*!< DSI Host Video VBP Configuration Register,                 Address offset: 0x58      */
-  __IO uint32_t VVFPCR;        /*!< DSI Host Video VFP Configuration Register,                 Address offset: 0x5C      */
-  __IO uint32_t VVACR;         /*!< DSI Host Video VA Configuration Register,                  Address offset: 0x60      */
-  __IO uint32_t LCCR;          /*!< DSI Host LTDC Command Configuration Register,              Address offset: 0x64      */ 
-  __IO uint32_t CMCR;          /*!< DSI Host Command Mode Configuration Register,              Address offset: 0x68      */
-  __IO uint32_t GHCR;          /*!< DSI Host Generic Header Configuration Register,            Address offset: 0x6C      */
-  __IO uint32_t GPDR;          /*!< DSI Host Generic Payload Data Register,                    Address offset: 0x70      */
-  __IO uint32_t GPSR;          /*!< DSI Host Generic Packet Status Register,                   Address offset: 0x74      */
-  __IO uint32_t TCCR[6];       /*!< DSI Host Timeout Counter Configuration Register,           Address offset: 0x78-0x8F */
-  __IO uint32_t TDCR;          /*!< DSI Host 3D Configuration Register,                        Address offset: 0x90      */ 
-  __IO uint32_t CLCR;          /*!< DSI Host Clock Lane Configuration Register,                Address offset: 0x94      */
-  __IO uint32_t CLTCR;         /*!< DSI Host Clock Lane Timer Configuration Register,          Address offset: 0x98      */
-  __IO uint32_t DLTCR;         /*!< DSI Host Data Lane Timer Configuration Register,           Address offset: 0x9C      */
-  __IO uint32_t PCTLR;         /*!< DSI Host PHY Control Register,                             Address offset: 0xA0      */ 
-  __IO uint32_t PCONFR;        /*!< DSI Host PHY Configuration Register,                       Address offset: 0xA4      */ 
-  __IO uint32_t PUCR;          /*!< DSI Host PHY ULPS Control Register,                        Address offset: 0xA8      */
-  __IO uint32_t PTTCR;         /*!< DSI Host PHY TX Triggers Configuration Register,           Address offset: 0xAC      */
-  __IO uint32_t PSR;           /*!< DSI Host PHY Status Register,                              Address offset: 0xB0      */
-  uint32_t      RESERVED1[2];  /*!< Reserved, 0xB4 - 0xBB                                                                */
-  __IO uint32_t ISR[2];        /*!< DSI Host Interrupt & Status Register,                      Address offset: 0xBC-0xC3 */
-  __IO uint32_t IER[2];        /*!< DSI Host Interrupt Enable Register,                        Address offset: 0xC4-0xCB */
-  uint32_t      RESERVED2[3];  /*!< Reserved, 0xD0 - 0xD7                                                                */
-  __IO uint32_t FIR[2];        /*!< DSI Host Force Interrupt Register,                         Address offset: 0xD8-0xDF */
-  uint32_t      RESERVED3[8];  /*!< Reserved, 0xE0 - 0xFF                                                                */
-  __IO uint32_t VSCR;          /*!< DSI Host Video Shadow Control Register,                    Address offset: 0x100     */
-  uint32_t      RESERVED4[2];  /*!< Reserved, 0x104 - 0x10B                                                              */
-  __IO uint32_t LCVCIDR;       /*!< DSI Host LTDC Current VCID Register,                       Address offset: 0x10C     */
-  __IO uint32_t LCCCR;         /*!< DSI Host LTDC Current Color Coding Register,               Address offset: 0x110     */
-  uint32_t      RESERVED5;     /*!< Reserved, 0x114                                                                      */
-  __IO uint32_t LPMCCR;        /*!< DSI Host Low-power Mode Current Configuration Register,    Address offset: 0x118     */
-  uint32_t      RESERVED6[7];  /*!< Reserved, 0x11C - 0x137                                                              */
-  __IO uint32_t VMCCR;         /*!< DSI Host Video Mode Current Configuration Register,        Address offset: 0x138     */
-  __IO uint32_t VPCCR;         /*!< DSI Host Video Packet Current Configuration Register,      Address offset: 0x13C     */
-  __IO uint32_t VCCCR;         /*!< DSI Host Video Chuncks Current Configuration Register,     Address offset: 0x140     */
-  __IO uint32_t VNPCCR;        /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144     */
-  __IO uint32_t VHSACCR;       /*!< DSI Host Video HSA Current Configuration Register,         Address offset: 0x148     */
-  __IO uint32_t VHBPCCR;       /*!< DSI Host Video HBP Current Configuration Register,         Address offset: 0x14C     */
-  __IO uint32_t VLCCR;         /*!< DSI Host Video Line Current Configuration Register,        Address offset: 0x150     */
-  __IO uint32_t VVSACCR;       /*!< DSI Host Video VSA Current Configuration Register,         Address offset: 0x154     */ 
-  __IO uint32_t VVBPCCR;       /*!< DSI Host Video VBP Current Configuration Register,         Address offset: 0x158     */
-  __IO uint32_t VVFPCCR;       /*!< DSI Host Video VFP Current Configuration Register,         Address offset: 0x15C     */
-  __IO uint32_t VVACCR;        /*!< DSI Host Video VA Current Configuration Register,          Address offset: 0x160     */
-  uint32_t      RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F                                                              */
-  __IO uint32_t TDCCR;         /*!< DSI Host 3D Current Configuration Register,                Address offset: 0x190     */ 
-  uint32_t      RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF                                                               */
-  __IO uint32_t WCFGR;          /*!< DSI Wrapper Configuration Register,                       Address offset: 0x400       */
-  __IO uint32_t WCR;            /*!< DSI Wrapper Control Register,                             Address offset: 0x404       */
-  __IO uint32_t WIER;           /*!< DSI Wrapper Interrupt Enable Register,                    Address offset: 0x408       */
-  __IO uint32_t WISR;           /*!< DSI Wrapper Interrupt and Status Register,                Address offset: 0x40C       */
-  __IO uint32_t WIFCR;          /*!< DSI Wrapper Interrupt Flag Clear Register,                Address offset: 0x410       */
-  uint32_t      RESERVED9;      /*!< Reserved, 0x414                                                                       */
-  __IO uint32_t WPCR[5];        /*!< DSI Wrapper PHY Configuration Register,                   Address offset: 0x418-0x42B */
-  uint32_t      RESERVED10;     /*!< Reserved, 0x42C                                                                       */
-  __IO uint32_t WRPCR;          /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430                 */
-} DSI_TypeDef;
-
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-#define RAMITCM_BASE           0x00000000U /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM  */
-#define FLASHITCM_BASE         0x00200000U /*!< Base address of : (up to 2 MB) embedded FLASH memory  accessible over ITCM              */                       
-#define FLASHAXI_BASE          0x08000000U /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI                */                       
-#define RAMDTCM_BASE           0x20000000U /*!< Base address of : 128KB system data RAM accessible over DTCM                            */
-#define PERIPH_BASE            0x40000000U /*!< Base address of : AHB/ABP Peripherals                                                   */
-#define BKPSRAM_BASE           0x40024000U /*!< Base address of : Backup SRAM(4 KB)                                                     */
-#define QSPI_BASE              0x90000000U /*!< Base address of : QSPI memories  accessible over AXI                                    */
-#define FMC_R_BASE             0xA0000000U /*!< Base address of : FMC Control registers                                                 */
-#define QSPI_R_BASE            0xA0001000U /*!< Base address of : QSPI Control  registers                                               */
-#define SRAM1_BASE             0x20020000U /*!< Base address of : 368KB RAM1 accessible over AXI/AHB                                    */
-#define SRAM2_BASE             0x2007C000U /*!< Base address of : 16KB RAM2 accessible over AXI/AHB                                     */
-#define FLASH_END              0x081FFFFFU /*!< FLASH end address */
-
-/* Legacy define */
-#define FLASH_BASE     FLASHAXI_BASE
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE        PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000U)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)
-#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800U)
-#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00U)
-#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000U)
-#define LPTIM1_BASE           (APB1PERIPH_BASE + 0x2400U)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)
-#define CAN3_BASE             (APB1PERIPH_BASE + 0x3400U)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)
-#define SPDIFRX_BASE          (APB1PERIPH_BASE + 0x4000U)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800U)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00U)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x5000U)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)
-#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)
-#define I2C4_BASE             (APB1PERIPH_BASE + 0x6000U)
-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)
-#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800U)
-#define CEC_BASE              (APB1PERIPH_BASE + 0x6C00U)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)
-#define UART7_BASE            (APB1PERIPH_BASE + 0x7800U)
-#define UART8_BASE            (APB1PERIPH_BASE + 0x7C00U)
-
-/*!< APB2 peripherals */
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000U)
-#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400U)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x1000U)
-#define USART6_BASE           (APB2PERIPH_BASE + 0x1400U)
-#define SDMMC2_BASE           (APB2PERIPH_BASE + 0x1C00U)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000U)
-#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100U)
-#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200U)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x2300U)
-#define SDMMC1_BASE           (APB2PERIPH_BASE + 0x2C00U)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)
-#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400U)
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800U)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00U)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000U)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400U)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800U)
-#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000U)
-#define SPI6_BASE             (APB2PERIPH_BASE + 0x5400U)
-#define SAI1_BASE             (APB2PERIPH_BASE + 0x5800U)
-#define SAI2_BASE             (APB2PERIPH_BASE + 0x5C00U)
-#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004U)
-#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024U)
-#define SAI2_Block_A_BASE     (SAI2_BASE + 0x004U)
-#define SAI2_Block_B_BASE     (SAI2_BASE + 0x024U)
-#define LTDC_BASE             (APB2PERIPH_BASE + 0x6800U)
-#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84U)
-#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104U)
-#define DSI_BASE              (APB2PERIPH_BASE + 0x6C00U)
-#define DFSDM1_BASE           (APB2PERIPH_BASE + 0x7400U)
-#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00U)
-#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20U)
-#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40U)
-#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60U)
-#define DFSDM1_Channel4_BASE  (DFSDM1_BASE + 0x80U)
-#define DFSDM1_Channel5_BASE  (DFSDM1_BASE + 0xA0U)
-#define DFSDM1_Channel6_BASE  (DFSDM1_BASE + 0xC0U)
-#define DFSDM1_Channel7_BASE  (DFSDM1_BASE + 0xE0U)
-#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100U)
-#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180U)
-#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200U)
-#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280U)
-#define MDIOS_BASE            (APB2PERIPH_BASE + 0x7800U)
-/*!< AHB1 peripherals */
-#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000U)
-#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400U)
-#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800U)
-#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00U)
-#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000U)
-#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400U)
-#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800U)
-#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00U)
-#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000U)
-#define GPIOJ_BASE            (AHB1PERIPH_BASE + 0x2400U)
-#define GPIOK_BASE            (AHB1PERIPH_BASE + 0x2800U)
-#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)
-#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800U)
-#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00U)
-#define UID_BASE              0x1FF0F420U                   /*!< Unique device ID register base address */
-#define FLASHSIZE_BASE        0x1FF0F442U                   /*!< FLASH Size register base address */
-#define PACKAGESIZE_BASE      0x1FFF7BF0U                   /*!< Package size register base address */
-#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000U)
-#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010U)
-#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028U)
-#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040U)
-#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058U)
-#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070U)
-#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088U)
-#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0U)
-#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8U)
-#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400U)
-#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010U)
-#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028U)
-#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040U)
-#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058U)
-#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070U)
-#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088U)
-#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0U)
-#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)
-#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000U)
-#define ETH_MAC_BASE          (ETH_BASE)
-#define ETH_MMC_BASE          (ETH_BASE + 0x0100U)
-#define ETH_PTP_BASE          (ETH_BASE + 0x0700U)
-#define ETH_DMA_BASE          (ETH_BASE + 0x1000U)
-#define DMA2D_BASE            (AHB1PERIPH_BASE + 0xB000U)
-/*!< AHB2 peripherals */
-#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000U)
-#define JPEG_BASE           (AHB2PERIPH_BASE + 0x51000U)
-#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800U)
-/*!< FMC Bankx registers base address */
-#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000U)
-#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104U)
-#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080U)
-#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140U)
-
-/* Debug MCU registers base address */
-#define DBGMCU_BASE           0xE0042000U
-
-/*!< USB registers base address */
-#define USB_OTG_HS_PERIPH_BASE               0x40040000U
-#define USB_OTG_FS_PERIPH_BASE               0x50000000U
-
-#define USB_OTG_GLOBAL_BASE                  0x000U
-#define USB_OTG_DEVICE_BASE                  0x800U
-#define USB_OTG_IN_ENDPOINT_BASE             0x900U
-#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U
-#define USB_OTG_EP_REG_SIZE                  0x20U
-#define USB_OTG_HOST_BASE                    0x400U
-#define USB_OTG_HOST_PORT_BASE               0x440U
-#define USB_OTG_HOST_CHANNEL_BASE            0x500U
-#define USB_OTG_HOST_CHANNEL_SIZE            0x20U
-#define USB_OTG_PCGCCTL_BASE                 0xE00U
-#define USB_OTG_FIFO_BASE                    0x1000U
-#define USB_OTG_FIFO_SIZE                    0x1000U
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
-#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
-#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
-#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define SPDIFRX             ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define UART4               ((USART_TypeDef *) UART4_BASE)
-#define UART5               ((USART_TypeDef *) UART5_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
-#define I2C4                ((I2C_TypeDef *) I2C4_BASE)
-#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
-#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
-#define CEC                 ((CEC_TypeDef *) CEC_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
-#define UART7               ((USART_TypeDef *) UART7_BASE)
-#define UART8               ((USART_TypeDef *) UART8_BASE)
-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
-#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define USART6              ((USART_TypeDef *) USART6_BASE)
-#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
-#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
-#define SDMMC1              ((SDMMC_TypeDef *) SDMMC1_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE) 
-#define SPI4                ((SPI_TypeDef *) SPI4_BASE)
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-#define SPI5                ((SPI_TypeDef *) SPI5_BASE)
-#define SPI6                ((SPI_TypeDef *) SPI6_BASE)
-#define SAI1                ((SAI_TypeDef *) SAI1_BASE)
-#define SAI2                ((SAI_TypeDef *) SAI2_BASE)
-#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
-#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
-#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
-#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
-#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)
-#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
-#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
-#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)
-#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
-#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
-#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
-#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
-#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
-#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
-#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
-#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
-#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
-#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
-#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
-#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
-#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
-#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
-#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
-#define ETH                 ((ETH_TypeDef *) ETH_BASE)  
-#define DMA2D               ((DMA2D_TypeDef *)DMA2D_BASE)
-#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
-#define RNG                 ((RNG_TypeDef *) RNG_BASE)
-#define FMC_Bank1           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
-#define FMC_Bank1E          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
-#define FMC_Bank3           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
-#define FMC_Bank5_6         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
-#define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
-#define USB_OTG_HS          ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
-#define CAN3                ((CAN_TypeDef *) CAN3_BASE)
-#define SDMMC2              ((SDMMC_TypeDef *) SDMMC2_BASE)
-#define MDIOS               ((MDIOS_TypeDef *) MDIOS_BASE)
-#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
-#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
-#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
-#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
-#define DFSDM1_Channel4     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
-#define DFSDM1_Channel5     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
-#define DFSDM1_Channel6     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
-#define DFSDM1_Channel7     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
-#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
-#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
-#define DFSDM1_Filter2      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
-#define DFSDM1_Filter3      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
-#define JPEG                ((JPEG_TypeDef *) JPEG_BASE)
-#define DSI                 ((DSI_TypeDef *)DSI_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers_Bits_Definition               */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Analog to Digital Converter                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          0x00000001U        /*!<Analog watchdog flag                                 */
-#define  ADC_SR_EOC                          0x00000002U        /*!<End of conversion                                    */
-#define  ADC_SR_JEOC                         0x00000004U        /*!<Injected channel end of conversion                   */
-#define  ADC_SR_JSTRT                        0x00000008U        /*!<Injected channel Start flag                          */
-#define  ADC_SR_STRT                         0x00000010U        /*!<Regular channel Start flag                           */
-#define  ADC_SR_OVR                          0x00000020U        /*!<Overrun flag                                         */
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC                             */
-#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable                    */
-#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels               */
-#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
-#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion                  */
-#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels               */
-#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels              */
-#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels          */
-#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels           */
-#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution)                           */
-#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
-  
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF                                       */
-#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion                                        */
-#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode                                    */
-#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC)                           */
-#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection                                  */
-#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment                                               */
-#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      ((uint16_t)0xFFFFU)            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      ((uint16_t)0xFFFFU)            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      ((uint16_t)0xFFFFU)            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      ((uint16_t)0xFFFFU)            /*!<Injected data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag               */
-#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion                  */
-#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag        */
-#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag         */
-#define  ADC_CSR_OVR1                        0x00000020U        /*!<ADC1 Overrun flag                       */
-#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag               */
-#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion                  */
-#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag        */
-#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag         */
-#define  ADC_CSR_OVR2                        0x00002000U        /*!<ADC2 Overrun flag                       */
-#define  ADC_CSR_AWD3                        0x00010000U        /*!<ADC3 Analog watchdog flag               */
-#define  ADC_CSR_EOC3                        0x00020000U        /*!<ADC3 End of conversion                  */
-#define  ADC_CSR_JEOC3                       0x00040000U        /*!<ADC3 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT3                      0x00080000U        /*!<ADC3 Injected channel Start flag        */
-#define  ADC_CSR_STRT3                       0x00100000U        /*!<ADC3 Regular channel Start flag         */
-#define  ADC_CSR_OVR3                        0x00200000U        /*!<ADC3 Overrun flag                       */
-
-/* Legacy defines */
-#define  ADC_CSR_DOVR1                       ADC_CSR_OVR1
-#define  ADC_CSR_DOVR2                       ADC_CSR_OVR2
-#define  ADC_CSR_DOVR3                       ADC_CSR_OVR3
-
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
-#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
-#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
-#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
-#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
-
-/*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                       0x0000FFFFU         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                       0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Controller Area Network                            */
-/*                                                                            */
-/******************************************************************************/
-/*!<CAN control and status registers */
-/*******************  Bit definition for CAN_MCR register  ********************/
-#define  CAN_MCR_INRQ                        0x00000001U        /*!<Initialization Request            */
-#define  CAN_MCR_SLEEP                       0x00000002U        /*!<Sleep Mode Request                */
-#define  CAN_MCR_TXFP                        0x00000004U        /*!<Transmit FIFO Priority            */
-#define  CAN_MCR_RFLM                        0x00000008U        /*!<Receive FIFO Locked Mode          */
-#define  CAN_MCR_NART                        0x00000010U        /*!<No Automatic Retransmission       */
-#define  CAN_MCR_AWUM                        0x00000020U        /*!<Automatic Wakeup Mode             */
-#define  CAN_MCR_ABOM                        0x00000040U        /*!<Automatic Bus-Off Management      */
-#define  CAN_MCR_TTCM                        0x00000080U        /*!<Time Triggered Communication Mode */
-#define  CAN_MCR_RESET                       0x00008000U        /*!<bxCAN software master reset       */
-                                                                           
-/*******************  Bit definition for CAN_MSR register  ********************/
-#define  CAN_MSR_INAK                        0x00000001U        /*!<Initialization Acknowledge  */
-#define  CAN_MSR_SLAK                        0x00000002U        /*!<Sleep Acknowledge           */
-#define  CAN_MSR_ERRI                        0x00000004U        /*!<Error Interrupt             */
-#define  CAN_MSR_WKUI                        0x00000008U        /*!<Wakeup Interrupt            */
-#define  CAN_MSR_SLAKI                       0x00000010U        /*!<Sleep Acknowledge Interrupt */
-#define  CAN_MSR_TXM                         0x00000100U        /*!<Transmit Mode               */
-#define  CAN_MSR_RXM                         0x00000200U        /*!<Receive Mode                */
-#define  CAN_MSR_SAMP                        0x00000400U        /*!<Last Sample Point           */
-#define  CAN_MSR_RX                          0x00000800U        /*!<CAN Rx Signal               */
-
-/*******************  Bit definition for CAN_TSR register  ********************/
-#define  CAN_TSR_RQCP0                       0x00000001U        /*!<Request Completed Mailbox0      */
-#define  CAN_TSR_TXOK0                       0x00000002U        /*!<Transmission OK of Mailbox0     */
-#define  CAN_TSR_ALST0                       0x00000004U        /*!<Arbitration Lost for Mailbox0   */
-#define  CAN_TSR_TERR0                       0x00000008U        /*!<Transmission Error of Mailbox0  */
-#define  CAN_TSR_ABRQ0                       0x00000080U        /*!<Abort Request for Mailbox0      */
-#define  CAN_TSR_RQCP1                       0x00000100U        /*!<Request Completed Mailbox1      */
-#define  CAN_TSR_TXOK1                       0x00000200U        /*!<Transmission OK of Mailbox1     */
-#define  CAN_TSR_ALST1                       0x00000400U        /*!<Arbitration Lost for Mailbox1   */
-#define  CAN_TSR_TERR1                       0x00000800U        /*!<Transmission Error of Mailbox1  */
-#define  CAN_TSR_ABRQ1                       0x00008000U        /*!<Abort Request for Mailbox 1     */
-#define  CAN_TSR_RQCP2                       0x00010000U        /*!<Request Completed Mailbox2      */
-#define  CAN_TSR_TXOK2                       0x00020000U        /*!<Transmission OK of Mailbox 2    */
-#define  CAN_TSR_ALST2                       0x00040000U        /*!<Arbitration Lost for mailbox 2  */
-#define  CAN_TSR_TERR2                       0x00080000U        /*!<Transmission Error of Mailbox 2 */
-#define  CAN_TSR_ABRQ2                       0x00800000U        /*!<Abort Request for Mailbox 2     */
-#define  CAN_TSR_CODE                        0x03000000U        /*!<Mailbox Code                    */
-
-#define  CAN_TSR_TME                         0x1C000000U        /*!<TME[2:0] bits */
-#define  CAN_TSR_TME0                        0x04000000U        /*!<Transmit Mailbox 0 Empty */
-#define  CAN_TSR_TME1                        0x08000000U        /*!<Transmit Mailbox 1 Empty */
-#define  CAN_TSR_TME2                        0x10000000U        /*!<Transmit Mailbox 2 Empty */
-
-#define  CAN_TSR_LOW                         0xE0000000U        /*!<LOW[2:0] bits */
-#define  CAN_TSR_LOW0                        0x20000000U        /*!<Lowest Priority Flag for Mailbox 0 */
-#define  CAN_TSR_LOW1                        0x40000000U        /*!<Lowest Priority Flag for Mailbox 1 */
-#define  CAN_TSR_LOW2                        0x80000000U        /*!<Lowest Priority Flag for Mailbox 2 */
-
-/*******************  Bit definition for CAN_RF0R register  *******************/
-#define  CAN_RF0R_FMP0                       0x00000003U        /*!<FIFO 0 Message Pending        */
-#define  CAN_RF0R_FULL0                      0x00000008U        /*!<FIFO 0 Full                   */
-#define  CAN_RF0R_FOVR0                      0x00000010U        /*!<FIFO 0 Overrun                */
-#define  CAN_RF0R_RFOM0                      0x00000020U        /*!<Release FIFO 0 Output Mailbox */
-
-/*******************  Bit definition for CAN_RF1R register  *******************/
-#define  CAN_RF1R_FMP1                       0x00000003U        /*!<FIFO 1 Message Pending        */
-#define  CAN_RF1R_FULL1                      0x00000008U        /*!<FIFO 1 Full                   */
-#define  CAN_RF1R_FOVR1                      0x00000010U        /*!<FIFO 1 Overrun                */
-#define  CAN_RF1R_RFOM1                      0x00000020U        /*!<Release FIFO 1 Output Mailbox */
-
-/********************  Bit definition for CAN_IER register  *******************/
-#define  CAN_IER_TMEIE                       0x00000001U        /*!<Transmit Mailbox Empty Interrupt Enable */
-#define  CAN_IER_FMPIE0                      0x00000002U        /*!<FIFO Message Pending Interrupt Enable   */
-#define  CAN_IER_FFIE0                       0x00000004U        /*!<FIFO Full Interrupt Enable              */
-#define  CAN_IER_FOVIE0                      0x00000008U        /*!<FIFO Overrun Interrupt Enable           */
-#define  CAN_IER_FMPIE1                      0x00000010U        /*!<FIFO Message Pending Interrupt Enable   */
-#define  CAN_IER_FFIE1                       0x00000020U        /*!<FIFO Full Interrupt Enable              */
-#define  CAN_IER_FOVIE1                      0x00000040U        /*!<FIFO Overrun Interrupt Enable           */
-#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error Warning Interrupt Enable          */
-#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error Passive Interrupt Enable          */
-#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-Off Interrupt Enable                */
-#define  CAN_IER_LECIE                       0x00000800U        /*!<Last Error Code Interrupt Enable        */
-#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error Interrupt Enable                  */
-#define  CAN_IER_WKUIE                       0x00010000U        /*!<Wakeup Interrupt Enable                 */
-#define  CAN_IER_SLKIE                       0x00020000U        /*!<Sleep Interrupt Enable                  */
-
-/********************  Bit definition for CAN_ESR register  *******************/
-#define  CAN_ESR_EWGF                        0x00000001U        /*!<Error Warning Flag */
-#define  CAN_ESR_EPVF                        0x00000002U        /*!<Error Passive Flag */
-#define  CAN_ESR_BOFF                        0x00000004U        /*!<Bus-Off Flag */
-
-#define  CAN_ESR_LEC                         0x00000070U        /*!<LEC[2:0] bits (Last Error Code) */
-#define  CAN_ESR_LEC_0                       0x00000010U        /*!<Bit 0 */
-#define  CAN_ESR_LEC_1                       0x00000020U        /*!<Bit 1 */
-#define  CAN_ESR_LEC_2                       0x00000040U        /*!<Bit 2 */
-
-#define  CAN_ESR_TEC                         0x00FF0000U        /*!<Least significant byte of the 9-bit Transmit Error Counter */
-#define  CAN_ESR_REC                         0xFF000000U        /*!<Receive Error Counter */
-
-/*******************  Bit definition for CAN_BTR register  ********************/
-#define  CAN_BTR_BRP                         0x000003FFU        /*!<Baud Rate Prescaler           */
-#define  CAN_BTR_TS1                         0x000F0000U        /*!<Time Segment 1                */
-#define  CAN_BTR_TS1_0                       0x00010000U        /*!<Bit 0 */
-#define  CAN_BTR_TS1_1                       0x00020000U        /*!<Bit 1 */
-#define  CAN_BTR_TS1_2                       0x00040000U        /*!<Bit 2 */
-#define  CAN_BTR_TS1_3                       0x00080000U        /*!<Bit 3 */
-#define  CAN_BTR_TS2                         0x00700000U        /*!<Time Segment 2                */
-#define  CAN_BTR_TS2_0                       0x00100000U        /*!<Bit 0 */
-#define  CAN_BTR_TS2_1                       0x00200000U        /*!<Bit 1 */
-#define  CAN_BTR_TS2_2                       0x00400000U        /*!<Bit 2 */
-#define  CAN_BTR_SJW                         0x03000000U        /*!<Resynchronization Jump Width  */
-#define  CAN_BTR_SJW_0                       0x01000000U        /*!<Bit 0 */
-#define  CAN_BTR_SJW_1                       0x02000000U        /*!<Bit 1 */
-#define  CAN_BTR_LBKM                        0x40000000U        /*!<Loop Back Mode (Debug)        */
-#define  CAN_BTR_SILM                        0x80000000U        /*!<Silent Mode                   */
-
-/*!<Mailbox registers */
-/******************  Bit definition for CAN_TI0R register  ********************/
-#define  CAN_TI0R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request                   */
-#define  CAN_TI0R_RTR                        0x00000002U        /*!<Remote Transmission Request                */
-#define  CAN_TI0R_IDE                        0x00000004U        /*!<Identifier Extension                       */
-#define  CAN_TI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier                        */
-#define  CAN_TI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/******************  Bit definition for CAN_TDT0R register  *******************/
-#define  CAN_TDT0R_DLC                       0x0000000FU        /*!<Data Length Code     */
-#define  CAN_TDT0R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp   */
-
-/******************  Bit definition for CAN_TDL0R register  *******************/
-#define  CAN_TDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/******************  Bit definition for CAN_TDH0R register  *******************/
-#define  CAN_TDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI1R register  *******************/
-#define  CAN_TI1R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request                   */
-#define  CAN_TI1R_RTR                        0x00000002U        /*!<Remote Transmission Request                */
-#define  CAN_TI1R_IDE                        0x00000004U        /*!<Identifier Extension                       */
-#define  CAN_TI1R_EXID                       0x001FFFF8U        /*!<Extended Identifier                        */
-#define  CAN_TI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT1R register  ******************/
-#define  CAN_TDT1R_DLC                       0x0000000FU        /*!<Data Length Code     */
-#define  CAN_TDT1R_TGT                       0x00000100U        /*!<Transmit Global Time */
-#define  CAN_TDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp   */
-
-/*******************  Bit definition for CAN_TDL1R register  ******************/
-#define  CAN_TDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH1R register  ******************/
-#define  CAN_TDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI2R register  *******************/
-#define  CAN_TI2R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request                   */
-#define  CAN_TI2R_RTR                        0x00000002U        /*!<Remote Transmission Request                */
-#define  CAN_TI2R_IDE                        0x00000004U        /*!<Identifier Extension                       */
-#define  CAN_TI2R_EXID                       0x001FFFF8U        /*!<Extended identifier                        */
-#define  CAN_TI2R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT2R register  ******************/  
-#define  CAN_TDT2R_DLC                       0x0000000FU        /*!<Data Length Code      */
-#define  CAN_TDT2R_TGT                       0x00000100U        /*!<Transmit Global Time  */
-#define  CAN_TDT2R_TIME                      0xFFFF0000U        /*!<Message Time Stamp    */
-
-/*******************  Bit definition for CAN_TDL2R register  ******************/
-#define  CAN_TDL2R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_TDL2R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_TDL2R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_TDL2R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH2R register  ******************/
-#define  CAN_TDH2R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_TDH2R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_TDH2R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_TDH2R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI0R register  *******************/
-#define  CAN_RI0R_RTR                        0x00000002U        /*!<Remote Transmission Request                */
-#define  CAN_RI0R_IDE                        0x00000004U        /*!<Identifier Extension                       */
-#define  CAN_RI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier                        */
-#define  CAN_RI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT0R register  ******************/
-#define  CAN_RDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
-#define  CAN_RDT0R_FMI                       0x0000FF00U        /*!<Filter Match Index */
-#define  CAN_RDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL0R register  ******************/
-#define  CAN_RDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_RDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_RDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_RDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH0R register  ******************/
-#define  CAN_RDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_RDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_RDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_RDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI1R register  *******************/
-#define  CAN_RI1R_RTR                        0x00000002U        /*!<Remote Transmission Request                */
-#define  CAN_RI1R_IDE                        0x00000004U        /*!<Identifier Extension                       */
-#define  CAN_RI1R_EXID                       0x001FFFF8U        /*!<Extended identifier                        */
-#define  CAN_RI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT1R register  ******************/
-#define  CAN_RDT1R_DLC                       0x0000000FU        /*!<Data Length Code   */
-#define  CAN_RDT1R_FMI                       0x0000FF00U        /*!<Filter Match Index */
-#define  CAN_RDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL1R register  ******************/
-#define  CAN_RDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
-#define  CAN_RDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
-#define  CAN_RDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
-#define  CAN_RDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH1R register  ******************/
-#define  CAN_RDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
-#define  CAN_RDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
-#define  CAN_RDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
-#define  CAN_RDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
-
-/*!<CAN filter registers */
-/*******************  Bit definition for CAN_FMR register  ********************/
-#define  CAN_FMR_FINIT                       ((uint8_t)0x01U)               /*!<Filter Init Mode */
-#define  CAN_FMR_CAN2SB                      0x00003F00U        /*!<CAN2 start bank */
-
-/*******************  Bit definition for CAN_FM1R register  *******************/
-#define  CAN_FM1R_FBM                        0x3FFFU            /*!<Filter Mode */
-#define  CAN_FM1R_FBM0                       0x0001U            /*!<Filter Init Mode bit 0  */
-#define  CAN_FM1R_FBM1                       0x0002U            /*!<Filter Init Mode bit 1  */
-#define  CAN_FM1R_FBM2                       0x0004U            /*!<Filter Init Mode bit 2  */
-#define  CAN_FM1R_FBM3                       0x0008U            /*!<Filter Init Mode bit 3  */
-#define  CAN_FM1R_FBM4                       0x0010U            /*!<Filter Init Mode bit 4  */
-#define  CAN_FM1R_FBM5                       0x0020U            /*!<Filter Init Mode bit 5  */
-#define  CAN_FM1R_FBM6                       0x0040U            /*!<Filter Init Mode bit 6  */
-#define  CAN_FM1R_FBM7                       0x0080U            /*!<Filter Init Mode bit 7  */
-#define  CAN_FM1R_FBM8                       0x0100U            /*!<Filter Init Mode bit 8  */
-#define  CAN_FM1R_FBM9                       0x0200U            /*!<Filter Init Mode bit 9  */
-#define  CAN_FM1R_FBM10                      0x0400U            /*!<Filter Init Mode bit 10 */
-#define  CAN_FM1R_FBM11                      0x0800U            /*!<Filter Init Mode bit 11 */
-#define  CAN_FM1R_FBM12                      0x1000U            /*!<Filter Init Mode bit 12 */
-#define  CAN_FM1R_FBM13                      0x2000U            /*!<Filter Init Mode bit 13 */
-
-/*******************  Bit definition for CAN_FS1R register  *******************/
-#define  CAN_FS1R_FSC                        0x00003FFFU        /*!<Filter Scale Configuration        */
-#define  CAN_FS1R_FSC0                       0x00000001U        /*!<Filter Scale Configuration bit 0  */
-#define  CAN_FS1R_FSC1                       0x00000002U        /*!<Filter Scale Configuration bit 1  */
-#define  CAN_FS1R_FSC2                       0x00000004U        /*!<Filter Scale Configuration bit 2  */
-#define  CAN_FS1R_FSC3                       0x00000008U        /*!<Filter Scale Configuration bit 3  */
-#define  CAN_FS1R_FSC4                       0x00000010U        /*!<Filter Scale Configuration bit 4  */
-#define  CAN_FS1R_FSC5                       0x00000020U        /*!<Filter Scale Configuration bit 5  */
-#define  CAN_FS1R_FSC6                       0x00000040U        /*!<Filter Scale Configuration bit 6  */
-#define  CAN_FS1R_FSC7                       0x00000080U        /*!<Filter Scale Configuration bit 7  */
-#define  CAN_FS1R_FSC8                       0x00000100U        /*!<Filter Scale Configuration bit 8  */
-#define  CAN_FS1R_FSC9                       0x00000200U        /*!<Filter Scale Configuration bit 9  */
-#define  CAN_FS1R_FSC10                      0x00000400U        /*!<Filter Scale Configuration bit 10 */
-#define  CAN_FS1R_FSC11                      0x00000800U        /*!<Filter Scale Configuration bit 11 */
-#define  CAN_FS1R_FSC12                      0x00001000U        /*!<Filter Scale Configuration bit 12 */
-#define  CAN_FS1R_FSC13                      0x00002000U        /*!<Filter Scale Configuration bit 13 */
-
-/******************  Bit definition for CAN_FFA1R register  *******************/
-#define  CAN_FFA1R_FFA                       0x00003FFFU        /*!<Filter FIFO Assignment */
-#define  CAN_FFA1R_FFA0                      0x00000001U        /*!<Filter FIFO Assignment for Filter 0 */
-#define  CAN_FFA1R_FFA1                      0x00000002U        /*!<Filter FIFO Assignment for Filter 1 */
-#define  CAN_FFA1R_FFA2                      0x00000004U        /*!<Filter FIFO Assignment for Filter 2 */
-#define  CAN_FFA1R_FFA3                      0x00000008U        /*!<Filter FIFO Assignment for Filter 3 */
-#define  CAN_FFA1R_FFA4                      0x00000010U        /*!<Filter FIFO Assignment for Filter 4 */
-#define  CAN_FFA1R_FFA5                      0x00000020U        /*!<Filter FIFO Assignment for Filter 5 */
-#define  CAN_FFA1R_FFA6                      0x00000040U        /*!<Filter FIFO Assignment for Filter 6 */
-#define  CAN_FFA1R_FFA7                      0x00000080U        /*!<Filter FIFO Assignment for Filter 7 */
-#define  CAN_FFA1R_FFA8                      0x00000100U        /*!<Filter FIFO Assignment for Filter 8 */
-#define  CAN_FFA1R_FFA9                      0x00000200U        /*!<Filter FIFO Assignment for Filter 9 */
-#define  CAN_FFA1R_FFA10                     0x00000400U        /*!<Filter FIFO Assignment for Filter 10 */
-#define  CAN_FFA1R_FFA11                     0x00000800U        /*!<Filter FIFO Assignment for Filter 11 */
-#define  CAN_FFA1R_FFA12                     0x00001000U        /*!<Filter FIFO Assignment for Filter 12 */
-#define  CAN_FFA1R_FFA13                     0x00002000U        /*!<Filter FIFO Assignment for Filter 13 */
-
-/*******************  Bit definition for CAN_FA1R register  *******************/
-#define  CAN_FA1R_FACT                       0x00003FFFU        /*!<Filter Active    */
-#define  CAN_FA1R_FACT0                      0x00000001U        /*!<Filter 0 Active  */
-#define  CAN_FA1R_FACT1                      0x00000002U        /*!<Filter 1 Active  */
-#define  CAN_FA1R_FACT2                      0x00000004U        /*!<Filter 2 Active  */
-#define  CAN_FA1R_FACT3                      0x00000008U        /*!<Filter 3 Active  */
-#define  CAN_FA1R_FACT4                      0x00000010U        /*!<Filter 4 Active  */
-#define  CAN_FA1R_FACT5                      0x00000020U        /*!<Filter 5 Active  */
-#define  CAN_FA1R_FACT6                      0x00000040U        /*!<Filter 6 Active  */
-#define  CAN_FA1R_FACT7                      0x00000080U        /*!<Filter 7 Active  */
-#define  CAN_FA1R_FACT8                      0x00000100U        /*!<Filter 8 Active  */
-#define  CAN_FA1R_FACT9                      0x00000200U        /*!<Filter 9 Active  */
-#define  CAN_FA1R_FACT10                     0x00000400U        /*!<Filter 10 Active */
-#define  CAN_FA1R_FACT11                     0x00000800U        /*!<Filter 11 Active */
-#define  CAN_FA1R_FACT12                     0x00001000U        /*!<Filter 12 Active */
-#define  CAN_FA1R_FACT13                     0x00002000U        /*!<Filter 13 Active */
-
-/*******************  Bit definition for CAN_F0R1 register  *******************/
-#define  CAN_F0R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F0R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F0R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F0R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F0R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F0R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F0R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F0R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F0R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F0R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F0R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F0R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F0R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F0R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F0R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F0R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F0R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F0R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F0R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F0R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F0R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F0R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F0R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F0R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F0R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F0R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F0R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F0R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F0R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F0R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F0R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F0R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R1 register  *******************/
-#define  CAN_F1R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F1R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F1R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F1R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F1R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F1R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F1R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F1R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F1R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F1R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F1R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F1R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F1R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F1R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F1R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F1R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F1R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F1R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F1R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F1R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F1R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F1R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F1R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F1R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F1R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F1R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F1R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F1R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F1R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F1R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F1R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F1R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R1 register  *******************/
-#define  CAN_F2R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F2R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F2R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F2R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F2R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F2R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F2R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F2R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F2R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F2R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F2R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F2R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F2R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F2R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F2R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F2R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F2R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F2R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F2R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F2R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F2R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F2R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F2R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F2R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F2R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F2R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F2R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F2R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F2R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F2R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F2R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F2R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R1 register  *******************/
-#define  CAN_F3R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F3R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F3R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F3R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F3R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F3R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F3R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F3R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F3R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F3R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F3R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F3R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F3R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F3R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F3R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F3R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F3R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F3R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F3R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F3R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F3R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F3R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F3R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F3R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F3R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F3R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F3R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F3R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F3R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F3R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F3R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F3R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R1 register  *******************/
-#define  CAN_F4R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F4R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F4R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F4R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F4R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F4R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F4R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F4R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F4R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F4R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F4R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F4R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F4R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F4R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F4R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F4R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F4R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F4R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F4R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F4R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F4R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F4R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F4R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F4R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F4R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F4R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F4R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F4R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F4R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F4R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F4R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F4R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R1 register  *******************/
-#define  CAN_F5R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F5R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F5R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F5R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F5R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F5R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F5R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F5R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F5R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F5R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F5R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F5R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F5R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F5R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F5R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F5R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F5R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F5R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F5R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F5R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F5R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F5R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F5R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F5R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F5R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F5R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F5R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F5R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F5R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F5R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F5R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F5R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R1 register  *******************/
-#define  CAN_F6R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F6R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F6R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F6R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F6R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F6R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F6R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F6R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F6R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F6R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F6R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F6R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F6R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F6R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F6R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F6R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F6R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F6R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F6R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F6R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F6R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F6R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F6R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F6R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F6R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F6R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F6R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F6R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F6R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F6R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F6R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F6R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R1 register  *******************/
-#define  CAN_F7R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F7R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F7R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F7R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F7R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F7R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F7R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F7R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F7R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F7R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F7R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F7R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F7R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F7R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F7R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F7R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F7R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F7R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F7R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F7R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F7R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F7R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F7R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F7R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F7R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F7R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F7R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F7R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F7R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F7R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F7R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F7R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R1 register  *******************/
-#define  CAN_F8R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F8R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F8R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F8R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F8R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F8R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F8R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F8R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F8R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F8R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F8R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F8R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F8R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F8R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F8R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F8R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F8R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F8R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F8R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F8R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F8R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F8R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F8R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F8R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F8R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F8R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F8R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F8R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F8R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F8R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F8R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F8R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R1 register  *******************/
-#define  CAN_F9R1_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F9R1_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F9R1_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F9R1_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F9R1_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F9R1_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F9R1_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F9R1_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F9R1_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F9R1_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F9R1_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F9R1_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F9R1_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F9R1_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F9R1_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F9R1_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F9R1_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F9R1_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F9R1_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F9R1_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F9R1_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F9R1_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F9R1_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F9R1_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F9R1_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F9R1_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F9R1_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F9R1_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F9R1_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F9R1_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F9R1_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F9R1_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R1 register  ******************/
-#define  CAN_F10R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F10R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F10R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F10R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F10R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F10R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F10R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F10R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F10R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F10R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F10R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F10R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F10R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F10R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F10R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F10R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F10R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F10R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F10R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F10R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F10R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F10R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F10R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F10R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F10R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F10R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F10R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F10R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F10R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F10R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F10R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F10R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R1 register  ******************/
-#define  CAN_F11R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F11R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F11R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F11R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F11R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F11R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F11R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F11R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F11R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F11R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F11R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F11R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F11R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F11R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F11R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F11R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F11R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F11R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F11R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F11R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F11R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F11R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F11R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F11R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F11R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F11R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F11R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F11R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F11R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F11R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F11R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F11R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R1 register  ******************/
-#define  CAN_F12R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F12R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F12R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F12R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F12R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F12R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F12R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F12R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F12R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F12R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F12R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F12R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F12R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F12R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F12R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F12R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F12R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F12R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F12R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F12R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F12R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F12R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F12R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F12R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F12R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F12R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F12R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F12R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F12R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F12R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F12R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F12R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R1 register  ******************/
-#define  CAN_F13R1_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F13R1_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F13R1_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F13R1_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F13R1_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F13R1_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F13R1_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F13R1_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F13R1_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F13R1_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F13R1_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F13R1_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F13R1_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F13R1_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F13R1_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F13R1_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F13R1_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F13R1_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F13R1_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F13R1_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F13R1_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F13R1_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F13R1_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F13R1_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F13R1_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F13R1_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F13R1_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F13R1_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F13R1_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F13R1_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F13R1_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F13R1_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F0R2 register  *******************/
-#define  CAN_F0R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F0R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F0R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F0R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F0R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F0R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F0R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F0R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F0R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F0R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F0R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F0R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F0R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F0R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F0R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F0R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F0R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F0R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F0R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F0R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F0R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F0R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F0R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F0R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F0R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F0R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F0R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F0R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F0R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F0R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F0R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F0R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R2 register  *******************/
-#define  CAN_F1R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F1R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F1R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F1R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F1R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F1R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F1R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F1R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F1R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F1R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F1R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F1R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F1R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F1R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F1R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F1R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F1R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F1R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F1R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F1R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F1R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F1R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F1R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F1R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F1R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F1R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F1R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F1R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F1R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F1R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F1R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F1R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R2 register  *******************/
-#define  CAN_F2R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F2R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F2R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F2R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F2R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F2R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F2R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F2R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F2R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F2R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F2R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F2R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F2R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F2R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F2R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F2R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F2R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F2R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F2R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F2R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F2R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F2R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F2R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F2R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F2R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F2R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F2R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F2R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F2R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F2R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F2R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F2R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R2 register  *******************/
-#define  CAN_F3R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F3R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F3R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F3R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F3R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F3R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F3R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F3R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F3R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F3R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F3R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F3R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F3R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F3R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F3R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F3R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F3R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F3R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F3R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F3R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F3R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F3R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F3R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F3R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F3R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F3R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F3R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F3R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F3R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F3R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F3R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F3R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R2 register  *******************/
-#define  CAN_F4R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F4R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F4R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F4R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F4R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F4R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F4R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F4R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F4R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F4R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F4R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F4R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F4R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F4R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F4R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F4R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F4R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F4R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F4R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F4R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F4R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F4R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F4R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F4R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F4R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F4R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F4R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F4R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F4R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F4R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F4R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F4R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R2 register  *******************/
-#define  CAN_F5R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F5R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F5R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F5R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F5R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F5R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F5R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F5R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F5R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F5R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F5R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F5R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F5R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F5R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F5R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F5R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F5R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F5R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F5R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F5R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F5R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F5R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F5R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F5R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F5R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F5R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F5R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F5R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F5R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F5R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F5R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F5R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R2 register  *******************/
-#define  CAN_F6R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F6R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F6R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F6R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F6R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F6R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F6R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F6R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F6R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F6R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F6R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F6R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F6R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F6R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F6R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F6R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F6R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F6R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F6R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F6R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F6R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F6R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F6R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F6R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F6R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F6R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F6R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F6R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F6R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F6R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F6R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F6R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R2 register  *******************/
-#define  CAN_F7R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F7R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F7R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F7R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F7R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F7R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F7R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F7R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F7R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F7R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F7R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F7R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F7R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F7R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F7R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F7R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F7R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F7R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F7R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F7R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F7R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F7R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F7R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F7R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F7R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F7R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F7R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F7R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F7R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F7R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F7R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F7R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R2 register  *******************/
-#define  CAN_F8R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F8R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F8R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F8R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F8R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F8R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F8R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F8R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F8R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F8R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F8R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F8R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F8R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F8R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F8R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F8R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F8R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F8R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F8R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F8R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F8R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F8R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F8R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F8R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F8R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F8R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F8R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F8R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F8R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F8R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F8R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F8R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R2 register  *******************/
-#define  CAN_F9R2_FB0                        0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F9R2_FB1                        0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F9R2_FB2                        0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F9R2_FB3                        0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F9R2_FB4                        0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F9R2_FB5                        0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F9R2_FB6                        0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F9R2_FB7                        0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F9R2_FB8                        0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F9R2_FB9                        0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F9R2_FB10                       0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F9R2_FB11                       0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F9R2_FB12                       0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F9R2_FB13                       0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F9R2_FB14                       0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F9R2_FB15                       0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F9R2_FB16                       0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F9R2_FB17                       0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F9R2_FB18                       0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F9R2_FB19                       0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F9R2_FB20                       0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F9R2_FB21                       0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F9R2_FB22                       0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F9R2_FB23                       0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F9R2_FB24                       0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F9R2_FB25                       0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F9R2_FB26                       0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F9R2_FB27                       0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F9R2_FB28                       0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F9R2_FB29                       0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F9R2_FB30                       0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F9R2_FB31                       0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R2 register  ******************/
-#define  CAN_F10R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F10R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F10R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F10R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F10R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F10R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F10R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F10R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F10R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F10R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F10R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F10R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F10R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F10R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F10R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F10R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F10R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F10R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F10R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F10R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F10R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F10R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F10R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F10R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F10R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F10R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F10R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F10R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F10R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F10R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F10R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F10R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R2 register  ******************/
-#define  CAN_F11R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F11R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F11R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F11R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F11R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F11R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F11R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F11R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F11R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F11R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F11R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F11R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F11R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F11R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F11R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F11R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F11R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F11R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F11R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F11R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F11R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F11R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F11R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F11R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F11R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F11R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F11R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F11R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F11R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F11R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F11R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F11R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R2 register  ******************/
-#define  CAN_F12R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F12R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F12R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F12R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F12R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F12R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F12R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F12R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F12R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F12R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F12R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F12R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F12R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F12R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F12R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F12R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F12R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F12R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F12R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F12R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F12R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F12R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F12R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F12R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F12R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F12R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F12R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F12R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F12R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F12R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F12R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F12R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R2 register  ******************/
-#define  CAN_F13R2_FB0                       0x00000001U        /*!<Filter bit 0 */
-#define  CAN_F13R2_FB1                       0x00000002U        /*!<Filter bit 1 */
-#define  CAN_F13R2_FB2                       0x00000004U        /*!<Filter bit 2 */
-#define  CAN_F13R2_FB3                       0x00000008U        /*!<Filter bit 3 */
-#define  CAN_F13R2_FB4                       0x00000010U        /*!<Filter bit 4 */
-#define  CAN_F13R2_FB5                       0x00000020U        /*!<Filter bit 5 */
-#define  CAN_F13R2_FB6                       0x00000040U        /*!<Filter bit 6 */
-#define  CAN_F13R2_FB7                       0x00000080U        /*!<Filter bit 7 */
-#define  CAN_F13R2_FB8                       0x00000100U        /*!<Filter bit 8 */
-#define  CAN_F13R2_FB9                       0x00000200U        /*!<Filter bit 9 */
-#define  CAN_F13R2_FB10                      0x00000400U        /*!<Filter bit 10 */
-#define  CAN_F13R2_FB11                      0x00000800U        /*!<Filter bit 11 */
-#define  CAN_F13R2_FB12                      0x00001000U        /*!<Filter bit 12 */
-#define  CAN_F13R2_FB13                      0x00002000U        /*!<Filter bit 13 */
-#define  CAN_F13R2_FB14                      0x00004000U        /*!<Filter bit 14 */
-#define  CAN_F13R2_FB15                      0x00008000U        /*!<Filter bit 15 */
-#define  CAN_F13R2_FB16                      0x00010000U        /*!<Filter bit 16 */
-#define  CAN_F13R2_FB17                      0x00020000U        /*!<Filter bit 17 */
-#define  CAN_F13R2_FB18                      0x00040000U        /*!<Filter bit 18 */
-#define  CAN_F13R2_FB19                      0x00080000U        /*!<Filter bit 19 */
-#define  CAN_F13R2_FB20                      0x00100000U        /*!<Filter bit 20 */
-#define  CAN_F13R2_FB21                      0x00200000U        /*!<Filter bit 21 */
-#define  CAN_F13R2_FB22                      0x00400000U        /*!<Filter bit 22 */
-#define  CAN_F13R2_FB23                      0x00800000U        /*!<Filter bit 23 */
-#define  CAN_F13R2_FB24                      0x01000000U        /*!<Filter bit 24 */
-#define  CAN_F13R2_FB25                      0x02000000U        /*!<Filter bit 25 */
-#define  CAN_F13R2_FB26                      0x04000000U        /*!<Filter bit 26 */
-#define  CAN_F13R2_FB27                      0x08000000U        /*!<Filter bit 27 */
-#define  CAN_F13R2_FB28                      0x10000000U        /*!<Filter bit 28 */
-#define  CAN_F13R2_FB29                      0x20000000U        /*!<Filter bit 29 */
-#define  CAN_F13R2_FB30                      0x40000000U        /*!<Filter bit 30 */
-#define  CAN_F13R2_FB31                      0x80000000U        /*!<Filter bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 HDMI-CEC (CEC)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CEC_CR register  *********************/
-#define  CEC_CR_CECEN                        0x00000001U       /*!< CEC Enable                         */
-#define  CEC_CR_TXSOM                        0x00000002U       /*!< CEC Tx Start Of Message            */
-#define  CEC_CR_TXEOM                        0x00000004U       /*!< CEC Tx End Of Message              */
-
-/*******************  Bit definition for CEC_CFGR register  *******************/
-#define  CEC_CFGR_SFT                        0x00000007U       /*!< CEC Signal Free Time               */
-#define  CEC_CFGR_RXTOL                      0x00000008U       /*!< CEC Tolerance                      */
-#define  CEC_CFGR_BRESTP                     0x00000010U       /*!< CEC Rx Stop                        */
-#define  CEC_CFGR_BREGEN                     0x00000020U       /*!< CEC Bit Rising Error generation    */
-#define  CEC_CFGR_LBPEGEN                    0x00000040U       /*!< CEC Long Period Error generation   */
-#define  CEC_CFGR_BRDNOGEN                   0x00000080U       /*!< CEC Broadcast no Error generation  */
-#define  CEC_CFGR_SFTOPT                     0x00000100U       /*!< CEC Signal Free Time optional      */
-#define  CEC_CFGR_OAR                        0x7FFF0000U       /*!< CEC Own Address                    */
-#define  CEC_CFGR_LSTN                       0x80000000U       /*!< CEC Listen mode                    */
-
-/*******************  Bit definition for CEC_TXDR register  *******************/
-#define  CEC_TXDR_TXD                        0x000000FFU       /*!< CEC Tx Data                        */
-
-/*******************  Bit definition for CEC_RXDR register  *******************/
-#define  CEC_TXDR_RXD                        0x000000FFU       /*!< CEC Rx Data                        */
-
-/*******************  Bit definition for CEC_ISR register  ********************/
-#define  CEC_ISR_RXBR                        0x00000001U       /*!< CEC Rx-Byte Received                   */
-#define  CEC_ISR_RXEND                       0x00000002U       /*!< CEC End Of Reception                   */
-#define  CEC_ISR_RXOVR                       0x00000004U       /*!< CEC Rx-Overrun                         */
-#define  CEC_ISR_BRE                         0x00000008U       /*!< CEC Rx Bit Rising Error                */
-#define  CEC_ISR_SBPE                        0x00000010U       /*!< CEC Rx Short Bit period Error          */
-#define  CEC_ISR_LBPE                        0x00000020U       /*!< CEC Rx Long Bit period Error           */
-#define  CEC_ISR_RXACKE                      0x00000040U       /*!< CEC Rx Missing Acknowledge             */
-#define  CEC_ISR_ARBLST                      0x00000080U       /*!< CEC Arbitration Lost                   */
-#define  CEC_ISR_TXBR                        0x00000100U       /*!< CEC Tx Byte Request                    */
-#define  CEC_ISR_TXEND                       0x00000200U       /*!< CEC End of Transmission                */
-#define  CEC_ISR_TXUDR                       0x00000400U       /*!< CEC Tx-Buffer Underrun                 */
-#define  CEC_ISR_TXERR                       0x00000800U       /*!< CEC Tx-Error                           */
-#define  CEC_ISR_TXACKE                      0x00001000U       /*!< CEC Tx Missing Acknowledge             */
-
-/*******************  Bit definition for CEC_IER register  ********************/
-#define  CEC_IER_RXBRIE                      0x00000001U       /*!< CEC Rx-Byte Received IT Enable         */
-#define  CEC_IER_RXENDIE                     0x00000002U       /*!< CEC End Of Reception IT Enable         */
-#define  CEC_IER_RXOVRIE                     0x00000004U       /*!< CEC Rx-Overrun IT Enable               */
-#define  CEC_IER_BREIE                       0x00000008U       /*!< CEC Rx Bit Rising Error IT Enable      */
-#define  CEC_IER_SBPEIE                      0x00000010U       /*!< CEC Rx Short Bit period Error IT Enable*/
-#define  CEC_IER_LBPEIE                      0x00000020U       /*!< CEC Rx Long Bit period Error IT Enable */
-#define  CEC_IER_RXACKEIE                    0x00000040U       /*!< CEC Rx Missing Acknowledge IT Enable   */
-#define  CEC_IER_ARBLSTIE                    0x00000080U       /*!< CEC Arbitration Lost IT Enable         */
-#define  CEC_IER_TXBRIE                      0x00000100U       /*!< CEC Tx Byte Request  IT Enable         */
-#define  CEC_IER_TXENDIE                     0x00000200U       /*!< CEC End of Transmission IT Enable      */
-#define  CEC_IER_TXUDRIE                     0x00000400U       /*!< CEC Tx-Buffer Underrun IT Enable       */
-#define  CEC_IER_TXERRIE                     0x00000800U       /*!< CEC Tx-Error IT Enable                 */
-#define  CEC_IER_TXACKEIE                    0x00001000U       /*!< CEC Tx Missing Acknowledge IT Enable   */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRC calculation unit                              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           0xFFFFFFFFU     /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         0x000000FFU     /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        0x00000001U     /*!< RESET the CRC computation unit bit */
-#define  CRC_CR_POLYSIZE                     0x00000018U     /*!< Polynomial size bits               */
-#define  CRC_CR_POLYSIZE_0                   0x00000008U     /*!< Polynomial size bit 0              */
-#define  CRC_CR_POLYSIZE_1                   0x00000010U     /*!< Polynomial size bit 1              */
-#define  CRC_CR_REV_IN                       0x00000060U     /*!< REV_IN Reverse Input Data bits     */
-#define  CRC_CR_REV_IN_0                     0x00000020U     /*!< Bit 0 */
-#define  CRC_CR_REV_IN_1                     0x00000040U     /*!< Bit 1 */
-#define  CRC_CR_REV_OUT                      0x00000080U     /*!< REV_OUT Reverse Output Data bits   */
-
-/*******************  Bit definition for CRC_INIT register  *******************/
-#define  CRC_INIT_INIT                       0xFFFFFFFFU     /*!< Initial CRC value bits         */
-
-/*******************  Bit definition for CRC_POL register  ********************/
-#define  CRC_POL_POL                         0xFFFFFFFFU     /*!< Coefficients of the polynomial */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Digital to Analog Converter                           */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DAC_CR register  ********************/
-#define  DAC_CR_EN1                          0x00000001U        /*!<DAC channel1 enable                         */
-#define  DAC_CR_BOFF1                        0x00000002U        /*!<DAC channel1 output buffer disable          */
-#define  DAC_CR_TEN1                         0x00000004U        /*!<DAC channel1 Trigger enable                 */
-#define  DAC_CR_TSEL1                        0x00000038U        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define  DAC_CR_TSEL1_0                      0x00000008U        /*!<Bit 0 */
-#define  DAC_CR_TSEL1_1                      0x00000010U        /*!<Bit 1 */
-#define  DAC_CR_TSEL1_2                      0x00000020U        /*!<Bit 2 */
-#define  DAC_CR_WAVE1                        0x000000C0U        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enablEU) */
-#define  DAC_CR_WAVE1_0                      0x00000040U        /*!<Bit 0 */
-#define  DAC_CR_WAVE1_1                      0x00000080U        /*!<Bit 1 */
-#define  DAC_CR_MAMP1                        0x00000F00U        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP1_0                      0x00000100U        /*!<Bit 0 */
-#define  DAC_CR_MAMP1_1                      0x00000200U        /*!<Bit 1 */
-#define  DAC_CR_MAMP1_2                      0x00000400U        /*!<Bit 2 */
-#define  DAC_CR_MAMP1_3                      0x00000800U        /*!<Bit 3 */
-#define  DAC_CR_DMAEN1                       0x00001000U        /*!<DAC channel1 DMA enable                     */
-#define  DAC_CR_DMAUDRIE1                    0x00002000U        /*!<DAC channel1 DMA underrun interrupt enable  */
-#define  DAC_CR_EN2                          0x00010000U        /*!<DAC channel2 enable                         */
-#define  DAC_CR_BOFF2                        0x00020000U        /*!<DAC channel2 output buffer disable          */
-#define  DAC_CR_TEN2                         0x00040000U        /*!<DAC channel2 Trigger enable                 */
-#define  DAC_CR_TSEL2                        0x00380000U        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define  DAC_CR_TSEL2_0                      0x00080000U        /*!<Bit 0 */
-#define  DAC_CR_TSEL2_1                      0x00100000U        /*!<Bit 1 */
-#define  DAC_CR_TSEL2_2                      0x00200000U        /*!<Bit 2 */
-#define  DAC_CR_WAVE2                        0x00C00000U        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE2_0                      0x00400000U        /*!<Bit 0 */
-#define  DAC_CR_WAVE2_1                      0x00800000U        /*!<Bit 1 */
-#define  DAC_CR_MAMP2                        0x0F000000U        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP2_0                      0x01000000U        /*!<Bit 0 */
-#define  DAC_CR_MAMP2_1                      0x02000000U        /*!<Bit 1 */
-#define  DAC_CR_MAMP2_2                      0x04000000U        /*!<Bit 2 */
-#define  DAC_CR_MAMP2_3                      0x08000000U        /*!<Bit 3 */
-#define  DAC_CR_DMAEN2                       0x10000000U        /*!<DAC channel2 DMA enable                    */
-#define  DAC_CR_DMAUDRIE2                    0x20000000U        /*!<DAC channel2 DMA underrun interrupt enable */
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define  DAC_SWTRIGR_SWTRIG1                 0x01U               /*!<DAC channel1 software trigger */
-#define  DAC_SWTRIGR_SWTRIG2                 0x02U               /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define  DAC_DHR12R1_DACC1DHR                0x0FFFU            /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define  DAC_DHR12L1_DACC1DHR                0xFFF0U            /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define  DAC_DHR8R1_DACC1DHR                 0xFFU               /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define  DAC_DHR12R2_DACC2DHR                0x0FFFU            /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define  DAC_DHR12L2_DACC2DHR                0xFFF0U            /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define  DAC_DHR8R2_DACC2DHR                 0xFFU               /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define  DAC_DHR12RD_DACC1DHR                0x00000FFFU        /*!<DAC channel1 12-bit Right aligned data */
-#define  DAC_DHR12RD_DACC2DHR                0x0FFF0000U        /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define  DAC_DHR12LD_DACC1DHR                0x0000FFF0U        /*!<DAC channel1 12-bit Left aligned data */
-#define  DAC_DHR12LD_DACC2DHR                0xFFF00000U        /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define  DAC_DHR8RD_DACC1DHR                 0x00FFU            /*!<DAC channel1 8-bit Right aligned data */
-#define  DAC_DHR8RD_DACC2DHR                 0xFF00U            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define  DAC_DOR1_DACC1DOR                   0x0FFFU            /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define  DAC_DOR2_DACC2DOR                   0x0FFFU            /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define  DAC_SR_DMAUDR1                      0x00002000U        /*!<DAC channel1 DMA underrun flag */
-#define  DAC_SR_DMAUDR2                      0x20000000U        /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                 Digital Filter for Sigma Delta Modulators                  */
-/*                                                                            */
-/******************************************************************************/
-
-/****************   DFSDM channel configuration registers  ********************/
-
-/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/
-#define  DFSDM_CHCFGR1_DFSDMEN                0x80000000U            /*!< Global enable for DFSDM interface */
-#define  DFSDM_CHCFGR1_CKOUTSRC               0x40000000U            /*!< Output serial clock source selection */
-#define  DFSDM_CHCFGR1_CKOUTDIV               0x00FF0000U            /*!< CKOUTDIV[7:0] output serial clock divider */
-#define  DFSDM_CHCFGR1_DATPACK                0x0000C000U            /*!< DATPACK[1:0] Data packing mode */
-#define  DFSDM_CHCFGR1_DATPACK_1              0x00008000U            /*!< Data packing mode, Bit 1 */
-#define  DFSDM_CHCFGR1_DATPACK_0              0x00004000U            /*!< Data packing mode, Bit 0 */
-#define  DFSDM_CHCFGR1_DATMPX                 0x00003000U            /*!< DATMPX[1:0] Input data multiplexer for channel y */
-#define  DFSDM_CHCFGR1_DATMPX_1               0x00002000U            /*!< Input data multiplexer for channel y, Bit 1 */
-#define  DFSDM_CHCFGR1_DATMPX_0               0x00001000U            /*!< Input data multiplexer for channel y, Bit 0 */
-#define  DFSDM_CHCFGR1_CHINSEL                0x00000100U            /*!< Serial inputs selection for channel y */
-#define  DFSDM_CHCFGR1_CHEN                   0x00000080U            /*!< Channel y enable */
-#define  DFSDM_CHCFGR1_CKABEN                 0x00000040U            /*!< Clock absence detector enable on channel y */
-#define  DFSDM_CHCFGR1_SCDEN                  0x00000020U            /*!< Short circuit detector enable on channel y */
-#define  DFSDM_CHCFGR1_SPICKSEL               0x0000000CU            /*!< SPICKSEL[1:0] SPI clock select for channel y */
-#define  DFSDM_CHCFGR1_SPICKSEL_1             0x00000008U            /*!< SPI clock select for channel y, Bit 1 */
-#define  DFSDM_CHCFGR1_SPICKSEL_0             0x00000004U            /*!< SPI clock select for channel y, Bit 0 */
-#define  DFSDM_CHCFGR1_SITP                   0x00000003U            /*!< SITP[1:0] Serial interface type for channel y */
-#define  DFSDM_CHCFGR1_SITP_1                 0x00000002U            /*!< Serial interface type for channel y, Bit 1 */
-#define  DFSDM_CHCFGR1_SITP_0                 0x00000001U            /*!< Serial interface type for channel y, Bit 0 */
-
-/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/
-#define  DFSDM_CHCFGR2_OFFSET                 0xFFFFFF00U            /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
-#define  DFSDM_CHCFGR2_DTRBS                  0x000000F8U            /*!< DTRBS[4:0] Data right bit-shift for channel y */
-
-/******************  Bit definition for DFSDM_CHAWSCDR register *****************/
-#define  DFSDM_CHAWSCDR_AWFORD                0x00C00000U            /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
-#define  DFSDM_CHAWSCDR_AWFORD_1              0x00800000U            /*!< Analog watchdog Sinc filter order on channel y, Bit 1 */
-#define  DFSDM_CHAWSCDR_AWFORD_0              0x00400000U            /*!< Analog watchdog Sinc filter order on channel y, Bit 0 */
-#define  DFSDM_CHAWSCDR_AWFOSR                0x001F0000U            /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
-#define  DFSDM_CHAWSCDR_BKSCD                 0x0000F000U            /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
-#define  DFSDM_CHAWSCDR_SCDT                  0x000000FFU            /*!< SCDT[7:0] Short circuit detector threshold for channel y */
-
-/****************  Bit definition for DFSDM_CHWDATR register *******************/
-#define  DFSDM_CHWDATR_WDATA                  0x0000FFFFU            /*!< WDATA[15:0] Input channel y watchdog data */
-
-/****************  Bit definition for DFSDM_CHDATINR register *****************/
-#define  DFSDM_CHDATINR_INDAT0                0x0000FFFFU            /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
-#define  DFSDM_CHDATINR_INDAT1                0xFFFF0000U            /*!< INDAT0[15:0] Input data for channel y */
-
-/************************   DFSDM module registers  ****************************/
-
-/********************  Bit definition for DFSDM_FLTCR1 register *******************/
-#define  DFSDM_FLTCR1_AWFSEL                  0x40000000U            /*!< Analog watchdog fast mode select */
-#define  DFSDM_FLTCR1_FAST                    0x20000000U            /*!< Fast conversion mode selection */
-#define  DFSDM_FLTCR1_RCH                     0x07000000U            /*!< RCH[2:0] Regular channel selection */
-#define  DFSDM_FLTCR1_RDMAEN                  0x00200000U            /*!< DMA channel enabled to read data for the regular conversion */
-#define  DFSDM_FLTCR1_RSYNC                   0x00080000U            /*!< Launch regular conversion synchronously with DFSDMx */
-#define  DFSDM_FLTCR1_RCONT                   0x00040000U            /*!< Continuous mode selection for regular conversions */
-#define  DFSDM_FLTCR1_RSWSTART                0x00020000U            /*!< Software start of a conversion on the regular channel */
-#define  DFSDM_FLTCR1_JEXTEN                  0x00006000U            /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
-#define  DFSDM_FLTCR1_JEXTEN_1                0x00004000U            /*!< Trigger enable and trigger edge selection for injected conversions, Bit 1 */
-#define  DFSDM_FLTCR1_JEXTEN_0                0x00002000U            /*!< Trigger enable and trigger edge selection for injected conversions, Bit 0 */
-#define  DFSDM_FLTCR1_JEXTSEL                 0x00001F00U            /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */
-#define  DFSDM_FLTCR1_JEXTSEL_0               0x00000100U            /*!< Trigger signal selection for launching injected conversions, Bit 0 */
-#define  DFSDM_FLTCR1_JEXTSEL_1               0x00000200U            /*!< Trigger signal selection for launching injected conversions, Bit 1 */
-#define  DFSDM_FLTCR1_JEXTSEL_2               0x00000400U            /*!< Trigger signal selection for launching injected conversions, Bit 2 */
-#define  DFSDM_FLTCR1_JEXTSEL_3               0x00000800U            /*!< Trigger signal selection for launching injected conversions, Bit 3 */
-#define  DFSDM_FLTCR1_JEXTSEL_4               0x00001000U            /*!< Trigger signal selection for launching injected conversions, Bit 4 */
-#define  DFSDM_FLTCR1_JDMAEN                  0x00000020U            /*!< DMA channel enabled to read data for the injected channel group */
-#define  DFSDM_FLTCR1_JSCAN                   0x00000010U            /*!< Scanning conversion in continuous mode selection for injected conversions */
-#define  DFSDM_FLTCR1_JSYNC                   0x00000008U            /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */
-#define  DFSDM_FLTCR1_JSWSTART                0x00000002U            /*!< Start the conversion of the injected group of channels */
-#define  DFSDM_FLTCR1_DFEN                    0x00000001U            /*!< DFSDM enable */
-
-/********************  Bit definition for DFSDM_FLTCR2 register *******************/
-#define  DFSDM_FLTCR2_AWDCH                   0x00FF0000U            /*!< AWDCH[7:0] Analog watchdog channel selection */
-#define  DFSDM_FLTCR2_EXCH                    0x0000FF00U            /*!< EXCH[7:0] Extreme detector channel selection */
-#define  DFSDM_FLTCR2_CKABIE                  0x00000040U            /*!< Clock absence interrupt enable */
-#define  DFSDM_FLTCR2_SCDIE                   0x00000020U            /*!< Short circuit detector interrupt enable */
-#define  DFSDM_FLTCR2_AWDIE                   0x00000010U            /*!< Analog watchdog interrupt enable */
-#define  DFSDM_FLTCR2_ROVRIE                  0x00000008U            /*!< Regular data overrun interrupt enable */
-#define  DFSDM_FLTCR2_JOVRIE                  0x00000004U            /*!< Injected data overrun interrupt enable */
-#define  DFSDM_FLTCR2_REOCIE                  0x00000002U            /*!< Regular end of conversion interrupt enable */
-#define  DFSDM_FLTCR2_JEOCIE                  0x00000001U            /*!< Injected end of conversion interrupt enable */
-
-/********************  Bit definition for DFSDM_FLTISR register *******************/
-#define  DFSDM_FLTISR_SCDF                    0xFF000000U            /*!< SCDF[7:0] Short circuit detector flag */
-#define  DFSDM_FLTISR_CKABF                   0x00FF0000U            /*!< CKABF[7:0] Clock absence flag */
-#define  DFSDM_FLTISR_RCIP                    0x00004000U            /*!< Regular conversion in progress status */
-#define  DFSDM_FLTISR_JCIP                    0x00002000U            /*!< Injected conversion in progress status */
-#define  DFSDM_FLTISR_AWDF                    0x00000010U            /*!< Analog watchdog */
-#define  DFSDM_FLTISR_ROVRF                   0x00000008U            /*!< Regular conversion overrun flag */
-#define  DFSDM_FLTISR_JOVRF                   0x00000004U            /*!< Injected conversion overrun flag */
-#define  DFSDM_FLTISR_REOCF                   0x00000002U            /*!< End of regular conversion flag */
-#define  DFSDM_FLTISR_JEOCF                   0x00000001U            /*!< End of injected conversion flag */
-
-/********************  Bit definition for DFSDM_FLTICR register *******************/
-#define  DFSDM_FLTICR_CLRSCSDF                0xFF000000U            /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
-#define  DFSDM_FLTICR_CLRCKABF                0x00FF0000U            /*!< CLRCKABF[7:0] Clear the clock absence flag */
-#define  DFSDM_FLTICR_CLRROVRF                0x00000008U            /*!< Clear the regular conversion overrun flag */
-#define  DFSDM_FLTICR_CLRJOVRF                0x00000004U            /*!< Clear the injected conversion overrun flag */
-
-/*******************  Bit definition for DFSDM_FLTJCHGR register ******************/
-#define  DFSDM_FLTJCHGR_JCHG                  0x000000FFU            /*!< JCHG[7:0] Injected channel group selection */
-
-/********************  Bit definition for DFSDM_FLTFCR register *******************/
-#define  DFSDM_FLTFCR_FORD                    0xE0000000U            /*!< FORD[2:0] Sinc filter order */
-#define  DFSDM_FLTFCR_FORD_2                  0x80000000U            /*!< Sinc filter order, Bit 2 */
-#define  DFSDM_FLTFCR_FORD_1                  0x40000000U            /*!< Sinc filter order, Bit 1 */
-#define  DFSDM_FLTFCR_FORD_0                  0x20000000U            /*!< Sinc filter order, Bit 0 */
-#define  DFSDM_FLTFCR_FOSR                    0x03FF0000U            /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
-#define  DFSDM_FLTFCR_IOSR                    0x000000FFU            /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
-
-/******************  Bit definition for DFSDM_FLTJDATAR register *****************/
-#define  DFSDM_FLTJDATAR_JDATA                0xFFFFFF00U            /*!< JDATA[23:0] Injected group conversion data */
-#define  DFSDM_FLTJDATAR_JDATACH              0x00000007U            /*!< JDATACH[2:0] Injected channel most recently converted */
-
-/******************  Bit definition for DFSDM_FLTRDATAR register *****************/
-#define  DFSDM_FLTRDATAR_RDATA                0xFFFFFF00U            /*!< RDATA[23:0] Regular channel conversion data */
-#define  DFSDM_FLTRDATAR_RPEND                0x00000010U            /*!< RPEND Regular channel pending data */
-#define  DFSDM_FLTRDATAR_RDATACH              0x00000007U            /*!< RDATACH[2:0] Regular channel most recently converted */
-
-/******************  Bit definition for DFSDM_FLTAWHTR register ******************/
-#define  DFSDM_FLTAWHTR_AWHT                  0xFFFFFF00U             /*!< AWHT[23:0] Analog watchdog high threshold */
-#define  DFSDM_FLTAWHTR_BKAWH                 0x0000000FU             /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
-
-/******************  Bit definition for DFSDM_FLTAWLTR register ******************/
-#define  DFSDM_FLTAWLTR_AWLT                  0xFFFFFF00U             /*!< AWLT[23:0] Analog watchdog low threshold */
-#define  DFSDM_FLTAWLTR_BKAWL                 0x0000000FU             /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
-
-/******************  Bit definition for DFSDM_FLTAWSR register ******************/
-#define  DFSDM_FLTAWSR_AWHTF                  0x0000FF00U             /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
-#define  DFSDM_FLTAWSR_AWLTF                  0x000000FFU             /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
-
-/******************  Bit definition for DFSDM_FLTAWCFR register *****************/
-#define  DFSDM_FLTAWCFR_CLRAWHTF              0x0000FF00U             /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
-#define  DFSDM_FLTAWCFR_CLRAWLTF              0x000000FFU             /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
-
-/******************  Bit definition for DFSDM_FLTEXMAX register ******************/
-#define  DFSDM_FLTEXMAX_EXMAX                 0xFFFFFF00U             /*!< EXMAX[23:0] Extreme detector maximum value */
-#define  DFSDM_FLTEXMAX_EXMAXCH               0x00000007U             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
-
-/******************  Bit definition for DFSDM_FLTEXMIN register ******************/
-#define  DFSDM_FLTEXMIN_EXMIN                 0xFFFFFF00U             /*!< EXMIN[23:0] Extreme detector minimum value */
-#define  DFSDM_FLTEXMIN_EXMINCH               0x00000007U             /*!< EXMINCH[2:0] Extreme detector minimum data channel */
-
-/******************  Bit definition for DFSDM_FLTCNVTIMR register ******************/
-#define  DFSDM_FLTCNVTIMR_CNVCNT              0xFFFFFFF0U             /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 Debug MCU                                  */
-/*                                                                            */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    DCMI                                    */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DCMI_CR register  ******************/
-#define DCMI_CR_CAPTURE                      0x00000001U
-#define DCMI_CR_CM                           0x00000002U
-#define DCMI_CR_CROP                         0x00000004U
-#define DCMI_CR_JPEG                         0x00000008U
-#define DCMI_CR_ESS                          0x00000010U
-#define DCMI_CR_PCKPOL                       0x00000020U
-#define DCMI_CR_HSPOL                        0x00000040U
-#define DCMI_CR_VSPOL                        0x00000080U
-#define DCMI_CR_FCRC_0                       0x00000100U
-#define DCMI_CR_FCRC_1                       0x00000200U
-#define DCMI_CR_EDM_0                        0x00000400U
-#define DCMI_CR_EDM_1                        0x00000800U
-#define DCMI_CR_CRE                          0x00001000U
-#define DCMI_CR_ENABLE                       0x00004000U
-#define DCMI_CR_BSM                          0x00030000U
-#define DCMI_CR_BSM_0                        0x00010000U
-#define DCMI_CR_BSM_1                        0x00020000U
-#define DCMI_CR_OEBS                         0x00040000U
-#define DCMI_CR_LSM                          0x00080000U
-#define DCMI_CR_OELS                         0x00100000U
-
-/********************  Bits definition for DCMI_SR register  ******************/
-#define DCMI_SR_HSYNC                        0x00000001U
-#define DCMI_SR_VSYNC                        0x00000002U
-#define DCMI_SR_FNE                          0x00000004U
-
-/********************  Bits definition for DCMI_RIS register   ****************/
-#define DCMI_RIS_FRAME_RIS                   0x00000001U
-#define DCMI_RIS_OVR_RIS                     0x00000002U
-#define DCMI_RIS_ERR_RIS                     0x00000004U
-#define DCMI_RIS_VSYNC_RIS                   0x00000008U
-#define DCMI_RIS_LINE_RIS                    0x00000010U
-
-/* Legacy defines */
-#define DCMI_RISR_FRAME_RIS                  DCMI_RIS_FRAME_RIS
-#define DCMI_RISR_OVF_RIS                    DCMI_RIS_OVR_RIS
-#define DCMI_RISR_ERR_RIS                    DCMI_RIS_ERR_RIS
-#define DCMI_RISR_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS
-#define DCMI_RISR_LINE_RIS                   DCMI_RIS_LINE_RIS
-
-/********************  Bits definition for DCMI_IER register  *****************/
-#define DCMI_IER_FRAME_IE                    0x00000001U
-#define DCMI_IER_OVR_IE                      0x00000002U
-#define DCMI_IER_ERR_IE                      0x00000004U
-#define DCMI_IER_VSYNC_IE                    0x00000008U
-#define DCMI_IER_LINE_IE                     0x00000010U
-
-
-/********************  Bits definition for DCMI_MIS register  *****************/
-#define DCMI_MIS_FRAME_MIS                   0x00000001U
-#define DCMI_MIS_OVR_MIS                     0x00000002U
-#define DCMI_MIS_ERR_MIS                     0x00000004U
-#define DCMI_MIS_VSYNC_MIS                   0x00000008U
-#define DCMI_MIS_LINE_MIS                    0x00000010U
-
-
-/********************  Bits definition for DCMI_ICR register  *****************/
-#define DCMI_ICR_FRAME_ISC                   0x00000001U
-#define DCMI_ICR_OVR_ISC                     0x00000002U
-#define DCMI_ICR_ERR_ISC                     0x00000004U
-#define DCMI_ICR_VSYNC_ISC                   0x00000008U
-#define DCMI_ICR_LINE_ISC                    0x00000010U
-
-
-/********************  Bits definition for DCMI_ESCR register  ******************/
-#define DCMI_ESCR_FSC                        0x000000FFU
-#define DCMI_ESCR_LSC                        0x0000FF00U
-#define DCMI_ESCR_LEC                        0x00FF0000U
-#define DCMI_ESCR_FEC                        0xFF000000U
-
-/********************  Bits definition for DCMI_ESUR register  ******************/
-#define DCMI_ESUR_FSU                        0x000000FFU
-#define DCMI_ESUR_LSU                        0x0000FF00U
-#define DCMI_ESUR_LEU                        0x00FF0000U
-#define DCMI_ESUR_FEU                        0xFF000000U
-
-/********************  Bits definition for DCMI_CWSTRT register  ******************/
-#define DCMI_CWSTRT_HOFFCNT                  0x00003FFFU
-#define DCMI_CWSTRT_VST                      0x1FFF0000U
-
-/********************  Bits definition for DCMI_CWSIZE register  ******************/
-#define DCMI_CWSIZE_CAPCNT                   0x00003FFFU
-#define DCMI_CWSIZE_VLINE                    0x3FFF0000U
-
-/********************  Bits definition for DCMI_DR register  ******************/
-#define DCMI_DR_BYTE0                        0x000000FFU
-#define DCMI_DR_BYTE1                        0x0000FF00U
-#define DCMI_DR_BYTE2                        0x00FF0000U
-#define DCMI_DR_BYTE3                        0xFF000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                             DMA Controller                                 */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DMA_SxCR register  *****************/ 
-#define DMA_SxCR_CHSEL                       0x1E000000U
-#define DMA_SxCR_CHSEL_0                     0x02000000U
-#define DMA_SxCR_CHSEL_1                     0x04000000U
-#define DMA_SxCR_CHSEL_2                     0x08000000U 
-#define DMA_SxCR_CHSEL_3                     0x10000000U
-#define DMA_SxCR_MBURST                      0x01800000U
-#define DMA_SxCR_MBURST_0                    0x00800000U
-#define DMA_SxCR_MBURST_1                    0x01000000U
-#define DMA_SxCR_PBURST                      0x00600000U
-#define DMA_SxCR_PBURST_0                    0x00200000U
-#define DMA_SxCR_PBURST_1                    0x00400000U
-#define DMA_SxCR_CT                          0x00080000U  
-#define DMA_SxCR_DBM                         0x00040000U
-#define DMA_SxCR_PL                          0x00030000U
-#define DMA_SxCR_PL_0                        0x00010000U
-#define DMA_SxCR_PL_1                        0x00020000U
-#define DMA_SxCR_PINCOS                      0x00008000U
-#define DMA_SxCR_MSIZE                       0x00006000U
-#define DMA_SxCR_MSIZE_0                     0x00002000U
-#define DMA_SxCR_MSIZE_1                     0x00004000U
-#define DMA_SxCR_PSIZE                       0x00001800U
-#define DMA_SxCR_PSIZE_0                     0x00000800U
-#define DMA_SxCR_PSIZE_1                     0x00001000U
-#define DMA_SxCR_MINC                        0x00000400U
-#define DMA_SxCR_PINC                        0x00000200U
-#define DMA_SxCR_CIRC                        0x00000100U
-#define DMA_SxCR_DIR                         0x000000C0U
-#define DMA_SxCR_DIR_0                       0x00000040U
-#define DMA_SxCR_DIR_1                       0x00000080U
-#define DMA_SxCR_PFCTRL                      0x00000020U
-#define DMA_SxCR_TCIE                        0x00000010U
-#define DMA_SxCR_HTIE                        0x00000008U
-#define DMA_SxCR_TEIE                        0x00000004U
-#define DMA_SxCR_DMEIE                       0x00000002U
-#define DMA_SxCR_EN                          0x00000001U
-
-/********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            0x0000FFFFU
-#define DMA_SxNDT_0                          0x00000001U
-#define DMA_SxNDT_1                          0x00000002U
-#define DMA_SxNDT_2                          0x00000004U
-#define DMA_SxNDT_3                          0x00000008U
-#define DMA_SxNDT_4                          0x00000010U
-#define DMA_SxNDT_5                          0x00000020U
-#define DMA_SxNDT_6                          0x00000040U
-#define DMA_SxNDT_7                          0x00000080U
-#define DMA_SxNDT_8                          0x00000100U
-#define DMA_SxNDT_9                          0x00000200U
-#define DMA_SxNDT_10                         0x00000400U
-#define DMA_SxNDT_11                         0x00000800U
-#define DMA_SxNDT_12                         0x00001000U
-#define DMA_SxNDT_13                         0x00002000U
-#define DMA_SxNDT_14                         0x00004000U
-#define DMA_SxNDT_15                         0x00008000U
-
-/********************  Bits definition for DMA_SxFCR register  ****************/ 
-#define DMA_SxFCR_FEIE                       0x00000080U
-#define DMA_SxFCR_FS                         0x00000038U
-#define DMA_SxFCR_FS_0                       0x00000008U
-#define DMA_SxFCR_FS_1                       0x00000010U
-#define DMA_SxFCR_FS_2                       0x00000020U
-#define DMA_SxFCR_DMDIS                      0x00000004U
-#define DMA_SxFCR_FTH                        0x00000003U
-#define DMA_SxFCR_FTH_0                      0x00000001U
-#define DMA_SxFCR_FTH_1                      0x00000002U
-
-/********************  Bits definition for DMA_LISR register  *****************/ 
-#define DMA_LISR_TCIF3                       0x08000000U
-#define DMA_LISR_HTIF3                       0x04000000U
-#define DMA_LISR_TEIF3                       0x02000000U
-#define DMA_LISR_DMEIF3                      0x01000000U
-#define DMA_LISR_FEIF3                       0x00400000U
-#define DMA_LISR_TCIF2                       0x00200000U
-#define DMA_LISR_HTIF2                       0x00100000U
-#define DMA_LISR_TEIF2                       0x00080000U
-#define DMA_LISR_DMEIF2                      0x00040000U
-#define DMA_LISR_FEIF2                       0x00010000U
-#define DMA_LISR_TCIF1                       0x00000800U
-#define DMA_LISR_HTIF1                       0x00000400U
-#define DMA_LISR_TEIF1                       0x00000200U
-#define DMA_LISR_DMEIF1                      0x00000100U
-#define DMA_LISR_FEIF1                       0x00000040U
-#define DMA_LISR_TCIF0                       0x00000020U
-#define DMA_LISR_HTIF0                       0x00000010U
-#define DMA_LISR_TEIF0                       0x00000008U
-#define DMA_LISR_DMEIF0                      0x00000004U
-#define DMA_LISR_FEIF0                       0x00000001U
-
-/********************  Bits definition for DMA_HISR register  *****************/ 
-#define DMA_HISR_TCIF7                       0x08000000U
-#define DMA_HISR_HTIF7                       0x04000000U
-#define DMA_HISR_TEIF7                       0x02000000U
-#define DMA_HISR_DMEIF7                      0x01000000U
-#define DMA_HISR_FEIF7                       0x00400000U
-#define DMA_HISR_TCIF6                       0x00200000U
-#define DMA_HISR_HTIF6                       0x00100000U
-#define DMA_HISR_TEIF6                       0x00080000U
-#define DMA_HISR_DMEIF6                      0x00040000U
-#define DMA_HISR_FEIF6                       0x00010000U
-#define DMA_HISR_TCIF5                       0x00000800U
-#define DMA_HISR_HTIF5                       0x00000400U
-#define DMA_HISR_TEIF5                       0x00000200U
-#define DMA_HISR_DMEIF5                      0x00000100U
-#define DMA_HISR_FEIF5                       0x00000040U
-#define DMA_HISR_TCIF4                       0x00000020U
-#define DMA_HISR_HTIF4                       0x00000010U
-#define DMA_HISR_TEIF4                       0x00000008U
-#define DMA_HISR_DMEIF4                      0x00000004U
-#define DMA_HISR_FEIF4                       0x00000001U
-
-/********************  Bits definition for DMA_LIFCR register  ****************/ 
-#define DMA_LIFCR_CTCIF3                     0x08000000U
-#define DMA_LIFCR_CHTIF3                     0x04000000U
-#define DMA_LIFCR_CTEIF3                     0x02000000U
-#define DMA_LIFCR_CDMEIF3                    0x01000000U
-#define DMA_LIFCR_CFEIF3                     0x00400000U
-#define DMA_LIFCR_CTCIF2                     0x00200000U
-#define DMA_LIFCR_CHTIF2                     0x00100000U
-#define DMA_LIFCR_CTEIF2                     0x00080000U
-#define DMA_LIFCR_CDMEIF2                    0x00040000U
-#define DMA_LIFCR_CFEIF2                     0x00010000U
-#define DMA_LIFCR_CTCIF1                     0x00000800U
-#define DMA_LIFCR_CHTIF1                     0x00000400U
-#define DMA_LIFCR_CTEIF1                     0x00000200U
-#define DMA_LIFCR_CDMEIF1                    0x00000100U
-#define DMA_LIFCR_CFEIF1                     0x00000040U
-#define DMA_LIFCR_CTCIF0                     0x00000020U
-#define DMA_LIFCR_CHTIF0                     0x00000010U
-#define DMA_LIFCR_CTEIF0                     0x00000008U
-#define DMA_LIFCR_CDMEIF0                    0x00000004U
-#define DMA_LIFCR_CFEIF0                     0x00000001U
-
-/********************  Bits definition for DMA_HIFCR  register  ****************/ 
-#define DMA_HIFCR_CTCIF7                     0x08000000U
-#define DMA_HIFCR_CHTIF7                     0x04000000U
-#define DMA_HIFCR_CTEIF7                     0x02000000U
-#define DMA_HIFCR_CDMEIF7                    0x01000000U
-#define DMA_HIFCR_CFEIF7                     0x00400000U
-#define DMA_HIFCR_CTCIF6                     0x00200000U
-#define DMA_HIFCR_CHTIF6                     0x00100000U
-#define DMA_HIFCR_CTEIF6                     0x00080000U
-#define DMA_HIFCR_CDMEIF6                    0x00040000U
-#define DMA_HIFCR_CFEIF6                     0x00010000U
-#define DMA_HIFCR_CTCIF5                     0x00000800U
-#define DMA_HIFCR_CHTIF5                     0x00000400U
-#define DMA_HIFCR_CTEIF5                     0x00000200U
-#define DMA_HIFCR_CDMEIF5                    0x00000100U
-#define DMA_HIFCR_CFEIF5                     0x00000040U
-#define DMA_HIFCR_CTCIF4                     0x00000020U
-#define DMA_HIFCR_CHTIF4                     0x00000010U
-#define DMA_HIFCR_CTEIF4                     0x00000008U
-#define DMA_HIFCR_CDMEIF4                    0x00000004U
-#define DMA_HIFCR_CFEIF4                     0x00000001U
-
-/******************************************************************************/
-/*                                                                            */
-/*                         AHB Master DMA2D Controller (DMA2D)                */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for DMA2D_CR register  ******************/
-
-#define DMA2D_CR_START                     0x00000001U               /*!< Start transfer                          */
-#define DMA2D_CR_SUSP                      0x00000002U               /*!< Suspend transfer                        */
-#define DMA2D_CR_ABORT                     0x00000004U               /*!< Abort transfer                          */
-#define DMA2D_CR_TEIE                      0x00000100U               /*!< Transfer Error Interrupt Enable         */
-#define DMA2D_CR_TCIE                      0x00000200U               /*!< Transfer Complete Interrupt Enable      */
-#define DMA2D_CR_TWIE                      0x00000400U               /*!< Transfer Watermark Interrupt Enable     */
-#define DMA2D_CR_CAEIE                     0x00000800U               /*!< CLUT Access Error Interrupt Enable      */
-#define DMA2D_CR_CTCIE                     0x00001000U               /*!< CLUT Transfer Complete Interrupt Enable */
-#define DMA2D_CR_CEIE                      0x00002000U               /*!< Configuration Error Interrupt Enable    */
-#define DMA2D_CR_MODE                      0x00030000U               /*!< DMA2D Mode[1:0]                         */
-#define DMA2D_CR_MODE_0                    0x00010000U               /*!< DMA2D Mode bit 0                        */
-#define DMA2D_CR_MODE_1                    0x00020000U               /*!< DMA2D Mode bit 1                        */
-
-/********************  Bit definition for DMA2D_ISR register  *****************/
-
-#define DMA2D_ISR_TEIF                     0x00000001U               /*!< Transfer Error Interrupt Flag         */
-#define DMA2D_ISR_TCIF                     0x00000002U               /*!< Transfer Complete Interrupt Flag      */
-#define DMA2D_ISR_TWIF                     0x00000004U               /*!< Transfer Watermark Interrupt Flag     */
-#define DMA2D_ISR_CAEIF                    0x00000008U               /*!< CLUT Access Error Interrupt Flag      */
-#define DMA2D_ISR_CTCIF                    0x00000010U               /*!< CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_ISR_CEIF                     0x00000020U               /*!< Configuration Error Interrupt Flag    */
-
-/********************  Bit definition for DMA2D_IFCR register  ****************/
-
-#define DMA2D_IFCR_CTEIF                   0x00000001U               /*!< Clears Transfer Error Interrupt Flag         */
-#define DMA2D_IFCR_CTCIF                   0x00000002U               /*!< Clears Transfer Complete Interrupt Flag      */
-#define DMA2D_IFCR_CTWIF                   0x00000004U               /*!< Clears Transfer Watermark Interrupt Flag     */
-#define DMA2D_IFCR_CAECIF                  0x00000008U               /*!< Clears CLUT Access Error Interrupt Flag      */
-#define DMA2D_IFCR_CCTCIF                  0x00000010U               /*!< Clears CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_IFCR_CCEIF                   0x00000020U               /*!< Clears Configuration Error Interrupt Flag    */
-
-/* Legacy defines */
-#define DMA2D_IFSR_CTEIF                   DMA2D_IFCR_CTEIF                     /*!< Clears Transfer Error Interrupt Flag         */
-#define DMA2D_IFSR_CTCIF                   DMA2D_IFCR_CTCIF                     /*!< Clears Transfer Complete Interrupt Flag      */
-#define DMA2D_IFSR_CTWIF                   DMA2D_IFCR_CTWIF                     /*!< Clears Transfer Watermark Interrupt Flag     */
-#define DMA2D_IFSR_CCAEIF                  DMA2D_IFCR_CAECIF                    /*!< Clears CLUT Access Error Interrupt Flag      */
-#define DMA2D_IFSR_CCTCIF                  DMA2D_IFCR_CCTCIF                    /*!< Clears CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_IFSR_CCEIF                   DMA2D_IFCR_CCEIF                     /*!< Clears Configuration Error Interrupt Flag    */
-
-/********************  Bit definition for DMA2D_FGMAR register  ***************/
-
-#define DMA2D_FGMAR_MA                     0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_FGOR register  ****************/
-
-#define DMA2D_FGOR_LO                      0x00003FFFU               /*!< Line Offset */
-
-/********************  Bit definition for DMA2D_BGMAR register  ***************/
-
-#define DMA2D_BGMAR_MA                     0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_BGOR register  ****************/
-
-#define DMA2D_BGOR_LO                      0x00003FFFU               /*!< Line Offset */
-
-/********************  Bit definition for DMA2D_FGPFCCR register  *************/
-
-#define DMA2D_FGPFCCR_CM                   0x0000000FU               /*!< Input color mode CM[3:0] */
-#define DMA2D_FGPFCCR_CM_0                 0x00000001U               /*!< Input color mode CM bit 0 */
-#define DMA2D_FGPFCCR_CM_1                 0x00000002U               /*!< Input color mode CM bit 1 */
-#define DMA2D_FGPFCCR_CM_2                 0x00000004U               /*!< Input color mode CM bit 2 */
-#define DMA2D_FGPFCCR_CM_3                 0x00000008U               /*!< Input color mode CM bit 3 */
-#define DMA2D_FGPFCCR_CCM                  0x00000010U               /*!< CLUT Color mode */
-#define DMA2D_FGPFCCR_START                0x00000020U               /*!< Start */
-#define DMA2D_FGPFCCR_CS                   0x0000FF00U               /*!< CLUT size */
-#define DMA2D_FGPFCCR_AM                   0x00030000U               /*!< Alpha mode AM[1:0] */
-#define DMA2D_FGPFCCR_AM_0                 0x00010000U               /*!< Alpha mode AM bit 0 */
-#define DMA2D_FGPFCCR_AM_1                 0x00020000U               /*!< Alpha mode AM bit 1 */
-#define DMA2D_FGPFCCR_AI                   0x00100000U               /*!< Foreground Input Alpha Inverted */
-#define DMA2D_FGPFCCR_RBS                  0x00200000U               /*!< Foreground Input Red Blue Swap */
-#define DMA2D_FGPFCCR_ALPHA                0xFF000000U               /*!< Alpha value */
-
-/********************  Bit definition for DMA2D_FGCOLR register  **************/
-
-#define DMA2D_FGCOLR_BLUE                  0x000000FFU               /*!< Blue Value */
-#define DMA2D_FGCOLR_GREEN                 0x0000FF00U               /*!< Green Value */
-#define DMA2D_FGCOLR_RED                   0x00FF0000U               /*!< Red Value */   
-
-/********************  Bit definition for DMA2D_BGPFCCR register  *************/
-
-#define DMA2D_BGPFCCR_CM                   0x0000000FU               /*!< Input color mode CM[3:0] */
-#define DMA2D_BGPFCCR_CM_0                 0x00000001U               /*!< Input color mode CM bit 0 */
-#define DMA2D_BGPFCCR_CM_1                 0x00000002U               /*!< Input color mode CM bit 1 */
-#define DMA2D_BGPFCCR_CM_2                 0x00000004U               /*!< Input color mode CM bit 2 */
-#define DMA2D_FGPFCCR_CM_3                 0x00000008U               /*!< Input color mode CM bit 3 */
-#define DMA2D_BGPFCCR_CCM                  0x00000010U               /*!< CLUT Color mode */
-#define DMA2D_BGPFCCR_START                0x00000020U               /*!< Start */
-#define DMA2D_BGPFCCR_CS                   0x0000FF00U               /*!< CLUT size */
-#define DMA2D_BGPFCCR_AM                   0x00030000U               /*!< Alpha mode AM[1:0] */
-#define DMA2D_BGPFCCR_AM_0                 0x00010000U               /*!< Alpha mode AM bit 0 */
-#define DMA2D_BGPFCCR_AM_1                 0x00020000U               /*!< Alpha mode AM bit 1 */
-#define DMA2D_BGPFCCR_AI                   0x00100000U               /*!< background Input Alpha Inverted */
-#define DMA2D_BGPFCCR_RBS                  0x00200000U               /*!< Background Input Red Blue Swap */
-#define DMA2D_BGPFCCR_ALPHA                0xFF000000U               /*!< background Input Alpha value */
-
-/********************  Bit definition for DMA2D_BGCOLR register  **************/
-
-#define DMA2D_BGCOLR_BLUE                  0x000000FFU               /*!< Blue Value */
-#define DMA2D_BGCOLR_GREEN                 0x0000FF00U               /*!< Green Value */
-#define DMA2D_BGCOLR_RED                   0x00FF0000U               /*!< Red Value */
-
-/********************  Bit definition for DMA2D_FGCMAR register  **************/
-
-#define DMA2D_FGCMAR_MA                    0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_BGCMAR register  **************/
-
-#define DMA2D_BGCMAR_MA                    0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_OPFCCR register  **************/
-
-#define DMA2D_OPFCCR_CM                    0x00000007U               /*!< Color mode CM[2:0] */
-#define DMA2D_OPFCCR_CM_0                  0x00000001U               /*!< Color mode CM bit 0 */
-#define DMA2D_OPFCCR_CM_1                  0x00000002U               /*!< Color mode CM bit 1 */
-#define DMA2D_OPFCCR_CM_2                  0x00000004U               /*!< Color mode CM bit 2 */
-#define DMA2D_OPFCCR_AI                    0x00100000U               /*!< Output Alpha Inverted */
-#define DMA2D_OPFCCR_RBS                   0x00200000U               /*!< Output Red Blue Swap */
-
-/********************  Bit definition for DMA2D_OCOLR register  ***************/
-
-/*!<Mode_ARGB8888/RGB888 */
-
-#define DMA2D_OCOLR_BLUE_1                 0x000000FFU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_1                0x0000FF00U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_1                  0x00FF0000U               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_1                0xFF000000U               /*!< Alpha Channel Value */
-
-/*!<Mode_RGB565 */
-#define DMA2D_OCOLR_BLUE_2                 0x0000001FU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_2                0x000007E0U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_2                  0x0000F800U               /*!< Red Value */
-
-/*!<Mode_ARGB1555 */
-#define DMA2D_OCOLR_BLUE_3                 0x0000001FU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_3                0x000003E0U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_3                  0x00007C00U               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_3                0x00008000U               /*!< Alpha Channel Value */
-
-/*!<Mode_ARGB4444 */
-#define DMA2D_OCOLR_BLUE_4                 0x0000000FU               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_4                0x000000F0U               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_4                  0x00000F00U               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_4                0x0000F000U               /*!< Alpha Channel Value */
-
-/********************  Bit definition for DMA2D_OMAR register  ****************/
-
-#define DMA2D_OMAR_MA                      0xFFFFFFFFU               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_OOR register  *****************/
-
-#define DMA2D_OOR_LO                       0x00003FFFU               /*!< Line Offset */
-
-/********************  Bit definition for DMA2D_NLR register  *****************/
-
-#define DMA2D_NLR_NL                       0x0000FFFFU               /*!< Number of Lines */
-#define DMA2D_NLR_PL                       0x3FFF0000U               /*!< Pixel per Lines */
-
-/********************  Bit definition for DMA2D_LWR register  *****************/
-
-#define DMA2D_LWR_LW                       0x0000FFFFU               /*!< Line Watermark */
-
-/********************  Bit definition for DMA2D_AMTCR register  ***************/
-
-#define DMA2D_AMTCR_EN                     0x00000001U               /*!< Enable */
-#define DMA2D_AMTCR_DT                     0x0000FF00U               /*!< Dead Time */
-
-
-/********************  Bit definition for DMA2D_FGCLUT register  **************/
-                                                                     
-/********************  Bit definition for DMA2D_BGCLUT register  **************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                    External Interrupt/Event Controller                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
-#define  EXTI_IMR_MR23                       0x00800000U        /*!< Interrupt Mask on line 23 */
-#define  EXTI_IMR_MR24                       0x01000000U        /*!< Interrupt Mask on line 24 */
-
-/* Reference Defines */
-#define  EXTI_IMR_IM0                        EXTI_IMR_MR0                     
-#define  EXTI_IMR_IM1                        EXTI_IMR_MR1 
-#define  EXTI_IMR_IM2                        EXTI_IMR_MR2 
-#define  EXTI_IMR_IM3                        EXTI_IMR_MR3 
-#define  EXTI_IMR_IM4                        EXTI_IMR_MR4 
-#define  EXTI_IMR_IM5                        EXTI_IMR_MR5 
-#define  EXTI_IMR_IM6                        EXTI_IMR_MR6 
-#define  EXTI_IMR_IM7                        EXTI_IMR_MR7 
-#define  EXTI_IMR_IM8                        EXTI_IMR_MR8 
-#define  EXTI_IMR_IM9                        EXTI_IMR_MR9 
-#define  EXTI_IMR_IM10                       EXTI_IMR_MR10
-#define  EXTI_IMR_IM11                       EXTI_IMR_MR11
-#define  EXTI_IMR_IM12                       EXTI_IMR_MR12
-#define  EXTI_IMR_IM13                       EXTI_IMR_MR13
-#define  EXTI_IMR_IM14                       EXTI_IMR_MR14
-#define  EXTI_IMR_IM15                       EXTI_IMR_MR15
-#define  EXTI_IMR_IM16                       EXTI_IMR_MR16
-#define  EXTI_IMR_IM17                       EXTI_IMR_MR17
-#define  EXTI_IMR_IM18                       EXTI_IMR_MR18
-#define  EXTI_IMR_IM19                       EXTI_IMR_MR19
-#define  EXTI_IMR_IM20                       EXTI_IMR_MR20
-#define  EXTI_IMR_IM21                       EXTI_IMR_MR21
-#define  EXTI_IMR_IM22                       EXTI_IMR_MR22
-#define  EXTI_IMR_IM23                       EXTI_IMR_MR23
-#define  EXTI_IMR_IM24                       EXTI_IMR_MR24
-
-#define  EXTI_IMR_IM                         0x01FFFFFFU        /*!< Interrupt Mask All */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
-#define  EXTI_EMR_MR23                       0x00800000U        /*!< Event Mask on line 23 */
-#define  EXTI_EMR_MR24                       0x01000000U        /*!< Event Mask on line 24 */
-
-/* Reference Defines */
-#define  EXTI_EMR_EM0                        EXTI_EMR_MR0                         
-#define  EXTI_EMR_EM1                        EXTI_EMR_MR1 
-#define  EXTI_EMR_EM2                        EXTI_EMR_MR2 
-#define  EXTI_EMR_EM3                        EXTI_EMR_MR3 
-#define  EXTI_EMR_EM4                        EXTI_EMR_MR4 
-#define  EXTI_EMR_EM5                        EXTI_EMR_MR5 
-#define  EXTI_EMR_EM6                        EXTI_EMR_MR6 
-#define  EXTI_EMR_EM7                        EXTI_EMR_MR7 
-#define  EXTI_EMR_EM8                        EXTI_EMR_MR8 
-#define  EXTI_EMR_EM9                        EXTI_EMR_MR9 
-#define  EXTI_EMR_EM10                       EXTI_EMR_MR10
-#define  EXTI_EMR_EM11                       EXTI_EMR_MR11
-#define  EXTI_EMR_EM12                       EXTI_EMR_MR12
-#define  EXTI_EMR_EM13                       EXTI_EMR_MR13
-#define  EXTI_EMR_EM14                       EXTI_EMR_MR14
-#define  EXTI_EMR_EM15                       EXTI_EMR_MR15
-#define  EXTI_EMR_EM16                       EXTI_EMR_MR16
-#define  EXTI_EMR_EM17                       EXTI_EMR_MR17
-#define  EXTI_EMR_EM18                       EXTI_EMR_MR18
-#define  EXTI_EMR_EM19                       EXTI_EMR_MR19
-#define  EXTI_EMR_EM20                       EXTI_EMR_MR20
-#define  EXTI_EMR_EM21                       EXTI_EMR_MR21
-#define  EXTI_EMR_EM22                       EXTI_EMR_MR22
-#define  EXTI_EMR_EM23                       EXTI_EMR_MR23
-#define  EXTI_EMR_EM24                       EXTI_EMR_MR24
-
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
-#define  EXTI_RTSR_TR23                      0x00800000U        /*!< Rising trigger event configuration bit of line 23 */
-#define  EXTI_RTSR_TR24                      0x01000000U        /*!< Rising trigger event configuration bit of line 24 */
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
-#define  EXTI_FTSR_TR23                      0x00800000U        /*!< Falling trigger event configuration bit of line 23 */
-#define  EXTI_FTSR_TR24                      0x01000000U        /*!< Falling trigger event configuration bit of line 24 */
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
-#define  EXTI_SWIER_SWIER23                  0x00800000U        /*!< Software Interrupt on line 23 */
-#define  EXTI_SWIER_SWIER24                  0x01000000U        /*!< Software Interrupt on line 24 */
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
-#define  EXTI_PR_PR23                        0x00800000U        /*!< Pending bit for line 23 */
-#define  EXTI_PR_PR24                        0x01000000U        /*!< Pending bit for line 24 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    FLASH                                   */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief FLASH Total Sectors Number
-*/
-#define FLASH_SECTOR_TOTAL  24
-
-/*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    0x0000000FU
-#define FLASH_ACR_LATENCY_0WS                0x00000000U
-#define FLASH_ACR_LATENCY_1WS                0x00000001U
-#define FLASH_ACR_LATENCY_2WS                0x00000002U
-#define FLASH_ACR_LATENCY_3WS                0x00000003U
-#define FLASH_ACR_LATENCY_4WS                0x00000004U
-#define FLASH_ACR_LATENCY_5WS                0x00000005U
-#define FLASH_ACR_LATENCY_6WS                0x00000006U
-#define FLASH_ACR_LATENCY_7WS                0x00000007U
-#define FLASH_ACR_LATENCY_8WS                0x00000008U
-#define FLASH_ACR_LATENCY_9WS                0x00000009U
-#define FLASH_ACR_LATENCY_10WS               0x0000000AU
-#define FLASH_ACR_LATENCY_11WS               0x0000000BU
-#define FLASH_ACR_LATENCY_12WS               0x0000000CU
-#define FLASH_ACR_LATENCY_13WS               0x0000000DU
-#define FLASH_ACR_LATENCY_14WS               0x0000000EU
-#define FLASH_ACR_LATENCY_15WS               0x0000000FU
-#define FLASH_ACR_PRFTEN                     0x00000100U
-#define FLASH_ACR_ARTEN                      0x00000200U
-#define FLASH_ACR_ARTRST                     0x00000800U
-
-/*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         0x00000001U
-#define FLASH_SR_OPERR                       0x00000002U
-#define FLASH_SR_WRPERR                      0x00000010U
-#define FLASH_SR_PGAERR                      0x00000020U
-#define FLASH_SR_PGPERR                      0x00000040U
-#define FLASH_SR_ERSERR                      0x00000080U
-#define FLASH_SR_BSY                         0x00010000U
-
-/*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          0x00000001U
-#define FLASH_CR_SER                         0x00000002U
-#define FLASH_CR_MER                         0x00000004U
-#define FLASH_CR_MER1                        FLASH_CR_MER
-#define FLASH_CR_SNB                         0x000000F8U
-#define FLASH_CR_SNB_0                       0x00000008U
-#define FLASH_CR_SNB_1                       0x00000010U
-#define FLASH_CR_SNB_2                       0x00000020U
-#define FLASH_CR_SNB_3                       0x00000040U
-#define FLASH_CR_SNB_4                       0x00000080U
-#define FLASH_CR_PSIZE                       0x00000300U
-#define FLASH_CR_PSIZE_0                     0x00000100U
-#define FLASH_CR_PSIZE_1                     0x00000200U
-#define FLASH_CR_MER2                        0x00008000U
-#define FLASH_CR_STRT                        0x00010000U
-#define FLASH_CR_EOPIE                       0x01000000U
-#define FLASH_CR_ERRIE                       0x02000000U
-#define FLASH_CR_LOCK                        0x80000000U
-
-/*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                 0x00000001U
-#define FLASH_OPTCR_OPTSTRT                 0x00000002U
-#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
-#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
-#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
-#define FLASH_OPTCR_WWDG_SW                 0x00000010U
-#define FLASH_OPTCR_IWDG_SW                 0x00000020U
-#define FLASH_OPTCR_nRST_STOP               0x00000040U
-#define FLASH_OPTCR_nRST_STDBY              0x00000080U
-#define FLASH_OPTCR_RDP                     0x0000FF00U
-#define FLASH_OPTCR_RDP_0                   0x00000100U
-#define FLASH_OPTCR_RDP_1                   0x00000200U
-#define FLASH_OPTCR_RDP_2                   0x00000400U
-#define FLASH_OPTCR_RDP_3                   0x00000800U
-#define FLASH_OPTCR_RDP_4                   0x00001000U
-#define FLASH_OPTCR_RDP_5                   0x00002000U
-#define FLASH_OPTCR_RDP_6                   0x00004000U
-#define FLASH_OPTCR_RDP_7                   0x00008000U
-#define FLASH_OPTCR_nWRP                    0x0FFF0000U
-#define FLASH_OPTCR_nWRP_0                  0x00010000U
-#define FLASH_OPTCR_nWRP_1                  0x00020000U
-#define FLASH_OPTCR_nWRP_2                  0x00040000U
-#define FLASH_OPTCR_nWRP_3                  0x00080000U
-#define FLASH_OPTCR_nWRP_4                  0x00100000U
-#define FLASH_OPTCR_nWRP_5                  0x00200000U
-#define FLASH_OPTCR_nWRP_6                  0x00400000U
-#define FLASH_OPTCR_nWRP_7                  0x00800000U
-#define FLASH_OPTCR_nWRP_8                  0x01000000U
-#define FLASH_OPTCR_nWRP_9                  0x02000000U
-#define FLASH_OPTCR_nWRP_10                 0x04000000U
-#define FLASH_OPTCR_nWRP_11                 0x08000000U
-#define FLASH_OPTCR_nDBOOT                  0x10000000U
-#define FLASH_OPTCR_nDBANK                  0x20000000U
-#define FLASH_OPTCR_IWDG_STDBY              0x40000000U
-#define FLASH_OPTCR_IWDG_STOP               0x80000000U
-
-/*******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_BOOT_ADD0              0x0000FFFFU
-#define FLASH_OPTCR1_BOOT_ADD1              0xFFFF0000U
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Flexible Memory Controller                        */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for FMC_BCR1 register  *******************/
-#define  FMC_BCR1_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR1_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-#define  FMC_BCR1_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR1_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR1_MTYP_1                    0x00000008U        /*!<Bit 1 */
-#define  FMC_BCR1_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR1_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR1_MWID_1                    0x00000020U        /*!<Bit 1 */
-#define  FMC_BCR1_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR1_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR1_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR1_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
-#define  FMC_BCR1_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR1_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR1_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR1_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR1_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR1_CPSIZE                    0x00070000U        /*!<CRAM page size             */
-#define  FMC_BCR1_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FMC_BCR1_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FMC_BCR1_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FMC_BCR1_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-#define  FMC_BCR1_CCLKEN                    0x00100000U        /*!<Continous clock enable     */
-#define  FMC_BCR1_WFDIS                     0x00200000U        /*!<Write FIFO Disable         */
-
-/******************  Bit definition for FMC_BCR2 register  *******************/
-#define  FMC_BCR2_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR2_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-#define  FMC_BCR2_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR2_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR2_MTYP_1                    0x00000008U        /*!<Bit 1 */
-#define  FMC_BCR2_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR2_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR2_MWID_1                    0x00000020U        /*!<Bit 1 */
-#define  FMC_BCR2_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR2_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR2_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR2_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
-#define  FMC_BCR2_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR2_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR2_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR2_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR2_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR2_CPSIZE                    0x00070000U        /*!<CRAM page size             */
-#define  FMC_BCR2_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FMC_BCR2_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FMC_BCR2_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FMC_BCR2_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FMC_BCR3 register  *******************/
-#define  FMC_BCR3_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR3_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-#define  FMC_BCR3_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR3_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR3_MTYP_1                    0x00000008U        /*!<Bit 1 */
-#define  FMC_BCR3_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR3_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR3_MWID_1                    0x00000020U        /*!<Bit 1 */
-#define  FMC_BCR3_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR3_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR3_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR3_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
-#define  FMC_BCR3_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR3_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR3_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR3_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR3_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR3_CPSIZE                    0x00070000U        /*!<CRAM page size             */
-#define  FMC_BCR3_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FMC_BCR3_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FMC_BCR3_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FMC_BCR3_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FMC_BCR4 register  *******************/
-#define  FMC_BCR4_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
-#define  FMC_BCR4_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
-#define  FMC_BCR4_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR4_MTYP_0                    0x00000004U        /*!<Bit 0 */
-#define  FMC_BCR4_MTYP_1                    0x00000008U        /*!<Bit 1 */
-#define  FMC_BCR4_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR4_MWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_BCR4_MWID_1                    0x00000020U        /*!<Bit 1 */
-#define  FMC_BCR4_FACCEN                    0x00000040U        /*!<Flash access enable        */
-#define  FMC_BCR4_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
-#define  FMC_BCR4_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
-#define  FMC_BCR4_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
-#define  FMC_BCR4_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
-#define  FMC_BCR4_WREN                      0x00001000U        /*!<Write enable bit           */
-#define  FMC_BCR4_WAITEN                    0x00002000U        /*!<Wait enable bit            */
-#define  FMC_BCR4_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
-#define  FMC_BCR4_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
-#define  FMC_BCR4_CPSIZE                    0x00070000U        /*!<CRAM page size             */
-#define  FMC_BCR4_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
-#define  FMC_BCR4_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
-#define  FMC_BCR4_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
-#define  FMC_BCR4_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
-
-/******************  Bit definition for FMC_BTR1 register  ******************/
-#define  FMC_BTR1_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR1_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR1_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR1_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR1_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-#define  FMC_BTR1_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
-#define  FMC_BTR1_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR1_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR1_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR1_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-#define  FMC_BTR1_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR1_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR1_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR1_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR1_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR1_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR1_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR1_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR1_DATAST_7                  0x00008000U        /*!<Bit 7 */
-#define  FMC_BTR1_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR1_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR1_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR1_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR1_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-#define  FMC_BTR1_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR1_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR1_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR1_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR1_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-#define  FMC_BTR1_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR1_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR1_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR1_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR1_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-#define  FMC_BTR1_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR1_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR1_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BTR2 register  *******************/
-#define  FMC_BTR2_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR2_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR2_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR2_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR2_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-#define  FMC_BTR2_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR2_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR2_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR2_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR2_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-#define  FMC_BTR2_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR2_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR2_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR2_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR2_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR2_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR2_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR2_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR2_DATAST_7                  0x00008000U        /*!<Bit 7 */
-#define  FMC_BTR2_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR2_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR2_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR2_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR2_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-#define  FMC_BTR2_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR2_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR2_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR2_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR2_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-#define  FMC_BTR2_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR2_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR2_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR2_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR2_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-#define  FMC_BTR2_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR2_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR2_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/*******************  Bit definition for FMC_BTR3 register  *******************/
-#define  FMC_BTR3_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR3_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR3_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR3_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR3_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-#define  FMC_BTR3_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR3_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR3_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR3_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR3_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-#define  FMC_BTR3_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR3_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR3_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR3_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR3_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR3_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR3_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR3_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR3_DATAST_7                  0x00008000U        /*!<Bit 7 */
-#define  FMC_BTR3_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR3_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR3_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR3_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR3_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-#define  FMC_BTR3_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR3_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR3_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR3_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR3_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-#define  FMC_BTR3_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR3_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR3_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR3_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR3_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-#define  FMC_BTR3_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR3_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR3_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BTR4 register  *******************/
-#define  FMC_BTR4_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR4_ADDSET_0                  0x00000001U        /*!<Bit 0 */
-#define  FMC_BTR4_ADDSET_1                  0x00000002U        /*!<Bit 1 */
-#define  FMC_BTR4_ADDSET_2                  0x00000004U        /*!<Bit 2 */
-#define  FMC_BTR4_ADDSET_3                  0x00000008U        /*!<Bit 3 */
-#define  FMC_BTR4_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR4_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
-#define  FMC_BTR4_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
-#define  FMC_BTR4_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
-#define  FMC_BTR4_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
-#define  FMC_BTR4_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR4_DATAST_0                  0x00000100U        /*!<Bit 0 */
-#define  FMC_BTR4_DATAST_1                  0x00000200U        /*!<Bit 1 */
-#define  FMC_BTR4_DATAST_2                  0x00000400U        /*!<Bit 2 */
-#define  FMC_BTR4_DATAST_3                  0x00000800U        /*!<Bit 3 */
-#define  FMC_BTR4_DATAST_4                  0x00001000U        /*!<Bit 4 */
-#define  FMC_BTR4_DATAST_5                  0x00002000U        /*!<Bit 5 */
-#define  FMC_BTR4_DATAST_6                  0x00004000U        /*!<Bit 6 */
-#define  FMC_BTR4_DATAST_7                  0x00008000U        /*!<Bit 7 */
-#define  FMC_BTR4_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR4_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
-#define  FMC_BTR4_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
-#define  FMC_BTR4_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
-#define  FMC_BTR4_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
-#define  FMC_BTR4_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR4_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
-#define  FMC_BTR4_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
-#define  FMC_BTR4_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
-#define  FMC_BTR4_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
-#define  FMC_BTR4_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR4_DATLAT_0                  0x01000000U        /*!<Bit 0 */
-#define  FMC_BTR4_DATLAT_1                  0x02000000U        /*!<Bit 1 */
-#define  FMC_BTR4_DATLAT_2                  0x04000000U        /*!<Bit 2 */
-#define  FMC_BTR4_DATLAT_3                  0x08000000U        /*!<Bit 3 */
-#define  FMC_BTR4_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR4_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
-#define  FMC_BTR4_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR1 register  ******************/
-#define  FMC_BWTR1_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR1_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR1_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR1_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR1_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-#define  FMC_BWTR1_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR1_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR1_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR1_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR1_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-#define  FMC_BWTR1_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR1_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR1_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR1_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR1_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR1_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR1_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR1_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR1_DATAST_7                 0x00008000U        /*!<Bit 7 */
-#define  FMC_BWTR1_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BWTR1_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR1_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR1_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR1_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-#define  FMC_BWTR1_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR1_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR1_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR2 register  ******************/
-#define  FMC_BWTR2_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR2_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR2_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR2_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR2_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-#define  FMC_BWTR2_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR2_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR2_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR2_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR2_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-#define  FMC_BWTR2_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR2_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR2_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR2_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR2_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR2_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR2_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR2_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR2_DATAST_7                 0x00008000U        /*!<Bit 7 */
-#define  FMC_BWTR2_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BWTR2_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR2_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR2_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR2_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-#define  FMC_BWTR2_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR2_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR2_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR3 register  ******************/
-#define  FMC_BWTR3_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR3_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR3_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR3_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR3_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-#define  FMC_BWTR3_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR3_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR3_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR3_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR3_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-#define  FMC_BWTR3_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR3_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR3_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR3_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR3_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR3_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR3_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR3_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR3_DATAST_7                 0x00008000U        /*!<Bit 7 */
-#define  FMC_BWTR3_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BWTR3_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR3_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR3_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR3_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-#define  FMC_BWTR3_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR3_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR3_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR4 register  ******************/
-#define  FMC_BWTR4_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR4_ADDSET_0                 0x00000001U        /*!<Bit 0 */
-#define  FMC_BWTR4_ADDSET_1                 0x00000002U        /*!<Bit 1 */
-#define  FMC_BWTR4_ADDSET_2                 0x00000004U        /*!<Bit 2 */
-#define  FMC_BWTR4_ADDSET_3                 0x00000008U        /*!<Bit 3 */
-#define  FMC_BWTR4_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR4_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
-#define  FMC_BWTR4_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
-#define  FMC_BWTR4_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
-#define  FMC_BWTR4_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
-#define  FMC_BWTR4_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR4_DATAST_0                 0x00000100U        /*!<Bit 0 */
-#define  FMC_BWTR4_DATAST_1                 0x00000200U        /*!<Bit 1 */
-#define  FMC_BWTR4_DATAST_2                 0x00000400U        /*!<Bit 2 */
-#define  FMC_BWTR4_DATAST_3                 0x00000800U        /*!<Bit 3 */
-#define  FMC_BWTR4_DATAST_4                 0x00001000U        /*!<Bit 4 */
-#define  FMC_BWTR4_DATAST_5                 0x00002000U        /*!<Bit 5 */
-#define  FMC_BWTR4_DATAST_6                 0x00004000U        /*!<Bit 6 */
-#define  FMC_BWTR4_DATAST_7                 0x00008000U        /*!<Bit 7 */
-#define  FMC_BWTR4_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BWTR4_BUSTURN_0                0x00010000U        /*!<Bit 0 */
-#define  FMC_BWTR4_BUSTURN_1                0x00020000U        /*!<Bit 1 */
-#define  FMC_BWTR4_BUSTURN_2                0x00040000U        /*!<Bit 2 */
-#define  FMC_BWTR4_BUSTURN_3                0x00080000U        /*!<Bit 3 */
-#define  FMC_BWTR4_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR4_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
-#define  FMC_BWTR4_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_PCR register  *******************/
-#define  FMC_PCR_PWAITEN                   0x00000002U        /*!<Wait feature enable bit                   */
-#define  FMC_PCR_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FMC_PCR_PTYP                      0x00000008U        /*!<Memory type                               */
-#define  FMC_PCR_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FMC_PCR_PWID_0                    0x00000010U        /*!<Bit 0 */
-#define  FMC_PCR_PWID_1                    0x00000020U        /*!<Bit 1 */
-#define  FMC_PCR_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit          */
-#define  FMC_PCR_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay)          */
-#define  FMC_PCR_TCLR_0                    0x00000200U        /*!<Bit 0 */
-#define  FMC_PCR_TCLR_1                    0x00000400U        /*!<Bit 1 */
-#define  FMC_PCR_TCLR_2                    0x00000800U        /*!<Bit 2 */
-#define  FMC_PCR_TCLR_3                    0x00001000U        /*!<Bit 3 */
-#define  FMC_PCR_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay)           */
-#define  FMC_PCR_TAR_0                     0x00002000U        /*!<Bit 0 */
-#define  FMC_PCR_TAR_1                     0x00004000U        /*!<Bit 1 */
-#define  FMC_PCR_TAR_2                     0x00008000U        /*!<Bit 2 */
-#define  FMC_PCR_TAR_3                     0x00010000U        /*!<Bit 3 */
-#define  FMC_PCR_ECCPS                     0x000E0000U        /*!<ECCPS[2:0] bits (ECC page size)           */
-#define  FMC_PCR_ECCPS_0                   0x00020000U        /*!<Bit 0 */
-#define  FMC_PCR_ECCPS_1                   0x00040000U        /*!<Bit 1 */
-#define  FMC_PCR_ECCPS_2                   0x00080000U        /*!<Bit 2 */
-
-/*******************  Bit definition for FMC_SR register  *******************/
-#define  FMC_SR_IRS                        0x01U              /*!<Interrupt Rising Edge status                */
-#define  FMC_SR_ILS                        0x02U              /*!<Interrupt Level status                      */
-#define  FMC_SR_IFS                        0x04U              /*!<Interrupt Falling Edge status               */
-#define  FMC_SR_IREN                       0x08U              /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FMC_SR_ILEN                       0x10U              /*!<Interrupt Level detection Enable bit        */
-#define  FMC_SR_IFEN                       0x20U              /*!<Interrupt Falling Edge detection Enable bit */
-#define  FMC_SR_FEMPT                      0x40U              /*!<FIFO empty                                  */
-
-/******************  Bit definition for FMC_PMEM register  ******************/
-#define  FMC_PMEM_MEMSET3                  0x000000FFU        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
-#define  FMC_PMEM_MEMSET3_0                0x00000001U        /*!<Bit 0 */
-#define  FMC_PMEM_MEMSET3_1                0x00000002U        /*!<Bit 1 */
-#define  FMC_PMEM_MEMSET3_2                0x00000004U        /*!<Bit 2 */
-#define  FMC_PMEM_MEMSET3_3                0x00000008U        /*!<Bit 3 */
-#define  FMC_PMEM_MEMSET3_4                0x00000010U        /*!<Bit 4 */
-#define  FMC_PMEM_MEMSET3_5                0x00000020U        /*!<Bit 5 */
-#define  FMC_PMEM_MEMSET3_6                0x00000040U        /*!<Bit 6 */
-#define  FMC_PMEM_MEMSET3_7                0x00000080U        /*!<Bit 7 */
-#define  FMC_PMEM_MEMWAIT3                 0x0000FF00U        /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
-#define  FMC_PMEM_MEMWAIT3_0               0x00000100U        /*!<Bit 0 */
-#define  FMC_PMEM_MEMWAIT3_1               0x00000200U        /*!<Bit 1 */
-#define  FMC_PMEM_MEMWAIT3_2               0x00000400U        /*!<Bit 2 */
-#define  FMC_PMEM_MEMWAIT3_3               0x00000800U        /*!<Bit 3 */
-#define  FMC_PMEM_MEMWAIT3_4               0x00001000U        /*!<Bit 4 */
-#define  FMC_PMEM_MEMWAIT3_5               0x00002000U        /*!<Bit 5 */
-#define  FMC_PMEM_MEMWAIT3_6               0x00004000U        /*!<Bit 6 */
-#define  FMC_PMEM_MEMWAIT3_7               0x00008000U        /*!<Bit 7 */
-#define  FMC_PMEM_MEMHOLD3                 0x00FF0000U        /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
-#define  FMC_PMEM_MEMHOLD3_0               0x00010000U        /*!<Bit 0 */
-#define  FMC_PMEM_MEMHOLD3_1               0x00020000U        /*!<Bit 1 */
-#define  FMC_PMEM_MEMHOLD3_2               0x00040000U        /*!<Bit 2 */
-#define  FMC_PMEM_MEMHOLD3_3               0x00080000U        /*!<Bit 3 */
-#define  FMC_PMEM_MEMHOLD3_4               0x00100000U        /*!<Bit 4 */
-#define  FMC_PMEM_MEMHOLD3_5               0x00200000U        /*!<Bit 5 */
-#define  FMC_PMEM_MEMHOLD3_6               0x00400000U        /*!<Bit 6 */
-#define  FMC_PMEM_MEMHOLD3_7               0x00800000U        /*!<Bit 7 */
-#define  FMC_PMEM_MEMHIZ3                  0xFF000000U        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
-#define  FMC_PMEM_MEMHIZ3_0                0x01000000U        /*!<Bit 0 */
-#define  FMC_PMEM_MEMHIZ3_1                0x02000000U        /*!<Bit 1 */
-#define  FMC_PMEM_MEMHIZ3_2                0x04000000U        /*!<Bit 2 */
-#define  FMC_PMEM_MEMHIZ3_3                0x08000000U        /*!<Bit 3 */
-#define  FMC_PMEM_MEMHIZ3_4                0x10000000U        /*!<Bit 4 */
-#define  FMC_PMEM_MEMHIZ3_5                0x20000000U        /*!<Bit 5 */
-#define  FMC_PMEM_MEMHIZ3_6                0x40000000U        /*!<Bit 6 */
-#define  FMC_PMEM_MEMHIZ3_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_PATT register  ******************/
-#define  FMC_PATT_ATTSET3                  0x000000FFU        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
-#define  FMC_PATT_ATTSET3_0                0x00000001U        /*!<Bit 0 */
-#define  FMC_PATT_ATTSET3_1                0x00000002U        /*!<Bit 1 */
-#define  FMC_PATT_ATTSET3_2                0x00000004U        /*!<Bit 2 */
-#define  FMC_PATT_ATTSET3_3                0x00000008U        /*!<Bit 3 */
-#define  FMC_PATT_ATTSET3_4                0x00000010U        /*!<Bit 4 */
-#define  FMC_PATT_ATTSET3_5                0x00000020U        /*!<Bit 5 */
-#define  FMC_PATT_ATTSET3_6                0x00000040U        /*!<Bit 6 */
-#define  FMC_PATT_ATTSET3_7                0x00000080U        /*!<Bit 7 */
-#define  FMC_PATT_ATTWAIT3                 0x0000FF00U        /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
-#define  FMC_PATT_ATTWAIT3_0               0x00000100U        /*!<Bit 0 */
-#define  FMC_PATT_ATTWAIT3_1               0x00000200U        /*!<Bit 1 */
-#define  FMC_PATT_ATTWAIT3_2               0x00000400U        /*!<Bit 2 */
-#define  FMC_PATT_ATTWAIT3_3               0x00000800U        /*!<Bit 3 */
-#define  FMC_PATT_ATTWAIT3_4               0x00001000U        /*!<Bit 4 */
-#define  FMC_PATT_ATTWAIT3_5               0x00002000U        /*!<Bit 5 */
-#define  FMC_PATT_ATTWAIT3_6               0x00004000U        /*!<Bit 6 */
-#define  FMC_PATT_ATTWAIT3_7               0x00008000U        /*!<Bit 7 */
-#define  FMC_PATT_ATTHOLD3                 0x00FF0000U        /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
-#define  FMC_PATT_ATTHOLD3_0               0x00010000U        /*!<Bit 0 */
-#define  FMC_PATT_ATTHOLD3_1               0x00020000U        /*!<Bit 1 */
-#define  FMC_PATT_ATTHOLD3_2               0x00040000U        /*!<Bit 2 */
-#define  FMC_PATT_ATTHOLD3_3               0x00080000U        /*!<Bit 3 */
-#define  FMC_PATT_ATTHOLD3_4               0x00100000U        /*!<Bit 4 */
-#define  FMC_PATT_ATTHOLD3_5               0x00200000U        /*!<Bit 5 */
-#define  FMC_PATT_ATTHOLD3_6               0x00400000U        /*!<Bit 6 */
-#define  FMC_PATT_ATTHOLD3_7               0x00800000U        /*!<Bit 7 */
-#define  FMC_PATT_ATTHIZ3                  0xFF000000U        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
-#define  FMC_PATT_ATTHIZ3_0                0x01000000U        /*!<Bit 0 */
-#define  FMC_PATT_ATTHIZ3_1                0x02000000U        /*!<Bit 1 */
-#define  FMC_PATT_ATTHIZ3_2                0x04000000U        /*!<Bit 2 */
-#define  FMC_PATT_ATTHIZ3_3                0x08000000U        /*!<Bit 3 */
-#define  FMC_PATT_ATTHIZ3_4                0x10000000U        /*!<Bit 4 */
-#define  FMC_PATT_ATTHIZ3_5                0x20000000U        /*!<Bit 5 */
-#define  FMC_PATT_ATTHIZ3_6                0x40000000U        /*!<Bit 6 */
-#define  FMC_PATT_ATTHIZ3_7                0x80000000U        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_ECCR register  ******************/
-#define  FMC_ECCR_ECC3                     0xFFFFFFFFU        /*!<ECC result */
-
-/******************  Bit definition for FMC_SDCR1 register  ******************/
-#define  FMC_SDCR1_NC                       0x00000003U        /*!<NC[1:0] bits (Number of column bits) */
-#define  FMC_SDCR1_NC_0                     0x00000001U        /*!<Bit 0 */
-#define  FMC_SDCR1_NC_1                     0x00000002U        /*!<Bit 1 */
-#define  FMC_SDCR1_NR                       0x0000000CU        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR1_NR_0                     0x00000004U        /*!<Bit 0 */
-#define  FMC_SDCR1_NR_1                     0x00000008U        /*!<Bit 1 */
-#define  FMC_SDCR1_MWID                     0x00000030U        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR1_MWID_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDCR1_MWID_1                   0x00000020U        /*!<Bit 1 */
-#define  FMC_SDCR1_NB                       0x00000040U        /*!<Number of internal bank */
-#define  FMC_SDCR1_CAS                      0x00000180U        /*!<CAS[1:0] bits (CAS latency) */
-#define  FMC_SDCR1_CAS_0                    0x00000080U        /*!<Bit 0 */
-#define  FMC_SDCR1_CAS_1                    0x00000100U        /*!<Bit 1 */
-#define  FMC_SDCR1_WP                       0x00000200U        /*!<Write protection */
-#define  FMC_SDCR1_SDCLK                    0x00000C00U        /*!<SDRAM clock configuration */
-#define  FMC_SDCR1_SDCLK_0                  0x00000400U        /*!<Bit 0 */
-#define  FMC_SDCR1_SDCLK_1                  0x00000800U        /*!<Bit 1 */
-#define  FMC_SDCR1_RBURST                   0x00001000U        /*!<Read burst */
-#define  FMC_SDCR1_RPIPE                    0x00006000U        /*!<Write protection */
-#define  FMC_SDCR1_RPIPE_0                  0x00002000U        /*!<Bit 0 */
-#define  FMC_SDCR1_RPIPE_1                  0x00004000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_SDCR2 register  ******************/
-#define  FMC_SDCR2_NC                       0x00000003U        /*!<NC[1:0] bits (Number of column bits) */
-#define  FMC_SDCR2_NC_0                     0x00000001U        /*!<Bit 0 */
-#define  FMC_SDCR2_NC_1                     0x00000002U        /*!<Bit 1 */
-#define  FMC_SDCR2_NR                       0x0000000CU        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR2_NR_0                     0x00000004U        /*!<Bit 0 */
-#define  FMC_SDCR2_NR_1                     0x00000008U        /*!<Bit 1 */
-#define  FMC_SDCR2_MWID                     0x00000030U        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR2_MWID_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDCR2_MWID_1                   0x00000020U        /*!<Bit 1 */
-#define  FMC_SDCR2_NB                       0x00000040U        /*!<Number of internal bank */
-#define  FMC_SDCR2_CAS                      0x00000180U        /*!<CAS[1:0] bits (CAS latency) */
-#define  FMC_SDCR2_CAS_0                    0x00000080U        /*!<Bit 0 */
-#define  FMC_SDCR2_CAS_1                    0x00000100U        /*!<Bit 1 */
-#define  FMC_SDCR2_WP                       0x00000200U        /*!<Write protection */
-#define  FMC_SDCR2_SDCLK                    0x00000C00U        /*!<SDCLK[1:0] (SDRAM clock configuration) */
-#define  FMC_SDCR2_SDCLK_0                  0x00000400U        /*!<Bit 0 */
-#define  FMC_SDCR2_SDCLK_1                  0x00000800U        /*!<Bit 1 */
-#define  FMC_SDCR2_RBURST                   0x00001000U        /*!<Read burst */
-#define  FMC_SDCR2_RPIPE                    0x00006000U        /*!<RPIPE[1:0](Read pipe) */
-#define  FMC_SDCR2_RPIPE_0                  0x00002000U        /*!<Bit 0 */
-#define  FMC_SDCR2_RPIPE_1                  0x00004000U        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_SDTR1 register  ******************/
-#define  FMC_SDTR1_TMRD                     0x0000000FU        /*!<TMRD[3:0] bits (Load mode register to active) */
-#define  FMC_SDTR1_TMRD_0                   0x00000001U        /*!<Bit 0 */
-#define  FMC_SDTR1_TMRD_1                   0x00000002U        /*!<Bit 1 */
-#define  FMC_SDTR1_TMRD_2                   0x00000004U        /*!<Bit 2 */
-#define  FMC_SDTR1_TMRD_3                   0x00000008U        /*!<Bit 3 */
-#define  FMC_SDTR1_TXSR                     0x000000F0U        /*!<TXSR[3:0] bits (Exit self refresh) */
-#define  FMC_SDTR1_TXSR_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDTR1_TXSR_1                   0x00000020U        /*!<Bit 1 */
-#define  FMC_SDTR1_TXSR_2                   0x00000040U        /*!<Bit 2 */
-#define  FMC_SDTR1_TXSR_3                   0x00000080U        /*!<Bit 3 */
-#define  FMC_SDTR1_TRAS                     0x00000F00U        /*!<TRAS[3:0] bits (Self refresh time) */
-#define  FMC_SDTR1_TRAS_0                   0x00000100U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRAS_1                   0x00000200U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRAS_2                   0x00000400U        /*!<Bit 2 */
-#define  FMC_SDTR1_TRAS_3                   0x00000800U        /*!<Bit 3 */
-#define  FMC_SDTR1_TRC                      0x0000F000U        /*!<TRC[2:0] bits (Row cycle delay) */
-#define  FMC_SDTR1_TRC_0                    0x00001000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRC_1                    0x00002000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRC_2                    0x00004000U        /*!<Bit 2 */
-#define  FMC_SDTR1_TWR                      0x000F0000U        /*!<TRC[2:0] bits (Write recovery delay) */
-#define  FMC_SDTR1_TWR_0                    0x00010000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TWR_1                    0x00020000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TWR_2                    0x00040000U        /*!<Bit 2 */
-#define  FMC_SDTR1_TRP                      0x00F00000U        /*!<TRP[2:0] bits (Row precharge delay) */
-#define  FMC_SDTR1_TRP_0                    0x00100000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRP_1                    0x00200000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRP_2                    0x00400000U        /*!<Bit 2 */
-#define  FMC_SDTR1_TRCD                     0x0F000000U        /*!<TRP[2:0] bits (Row to column delay) */
-#define  FMC_SDTR1_TRCD_0                   0x01000000U        /*!<Bit 0 */
-#define  FMC_SDTR1_TRCD_1                   0x02000000U        /*!<Bit 1 */
-#define  FMC_SDTR1_TRCD_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for FMC_SDTR2 register  ******************/
-#define  FMC_SDTR2_TMRD                     0x0000000FU        /*!<TMRD[3:0] bits (Load mode register to active) */
-#define  FMC_SDTR2_TMRD_0                   0x00000001U        /*!<Bit 0 */
-#define  FMC_SDTR2_TMRD_1                   0x00000002U        /*!<Bit 1 */
-#define  FMC_SDTR2_TMRD_2                   0x00000004U        /*!<Bit 2 */
-#define  FMC_SDTR2_TMRD_3                   0x00000008U        /*!<Bit 3 */
-#define  FMC_SDTR2_TXSR                     0x000000F0U        /*!<TXSR[3:0] bits (Exit self refresh) */
-#define  FMC_SDTR2_TXSR_0                   0x00000010U        /*!<Bit 0 */
-#define  FMC_SDTR2_TXSR_1                   0x00000020U        /*!<Bit 1 */
-#define  FMC_SDTR2_TXSR_2                   0x00000040U        /*!<Bit 2 */
-#define  FMC_SDTR2_TXSR_3                   0x00000080U        /*!<Bit 3 */
-#define  FMC_SDTR2_TRAS                     0x00000F00U        /*!<TRAS[3:0] bits (Self refresh time) */
-#define  FMC_SDTR2_TRAS_0                   0x00000100U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRAS_1                   0x00000200U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRAS_2                   0x00000400U        /*!<Bit 2 */
-#define  FMC_SDTR2_TRAS_3                   0x00000800U        /*!<Bit 3 */
-#define  FMC_SDTR2_TRC                      0x0000F000U        /*!<TRC[2:0] bits (Row cycle delay) */
-#define  FMC_SDTR2_TRC_0                    0x00001000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRC_1                    0x00002000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRC_2                    0x00004000U        /*!<Bit 2 */
-#define  FMC_SDTR2_TWR                      0x000F0000U        /*!<TRC[2:0] bits (Write recovery delay) */
-#define  FMC_SDTR2_TWR_0                    0x00010000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TWR_1                    0x00020000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TWR_2                    0x00040000U        /*!<Bit 2 */
-#define  FMC_SDTR2_TRP                      0x00F00000U        /*!<TRP[2:0] bits (Row precharge delay) */
-#define  FMC_SDTR2_TRP_0                    0x00100000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRP_1                    0x00200000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRP_2                    0x00400000U        /*!<Bit 2 */
-#define  FMC_SDTR2_TRCD                     0x0F000000U        /*!<TRP[2:0] bits (Row to column delay) */
-#define  FMC_SDTR2_TRCD_0                   0x01000000U        /*!<Bit 0 */
-#define  FMC_SDTR2_TRCD_1                   0x02000000U        /*!<Bit 1 */
-#define  FMC_SDTR2_TRCD_2                   0x04000000U        /*!<Bit 2 */
-
-/******************  Bit definition for FMC_SDCMR register  ******************/
-#define  FMC_SDCMR_MODE                     0x00000007U        /*!<MODE[2:0] bits (Command mode) */
-#define  FMC_SDCMR_MODE_0                   0x00000001U        /*!<Bit 0 */
-#define  FMC_SDCMR_MODE_1                   0x00000002U        /*!<Bit 1 */
-#define  FMC_SDCMR_MODE_2                   0x00000003U        /*!<Bit 2 */
-#define  FMC_SDCMR_CTB2                     0x00000008U        /*!<Command target 2 */
-#define  FMC_SDCMR_CTB1                     0x00000010U        /*!<Command target 1 */
-#define  FMC_SDCMR_NRFS                     0x000001E0U        /*!<NRFS[3:0] bits (Number of auto-refresh) */
-#define  FMC_SDCMR_NRFS_0                   0x00000020U        /*!<Bit 0 */
-#define  FMC_SDCMR_NRFS_1                   0x00000040U        /*!<Bit 1 */
-#define  FMC_SDCMR_NRFS_2                   0x00000080U        /*!<Bit 2 */
-#define  FMC_SDCMR_NRFS_3                   0x00000100U        /*!<Bit 3 */
-#define  FMC_SDCMR_MRD                      0x003FFE00U        /*!<MRD[12:0] bits (Mode register definition) */
-
-/******************  Bit definition for FMC_SDRTR register  ******************/
-#define  FMC_SDRTR_CRE                      0x00000001U        /*!<Clear refresh error flag */
-#define  FMC_SDRTR_COUNT                    0x00003FFEU        /*!<COUNT[12:0] bits (Refresh timer count) */
-#define  FMC_SDRTR_REIE                     0x00004000U        /*!<RES interupt enable */
-
-/******************  Bit definition for FMC_SDSR register  ******************/
-#define  FMC_SDSR_RE                        0x00000001U        /*!<Refresh error flag */
-#define  FMC_SDSR_MODES1                    0x00000006U        /*!<MODES1[1:0]bits (Status mode for bank 1) */
-#define  FMC_SDSR_MODES1_0                  0x00000002U        /*!<Bit 0 */
-#define  FMC_SDSR_MODES1_1                  0x00000004U        /*!<Bit 1 */
-#define  FMC_SDSR_MODES2                    0x00000018U        /*!<MODES2[1:0]bits (Status mode for bank 2) */
-#define  FMC_SDSR_MODES2_0                  0x00000008U        /*!<Bit 0 */
-#define  FMC_SDSR_MODES2_1                  0x00000010U        /*!<Bit 1 */
-#define  FMC_SDSR_BUSY                      0x00000020U        /*!<Busy status */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    0x00000003U
-#define GPIO_MODER_MODER0_0                  0x00000001U
-#define GPIO_MODER_MODER0_1                  0x00000002U
-#define GPIO_MODER_MODER1                    0x0000000CU
-#define GPIO_MODER_MODER1_0                  0x00000004U
-#define GPIO_MODER_MODER1_1                  0x00000008U
-#define GPIO_MODER_MODER2                    0x00000030U
-#define GPIO_MODER_MODER2_0                  0x00000010U
-#define GPIO_MODER_MODER2_1                  0x00000020U
-#define GPIO_MODER_MODER3                    0x000000C0U
-#define GPIO_MODER_MODER3_0                  0x00000040U
-#define GPIO_MODER_MODER3_1                  0x00000080U
-#define GPIO_MODER_MODER4                    0x00000300U
-#define GPIO_MODER_MODER4_0                  0x00000100U
-#define GPIO_MODER_MODER4_1                  0x00000200U
-#define GPIO_MODER_MODER5                    0x00000C00U
-#define GPIO_MODER_MODER5_0                  0x00000400U
-#define GPIO_MODER_MODER5_1                  0x00000800U
-#define GPIO_MODER_MODER6                    0x00003000U
-#define GPIO_MODER_MODER6_0                  0x00001000U
-#define GPIO_MODER_MODER6_1                  0x00002000U
-#define GPIO_MODER_MODER7                    0x0000C000U
-#define GPIO_MODER_MODER7_0                  0x00004000U
-#define GPIO_MODER_MODER7_1                  0x00008000U
-#define GPIO_MODER_MODER8                    0x00030000U
-#define GPIO_MODER_MODER8_0                  0x00010000U
-#define GPIO_MODER_MODER8_1                  0x00020000U
-#define GPIO_MODER_MODER9                    0x000C0000U
-#define GPIO_MODER_MODER9_0                  0x00040000U
-#define GPIO_MODER_MODER9_1                  0x00080000U
-#define GPIO_MODER_MODER10                   0x00300000U
-#define GPIO_MODER_MODER10_0                 0x00100000U
-#define GPIO_MODER_MODER10_1                 0x00200000U
-#define GPIO_MODER_MODER11                   0x00C00000U
-#define GPIO_MODER_MODER11_0                 0x00400000U
-#define GPIO_MODER_MODER11_1                 0x00800000U
-#define GPIO_MODER_MODER12                   0x03000000U
-#define GPIO_MODER_MODER12_0                 0x01000000U
-#define GPIO_MODER_MODER12_1                 0x02000000U
-#define GPIO_MODER_MODER13                   0x0C000000U
-#define GPIO_MODER_MODER13_0                 0x04000000U
-#define GPIO_MODER_MODER13_1                 0x08000000U
-#define GPIO_MODER_MODER14                   0x30000000U
-#define GPIO_MODER_MODER14_0                 0x10000000U
-#define GPIO_MODER_MODER14_1                 0x20000000U
-#define GPIO_MODER_MODER15                   0xC0000000U
-#define GPIO_MODER_MODER15_0                 0x40000000U
-#define GPIO_MODER_MODER15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     0x00000001U
-#define GPIO_OTYPER_OT_1                     0x00000002U
-#define GPIO_OTYPER_OT_2                     0x00000004U
-#define GPIO_OTYPER_OT_3                     0x00000008U
-#define GPIO_OTYPER_OT_4                     0x00000010U
-#define GPIO_OTYPER_OT_5                     0x00000020U
-#define GPIO_OTYPER_OT_6                     0x00000040U
-#define GPIO_OTYPER_OT_7                     0x00000080U
-#define GPIO_OTYPER_OT_8                     0x00000100U
-#define GPIO_OTYPER_OT_9                     0x00000200U
-#define GPIO_OTYPER_OT_10                    0x00000400U
-#define GPIO_OTYPER_OT_11                    0x00000800U
-#define GPIO_OTYPER_OT_12                    0x00001000U
-#define GPIO_OTYPER_OT_13                    0x00002000U
-#define GPIO_OTYPER_OT_14                    0x00004000U
-#define GPIO_OTYPER_OT_15                    0x00008000U
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
-#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
-#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
-#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
-#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
-#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
-#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
-#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
-#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
-#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
-#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
-#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
-#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
-#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
-#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
-#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
-#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
-#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
-#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
-#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
-#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
-#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
-#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
-#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
-#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
-#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
-#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
-#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
-#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
-#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
-#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
-#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
-#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
-#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
-#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
-#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
-#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
-#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
-#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
-#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
-#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
-#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
-#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
-#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
-#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
-#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
-#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
-#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    0x00000003U
-#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
-#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
-#define GPIO_PUPDR_PUPDR1                    0x0000000CU
-#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
-#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
-#define GPIO_PUPDR_PUPDR2                    0x00000030U
-#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
-#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
-#define GPIO_PUPDR_PUPDR3                    0x000000C0U
-#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
-#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
-#define GPIO_PUPDR_PUPDR4                    0x00000300U
-#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
-#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
-#define GPIO_PUPDR_PUPDR5                    0x00000C00U
-#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
-#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
-#define GPIO_PUPDR_PUPDR6                    0x00003000U
-#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
-#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
-#define GPIO_PUPDR_PUPDR7                    0x0000C000U
-#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
-#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
-#define GPIO_PUPDR_PUPDR8                    0x00030000U
-#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
-#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
-#define GPIO_PUPDR_PUPDR9                    0x000C0000U
-#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
-#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
-#define GPIO_PUPDR_PUPDR10                   0x00300000U
-#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
-#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
-#define GPIO_PUPDR_PUPDR11                   0x00C00000U
-#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
-#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
-#define GPIO_PUPDR_PUPDR12                   0x03000000U
-#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
-#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
-#define GPIO_PUPDR_PUPDR13                   0x0C000000U
-#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
-#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
-#define GPIO_PUPDR_PUPDR14                   0x30000000U
-#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
-#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
-#define GPIO_PUPDR_PUPDR15                   0xC0000000U
-#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
-#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       0x00000001U
-#define GPIO_IDR_IDR_1                       0x00000002U
-#define GPIO_IDR_IDR_2                       0x00000004U
-#define GPIO_IDR_IDR_3                       0x00000008U
-#define GPIO_IDR_IDR_4                       0x00000010U
-#define GPIO_IDR_IDR_5                       0x00000020U
-#define GPIO_IDR_IDR_6                       0x00000040U
-#define GPIO_IDR_IDR_7                       0x00000080U
-#define GPIO_IDR_IDR_8                       0x00000100U
-#define GPIO_IDR_IDR_9                       0x00000200U
-#define GPIO_IDR_IDR_10                      0x00000400U
-#define GPIO_IDR_IDR_11                      0x00000800U
-#define GPIO_IDR_IDR_12                      0x00001000U
-#define GPIO_IDR_IDR_13                      0x00002000U
-#define GPIO_IDR_IDR_14                      0x00004000U
-#define GPIO_IDR_IDR_15                      0x00008000U
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       0x00000001U
-#define GPIO_ODR_ODR_1                       0x00000002U
-#define GPIO_ODR_ODR_2                       0x00000004U
-#define GPIO_ODR_ODR_3                       0x00000008U
-#define GPIO_ODR_ODR_4                       0x00000010U
-#define GPIO_ODR_ODR_5                       0x00000020U
-#define GPIO_ODR_ODR_6                       0x00000040U
-#define GPIO_ODR_ODR_7                       0x00000080U
-#define GPIO_ODR_ODR_8                       0x00000100U
-#define GPIO_ODR_ODR_9                       0x00000200U
-#define GPIO_ODR_ODR_10                      0x00000400U
-#define GPIO_ODR_ODR_11                      0x00000800U
-#define GPIO_ODR_ODR_12                      0x00001000U
-#define GPIO_ODR_ODR_13                      0x00002000U
-#define GPIO_ODR_ODR_14                      0x00004000U
-#define GPIO_ODR_ODR_15                      0x00008000U
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       0x00000001U
-#define GPIO_BSRR_BS_1                       0x00000002U
-#define GPIO_BSRR_BS_2                       0x00000004U
-#define GPIO_BSRR_BS_3                       0x00000008U
-#define GPIO_BSRR_BS_4                       0x00000010U
-#define GPIO_BSRR_BS_5                       0x00000020U
-#define GPIO_BSRR_BS_6                       0x00000040U
-#define GPIO_BSRR_BS_7                       0x00000080U
-#define GPIO_BSRR_BS_8                       0x00000100U
-#define GPIO_BSRR_BS_9                       0x00000200U
-#define GPIO_BSRR_BS_10                      0x00000400U
-#define GPIO_BSRR_BS_11                      0x00000800U
-#define GPIO_BSRR_BS_12                      0x00001000U
-#define GPIO_BSRR_BS_13                      0x00002000U
-#define GPIO_BSRR_BS_14                      0x00004000U
-#define GPIO_BSRR_BS_15                      0x00008000U
-#define GPIO_BSRR_BR_0                       0x00010000U
-#define GPIO_BSRR_BR_1                       0x00020000U
-#define GPIO_BSRR_BR_2                       0x00040000U
-#define GPIO_BSRR_BR_3                       0x00080000U
-#define GPIO_BSRR_BR_4                       0x00100000U
-#define GPIO_BSRR_BR_5                       0x00200000U
-#define GPIO_BSRR_BR_6                       0x00400000U
-#define GPIO_BSRR_BR_7                       0x00800000U
-#define GPIO_BSRR_BR_8                       0x01000000U
-#define GPIO_BSRR_BR_9                       0x02000000U
-#define GPIO_BSRR_BR_10                      0x04000000U
-#define GPIO_BSRR_BR_11                      0x08000000U
-#define GPIO_BSRR_BR_12                      0x10000000U
-#define GPIO_BSRR_BR_13                      0x20000000U
-#define GPIO_BSRR_BR_14                      0x40000000U
-#define GPIO_BSRR_BR_15                      0x80000000U
-
-/****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0                       0x00000001U
-#define GPIO_LCKR_LCK1                       0x00000002U
-#define GPIO_LCKR_LCK2                       0x00000004U
-#define GPIO_LCKR_LCK3                       0x00000008U
-#define GPIO_LCKR_LCK4                       0x00000010U
-#define GPIO_LCKR_LCK5                       0x00000020U
-#define GPIO_LCKR_LCK6                       0x00000040U
-#define GPIO_LCKR_LCK7                       0x00000080U
-#define GPIO_LCKR_LCK8                       0x00000100U
-#define GPIO_LCKR_LCK9                       0x00000200U
-#define GPIO_LCKR_LCK10                      0x00000400U
-#define GPIO_LCKR_LCK11                      0x00000800U
-#define GPIO_LCKR_LCK12                      0x00001000U
-#define GPIO_LCKR_LCK13                      0x00002000U
-#define GPIO_LCKR_LCK14                      0x00004000U
-#define GPIO_LCKR_LCK15                      0x00008000U
-#define GPIO_LCKR_LCKK                       0x00010000U
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Inter-integrated Circuit Interface (I2C)              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define  I2C_CR1_PE                          0x00000001U        /*!< Peripheral enable                   */
-#define  I2C_CR1_TXIE                        0x00000002U        /*!< TX interrupt enable                 */
-#define  I2C_CR1_RXIE                        0x00000004U        /*!< RX interrupt enable                 */
-#define  I2C_CR1_ADDRIE                      0x00000008U        /*!< Address match interrupt enable      */
-#define  I2C_CR1_NACKIE                      0x00000010U        /*!< NACK received interrupt enable      */
-#define  I2C_CR1_STOPIE                      0x00000020U        /*!< STOP detection interrupt enable     */
-#define  I2C_CR1_TCIE                        0x00000040U        /*!< Transfer complete interrupt enable  */
-#define  I2C_CR1_ERRIE                       0x00000080U        /*!< Errors interrupt enable             */
-#define  I2C_CR1_DNF                         0x00000F00U        /*!< Digital noise filter                */
-#define  I2C_CR1_ANFOFF                      0x00001000U        /*!< Analog noise filter OFF             */
-#define  I2C_CR1_TXDMAEN                     0x00004000U        /*!< DMA transmission requests enable    */
-#define  I2C_CR1_RXDMAEN                     0x00008000U        /*!< DMA reception requests enable       */
-#define  I2C_CR1_SBC                         0x00010000U        /*!< Slave byte control                  */
-#define  I2C_CR1_NOSTRETCH                   0x00020000U        /*!< Clock stretching disable            */
-#define  I2C_CR1_GCEN                        0x00080000U        /*!< General call enable                 */
-#define  I2C_CR1_SMBHEN                      0x00100000U        /*!< SMBus host address enable           */
-#define  I2C_CR1_SMBDEN                      0x00200000U        /*!< SMBus device default address enable */
-#define  I2C_CR1_ALERTEN                     0x00400000U        /*!< SMBus alert enable                  */
-#define  I2C_CR1_PECEN                       0x00800000U        /*!< PEC enable                          */
-
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_SADD                        0x000003FFU        /*!< Slave address (master mode)                             */
-#define  I2C_CR2_RD_WRN                      0x00000400U        /*!< Transfer direction (master mode)                        */
-#define  I2C_CR2_ADD10                       0x00000800U        /*!< 10-bit addressing mode (master mode)                    */
-#define  I2C_CR2_HEAD10R                     0x00001000U        /*!< 10-bit address header only read direction (master mode) */
-#define  I2C_CR2_START                       0x00002000U        /*!< START generation                                        */
-#define  I2C_CR2_STOP                        0x00004000U        /*!< STOP generation (master mode)                           */
-#define  I2C_CR2_NACK                        0x00008000U        /*!< NACK generation (slave mode)                            */
-#define  I2C_CR2_NBYTES                      0x00FF0000U        /*!< Number of bytes                                         */
-#define  I2C_CR2_RELOAD                      0x01000000U        /*!< NBYTES reload mode                                      */
-#define  I2C_CR2_AUTOEND                     0x02000000U        /*!< Automatic end mode (master mode)                        */
-#define  I2C_CR2_PECBYTE                     0x04000000U        /*!< Packet error checking byte                              */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define  I2C_OAR1_OA1                        0x000003FFU        /*!< Interface own address 1   */
-#define  I2C_OAR1_OA1MODE                    0x00000400U        /*!< Own address 1 10-bit mode */
-#define  I2C_OAR1_OA1EN                      0x00008000U        /*!< Own address 1 enable      */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define  I2C_OAR2_OA2                        0x000000FEU        /*!< Interface own address 2 */
-#define  I2C_OAR2_OA2MSK                     0x00000700U        /*!< Own address 2 masks     */
-#define  I2C_OAR2_OA2NOMASK                  0x00000000U        /*!< No mask */
-#define  I2C_OAR2_OA2MASK01                  0x00000100U        /*!< OA2[1] is masked, Only OA2[7:2] are compared */
-#define  I2C_OAR2_OA2MASK02                  0x00000200U        /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
-#define  I2C_OAR2_OA2MASK03                  0x00000300U        /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
-#define  I2C_OAR2_OA2MASK04                  0x00000400U        /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
-#define  I2C_OAR2_OA2MASK05                  0x00000500U        /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
-#define  I2C_OAR2_OA2MASK06                  0x00000600U        /*!< OA2[6:1] is masked, Only OA2[7] are compared */
-#define  I2C_OAR2_OA2MASK07                  0x00000700U        /*!< OA2[7:1] is masked, No comparison is done */
-#define  I2C_OAR2_OA2EN                      0x00008000U        /*!< Own address 2 enable    */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define  I2C_TIMINGR_SCLL                    0x000000FFU        /*!< SCL low period (master mode)  */
-#define  I2C_TIMINGR_SCLH                    0x0000FF00U        /*!< SCL high period (master mode) */
-#define  I2C_TIMINGR_SDADEL                  0x000F0000U        /*!< Data hold time                */
-#define  I2C_TIMINGR_SCLDEL                  0x00F00000U        /*!< Data setup time               */
-#define  I2C_TIMINGR_PRESC                   0xF0000000U        /*!< Timings prescaler             */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define  I2C_TIMEOUTR_TIMEOUTA               0x00000FFFU        /*!< Bus timeout A                 */
-#define  I2C_TIMEOUTR_TIDLE                  0x00001000U        /*!< Idle clock timeout detection  */
-#define  I2C_TIMEOUTR_TIMOUTEN               0x00008000U        /*!< Clock timeout enable          */
-#define  I2C_TIMEOUTR_TIMEOUTB               0x0FFF0000U        /*!< Bus timeout B                 */
-#define  I2C_TIMEOUTR_TEXTEN                 0x80000000U        /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define  I2C_ISR_TXE                         0x00000001U        /*!< Transmit data register empty    */
-#define  I2C_ISR_TXIS                        0x00000002U        /*!< Transmit interrupt status       */
-#define  I2C_ISR_RXNE                        0x00000004U        /*!< Receive data register not empty */
-#define  I2C_ISR_ADDR                        0x00000008U        /*!< Address matched (slave mode)    */
-#define  I2C_ISR_NACKF                       0x00000010U        /*!< NACK received flag              */
-#define  I2C_ISR_STOPF                       0x00000020U        /*!< STOP detection flag             */
-#define  I2C_ISR_TC                          0x00000040U        /*!< Transfer complete (master mode) */
-#define  I2C_ISR_TCR                         0x00000080U        /*!< Transfer complete reload        */
-#define  I2C_ISR_BERR                        0x00000100U        /*!< Bus error                       */
-#define  I2C_ISR_ARLO                        0x00000200U        /*!< Arbitration lost                */
-#define  I2C_ISR_OVR                         0x00000400U        /*!< Overrun/Underrun                */
-#define  I2C_ISR_PECERR                      0x00000800U        /*!< PEC error in reception          */
-#define  I2C_ISR_TIMEOUT                     0x00001000U        /*!< Timeout or Tlow detection flag  */
-#define  I2C_ISR_ALERT                       0x00002000U        /*!< SMBus alert                     */
-#define  I2C_ISR_BUSY                        0x00008000U        /*!< Bus busy                        */
-#define  I2C_ISR_DIR                         0x00010000U        /*!< Transfer direction (slave mode) */
-#define  I2C_ISR_ADDCODE                     0x00FE0000U        /*!< Address match code (slave mode) */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define  I2C_ICR_ADDRCF                      0x00000008U        /*!< Address matched clear flag      */
-#define  I2C_ICR_NACKCF                      0x00000010U        /*!< NACK clear flag                 */
-#define  I2C_ICR_STOPCF                      0x00000020U        /*!< STOP detection clear flag       */
-#define  I2C_ICR_BERRCF                      0x00000100U        /*!< Bus error clear flag            */
-#define  I2C_ICR_ARLOCF                      0x00000200U        /*!< Arbitration lost clear flag     */
-#define  I2C_ICR_OVRCF                       0x00000400U        /*!< Overrun/Underrun clear flag     */
-#define  I2C_ICR_PECCF                       0x00000800U        /*!< PAC error clear flag            */
-#define  I2C_ICR_TIMOUTCF                    0x00001000U        /*!< Timeout clear flag              */
-#define  I2C_ICR_ALERTCF                     0x00002000U        /*!< Alert clear flag                */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define  I2C_PECR_PEC                        0x000000FFU        /*!< PEC register        */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define  I2C_RXDR_RXDATA                     0x000000FFU        /*!< 8-bit receive data  */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define  I2C_TXDR_TXDATA                     0x000000FFU        /*!< 8-bit transmit data */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Independent WATCHDOG                             */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         0x01U               /*!< Watchdog prescaler value update */
-#define  IWDG_SR_RVU                         0x02U               /*!< Watchdog counter reload value update */
-#define  IWDG_SR_WVU                         0x04U               /*!< Watchdog counter window value update */
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_WINR_WIN                       0x0FFFU             /*!< Watchdog counter window value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      LCD-TFT Display Controller (LTDC)                     */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for LTDC_SSCR register  *****************/
-
-#define LTDC_SSCR_VSH                       0x000007FFU              /*!< Vertical Synchronization Height  */
-#define LTDC_SSCR_HSW                       0x0FFF0000U              /*!< Horizontal Synchronization Width */
-
-/********************  Bit definition for LTDC_BPCR register  *****************/
-
-#define LTDC_BPCR_AVBP                      0x000007FFU              /*!< Accumulated Vertical Back Porch   */
-#define LTDC_BPCR_AHBP                      0x0FFF0000U              /*!< Accumulated Horizontal Back Porch */
-
-/********************  Bit definition for LTDC_AWCR register  *****************/
-
-#define LTDC_AWCR_AAH                       0x000007FFU              /*!< Accumulated Active heigh */
-#define LTDC_AWCR_AAW                       0x0FFF0000U              /*!< Accumulated Active Width */
-
-/********************  Bit definition for LTDC_TWCR register  *****************/
-
-#define LTDC_TWCR_TOTALH                    0x000007FFU              /*!< Total Heigh */
-#define LTDC_TWCR_TOTALW                    0x0FFF0000U              /*!< Total Width */
-
-/********************  Bit definition for LTDC_GCR register  ******************/
-
-#define LTDC_GCR_LTDCEN                     0x00000001U              /*!< LCD-TFT controller enable bit       */
-#define LTDC_GCR_DBW                        0x00000070U              /*!< Dither Blue Width                   */
-#define LTDC_GCR_DGW                        0x00000700U              /*!< Dither Green Width                  */
-#define LTDC_GCR_DRW                        0x00007000U              /*!< Dither Red Width                    */
-#define LTDC_GCR_DEN                        0x00010000U              /*!< Dither Enable                       */
-#define LTDC_GCR_PCPOL                      0x10000000U              /*!< Pixel Clock Polarity                */
-#define LTDC_GCR_DEPOL                      0x20000000U              /*!< Data Enable Polarity                */
-#define LTDC_GCR_VSPOL                      0x40000000U              /*!< Vertical Synchronization Polarity   */
-#define LTDC_GCR_HSPOL                      0x80000000U              /*!< Horizontal Synchronization Polarity */
-
-
-/********************  Bit definition for LTDC_SRCR register  *****************/
-
-#define LTDC_SRCR_IMR                      0x00000001U               /*!< Immediate Reload         */
-#define LTDC_SRCR_VBR                      0x00000002U               /*!< Vertical Blanking Reload */
-
-/********************  Bit definition for LTDC_BCCR register  *****************/
-
-#define LTDC_BCCR_BCBLUE                    0x000000FFU              /*!< Background Blue value  */
-#define LTDC_BCCR_BCGREEN                   0x0000FF00U              /*!< Background Green value */
-#define LTDC_BCCR_BCRED                     0x00FF0000U              /*!< Background Red value   */
-
-/********************  Bit definition for LTDC_IER register  ******************/
-
-#define LTDC_IER_LIE                        0x00000001U              /*!< Line Interrupt Enable            */
-#define LTDC_IER_FUIE                       0x00000002U              /*!< FIFO Underrun Interrupt Enable   */
-#define LTDC_IER_TERRIE                     0x00000004U              /*!< Transfer Error Interrupt Enable  */
-#define LTDC_IER_RRIE                       0x00000008U              /*!< Register Reload interrupt enable */
-
-/********************  Bit definition for LTDC_ISR register  ******************/
-
-#define LTDC_ISR_LIF                        0x00000001U              /*!< Line Interrupt Flag */
-#define LTDC_ISR_FUIF                       0x00000002U              /*!< FIFO Underrun Interrupt Flag */
-#define LTDC_ISR_TERRIF                     0x00000004U              /*!< Transfer Error Interrupt Flag */
-#define LTDC_ISR_RRIF                       0x00000008U              /*!< Register Reload interrupt Flag */
-
-/********************  Bit definition for LTDC_ICR register  ******************/
-
-#define LTDC_ICR_CLIF                       0x00000001U              /*!< Clears the Line Interrupt Flag */
-#define LTDC_ICR_CFUIF                      0x00000002U              /*!< Clears the FIFO Underrun Interrupt Flag */
-#define LTDC_ICR_CTERRIF                    0x00000004U              /*!< Clears the Transfer Error Interrupt Flag */
-#define LTDC_ICR_CRRIF                      0x00000008U              /*!< Clears Register Reload interrupt Flag */
-
-/********************  Bit definition for LTDC_LIPCR register  ****************/
-
-#define LTDC_LIPCR_LIPOS                    0x000007FFU              /*!< Line Interrupt Position */
-
-/********************  Bit definition for LTDC_CPSR register  *****************/
-
-#define LTDC_CPSR_CYPOS                     0x0000FFFFU              /*!< Current Y Position */
-#define LTDC_CPSR_CXPOS                     0xFFFF0000U              /*!< Current X Position */
-
-/********************  Bit definition for LTDC_CDSR register  *****************/
-
-#define LTDC_CDSR_VDES                      0x00000001U              /*!< Vertical Data Enable Status       */
-#define LTDC_CDSR_HDES                      0x00000002U              /*!< Horizontal Data Enable Status     */
-#define LTDC_CDSR_VSYNCS                    0x00000004U              /*!< Vertical Synchronization Status   */
-#define LTDC_CDSR_HSYNCS                    0x00000008U              /*!< Horizontal Synchronization Status */
-
-/********************  Bit definition for LTDC_LxCR register  *****************/
-
-#define LTDC_LxCR_LEN                       0x00000001U              /*!< Layer Enable              */
-#define LTDC_LxCR_COLKEN                    0x00000002U              /*!< Color Keying Enable       */
-#define LTDC_LxCR_CLUTEN                    0x00000010U              /*!< Color Lockup Table Enable */
-
-/********************  Bit definition for LTDC_LxWHPCR register  **************/
-
-#define LTDC_LxWHPCR_WHSTPOS                0x00000FFFU              /*!< Window Horizontal Start Position */
-#define LTDC_LxWHPCR_WHSPPOS                0xFFFF0000U              /*!< Window Horizontal Stop Position  */
-
-/********************  Bit definition for LTDC_LxWVPCR register  **************/
-
-#define LTDC_LxWVPCR_WVSTPOS                0x00000FFFU              /*!< Window Vertical Start Position */
-#define LTDC_LxWVPCR_WVSPPOS                0xFFFF0000U              /*!< Window Vertical Stop Position  */
-
-/********************  Bit definition for LTDC_LxCKCR register  ***************/
-
-#define LTDC_LxCKCR_CKBLUE                  0x000000FFU              /*!< Color Key Blue value  */
-#define LTDC_LxCKCR_CKGREEN                 0x0000FF00U              /*!< Color Key Green value */
-#define LTDC_LxCKCR_CKRED                   0x00FF0000U              /*!< Color Key Red value   */
-
-/********************  Bit definition for LTDC_LxPFCR register  ***************/
-
-#define LTDC_LxPFCR_PF                      0x00000007U              /*!< Pixel Format */
-
-/********************  Bit definition for LTDC_LxCACR register  ***************/
-
-#define LTDC_LxCACR_CONSTA                  0x000000FFU              /*!< Constant Alpha */
-
-/********************  Bit definition for LTDC_LxDCCR register  ***************/
-
-#define LTDC_LxDCCR_DCBLUE                  0x000000FFU              /*!< Default Color Blue  */
-#define LTDC_LxDCCR_DCGREEN                 0x0000FF00U              /*!< Default Color Green */
-#define LTDC_LxDCCR_DCRED                   0x00FF0000U              /*!< Default Color Red   */
-#define LTDC_LxDCCR_DCALPHA                 0xFF000000U              /*!< Default Color Alpha */
-                                
-/********************  Bit definition for LTDC_LxBFCR register  ***************/
-
-#define LTDC_LxBFCR_BF2                     0x00000007U              /*!< Blending Factor 2 */
-#define LTDC_LxBFCR_BF1                     0x00000700U              /*!< Blending Factor 1 */
-
-/********************  Bit definition for LTDC_LxCFBAR register  **************/
-
-#define LTDC_LxCFBAR_CFBADD                 0xFFFFFFFFU              /*!< Color Frame Buffer Start Address */
-
-/********************  Bit definition for LTDC_LxCFBLR register  **************/
-
-#define LTDC_LxCFBLR_CFBLL                  0x00001FFFU              /*!< Color Frame Buffer Line Length    */
-#define LTDC_LxCFBLR_CFBP                   0x1FFF0000U              /*!< Color Frame Buffer Pitch in bytes */
-
-/********************  Bit definition for LTDC_LxCFBLNR register  *************/
-
-#define LTDC_LxCFBLNR_CFBLNBR               0x000007FFU              /*!< Frame Buffer Line Number */
-
-/********************  Bit definition for LTDC_LxCLUTWR register  *************/
-
-#define LTDC_LxCLUTWR_BLUE                  0x000000FFU              /*!< Blue value   */
-#define LTDC_LxCLUTWR_GREEN                 0x0000FF00U              /*!< Green value  */
-#define LTDC_LxCLUTWR_RED                   0x00FF0000U              /*!< Red value    */
-#define LTDC_LxCLUTWR_CLUTADD               0xFF000000U              /*!< CLUT address */
-
-/******************************************************************************/
-/*                                                                            */
-/*                             Power Control                                  */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for PWR_CR1 register  ********************/
-#define  PWR_CR1_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
-#define  PWR_CR1_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
-#define  PWR_CR1_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
-#define  PWR_CR1_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
-#define  PWR_CR1_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR1_PLS_0                        0x00000020U     /*!< Bit 0 */
-#define  PWR_CR1_PLS_1                        0x00000040U     /*!< Bit 1 */
-#define  PWR_CR1_PLS_2                        0x00000080U     /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define  PWR_CR1_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
-#define  PWR_CR1_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
-#define  PWR_CR1_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
-#define  PWR_CR1_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
-#define  PWR_CR1_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
-#define  PWR_CR1_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
-#define  PWR_CR1_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
-#define  PWR_CR1_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
-#define  PWR_CR1_DBP                          0x00000100U     /*!< Disable Backup Domain write protection                     */
-#define  PWR_CR1_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                              */
-#define  PWR_CR1_LPUDS                        0x00000400U     /*!< Low-power regulator in deepsleep under-drive mode          */
-#define  PWR_CR1_MRUDS                        0x00000800U     /*!< Main regulator in deepsleep under-drive mode               */
-#define  PWR_CR1_ADCDC1                       0x00002000U     /*!< Refer to AN4073 on how to use this bit */ 
-#define  PWR_CR1_VOS                          0x0000C000U     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
-#define  PWR_CR1_VOS_0                        0x00004000U     /*!< Bit 0 */
-#define  PWR_CR1_VOS_1                        0x00008000U     /*!< Bit 1 */
-#define  PWR_CR1_ODEN                         0x00010000U     /*!< Over Drive enable                   */
-#define  PWR_CR1_ODSWEN                       0x00020000U     /*!< Over Drive switch enabled           */
-#define  PWR_CR1_UDEN                         0x000C0000U     /*!< Under Drive enable in stop mode     */
-#define  PWR_CR1_UDEN_0                       0x00040000U     /*!< Bit 0                               */
-#define  PWR_CR1_UDEN_1                       0x00080000U     /*!< Bit 1                               */
-
-/*******************  Bit definition for PWR_CSR1 register  ********************/
-#define  PWR_CSR1_WUIF                        0x00000001U     /*!< Wake up internal Flag                            */
-#define  PWR_CSR1_SBF                         0x00000002U     /*!< Standby Flag                                     */
-#define  PWR_CSR1_PVDO                        0x00000004U     /*!< PVD Output                                       */
-#define  PWR_CSR1_BRR                         0x00000008U     /*!< Backup regulator ready                           */
-#define  PWR_CSR1_EIWUP                       0x00000100U     /*!< Enable internal wakeup                           */
-#define  PWR_CSR1_BRE                         0x00000200U     /*!< Backup regulator enable                          */
-#define  PWR_CSR1_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
-#define  PWR_CSR1_ODRDY                       0x00010000U     /*!< Over Drive generator ready                       */
-#define  PWR_CSR1_ODSWRDY                     0x00020000U     /*!< Over Drive Switch ready                          */
-#define  PWR_CSR1_UDRDY                       0x000C0000U     /*!< Under Drive ready                                */
-
-
-/********************  Bit definition for PWR_CR2 register  ********************/
-#define  PWR_CR2_CWUPF1                         0x00000001U     /*!< Clear Wakeup Pin Flag for PA0      */
-#define  PWR_CR2_CWUPF2                         0x00000002U     /*!< Clear Wakeup Pin Flag for PA2      */
-#define  PWR_CR2_CWUPF3                         0x00000004U     /*!< Clear Wakeup Pin Flag for PC1      */
-#define  PWR_CR2_CWUPF4                         0x00000008U     /*!< Clear Wakeup Pin Flag for PC13     */
-#define  PWR_CR2_CWUPF5                         0x00000010U     /*!< Clear Wakeup Pin Flag for PI8      */
-#define  PWR_CR2_CWUPF6                         0x00000020U     /*!< Clear Wakeup Pin Flag for PI11     */
-#define  PWR_CR2_WUPP1                          0x00000100U     /*!< Wakeup Pin Polarity bit for PA0    */
-#define  PWR_CR2_WUPP2                          0x00000200U     /*!< Wakeup Pin Polarity bit for PA2    */
-#define  PWR_CR2_WUPP3                          0x00000400U     /*!< Wakeup Pin Polarity bit for PC1    */
-#define  PWR_CR2_WUPP4                          0x00000800U     /*!< Wakeup Pin Polarity bit for PC13   */
-#define  PWR_CR2_WUPP5                          0x00001000U     /*!< Wakeup Pin Polarity bit for PI8    */
-#define  PWR_CR2_WUPP6                          0x00002000U     /*!< Wakeup Pin Polarity bit for PI11   */
-
-/*******************  Bit definition for PWR_CSR2 register  ********************/
-#define  PWR_CSR2_WUPF1                         0x00000001U     /*!< Wakeup Pin Flag for PA0            */
-#define  PWR_CSR2_WUPF2                         0x00000002U     /*!< Wakeup Pin Flag for PA2            */
-#define  PWR_CSR2_WUPF3                         0x00000004U     /*!< Wakeup Pin Flag for PC1            */
-#define  PWR_CSR2_WUPF4                         0x00000008U     /*!< Wakeup Pin Flag for PC13           */
-#define  PWR_CSR2_WUPF5                         0x00000010U     /*!< Wakeup Pin Flag for PI8            */
-#define  PWR_CSR2_WUPF6                         0x00000020U     /*!< Wakeup Pin Flag for PI11           */
-#define  PWR_CSR2_EWUP1                         0x00000100U     /*!< Enable Wakeup Pin PA0              */
-#define  PWR_CSR2_EWUP2                         0x00000200U     /*!< Enable Wakeup Pin PA2              */
-#define  PWR_CSR2_EWUP3                         0x00000400U     /*!< Enable Wakeup Pin PC1              */
-#define  PWR_CSR2_EWUP4                         0x00000800U     /*!< Enable Wakeup Pin PC13             */
-#define  PWR_CSR2_EWUP5                         0x00001000U     /*!< Enable Wakeup Pin PI8              */
-#define  PWR_CSR2_EWUP6                         0x00002000U     /*!< Enable Wakeup Pin PI11             */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    QUADSPI                                 */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for QUADSPI_CR register  *******************/
-#define  QUADSPI_CR_EN                           0x00000001U            /*!< Enable                            */
-#define  QUADSPI_CR_ABORT                        0x00000002U            /*!< Abort request                     */
-#define  QUADSPI_CR_DMAEN                        0x00000004U            /*!< DMA Enable                        */
-#define  QUADSPI_CR_TCEN                         0x00000008U            /*!< Timeout Counter Enable            */
-#define  QUADSPI_CR_SSHIFT                       0x00000010U            /*!< Sample Shift                      */
-#define  QUADSPI_CR_DFM                          0x00000040U            /*!< Dual Flash Mode                   */
-#define  QUADSPI_CR_FSEL                         0x00000080U            /*!< Flash Select                      */
-#define  QUADSPI_CR_FTHRES                       0x00001F00U            /*!< FTHRES[4:0] FIFO Level            */
-#define  QUADSPI_CR_FTHRES_0                     0x00000100U            /*!< Bit 0 */
-#define  QUADSPI_CR_FTHRES_1                     0x00000200U            /*!< Bit 1 */
-#define  QUADSPI_CR_FTHRES_2                     0x00000400U            /*!< Bit 2 */
-#define  QUADSPI_CR_FTHRES_3                     0x00000800U            /*!< Bit 3 */
-#define  QUADSPI_CR_FTHRES_4                     0x00001000U            /*!< Bit 4 */
-#define  QUADSPI_CR_TEIE                         0x00010000U            /*!< Transfer Error Interrupt Enable    */
-#define  QUADSPI_CR_TCIE                         0x00020000U            /*!< Transfer Complete Interrupt Enable */
-#define  QUADSPI_CR_FTIE                         0x00040000U            /*!< FIFO Threshold Interrupt Enable    */
-#define  QUADSPI_CR_SMIE                         0x00080000U            /*!< Status Match Interrupt Enable      */
-#define  QUADSPI_CR_TOIE                         0x00100000U            /*!< TimeOut Interrupt Enable           */
-#define  QUADSPI_CR_APMS                         0x00400000U            /*!< Bit 1                              */
-#define  QUADSPI_CR_PMM                          0x00800000U            /*!< Polling Match Mode                 */
-#define  QUADSPI_CR_PRESCALER                    0xFF000000U            /*!< PRESCALER[7:0] Clock prescaler     */
-#define  QUADSPI_CR_PRESCALER_0                  0x01000000U            /*!< Bit 0 */
-#define  QUADSPI_CR_PRESCALER_1                  0x02000000U            /*!< Bit 1 */
-#define  QUADSPI_CR_PRESCALER_2                  0x04000000U            /*!< Bit 2 */
-#define  QUADSPI_CR_PRESCALER_3                  0x08000000U            /*!< Bit 3 */
-#define  QUADSPI_CR_PRESCALER_4                  0x10000000U            /*!< Bit 4 */
-#define  QUADSPI_CR_PRESCALER_5                  0x20000000U            /*!< Bit 5 */
-#define  QUADSPI_CR_PRESCALER_6                  0x40000000U            /*!< Bit 6 */
-#define  QUADSPI_CR_PRESCALER_7                  0x80000000U            /*!< Bit 7 */
-
-/*****************  Bit definition for QUADSPI_DCR register  ******************/
-#define  QUADSPI_DCR_CKMODE                      0x00000001U            /*!< Mode 0 / Mode 3                 */
-#define  QUADSPI_DCR_CSHT                        0x00000700U            /*!< CSHT[2:0]: ChipSelect High Time */
-#define  QUADSPI_DCR_CSHT_0                      0x00000100U            /*!< Bit 0 */
-#define  QUADSPI_DCR_CSHT_1                      0x00000200U            /*!< Bit 1 */
-#define  QUADSPI_DCR_CSHT_2                      0x00000400U            /*!< Bit 2 */
-#define  QUADSPI_DCR_FSIZE                       0x001F0000U            /*!< FSIZE[4:0]: Flash Size          */
-#define  QUADSPI_DCR_FSIZE_0                     0x00010000U            /*!< Bit 0 */
-#define  QUADSPI_DCR_FSIZE_1                     0x00020000U            /*!< Bit 1 */
-#define  QUADSPI_DCR_FSIZE_2                     0x00040000U            /*!< Bit 2 */
-#define  QUADSPI_DCR_FSIZE_3                     0x00080000U            /*!< Bit 3 */
-#define  QUADSPI_DCR_FSIZE_4                     0x00100000U            /*!< Bit 4 */
-
-/******************  Bit definition for QUADSPI_SR register  *******************/
-#define  QUADSPI_SR_TEF                          0x00000001U             /*!< Transfer Error Flag    */
-#define  QUADSPI_SR_TCF                          0x00000002U             /*!< Transfer Complete Flag */
-#define  QUADSPI_SR_FTF                          0x00000004U             /*!< FIFO Threshlod Flag    */
-#define  QUADSPI_SR_SMF                          0x00000008U             /*!< Status Match Flag      */
-#define  QUADSPI_SR_TOF                          0x00000010U             /*!< Timeout Flag           */
-#define  QUADSPI_SR_BUSY                         0x00000020U             /*!< Busy                   */
-#define  QUADSPI_SR_FLEVEL                       0x00001F00U             /*!< FIFO Threshlod Flag    */
-#define  QUADSPI_SR_FLEVEL_0                     0x00000100U             /*!< Bit 0 */
-#define  QUADSPI_SR_FLEVEL_1                     0x00000200U             /*!< Bit 1 */
-#define  QUADSPI_SR_FLEVEL_2                     0x00000400U             /*!< Bit 2 */
-#define  QUADSPI_SR_FLEVEL_3                     0x00000800U             /*!< Bit 3 */
-#define  QUADSPI_SR_FLEVEL_4                     0x00001000U             /*!< Bit 4 */
-
-/******************  Bit definition for QUADSPI_FCR register  ******************/
-#define  QUADSPI_FCR_CTEF                        0x00000001U             /*!< Clear Transfer Error Flag    */
-#define  QUADSPI_FCR_CTCF                        0x00000002U             /*!< Clear Transfer Complete Flag */
-#define  QUADSPI_FCR_CSMF                        0x00000008U             /*!< Clear Status Match Flag      */
-#define  QUADSPI_FCR_CTOF                        0x00000010U             /*!< Clear Timeout Flag           */
-
-/******************  Bit definition for QUADSPI_DLR register  ******************/
-#define  QUADSPI_DLR_DL                          0xFFFFFFFFU             /*!< DL[31:0]: Data Length */
-
-/******************  Bit definition for QUADSPI_CCR register  ******************/
-#define  QUADSPI_CCR_INSTRUCTION                  0x000000FFU            /*!< INSTRUCTION[7:0]: Instruction    */
-#define  QUADSPI_CCR_INSTRUCTION_0                0x00000001U            /*!< Bit 0 */
-#define  QUADSPI_CCR_INSTRUCTION_1                0x00000002U            /*!< Bit 1 */
-#define  QUADSPI_CCR_INSTRUCTION_2                0x00000004U            /*!< Bit 2 */
-#define  QUADSPI_CCR_INSTRUCTION_3                0x00000008U            /*!< Bit 3 */
-#define  QUADSPI_CCR_INSTRUCTION_4                0x00000010U            /*!< Bit 4 */
-#define  QUADSPI_CCR_INSTRUCTION_5                0x00000020U            /*!< Bit 5 */
-#define  QUADSPI_CCR_INSTRUCTION_6                0x00000040U            /*!< Bit 6 */
-#define  QUADSPI_CCR_INSTRUCTION_7                0x00000080U            /*!< Bit 7 */
-#define  QUADSPI_CCR_IMODE                        0x00000300U            /*!< IMODE[1:0]: Instruction Mode      */
-#define  QUADSPI_CCR_IMODE_0                      0x00000100U            /*!< Bit 0 */
-#define  QUADSPI_CCR_IMODE_1                      0x00000200U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ADMODE                       0x00000C00U            /*!< ADMODE[1:0]: Address Mode         */
-#define  QUADSPI_CCR_ADMODE_0                     0x00000400U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ADMODE_1                     0x00000800U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ADSIZE                       0x00003000U            /*!< ADSIZE[1:0]: Address Size         */
-#define  QUADSPI_CCR_ADSIZE_0                     0x00001000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ADSIZE_1                     0x00002000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ABMODE                       0x0000C000U            /*!< ABMODE[1:0]: Alternate Bytes Mode */
-#define  QUADSPI_CCR_ABMODE_0                     0x00004000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ABMODE_1                     0x00008000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_ABSIZE                       0x00030000U            /*!< ABSIZE[1:0]: Instruction Mode     */
-#define  QUADSPI_CCR_ABSIZE_0                     0x00010000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_ABSIZE_1                     0x00020000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_DCYC                         0x007C0000U            /*!< DCYC[4:0]: Dummy Cycles           */
-#define  QUADSPI_CCR_DCYC_0                       0x00040000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_DCYC_1                       0x00080000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_DCYC_2                       0x00100000U            /*!< Bit 2 */
-#define  QUADSPI_CCR_DCYC_3                       0x00200000U            /*!< Bit 3 */
-#define  QUADSPI_CCR_DCYC_4                       0x00400000U            /*!< Bit 4 */
-#define  QUADSPI_CCR_DMODE                        0x03000000U            /*!< DMODE[1:0]: Data Mode              */
-#define  QUADSPI_CCR_DMODE_0                      0x01000000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_DMODE_1                      0x02000000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_FMODE                        0x0C000000U            /*!< FMODE[1:0]: Functional Mode        */
-#define  QUADSPI_CCR_FMODE_0                      0x04000000U            /*!< Bit 0 */
-#define  QUADSPI_CCR_FMODE_1                      0x08000000U            /*!< Bit 1 */
-#define  QUADSPI_CCR_SIOO                         0x10000000U            /*!< SIOO: Send Instruction Only Once Mode */
-#define  QUADSPI_CCR_DHHC                         0x40000000U            /*!< DHHC: Delay Half Hclk Cycle           */
-#define  QUADSPI_CCR_DDRM                         0x80000000U            /*!< DDRM: Double Data Rate Mode           */ 
-/******************  Bit definition for QUADSPI_AR register  *******************/
-#define  QUADSPI_AR_ADDRESS                       0xFFFFFFFFU            /*!< ADDRESS[31:0]: Address */
-
-/******************  Bit definition for QUADSPI_ABR register  ******************/
-#define  QUADSPI_ABR_ALTERNATE                    0xFFFFFFFFU            /*!< ALTERNATE[31:0]: Alternate Bytes */
-
-/******************  Bit definition for QUADSPI_DR register  *******************/
-#define  QUADSPI_DR_DATA                          0xFFFFFFFFU            /*!< DATA[31:0]: Data */
-
-/******************  Bit definition for QUADSPI_PSMKR register  ****************/
-#define  QUADSPI_PSMKR_MASK                       0xFFFFFFFFU            /*!< MASK[31:0]: Status Mask */
-
-/******************  Bit definition for QUADSPI_PSMAR register  ****************/
-#define  QUADSPI_PSMAR_MATCH                      0xFFFFFFFFU            /*!< MATCH[31:0]: Status Match */
-
-/******************  Bit definition for QUADSPI_PIR register  *****************/
-#define  QUADSPI_PIR_INTERVAL                     0x0000FFFFU            /*!< INTERVAL[15:0]: Polling Interval */
-
-/******************  Bit definition for QUADSPI_LPTR register  *****************/
-#define  QUADSPI_LPTR_TIMEOUT                     0x0000FFFFU            /*!< TIMEOUT[15:0]: Timeout period */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        0x00000001U
-#define  RCC_CR_HSIRDY                       0x00000002U
-#define  RCC_CR_HSITRIM                      0x000000F8U
-#define  RCC_CR_HSITRIM_0                    0x00000008U /*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    0x00000010U /*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    0x00000020U /*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    0x00000040U /*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    0x00000080U /*!<Bit 4 */
-#define  RCC_CR_HSICAL                       0x0000FF00U
-#define  RCC_CR_HSICAL_0                     0x00000100U /*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     0x00000200U /*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     0x00000400U /*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     0x00000800U /*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     0x00001000U /*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     0x00002000U /*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     0x00004000U /*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     0x00008000U /*!<Bit 7 */
-#define  RCC_CR_HSEON                        0x00010000U
-#define  RCC_CR_HSERDY                       0x00020000U
-#define  RCC_CR_HSEBYP                       0x00040000U
-#define  RCC_CR_CSSON                        0x00080000U
-#define  RCC_CR_PLLON                        0x01000000U
-#define  RCC_CR_PLLRDY                       0x02000000U
-#define  RCC_CR_PLLI2SON                     0x04000000U
-#define  RCC_CR_PLLI2SRDY                    0x08000000U
-#define  RCC_CR_PLLSAION                     0x10000000U
-#define  RCC_CR_PLLSAIRDY                    0x20000000U
-
-/********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    0x0000003FU
-#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
-#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
-#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
-#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
-#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
-#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
-#define  RCC_PLLCFGR_PLLN                    0x00007FC0U
-#define  RCC_PLLCFGR_PLLN_0                  0x00000040U
-#define  RCC_PLLCFGR_PLLN_1                  0x00000080U
-#define  RCC_PLLCFGR_PLLN_2                  0x00000100U
-#define  RCC_PLLCFGR_PLLN_3                  0x00000200U
-#define  RCC_PLLCFGR_PLLN_4                  0x00000400U
-#define  RCC_PLLCFGR_PLLN_5                  0x00000800U
-#define  RCC_PLLCFGR_PLLN_6                  0x00001000U
-#define  RCC_PLLCFGR_PLLN_7                  0x00002000U
-#define  RCC_PLLCFGR_PLLN_8                  0x00004000U
-#define  RCC_PLLCFGR_PLLP                    0x00030000U
-#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
-#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
-#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
-#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
-#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
-#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
-#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
-#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
-#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
-
-#define  RCC_PLLCFGR_PLLR                    0x70000000U
-#define  RCC_PLLCFGR_PLLR_0                  0x10000000U
-#define  RCC_PLLCFGR_PLLR_1                  0x20000000U
-#define  RCC_PLLCFGR_PLLR_2                  0x40000000U
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-/*!< SW configuration */
-#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
-#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
-#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
-
-#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
-
-/*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     0x001F0000U
-#define  RCC_CFGR_RTCPRE_0                   0x00010000U
-#define  RCC_CFGR_RTCPRE_1                   0x00020000U
-#define  RCC_CFGR_RTCPRE_2                   0x00040000U
-#define  RCC_CFGR_RTCPRE_3                   0x00080000U
-#define  RCC_CFGR_RTCPRE_4                   0x00100000U
-
-/*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       0x00600000U
-#define  RCC_CFGR_MCO1_0                     0x00200000U
-#define  RCC_CFGR_MCO1_1                     0x00400000U
-
-#define  RCC_CFGR_I2SSRC                     0x00800000U
-
-#define  RCC_CFGR_MCO1PRE                    0x07000000U
-#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
-#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
-#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
-
-#define  RCC_CFGR_MCO2PRE                    0x38000000U
-#define  RCC_CFGR_MCO2PRE_0                  0x08000000U
-#define  RCC_CFGR_MCO2PRE_1                  0x10000000U
-#define  RCC_CFGR_MCO2PRE_2                  0x20000000U
-
-#define  RCC_CFGR_MCO2                       0xC0000000U
-#define  RCC_CFGR_MCO2_0                     0x40000000U
-#define  RCC_CFGR_MCO2_1                     0x80000000U
-
-/********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     0x00000001U
-#define  RCC_CIR_LSERDYF                     0x00000002U
-#define  RCC_CIR_HSIRDYF                     0x00000004U
-#define  RCC_CIR_HSERDYF                     0x00000008U
-#define  RCC_CIR_PLLRDYF                     0x00000010U
-#define  RCC_CIR_PLLI2SRDYF                  0x00000020U
-#define  RCC_CIR_PLLSAIRDYF                  0x00000040U
-#define  RCC_CIR_CSSF                        0x00000080U
-#define  RCC_CIR_LSIRDYIE                    0x00000100U
-#define  RCC_CIR_LSERDYIE                    0x00000200U
-#define  RCC_CIR_HSIRDYIE                    0x00000400U
-#define  RCC_CIR_HSERDYIE                    0x00000800U
-#define  RCC_CIR_PLLRDYIE                    0x00001000U
-#define  RCC_CIR_PLLI2SRDYIE                 0x00002000U
-#define  RCC_CIR_PLLSAIRDYIE                 0x00004000U
-#define  RCC_CIR_LSIRDYC                     0x00010000U
-#define  RCC_CIR_LSERDYC                     0x00020000U
-#define  RCC_CIR_HSIRDYC                     0x00040000U
-#define  RCC_CIR_HSERDYC                     0x00080000U
-#define  RCC_CIR_PLLRDYC                     0x00100000U
-#define  RCC_CIR_PLLI2SRDYC                  0x00200000U
-#define  RCC_CIR_PLLSAIRDYC                  0x00400000U
-#define  RCC_CIR_CSSC                        0x00800000U
-
-/********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
-#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
-#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
-#define  RCC_AHB1RSTR_GPIODRST               0x00000008U
-#define  RCC_AHB1RSTR_GPIOERST               0x00000010U
-#define  RCC_AHB1RSTR_GPIOFRST               0x00000020U
-#define  RCC_AHB1RSTR_GPIOGRST               0x00000040U
-#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
-#define  RCC_AHB1RSTR_GPIOIRST               0x00000100U
-#define  RCC_AHB1RSTR_GPIOJRST               0x00000200U
-#define  RCC_AHB1RSTR_GPIOKRST               0x00000400U
-#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
-#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
-#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
-#define  RCC_AHB1RSTR_DMA2DRST               0x00800000U
-#define  RCC_AHB1RSTR_ETHMACRST              0x02000000U
-#define  RCC_AHB1RSTR_OTGHRST                0x20000000U
-
-/********************  Bit definition for RCC_AHB2RSTR register  **************/
-#define  RCC_AHB2RSTR_DCMIRST                0x00000001U
-#define  RCC_AHB2RSTR_JPEGRST                0x00000002U
-#define  RCC_AHB2RSTR_RNGRST                 0x00000040U
-#define  RCC_AHB2RSTR_OTGFSRST               0x00000080U
-
-/********************  Bit definition for RCC_AHB3RSTR register  **************/
-
-#define  RCC_AHB3RSTR_FMCRST                 0x00000001U
-#define  RCC_AHB3RSTR_QSPIRST                0x00000002U
-
-/********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM2RST                0x00000001U
-#define  RCC_APB1RSTR_TIM3RST                0x00000002U
-#define  RCC_APB1RSTR_TIM4RST                0x00000004U
-#define  RCC_APB1RSTR_TIM5RST                0x00000008U
-#define  RCC_APB1RSTR_TIM6RST                0x00000010U
-#define  RCC_APB1RSTR_TIM7RST                0x00000020U
-#define  RCC_APB1RSTR_TIM12RST               0x00000040U
-#define  RCC_APB1RSTR_TIM13RST               0x00000080U
-#define  RCC_APB1RSTR_TIM14RST               0x00000100U
-#define  RCC_APB1RSTR_LPTIM1RST              0x00000200U
-#define  RCC_APB1RSTR_WWDGRST                0x00000800U
-#define  RCC_APB1RSTR_CAN3RST                0x00002000U
-#define  RCC_APB1RSTR_SPI2RST                0x00004000U
-#define  RCC_APB1RSTR_SPI3RST                0x00008000U
-#define  RCC_APB1RSTR_SPDIFRXRST             0x00010000U
-#define  RCC_APB1RSTR_USART2RST              0x00020000U
-#define  RCC_APB1RSTR_USART3RST              0x00040000U
-#define  RCC_APB1RSTR_UART4RST               0x00080000U
-#define  RCC_APB1RSTR_UART5RST               0x00100000U
-#define  RCC_APB1RSTR_I2C1RST                0x00200000U
-#define  RCC_APB1RSTR_I2C2RST                0x00400000U
-#define  RCC_APB1RSTR_I2C3RST                0x00800000U
-#define  RCC_APB1RSTR_I2C4RST                0x01000000U
-#define  RCC_APB1RSTR_CAN1RST                0x02000000U
-#define  RCC_APB1RSTR_CAN2RST                0x04000000U
-#define  RCC_APB1RSTR_CECRST                 0x08000000U
-#define  RCC_APB1RSTR_PWRRST                 0x10000000U
-#define  RCC_APB1RSTR_DACRST                 0x20000000U
-#define  RCC_APB1RSTR_UART7RST               0x40000000U
-#define  RCC_APB1RSTR_UART8RST               0x80000000U
-
-/********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                0x00000001U
-#define  RCC_APB2RSTR_TIM8RST                0x00000002U
-#define  RCC_APB2RSTR_USART1RST              0x00000010U
-#define  RCC_APB2RSTR_USART6RST              0x00000020U
-#define  RCC_APB2RSTR_SDMMC2RST              0x00000080U
-#define  RCC_APB2RSTR_ADCRST                 0x00000100U
-#define  RCC_APB2RSTR_SDMMC1RST              0x00000800U
-#define  RCC_APB2RSTR_SPI1RST                0x00001000U
-#define  RCC_APB2RSTR_SPI4RST                0x00002000U
-#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
-#define  RCC_APB2RSTR_TIM9RST                0x00010000U
-#define  RCC_APB2RSTR_TIM10RST               0x00020000U
-#define  RCC_APB2RSTR_TIM11RST               0x00040000U
-#define  RCC_APB2RSTR_SPI5RST                0x00100000U
-#define  RCC_APB2RSTR_SPI6RST                0x00200000U
-#define  RCC_APB2RSTR_SAI1RST                0x00400000U
-#define  RCC_APB2RSTR_SAI2RST                0x00800000U
-#define  RCC_APB2RSTR_LTDCRST                0x04000000U
-#define  RCC_APB2RSTR_DSIRST                 0x08000000U
-#define  RCC_APB2RSTR_DFSDM1RST              0x20000000U
-#define  RCC_APB2RSTR_MDIORST                0x40000000U
-
-/********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
-#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
-#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
-#define  RCC_AHB1ENR_GPIODEN                 0x00000008U
-#define  RCC_AHB1ENR_GPIOEEN                 0x00000010U
-#define  RCC_AHB1ENR_GPIOFEN                 0x00000020U
-#define  RCC_AHB1ENR_GPIOGEN                 0x00000040U
-#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
-#define  RCC_AHB1ENR_GPIOIEN                 0x00000100U
-#define  RCC_AHB1ENR_GPIOJEN                 0x00000200U
-#define  RCC_AHB1ENR_GPIOKEN                 0x00000400U
-#define  RCC_AHB1ENR_CRCEN                   0x00001000U
-#define  RCC_AHB1ENR_BKPSRAMEN               0x00040000U
-#define  RCC_AHB1ENR_DTCMRAMEN               0x00100000U
-#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
-#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
-#define  RCC_AHB1ENR_DMA2DEN                 0x00800000U
-#define  RCC_AHB1ENR_ETHMACEN                0x02000000U
-#define  RCC_AHB1ENR_ETHMACTXEN              0x04000000U
-#define  RCC_AHB1ENR_ETHMACRXEN              0x08000000U
-#define  RCC_AHB1ENR_ETHMACPTPEN             0x10000000U
-#define  RCC_AHB1ENR_OTGHSEN                 0x20000000U
-#define  RCC_AHB1ENR_OTGHSULPIEN             0x40000000U
-
-/********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define  RCC_AHB2ENR_DCMIEN                  0x00000001U
-#define  RCC_AHB2ENR_JPEGEN                  0x00000002U
-#define  RCC_AHB2ENR_RNGEN                   0x00000040U
-#define  RCC_AHB2ENR_OTGFSEN                 0x00000080U
-
-/********************  Bit definition for RCC_AHB3ENR register  ***************/
-#define  RCC_AHB3ENR_FMCEN                  0x00000001U
-#define  RCC_AHB3ENR_QSPIEN                 0x00000002U
-
-/********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM2EN                  0x00000001U
-#define  RCC_APB1ENR_TIM3EN                  0x00000002U
-#define  RCC_APB1ENR_TIM4EN                  0x00000004U
-#define  RCC_APB1ENR_TIM5EN                  0x00000008U
-#define  RCC_APB1ENR_TIM6EN                  0x00000010U
-#define  RCC_APB1ENR_TIM7EN                  0x00000020U
-#define  RCC_APB1ENR_TIM12EN                 0x00000040U
-#define  RCC_APB1ENR_TIM13EN                 0x00000080U
-#define  RCC_APB1ENR_TIM14EN                 0x00000100U
-#define  RCC_APB1ENR_LPTIM1EN                0x00000200U
-#define  RCC_APB1ENR_RTCEN                   0x00000400U
-#define  RCC_APB1ENR_WWDGEN                  0x00000800U
-#define  RCC_APB1ENR_CAN3EN                  0x00002000U
-#define  RCC_APB1ENR_SPI2EN                  0x00004000U
-#define  RCC_APB1ENR_SPI3EN                  0x00008000U
-#define  RCC_APB1ENR_SPDIFRXEN               0x00010000U
-#define  RCC_APB1ENR_USART2EN                0x00020000U
-#define  RCC_APB1ENR_USART3EN                0x00040000U
-#define  RCC_APB1ENR_UART4EN                 0x00080000U
-#define  RCC_APB1ENR_UART5EN                 0x00100000U
-#define  RCC_APB1ENR_I2C1EN                  0x00200000U
-#define  RCC_APB1ENR_I2C2EN                  0x00400000U
-#define  RCC_APB1ENR_I2C3EN                  0x00800000U
-#define  RCC_APB1ENR_I2C4EN                  0x01000000U
-#define  RCC_APB1ENR_CAN1EN                  0x02000000U
-#define  RCC_APB1ENR_CAN2EN                  0x04000000U
-#define  RCC_APB1ENR_CECEN                   0x08000000U
-#define  RCC_APB1ENR_PWREN                   0x10000000U
-#define  RCC_APB1ENR_DACEN                   0x20000000U
-#define  RCC_APB1ENR_UART7EN                 0x40000000U
-#define  RCC_APB1ENR_UART8EN                 0x80000000U
-
-/********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  0x00000001U
-#define  RCC_APB2ENR_TIM8EN                  0x00000002U
-#define  RCC_APB2ENR_USART1EN                0x00000010U
-#define  RCC_APB2ENR_USART6EN                0x00000020U
-#define  RCC_APB2ENR_SDMMC2EN                0x00000080U
-#define  RCC_APB2ENR_ADC1EN                  0x00000100U
-#define  RCC_APB2ENR_ADC2EN                  0x00000200U
-#define  RCC_APB2ENR_ADC3EN                  0x00000400U
-#define  RCC_APB2ENR_SDMMC1EN                0x00000800U
-#define  RCC_APB2ENR_SPI1EN                  0x00001000U
-#define  RCC_APB2ENR_SPI4EN                  0x00002000U
-#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
-#define  RCC_APB2ENR_TIM9EN                  0x00010000U
-#define  RCC_APB2ENR_TIM10EN                 0x00020000U
-#define  RCC_APB2ENR_TIM11EN                 0x00040000U
-#define  RCC_APB2ENR_SPI5EN                  0x00100000U
-#define  RCC_APB2ENR_SPI6EN                  0x00200000U
-#define  RCC_APB2ENR_SAI1EN                  0x00400000U
-#define  RCC_APB2ENR_SAI2EN                  0x00800000U
-#define  RCC_APB2ENR_LTDCEN                  0x04000000U
-#define  RCC_APB2ENR_DSIEN                   0x08000000U
-#define  RCC_APB2ENR_DFSDM1EN                0x20000000U
-#define  RCC_APB2ENR_MDIOEN                  0x40000000U
-
-/********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
-#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
-#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
-#define  RCC_AHB1LPENR_GPIODLPEN             0x00000008U
-#define  RCC_AHB1LPENR_GPIOELPEN             0x00000010U
-#define  RCC_AHB1LPENR_GPIOFLPEN             0x00000020U
-#define  RCC_AHB1LPENR_GPIOGLPEN             0x00000040U
-#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
-#define  RCC_AHB1LPENR_GPIOILPEN             0x00000100U
-#define  RCC_AHB1LPENR_GPIOJLPEN             0x00000200U
-#define  RCC_AHB1LPENR_GPIOKLPEN             0x00000400U
-#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
-#define  RCC_AHB1LPENR_AXILPEN               0x00002000U
-#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
-#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
-#define  RCC_AHB1LPENR_SRAM2LPEN             0x00020000U
-#define  RCC_AHB1LPENR_BKPSRAMLPEN           0x00040000U
-#define  RCC_AHB1LPENR_DTCMLPEN              0x00100000U
-#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
-#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
-#define  RCC_AHB1LPENR_DMA2DLPEN             0x00800000U
-#define  RCC_AHB1LPENR_ETHMACLPEN            0x02000000U
-#define  RCC_AHB1LPENR_ETHMACTXLPEN          0x04000000U
-#define  RCC_AHB1LPENR_ETHMACRXLPEN          0x08000000U
-#define  RCC_AHB1LPENR_ETHMACPTPLPEN         0x10000000U
-#define  RCC_AHB1LPENR_OTGHSLPEN             0x20000000U
-#define  RCC_AHB1LPENR_OTGHSULPILPEN         0x40000000U
-
-/********************  Bit definition for RCC_AHB2LPENR register  *************/
-#define  RCC_AHB2LPENR_DCMILPEN              0x00000001U
-#define  RCC_AHB2LPENR_JPEGLPEN              0x00000002U
-#define  RCC_AHB2LPENR_RNGLPEN               0x00000040U
-#define  RCC_AHB2LPENR_OTGFSLPEN             0x00000080U
-
-/********************  Bit definition for RCC_AHB3LPENR register  *************/
-#define  RCC_AHB3LPENR_FMCLPEN               0x00000001U
-#define  RCC_AHB3LPENR_QSPILPEN              0x00000002U
-/********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM2LPEN              0x00000001U
-#define  RCC_APB1LPENR_TIM3LPEN              0x00000002U
-#define  RCC_APB1LPENR_TIM4LPEN              0x00000004U
-#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
-#define  RCC_APB1LPENR_TIM6LPEN              0x00000010U
-#define  RCC_APB1LPENR_TIM7LPEN              0x00000020U
-#define  RCC_APB1LPENR_TIM12LPEN             0x00000040U
-#define  RCC_APB1LPENR_TIM13LPEN             0x00000080U
-#define  RCC_APB1LPENR_TIM14LPEN             0x00000100U
-#define  RCC_APB1LPENR_LPTIM1LPEN            0x00000200U
-#define  RCC_APB1LPENR_RTCLPEN               0x00000400U
-#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
-#define  RCC_APB1LPENR_CAN3LPEN              0x00002000U
-#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U
-#define  RCC_APB1LPENR_SPI3LPEN              0x00008000U
-#define  RCC_APB1LPENR_SPDIFRXLPEN           0x00010000U
-#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
-#define  RCC_APB1LPENR_USART3LPEN            0x00040000U
-#define  RCC_APB1LPENR_UART4LPEN             0x00080000U
-#define  RCC_APB1LPENR_UART5LPEN             0x00100000U
-#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
-#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
-#define  RCC_APB1LPENR_I2C3LPEN              0x00800000U
-#define  RCC_APB1LPENR_I2C4LPEN              0x01000000U
-#define  RCC_APB1LPENR_CAN1LPEN              0x02000000U
-#define  RCC_APB1LPENR_CAN2LPEN              0x04000000U
-#define  RCC_APB1LPENR_CECLPEN               0x08000000U
-#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
-#define  RCC_APB1LPENR_DACLPEN               0x20000000U
-#define  RCC_APB1LPENR_UART7LPEN             0x40000000U
-#define  RCC_APB1LPENR_UART8LPEN             0x80000000U
-
-/********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
-#define  RCC_APB2LPENR_TIM8LPEN              0x00000002U
-#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
-#define  RCC_APB2LPENR_USART6LPEN            0x00000020U
-#define  RCC_APB2LPENR_SDMMC2LPEN            0x00000080U
-#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
-#define  RCC_APB2LPENR_ADC2LPEN              0x00000200U
-#define  RCC_APB2LPENR_ADC3LPEN              0x00000400U
-#define  RCC_APB2LPENR_SDMMC1LPEN            0x00000800U
-#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
-#define  RCC_APB2LPENR_SPI4LPEN              0x00002000U
-#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
-#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
-#define  RCC_APB2LPENR_TIM10LPEN             0x00020000U
-#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
-#define  RCC_APB2LPENR_SPI5LPEN              0x00100000U
-#define  RCC_APB2LPENR_SPI6LPEN              0x00200000U
-#define  RCC_APB2LPENR_SAI1LPEN              0x00400000U
-#define  RCC_APB2LPENR_SAI2LPEN              0x00800000U
-#define  RCC_APB2LPENR_LTDCLPEN              0x04000000U
-#define  RCC_APB2LPENR_DSILPEN               0x08000000U
-#define  RCC_APB2LPENR_DFSDM1LPEN            0x20000000U
-#define  RCC_APB2LPENR_MDIOLPEN              0x40000000U
-
-/********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      0x00000001U
-#define  RCC_BDCR_LSERDY                     0x00000002U
-#define  RCC_BDCR_LSEBYP                     0x00000004U
-#define  RCC_BDCR_LSEDRV                     0x00000018U
-#define  RCC_BDCR_LSEDRV_0                   0x00000008U
-#define  RCC_BDCR_LSEDRV_1                   0x00000010U
-#define  RCC_BDCR_RTCSEL                     0x00000300U
-#define  RCC_BDCR_RTCSEL_0                   0x00000100U
-#define  RCC_BDCR_RTCSEL_1                   0x00000200U
-#define  RCC_BDCR_RTCEN                      0x00008000U
-#define  RCC_BDCR_BDRST                      0x00010000U
-
-/********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       0x00000001U
-#define  RCC_CSR_LSIRDY                      0x00000002U
-#define  RCC_CSR_RMVF                        0x01000000U
-#define  RCC_CSR_BORRSTF                     0x02000000U
-#define  RCC_CSR_PINRSTF                     0x04000000U
-#define  RCC_CSR_PORRSTF                     0x08000000U
-#define  RCC_CSR_SFTRSTF                     0x10000000U
-#define  RCC_CSR_IWDGRSTF                    0x20000000U
-#define  RCC_CSR_WWDGRSTF                    0x40000000U
-#define  RCC_CSR_LPWRRSTF                    0x80000000U
-
-/********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    0x00001FFFU
-#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
-#define  RCC_SSCGR_SPREADSEL                 0x40000000U
-#define  RCC_SSCGR_SSCGEN                    0x80000000U
-
-/********************  Bit definition for RCC_PLLI2SCFGR register  ************/
-#define  RCC_PLLI2SCFGR_PLLI2SN              0x00007FC0U
-#define  RCC_PLLI2SCFGR_PLLI2SN_0            0x00000040U
-#define  RCC_PLLI2SCFGR_PLLI2SN_1            0x00000080U
-#define  RCC_PLLI2SCFGR_PLLI2SN_2            0x00000100U
-#define  RCC_PLLI2SCFGR_PLLI2SN_3            0x00000200U
-#define  RCC_PLLI2SCFGR_PLLI2SN_4            0x00000400U
-#define  RCC_PLLI2SCFGR_PLLI2SN_5            0x00000800U
-#define  RCC_PLLI2SCFGR_PLLI2SN_6            0x00001000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_7            0x00002000U
-#define  RCC_PLLI2SCFGR_PLLI2SN_8            0x00004000U
-#define  RCC_PLLI2SCFGR_PLLI2SP              0x00030000U
-#define  RCC_PLLI2SCFGR_PLLI2SP_0            0x00010000U
-#define  RCC_PLLI2SCFGR_PLLI2SP_1            0x00020000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ              0x0F000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_0            0x01000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_1            0x02000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_2            0x04000000U
-#define  RCC_PLLI2SCFGR_PLLI2SQ_3            0x08000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR              0x70000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_0            0x10000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_1            0x20000000U
-#define  RCC_PLLI2SCFGR_PLLI2SR_2            0x40000000U
-
-/********************  Bit definition for RCC_PLLSAICFGR register  ************/
-#define  RCC_PLLSAICFGR_PLLSAIN              0x00007FC0U
-#define  RCC_PLLSAICFGR_PLLSAIN_0            0x00000040U
-#define  RCC_PLLSAICFGR_PLLSAIN_1            0x00000080U
-#define  RCC_PLLSAICFGR_PLLSAIN_2            0x00000100U
-#define  RCC_PLLSAICFGR_PLLSAIN_3            0x00000200U
-#define  RCC_PLLSAICFGR_PLLSAIN_4            0x00000400U
-#define  RCC_PLLSAICFGR_PLLSAIN_5            0x00000800U
-#define  RCC_PLLSAICFGR_PLLSAIN_6            0x00001000U
-#define  RCC_PLLSAICFGR_PLLSAIN_7            0x00002000U
-#define  RCC_PLLSAICFGR_PLLSAIN_8            0x00004000U
-#define  RCC_PLLSAICFGR_PLLSAIP              0x00030000U
-#define  RCC_PLLSAICFGR_PLLSAIP_0            0x00010000U
-#define  RCC_PLLSAICFGR_PLLSAIP_1            0x00020000U
-#define  RCC_PLLSAICFGR_PLLSAIQ              0x0F000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_0            0x01000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_1            0x02000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_2            0x04000000U
-#define  RCC_PLLSAICFGR_PLLSAIQ_3            0x08000000U
-#define  RCC_PLLSAICFGR_PLLSAIR              0x70000000U
-#define  RCC_PLLSAICFGR_PLLSAIR_0            0x10000000U
-#define  RCC_PLLSAICFGR_PLLSAIR_1            0x20000000U
-#define  RCC_PLLSAICFGR_PLLSAIR_2            0x40000000U
-
-/********************  Bit definition for RCC_DCKCFGR1 register  ***************/
-#define  RCC_DCKCFGR1_PLLI2SDIVQ             0x0000001FU
-#define  RCC_DCKCFGR1_PLLI2SDIVQ_0           0x00000001U
-#define  RCC_DCKCFGR1_PLLI2SDIVQ_1           0x00000002U
-#define  RCC_DCKCFGR1_PLLI2SDIVQ_2           0x00000004U
-#define  RCC_DCKCFGR1_PLLI2SDIVQ_3           0x00000008U
-#define  RCC_DCKCFGR1_PLLI2SDIVQ_4           0x00000010U
-
-#define  RCC_DCKCFGR1_PLLSAIDIVQ             0x00001F00U
-#define  RCC_DCKCFGR1_PLLSAIDIVQ_0           0x00000100U
-#define  RCC_DCKCFGR1_PLLSAIDIVQ_1           0x00000200U
-#define  RCC_DCKCFGR1_PLLSAIDIVQ_2           0x00000400U
-#define  RCC_DCKCFGR1_PLLSAIDIVQ_3           0x00000800U
-#define  RCC_DCKCFGR1_PLLSAIDIVQ_4           0x00001000U
-
-#define  RCC_DCKCFGR1_PLLSAIDIVR             0x00030000U
-#define  RCC_DCKCFGR1_PLLSAIDIVR_0           0x00010000U
-#define  RCC_DCKCFGR1_PLLSAIDIVR_1           0x00020000U
-
-#define  RCC_DCKCFGR1_SAI1SEL                0x00300000U
-#define  RCC_DCKCFGR1_SAI1SEL_0              0x00100000U
-#define  RCC_DCKCFGR1_SAI1SEL_1              0x00200000U
-
-#define  RCC_DCKCFGR1_SAI2SEL                0x00C00000U
-#define  RCC_DCKCFGR1_SAI2SEL_0              0x00400000U
-#define  RCC_DCKCFGR1_SAI2SEL_1              0x00800000U
-
-#define  RCC_DCKCFGR1_TIMPRE                 0x01000000U
-#define  RCC_DCKCFGR1_DFSDM1SEL              0x02000000U
-#define  RCC_DCKCFGR1_ADFSDM1SEL             0x04000000U
-
-/********************  Bit definition for RCC_DCKCFGR2 register  ***************/
-#define  RCC_DCKCFGR2_USART1SEL              0x00000003U
-#define  RCC_DCKCFGR2_USART1SEL_0            0x00000001U
-#define  RCC_DCKCFGR2_USART1SEL_1            0x00000002U
-#define  RCC_DCKCFGR2_USART2SEL              0x0000000CU
-#define  RCC_DCKCFGR2_USART2SEL_0            0x00000004U
-#define  RCC_DCKCFGR2_USART2SEL_1            0x00000008U
-#define  RCC_DCKCFGR2_USART3SEL              0x00000030U
-#define  RCC_DCKCFGR2_USART3SEL_0            0x00000010U
-#define  RCC_DCKCFGR2_USART3SEL_1            0x00000020U
-#define  RCC_DCKCFGR2_UART4SEL               0x000000C0U
-#define  RCC_DCKCFGR2_UART4SEL_0             0x00000040U
-#define  RCC_DCKCFGR2_UART4SEL_1             0x00000080U
-#define  RCC_DCKCFGR2_UART5SEL               0x00000300U
-#define  RCC_DCKCFGR2_UART5SEL_0             0x00000100U
-#define  RCC_DCKCFGR2_UART5SEL_1             0x00000200U
-#define  RCC_DCKCFGR2_USART6SEL              0x00000C00U
-#define  RCC_DCKCFGR2_USART6SEL_0            0x00000400U
-#define  RCC_DCKCFGR2_USART6SEL_1            0x00000800U
-#define  RCC_DCKCFGR2_UART7SEL               0x00003000U
-#define  RCC_DCKCFGR2_UART7SEL_0             0x00001000U
-#define  RCC_DCKCFGR2_UART7SEL_1             0x00002000U
-#define  RCC_DCKCFGR2_UART8SEL               0x0000C000U
-#define  RCC_DCKCFGR2_UART8SEL_0             0x00004000U
-#define  RCC_DCKCFGR2_UART8SEL_1             0x00008000U
-#define  RCC_DCKCFGR2_I2C1SEL                0x00030000U
-#define  RCC_DCKCFGR2_I2C1SEL_0              0x00010000U
-#define  RCC_DCKCFGR2_I2C1SEL_1              0x00020000U
-#define  RCC_DCKCFGR2_I2C2SEL                0x000C0000U
-#define  RCC_DCKCFGR2_I2C2SEL_0              0x00040000U
-#define  RCC_DCKCFGR2_I2C2SEL_1              0x00080000U
-#define  RCC_DCKCFGR2_I2C3SEL                0x00300000U
-#define  RCC_DCKCFGR2_I2C3SEL_0              0x00100000U
-#define  RCC_DCKCFGR2_I2C3SEL_1              0x00200000U
-#define  RCC_DCKCFGR2_I2C4SEL                0x00C00000U
-#define  RCC_DCKCFGR2_I2C4SEL_0              0x00400000U
-#define  RCC_DCKCFGR2_I2C4SEL_1              0x00800000U
-#define  RCC_DCKCFGR2_LPTIM1SEL              0x03000000U
-#define  RCC_DCKCFGR2_LPTIM1SEL_0            0x01000000U
-#define  RCC_DCKCFGR2_LPTIM1SEL_1            0x02000000U
-#define  RCC_DCKCFGR2_CECSEL                 0x04000000U
-#define  RCC_DCKCFGR2_CK48MSEL               0x08000000U
-#define  RCC_DCKCFGR2_SDMMC1SEL              0x10000000U
-#define  RCC_DCKCFGR2_SDMMC2SEL              0x20000000U
-#define  RCC_DCKCFGR2_DSISEL                 0x40000000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    RNG                                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN                         0x00000004U
-#define RNG_CR_IE                            0x00000008U
-
-/********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY                          0x00000001U
-#define RNG_SR_CECS                          0x00000002U
-#define RNG_SR_SECS                          0x00000004U
-#define RNG_SR_CEIS                          0x00000020U
-#define RNG_SR_SEIS                          0x00000040U
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            0x00400000U
-#define RTC_TR_HT                            0x00300000U
-#define RTC_TR_HT_0                          0x00100000U
-#define RTC_TR_HT_1                          0x00200000U
-#define RTC_TR_HU                            0x000F0000U
-#define RTC_TR_HU_0                          0x00010000U
-#define RTC_TR_HU_1                          0x00020000U
-#define RTC_TR_HU_2                          0x00040000U
-#define RTC_TR_HU_3                          0x00080000U
-#define RTC_TR_MNT                           0x00007000U
-#define RTC_TR_MNT_0                         0x00001000U
-#define RTC_TR_MNT_1                         0x00002000U
-#define RTC_TR_MNT_2                         0x00004000U
-#define RTC_TR_MNU                           0x00000F00U
-#define RTC_TR_MNU_0                         0x00000100U
-#define RTC_TR_MNU_1                         0x00000200U
-#define RTC_TR_MNU_2                         0x00000400U
-#define RTC_TR_MNU_3                         0x00000800U
-#define RTC_TR_ST                            0x00000070U
-#define RTC_TR_ST_0                          0x00000010U
-#define RTC_TR_ST_1                          0x00000020U
-#define RTC_TR_ST_2                          0x00000040U
-#define RTC_TR_SU                            0x0000000FU
-#define RTC_TR_SU_0                          0x00000001U
-#define RTC_TR_SU_1                          0x00000002U
-#define RTC_TR_SU_2                          0x00000004U
-#define RTC_TR_SU_3                          0x00000008U
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            0x00F00000U
-#define RTC_DR_YT_0                          0x00100000U
-#define RTC_DR_YT_1                          0x00200000U
-#define RTC_DR_YT_2                          0x00400000U
-#define RTC_DR_YT_3                          0x00800000U
-#define RTC_DR_YU                            0x000F0000U
-#define RTC_DR_YU_0                          0x00010000U
-#define RTC_DR_YU_1                          0x00020000U
-#define RTC_DR_YU_2                          0x00040000U
-#define RTC_DR_YU_3                          0x00080000U
-#define RTC_DR_WDU                           0x0000E000U
-#define RTC_DR_WDU_0                         0x00002000U
-#define RTC_DR_WDU_1                         0x00004000U
-#define RTC_DR_WDU_2                         0x00008000U
-#define RTC_DR_MT                            0x00001000U
-#define RTC_DR_MU                            0x00000F00U
-#define RTC_DR_MU_0                          0x00000100U
-#define RTC_DR_MU_1                          0x00000200U
-#define RTC_DR_MU_2                          0x00000400U
-#define RTC_DR_MU_3                          0x00000800U
-#define RTC_DR_DT                            0x00000030U
-#define RTC_DR_DT_0                          0x00000010U
-#define RTC_DR_DT_1                          0x00000020U
-#define RTC_DR_DU                            0x0000000FU
-#define RTC_DR_DU_0                          0x00000001U
-#define RTC_DR_DU_1                          0x00000002U
-#define RTC_DR_DU_2                          0x00000004U
-#define RTC_DR_DU_3                          0x00000008U
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_ITSE                          0x01000000U 
-#define RTC_CR_COE                           0x00800000U
-#define RTC_CR_OSEL                          0x00600000U
-#define RTC_CR_OSEL_0                        0x00200000U
-#define RTC_CR_OSEL_1                        0x00400000U
-#define RTC_CR_POL                           0x00100000U
-#define RTC_CR_COSEL                         0x00080000U
-#define RTC_CR_BKP                           0x00040000U
-#define RTC_CR_SUB1H                         0x00020000U
-#define RTC_CR_ADD1H                         0x00010000U
-#define RTC_CR_TSIE                          0x00008000U
-#define RTC_CR_WUTIE                         0x00004000U
-#define RTC_CR_ALRBIE                        0x00002000U
-#define RTC_CR_ALRAIE                        0x00001000U
-#define RTC_CR_TSE                           0x00000800U
-#define RTC_CR_WUTE                          0x00000400U
-#define RTC_CR_ALRBE                         0x00000200U
-#define RTC_CR_ALRAE                         0x00000100U
-#define RTC_CR_FMT                           0x00000040U
-#define RTC_CR_BYPSHAD                       0x00000020U
-#define RTC_CR_REFCKON                       0x00000010U
-#define RTC_CR_TSEDGE                        0x00000008U
-#define RTC_CR_WUCKSEL                       0x00000007U
-#define RTC_CR_WUCKSEL_0                     0x00000001U
-#define RTC_CR_WUCKSEL_1                     0x00000002U
-#define RTC_CR_WUCKSEL_2                     0x00000004U
-
-/* Legacy define */
-#define RTC_CR_BCK                           RTC_CR_BKP
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_ITSF                         0x00020000U
-#define RTC_ISR_RECALPF                      0x00010000U
-#define RTC_ISR_TAMP3F                       0x00008000U
-#define RTC_ISR_TAMP2F                       0x00004000U
-#define RTC_ISR_TAMP1F                       0x00002000U
-#define RTC_ISR_TSOVF                        0x00001000U
-#define RTC_ISR_TSF                          0x00000800U
-#define RTC_ISR_WUTF                         0x00000400U
-#define RTC_ISR_ALRBF                        0x00000200U
-#define RTC_ISR_ALRAF                        0x00000100U
-#define RTC_ISR_INIT                         0x00000080U
-#define RTC_ISR_INITF                        0x00000040U
-#define RTC_ISR_RSF                          0x00000020U
-#define RTC_ISR_INITS                        0x00000010U
-#define RTC_ISR_SHPF                         0x00000008U
-#define RTC_ISR_WUTWF                        0x00000004U
-#define RTC_ISR_ALRBWF                       0x00000002U
-#define RTC_ISR_ALRAWF                       0x00000001U
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    0x007F0000U
-#define RTC_PRER_PREDIV_S                    0x00007FFFU
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         0x0000FFFFU
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      0x80000000U
-#define RTC_ALRMAR_WDSEL                     0x40000000U
-#define RTC_ALRMAR_DT                        0x30000000U
-#define RTC_ALRMAR_DT_0                      0x10000000U
-#define RTC_ALRMAR_DT_1                      0x20000000U
-#define RTC_ALRMAR_DU                        0x0F000000U
-#define RTC_ALRMAR_DU_0                      0x01000000U
-#define RTC_ALRMAR_DU_1                      0x02000000U
-#define RTC_ALRMAR_DU_2                      0x04000000U
-#define RTC_ALRMAR_DU_3                      0x08000000U
-#define RTC_ALRMAR_MSK3                      0x00800000U
-#define RTC_ALRMAR_PM                        0x00400000U
-#define RTC_ALRMAR_HT                        0x00300000U
-#define RTC_ALRMAR_HT_0                      0x00100000U
-#define RTC_ALRMAR_HT_1                      0x00200000U
-#define RTC_ALRMAR_HU                        0x000F0000U
-#define RTC_ALRMAR_HU_0                      0x00010000U
-#define RTC_ALRMAR_HU_1                      0x00020000U
-#define RTC_ALRMAR_HU_2                      0x00040000U
-#define RTC_ALRMAR_HU_3                      0x00080000U
-#define RTC_ALRMAR_MSK2                      0x00008000U
-#define RTC_ALRMAR_MNT                       0x00007000U
-#define RTC_ALRMAR_MNT_0                     0x00001000U
-#define RTC_ALRMAR_MNT_1                     0x00002000U
-#define RTC_ALRMAR_MNT_2                     0x00004000U
-#define RTC_ALRMAR_MNU                       0x00000F00U
-#define RTC_ALRMAR_MNU_0                     0x00000100U
-#define RTC_ALRMAR_MNU_1                     0x00000200U
-#define RTC_ALRMAR_MNU_2                     0x00000400U
-#define RTC_ALRMAR_MNU_3                     0x00000800U
-#define RTC_ALRMAR_MSK1                      0x00000080U
-#define RTC_ALRMAR_ST                        0x00000070U
-#define RTC_ALRMAR_ST_0                      0x00000010U
-#define RTC_ALRMAR_ST_1                      0x00000020U
-#define RTC_ALRMAR_ST_2                      0x00000040U
-#define RTC_ALRMAR_SU                        0x0000000FU
-#define RTC_ALRMAR_SU_0                      0x00000001U
-#define RTC_ALRMAR_SU_1                      0x00000002U
-#define RTC_ALRMAR_SU_2                      0x00000004U
-#define RTC_ALRMAR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      0x80000000U
-#define RTC_ALRMBR_WDSEL                     0x40000000U
-#define RTC_ALRMBR_DT                        0x30000000U
-#define RTC_ALRMBR_DT_0                      0x10000000U
-#define RTC_ALRMBR_DT_1                      0x20000000U
-#define RTC_ALRMBR_DU                        0x0F000000U
-#define RTC_ALRMBR_DU_0                      0x01000000U
-#define RTC_ALRMBR_DU_1                      0x02000000U
-#define RTC_ALRMBR_DU_2                      0x04000000U
-#define RTC_ALRMBR_DU_3                      0x08000000U
-#define RTC_ALRMBR_MSK3                      0x00800000U
-#define RTC_ALRMBR_PM                        0x00400000U
-#define RTC_ALRMBR_HT                        0x00300000U
-#define RTC_ALRMBR_HT_0                      0x00100000U
-#define RTC_ALRMBR_HT_1                      0x00200000U
-#define RTC_ALRMBR_HU                        0x000F0000U
-#define RTC_ALRMBR_HU_0                      0x00010000U
-#define RTC_ALRMBR_HU_1                      0x00020000U
-#define RTC_ALRMBR_HU_2                      0x00040000U
-#define RTC_ALRMBR_HU_3                      0x00080000U
-#define RTC_ALRMBR_MSK2                      0x00008000U
-#define RTC_ALRMBR_MNT                       0x00007000U
-#define RTC_ALRMBR_MNT_0                     0x00001000U
-#define RTC_ALRMBR_MNT_1                     0x00002000U
-#define RTC_ALRMBR_MNT_2                     0x00004000U
-#define RTC_ALRMBR_MNU                       0x00000F00U
-#define RTC_ALRMBR_MNU_0                     0x00000100U
-#define RTC_ALRMBR_MNU_1                     0x00000200U
-#define RTC_ALRMBR_MNU_2                     0x00000400U
-#define RTC_ALRMBR_MNU_3                     0x00000800U
-#define RTC_ALRMBR_MSK1                      0x00000080U
-#define RTC_ALRMBR_ST                        0x00000070U
-#define RTC_ALRMBR_ST_0                      0x00000010U
-#define RTC_ALRMBR_ST_1                      0x00000020U
-#define RTC_ALRMBR_ST_2                      0x00000040U
-#define RTC_ALRMBR_SU                        0x0000000FU
-#define RTC_ALRMBR_SU_0                      0x00000001U
-#define RTC_ALRMBR_SU_1                      0x00000002U
-#define RTC_ALRMBR_SU_2                      0x00000004U
-#define RTC_ALRMBR_SU_3                      0x00000008U
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          0x000000FFU
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           0x0000FFFFU
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     0x00007FFFU
-#define RTC_SHIFTR_ADD1S                     0x80000000U
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          0x00400000U
-#define RTC_TSTR_HT                          0x00300000U
-#define RTC_TSTR_HT_0                        0x00100000U
-#define RTC_TSTR_HT_1                        0x00200000U
-#define RTC_TSTR_HU                          0x000F0000U
-#define RTC_TSTR_HU_0                        0x00010000U
-#define RTC_TSTR_HU_1                        0x00020000U
-#define RTC_TSTR_HU_2                        0x00040000U
-#define RTC_TSTR_HU_3                        0x00080000U
-#define RTC_TSTR_MNT                         0x00007000U
-#define RTC_TSTR_MNT_0                       0x00001000U
-#define RTC_TSTR_MNT_1                       0x00002000U
-#define RTC_TSTR_MNT_2                       0x00004000U
-#define RTC_TSTR_MNU                         0x00000F00U
-#define RTC_TSTR_MNU_0                       0x00000100U
-#define RTC_TSTR_MNU_1                       0x00000200U
-#define RTC_TSTR_MNU_2                       0x00000400U
-#define RTC_TSTR_MNU_3                       0x00000800U
-#define RTC_TSTR_ST                          0x00000070U
-#define RTC_TSTR_ST_0                        0x00000010U
-#define RTC_TSTR_ST_1                        0x00000020U
-#define RTC_TSTR_ST_2                        0x00000040U
-#define RTC_TSTR_SU                          0x0000000FU
-#define RTC_TSTR_SU_0                        0x00000001U
-#define RTC_TSTR_SU_1                        0x00000002U
-#define RTC_TSTR_SU_2                        0x00000004U
-#define RTC_TSTR_SU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         0x0000E000U
-#define RTC_TSDR_WDU_0                       0x00002000U
-#define RTC_TSDR_WDU_1                       0x00004000U
-#define RTC_TSDR_WDU_2                       0x00008000U
-#define RTC_TSDR_MT                          0x00001000U
-#define RTC_TSDR_MU                          0x00000F00U
-#define RTC_TSDR_MU_0                        0x00000100U
-#define RTC_TSDR_MU_1                        0x00000200U
-#define RTC_TSDR_MU_2                        0x00000400U
-#define RTC_TSDR_MU_3                        0x00000800U
-#define RTC_TSDR_DT                          0x00000030U
-#define RTC_TSDR_DT_0                        0x00000010U
-#define RTC_TSDR_DT_1                        0x00000020U
-#define RTC_TSDR_DU                          0x0000000FU
-#define RTC_TSDR_DU_0                        0x00000001U
-#define RTC_TSDR_DU_1                        0x00000002U
-#define RTC_TSDR_DU_2                        0x00000004U
-#define RTC_TSDR_DU_3                        0x00000008U
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         0x0000FFFFU
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        0x00008000U
-#define RTC_CALR_CALW8                       0x00004000U
-#define RTC_CALR_CALW16                      0x00002000U
-#define RTC_CALR_CALM                        0x000001FFU
-#define RTC_CALR_CALM_0                      0x00000001U
-#define RTC_CALR_CALM_1                      0x00000002U
-#define RTC_CALR_CALM_2                      0x00000004U
-#define RTC_CALR_CALM_3                      0x00000008U
-#define RTC_CALR_CALM_4                      0x00000010U
-#define RTC_CALR_CALM_5                      0x00000020U
-#define RTC_CALR_CALM_6                      0x00000040U
-#define RTC_CALR_CALM_7                      0x00000080U
-#define RTC_CALR_CALM_8                      0x00000100U
-
-/********************  Bits definition for RTC_TAMPCR register  ****************/
-#define RTC_TAMPCR_TAMP3MF                   0x01000000U
-#define RTC_TAMPCR_TAMP3NOERASE              0x00800000U
-#define RTC_TAMPCR_TAMP3IE                   0x00400000U
-#define RTC_TAMPCR_TAMP2MF                   0x00200000U
-#define RTC_TAMPCR_TAMP2NOERASE              0x00100000U
-#define RTC_TAMPCR_TAMP2IE                   0x00080000U
-#define RTC_TAMPCR_TAMP1MF                   0x00040000U
-#define RTC_TAMPCR_TAMP1NOERASE              0x00020000U
-#define RTC_TAMPCR_TAMP1IE                   0x00010000U
-#define RTC_TAMPCR_TAMPPUDIS                 0x00008000U
-#define RTC_TAMPCR_TAMPPRCH                  0x00006000U
-#define RTC_TAMPCR_TAMPPRCH_0                0x00002000U
-#define RTC_TAMPCR_TAMPPRCH_1                0x00004000U
-#define RTC_TAMPCR_TAMPFLT                   0x00001800U
-#define RTC_TAMPCR_TAMPFLT_0                 0x00000800U
-#define RTC_TAMPCR_TAMPFLT_1                 0x00001000U
-#define RTC_TAMPCR_TAMPFREQ                  0x00000700U
-#define RTC_TAMPCR_TAMPFREQ_0                0x00000100U
-#define RTC_TAMPCR_TAMPFREQ_1                0x00000200U
-#define RTC_TAMPCR_TAMPFREQ_2                0x00000400U
-#define RTC_TAMPCR_TAMPTS                    0x00000080U
-#define RTC_TAMPCR_TAMP3TRG                  0x00000040U
-#define RTC_TAMPCR_TAMP3E                    0x00000020U
-#define RTC_TAMPCR_TAMP2TRG                  0x00000010U
-#define RTC_TAMPCR_TAMP2E                    0x00000008U
-#define RTC_TAMPCR_TAMPIE                    0x00000004U
-#define RTC_TAMPCR_TAMP1TRG                  0x00000002U
-#define RTC_TAMPCR_TAMP1E                    0x00000001U
-
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  0x0F000000U
-#define RTC_ALRMASSR_MASKSS_0                0x01000000U
-#define RTC_ALRMASSR_MASKSS_1                0x02000000U
-#define RTC_ALRMASSR_MASKSS_2                0x04000000U
-#define RTC_ALRMASSR_MASKSS_3                0x08000000U
-#define RTC_ALRMASSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
-#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
-#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
-#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
-#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
-#define RTC_ALRMBSSR_SS                      0x00007FFFU
-
-/********************  Bits definition for RTC_OR register  ****************/
-#define RTC_OR_TSINSEL                       0x00000006U
-#define RTC_OR_TSINSEL_0                     0x00000002U
-#define RTC_OR_TSINSEL_1                     0x00000004U
-#define RTC_OR_ALARMTYPE                     0x00000008U
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP20R register  ***************/
-#define RTC_BKP20R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP21R register  ***************/
-#define RTC_BKP21R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP22R register  ***************/
-#define RTC_BKP22R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP23R register  ***************/
-#define RTC_BKP23R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP24R register  ***************/
-#define RTC_BKP24R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP25R register  ***************/
-#define RTC_BKP25R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP26R register  ***************/
-#define RTC_BKP26R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP27R register  ***************/
-#define RTC_BKP27R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP28R register  ***************/
-#define RTC_BKP28R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP29R register  ***************/
-#define RTC_BKP29R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP30R register  ***************/
-#define RTC_BKP30R                           0xFFFFFFFFU
-
-/********************  Bits definition for RTC_BKP31R register  ***************/
-#define RTC_BKP31R                           0xFFFFFFFFU
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER                       0x00000020U
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Serial Audio Interface                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for SAI_GCR register  *******************/
-#define  SAI_GCR_SYNCIN                      0x00000003U        /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
-#define  SAI_GCR_SYNCIN_0                    0x00000001U        /*!<Bit 0 */
-#define  SAI_GCR_SYNCIN_1                    0x00000002U        /*!<Bit 1 */
-                                             
-#define  SAI_GCR_SYNCOUT                     0x00000030U        /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
-#define  SAI_GCR_SYNCOUT_0                   0x00000010U        /*!<Bit 0 */
-#define  SAI_GCR_SYNCOUT_1                   0x00000020U        /*!<Bit 1 */
-
-/*******************  Bit definition for SAI_xCR1 register  *******************/
-#define  SAI_xCR1_MODE                       0x00000003U        /*!<MODE[1:0] bits (Audio Block Mode)           */
-#define  SAI_xCR1_MODE_0                     0x00000001U        /*!<Bit 0 */
-#define  SAI_xCR1_MODE_1                     0x00000002U        /*!<Bit 1 */
-                                             
-#define  SAI_xCR1_PRTCFG                     0x0000000CU        /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
-#define  SAI_xCR1_PRTCFG_0                   0x00000004U        /*!<Bit 0 */
-#define  SAI_xCR1_PRTCFG_1                   0x00000008U        /*!<Bit 1 */
-                                             
-#define  SAI_xCR1_DS                         0x000000E0U        /*!<DS[1:0] bits (Data Size) */
-#define  SAI_xCR1_DS_0                       0x00000020U        /*!<Bit 0 */
-#define  SAI_xCR1_DS_1                       0x00000040U        /*!<Bit 1 */
-#define  SAI_xCR1_DS_2                       0x00000080U        /*!<Bit 2 */
-                                             
-#define  SAI_xCR1_LSBFIRST                   0x00000100U        /*!<LSB First Configuration  */
-#define  SAI_xCR1_CKSTR                      0x00000200U        /*!<ClocK STRobing edge      */
-                                             
-#define  SAI_xCR1_SYNCEN                     0x00000C00U        /*!<SYNCEN[1:0](SYNChronization ENable) */
-#define  SAI_xCR1_SYNCEN_0                   0x00000400U        /*!<Bit 0 */
-#define  SAI_xCR1_SYNCEN_1                   0x00000800U        /*!<Bit 1 */
-                                             
-#define  SAI_xCR1_MONO                       0x00001000U        /*!<Mono mode                  */
-#define  SAI_xCR1_OUTDRIV                    0x00002000U        /*!<Output Drive               */
-#define  SAI_xCR1_SAIEN                      0x00010000U        /*!<Audio Block enable         */
-#define  SAI_xCR1_DMAEN                      0x00020000U        /*!<DMA enable                 */
-#define  SAI_xCR1_NODIV                      0x00080000U        /*!<No Divider Configuration   */
-                                             
-#define  SAI_xCR1_MCKDIV                     0x00F00000U        /*!<MCKDIV[3:0] (Master ClocK Divider)  */
-#define  SAI_xCR1_MCKDIV_0                   0x00100000U        /*!<Bit 0  */
-#define  SAI_xCR1_MCKDIV_1                   0x00200000U        /*!<Bit 1  */
-#define  SAI_xCR1_MCKDIV_2                   0x00400000U        /*!<Bit 2  */
-#define  SAI_xCR1_MCKDIV_3                   0x00800000U        /*!<Bit 3  */
-
-/*******************  Bit definition for SAI_xCR2 register  *******************/
-#define  SAI_xCR2_FTH                        0x00000007U        /*!<FTH[2:0](Fifo THreshold)  */
-#define  SAI_xCR2_FTH_0                      0x00000001U        /*!<Bit 0 */
-#define  SAI_xCR2_FTH_1                      0x00000002U        /*!<Bit 1 */
-#define  SAI_xCR2_FTH_2                      0x00000004U        /*!<Bit 2 */
-                                             
-#define  SAI_xCR2_FFLUSH                     0x00000008U        /*!<Fifo FLUSH                       */
-#define  SAI_xCR2_TRIS                       0x00000010U        /*!<TRIState Management on data line */
-#define  SAI_xCR2_MUTE                       0x00000020U        /*!<Mute mode                        */
-#define  SAI_xCR2_MUTEVAL                    0x00000040U        /*!<Muate value                      */
-                                             
-#define  SAI_xCR2_MUTECNT                    0x00001F80U       /*!<MUTECNT[5:0] (MUTE counter) */
-#define  SAI_xCR2_MUTECNT_0                  0x00000080U        /*!<Bit 0 */
-#define  SAI_xCR2_MUTECNT_1                  0x00000100U        /*!<Bit 1 */
-#define  SAI_xCR2_MUTECNT_2                  0x00000200U        /*!<Bit 2 */
-#define  SAI_xCR2_MUTECNT_3                  0x00000400U        /*!<Bit 3 */
-#define  SAI_xCR2_MUTECNT_4                  0x00000800U        /*!<Bit 4 */
-#define  SAI_xCR2_MUTECNT_5                  0x00001000U        /*!<Bit 5 */
-                                             
-#define  SAI_xCR2_CPL                        0x00002000U        /*!< Complement Bit             */
-                                             
-#define  SAI_xCR2_COMP                       0x0000C000U        /*!<COMP[1:0] (Companding mode) */
-#define  SAI_xCR2_COMP_0                     0x00004000U        /*!<Bit 0 */
-#define  SAI_xCR2_COMP_1                     0x00008000U        /*!<Bit 1 */
-
-/******************  Bit definition for SAI_xFRCR register  *******************/
-#define  SAI_xFRCR_FRL                       0x000000FFU        /*!<FRL[1:0](Frame length)  */
-#define  SAI_xFRCR_FRL_0                     0x00000001U        /*!<Bit 0 */
-#define  SAI_xFRCR_FRL_1                     0x00000002U        /*!<Bit 1 */
-#define  SAI_xFRCR_FRL_2                     0x00000004U        /*!<Bit 2 */
-#define  SAI_xFRCR_FRL_3                     0x00000008U        /*!<Bit 3 */
-#define  SAI_xFRCR_FRL_4                     0x00000010U        /*!<Bit 4 */
-#define  SAI_xFRCR_FRL_5                     0x00000020U        /*!<Bit 5 */
-#define  SAI_xFRCR_FRL_6                     0x00000040U        /*!<Bit 6 */
-#define  SAI_xFRCR_FRL_7                     0x00000080U        /*!<Bit 7 */
-                                                        
-#define  SAI_xFRCR_FSALL                     0x00007F00U        /*!<FRL[1:0] (Frame synchronization active level length)  */
-#define  SAI_xFRCR_FSALL_0                   0x00000100U        /*!<Bit 0 */
-#define  SAI_xFRCR_FSALL_1                   0x00000200U        /*!<Bit 1 */
-#define  SAI_xFRCR_FSALL_2                   0x00000400U        /*!<Bit 2 */
-#define  SAI_xFRCR_FSALL_3                   0x00000800U        /*!<Bit 3 */
-#define  SAI_xFRCR_FSALL_4                   0x00001000U        /*!<Bit 4 */
-#define  SAI_xFRCR_FSALL_5                   0x00002000U        /*!<Bit 5 */
-#define  SAI_xFRCR_FSALL_6                   0x00004000U        /*!<Bit 6 */
-                                                        
-#define  SAI_xFRCR_FSDEF                     0x00010000U        /*!<Frame Synchronization Definition  */
-#define  SAI_xFRCR_FSPOL                     0x00020000U        /*!<Frame Synchronization POLarity    */
-#define  SAI_xFRCR_FSOFF                     0x00040000U        /*!<Frame Synchronization OFFset      */
-                                             
-/* Legacy define */                          
-#define  SAI_xFRCR_FSPO                      SAI_xFRCR_FSPOL
-
-/******************  Bit definition for SAI_xSLOTR register  *******************/
-#define  SAI_xSLOTR_FBOFF                    0x0000001FU        /*!<FRL[4:0](First Bit Offset)  */
-#define  SAI_xSLOTR_FBOFF_0                  0x00000001U        /*!<Bit 0 */
-#define  SAI_xSLOTR_FBOFF_1                  0x00000002U        /*!<Bit 1 */
-#define  SAI_xSLOTR_FBOFF_2                  0x00000004U        /*!<Bit 2 */
-#define  SAI_xSLOTR_FBOFF_3                  0x00000008U        /*!<Bit 3 */
-#define  SAI_xSLOTR_FBOFF_4                  0x00000010U        /*!<Bit 4 */
-                                            
-#define  SAI_xSLOTR_SLOTSZ                   0x000000C0U        /*!<SLOTSZ[1:0] (Slot size)  */
-#define  SAI_xSLOTR_SLOTSZ_0                 0x00000040U        /*!<Bit 0 */
-#define  SAI_xSLOTR_SLOTSZ_1                 0x00000080U        /*!<Bit 1 */
-                                            
-#define  SAI_xSLOTR_NBSLOT                   0x00000F00U        /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
-#define  SAI_xSLOTR_NBSLOT_0                 0x00000100U        /*!<Bit 0 */
-#define  SAI_xSLOTR_NBSLOT_1                 0x00000200U        /*!<Bit 1 */
-#define  SAI_xSLOTR_NBSLOT_2                 0x00000400U        /*!<Bit 2 */
-#define  SAI_xSLOTR_NBSLOT_3                 0x00000800U        /*!<Bit 3 */
-                                            
-#define  SAI_xSLOTR_SLOTEN                   0xFFFF0000U        /*!<SLOTEN[15:0] (Slot Enable)  */
-
-/*******************  Bit definition for SAI_xIMR register  *******************/
-#define  SAI_xIMR_OVRUDRIE                   0x00000001U        /*!<Overrun underrun interrupt enable                              */
-#define  SAI_xIMR_MUTEDETIE                  0x00000002U        /*!<Mute detection interrupt enable                                */
-#define  SAI_xIMR_WCKCFGIE                   0x00000004U        /*!<Wrong Clock Configuration interrupt enable                     */
-#define  SAI_xIMR_FREQIE                     0x00000008U        /*!<FIFO request interrupt enable                                  */
-#define  SAI_xIMR_CNRDYIE                    0x00000010U        /*!<Codec not ready interrupt enable                               */
-#define  SAI_xIMR_AFSDETIE                   0x00000020U        /*!<Anticipated frame synchronization detection interrupt enable   */
-#define  SAI_xIMR_LFSDETIE                   0x00000040U        /*!<Late frame synchronization detection interrupt enable          */
-
-/********************  Bit definition for SAI_xSR register  *******************/
-#define  SAI_xSR_OVRUDR                      0x00000001U         /*!<Overrun underrun                               */
-#define  SAI_xSR_MUTEDET                     0x00000002U         /*!<Mute detection                                 */
-#define  SAI_xSR_WCKCFG                      0x00000004U         /*!<Wrong Clock Configuration                      */
-#define  SAI_xSR_FREQ                        0x00000008U         /*!<FIFO request                                   */
-#define  SAI_xSR_CNRDY                       0x00000010U         /*!<Codec not ready                                */
-#define  SAI_xSR_AFSDET                      0x00000020U         /*!<Anticipated frame synchronization detection    */
-#define  SAI_xSR_LFSDET                      0x00000040U         /*!<Late frame synchronization detection           */
-                                             
-#define  SAI_xSR_FLVL                        0x00070000U         /*!<FLVL[2:0] (FIFO Level Threshold)               */
-#define  SAI_xSR_FLVL_0                      0x00010000U         /*!<Bit 0 */
-#define  SAI_xSR_FLVL_1                      0x00020000U         /*!<Bit 1 */
-#define  SAI_xSR_FLVL_2                      0x00040000U         /*!<Bit 2 */
-
-/******************  Bit definition for SAI_xCLRFR register  ******************/
-#define  SAI_xCLRFR_COVRUDR                  0x00000001U        /*!<Clear Overrun underrun                               */
-#define  SAI_xCLRFR_CMUTEDET                 0x00000002U        /*!<Clear Mute detection                                 */
-#define  SAI_xCLRFR_CWCKCFG                  0x00000004U        /*!<Clear Wrong Clock Configuration                      */
-#define  SAI_xCLRFR_CFREQ                    0x00000008U        /*!<Clear FIFO request                                   */
-#define  SAI_xCLRFR_CCNRDY                   0x00000010U        /*!<Clear Codec not ready                                */
-#define  SAI_xCLRFR_CAFSDET                  0x00000020U        /*!<Clear Anticipated frame synchronization detection    */
-#define  SAI_xCLRFR_CLFSDET                  0x00000040U        /*!<Clear Late frame synchronization detection           */
-
-/******************  Bit definition for SAI_xDR register  *********************/
-#define  SAI_xDR_DATA                        0xFFFFFFFFU        
-
-/******************************************************************************/
-/*                                                                            */
-/*                              SPDIF-RX Interface                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for SPDIF_CR register  *******************/
-#define  SPDIFRX_CR_SPDIFEN                0x00000003U        /*!<Peripheral Block Enable                      */
-#define  SPDIFRX_CR_RXDMAEN                0x00000004U        /*!<Receiver DMA Enable for data flow            */
-#define  SPDIFRX_CR_RXSTEO                 0x00000008U        /*!<Stereo Mode                                  */
-#define  SPDIFRX_CR_DRFMT                  0x00000030U        /*!<RX Data format                               */
-#define  SPDIFRX_CR_PMSK                   0x00000040U        /*!<Mask Parity error bit                        */
-#define  SPDIFRX_CR_VMSK                   0x00000080U        /*!<Mask of Validity bit                         */
-#define  SPDIFRX_CR_CUMSK                  0x00000100U        /*!<Mask of channel status and user bits         */
-#define  SPDIFRX_CR_PTMSK                  0x00000200U        /*!<Mask of Preamble Type bits                   */
-#define  SPDIFRX_CR_CBDMAEN                0x00000400U        /*!<Control Buffer DMA ENable for control flow   */
-#define  SPDIFRX_CR_CHSEL                  0x00000800U        /*!<Channel Selection                            */
-#define  SPDIFRX_CR_NBTR                   0x00003000U        /*!<Maximum allowed re-tries during synchronization phase */
-#define  SPDIFRX_CR_WFA                    0x00004000U        /*!<Wait For Activity     */
-#define  SPDIFRX_CR_INSEL                  0x00070000U        /*!<SPDIF input selection */
-
-/*******************  Bit definition for SPDIFRX_IMR register  *******************/
-#define  SPDIFRX_IMR_RXNEIE                0x00000001U        /*!<RXNE interrupt enable                              */
-#define  SPDIFRX_IMR_CSRNEIE               0x00000002U        /*!<Control Buffer Ready Interrupt Enable              */
-#define  SPDIFRX_IMR_PERRIE                0x00000004U        /*!<Parity error interrupt enable                      */
-#define  SPDIFRX_IMR_OVRIE                 0x00000008U        /*!<Overrun error Interrupt Enable                     */
-#define  SPDIFRX_IMR_SBLKIE                0x00000010U        /*!<Synchronization Block Detected Interrupt Enable    */
-#define  SPDIFRX_IMR_SYNCDIE               0x00000020U        /*!<Synchronization Done                               */
-#define  SPDIFRX_IMR_IFEIE                 0x00000040U        /*!<Serial Interface Error Interrupt Enable            */
-
-/*******************  Bit definition for SPDIFRX_SR register  *******************/
-#define  SPDIFRX_SR_RXNE                   0x00000001U       /*!<Read data register not empty                          */
-#define  SPDIFRX_SR_CSRNE                  0x00000002U       /*!<The Control Buffer register is not empty              */
-#define  SPDIFRX_SR_PERR                   0x00000004U       /*!<Parity error                                          */
-#define  SPDIFRX_SR_OVR                    0x00000008U       /*!<Overrun error                                         */
-#define  SPDIFRX_SR_SBD                    0x00000010U       /*!<Synchronization Block Detected                        */
-#define  SPDIFRX_SR_SYNCD                  0x00000020U       /*!<Synchronization Done                                  */
-#define  SPDIFRX_SR_FERR                   0x00000040U       /*!<Framing error                                         */
-#define  SPDIFRX_SR_SERR                   0x00000080U       /*!<Synchronization error                                 */
-#define  SPDIFRX_SR_TERR                   0x00000100U       /*!<Time-out error                                        */
-#define  SPDIFRX_SR_WIDTH5                 0x7FFF0000U       /*!<Duration of 5 symbols counted with spdif_clk          */
-
-/*******************  Bit definition for SPDIFRX_IFCR register  *******************/
-#define  SPDIFRX_IFCR_PERRCF               0x00000004U       /*!<Clears the Parity error flag                         */
-#define  SPDIFRX_IFCR_OVRCF                0x00000008U       /*!<Clears the Overrun error flag                        */
-#define  SPDIFRX_IFCR_SBDCF                0x00000010U       /*!<Clears the Synchronization Block Detected flag       */
-#define  SPDIFRX_IFCR_SYNCDCF              0x00000020U       /*!<Clears the Synchronization Done flag                 */
-
-/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/
-#define  SPDIFRX_DR0_DR                    0x00FFFFFFU        /*!<Data value            */
-#define  SPDIFRX_DR0_PE                    0x01000000U        /*!<Parity Error bit      */
-#define  SPDIFRX_DR0_V                     0x02000000U        /*!<Validity bit          */
-#define  SPDIFRX_DR0_U                     0x04000000U        /*!<User bit              */
-#define  SPDIFRX_DR0_C                     0x08000000U        /*!<Channel Status bit    */
-#define  SPDIFRX_DR0_PT                    0x30000000U        /*!<Preamble Type         */
-
-/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/
-#define  SPDIFRX_DR1_DR                    0xFFFFFF00U        /*!<Data value            */
-#define  SPDIFRX_DR1_PT                    0x00000030U        /*!<Preamble Type         */
-#define  SPDIFRX_DR1_C                     0x00000008U        /*!<Channel Status bit    */
-#define  SPDIFRX_DR1_U                     0x00000004U        /*!<User bit              */
-#define  SPDIFRX_DR1_V                     0x00000002U        /*!<Validity bit          */
-#define  SPDIFRX_DR1_PE                    0x00000001U        /*!<Parity Error bit      */
-
-/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/
-#define  SPDIFRX_DR1_DRNL1                 0xFFFF0000U        /*!<Data value Channel B      */
-#define  SPDIFRX_DR1_DRNL2                 0x0000FFFFU        /*!<Data value Channel A      */
-
-/*******************  Bit definition for SPDIFRX_CSR register   *******************/
-#define  SPDIFRX_CSR_USR                   0x0000FFFFU        /*!<User data information           */
-#define  SPDIFRX_CSR_CS                    0x00FF0000U        /*!<Channel A status information    */
-#define  SPDIFRX_CSR_SOB                   0x01000000U        /*!<Start Of Block                  */
-
-/*******************  Bit definition for SPDIFRX_DIR register    *******************/
-#define  SPDIFRX_DIR_THI                   0x000013FFU        /*!<Threshold LOW      */
-#define  SPDIFRX_DIR_TLO                   0x1FFF0000U        /*!<Threshold HIGH     */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          SD host Interface                                 */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SDMMC_POWER register  ******************/
-#define  SDMMC_POWER_PWRCTRL                  0x03U               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDMMC_POWER_PWRCTRL_0                0x01U               /*!<Bit 0 */
-#define  SDMMC_POWER_PWRCTRL_1                0x02U               /*!<Bit 1 */
-
-/******************  Bit definition for SDMMC_CLKCR register  ******************/
-#define  SDMMC_CLKCR_CLKDIV                   0x00FFU            /*!<Clock divide factor             */
-#define  SDMMC_CLKCR_CLKEN                    0x0100U            /*!<Clock enable bit                */
-#define  SDMMC_CLKCR_PWRSAV                   0x0200U            /*!<Power saving configuration bit  */
-#define  SDMMC_CLKCR_BYPASS                   0x0400U            /*!<Clock divider bypass enable bit */
-         
-#define  SDMMC_CLKCR_WIDBUS                   0x1800U            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDMMC_CLKCR_WIDBUS_0                 0x0800U            /*!<Bit 0 */
-#define  SDMMC_CLKCR_WIDBUS_1                 0x1000U            /*!<Bit 1 */
-         
-#define  SDMMC_CLKCR_NEGEDGE                  0x2000U            /*!<SDMMC_CK dephasing selection bit */
-#define  SDMMC_CLKCR_HWFC_EN                  0x4000U            /*!<HW Flow Control enable          */
-
-/*******************  Bit definition for SDMMC_ARG register  *******************/
-#define  SDMMC_ARG_CMDARG                     0xFFFFFFFFU            /*!<Command argument */
-
-/*******************  Bit definition for SDMMC_CMD register  *******************/
-#define  SDMMC_CMD_CMDINDEX                   0x003FU            /*!<Command Index                               */
-         
-#define  SDMMC_CMD_WAITRESP                   0x00C0U            /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDMMC_CMD_WAITRESP_0                 0x0040U            /*!< Bit 0 */
-#define  SDMMC_CMD_WAITRESP_1                 0x0080U            /*!< Bit 1 */
-         
-#define  SDMMC_CMD_WAITINT                    0x0100U            /*!<CPSM Waits for Interrupt Request                               */
-#define  SDMMC_CMD_WAITPEND                   0x0200U            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDMMC_CMD_CPSMEN                     0x0400U            /*!<Command path state machine (CPSM) Enable bit                   */
-#define  SDMMC_CMD_SDIOSUSPEND                0x0800U            /*!<SD I/O suspend command                                         */
-
-/*****************  Bit definition for SDMMC_RESPCMD register  *****************/
-#define  SDMMC_RESPCMD_RESPCMD                0x3FU               /*!<Response command index */
-
-/******************  Bit definition for SDMMC_RESP0 register  ******************/
-#define  SDMMC_RESP0_CARDSTATUS0              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDMMC_RESP1 register  ******************/
-#define  SDMMC_RESP1_CARDSTATUS1              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDMMC_RESP2 register  ******************/
-#define  SDMMC_RESP2_CARDSTATUS2              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDMMC_RESP3 register  ******************/
-#define  SDMMC_RESP3_CARDSTATUS3              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDMMC_RESP4 register  ******************/
-#define  SDMMC_RESP4_CARDSTATUS4              0xFFFFFFFFU        /*!<Card Status */
-
-/******************  Bit definition for SDMMC_DTIMER register  *****************/
-#define  SDMMC_DTIMER_DATATIME                0xFFFFFFFFU        /*!<Data timeout period. */
-
-/******************  Bit definition for SDMMC_DLEN register  *******************/
-#define  SDMMC_DLEN_DATALENGTH                0x01FFFFFFU        /*!<Data length value    */
-
-/******************  Bit definition for SDMMC_DCTRL register  ******************/
-#define  SDMMC_DCTRL_DTEN                     0x0001U            /*!<Data transfer enabled bit         */
-#define  SDMMC_DCTRL_DTDIR                    0x0002U            /*!<Data transfer direction selection */
-#define  SDMMC_DCTRL_DTMODE                   0x0004U            /*!<Data transfer mode selection      */
-#define  SDMMC_DCTRL_DMAEN                    0x0008U            /*!<DMA enabled bit                   */
-
-#define  SDMMC_DCTRL_DBLOCKSIZE               0x00F0U            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDMMC_DCTRL_DBLOCKSIZE_0             0x0010U            /*!<Bit 0 */
-#define  SDMMC_DCTRL_DBLOCKSIZE_1             0x0020U            /*!<Bit 1 */
-#define  SDMMC_DCTRL_DBLOCKSIZE_2             0x0040U            /*!<Bit 2 */
-#define  SDMMC_DCTRL_DBLOCKSIZE_3             0x0080U            /*!<Bit 3 */
-
-#define  SDMMC_DCTRL_RWSTART                  0x0100U            /*!<Read wait start         */
-#define  SDMMC_DCTRL_RWSTOP                   0x0200U            /*!<Read wait stop          */
-#define  SDMMC_DCTRL_RWMOD                    0x0400U            /*!<Read wait mode          */
-#define  SDMMC_DCTRL_SDIOEN                   0x0800U            /*!<SD I/O enable functions */
-
-/******************  Bit definition for SDMMC_DCOUNT register  *****************/
-#define  SDMMC_DCOUNT_DATACOUNT               0x01FFFFFFU        /*!<Data count value */
-
-/******************  Bit definition for SDMMC_STA registe  ********************/
-#define  SDMMC_STA_CCRCFAIL                   0x00000001U        /*!<Command response received (CRC check failed)  */
-#define  SDMMC_STA_DCRCFAIL                   0x00000002U        /*!<Data block sent/received (CRC check failed)   */
-#define  SDMMC_STA_CTIMEOUT                   0x00000004U        /*!<Command response timeout                      */
-#define  SDMMC_STA_DTIMEOUT                   0x00000008U        /*!<Data timeout                                  */
-#define  SDMMC_STA_TXUNDERR                   0x00000010U        /*!<Transmit FIFO underrun error                  */
-#define  SDMMC_STA_RXOVERR                    0x00000020U        /*!<Received FIFO overrun error                   */
-#define  SDMMC_STA_CMDREND                    0x00000040U        /*!<Command response received (CRC check passed)  */
-#define  SDMMC_STA_CMDSENT                    0x00000080U        /*!<Command sent (no response required)           */
-#define  SDMMC_STA_DATAEND                    0x00000100U        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
-#define  SDMMC_STA_DBCKEND                    0x00000400U        /*!<Data block sent/received (CRC check passed)   */
-#define  SDMMC_STA_CMDACT                     0x00000800U        /*!<Command transfer in progress                  */
-#define  SDMMC_STA_TXACT                      0x00001000U        /*!<Data transmit in progress                     */
-#define  SDMMC_STA_RXACT                      0x00002000U        /*!<Data receive in progress                      */
-#define  SDMMC_STA_TXFIFOHE                   0x00004000U        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDMMC_STA_RXFIFOHF                   0x00008000U        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDMMC_STA_TXFIFOF                    0x00010000U        /*!<Transmit FIFO full                            */
-#define  SDMMC_STA_RXFIFOF                    0x00020000U        /*!<Receive FIFO full                             */
-#define  SDMMC_STA_TXFIFOE                    0x00040000U        /*!<Transmit FIFO empty                           */
-#define  SDMMC_STA_RXFIFOE                    0x00080000U        /*!<Receive FIFO empty                            */
-#define  SDMMC_STA_TXDAVL                     0x00100000U        /*!<Data available in transmit FIFO               */
-#define  SDMMC_STA_RXDAVL                     0x00200000U        /*!<Data available in receive FIFO                */
-#define  SDMMC_STA_SDIOIT                     0x00400000U        /*!<SDMMC interrupt received                       */
-
-/*******************  Bit definition for SDMMC_ICR register  *******************/
-#define  SDMMC_ICR_CCRCFAILC                  0x00000001U        /*!<CCRCFAIL flag clear bit */
-#define  SDMMC_ICR_DCRCFAILC                  0x00000002U        /*!<DCRCFAIL flag clear bit */
-#define  SDMMC_ICR_CTIMEOUTC                  0x00000004U        /*!<CTIMEOUT flag clear bit */
-#define  SDMMC_ICR_DTIMEOUTC                  0x00000008U        /*!<DTIMEOUT flag clear bit */
-#define  SDMMC_ICR_TXUNDERRC                  0x00000010U        /*!<TXUNDERR flag clear bit */
-#define  SDMMC_ICR_RXOVERRC                   0x00000020U        /*!<RXOVERR flag clear bit  */
-#define  SDMMC_ICR_CMDRENDC                   0x00000040U        /*!<CMDREND flag clear bit  */
-#define  SDMMC_ICR_CMDSENTC                   0x00000080U        /*!<CMDSENT flag clear bit  */
-#define  SDMMC_ICR_DATAENDC                   0x00000100U        /*!<DATAEND flag clear bit  */
-#define  SDMMC_ICR_DBCKENDC                   0x00000400U        /*!<DBCKEND flag clear bit  */
-#define  SDMMC_ICR_SDIOITC                    0x00400000U        /*!<SDMMCIT flag clear bit   */
-
-/******************  Bit definition for SDMMC_MASK register  *******************/
-#define  SDMMC_MASK_CCRCFAILIE                0x00000001U        /*!<Command CRC Fail Interrupt Enable          */
-#define  SDMMC_MASK_DCRCFAILIE                0x00000002U        /*!<Data CRC Fail Interrupt Enable             */
-#define  SDMMC_MASK_CTIMEOUTIE                0x00000004U        /*!<Command TimeOut Interrupt Enable           */
-#define  SDMMC_MASK_DTIMEOUTIE                0x00000008U        /*!<Data TimeOut Interrupt Enable              */
-#define  SDMMC_MASK_TXUNDERRIE                0x00000010U        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
-#define  SDMMC_MASK_RXOVERRIE                 0x00000020U        /*!<Rx FIFO OverRun Error Interrupt Enable     */
-#define  SDMMC_MASK_CMDRENDIE                 0x00000040U        /*!<Command Response Received Interrupt Enable */
-#define  SDMMC_MASK_CMDSENTIE                 0x00000080U        /*!<Command Sent Interrupt Enable              */
-#define  SDMMC_MASK_DATAENDIE                 0x00000100U        /*!<Data End Interrupt Enable                  */
-#define  SDMMC_MASK_DBCKENDIE                 0x00000400U        /*!<Data Block End Interrupt Enable            */
-#define  SDMMC_MASK_CMDACTIE                  0x00000800U        /*!<CCommand Acting Interrupt Enable           */
-#define  SDMMC_MASK_TXACTIE                   0x00001000U        /*!<Data Transmit Acting Interrupt Enable      */
-#define  SDMMC_MASK_RXACTIE                   0x00002000U        /*!<Data receive acting interrupt enabled      */
-#define  SDMMC_MASK_TXFIFOHEIE                0x00004000U        /*!<Tx FIFO Half Empty interrupt Enable        */
-#define  SDMMC_MASK_RXFIFOHFIE                0x00008000U        /*!<Rx FIFO Half Full interrupt Enable         */
-#define  SDMMC_MASK_TXFIFOFIE                 0x00010000U        /*!<Tx FIFO Full interrupt Enable              */
-#define  SDMMC_MASK_RXFIFOFIE                 0x00020000U        /*!<Rx FIFO Full interrupt Enable              */
-#define  SDMMC_MASK_TXFIFOEIE                 0x00040000U        /*!<Tx FIFO Empty interrupt Enable             */
-#define  SDMMC_MASK_RXFIFOEIE                 0x00080000U        /*!<Rx FIFO Empty interrupt Enable             */
-#define  SDMMC_MASK_TXDAVLIE                  0x00100000U        /*!<Data available in Tx FIFO interrupt Enable */
-#define  SDMMC_MASK_RXDAVLIE                  0x00200000U        /*!<Data available in Rx FIFO interrupt Enable */
-#define  SDMMC_MASK_SDIOITIE                  0x00400000U        /*!<SDMMC Mode Interrupt Received interrupt Enable */
-
-/*****************  Bit definition for SDMMC_FIFOCNT register  *****************/
-#define  SDMMC_FIFOCNT_FIFOCOUNT              0x00FFFFFFU        /*!<Remaining number of words to be written to or read from the FIFO */
-
-/******************  Bit definition for SDMMC_FIFO register  *******************/
-#define  SDMMC_FIFO_FIFODATA                  0xFFFFFFFFU        /*!<Receive and transmit FIFO data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface (SPI)                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        0x00000001U        /*!< Clock Phase                        */
-#define  SPI_CR1_CPOL                        0x00000002U        /*!< Clock Polarity                     */
-#define  SPI_CR1_MSTR                        0x00000004U        /*!< Master Selection                   */
-#define  SPI_CR1_BR                          0x00000038U        /*!< BR[2:0] bits (Baud Rate Control)   */
-#define  SPI_CR1_BR_0                        0x00000008U        /*!< Bit 0 */
-#define  SPI_CR1_BR_1                        0x00000010U        /*!< Bit 1 */
-#define  SPI_CR1_BR_2                        0x00000020U        /*!< Bit 2 */
-#define  SPI_CR1_SPE                         0x00000040U        /*!< SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    0x00000080U        /*!< Frame Format                        */
-#define  SPI_CR1_SSI                         0x00000100U        /*!< Internal slave select               */
-#define  SPI_CR1_SSM                         0x00000200U        /*!< Software slave management           */
-#define  SPI_CR1_RXONLY                      0x00000400U        /*!< Receive only                        */
-#define  SPI_CR1_CRCL                        0x00000800U        /*!< CRC Length                          */
-#define  SPI_CR1_CRCNEXT                     0x00001000U        /*!< Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       0x00002000U        /*!< Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      0x00004000U        /*!< Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    0x00008000U        /*!< Bidirectional data mode enable      */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     0x00000001U        /*!< Rx Buffer DMA Enable                 */
-#define  SPI_CR2_TXDMAEN                     0x00000002U        /*!< Tx Buffer DMA Enable                 */
-#define  SPI_CR2_SSOE                        0x00000004U        /*!< SS Output Enable                     */
-#define  SPI_CR2_NSSP                        0x00000008U        /*!< NSS pulse management Enable          */
-#define  SPI_CR2_FRF                         0x00000010U        /*!< Frame Format Enable                  */
-#define  SPI_CR2_ERRIE                       0x00000020U        /*!< Error Interrupt Enable               */
-#define  SPI_CR2_RXNEIE                      0x00000040U        /*!< RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       0x00000080U        /*!< Tx buffer Empty Interrupt Enable     */
-#define  SPI_CR2_DS                          0x00000F00U        /*!< DS[3:0] Data Size                    */
-#define  SPI_CR2_DS_0                        0x00000100U        /*!< Bit 0 */
-#define  SPI_CR2_DS_1                        0x00000200U        /*!< Bit 1 */
-#define  SPI_CR2_DS_2                        0x00000400U        /*!< Bit 2 */
-#define  SPI_CR2_DS_3                        0x00000800U        /*!< Bit 3 */
-#define  SPI_CR2_FRXTH                       0x00001000U        /*!< FIFO reception Threshold           */
-#define  SPI_CR2_LDMARX                      0x00002000U        /*!< Last DMA transfer for reception    */
-#define  SPI_CR2_LDMATX                      0x00004000U        /*!< Last DMA transfer for transmission */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         0x00000001U        /*!< Receive buffer Not Empty  */
-#define  SPI_SR_TXE                          0x00000002U        /*!< Transmit buffer Empty     */
-#define  SPI_SR_CHSIDE                       0x00000004U        /*!< Channel side              */
-#define  SPI_SR_UDR                          0x00000008U        /*!< Underrun flag             */
-#define  SPI_SR_CRCERR                       0x00000010U        /*!< CRC Error flag            */
-#define  SPI_SR_MODF                         0x00000020U        /*!< Mode fault                */
-#define  SPI_SR_OVR                          0x00000040U        /*!< Overrun flag              */
-#define  SPI_SR_BSY                          0x00000080U        /*!< Busy flag                 */
-#define  SPI_SR_FRE                          0x00000100U        /*!< TI frame format error     */
-#define  SPI_SR_FRLVL                        0x00000600U        /*!< FIFO Reception Level      */
-#define  SPI_SR_FRLVL_0                      0x00000200U        /*!< Bit 0 */
-#define  SPI_SR_FRLVL_1                      0x00000400U        /*!< Bit 1 */
-#define  SPI_SR_FTLVL                        0x00001800U        /*!< FIFO Transmission Level   */
-#define  SPI_SR_FTLVL_0                      0x00000800U        /*!< Bit 0 */
-#define  SPI_SR_FTLVL_1                      0x00001000U        /*!< Bit 1 */  
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           0xFFFFU            /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   0xFFFFU            /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    0xFFFFU            /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    0xFFFFU            /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   0x00000001U        /*!<Channel length (number of bits per audio channel) */
-#define  SPI_I2SCFGR_DATLEN                  0x00000006U        /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define  SPI_I2SCFGR_DATLEN_0                0x00000002U        /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                0x00000004U        /*!<Bit 1 */
-#define  SPI_I2SCFGR_CKPOL                   0x00000008U        /*!<steady state clock polarity                       */
-#define  SPI_I2SCFGR_I2SSTD                  0x00000030U        /*!<I2SSTD[1:0] bits (I2S standard selection)         */
-#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U        /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U        /*!<Bit 1 */
-#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U        /*!<PCM frame synchronization                         */
-#define  SPI_I2SCFGR_I2SCFG                  0x00000300U        /*!<I2SCFG[1:0] bits (I2S configuration mode)         */
-#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U        /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U        /*!<Bit 1 */
-#define  SPI_I2SCFGR_I2SE                    0x00000400U        /*!<I2S Enable                                        */
-#define  SPI_I2SCFGR_I2SMOD                  0x00000800U        /*!<I2S mode selection                                */
-#define  SPI_I2SCFGR_ASTRTEN                 0x00001000U        /*!<Asynchronous start enable                        */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    0x00FFU            /*!<I2S Linear prescaler         */
-#define  SPI_I2SPR_ODD                       0x0100U            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     0x0200U            /*!<Master Clock Output Enable   */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 SYSCFG                                     */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
-#define SYSCFG_MEMRMP_MEM_BOOT         0x00000001U /*!< Boot information after Reset */
-
-#define SYSCFG_MEMRMP_SWP_FB           0x00000100U /*!< User Flash Bank swap    */
-
-#define SYSCFG_MEMRMP_SWP_FMC          0x00000C00U /*!< FMC Memory Mapping swapping */
-#define SYSCFG_MEMRMP_SWP_FMC_0        0x00000400U 
-#define SYSCFG_MEMRMP_SWP_FMC_1        0x00000800U 
-
-/******************  Bit definition for SYSCFG_PMC register  ******************/
-#define SYSCFG_PMC_I2C1_FMP             0x00000001U /*!< I2C1_FMP I2C1 Fast Mode + Enable */
-#define SYSCFG_PMC_I2C2_FMP             0x00000002U /*!< I2C2_FMP I2C2 Fast Mode + Enable */
-#define SYSCFG_PMC_I2C3_FMP             0x00000004U /*!< I2C3_FMP I2C3 Fast Mode + Enable */
-#define SYSCFG_PMC_I2C4_FMP             0x00000008U /*!< I2C4_FMP I2C4 Fast Mode + Enable */
-#define SYSCFG_PMC_I2C_PB6_FMP          0x00000010U /*!< PB6_FMP Fast Mode + Enable */
-#define SYSCFG_PMC_I2C_PB7_FMP          0x00000020U /*!< PB7_FMP Fast Mode + Enable */
-#define SYSCFG_PMC_I2C_PB8_FMP          0x00000040U /*!< PB8_FMP Fast Mode + Enable */
-#define SYSCFG_PMC_I2C_PB9_FMP          0x00000080U /*!< PB9_FMP Fast Mode + Enable */
-
-#define SYSCFG_PMC_ADCxDC2              0x00070000U /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC1DC2              0x00010000U /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC2DC2              0x00020000U /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC3DC2              0x00040000U /*!< Refer to AN4073 on how to use this bit  */
-
-#define SYSCFG_PMC_MII_RMII_SEL         0x00800000U /*!<Ethernet PHY interface selection */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
-/** 
-  * @brief   EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         0x0003U /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         0x0004U /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         0x0005U /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         0x0006U /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PI         0x0008U /*!<PI[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PJ         0x0009U /*!<PJ[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PK         0x000AU /*!<PK[0] pin */
-
-/** 
-  * @brief   EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         0x0030U /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         0x0040U /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         0x0050U /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         0x0060U /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PI         0x0080U /*!<PI[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PJ         0x0090U /*!<PJ[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PK         0x00A0U /*!<PK[1] pin */
-
-/** 
-  * @brief   EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         0x0300U /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         0x0400U /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         0x0500U /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         0x0600U /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PI         0x0800U /*!<PI[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PJ         0x0900U /*!<PJ[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PK         0x0A00U /*!<PK[2] pin */
-
-/** 
-  * @brief   EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         0x3000U /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         0x4000U /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         0x5000U /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         0x6000U /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PI         0x8000U /*!<PI[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PJ         0x9000U /*!<PJ[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PK         0xA000U /*!<PK[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
-/** 
-  * @brief   EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         0x0003U /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         0x0004U /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         0x0005U /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         0x0006U /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PI         0x0008U /*!<PI[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PJ         0x0009U /*!<PJ[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PK         0x000AU /*!<PK[4] pin */
-
-/** 
-  * @brief   EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         0x0030U /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         0x0040U /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         0x0050U /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         0x0060U /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PI         0x0080U /*!<PI[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PJ         0x0090U /*!<PJ[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PK         0x00A0U /*!<PK[5] pin */
-
-/** 
-  * @brief   EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         0x0300U /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         0x0400U /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         0x0500U /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         0x0600U /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PI         0x0800U /*!<PI[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PJ         0x0900U /*!<PJ[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PK         0x0A00U /*!<PK[6] pin */
-
-/** 
-  * @brief   EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         0x3000U /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         0x4000U /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         0x5000U /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         0x6000U /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PI         0x8000U /*!<PI[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PJ         0x9000U /*!<PJ[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PK         0xA000U /*!<PK[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
-           
-/** 
-  * @brief   EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         0x0003U /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         0x0004U /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         0x0005U /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         0x0006U /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PI         0x0008U /*!<PI[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PJ         0x0009U /*!<PJ[8] pin */
-
-/** 
-  * @brief   EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         0x0030U /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         0x0040U /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         0x0050U /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         0x0060U /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PI         0x0080U /*!<PI[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PJ         0x0090U /*!<PJ[9] pin */
-
-/** 
-  * @brief   EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        0x0300U /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        0x0400U /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        0x0500U /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        0x0600U /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PI        0x0800U /*!<PI[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PJ        0x0900U /*!<PJ[10] pin */
-
-/** 
-  * @brief   EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        0x3000U /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        0x4000U /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        0x5000U /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        0x6000U /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PI        0x8000U /*!<PI[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PJ        0x9000U /*!<PJ[11] pin */
-
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
-/** 
-  * @brief   EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        0x0003U /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        0x0004U /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        0x0005U /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        0x0006U /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PI        0x0008U /*!<PI[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PJ        0x0009U /*!<PJ[12] pin */
-
-/** 
-  * @brief   EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        0x0030U /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        0x0040U /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        0x0050U /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        0x0060U /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PI        0x0080U /*!<PI[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PJ        0x0090U /*!<PJ[13] pin */
-
-/** 
-  * @brief   EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        0x0300U /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        0x0400U /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        0x0500U /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        0x0600U /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PI        0x0800U /*!<PI[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PJ        0x0900U /*!<PJ[14] pin */
-
-/** 
-  * @brief   EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        0x3000U /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        0x4000U /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        0x5000U /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        0x6000U /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PI        0x8000U /*!<PI[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PJ        0x9000U /*!<PJ[15] pin */
-
-/******************  Bit definition for SYSCFG_CBR register  ******************/  
-#define SYSCFG_CBR_CLL                  0x00000001U /*!<Core Lockup Lock */
-#define SYSCFG_CBR_PVDL                 0x00000004U /*!<PVD Lock         */
-
-/******************  Bit definition for SYSCFG_CMPCR register  ****************/  
-#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell power-down */
-#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell ready flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    TIM                                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
-#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
-#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
-#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
-#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
-
-#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
-
-#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
-
-#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
-#define  TIM_CR1_UIFREMAP                    0x0800U            /*!<UIF status bit */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        0x00000001U            /*!<Capture/Compare Preloaded Control        */
-#define  TIM_CR2_CCUS                        0x00000004U            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        0x00000008U            /*!<Capture/Compare DMA Selection            */
-
-#define  TIM_CR2_OIS5                        0x00010000U            /*!<Output Idle state 4 (OC4 output) */
-#define  TIM_CR2_OIS6                        0x00040000U            /*!<Output Idle state 4 (OC4 output) */
-
-#define  TIM_CR2_MMS                         0x0070U           /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       0x0010U           /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       0x0020U           /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       0x0040U           /*!<Bit 2 */
-
-#define  TIM_CR2_MMS2                        0x00F00000U            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS2_0                      0x00100000U            /*!<Bit 0 */
-#define  TIM_CR2_MMS2_1                      0x00200000U            /*!<Bit 1 */
-#define  TIM_CR2_MMS2_2                      0x00400000U            /*!<Bit 2 */
-#define  TIM_CR2_MMS2_3                      0x00800000U            /*!<Bit 2 */
-
-#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
-#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
-#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
-#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        0x00010007U            /*!<SMS[2:0] bits (Slave mode selection)    */
-#define  TIM_SMCR_SMS_0                      0x00000001U            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      0x00000002U            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      0x00000004U            /*!<Bit 2 */
-#define  TIM_SMCR_SMS_3                      0x00010000U            /*!<Bit 3 */
-#define  TIM_SMCR_OCCS                       0x00000008U            /*!< OCREF clear selection */
-
-#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
-#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
-
-#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
-
-#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
-
-#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
-
-#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
-#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
-#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
-#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
-#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
-#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
-#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
-#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
-#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
-#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
-#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
-#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
-#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
-#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
-#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
-#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
-#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
-#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
-#define  TIM_SR_B2IF                         0x0100U            /*!<Break2 interrupt Flag               */
-#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          0x00000001U               /*!<Update Generation                         */
-#define  TIM_EGR_CC1G                        0x00000002U               /*!<Capture/Compare 1 Generation              */
-#define  TIM_EGR_CC2G                        0x00000004U               /*!<Capture/Compare 2 Generation              */
-#define  TIM_EGR_CC3G                        0x00000008U               /*!<Capture/Compare 3 Generation              */
-#define  TIM_EGR_CC4G                        0x00000010U               /*!<Capture/Compare 4 Generation              */
-#define  TIM_EGR_COMG                        0x00000020U               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          0x00000040U               /*!<Trigger Generation                        */
-#define  TIM_EGR_BG                          0x00000080U               /*!<Break Generation                          */
-#define  TIM_EGR_B2G                         0x00000100U              /*!<Break2 Generation                          */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      0x00000003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    0x00000001U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    0x00000002U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC1FE                     0x00000004U            /*!<Output Compare 1 Fast enable                 */
-#define  TIM_CCMR1_OC1PE                     0x00000008U            /*!<Output Compare 1 Preload enable              */
-
-#define  TIM_CCMR1_OC1M                      0x00010070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define  TIM_CCMR1_OC1M_0                    0x00000010U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    0x00000020U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    0x00000040U            /*!<Bit 2 */
-#define  TIM_CCMR1_OC1M_3                    0x00010000U            /*!<Bit 3 */
-
-#define  TIM_CCMR1_OC1CE                     0x00000080U            /*!<Output Compare 1Clear Enable                 */
-
-#define  TIM_CCMR1_CC2S                      0x00000300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    0x00000100U            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    0x00000200U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC2FE                     0x00000400U            /*!<Output Compare 2 Fast enable                 */
-#define  TIM_CCMR1_OC2PE                     0x00000800U            /*!<Output Compare 2 Preload enable              */
-
-#define  TIM_CCMR1_OC2M                      0x01007000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define  TIM_CCMR1_OC2M_0                    0x00001000U            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    0x00002000U            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    0x00004000U            /*!<Bit 2 */
-#define  TIM_CCMR1_OC2M_3                    0x01000000U            /*!<Bit 3 */
-
-#define  TIM_CCMR1_OC2CE                     0x00008000U            /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      0x00000003U        /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define  TIM_CCMR2_CC3S_0                    0x00000001U        /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    0x00000002U        /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC3FE                     0x00000004U        /*!<Output Compare 3 Fast enable           */
-#define  TIM_CCMR2_OC3PE                     0x00000008U        /*!<Output Compare 3 Preload enable        */
-
-#define  TIM_CCMR2_OC3M                      0x00010070U        /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    0x00000010U        /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    0x00000020U        /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    0x00000040U        /*!<Bit 2 */
-#define  TIM_CCMR2_OC3M_3                    0x00010000U        /*!<Bit 3 */
-
-
-
-#define  TIM_CCMR2_OC3CE                     0x00000080U        /*!<Output Compare 3 Clear Enable */
-
-#define  TIM_CCMR2_CC4S                      0x00000300U        /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    0x00000100U        /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    0x00000200U        /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC4FE                     0x00000400U        /*!<Output Compare 4 Fast enable    */
-#define  TIM_CCMR2_OC4PE                     0x00000800U        /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR2_OC4M                      0x01007000U        /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    0x00001000U        /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    0x00002000U        /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    0x00004000U        /*!<Bit 2 */
-#define  TIM_CCMR2_OC4M_3                    0x01000000U        /*!<Bit 3 */
-
-#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
-
-#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       0x00000001U            /*!<Capture/Compare 1 output enable */
-#define  TIM_CCER_CC1P                       0x00000002U            /*!<Capture/Compare 1 output Polarity */
-#define  TIM_CCER_CC1NE                      0x00000004U            /*!<Capture/Compare 1 Complementary output enable */
-#define  TIM_CCER_CC1NP                      0x00000008U            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       0x00000010U            /*!<Capture/Compare 2 output enable */
-#define  TIM_CCER_CC2P                       0x00000020U            /*!<Capture/Compare 2 output Polarity */
-#define  TIM_CCER_CC2NE                      0x00000040U            /*!<Capture/Compare 2 Complementary output enable */
-#define  TIM_CCER_CC2NP                      0x00000080U            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       0x00000100U            /*!<Capture/Compare 3 output enable */
-#define  TIM_CCER_CC3P                       0x00000200U            /*!<Capture/Compare 3 output Polarity */
-#define  TIM_CCER_CC3NE                      0x00000400U            /*!<Capture/Compare 3 Complementary output enable */
-#define  TIM_CCER_CC3NP                      0x00000800U            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       0x00001000U            /*!<Capture/Compare 4 output enable */
-#define  TIM_CCER_CC4P                       0x00002000U            /*!<Capture/Compare 4 output Polarity */
-#define  TIM_CCER_CC4NP                      0x00008000U            /*!<Capture/Compare 4 Complementary output Polarity */
-#define  TIM_CCER_CC5E                       0x00010000U            /*!<Capture/Compare 5 output enable */
-#define  TIM_CCER_CC5P                       0x00020000U            /*!<Capture/Compare 5 output Polarity */
-#define  TIM_CCER_CC6E                       0x00100000U            /*!<Capture/Compare 6 output enable */
-#define  TIM_CCER_CC6P                       0x00200000U            /*!<Capture/Compare 6 output Polarity */
-
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         ((uint8_t)0xFFU)               /*!<Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
-
-/*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        0x000000FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      0x00000001U            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      0x00000002U            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      0x00000004U            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      0x00000008U            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      0x00000010U            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      0x00000020U            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      0x00000040U            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      0x00000080U            /*!<Bit 7 */
-
-#define  TIM_BDTR_LOCK                       0x00000300U            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     0x00000100U            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     0x00000200U            /*!<Bit 1 */
-
-#define  TIM_BDTR_OSSI                       0x00000400U            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       0x00000800U            /*!<Off-State Selection for Run mode  */
-#define  TIM_BDTR_BKE                        0x00001000U            /*!<Break enable                      */
-#define  TIM_BDTR_BKP                        0x00002000U            /*!<Break Polarity                    */
-#define  TIM_BDTR_AOE                        0x00004000U            /*!<Automatic Output enable           */
-#define  TIM_BDTR_MOE                        0x00008000U            /*!<Main Output enable                */
-#define  TIM_BDTR_BKF                        0x000F0000U            /*!<Break Filter for Break1 */
-#define  TIM_BDTR_BK2F                       0x00F00000U            /*!<Break Filter for Break2 */
-#define  TIM_BDTR_BK2E                       0x01000000U            /*!<Break enable for Break2 */
-#define  TIM_BDTR_BK2P                       0x02000000U            /*!<Break Polarity for Break2 */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
-
-#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
-
-/*******************  Bit definition for TIM_OR regiter  *********************/
-#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
-#define TIM_OR_ITR1_RMP                      0x0C00U            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
-#define TIM_OR_ITR1_RMP_0                    0x0400U            /*!<Bit 0 */
-#define TIM_OR_ITR1_RMP_1                    0x0800U            /*!<Bit 1 */
-
-/******************  Bit definition for TIM_CCMR3 register  *******************/
-#define  TIM_CCMR3_OC5FE                     0x00000004U            /*!<Output Compare 5 Fast enable */
-#define  TIM_CCMR3_OC5PE                     0x00000008U            /*!<Output Compare 5 Preload enable */
-
-#define  TIM_CCMR3_OC5M                      0x00010070U            /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
-#define  TIM_CCMR3_OC5M_0                    0x00000010U            /*!<Bit 0 */
-#define  TIM_CCMR3_OC5M_1                    0x00000020U            /*!<Bit 1 */
-#define  TIM_CCMR3_OC5M_2                    0x00000040U            /*!<Bit 2 */
-#define  TIM_CCMR3_OC5M_3                    0x00010000U            /*!<Bit 3 */
-
-#define  TIM_CCMR3_OC5CE                     0x00000080U            /*!<Output Compare 5 Clear Enable */
-
-#define  TIM_CCMR3_OC6FE                     0x00000400U            /*!<Output Compare 4 Fast enable */
-#define  TIM_CCMR3_OC6PE                     0x00000800U            /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR3_OC6M                      0x01007000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR3_OC6M_0                    0x00001000U            /*!<Bit 0 */
-#define  TIM_CCMR3_OC6M_1                    0x00002000U            /*!<Bit 1 */
-#define  TIM_CCMR3_OC6M_2                    0x00004000U            /*!<Bit 2 */
-#define  TIM_CCMR3_OC6M_3                    0x01000000U            /*!<Bit 3 */
-
-#define  TIM_CCMR3_OC6CE                     0x00008000U            /*!<Output Compare 4 Clear Enable */
-
-/*******************  Bit definition for TIM_CCR5 register  *******************/
-#define  TIM_CCR5_CCR5                       0xFFFFFFFFU        /*!<Capture/Compare 5 Value */
-#define  TIM_CCR5_GC5C1                      0x20000000U        /*!<Group Channel 5 and Channel 1 */
-#define  TIM_CCR5_GC5C2                      0x40000000U        /*!<Group Channel 5 and Channel 2 */
-#define  TIM_CCR5_GC5C3                      0x80000000U        /*!<Group Channel 5 and Channel 3 */
-
-/*******************  Bit definition for TIM_CCR6 register  *******************/
-#define  TIM_CCR6_CCR6                       ((uint16_t)0xFFFFU)            /*!<Capture/Compare 6 Value */
-
-/*******************  Bit definition for TIM1_AF1 register  *******************/
-#define TIM1_AF1_BKINE                       0x00000001U        /*!<BRK BKIN input enable */
-#define TIM1_AF1_BKDF1BKE                    0x00000100U        /*!<BRK DFSDM1_BREAK enable */
-
-/*******************  Bit definition for TIM1_AF2 register  *******************/
-#define TIM1_AF2_BK2INE                      0x00000001U        /*!<BRK2 BKIN input enable */
-#define TIM1_AF2_BK2DF1BKE                   0x00000100U        /*!<BRK2 DFSDM1_BREAK enable */
-
-/*******************  Bit definition for TIM8_AF1 register  *******************/
-#define TIM8_AF1_BKINE                       0x00000001U        /*!<BRK BKIN input enable */
-#define TIM8_AF1_BKDF1BKE                    0x00000100U        /*!<BRK DFSDM1_BREAK enable */
-
-/*******************  Bit definition for TIM8_AF2 register  *******************/
-#define TIM8_AF2_BK2INE                      0x00000001U        /*!<BRK2 BKIN2 input enable */
-#define TIM8_AF2_BK2DF1BKE                   0x00000100U        /*!<BRK2 DFSDM1_BREAK enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Low Power Timer (LPTIM)                            */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for LPTIM_ISR register  *******************/
-#define  LPTIM_ISR_CMPM                         0x00000001U            /*!< Compare match                       */
-#define  LPTIM_ISR_ARRM                         0x00000002U            /*!< Autoreload match                    */
-#define  LPTIM_ISR_EXTTRIG                      0x00000004U            /*!< External trigger edge event         */
-#define  LPTIM_ISR_CMPOK                        0x00000008U            /*!< Compare register update OK          */
-#define  LPTIM_ISR_ARROK                        0x00000010U            /*!< Autoreload register update OK       */
-#define  LPTIM_ISR_UP                           0x00000020U            /*!< Counter direction change down to up */
-#define  LPTIM_ISR_DOWN                         0x00000040U            /*!< Counter direction change up to down */
-
-/******************  Bit definition for LPTIM_ICR register  *******************/
-#define  LPTIM_ICR_CMPMCF                       0x00000001U            /*!< Compare match Clear Flag                       */
-#define  LPTIM_ICR_ARRMCF                       0x00000002U            /*!< Autoreload match Clear Flag                    */
-#define  LPTIM_ICR_EXTTRIGCF                    0x00000004U            /*!< External trigger edge event Clear Flag         */
-#define  LPTIM_ICR_CMPOKCF                      0x00000008U            /*!< Compare register update OK Clear Flag          */
-#define  LPTIM_ICR_ARROKCF                      0x00000010U            /*!< Autoreload register update OK Clear Flag       */
-#define  LPTIM_ICR_UPCF                         0x00000020U            /*!< Counter direction change down to up Clear Flag */
-#define  LPTIM_ICR_DOWNCF                       0x00000040U            /*!< Counter direction change up to down Clear Flag */
-
-/******************  Bit definition for LPTIM_IER register *******************/
-#define  LPTIM_IER_CMPMIE                       0x00000001U            /*!< Compare match Interrupt Enable                       */
-#define  LPTIM_IER_ARRMIE                       0x00000002U            /*!< Autoreload match Interrupt Enable                    */
-#define  LPTIM_IER_EXTTRIGIE                    0x00000004U            /*!< External trigger edge event Interrupt Enable         */
-#define  LPTIM_IER_CMPOKIE                      0x00000008U            /*!< Compare register update OK Interrupt Enable          */
-#define  LPTIM_IER_ARROKIE                      0x00000010U            /*!< Autoreload register update OK Interrupt Enable       */
-#define  LPTIM_IER_UPIE                         0x00000020U            /*!< Counter direction change down to up Interrupt Enable */
-#define  LPTIM_IER_DOWNIE                       0x00000040U            /*!< Counter direction change up to down Interrupt Enable */
-
-/******************  Bit definition for LPTIM_CFGR register*******************/
-#define  LPTIM_CFGR_CKSEL                       0x00000001U             /*!< Clock selector */
-
-#define  LPTIM_CFGR_CKPOL                       0x00000006U             /*!< CKPOL[1:0] bits (Clock polarity) */
-#define  LPTIM_CFGR_CKPOL_0                     0x00000002U             /*!< Bit 0 */
-#define  LPTIM_CFGR_CKPOL_1                     0x00000004U             /*!< Bit 1 */
-
-#define  LPTIM_CFGR_CKFLT                       0x00000018U             /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
-#define  LPTIM_CFGR_CKFLT_0                     0x00000008U             /*!< Bit 0 */
-#define  LPTIM_CFGR_CKFLT_1                     0x00000010U             /*!< Bit 1 */
-
-#define  LPTIM_CFGR_TRGFLT                      0x000000C0U             /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
-#define  LPTIM_CFGR_TRGFLT_0                    0x00000040U             /*!< Bit 0 */
-#define  LPTIM_CFGR_TRGFLT_1                    0x00000080U             /*!< Bit 1 */
-
-#define  LPTIM_CFGR_PRESC                       0x00000E00U             /*!< PRESC[2:0] bits (Clock prescaler) */
-#define  LPTIM_CFGR_PRESC_0                     0x00000200U             /*!< Bit 0 */
-#define  LPTIM_CFGR_PRESC_1                     0x00000400U             /*!< Bit 1 */
-#define  LPTIM_CFGR_PRESC_2                     0x00000800U             /*!< Bit 2 */
-
-#define  LPTIM_CFGR_TRIGSEL                     0x0000E000U             /*!< TRIGSEL[2:0]] bits (Trigger selector) */
-#define  LPTIM_CFGR_TRIGSEL_0                   0x00002000U             /*!< Bit 0 */
-#define  LPTIM_CFGR_TRIGSEL_1                   0x00004000U             /*!< Bit 1 */
-#define  LPTIM_CFGR_TRIGSEL_2                   0x00008000U             /*!< Bit 2 */
-
-#define  LPTIM_CFGR_TRIGEN                      0x00060000U             /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
-#define  LPTIM_CFGR_TRIGEN_0                    0x00020000U             /*!< Bit 0 */
-#define  LPTIM_CFGR_TRIGEN_1                    0x00040000U             /*!< Bit 1 */
-
-#define  LPTIM_CFGR_TIMOUT                      0x00080000U             /*!< Timout enable           */
-#define  LPTIM_CFGR_WAVE                        0x00100000U             /*!< Waveform shape          */
-#define  LPTIM_CFGR_WAVPOL                      0x00200000U             /*!< Waveform shape polarity */
-#define  LPTIM_CFGR_PRELOAD                     0x00400000U             /*!< Reg update mode         */
-#define  LPTIM_CFGR_COUNTMODE                   0x00800000U             /*!< Counter mode enable     */     
-#define  LPTIM_CFGR_ENC                         0x01000000U             /*!< Encoder mode enable     */          
-
-/******************  Bit definition for LPTIM_CR register  ********************/
-#define  LPTIM_CR_ENABLE                        0x00000001U             /*!< LPTIMer enable                 */
-#define  LPTIM_CR_SNGSTRT                       0x00000002U             /*!< Timer start in single mode     */
-#define  LPTIM_CR_CNTSTRT                       0x00000004U             /*!< Timer start in continuous mode */
-
-/******************  Bit definition for LPTIM_CMP register *******************/
-#define  LPTIM_CMP_CMP                          0x0000FFFFU             /*!< Compare register     */
-
-/******************  Bit definition for LPTIM_ARR register *******************/
-#define  LPTIM_ARR_ARR                          0x0000FFFFU             /*!< Auto reload register */
-
-/******************  Bit definition for LPTIM_CNT register *******************/
-#define  LPTIM_CNT_CNT                          0x0000FFFFU             /*!< Counter register     */
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_UE                        0x00000001U            /*!< USART Enable                                    */
-#define  USART_CR1_RE                        0x00000004U            /*!< Receiver Enable                                 */
-#define  USART_CR1_TE                        0x00000008U            /*!< Transmitter Enable                              */
-#define  USART_CR1_IDLEIE                    0x00000010U            /*!< IDLE Interrupt Enable                           */
-#define  USART_CR1_RXNEIE                    0x00000020U            /*!< RXNE Interrupt Enable                           */
-#define  USART_CR1_TCIE                      0x00000040U            /*!< Transmission Complete Interrupt Enable          */
-#define  USART_CR1_TXEIE                     0x00000080U            /*!< TXE Interrupt Enable                            */
-#define  USART_CR1_PEIE                      0x00000100U            /*!< PE Interrupt Enable                             */
-#define  USART_CR1_PS                        0x00000200U            /*!< Parity Selection                                */
-#define  USART_CR1_PCE                       0x00000400U            /*!< Parity Control Enable                           */
-#define  USART_CR1_WAKE                      0x00000800U            /*!< Receiver Wakeup method                          */
-#define  USART_CR1_M                         0x10001000U            /*!< Word length                                     */
-#define  USART_CR1_M_0                       0x00001000U            /*!< Word length - Bit 0                             */
-#define  USART_CR1_MME                       0x00002000U            /*!< Mute Mode Enable                                */
-#define  USART_CR1_CMIE                      0x00004000U            /*!< Character match interrupt enable                */
-#define  USART_CR1_OVER8                     0x00008000U            /*!< Oversampling by 8-bit or 16-bit mode            */
-#define  USART_CR1_DEDT                      0x001F0000U            /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
-#define  USART_CR1_DEDT_0                    0x00010000U            /*!< Bit 0 */
-#define  USART_CR1_DEDT_1                    0x00020000U            /*!< Bit 1 */
-#define  USART_CR1_DEDT_2                    0x00040000U            /*!< Bit 2 */
-#define  USART_CR1_DEDT_3                    0x00080000U            /*!< Bit 3 */
-#define  USART_CR1_DEDT_4                    0x00100000U            /*!< Bit 4 */
-#define  USART_CR1_DEAT                      0x03E00000U            /*!< DEAT[4:0] bits (Driver Enable Assertion Time)   */
-#define  USART_CR1_DEAT_0                    0x00200000U            /*!< Bit 0 */
-#define  USART_CR1_DEAT_1                    0x00400000U            /*!< Bit 1 */
-#define  USART_CR1_DEAT_2                    0x00800000U            /*!< Bit 2 */
-#define  USART_CR1_DEAT_3                    0x01000000U            /*!< Bit 3 */
-#define  USART_CR1_DEAT_4                    0x02000000U            /*!< Bit 4 */
-#define  USART_CR1_RTOIE                     0x04000000U            /*!< Receive Time Out interrupt enable */
-#define  USART_CR1_EOBIE                     0x08000000U            /*!< End of Block interrupt enable     */
-#define  USART_CR1_M_1                       0x10000000U            /*!< Word length - Bit 1               */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADDM7                     0x00000010U            /*!< 7-bit or 4-bit Address Detection       */
-#define  USART_CR2_LBDL                      0x00000020U            /*!< LIN Break Detection Length             */
-#define  USART_CR2_LBDIE                     0x00000040U            /*!< LIN Break Detection Interrupt Enable   */
-#define  USART_CR2_LBCL                      0x00000100U            /*!< Last Bit Clock pulse                   */
-#define  USART_CR2_CPHA                      0x00000200U            /*!< Clock Phase                            */
-#define  USART_CR2_CPOL                      0x00000400U            /*!< Clock Polarity                         */
-#define  USART_CR2_CLKEN                     0x00000800U            /*!< Clock Enable                           */
-#define  USART_CR2_STOP                      0x00003000U            /*!< STOP[1:0] bits (STOP bits)             */
-#define  USART_CR2_STOP_0                    0x00001000U            /*!< Bit 0 */
-#define  USART_CR2_STOP_1                    0x00002000U            /*!< Bit 1 */
-#define  USART_CR2_LINEN                     0x00004000U            /*!< LIN mode enable                        */
-#define  USART_CR2_SWAP                      0x00008000U            /*!< SWAP TX/RX pins                        */
-#define  USART_CR2_RXINV                     0x00010000U            /*!< RX pin active level inversion          */
-#define  USART_CR2_TXINV                     0x00020000U            /*!< TX pin active level inversion          */
-#define  USART_CR2_DATAINV                   0x00040000U            /*!< Binary data inversion                  */
-#define  USART_CR2_MSBFIRST                  0x00080000U            /*!< Most Significant Bit First             */
-#define  USART_CR2_ABREN                     0x00100000U            /*!< Auto Baud-Rate Enable                  */
-#define  USART_CR2_ABRMODE                   0x00600000U            /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
-#define  USART_CR2_ABRMODE_0                 0x00200000U            /*!< Bit 0 */
-#define  USART_CR2_ABRMODE_1                 0x00400000U            /*!< Bit 1 */
-#define  USART_CR2_RTOEN                     0x00800000U            /*!< Receiver Time-Out enable  */
-#define  USART_CR2_ADD                       0xFF000000U            /*!< Address of the USART node */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       0x00000001U            /*!< Error Interrupt Enable                         */
-#define  USART_CR3_IREN                      0x00000002U            /*!< IrDA mode Enable                               */
-#define  USART_CR3_IRLP                      0x00000004U            /*!< IrDA Low-Power                                 */
-#define  USART_CR3_HDSEL                     0x00000008U            /*!< Half-Duplex Selection                          */
-#define  USART_CR3_NACK                      0x00000010U            /*!< SmartCard NACK enable                          */
-#define  USART_CR3_SCEN                      0x00000020U            /*!< SmartCard mode enable                          */
-#define  USART_CR3_DMAR                      0x00000040U            /*!< DMA Enable Receiver                            */
-#define  USART_CR3_DMAT                      0x00000080U            /*!< DMA Enable Transmitter                         */
-#define  USART_CR3_RTSE                      0x00000100U            /*!< RTS Enable                                     */
-#define  USART_CR3_CTSE                      0x00000200U            /*!< CTS Enable                                     */
-#define  USART_CR3_CTSIE                     0x00000400U            /*!< CTS Interrupt Enable                           */
-#define  USART_CR3_ONEBIT                    0x00000800U            /*!< One sample bit method enable                   */
-#define  USART_CR3_OVRDIS                    0x00001000U            /*!< Overrun Disable                                */
-#define  USART_CR3_DDRE                      0x00002000U            /*!< DMA Disable on Reception Error                 */
-#define  USART_CR3_DEM                       0x00004000U            /*!< Driver Enable Mode                             */
-#define  USART_CR3_DEP                       0x00008000U            /*!< Driver Enable Polarity Selection               */
-#define  USART_CR3_SCARCNT                   0x000E0000U            /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
-#define  USART_CR3_SCARCNT_0                 0x00020000U            /*!< Bit 0 */
-#define  USART_CR3_SCARCNT_1                 0x00040000U            /*!< Bit 1 */
-#define  USART_CR3_SCARCNT_2                 0x00080000U            /*!< Bit 2 */
-
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_FRACTION              0x000FU                /*!< Fraction of USARTDIV */
-#define  USART_BRR_DIV_MANTISSA              0xFFF0U                /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      0x00FFU                /*!< PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_GT                       0xFF00U                /*!< GT[7:0] bits (Guard time value) */
-
-
-/*******************  Bit definition for USART_RTOR register  *****************/
-#define  USART_RTOR_RTO                      0x00FFFFFFU            /*!< Receiver Time Out Value */
-#define  USART_RTOR_BLEN                     0xFF000000U            /*!< Block Length */
-
-/*******************  Bit definition for USART_RQR register  ******************/
-#define  USART_RQR_ABRRQ                     0x0001U                /*!< Auto-Baud Rate Request      */
-#define  USART_RQR_SBKRQ                     0x0002U                /*!< Send Break Request          */
-#define  USART_RQR_MMRQ                      0x0004U                /*!< Mute Mode Request           */
-#define  USART_RQR_RXFRQ                     0x0008U                /*!< Receive Data flush Request  */
-#define  USART_RQR_TXFRQ                     0x0010U                /*!< Transmit data flush Request */
-
-/*******************  Bit definition for USART_ISR register  ******************/
-#define  USART_ISR_PE                        0x00000001U            /*!< Parity Error                        */
-#define  USART_ISR_FE                        0x00000002U            /*!< Framing Error                       */
-#define  USART_ISR_NE                        0x00000004U            /*!< Noise detected Flag                 */
-#define  USART_ISR_ORE                       0x00000008U            /*!< OverRun Error                       */
-#define  USART_ISR_IDLE                      0x00000010U            /*!< IDLE line detected                  */
-#define  USART_ISR_RXNE                      0x00000020U            /*!< Read Data Register Not Empty        */
-#define  USART_ISR_TC                        0x00000040U            /*!< Transmission Complete               */
-#define  USART_ISR_TXE                       0x00000080U            /*!< Transmit Data Register Empty        */
-#define  USART_ISR_LBDF                      0x00000100U            /*!< LIN Break Detection Flag            */
-#define  USART_ISR_CTSIF                     0x00000200U            /*!< CTS interrupt flag                  */
-#define  USART_ISR_CTS                       0x00000400U            /*!< CTS flag                            */
-#define  USART_ISR_RTOF                      0x00000800U            /*!< Receiver Time Out                   */
-#define  USART_ISR_EOBF                      0x00001000U            /*!< End Of Block Flag                   */
-#define  USART_ISR_ABRE                      0x00004000U            /*!< Auto-Baud Rate Error                */
-#define  USART_ISR_ABRF                      0x00008000U            /*!< Auto-Baud Rate Flag                 */
-#define  USART_ISR_BUSY                      0x00010000U            /*!< Busy Flag                           */
-#define  USART_ISR_CMF                       0x00020000U            /*!< Character Match Flag                */
-#define  USART_ISR_SBKF                      0x00040000U            /*!< Send Break Flag                     */
-#define  USART_ISR_RWU                       0x00080000U            /*!< Receive Wake Up from mute mode Flag */
-#define  USART_ISR_WUF                       0x00100000U            /*!< Wake Up from stop mode Flag         */
-#define  USART_ISR_TEACK                     0x00200000U            /*!< Transmit Enable Acknowledge Flag    */
-#define  USART_ISR_REACK                     0x00400000U            /*!< Receive Enable Acknowledge Flag     */
-
-
-/*******************  Bit definition for USART_ICR register  ******************/
-#define  USART_ICR_PECF                      0x00000001U            /*!< Parity Error Clear Flag             */
-#define  USART_ICR_FECF                      0x00000002U            /*!< Framing Error Clear Flag            */
-#define  USART_ICR_NCF                       0x00000004U            /*!< Noise detected Clear Flag           */
-#define  USART_ICR_ORECF                     0x00000008U            /*!< OverRun Error Clear Flag            */
-#define  USART_ICR_IDLECF                    0x00000010U            /*!< IDLE line detected Clear Flag       */
-#define  USART_ICR_TCCF                      0x00000040U            /*!< Transmission Complete Clear Flag    */
-#define  USART_ICR_LBDCF                     0x00000100U            /*!< LIN Break Detection Clear Flag      */
-#define  USART_ICR_CTSCF                     0x00000200U            /*!< CTS Interrupt Clear Flag            */
-#define  USART_ICR_RTOCF                     0x00000800U            /*!< Receiver Time Out Clear Flag        */
-#define  USART_ICR_EOBCF                     0x00001000U            /*!< End Of Block Clear Flag             */
-#define  USART_ICR_CMCF                      0x00020000U            /*!< Character Match Clear Flag          */
-#define  USART_ICR_WUCF                      0x00100000U            /*!< Wake Up from stop mode Clear Flag   */
-
-/*******************  Bit definition for USART_RDR register  ******************/
-#define  USART_RDR_RDR                       0x01FFU                /*!< RDR[8:0] bits (Receive Data value) */
-
-/*******************  Bit definition for USART_TDR register  ******************/
-#define  USART_TDR_TDR                       0x01FFU                /*!< TDR[8:0] bits (Transmit Data value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Window WATCHDOG                                 */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                            0x7FU                 /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T_0                          0x01U                 /*!<Bit 0 */
-#define  WWDG_CR_T_1                          0x02U                 /*!<Bit 1 */
-#define  WWDG_CR_T_2                          0x04U                 /*!<Bit 2 */
-#define  WWDG_CR_T_3                          0x08U                 /*!<Bit 3 */
-#define  WWDG_CR_T_4                          0x10U                 /*!<Bit 4 */
-#define  WWDG_CR_T_5                          0x20U                 /*!<Bit 5 */
-#define  WWDG_CR_T_6                          0x40U                 /*!<Bit 6 */
-
-
-#define  WWDG_CR_WDGA                        0x80U                  /*!<Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          0x007FU                /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W_0                        0x0001U                /*!<Bit 0 */
-#define  WWDG_CFR_W_1                        0x0002U                /*!<Bit 1 */
-#define  WWDG_CFR_W_2                        0x0004U                /*!<Bit 2 */
-#define  WWDG_CFR_W_3                        0x0008U                /*!<Bit 3 */
-#define  WWDG_CFR_W_4                        0x0010U                /*!<Bit 4 */
-#define  WWDG_CFR_W_5                        0x0020U                /*!<Bit 5 */
-#define  WWDG_CFR_W_6                        0x0040U                /*!<Bit 6 */
-
-
-#define  WWDG_CFR_WDGTB                      0x0180U                /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB_0                    0x0080U                /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB_1                    0x0100U                /*!<Bit 1 */
-
-
-#define  WWDG_CFR_EWI                        0x0200U               /*!<Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        0x01U                  /*!<Early Wakeup Interrupt Flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                DBG                                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
-#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
-
-/********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
-#define  DBGMCU_CR_DBG_STOP                  0x00000002U
-#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
-#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
-
-#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
-#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U /*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U /*!<Bit 1 */
-
-/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            0x00000001U
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            0x00000002U
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            0x00000004U
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            0x00000020U
-#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           0x00000040U
-#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           0x00000080U
-#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           0x00000100U
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
-#define  DBGMCU_APB1_FZ_DBG_CAN3_STOP            0x00002000U
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
-#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
-
-/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP            0x00000001U
-#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP            0x00000002U
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP            0x00010000U
-#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP           0x00020000U
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP           0x00040000U
-
-/******************************************************************************/
-/*                                                                            */
-/*                Ethernet MAC Registers bits definitions                     */
-/*                                                                            */
-/******************************************************************************/
-/* Bit definition for Ethernet MAC Control Register register */
-#define ETH_MACCR_WD              0x00800000U  /* Watchdog disable */
-#define ETH_MACCR_JD              0x00400000U  /* Jabber disable */
-#define ETH_MACCR_IFG             0x000E0000U  /* Inter-frame gap */
-#define ETH_MACCR_IFG_96Bit       0x00000000U  /* Minimum IFG between frames during transmission is 96Bit */
-#define ETH_MACCR_IFG_88Bit       0x00020000U  /* Minimum IFG between frames during transmission is 88Bit */
-#define ETH_MACCR_IFG_80Bit       0x00040000U  /* Minimum IFG between frames during transmission is 80Bit */
-#define ETH_MACCR_IFG_72Bit       0x00060000U  /* Minimum IFG between frames during transmission is 72Bit */
-#define ETH_MACCR_IFG_64Bit       0x00080000U  /* Minimum IFG between frames during transmission is 64Bit */        
-#define ETH_MACCR_IFG_56Bit       0x000A0000U  /* Minimum IFG between frames during transmission is 56Bit */
-#define ETH_MACCR_IFG_48Bit       0x000C0000U  /* Minimum IFG between frames during transmission is 48Bit */
-#define ETH_MACCR_IFG_40Bit       0x000E0000U  /* Minimum IFG between frames during transmission is 40Bit */              
-#define ETH_MACCR_CSD             0x00010000U  /* Carrier sense disable (during transmission) */
-#define ETH_MACCR_FES             0x00004000U  /* Fast ethernet speed */
-#define ETH_MACCR_ROD             0x00002000U  /* Receive own disable */
-#define ETH_MACCR_LM              0x00001000U  /* loopback mode */
-#define ETH_MACCR_DM              0x00000800U  /* Duplex mode */
-#define ETH_MACCR_IPCO            0x00000400U  /* IP Checksum offload */
-#define ETH_MACCR_RD              0x00000200U  /* Retry disable */
-#define ETH_MACCR_APCS            0x00000080U  /* Automatic Pad/CRC stripping */
-#define ETH_MACCR_BL              0x00000060U  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
-                                                       a transmission attempt during retries after a collision: 0 =< r <2^k */
-#define ETH_MACCR_BL_10           0x00000000U  /* k = min (n, 10) */
-#define ETH_MACCR_BL_8            0x00000020U  /* k = min (n, 8) */
-#define ETH_MACCR_BL_4            0x00000040U  /* k = min (n, 4) */
-#define ETH_MACCR_BL_1            0x00000060U  /* k = min (n, 1) */ 
-#define ETH_MACCR_DC              0x00000010U  /* Defferal check */
-#define ETH_MACCR_TE              0x00000008U  /* Transmitter enable */
-#define ETH_MACCR_RE              0x00000004U  /* Receiver enable */
-
-/* Bit definition for Ethernet MAC Frame Filter Register */
-#define ETH_MACFFR_RA             0x80000000U  /* Receive all */ 
-#define ETH_MACFFR_HPF            0x00000400U  /* Hash or perfect filter */ 
-#define ETH_MACFFR_SAF            0x00000200U  /* Source address filter enable */ 
-#define ETH_MACFFR_SAIF           0x00000100U  /* SA inverse filtering */ 
-#define ETH_MACFFR_PCF            0x000000C0U  /* Pass control frames: 3 cases */
-#define ETH_MACFFR_PCF_BlockAll                0x00000040U  /* MAC filters all control frames from reaching the application */
-#define ETH_MACFFR_PCF_ForwardAll              0x00000080U  /* MAC forwards all control frames to application even if they fail the Address Filter */
-#define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U  /* MAC forwards control frames that pass the Address Filter. */ 
-#define ETH_MACFFR_BFD             0x00000020U  /* Broadcast frame disable */ 
-#define ETH_MACFFR_PAM             0x00000010U  /* Pass all mutlicast */ 
-#define ETH_MACFFR_DAIF            0x00000008U  /* DA Inverse filtering */ 
-#define ETH_MACFFR_HM              0x00000004U  /* Hash multicast */ 
-#define ETH_MACFFR_HU              0x00000002U  /* Hash unicast */
-#define ETH_MACFFR_PM              0x00000001U  /* Promiscuous mode */
-
-/* Bit definition for Ethernet MAC Hash Table High Register */
-#define ETH_MACHTHR_HTH            0xFFFFFFFFU  /* Hash table high */
-
-/* Bit definition for Ethernet MAC Hash Table Low Register */
-#define ETH_MACHTLR_HTL            0xFFFFFFFFU  /* Hash table low */
-
-/* Bit definition for Ethernet MAC MII Address Register */
-#define ETH_MACMIIAR_PA            0x0000F800U  /* Physical layer address */ 
-#define ETH_MACMIIAR_MR            0x000007C0U  /* MII register in the selected PHY */ 
-#define ETH_MACMIIAR_CR            0x0000001CU  /* CR clock range: 6 cases */ 
-#define ETH_MACMIIAR_CR_Div42      0x00000000U  /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
-#define ETH_MACMIIAR_CR_Div62      0x00000004U  /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
-#define ETH_MACMIIAR_CR_Div16      0x00000008U  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
-#define ETH_MACMIIAR_CR_Div26      0x0000000CU  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
-#define ETH_MACMIIAR_CR_Div102     0x00000010U  /* HCLK:150-168 MHz; MDC clock= HCLK/102 */  
-#define ETH_MACMIIAR_MW            0x00000002U  /* MII write */ 
-#define ETH_MACMIIAR_MB            0x00000001U  /* MII busy */ 
-  
-/* Bit definition for Ethernet MAC MII Data Register */
-#define ETH_MACMIIDR_MD            0x0000FFFFU  /* MII data: read/write data from/to PHY */
-
-/* Bit definition for Ethernet MAC Flow Control Register */
-#define ETH_MACFCR_PT              0xFFFF0000U  /* Pause time */
-#define ETH_MACFCR_ZQPD            0x00000080U  /* Zero-quanta pause disable */
-#define ETH_MACFCR_PLT             0x00000030U  /* Pause low threshold: 4 cases */
-#define ETH_MACFCR_PLT_Minus4      0x00000000U  /* Pause time minus 4 slot times */
-#define ETH_MACFCR_PLT_Minus28     0x00000010U  /* Pause time minus 28 slot times */
-#define ETH_MACFCR_PLT_Minus144    0x00000020U  /* Pause time minus 144 slot times */
-#define ETH_MACFCR_PLT_Minus256    0x00000030U  /* Pause time minus 256 slot times */      
-#define ETH_MACFCR_UPFD            0x00000008U  /* Unicast pause frame detect */
-#define ETH_MACFCR_RFCE            0x00000004U  /* Receive flow control enable */
-#define ETH_MACFCR_TFCE            0x00000002U  /* Transmit flow control enable */
-#define ETH_MACFCR_FCBBPA          0x00000001U  /* Flow control busy/backpressure activate */
-
-/* Bit definition for Ethernet MAC VLAN Tag Register */
-#define ETH_MACVLANTR_VLANTC       0x00010000U  /* 12-bit VLAN tag comparison */
-#define ETH_MACVLANTR_VLANTI       0x0000FFFFU  /* VLAN tag identifier (for receive frames) */
-
-/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ 
-#define ETH_MACRWUFFR_D            0xFFFFFFFFU  /* Wake-up frame filter register data */
-/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
-   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
-/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
-   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
-   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
-   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
-   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - 
-                              RSVD - Filter1 Command - RSVD - Filter0 Command
-   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
-   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
-   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
-
-/* Bit definition for Ethernet MAC PMT Control and Status Register */ 
-#define ETH_MACPMTCSR_WFFRPR       0x80000000U  /* Wake-Up Frame Filter Register Pointer Reset */
-#define ETH_MACPMTCSR_GU           0x00000200U  /* Global Unicast */
-#define ETH_MACPMTCSR_WFR          0x00000040U  /* Wake-Up Frame Received */
-#define ETH_MACPMTCSR_MPR          0x00000020U  /* Magic Packet Received */
-#define ETH_MACPMTCSR_WFE          0x00000004U  /* Wake-Up Frame Enable */
-#define ETH_MACPMTCSR_MPE          0x00000002U  /* Magic Packet Enable */
-#define ETH_MACPMTCSR_PD           0x00000001U  /* Power Down */
-
-/* Bit definition for Ethernet MAC Status Register */
-#define ETH_MACSR_TSTS      0x00000200U  /* Time stamp trigger status */
-#define ETH_MACSR_MMCTS     0x00000040U  /* MMC transmit status */
-#define ETH_MACSR_MMMCRS    0x00000020U  /* MMC receive status */
-#define ETH_MACSR_MMCS      0x00000010U  /* MMC status */
-#define ETH_MACSR_PMTS      0x00000008U  /* PMT status */
-
-/* Bit definition for Ethernet MAC Interrupt Mask Register */
-#define ETH_MACIMR_TSTIM     0x00000200U  /* Time stamp trigger interrupt mask */
-#define ETH_MACIMR_PMTIM     0x00000008U  /* PMT interrupt mask */
-
-/* Bit definition for Ethernet MAC Address0 High Register */
-#define ETH_MACA0HR_MACA0H   0x0000FFFFU  /* MAC address0 high */
-
-/* Bit definition for Ethernet MAC Address0 Low Register */
-#define ETH_MACA0LR_MACA0L   0xFFFFFFFFU  /* MAC address0 low */
-
-/* Bit definition for Ethernet MAC Address1 High Register */
-#define ETH_MACA1HR_AE       0x80000000U  /* Address enable */
-#define ETH_MACA1HR_SA       0x40000000U  /* Source address */
-#define ETH_MACA1HR_MBC      0x3F000000U  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
-  #define ETH_MACA1HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA1HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA1HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA1HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA1HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA1HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [7:0] */ 
-#define ETH_MACA1HR_MACA1H            0x0000FFFFU  /* MAC address1 high */
-
-/* Bit definition for Ethernet MAC Address1 Low Register */
-#define ETH_MACA1LR_MACA1L   0xFFFFFFFFU  /* MAC address1 low */
-
-/* Bit definition for Ethernet MAC Address2 High Register */
-#define ETH_MACA2HR_AE       0x80000000U  /* Address enable */
-#define ETH_MACA2HR_SA       0x40000000U  /* Source address */
-#define ETH_MACA2HR_MBC      0x3F000000U  /* Mask byte control */
-  #define ETH_MACA2HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA2HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA2HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA2HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA2HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA2HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA2HR_MACA2H   0x0000FFFFU  /* MAC address1 high */
-
-/* Bit definition for Ethernet MAC Address2 Low Register */
-#define ETH_MACA2LR_MACA2L   0xFFFFFFFFU  /* MAC address2 low */
-
-/* Bit definition for Ethernet MAC Address3 High Register */
-#define ETH_MACA3HR_AE       0x80000000U  /* Address enable */
-#define ETH_MACA3HR_SA       0x40000000U  /* Source address */
-#define ETH_MACA3HR_MBC      0x3F000000U  /* Mask byte control */
-  #define ETH_MACA3HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA3HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA3HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA3HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA3HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA3HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA3HR_MACA3H   0x0000FFFFU  /* MAC address3 high */
-
-/* Bit definition for Ethernet MAC Address3 Low Register */
-#define ETH_MACA3LR_MACA3L   0xFFFFFFFFU  /* MAC address3 low */
-
-/******************************************************************************/
-/*                Ethernet MMC Registers bits definition                      */
-/******************************************************************************/
-
-/* Bit definition for Ethernet MMC Contol Register */
-#define ETH_MMCCR_MCFHP      0x00000020U  /* MMC counter Full-Half preset */
-#define ETH_MMCCR_MCP        0x00000010U  /* MMC counter preset */
-#define ETH_MMCCR_MCF        0x00000008U  /* MMC Counter Freeze */
-#define ETH_MMCCR_ROR        0x00000004U  /* Reset on Read */
-#define ETH_MMCCR_CSR        0x00000002U  /* Counter Stop Rollover */
-#define ETH_MMCCR_CR         0x00000001U  /* Counters Reset */
-
-/* Bit definition for Ethernet MMC Receive Interrupt Register */
-#define ETH_MMCRIR_RGUFS     0x00020000U  /* Set when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIR_RFAES     0x00000040U  /* Set when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIR_RFCES     0x00000020U  /* Set when Rx crc error counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmit Interrupt Register */
-#define ETH_MMCTIR_TGFS      0x00200000U  /* Set when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFMSCS   0x00008000U  /* Set when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFSCS    0x00004000U  /* Set when Tx good single col counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
-#define ETH_MMCRIMR_RGUFM    0x00020000U  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFAEM    0x00000040U  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFCEM    0x00000020U  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
-#define ETH_MMCTIMR_TGFM     0x00200000U  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFMSCM  0x00008000U  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFSCM   0x00004000U  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
-#define ETH_MMCTGFSCCR_TGFSCC     0xFFFFFFFFU  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
-#define ETH_MMCTGFMSCCR_TGFMSCC   0xFFFFFFFFU  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
-#define ETH_MMCTGFCR_TGFC    0xFFFFFFFFU  /* Number of good frames transmitted. */
-
-/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
-#define ETH_MMCRFCECR_RFCEC  0xFFFFFFFFU  /* Number of frames received with CRC error. */
-
-/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
-#define ETH_MMCRFAECR_RFAEC  0xFFFFFFFFU  /* Number of frames received with alignment (dribble) error */
-
-/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
-#define ETH_MMCRGUFCR_RGUFC  0xFFFFFFFFU  /* Number of good unicast frames received. */
-
-/******************************************************************************/
-/*               Ethernet PTP Registers bits definition                       */
-/******************************************************************************/
-
-/* Bit definition for Ethernet PTP Time Stamp Contol Register */
-#define ETH_PTPTSCR_TSCNT       0x00030000U  /* Time stamp clock node type */
-#define ETH_PTPTSSR_TSSMRME     0x00008000U  /* Time stamp snapshot for message relevant to master enable */
-#define ETH_PTPTSSR_TSSEME      0x00004000U  /* Time stamp snapshot for event message enable */
-#define ETH_PTPTSSR_TSSIPV4FE   0x00002000U  /* Time stamp snapshot for IPv4 frames enable */
-#define ETH_PTPTSSR_TSSIPV6FE   0x00001000U  /* Time stamp snapshot for IPv6 frames enable */
-#define ETH_PTPTSSR_TSSPTPOEFE  0x00000800U  /* Time stamp snapshot for PTP over ethernet frames enable */
-#define ETH_PTPTSSR_TSPTPPSV2E  0x00000400U  /* Time stamp PTP packet snooping for version2 format enable */
-#define ETH_PTPTSSR_TSSSR       0x00000200U  /* Time stamp Sub-seconds rollover */
-#define ETH_PTPTSSR_TSSARFE     0x00000100U  /* Time stamp snapshot for all received frames enable */
-
-#define ETH_PTPTSCR_TSARU       0x00000020U  /* Addend register update */
-#define ETH_PTPTSCR_TSITE       0x00000010U  /* Time stamp interrupt trigger enable */
-#define ETH_PTPTSCR_TSSTU       0x00000008U  /* Time stamp update */
-#define ETH_PTPTSCR_TSSTI       0x00000004U  /* Time stamp initialize */
-#define ETH_PTPTSCR_TSFCU       0x00000002U  /* Time stamp fine or coarse update */
-#define ETH_PTPTSCR_TSE         0x00000001U  /* Time stamp enable */
-
-/* Bit definition for Ethernet PTP Sub-Second Increment Register */
-#define ETH_PTPSSIR_STSSI      0x000000FFU   /* System time Sub-second increment value */
-
-/* Bit definition for Ethernet PTP Time Stamp High Register */
-#define ETH_PTPTSHR_STS        0xFFFFFFFFU   /* System Time second */
-
-/* Bit definition for Ethernet PTP Time Stamp Low Register */
-#define ETH_PTPTSLR_STPNS      0x80000000U  /* System Time Positive or negative time */
-#define ETH_PTPTSLR_STSS       0x7FFFFFFFU  /* System Time sub-seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp High Update Register */
-#define ETH_PTPTSHUR_TSUS      0xFFFFFFFFU  /* Time stamp update seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
-#define ETH_PTPTSLUR_TSUPNS    0x80000000U  /* Time stamp update Positive or negative time */
-#define ETH_PTPTSLUR_TSUSS     0x7FFFFFFFU  /* Time stamp update sub-seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp Addend Register */
-#define ETH_PTPTSAR_TSA        0xFFFFFFFFU  /* Time stamp addend */
-
-/* Bit definition for Ethernet PTP Target Time High Register */
-#define ETH_PTPTTHR_TTSH       0xFFFFFFFFU  /* Target time stamp high */
-
-/* Bit definition for Ethernet PTP Target Time Low Register */
-#define ETH_PTPTTLR_TTSL       0xFFFFFFFFU  /* Target time stamp low */
-
-/* Bit definition for Ethernet PTP Time Stamp Status Register */
-#define ETH_PTPTSSR_TSTTR      0x00000020U  /* Time stamp target time reached */
-#define ETH_PTPTSSR_TSSO       0x00000010U  /* Time stamp seconds overflow */
-
-/******************************************************************************/
-/*                 Ethernet DMA Registers bits definition                     */
-/******************************************************************************/
-
-/* Bit definition for Ethernet DMA Bus Mode Register */
-#define ETH_DMABMR_AAB        0x02000000U  /* Address-Aligned beats */
-#define ETH_DMABMR_FPM        0x01000000U  /* 4xPBL mode */
-#define ETH_DMABMR_USP        0x00800000U  /* Use separate PBL */
-#define ETH_DMABMR_RDP        0x007E0000U  /* RxDMA PBL */
-  #define ETH_DMABMR_RDP_1Beat    0x00020000U  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
-  #define ETH_DMABMR_RDP_2Beat    0x00040000U  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
-  #define ETH_DMABMR_RDP_4Beat    0x00080000U  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-  #define ETH_DMABMR_RDP_8Beat    0x00100000U  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-  #define ETH_DMABMR_RDP_16Beat   0x00200000U  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-  #define ETH_DMABMR_RDP_32Beat   0x00400000U  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */                
-  #define ETH_DMABMR_RDP_4xPBL_4Beat   0x01020000U  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-  #define ETH_DMABMR_RDP_4xPBL_8Beat   0x01040000U  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-  #define ETH_DMABMR_RDP_4xPBL_16Beat  0x01080000U  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-  #define ETH_DMABMR_RDP_4xPBL_32Beat  0x01100000U  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
-  #define ETH_DMABMR_RDP_4xPBL_64Beat  0x01200000U  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
-  #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */  
-#define ETH_DMABMR_FB        0x00010000U  /* Fixed Burst */
-#define ETH_DMABMR_RTPR      0x0000C000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_1_1     0x00000000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_2_1     0x00004000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_3_1     0x00008000U  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_4_1     0x0000C000U  /* Rx Tx priority ratio */  
-#define ETH_DMABMR_PBL    0x00003F00U  /* Programmable burst length */
-  #define ETH_DMABMR_PBL_1Beat    0x00000100U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
-  #define ETH_DMABMR_PBL_2Beat    0x00000200U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
-  #define ETH_DMABMR_PBL_4Beat    0x00000400U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-  #define ETH_DMABMR_PBL_8Beat    0x00000800U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-  #define ETH_DMABMR_PBL_16Beat   0x00001000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-  #define ETH_DMABMR_PBL_32Beat   0x00002000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
-  #define ETH_DMABMR_PBL_4xPBL_4Beat   0x01000100U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-  #define ETH_DMABMR_PBL_4xPBL_8Beat   0x01000200U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-  #define ETH_DMABMR_PBL_4xPBL_16Beat  0x01000400U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-  #define ETH_DMABMR_PBL_4xPBL_32Beat  0x01000800U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
-  #define ETH_DMABMR_PBL_4xPBL_64Beat  0x01001000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
-  #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
-#define ETH_DMABMR_EDE       0x00000080U  /* Enhanced Descriptor Enable */
-#define ETH_DMABMR_DSL       0x0000007CU  /* Descriptor Skip Length */
-#define ETH_DMABMR_DA        0x00000002U  /* DMA arbitration scheme */
-#define ETH_DMABMR_SR        0x00000001U  /* Software reset */
-
-/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
-#define ETH_DMATPDR_TPD      0xFFFFFFFFU  /* Transmit poll demand */
-
-/* Bit definition for Ethernet DMA Receive Poll Demand Register */
-#define ETH_DMARPDR_RPD      0xFFFFFFFFU  /* Receive poll demand  */
-
-/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
-#define ETH_DMARDLAR_SRL     0xFFFFFFFFU  /* Start of receive list */
-
-/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
-#define ETH_DMATDLAR_STL     0xFFFFFFFFU  /* Start of transmit list */
-
-/* Bit definition for Ethernet DMA Status Register */
-#define ETH_DMASR_TSTS       0x20000000U  /* Time-stamp trigger status */
-#define ETH_DMASR_PMTS       0x10000000U  /* PMT status */
-#define ETH_DMASR_MMCS       0x08000000U  /* MMC status */
-#define ETH_DMASR_EBS        0x03800000U  /* Error bits status */
-  /* combination with EBS[2:0] for GetFlagStatus function */
-  #define ETH_DMASR_EBS_DescAccess      0x02000000U  /* Error bits 0-data buffer, 1-desc. access */
-  #define ETH_DMASR_EBS_ReadTransf      0x01000000U  /* Error bits 0-write trnsf, 1-read transfr */
-  #define ETH_DMASR_EBS_DataTransfTx    0x00800000U  /* Error bits 0-Rx DMA, 1-Tx DMA */
-#define ETH_DMASR_TPS         0x00700000U  /* Transmit process state */
-  #define ETH_DMASR_TPS_Stopped         0x00000000U  /* Stopped - Reset or Stop Tx Command issued  */
-  #define ETH_DMASR_TPS_Fetching        0x00100000U  /* Running - fetching the Tx descriptor */
-  #define ETH_DMASR_TPS_Waiting         0x00200000U  /* Running - waiting for status */
-  #define ETH_DMASR_TPS_Reading         0x00300000U  /* Running - reading the data from host memory */
-  #define ETH_DMASR_TPS_Suspended       0x00600000U  /* Suspended - Tx Descriptor unavailabe */
-  #define ETH_DMASR_TPS_Closing         0x00700000U  /* Running - closing Rx descriptor */
-#define ETH_DMASR_RPS         0x000E0000U  /* Receive process state */
-  #define ETH_DMASR_RPS_Stopped         0x00000000U  /* Stopped - Reset or Stop Rx Command issued */
-  #define ETH_DMASR_RPS_Fetching        0x00020000U  /* Running - fetching the Rx descriptor */
-  #define ETH_DMASR_RPS_Waiting         0x00060000U  /* Running - waiting for packet */
-  #define ETH_DMASR_RPS_Suspended       0x00080000U  /* Suspended - Rx Descriptor unavailable */
-  #define ETH_DMASR_RPS_Closing         0x000A0000U  /* Running - closing descriptor */
-  #define ETH_DMASR_RPS_Queuing         0x000E0000U  /* Running - queuing the recieve frame into host memory */
-#define ETH_DMASR_NIS        0x00010000U  /* Normal interrupt summary */
-#define ETH_DMASR_AIS        0x00008000U  /* Abnormal interrupt summary */
-#define ETH_DMASR_ERS        0x00004000U  /* Early receive status */
-#define ETH_DMASR_FBES       0x00002000U  /* Fatal bus error status */
-#define ETH_DMASR_ETS        0x00000400U  /* Early transmit status */
-#define ETH_DMASR_RWTS       0x00000200U  /* Receive watchdog timeout status */
-#define ETH_DMASR_RPSS       0x00000100U  /* Receive process stopped status */
-#define ETH_DMASR_RBUS       0x00000080U  /* Receive buffer unavailable status */
-#define ETH_DMASR_RS         0x00000040U  /* Receive status */
-#define ETH_DMASR_TUS        0x00000020U  /* Transmit underflow status */
-#define ETH_DMASR_ROS        0x00000010U  /* Receive overflow status */
-#define ETH_DMASR_TJTS       0x00000008U  /* Transmit jabber timeout status */
-#define ETH_DMASR_TBUS       0x00000004U  /* Transmit buffer unavailable status */
-#define ETH_DMASR_TPSS       0x00000002U  /* Transmit process stopped status */
-#define ETH_DMASR_TS         0x00000001U  /* Transmit status */
-
-/* Bit definition for Ethernet DMA Operation Mode Register */
-#define ETH_DMAOMR_DTCEFD    0x04000000U  /* Disable Dropping of TCP/IP checksum error frames */
-#define ETH_DMAOMR_RSF       0x02000000U  /* Receive store and forward */
-#define ETH_DMAOMR_DFRF      0x01000000U  /* Disable flushing of received frames */
-#define ETH_DMAOMR_TSF       0x00200000U  /* Transmit store and forward */
-#define ETH_DMAOMR_FTF       0x00100000U  /* Flush transmit FIFO */
-#define ETH_DMAOMR_TTC       0x0001C000U  /* Transmit threshold control */
-  #define ETH_DMAOMR_TTC_64Bytes       0x00000000U  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
-  #define ETH_DMAOMR_TTC_128Bytes      0x00004000U  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
-  #define ETH_DMAOMR_TTC_192Bytes      0x00008000U  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
-  #define ETH_DMAOMR_TTC_256Bytes      0x0000C000U  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
-  #define ETH_DMAOMR_TTC_40Bytes       0x00010000U  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
-  #define ETH_DMAOMR_TTC_32Bytes       0x00014000U  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
-  #define ETH_DMAOMR_TTC_24Bytes       0x00018000U  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
-  #define ETH_DMAOMR_TTC_16Bytes       0x0001C000U  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
-#define ETH_DMAOMR_ST        0x00002000U  /* Start/stop transmission command */
-#define ETH_DMAOMR_FEF       0x00000080U  /* Forward error frames */
-#define ETH_DMAOMR_FUGF      0x00000040U  /* Forward undersized good frames */
-#define ETH_DMAOMR_RTC       0x00000018U  /* receive threshold control */
-  #define ETH_DMAOMR_RTC_64Bytes       0x00000000U  /* threshold level of the MTL Receive FIFO is 64 Bytes */
-  #define ETH_DMAOMR_RTC_32Bytes       0x00000008U  /* threshold level of the MTL Receive FIFO is 32 Bytes */
-  #define ETH_DMAOMR_RTC_96Bytes       0x00000010U  /* threshold level of the MTL Receive FIFO is 96 Bytes */
-  #define ETH_DMAOMR_RTC_128Bytes      0x00000018U  /* threshold level of the MTL Receive FIFO is 128 Bytes */
-#define ETH_DMAOMR_OSF       0x00000004U  /* operate on second frame */
-#define ETH_DMAOMR_SR        0x00000002U  /* Start/stop receive */
-
-/* Bit definition for Ethernet DMA Interrupt Enable Register */
-#define ETH_DMAIER_NISE      0x00010000U  /* Normal interrupt summary enable */
-#define ETH_DMAIER_AISE      0x00008000U  /* Abnormal interrupt summary enable */
-#define ETH_DMAIER_ERIE      0x00004000U  /* Early receive interrupt enable */
-#define ETH_DMAIER_FBEIE     0x00002000U  /* Fatal bus error interrupt enable */
-#define ETH_DMAIER_ETIE      0x00000400U  /* Early transmit interrupt enable */
-#define ETH_DMAIER_RWTIE     0x00000200U  /* Receive watchdog timeout interrupt enable */
-#define ETH_DMAIER_RPSIE     0x00000100U  /* Receive process stopped interrupt enable */
-#define ETH_DMAIER_RBUIE     0x00000080U  /* Receive buffer unavailable interrupt enable */
-#define ETH_DMAIER_RIE       0x00000040U  /* Receive interrupt enable */
-#define ETH_DMAIER_TUIE      0x00000020U  /* Transmit Underflow interrupt enable */
-#define ETH_DMAIER_ROIE      0x00000010U  /* Receive Overflow interrupt enable */
-#define ETH_DMAIER_TJTIE     0x00000008U  /* Transmit jabber timeout interrupt enable */
-#define ETH_DMAIER_TBUIE     0x00000004U  /* Transmit buffer unavailable interrupt enable */
-#define ETH_DMAIER_TPSIE     0x00000002U  /* Transmit process stopped interrupt enable */
-#define ETH_DMAIER_TIE       0x00000001U  /* Transmit interrupt enable */
-
-/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
-#define ETH_DMAMFBOCR_OFOC   0x10000000U  /* Overflow bit for FIFO overflow counter */
-#define ETH_DMAMFBOCR_MFA    0x0FFE0000U  /* Number of frames missed by the application */
-#define ETH_DMAMFBOCR_OMFC   0x00010000U  /* Overflow bit for missed frame counter */
-#define ETH_DMAMFBOCR_MFC    0x0000FFFFU  /* Number of frames missed by the controller */
-
-/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
-#define ETH_DMACHTDR_HTDAP   0xFFFFFFFFU  /* Host transmit descriptor address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
-#define ETH_DMACHRDR_HRDAP   0xFFFFFFFFU  /* Host receive descriptor address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
-#define ETH_DMACHTBAR_HTBAP  0xFFFFFFFFU  /* Host transmit buffer address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
-#define ETH_DMACHRBAR_HRBAP  0xFFFFFFFFU  /* Host receive buffer address pointer */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                       USB_OTG                              */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for USB_OTG_GOTGCTL register  ********************/
-#define USB_OTG_GOTGCTL_SRQSCS                  0x00000001U         /*!< Session request success */
-#define USB_OTG_GOTGCTL_SRQ                     0x00000002U         /*!< Session request */
-#define USB_OTG_GOTGCTL_VBVALOEN                0x00000004U         /*!< VBUS valid override enable */
-#define USB_OTG_GOTGCTL_VBVALOVAL               0x00000008U         /*!< VBUS valid override value */
-#define USB_OTG_GOTGCTL_AVALOEN                 0x00000010U         /*!< A-peripheral session valid override enable */
-#define USB_OTG_GOTGCTL_AVALOVAL                0x00000020U         /*!< A-peripheral session valid override value */
-#define USB_OTG_GOTGCTL_BVALOEN                 0x00000040U         /*!< B-peripheral session valid override enable */
-#define USB_OTG_GOTGCTL_BVALOVAL                0x00000080U         /*!< B-peripheral session valid override value  */
-#define USB_OTG_GOTGCTL_HNGSCS                  0x00000100U         /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_HNPRQ                   0x00000200U         /*!< HNP request */
-#define USB_OTG_GOTGCTL_HSHNPEN                 0x00000400U         /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_DHNPEN                  0x00000800U         /*!< Device HNP enabled */
-#define USB_OTG_GOTGCTL_EHEN                    0x00001000U         /*!< Embedded host enable */
-#define USB_OTG_GOTGCTL_CIDSTS                  0x00010000U         /*!< Connector ID status */
-#define USB_OTG_GOTGCTL_DBCT                    0x00020000U         /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD                   0x00040000U         /*!< A-session valid  */
-#define USB_OTG_GOTGCTL_BSESVLD                 0x00080000U         /*!< B-session valid */
-#define USB_OTG_GOTGCTL_OTGVER                  0x00100000U         /*!< OTG version  */
-
-/********************  Bit definition for USB_OTG_HCFG register  ********************/
-#define USB_OTG_HCFG_FSLSPCS                 0x00000003U            /*!< FS/LS PHY clock select  */
-#define USB_OTG_HCFG_FSLSPCS_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCFG_FSLSPCS_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCFG_FSLSS                   0x00000004U            /*!< FS- and LS-only support */
-
-/********************  Bit definition for USB_OTG_DCFG register  ********************/
-#define USB_OTG_DCFG_DSPD                    0x00000003U            /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                  0x00000001U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DSPD_1                  0x00000002U            /*!<Bit 1 */
-#define USB_OTG_DCFG_NZLSOHSK                0x00000004U            /*!< Nonzero-length status OUT handshake */
-
-#define USB_OTG_DCFG_DAD                     0x000007F0U            /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                   0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCFG_DAD_1                   0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCFG_DAD_2                   0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCFG_DAD_3                   0x00000080U            /*!<Bit 3 */
-#define USB_OTG_DCFG_DAD_4                   0x00000100U            /*!<Bit 4 */
-#define USB_OTG_DCFG_DAD_5                   0x00000200U            /*!<Bit 5 */
-#define USB_OTG_DCFG_DAD_6                   0x00000400U            /*!<Bit 6 */
-
-#define USB_OTG_DCFG_PFIVL                   0x00001800U            /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PFIVL_1                 0x00001000U            /*!<Bit 1 */
-
-#define USB_OTG_DCFG_PERSCHIVL               0x03000000U            /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0             0x01000000U            /*!<Bit 0 */
-#define USB_OTG_DCFG_PERSCHIVL_1             0x02000000U            /*!<Bit 1 */
-
-/********************  Bit definition for USB_OTG_PCGCR register  ********************/
-#define USB_OTG_PCGCR_STPPCLK                 0x00000001U            /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK                0x00000002U            /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP                 0x00000010U            /*!< PHY suspended */
-
-/********************  Bit definition for USB_OTG_GOTGINT register  ********************/
-#define USB_OTG_GOTGINT_SEDET                   0x00000004U            /*!< Session end detected                   */
-#define USB_OTG_GOTGINT_SRSSCHG                 0x00000100U            /*!< Session request success status change  */
-#define USB_OTG_GOTGINT_HNSSCHG                 0x00000200U            /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET                  0x00020000U            /*!< Host negotiation detected              */
-#define USB_OTG_GOTGINT_ADTOCHG                 0x00040000U            /*!< A-device timeout change                */
-#define USB_OTG_GOTGINT_DBCDNE                  0x00080000U            /*!< Debounce done                          */
-#define USB_OTG_GOTGINT_IDCHNG                  0x00100000U            /*!< Change in ID pin input value           */
-
-/********************  Bit definition for USB_OTG_DCTL register  ********************/
-#define USB_OTG_DCTL_RWUSIG                  0x00000001U            /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS                    0x00000002U            /*!< Soft disconnect         */
-#define USB_OTG_DCTL_GINSTS                  0x00000004U            /*!< Global IN NAK status    */
-#define USB_OTG_DCTL_GONSTS                  0x00000008U            /*!< Global OUT NAK status   */
-
-#define USB_OTG_DCTL_TCTL                    0x00000070U            /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                  0x00000010U            /*!<Bit 0 */
-#define USB_OTG_DCTL_TCTL_1                  0x00000020U            /*!<Bit 1 */
-#define USB_OTG_DCTL_TCTL_2                  0x00000040U            /*!<Bit 2 */
-#define USB_OTG_DCTL_SGINAK                  0x00000080U            /*!< Set global IN NAK         */
-#define USB_OTG_DCTL_CGINAK                  0x00000100U            /*!< Clear global IN NAK       */
-#define USB_OTG_DCTL_SGONAK                  0x00000200U            /*!< Set global OUT NAK        */
-#define USB_OTG_DCTL_CGONAK                  0x00000400U            /*!< Clear global OUT NAK      */
-#define USB_OTG_DCTL_POPRGDNE                0x00000800U            /*!< Power-on programming done */
-
-/********************  Bit definition for USB_OTG_HFIR register  ********************/
-#define USB_OTG_HFIR_FRIVL                   0x0000FFFFU            /*!< Frame interval */
-
-/********************  Bit definition for USB_OTG_HFNUM register  ********************/
-#define USB_OTG_HFNUM_FRNUM                   0x0000FFFFU            /*!< Frame number         */
-#define USB_OTG_HFNUM_FTREM                   0xFFFF0000U            /*!< Frame time remaining */
-
-/********************  Bit definition for USB_OTG_DSTS register  ********************/
-#define USB_OTG_DSTS_SUSPSTS                 0x00000001U            /*!< Suspend status   */
-
-#define USB_OTG_DSTS_ENUMSPD                 0x00000006U            /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_DSTS_ENUMSPD_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_DSTS_EERR                    0x00000008U            /*!< Erratic error     */
-#define USB_OTG_DSTS_FNSOF                   0x003FFF00U            /*!< Frame number of the received SOF */
-
-/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
-#define USB_OTG_GAHBCFG_GINT                    0x00000001U            /*!< Global interrupt mask */
-#define USB_OTG_GAHBCFG_HBSTLEN                 0x0000001EU            /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0               0x00000002U            /*!<Bit 0 */
-#define USB_OTG_GAHBCFG_HBSTLEN_1               0x00000004U            /*!<Bit 1 */
-#define USB_OTG_GAHBCFG_HBSTLEN_2               0x00000008U            /*!<Bit 2 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3               0x00000010U            /*!<Bit 3 */
-#define USB_OTG_GAHBCFG_DMAEN                   0x00000020U            /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL                 0x00000080U            /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL                0x00000100U            /*!< Periodic TxFIFO empty level */
-
-/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
-#define USB_OTG_GUSBCFG_TOCAL                   0x00000007U            /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TOCAL_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TOCAL_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_PHYSEL                  0x00000040U            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP                  0x00000100U            /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP                  0x00000200U            /*!< HNP-capable */
-#define USB_OTG_GUSBCFG_TRDT                    0x00003C00U            /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                  0x00000400U            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TRDT_1                  0x00000800U            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TRDT_2                  0x00001000U            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_TRDT_3                  0x00002000U            /*!<Bit 3 */
-#define USB_OTG_GUSBCFG_PHYLPCS                 0x00008000U            /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS                0x00020000U            /*!< ULPI FS/LS select               */
-#define USB_OTG_GUSBCFG_ULPIAR                  0x00040000U            /*!< ULPI Auto-resume                */
-#define USB_OTG_GUSBCFG_ULPICSM                 0x00080000U            /*!< ULPI Clock SuspendM             */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD              0x00100000U            /*!< ULPI External VBUS Drive        */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI              0x00200000U            /*!< ULPI external VBUS indicator    */
-#define USB_OTG_GUSBCFG_TSDPS                   0x00400000U            /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI                    0x00800000U            /*!< Indicator complement            */
-#define USB_OTG_GUSBCFG_PTCI                    0x01000000U            /*!< Indicator pass through          */
-#define USB_OTG_GUSBCFG_ULPIIPD                 0x02000000U            /*!< ULPI interface protect disable  */
-#define USB_OTG_GUSBCFG_FHMOD                   0x20000000U            /*!< Forced host mode                */
-#define USB_OTG_GUSBCFG_FDMOD                   0x40000000U            /*!< Forced peripheral mode          */
-#define USB_OTG_GUSBCFG_CTXPKT                  0x80000000U            /*!< Corrupt Tx packet               */
-
-/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
-#define USB_OTG_GRSTCTL_CSRST                   0x00000001U            /*!< Core soft reset          */
-#define USB_OTG_GRSTCTL_HSRST                   0x00000002U            /*!< HCLK soft reset          */
-#define USB_OTG_GRSTCTL_FCRST                   0x00000004U            /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH                 0x00000010U            /*!< RxFIFO flush             */
-#define USB_OTG_GRSTCTL_TXFFLSH                 0x00000020U            /*!< TxFIFO flush             */
-#define USB_OTG_GRSTCTL_TXFNUM                  0x000007C0U            /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                0x00000040U            /*!<Bit 0 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                0x00000080U            /*!<Bit 1 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                0x00000100U            /*!<Bit 2 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                0x00000200U            /*!<Bit 3 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                0x00000400U            /*!<Bit 4 */
-#define USB_OTG_GRSTCTL_DMAREQ                  0x40000000U            /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL                  0x80000000U            /*!< AHB master idle */
-
-/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
-#define USB_OTG_DIEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask                 */
-#define USB_OTG_DIEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask                  */
-#define USB_OTG_DIEPMSK_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask          */
-#define USB_OTG_DIEPMSK_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask           */
-#define USB_OTG_DIEPMSK_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask                    */
-#define USB_OTG_DIEPMSK_TXFURM                  0x00000100U            /*!< FIFO underrun mask                                */
-#define USB_OTG_DIEPMSK_BIM                     0x00000200U            /*!< BNA interrupt mask                                */
-
-/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
-#define USB_OTG_HPTXSTS_PTXFSAVL                0x0000FFFFU            /*!< Periodic transmit data FIFO space available     */
-#define USB_OTG_HPTXSTS_PTXQSAV                 0x00FF0000U            /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0               0x00010000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1               0x00020000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2               0x00040000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3               0x00080000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4               0x00100000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5               0x00200000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6               0x00400000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7               0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_HPTXSTS_PTXQTOP                 0xFF000000U            /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0               0x01000000U            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1               0x02000000U            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2               0x04000000U            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3               0x08000000U            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4               0x10000000U            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5               0x20000000U            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6               0x40000000U            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7               0x80000000U            /*!<Bit 7 */
-
-/********************  Bit definition for USB_OTG_HAINT register  ********************/
-#define USB_OTG_HAINT_HAINT                     0x0000FFFFU            /*!< Channel interrupts */
-
-/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
-#define USB_OTG_DOEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask               */
-#define USB_OTG_DOEPMSK_STUPM                   0x00000008U            /*!< SETUP phase done mask                          */
-#define USB_OTG_DOEPMSK_OTEPDM                  0x00000010U            /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_OTEPSPRM                0x00000020U            /*!< Status Phase Received mask                     */
-#define USB_OTG_DOEPMSK_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received mask       */
-#define USB_OTG_DOEPMSK_OPEM                    0x00000100U            /*!< OUT packet error mask                          */
-#define USB_OTG_DOEPMSK_BOIM                    0x00000200U            /*!< BNA interrupt mask                             */
-
-/********************  Bit definition for USB_OTG_GINTSTS register  ********************/
-#define USB_OTG_GINTSTS_CMOD                    0x00000001U            /*!< Current mode of operation                      */
-#define USB_OTG_GINTSTS_MMIS                    0x00000002U            /*!< Mode mismatch interrupt                        */
-#define USB_OTG_GINTSTS_OTGINT                  0x00000004U            /*!< OTG interrupt                                  */
-#define USB_OTG_GINTSTS_SOF                     0x00000008U            /*!< Start of frame                                 */
-#define USB_OTG_GINTSTS_RXFLVL                  0x00000010U            /*!< RxFIFO nonempty                                */
-#define USB_OTG_GINTSTS_NPTXFE                  0x00000020U            /*!< Nonperiodic TxFIFO empty                       */
-#define USB_OTG_GINTSTS_GINAKEFF                0x00000040U            /*!< Global IN nonperiodic NAK effective            */
-#define USB_OTG_GINTSTS_BOUTNAKEFF              0x00000080U            /*!< Global OUT NAK effective                       */
-#define USB_OTG_GINTSTS_ESUSP                   0x00000400U            /*!< Early suspend                                  */
-#define USB_OTG_GINTSTS_USBSUSP                 0x00000800U            /*!< USB suspend                                    */
-#define USB_OTG_GINTSTS_USBRST                  0x00001000U            /*!< USB reset                                      */
-#define USB_OTG_GINTSTS_ENUMDNE                 0x00002000U            /*!< Enumeration done                               */
-#define USB_OTG_GINTSTS_ISOODRP                 0x00004000U            /*!< Isochronous OUT packet dropped interrupt       */
-#define USB_OTG_GINTSTS_EOPF                    0x00008000U            /*!< End of periodic frame interrupt                */
-#define USB_OTG_GINTSTS_IEPINT                  0x00040000U            /*!< IN endpoint interrupt                          */
-#define USB_OTG_GINTSTS_OEPINT                  0x00080000U            /*!< OUT endpoint interrupt                         */
-#define USB_OTG_GINTSTS_IISOIXFR                0x00100000U            /*!< Incomplete isochronous IN transfer             */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       0x00200000U            /*!< Incomplete periodic transfer                   */
-#define USB_OTG_GINTSTS_DATAFSUSP               0x00400000U            /*!< Data fetch suspended                           */
-#define USB_OTG_GINTSTS_RSTDET                  0x00800000U            /*!< Reset detected interrupt                       */
-#define USB_OTG_GINTSTS_HPRTINT                 0x01000000U            /*!< Host port interrupt                            */
-#define USB_OTG_GINTSTS_HCINT                   0x02000000U            /*!< Host channels interrupt                        */
-#define USB_OTG_GINTSTS_PTXFE                   0x04000000U            /*!< Periodic TxFIFO empty                          */
-#define USB_OTG_GINTSTS_LPMINT                  0x08000000U            /*!< LPM interrupt                                  */
-#define USB_OTG_GINTSTS_CIDSCHG                 0x10000000U            /*!< Connector ID status change                     */
-#define USB_OTG_GINTSTS_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt                  */
-#define USB_OTG_GINTSTS_SRQINT                  0x40000000U            /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT                  0x80000000U            /*!< Resume/remote wakeup detected interrupt        */
-
-/********************  Bit definition for USB_OTG_GINTMSK register  ********************/
-#define USB_OTG_GINTMSK_MMISM                   0x00000002U            /*!< Mode mismatch interrupt mask                        */
-#define USB_OTG_GINTMSK_OTGINT                  0x00000004U            /*!< OTG interrupt mask                                  */
-#define USB_OTG_GINTMSK_SOFM                    0x00000008U            /*!< Start of frame mask                                 */
-#define USB_OTG_GINTMSK_RXFLVLM                 0x00000010U            /*!< Receive FIFO nonempty mask                          */
-#define USB_OTG_GINTMSK_NPTXFEM                 0x00000020U            /*!< Nonperiodic TxFIFO empty mask                       */
-#define USB_OTG_GINTMSK_GINAKEFFM               0x00000040U            /*!< Global nonperiodic IN NAK effective mask            */
-#define USB_OTG_GINTMSK_GONAKEFFM               0x00000080U            /*!< Global OUT NAK effective mask                       */
-#define USB_OTG_GINTMSK_ESUSPM                  0x00000400U            /*!< Early suspend mask                                  */
-#define USB_OTG_GINTMSK_USBSUSPM                0x00000800U            /*!< USB suspend mask                                    */
-#define USB_OTG_GINTMSK_USBRST                  0x00001000U            /*!< USB reset mask                                      */
-#define USB_OTG_GINTMSK_ENUMDNEM                0x00002000U            /*!< Enumeration done mask                               */
-#define USB_OTG_GINTMSK_ISOODRPM                0x00004000U            /*!< Isochronous OUT packet dropped interrupt mask       */
-#define USB_OTG_GINTMSK_EOPFM                   0x00008000U            /*!< End of periodic frame interrupt mask                */
-#define USB_OTG_GINTMSK_EPMISM                  0x00020000U            /*!< Endpoint mismatch interrupt mask                    */
-#define USB_OTG_GINTMSK_IEPINT                  0x00040000U            /*!< IN endpoints interrupt mask                         */
-#define USB_OTG_GINTMSK_OEPINT                  0x00080000U            /*!< OUT endpoints interrupt mask                        */
-#define USB_OTG_GINTMSK_IISOIXFRM               0x00100000U            /*!< Incomplete isochronous IN transfer mask             */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         0x00200000U            /*!< Incomplete periodic transfer mask                   */
-#define USB_OTG_GINTMSK_FSUSPM                  0x00400000U            /*!< Data fetch suspended mask                           */
-#define USB_OTG_GINTMSK_RSTDEM                  0x00800000U            /*!< Reset detected interrupt mask                       */
-#define USB_OTG_GINTMSK_PRTIM                   0x01000000U            /*!< Host port interrupt mask                            */
-#define USB_OTG_GINTMSK_HCIM                    0x02000000U            /*!< Host channels interrupt mask                        */
-#define USB_OTG_GINTMSK_PTXFEM                  0x04000000U            /*!< Periodic TxFIFO empty mask                          */
-#define USB_OTG_GINTMSK_LPMINTM                 0x08000000U            /*!< LPM interrupt Mask                                  */
-#define USB_OTG_GINTMSK_CIDSCHGM                0x10000000U            /*!< Connector ID status change mask                     */
-#define USB_OTG_GINTMSK_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt mask                  */
-#define USB_OTG_GINTMSK_SRQIM                   0x40000000U            /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM                    0x80000000U            /*!< Resume/remote wakeup detected interrupt mask        */
-
-/********************  Bit definition for USB_OTG_DAINT register  ********************/
-#define USB_OTG_DAINT_IEPINT                  0x0000FFFFU            /*!< IN endpoint interrupt bits  */
-#define USB_OTG_DAINT_OEPINT                  0xFFFF0000U            /*!< OUT endpoint interrupt bits */
-
-/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
-#define USB_OTG_HAINTMSK_HAINTM                  0x0000FFFFU            /*!< Channel interrupt mask */
-
-/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
-#define USB_OTG_GRXSTSP_EPNUM                    0x0000000FU            /*!< IN EP interrupt mask bits  */
-#define USB_OTG_GRXSTSP_BCNT                     0x00007FF0U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID                     0x00018000U            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS                   0x001E0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
-#define USB_OTG_DAINTMSK_IEPM                    0x0000FFFFU            /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM                    0xFFFF0000U            /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for OTG register  ********************/
-
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition for OTG register  ********************/
-
-#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
-#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
-
-#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
-#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
-
-#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
-
-/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
-#define USB_OTG_GRXFSIZ_RXFD            0x0000FFFFU            /*!< RxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
-#define USB_OTG_DVBUSDIS_VBUSDT         0x0000FFFFU            /*!< Device VBUS discharge time */
-
-/********************  Bit definition for OTG register  ********************/
-#define USB_OTG_NPTXFSA                 0x0000FFFFU            /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD                  0xFFFF0000U            /*!< Nonperiodic TxFIFO depth               */
-#define USB_OTG_TX0FSA                  0x0000FFFFU            /*!< Endpoint 0 transmit RAM start address  */
-#define USB_OTG_TX0FD                   0xFFFF0000U            /*!< Endpoint 0 TxFIFO depth                */
-
-/********************  Bit definition for USB_OTG_DVBUSPULSE register  ********************/
-#define USB_OTG_DVBUSPULSE_DVBUSP                0x00000FFFU            /*!< Device VBUS pulsing time */
-
-/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
-#define USB_OTG_GNPTXSTS_NPTXFSAV                0x0000FFFFU            /*!< Nonperiodic TxFIFO space available */
-
-#define USB_OTG_GNPTXSTS_NPTQXSAV                0x00FF0000U            /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0              0x00010000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1              0x00020000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2              0x00040000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3              0x00080000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4              0x00100000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5              0x00200000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6              0x00400000U            /*!<Bit 6 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7              0x00800000U            /*!<Bit 7 */
-
-#define USB_OTG_GNPTXSTS_NPTXQTOP                0x7F000000U            /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0              0x01000000U            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1              0x02000000U            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2              0x04000000U            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3              0x08000000U            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4              0x10000000U            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5              0x20000000U            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6              0x40000000U            /*!<Bit 6 */
-
-/********************  Bit definition for USB_OTG_DTHRCTL register  ********************/
-#define USB_OTG_DTHRCTL_NONISOTHREN             0x00000001U            /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN                0x00000002U            /*!< ISO IN endpoint threshold enable */
-
-#define USB_OTG_DTHRCTL_TXTHRLEN                0x000007FCU            /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0              0x00000004U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1              0x00000008U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2              0x00000010U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3              0x00000020U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4              0x00000040U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5              0x00000080U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6              0x00000100U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7              0x00000200U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8              0x00000400U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_RXTHREN                 0x00010000U            /*!< Receive threshold enable */
-
-#define USB_OTG_DTHRCTL_RXTHRLEN                0x03FE0000U            /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0              0x00020000U            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1              0x00040000U            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2              0x00080000U            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3              0x00100000U            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4              0x00200000U            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5              0x00400000U            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6              0x00800000U            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7              0x01000000U            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8              0x02000000U            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_ARPEN                   0x08000000U            /*!< Arbiter parking enable */
-
-/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM            0x0000FFFFU         /*!< IN EP Tx FIFO empty interrupt mask bits */
-
-/********************  Bit definition for USB_OTG_DEACHINT register  ********************/
-#define USB_OTG_DEACHINT_IEP1INT                0x00000002U           /*!< IN endpoint 1interrupt bit   */
-#define USB_OTG_DEACHINT_OEP1INT                0x00020000U           /*!< OUT endpoint 1 interrupt bit */
-
-/********************  Bit definition for USB_OTG_GCCFG register  ********************/
-#define USB_OTG_GCCFG_PWRDWN                 0x00010000U              /*!< Power down */
-#define USB_OTG_GCCFG_VBDEN                  0x00200000U              /*!< USB VBUS Detection Enable */
-
-/********************  Bit definition for USB_OTG_GPWRDN) register  ********************/
-#define USB_OTG_GPWRDN_ADPMEN                 0x00000001U             /*!< ADP module enable */
-#define USB_OTG_GPWRDN_ADPIF                  0x00800000U             /*!< ADP Interrupt flag */
-
-/********************  Bit definition for USB_OTG_DEACHINTMSK register  ********************/
-#define USB_OTG_DEACHINTMSK_IEP1INTM          0x00000002U            /*!< IN Endpoint 1 interrupt mask bit  */
-#define USB_OTG_DEACHINTMSK_OEP1INTM          0x00020000U            /*!< OUT Endpoint 1 interrupt mask bit */
- 
-/********************  Bit definition for USB_OTG_CID register  ********************/
-#define USB_OTG_CID_PRODUCT_ID               0xFFFFFFFFU            /*!< Product ID field */
-
-/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/
-#define  USB_OTG_GLPMCFG_LPMEN               0x00000001U            /*!< LPM support enable                                     */
-#define  USB_OTG_GLPMCFG_LPMACK              0x00000002U            /*!< LPM Token acknowledge enable                           */
-#define  USB_OTG_GLPMCFG_BESL                0x0000003CU            /*!< BESL value received with last ACKed LPM Token          */
-#define  USB_OTG_GLPMCFG_REMWAKE             0x00000040U            /*!< bRemoteWake value received with last ACKed LPM Token   */
-#define  USB_OTG_GLPMCFG_L1SSEN              0x00000080U            /*!< L1 shallow sleep enable                                */
-#define  USB_OTG_GLPMCFG_BESLTHRS            0x00000F00U            /*!< BESL threshold                                         */
-#define  USB_OTG_GLPMCFG_L1DSEN              0x00001000U            /*!< L1 deep sleep enable                                   */
-#define  USB_OTG_GLPMCFG_LPMRSP              0x00006000U            /*!< LPM response                                           */
-#define  USB_OTG_GLPMCFG_SLPSTS              0x00008000U            /*!< Port sleep status                                      */
-#define  USB_OTG_GLPMCFG_L1RSMOK             0x00010000U            /*!< Sleep State Resume OK                                  */
-#define  USB_OTG_GLPMCFG_LPMCHIDX            0x001E0000U            /*!< LPM Channel Index                                      */
-#define  USB_OTG_GLPMCFG_LPMRCNT             0x00E00000U            /*!< LPM retry count                                        */
-#define  USB_OTG_GLPMCFG_SNDLPM              0x01000000U            /*!< Send LPM transaction                                   */
-#define  USB_OTG_GLPMCFG_LPMRCNTSTS          0x0E000000U            /*!< LPM retry count status                                 */
-#define  USB_OTG_GLPMCFG_ENBESL              0x10000000U            /*!< Enable best effort service latency                     */
-
-/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
-#define USB_OTG_DIEPEACHMSK1_XFRCM           0x00000001U            /*!< Transfer completed interrupt mask                 */
-#define USB_OTG_DIEPEACHMSK1_EPDM            0x00000002U            /*!< Endpoint disabled interrupt mask                  */
-#define USB_OTG_DIEPEACHMSK1_TOM             0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK       0x00000010U            /*!< IN token received when TxFIFO empty mask          */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM         0x00000020U            /*!< IN token received with EP mismatch mask           */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM         0x00000040U            /*!< IN endpoint NAK effective mask                    */
-#define USB_OTG_DIEPEACHMSK1_TXFURM          0x00000100U            /*!< FIFO underrun mask                                */
-#define USB_OTG_DIEPEACHMSK1_BIM             0x00000200U            /*!< BNA interrupt mask                                */
-#define USB_OTG_DIEPEACHMSK1_NAKM            0x00002000U            /*!< NAK interrupt mask                                */
-
-/********************  Bit definition for USB_OTG_HPRT register  ********************/
-#define USB_OTG_HPRT_PCSTS                   0x00000001U            /*!< Port connect status        */
-#define USB_OTG_HPRT_PCDET                   0x00000002U            /*!< Port connect detected      */
-#define USB_OTG_HPRT_PENA                    0x00000004U            /*!< Port enable                */
-#define USB_OTG_HPRT_PENCHNG                 0x00000008U            /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA                    0x00000010U            /*!< Port overcurrent active    */
-#define USB_OTG_HPRT_POCCHNG                 0x00000020U            /*!< Port overcurrent change    */
-#define USB_OTG_HPRT_PRES                    0x00000040U            /*!< Port resume                */
-#define USB_OTG_HPRT_PSUSP                   0x00000080U            /*!< Port suspend               */
-#define USB_OTG_HPRT_PRST                    0x00000100U            /*!< Port reset                 */
-
-#define USB_OTG_HPRT_PLSTS                   0x00000C00U            /*!< Port line status           */
-#define USB_OTG_HPRT_PLSTS_0                 0x00000400U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PLSTS_1                 0x00000800U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PPWR                    0x00001000U            /*!< Port power                 */
-
-#define USB_OTG_HPRT_PTCTL                   0x0001E000U            /*!< Port test control          */
-#define USB_OTG_HPRT_PTCTL_0                 0x00002000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PTCTL_1                 0x00004000U            /*!<Bit 1 */
-#define USB_OTG_HPRT_PTCTL_2                 0x00008000U            /*!<Bit 2 */
-#define USB_OTG_HPRT_PTCTL_3                 0x00010000U            /*!<Bit 3 */
-
-#define USB_OTG_HPRT_PSPD                    0x00060000U            /*!< Port speed                 */
-#define USB_OTG_HPRT_PSPD_0                  0x00020000U            /*!<Bit 0 */
-#define USB_OTG_HPRT_PSPD_1                  0x00040000U            /*!<Bit 1 */
-
-/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
-#define USB_OTG_DOEPEACHMSK1_XFRCM               0x00000001U            /*!< Transfer completed interrupt mask         */
-#define USB_OTG_DOEPEACHMSK1_EPDM                0x00000002U            /*!< Endpoint disabled interrupt mask          */
-#define USB_OTG_DOEPEACHMSK1_TOM                 0x00000008U            /*!< Timeout condition mask                    */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           0x00000010U            /*!< IN token received when TxFIFO empty mask  */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM             0x00000020U            /*!< IN token received with EP mismatch mask   */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM             0x00000040U            /*!< IN endpoint NAK effective mask            */
-#define USB_OTG_DOEPEACHMSK1_TXFURM              0x00000100U            /*!< OUT packet error mask                     */
-#define USB_OTG_DOEPEACHMSK1_BIM                 0x00000200U            /*!< BNA interrupt mask                        */
-#define USB_OTG_DOEPEACHMSK1_BERRM               0x00001000U            /*!< Bubble error interrupt mask               */
-#define USB_OTG_DOEPEACHMSK1_NAKM                0x00002000U            /*!< NAK interrupt mask                        */
-#define USB_OTG_DOEPEACHMSK1_NYETM               0x00004000U            /*!< NYET interrupt mask                       */
-
-/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
-#define USB_OTG_HPTXFSIZ_PTXSA                   0x0000FFFFU            /*!< Host periodic TxFIFO start address            */
-#define USB_OTG_HPTXFSIZ_PTXFD                   0xFFFF0000U            /*!< Host periodic TxFIFO depth                    */
-
-/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
-#define USB_OTG_DIEPCTL_MPSIZ                   0x000007FFU            /*!< Maximum packet size              */
-#define USB_OTG_DIEPCTL_USBAEP                  0x00008000U            /*!< USB active endpoint              */
-#define USB_OTG_DIEPCTL_EONUM_DPID              0x00010000U            /*!< Even/odd frame                   */
-#define USB_OTG_DIEPCTL_NAKSTS                  0x00020000U            /*!< NAK status                       */
-
-#define USB_OTG_DIEPCTL_EPTYP                   0x000C0000U            /*!< Endpoint type                    */
-#define USB_OTG_DIEPCTL_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_STALL                   0x00200000U            /*!< STALL handshake                  */
-
-#define USB_OTG_DIEPCTL_TXFNUM                  0x03C00000U            /*!< TxFIFO number                    */
-#define USB_OTG_DIEPCTL_TXFNUM_0                0x00400000U            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                0x00800000U            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                0x01000000U            /*!<Bit 2 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                0x02000000U            /*!<Bit 3 */
-#define USB_OTG_DIEPCTL_CNAK                    0x04000000U            /*!< Clear NAK                        */
-#define USB_OTG_DIEPCTL_SNAK                    0x08000000U            /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          0x10000000U            /*!< Set DATA0 PID                    */
-#define USB_OTG_DIEPCTL_SODDFRM                 0x20000000U            /*!< Set odd frame                    */
-#define USB_OTG_DIEPCTL_EPDIS                   0x40000000U            /*!< Endpoint disable                 */
-#define USB_OTG_DIEPCTL_EPENA                   0x80000000U            /*!< Endpoint enable                  */
-
-/********************  Bit definition for USB_OTG_HCCHAR register  ********************/
-#define USB_OTG_HCCHAR_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
-
-#define USB_OTG_HCCHAR_EPNUM                   0x00007800U            /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                 0x00000800U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPNUM_1                 0x00001000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_EPNUM_2                 0x00002000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_EPNUM_3                 0x00004000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_EPDIR                   0x00008000U            /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV                   0x00020000U            /*!< Low-speed device */
-
-#define USB_OTG_HCCHAR_EPTYP                   0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                 0x00040000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPTYP_1                 0x00080000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_MC                      0x00300000U            /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                    0x00100000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_MC_1                    0x00200000U            /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_DAD                     0x1FC00000U            /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                   0x00400000U            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_DAD_1                   0x00800000U            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_DAD_2                   0x01000000U            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_DAD_3                   0x02000000U            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_DAD_4                   0x04000000U            /*!<Bit 4 */
-#define USB_OTG_HCCHAR_DAD_5                   0x08000000U            /*!<Bit 5 */
-#define USB_OTG_HCCHAR_DAD_6                   0x10000000U            /*!<Bit 6 */
-#define USB_OTG_HCCHAR_ODDFRM                  0x20000000U            /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS                   0x40000000U            /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA                   0x80000000U            /*!< Channel enable */
-
-/********************  Bit definition for USB_OTG_HCSPLT register  ********************/
-
-#define USB_OTG_HCSPLT_PRTADDR                 0x0000007FU            /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0               0x00000001U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_PRTADDR_1               0x00000002U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_PRTADDR_2               0x00000004U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_PRTADDR_3               0x00000008U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_PRTADDR_4               0x00000010U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_PRTADDR_5               0x00000020U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_PRTADDR_6               0x00000040U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_HUBADDR                 0x00003F80U            /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0               0x00000080U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_HUBADDR_1               0x00000100U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_HUBADDR_2               0x00000200U            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_HUBADDR_3               0x00000400U            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_HUBADDR_4               0x00000800U            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_HUBADDR_5               0x00001000U            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_HUBADDR_6               0x00002000U            /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_XACTPOS                 0x0000C000U            /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0               0x00004000U            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_XACTPOS_1               0x00008000U            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_COMPLSPLT               0x00010000U            /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN                 0x80000000U            /*!< Split enable */
-
-/********************  Bit definition for USB_OTG_HCINT register  ********************/
-#define USB_OTG_HCINT_XFRC                    0x00000001U            /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH                     0x00000002U            /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINT_STALL                   0x00000008U            /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK                     0x00000010U            /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK                     0x00000020U            /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET                    0x00000040U            /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR                   0x00000080U            /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR                   0x00000100U            /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR                   0x00000200U            /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR                   0x00000400U            /*!< Data toggle error */
-
-/********************  Bit definition for USB_OTG_DIEPINT register  ********************/
-#define USB_OTG_DIEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_TOC                     0x00000008U            /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE                  0x00000010U            /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNE                  0x00000040U            /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE                    0x00000080U            /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN              0x00000100U            /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA                     0x00000200U            /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS               0x00000800U            /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR                    0x00001000U            /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK                     0x00002000U            /*!< NAK interrupt */
-
-/********************  Bit definition for USB_OTG_HCINTMSK register  ********************/
-#define USB_OTG_HCINTMSK_XFRCM                   0x00000001U            /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM                    0x00000002U            /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR                  0x00000004U            /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM                  0x00000008U            /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM                    0x00000010U            /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM                    0x00000020U            /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET                    0x00000040U            /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM                  0x00000080U            /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM                  0x00000100U            /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM                  0x00000200U            /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM                  0x00000400U            /*!< Data toggle error mask */
-
-/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
-
-#define USB_OTG_DIEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT                  0x60000000U            /*!< Packet count */
-/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
-#define USB_OTG_HCTSIZ_XFRSIZ                    0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT                    0x1FF80000U            /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING                    0x80000000U            /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID                      0x60000000U            /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                    0x20000000U            /*!<Bit 0 */
-#define USB_OTG_HCTSIZ_DPID_1                    0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
-#define USB_OTG_DIEPDMA_DMAADDR                  0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition for USB_OTG_HCDMA register  ********************/
-#define USB_OTG_HCDMA_DMAADDR                    0xFFFFFFFFU            /*!< DMA address */
-
-/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
-#define USB_OTG_DTXFSTS_INEPTFSAV                0x0000FFFFU            /*!< IN endpoint TxFIFO space available */
-
-/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
-#define USB_OTG_DIEPTXF_INEPTXSA                 0x0000FFFFU            /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD                 0xFFFF0000U            /*!< IN endpoint TxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
-#define USB_OTG_DOEPCTL_MPSIZ                     0x000007FFU            /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP                    0x00008000U            /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS                    0x00020000U            /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            0x10000000U            /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM                   0x20000000U            /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP                     0x000C0000U            /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                   0x00040000U            /*!<Bit 0 */
-#define USB_OTG_DOEPCTL_EPTYP_1                   0x00080000U            /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_SNPM                      0x00100000U            /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL                     0x00200000U            /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK                      0x04000000U            /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK                      0x08000000U            /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS                     0x40000000U            /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA                     0x80000000U            /*!< Endpoint enable */
-
-/********************  Bit definition for USB_OTG_DOEPINT register  ********************/
-#define USB_OTG_DOEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_STUP                    0x00000008U            /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS                 0x00000010U            /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_OTEPSPR                 0x00000020U            /*!< Status Phase Received For Control Write */
-#define USB_OTG_DOEPINT_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_NYET                    0x00004000U            /*!< NYET interrupt */
-
-/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
-#define USB_OTG_DOEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
-
-#define USB_OTG_DOEPTSIZ_STUPCNT                 0x60000000U            /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0               0x20000000U            /*!<Bit 0 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1               0x40000000U            /*!<Bit 1 */
-
-/********************  Bit definition for PCGCCTL register  ********************/
-#define USB_OTG_PCGCCTL_STOPCLK                 0x00000001U            /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK                 0x00000002U            /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP                 0x00000010U            /*!<Bit 1 */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                        JPEG Encoder/Decoder                                */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for CONFR0 register  ********************/
-#define  JPEG_CONFR0_START                       0x00000001U        /*!<Start/Stop bit */  
-
-/********************  Bit definition for CONFR1 register  *******************/
-#define  JPEG_CONFR1_NF                          0x00000003U        /*!<Number of color components */  
-#define  JPEG_CONFR1_NF_0                        0x00000001U        /*!<Bit 0 */   
-#define  JPEG_CONFR1_NF_1                        0x00000002U        /*!<Bit 1 */
-#define  JPEG_CONFR1_RE                          0x00000004U        /*!<Restart maker Enable */  
-#define  JPEG_CONFR1_DE                          0x00000008U        /*!<Decoding Enable */  
-#define  JPEG_CONFR1_COLORSPACE                  0x00000030U        /*!<Color Space */  
-#define  JPEG_CONFR1_COLORSPACE_0                0x00000010U        /*!<Bit 0 */  
-#define  JPEG_CONFR1_COLORSPACE_1                0x00000020U        /*!<Bit 1 */  
-#define  JPEG_CONFR1_NS                          0x000000C0U        /*!<Number of components for Scan */  
-#define  JPEG_CONFR1_NS_0                        0x00000040U        /*!<Bit 0 */  
-#define  JPEG_CONFR1_NS_1                        0x00000080U        /*!<Bit 1 */
-#define  JPEG_CONFR1_HDR                         0x00000100U        /*!<Header Processing On/Off */
-#define  JPEG_CONFR1_YSIZE                       0xFFFF0000U        /*!<Number of lines in source image */
-
-/********************  Bit definition for CONFR2 register  *******************/
-#define  JPEG_CONFR2_NMCU                        0x03FFFFFFU        /*!<Number of MCU units minus 1 to encode */
-
-/********************  Bit definition for CONFR3 register  *******************/
-#define  JPEG_CONFR3_NRST                        0x0000FFFFU        /*!<Number of MCU between two restart makers minus 1 */
-#define  JPEG_CONFR3_XSIZE                       0xFFFF0000U        /*!<Number of pixels per line */
-
-/********************  Bit definition for CONFR4 register  *******************/
-#define  JPEG_CONFR4_HD                          0x00000001U        /*!<Selects the Huffman table for encoding the DC coefficients */  
-#define  JPEG_CONFR4_HA                          0x00000002U        /*!<Selects the Huffman table for encoding the AC coefficients */ 
-#define  JPEG_CONFR4_QT                          0x0000000CU        /*!<Selects quantization table associated with a color component */
-#define  JPEG_CONFR4_QT_0                        0x00000004U        /*!<Bit 0 */
-#define  JPEG_CONFR4_QT_1                        0x00000008U        /*!<Bit 1 */
-#define  JPEG_CONFR4_NB                          0x000000F0U        /*!<Number of data units minus 1 that belong to a particular color in the MCU */
-#define  JPEG_CONFR4_NB_0                        0x00000010U        /*!<Bit 0 */
-#define  JPEG_CONFR4_NB_1                        0x00000020U        /*!<Bit 1 */
-#define  JPEG_CONFR4_NB_2                        0x00000040U        /*!<Bit 2 */
-#define  JPEG_CONFR4_NB_3                        0x00000080U        /*!<Bit 3 */
-#define  JPEG_CONFR4_VSF                         0x00000F00U        /*!<Vertical sampling factor for component 1 */
-#define  JPEG_CONFR4_VSF_0                       0x00000100U        /*!<Bit 0 */
-#define  JPEG_CONFR4_VSF_1                       0x00000200U        /*!<Bit 1 */
-#define  JPEG_CONFR4_VSF_2                       0x00000400U        /*!<Bit 2 */
-#define  JPEG_CONFR4_VSF_3                       0x00000800U        /*!<Bit 3 */
-#define  JPEG_CONFR4_HSF                         0x0000F000U        /*!<Horizontal sampling factor for component 1 */
-#define  JPEG_CONFR4_HSF_0                       0x00001000U        /*!<Bit 0 */
-#define  JPEG_CONFR4_HSF_1                       0x00002000U        /*!<Bit 1 */
-#define  JPEG_CONFR4_HSF_2                       0x00004000U        /*!<Bit 2 */
-#define  JPEG_CONFR4_HSF_3                       0x00008000U        /*!<Bit 3 */
-
-/********************  Bit definition for CONFR5 register  *******************/
-#define  JPEG_CONFR5_HD                          0x00000001U        /*!<Selects the Huffman table for encoding the DC coefficients */  
-#define  JPEG_CONFR5_HA                          0x00000002U        /*!<Selects the Huffman table for encoding the AC coefficients */ 
-#define  JPEG_CONFR5_QT                          0x0000000CU        /*!<Selects quantization table associated with a color component */
-#define  JPEG_CONFR5_QT_0                        0x00000004U        /*!<Bit 0 */
-#define  JPEG_CONFR5_QT_1                        0x00000008U        /*!<Bit 1 */
-#define  JPEG_CONFR5_NB                          0x000000F0U        /*!<Number of data units minus 1 that belong to a particular color in the MCU */
-#define  JPEG_CONFR5_NB_0                        0x00000010U        /*!<Bit 0 */
-#define  JPEG_CONFR5_NB_1                        0x00000020U        /*!<Bit 1 */
-#define  JPEG_CONFR5_NB_2                        0x00000040U        /*!<Bit 2 */
-#define  JPEG_CONFR5_NB_3                        0x00000080U        /*!<Bit 3 */
-#define  JPEG_CONFR5_VSF                         0x00000F00U        /*!<Vertical sampling factor for component 2 */
-#define  JPEG_CONFR5_VSF_0                       0x00000100U        /*!<Bit 0 */
-#define  JPEG_CONFR5_VSF_1                       0x00000200U        /*!<Bit 1 */
-#define  JPEG_CONFR5_VSF_2                       0x00000400U        /*!<Bit 2 */
-#define  JPEG_CONFR5_VSF_3                       0x00000800U        /*!<Bit 3 */
-#define  JPEG_CONFR5_HSF                         0x0000F000U        /*!<Horizontal sampling factor for component 2 */
-#define  JPEG_CONFR5_HSF_0                       0x00001000U        /*!<Bit 0 */
-#define  JPEG_CONFR5_HSF_1                       0x00002000U        /*!<Bit 1 */
-#define  JPEG_CONFR5_HSF_2                       0x00004000U        /*!<Bit 2 */
-#define  JPEG_CONFR5_HSF_3                       0x00008000U        /*!<Bit 3 */
-
-/********************  Bit definition for CONFR6 register  *******************/
-#define  JPEG_CONFR6_HD                          0x00000001U        /*!<Selects the Huffman table for encoding the DC coefficients */  
-#define  JPEG_CONFR6_HA                          0x00000002U        /*!<Selects the Huffman table for encoding the AC coefficients */ 
-#define  JPEG_CONFR6_QT                          0x0000000CU        /*!<Selects quantization table associated with a color component */
-#define  JPEG_CONFR6_QT_0                        0x00000004U        /*!<Bit 0 */
-#define  JPEG_CONFR6_QT_1                        0x00000008U        /*!<Bit 1 */
-#define  JPEG_CONFR6_NB                          0x000000F0U        /*!<Number of data units minus 1 that belong to a particular color in the MCU */
-#define  JPEG_CONFR6_NB_0                        0x00000010U        /*!<Bit 0 */
-#define  JPEG_CONFR6_NB_1                        0x00000020U        /*!<Bit 1 */
-#define  JPEG_CONFR6_NB_2                        0x00000040U        /*!<Bit 2 */
-#define  JPEG_CONFR6_NB_3                        0x00000080U        /*!<Bit 3 */
-#define  JPEG_CONFR6_VSF                         0x00000F00U        /*!<Vertical sampling factor for component 2 */
-#define  JPEG_CONFR6_VSF_0                       0x00000100U        /*!<Bit 0 */
-#define  JPEG_CONFR6_VSF_1                       0x00000200U        /*!<Bit 1 */
-#define  JPEG_CONFR6_VSF_2                       0x00000400U        /*!<Bit 2 */
-#define  JPEG_CONFR6_VSF_3                       0x00000800U        /*!<Bit 3 */
-#define  JPEG_CONFR6_HSF                         0x0000F000U        /*!<Horizontal sampling factor for component 2 */
-#define  JPEG_CONFR6_HSF_0                       0x00001000U        /*!<Bit 0 */
-#define  JPEG_CONFR6_HSF_1                       0x00002000U        /*!<Bit 1 */
-#define  JPEG_CONFR6_HSF_2                       0x00004000U        /*!<Bit 2 */
-#define  JPEG_CONFR6_HSF_3                       0x00008000U        /*!<Bit 3 */
-
-/********************  Bit definition for CONFR7 register  *******************/
-#define  JPEG_CONFR7_HD                          0x00000001U        /*!<Selects the Huffman table for encoding the DC coefficients */  
-#define  JPEG_CONFR7_HA                          0x00000002U        /*!<Selects the Huffman table for encoding the AC coefficients */ 
-#define  JPEG_CONFR7_QT                          0x0000000CU        /*!<Selects quantization table associated with a color component */
-#define  JPEG_CONFR7_QT_0                        0x00000004U        /*!<Bit 0 */
-#define  JPEG_CONFR7_QT_1                        0x00000008U        /*!<Bit 1 */
-#define  JPEG_CONFR7_NB                          0x000000F0U        /*!<Number of data units minus 1 that belong to a particular color in the MCU */
-#define  JPEG_CONFR7_NB_0                        0x00000010U        /*!<Bit 0 */
-#define  JPEG_CONFR7_NB_1                        0x00000020U        /*!<Bit 1 */
-#define  JPEG_CONFR7_NB_2                        0x00000040U        /*!<Bit 2 */
-#define  JPEG_CONFR7_NB_3                        0x00000080U        /*!<Bit 3 */
-#define  JPEG_CONFR7_VSF                         0x00000F00U        /*!<Vertical sampling factor for component 2 */
-#define  JPEG_CONFR7_VSF_0                       0x00000100U        /*!<Bit 0 */
-#define  JPEG_CONFR7_VSF_1                       0x00000200U        /*!<Bit 1 */
-#define  JPEG_CONFR7_VSF_2                       0x00000400U        /*!<Bit 2 */
-#define  JPEG_CONFR7_VSF_3                       0x00000800U        /*!<Bit 3 */
-#define  JPEG_CONFR7_HSF                         0x0000F000U        /*!<Horizontal sampling factor for component 2 */
-#define  JPEG_CONFR7_HSF_0                       0x00001000U        /*!<Bit 0 */
-#define  JPEG_CONFR7_HSF_1                       0x00002000U        /*!<Bit 1 */
-#define  JPEG_CONFR7_HSF_2                       0x00004000U        /*!<Bit 2 */
-#define  JPEG_CONFR7_HSF_3                       0x00008000U        /*!<Bit 3 */
-
-/********************  Bit definition for CR register  *******************/
-#define  JPEG_CR_JCEN                            0x00000001U        /*!<Enable the JPEG Codec Core */
-#define  JPEG_CR_IFTIE                           0x00000002U        /*!<Input FIFO Threshold Interrupt Enable */
-#define  JPEG_CR_IFNFIE                          0x00000004U        /*!<Input FIFO Not Full Interrupt Enable */
-#define  JPEG_CR_OFTIE                           0x00000008U        /*!<Output FIFO Threshold Interrupt Enable */
-#define  JPEG_CR_OFNEIE                          0x00000010U        /*!<Output FIFO Not Empty Interrupt Enable */
-#define  JPEG_CR_EOCIE                           0x00000020U        /*!<End of Conversion Interrupt Enable */
-#define  JPEG_CR_HPDIE                           0x00000040U        /*!<Header Parsing Done Interrupt Enable */
-#define  JPEG_CR_IDMAEN                          0x00000800U        /*!<Enable the DMA request generation for the input FIFO */
-#define  JPEG_CR_ODMAEN                          0x00001000U        /*!<Enable the DMA request generation for the output FIFO */
-#define  JPEG_CR_IFF                             0x00002000U        /*!<Flush the input FIFO */
-#define  JPEG_CR_OFF                             0x00004000U        /*!<Flush the output FIFO */
-
-/********************  Bit definition for SR register  *******************/
-#define  JPEG_SR_IFTF                            0x00000002U        /*!<Input FIFO is not full and is bellow its threshold flag */
-#define  JPEG_SR_IFNFF                           0x00000004U        /*!<Input FIFO Not Full Flag, a data can be written */
-#define  JPEG_SR_OFTF                            0x00000008U        /*!<Output FIFO is not empty and has reach its threshold */
-#define  JPEG_SR_OFNEF                           0x000000010U       /*!<Output FIFO is not empty, a data is available */
-#define  JPEG_SR_EOCF                            0x000000020U       /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */
-#define  JPEG_SR_HPDF                            0x000000040U       /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */
-#define  JPEG_SR_COF                             0x000000080U       /*!<JPEG Codec operation on going  flag */
-
-/********************  Bit definition for CFR register  *******************/
-#define  JPEG_CFR_CEOCF                          0x00000020U       /*!<Clear End of Conversion Flag */
-#define  JPEG_CFR_CHPDF                          0x00000040U       /*!<Clear Header Parsing Done Flag */
-
-/********************  Bit definition for DIR register  ********************/
-#define  JPEG_DIR_DATAIN                         0xFFFFFFFFU        /*!<Data Input FIFO */
-
-/********************  Bit definition for DOR register  ********************/
-#define  JPEG_DOR_DATAOUT                        0xFFFFFFFFU        /*!<Data Output FIFO */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                MDIOS                                        */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for MDIOS_CR register  *******************/
-#define MDIOS_CR_EN               0x00000001U    /*!<Peripheral enable */
-#define MDIOS_CR_WRIE             0x00000002U    /*!<Register write interrupt enable */ 
-#define MDIOS_CR_RDIE             0x00000004U    /*!<Register Read Interrupt Enable */
-#define MDIOS_CR_EIE              0x00000008U    /*!<Error interrupt enable */
-#define MDIOS_CR_DPC              0x00000080U    /*!<Disable Preamble Check */
-#define MDIOS_CR_PORT_ADDRESS     0x00001F00U    /*!<PORT_ADDRESS[4:0] bits */
-#define MDIOS_CR_PORT_ADDRESS_0   0x00000100U    /*!<Bit 0 */
-#define MDIOS_CR_PORT_ADDRESS_1   0x00000200U    /*!<Bit 1 */
-#define MDIOS_CR_PORT_ADDRESS_2   0x00000400U    /*!<Bit 2 */
-#define MDIOS_CR_PORT_ADDRESS_3   0x00000800U    /*!<Bit 3 */
-#define MDIOS_CR_PORT_ADDRESS_4   0x00001000U    /*!<Bit 4 */
-
-/********************  Bit definition for MDIOS_WRFR register  *******************/
-#define MDIOS_WRFR_WRF            0xFFFFFFFFU    /*!<WRF[31:0] bits (Write flags for MDIO register 0 to 31) */
-
-/********************  Bit definition for MDIOS_CWRFR register  *******************/
-#define MDIOS_CWRFR_CWRF           0xFFFFFFFFU    /*!<CWRF[31:0] bits (Clear the write flag for MDIO register 0 to 31) */
-
-/********************  Bit definition for MDIOS_RDFR register  *******************/
-#define MDIOS_RDFR_RDF           0xFFFFFFFFU      /*!<RDF[31:0] bits (Read flags for MDIO registers 0 to 31) */
-
-/********************  Bit definition for MDIOS_CRDFR register  *******************/
-#define MDIOS_CRDFR_CRDF          0xFFFFFFFFU      /*!<CRDF[31:0] bits (Clear the read flag for MDIO registers 0 to 31) */
-
-/********************  Bit definition for MDIOS_SR register  *******************/
-#define MDIOS_SR_PERF             0x00000001U    /*!< Preamble error flag */
-#define MDIOS_SR_SERF             0x00000002U    /*!< Start error flag */
-#define MDIOS_SR_TERF             0x00000004U    /*!< Turnaround error flag */
-
-/********************  Bit definition for MDIOS_CLRFR register  *******************/
-#define MDIOS_CLRFR_CPERF             0x00000001U    /*!< Clear the preamble error flag */
-#define MDIOS_CLRFR_CSERF             0x00000002U    /*!< Clear the start error flag */
-#define MDIOS_CLRFR_CTERF             0x00000004U    /*!< Clear the turnaround error flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Display Serial Interface (DSI)                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for DSI_VR register  *****************/
-#define DSI_VR                         0x3133302AU               /*!< DSI Host Version */
-
-/*******************  Bit definition for DSI_CR register  *****************/
-#define DSI_CR_EN                      0x00000001U               /*!< DSI Host power up and reset */
-
-/*******************  Bit definition for DSI_CCR register  ****************/
-#define DSI_CCR_TXECKDIV               0x000000FFU               /*!< TX Escape Clock Division */
-#define DSI_CCR_TXECKDIV0              0x00000001U
-#define DSI_CCR_TXECKDIV1              0x00000002U
-#define DSI_CCR_TXECKDIV2              0x00000004U
-#define DSI_CCR_TXECKDIV3              0x00000008U
-#define DSI_CCR_TXECKDIV4              0x00000010U
-#define DSI_CCR_TXECKDIV5              0x00000020U
-#define DSI_CCR_TXECKDIV6              0x00000040U
-#define DSI_CCR_TXECKDIV7              0x00000080U
-
-#define DSI_CCR_TOCKDIV                0x0000FF00U               /*!< Timeout Clock Division */
-#define DSI_CCR_TOCKDIV0               0x00000100U
-#define DSI_CCR_TOCKDIV1               0x00000200U
-#define DSI_CCR_TOCKDIV2               0x00000400U
-#define DSI_CCR_TOCKDIV3               0x00000800U
-#define DSI_CCR_TOCKDIV4               0x00001000U
-#define DSI_CCR_TOCKDIV5               0x00002000U
-#define DSI_CCR_TOCKDIV6               0x00004000U
-#define DSI_CCR_TOCKDIV7               0x00008000U
-
-/*******************  Bit definition for DSI_LVCIDR register  *************/
-#define DSI_LVCIDR_VCID                0x00000003U               /*!< Virtual Channel ID */
-#define DSI_LVCIDR_VCID0               0x00000001U
-#define DSI_LVCIDR_VCID1               0x00000002U
-
-/*******************  Bit definition for DSI_LCOLCR register  *************/
-#define DSI_LCOLCR_COLC                0x0000000FU               /*!< Color Coding */
-#define DSI_LCOLCR_COLC0               0x00000001U
-#define DSI_LCOLCR_COLC1               0x00000020U
-#define DSI_LCOLCR_COLC2               0x00000040U
-#define DSI_LCOLCR_COLC3               0x00000080U
-
-#define DSI_LCOLCR_LPE                 0x00000100U               /*!< Loosly Packet Enable */
-
-/*******************  Bit definition for DSI_LPCR register  ***************/
-#define DSI_LPCR_DEP                   0x00000001U               /*!< Data Enable Polarity */
-#define DSI_LPCR_VSP                   0x00000002U               /*!< VSYNC Polarity */
-#define DSI_LPCR_HSP                   0x00000004U               /*!< HSYNC Polarity */
-
-/*******************  Bit definition for DSI_LPMCR register  **************/
-#define DSI_LPMCR_VLPSIZE              0x000000FFU               /*!< VACT Largest Packet Size */
-#define DSI_LPMCR_VLPSIZE0             0x00000001U
-#define DSI_LPMCR_VLPSIZE1             0x00000002U
-#define DSI_LPMCR_VLPSIZE2             0x00000004U
-#define DSI_LPMCR_VLPSIZE3             0x00000008U
-#define DSI_LPMCR_VLPSIZE4             0x00000010U
-#define DSI_LPMCR_VLPSIZE5             0x00000020U
-#define DSI_LPMCR_VLPSIZE6             0x00000040U
-#define DSI_LPMCR_VLPSIZE7             0x00000080U
-
-#define DSI_LPMCR_LPSIZE               0x00FF0000U               /*!< Largest Packet Size */
-#define DSI_LPMCR_LPSIZE0              0x00010000U
-#define DSI_LPMCR_LPSIZE1              0x00020000U
-#define DSI_LPMCR_LPSIZE2              0x00040000U
-#define DSI_LPMCR_LPSIZE3              0x00080000U
-#define DSI_LPMCR_LPSIZE4              0x00100000U
-#define DSI_LPMCR_LPSIZE5              0x00200000U
-#define DSI_LPMCR_LPSIZE6              0x00400000U
-#define DSI_LPMCR_LPSIZE7              0x00800000U
-
-/*******************  Bit definition for DSI_PCR register  ****************/
-#define DSI_PCR_ETTXE                  0x00000001U               /*!< EoTp Transmission Enable */
-#define DSI_PCR_ETRXE                  0x00000002U               /*!< EoTp Reception Enable */
-#define DSI_PCR_BTAE                   0x00000004U               /*!< Bus Turn Around Enable */
-#define DSI_PCR_ECCRXE                 0x00000008U               /*!< ECC Reception Enable */
-#define DSI_PCR_CRCRXE                 0x00000010U               /*!< CRC Reception Enable */
-
-/*******************  Bit definition for DSI_GVCIDR register  *************/
-#define DSI_GVCIDR_VCID                0x00000003U               /*!< Virtual Channel ID */
-#define DSI_GVCIDR_VCID0               0x00000001U
-#define DSI_GVCIDR_VCID1               0x00000002U
-
-/*******************  Bit definition for DSI_MCR register  ****************/
-#define DSI_MCR_CMDM                   0x00000001U               /*!< Command Mode */
-
-/*******************  Bit definition for DSI_VMCR register  ***************/
-#define DSI_VMCR_VMT                   0x00000003U               /*!< Video Mode Type */
-#define DSI_VMCR_VMT0                  0x00000001U
-#define DSI_VMCR_VMT1                  0x00000002U
-
-#define DSI_VMCR_LPVSAE                0x00000100U               /*!< Low-Power Vertical Sync Active Enable */
-#define DSI_VMCR_LPVBPE                0x00000200U               /*!< Low-power Vertical Back-Porch Enable */
-#define DSI_VMCR_LPVFPE                0x00000400U               /*!< Low-power Vertical Front-porch Enable */
-#define DSI_VMCR_LPVAE                 0x00000800U               /*!< Low-Power Vertical Active Enable */
-#define DSI_VMCR_LPHBPE                0x00001000U               /*!< Low-Power Horizontal Back-Porch Enable */
-#define DSI_VMCR_LPHFPE                0x00002000U               /*!< Low-Power Horizontal Front-Porch Enable */
-#define DSI_VMCR_FBTAAE                0x00004000U               /*!< Frame Bus-Turn-Around Acknowledge Enable */
-#define DSI_VMCR_LPCE                  0x00008000U               /*!< Low-Power Command Enable */
-#define DSI_VMCR_PGE                   0x00010000U               /*!< Pattern Generator Enable */
-#define DSI_VMCR_PGM                   0x00100000U               /*!< Pattern Generator Mode */
-#define DSI_VMCR_PGO                   0x01000000U               /*!< Pattern Generator Orientation */
-
-/*******************  Bit definition for DSI_VPCR register  ***************/
-#define DSI_VPCR_VPSIZE                0x00003FFFU               /*!< Video Packet Size */
-#define DSI_VPCR_VPSIZE0               0x00000001U
-#define DSI_VPCR_VPSIZE1               0x00000002U
-#define DSI_VPCR_VPSIZE2               0x00000004U
-#define DSI_VPCR_VPSIZE3               0x00000008U
-#define DSI_VPCR_VPSIZE4               0x00000010U
-#define DSI_VPCR_VPSIZE5               0x00000020U
-#define DSI_VPCR_VPSIZE6               0x00000040U
-#define DSI_VPCR_VPSIZE7               0x00000080U
-#define DSI_VPCR_VPSIZE8               0x00000100U
-#define DSI_VPCR_VPSIZE9               0x00000200U
-#define DSI_VPCR_VPSIZE10              0x00000400U
-#define DSI_VPCR_VPSIZE11              0x00000800U
-#define DSI_VPCR_VPSIZE12              0x00001000U
-#define DSI_VPCR_VPSIZE13              0x00002000U
-
-/*******************  Bit definition for DSI_VCCR register  ***************/
-#define DSI_VCCR_NUMC                  0x00001FFFU               /*!< Number of Chunks */
-#define DSI_VCCR_NUMC0                 0x00000001U
-#define DSI_VCCR_NUMC1                 0x00000002U
-#define DSI_VCCR_NUMC2                 0x00000004U
-#define DSI_VCCR_NUMC3                 0x00000008U
-#define DSI_VCCR_NUMC4                 0x00000010U
-#define DSI_VCCR_NUMC5                 0x00000020U
-#define DSI_VCCR_NUMC6                 0x00000040U
-#define DSI_VCCR_NUMC7                 0x00000080U
-#define DSI_VCCR_NUMC8                 0x00000100U
-#define DSI_VCCR_NUMC9                 0x00000200U
-#define DSI_VCCR_NUMC10                0x00000400U
-#define DSI_VCCR_NUMC11                0x00000800U
-#define DSI_VCCR_NUMC12                0x00001000U
-
-/*******************  Bit definition for DSI_VNPCR register  **************/
-#define DSI_VNPCR_NPSIZE               0x00001FFFU               /*!< Null Packet Size */
-#define DSI_VNPCR_NPSIZE0              0x00000001U
-#define DSI_VNPCR_NPSIZE1              0x00000002U
-#define DSI_VNPCR_NPSIZE2              0x00000004U
-#define DSI_VNPCR_NPSIZE3              0x00000008U
-#define DSI_VNPCR_NPSIZE4              0x00000010U
-#define DSI_VNPCR_NPSIZE5              0x00000020U
-#define DSI_VNPCR_NPSIZE6              0x00000040U
-#define DSI_VNPCR_NPSIZE7              0x00000080U
-#define DSI_VNPCR_NPSIZE8              0x00000100U
-#define DSI_VNPCR_NPSIZE9              0x00000200U
-#define DSI_VNPCR_NPSIZE10             0x00000400U
-#define DSI_VNPCR_NPSIZE11             0x00000800U
-#define DSI_VNPCR_NPSIZE12             0x00001000U
-
-/*******************  Bit definition for DSI_VHSACR register  *************/
-#define DSI_VHSACR_HSA                 0x00000FFFU               /*!< Horizontal Synchronism Active duration */
-#define DSI_VHSACR_HSA0                0x00000001U
-#define DSI_VHSACR_HSA1                0x00000002U
-#define DSI_VHSACR_HSA2                0x00000004U
-#define DSI_VHSACR_HSA3                0x00000008U
-#define DSI_VHSACR_HSA4                0x00000010U
-#define DSI_VHSACR_HSA5                0x00000020U
-#define DSI_VHSACR_HSA6                0x00000040U
-#define DSI_VHSACR_HSA7                0x00000080U
-#define DSI_VHSACR_HSA8                0x00000100U
-#define DSI_VHSACR_HSA9                0x00000200U
-#define DSI_VHSACR_HSA10               0x00000400U
-#define DSI_VHSACR_HSA11               0x00000800U
-
-/*******************  Bit definition for DSI_VHBPCR register  *************/
-#define DSI_VHBPCR_HBP                 0x00000FFFU               /*!< Horizontal Back-Porch duration */
-#define DSI_VHBPCR_HBP0                0x00000001U
-#define DSI_VHBPCR_HBP1                0x00000002U
-#define DSI_VHBPCR_HBP2                0x00000004U
-#define DSI_VHBPCR_HBP3                0x00000008U
-#define DSI_VHBPCR_HBP4                0x00000010U
-#define DSI_VHBPCR_HBP5                0x00000020U
-#define DSI_VHBPCR_HBP6                0x00000040U
-#define DSI_VHBPCR_HBP7                0x00000080U
-#define DSI_VHBPCR_HBP8                0x00000100U
-#define DSI_VHBPCR_HBP9                0x00000200U
-#define DSI_VHBPCR_HBP10               0x00000400U
-#define DSI_VHBPCR_HBP11               0x00000800U
-
-/*******************  Bit definition for DSI_VLCR register  ***************/
-#define DSI_VLCR_HLINE                 0x00007FFFU               /*!< Horizontal Line duration */
-#define DSI_VLCR_HLINE0                0x00000001U
-#define DSI_VLCR_HLINE1                0x00000002U
-#define DSI_VLCR_HLINE2                0x00000004U
-#define DSI_VLCR_HLINE3                0x00000008U
-#define DSI_VLCR_HLINE4                0x00000010U
-#define DSI_VLCR_HLINE5                0x00000020U
-#define DSI_VLCR_HLINE6                0x00000040U
-#define DSI_VLCR_HLINE7                0x00000080U
-#define DSI_VLCR_HLINE8                0x00000100U
-#define DSI_VLCR_HLINE9                0x00000200U
-#define DSI_VLCR_HLINE10               0x00000400U
-#define DSI_VLCR_HLINE11               0x00000800U
-#define DSI_VLCR_HLINE12               0x00001000U
-#define DSI_VLCR_HLINE13               0x00002000U
-#define DSI_VLCR_HLINE14               0x00004000U
-
-/*******************  Bit definition for DSI_VVSACR register  *************/
-#define DSI_VVSACR_VSA                 0x000003FFU               /*!< Vertical Synchronism Active duration */
-#define DSI_VVSACR_VSA0                0x00000001U
-#define DSI_VVSACR_VSA1                0x00000002U
-#define DSI_VVSACR_VSA2                0x00000004U
-#define DSI_VVSACR_VSA3                0x00000008U
-#define DSI_VVSACR_VSA4                0x00000010U
-#define DSI_VVSACR_VSA5                0x00000020U
-#define DSI_VVSACR_VSA6                0x00000040U
-#define DSI_VVSACR_VSA7                0x00000080U
-#define DSI_VVSACR_VSA8                0x00000100U
-#define DSI_VVSACR_VSA9                0x00000200U
-
-/*******************  Bit definition for DSI_VVBPCR register  *************/
-#define DSI_VVBPCR_VBP                 0x000003FFU               /*!< Vertical Back-Porch duration */
-#define DSI_VVBPCR_VBP0                0x00000001U
-#define DSI_VVBPCR_VBP1                0x00000002U
-#define DSI_VVBPCR_VBP2                0x00000004U
-#define DSI_VVBPCR_VBP3                0x00000008U
-#define DSI_VVBPCR_VBP4                0x00000010U
-#define DSI_VVBPCR_VBP5                0x00000020U
-#define DSI_VVBPCR_VBP6                0x00000040U
-#define DSI_VVBPCR_VBP7                0x00000080U
-#define DSI_VVBPCR_VBP8                0x00000100U
-#define DSI_VVBPCR_VBP9                0x00000200U
-
-/*******************  Bit definition for DSI_VVFPCR register  *************/
-#define DSI_VVFPCR_VFP                 0x000003FFU               /*!< Vertical Front-Porch duration */
-#define DSI_VVFPCR_VFP0                0x00000001U
-#define DSI_VVFPCR_VFP1                0x00000002U
-#define DSI_VVFPCR_VFP2                0x00000004U
-#define DSI_VVFPCR_VFP3                0x00000008U
-#define DSI_VVFPCR_VFP4                0x00000010U
-#define DSI_VVFPCR_VFP5                0x00000020U
-#define DSI_VVFPCR_VFP6                0x00000040U
-#define DSI_VVFPCR_VFP7                0x00000080U
-#define DSI_VVFPCR_VFP8                0x00000100U
-#define DSI_VVFPCR_VFP9                0x00000200U
-
-/*******************  Bit definition for DSI_VVACR register  **************/
-#define DSI_VVACR_VA                   0x00003FFFU               /*!< Vertical Active duration */
-#define DSI_VVACR_VA0                  0x00000001U
-#define DSI_VVACR_VA1                  0x00000002U
-#define DSI_VVACR_VA2                  0x00000004U
-#define DSI_VVACR_VA3                  0x00000008U
-#define DSI_VVACR_VA4                  0x00000010U
-#define DSI_VVACR_VA5                  0x00000020U
-#define DSI_VVACR_VA6                  0x00000040U
-#define DSI_VVACR_VA7                  0x00000080U
-#define DSI_VVACR_VA8                  0x00000100U
-#define DSI_VVACR_VA9                  0x00000200U
-#define DSI_VVACR_VA10                 0x00000400U
-#define DSI_VVACR_VA11                 0x00000800U
-#define DSI_VVACR_VA12                 0x00001000U
-#define DSI_VVACR_VA13                 0x00002000U
-
-/*******************  Bit definition for DSI_LCCR register  ***************/
-#define DSI_LCCR_CMDSIZE               0x0000FFFFU               /*!< Command Size */
-#define DSI_LCCR_CMDSIZE0              0x00000001U
-#define DSI_LCCR_CMDSIZE1              0x00000002U
-#define DSI_LCCR_CMDSIZE2              0x00000004U
-#define DSI_LCCR_CMDSIZE3              0x00000008U
-#define DSI_LCCR_CMDSIZE4              0x00000010U
-#define DSI_LCCR_CMDSIZE5              0x00000020U
-#define DSI_LCCR_CMDSIZE6              0x00000040U
-#define DSI_LCCR_CMDSIZE7              0x00000080U
-#define DSI_LCCR_CMDSIZE8              0x00000100U
-#define DSI_LCCR_CMDSIZE9              0x00000200U
-#define DSI_LCCR_CMDSIZE10             0x00000400U
-#define DSI_LCCR_CMDSIZE11             0x00000800U
-#define DSI_LCCR_CMDSIZE12             0x00001000U
-#define DSI_LCCR_CMDSIZE13             0x00002000U
-#define DSI_LCCR_CMDSIZE14             0x00004000U
-#define DSI_LCCR_CMDSIZE15             0x00008000U
-
-/*******************  Bit definition for DSI_CMCR register  ***************/
-#define DSI_CMCR_TEARE                 0x00000001U               /*!< Tearing Effect Acknowledge Request Enable */
-#define DSI_CMCR_ARE                   0x00000002U               /*!< Acknowledge Request Enable */
-#define DSI_CMCR_GSW0TX                0x00000100U               /*!< Generic Short Write Zero parameters Transmission */
-#define DSI_CMCR_GSW1TX                0x00000200U               /*!< Generic Short Write One parameters Transmission */
-#define DSI_CMCR_GSW2TX                0x00000400U               /*!< Generic Short Write Two parameters Transmission */
-#define DSI_CMCR_GSR0TX                0x00000800U               /*!< Generic Short Read Zero parameters Transmission */
-#define DSI_CMCR_GSR1TX                0x00001000U               /*!< Generic Short Read One parameters Transmission */
-#define DSI_CMCR_GSR2TX                0x00002000U               /*!< Generic Short Read Two parameters Transmission */
-#define DSI_CMCR_GLWTX                 0x00004000U               /*!< Generic Long Write Transmission */
-#define DSI_CMCR_DSW0TX                0x00010000U               /*!< DCS Short Write Zero parameter Transmission */
-#define DSI_CMCR_DSW1TX                0x00020000U               /*!< DCS Short Read One parameter Transmission */
-#define DSI_CMCR_DSR0TX                0x00040000U               /*!< DCS Short Read Zero parameter Transmission */
-#define DSI_CMCR_DLWTX                 0x00080000U               /*!< DCS Long Write Transmission */
-#define DSI_CMCR_MRDPS                 0x01000000U               /*!< Maximum Read Packet Size */
-
-/*******************  Bit definition for DSI_GHCR register  ***************/
-#define DSI_GHCR_DT                    0x0000003FU               /*!< Type */
-#define DSI_GHCR_DT0                   0x00000001U
-#define DSI_GHCR_DT1                   0x00000002U
-#define DSI_GHCR_DT2                   0x00000004U
-#define DSI_GHCR_DT3                   0x00000008U
-#define DSI_GHCR_DT4                   0x00000010U
-#define DSI_GHCR_DT5                   0x00000020U
-
-#define DSI_GHCR_VCID                  0x000000C0U               /*!< Channel */
-#define DSI_GHCR_VCID0                 0x00000040U
-#define DSI_GHCR_VCID1                 0x00000080U
-
-#define DSI_GHCR_WCLSB                 0x0000FF00U               /*!< WordCount LSB */
-#define DSI_GHCR_WCLSB0                0x00000100U
-#define DSI_GHCR_WCLSB1                0x00000200U
-#define DSI_GHCR_WCLSB2                0x00000400U
-#define DSI_GHCR_WCLSB3                0x00000800U
-#define DSI_GHCR_WCLSB4                0x00001000U
-#define DSI_GHCR_WCLSB5                0x00002000U
-#define DSI_GHCR_WCLSB6                0x00004000U
-#define DSI_GHCR_WCLSB7                0x00008000U
-
-#define DSI_GHCR_WCMSB                 0x00FF0000U               /*!< WordCount MSB */
-#define DSI_GHCR_WCMSB0                0x00010000U
-#define DSI_GHCR_WCMSB1                0x00020000U
-#define DSI_GHCR_WCMSB2                0x00040000U
-#define DSI_GHCR_WCMSB3                0x00080000U
-#define DSI_GHCR_WCMSB4                0x00100000U
-#define DSI_GHCR_WCMSB5                0x00200000U
-#define DSI_GHCR_WCMSB6                0x00400000U
-#define DSI_GHCR_WCMSB7                0x00800000U
-
-/*******************  Bit definition for DSI_GPDR register  ***************/
-#define DSI_GPDR_DATA1                 0x000000FFU               /*!< Payload Byte 1 */
-#define DSI_GPDR_DATA1_0               0x00000001U
-#define DSI_GPDR_DATA1_1               0x00000002U
-#define DSI_GPDR_DATA1_2               0x00000004U
-#define DSI_GPDR_DATA1_3               0x00000008U
-#define DSI_GPDR_DATA1_4               0x00000010U
-#define DSI_GPDR_DATA1_5               0x00000020U
-#define DSI_GPDR_DATA1_6               0x00000040U
-#define DSI_GPDR_DATA1_7               0x00000080U
-
-#define DSI_GPDR_DATA2                 0x0000FF00U               /*!< Payload Byte 2 */
-#define DSI_GPDR_DATA2_0               0x00000100U
-#define DSI_GPDR_DATA2_1               0x00000200U
-#define DSI_GPDR_DATA2_2               0x00000400U
-#define DSI_GPDR_DATA2_3               0x00000800U
-#define DSI_GPDR_DATA2_4               0x00001000U
-#define DSI_GPDR_DATA2_5               0x00002000U
-#define DSI_GPDR_DATA2_6               0x00004000U
-#define DSI_GPDR_DATA2_7               0x00008000U
-
-#define DSI_GPDR_DATA3                 0x00FF0000U               /*!< Payload Byte 3 */
-#define DSI_GPDR_DATA3_0               0x00010000U
-#define DSI_GPDR_DATA3_1               0x00020000U
-#define DSI_GPDR_DATA3_2               0x00040000U
-#define DSI_GPDR_DATA3_3               0x00080000U
-#define DSI_GPDR_DATA3_4               0x00100000U
-#define DSI_GPDR_DATA3_5               0x00200000U
-#define DSI_GPDR_DATA3_6               0x00400000U
-#define DSI_GPDR_DATA3_7               0x00800000U
-
-#define DSI_GPDR_DATA4                 0xFF000000U               /*!< Payload Byte 4 */
-#define DSI_GPDR_DATA4_0               0x01000000U
-#define DSI_GPDR_DATA4_1               0x02000000U
-#define DSI_GPDR_DATA4_2               0x04000000U
-#define DSI_GPDR_DATA4_3               0x08000000U
-#define DSI_GPDR_DATA4_4               0x10000000U
-#define DSI_GPDR_DATA4_5               0x20000000U
-#define DSI_GPDR_DATA4_6               0x40000000U
-#define DSI_GPDR_DATA4_7               0x80000000U
-
-/*******************  Bit definition for DSI_GPSR register  ***************/
-#define DSI_GPSR_CMDFE                 0x00000001U               /*!< Command FIFO Empty */
-#define DSI_GPSR_CMDFF                 0x00000002U               /*!< Command FIFO Full */
-#define DSI_GPSR_PWRFE                 0x00000004U               /*!< Payload Write FIFO Empty */
-#define DSI_GPSR_PWRFF                 0x00000008U               /*!< Payload Write FIFO Full */
-#define DSI_GPSR_PRDFE                 0x00000010U               /*!< Payload Read FIFO Empty */
-#define DSI_GPSR_PRDFF                 0x00000020U               /*!< Payload Read FIFO Full */
-#define DSI_GPSR_RCB                   0x00000040U               /*!< Read Command Busy */
-
-/*******************  Bit definition for DSI_TCCR0register  **************/
-#define DSI_TCCR0_LPRX_TOCNT           0x0000FFFFU               /*!< Low-power Reception Timeout Counter */
-#define DSI_TCCR0_LPRX_TOCNT0          0x00000001U
-#define DSI_TCCR0_LPRX_TOCNT1          0x00000002U
-#define DSI_TCCR0_LPRX_TOCNT2          0x00000004U
-#define DSI_TCCR0_LPRX_TOCNT3          0x00000008U
-#define DSI_TCCR0_LPRX_TOCNT4          0x00000010U
-#define DSI_TCCR0_LPRX_TOCNT5          0x00000020U
-#define DSI_TCCR0_LPRX_TOCNT6          0x00000040U
-#define DSI_TCCR0_LPRX_TOCNT7          0x00000080U
-#define DSI_TCCR0_LPRX_TOCNT8          0x00000100U
-#define DSI_TCCR0_LPRX_TOCNT9          0x00000200U
-#define DSI_TCCR0_LPRX_TOCNT10         0x00000400U
-#define DSI_TCCR0_LPRX_TOCNT11         0x00000800U
-#define DSI_TCCR0_LPRX_TOCNT12         0x00001000U
-#define DSI_TCCR0_LPRX_TOCNT13         0x00002000U
-#define DSI_TCCR0_LPRX_TOCNT14         0x00004000U
-#define DSI_TCCR0_LPRX_TOCNT15         0x00008000U
-
-#define DSI_TCCR0_HSTX_TOCNT           0xFFFF0000U               /*!< High-Speed Transmission Timeout Counter */
-#define DSI_TCCR0_HSTX_TOCNT0          0x00010000U
-#define DSI_TCCR0_HSTX_TOCNT1          0x00020000U
-#define DSI_TCCR0_HSTX_TOCNT2          0x00040000U
-#define DSI_TCCR0_HSTX_TOCNT3          0x00080000U
-#define DSI_TCCR0_HSTX_TOCNT4          0x00100000U
-#define DSI_TCCR0_HSTX_TOCNT5          0x00200000U
-#define DSI_TCCR0_HSTX_TOCNT6          0x00400000U
-#define DSI_TCCR0_HSTX_TOCNT7          0x00800000U
-#define DSI_TCCR0_HSTX_TOCNT8          0x01000000U
-#define DSI_TCCR0_HSTX_TOCNT9          0x02000000U
-#define DSI_TCCR0_HSTX_TOCNT10         0x04000000U
-#define DSI_TCCR0_HSTX_TOCNT11         0x08000000U
-#define DSI_TCCR0_HSTX_TOCNT12         0x10000000U
-#define DSI_TCCR0_HSTX_TOCNT13         0x20000000U
-#define DSI_TCCR0_HSTX_TOCNT14         0x40000000U
-#define DSI_TCCR0_HSTX_TOCNT15         0x80000000U
-
-/*******************  Bit definition for DSI_TCCR1register  **************/
-#define DSI_TCCR1_HSRD_TOCNT           0x0000FFFFU               /*!< High-Speed Read Timeout Counter */
-#define DSI_TCCR1_HSRD_TOCNT0          0x00000001U
-#define DSI_TCCR1_HSRD_TOCNT1          0x00000002U
-#define DSI_TCCR1_HSRD_TOCNT2          0x00000004U
-#define DSI_TCCR1_HSRD_TOCNT3          0x00000008U
-#define DSI_TCCR1_HSRD_TOCNT4          0x00000010U
-#define DSI_TCCR1_HSRD_TOCNT5          0x00000020U
-#define DSI_TCCR1_HSRD_TOCNT6          0x00000040U
-#define DSI_TCCR1_HSRD_TOCNT7          0x00000080U
-#define DSI_TCCR1_HSRD_TOCNT8          0x00000100U
-#define DSI_TCCR1_HSRD_TOCNT9          0x00000200U
-#define DSI_TCCR1_HSRD_TOCNT10         0x00000400U
-#define DSI_TCCR1_HSRD_TOCNT11         0x00000800U
-#define DSI_TCCR1_HSRD_TOCNT12         0x00001000U
-#define DSI_TCCR1_HSRD_TOCNT13         0x00002000U
-#define DSI_TCCR1_HSRD_TOCNT14         0x00004000U
-#define DSI_TCCR1_HSRD_TOCNT15         0x00008000U
-
-/*******************  Bit definition for DSI_TCCR2 register  **************/
-#define DSI_TCCR2_LPRD_TOCNT           0x0000FFFFU               /*!< Low-Power Read Timeout Counter */
-#define DSI_TCCR2_LPRD_TOCNT0          0x00000001U
-#define DSI_TCCR2_LPRD_TOCNT1          0x00000002U
-#define DSI_TCCR2_LPRD_TOCNT2          0x00000004U
-#define DSI_TCCR2_LPRD_TOCNT3          0x00000008U
-#define DSI_TCCR2_LPRD_TOCNT4          0x00000010U
-#define DSI_TCCR2_LPRD_TOCNT5          0x00000020U
-#define DSI_TCCR2_LPRD_TOCNT6          0x00000040U
-#define DSI_TCCR2_LPRD_TOCNT7          0x00000080U
-#define DSI_TCCR2_LPRD_TOCNT8          0x00000100U
-#define DSI_TCCR2_LPRD_TOCNT9          0x00000200U
-#define DSI_TCCR2_LPRD_TOCNT10         0x00000400U
-#define DSI_TCCR2_LPRD_TOCNT11         0x00000800U
-#define DSI_TCCR2_LPRD_TOCNT12         0x00001000U
-#define DSI_TCCR2_LPRD_TOCNT13         0x00002000U
-#define DSI_TCCR2_LPRD_TOCNT14         0x00004000U
-#define DSI_TCCR2_LPRD_TOCNT15         0x00008000U
-
-/*******************  Bit definition for DSI_TCCR3 register  **************/
-#define DSI_TCCR3_HSWR_TOCNT           0x0000FFFFU               /*!< High-Speed Write Timeout Counter */
-#define DSI_TCCR3_HSWR_TOCNT0          0x00000001U
-#define DSI_TCCR3_HSWR_TOCNT1          0x00000002U
-#define DSI_TCCR3_HSWR_TOCNT2          0x00000004U
-#define DSI_TCCR3_HSWR_TOCNT3          0x00000008U
-#define DSI_TCCR3_HSWR_TOCNT4          0x00000010U
-#define DSI_TCCR3_HSWR_TOCNT5          0x00000020U
-#define DSI_TCCR3_HSWR_TOCNT6          0x00000040U
-#define DSI_TCCR3_HSWR_TOCNT7          0x00000080U
-#define DSI_TCCR3_HSWR_TOCNT8          0x00000100U
-#define DSI_TCCR3_HSWR_TOCNT9          0x00000200U
-#define DSI_TCCR3_HSWR_TOCNT10         0x00000400U
-#define DSI_TCCR3_HSWR_TOCNT11         0x00000800U
-#define DSI_TCCR3_HSWR_TOCNT12         0x00001000U
-#define DSI_TCCR3_HSWR_TOCNT13         0x00002000U
-#define DSI_TCCR3_HSWR_TOCNT14         0x00004000U
-#define DSI_TCCR3_HSWR_TOCNT15         0x00008000U
-
-#define DSI_TCCR3_PM                   0x01000000U               /*!< Presp Mode */
-
-/*******************  Bit definition for DSI_TCCR4 register  **************/
-#define DSI_TCCR4_LPWR_TOCNT           0x0000FFFFU               /*!< Low-Power Write Timeout Counter */
-#define DSI_TCCR4_LPWR_TOCNT0          0x00000001U
-#define DSI_TCCR4_LPWR_TOCNT1          0x00000002U
-#define DSI_TCCR4_LPWR_TOCNT2          0x00000004U
-#define DSI_TCCR4_LPWR_TOCNT3          0x00000008U
-#define DSI_TCCR4_LPWR_TOCNT4          0x00000010U
-#define DSI_TCCR4_LPWR_TOCNT5          0x00000020U
-#define DSI_TCCR4_LPWR_TOCNT6          0x00000040U
-#define DSI_TCCR4_LPWR_TOCNT7          0x00000080U
-#define DSI_TCCR4_LPWR_TOCNT8          0x00000100U
-#define DSI_TCCR4_LPWR_TOCNT9          0x00000200U
-#define DSI_TCCR4_LPWR_TOCNT10         0x00000400U
-#define DSI_TCCR4_LPWR_TOCNT11         0x00000800U
-#define DSI_TCCR4_LPWR_TOCNT12         0x00001000U
-#define DSI_TCCR4_LPWR_TOCNT13         0x00002000U
-#define DSI_TCCR4_LPWR_TOCNT14         0x00004000U
-#define DSI_TCCR4_LPWR_TOCNT15         0x00008000U
-
-/*******************  Bit definition for DSI_TCCR5register  **************/
-#define DSI_TCCR5_BTA_TOCNT            0x0000FFFFU               /*!< Bus-Turn-Around Timeout Counter */
-#define DSI_TCCR5_BTA_TOCNT0           0x00000001U
-#define DSI_TCCR5_BTA_TOCNT1           0x00000002U
-#define DSI_TCCR5_BTA_TOCNT2           0x00000004U
-#define DSI_TCCR5_BTA_TOCNT3           0x00000008U
-#define DSI_TCCR5_BTA_TOCNT4           0x00000010U
-#define DSI_TCCR5_BTA_TOCNT5           0x00000020U
-#define DSI_TCCR5_BTA_TOCNT6           0x00000040U
-#define DSI_TCCR5_BTA_TOCNT7           0x00000080U
-#define DSI_TCCR5_BTA_TOCNT8           0x00000100U
-#define DSI_TCCR5_BTA_TOCNT9           0x00000200U
-#define DSI_TCCR5_BTA_TOCNT10          0x00000400U
-#define DSI_TCCR5_BTA_TOCNT11          0x00000800U
-#define DSI_TCCR5_BTA_TOCNT12          0x00001000U
-#define DSI_TCCR5_BTA_TOCNT13          0x00002000U
-#define DSI_TCCR5_BTA_TOCNT14          0x00004000U
-#define DSI_TCCR5_BTA_TOCNT15          0x00008000U
-
-/*******************  Bit definition for DSI_TDCR register  ***************/
-#define DSI_TDCR_3DM                   0x00000003U               /*!< 3D Mode */
-#define DSI_TDCR_3DM0                  0x00000001U
-#define DSI_TDCR_3DM1                  0x00000002U
-
-#define DSI_TDCR_3DF                   0x0000000CU               /*!< 3D Format */
-#define DSI_TDCR_3DF0                  0x00000004U
-#define DSI_TDCR_3DF1                  0x00000008U
-
-#define DSI_TDCR_SVS                   0x00000010U               /*!< Second VSYNC */
-#define DSI_TDCR_RF                    0x00000020U               /*!< Right First */
-#define DSI_TDCR_S3DC                  0x00010000U               /*!< Send 3D Control */
-
-/*******************  Bit definition for DSI_CLCR register  ***************/
-#define DSI_CLCR_DPCC                  0x00000001U               /*!< D-PHY Clock Control */
-#define DSI_CLCR_ACR                   0x00000002U               /*!< Automatic Clocklane Control */
-
-/*******************  Bit definition for DSI_CLTCR register  **************/
-#define DSI_CLTCR_LP2HS_TIME           0x000003FFU               /*!< Low-Power to High-Speed Time */
-#define DSI_CLTCR_LP2HS_TIME0          0x00000001U
-#define DSI_CLTCR_LP2HS_TIME1          0x00000002U
-#define DSI_CLTCR_LP2HS_TIME2          0x00000004U
-#define DSI_CLTCR_LP2HS_TIME3          0x00000008U
-#define DSI_CLTCR_LP2HS_TIME4          0x00000010U
-#define DSI_CLTCR_LP2HS_TIME5          0x00000020U
-#define DSI_CLTCR_LP2HS_TIME6          0x00000040U
-#define DSI_CLTCR_LP2HS_TIME7          0x00000080U
-#define DSI_CLTCR_LP2HS_TIME8          0x00000100U
-#define DSI_CLTCR_LP2HS_TIME9          0x00000200U
-
-#define DSI_CLTCR_HS2LP_TIME           0x03FF0000U               /*!< High-Speed to Low-Power Time */
-#define DSI_CLTCR_HS2LP_TIME0          0x00010000U
-#define DSI_CLTCR_HS2LP_TIME1          0x00020000U
-#define DSI_CLTCR_HS2LP_TIME2          0x00040000U
-#define DSI_CLTCR_HS2LP_TIME3          0x00080000U
-#define DSI_CLTCR_HS2LP_TIME4          0x00100000U
-#define DSI_CLTCR_HS2LP_TIME5          0x00200000U
-#define DSI_CLTCR_HS2LP_TIME6          0x00400000U
-#define DSI_CLTCR_HS2LP_TIME7          0x00800000U
-#define DSI_CLTCR_HS2LP_TIME8          0x01000000U
-#define DSI_CLTCR_HS2LP_TIME9          0x02000000U
-
-/*******************  Bit definition for DSI_DLTCR register  **************/
-#define DSI_DLTCR_MRD_TIME             0x00007FFFU               /*!< Maximum Read Time */
-#define DSI_DLTCR_MRD_TIME0            0x00000001U
-#define DSI_DLTCR_MRD_TIME1            0x00000002U
-#define DSI_DLTCR_MRD_TIME2            0x00000004U
-#define DSI_DLTCR_MRD_TIME3            0x00000008U
-#define DSI_DLTCR_MRD_TIME4            0x00000010U
-#define DSI_DLTCR_MRD_TIME5            0x00000020U
-#define DSI_DLTCR_MRD_TIME6            0x00000040U
-#define DSI_DLTCR_MRD_TIME7            0x00000080U
-#define DSI_DLTCR_MRD_TIME8            0x00000100U
-#define DSI_DLTCR_MRD_TIME9            0x00000200U
-#define DSI_DLTCR_MRD_TIME10           0x00000400U
-#define DSI_DLTCR_MRD_TIME11           0x00000800U
-#define DSI_DLTCR_MRD_TIME12           0x00001000U
-#define DSI_DLTCR_MRD_TIME13           0x00002000U
-#define DSI_DLTCR_MRD_TIME14           0x00004000U
-
-#define DSI_DLTCR_LP2HS_TIME           0x00FF0000U               /*!< Low-Power To High-Speed Time */
-#define DSI_DLTCR_LP2HS_TIME0          0x00010000U
-#define DSI_DLTCR_LP2HS_TIME1          0x00020000U
-#define DSI_DLTCR_LP2HS_TIME2          0x00040000U
-#define DSI_DLTCR_LP2HS_TIME3          0x00080000U
-#define DSI_DLTCR_LP2HS_TIME4          0x00100000U
-#define DSI_DLTCR_LP2HS_TIME5          0x00200000U
-#define DSI_DLTCR_LP2HS_TIME6          0x00400000U
-#define DSI_DLTCR_LP2HS_TIME7          0x00800000U
-
-#define DSI_DLTCR_HS2LP_TIME           0xFF000000U               /*!< High-Speed To Low-Power Time */
-#define DSI_DLTCR_HS2LP_TIME0          0x01000000U
-#define DSI_DLTCR_HS2LP_TIME1          0x02000000U
-#define DSI_DLTCR_HS2LP_TIME2          0x04000000U
-#define DSI_DLTCR_HS2LP_TIME3          0x08000000U
-#define DSI_DLTCR_HS2LP_TIME4          0x10000000U
-#define DSI_DLTCR_HS2LP_TIME5          0x20000000U
-#define DSI_DLTCR_HS2LP_TIME6          0x40000000U
-#define DSI_DLTCR_HS2LP_TIME7          0x80000000U
-
-/*******************  Bit definition for DSI_PCTLRregister  **************/
-#define DSI_PCTLR_DEN                  0x00000002U               /*!< Digital Enable */
-#define DSI_PCTLR_CKE                  0x00000004U               /*!< Clock Enable */
-
-/*******************  Bit definition for DSI_PCONFR register  *************/
-#define DSI_PCONFR_NL                  0x00000003U               /*!< Number of Lanes */
-#define DSI_PCONFR_NL0                 0x00000001U
-#define DSI_PCONFR_NL1                 0x00000002U
-
-#define DSI_PCONFR_SW_TIME             0x0000FF00U               /*!< Stop Wait Time */
-#define DSI_PCONFR_SW_TIME0            0x00000100U
-#define DSI_PCONFR_SW_TIME1            0x00000200U
-#define DSI_PCONFR_SW_TIME2            0x00000400U
-#define DSI_PCONFR_SW_TIME3            0x00000800U
-#define DSI_PCONFR_SW_TIME4            0x00001000U
-#define DSI_PCONFR_SW_TIME5            0x00002000U
-#define DSI_PCONFR_SW_TIME6            0x00004000U
-#define DSI_PCONFR_SW_TIME7            0x00008000U
-
-/*******************  Bit definition for DSI_PUCR register  ***************/
-#define DSI_PUCR_URCL                  0x00000001U               /*!< ULPS Request on Clock Lane */
-#define DSI_PUCR_UECL                  0x00000002U               /*!< ULPS Exit on Clock Lane */
-#define DSI_PUCR_URDL                  0x00000004U               /*!< ULPS Request on Data Lane */
-#define DSI_PUCR_UEDL                  0x00000008U               /*!< ULPS Exit on Data Lane */
-
-/*******************  Bit definition for DSI_PTTCRregister  **************/
-#define DSI_PTTCR_TX_TRIG              0x0000000FU               /*!< Transmission Trigger */
-#define DSI_PTTCR_TX_TRIG0             0x00000001U
-#define DSI_PTTCR_TX_TRIG1             0x00000002U
-#define DSI_PTTCR_TX_TRIG2             0x00000004U
-#define DSI_PTTCR_TX_TRIG3             0x00000008U
-
-/*******************  Bit definition for DSI_PSR register  ****************/
-#define DSI_PSR_PD                     0x00000002U               /*!< PHY Direction */
-#define DSI_PSR_PSSC                   0x00000004U               /*!< PHY Stop State Clock lane */
-#define DSI_PSR_UANC                   0x00000008U               /*!< ULPS Active Not Clock lane */
-#define DSI_PSR_PSS0                   0x00000010U               /*!< PHY Stop State lane 0 */
-#define DSI_PSR_UAN0                   0x00000020U               /*!< ULPS Active Not lane 0 */
-#define DSI_PSR_RUE0                   0x00000040U               /*!< RX ULPS Escape lane 0 */
-#define DSI_PSR_PSS1                   0x00000080U               /*!< PHY Stop State lane 1 */
-#define DSI_PSR_UAN1                   0x00000100U               /*!< ULPS Active Not lane 1 */
-
-/*******************  Bit definition for DSI_ISR0 register  ***************/
-#define DSI_ISR0_AE0                   0x00000001U               /*!< Acknowledge Error 0 */
-#define DSI_ISR0_AE1                   0x00000002U               /*!< Acknowledge Error 1 */
-#define DSI_ISR0_AE2                   0x00000004U               /*!< Acknowledge Error 2 */
-#define DSI_ISR0_AE3                   0x00000008U               /*!< Acknowledge Error 3 */
-#define DSI_ISR0_AE4                   0x00000010U               /*!< Acknowledge Error 4 */
-#define DSI_ISR0_AE5                   0x00000020U               /*!< Acknowledge Error 5 */
-#define DSI_ISR0_AE6                   0x00000040U               /*!< Acknowledge Error 6 */
-#define DSI_ISR0_AE7                   0x00000080U               /*!< Acknowledge Error 7 */
-#define DSI_ISR0_AE8                   0x00000100U               /*!< Acknowledge Error 8 */
-#define DSI_ISR0_AE9                   0x00000200U               /*!< Acknowledge Error 9 */
-#define DSI_ISR0_AE10                  0x00000400U               /*!< Acknowledge Error 10 */
-#define DSI_ISR0_AE11                  0x00000800U               /*!< Acknowledge Error 11 */
-#define DSI_ISR0_AE12                  0x00001000U               /*!< Acknowledge Error 12 */
-#define DSI_ISR0_AE13                  0x00002000U               /*!< Acknowledge Error 13 */
-#define DSI_ISR0_AE14                  0x00004000U               /*!< Acknowledge Error 14 */
-#define DSI_ISR0_AE15                  0x00008000U               /*!< Acknowledge Error 15 */
-#define DSI_ISR0_PE0                   0x00010000U               /*!< PHY Error 0 */
-#define DSI_ISR0_PE1                   0x00020000U               /*!< PHY Error 1 */
-#define DSI_ISR0_PE2                   0x00040000U               /*!< PHY Error 2 */
-#define DSI_ISR0_PE3                   0x00080000U               /*!< PHY Error 3 */
-#define DSI_ISR0_PE4                   0x00100000U               /*!< PHY Error 4 */
-
-/*******************  Bit definition for DSI_ISR1 register  ***************/
-#define DSI_ISR1_TOHSTX                0x00000001U               /*!< Timeout High-Speed Transmission */
-#define DSI_ISR1_TOLPRX                0x00000002U               /*!< Timeout Low-Power Reception */
-#define DSI_ISR1_ECCSE                 0x00000004U               /*!< ECC Single-bit Error */
-#define DSI_ISR1_ECCME                 0x00000008U               /*!< ECC Multi-bit Error */
-#define DSI_ISR1_CRCE                  0x00000010U               /*!< CRC Error */
-#define DSI_ISR1_PSE                   0x00000020U               /*!< Packet Size Error */
-#define DSI_ISR1_EOTPE                 0x00000040U               /*!< EoTp Error */
-#define DSI_ISR1_LPWRE                 0x00000080U               /*!< LTDC Payload Write Error */
-#define DSI_ISR1_GCWRE                 0x00000100U               /*!< Generic Command Write Error */
-#define DSI_ISR1_GPWRE                 0x00000200U               /*!< Generic Payload Write Error */
-#define DSI_ISR1_GPTXE                 0x00000400U               /*!< Generic Payload Transmit Error */
-#define DSI_ISR1_GPRDE                 0x00000800U               /*!< Generic Payload Read Error */
-#define DSI_ISR1_GPRXE                 0x00001000U               /*!< Generic Payload Receive Error */
-
-/*******************  Bit definition for DSI_IER0 register  ***************/
-#define DSI_IER0_AE0IE                 0x00000001U               /*!< Acknowledge Error 0 Interrupt Enable */
-#define DSI_IER0_AE1IE                 0x00000002U               /*!< Acknowledge Error 1 Interrupt Enable */
-#define DSI_IER0_AE2IE                 0x00000004U               /*!< Acknowledge Error 2 Interrupt Enable */
-#define DSI_IER0_AE3IE                 0x00000008U               /*!< Acknowledge Error 3 Interrupt Enable */
-#define DSI_IER0_AE4IE                 0x00000010U               /*!< Acknowledge Error 4 Interrupt Enable */
-#define DSI_IER0_AE5IE                 0x00000020U               /*!< Acknowledge Error 5 Interrupt Enable */
-#define DSI_IER0_AE6IE                 0x00000040U               /*!< Acknowledge Error 6 Interrupt Enable */
-#define DSI_IER0_AE7IE                 0x00000080U               /*!< Acknowledge Error 7 Interrupt Enable */
-#define DSI_IER0_AE8IE                 0x00000100U               /*!< Acknowledge Error 8 Interrupt Enable */
-#define DSI_IER0_AE9IE                 0x00000200U               /*!< Acknowledge Error 9 Interrupt Enable */
-#define DSI_IER0_AE10IE                0x00000400U               /*!< Acknowledge Error 10 Interrupt Enable */
-#define DSI_IER0_AE11IE                0x00000800U               /*!< Acknowledge Error 11 Interrupt Enable */
-#define DSI_IER0_AE12IE                0x00001000U               /*!< Acknowledge Error 12 Interrupt Enable */
-#define DSI_IER0_AE13IE                0x00002000U               /*!< Acknowledge Error 13 Interrupt Enable */
-#define DSI_IER0_AE14IE                0x00004000U               /*!< Acknowledge Error 14 Interrupt Enable */
-#define DSI_IER0_AE15IE                0x00008000U               /*!< Acknowledge Error 15 Interrupt Enable */
-#define DSI_IER0_PE0IE                 0x00010000U               /*!< PHY Error 0 Interrupt Enable */
-#define DSI_IER0_PE1IE                 0x00020000U               /*!< PHY Error 1 Interrupt Enable */
-#define DSI_IER0_PE2IE                 0x00040000U               /*!< PHY Error 2 Interrupt Enable */
-#define DSI_IER0_PE3IE                 0x00080000U               /*!< PHY Error 3 Interrupt Enable */
-#define DSI_IER0_PE4IE                 0x00100000U               /*!< PHY Error 4 Interrupt Enable */
-
-/*******************  Bit definition for DSI_IER1 register  ***************/
-#define DSI_IER1_TOHSTXIE              0x00000001U               /*!< Timeout High-Speed Transmission Interrupt Enable */
-#define DSI_IER1_TOLPRXIE              0x00000002U               /*!< Timeout Low-Power Reception Interrupt Enable */
-#define DSI_IER1_ECCSEIE               0x00000004U               /*!< ECC Single-bit Error Interrupt Enable */
-#define DSI_IER1_ECCMEIE               0x00000008U               /*!< ECC Multi-bit Error Interrupt Enable */
-#define DSI_IER1_CRCEIE                0x00000010U               /*!< CRC Error Interrupt Enable */
-#define DSI_IER1_PSEIE                 0x00000020U               /*!< Packet Size Error Interrupt Enable */
-#define DSI_IER1_EOTPEIE               0x00000040U               /*!< EoTp Error Interrupt Enable */
-#define DSI_IER1_LPWREIE               0x00000080U               /*!< LTDC Payload Write Error Interrupt Enable */
-#define DSI_IER1_GCWREIE               0x00000100U               /*!< Generic Command Write Error Interrupt Enable */
-#define DSI_IER1_GPWREIE               0x00000200U               /*!< Generic Payload Write Error Interrupt Enable */
-#define DSI_IER1_GPTXEIE               0x00000400U               /*!< Generic Payload Transmit Error Interrupt Enable */
-#define DSI_IER1_GPRDEIE               0x00000800U               /*!< Generic Payload Read Error Interrupt Enable */
-#define DSI_IER1_GPRXEIE               0x00001000U               /*!< Generic Payload Receive Error Interrupt Enable */
-
-/*******************  Bit definition for DSI_FIR0 register  ***************/
-#define DSI_FIR0_FAE0                  0x00000001U               /*!< Force Acknowledge Error 0 */
-#define DSI_FIR0_FAE1                  0x00000002U               /*!< Force Acknowledge Error 1 */
-#define DSI_FIR0_FAE2                  0x00000004U               /*!< Force Acknowledge Error 2 */
-#define DSI_FIR0_FAE3                  0x00000008U               /*!< Force Acknowledge Error 3 */
-#define DSI_FIR0_FAE4                  0x00000010U               /*!< Force Acknowledge Error 4 */
-#define DSI_FIR0_FAE5                  0x00000020U               /*!< Force Acknowledge Error 5 */
-#define DSI_FIR0_FAE6                  0x00000040U               /*!< Force Acknowledge Error 6 */
-#define DSI_FIR0_FAE7                  0x00000080U               /*!< Force Acknowledge Error 7 */
-#define DSI_FIR0_FAE8                  0x00000100U               /*!< Force Acknowledge Error 8 */
-#define DSI_FIR0_FAE9                  0x00000200U               /*!< Force Acknowledge Error 9 */
-#define DSI_FIR0_FAE10                 0x00000400U               /*!< Force Acknowledge Error 10 */
-#define DSI_FIR0_FAE11                 0x00000800U               /*!< Force Acknowledge Error 11 */
-#define DSI_FIR0_FAE12                 0x00001000U               /*!< Force Acknowledge Error 12 */
-#define DSI_FIR0_FAE13                 0x00002000U               /*!< Force Acknowledge Error 13 */
-#define DSI_FIR0_FAE14                 0x00004000U               /*!< Force Acknowledge Error 14 */
-#define DSI_FIR0_FAE15                 0x00008000U               /*!< Force Acknowledge Error 15 */
-#define DSI_FIR0_FPE0                  0x00010000U               /*!< Force PHY Error 0 */
-#define DSI_FIR0_FPE1                  0x00020000U               /*!< Force PHY Error 1 */
-#define DSI_FIR0_FPE2                  0x00040000U               /*!< Force PHY Error 2 */
-#define DSI_FIR0_FPE3                  0x00080000U               /*!< Force PHY Error 3 */
-#define DSI_FIR0_FPE4                  0x00100000U               /*!< Force PHY Error 4 */
-
-/*******************  Bit definition for DSI_FIR1 register  ***************/
-#define DSI_FIR1_FTOHSTX               0x00000001U               /*!< Force Timeout High-Speed Transmission */
-#define DSI_FIR1_FTOLPRX               0x00000002U               /*!< Force Timeout Low-Power Reception */
-#define DSI_FIR1_FECCSE                0x00000004U               /*!< Force ECC Single-bit Error */
-#define DSI_FIR1_FECCME                0x00000008U               /*!< Force ECC Multi-bit Error */
-#define DSI_FIR1_FCRCE                 0x00000010U               /*!< Force CRC Error */
-#define DSI_FIR1_FPSE                  0x00000020U               /*!< Force Packet Size Error */
-#define DSI_FIR1_FEOTPE                0x00000040U               /*!< Force EoTp Error */
-#define DSI_FIR1_FLPWRE                0x00000080U               /*!< Force LTDC Payload Write Error */
-#define DSI_FIR1_FGCWRE                0x00000100U               /*!< Force Generic Command Write Error */
-#define DSI_FIR1_FGPWRE                0x00000200U               /*!< Force Generic Payload Write Error */
-#define DSI_FIR1_FGPTXE                0x00000400U               /*!< Force Generic Payload Transmit Error */
-#define DSI_FIR1_FGPRDE                0x00000800U               /*!< Force Generic Payload Read Error */
-#define DSI_FIR1_FGPRXE                0x00001000U               /*!< Force Generic Payload Receive Error */
-
-/*******************  Bit definition for DSI_VSCR register  ***************/
-#define DSI_VSCR_EN                    0x00000001U               /*!< Enable */
-#define DSI_VSCR_UR                    0x00000100U               /*!< Update Register */
-
-/*******************  Bit definition for DSI_LCVCIDR register  ************/
-#define DSI_LCVCIDR_VCID               0x00000003U               /*!< Virtual Channel ID */
-#define DSI_LCVCIDR_VCID0              0x00000001U
-#define DSI_LCVCIDR_VCID1              0x00000002U
-
-/*******************  Bit definition for DSI_LCCCR register  **************/
-#define DSI_LCCCR_COLC                 0x0000000FU               /*!< Color Coding */
-#define DSI_LCCCR_COLC0                0x00000001U
-#define DSI_LCCCR_COLC1                0x00000002U
-#define DSI_LCCCR_COLC2                0x00000004U
-#define DSI_LCCCR_COLC3                0x00000008U
-
-#define DSI_LCCCR_LPE                  0x00000100U               /*!< Loosely Packed Enable */
-
-/*******************  Bit definition for DSI_LPMCCR register  *************/
-#define DSI_LPMCCR_VLPSIZE             0x000000FFU               /*!< VACT Largest Packet Size */
-#define DSI_LPMCCR_VLPSIZE0            0x00000001U
-#define DSI_LPMCCR_VLPSIZE1            0x00000002U
-#define DSI_LPMCCR_VLPSIZE2            0x00000004U
-#define DSI_LPMCCR_VLPSIZE3            0x00000008U
-#define DSI_LPMCCR_VLPSIZE4            0x00000010U
-#define DSI_LPMCCR_VLPSIZE5            0x00000020U
-#define DSI_LPMCCR_VLPSIZE6            0x00000040U
-#define DSI_LPMCCR_VLPSIZE7            0x00000080U
-
-#define DSI_LPMCCR_LPSIZE              0x00FF0000U               /*!< Largest Packet Size */
-#define DSI_LPMCCR_LPSIZE0             0x00010000U
-#define DSI_LPMCCR_LPSIZE1             0x00020000U
-#define DSI_LPMCCR_LPSIZE2             0x00040000U
-#define DSI_LPMCCR_LPSIZE3             0x00080000U
-#define DSI_LPMCCR_LPSIZE4             0x00100000U
-#define DSI_LPMCCR_LPSIZE5             0x00200000U
-#define DSI_LPMCCR_LPSIZE6             0x00400000U
-#define DSI_LPMCCR_LPSIZE7             0x00800000U
-
-/*******************  Bit definition for DSI_VMCCR register  **************/
-#define DSI_VMCCR_VMT                  0x00000003U               /*!< Video Mode Type */
-#define DSI_VMCCR_VMT0                 0x00000001U
-#define DSI_VMCCR_VMT1                 0x00000002U
-
-#define DSI_VMCCR_LPVSAE               0x00000100U               /*!< Low-power Vertical Sync time Enable */
-#define DSI_VMCCR_LPVBPE               0x00000200U               /*!< Low-power Vertical Back-porch Enable */
-#define DSI_VMCCR_LPVFPE               0x00000400U               /*!< Low-power Vertical Front-porch Enable */
-#define DSI_VMCCR_LPVAE                0x00000800U               /*!< Low-power Vertical Active Enable */
-#define DSI_VMCCR_LPHBPE               0x00001000U               /*!< Low-power Horizontal Back-porch Enable */
-#define DSI_VMCCR_LPHFE                0x00002000U               /*!< Low-power Horizontal Front-porch Enable */
-#define DSI_VMCCR_FBTAAE               0x00004000U               /*!< Frame BTA Acknowledge Enable */
-#define DSI_VMCCR_LPCE                 0x00008000U               /*!< Low-power Command Enable */
-
-/*******************  Bit definition for DSI_VPCCR register  **************/
-#define DSI_VPCCR_VPSIZE               0x00003FFFU               /*!< Video Packet Size */
-#define DSI_VPCCR_VPSIZE0              0x00000001U
-#define DSI_VPCCR_VPSIZE1              0x00000002U
-#define DSI_VPCCR_VPSIZE2              0x00000004U
-#define DSI_VPCCR_VPSIZE3              0x00000008U
-#define DSI_VPCCR_VPSIZE4              0x00000010U
-#define DSI_VPCCR_VPSIZE5              0x00000020U
-#define DSI_VPCCR_VPSIZE6              0x00000040U
-#define DSI_VPCCR_VPSIZE7              0x00000080U
-#define DSI_VPCCR_VPSIZE8              0x00000100U
-#define DSI_VPCCR_VPSIZE9              0x00000200U
-#define DSI_VPCCR_VPSIZE10             0x00000400U
-#define DSI_VPCCR_VPSIZE11             0x00000800U
-#define DSI_VPCCR_VPSIZE12             0x00001000U
-#define DSI_VPCCR_VPSIZE13             0x00002000U
-
-/*******************  Bit definition for DSI_VCCCR register  **************/
-#define DSI_VCCCR_NUMC                 0x00001FFFU               /*!< Number of Chunks */
-#define DSI_VCCCR_NUMC0                0x00000001U
-#define DSI_VCCCR_NUMC1                0x00000002U
-#define DSI_VCCCR_NUMC2                0x00000004U
-#define DSI_VCCCR_NUMC3                0x00000008U
-#define DSI_VCCCR_NUMC4                0x00000010U
-#define DSI_VCCCR_NUMC5                0x00000020U
-#define DSI_VCCCR_NUMC6                0x00000040U
-#define DSI_VCCCR_NUMC7                0x00000080U
-#define DSI_VCCCR_NUMC8                0x00000100U
-#define DSI_VCCCR_NUMC9                0x00000200U
-#define DSI_VCCCR_NUMC10               0x00000400U
-#define DSI_VCCCR_NUMC11               0x00000800U
-#define DSI_VCCCR_NUMC12               0x00001000U
-
-/*******************  Bit definition for DSI_VNPCCR register  *************/
-#define DSI_VNPCCR_NPSIZE              0x00001FFFU               /*!< Number of Chunks */
-#define DSI_VNPCCR_NPSIZE0             0x00000001U
-#define DSI_VNPCCR_NPSIZE1             0x00000002U
-#define DSI_VNPCCR_NPSIZE2             0x00000004U
-#define DSI_VNPCCR_NPSIZE3             0x00000008U
-#define DSI_VNPCCR_NPSIZE4             0x00000010U
-#define DSI_VNPCCR_NPSIZE5             0x00000020U
-#define DSI_VNPCCR_NPSIZE6             0x00000040U
-#define DSI_VNPCCR_NPSIZE7             0x00000080U
-#define DSI_VNPCCR_NPSIZE8             0x00000100U
-#define DSI_VNPCCR_NPSIZE9             0x00000200U
-#define DSI_VNPCCR_NPSIZE10            0x00000400U
-#define DSI_VNPCCR_NPSIZE11            0x00000800U
-#define DSI_VNPCCR_NPSIZE12            0x00001000U
-
-/*******************  Bit definition for DSI_VHSACCR register  ************/
-#define DSI_VHSACCR_HSA                0x00000FFFU               /*!< Horizontal Synchronism Active duration */
-#define DSI_VHSACCR_HSA0               0x00000001U
-#define DSI_VHSACCR_HSA1               0x00000002U
-#define DSI_VHSACCR_HSA2               0x00000004U
-#define DSI_VHSACCR_HSA3               0x00000008U
-#define DSI_VHSACCR_HSA4               0x00000010U
-#define DSI_VHSACCR_HSA5               0x00000020U
-#define DSI_VHSACCR_HSA6               0x00000040U
-#define DSI_VHSACCR_HSA7               0x00000080U
-#define DSI_VHSACCR_HSA8               0x00000100U
-#define DSI_VHSACCR_HSA9               0x00000200U
-#define DSI_VHSACCR_HSA10              0x00000400U
-#define DSI_VHSACCR_HSA11              0x00000800U
-
-/*******************  Bit definition for DSI_VHBPCCR register  ************/
-#define DSI_VHBPCCR_HBP                0x00000FFFU               /*!< Horizontal Back-Porch duration */
-#define DSI_VHBPCCR_HBP0               0x00000001U
-#define DSI_VHBPCCR_HBP1               0x00000002U
-#define DSI_VHBPCCR_HBP2               0x00000004U
-#define DSI_VHBPCCR_HBP3               0x00000008U
-#define DSI_VHBPCCR_HBP4               0x00000010U
-#define DSI_VHBPCCR_HBP5               0x00000020U
-#define DSI_VHBPCCR_HBP6               0x00000040U
-#define DSI_VHBPCCR_HBP7               0x00000080U
-#define DSI_VHBPCCR_HBP8               0x00000100U
-#define DSI_VHBPCCR_HBP9               0x00000200U
-#define DSI_VHBPCCR_HBP10              0x00000400U
-#define DSI_VHBPCCR_HBP11              0x00000800U
-
-/*******************  Bit definition for DSI_VLCCR register  **************/
-#define DSI_VLCCR_HLINE                0x00007FFFU               /*!< Horizontal Line duration */
-#define DSI_VLCCR_HLINE0               0x00000001U
-#define DSI_VLCCR_HLINE1               0x00000002U
-#define DSI_VLCCR_HLINE2               0x00000004U
-#define DSI_VLCCR_HLINE3               0x00000008U
-#define DSI_VLCCR_HLINE4               0x00000010U
-#define DSI_VLCCR_HLINE5               0x00000020U
-#define DSI_VLCCR_HLINE6               0x00000040U
-#define DSI_VLCCR_HLINE7               0x00000080U
-#define DSI_VLCCR_HLINE8               0x00000100U
-#define DSI_VLCCR_HLINE9               0x00000200U
-#define DSI_VLCCR_HLINE10              0x00000400U
-#define DSI_VLCCR_HLINE11              0x00000800U
-#define DSI_VLCCR_HLINE12              0x00001000U
-#define DSI_VLCCR_HLINE13              0x00002000U
-#define DSI_VLCCR_HLINE14              0x00004000U
-
-/*******************  Bit definition for DSI_VVSACCR register  ***************/
-#define DSI_VVSACCR_VSA                0x000003FFU               /*!< Vertical Synchronism Active duration */
-#define DSI_VVSACCR_VSA0               0x00000001U
-#define DSI_VVSACCR_VSA1               0x00000002U
-#define DSI_VVSACCR_VSA2               0x00000004U
-#define DSI_VVSACCR_VSA3               0x00000008U
-#define DSI_VVSACCR_VSA4               0x00000010U
-#define DSI_VVSACCR_VSA5               0x00000020U
-#define DSI_VVSACCR_VSA6               0x00000040U
-#define DSI_VVSACCR_VSA7               0x00000080U
-#define DSI_VVSACCR_VSA8               0x00000100U
-#define DSI_VVSACCR_VSA9               0x00000200U
-
-/*******************  Bit definition for DSI_VVBPCCR register  ************/
-#define DSI_VVBPCCR_VBP                0x000003FFU               /*!< Vertical Back-Porch duration */
-#define DSI_VVBPCCR_VBP0               0x00000001U
-#define DSI_VVBPCCR_VBP1               0x00000002U
-#define DSI_VVBPCCR_VBP2               0x00000004U
-#define DSI_VVBPCCR_VBP3               0x00000008U
-#define DSI_VVBPCCR_VBP4               0x00000010U
-#define DSI_VVBPCCR_VBP5               0x00000020U
-#define DSI_VVBPCCR_VBP6               0x00000040U
-#define DSI_VVBPCCR_VBP7               0x00000080U
-#define DSI_VVBPCCR_VBP8               0x00000100U
-#define DSI_VVBPCCR_VBP9               0x00000200U
-
-/*******************  Bit definition for DSI_VVFPCCR register  ************/
-#define DSI_VVFPCCR_VFP                0x000003FFU               /*!< Vertical Front-Porch duration */
-#define DSI_VVFPCCR_VFP0               0x00000001U
-#define DSI_VVFPCCR_VFP1               0x00000002U
-#define DSI_VVFPCCR_VFP2               0x00000004U
-#define DSI_VVFPCCR_VFP3               0x00000008U
-#define DSI_VVFPCCR_VFP4               0x00000010U
-#define DSI_VVFPCCR_VFP5               0x00000020U
-#define DSI_VVFPCCR_VFP6               0x00000040U
-#define DSI_VVFPCCR_VFP7               0x00000080U
-#define DSI_VVFPCCR_VFP8               0x00000100U
-#define DSI_VVFPCCR_VFP9               0x00000200U
-
-/*******************  Bit definition for DSI_VVACCR register  *************/
-#define DSI_VVACCR_VA                  0x00003FFFU               /*!< Vertical Active duration */
-#define DSI_VVACCR_VA0                 0x00000001U
-#define DSI_VVACCR_VA1                 0x00000002U
-#define DSI_VVACCR_VA2                 0x00000004U
-#define DSI_VVACCR_VA3                 0x00000008U
-#define DSI_VVACCR_VA4                 0x00000010U
-#define DSI_VVACCR_VA5                 0x00000020U
-#define DSI_VVACCR_VA6                 0x00000040U
-#define DSI_VVACCR_VA7                 0x00000080U
-#define DSI_VVACCR_VA8                 0x00000100U
-#define DSI_VVACCR_VA9                 0x00000200U
-#define DSI_VVACCR_VA10                0x00000400U
-#define DSI_VVACCR_VA11                0x00000800U
-#define DSI_VVACCR_VA12                0x00001000U
-#define DSI_VVACCR_VA13                0x00002000U
-
-/*******************  Bit definition for DSI_TDCCR register  **************/
-#define DSI_TDCCR_3DM                  0x00000003U               /*!< 3D Mode */
-#define DSI_TDCCR_3DM0                 0x00000001U
-#define DSI_TDCCR_3DM1                 0x00000002U
-
-#define DSI_TDCCR_3DF                  0x0000000CU               /*!< 3D Format */
-#define DSI_TDCCR_3DF0                 0x00000004U
-#define DSI_TDCCR_3DF1                 0x00000008U
-
-#define DSI_TDCCR_SVS                  0x00000010U               /*!< Second VSYNC */
-#define DSI_TDCCR_RF                   0x00000020U               /*!< Right First */
-#define DSI_TDCCR_S3DC                 0x00010000U               /*!< Send 3D Control */
-
-/*******************  Bit definition for DSI_WCFGR register  ***************/
-#define DSI_WCFGR_DSIM                   0x00000001U              /*!< DSI Mode */
-#define DSI_WCFGR_COLMUX                 0x0000000EU              /*!< Color Multiplexing */
-#define DSI_WCFGR_COLMUX0                0x00000002U
-#define DSI_WCFGR_COLMUX1                0x00000004U
-#define DSI_WCFGR_COLMUX2                0x00000008U
-
-#define DSI_WCFGR_TESRC                  0x00000010U              /*!< Tearing Effect Source */
-#define DSI_WCFGR_TEPOL                  0x00000020U              /*!< Tearing Effect Polarity */
-#define DSI_WCFGR_AR                     0x00000040U              /*!< Automatic Refresh */
-#define DSI_WCFGR_VSPOL                  0x00000080U              /*!< VSync Polarity */
-
-/*******************  Bit definition for DSI_WCR register  *****************/
-#define DSI_WCR_COLM                     0x00000001U              /*!< Color Mode */
-#define DSI_WCR_SHTDN                    0x00000002U              /*!< Shutdown */
-#define DSI_WCR_LTDCEN                   0x00000004U              /*!< LTDC Enable */
-#define DSI_WCR_DSIEN                    0x00000008U              /*!< DSI Enable */
-
-/*******************  Bit definition for DSI_WIER register  ****************/
-#define DSI_WIER_TEIE                    0x00000001U              /*!< Tearing Effect Interrupt Enable */
-#define DSI_WIER_ERIE                    0x00000002U              /*!< End of Refresh Interrupt Enable */
-#define DSI_WIER_PLLLIE                  0x00000200U              /*!< PLL Lock Interrupt Enable */
-#define DSI_WIER_PLLUIE                  0x00000400U              /*!< PLL Unlock Interrupt Enable */
-#define DSI_WIER_RRIE                    0x00002000U              /*!< Regulator Ready Interrupt Enable */
-
-/*******************  Bit definition for DSI_WISR register  ****************/
-#define DSI_WISR_TEIF                    0x00000001U              /*!< Tearing Effect Interrupt Flag */
-#define DSI_WISR_ERIF                    0x00000002U              /*!< End of Refresh Interrupt Flag */
-#define DSI_WISR_BUSY                    0x00000004U              /*!< Busy Flag */
-#define DSI_WISR_PLLLS                   0x00000100U              /*!< PLL Lock Status */
-#define DSI_WISR_PLLLIF                  0x00000200U              /*!< PLL Lock Interrupt Flag */
-#define DSI_WISR_PLLUIF                  0x00000400U              /*!< PLL Unlock Interrupt Flag */
-#define DSI_WISR_RRS                     0x00001000U              /*!< Regulator Ready Flag */
-#define DSI_WISR_RRIF                    0x00002000U              /*!< Regulator Ready Interrupt Flag */
-
-/*******************  Bit definition for DSI_WIFCR register  ***************/
-#define DSI_WIFCR_CTEIF                  0x00000001U              /*!< Clear Tearing Effect Interrupt Flag */
-#define DSI_WIFCR_CERIF                  0x00000002U              /*!< Clear End of Refresh Interrupt Flag */
-#define DSI_WIFCR_CPLLLIF                0x00000200U              /*!< Clear PLL Lock Interrupt Flag */
-#define DSI_WIFCR_CPLLUIF                0x00000400U              /*!< Clear PLL Unlock Interrupt Flag */
-#define DSI_WIFCR_CRRIF                  0x00002000U              /*!< Clear Regulator Ready Interrupt Flag */
-
-/*******************  Bit definition for DSI_WPCR0 register  ***************/
-#define DSI_WPCR0_UIX4                   0x0000003FU              /*!< Unit Interval multiplied by 4 */
-#define DSI_WPCR0_UIX4_0                 0x00000001U
-#define DSI_WPCR0_UIX4_1                 0x00000002U
-#define DSI_WPCR0_UIX4_2                 0x00000004U
-#define DSI_WPCR0_UIX4_3                 0x00000008U
-#define DSI_WPCR0_UIX4_4                 0x00000010U
-#define DSI_WPCR0_UIX4_5                 0x00000020U
-
-#define DSI_WPCR0_SWCL                   0x00000040U              /*!< Swap pins on clock lane */
-#define DSI_WPCR0_SWDL0                  0x00000080U              /*!< Swap pins on data lane 1 */
-#define DSI_WPCR0_SWDL1                  0x00000100U              /*!< Swap pins on data lane 2 */
-#define DSI_WPCR0_HSICL                  0x00000200U              /*!< Invert the high-speed data signal on clock lane */
-#define DSI_WPCR0_HSIDL0                 0x00000400U              /*!< Invert the high-speed data signal on lane 1 */
-#define DSI_WPCR0_HSIDL1                 0x00000800U              /*!< Invert the high-speed data signal on lane 2 */
-#define DSI_WPCR0_FTXSMCL                0x00001000U              /*!< Force clock lane in TX stop mode */
-#define DSI_WPCR0_FTXSMDL                0x00002000U              /*!< Force data lanes in TX stop mode */
-#define DSI_WPCR0_CDOFFDL                0x00004000U              /*!< Contention detection OFF */
-#define DSI_WPCR0_TDDL                   0x00010000U              /*!< Turn Disable Data Lanes */
-#define DSI_WPCR0_PDEN                   0x00040000U              /*!< Pull-Down Enable */
-#define DSI_WPCR0_TCLKPREPEN             0x00080000U              /*!< Timer for t-CLKPREP Enable */
-#define DSI_WPCR0_TCLKZEROEN             0x00100000U              /*!< Timer for t-CLKZERO Enable */
-#define DSI_WPCR0_THSPREPEN              0x00200000U              /*!< Timer for t-HSPREP Enable */
-#define DSI_WPCR0_THSTRAILEN             0x00400000U              /*!< Timer for t-HSTRAIL Enable */
-#define DSI_WPCR0_THSZEROEN              0x00800000U              /*!< Timer for t-HSZERO Enable */
-#define DSI_WPCR0_TLPXDEN                0x01000000U              /*!< Timer for t-LPXD Enable */
-#define DSI_WPCR0_THSEXITEN              0x02000000U              /*!< Timer for t-HSEXIT Enable */
-#define DSI_WPCR0_TLPXCEN                0x04000000U              /*!< Timer for t-LPXC Enable */
-#define DSI_WPCR0_TCLKPOSTEN             0x08000000U              /*!< Timer for t-CLKPOST Enable */
-
-/*******************  Bit definition for DSI_WPCR1 register  ***************/
-#define DSI_WPCR1_HSTXDCL                0x00000003U              /*!< High-Speed Transmission Delay on Clock Lane */
-#define DSI_WPCR1_HSTXDCL0               0x00000001U
-#define DSI_WPCR1_HSTXDCL1               0x00000002U
-
-#define DSI_WPCR1_HSTXDDL                0x0000000CU              /*!< High-Speed Transmission Delay on Data Lane */
-#define DSI_WPCR1_HSTXDDL0               0x00000004U
-#define DSI_WPCR1_HSTXDDL1               0x00000008U
-
-#define DSI_WPCR1_LPSRCCL                0x000000C0U              /*!< Low-Power transmission Slew Rate Compensation on Clock Lane */
-#define DSI_WPCR1_LPSRCCL0               0x00000040U
-#define DSI_WPCR1_LPSRCCL1               0x00000080U
-
-#define DSI_WPCR1_LPSRCDL                0x00000300U              /*!< Low-Power transmission Slew Rate Compensation on Data Lane */
-#define DSI_WPCR1_LPSRCDL0               0x00000100U
-#define DSI_WPCR1_LPSRCDL1               0x00000200U
-
-#define DSI_WPCR1_SDDC                   0x00001000U              /*!< SDD Control */
-
-#define DSI_WPCR1_LPRXVCDL               0x0000C000U              /*!< Low-Power Reception V-IL Compensation on Data Lanes */
-#define DSI_WPCR1_LPRXVCDL0              0x00004000U
-#define DSI_WPCR1_LPRXVCDL1              0x00008000U
-
-#define DSI_WPCR1_HSTXSRCCL              0x00030000U              /*!< High-Speed Transmission Delay on Clock Lane */
-#define DSI_WPCR1_HSTXSRCCL0             0x00010000U
-#define DSI_WPCR1_HSTXSRCCL1             0x00020000U
-
-#define DSI_WPCR1_HSTXSRCDL              0x000C0000U              /*!< High-Speed Transmission Delay on Data Lane */
-#define DSI_WPCR1_HSTXSRCDL0             0x00040000U
-#define DSI_WPCR1_HSTXSRCDL1             0x00080000U
-
-#define DSI_WPCR1_FLPRXLPM               0x00400000U              /*!< Forces LP Receiver in Low-Power Mode */
-
-#define DSI_WPCR1_LPRXFT                 0x06000000U              /*!< Low-Power RX low-pass Filtering Tuning */
-#define DSI_WPCR1_LPRXFT0                0x02000000U
-#define DSI_WPCR1_LPRXFT1                0x04000000U
-
-/*******************  Bit definition for DSI_WPCR2 register  ***************/
-#define DSI_WPCR2_TCLKPREP               0x000000FFU              /*!< t-CLKPREP */
-#define DSI_WPCR2_TCLKPREP0              0x00000001U
-#define DSI_WPCR2_TCLKPREP1              0x00000002U
-#define DSI_WPCR2_TCLKPREP2              0x00000004U
-#define DSI_WPCR2_TCLKPREP3              0x00000008U
-#define DSI_WPCR2_TCLKPREP4              0x00000010U
-#define DSI_WPCR2_TCLKPREP5              0x00000020U
-#define DSI_WPCR2_TCLKPREP6              0x00000040U
-#define DSI_WPCR2_TCLKPREP7              0x00000080U
-
-#define DSI_WPCR2_TCLKZERO               0x0000FF00U              /*!< t-CLKZERO */
-#define DSI_WPCR2_TCLKZERO0              0x00000100U
-#define DSI_WPCR2_TCLKZERO1              0x00000200U
-#define DSI_WPCR2_TCLKZERO2              0x00000400U
-#define DSI_WPCR2_TCLKZERO3              0x00000800U
-#define DSI_WPCR2_TCLKZERO4              0x00001000U
-#define DSI_WPCR2_TCLKZERO5              0x00002000U
-#define DSI_WPCR2_TCLKZERO6              0x00004000U
-#define DSI_WPCR2_TCLKZERO7              0x00008000U
-
-#define DSI_WPCR2_THSPREP                0x00FF0000U              /*!< t-HSPREP */
-#define DSI_WPCR2_THSPREP0               0x00010000U
-#define DSI_WPCR2_THSPREP1               0x00020000U
-#define DSI_WPCR2_THSPREP2               0x00040000U
-#define DSI_WPCR2_THSPREP3               0x00080000U
-#define DSI_WPCR2_THSPREP4               0x00100000U
-#define DSI_WPCR2_THSPREP5               0x00200000U
-#define DSI_WPCR2_THSPREP6               0x00400000U
-#define DSI_WPCR2_THSPREP7               0x00800000U
-
-#define DSI_WPCR2_THSTRAIL               0xFF000000U              /*!< t-HSTRAIL */
-#define DSI_WPCR2_THSTRAIL0              0x01000000U
-#define DSI_WPCR2_THSTRAIL1              0x02000000U
-#define DSI_WPCR2_THSTRAIL2              0x04000000U
-#define DSI_WPCR2_THSTRAIL3              0x08000000U
-#define DSI_WPCR2_THSTRAIL4              0x10000000U
-#define DSI_WPCR2_THSTRAIL5              0x20000000U
-#define DSI_WPCR2_THSTRAIL6              0x40000000U
-#define DSI_WPCR2_THSTRAIL7              0x80000000U
-
-/*******************  Bit definition for DSI_WPCR3 register  ***************/
-#define DSI_WPCR3_THSZERO                0x000000FFU              /*!< t-HSZERO */
-#define DSI_WPCR3_THSZERO0               0x00000001U
-#define DSI_WPCR3_THSZERO1               0x00000002U
-#define DSI_WPCR3_THSZERO2               0x00000004U
-#define DSI_WPCR3_THSZERO3               0x00000008U
-#define DSI_WPCR3_THSZERO4               0x00000010U
-#define DSI_WPCR3_THSZERO5               0x00000020U
-#define DSI_WPCR3_THSZERO6               0x00000040U
-#define DSI_WPCR3_THSZERO7               0x00000080U
-
-#define DSI_WPCR3_TLPXD                  0x0000FF00U              /*!< t-LPXD */
-#define DSI_WPCR3_TLPXD0                 0x00000100U
-#define DSI_WPCR3_TLPXD1                 0x00000200U
-#define DSI_WPCR3_TLPXD2                 0x00000400U
-#define DSI_WPCR3_TLPXD3                 0x00000800U
-#define DSI_WPCR3_TLPXD4                 0x00001000U
-#define DSI_WPCR3_TLPXD5                 0x00002000U
-#define DSI_WPCR3_TLPXD6                 0x00004000U
-#define DSI_WPCR3_TLPXD7                 0x00008000U
-
-#define DSI_WPCR3_THSEXIT                0x00FF0000U              /*!< t-HSEXIT */
-#define DSI_WPCR3_THSEXIT0               0x00010000U
-#define DSI_WPCR3_THSEXIT1               0x00020000U
-#define DSI_WPCR3_THSEXIT2               0x00040000U
-#define DSI_WPCR3_THSEXIT3               0x00080000U
-#define DSI_WPCR3_THSEXIT4               0x00100000U
-#define DSI_WPCR3_THSEXIT5               0x00200000U
-#define DSI_WPCR3_THSEXIT6               0x00400000U
-#define DSI_WPCR3_THSEXIT7               0x00800000U
-
-#define DSI_WPCR3_TLPXC                  0xFF000000U              /*!< t-LPXC */
-#define DSI_WPCR3_TLPXC0                 0x01000000U
-#define DSI_WPCR3_TLPXC1                 0x02000000U
-#define DSI_WPCR3_TLPXC2                 0x04000000U
-#define DSI_WPCR3_TLPXC3                 0x08000000U
-#define DSI_WPCR3_TLPXC4                 0x10000000U
-#define DSI_WPCR3_TLPXC5                 0x20000000U
-#define DSI_WPCR3_TLPXC6                 0x40000000U
-#define DSI_WPCR3_TLPXC7                 0x80000000U
-
-/*******************  Bit definition for DSI_WPCR4 register  ***************/
-#define DSI_WPCR4_TCLKPOST               0x000000FFU              /*!< t-CLKPOST */
-#define DSI_WPCR4_TCLKPOST0              0x00000001U
-#define DSI_WPCR4_TCLKPOST1              0x00000002U
-#define DSI_WPCR4_TCLKPOST2              0x00000004U
-#define DSI_WPCR4_TCLKPOST3              0x00000008U
-#define DSI_WPCR4_TCLKPOST4              0x00000010U
-#define DSI_WPCR4_TCLKPOST5              0x00000020U
-#define DSI_WPCR4_TCLKPOST6              0x00000040U
-#define DSI_WPCR4_TCLKPOST7              0x00000080U
-
-/*******************  Bit definition for DSI_WRPCR register  ***************/
-#define DSI_WRPCR_PLLEN                  0x00000001U              /*!< PLL Enable */
-#define DSI_WRPCR_PLL_NDIV               0x000001FCU              /*!< PLL Loop Division Factor */
-#define DSI_WRPCR_PLL_NDIV0              0x00000004U
-#define DSI_WRPCR_PLL_NDIV1              0x00000008U
-#define DSI_WRPCR_PLL_NDIV2              0x00000010U
-#define DSI_WRPCR_PLL_NDIV3              0x00000020U
-#define DSI_WRPCR_PLL_NDIV4              0x00000040U
-#define DSI_WRPCR_PLL_NDIV5              0x00000080U
-#define DSI_WRPCR_PLL_NDIV6              0x00000100U
-
-#define DSI_WRPCR_PLL_IDF                0x00007800U              /*!< PLL Input Division Factor */
-#define DSI_WRPCR_PLL_IDF0               0x00000800U
-#define DSI_WRPCR_PLL_IDF1               0x00001000U
-#define DSI_WRPCR_PLL_IDF2               0x00002000U
-#define DSI_WRPCR_PLL_IDF3               0x00004000U
-
-#define DSI_WRPCR_PLL_ODF                0x00030000U              /*!< PLL Output Division Factor */
-#define DSI_WRPCR_PLL_ODF0               0x00010000U
-#define DSI_WRPCR_PLL_ODF1               0x00020000U
-
-#define DSI_WRPCR_REGEN                  0x01000000U              /*!< Regulator Enable */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || \
-                                       ((__INSTANCE__) == ADC2) || \
-                                       ((__INSTANCE__) == ADC3))
-
-/******************************* CAN Instances ********************************/
-#define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) || \
-                                           ((__INSTANCE__) == CAN2) || \
-									       ((__INSTANCE__) == CAN3))
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)
-
-/******************************* DAC Instances ********************************/
-#define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC)
-
-/******************************* DCMI Instances *******************************/
-#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
-
-/****************************** DFSDM Instances *******************************/
-#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
-                                                ((INSTANCE) == DFSDM1_Filter1) || \
-                                                ((INSTANCE) == DFSDM1_Filter2) || \
-                                                ((INSTANCE) == DFSDM1_Filter3))
-
-#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
-                                                 ((INSTANCE) == DFSDM1_Channel1) || \
-                                                 ((INSTANCE) == DFSDM1_Channel2) || \
-                                                 ((INSTANCE) == DFSDM1_Channel3) || \
-                                                 ((INSTANCE) == DFSDM1_Channel4) || \
-                                                 ((INSTANCE) == DFSDM1_Channel5) || \
-                                                 ((INSTANCE) == DFSDM1_Channel6) || \
-                                                 ((INSTANCE) == DFSDM1_Channel7))
-
-/******************************* DMA2D Instances *******************************/
-#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
-
-/******************************** DMA Instances *******************************/
-#define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) || \
-                                              ((__INSTANCE__) == DMA1_Stream1) || \
-                                              ((__INSTANCE__) == DMA1_Stream2) || \
-                                              ((__INSTANCE__) == DMA1_Stream3) || \
-                                              ((__INSTANCE__) == DMA1_Stream4) || \
-                                              ((__INSTANCE__) == DMA1_Stream5) || \
-                                              ((__INSTANCE__) == DMA1_Stream6) || \
-                                              ((__INSTANCE__) == DMA1_Stream7) || \
-                                              ((__INSTANCE__) == DMA2_Stream0) || \
-                                              ((__INSTANCE__) == DMA2_Stream1) || \
-                                              ((__INSTANCE__) == DMA2_Stream2) || \
-                                              ((__INSTANCE__) == DMA2_Stream3) || \
-                                              ((__INSTANCE__) == DMA2_Stream4) || \
-                                              ((__INSTANCE__) == DMA2_Stream5) || \
-                                              ((__INSTANCE__) == DMA2_Stream6) || \
-                                              ((__INSTANCE__) == DMA2_Stream7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
-                                            ((__INSTANCE__) == GPIOB) || \
-                                            ((__INSTANCE__) == GPIOC) || \
-                                            ((__INSTANCE__) == GPIOD) || \
-                                            ((__INSTANCE__) == GPIOE) || \
-                                            ((__INSTANCE__) == GPIOF) || \
-                                            ((__INSTANCE__) == GPIOG) || \
-                                            ((__INSTANCE__) == GPIOH) || \
-                                            ((__INSTANCE__) == GPIOI) || \
-                                            ((__INSTANCE__) == GPIOJ) || \
-                                            ((__INSTANCE__) == GPIOK))
-										
-#define IS_GPIO_AF_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == GPIOA) || \
-                                             ((__INSTANCE__) == GPIOB) || \
-                                             ((__INSTANCE__) == GPIOC) || \
-                                             ((__INSTANCE__) == GPIOD) || \
-                                             ((__INSTANCE__) == GPIOE) || \
-                                             ((__INSTANCE__) == GPIOF) || \
-                                             ((__INSTANCE__) == GPIOG) || \
-                                             ((__INSTANCE__) == GPIOH) || \
-                                             ((__INSTANCE__) == GPIOI) || \
-                                             ((__INSTANCE__) == GPIOJ) || \
-                                             ((__INSTANCE__) == GPIOK))
-
-/****************************** CEC Instances *********************************/
-#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
-
-/****************************** QSPI Instances *********************************/
-#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
-
-                                        
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
-                                           ((__INSTANCE__) == I2C2) || \
-                                           ((__INSTANCE__) == I2C3) || \
-                                           ((__INSTANCE__) == I2C4))
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == SPI1) || \
-                                            ((__INSTANCE__) == SPI2) || \
-                                            ((__INSTANCE__) == SPI3))
-
-/******************************* LPTIM Instances ********************************/
-#define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
-
-/****************************** LTDC Instances ********************************/
-#define IS_LTDC_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == LTDC)
-
-/****************************** MDIOS Instances ********************************/
-#define IS_MDIOS_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == MDIOS)
-
-/****************************** MDIOS Instances ********************************/
-#define IS_JPEG_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == JPEG)
-
-
-/******************************* RNG Instances ********************************/
-#define IS_RNG_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == RNG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == RTC)
-
-/******************************* SAI Instances ********************************/
-#define IS_SAI_ALL_INSTANCE(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) || \
-                                         ((__PERIPH__) == SAI1_Block_B) || \
-                                         ((__PERIPH__) == SAI2_Block_A) || \
-                                         ((__PERIPH__) == SAI2_Block_B))
-/* Legacy define */
-#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
-
-/******************************** SDMMC Instances *******************************/
-#define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SDMMC1) || \
-                                             ((__INSTANCE__) == SDMMC2))
-
-/****************************** SPDIFRX Instances *********************************/
-#define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)
-                                     
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
-                                           ((__INSTANCE__) == SPI2) || \
-                                           ((__INSTANCE__) == SPI3) || \
-                                           ((__INSTANCE__) == SPI4) || \
-                                           ((__INSTANCE__) == SPI5) || \
-                                           ((__INSTANCE__) == SPI6))
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1)   || \
-                                   ((__INSTANCE__) == TIM2)   || \
-                                   ((__INSTANCE__) == TIM3)   || \
-                                   ((__INSTANCE__) == TIM4)   || \
-                                   ((__INSTANCE__) == TIM5)   || \
-                                   ((__INSTANCE__) == TIM6)   || \
-                                   ((__INSTANCE__) == TIM7)   || \
-                                   ((__INSTANCE__) == TIM8)   || \
-                                   ((__INSTANCE__) == TIM9)   || \
-                                   ((__INSTANCE__) == TIM10)  || \
-                                   ((__INSTANCE__) == TIM11)  || \
-                                   ((__INSTANCE__) == TIM12)  || \
-                                   ((__INSTANCE__) == TIM13)  || \
-                                   ((__INSTANCE__) == TIM14))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1)  || \
-                                         ((__INSTANCE__) == TIM2)  || \
-                                         ((__INSTANCE__) == TIM3)  || \
-                                         ((__INSTANCE__) == TIM4)  || \
-                                         ((__INSTANCE__) == TIM5)  || \
-                                         ((__INSTANCE__) == TIM8)  || \
-                                         ((__INSTANCE__) == TIM9)  || \
-                                         ((__INSTANCE__) == TIM10) || \
-                                         ((__INSTANCE__) == TIM11) || \
-                                         ((__INSTANCE__) == TIM12) || \
-                                         ((__INSTANCE__) == TIM13) || \
-                                         ((__INSTANCE__) == TIM14))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1)  || \
-                                         ((__INSTANCE__) == TIM2)  || \
-                                         ((__INSTANCE__) == TIM3)  || \
-                                         ((__INSTANCE__) == TIM4)  || \
-                                         ((__INSTANCE__) == TIM5)  || \
-                                         ((__INSTANCE__) == TIM8)  || \
-                                         ((__INSTANCE__) == TIM9)  || \
-                                         ((__INSTANCE__) == TIM12))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1) || \
-                                         ((__INSTANCE__) == TIM2) || \
-                                         ((__INSTANCE__) == TIM3) || \
-                                         ((__INSTANCE__) == TIM4) || \
-                                         ((__INSTANCE__) == TIM5) || \
-                                         ((__INSTANCE__) == TIM8))
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
-                                       ((__INSTANCE__) == TIM2) || \
-                                       ((__INSTANCE__) == TIM3) || \
-                                       ((__INSTANCE__) == TIM4) || \
-                                       ((__INSTANCE__) == TIM5) || \
-                                       ((__INSTANCE__) == TIM8))
-                                       
-/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
-#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \
-                                       (((__INSTANCE__) == TIM1)    || \
-                                        ((__INSTANCE__) == TIM8))
-
-/****************** TIM Instances : supporting OCxREF clear *******************/
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\
-                                  (((__INSTANCE__) == TIM1)    || \
-                                   ((__INSTANCE__) == TIM2)    || \
-                                   ((__INSTANCE__) == TIM3)    || \
-                                   ((__INSTANCE__) == TIM4)    || \
-                                   ((__INSTANCE__) == TIM8))
-
-/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\
-                                                 (((__INSTANCE__) == TIM1)    || \
-                                                  ((__INSTANCE__) == TIM2)    || \
-                                                  ((__INSTANCE__) == TIM3)    || \
-                                                  ((__INSTANCE__) == TIM4)    || \
-                                                  ((__INSTANCE__) == TIM5)    || \
-                                                  ((__INSTANCE__) == TIM8))
- 
-/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\
-                                                   (((__INSTANCE__) == TIM1)    || \
-                                                    ((__INSTANCE__) == TIM2)    || \
-                                                    ((__INSTANCE__) == TIM3)    || \
-                                                    ((__INSTANCE__) == TIM4)    || \
-                                                    ((__INSTANCE__) == TIM5)    || \
-                                                    ((__INSTANCE__) == TIM8))
-/****************** TIM Instances : at least 5 capture/compare channels *******/
-#define IS_TIM_CC5_INSTANCE(__INSTANCE__)\
-  (((__INSTANCE__) == TIM1)    || \
-   ((__INSTANCE__) == TIM8) )
-
-/****************** TIM Instances : at least 6 capture/compare channels *******/
-#define IS_TIM_CC6_INSTANCE(__INSTANCE__)\
-  (((__INSTANCE__) == TIM1)    || \
-   ((__INSTANCE__) == TIM8))
-
-                                       
-/******************** TIM Instances : Advanced-control timers *****************/
-#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
-                                            ((__INSTANCE__) == TIM8))
-
-/****************** TIM Instances : supporting 2 break inputs *****************/
-#define IS_TIM_BREAK_INSTANCE(__INSTANCE__)\
-  (((__INSTANCE__) == TIM1)    || \
-   ((__INSTANCE__) == TIM8))
-   
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1) || \
-                                         ((__INSTANCE__) == TIM2) || \
-                                         ((__INSTANCE__) == TIM3) || \
-                                         ((__INSTANCE__) == TIM4) || \
-                                         ((__INSTANCE__) == TIM5) || \
-                                         ((__INSTANCE__) == TIM8))
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
-                                       ((__INSTANCE__) == TIM2) || \
-                                       ((__INSTANCE__) == TIM3) || \
-                                       ((__INSTANCE__) == TIM4) || \
-                                       ((__INSTANCE__) == TIM5) || \
-                                       ((__INSTANCE__) == TIM6) || \
-                                       ((__INSTANCE__) == TIM7) || \
-                                       ((__INSTANCE__) == TIM8))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
-                                          ((__INSTANCE__) == TIM2) || \
-                                          ((__INSTANCE__) == TIM3) || \
-                                          ((__INSTANCE__) == TIM4) || \
-                                          ((__INSTANCE__) == TIM5) || \
-                                          ((__INSTANCE__) == TIM8))
-
-/************ TIM Instances : DMA requests generation (COMDE) *****************/
-#define IS_TIM_CCDMA_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1) || \
-                                          ((__INSTANCE__) == TIM2) || \
-                                          ((__INSTANCE__) == TIM3) || \
-                                          ((__INSTANCE__) == TIM4) || \
-                                          ((__INSTANCE__) == TIM5) || \
-                                          ((__INSTANCE__) == TIM8)) 
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1) || \
-                                             ((__INSTANCE__) == TIM2) || \
-                                             ((__INSTANCE__) == TIM3) || \
-                                             ((__INSTANCE__) == TIM4) || \
-                                             ((__INSTANCE__) == TIM5) || \
-                                             ((__INSTANCE__) == TIM8))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
-                                          ((__INSTANCE__) == TIM2) || \
-                                          ((__INSTANCE__) == TIM3) || \
-                                          ((__INSTANCE__) == TIM4) || \
-                                          ((__INSTANCE__) == TIM5) || \
-                                          ((__INSTANCE__) == TIM6) || \
-                                          ((__INSTANCE__) == TIM7) || \
-                                          ((__INSTANCE__) == TIM8) || \
-                                          ((__INSTANCE__) == TIM13) || \
-                                          ((__INSTANCE__) == TIM14))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
-                                         ((__INSTANCE__) == TIM2) || \
-                                         ((__INSTANCE__) == TIM3) || \
-                                         ((__INSTANCE__) == TIM4) || \
-                                         ((__INSTANCE__) == TIM5) || \
-                                         ((__INSTANCE__) == TIM8) || \
-                                         ((__INSTANCE__) == TIM9) || \
-                                         ((__INSTANCE__) == TIM12))
-
-/********************** TIM Instances : 32 bit Counter ************************/
-#define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__)(((__INSTANCE__) == TIM2) || \
-                                              ((__INSTANCE__) == TIM5))
-
-/***************** TIM Instances : external trigger input available ************/
-#define IS_TIM_ETR_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1) || \
-                                        ((__INSTANCE__) == TIM2) || \
-                                        ((__INSTANCE__) == TIM3) || \
-                                        ((__INSTANCE__) == TIM4) || \
-                                        ((__INSTANCE__) == TIM5) || \
-                                        ((__INSTANCE__) == TIM8))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2)  || \
-                                         ((__INSTANCE__) == TIM5)  || \
-                                         ((__INSTANCE__) == TIM11))
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \
-    ((((__INSTANCE__) == TIM1) &&                  \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM2) &&                   \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM3) &&                   \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM4) &&                   \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM5) &&                   \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM8) &&                   \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM9) &&                   \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM10) &&                  \
-     (((__CHANNEL__) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM11) &&                  \
-     (((__CHANNEL__) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM12) &&                  \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
-      ((__CHANNEL__) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM13) &&                  \
-     (((__CHANNEL__) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((__INSTANCE__) == TIM14) &&                  \
-     (((__CHANNEL__) == TIM_CHANNEL_1))))
-
-/************ TIM Instances : complementary output(s) available ***************/
-#define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \
-   ((((__INSTANCE__) == TIM1) &&                    \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||           \
-      ((__CHANNEL__) == TIM_CHANNEL_2) ||           \
-      ((__CHANNEL__) == TIM_CHANNEL_3)))            \
-    ||                                          \
-    (((__INSTANCE__) == TIM8) &&                    \
-     (((__CHANNEL__) == TIM_CHANNEL_1) ||           \
-      ((__CHANNEL__) == TIM_CHANNEL_2) ||           \
-      ((__CHANNEL__) == TIM_CHANNEL_3))))
-
-/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
-#define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\
-  (((__INSTANCE__) == TIM1)    || \
-   ((__INSTANCE__) == TIM8) )
-
-/****************** TIM Instances : supporting synchronization ****************/
-#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
-    (((__INSTANCE__) == TIM1)    || \
-     ((__INSTANCE__) == TIM2)    || \
-     ((__INSTANCE__) == TIM3)    || \
-     ((__INSTANCE__) == TIM4)    || \
-     ((__INSTANCE__) == TIM5)    || \
-     ((__INSTANCE__) == TIM6)    || \
-     ((__INSTANCE__) == TIM7)    || \
-     ((__INSTANCE__) == TIM8))  
-      
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
-                                     ((__INSTANCE__) == USART2) || \
-                                     ((__INSTANCE__) == USART3) || \
-                                     ((__INSTANCE__) == USART6))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
-                                    ((__INSTANCE__) == USART2) || \
-                                    ((__INSTANCE__) == USART3) || \
-                                    ((__INSTANCE__) == UART4)  || \
-                                    ((__INSTANCE__) == UART5)  || \
-                                    ((__INSTANCE__) == USART6) || \
-                                    ((__INSTANCE__) == UART7)  || \
-                                    ((__INSTANCE__) == UART8))
-
-/****************** UART Instances : Driver Enable *****************/
-#define IS_UART_DRIVER_ENABLE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
-                                    ((__INSTANCE__) == USART2) || \
-                                    ((__INSTANCE__) == USART3) || \
-                                    ((__INSTANCE__) == UART4)  || \
-                                    ((__INSTANCE__) == UART5)  || \
-                                    ((__INSTANCE__) == USART6) || \
-                                    ((__INSTANCE__) == UART7)  || \
-                                    ((__INSTANCE__) == UART8))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
-                                    ((__INSTANCE__) == USART2) || \
-                                    ((__INSTANCE__) == USART3) || \
-                                    ((__INSTANCE__) == UART4)  || \
-                                    ((__INSTANCE__) == UART5)  || \
-                                    ((__INSTANCE__) == USART6) || \
-                                    ((__INSTANCE__) == UART7)  || \
-                                    ((__INSTANCE__) == UART8))
-
-/********************* UART Instances : Smart card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
-                                         ((__INSTANCE__) == USART2) || \
-                                         ((__INSTANCE__) == USART3) || \
-                                         ((__INSTANCE__) == USART6))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
-                                    ((__INSTANCE__) == USART2) || \
-                                    ((__INSTANCE__) == USART3) || \
-                                    ((__INSTANCE__) == UART4)  || \
-                                    ((__INSTANCE__) == UART5)  || \
-                                    ((__INSTANCE__) == USART6) || \
-                                    ((__INSTANCE__) == UART7)  || \
-                                    ((__INSTANCE__) == UART8))     
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == WWDG)
-
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32F7xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */
-/*  product lines within the same STM32F7 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-#define HASH_RNG_IRQn              RNG_IRQn
-
-/* Aliases for __IRQHandler */
-#define HASH_RNG_IRQHandler        RNG_IRQHandler
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32F769xx_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/cmsis/stm32f7xx.h b/stmhal/cmsis/stm32f7xx.h
deleted file mode 100644
index ae2a4d899a..0000000000
--- a/stmhal/cmsis/stm32f7xx.h
+++ /dev/null
@@ -1,230 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx.h
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   CMSIS STM32F7xx Device Peripheral Access Layer Header File.
-  *
-  *          The file is the unique include file that the application programmer
-  *          is using in the C source code, usually in main.c. This file contains:
-  *           - Configuration section that allows to select:
-  *              - The STM32F7xx device used in the target application
-  *              - To use or not the peripheral's drivers in application code(i.e.
-  *                code will be based on direct access to peripheral's registers
-  *                rather than drivers API), this option is controlled by
-  *                "#define USE_HAL_DRIVER"
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f7xx
-  * @{
-  */
-
-#ifndef __STM32F7xx_H
-#define __STM32F7xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-
-/** @addtogroup Library_configuration_section
-  * @{
-  */
-
-/**
-  * @brief STM32 Family
-  */
-#if !defined  (STM32F7)
-#define STM32F7
-#endif /* STM32F7 */
-
-/* Uncomment the line below according to the target STM32 device used in your
-   application
-  */
-#if !defined (STM32F756xx) && !defined (STM32F746xx) && !defined (STM32F745xx) && !defined (STM32F767xx) && \
-    !defined (STM32F769xx) && !defined (STM32F777xx) && !defined (STM32F779xx) && !defined (STM32F722xx) && \
-	!defined (STM32F723xx) && !defined (STM32F732xx) && !defined (STM32F733xx)
-  /* #define STM32F756xx */   /*!< STM32F756VG, STM32F756ZG, STM32F756ZG, STM32F756IG, STM32F756BG,
-                                   STM32F756NG Devices */
-  /* #define STM32F746xx */   /*!< STM32F746VE, STM32F746VG, STM32F746ZE, STM32F746ZG, STM32F746IE, STM32F746IG,
-                                   STM32F746BE, STM32F746BG, STM32F746NE, STM32F746NG Devices */
-  /* #define STM32F745xx */   /*!< STM32F745VE, STM32F745VG, STM32F745ZG, STM32F745ZE, STM32F745IE, STM32F745IG Devices */
-  /* #define STM32F765xx */   /*!< STM32F765BI, STM32F765BG, STM32F765NI, STM32F765NG, STM32F765II, STM32F765IG,
-                                   STM32F765ZI, STM32F765ZG, STM32F765VI, STM32F765VG Devices */
-  /* #define STM32F767xx */   /*!< STM32F767BG, STM32F767BI, STM32F767IG, STM32F767II, STM32F767NG, STM32F767NI,
-                                   STM32F767VG, STM32F767VI, STM32F767ZG, STM32F767ZI Devices */
-  /* #define STM32F769xx */   /*!< STM32F769AG, STM32F769AI, STM32F769BG, STM32F769BI, STM32F769IG, STM32F769II,
-                                   STM32F769NG, STM32F769NI, STM32F768AI Devices */
-  /* #define STM32F777xx */   /*!< STM32F777VI, STM32F777ZI, STM32F777II, STM32F777BI, STM32F777NI Devices */
-  /* #define STM32F779xx */   /*!< STM32F779II, STM32F779BI, STM32F779NI, STM32F779AI, STM32F778AI Devices */
-  /* #define STM32F722xx */   /*!< STM32F722IE, STM32F722ZE, STM32F722VE, STM32F722RE, STM32F722IC, STM32F722ZC,
-                                   STM32F722VC, STM32F722RC Devices */
-  /* #define STM32F723xx */   /*!< STM32F723IE, STM32F723ZE, STM32F723VE, STM32F723IC, STM32F723ZC, STM32F723VC Devices */
-  /* #define STM32F732xx */   /*!< STM32F732IE, STM32F732ZE, STM32F732VE, STM32F732RE Devices */
-  /* #define STM32F733xx */   /*!< STM32F733IE, STM32F733ZE, STM32F733VE Devices */
-#endif
-
-/*  Tip: To avoid modifying this file each time you need to switch between these
-        devices, you can define the device in your toolchain compiler preprocessor.
-  */
-
-#if !defined  (USE_HAL_DRIVER)
-/**
- * @brief Comment the line below if you will not use the peripherals drivers.
-   In this case, these drivers will not be included and the application code will
-   be based on direct access to peripherals registers
-   */
-  /*#define USE_HAL_DRIVER */
-#endif /* USE_HAL_DRIVER */
-
-/**
-  * @brief CMSIS Device version number V1.1.2
-  */
-#define __STM32F7_CMSIS_VERSION_MAIN   (0x01) /*!< [31:24] main version */
-#define __STM32F7_CMSIS_VERSION_SUB1   (0x01) /*!< [23:16] sub1 version */
-#define __STM32F7_CMSIS_VERSION_SUB2   (0x02) /*!< [15:8]  sub2 version */
-#define __STM32F7_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
-#define __STM32F7_CMSIS_VERSION        ((__STM32F7_CMSIS_VERSION_MAIN << 24)\
-                                       |(__STM32F7_CMSIS_VERSION_SUB1 << 16)\
-                                       |(__STM32F7_CMSIS_VERSION_SUB2 << 8 )\
-                                       |(__STM32F7_CMSIS_VERSION))
-/**
-  * @}
-  */
-
-/** @addtogroup Device_Included
-  * @{
-  */
-#if defined(STM32F722xx)
-  #include "stm32f722xx.h"
-#elif defined(STM32F723xx)
-  #include "stm32f723xx.h"
-#elif defined(STM32F732xx)
-  #include "stm32f732xx.h"
-#elif defined(STM32F733xx)
-  #include "stm32f733xx.h"
-#elif defined(STM32F756xx)
-  #include "stm32f756xx.h"
-#elif defined(STM32F746xx)
-  #include "stm32f746xx.h"
-#elif defined(STM32F745xx)
-  #include "stm32f745xx.h"
-#elif defined(STM32F765xx)
-  #include "stm32f765xx.h"
-#elif defined(STM32F767xx)
-  #include "stm32f767xx.h"
-#elif defined(STM32F769xx)
-  #include "stm32f769xx.h"
-#elif defined(STM32F777xx)
-  #include "stm32f777xx.h"
-#elif defined(STM32F779xx)
-  #include "stm32f779xx.h"
-#else
- #error "Please select first the target STM32F7xx device used in your application (in stm32f7xx.h file)"
-#endif
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_types
-  * @{
-  */
-typedef enum
-{
-  RESET = 0,
-  SET = !RESET
-} FlagStatus, ITStatus;
-
-typedef enum
-{
-  DISABLE = 0,
-  ENABLE = !DISABLE
-} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum
-{
-  ERROR = 0,
-  SUCCESS = !ERROR
-} ErrorStatus;
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macro
-  * @{
-  */
-#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
-
-#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
-
-#define READ_BIT(REG, BIT)    ((REG) & (BIT))
-
-#define CLEAR_REG(REG)        ((REG) = (0x0))
-
-#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
-
-#define READ_REG(REG)         ((REG))
-
-#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
-
-#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))
-
-/**
-  * @}
-  */
-
-#ifdef USE_HAL_DRIVER
-  #include "stm32f7xx_hal_conf.h"
-#endif /* USE_HAL_DRIVER */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32F7xx_H */
-
-/**
-  * @}
-  */
-
-  /**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/cmsis/stm32l476xx.h b/stmhal/cmsis/stm32l476xx.h
deleted file mode 100644
index 14ba51eec5..0000000000
--- a/stmhal/cmsis/stm32l476xx.h
+++ /dev/null
@@ -1,10136 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l476xx.h
-  * @author  MCD Application Team
-  * @version V1.0.3
-  * @date    29-January-2016
-  * @brief   CMSIS STM32L476xx Device Peripheral Access Layer Header File.
-  *
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral's registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS_Device
-  * @{
-  */
-
-/** @addtogroup stm32l476xx
-  * @{
-  */
-
-#ifndef __STM32L476xx_H
-#define __STM32L476xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-
-/**
-  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
-   */
-#define __CM4_REV                 0x0001  /*!< Cortex-M4 revision r0p1                       */
-#define __MPU_PRESENT             1       /*!< STM32L4XX provides an MPU                     */
-#define __NVIC_PRIO_BITS          4       /*!< STM32L4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1       /*!< FPU present                                   */
-
-/**
-  * @}
-  */
-
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32L4XX Interrupt Number Definition, according to the selected device
- *        in @ref Library_configuration_section
- */
-typedef enum
-{
-/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Cortex-M4 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M4 Hard Fault Interrupt                                  */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
-  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
-/******  STM32 specific Interrupt Numbers **********************************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
-  PVD_PVM_IRQn                = 1,      /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts    */
-  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
-  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                                   */
-  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                                   */
-  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                                   */
-  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                                   */
-  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                                   */
-  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                                   */
-  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                                   */
-  ADC1_2_IRQn                 = 18,     /*!< ADC1, ADC2 SAR global Interrupts                                  */
-  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
-  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
-  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
-  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
-  TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break interrupt and TIM15 global interrupt                   */
-  TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM16 global interrupt                  */
-  TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM17 global interrupt */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
-  DFSDM3_IRQn                 = 42,     /*!< SD Filter 3 global Interrupt                                      */
-  TIM8_BRK_IRQn               = 43,     /*!< TIM8 Break Interrupt                                              */
-  TIM8_UP_IRQn                = 44,     /*!< TIM8 Update Interrupt                                             */
-  TIM8_TRG_COM_IRQn           = 45,     /*!< TIM8 Trigger and Commutation Interrupt                            */
-  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
-  ADC3_IRQn                   = 47,     /*!< ADC3 global  Interrupt                                            */
-  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
-  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
-  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
-  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
-  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
-  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
-  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
-  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                                   */
-  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                                   */
-  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                                   */
-  DMA2_Channel4_IRQn          = 59,     /*!< DMA2 Channel 4 global Interrupt                                   */
-  DMA2_Channel5_IRQn          = 60,     /*!< DMA2 Channel 5 global Interrupt                                   */
-  DFSDM0_IRQn                 = 61,     /*!< SD Filter 0 global Interrupt                                      */
-  DFSDM1_IRQn                 = 62,     /*!< SD Filter 1 global Interrupt                                      */
-  DFSDM2_IRQn                 = 63,     /*!< SD Filter 2 global Interrupt                                      */
-  COMP_IRQn                   = 64,     /*!< COMP1 and COMP2 Interrupts                                        */
-  LPTIM1_IRQn                 = 65,     /*!< LP TIM1 interrupt                                                 */
-  LPTIM2_IRQn                 = 66,     /*!< LP TIM2 interrupt                                                 */
-  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
-  DMA2_Channel6_IRQn          = 68,     /*!< DMA2 Channel 6 global interrupt                                   */
-  DMA2_Channel7_IRQn          = 69,     /*!< DMA2 Channel 7 global interrupt                                   */
-  LPUART1_IRQn                = 70,     /*!< LP UART1 interrupt                                                */
-  QUADSPI_IRQn                = 71,     /*!< Quad SPI global interrupt                                         */
-  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
-  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
-  SAI1_IRQn                   = 74,     /*!< Serial Audio Interface 1 global interrupt                         */
-  SAI2_IRQn                   = 75,     /*!< Serial Audio Interface 2 global interrupt                         */
-  SWPMI1_IRQn                 = 76,     /*!< Serial Wire Interface 1 global interrupt                          */
-  TSC_IRQn                    = 77,     /*!< Touch Sense Controller global interrupt                           */
-  LCD_IRQn                    = 78,     /*!< LCD global interrupt                                              */
-  RNG_IRQn                    = 80,     /*!< RNG global interrupt                                              */
-  FPU_IRQn                    = 81      /*!< FPU global interrupt                                              */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
-#include "system_stm32l4xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */
-
-/**
-  * @brief Analog to Digital Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< ADC interrupt and status register,             Address offset: 0x00 */
-  __IO uint32_t IER;          /*!< ADC interrupt enable register,                 Address offset: 0x04 */
-  __IO uint32_t CR;           /*!< ADC control register,                          Address offset: 0x08 */
-  __IO uint32_t CFGR;         /*!< ADC configuration register 1,                  Address offset: 0x0C */
-  __IO uint32_t CFGR2;        /*!< ADC configuration register 2,                  Address offset: 0x10 */
-  __IO uint32_t SMPR1;        /*!< ADC sampling time register 1,                  Address offset: 0x14 */
-  __IO uint32_t SMPR2;        /*!< ADC sampling time register 2,                  Address offset: 0x18 */
-       uint32_t RESERVED1;    /*!< Reserved,                                                      0x1C */
-  __IO uint32_t TR1;          /*!< ADC analog watchdog 1 threshold register,      Address offset: 0x20 */
-  __IO uint32_t TR2;          /*!< ADC analog watchdog 2 threshold register,      Address offset: 0x24 */
-  __IO uint32_t TR3;          /*!< ADC analog watchdog 3 threshold register,      Address offset: 0x28 */
-       uint32_t RESERVED2;    /*!< Reserved,                                                      0x2C */
-  __IO uint32_t SQR1;         /*!< ADC group regular sequencer register 1,        Address offset: 0x30 */
-  __IO uint32_t SQR2;         /*!< ADC group regular sequencer register 2,        Address offset: 0x34 */
-  __IO uint32_t SQR3;         /*!< ADC group regular sequencer register 3,        Address offset: 0x38 */
-  __IO uint32_t SQR4;         /*!< ADC group regular sequencer register 4,        Address offset: 0x3C */
-  __IO uint32_t DR;           /*!< ADC group regular data register,               Address offset: 0x40 */
-       uint32_t RESERVED3;    /*!< Reserved,                                                      0x44 */
-       uint32_t RESERVED4;    /*!< Reserved,                                                      0x48 */
-  __IO uint32_t JSQR;         /*!< ADC group injected sequencer register,         Address offset: 0x4C */
-       uint32_t RESERVED5[4]; /*!< Reserved,                                               0x50 - 0x5C */
-  __IO uint32_t OFR1;         /*!< ADC offset register 1,                         Address offset: 0x60 */
-  __IO uint32_t OFR2;         /*!< ADC offset register 2,                         Address offset: 0x64 */
-  __IO uint32_t OFR3;         /*!< ADC offset register 3,                         Address offset: 0x68 */
-  __IO uint32_t OFR4;         /*!< ADC offset register 4,                         Address offset: 0x6C */
-       uint32_t RESERVED6[4]; /*!< Reserved,                                               0x70 - 0x7C */
-  __IO uint32_t JDR1;         /*!< ADC group injected rank 1 data register,       Address offset: 0x80 */
-  __IO uint32_t JDR2;         /*!< ADC group injected rank 2 data register,       Address offset: 0x84 */
-  __IO uint32_t JDR3;         /*!< ADC group injected rank 3 data register,       Address offset: 0x88 */
-  __IO uint32_t JDR4;         /*!< ADC group injected rank 4 data register,       Address offset: 0x8C */
-       uint32_t RESERVED7[4]; /*!< Reserved,                                             0x090 - 0x09C */
-  __IO uint32_t AWD2CR;       /*!< ADC analog watchdog 1 configuration register,  Address offset: 0xA0 */
-  __IO uint32_t AWD3CR;       /*!< ADC analog watchdog 3 Configuration Register,  Address offset: 0xA4 */
-       uint32_t RESERVED8;    /*!< Reserved,                                                     0x0A8 */
-       uint32_t RESERVED9;    /*!< Reserved,                                                     0x0AC */
-  __IO uint32_t DIFSEL;       /*!< ADC differential mode selection register,      Address offset: 0xB0 */
-  __IO uint32_t CALFACT;      /*!< ADC calibration factors,                       Address offset: 0xB4 */
-
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< ADC common status register,                    Address offset: ADC1 base address + 0x300 */
-  uint32_t      RESERVED;     /*!< Reserved,                                      Address offset: ADC1 base address + 0x304 */
-  __IO uint32_t CCR;          /*!< ADC common configuration register,             Address offset: ADC1 base address + 0x308 */
-  __IO uint32_t CDR;          /*!< ADC common group regular data register         Address offset: ADC1 base address + 0x30C */
-} ADC_Common_TypeDef;
-
-
-/**
-  * @brief Controller Area Network TxMailBox
-  */
-
-typedef struct
-{
-  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
-  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
-  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
-  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
-} CAN_TxMailBox_TypeDef;
-
-/**
-  * @brief Controller Area Network FIFOMailBox
-  */
-
-typedef struct
-{
-  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
-  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
-  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
-  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
-} CAN_FIFOMailBox_TypeDef;
-
-/**
-  * @brief Controller Area Network FilterRegister
-  */
-
-typedef struct
-{
-  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
-  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
-} CAN_FilterRegister_TypeDef;
-
-/**
-  * @brief Controller Area Network
-  */
-
-typedef struct
-{
-  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
-  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
-  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
-  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
-  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
-  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
-  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
-  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
-  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
-  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
-  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
-  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
-  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
-  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
-  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
-  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
-  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
-  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
-  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
-  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
-  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */
-  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
-} CAN_TypeDef;
-
-
-/**
-  * @brief Comparator
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-/**
-  * @brief CRC calculation unit
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint8_t  IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
-  uint8_t       RESERVED0;   /*!< Reserved,                                                    0x05 */
-  uint16_t      RESERVED1;   /*!< Reserved,                                                    0x06 */
-  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
-  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */
-  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
-  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
-} CRC_TypeDef;
-
-/**
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;          /*!< DAC control register,                                    Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;     /*!< DAC software trigger register,                           Address offset: 0x04 */
-  __IO uint32_t DHR12R1;     /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
-  __IO uint32_t DHR12L1;     /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
-  __IO uint32_t DHR8R1;      /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
-  __IO uint32_t DHR12R2;     /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
-  __IO uint32_t DHR12L2;     /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
-  __IO uint32_t DHR8R2;      /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
-  __IO uint32_t DHR12RD;     /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
-  __IO uint32_t DHR12LD;     /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
-  __IO uint32_t DHR8RD;      /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
-  __IO uint32_t DOR1;        /*!< DAC channel1 data output register,                       Address offset: 0x2C */
-  __IO uint32_t DOR2;        /*!< DAC channel2 data output register,                       Address offset: 0x30 */
-  __IO uint32_t SR;          /*!< DAC status register,                                     Address offset: 0x34 */
-  __IO uint32_t CCR;         /*!< DAC calibration control register,                        Address offset: 0x38 */
-  __IO uint32_t MCR;         /*!< DAC mode control register,                               Address offset: 0x3C */
-  __IO uint32_t SHSR1;       /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */
-  __IO uint32_t SHSR2;       /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */
-  __IO uint32_t SHHR;        /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */
-  __IO uint32_t SHRR;        /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */
-} DAC_TypeDef;
-
-/**
-  * @brief DFSDM module registers
-  */
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< DFSDM control register1,                          Address offset: 0x100 */
-  __IO uint32_t CR2;         /*!< DFSDM control register2,                          Address offset: 0x104 */
-  __IO uint32_t ISR;         /*!< DFSDM interrupt and status register,              Address offset: 0x108 */
-  __IO uint32_t ICR;         /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */
-  __IO uint32_t JCHGR;       /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */
-  __IO uint32_t FCR;         /*!< DFSDM filter control register,                    Address offset: 0x114 */
-  __IO uint32_t JDATAR;      /*!< DFSDM data register for injected group,           Address offset: 0x118 */
-  __IO uint32_t RDATAR;      /*!< DFSDM data register for regular group,            Address offset: 0x11C */
-  __IO uint32_t AWHTR;       /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */
-  __IO uint32_t AWLTR;       /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */
-  __IO uint32_t AWSR;        /*!< DFSDM analog watchdog status register             Address offset: 0x128 */
-  __IO uint32_t AWCFR;       /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */
-  __IO uint32_t EXMAX;       /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */
-  __IO uint32_t EXMIN;       /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */
-  __IO uint32_t CNVTIMR;     /*!< DFSDM conversion timer,                           Address offset: 0x138 */
-} DFSDM_Filter_TypeDef;
-
-/**
-  * @brief DFSDM channel configuration registers
-  */
-typedef struct
-{
-  __IO uint32_t CHCFGR1;     /*!< DFSDM channel configuration register1,            Address offset: 0x00 */
-  __IO uint32_t CHCFGR2;     /*!< DFSDM channel configuration register2,            Address offset: 0x04 */
-  __IO uint32_t AWSCDR;      /*!< DFSDM channel analog watchdog and
-                                  short circuit detector register,                  Address offset: 0x08 */
-  __IO uint32_t CHWDATAR;    /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */
-  __IO uint32_t CHDATINR;    /*!< DFSDM channel data input register,                Address offset: 0x10 */
-} DFSDM_Channel_TypeDef;
-
-/**
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;      /*!< MCU device ID code,                 Address offset: 0x00 */
-  __IO uint32_t CR;          /*!< Debug MCU configuration register,   Address offset: 0x04 */
-  __IO uint32_t APB1FZR1;    /*!< Debug MCU APB1 freeze register 1,   Address offset: 0x08 */
-  __IO uint32_t APB1FZR2;    /*!< Debug MCU APB1 freeze register 2,   Address offset: 0x0C */
-  __IO uint32_t APB2FZ;      /*!< Debug MCU APB2 freeze register,     Address offset: 0x10 */
-} DBGMCU_TypeDef;
-
-
-/**
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;         /*!< DMA channel x configuration register        */
-  __IO uint32_t CNDTR;       /*!< DMA channel x number of data register       */
-  __IO uint32_t CPAR;        /*!< DMA channel x peripheral address register   */
-  __IO uint32_t CMAR;        /*!< DMA channel x memory address register       */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;         /*!< DMA interrupt status register,                 Address offset: 0x00 */
-  __IO uint32_t IFCR;        /*!< DMA interrupt flag clear register,             Address offset: 0x04 */
-} DMA_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSELR;       /*!< DMA channel selection register              */
-} DMA_Request_TypeDef;
-
-/* Legacy define */
-#define DMA_request_TypeDef  DMA_Request_TypeDef
-
-/**
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR1;        /*!< EXTI Interrupt mask register 1,             Address offset: 0x00 */
-  __IO uint32_t EMR1;        /*!< EXTI Event mask register 1,                 Address offset: 0x04 */
-  __IO uint32_t RTSR1;       /*!< EXTI Rising trigger selection register 1,   Address offset: 0x08 */
-  __IO uint32_t FTSR1;       /*!< EXTI Falling trigger selection register 1,  Address offset: 0x0C */
-  __IO uint32_t SWIER1;      /*!< EXTI Software interrupt event register 1,   Address offset: 0x10 */
-  __IO uint32_t PR1;         /*!< EXTI Pending register 1,                    Address offset: 0x14 */
-  uint32_t      RESERVED1;   /*!< Reserved, 0x18                                                   */
-  uint32_t      RESERVED2;   /*!< Reserved, 0x1C                                                   */
-  __IO uint32_t IMR2;        /*!< EXTI Interrupt mask register 2,             Address offset: 0x20 */
-  __IO uint32_t EMR2;        /*!< EXTI Event mask register 2,                 Address offset: 0x24 */
-  __IO uint32_t RTSR2;       /*!< EXTI Rising trigger selection register 2,   Address offset: 0x28 */
-  __IO uint32_t FTSR2;       /*!< EXTI Falling trigger selection register 2,  Address offset: 0x2C */
-  __IO uint32_t SWIER2;      /*!< EXTI Software interrupt event register 2,   Address offset: 0x30 */
-  __IO uint32_t PR2;         /*!< EXTI Pending register 2,                    Address offset: 0x34 */
-} EXTI_TypeDef;
-
-
-/**
-  * @brief Firewall
-  */
-
-typedef struct
-{
-  __IO uint32_t CSSA;        /*!< Code Segment Start Address register,              Address offset: 0x00 */
-  __IO uint32_t CSL;         /*!< Code Segment Length register,                      Address offset: 0x04 */
-  __IO uint32_t NVDSSA;      /*!< NON volatile data Segment Start Address register,  Address offset: 0x08 */
-  __IO uint32_t NVDSL;       /*!< NON volatile data Segment Length register,         Address offset: 0x0C */
-  __IO uint32_t VDSSA ;      /*!< Volatile data Segment Start Address register,      Address offset: 0x10 */
-  __IO uint32_t VDSL ;       /*!< Volatile data Segment Length register,             Address offset: 0x14 */
-  uint32_t      RESERVED1;   /*!< Reserved1,                                         Address offset: 0x18 */
-  uint32_t      RESERVED2;   /*!< Reserved2,                                         Address offset: 0x1C */
-  __IO uint32_t CR ;         /*!< Configuration  register,                           Address offset: 0x20 */
-} FIREWALL_TypeDef;
-
-
-/**
-  * @brief FLASH Registers
-  */
-
-typedef struct
-{
-  __IO uint32_t ACR;              /*!< FLASH access control register,            Address offset: 0x00 */
-  __IO uint32_t PDKEYR;           /*!< FLASH power down key register,            Address offset: 0x04 */
-  __IO uint32_t KEYR;             /*!< FLASH key register,                       Address offset: 0x08 */
-  __IO uint32_t OPTKEYR;          /*!< FLASH option key register,                Address offset: 0x0C */
-  __IO uint32_t SR;               /*!< FLASH status register,                    Address offset: 0x10 */
-  __IO uint32_t CR;               /*!< FLASH control register,                   Address offset: 0x14 */
-  __IO uint32_t ECCR;             /*!< FLASH ECC register,                       Address offset: 0x18 */
-  __IO uint32_t RESERVED1;        /*!< Reserved1,                                Address offset: 0x1C */
-  __IO uint32_t OPTR;             /*!< FLASH option register,                    Address offset: 0x20 */
-  __IO uint32_t PCROP1SR;         /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
-  __IO uint32_t PCROP1ER;         /*!< FLASH bank1 PCROP end address register,   Address offset: 0x28 */
-  __IO uint32_t WRP1AR;           /*!< FLASH bank1 WRP area A address register,  Address offset: 0x2C */
-  __IO uint32_t WRP1BR;           /*!< FLASH bank1 WRP area B address register,  Address offset: 0x30 */
-       uint32_t RESERVED2[4];     /*!< Reserved2,                                Address offset: 0x34 */
-  __IO uint32_t PCROP2SR;         /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */
-  __IO uint32_t PCROP2ER;         /*!< FLASH bank2 PCROP end address register,   Address offset: 0x48 */
-  __IO uint32_t WRP2AR;           /*!< FLASH bank2 WRP area A address register,  Address offset: 0x4C */
-  __IO uint32_t WRP2BR;           /*!< FLASH bank2 WRP area B address register,  Address offset: 0x50 */
-} FLASH_TypeDef;
-
-
-/**
-  * @brief Flexible Memory Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t BTCR[8];     /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
-} FMC_Bank1_TypeDef;
-
-/**
-  * @brief Flexible Memory Controller Bank1E
-  */
-
-typedef struct
-{
-  __IO uint32_t BWTR[7];     /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
-} FMC_Bank1E_TypeDef;
-
-/**
-  * @brief Flexible Memory Controller Bank3
-  */
-
-typedef struct
-{
-  __IO uint32_t PCR;        /*!< NAND Flash control register,                       Address offset: 0x80 */
-  __IO uint32_t SR;         /*!< NAND Flash FIFO status and interrupt register,     Address offset: 0x84 */
-  __IO uint32_t PMEM;       /*!< NAND Flash Common memory space timing register,    Address offset: 0x88 */
-  __IO uint32_t PATT;       /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
-  uint32_t      RESERVED0;  /*!< Reserved, 0x90                                                            */
-  __IO uint32_t ECCR;       /*!< NAND Flash ECC result registers,                   Address offset: 0x94 */
-} FMC_Bank3_TypeDef;
-
-/**
-  * @brief General Purpose I/O
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;       /*!< GPIO port mode register,               Address offset: 0x00      */
-  __IO uint32_t OTYPER;      /*!< GPIO port output type register,        Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;     /*!< GPIO port output speed register,       Address offset: 0x08      */
-  __IO uint32_t PUPDR;       /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
-  __IO uint32_t IDR;         /*!< GPIO port input data register,         Address offset: 0x10      */
-  __IO uint32_t ODR;         /*!< GPIO port output data register,        Address offset: 0x14      */
-  __IO uint32_t BSRR;        /*!< GPIO port bit set/reset  register,     Address offset: 0x18      */
-  __IO uint32_t LCKR;        /*!< GPIO port configuration lock register, Address offset: 0x1C      */
-  __IO uint32_t AFR[2];      /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
-  __IO uint32_t BRR;         /*!< GPIO Bit Reset register,               Address offset: 0x28      */
-  __IO uint32_t ASCR;        /*!< GPIO analog switch control register,   Address offset: 0x2C     */
-
-} GPIO_TypeDef;
-
-
-/**
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< I2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< I2C Control register 2,            Address offset: 0x04 */
-  __IO uint32_t OAR1;        /*!< I2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;        /*!< I2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;     /*!< I2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR;    /*!< I2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;         /*!< I2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;         /*!< I2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;        /*!< I2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;        /*!< I2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;        /*!< I2C Transmit data register,        Address offset: 0x28 */
-} I2C_TypeDef;
-
-/**
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;          /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;          /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;         /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;          /*!< IWDG Status register,    Address offset: 0x0C */
-  __IO uint32_t WINR;        /*!< IWDG Window register,    Address offset: 0x10 */
-} IWDG_TypeDef;
-
-/**
-  * @brief LCD
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;          /*!< LCD control register,              Address offset: 0x00 */
-  __IO uint32_t FCR;         /*!< LCD frame control register,        Address offset: 0x04 */
-  __IO uint32_t SR;          /*!< LCD status register,               Address offset: 0x08 */
-  __IO uint32_t CLR;         /*!< LCD clear register,                Address offset: 0x0C */
-  uint32_t RESERVED;         /*!< Reserved,                          Address offset: 0x10 */
-  __IO uint32_t RAM[16];     /*!< LCD display memory,           Address offset: 0x14-0x50 */
-} LCD_TypeDef;
-
-/**
-  * @brief LPTIMER
-  */
-typedef struct
-{
-  __IO uint32_t ISR;         /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */
-  __IO uint32_t ICR;         /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */
-  __IO uint32_t IER;         /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */
-  __IO uint32_t CFGR;        /*!< LPTIM Configuration register,                       Address offset: 0x0C */
-  __IO uint32_t CR;          /*!< LPTIM Control register,                             Address offset: 0x10 */
-  __IO uint32_t CMP;         /*!< LPTIM Compare register,                             Address offset: 0x14 */
-  __IO uint32_t ARR;         /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
-  __IO uint32_t CNT;         /*!< LPTIM Counter register,                             Address offset: 0x1C */
-  __IO uint32_t OR;          /*!< LPTIM Option register,                              Address offset: 0x20 */
-} LPTIM_TypeDef;
-
-
-/**
-  * @brief Operational Amplifier (OPAMP)
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< OPAMP control/status register,                     Address offset: 0x00 */
-  __IO uint32_t OTR;         /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */
-  __IO uint32_t LPOTR;       /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
-} OPAMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */
-} OPAMP_Common_TypeDef;
-
-/**
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;   /*!< PWR power control register 1,        Address offset: 0x00 */
-  __IO uint32_t CR2;   /*!< PWR power control register 2,        Address offset: 0x04 */
-  __IO uint32_t CR3;   /*!< PWR power control register 3,        Address offset: 0x08 */
-  __IO uint32_t CR4;   /*!< PWR power control register 4,        Address offset: 0x0C */
-  __IO uint32_t SR1;   /*!< PWR power status register 1,         Address offset: 0x10 */
-  __IO uint32_t SR2;   /*!< PWR power status register 2,         Address offset: 0x14 */
-  __IO uint32_t SCR;   /*!< PWR power status reset register,     Address offset: 0x18 */
-  uint32_t RESERVED;   /*!< Reserved,                            Address offset: 0x1C */
-  __IO uint32_t PUCRA; /*!< Pull_up control register of portA,   Address offset: 0x20 */
-  __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
-  __IO uint32_t PUCRB; /*!< Pull_up control register of portB,   Address offset: 0x28 */
-  __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
-  __IO uint32_t PUCRC; /*!< Pull_up control register of portC,   Address offset: 0x30 */
-  __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
-  __IO uint32_t PUCRD; /*!< Pull_up control register of portD,   Address offset: 0x38 */
-  __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
-  __IO uint32_t PUCRE; /*!< Pull_up control register of portE,   Address offset: 0x40 */
-  __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
-  __IO uint32_t PUCRF; /*!< Pull_up control register of portF,   Address offset: 0x48 */
-  __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */
-  __IO uint32_t PUCRG; /*!< Pull_up control register of portG,   Address offset: 0x50 */
-  __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */
-  __IO uint32_t PUCRH; /*!< Pull_up control register of portH,   Address offset: 0x58 */
-  __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */
-} PWR_TypeDef;
-
-
-/**
-  * @brief QUAD Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;          /*!< QUADSPI Control register,                           Address offset: 0x00 */
-  __IO uint32_t DCR;         /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
-  __IO uint32_t SR;          /*!< QUADSPI Status register,                            Address offset: 0x08 */
-  __IO uint32_t FCR;         /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
-  __IO uint32_t DLR;         /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
-  __IO uint32_t CCR;         /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
-  __IO uint32_t AR;          /*!< QUADSPI Address register,                           Address offset: 0x18 */
-  __IO uint32_t ABR;         /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
-  __IO uint32_t DR;          /*!< QUADSPI Data register,                              Address offset: 0x20 */
-  __IO uint32_t PSMKR;       /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
-  __IO uint32_t PSMAR;       /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */
-  __IO uint32_t PIR;         /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
-  __IO uint32_t LPTR;        /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */
-} QUADSPI_TypeDef;
-
-
-/**
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;          /*!< RCC clock control register,                                              Address offset: 0x00 */
-  __IO uint32_t ICSCR;       /*!< RCC internal clock sources calibration register,                         Address offset: 0x04 */
-  __IO uint32_t CFGR;        /*!< RCC clock configuration register,                                        Address offset: 0x08 */
-  __IO uint32_t PLLCFGR;     /*!< RCC system PLL configuration register,                                   Address offset: 0x0C */
-  __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register,                                     Address offset: 0x10 */
-  __IO uint32_t PLLSAI2CFGR; /*!< RCC PLL SAI2 configuration register,                                     Address offset: 0x14 */
-  __IO uint32_t CIER;        /*!< RCC clock interrupt enable register,                                     Address offset: 0x18 */
-  __IO uint32_t CIFR;        /*!< RCC clock interrupt flag register,                                       Address offset: 0x1C */
-  __IO uint32_t CICR;        /*!< RCC clock interrupt clear register,                                      Address offset: 0x20 */
-  uint32_t      RESERVED0;   /*!< Reserved,                                                                Address offset: 0x24 */
-  __IO uint32_t AHB1RSTR;    /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x28 */
-  __IO uint32_t AHB2RSTR;    /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x2C */
-  __IO uint32_t AHB3RSTR;    /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x30 */
-  uint32_t      RESERVED1;   /*!< Reserved,                                                                Address offset: 0x34 */
-  __IO uint32_t APB1RSTR1;   /*!< RCC APB1 peripheral reset register 1,                                    Address offset: 0x38 */
-  __IO uint32_t APB1RSTR2;   /*!< RCC APB1 peripheral reset register 2,                                    Address offset: 0x3C */
-  __IO uint32_t APB2RSTR;    /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x40 */
-  uint32_t      RESERVED2;   /*!< Reserved,                                                                Address offset: 0x44 */
-  __IO uint32_t AHB1ENR;     /*!< RCC AHB1 peripheral clocks enable register,                              Address offset: 0x48 */
-  __IO uint32_t AHB2ENR;     /*!< RCC AHB2 peripheral clocks enable register,                              Address offset: 0x4C */
-  __IO uint32_t AHB3ENR;     /*!< RCC AHB3 peripheral clocks enable register,                              Address offset: 0x50 */
-  uint32_t      RESERVED3;   /*!< Reserved,                                                                Address offset: 0x54 */
-  __IO uint32_t APB1ENR1;    /*!< RCC APB1 peripheral clocks enable register 1,                            Address offset: 0x58 */
-  __IO uint32_t APB1ENR2;    /*!< RCC APB1 peripheral clocks enable register 2,                            Address offset: 0x5C */
-  __IO uint32_t APB2ENR;     /*!< RCC APB2 peripheral clocks enable register,                              Address offset: 0x60 */
-  uint32_t      RESERVED4;   /*!< Reserved,                                                                Address offset: 0x64 */
-  __IO uint32_t AHB1SMENR;   /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x68 */
-  __IO uint32_t AHB2SMENR;   /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x6C */
-  __IO uint32_t AHB3SMENR;   /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x70 */
-  uint32_t      RESERVED5;   /*!< Reserved,                                                                Address offset: 0x74 */
-  __IO uint32_t APB1SMENR1;  /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
-  __IO uint32_t APB1SMENR2;  /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
-  __IO uint32_t APB2SMENR;   /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
-  uint32_t      RESERVED6;   /*!< Reserved,                                                                Address offset: 0x84 */
-  __IO uint32_t CCIPR;       /*!< RCC peripherals independent clock configuration register,                Address offset: 0x88 */
-  __IO uint32_t RESERVED7;   /*!< Reserved,                                                                Address offset: 0x8C */
-  __IO uint32_t BDCR;        /*!< RCC backup domain control register,                                      Address offset: 0x90 */
-  __IO uint32_t CSR;         /*!< RCC clock control & status register,                                     Address offset: 0x94 */
-} RCC_TypeDef;
-
-/**
-  * @brief Real-Time Clock
-  */
-
-typedef struct
-{
-  __IO uint32_t TR;          /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;          /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;          /*!< RTC control register,                                      Address offset: 0x08 */
-  __IO uint32_t ISR;         /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;        /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;        /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-       uint32_t reserved;    /*!< Reserved  */
-  __IO uint32_t ALRMAR;      /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;      /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;         /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;         /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;      /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;        /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;        /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;       /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;        /*!< RTC calibration register,                                  Address offset: 0x3C */
-  __IO uint32_t TAMPCR;      /*!< RTC tamper configuration register,                         Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;    /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;    /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  __IO uint32_t OR;          /*!< RTC option register,                                       Address offset: 0x4C */
-  __IO uint32_t BKP0R;       /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;       /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;       /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;       /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;       /*!< RTC backup register 4,                                     Address offset: 0x60 */
-  __IO uint32_t BKP5R;       /*!< RTC backup register 5,                                     Address offset: 0x64 */
-  __IO uint32_t BKP6R;       /*!< RTC backup register 6,                                     Address offset: 0x68 */
-  __IO uint32_t BKP7R;       /*!< RTC backup register 7,                                     Address offset: 0x6C */
-  __IO uint32_t BKP8R;       /*!< RTC backup register 8,                                     Address offset: 0x70 */
-  __IO uint32_t BKP9R;       /*!< RTC backup register 9,                                     Address offset: 0x74 */
-  __IO uint32_t BKP10R;      /*!< RTC backup register 10,                                    Address offset: 0x78 */
-  __IO uint32_t BKP11R;      /*!< RTC backup register 11,                                    Address offset: 0x7C */
-  __IO uint32_t BKP12R;      /*!< RTC backup register 12,                                    Address offset: 0x80 */
-  __IO uint32_t BKP13R;      /*!< RTC backup register 13,                                    Address offset: 0x84 */
-  __IO uint32_t BKP14R;      /*!< RTC backup register 14,                                    Address offset: 0x88 */
-  __IO uint32_t BKP15R;      /*!< RTC backup register 15,                                    Address offset: 0x8C */
-  __IO uint32_t BKP16R;      /*!< RTC backup register 16,                                    Address offset: 0x90 */
-  __IO uint32_t BKP17R;      /*!< RTC backup register 17,                                    Address offset: 0x94 */
-  __IO uint32_t BKP18R;      /*!< RTC backup register 18,                                    Address offset: 0x98 */
-  __IO uint32_t BKP19R;      /*!< RTC backup register 19,                                    Address offset: 0x9C */
-  __IO uint32_t BKP20R;      /*!< RTC backup register 20,                                    Address offset: 0xA0 */
-  __IO uint32_t BKP21R;      /*!< RTC backup register 21,                                    Address offset: 0xA4 */
-  __IO uint32_t BKP22R;      /*!< RTC backup register 22,                                    Address offset: 0xA8 */
-  __IO uint32_t BKP23R;      /*!< RTC backup register 23,                                    Address offset: 0xAC */
-  __IO uint32_t BKP24R;      /*!< RTC backup register 24,                                    Address offset: 0xB0 */
-  __IO uint32_t BKP25R;      /*!< RTC backup register 25,                                    Address offset: 0xB4 */
-  __IO uint32_t BKP26R;      /*!< RTC backup register 26,                                    Address offset: 0xB8 */
-  __IO uint32_t BKP27R;      /*!< RTC backup register 27,                                    Address offset: 0xBC */
-  __IO uint32_t BKP28R;      /*!< RTC backup register 28,                                    Address offset: 0xC0 */
-  __IO uint32_t BKP29R;      /*!< RTC backup register 29,                                    Address offset: 0xC4 */
-  __IO uint32_t BKP30R;      /*!< RTC backup register 30,                                    Address offset: 0xC8 */
-  __IO uint32_t BKP31R;      /*!< RTC backup register 31,                                    Address offset: 0xCC */
-} RTC_TypeDef;
-
-
-/**
-  * @brief Serial Audio Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t GCR;         /*!< SAI global configuration register,        Address offset: 0x00 */
-} SAI_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< SAI block x configuration register 1,     Address offset: 0x04 */
-  __IO uint32_t CR2;         /*!< SAI block x configuration register 2,     Address offset: 0x08 */
-  __IO uint32_t FRCR;        /*!< SAI block x frame configuration register, Address offset: 0x0C */
-  __IO uint32_t SLOTR;       /*!< SAI block x slot register,                Address offset: 0x10 */
-  __IO uint32_t IMR;         /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
-  __IO uint32_t SR;          /*!< SAI block x status register,              Address offset: 0x18 */
-  __IO uint32_t CLRFR;       /*!< SAI block x clear flag register,          Address offset: 0x1C */
-  __IO uint32_t DR;          /*!< SAI block x data register,                Address offset: 0x20 */
-} SAI_Block_TypeDef;
-
-
-/**
-  * @brief Secure digital input/output Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t POWER;          /*!< SDMMC power control register,    Address offset: 0x00 */
-  __IO uint32_t CLKCR;          /*!< SDMMC clock control register,    Address offset: 0x04 */
-  __IO uint32_t ARG;            /*!< SDMMC argument register,         Address offset: 0x08 */
-  __IO uint32_t CMD;            /*!< SDMMC command register,          Address offset: 0x0C */
-  __I uint32_t  RESPCMD;        /*!< SDMMC command response register, Address offset: 0x10 */
-  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,       Address offset: 0x14 */
-  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,       Address offset: 0x18 */
-  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,       Address offset: 0x1C */
-  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,       Address offset: 0x20 */
-  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,       Address offset: 0x24 */
-  __IO uint32_t DLEN;           /*!< SDMMC data length register,      Address offset: 0x28 */
-  __IO uint32_t DCTRL;          /*!< SDMMC data control register,     Address offset: 0x2C */
-  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,     Address offset: 0x30 */
-  __I uint32_t  STA;            /*!< SDMMC status register,           Address offset: 0x34 */
-  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,  Address offset: 0x38 */
-  __IO uint32_t MASK;           /*!< SDMMC mask register,             Address offset: 0x3C */
-  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
-  __I uint32_t  FIFOCNT;        /*!< SDMMC FIFO counter register,     Address offset: 0x48 */
-  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
-  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,        Address offset: 0x80 */
-} SDMMC_TypeDef;
-
-
-/**
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< SPI Control register 1,                              Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< SPI Control register 2,                              Address offset: 0x04 */
-  __IO uint32_t SR;          /*!< SPI Status register,                                 Address offset: 0x08 */
-  __IO uint32_t DR;          /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;       /*!< SPI CRC polynomial register,                         Address offset: 0x10 */
-  __IO uint32_t RXCRCR;      /*!< SPI Rx CRC register,                                 Address offset: 0x14 */
-  __IO uint32_t TXCRCR;      /*!< SPI Tx CRC register,                                 Address offset: 0x18 */
-  uint32_t  RESERVED1;       /*!< Reserved,                                            Address offset: 0x1C */
-  uint32_t  RESERVED2;       /*!< Reserved,                                            Address offset: 0x20 */
-} SPI_TypeDef;
-
-
-/**
-  * @brief Single Wire Protocol Master Interface SPWMI
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;          /*!< SWPMI Configuration/Control register,     Address offset: 0x00 */
-  __IO uint32_t BRR;         /*!< SWPMI bitrate register,                   Address offset: 0x04 */
-    uint32_t  RESERVED1;     /*!< Reserved, 0x08                                                 */
-  __IO uint32_t ISR;         /*!< SWPMI Interrupt and Status register,      Address offset: 0x0C */
-  __IO uint32_t ICR;         /*!< SWPMI Interrupt Flag Clear register,      Address offset: 0x10 */
-  __IO uint32_t IER;         /*!< SWPMI Interrupt Enable register,          Address offset: 0x14 */
-  __IO uint32_t RFL;         /*!< SWPMI Receive Frame Length register,      Address offset: 0x18 */
-  __IO uint32_t TDR;         /*!< SWPMI Transmit data register,             Address offset: 0x1C */
-  __IO uint32_t RDR;         /*!< SWPMI Receive data register,              Address offset: 0x20 */
-  __IO uint32_t OR;          /*!< SWPMI Option register,                    Address offset: 0x24 */
-} SWPMI_TypeDef;
-
-
-/**
-  * @brief System configuration controller
-  */
-
-typedef struct
-{
-  __IO uint32_t MEMRMP;      /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t CFGR1;       /*!< SYSCFG configuration register 1,                   Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];   /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-  __IO uint32_t SCSR;        /*!< SYSCFG SRAM2 control and status register,          Address offset: 0x18      */
-  __IO uint32_t CFGR2;       /*!< SYSCFG configuration register 2,                   Address offset: 0x1C      */
-  __IO uint32_t SWPR;        /*!< SYSCFG SRAM2 write protection register,            Address offset: 0x20      */
-  __IO uint32_t SKR;         /*!< SYSCFG SRAM2 key register,                         Address offset: 0x24      */
-} SYSCFG_TypeDef;
-
-
-/**
-  * @brief TIM
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */
-  __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */
-  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */
-  __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */
-  __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */
-  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */
-  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */
-  __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */
-  __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */
-  __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */
-  __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */
-  __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */
-  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */
-  __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */
-  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */
-  __IO uint32_t OR1;         /*!< TIM option register 1,                    Address offset: 0x50 */
-  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */
-  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */
-  __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */
-  __IO uint32_t OR2;         /*!< TIM option register 2,                    Address offset: 0x60 */
-  __IO uint32_t OR3;         /*!< TIM option register 3,                    Address offset: 0x64 */
-} TIM_TypeDef;
-
-
-/**
-  * @brief Touch Sensing Controller (TSC)
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< TSC control register,                                     Address offset: 0x00 */
-  __IO uint32_t IER;           /*!< TSC interrupt enable register,                            Address offset: 0x04 */
-  __IO uint32_t ICR;           /*!< TSC interrupt clear register,                             Address offset: 0x08 */
-  __IO uint32_t ISR;           /*!< TSC interrupt status register,                            Address offset: 0x0C */
-  __IO uint32_t IOHCR;         /*!< TSC I/O hysteresis control register,                      Address offset: 0x10 */
-  uint32_t      RESERVED1;     /*!< Reserved,                                                 Address offset: 0x14 */
-  __IO uint32_t IOASCR;        /*!< TSC I/O analog switch control register,                   Address offset: 0x18 */
-  uint32_t      RESERVED2;     /*!< Reserved,                                                 Address offset: 0x1C */
-  __IO uint32_t IOSCR;         /*!< TSC I/O sampling control register,                        Address offset: 0x20 */
-  uint32_t      RESERVED3;     /*!< Reserved,                                                 Address offset: 0x24 */
-  __IO uint32_t IOCCR;         /*!< TSC I/O channel control register,                         Address offset: 0x28 */
-  uint32_t      RESERVED4;     /*!< Reserved,                                                 Address offset: 0x2C */
-  __IO uint32_t IOGCSR;        /*!< TSC I/O group control status register,                    Address offset: 0x30 */
-  __IO uint32_t IOGXCR[8];     /*!< TSC I/O group x counter register,                         Address offset: 0x34-50 */
-} TSC_TypeDef;
-
-/**
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< USART Control register 1,                 Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< USART Control register 2,                 Address offset: 0x04 */
-  __IO uint32_t CR3;         /*!< USART Control register 3,                 Address offset: 0x08 */
-  __IO uint32_t BRR;         /*!< USART Baud rate register,                 Address offset: 0x0C */
-  __IO uint16_t GTPR;        /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
-  uint16_t  RESERVED2;       /*!< Reserved, 0x12                                                 */
-  __IO uint32_t RTOR;        /*!< USART Receiver Time Out register,         Address offset: 0x14 */
-  __IO uint16_t RQR;         /*!< USART Request register,                   Address offset: 0x18 */
-  uint16_t  RESERVED3;       /*!< Reserved, 0x1A                                                 */
-  __IO uint32_t ISR;         /*!< USART Interrupt and status register,      Address offset: 0x1C */
-  __IO uint32_t ICR;         /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
-  __IO uint16_t RDR;         /*!< USART Receive Data register,              Address offset: 0x24 */
-  uint16_t  RESERVED4;       /*!< Reserved, 0x26                                                 */
-  __IO uint16_t TDR;         /*!< USART Transmit Data register,             Address offset: 0x28 */
-  uint16_t  RESERVED5;       /*!< Reserved, 0x2A                                                 */
-} USART_TypeDef;
-
-/**
-  * @brief VREFBUF
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */
-  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */
-} VREFBUF_TypeDef;
-
-/**
-  * @brief Window WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;          /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;         /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;          /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/**
-  * @brief RNG
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
-  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
-  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
-} RNG_TypeDef;
-
-/** 
-  * @brief USB_OTG_Core_register
-  */
-typedef struct
-{
-  __IO uint32_t GOTGCTL;              /*!<  USB_OTG Control and Status Register          000h*/
-  __IO uint32_t GOTGINT;              /*!<  USB_OTG Interrupt Register                   004h*/
-  __IO uint32_t GAHBCFG;              /*!<  Core AHB Configuration Register              008h*/
-  __IO uint32_t GUSBCFG;              /*!<  Core USB Configuration Register              00Ch*/
-  __IO uint32_t GRSTCTL;              /*!<  Core Reset Register                          010h*/
-  __IO uint32_t GINTSTS;              /*!<  Core Interrupt Register                      014h*/
-  __IO uint32_t GINTMSK;              /*!<  Core Interrupt Mask Register                 018h*/
-  __IO uint32_t GRXSTSR;              /*!<  Receive Sts Q Read Register                  01Ch*/
-  __IO uint32_t GRXSTSP;              /*!<  Receive Sts Q Read & POP Register            020h*/
-  __IO uint32_t GRXFSIZ;              /* Receive FIFO Size Register                      024h*/
-  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!<  EP0 / Non Periodic Tx FIFO Size Register     028h*/
-  __IO uint32_t HNPTXSTS;             /*!<  Non Periodic Tx FIFO/Queue Sts reg           02Ch*/
-  uint32_t Reserved30[2];             /* Reserved                                        030h*/
-  __IO uint32_t GCCFG;                /* General Purpose IO Register                     038h*/
-  __IO uint32_t CID;                  /* User ID Register                                03Ch*/
-  uint32_t  Reserved5[3];             /* Reserved                                        040h-048h*/
-  __IO uint32_t GHWCFG3;              /* User HW config3                                 04Ch*/
-  uint32_t  Reserved6;                /* Reserved                                        050h*/ 
-  __IO uint32_t GLPMCFG;              /* LPM Register                                    054h*/
-  __IO uint32_t GPWRDN;               /* Power Down Register                             058h*/
-  __IO uint32_t GDFIFOCFG;            /* DFIFO Software Config Register                  05Ch*/
-   __IO uint32_t GADPCTL;             /* ADP Timer, Control and Status Register          60Ch*/
-    uint32_t  Reserved43[39];         /* Reserved                                        058h-0FFh*/
-  __IO uint32_t HPTXFSIZ;             /* Host Periodic Tx FIFO Size Reg                  100h*/
-  __IO uint32_t DIEPTXF[0x0F];        /* dev Periodic Transmit FIFO */
-} USB_OTG_GlobalTypeDef;
-
-/** 
-  * @brief USB_OTG_device_Registers
-  */
-typedef struct 
-{
-  __IO uint32_t DCFG;        /* dev Configuration Register   800h*/
-  __IO uint32_t DCTL;        /* dev Control Register         804h*/
-  __IO uint32_t DSTS;        /* dev Status Register (RO)     808h*/
-  uint32_t Reserved0C;       /* Reserved                     80Ch*/
-  __IO uint32_t DIEPMSK;     /* dev IN Endpoint Mask         810h*/
-  __IO uint32_t DOEPMSK;     /* dev OUT Endpoint Mask        814h*/
-  __IO uint32_t DAINT;       /* dev All Endpoints Itr Reg    818h*/
-  __IO uint32_t DAINTMSK;    /* dev All Endpoints Itr Mask   81Ch*/
-  uint32_t  Reserved20;      /* Reserved                     820h*/
-  uint32_t Reserved9;        /* Reserved                     824h*/
-  __IO uint32_t DVBUSDIS;    /* dev VBUS discharge Register  828h*/
-  __IO uint32_t DVBUSPULSE;  /* dev VBUS Pulse Register      82Ch*/
-  __IO uint32_t DTHRCTL;     /* dev thr                      830h*/
-  __IO uint32_t DIEPEMPMSK;  /* dev empty msk             834h*/
-  __IO uint32_t DEACHINT;    /* dedicated EP interrupt       838h*/
-  __IO uint32_t DEACHMSK;    /* dedicated EP msk             83Ch*/  
-  uint32_t Reserved40;       /* dedicated EP mask           840h*/
-  __IO uint32_t DINEP1MSK;   /* dedicated EP mask           844h*/
-  uint32_t  Reserved44[15];  /* Reserved                 844-87Ch*/
-  __IO uint32_t DOUTEP1MSK;  /* dedicated EP msk            884h*/   
-} USB_OTG_DeviceTypeDef;
-
-/** 
-  * @brief USB_OTG_IN_Endpoint-Specific_Register
-  */
-typedef struct 
-{
-  __IO uint32_t DIEPCTL;     /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
-  uint32_t Reserved04;       /* Reserved                       900h + (ep_num * 20h) + 04h*/
-  __IO uint32_t DIEPINT;     /* dev IN Endpoint Itr Reg     900h + (ep_num * 20h) + 08h*/
-  uint32_t Reserved0C;       /* Reserved                       900h + (ep_num * 20h) + 0Ch*/
-  __IO uint32_t DIEPTSIZ;    /* IN Endpoint Txfer Size   900h + (ep_num * 20h) + 10h*/
-  __IO uint32_t DIEPDMA;     /* IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h*/
-  __IO uint32_t DTXFSTS;     /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
-  uint32_t Reserved18;       /* Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
-} USB_OTG_INEndpointTypeDef;
-
-/** 
-  * @brief USB_OTG_OUT_Endpoint-Specific_Registers
-  */
-typedef struct 
-{
-  __IO uint32_t DOEPCTL;     /* dev OUT Endpoint Control Reg  B00h + (ep_num * 20h) + 00h*/
-  uint32_t Reserved04;       /* Reserved                      B00h + (ep_num * 20h) + 04h*/
-  __IO uint32_t DOEPINT;     /* dev OUT Endpoint Itr Reg      B00h + (ep_num * 20h) + 08h*/
-  uint32_t Reserved0C;       /* Reserved                      B00h + (ep_num * 20h) + 0Ch*/
-  __IO uint32_t DOEPTSIZ;    /* dev OUT Endpoint Txfer Size   B00h + (ep_num * 20h) + 10h*/
-  __IO uint32_t DOEPDMA;     /* dev OUT Endpoint DMA Address  B00h + (ep_num * 20h) + 14h*/
-  uint32_t Reserved18[2];    /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
-} USB_OTG_OUTEndpointTypeDef;
-
-/** 
-  * @brief USB_OTG_Host_Mode_Register_Structures
-  */
-typedef struct 
-{
-  __IO uint32_t HCFG;        /* Host Configuration Register    400h*/
-  __IO uint32_t HFIR;        /* Host Frame Interval Register   404h*/
-  __IO uint32_t HFNUM;       /* Host Frame Nbr/Frame Remaining 408h*/
-  uint32_t Reserved40C;      /* Reserved                       40Ch*/
-  __IO uint32_t HPTXSTS;     /* Host Periodic Tx FIFO/ Queue Status 410h*/
-  __IO uint32_t HAINT;       /* Host All Channels Interrupt Register 414h*/
-  __IO uint32_t HAINTMSK;    /* Host All Channels Interrupt Mask 418h*/
-} USB_OTG_HostTypeDef;
-
-/** 
-  * @brief USB_OTG_Host_Channel_Specific_Registers
-  */
-typedef struct
-{
-  __IO uint32_t HCCHAR;
-  __IO uint32_t HCSPLT;
-  __IO uint32_t HCINT;
-  __IO uint32_t HCINTMSK;
-  __IO uint32_t HCTSIZ;
-  __IO uint32_t HCDMA;
-  uint32_t Reserved[2];
-} USB_OTG_HostChannelTypeDef;
-
-/**
-  * @}
-  */
-
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-#define FLASH_BASE            ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address */
-#define SRAM1_BASE            ((uint32_t)0x20000000U) /*!< SRAM1(up to 96 KB) base address*/
-#define PERIPH_BASE           ((uint32_t)0x40000000U) /*!< Peripheral base address */
-#define FMC_BASE              ((uint32_t)0x60000000U) /*!< FMC base address */
-#define SRAM2_BASE            ((uint32_t)0x10000000U) /*!< SRAM2(32 KB) base address*/
-#define FMC_R_BASE            ((uint32_t)0xA0000000U) /*!< FMC  control registers base address */
-#define QSPI_R_BASE           ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
-#define SRAM1_BB_BASE         ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
-#define PERIPH_BB_BASE        ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
-#define SRAM2_BB_BASE         ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
-
-/* Legacy defines */
-#define SRAM_BASE             SRAM1_BASE
-#define SRAM_BB_BASE          SRAM1_BB_BASE
-
-#define SRAM1_SIZE_MAX        ((uint32_t)0x00018000U) /*!< maximum SRAM1 size (up to 96 KBytes) */
-#define SRAM2_SIZE            ((uint32_t)0x00008000U) /*!< SRAM2 size (32 KBytes) */
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE        PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000U)
-
-#define FMC_BANK1             FMC_BASE
-#define FMC_BANK1_1           FMC_BANK1
-#define FMC_BANK1_2           (FMC_BANK1 + 0x04000000U)
-#define FMC_BANK1_3           (FMC_BANK1 + 0x08000000U)
-#define FMC_BANK1_4           (FMC_BANK1 + 0x0C000000U)
-#define FMC_BANK3             (FMC_BASE  + 0x20000000U)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)
-#define LCD_BASE              (APB1PERIPH_BASE + 0x2400U)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800U)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00U)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x5000U)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)
-#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)
-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)
-#define DAC1_BASE             (APB1PERIPH_BASE + 0x7400U)
-#define OPAMP_BASE            (APB1PERIPH_BASE + 0x7800U)
-#define OPAMP1_BASE           (APB1PERIPH_BASE + 0x7800U)
-#define OPAMP2_BASE           (APB1PERIPH_BASE + 0x7810U)
-#define LPTIM1_BASE           (APB1PERIPH_BASE + 0x7C00U)
-#define LPUART1_BASE          (APB1PERIPH_BASE + 0x8000U)
-#define SWPMI1_BASE           (APB1PERIPH_BASE + 0x8800U)
-#define LPTIM2_BASE           (APB1PERIPH_BASE + 0x9400U)
-
-
-/*!< APB2 peripherals */
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x0000U)
-#define VREFBUF_BASE          (APB2PERIPH_BASE + 0x0030U)
-#define COMP1_BASE            (APB2PERIPH_BASE + 0x0200U)
-#define COMP2_BASE            (APB2PERIPH_BASE + 0x0204U)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400U)
-#define FIREWALL_BASE         (APB2PERIPH_BASE + 0x1C00U)
-#define SDMMC1_BASE           (APB2PERIPH_BASE + 0x2800U)
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00U)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)
-#define TIM8_BASE             (APB2PERIPH_BASE + 0x3400U)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x3800U)
-#define TIM15_BASE            (APB2PERIPH_BASE + 0x4000U)
-#define TIM16_BASE            (APB2PERIPH_BASE + 0x4400U)
-#define TIM17_BASE            (APB2PERIPH_BASE + 0x4800U)
-#define SAI1_BASE             (APB2PERIPH_BASE + 0x5400U)
-#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004)
-#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024)
-#define SAI2_BASE             (APB2PERIPH_BASE + 0x5800U)
-#define SAI2_Block_A_BASE     (SAI2_BASE + 0x004)
-#define SAI2_Block_B_BASE     (SAI2_BASE + 0x024)
-#define DFSDM_BASE            (APB2PERIPH_BASE + 0x6000U)
-#define DFSDM_Channel0_BASE   (DFSDM_BASE + 0x00)
-#define DFSDM_Channel1_BASE   (DFSDM_BASE + 0x20)
-#define DFSDM_Channel2_BASE   (DFSDM_BASE + 0x40)
-#define DFSDM_Channel3_BASE   (DFSDM_BASE + 0x60)
-#define DFSDM_Channel4_BASE   (DFSDM_BASE + 0x80)
-#define DFSDM_Channel5_BASE   (DFSDM_BASE + 0xA0)
-#define DFSDM_Channel6_BASE   (DFSDM_BASE + 0xC0)
-#define DFSDM_Channel7_BASE   (DFSDM_BASE + 0xE0)
-#define DFSDM_Filter0_BASE    (DFSDM_BASE + 0x100)
-#define DFSDM_Filter1_BASE    (DFSDM_BASE + 0x180)
-#define DFSDM_Filter2_BASE    (DFSDM_BASE + 0x200)
-#define DFSDM_Filter3_BASE    (DFSDM_BASE + 0x280)
-
-/*!< AHB1 peripherals */
-#define DMA1_BASE             (AHB1PERIPH_BASE)
-#define DMA2_BASE             (AHB1PERIPH_BASE + 0x0400U)
-#define RCC_BASE              (AHB1PERIPH_BASE + 0x1000U)
-#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x2000U)
-#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)
-#define TSC_BASE              (AHB1PERIPH_BASE + 0x4000U)
-
-
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x0008U)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x001CU)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x0030U)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x0044U)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x0058U)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x006CU)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x0080U)
-#define DMA1_CSELR_BASE       (DMA1_BASE + 0x00A8U)
-
-
-#define DMA2_Channel1_BASE    (DMA2_BASE + 0x0008U)
-#define DMA2_Channel2_BASE    (DMA2_BASE + 0x001CU)
-#define DMA2_Channel3_BASE    (DMA2_BASE + 0x0030U)
-#define DMA2_Channel4_BASE    (DMA2_BASE + 0x0044U)
-#define DMA2_Channel5_BASE    (DMA2_BASE + 0x0058U)
-#define DMA2_Channel6_BASE    (DMA2_BASE + 0x006CU)
-#define DMA2_Channel7_BASE    (DMA2_BASE + 0x0080U)
-#define DMA2_CSELR_BASE       (DMA2_BASE + 0x00A8U)
-
-
-/*!< AHB2 peripherals */
-#define GPIOA_BASE            (AHB2PERIPH_BASE + 0x0000U)
-#define GPIOB_BASE            (AHB2PERIPH_BASE + 0x0400U)
-#define GPIOC_BASE            (AHB2PERIPH_BASE + 0x0800U)
-#define GPIOD_BASE            (AHB2PERIPH_BASE + 0x0C00U)
-#define GPIOE_BASE            (AHB2PERIPH_BASE + 0x1000U)
-#define GPIOF_BASE            (AHB2PERIPH_BASE + 0x1400U)
-#define GPIOG_BASE            (AHB2PERIPH_BASE + 0x1800U)
-#define GPIOH_BASE            (AHB2PERIPH_BASE + 0x1C00U)
-
-#define USBOTG_BASE           (AHB2PERIPH_BASE + 0x08000000U)
-
-#define ADC1_BASE             (AHB2PERIPH_BASE + 0x08040000U)
-#define ADC2_BASE             (AHB2PERIPH_BASE + 0x08040100U)
-#define ADC3_BASE             (AHB2PERIPH_BASE + 0x08040200U)
-#define ADC123_COMMON_BASE    (AHB2PERIPH_BASE + 0x08040300U)
-
-
-#define RNG_BASE              (AHB2PERIPH_BASE + 0x08060800U)
-
-/*!< FMC Banks registers base  address */
-#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000U)
-#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104U)
-#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080U)
-
-/* Debug MCU registers base address */
-#define DBGMCU_BASE           ((uint32_t)0xE0042000U)
-
-/*!< USB registers base address */
-#define USB_OTG_FS_PERIPH_BASE               ((uint32_t)0x50000000U)
-
-#define USB_OTG_GLOBAL_BASE                  ((uint32_t)0x00000000U)
-#define USB_OTG_DEVICE_BASE                  ((uint32_t)0x00000800U)
-#define USB_OTG_IN_ENDPOINT_BASE             ((uint32_t)0x00000900U)
-#define USB_OTG_OUT_ENDPOINT_BASE            ((uint32_t)0x00000B00U)
-#define USB_OTG_EP_REG_SIZE                  ((uint32_t)0x00000020U)
-#define USB_OTG_HOST_BASE                    ((uint32_t)0x00000400U)
-#define USB_OTG_HOST_PORT_BASE               ((uint32_t)0x00000440U)
-#define USB_OTG_HOST_CHANNEL_BASE            ((uint32_t)0x00000500U)
-#define USB_OTG_HOST_CHANNEL_SIZE            ((uint32_t)0x00000020U)
-#define USB_OTG_PCGCCTL_BASE                 ((uint32_t)0x00000E00U)
-#define USB_OTG_FIFO_BASE                    ((uint32_t)0x00001000U)
-#define USB_OTG_FIFO_SIZE                    ((uint32_t)0x00001000U)
-
-
-#define PACKAGE_BASE          ((uint32_t)0x1FFF7500U)        /*!< Package data register base address     */
-#define UID_BASE              ((uint32_t)0x1FFF7590U)        /*!< Unique device ID register base address */
-#define FLASHSIZE_BASE        ((uint32_t)0x1FFF75E0U)        /*!< Flash size data register base address  */
-/**
-  * @}
-  */
-
-/** @addtogroup Peripheral_declaration
-  * @{
-  */
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define LCD                 ((LCD_TypeDef *) LCD_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define UART4               ((USART_TypeDef *) UART4_BASE)
-#define UART5               ((USART_TypeDef *) UART5_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
-#define CAN                 ((CAN_TypeDef *) CAN1_BASE)
-#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC1_BASE)
-#define DAC1                ((DAC_TypeDef *) DAC1_BASE)
-#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
-#define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)
-#define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)
-#define OPAMP12_COMMON      ((OPAMP_Common_TypeDef *) OPAMP1_BASE)
-#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
-#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
-#define SWPMI1              ((SWPMI_TypeDef *) SWPMI1_BASE)
-#define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)
-
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)
-#define COMP1               ((COMP_TypeDef *) COMP1_BASE)
-#define COMP2               ((COMP_TypeDef *) COMP2_BASE)
-#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP2_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define FIREWALL            ((FIREWALL_TypeDef *) FIREWALL_BASE)
-#define SDMMC1              ((SDMMC_TypeDef *) SDMMC1_BASE)
-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define TIM15               ((TIM_TypeDef *) TIM15_BASE)
-#define TIM16               ((TIM_TypeDef *) TIM16_BASE)
-#define TIM17               ((TIM_TypeDef *) TIM17_BASE)
-#define SAI1                ((SAI_TypeDef *) SAI1_BASE)
-#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
-#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
-#define SAI2                ((SAI_TypeDef *) SAI2_BASE)
-#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
-#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
-#define DFSDM_Channel0      ((DFSDM_Channel_TypeDef *) DFSDM_Channel0_BASE)
-#define DFSDM_Channel1      ((DFSDM_Channel_TypeDef *) DFSDM_Channel1_BASE)
-#define DFSDM_Channel2      ((DFSDM_Channel_TypeDef *) DFSDM_Channel2_BASE)
-#define DFSDM_Channel3      ((DFSDM_Channel_TypeDef *) DFSDM_Channel3_BASE)
-#define DFSDM_Channel4      ((DFSDM_Channel_TypeDef *) DFSDM_Channel4_BASE)
-#define DFSDM_Channel5      ((DFSDM_Channel_TypeDef *) DFSDM_Channel5_BASE)
-#define DFSDM_Channel6      ((DFSDM_Channel_TypeDef *) DFSDM_Channel6_BASE)
-#define DFSDM_Channel7      ((DFSDM_Channel_TypeDef *) DFSDM_Channel7_BASE)
-#define DFSDM_Filter0       ((DFSDM_Filter_TypeDef *) DFSDM_Filter0_BASE)
-#define DFSDM_Filter1       ((DFSDM_Filter_TypeDef *) DFSDM_Filter1_BASE)
-#define DFSDM_Filter2       ((DFSDM_Filter_TypeDef *) DFSDM_Filter2_BASE)
-#define DFSDM_Filter3       ((DFSDM_Filter_TypeDef *) DFSDM_Filter3_BASE)
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define TSC                 ((TSC_TypeDef *) TSC_BASE)
-
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
-#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
-#define ADC123_COMMON       ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
-#define RNG                 ((RNG_TypeDef *) RNG_BASE)
-
-
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA1_CSELR          ((DMA_request_TypeDef *) DMA1_CSELR_BASE)
-
-
-#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
-#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
-#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
-#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
-#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
-#define DMA2_Channel6       ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
-#define DMA2_Channel7       ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
-#define DMA2_CSELR          ((DMA_request_TypeDef *) DMA2_CSELR_BASE)
-
-
-#define FMC_Bank1_R         ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
-#define FMC_Bank1E_R        ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
-#define FMC_Bank3_R         ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
-
-#define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)
-
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-/** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-
-/******************************************************************************/
-/*                         Peripheral Registers_Bits_Definition               */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Analog to Digital Converter                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L4 family)
- */
-#define ADC_MULTIMODE_SUPPORT                          /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
-
-/********************  Bit definition for ADC_ISR register  *******************/
-#define ADC_ISR_ADRDY           ((uint32_t)0x00000001U) /*!< ADC ready flag */
-#define ADC_ISR_EOSMP           ((uint32_t)0x00000002U) /*!< ADC group regular end of sampling flag */
-#define ADC_ISR_EOC             ((uint32_t)0x00000004U) /*!< ADC group regular end of unitary conversion flag */
-#define ADC_ISR_EOS             ((uint32_t)0x00000008U) /*!< ADC group regular end of sequence conversions flag */
-#define ADC_ISR_OVR             ((uint32_t)0x00000010U) /*!< ADC group regular overrun flag */
-#define ADC_ISR_JEOC            ((uint32_t)0x00000020U) /*!< ADC group injected end of unitary conversion flag */
-#define ADC_ISR_JEOS            ((uint32_t)0x00000040U) /*!< ADC group injected end of sequence conversions flag */
-#define ADC_ISR_AWD1            ((uint32_t)0x00000080U) /*!< ADC analog watchdog 1 flag */
-#define ADC_ISR_AWD2            ((uint32_t)0x00000100U) /*!< ADC analog watchdog 2 flag */
-#define ADC_ISR_AWD3            ((uint32_t)0x00000200U) /*!< ADC analog watchdog 3 flag */
-#define ADC_ISR_JQOVF           ((uint32_t)0x00000400U) /*!< ADC group injected contexts queue overflow flag */
-
-/********************  Bit definition for ADC_IER register  *******************/
-#define ADC_IER_ADRDYIE         ((uint32_t)0x00000001U) /*!< ADC ready interrupt */
-#define ADC_IER_EOSMPIE         ((uint32_t)0x00000002U) /*!< ADC group regular end of sampling interrupt */
-#define ADC_IER_EOCIE           ((uint32_t)0x00000004U) /*!< ADC group regular end of unitary conversion interrupt */
-#define ADC_IER_EOSIE           ((uint32_t)0x00000008U) /*!< ADC group regular end of sequence conversions interrupt */
-#define ADC_IER_OVRIE           ((uint32_t)0x00000010U) /*!< ADC group regular overrun interrupt */
-#define ADC_IER_JEOCIE          ((uint32_t)0x00000020U) /*!< ADC group injected end of unitary conversion interrupt */
-#define ADC_IER_JEOSIE          ((uint32_t)0x00000040U) /*!< ADC group injected end of sequence conversions interrupt */
-#define ADC_IER_AWD1IE          ((uint32_t)0x00000080U) /*!< ADC analog watchdog 1 interrupt */
-#define ADC_IER_AWD2IE          ((uint32_t)0x00000100U) /*!< ADC analog watchdog 2 interrupt */
-#define ADC_IER_AWD3IE          ((uint32_t)0x00000200U) /*!< ADC analog watchdog 3 interrupt */
-#define ADC_IER_JQOVFIE         ((uint32_t)0x00000400U) /*!< ADC group injected contexts queue overflow interrupt */
-
-/* Legacy defines */
-#define ADC_IER_ADRDY           (ADC_IER_ADRDYIE)
-#define ADC_IER_EOSMP           (ADC_IER_EOSMPIE)
-#define ADC_IER_EOC             (ADC_IER_EOCIE)
-#define ADC_IER_EOS             (ADC_IER_EOSIE)
-#define ADC_IER_OVR             (ADC_IER_OVRIE)
-#define ADC_IER_JEOC            (ADC_IER_JEOCIE)
-#define ADC_IER_JEOS            (ADC_IER_JEOSIE)
-#define ADC_IER_AWD1            (ADC_IER_AWD1IE)
-#define ADC_IER_AWD2            (ADC_IER_AWD2IE)
-#define ADC_IER_AWD3            (ADC_IER_AWD3IE)
-#define ADC_IER_JQOVF           (ADC_IER_JQOVFIE)
-
-/********************  Bit definition for ADC_CR register  ********************/
-#define ADC_CR_ADEN             ((uint32_t)0x00000001U) /*!< ADC enable */
-#define ADC_CR_ADDIS            ((uint32_t)0x00000002U) /*!< ADC disable */
-#define ADC_CR_ADSTART          ((uint32_t)0x00000004U) /*!< ADC group regular conversion start */
-#define ADC_CR_JADSTART         ((uint32_t)0x00000008U) /*!< ADC group injected conversion start */
-#define ADC_CR_ADSTP            ((uint32_t)0x00000010U) /*!< ADC group regular conversion stop */
-#define ADC_CR_JADSTP           ((uint32_t)0x00000020U) /*!< ADC group injected conversion stop */
-#define ADC_CR_ADVREGEN         ((uint32_t)0x10000000U) /*!< ADC voltage regulator enable */
-#define ADC_CR_DEEPPWD          ((uint32_t)0x20000000U) /*!< ADC deep power down enable */
-#define ADC_CR_ADCALDIF         ((uint32_t)0x40000000U) /*!< ADC differential mode for calibration */
-#define ADC_CR_ADCAL            ((uint32_t)0x80000000U) /*!< ADC calibration */
-
-/********************  Bit definition for ADC_CFGR register  ******************/
-#define ADC_CFGR_DMAEN          ((uint32_t)0x00000001U) /*!< ADC DMA transfer enable */
-#define ADC_CFGR_DMACFG         ((uint32_t)0x00000002U) /*!< ADC DMA transfer configuration */
-
-#define ADC_CFGR_RES            ((uint32_t)0x00000018U) /*!< ADC data resolution */
-#define ADC_CFGR_RES_0          ((uint32_t)0x00000008U) /*!< bit 0 */
-#define ADC_CFGR_RES_1          ((uint32_t)0x00000010U) /*!< bit 1 */
-
-#define ADC_CFGR_ALIGN          ((uint32_t)0x00000020U) /*!< ADC data alignement */
-
-#define ADC_CFGR_EXTSEL         ((uint32_t)0x000003C0U) /*!< ADC group regular external trigger source */
-#define ADC_CFGR_EXTSEL_0       ((uint32_t)0x00000040U) /*!< bit 0 */
-#define ADC_CFGR_EXTSEL_1       ((uint32_t)0x00000080U) /*!< bit 1 */
-#define ADC_CFGR_EXTSEL_2       ((uint32_t)0x00000100U) /*!< bit 2 */
-#define ADC_CFGR_EXTSEL_3       ((uint32_t)0x00000200U) /*!< bit 3 */
-
-#define ADC_CFGR_EXTEN          ((uint32_t)0x00000C00U) /*!< ADC group regular external trigger polarity */
-#define ADC_CFGR_EXTEN_0        ((uint32_t)0x00000400U) /*!< bit 0 */
-#define ADC_CFGR_EXTEN_1        ((uint32_t)0x00000800U) /*!< bit 1 */
-
-#define ADC_CFGR_OVRMOD         ((uint32_t)0x00001000U) /*!< ADC group regular overrun configuration */
-#define ADC_CFGR_CONT           ((uint32_t)0x00002000U) /*!< ADC group regular continuous conversion mode */
-#define ADC_CFGR_AUTDLY         ((uint32_t)0x00004000U) /*!< ADC low power auto wait */
-
-#define ADC_CFGR_DISCEN         ((uint32_t)0x00010000U) /*!< ADC group regular sequencer discontinuous mode */
-
-#define ADC_CFGR_DISCNUM        ((uint32_t)0x000E0000U) /*!< ADC Discontinuous mode channel count */
-#define ADC_CFGR_DISCNUM_0      ((uint32_t)0x00020000U) /*!< bit 0 */
-#define ADC_CFGR_DISCNUM_1      ((uint32_t)0x00040000U) /*!< bit 1 */
-#define ADC_CFGR_DISCNUM_2      ((uint32_t)0x00080000U) /*!< bit 2 */
-
-#define ADC_CFGR_JDISCEN        ((uint32_t)0x00100000U) /*!< ADC Discontinuous mode on injected channels */
-#define ADC_CFGR_JQM            ((uint32_t)0x00200000U) /*!< ADC group injected contexts queue mode */
-#define ADC_CFGR_AWD1SGL        ((uint32_t)0x00400000U) /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
-#define ADC_CFGR_AWD1EN         ((uint32_t)0x00800000U) /*!< ADC analog watchdog 1 enable on scope ADC group regular */
-#define ADC_CFGR_JAWD1EN        ((uint32_t)0x01000000U) /*!< ADC analog watchdog 1 enable on scope ADC group injected */
-#define ADC_CFGR_JAUTO          ((uint32_t)0x02000000U) /*!< ADC group injected automatic trigger mode */
-
-#define ADC_CFGR_AWD1CH         ((uint32_t)0x7C000000U) /*!< ADC analog watchdog 1 monitored channel selection */
-#define ADC_CFGR_AWD1CH_0       ((uint32_t)0x04000000U) /*!< bit 0 */
-#define ADC_CFGR_AWD1CH_1       ((uint32_t)0x08000000U) /*!< bit 1  */
-#define ADC_CFGR_AWD1CH_2       ((uint32_t)0x10000000U) /*!< bit 2  */
-#define ADC_CFGR_AWD1CH_3       ((uint32_t)0x20000000U) /*!< bit 3  */
-#define ADC_CFGR_AWD1CH_4       ((uint32_t)0x40000000U) /*!< bit 4  */
-
-#define ADC_CFGR_JQDIS          ((uint32_t)0x80000000U) /*!< ADC group injected contexts queue disable */
-
-/********************  Bit definition for ADC_CFGR2 register  *****************/
-#define ADC_CFGR2_ROVSE         ((uint32_t)0x00000001U) /*!< ADC oversampler enable on scope ADC group regular */
-#define ADC_CFGR2_JOVSE         ((uint32_t)0x00000002U) /*!< ADC oversampler enable on scope ADC group injected */
-
-#define ADC_CFGR2_OVSR          ((uint32_t)0x0000001CU) /*!< ADC oversampling ratio */
-#define ADC_CFGR2_OVSR_0        ((uint32_t)0x00000004U) /*!< bit 0 */
-#define ADC_CFGR2_OVSR_1        ((uint32_t)0x00000008U) /*!< bit 1 */
-#define ADC_CFGR2_OVSR_2        ((uint32_t)0x00000010U) /*!< bit 2 */
-
-#define ADC_CFGR2_OVSS          ((uint32_t)0x000001E0U) /*!< ADC oversampling shift */
-#define ADC_CFGR2_OVSS_0        ((uint32_t)0x00000020U) /*!< bit 0 */
-#define ADC_CFGR2_OVSS_1        ((uint32_t)0x00000040U) /*!< bit 1 */
-#define ADC_CFGR2_OVSS_2        ((uint32_t)0x00000080U) /*!< bit 2 */
-#define ADC_CFGR2_OVSS_3        ((uint32_t)0x00000100U) /*!< bit 3 */
-
-#define ADC_CFGR2_TROVS         ((uint32_t)0x00000200U) /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
-#define ADC_CFGR2_ROVSM         ((uint32_t)0x00000400U) /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
-
-/********************  Bit definition for ADC_SMPR1 register  *****************/
-#define ADC_SMPR1_SMP0          ((uint32_t)0x00000007U) /*!< ADC channel 0 sampling time selection  */
-#define ADC_SMPR1_SMP0_0        ((uint32_t)0x00000001U) /*!< bit 0 */
-#define ADC_SMPR1_SMP0_1        ((uint32_t)0x00000002U) /*!< bit 1 */
-#define ADC_SMPR1_SMP0_2        ((uint32_t)0x00000004U) /*!< bit 2 */
-
-#define ADC_SMPR1_SMP1          ((uint32_t)0x00000038U) /*!< ADC channel 1 sampling time selection  */
-#define ADC_SMPR1_SMP1_0        ((uint32_t)0x00000008U) /*!< bit 0 */
-#define ADC_SMPR1_SMP1_1        ((uint32_t)0x00000010U) /*!< bit 1 */
-#define ADC_SMPR1_SMP1_2        ((uint32_t)0x00000020U) /*!< bit 2 */
-
-#define ADC_SMPR1_SMP2          ((uint32_t)0x000001C0U) /*!< ADC channel 2 sampling time selection  */
-#define ADC_SMPR1_SMP2_0        ((uint32_t)0x00000040U) /*!< bit 0 */
-#define ADC_SMPR1_SMP2_1        ((uint32_t)0x00000080U) /*!< bit 1 */
-#define ADC_SMPR1_SMP2_2        ((uint32_t)0x00000100U) /*!< bit 2 */
-
-#define ADC_SMPR1_SMP3          ((uint32_t)0x00000E00U) /*!< ADC channel 3 sampling time selection  */
-#define ADC_SMPR1_SMP3_0        ((uint32_t)0x00000200U) /*!< bit 0 */
-#define ADC_SMPR1_SMP3_1        ((uint32_t)0x00000400U) /*!< bit 1 */
-#define ADC_SMPR1_SMP3_2        ((uint32_t)0x00000800U) /*!< bit 2 */
-
-#define ADC_SMPR1_SMP4          ((uint32_t)0x00007000U) /*!< ADC channel 4 sampling time selection  */
-#define ADC_SMPR1_SMP4_0        ((uint32_t)0x00001000U) /*!< bit 0 */
-#define ADC_SMPR1_SMP4_1        ((uint32_t)0x00002000U) /*!< bit 1 */
-#define ADC_SMPR1_SMP4_2        ((uint32_t)0x00004000U) /*!< bit 2 */
-
-#define ADC_SMPR1_SMP5          ((uint32_t)0x00038000U) /*!< ADC channel 5 sampling time selection  */
-#define ADC_SMPR1_SMP5_0        ((uint32_t)0x00008000U) /*!< bit 0 */
-#define ADC_SMPR1_SMP5_1        ((uint32_t)0x00010000U) /*!< bit 1 */
-#define ADC_SMPR1_SMP5_2        ((uint32_t)0x00020000U) /*!< bit 2 */
-
-#define ADC_SMPR1_SMP6          ((uint32_t)0x001C0000U) /*!< ADC channel 6 sampling time selection  */
-#define ADC_SMPR1_SMP6_0        ((uint32_t)0x00040000U) /*!< bit 0 */
-#define ADC_SMPR1_SMP6_1        ((uint32_t)0x00080000U) /*!< bit 1 */
-#define ADC_SMPR1_SMP6_2        ((uint32_t)0x00100000U) /*!< bit 2 */
-
-#define ADC_SMPR1_SMP7          ((uint32_t)0x00E00000U) /*!< ADC channel 7 sampling time selection  */
-#define ADC_SMPR1_SMP7_0        ((uint32_t)0x00200000U) /*!< bit 0 */
-#define ADC_SMPR1_SMP7_1        ((uint32_t)0x00400000U) /*!< bit 1 */
-#define ADC_SMPR1_SMP7_2        ((uint32_t)0x00800000U) /*!< bit 2 */
-
-#define ADC_SMPR1_SMP8          ((uint32_t)0x07000000U) /*!< ADC channel 8 sampling time selection  */
-#define ADC_SMPR1_SMP8_0        ((uint32_t)0x01000000U) /*!< bit 0 */
-#define ADC_SMPR1_SMP8_1        ((uint32_t)0x02000000U) /*!< bit 1 */
-#define ADC_SMPR1_SMP8_2        ((uint32_t)0x04000000U) /*!< bit 2 */
-
-#define ADC_SMPR1_SMP9          ((uint32_t)0x38000000U) /*!< ADC channel 9 sampling time selection  */
-#define ADC_SMPR1_SMP9_0        ((uint32_t)0x08000000U) /*!< bit 0 */
-#define ADC_SMPR1_SMP9_1        ((uint32_t)0x10000000U) /*!< bit 1 */
-#define ADC_SMPR1_SMP9_2        ((uint32_t)0x20000000U) /*!< bit 2 */
-
-/********************  Bit definition for ADC_SMPR2 register  *****************/
-#define ADC_SMPR2_SMP10         ((uint32_t)0x00000007U) /*!< ADC channel 10 sampling time selection  */
-#define ADC_SMPR2_SMP10_0       ((uint32_t)0x00000001U) /*!< bit 0 */
-#define ADC_SMPR2_SMP10_1       ((uint32_t)0x00000002U) /*!< bit 1 */
-#define ADC_SMPR2_SMP10_2       ((uint32_t)0x00000004U) /*!< bit 2 */
-
-#define ADC_SMPR2_SMP11         ((uint32_t)0x00000038U) /*!< ADC channel 11 sampling time selection  */
-#define ADC_SMPR2_SMP11_0       ((uint32_t)0x00000008U) /*!< bit 0 */
-#define ADC_SMPR2_SMP11_1       ((uint32_t)0x00000010U) /*!< bit 1 */
-#define ADC_SMPR2_SMP11_2       ((uint32_t)0x00000020U) /*!< bit 2 */
-
-#define ADC_SMPR2_SMP12         ((uint32_t)0x000001C0U) /*!< ADC channel 12 sampling time selection  */
-#define ADC_SMPR2_SMP12_0       ((uint32_t)0x00000040U) /*!< bit 0 */
-#define ADC_SMPR2_SMP12_1       ((uint32_t)0x00000080U) /*!< bit 1 */
-#define ADC_SMPR2_SMP12_2       ((uint32_t)0x00000100U) /*!< bit 2 */
-
-#define ADC_SMPR2_SMP13         ((uint32_t)0x00000E00U) /*!< ADC channel 13 sampling time selection  */
-#define ADC_SMPR2_SMP13_0       ((uint32_t)0x00000200U) /*!< bit 0 */
-#define ADC_SMPR2_SMP13_1       ((uint32_t)0x00000400U) /*!< bit 1 */
-#define ADC_SMPR2_SMP13_2       ((uint32_t)0x00000800U) /*!< bit 2 */
-
-#define ADC_SMPR2_SMP14         ((uint32_t)0x00007000U) /*!< ADC channel 14 sampling time selection  */
-#define ADC_SMPR2_SMP14_0       ((uint32_t)0x00001000U) /*!< bit 0 */
-#define ADC_SMPR2_SMP14_1       ((uint32_t)0x00002000U) /*!< bit 1 */
-#define ADC_SMPR2_SMP14_2       ((uint32_t)0x00004000U) /*!< bit 2 */
-
-#define ADC_SMPR2_SMP15         ((uint32_t)0x00038000U) /*!< ADC channel 15 sampling time selection  */
-#define ADC_SMPR2_SMP15_0       ((uint32_t)0x00008000U) /*!< bit 0 */
-#define ADC_SMPR2_SMP15_1       ((uint32_t)0x00010000U) /*!< bit 1 */
-#define ADC_SMPR2_SMP15_2       ((uint32_t)0x00020000U) /*!< bit 2 */
-
-#define ADC_SMPR2_SMP16         ((uint32_t)0x001C0000U) /*!< ADC channel 16 sampling time selection  */
-#define ADC_SMPR2_SMP16_0       ((uint32_t)0x00040000U) /*!< bit 0 */
-#define ADC_SMPR2_SMP16_1       ((uint32_t)0x00080000U) /*!< bit 1 */
-#define ADC_SMPR2_SMP16_2       ((uint32_t)0x00100000U) /*!< bit 2 */
-
-#define ADC_SMPR2_SMP17         ((uint32_t)0x00E00000U) /*!< ADC channel 17 sampling time selection  */
-#define ADC_SMPR2_SMP17_0       ((uint32_t)0x00200000U) /*!< bit 0 */
-#define ADC_SMPR2_SMP17_1       ((uint32_t)0x00400000U) /*!< bit 1 */
-#define ADC_SMPR2_SMP17_2       ((uint32_t)0x00800000U) /*!< bit 2 */
-
-#define ADC_SMPR2_SMP18         ((uint32_t)0x07000000U) /*!< ADC channel 18 sampling time selection  */
-#define ADC_SMPR2_SMP18_0       ((uint32_t)0x01000000U) /*!< bit 0 */
-#define ADC_SMPR2_SMP18_1       ((uint32_t)0x02000000U) /*!< bit 1 */
-#define ADC_SMPR2_SMP18_2       ((uint32_t)0x04000000U) /*!< bit 2 */
-
-/********************  Bit definition for ADC_TR1 register  *******************/
-#define ADC_TR1_LT1             ((uint32_t)0x00000FFFU) /*!< ADC analog watchdog 1 threshold low */
-#define ADC_TR1_LT1_0           ((uint32_t)0x00000001U) /*!< bit 0 */
-#define ADC_TR1_LT1_1           ((uint32_t)0x00000002U) /*!< bit 1 */
-#define ADC_TR1_LT1_2           ((uint32_t)0x00000004U) /*!< bit 2 */
-#define ADC_TR1_LT1_3           ((uint32_t)0x00000008U) /*!< bit 3 */
-#define ADC_TR1_LT1_4           ((uint32_t)0x00000010U) /*!< bit 4 */
-#define ADC_TR1_LT1_5           ((uint32_t)0x00000020U) /*!< bit 5 */
-#define ADC_TR1_LT1_6           ((uint32_t)0x00000040U) /*!< bit 6 */
-#define ADC_TR1_LT1_7           ((uint32_t)0x00000080U) /*!< bit 7 */
-#define ADC_TR1_LT1_8           ((uint32_t)0x00000100U) /*!< bit 8 */
-#define ADC_TR1_LT1_9           ((uint32_t)0x00000200U) /*!< bit 9 */
-#define ADC_TR1_LT1_10          ((uint32_t)0x00000400U) /*!< bit 10 */
-#define ADC_TR1_LT1_11          ((uint32_t)0x00000800U) /*!< bit 11 */
-
-#define ADC_TR1_HT1             ((uint32_t)0x0FFF0000U) /*!< ADC Analog watchdog 1 threshold high */
-#define ADC_TR1_HT1_0           ((uint32_t)0x00010000U) /*!< bit 0 */
-#define ADC_TR1_HT1_1           ((uint32_t)0x00020000U) /*!< bit 1 */
-#define ADC_TR1_HT1_2           ((uint32_t)0x00040000U) /*!< bit 2 */
-#define ADC_TR1_HT1_3           ((uint32_t)0x00080000U) /*!< bit 3 */
-#define ADC_TR1_HT1_4           ((uint32_t)0x00100000U) /*!< bit 4 */
-#define ADC_TR1_HT1_5           ((uint32_t)0x00200000U) /*!< bit 5 */
-#define ADC_TR1_HT1_6           ((uint32_t)0x00400000U) /*!< bit 6 */
-#define ADC_TR1_HT1_7           ((uint32_t)0x00800000U) /*!< bit 7 */
-#define ADC_TR1_HT1_8           ((uint32_t)0x01000000U) /*!< bit 8 */
-#define ADC_TR1_HT1_9           ((uint32_t)0x02000000U) /*!< bit 9 */
-#define ADC_TR1_HT1_10          ((uint32_t)0x04000000U) /*!< bit 10 */
-#define ADC_TR1_HT1_11          ((uint32_t)0x08000000U) /*!< bit 11 */
-
-/********************  Bit definition for ADC_TR2 register  *******************/
-#define ADC_TR2_LT2             ((uint32_t)0x000000FFU) /*!< ADC analog watchdog 2 threshold low */
-#define ADC_TR2_LT2_0           ((uint32_t)0x00000001U) /*!< bit 0 */
-#define ADC_TR2_LT2_1           ((uint32_t)0x00000002U) /*!< bit 1 */
-#define ADC_TR2_LT2_2           ((uint32_t)0x00000004U) /*!< bit 2 */
-#define ADC_TR2_LT2_3           ((uint32_t)0x00000008U) /*!< bit 3 */
-#define ADC_TR2_LT2_4           ((uint32_t)0x00000010U) /*!< bit 4 */
-#define ADC_TR2_LT2_5           ((uint32_t)0x00000020U) /*!< bit 5 */
-#define ADC_TR2_LT2_6           ((uint32_t)0x00000040U) /*!< bit 6 */
-#define ADC_TR2_LT2_7           ((uint32_t)0x00000080U) /*!< bit 7 */
-
-#define ADC_TR2_HT2             ((uint32_t)0x00FF0000U) /*!< ADC analog watchdog 2 threshold high */
-#define ADC_TR2_HT2_0           ((uint32_t)0x00010000U) /*!< bit 0 */
-#define ADC_TR2_HT2_1           ((uint32_t)0x00020000U) /*!< bit 1 */
-#define ADC_TR2_HT2_2           ((uint32_t)0x00040000U) /*!< bit 2 */
-#define ADC_TR2_HT2_3           ((uint32_t)0x00080000U) /*!< bit 3 */
-#define ADC_TR2_HT2_4           ((uint32_t)0x00100000U) /*!< bit 4 */
-#define ADC_TR2_HT2_5           ((uint32_t)0x00200000U) /*!< bit 5 */
-#define ADC_TR2_HT2_6           ((uint32_t)0x00400000U) /*!< bit 6 */
-#define ADC_TR2_HT2_7           ((uint32_t)0x00800000U) /*!< bit 7 */
-
-/********************  Bit definition for ADC_TR3 register  *******************/
-#define ADC_TR3_LT3             ((uint32_t)0x000000FFU) /*!< ADC analog watchdog 3 threshold low */
-#define ADC_TR3_LT3_0           ((uint32_t)0x00000001U) /*!< bit 0 */
-#define ADC_TR3_LT3_1           ((uint32_t)0x00000002U) /*!< bit 1 */
-#define ADC_TR3_LT3_2           ((uint32_t)0x00000004U) /*!< bit 2 */
-#define ADC_TR3_LT3_3           ((uint32_t)0x00000008U) /*!< bit 3 */
-#define ADC_TR3_LT3_4           ((uint32_t)0x00000010U) /*!< bit 4 */
-#define ADC_TR3_LT3_5           ((uint32_t)0x00000020U) /*!< bit 5 */
-#define ADC_TR3_LT3_6           ((uint32_t)0x00000040U) /*!< bit 6 */
-#define ADC_TR3_LT3_7           ((uint32_t)0x00000080U) /*!< bit 7 */
-
-#define ADC_TR3_HT3             ((uint32_t)0x00FF0000U) /*!< ADC analog watchdog 3 threshold high */
-#define ADC_TR3_HT3_0           ((uint32_t)0x00010000U) /*!< bit 0 */
-#define ADC_TR3_HT3_1           ((uint32_t)0x00020000U) /*!< bit 1 */
-#define ADC_TR3_HT3_2           ((uint32_t)0x00040000U) /*!< bit 2 */
-#define ADC_TR3_HT3_3           ((uint32_t)0x00080000U) /*!< bit 3 */
-#define ADC_TR3_HT3_4           ((uint32_t)0x00100000U) /*!< bit 4 */
-#define ADC_TR3_HT3_5           ((uint32_t)0x00200000U) /*!< bit 5 */
-#define ADC_TR3_HT3_6           ((uint32_t)0x00400000U) /*!< bit 6 */
-#define ADC_TR3_HT3_7           ((uint32_t)0x00800000U) /*!< bit 7 */
-
-/********************  Bit definition for ADC_SQR1 register  ******************/
-#define ADC_SQR1_L              ((uint32_t)0x0000000FU) /*!< ADC group regular sequencer scan length */
-#define ADC_SQR1_L_0            ((uint32_t)0x00000001U) /*!< bit 0 */
-#define ADC_SQR1_L_1            ((uint32_t)0x00000002U) /*!< bit 1 */
-#define ADC_SQR1_L_2            ((uint32_t)0x00000004U) /*!< bit 2 */
-#define ADC_SQR1_L_3            ((uint32_t)0x00000008U) /*!< bit 3 */
-
-#define ADC_SQR1_SQ1            ((uint32_t)0x000007C0U) /*!< ADC group regular sequencer rank 1 */
-#define ADC_SQR1_SQ1_0          ((uint32_t)0x00000040U) /*!< bit 0 */
-#define ADC_SQR1_SQ1_1          ((uint32_t)0x00000080U) /*!< bit 1 */
-#define ADC_SQR1_SQ1_2          ((uint32_t)0x00000100U) /*!< bit 2 */
-#define ADC_SQR1_SQ1_3          ((uint32_t)0x00000200U) /*!< bit 3 */
-#define ADC_SQR1_SQ1_4          ((uint32_t)0x00000400U) /*!< bit 4 */
-
-#define ADC_SQR1_SQ2            ((uint32_t)0x0001F000U) /*!< ADC group regular sequencer rank 2 */
-#define ADC_SQR1_SQ2_0          ((uint32_t)0x00001000U) /*!< bit 0 */
-#define ADC_SQR1_SQ2_1          ((uint32_t)0x00002000U) /*!< bit 1 */
-#define ADC_SQR1_SQ2_2          ((uint32_t)0x00004000U) /*!< bit 2 */
-#define ADC_SQR1_SQ2_3          ((uint32_t)0x00008000U) /*!< bit 3 */
-#define ADC_SQR1_SQ2_4          ((uint32_t)0x00010000U) /*!< bit 4 */
-
-#define ADC_SQR1_SQ3            ((uint32_t)0x007C0000U) /*!< ADC group regular sequencer rank 3 */
-#define ADC_SQR1_SQ3_0          ((uint32_t)0x00040000U) /*!< bit 0 */
-#define ADC_SQR1_SQ3_1          ((uint32_t)0x00080000U) /*!< bit 1 */
-#define ADC_SQR1_SQ3_2          ((uint32_t)0x00100000U) /*!< bit 2 */
-#define ADC_SQR1_SQ3_3          ((uint32_t)0x00200000U) /*!< bit 3 */
-#define ADC_SQR1_SQ3_4          ((uint32_t)0x00400000U) /*!< bit 4 */
-
-#define ADC_SQR1_SQ4            ((uint32_t)0x1F000000U) /*!< ADC group regular sequencer rank 4 */
-#define ADC_SQR1_SQ4_0          ((uint32_t)0x01000000U) /*!< bit 0 */
-#define ADC_SQR1_SQ4_1          ((uint32_t)0x02000000U) /*!< bit 1 */
-#define ADC_SQR1_SQ4_2          ((uint32_t)0x04000000U) /*!< bit 2 */
-#define ADC_SQR1_SQ4_3          ((uint32_t)0x08000000U) /*!< bit 3 */
-#define ADC_SQR1_SQ4_4          ((uint32_t)0x10000000U) /*!< bit 4 */
-
-/********************  Bit definition for ADC_SQR2 register  ******************/
-#define ADC_SQR2_SQ5            ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 5 */
-#define ADC_SQR2_SQ5_0          ((uint32_t)0x00000001U) /*!< bit 0 */
-#define ADC_SQR2_SQ5_1          ((uint32_t)0x00000002U) /*!< bit 1 */
-#define ADC_SQR2_SQ5_2          ((uint32_t)0x00000004U) /*!< bit 2 */
-#define ADC_SQR2_SQ5_3          ((uint32_t)0x00000008U) /*!< bit 3 */
-#define ADC_SQR2_SQ5_4          ((uint32_t)0x00000010U) /*!< bit 4 */
-
-#define ADC_SQR2_SQ6            ((uint32_t)0x000007C0U) /*!< ADC group regular sequencer rank 6 */
-#define ADC_SQR2_SQ6_0          ((uint32_t)0x00000040U) /*!< bit 0 */
-#define ADC_SQR2_SQ6_1          ((uint32_t)0x00000080U) /*!< bit 1 */
-#define ADC_SQR2_SQ6_2          ((uint32_t)0x00000100U) /*!< bit 2 */
-#define ADC_SQR2_SQ6_3          ((uint32_t)0x00000200U) /*!< bit 3 */
-#define ADC_SQR2_SQ6_4          ((uint32_t)0x00000400U) /*!< bit 4 */
-
-#define ADC_SQR2_SQ7            ((uint32_t)0x0001F000U) /*!< ADC group regular sequencer rank 7 */
-#define ADC_SQR2_SQ7_0          ((uint32_t)0x00001000U) /*!< bit 0 */
-#define ADC_SQR2_SQ7_1          ((uint32_t)0x00002000U) /*!< bit 1 */
-#define ADC_SQR2_SQ7_2          ((uint32_t)0x00004000U) /*!< bit 2 */
-#define ADC_SQR2_SQ7_3          ((uint32_t)0x00008000U) /*!< bit 3 */
-#define ADC_SQR2_SQ7_4          ((uint32_t)0x00010000U) /*!< bit 4 */
-
-#define ADC_SQR2_SQ8            ((uint32_t)0x007C0000U) /*!< ADC group regular sequencer rank 8 */
-#define ADC_SQR2_SQ8_0          ((uint32_t)0x00040000U) /*!< bit 0 */
-#define ADC_SQR2_SQ8_1          ((uint32_t)0x00080000U) /*!< bit 1 */
-#define ADC_SQR2_SQ8_2          ((uint32_t)0x00100000U) /*!< bit 2 */
-#define ADC_SQR2_SQ8_3          ((uint32_t)0x00200000U) /*!< bit 3 */
-#define ADC_SQR2_SQ8_4          ((uint32_t)0x00400000U) /*!< bit 4 */
-
-#define ADC_SQR2_SQ9            ((uint32_t)0x1F000000U) /*!< ADC group regular sequencer rank 9 */
-#define ADC_SQR2_SQ9_0          ((uint32_t)0x01000000U) /*!< bit 0 */
-#define ADC_SQR2_SQ9_1          ((uint32_t)0x02000000U) /*!< bit 1 */
-#define ADC_SQR2_SQ9_2          ((uint32_t)0x04000000U) /*!< bit 2 */
-#define ADC_SQR2_SQ9_3          ((uint32_t)0x08000000U) /*!< bit 3 */
-#define ADC_SQR2_SQ9_4          ((uint32_t)0x10000000U) /*!< bit 4 */
-
-/********************  Bit definition for ADC_SQR3 register  ******************/
-#define ADC_SQR3_SQ10           ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 10 */
-#define ADC_SQR3_SQ10_0         ((uint32_t)0x00000001U) /*!< bit 0 */
-#define ADC_SQR3_SQ10_1         ((uint32_t)0x00000002U) /*!< bit 1 */
-#define ADC_SQR3_SQ10_2         ((uint32_t)0x00000004U) /*!< bit 2 */
-#define ADC_SQR3_SQ10_3         ((uint32_t)0x00000008U) /*!< bit 3 */
-#define ADC_SQR3_SQ10_4         ((uint32_t)0x00000010U) /*!< bit 4 */
-
-#define ADC_SQR3_SQ11           ((uint32_t)0x000007C0U) /*!< ADC group regular sequencer rank 11 */
-#define ADC_SQR3_SQ11_0         ((uint32_t)0x00000040U) /*!< bit 0 */
-#define ADC_SQR3_SQ11_1         ((uint32_t)0x00000080U) /*!< bit 1 */
-#define ADC_SQR3_SQ11_2         ((uint32_t)0x00000100U) /*!< bit 2 */
-#define ADC_SQR3_SQ11_3         ((uint32_t)0x00000200U) /*!< bit 3 */
-#define ADC_SQR3_SQ11_4         ((uint32_t)0x00000400U) /*!< bit 4 */
-
-#define ADC_SQR3_SQ12           ((uint32_t)0x0001F000U) /*!< ADC group regular sequencer rank 12 */
-#define ADC_SQR3_SQ12_0         ((uint32_t)0x00001000U) /*!< bit 0 */
-#define ADC_SQR3_SQ12_1         ((uint32_t)0x00002000U) /*!< bit 1 */
-#define ADC_SQR3_SQ12_2         ((uint32_t)0x00004000U) /*!< bit 2 */
-#define ADC_SQR3_SQ12_3         ((uint32_t)0x00008000U) /*!< bit 3 */
-#define ADC_SQR3_SQ12_4         ((uint32_t)0x00010000U) /*!< bit 4 */
-
-#define ADC_SQR3_SQ13           ((uint32_t)0x007C0000U) /*!< ADC group regular sequencer rank 13 */
-#define ADC_SQR3_SQ13_0         ((uint32_t)0x00040000U) /*!< bit 0 */
-#define ADC_SQR3_SQ13_1         ((uint32_t)0x00080000U) /*!< bit 1 */
-#define ADC_SQR3_SQ13_2         ((uint32_t)0x00100000U) /*!< bit 2 */
-#define ADC_SQR3_SQ13_3         ((uint32_t)0x00200000U) /*!< bit 3 */
-#define ADC_SQR3_SQ13_4         ((uint32_t)0x00400000U) /*!< bit 4 */
-
-#define ADC_SQR3_SQ14           ((uint32_t)0x1F000000U) /*!< ADC group regular sequencer rank 14 */
-#define ADC_SQR3_SQ14_0         ((uint32_t)0x01000000U) /*!< bit 0 */
-#define ADC_SQR3_SQ14_1         ((uint32_t)0x02000000U) /*!< bit 1 */
-#define ADC_SQR3_SQ14_2         ((uint32_t)0x04000000U) /*!< bit 2 */
-#define ADC_SQR3_SQ14_3         ((uint32_t)0x08000000U) /*!< bit 3 */
-#define ADC_SQR3_SQ14_4         ((uint32_t)0x10000000U) /*!< bit 4 */
-
-/********************  Bit definition for ADC_SQR4 register  ******************/
-#define ADC_SQR4_SQ15           ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 15 */
-#define ADC_SQR4_SQ15_0         ((uint32_t)0x00000001U) /*!< bit 0 */
-#define ADC_SQR4_SQ15_1         ((uint32_t)0x00000002U) /*!< bit 1 */
-#define ADC_SQR4_SQ15_2         ((uint32_t)0x00000004U) /*!< bit 2 */
-#define ADC_SQR4_SQ15_3         ((uint32_t)0x00000008U) /*!< bit 3 */
-#define ADC_SQR4_SQ15_4         ((uint32_t)0x00000010U) /*!<5 bit 4 */
-
-#define ADC_SQR4_SQ16           ((uint32_t)0x000007C0U) /*!< ADC group regular sequencer rank 16 */
-#define ADC_SQR4_SQ16_0         ((uint32_t)0x00000040U) /*!< bit 0 */
-#define ADC_SQR4_SQ16_1         ((uint32_t)0x00000080U) /*!< bit 1 */
-#define ADC_SQR4_SQ16_2         ((uint32_t)0x00000100U) /*!< bit 2 */
-#define ADC_SQR4_SQ16_3         ((uint32_t)0x00000200U) /*!< bit 3 */
-#define ADC_SQR4_SQ16_4         ((uint32_t)0x00000400U) /*!< bit 4 */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_RDATA            ((uint32_t)0x0000FFFFU) /*!< ADC group regular conversion data */
-#define ADC_DR_RDATA_0          ((uint32_t)0x00000001U) /*!< bit 0 */
-#define ADC_DR_RDATA_1          ((uint32_t)0x00000002U) /*!< bit 1 */
-#define ADC_DR_RDATA_2          ((uint32_t)0x00000004U) /*!< bit 2 */
-#define ADC_DR_RDATA_3          ((uint32_t)0x00000008U) /*!< bit 3 */
-#define ADC_DR_RDATA_4          ((uint32_t)0x00000010U) /*!< bit 4 */
-#define ADC_DR_RDATA_5          ((uint32_t)0x00000020U) /*!< bit 5 */
-#define ADC_DR_RDATA_6          ((uint32_t)0x00000040U) /*!< bit 6 */
-#define ADC_DR_RDATA_7          ((uint32_t)0x00000080U) /*!< bit 7 */
-#define ADC_DR_RDATA_8          ((uint32_t)0x00000100U) /*!< bit 8 */
-#define ADC_DR_RDATA_9          ((uint32_t)0x00000200U) /*!< bit 9 */
-#define ADC_DR_RDATA_10         ((uint32_t)0x00000400U) /*!< bit 10 */
-#define ADC_DR_RDATA_11         ((uint32_t)0x00000800U) /*!< bit 11 */
-#define ADC_DR_RDATA_12         ((uint32_t)0x00001000U) /*!< bit 12 */
-#define ADC_DR_RDATA_13         ((uint32_t)0x00002000U) /*!< bit 13 */
-#define ADC_DR_RDATA_14         ((uint32_t)0x00004000U) /*!< bit 14 */
-#define ADC_DR_RDATA_15         ((uint32_t)0x00008000U) /*!< bit 15 */
-
-/********************  Bit definition for ADC_JSQR register  ******************/
-#define ADC_JSQR_JL             ((uint32_t)0x00000003U) /*!< ADC group injected sequencer scan length */
-#define ADC_JSQR_JL_0           ((uint32_t)0x00000001U) /*!< bit 0 */
-#define ADC_JSQR_JL_1           ((uint32_t)0x00000002U) /*!< bit 1 */
-
-#define ADC_JSQR_JEXTSEL        ((uint32_t)0x0000003CU) /*!< ADC group injected external trigger source */
-#define ADC_JSQR_JEXTSEL_0      ((uint32_t)0x00000004U) /*!< bit 0 */
-#define ADC_JSQR_JEXTSEL_1      ((uint32_t)0x00000008U) /*!< bit 1 */
-#define ADC_JSQR_JEXTSEL_2      ((uint32_t)0x00000010U) /*!< bit 2 */
-#define ADC_JSQR_JEXTSEL_3      ((uint32_t)0x00000020U) /*!< bit 3 */
-
-#define ADC_JSQR_JEXTEN         ((uint32_t)0x000000C0U) /*!< ADC group injected external trigger polarity */
-#define ADC_JSQR_JEXTEN_0       ((uint32_t)0x00000040U) /*!< bit 0 */
-#define ADC_JSQR_JEXTEN_1       ((uint32_t)0x00000080U) /*!< bit 1 */
-
-#define ADC_JSQR_JSQ1           ((uint32_t)0x00001F00U) /*!< ADC group injected sequencer rank 1 */
-#define ADC_JSQR_JSQ1_0         ((uint32_t)0x00000100U) /*!< bit 0 */
-#define ADC_JSQR_JSQ1_1         ((uint32_t)0x00000200U) /*!< bit 1 */
-#define ADC_JSQR_JSQ1_2         ((uint32_t)0x00000400U) /*!< bit 2 */
-#define ADC_JSQR_JSQ1_3         ((uint32_t)0x00000800U) /*!< bit 3 */
-#define ADC_JSQR_JSQ1_4         ((uint32_t)0x00001000U) /*!< bit 4 */
-
-#define ADC_JSQR_JSQ2           ((uint32_t)0x0007C000U) /*!< ADC group injected sequencer rank 2 */
-#define ADC_JSQR_JSQ2_0         ((uint32_t)0x00004000U) /*!< bit 0 */
-#define ADC_JSQR_JSQ2_1         ((uint32_t)0x00008000U) /*!< bit 1 */
-#define ADC_JSQR_JSQ2_2         ((uint32_t)0x00010000U) /*!< bit 2 */
-#define ADC_JSQR_JSQ2_3         ((uint32_t)0x00020000U) /*!< bit 3 */
-#define ADC_JSQR_JSQ2_4         ((uint32_t)0x00040000U) /*!< bit 4 */
-
-#define ADC_JSQR_JSQ3           ((uint32_t)0x01F00000U) /*!< ADC group injected sequencer rank 3 */
-#define ADC_JSQR_JSQ3_0         ((uint32_t)0x00100000U) /*!< bit 0 */
-#define ADC_JSQR_JSQ3_1         ((uint32_t)0x00200000U) /*!< bit 1 */
-#define ADC_JSQR_JSQ3_2         ((uint32_t)0x00400000U) /*!< bit 2 */
-#define ADC_JSQR_JSQ3_3         ((uint32_t)0x00800000U) /*!< bit 3 */
-#define ADC_JSQR_JSQ3_4         ((uint32_t)0x01000000U) /*!< bit 4 */
-
-#define ADC_JSQR_JSQ4           ((uint32_t)0x7C000000U) /*!< ADC group injected sequencer rank 4 */
-#define ADC_JSQR_JSQ4_0         ((uint32_t)0x04000000U) /*!< bit 0 */
-#define ADC_JSQR_JSQ4_1         ((uint32_t)0x08000000U) /*!< bit 1 */
-#define ADC_JSQR_JSQ4_2         ((uint32_t)0x10000000U) /*!< bit 2 */
-#define ADC_JSQR_JSQ4_3         ((uint32_t)0x20000000U) /*!< bit 3 */
-#define ADC_JSQR_JSQ4_4         ((uint32_t)0x40000000U) /*!< bit 4 */
-
-
-/********************  Bit definition for ADC_OFR1 register  ******************/
-#define ADC_OFR1_OFFSET1        ((uint32_t)0x00000FFFU) /*!< ADC offset number 1 offset level */
-#define ADC_OFR1_OFFSET1_0      ((uint32_t)0x00000001U) /*!< bit 0 */
-#define ADC_OFR1_OFFSET1_1      ((uint32_t)0x00000002U) /*!< bit 1 */
-#define ADC_OFR1_OFFSET1_2      ((uint32_t)0x00000004U) /*!< bit 2 */
-#define ADC_OFR1_OFFSET1_3      ((uint32_t)0x00000008U) /*!< bit 3 */
-#define ADC_OFR1_OFFSET1_4      ((uint32_t)0x00000010U) /*!< bit 4 */
-#define ADC_OFR1_OFFSET1_5      ((uint32_t)0x00000020U) /*!< bit 5 */
-#define ADC_OFR1_OFFSET1_6      ((uint32_t)0x00000040U) /*!< bit 6 */
-#define ADC_OFR1_OFFSET1_7      ((uint32_t)0x00000080U) /*!< bit 7 */
-#define ADC_OFR1_OFFSET1_8      ((uint32_t)0x00000100U) /*!< bit 8 */
-#define ADC_OFR1_OFFSET1_9      ((uint32_t)0x00000200U) /*!< bit 9 */
-#define ADC_OFR1_OFFSET1_10     ((uint32_t)0x00000400U) /*!< bit 10 */
-#define ADC_OFR1_OFFSET1_11     ((uint32_t)0x00000800U) /*!< bit 11 */
-
-#define ADC_OFR1_OFFSET1_CH     ((uint32_t)0x7C000000U) /*!< ADC offset number 1 channel selection */
-#define ADC_OFR1_OFFSET1_CH_0   ((uint32_t)0x04000000U) /*!<  bit 0 */
-#define ADC_OFR1_OFFSET1_CH_1   ((uint32_t)0x08000000U) /*!<  bit 1 */
-#define ADC_OFR1_OFFSET1_CH_2   ((uint32_t)0x10000000U) /*!<  bit 2 */
-#define ADC_OFR1_OFFSET1_CH_3   ((uint32_t)0x20000000U) /*!<  bit 3 */
-#define ADC_OFR1_OFFSET1_CH_4   ((uint32_t)0x40000000U) /*!<  bit 4 */
-
-#define ADC_OFR1_OFFSET1_EN     ((uint32_t)0x80000000U) /*!< ADC offset number 1 enable */
-
-/********************  Bit definition for ADC_OFR2 register  ******************/
-#define ADC_OFR2_OFFSET2        ((uint32_t)0x00000FFFU) /*!< ADC offset number 2 offset level */
-#define ADC_OFR2_OFFSET2_0      ((uint32_t)0x00000001U) /*!< bit 0 */
-#define ADC_OFR2_OFFSET2_1      ((uint32_t)0x00000002U) /*!< bit 1 */
-#define ADC_OFR2_OFFSET2_2      ((uint32_t)0x00000004U) /*!< bit 2 */
-#define ADC_OFR2_OFFSET2_3      ((uint32_t)0x00000008U) /*!< bit 3 */
-#define ADC_OFR2_OFFSET2_4      ((uint32_t)0x00000010U) /*!< bit 4 */
-#define ADC_OFR2_OFFSET2_5      ((uint32_t)0x00000020U) /*!< bit 5 */
-#define ADC_OFR2_OFFSET2_6      ((uint32_t)0x00000040U) /*!< bit 6 */
-#define ADC_OFR2_OFFSET2_7      ((uint32_t)0x00000080U) /*!< bit 7 */
-#define ADC_OFR2_OFFSET2_8      ((uint32_t)0x00000100U) /*!< bit 8 */
-#define ADC_OFR2_OFFSET2_9      ((uint32_t)0x00000200U) /*!< bit 9 */
-#define ADC_OFR2_OFFSET2_10     ((uint32_t)0x00000400U) /*!< bit 10 */
-#define ADC_OFR2_OFFSET2_11     ((uint32_t)0x00000800U) /*!< bit 11 */
-
-#define ADC_OFR2_OFFSET2_CH     ((uint32_t)0x7C000000U) /*!< ADC offset number 2 channel selection */
-#define ADC_OFR2_OFFSET2_CH_0   ((uint32_t)0x04000000U) /*!< bit 0 */
-#define ADC_OFR2_OFFSET2_CH_1   ((uint32_t)0x08000000U) /*!< bit 1 */
-#define ADC_OFR2_OFFSET2_CH_2   ((uint32_t)0x10000000U) /*!< bit 2 */
-#define ADC_OFR2_OFFSET2_CH_3   ((uint32_t)0x20000000U) /*!< bit 3 */
-#define ADC_OFR2_OFFSET2_CH_4   ((uint32_t)0x40000000U) /*!< bit 4 */
-
-#define ADC_OFR2_OFFSET2_EN     ((uint32_t)0x80000000U) /*!< ADC offset number 2 enable */
-
-/********************  Bit definition for ADC_OFR3 register  ******************/
-#define ADC_OFR3_OFFSET3        ((uint32_t)0x00000FFFU) /*!< ADC offset number 3 offset level */
-#define ADC_OFR3_OFFSET3_0      ((uint32_t)0x00000001U) /*!< bit 0 */
-#define ADC_OFR3_OFFSET3_1      ((uint32_t)0x00000002U) /*!< bit 1 */
-#define ADC_OFR3_OFFSET3_2      ((uint32_t)0x00000004U) /*!< bit 2 */
-#define ADC_OFR3_OFFSET3_3      ((uint32_t)0x00000008U) /*!< bit 3 */
-#define ADC_OFR3_OFFSET3_4      ((uint32_t)0x00000010U) /*!< bit 4 */
-#define ADC_OFR3_OFFSET3_5      ((uint32_t)0x00000020U) /*!< bit 5 */
-#define ADC_OFR3_OFFSET3_6      ((uint32_t)0x00000040U) /*!< bit 6 */
-#define ADC_OFR3_OFFSET3_7      ((uint32_t)0x00000080U) /*!< bit 7 */
-#define ADC_OFR3_OFFSET3_8      ((uint32_t)0x00000100U) /*!< bit 8 */
-#define ADC_OFR3_OFFSET3_9      ((uint32_t)0x00000200U) /*!< bit 9 */
-#define ADC_OFR3_OFFSET3_10     ((uint32_t)0x00000400U) /*!< bit 10 */
-#define ADC_OFR3_OFFSET3_11     ((uint32_t)0x00000800U) /*!< bit 11 */
-
-#define ADC_OFR3_OFFSET3_CH     ((uint32_t)0x7C000000U) /*!< ADC offset number 3 channel selection */
-#define ADC_OFR3_OFFSET3_CH_0   ((uint32_t)0x04000000U) /*!< bit 0 */
-#define ADC_OFR3_OFFSET3_CH_1   ((uint32_t)0x08000000U) /*!< bit 1 */
-#define ADC_OFR3_OFFSET3_CH_2   ((uint32_t)0x10000000U) /*!< bit 2 */
-#define ADC_OFR3_OFFSET3_CH_3   ((uint32_t)0x20000000U) /*!< bit 3 */
-#define ADC_OFR3_OFFSET3_CH_4   ((uint32_t)0x40000000U) /*!< bit 4 */
-
-#define ADC_OFR3_OFFSET3_EN     ((uint32_t)0x80000000U) /*!< ADC offset number 3 enable */
-
-/********************  Bit definition for ADC_OFR4 register  ******************/
-#define ADC_OFR4_OFFSET4        ((uint32_t)0x00000FFFU) /*!< ADC offset number 4 offset level */
-#define ADC_OFR4_OFFSET4_0      ((uint32_t)0x00000001U) /*!< bit 0 */
-#define ADC_OFR4_OFFSET4_1      ((uint32_t)0x00000002U) /*!< bit 1 */
-#define ADC_OFR4_OFFSET4_2      ((uint32_t)0x00000004U) /*!< bit 2 */
-#define ADC_OFR4_OFFSET4_3      ((uint32_t)0x00000008U) /*!< bit 3 */
-#define ADC_OFR4_OFFSET4_4      ((uint32_t)0x00000010U) /*!< bit 4 */
-#define ADC_OFR4_OFFSET4_5      ((uint32_t)0x00000020U) /*!< bit 5 */
-#define ADC_OFR4_OFFSET4_6      ((uint32_t)0x00000040U) /*!< bit 6 */
-#define ADC_OFR4_OFFSET4_7      ((uint32_t)0x00000080U) /*!< bit 7 */
-#define ADC_OFR4_OFFSET4_8      ((uint32_t)0x00000100U) /*!< bit 8 */
-#define ADC_OFR4_OFFSET4_9      ((uint32_t)0x00000200U) /*!< bit 9 */
-#define ADC_OFR4_OFFSET4_10     ((uint32_t)0x00000400U) /*!< bit 10 */
-#define ADC_OFR4_OFFSET4_11     ((uint32_t)0x00000800U) /*!< bit 11 */
-
-#define ADC_OFR4_OFFSET4_CH     ((uint32_t)0x7C000000U) /*!< ADC offset number 4 channel selection */
-#define ADC_OFR4_OFFSET4_CH_0   ((uint32_t)0x04000000U) /*!< bit 0 */
-#define ADC_OFR4_OFFSET4_CH_1   ((uint32_t)0x08000000U) /*!< bit 1 */
-#define ADC_OFR4_OFFSET4_CH_2   ((uint32_t)0x10000000U) /*!< bit 2 */
-#define ADC_OFR4_OFFSET4_CH_3   ((uint32_t)0x20000000U) /*!< bit 3 */
-#define ADC_OFR4_OFFSET4_CH_4   ((uint32_t)0x40000000U) /*!< bit 4 */
-
-#define ADC_OFR4_OFFSET4_EN     ((uint32_t)0x80000000U) /*!< ADC offset number 4 enable */
-
-/********************  Bit definition for ADC_JDR1 register  ******************/
-#define ADC_JDR1_JDATA          ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 1 conversion data */
-#define ADC_JDR1_JDATA_0        ((uint32_t)0x00000001U) /*!< bit 0 */
-#define ADC_JDR1_JDATA_1        ((uint32_t)0x00000002U) /*!< bit 1 */
-#define ADC_JDR1_JDATA_2        ((uint32_t)0x00000004U) /*!< bit 2 */
-#define ADC_JDR1_JDATA_3        ((uint32_t)0x00000008U) /*!< bit 3 */
-#define ADC_JDR1_JDATA_4        ((uint32_t)0x00000010U) /*!< bit 4 */
-#define ADC_JDR1_JDATA_5        ((uint32_t)0x00000020U) /*!< bit 5 */
-#define ADC_JDR1_JDATA_6        ((uint32_t)0x00000040U) /*!< bit 6 */
-#define ADC_JDR1_JDATA_7        ((uint32_t)0x00000080U) /*!< bit 7 */
-#define ADC_JDR1_JDATA_8        ((uint32_t)0x00000100U) /*!< bit 8 */
-#define ADC_JDR1_JDATA_9        ((uint32_t)0x00000200U) /*!< bit 9 */
-#define ADC_JDR1_JDATA_10       ((uint32_t)0x00000400U) /*!< bit 10 */
-#define ADC_JDR1_JDATA_11       ((uint32_t)0x00000800U) /*!< bit 11 */
-#define ADC_JDR1_JDATA_12       ((uint32_t)0x00001000U) /*!< bit 12 */
-#define ADC_JDR1_JDATA_13       ((uint32_t)0x00002000U) /*!< bit 13 */
-#define ADC_JDR1_JDATA_14       ((uint32_t)0x00004000U) /*!< bit 14 */
-#define ADC_JDR1_JDATA_15       ((uint32_t)0x00008000U) /*!< bit 15 */
-
-/********************  Bit definition for ADC_JDR2 register  ******************/
-#define ADC_JDR2_JDATA          ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 2 conversion data */
-#define ADC_JDR2_JDATA_0        ((uint32_t)0x00000001U) /*!< bit 0 */
-#define ADC_JDR2_JDATA_1        ((uint32_t)0x00000002U) /*!< bit 1 */
-#define ADC_JDR2_JDATA_2        ((uint32_t)0x00000004U) /*!< bit 2 */
-#define ADC_JDR2_JDATA_3        ((uint32_t)0x00000008U) /*!< bit 3 */
-#define ADC_JDR2_JDATA_4        ((uint32_t)0x00000010U) /*!< bit 4 */
-#define ADC_JDR2_JDATA_5        ((uint32_t)0x00000020U) /*!< bit 5 */
-#define ADC_JDR2_JDATA_6        ((uint32_t)0x00000040U) /*!< bit 6 */
-#define ADC_JDR2_JDATA_7        ((uint32_t)0x00000080U) /*!< bit 7 */
-#define ADC_JDR2_JDATA_8        ((uint32_t)0x00000100U) /*!< bit 8 */
-#define ADC_JDR2_JDATA_9        ((uint32_t)0x00000200U) /*!< bit 9 */
-#define ADC_JDR2_JDATA_10       ((uint32_t)0x00000400U) /*!< bit 10 */
-#define ADC_JDR2_JDATA_11       ((uint32_t)0x00000800U) /*!< bit 11 */
-#define ADC_JDR2_JDATA_12       ((uint32_t)0x00001000U) /*!< bit 12 */
-#define ADC_JDR2_JDATA_13       ((uint32_t)0x00002000U) /*!< bit 13 */
-#define ADC_JDR2_JDATA_14       ((uint32_t)0x00004000U) /*!< bit 14 */
-#define ADC_JDR2_JDATA_15       ((uint32_t)0x00008000U) /*!< bit 15 */
-
-/********************  Bit definition for ADC_JDR3 register  ******************/
-#define ADC_JDR3_JDATA          ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 3 conversion data */
-#define ADC_JDR3_JDATA_0        ((uint32_t)0x00000001U) /*!< bit 0 */
-#define ADC_JDR3_JDATA_1        ((uint32_t)0x00000002U) /*!< bit 1 */
-#define ADC_JDR3_JDATA_2        ((uint32_t)0x00000004U) /*!< bit 2 */
-#define ADC_JDR3_JDATA_3        ((uint32_t)0x00000008U) /*!< bit 3 */
-#define ADC_JDR3_JDATA_4        ((uint32_t)0x00000010U) /*!< bit 4 */
-#define ADC_JDR3_JDATA_5        ((uint32_t)0x00000020U) /*!< bit 5 */
-#define ADC_JDR3_JDATA_6        ((uint32_t)0x00000040U) /*!< bit 6 */
-#define ADC_JDR3_JDATA_7        ((uint32_t)0x00000080U) /*!< bit 7 */
-#define ADC_JDR3_JDATA_8        ((uint32_t)0x00000100U) /*!< bit 8 */
-#define ADC_JDR3_JDATA_9        ((uint32_t)0x00000200U) /*!< bit 9 */
-#define ADC_JDR3_JDATA_10       ((uint32_t)0x00000400U) /*!< bit 10 */
-#define ADC_JDR3_JDATA_11       ((uint32_t)0x00000800U) /*!< bit 11 */
-#define ADC_JDR3_JDATA_12       ((uint32_t)0x00001000U) /*!< bit 12 */
-#define ADC_JDR3_JDATA_13       ((uint32_t)0x00002000U) /*!< bit 13 */
-#define ADC_JDR3_JDATA_14       ((uint32_t)0x00004000U) /*!< bit 14 */
-#define ADC_JDR3_JDATA_15       ((uint32_t)0x00008000U) /*!< bit 15 */
-
-/********************  Bit definition for ADC_JDR4 register  ******************/
-#define ADC_JDR4_JDATA          ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 4 conversion data */
-#define ADC_JDR4_JDATA_0        ((uint32_t)0x00000001U) /*!< bit 0 */
-#define ADC_JDR4_JDATA_1        ((uint32_t)0x00000002U) /*!< bit 1 */
-#define ADC_JDR4_JDATA_2        ((uint32_t)0x00000004U) /*!< bit 2 */
-#define ADC_JDR4_JDATA_3        ((uint32_t)0x00000008U) /*!< bit 3 */
-#define ADC_JDR4_JDATA_4        ((uint32_t)0x00000010U) /*!< bit 4 */
-#define ADC_JDR4_JDATA_5        ((uint32_t)0x00000020U) /*!< bit 5 */
-#define ADC_JDR4_JDATA_6        ((uint32_t)0x00000040U) /*!< bit 6 */
-#define ADC_JDR4_JDATA_7        ((uint32_t)0x00000080U) /*!< bit 7 */
-#define ADC_JDR4_JDATA_8        ((uint32_t)0x00000100U) /*!< bit 8 */
-#define ADC_JDR4_JDATA_9        ((uint32_t)0x00000200U) /*!< bit 9 */
-#define ADC_JDR4_JDATA_10       ((uint32_t)0x00000400U) /*!< bit 10 */
-#define ADC_JDR4_JDATA_11       ((uint32_t)0x00000800U) /*!< bit 11 */
-#define ADC_JDR4_JDATA_12       ((uint32_t)0x00001000U) /*!< bit 12 */
-#define ADC_JDR4_JDATA_13       ((uint32_t)0x00002000U) /*!< bit 13 */
-#define ADC_JDR4_JDATA_14       ((uint32_t)0x00004000U) /*!< bit 14 */
-#define ADC_JDR4_JDATA_15       ((uint32_t)0x00008000U) /*!< bit 15 */
-
-/********************  Bit definition for ADC_AWD2CR register  ****************/
-#define ADC_AWD2CR_AWD2CH       ((uint32_t)0x0007FFFFU) /*!< ADC analog watchdog 2 monitored channel selection */
-#define ADC_AWD2CR_AWD2CH_0     ((uint32_t)0x00000001U) /*!< ADC analog watchdog 2 monitoring channel 0 */
-#define ADC_AWD2CR_AWD2CH_1     ((uint32_t)0x00000002U) /*!< ADC analog watchdog 2 monitoring channel 1 */
-#define ADC_AWD2CR_AWD2CH_2     ((uint32_t)0x00000004U) /*!< ADC analog watchdog 2 monitoring channel 2 */
-#define ADC_AWD2CR_AWD2CH_3     ((uint32_t)0x00000008U) /*!< ADC analog watchdog 2 monitoring channel 3 */
-#define ADC_AWD2CR_AWD2CH_4     ((uint32_t)0x00000010U) /*!< ADC analog watchdog 2 monitoring channel 4 */
-#define ADC_AWD2CR_AWD2CH_5     ((uint32_t)0x00000020U) /*!< ADC analog watchdog 2 monitoring channel 5 */
-#define ADC_AWD2CR_AWD2CH_6     ((uint32_t)0x00000040U) /*!< ADC analog watchdog 2 monitoring channel 6 */
-#define ADC_AWD2CR_AWD2CH_7     ((uint32_t)0x00000080U) /*!< ADC analog watchdog 2 monitoring channel 7 */
-#define ADC_AWD2CR_AWD2CH_8     ((uint32_t)0x00000100U) /*!< ADC analog watchdog 2 monitoring channel 8 */
-#define ADC_AWD2CR_AWD2CH_9     ((uint32_t)0x00000200U) /*!< ADC analog watchdog 2 monitoring channel 9 */
-#define ADC_AWD2CR_AWD2CH_10    ((uint32_t)0x00000400U) /*!< ADC analog watchdog 2 monitoring channel 10 */
-#define ADC_AWD2CR_AWD2CH_11    ((uint32_t)0x00000800U) /*!< ADC analog watchdog 2 monitoring channel 11 */
-#define ADC_AWD2CR_AWD2CH_12    ((uint32_t)0x00001000U) /*!< ADC analog watchdog 2 monitoring channel 12 */
-#define ADC_AWD2CR_AWD2CH_13    ((uint32_t)0x00002000U) /*!< ADC analog watchdog 2 monitoring channel 13 */
-#define ADC_AWD2CR_AWD2CH_14    ((uint32_t)0x00004000U) /*!< ADC analog watchdog 2 monitoring channel 14 */
-#define ADC_AWD2CR_AWD2CH_15    ((uint32_t)0x00008000U) /*!< ADC analog watchdog 2 monitoring channel 15 */
-#define ADC_AWD2CR_AWD2CH_16    ((uint32_t)0x00010000U) /*!< ADC analog watchdog 2 monitoring channel 16 */
-#define ADC_AWD2CR_AWD2CH_17    ((uint32_t)0x00020000U) /*!< ADC analog watchdog 2 monitoring channel 17 */
-#define ADC_AWD2CR_AWD2CH_18    ((uint32_t)0x00040000U) /*!< ADC analog watchdog 2 monitoring channel 18 */
-
-/********************  Bit definition for ADC_AWD3CR register  ****************/
-#define ADC_AWD3CR_AWD3CH       ((uint32_t)0x0007FFFFU) /*!< ADC analog watchdog 3 monitored channel selection */
-#define ADC_AWD3CR_AWD3CH_0     ((uint32_t)0x00000001U) /*!< ADC analog watchdog 3 monitoring channel 0 */
-#define ADC_AWD3CR_AWD3CH_1     ((uint32_t)0x00000002U) /*!< ADC analog watchdog 3 monitoring channel 1 */
-#define ADC_AWD3CR_AWD3CH_2     ((uint32_t)0x00000004U) /*!< ADC analog watchdog 3 monitoring channel 2 */
-#define ADC_AWD3CR_AWD3CH_3     ((uint32_t)0x00000008U) /*!< ADC analog watchdog 3 monitoring channel 3 */
-#define ADC_AWD3CR_AWD3CH_4     ((uint32_t)0x00000010U) /*!< ADC analog watchdog 3 monitoring channel 4 */
-#define ADC_AWD3CR_AWD3CH_5     ((uint32_t)0x00000020U) /*!< ADC analog watchdog 3 monitoring channel 5 */
-#define ADC_AWD3CR_AWD3CH_6     ((uint32_t)0x00000040U) /*!< ADC analog watchdog 3 monitoring channel 6 */
-#define ADC_AWD3CR_AWD3CH_7     ((uint32_t)0x00000080U) /*!< ADC analog watchdog 3 monitoring channel 7 */
-#define ADC_AWD3CR_AWD3CH_8     ((uint32_t)0x00000100U) /*!< ADC analog watchdog 3 monitoring channel 8 */
-#define ADC_AWD3CR_AWD3CH_9     ((uint32_t)0x00000200U) /*!< ADC analog watchdog 3 monitoring channel 9 */
-#define ADC_AWD3CR_AWD3CH_10    ((uint32_t)0x00000400U) /*!< ADC analog watchdog 3 monitoring channel 10 */
-#define ADC_AWD3CR_AWD3CH_11    ((uint32_t)0x00000800U) /*!< ADC analog watchdog 3 monitoring channel 11 */
-#define ADC_AWD3CR_AWD3CH_12    ((uint32_t)0x00001000U) /*!< ADC analog watchdog 3 monitoring channel 12 */
-#define ADC_AWD3CR_AWD3CH_13    ((uint32_t)0x00002000U) /*!< ADC analog watchdog 3 monitoring channel 13 */
-#define ADC_AWD3CR_AWD3CH_14    ((uint32_t)0x00004000U) /*!< ADC analog watchdog 3 monitoring channel 14 */
-#define ADC_AWD3CR_AWD3CH_15    ((uint32_t)0x00008000U) /*!< ADC analog watchdog 3 monitoring channel 15 */
-#define ADC_AWD3CR_AWD3CH_16    ((uint32_t)0x00010000U) /*!< ADC analog watchdog 3 monitoring channel 16 */
-#define ADC_AWD3CR_AWD3CH_17    ((uint32_t)0x00020000U) /*!< ADC analog watchdog 3 monitoring channel 17 */
-#define ADC_AWD3CR_AWD3CH_18    ((uint32_t)0x00040000U) /*!< ADC analog watchdog 3 monitoring channel 18 */
-
-/********************  Bit definition for ADC_DIFSEL register  ****************/
-#define ADC_DIFSEL_DIFSEL       ((uint32_t)0x0007FFFFU) /*!< ADC channel differential or single-ended mode */
-#define ADC_DIFSEL_DIFSEL_0     ((uint32_t)0x00000001U) /*!< bit 0 */
-#define ADC_DIFSEL_DIFSEL_1     ((uint32_t)0x00000002U) /*!< bit 1 */
-#define ADC_DIFSEL_DIFSEL_2     ((uint32_t)0x00000004U) /*!< bit 2 */
-#define ADC_DIFSEL_DIFSEL_3     ((uint32_t)0x00000008U) /*!< bit 3 */
-#define ADC_DIFSEL_DIFSEL_4     ((uint32_t)0x00000010U) /*!< bit 4 */
-#define ADC_DIFSEL_DIFSEL_5     ((uint32_t)0x00000020U) /*!< bit 5 */
-#define ADC_DIFSEL_DIFSEL_6     ((uint32_t)0x00000040U) /*!< bit 6 */
-#define ADC_DIFSEL_DIFSEL_7     ((uint32_t)0x00000080U) /*!< bit 7 */
-#define ADC_DIFSEL_DIFSEL_8     ((uint32_t)0x00000100U) /*!< bit 8 */
-#define ADC_DIFSEL_DIFSEL_9     ((uint32_t)0x00000200U) /*!< bit 9 */
-#define ADC_DIFSEL_DIFSEL_10    ((uint32_t)0x00000400U) /*!< bit 10 */
-#define ADC_DIFSEL_DIFSEL_11    ((uint32_t)0x00000800U) /*!< bit 11 */
-#define ADC_DIFSEL_DIFSEL_12    ((uint32_t)0x00001000U) /*!< bit 12 */
-#define ADC_DIFSEL_DIFSEL_13    ((uint32_t)0x00002000U) /*!< bit 13 */
-#define ADC_DIFSEL_DIFSEL_14    ((uint32_t)0x00004000U) /*!< bit 14 */
-#define ADC_DIFSEL_DIFSEL_15    ((uint32_t)0x00008000U) /*!< bit 15 */
-#define ADC_DIFSEL_DIFSEL_16    ((uint32_t)0x00010000U) /*!< bit 16 */
-#define ADC_DIFSEL_DIFSEL_17    ((uint32_t)0x00020000U) /*!< bit 17 */
-#define ADC_DIFSEL_DIFSEL_18    ((uint32_t)0x00040000U) /*!< bit 18 */
-
-/********************  Bit definition for ADC_CALFACT register  ***************/
-#define ADC_CALFACT_CALFACT_S   ((uint32_t)0x0000007FU) /*!< ADC calibration factor in single-ended mode */
-#define ADC_CALFACT_CALFACT_S_0 ((uint32_t)0x00000001U) /*!< bit 0 */
-#define ADC_CALFACT_CALFACT_S_1 ((uint32_t)0x00000002U) /*!< bit 1 */
-#define ADC_CALFACT_CALFACT_S_2 ((uint32_t)0x00000004U) /*!< bit 2 */
-#define ADC_CALFACT_CALFACT_S_3 ((uint32_t)0x00000008U) /*!< bit 3 */
-#define ADC_CALFACT_CALFACT_S_4 ((uint32_t)0x00000010U) /*!< bit 4 */
-#define ADC_CALFACT_CALFACT_S_5 ((uint32_t)0x00000020U) /*!< bit 5 */
-#define ADC_CALFACT_CALFACT_S_6 ((uint32_t)0x00000040U) /*!< bit 6 */
-
-#define ADC_CALFACT_CALFACT_D   ((uint32_t)0x007F0000U) /*!< ADC calibration factor in differential mode */
-#define ADC_CALFACT_CALFACT_D_0 ((uint32_t)0x00010000U) /*!< bit 0 */
-#define ADC_CALFACT_CALFACT_D_1 ((uint32_t)0x00020000U) /*!< bit 1 */
-#define ADC_CALFACT_CALFACT_D_2 ((uint32_t)0x00040000U) /*!< bit 2 */
-#define ADC_CALFACT_CALFACT_D_3 ((uint32_t)0x00080000U) /*!< bit 3 */
-#define ADC_CALFACT_CALFACT_D_4 ((uint32_t)0x00100000U) /*!< bit 4 */
-#define ADC_CALFACT_CALFACT_D_5 ((uint32_t)0x00200000U) /*!< bit 5 */
-#define ADC_CALFACT_CALFACT_D_6 ((uint32_t)0x00400000U) /*!< bit 6 */
-
-/*************************  ADC Common registers  *****************************/
-/********************  Bit definition for ADC_CSR register  *******************/
-#define ADC_CSR_ADRDY_MST       ((uint32_t)0x00000001U) /*!< ADC multimode master ready flag */
-#define ADC_CSR_EOSMP_MST       ((uint32_t)0x00000002U) /*!< ADC multimode master group regular end of sampling flag */
-#define ADC_CSR_EOC_MST         ((uint32_t)0x00000004U) /*!< ADC multimode master group regular end of unitary conversion flag */
-#define ADC_CSR_EOS_MST         ((uint32_t)0x00000008U) /*!< ADC multimode master group regular end of sequence conversions flag */
-#define ADC_CSR_OVR_MST         ((uint32_t)0x00000010U) /*!< ADC multimode master group regular overrun flag */
-#define ADC_CSR_JEOC_MST        ((uint32_t)0x00000020U) /*!< ADC multimode master group injected end of unitary conversion flag */
-#define ADC_CSR_JEOS_MST        ((uint32_t)0x00000040U) /*!< ADC multimode master group injected end of sequence conversions flag */
-#define ADC_CSR_AWD1_MST        ((uint32_t)0x00000080U) /*!< ADC multimode master analog watchdog 1 flag */
-#define ADC_CSR_AWD2_MST        ((uint32_t)0x00000100U) /*!< ADC multimode master analog watchdog 2 flag */
-#define ADC_CSR_AWD3_MST        ((uint32_t)0x00000200U) /*!< ADC multimode master analog watchdog 3 flag */
-#define ADC_CSR_JQOVF_MST       ((uint32_t)0x00000400U) /*!< ADC multimode master group injected contexts queue overflow flag */
-
-#define ADC_CSR_ADRDY_SLV       ((uint32_t)0x00010000U) /*!< ADC multimode slave ready flag */
-#define ADC_CSR_EOSMP_SLV       ((uint32_t)0x00020000U) /*!< ADC multimode slave group regular end of sampling flag */
-#define ADC_CSR_EOC_SLV         ((uint32_t)0x00040000U) /*!< ADC multimode slave group regular end of unitary conversion flag */
-#define ADC_CSR_EOS_SLV         ((uint32_t)0x00080000U) /*!< ADC multimode slave group regular end of sequence conversions flag */
-#define ADC_CSR_OVR_SLV         ((uint32_t)0x00100000U) /*!< ADC multimode slave group regular overrun flag */
-#define ADC_CSR_JEOC_SLV        ((uint32_t)0x00200000U) /*!< ADC multimode slave group injected end of unitary conversion flag */
-#define ADC_CSR_JEOS_SLV        ((uint32_t)0x00400000U) /*!< ADC multimode slave group injected end of sequence conversions flag */
-#define ADC_CSR_AWD1_SLV        ((uint32_t)0x00800000U) /*!< ADC multimode slave analog watchdog 1 flag */
-#define ADC_CSR_AWD2_SLV        ((uint32_t)0x01000000U) /*!< ADC multimode slave analog watchdog 2 flag */
-#define ADC_CSR_AWD3_SLV        ((uint32_t)0x02000000U) /*!< ADC multimode slave analog watchdog 3 flag */
-#define ADC_CSR_JQOVF_SLV       ((uint32_t)0x04000000U) /*!< ADC multimode slave group injected contexts queue overflow flag */
-
-/********************  Bit definition for ADC_CCR register  *******************/
-#define ADC_CCR_DUAL            ((uint32_t)0x0000001FU) /*!< ADC multimode mode selection */
-#define ADC_CCR_DUAL_0          ((uint32_t)0x00000001U) /*!< bit 0 */
-#define ADC_CCR_DUAL_1          ((uint32_t)0x00000002U) /*!< bit 1 */
-#define ADC_CCR_DUAL_2          ((uint32_t)0x00000004U) /*!< bit 2 */
-#define ADC_CCR_DUAL_3          ((uint32_t)0x00000008U) /*!< bit 3 */
-#define ADC_CCR_DUAL_4          ((uint32_t)0x00000010U) /*!< bit 4 */
-
-#define ADC_CCR_DELAY           ((uint32_t)0x00000F00U) /*!< ADC multimode delay between 2 sampling phases */
-#define ADC_CCR_DELAY_0         ((uint32_t)0x00000100U) /*!< bit 0 */
-#define ADC_CCR_DELAY_1         ((uint32_t)0x00000200U) /*!< bit 1 */
-#define ADC_CCR_DELAY_2         ((uint32_t)0x00000400U) /*!< bit 2 */
-#define ADC_CCR_DELAY_3         ((uint32_t)0x00000800U) /*!< bit 3 */
-
-#define ADC_CCR_DMACFG          ((uint32_t)0x00002000U) /*!< ADC multimode DMA transfer configuration */
-
-#define ADC_CCR_MDMA            ((uint32_t)0x0000C000U) /*!< ADC multimode DMA transfer enable */
-#define ADC_CCR_MDMA_0          ((uint32_t)0x00004000U) /*!< bit 0 */
-#define ADC_CCR_MDMA_1          ((uint32_t)0x00008000U) /*!< bit 1 */
-
-#define ADC_CCR_CKMODE          ((uint32_t)0x00030000U) /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
-#define ADC_CCR_CKMODE_0        ((uint32_t)0x00010000U) /*!< bit 0 */
-#define ADC_CCR_CKMODE_1        ((uint32_t)0x00020000U) /*!< bit 1 */
-
-#define ADC_CCR_PRESC           ((uint32_t)0x003C0000U) /*!< ADC common clock prescaler, only for clock source asynchronous */
-#define ADC_CCR_PRESC_0         ((uint32_t)0x00040000U) /*!< bit 0 */
-#define ADC_CCR_PRESC_1         ((uint32_t)0x00080000U) /*!< bit 1 */
-#define ADC_CCR_PRESC_2         ((uint32_t)0x00100000U) /*!< bit 2 */
-#define ADC_CCR_PRESC_3         ((uint32_t)0x00200000U) /*!< bit 3 */
-
-#define ADC_CCR_VREFEN          ((uint32_t)0x00400000U) /*!< ADC internal path to VrefInt enable */
-#define ADC_CCR_TSEN            ((uint32_t)0x00800000U) /*!< ADC internal path to temperature sensor enable */
-#define ADC_CCR_VBATEN          ((uint32_t)0x01000000U) /*!< ADC internal path to battery voltage enable */
-
-/********************  Bit definition for ADC_CDR register  *******************/
-#define ADC_CDR_RDATA_MST       ((uint32_t)0x0000FFFFU) /*!< ADC multimode master group regular conversion data */
-#define ADC_CDR_RDATA_MST_0     ((uint32_t)0x00000001U) /*!< bit 0 */
-#define ADC_CDR_RDATA_MST_1     ((uint32_t)0x00000002U) /*!< bit 1 */
-#define ADC_CDR_RDATA_MST_2     ((uint32_t)0x00000004U) /*!< bit 2 */
-#define ADC_CDR_RDATA_MST_3     ((uint32_t)0x00000008U) /*!< bit 3 */
-#define ADC_CDR_RDATA_MST_4     ((uint32_t)0x00000010U) /*!< bit 4 */
-#define ADC_CDR_RDATA_MST_5     ((uint32_t)0x00000020U) /*!< bit 5 */
-#define ADC_CDR_RDATA_MST_6     ((uint32_t)0x00000040U) /*!< bit 6 */
-#define ADC_CDR_RDATA_MST_7     ((uint32_t)0x00000080U) /*!< bit 7 */
-#define ADC_CDR_RDATA_MST_8     ((uint32_t)0x00000100U) /*!< bit 8 */
-#define ADC_CDR_RDATA_MST_9     ((uint32_t)0x00000200U) /*!< bit 9 */
-#define ADC_CDR_RDATA_MST_10    ((uint32_t)0x00000400U) /*!< bit 10 */
-#define ADC_CDR_RDATA_MST_11    ((uint32_t)0x00000800U) /*!< bit 11 */
-#define ADC_CDR_RDATA_MST_12    ((uint32_t)0x00001000U) /*!< bit 12 */
-#define ADC_CDR_RDATA_MST_13    ((uint32_t)0x00002000U) /*!< bit 13 */
-#define ADC_CDR_RDATA_MST_14    ((uint32_t)0x00004000U) /*!< bit 14 */
-#define ADC_CDR_RDATA_MST_15    ((uint32_t)0x00008000U) /*!< bit 15 */
-
-#define ADC_CDR_RDATA_SLV       ((uint32_t)0xFFFF0000U) /*!< ADC multimode slave group regular conversion data */
-#define ADC_CDR_RDATA_SLV_0     ((uint32_t)0x00010000U) /*!< bit 0 */
-#define ADC_CDR_RDATA_SLV_1     ((uint32_t)0x00020000U) /*!< bit 1 */
-#define ADC_CDR_RDATA_SLV_2     ((uint32_t)0x00040000U) /*!< bit 2 */
-#define ADC_CDR_RDATA_SLV_3     ((uint32_t)0x00080000U) /*!< bit 3 */
-#define ADC_CDR_RDATA_SLV_4     ((uint32_t)0x00100000U) /*!< bit 4 */
-#define ADC_CDR_RDATA_SLV_5     ((uint32_t)0x00200000U) /*!< bit 5 */
-#define ADC_CDR_RDATA_SLV_6     ((uint32_t)0x00400000U) /*!< bit 6 */
-#define ADC_CDR_RDATA_SLV_7     ((uint32_t)0x00800000U) /*!< bit 7 */
-#define ADC_CDR_RDATA_SLV_8     ((uint32_t)0x01000000U) /*!< bit 8 */
-#define ADC_CDR_RDATA_SLV_9     ((uint32_t)0x02000000U) /*!< bit 9 */
-#define ADC_CDR_RDATA_SLV_10    ((uint32_t)0x04000000U) /*!< bit 10 */
-#define ADC_CDR_RDATA_SLV_11    ((uint32_t)0x08000000U) /*!< bit 11 */
-#define ADC_CDR_RDATA_SLV_12    ((uint32_t)0x10000000U) /*!< bit 12 */
-#define ADC_CDR_RDATA_SLV_13    ((uint32_t)0x20000000U) /*!< bit 13 */
-#define ADC_CDR_RDATA_SLV_14    ((uint32_t)0x40000000U) /*!< bit 14 */
-#define ADC_CDR_RDATA_SLV_15    ((uint32_t)0x80000000U) /*!< bit 15 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Controller Area Network                            */
-/*                                                                            */
-/******************************************************************************/
-/*!<CAN control and status registers */
-/*******************  Bit definition for CAN_MCR register  ********************/
-#define  CAN_MCR_INRQ                        ((uint16_t)0x0001U)            /*!<Initialization Request */
-#define  CAN_MCR_SLEEP                       ((uint16_t)0x0002U)            /*!<Sleep Mode Request */
-#define  CAN_MCR_TXFP                        ((uint16_t)0x0004U)            /*!<Transmit FIFO Priority */
-#define  CAN_MCR_RFLM                        ((uint16_t)0x0008U)            /*!<Receive FIFO Locked Mode */
-#define  CAN_MCR_NART                        ((uint16_t)0x0010U)            /*!<No Automatic Retransmission */
-#define  CAN_MCR_AWUM                        ((uint16_t)0x0020U)            /*!<Automatic Wakeup Mode */
-#define  CAN_MCR_ABOM                        ((uint16_t)0x0040U)            /*!<Automatic Bus-Off Management */
-#define  CAN_MCR_TTCM                        ((uint16_t)0x0080U)            /*!<Time Triggered Communication Mode */
-#define  CAN_MCR_RESET                       ((uint16_t)0x8000U)            /*!<bxCAN software master reset */
-
-/*******************  Bit definition for CAN_MSR register  ********************/
-#define  CAN_MSR_INAK                        ((uint16_t)0x0001U)            /*!<Initialization Acknowledge */
-#define  CAN_MSR_SLAK                        ((uint16_t)0x0002U)            /*!<Sleep Acknowledge */
-#define  CAN_MSR_ERRI                        ((uint16_t)0x0004U)            /*!<Error Interrupt */
-#define  CAN_MSR_WKUI                        ((uint16_t)0x0008U)            /*!<Wakeup Interrupt */
-#define  CAN_MSR_SLAKI                       ((uint16_t)0x0010U)            /*!<Sleep Acknowledge Interrupt */
-#define  CAN_MSR_TXM                         ((uint16_t)0x0100U)            /*!<Transmit Mode */
-#define  CAN_MSR_RXM                         ((uint16_t)0x0200U)            /*!<Receive Mode */
-#define  CAN_MSR_SAMP                        ((uint16_t)0x0400U)            /*!<Last Sample Point */
-#define  CAN_MSR_RX                          ((uint16_t)0x0800U)            /*!<CAN Rx Signal */
-
-/*******************  Bit definition for CAN_TSR register  ********************/
-#define  CAN_TSR_RQCP0                       ((uint32_t)0x00000001U)        /*!<Request Completed Mailbox0 */
-#define  CAN_TSR_TXOK0                       ((uint32_t)0x00000002U)        /*!<Transmission OK of Mailbox0 */
-#define  CAN_TSR_ALST0                       ((uint32_t)0x00000004U)        /*!<Arbitration Lost for Mailbox0 */
-#define  CAN_TSR_TERR0                       ((uint32_t)0x00000008U)        /*!<Transmission Error of Mailbox0 */
-#define  CAN_TSR_ABRQ0                       ((uint32_t)0x00000080U)        /*!<Abort Request for Mailbox0 */
-#define  CAN_TSR_RQCP1                       ((uint32_t)0x00000100U)        /*!<Request Completed Mailbox1 */
-#define  CAN_TSR_TXOK1                       ((uint32_t)0x00000200U)        /*!<Transmission OK of Mailbox1 */
-#define  CAN_TSR_ALST1                       ((uint32_t)0x00000400U)        /*!<Arbitration Lost for Mailbox1 */
-#define  CAN_TSR_TERR1                       ((uint32_t)0x00000800U)        /*!<Transmission Error of Mailbox1 */
-#define  CAN_TSR_ABRQ1                       ((uint32_t)0x00008000U)        /*!<Abort Request for Mailbox 1 */
-#define  CAN_TSR_RQCP2                       ((uint32_t)0x00010000U)        /*!<Request Completed Mailbox2 */
-#define  CAN_TSR_TXOK2                       ((uint32_t)0x00020000U)        /*!<Transmission OK of Mailbox 2 */
-#define  CAN_TSR_ALST2                       ((uint32_t)0x00040000U)        /*!<Arbitration Lost for mailbox 2 */
-#define  CAN_TSR_TERR2                       ((uint32_t)0x00080000U)        /*!<Transmission Error of Mailbox 2 */
-#define  CAN_TSR_ABRQ2                       ((uint32_t)0x00800000U)        /*!<Abort Request for Mailbox 2 */
-#define  CAN_TSR_CODE                        ((uint32_t)0x03000000U)        /*!<Mailbox Code */
-
-#define  CAN_TSR_TME                         ((uint32_t)0x1C000000U)        /*!<TME[2:0] bits */
-#define  CAN_TSR_TME0                        ((uint32_t)0x04000000U)        /*!<Transmit Mailbox 0 Empty */
-#define  CAN_TSR_TME1                        ((uint32_t)0x08000000U)        /*!<Transmit Mailbox 1 Empty */
-#define  CAN_TSR_TME2                        ((uint32_t)0x10000000U)        /*!<Transmit Mailbox 2 Empty */
-
-#define  CAN_TSR_LOW                         ((uint32_t)0xE0000000U)        /*!<LOW[2:0] bits */
-#define  CAN_TSR_LOW0                        ((uint32_t)0x20000000U)        /*!<Lowest Priority Flag for Mailbox 0 */
-#define  CAN_TSR_LOW1                        ((uint32_t)0x40000000U)        /*!<Lowest Priority Flag for Mailbox 1 */
-#define  CAN_TSR_LOW2                        ((uint32_t)0x80000000U)        /*!<Lowest Priority Flag for Mailbox 2 */
-
-/*******************  Bit definition for CAN_RF0R register  *******************/
-#define  CAN_RF0R_FMP0                       ((uint8_t)0x03U)               /*!<FIFO 0 Message Pending */
-#define  CAN_RF0R_FULL0                      ((uint8_t)0x08U)               /*!<FIFO 0 Full */
-#define  CAN_RF0R_FOVR0                      ((uint8_t)0x10U)               /*!<FIFO 0 Overrun */
-#define  CAN_RF0R_RFOM0                      ((uint8_t)0x20U)               /*!<Release FIFO 0 Output Mailbox */
-
-/*******************  Bit definition for CAN_RF1R register  *******************/
-#define  CAN_RF1R_FMP1                       ((uint8_t)0x03U)               /*!<FIFO 1 Message Pending */
-#define  CAN_RF1R_FULL1                      ((uint8_t)0x08U)               /*!<FIFO 1 Full */
-#define  CAN_RF1R_FOVR1                      ((uint8_t)0x10U)               /*!<FIFO 1 Overrun */
-#define  CAN_RF1R_RFOM1                      ((uint8_t)0x20U)               /*!<Release FIFO 1 Output Mailbox */
-
-/********************  Bit definition for CAN_IER register  *******************/
-#define  CAN_IER_TMEIE                       ((uint32_t)0x00000001U)        /*!<Transmit Mailbox Empty Interrupt Enable */
-#define  CAN_IER_FMPIE0                      ((uint32_t)0x00000002U)        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE0                       ((uint32_t)0x00000004U)        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE0                      ((uint32_t)0x00000008U)        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_FMPIE1                      ((uint32_t)0x00000010U)        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE1                       ((uint32_t)0x00000020U)        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE1                      ((uint32_t)0x00000040U)        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_EWGIE                       ((uint32_t)0x00000100U)        /*!<Error Warning Interrupt Enable */
-#define  CAN_IER_EPVIE                       ((uint32_t)0x00000200U)        /*!<Error Passive Interrupt Enable */
-#define  CAN_IER_BOFIE                       ((uint32_t)0x00000400U)        /*!<Bus-Off Interrupt Enable */
-#define  CAN_IER_LECIE                       ((uint32_t)0x00000800U)        /*!<Last Error Code Interrupt Enable */
-#define  CAN_IER_ERRIE                       ((uint32_t)0x00008000U)        /*!<Error Interrupt Enable */
-#define  CAN_IER_WKUIE                       ((uint32_t)0x00010000U)        /*!<Wakeup Interrupt Enable */
-#define  CAN_IER_SLKIE                       ((uint32_t)0x00020000U)        /*!<Sleep Interrupt Enable */
-
-/********************  Bit definition for CAN_ESR register  *******************/
-#define  CAN_ESR_EWGF                        ((uint32_t)0x00000001U)        /*!<Error Warning Flag */
-#define  CAN_ESR_EPVF                        ((uint32_t)0x00000002U)        /*!<Error Passive Flag */
-#define  CAN_ESR_BOFF                        ((uint32_t)0x00000004U)        /*!<Bus-Off Flag */
-
-#define  CAN_ESR_LEC                         ((uint32_t)0x00000070U)        /*!<LEC[2:0] bits (Last Error Code) */
-#define  CAN_ESR_LEC_0                       ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  CAN_ESR_LEC_1                       ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  CAN_ESR_LEC_2                       ((uint32_t)0x00000040U)        /*!<Bit 2 */
-
-#define  CAN_ESR_TEC                         ((uint32_t)0x00FF0000U)        /*!<Least significant byte of the 9-bit Transmit Error Counter */
-#define  CAN_ESR_REC                         ((uint32_t)0xFF000000U)        /*!<Receive Error Counter */
-
-/*******************  Bit definition for CAN_BTR register  ********************/
-#define  CAN_BTR_BRP                         ((uint32_t)0x000003FFU)        /*!<Baud Rate Prescaler */
-#define  CAN_BTR_TS1_0                       ((uint32_t)0x00010000U)        /*!<Time Segment 1 (Bit 0) */
-#define  CAN_BTR_TS1_1                       ((uint32_t)0x00020000U)        /*!<Time Segment 1 (Bit 1) */
-#define  CAN_BTR_TS1_2                       ((uint32_t)0x00040000U)        /*!<Time Segment 1 (Bit 2) */
-#define  CAN_BTR_TS1_3                       ((uint32_t)0x00080000U)        /*!<Time Segment 1 (Bit 3) */
-#define  CAN_BTR_TS1                         ((uint32_t)0x000F0000U)        /*!<Time Segment 1 */
-#define  CAN_BTR_TS2_0                       ((uint32_t)0x00100000U)        /*!<Time Segment 2 (Bit 0) */
-#define  CAN_BTR_TS2_1                       ((uint32_t)0x00200000U)        /*!<Time Segment 2 (Bit 1) */
-#define  CAN_BTR_TS2_2                       ((uint32_t)0x00400000U)        /*!<Time Segment 2 (Bit 2) */
-#define  CAN_BTR_TS2                         ((uint32_t)0x00700000U)        /*!<Time Segment 2 */
-#define  CAN_BTR_SJW_0                       ((uint32_t)0x01000000U)        /*!<Resynchronization Jump Width (Bit 0) */
-#define  CAN_BTR_SJW_1                       ((uint32_t)0x02000000U)        /*!<Resynchronization Jump Width (Bit 1) */
-#define  CAN_BTR_SJW                         ((uint32_t)0x03000000U)        /*!<Resynchronization Jump Width */
-#define  CAN_BTR_LBKM                        ((uint32_t)0x40000000U)        /*!<Loop Back Mode (Debug) */
-#define  CAN_BTR_SILM                        ((uint32_t)0x80000000U)        /*!<Silent Mode */
-
-/*!<Mailbox registers */
-/******************  Bit definition for CAN_TI0R register  ********************/
-#define  CAN_TI0R_TXRQ                       ((uint32_t)0x00000001U)        /*!<Transmit Mailbox Request */
-#define  CAN_TI0R_RTR                        ((uint32_t)0x00000002U)        /*!<Remote Transmission Request */
-#define  CAN_TI0R_IDE                        ((uint32_t)0x00000004U)        /*!<Identifier Extension */
-#define  CAN_TI0R_EXID                       ((uint32_t)0x001FFFF8U)        /*!<Extended Identifier */
-#define  CAN_TI0R_STID                       ((uint32_t)0xFFE00000U)        /*!<Standard Identifier or Extended Identifier */
-
-/******************  Bit definition for CAN_TDT0R register  *******************/
-#define  CAN_TDT0R_DLC                       ((uint32_t)0x0000000FU)        /*!<Data Length Code */
-#define  CAN_TDT0R_TGT                       ((uint32_t)0x00000100U)        /*!<Transmit Global Time */
-#define  CAN_TDT0R_TIME                      ((uint32_t)0xFFFF0000U)        /*!<Message Time Stamp */
-
-/******************  Bit definition for CAN_TDL0R register  *******************/
-#define  CAN_TDL0R_DATA0                     ((uint32_t)0x000000FFU)        /*!<Data byte 0 */
-#define  CAN_TDL0R_DATA1                     ((uint32_t)0x0000FF00U)        /*!<Data byte 1 */
-#define  CAN_TDL0R_DATA2                     ((uint32_t)0x00FF0000U)        /*!<Data byte 2 */
-#define  CAN_TDL0R_DATA3                     ((uint32_t)0xFF000000U)        /*!<Data byte 3 */
-
-/******************  Bit definition for CAN_TDH0R register  *******************/
-#define  CAN_TDH0R_DATA4                     ((uint32_t)0x000000FFU)        /*!<Data byte 4 */
-#define  CAN_TDH0R_DATA5                     ((uint32_t)0x0000FF00U)        /*!<Data byte 5 */
-#define  CAN_TDH0R_DATA6                     ((uint32_t)0x00FF0000U)        /*!<Data byte 6 */
-#define  CAN_TDH0R_DATA7                     ((uint32_t)0xFF000000U)        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI1R register  *******************/
-#define  CAN_TI1R_TXRQ                       ((uint32_t)0x00000001U)        /*!<Transmit Mailbox Request */
-#define  CAN_TI1R_RTR                        ((uint32_t)0x00000002U)        /*!<Remote Transmission Request */
-#define  CAN_TI1R_IDE                        ((uint32_t)0x00000004U)        /*!<Identifier Extension */
-#define  CAN_TI1R_EXID                       ((uint32_t)0x001FFFF8U)        /*!<Extended Identifier */
-#define  CAN_TI1R_STID                       ((uint32_t)0xFFE00000U)        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT1R register  ******************/
-#define  CAN_TDT1R_DLC                       ((uint32_t)0x0000000FU)        /*!<Data Length Code */
-#define  CAN_TDT1R_TGT                       ((uint32_t)0x00000100U)        /*!<Transmit Global Time */
-#define  CAN_TDT1R_TIME                      ((uint32_t)0xFFFF0000U)        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL1R register  ******************/
-#define  CAN_TDL1R_DATA0                     ((uint32_t)0x000000FFU)        /*!<Data byte 0 */
-#define  CAN_TDL1R_DATA1                     ((uint32_t)0x0000FF00U)        /*!<Data byte 1 */
-#define  CAN_TDL1R_DATA2                     ((uint32_t)0x00FF0000U)        /*!<Data byte 2 */
-#define  CAN_TDL1R_DATA3                     ((uint32_t)0xFF000000U)        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH1R register  ******************/
-#define  CAN_TDH1R_DATA4                     ((uint32_t)0x000000FFU)        /*!<Data byte 4 */
-#define  CAN_TDH1R_DATA5                     ((uint32_t)0x0000FF00U)        /*!<Data byte 5 */
-#define  CAN_TDH1R_DATA6                     ((uint32_t)0x00FF0000U)        /*!<Data byte 6 */
-#define  CAN_TDH1R_DATA7                     ((uint32_t)0xFF000000U)        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI2R register  *******************/
-#define  CAN_TI2R_TXRQ                       ((uint32_t)0x00000001U)        /*!<Transmit Mailbox Request */
-#define  CAN_TI2R_RTR                        ((uint32_t)0x00000002U)        /*!<Remote Transmission Request */
-#define  CAN_TI2R_IDE                        ((uint32_t)0x00000004U)        /*!<Identifier Extension */
-#define  CAN_TI2R_EXID                       ((uint32_t)0x001FFFF8U)        /*!<Extended identifier */
-#define  CAN_TI2R_STID                       ((uint32_t)0xFFE00000U)        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT2R register  ******************/
-#define  CAN_TDT2R_DLC                       ((uint32_t)0x0000000FU)        /*!<Data Length Code */
-#define  CAN_TDT2R_TGT                       ((uint32_t)0x00000100U)        /*!<Transmit Global Time */
-#define  CAN_TDT2R_TIME                      ((uint32_t)0xFFFF0000U)        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL2R register  ******************/
-#define  CAN_TDL2R_DATA0                     ((uint32_t)0x000000FFU)        /*!<Data byte 0 */
-#define  CAN_TDL2R_DATA1                     ((uint32_t)0x0000FF00U)        /*!<Data byte 1 */
-#define  CAN_TDL2R_DATA2                     ((uint32_t)0x00FF0000U)        /*!<Data byte 2 */
-#define  CAN_TDL2R_DATA3                     ((uint32_t)0xFF000000U)        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH2R register  ******************/
-#define  CAN_TDH2R_DATA4                     ((uint32_t)0x000000FFU)        /*!<Data byte 4 */
-#define  CAN_TDH2R_DATA5                     ((uint32_t)0x0000FF00U)        /*!<Data byte 5 */
-#define  CAN_TDH2R_DATA6                     ((uint32_t)0x00FF0000U)        /*!<Data byte 6 */
-#define  CAN_TDH2R_DATA7                     ((uint32_t)0xFF000000U)        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI0R register  *******************/
-#define  CAN_RI0R_RTR                        ((uint32_t)0x00000002U)        /*!<Remote Transmission Request */
-#define  CAN_RI0R_IDE                        ((uint32_t)0x00000004U)        /*!<Identifier Extension */
-#define  CAN_RI0R_EXID                       ((uint32_t)0x001FFFF8U)        /*!<Extended Identifier */
-#define  CAN_RI0R_STID                       ((uint32_t)0xFFE00000U)        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT0R register  ******************/
-#define  CAN_RDT0R_DLC                       ((uint32_t)0x0000000FU)        /*!<Data Length Code */
-#define  CAN_RDT0R_FMI                       ((uint32_t)0x0000FF00U)        /*!<Filter Match Index */
-#define  CAN_RDT0R_TIME                      ((uint32_t)0xFFFF0000U)        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL0R register  ******************/
-#define  CAN_RDL0R_DATA0                     ((uint32_t)0x000000FFU)        /*!<Data byte 0 */
-#define  CAN_RDL0R_DATA1                     ((uint32_t)0x0000FF00U)        /*!<Data byte 1 */
-#define  CAN_RDL0R_DATA2                     ((uint32_t)0x00FF0000U)        /*!<Data byte 2 */
-#define  CAN_RDL0R_DATA3                     ((uint32_t)0xFF000000U)        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH0R register  ******************/
-#define  CAN_RDH0R_DATA4                     ((uint32_t)0x000000FFU)        /*!<Data byte 4 */
-#define  CAN_RDH0R_DATA5                     ((uint32_t)0x0000FF00U)        /*!<Data byte 5 */
-#define  CAN_RDH0R_DATA6                     ((uint32_t)0x00FF0000U)        /*!<Data byte 6 */
-#define  CAN_RDH0R_DATA7                     ((uint32_t)0xFF000000U)        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI1R register  *******************/
-#define  CAN_RI1R_RTR                        ((uint32_t)0x00000002U)        /*!<Remote Transmission Request */
-#define  CAN_RI1R_IDE                        ((uint32_t)0x00000004U)        /*!<Identifier Extension */
-#define  CAN_RI1R_EXID                       ((uint32_t)0x001FFFF8U)        /*!<Extended identifier */
-#define  CAN_RI1R_STID                       ((uint32_t)0xFFE00000U)        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT1R register  ******************/
-#define  CAN_RDT1R_DLC                       ((uint32_t)0x0000000FU)        /*!<Data Length Code */
-#define  CAN_RDT1R_FMI                       ((uint32_t)0x0000FF00U)        /*!<Filter Match Index */
-#define  CAN_RDT1R_TIME                      ((uint32_t)0xFFFF0000U)        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL1R register  ******************/
-#define  CAN_RDL1R_DATA0                     ((uint32_t)0x000000FFU)        /*!<Data byte 0 */
-#define  CAN_RDL1R_DATA1                     ((uint32_t)0x0000FF00U)        /*!<Data byte 1 */
-#define  CAN_RDL1R_DATA2                     ((uint32_t)0x00FF0000U)        /*!<Data byte 2 */
-#define  CAN_RDL1R_DATA3                     ((uint32_t)0xFF000000U)        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH1R register  ******************/
-#define  CAN_RDH1R_DATA4                     ((uint32_t)0x000000FFU)        /*!<Data byte 4 */
-#define  CAN_RDH1R_DATA5                     ((uint32_t)0x0000FF00U)        /*!<Data byte 5 */
-#define  CAN_RDH1R_DATA6                     ((uint32_t)0x00FF0000U)        /*!<Data byte 6 */
-#define  CAN_RDH1R_DATA7                     ((uint32_t)0xFF000000U)        /*!<Data byte 7 */
-
-/*!<CAN filter registers */
-/*******************  Bit definition for CAN_FMR register  ********************/
-#define  CAN_FMR_FINIT                       ((uint8_t)0x01U)               /*!<Filter Init Mode */
-
-/*******************  Bit definition for CAN_FM1R register  *******************/
-#define  CAN_FM1R_FBM                        ((uint16_t)0x3FFFU)            /*!<Filter Mode */
-#define  CAN_FM1R_FBM0                       ((uint16_t)0x0001U)            /*!<Filter Init Mode bit 0 */
-#define  CAN_FM1R_FBM1                       ((uint16_t)0x0002U)            /*!<Filter Init Mode bit 1 */
-#define  CAN_FM1R_FBM2                       ((uint16_t)0x0004U)            /*!<Filter Init Mode bit 2 */
-#define  CAN_FM1R_FBM3                       ((uint16_t)0x0008U)            /*!<Filter Init Mode bit 3 */
-#define  CAN_FM1R_FBM4                       ((uint16_t)0x0010U)            /*!<Filter Init Mode bit 4 */
-#define  CAN_FM1R_FBM5                       ((uint16_t)0x0020U)            /*!<Filter Init Mode bit 5 */
-#define  CAN_FM1R_FBM6                       ((uint16_t)0x0040U)            /*!<Filter Init Mode bit 6 */
-#define  CAN_FM1R_FBM7                       ((uint16_t)0x0080U)            /*!<Filter Init Mode bit 7 */
-#define  CAN_FM1R_FBM8                       ((uint16_t)0x0100U)            /*!<Filter Init Mode bit 8 */
-#define  CAN_FM1R_FBM9                       ((uint16_t)0x0200U)            /*!<Filter Init Mode bit 9 */
-#define  CAN_FM1R_FBM10                      ((uint16_t)0x0400U)            /*!<Filter Init Mode bit 10 */
-#define  CAN_FM1R_FBM11                      ((uint16_t)0x0800U)            /*!<Filter Init Mode bit 11 */
-#define  CAN_FM1R_FBM12                      ((uint16_t)0x1000U)            /*!<Filter Init Mode bit 12 */
-#define  CAN_FM1R_FBM13                      ((uint16_t)0x2000U)            /*!<Filter Init Mode bit 13 */
-
-/*******************  Bit definition for CAN_FS1R register  *******************/
-#define  CAN_FS1R_FSC                        ((uint16_t)0x3FFFU)            /*!<Filter Scale Configuration */
-#define  CAN_FS1R_FSC0                       ((uint16_t)0x0001U)            /*!<Filter Scale Configuration bit 0 */
-#define  CAN_FS1R_FSC1                       ((uint16_t)0x0002U)            /*!<Filter Scale Configuration bit 1 */
-#define  CAN_FS1R_FSC2                       ((uint16_t)0x0004U)            /*!<Filter Scale Configuration bit 2 */
-#define  CAN_FS1R_FSC3                       ((uint16_t)0x0008U)            /*!<Filter Scale Configuration bit 3 */
-#define  CAN_FS1R_FSC4                       ((uint16_t)0x0010U)            /*!<Filter Scale Configuration bit 4 */
-#define  CAN_FS1R_FSC5                       ((uint16_t)0x0020U)            /*!<Filter Scale Configuration bit 5 */
-#define  CAN_FS1R_FSC6                       ((uint16_t)0x0040U)            /*!<Filter Scale Configuration bit 6 */
-#define  CAN_FS1R_FSC7                       ((uint16_t)0x0080U)            /*!<Filter Scale Configuration bit 7 */
-#define  CAN_FS1R_FSC8                       ((uint16_t)0x0100U)            /*!<Filter Scale Configuration bit 8 */
-#define  CAN_FS1R_FSC9                       ((uint16_t)0x0200U)            /*!<Filter Scale Configuration bit 9 */
-#define  CAN_FS1R_FSC10                      ((uint16_t)0x0400U)            /*!<Filter Scale Configuration bit 10 */
-#define  CAN_FS1R_FSC11                      ((uint16_t)0x0800U)            /*!<Filter Scale Configuration bit 11 */
-#define  CAN_FS1R_FSC12                      ((uint16_t)0x1000U)            /*!<Filter Scale Configuration bit 12 */
-#define  CAN_FS1R_FSC13                      ((uint16_t)0x2000U)            /*!<Filter Scale Configuration bit 13 */
-
-/******************  Bit definition for CAN_FFA1R register  *******************/
-#define  CAN_FFA1R_FFA                       ((uint16_t)0x3FFFU)            /*!<Filter FIFO Assignment */
-#define  CAN_FFA1R_FFA0                      ((uint16_t)0x0001U)            /*!<Filter FIFO Assignment for Filter 0 */
-#define  CAN_FFA1R_FFA1                      ((uint16_t)0x0002U)            /*!<Filter FIFO Assignment for Filter 1 */
-#define  CAN_FFA1R_FFA2                      ((uint16_t)0x0004U)            /*!<Filter FIFO Assignment for Filter 2 */
-#define  CAN_FFA1R_FFA3                      ((uint16_t)0x0008U)            /*!<Filter FIFO Assignment for Filter 3 */
-#define  CAN_FFA1R_FFA4                      ((uint16_t)0x0010U)            /*!<Filter FIFO Assignment for Filter 4 */
-#define  CAN_FFA1R_FFA5                      ((uint16_t)0x0020U)            /*!<Filter FIFO Assignment for Filter 5 */
-#define  CAN_FFA1R_FFA6                      ((uint16_t)0x0040U)            /*!<Filter FIFO Assignment for Filter 6 */
-#define  CAN_FFA1R_FFA7                      ((uint16_t)0x0080U)            /*!<Filter FIFO Assignment for Filter 7 */
-#define  CAN_FFA1R_FFA8                      ((uint16_t)0x0100U)            /*!<Filter FIFO Assignment for Filter 8 */
-#define  CAN_FFA1R_FFA9                      ((uint16_t)0x0200U)            /*!<Filter FIFO Assignment for Filter 9 */
-#define  CAN_FFA1R_FFA10                     ((uint16_t)0x0400U)            /*!<Filter FIFO Assignment for Filter 10 */
-#define  CAN_FFA1R_FFA11                     ((uint16_t)0x0800U)            /*!<Filter FIFO Assignment for Filter 11 */
-#define  CAN_FFA1R_FFA12                     ((uint16_t)0x1000U)            /*!<Filter FIFO Assignment for Filter 12 */
-#define  CAN_FFA1R_FFA13                     ((uint16_t)0x2000U)            /*!<Filter FIFO Assignment for Filter 13 */
-
-/*******************  Bit definition for CAN_FA1R register  *******************/
-#define  CAN_FA1R_FACT                       ((uint16_t)0x3FFFU)            /*!<Filter Active */
-#define  CAN_FA1R_FACT0                      ((uint16_t)0x0001U)            /*!<Filter 0 Active */
-#define  CAN_FA1R_FACT1                      ((uint16_t)0x0002U)            /*!<Filter 1 Active */
-#define  CAN_FA1R_FACT2                      ((uint16_t)0x0004U)            /*!<Filter 2 Active */
-#define  CAN_FA1R_FACT3                      ((uint16_t)0x0008U)            /*!<Filter 3 Active */
-#define  CAN_FA1R_FACT4                      ((uint16_t)0x0010U)            /*!<Filter 4 Active */
-#define  CAN_FA1R_FACT5                      ((uint16_t)0x0020U)            /*!<Filter 5 Active */
-#define  CAN_FA1R_FACT6                      ((uint16_t)0x0040U)            /*!<Filter 6 Active */
-#define  CAN_FA1R_FACT7                      ((uint16_t)0x0080U)            /*!<Filter 7 Active */
-#define  CAN_FA1R_FACT8                      ((uint16_t)0x0100U)            /*!<Filter 8 Active */
-#define  CAN_FA1R_FACT9                      ((uint16_t)0x0200U)            /*!<Filter 9 Active */
-#define  CAN_FA1R_FACT10                     ((uint16_t)0x0400U)            /*!<Filter 10 Active */
-#define  CAN_FA1R_FACT11                     ((uint16_t)0x0800U)            /*!<Filter 11 Active */
-#define  CAN_FA1R_FACT12                     ((uint16_t)0x1000U)            /*!<Filter 12 Active */
-#define  CAN_FA1R_FACT13                     ((uint16_t)0x2000U)            /*!<Filter 13 Active */
-
-/*******************  Bit definition for CAN_F0R1 register  *******************/
-#define  CAN_F0R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F0R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F0R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F0R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F0R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F0R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F0R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F0R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F0R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F0R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F0R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F0R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F0R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F0R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F0R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F0R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F0R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F0R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F0R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F0R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F0R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F0R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F0R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F0R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F0R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F0R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F0R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F0R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F0R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F0R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F0R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F0R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R1 register  *******************/
-#define  CAN_F1R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F1R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F1R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F1R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F1R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F1R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F1R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F1R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F1R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F1R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F1R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F1R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F1R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F1R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F1R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F1R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F1R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F1R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F1R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F1R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F1R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F1R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F1R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F1R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F1R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F1R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F1R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F1R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F1R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F1R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F1R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F1R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R1 register  *******************/
-#define  CAN_F2R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F2R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F2R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F2R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F2R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F2R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F2R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F2R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F2R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F2R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F2R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F2R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F2R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F2R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F2R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F2R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F2R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F2R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F2R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F2R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F2R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F2R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F2R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F2R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F2R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F2R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F2R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F2R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F2R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F2R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F2R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F2R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R1 register  *******************/
-#define  CAN_F3R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F3R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F3R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F3R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F3R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F3R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F3R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F3R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F3R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F3R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F3R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F3R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F3R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F3R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F3R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F3R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F3R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F3R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F3R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F3R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F3R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F3R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F3R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F3R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F3R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F3R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F3R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F3R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F3R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F3R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F3R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F3R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R1 register  *******************/
-#define  CAN_F4R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F4R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F4R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F4R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F4R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F4R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F4R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F4R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F4R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F4R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F4R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F4R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F4R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F4R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F4R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F4R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F4R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F4R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F4R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F4R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F4R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F4R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F4R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F4R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F4R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F4R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F4R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F4R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F4R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F4R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F4R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F4R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R1 register  *******************/
-#define  CAN_F5R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F5R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F5R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F5R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F5R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F5R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F5R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F5R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F5R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F5R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F5R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F5R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F5R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F5R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F5R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F5R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F5R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F5R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F5R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F5R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F5R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F5R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F5R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F5R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F5R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F5R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F5R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F5R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F5R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F5R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F5R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F5R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R1 register  *******************/
-#define  CAN_F6R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F6R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F6R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F6R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F6R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F6R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F6R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F6R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F6R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F6R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F6R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F6R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F6R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F6R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F6R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F6R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F6R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F6R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F6R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F6R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F6R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F6R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F6R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F6R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F6R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F6R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F6R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F6R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F6R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F6R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F6R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F6R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R1 register  *******************/
-#define  CAN_F7R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F7R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F7R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F7R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F7R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F7R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F7R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F7R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F7R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F7R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F7R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F7R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F7R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F7R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F7R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F7R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F7R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F7R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F7R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F7R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F7R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F7R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F7R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F7R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F7R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F7R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F7R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F7R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F7R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F7R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F7R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F7R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R1 register  *******************/
-#define  CAN_F8R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F8R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F8R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F8R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F8R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F8R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F8R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F8R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F8R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F8R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F8R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F8R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F8R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F8R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F8R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F8R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F8R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F8R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F8R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F8R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F8R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F8R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F8R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F8R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F8R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F8R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F8R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F8R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F8R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F8R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F8R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F8R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R1 register  *******************/
-#define  CAN_F9R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F9R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F9R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F9R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F9R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F9R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F9R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F9R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F9R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F9R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F9R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F9R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F9R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F9R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F9R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F9R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F9R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F9R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F9R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F9R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F9R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F9R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F9R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F9R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F9R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F9R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F9R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F9R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F9R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F9R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F9R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F9R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R1 register  ******************/
-#define  CAN_F10R1_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F10R1_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F10R1_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F10R1_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F10R1_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F10R1_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F10R1_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F10R1_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F10R1_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F10R1_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F10R1_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F10R1_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F10R1_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F10R1_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F10R1_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F10R1_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F10R1_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F10R1_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F10R1_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F10R1_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F10R1_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F10R1_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F10R1_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F10R1_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F10R1_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F10R1_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F10R1_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F10R1_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F10R1_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F10R1_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F10R1_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F10R1_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R1 register  ******************/
-#define  CAN_F11R1_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F11R1_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F11R1_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F11R1_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F11R1_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F11R1_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F11R1_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F11R1_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F11R1_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F11R1_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F11R1_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F11R1_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F11R1_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F11R1_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F11R1_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F11R1_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F11R1_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F11R1_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F11R1_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F11R1_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F11R1_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F11R1_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F11R1_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F11R1_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F11R1_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F11R1_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F11R1_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F11R1_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F11R1_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F11R1_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F11R1_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F11R1_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R1 register  ******************/
-#define  CAN_F12R1_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F12R1_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F12R1_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F12R1_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F12R1_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F12R1_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F12R1_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F12R1_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F12R1_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F12R1_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F12R1_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F12R1_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F12R1_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F12R1_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F12R1_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F12R1_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F12R1_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F12R1_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F12R1_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F12R1_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F12R1_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F12R1_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F12R1_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F12R1_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F12R1_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F12R1_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F12R1_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F12R1_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F12R1_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F12R1_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F12R1_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F12R1_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R1 register  ******************/
-#define  CAN_F13R1_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F13R1_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F13R1_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F13R1_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F13R1_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F13R1_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F13R1_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F13R1_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F13R1_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F13R1_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F13R1_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F13R1_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F13R1_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F13R1_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F13R1_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F13R1_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F13R1_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F13R1_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F13R1_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F13R1_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F13R1_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F13R1_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F13R1_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F13R1_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F13R1_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F13R1_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F13R1_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F13R1_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F13R1_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F13R1_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F13R1_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F13R1_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F0R2 register  *******************/
-#define  CAN_F0R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F0R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F0R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F0R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F0R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F0R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F0R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F0R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F0R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F0R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F0R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F0R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F0R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F0R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F0R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F0R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F0R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F0R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F0R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F0R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F0R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F0R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F0R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F0R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F0R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F0R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F0R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F0R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F0R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F0R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F0R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F0R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R2 register  *******************/
-#define  CAN_F1R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F1R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F1R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F1R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F1R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F1R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F1R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F1R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F1R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F1R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F1R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F1R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F1R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F1R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F1R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F1R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F1R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F1R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F1R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F1R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F1R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F1R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F1R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F1R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F1R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F1R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F1R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F1R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F1R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F1R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F1R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F1R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R2 register  *******************/
-#define  CAN_F2R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F2R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F2R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F2R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F2R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F2R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F2R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F2R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F2R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F2R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F2R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F2R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F2R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F2R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F2R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F2R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F2R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F2R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F2R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F2R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F2R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F2R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F2R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F2R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F2R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F2R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F2R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F2R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F2R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F2R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F2R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F2R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R2 register  *******************/
-#define  CAN_F3R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F3R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F3R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F3R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F3R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F3R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F3R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F3R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F3R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F3R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F3R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F3R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F3R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F3R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F3R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F3R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F3R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F3R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F3R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F3R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F3R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F3R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F3R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F3R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F3R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F3R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F3R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F3R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F3R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F3R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F3R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F3R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R2 register  *******************/
-#define  CAN_F4R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F4R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F4R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F4R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F4R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F4R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F4R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F4R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F4R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F4R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F4R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F4R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F4R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F4R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F4R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F4R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F4R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F4R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F4R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F4R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F4R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F4R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F4R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F4R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F4R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F4R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F4R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F4R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F4R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F4R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F4R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F4R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R2 register  *******************/
-#define  CAN_F5R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F5R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F5R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F5R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F5R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F5R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F5R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F5R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F5R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F5R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F5R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F5R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F5R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F5R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F5R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F5R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F5R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F5R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F5R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F5R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F5R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F5R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F5R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F5R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F5R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F5R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F5R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F5R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F5R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F5R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F5R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F5R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R2 register  *******************/
-#define  CAN_F6R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F6R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F6R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F6R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F6R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F6R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F6R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F6R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F6R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F6R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F6R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F6R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F6R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F6R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F6R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F6R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F6R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F6R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F6R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F6R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F6R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F6R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F6R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F6R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F6R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F6R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F6R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F6R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F6R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F6R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F6R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F6R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R2 register  *******************/
-#define  CAN_F7R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F7R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F7R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F7R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F7R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F7R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F7R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F7R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F7R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F7R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F7R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F7R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F7R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F7R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F7R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F7R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F7R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F7R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F7R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F7R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F7R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F7R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F7R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F7R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F7R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F7R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F7R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F7R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F7R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F7R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F7R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F7R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R2 register  *******************/
-#define  CAN_F8R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F8R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F8R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F8R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F8R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F8R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F8R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F8R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F8R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F8R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F8R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F8R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F8R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F8R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F8R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F8R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F8R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F8R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F8R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F8R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F8R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F8R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F8R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F8R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F8R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F8R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F8R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F8R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F8R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F8R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F8R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F8R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R2 register  *******************/
-#define  CAN_F9R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F9R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F9R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F9R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F9R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F9R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F9R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F9R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F9R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F9R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F9R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F9R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F9R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F9R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F9R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F9R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F9R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F9R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F9R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F9R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F9R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F9R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F9R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F9R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F9R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F9R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F9R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F9R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F9R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F9R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F9R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F9R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R2 register  ******************/
-#define  CAN_F10R2_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F10R2_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F10R2_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F10R2_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F10R2_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F10R2_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F10R2_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F10R2_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F10R2_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F10R2_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F10R2_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F10R2_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F10R2_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F10R2_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F10R2_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F10R2_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F10R2_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F10R2_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F10R2_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F10R2_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F10R2_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F10R2_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F10R2_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F10R2_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F10R2_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F10R2_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F10R2_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F10R2_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F10R2_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F10R2_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F10R2_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F10R2_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R2 register  ******************/
-#define  CAN_F11R2_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F11R2_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F11R2_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F11R2_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F11R2_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F11R2_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F11R2_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F11R2_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F11R2_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F11R2_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F11R2_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F11R2_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F11R2_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F11R2_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F11R2_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F11R2_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F11R2_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F11R2_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F11R2_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F11R2_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F11R2_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F11R2_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F11R2_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F11R2_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F11R2_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F11R2_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F11R2_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F11R2_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F11R2_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F11R2_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F11R2_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F11R2_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R2 register  ******************/
-#define  CAN_F12R2_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F12R2_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F12R2_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F12R2_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F12R2_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F12R2_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F12R2_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F12R2_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F12R2_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F12R2_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F12R2_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F12R2_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F12R2_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F12R2_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F12R2_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F12R2_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F12R2_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F12R2_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F12R2_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F12R2_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F12R2_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F12R2_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F12R2_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F12R2_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F12R2_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F12R2_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F12R2_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F12R2_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F12R2_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F12R2_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F12R2_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F12R2_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R2 register  ******************/
-#define  CAN_F13R2_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F13R2_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F13R2_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F13R2_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F13R2_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F13R2_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F13R2_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F13R2_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F13R2_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F13R2_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F13R2_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F13R2_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F13R2_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F13R2_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F13R2_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F13R2_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F13R2_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F13R2_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F13R2_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F13R2_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F13R2_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F13R2_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F13R2_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F13R2_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F13R2_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F13R2_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F13R2_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F13R2_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F13R2_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F13R2_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F13R2_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F13R2_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRC calculation unit                              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFFU) /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         ((uint8_t)0xFFU)        /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        ((uint32_t)0x00000001U) /*!< RESET the CRC computation unit bit */
-#define  CRC_CR_POLYSIZE                     ((uint32_t)0x00000018U) /*!< Polynomial size bits */
-#define  CRC_CR_POLYSIZE_0                   ((uint32_t)0x00000008U) /*!< Polynomial size bit 0 */
-#define  CRC_CR_POLYSIZE_1                   ((uint32_t)0x00000010U) /*!< Polynomial size bit 1 */
-#define  CRC_CR_REV_IN                       ((uint32_t)0x00000060U) /*!< REV_IN Reverse Input Data bits */
-#define  CRC_CR_REV_IN_0                     ((uint32_t)0x00000020U) /*!< Bit 0 */
-#define  CRC_CR_REV_IN_1                     ((uint32_t)0x00000040U) /*!< Bit 1 */
-#define  CRC_CR_REV_OUT                      ((uint32_t)0x00000080U) /*!< REV_OUT Reverse Output Data bits */
-
-/*******************  Bit definition for CRC_INIT register  *******************/
-#define  CRC_INIT_INIT                       ((uint32_t)0xFFFFFFFFU) /*!< Initial CRC value bits */
-
-/*******************  Bit definition for CRC_POL register  ********************/
-#define  CRC_POL_POL                         ((uint32_t)0xFFFFFFFFU) /*!< Coefficients of the polynomial */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Digital to Analog Converter                           */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DAC_CR register  ********************/
-#define  DAC_CR_EN1                          ((uint32_t)0x00000001U)        /*!<DAC channel1 enable */
-#define  DAC_CR_TEN1                         ((uint32_t)0x00000004U)        /*!<DAC channel1 Trigger enable */
-
-#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038U)        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008U)        /*!<Bit 0 */
-#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010U)        /*!<Bit 1 */
-#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020U)        /*!<Bit 2 */
-
-#define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0U)        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040U)        /*!<Bit 0 */
-#define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080U)        /*!<Bit 1 */
-
-#define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00U)        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800U)        /*!<Bit 3 */
-
-#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000U)        /*!<DAC channel1 DMA enable */
-#define  DAC_CR_DMAUDRIE1                    ((uint32_t)0x00002000U)        /*!<DAC channel 1 DMA underrun interrupt enable  >*/
-#define  DAC_CR_CEN1                         ((uint32_t)0x00004000U)        /*!<DAC channel 1 calibration enable >*/
-
-#define  DAC_CR_EN2                          ((uint32_t)0x00010000U)        /*!<DAC channel2 enable */
-#define  DAC_CR_TEN2                         ((uint32_t)0x00040000U)        /*!<DAC channel2 Trigger enable */
-
-#define  DAC_CR_TSEL2                        ((uint32_t)0x00380000U)        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000U)        /*!<Bit 0 */
-#define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000U)        /*!<Bit 1 */
-#define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000U)        /*!<Bit 2 */
-
-#define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000U)        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000U)        /*!<Bit 0 */
-#define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000U)        /*!<Bit 1 */
-
-#define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000U)        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000U)        /*!<Bit 3 */
-
-#define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000U)        /*!<DAC channel2 DMA enabled */
-#define  DAC_CR_DMAUDRIE2                    ((uint32_t)0x20000000U)        /*!<DAC channel2 DMA underrun interrupt enable  >*/
-#define  DAC_CR_CEN2                         ((uint32_t)0x40000000U)        /*!<DAC channel2 calibration enable >*/
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define  DAC_SWTRIGR_SWTRIG1                 ((uint32_t)0x00000001U)        /*!<DAC channel1 software trigger */
-#define  DAC_SWTRIGR_SWTRIG2                 ((uint32_t)0x00000002U)        /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define  DAC_DHR12R1_DACC1DHR                ((uint32_t)0x00000FFFU)        /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define  DAC_DHR12L1_DACC1DHR                ((uint32_t)0x0000FFF0U)        /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define  DAC_DHR8R1_DACC1DHR                 ((uint32_t)0x000000FFU)        /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define  DAC_DHR12R2_DACC2DHR                ((uint32_t)0x00000FFFU)        /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define  DAC_DHR12L2_DACC2DHR                ((uint32_t)0x0000FFF0U)        /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define  DAC_DHR8R2_DACC2DHR                 ((uint32_t)0x000000FFU)        /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define  DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFFU)        /*!<DAC channel1 12-bit Right aligned data */
-#define  DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000U)        /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define  DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0U)        /*!<DAC channel1 12-bit Left aligned data */
-#define  DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000U)        /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define  DAC_DHR8RD_DACC1DHR                 ((uint32_t)0x000000FFU)        /*!<DAC channel1 8-bit Right aligned data */
-#define  DAC_DHR8RD_DACC2DHR                 ((uint32_t)0x0000FF00U)        /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define  DAC_DOR1_DACC1DOR                   ((uint32_t)0x00000FFFU)        /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define  DAC_DOR2_DACC2DOR                   ((uint32_t)0x00000FFFU)        /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000U)        /*!<DAC channel1 DMA underrun flag */
-#define  DAC_SR_CAL_FLAG1                    ((uint32_t)0x00004000U)        /*!<DAC channel1 calibration offset status */
-#define  DAC_SR_BWST1                        ((uint32_t)0x20008000U)        /*!<DAC channel1 busy writing sample time flag */
-
-#define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000U)        /*!<DAC channel2 DMA underrun flag */
-#define  DAC_SR_CAL_FLAG2                    ((uint32_t)0x40000000U)        /*!<DAC channel2 calibration offset status */
-#define  DAC_SR_BWST2                        ((uint32_t)0x80000000U)        /*!<DAC channel2 busy writing sample time flag */
-
-/*******************  Bit definition for DAC_CCR register  ********************/
-#define  DAC_CCR_OTRIM1                      ((uint32_t)0x0000001FU)        /*!<DAC channel1 offset trimming value */
-#define  DAC_CCR_OTRIM2                      ((uint32_t)0x001F0000U)        /*!<DAC channel2 offset trimming value */
-
-/*******************  Bit definition for DAC_MCR register  *******************/
-#define  DAC_MCR_MODE1                        ((uint32_t)0x00000007U)        /*!<MODE1[2:0] (DAC channel1 mode) */
-#define  DAC_MCR_MODE1_0                      ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  DAC_MCR_MODE1_1                      ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  DAC_MCR_MODE1_2                      ((uint32_t)0x00000004U)        /*!<Bit 2 */
-
-#define  DAC_MCR_MODE2                        ((uint32_t)0x00070000U)        /*!<MODE2[2:0] (DAC channel2 mode) */
-#define  DAC_MCR_MODE2_0                      ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  DAC_MCR_MODE2_1                      ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  DAC_MCR_MODE2_2                      ((uint32_t)0x00040000U)        /*!<Bit 2 */
-
-/******************  Bit definition for DAC_SHSR1 register  ******************/
-#define  DAC_SHSR1_TSAMPLE1                   ((uint32_t)0x000003FFU)        /*!<DAC channel1 sample time */
-
-/******************  Bit definition for DAC_SHSR2 register  ******************/
-#define  DAC_SHSR2_TSAMPLE2                   ((uint32_t)0x000003FFU)        /*!<DAC channel2 sample time */
-
-/******************  Bit definition for DAC_SHHR register  ******************/
-#define  DAC_SHHR_THOLD1                      ((uint32_t)0x000003FFU)        /*!<DAC channel1 hold time */
-#define  DAC_SHHR_THOLD2                      ((uint32_t)0x03FF0000U)        /*!<DAC channel2 hold time */
-
-/******************  Bit definition for DAC_SHRR register  ******************/
-#define  DAC_SHRR_TREFRESH1                   ((uint32_t)0x000000FFU)        /*!<DAC channel1 refresh time */
-#define  DAC_SHRR_TREFRESH2                   ((uint32_t)0x00FF0000U)        /*!<DAC channel2 refresh time */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                 Digital Filter for Sigma Delta Modulators                  */
-/*                                                                            */
-/******************************************************************************/
-
-/****************   DFSDM channel configuration registers  ********************/
-
-/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/
-#define  DFSDM_CHCFGR1_DFSDMEN                ((uint32_t)0x80000000U)            /*!< Global enable for DFSDM interface */
-#define  DFSDM_CHCFGR1_CKOUTSRC               ((uint32_t)0x40000000U)            /*!< Output serial clock source selection */
-#define  DFSDM_CHCFGR1_CKOUTDIV               ((uint32_t)0x00FF0000U)            /*!< CKOUTDIV[7:0] output serial clock divider */
-#define  DFSDM_CHCFGR1_DATPACK                ((uint32_t)0x0000C000U)            /*!< DATPACK[1:0] Data packing mode */
-#define  DFSDM_CHCFGR1_DATPACK_1              ((uint32_t)0x00008000U)            /*!< Data packing mode, Bit 1 */
-#define  DFSDM_CHCFGR1_DATPACK_0              ((uint32_t)0x00004000U)            /*!< Data packing mode, Bit 0 */
-#define  DFSDM_CHCFGR1_DATMPX                 ((uint32_t)0x00003000U)            /*!< DATMPX[1:0] Input data multiplexer for channel y */
-#define  DFSDM_CHCFGR1_DATMPX_1               ((uint32_t)0x00002000U)            /*!< Input data multiplexer for channel y, Bit 1 */
-#define  DFSDM_CHCFGR1_DATMPX_0               ((uint32_t)0x00001000U)            /*!< Input data multiplexer for channel y, Bit 0 */
-#define  DFSDM_CHCFGR1_CHINSEL                ((uint32_t)0x00000100U)            /*!< Serial inputs selection for channel y */
-#define  DFSDM_CHCFGR1_CHEN                   ((uint32_t)0x00000080U)            /*!< Channel y enable */
-#define  DFSDM_CHCFGR1_CKABEN                 ((uint32_t)0x00000040U)            /*!< Clock absence detector enable on channel y */
-#define  DFSDM_CHCFGR1_SCDEN                  ((uint32_t)0x00000020U)            /*!< Short circuit detector enable on channel y */
-#define  DFSDM_CHCFGR1_SPICKSEL               ((uint32_t)0x0000000CU)            /*!< SPICKSEL[1:0] SPI clock select for channel y */
-#define  DFSDM_CHCFGR1_SPICKSEL_1             ((uint32_t)0x00000008U)            /*!< SPI clock select for channel y, Bit 1 */
-#define  DFSDM_CHCFGR1_SPICKSEL_0             ((uint32_t)0x00000004U)            /*!< SPI clock select for channel y, Bit 0 */
-#define  DFSDM_CHCFGR1_SITP                   ((uint32_t)0x00000003U)            /*!< SITP[1:0] Serial interface type for channel y */
-#define  DFSDM_CHCFGR1_SITP_1                 ((uint32_t)0x00000002U)            /*!< Serial interface type for channel y, Bit 1 */
-#define  DFSDM_CHCFGR1_SITP_0                 ((uint32_t)0x00000001U)            /*!< Serial interface type for channel y, Bit 0 */
-
-/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/
-#define  DFSDM_CHCFGR2_OFFSET                 ((uint32_t)0xFFFFFF00U)            /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
-#define  DFSDM_CHCFGR2_DTRBS                  ((uint32_t)0x000000F8U)            /*!< DTRBS[4:0] Data right bit-shift for channel y */
-
-/******************  Bit definition for DFSDM_AWSCDR register *****************/
-#define  DFSDM_AWSCDR_AWFORD                  ((uint32_t)0x00C00000U)            /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
-#define  DFSDM_AWSCDR_AWFORD_1                ((uint32_t)0x00800000U)            /*!< Analog watchdog Sinc filter order on channel y, Bit 1 */
-#define  DFSDM_AWSCDR_AWFORD_0                ((uint32_t)0x00400000U)            /*!< Analog watchdog Sinc filter order on channel y, Bit 0 */
-#define  DFSDM_AWSCDR_AWFOSR                  ((uint32_t)0x001F0000U)            /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
-#define  DFSDM_AWSCDR_BKSCD                   ((uint32_t)0x0000F000U)            /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
-#define  DFSDM_AWSCDR_SCDT                    ((uint32_t)0x000000FFU)            /*!< SCDT[7:0] Short circuit detector threshold for channel y */
-
-/****************  Bit definition for DFSDM_CHWDATR register *******************/
-#define  DFSDM_AWSCDR_WDATA                   ((uint32_t)0x0000FFFFU)            /*!< WDATA[15:0] Input channel y watchdog data */
-
-/****************  Bit definition for DFSDM_CHDATINR register *****************/
-#define  DFSDM_AWSCDR_INDAT0                   ((uint32_t)0x0000FFFFU)            /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
-#define  DFSDM_AWSCDR_INDAT1                   ((uint32_t)0xFFFF0000U)            /*!< INDAT0[15:0] Input data for channel y */
-
-/************************   DFSDM module registers  ****************************/
-
-/********************  Bit definition for DFSDM_CR1 register *******************/
-#define  DFSDM_CR1_AWFSEL                     ((uint32_t)0x40000000U)            /*!< Analog watchdog fast mode select */
-#define  DFSDM_CR1_FAST                       ((uint32_t)0x20000000U)            /*!< Fast conversion mode selection */
-#define  DFSDM_CR1_RCH                        ((uint32_t)0x07000000U)            /*!< RCH[2:0] Regular channel selection */
-#define  DFSDM_CR1_RDMAEN                     ((uint32_t)0x00200000U)            /*!< DMA channel enabled to read data for the regular conversion */
-#define  DFSDM_CR1_RSYNC                      ((uint32_t)0x00080000U)            /*!< Launch regular conversion synchronously with DFSDMx */
-#define  DFSDM_CR1_RCONT                      ((uint32_t)0x00040000U)            /*!< Continuous mode selection for regular conversions */
-#define  DFSDM_CR1_RSWSTART                   ((uint32_t)0x00020000U)            /*!< Software start of a conversion on the regular channel */
-#define  DFSDM_CR1_JEXTEN                     ((uint32_t)0x00006000U)            /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
-#define  DFSDM_CR1_JEXTEN_1                   ((uint32_t)0x00004000U)            /*!< Trigger enable and trigger edge selection for injected conversions, Bit 1 */
-#define  DFSDM_CR1_JEXTEN_0                   ((uint32_t)0x00002000U)            /*!< Trigger enable and trigger edge selection for injected conversions, Bit 0 */
-#define  DFSDM_CR1_JEXTSEL                    ((uint32_t)0x00000700U)            /*!< JEXTSEL[2:0]Trigger signal selection for launching injected conversions */
-#define  DFSDM_CR1_JEXTSEL_2                  ((uint32_t)0x00000400U)            /*!< Trigger signal selection for launching injected conversions, Bit 2 */
-#define  DFSDM_CR1_JEXTSEL_1                  ((uint32_t)0x00000200U)            /*!< Trigger signal selection for launching injected conversions, Bit 1 */
-#define  DFSDM_CR1_JEXTSEL_0                  ((uint32_t)0x00000100U)            /*!< Trigger signal selection for launching injected conversions, Bit 0 */
-#define  DFSDM_CR1_JDMAEN                     ((uint32_t)0x00000020U)            /*!< DMA channel enabled to read data for the injected channel group */
-#define  DFSDM_CR1_JSCAN                      ((uint32_t)0x00000010U)            /*!< Scanning conversion in continuous mode selection for injected conversions */
-#define  DFSDM_CR1_JSYNC                      ((uint32_t)0x00000008U)            /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */
-#define  DFSDM_CR1_JSWSTART                   ((uint32_t)0x00000002U)            /*!< Start the conversion of the injected group of channels */
-#define  DFSDM_CR1_DFEN                       ((uint32_t)0x00000001U)            /*!< DFSDM enable */
-
-/********************  Bit definition for DFSDM_CR2 register *******************/
-#define  DFSDM_CR2_AWDCH                      ((uint32_t)0x00FF0000U)            /*!< AWDCH[7:0] Analog watchdog channel selection */
-#define  DFSDM_CR2_EXCH                       ((uint32_t)0x0000FF00U)            /*!< EXCH[7:0] Extreme detector channel selection */
-#define  DFSDM_CR2_CKABIE                     ((uint32_t)0x00000040U)            /*!< Clock absence interrupt enable */
-#define  DFSDM_CR2_SCDIE                      ((uint32_t)0x00000020U)            /*!< Short circuit detector interrupt enable */
-#define  DFSDM_CR2_AWDIE                      ((uint32_t)0x00000010U)            /*!< Analog watchdog interrupt enable */
-#define  DFSDM_CR2_ROVRIE                     ((uint32_t)0x00000008U)            /*!< Regular data overrun interrupt enable */
-#define  DFSDM_CR2_JOVRIE                     ((uint32_t)0x00000004U)            /*!< Injected data overrun interrupt enable */
-#define  DFSDM_CR2_REOCIE                     ((uint32_t)0x00000002U)            /*!< Regular end of conversion interrupt enable */
-#define  DFSDM_CR2_JEOCIE                     ((uint32_t)0x00000001U)            /*!< Injected end of conversion interrupt enable */
-
-/********************  Bit definition for DFSDM_ISR register *******************/
-#define  DFSDM_ISR_SCDF                       ((uint32_t)0xFF000000U)            /*!< SCDF[7:0] Short circuit detector flag */
-#define  DFSDM_ISR_CKABF                      ((uint32_t)0x00FF0000U)            /*!< CKABF[7:0] Clock absence flag */
-#define  DFSDM_ISR_RCIP                       ((uint32_t)0x00004000U)            /*!< Regular conversion in progress status */
-#define  DFSDM_ISR_JCIP                       ((uint32_t)0x00002000U)            /*!< Injected conversion in progress status */
-#define  DFSDM_ISR_AWDF                       ((uint32_t)0x00000010U)            /*!< Analog watchdog */
-#define  DFSDM_ISR_ROVRF                      ((uint32_t)0x00000008U)            /*!< Regular conversion overrun flag */
-#define  DFSDM_ISR_JOVRF                      ((uint32_t)0x00000004U)            /*!< Injected conversion overrun flag */
-#define  DFSDM_ISR_REOCF                      ((uint32_t)0x00000002U)            /*!< End of regular conversion flag */
-#define  DFSDM_ISR_JEOCF                      ((uint32_t)0x00000001U)            /*!< End of injected conversion flag */
-
-/********************  Bit definition for DFSDM_ICR register *******************/
-#define  DFSDM_ICR_CLRSCSDF                   ((uint32_t)0xFF000000U)            /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
-#define  DFSDM_ICR_CLRCKABF                   ((uint32_t)0x00FF0000U)            /*!< CLRCKABF[7:0] Clear the clock absence flag */
-#define  DFSDM_ICR_CLRROVRF                   ((uint32_t)0x00000008U)            /*!< Clear the regular conversion overrun flag */
-#define  DFSDM_ICR_CLRJOVRF                   ((uint32_t)0x00000004U)            /*!< Clear the injected conversion overrun flag */
-
-/*******************  Bit definition for DFSDM_JCHGR register ******************/
-#define  DFSDM_JCHGR_JCHG                     ((uint32_t)0x000000FFU)            /*!< JCHG[7:0] Injected channel group selection */
-
-/********************  Bit definition for DFSDM_FCR register *******************/
-#define  DFSDM_FCR_FORD                       ((uint32_t)0xE0000000U)            /*!< FORD[2:0] Sinc filter order */
-#define  DFSDM_FCR_FORD_2                     ((uint32_t)0x80000000U)            /*!< Sinc filter order, Bit 2 */
-#define  DFSDM_FCR_FORD_1                     ((uint32_t)0x40000000U)            /*!< Sinc filter order, Bit 1 */
-#define  DFSDM_FCR_FORD_0                     ((uint32_t)0x20000000U)            /*!< Sinc filter order, Bit 0 */
-#define  DFSDM_FCR_FOSR                       ((uint32_t)0x03FF0000U)            /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
-#define  DFSDM_FCR_IOSR                       ((uint32_t)0x000000FFU)            /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
-
-/******************  Bit definition for DFSDM_JDATAR register *****************/
-#define  DFSDM_JDATAR_JDATA                   ((uint32_t)0xFFFFFF00U)            /*!< JDATA[23:0] Injected group conversion data */
-#define  DFSDM_JDATAR_JDATACH                 ((uint32_t)0x00000007U)            /*!< JDATACH[2:0] Injected channel most recently converted */
-
-/******************  Bit definition for DFSDM_RDATAR register *****************/
-#define  DFSDM_RDATAR_RDATA                   ((uint32_t)0xFFFFFF00U)            /*!< RDATA[23:0] Regular channel conversion data */
-#define  DFSDM_RDATAR_RPEND                   ((uint32_t)0x00000010U)            /*!< RPEND Regular channel pending data */
-#define  DFSDM_RDATAR_RDATACH                 ((uint32_t)0x00000007U)            /*!< RDATACH[2:0] Regular channel most recently converted */
-
-/******************  Bit definition for DFSDM_AWHTR register ******************/
-#define  DFSDM_AWHTR_AWHT                    ((uint32_t)0xFFFFFF00U)             /*!< AWHT[23:0] Analog watchdog high threshold */
-#define  DFSDM_AWHTR_BKAWH                   ((uint32_t)0x0000000FU)             /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
-
-/******************  Bit definition for DFSDM_AWLTR register ******************/
-#define  DFSDM_AWLTR_AWLT                    ((uint32_t)0xFFFFFF00U)             /*!< AWHT[23:0] Analog watchdog low threshold */
-#define  DFSDM_AWLTR_BKAWL                   ((uint32_t)0x0000000FU)             /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
-
-/******************  Bit definition for DFSDM_AWSR register ******************/
-#define  DFSDM_AWSR_AWHTF                    ((uint32_t)0x0000FF00U)             /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
-#define  DFSDM_AWSR_AWLTF                    ((uint32_t)0x000000FFU)             /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
-
-/******************  Bit definition for DFSDM_AWCFR) register *****************/
-#define  DFSDM_AWCFR_CLRAWHTF                ((uint32_t)0x0000FF00U)             /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
-#define  DFSDM_AWCFR_CLRAWLTF                ((uint32_t)0x000000FFU)             /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
-
-/******************  Bit definition for DFSDM_EXMAX register ******************/
-#define  DFSDM_EXMAX_EXMAX                   ((uint32_t)0xFFFFFF00U)             /*!< EXMAX[23:0] Extreme detector maximum value */
-#define  DFSDM_EXMAX_EXMAXCH                 ((uint32_t)0x00000007U)             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
-
-/******************  Bit definition for DFSDM_EXMIN register ******************/
-#define  DFSDM_EXMIN_EXMIN                   ((uint32_t)0xFFFFFF00U)             /*!< EXMIN[23:0] Extreme detector minimum value */
-#define  DFSDM_EXMIN_EXMINCH                 ((uint32_t)0x00000007U)             /*!< EXMINCH[2:0] Extreme detector minimum data channel */
-
-/******************  Bit definition for DFSDM_EXMIN register ******************/
-#define  DFSDM_CNVTIMR_CNVCNT                ((uint32_t)0xFFFFFFF0U)             /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define  DMA_ISR_GIF1                        ((uint32_t)0x00000001U)        /*!< Channel 1 Global interrupt flag */
-#define  DMA_ISR_TCIF1                       ((uint32_t)0x00000002U)        /*!< Channel 1 Transfer Complete flag */
-#define  DMA_ISR_HTIF1                       ((uint32_t)0x00000004U)        /*!< Channel 1 Half Transfer flag */
-#define  DMA_ISR_TEIF1                       ((uint32_t)0x00000008U)        /*!< Channel 1 Transfer Error flag */
-#define  DMA_ISR_GIF2                        ((uint32_t)0x00000010U)        /*!< Channel 2 Global interrupt flag */
-#define  DMA_ISR_TCIF2                       ((uint32_t)0x00000020U)        /*!< Channel 2 Transfer Complete flag */
-#define  DMA_ISR_HTIF2                       ((uint32_t)0x00000040U)        /*!< Channel 2 Half Transfer flag */
-#define  DMA_ISR_TEIF2                       ((uint32_t)0x00000080U)        /*!< Channel 2 Transfer Error flag */
-#define  DMA_ISR_GIF3                        ((uint32_t)0x00000100U)        /*!< Channel 3 Global interrupt flag */
-#define  DMA_ISR_TCIF3                       ((uint32_t)0x00000200U)        /*!< Channel 3 Transfer Complete flag */
-#define  DMA_ISR_HTIF3                       ((uint32_t)0x00000400U)        /*!< Channel 3 Half Transfer flag */
-#define  DMA_ISR_TEIF3                       ((uint32_t)0x00000800U)        /*!< Channel 3 Transfer Error flag */
-#define  DMA_ISR_GIF4                        ((uint32_t)0x00001000U)        /*!< Channel 4 Global interrupt flag */
-#define  DMA_ISR_TCIF4                       ((uint32_t)0x00002000U)        /*!< Channel 4 Transfer Complete flag */
-#define  DMA_ISR_HTIF4                       ((uint32_t)0x00004000U)        /*!< Channel 4 Half Transfer flag */
-#define  DMA_ISR_TEIF4                       ((uint32_t)0x00008000U)        /*!< Channel 4 Transfer Error flag */
-#define  DMA_ISR_GIF5                        ((uint32_t)0x00010000U)        /*!< Channel 5 Global interrupt flag */
-#define  DMA_ISR_TCIF5                       ((uint32_t)0x00020000U)        /*!< Channel 5 Transfer Complete flag */
-#define  DMA_ISR_HTIF5                       ((uint32_t)0x00040000U)        /*!< Channel 5 Half Transfer flag */
-#define  DMA_ISR_TEIF5                       ((uint32_t)0x00080000U)        /*!< Channel 5 Transfer Error flag */
-#define  DMA_ISR_GIF6                        ((uint32_t)0x00100000U)        /*!< Channel 6 Global interrupt flag */
-#define  DMA_ISR_TCIF6                       ((uint32_t)0x00200000U)        /*!< Channel 6 Transfer Complete flag */
-#define  DMA_ISR_HTIF6                       ((uint32_t)0x00400000U)        /*!< Channel 6 Half Transfer flag */
-#define  DMA_ISR_TEIF6                       ((uint32_t)0x00800000U)        /*!< Channel 6 Transfer Error flag */
-#define  DMA_ISR_GIF7                        ((uint32_t)0x01000000U)        /*!< Channel 7 Global interrupt flag */
-#define  DMA_ISR_TCIF7                       ((uint32_t)0x02000000U)        /*!< Channel 7 Transfer Complete flag */
-#define  DMA_ISR_HTIF7                       ((uint32_t)0x04000000U)        /*!< Channel 7 Half Transfer flag */
-#define  DMA_ISR_TEIF7                       ((uint32_t)0x08000000U)        /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define  DMA_IFCR_CGIF1                      ((uint32_t)0x00000001U)        /*!< Channel 1 Global interrupt clearr */
-#define  DMA_IFCR_CTCIF1                     ((uint32_t)0x00000002U)        /*!< Channel 1 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF1                     ((uint32_t)0x00000004U)        /*!< Channel 1 Half Transfer clear */
-#define  DMA_IFCR_CTEIF1                     ((uint32_t)0x00000008U)        /*!< Channel 1 Transfer Error clear */
-#define  DMA_IFCR_CGIF2                      ((uint32_t)0x00000010U)        /*!< Channel 2 Global interrupt clear */
-#define  DMA_IFCR_CTCIF2                     ((uint32_t)0x00000020U)        /*!< Channel 2 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF2                     ((uint32_t)0x00000040U)        /*!< Channel 2 Half Transfer clear */
-#define  DMA_IFCR_CTEIF2                     ((uint32_t)0x00000080U)        /*!< Channel 2 Transfer Error clear */
-#define  DMA_IFCR_CGIF3                      ((uint32_t)0x00000100U)        /*!< Channel 3 Global interrupt clear */
-#define  DMA_IFCR_CTCIF3                     ((uint32_t)0x00000200U)        /*!< Channel 3 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF3                     ((uint32_t)0x00000400U)        /*!< Channel 3 Half Transfer clear */
-#define  DMA_IFCR_CTEIF3                     ((uint32_t)0x00000800U)        /*!< Channel 3 Transfer Error clear */
-#define  DMA_IFCR_CGIF4                      ((uint32_t)0x00001000U)        /*!< Channel 4 Global interrupt clear */
-#define  DMA_IFCR_CTCIF4                     ((uint32_t)0x00002000U)        /*!< Channel 4 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF4                     ((uint32_t)0x00004000U)        /*!< Channel 4 Half Transfer clear */
-#define  DMA_IFCR_CTEIF4                     ((uint32_t)0x00008000U)        /*!< Channel 4 Transfer Error clear */
-#define  DMA_IFCR_CGIF5                      ((uint32_t)0x00010000U)        /*!< Channel 5 Global interrupt clear */
-#define  DMA_IFCR_CTCIF5                     ((uint32_t)0x00020000U)        /*!< Channel 5 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF5                     ((uint32_t)0x00040000U)        /*!< Channel 5 Half Transfer clear */
-#define  DMA_IFCR_CTEIF5                     ((uint32_t)0x00080000U)        /*!< Channel 5 Transfer Error clear */
-#define  DMA_IFCR_CGIF6                      ((uint32_t)0x00100000U)        /*!< Channel 6 Global interrupt clear */
-#define  DMA_IFCR_CTCIF6                     ((uint32_t)0x00200000U)        /*!< Channel 6 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF6                     ((uint32_t)0x00400000U)        /*!< Channel 6 Half Transfer clear */
-#define  DMA_IFCR_CTEIF6                     ((uint32_t)0x00800000U)        /*!< Channel 6 Transfer Error clear */
-#define  DMA_IFCR_CGIF7                      ((uint32_t)0x01000000U)        /*!< Channel 7 Global interrupt clear */
-#define  DMA_IFCR_CTCIF7                     ((uint32_t)0x02000000U)        /*!< Channel 7 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF7                     ((uint32_t)0x04000000U)        /*!< Channel 7 Half Transfer clear */
-#define  DMA_IFCR_CTEIF7                     ((uint32_t)0x08000000U)        /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  ********************/
-#define  DMA_CCR_EN                          ((uint32_t)0x00000001U)        /*!< Channel enable                      */
-#define  DMA_CCR_TCIE                        ((uint32_t)0x00000002U)        /*!< Transfer complete interrupt enable  */
-#define  DMA_CCR_HTIE                        ((uint32_t)0x00000004U)        /*!< Half Transfer interrupt enable      */
-#define  DMA_CCR_TEIE                        ((uint32_t)0x00000008U)        /*!< Transfer error interrupt enable     */
-#define  DMA_CCR_DIR                         ((uint32_t)0x00000010U)        /*!< Data transfer direction             */
-#define  DMA_CCR_CIRC                        ((uint32_t)0x00000020U)        /*!< Circular mode                       */
-#define  DMA_CCR_PINC                        ((uint32_t)0x00000040U)        /*!< Peripheral increment mode           */
-#define  DMA_CCR_MINC                        ((uint32_t)0x00000080U)        /*!< Memory increment mode               */
-
-#define  DMA_CCR_PSIZE                       ((uint32_t)0x00000300U)        /*!< PSIZE[1:0] bits (Peripheral size)   */
-#define  DMA_CCR_PSIZE_0                     ((uint32_t)0x00000100U)        /*!< Bit 0                               */
-#define  DMA_CCR_PSIZE_1                     ((uint32_t)0x00000200U)        /*!< Bit 1                               */
-
-#define  DMA_CCR_MSIZE                       ((uint32_t)0x00000C00U)        /*!< MSIZE[1:0] bits (Memory size)       */
-#define  DMA_CCR_MSIZE_0                     ((uint32_t)0x00000400U)        /*!< Bit 0                               */
-#define  DMA_CCR_MSIZE_1                     ((uint32_t)0x00000800U)        /*!< Bit 1                               */
-
-#define  DMA_CCR_PL                          ((uint32_t)0x00003000U)        /*!< PL[1:0] bits(Channel Priority level)*/
-#define  DMA_CCR_PL_0                        ((uint32_t)0x00001000U)        /*!< Bit 0                               */
-#define  DMA_CCR_PL_1                        ((uint32_t)0x00002000U)        /*!< Bit 1                               */
-
-#define  DMA_CCR_MEM2MEM                     ((uint32_t)0x00004000U)        /*!< Memory to memory mode               */
-
-/******************  Bit definition for DMA_CNDTR register  *******************/
-#define  DMA_CNDTR_NDT                       ((uint32_t)0x0000FFFFU)        /*!< Number of data to Transfer          */
-
-/******************  Bit definition for DMA_CPAR register  ********************/
-#define  DMA_CPAR_PA                         ((uint32_t)0xFFFFFFFFU)        /*!< Peripheral Address                  */
-
-/******************  Bit definition for DMA_CMAR register  ********************/
-#define  DMA_CMAR_MA                         ((uint32_t)0xFFFFFFFFU)        /*!< Memory Address                      */
-
-
-/*******************  Bit definition for DMA_CSELR register  *******************/
-#define  DMA_CSELR_C1S                          ((uint32_t)0x0000000FU)          /*!< Channel 1 Selection */
-#define  DMA_CSELR_C2S                          ((uint32_t)0x000000F0U)          /*!< Channel 2 Selection */
-#define  DMA_CSELR_C3S                          ((uint32_t)0x00000F00U)          /*!< Channel 3 Selection */
-#define  DMA_CSELR_C4S                          ((uint32_t)0x0000F000U)          /*!< Channel 4 Selection */
-#define  DMA_CSELR_C5S                          ((uint32_t)0x000F0000U)          /*!< Channel 5 Selection */
-#define  DMA_CSELR_C6S                          ((uint32_t)0x00F00000U)          /*!< Channel 6 Selection */
-#define  DMA_CSELR_C7S                          ((uint32_t)0x0F000000U)          /*!< Channel 7 Selection */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                    External Interrupt/Event Controller                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for EXTI_IMR1 register  ******************/
-#define  EXTI_IMR1_IM0                       ((uint32_t)0x00000001U)        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR1_IM1                       ((uint32_t)0x00000002U)        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR1_IM2                       ((uint32_t)0x00000004U)        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR1_IM3                       ((uint32_t)0x00000008U)        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR1_IM4                       ((uint32_t)0x00000010U)        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR1_IM5                       ((uint32_t)0x00000020U)        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR1_IM6                       ((uint32_t)0x00000040U)        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR1_IM7                       ((uint32_t)0x00000080U)        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR1_IM8                       ((uint32_t)0x00000100U)        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR1_IM9                       ((uint32_t)0x00000200U)        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR1_IM10                      ((uint32_t)0x00000400U)        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR1_IM11                      ((uint32_t)0x00000800U)        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR1_IM12                      ((uint32_t)0x00001000U)        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR1_IM13                      ((uint32_t)0x00002000U)        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR1_IM14                      ((uint32_t)0x00004000U)        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR1_IM15                      ((uint32_t)0x00008000U)        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR1_IM16                      ((uint32_t)0x00010000U)        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR1_IM17                      ((uint32_t)0x00020000U)        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR1_IM18                      ((uint32_t)0x00040000U)        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR1_IM19                      ((uint32_t)0x00080000U)        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR1_IM20                      ((uint32_t)0x00100000U)        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR1_IM21                      ((uint32_t)0x00200000U)        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR1_IM22                      ((uint32_t)0x00400000U)        /*!< Interrupt Mask on line 22 */
-#define  EXTI_IMR1_IM23                      ((uint32_t)0x00800000U)        /*!< Interrupt Mask on line 23 */
-#define  EXTI_IMR1_IM24                      ((uint32_t)0x01000000U)        /*!< Interrupt Mask on line 24 */
-#define  EXTI_IMR1_IM25                      ((uint32_t)0x02000000U)        /*!< Interrupt Mask on line 25 */
-#define  EXTI_IMR1_IM26                      ((uint32_t)0x04000000U)        /*!< Interrupt Mask on line 26 */
-#define  EXTI_IMR1_IM27                      ((uint32_t)0x08000000U)        /*!< Interrupt Mask on line 27 */
-#define  EXTI_IMR1_IM28                      ((uint32_t)0x10000000U)        /*!< Interrupt Mask on line 28 */
-#define  EXTI_IMR1_IM29                      ((uint32_t)0x20000000U)        /*!< Interrupt Mask on line 29 */
-#define  EXTI_IMR1_IM30                      ((uint32_t)0x40000000U)        /*!< Interrupt Mask on line 30 */
-#define  EXTI_IMR1_IM31                      ((uint32_t)0x80000000U)        /*!< Interrupt Mask on line 31 */
-
-/*******************  Bit definition for EXTI_EMR1 register  ******************/
-#define  EXTI_EMR1_EM0                       ((uint32_t)0x00000001U)        /*!< Event Mask on line 0 */
-#define  EXTI_EMR1_EM1                       ((uint32_t)0x00000002U)        /*!< Event Mask on line 1 */
-#define  EXTI_EMR1_EM2                       ((uint32_t)0x00000004U)        /*!< Event Mask on line 2 */
-#define  EXTI_EMR1_EM3                       ((uint32_t)0x00000008U)        /*!< Event Mask on line 3 */
-#define  EXTI_EMR1_EM4                       ((uint32_t)0x00000010U)        /*!< Event Mask on line 4 */
-#define  EXTI_EMR1_EM5                       ((uint32_t)0x00000020U)        /*!< Event Mask on line 5 */
-#define  EXTI_EMR1_EM6                       ((uint32_t)0x00000040U)        /*!< Event Mask on line 6 */
-#define  EXTI_EMR1_EM7                       ((uint32_t)0x00000080U)        /*!< Event Mask on line 7 */
-#define  EXTI_EMR1_EM8                       ((uint32_t)0x00000100U)        /*!< Event Mask on line 8 */
-#define  EXTI_EMR1_EM9                       ((uint32_t)0x00000200U)        /*!< Event Mask on line 9 */
-#define  EXTI_EMR1_EM10                      ((uint32_t)0x00000400U)        /*!< Event Mask on line 10 */
-#define  EXTI_EMR1_EM11                      ((uint32_t)0x00000800U)        /*!< Event Mask on line 11 */
-#define  EXTI_EMR1_EM12                      ((uint32_t)0x00001000U)        /*!< Event Mask on line 12 */
-#define  EXTI_EMR1_EM13                      ((uint32_t)0x00002000U)        /*!< Event Mask on line 13 */
-#define  EXTI_EMR1_EM14                      ((uint32_t)0x00004000U)        /*!< Event Mask on line 14 */
-#define  EXTI_EMR1_EM15                      ((uint32_t)0x00008000U)        /*!< Event Mask on line 15 */
-#define  EXTI_EMR1_EM16                      ((uint32_t)0x00010000U)        /*!< Event Mask on line 16 */
-#define  EXTI_EMR1_EM17                      ((uint32_t)0x00020000U)        /*!< Event Mask on line 17 */
-#define  EXTI_EMR1_EM18                      ((uint32_t)0x00040000U)        /*!< Event Mask on line 18 */
-#define  EXTI_EMR1_EM19                      ((uint32_t)0x00080000U)        /*!< Event Mask on line 19 */
-#define  EXTI_EMR1_EM20                      ((uint32_t)0x00100000U)        /*!< Event Mask on line 20 */
-#define  EXTI_EMR1_EM21                      ((uint32_t)0x00200000U)        /*!< Event Mask on line 21 */
-#define  EXTI_EMR1_EM22                      ((uint32_t)0x00400000U)        /*!< Event Mask on line 22 */
-#define  EXTI_EMR1_EM23                      ((uint32_t)0x00800000U)        /*!< Event Mask on line 23 */
-#define  EXTI_EMR1_EM24                      ((uint32_t)0x01000000U)        /*!< Event Mask on line 24 */
-#define  EXTI_EMR1_EM25                      ((uint32_t)0x02000000U)        /*!< Event Mask on line 25 */
-#define  EXTI_EMR1_EM26                      ((uint32_t)0x04000000U)        /*!< Event Mask on line 26 */
-#define  EXTI_EMR1_EM27                      ((uint32_t)0x08000000U)        /*!< Event Mask on line 27 */
-#define  EXTI_EMR1_EM28                      ((uint32_t)0x10000000U)        /*!< Event Mask on line 28 */
-#define  EXTI_EMR1_EM29                      ((uint32_t)0x20000000U)        /*!< Event Mask on line 29 */
-#define  EXTI_EMR1_EM30                      ((uint32_t)0x40000000U)        /*!< Event Mask on line 30 */
-#define  EXTI_EMR1_EM31                      ((uint32_t)0x80000000U)        /*!< Event Mask on line 31 */
-
-/******************  Bit definition for EXTI_RTSR1 register  ******************/
-#define  EXTI_RTSR1_RT0                      ((uint32_t)0x00000001U)        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR1_RT1                      ((uint32_t)0x00000002U)        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR1_RT2                      ((uint32_t)0x00000004U)        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR1_RT3                      ((uint32_t)0x00000008U)        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR1_RT4                      ((uint32_t)0x00000010U)        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR1_RT5                      ((uint32_t)0x00000020U)        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR1_RT6                      ((uint32_t)0x00000040U)        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR1_RT7                      ((uint32_t)0x00000080U)        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR1_RT8                      ((uint32_t)0x00000100U)        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR1_RT9                      ((uint32_t)0x00000200U)        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR1_RT10                     ((uint32_t)0x00000400U)        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR1_RT11                     ((uint32_t)0x00000800U)        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR1_RT12                     ((uint32_t)0x00001000U)        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR1_RT13                     ((uint32_t)0x00002000U)        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR1_RT14                     ((uint32_t)0x00004000U)        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR1_RT15                     ((uint32_t)0x00008000U)        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR1_RT16                     ((uint32_t)0x00010000U)        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR1_RT18                     ((uint32_t)0x00040000U)        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR1_RT19                     ((uint32_t)0x00080000U)        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR1_RT20                     ((uint32_t)0x00100000U)        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR1_RT21                     ((uint32_t)0x00200000U)        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR1_RT22                     ((uint32_t)0x00400000U)        /*!< Rising trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_FTSR1 register  ******************/
-#define  EXTI_FTSR1_FT0                      ((uint32_t)0x00000001U)        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR1_FT1                      ((uint32_t)0x00000002U)        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR1_FT2                      ((uint32_t)0x00000004U)        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR1_FT3                      ((uint32_t)0x00000008U)        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR1_FT4                      ((uint32_t)0x00000010U)        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR1_FT5                      ((uint32_t)0x00000020U)        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR1_FT6                      ((uint32_t)0x00000040U)        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR1_FT7                      ((uint32_t)0x00000080U)        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR1_FT8                      ((uint32_t)0x00000100U)        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR1_FT9                      ((uint32_t)0x00000200U)        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR1_FT10                     ((uint32_t)0x00000400U)        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR1_FT11                     ((uint32_t)0x00000800U)        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR1_FT12                     ((uint32_t)0x00001000U)        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR1_FT13                     ((uint32_t)0x00002000U)        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR1_FT14                     ((uint32_t)0x00004000U)        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR1_FT15                     ((uint32_t)0x00008000U)        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR1_FT16                     ((uint32_t)0x00010000U)        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR1_FT18                     ((uint32_t)0x00040000U)        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR1_FT19                     ((uint32_t)0x00080000U)        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR1_FT20                     ((uint32_t)0x00100000U)        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR1_FT21                     ((uint32_t)0x00200000U)        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR1_FT22                     ((uint32_t)0x00400000U)        /*!< Falling trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_SWIER1 register  *****************/
-#define  EXTI_SWIER1_SWI0                    ((uint32_t)0x00000001U)        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER1_SWI1                    ((uint32_t)0x00000002U)        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER1_SWI2                    ((uint32_t)0x00000004U)        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER1_SWI3                    ((uint32_t)0x00000008U)        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER1_SWI4                    ((uint32_t)0x00000010U)        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER1_SWI5                    ((uint32_t)0x00000020U)        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER1_SWI6                    ((uint32_t)0x00000040U)        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER1_SWI7                    ((uint32_t)0x00000080U)        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER1_SWI8                    ((uint32_t)0x00000100U)        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER1_SWI9                    ((uint32_t)0x00000200U)        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER1_SWI10                   ((uint32_t)0x00000400U)        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER1_SWI11                   ((uint32_t)0x00000800U)        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER1_SWI12                   ((uint32_t)0x00001000U)        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER1_SWI13                   ((uint32_t)0x00002000U)        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER1_SWI14                   ((uint32_t)0x00004000U)        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER1_SWI15                   ((uint32_t)0x00008000U)        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER1_SWI16                   ((uint32_t)0x00010000U)        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER1_SWI18                   ((uint32_t)0x00040000U)        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER1_SWI19                   ((uint32_t)0x00080000U)        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER1_SWI20                   ((uint32_t)0x00100000U)        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER1_SWI21                   ((uint32_t)0x00200000U)        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER1_SWI22                   ((uint32_t)0x00400000U)        /*!< Software Interrupt on line 22 */
-
-/*******************  Bit definition for EXTI_PR1 register  *******************/
-#define  EXTI_PR1_PIF0                       ((uint32_t)0x00000001U)        /*!< Pending bit for line 0 */
-#define  EXTI_PR1_PIF1                       ((uint32_t)0x00000002U)        /*!< Pending bit for line 1 */
-#define  EXTI_PR1_PIF2                       ((uint32_t)0x00000004U)        /*!< Pending bit for line 2 */
-#define  EXTI_PR1_PIF3                       ((uint32_t)0x00000008U)        /*!< Pending bit for line 3 */
-#define  EXTI_PR1_PIF4                       ((uint32_t)0x00000010U)        /*!< Pending bit for line 4 */
-#define  EXTI_PR1_PIF5                       ((uint32_t)0x00000020U)        /*!< Pending bit for line 5 */
-#define  EXTI_PR1_PIF6                       ((uint32_t)0x00000040U)        /*!< Pending bit for line 6 */
-#define  EXTI_PR1_PIF7                       ((uint32_t)0x00000080U)        /*!< Pending bit for line 7 */
-#define  EXTI_PR1_PIF8                       ((uint32_t)0x00000100U)        /*!< Pending bit for line 8 */
-#define  EXTI_PR1_PIF9                       ((uint32_t)0x00000200U)        /*!< Pending bit for line 9 */
-#define  EXTI_PR1_PIF10                      ((uint32_t)0x00000400U)        /*!< Pending bit for line 10 */
-#define  EXTI_PR1_PIF11                      ((uint32_t)0x00000800U)        /*!< Pending bit for line 11 */
-#define  EXTI_PR1_PIF12                      ((uint32_t)0x00001000U)        /*!< Pending bit for line 12 */
-#define  EXTI_PR1_PIF13                      ((uint32_t)0x00002000U)        /*!< Pending bit for line 13 */
-#define  EXTI_PR1_PIF14                      ((uint32_t)0x00004000U)        /*!< Pending bit for line 14 */
-#define  EXTI_PR1_PIF15                      ((uint32_t)0x00008000U)        /*!< Pending bit for line 15 */
-#define  EXTI_PR1_PIF16                      ((uint32_t)0x00010000U)        /*!< Pending bit for line 16 */
-#define  EXTI_PR1_PIF18                      ((uint32_t)0x00040000U)        /*!< Pending bit for line 18 */
-#define  EXTI_PR1_PIF19                      ((uint32_t)0x00080000U)        /*!< Pending bit for line 19 */
-#define  EXTI_PR1_PIF20                      ((uint32_t)0x00100000U)        /*!< Pending bit for line 20 */
-#define  EXTI_PR1_PIF21                      ((uint32_t)0x00200000U)        /*!< Pending bit for line 21 */
-#define  EXTI_PR1_PIF22                      ((uint32_t)0x00400000U)        /*!< Pending bit for line 22 */
-
-/*******************  Bit definition for EXTI_IMR2 register  ******************/
-#define  EXTI_IMR2_IM32                      ((uint32_t)0x00000001U)        /*!< Interrupt Mask on line 32 */
-#define  EXTI_IMR2_IM33                      ((uint32_t)0x00000002U)        /*!< Interrupt Mask on line 33 */
-#define  EXTI_IMR2_IM34                      ((uint32_t)0x00000004U)        /*!< Interrupt Mask on line 34 */
-#define  EXTI_IMR2_IM35                      ((uint32_t)0x00000008U)        /*!< Interrupt Mask on line 35 */
-#define  EXTI_IMR2_IM36                      ((uint32_t)0x00000010U)        /*!< Interrupt Mask on line 36 */
-#define  EXTI_IMR2_IM37                      ((uint32_t)0x00000020U)        /*!< Interrupt Mask on line 37 */
-#define  EXTI_IMR2_IM38                      ((uint32_t)0x00000040U)        /*!< Interrupt Mask on line 38 */
-#define  EXTI_IMR2_IM39                      ((uint32_t)0x00000080U)        /*!< Interrupt Mask on line 39 */
-
-/*******************  Bit definition for EXTI_EMR2 register  ******************/
-#define  EXTI_EMR2_EM32                      ((uint32_t)0x00000001U)        /*!< Event Mask on line 32 */
-#define  EXTI_EMR2_EM33                      ((uint32_t)0x00000002U)        /*!< Event Mask on line 33 */
-#define  EXTI_EMR2_EM34                      ((uint32_t)0x00000004U)        /*!< Event Mask on line 34 */
-#define  EXTI_EMR2_EM35                      ((uint32_t)0x00000008U)        /*!< Event Mask on line 35 */
-#define  EXTI_EMR2_EM36                      ((uint32_t)0x00000010U)        /*!< Event Mask on line 36 */
-#define  EXTI_EMR2_EM37                      ((uint32_t)0x00000020U)        /*!< Event Mask on line 37 */
-#define  EXTI_EMR2_EM38                      ((uint32_t)0x00000040U)        /*!< Event Mask on line 38 */
-#define  EXTI_EMR2_EM39                      ((uint32_t)0x00000080U)        /*!< Event Mask on line 39 */
-
-/******************  Bit definition for EXTI_RTSR2 register  ******************/
-#define  EXTI_RTSR2_RT35                     ((uint32_t)0x00000008U)        /*!< Rising trigger event configuration bit of line 35 */
-#define  EXTI_RTSR2_RT36                     ((uint32_t)0x00000010U)        /*!< Rising trigger event configuration bit of line 36 */
-#define  EXTI_RTSR2_RT37                     ((uint32_t)0x00000020U)        /*!< Rising trigger event configuration bit of line 37 */
-#define  EXTI_RTSR2_RT38                     ((uint32_t)0x00000040U)        /*!< Rising trigger event configuration bit of line 38 */
-
-/******************  Bit definition for EXTI_FTSR2 register  ******************/
-#define  EXTI_FTSR2_FT35                     ((uint32_t)0x00000008U)        /*!< Falling trigger event configuration bit of line 35 */
-#define  EXTI_FTSR2_FT36                     ((uint32_t)0x00000010U)        /*!< Falling trigger event configuration bit of line 36 */
-#define  EXTI_FTSR2_FT37                     ((uint32_t)0x00000020U)        /*!< Falling trigger event configuration bit of line 37 */
-#define  EXTI_FTSR2_FT38                     ((uint32_t)0x00000040U)        /*!< Falling trigger event configuration bit of line 38 */
-
-/******************  Bit definition for EXTI_SWIER2 register  *****************/
-#define  EXTI_SWIER2_SWI35                   ((uint32_t)0x00000008U)        /*!< Software Interrupt on line 35 */
-#define  EXTI_SWIER2_SWI36                   ((uint32_t)0x00000010U)        /*!< Software Interrupt on line 36 */
-#define  EXTI_SWIER2_SWI37                   ((uint32_t)0x00000020U)        /*!< Software Interrupt on line 37 */
-#define  EXTI_SWIER2_SWI38                   ((uint32_t)0x00000040U)        /*!< Software Interrupt on line 38 */
-
-/*******************  Bit definition for EXTI_PR2 register  *******************/
-#define  EXTI_PR2_PIF35                       ((uint32_t)0x00000008U)        /*!< Pending bit for line 35 */
-#define  EXTI_PR2_PIF36                       ((uint32_t)0x00000010U)        /*!< Pending bit for line 36 */
-#define  EXTI_PR2_PIF37                       ((uint32_t)0x00000020U)        /*!< Pending bit for line 37 */
-#define  EXTI_PR2_PIF38                       ((uint32_t)0x00000040U)        /*!< Pending bit for line 38 */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    FLASH                                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    ((uint32_t)0x00000007U)
-#define FLASH_ACR_LATENCY_0WS                ((uint32_t)0x00000000U)
-#define FLASH_ACR_LATENCY_1WS                ((uint32_t)0x00000001U)
-#define FLASH_ACR_LATENCY_2WS                ((uint32_t)0x00000002U)
-#define FLASH_ACR_LATENCY_3WS                ((uint32_t)0x00000003U)
-#define FLASH_ACR_LATENCY_4WS                ((uint32_t)0x00000004U)
-#define FLASH_ACR_PRFTEN                     ((uint32_t)0x00000100U)
-#define FLASH_ACR_ICEN                       ((uint32_t)0x00000200U)
-#define FLASH_ACR_DCEN                       ((uint32_t)0x00000400U)
-#define FLASH_ACR_ICRST                      ((uint32_t)0x00000800U)
-#define FLASH_ACR_DCRST                      ((uint32_t)0x00001000U)
-#define FLASH_ACR_RUN_PD                     ((uint32_t)0x00002000U)   /*!< Flash power down mode during run */
-#define FLASH_ACR_SLEEP_PD                   ((uint32_t)0x00004000U)   /*!< Flash power down mode during sleep */
-
-/*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         ((uint32_t)0x00000001U)
-#define FLASH_SR_OPERR                       ((uint32_t)0x00000002U)
-#define FLASH_SR_PROGERR                     ((uint32_t)0x00000008U)
-#define FLASH_SR_WRPERR                      ((uint32_t)0x00000010U)
-#define FLASH_SR_PGAERR                      ((uint32_t)0x00000020U)
-#define FLASH_SR_SIZERR                      ((uint32_t)0x00000040U)
-#define FLASH_SR_PGSERR                      ((uint32_t)0x00000080U)
-#define FLASH_SR_MISERR                      ((uint32_t)0x00000100U)
-#define FLASH_SR_FASTERR                     ((uint32_t)0x00000200U)
-#define FLASH_SR_RDERR                       ((uint32_t)0x00004000U)
-#define FLASH_SR_OPTVERR                     ((uint32_t)0x00008000U)
-#define FLASH_SR_BSY                         ((uint32_t)0x00010000U)
-
-/*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          ((uint32_t)0x00000001U)
-#define FLASH_CR_PER                         ((uint32_t)0x00000002U)
-#define FLASH_CR_MER1                        ((uint32_t)0x00000004U)
-#define FLASH_CR_PNB                         ((uint32_t)0x000007F8U)
-#define FLASH_CR_BKER                        ((uint32_t)0x00000800U)
-#define FLASH_CR_MER2                        ((uint32_t)0x00008000U)
-#define FLASH_CR_STRT                        ((uint32_t)0x00010000U)
-#define FLASH_CR_OPTSTRT                     ((uint32_t)0x00020000U)
-#define FLASH_CR_FSTPG                       ((uint32_t)0x00040000U)
-#define FLASH_CR_EOPIE                       ((uint32_t)0x01000000U)
-#define FLASH_CR_ERRIE                       ((uint32_t)0x02000000U)
-#define FLASH_CR_RDERRIE                     ((uint32_t)0x04000000U)
-#define FLASH_CR_OBL_LAUNCH                  ((uint32_t)0x08000000U)
-#define FLASH_CR_OPTLOCK                     ((uint32_t)0x40000000U)
-#define FLASH_CR_LOCK                        ((uint32_t)0x80000000U)
-
-/*******************  Bits definition for FLASH_ECCR register  ***************/
-#define FLASH_ECCR_ADDR_ECC                 ((uint32_t)0x0007FFFFU)
-#define FLASH_ECCR_BK_ECC                   ((uint32_t)0x00080000U)
-#define FLASH_ECCR_SYSF_ECC                 ((uint32_t)0x00100000U)
-#define FLASH_ECCR_ECCIE                    ((uint32_t)0x01000000U)
-#define FLASH_ECCR_ECCC                     ((uint32_t)0x40000000U)
-#define FLASH_ECCR_ECCD                     ((uint32_t)0x80000000U)
-
-/*******************  Bits definition for FLASH_OPTR register  ***************/
-#define FLASH_OPTR_RDP                      ((uint32_t)0x000000FFU)
-#define FLASH_OPTR_BOR_LEV                  ((uint32_t)0x00000700U)
-#define FLASH_OPTR_BOR_LEV_0                ((uint32_t)0x00000000U)
-#define FLASH_OPTR_BOR_LEV_1                ((uint32_t)0x00000100U)
-#define FLASH_OPTR_BOR_LEV_2                ((uint32_t)0x00000200U)
-#define FLASH_OPTR_BOR_LEV_3                ((uint32_t)0x00000300U)
-#define FLASH_OPTR_BOR_LEV_4                ((uint32_t)0x00000400U)
-#define FLASH_OPTR_nRST_STOP                ((uint32_t)0x00001000U)
-#define FLASH_OPTR_nRST_STDBY               ((uint32_t)0x00002000U)
-#define FLASH_OPTR_nRST_SHDW                ((uint32_t)0x00004000U)
-#define FLASH_OPTR_IWDG_SW                  ((uint32_t)0x00010000U)
-#define FLASH_OPTR_IWDG_STOP                ((uint32_t)0x00020000U)
-#define FLASH_OPTR_IWDG_STDBY               ((uint32_t)0x00040000U)
-#define FLASH_OPTR_WWDG_SW                  ((uint32_t)0x00080000U)
-#define FLASH_OPTR_BFB2                     ((uint32_t)0x00100000U)
-#define FLASH_OPTR_DUALBANK                 ((uint32_t)0x00200000U)
-#define FLASH_OPTR_nBOOT1                   ((uint32_t)0x00800000U)
-#define FLASH_OPTR_SRAM2_PE                 ((uint32_t)0x01000000U)
-#define FLASH_OPTR_SRAM2_RST                ((uint32_t)0x02000000U)
-
-/******************  Bits definition for FLASH_PCROP1SR register  **********/
-#define FLASH_PCROP1SR_PCROP1_STRT          ((uint32_t)0x0000FFFFU)
-
-/******************  Bits definition for FLASH_PCROP1ER register  ***********/
-#define FLASH_PCROP1ER_PCROP1_END           ((uint32_t)0x0000FFFFU)
-#define FLASH_PCROP1ER_PCROP_RDP            ((uint32_t)0x80000000U)
-
-/******************  Bits definition for FLASH_WRP1AR register  ***************/
-#define FLASH_WRP1AR_WRP1A_STRT             ((uint32_t)0x000000FFU)
-#define FLASH_WRP1AR_WRP1A_END              ((uint32_t)0x00FF0000U)
-
-/******************  Bits definition for FLASH_WRPB1R register  ***************/
-#define FLASH_WRP1BR_WRP1B_STRT             ((uint32_t)0x000000FFU)
-#define FLASH_WRP1BR_WRP1B_END              ((uint32_t)0x00FF0000U)
-
-/******************  Bits definition for FLASH_PCROP2SR register  **********/
-#define FLASH_PCROP2SR_PCROP2_STRT          ((uint32_t)0x0000FFFFU)
-
-/******************  Bits definition for FLASH_PCROP2ER register  ***********/
- #define FLASH_PCROP2ER_PCROP2_END          ((uint32_t)0x0000FFFFU)
-
-/******************  Bits definition for FLASH_WRP2AR register  ***************/
-#define FLASH_WRP2AR_WRP2A_STRT             ((uint32_t)0x000000FFU)
-#define FLASH_WRP2AR_WRP2A_END              ((uint32_t)0x00FF0000U)
-
-/******************  Bits definition for FLASH_WRP2BR register  ***************/
-#define FLASH_WRP2BR_WRP2B_STRT             ((uint32_t)0x000000FFU)
-#define FLASH_WRP2BR_WRP2B_END              ((uint32_t)0x00FF0000U)
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Flexible Memory Controller                        */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for FMC_BCR1 register  *******************/
-#define  FMC_BCR1_CCLKEN                    ((uint32_t)0x00100000U)        /*!<Continous clock enable     */
-
-/******************  Bit definition for FMC_BCRx registers (x=1..4)  *********/
-#define  FMC_BCRx_MBKEN                     ((uint32_t)0x00000001U)        /*!<Memory bank enable bit                 */
-#define  FMC_BCRx_MUXEN                     ((uint32_t)0x00000002U)        /*!<Address/data multiplexing enable bit   */
-
-#define  FMC_BCRx_MTYP                      ((uint32_t)0x0000000CU)        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCRx_MTYP_0                    ((uint32_t)0x00000004U)        /*!<Bit 0 */
-#define  FMC_BCRx_MTYP_1                    ((uint32_t)0x00000008U)        /*!<Bit 1 */
-
-#define  FMC_BCRx_MWID                      ((uint32_t)0x00000030U)        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCRx_MWID_0                    ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BCRx_MWID_1                    ((uint32_t)0x00000020U)        /*!<Bit 1 */
-
-#define  FMC_BCRx_FACCEN                    ((uint32_t)0x00000040U)        /*!<Flash access enable        */
-#define  FMC_BCRx_BURSTEN                   ((uint32_t)0x00000100U)        /*!<Burst enable bit           */
-#define  FMC_BCRx_WAITPOL                   ((uint32_t)0x00000200U)        /*!<Wait signal polarity bit   */
-#define  FMC_BCRx_WAITCFG                   ((uint32_t)0x00000800U)        /*!<Wait timing configuration  */
-#define  FMC_BCRx_WREN                      ((uint32_t)0x00001000U)        /*!<Write enable bit           */
-#define  FMC_BCRx_WAITEN                    ((uint32_t)0x00002000U)        /*!<Wait enable bit            */
-#define  FMC_BCRx_EXTMOD                    ((uint32_t)0x00004000U)        /*!<Extended mode enable       */
-#define  FMC_BCRx_ASYNCWAIT                 ((uint32_t)0x00008000U)        /*!<Asynchronous wait          */
-
-#define  FMC_BCRx_CPSIZE                    ((uint32_t)0x00070000U)        /*!<CRAM page size             */
-#define  FMC_BCRx_CPSIZE_0                  ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_BCRx_CPSIZE_1                  ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_BCRx_CPSIZE_2                  ((uint32_t)0x00040000U)        /*!<Bit 1 */
-
-#define  FMC_BCRx_CBURSTRW                  ((uint32_t)0x00080000U)        /*!<Write burst enable         */
-
-/******************  Bit definition for FMC_BTRx registers (x=1..4)  *********/
-#define  FMC_BTRx_ADDSET                    ((uint32_t)0x0000000FU)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTRx_ADDSET_0                  ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_BTRx_ADDSET_1                  ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_BTRx_ADDSET_2                  ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_BTRx_ADDSET_3                  ((uint32_t)0x00000008U)        /*!<Bit 3 */
-
-#define  FMC_BTRx_ADDHLD                    ((uint32_t)0x000000F0U)        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
-#define  FMC_BTRx_ADDHLD_0                  ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BTRx_ADDHLD_1                  ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FMC_BTRx_ADDHLD_2                  ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FMC_BTRx_ADDHLD_3                  ((uint32_t)0x00000080U)        /*!<Bit 3 */
-
-#define  FMC_BTRx_DATAST                    ((uint32_t)0x0000FF00U)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTRx_DATAST_0                  ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_BTRx_DATAST_1                  ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_BTRx_DATAST_2                  ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_BTRx_DATAST_3                  ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_BTRx_DATAST_4                  ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_BTRx_DATAST_5                  ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_BTRx_DATAST_6                  ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_BTRx_DATAST_7                  ((uint32_t)0x00008000U)        /*!<Bit 7 */
-
-#define  FMC_BTRx_BUSTURN                   ((uint32_t)0x000F0000U)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTRx_BUSTURN_0                 ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_BTRx_BUSTURN_1                 ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_BTRx_BUSTURN_2                 ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_BTRx_BUSTURN_3                 ((uint32_t)0x00080000U)        /*!<Bit 3 */
-
-#define  FMC_BTRx_CLKDIV                    ((uint32_t)0x00F00000U)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTRx_CLKDIV_0                  ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  FMC_BTRx_CLKDIV_1                  ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  FMC_BTRx_CLKDIV_2                  ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  FMC_BTRx_CLKDIV_3                  ((uint32_t)0x00800000U)        /*!<Bit 3 */
-
-#define  FMC_BTRx_DATLAT                    ((uint32_t)0x0F000000U)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTRx_DATLAT_0                  ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FMC_BTRx_DATLAT_1                  ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FMC_BTRx_DATLAT_2                  ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FMC_BTRx_DATLAT_3                  ((uint32_t)0x08000000U)        /*!<Bit 3 */
-
-#define  FMC_BTRx_ACCMOD                    ((uint32_t)0x30000000U)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTRx_ACCMOD_0                  ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  FMC_BTRx_ACCMOD_1                  ((uint32_t)0x20000000U)        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/
-#define  FMC_BWTRx_ADDSET                   ((uint32_t)0x0000000FU)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTRx_ADDSET_0                 ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_BWTRx_ADDSET_1                 ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_BWTRx_ADDSET_2                 ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_BWTRx_ADDSET_3                 ((uint32_t)0x00000008U)        /*!<Bit 3 */
-
-#define  FMC_BWTRx_ADDHLD                   ((uint32_t)0x000000F0U)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTRx_ADDHLD_0                 ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BWTRx_ADDHLD_1                 ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FMC_BWTRx_ADDHLD_2                 ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FMC_BWTRx_ADDHLD_3                 ((uint32_t)0x00000080U)        /*!<Bit 3 */
-
-#define  FMC_BWTRx_DATAST                   ((uint32_t)0x0000FF00U)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTRx_DATAST_0                 ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_BWTRx_DATAST_1                 ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_BWTRx_DATAST_2                 ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_BWTRx_DATAST_3                 ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_BWTRx_DATAST_4                 ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_BWTRx_DATAST_5                 ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_BWTRx_DATAST_6                 ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_BWTRx_DATAST_7                 ((uint32_t)0x00008000U)        /*!<Bit 7 */
-
-#define  FMC_BWTRx_ACCMOD                   ((uint32_t)0x30000000U)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTRx_ACCMOD_0                 ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  FMC_BWTRx_ACCMOD_1                 ((uint32_t)0x20000000U)        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_PCR register  ********************/
-#define  FMC_PCR_PWAITEN                    ((uint32_t)0x00000002U)        /*!<Wait feature enable bit                   */
-#define  FMC_PCR_PBKEN                      ((uint32_t)0x00000004U)        /*!<NAND Flash memory bank enable bit */
-#define  FMC_PCR_PTYP                       ((uint32_t)0x00000008U)        /*!<Memory type                               */
-
-#define  FMC_PCR_PWID                       ((uint32_t)0x00000030U)        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FMC_PCR_PWID_0                     ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_PCR_PWID_1                     ((uint32_t)0x00000020U)        /*!<Bit 1 */
-
-#define  FMC_PCR_ECCEN                      ((uint32_t)0x00000040U)        /*!<ECC computation logic enable bit          */
-
-#define  FMC_PCR_TCLR                       ((uint32_t)0x00001E00U)        /*!<TCLR[3:0] bits (CLE to RE delay)          */
-#define  FMC_PCR_TCLR_0                     ((uint32_t)0x00000200U)        /*!<Bit 0 */
-#define  FMC_PCR_TCLR_1                     ((uint32_t)0x00000400U)        /*!<Bit 1 */
-#define  FMC_PCR_TCLR_2                     ((uint32_t)0x00000800U)        /*!<Bit 2 */
-#define  FMC_PCR_TCLR_3                     ((uint32_t)0x00001000U)        /*!<Bit 3 */
-
-#define  FMC_PCR_TAR                        ((uint32_t)0x0001E000U)        /*!<TAR[3:0] bits (ALE to RE delay)           */
-#define  FMC_PCR_TAR_0                      ((uint32_t)0x00002000U)        /*!<Bit 0 */
-#define  FMC_PCR_TAR_1                      ((uint32_t)0x00004000U)        /*!<Bit 1 */
-#define  FMC_PCR_TAR_2                      ((uint32_t)0x00008000U)        /*!<Bit 2 */
-#define  FMC_PCR_TAR_3                      ((uint32_t)0x00010000U)        /*!<Bit 3 */
-
-#define  FMC_PCR_ECCPS                      ((uint32_t)0x000E0000U)        /*!<ECCPS[1:0] bits (ECC page size)           */
-#define  FMC_PCR_ECCPS_0                    ((uint32_t)0x00020000U)        /*!<Bit 0 */
-#define  FMC_PCR_ECCPS_1                    ((uint32_t)0x00040000U)        /*!<Bit 1 */
-#define  FMC_PCR_ECCPS_2                    ((uint32_t)0x00080000U)        /*!<Bit 2 */
-
-/*******************  Bit definition for FMC_SR register  ********************/
-#define  FMC_SR_IRS                         ((uint32_t)0x00000001U)        /*!<Interrupt Rising Edge status                */
-#define  FMC_SR_ILS                         ((uint32_t)0x00000002U)        /*!<Interrupt Level status                      */
-#define  FMC_SR_IFS                         ((uint32_t)0x00000004U)        /*!<Interrupt Falling Edge status               */
-#define  FMC_SR_IREN                        ((uint32_t)0x00000008U)        /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FMC_SR_ILEN                        ((uint32_t)0x00000010U)        /*!<Interrupt Level detection Enable bit        */
-#define  FMC_SR_IFEN                        ((uint32_t)0x00000020U)        /*!<Interrupt Falling Edge detection Enable bit */
-#define  FMC_SR_FEMPT                       ((uint32_t)0x00000040U)        /*!<FIFO empty                                  */
-
-/******************  Bit definition for FMC_PMEM register  ******************/
-#define  FMC_PMEM_MEMSET                    ((uint32_t)0x000000FFU)        /*!<MEMSET[7:0] bits (Common memory setup time) */
-#define  FMC_PMEM_MEMSET_0                  ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_PMEM_MEMSET_1                  ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_PMEM_MEMSET_2                  ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_PMEM_MEMSET_3                  ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  FMC_PMEM_MEMSET_4                  ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  FMC_PMEM_MEMSET_5                  ((uint32_t)0x00000020U)        /*!<Bit 5 */
-#define  FMC_PMEM_MEMSET_6                  ((uint32_t)0x00000040U)        /*!<Bit 6 */
-#define  FMC_PMEM_MEMSET_7                  ((uint32_t)0x00000080U)        /*!<Bit 7 */
-
-#define  FMC_PMEM_MEMWAIT                   ((uint32_t)0x0000FF00U)        /*!<MEMWAIT[7:0] bits (Common memory wait time) */
-#define  FMC_PMEM_MEMWAIT_0                 ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_PMEM_MEMWAIT_1                 ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_PMEM_MEMWAIT_2                 ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_PMEM_MEMWAIT_3                 ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_PMEM_MEMWAIT_4                 ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_PMEM_MEMWAIT_5                 ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_PMEM_MEMWAIT_6                 ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_PMEM_MEMWAIT_7                 ((uint32_t)0x00008000U)        /*!<Bit 7 */
-
-#define  FMC_PMEM_MEMHOLD                   ((uint32_t)0x00FF0000U)        /*!<MEMHOLD[7:0] bits (Common memory hold time) */
-#define  FMC_PMEM_MEMHOLD_0                 ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_PMEM_MEMHOLD_1                 ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_PMEM_MEMHOLD_2                 ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_PMEM_MEMHOLD_3                 ((uint32_t)0x00080000U)        /*!<Bit 3 */
-#define  FMC_PMEM_MEMHOLD_4                 ((uint32_t)0x00100000U)        /*!<Bit 4 */
-#define  FMC_PMEM_MEMHOLD_5                 ((uint32_t)0x00200000U)        /*!<Bit 5 */
-#define  FMC_PMEM_MEMHOLD_6                 ((uint32_t)0x00400000U)        /*!<Bit 6 */
-#define  FMC_PMEM_MEMHOLD_7                 ((uint32_t)0x00800000U)        /*!<Bit 7 */
-
-#define  FMC_PMEM_MEMHIZ                    ((uint32_t)0xFF000000U)        /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */
-#define  FMC_PMEM_MEMHIZ_0                  ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FMC_PMEM_MEMHIZ_1                  ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FMC_PMEM_MEMHIZ_2                  ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FMC_PMEM_MEMHIZ_3                  ((uint32_t)0x08000000U)        /*!<Bit 3 */
-#define  FMC_PMEM_MEMHIZ_4                  ((uint32_t)0x10000000U)        /*!<Bit 4 */
-#define  FMC_PMEM_MEMHIZ_5                  ((uint32_t)0x20000000U)        /*!<Bit 5 */
-#define  FMC_PMEM_MEMHIZ_6                  ((uint32_t)0x40000000U)        /*!<Bit 6 */
-#define  FMC_PMEM_MEMHIZ_7                  ((uint32_t)0x80000000U)        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_PATT register  *******************/
-#define  FMC_PATT_ATTSET                    ((uint32_t)0x000000FFU)        /*!<ATTSET[7:0] bits (Attribute memory setup time) */
-#define  FMC_PATT_ATTSET_0                  ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_PATT_ATTSET_1                  ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_PATT_ATTSET_2                  ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_PATT_ATTSET_3                  ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  FMC_PATT_ATTSET_4                  ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  FMC_PATT_ATTSET_5                  ((uint32_t)0x00000020U)        /*!<Bit 5 */
-#define  FMC_PATT_ATTSET_6                  ((uint32_t)0x00000040U)        /*!<Bit 6 */
-#define  FMC_PATT_ATTSET_7                  ((uint32_t)0x00000080U)        /*!<Bit 7 */
-
-#define  FMC_PATT_ATTWAIT                   ((uint32_t)0x0000FF00U)        /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */
-#define  FMC_PATT_ATTWAIT_0                 ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_PATT_ATTWAIT_1                 ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_PATT_ATTWAIT_2                 ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_PATT_ATTWAIT_3                 ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_PATT_ATTWAIT_4                 ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_PATT_ATTWAIT_5                 ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_PATT_ATTWAIT_6                 ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_PATT_ATTWAIT_7                 ((uint32_t)0x00008000U)        /*!<Bit 7 */
-
-#define  FMC_PATT_ATTHOLD                   ((uint32_t)0x00FF0000U)        /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */
-#define  FMC_PATT_ATTHOLD_0                 ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_PATT_ATTHOLD_1                 ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_PATT_ATTHOLD_2                 ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_PATT_ATTHOLD_3                 ((uint32_t)0x00080000U)        /*!<Bit 3 */
-#define  FMC_PATT_ATTHOLD_4                 ((uint32_t)0x00100000U)        /*!<Bit 4 */
-#define  FMC_PATT_ATTHOLD_5                 ((uint32_t)0x00200000U)        /*!<Bit 5 */
-#define  FMC_PATT_ATTHOLD_6                 ((uint32_t)0x00400000U)        /*!<Bit 6 */
-#define  FMC_PATT_ATTHOLD_7                 ((uint32_t)0x00800000U)        /*!<Bit 7 */
-
-#define  FMC_PATT_ATTHIZ                    ((uint32_t)0xFF000000U)        /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */
-#define  FMC_PATT_ATTHIZ_0                  ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FMC_PATT_ATTHIZ_1                  ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FMC_PATT_ATTHIZ_2                  ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FMC_PATT_ATTHIZ_3                  ((uint32_t)0x08000000U)        /*!<Bit 3 */
-#define  FMC_PATT_ATTHIZ_4                  ((uint32_t)0x10000000U)        /*!<Bit 4 */
-#define  FMC_PATT_ATTHIZ_5                  ((uint32_t)0x20000000U)        /*!<Bit 5 */
-#define  FMC_PATT_ATTHIZ_6                  ((uint32_t)0x40000000U)        /*!<Bit 6 */
-#define  FMC_PATT_ATTHIZ_7                  ((uint32_t)0x80000000U)        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_ECCR register  *******************/
-#define  FMC_ECCR_ECC                       ((uint32_t)0xFFFFFFFFU)        /*!<ECC result */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       General Purpose IOs (GPIO)                           */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODE0                    ((uint32_t)0x00000003U)
-#define GPIO_MODER_MODE0_0                  ((uint32_t)0x00000001U)
-#define GPIO_MODER_MODE0_1                  ((uint32_t)0x00000002U)
-#define GPIO_MODER_MODE1                    ((uint32_t)0x0000000CU)
-#define GPIO_MODER_MODE1_0                  ((uint32_t)0x00000004U)
-#define GPIO_MODER_MODE1_1                  ((uint32_t)0x00000008U)
-#define GPIO_MODER_MODE2                    ((uint32_t)0x00000030U)
-#define GPIO_MODER_MODE2_0                  ((uint32_t)0x00000010U)
-#define GPIO_MODER_MODE2_1                  ((uint32_t)0x00000020U)
-#define GPIO_MODER_MODE3                    ((uint32_t)0x000000C0U)
-#define GPIO_MODER_MODE3_0                  ((uint32_t)0x00000040U)
-#define GPIO_MODER_MODE3_1                  ((uint32_t)0x00000080U)
-#define GPIO_MODER_MODE4                    ((uint32_t)0x00000300U)
-#define GPIO_MODER_MODE4_0                  ((uint32_t)0x00000100U)
-#define GPIO_MODER_MODE4_1                  ((uint32_t)0x00000200U)
-#define GPIO_MODER_MODE5                    ((uint32_t)0x00000C00U)
-#define GPIO_MODER_MODE5_0                  ((uint32_t)0x00000400U)
-#define GPIO_MODER_MODE5_1                  ((uint32_t)0x00000800U)
-#define GPIO_MODER_MODE6                    ((uint32_t)0x00003000U)
-#define GPIO_MODER_MODE6_0                  ((uint32_t)0x00001000U)
-#define GPIO_MODER_MODE6_1                  ((uint32_t)0x00002000U)
-#define GPIO_MODER_MODE7                    ((uint32_t)0x0000C000U)
-#define GPIO_MODER_MODE7_0                  ((uint32_t)0x00004000U)
-#define GPIO_MODER_MODE7_1                  ((uint32_t)0x00008000U)
-#define GPIO_MODER_MODE8                    ((uint32_t)0x00030000U)
-#define GPIO_MODER_MODE8_0                  ((uint32_t)0x00010000U)
-#define GPIO_MODER_MODE8_1                  ((uint32_t)0x00020000U)
-#define GPIO_MODER_MODE9                    ((uint32_t)0x000C0000U)
-#define GPIO_MODER_MODE9_0                  ((uint32_t)0x00040000U)
-#define GPIO_MODER_MODE9_1                  ((uint32_t)0x00080000U)
-#define GPIO_MODER_MODE10                   ((uint32_t)0x00300000U)
-#define GPIO_MODER_MODE10_0                 ((uint32_t)0x00100000U)
-#define GPIO_MODER_MODE10_1                 ((uint32_t)0x00200000U)
-#define GPIO_MODER_MODE11                   ((uint32_t)0x00C00000U)
-#define GPIO_MODER_MODE11_0                 ((uint32_t)0x00400000U)
-#define GPIO_MODER_MODE11_1                 ((uint32_t)0x00800000U)
-#define GPIO_MODER_MODE12                   ((uint32_t)0x03000000U)
-#define GPIO_MODER_MODE12_0                 ((uint32_t)0x01000000U)
-#define GPIO_MODER_MODE12_1                 ((uint32_t)0x02000000U)
-#define GPIO_MODER_MODE13                   ((uint32_t)0x0C000000U)
-#define GPIO_MODER_MODE13_0                 ((uint32_t)0x04000000U)
-#define GPIO_MODER_MODE13_1                 ((uint32_t)0x08000000U)
-#define GPIO_MODER_MODE14                   ((uint32_t)0x30000000U)
-#define GPIO_MODER_MODE14_0                 ((uint32_t)0x10000000U)
-#define GPIO_MODER_MODE14_1                 ((uint32_t)0x20000000U)
-#define GPIO_MODER_MODE15                   ((uint32_t)0xC0000000U)
-#define GPIO_MODER_MODE15_0                 ((uint32_t)0x40000000U)
-#define GPIO_MODER_MODE15_1                 ((uint32_t)0x80000000U)
-
-/* Legacy defines */
-#define GPIO_MODER_MODER0                   GPIO_MODER_MODE0
-#define GPIO_MODER_MODER0_0                 GPIO_MODER_MODE0_0
-#define GPIO_MODER_MODER0_1                 GPIO_MODER_MODE0_1
-#define GPIO_MODER_MODER1                   GPIO_MODER_MODE1
-#define GPIO_MODER_MODER1_0                 GPIO_MODER_MODE1_0
-#define GPIO_MODER_MODER1_1                 GPIO_MODER_MODE1_1
-#define GPIO_MODER_MODER2                   GPIO_MODER_MODE2
-#define GPIO_MODER_MODER2_0                 GPIO_MODER_MODE2_0
-#define GPIO_MODER_MODER2_1                 GPIO_MODER_MODE2_1
-#define GPIO_MODER_MODER3                   GPIO_MODER_MODE3
-#define GPIO_MODER_MODER3_0                 GPIO_MODER_MODE3_0
-#define GPIO_MODER_MODER3_1                 GPIO_MODER_MODE3_1
-#define GPIO_MODER_MODER4                   GPIO_MODER_MODE4
-#define GPIO_MODER_MODER4_0                 GPIO_MODER_MODE4_0
-#define GPIO_MODER_MODER4_1                 GPIO_MODER_MODE4_1
-#define GPIO_MODER_MODER5                   GPIO_MODER_MODE5
-#define GPIO_MODER_MODER5_0                 GPIO_MODER_MODE5_0
-#define GPIO_MODER_MODER5_1                 GPIO_MODER_MODE5_1
-#define GPIO_MODER_MODER6                   GPIO_MODER_MODE6
-#define GPIO_MODER_MODER6_0                 GPIO_MODER_MODE6_0
-#define GPIO_MODER_MODER6_1                 GPIO_MODER_MODE6_1
-#define GPIO_MODER_MODER7                   GPIO_MODER_MODE7
-#define GPIO_MODER_MODER7_0                 GPIO_MODER_MODE7_0
-#define GPIO_MODER_MODER7_1                 GPIO_MODER_MODE7_1
-#define GPIO_MODER_MODER8                   GPIO_MODER_MODE8
-#define GPIO_MODER_MODER8_0                 GPIO_MODER_MODE8_0
-#define GPIO_MODER_MODER8_1                 GPIO_MODER_MODE8_1
-#define GPIO_MODER_MODER9                   GPIO_MODER_MODE9
-#define GPIO_MODER_MODER9_0                 GPIO_MODER_MODE9_0
-#define GPIO_MODER_MODER9_1                 GPIO_MODER_MODE9_1
-#define GPIO_MODER_MODER10                  GPIO_MODER_MODE10
-#define GPIO_MODER_MODER10_0                GPIO_MODER_MODE10_0
-#define GPIO_MODER_MODER10_1                GPIO_MODER_MODE10_1
-#define GPIO_MODER_MODER11                  GPIO_MODER_MODE11
-#define GPIO_MODER_MODER11_0                GPIO_MODER_MODE11_0
-#define GPIO_MODER_MODER11_1                GPIO_MODER_MODE11_1
-#define GPIO_MODER_MODER12                  GPIO_MODER_MODE12
-#define GPIO_MODER_MODER12_0                GPIO_MODER_MODE12_0
-#define GPIO_MODER_MODER12_1                GPIO_MODER_MODE12_1
-#define GPIO_MODER_MODER13                  GPIO_MODER_MODE13
-#define GPIO_MODER_MODER13_0                GPIO_MODER_MODE13_0
-#define GPIO_MODER_MODER13_1                GPIO_MODER_MODE13_1
-#define GPIO_MODER_MODER14                  GPIO_MODER_MODE14
-#define GPIO_MODER_MODER14_0                GPIO_MODER_MODE14_0
-#define GPIO_MODER_MODER14_1                GPIO_MODER_MODE14_1
-#define GPIO_MODER_MODER15                  GPIO_MODER_MODE15
-#define GPIO_MODER_MODER15_0                GPIO_MODER_MODE15_0
-#define GPIO_MODER_MODER15_1                GPIO_MODER_MODE15_1
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT0                     ((uint32_t)0x00000001U)
-#define GPIO_OTYPER_OT1                     ((uint32_t)0x00000002U)
-#define GPIO_OTYPER_OT2                     ((uint32_t)0x00000004U)
-#define GPIO_OTYPER_OT3                     ((uint32_t)0x00000008U)
-#define GPIO_OTYPER_OT4                     ((uint32_t)0x00000010U)
-#define GPIO_OTYPER_OT5                     ((uint32_t)0x00000020U)
-#define GPIO_OTYPER_OT6                     ((uint32_t)0x00000040U)
-#define GPIO_OTYPER_OT7                     ((uint32_t)0x00000080U)
-#define GPIO_OTYPER_OT8                     ((uint32_t)0x00000100U)
-#define GPIO_OTYPER_OT9                     ((uint32_t)0x00000200U)
-#define GPIO_OTYPER_OT10                    ((uint32_t)0x00000400U)
-#define GPIO_OTYPER_OT11                    ((uint32_t)0x00000800U)
-#define GPIO_OTYPER_OT12                    ((uint32_t)0x00001000U)
-#define GPIO_OTYPER_OT13                    ((uint32_t)0x00002000U)
-#define GPIO_OTYPER_OT14                    ((uint32_t)0x00004000U)
-#define GPIO_OTYPER_OT15                    ((uint32_t)0x00008000U)
-
-/* Legacy defines */
-#define GPIO_OTYPER_OT_0                    GPIO_OTYPER_OT0
-#define GPIO_OTYPER_OT_1                    GPIO_OTYPER_OT1
-#define GPIO_OTYPER_OT_2                    GPIO_OTYPER_OT2
-#define GPIO_OTYPER_OT_3                    GPIO_OTYPER_OT3
-#define GPIO_OTYPER_OT_4                    GPIO_OTYPER_OT4
-#define GPIO_OTYPER_OT_5                    GPIO_OTYPER_OT5
-#define GPIO_OTYPER_OT_6                    GPIO_OTYPER_OT6
-#define GPIO_OTYPER_OT_7                    GPIO_OTYPER_OT7
-#define GPIO_OTYPER_OT_8                    GPIO_OTYPER_OT8
-#define GPIO_OTYPER_OT_9                    GPIO_OTYPER_OT9
-#define GPIO_OTYPER_OT_10                   GPIO_OTYPER_OT10
-#define GPIO_OTYPER_OT_11                   GPIO_OTYPER_OT11
-#define GPIO_OTYPER_OT_12                   GPIO_OTYPER_OT12
-#define GPIO_OTYPER_OT_13                   GPIO_OTYPER_OT13
-#define GPIO_OTYPER_OT_14                   GPIO_OTYPER_OT14
-#define GPIO_OTYPER_OT_15                   GPIO_OTYPER_OT15
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDR_OSPEED0                ((uint32_t)0x00000003U)
-#define GPIO_OSPEEDR_OSPEED0_0              ((uint32_t)0x00000001U)
-#define GPIO_OSPEEDR_OSPEED0_1              ((uint32_t)0x00000002U)
-#define GPIO_OSPEEDR_OSPEED1                ((uint32_t)0x0000000CU)
-#define GPIO_OSPEEDR_OSPEED1_0              ((uint32_t)0x00000004U)
-#define GPIO_OSPEEDR_OSPEED1_1              ((uint32_t)0x00000008U)
-#define GPIO_OSPEEDR_OSPEED2                ((uint32_t)0x00000030U)
-#define GPIO_OSPEEDR_OSPEED2_0              ((uint32_t)0x00000010U)
-#define GPIO_OSPEEDR_OSPEED2_1              ((uint32_t)0x00000020U)
-#define GPIO_OSPEEDR_OSPEED3                ((uint32_t)0x000000C0U)
-#define GPIO_OSPEEDR_OSPEED3_0              ((uint32_t)0x00000040U)
-#define GPIO_OSPEEDR_OSPEED3_1              ((uint32_t)0x00000080U)
-#define GPIO_OSPEEDR_OSPEED4                ((uint32_t)0x00000300U)
-#define GPIO_OSPEEDR_OSPEED4_0              ((uint32_t)0x00000100U)
-#define GPIO_OSPEEDR_OSPEED4_1              ((uint32_t)0x00000200U)
-#define GPIO_OSPEEDR_OSPEED5                ((uint32_t)0x00000C00U)
-#define GPIO_OSPEEDR_OSPEED5_0              ((uint32_t)0x00000400U)
-#define GPIO_OSPEEDR_OSPEED5_1              ((uint32_t)0x00000800U)
-#define GPIO_OSPEEDR_OSPEED6                ((uint32_t)0x00003000U)
-#define GPIO_OSPEEDR_OSPEED6_0              ((uint32_t)0x00001000U)
-#define GPIO_OSPEEDR_OSPEED6_1              ((uint32_t)0x00002000U)
-#define GPIO_OSPEEDR_OSPEED7                ((uint32_t)0x0000C000U)
-#define GPIO_OSPEEDR_OSPEED7_0              ((uint32_t)0x00004000U)
-#define GPIO_OSPEEDR_OSPEED7_1              ((uint32_t)0x00008000U)
-#define GPIO_OSPEEDR_OSPEED8                ((uint32_t)0x00030000U)
-#define GPIO_OSPEEDR_OSPEED8_0              ((uint32_t)0x00010000U)
-#define GPIO_OSPEEDR_OSPEED8_1              ((uint32_t)0x00020000U)
-#define GPIO_OSPEEDR_OSPEED9                ((uint32_t)0x000C0000U)
-#define GPIO_OSPEEDR_OSPEED9_0              ((uint32_t)0x00040000U)
-#define GPIO_OSPEEDR_OSPEED9_1              ((uint32_t)0x00080000U)
-#define GPIO_OSPEEDR_OSPEED10               ((uint32_t)0x00300000U)
-#define GPIO_OSPEEDR_OSPEED10_0             ((uint32_t)0x00100000U)
-#define GPIO_OSPEEDR_OSPEED10_1             ((uint32_t)0x00200000U)
-#define GPIO_OSPEEDR_OSPEED11               ((uint32_t)0x00C00000U)
-#define GPIO_OSPEEDR_OSPEED11_0             ((uint32_t)0x00400000U)
-#define GPIO_OSPEEDR_OSPEED11_1             ((uint32_t)0x00800000U)
-#define GPIO_OSPEEDR_OSPEED12               ((uint32_t)0x03000000U)
-#define GPIO_OSPEEDR_OSPEED12_0             ((uint32_t)0x01000000U)
-#define GPIO_OSPEEDR_OSPEED12_1             ((uint32_t)0x02000000U)
-#define GPIO_OSPEEDR_OSPEED13               ((uint32_t)0x0C000000U)
-#define GPIO_OSPEEDR_OSPEED13_0             ((uint32_t)0x04000000U)
-#define GPIO_OSPEEDR_OSPEED13_1             ((uint32_t)0x08000000U)
-#define GPIO_OSPEEDR_OSPEED14               ((uint32_t)0x30000000U)
-#define GPIO_OSPEEDR_OSPEED14_0             ((uint32_t)0x10000000U)
-#define GPIO_OSPEEDR_OSPEED14_1             ((uint32_t)0x20000000U)
-#define GPIO_OSPEEDR_OSPEED15               ((uint32_t)0xC0000000U)
-#define GPIO_OSPEEDR_OSPEED15_0             ((uint32_t)0x40000000U)
-#define GPIO_OSPEEDR_OSPEED15_1             ((uint32_t)0x80000000U)
-
-/* Legacy defines */
-#define GPIO_OSPEEDER_OSPEEDR0              GPIO_OSPEEDR_OSPEED0
-#define GPIO_OSPEEDER_OSPEEDR0_0            GPIO_OSPEEDR_OSPEED0_0
-#define GPIO_OSPEEDER_OSPEEDR0_1            GPIO_OSPEEDR_OSPEED0_1
-#define GPIO_OSPEEDER_OSPEEDR1              GPIO_OSPEEDR_OSPEED1
-#define GPIO_OSPEEDER_OSPEEDR1_0            GPIO_OSPEEDR_OSPEED1_0
-#define GPIO_OSPEEDER_OSPEEDR1_1            GPIO_OSPEEDR_OSPEED1_1
-#define GPIO_OSPEEDER_OSPEEDR2              GPIO_OSPEEDR_OSPEED2
-#define GPIO_OSPEEDER_OSPEEDR2_0            GPIO_OSPEEDR_OSPEED2_0
-#define GPIO_OSPEEDER_OSPEEDR2_1            GPIO_OSPEEDR_OSPEED2_1
-#define GPIO_OSPEEDER_OSPEEDR3              GPIO_OSPEEDR_OSPEED3
-#define GPIO_OSPEEDER_OSPEEDR3_0            GPIO_OSPEEDR_OSPEED3_0
-#define GPIO_OSPEEDER_OSPEEDR3_1            GPIO_OSPEEDR_OSPEED3_1
-#define GPIO_OSPEEDER_OSPEEDR4              GPIO_OSPEEDR_OSPEED4
-#define GPIO_OSPEEDER_OSPEEDR4_0            GPIO_OSPEEDR_OSPEED4_0
-#define GPIO_OSPEEDER_OSPEEDR4_1            GPIO_OSPEEDR_OSPEED4_1
-#define GPIO_OSPEEDER_OSPEEDR5              GPIO_OSPEEDR_OSPEED5
-#define GPIO_OSPEEDER_OSPEEDR5_0            GPIO_OSPEEDR_OSPEED5_0
-#define GPIO_OSPEEDER_OSPEEDR5_1            GPIO_OSPEEDR_OSPEED5_1
-#define GPIO_OSPEEDER_OSPEEDR6              GPIO_OSPEEDR_OSPEED6
-#define GPIO_OSPEEDER_OSPEEDR6_0            GPIO_OSPEEDR_OSPEED6_0
-#define GPIO_OSPEEDER_OSPEEDR6_1            GPIO_OSPEEDR_OSPEED6_1
-#define GPIO_OSPEEDER_OSPEEDR7              GPIO_OSPEEDR_OSPEED7
-#define GPIO_OSPEEDER_OSPEEDR7_0            GPIO_OSPEEDR_OSPEED7_0
-#define GPIO_OSPEEDER_OSPEEDR7_1            GPIO_OSPEEDR_OSPEED7_1
-#define GPIO_OSPEEDER_OSPEEDR8              GPIO_OSPEEDR_OSPEED8
-#define GPIO_OSPEEDER_OSPEEDR8_0            GPIO_OSPEEDR_OSPEED8_0
-#define GPIO_OSPEEDER_OSPEEDR8_1            GPIO_OSPEEDR_OSPEED8_1
-#define GPIO_OSPEEDER_OSPEEDR9              GPIO_OSPEEDR_OSPEED9
-#define GPIO_OSPEEDER_OSPEEDR9_0            GPIO_OSPEEDR_OSPEED9_0
-#define GPIO_OSPEEDER_OSPEEDR9_1            GPIO_OSPEEDR_OSPEED9_1
-#define GPIO_OSPEEDER_OSPEEDR10             GPIO_OSPEEDR_OSPEED10
-#define GPIO_OSPEEDER_OSPEEDR10_0           GPIO_OSPEEDR_OSPEED10_0
-#define GPIO_OSPEEDER_OSPEEDR10_1           GPIO_OSPEEDR_OSPEED10_1
-#define GPIO_OSPEEDER_OSPEEDR11             GPIO_OSPEEDR_OSPEED11
-#define GPIO_OSPEEDER_OSPEEDR11_0           GPIO_OSPEEDR_OSPEED11_0
-#define GPIO_OSPEEDER_OSPEEDR11_1           GPIO_OSPEEDR_OSPEED11_1
-#define GPIO_OSPEEDER_OSPEEDR12             GPIO_OSPEEDR_OSPEED12
-#define GPIO_OSPEEDER_OSPEEDR12_0           GPIO_OSPEEDR_OSPEED12_0
-#define GPIO_OSPEEDER_OSPEEDR12_1           GPIO_OSPEEDR_OSPEED12_1
-#define GPIO_OSPEEDER_OSPEEDR13             GPIO_OSPEEDR_OSPEED13
-#define GPIO_OSPEEDER_OSPEEDR13_0           GPIO_OSPEEDR_OSPEED13_0
-#define GPIO_OSPEEDER_OSPEEDR13_1           GPIO_OSPEEDR_OSPEED13_1
-#define GPIO_OSPEEDER_OSPEEDR14             GPIO_OSPEEDR_OSPEED14
-#define GPIO_OSPEEDER_OSPEEDR14_0           GPIO_OSPEEDR_OSPEED14_0
-#define GPIO_OSPEEDER_OSPEEDR14_1           GPIO_OSPEEDR_OSPEED14_1
-#define GPIO_OSPEEDER_OSPEEDR15             GPIO_OSPEEDR_OSPEED15
-#define GPIO_OSPEEDER_OSPEEDR15_0           GPIO_OSPEEDR_OSPEED15_0
-#define GPIO_OSPEEDER_OSPEEDR15_1           GPIO_OSPEEDR_OSPEED15_1
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPD0                    ((uint32_t)0x00000003U)
-#define GPIO_PUPDR_PUPD0_0                  ((uint32_t)0x00000001U)
-#define GPIO_PUPDR_PUPD0_1                  ((uint32_t)0x00000002U)
-#define GPIO_PUPDR_PUPD1                    ((uint32_t)0x0000000CU)
-#define GPIO_PUPDR_PUPD1_0                  ((uint32_t)0x00000004U)
-#define GPIO_PUPDR_PUPD1_1                  ((uint32_t)0x00000008U)
-#define GPIO_PUPDR_PUPD2                    ((uint32_t)0x00000030U)
-#define GPIO_PUPDR_PUPD2_0                  ((uint32_t)0x00000010U)
-#define GPIO_PUPDR_PUPD2_1                  ((uint32_t)0x00000020U)
-#define GPIO_PUPDR_PUPD3                    ((uint32_t)0x000000C0U)
-#define GPIO_PUPDR_PUPD3_0                  ((uint32_t)0x00000040U)
-#define GPIO_PUPDR_PUPD3_1                  ((uint32_t)0x00000080U)
-#define GPIO_PUPDR_PUPD4                    ((uint32_t)0x00000300U)
-#define GPIO_PUPDR_PUPD4_0                  ((uint32_t)0x00000100U)
-#define GPIO_PUPDR_PUPD4_1                  ((uint32_t)0x00000200U)
-#define GPIO_PUPDR_PUPD5                    ((uint32_t)0x00000C00U)
-#define GPIO_PUPDR_PUPD5_0                  ((uint32_t)0x00000400U)
-#define GPIO_PUPDR_PUPD5_1                  ((uint32_t)0x00000800U)
-#define GPIO_PUPDR_PUPD6                    ((uint32_t)0x00003000U)
-#define GPIO_PUPDR_PUPD6_0                  ((uint32_t)0x00001000U)
-#define GPIO_PUPDR_PUPD6_1                  ((uint32_t)0x00002000U)
-#define GPIO_PUPDR_PUPD7                    ((uint32_t)0x0000C000U)
-#define GPIO_PUPDR_PUPD7_0                  ((uint32_t)0x00004000U)
-#define GPIO_PUPDR_PUPD7_1                  ((uint32_t)0x00008000U)
-#define GPIO_PUPDR_PUPD8                    ((uint32_t)0x00030000U)
-#define GPIO_PUPDR_PUPD8_0                  ((uint32_t)0x00010000U)
-#define GPIO_PUPDR_PUPD8_1                  ((uint32_t)0x00020000U)
-#define GPIO_PUPDR_PUPD9                    ((uint32_t)0x000C0000U)
-#define GPIO_PUPDR_PUPD9_0                  ((uint32_t)0x00040000U)
-#define GPIO_PUPDR_PUPD9_1                  ((uint32_t)0x00080000U)
-#define GPIO_PUPDR_PUPD10                   ((uint32_t)0x00300000U)
-#define GPIO_PUPDR_PUPD10_0                 ((uint32_t)0x00100000U)
-#define GPIO_PUPDR_PUPD10_1                 ((uint32_t)0x00200000U)
-#define GPIO_PUPDR_PUPD11                   ((uint32_t)0x00C00000U)
-#define GPIO_PUPDR_PUPD11_0                 ((uint32_t)0x00400000U)
-#define GPIO_PUPDR_PUPD11_1                 ((uint32_t)0x00800000U)
-#define GPIO_PUPDR_PUPD12                   ((uint32_t)0x03000000U)
-#define GPIO_PUPDR_PUPD12_0                 ((uint32_t)0x01000000U)
-#define GPIO_PUPDR_PUPD12_1                 ((uint32_t)0x02000000U)
-#define GPIO_PUPDR_PUPD13                   ((uint32_t)0x0C000000U)
-#define GPIO_PUPDR_PUPD13_0                 ((uint32_t)0x04000000U)
-#define GPIO_PUPDR_PUPD13_1                 ((uint32_t)0x08000000U)
-#define GPIO_PUPDR_PUPD14                   ((uint32_t)0x30000000U)
-#define GPIO_PUPDR_PUPD14_0                 ((uint32_t)0x10000000U)
-#define GPIO_PUPDR_PUPD14_1                 ((uint32_t)0x20000000U)
-#define GPIO_PUPDR_PUPD15                   ((uint32_t)0xC0000000U)
-#define GPIO_PUPDR_PUPD15_0                 ((uint32_t)0x40000000U)
-#define GPIO_PUPDR_PUPD15_1                 ((uint32_t)0x80000000U)
-
-/* Legacy defines */
-#define GPIO_PUPDR_PUPDR0                   GPIO_PUPDR_PUPD0
-#define GPIO_PUPDR_PUPDR0_0                 GPIO_PUPDR_PUPD0_0
-#define GPIO_PUPDR_PUPDR0_1                 GPIO_PUPDR_PUPD0_1
-#define GPIO_PUPDR_PUPDR1                   GPIO_PUPDR_PUPD1
-#define GPIO_PUPDR_PUPDR1_0                 GPIO_PUPDR_PUPD1_0
-#define GPIO_PUPDR_PUPDR1_1                 GPIO_PUPDR_PUPD1_1
-#define GPIO_PUPDR_PUPDR2                   GPIO_PUPDR_PUPD2
-#define GPIO_PUPDR_PUPDR2_0                 GPIO_PUPDR_PUPD2_0
-#define GPIO_PUPDR_PUPDR2_1                 GPIO_PUPDR_PUPD2_1
-#define GPIO_PUPDR_PUPDR3                   GPIO_PUPDR_PUPD3
-#define GPIO_PUPDR_PUPDR3_0                 GPIO_PUPDR_PUPD3_0
-#define GPIO_PUPDR_PUPDR3_1                 GPIO_PUPDR_PUPD3_1
-#define GPIO_PUPDR_PUPDR4                   GPIO_PUPDR_PUPD4
-#define GPIO_PUPDR_PUPDR4_0                 GPIO_PUPDR_PUPD4_0
-#define GPIO_PUPDR_PUPDR4_1                 GPIO_PUPDR_PUPD4_1
-#define GPIO_PUPDR_PUPDR5                   GPIO_PUPDR_PUPD5
-#define GPIO_PUPDR_PUPDR5_0                 GPIO_PUPDR_PUPD5_0
-#define GPIO_PUPDR_PUPDR5_1                 GPIO_PUPDR_PUPD5_1
-#define GPIO_PUPDR_PUPDR6                   GPIO_PUPDR_PUPD6
-#define GPIO_PUPDR_PUPDR6_0                 GPIO_PUPDR_PUPD6_0
-#define GPIO_PUPDR_PUPDR6_1                 GPIO_PUPDR_PUPD6_1
-#define GPIO_PUPDR_PUPDR7                   GPIO_PUPDR_PUPD7
-#define GPIO_PUPDR_PUPDR7_0                 GPIO_PUPDR_PUPD7_0
-#define GPIO_PUPDR_PUPDR7_1                 GPIO_PUPDR_PUPD7_1
-#define GPIO_PUPDR_PUPDR8                   GPIO_PUPDR_PUPD8
-#define GPIO_PUPDR_PUPDR8_0                 GPIO_PUPDR_PUPD8_0
-#define GPIO_PUPDR_PUPDR8_1                 GPIO_PUPDR_PUPD8_1
-#define GPIO_PUPDR_PUPDR9                   GPIO_PUPDR_PUPD9
-#define GPIO_PUPDR_PUPDR9_0                 GPIO_PUPDR_PUPD9_0
-#define GPIO_PUPDR_PUPDR9_1                 GPIO_PUPDR_PUPD9_1
-#define GPIO_PUPDR_PUPDR10                  GPIO_PUPDR_PUPD10
-#define GPIO_PUPDR_PUPDR10_0                GPIO_PUPDR_PUPD10_0
-#define GPIO_PUPDR_PUPDR10_1                GPIO_PUPDR_PUPD10_1
-#define GPIO_PUPDR_PUPDR11                  GPIO_PUPDR_PUPD11
-#define GPIO_PUPDR_PUPDR11_0                GPIO_PUPDR_PUPD11_0
-#define GPIO_PUPDR_PUPDR11_1                GPIO_PUPDR_PUPD11_1
-#define GPIO_PUPDR_PUPDR12                  GPIO_PUPDR_PUPD12
-#define GPIO_PUPDR_PUPDR12_0                GPIO_PUPDR_PUPD12_0
-#define GPIO_PUPDR_PUPDR12_1                GPIO_PUPDR_PUPD12_1
-#define GPIO_PUPDR_PUPDR13                  GPIO_PUPDR_PUPD13
-#define GPIO_PUPDR_PUPDR13_0                GPIO_PUPDR_PUPD13_0
-#define GPIO_PUPDR_PUPDR13_1                GPIO_PUPDR_PUPD13_1
-#define GPIO_PUPDR_PUPDR14                  GPIO_PUPDR_PUPD14
-#define GPIO_PUPDR_PUPDR14_0                GPIO_PUPDR_PUPD14_0
-#define GPIO_PUPDR_PUPDR14_1                GPIO_PUPDR_PUPD14_1
-#define GPIO_PUPDR_PUPDR15                  GPIO_PUPDR_PUPD15
-#define GPIO_PUPDR_PUPDR15_0                GPIO_PUPDR_PUPD15_0
-#define GPIO_PUPDR_PUPDR15_1                GPIO_PUPDR_PUPD15_1
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_ID0                        ((uint32_t)0x00000001U)
-#define GPIO_IDR_ID1                        ((uint32_t)0x00000002U)
-#define GPIO_IDR_ID2                        ((uint32_t)0x00000004U)
-#define GPIO_IDR_ID3                        ((uint32_t)0x00000008U)
-#define GPIO_IDR_ID4                        ((uint32_t)0x00000010U)
-#define GPIO_IDR_ID5                        ((uint32_t)0x00000020U)
-#define GPIO_IDR_ID6                        ((uint32_t)0x00000040U)
-#define GPIO_IDR_ID7                        ((uint32_t)0x00000080U)
-#define GPIO_IDR_ID8                        ((uint32_t)0x00000100U)
-#define GPIO_IDR_ID9                        ((uint32_t)0x00000200U)
-#define GPIO_IDR_ID10                       ((uint32_t)0x00000400U)
-#define GPIO_IDR_ID11                       ((uint32_t)0x00000800U)
-#define GPIO_IDR_ID12                       ((uint32_t)0x00001000U)
-#define GPIO_IDR_ID13                       ((uint32_t)0x00002000U)
-#define GPIO_IDR_ID14                       ((uint32_t)0x00004000U)
-#define GPIO_IDR_ID15                       ((uint32_t)0x00008000U)
-
-/* Legacy defines */
-#define GPIO_IDR_IDR_0                      GPIO_IDR_ID0
-#define GPIO_IDR_IDR_1                      GPIO_IDR_ID1
-#define GPIO_IDR_IDR_2                      GPIO_IDR_ID2
-#define GPIO_IDR_IDR_3                      GPIO_IDR_ID3
-#define GPIO_IDR_IDR_4                      GPIO_IDR_ID4
-#define GPIO_IDR_IDR_5                      GPIO_IDR_ID5
-#define GPIO_IDR_IDR_6                      GPIO_IDR_ID6
-#define GPIO_IDR_IDR_7                      GPIO_IDR_ID7
-#define GPIO_IDR_IDR_8                      GPIO_IDR_ID8
-#define GPIO_IDR_IDR_9                      GPIO_IDR_ID9
-#define GPIO_IDR_IDR_10                     GPIO_IDR_ID10
-#define GPIO_IDR_IDR_11                     GPIO_IDR_ID11
-#define GPIO_IDR_IDR_12                     GPIO_IDR_ID12
-#define GPIO_IDR_IDR_13                     GPIO_IDR_ID13
-#define GPIO_IDR_IDR_14                     GPIO_IDR_ID14
-#define GPIO_IDR_IDR_15                     GPIO_IDR_ID15
-
-/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
-#define GPIO_OTYPER_IDR_0                   GPIO_IDR_ID0
-#define GPIO_OTYPER_IDR_1                   GPIO_IDR_ID1
-#define GPIO_OTYPER_IDR_2                   GPIO_IDR_ID2
-#define GPIO_OTYPER_IDR_3                   GPIO_IDR_ID3
-#define GPIO_OTYPER_IDR_4                   GPIO_IDR_ID4
-#define GPIO_OTYPER_IDR_5                   GPIO_IDR_ID5
-#define GPIO_OTYPER_IDR_6                   GPIO_IDR_ID6
-#define GPIO_OTYPER_IDR_7                   GPIO_IDR_ID7
-#define GPIO_OTYPER_IDR_8                   GPIO_IDR_ID8
-#define GPIO_OTYPER_IDR_9                   GPIO_IDR_ID9
-#define GPIO_OTYPER_IDR_10                  GPIO_IDR_ID10
-#define GPIO_OTYPER_IDR_11                  GPIO_IDR_ID11
-#define GPIO_OTYPER_IDR_12                  GPIO_IDR_ID12
-#define GPIO_OTYPER_IDR_13                  GPIO_IDR_ID13
-#define GPIO_OTYPER_IDR_14                  GPIO_IDR_ID14
-#define GPIO_OTYPER_IDR_15                  GPIO_IDR_ID15
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_OD0                        ((uint32_t)0x00000001U)
-#define GPIO_ODR_OD1                        ((uint32_t)0x00000002U)
-#define GPIO_ODR_OD2                        ((uint32_t)0x00000004U)
-#define GPIO_ODR_OD3                        ((uint32_t)0x00000008U)
-#define GPIO_ODR_OD4                        ((uint32_t)0x00000010U)
-#define GPIO_ODR_OD5                        ((uint32_t)0x00000020U)
-#define GPIO_ODR_OD6                        ((uint32_t)0x00000040U)
-#define GPIO_ODR_OD7                        ((uint32_t)0x00000080U)
-#define GPIO_ODR_OD8                        ((uint32_t)0x00000100U)
-#define GPIO_ODR_OD9                        ((uint32_t)0x00000200U)
-#define GPIO_ODR_OD10                       ((uint32_t)0x00000400U)
-#define GPIO_ODR_OD11                       ((uint32_t)0x00000800U)
-#define GPIO_ODR_OD12                       ((uint32_t)0x00001000U)
-#define GPIO_ODR_OD13                       ((uint32_t)0x00002000U)
-#define GPIO_ODR_OD14                       ((uint32_t)0x00004000U)
-#define GPIO_ODR_OD15                       ((uint32_t)0x00008000U)
-
-/* Legacy defines */
-#define GPIO_ODR_ODR_0                      GPIO_ODR_OD0
-#define GPIO_ODR_ODR_1                      GPIO_ODR_OD1
-#define GPIO_ODR_ODR_2                      GPIO_ODR_OD2
-#define GPIO_ODR_ODR_3                      GPIO_ODR_OD3
-#define GPIO_ODR_ODR_4                      GPIO_ODR_OD4
-#define GPIO_ODR_ODR_5                      GPIO_ODR_OD5
-#define GPIO_ODR_ODR_6                      GPIO_ODR_OD6
-#define GPIO_ODR_ODR_7                      GPIO_ODR_OD7
-#define GPIO_ODR_ODR_8                      GPIO_ODR_OD8
-#define GPIO_ODR_ODR_9                      GPIO_ODR_OD9
-#define GPIO_ODR_ODR_10                     GPIO_ODR_OD10
-#define GPIO_ODR_ODR_11                     GPIO_ODR_OD11
-#define GPIO_ODR_ODR_12                     GPIO_ODR_OD12
-#define GPIO_ODR_ODR_13                     GPIO_ODR_OD13
-#define GPIO_ODR_ODR_14                     GPIO_ODR_OD14
-#define GPIO_ODR_ODR_15                     GPIO_ODR_OD15
-
-/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
-#define GPIO_OTYPER_ODR_0                   GPIO_ODR_OD0
-#define GPIO_OTYPER_ODR_1                   GPIO_ODR_OD1
-#define GPIO_OTYPER_ODR_2                   GPIO_ODR_OD2
-#define GPIO_OTYPER_ODR_3                   GPIO_ODR_OD3
-#define GPIO_OTYPER_ODR_4                   GPIO_ODR_OD4
-#define GPIO_OTYPER_ODR_5                   GPIO_ODR_OD5
-#define GPIO_OTYPER_ODR_6                   GPIO_ODR_OD6
-#define GPIO_OTYPER_ODR_7                   GPIO_ODR_OD7
-#define GPIO_OTYPER_ODR_8                   GPIO_ODR_OD8
-#define GPIO_OTYPER_ODR_9                   GPIO_ODR_OD9
-#define GPIO_OTYPER_ODR_10                  GPIO_ODR_OD10
-#define GPIO_OTYPER_ODR_11                  GPIO_ODR_OD11
-#define GPIO_OTYPER_ODR_12                  GPIO_ODR_OD12
-#define GPIO_OTYPER_ODR_13                  GPIO_ODR_OD13
-#define GPIO_OTYPER_ODR_14                  GPIO_ODR_OD14
-#define GPIO_OTYPER_ODR_15                  GPIO_ODR_OD15
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS0                       ((uint32_t)0x00000001U)
-#define GPIO_BSRR_BS1                       ((uint32_t)0x00000002U)
-#define GPIO_BSRR_BS2                       ((uint32_t)0x00000004U)
-#define GPIO_BSRR_BS3                       ((uint32_t)0x00000008U)
-#define GPIO_BSRR_BS4                       ((uint32_t)0x00000010U)
-#define GPIO_BSRR_BS5                       ((uint32_t)0x00000020U)
-#define GPIO_BSRR_BS6                       ((uint32_t)0x00000040U)
-#define GPIO_BSRR_BS7                       ((uint32_t)0x00000080U)
-#define GPIO_BSRR_BS8                       ((uint32_t)0x00000100U)
-#define GPIO_BSRR_BS9                       ((uint32_t)0x00000200U)
-#define GPIO_BSRR_BS10                      ((uint32_t)0x00000400U)
-#define GPIO_BSRR_BS11                      ((uint32_t)0x00000800U)
-#define GPIO_BSRR_BS12                      ((uint32_t)0x00001000U)
-#define GPIO_BSRR_BS13                      ((uint32_t)0x00002000U)
-#define GPIO_BSRR_BS14                      ((uint32_t)0x00004000U)
-#define GPIO_BSRR_BS15                      ((uint32_t)0x00008000U)
-#define GPIO_BSRR_BR0                       ((uint32_t)0x00010000U)
-#define GPIO_BSRR_BR1                       ((uint32_t)0x00020000U)
-#define GPIO_BSRR_BR2                       ((uint32_t)0x00040000U)
-#define GPIO_BSRR_BR3                       ((uint32_t)0x00080000U)
-#define GPIO_BSRR_BR4                       ((uint32_t)0x00100000U)
-#define GPIO_BSRR_BR5                       ((uint32_t)0x00200000U)
-#define GPIO_BSRR_BR6                       ((uint32_t)0x00400000U)
-#define GPIO_BSRR_BR7                       ((uint32_t)0x00800000U)
-#define GPIO_BSRR_BR8                       ((uint32_t)0x01000000U)
-#define GPIO_BSRR_BR9                       ((uint32_t)0x02000000U)
-#define GPIO_BSRR_BR10                      ((uint32_t)0x04000000U)
-#define GPIO_BSRR_BR11                      ((uint32_t)0x08000000U)
-#define GPIO_BSRR_BR12                      ((uint32_t)0x10000000U)
-#define GPIO_BSRR_BR13                      ((uint32_t)0x20000000U)
-#define GPIO_BSRR_BR14                      ((uint32_t)0x40000000U)
-#define GPIO_BSRR_BR15                      ((uint32_t)0x80000000U)
-
-/* Legacy defines */
-#define GPIO_BSRR_BS_0                      GPIO_BSRR_BS0
-#define GPIO_BSRR_BS_1                      GPIO_BSRR_BS1
-#define GPIO_BSRR_BS_2                      GPIO_BSRR_BS2
-#define GPIO_BSRR_BS_3                      GPIO_BSRR_BS3
-#define GPIO_BSRR_BS_4                      GPIO_BSRR_BS4
-#define GPIO_BSRR_BS_5                      GPIO_BSRR_BS5
-#define GPIO_BSRR_BS_6                      GPIO_BSRR_BS6
-#define GPIO_BSRR_BS_7                      GPIO_BSRR_BS7
-#define GPIO_BSRR_BS_8                      GPIO_BSRR_BS8
-#define GPIO_BSRR_BS_9                      GPIO_BSRR_BS9
-#define GPIO_BSRR_BS_10                     GPIO_BSRR_BS10
-#define GPIO_BSRR_BS_11                     GPIO_BSRR_BS11
-#define GPIO_BSRR_BS_12                     GPIO_BSRR_BS12
-#define GPIO_BSRR_BS_13                     GPIO_BSRR_BS13
-#define GPIO_BSRR_BS_14                     GPIO_BSRR_BS14
-#define GPIO_BSRR_BS_15                     GPIO_BSRR_BS15
-#define GPIO_BSRR_BR_0                      GPIO_BSRR_BR0
-#define GPIO_BSRR_BR_1                      GPIO_BSRR_BR1
-#define GPIO_BSRR_BR_2                      GPIO_BSRR_BR2
-#define GPIO_BSRR_BR_3                      GPIO_BSRR_BR3
-#define GPIO_BSRR_BR_4                      GPIO_BSRR_BR4
-#define GPIO_BSRR_BR_5                      GPIO_BSRR_BR5
-#define GPIO_BSRR_BR_6                      GPIO_BSRR_BR6
-#define GPIO_BSRR_BR_7                      GPIO_BSRR_BR7
-#define GPIO_BSRR_BR_8                      GPIO_BSRR_BR8
-#define GPIO_BSRR_BR_9                      GPIO_BSRR_BR9
-#define GPIO_BSRR_BR_10                     GPIO_BSRR_BR10
-#define GPIO_BSRR_BR_11                     GPIO_BSRR_BR11
-#define GPIO_BSRR_BR_12                     GPIO_BSRR_BR12
-#define GPIO_BSRR_BR_13                     GPIO_BSRR_BR13
-#define GPIO_BSRR_BR_14                     GPIO_BSRR_BR14
-#define GPIO_BSRR_BR_15                     GPIO_BSRR_BR15
-
-/****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0                      ((uint32_t)0x00000001U)
-#define GPIO_LCKR_LCK1                      ((uint32_t)0x00000002U)
-#define GPIO_LCKR_LCK2                      ((uint32_t)0x00000004U)
-#define GPIO_LCKR_LCK3                      ((uint32_t)0x00000008U)
-#define GPIO_LCKR_LCK4                      ((uint32_t)0x00000010U)
-#define GPIO_LCKR_LCK5                      ((uint32_t)0x00000020U)
-#define GPIO_LCKR_LCK6                      ((uint32_t)0x00000040U)
-#define GPIO_LCKR_LCK7                      ((uint32_t)0x00000080U)
-#define GPIO_LCKR_LCK8                      ((uint32_t)0x00000100U)
-#define GPIO_LCKR_LCK9                      ((uint32_t)0x00000200U)
-#define GPIO_LCKR_LCK10                     ((uint32_t)0x00000400U)
-#define GPIO_LCKR_LCK11                     ((uint32_t)0x00000800U)
-#define GPIO_LCKR_LCK12                     ((uint32_t)0x00001000U)
-#define GPIO_LCKR_LCK13                     ((uint32_t)0x00002000U)
-#define GPIO_LCKR_LCK14                     ((uint32_t)0x00004000U)
-#define GPIO_LCKR_LCK15                     ((uint32_t)0x00008000U)
-#define GPIO_LCKR_LCKK                      ((uint32_t)0x00010000U)
-
-/****************** Bit definition for GPIO_AFRL register *********************/
-#define GPIO_AFRL_AFSEL0                    ((uint32_t)0x0000000FU)
-#define GPIO_AFRL_AFSEL0_0                  ((uint32_t)0x00000001U)
-#define GPIO_AFRL_AFSEL0_1                  ((uint32_t)0x00000002U)
-#define GPIO_AFRL_AFSEL0_2                  ((uint32_t)0x00000004U)
-#define GPIO_AFRL_AFSEL0_3                  ((uint32_t)0x00000008U)
-#define GPIO_AFRL_AFSEL1                    ((uint32_t)0x000000F0U)
-#define GPIO_AFRL_AFSEL1_0                  ((uint32_t)0x00000010U)
-#define GPIO_AFRL_AFSEL1_1                  ((uint32_t)0x00000020U)
-#define GPIO_AFRL_AFSEL1_2                  ((uint32_t)0x00000040U)
-#define GPIO_AFRL_AFSEL1_3                  ((uint32_t)0x00000080U)
-#define GPIO_AFRL_AFSEL2                    ((uint32_t)0x00000F00U)
-#define GPIO_AFRL_AFSEL2_0                  ((uint32_t)0x00000100U)
-#define GPIO_AFRL_AFSEL2_1                  ((uint32_t)0x00000200U)
-#define GPIO_AFRL_AFSEL2_2                  ((uint32_t)0x00000400U)
-#define GPIO_AFRL_AFSEL2_3                  ((uint32_t)0x00000800U)
-#define GPIO_AFRL_AFSEL3                    ((uint32_t)0x0000F000U)
-#define GPIO_AFRL_AFSEL3_0                  ((uint32_t)0x00001000U)
-#define GPIO_AFRL_AFSEL3_1                  ((uint32_t)0x00002000U)
-#define GPIO_AFRL_AFSEL3_2                  ((uint32_t)0x00004000U)
-#define GPIO_AFRL_AFSEL3_3                  ((uint32_t)0x00008000U)
-#define GPIO_AFRL_AFSEL4                    ((uint32_t)0x000F0000U)
-#define GPIO_AFRL_AFSEL4_0                  ((uint32_t)0x00010000U)
-#define GPIO_AFRL_AFSEL4_1                  ((uint32_t)0x00020000U)
-#define GPIO_AFRL_AFSEL4_2                  ((uint32_t)0x00040000U)
-#define GPIO_AFRL_AFSEL4_3                  ((uint32_t)0x00080000U)
-#define GPIO_AFRL_AFSEL5                    ((uint32_t)0x00F00000U)
-#define GPIO_AFRL_AFSEL5_0                  ((uint32_t)0x00100000U)
-#define GPIO_AFRL_AFSEL5_1                  ((uint32_t)0x00200000U)
-#define GPIO_AFRL_AFSEL5_2                  ((uint32_t)0x00400000U)
-#define GPIO_AFRL_AFSEL5_3                  ((uint32_t)0x00800000U)
-#define GPIO_AFRL_AFSEL6                    ((uint32_t)0x0F000000U)
-#define GPIO_AFRL_AFSEL6_0                  ((uint32_t)0x01000000U)
-#define GPIO_AFRL_AFSEL6_1                  ((uint32_t)0x02000000U)
-#define GPIO_AFRL_AFSEL6_2                  ((uint32_t)0x04000000U)
-#define GPIO_AFRL_AFSEL6_3                  ((uint32_t)0x08000000U)
-#define GPIO_AFRL_AFSEL7                    ((uint32_t)0xF0000000U)
-#define GPIO_AFRL_AFSEL7_0                  ((uint32_t)0x10000000U)
-#define GPIO_AFRL_AFSEL7_1                  ((uint32_t)0x20000000U)
-#define GPIO_AFRL_AFSEL7_2                  ((uint32_t)0x40000000U)
-#define GPIO_AFRL_AFSEL7_3                  ((uint32_t)0x80000000U)
-
-/* Legacy defines */
-#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0
-#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1
-#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2
-#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3
-#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4
-#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5
-#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6
-#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7
-
-/****************** Bit definition for GPIO_AFRH register *********************/
-#define GPIO_AFRH_AFSEL8                    ((uint32_t)0x0000000FU)
-#define GPIO_AFRH_AFSEL8_0                  ((uint32_t)0x00000001U)
-#define GPIO_AFRH_AFSEL8_1                  ((uint32_t)0x00000002U)
-#define GPIO_AFRH_AFSEL8_2                  ((uint32_t)0x00000004U)
-#define GPIO_AFRH_AFSEL8_3                  ((uint32_t)0x00000008U)
-#define GPIO_AFRH_AFSEL9                    ((uint32_t)0x000000F0U)
-#define GPIO_AFRH_AFSEL9_0                  ((uint32_t)0x00000010U)
-#define GPIO_AFRH_AFSEL9_1                  ((uint32_t)0x00000020U)
-#define GPIO_AFRH_AFSEL9_2                  ((uint32_t)0x00000040U)
-#define GPIO_AFRH_AFSEL9_3                  ((uint32_t)0x00000080U)
-#define GPIO_AFRH_AFSEL10                   ((uint32_t)0x00000F00U)
-#define GPIO_AFRH_AFSEL10_0                 ((uint32_t)0x00000100U)
-#define GPIO_AFRH_AFSEL10_1                 ((uint32_t)0x00000200U)
-#define GPIO_AFRH_AFSEL10_2                 ((uint32_t)0x00000400U)
-#define GPIO_AFRH_AFSEL10_3                 ((uint32_t)0x00000800U)
-#define GPIO_AFRH_AFSEL11                   ((uint32_t)0x0000F000U)
-#define GPIO_AFRH_AFSEL11_0                 ((uint32_t)0x00001000U)
-#define GPIO_AFRH_AFSEL11_1                 ((uint32_t)0x00002000U)
-#define GPIO_AFRH_AFSEL11_2                 ((uint32_t)0x00004000U)
-#define GPIO_AFRH_AFSEL11_3                 ((uint32_t)0x00008000U)
-#define GPIO_AFRH_AFSEL12                   ((uint32_t)0x000F0000U)
-#define GPIO_AFRH_AFSEL12_0                 ((uint32_t)0x00010000U)
-#define GPIO_AFRH_AFSEL12_1                 ((uint32_t)0x00020000U)
-#define GPIO_AFRH_AFSEL12_2                 ((uint32_t)0x00040000U)
-#define GPIO_AFRH_AFSEL12_3                 ((uint32_t)0x00080000U)
-#define GPIO_AFRH_AFSEL13                   ((uint32_t)0x00F00000U)
-#define GPIO_AFRH_AFSEL13_0                 ((uint32_t)0x00100000U)
-#define GPIO_AFRH_AFSEL13_1                 ((uint32_t)0x00200000U)
-#define GPIO_AFRH_AFSEL13_2                 ((uint32_t)0x00400000U)
-#define GPIO_AFRH_AFSEL13_3                 ((uint32_t)0x00800000U)
-#define GPIO_AFRH_AFSEL14                   ((uint32_t)0x0F000000U)
-#define GPIO_AFRH_AFSEL14_0                 ((uint32_t)0x01000000U)
-#define GPIO_AFRH_AFSEL14_1                 ((uint32_t)0x02000000U)
-#define GPIO_AFRH_AFSEL14_2                 ((uint32_t)0x04000000U)
-#define GPIO_AFRH_AFSEL14_3                 ((uint32_t)0x08000000U)
-#define GPIO_AFRH_AFSEL15                   ((uint32_t)0xF0000000U)
-#define GPIO_AFRH_AFSEL15_0                 ((uint32_t)0x10000000U)
-#define GPIO_AFRH_AFSEL15_1                 ((uint32_t)0x20000000U)
-#define GPIO_AFRH_AFSEL15_2                 ((uint32_t)0x40000000U)
-#define GPIO_AFRH_AFSEL15_3                 ((uint32_t)0x80000000U)
-
-/* Legacy defines */
-#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8
-#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9
-#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10
-#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11
-#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12
-#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13
-#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14
-#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15
-
-/******************  Bits definition for GPIO_BRR register  ******************/
-#define GPIO_BRR_BR0                        ((uint32_t)0x00000001U)
-#define GPIO_BRR_BR1                        ((uint32_t)0x00000002U)
-#define GPIO_BRR_BR2                        ((uint32_t)0x00000004U)
-#define GPIO_BRR_BR3                        ((uint32_t)0x00000008U)
-#define GPIO_BRR_BR4                        ((uint32_t)0x00000010U)
-#define GPIO_BRR_BR5                        ((uint32_t)0x00000020U)
-#define GPIO_BRR_BR6                        ((uint32_t)0x00000040U)
-#define GPIO_BRR_BR7                        ((uint32_t)0x00000080U)
-#define GPIO_BRR_BR8                        ((uint32_t)0x00000100U)
-#define GPIO_BRR_BR9                        ((uint32_t)0x00000200U)
-#define GPIO_BRR_BR10                       ((uint32_t)0x00000400U)
-#define GPIO_BRR_BR11                       ((uint32_t)0x00000800U)
-#define GPIO_BRR_BR12                       ((uint32_t)0x00001000U)
-#define GPIO_BRR_BR13                       ((uint32_t)0x00002000U)
-#define GPIO_BRR_BR14                       ((uint32_t)0x00004000U)
-#define GPIO_BRR_BR15                       ((uint32_t)0x00008000U)
-
-/* Legacy defines */
-#define GPIO_BRR_BR_0                       GPIO_BRR_BR0
-#define GPIO_BRR_BR_1                       GPIO_BRR_BR1
-#define GPIO_BRR_BR_2                       GPIO_BRR_BR2
-#define GPIO_BRR_BR_3                       GPIO_BRR_BR3
-#define GPIO_BRR_BR_4                       GPIO_BRR_BR4
-#define GPIO_BRR_BR_5                       GPIO_BRR_BR5
-#define GPIO_BRR_BR_6                       GPIO_BRR_BR6
-#define GPIO_BRR_BR_7                       GPIO_BRR_BR7
-#define GPIO_BRR_BR_8                       GPIO_BRR_BR8
-#define GPIO_BRR_BR_9                       GPIO_BRR_BR9
-#define GPIO_BRR_BR_10                      GPIO_BRR_BR10
-#define GPIO_BRR_BR_11                      GPIO_BRR_BR11
-#define GPIO_BRR_BR_12                      GPIO_BRR_BR12
-#define GPIO_BRR_BR_13                      GPIO_BRR_BR13
-#define GPIO_BRR_BR_14                      GPIO_BRR_BR14
-#define GPIO_BRR_BR_15                      GPIO_BRR_BR15
-
-
-/******************  Bits definition for GPIO_ASCR register  *******************/
-#define GPIO_ASCR_ASC0                      ((uint32_t)0x00000001U)
-#define GPIO_ASCR_ASC1                      ((uint32_t)0x00000002U)
-#define GPIO_ASCR_ASC2                      ((uint32_t)0x00000004U)
-#define GPIO_ASCR_ASC3                      ((uint32_t)0x00000008U)
-#define GPIO_ASCR_ASC4                      ((uint32_t)0x00000010U)
-#define GPIO_ASCR_ASC5                      ((uint32_t)0x00000020U)
-#define GPIO_ASCR_ASC6                      ((uint32_t)0x00000040U)
-#define GPIO_ASCR_ASC7                      ((uint32_t)0x00000080U)
-#define GPIO_ASCR_ASC8                      ((uint32_t)0x00000100U)
-#define GPIO_ASCR_ASC9                      ((uint32_t)0x00000200U)
-#define GPIO_ASCR_ASC10                     ((uint32_t)0x00000400U)
-#define GPIO_ASCR_ASC11                     ((uint32_t)0x00000800U)
-#define GPIO_ASCR_ASC12                     ((uint32_t)0x00001000U)
-#define GPIO_ASCR_ASC13                     ((uint32_t)0x00002000U)
-#define GPIO_ASCR_ASC14                     ((uint32_t)0x00004000U)
-#define GPIO_ASCR_ASC15                     ((uint32_t)0x00008000U)
-
-/* Legacy defines */
-#define GPIO_ASCR_EN_0                      GPIO_ASCR_ASC0
-#define GPIO_ASCR_EN_1                      GPIO_ASCR_ASC1
-#define GPIO_ASCR_EN_2                      GPIO_ASCR_ASC2
-#define GPIO_ASCR_EN_3                      GPIO_ASCR_ASC3
-#define GPIO_ASCR_EN_4                      GPIO_ASCR_ASC4
-#define GPIO_ASCR_EN_5                      GPIO_ASCR_ASC5
-#define GPIO_ASCR_EN_6                      GPIO_ASCR_ASC6
-#define GPIO_ASCR_EN_7                      GPIO_ASCR_ASC7
-#define GPIO_ASCR_EN_8                      GPIO_ASCR_ASC8
-#define GPIO_ASCR_EN_9                      GPIO_ASCR_ASC9
-#define GPIO_ASCR_EN_10                     GPIO_ASCR_ASC10
-#define GPIO_ASCR_EN_11                     GPIO_ASCR_ASC11
-#define GPIO_ASCR_EN_12                     GPIO_ASCR_ASC12
-#define GPIO_ASCR_EN_13                     GPIO_ASCR_ASC13
-#define GPIO_ASCR_EN_14                     GPIO_ASCR_ASC14
-#define GPIO_ASCR_EN_15                     GPIO_ASCR_ASC15
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Inter-integrated Circuit Interface (I2C)              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define  I2C_CR1_PE                          ((uint32_t)0x00000001U)        /*!< Peripheral enable                   */
-#define  I2C_CR1_TXIE                        ((uint32_t)0x00000002U)        /*!< TX interrupt enable                 */
-#define  I2C_CR1_RXIE                        ((uint32_t)0x00000004U)        /*!< RX interrupt enable                 */
-#define  I2C_CR1_ADDRIE                      ((uint32_t)0x00000008U)        /*!< Address match interrupt enable      */
-#define  I2C_CR1_NACKIE                      ((uint32_t)0x00000010U)        /*!< NACK received interrupt enable      */
-#define  I2C_CR1_STOPIE                      ((uint32_t)0x00000020U)        /*!< STOP detection interrupt enable     */
-#define  I2C_CR1_TCIE                        ((uint32_t)0x00000040U)        /*!< Transfer complete interrupt enable  */
-#define  I2C_CR1_ERRIE                       ((uint32_t)0x00000080U)        /*!< Errors interrupt enable             */
-#define  I2C_CR1_DNF                         ((uint32_t)0x00000F00U)        /*!< Digital noise filter                */
-#define  I2C_CR1_ANFOFF                      ((uint32_t)0x00001000U)        /*!< Analog noise filter OFF             */
-#define  I2C_CR1_SWRST                       ((uint32_t)0x00002000U)        /*!< Software reset                      */
-#define  I2C_CR1_TXDMAEN                     ((uint32_t)0x00004000U)        /*!< DMA transmission requests enable    */
-#define  I2C_CR1_RXDMAEN                     ((uint32_t)0x00008000U)        /*!< DMA reception requests enable       */
-#define  I2C_CR1_SBC                         ((uint32_t)0x00010000U)        /*!< Slave byte control                  */
-#define  I2C_CR1_NOSTRETCH                   ((uint32_t)0x00020000U)        /*!< Clock stretching disable            */
-#define  I2C_CR1_WUPEN                       ((uint32_t)0x00040000U)        /*!< Wakeup from STOP enable             */
-#define  I2C_CR1_GCEN                        ((uint32_t)0x00080000U)        /*!< General call enable                 */
-#define  I2C_CR1_SMBHEN                      ((uint32_t)0x00100000U)        /*!< SMBus host address enable           */
-#define  I2C_CR1_SMBDEN                      ((uint32_t)0x00200000U)        /*!< SMBus device default address enable */
-#define  I2C_CR1_ALERTEN                     ((uint32_t)0x00400000U)        /*!< SMBus alert enable                  */
-#define  I2C_CR1_PECEN                       ((uint32_t)0x00800000U)        /*!< PEC enable                          */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_SADD                        ((uint32_t)0x000003FFU)        /*!< Slave address (master mode)                             */
-#define  I2C_CR2_RD_WRN                      ((uint32_t)0x00000400U)        /*!< Transfer direction (master mode)                        */
-#define  I2C_CR2_ADD10                       ((uint32_t)0x00000800U)        /*!< 10-bit addressing mode (master mode)                    */
-#define  I2C_CR2_HEAD10R                     ((uint32_t)0x00001000U)        /*!< 10-bit address header only read direction (master mode) */
-#define  I2C_CR2_START                       ((uint32_t)0x00002000U)        /*!< START generation                                        */
-#define  I2C_CR2_STOP                        ((uint32_t)0x00004000U)        /*!< STOP generation (master mode)                           */
-#define  I2C_CR2_NACK                        ((uint32_t)0x00008000U)        /*!< NACK generation (slave mode)                            */
-#define  I2C_CR2_NBYTES                      ((uint32_t)0x00FF0000U)        /*!< Number of bytes                                         */
-#define  I2C_CR2_RELOAD                      ((uint32_t)0x01000000U)        /*!< NBYTES reload mode                                      */
-#define  I2C_CR2_AUTOEND                     ((uint32_t)0x02000000U)        /*!< Automatic end mode (master mode)                        */
-#define  I2C_CR2_PECBYTE                     ((uint32_t)0x04000000U)        /*!< Packet error checking byte                              */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define  I2C_OAR1_OA1                        ((uint32_t)0x000003FFU)        /*!< Interface own address 1   */
-#define  I2C_OAR1_OA1MODE                    ((uint32_t)0x00000400U)        /*!< Own address 1 10-bit mode */
-#define  I2C_OAR1_OA1EN                      ((uint32_t)0x00008000U)        /*!< Own address 1 enable      */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define  I2C_OAR2_OA2                        ((uint32_t)0x000000FEU)        /*!< Interface own address 2                        */
-#define  I2C_OAR2_OA2MSK                     ((uint32_t)0x00000700U)        /*!< Own address 2 masks                            */
-#define  I2C_OAR2_OA2NOMASK                  ((uint32_t)0x00000000U)        /*!< No mask                                        */
-#define  I2C_OAR2_OA2MASK01                  ((uint32_t)0x00000100U)        /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
-#define  I2C_OAR2_OA2MASK02                  ((uint32_t)0x00000200U)        /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
-#define  I2C_OAR2_OA2MASK03                  ((uint32_t)0x00000300U)        /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
-#define  I2C_OAR2_OA2MASK04                  ((uint32_t)0x00000400U)        /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
-#define  I2C_OAR2_OA2MASK05                  ((uint32_t)0x00000500U)        /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
-#define  I2C_OAR2_OA2MASK06                  ((uint32_t)0x00000600U)        /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
-#define  I2C_OAR2_OA2MASK07                  ((uint32_t)0x00000700U)        /*!< OA2[7:1] is masked, No comparison is done      */
-#define  I2C_OAR2_OA2EN                      ((uint32_t)0x00008000U)        /*!< Own address 2 enable                           */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define  I2C_TIMINGR_SCLL                    ((uint32_t)0x000000FFU)        /*!< SCL low period (master mode)  */
-#define  I2C_TIMINGR_SCLH                    ((uint32_t)0x0000FF00U)        /*!< SCL high period (master mode) */
-#define  I2C_TIMINGR_SDADEL                  ((uint32_t)0x000F0000U)        /*!< Data hold time                */
-#define  I2C_TIMINGR_SCLDEL                  ((uint32_t)0x00F00000U)        /*!< Data setup time               */
-#define  I2C_TIMINGR_PRESC                   ((uint32_t)0xF0000000U)        /*!< Timings prescaler             */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define  I2C_TIMEOUTR_TIMEOUTA               ((uint32_t)0x00000FFFU)        /*!< Bus timeout A                 */
-#define  I2C_TIMEOUTR_TIDLE                  ((uint32_t)0x00001000U)        /*!< Idle clock timeout detection  */
-#define  I2C_TIMEOUTR_TIMOUTEN               ((uint32_t)0x00008000U)        /*!< Clock timeout enable          */
-#define  I2C_TIMEOUTR_TIMEOUTB               ((uint32_t)0x0FFF0000U)        /*!< Bus timeout B                 */
-#define  I2C_TIMEOUTR_TEXTEN                 ((uint32_t)0x80000000U)        /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define  I2C_ISR_TXE                         ((uint32_t)0x00000001U)        /*!< Transmit data register empty    */
-#define  I2C_ISR_TXIS                        ((uint32_t)0x00000002U)        /*!< Transmit interrupt status       */
-#define  I2C_ISR_RXNE                        ((uint32_t)0x00000004U)        /*!< Receive data register not empty */
-#define  I2C_ISR_ADDR                        ((uint32_t)0x00000008U)        /*!< Address matched (slave mode)    */
-#define  I2C_ISR_NACKF                       ((uint32_t)0x00000010U)        /*!< NACK received flag              */
-#define  I2C_ISR_STOPF                       ((uint32_t)0x00000020U)        /*!< STOP detection flag             */
-#define  I2C_ISR_TC                          ((uint32_t)0x00000040U)        /*!< Transfer complete (master mode) */
-#define  I2C_ISR_TCR                         ((uint32_t)0x00000080U)        /*!< Transfer complete reload        */
-#define  I2C_ISR_BERR                        ((uint32_t)0x00000100U)        /*!< Bus error                       */
-#define  I2C_ISR_ARLO                        ((uint32_t)0x00000200U)        /*!< Arbitration lost                */
-#define  I2C_ISR_OVR                         ((uint32_t)0x00000400U)        /*!< Overrun/Underrun                */
-#define  I2C_ISR_PECERR                      ((uint32_t)0x00000800U)        /*!< PEC error in reception          */
-#define  I2C_ISR_TIMEOUT                     ((uint32_t)0x00001000U)        /*!< Timeout or Tlow detection flag  */
-#define  I2C_ISR_ALERT                       ((uint32_t)0x00002000U)        /*!< SMBus alert                     */
-#define  I2C_ISR_BUSY                        ((uint32_t)0x00008000U)        /*!< Bus busy                        */
-#define  I2C_ISR_DIR                         ((uint32_t)0x00010000U)        /*!< Transfer direction (slave mode) */
-#define  I2C_ISR_ADDCODE                     ((uint32_t)0x00FE0000U)        /*!< Address match code (slave mode) */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define  I2C_ICR_ADDRCF                      ((uint32_t)0x00000008U)        /*!< Address matched clear flag  */
-#define  I2C_ICR_NACKCF                      ((uint32_t)0x00000010U)        /*!< NACK clear flag             */
-#define  I2C_ICR_STOPCF                      ((uint32_t)0x00000020U)        /*!< STOP detection clear flag   */
-#define  I2C_ICR_BERRCF                      ((uint32_t)0x00000100U)        /*!< Bus error clear flag        */
-#define  I2C_ICR_ARLOCF                      ((uint32_t)0x00000200U)        /*!< Arbitration lost clear flag */
-#define  I2C_ICR_OVRCF                       ((uint32_t)0x00000400U)        /*!< Overrun/Underrun clear flag */
-#define  I2C_ICR_PECCF                       ((uint32_t)0x00000800U)        /*!< PAC error clear flag        */
-#define  I2C_ICR_TIMOUTCF                    ((uint32_t)0x00001000U)        /*!< Timeout clear flag          */
-#define  I2C_ICR_ALERTCF                     ((uint32_t)0x00002000U)        /*!< Alert clear flag            */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define  I2C_PECR_PEC                        ((uint32_t)0x000000FFU)        /*!< PEC register */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define  I2C_RXDR_RXDATA                     ((uint32_t)0x000000FFU)        /*!< 8-bit receive data */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define  I2C_TXDR_TXDATA                     ((uint32_t)0x000000FFU)        /*!< 8-bit transmit data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Independent WATCHDOG                             */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         ((uint32_t)0x0000FFFFU)        /*!<Key value (write only, read 0000h)  */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          ((uint32_t)0x00000007U)        /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        ((uint32_t)0x00000004U)        /*!<Bit 2 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         ((uint32_t)0x00000FFFU)        /*!<Watchdog counter reload value        */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         ((uint32_t)0x00000001U)        /*!< Watchdog prescaler value update */
-#define  IWDG_SR_RVU                         ((uint32_t)0x00000002U)        /*!< Watchdog counter reload value update */
-#define  IWDG_SR_WVU                         ((uint32_t)0x00000004U)        /*!< Watchdog counter window value update */
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_WINR_WIN                       ((uint32_t)0x00000FFFU)        /*!< Watchdog counter window value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                     Firewall                               */
-/*                                                                            */
-/******************************************************************************/
-
-/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL;LSSA;LSL register */
-#define  FW_CSSA_ADD                   ((uint32_t)0x00FFFF00U)        /*!< Code Segment Start Address */
-#define  FW_CSL_LENG                   ((uint32_t)0x003FFF00U)        /*!< Code Segment Length        */
-#define  FW_NVDSSA_ADD                 ((uint32_t)0x00FFFF00U)        /*!< Non Volatile Dat Segment Start Address */
-#define  FW_NVDSL_LENG                 ((uint32_t)0x003FFF00U)        /*!< Non Volatile Data Segment Length */
-#define  FW_VDSSA_ADD                  ((uint32_t)0x0001FFC0U)        /*!< Volatile Data Segment Start Address */
-#define  FW_VDSL_LENG                  ((uint32_t)0x0001FFC0U)        /*!< Volatile Data Segment Length */
-#define  FW_LSSA_ADD                   ((uint32_t)0x0007FF80U)        /*!< Library Segment Start Address*/
-#define  FW_LSL_LENG                   ((uint32_t)0x0007FF80U)        /*!< Library Segment Length*/
-
-/**************************Bit definition for CR register *********************/
-#define  FW_CR_FPA                     ((uint32_t)0x00000001U)         /*!< Firewall Pre Arm*/
-#define  FW_CR_VDS                     ((uint32_t)0x00000002U)         /*!< Volatile Data Sharing*/
-#define  FW_CR_VDE                     ((uint32_t)0x00000004U)         /*!< Volatile Data Execution*/
-
-/******************************************************************************/
-/*                                                                            */
-/*                             Power Control                                  */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for PWR_CR1 register  ********************/
-
-#define  PWR_CR1_LPR                         ((uint32_t)0x00004000U)     /*!< Regulator low-power mode */
-#define  PWR_CR1_VOS                         ((uint32_t)0x00000600U)     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
-#define  PWR_CR1_VOS_0                       ((uint32_t)0x00000200U)     /*!< Bit 0 */
-#define  PWR_CR1_VOS_1                       ((uint32_t)0x00000400U)     /*!< Bit 1 */
-#define  PWR_CR1_DBP                         ((uint32_t)0x00000100U)     /*!< Disable Back-up domain Protection */
-#define  PWR_CR1_LPMS                        ((uint32_t)0x00000007U)     /*!< Low-power mode selection field */
-#define  PWR_CR1_LPMS_STOP0                  ((uint32_t)0x00000000U)     /*!< Stop 0 mode */
-#define  PWR_CR1_LPMS_STOP1                  ((uint32_t)0x00000001U)     /*!< Stop 1 mode */
-#define  PWR_CR1_LPMS_STOP2                  ((uint32_t)0x00000002U)     /*!< Stop 2 mode */
-#define  PWR_CR1_LPMS_STANDBY                ((uint32_t)0x00000003U)     /*!< Stand-by mode */
-#define  PWR_CR1_LPMS_SHUTDOWN               ((uint32_t)0x00000004U)     /*!< Shut-down mode */
-
-
-/********************  Bit definition for PWR_CR2 register  ********************/
-#define  PWR_CR2_USV                         ((uint32_t)0x00000400U)     /*!< VDD USB Supply Valid */
-#define  PWR_CR2_IOSV                        ((uint32_t)0x00000200U)     /*!< VDD IO2 independent I/Os Supply Valid */
-/*!< PVME  Peripheral Voltage Monitor Enable */
-#define  PWR_CR2_PVME                        ((uint32_t)0x000000F0U)     /*!< PVM bits field */
-#define  PWR_CR2_PVME4                       ((uint32_t)0x00000080U)     /*!< PVM 4 Enable */
-#define  PWR_CR2_PVME3                       ((uint32_t)0x00000040U)     /*!< PVM 3 Enable */
-#define  PWR_CR2_PVME2                       ((uint32_t)0x00000020U)     /*!< PVM 2 Enable */
-#define  PWR_CR2_PVME1                       ((uint32_t)0x00000010U)     /*!< PVM 1 Enable */
-/*!< PVD level configuration */
-#define  PWR_CR2_PLS                         ((uint32_t)0x0000000EU)     /*!< PVD level selection */
-#define  PWR_CR2_PLS_LEV0                    ((uint32_t)0x00000000U)     /*!< PVD level 0 */
-#define  PWR_CR2_PLS_LEV1                    ((uint32_t)0x00000002U)     /*!< PVD level 1 */
-#define  PWR_CR2_PLS_LEV2                    ((uint32_t)0x00000004U)     /*!< PVD level 2 */
-#define  PWR_CR2_PLS_LEV3                    ((uint32_t)0x00000006U)     /*!< PVD level 3 */
-#define  PWR_CR2_PLS_LEV4                    ((uint32_t)0x00000008U)     /*!< PVD level 4 */
-#define  PWR_CR2_PLS_LEV5                    ((uint32_t)0x0000000AU)     /*!< PVD level 5 */
-#define  PWR_CR2_PLS_LEV6                    ((uint32_t)0x0000000CU)     /*!< PVD level 6 */
-#define  PWR_CR2_PLS_LEV7                    ((uint32_t)0x0000000EU)     /*!< PVD level 7 */
-#define  PWR_CR2_PVDE                        ((uint32_t)0x00000001U)     /*!< Power Voltage Detector Enable */
-
-/********************  Bit definition for PWR_CR3 register  ********************/
-#define  PWR_CR3_EIWF                        ((uint32_t)0x00008000U)      /*!< Enable Internal Wake-up line */
-#define  PWR_CR3_APC                         ((uint32_t)0x00000400U)      /*!< Apply pull-up and pull-down configuration */
-#define  PWR_CR3_RRS                         ((uint32_t)0x00000100U)      /*!< SRAM2 Retention in Stand-by mode */
-#define  PWR_CR3_EWUP5                       ((uint32_t)0x00000010U)      /*!< Enable Wake-Up Pin 5 */
-#define  PWR_CR3_EWUP4                       ((uint32_t)0x00000008U)      /*!< Enable Wake-Up Pin 4 */
-#define  PWR_CR3_EWUP3                       ((uint32_t)0x00000004U)      /*!< Enable Wake-Up Pin 3 */
-#define  PWR_CR3_EWUP2                       ((uint32_t)0x00000002U)      /*!< Enable Wake-Up Pin 2 */
-#define  PWR_CR3_EWUP1                       ((uint32_t)0x00000001U)      /*!< Enable Wake-Up Pin 1 */
-#define  PWR_CR3_EWUP                        ((uint32_t)0x0000001FU)      /*!< Enable Wake-Up Pins  */
-
-/********************  Bit definition for PWR_CR4 register  ********************/
-#define  PWR_CR4_VBRS                        ((uint32_t)0x00000200U)      /*!< VBAT Battery charging Resistor Selection */
-#define  PWR_CR4_VBE                         ((uint32_t)0x00000100U)      /*!< VBAT Battery charging Enable  */
-#define  PWR_CR4_WP5                         ((uint32_t)0x00000010U)      /*!< Wake-Up Pin 5 polarity */
-#define  PWR_CR4_WP4                         ((uint32_t)0x00000008U)      /*!< Wake-Up Pin 4 polarity */
-#define  PWR_CR4_WP3                         ((uint32_t)0x00000004U)      /*!< Wake-Up Pin 3 polarity */
-#define  PWR_CR4_WP2                         ((uint32_t)0x00000002U)      /*!< Wake-Up Pin 2 polarity */
-#define  PWR_CR4_WP1                         ((uint32_t)0x00000001U)      /*!< Wake-Up Pin 1 polarity */
-
-/********************  Bit definition for PWR_SR1 register  ********************/
-#define   PWR_SR1_WUFI                       ((uint32_t)0x00008000U)     /*!< Wake-Up Flag Internal */
-#define   PWR_SR1_SBF                        ((uint32_t)0x00000100U)     /*!< Stand-By Flag */
-#define   PWR_SR1_WUF                        ((uint32_t)0x0000001FU)     /*!< Wake-up Flags */
-#define   PWR_SR1_WUF5                       ((uint32_t)0x00000010U)     /*!< Wake-up Flag 5 */
-#define   PWR_SR1_WUF4                       ((uint32_t)0x00000008U)     /*!< Wake-up Flag 4 */
-#define   PWR_SR1_WUF3                       ((uint32_t)0x00000004U)     /*!< Wake-up Flag 3 */
-#define   PWR_SR1_WUF2                       ((uint32_t)0x00000002U)     /*!< Wake-up Flag 2 */
-#define   PWR_SR1_WUF1                       ((uint32_t)0x00000001U)     /*!< Wake-up Flag 1 */
-
-/********************  Bit definition for PWR_SR2 register  ********************/
-#define   PWR_SR2_PVMO4                      ((uint32_t)0x00008000U)     /*!< Peripheral Voltage Monitoring Output 4 */
-#define   PWR_SR2_PVMO3                      ((uint32_t)0x00004000U)     /*!< Peripheral Voltage Monitoring Output 3 */
-#define   PWR_SR2_PVMO2                      ((uint32_t)0x00002000U)     /*!< Peripheral Voltage Monitoring Output 2 */
-#define   PWR_SR2_PVMO1                      ((uint32_t)0x00001000U)     /*!< Peripheral Voltage Monitoring Output 1 */
-#define   PWR_SR2_PVDO                       ((uint32_t)0x00000800U)     /*!< Power Voltage Detector Output */
-#define   PWR_SR2_VOSF                       ((uint32_t)0x00000400U)     /*!< Voltage Scaling Flag */
-#define   PWR_SR2_REGLPF                     ((uint32_t)0x00000200U)     /*!< Low-power Regulator Flag */
-#define   PWR_SR2_REGLPS                     ((uint32_t)0x00000100U)     /*!< Low-power Regulator Started */
-
-/********************  Bit definition for PWR_SCR register  ********************/
-#define   PWR_SCR_CSBF                       ((uint32_t)0x00000100U)      /*!< Clear Stand-By Flag */
-#define   PWR_SCR_CWUF                       ((uint32_t)0x0000001FU)      /*!< Clear Wake-up Flags  */
-#define   PWR_SCR_CWUF5                      ((uint32_t)0x00000010U)      /*!< Clear Wake-up Flag 5 */
-#define   PWR_SCR_CWUF4                      ((uint32_t)0x00000008U)      /*!< Clear Wake-up Flag 4 */
-#define   PWR_SCR_CWUF3                      ((uint32_t)0x00000004U)      /*!< Clear Wake-up Flag 3 */
-#define   PWR_SCR_CWUF2                      ((uint32_t)0x00000002U)      /*!< Clear Wake-up Flag 2 */
-#define   PWR_SCR_CWUF1                      ((uint32_t)0x00000001U)      /*!< Clear Wake-up Flag 1 */
-
-/********************  Bit definition for PWR_PUCRA register  ********************/
-#define   PWR_PUCRA_PA15                     ((uint32_t)0x00008000U)      /*!< Port PA15 Pull-Up set */
-#define   PWR_PUCRA_PA13                     ((uint32_t)0x00002000U)      /*!< Port PA13 Pull-Up set */
-#define   PWR_PUCRA_PA12                     ((uint32_t)0x00001000U)      /*!< Port PA12 Pull-Up set */
-#define   PWR_PUCRA_PA11                     ((uint32_t)0x00000800U)      /*!< Port PA11 Pull-Up set */
-#define   PWR_PUCRA_PA10                     ((uint32_t)0x00000400U)      /*!< Port PA10 Pull-Up set */
-#define   PWR_PUCRA_PA9                      ((uint32_t)0x00000200U)      /*!< Port PA9 Pull-Up set  */
-#define   PWR_PUCRA_PA8                      ((uint32_t)0x00000100U)      /*!< Port PA8 Pull-Up set  */
-#define   PWR_PUCRA_PA7                      ((uint32_t)0x00000080U)      /*!< Port PA7 Pull-Up set  */
-#define   PWR_PUCRA_PA6                      ((uint32_t)0x00000040U)      /*!< Port PA6 Pull-Up set  */
-#define   PWR_PUCRA_PA5                      ((uint32_t)0x00000020U)      /*!< Port PA5 Pull-Up set  */
-#define   PWR_PUCRA_PA4                      ((uint32_t)0x00000010U)      /*!< Port PA4 Pull-Up set  */
-#define   PWR_PUCRA_PA3                      ((uint32_t)0x00000008U)      /*!< Port PA3 Pull-Up set  */
-#define   PWR_PUCRA_PA2                      ((uint32_t)0x00000004U)      /*!< Port PA2 Pull-Up set  */
-#define   PWR_PUCRA_PA1                      ((uint32_t)0x00000002U)      /*!< Port PA1 Pull-Up set  */
-#define   PWR_PUCRA_PA0                      ((uint32_t)0x00000001U)      /*!< Port PA0 Pull-Up set  */
-
-/********************  Bit definition for PWR_PDCRA register  ********************/
-#define   PWR_PDCRA_PA14                     ((uint32_t)0x00004000U)      /*!< Port PA14 Pull-Down set */
-#define   PWR_PDCRA_PA12                     ((uint32_t)0x00001000U)      /*!< Port PA12 Pull-Down set */
-#define   PWR_PDCRA_PA11                     ((uint32_t)0x00000800U)      /*!< Port PA11 Pull-Down set */
-#define   PWR_PDCRA_PA10                     ((uint32_t)0x00000400U)      /*!< Port PA10 Pull-Down set */
-#define   PWR_PDCRA_PA9                      ((uint32_t)0x00000200U)      /*!< Port PA9 Pull-Down set  */
-#define   PWR_PDCRA_PA8                      ((uint32_t)0x00000100U)      /*!< Port PA8 Pull-Down set  */
-#define   PWR_PDCRA_PA7                      ((uint32_t)0x00000080U)      /*!< Port PA7 Pull-Down set  */
-#define   PWR_PDCRA_PA6                      ((uint32_t)0x00000040U)      /*!< Port PA6 Pull-Down set  */
-#define   PWR_PDCRA_PA5                      ((uint32_t)0x00000020U)      /*!< Port PA5 Pull-Down set  */
-#define   PWR_PDCRA_PA4                      ((uint32_t)0x00000010U)      /*!< Port PA4 Pull-Down set  */
-#define   PWR_PDCRA_PA3                      ((uint32_t)0x00000008U)      /*!< Port PA3 Pull-Down set  */
-#define   PWR_PDCRA_PA2                      ((uint32_t)0x00000004U)      /*!< Port PA2 Pull-Down set  */
-#define   PWR_PDCRA_PA1                      ((uint32_t)0x00000002U)      /*!< Port PA1 Pull-Down set  */
-#define   PWR_PDCRA_PA0                      ((uint32_t)0x00000001U)      /*!< Port PA0 Pull-Down set  */
-
-/********************  Bit definition for PWR_PUCRB register  ********************/
-#define   PWR_PUCRB_PB15                     ((uint32_t)0x00008000U)      /*!< Port PB15 Pull-Up set */
-#define   PWR_PUCRB_PB14                     ((uint32_t)0x00004000U)      /*!< Port PB14 Pull-Up set */
-#define   PWR_PUCRB_PB13                     ((uint32_t)0x00002000U)      /*!< Port PB13 Pull-Up set */
-#define   PWR_PUCRB_PB12                     ((uint32_t)0x00001000U)      /*!< Port PB12 Pull-Up set */
-#define   PWR_PUCRB_PB11                     ((uint32_t)0x00000800U)      /*!< Port PB11 Pull-Up set */
-#define   PWR_PUCRB_PB10                     ((uint32_t)0x00000400U)      /*!< Port PB10 Pull-Up set */
-#define   PWR_PUCRB_PB9                      ((uint32_t)0x00000200U)      /*!< Port PB9 Pull-Up set  */
-#define   PWR_PUCRB_PB8                      ((uint32_t)0x00000100U)      /*!< Port PB8 Pull-Up set  */
-#define   PWR_PUCRB_PB7                      ((uint32_t)0x00000080U)      /*!< Port PB7 Pull-Up set  */
-#define   PWR_PUCRB_PB6                      ((uint32_t)0x00000040U)      /*!< Port PB6 Pull-Up set  */
-#define   PWR_PUCRB_PB5                      ((uint32_t)0x00000020U)      /*!< Port PB5 Pull-Up set  */
-#define   PWR_PUCRB_PB4                      ((uint32_t)0x00000010U)      /*!< Port PB4 Pull-Up set  */
-#define   PWR_PUCRB_PB3                      ((uint32_t)0x00000008U)      /*!< Port PB3 Pull-Up set  */
-#define   PWR_PUCRB_PB2                      ((uint32_t)0x00000004U)      /*!< Port PB2 Pull-Up set  */
-#define   PWR_PUCRB_PB1                      ((uint32_t)0x00000002U)      /*!< Port PB1 Pull-Up set  */
-#define   PWR_PUCRB_PB0                      ((uint32_t)0x00000001U)      /*!< Port PB0 Pull-Up set  */
-
-/********************  Bit definition for PWR_PDCRB register  ********************/
-#define   PWR_PDCRB_PB15                     ((uint32_t)0x00008000U)      /*!< Port PB15 Pull-Down set */
-#define   PWR_PDCRB_PB14                     ((uint32_t)0x00004000U)      /*!< Port PB14 Pull-Down set */
-#define   PWR_PDCRB_PB13                     ((uint32_t)0x00002000U)      /*!< Port PB13 Pull-Down set */
-#define   PWR_PDCRB_PB12                     ((uint32_t)0x00001000U)      /*!< Port PB12 Pull-Down set */
-#define   PWR_PDCRB_PB11                     ((uint32_t)0x00000800U)      /*!< Port PB11 Pull-Down set */
-#define   PWR_PDCRB_PB10                     ((uint32_t)0x00000400U)      /*!< Port PB10 Pull-Down set */
-#define   PWR_PDCRB_PB9                      ((uint32_t)0x00000200U)      /*!< Port PB9 Pull-Down set  */
-#define   PWR_PDCRB_PB8                      ((uint32_t)0x00000100U)      /*!< Port PB8 Pull-Down set  */
-#define   PWR_PDCRB_PB7                      ((uint32_t)0x00000080U)      /*!< Port PB7 Pull-Down set  */
-#define   PWR_PDCRB_PB6                      ((uint32_t)0x00000040U)      /*!< Port PB6 Pull-Down set  */
-#define   PWR_PDCRB_PB5                      ((uint32_t)0x00000020U)      /*!< Port PB5 Pull-Down set  */
-#define   PWR_PDCRB_PB3                      ((uint32_t)0x00000008U)      /*!< Port PB3 Pull-Down set  */
-#define   PWR_PDCRB_PB2                      ((uint32_t)0x00000004U)      /*!< Port PB2 Pull-Down set  */
-#define   PWR_PDCRB_PB1                      ((uint32_t)0x00000002U)      /*!< Port PB1 Pull-Down set  */
-#define   PWR_PDCRB_PB0                      ((uint32_t)0x00000001U)      /*!< Port PB0 Pull-Down set  */
-
-/********************  Bit definition for PWR_PUCRC register  ********************/
-#define   PWR_PUCRC_PC15                     ((uint32_t)0x00008000U)      /*!< Port PC15 Pull-Up set */
-#define   PWR_PUCRC_PC14                     ((uint32_t)0x00004000U)      /*!< Port PC14 Pull-Up set */
-#define   PWR_PUCRC_PC13                     ((uint32_t)0x00002000U)      /*!< Port PC13 Pull-Up set */
-#define   PWR_PUCRC_PC12                     ((uint32_t)0x00001000U)      /*!< Port PC12 Pull-Up set */
-#define   PWR_PUCRC_PC11                     ((uint32_t)0x00000800U)      /*!< Port PC11 Pull-Up set */
-#define   PWR_PUCRC_PC10                     ((uint32_t)0x00000400U)      /*!< Port PC10 Pull-Up set */
-#define   PWR_PUCRC_PC9                      ((uint32_t)0x00000200U)      /*!< Port PC9 Pull-Up set  */
-#define   PWR_PUCRC_PC8                      ((uint32_t)0x00000100U)      /*!< Port PC8 Pull-Up set  */
-#define   PWR_PUCRC_PC7                      ((uint32_t)0x00000080U)      /*!< Port PC7 Pull-Up set  */
-#define   PWR_PUCRC_PC6                      ((uint32_t)0x00000040U)      /*!< Port PC6 Pull-Up set  */
-#define   PWR_PUCRC_PC5                      ((uint32_t)0x00000020U)      /*!< Port PC5 Pull-Up set  */
-#define   PWR_PUCRC_PC4                      ((uint32_t)0x00000010U)      /*!< Port PC4 Pull-Up set  */
-#define   PWR_PUCRC_PC3                      ((uint32_t)0x00000008U)      /*!< Port PC3 Pull-Up set  */
-#define   PWR_PUCRC_PC2                      ((uint32_t)0x00000004U)      /*!< Port PC2 Pull-Up set  */
-#define   PWR_PUCRC_PC1                      ((uint32_t)0x00000002U)      /*!< Port PC1 Pull-Up set  */
-#define   PWR_PUCRC_PC0                      ((uint32_t)0x00000001U)      /*!< Port PC0 Pull-Up set  */
-
-/********************  Bit definition for PWR_PDCRC register  ********************/
-#define   PWR_PDCRC_PC15                     ((uint32_t)0x00008000U)      /*!< Port PC15 Pull-Down set */
-#define   PWR_PDCRC_PC14                     ((uint32_t)0x00004000U)      /*!< Port PC14 Pull-Down set */
-#define   PWR_PDCRC_PC13                     ((uint32_t)0x00002000U)      /*!< Port PC13 Pull-Down set */
-#define   PWR_PDCRC_PC12                     ((uint32_t)0x00001000U)      /*!< Port PC12 Pull-Down set */
-#define   PWR_PDCRC_PC11                     ((uint32_t)0x00000800U)      /*!< Port PC11 Pull-Down set */
-#define   PWR_PDCRC_PC10                     ((uint32_t)0x00000400U)      /*!< Port PC10 Pull-Down set */
-#define   PWR_PDCRC_PC9                      ((uint32_t)0x00000200U)      /*!< Port PC9 Pull-Down set  */
-#define   PWR_PDCRC_PC8                      ((uint32_t)0x00000100U)      /*!< Port PC8 Pull-Down set  */
-#define   PWR_PDCRC_PC7                      ((uint32_t)0x00000080U)      /*!< Port PC7 Pull-Down set  */
-#define   PWR_PDCRC_PC6                      ((uint32_t)0x00000040U)      /*!< Port PC6 Pull-Down set  */
-#define   PWR_PDCRC_PC5                      ((uint32_t)0x00000020U)      /*!< Port PC5 Pull-Down set  */
-#define   PWR_PDCRC_PC4                      ((uint32_t)0x00000010U)      /*!< Port PC4 Pull-Down set  */
-#define   PWR_PDCRC_PC3                      ((uint32_t)0x00000008U)      /*!< Port PC3 Pull-Down set  */
-#define   PWR_PDCRC_PC2                      ((uint32_t)0x00000004U)      /*!< Port PC2 Pull-Down set  */
-#define   PWR_PDCRC_PC1                      ((uint32_t)0x00000002U)      /*!< Port PC1 Pull-Down set  */
-#define   PWR_PDCRC_PC0                      ((uint32_t)0x00000001U)      /*!< Port PC0 Pull-Down set  */
-
-/********************  Bit definition for PWR_PUCRD register  ********************/
-#define   PWR_PUCRD_PD15                     ((uint32_t)0x00008000U)      /*!< Port PD15 Pull-Up set */
-#define   PWR_PUCRD_PD14                     ((uint32_t)0x00004000U)      /*!< Port PD14 Pull-Up set */
-#define   PWR_PUCRD_PD13                     ((uint32_t)0x00002000U)      /*!< Port PD13 Pull-Up set */
-#define   PWR_PUCRD_PD12                     ((uint32_t)0x00001000U)      /*!< Port PD12 Pull-Up set */
-#define   PWR_PUCRD_PD11                     ((uint32_t)0x00000800U)      /*!< Port PD11 Pull-Up set */
-#define   PWR_PUCRD_PD10                     ((uint32_t)0x00000400U)      /*!< Port PD10 Pull-Up set */
-#define   PWR_PUCRD_PD9                      ((uint32_t)0x00000200U)      /*!< Port PD9 Pull-Up set  */
-#define   PWR_PUCRD_PD8                      ((uint32_t)0x00000100U)      /*!< Port PD8 Pull-Up set  */
-#define   PWR_PUCRD_PD7                      ((uint32_t)0x00000080U)      /*!< Port PD7 Pull-Up set  */
-#define   PWR_PUCRD_PD6                      ((uint32_t)0x00000040U)      /*!< Port PD6 Pull-Up set  */
-#define   PWR_PUCRD_PD5                      ((uint32_t)0x00000020U)      /*!< Port PD5 Pull-Up set  */
-#define   PWR_PUCRD_PD4                      ((uint32_t)0x00000010U)      /*!< Port PD4 Pull-Up set  */
-#define   PWR_PUCRD_PD3                      ((uint32_t)0x00000008U)      /*!< Port PD3 Pull-Up set  */
-#define   PWR_PUCRD_PD2                      ((uint32_t)0x00000004U)      /*!< Port PD2 Pull-Up set  */
-#define   PWR_PUCRD_PD1                      ((uint32_t)0x00000002U)      /*!< Port PD1 Pull-Up set  */
-#define   PWR_PUCRD_PD0                      ((uint32_t)0x00000001U)      /*!< Port PD0 Pull-Up set  */
-
-/********************  Bit definition for PWR_PDCRD register  ********************/
-#define   PWR_PDCRD_PD15                     ((uint32_t)0x00008000U)      /*!< Port PD15 Pull-Down set */
-#define   PWR_PDCRD_PD14                     ((uint32_t)0x00004000U)      /*!< Port PD14 Pull-Down set */
-#define   PWR_PDCRD_PD13                     ((uint32_t)0x00002000U)      /*!< Port PD13 Pull-Down set */
-#define   PWR_PDCRD_PD12                     ((uint32_t)0x00001000U)      /*!< Port PD12 Pull-Down set */
-#define   PWR_PDCRD_PD11                     ((uint32_t)0x00000800U)      /*!< Port PD11 Pull-Down set */
-#define   PWR_PDCRD_PD10                     ((uint32_t)0x00000400U)      /*!< Port PD10 Pull-Down set */
-#define   PWR_PDCRD_PD9                      ((uint32_t)0x00000200U)      /*!< Port PD9 Pull-Down set  */
-#define   PWR_PDCRD_PD8                      ((uint32_t)0x00000100U)      /*!< Port PD8 Pull-Down set  */
-#define   PWR_PDCRD_PD7                      ((uint32_t)0x00000080U)      /*!< Port PD7 Pull-Down set  */
-#define   PWR_PDCRD_PD6                      ((uint32_t)0x00000040U)      /*!< Port PD6 Pull-Down set  */
-#define   PWR_PDCRD_PD5                      ((uint32_t)0x00000020U)      /*!< Port PD5 Pull-Down set  */
-#define   PWR_PDCRD_PD4                      ((uint32_t)0x00000010U)      /*!< Port PD4 Pull-Down set  */
-#define   PWR_PDCRD_PD3                      ((uint32_t)0x00000008U)      /*!< Port PD3 Pull-Down set  */
-#define   PWR_PDCRD_PD2                      ((uint32_t)0x00000004U)      /*!< Port PD2 Pull-Down set  */
-#define   PWR_PDCRD_PD1                      ((uint32_t)0x00000002U)      /*!< Port PD1 Pull-Down set  */
-#define   PWR_PDCRD_PD0                      ((uint32_t)0x00000001U)      /*!< Port PD0 Pull-Down set  */
-
-/********************  Bit definition for PWR_PUCRE register  ********************/
-#define   PWR_PUCRE_PE15                     ((uint32_t)0x00008000U)      /*!< Port PE15 Pull-Up set */
-#define   PWR_PUCRE_PE14                     ((uint32_t)0x00004000U)      /*!< Port PE14 Pull-Up set */
-#define   PWR_PUCRE_PE13                     ((uint32_t)0x00002000U)      /*!< Port PE13 Pull-Up set */
-#define   PWR_PUCRE_PE12                     ((uint32_t)0x00001000U)      /*!< Port PE12 Pull-Up set */
-#define   PWR_PUCRE_PE11                     ((uint32_t)0x00000800U)      /*!< Port PE11 Pull-Up set */
-#define   PWR_PUCRE_PE10                     ((uint32_t)0x00000400U)      /*!< Port PE10 Pull-Up set */
-#define   PWR_PUCRE_PE9                      ((uint32_t)0x00000200U)      /*!< Port PE9 Pull-Up set  */
-#define   PWR_PUCRE_PE8                      ((uint32_t)0x00000100U)      /*!< Port PE8 Pull-Up set  */
-#define   PWR_PUCRE_PE7                      ((uint32_t)0x00000080U)      /*!< Port PE7 Pull-Up set  */
-#define   PWR_PUCRE_PE6                      ((uint32_t)0x00000040U)      /*!< Port PE6 Pull-Up set  */
-#define   PWR_PUCRE_PE5                      ((uint32_t)0x00000020U)      /*!< Port PE5 Pull-Up set  */
-#define   PWR_PUCRE_PE4                      ((uint32_t)0x00000010U)      /*!< Port PE4 Pull-Up set  */
-#define   PWR_PUCRE_PE3                      ((uint32_t)0x00000008U)      /*!< Port PE3 Pull-Up set  */
-#define   PWR_PUCRE_PE2                      ((uint32_t)0x00000004U)      /*!< Port PE2 Pull-Up set  */
-#define   PWR_PUCRE_PE1                      ((uint32_t)0x00000002U)      /*!< Port PE1 Pull-Up set  */
-#define   PWR_PUCRE_PE0                      ((uint32_t)0x00000001U)      /*!< Port PE0 Pull-Up set  */
-
-/********************  Bit definition for PWR_PDCRE register  ********************/
-#define   PWR_PDCRE_PE15                     ((uint32_t)0x00008000U)      /*!< Port PE15 Pull-Down set */
-#define   PWR_PDCRE_PE14                     ((uint32_t)0x00004000U)      /*!< Port PE14 Pull-Down set */
-#define   PWR_PDCRE_PE13                     ((uint32_t)0x00002000U)      /*!< Port PE13 Pull-Down set */
-#define   PWR_PDCRE_PE12                     ((uint32_t)0x00001000U)      /*!< Port PE12 Pull-Down set */
-#define   PWR_PDCRE_PE11                     ((uint32_t)0x00000800U)      /*!< Port PE11 Pull-Down set */
-#define   PWR_PDCRE_PE10                     ((uint32_t)0x00000400U)      /*!< Port PE10 Pull-Down set */
-#define   PWR_PDCRE_PE9                      ((uint32_t)0x00000200U)      /*!< Port PE9 Pull-Down set  */
-#define   PWR_PDCRE_PE8                      ((uint32_t)0x00000100U)      /*!< Port PE8 Pull-Down set  */
-#define   PWR_PDCRE_PE7                      ((uint32_t)0x00000080U)      /*!< Port PE7 Pull-Down set  */
-#define   PWR_PDCRE_PE6                      ((uint32_t)0x00000040U)      /*!< Port PE6 Pull-Down set  */
-#define   PWR_PDCRE_PE5                      ((uint32_t)0x00000020U)      /*!< Port PE5 Pull-Down set  */
-#define   PWR_PDCRE_PE4                      ((uint32_t)0x00000010U)      /*!< Port PE4 Pull-Down set  */
-#define   PWR_PDCRE_PE3                      ((uint32_t)0x00000008U)      /*!< Port PE3 Pull-Down set  */
-#define   PWR_PDCRE_PE2                      ((uint32_t)0x00000004U)      /*!< Port PE2 Pull-Down set  */
-#define   PWR_PDCRE_PE1                      ((uint32_t)0x00000002U)      /*!< Port PE1 Pull-Down set  */
-#define   PWR_PDCRE_PE0                      ((uint32_t)0x00000001U)      /*!< Port PE0 Pull-Down set  */
-
-/********************  Bit definition for PWR_PUCRF register  ********************/
-#define   PWR_PUCRF_PF15                     ((uint32_t)0x00008000U)      /*!< Port PF15 Pull-Up set */
-#define   PWR_PUCRF_PF14                     ((uint32_t)0x00004000U)      /*!< Port PF14 Pull-Up set */
-#define   PWR_PUCRF_PF13                     ((uint32_t)0x00002000U)      /*!< Port PF13 Pull-Up set */
-#define   PWR_PUCRF_PF12                     ((uint32_t)0x00001000U)      /*!< Port PF12 Pull-Up set */
-#define   PWR_PUCRF_PF11                     ((uint32_t)0x00000800U)      /*!< Port PF11 Pull-Up set */
-#define   PWR_PUCRF_PF10                     ((uint32_t)0x00000400U)      /*!< Port PF10 Pull-Up set */
-#define   PWR_PUCRF_PF9                      ((uint32_t)0x00000200U)      /*!< Port PF9 Pull-Up set  */
-#define   PWR_PUCRF_PF8                      ((uint32_t)0x00000100U)      /*!< Port PF8 Pull-Up set  */
-#define   PWR_PUCRF_PF7                      ((uint32_t)0x00000080U)      /*!< Port PF7 Pull-Up set  */
-#define   PWR_PUCRF_PF6                      ((uint32_t)0x00000040U)      /*!< Port PF6 Pull-Up set  */
-#define   PWR_PUCRF_PF5                      ((uint32_t)0x00000020U)      /*!< Port PF5 Pull-Up set  */
-#define   PWR_PUCRF_PF4                      ((uint32_t)0x00000010U)      /*!< Port PF4 Pull-Up set  */
-#define   PWR_PUCRF_PF3                      ((uint32_t)0x00000008U)      /*!< Port PF3 Pull-Up set  */
-#define   PWR_PUCRF_PF2                      ((uint32_t)0x00000004U)      /*!< Port PF2 Pull-Up set  */
-#define   PWR_PUCRF_PF1                      ((uint32_t)0x00000002U)      /*!< Port PF1 Pull-Up set  */
-#define   PWR_PUCRF_PF0                      ((uint32_t)0x00000001U)      /*!< Port PF0 Pull-Up set  */
-
-/********************  Bit definition for PWR_PDCRF register  ********************/
-#define   PWR_PDCRF_PF15                     ((uint32_t)0x00008000U)      /*!< Port PF15 Pull-Down set */
-#define   PWR_PDCRF_PF14                     ((uint32_t)0x00004000U)      /*!< Port PF14 Pull-Down set */
-#define   PWR_PDCRF_PF13                     ((uint32_t)0x00002000U)      /*!< Port PF13 Pull-Down set */
-#define   PWR_PDCRF_PF12                     ((uint32_t)0x00001000U)      /*!< Port PF12 Pull-Down set */
-#define   PWR_PDCRF_PF11                     ((uint32_t)0x00000800U)      /*!< Port PF11 Pull-Down set */
-#define   PWR_PDCRF_PF10                     ((uint32_t)0x00000400U)      /*!< Port PF10 Pull-Down set */
-#define   PWR_PDCRF_PF9                      ((uint32_t)0x00000200U)      /*!< Port PF9 Pull-Down set  */
-#define   PWR_PDCRF_PF8                      ((uint32_t)0x00000100U)      /*!< Port PF8 Pull-Down set  */
-#define   PWR_PDCRF_PF7                      ((uint32_t)0x00000080U)      /*!< Port PF7 Pull-Down set  */
-#define   PWR_PDCRF_PF6                      ((uint32_t)0x00000040U)      /*!< Port PF6 Pull-Down set  */
-#define   PWR_PDCRF_PF5                      ((uint32_t)0x00000020U)      /*!< Port PF5 Pull-Down set  */
-#define   PWR_PDCRF_PF4                      ((uint32_t)0x00000010U)      /*!< Port PF4 Pull-Down set  */
-#define   PWR_PDCRF_PF3                      ((uint32_t)0x00000008U)      /*!< Port PF3 Pull-Down set  */
-#define   PWR_PDCRF_PF2                      ((uint32_t)0x00000004U)      /*!< Port PF2 Pull-Down set  */
-#define   PWR_PDCRF_PF1                      ((uint32_t)0x00000002U)      /*!< Port PF1 Pull-Down set  */
-#define   PWR_PDCRF_PF0                      ((uint32_t)0x00000001U)      /*!< Port PF0 Pull-Down set  */
-
-/********************  Bit definition for PWR_PUCRG register  ********************/
-#define   PWR_PUCRG_PG15                     ((uint32_t)0x00008000U)      /*!< Port PG15 Pull-Up set */
-#define   PWR_PUCRG_PG14                     ((uint32_t)0x00004000U)      /*!< Port PG14 Pull-Up set */
-#define   PWR_PUCRG_PG13                     ((uint32_t)0x00002000U)      /*!< Port PG13 Pull-Up set */
-#define   PWR_PUCRG_PG12                     ((uint32_t)0x00001000U)      /*!< Port PG12 Pull-Up set */
-#define   PWR_PUCRG_PG11                     ((uint32_t)0x00000800U)      /*!< Port PG11 Pull-Up set */
-#define   PWR_PUCRG_PG10                     ((uint32_t)0x00000400U)      /*!< Port PG10 Pull-Up set */
-#define   PWR_PUCRG_PG9                      ((uint32_t)0x00000200U)      /*!< Port PG9 Pull-Up set  */
-#define   PWR_PUCRG_PG8                      ((uint32_t)0x00000100U)      /*!< Port PG8 Pull-Up set  */
-#define   PWR_PUCRG_PG7                      ((uint32_t)0x00000080U)      /*!< Port PG7 Pull-Up set  */
-#define   PWR_PUCRG_PG6                      ((uint32_t)0x00000040U)      /*!< Port PG6 Pull-Up set  */
-#define   PWR_PUCRG_PG5                      ((uint32_t)0x00000020U)      /*!< Port PG5 Pull-Up set  */
-#define   PWR_PUCRG_PG4                      ((uint32_t)0x00000010U)      /*!< Port PG4 Pull-Up set  */
-#define   PWR_PUCRG_PG3                      ((uint32_t)0x00000008U)      /*!< Port PG3 Pull-Up set  */
-#define   PWR_PUCRG_PG2                      ((uint32_t)0x00000004U)      /*!< Port PG2 Pull-Up set  */
-#define   PWR_PUCRG_PG1                      ((uint32_t)0x00000002U)      /*!< Port PG1 Pull-Up set  */
-#define   PWR_PUCRG_PG0                      ((uint32_t)0x00000001U)      /*!< Port PG0 Pull-Up set  */
-
-/********************  Bit definition for PWR_PDCRG register  ********************/
-#define   PWR_PDCRG_PG15                     ((uint32_t)0x00008000U)      /*!< Port PG15 Pull-Down set */
-#define   PWR_PDCRG_PG14                     ((uint32_t)0x00004000U)      /*!< Port PG14 Pull-Down set */
-#define   PWR_PDCRG_PG13                     ((uint32_t)0x00002000U)      /*!< Port PG13 Pull-Down set */
-#define   PWR_PDCRG_PG12                     ((uint32_t)0x00001000U)      /*!< Port PG12 Pull-Down set */
-#define   PWR_PDCRG_PG11                     ((uint32_t)0x00000800U)      /*!< Port PG11 Pull-Down set */
-#define   PWR_PDCRG_PG10                     ((uint32_t)0x00000400U)      /*!< Port PG10 Pull-Down set */
-#define   PWR_PDCRG_PG9                      ((uint32_t)0x00000200U)      /*!< Port PG9 Pull-Down set  */
-#define   PWR_PDCRG_PG8                      ((uint32_t)0x00000100U)      /*!< Port PG8 Pull-Down set  */
-#define   PWR_PDCRG_PG7                      ((uint32_t)0x00000080U)      /*!< Port PG7 Pull-Down set  */
-#define   PWR_PDCRG_PG6                      ((uint32_t)0x00000040U)      /*!< Port PG6 Pull-Down set  */
-#define   PWR_PDCRG_PG5                      ((uint32_t)0x00000020U)      /*!< Port PG5 Pull-Down set  */
-#define   PWR_PDCRG_PG4                      ((uint32_t)0x00000010U)      /*!< Port PG4 Pull-Down set  */
-#define   PWR_PDCRG_PG3                      ((uint32_t)0x00000008U)      /*!< Port PG3 Pull-Down set  */
-#define   PWR_PDCRG_PG2                      ((uint32_t)0x00000004U)      /*!< Port PG2 Pull-Down set  */
-#define   PWR_PDCRG_PG1                      ((uint32_t)0x00000002U)      /*!< Port PG1 Pull-Down set  */
-#define   PWR_PDCRG_PG0                      ((uint32_t)0x00000001U)      /*!< Port PG0 Pull-Down set  */
-
-/********************  Bit definition for PWR_PUCRH register  ********************/
-#define   PWR_PUCRH_PH1                      ((uint32_t)0x00000002U)      /*!< Port PH1 Pull-Up set  */
-#define   PWR_PUCRH_PH0                      ((uint32_t)0x00000001U)      /*!< Port PH0 Pull-Up set  */
-
-/********************  Bit definition for PWR_PDCRH register  ********************/
-#define   PWR_PDCRH_PH1                      ((uint32_t)0x00000002U)      /*!< Port PH1 Pull-Down set  */
-#define   PWR_PDCRH_PH0                      ((uint32_t)0x00000001U)      /*!< Port PH0 Pull-Down set  */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions  (not present on all devices in the STM32L4 family)
-*/
-#define RCC_PLLSAI2_SUPPORT
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_MSION                        ((uint32_t)0x00000001U)      /*!< Internal Multi Speed oscillator (MSI) clock enable */
-#define  RCC_CR_MSIRDY                       ((uint32_t)0x00000002U)      /*!< Internal Multi Speed oscillator (MSI) clock ready flag */
-#define  RCC_CR_MSIPLLEN                     ((uint32_t)0x00000004U)      /*!< Internal Multi Speed oscillator (MSI) PLL enable */
-#define  RCC_CR_MSIRGSEL                     ((uint32_t)0x00000008U)      /*!< Internal Multi Speed oscillator (MSI) range selection */
-
-/*!< MSIRANGE configuration : 12 frequency ranges available */
-#define  RCC_CR_MSIRANGE                     ((uint32_t)0x000000F0U)       /*!< Internal Multi Speed oscillator (MSI) clock Range */
-#define  RCC_CR_MSIRANGE_0                   ((uint32_t)0x00000000U)       /*!< Internal Multi Speed oscillator (MSI) clock Range 100 KHz */
-#define  RCC_CR_MSIRANGE_1                   ((uint32_t)0x00000010U)       /*!< Internal Multi Speed oscillator (MSI) clock Range 200 KHz */
-#define  RCC_CR_MSIRANGE_2                   ((uint32_t)0x00000020U)       /*!< Internal Multi Speed oscillator (MSI) clock Range 400 KHz */
-#define  RCC_CR_MSIRANGE_3                   ((uint32_t)0x00000030U)       /*!< Internal Multi Speed oscillator (MSI) clock Range 800 KHz */
-#define  RCC_CR_MSIRANGE_4                   ((uint32_t)0x00000040U)       /*!< Internal Multi Speed oscillator (MSI) clock Range 1 MHz */
-#define  RCC_CR_MSIRANGE_5                   ((uint32_t)0x00000050U)       /*!< Internal Multi Speed oscillator (MSI) clock Range 2 MHz */
-#define  RCC_CR_MSIRANGE_6                   ((uint32_t)0x00000060U)       /*!< Internal Multi Speed oscillator (MSI) clock Range 4  MHz */
-#define  RCC_CR_MSIRANGE_7                   ((uint32_t)0x00000070U)       /*!< Internal Multi Speed oscillator (MSI) clock Range 8 KHz */
-#define  RCC_CR_MSIRANGE_8                   ((uint32_t)0x00000080U)       /*!< Internal Multi Speed oscillator (MSI) clock Range 16 MHz */
-#define  RCC_CR_MSIRANGE_9                   ((uint32_t)0x00000090U)       /*!< Internal Multi Speed oscillator (MSI) clock Range 24 MHz */
-#define  RCC_CR_MSIRANGE_10                  ((uint32_t)0x000000A0U)       /*!< Internal Multi Speed oscillator (MSI) clock Range 32 MHz */
-#define  RCC_CR_MSIRANGE_11                  ((uint32_t)0x000000B0U)       /*!< Internal Multi Speed oscillator (MSI) clock Range 48  MHz */
-
-#define  RCC_CR_HSION                        ((uint32_t)0x00000100U)       /*!< Internal High Speed oscillator (HSI16) clock enable */
-#define  RCC_CR_HSIKERON                     ((uint32_t)0x00000200U)       /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
-#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000400U)       /*!< Internal High Speed oscillator (HSI16) clock ready flag */
-#define  RCC_CR_HSIASFS                      ((uint32_t)0x00000800U)       /*!< HSI16 Automatic Start from Stop */
-
-#define  RCC_CR_HSEON                        ((uint32_t)0x00010000U)       /*!< External High Speed oscillator (HSE) clock enable */
-#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000U)       /*!< External High Speed oscillator (HSE) clock ready */
-#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000U)       /*!< External High Speed oscillator (HSE) clock bypass */
-#define  RCC_CR_CSSON                        ((uint32_t)0x00080000U)       /*!< HSE Clock Security System enable */
-
-#define  RCC_CR_PLLON                        ((uint32_t)0x01000000U)       /*!< System PLL clock enable */
-#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000U)       /*!< System PLL clock ready */
-#define  RCC_CR_PLLSAI1ON                    ((uint32_t)0x04000000U)       /*!< SAI1 PLL enable */
-#define  RCC_CR_PLLSAI1RDY                   ((uint32_t)0x08000000U)       /*!< SAI1 PLL ready */
-#define  RCC_CR_PLLSAI2ON                    ((uint32_t)0x10000000U)       /*!< SAI2 PLL enable */
-#define  RCC_CR_PLLSAI2RDY                   ((uint32_t)0x20000000U)       /*!< SAI2 PLL ready */
-
-/********************  Bit definition for RCC_ICSCR register  ***************/
-/*!< MSICAL configuration */
-#define  RCC_ICSCR_MSICAL                    ((uint32_t)0x000000FFU)       /*!< MSICAL[7:0] bits */
-#define  RCC_ICSCR_MSICAL_0                  ((uint32_t)0x00000001U)       /*!<Bit 0 */
-#define  RCC_ICSCR_MSICAL_1                  ((uint32_t)0x00000002U)       /*!<Bit 1 */
-#define  RCC_ICSCR_MSICAL_2                  ((uint32_t)0x00000004U)       /*!<Bit 2 */
-#define  RCC_ICSCR_MSICAL_3                  ((uint32_t)0x00000008U)       /*!<Bit 3 */
-#define  RCC_ICSCR_MSICAL_4                  ((uint32_t)0x00000010U)       /*!<Bit 4 */
-#define  RCC_ICSCR_MSICAL_5                  ((uint32_t)0x00000020U)       /*!<Bit 5 */
-#define  RCC_ICSCR_MSICAL_6                  ((uint32_t)0x00000040U)       /*!<Bit 6 */
-#define  RCC_ICSCR_MSICAL_7                  ((uint32_t)0x00000080U)       /*!<Bit 7 */
-
-/*!< MSITRIM configuration */
-#define  RCC_ICSCR_MSITRIM                   ((uint32_t)0x0000FF00U)       /*!< MSITRIM[7:0] bits */
-#define  RCC_ICSCR_MSITRIM_0                 ((uint32_t)0x00000100U)       /*!<Bit 0 */
-#define  RCC_ICSCR_MSITRIM_1                 ((uint32_t)0x00000200U)       /*!<Bit 1 */
-#define  RCC_ICSCR_MSITRIM_2                 ((uint32_t)0x00000400U)       /*!<Bit 2 */
-#define  RCC_ICSCR_MSITRIM_3                 ((uint32_t)0x00000800U)       /*!<Bit 3 */
-#define  RCC_ICSCR_MSITRIM_4                 ((uint32_t)0x00001000U)       /*!<Bit 4 */
-#define  RCC_ICSCR_MSITRIM_5                 ((uint32_t)0x00002000U)       /*!<Bit 5 */
-#define  RCC_ICSCR_MSITRIM_6                 ((uint32_t)0x00004000U)       /*!<Bit 6 */
-#define  RCC_ICSCR_MSITRIM_7                 ((uint32_t)0x00008000U)       /*!<Bit 7 */
-
-/*!< HSICAL configuration */
-#define  RCC_ICSCR_HSICAL                    ((uint32_t)0x00FF0000U)       /*!< HSICAL[7:0] bits */
-#define  RCC_ICSCR_HSICAL_0                  ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  RCC_ICSCR_HSICAL_1                  ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  RCC_ICSCR_HSICAL_2                  ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  RCC_ICSCR_HSICAL_3                  ((uint32_t)0x00080000U)        /*!<Bit 3 */
-#define  RCC_ICSCR_HSICAL_4                  ((uint32_t)0x00100000U)        /*!<Bit 4 */
-#define  RCC_ICSCR_HSICAL_5                  ((uint32_t)0x00200000U)        /*!<Bit 5 */
-#define  RCC_ICSCR_HSICAL_6                  ((uint32_t)0x00400000U)        /*!<Bit 6 */
-#define  RCC_ICSCR_HSICAL_7                  ((uint32_t)0x00800000U)        /*!<Bit 7 */
-
-/*!< HSITRIM configuration */
-#define  RCC_ICSCR_HSITRIM                   ((uint32_t)0x1F000000U)       /*!< HSITRIM[4:0] bits */
-#define  RCC_ICSCR_HSITRIM_0                 ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  RCC_ICSCR_HSITRIM_1                 ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  RCC_ICSCR_HSITRIM_2                 ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  RCC_ICSCR_HSITRIM_3                 ((uint32_t)0x08000000U)        /*!<Bit 3 */
-#define  RCC_ICSCR_HSITRIM_4                 ((uint32_t)0x10000000U)        /*!<Bit 4 */
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-/*!< SW configuration */
-#define  RCC_CFGR_SW                         ((uint32_t)0x00000003U)      /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001U)      /*!<Bit 0 */
-#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002U)      /*!<Bit 1 */
-
-#define  RCC_CFGR_SW_MSI                     ((uint32_t)0x00000000U)      /*!< MSI oscillator selection as system clock */
-#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000001U)      /*!< HSI16 oscillator selection as system clock */
-#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000002U)      /*!< HSE oscillator selection as system clock */
-#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000003U)      /*!< PLL selection as system clock */
-
-/*!< SWS configuration */
-#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000CU)      /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004U)      /*!<Bit 0 */
-#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008U)      /*!<Bit 1 */
-
-#define  RCC_CFGR_SWS_MSI                    ((uint32_t)0x00000000U)      /*!< MSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000004U)      /*!< HSI16 oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000008U)      /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x0000000CU)      /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0U)      /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010U)      /*!<Bit 0 */
-#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020U)      /*!<Bit 1 */
-#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040U)      /*!<Bit 2 */
-#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080U)      /*!<Bit 3 */
-
-#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000U)      /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080U)      /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090U)      /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0U)      /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0U)      /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0U)      /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0U)      /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0U)      /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0U)      /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00000700U)      /*!< PRE1[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000100U)      /*!<Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000200U)      /*!<Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00000400U)      /*!<Bit 2 */
-
-#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000U)      /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00000400U)      /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00000500U)      /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00000600U)      /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00000700U)      /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      ((uint32_t)0x00003800U)      /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00000800U)      /*!<Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00001000U)      /*!<Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00002000U)      /*!<Bit 2 */
-
-#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000U)      /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00002000U)      /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x00002800U)      /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x00003000U)      /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x00003800U)      /*!< HCLK divided by 16 */
-
-#define  RCC_CFGR_STOPWUCK                   ((uint32_t)0x00008000U)      /*!< Wake Up from stop and CSS backup clock selection */
-
-/*!< MCOSEL configuration */
-#define  RCC_CFGR_MCOSEL                     ((uint32_t)0x07000000U)      /*!< MCOSEL [2:0] bits (Clock output selection) */
-#define  RCC_CFGR_MCOSEL_0                   ((uint32_t)0x01000000U)      /*!<Bit 0 */
-#define  RCC_CFGR_MCOSEL_1                   ((uint32_t)0x02000000U)      /*!<Bit 1 */
-#define  RCC_CFGR_MCOSEL_2                   ((uint32_t)0x04000000U)      /*!<Bit 2 */
-
-#define  RCC_CFGR_MCOPRE                     ((uint32_t)0x70000000U)      /*!< MCO prescaler */
-#define  RCC_CFGR_MCOPRE_0                   ((uint32_t)0x10000000U)      /*!<Bit 0 */
-#define  RCC_CFGR_MCOPRE_1                   ((uint32_t)0x20000000U)      /*!<Bit 1 */
-#define  RCC_CFGR_MCOPRE_2                   ((uint32_t)0x40000000U)      /*!<Bit 2 */
- 
-#define  RCC_CFGR_MCOPRE_DIV1                ((uint32_t)0x00000000U)      /*!< MCO is divided by 1 */
-#define  RCC_CFGR_MCOPRE_DIV2                ((uint32_t)0x10000000U)      /*!< MCO is divided by 2 */
-#define  RCC_CFGR_MCOPRE_DIV4                ((uint32_t)0x20000000U)      /*!< MCO is divided by 4 */
-#define  RCC_CFGR_MCOPRE_DIV8                ((uint32_t)0x30000000U)      /*!< MCO is divided by 8 */
-#define  RCC_CFGR_MCOPRE_DIV16               ((uint32_t)0x40000000U)      /*!< MCO is divided by 16 */
- 
-/* Legacy aliases */
-#define  RCC_CFGR_MCO_PRE                    RCC_CFGR_MCOPRE
-#define  RCC_CFGR_MCO_PRE_1                  RCC_CFGR_MCOPRE_DIV1
-#define  RCC_CFGR_MCO_PRE_2                  RCC_CFGR_MCOPRE_DIV2
-#define  RCC_CFGR_MCO_PRE_4                  RCC_CFGR_MCOPRE_DIV4
-#define  RCC_CFGR_MCO_PRE_8                  RCC_CFGR_MCOPRE_DIV8
-#define  RCC_CFGR_MCO_PRE_16                 RCC_CFGR_MCOPRE_DIV16
-
-/********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLSRC                  ((uint32_t)0x00000003U)
-
-#define  RCC_PLLCFGR_PLLSRC_MSI              ((uint32_t)0x00000001U)      /*!< MSI oscillator source clock selected */
-#define  RCC_PLLCFGR_PLLSRC_HSI              ((uint32_t)0x00000002U)      /*!< HSI16 oscillator source clock selected */
-#define  RCC_PLLCFGR_PLLSRC_HSE              ((uint32_t)0x00000003U)      /*!< HSE oscillator source clock selected */
-
-#define  RCC_PLLCFGR_PLLM                    ((uint32_t)0x00000070U)
-#define  RCC_PLLCFGR_PLLM_0                  ((uint32_t)0x00000010U)
-#define  RCC_PLLCFGR_PLLM_1                  ((uint32_t)0x00000020U)
-#define  RCC_PLLCFGR_PLLM_2                  ((uint32_t)0x00000040U)
-
-#define  RCC_PLLCFGR_PLLN                    ((uint32_t)0x00007F00U)
-#define  RCC_PLLCFGR_PLLN_0                  ((uint32_t)0x00000100U)
-#define  RCC_PLLCFGR_PLLN_1                  ((uint32_t)0x00000200U)
-#define  RCC_PLLCFGR_PLLN_2                  ((uint32_t)0x00000400U)
-#define  RCC_PLLCFGR_PLLN_3                  ((uint32_t)0x00000800U)
-#define  RCC_PLLCFGR_PLLN_4                  ((uint32_t)0x00001000U)
-#define  RCC_PLLCFGR_PLLN_5                  ((uint32_t)0x00002000U)
-#define  RCC_PLLCFGR_PLLN_6                  ((uint32_t)0x00004000U)
-
-#define  RCC_PLLCFGR_PLLPEN                  ((uint32_t)0x00010000U)
-#define  RCC_PLLCFGR_PLLP                    ((uint32_t)0x00020000U)
-#define  RCC_PLLCFGR_PLLQEN                  ((uint32_t)0x00100000U)
-
-#define  RCC_PLLCFGR_PLLQ                    ((uint32_t)0x00600000U)
-#define  RCC_PLLCFGR_PLLQ_0                  ((uint32_t)0x00200000U)
-#define  RCC_PLLCFGR_PLLQ_1                  ((uint32_t)0x00400000U)
-
-#define  RCC_PLLCFGR_PLLREN                  ((uint32_t)0x01000000U)
-#define  RCC_PLLCFGR_PLLR                    ((uint32_t)0x06000000U)
-#define  RCC_PLLCFGR_PLLR_0                  ((uint32_t)0x02000000U)
-#define  RCC_PLLCFGR_PLLR_1                  ((uint32_t)0x04000000U)
-
-/********************  Bit definition for RCC_PLLSAI1CFGR register  ************/
-#define  RCC_PLLSAI1CFGR_PLLSAI1N            ((uint32_t)0x00007F00U)
-#define  RCC_PLLSAI1CFGR_PLLSAI1N_0          ((uint32_t)0x00000100U)
-#define  RCC_PLLSAI1CFGR_PLLSAI1N_1          ((uint32_t)0x00000200U)
-#define  RCC_PLLSAI1CFGR_PLLSAI1N_2          ((uint32_t)0x00000400U)
-#define  RCC_PLLSAI1CFGR_PLLSAI1N_3          ((uint32_t)0x00000800U)
-#define  RCC_PLLSAI1CFGR_PLLSAI1N_4          ((uint32_t)0x00001000U)
-#define  RCC_PLLSAI1CFGR_PLLSAI1N_5          ((uint32_t)0x00002000U)
-#define  RCC_PLLSAI1CFGR_PLLSAI1N_6          ((uint32_t)0x00004000U)
-
-#define  RCC_PLLSAI1CFGR_PLLSAI1PEN          ((uint32_t)0x00010000U)
-#define  RCC_PLLSAI1CFGR_PLLSAI1P            ((uint32_t)0x00020000U)
-
-#define  RCC_PLLSAI1CFGR_PLLSAI1QEN          ((uint32_t)0x00100000U)
-#define  RCC_PLLSAI1CFGR_PLLSAI1Q            ((uint32_t)0x00600000U)
-#define  RCC_PLLSAI1CFGR_PLLSAI1Q_0          ((uint32_t)0x00200000U)
-#define  RCC_PLLSAI1CFGR_PLLSAI1Q_1          ((uint32_t)0x00400000U)
-
-#define  RCC_PLLSAI1CFGR_PLLSAI1REN          ((uint32_t)0x01000000U)
-#define  RCC_PLLSAI1CFGR_PLLSAI1R            ((uint32_t)0x06000000U)
-#define  RCC_PLLSAI1CFGR_PLLSAI1R_0          ((uint32_t)0x02000000U)
-#define  RCC_PLLSAI1CFGR_PLLSAI1R_1          ((uint32_t)0x04000000U)
-
-/********************  Bit definition for RCC_PLLSAI2CFGR register  ************/
-#define  RCC_PLLSAI2CFGR_PLLSAI2N            ((uint32_t)0x00007F00U)
-#define  RCC_PLLSAI2CFGR_PLLSAI2N_0          ((uint32_t)0x00000100U)
-#define  RCC_PLLSAI2CFGR_PLLSAI2N_1          ((uint32_t)0x00000200U)
-#define  RCC_PLLSAI2CFGR_PLLSAI2N_2          ((uint32_t)0x00000400U)
-#define  RCC_PLLSAI2CFGR_PLLSAI2N_3          ((uint32_t)0x00000800U)
-#define  RCC_PLLSAI2CFGR_PLLSAI2N_4          ((uint32_t)0x00001000U)
-#define  RCC_PLLSAI2CFGR_PLLSAI2N_5          ((uint32_t)0x00002000U)
-#define  RCC_PLLSAI2CFGR_PLLSAI2N_6          ((uint32_t)0x00004000U)
-
-#define  RCC_PLLSAI2CFGR_PLLSAI2PEN          ((uint32_t)0x00010000U)
-#define  RCC_PLLSAI2CFGR_PLLSAI2P            ((uint32_t)0x00020000U)
-
-#define  RCC_PLLSAI2CFGR_PLLSAI2REN          ((uint32_t)0x01000000U)
-#define  RCC_PLLSAI2CFGR_PLLSAI2R            ((uint32_t)0x06000000U)
-#define  RCC_PLLSAI2CFGR_PLLSAI2R_0          ((uint32_t)0x02000000U)
-#define  RCC_PLLSAI2CFGR_PLLSAI2R_1          ((uint32_t)0x04000000U)
-
-/********************  Bit definition for RCC_CIER register  ******************/
-#define  RCC_CIER_LSIRDYIE                   ((uint32_t)0x00000001U)
-#define  RCC_CIER_LSERDYIE                   ((uint32_t)0x00000002U)
-#define  RCC_CIER_MSIRDYIE                   ((uint32_t)0x00000004U)
-#define  RCC_CIER_HSIRDYIE                   ((uint32_t)0x00000008U)
-#define  RCC_CIER_HSERDYIE                   ((uint32_t)0x00000010U)
-#define  RCC_CIER_PLLRDYIE                   ((uint32_t)0x00000020U)
-#define  RCC_CIER_PLLSAI1RDYIE               ((uint32_t)0x00000040U)
-#define  RCC_CIER_PLLSAI2RDYIE               ((uint32_t)0x00000080U)
-#define  RCC_CIER_LSECSSIE                   ((uint32_t)0x00000200U)
-
-/********************  Bit definition for RCC_CIFR register  ******************/
-#define  RCC_CIFR_LSIRDYF                    ((uint32_t)0x00000001U)
-#define  RCC_CIFR_LSERDYF                    ((uint32_t)0x00000002U)
-#define  RCC_CIFR_MSIRDYF                    ((uint32_t)0x00000004U)
-#define  RCC_CIFR_HSIRDYF                    ((uint32_t)0x00000008U)
-#define  RCC_CIFR_HSERDYF                    ((uint32_t)0x00000010U)
-#define  RCC_CIFR_PLLRDYF                    ((uint32_t)0x00000020U)
-#define  RCC_CIFR_PLLSAI1RDYF                ((uint32_t)0x00000040U)
-#define  RCC_CIFR_PLLSAI2RDYF                ((uint32_t)0x00000080U)
-#define  RCC_CIFR_CSSF                       ((uint32_t)0x00000100U)
-#define  RCC_CIFR_LSECSSF                    ((uint32_t)0x00000200U)
-
-/********************  Bit definition for RCC_CICR register  ******************/
-#define  RCC_CICR_LSIRDYC                    ((uint32_t)0x00000001U)
-#define  RCC_CICR_LSERDYC                    ((uint32_t)0x00000002U)
-#define  RCC_CICR_MSIRDYC                    ((uint32_t)0x00000004U)
-#define  RCC_CICR_HSIRDYC                    ((uint32_t)0x00000008U)
-#define  RCC_CICR_HSERDYC                    ((uint32_t)0x00000010U)
-#define  RCC_CICR_PLLRDYC                    ((uint32_t)0x00000020U)
-#define  RCC_CICR_PLLSAI1RDYC                ((uint32_t)0x00000040U)
-#define  RCC_CICR_PLLSAI2RDYC                ((uint32_t)0x00000080U)
-#define  RCC_CICR_CSSC                       ((uint32_t)0x00000100U)
-#define  RCC_CICR_LSECSSC                    ((uint32_t)0x00000200U)
-
-/********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_DMA1RST                ((uint32_t)0x00000001U)
-#define  RCC_AHB1RSTR_DMA2RST                ((uint32_t)0x00000002U)
-#define  RCC_AHB1RSTR_FLASHRST               ((uint32_t)0x00000100U)
-#define  RCC_AHB1RSTR_CRCRST                 ((uint32_t)0x00001000U)
-#define  RCC_AHB1RSTR_TSCRST                 ((uint32_t)0x00010000U)
-
-/********************  Bit definition for RCC_AHB2RSTR register  **************/
-#define  RCC_AHB2RSTR_GPIOARST               ((uint32_t)0x00000001U)
-#define  RCC_AHB2RSTR_GPIOBRST               ((uint32_t)0x00000002U)
-#define  RCC_AHB2RSTR_GPIOCRST               ((uint32_t)0x00000004U)
-#define  RCC_AHB2RSTR_GPIODRST               ((uint32_t)0x00000008U)
-#define  RCC_AHB2RSTR_GPIOERST               ((uint32_t)0x00000010U)
-#define  RCC_AHB2RSTR_GPIOFRST               ((uint32_t)0x00000020U)
-#define  RCC_AHB2RSTR_GPIOGRST               ((uint32_t)0x00000040U)
-#define  RCC_AHB2RSTR_GPIOHRST               ((uint32_t)0x00000080U)
-#define  RCC_AHB2RSTR_OTGFSRST               ((uint32_t)0x00001000U)
-#define  RCC_AHB2RSTR_ADCRST                 ((uint32_t)0x00002000U)
-#define  RCC_AHB2RSTR_RNGRST                 ((uint32_t)0x00040000U)
-
-/********************  Bit definition for RCC_AHB3RSTR register  **************/
-#define  RCC_AHB3RSTR_FMCRST                 ((uint32_t)0x00000001U)
-#define  RCC_AHB3RSTR_QSPIRST                ((uint32_t)0x00000100U)
-
-/********************  Bit definition for RCC_APB1RSTR1 register  **************/
-#define  RCC_APB1RSTR1_TIM2RST               ((uint32_t)0x00000001U)
-#define  RCC_APB1RSTR1_TIM3RST               ((uint32_t)0x00000002U)
-#define  RCC_APB1RSTR1_TIM4RST               ((uint32_t)0x00000004U)
-#define  RCC_APB1RSTR1_TIM5RST               ((uint32_t)0x00000008U)
-#define  RCC_APB1RSTR1_TIM6RST               ((uint32_t)0x00000010U)
-#define  RCC_APB1RSTR1_TIM7RST               ((uint32_t)0x00000020U)
-#define  RCC_APB1RSTR1_LCDRST                ((uint32_t)0x00000200U)
-#define  RCC_APB1RSTR1_SPI2RST               ((uint32_t)0x00004000U)
-#define  RCC_APB1RSTR1_SPI3RST               ((uint32_t)0x00008000U)
-#define  RCC_APB1RSTR1_USART2RST             ((uint32_t)0x00020000U)
-#define  RCC_APB1RSTR1_USART3RST             ((uint32_t)0x00040000U)
-#define  RCC_APB1RSTR1_UART4RST              ((uint32_t)0x00080000U)
-#define  RCC_APB1RSTR1_UART5RST              ((uint32_t)0x00100000U)
-#define  RCC_APB1RSTR1_I2C1RST               ((uint32_t)0x00200000U)
-#define  RCC_APB1RSTR1_I2C2RST               ((uint32_t)0x00400000U)
-#define  RCC_APB1RSTR1_I2C3RST               ((uint32_t)0x00800000U)
-#define  RCC_APB1RSTR1_CAN1RST               ((uint32_t)0x02000000U)
-#define  RCC_APB1RSTR1_PWRRST                ((uint32_t)0x10000000U)
-#define  RCC_APB1RSTR1_DAC1RST               ((uint32_t)0x20000000U)
-#define  RCC_APB1RSTR1_OPAMPRST              ((uint32_t)0x40000000U)
-#define  RCC_APB1RSTR1_LPTIM1RST             ((uint32_t)0x80000000U)
-
-/********************  Bit definition for RCC_APB1RSTR2 register  **************/
-#define  RCC_APB1RSTR2_LPUART1RST            ((uint32_t)0x00000001U)
-#define  RCC_APB1RSTR2_SWPMI1RST             ((uint32_t)0x00000004U)
-#define  RCC_APB1RSTR2_LPTIM2RST             ((uint32_t)0x00000020U)
-
-/********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00000001U)
-#define  RCC_APB2RSTR_SDMMC1RST              ((uint32_t)0x00000400U)
-#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000800U)
-#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000U)
-#define  RCC_APB2RSTR_TIM8RST                ((uint32_t)0x00002000U)
-#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00004000U)
-#define  RCC_APB2RSTR_TIM15RST               ((uint32_t)0x00010000U)
-#define  RCC_APB2RSTR_TIM16RST               ((uint32_t)0x00020000U)
-#define  RCC_APB2RSTR_TIM17RST               ((uint32_t)0x00040000U)
-#define  RCC_APB2RSTR_SAI1RST                ((uint32_t)0x00200000U)
-#define  RCC_APB2RSTR_SAI2RST                ((uint32_t)0x00400000U)
-#define  RCC_APB2RSTR_DFSDMRST               ((uint32_t)0x01000000U)
-
-/********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_DMA1EN                  ((uint32_t)0x00000001U)
-#define  RCC_AHB1ENR_DMA2EN                  ((uint32_t)0x00000002U)
-#define  RCC_AHB1ENR_FLASHEN                 ((uint32_t)0x00000100U)
-#define  RCC_AHB1ENR_CRCEN                   ((uint32_t)0x00001000U)
-#define  RCC_AHB1ENR_TSCEN                   ((uint32_t)0x00010000U)
-
-/********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define  RCC_AHB2ENR_GPIOAEN                 ((uint32_t)0x00000001U)
-#define  RCC_AHB2ENR_GPIOBEN                 ((uint32_t)0x00000002U)
-#define  RCC_AHB2ENR_GPIOCEN                 ((uint32_t)0x00000004U)
-#define  RCC_AHB2ENR_GPIODEN                 ((uint32_t)0x00000008U)
-#define  RCC_AHB2ENR_GPIOEEN                 ((uint32_t)0x00000010U)
-#define  RCC_AHB2ENR_GPIOFEN                 ((uint32_t)0x00000020U)
-#define  RCC_AHB2ENR_GPIOGEN                 ((uint32_t)0x00000040U)
-#define  RCC_AHB2ENR_GPIOHEN                 ((uint32_t)0x00000080U)
-#define  RCC_AHB2ENR_OTGFSEN                 ((uint32_t)0x00001000U)
-#define  RCC_AHB2ENR_ADCEN                   ((uint32_t)0x00002000U)
-#define  RCC_AHB2ENR_RNGEN                   ((uint32_t)0x00040000U)
-
-/********************  Bit definition for RCC_AHB3ENR register  ***************/
-#define  RCC_AHB3ENR_FMCEN                   ((uint32_t)0x00000001U)
-#define  RCC_AHB3ENR_QSPIEN                  ((uint32_t)0x00000100U)
-
-/********************  Bit definition for RCC_APB1ENR1 register  ***************/
-#define  RCC_APB1ENR1_TIM2EN                 ((uint32_t)0x00000001U)
-#define  RCC_APB1ENR1_TIM3EN                 ((uint32_t)0x00000002U)
-#define  RCC_APB1ENR1_TIM4EN                 ((uint32_t)0x00000004U)
-#define  RCC_APB1ENR1_TIM5EN                 ((uint32_t)0x00000008U)
-#define  RCC_APB1ENR1_TIM6EN                 ((uint32_t)0x00000010U)
-#define  RCC_APB1ENR1_TIM7EN                 ((uint32_t)0x00000020U)
-#define  RCC_APB1ENR1_LCDEN                  ((uint32_t)0x00000200U)
-#define  RCC_APB1ENR1_WWDGEN                 ((uint32_t)0x00000800U)
-#define  RCC_APB1ENR1_SPI2EN                 ((uint32_t)0x00004000U)
-#define  RCC_APB1ENR1_SPI3EN                 ((uint32_t)0x00008000U)
-#define  RCC_APB1ENR1_USART2EN               ((uint32_t)0x00020000U)
-#define  RCC_APB1ENR1_USART3EN               ((uint32_t)0x00040000U)
-#define  RCC_APB1ENR1_UART4EN                ((uint32_t)0x00080000U)
-#define  RCC_APB1ENR1_UART5EN                ((uint32_t)0x00100000U)
-#define  RCC_APB1ENR1_I2C1EN                 ((uint32_t)0x00200000U)
-#define  RCC_APB1ENR1_I2C2EN                 ((uint32_t)0x00400000U)
-#define  RCC_APB1ENR1_I2C3EN                 ((uint32_t)0x00800000U)
-#define  RCC_APB1ENR1_CAN1EN                 ((uint32_t)0x02000000U)
-#define  RCC_APB1ENR1_PWREN                  ((uint32_t)0x10000000U)
-#define  RCC_APB1ENR1_DAC1EN                 ((uint32_t)0x20000000U)
-#define  RCC_APB1ENR1_OPAMPEN                ((uint32_t)0x40000000U)
-#define  RCC_APB1ENR1_LPTIM1EN               ((uint32_t)0x80000000U)
-
-/********************  Bit definition for RCC_APB1RSTR2 register  **************/
-#define  RCC_APB1ENR2_LPUART1EN              ((uint32_t)0x00000001U)
-#define  RCC_APB1ENR2_SWPMI1EN               ((uint32_t)0x00000004U)
-#define  RCC_APB1ENR2_LPTIM2EN               ((uint32_t)0x00000020U)
-
-/********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00000001U)
-#define  RCC_APB2ENR_FWEN                    ((uint32_t)0x00000080U)
-#define  RCC_APB2ENR_SDMMC1EN                ((uint32_t)0x00000400U)
-#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000800U)
-#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000U)
-#define  RCC_APB2ENR_TIM8EN                  ((uint32_t)0x00002000U)
-#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00004000U)
-#define  RCC_APB2ENR_TIM15EN                 ((uint32_t)0x00010000U)
-#define  RCC_APB2ENR_TIM16EN                 ((uint32_t)0x00020000U)
-#define  RCC_APB2ENR_TIM17EN                 ((uint32_t)0x00040000U)
-#define  RCC_APB2ENR_SAI1EN                  ((uint32_t)0x00200000U)
-#define  RCC_APB2ENR_SAI2EN                  ((uint32_t)0x00400000U)
-#define  RCC_APB2ENR_DFSDMEN                 ((uint32_t)0x01000000U)
-
-/********************  Bit definition for RCC_AHB1SMENR register  ***************/
-#define  RCC_AHB1SMENR_DMA1SMEN              ((uint32_t)0x00000001U)
-#define  RCC_AHB1SMENR_DMA2SMEN              ((uint32_t)0x00000002U)
-#define  RCC_AHB1SMENR_FLASHSMEN             ((uint32_t)0x00000100U)
-#define  RCC_AHB1SMENR_SRAM1SMEN             ((uint32_t)0x00000200U)
-#define  RCC_AHB1SMENR_CRCSMEN               ((uint32_t)0x00001000U)
-#define  RCC_AHB1SMENR_TSCSMEN               ((uint32_t)0x00010000U)
-
-/********************  Bit definition for RCC_AHB2SMENR register  *************/
-#define  RCC_AHB2SMENR_GPIOASMEN             ((uint32_t)0x00000001U)
-#define  RCC_AHB2SMENR_GPIOBSMEN             ((uint32_t)0x00000002U)
-#define  RCC_AHB2SMENR_GPIOCSMEN             ((uint32_t)0x00000004U)
-#define  RCC_AHB2SMENR_GPIODSMEN             ((uint32_t)0x00000008U)
-#define  RCC_AHB2SMENR_GPIOESMEN             ((uint32_t)0x00000010U)
-#define  RCC_AHB2SMENR_GPIOFSMEN             ((uint32_t)0x00000020U)
-#define  RCC_AHB2SMENR_GPIOGSMEN             ((uint32_t)0x00000040U)
-#define  RCC_AHB2SMENR_GPIOHSMEN             ((uint32_t)0x00000080U)
-#define  RCC_AHB2SMENR_SRAM2SMEN             ((uint32_t)0x00000200U)
-#define  RCC_AHB2SMENR_OTGFSSMEN             ((uint32_t)0x00001000U)
-#define  RCC_AHB2SMENR_ADCSMEN               ((uint32_t)0x00002000U)
-#define  RCC_AHB2SMENR_RNGSMEN               ((uint32_t)0x00040000U)
-
-/********************  Bit definition for RCC_AHB3SMENR register  *************/
-#define  RCC_AHB3SMENR_FMCSMEN               ((uint32_t)0x00000001U)
-#define  RCC_AHB3SMENR_QSPISMEN              ((uint32_t)0x00000100U)
-
-/********************  Bit definition for RCC_APB1SMENR1 register  *************/
-#define  RCC_APB1SMENR1_TIM2SMEN             ((uint32_t)0x00000001U)
-#define  RCC_APB1SMENR1_TIM3SMEN             ((uint32_t)0x00000002U)
-#define  RCC_APB1SMENR1_TIM4SMEN             ((uint32_t)0x00000004U)
-#define  RCC_APB1SMENR1_TIM5SMEN             ((uint32_t)0x00000008U)
-#define  RCC_APB1SMENR1_TIM6SMEN             ((uint32_t)0x00000010U)
-#define  RCC_APB1SMENR1_TIM7SMEN             ((uint32_t)0x00000020U)
-#define  RCC_APB1SMENR1_LCDSMEN              ((uint32_t)0x00000200U)
-#define  RCC_APB1SMENR1_WWDGSMEN             ((uint32_t)0x00000800U)
-#define  RCC_APB1SMENR1_SPI2SMEN             ((uint32_t)0x00004000U)
-#define  RCC_APB1SMENR1_SPI3SMEN             ((uint32_t)0x00008000U)
-#define  RCC_APB1SMENR1_USART2SMEN           ((uint32_t)0x00020000U)
-#define  RCC_APB1SMENR1_USART3SMEN           ((uint32_t)0x00040000U)
-#define  RCC_APB1SMENR1_UART4SMEN            ((uint32_t)0x00080000U)
-#define  RCC_APB1SMENR1_UART5SMEN            ((uint32_t)0x00100000U)
-#define  RCC_APB1SMENR1_I2C1SMEN             ((uint32_t)0x00200000U)
-#define  RCC_APB1SMENR1_I2C2SMEN             ((uint32_t)0x00400000U)
-#define  RCC_APB1SMENR1_I2C3SMEN             ((uint32_t)0x00800000U)
-#define  RCC_APB1SMENR1_CAN1SMEN             ((uint32_t)0x02000000U)
-#define  RCC_APB1SMENR1_PWRSMEN              ((uint32_t)0x10000000U)
-#define  RCC_APB1SMENR1_DAC1SMEN             ((uint32_t)0x20000000U)
-#define  RCC_APB1SMENR1_OPAMPSMEN            ((uint32_t)0x40000000U)
-#define  RCC_APB1SMENR1_LPTIM1SMEN           ((uint32_t)0x80000000U)
-
-/********************  Bit definition for RCC_APB1SMENR2 register  *************/
-#define  RCC_APB1SMENR2_LPUART1SMEN          ((uint32_t)0x00000001U)
-#define  RCC_APB1SMENR2_SWPMI1SMEN           ((uint32_t)0x00000004U)
-#define  RCC_APB1SMENR2_LPTIM2SMEN           ((uint32_t)0x00000020U)
-
-/********************  Bit definition for RCC_APB2SMENR register  *************/
-#define  RCC_APB2SMENR_SYSCFGSMEN            ((uint32_t)0x00000001U)
-#define  RCC_APB2SMENR_SDMMC1SMEN            ((uint32_t)0x00000400U)
-#define  RCC_APB2SMENR_TIM1SMEN              ((uint32_t)0x00000800U)
-#define  RCC_APB2SMENR_SPI1SMEN              ((uint32_t)0x00001000U)
-#define  RCC_APB2SMENR_TIM8SMEN              ((uint32_t)0x00002000U)
-#define  RCC_APB2SMENR_USART1SMEN            ((uint32_t)0x00004000U)
-#define  RCC_APB2SMENR_TIM15SMEN             ((uint32_t)0x00010000U)
-#define  RCC_APB2SMENR_TIM16SMEN             ((uint32_t)0x00020000U)
-#define  RCC_APB2SMENR_TIM17SMEN             ((uint32_t)0x00040000U)
-#define  RCC_APB2SMENR_SAI1SMEN              ((uint32_t)0x00200000U)
-#define  RCC_APB2SMENR_SAI2SMEN              ((uint32_t)0x00400000U)
-#define  RCC_APB2SMENR_DFSDMSMEN             ((uint32_t)0x01000000U)
-
-/********************  Bit definition for RCC_CCIPR register  ******************/
-#define  RCC_CCIPR_USART1SEL                 ((uint32_t)0x00000003U)
-#define  RCC_CCIPR_USART1SEL_0               ((uint32_t)0x00000001U)
-#define  RCC_CCIPR_USART1SEL_1               ((uint32_t)0x00000002U)
-
-#define  RCC_CCIPR_USART2SEL                 ((uint32_t)0x0000000CU)
-#define  RCC_CCIPR_USART2SEL_0               ((uint32_t)0x00000004U)
-#define  RCC_CCIPR_USART2SEL_1               ((uint32_t)0x00000008U)
-
-#define  RCC_CCIPR_USART3SEL                 ((uint32_t)0x00000030U)
-#define  RCC_CCIPR_USART3SEL_0               ((uint32_t)0x00000010U)
-#define  RCC_CCIPR_USART3SEL_1               ((uint32_t)0x00000020U)
-
-#define  RCC_CCIPR_UART4SEL                  ((uint32_t)0x000000C0U)
-#define  RCC_CCIPR_UART4SEL_0                ((uint32_t)0x00000040U)
-#define  RCC_CCIPR_UART4SEL_1                ((uint32_t)0x00000080U)
-
-#define  RCC_CCIPR_UART5SEL                  ((uint32_t)0x00000300U)
-#define  RCC_CCIPR_UART5SEL_0                ((uint32_t)0x00000100U)
-#define  RCC_CCIPR_UART5SEL_1                ((uint32_t)0x00000200U)
-
-#define  RCC_CCIPR_LPUART1SEL                ((uint32_t)0x00000C00U)
-#define  RCC_CCIPR_LPUART1SEL_0              ((uint32_t)0x00000400U)
-#define  RCC_CCIPR_LPUART1SEL_1              ((uint32_t)0x00000800U)
-
-#define  RCC_CCIPR_I2C1SEL                   ((uint32_t)0x00003000U)
-#define  RCC_CCIPR_I2C1SEL_0                 ((uint32_t)0x00001000U)
-#define  RCC_CCIPR_I2C1SEL_1                 ((uint32_t)0x00002000U)
-
-#define  RCC_CCIPR_I2C2SEL                   ((uint32_t)0x0000C000U)
-#define  RCC_CCIPR_I2C2SEL_0                 ((uint32_t)0x00004000U)
-#define  RCC_CCIPR_I2C2SEL_1                 ((uint32_t)0x00008000U)
-
-#define  RCC_CCIPR_I2C3SEL                   ((uint32_t)0x00030000U)
-#define  RCC_CCIPR_I2C3SEL_0                 ((uint32_t)0x00010000U)
-#define  RCC_CCIPR_I2C3SEL_1                 ((uint32_t)0x00020000U)
-
-#define  RCC_CCIPR_LPTIM1SEL                 ((uint32_t)0x000C0000U)
-#define  RCC_CCIPR_LPTIM1SEL_0               ((uint32_t)0x00040000U)
-#define  RCC_CCIPR_LPTIM1SEL_1               ((uint32_t)0x00080000U)
-
-#define  RCC_CCIPR_LPTIM2SEL                 ((uint32_t)0x00300000U)
-#define  RCC_CCIPR_LPTIM2SEL_0               ((uint32_t)0x00100000U)
-#define  RCC_CCIPR_LPTIM2SEL_1               ((uint32_t)0x00200000U)
-
-#define  RCC_CCIPR_SAI1SEL                   ((uint32_t)0x00C00000U)
-#define  RCC_CCIPR_SAI1SEL_0                 ((uint32_t)0x00400000U)
-#define  RCC_CCIPR_SAI1SEL_1                 ((uint32_t)0x00800000U)
-
-#define  RCC_CCIPR_SAI2SEL                   ((uint32_t)0x03000000U)
-#define  RCC_CCIPR_SAI2SEL_0                 ((uint32_t)0x01000000U)
-#define  RCC_CCIPR_SAI2SEL_1                 ((uint32_t)0x02000000U)
-
-#define  RCC_CCIPR_CLK48SEL                  ((uint32_t)0x0C000000U)
-#define  RCC_CCIPR_CLK48SEL_0                ((uint32_t)0x04000000U)
-#define  RCC_CCIPR_CLK48SEL_1                ((uint32_t)0x08000000U)
-
-#define  RCC_CCIPR_ADCSEL                    ((uint32_t)0x30000000U)
-#define  RCC_CCIPR_ADCSEL_0                  ((uint32_t)0x10000000U)
-#define  RCC_CCIPR_ADCSEL_1                  ((uint32_t)0x20000000U)
-
-#define  RCC_CCIPR_SWPMI1SEL                 ((uint32_t)0x40000000U)
-#define  RCC_CCIPR_DFSDMSEL                  ((uint32_t)0x80000000U)
-
-/********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001U)
-#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002U)
-#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004U)
-
-#define  RCC_BDCR_LSEDRV                     ((uint32_t)0x00000018U)
-#define  RCC_BDCR_LSEDRV_0                   ((uint32_t)0x00000008U)
-#define  RCC_BDCR_LSEDRV_1                   ((uint32_t)0x00000010U)
-
-#define  RCC_BDCR_LSECSSON                   ((uint32_t)0x00000020U)
-#define  RCC_BDCR_LSECSSD                    ((uint32_t)0x00000040U)
-
-#define  RCC_BDCR_RTCSEL                     ((uint32_t)0x00000300U)
-#define  RCC_BDCR_RTCSEL_0                   ((uint32_t)0x00000100U)
-#define  RCC_BDCR_RTCSEL_1                   ((uint32_t)0x00000200U)
-
-#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000U)
-#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000U)
-#define  RCC_BDCR_LSCOEN                     ((uint32_t)0x01000000U)
-#define  RCC_BDCR_LSCOSEL                    ((uint32_t)0x02000000U)
-
-/********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       ((uint32_t)0x00000001U)
-#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002U)
-
-#define  RCC_CSR_MSISRANGE                   ((uint32_t)0x00000F00U)
-#define  RCC_CSR_MSISRANGE_1                 ((uint32_t)0x00000400U)      /*!< MSI frequency 1MHZ */
-#define  RCC_CSR_MSISRANGE_2                 ((uint32_t)0x00000500U)      /*!< MSI frequency 2MHZ */
-#define  RCC_CSR_MSISRANGE_4                 ((uint32_t)0x00000600U)      /*!< The default frequency 4MHZ */
-#define  RCC_CSR_MSISRANGE_8                 ((uint32_t)0x00000700U)      /*!< MSI frequency 8MHZ */
-
-#define  RCC_CSR_RMVF                        ((uint32_t)0x00800000U)
-#define  RCC_CSR_FWRSTF                      ((uint32_t)0x01000000U)
-#define  RCC_CSR_OBLRSTF                     ((uint32_t)0x02000000U)
-#define  RCC_CSR_PINRSTF                     ((uint32_t)0x04000000U)
-#define  RCC_CSR_BORRSTF                     ((uint32_t)0x08000000U)
-#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000U)
-#define  RCC_CSR_IWDGRSTF                    ((uint32_t)0x20000000U)
-#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000U)
-#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000U)
-
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    RNG                                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN                         ((uint32_t)0x00000004U)
-#define RNG_CR_IE                            ((uint32_t)0x00000008U)
-
-/********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY                          ((uint32_t)0x00000001U)
-#define RNG_SR_CECS                          ((uint32_t)0x00000002U)
-#define RNG_SR_SECS                          ((uint32_t)0x00000004U)
-#define RNG_SR_CEIS                          ((uint32_t)0x00000020U)
-#define RNG_SR_SEIS                          ((uint32_t)0x00000040U)
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions
-*/
-#define RTC_TAMPER1_SUPPORT
-#define RTC_TAMPER3_SUPPORT
-#define RTC_WAKEUP_SUPPORT
-#define RTC_BACKUP_SUPPORT
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            ((uint32_t)0x00400000U)
-#define RTC_TR_HT                            ((uint32_t)0x00300000U)
-#define RTC_TR_HT_0                          ((uint32_t)0x00100000U)
-#define RTC_TR_HT_1                          ((uint32_t)0x00200000U)
-#define RTC_TR_HU                            ((uint32_t)0x000F0000U)
-#define RTC_TR_HU_0                          ((uint32_t)0x00010000U)
-#define RTC_TR_HU_1                          ((uint32_t)0x00020000U)
-#define RTC_TR_HU_2                          ((uint32_t)0x00040000U)
-#define RTC_TR_HU_3                          ((uint32_t)0x00080000U)
-#define RTC_TR_MNT                           ((uint32_t)0x00007000U)
-#define RTC_TR_MNT_0                         ((uint32_t)0x00001000U)
-#define RTC_TR_MNT_1                         ((uint32_t)0x00002000U)
-#define RTC_TR_MNT_2                         ((uint32_t)0x00004000U)
-#define RTC_TR_MNU                           ((uint32_t)0x00000F00U)
-#define RTC_TR_MNU_0                         ((uint32_t)0x00000100U)
-#define RTC_TR_MNU_1                         ((uint32_t)0x00000200U)
-#define RTC_TR_MNU_2                         ((uint32_t)0x00000400U)
-#define RTC_TR_MNU_3                         ((uint32_t)0x00000800U)
-#define RTC_TR_ST                            ((uint32_t)0x00000070U)
-#define RTC_TR_ST_0                          ((uint32_t)0x00000010U)
-#define RTC_TR_ST_1                          ((uint32_t)0x00000020U)
-#define RTC_TR_ST_2                          ((uint32_t)0x00000040U)
-#define RTC_TR_SU                            ((uint32_t)0x0000000FU)
-#define RTC_TR_SU_0                          ((uint32_t)0x00000001U)
-#define RTC_TR_SU_1                          ((uint32_t)0x00000002U)
-#define RTC_TR_SU_2                          ((uint32_t)0x00000004U)
-#define RTC_TR_SU_3                          ((uint32_t)0x00000008U)
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            ((uint32_t)0x00F00000U)
-#define RTC_DR_YT_0                          ((uint32_t)0x00100000U)
-#define RTC_DR_YT_1                          ((uint32_t)0x00200000U)
-#define RTC_DR_YT_2                          ((uint32_t)0x00400000U)
-#define RTC_DR_YT_3                          ((uint32_t)0x00800000U)
-#define RTC_DR_YU                            ((uint32_t)0x000F0000U)
-#define RTC_DR_YU_0                          ((uint32_t)0x00010000U)
-#define RTC_DR_YU_1                          ((uint32_t)0x00020000U)
-#define RTC_DR_YU_2                          ((uint32_t)0x00040000U)
-#define RTC_DR_YU_3                          ((uint32_t)0x00080000U)
-#define RTC_DR_WDU                           ((uint32_t)0x0000E000U)
-#define RTC_DR_WDU_0                         ((uint32_t)0x00002000U)
-#define RTC_DR_WDU_1                         ((uint32_t)0x00004000U)
-#define RTC_DR_WDU_2                         ((uint32_t)0x00008000U)
-#define RTC_DR_MT                            ((uint32_t)0x00001000U)
-#define RTC_DR_MU                            ((uint32_t)0x00000F00U)
-#define RTC_DR_MU_0                          ((uint32_t)0x00000100U)
-#define RTC_DR_MU_1                          ((uint32_t)0x00000200U)
-#define RTC_DR_MU_2                          ((uint32_t)0x00000400U)
-#define RTC_DR_MU_3                          ((uint32_t)0x00000800U)
-#define RTC_DR_DT                            ((uint32_t)0x00000030U)
-#define RTC_DR_DT_0                          ((uint32_t)0x00000010U)
-#define RTC_DR_DT_1                          ((uint32_t)0x00000020U)
-#define RTC_DR_DU                            ((uint32_t)0x0000000FU)
-#define RTC_DR_DU_0                          ((uint32_t)0x00000001U)
-#define RTC_DR_DU_1                          ((uint32_t)0x00000002U)
-#define RTC_DR_DU_2                          ((uint32_t)0x00000004U)
-#define RTC_DR_DU_3                          ((uint32_t)0x00000008U)
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_ITSE                          ((uint32_t)0x01000000U)
-#define RTC_CR_COE                           ((uint32_t)0x00800000U)
-#define RTC_CR_OSEL                          ((uint32_t)0x00600000U)
-#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000U)
-#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000U)
-#define RTC_CR_POL                           ((uint32_t)0x00100000U)
-#define RTC_CR_COSEL                         ((uint32_t)0x00080000U)
-#define RTC_CR_BCK                           ((uint32_t)0x00040000U)
-#define RTC_CR_SUB1H                         ((uint32_t)0x00020000U)
-#define RTC_CR_ADD1H                         ((uint32_t)0x00010000U)
-#define RTC_CR_TSIE                          ((uint32_t)0x00008000U)
-#define RTC_CR_WUTIE                         ((uint32_t)0x00004000U)
-#define RTC_CR_ALRBIE                        ((uint32_t)0x00002000U)
-#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000U)
-#define RTC_CR_TSE                           ((uint32_t)0x00000800U)
-#define RTC_CR_WUTE                          ((uint32_t)0x00000400U)
-#define RTC_CR_ALRBE                         ((uint32_t)0x00000200U)
-#define RTC_CR_ALRAE                         ((uint32_t)0x00000100U)
-#define RTC_CR_FMT                           ((uint32_t)0x00000040U)
-#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020U)
-#define RTC_CR_REFCKON                       ((uint32_t)0x00000010U)
-#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008U)
-#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007U)
-#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001U)
-#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002U)
-#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004U)
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_ITSF                         ((uint32_t)0x00020000U)
-#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000U)
-#define RTC_ISR_TAMP3F                       ((uint32_t)0x00008000U)
-#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000U)
-#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000U)
-#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000U)
-#define RTC_ISR_TSF                          ((uint32_t)0x00000800U)
-#define RTC_ISR_WUTF                         ((uint32_t)0x00000400U)
-#define RTC_ISR_ALRBF                        ((uint32_t)0x00000200U)
-#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100U)
-#define RTC_ISR_INIT                         ((uint32_t)0x00000080U)
-#define RTC_ISR_INITF                        ((uint32_t)0x00000040U)
-#define RTC_ISR_RSF                          ((uint32_t)0x00000020U)
-#define RTC_ISR_INITS                        ((uint32_t)0x00000010U)
-#define RTC_ISR_SHPF                         ((uint32_t)0x00000008U)
-#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004U)
-#define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002U)
-#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001U)
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000U)
-#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFFU)
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFFU)
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000U)
-#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000U)
-#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000U)
-#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000U)
-#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000U)
-#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000U)
-#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000U)
-#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000U)
-#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000U)
-#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000U)
-#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000U)
-#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000U)
-#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000U)
-#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000U)
-#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000U)
-#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000U)
-#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000U)
-#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000U)
-#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000U)
-#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000U)
-#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000U)
-#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000U)
-#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000U)
-#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000U)
-#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000U)
-#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00U)
-#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100U)
-#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200U)
-#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400U)
-#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800U)
-#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080U)
-#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070U)
-#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010U)
-#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020U)
-#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040U)
-#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000FU)
-#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001U)
-#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002U)
-#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004U)
-#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008U)
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      ((uint32_t)0x80000000U)
-#define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000U)
-#define RTC_ALRMBR_DT                        ((uint32_t)0x30000000U)
-#define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000U)
-#define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000U)
-#define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000U)
-#define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000U)
-#define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000U)
-#define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000U)
-#define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000U)
-#define RTC_ALRMBR_MSK3                      ((uint32_t)0x00800000U)
-#define RTC_ALRMBR_PM                        ((uint32_t)0x00400000U)
-#define RTC_ALRMBR_HT                        ((uint32_t)0x00300000U)
-#define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000U)
-#define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000U)
-#define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000U)
-#define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000U)
-#define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000U)
-#define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000U)
-#define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000U)
-#define RTC_ALRMBR_MSK2                      ((uint32_t)0x00008000U)
-#define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000U)
-#define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000U)
-#define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000U)
-#define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000U)
-#define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00U)
-#define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100U)
-#define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200U)
-#define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400U)
-#define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800U)
-#define RTC_ALRMBR_MSK1                      ((uint32_t)0x00000080U)
-#define RTC_ALRMBR_ST                        ((uint32_t)0x00000070U)
-#define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010U)
-#define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020U)
-#define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040U)
-#define RTC_ALRMBR_SU                        ((uint32_t)0x0000000FU)
-#define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001U)
-#define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002U)
-#define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004U)
-#define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008U)
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          ((uint32_t)0x000000FFU)
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           ((uint32_t)0x0000FFFFU)
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFFU)
-#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000U)
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          ((uint32_t)0x00400000U)
-#define RTC_TSTR_HT                          ((uint32_t)0x00300000U)
-#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000U)
-#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000U)
-#define RTC_TSTR_HU                          ((uint32_t)0x000F0000U)
-#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000U)
-#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000U)
-#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000U)
-#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000U)
-#define RTC_TSTR_MNT                         ((uint32_t)0x00007000U)
-#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000U)
-#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000U)
-#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000U)
-#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00U)
-#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100U)
-#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200U)
-#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400U)
-#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800U)
-#define RTC_TSTR_ST                          ((uint32_t)0x00000070U)
-#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010U)
-#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020U)
-#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040U)
-#define RTC_TSTR_SU                          ((uint32_t)0x0000000FU)
-#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001U)
-#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002U)
-#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004U)
-#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008U)
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000U)
-#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000U)
-#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000U)
-#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000U)
-#define RTC_TSDR_MT                          ((uint32_t)0x00001000U)
-#define RTC_TSDR_MU                          ((uint32_t)0x00000F00U)
-#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100U)
-#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200U)
-#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400U)
-#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800U)
-#define RTC_TSDR_DT                          ((uint32_t)0x00000030U)
-#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010U)
-#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020U)
-#define RTC_TSDR_DU                          ((uint32_t)0x0000000FU)
-#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001U)
-#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002U)
-#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004U)
-#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008U)
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFFU)
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        ((uint32_t)0x00008000U)
-#define RTC_CALR_CALW8                       ((uint32_t)0x00004000U)
-#define RTC_CALR_CALW16                      ((uint32_t)0x00002000U)
-#define RTC_CALR_CALM                        ((uint32_t)0x000001FFU)
-#define RTC_CALR_CALM_0                      ((uint32_t)0x00000001U)
-#define RTC_CALR_CALM_1                      ((uint32_t)0x00000002U)
-#define RTC_CALR_CALM_2                      ((uint32_t)0x00000004U)
-#define RTC_CALR_CALM_3                      ((uint32_t)0x00000008U)
-#define RTC_CALR_CALM_4                      ((uint32_t)0x00000010U)
-#define RTC_CALR_CALM_5                      ((uint32_t)0x00000020U)
-#define RTC_CALR_CALM_6                      ((uint32_t)0x00000040U)
-#define RTC_CALR_CALM_7                      ((uint32_t)0x00000080U)
-#define RTC_CALR_CALM_8                      ((uint32_t)0x00000100U)
-
-/********************  Bits definition for RTC_TAMPCR register  ***************/
-#define RTC_TAMPCR_TAMP3MF                   ((uint32_t)0x01000000U)
-#define RTC_TAMPCR_TAMP3NOERASE              ((uint32_t)0x00800000U)
-#define RTC_TAMPCR_TAMP3IE                   ((uint32_t)0x00400000U)
-#define RTC_TAMPCR_TAMP2MF                   ((uint32_t)0x00200000U)
-#define RTC_TAMPCR_TAMP2NOERASE              ((uint32_t)0x00100000U)
-#define RTC_TAMPCR_TAMP2IE                   ((uint32_t)0x00080000U)
-#define RTC_TAMPCR_TAMP1MF                   ((uint32_t)0x00040000U)
-#define RTC_TAMPCR_TAMP1NOERASE              ((uint32_t)0x00020000U)
-#define RTC_TAMPCR_TAMP1IE                   ((uint32_t)0x00010000U)
-#define RTC_TAMPCR_TAMPPUDIS                 ((uint32_t)0x00008000U)
-#define RTC_TAMPCR_TAMPPRCH                  ((uint32_t)0x00006000U)
-#define RTC_TAMPCR_TAMPPRCH_0                ((uint32_t)0x00002000U)
-#define RTC_TAMPCR_TAMPPRCH_1                ((uint32_t)0x00004000U)
-#define RTC_TAMPCR_TAMPFLT                   ((uint32_t)0x00001800U)
-#define RTC_TAMPCR_TAMPFLT_0                 ((uint32_t)0x00000800U)
-#define RTC_TAMPCR_TAMPFLT_1                 ((uint32_t)0x00001000U)
-#define RTC_TAMPCR_TAMPFREQ                  ((uint32_t)0x00000700U)
-#define RTC_TAMPCR_TAMPFREQ_0                ((uint32_t)0x00000100U)
-#define RTC_TAMPCR_TAMPFREQ_1                ((uint32_t)0x00000200U)
-#define RTC_TAMPCR_TAMPFREQ_2                ((uint32_t)0x00000400U)
-#define RTC_TAMPCR_TAMPTS                    ((uint32_t)0x00000080U)
-#define RTC_TAMPCR_TAMP3TRG                  ((uint32_t)0x00000040U)
-#define RTC_TAMPCR_TAMP3E                    ((uint32_t)0x00000020U)
-#define RTC_TAMPCR_TAMP2TRG                  ((uint32_t)0x00000010U)
-#define RTC_TAMPCR_TAMP2E                    ((uint32_t)0x00000008U)
-#define RTC_TAMPCR_TAMPIE                    ((uint32_t)0x00000004U)
-#define RTC_TAMPCR_TAMP1TRG                  ((uint32_t)0x00000002U)
-#define RTC_TAMPCR_TAMP1E                    ((uint32_t)0x00000001U)
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000U)
-#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000U)
-#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000U)
-#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000U)
-#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000U)
-#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFFU)
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  ((uint32_t)0x0F000000U)
-#define RTC_ALRMBSSR_MASKSS_0                ((uint32_t)0x01000000U)
-#define RTC_ALRMBSSR_MASKSS_1                ((uint32_t)0x02000000U)
-#define RTC_ALRMBSSR_MASKSS_2                ((uint32_t)0x04000000U)
-#define RTC_ALRMBSSR_MASKSS_3                ((uint32_t)0x08000000U)
-#define RTC_ALRMBSSR_SS                      ((uint32_t)0x00007FFFU)
-
-/********************  Bits definition for RTC_0R register  *******************/
-#define RTC_OR_OUT_RMP                      ((uint32_t)0x00000002U)
-#define RTC_OR_ALARMOUTTYPE                 ((uint32_t)0x00000001U)
-
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFFU)
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFFU)
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFFU)
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFFU)
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFFU)
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            ((uint32_t)0xFFFFFFFFU)
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            ((uint32_t)0xFFFFFFFFU)
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            ((uint32_t)0xFFFFFFFFU)
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            ((uint32_t)0xFFFFFFFFU)
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            ((uint32_t)0xFFFFFFFFU)
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           ((uint32_t)0xFFFFFFFFU)
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           ((uint32_t)0xFFFFFFFFU)
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           ((uint32_t)0xFFFFFFFFU)
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           ((uint32_t)0xFFFFFFFFU)
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           ((uint32_t)0xFFFFFFFFU)
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           ((uint32_t)0xFFFFFFFFU)
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           ((uint32_t)0xFFFFFFFFU)
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           ((uint32_t)0xFFFFFFFFU)
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           ((uint32_t)0xFFFFFFFFU)
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           ((uint32_t)0xFFFFFFFFU)
-
-/********************  Bits definition for RTC_BKP20R register  ***************/
-#define RTC_BKP20R                           ((uint32_t)0xFFFFFFFFU)
-
-/********************  Bits definition for RTC_BKP21R register  ***************/
-#define RTC_BKP21R                           ((uint32_t)0xFFFFFFFFU)
-
-/********************  Bits definition for RTC_BKP22R register  ***************/
-#define RTC_BKP22R                           ((uint32_t)0xFFFFFFFFU)
-
-/********************  Bits definition for RTC_BKP23R register  ***************/
-#define RTC_BKP23R                           ((uint32_t)0xFFFFFFFFU)
-
-/********************  Bits definition for RTC_BKP24R register  ***************/
-#define RTC_BKP24R                           ((uint32_t)0xFFFFFFFFU)
-
-/********************  Bits definition for RTC_BKP25R register  ***************/
-#define RTC_BKP25R                           ((uint32_t)0xFFFFFFFFU)
-
-/********************  Bits definition for RTC_BKP26R register  ***************/
-#define RTC_BKP26R                           ((uint32_t)0xFFFFFFFFU)
-
-/********************  Bits definition for RTC_BKP27R register  ***************/
-#define RTC_BKP27R                           ((uint32_t)0xFFFFFFFFU)
-
-/********************  Bits definition for RTC_BKP28R register  ***************/
-#define RTC_BKP28R                           ((uint32_t)0xFFFFFFFFU)
-
-/********************  Bits definition for RTC_BKP29R register  ***************/
-#define RTC_BKP29R                           ((uint32_t)0xFFFFFFFFU)
-
-/********************  Bits definition for RTC_BKP30R register  ***************/
-#define RTC_BKP30R                           ((uint32_t)0xFFFFFFFFU)
-
-/********************  Bits definition for RTC_BKP31R register  ***************/
-#define RTC_BKP31R                           ((uint32_t)0xFFFFFFFFU)
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER                       ((uint32_t)0x00000020U)
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Serial Audio Interface                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for SAI_GCR register  *******************/
-#define  SAI_GCR_SYNCIN                  ((uint32_t)0x00000003U)        /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
-#define  SAI_GCR_SYNCIN_0                ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  SAI_GCR_SYNCIN_1                ((uint32_t)0x00000002U)        /*!<Bit 1 */
-
-#define  SAI_GCR_SYNCOUT                 ((uint32_t)0x00000030U)        /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
-#define  SAI_GCR_SYNCOUT_0               ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  SAI_GCR_SYNCOUT_1               ((uint32_t)0x00000020U)        /*!<Bit 1 */
-
-/*******************  Bit definition for SAI_xCR1 register  *******************/
-#define  SAI_xCR1_MODE                    ((uint32_t)0x00000003U)        /*!<MODE[1:0] bits (Audio Block Mode)           */
-#define  SAI_xCR1_MODE_0                  ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  SAI_xCR1_MODE_1                  ((uint32_t)0x00000002U)        /*!<Bit 1 */
-
-#define  SAI_xCR1_PRTCFG                  ((uint32_t)0x0000000CU)        /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
-#define  SAI_xCR1_PRTCFG_0                ((uint32_t)0x00000004U)        /*!<Bit 0 */
-#define  SAI_xCR1_PRTCFG_1                ((uint32_t)0x00000008U)        /*!<Bit 1 */
-
-#define  SAI_xCR1_DS                      ((uint32_t)0x000000E0U)        /*!<DS[1:0] bits (Data Size) */
-#define  SAI_xCR1_DS_0                    ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  SAI_xCR1_DS_1                    ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  SAI_xCR1_DS_2                    ((uint32_t)0x00000080U)        /*!<Bit 2 */
-
-#define  SAI_xCR1_LSBFIRST                ((uint32_t)0x00000100U)        /*!<LSB First Configuration  */
-#define  SAI_xCR1_CKSTR                   ((uint32_t)0x00000200U)        /*!<ClocK STRobing edge      */
-
-#define  SAI_xCR1_SYNCEN                  ((uint32_t)0x00000C00U)        /*!<SYNCEN[1:0](SYNChronization ENable) */
-#define  SAI_xCR1_SYNCEN_0                ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  SAI_xCR1_SYNCEN_1                ((uint32_t)0x00000800U)        /*!<Bit 1 */
-
-#define  SAI_xCR1_MONO                    ((uint32_t)0x00001000U)        /*!<Mono mode                  */
-#define  SAI_xCR1_OUTDRIV                 ((uint32_t)0x00002000U)        /*!<Output Drive               */
-#define  SAI_xCR1_SAIEN                   ((uint32_t)0x00010000U)        /*!<Audio Block enable         */
-#define  SAI_xCR1_DMAEN                   ((uint32_t)0x00020000U)        /*!<DMA enable                 */
-#define  SAI_xCR1_NODIV                   ((uint32_t)0x00080000U)        /*!<No Divider Configuration   */
-
-#define  SAI_xCR1_MCKDIV                  ((uint32_t)0x00F00000U)        /*!<MCKDIV[3:0] (Master ClocK Divider)  */
-#define  SAI_xCR1_MCKDIV_0                ((uint32_t)0x00100000U)        /*!<Bit 0  */
-#define  SAI_xCR1_MCKDIV_1                ((uint32_t)0x00200000U)        /*!<Bit 1  */
-#define  SAI_xCR1_MCKDIV_2                ((uint32_t)0x00400000U)        /*!<Bit 2  */
-#define  SAI_xCR1_MCKDIV_3                ((uint32_t)0x00800000U)        /*!<Bit 3  */
-
-/*******************  Bit definition for SAI_xCR2 register  *******************/
-#define  SAI_xCR2_FTH                     ((uint32_t)0x00000007U)        /*!<FTH[2:0](Fifo THreshold)  */
-#define  SAI_xCR2_FTH_0                   ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  SAI_xCR2_FTH_1                   ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  SAI_xCR2_FTH_2                   ((uint32_t)0x00000004U)        /*!<Bit 2 */
-
-#define  SAI_xCR2_FFLUSH                  ((uint32_t)0x00000008U)        /*!<Fifo FLUSH                       */
-#define  SAI_xCR2_TRIS                    ((uint32_t)0x00000010U)        /*!<TRIState Management on data line */
-#define  SAI_xCR2_MUTE                    ((uint32_t)0x00000020U)        /*!<Mute mode                        */
-#define  SAI_xCR2_MUTEVAL                 ((uint32_t)0x00000040U)        /*!<Muate value                      */
-
-
-#define  SAI_xCR2_MUTECNT                 ((uint32_t)0x00001F80U)        /*!<MUTECNT[5:0] (MUTE counter) */
-#define  SAI_xCR2_MUTECNT_0               ((uint32_t)0x00000080U)        /*!<Bit 0 */
-#define  SAI_xCR2_MUTECNT_1               ((uint32_t)0x00000100U)        /*!<Bit 1 */
-#define  SAI_xCR2_MUTECNT_2               ((uint32_t)0x00000200U)        /*!<Bit 2 */
-#define  SAI_xCR2_MUTECNT_3               ((uint32_t)0x00000400U)        /*!<Bit 3 */
-#define  SAI_xCR2_MUTECNT_4               ((uint32_t)0x00000800U)        /*!<Bit 4 */
-#define  SAI_xCR2_MUTECNT_5               ((uint32_t)0x00001000U)        /*!<Bit 5 */
-
-#define  SAI_xCR2_CPL                     ((uint32_t)0x00002000U)        /*!<CPL mode                    */
-#define  SAI_xCR2_COMP                    ((uint32_t)0x0000C000U)        /*!<COMP[1:0] (Companding mode) */
-#define  SAI_xCR2_COMP_0                  ((uint32_t)0x00004000U)        /*!<Bit 0 */
-#define  SAI_xCR2_COMP_1                  ((uint32_t)0x00008000U)        /*!<Bit 1 */
-
-
-/******************  Bit definition for SAI_xFRCR register  *******************/
-#define  SAI_xFRCR_FRL                    ((uint32_t)0x000000FFU)        /*!<FRL[7:0](Frame length)  */
-#define  SAI_xFRCR_FRL_0                  ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  SAI_xFRCR_FRL_1                  ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  SAI_xFRCR_FRL_2                  ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  SAI_xFRCR_FRL_3                  ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  SAI_xFRCR_FRL_4                  ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  SAI_xFRCR_FRL_5                  ((uint32_t)0x00000020U)        /*!<Bit 5 */
-#define  SAI_xFRCR_FRL_6                  ((uint32_t)0x00000040U)        /*!<Bit 6 */
-#define  SAI_xFRCR_FRL_7                  ((uint32_t)0x00000080U)        /*!<Bit 7 */
-
-#define  SAI_xFRCR_FSALL                  ((uint32_t)0x00007F00U)        /*!<FRL[6:0] (Frame synchronization active level length)  */
-#define  SAI_xFRCR_FSALL_0                ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  SAI_xFRCR_FSALL_1                ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  SAI_xFRCR_FSALL_2                ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  SAI_xFRCR_FSALL_3                ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  SAI_xFRCR_FSALL_4                ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  SAI_xFRCR_FSALL_5                ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  SAI_xFRCR_FSALL_6                ((uint32_t)0x00004000U)        /*!<Bit 6 */
-
-#define  SAI_xFRCR_FSDEF                  ((uint32_t)0x00010000U)        /*!< Frame Synchronization Definition */
-#define  SAI_xFRCR_FSPO                   ((uint32_t)0x00020000U)        /*!<Frame Synchronization POLarity    */
-#define  SAI_xFRCR_FSOFF                  ((uint32_t)0x00040000U)        /*!<Frame Synchronization OFFset      */
-
-/******************  Bit definition for SAI_xSLOTR register  *******************/
-#define  SAI_xSLOTR_FBOFF                 ((uint32_t)0x0000001FU)        /*!<FRL[4:0](First Bit Offset)  */
-#define  SAI_xSLOTR_FBOFF_0               ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  SAI_xSLOTR_FBOFF_1               ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  SAI_xSLOTR_FBOFF_2               ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  SAI_xSLOTR_FBOFF_3               ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  SAI_xSLOTR_FBOFF_4               ((uint32_t)0x00000010U)        /*!<Bit 4 */
-
-#define  SAI_xSLOTR_SLOTSZ                ((uint32_t)0x000000C0U)        /*!<SLOTSZ[1:0] (Slot size)  */
-#define  SAI_xSLOTR_SLOTSZ_0              ((uint32_t)0x00000040U)        /*!<Bit 0 */
-#define  SAI_xSLOTR_SLOTSZ_1              ((uint32_t)0x00000080U)        /*!<Bit 1 */
-
-#define  SAI_xSLOTR_NBSLOT                ((uint32_t)0x00000F00U)        /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
-#define  SAI_xSLOTR_NBSLOT_0              ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  SAI_xSLOTR_NBSLOT_1              ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  SAI_xSLOTR_NBSLOT_2              ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  SAI_xSLOTR_NBSLOT_3              ((uint32_t)0x00000800U)        /*!<Bit 3 */
-
-#define  SAI_xSLOTR_SLOTEN                ((uint32_t)0xFFFF0000U)        /*!<SLOTEN[15:0] (Slot Enable)  */
-
-/*******************  Bit definition for SAI_xIMR register  *******************/
-#define  SAI_xIMR_OVRUDRIE                ((uint32_t)0x00000001U)        /*!<Overrun underrun interrupt enable                              */
-#define  SAI_xIMR_MUTEDETIE               ((uint32_t)0x00000002U)        /*!<Mute detection interrupt enable                                */
-#define  SAI_xIMR_WCKCFGIE                ((uint32_t)0x00000004U)        /*!<Wrong Clock Configuration interrupt enable                     */
-#define  SAI_xIMR_FREQIE                  ((uint32_t)0x00000008U)        /*!<FIFO request interrupt enable                                  */
-#define  SAI_xIMR_CNRDYIE                 ((uint32_t)0x00000010U)        /*!<Codec not ready interrupt enable                               */
-#define  SAI_xIMR_AFSDETIE                ((uint32_t)0x00000020U)        /*!<Anticipated frame synchronization detection interrupt enable   */
-#define  SAI_xIMR_LFSDETIE                ((uint32_t)0x00000040U)        /*!<Late frame synchronization detection interrupt enable          */
-
-/********************  Bit definition for SAI_xSR register  *******************/
-#define  SAI_xSR_OVRUDR                   ((uint32_t)0x00000001U)         /*!<Overrun underrun                               */
-#define  SAI_xSR_MUTEDET                  ((uint32_t)0x00000002U)         /*!<Mute detection                                 */
-#define  SAI_xSR_WCKCFG                   ((uint32_t)0x00000004U)         /*!<Wrong Clock Configuration                      */
-#define  SAI_xSR_FREQ                     ((uint32_t)0x00000008U)         /*!<FIFO request                                   */
-#define  SAI_xSR_CNRDY                    ((uint32_t)0x00000010U)         /*!<Codec not ready                                */
-#define  SAI_xSR_AFSDET                   ((uint32_t)0x00000020U)         /*!<Anticipated frame synchronization detection    */
-#define  SAI_xSR_LFSDET                   ((uint32_t)0x00000040U)         /*!<Late frame synchronization detection           */
-
-#define  SAI_xSR_FLVL                     ((uint32_t)0x00070000U)         /*!<FLVL[2:0] (FIFO Level Threshold)               */
-#define  SAI_xSR_FLVL_0                   ((uint32_t)0x00010000U)         /*!<Bit 0 */
-#define  SAI_xSR_FLVL_1                   ((uint32_t)0x00020000U)         /*!<Bit 1 */
-#define  SAI_xSR_FLVL_2                   ((uint32_t)0x00030000U)         /*!<Bit 2 */
-
-/******************  Bit definition for SAI_xCLRFR register  ******************/
-#define  SAI_xCLRFR_COVRUDR               ((uint32_t)0x00000001U)        /*!<Clear Overrun underrun                               */
-#define  SAI_xCLRFR_CMUTEDET              ((uint32_t)0x00000002U)        /*!<Clear Mute detection                                 */
-#define  SAI_xCLRFR_CWCKCFG               ((uint32_t)0x00000004U)        /*!<Clear Wrong Clock Configuration                      */
-#define  SAI_xCLRFR_CFREQ                 ((uint32_t)0x00000008U)        /*!<Clear FIFO request                                   */
-#define  SAI_xCLRFR_CCNRDY                ((uint32_t)0x00000010U)        /*!<Clear Codec not ready                                */
-#define  SAI_xCLRFR_CAFSDET               ((uint32_t)0x00000020U)        /*!<Clear Anticipated frame synchronization detection    */
-#define  SAI_xCLRFR_CLFSDET               ((uint32_t)0x00000040U)        /*!<Clear Late frame synchronization detection           */
-
-/******************  Bit definition for SAI_xDR register  ******************/
-#define  SAI_xDR_DATA                     ((uint32_t)0xFFFFFFFFU)
-
-/******************************************************************************/
-/*                                                                            */
-/*                          LCD Controller (LCD)                              */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for LCD_CR register  *********************/
-#define LCD_CR_LCDEN               ((uint32_t)0x00000001U)     /*!< LCD Enable Bit */
-#define LCD_CR_VSEL                ((uint32_t)0x00000002U)     /*!< Voltage source selector Bit */
-
-#define LCD_CR_DUTY                ((uint32_t)0x0000001CU)     /*!< DUTY[2:0] bits (Duty selector) */
-#define LCD_CR_DUTY_0              ((uint32_t)0x00000004U)     /*!< Duty selector Bit 0 */
-#define LCD_CR_DUTY_1              ((uint32_t)0x00000008U)     /*!< Duty selector Bit 1 */
-#define LCD_CR_DUTY_2              ((uint32_t)0x00000010U)     /*!< Duty selector Bit 2 */
-
-#define LCD_CR_BIAS                ((uint32_t)0x00000060U)     /*!< BIAS[1:0] bits (Bias selector) */
-#define LCD_CR_BIAS_0              ((uint32_t)0x00000020U)     /*!< Bias selector Bit 0 */
-#define LCD_CR_BIAS_1              ((uint32_t)0x00000040U)     /*!< Bias selector Bit 1 */
-
-#define LCD_CR_MUX_SEG             ((uint32_t)0x00000080U)     /*!< Mux Segment Enable Bit */
-#define LCD_CR_BUFEN               ((uint32_t)0x00000100U)     /*!< Voltage output buffer enable */
-
-/*******************  Bit definition for LCD_FCR register  ********************/
-#define LCD_FCR_HD                 ((uint32_t)0x00000001U)     /*!< High Drive Enable Bit */
-#define LCD_FCR_SOFIE              ((uint32_t)0x00000002U)     /*!< Start of Frame Interrupt Enable Bit */
-#define LCD_FCR_UDDIE              ((uint32_t)0x00000008U)     /*!< Update Display Done Interrupt Enable Bit */
-
-#define LCD_FCR_PON                ((uint32_t)0x00000070U)     /*!< PON[2:0] bits (Pulse ON Duration) */
-#define LCD_FCR_PON_0              ((uint32_t)0x00000010U)     /*!< Bit 0 */
-#define LCD_FCR_PON_1              ((uint32_t)0x00000020U)     /*!< Bit 1 */
-#define LCD_FCR_PON_2              ((uint32_t)0x00000040U)     /*!< Bit 2 */
-
-#define LCD_FCR_DEAD               ((uint32_t)0x00000380U)     /*!< DEAD[2:0] bits (DEAD Time) */
-#define LCD_FCR_DEAD_0             ((uint32_t)0x00000080U)     /*!< Bit 0 */
-#define LCD_FCR_DEAD_1             ((uint32_t)0x00000100U)     /*!< Bit 1 */
-#define LCD_FCR_DEAD_2             ((uint32_t)0x00000200U)     /*!< Bit 2 */
-
-#define LCD_FCR_CC                 ((uint32_t)0x00001C00U)     /*!< CC[2:0] bits (Contrast Control) */
-#define LCD_FCR_CC_0               ((uint32_t)0x00000400U)     /*!< Bit 0 */
-#define LCD_FCR_CC_1               ((uint32_t)0x00000800U)     /*!< Bit 1 */
-#define LCD_FCR_CC_2               ((uint32_t)0x00001000U)     /*!< Bit 2 */
-
-#define LCD_FCR_BLINKF             ((uint32_t)0x0000E000U)     /*!< BLINKF[2:0] bits (Blink Frequency) */
-#define LCD_FCR_BLINKF_0           ((uint32_t)0x00002000U)     /*!< Bit 0 */
-#define LCD_FCR_BLINKF_1           ((uint32_t)0x00004000U)     /*!< Bit 1 */
-#define LCD_FCR_BLINKF_2           ((uint32_t)0x00008000U)     /*!< Bit 2 */
-
-#define LCD_FCR_BLINK              ((uint32_t)0x00030000U)     /*!< BLINK[1:0] bits (Blink Enable) */
-#define LCD_FCR_BLINK_0            ((uint32_t)0x00010000U)     /*!< Bit 0 */
-#define LCD_FCR_BLINK_1            ((uint32_t)0x00020000U)     /*!< Bit 1 */
-
-#define LCD_FCR_DIV                ((uint32_t)0x003C0000U)     /*!< DIV[3:0] bits (Divider) */
-#define LCD_FCR_PS                 ((uint32_t)0x03C00000U)     /*!< PS[3:0] bits (Prescaler) */
-
-/*******************  Bit definition for LCD_SR register  *********************/
-#define LCD_SR_ENS                 ((uint32_t)0x00000001U)     /*!< LCD Enabled Bit */
-#define LCD_SR_SOF                 ((uint32_t)0x00000002U)     /*!< Start Of Frame Flag Bit */
-#define LCD_SR_UDR                 ((uint32_t)0x00000004U)     /*!< Update Display Request Bit */
-#define LCD_SR_UDD                 ((uint32_t)0x00000008U)     /*!< Update Display Done Flag Bit */
-#define LCD_SR_RDY                 ((uint32_t)0x00000010U)     /*!< Ready Flag Bit */
-#define LCD_SR_FCRSR               ((uint32_t)0x00000020U)     /*!< LCD FCR Register Synchronization Flag Bit */
-
-/*******************  Bit definition for LCD_CLR register  ********************/
-#define LCD_CLR_SOFC               ((uint32_t)0x00000002U)     /*!< Start Of Frame Flag Clear Bit */
-#define LCD_CLR_UDDC               ((uint32_t)0x00000008U)     /*!< Update Display Done Flag Clear Bit */
-
-/*******************  Bit definition for LCD_RAM register  ********************/
-#define LCD_RAM_SEGMENT_DATA       ((uint32_t)0xFFFFFFFFU)     /*!< Segment Data Bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           SDMMC Interface                                  */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SDMMC_POWER register  ******************/
-#define  SDMMC_POWER_PWRCTRL                  ((uint8_t)0x03U)               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDMMC_POWER_PWRCTRL_0                ((uint8_t)0x01U)               /*!<Bit 0 */
-#define  SDMMC_POWER_PWRCTRL_1                ((uint8_t)0x02U)               /*!<Bit 1 */
-
-/******************  Bit definition for SDMMC_CLKCR register  ******************/
-#define  SDMMC_CLKCR_CLKDIV                   ((uint16_t)0x00FFU)            /*!<Clock divide factor             */
-#define  SDMMC_CLKCR_CLKEN                    ((uint16_t)0x0100U)            /*!<Clock enable bit                */
-#define  SDMMC_CLKCR_PWRSAV                   ((uint16_t)0x0200U)            /*!<Power saving configuration bit  */
-#define  SDMMC_CLKCR_BYPASS                   ((uint16_t)0x0400U)            /*!<Clock divider bypass enable bit */
-
-#define  SDMMC_CLKCR_WIDBUS                   ((uint16_t)0x1800U)            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDMMC_CLKCR_WIDBUS_0                 ((uint16_t)0x0800U)            /*!<Bit 0 */
-#define  SDMMC_CLKCR_WIDBUS_1                 ((uint16_t)0x1000U)            /*!<Bit 1 */
-
-#define  SDMMC_CLKCR_NEGEDGE                  ((uint16_t)0x2000U)            /*!<SDMMC_CK dephasing selection bit */
-#define  SDMMC_CLKCR_HWFC_EN                  ((uint16_t)0x4000U)            /*!<HW Flow Control enable          */
-
-/*******************  Bit definition for SDMMC_ARG register  *******************/
-#define  SDMMC_ARG_CMDARG                     ((uint32_t)0xFFFFFFFFU)            /*!<Command argument */
-
-/*******************  Bit definition for SDMMC_CMD register  *******************/
-#define  SDMMC_CMD_CMDINDEX                   ((uint16_t)0x003FU)            /*!<Command Index                               */
-
-#define  SDMMC_CMD_WAITRESP                   ((uint16_t)0x00C0U)            /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDMMC_CMD_WAITRESP_0                 ((uint16_t)0x0040U)            /*!< Bit 0 */
-#define  SDMMC_CMD_WAITRESP_1                 ((uint16_t)0x0080U)            /*!< Bit 1 */
-
-#define  SDMMC_CMD_WAITINT                    ((uint16_t)0x0100U)            /*!<CPSM Waits for Interrupt Request                               */
-#define  SDMMC_CMD_WAITPEND                   ((uint16_t)0x0200U)            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDMMC_CMD_CPSMEN                     ((uint16_t)0x0400U)            /*!<Command path state machine (CPSM) Enable bit                   */
-#define  SDMMC_CMD_SDIOSUSPEND                ((uint16_t)0x0800U)            /*!<SD I/O suspend command                                         */
-
-/*****************  Bit definition for SDMMC_RESPCMD register  *****************/
-#define  SDMMC_RESPCMD_RESPCMD                ((uint8_t)0x3FU)               /*!<Response command index */
-
-/******************  Bit definition for SDMMC_RESP0 register  ******************/
-#define  SDMMC_RESP0_CARDSTATUS0              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
-
-/******************  Bit definition for SDMMC_RESP1 register  ******************/
-#define  SDMMC_RESP1_CARDSTATUS1              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
-
-/******************  Bit definition for SDMMC_RESP2 register  ******************/
-#define  SDMMC_RESP2_CARDSTATUS2              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
-
-/******************  Bit definition for SDMMC_RESP3 register  ******************/
-#define  SDMMC_RESP3_CARDSTATUS3              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
-
-/******************  Bit definition for SDMMC_RESP4 register  ******************/
-#define  SDMMC_RESP4_CARDSTATUS4              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
-
-/******************  Bit definition for SDMMC_DTIMER register  *****************/
-#define  SDMMC_DTIMER_DATATIME                ((uint32_t)0xFFFFFFFFU)        /*!<Data timeout period. */
-
-/******************  Bit definition for SDMMC_DLEN register  *******************/
-#define  SDMMC_DLEN_DATALENGTH                ((uint32_t)0x01FFFFFFU)        /*!<Data length value    */
-
-/******************  Bit definition for SDMMC_DCTRL register  ******************/
-#define  SDMMC_DCTRL_DTEN                     ((uint16_t)0x0001U)            /*!<Data transfer enabled bit         */
-#define  SDMMC_DCTRL_DTDIR                    ((uint16_t)0x0002U)            /*!<Data transfer direction selection */
-#define  SDMMC_DCTRL_DTMODE                   ((uint16_t)0x0004U)            /*!<Data transfer mode selection      */
-#define  SDMMC_DCTRL_DMAEN                    ((uint16_t)0x0008U)            /*!<DMA enabled bit                   */
-
-#define  SDMMC_DCTRL_DBLOCKSIZE               ((uint16_t)0x00F0U)            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDMMC_DCTRL_DBLOCKSIZE_0             ((uint16_t)0x0010U)            /*!<Bit 0 */
-#define  SDMMC_DCTRL_DBLOCKSIZE_1             ((uint16_t)0x0020U)            /*!<Bit 1 */
-#define  SDMMC_DCTRL_DBLOCKSIZE_2             ((uint16_t)0x0040U)            /*!<Bit 2 */
-#define  SDMMC_DCTRL_DBLOCKSIZE_3             ((uint16_t)0x0080U)            /*!<Bit 3 */
-
-#define  SDMMC_DCTRL_RWSTART                  ((uint16_t)0x0100U)            /*!<Read wait start         */
-#define  SDMMC_DCTRL_RWSTOP                   ((uint16_t)0x0200U)            /*!<Read wait stop          */
-#define  SDMMC_DCTRL_RWMOD                    ((uint16_t)0x0400U)            /*!<Read wait mode          */
-#define  SDMMC_DCTRL_SDIOEN                   ((uint16_t)0x0800U)            /*!<SD I/O enable functions */
-
-/******************  Bit definition for SDMMC_DCOUNT register  *****************/
-#define  SDMMC_DCOUNT_DATACOUNT               ((uint32_t)0x01FFFFFFU)        /*!<Data count value */
-
-/******************  Bit definition for SDMMC_STA register  ********************/
-#define  SDMMC_STA_CCRCFAIL                   ((uint32_t)0x00000001U)        /*!<Command response received (CRC check failed)  */
-#define  SDMMC_STA_DCRCFAIL                   ((uint32_t)0x00000002U)        /*!<Data block sent/received (CRC check failed)   */
-#define  SDMMC_STA_CTIMEOUT                   ((uint32_t)0x00000004U)        /*!<Command response timeout                      */
-#define  SDMMC_STA_DTIMEOUT                   ((uint32_t)0x00000008U)        /*!<Data timeout                                  */
-#define  SDMMC_STA_TXUNDERR                   ((uint32_t)0x00000010U)        /*!<Transmit FIFO underrun error                  */
-#define  SDMMC_STA_RXOVERR                    ((uint32_t)0x00000020U)        /*!<Received FIFO overrun error                   */
-#define  SDMMC_STA_CMDREND                    ((uint32_t)0x00000040U)        /*!<Command response received (CRC check passed)  */
-#define  SDMMC_STA_CMDSENT                    ((uint32_t)0x00000080U)        /*!<Command sent (no response required)           */
-#define  SDMMC_STA_DATAEND                    ((uint32_t)0x00000100U)        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
-#define  SDMMC_STA_STBITERR                   ((uint32_t)0x00000200U)        /*!<Start bit not detected on all data signals in wide bus mode */
-#define  SDMMC_STA_DBCKEND                    ((uint32_t)0x00000400U)        /*!<Data block sent/received (CRC check passed)   */
-#define  SDMMC_STA_CMDACT                     ((uint32_t)0x00000800U)        /*!<Command transfer in progress                  */
-#define  SDMMC_STA_TXACT                      ((uint32_t)0x00001000U)        /*!<Data transmit in progress                     */
-#define  SDMMC_STA_RXACT                      ((uint32_t)0x00002000U)        /*!<Data receive in progress                      */
-#define  SDMMC_STA_TXFIFOHE                   ((uint32_t)0x00004000U)        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDMMC_STA_RXFIFOHF                   ((uint32_t)0x00008000U)        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDMMC_STA_TXFIFOF                    ((uint32_t)0x00010000U)        /*!<Transmit FIFO full                            */
-#define  SDMMC_STA_RXFIFOF                    ((uint32_t)0x00020000U)        /*!<Receive FIFO full                             */
-#define  SDMMC_STA_TXFIFOE                    ((uint32_t)0x00040000U)        /*!<Transmit FIFO empty                           */
-#define  SDMMC_STA_RXFIFOE                    ((uint32_t)0x00080000U)        /*!<Receive FIFO empty                            */
-#define  SDMMC_STA_TXDAVL                     ((uint32_t)0x00100000U)        /*!<Data available in transmit FIFO               */
-#define  SDMMC_STA_RXDAVL                     ((uint32_t)0x00200000U)        /*!<Data available in receive FIFO                */
-#define  SDMMC_STA_SDIOIT                     ((uint32_t)0x00400000U)        /*!<SDIO interrupt received                       */
-
-/*******************  Bit definition for SDMMC_ICR register  *******************/
-#define  SDMMC_ICR_CCRCFAILC                  ((uint32_t)0x00000001U)        /*!<CCRCFAIL flag clear bit */
-#define  SDMMC_ICR_DCRCFAILC                  ((uint32_t)0x00000002U)        /*!<DCRCFAIL flag clear bit */
-#define  SDMMC_ICR_CTIMEOUTC                  ((uint32_t)0x00000004U)        /*!<CTIMEOUT flag clear bit */
-#define  SDMMC_ICR_DTIMEOUTC                  ((uint32_t)0x00000008U)        /*!<DTIMEOUT flag clear bit */
-#define  SDMMC_ICR_TXUNDERRC                  ((uint32_t)0x00000010U)        /*!<TXUNDERR flag clear bit */
-#define  SDMMC_ICR_RXOVERRC                   ((uint32_t)0x00000020U)        /*!<RXOVERR flag clear bit  */
-#define  SDMMC_ICR_CMDRENDC                   ((uint32_t)0x00000040U)        /*!<CMDREND flag clear bit  */
-#define  SDMMC_ICR_CMDSENTC                   ((uint32_t)0x00000080U)        /*!<CMDSENT flag clear bit  */
-#define  SDMMC_ICR_DATAENDC                   ((uint32_t)0x00000100U)        /*!<DATAEND flag clear bit  */
-#define  SDMMC_ICR_STBITERRC                  ((uint32_t)0x00000200U)        /*!<STBITERR flag clear bit */
-#define  SDMMC_ICR_DBCKENDC                   ((uint32_t)0x00000400U)        /*!<DBCKEND flag clear bit  */
-#define  SDMMC_ICR_SDIOITC                    ((uint32_t)0x00400000U)        /*!<SDIOIT flag clear bit   */
-
-/******************  Bit definition for SDMMC_MASK register  *******************/
-#define  SDMMC_MASK_CCRCFAILIE                ((uint32_t)0x00000001U)        /*!<Command CRC Fail Interrupt Enable          */
-#define  SDMMC_MASK_DCRCFAILIE                ((uint32_t)0x00000002U)        /*!<Data CRC Fail Interrupt Enable             */
-#define  SDMMC_MASK_CTIMEOUTIE                ((uint32_t)0x00000004U)        /*!<Command TimeOut Interrupt Enable           */
-#define  SDMMC_MASK_DTIMEOUTIE                ((uint32_t)0x00000008U)        /*!<Data TimeOut Interrupt Enable              */
-#define  SDMMC_MASK_TXUNDERRIE                ((uint32_t)0x00000010U)        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
-#define  SDMMC_MASK_RXOVERRIE                 ((uint32_t)0x00000020U)        /*!<Rx FIFO OverRun Error Interrupt Enable     */
-#define  SDMMC_MASK_CMDRENDIE                 ((uint32_t)0x00000040U)        /*!<Command Response Received Interrupt Enable */
-#define  SDMMC_MASK_CMDSENTIE                 ((uint32_t)0x00000080U)        /*!<Command Sent Interrupt Enable              */
-#define  SDMMC_MASK_DATAENDIE                 ((uint32_t)0x00000100U)        /*!<Data End Interrupt Enable                  */
-#define  SDMMC_MASK_DBCKENDIE                 ((uint32_t)0x00000400U)        /*!<Data Block End Interrupt Enable            */
-#define  SDMMC_MASK_CMDACTIE                  ((uint32_t)0x00000800U)        /*!<CCommand Acting Interrupt Enable           */
-#define  SDMMC_MASK_TXACTIE                   ((uint32_t)0x00001000U)        /*!<Data Transmit Acting Interrupt Enable      */
-#define  SDMMC_MASK_RXACTIE                   ((uint32_t)0x00002000U)        /*!<Data receive acting interrupt enabled      */
-#define  SDMMC_MASK_TXFIFOHEIE                ((uint32_t)0x00004000U)        /*!<Tx FIFO Half Empty interrupt Enable        */
-#define  SDMMC_MASK_RXFIFOHFIE                ((uint32_t)0x00008000U)        /*!<Rx FIFO Half Full interrupt Enable         */
-#define  SDMMC_MASK_TXFIFOFIE                 ((uint32_t)0x00010000U)        /*!<Tx FIFO Full interrupt Enable              */
-#define  SDMMC_MASK_RXFIFOFIE                 ((uint32_t)0x00020000U)        /*!<Rx FIFO Full interrupt Enable              */
-#define  SDMMC_MASK_TXFIFOEIE                 ((uint32_t)0x00040000U)        /*!<Tx FIFO Empty interrupt Enable             */
-#define  SDMMC_MASK_RXFIFOEIE                 ((uint32_t)0x00080000U)        /*!<Rx FIFO Empty interrupt Enable             */
-#define  SDMMC_MASK_TXDAVLIE                  ((uint32_t)0x00100000U)        /*!<Data available in Tx FIFO interrupt Enable */
-#define  SDMMC_MASK_RXDAVLIE                  ((uint32_t)0x00200000U)        /*!<Data available in Rx FIFO interrupt Enable */
-#define  SDMMC_MASK_SDIOITIE                  ((uint32_t)0x00400000U)        /*!<SDIO Mode Interrupt Received interrupt Enable */
-
-/*****************  Bit definition for SDMMC_FIFOCNT register  *****************/
-#define  SDMMC_FIFOCNT_FIFOCOUNT              ((uint32_t)0x00FFFFFFU)        /*!<Remaining number of words to be written to or read from the FIFO */
-
-/******************  Bit definition for SDMMC_FIFO register  *******************/
-#define  SDMMC_FIFO_FIFODATA                  ((uint32_t)0xFFFFFFFFU)        /*!<Receive and transmit FIFO data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface (SPI)                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        ((uint32_t)0x00000001U)            /*!<Clock Phase      */
-#define  SPI_CR1_CPOL                        ((uint32_t)0x00000002U)            /*!<Clock Polarity   */
-#define  SPI_CR1_MSTR                        ((uint32_t)0x00000004U)            /*!<Master Selection */
-
-#define  SPI_CR1_BR                          ((uint32_t)0x00000038U)            /*!<BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        ((uint32_t)0x00000008U)            /*!<Bit 0 */
-#define  SPI_CR1_BR_1                        ((uint32_t)0x00000010U)            /*!<Bit 1 */
-#define  SPI_CR1_BR_2                        ((uint32_t)0x00000020U)            /*!<Bit 2 */
-
-#define  SPI_CR1_SPE                         ((uint32_t)0x00000040U)            /*!<SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    ((uint32_t)0x00000080U)            /*!<Frame Format                        */
-#define  SPI_CR1_SSI                         ((uint32_t)0x00000100U)            /*!<Internal slave select               */
-#define  SPI_CR1_SSM                         ((uint32_t)0x00000200U)            /*!<Software slave management           */
-#define  SPI_CR1_RXONLY                      ((uint32_t)0x00000400U)            /*!<Receive only                        */
-#define  SPI_CR1_CRCL                        ((uint32_t)0x00000800U)            /*!< CRC Length */
-#define  SPI_CR1_CRCNEXT                     ((uint32_t)0x00001000U)            /*!<Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       ((uint32_t)0x00002000U)            /*!<Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      ((uint32_t)0x00004000U)            /*!<Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    ((uint32_t)0x00008000U)            /*!<Bidirectional data mode enable      */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     ((uint32_t)0x00000001U)            /*!< Rx Buffer DMA Enable */
-#define  SPI_CR2_TXDMAEN                     ((uint32_t)0x00000002U)            /*!< Tx Buffer DMA Enable */
-#define  SPI_CR2_SSOE                        ((uint32_t)0x00000004U)            /*!< SS Output Enable */
-#define  SPI_CR2_NSSP                        ((uint32_t)0x00000008U)            /*!< NSS pulse management Enable */
-#define  SPI_CR2_FRF                         ((uint32_t)0x00000010U)            /*!< Frame Format Enable */
-#define  SPI_CR2_ERRIE                       ((uint32_t)0x00000020U)            /*!< Error Interrupt Enable */
-#define  SPI_CR2_RXNEIE                      ((uint32_t)0x00000040U)            /*!< RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       ((uint32_t)0x00000080U)            /*!< Tx buffer Empty Interrupt Enable */
-#define  SPI_CR2_DS                          ((uint32_t)0x00000F00U)            /*!< DS[3:0] Data Size */
-#define  SPI_CR2_DS_0                        ((uint32_t)0x00000100U)            /*!< Bit 0 */
-#define  SPI_CR2_DS_1                        ((uint32_t)0x00000200U)            /*!< Bit 1 */
-#define  SPI_CR2_DS_2                        ((uint32_t)0x00000400U)            /*!< Bit 2 */
-#define  SPI_CR2_DS_3                        ((uint32_t)0x00000800U)            /*!< Bit 3 */
-#define  SPI_CR2_FRXTH                       ((uint32_t)0x00001000U)            /*!< FIFO reception Threshold */
-#define  SPI_CR2_LDMARX                      ((uint32_t)0x00002000U)            /*!< Last DMA transfer for reception */
-#define  SPI_CR2_LDMATX                      ((uint32_t)0x00004000U)            /*!< Last DMA transfer for transmission */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         ((uint32_t)0x00000001U)            /*!< Receive buffer Not Empty */
-#define  SPI_SR_TXE                          ((uint32_t)0x00000002U)            /*!< Transmit buffer Empty */
-#define  SPI_SR_CHSIDE                       ((uint32_t)0x00000004U)            /*!< Channel side */
-#define  SPI_SR_UDR                          ((uint32_t)0x00000008U)            /*!< Underrun flag */
-#define  SPI_SR_CRCERR                       ((uint32_t)0x00000010U)            /*!< CRC Error flag */
-#define  SPI_SR_MODF                         ((uint32_t)0x00000020U)            /*!< Mode fault */
-#define  SPI_SR_OVR                          ((uint32_t)0x00000040U)            /*!< Overrun flag */
-#define  SPI_SR_BSY                          ((uint32_t)0x00000080U)            /*!< Busy flag */
-#define  SPI_SR_FRE                          ((uint32_t)0x00000100U)            /*!< TI frame format error */
-#define  SPI_SR_FRLVL                        ((uint32_t)0x00000600U)            /*!< FIFO Reception Level */
-#define  SPI_SR_FRLVL_0                      ((uint32_t)0x00000200U)            /*!< Bit 0 */
-#define  SPI_SR_FRLVL_1                      ((uint32_t)0x00000400U)            /*!< Bit 1 */
-#define  SPI_SR_FTLVL                        ((uint32_t)0x00001800U)            /*!< FIFO Transmission Level */
-#define  SPI_SR_FTLVL_0                      ((uint32_t)0x00000800U)            /*!< Bit 0 */
-#define  SPI_SR_FTLVL_1                      ((uint32_t)0x00001000U)            /*!< Bit 1 */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           ((uint32_t)0x0000FFFFU)            /*!<Data Register           */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   ((uint32_t)0x0000FFFFU)            /*!<CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    ((uint32_t)0x0000FFFFU)            /*!<Rx CRC Register         */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    ((uint32_t)0x0000FFFFU)            /*!<Tx CRC Register         */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    QUADSPI                                 */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for QUADSPI_CR register  *******************/
-#define  QUADSPI_CR_EN                           ((uint32_t)0x00000001U)            /*!< Enable */
-#define  QUADSPI_CR_ABORT                        ((uint32_t)0x00000002U)            /*!< Abort request */
-#define  QUADSPI_CR_DMAEN                        ((uint32_t)0x00000004U)            /*!< DMA Enable */
-#define  QUADSPI_CR_TCEN                         ((uint32_t)0x00000008U)            /*!< Timeout Counter Enable */
-#define  QUADSPI_CR_SSHIFT                       ((uint32_t)0x00000010U)            /*!< Sample Shift */
-#define  QUADSPI_CR_FTHRES                       ((uint32_t)0x00000F00U)            /*!< FTHRES[3:0] FIFO Level */
-#define  QUADSPI_CR_TEIE                         ((uint32_t)0x00010000U)            /*!< Transfer Error Interrupt Enable */
-#define  QUADSPI_CR_TCIE                         ((uint32_t)0x00020000U)            /*!< Transfer Complete Interrupt Enable */
-#define  QUADSPI_CR_FTIE                         ((uint32_t)0x00040000U)            /*!< FIFO Threshold Interrupt Enable */
-#define  QUADSPI_CR_SMIE                         ((uint32_t)0x00080000U)            /*!< Status Match Interrupt Enable */
-#define  QUADSPI_CR_TOIE                         ((uint32_t)0x00100000U)            /*!< TimeOut Interrupt Enable */
-#define  QUADSPI_CR_APMS                         ((uint32_t)0x00400000U)            /*!< Automatic Polling Mode Stop */
-#define  QUADSPI_CR_PMM                          ((uint32_t)0x00800000U)            /*!< Polling Match Mode */
-#define  QUADSPI_CR_PRESCALER                    ((uint32_t)0xFF000000U)            /*!< PRESCALER[7:0] Clock prescaler */
-
-/*****************  Bit definition for QUADSPI_DCR register  ******************/
-#define  QUADSPI_DCR_CKMODE                      ((uint32_t)0x00000001U)            /*!< Mode 0 / Mode 3 */
-#define  QUADSPI_DCR_CSHT                        ((uint32_t)0x00000700U)            /*!< CSHT[2:0]: ChipSelect High Time */
-#define  QUADSPI_DCR_CSHT_0                      ((uint32_t)0x00000100U)            /*!< Bit 0 */
-#define  QUADSPI_DCR_CSHT_1                      ((uint32_t)0x00000200U)            /*!< Bit 1 */
-#define  QUADSPI_DCR_CSHT_2                      ((uint32_t)0x00000400U)            /*!< Bit 2 */
-#define  QUADSPI_DCR_FSIZE                       ((uint32_t)0x001F0000U)            /*!< FSIZE[4:0]: Flash Size */
-
-/******************  Bit definition for QUADSPI_SR register  *******************/
-#define  QUADSPI_SR_TEF                          ((uint32_t)0x00000001U)             /*!< Transfer Error Flag */
-#define  QUADSPI_SR_TCF                          ((uint32_t)0x00000002U)             /*!< Transfer Complete Flag */
-#define  QUADSPI_SR_FTF                          ((uint32_t)0x00000004U)             /*!< FIFO Threshlod Flag */
-#define  QUADSPI_SR_SMF                          ((uint32_t)0x00000008U)             /*!< Status Match Flag */
-#define  QUADSPI_SR_TOF                          ((uint32_t)0x00000010U)             /*!< Timeout Flag */
-#define  QUADSPI_SR_BUSY                         ((uint32_t)0x00000020U)             /*!< Busy */
-#define  QUADSPI_SR_FLEVEL                       ((uint32_t)0x00001F00U)             /*!< FIFO Threshlod Flag */
-
-/******************  Bit definition for QUADSPI_FCR register  ******************/
-#define  QUADSPI_FCR_CTEF                        ((uint32_t)0x00000001U)             /*!< Clear Transfer Error Flag */
-#define  QUADSPI_FCR_CTCF                        ((uint32_t)0x00000002U)             /*!< Clear Transfer Complete Flag */
-#define  QUADSPI_FCR_CSMF                        ((uint32_t)0x00000008U)             /*!< Clear Status Match Flag */
-#define  QUADSPI_FCR_CTOF                        ((uint32_t)0x00000010U)             /*!< Clear Timeout Flag */
-
-/******************  Bit definition for QUADSPI_DLR register  ******************/
-#define  QUADSPI_DLR_DL                        ((uint32_t)0xFFFFFFFFU)               /*!< DL[31:0]: Data Length */
-
-/******************  Bit definition for QUADSPI_CCR register  ******************/
-#define  QUADSPI_CCR_INSTRUCTION                  ((uint32_t)0x000000FFU)            /*!< INSTRUCTION[7:0]: Instruction */
-#define  QUADSPI_CCR_IMODE                        ((uint32_t)0x00000300U)            /*!< IMODE[1:0]: Instruction Mode */
-#define  QUADSPI_CCR_IMODE_0                      ((uint32_t)0x00000100U)            /*!< Bit 0 */
-#define  QUADSPI_CCR_IMODE_1                      ((uint32_t)0x00000200U)            /*!< Bit 1 */
-#define  QUADSPI_CCR_ADMODE                       ((uint32_t)0x00000C00U)            /*!< ADMODE[1:0]: Address Mode */
-#define  QUADSPI_CCR_ADMODE_0                     ((uint32_t)0x00000400U)            /*!< Bit 0 */
-#define  QUADSPI_CCR_ADMODE_1                     ((uint32_t)0x00000800U)            /*!< Bit 1 */
-#define  QUADSPI_CCR_ADSIZE                       ((uint32_t)0x00003000U)            /*!< ADSIZE[1:0]: Address Size */
-#define  QUADSPI_CCR_ADSIZE_0                     ((uint32_t)0x00001000U)            /*!< Bit 0 */
-#define  QUADSPI_CCR_ADSIZE_1                     ((uint32_t)0x00002000U)            /*!< Bit 1 */
-#define  QUADSPI_CCR_ABMODE                       ((uint32_t)0x0000C000U)            /*!< ABMODE[1:0]: Alternate Bytes Mode */
-#define  QUADSPI_CCR_ABMODE_0                     ((uint32_t)0x00004000U)            /*!< Bit 0 */
-#define  QUADSPI_CCR_ABMODE_1                     ((uint32_t)0x00008000U)            /*!< Bit 1 */
-#define  QUADSPI_CCR_ABSIZE                       ((uint32_t)0x00030000U)            /*!< ABSIZE[1:0]: Instruction Mode */
-#define  QUADSPI_CCR_ABSIZE_0                     ((uint32_t)0x00010000U)            /*!< Bit 0 */
-#define  QUADSPI_CCR_ABSIZE_1                     ((uint32_t)0x00020000U)            /*!< Bit 1 */
-#define  QUADSPI_CCR_DCYC                         ((uint32_t)0x007C0000U)            /*!< DCYC[4:0]: Dummy Cycles */
-#define  QUADSPI_CCR_DMODE                        ((uint32_t)0x03000000U)            /*!< DMODE[1:0]: Data Mode */
-#define  QUADSPI_CCR_DMODE_0                      ((uint32_t)0x01000000U)            /*!< Bit 0 */
-#define  QUADSPI_CCR_DMODE_1                      ((uint32_t)0x02000000U)            /*!< Bit 1 */
-#define  QUADSPI_CCR_FMODE                        ((uint32_t)0x0C000000U)            /*!< FMODE[1:0]: Functional Mode */
-#define  QUADSPI_CCR_FMODE_0                      ((uint32_t)0x04000000U)            /*!< Bit 0 */
-#define  QUADSPI_CCR_FMODE_1                      ((uint32_t)0x08000000U)            /*!< Bit 1 */
-#define  QUADSPI_CCR_SIOO                         ((uint32_t)0x10000000U)            /*!< SIOO: Send Instruction Only Once Mode */
-#define  QUADSPI_CCR_DDRM                         ((uint32_t)0x80000000U)            /*!< DDRM: Double Data Rate Mode */
-
-/******************  Bit definition for QUADSPI_AR register  *******************/
-#define  QUADSPI_AR_ADDRESS                       ((uint32_t)0xFFFFFFFFU)            /*!< ADDRESS[31:0]: Address */
-
-/******************  Bit definition for QUADSPI_ABR register  ******************/
-#define  QUADSPI_ABR_ALTERNATE                    ((uint32_t)0xFFFFFFFFU)            /*!< ALTERNATE[31:0]: Alternate Bytes */
-
-/******************  Bit definition for QUADSPI_DR register  *******************/
-#define  QUADSPI_DR_DATA                          ((uint32_t)0xFFFFFFFFU)            /*!< DATA[31:0]: Data */
-
-/******************  Bit definition for QUADSPI_PSMKR register  ****************/
-#define  QUADSPI_PSMKR_MASK                       ((uint32_t)0xFFFFFFFFU)            /*!< MASK[31:0]: Status Mask */
-
-/******************  Bit definition for QUADSPI_PSMAR register  ****************/
-#define  QUADSPI_PSMAR_MATCH                      ((uint32_t)0xFFFFFFFFU)            /*!< MATCH[31:0]: Status Match */
-
-/******************  Bit definition for QUADSPI_PIR register  *****************/
-#define  QUADSPI_PIR_INTERVAL                     ((uint32_t)0x0000FFFFU)            /*!< INTERVAL[15:0]: Polling Interval */
-
-/******************  Bit definition for QUADSPI_LPTR register  *****************/
-#define  QUADSPI_LPTR_TIMEOUT                     ((uint32_t)0x0000FFFFU)            /*!< TIMEOUT[15:0]: Timeout period */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 SYSCFG                                     */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SYSCFG_MEMRMP register  ***************/
-#define SYSCFG_MEMRMP_MEM_MODE          ((uint32_t)0x00000007U) /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        ((uint32_t)0x00000001U)
-#define SYSCFG_MEMRMP_MEM_MODE_1        ((uint32_t)0x00000002U)
-#define SYSCFG_MEMRMP_MEM_MODE_2        ((uint32_t)0x00000004U)
-
-#define SYSCFG_MEMRMP_FB_MODE           ((uint32_t)0x00000100U) /*!< Flash Bank mode selection */
-
-
-/******************  Bit definition for SYSCFG_CFGR1 register  ******************/
-#define SYSCFG_CFGR1_FWDIS                  ((uint32_t)0x00000001U) /*!< FIREWALL access enable*/
-#define SYSCFG_CFGR1_BOOSTEN                ((uint32_t)0x00000100U) /*!< I/O analog switch voltage booster enable */
-#define SYSCFG_CFGR1_I2C_PB6_FMP            ((uint32_t)0x00010000U) /*!< I2C PB6 Fast mode plus */
-#define SYSCFG_CFGR1_I2C_PB7_FMP            ((uint32_t)0x00020000U) /*!< I2C PB7 Fast mode plus */
-#define SYSCFG_CFGR1_I2C_PB8_FMP            ((uint32_t)0x00040000U) /*!< I2C PB8 Fast mode plus */
-#define SYSCFG_CFGR1_I2C_PB9_FMP            ((uint32_t)0x00080000U) /*!< I2C PB9 Fast mode plus */
-#define SYSCFG_CFGR1_I2C1_FMP               ((uint32_t)0x00100000U) /*!< I2C1 Fast mode plus */
-#define SYSCFG_CFGR1_I2C2_FMP               ((uint32_t)0x00200000U) /*!< I2C2 Fast mode plus */
-#define SYSCFG_CFGR1_I2C3_FMP               ((uint32_t)0x00400000U) /*!< I2C3 Fast mode plus */
-#define SYSCFG_CFGR1_FPU_IE_0               ((uint32_t)0x04000000U) /*!<  Invalid operation Interrupt enable */
-#define SYSCFG_CFGR1_FPU_IE_1               ((uint32_t)0x08000000U) /*!<  Divide-by-zero Interrupt enable */
-#define SYSCFG_CFGR1_FPU_IE_2               ((uint32_t)0x10000000U) /*!<  Underflow Interrupt enable */
-#define SYSCFG_CFGR1_FPU_IE_3               ((uint32_t)0x20000000U) /*!<  Overflow Interrupt enable */
-#define SYSCFG_CFGR1_FPU_IE_4               ((uint32_t)0x40000000U) /*!<  Input denormal Interrupt enable */
-#define SYSCFG_CFGR1_FPU_IE_5               ((uint32_t)0x80000000U) /*!<  Inexact Interrupt enable (interrupt disabled at reset) */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            ((uint32_t)0x00000007U) /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            ((uint32_t)0x00000070U) /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            ((uint32_t)0x00000700U) /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            ((uint32_t)0x00007000U) /*!<EXTI 3 configuration */
-/**
-  * @brief   EXTI0 configuration
-  */
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000U) /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001U) /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002U) /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003U) /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004U) /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000005U) /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000006U) /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000007U) /*!<PH[0] pin */
-
-
-/**
-  * @brief   EXTI1 configuration
-  */
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000U) /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010U) /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020U) /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030U) /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040U) /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000050U) /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000060U) /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000070U) /*!<PH[1] pin */
-
-/**
-  * @brief   EXTI2 configuration
-  */
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000U) /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100U) /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200U) /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300U) /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400U) /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000500U) /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000600U) /*!<PG[2] pin */
-
-
-/**
-  * @brief   EXTI3 configuration
-  */
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000U) /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000U) /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000U) /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000U) /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000U) /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00005000U) /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00006000U) /*!<PG[3] pin */
-
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            ((uint32_t)0x00000007U) /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            ((uint32_t)0x00000070U) /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            ((uint32_t)0x00000700U) /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            ((uint32_t)0x00007000U) /*!<EXTI 7 configuration */
-/**
-  * @brief   EXTI4 configuration
-  */
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000U) /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001U) /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002U) /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003U) /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004U) /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000005U) /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000006U) /*!<PG[4] pin */
-
-/**
-  * @brief   EXTI5 configuration
-  */
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000U) /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010U) /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020U) /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030U) /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040U) /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000050U) /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000060U) /*!<PG[5] pin */
-
-/**
-  * @brief   EXTI6 configuration
-  */
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000U) /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100U) /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200U) /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300U) /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400U) /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000500U) /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000600U) /*!<PG[6] pin */
-
-/**
-  * @brief   EXTI7 configuration
-  */
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000U) /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000U) /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000U) /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000U) /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000U) /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00005000U) /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00006000U) /*!<PG[7] pin */
-
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            ((uint32_t)0x00000007U) /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            ((uint32_t)0x00000070U) /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           ((uint32_t)0x00000700U) /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           ((uint32_t)0x00007000U) /*!<EXTI 11 configuration */
-
-/**
-  * @brief   EXTI8 configuration
-  */
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000U) /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001U) /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002U) /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003U) /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004U) /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000005U) /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000006U) /*!<PG[8] pin */
-
-/**
-  * @brief   EXTI9 configuration
-  */
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000U) /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010U) /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020U) /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030U) /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040U) /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000050U) /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000060U) /*!<PG[9] pin */
-
-/**
-  * @brief   EXTI10 configuration
-  */
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000U) /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100U) /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200U) /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300U) /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400U) /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000500U) /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000600U) /*!<PG[10] pin */
-
-/**
-  * @brief   EXTI11 configuration
-  */
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000U) /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000U) /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000U) /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000U) /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000U) /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00005000U) /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00006000U) /*!<PG[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           ((uint32_t)0x00000007U) /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           ((uint32_t)0x00000070U) /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           ((uint32_t)0x00000700U) /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           ((uint32_t)0x00007000U) /*!<EXTI 15 configuration */
-/**
-  * @brief   EXTI12 configuration
-  */
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000U) /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001U) /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002U) /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003U) /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004U) /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000005U) /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000006U) /*!<PG[12] pin */
-
-/**
-  * @brief   EXTI13 configuration
-  */
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000U) /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010U) /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020U) /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030U) /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040U) /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000050U) /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000060U) /*!<PG[13] pin */
-
-/**
-  * @brief   EXTI14 configuration
-  */
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000U) /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100U) /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200U) /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300U) /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400U) /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000500U) /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000600U) /*!<PG[14] pin */
-
-/**
-  * @brief   EXTI15 configuration
-  */
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000U) /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000U) /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000U) /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000U) /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000U) /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00005000U) /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00006000U) /*!<PG[15] pin */
-
-/******************  Bit definition for SYSCFG_SCSR register  ****************/
-#define SYSCFG_SCSR_SRAM2ER             ((uint32_t)0x00000001U) /*!< SRAM2 Erase Request */
-#define SYSCFG_SCSR_SRAM2BSY            ((uint32_t)0x00000002U) /*!< SRAM2 Erase Ongoing */
-
-/******************  Bit definition for SYSCFG_CFGR2 register  ****************/
-#define SYSCFG_CFGR2_CLL                ((uint32_t)0x00000001U) /*!< Core Lockup Lock */
-#define SYSCFG_CFGR2_SPL                ((uint32_t)0x00000002U) /*!< SRAM Parity Lock*/
-#define SYSCFG_CFGR2_PVDL               ((uint32_t)0x00000004U) /*!<  PVD Lock */
-#define SYSCFG_CFGR2_ECCL               ((uint32_t)0x00000008U) /*!< ECC Lock*/
-#define SYSCFG_CFGR2_SPF                ((uint32_t)0x00000100U) /*!< SRAM Parity Flag */
-
-/******************  Bit definition for SYSCFG_SWPR register  ****************/
-#define SYSCFG_SWPR_PAGE0          ((uint32_t)0x00000001U) /*!< SRAM2 Write protection page 0 */
-#define SYSCFG_SWPR_PAGE1          ((uint32_t)0x00000002U) /*!< SRAM2 Write protection page 1 */
-#define SYSCFG_SWPR_PAGE2          ((uint32_t)0x00000004U) /*!< SRAM2 Write protection page 2 */
-#define SYSCFG_SWPR_PAGE3          ((uint32_t)0x00000008U) /*!< SRAM2 Write protection page 3 */
-#define SYSCFG_SWPR_PAGE4          ((uint32_t)0x00000010U) /*!< SRAM2 Write protection page 4 */
-#define SYSCFG_SWPR_PAGE5          ((uint32_t)0x00000020U) /*!< SRAM2 Write protection page 5 */
-#define SYSCFG_SWPR_PAGE6          ((uint32_t)0x00000040U) /*!< SRAM2 Write protection page 6 */
-#define SYSCFG_SWPR_PAGE7          ((uint32_t)0x00000080U) /*!< SRAM2 Write protection page 7 */
-#define SYSCFG_SWPR_PAGE8          ((uint32_t)0x00000100U) /*!< SRAM2 Write protection page 8 */
-#define SYSCFG_SWPR_PAGE9          ((uint32_t)0x00000200U) /*!< SRAM2 Write protection page 9 */
-#define SYSCFG_SWPR_PAGE10         ((uint32_t)0x00000400U) /*!< SRAM2 Write protection page 10*/
-#define SYSCFG_SWPR_PAGE11         ((uint32_t)0x00000800U) /*!< SRAM2 Write protection page 11*/
-#define SYSCFG_SWPR_PAGE12         ((uint32_t)0x00001000U) /*!< SRAM2 Write protection page 12*/
-#define SYSCFG_SWPR_PAGE13         ((uint32_t)0x00002000U) /*!< SRAM2 Write protection page 13*/
-#define SYSCFG_SWPR_PAGE14         ((uint32_t)0x00004000U) /*!< SRAM2 Write protection page 14*/
-#define SYSCFG_SWPR_PAGE15         ((uint32_t)0x00008000U) /*!< SRAM2 Write protection page 15*/
-#define SYSCFG_SWPR_PAGE16         ((uint32_t)0x00010000U) /*!< SRAM2 Write protection page 16*/
-#define SYSCFG_SWPR_PAGE17         ((uint32_t)0x00020000U) /*!< SRAM2 Write protection page 17*/
-#define SYSCFG_SWPR_PAGE18         ((uint32_t)0x00040000U) /*!< SRAM2 Write protection page 18*/
-#define SYSCFG_SWPR_PAGE19         ((uint32_t)0x00080000U) /*!< SRAM2 Write protection page 19*/
-#define SYSCFG_SWPR_PAGE20         ((uint32_t)0x00100000U) /*!< SRAM2 Write protection page 20*/
-#define SYSCFG_SWPR_PAGE21         ((uint32_t)0x00200000U) /*!< SRAM2 Write protection page 21*/
-#define SYSCFG_SWPR_PAGE22         ((uint32_t)0x00400000U) /*!< SRAM2 Write protection page 22*/
-#define SYSCFG_SWPR_PAGE23         ((uint32_t)0x00800000U) /*!< SRAM2 Write protection page 23*/
-#define SYSCFG_SWPR_PAGE24         ((uint32_t)0x01000000U) /*!< SRAM2 Write protection page 24*/
-#define SYSCFG_SWPR_PAGE25         ((uint32_t)0x02000000U) /*!< SRAM2 Write protection page 25*/
-#define SYSCFG_SWPR_PAGE26         ((uint32_t)0x04000000U) /*!< SRAM2 Write protection page 26*/
-#define SYSCFG_SWPR_PAGE27         ((uint32_t)0x08000000U) /*!< SRAM2 Write protection page 27*/
-#define SYSCFG_SWPR_PAGE28         ((uint32_t)0x10000000U) /*!< SRAM2 Write protection page 28*/
-#define SYSCFG_SWPR_PAGE29         ((uint32_t)0x20000000U) /*!< SRAM2 Write protection page 29*/
-#define SYSCFG_SWPR_PAGE30         ((uint32_t)0x40000000U) /*!< SRAM2 Write protection page 30*/
-#define SYSCFG_SWPR_PAGE31         ((uint32_t)0x80000000U) /*!< SRAM2 Write protection page 31*/
-
-/******************  Bit definition for SYSCFG_SKR register  ****************/
-#define SYSCFG_SKR_KEY             ((uint32_t)0x000000FFU) /*!<  SRAM2 write protection key for software erase  */
-
-
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    TIM                                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN               ((uint32_t)0x00000001U)            /*!<Counter enable */
-#define  TIM_CR1_UDIS              ((uint32_t)0x00000002U)            /*!<Update disable */
-#define  TIM_CR1_URS               ((uint32_t)0x00000004U)            /*!<Update request source */
-#define  TIM_CR1_OPM               ((uint32_t)0x00000008U)            /*!<One pulse mode */
-#define  TIM_CR1_DIR               ((uint32_t)0x00000010U)            /*!<Direction */
-
-#define  TIM_CR1_CMS               ((uint32_t)0x00000060U)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0             ((uint32_t)0x00000020U)            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1             ((uint32_t)0x00000040U)            /*!<Bit 1 */
-
-#define  TIM_CR1_ARPE              ((uint32_t)0x00000080U)            /*!<Auto-reload preload enable */
-
-#define  TIM_CR1_CKD               ((uint32_t)0x00000300U)            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0             ((uint32_t)0x00000100U)            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1             ((uint32_t)0x00000200U)            /*!<Bit 1 */
-
-#define  TIM_CR1_UIFREMAP          ((uint32_t)0x00000800U)            /*!<Update interrupt flag remap */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC              ((uint32_t)0x00000001U)            /*!<Capture/Compare Preloaded Control */
-#define  TIM_CR2_CCUS              ((uint32_t)0x00000004U)            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS              ((uint32_t)0x00000008U)            /*!<Capture/Compare DMA Selection */
-
-#define  TIM_CR2_MMS               ((uint32_t)0x00000070U)            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0             ((uint32_t)0x00000010U)            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1             ((uint32_t)0x00000020U)            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2             ((uint32_t)0x00000040U)            /*!<Bit 2 */
-
-#define  TIM_CR2_TI1S              ((uint32_t)0x00000080U)            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1              ((uint32_t)0x00000100U)            /*!<Output Idle state 1 (OC1 output) */
-#define  TIM_CR2_OIS1N             ((uint32_t)0x00000200U)            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2              ((uint32_t)0x00000400U)            /*!<Output Idle state 2 (OC2 output) */
-#define  TIM_CR2_OIS2N             ((uint32_t)0x00000800U)            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3              ((uint32_t)0x00001000U)            /*!<Output Idle state 3 (OC3 output) */
-#define  TIM_CR2_OIS3N             ((uint32_t)0x00002000U)            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4              ((uint32_t)0x00004000U)            /*!<Output Idle state 4 (OC4 output) */
-#define  TIM_CR2_OIS5              ((uint32_t)0x00010000U)            /*!<Output Idle state 5 (OC5 output) */
-#define  TIM_CR2_OIS6              ((uint32_t)0x00040000U)            /*!<Output Idle state 6 (OC6 output) */
-
-#define  TIM_CR2_MMS2              ((uint32_t)0x00F00000U)            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS2_0            ((uint32_t)0x00100000U)            /*!<Bit 0 */
-#define  TIM_CR2_MMS2_1            ((uint32_t)0x00200000U)            /*!<Bit 1 */
-#define  TIM_CR2_MMS2_2            ((uint32_t)0x00400000U)            /*!<Bit 2 */
-#define  TIM_CR2_MMS2_3            ((uint32_t)0x00800000U)            /*!<Bit 2 */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS              ((uint32_t)0x00010007U)            /*!<SMS[2:0] bits (Slave mode selection) */
-#define  TIM_SMCR_SMS_0            ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1            ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2            ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define  TIM_SMCR_SMS_3            ((uint32_t)0x00010000U)            /*!<Bit 3 */
-
-#define  TIM_SMCR_OCCS             ((uint32_t)0x00000008U)            /*!< OCREF clear selection */
-
-#define  TIM_SMCR_TS               ((uint32_t)0x00000070U)            /*!<TS[2:0] bits (Trigger selection) */
-#define  TIM_SMCR_TS_0             ((uint32_t)0x00000010U)            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1             ((uint32_t)0x00000020U)            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2             ((uint32_t)0x00000040U)            /*!<Bit 2 */
-
-#define  TIM_SMCR_MSM              ((uint32_t)0x00000080U)            /*!<Master/slave mode */
-
-#define  TIM_SMCR_ETF              ((uint32_t)0x00000F00U)            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0            ((uint32_t)0x00000100U)            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1            ((uint32_t)0x00000200U)            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2            ((uint32_t)0x00000400U)            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3            ((uint32_t)0x00000800U)            /*!<Bit 3 */
-
-#define  TIM_SMCR_ETPS             ((uint32_t)0x00003000U)            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0           ((uint32_t)0x00001000U)            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1           ((uint32_t)0x00002000U)            /*!<Bit 1 */
-
-#define  TIM_SMCR_ECE              ((uint32_t)0x00004000U)            /*!<External clock enable */
-#define  TIM_SMCR_ETP              ((uint32_t)0x00008000U)            /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE              ((uint32_t)0x00000001U)            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE            ((uint32_t)0x00000002U)            /*!<Capture/Compare 1 interrupt enable */
-#define  TIM_DIER_CC2IE            ((uint32_t)0x00000004U)            /*!<Capture/Compare 2 interrupt enable */
-#define  TIM_DIER_CC3IE            ((uint32_t)0x00000008U)            /*!<Capture/Compare 3 interrupt enable */
-#define  TIM_DIER_CC4IE            ((uint32_t)0x00000010U)            /*!<Capture/Compare 4 interrupt enable */
-#define  TIM_DIER_COMIE            ((uint32_t)0x00000020U)            /*!<COM interrupt enable */
-#define  TIM_DIER_TIE              ((uint32_t)0x00000040U)            /*!<Trigger interrupt enable */
-#define  TIM_DIER_BIE              ((uint32_t)0x00000080U)            /*!<Break interrupt enable */
-#define  TIM_DIER_UDE              ((uint32_t)0x00000100U)            /*!<Update DMA request enable */
-#define  TIM_DIER_CC1DE            ((uint32_t)0x00000200U)            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE            ((uint32_t)0x00000400U)            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE            ((uint32_t)0x00000800U)            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE            ((uint32_t)0x00001000U)            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE            ((uint32_t)0x00002000U)            /*!<COM DMA request enable */
-#define  TIM_DIER_TDE              ((uint32_t)0x00004000U)            /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                ((uint32_t)0x00000001U)            /*!<Update interrupt Flag */
-#define  TIM_SR_CC1IF              ((uint32_t)0x00000002U)            /*!<Capture/Compare 1 interrupt Flag */
-#define  TIM_SR_CC2IF              ((uint32_t)0x00000004U)            /*!<Capture/Compare 2 interrupt Flag */
-#define  TIM_SR_CC3IF              ((uint32_t)0x00000008U)            /*!<Capture/Compare 3 interrupt Flag */
-#define  TIM_SR_CC4IF              ((uint32_t)0x00000010U)            /*!<Capture/Compare 4 interrupt Flag */
-#define  TIM_SR_COMIF              ((uint32_t)0x00000020U)            /*!<COM interrupt Flag */
-#define  TIM_SR_TIF                ((uint32_t)0x00000040U)            /*!<Trigger interrupt Flag */
-#define  TIM_SR_BIF                ((uint32_t)0x00000080U)            /*!<Break interrupt Flag */
-#define  TIM_SR_B2IF               ((uint32_t)0x00000100U)            /*!<Break 2 interrupt Flag */
-#define  TIM_SR_CC1OF              ((uint32_t)0x00000200U)            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF              ((uint32_t)0x00000400U)            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF              ((uint32_t)0x00000800U)            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF              ((uint32_t)0x00001000U)            /*!<Capture/Compare 4 Overcapture Flag */
-#define  TIM_SR_SBIF               ((uint32_t)0x00002000U)            /*!<System Break interrupt Flag */
-#define  TIM_SR_CC5IF              ((uint32_t)0x00010000U)            /*!<Capture/Compare 5 interrupt Flag */
-#define  TIM_SR_CC6IF              ((uint32_t)0x00020000U)            /*!<Capture/Compare 6 interrupt Flag */
-
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                ((uint32_t)0x00000001U)            /*!<Update Generation */
-#define  TIM_EGR_CC1G              ((uint32_t)0x00000002U)            /*!<Capture/Compare 1 Generation */
-#define  TIM_EGR_CC2G              ((uint32_t)0x00000004U)            /*!<Capture/Compare 2 Generation */
-#define  TIM_EGR_CC3G              ((uint32_t)0x00000008U)            /*!<Capture/Compare 3 Generation */
-#define  TIM_EGR_CC4G              ((uint32_t)0x00000010U)            /*!<Capture/Compare 4 Generation */
-#define  TIM_EGR_COMG              ((uint32_t)0x00000020U)            /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                ((uint32_t)0x00000040U)            /*!<Trigger Generation */
-#define  TIM_EGR_BG                ((uint32_t)0x00000080U)            /*!<Break Generation */
-#define  TIM_EGR_B2G               ((uint32_t)0x00000100U)            /*!<Break 2 Generation */
-
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S            ((uint32_t)0x00000003U)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0          ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1          ((uint32_t)0x00000002U)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC1FE           ((uint32_t)0x00000004U)            /*!<Output Compare 1 Fast enable */
-#define  TIM_CCMR1_OC1PE           ((uint32_t)0x00000008U)            /*!<Output Compare 1 Preload enable */
-
-#define  TIM_CCMR1_OC1M            ((uint32_t)0x00010070U)            /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define  TIM_CCMR1_OC1M_0          ((uint32_t)0x00000010U)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1          ((uint32_t)0x00000020U)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2          ((uint32_t)0x00000040U)            /*!<Bit 2 */
-#define  TIM_CCMR1_OC1M_3          ((uint32_t)0x00010000U)            /*!<Bit 3 */
-
-#define  TIM_CCMR1_OC1CE           ((uint32_t)0x00000080U)            /*!<Output Compare 1 Clear Enable */
-
-#define  TIM_CCMR1_CC2S            ((uint32_t)0x00000300U)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0          ((uint32_t)0x00000100U)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1          ((uint32_t)0x00000200U)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC2FE           ((uint32_t)0x00000400U)            /*!<Output Compare 2 Fast enable */
-#define  TIM_CCMR1_OC2PE           ((uint32_t)0x00000800U)            /*!<Output Compare 2 Preload enable */
-
-#define  TIM_CCMR1_OC2M            ((uint32_t)0x01007000U)            /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define  TIM_CCMR1_OC2M_0          ((uint32_t)0x00001000U)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1          ((uint32_t)0x00002000U)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2          ((uint32_t)0x00004000U)            /*!<Bit 2 */
-#define  TIM_CCMR1_OC2M_3          ((uint32_t)0x01000000U)            /*!<Bit 3 */
-
-#define  TIM_CCMR1_OC2CE           ((uint32_t)0x00008000U)            /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-#define  TIM_CCMR1_IC1PSC          ((uint32_t)0x0000000CU)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0        ((uint32_t)0x00000004U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1        ((uint32_t)0x00000008U)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC1F            ((uint32_t)0x000000F0U)            /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define  TIM_CCMR1_IC1F_0          ((uint32_t)0x00000010U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1          ((uint32_t)0x00000020U)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2          ((uint32_t)0x00000040U)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3          ((uint32_t)0x00000080U)            /*!<Bit 3 */
-
-#define  TIM_CCMR1_IC2PSC          ((uint32_t)0x00000C00U)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define  TIM_CCMR1_IC2PSC_0        ((uint32_t)0x00000400U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1        ((uint32_t)0x00000800U)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC2F            ((uint32_t)0x0000F000U)            /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define  TIM_CCMR1_IC2F_0          ((uint32_t)0x00001000U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1          ((uint32_t)0x00002000U)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2          ((uint32_t)0x00004000U)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3          ((uint32_t)0x00008000U)            /*!<Bit 3 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S            ((uint32_t)0x00000003U)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define  TIM_CCMR2_CC3S_0          ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1          ((uint32_t)0x00000002U)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC3FE           ((uint32_t)0x00000004U)            /*!<Output Compare 3 Fast enable */
-#define  TIM_CCMR2_OC3PE           ((uint32_t)0x00000008U)            /*!<Output Compare 3 Preload enable */
-
-#define  TIM_CCMR2_OC3M            ((uint32_t)0x00010070U)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0          ((uint32_t)0x00000010U)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1          ((uint32_t)0x00000020U)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2          ((uint32_t)0x00000040U)            /*!<Bit 2 */
-#define  TIM_CCMR2_OC3M_3          ((uint32_t)0x00010000U)            /*!<Bit 3 */
-
-#define  TIM_CCMR2_OC3CE           ((uint32_t)0x00000080U)            /*!<Output Compare 3 Clear Enable */
-
-#define  TIM_CCMR2_CC4S            ((uint32_t)0x00000300U)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0          ((uint32_t)0x00000100U)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1          ((uint32_t)0x00000200U)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC4FE           ((uint32_t)0x00000400U)            /*!<Output Compare 4 Fast enable */
-#define  TIM_CCMR2_OC4PE           ((uint32_t)0x00000800U)            /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR2_OC4M            ((uint32_t)0x01007000U)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0          ((uint32_t)0x00001000U)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1          ((uint32_t)0x00002000U)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2          ((uint32_t)0x00004000U)            /*!<Bit 2 */
-#define  TIM_CCMR2_OC4M_3          ((uint32_t)0x01000000U)            /*!<Bit 3 */
-
-#define  TIM_CCMR2_OC4CE           ((uint32_t)0x00008000U)            /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-#define  TIM_CCMR2_IC3PSC          ((uint32_t)0x0000000CU)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0        ((uint32_t)0x00000004U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1        ((uint32_t)0x00000008U)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC3F            ((uint32_t)0x000000F0U)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0          ((uint32_t)0x00000010U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1          ((uint32_t)0x00000020U)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2          ((uint32_t)0x00000040U)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3          ((uint32_t)0x00000080U)            /*!<Bit 3 */
-
-#define  TIM_CCMR2_IC4PSC          ((uint32_t)0x00000C00U)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0        ((uint32_t)0x00000400U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1        ((uint32_t)0x00000800U)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC4F            ((uint32_t)0x0000F000U)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0          ((uint32_t)0x00001000U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1          ((uint32_t)0x00002000U)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2          ((uint32_t)0x00004000U)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3          ((uint32_t)0x00008000U)            /*!<Bit 3 */
-
-/******************  Bit definition for TIM_CCMR3 register  *******************/
-#define  TIM_CCMR3_OC5FE           ((uint32_t)0x00000004U)            /*!<Output Compare 5 Fast enable */
-#define  TIM_CCMR3_OC5PE           ((uint32_t)0x00000008U)            /*!<Output Compare 5 Preload enable */
-
-#define  TIM_CCMR3_OC5M            ((uint32_t)0x00010070U)            /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
-#define  TIM_CCMR3_OC5M_0          ((uint32_t)0x00000010U)            /*!<Bit 0 */
-#define  TIM_CCMR3_OC5M_1          ((uint32_t)0x00000020U)            /*!<Bit 1 */
-#define  TIM_CCMR3_OC5M_2          ((uint32_t)0x00000040U)            /*!<Bit 2 */
-#define  TIM_CCMR3_OC5M_3          ((uint32_t)0x00010000U)            /*!<Bit 3 */
-
-#define  TIM_CCMR3_OC5CE           ((uint32_t)0x00000080U)            /*!<Output Compare 5 Clear Enable */
-
-#define  TIM_CCMR3_OC6FE           ((uint32_t)0x00000400U)            /*!<Output Compare 6 Fast enable */
-#define  TIM_CCMR3_OC6PE           ((uint32_t)0x00000800U)            /*!<Output Compare 6 Preload enable */
-
-#define  TIM_CCMR3_OC6M            ((uint32_t)0x01007000U)            /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
-#define  TIM_CCMR3_OC6M_0          ((uint32_t)0x00001000U)            /*!<Bit 0 */
-#define  TIM_CCMR3_OC6M_1          ((uint32_t)0x00002000U)            /*!<Bit 1 */
-#define  TIM_CCMR3_OC6M_2          ((uint32_t)0x00004000U)            /*!<Bit 2 */
-#define  TIM_CCMR3_OC6M_3          ((uint32_t)0x01000000U)            /*!<Bit 3 */
-
-#define  TIM_CCMR3_OC6CE           ((uint32_t)0x00008000U)            /*!<Output Compare 6 Clear Enable */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E             ((uint32_t)0x00000001U)            /*!<Capture/Compare 1 output enable */
-#define  TIM_CCER_CC1P             ((uint32_t)0x00000002U)            /*!<Capture/Compare 1 output Polarity */
-#define  TIM_CCER_CC1NE            ((uint32_t)0x00000004U)            /*!<Capture/Compare 1 Complementary output enable */
-#define  TIM_CCER_CC1NP            ((uint32_t)0x00000008U)            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E             ((uint32_t)0x00000010U)            /*!<Capture/Compare 2 output enable */
-#define  TIM_CCER_CC2P             ((uint32_t)0x00000020U)            /*!<Capture/Compare 2 output Polarity */
-#define  TIM_CCER_CC2NE            ((uint32_t)0x00000040U)            /*!<Capture/Compare 2 Complementary output enable */
-#define  TIM_CCER_CC2NP            ((uint32_t)0x00000080U)            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E             ((uint32_t)0x00000100U)            /*!<Capture/Compare 3 output enable */
-#define  TIM_CCER_CC3P             ((uint32_t)0x00000200U)            /*!<Capture/Compare 3 output Polarity */
-#define  TIM_CCER_CC3NE            ((uint32_t)0x00000400U)            /*!<Capture/Compare 3 Complementary output enable */
-#define  TIM_CCER_CC3NP            ((uint32_t)0x00000800U)            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E             ((uint32_t)0x00001000U)            /*!<Capture/Compare 4 output enable */
-#define  TIM_CCER_CC4P             ((uint32_t)0x00002000U)            /*!<Capture/Compare 4 output Polarity */
-#define  TIM_CCER_CC4NP            ((uint32_t)0x00008000U)            /*!<Capture/Compare 4 Complementary output Polarity */
-#define  TIM_CCER_CC5E             ((uint32_t)0x00010000U)            /*!<Capture/Compare 5 output enable */
-#define  TIM_CCER_CC5P             ((uint32_t)0x00020000U)            /*!<Capture/Compare 5 output Polarity */
-#define  TIM_CCER_CC6E             ((uint32_t)0x00100000U)            /*!<Capture/Compare 6 output enable */
-#define  TIM_CCER_CC6P             ((uint32_t)0x00200000U)            /*!<Capture/Compare 6 output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT               ((uint32_t)0xFFFFFFFFU)            /*!<Counter Value */
-#define  TIM_CNT_UIFCPY            ((uint32_t)0x80000000U)            /*!<Update interrupt flag copy (if UIFREMAP=1) */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC               ((uint32_t)0x0000FFFFU)            /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR               ((uint32_t)0xFFFFFFFFU)            /*!<Actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP               ((uint32_t)0x0000FFFFU)            /*!<Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1             ((uint32_t)0x0000FFFFU)            /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2             ((uint32_t)0x0000FFFFU)            /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3             ((uint32_t)0x0000FFFFU)            /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4             ((uint32_t)0x0000FFFFU)            /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_CCR5 register  *******************/
-#define  TIM_CCR5_CCR5             ((uint32_t)0xFFFFFFFFU)            /*!<Capture/Compare 5 Value */
-#define  TIM_CCR5_GC5C1            ((uint32_t)0x20000000U)            /*!<Group Channel 5 and Channel 1 */
-#define  TIM_CCR5_GC5C2            ((uint32_t)0x40000000U)            /*!<Group Channel 5 and Channel 2 */
-#define  TIM_CCR5_GC5C3            ((uint32_t)0x80000000U)            /*!<Group Channel 5 and Channel 3 */
-
-/*******************  Bit definition for TIM_CCR6 register  *******************/
-#define  TIM_CCR6_CCR6             ((uint32_t)0x0000FFFFU)            /*!<Capture/Compare 6 Value */
-
-/*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG              ((uint32_t)0x000000FFU)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0            ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1            ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2            ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3            ((uint32_t)0x00000008U)            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4            ((uint32_t)0x00000010U)            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5            ((uint32_t)0x00000020U)            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6            ((uint32_t)0x00000040U)            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7            ((uint32_t)0x00000080U)            /*!<Bit 7 */
-
-#define  TIM_BDTR_LOCK             ((uint32_t)0x00000300U)            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0           ((uint32_t)0x00000100U)            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1           ((uint32_t)0x00000200U)            /*!<Bit 1 */
-
-#define  TIM_BDTR_OSSI             ((uint32_t)0x00000400U)            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR             ((uint32_t)0x00000800U)            /*!<Off-State Selection for Run mode */
-#define  TIM_BDTR_BKE              ((uint32_t)0x00001000U)            /*!<Break enable for Break 1 */
-#define  TIM_BDTR_BKP              ((uint32_t)0x00002000U)            /*!<Break Polarity for Break 1 */
-#define  TIM_BDTR_AOE              ((uint32_t)0x00004000U)            /*!<Automatic Output enable */
-#define  TIM_BDTR_MOE              ((uint32_t)0x00008000U)            /*!<Main Output enable */
-
-#define  TIM_BDTR_BKF              ((uint32_t)0x000F0000U)            /*!<Break Filter for Break 1 */
-#define  TIM_BDTR_BK2F             ((uint32_t)0x00F00000U)            /*!<Break Filter for Break 2 */
-
-#define  TIM_BDTR_BK2E             ((uint32_t)0x01000000U)            /*!<Break enable for Break 2 */
-#define  TIM_BDTR_BK2P             ((uint32_t)0x02000000U)            /*!<Break Polarity for Break 2 */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA               ((uint32_t)0x0000001FU)            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0             ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1             ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2             ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3             ((uint32_t)0x00000008U)            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4             ((uint32_t)0x00000010U)            /*!<Bit 4 */
-
-#define  TIM_DCR_DBL               ((uint32_t)0x00001F00U)            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0             ((uint32_t)0x00000100U)            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1             ((uint32_t)0x00000200U)            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2             ((uint32_t)0x00000400U)            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3             ((uint32_t)0x00000800U)            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4             ((uint32_t)0x00001000U)            /*!<Bit 4 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB             ((uint32_t)0x0000FFFFU)            /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM1_OR1 register  *******************/
-#define TIM1_OR1_ETR_ADC1_RMP      ((uint32_t)0x00000003U)            /*!<ETR_ADC1_RMP[1:0] bits (TIM1 ETR remap on ADC1) */
-#define TIM1_OR1_ETR_ADC1_RMP_0    ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define TIM1_OR1_ETR_ADC1_RMP_1    ((uint32_t)0x00000002U)            /*!<Bit 1 */
-
-#define TIM1_OR1_ETR_ADC3_RMP      ((uint32_t)0x0000000CU)            /*!<ETR_ADC3_RMP[1:0] bits (TIM1 ETR remap on ADC3) */
-#define TIM1_OR1_ETR_ADC3_RMP_0    ((uint32_t)0x00000004U)            /*!<Bit 0 */
-#define TIM1_OR1_ETR_ADC3_RMP_1    ((uint32_t)0x00000008U)            /*!<Bit 1 */
-
-#define TIM1_OR1_TI1_RMP           ((uint32_t)0x00000010U)            /*!<TIM1 Input Capture 1 remap */
-
-/*******************  Bit definition for TIM1_OR2 register  *******************/
-#define TIM1_OR2_BKINE             ((uint32_t)0x00000001U)            /*!<BRK BKIN input enable */
-#define TIM1_OR2_BKCMP1E           ((uint32_t)0x00000002U)            /*!<BRK COMP1 enable */
-#define TIM1_OR2_BKCMP2E           ((uint32_t)0x00000004U)            /*!<BRK COMP2 enable */
-#define TIM1_OR2_BKDFBK0E          ((uint32_t)0x00000100U)            /*!<BRK DFSDM_BREAK[0] enable */
-#define TIM1_OR2_BKINP             ((uint32_t)0x00000200U)            /*!<BRK BKIN input polarity */
-#define TIM1_OR2_BKCMP1P           ((uint32_t)0x00000400U)            /*!<BRK COMP1 input polarity */
-#define TIM1_OR2_BKCMP2P           ((uint32_t)0x00000800U)            /*!<BRK COMP2 input polarity */
-
-#define TIM1_OR2_ETRSEL            ((uint32_t)0x0001C000U)            /*!<ETRSEL[2:0] bits (TIM1 ETR source selection) */
-#define TIM1_OR2_ETRSEL_0          ((uint32_t)0x00004000U)            /*!<Bit 0 */
-#define TIM1_OR2_ETRSEL_1          ((uint32_t)0x00008000U)            /*!<Bit 1 */
-#define TIM1_OR2_ETRSEL_2          ((uint32_t)0x00010000U)            /*!<Bit 2 */
-
-/*******************  Bit definition for TIM1_OR3 register  *******************/
-#define TIM1_OR3_BK2INE            ((uint32_t)0x00000001U)            /*!<BRK2 BKIN2 input enable */
-#define TIM1_OR3_BK2CMP1E          ((uint32_t)0x00000002U)            /*!<BRK2 COMP1 enable */
-#define TIM1_OR3_BK2CMP2E          ((uint32_t)0x00000004U)            /*!<BRK2 COMP2 enable */
-#define TIM1_OR3_BK2DFBK1E         ((uint32_t)0x00000100U)            /*!<BRK2 DFSDM_BREAK[1] enable */
-#define TIM1_OR3_BK2INP            ((uint32_t)0x00000200U)            /*!<BRK2 BKIN2 input polarity */
-#define TIM1_OR3_BK2CMP1P          ((uint32_t)0x00000400U)            /*!<BRK2 COMP1 input polarity */
-#define TIM1_OR3_BK2CMP2P          ((uint32_t)0x00000800U)            /*!<BRK2 COMP2 input polarity */
-
-/*******************  Bit definition for TIM8_OR1 register  *******************/
-#define TIM8_OR1_ETR_ADC2_RMP      ((uint32_t)0x00000003U)            /*!<ETR_ADC2_RMP[1:0] bits (TIM8 ETR remap on ADC2) */
-#define TIM8_OR1_ETR_ADC2_RMP_0    ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define TIM8_OR1_ETR_ADC2_RMP_1    ((uint32_t)0x00000002U)            /*!<Bit 1 */
-
-#define TIM8_OR1_ETR_ADC3_RMP      ((uint32_t)0x0000000CU)            /*!<ETR_ADC3_RMP[1:0] bits (TIM8 ETR remap on ADC3) */
-#define TIM8_OR1_ETR_ADC3_RMP_0    ((uint32_t)0x00000004U)            /*!<Bit 0 */
-#define TIM8_OR1_ETR_ADC3_RMP_1    ((uint32_t)0x00000008U)            /*!<Bit 1 */
-
-#define TIM8_OR1_TI1_RMP           ((uint32_t)0x00000010U)            /*!<TIM8 Input Capture 1 remap */
-
-/*******************  Bit definition for TIM8_OR2 register  *******************/
-#define TIM8_OR2_BKINE             ((uint32_t)0x00000001U)            /*!<BRK BKIN input enable */
-#define TIM8_OR2_BKCMP1E           ((uint32_t)0x00000002U)            /*!<BRK COMP1 enable */
-#define TIM8_OR2_BKCMP2E           ((uint32_t)0x00000004U)            /*!<BRK COMP2 enable */
-#define TIM8_OR2_BKDFBK2E          ((uint32_t)0x00000100U)            /*!<BRK DFSDM_BREAK[2] enable */
-#define TIM8_OR2_BKINP             ((uint32_t)0x00000200U)            /*!<BRK BKIN input polarity */
-#define TIM8_OR2_BKCMP1P           ((uint32_t)0x00000400U)            /*!<BRK COMP1 input polarity */
-#define TIM8_OR2_BKCMP2P           ((uint32_t)0x00000800U)            /*!<BRK COMP2 input polarity */
-
-#define TIM8_OR2_ETRSEL            ((uint32_t)0x0001C000U)            /*!<ETRSEL[2:0] bits (TIM8 ETR source selection) */
-#define TIM8_OR2_ETRSEL_0          ((uint32_t)0x00004000U)            /*!<Bit 0 */
-#define TIM8_OR2_ETRSEL_1          ((uint32_t)0x00008000U)            /*!<Bit 1 */
-#define TIM8_OR2_ETRSEL_2          ((uint32_t)0x00010000U)            /*!<Bit 2 */
-
-/*******************  Bit definition for TIM8_OR3 register  *******************/
-#define TIM8_OR3_BK2INE            ((uint32_t)0x00000001U)            /*!<BRK2 BKIN2 input enable */
-#define TIM8_OR3_BK2CMP1E          ((uint32_t)0x00000002U)            /*!<BRK2 COMP1 enable */
-#define TIM8_OR3_BK2CMP2E          ((uint32_t)0x00000004U)            /*!<BRK2 COMP2 enable */
-#define TIM8_OR3_BK2DFBK3E         ((uint32_t)0x00000100U)            /*!<BRK2 DFSDM_BREAK[3] enable */
-#define TIM8_OR3_BK2INP            ((uint32_t)0x00000200U)            /*!<BRK2 BKIN2 input polarity */
-#define TIM8_OR3_BK2CMP1P          ((uint32_t)0x00000400U)            /*!<BRK2 COMP1 input polarity */
-#define TIM8_OR3_BK2CMP2P          ((uint32_t)0x00000800U)            /*!<BRK2 COMP2 input polarity */
-
-/*******************  Bit definition for TIM2_OR1 register  *******************/
-#define TIM2_OR1_ITR1_RMP          ((uint32_t)0x00000001U)            /*!<TIM2 Internal trigger 1 remap */
-#define TIM2_OR1_ETR1_RMP          ((uint32_t)0x00000002U)            /*!<TIM2 External trigger 1 remap */
-
-#define TIM2_OR1_TI4_RMP           ((uint32_t)0x0000000CU)            /*!<TI4_RMP[1:0] bits (TIM2 Input Capture 4 remap) */
-#define TIM2_OR1_TI4_RMP_0         ((uint32_t)0x00000004U)            /*!<Bit 0 */
-#define TIM2_OR1_TI4_RMP_1         ((uint32_t)0x00000008U)            /*!<Bit 1 */
-
-/*******************  Bit definition for TIM2_OR2 register  *******************/
-#define TIM2_OR2_ETRSEL            ((uint32_t)0x0001C000U)            /*!<ETRSEL[2:0] bits (TIM2 ETR source selection) */
-#define TIM2_OR2_ETRSEL_0          ((uint32_t)0x00004000U)            /*!<Bit 0 */
-#define TIM2_OR2_ETRSEL_1          ((uint32_t)0x00008000U)            /*!<Bit 1 */
-#define TIM2_OR2_ETRSEL_2          ((uint32_t)0x00010000U)            /*!<Bit 2 */
-
-/*******************  Bit definition for TIM3_OR1 register  *******************/
-#define TIM3_OR1_TI1_RMP           ((uint32_t)0x00000003U)            /*!<TI1_RMP[1:0] bits (TIM3 Input Capture 1 remap) */
-#define TIM3_OR1_TI1_RMP_0         ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define TIM3_OR1_TI1_RMP_1         ((uint32_t)0x00000002U)            /*!<Bit 1 */
-
-/*******************  Bit definition for TIM3_OR2 register  *******************/
-#define TIM3_OR2_ETRSEL            ((uint32_t)0x0001C000U)            /*!<ETRSEL[2:0] bits (TIM3 ETR source selection) */
-#define TIM3_OR2_ETRSEL_0          ((uint32_t)0x00004000U)            /*!<Bit 0 */
-#define TIM3_OR2_ETRSEL_1          ((uint32_t)0x00008000U)            /*!<Bit 1 */
-#define TIM3_OR2_ETRSEL_2          ((uint32_t)0x00010000U)            /*!<Bit 2 */
-
-/*******************  Bit definition for TIM15_OR1 register  ******************/
-#define TIM15_OR1_TI1_RMP          ((uint32_t)0x00000001U)            /*!<TIM15 Input Capture 1 remap */
-
-#define TIM15_OR1_ENCODER_MODE     ((uint32_t)0x00000006U)            /*!<ENCODER_MODE[1:0] bits (TIM15 Encoder mode) */
-#define TIM15_OR1_ENCODER_MODE_0   ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define TIM15_OR1_ENCODER_MODE_1   ((uint32_t)0x00000004U)            /*!<Bit 1 */
-
-/*******************  Bit definition for TIM15_OR2 register  ******************/
-#define TIM15_OR2_BKINE            ((uint32_t)0x00000001U)            /*!<BRK BKIN input enable */
-#define TIM15_OR2_BKCMP1E          ((uint32_t)0x00000002U)            /*!<BRK COMP1 enable */
-#define TIM15_OR2_BKCMP2E          ((uint32_t)0x00000004U)            /*!<BRK COMP2 enable */
-#define TIM15_OR2_BKDFBK0E         ((uint32_t)0x00000100U)            /*!<BRK DFSDM_BREAK[0] enable */
-#define TIM15_OR2_BKINP            ((uint32_t)0x00000200U)            /*!<BRK BKIN input polarity */
-#define TIM15_OR2_BKCMP1P          ((uint32_t)0x00000400U)            /*!<BRK COMP1 input polarity */
-#define TIM15_OR2_BKCMP2P          ((uint32_t)0x00000800U)            /*!<BRK COMP2 input polarity */
-
-/*******************  Bit definition for TIM16_OR1 register  ******************/
-#define TIM16_OR1_TI1_RMP          ((uint32_t)0x00000003U)            /*!<TI1_RMP[1:0] bits (TIM16 Input Capture 1 remap) */
-#define TIM16_OR1_TI1_RMP_0        ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define TIM16_OR1_TI1_RMP_1        ((uint32_t)0x00000002U)            /*!<Bit 1 */
-
-/*******************  Bit definition for TIM16_OR2 register  ******************/
-#define TIM16_OR2_BKINE            ((uint32_t)0x00000001U)            /*!<BRK BKIN input enable */
-#define TIM16_OR2_BKCMP1E          ((uint32_t)0x00000002U)            /*!<BRK COMP1 enable */
-#define TIM16_OR2_BKCMP2E          ((uint32_t)0x00000004U)            /*!<BRK COMP2 enable */
-#define TIM16_OR2_BKDFBK1E         ((uint32_t)0x00000100U)            /*!<BRK DFSDM_BREAK[1] enable */
-#define TIM16_OR2_BKINP            ((uint32_t)0x00000200U)            /*!<BRK BKIN input polarity */
-#define TIM16_OR2_BKCMP1P          ((uint32_t)0x00000400U)            /*!<BRK COMP1 input polarity */
-#define TIM16_OR2_BKCMP2P          ((uint32_t)0x00000800U)            /*!<BRK COMP2 input polarity */
-
-/*******************  Bit definition for TIM17_OR1 register  ******************/
-#define TIM17_OR1_TI1_RMP          ((uint32_t)0x00000003U)            /*!<TI1_RMP[1:0] bits (TIM17 Input Capture 1 remap) */
-#define TIM17_OR1_TI1_RMP_0        ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define TIM17_OR1_TI1_RMP_1        ((uint32_t)0x00000002U)            /*!<Bit 1 */
-
-/*******************  Bit definition for TIM17_OR2 register  ******************/
-#define TIM17_OR2_BKINE            ((uint32_t)0x00000001U)            /*!<BRK BKIN input enable */
-#define TIM17_OR2_BKCMP1E          ((uint32_t)0x00000002U)            /*!<BRK COMP1 enable */
-#define TIM17_OR2_BKCMP2E          ((uint32_t)0x00000004U)            /*!<BRK COMP2 enable */
-#define TIM17_OR2_BKDFBK2E         ((uint32_t)0x00000100U)            /*!<BRK DFSDM_BREAK[2] enable */
-#define TIM17_OR2_BKINP            ((uint32_t)0x00000200U)            /*!<BRK BKIN input polarity */
-#define TIM17_OR2_BKCMP1P          ((uint32_t)0x00000400U)            /*!<BRK COMP1 input polarity */
-#define TIM17_OR2_BKCMP2P          ((uint32_t)0x00000800U)            /*!<BRK COMP2 input polarity */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Low Power Timer (LPTTIM)                           */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for LPTIM_ISR register  *******************/
-#define  LPTIM_ISR_CMPM                         ((uint32_t)0x00000001U)            /*!< Compare match */
-#define  LPTIM_ISR_ARRM                         ((uint32_t)0x00000002U)            /*!< Autoreload match */
-#define  LPTIM_ISR_EXTTRIG                      ((uint32_t)0x00000004U)            /*!< External trigger edge event */
-#define  LPTIM_ISR_CMPOK                        ((uint32_t)0x00000008U)            /*!< Compare register update OK */
-#define  LPTIM_ISR_ARROK                        ((uint32_t)0x00000010U)            /*!< Autoreload register update OK */
-#define  LPTIM_ISR_UP                           ((uint32_t)0x00000020U)            /*!< Counter direction change down to up */
-#define  LPTIM_ISR_DOWN                         ((uint32_t)0x00000040U)            /*!< Counter direction change up to down */
-
-/******************  Bit definition for LPTIM_ICR register  *******************/
-#define  LPTIM_ICR_CMPMCF                       ((uint32_t)0x00000001U)            /*!< Compare match Clear Flag */
-#define  LPTIM_ICR_ARRMCF                       ((uint32_t)0x00000002U)            /*!< Autoreload match Clear Flag */
-#define  LPTIM_ICR_EXTTRIGCF                    ((uint32_t)0x00000004U)            /*!< External trigger edge event Clear Flag */
-#define  LPTIM_ICR_CMPOKCF                      ((uint32_t)0x00000008U)            /*!< Compare register update OK Clear Flag */
-#define  LPTIM_ICR_ARROKCF                      ((uint32_t)0x00000010U)            /*!< Autoreload register update OK Clear Flag */
-#define  LPTIM_ICR_UPCF                         ((uint32_t)0x00000020U)            /*!< Counter direction change down to up Clear Flag */
-#define  LPTIM_ICR_DOWNCF                       ((uint32_t)0x00000040U)            /*!< Counter direction change up to down Clear Flag */
-
-/******************  Bit definition for LPTIM_IER register ********************/
-#define  LPTIM_IER_CMPMIE                       ((uint32_t)0x00000001U)            /*!< Compare match Interrupt Enable */
-#define  LPTIM_IER_ARRMIE                       ((uint32_t)0x00000002U)            /*!< Autoreload match Interrupt Enable */
-#define  LPTIM_IER_EXTTRIGIE                    ((uint32_t)0x00000004U)            /*!< External trigger edge event Interrupt Enable */
-#define  LPTIM_IER_CMPOKIE                      ((uint32_t)0x00000008U)            /*!< Compare register update OK Interrupt Enable */
-#define  LPTIM_IER_ARROKIE                      ((uint32_t)0x00000010U)            /*!< Autoreload register update OK Interrupt Enable */
-#define  LPTIM_IER_UPIE                         ((uint32_t)0x00000020U)            /*!< Counter direction change down to up Interrupt Enable */
-#define  LPTIM_IER_DOWNIE                       ((uint32_t)0x00000040U)            /*!< Counter direction change up to down Interrupt Enable */
-
-/******************  Bit definition for LPTIM_CFGR register *******************/
-#define  LPTIM_CFGR_CKSEL                       ((uint32_t)0x00000001U)             /*!< Clock selector */
-
-#define  LPTIM_CFGR_CKPOL                       ((uint32_t)0x00000006U)             /*!< CKPOL[1:0] bits (Clock polarity) */
-#define  LPTIM_CFGR_CKPOL_0                     ((uint32_t)0x00000002U)             /*!< Bit 0 */
-#define  LPTIM_CFGR_CKPOL_1                     ((uint32_t)0x00000004U)             /*!< Bit 1 */
-
-#define  LPTIM_CFGR_CKFLT                       ((uint32_t)0x00000018U)             /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
-#define  LPTIM_CFGR_CKFLT_0                     ((uint32_t)0x00000008U)             /*!< Bit 0 */
-#define  LPTIM_CFGR_CKFLT_1                     ((uint32_t)0x00000010U)             /*!< Bit 1 */
-
-#define  LPTIM_CFGR_TRGFLT                      ((uint32_t)0x000000C0U)             /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
-#define  LPTIM_CFGR_TRGFLT_0                    ((uint32_t)0x00000040U)             /*!< Bit 0 */
-#define  LPTIM_CFGR_TRGFLT_1                    ((uint32_t)0x00000080U)             /*!< Bit 1 */
-
-#define  LPTIM_CFGR_PRESC                       ((uint32_t)0x00000E00U)             /*!< PRESC[2:0] bits (Clock prescaler) */
-#define  LPTIM_CFGR_PRESC_0                     ((uint32_t)0x00000200U)             /*!< Bit 0 */
-#define  LPTIM_CFGR_PRESC_1                     ((uint32_t)0x00000400U)             /*!< Bit 1 */
-#define  LPTIM_CFGR_PRESC_2                     ((uint32_t)0x00000800U)             /*!< Bit 2 */
-
-#define  LPTIM_CFGR_TRIGSEL                     ((uint32_t)0x0000E000U)             /*!< TRIGSEL[2:0]] bits (Trigger selector) */
-#define  LPTIM_CFGR_TRIGSEL_0                   ((uint32_t)0x00002000U)             /*!< Bit 0 */
-#define  LPTIM_CFGR_TRIGSEL_1                   ((uint32_t)0x00004000U)             /*!< Bit 1 */
-#define  LPTIM_CFGR_TRIGSEL_2                   ((uint32_t)0x00008000U)             /*!< Bit 2 */
-
-#define  LPTIM_CFGR_TRIGEN                      ((uint32_t)0x00060000U)             /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
-#define  LPTIM_CFGR_TRIGEN_0                    ((uint32_t)0x00020000U)             /*!< Bit 0 */
-#define  LPTIM_CFGR_TRIGEN_1                    ((uint32_t)0x00040000U)             /*!< Bit 1 */
-
-#define  LPTIM_CFGR_TIMOUT                      ((uint32_t)0x00080000U)             /*!< Timout enable */
-#define  LPTIM_CFGR_WAVE                        ((uint32_t)0x00100000U)             /*!< Waveform shape */
-#define  LPTIM_CFGR_WAVPOL                      ((uint32_t)0x00200000U)             /*!< Waveform shape polarity */
-#define  LPTIM_CFGR_PRELOAD                     ((uint32_t)0x00400000U)             /*!< Reg update mode */
-#define  LPTIM_CFGR_COUNTMODE                   ((uint32_t)0x00800000U)             /*!< Counter mode enable */
-#define  LPTIM_CFGR_ENC                         ((uint32_t)0x01000000U)             /*!< Encoder mode enable */
-
-/******************  Bit definition for LPTIM_CR register  ********************/
-#define  LPTIM_CR_ENABLE                        ((uint32_t)0x00000001U)             /*!< LPTIMer enable */
-#define  LPTIM_CR_SNGSTRT                       ((uint32_t)0x00000002U)             /*!< Timer start in single mode */
-#define  LPTIM_CR_CNTSTRT                       ((uint32_t)0x00000004U)             /*!< Timer start in continuous mode */
-
-/******************  Bit definition for LPTIM_CMP register  *******************/
-#define  LPTIM_CMP_CMP                          ((uint32_t)0x0000FFFFU)             /*!< Compare register */
-
-/******************  Bit definition for LPTIM_ARR register  *******************/
-#define  LPTIM_ARR_ARR                          ((uint32_t)0x0000FFFFU)             /*!< Auto reload register */
-
-/******************  Bit definition for LPTIM_CNT register  *******************/
-#define  LPTIM_CNT_CNT                          ((uint32_t)0x0000FFFFU)             /*!< Counter register */
-
-/******************  Bit definition for LPTIM_OR register  *******************/
-#define  LPTIM_OR_OR                           ((uint32_t)0x00000003U)               /*!< LPTIMER[1:0] bits (Remap selection) */
-#define  LPTIM_OR_OR_0                         ((uint32_t)0x00000001U)               /*!< Bit 0 */
-#define  LPTIM_OR_OR_1                         ((uint32_t)0x00000002U)               /*!< Bit 1 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-/**********************  Bit definition for COMPx_CSR register  ***************/
-#define COMP_CSR_EN                    ((uint32_t)0x00000001U) /*!< COMPx enable */
-
-#define COMP_CSR_PWRMODE               ((uint32_t)0x0000000CU) /*!< COMPx power mode */
-#define COMP_CSR_PWRMODE_0             ((uint32_t)0x00000004U) /*!< COMPx power mode bit 0 */
-#define COMP_CSR_PWRMODE_1             ((uint32_t)0x00000008U) /*!< COMPx power mode bit 1 */
-
-#define COMP_CSR_INMSEL                ((uint32_t)0x00000070U) /*!< COMPx inverting input (minus) selection */
-#define COMP_CSR_INMSEL_0              ((uint32_t)0x00000010U) /*!< COMPx inverting input (minus) selection bit 0 */
-#define COMP_CSR_INMSEL_1              ((uint32_t)0x00000020U) /*!< COMPx inverting input (minus) selection bit 1 */
-#define COMP_CSR_INMSEL_2              ((uint32_t)0x00000040U) /*!< COMPx inverting input (minus) selection bit 2 */
-
-#define COMP_CSR_INPSEL                ((uint32_t)0x00000080U) /*!< COMPx non inverting input (plus) selection */
-#define COMP_CSR_INPSEL_0              ((uint32_t)0x00000080U) /*!< COMPx non inverting input (plus) selection bit 0*/
-#define COMP_CSR_WINMODE               ((uint32_t)0x00000200U) /*!< COMPx window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-#define COMP_CSR_POLARITY              ((uint32_t)0x00008000U) /*!< COMPx output polarity */
-
-#define COMP_CSR_HYST                  ((uint32_t)0x00030000U) /*!< COMPx hysteresis */
-#define COMP_CSR_HYST_0                ((uint32_t)0x00010000U) /*!< COMPx hysteresis bit 0 */
-#define COMP_CSR_HYST_1                ((uint32_t)0x00020000U) /*!< COMPx hysteresis bit 1 */
-
-#define COMP_CSR_BLANKING              ((uint32_t)0x001C0000U) /*!< COMPx blanking source */
-#define COMP_CSR_BLANKING_0            ((uint32_t)0x00040000U) /*!< COMPx blanking source bit 0 */
-#define COMP_CSR_BLANKING_1            ((uint32_t)0x00080000U) /*!< COMPx blanking source bit 1 */
-#define COMP_CSR_BLANKING_2            ((uint32_t)0x00100000U) /*!< COMPx blanking source bit 2 */
-
-#define COMP_CSR_BRGEN                 ((uint32_t)0x00400000U) /*!< COMPx voltage scaler enable */
-#define COMP_CSR_SCALEN                ((uint32_t)0x00800000U) /*!< COMPx scaler bridge enable */
-#define COMP_CSR_VALUE                 ((uint32_t)0x40000000U) /*!< COMPx value */
-#define COMP_CSR_LOCK                  ((uint32_t)0x80000000U) /*!< COMPx lock */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Operational Amplifier (OPAMP)                      */
-/*                                                                            */
-/******************************************************************************/
-/*********************  Bit definition for OPAMPx_CSR register  ***************/
-#define OPAMP_CSR_OPAMPxEN            ((uint32_t)0x00000001U) /*!< OPAMP enable */
-#define OPAMP_CSR_OPALPM              ((uint32_t)0x00000002U) /*!< Operational amplifier Low Power Mode */
-
-#define OPAMP_CSR_OPAMODE             ((uint32_t)0x0000000CU) /*!< Operational amplifier PGA mode */
-#define OPAMP_CSR_OPAMODE_0           ((uint32_t)0x00000004U) /*!< Bit 0 */
-#define OPAMP_CSR_OPAMODE_1           ((uint32_t)0x00000008U) /*!< Bit 1 */
-
-#define OPAMP_CSR_PGGAIN             ((uint32_t)0x00000030U) /*!< Operational amplifier Programmable amplifier gain value */
-#define OPAMP_CSR_PGGAIN_0           ((uint32_t)0x00000010U) /*!< Bit 0 */
-#define OPAMP_CSR_PGGAIN_1           ((uint32_t)0x00000020U) /*!< Bit 1 */
-
-#define OPAMP_CSR_VMSEL               ((uint32_t)0x00000300U) /*!< Inverting input selection */
-#define OPAMP_CSR_VMSEL_0             ((uint32_t)0x00000100U) /*!< Bit 0 */
-#define OPAMP_CSR_VMSEL_1             ((uint32_t)0x00000200U) /*!< Bit 1 */
-
-#define OPAMP_CSR_VPSEL               ((uint32_t)0x00000400U) /*!< Non inverted input selection */
-#define OPAMP_CSR_CALON               ((uint32_t)0x00001000U) /*!< Calibration mode enable */
-#define OPAMP_CSR_CALSEL              ((uint32_t)0x00002000U) /*!< Calibration selection */
-#define OPAMP_CSR_USERTRIM            ((uint32_t)0x00004000U) /*!< User trimming enable */
-#define OPAMP_CSR_CALOUT              ((uint32_t)0x00008000U) /*!< Operational amplifier1 calibration output */
-
-/*********************  Bit definition for OPAMP1_CSR register  ***************/
-#define OPAMP1_CSR_OPAEN               ((uint32_t)0x00000001U) /*!< Operational amplifier1 Enable */
-#define OPAMP1_CSR_OPALPM              ((uint32_t)0x00000002U) /*!< Operational amplifier1 Low Power Mode */
-
-#define OPAMP1_CSR_OPAMODE             ((uint32_t)0x0000000CU) /*!< Operational amplifier1 PGA mode */
-#define OPAMP1_CSR_OPAMODE_0           ((uint32_t)0x00000004U) /*!< Bit 0 */
-#define OPAMP1_CSR_OPAMODE_1           ((uint32_t)0x00000008U) /*!< Bit 1 */
-
-#define OPAMP1_CSR_PGAGAIN             ((uint32_t)0x00000030U) /*!< Operational amplifier1 Programmable amplifier gain value */
-#define OPAMP1_CSR_PGAGAIN_0           ((uint32_t)0x00000010U) /*!< Bit 0 */
-#define OPAMP1_CSR_PGAGAIN_1           ((uint32_t)0x00000020U) /*!< Bit 1 */
-
-#define OPAMP1_CSR_VMSEL               ((uint32_t)0x00000300U) /*!< Inverting input selection */
-#define OPAMP1_CSR_VMSEL_0             ((uint32_t)0x00000100U) /*!< Bit 0 */
-#define OPAMP1_CSR_VMSEL_1             ((uint32_t)0x00000200U) /*!< Bit 1 */
-
-#define OPAMP1_CSR_VPSEL               ((uint32_t)0x00000400U) /*!< Non inverted input selection */
-#define OPAMP1_CSR_CALON               ((uint32_t)0x00001000U) /*!< Calibration mode enable */
-#define OPAMP1_CSR_CALSEL              ((uint32_t)0x00002000U) /*!< Calibration selection */
-#define OPAMP1_CSR_USERTRIM            ((uint32_t)0x00004000U) /*!< User trimming enable */
-#define OPAMP1_CSR_CALOUT              ((uint32_t)0x00008000U) /*!< Operational amplifier1 calibration output */
-#define OPAMP1_CSR_OPARANGE            ((uint32_t)0x80000000U) /*!< Operational amplifiers power supply range for stability */
-
-/*********************  Bit definition for OPAMP2_CSR register  ***************/
-#define OPAMP2_CSR_OPAEN               ((uint32_t)0x00000001U) /*!< Operational amplifier2 Enable */
-#define OPAMP2_CSR_OPALPM              ((uint32_t)0x00000002U) /*!< Operational amplifier2 Low Power Mode */
-
-#define OPAMP2_CSR_OPAMODE             ((uint32_t)0x0000000CU) /*!< Operational amplifier2 PGA mode */
-#define OPAMP2_CSR_OPAMODE_0           ((uint32_t)0x00000004U) /*!< Bit 0 */
-#define OPAMP2_CSR_OPAMODE_1           ((uint32_t)0x00000008U) /*!< Bit 1 */
-
-#define OPAMP2_CSR_PGAGAIN             ((uint32_t)0x00000030U) /*!< Operational amplifier2 Programmable amplifier gain value */
-#define OPAMP2_CSR_PGAGAIN_0           ((uint32_t)0x00000010U) /*!< Bit 0 */
-#define OPAMP2_CSR_PGAGAIN_1           ((uint32_t)0x00000020U) /*!< Bit 1 */
-
-#define OPAMP2_CSR_VMSEL               ((uint32_t)0x00000300U) /*!< Inverting input selection */
-#define OPAMP2_CSR_VMSEL_0             ((uint32_t)0x00000100U) /*!< Bit 0 */
-#define OPAMP2_CSR_VMSEL_1             ((uint32_t)0x00000200U) /*!< Bit 1 */
-
-#define OPAMP2_CSR_VPSEL               ((uint32_t)0x00000400U) /*!< Non inverted input selection */
-#define OPAMP2_CSR_CALON               ((uint32_t)0x00001000U) /*!< Calibration mode enable */
-#define OPAMP2_CSR_CALSEL              ((uint32_t)0x00002000U) /*!< Calibration selection */
-#define OPAMP2_CSR_USERTRIM            ((uint32_t)0x00004000U) /*!< User trimming enable */
-#define OPAMP2_CSR_CALOUT              ((uint32_t)0x00008000U) /*!< Operational amplifier2 calibration output */
-
-/*******************  Bit definition for OPAMP_OTR register  ******************/
-#define OPAMP_OTR_TRIMOFFSETN            ((uint32_t)0x0000001FU)        /*!< Trim for NMOS differential pairs */
-#define OPAMP_OTR_TRIMOFFSETP            ((uint32_t)0x00001F00U)        /*!< Trim for PMOS differential pairs */
-
-/*******************  Bit definition for OPAMP1_OTR register  ******************/
-#define OPAMP1_OTR_TRIMOFFSETN            ((uint32_t)0x0000001FU)        /*!< Trim for NMOS differential pairs */
-#define OPAMP1_OTR_TRIMOFFSETP            ((uint32_t)0x00001F00U)        /*!< Trim for PMOS differential pairs */
-
-/*******************  Bit definition for OPAMP2_OTR register  ******************/
-#define OPAMP2_OTR_TRIMOFFSETN            ((uint32_t)0x0000001FU)        /*!< Trim for NMOS differential pairs */
-#define OPAMP2_OTR_TRIMOFFSETP            ((uint32_t)0x00001F00U)        /*!< Trim for PMOS differential pairs */
-
-/*******************  Bit definition for OPAMP_LPOTR register  ****************/
-#define OPAMP_LPOTR_TRIMLPOFFSETN        ((uint32_t)0x0000001FU)        /*!< Trim for NMOS differential pairs */
-#define OPAMP_LPOTR_TRIMLPOFFSETP        ((uint32_t)0x00001F00U)        /*!< Trim for PMOS differential pairs */
-
-/*******************  Bit definition for OPAMP1_LPOTR register  ****************/
-#define OPAMP1_LPOTR_TRIMLPOFFSETN        ((uint32_t)0x0000001FU)        /*!< Trim for NMOS differential pairs */
-#define OPAMP1_LPOTR_TRIMLPOFFSETP        ((uint32_t)0x00001F00U)        /*!< Trim for PMOS differential pairs */
-
-/*******************  Bit definition for OPAMP2_LPOTR register  ****************/
-#define OPAMP2_LPOTR_TRIMLPOFFSETN        ((uint32_t)0x0000001FU)        /*!< Trim for NMOS differential pairs */
-#define OPAMP2_LPOTR_TRIMLPOFFSETP        ((uint32_t)0x00001F00U)        /*!< Trim for PMOS differential pairs */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Touch Sensing Controller (TSC)                    */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TSC_CR register  *********************/
-#define TSC_CR_TSCE                         ((uint32_t)0x00000001U)            /*!<Touch sensing controller enable */
-#define TSC_CR_START                        ((uint32_t)0x00000002U)            /*!<Start acquisition */
-#define TSC_CR_AM                           ((uint32_t)0x00000004U)            /*!<Acquisition mode */
-#define TSC_CR_SYNCPOL                      ((uint32_t)0x00000008U)            /*!<Synchronization pin polarity */
-#define TSC_CR_IODEF                        ((uint32_t)0x00000010U)            /*!<IO default mode */
-
-#define TSC_CR_MCV                          ((uint32_t)0x000000E0U)            /*!<MCV[2:0] bits (Max Count Value) */
-#define TSC_CR_MCV_0                        ((uint32_t)0x00000020U)            /*!<Bit 0 */
-#define TSC_CR_MCV_1                        ((uint32_t)0x00000040U)            /*!<Bit 1 */
-#define TSC_CR_MCV_2                        ((uint32_t)0x00000080U)            /*!<Bit 2 */
-
-#define TSC_CR_PGPSC                        ((uint32_t)0x00007000U)            /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
-#define TSC_CR_PGPSC_0                      ((uint32_t)0x00001000U)            /*!<Bit 0 */
-#define TSC_CR_PGPSC_1                      ((uint32_t)0x00002000U)            /*!<Bit 1 */
-#define TSC_CR_PGPSC_2                      ((uint32_t)0x00004000U)            /*!<Bit 2 */
-
-#define TSC_CR_SSPSC                        ((uint32_t)0x00008000U)            /*!<Spread Spectrum Prescaler */
-#define TSC_CR_SSE                          ((uint32_t)0x00010000U)            /*!<Spread Spectrum Enable */
-
-#define TSC_CR_SSD                          ((uint32_t)0x00FE0000U)            /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
-#define TSC_CR_SSD_0                        ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define TSC_CR_SSD_1                        ((uint32_t)0x00040000U)            /*!<Bit 1 */
-#define TSC_CR_SSD_2                        ((uint32_t)0x00080000U)            /*!<Bit 2 */
-#define TSC_CR_SSD_3                        ((uint32_t)0x00100000U)            /*!<Bit 3 */
-#define TSC_CR_SSD_4                        ((uint32_t)0x00200000U)            /*!<Bit 4 */
-#define TSC_CR_SSD_5                        ((uint32_t)0x00400000U)            /*!<Bit 5 */
-#define TSC_CR_SSD_6                        ((uint32_t)0x00800000U)            /*!<Bit 6 */
-
-#define TSC_CR_CTPL                         ((uint32_t)0x0F000000U)            /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
-#define TSC_CR_CTPL_0                       ((uint32_t)0x01000000U)            /*!<Bit 0 */
-#define TSC_CR_CTPL_1                       ((uint32_t)0x02000000U)            /*!<Bit 1 */
-#define TSC_CR_CTPL_2                       ((uint32_t)0x04000000U)            /*!<Bit 2 */
-#define TSC_CR_CTPL_3                       ((uint32_t)0x08000000U)            /*!<Bit 3 */
-
-#define TSC_CR_CTPH                         ((uint32_t)0xF0000000U)            /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
-#define TSC_CR_CTPH_0                       ((uint32_t)0x10000000U)            /*!<Bit 0 */
-#define TSC_CR_CTPH_1                       ((uint32_t)0x20000000U)            /*!<Bit 1 */
-#define TSC_CR_CTPH_2                       ((uint32_t)0x40000000U)            /*!<Bit 2 */
-#define TSC_CR_CTPH_3                       ((uint32_t)0x80000000U)            /*!<Bit 3 */
-
-/*******************  Bit definition for TSC_IER register  ********************/
-#define TSC_IER_EOAIE                       ((uint32_t)0x00000001U)            /*!<End of acquisition interrupt enable */
-#define TSC_IER_MCEIE                       ((uint32_t)0x00000002U)            /*!<Max count error interrupt enable */
-
-/*******************  Bit definition for TSC_ICR register  ********************/
-#define TSC_ICR_EOAIC                       ((uint32_t)0x00000001U)            /*!<End of acquisition interrupt clear */
-#define TSC_ICR_MCEIC                       ((uint32_t)0x00000002U)            /*!<Max count error interrupt clear */
-
-/*******************  Bit definition for TSC_ISR register  ********************/
-#define TSC_ISR_EOAF                        ((uint32_t)0x00000001U)            /*!<End of acquisition flag */
-#define TSC_ISR_MCEF                        ((uint32_t)0x00000002U)            /*!<Max count error flag */
-
-/*******************  Bit definition for TSC_IOHCR register  ******************/
-#define TSC_IOHCR_G1_IO1                    ((uint32_t)0x00000001U)            /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO2                    ((uint32_t)0x00000002U)            /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO3                    ((uint32_t)0x00000004U)            /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO4                    ((uint32_t)0x00000008U)            /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO1                    ((uint32_t)0x00000010U)            /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO2                    ((uint32_t)0x00000020U)            /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO3                    ((uint32_t)0x00000040U)            /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO4                    ((uint32_t)0x00000080U)            /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO1                    ((uint32_t)0x00000100U)            /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO2                    ((uint32_t)0x00000200U)            /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO3                    ((uint32_t)0x00000400U)            /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO4                    ((uint32_t)0x00000800U)            /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO1                    ((uint32_t)0x00001000U)            /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO2                    ((uint32_t)0x00002000U)            /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO3                    ((uint32_t)0x00004000U)            /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO4                    ((uint32_t)0x00008000U)            /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO1                    ((uint32_t)0x00010000U)            /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO2                    ((uint32_t)0x00020000U)            /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO3                    ((uint32_t)0x00040000U)            /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO4                    ((uint32_t)0x00080000U)            /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO1                    ((uint32_t)0x00100000U)            /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO2                    ((uint32_t)0x00200000U)            /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO3                    ((uint32_t)0x00400000U)            /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO4                    ((uint32_t)0x00800000U)            /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO1                    ((uint32_t)0x01000000U)            /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO2                    ((uint32_t)0x02000000U)            /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO3                    ((uint32_t)0x04000000U)            /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO4                    ((uint32_t)0x08000000U)            /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO1                    ((uint32_t)0x10000000U)            /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO2                    ((uint32_t)0x20000000U)            /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO3                    ((uint32_t)0x40000000U)            /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO4                    ((uint32_t)0x80000000U)            /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
-
-/*******************  Bit definition for TSC_IOASCR register  *****************/
-#define TSC_IOASCR_G1_IO1                   ((uint32_t)0x00000001U)            /*!<GROUP1_IO1 analog switch enable */
-#define TSC_IOASCR_G1_IO2                   ((uint32_t)0x00000002U)            /*!<GROUP1_IO2 analog switch enable */
-#define TSC_IOASCR_G1_IO3                   ((uint32_t)0x00000004U)            /*!<GROUP1_IO3 analog switch enable */
-#define TSC_IOASCR_G1_IO4                   ((uint32_t)0x00000008U)            /*!<GROUP1_IO4 analog switch enable */
-#define TSC_IOASCR_G2_IO1                   ((uint32_t)0x00000010U)            /*!<GROUP2_IO1 analog switch enable */
-#define TSC_IOASCR_G2_IO2                   ((uint32_t)0x00000020U)            /*!<GROUP2_IO2 analog switch enable */
-#define TSC_IOASCR_G2_IO3                   ((uint32_t)0x00000040U)            /*!<GROUP2_IO3 analog switch enable */
-#define TSC_IOASCR_G2_IO4                   ((uint32_t)0x00000080U)            /*!<GROUP2_IO4 analog switch enable */
-#define TSC_IOASCR_G3_IO1                   ((uint32_t)0x00000100U)            /*!<GROUP3_IO1 analog switch enable */
-#define TSC_IOASCR_G3_IO2                   ((uint32_t)0x00000200U)            /*!<GROUP3_IO2 analog switch enable */
-#define TSC_IOASCR_G3_IO3                   ((uint32_t)0x00000400U)            /*!<GROUP3_IO3 analog switch enable */
-#define TSC_IOASCR_G3_IO4                   ((uint32_t)0x00000800U)            /*!<GROUP3_IO4 analog switch enable */
-#define TSC_IOASCR_G4_IO1                   ((uint32_t)0x00001000U)            /*!<GROUP4_IO1 analog switch enable */
-#define TSC_IOASCR_G4_IO2                   ((uint32_t)0x00002000U)            /*!<GROUP4_IO2 analog switch enable */
-#define TSC_IOASCR_G4_IO3                   ((uint32_t)0x00004000U)            /*!<GROUP4_IO3 analog switch enable */
-#define TSC_IOASCR_G4_IO4                   ((uint32_t)0x00008000U)            /*!<GROUP4_IO4 analog switch enable */
-#define TSC_IOASCR_G5_IO1                   ((uint32_t)0x00010000U)            /*!<GROUP5_IO1 analog switch enable */
-#define TSC_IOASCR_G5_IO2                   ((uint32_t)0x00020000U)            /*!<GROUP5_IO2 analog switch enable */
-#define TSC_IOASCR_G5_IO3                   ((uint32_t)0x00040000U)            /*!<GROUP5_IO3 analog switch enable */
-#define TSC_IOASCR_G5_IO4                   ((uint32_t)0x00080000U)            /*!<GROUP5_IO4 analog switch enable */
-#define TSC_IOASCR_G6_IO1                   ((uint32_t)0x00100000U)            /*!<GROUP6_IO1 analog switch enable */
-#define TSC_IOASCR_G6_IO2                   ((uint32_t)0x00200000U)            /*!<GROUP6_IO2 analog switch enable */
-#define TSC_IOASCR_G6_IO3                   ((uint32_t)0x00400000U)            /*!<GROUP6_IO3 analog switch enable */
-#define TSC_IOASCR_G6_IO4                   ((uint32_t)0x00800000U)            /*!<GROUP6_IO4 analog switch enable */
-#define TSC_IOASCR_G7_IO1                   ((uint32_t)0x01000000U)            /*!<GROUP7_IO1 analog switch enable */
-#define TSC_IOASCR_G7_IO2                   ((uint32_t)0x02000000U)            /*!<GROUP7_IO2 analog switch enable */
-#define TSC_IOASCR_G7_IO3                   ((uint32_t)0x04000000U)            /*!<GROUP7_IO3 analog switch enable */
-#define TSC_IOASCR_G7_IO4                   ((uint32_t)0x08000000U)            /*!<GROUP7_IO4 analog switch enable */
-#define TSC_IOASCR_G8_IO1                   ((uint32_t)0x10000000U)            /*!<GROUP8_IO1 analog switch enable */
-#define TSC_IOASCR_G8_IO2                   ((uint32_t)0x20000000U)            /*!<GROUP8_IO2 analog switch enable */
-#define TSC_IOASCR_G8_IO3                   ((uint32_t)0x40000000U)            /*!<GROUP8_IO3 analog switch enable */
-#define TSC_IOASCR_G8_IO4                   ((uint32_t)0x80000000U)            /*!<GROUP8_IO4 analog switch enable */
-
-/*******************  Bit definition for TSC_IOSCR register  ******************/
-#define TSC_IOSCR_G1_IO1                    ((uint32_t)0x00000001U)            /*!<GROUP1_IO1 sampling mode */
-#define TSC_IOSCR_G1_IO2                    ((uint32_t)0x00000002U)            /*!<GROUP1_IO2 sampling mode */
-#define TSC_IOSCR_G1_IO3                    ((uint32_t)0x00000004U)            /*!<GROUP1_IO3 sampling mode */
-#define TSC_IOSCR_G1_IO4                    ((uint32_t)0x00000008U)            /*!<GROUP1_IO4 sampling mode */
-#define TSC_IOSCR_G2_IO1                    ((uint32_t)0x00000010U)            /*!<GROUP2_IO1 sampling mode */
-#define TSC_IOSCR_G2_IO2                    ((uint32_t)0x00000020U)            /*!<GROUP2_IO2 sampling mode */
-#define TSC_IOSCR_G2_IO3                    ((uint32_t)0x00000040U)            /*!<GROUP2_IO3 sampling mode */
-#define TSC_IOSCR_G2_IO4                    ((uint32_t)0x00000080U)            /*!<GROUP2_IO4 sampling mode */
-#define TSC_IOSCR_G3_IO1                    ((uint32_t)0x00000100U)            /*!<GROUP3_IO1 sampling mode */
-#define TSC_IOSCR_G3_IO2                    ((uint32_t)0x00000200U)            /*!<GROUP3_IO2 sampling mode */
-#define TSC_IOSCR_G3_IO3                    ((uint32_t)0x00000400U)            /*!<GROUP3_IO3 sampling mode */
-#define TSC_IOSCR_G3_IO4                    ((uint32_t)0x00000800U)            /*!<GROUP3_IO4 sampling mode */
-#define TSC_IOSCR_G4_IO1                    ((uint32_t)0x00001000U)            /*!<GROUP4_IO1 sampling mode */
-#define TSC_IOSCR_G4_IO2                    ((uint32_t)0x00002000U)            /*!<GROUP4_IO2 sampling mode */
-#define TSC_IOSCR_G4_IO3                    ((uint32_t)0x00004000U)            /*!<GROUP4_IO3 sampling mode */
-#define TSC_IOSCR_G4_IO4                    ((uint32_t)0x00008000U)            /*!<GROUP4_IO4 sampling mode */
-#define TSC_IOSCR_G5_IO1                    ((uint32_t)0x00010000U)            /*!<GROUP5_IO1 sampling mode */
-#define TSC_IOSCR_G5_IO2                    ((uint32_t)0x00020000U)            /*!<GROUP5_IO2 sampling mode */
-#define TSC_IOSCR_G5_IO3                    ((uint32_t)0x00040000U)            /*!<GROUP5_IO3 sampling mode */
-#define TSC_IOSCR_G5_IO4                    ((uint32_t)0x00080000U)            /*!<GROUP5_IO4 sampling mode */
-#define TSC_IOSCR_G6_IO1                    ((uint32_t)0x00100000U)            /*!<GROUP6_IO1 sampling mode */
-#define TSC_IOSCR_G6_IO2                    ((uint32_t)0x00200000U)            /*!<GROUP6_IO2 sampling mode */
-#define TSC_IOSCR_G6_IO3                    ((uint32_t)0x00400000U)            /*!<GROUP6_IO3 sampling mode */
-#define TSC_IOSCR_G6_IO4                    ((uint32_t)0x00800000U)            /*!<GROUP6_IO4 sampling mode */
-#define TSC_IOSCR_G7_IO1                    ((uint32_t)0x01000000U)            /*!<GROUP7_IO1 sampling mode */
-#define TSC_IOSCR_G7_IO2                    ((uint32_t)0x02000000U)            /*!<GROUP7_IO2 sampling mode */
-#define TSC_IOSCR_G7_IO3                    ((uint32_t)0x04000000U)            /*!<GROUP7_IO3 sampling mode */
-#define TSC_IOSCR_G7_IO4                    ((uint32_t)0x08000000U)            /*!<GROUP7_IO4 sampling mode */
-#define TSC_IOSCR_G8_IO1                    ((uint32_t)0x10000000U)            /*!<GROUP8_IO1 sampling mode */
-#define TSC_IOSCR_G8_IO2                    ((uint32_t)0x20000000U)            /*!<GROUP8_IO2 sampling mode */
-#define TSC_IOSCR_G8_IO3                    ((uint32_t)0x40000000U)            /*!<GROUP8_IO3 sampling mode */
-#define TSC_IOSCR_G8_IO4                    ((uint32_t)0x80000000U)            /*!<GROUP8_IO4 sampling mode */
-
-/*******************  Bit definition for TSC_IOCCR register  ******************/
-#define TSC_IOCCR_G1_IO1                    ((uint32_t)0x00000001U)            /*!<GROUP1_IO1 channel mode */
-#define TSC_IOCCR_G1_IO2                    ((uint32_t)0x00000002U)            /*!<GROUP1_IO2 channel mode */
-#define TSC_IOCCR_G1_IO3                    ((uint32_t)0x00000004U)            /*!<GROUP1_IO3 channel mode */
-#define TSC_IOCCR_G1_IO4                    ((uint32_t)0x00000008U)            /*!<GROUP1_IO4 channel mode */
-#define TSC_IOCCR_G2_IO1                    ((uint32_t)0x00000010U)            /*!<GROUP2_IO1 channel mode */
-#define TSC_IOCCR_G2_IO2                    ((uint32_t)0x00000020U)            /*!<GROUP2_IO2 channel mode */
-#define TSC_IOCCR_G2_IO3                    ((uint32_t)0x00000040U)            /*!<GROUP2_IO3 channel mode */
-#define TSC_IOCCR_G2_IO4                    ((uint32_t)0x00000080U)            /*!<GROUP2_IO4 channel mode */
-#define TSC_IOCCR_G3_IO1                    ((uint32_t)0x00000100U)            /*!<GROUP3_IO1 channel mode */
-#define TSC_IOCCR_G3_IO2                    ((uint32_t)0x00000200U)            /*!<GROUP3_IO2 channel mode */
-#define TSC_IOCCR_G3_IO3                    ((uint32_t)0x00000400U)            /*!<GROUP3_IO3 channel mode */
-#define TSC_IOCCR_G3_IO4                    ((uint32_t)0x00000800U)            /*!<GROUP3_IO4 channel mode */
-#define TSC_IOCCR_G4_IO1                    ((uint32_t)0x00001000U)            /*!<GROUP4_IO1 channel mode */
-#define TSC_IOCCR_G4_IO2                    ((uint32_t)0x00002000U)            /*!<GROUP4_IO2 channel mode */
-#define TSC_IOCCR_G4_IO3                    ((uint32_t)0x00004000U)            /*!<GROUP4_IO3 channel mode */
-#define TSC_IOCCR_G4_IO4                    ((uint32_t)0x00008000U)            /*!<GROUP4_IO4 channel mode */
-#define TSC_IOCCR_G5_IO1                    ((uint32_t)0x00010000U)            /*!<GROUP5_IO1 channel mode */
-#define TSC_IOCCR_G5_IO2                    ((uint32_t)0x00020000U)            /*!<GROUP5_IO2 channel mode */
-#define TSC_IOCCR_G5_IO3                    ((uint32_t)0x00040000U)            /*!<GROUP5_IO3 channel mode */
-#define TSC_IOCCR_G5_IO4                    ((uint32_t)0x00080000U)            /*!<GROUP5_IO4 channel mode */
-#define TSC_IOCCR_G6_IO1                    ((uint32_t)0x00100000U)            /*!<GROUP6_IO1 channel mode */
-#define TSC_IOCCR_G6_IO2                    ((uint32_t)0x00200000U)            /*!<GROUP6_IO2 channel mode */
-#define TSC_IOCCR_G6_IO3                    ((uint32_t)0x00400000U)            /*!<GROUP6_IO3 channel mode */
-#define TSC_IOCCR_G6_IO4                    ((uint32_t)0x00800000U)            /*!<GROUP6_IO4 channel mode */
-#define TSC_IOCCR_G7_IO1                    ((uint32_t)0x01000000U)            /*!<GROUP7_IO1 channel mode */
-#define TSC_IOCCR_G7_IO2                    ((uint32_t)0x02000000U)            /*!<GROUP7_IO2 channel mode */
-#define TSC_IOCCR_G7_IO3                    ((uint32_t)0x04000000U)            /*!<GROUP7_IO3 channel mode */
-#define TSC_IOCCR_G7_IO4                    ((uint32_t)0x08000000U)            /*!<GROUP7_IO4 channel mode */
-#define TSC_IOCCR_G8_IO1                    ((uint32_t)0x10000000U)            /*!<GROUP8_IO1 channel mode */
-#define TSC_IOCCR_G8_IO2                    ((uint32_t)0x20000000U)            /*!<GROUP8_IO2 channel mode */
-#define TSC_IOCCR_G8_IO3                    ((uint32_t)0x40000000U)            /*!<GROUP8_IO3 channel mode */
-#define TSC_IOCCR_G8_IO4                    ((uint32_t)0x80000000U)            /*!<GROUP8_IO4 channel mode */
-
-/*******************  Bit definition for TSC_IOGCSR register  *****************/
-#define TSC_IOGCSR_G1E                      ((uint32_t)0x00000001U)            /*!<Analog IO GROUP1 enable */
-#define TSC_IOGCSR_G2E                      ((uint32_t)0x00000002U)            /*!<Analog IO GROUP2 enable */
-#define TSC_IOGCSR_G3E                      ((uint32_t)0x00000004U)            /*!<Analog IO GROUP3 enable */
-#define TSC_IOGCSR_G4E                      ((uint32_t)0x00000008U)            /*!<Analog IO GROUP4 enable */
-#define TSC_IOGCSR_G5E                      ((uint32_t)0x00000010U)            /*!<Analog IO GROUP5 enable */
-#define TSC_IOGCSR_G6E                      ((uint32_t)0x00000020U)            /*!<Analog IO GROUP6 enable */
-#define TSC_IOGCSR_G7E                      ((uint32_t)0x00000040U)            /*!<Analog IO GROUP7 enable */
-#define TSC_IOGCSR_G8E                      ((uint32_t)0x00000080U)            /*!<Analog IO GROUP8 enable */
-#define TSC_IOGCSR_G1S                      ((uint32_t)0x00010000U)            /*!<Analog IO GROUP1 status */
-#define TSC_IOGCSR_G2S                      ((uint32_t)0x00020000U)            /*!<Analog IO GROUP2 status */
-#define TSC_IOGCSR_G3S                      ((uint32_t)0x00040000U)            /*!<Analog IO GROUP3 status */
-#define TSC_IOGCSR_G4S                      ((uint32_t)0x00080000U)            /*!<Analog IO GROUP4 status */
-#define TSC_IOGCSR_G5S                      ((uint32_t)0x00100000U)            /*!<Analog IO GROUP5 status */
-#define TSC_IOGCSR_G6S                      ((uint32_t)0x00200000U)            /*!<Analog IO GROUP6 status */
-#define TSC_IOGCSR_G7S                      ((uint32_t)0x00400000U)            /*!<Analog IO GROUP7 status */
-#define TSC_IOGCSR_G8S                      ((uint32_t)0x00800000U)            /*!<Analog IO GROUP8 status */
-
-/*******************  Bit definition for TSC_IOGXCR register  *****************/
-#define TSC_IOGXCR_CNT                      ((uint32_t)0x00003FFFU)            /*!<CNT[13:0] bits (Counter value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_UE                        ((uint32_t)0x00000001U)            /*!< USART Enable */
-#define  USART_CR1_UESM                      ((uint32_t)0x00000002U)            /*!< USART Enable in STOP Mode */
-#define  USART_CR1_RE                        ((uint32_t)0x00000004U)            /*!< Receiver Enable */
-#define  USART_CR1_TE                        ((uint32_t)0x00000008U)            /*!< Transmitter Enable */
-#define  USART_CR1_IDLEIE                    ((uint32_t)0x00000010U)            /*!< IDLE Interrupt Enable */
-#define  USART_CR1_RXNEIE                    ((uint32_t)0x00000020U)            /*!< RXNE Interrupt Enable */
-#define  USART_CR1_TCIE                      ((uint32_t)0x00000040U)            /*!< Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     ((uint32_t)0x00000080U)            /*!< TXE Interrupt Enable */
-#define  USART_CR1_PEIE                      ((uint32_t)0x00000100U)            /*!< PE Interrupt Enable */
-#define  USART_CR1_PS                        ((uint32_t)0x00000200U)            /*!< Parity Selection */
-#define  USART_CR1_PCE                       ((uint32_t)0x00000400U)            /*!< Parity Control Enable */
-#define  USART_CR1_WAKE                      ((uint32_t)0x00000800U)            /*!< Receiver Wakeup method */
-#define  USART_CR1_M                         ((uint32_t)0x10001000U)            /*!< Word length */
-#define  USART_CR1_M0                        ((uint32_t)0x00001000U)            /*!< Word length - Bit 0 */
-#define  USART_CR1_MME                       ((uint32_t)0x00002000U)            /*!< Mute Mode Enable */
-#define  USART_CR1_CMIE                      ((uint32_t)0x00004000U)            /*!< Character match interrupt enable */
-#define  USART_CR1_OVER8                     ((uint32_t)0x00008000U)            /*!< Oversampling by 8-bit or 16-bit mode */
-#define  USART_CR1_DEDT                      ((uint32_t)0x001F0000U)            /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
-#define  USART_CR1_DEDT_0                    ((uint32_t)0x00010000U)            /*!< Bit 0 */
-#define  USART_CR1_DEDT_1                    ((uint32_t)0x00020000U)            /*!< Bit 1 */
-#define  USART_CR1_DEDT_2                    ((uint32_t)0x00040000U)            /*!< Bit 2 */
-#define  USART_CR1_DEDT_3                    ((uint32_t)0x00080000U)            /*!< Bit 3 */
-#define  USART_CR1_DEDT_4                    ((uint32_t)0x00100000U)            /*!< Bit 4 */
-#define  USART_CR1_DEAT                      ((uint32_t)0x03E00000U)            /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
-#define  USART_CR1_DEAT_0                    ((uint32_t)0x00200000U)            /*!< Bit 0 */
-#define  USART_CR1_DEAT_1                    ((uint32_t)0x00400000U)            /*!< Bit 1 */
-#define  USART_CR1_DEAT_2                    ((uint32_t)0x00800000U)            /*!< Bit 2 */
-#define  USART_CR1_DEAT_3                    ((uint32_t)0x01000000U)            /*!< Bit 3 */
-#define  USART_CR1_DEAT_4                    ((uint32_t)0x02000000U)            /*!< Bit 4 */
-#define  USART_CR1_RTOIE                     ((uint32_t)0x04000000U)            /*!< Receive Time Out interrupt enable */
-#define  USART_CR1_EOBIE                     ((uint32_t)0x08000000U)            /*!< End of Block interrupt enable */
-#define  USART_CR1_M1                        ((uint32_t)0x10000000U)            /*!< Word length - Bit 1 */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADDM7                     ((uint32_t)0x00000010U)            /*!< 7-bit or 4-bit Address Detection */
-#define  USART_CR2_LBDL                      ((uint32_t)0x00000020U)            /*!< LIN Break Detection Length */
-#define  USART_CR2_LBDIE                     ((uint32_t)0x00000040U)            /*!< LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      ((uint32_t)0x00000100U)            /*!< Last Bit Clock pulse */
-#define  USART_CR2_CPHA                      ((uint32_t)0x00000200U)            /*!< Clock Phase */
-#define  USART_CR2_CPOL                      ((uint32_t)0x00000400U)            /*!< Clock Polarity */
-#define  USART_CR2_CLKEN                     ((uint32_t)0x00000800U)            /*!< Clock Enable */
-#define  USART_CR2_STOP                      ((uint32_t)0x00003000U)            /*!< STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    ((uint32_t)0x00001000U)            /*!< Bit 0 */
-#define  USART_CR2_STOP_1                    ((uint32_t)0x00002000U)            /*!< Bit 1 */
-#define  USART_CR2_LINEN                     ((uint32_t)0x00004000U)            /*!< LIN mode enable */
-#define  USART_CR2_SWAP                      ((uint32_t)0x00008000U)            /*!< SWAP TX/RX pins */
-#define  USART_CR2_RXINV                     ((uint32_t)0x00010000U)            /*!< RX pin active level inversion */
-#define  USART_CR2_TXINV                     ((uint32_t)0x00020000U)            /*!< TX pin active level inversion */
-#define  USART_CR2_DATAINV                   ((uint32_t)0x00040000U)            /*!< Binary data inversion */
-#define  USART_CR2_MSBFIRST                  ((uint32_t)0x00080000U)            /*!< Most Significant Bit First */
-#define  USART_CR2_ABREN                     ((uint32_t)0x00100000U)            /*!< Auto Baud-Rate Enable*/
-#define  USART_CR2_ABRMODE                   ((uint32_t)0x00600000U)            /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
-#define  USART_CR2_ABRMODE_0                 ((uint32_t)0x00200000U)            /*!< Bit 0 */
-#define  USART_CR2_ABRMODE_1                 ((uint32_t)0x00400000U)            /*!< Bit 1 */
-#define  USART_CR2_RTOEN                     ((uint32_t)0x00800000U)            /*!< Receiver Time-Out enable */
-#define  USART_CR2_ADD                       ((uint32_t)0xFF000000U)            /*!< Address of the USART node */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       ((uint32_t)0x00000001U)            /*!< Error Interrupt Enable */
-#define  USART_CR3_IREN                      ((uint32_t)0x00000002U)            /*!< IrDA mode Enable */
-#define  USART_CR3_IRLP                      ((uint32_t)0x00000004U)            /*!< IrDA Low-Power */
-#define  USART_CR3_HDSEL                     ((uint32_t)0x00000008U)            /*!< Half-Duplex Selection */
-#define  USART_CR3_NACK                      ((uint32_t)0x00000010U)            /*!< SmartCard NACK enable */
-#define  USART_CR3_SCEN                      ((uint32_t)0x00000020U)            /*!< SmartCard mode enable */
-#define  USART_CR3_DMAR                      ((uint32_t)0x00000040U)            /*!< DMA Enable Receiver */
-#define  USART_CR3_DMAT                      ((uint32_t)0x00000080U)            /*!< DMA Enable Transmitter */
-#define  USART_CR3_RTSE                      ((uint32_t)0x00000100U)            /*!< RTS Enable */
-#define  USART_CR3_CTSE                      ((uint32_t)0x00000200U)            /*!< CTS Enable */
-#define  USART_CR3_CTSIE                     ((uint32_t)0x00000400U)            /*!< CTS Interrupt Enable */
-#define  USART_CR3_ONEBIT                    ((uint32_t)0x00000800U)            /*!< One sample bit method enable */
-#define  USART_CR3_OVRDIS                    ((uint32_t)0x00001000U)            /*!< Overrun Disable */
-#define  USART_CR3_DDRE                      ((uint32_t)0x00002000U)            /*!< DMA Disable on Reception Error */
-#define  USART_CR3_DEM                       ((uint32_t)0x00004000U)            /*!< Driver Enable Mode */
-#define  USART_CR3_DEP                       ((uint32_t)0x00008000U)            /*!< Driver Enable Polarity Selection */
-#define  USART_CR3_SCARCNT                   ((uint32_t)0x000E0000U)            /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
-#define  USART_CR3_SCARCNT_0                 ((uint32_t)0x00020000U)            /*!< Bit 0 */
-#define  USART_CR3_SCARCNT_1                 ((uint32_t)0x00040000U)            /*!< Bit 1 */
-#define  USART_CR3_SCARCNT_2                 ((uint32_t)0x00080000U)            /*!< Bit 2 */
-#define  USART_CR3_WUS                       ((uint32_t)0x00300000U)            /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
-#define  USART_CR3_WUS_0                     ((uint32_t)0x00100000U)            /*!< Bit 0 */
-#define  USART_CR3_WUS_1                     ((uint32_t)0x00200000U)            /*!< Bit 1 */
-#define  USART_CR3_WUFIE                     ((uint32_t)0x00400000U)            /*!< Wake Up Interrupt Enable */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_FRACTION              ((uint16_t)0x000FU)                /*!< Fraction of USARTDIV */
-#define  USART_BRR_DIV_MANTISSA              ((uint16_t)0xFFF0U)                /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      ((uint32_t)0x000000FFU)            /*!< PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_GT                       ((uint32_t)0x0000FF00U)            /*!< GT[7:0] bits (Guard time value) */
-
-
-/*******************  Bit definition for USART_RTOR register  *****************/
-#define  USART_RTOR_RTO                      ((uint32_t)0x00FFFFFFU)            /*!< Receiver Time Out Value */
-#define  USART_RTOR_BLEN                     ((uint32_t)0xFF000000U)            /*!< Block Length */
-
-/*******************  Bit definition for USART_RQR register  ******************/
-#define  USART_RQR_ABRRQ                     ((uint16_t)0x0001U)                /*!< Auto-Baud Rate Request */
-#define  USART_RQR_SBKRQ                     ((uint16_t)0x0002U)                /*!< Send Break Request */
-#define  USART_RQR_MMRQ                      ((uint16_t)0x0004U)                /*!< Mute Mode Request */
-#define  USART_RQR_RXFRQ                     ((uint16_t)0x0008U)                /*!< Receive Data flush Request */
-#define  USART_RQR_TXFRQ                     ((uint16_t)0x0010U)                /*!< Transmit data flush Request */
-
-/*******************  Bit definition for USART_ISR register  ******************/
-#define  USART_ISR_PE                        ((uint32_t)0x00000001U)            /*!< Parity Error */
-#define  USART_ISR_FE                        ((uint32_t)0x00000002U)            /*!< Framing Error */
-#define  USART_ISR_NE                        ((uint32_t)0x00000004U)            /*!< Noise detected Flag */
-#define  USART_ISR_ORE                       ((uint32_t)0x00000008U)            /*!< OverRun Error */
-#define  USART_ISR_IDLE                      ((uint32_t)0x00000010U)            /*!< IDLE line detected */
-#define  USART_ISR_RXNE                      ((uint32_t)0x00000020U)            /*!< Read Data Register Not Empty */
-#define  USART_ISR_TC                        ((uint32_t)0x00000040U)            /*!< Transmission Complete */
-#define  USART_ISR_TXE                       ((uint32_t)0x00000080U)            /*!< Transmit Data Register Empty */
-#define  USART_ISR_LBDF                      ((uint32_t)0x00000100U)            /*!< LIN Break Detection Flag */
-#define  USART_ISR_CTSIF                     ((uint32_t)0x00000200U)            /*!< CTS interrupt flag */
-#define  USART_ISR_CTS                       ((uint32_t)0x00000400U)            /*!< CTS flag */
-#define  USART_ISR_RTOF                      ((uint32_t)0x00000800U)            /*!< Receiver Time Out */
-#define  USART_ISR_EOBF                      ((uint32_t)0x00001000U)            /*!< End Of Block Flag */
-#define  USART_ISR_ABRE                      ((uint32_t)0x00004000U)            /*!< Auto-Baud Rate Error */
-#define  USART_ISR_ABRF                      ((uint32_t)0x00008000U)            /*!< Auto-Baud Rate Flag */
-#define  USART_ISR_BUSY                      ((uint32_t)0x00010000U)            /*!< Busy Flag */
-#define  USART_ISR_CMF                       ((uint32_t)0x00020000U)            /*!< Character Match Flag */
-#define  USART_ISR_SBKF                      ((uint32_t)0x00040000U)            /*!< Send Break Flag */
-#define  USART_ISR_RWU                       ((uint32_t)0x00080000U)            /*!< Receive Wake Up from mute mode Flag */
-#define  USART_ISR_WUF                       ((uint32_t)0x00100000U)            /*!< Wake Up from stop mode Flag */
-#define  USART_ISR_TEACK                     ((uint32_t)0x00200000U)            /*!< Transmit Enable Acknowledge Flag */
-#define  USART_ISR_REACK                     ((uint32_t)0x00400000U)            /*!< Receive Enable Acknowledge Flag */
-
-/*******************  Bit definition for USART_ICR register  ******************/
-#define  USART_ICR_PECF                      ((uint32_t)0x00000001U)            /*!< Parity Error Clear Flag */
-#define  USART_ICR_FECF                      ((uint32_t)0x00000002U)            /*!< Framing Error Clear Flag */
-#define  USART_ICR_NCF                       ((uint32_t)0x00000004U)            /*!< Noise detected Clear Flag */
-#define  USART_ICR_ORECF                     ((uint32_t)0x00000008U)            /*!< OverRun Error Clear Flag */
-#define  USART_ICR_IDLECF                    ((uint32_t)0x00000010U)            /*!< IDLE line detected Clear Flag */
-#define  USART_ICR_TCCF                      ((uint32_t)0x00000040U)            /*!< Transmission Complete Clear Flag */
-#define  USART_ICR_LBDCF                     ((uint32_t)0x00000100U)            /*!< LIN Break Detection Clear Flag */
-#define  USART_ICR_CTSCF                     ((uint32_t)0x00000200U)            /*!< CTS Interrupt Clear Flag */
-#define  USART_ICR_RTOCF                     ((uint32_t)0x00000800U)            /*!< Receiver Time Out Clear Flag */
-#define  USART_ICR_EOBCF                     ((uint32_t)0x00001000U)            /*!< End Of Block Clear Flag */
-#define  USART_ICR_CMCF                      ((uint32_t)0x00020000U)            /*!< Character Match Clear Flag */
-#define  USART_ICR_WUCF                      ((uint32_t)0x00100000U)            /*!< Wake Up from stop mode Clear Flag */
-
-/*******************  Bit definition for USART_RDR register  ******************/
-#define  USART_RDR_RDR                       ((uint16_t)0x01FFU)                /*!< RDR[8:0] bits (Receive Data value) */
-
-/*******************  Bit definition for USART_TDR register  ******************/
-#define  USART_TDR_TDR                       ((uint16_t)0x01FFU)                /*!< TDR[8:0] bits (Transmit Data value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*           Single Wire Protocol Master Interface (SWPMI)                    */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for SWPMI_CR register   ********************/
-#define  SWPMI_CR_RXDMA                      ((uint32_t)0x00000001U)        /*!<Reception DMA enable                                 */
-#define  SWPMI_CR_TXDMA                      ((uint32_t)0x00000002U)        /*!<Transmission DMA enable                              */
-#define  SWPMI_CR_RXMODE                     ((uint32_t)0x00000004U)        /*!<Reception buffering mode                             */
-#define  SWPMI_CR_TXMODE                     ((uint32_t)0x00000008U)        /*!<Transmission buffering mode                          */
-#define  SWPMI_CR_LPBK                       ((uint32_t)0x00000010U)        /*!<Loopback mode enable                                 */
-#define  SWPMI_CR_SWPACT                     ((uint32_t)0x00000020U)        /*!<Single wire protocol master interface activate       */
-#define  SWPMI_CR_DEACT                      ((uint32_t)0x00000400U)        /*!<Single wire protocol master interface deactivate     */
-
-/*******************  Bit definition for SWPMI_BRR register  ********************/
-#define  SWPMI_BRR_BR                        ((uint32_t)0x0000003FU)        /*!<BR[5:0] bits (Bitrate prescaler) */
-
-/*******************  Bit definition for SWPMI_ISR register  ********************/
-#define  SWPMI_ISR_RXBFF                     ((uint32_t)0x00000001U)        /*!<Receive buffer full flag        */
-#define  SWPMI_ISR_TXBEF                     ((uint32_t)0x00000002U)        /*!<Transmit buffer empty flag      */
-#define  SWPMI_ISR_RXBERF                    ((uint32_t)0x00000004U)        /*!<Receive CRC error flag          */
-#define  SWPMI_ISR_RXOVRF                    ((uint32_t)0x00000008U)        /*!<Receive overrun error flag      */
-#define  SWPMI_ISR_TXUNRF                    ((uint32_t)0x00000010U)        /*!<Transmit underrun error flag    */
-#define  SWPMI_ISR_RXNE                      ((uint32_t)0x00000020U)        /*!<Receive data register not empty */
-#define  SWPMI_ISR_TXE                       ((uint32_t)0x00000040U)        /*!<Transmit data register empty    */
-#define  SWPMI_ISR_TCF                       ((uint32_t)0x00000080U)        /*!<Transfer complete flag          */
-#define  SWPMI_ISR_SRF                       ((uint32_t)0x00000100U)        /*!<Slave resume flag               */
-#define  SWPMI_ISR_SUSP                      ((uint32_t)0x00000200U)        /*!<SUSPEND flag                    */
-#define  SWPMI_ISR_DEACTF                    ((uint32_t)0x00000400U)        /*!<DEACTIVATED flag                */
-
-/*******************  Bit definition for SWPMI_ICR register  ********************/
-#define  SWPMI_ICR_CRXBFF                    ((uint32_t)0x00000001U)        /*!<Clear receive buffer full flag       */
-#define  SWPMI_ICR_CTXBEF                    ((uint32_t)0x00000002U)        /*!<Clear transmit buffer empty flag     */
-#define  SWPMI_ICR_CRXBERF                   ((uint32_t)0x00000004U)        /*!<Clear receive CRC error flag         */
-#define  SWPMI_ICR_CRXOVRF                   ((uint32_t)0x00000008U)        /*!<Clear receive overrun error flag     */
-#define  SWPMI_ICR_CTXUNRF                   ((uint32_t)0x00000010U)        /*!<Clear transmit underrun error flag   */
-#define  SWPMI_ICR_CTCF                      ((uint32_t)0x00000080U)        /*!<Clear transfer complete flag         */
-#define  SWPMI_ICR_CSRF                      ((uint32_t)0x00000100U)        /*!<Clear slave resume flag              */
-
-/*******************  Bit definition for SWPMI_IER register  ********************/
-#define  SWPMI_IER_SRIE                      ((uint32_t)0x00000100U)        /*!<Slave resume interrupt enable               */
-#define  SWPMI_IER_TCIE                      ((uint32_t)0x00000080U)        /*!<Transmit complete interrupt enable          */
-#define  SWPMI_IER_TIE                       ((uint32_t)0x00000040U)        /*!<Transmit interrupt enable                   */
-#define  SWPMI_IER_RIE                       ((uint32_t)0x00000020U)        /*!<Receive interrupt enable                    */
-#define  SWPMI_IER_TXUNRIE                   ((uint32_t)0x00000010U)        /*!<Transmit underrun error interrupt enable    */
-#define  SWPMI_IER_RXOVRIE                   ((uint32_t)0x00000008U)        /*!<Receive overrun error interrupt enable      */
-#define  SWPMI_IER_RXBERIE                   ((uint32_t)0x00000004U)        /*!<Receive CRC error interrupt enable          */
-#define  SWPMI_IER_TXBEIE                    ((uint32_t)0x00000002U)        /*!<Transmit buffer empty interrupt enable      */
-#define  SWPMI_IER_RXBFIE                    ((uint32_t)0x00000001U)        /*!<Receive buffer full interrupt enable        */
-
-/*******************  Bit definition for SWPMI_RFL register  ********************/
-#define  SWPMI_RFL_RFL                       ((uint32_t)0x0000001FU)        /*!<RFL[4:0] bits (Receive Frame length) */
-#define  SWPMI_RFL_RFL_0_1                   ((uint32_t)0x00000003U)        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
-
-/*******************  Bit definition for SWPMI_TDR register  ********************/
-#define  SWPMI_TDR_TD                        ((uint32_t)0xFFFFFFFFU)        /*!<Transmit Data Register         */
-
-/*******************  Bit definition for SWPMI_RDR register  ********************/
-#define  SWPMI_RDR_RD                        ((uint32_t)0xFFFFFFFFU)        /*!<Receive Data Register          */
-
-/*******************  Bit definition for SWPMI_OR register  ********************/
-#define  SWPMI_OR_TBYP                       ((uint32_t)0x00000001U)        /*!<SWP Transceiver Bypass */
-#define  SWPMI_OR_CLASS                      ((uint32_t)0x00000002U)        /*!<SWP Voltage Class selection */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 VREFBUF                                    */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for VREFBUF_CSR register  ****************/
-#define  VREFBUF_CSR_ENVR                    ((uint32_t)0x00000001U)        /*!<Voltage reference buffer enable */
-#define  VREFBUF_CSR_HIZ                     ((uint32_t)0x00000002U)        /*!<High impedance mode             */
-#define  VREFBUF_CSR_VRS                     ((uint32_t)0x00000004U)        /*!<Voltage reference scale         */
-#define  VREFBUF_CSR_VRR                     ((uint32_t)0x00000008U)        /*!<Voltage reference buffer ready  */
-
-/*******************  Bit definition for VREFBUF_CCR register  ******************/
-#define  VREFBUF_CCR_TRIM                    ((uint32_t)0x0000003FU)        /*!<TRIM[5:0] bits (Trimming code)  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Window WATCHDOG                                 */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           ((uint32_t)0x0000007FU)        /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T_0                         ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  WWDG_CR_T_1                         ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  WWDG_CR_T_2                         ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  WWDG_CR_T_3                         ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  WWDG_CR_T_4                         ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  WWDG_CR_T_5                         ((uint32_t)0x00000020U)        /*!<Bit 5 */
-#define  WWDG_CR_T_6                         ((uint32_t)0x00000040U)        /*!<Bit 6 */
-
-#define  WWDG_CR_WDGA                        ((uint32_t)0x00000080U)        /*!<Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          ((uint32_t)0x0000007FU)        /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W_0                        ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  WWDG_CFR_W_1                        ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  WWDG_CFR_W_2                        ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  WWDG_CFR_W_3                        ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  WWDG_CFR_W_4                        ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  WWDG_CFR_W_5                        ((uint32_t)0x00000020U)        /*!<Bit 5 */
-#define  WWDG_CFR_W_6                        ((uint32_t)0x00000040U)        /*!<Bit 6 */
-
-#define  WWDG_CFR_WDGTB                      ((uint32_t)0x00000180U)        /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB_0                    ((uint32_t)0x00000080U)        /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB_1                    ((uint32_t)0x00000100U)        /*!<Bit 1 */
-
-#define  WWDG_CFR_EWI                        ((uint32_t)0x00000200U)        /*!<Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        ((uint32_t)0x00000001U)        /*!<Early Wakeup Interrupt Flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 Debug MCU                                  */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFFU)
-#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000U)
-
-/********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001U)
-#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002U)
-#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004U)
-#define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020U)
-
-#define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0U)
-#define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040U)/*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080U)/*!<Bit 1 */
-
-/********************  Bit definition for DBGMCU_APB1FZR1 register  ***********/
-#define  DBGMCU_APB1FZR1_DBG_TIM2_STOP       ((uint32_t)0x00000001U)
-#define  DBGMCU_APB1FZR1_DBG_TIM3_STOP       ((uint32_t)0x00000002U)
-#define  DBGMCU_APB1FZR1_DBG_TIM4_STOP       ((uint32_t)0x00000004U)
-#define  DBGMCU_APB1FZR1_DBG_TIM5_STOP       ((uint32_t)0x00000008U)
-#define  DBGMCU_APB1FZR1_DBG_TIM6_STOP       ((uint32_t)0x00000010U)
-#define  DBGMCU_APB1FZR1_DBG_TIM7_STOP       ((uint32_t)0x00000020U)
-#define  DBGMCU_APB1FZR1_DBG_RTC_STOP        ((uint32_t)0x00000400U)
-#define  DBGMCU_APB1FZR1_DBG_WWDG_STOP       ((uint32_t)0x00000800U)
-#define  DBGMCU_APB1FZR1_DBG_IWDG_STOP       ((uint32_t)0x00001000U)
-#define  DBGMCU_APB1FZR1_DBG_I2C1_STOP       ((uint32_t)0x00200000U)
-#define  DBGMCU_APB1FZR1_DBG_I2C2_STOP       ((uint32_t)0x00400000U)
-#define  DBGMCU_APB1FZR1_DBG_I2C3_STOP       ((uint32_t)0x00800000U)
-#define  DBGMCU_APB1FZR1_DBG_CAN_STOP        ((uint32_t)0x02000000U)
-#define  DBGMCU_APB1FZR1_DBG_LPTIM1_STOP     ((uint32_t)0x80000000U)
-
-/********************  Bit definition for DBGMCU_APB1FZR2 register  **********/
-#define  DBGMCU_APB1FZR2_DBG_LPTIM2_STOP     ((uint32_t)0x00000020U)
-
-/********************  Bit definition for DBGMCU_APB2FZ register  ************/
-#define  DBGMCU_APB2FZ_DBG_TIM1_STOP         ((uint32_t)0x00000800U)
-#define  DBGMCU_APB2FZ_DBG_TIM8_STOP         ((uint32_t)0x00002000U)
-#define  DBGMCU_APB2FZ_DBG_TIM15_STOP        ((uint32_t)0x00010000U)
-#define  DBGMCU_APB2FZ_DBG_TIM16_STOP        ((uint32_t)0x00020000U)
-#define  DBGMCU_APB2FZ_DBG_TIM17_STOP        ((uint32_t)0x00040000U)
-
-/******************************************************************************/
-/*                                                                            */
-/*                                       USB_OTG                              */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for USB_OTG_GOTGCTL register  ********************/
-#define USB_OTG_GOTGCTL_SRQSCS                  ((uint32_t)0x00000001U)         /*!< Session request success */
-#define USB_OTG_GOTGCTL_SRQ                     ((uint32_t)0x00000002U)         /*!< Session request */
-#define USB_OTG_GOTGCTL_VBVALOEN                ((uint32_t)0x00000004U)         /*!< VBUS valid override enable */
-#define USB_OTG_GOTGCTL_VBVALOVAL               ((uint32_t)0x00000008U)         /*!< VBUS valid override value */
-#define USB_OTG_GOTGCTL_AVALOEN                 ((uint32_t)0x00000010U)         /*!< A-peripheral session valid override enable */
-#define USB_OTG_GOTGCTL_AVALOVAL                ((uint32_t)0x00000020U)         /*!< A-peripheral session valid override value */
-#define USB_OTG_GOTGCTL_BVALOEN                 ((uint32_t)0x00000040U)         /*!< B-peripheral session valid override enable */
-#define USB_OTG_GOTGCTL_BVALOVAL                ((uint32_t)0x00000080U)         /*!< B-peripheral session valid override value  */
-#define USB_OTG_GOTGCTL_BSESVLD                 ((uint32_t)0x00080000U)         /*!<  B-session valid*/
-
-/********************  Bit definition for USB_OTG_HCFG register  ********************/
-
-#define USB_OTG_HCFG_FSLSPCS                 ((uint32_t)0x00000003U)            /*!< FS/LS PHY clock select */
-#define USB_OTG_HCFG_FSLSPCS_0               ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_HCFG_FSLSPCS_1               ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_HCFG_FSLSS                   ((uint32_t)0x00000004U)            /*!< FS- and LS-only support */
-
-/********************  Bit definition for USB_OTG_DCFG register  ********************/
-
-#define USB_OTG_DCFG_DSPD                    ((uint32_t)0x00000003U)            /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                  ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_DSPD_1                  ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_DCFG_NZLSOHSK                ((uint32_t)0x00000004U)            /*!< Nonzero-length status OUT handshake */
-#define USB_OTG_DCFG_DAD                     ((uint32_t)0x000007F0U)            /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                   ((uint32_t)0x00000010U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_DAD_1                   ((uint32_t)0x00000020U)            /*!<Bit 1 */
-#define USB_OTG_DCFG_DAD_2                   ((uint32_t)0x00000040U)            /*!<Bit 2 */
-#define USB_OTG_DCFG_DAD_3                   ((uint32_t)0x00000080U)            /*!<Bit 3 */
-#define USB_OTG_DCFG_DAD_4                   ((uint32_t)0x00000100U)            /*!<Bit 4 */
-#define USB_OTG_DCFG_DAD_5                   ((uint32_t)0x00000200U)            /*!<Bit 5 */
-#define USB_OTG_DCFG_DAD_6                   ((uint32_t)0x00000400U)            /*!<Bit 6 */
-#define USB_OTG_DCFG_PFIVL                   ((uint32_t)0x00001800U)            /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                 ((uint32_t)0x00000800U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_PFIVL_1                 ((uint32_t)0x00001000U)            /*!<Bit 1 */
-#define USB_OTG_DCFG_PERSCHIVL               ((uint32_t)0x03000000U)            /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0             ((uint32_t)0x01000000U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_PERSCHIVL_1             ((uint32_t)0x02000000U)            /*!<Bit 1 */
-
-/********************  Bit definition for USB_OTG_PCGCR register  ********************/
-#define USB_OTG_PCGCR_STPPCLK                 ((uint32_t)0x00000001U)           /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK                ((uint32_t)0x00000002U)           /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP                 ((uint32_t)0x00000010U)           /*!< PHY suspended */
-
-/********************  Bit definition for USB_OTG_GOTGINT register  ********************/
-#define USB_OTG_GOTGINT_SEDET                   ((uint32_t)0x00000004U)         /*!< Session end detected */
-#define USB_OTG_GOTGINT_SRSSCHG                 ((uint32_t)0x00000100U)         /*!< Session request success status change */
-#define USB_OTG_GOTGINT_HNSSCHG                 ((uint32_t)0x00000200U)         /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET                  ((uint32_t)0x00020000U)         /*!< Host negotiation detected */
-#define USB_OTG_GOTGINT_ADTOCHG                 ((uint32_t)0x00040000U)         /*!< A-device timeout change */
-#define USB_OTG_GOTGINT_DBCDNE                  ((uint32_t)0x00080000U)         /*!< Debounce done */
-
-/********************  Bit definition for USB_OTG_DCTL register  ********************/
-#define USB_OTG_DCTL_RWUSIG                  ((uint32_t)0x00000001U)            /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS                    ((uint32_t)0x00000002U)            /*!< Soft disconnect */
-#define USB_OTG_DCTL_GINSTS                  ((uint32_t)0x00000004U)            /*!< Global IN NAK status */
-#define USB_OTG_DCTL_GONSTS                  ((uint32_t)0x00000008U)            /*!< Global OUT NAK status */
-
-#define USB_OTG_DCTL_TCTL                    ((uint32_t)0x00000070U)            /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                  ((uint32_t)0x00000010U)            /*!<Bit 0 */
-#define USB_OTG_DCTL_TCTL_1                  ((uint32_t)0x00000020U)            /*!<Bit 1 */
-#define USB_OTG_DCTL_TCTL_2                  ((uint32_t)0x00000040U)            /*!<Bit 2 */
-#define USB_OTG_DCTL_SGINAK                  ((uint32_t)0x00000080U)            /*!< Set global IN NAK */
-#define USB_OTG_DCTL_CGINAK                  ((uint32_t)0x00000100U)            /*!< Clear global IN NAK */
-#define USB_OTG_DCTL_SGONAK                  ((uint32_t)0x00000200U)            /*!< Set global OUT NAK */
-#define USB_OTG_DCTL_CGONAK                  ((uint32_t)0x00000400U)            /*!< Clear global OUT NAK */
-#define USB_OTG_DCTL_POPRGDNE                ((uint32_t)0x00000800U)            /*!< Power-on programming done */
-
-/********************  Bit definition for USB_OTG_HFIR register  ********************/
-#define USB_OTG_HFIR_FRIVL                   ((uint32_t)0x0000FFFFU)            /*!< Frame interval */
-
-/********************  Bit definition for USB_OTG_HFNUM register  ********************/
-#define USB_OTG_HFNUM_FRNUM                   ((uint32_t)0x0000FFFFU)           /*!< Frame number */
-#define USB_OTG_HFNUM_FTREM                   ((uint32_t)0xFFFF0000U)           /*!< Frame time remaining */
-
-/********************  Bit definition for USB_OTG_DSTS register  ********************/
-#define USB_OTG_DSTS_SUSPSTS                 ((uint32_t)0x00000001U)            /*!< Suspend status */
-
-#define USB_OTG_DSTS_ENUMSPD                 ((uint32_t)0x00000006U)            /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0               ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define USB_OTG_DSTS_ENUMSPD_1               ((uint32_t)0x00000004U)            /*!<Bit 1 */
-#define USB_OTG_DSTS_EERR                    ((uint32_t)0x00000008U)            /*!< Erratic error */
-#define USB_OTG_DSTS_FNSOF                   ((uint32_t)0x003FFF00U)            /*!< Frame number of the received SOF */
-
-/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
-#define USB_OTG_GAHBCFG_GINT                    ((uint32_t)0x00000001U)         /*!< Global interrupt mask */
-#define USB_OTG_GAHBCFG_HBSTLEN                 ((uint32_t)0x0000001EU)         /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0               ((uint32_t)0x00000002U)         /*!<Bit 0 */
-#define USB_OTG_GAHBCFG_HBSTLEN_1               ((uint32_t)0x00000004U)         /*!<Bit 1 */
-#define USB_OTG_GAHBCFG_HBSTLEN_2               ((uint32_t)0x00000008U)         /*!<Bit 2 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3               ((uint32_t)0x00000010U)         /*!<Bit 3 */
-#define USB_OTG_GAHBCFG_DMAEN                   ((uint32_t)0x00000020U)         /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL                 ((uint32_t)0x00000080U)         /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL                ((uint32_t)0x00000100U)         /*!< Periodic TxFIFO empty level */
-
-/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
-
-#define USB_OTG_GUSBCFG_TOCAL                   ((uint32_t)0x00000007U)         /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                 ((uint32_t)0x00000001U)         /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TOCAL_1                 ((uint32_t)0x00000002U)         /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TOCAL_2                 ((uint32_t)0x00000004U)         /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_PHYSEL                  ((uint32_t)0x00000040U)         /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP                  ((uint32_t)0x00000100U)         /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP                  ((uint32_t)0x00000200U)         /*!< HNP-capable */
-#define USB_OTG_GUSBCFG_TRDT                    ((uint32_t)0x00003C00U)         /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                  ((uint32_t)0x00000400U)         /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TRDT_1                  ((uint32_t)0x00000800U)         /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TRDT_2                  ((uint32_t)0x00001000U)         /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_TRDT_3                  ((uint32_t)0x00002000U)         /*!<Bit 3 */
-#define USB_OTG_GUSBCFG_PHYLPCS                 ((uint32_t)0x00008000U)         /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS                ((uint32_t)0x00020000U)         /*!< ULPI FS/LS select */
-#define USB_OTG_GUSBCFG_ULPIAR                  ((uint32_t)0x00040000U)         /*!< ULPI Auto-resume */
-#define USB_OTG_GUSBCFG_ULPICSM                 ((uint32_t)0x00080000U)         /*!< ULPI Clock SuspendM */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD              ((uint32_t)0x00100000U)         /*!< ULPI External VBUS Drive */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI              ((uint32_t)0x00200000U)         /*!< ULPI external VBUS indicator */
-#define USB_OTG_GUSBCFG_TSDPS                   ((uint32_t)0x00400000U)         /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI                    ((uint32_t)0x00800000U)         /*!< Indicator complement */
-#define USB_OTG_GUSBCFG_PTCI                    ((uint32_t)0x01000000U)         /*!< Indicator pass through */
-#define USB_OTG_GUSBCFG_ULPIIPD                 ((uint32_t)0x02000000U)         /*!< ULPI interface protect disable */
-#define USB_OTG_GUSBCFG_FHMOD                   ((uint32_t)0x20000000U)         /*!< Forced host mode */
-#define USB_OTG_GUSBCFG_FDMOD                   ((uint32_t)0x40000000U)         /*!< Forced peripheral mode */
-#define USB_OTG_GUSBCFG_CTXPKT                  ((uint32_t)0x80000000U)         /*!< Corrupt Tx packet */
-
-/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
-#define USB_OTG_GRSTCTL_CSRST                   ((uint32_t)0x00000001U)         /*!< Core soft reset */
-#define USB_OTG_GRSTCTL_HSRST                   ((uint32_t)0x00000002U)         /*!< HCLK soft reset */
-#define USB_OTG_GRSTCTL_FCRST                   ((uint32_t)0x00000004U)         /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH                 ((uint32_t)0x00000010U)         /*!< RxFIFO flush */
-#define USB_OTG_GRSTCTL_TXFFLSH                 ((uint32_t)0x00000020U)         /*!< TxFIFO flush */
-#define USB_OTG_GRSTCTL_TXFNUM                  ((uint32_t)0x000007C0U)         /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                ((uint32_t)0x00000040U)         /*!<Bit 0 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                ((uint32_t)0x00000080U)         /*!<Bit 1 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                ((uint32_t)0x00000100U)         /*!<Bit 2 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                ((uint32_t)0x00000200U)         /*!<Bit 3 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                ((uint32_t)0x00000400U)         /*!<Bit 4 */
-#define USB_OTG_GRSTCTL_DMAREQ                  ((uint32_t)0x40000000U)         /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL                  ((uint32_t)0x80000000U)         /*!< AHB master idle */
-
-/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
-#define USB_OTG_DIEPMSK_XFRCM                   ((uint32_t)0x00000001U)         /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPMSK_EPDM                    ((uint32_t)0x00000002U)         /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPMSK_TOM                     ((uint32_t)0x00000008U)         /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK               ((uint32_t)0x00000010U)         /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPMSK_INEPNMM                 ((uint32_t)0x00000020U)         /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPMSK_INEPNEM                 ((uint32_t)0x00000040U)         /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPMSK_TXFURM                  ((uint32_t)0x00000100U)         /*!< FIFO underrun mask */
-#define USB_OTG_DIEPMSK_BIM                     ((uint32_t)0x00000200U)         /*!< BNA interrupt mask */
-
-/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
-#define USB_OTG_HPTXSTS_PTXFSAVL                ((uint32_t)0x0000FFFFU)         /*!< Periodic transmit data FIFO space available */
-#define USB_OTG_HPTXSTS_PTXQSAV                 ((uint32_t)0x00FF0000U)         /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0               ((uint32_t)0x00010000U)         /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1               ((uint32_t)0x00020000U)         /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2               ((uint32_t)0x00040000U)         /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3               ((uint32_t)0x00080000U)         /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4               ((uint32_t)0x00100000U)         /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5               ((uint32_t)0x00200000U)         /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6               ((uint32_t)0x00400000U)         /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7               ((uint32_t)0x00800000U)         /*!<Bit 7 */
-
-#define USB_OTG_HPTXSTS_PTXQTOP                 ((uint32_t)0xFF000000U)         /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0               ((uint32_t)0x01000000U)         /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1               ((uint32_t)0x02000000U)         /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2               ((uint32_t)0x04000000U)         /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3               ((uint32_t)0x08000000U)         /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4               ((uint32_t)0x10000000U)         /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5               ((uint32_t)0x20000000U)         /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6               ((uint32_t)0x40000000U)         /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7               ((uint32_t)0x80000000U)         /*!<Bit 7 */
-
-/********************  Bit definition for USB_OTG_HAINT register  ********************/
-#define USB_OTG_HAINT_HAINT                   ((uint32_t)0x0000FFFFU)           /*!< Channel interrupts */
-
-/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
-#define USB_OTG_DOEPMSK_XFRCM                   ((uint32_t)0x00000001U)         /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM                    ((uint32_t)0x00000002U)         /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPMSK_STUPM                   ((uint32_t)0x00000008U)         /*!< SETUP phase done mask */
-#define USB_OTG_DOEPMSK_OTEPDM                  ((uint32_t)0x00000010U)         /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_B2BSTUP                 ((uint32_t)0x00000040U)         /*!< Back-to-back SETUP packets received mask */
-#define USB_OTG_DOEPMSK_OPEM                    ((uint32_t)0x00000100U)         /*!< OUT packet error mask */
-#define USB_OTG_DOEPMSK_BOIM                    ((uint32_t)0x00000200U)         /*!< BNA interrupt mask */
-
-/********************  Bit definition for USB_OTG_GINTSTS register  ********************/
-#define USB_OTG_GINTSTS_CMOD                    ((uint32_t)0x00000001U)         /*!< Current mode of operation */
-#define USB_OTG_GINTSTS_MMIS                    ((uint32_t)0x00000002U)         /*!< Mode mismatch interrupt */
-#define USB_OTG_GINTSTS_OTGINT                  ((uint32_t)0x00000004U)         /*!< OTG interrupt */
-#define USB_OTG_GINTSTS_SOF                     ((uint32_t)0x00000008U)         /*!< Start of frame */
-#define USB_OTG_GINTSTS_RXFLVL                  ((uint32_t)0x00000010U)         /*!< RxFIFO nonempty */
-#define USB_OTG_GINTSTS_NPTXFE                  ((uint32_t)0x00000020U)         /*!< Nonperiodic TxFIFO empty */
-#define USB_OTG_GINTSTS_GINAKEFF                ((uint32_t)0x00000040U)         /*!< Global IN nonperiodic NAK effective */
-#define USB_OTG_GINTSTS_BOUTNAKEFF              ((uint32_t)0x00000080U)         /*!< Global OUT NAK effective */
-#define USB_OTG_GINTSTS_ESUSP                   ((uint32_t)0x00000400U)         /*!< Early suspend */
-#define USB_OTG_GINTSTS_USBSUSP                 ((uint32_t)0x00000800U)         /*!< USB suspend */
-#define USB_OTG_GINTSTS_USBRST                  ((uint32_t)0x00001000U)         /*!< USB reset */
-#define USB_OTG_GINTSTS_ENUMDNE                 ((uint32_t)0x00002000U)         /*!< Enumeration done */
-#define USB_OTG_GINTSTS_ISOODRP                 ((uint32_t)0x00004000U)         /*!< Isochronous OUT packet dropped interrupt */
-#define USB_OTG_GINTSTS_EOPF                    ((uint32_t)0x00008000U)         /*!< End of periodic frame interrupt */
-#define USB_OTG_GINTSTS_IEPINT                  ((uint32_t)0x00040000U)         /*!< IN endpoint interrupt */
-#define USB_OTG_GINTSTS_OEPINT                  ((uint32_t)0x00080000U)         /*!< OUT endpoint interrupt */
-#define USB_OTG_GINTSTS_IISOIXFR                ((uint32_t)0x00100000U)         /*!< Incomplete isochronous IN transfer */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       ((uint32_t)0x00200000U)         /*!< Incomplete periodic transfer */
-#define USB_OTG_GINTSTS_DATAFSUSP               ((uint32_t)0x00400000U)         /*!< Data fetch suspended */
-#define USB_OTG_GINTSTS_HPRTINT                 ((uint32_t)0x01000000U)         /*!< Host port interrupt */
-#define USB_OTG_GINTSTS_HCINT                   ((uint32_t)0x02000000U)         /*!< Host channels interrupt */
-#define USB_OTG_GINTSTS_PTXFE                   ((uint32_t)0x04000000U)         /*!< Periodic TxFIFO empty */
-#define USB_OTG_GINTSTS_LPMINT                   ((uint32_t)0x08000000U)        /*!< LPM interrupt */
-#define USB_OTG_GINTSTS_CIDSCHG                 ((uint32_t)0x10000000U)         /*!< Connector ID status change */
-#define USB_OTG_GINTSTS_DISCINT                 ((uint32_t)0x20000000U)         /*!< Disconnect detected interrupt */
-#define USB_OTG_GINTSTS_SRQINT                  ((uint32_t)0x40000000U)         /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT                  ((uint32_t)0x80000000U)         /*!< Resume/remote wakeup detected interrupt */
-
-/********************  Bit definition for USB_OTG_GINTMSK register  ********************/
-
-#define USB_OTG_GINTMSK_MMISM                   ((uint32_t)0x00000002U)         /*!< Mode mismatch interrupt mask */
-#define USB_OTG_GINTMSK_OTGINT                  ((uint32_t)0x00000004U)         /*!< OTG interrupt mask */
-#define USB_OTG_GINTMSK_SOFM                    ((uint32_t)0x00000008U)         /*!< Start of frame mask */
-#define USB_OTG_GINTMSK_RXFLVLM                 ((uint32_t)0x00000010U)         /*!< Receive FIFO nonempty mask */
-#define USB_OTG_GINTMSK_NPTXFEM                 ((uint32_t)0x00000020U)         /*!< Nonperiodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_GINAKEFFM               ((uint32_t)0x00000040U)         /*!< Global nonperiodic IN NAK effective mask */
-#define USB_OTG_GINTMSK_GONAKEFFM               ((uint32_t)0x00000080U)         /*!< Global OUT NAK effective mask */
-#define USB_OTG_GINTMSK_ESUSPM                  ((uint32_t)0x00000400U)         /*!< Early suspend mask */
-#define USB_OTG_GINTMSK_USBSUSPM                ((uint32_t)0x00000800U)         /*!< USB suspend mask */
-#define USB_OTG_GINTMSK_USBRST                  ((uint32_t)0x00001000U)         /*!< USB reset mask */
-#define USB_OTG_GINTMSK_ENUMDNEM                ((uint32_t)0x00002000U)         /*!< Enumeration done mask */
-#define USB_OTG_GINTMSK_ISOODRPM                ((uint32_t)0x00004000U)         /*!< Isochronous OUT packet dropped interrupt mask */
-#define USB_OTG_GINTMSK_EOPFM                   ((uint32_t)0x00008000U)         /*!< End of periodic frame interrupt mask */
-#define USB_OTG_GINTMSK_EPMISM                  ((uint32_t)0x00020000U)         /*!< Endpoint mismatch interrupt mask */
-#define USB_OTG_GINTMSK_IEPINT                  ((uint32_t)0x00040000U)         /*!< IN endpoints interrupt mask */
-#define USB_OTG_GINTMSK_OEPINT                  ((uint32_t)0x00080000U)         /*!< OUT endpoints interrupt mask */
-#define USB_OTG_GINTMSK_IISOIXFRM               ((uint32_t)0x00100000U)         /*!< Incomplete isochronous IN transfer mask */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         ((uint32_t)0x00200000U)         /*!< Incomplete periodic transfer mask */
-#define USB_OTG_GINTMSK_FSUSPM                  ((uint32_t)0x00400000U)         /*!< Data fetch suspended mask */
-#define USB_OTG_GINTMSK_PRTIM                   ((uint32_t)0x01000000U)         /*!< Host port interrupt mask */
-#define USB_OTG_GINTMSK_HCIM                    ((uint32_t)0x02000000U)         /*!< Host channels interrupt mask */
-#define USB_OTG_GINTMSK_PTXFEM                  ((uint32_t)0x04000000U)         /*!< Periodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_LPMINTM                 ((uint32_t)0x08000000U)         /*!< LPM interrupt Mask */
-#define USB_OTG_GINTMSK_CIDSCHGM                ((uint32_t)0x10000000U)         /*!< Connector ID status change mask */
-#define USB_OTG_GINTMSK_DISCINT                 ((uint32_t)0x20000000U)         /*!< Disconnect detected interrupt mask */
-#define USB_OTG_GINTMSK_SRQIM                   ((uint32_t)0x40000000U)         /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM                    ((uint32_t)0x80000000U)         /*!< Resume/remote wakeup detected interrupt mask */
-
-/********************  Bit definition for USB_OTG_DAINT register  ********************/
-#define USB_OTG_DAINT_IEPINT                  ((uint32_t)0x0000FFFFU)            /*!< IN endpoint interrupt bits */
-#define USB_OTG_DAINT_OEPINT                  ((uint32_t)0xFFFF0000U)            /*!< OUT endpoint interrupt bits */
-
-/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
-#define USB_OTG_HAINTMSK_HAINTM                  ((uint32_t)0x0000FFFFU)        /*!< Channel interrupt mask */
-
-/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
-#define USB_OTG_GRXSTSP_EPNUM                    ((uint32_t)0x0000000FU)        /*!< IN EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_BCNT                     ((uint32_t)0x00007FF0U)        /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID                     ((uint32_t)0x00018000U)        /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS                   ((uint32_t)0x001E0000U)        /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
-#define USB_OTG_DAINTMSK_IEPM                    ((uint32_t)0x0000FFFFU)        /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM                    ((uint32_t)0xFFFF0000U)        /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for OTG register  ********************/
-
-#define USB_OTG_CHNUM                   ((uint32_t)0x0000000FU)                 /*!< Channel number */
-#define USB_OTG_CHNUM_0                 ((uint32_t)0x00000001U)                 /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 ((uint32_t)0x00000002U)                 /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 ((uint32_t)0x00000004U)                 /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 ((uint32_t)0x00000008U)                 /*!<Bit 3 */
-#define USB_OTG_BCNT                    ((uint32_t)0x00007FF0U)                 /*!< Byte count */                                                                             
-#define USB_OTG_DPID                    ((uint32_t)0x00018000U)                 /*!< Data PID */
-#define USB_OTG_DPID_0                  ((uint32_t)0x00008000U)                 /*!<Bit 0 */
-#define USB_OTG_DPID_1                  ((uint32_t)0x00010000U)                 /*!<Bit 1 */                                                                           
-#define USB_OTG_PKTSTS                  ((uint32_t)0x001E0000U)                 /*!< Packet status */
-#define USB_OTG_PKTSTS_0                ((uint32_t)0x00020000U)                 /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                ((uint32_t)0x00040000U)                 /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                ((uint32_t)0x00080000U)                 /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                ((uint32_t)0x00100000U)                 /*!<Bit 3 */                                                                         
-#define USB_OTG_EPNUM                   ((uint32_t)0x0000000FU)                 /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 ((uint32_t)0x00000001U)                 /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 ((uint32_t)0x00000002U)                 /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 ((uint32_t)0x00000004U)                 /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 ((uint32_t)0x00000008U)                 /*!<Bit 3 */                                                                            
-#define USB_OTG_FRMNUM                  ((uint32_t)0x01E00000U)                 /*!< Frame number */
-#define USB_OTG_FRMNUM_0                ((uint32_t)0x00200000U)                 /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                ((uint32_t)0x00400000U)                 /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                ((uint32_t)0x00800000U)                 /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                ((uint32_t)0x01000000U)                 /*!<Bit 3 */
-
-/********************  Bit definition for OTG register  ********************/
-
-#define USB_OTG_CHNUM                   ((uint32_t)0x0000000FU)                 /*!< Channel number */
-#define USB_OTG_CHNUM_0                 ((uint32_t)0x00000001U)                 /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 ((uint32_t)0x00000002U)                 /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 ((uint32_t)0x00000004U)                 /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 ((uint32_t)0x00000008U)                 /*!<Bit 3 */
-#define USB_OTG_BCNT                    ((uint32_t)0x00007FF0U)                 /*!< Byte count */                                                                         
-#define USB_OTG_DPID                    ((uint32_t)0x00018000U)                 /*!< Data PID */
-#define USB_OTG_DPID_0                  ((uint32_t)0x00008000U)                 /*!<Bit 0 */
-#define USB_OTG_DPID_1                  ((uint32_t)0x00010000U)                 /*!<Bit 1 */                                                                         
-#define USB_OTG_PKTSTS                  ((uint32_t)0x001E0000U)                 /*!< Packet status */
-#define USB_OTG_PKTSTS_0                ((uint32_t)0x00020000U)                 /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                ((uint32_t)0x00040000U)                 /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                ((uint32_t)0x00080000U)                 /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                ((uint32_t)0x00100000U)                 /*!<Bit 3 */                                                                            
-#define USB_OTG_EPNUM                   ((uint32_t)0x0000000FU)                 /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 ((uint32_t)0x00000001U)                 /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 ((uint32_t)0x00000002U)                 /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 ((uint32_t)0x00000004U)                 /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 ((uint32_t)0x00000008U)                 /*!<Bit 3 */                                                                             
-#define USB_OTG_FRMNUM                  ((uint32_t)0x01E00000U)                 /*!< Frame number */
-#define USB_OTG_FRMNUM_0                ((uint32_t)0x00200000U)                 /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                ((uint32_t)0x00400000U)                 /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                ((uint32_t)0x00800000U)                 /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                ((uint32_t)0x01000000U)                 /*!<Bit 3 */
-
-/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
-#define USB_OTG_GRXFSIZ_RXFD                    ((uint32_t)0x0000FFFFU)         /*!< RxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
-#define USB_OTG_DVBUSDIS_VBUSDT                  ((uint32_t)0x0000FFFFU)        /*!< Device VBUS discharge time */
-
-/********************  Bit definition for OTG register  ********************/
-#define USB_OTG_NPTXFSA                 ((uint32_t)0x0000FFFFU)                 /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD                  ((uint32_t)0xFFFF0000U)                 /*!< Nonperiodic TxFIFO depth */
-#define USB_OTG_TX0FSA                  ((uint32_t)0x0000FFFFU)                 /*!< Endpoint 0 transmit RAM start address */
-#define USB_OTG_TX0FD                   ((uint32_t)0xFFFF0000U)                 /*!< Endpoint 0 TxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DVBUSPULSE register  ********************/
-#define USB_OTG_DVBUSPULSE_DVBUSP                  ((uint32_t)0x00000FFFU)      /*!< Device VBUS pulsing time */
-
-/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
-#define USB_OTG_GNPTXSTS_NPTXFSAV                ((uint32_t)0x0000FFFFU)        /*!< Nonperiodic TxFIFO space available */
-
-#define USB_OTG_GNPTXSTS_NPTQXSAV                ((uint32_t)0x00FF0000U)        /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0              ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1              ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2              ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3              ((uint32_t)0x00080000U)        /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4              ((uint32_t)0x00100000U)        /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5              ((uint32_t)0x00200000U)        /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6              ((uint32_t)0x00400000U)        /*!<Bit 6 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7              ((uint32_t)0x00800000U)        /*!<Bit 7 */
-
-#define USB_OTG_GNPTXSTS_NPTXQTOP                ((uint32_t)0x7F000000U)        /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0              ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1              ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2              ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3              ((uint32_t)0x08000000U)        /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4              ((uint32_t)0x10000000U)        /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5              ((uint32_t)0x20000000U)        /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6              ((uint32_t)0x40000000U)        /*!<Bit 6 */
-
-/********************  Bit definition for USB_OTG_DTHRCTL register  ***************/
-#define USB_OTG_DTHRCTL_NONISOTHREN             ((uint32_t)0x00000001U)         /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN                ((uint32_t)0x00000002U)         /*!< ISO IN endpoint threshold enable */
-
-#define USB_OTG_DTHRCTL_TXTHRLEN                ((uint32_t)0x000007FCU)         /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0              ((uint32_t)0x00000004U)         /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1              ((uint32_t)0x00000008U)         /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2              ((uint32_t)0x00000010U)         /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3              ((uint32_t)0x00000020U)         /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4              ((uint32_t)0x00000040U)         /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5              ((uint32_t)0x00000080U)         /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6              ((uint32_t)0x00000100U)         /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7              ((uint32_t)0x00000200U)         /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8              ((uint32_t)0x00000400U)         /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_RXTHREN                 ((uint32_t)0x00010000U)         /*!< Receive threshold enable */
-
-#define USB_OTG_DTHRCTL_RXTHRLEN                ((uint32_t)0x03FE0000U)         /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0              ((uint32_t)0x00020000U)         /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1              ((uint32_t)0x00040000U)         /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2              ((uint32_t)0x00080000U)         /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3              ((uint32_t)0x00100000U)         /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4              ((uint32_t)0x00200000U)         /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5              ((uint32_t)0x00400000U)         /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6              ((uint32_t)0x00800000U)         /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7              ((uint32_t)0x01000000U)         /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8              ((uint32_t)0x02000000U)         /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_ARPEN                   ((uint32_t)0x08000000U)         /*!< Arbiter parking enable */
-
-/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ***************/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM               ((uint32_t)0x0000FFFFU)      /*!< IN EP Tx FIFO empty interrupt mask bits */
-
-/********************  Bit definition for USB_OTG_DEACHINT register  ********************/
-#define USB_OTG_DEACHINT_IEP1INT                 ((uint32_t)0x00000002U)        /*!< IN endpoint 1interrupt bit */
-#define USB_OTG_DEACHINT_OEP1INT                 ((uint32_t)0x00020000U)        /*!< OUT endpoint 1 interrupt bit */
-
-/********************  Bit definition for USB_OTG_GCCFG register  ********************/
-#define USB_OTG_GCCFG_DCDET                  ((uint32_t)0x00000001U)            /*!< Data contact detection (DCD) status */
-#define USB_OTG_GCCFG_PDET                   ((uint32_t)0x00000002U)            /*!< Primary detection (PD) status */
-#define USB_OTG_GCCFG_SDET                   ((uint32_t)0x00000004U)            /*!< Secondary detection (SD) status */
-#define USB_OTG_GCCFG_PS2DET                 ((uint32_t)0x00000008U)            /*!< DM pull-up detection status */
-#define USB_OTG_GCCFG_PWRDWN                 ((uint32_t)0x00010000U)            /*!< Power down */
-#define USB_OTG_GCCFG_BCDEN                  ((uint32_t)0x00020000U)            /*!< Battery charging detector (BCD) enable */
-#define USB_OTG_GCCFG_DCDEN                  ((uint32_t)0x00040000U)            /*!< Data contact detection (DCD) mode enable*/
-#define USB_OTG_GCCFG_PDEN                   ((uint32_t)0x00080000U)            /*!< Primary detection (PD) mode enable*/
-#define USB_OTG_GCCFG_SDEN                   ((uint32_t)0x00100000U)            /*!< Secondary detection (SD) mode enable */
-#define USB_OTG_GCCFG_VBDEN                  ((uint32_t)0x00200000U)            /*!< Secondary detection (SD) mode enable */
-
-/********************  Bit definition for USB_OTG_GPWRDN) register  ********************/
-#define USB_OTG_GPWRDN_DISABLEVBUS                 ((uint32_t)0x00000040U)      /*!< Power down */
-
-/********************  Bit definition for USB_OTG_DEACHINTMSK register  ********************/
-#define USB_OTG_DEACHINTMSK_IEP1INTM                ((uint32_t)0x00000002U)     /*!< IN Endpoint 1 interrupt mask bit */
-#define USB_OTG_DEACHINTMSK_OEP1INTM                ((uint32_t)0x00020000U)     /*!< OUT Endpoint 1 interrupt mask bit */
-
-/********************  Bit definition for USB_OTG_CID register  ********************/
-#define USB_OTG_CID_PRODUCT_ID              ((uint32_t)0xFFFFFFFFU)             /*!< Product ID field */
-
-
-/********************  Bit definition for USB_OTG_GHWCFG3 register  ********************/
-#define  USB_OTG_GHWCFG3_LPMMode              ((uint32_t)0x00004000U)           /* LPM mode specified for Mode of Operation */ 
-
-/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/
-#define  USB_OTG_GLPMCFG_ENBESL                      ((uint32_t)0x10000000U)    /* Enable best effort service latency */ 
-#define  USB_OTG_GLPMCFG_LPMRCNTSTS                  ((uint32_t)0x0E000000U)    /* LPM retry count status */ 
-#define  USB_OTG_GLPMCFG_SNDLPM                      ((uint32_t)0x01000000U)    /* Send LPM transaction */ 
-#define  USB_OTG_GLPMCFG_LPMRCNT                     ((uint32_t)0x00E00000U)    /* LPM retry count */ 
-#define  USB_OTG_GLPMCFG_LPMCHIDX                    ((uint32_t)0x001E0000U)    /* LPMCHIDX: */ 
-#define  USB_OTG_GLPMCFG_L1ResumeOK                  ((uint32_t)0x00010000U)    /* Sleep State Resume OK */ 
-#define  USB_OTG_GLPMCFG_SLPSTS                      ((uint32_t)0x00008000U)    /* Port sleep status */ 
-#define  USB_OTG_GLPMCFG_LPMRSP                      ((uint32_t)0x00006000U)    /* LPM response */ 
-#define  USB_OTG_GLPMCFG_L1DSEN                      ((uint32_t)0x00001000U)    /* L1 deep sleep enable */ 
-#define  USB_OTG_GLPMCFG_BESLTHRS                    ((uint32_t)0x00000F00U)    /* BESL threshold */ 
-#define  USB_OTG_GLPMCFG_L1SSEN                      ((uint32_t)0x00000080U)    /* L1 shallow sleep enable */ 
-#define  USB_OTG_GLPMCFG_REMWAKE                     ((uint32_t)0x00000040U)    /* bRemoteWake value received with last ACKed LPM Token */ 
-#define  USB_OTG_GLPMCFG_BESL                        ((uint32_t)0x0000003CU)    /* BESL value received with last ACKed LPM Token  */
-#define  USB_OTG_GLPMCFG_LPMACK                      ((uint32_t)0x00000002U)    /* LPM Token acknowledge enable*/
-#define  USB_OTG_GLPMCFG_LPMEN                       ((uint32_t)0x00000001U)    /* LPM support enable  */
-
-
-/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
-#define USB_OTG_DIEPEACHMSK1_XFRCM                   ((uint32_t)0x00000001U)    /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_EPDM                    ((uint32_t)0x00000002U)    /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_TOM                     ((uint32_t)0x00000008U)    /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK               ((uint32_t)0x00000010U)    /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM                 ((uint32_t)0x00000020U)    /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM                 ((uint32_t)0x00000040U)    /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPEACHMSK1_TXFURM                  ((uint32_t)0x00000100U)    /*!< FIFO underrun mask */
-#define USB_OTG_DIEPEACHMSK1_BIM                     ((uint32_t)0x00000200U)    /*!< BNA interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_NAKM                    ((uint32_t)0x00002000U)    /*!< NAK interrupt mask */
-
-/********************  Bit definition for USB_OTG_HPRT register  ********************/
-#define USB_OTG_HPRT_PCSTS                   ((uint32_t)0x00000001U)            /*!< Port connect status */
-#define USB_OTG_HPRT_PCDET                   ((uint32_t)0x00000002U)            /*!< Port connect detected */
-#define USB_OTG_HPRT_PENA                    ((uint32_t)0x00000004U)            /*!< Port enable */
-#define USB_OTG_HPRT_PENCHNG                 ((uint32_t)0x00000008U)            /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA                    ((uint32_t)0x00000010U)            /*!< Port overcurrent active */
-#define USB_OTG_HPRT_POCCHNG                 ((uint32_t)0x00000020U)            /*!< Port overcurrent change */
-#define USB_OTG_HPRT_PRES                    ((uint32_t)0x00000040U)            /*!< Port resume */
-#define USB_OTG_HPRT_PSUSP                   ((uint32_t)0x00000080U)            /*!< Port suspend */
-#define USB_OTG_HPRT_PRST                    ((uint32_t)0x00000100U)            /*!< Port reset */
-
-#define USB_OTG_HPRT_PLSTS                   ((uint32_t)0x00000C00U)            /*!< Port line status */
-#define USB_OTG_HPRT_PLSTS_0                 ((uint32_t)0x00000400U)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PLSTS_1                 ((uint32_t)0x00000800U)            /*!<Bit 1 */
-#define USB_OTG_HPRT_PPWR                    ((uint32_t)0x00001000U)            /*!< Port power */
-
-#define USB_OTG_HPRT_PTCTL                   ((uint32_t)0x0001E000U)            /*!< Port test control */
-#define USB_OTG_HPRT_PTCTL_0                 ((uint32_t)0x00002000U)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PTCTL_1                 ((uint32_t)0x00004000U)            /*!<Bit 1 */
-#define USB_OTG_HPRT_PTCTL_2                 ((uint32_t)0x00008000U)            /*!<Bit 2 */
-#define USB_OTG_HPRT_PTCTL_3                 ((uint32_t)0x00010000U)            /*!<Bit 3 */
-
-#define USB_OTG_HPRT_PSPD                    ((uint32_t)0x00060000U)            /*!< Port speed */
-#define USB_OTG_HPRT_PSPD_0                  ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PSPD_1                  ((uint32_t)0x00040000U)            /*!<Bit 1 */
-
-/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
-#define USB_OTG_DOEPEACHMSK1_XFRCM                   ((uint32_t)0x00000001U)    /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_EPDM                    ((uint32_t)0x00000002U)    /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_TOM                     ((uint32_t)0x00000008U)    /*!< Timeout condition mask */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               ((uint32_t)0x00000010U)    /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM                 ((uint32_t)0x00000020U)    /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM                 ((uint32_t)0x00000040U)    /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DOEPEACHMSK1_TXFURM                  ((uint32_t)0x00000100U)    /*!< OUT packet error mask */
-#define USB_OTG_DOEPEACHMSK1_BIM                     ((uint32_t)0x00000200U)    /*!< BNA interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_BERRM                   ((uint32_t)0x00001000U)    /*!< Bubble error interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NAKM                    ((uint32_t)0x00002000U)    /*!< NAK interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NYETM                   ((uint32_t)0x00004000U)    /*!< NYET interrupt mask */
-
-/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
-#define USB_OTG_HPTXFSIZ_PTXSA                   ((uint32_t)0x0000FFFFU)        /*!< Host periodic TxFIFO start address */
-#define USB_OTG_HPTXFSIZ_PTXFD                   ((uint32_t)0xFFFF0000U)        /*!< Host periodic TxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
-#define USB_OTG_DIEPCTL_MPSIZ                   ((uint32_t)0x000007FFU)         /*!< Maximum packet size */
-#define USB_OTG_DIEPCTL_USBAEP                  ((uint32_t)0x00008000U)         /*!< USB active endpoint */
-#define USB_OTG_DIEPCTL_EONUM_DPID              ((uint32_t)0x00010000U)         /*!< Even/odd frame */
-#define USB_OTG_DIEPCTL_NAKSTS                  ((uint32_t)0x00020000U)         /*!< NAK status */
-                                                                             
-#define USB_OTG_DIEPCTL_EPTYP                   ((uint32_t)0x000C0000U)         /*!< Endpoint type */
-#define USB_OTG_DIEPCTL_EPTYP_0                 ((uint32_t)0x00040000U)         /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_EPTYP_1                 ((uint32_t)0x00080000U)         /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_STALL                   ((uint32_t)0x00200000U)         /*!< STALL handshake */
-                                                                             
-#define USB_OTG_DIEPCTL_TXFNUM                  ((uint32_t)0x03C00000U)         /*!< TxFIFO number */
-#define USB_OTG_DIEPCTL_TXFNUM_0                ((uint32_t)0x00400000U)         /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                ((uint32_t)0x00800000U)         /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                ((uint32_t)0x01000000U)         /*!<Bit 2 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                ((uint32_t)0x02000000U)         /*!<Bit 3 */
-#define USB_OTG_DIEPCTL_CNAK                    ((uint32_t)0x04000000U)         /*!< Clear NAK */
-#define USB_OTG_DIEPCTL_SNAK                    ((uint32_t)0x08000000U)         /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          ((uint32_t)0x10000000U)         /*!< Set DATA0 PID */
-#define USB_OTG_DIEPCTL_SODDFRM                 ((uint32_t)0x20000000U)         /*!< Set odd frame */
-#define USB_OTG_DIEPCTL_EPDIS                   ((uint32_t)0x40000000U)         /*!< Endpoint disable */
-#define USB_OTG_DIEPCTL_EPENA                   ((uint32_t)0x80000000U)         /*!< Endpoint enable */
-
-/********************  Bit definition for USB_OTG_HCCHAR register  ********************/
-#define USB_OTG_HCCHAR_MPSIZ                   ((uint32_t)0x000007FFU)          /*!< Maximum packet size */
-                                                                              
-#define USB_OTG_HCCHAR_EPNUM                   ((uint32_t)0x00007800U)          /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                 ((uint32_t)0x00000800U)          /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPNUM_1                 ((uint32_t)0x00001000U)          /*!<Bit 1 */
-#define USB_OTG_HCCHAR_EPNUM_2                 ((uint32_t)0x00002000U)          /*!<Bit 2 */
-#define USB_OTG_HCCHAR_EPNUM_3                 ((uint32_t)0x00004000U)          /*!<Bit 3 */
-#define USB_OTG_HCCHAR_EPDIR                   ((uint32_t)0x00008000U)          /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV                   ((uint32_t)0x00020000U)          /*!< Low-speed device */
-                                                                              
-#define USB_OTG_HCCHAR_EPTYP                   ((uint32_t)0x000C0000U)          /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                 ((uint32_t)0x00040000U)          /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPTYP_1                 ((uint32_t)0x00080000U)          /*!<Bit 1 */
-                                                                              
-#define USB_OTG_HCCHAR_MC                      ((uint32_t)0x00300000U)          /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                    ((uint32_t)0x00100000U)          /*!<Bit 0 */
-#define USB_OTG_HCCHAR_MC_1                    ((uint32_t)0x00200000U)          /*!<Bit 1 */
-                                                                              
-#define USB_OTG_HCCHAR_DAD                     ((uint32_t)0x1FC00000U)          /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                   ((uint32_t)0x00400000U)          /*!<Bit 0 */
-#define USB_OTG_HCCHAR_DAD_1                   ((uint32_t)0x00800000U)          /*!<Bit 1 */
-#define USB_OTG_HCCHAR_DAD_2                   ((uint32_t)0x01000000U)          /*!<Bit 2 */
-#define USB_OTG_HCCHAR_DAD_3                   ((uint32_t)0x02000000U)          /*!<Bit 3 */
-#define USB_OTG_HCCHAR_DAD_4                   ((uint32_t)0x04000000U)          /*!<Bit 4 */
-#define USB_OTG_HCCHAR_DAD_5                   ((uint32_t)0x08000000U)          /*!<Bit 5 */
-#define USB_OTG_HCCHAR_DAD_6                   ((uint32_t)0x10000000U)          /*!<Bit 6 */
-#define USB_OTG_HCCHAR_ODDFRM                  ((uint32_t)0x20000000U)          /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS                   ((uint32_t)0x40000000U)          /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA                   ((uint32_t)0x80000000U)          /*!< Channel enable */
-
-/********************  Bit definition for USB_OTG_HCSPLT register  ********************/
-
-#define USB_OTG_HCSPLT_PRTADDR                 ((uint32_t)0x0000007FU)          /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0               ((uint32_t)0x00000001U)          /*!<Bit 0 */
-#define USB_OTG_HCSPLT_PRTADDR_1               ((uint32_t)0x00000002U)          /*!<Bit 1 */
-#define USB_OTG_HCSPLT_PRTADDR_2               ((uint32_t)0x00000004U)          /*!<Bit 2 */
-#define USB_OTG_HCSPLT_PRTADDR_3               ((uint32_t)0x00000008U)          /*!<Bit 3 */
-#define USB_OTG_HCSPLT_PRTADDR_4               ((uint32_t)0x00000010U)          /*!<Bit 4 */
-#define USB_OTG_HCSPLT_PRTADDR_5               ((uint32_t)0x00000020U)          /*!<Bit 5 */
-#define USB_OTG_HCSPLT_PRTADDR_6               ((uint32_t)0x00000040U)          /*!<Bit 6 */
-                                                                               
-#define USB_OTG_HCSPLT_HUBADDR                 ((uint32_t)0x00003F80U)          /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0               ((uint32_t)0x00000080U)          /*!<Bit 0 */
-#define USB_OTG_HCSPLT_HUBADDR_1               ((uint32_t)0x00000100U)          /*!<Bit 1 */
-#define USB_OTG_HCSPLT_HUBADDR_2               ((uint32_t)0x00000200U)          /*!<Bit 2 */
-#define USB_OTG_HCSPLT_HUBADDR_3               ((uint32_t)0x00000400U)          /*!<Bit 3 */
-#define USB_OTG_HCSPLT_HUBADDR_4               ((uint32_t)0x00000800U)          /*!<Bit 4 */
-#define USB_OTG_HCSPLT_HUBADDR_5               ((uint32_t)0x00001000U)          /*!<Bit 5 */
-#define USB_OTG_HCSPLT_HUBADDR_6               ((uint32_t)0x00002000U)          /*!<Bit 6 */
-                                                                               
-#define USB_OTG_HCSPLT_XACTPOS                 ((uint32_t)0x0000C000U)          /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0               ((uint32_t)0x00004000U)          /*!<Bit 0 */
-#define USB_OTG_HCSPLT_XACTPOS_1               ((uint32_t)0x00008000U)          /*!<Bit 1 */
-#define USB_OTG_HCSPLT_COMPLSPLT               ((uint32_t)0x00010000U)          /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN                 ((uint32_t)0x80000000U)          /*!< Split enable */
-
-/********************  Bit definition for USB_OTG_HCINT register  ********************/
-#define USB_OTG_HCINT_XFRC                    ((uint32_t)0x00000001U)           /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH                     ((uint32_t)0x00000002U)           /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR                  ((uint32_t)0x00000004U)           /*!< AHB error */
-#define USB_OTG_HCINT_STALL                   ((uint32_t)0x00000008U)           /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK                     ((uint32_t)0x00000010U)           /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK                     ((uint32_t)0x00000020U)           /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET                    ((uint32_t)0x00000040U)           /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR                   ((uint32_t)0x00000080U)           /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR                   ((uint32_t)0x00000100U)           /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR                   ((uint32_t)0x00000200U)           /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR                   ((uint32_t)0x00000400U)           /*!< Data toggle error */
-
-/********************  Bit definition for USB_OTG_DIEPINT register  ********************/
-#define USB_OTG_DIEPINT_XFRC                    ((uint32_t)0x00000001U)         /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD                  ((uint32_t)0x00000002U)         /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_TOC                     ((uint32_t)0x00000008U)         /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE                  ((uint32_t)0x00000010U)         /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNE                  ((uint32_t)0x00000040U)         /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE                    ((uint32_t)0x00000080U)         /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN              ((uint32_t)0x00000100U)         /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA                     ((uint32_t)0x00000200U)         /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS               ((uint32_t)0x00000800U)         /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR                    ((uint32_t)0x00001000U)         /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK                     ((uint32_t)0x00002000U)         /*!< NAK interrupt */
-
-/********************  Bit definition for USB_OTG_HCINTMSK register  ********************/
-#define USB_OTG_HCINTMSK_XFRCM                   ((uint32_t)0x00000001U)        /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM                    ((uint32_t)0x00000002U)        /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR                  ((uint32_t)0x00000004U)        /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM                  ((uint32_t)0x00000008U)        /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM                    ((uint32_t)0x00000010U)        /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM                    ((uint32_t)0x00000020U)        /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET                    ((uint32_t)0x00000040U)        /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM                  ((uint32_t)0x00000080U)        /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM                  ((uint32_t)0x00000100U)        /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM                  ((uint32_t)0x00000200U)        /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM                  ((uint32_t)0x00000400U)        /*!< Data toggle error mask */
-
-/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
-
-#define USB_OTG_DIEPTSIZ_XFRSIZ                  ((uint32_t)0x0007FFFFU)        /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT                  ((uint32_t)0x1FF80000U)        /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT                  ((uint32_t)0x60000000U)        /*!< Packet count */
-/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
-#define USB_OTG_HCTSIZ_XFRSIZ                    ((uint32_t)0x0007FFFFU)        /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT                    ((uint32_t)0x1FF80000U)        /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING                    ((uint32_t)0x80000000U)        /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID                      ((uint32_t)0x60000000U)        /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                    ((uint32_t)0x20000000U)        /*!<Bit 0 */
-#define USB_OTG_HCTSIZ_DPID_1                    ((uint32_t)0x40000000U)        /*!<Bit 1 */
-
-/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
-#define USB_OTG_DIEPDMA_DMAADDR                  ((uint32_t)0xFFFFFFFFU)        /*!< DMA address */
-
-/********************  Bit definition for USB_OTG_HCDMA register  ********************/
-#define USB_OTG_HCDMA_DMAADDR                    ((uint32_t)0xFFFFFFFFU)        /*!< DMA address */
-
-/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
-#define USB_OTG_DTXFSTS_INEPTFSAV                ((uint32_t)0x0000FFFFU)        /*!< IN endpoint TxFIFO space avail */
-
-/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
-#define USB_OTG_DIEPTXF_INEPTXSA                 ((uint32_t)0x0000FFFFU)        /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD                 ((uint32_t)0xFFFF0000U)        /*!< IN endpoint TxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
-
-#define USB_OTG_DOEPCTL_MPSIZ                     ((uint32_t)0x000007FFU)       /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP                    ((uint32_t)0x00008000U)       /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS                    ((uint32_t)0x00020000U)       /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            ((uint32_t)0x10000000U)       /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM                   ((uint32_t)0x20000000U)       /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP                     ((uint32_t)0x000C0000U)       /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                   ((uint32_t)0x00040000U)       /*!<Bit 0 */
-#define USB_OTG_DOEPCTL_EPTYP_1                   ((uint32_t)0x00080000U)       /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_SNPM                      ((uint32_t)0x00100000U)       /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL                     ((uint32_t)0x00200000U)       /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK                      ((uint32_t)0x04000000U)       /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK                      ((uint32_t)0x08000000U)       /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS                     ((uint32_t)0x40000000U)       /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA                     ((uint32_t)0x80000000U)       /*!< Endpoint enable */
-
-/********************  Bit definition for USB_OTG_DOEPINT register  ********************/
-#define USB_OTG_DOEPINT_XFRC                    ((uint32_t)0x00000001U)         /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD                  ((uint32_t)0x00000002U)         /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_STUP                    ((uint32_t)0x00000008U)         /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS                 ((uint32_t)0x00000010U)         /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_B2BSTUP                 ((uint32_t)0x00000040U)         /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_NYET                    ((uint32_t)0x00004000U)         /*!< NYET interrupt */
-
-/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
-
-#define USB_OTG_DOEPTSIZ_XFRSIZ                  ((uint32_t)0x0007FFFFU)        /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT                  ((uint32_t)0x1FF80000U)        /*!< Packet count */
-
-#define USB_OTG_DOEPTSIZ_STUPCNT                 ((uint32_t)0x60000000U)        /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0               ((uint32_t)0x20000000U)        /*!<Bit 0 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1               ((uint32_t)0x40000000U)        /*!<Bit 1 */
-
-/********************  Bit definition for PCGCCTL register  ********************/
-#define USB_OTG_PCGCCTL_STOPCLK                 ((uint32_t)0x00000001U)         /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK                 ((uint32_t)0x00000002U)         /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP                 ((uint32_t)0x00000010U)         /*!<Bit 1 */
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
-                                       ((INSTANCE) == ADC2) || \
-                                       ((INSTANCE) == ADC3))
-
-#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
-
-/******************************** CAN Instances ******************************/
-#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
-
-/******************************** COMP Instances ******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                        ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
-
-/******************** COMP Instances with window mode capability **************/
-#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
-
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DAC Instances ********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
-
-/****************************** DFSDM Instances *******************************/
-#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM_Filter0) || \
-                                                ((INSTANCE) == DFSDM_Filter1) || \
-                                                ((INSTANCE) == DFSDM_Filter2) || \
-                                                ((INSTANCE) == DFSDM_Filter3))
-
-#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM_Channel0) || \
-                                                 ((INSTANCE) == DFSDM_Channel1) || \
-                                                 ((INSTANCE) == DFSDM_Channel2) || \
-                                                 ((INSTANCE) == DFSDM_Channel3) || \
-                                                 ((INSTANCE) == DFSDM_Channel4) || \
-                                                 ((INSTANCE) == DFSDM_Channel5) || \
-                                                 ((INSTANCE) == DFSDM_Channel6) || \
-                                                 ((INSTANCE) == DFSDM_Channel7))
-
-/******************************** DMA Instances *******************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7) || \
-                                       ((INSTANCE) == DMA2_Channel1) || \
-                                       ((INSTANCE) == DMA2_Channel2) || \
-                                       ((INSTANCE) == DMA2_Channel3) || \
-                                       ((INSTANCE) == DMA2_Channel4) || \
-                                       ((INSTANCE) == DMA2_Channel5) || \
-                                       ((INSTANCE) == DMA2_Channel6) || \
-                                       ((INSTANCE) == DMA2_Channel7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOF) || \
-                                        ((INSTANCE) == GPIOG) || \
-                                        ((INSTANCE) == GPIOH))
-
-/******************************* GPIO AF Instances ****************************/
-/* On L4, all GPIO Bank support AF */
-#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/**************************** GPIO Lock Instances *****************************/
-/* On L4, all GPIO Bank support the Lock mechanism */
-#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2) || \
-                                       ((INSTANCE) == I2C3))
-
-/******************************* LCD Instances ********************************/
-#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
-
-/******************************* HCD Instances *******************************/
-#define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
-
-/****************************** OPAMP Instances *******************************/
-#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
-                                         ((INSTANCE) == OPAMP2))
-
-#define IS_OPAMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP12_COMMON)
-
-/******************************* PCD Instances *******************************/
-#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
-
-/******************************* QSPI Instances *******************************/
-#define IS_QSPI_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == QUADSPI)
-
-/******************************* RNG Instances ********************************/
-#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SAI Instances *******************************/
-#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
-                                       ((INSTANCE) == SAI1_Block_B) || \
-                                       ((INSTANCE) == SAI2_Block_A) || \
-                                       ((INSTANCE) == SAI2_Block_B))
-
-/****************************** SDMMC Instances *******************************/
-#define IS_SDMMC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDMMC1)
-
-/****************************** SMBUS Instances *******************************/
-#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                         ((INSTANCE) == I2C2) || \
-                                         ((INSTANCE) == I2C3))
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-
-/******************************** SWPMI Instances *****************************/
-#define IS_SWPMI_INSTANCE(INSTANCE)  ((INSTANCE) == SWPMI1)
-
-/****************** LPTIM Instances : All supported instances *****************/
-#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \
-                                         ((INSTANCE) == LPTIM2))
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
-                                         ((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM3)   || \
-                                         ((INSTANCE) == TIM4)   || \
-                                         ((INSTANCE) == TIM5)   || \
-                                         ((INSTANCE) == TIM6)   || \
-                                         ((INSTANCE) == TIM7)   || \
-                                         ((INSTANCE) == TIM8)   || \
-                                         ((INSTANCE) == TIM15)  || \
-                                         ((INSTANCE) == TIM16)  || \
-                                         ((INSTANCE) == TIM17))
-
-/****************** TIM Instances : supporting 32 bits counter ****************/
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                               ((INSTANCE) == TIM5))
-
-/****************** TIM Instances : supporting the break function *************/
-#define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
-                                            ((INSTANCE) == TIM8)    || \
-                                            ((INSTANCE) == TIM15)   || \
-                                            ((INSTANCE) == TIM16)   || \
-                                            ((INSTANCE) == TIM17))
-
-/************** TIM Instances : supporting Break source selection *************/
-#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
-                                               ((INSTANCE) == TIM8)   || \
-                                               ((INSTANCE) == TIM15)  || \
-                                               ((INSTANCE) == TIM16)  || \
-                                               ((INSTANCE) == TIM17))
-
-/****************** TIM Instances : supporting 2 break inputs *****************/
-#define IS_TIM_BKIN2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
-                                            ((INSTANCE) == TIM8))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
-                                         ((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM3)   || \
-                                         ((INSTANCE) == TIM4)   || \
-                                         ((INSTANCE) == TIM5)   || \
-                                         ((INSTANCE) == TIM8)   || \
-                                         ((INSTANCE) == TIM15)  || \
-                                         ((INSTANCE) == TIM16)  || \
-                                         ((INSTANCE) == TIM17))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
-                                         ((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM3)   || \
-                                         ((INSTANCE) == TIM4)   || \
-                                         ((INSTANCE) == TIM5)   || \
-                                         ((INSTANCE) == TIM8)   || \
-                                         ((INSTANCE) == TIM15))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
-                                         ((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM3)   || \
-                                         ((INSTANCE) == TIM4)   || \
-                                         ((INSTANCE) == TIM5)   || \
-                                         ((INSTANCE) == TIM8))
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
-                                         ((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM3)   || \
-                                         ((INSTANCE) == TIM4)   || \
-                                         ((INSTANCE) == TIM5)   || \
-                                         ((INSTANCE) == TIM8))
-
-/****************** TIM Instances : at least 5 capture/compare channels *******/
-#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
-                                         ((INSTANCE) == TIM8))
-
-/****************** TIM Instances : at least 6 capture/compare channels *******/
-#define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
-                                         ((INSTANCE) == TIM8))
-
-/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
-#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \
-                                            ((INSTANCE) == TIM8)   || \
-                                            ((INSTANCE) == TIM15)  || \
-                                            ((INSTANCE) == TIM16)  || \
-                                            ((INSTANCE) == TIM17))
-
-/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
-#define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
-                                            ((INSTANCE) == TIM2)   || \
-                                            ((INSTANCE) == TIM3)   || \
-                                            ((INSTANCE) == TIM4)   || \
-                                            ((INSTANCE) == TIM5)   || \
-                                            ((INSTANCE) == TIM6)   || \
-                                            ((INSTANCE) == TIM7)   || \
-                                            ((INSTANCE) == TIM8)   || \
-                                            ((INSTANCE) == TIM15)  || \
-                                            ((INSTANCE) == TIM16)  || \
-                                            ((INSTANCE) == TIM17))
-
-/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
-                                            ((INSTANCE) == TIM2)   || \
-                                            ((INSTANCE) == TIM3)   || \
-                                            ((INSTANCE) == TIM4)   || \
-                                            ((INSTANCE) == TIM5)   || \
-                                            ((INSTANCE) == TIM8)   || \
-                                            ((INSTANCE) == TIM15)  || \
-                                            ((INSTANCE) == TIM16)  || \
-                                            ((INSTANCE) == TIM17))
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
-                                            ((INSTANCE) == TIM2)   || \
-                                            ((INSTANCE) == TIM3)   || \
-                                            ((INSTANCE) == TIM4)   || \
-                                            ((INSTANCE) == TIM5)   || \
-                                            ((INSTANCE) == TIM8)   || \
-                                            ((INSTANCE) == TIM15)  || \
-                                            ((INSTANCE) == TIM16)  || \
-                                            ((INSTANCE) == TIM17))
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM1) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4) ||          \
-      ((CHANNEL) == TIM_CHANNEL_5) ||          \
-      ((CHANNEL) == TIM_CHANNEL_6)))           \
-     ||                                        \
-     (((INSTANCE) == TIM2) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-     ||                                        \
-     (((INSTANCE) == TIM3) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-     ||                                        \
-     (((INSTANCE) == TIM4) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-     ||                                        \
-     (((INSTANCE) == TIM5) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-     ||                                        \
-     (((INSTANCE) == TIM8) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4) ||          \
-      ((CHANNEL) == TIM_CHANNEL_5) ||          \
-      ((CHANNEL) == TIM_CHANNEL_6)))           \
-     ||                                        \
-     (((INSTANCE) == TIM15) &&                 \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-     ||                                        \
-     (((INSTANCE) == TIM16) &&                 \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-     ||                                        \
-     (((INSTANCE) == TIM17) &&                 \
-      (((CHANNEL) == TIM_CHANNEL_1))))
-
-/****************** TIM Instances : supporting complementary output(s) ********/
-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
-   ((((INSTANCE) == TIM1) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3)))            \
-    ||                                          \
-    (((INSTANCE) == TIM8) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3)))            \
-    ||                                          \
-    (((INSTANCE) == TIM15) &&                   \
-     ((CHANNEL) == TIM_CHANNEL_1))              \
-    ||                                          \
-    (((INSTANCE) == TIM16) &&                   \
-     ((CHANNEL) == TIM_CHANNEL_1))              \
-    ||                                          \
-    (((INSTANCE) == TIM17) &&                   \
-     ((CHANNEL) == TIM_CHANNEL_1)))
-
-/****************** TIM Instances : supporting clock division *****************/
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)    || \
-                                                    ((INSTANCE) == TIM2)    || \
-                                                    ((INSTANCE) == TIM3)    || \
-                                                    ((INSTANCE) == TIM4)    || \
-                                                    ((INSTANCE) == TIM5)    || \
-                                                    ((INSTANCE) == TIM8)    || \
-                                                    ((INSTANCE) == TIM15)   || \
-                                                    ((INSTANCE) == TIM16)   || \
-                                                    ((INSTANCE) == TIM17))
-
-/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                                        ((INSTANCE) == TIM2) || \
-                                                        ((INSTANCE) == TIM3) || \
-                                                        ((INSTANCE) == TIM4) || \
-                                                        ((INSTANCE) == TIM5) || \
-                                                        ((INSTANCE) == TIM8) || \
-                                                        ((INSTANCE) == TIM15))
-
-/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                                        ((INSTANCE) == TIM2) || \
-                                                        ((INSTANCE) == TIM3) || \
-                                                        ((INSTANCE) == TIM4) || \
-                                                        ((INSTANCE) == TIM5) || \
-                                                        ((INSTANCE) == TIM8))
-
-/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \
-                                                        ((INSTANCE) == TIM2) || \
-                                                        ((INSTANCE) == TIM3) || \
-                                                        ((INSTANCE) == TIM4) || \
-                                                        ((INSTANCE) == TIM5) || \
-                                                        ((INSTANCE) == TIM8) || \
-                                                        ((INSTANCE) == TIM15))
-
-/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \
-                                                        ((INSTANCE) == TIM2) || \
-                                                        ((INSTANCE) == TIM3) || \
-                                                        ((INSTANCE) == TIM4) || \
-                                                        ((INSTANCE) == TIM5) || \
-                                                        ((INSTANCE) == TIM8) || \
-                                                        ((INSTANCE) == TIM15))
-
-/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
-#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
-                                                     ((INSTANCE) == TIM8))
-
-/****************** TIM Instances : supporting commutation event generation ***/
-#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
-                                                     ((INSTANCE) == TIM8)   || \
-                                                     ((INSTANCE) == TIM15)  || \
-                                                     ((INSTANCE) == TIM16)  || \
-                                                     ((INSTANCE) == TIM17))
-
-/****************** TIM Instances : supporting counting mode selection ********/
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                                        ((INSTANCE) == TIM2) || \
-                                                        ((INSTANCE) == TIM3) || \
-                                                        ((INSTANCE) == TIM4) || \
-                                                        ((INSTANCE) == TIM5) || \
-                                                        ((INSTANCE) == TIM8))
-
-/****************** TIM Instances : supporting encoder interface **************/
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
-                                                      ((INSTANCE) == TIM2)  || \
-                                                      ((INSTANCE) == TIM3)  || \
-                                                      ((INSTANCE) == TIM4)  || \
-                                                      ((INSTANCE) == TIM5)  || \
-                                                      ((INSTANCE) == TIM8))
-
-/****************** TIM Instances : supporting Hall sensor interface **********/
-#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
-                                                         ((INSTANCE) == TIM2)   || \
-                                                         ((INSTANCE) == TIM3)   || \
-                                                         ((INSTANCE) == TIM4)   || \
-                                                         ((INSTANCE) == TIM5))
-
-/**************** TIM Instances : external trigger input available ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)  || \
-                                            ((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM4)  || \
-                                            ((INSTANCE) == TIM5)  || \
-                                            ((INSTANCE) == TIM8))
-
-/************* TIM Instances : supporting ETR source selection ***************/
-#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
-                                             ((INSTANCE) == TIM2)  || \
-                                             ((INSTANCE) == TIM3)  || \
-                                             ((INSTANCE) == TIM8))
-      
-/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
-                                            ((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM4)  || \
-                                            ((INSTANCE) == TIM5)  || \
-                                            ((INSTANCE) == TIM6)  || \
-                                            ((INSTANCE) == TIM7)  || \
-                                            ((INSTANCE) == TIM8)  || \
-                                            ((INSTANCE) == TIM15))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
-                                            ((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM4)  || \
-                                            ((INSTANCE) == TIM5)  || \
-                                            ((INSTANCE) == TIM8)  || \
-                                            ((INSTANCE) == TIM15))
-
-/****************** TIM Instances : supporting OCxREF clear *******************/
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \
-                                                       ((INSTANCE) == TIM2) || \
-                                                       ((INSTANCE) == TIM3) || \
-                                                       ((INSTANCE) == TIM4) || \
-                                                       ((INSTANCE) == TIM5) || \
-                                                       ((INSTANCE) == TIM8))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
-                                            ((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM8)  || \
-                                            ((INSTANCE) == TIM15) || \
-                                            ((INSTANCE) == TIM16) || \
-                                            ((INSTANCE) == TIM17))
-
-/****************** TIM Instances : supporting repetition counter *************/
-#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
-                                                       ((INSTANCE) == TIM8)  || \
-                                                       ((INSTANCE) == TIM15) || \
-                                                       ((INSTANCE) == TIM16) || \
-                                                       ((INSTANCE) == TIM17))
-
-/****************** TIM Instances : supporting synchronization ****************/
-#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)  IS_TIM_MASTER_INSTANCE(INSTANCE)
-
-/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
-#define IS_TIM_TRGO2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
-                                            ((INSTANCE) == TIM8))
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
-                                            ((INSTANCE) == TIM2)   || \
-                                            ((INSTANCE) == TIM3)   || \
-                                            ((INSTANCE) == TIM4)   || \
-                                            ((INSTANCE) == TIM5)   || \
-                                            ((INSTANCE) == TIM8)   || \
-                                            ((INSTANCE) == TIM15))
-
-/****************************** TSC Instances *********************************/
-#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5))
-
-/****************** UART Instances : Auto Baud Rate detection ****************/
-#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                                            ((INSTANCE) == USART2) || \
-                                                            ((INSTANCE) == USART3) || \
-                                                            ((INSTANCE) == UART4)  || \
-                                                            ((INSTANCE) == UART5))
-
-/****************** UART Instances : Driver Enable *****************/
-#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)     (((INSTANCE) == USART1) || \
-                                                      ((INSTANCE) == USART2) || \
-                                                      ((INSTANCE) == USART3) || \
-                                                      ((INSTANCE) == UART4)  || \
-                                                      ((INSTANCE) == UART5)  || \
-                                                      ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == USART3) || \
-                                                 ((INSTANCE) == UART4)  || \
-                                                 ((INSTANCE) == UART5)  || \
-                                                 ((INSTANCE) == LPUART1))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3) || \
-                                           ((INSTANCE) == UART4)  || \
-                                           ((INSTANCE) == UART5)  || \
-                                           ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                          ((INSTANCE) == USART2) || \
-                                          ((INSTANCE) == USART3) || \
-                                          ((INSTANCE) == UART4)  || \
-                                          ((INSTANCE) == UART5))
-
-/******************** UART Instances : Wake-up from Stop mode **********************/
-#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                      ((INSTANCE) == USART2) || \
-                                                      ((INSTANCE) == USART3) || \
-                                                      ((INSTANCE) == UART4)  || \
-                                                      ((INSTANCE) == UART5)  || \
-                                                      ((INSTANCE) == LPUART1))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5))
-
-/********************* USART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3))
-
-/******************** LPUART Instance *****************************************/
-#define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/**
-  * @}
-  */
-
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L4xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L4 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-#define TIM8_IRQn                      TIM8_UP_IRQn
-
-/* Aliases for __IRQHandler */
-#define TIM8_IRQHandler                TIM8_UP_IRQHandler
-
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L476xx_H */
-
-/**
-  * @}
-  */
-
-  /**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/cmsis/stm32l4xx.h b/stmhal/cmsis/stm32l4xx.h
deleted file mode 100644
index 157df0ce79..0000000000
--- a/stmhal/cmsis/stm32l4xx.h
+++ /dev/null
@@ -1,207 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx.h
-  * @author  MCD Application Team
-  * @version V1.0.3
-  * @date    29-January-2016
-  * @brief   CMSIS STM32L4xx Device Peripheral Access Layer Header File.
-  *
-  *          The file is the unique include file that the application programmer
-  *          is using in the C source code, usually in main.c. This file contains:
-  *           - Configuration section that allows to select:
-  *              - The STM32L4xx device used in the target application
-  *              - To use or not the peripheral's drivers in application code(i.e.
-  *                code will be based on direct access to peripheral's registers
-  *                rather than drivers API), this option is controlled by
-  *                "#define USE_HAL_DRIVER"
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l4xx
-  * @{
-  */
-
-#ifndef __STM32L4xx_H
-#define __STM32L4xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-
-/** @addtogroup Library_configuration_section
-  * @{
-  */
-
-/**
-  * @brief STM32 Family
-  */
-#if !defined (STM32L4)
-#define STM32L4
-#endif /* STM32L4 */
-
-/* Uncomment the line below according to the target STM32L4 device used in your
-   application
-  */
-
-#if !defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx)
-  /* #define STM32L471xx */   /*!< STM32L471xx Devices */
-  /* #define STM32L475xx */   /*!< STM32L475xx Devices */
-  /* #define STM32L476xx */   /*!< STM32L476xx Devices */
-  /* #define STM32L485xx */   /*!< STM32L485xx Devices */
-  /* #define STM32L486xx */   /*!< STM32L486xx Devices */
-#endif
-
-/*  Tip: To avoid modifying this file each time you need to switch between these
-        devices, you can define the device in your toolchain compiler preprocessor.
-  */
-#if !defined  (USE_HAL_DRIVER)
-/**
- * @brief Comment the line below if you will not use the peripherals drivers.
-   In this case, these drivers will not be included and the application code will
-   be based on direct access to peripherals registers
-   */
-  /*#define USE_HAL_DRIVER */
-#endif /* USE_HAL_DRIVER */
-
-/**
-  * @brief CMSIS Device version number V1.0.3
-  */
-#define __STM32L4_CMSIS_VERSION_MAIN   (0x01) /*!< [31:24] main version */
-#define __STM32L4_CMSIS_VERSION_SUB1   (0x00) /*!< [23:16] sub1 version */
-#define __STM32L4_CMSIS_VERSION_SUB2   (0x03) /*!< [15:8]  sub2 version */
-#define __STM32L4_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
-#define __STM32L4_CMSIS_VERSION        ((__STM32L4_CMSIS_VERSION_MAIN << 24)\
-                                       |(__STM32L4_CMSIS_VERSION_SUB1 << 16)\
-                                       |(__STM32L4_CMSIS_VERSION_SUB2 << 8 )\
-                                       |(__STM32L4_CMSIS_VERSION_RC))
-
-/**
-  * @}
-  */
-
-/** @addtogroup Device_Included
-  * @{
-  */
-
-#if defined(STM32L471xx)
-  #include "stm32l471xx.h"
-#elif defined(STM32L475xx)
-  #include "stm32l475xx.h"
-#elif defined(STM32L476xx)
-  #include "stm32l476xx.h"
-#elif defined(STM32L485xx)
-  #include "stm32l485xx.h"
-#elif defined(STM32L486xx)
-  #include "stm32l486xx.h"
-#else
- #error "Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)"
-#endif
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_types
-  * @{
-  */
-typedef enum
-{
-  RESET = 0,
-  SET = !RESET
-} FlagStatus, ITStatus;
-
-typedef enum
-{
-  DISABLE = 0,
-  ENABLE = !DISABLE
-} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum
-{
-  ERROR = 0,
-  SUCCESS = !ERROR
-} ErrorStatus;
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
-
-#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
-
-#define READ_BIT(REG, BIT)    ((REG) & (BIT))
-
-#define CLEAR_REG(REG)        ((REG) = (0x0))
-
-#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
-
-#define READ_REG(REG)         ((REG))
-
-#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
-
-#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))
-
-
-/**
-  * @}
-  */
-
-#if defined (USE_HAL_DRIVER)
- #include "stm32l4xx_hal.h"
-#endif /* USE_HAL_DRIVER */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L4xx_H */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/cmsis/system_stm32f4xx.h b/stmhal/cmsis/system_stm32f4xx.h
deleted file mode 100644
index e82a996bd6..0000000000
--- a/stmhal/cmsis/system_stm32f4xx.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32f4xx.h
-  * @author  MCD Application Team
-  * @version V2.5.1
-  * @date    28-June-2016
-  * @brief   CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.       
-  ******************************************************************************  
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************  
-  */ 
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f4xx_system
-  * @{
-  */  
-  
-/**
-  * @brief Define to prevent recursive inclusion
-  */
-#ifndef __SYSTEM_STM32F4XX_H
-#define __SYSTEM_STM32F4XX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-/** @addtogroup STM32F4xx_System_Includes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup STM32F4xx_System_Exported_types
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F4xx_System_Exported_Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F4xx_System_Exported_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F4xx_System_Exported_Functions
-  * @{
-  */
-  
-extern void SystemInit(void);
-extern void SystemCoreClockUpdate(void);
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__SYSTEM_STM32F4XX_H */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */  
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/cmsis/system_stm32f7xx.h b/stmhal/cmsis/system_stm32f7xx.h
deleted file mode 100644
index 15419dfdef..0000000000
--- a/stmhal/cmsis/system_stm32f7xx.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32f7xx.h
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   CMSIS Cortex-M7 Device System Source File for STM32F7xx devices.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f7xx_system
-  * @{
-  */
-
-/**
-  * @brief Define to prevent recursive inclusion
-  */
-#ifndef __SYSTEM_STM32F7XX_H
-#define __SYSTEM_STM32F7XX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/** @addtogroup STM32F7xx_System_Includes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup STM32F7xx_System_Exported_Variables
-  * @{
-  */
-  /* The SystemCoreClock variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-    */
-extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
-
-extern const uint8_t  AHBPrescTable[16];    /*!< AHB prescalers table values */
-extern const uint8_t  APBPrescTable[8];     /*!< APB prescalers table values */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F7xx_System_Exported_Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F7xx_System_Exported_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F7xx_System_Exported_Functions
-  * @{
-  */
-
-extern void SystemInit(void);
-extern void SystemCoreClockUpdate(void);
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__SYSTEM_STM32F7XX_H */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/cmsis/system_stm32l4xx.h b/stmhal/cmsis/system_stm32l4xx.h
deleted file mode 100644
index aa56aebf72..0000000000
--- a/stmhal/cmsis/system_stm32l4xx.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32l4xx.h
-  * @author  MCD Application Team
-  * @version V1.0.3
-  * @date    29-January-2016
-  * @brief   CMSIS Cortex-M4 Device System Source File for STM32L4xx devices.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l4xx_system
-  * @{
-  */
-
-/**
-  * @brief Define to prevent recursive inclusion
-  */
-#ifndef __SYSTEM_STM32L4XX_H
-#define __SYSTEM_STM32L4XX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/** @addtogroup STM32L4xx_System_Includes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup STM32L4xx_System_Exported_Variables
-  * @{
-  */
-  /* The SystemCoreClock variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-extern uint32_t SystemCoreClock;            /*!< System Clock Frequency (Core Clock) */
-
-extern const uint8_t  AHBPrescTable[16];    /*!< AHB prescalers table values */
-extern const uint8_t  APBPrescTable[8];     /*!< APB prescalers table values */
-extern const uint32_t MSIRangeTable[12];    /*!< MSI ranges table values     */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L4xx_System_Exported_Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L4xx_System_Exported_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L4xx_System_Exported_Functions
-  * @{
-  */
-
-extern void SystemInit(void);
-extern void SystemCoreClockUpdate(void);
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__SYSTEM_STM32L4XX_H */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/HALCOMMITS b/stmhal/hal/HALCOMMITS
deleted file mode 100644
index 6d541d2c83..0000000000
--- a/stmhal/hal/HALCOMMITS
+++ /dev/null
@@ -1,110 +0,0 @@
-This is a list of all commits that relate to the ST Cube HAL, including
-additions, modifications and deletions.  Any commit which touches the HAL
-should be separate from any other changes and should be listed here, most
-recent commit at the top of the list.  This makes it easier to upgrade to
-a new HAL version.
-
-44cb2ff7ab99edf91c95b9ef3d9fe3e119d71cf8
-stmhal: Port of f4 hal commit 1d7fb82 to updated f7 hal.
-
-821863751f942f54c140f80d5a92ad7046112331
-stmhal: Port of f4 hal commit 09de030 to updated f7 hal.
-
-e1c6ed634f4387a6c9d7e132ed7d0bb245a9618a
-stmhal: Port of f4 hal commit c568a2b to updated f7 hal.
-
-b9741cd8f84a2f49e3ea00382bfa71d994bc83ff
-stmhal/hal: Update ST32CubeF7 HAL files to V1.1.2.
-
-13400e13758f7e23fc17bae753030723046ba3aa
-stmhal/hal: do not include <stdio.h> in HAL headers
-
-63ca7a211ac832fb885753ad837a7b3de2aaa5da
-stmhal/dma: precalculate register base and bitshift on handle init
-
-6a8f6c119c249e52fbc4d4fd55b2bec65544c811
-stmhal/hal/sd: reapply HAL commit 09de030 for f4
-
-e2b48221892ca5445d9e255753e4ccfcd07a8171
-stmhal/hal/rcc: reapply HAL commit c568a2b for f4
-
-4f7c5fa64769f836b1cb3d357be4864807e10694
-stmhal/hal: reapply HAL commit 9db719b for f4
-
-c79ff9930aed2a91a888f8eb58f27946ca8287ca
-stmhal/hal/sd: reapply HAL commit 1d7fb82 for f4
-
-a9fb88e1dcc95e9c2a788549bca0bede6b2ee02c
-stmhal/hal/i2c: reapply HAL commit ea040a4 for f4
-
-e8b435d1f80a220a4f561b1e653ea33b69517513
-stmhal: apply STM32CubeF4 v1.13.1 patch - upgrade HAL driver to v1.5.2
-
-c1fa33b493db3f861c322c84da56aed0c1599339
-stmhal: upgrade to STM32CubeF4 v1.13.0 - HAL v1.5.1
-
-4f5c4fdd98c22991f79b4e58e5add28ad9f9c6c4
-stmhal: upgrade to STM32CubeF4 v1.13.0 - CMSIS/Device 2.5.1
-
-daa279a3a1b38bc7a8218e2c6186e63483c7cfc3
-stmhal: Port of f4 hal commit 1d7fb82 to l4 hal
-
-d4c33499579eb8f4febec2f5f01f5021f719fdaf
-stmhal: L4: Adapt UART HAL to avoid 64-bit integer division.
-
-f4942db044e9f614a9fc7254bb72b3441a2362a2
-stmhal: L4: Add basic STM32L4xx HAL files.
-
-2ba6677775b8704723435dc07e7b619f4c85c43d
-stmhal: L4: Add CMSIS files to support STM32L476.
-
-ea040a4f9ace1c50abc22ab755415305fd2bda41
-stmhal: In HAL I2C driver, move DMA setup to after sending I2C address.
-
-7a55c1a88473d36d4a907c1a2e33967a6c38d157
-stmhal: Port of f4 hal commit 1d7fb82 to f7 hal
-
-28e51c9eb1f633bb4f0a17e964ef7791d54c913d
-stmhal: Port of f4 hal commit 09de030 to f7 hal
-
-af9d885f8cbbe454a8bf655a08c33c775c4838dd
-stmhal: Port of f4 hal commit c568a2b to f7 hal
-
-f243851ccdbb686508f37a573e3ba46da5fffa0c
-stmhal: Expose uwTick in f7 hal.
-
-7c934ae5019d285b58cec3d1edcbc44d90fa6295
-stmhal: Add hal and cmsis files from STM32Cube_FW_F7_V1.1.0.
-
-99a21dc05d7c7e42131264259f287c84afe86200
-stmhal: Add stm32fxxx_hal_i2s_ex.c to hal/f2 (dummy) and hal/f4.
-
-0621eca05ecaf012d0e69bebb0f0fc90719ce9e5
-stmhal: Add STM32CubeF2 version 1.1.0, in hal/f2 directory.
-
-e4d43401eb098d3bfb4e9074e15b67fd86aaffe3
-stmhal: Move HAL Cube files to f4/ subdir, keeping only those we use.
-
-c568a2b44387bee14ea5f427a6e9b736eb1b5345
-stmhal: Adjust computation of SYSCLK to retain precision.
-
-1d7fb82f0aec11331635532583617d773888b991
-stmhal: Change 64-bit arithmetic to 32-bit for SD card block addressing.
-
-09de030651b95956eb9f899e850f24d0ce804460
-stmhal/hal/src/stm32f4xx_hal_sd.c: fix SDHC card capacity
-
-34e43c7ee9700249dc6e5b333b7c264d45d6b530
-stmhal: Improve efficiency of SysTick IRQ and HAL_Delay.
-     
-3ef911345c94a6d612ab50c1e912e81cb2cc3f71
-stmhal: Update STM32Cube F4 HAL driver to V1.3.0.
-
-d689430e790bfbd40a4fc3139b118aee5576baf7
-stmhal: Add SPI class.
-
-9db719bb57626d72ab84ab0ccd2294bf89158762
-stmhal - More systick cleanup. Fix HAL_Delay
-
-dd38d907244bc0e483c3d760f2ba464a394ec229
-Initial checkin with STM HAL
diff --git a/stmhal/hal/f4/inc/Legacy/stm32_hal_legacy.h b/stmhal/hal/f4/inc/Legacy/stm32_hal_legacy.h
deleted file mode 100644
index 7df278ad4a..0000000000
--- a/stmhal/hal/f4/inc/Legacy/stm32_hal_legacy.h
+++ /dev/null
@@ -1,3123 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32_hal_legacy.h
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   This file contains aliases definition for the STM32Cube HAL constants 
-  *          macros and functions maintained for legacy purpose.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32_HAL_LEGACY
-#define __STM32_HAL_LEGACY
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define AES_FLAG_RDERR                  CRYP_FLAG_RDERR
-#define AES_FLAG_WRERR                  CRYP_FLAG_WRERR
-#define AES_CLEARFLAG_CCF               CRYP_CLEARFLAG_CCF
-#define AES_CLEARFLAG_RDERR             CRYP_CLEARFLAG_RDERR
-#define AES_CLEARFLAG_WRERR             CRYP_CLEARFLAG_WRERR
-
-/**
-  * @}
-  */
-  
-/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define ADC_RESOLUTION12b               ADC_RESOLUTION_12B
-#define ADC_RESOLUTION10b               ADC_RESOLUTION_10B
-#define ADC_RESOLUTION8b                ADC_RESOLUTION_8B
-#define ADC_RESOLUTION6b                ADC_RESOLUTION_6B
-#define OVR_DATA_OVERWRITTEN            ADC_OVR_DATA_OVERWRITTEN
-#define OVR_DATA_PRESERVED              ADC_OVR_DATA_PRESERVED
-#define EOC_SINGLE_CONV                 ADC_EOC_SINGLE_CONV
-#define EOC_SEQ_CONV                    ADC_EOC_SEQ_CONV
-#define EOC_SINGLE_SEQ_CONV             ADC_EOC_SINGLE_SEQ_CONV
-#define REGULAR_GROUP                   ADC_REGULAR_GROUP
-#define INJECTED_GROUP                  ADC_INJECTED_GROUP
-#define REGULAR_INJECTED_GROUP          ADC_REGULAR_INJECTED_GROUP
-#define AWD_EVENT                       ADC_AWD_EVENT
-#define AWD1_EVENT                      ADC_AWD1_EVENT
-#define AWD2_EVENT                      ADC_AWD2_EVENT
-#define AWD3_EVENT                      ADC_AWD3_EVENT
-#define OVR_EVENT                       ADC_OVR_EVENT
-#define JQOVF_EVENT                     ADC_JQOVF_EVENT
-#define ALL_CHANNELS                    ADC_ALL_CHANNELS
-#define REGULAR_CHANNELS                ADC_REGULAR_CHANNELS
-#define INJECTED_CHANNELS               ADC_INJECTED_CHANNELS
-#define SYSCFG_FLAG_SENSOR_ADC          ADC_FLAG_SENSOR
-#define SYSCFG_FLAG_VREF_ADC            ADC_FLAG_VREFINT
-#define ADC_CLOCKPRESCALER_PCLK_DIV1    ADC_CLOCK_SYNC_PCLK_DIV1
-#define ADC_CLOCKPRESCALER_PCLK_DIV2    ADC_CLOCK_SYNC_PCLK_DIV2
-#define ADC_CLOCKPRESCALER_PCLK_DIV4    ADC_CLOCK_SYNC_PCLK_DIV4
-#define ADC_CLOCKPRESCALER_PCLK_DIV6    ADC_CLOCK_SYNC_PCLK_DIV6
-#define ADC_CLOCKPRESCALER_PCLK_DIV8    ADC_CLOCK_SYNC_PCLK_DIV8
-#define ADC_EXTERNALTRIG0_T6_TRGO       ADC_EXTERNALTRIGCONV_T6_TRGO 
-#define ADC_EXTERNALTRIG1_T21_CC2       ADC_EXTERNALTRIGCONV_T21_CC2 
-#define ADC_EXTERNALTRIG2_T2_TRGO       ADC_EXTERNALTRIGCONV_T2_TRGO 
-#define ADC_EXTERNALTRIG3_T2_CC4        ADC_EXTERNALTRIGCONV_T2_CC4  
-#define ADC_EXTERNALTRIG4_T22_TRGO      ADC_EXTERNALTRIGCONV_T22_TRGO
-#define ADC_EXTERNALTRIG7_EXT_IT11      ADC_EXTERNALTRIGCONV_EXT_IT11
-#define ADC_CLOCK_ASYNC                 ADC_CLOCK_ASYNC_DIV1
-#define ADC_EXTERNALTRIG_EDGE_NONE      ADC_EXTERNALTRIGCONVEDGE_NONE
-#define ADC_EXTERNALTRIG_EDGE_RISING    ADC_EXTERNALTRIGCONVEDGE_RISING
-#define ADC_EXTERNALTRIG_EDGE_FALLING   ADC_EXTERNALTRIGCONVEDGE_FALLING
-#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
-#define ADC_SAMPLETIME_2CYCLE_5         ADC_SAMPLETIME_2CYCLES_5
-
-#define HAL_ADC_STATE_BUSY_REG          HAL_ADC_STATE_REG_BUSY
-#define HAL_ADC_STATE_BUSY_INJ          HAL_ADC_STATE_INJ_BUSY
-#define HAL_ADC_STATE_EOC_REG           HAL_ADC_STATE_REG_EOC
-#define HAL_ADC_STATE_EOC_INJ           HAL_ADC_STATE_INJ_EOC
-#define HAL_ADC_STATE_ERROR             HAL_ADC_STATE_ERROR_INTERNAL
-#define HAL_ADC_STATE_BUSY              HAL_ADC_STATE_BUSY_INTERNAL
-#define HAL_ADC_STATE_AWD               HAL_ADC_STATE_AWD1 
-/**
-  * @}
-  */
-  
-/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
-  * @{
-  */ 
-  
-#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG 
-
-/**
-  * @}
-  */   
-   
-/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define COMP_WINDOWMODE_DISABLED       COMP_WINDOWMODE_DISABLE
-#define COMP_WINDOWMODE_ENABLED        COMP_WINDOWMODE_ENABLE
-#define COMP_EXTI_LINE_COMP1_EVENT     COMP_EXTI_LINE_COMP1
-#define COMP_EXTI_LINE_COMP2_EVENT     COMP_EXTI_LINE_COMP2
-#define COMP_EXTI_LINE_COMP3_EVENT     COMP_EXTI_LINE_COMP3
-#define COMP_EXTI_LINE_COMP4_EVENT     COMP_EXTI_LINE_COMP4
-#define COMP_EXTI_LINE_COMP5_EVENT     COMP_EXTI_LINE_COMP5
-#define COMP_EXTI_LINE_COMP6_EVENT     COMP_EXTI_LINE_COMP6
-#define COMP_EXTI_LINE_COMP7_EVENT     COMP_EXTI_LINE_COMP7
-#define COMP_OUTPUT_COMP6TIM2OCREFCLR  COMP_OUTPUT_COMP6_TIM2OCREFCLR
-#if defined(STM32F373xC) || defined(STM32F378xx)
-#define COMP_OUTPUT_TIM3IC1            COMP_OUTPUT_COMP1_TIM3IC1
-#define COMP_OUTPUT_TIM3OCREFCLR       COMP_OUTPUT_COMP1_TIM3OCREFCLR
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32L0) || defined(STM32L4)
-#define COMP_WINDOWMODE_ENABLE         COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
-
-#define COMP_NONINVERTINGINPUT_IO1      COMP_INPUT_PLUS_IO1
-#define COMP_NONINVERTINGINPUT_IO2      COMP_INPUT_PLUS_IO2
-#define COMP_NONINVERTINGINPUT_IO3      COMP_INPUT_PLUS_IO3
- 
-#define COMP_INVERTINGINPUT_1_4VREFINT  COMP_INPUT_MINUS_1_4VREFINT
-#define COMP_INVERTINGINPUT_1_2VREFINT  COMP_INPUT_MINUS_1_2VREFINT
-#define COMP_INVERTINGINPUT_3_4VREFINT  COMP_INPUT_MINUS_3_4VREFINT
-#define COMP_INVERTINGINPUT_VREFINT     COMP_INPUT_MINUS_VREFINT
-#define COMP_INVERTINGINPUT_DAC1_CH1    COMP_INPUT_MINUS_DAC1_CH1
-#define COMP_INVERTINGINPUT_DAC1_CH2    COMP_INPUT_MINUS_DAC1_CH2
-#define COMP_INVERTINGINPUT_DAC1        COMP_INPUT_MINUS_DAC1_CH1
-#define COMP_INVERTINGINPUT_DAC2        COMP_INPUT_MINUS_DAC1_CH2
-#define COMP_INVERTINGINPUT_IO1         COMP_INPUT_MINUS_IO1
-#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_IO2
-#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO3
-#define COMP_INVERTINGINPUT_IO4         COMP_INPUT_MINUS_IO4
-#define COMP_INVERTINGINPUT_IO5         COMP_INPUT_MINUS_IO5
-
-#define COMP_OUTPUTLEVEL_LOW            COMP_OUTPUT_LEVEL_LOW
-#define COMP_OUTPUTLEVEL_HIGH           COMP_OUTPUT_LEVEL_HIGH
-
-/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose.                    */
-/*       To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()".        */
-#if defined(COMP_CSR_LOCK)
-#define COMP_FLAG_LOCK                 COMP_CSR_LOCK
-#elif defined(COMP_CSR_COMP1LOCK)
-#define COMP_FLAG_LOCK                 COMP_CSR_COMP1LOCK
-#elif defined(COMP_CSR_COMPxLOCK)
-#define COMP_FLAG_LOCK                 COMP_CSR_COMPxLOCK
-#endif
-
-#if defined(STM32L4)
-#define COMP_BLANKINGSRCE_TIM1OC5        COMP_BLANKINGSRC_TIM1_OC5_COMP1
-#define COMP_BLANKINGSRCE_TIM2OC3        COMP_BLANKINGSRC_TIM2_OC3_COMP1
-#define COMP_BLANKINGSRCE_TIM3OC3        COMP_BLANKINGSRC_TIM3_OC3_COMP1
-#define COMP_BLANKINGSRCE_TIM3OC4        COMP_BLANKINGSRC_TIM3_OC4_COMP2
-#define COMP_BLANKINGSRCE_TIM8OC5        COMP_BLANKINGSRC_TIM8_OC5_COMP2
-#define COMP_BLANKINGSRCE_TIM15OC1       COMP_BLANKINGSRC_TIM15_OC1_COMP2
-#define COMP_BLANKINGSRCE_NONE           COMP_BLANKINGSRC_NONE
-#endif
-
-#if defined(STM32L0)
-#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_MEDIUMSPEED
-#define COMP_MODE_LOWSPEED               COMP_POWERMODE_ULTRALOWPOWER
-#else
-#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_HIGHSPEED
-#define COMP_MODE_MEDIUMSPEED            COMP_POWERMODE_MEDIUMSPEED
-#define COMP_MODE_LOWPOWER               COMP_POWERMODE_LOWPOWER
-#define COMP_MODE_ULTRALOWPOWER          COMP_POWERMODE_ULTRALOWPOWER
-#endif
-
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
-/**
-  * @}
-  */
-
-/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-  
-#define CRC_OUTPUTDATA_INVERSION_DISABLED    CRC_OUTPUTDATA_INVERSION_DISABLE
-#define CRC_OUTPUTDATA_INVERSION_ENABLED     CRC_OUTPUTDATA_INVERSION_ENABLE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define DAC1_CHANNEL_1                                  DAC_CHANNEL_1
-#define DAC1_CHANNEL_2                                  DAC_CHANNEL_2
-#define DAC2_CHANNEL_1                                  DAC_CHANNEL_1
-#define DAC_WAVE_NONE                                   ((uint32_t)0x00000000U)
-#define DAC_WAVE_NOISE                                  ((uint32_t)DAC_CR_WAVE1_0)
-#define DAC_WAVE_TRIANGLE                               ((uint32_t)DAC_CR_WAVE1_1)                           
-#define DAC_WAVEGENERATION_NONE                         DAC_WAVE_NONE
-#define DAC_WAVEGENERATION_NOISE                        DAC_WAVE_NOISE
-#define DAC_WAVEGENERATION_TRIANGLE                     DAC_WAVE_TRIANGLE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define HAL_REMAPDMA_ADC_DMA_CH2                DMA_REMAP_ADC_DMA_CH2       
-#define HAL_REMAPDMA_USART1_TX_DMA_CH4          DMA_REMAP_USART1_TX_DMA_CH4 
-#define HAL_REMAPDMA_USART1_RX_DMA_CH5          DMA_REMAP_USART1_RX_DMA_CH5   
-#define HAL_REMAPDMA_TIM16_DMA_CH4              DMA_REMAP_TIM16_DMA_CH4       
-#define HAL_REMAPDMA_TIM17_DMA_CH2              DMA_REMAP_TIM17_DMA_CH2       
-#define HAL_REMAPDMA_USART3_DMA_CH32            DMA_REMAP_USART3_DMA_CH32
-#define HAL_REMAPDMA_TIM16_DMA_CH6              DMA_REMAP_TIM16_DMA_CH6
-#define HAL_REMAPDMA_TIM17_DMA_CH7              DMA_REMAP_TIM17_DMA_CH7      
-#define HAL_REMAPDMA_SPI2_DMA_CH67              DMA_REMAP_SPI2_DMA_CH67  
-#define HAL_REMAPDMA_USART2_DMA_CH67            DMA_REMAP_USART2_DMA_CH67 
-#define HAL_REMAPDMA_USART3_DMA_CH32            DMA_REMAP_USART3_DMA_CH32  
-#define HAL_REMAPDMA_I2C1_DMA_CH76              DMA_REMAP_I2C1_DMA_CH76   
-#define HAL_REMAPDMA_TIM1_DMA_CH6               DMA_REMAP_TIM1_DMA_CH6     
-#define HAL_REMAPDMA_TIM2_DMA_CH7               DMA_REMAP_TIM2_DMA_CH7      
-#define HAL_REMAPDMA_TIM3_DMA_CH6               DMA_REMAP_TIM3_DMA_CH6    
-  
-#define IS_HAL_REMAPDMA                          IS_DMA_REMAP  
-#define __HAL_REMAPDMA_CHANNEL_ENABLE            __HAL_DMA_REMAP_CHANNEL_ENABLE
-#define __HAL_REMAPDMA_CHANNEL_DISABLE           __HAL_DMA_REMAP_CHANNEL_DISABLE
-  
-  
-  
-/**
-  * @}
-  */
-
-/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
-  * @{
-  */
-  
-#define TYPEPROGRAM_BYTE              FLASH_TYPEPROGRAM_BYTE
-#define TYPEPROGRAM_HALFWORD          FLASH_TYPEPROGRAM_HALFWORD
-#define TYPEPROGRAM_WORD              FLASH_TYPEPROGRAM_WORD
-#define TYPEPROGRAM_DOUBLEWORD        FLASH_TYPEPROGRAM_DOUBLEWORD
-#define TYPEERASE_SECTORS             FLASH_TYPEERASE_SECTORS
-#define TYPEERASE_PAGES               FLASH_TYPEERASE_PAGES
-#define TYPEERASE_PAGEERASE           FLASH_TYPEERASE_PAGES
-#define TYPEERASE_MASSERASE           FLASH_TYPEERASE_MASSERASE
-#define WRPSTATE_DISABLE              OB_WRPSTATE_DISABLE
-#define WRPSTATE_ENABLE               OB_WRPSTATE_ENABLE
-#define HAL_FLASH_TIMEOUT_VALUE       FLASH_TIMEOUT_VALUE
-#define OBEX_PCROP                    OPTIONBYTE_PCROP
-#define OBEX_BOOTCONFIG               OPTIONBYTE_BOOTCONFIG
-#define PCROPSTATE_DISABLE            OB_PCROP_STATE_DISABLE
-#define PCROPSTATE_ENABLE             OB_PCROP_STATE_ENABLE
-#define TYPEERASEDATA_BYTE            FLASH_TYPEERASEDATA_BYTE
-#define TYPEERASEDATA_HALFWORD        FLASH_TYPEERASEDATA_HALFWORD
-#define TYPEERASEDATA_WORD            FLASH_TYPEERASEDATA_WORD
-#define TYPEPROGRAMDATA_BYTE          FLASH_TYPEPROGRAMDATA_BYTE
-#define TYPEPROGRAMDATA_HALFWORD      FLASH_TYPEPROGRAMDATA_HALFWORD
-#define TYPEPROGRAMDATA_WORD          FLASH_TYPEPROGRAMDATA_WORD
-#define TYPEPROGRAMDATA_FASTBYTE      FLASH_TYPEPROGRAMDATA_FASTBYTE
-#define TYPEPROGRAMDATA_FASTHALFWORD  FLASH_TYPEPROGRAMDATA_FASTHALFWORD
-#define TYPEPROGRAMDATA_FASTWORD      FLASH_TYPEPROGRAMDATA_FASTWORD
-#define PAGESIZE                      FLASH_PAGE_SIZE
-#define TYPEPROGRAM_FASTBYTE          FLASH_TYPEPROGRAM_BYTE
-#define TYPEPROGRAM_FASTHALFWORD      FLASH_TYPEPROGRAM_HALFWORD
-#define TYPEPROGRAM_FASTWORD          FLASH_TYPEPROGRAM_WORD
-#define VOLTAGE_RANGE_1               FLASH_VOLTAGE_RANGE_1
-#define VOLTAGE_RANGE_2               FLASH_VOLTAGE_RANGE_2
-#define VOLTAGE_RANGE_3               FLASH_VOLTAGE_RANGE_3
-#define VOLTAGE_RANGE_4               FLASH_VOLTAGE_RANGE_4
-#define TYPEPROGRAM_FAST              FLASH_TYPEPROGRAM_FAST
-#define TYPEPROGRAM_FAST_AND_LAST     FLASH_TYPEPROGRAM_FAST_AND_LAST
-#define WRPAREA_BANK1_AREAA           OB_WRPAREA_BANK1_AREAA
-#define WRPAREA_BANK1_AREAB           OB_WRPAREA_BANK1_AREAB
-#define WRPAREA_BANK2_AREAA           OB_WRPAREA_BANK2_AREAA
-#define WRPAREA_BANK2_AREAB           OB_WRPAREA_BANK2_AREAB
-#define IWDG_STDBY_FREEZE             OB_IWDG_STDBY_FREEZE
-#define IWDG_STDBY_ACTIVE             OB_IWDG_STDBY_RUN
-#define IWDG_STOP_FREEZE              OB_IWDG_STOP_FREEZE
-#define IWDG_STOP_ACTIVE              OB_IWDG_STOP_RUN
-#define FLASH_ERROR_NONE              HAL_FLASH_ERROR_NONE
-#define FLASH_ERROR_RD                HAL_FLASH_ERROR_RD
-#define FLASH_ERROR_PG                HAL_FLASH_ERROR_PROG
-#define FLASH_ERROR_PGP               HAL_FLASH_ERROR_PGS
-#define FLASH_ERROR_WRP               HAL_FLASH_ERROR_WRP
-#define FLASH_ERROR_OPTV              HAL_FLASH_ERROR_OPTV
-#define FLASH_ERROR_OPTVUSR           HAL_FLASH_ERROR_OPTVUSR
-#define FLASH_ERROR_PROG              HAL_FLASH_ERROR_PROG
-#define FLASH_ERROR_OP                HAL_FLASH_ERROR_OPERATION
-#define FLASH_ERROR_PGA               HAL_FLASH_ERROR_PGA
-#define FLASH_ERROR_SIZE              HAL_FLASH_ERROR_SIZE
-#define FLASH_ERROR_SIZ               HAL_FLASH_ERROR_SIZE
-#define FLASH_ERROR_PGS               HAL_FLASH_ERROR_PGS
-#define FLASH_ERROR_MIS               HAL_FLASH_ERROR_MIS
-#define FLASH_ERROR_FAST              HAL_FLASH_ERROR_FAST
-#define FLASH_ERROR_FWWERR            HAL_FLASH_ERROR_FWWERR
-#define FLASH_ERROR_NOTZERO           HAL_FLASH_ERROR_NOTZERO
-#define FLASH_ERROR_OPERATION         HAL_FLASH_ERROR_OPERATION
-#define FLASH_ERROR_ERS               HAL_FLASH_ERROR_ERS
-#define OB_WDG_SW                     OB_IWDG_SW
-#define OB_WDG_HW                     OB_IWDG_HW
-#define OB_SDADC12_VDD_MONITOR_SET    OB_SDACD_VDD_MONITOR_SET
-#define OB_SDADC12_VDD_MONITOR_RESET  OB_SDACD_VDD_MONITOR_RESET
-#define OB_RAM_PARITY_CHECK_SET       OB_SRAM_PARITY_SET
-#define OB_RAM_PARITY_CHECK_RESET     OB_SRAM_PARITY_RESET
-#define IS_OB_SDADC12_VDD_MONITOR     IS_OB_SDACD_VDD_MONITOR
-#define OB_RDP_LEVEL0                 OB_RDP_LEVEL_0
-#define OB_RDP_LEVEL1                 OB_RDP_LEVEL_1
-#define OB_RDP_LEVEL2                 OB_RDP_LEVEL_2
-/**
-  * @}
-  */
-  
-/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
-  * @{
-  */
-  
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9    I2C_FASTMODEPLUS_PA9
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10   I2C_FASTMODEPLUS_PA10
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6    I2C_FASTMODEPLUS_PB6
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7    I2C_FASTMODEPLUS_PB7
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8    I2C_FASTMODEPLUS_PB8
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9    I2C_FASTMODEPLUS_PB9
-#define HAL_SYSCFG_FASTMODEPLUS_I2C1       I2C_FASTMODEPLUS_I2C1
-#define HAL_SYSCFG_FASTMODEPLUS_I2C2       I2C_FASTMODEPLUS_I2C2
-#define HAL_SYSCFG_FASTMODEPLUS_I2C3       I2C_FASTMODEPLUS_I2C3
-/**
-  * @}
-  */
-  
-
-/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
-  * @{
-  */
-#if defined(STM32L4) || defined(STM32F7)
-#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE       FMC_NAND_WAIT_FEATURE_DISABLE
-#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE        FMC_NAND_WAIT_FEATURE_ENABLE
-#define FMC_NAND_PCC_MEM_BUS_WIDTH_8            FMC_NAND_MEM_BUS_WIDTH_8
-#define FMC_NAND_PCC_MEM_BUS_WIDTH_16           FMC_NAND_MEM_BUS_WIDTH_16
-#else
-#define FMC_NAND_WAIT_FEATURE_DISABLE           FMC_NAND_PCC_WAIT_FEATURE_DISABLE
-#define FMC_NAND_WAIT_FEATURE_ENABLE            FMC_NAND_PCC_WAIT_FEATURE_ENABLE
-#define FMC_NAND_MEM_BUS_WIDTH_8                FMC_NAND_PCC_MEM_BUS_WIDTH_8
-#define FMC_NAND_MEM_BUS_WIDTH_16               FMC_NAND_PCC_MEM_BUS_WIDTH_16
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-  
-#define FSMC_NORSRAM_TYPEDEF                      FSMC_NORSRAM_TypeDef
-#define FSMC_NORSRAM_EXTENDED_TYPEDEF             FSMC_NORSRAM_EXTENDED_TypeDef
-/**
-  * @}
-  */
-
-/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define GET_GPIO_SOURCE                           GPIO_GET_INDEX
-#define GET_GPIO_INDEX                            GPIO_GET_INDEX
-
-#if defined(STM32F4)
-#define GPIO_AF12_SDMMC                           GPIO_AF12_SDIO
-#define GPIO_AF12_SDMMC1                          GPIO_AF12_SDIO
-#endif
-
-#if defined(STM32F7)
-#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1
-#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
-#endif
-
-#if defined(STM32L4)
-#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1
-#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
-#endif
-
-#define GPIO_AF0_LPTIM                            GPIO_AF0_LPTIM1
-#define GPIO_AF1_LPTIM                            GPIO_AF1_LPTIM1
-#define GPIO_AF2_LPTIM                            GPIO_AF2_LPTIM1
-
-#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7)
-#define  GPIO_SPEED_LOW                           GPIO_SPEED_FREQ_LOW     
-#define  GPIO_SPEED_MEDIUM                        GPIO_SPEED_FREQ_MEDIUM     
-#define  GPIO_SPEED_FAST                          GPIO_SPEED_FREQ_HIGH     
-#define  GPIO_SPEED_HIGH                          GPIO_SPEED_FREQ_VERY_HIGH       
-#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */
-
-#if defined(STM32L1) 
- #define  GPIO_SPEED_VERY_LOW    GPIO_SPEED_FREQ_LOW     
- #define  GPIO_SPEED_LOW         GPIO_SPEED_FREQ_MEDIUM     
- #define  GPIO_SPEED_MEDIUM      GPIO_SPEED_FREQ_HIGH     
- #define  GPIO_SPEED_HIGH        GPIO_SPEED_FREQ_VERY_HIGH     
-#endif /* STM32L1 */
-
-#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
- #define  GPIO_SPEED_LOW    GPIO_SPEED_FREQ_LOW
- #define  GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
- #define  GPIO_SPEED_HIGH   GPIO_SPEED_FREQ_HIGH
-#endif /* STM32F0 || STM32F3 || STM32F1 */
-
-#define GPIO_AF6_DFSDM                            GPIO_AF6_DFSDM1
-/**
-  * @}
-  */
-
-/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define HRTIM_TIMDELAYEDPROTECTION_DISABLED           HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
-#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
-   
-#define __HAL_HRTIM_SetCounter        __HAL_HRTIM_SETCOUNTER
-#define __HAL_HRTIM_GetCounter        __HAL_HRTIM_GETCOUNTER
-#define __HAL_HRTIM_SetPeriod         __HAL_HRTIM_SETPERIOD
-#define __HAL_HRTIM_GetPeriod         __HAL_HRTIM_GETPERIOD
-#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
-#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
-#define __HAL_HRTIM_SetCompare        __HAL_HRTIM_SETCOMPARE
-#define __HAL_HRTIM_GetCompare        __HAL_HRTIM_GETCOMPARE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define I2C_DUALADDRESS_DISABLED                I2C_DUALADDRESS_DISABLE
-#define I2C_DUALADDRESS_ENABLED                 I2C_DUALADDRESS_ENABLE
-#define I2C_GENERALCALL_DISABLED                I2C_GENERALCALL_DISABLE
-#define I2C_GENERALCALL_ENABLED                 I2C_GENERALCALL_ENABLE
-#define I2C_NOSTRETCH_DISABLED                  I2C_NOSTRETCH_DISABLE
-#define I2C_NOSTRETCH_ENABLED                   I2C_NOSTRETCH_ENABLE
-#define I2C_ANALOGFILTER_ENABLED                I2C_ANALOGFILTER_ENABLE
-#define I2C_ANALOGFILTER_DISABLED               I2C_ANALOGFILTER_DISABLE
-#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
-#define HAL_I2C_STATE_MEM_BUSY_TX               HAL_I2C_STATE_BUSY_TX
-#define HAL_I2C_STATE_MEM_BUSY_RX               HAL_I2C_STATE_BUSY_RX
-#define HAL_I2C_STATE_MASTER_BUSY_TX            HAL_I2C_STATE_BUSY_TX
-#define HAL_I2C_STATE_MASTER_BUSY_RX            HAL_I2C_STATE_BUSY_RX
-#define HAL_I2C_STATE_SLAVE_BUSY_TX             HAL_I2C_STATE_BUSY_TX
-#define HAL_I2C_STATE_SLAVE_BUSY_RX             HAL_I2C_STATE_BUSY_RX
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define IRDA_ONE_BIT_SAMPLE_DISABLED            IRDA_ONE_BIT_SAMPLE_DISABLE
-#define IRDA_ONE_BIT_SAMPLE_ENABLED             IRDA_ONE_BIT_SAMPLE_ENABLE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define KR_KEY_RELOAD                   IWDG_KEY_RELOAD
-#define KR_KEY_ENABLE                   IWDG_KEY_ENABLE
-#define KR_KEY_EWA                      IWDG_KEY_WRITE_ACCESS_ENABLE
-#define KR_KEY_DWA                      IWDG_KEY_WRITE_ACCESS_DISABLE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
-#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
-#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
-#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
-
-#define LPTIM_CLOCKPOLARITY_RISINGEDGE          LPTIM_CLOCKPOLARITY_RISING
-#define LPTIM_CLOCKPOLARITY_FALLINGEDGE         LPTIM_CLOCKPOLARITY_FALLING
-#define LPTIM_CLOCKPOLARITY_BOTHEDGES           LPTIM_CLOCKPOLARITY_RISING_FALLING
-
-#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION  LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
-#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS      LPTIM_TRIGSAMPLETIME_2TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS      LPTIM_TRIGSAMPLETIME_4TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS      LPTIM_TRIGSAMPLETIME_8TRANSITIONS        
-
-/* The following 3 definition have also been present in a temporary version of lptim.h */
-/* They need to be renamed also to the right name, just in case */
-#define LPTIM_TRIGSAMPLETIME_2TRANSITION        LPTIM_TRIGSAMPLETIME_2TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_4TRANSITION        LPTIM_TRIGSAMPLETIME_4TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_8TRANSITION        LPTIM_TRIGSAMPLETIME_8TRANSITIONS
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define HAL_NAND_Read_Page              HAL_NAND_Read_Page_8b
-#define HAL_NAND_Write_Page             HAL_NAND_Write_Page_8b
-#define HAL_NAND_Read_SpareArea         HAL_NAND_Read_SpareArea_8b
-#define HAL_NAND_Write_SpareArea        HAL_NAND_Write_SpareArea_8b
-
-#define NAND_AddressTypedef             NAND_AddressTypeDef
-
-#define __ARRAY_ADDRESS                 ARRAY_ADDRESS
-#define __ADDR_1st_CYCLE                ADDR_1ST_CYCLE
-#define __ADDR_2nd_CYCLE                ADDR_2ND_CYCLE
-#define __ADDR_3rd_CYCLE                ADDR_3RD_CYCLE
-#define __ADDR_4th_CYCLE                ADDR_4TH_CYCLE
-/**
-  * @}
-  */
-   
-/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define NOR_StatusTypedef              HAL_NOR_StatusTypeDef
-#define NOR_SUCCESS                    HAL_NOR_STATUS_SUCCESS
-#define NOR_ONGOING                    HAL_NOR_STATUS_ONGOING
-#define NOR_ERROR                      HAL_NOR_STATUS_ERROR
-#define NOR_TIMEOUT                    HAL_NOR_STATUS_TIMEOUT
-
-#define __NOR_WRITE                    NOR_WRITE
-#define __NOR_ADDR_SHIFT               NOR_ADDR_SHIFT
-/**
-  * @}
-  */
-
-/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define OPAMP_NONINVERTINGINPUT_VP0           OPAMP_NONINVERTINGINPUT_IO0
-#define OPAMP_NONINVERTINGINPUT_VP1           OPAMP_NONINVERTINGINPUT_IO1
-#define OPAMP_NONINVERTINGINPUT_VP2           OPAMP_NONINVERTINGINPUT_IO2
-#define OPAMP_NONINVERTINGINPUT_VP3           OPAMP_NONINVERTINGINPUT_IO3
-                                              
-#define OPAMP_SEC_NONINVERTINGINPUT_VP0       OPAMP_SEC_NONINVERTINGINPUT_IO0
-#define OPAMP_SEC_NONINVERTINGINPUT_VP1       OPAMP_SEC_NONINVERTINGINPUT_IO1
-#define OPAMP_SEC_NONINVERTINGINPUT_VP2       OPAMP_SEC_NONINVERTINGINPUT_IO2
-#define OPAMP_SEC_NONINVERTINGINPUT_VP3       OPAMP_SEC_NONINVERTINGINPUT_IO3   
-
-#define OPAMP_INVERTINGINPUT_VM0              OPAMP_INVERTINGINPUT_IO0
-#define OPAMP_INVERTINGINPUT_VM1              OPAMP_INVERTINGINPUT_IO1
-
-#define IOPAMP_INVERTINGINPUT_VM0             OPAMP_INVERTINGINPUT_IO0
-#define IOPAMP_INVERTINGINPUT_VM1             OPAMP_INVERTINGINPUT_IO1
-
-#define OPAMP_SEC_INVERTINGINPUT_VM0          OPAMP_SEC_INVERTINGINPUT_IO0
-#define OPAMP_SEC_INVERTINGINPUT_VM1          OPAMP_SEC_INVERTINGINPUT_IO1    
-
-#define OPAMP_INVERTINGINPUT_VINM             OPAMP_SEC_INVERTINGINPUT_IO1
-                                                                      
-#define OPAMP_PGACONNECT_NO                   OPAMP_PGA_CONNECT_INVERTINGINPUT_NO             
-#define OPAMP_PGACONNECT_VM0                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0            
-#define OPAMP_PGACONNECT_VM1                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1          
-                                                        
-/**
-  * @}
-  */
-
-/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define I2S_STANDARD_PHILLIPS      I2S_STANDARD_PHILIPS
-#if defined(STM32F7) 
-  #define I2S_CLOCK_SYSCLK           I2S_CLOCK_PLL
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-/* Compact Flash-ATA registers description */
-#define CF_DATA                       ATA_DATA                
-#define CF_SECTOR_COUNT               ATA_SECTOR_COUNT        
-#define CF_SECTOR_NUMBER              ATA_SECTOR_NUMBER       
-#define CF_CYLINDER_LOW               ATA_CYLINDER_LOW        
-#define CF_CYLINDER_HIGH              ATA_CYLINDER_HIGH       
-#define CF_CARD_HEAD                  ATA_CARD_HEAD           
-#define CF_STATUS_CMD                 ATA_STATUS_CMD          
-#define CF_STATUS_CMD_ALTERNATE       ATA_STATUS_CMD_ALTERNATE
-#define CF_COMMON_DATA_AREA           ATA_COMMON_DATA_AREA    
-
-/* Compact Flash-ATA commands */
-#define CF_READ_SECTOR_CMD            ATA_READ_SECTOR_CMD 
-#define CF_WRITE_SECTOR_CMD           ATA_WRITE_SECTOR_CMD
-#define CF_ERASE_SECTOR_CMD           ATA_ERASE_SECTOR_CMD
-#define CF_IDENTIFY_CMD               ATA_IDENTIFY_CMD
-
-#define PCCARD_StatusTypedef          HAL_PCCARD_StatusTypeDef
-#define PCCARD_SUCCESS                HAL_PCCARD_STATUS_SUCCESS
-#define PCCARD_ONGOING                HAL_PCCARD_STATUS_ONGOING
-#define PCCARD_ERROR                  HAL_PCCARD_STATUS_ERROR
-#define PCCARD_TIMEOUT                HAL_PCCARD_STATUS_TIMEOUT
-/**
-  * @}
-  */
-  
-/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-  
-#define FORMAT_BIN                  RTC_FORMAT_BIN
-#define FORMAT_BCD                  RTC_FORMAT_BCD
-
-#define RTC_ALARMSUBSECONDMASK_None     RTC_ALARMSUBSECONDMASK_NONE
-#define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE
-#define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE
-#define RTC_TAMPERMASK_FLAG_DISABLED    RTC_TAMPERMASK_FLAG_DISABLE
-#define RTC_TAMPERMASK_FLAG_ENABLED     RTC_TAMPERMASK_FLAG_ENABLE
-
-#define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE 
-#define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE 
-#define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE
-#define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE 
-#define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE 
-#define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE
-#define RTC_TAMPER1_2_INTERRUPT         RTC_ALL_TAMPER_INTERRUPT 
-#define RTC_TAMPER1_2_3_INTERRUPT       RTC_ALL_TAMPER_INTERRUPT 
-
-#define RTC_TIMESTAMPPIN_PC13  RTC_TIMESTAMPPIN_DEFAULT
-#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 
-#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
-#define RTC_TIMESTAMPPIN_PC1   RTC_TIMESTAMPPIN_POS2
-
-#define RTC_OUTPUT_REMAP_PC13  RTC_OUTPUT_REMAP_NONE
-#define RTC_OUTPUT_REMAP_PB14  RTC_OUTPUT_REMAP_POS1
-#define RTC_OUTPUT_REMAP_PB2   RTC_OUTPUT_REMAP_POS1
-
-#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT 
-#define RTC_TAMPERPIN_PA0  RTC_TAMPERPIN_POS1 
-#define RTC_TAMPERPIN_PI8  RTC_TAMPERPIN_POS1
-
-/**
-  * @}
-  */
-
-  
-/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define SMARTCARD_NACK_ENABLED                  SMARTCARD_NACK_ENABLE
-#define SMARTCARD_NACK_DISABLED                 SMARTCARD_NACK_DISABLE
-
-#define SMARTCARD_ONEBIT_SAMPLING_DISABLED      SMARTCARD_ONE_BIT_SAMPLE_DISABLE
-#define SMARTCARD_ONEBIT_SAMPLING_ENABLED       SMARTCARD_ONE_BIT_SAMPLE_ENABLE
-#define SMARTCARD_ONEBIT_SAMPLING_DISABLE       SMARTCARD_ONE_BIT_SAMPLE_DISABLE
-#define SMARTCARD_ONEBIT_SAMPLING_ENABLE        SMARTCARD_ONE_BIT_SAMPLE_ENABLE
-
-#define SMARTCARD_TIMEOUT_DISABLED              SMARTCARD_TIMEOUT_DISABLE
-#define SMARTCARD_TIMEOUT_ENABLED               SMARTCARD_TIMEOUT_ENABLE
-
-#define SMARTCARD_LASTBIT_DISABLED              SMARTCARD_LASTBIT_DISABLE
-#define SMARTCARD_LASTBIT_ENABLED               SMARTCARD_LASTBIT_ENABLE
-/**
-  * @}
-  */
-
-  
-/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define SMBUS_DUALADDRESS_DISABLED      SMBUS_DUALADDRESS_DISABLE
-#define SMBUS_DUALADDRESS_ENABLED       SMBUS_DUALADDRESS_ENABLE
-#define SMBUS_GENERALCALL_DISABLED      SMBUS_GENERALCALL_DISABLE
-#define SMBUS_GENERALCALL_ENABLED       SMBUS_GENERALCALL_ENABLE
-#define SMBUS_NOSTRETCH_DISABLED        SMBUS_NOSTRETCH_DISABLE
-#define SMBUS_NOSTRETCH_ENABLED         SMBUS_NOSTRETCH_ENABLE
-#define SMBUS_ANALOGFILTER_ENABLED      SMBUS_ANALOGFILTER_ENABLE
-#define SMBUS_ANALOGFILTER_DISABLED     SMBUS_ANALOGFILTER_DISABLE
-#define SMBUS_PEC_DISABLED              SMBUS_PEC_DISABLE
-#define SMBUS_PEC_ENABLED               SMBUS_PEC_ENABLE
-#define HAL_SMBUS_STATE_SLAVE_LISTEN    HAL_SMBUS_STATE_LISTEN
-/**
-  * @}
-  */
-  
-/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define SPI_TIMODE_DISABLED             SPI_TIMODE_DISABLE
-#define SPI_TIMODE_ENABLED              SPI_TIMODE_ENABLE
-
-#define SPI_CRCCALCULATION_DISABLED     SPI_CRCCALCULATION_DISABLE
-#define SPI_CRCCALCULATION_ENABLED      SPI_CRCCALCULATION_ENABLE
-
-#define SPI_NSS_PULSE_DISABLED          SPI_NSS_PULSE_DISABLE
-#define SPI_NSS_PULSE_ENABLED           SPI_NSS_PULSE_ENABLE
-
-/**
-  * @}
-  */
-  
-/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define CCER_CCxE_MASK                   TIM_CCER_CCxE_MASK
-#define CCER_CCxNE_MASK                  TIM_CCER_CCxNE_MASK
-  
-#define TIM_DMABase_CR1                  TIM_DMABASE_CR1
-#define TIM_DMABase_CR2                  TIM_DMABASE_CR2
-#define TIM_DMABase_SMCR                 TIM_DMABASE_SMCR
-#define TIM_DMABase_DIER                 TIM_DMABASE_DIER
-#define TIM_DMABase_SR                   TIM_DMABASE_SR
-#define TIM_DMABase_EGR                  TIM_DMABASE_EGR
-#define TIM_DMABase_CCMR1                TIM_DMABASE_CCMR1
-#define TIM_DMABase_CCMR2                TIM_DMABASE_CCMR2
-#define TIM_DMABase_CCER                 TIM_DMABASE_CCER
-#define TIM_DMABase_CNT                  TIM_DMABASE_CNT
-#define TIM_DMABase_PSC                  TIM_DMABASE_PSC
-#define TIM_DMABase_ARR                  TIM_DMABASE_ARR
-#define TIM_DMABase_RCR                  TIM_DMABASE_RCR
-#define TIM_DMABase_CCR1                 TIM_DMABASE_CCR1
-#define TIM_DMABase_CCR2                 TIM_DMABASE_CCR2
-#define TIM_DMABase_CCR3                 TIM_DMABASE_CCR3
-#define TIM_DMABase_CCR4                 TIM_DMABASE_CCR4
-#define TIM_DMABase_BDTR                 TIM_DMABASE_BDTR
-#define TIM_DMABase_DCR                  TIM_DMABASE_DCR
-#define TIM_DMABase_DMAR                 TIM_DMABASE_DMAR
-#define TIM_DMABase_OR1                  TIM_DMABASE_OR1
-#define TIM_DMABase_CCMR3                TIM_DMABASE_CCMR3
-#define TIM_DMABase_CCR5                 TIM_DMABASE_CCR5
-#define TIM_DMABase_CCR6                 TIM_DMABASE_CCR6
-#define TIM_DMABase_OR2                  TIM_DMABASE_OR2
-#define TIM_DMABase_OR3                  TIM_DMABASE_OR3
-#define TIM_DMABase_OR                   TIM_DMABASE_OR
-
-#define TIM_EventSource_Update           TIM_EVENTSOURCE_UPDATE
-#define TIM_EventSource_CC1              TIM_EVENTSOURCE_CC1
-#define TIM_EventSource_CC2              TIM_EVENTSOURCE_CC2
-#define TIM_EventSource_CC3              TIM_EVENTSOURCE_CC3
-#define TIM_EventSource_CC4              TIM_EVENTSOURCE_CC4
-#define TIM_EventSource_COM              TIM_EVENTSOURCE_COM
-#define TIM_EventSource_Trigger          TIM_EVENTSOURCE_TRIGGER
-#define TIM_EventSource_Break            TIM_EVENTSOURCE_BREAK
-#define TIM_EventSource_Break2           TIM_EVENTSOURCE_BREAK2
-
-#define TIM_DMABurstLength_1Transfer     TIM_DMABURSTLENGTH_1TRANSFER
-#define TIM_DMABurstLength_2Transfers    TIM_DMABURSTLENGTH_2TRANSFERS
-#define TIM_DMABurstLength_3Transfers    TIM_DMABURSTLENGTH_3TRANSFERS
-#define TIM_DMABurstLength_4Transfers    TIM_DMABURSTLENGTH_4TRANSFERS
-#define TIM_DMABurstLength_5Transfers    TIM_DMABURSTLENGTH_5TRANSFERS
-#define TIM_DMABurstLength_6Transfers    TIM_DMABURSTLENGTH_6TRANSFERS
-#define TIM_DMABurstLength_7Transfers    TIM_DMABURSTLENGTH_7TRANSFERS
-#define TIM_DMABurstLength_8Transfers    TIM_DMABURSTLENGTH_8TRANSFERS
-#define TIM_DMABurstLength_9Transfers    TIM_DMABURSTLENGTH_9TRANSFERS
-#define TIM_DMABurstLength_10Transfers   TIM_DMABURSTLENGTH_10TRANSFERS
-#define TIM_DMABurstLength_11Transfers   TIM_DMABURSTLENGTH_11TRANSFERS
-#define TIM_DMABurstLength_12Transfers   TIM_DMABURSTLENGTH_12TRANSFERS
-#define TIM_DMABurstLength_13Transfers   TIM_DMABURSTLENGTH_13TRANSFERS
-#define TIM_DMABurstLength_14Transfers   TIM_DMABURSTLENGTH_14TRANSFERS
-#define TIM_DMABurstLength_15Transfers   TIM_DMABURSTLENGTH_15TRANSFERS
-#define TIM_DMABurstLength_16Transfers   TIM_DMABURSTLENGTH_16TRANSFERS
-#define TIM_DMABurstLength_17Transfers   TIM_DMABURSTLENGTH_17TRANSFERS
-#define TIM_DMABurstLength_18Transfers   TIM_DMABURSTLENGTH_18TRANSFERS
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define TSC_SYNC_POL_FALL        TSC_SYNC_POLARITY_FALLING
-#define TSC_SYNC_POL_RISE_HIGH   TSC_SYNC_POLARITY_RISING
-/**
-  * @}
-  */
-
-/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define UART_ONEBIT_SAMPLING_DISABLED   UART_ONE_BIT_SAMPLE_DISABLE
-#define UART_ONEBIT_SAMPLING_ENABLED    UART_ONE_BIT_SAMPLE_ENABLE
-#define UART_ONE_BIT_SAMPLE_DISABLED    UART_ONE_BIT_SAMPLE_DISABLE
-#define UART_ONE_BIT_SAMPLE_ENABLED     UART_ONE_BIT_SAMPLE_ENABLE
-
-#define __HAL_UART_ONEBIT_ENABLE        __HAL_UART_ONE_BIT_SAMPLE_ENABLE
-#define __HAL_UART_ONEBIT_DISABLE       __HAL_UART_ONE_BIT_SAMPLE_DISABLE
-
-#define __DIV_SAMPLING16                UART_DIV_SAMPLING16
-#define __DIVMANT_SAMPLING16            UART_DIVMANT_SAMPLING16
-#define __DIVFRAQ_SAMPLING16            UART_DIVFRAQ_SAMPLING16
-#define __UART_BRR_SAMPLING16           UART_BRR_SAMPLING16
-
-#define __DIV_SAMPLING8                 UART_DIV_SAMPLING8
-#define __DIVMANT_SAMPLING8             UART_DIVMANT_SAMPLING8
-#define __DIVFRAQ_SAMPLING8             UART_DIVFRAQ_SAMPLING8
-#define __UART_BRR_SAMPLING8            UART_BRR_SAMPLING8
-
-#define UART_WAKEUPMETHODE_IDLELINE     UART_WAKEUPMETHOD_IDLELINE
-#define UART_WAKEUPMETHODE_ADDRESSMARK  UART_WAKEUPMETHOD_ADDRESSMARK
-
-/**
-  * @}
-  */
-
-  
-/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define USART_CLOCK_DISABLED            USART_CLOCK_DISABLE
-#define USART_CLOCK_ENABLED             USART_CLOCK_ENABLE
-
-#define USARTNACK_ENABLED               USART_NACK_ENABLE
-#define USARTNACK_DISABLED              USART_NACK_DISABLE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define CFR_BASE                    WWDG_CFR_BASE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define CAN_FilterFIFO0             CAN_FILTER_FIFO0
-#define CAN_FilterFIFO1             CAN_FILTER_FIFO1
-#define CAN_IT_RQCP0                CAN_IT_TME
-#define CAN_IT_RQCP1                CAN_IT_TME
-#define CAN_IT_RQCP2                CAN_IT_TME
-#define INAK_TIMEOUT                CAN_TIMEOUT_VALUE
-#define SLAK_TIMEOUT                CAN_TIMEOUT_VALUE
-#define CAN_TXSTATUS_FAILED         ((uint8_t)0x00U)
-#define CAN_TXSTATUS_OK             ((uint8_t)0x01U)
-#define CAN_TXSTATUS_PENDING        ((uint8_t)0x02U)
-
-/**
-  * @}
-  */
-  
-/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define VLAN_TAG                ETH_VLAN_TAG
-#define MIN_ETH_PAYLOAD         ETH_MIN_ETH_PAYLOAD
-#define MAX_ETH_PAYLOAD         ETH_MAX_ETH_PAYLOAD
-#define JUMBO_FRAME_PAYLOAD     ETH_JUMBO_FRAME_PAYLOAD
-#define MACMIIAR_CR_MASK        ETH_MACMIIAR_CR_MASK
-#define MACCR_CLEAR_MASK        ETH_MACCR_CLEAR_MASK
-#define MACFCR_CLEAR_MASK       ETH_MACFCR_CLEAR_MASK
-#define DMAOMR_CLEAR_MASK       ETH_DMAOMR_CLEAR_MASK
-
-#define ETH_MMCCR              ((uint32_t)0x00000100U)  
-#define ETH_MMCRIR             ((uint32_t)0x00000104U)  
-#define ETH_MMCTIR             ((uint32_t)0x00000108U)  
-#define ETH_MMCRIMR            ((uint32_t)0x0000010CU)  
-#define ETH_MMCTIMR            ((uint32_t)0x00000110U)  
-#define ETH_MMCTGFSCCR         ((uint32_t)0x0000014CU)  
-#define ETH_MMCTGFMSCCR        ((uint32_t)0x00000150U)  
-#define ETH_MMCTGFCR           ((uint32_t)0x00000168U)  
-#define ETH_MMCRFCECR          ((uint32_t)0x00000194U)  
-#define ETH_MMCRFAECR          ((uint32_t)0x00000198U)  
-#define ETH_MMCRGUFCR          ((uint32_t)0x000001C4U)
- 
-#define ETH_MAC_TXFIFO_FULL          ((uint32_t)0x02000000)  /* Tx FIFO full */
-#define ETH_MAC_TXFIFONOT_EMPTY      ((uint32_t)0x01000000)  /* Tx FIFO not empty */
-#define ETH_MAC_TXFIFO_WRITE_ACTIVE  ((uint32_t)0x00400000)  /* Tx FIFO write active */
-#define ETH_MAC_TXFIFO_IDLE     ((uint32_t)0x00000000)  /* Tx FIFO read status: Idle */
-#define ETH_MAC_TXFIFO_READ     ((uint32_t)0x00100000)  /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
-#define ETH_MAC_TXFIFO_WAITING  ((uint32_t)0x00200000)  /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
-#define ETH_MAC_TXFIFO_WRITING  ((uint32_t)0x00300000)  /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
-#define ETH_MAC_TRANSMISSION_PAUSE     ((uint32_t)0x00080000)  /* MAC transmitter in pause */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE            ((uint32_t)0x00000000)  /* MAC transmit frame controller: Idle */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING         ((uint32_t)0x00020000)  /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF   ((uint32_t)0x00040000)  /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING    ((uint32_t)0x00060000)  /* MAC transmit frame controller: Transferring input frame for transmission */
-#define ETH_MAC_MII_TRANSMIT_ACTIVE      ((uint32_t)0x00010000)  /* MAC MII transmit engine active */
-#define ETH_MAC_RXFIFO_EMPTY             ((uint32_t)0x00000000)  /* Rx FIFO fill level: empty */
-#define ETH_MAC_RXFIFO_BELOW_THRESHOLD   ((uint32_t)0x00000100)  /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
-#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD   ((uint32_t)0x00000200)  /* Rx FIFO fill level: fill-level above flow-control activate threshold */
-#define ETH_MAC_RXFIFO_FULL              ((uint32_t)0x00000300)  /* Rx FIFO fill level: full */
-#if defined(STM32F1)
-#else
-#define ETH_MAC_READCONTROLLER_IDLE               ((uint32_t)0x00000000)  /* Rx FIFO read controller IDLE state */
-#define ETH_MAC_READCONTROLLER_READING_DATA       ((uint32_t)0x00000020)  /* Rx FIFO read controller Reading frame data */
-#define ETH_MAC_READCONTROLLER_READING_STATUS     ((uint32_t)0x00000040)  /* Rx FIFO read controller Reading frame status (or time-stamp) */
-#endif
-#define ETH_MAC_READCONTROLLER_FLUSHING           ((uint32_t)0x00000060)  /* Rx FIFO read controller Flushing the frame data and status */
-#define ETH_MAC_RXFIFO_WRITE_ACTIVE     ((uint32_t)0x00000010)  /* Rx FIFO write controller active */
-#define ETH_MAC_SMALL_FIFO_NOTACTIVE    ((uint32_t)0x00000000)  /* MAC small FIFO read / write controllers not active */
-#define ETH_MAC_SMALL_FIFO_READ_ACTIVE  ((uint32_t)0x00000002)  /* MAC small FIFO read controller active */
-#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004)  /* MAC small FIFO write controller active */
-#define ETH_MAC_SMALL_FIFO_RW_ACTIVE    ((uint32_t)0x00000006)  /* MAC small FIFO read / write controllers active */
-#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE   ((uint32_t)0x00000001)  /* MAC MII receive protocol engine active */
-
-/**
-  * @}
-  */
-  
-/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define HAL_DCMI_ERROR_OVF      HAL_DCMI_ERROR_OVR
-#define DCMI_IT_OVF             DCMI_IT_OVR
-#define DCMI_FLAG_OVFRI         DCMI_FLAG_OVRRI
-#define DCMI_FLAG_OVFMI         DCMI_FLAG_OVRMI
-
-#define HAL_DCMI_ConfigCROP     HAL_DCMI_ConfigCrop
-#define HAL_DCMI_EnableCROP     HAL_DCMI_EnableCrop
-#define HAL_DCMI_DisableCROP    HAL_DCMI_DisableCrop
-
-/**
-  * @}
-  */  
-  
-#if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
-    defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define DMA2D_ARGB8888          DMA2D_OUTPUT_ARGB8888
-#define DMA2D_RGB888            DMA2D_OUTPUT_RGB888  
-#define DMA2D_RGB565            DMA2D_OUTPUT_RGB565  
-#define DMA2D_ARGB1555          DMA2D_OUTPUT_ARGB1555
-#define DMA2D_ARGB4444          DMA2D_OUTPUT_ARGB4444
-
-#define CM_ARGB8888             DMA2D_INPUT_ARGB8888
-#define CM_RGB888               DMA2D_INPUT_RGB888  
-#define CM_RGB565               DMA2D_INPUT_RGB565  
-#define CM_ARGB1555             DMA2D_INPUT_ARGB1555
-#define CM_ARGB4444             DMA2D_INPUT_ARGB4444
-#define CM_L8                   DMA2D_INPUT_L8      
-#define CM_AL44                 DMA2D_INPUT_AL44    
-#define CM_AL88                 DMA2D_INPUT_AL88    
-#define CM_L4                   DMA2D_INPUT_L4      
-#define CM_A8                   DMA2D_INPUT_A8      
-#define CM_A4                   DMA2D_INPUT_A4      
-/**
-  * @}
-  */    
-#endif  /* STM32L4xx ||  STM32F7*/
-
-/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
-  * @{
-  */
-  
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_CRYP_ComputationCpltCallback     HAL_CRYPEx_ComputationCpltCallback
-/**
-  * @}
-  */  
-
-/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
-  * @{
-  */ 
-#define HAL_HASH_STATETypeDef        HAL_HASH_StateTypeDef
-#define HAL_HASHPhaseTypeDef         HAL_HASH_PhaseTypeDef
-#define HAL_HMAC_MD5_Finish          HAL_HASH_MD5_Finish
-#define HAL_HMAC_SHA1_Finish         HAL_HASH_SHA1_Finish
-#define HAL_HMAC_SHA224_Finish       HAL_HASH_SHA224_Finish
-#define HAL_HMAC_SHA256_Finish       HAL_HASH_SHA256_Finish
-
-/*HASH Algorithm Selection*/
-
-#define HASH_AlgoSelection_SHA1      HASH_ALGOSELECTION_SHA1 
-#define HASH_AlgoSelection_SHA224    HASH_ALGOSELECTION_SHA224
-#define HASH_AlgoSelection_SHA256    HASH_ALGOSELECTION_SHA256
-#define HASH_AlgoSelection_MD5       HASH_ALGOSELECTION_MD5
-
-#define HASH_AlgoMode_HASH         HASH_ALGOMODE_HASH 
-#define HASH_AlgoMode_HMAC         HASH_ALGOMODE_HMAC
-
-#define HASH_HMACKeyType_ShortKey  HASH_HMAC_KEYTYPE_SHORTKEY
-#define HASH_HMACKeyType_LongKey   HASH_HMAC_KEYTYPE_LONGKEY
-/**
-  * @}
-  */
-  
-/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
-#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
-#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
-#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
-#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
-#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
-#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
-#define HAL_VREFINT_OutputSelect  HAL_SYSCFG_VREFINT_OutputSelect
-#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
-#if defined(STM32L0)
-#else
-#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
-#endif
-#define HAL_ADC_EnableBuffer_Cmd(cmd)  (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
-#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
-/**
-  * @}
-  */
-
-/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define FLASH_HalfPageProgram      HAL_FLASHEx_HalfPageProgram
-#define FLASH_EnableRunPowerDown   HAL_FLASHEx_EnableRunPowerDown
-#define FLASH_DisableRunPowerDown  HAL_FLASHEx_DisableRunPowerDown
-#define HAL_DATA_EEPROMEx_Unlock   HAL_FLASHEx_DATAEEPROM_Unlock
-#define HAL_DATA_EEPROMEx_Lock     HAL_FLASHEx_DATAEEPROM_Lock
-#define HAL_DATA_EEPROMEx_Erase    HAL_FLASHEx_DATAEEPROM_Erase
-#define HAL_DATA_EEPROMEx_Program  HAL_FLASHEx_DATAEEPROM_Program
-
- /**
-  * @}
-  */
-
-/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_I2CEx_AnalogFilter_Config         HAL_I2CEx_ConfigAnalogFilter
-#define HAL_I2CEx_DigitalFilter_Config        HAL_I2CEx_ConfigDigitalFilter
-#define HAL_FMPI2CEx_AnalogFilter_Config      HAL_FMPI2CEx_ConfigAnalogFilter
-#define HAL_FMPI2CEx_DigitalFilter_Config     HAL_FMPI2CEx_ConfigDigitalFilter
-
-#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
- /**
-  * @}
-  */
-
-/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
-  * @{
-  */
-#define HAL_PWR_PVDConfig                             HAL_PWR_ConfigPVD
-#define HAL_PWR_DisableBkUpReg                        HAL_PWREx_DisableBkUpReg
-#define HAL_PWR_DisableFlashPowerDown                 HAL_PWREx_DisableFlashPowerDown
-#define HAL_PWR_DisableVddio2Monitor                  HAL_PWREx_DisableVddio2Monitor
-#define HAL_PWR_EnableBkUpReg                         HAL_PWREx_EnableBkUpReg
-#define HAL_PWR_EnableFlashPowerDown                  HAL_PWREx_EnableFlashPowerDown
-#define HAL_PWR_EnableVddio2Monitor                   HAL_PWREx_EnableVddio2Monitor
-#define HAL_PWR_PVD_PVM_IRQHandler                    HAL_PWREx_PVD_PVM_IRQHandler
-#define HAL_PWR_PVDLevelConfig                        HAL_PWR_ConfigPVD
-#define HAL_PWR_Vddio2Monitor_IRQHandler              HAL_PWREx_Vddio2Monitor_IRQHandler
-#define HAL_PWR_Vddio2MonitorCallback                 HAL_PWREx_Vddio2MonitorCallback
-#define HAL_PWREx_ActivateOverDrive                   HAL_PWREx_EnableOverDrive
-#define HAL_PWREx_DeactivateOverDrive                 HAL_PWREx_DisableOverDrive
-#define HAL_PWREx_DisableSDADCAnalog                  HAL_PWREx_DisableSDADC
-#define HAL_PWREx_EnableSDADCAnalog                   HAL_PWREx_EnableSDADC
-#define HAL_PWREx_PVMConfig                           HAL_PWREx_ConfigPVM
-
-#define PWR_MODE_NORMAL                               PWR_PVD_MODE_NORMAL
-#define PWR_MODE_IT_RISING                            PWR_PVD_MODE_IT_RISING
-#define PWR_MODE_IT_FALLING                           PWR_PVD_MODE_IT_FALLING
-#define PWR_MODE_IT_RISING_FALLING                    PWR_PVD_MODE_IT_RISING_FALLING
-#define PWR_MODE_EVENT_RISING                         PWR_PVD_MODE_EVENT_RISING
-#define PWR_MODE_EVENT_FALLING                        PWR_PVD_MODE_EVENT_FALLING
-#define PWR_MODE_EVENT_RISING_FALLING                 PWR_PVD_MODE_EVENT_RISING_FALLING
-
-#define CR_OFFSET_BB                                  PWR_CR_OFFSET_BB
-#define CSR_OFFSET_BB                                 PWR_CSR_OFFSET_BB
-
-#define DBP_BitNumber                                 DBP_BIT_NUMBER
-#define PVDE_BitNumber                                PVDE_BIT_NUMBER
-#define PMODE_BitNumber                               PMODE_BIT_NUMBER
-#define EWUP_BitNumber                                EWUP_BIT_NUMBER
-#define FPDS_BitNumber                                FPDS_BIT_NUMBER
-#define ODEN_BitNumber                                ODEN_BIT_NUMBER
-#define ODSWEN_BitNumber                              ODSWEN_BIT_NUMBER
-#define MRLVDS_BitNumber                              MRLVDS_BIT_NUMBER
-#define LPLVDS_BitNumber                              LPLVDS_BIT_NUMBER
-#define BRE_BitNumber                                 BRE_BIT_NUMBER
-
-#define PWR_MODE_EVT                                  PWR_PVD_MODE_NORMAL
- 
- /**
-  * @}
-  */  
-  
-/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_SMBUS_Slave_Listen_IT          HAL_SMBUS_EnableListen_IT
-#define HAL_SMBUS_SlaveAddrCallback        HAL_SMBUS_AddrCallback         
-#define HAL_SMBUS_SlaveListenCpltCallback  HAL_SMBUS_ListenCpltCallback   
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_SPI_FlushRxFifo                HAL_SPIEx_FlushRxFifo
-/**
-  * @}
-  */  
-
-/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_TIM_DMADelayPulseCplt                       TIM_DMADelayPulseCplt
-#define HAL_TIM_DMAError                                TIM_DMAError
-#define HAL_TIM_DMACaptureCplt                          TIM_DMACaptureCplt
-#define HAL_TIMEx_DMACommutationCplt                    TIMEx_DMACommutationCplt
-/**
-  * @}
-  */
-   
-/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
-  * @{
-  */ 
-#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
-/**
-  * @}
-  */
-  
-/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
-  * @{
-  */ 
-#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
-/**
-  * @}
-  */  
-   
-  
-/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
-  * @{
-  */
-  
-/**
-  * @}
-  */
-
-/* Exported macros ------------------------------------------------------------*/
-
-/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define AES_IT_CC                      CRYP_IT_CC
-#define AES_IT_ERR                     CRYP_IT_ERR
-#define AES_FLAG_CCF                   CRYP_FLAG_CCF
-/**
-  * @}
-  */  
-  
-/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_GET_BOOT_MODE                   __HAL_SYSCFG_GET_BOOT_MODE
-#define __HAL_REMAPMEMORY_FLASH               __HAL_SYSCFG_REMAPMEMORY_FLASH
-#define __HAL_REMAPMEMORY_SYSTEMFLASH         __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
-#define __HAL_REMAPMEMORY_SRAM                __HAL_SYSCFG_REMAPMEMORY_SRAM
-#define __HAL_REMAPMEMORY_FMC                 __HAL_SYSCFG_REMAPMEMORY_FMC
-#define __HAL_REMAPMEMORY_FMC_SDRAM           __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM 
-#define __HAL_REMAPMEMORY_FSMC                __HAL_SYSCFG_REMAPMEMORY_FSMC
-#define __HAL_REMAPMEMORY_QUADSPI             __HAL_SYSCFG_REMAPMEMORY_QUADSPI
-#define __HAL_FMC_BANK                        __HAL_SYSCFG_FMC_BANK
-#define __HAL_GET_FLAG                        __HAL_SYSCFG_GET_FLAG
-#define __HAL_CLEAR_FLAG                      __HAL_SYSCFG_CLEAR_FLAG
-#define __HAL_VREFINT_OUT_ENABLE              __HAL_SYSCFG_VREFINT_OUT_ENABLE
-#define __HAL_VREFINT_OUT_DISABLE             __HAL_SYSCFG_VREFINT_OUT_DISABLE
-
-#define SYSCFG_FLAG_VREF_READY                SYSCFG_FLAG_VREFINT_READY
-#define SYSCFG_FLAG_RC48                      RCC_FLAG_HSI48
-#define IS_SYSCFG_FASTMODEPLUS_CONFIG         IS_I2C_FASTMODEPLUS
-#define UFB_MODE_BitNumber                    UFB_MODE_BIT_NUMBER
-#define CMP_PD_BitNumber                      CMP_PD_BIT_NUMBER
-
-/**
-  * @}
-  */
-
-   
-/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __ADC_ENABLE                                     __HAL_ADC_ENABLE
-#define __ADC_DISABLE                                    __HAL_ADC_DISABLE
-#define __HAL_ADC_ENABLING_CONDITIONS                    ADC_ENABLING_CONDITIONS
-#define __HAL_ADC_DISABLING_CONDITIONS                   ADC_DISABLING_CONDITIONS
-#define __HAL_ADC_IS_ENABLED                             ADC_IS_ENABLE
-#define __ADC_IS_ENABLED                                 ADC_IS_ENABLE
-#define __HAL_ADC_IS_SOFTWARE_START_REGULAR              ADC_IS_SOFTWARE_START_REGULAR
-#define __HAL_ADC_IS_SOFTWARE_START_INJECTED             ADC_IS_SOFTWARE_START_INJECTED
-#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
-#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR          ADC_IS_CONVERSION_ONGOING_REGULAR
-#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED         ADC_IS_CONVERSION_ONGOING_INJECTED
-#define __HAL_ADC_IS_CONVERSION_ONGOING                  ADC_IS_CONVERSION_ONGOING
-#define __HAL_ADC_CLEAR_ERRORCODE                        ADC_CLEAR_ERRORCODE
-
-#define __HAL_ADC_GET_RESOLUTION                         ADC_GET_RESOLUTION
-#define __HAL_ADC_JSQR_RK                                ADC_JSQR_RK
-#define __HAL_ADC_CFGR_AWD1CH                            ADC_CFGR_AWD1CH_SHIFT
-#define __HAL_ADC_CFGR_AWD23CR                           ADC_CFGR_AWD23CR
-#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION            ADC_CFGR_INJECT_AUTO_CONVERSION
-#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE              ADC_CFGR_INJECT_CONTEXT_QUEUE
-#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS             ADC_CFGR_INJECT_DISCCONTINUOUS
-#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS                ADC_CFGR_REG_DISCCONTINUOUS
-#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM                 ADC_CFGR_DISCONTINUOUS_NUM
-#define __HAL_ADC_CFGR_AUTOWAIT                          ADC_CFGR_AUTOWAIT
-#define __HAL_ADC_CFGR_CONTINUOUS                        ADC_CFGR_CONTINUOUS
-#define __HAL_ADC_CFGR_OVERRUN                           ADC_CFGR_OVERRUN
-#define __HAL_ADC_CFGR_DMACONTREQ                        ADC_CFGR_DMACONTREQ
-#define __HAL_ADC_CFGR_EXTSEL                            ADC_CFGR_EXTSEL_SET
-#define __HAL_ADC_JSQR_JEXTSEL                           ADC_JSQR_JEXTSEL_SET
-#define __HAL_ADC_OFR_CHANNEL                            ADC_OFR_CHANNEL
-#define __HAL_ADC_DIFSEL_CHANNEL                         ADC_DIFSEL_CHANNEL
-#define __HAL_ADC_CALFACT_DIFF_SET                       ADC_CALFACT_DIFF_SET
-#define __HAL_ADC_CALFACT_DIFF_GET                       ADC_CALFACT_DIFF_GET
-#define __HAL_ADC_TRX_HIGHTHRESHOLD                      ADC_TRX_HIGHTHRESHOLD
-
-#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION                ADC_OFFSET_SHIFT_RESOLUTION
-#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION         ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
-#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION        ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
-#define __HAL_ADC_COMMON_REGISTER                        ADC_COMMON_REGISTER
-#define __HAL_ADC_COMMON_CCR_MULTI                       ADC_COMMON_CCR_MULTI
-#define __HAL_ADC_MULTIMODE_IS_ENABLED                   ADC_MULTIMODE_IS_ENABLE
-#define __ADC_MULTIMODE_IS_ENABLED                       ADC_MULTIMODE_IS_ENABLE
-#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER        ADC_NONMULTIMODE_OR_MULTIMODEMASTER
-#define __HAL_ADC_COMMON_ADC_OTHER                       ADC_COMMON_ADC_OTHER
-#define __HAL_ADC_MULTI_SLAVE                            ADC_MULTI_SLAVE
-
-#define __HAL_ADC_SQR1_L                                 ADC_SQR1_L_SHIFT
-#define __HAL_ADC_JSQR_JL                                ADC_JSQR_JL_SHIFT
-#define __HAL_ADC_JSQR_RK_JL                             ADC_JSQR_RK_JL
-#define __HAL_ADC_CR1_DISCONTINUOUS_NUM                  ADC_CR1_DISCONTINUOUS_NUM
-#define __HAL_ADC_CR1_SCAN                               ADC_CR1_SCAN_SET
-#define __HAL_ADC_CONVCYCLES_MAX_RANGE                   ADC_CONVCYCLES_MAX_RANGE
-#define __HAL_ADC_CLOCK_PRESCALER_RANGE                  ADC_CLOCK_PRESCALER_RANGE
-#define __HAL_ADC_GET_CLOCK_PRESCALER                    ADC_GET_CLOCK_PRESCALER
-
-#define __HAL_ADC_SQR1                                   ADC_SQR1
-#define __HAL_ADC_SMPR1                                  ADC_SMPR1
-#define __HAL_ADC_SMPR2                                  ADC_SMPR2
-#define __HAL_ADC_SQR3_RK                                ADC_SQR3_RK
-#define __HAL_ADC_SQR2_RK                                ADC_SQR2_RK
-#define __HAL_ADC_SQR1_RK                                ADC_SQR1_RK
-#define __HAL_ADC_CR2_CONTINUOUS                         ADC_CR2_CONTINUOUS
-#define __HAL_ADC_CR1_DISCONTINUOUS                      ADC_CR1_DISCONTINUOUS
-#define __HAL_ADC_CR1_SCANCONV                           ADC_CR1_SCANCONV
-#define __HAL_ADC_CR2_EOCSelection                       ADC_CR2_EOCSelection
-#define __HAL_ADC_CR2_DMAContReq                         ADC_CR2_DMAContReq
-#define __HAL_ADC_GET_RESOLUTION                         ADC_GET_RESOLUTION
-#define __HAL_ADC_JSQR                                   ADC_JSQR
-
-#define __HAL_ADC_CHSELR_CHANNEL                         ADC_CHSELR_CHANNEL
-#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS               ADC_CFGR1_REG_DISCCONTINUOUS
-#define __HAL_ADC_CFGR1_AUTOOFF                          ADC_CFGR1_AUTOOFF
-#define __HAL_ADC_CFGR1_AUTOWAIT                         ADC_CFGR1_AUTOWAIT
-#define __HAL_ADC_CFGR1_CONTINUOUS                       ADC_CFGR1_CONTINUOUS
-#define __HAL_ADC_CFGR1_OVERRUN                          ADC_CFGR1_OVERRUN
-#define __HAL_ADC_CFGR1_SCANDIR                          ADC_CFGR1_SCANDIR
-#define __HAL_ADC_CFGR1_DMACONTREQ                       ADC_CFGR1_DMACONTREQ
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_DHR12R1_ALIGNEMENT                        DAC_DHR12R1_ALIGNMENT
-#define __HAL_DHR12R2_ALIGNEMENT                        DAC_DHR12R2_ALIGNMENT
-#define __HAL_DHR12RD_ALIGNEMENT                        DAC_DHR12RD_ALIGNMENT
-#define IS_DAC_GENERATE_WAVE                            IS_DAC_WAVE
-
-/**
-  * @}
-  */
-   
-/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
-#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
-#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
-#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
-#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
-#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
-#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
-#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
-#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
-#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
-#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
-#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
-#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
-#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
-#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
-#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
-
-#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
-#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
-#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
-#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
-#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
-#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
-#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
-#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
-#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
-#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
-#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
-#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
-#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
-#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
-
-
-#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
-#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
-#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
-#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
-#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
-#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
-#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
-#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
-#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
-#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
-#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
-#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
-#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
-#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
-#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
-#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
-#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
-#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
-#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
-#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
-#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
-#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
-#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
-#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#if defined(STM32F3)
-#define COMP_START                                       __HAL_COMP_ENABLE
-#define COMP_STOP                                        __HAL_COMP_DISABLE
-#define COMP_LOCK                                        __HAL_COMP_LOCK
-   
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
-                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F302xE) || defined(STM32F302xC)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
-                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
-                                                          __HAL_COMP_COMP7_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
-                                                          __HAL_COMP_COMP7_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
-                                                          __HAL_COMP_COMP7_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F373xC) ||defined(STM32F378xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
-                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
-# endif
-#else
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
-                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
-#endif
-
-#define __HAL_COMP_GET_EXTI_LINE  COMP_GET_EXTI_LINE
-
-#if defined(STM32L0) || defined(STM32L4)
-/* Note: On these STM32 families, the only argument of this macro             */
-/*       is COMP_FLAG_LOCK.                                                   */
-/*       This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle  */
-/*       argument.                                                            */
-#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__)  (__HAL_COMP_IS_LOCKED(__HANDLE__))
-#endif
-/**
-  * @}
-  */
-
-#if defined(STM32L0) || defined(STM32L4)
-/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_COMP_Start_IT       HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
-#define HAL_COMP_Stop_IT        HAL_COMP_Stop  /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
-/**
-  * @}
-  */
-#endif
-
-/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
-                          ((WAVE) == DAC_WAVE_NOISE)|| \
-                          ((WAVE) == DAC_WAVE_TRIANGLE))
-  
-/**
-  * @}
-  */
-
-/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define IS_WRPAREA          IS_OB_WRPAREA
-#define IS_TYPEPROGRAM      IS_FLASH_TYPEPROGRAM
-#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
-#define IS_TYPEERASE        IS_FLASH_TYPEERASE
-#define IS_NBSECTORS        IS_FLASH_NBSECTORS
-#define IS_OB_WDG_SOURCE    IS_OB_IWDG_SOURCE
-
-/**
-  * @}
-  */
-  
-/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
-  * @{
-  */
-  
-#define __HAL_I2C_RESET_CR2             I2C_RESET_CR2
-#define __HAL_I2C_GENERATE_START        I2C_GENERATE_START
-#define __HAL_I2C_FREQ_RANGE            I2C_FREQ_RANGE
-#define __HAL_I2C_RISE_TIME             I2C_RISE_TIME
-#define __HAL_I2C_SPEED_STANDARD        I2C_SPEED_STANDARD
-#define __HAL_I2C_SPEED_FAST            I2C_SPEED_FAST
-#define __HAL_I2C_SPEED                 I2C_SPEED
-#define __HAL_I2C_7BIT_ADD_WRITE        I2C_7BIT_ADD_WRITE
-#define __HAL_I2C_7BIT_ADD_READ         I2C_7BIT_ADD_READ
-#define __HAL_I2C_10BIT_ADDRESS         I2C_10BIT_ADDRESS
-#define __HAL_I2C_10BIT_HEADER_WRITE    I2C_10BIT_HEADER_WRITE
-#define __HAL_I2C_10BIT_HEADER_READ     I2C_10BIT_HEADER_READ
-#define __HAL_I2C_MEM_ADD_MSB           I2C_MEM_ADD_MSB
-#define __HAL_I2C_MEM_ADD_LSB           I2C_MEM_ADD_LSB
-#define __HAL_I2C_FREQRANGE             I2C_FREQRANGE
-/**
-  * @}
-  */
-  
-/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
-  * @{
-  */
-  
-#define IS_I2S_INSTANCE                 IS_I2S_ALL_INSTANCE
-#define IS_I2S_INSTANCE_EXT             IS_I2S_ALL_INSTANCE_EXT
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
-  * @{
-  */
-  
-#define __IRDA_DISABLE                  __HAL_IRDA_DISABLE
-#define __IRDA_ENABLE                   __HAL_IRDA_ENABLE
-
-#define __HAL_IRDA_GETCLOCKSOURCE       IRDA_GETCLOCKSOURCE
-#define __HAL_IRDA_MASK_COMPUTATION     IRDA_MASK_COMPUTATION
-#define __IRDA_GETCLOCKSOURCE           IRDA_GETCLOCKSOURCE
-#define __IRDA_MASK_COMPUTATION         IRDA_MASK_COMPUTATION
-
-#define IS_IRDA_ONEBIT_SAMPLE           IS_IRDA_ONE_BIT_SAMPLE                  
-
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_IWDG_ENABLE_WRITE_ACCESS  IWDG_ENABLE_WRITE_ACCESS
-#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __HAL_LPTIM_ENABLE_INTERRUPT    __HAL_LPTIM_ENABLE_IT
-#define __HAL_LPTIM_DISABLE_INTERRUPT   __HAL_LPTIM_DISABLE_IT
-#define __HAL_LPTIM_GET_ITSTATUS        __HAL_LPTIM_GET_IT_SOURCE
-
-/**
-  * @}
-  */
-  
-  
-/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __OPAMP_CSR_OPAXPD                OPAMP_CSR_OPAXPD
-#define __OPAMP_CSR_S3SELX                OPAMP_CSR_S3SELX
-#define __OPAMP_CSR_S4SELX                OPAMP_CSR_S4SELX
-#define __OPAMP_CSR_S5SELX                OPAMP_CSR_S5SELX
-#define __OPAMP_CSR_S6SELX                OPAMP_CSR_S6SELX
-#define __OPAMP_CSR_OPAXCAL_L             OPAMP_CSR_OPAXCAL_L
-#define __OPAMP_CSR_OPAXCAL_H             OPAMP_CSR_OPAXCAL_H
-#define __OPAMP_CSR_OPAXLPM               OPAMP_CSR_OPAXLPM
-#define __OPAMP_CSR_ALL_SWITCHES          OPAMP_CSR_ALL_SWITCHES
-#define __OPAMP_CSR_ANAWSELX              OPAMP_CSR_ANAWSELX
-#define __OPAMP_CSR_OPAXCALOUT            OPAMP_CSR_OPAXCALOUT
-#define __OPAMP_OFFSET_TRIM_BITSPOSITION  OPAMP_OFFSET_TRIM_BITSPOSITION
-#define __OPAMP_OFFSET_TRIM_SET           OPAMP_OFFSET_TRIM_SET
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_PVD_EVENT_DISABLE                                  __HAL_PWR_PVD_EXTI_DISABLE_EVENT
-#define __HAL_PVD_EVENT_ENABLE                                   __HAL_PWR_PVD_EXTI_ENABLE_EVENT
-#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
-#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
-#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PVM_EVENT_DISABLE                                  __HAL_PWR_PVM_EVENT_DISABLE
-#define __HAL_PVM_EVENT_ENABLE                                   __HAL_PWR_PVM_EVENT_ENABLE
-#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
-#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
-#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
-#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
-#define __HAL_PWR_INTERNALWAKEUP_DISABLE                         HAL_PWREx_DisableInternalWakeUpLine
-#define __HAL_PWR_INTERNALWAKEUP_ENABLE                          HAL_PWREx_EnableInternalWakeUpLine
-#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE                    HAL_PWREx_DisablePullUpPullDownConfig
-#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE                     HAL_PWREx_EnablePullUpPullDownConfig
-#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER()                  do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
-#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE                         __HAL_PWR_PVD_EXTI_DISABLE_EVENT
-#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE                          __HAL_PWR_PVD_EXTI_ENABLE_EVENT
-#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE                __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
-#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE                 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE                 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
-#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE                  __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER              __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER               __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PWR_PVM_DISABLE()                                  do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
-#define __HAL_PWR_PVM_ENABLE()                                   do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
-#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE                  HAL_PWREx_DisableSRAM2ContentRetention
-#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE                   HAL_PWREx_EnableSRAM2ContentRetention
-#define __HAL_PWR_VDDIO2_DISABLE                                 HAL_PWREx_DisableVddIO2
-#define __HAL_PWR_VDDIO2_ENABLE                                  HAL_PWREx_EnableVddIO2
-#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER                 __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
-#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER           __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PWR_VDDUSB_DISABLE                                 HAL_PWREx_DisableVddUSB
-#define __HAL_PWR_VDDUSB_ENABLE                                  HAL_PWREx_EnableVddUSB
-
-#if defined (STM32F4)
-#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD)         __HAL_PWR_PVD_EXTI_ENABLE_IT()
-#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_DISABLE_IT()
-#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD)          __HAL_PWR_PVD_EXTI_GET_FLAG()   
-#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
-#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD)     __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
-#else
-#define __HAL_PVD_EXTI_CLEAR_FLAG                                __HAL_PWR_PVD_EXTI_CLEAR_FLAG
-#define __HAL_PVD_EXTI_DISABLE_IT                                __HAL_PWR_PVD_EXTI_DISABLE_IT
-#define __HAL_PVD_EXTI_ENABLE_IT                                 __HAL_PWR_PVD_EXTI_ENABLE_IT
-#define __HAL_PVD_EXTI_GENERATE_SWIT                             __HAL_PWR_PVD_EXTI_GENERATE_SWIT
-#define __HAL_PVD_EXTI_GET_FLAG                                  __HAL_PWR_PVD_EXTI_GET_FLAG 
-#endif /* STM32F4 */
-/**   
-  * @}
-  */  
-  
-  
-/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
-  * @{
-  */
-  
-#define RCC_StopWakeUpClock_MSI     RCC_STOP_WAKEUPCLOCK_MSI
-#define RCC_StopWakeUpClock_HSI     RCC_STOP_WAKEUPCLOCK_HSI
-
-#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
-#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
-
-#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
-#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
-#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
-#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
-#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
-#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
-#define __ADC1_CLK_DISABLE        __HAL_RCC_ADC1_CLK_DISABLE
-#define __ADC1_CLK_ENABLE         __HAL_RCC_ADC1_CLK_ENABLE
-#define __ADC1_FORCE_RESET        __HAL_RCC_ADC1_FORCE_RESET
-#define __ADC1_RELEASE_RESET      __HAL_RCC_ADC1_RELEASE_RESET
-#define __ADC1_CLK_SLEEP_ENABLE   __HAL_RCC_ADC1_CLK_SLEEP_ENABLE  
-#define __ADC1_CLK_SLEEP_DISABLE  __HAL_RCC_ADC1_CLK_SLEEP_DISABLE  
-#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
-#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
-#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
-#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
-#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
-#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
-#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
-#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
-#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
-#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
-#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
-#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
-#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
-#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
-#define __CRYP_CLK_SLEEP_ENABLE      __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
-#define __CRYP_CLK_SLEEP_DISABLE  __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
-#define __CRYP_CLK_ENABLE  __HAL_RCC_CRYP_CLK_ENABLE
-#define __CRYP_CLK_DISABLE  __HAL_RCC_CRYP_CLK_DISABLE
-#define __CRYP_FORCE_RESET  __HAL_RCC_CRYP_FORCE_RESET
-#define __CRYP_RELEASE_RESET  __HAL_RCC_CRYP_RELEASE_RESET
-#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
-#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
-#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
-#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
-#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
-#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
-#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
-#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
-#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
-#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
-#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
-#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
-#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
-#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
-#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
-#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
-#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
-#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
-#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
-#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
-#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
-#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
-#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
-#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
-#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
-#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
-#define __CAN_CLK_DISABLE         __HAL_RCC_CAN1_CLK_DISABLE
-#define __CAN_CLK_ENABLE          __HAL_RCC_CAN1_CLK_ENABLE
-#define __CAN_FORCE_RESET         __HAL_RCC_CAN1_FORCE_RESET
-#define __CAN_RELEASE_RESET       __HAL_RCC_CAN1_RELEASE_RESET
-#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
-#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
-#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
-#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
-#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
-#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
-#define __COMP_CLK_DISABLE        __HAL_RCC_COMP_CLK_DISABLE
-#define __COMP_CLK_ENABLE         __HAL_RCC_COMP_CLK_ENABLE
-#define __COMP_FORCE_RESET        __HAL_RCC_COMP_FORCE_RESET
-#define __COMP_RELEASE_RESET      __HAL_RCC_COMP_RELEASE_RESET
-#define __COMP_CLK_SLEEP_ENABLE   __HAL_RCC_COMP_CLK_SLEEP_ENABLE
-#define __COMP_CLK_SLEEP_DISABLE  __HAL_RCC_COMP_CLK_SLEEP_DISABLE
-#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
-#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
-#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
-#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
-#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
-#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
-#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
-#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
-#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
-#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
-#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
-#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
-#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
-#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
-#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
-#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
-#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
-#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
-#define __DBGMCU_CLK_ENABLE     __HAL_RCC_DBGMCU_CLK_ENABLE
-#define __DBGMCU_CLK_DISABLE     __HAL_RCC_DBGMCU_CLK_DISABLE
-#define __DBGMCU_FORCE_RESET    __HAL_RCC_DBGMCU_FORCE_RESET
-#define __DBGMCU_RELEASE_RESET  __HAL_RCC_DBGMCU_RELEASE_RESET
-#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
-#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
-#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
-#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
-#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
-#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
-#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
-#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
-#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
-#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
-#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
-#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
-#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
-#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
-#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
-#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
-#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
-#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
-#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
-#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
-#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
-#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
-#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
-#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
-#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
-#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
-#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
-#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
-#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
-#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
-#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
-#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
-#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
-#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
-#define __FLITF_CLK_DISABLE       __HAL_RCC_FLITF_CLK_DISABLE
-#define __FLITF_CLK_ENABLE        __HAL_RCC_FLITF_CLK_ENABLE
-#define __FLITF_FORCE_RESET       __HAL_RCC_FLITF_FORCE_RESET
-#define __FLITF_RELEASE_RESET     __HAL_RCC_FLITF_RELEASE_RESET
-#define __FLITF_CLK_SLEEP_ENABLE  __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
-#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
-#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
-#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
-#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
-#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
-#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
-#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
-#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
-#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
-#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
-#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
-#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
-#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
-#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
-#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
-#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
-#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
-#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
-#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
-#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
-#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
-#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
-#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
-#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
-#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
-#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
-#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
-#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
-#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
-#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
-#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
-#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
-#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
-#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
-#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
-#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
-#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
-#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
-#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
-#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
-#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
-#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
-#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
-#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
-#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
-#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
-#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
-#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
-#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
-#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
-#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
-#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
-#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
-#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
-#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
-#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
-#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
-#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
-#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
-#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
-#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
-#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
-#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
-#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
-#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
-#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
-#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
-#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
-#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
-#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
-#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
-#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
-#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
-#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
-#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
-#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
-#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
-#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
-#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
-#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
-#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
-#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
-#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
-#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
-#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
-#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
-#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
-#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
-#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
-#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
-#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
-#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
-#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
-#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
-#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
-#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
-#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
-#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
-#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
-#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
-#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
-#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
-#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
-#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
-#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
-#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
-#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
-#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
-#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
-#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
-#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
-#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
-#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
-#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
-#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
-#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
-#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
-#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
-#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
-#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
-#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
-#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
-#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
-#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
-#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
-#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
-#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
-#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
-#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
-#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
-#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
-#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
-#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
-#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
-#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
-#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
-#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
-#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
-#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
-#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
-#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
-#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
-#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
-#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
-#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
-#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
-#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
-#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
-#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
-#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
-#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
-#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
-#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
-#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
-#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
-#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
-#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
-#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
-#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
-#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
-#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
-#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
-#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
-#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
-#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
-#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
-#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
-#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
-#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
-#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
-#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
-#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
-#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
-#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
-#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
-#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
-#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
-#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
-#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
-#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
-#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
-#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
-#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
-#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
-#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
-#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
-#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
-#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
-#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
-#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
-#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
-#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
-#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
-#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
-#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
-#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
-#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
-#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
-#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
-#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
-#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
-#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
-#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
-#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
-#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
-#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
-#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
-#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
-#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
-#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
-#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
-#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
-#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
-#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
-#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
-#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
-#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
-#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
-#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
-#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
-#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
-#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
-#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
-#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
-#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
-#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
-#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
-#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
-#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
-#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
-#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
-#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
-#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
-#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
-#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
-#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
-#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
-#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
-#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
-#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
-#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
-#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
-#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
-#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
-#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
-#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
-#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
-#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
-#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
-#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
-#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
-#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
-#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
-#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
-#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
-#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
-#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
-#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
-#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
-#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
-#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
-#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
-#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
-#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
-#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
-#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
-#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
-#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
-#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
-#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
-#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
-#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
-#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
-#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
-#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
-#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
-#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
-#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
-#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
-#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
-#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
-#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
-#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
-#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
-#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
-#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
-#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
-#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
-#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
-#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
-#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
-#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
-#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
-#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
-#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
-#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
-#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
-#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
-#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
-#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
-#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
-#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
-#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
-#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
-#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
-#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
-#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
-#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
-#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
-#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
-#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
-#define __USART4_CLK_DISABLE        __HAL_RCC_UART4_CLK_DISABLE
-#define __USART4_CLK_ENABLE         __HAL_RCC_UART4_CLK_ENABLE
-#define __USART4_CLK_SLEEP_ENABLE   __HAL_RCC_UART4_CLK_SLEEP_ENABLE
-#define __USART4_CLK_SLEEP_DISABLE  __HAL_RCC_UART4_CLK_SLEEP_DISABLE 
-#define __USART4_FORCE_RESET        __HAL_RCC_UART4_FORCE_RESET
-#define __USART4_RELEASE_RESET      __HAL_RCC_UART4_RELEASE_RESET
-#define __USART5_CLK_DISABLE        __HAL_RCC_UART5_CLK_DISABLE
-#define __USART5_CLK_ENABLE         __HAL_RCC_UART5_CLK_ENABLE
-#define __USART5_CLK_SLEEP_ENABLE   __HAL_RCC_UART5_CLK_SLEEP_ENABLE
-#define __USART5_CLK_SLEEP_DISABLE  __HAL_RCC_UART5_CLK_SLEEP_DISABLE 
-#define __USART5_FORCE_RESET        __HAL_RCC_UART5_FORCE_RESET
-#define __USART5_RELEASE_RESET      __HAL_RCC_UART5_RELEASE_RESET
-#define __USART7_CLK_DISABLE        __HAL_RCC_UART7_CLK_DISABLE
-#define __USART7_CLK_ENABLE         __HAL_RCC_UART7_CLK_ENABLE
-#define __USART7_FORCE_RESET        __HAL_RCC_UART7_FORCE_RESET
-#define __USART7_RELEASE_RESET      __HAL_RCC_UART7_RELEASE_RESET
-#define __USART8_CLK_DISABLE        __HAL_RCC_UART8_CLK_DISABLE
-#define __USART8_CLK_ENABLE         __HAL_RCC_UART8_CLK_ENABLE
-#define __USART8_FORCE_RESET        __HAL_RCC_UART8_FORCE_RESET
-#define __USART8_RELEASE_RESET      __HAL_RCC_UART8_RELEASE_RESET
-#define __USB_CLK_DISABLE         __HAL_RCC_USB_CLK_DISABLE
-#define __USB_CLK_ENABLE          __HAL_RCC_USB_CLK_ENABLE
-#define __USB_FORCE_RESET         __HAL_RCC_USB_FORCE_RESET
-#define __USB_CLK_SLEEP_ENABLE    __HAL_RCC_USB_CLK_SLEEP_ENABLE
-#define __USB_CLK_SLEEP_DISABLE   __HAL_RCC_USB_CLK_SLEEP_DISABLE
-#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
-#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
-#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
-#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
-#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
-#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
-#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
-#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
-#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
-#define __TIM21_CLK_ENABLE   __HAL_RCC_TIM21_CLK_ENABLE
-#define __TIM21_CLK_DISABLE   __HAL_RCC_TIM21_CLK_DISABLE
-#define __TIM21_FORCE_RESET   __HAL_RCC_TIM21_FORCE_RESET
-#define __TIM21_RELEASE_RESET  __HAL_RCC_TIM21_RELEASE_RESET
-#define __TIM21_CLK_SLEEP_ENABLE   __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
-#define __TIM21_CLK_SLEEP_DISABLE   __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
-#define __TIM22_CLK_ENABLE   __HAL_RCC_TIM22_CLK_ENABLE
-#define __TIM22_CLK_DISABLE   __HAL_RCC_TIM22_CLK_DISABLE
-#define __TIM22_FORCE_RESET   __HAL_RCC_TIM22_FORCE_RESET
-#define __TIM22_RELEASE_RESET  __HAL_RCC_TIM22_RELEASE_RESET
-#define __TIM22_CLK_SLEEP_ENABLE   __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
-#define __TIM22_CLK_SLEEP_DISABLE   __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
-#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
-#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
-#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
-#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
-#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
-#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
-#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
-#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
-
-#define __USB_OTG_FS_FORCE_RESET  __HAL_RCC_USB_OTG_FS_FORCE_RESET
-#define __USB_OTG_FS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
-#define __USB_OTG_FS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
-#define __USB_OTG_FS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
-#define __USB_OTG_HS_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_DISABLE
-#define __USB_OTG_HS_CLK_ENABLE          __HAL_RCC_USB_OTG_HS_CLK_ENABLE
-#define __USB_OTG_HS_ULPI_CLK_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
-#define __USB_OTG_HS_ULPI_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE  
-#define __TIM9_CLK_SLEEP_ENABLE          __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
-#define __TIM9_CLK_SLEEP_DISABLE  __HAL_RCC_TIM9_CLK_SLEEP_DISABLE  
-#define __TIM10_CLK_SLEEP_ENABLE  __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
-#define __TIM10_CLK_SLEEP_DISABLE  __HAL_RCC_TIM10_CLK_SLEEP_DISABLE  
-#define __TIM11_CLK_SLEEP_ENABLE  __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
-#define __TIM11_CLK_SLEEP_DISABLE  __HAL_RCC_TIM11_CLK_SLEEP_DISABLE  
-#define __ETHMACPTP_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
-#define __ETHMACPTP_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
-#define __ETHMACPTP_CLK_ENABLE          __HAL_RCC_ETHMACPTP_CLK_ENABLE
-#define __ETHMACPTP_CLK_DISABLE          __HAL_RCC_ETHMACPTP_CLK_DISABLE  
-#define __HASH_CLK_ENABLE          __HAL_RCC_HASH_CLK_ENABLE
-#define __HASH_FORCE_RESET          __HAL_RCC_HASH_FORCE_RESET
-#define __HASH_RELEASE_RESET          __HAL_RCC_HASH_RELEASE_RESET
-#define __HASH_CLK_SLEEP_ENABLE          __HAL_RCC_HASH_CLK_SLEEP_ENABLE
-#define __HASH_CLK_SLEEP_DISABLE  __HAL_RCC_HASH_CLK_SLEEP_DISABLE
-#define __HASH_CLK_DISABLE            __HAL_RCC_HASH_CLK_DISABLE  
-#define __SPI5_CLK_ENABLE          __HAL_RCC_SPI5_CLK_ENABLE
-#define __SPI5_CLK_DISABLE              __HAL_RCC_SPI5_CLK_DISABLE
-#define __SPI5_FORCE_RESET          __HAL_RCC_SPI5_FORCE_RESET
-#define __SPI5_RELEASE_RESET          __HAL_RCC_SPI5_RELEASE_RESET
-#define __SPI5_CLK_SLEEP_ENABLE          __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
-#define __SPI5_CLK_SLEEP_DISABLE  __HAL_RCC_SPI5_CLK_SLEEP_DISABLE  
-#define __SPI6_CLK_ENABLE          __HAL_RCC_SPI6_CLK_ENABLE
-#define __SPI6_CLK_DISABLE          __HAL_RCC_SPI6_CLK_DISABLE
-#define __SPI6_FORCE_RESET          __HAL_RCC_SPI6_FORCE_RESET
-#define __SPI6_RELEASE_RESET         __HAL_RCC_SPI6_RELEASE_RESET
-#define __SPI6_CLK_SLEEP_ENABLE          __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
-#define __SPI6_CLK_SLEEP_DISABLE  __HAL_RCC_SPI6_CLK_SLEEP_DISABLE  
-#define __LTDC_CLK_ENABLE          __HAL_RCC_LTDC_CLK_ENABLE
-#define __LTDC_CLK_DISABLE          __HAL_RCC_LTDC_CLK_DISABLE
-#define __LTDC_FORCE_RESET          __HAL_RCC_LTDC_FORCE_RESET
-#define __LTDC_RELEASE_RESET          __HAL_RCC_LTDC_RELEASE_RESET
-#define __LTDC_CLK_SLEEP_ENABLE          __HAL_RCC_LTDC_CLK_SLEEP_ENABLE  
-#define __ETHMAC_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
-#define __ETHMAC_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE  
-#define __ETHMACTX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
-#define __ETHMACTX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE  
-#define __ETHMACRX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
-#define __ETHMACRX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE  
-#define __TIM12_CLK_SLEEP_ENABLE  __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
-#define __TIM12_CLK_SLEEP_DISABLE  __HAL_RCC_TIM12_CLK_SLEEP_DISABLE  
-#define __TIM13_CLK_SLEEP_ENABLE  __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
-#define __TIM13_CLK_SLEEP_DISABLE  __HAL_RCC_TIM13_CLK_SLEEP_DISABLE  
-#define __TIM14_CLK_SLEEP_ENABLE  __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
-#define __TIM14_CLK_SLEEP_DISABLE  __HAL_RCC_TIM14_CLK_SLEEP_DISABLE  
-#define __BKPSRAM_CLK_ENABLE          __HAL_RCC_BKPSRAM_CLK_ENABLE
-#define __BKPSRAM_CLK_DISABLE          __HAL_RCC_BKPSRAM_CLK_DISABLE
-#define __BKPSRAM_CLK_SLEEP_ENABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
-#define __BKPSRAM_CLK_SLEEP_DISABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE  
-#define __CCMDATARAMEN_CLK_ENABLE  __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
-#define __CCMDATARAMEN_CLK_DISABLE  __HAL_RCC_CCMDATARAMEN_CLK_DISABLE  
-#define __USART6_CLK_ENABLE          __HAL_RCC_USART6_CLK_ENABLE
-#define __USART6_CLK_DISABLE          __HAL_RCC_USART6_CLK_DISABLE
-#define __USART6_FORCE_RESET        __HAL_RCC_USART6_FORCE_RESET
-#define __USART6_RELEASE_RESET        __HAL_RCC_USART6_RELEASE_RESET
-#define __USART6_CLK_SLEEP_ENABLE  __HAL_RCC_USART6_CLK_SLEEP_ENABLE
-#define __USART6_CLK_SLEEP_DISABLE  __HAL_RCC_USART6_CLK_SLEEP_DISABLE  
-#define __SPI4_CLK_ENABLE          __HAL_RCC_SPI4_CLK_ENABLE
-#define __SPI4_CLK_DISABLE          __HAL_RCC_SPI4_CLK_DISABLE
-#define __SPI4_FORCE_RESET          __HAL_RCC_SPI4_FORCE_RESET
-#define __SPI4_RELEASE_RESET        __HAL_RCC_SPI4_RELEASE_RESET
-#define __SPI4_CLK_SLEEP_ENABLE   __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
-#define __SPI4_CLK_SLEEP_DISABLE  __HAL_RCC_SPI4_CLK_SLEEP_DISABLE  
-#define __GPIOI_CLK_ENABLE          __HAL_RCC_GPIOI_CLK_ENABLE
-#define __GPIOI_CLK_DISABLE          __HAL_RCC_GPIOI_CLK_DISABLE
-#define __GPIOI_FORCE_RESET          __HAL_RCC_GPIOI_FORCE_RESET
-#define __GPIOI_RELEASE_RESET          __HAL_RCC_GPIOI_RELEASE_RESET
-#define __GPIOI_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
-#define __GPIOI_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE  
-#define __GPIOJ_CLK_ENABLE          __HAL_RCC_GPIOJ_CLK_ENABLE
-#define __GPIOJ_CLK_DISABLE          __HAL_RCC_GPIOJ_CLK_DISABLE
-#define __GPIOJ_FORCE_RESET         __HAL_RCC_GPIOJ_FORCE_RESET
-#define __GPIOJ_RELEASE_RESET          __HAL_RCC_GPIOJ_RELEASE_RESET
-#define __GPIOJ_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
-#define __GPIOJ_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE  
-#define __GPIOK_CLK_ENABLE          __HAL_RCC_GPIOK_CLK_ENABLE
-#define __GPIOK_CLK_DISABLE          __HAL_RCC_GPIOK_CLK_DISABLE
-#define __GPIOK_RELEASE_RESET          __HAL_RCC_GPIOK_RELEASE_RESET
-#define __GPIOK_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
-#define __GPIOK_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE  
-#define __ETH_CLK_ENABLE          __HAL_RCC_ETH_CLK_ENABLE
-#define __ETH_CLK_DISABLE          __HAL_RCC_ETH_CLK_DISABLE  
-#define __DCMI_CLK_ENABLE          __HAL_RCC_DCMI_CLK_ENABLE
-#define __DCMI_CLK_DISABLE          __HAL_RCC_DCMI_CLK_DISABLE
-#define __DCMI_FORCE_RESET          __HAL_RCC_DCMI_FORCE_RESET
-#define __DCMI_RELEASE_RESET          __HAL_RCC_DCMI_RELEASE_RESET
-#define __DCMI_CLK_SLEEP_ENABLE   __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
-#define __DCMI_CLK_SLEEP_DISABLE  __HAL_RCC_DCMI_CLK_SLEEP_DISABLE  
-#define __UART7_CLK_ENABLE          __HAL_RCC_UART7_CLK_ENABLE
-#define __UART7_CLK_DISABLE          __HAL_RCC_UART7_CLK_DISABLE
-#define __UART7_RELEASE_RESET       __HAL_RCC_UART7_RELEASE_RESET
-#define __UART7_FORCE_RESET       __HAL_RCC_UART7_FORCE_RESET
-#define __UART7_CLK_SLEEP_ENABLE  __HAL_RCC_UART7_CLK_SLEEP_ENABLE
-#define __UART7_CLK_SLEEP_DISABLE  __HAL_RCC_UART7_CLK_SLEEP_DISABLE  
-#define __UART8_CLK_ENABLE          __HAL_RCC_UART8_CLK_ENABLE
-#define __UART8_CLK_DISABLE          __HAL_RCC_UART8_CLK_DISABLE
-#define __UART8_FORCE_RESET          __HAL_RCC_UART8_FORCE_RESET
-#define __UART8_RELEASE_RESET          __HAL_RCC_UART8_RELEASE_RESET
-#define __UART8_CLK_SLEEP_ENABLE  __HAL_RCC_UART8_CLK_SLEEP_ENABLE
-#define __UART8_CLK_SLEEP_DISABLE  __HAL_RCC_UART8_CLK_SLEEP_DISABLE  
-#define __OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
-#define __OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
-#define __OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
-#define __OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET  
-#define __OTGHSULPI_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
-#define __OTGHSULPI_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
-#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
-#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
-#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
-#define __HAL_RCC_OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
-#define __HAL_RCC_OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET  
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE      __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE     __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE 
-#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED  __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED   
-#define __CRYP_FORCE_RESET             __HAL_RCC_CRYP_FORCE_RESET  
-#define __SRAM3_CLK_SLEEP_ENABLE       __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE  
-#define __CAN2_CLK_SLEEP_ENABLE        __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
-#define __CAN2_CLK_SLEEP_DISABLE       __HAL_RCC_CAN2_CLK_SLEEP_DISABLE  
-#define __DAC_CLK_SLEEP_ENABLE         __HAL_RCC_DAC_CLK_SLEEP_ENABLE
-#define __DAC_CLK_SLEEP_DISABLE        __HAL_RCC_DAC_CLK_SLEEP_DISABLE  
-#define __ADC2_CLK_SLEEP_ENABLE        __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
-#define __ADC2_CLK_SLEEP_DISABLE       __HAL_RCC_ADC2_CLK_SLEEP_DISABLE  
-#define __ADC3_CLK_SLEEP_ENABLE        __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
-#define __ADC3_CLK_SLEEP_DISABLE       __HAL_RCC_ADC3_CLK_SLEEP_DISABLE  
-#define __FSMC_FORCE_RESET             __HAL_RCC_FSMC_FORCE_RESET
-#define __FSMC_RELEASE_RESET           __HAL_RCC_FSMC_RELEASE_RESET
-#define __FSMC_CLK_SLEEP_ENABLE        __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
-#define __FSMC_CLK_SLEEP_DISABLE       __HAL_RCC_FSMC_CLK_SLEEP_DISABLE  
-#define __SDIO_FORCE_RESET             __HAL_RCC_SDIO_FORCE_RESET
-#define __SDIO_RELEASE_RESET           __HAL_RCC_SDIO_RELEASE_RESET
-#define __SDIO_CLK_SLEEP_DISABLE       __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
-#define __SDIO_CLK_SLEEP_ENABLE        __HAL_RCC_SDIO_CLK_SLEEP_ENABLE  
-#define __DMA2D_CLK_ENABLE             __HAL_RCC_DMA2D_CLK_ENABLE
-#define __DMA2D_CLK_DISABLE            __HAL_RCC_DMA2D_CLK_DISABLE
-#define __DMA2D_FORCE_RESET            __HAL_RCC_DMA2D_FORCE_RESET
-#define __DMA2D_RELEASE_RESET          __HAL_RCC_DMA2D_RELEASE_RESET
-#define __DMA2D_CLK_SLEEP_ENABLE       __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
-#define __DMA2D_CLK_SLEEP_DISABLE      __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
-
-/* alias define maintained for legacy */
-#define __HAL_RCC_OTGFS_FORCE_RESET    __HAL_RCC_USB_OTG_FS_FORCE_RESET
-#define __HAL_RCC_OTGFS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
-
-#define __ADC12_CLK_ENABLE          __HAL_RCC_ADC12_CLK_ENABLE
-#define __ADC12_CLK_DISABLE         __HAL_RCC_ADC12_CLK_DISABLE
-#define __ADC34_CLK_ENABLE          __HAL_RCC_ADC34_CLK_ENABLE
-#define __ADC34_CLK_DISABLE         __HAL_RCC_ADC34_CLK_DISABLE
-#define __ADC12_CLK_ENABLE          __HAL_RCC_ADC12_CLK_ENABLE
-#define __ADC12_CLK_DISABLE         __HAL_RCC_ADC12_CLK_DISABLE
-#define __DAC2_CLK_ENABLE           __HAL_RCC_DAC2_CLK_ENABLE
-#define __DAC2_CLK_DISABLE          __HAL_RCC_DAC2_CLK_DISABLE
-#define __TIM18_CLK_ENABLE          __HAL_RCC_TIM18_CLK_ENABLE
-#define __TIM18_CLK_DISABLE         __HAL_RCC_TIM18_CLK_DISABLE
-#define __TIM19_CLK_ENABLE          __HAL_RCC_TIM19_CLK_ENABLE
-#define __TIM19_CLK_DISABLE         __HAL_RCC_TIM19_CLK_DISABLE
-#define __TIM20_CLK_ENABLE          __HAL_RCC_TIM20_CLK_ENABLE
-#define __TIM20_CLK_DISABLE         __HAL_RCC_TIM20_CLK_DISABLE
-#define __HRTIM1_CLK_ENABLE         __HAL_RCC_HRTIM1_CLK_ENABLE
-#define __HRTIM1_CLK_DISABLE        __HAL_RCC_HRTIM1_CLK_DISABLE
-#define __SDADC1_CLK_ENABLE         __HAL_RCC_SDADC1_CLK_ENABLE
-#define __SDADC2_CLK_ENABLE         __HAL_RCC_SDADC2_CLK_ENABLE
-#define __SDADC3_CLK_ENABLE         __HAL_RCC_SDADC3_CLK_ENABLE
-#define __SDADC1_CLK_DISABLE        __HAL_RCC_SDADC1_CLK_DISABLE
-#define __SDADC2_CLK_DISABLE        __HAL_RCC_SDADC2_CLK_DISABLE
-#define __SDADC3_CLK_DISABLE        __HAL_RCC_SDADC3_CLK_DISABLE
-
-#define __ADC12_FORCE_RESET         __HAL_RCC_ADC12_FORCE_RESET
-#define __ADC12_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET
-#define __ADC34_FORCE_RESET         __HAL_RCC_ADC34_FORCE_RESET
-#define __ADC34_RELEASE_RESET       __HAL_RCC_ADC34_RELEASE_RESET
-#define __ADC12_FORCE_RESET         __HAL_RCC_ADC12_FORCE_RESET
-#define __ADC12_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET
-#define __DAC2_FORCE_RESET          __HAL_RCC_DAC2_FORCE_RESET
-#define __DAC2_RELEASE_RESET        __HAL_RCC_DAC2_RELEASE_RESET
-#define __TIM18_FORCE_RESET         __HAL_RCC_TIM18_FORCE_RESET
-#define __TIM18_RELEASE_RESET       __HAL_RCC_TIM18_RELEASE_RESET
-#define __TIM19_FORCE_RESET         __HAL_RCC_TIM19_FORCE_RESET
-#define __TIM19_RELEASE_RESET       __HAL_RCC_TIM19_RELEASE_RESET
-#define __TIM20_FORCE_RESET         __HAL_RCC_TIM20_FORCE_RESET
-#define __TIM20_RELEASE_RESET       __HAL_RCC_TIM20_RELEASE_RESET
-#define __HRTIM1_FORCE_RESET        __HAL_RCC_HRTIM1_FORCE_RESET
-#define __HRTIM1_RELEASE_RESET      __HAL_RCC_HRTIM1_RELEASE_RESET
-#define __SDADC1_FORCE_RESET        __HAL_RCC_SDADC1_FORCE_RESET
-#define __SDADC2_FORCE_RESET        __HAL_RCC_SDADC2_FORCE_RESET
-#define __SDADC3_FORCE_RESET        __HAL_RCC_SDADC3_FORCE_RESET
-#define __SDADC1_RELEASE_RESET      __HAL_RCC_SDADC1_RELEASE_RESET
-#define __SDADC2_RELEASE_RESET      __HAL_RCC_SDADC2_RELEASE_RESET
-#define __SDADC3_RELEASE_RESET      __HAL_RCC_SDADC3_RELEASE_RESET
-
-#define __ADC1_IS_CLK_ENABLED       __HAL_RCC_ADC1_IS_CLK_ENABLED
-#define __ADC1_IS_CLK_DISABLED      __HAL_RCC_ADC1_IS_CLK_DISABLED
-#define __ADC12_IS_CLK_ENABLED      __HAL_RCC_ADC12_IS_CLK_ENABLED
-#define __ADC12_IS_CLK_DISABLED     __HAL_RCC_ADC12_IS_CLK_DISABLED
-#define __ADC34_IS_CLK_ENABLED      __HAL_RCC_ADC34_IS_CLK_ENABLED
-#define __ADC34_IS_CLK_DISABLED     __HAL_RCC_ADC34_IS_CLK_DISABLED
-#define __CEC_IS_CLK_ENABLED        __HAL_RCC_CEC_IS_CLK_ENABLED
-#define __CEC_IS_CLK_DISABLED       __HAL_RCC_CEC_IS_CLK_DISABLED
-#define __CRC_IS_CLK_ENABLED        __HAL_RCC_CRC_IS_CLK_ENABLED
-#define __CRC_IS_CLK_DISABLED       __HAL_RCC_CRC_IS_CLK_DISABLED
-#define __DAC1_IS_CLK_ENABLED       __HAL_RCC_DAC1_IS_CLK_ENABLED
-#define __DAC1_IS_CLK_DISABLED      __HAL_RCC_DAC1_IS_CLK_DISABLED
-#define __DAC2_IS_CLK_ENABLED       __HAL_RCC_DAC2_IS_CLK_ENABLED
-#define __DAC2_IS_CLK_DISABLED      __HAL_RCC_DAC2_IS_CLK_DISABLED
-#define __DMA1_IS_CLK_ENABLED       __HAL_RCC_DMA1_IS_CLK_ENABLED
-#define __DMA1_IS_CLK_DISABLED      __HAL_RCC_DMA1_IS_CLK_DISABLED
-#define __DMA2_IS_CLK_ENABLED       __HAL_RCC_DMA2_IS_CLK_ENABLED
-#define __DMA2_IS_CLK_DISABLED      __HAL_RCC_DMA2_IS_CLK_DISABLED
-#define __FLITF_IS_CLK_ENABLED      __HAL_RCC_FLITF_IS_CLK_ENABLED
-#define __FLITF_IS_CLK_DISABLED     __HAL_RCC_FLITF_IS_CLK_DISABLED
-#define __FMC_IS_CLK_ENABLED        __HAL_RCC_FMC_IS_CLK_ENABLED
-#define __FMC_IS_CLK_DISABLED       __HAL_RCC_FMC_IS_CLK_DISABLED
-#define __GPIOA_IS_CLK_ENABLED      __HAL_RCC_GPIOA_IS_CLK_ENABLED
-#define __GPIOA_IS_CLK_DISABLED     __HAL_RCC_GPIOA_IS_CLK_DISABLED
-#define __GPIOB_IS_CLK_ENABLED      __HAL_RCC_GPIOB_IS_CLK_ENABLED
-#define __GPIOB_IS_CLK_DISABLED     __HAL_RCC_GPIOB_IS_CLK_DISABLED
-#define __GPIOC_IS_CLK_ENABLED      __HAL_RCC_GPIOC_IS_CLK_ENABLED
-#define __GPIOC_IS_CLK_DISABLED     __HAL_RCC_GPIOC_IS_CLK_DISABLED
-#define __GPIOD_IS_CLK_ENABLED      __HAL_RCC_GPIOD_IS_CLK_ENABLED
-#define __GPIOD_IS_CLK_DISABLED     __HAL_RCC_GPIOD_IS_CLK_DISABLED
-#define __GPIOE_IS_CLK_ENABLED      __HAL_RCC_GPIOE_IS_CLK_ENABLED
-#define __GPIOE_IS_CLK_DISABLED     __HAL_RCC_GPIOE_IS_CLK_DISABLED
-#define __GPIOF_IS_CLK_ENABLED      __HAL_RCC_GPIOF_IS_CLK_ENABLED
-#define __GPIOF_IS_CLK_DISABLED     __HAL_RCC_GPIOF_IS_CLK_DISABLED
-#define __GPIOG_IS_CLK_ENABLED      __HAL_RCC_GPIOG_IS_CLK_ENABLED
-#define __GPIOG_IS_CLK_DISABLED     __HAL_RCC_GPIOG_IS_CLK_DISABLED
-#define __GPIOH_IS_CLK_ENABLED      __HAL_RCC_GPIOH_IS_CLK_ENABLED
-#define __GPIOH_IS_CLK_DISABLED     __HAL_RCC_GPIOH_IS_CLK_DISABLED
-#define __HRTIM1_IS_CLK_ENABLED     __HAL_RCC_HRTIM1_IS_CLK_ENABLED
-#define __HRTIM1_IS_CLK_DISABLED    __HAL_RCC_HRTIM1_IS_CLK_DISABLED
-#define __I2C1_IS_CLK_ENABLED       __HAL_RCC_I2C1_IS_CLK_ENABLED
-#define __I2C1_IS_CLK_DISABLED      __HAL_RCC_I2C1_IS_CLK_DISABLED
-#define __I2C2_IS_CLK_ENABLED       __HAL_RCC_I2C2_IS_CLK_ENABLED
-#define __I2C2_IS_CLK_DISABLED      __HAL_RCC_I2C2_IS_CLK_DISABLED
-#define __I2C3_IS_CLK_ENABLED       __HAL_RCC_I2C3_IS_CLK_ENABLED
-#define __I2C3_IS_CLK_DISABLED      __HAL_RCC_I2C3_IS_CLK_DISABLED
-#define __PWR_IS_CLK_ENABLED        __HAL_RCC_PWR_IS_CLK_ENABLED
-#define __PWR_IS_CLK_DISABLED       __HAL_RCC_PWR_IS_CLK_DISABLED
-#define __SYSCFG_IS_CLK_ENABLED     __HAL_RCC_SYSCFG_IS_CLK_ENABLED
-#define __SYSCFG_IS_CLK_DISABLED    __HAL_RCC_SYSCFG_IS_CLK_DISABLED
-#define __SPI1_IS_CLK_ENABLED       __HAL_RCC_SPI1_IS_CLK_ENABLED
-#define __SPI1_IS_CLK_DISABLED      __HAL_RCC_SPI1_IS_CLK_DISABLED
-#define __SPI2_IS_CLK_ENABLED       __HAL_RCC_SPI2_IS_CLK_ENABLED
-#define __SPI2_IS_CLK_DISABLED      __HAL_RCC_SPI2_IS_CLK_DISABLED
-#define __SPI3_IS_CLK_ENABLED       __HAL_RCC_SPI3_IS_CLK_ENABLED
-#define __SPI3_IS_CLK_DISABLED      __HAL_RCC_SPI3_IS_CLK_DISABLED
-#define __SPI4_IS_CLK_ENABLED       __HAL_RCC_SPI4_IS_CLK_ENABLED
-#define __SPI4_IS_CLK_DISABLED      __HAL_RCC_SPI4_IS_CLK_DISABLED
-#define __SDADC1_IS_CLK_ENABLED     __HAL_RCC_SDADC1_IS_CLK_ENABLED
-#define __SDADC1_IS_CLK_DISABLED    __HAL_RCC_SDADC1_IS_CLK_DISABLED
-#define __SDADC2_IS_CLK_ENABLED     __HAL_RCC_SDADC2_IS_CLK_ENABLED
-#define __SDADC2_IS_CLK_DISABLED    __HAL_RCC_SDADC2_IS_CLK_DISABLED
-#define __SDADC3_IS_CLK_ENABLED     __HAL_RCC_SDADC3_IS_CLK_ENABLED
-#define __SDADC3_IS_CLK_DISABLED    __HAL_RCC_SDADC3_IS_CLK_DISABLED
-#define __SRAM_IS_CLK_ENABLED       __HAL_RCC_SRAM_IS_CLK_ENABLED
-#define __SRAM_IS_CLK_DISABLED      __HAL_RCC_SRAM_IS_CLK_DISABLED
-#define __TIM1_IS_CLK_ENABLED       __HAL_RCC_TIM1_IS_CLK_ENABLED
-#define __TIM1_IS_CLK_DISABLED      __HAL_RCC_TIM1_IS_CLK_DISABLED
-#define __TIM2_IS_CLK_ENABLED       __HAL_RCC_TIM2_IS_CLK_ENABLED
-#define __TIM2_IS_CLK_DISABLED      __HAL_RCC_TIM2_IS_CLK_DISABLED
-#define __TIM3_IS_CLK_ENABLED       __HAL_RCC_TIM3_IS_CLK_ENABLED
-#define __TIM3_IS_CLK_DISABLED      __HAL_RCC_TIM3_IS_CLK_DISABLED
-#define __TIM4_IS_CLK_ENABLED       __HAL_RCC_TIM4_IS_CLK_ENABLED
-#define __TIM4_IS_CLK_DISABLED      __HAL_RCC_TIM4_IS_CLK_DISABLED
-#define __TIM5_IS_CLK_ENABLED       __HAL_RCC_TIM5_IS_CLK_ENABLED
-#define __TIM5_IS_CLK_DISABLED      __HAL_RCC_TIM5_IS_CLK_DISABLED
-#define __TIM6_IS_CLK_ENABLED       __HAL_RCC_TIM6_IS_CLK_ENABLED
-#define __TIM6_IS_CLK_DISABLED      __HAL_RCC_TIM6_IS_CLK_DISABLED
-#define __TIM7_IS_CLK_ENABLED       __HAL_RCC_TIM7_IS_CLK_ENABLED
-#define __TIM7_IS_CLK_DISABLED      __HAL_RCC_TIM7_IS_CLK_DISABLED
-#define __TIM8_IS_CLK_ENABLED       __HAL_RCC_TIM8_IS_CLK_ENABLED
-#define __TIM8_IS_CLK_DISABLED      __HAL_RCC_TIM8_IS_CLK_DISABLED
-#define __TIM12_IS_CLK_ENABLED      __HAL_RCC_TIM12_IS_CLK_ENABLED
-#define __TIM12_IS_CLK_DISABLED     __HAL_RCC_TIM12_IS_CLK_DISABLED
-#define __TIM13_IS_CLK_ENABLED      __HAL_RCC_TIM13_IS_CLK_ENABLED
-#define __TIM13_IS_CLK_DISABLED     __HAL_RCC_TIM13_IS_CLK_DISABLED
-#define __TIM14_IS_CLK_ENABLED      __HAL_RCC_TIM14_IS_CLK_ENABLED
-#define __TIM14_IS_CLK_DISABLED     __HAL_RCC_TIM14_IS_CLK_DISABLED
-#define __TIM15_IS_CLK_ENABLED      __HAL_RCC_TIM15_IS_CLK_ENABLED
-#define __TIM15_IS_CLK_DISABLED     __HAL_RCC_TIM15_IS_CLK_DISABLED
-#define __TIM16_IS_CLK_ENABLED      __HAL_RCC_TIM16_IS_CLK_ENABLED
-#define __TIM16_IS_CLK_DISABLED     __HAL_RCC_TIM16_IS_CLK_DISABLED
-#define __TIM17_IS_CLK_ENABLED      __HAL_RCC_TIM17_IS_CLK_ENABLED
-#define __TIM17_IS_CLK_DISABLED     __HAL_RCC_TIM17_IS_CLK_DISABLED
-#define __TIM18_IS_CLK_ENABLED      __HAL_RCC_TIM18_IS_CLK_ENABLED
-#define __TIM18_IS_CLK_DISABLED     __HAL_RCC_TIM18_IS_CLK_DISABLED
-#define __TIM19_IS_CLK_ENABLED      __HAL_RCC_TIM19_IS_CLK_ENABLED
-#define __TIM19_IS_CLK_DISABLED     __HAL_RCC_TIM19_IS_CLK_DISABLED
-#define __TIM20_IS_CLK_ENABLED      __HAL_RCC_TIM20_IS_CLK_ENABLED
-#define __TIM20_IS_CLK_DISABLED     __HAL_RCC_TIM20_IS_CLK_DISABLED
-#define __TSC_IS_CLK_ENABLED        __HAL_RCC_TSC_IS_CLK_ENABLED
-#define __TSC_IS_CLK_DISABLED       __HAL_RCC_TSC_IS_CLK_DISABLED
-#define __UART4_IS_CLK_ENABLED      __HAL_RCC_UART4_IS_CLK_ENABLED
-#define __UART4_IS_CLK_DISABLED     __HAL_RCC_UART4_IS_CLK_DISABLED
-#define __UART5_IS_CLK_ENABLED      __HAL_RCC_UART5_IS_CLK_ENABLED
-#define __UART5_IS_CLK_DISABLED     __HAL_RCC_UART5_IS_CLK_DISABLED
-#define __USART1_IS_CLK_ENABLED     __HAL_RCC_USART1_IS_CLK_ENABLED
-#define __USART1_IS_CLK_DISABLED    __HAL_RCC_USART1_IS_CLK_DISABLED
-#define __USART2_IS_CLK_ENABLED     __HAL_RCC_USART2_IS_CLK_ENABLED
-#define __USART2_IS_CLK_DISABLED    __HAL_RCC_USART2_IS_CLK_DISABLED
-#define __USART3_IS_CLK_ENABLED     __HAL_RCC_USART3_IS_CLK_ENABLED
-#define __USART3_IS_CLK_DISABLED    __HAL_RCC_USART3_IS_CLK_DISABLED
-#define __USB_IS_CLK_ENABLED        __HAL_RCC_USB_IS_CLK_ENABLED
-#define __USB_IS_CLK_DISABLED       __HAL_RCC_USB_IS_CLK_DISABLED
-#define __WWDG_IS_CLK_ENABLED       __HAL_RCC_WWDG_IS_CLK_ENABLED
-#define __WWDG_IS_CLK_DISABLED      __HAL_RCC_WWDG_IS_CLK_DISABLED
-
-#if defined(STM32F4)
-#define __HAL_RCC_SDMMC1_FORCE_RESET       __HAL_RCC_SDIO_FORCE_RESET
-#define __HAL_RCC_SDMMC1_RELEASE_RESET     __HAL_RCC_SDIO_RELEASE_RESET
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE  __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
-#define __HAL_RCC_SDMMC1_CLK_ENABLE        __HAL_RCC_SDIO_CLK_ENABLE
-#define __HAL_RCC_SDMMC1_CLK_DISABLE       __HAL_RCC_SDIO_CLK_DISABLE
-#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED    __HAL_RCC_SDIO_IS_CLK_ENABLED
-#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED   __HAL_RCC_SDIO_IS_CLK_DISABLED
-#define Sdmmc1ClockSelection               SdioClockSelection
-#define RCC_PERIPHCLK_SDMMC1               RCC_PERIPHCLK_SDIO
-#define RCC_SDMMC1CLKSOURCE_CLK48          RCC_SDIOCLKSOURCE_CK48
-#define RCC_SDMMC1CLKSOURCE_SYSCLK         RCC_SDIOCLKSOURCE_SYSCLK
-#define __HAL_RCC_SDMMC1_CONFIG            __HAL_RCC_SDIO_CONFIG
-#define __HAL_RCC_GET_SDMMC1_SOURCE        __HAL_RCC_GET_SDIO_SOURCE
-#endif
-
-#if defined(STM32F7) || defined(STM32L4)
-#define __HAL_RCC_SDIO_FORCE_RESET         __HAL_RCC_SDMMC1_FORCE_RESET
-#define __HAL_RCC_SDIO_RELEASE_RESET       __HAL_RCC_SDMMC1_RELEASE_RESET
-#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE    __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
-#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE   __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
-#define __HAL_RCC_SDIO_CLK_ENABLE          __HAL_RCC_SDMMC1_CLK_ENABLE
-#define __HAL_RCC_SDIO_CLK_DISABLE         __HAL_RCC_SDMMC1_CLK_DISABLE
-#define __HAL_RCC_SDIO_IS_CLK_ENABLED      __HAL_RCC_SDMMC1_IS_CLK_ENABLED
-#define __HAL_RCC_SDIO_IS_CLK_DISABLED     __HAL_RCC_SDMMC1_IS_CLK_DISABLED
-#define SdioClockSelection                 Sdmmc1ClockSelection
-#define RCC_PERIPHCLK_SDIO                 RCC_PERIPHCLK_SDMMC1
-#define __HAL_RCC_SDIO_CONFIG              __HAL_RCC_SDMMC1_CONFIG
-#define __HAL_RCC_GET_SDIO_SOURCE          __HAL_RCC_GET_SDMMC1_SOURCE	
-#endif
-
-#if defined(STM32F7)
-#define RCC_SDIOCLKSOURCE_CLK48             RCC_SDMMC1CLKSOURCE_CLK48
-#define RCC_SDIOCLKSOURCE_SYSCLK           RCC_SDMMC1CLKSOURCE_SYSCLK
-#endif
-
-#define __HAL_RCC_I2SCLK            __HAL_RCC_I2S_CONFIG
-#define __HAL_RCC_I2SCLK_CONFIG     __HAL_RCC_I2S_CONFIG
-
-#define __RCC_PLLSRC                RCC_GET_PLL_OSCSOURCE
-
-#define IS_RCC_MSIRANGE             IS_RCC_MSI_CLOCK_RANGE
-#define IS_RCC_RTCCLK_SOURCE        IS_RCC_RTCCLKSOURCE
-#define IS_RCC_SYSCLK_DIV           IS_RCC_HCLK
-#define IS_RCC_HCLK_DIV             IS_RCC_PCLK
-#define IS_RCC_PERIPHCLK            IS_RCC_PERIPHCLOCK
-
-#define RCC_IT_HSI14                RCC_IT_HSI14RDY
-
-#if defined(STM32L0)
-#define RCC_IT_LSECSS              RCC_IT_CSSLSE 
-#define RCC_IT_CSS                 RCC_IT_CSSHSE
-#endif
-
-#define IS_RCC_MCOSOURCE            IS_RCC_MCO1SOURCE
-#define __HAL_RCC_MCO_CONFIG        __HAL_RCC_MCO1_CONFIG
-#define RCC_MCO_NODIV               RCC_MCODIV_1
-#define RCC_MCO_DIV1                RCC_MCODIV_1
-#define RCC_MCO_DIV2                RCC_MCODIV_2
-#define RCC_MCO_DIV4                RCC_MCODIV_4
-#define RCC_MCO_DIV8                RCC_MCODIV_8
-#define RCC_MCO_DIV16               RCC_MCODIV_16
-#define RCC_MCO_DIV32               RCC_MCODIV_32
-#define RCC_MCO_DIV64               RCC_MCODIV_64
-#define RCC_MCO_DIV128              RCC_MCODIV_128
-#define RCC_MCOSOURCE_NONE          RCC_MCO1SOURCE_NOCLOCK
-#define RCC_MCOSOURCE_LSI           RCC_MCO1SOURCE_LSI
-#define RCC_MCOSOURCE_LSE           RCC_MCO1SOURCE_LSE
-#define RCC_MCOSOURCE_SYSCLK        RCC_MCO1SOURCE_SYSCLK
-#define RCC_MCOSOURCE_HSI           RCC_MCO1SOURCE_HSI
-#define RCC_MCOSOURCE_HSI14         RCC_MCO1SOURCE_HSI14
-#define RCC_MCOSOURCE_HSI48         RCC_MCO1SOURCE_HSI48
-#define RCC_MCOSOURCE_HSE           RCC_MCO1SOURCE_HSE
-#define RCC_MCOSOURCE_PLLCLK_DIV1   RCC_MCO1SOURCE_PLLCLK
-#define RCC_MCOSOURCE_PLLCLK_NODIV  RCC_MCO1SOURCE_PLLCLK
-#define RCC_MCOSOURCE_PLLCLK_DIV2   RCC_MCO1SOURCE_PLLCLK_DIV2
-
-#define RCC_RTCCLKSOURCE_NONE       RCC_RTCCLKSOURCE_NO_CLK
-
-#define RCC_USBCLK_PLLSAI1          RCC_USBCLKSOURCE_PLLSAI1
-#define RCC_USBCLK_PLL              RCC_USBCLKSOURCE_PLL
-#define RCC_USBCLK_MSI              RCC_USBCLKSOURCE_MSI
-#define RCC_USBCLKSOURCE_PLLCLK     RCC_USBCLKSOURCE_PLL
-#define RCC_USBPLLCLK_DIV1          RCC_USBCLKSOURCE_PLL
-#define RCC_USBPLLCLK_DIV1_5        RCC_USBCLKSOURCE_PLL_DIV1_5
-#define RCC_USBPLLCLK_DIV2          RCC_USBCLKSOURCE_PLL_DIV2
-#define RCC_USBPLLCLK_DIV3          RCC_USBCLKSOURCE_PLL_DIV3
-
-#define HSION_BitNumber        RCC_HSION_BIT_NUMBER
-#define HSION_BITNUMBER        RCC_HSION_BIT_NUMBER
-#define HSEON_BitNumber        RCC_HSEON_BIT_NUMBER
-#define HSEON_BITNUMBER        RCC_HSEON_BIT_NUMBER
-#define MSION_BITNUMBER        RCC_MSION_BIT_NUMBER
-#define CSSON_BitNumber        RCC_CSSON_BIT_NUMBER
-#define CSSON_BITNUMBER        RCC_CSSON_BIT_NUMBER
-#define PLLON_BitNumber        RCC_PLLON_BIT_NUMBER
-#define PLLON_BITNUMBER        RCC_PLLON_BIT_NUMBER
-#define PLLI2SON_BitNumber     RCC_PLLI2SON_BIT_NUMBER
-#define I2SSRC_BitNumber       RCC_I2SSRC_BIT_NUMBER
-#define RTCEN_BitNumber        RCC_RTCEN_BIT_NUMBER
-#define RTCEN_BITNUMBER        RCC_RTCEN_BIT_NUMBER
-#define BDRST_BitNumber        RCC_BDRST_BIT_NUMBER
-#define BDRST_BITNUMBER        RCC_BDRST_BIT_NUMBER
-#define RTCRST_BITNUMBER       RCC_RTCRST_BIT_NUMBER
-#define LSION_BitNumber        RCC_LSION_BIT_NUMBER
-#define LSION_BITNUMBER        RCC_LSION_BIT_NUMBER
-#define LSEON_BitNumber        RCC_LSEON_BIT_NUMBER
-#define LSEON_BITNUMBER        RCC_LSEON_BIT_NUMBER
-#define LSEBYP_BITNUMBER       RCC_LSEBYP_BIT_NUMBER
-#define PLLSAION_BitNumber     RCC_PLLSAION_BIT_NUMBER
-#define TIMPRE_BitNumber       RCC_TIMPRE_BIT_NUMBER
-#define RMVF_BitNumber         RCC_RMVF_BIT_NUMBER
-#define RMVF_BITNUMBER         RCC_RMVF_BIT_NUMBER
-#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
-#define CR_BYTE2_ADDRESS       RCC_CR_BYTE2_ADDRESS
-#define CIR_BYTE1_ADDRESS      RCC_CIR_BYTE1_ADDRESS
-#define CIR_BYTE2_ADDRESS      RCC_CIR_BYTE2_ADDRESS
-#define BDCR_BYTE0_ADDRESS     RCC_BDCR_BYTE0_ADDRESS
-#define DBP_TIMEOUT_VALUE      RCC_DBP_TIMEOUT_VALUE
-#define LSE_TIMEOUT_VALUE      RCC_LSE_TIMEOUT_VALUE
-
-#define CR_HSION_BB            RCC_CR_HSION_BB
-#define CR_CSSON_BB            RCC_CR_CSSON_BB
-#define CR_PLLON_BB            RCC_CR_PLLON_BB
-#define CR_PLLI2SON_BB         RCC_CR_PLLI2SON_BB
-#define CR_MSION_BB            RCC_CR_MSION_BB
-#define CSR_LSION_BB           RCC_CSR_LSION_BB
-#define CSR_LSEON_BB           RCC_CSR_LSEON_BB
-#define CSR_LSEBYP_BB          RCC_CSR_LSEBYP_BB
-#define CSR_RTCEN_BB           RCC_CSR_RTCEN_BB
-#define CSR_RTCRST_BB          RCC_CSR_RTCRST_BB
-#define CFGR_I2SSRC_BB         RCC_CFGR_I2SSRC_BB
-#define BDCR_RTCEN_BB          RCC_BDCR_RTCEN_BB
-#define BDCR_BDRST_BB          RCC_BDCR_BDRST_BB
-#define CR_HSEON_BB            RCC_CR_HSEON_BB
-#define CSR_RMVF_BB            RCC_CSR_RMVF_BB
-#define CR_PLLSAION_BB         RCC_CR_PLLSAION_BB
-#define DCKCFGR_TIMPRE_BB      RCC_DCKCFGR_TIMPRE_BB
-
-#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER     __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
-#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER    __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
-#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB        __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
-#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB       __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
-#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE         __HAL_RCC_CRS_RELOADVALUE_CALCULATE
-
-#define __HAL_RCC_GET_IT_SOURCE                     __HAL_RCC_GET_IT
-
-#define RCC_CRS_SYNCWARM       RCC_CRS_SYNCWARN
-#define RCC_CRS_TRIMOV         RCC_CRS_TRIMOVF
-
-#define RCC_PERIPHCLK_CK48               RCC_PERIPHCLK_CLK48
-#define RCC_CK48CLKSOURCE_PLLQ           RCC_CLK48CLKSOURCE_PLLQ
-#define RCC_CK48CLKSOURCE_PLLSAIP        RCC_CLK48CLKSOURCE_PLLSAIP
-#define RCC_CK48CLKSOURCE_PLLI2SQ        RCC_CLK48CLKSOURCE_PLLI2SQ
-#define IS_RCC_CK48CLKSOURCE             IS_RCC_CLK48CLKSOURCE
-#define RCC_SDIOCLKSOURCE_CK48           RCC_SDIOCLKSOURCE_CLK48
-
-#define __HAL_RCC_DFSDM_CLK_ENABLE             __HAL_RCC_DFSDM1_CLK_ENABLE
-#define __HAL_RCC_DFSDM_CLK_DISABLE            __HAL_RCC_DFSDM1_CLK_DISABLE
-#define __HAL_RCC_DFSDM_IS_CLK_ENABLED         __HAL_RCC_DFSDM1_IS_CLK_ENABLED
-#define __HAL_RCC_DFSDM_IS_CLK_DISABLED        __HAL_RCC_DFSDM1_IS_CLK_DISABLED
-#define __HAL_RCC_DFSDM_FORCE_RESET            __HAL_RCC_DFSDM1_FORCE_RESET
-#define __HAL_RCC_DFSDM_RELEASE_RESET          __HAL_RCC_DFSDM1_RELEASE_RESET
-#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE       __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
-#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE      __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
-#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED   __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED  __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
-#define DfsdmClockSelection         Dfsdm1ClockSelection
-#define RCC_PERIPHCLK_DFSDM         RCC_PERIPHCLK_DFSDM1
-#define RCC_DFSDMCLKSOURCE_PCLK     RCC_DFSDM1CLKSOURCE_PCLK
-#define RCC_DFSDMCLKSOURCE_SYSCLK   RCC_DFSDM1CLKSOURCE_SYSCLK
-#define __HAL_RCC_DFSDM_CONFIG      __HAL_RCC_DFSDM1_CONFIG
-#define __HAL_RCC_GET_DFSDM_SOURCE  __HAL_RCC_GET_DFSDM1_SOURCE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define  HAL_RNG_ReadyCallback(__HANDLE__)  HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)                                       
-
-/**
-  * @}
-  */
-  
-/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-  
-#define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG
-#define __HAL_RTC_DISABLE_IT                      __HAL_RTC_EXTI_DISABLE_IT
-#define __HAL_RTC_ENABLE_IT                       __HAL_RTC_EXTI_ENABLE_IT
-
-#if defined (STM32F1)
-#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
-
-#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_ENABLE_IT()
-
-#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_DISABLE_IT()
-
-#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT)    __HAL_RTC_ALARM_EXTI_GET_FLAG()
-
-#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
-#else
-#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
-                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
-                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
-#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__)   (((__EXTI_LINE__)  == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
-                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
-                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
-#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
-                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
-                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
-#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__)    (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
-                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
-                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
-#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__)   (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
-                                                      (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() :  \
-                                                          __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
-#endif   /* STM32F1 */
-
-#define IS_ALARM                                  IS_RTC_ALARM
-#define IS_ALARM_MASK                             IS_RTC_ALARM_MASK
-#define IS_TAMPER                                 IS_RTC_TAMPER
-#define IS_TAMPER_ERASE_MODE                      IS_RTC_TAMPER_ERASE_MODE
-#define IS_TAMPER_FILTER                          IS_RTC_TAMPER_FILTER 
-#define IS_TAMPER_INTERRUPT                       IS_RTC_TAMPER_INTERRUPT
-#define IS_TAMPER_MASKFLAG_STATE                  IS_RTC_TAMPER_MASKFLAG_STATE
-#define IS_TAMPER_PRECHARGE_DURATION              IS_RTC_TAMPER_PRECHARGE_DURATION
-#define IS_TAMPER_PULLUP_STATE                    IS_RTC_TAMPER_PULLUP_STATE
-#define IS_TAMPER_SAMPLING_FREQ                   IS_RTC_TAMPER_SAMPLING_FREQ
-#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION     IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
-#define IS_TAMPER_TRIGGER                         IS_RTC_TAMPER_TRIGGER
-#define IS_WAKEUP_CLOCK                           IS_RTC_WAKEUP_CLOCK
-#define IS_WAKEUP_COUNTER                         IS_RTC_WAKEUP_COUNTER
-
-#define __RTC_WRITEPROTECTION_ENABLE  __HAL_RTC_WRITEPROTECTION_ENABLE
-#define __RTC_WRITEPROTECTION_DISABLE  __HAL_RTC_WRITEPROTECTION_DISABLE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define SD_OCR_CID_CSD_OVERWRIETE   SD_OCR_CID_CSD_OVERWRITE
-#define SD_CMD_SD_APP_STAUS         SD_CMD_SD_APP_STATUS
-
-#if defined(STM32F4)
-#define  SD_SDMMC_DISABLED          SD_SDIO_DISABLED
-#define  SD_SDMMC_FUNCTION_BUSY     SD_SDIO_FUNCTION_BUSY     
-#define  SD_SDMMC_FUNCTION_FAILED   SD_SDIO_FUNCTION_FAILED   
-#define  SD_SDMMC_UNKNOWN_FUNCTION  SD_SDIO_UNKNOWN_FUNCTION  
-#define  SD_CMD_SDMMC_SEN_OP_COND   SD_CMD_SDIO_SEN_OP_COND   
-#define  SD_CMD_SDMMC_RW_DIRECT     SD_CMD_SDIO_RW_DIRECT     
-#define  SD_CMD_SDMMC_RW_EXTENDED   SD_CMD_SDIO_RW_EXTENDED   
-#define  __HAL_SD_SDMMC_ENABLE      __HAL_SD_SDIO_ENABLE      
-#define  __HAL_SD_SDMMC_DISABLE     __HAL_SD_SDIO_DISABLE     
-#define  __HAL_SD_SDMMC_DMA_ENABLE  __HAL_SD_SDIO_DMA_ENABLE  
-#define  __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL  
-#define  __HAL_SD_SDMMC_ENABLE_IT   __HAL_SD_SDIO_ENABLE_IT   
-#define  __HAL_SD_SDMMC_DISABLE_IT  __HAL_SD_SDIO_DISABLE_IT  
-#define  __HAL_SD_SDMMC_GET_FLAG    __HAL_SD_SDIO_GET_FLAG    
-#define  __HAL_SD_SDMMC_CLEAR_FLAG  __HAL_SD_SDIO_CLEAR_FLAG  
-#define  __HAL_SD_SDMMC_GET_IT      __HAL_SD_SDIO_GET_IT      
-#define  __HAL_SD_SDMMC_CLEAR_IT    __HAL_SD_SDIO_CLEAR_IT    
-#define  SDMMC_STATIC_FLAGS         SDIO_STATIC_FLAGS	       
-#define  SDMMC_CMD0TIMEOUT          SDIO_CMD0TIMEOUT	       
-#define  SD_SDMMC_SEND_IF_COND      SD_SDIO_SEND_IF_COND
-/* alias CMSIS */
-#define  SDMMC1_IRQn                SDIO_IRQn
-#define  SDMMC1_IRQHandler          SDIO_IRQHandler
-#endif
-
-#if defined(STM32F7) || defined(STM32L4)
-#define  SD_SDIO_DISABLED           SD_SDMMC_DISABLED
-#define  SD_SDIO_FUNCTION_BUSY      SD_SDMMC_FUNCTION_BUSY    
-#define  SD_SDIO_FUNCTION_FAILED    SD_SDMMC_FUNCTION_FAILED  
-#define  SD_SDIO_UNKNOWN_FUNCTION   SD_SDMMC_UNKNOWN_FUNCTION
-#define  SD_CMD_SDIO_SEN_OP_COND    SD_CMD_SDMMC_SEN_OP_COND
-#define  SD_CMD_SDIO_RW_DIRECT      SD_CMD_SDMMC_RW_DIRECT
-#define  SD_CMD_SDIO_RW_EXTENDED    SD_CMD_SDMMC_RW_EXTENDED
-#define  __HAL_SD_SDIO_ENABLE       __HAL_SD_SDMMC_ENABLE
-#define  __HAL_SD_SDIO_DISABLE      __HAL_SD_SDMMC_DISABLE
-#define  __HAL_SD_SDIO_DMA_ENABLE   __HAL_SD_SDMMC_DMA_ENABLE
-#define  __HAL_SD_SDIO_DMA_DISABL   __HAL_SD_SDMMC_DMA_DISABLE
-#define  __HAL_SD_SDIO_ENABLE_IT    __HAL_SD_SDMMC_ENABLE_IT
-#define  __HAL_SD_SDIO_DISABLE_IT   __HAL_SD_SDMMC_DISABLE_IT
-#define  __HAL_SD_SDIO_GET_FLAG     __HAL_SD_SDMMC_GET_FLAG
-#define  __HAL_SD_SDIO_CLEAR_FLAG   __HAL_SD_SDMMC_CLEAR_FLAG
-#define  __HAL_SD_SDIO_GET_IT       __HAL_SD_SDMMC_GET_IT
-#define  __HAL_SD_SDIO_CLEAR_IT     __HAL_SD_SDMMC_CLEAR_IT
-#define  SDIO_STATIC_FLAGS	        SDMMC_STATIC_FLAGS
-#define  SDIO_CMD0TIMEOUT	          SDMMC_CMD0TIMEOUT
-#define  SD_SDIO_SEND_IF_COND	      SD_SDMMC_SEND_IF_COND
-/* alias CMSIS for compatibilities */
-#define  SDIO_IRQn                  SDMMC1_IRQn
-#define  SDIO_IRQHandler            SDMMC1_IRQHandler
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __SMARTCARD_ENABLE_IT           __HAL_SMARTCARD_ENABLE_IT
-#define __SMARTCARD_DISABLE_IT          __HAL_SMARTCARD_DISABLE_IT
-#define __SMARTCARD_ENABLE              __HAL_SMARTCARD_ENABLE
-#define __SMARTCARD_DISABLE             __HAL_SMARTCARD_DISABLE
-#define __SMARTCARD_DMA_REQUEST_ENABLE  __HAL_SMARTCARD_DMA_REQUEST_ENABLE
-#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
-
-#define __HAL_SMARTCARD_GETCLOCKSOURCE  SMARTCARD_GETCLOCKSOURCE
-#define __SMARTCARD_GETCLOCKSOURCE      SMARTCARD_GETCLOCKSOURCE
-
-#define IS_SMARTCARD_ONEBIT_SAMPLING    IS_SMARTCARD_ONE_BIT_SAMPLE                  
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_SMBUS_RESET_CR1           SMBUS_RESET_CR1
-#define __HAL_SMBUS_RESET_CR2           SMBUS_RESET_CR2
-#define __HAL_SMBUS_GENERATE_START      SMBUS_GENERATE_START
-#define __HAL_SMBUS_GET_ADDR_MATCH      SMBUS_GET_ADDR_MATCH
-#define __HAL_SMBUS_GET_DIR             SMBUS_GET_DIR
-#define __HAL_SMBUS_GET_STOP_MODE       SMBUS_GET_STOP_MODE
-#define __HAL_SMBUS_GET_PEC_MODE        SMBUS_GET_PEC_MODE
-#define __HAL_SMBUS_GET_ALERT_ENABLED   SMBUS_GET_ALERT_ENABLED
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __HAL_SPI_1LINE_TX              SPI_1LINE_TX
-#define __HAL_SPI_1LINE_RX              SPI_1LINE_RX
-#define __HAL_SPI_RESET_CRC             SPI_RESET_CRC
-
-/**
-  * @}
-  */
-  
-/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __HAL_UART_GETCLOCKSOURCE       UART_GETCLOCKSOURCE
-#define __HAL_UART_MASK_COMPUTATION     UART_MASK_COMPUTATION
-#define __UART_GETCLOCKSOURCE           UART_GETCLOCKSOURCE
-#define __UART_MASK_COMPUTATION         UART_MASK_COMPUTATION
-
-#define IS_UART_WAKEUPMETHODE           IS_UART_WAKEUPMETHOD
-
-#define IS_UART_ONEBIT_SAMPLE           IS_UART_ONE_BIT_SAMPLE                  
-#define IS_UART_ONEBIT_SAMPLING         IS_UART_ONE_BIT_SAMPLE                  
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __USART_ENABLE_IT               __HAL_USART_ENABLE_IT
-#define __USART_DISABLE_IT              __HAL_USART_DISABLE_IT
-#define __USART_ENABLE                  __HAL_USART_ENABLE
-#define __USART_DISABLE                 __HAL_USART_DISABLE
-
-#define __HAL_USART_GETCLOCKSOURCE      USART_GETCLOCKSOURCE
-#define __USART_GETCLOCKSOURCE          USART_GETCLOCKSOURCE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define USB_EXTI_LINE_WAKEUP                               USB_WAKEUP_EXTI_LINE
-
-#define USB_FS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
-#define USB_FS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
-#define USB_FS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
-#define USB_FS_EXTI_LINE_WAKEUP                            USB_OTG_FS_WAKEUP_EXTI_LINE
-
-#define USB_HS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
-#define USB_HS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
-#define USB_HS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
-#define USB_HS_EXTI_LINE_WAKEUP                            USB_OTG_HS_WAKEUP_EXTI_LINE
-
-#define __HAL_USB_EXTI_ENABLE_IT                           __HAL_USB_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_USB_EXTI_DISABLE_IT                          __HAL_USB_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_USB_EXTI_GET_FLAG                            __HAL_USB_WAKEUP_EXTI_GET_FLAG
-#define __HAL_USB_EXTI_CLEAR_FLAG                          __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER             __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
-#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER            __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER           __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
-
-#define __HAL_USB_FS_EXTI_ENABLE_IT                        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_USB_FS_EXTI_DISABLE_IT                       __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_USB_FS_EXTI_GET_FLAG                         __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
-#define __HAL_USB_FS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
-#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
-#define __HAL_USB_FS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
-
-#define __HAL_USB_HS_EXTI_ENABLE_IT                        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_USB_HS_EXTI_DISABLE_IT                       __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_USB_HS_EXTI_GET_FLAG                         __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
-#define __HAL_USB_HS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
-#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
-#define __HAL_USB_HS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
-
-#define HAL_PCD_ActiveRemoteWakeup                         HAL_PCD_ActivateRemoteWakeup
-#define HAL_PCD_DeActiveRemoteWakeup                       HAL_PCD_DeActivateRemoteWakeup
-
-#define HAL_PCD_SetTxFiFo                                  HAL_PCDEx_SetTxFiFo
-#define HAL_PCD_SetRxFiFo                                  HAL_PCDEx_SetRxFiFo
-/**
-  * @}
-  */
-
-/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_TIM_SetICPrescalerValue   TIM_SET_ICPRESCALERVALUE
-#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
-
-#define TIM_GET_ITSTATUS                __HAL_TIM_GET_IT_SOURCE
-#define TIM_GET_CLEAR_IT                __HAL_TIM_CLEAR_IT
-
-#define __HAL_TIM_GET_ITSTATUS          __HAL_TIM_GET_IT_SOURCE
-
-#define __HAL_TIM_DIRECTION_STATUS      __HAL_TIM_IS_TIM_COUNTING_DOWN
-#define __HAL_TIM_PRESCALER             __HAL_TIM_SET_PRESCALER
-#define __HAL_TIM_SetCounter            __HAL_TIM_SET_COUNTER
-#define __HAL_TIM_GetCounter            __HAL_TIM_GET_COUNTER
-#define __HAL_TIM_SetAutoreload         __HAL_TIM_SET_AUTORELOAD
-#define __HAL_TIM_GetAutoreload         __HAL_TIM_GET_AUTORELOAD
-#define __HAL_TIM_SetClockDivision      __HAL_TIM_SET_CLOCKDIVISION
-#define __HAL_TIM_GetClockDivision      __HAL_TIM_GET_CLOCKDIVISION
-#define __HAL_TIM_SetICPrescaler        __HAL_TIM_SET_ICPRESCALER
-#define __HAL_TIM_GetICPrescaler        __HAL_TIM_GET_ICPRESCALER
-#define __HAL_TIM_SetCompare            __HAL_TIM_SET_COMPARE
-#define __HAL_TIM_GetCompare            __HAL_TIM_GET_COMPARE
-
-#define TIM_BREAKINPUTSOURCE_DFSDM  TIM_BREAKINPUTSOURCE_DFSDM1
-/**
-  * @}
-  */
-
-/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
-  * @{
-  */
-  
-#define __HAL_ETH_EXTI_ENABLE_IT                   __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_ETH_EXTI_DISABLE_IT                  __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_ETH_EXTI_GET_FLAG                    __HAL_ETH_WAKEUP_EXTI_GET_FLAG
-#define __HAL_ETH_EXTI_CLEAR_FLAG                  __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER     __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
-#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER    __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
-#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER   __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
-
-#define ETH_PROMISCIOUSMODE_ENABLE   ETH_PROMISCUOUS_MODE_ENABLE 
-#define ETH_PROMISCIOUSMODE_DISABLE  ETH_PROMISCUOUS_MODE_DISABLE
-#define IS_ETH_PROMISCIOUS_MODE      IS_ETH_PROMISCUOUS_MODE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_LTDC_LAYER LTDC_LAYER
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define SAI_OUTPUTDRIVE_DISABLED          SAI_OUTPUTDRIVE_DISABLE
-#define SAI_OUTPUTDRIVE_ENABLED           SAI_OUTPUTDRIVE_ENABLE
-#define SAI_MASTERDIVIDER_ENABLED         SAI_MASTERDIVIDER_ENABLE
-#define SAI_MASTERDIVIDER_DISABLED        SAI_MASTERDIVIDER_DISABLE
-#define SAI_STREOMODE                     SAI_STEREOMODE
-#define SAI_FIFOStatus_Empty              SAI_FIFOSTATUS_EMPTY
-#define SAI_FIFOStatus_Less1QuarterFull   SAI_FIFOSTATUS_LESS1QUARTERFULL
-#define SAI_FIFOStatus_1QuarterFull       SAI_FIFOSTATUS_1QUARTERFULL
-#define SAI_FIFOStatus_HalfFull           SAI_FIFOSTATUS_HALFFULL
-#define SAI_FIFOStatus_3QuartersFull      SAI_FIFOSTATUS_3QUARTERFULL
-#define SAI_FIFOStatus_Full               SAI_FIFOSTATUS_FULL
-#define IS_SAI_BLOCK_MONO_STREO_MODE      IS_SAI_BLOCK_MONO_STEREO_MODE
-#define SAI_SYNCHRONOUS_EXT               SAI_SYNCHRONOUS_EXT_SAI1
-#define SAI_SYNCEXT_IN_ENABLE             SAI_SYNCEXT_OUTBLOCKA_ENABLE
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
-  * @{
-  */
-  
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ___STM32_HAL_LEGACY */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal.h b/stmhal/hal/f4/inc/stm32f4xx_hal.h
deleted file mode 100644
index ed9e6a6f31..0000000000
--- a/stmhal/hal/f4/inc/stm32f4xx_hal.h
+++ /dev/null
@@ -1,265 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal.h
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   This file contains all the functions prototypes for the HAL 
-  *          module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_H
-#define __STM32F4xx_HAL_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_conf.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup HAL
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup HAL_Exported_Macros HAL Exported Macros
-  * @{
-  */
-
-/** @brief  Freeze/Unfreeze Peripherals in Debug mode 
-  */
-#define __HAL_DBGMCU_FREEZE_TIM2()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM3()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM4()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM5()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM6()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM7()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM12()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM13()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM14()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
-#define __HAL_DBGMCU_FREEZE_RTC()            (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
-#define __HAL_DBGMCU_FREEZE_WWDG()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
-#define __HAL_DBGMCU_FREEZE_IWDG()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
-#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
-#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
-#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
-#define __HAL_DBGMCU_FREEZE_CAN1()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP))
-#define __HAL_DBGMCU_FREEZE_CAN2()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM1()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM8()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM9()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM10()          (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM11()          (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP))
-
-#define __HAL_DBGMCU_UNFREEZE_TIM2()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM3()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM4()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM5()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM6()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM7()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM12()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM13()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM14()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
-#define __HAL_DBGMCU_UNFREEZE_RTC()            (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
-#define __HAL_DBGMCU_UNFREEZE_WWDG()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
-#define __HAL_DBGMCU_UNFREEZE_IWDG()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
-#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
-#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
-#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
-#define __HAL_DBGMCU_UNFREEZE_CAN1()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP))
-#define __HAL_DBGMCU_UNFREEZE_CAN2()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM1()           (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM8()           (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM9()           (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM10()          (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM11()          (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP))
-
-/** @brief  Main Flash memory mapped at 0x00000000
-  */
-#define __HAL_SYSCFG_REMAPMEMORY_FLASH()             (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE))
-
-/** @brief  System Flash memory mapped at 0x00000000
-  */
-#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH()       do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
-                                                         SYSCFG->MEMRMP |= SYSCFG_MEMRMP_MEM_MODE_0;\
-                                                        }while(0);
-
-/** @brief  Embedded SRAM mapped at 0x00000000
-  */
-#define __HAL_SYSCFG_REMAPMEMORY_SRAM()       do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
-                                                  SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1);\
-                                                 }while(0);
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
-/** @brief  FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
-  */
-#define __HAL_SYSCFG_REMAPMEMORY_FSMC()       do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
-                                                  SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\
-                                                 }while(0);
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx)
-/** @brief  FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
-  */
-#define __HAL_SYSCFG_REMAPMEMORY_FMC()       do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
-                                                 SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\
-                                                }while(0);
-
-/** @brief  FMC/SDRAM Bank 1 and 2 mapped at 0x00000000
-  */
-#define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM()       do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
-                                                       SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_2);\
-                                                      }while(0);
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-/** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable
-  * @{
-  */
-/** @brief  SYSCFG Break Lockup lock
-  *         Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8 input
-  * @note   The selected configuration is locked and can be unlocked by system reset
-  */
-#define __HAL_SYSCFG_BREAK_PVD_LOCK()      do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
-                                               SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK;    \
-                                              }while(0)
-/**
- * @}
- */
-                                                 
-/** @defgroup PVD_Lock_Enable PVD Lock
-  * @{
-  */
-/** @brief  SYSCFG Break PVD lock
-  *         Enables and locks the PVD connection with Timer1/8 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register
-  * @note   The selected configuration is locked and can be unlocked by system reset
-  */
-#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK()     do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
-                                                 SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK;    \
-                                                }while(0)
-/**
- * @}
- */
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup HAL_Exported_Functions
-  * @{
-  */
-/** @addtogroup HAL_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization and de-initialization functions  ******************************/
-HAL_StatusTypeDef HAL_Init(void);
-HAL_StatusTypeDef HAL_DeInit(void);
-void HAL_MspInit(void);
-void HAL_MspDeInit(void);
-HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
-/**
-  * @}
-  */
-
-/** @addtogroup HAL_Exported_Functions_Group2
-  * @{
-  */
-/* Peripheral Control functions  ************************************************/
-void HAL_IncTick(void);
-void HAL_Delay(__IO uint32_t Delay);
-uint32_t HAL_GetTick(void);
-void HAL_SuspendTick(void);
-void HAL_ResumeTick(void);
-uint32_t HAL_GetHalVersion(void);
-uint32_t HAL_GetREVID(void);
-uint32_t HAL_GetDEVID(void);
-void HAL_DBGMCU_EnableDBGSleepMode(void);
-void HAL_DBGMCU_DisableDBGSleepMode(void);
-void HAL_DBGMCU_EnableDBGStopMode(void);
-void HAL_DBGMCU_DisableDBGStopMode(void);
-void HAL_DBGMCU_EnableDBGStandbyMode(void);
-void HAL_DBGMCU_DisableDBGStandbyMode(void);
-void HAL_EnableCompensationCell(void);
-void HAL_DisableCompensationCell(void);
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx)
-void HAL_EnableMemorySwappingBank(void);
-void HAL_DisableMemorySwappingBank(void);
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup HAL_Private_Variables HAL Private Variables
-  * @{
-  */
-/**
-  * @}
-  */
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup HAL_Private_Constants HAL Private Constants
-  * @{
-  */
-/**
-  * @}
-  */
-/* Private macros ------------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_adc.h b/stmhal/hal/f4/inc/stm32f4xx_hal_adc.h
deleted file mode 100644
index 23ab7160a2..0000000000
--- a/stmhal/hal/f4/inc/stm32f4xx_hal_adc.h
+++ /dev/null
@@ -1,860 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_adc.h
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   Header file containing functions prototypes of ADC HAL library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_ADC_H
-#define __STM32F4xx_ADC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup ADC
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup ADC_Exported_Types ADC Exported Types
-  * @{
-  */
-
-/** 
-  * @brief  Structure definition of ADC and regular group initialization 
-  * @note   Parameters of this structure are shared within 2 scopes:
-  *          - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank.
-  *          - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
-  * @note   The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
-  *         ADC state can be either:
-  *          - For all parameters: ADC disabled
-  *          - For all parameters except 'Resolution', 'ScanConvMode', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group.
-  *          - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going.
-  *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
-  *         without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
-  */
-typedef struct
-{
-  uint32_t ClockPrescaler;        /*!< Select ADC clock prescaler. The clock is common for 
-                                       all the ADCs.
-                                       This parameter can be a value of @ref ADC_ClockPrescaler */
-  uint32_t Resolution;            /*!< Configures the ADC resolution.
-                                       This parameter can be a value of @ref ADC_Resolution */
-  uint32_t DataAlign;             /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
-                                       or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
-                                       This parameter can be a value of @ref ADC_Data_align */
-  uint32_t ScanConvMode;          /*!< Configures the sequencer of regular and injected groups.
-                                       This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
-                                       If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
-                                                    Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
-                                       If enabled:  Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
-                                                    Scan direction is upward: from rank1 to rank 'n'.
-                                       This parameter can be set to ENABLE or DISABLE */
-  uint32_t EOCSelection;          /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
-                                       This parameter can be a value of @ref ADC_EOCSelection.
-                                       Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence.
-                                             Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT)
-                                             or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion.
-                                       Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()).
-                                             If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */
-  uint32_t ContinuousConvMode;    /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
-                                       after the selected trigger occurred (software start or external trigger).
-                                       This parameter can be set to ENABLE or DISABLE. */
-  uint32_t NbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
-                                       To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
-                                       This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
-  uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
-                                       Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
-                                       Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
-                                       This parameter can be set to ENABLE or DISABLE. */
-  uint32_t NbrOfDiscConversion;   /*!< Specifies the number of discontinuous conversions in which the  main sequence of regular group (parameter NbrOfConversion) will be subdivided.
-                                       If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
-                                       This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
-  uint32_t ExternalTrigConv;      /*!< Selects the external event used to trigger the conversion start of regular group.
-                                       If set to ADC_SOFTWARE_START, external triggers are disabled.
-                                       If set to external trigger source, triggering is on event rising edge by default.
-                                       This parameter can be a value of @ref ADC_External_trigger_Source_Regular */
-  uint32_t ExternalTrigConvEdge;  /*!< Selects the external trigger edge of regular group.
-                                       If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
-                                       This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
-  uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
-                                       or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
-                                       Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
-                                       Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).
-                                       This parameter can be set to ENABLE or DISABLE. */
-}ADC_InitTypeDef;
-
-
-
-/** 
-  * @brief  Structure definition of ADC channel for regular group   
-  * @note   The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
-  *         ADC can be either disabled or enabled without conversion on going on regular group.
-  */ 
-typedef struct 
-{
-  uint32_t Channel;                /*!< Specifies the channel to configure into ADC regular group.
-                                        This parameter can be a value of @ref ADC_channels */
-  uint32_t Rank;                   /*!< Specifies the rank in the regular group sequencer.
-                                        This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
-  uint32_t SamplingTime;           /*!< Sampling time value to be set for the selected channel.
-                                        Unit: ADC clock cycles
-                                        Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
-                                        This parameter can be a value of @ref ADC_sampling_times
-                                        Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
-                                                 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
-                                        Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
-                                              sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
-                                              Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
-  uint32_t Offset;                 /*!< Reserved for future use, can be set to 0 */
-}ADC_ChannelConfTypeDef;
-
-/** 
-  * @brief ADC Configuration multi-mode structure definition  
-  */ 
-typedef struct
-{
-  uint32_t WatchdogMode;      /*!< Configures the ADC analog watchdog mode.
-                                   This parameter can be a value of @ref ADC_analog_watchdog_selection */
-  uint32_t HighThreshold;     /*!< Configures the ADC analog watchdog High threshold value.
-                                   This parameter must be a 12-bit value. */     
-  uint32_t LowThreshold;      /*!< Configures the ADC analog watchdog High threshold value.
-                                   This parameter must be a 12-bit value. */
-  uint32_t Channel;           /*!< Configures ADC channel for the analog watchdog. 
-                                   This parameter has an effect only if watchdog mode is configured on single channel 
-                                   This parameter can be a value of @ref ADC_channels */      
-  uint32_t ITMode;            /*!< Specifies whether the analog watchdog is configured
-                                   is interrupt mode or in polling mode.
-                                   This parameter can be set to ENABLE or DISABLE */
-  uint32_t WatchdogNumber;    /*!< Reserved for future use, can be set to 0 */
-}ADC_AnalogWDGConfTypeDef;
-
-/** 
-  * @brief  HAL ADC state machine: ADC states definition (bitfields)
-  */ 
-/* States of ADC global scope */
-#define HAL_ADC_STATE_RESET             ((uint32_t)0x00000000U)    /*!< ADC not yet initialized or disabled */
-#define HAL_ADC_STATE_READY             ((uint32_t)0x00000001U)    /*!< ADC peripheral ready for use */
-#define HAL_ADC_STATE_BUSY_INTERNAL     ((uint32_t)0x00000002U)    /*!< ADC is busy to internal process (initialization, calibration) */
-#define HAL_ADC_STATE_TIMEOUT           ((uint32_t)0x00000004U)    /*!< TimeOut occurrence */
-
-/* States of ADC errors */
-#define HAL_ADC_STATE_ERROR_INTERNAL    ((uint32_t)0x00000010U)    /*!< Internal error occurrence */
-#define HAL_ADC_STATE_ERROR_CONFIG      ((uint32_t)0x00000020U)    /*!< Configuration error occurrence */
-#define HAL_ADC_STATE_ERROR_DMA         ((uint32_t)0x00000040U)    /*!< DMA error occurrence */
-
-/* States of ADC group regular */
-#define HAL_ADC_STATE_REG_BUSY          ((uint32_t)0x00000100U)    /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
-                                                                       external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
-#define HAL_ADC_STATE_REG_EOC           ((uint32_t)0x00000200U)    /*!< Conversion data available on group regular */
-#define HAL_ADC_STATE_REG_OVR           ((uint32_t)0x00000400U)    /*!< Overrun occurrence */
-
-/* States of ADC group injected */
-#define HAL_ADC_STATE_INJ_BUSY          ((uint32_t)0x00001000U)    /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
-                                                                       external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
-#define HAL_ADC_STATE_INJ_EOC           ((uint32_t)0x00002000U)    /*!< Conversion data available on group injected */
-
-/* States of ADC analog watchdogs */
-#define HAL_ADC_STATE_AWD1              ((uint32_t)0x00010000U)    /*!< Out-of-window occurrence of analog watchdog 1 */
-#define HAL_ADC_STATE_AWD2              ((uint32_t)0x00020000U)    /*!< Not available on STM32F4 device: Out-of-window occurrence of analog watchdog 2 */
-#define HAL_ADC_STATE_AWD3              ((uint32_t)0x00040000U)    /*!< Not available on STM32F4 device: Out-of-window occurrence of analog watchdog 3 */
-
-/* States of ADC multi-mode */
-#define HAL_ADC_STATE_MULTIMODE_SLAVE   ((uint32_t)0x00100000U)    /*!< Not available on STM32F4 device: ADC in multimode slave state, controlled by another ADC master ( */
-
-
-/** 
-  * @brief  ADC handle Structure definition
-  */ 
-typedef struct
-{
-  ADC_TypeDef                   *Instance;                   /*!< Register base address */
-
-  ADC_InitTypeDef               Init;                        /*!< ADC required parameters */
-
-  __IO uint32_t                 NbrOfCurrentConversionRank;  /*!< ADC number of current conversion rank */
-
-  DMA_HandleTypeDef             *DMA_Handle;                 /*!< Pointer DMA Handler */
-
-  HAL_LockTypeDef               Lock;                        /*!< ADC locking object */
-
-  __IO uint32_t                 State;                       /*!< ADC communication state */
-
-  __IO uint32_t                 ErrorCode;                   /*!< ADC Error code */
-}ADC_HandleTypeDef;
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup ADC_Exported_Constants ADC Exported Constants
-  * @{
-  */
-
-/** @defgroup ADC_Error_Code ADC Error Code
-  * @{
-  */
-#define HAL_ADC_ERROR_NONE        ((uint32_t)0x00U)   /*!< No error                                              */
-#define HAL_ADC_ERROR_INTERNAL    ((uint32_t)0x01U)   /*!< ADC IP internal error: if problem of clocking, 
-                                                          enable/disable, erroneous state                       */
-#define HAL_ADC_ERROR_OVR         ((uint32_t)0x02U)   /*!< Overrun error                                         */
-#define HAL_ADC_ERROR_DMA         ((uint32_t)0x04U)   /*!< DMA transfer error                                    */
-/**
-  * @}
-  */
-
-
-/** @defgroup ADC_ClockPrescaler  ADC Clock Prescaler
-  * @{
-  */ 
-#define ADC_CLOCK_SYNC_PCLK_DIV2    ((uint32_t)0x00000000U)
-#define ADC_CLOCK_SYNC_PCLK_DIV4    ((uint32_t)ADC_CCR_ADCPRE_0)
-#define ADC_CLOCK_SYNC_PCLK_DIV6    ((uint32_t)ADC_CCR_ADCPRE_1)
-#define ADC_CLOCK_SYNC_PCLK_DIV8    ((uint32_t)ADC_CCR_ADCPRE)
-/**
-  * @}
-  */ 
-
-/** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases
-  * @{
-  */ 
-#define ADC_TWOSAMPLINGDELAY_5CYCLES    ((uint32_t)0x00000000U)
-#define ADC_TWOSAMPLINGDELAY_6CYCLES    ((uint32_t)ADC_CCR_DELAY_0)
-#define ADC_TWOSAMPLINGDELAY_7CYCLES    ((uint32_t)ADC_CCR_DELAY_1)
-#define ADC_TWOSAMPLINGDELAY_8CYCLES    ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
-#define ADC_TWOSAMPLINGDELAY_9CYCLES    ((uint32_t)ADC_CCR_DELAY_2)
-#define ADC_TWOSAMPLINGDELAY_10CYCLES   ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
-#define ADC_TWOSAMPLINGDELAY_11CYCLES   ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
-#define ADC_TWOSAMPLINGDELAY_12CYCLES   ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
-#define ADC_TWOSAMPLINGDELAY_13CYCLES   ((uint32_t)ADC_CCR_DELAY_3)
-#define ADC_TWOSAMPLINGDELAY_14CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))
-#define ADC_TWOSAMPLINGDELAY_15CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))
-#define ADC_TWOSAMPLINGDELAY_16CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
-#define ADC_TWOSAMPLINGDELAY_17CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))
-#define ADC_TWOSAMPLINGDELAY_18CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
-#define ADC_TWOSAMPLINGDELAY_19CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
-#define ADC_TWOSAMPLINGDELAY_20CYCLES   ((uint32_t)ADC_CCR_DELAY)
-/**
-  * @}
-  */ 
-
-/** @defgroup ADC_Resolution ADC Resolution
-  * @{
-  */ 
-#define ADC_RESOLUTION_12B  ((uint32_t)0x00000000U)
-#define ADC_RESOLUTION_10B  ((uint32_t)ADC_CR1_RES_0)
-#define ADC_RESOLUTION_8B   ((uint32_t)ADC_CR1_RES_1)
-#define ADC_RESOLUTION_6B   ((uint32_t)ADC_CR1_RES)
-/**
-  * @}
-  */ 
-
-/** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular
-  * @{
-  */ 
-#define ADC_EXTERNALTRIGCONVEDGE_NONE           ((uint32_t)0x00000000U)
-#define ADC_EXTERNALTRIGCONVEDGE_RISING         ((uint32_t)ADC_CR2_EXTEN_0)
-#define ADC_EXTERNALTRIGCONVEDGE_FALLING        ((uint32_t)ADC_CR2_EXTEN_1)
-#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING  ((uint32_t)ADC_CR2_EXTEN)
-/**
-  * @}
-  */ 
-
-/** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular
-  * @{
-  */
-/* Note: Parameter ADC_SOFTWARE_START is a software parameter used for        */
-/*       compatibility with other STM32 devices.                              */
-#define ADC_EXTERNALTRIGCONV_T1_CC1    ((uint32_t)0x00000000U)
-#define ADC_EXTERNALTRIGCONV_T1_CC2    ((uint32_t)ADC_CR2_EXTSEL_0)
-#define ADC_EXTERNALTRIGCONV_T1_CC3    ((uint32_t)ADC_CR2_EXTSEL_1)
-#define ADC_EXTERNALTRIGCONV_T2_CC2    ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
-#define ADC_EXTERNALTRIGCONV_T2_CC3    ((uint32_t)ADC_CR2_EXTSEL_2)
-#define ADC_EXTERNALTRIGCONV_T2_CC4    ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
-#define ADC_EXTERNALTRIGCONV_T2_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
-#define ADC_EXTERNALTRIGCONV_T3_CC1    ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
-#define ADC_EXTERNALTRIGCONV_T3_TRGO   ((uint32_t)ADC_CR2_EXTSEL_3)
-#define ADC_EXTERNALTRIGCONV_T4_CC4    ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0))
-#define ADC_EXTERNALTRIGCONV_T5_CC1    ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1))
-#define ADC_EXTERNALTRIGCONV_T5_CC2    ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
-#define ADC_EXTERNALTRIGCONV_T5_CC3    ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2))
-#define ADC_EXTERNALTRIGCONV_T8_CC1    ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
-#define ADC_EXTERNALTRIGCONV_T8_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
-#define ADC_EXTERNALTRIGCONV_Ext_IT11  ((uint32_t)ADC_CR2_EXTSEL)
-#define ADC_SOFTWARE_START             ((uint32_t)ADC_CR2_EXTSEL + 1U)
-/**
-  * @}
-  */ 
-
-/** @defgroup ADC_Data_align ADC Data Align
-  * @{
-  */ 
-#define ADC_DATAALIGN_RIGHT      ((uint32_t)0x00000000U)
-#define ADC_DATAALIGN_LEFT       ((uint32_t)ADC_CR2_ALIGN)
-/**
-  * @}
-  */ 
-
-/** @defgroup ADC_channels  ADC Common Channels
-  * @{
-  */ 
-#define ADC_CHANNEL_0           ((uint32_t)0x00000000U)
-#define ADC_CHANNEL_1           ((uint32_t)ADC_CR1_AWDCH_0)
-#define ADC_CHANNEL_2           ((uint32_t)ADC_CR1_AWDCH_1)
-#define ADC_CHANNEL_3           ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
-#define ADC_CHANNEL_4           ((uint32_t)ADC_CR1_AWDCH_2)
-#define ADC_CHANNEL_5           ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
-#define ADC_CHANNEL_6           ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
-#define ADC_CHANNEL_7           ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
-#define ADC_CHANNEL_8           ((uint32_t)ADC_CR1_AWDCH_3)
-#define ADC_CHANNEL_9           ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0))
-#define ADC_CHANNEL_10          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1))
-#define ADC_CHANNEL_11          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
-#define ADC_CHANNEL_12          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2))
-#define ADC_CHANNEL_13          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
-#define ADC_CHANNEL_14          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
-#define ADC_CHANNEL_15          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
-#define ADC_CHANNEL_16          ((uint32_t)ADC_CR1_AWDCH_4)
-#define ADC_CHANNEL_17          ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))
-#define ADC_CHANNEL_18          ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))
-
-#define ADC_CHANNEL_VREFINT     ((uint32_t)ADC_CHANNEL_17)
-#define ADC_CHANNEL_VBAT        ((uint32_t)ADC_CHANNEL_18)
-/**
-  * @}
-  */ 
-
-/** @defgroup ADC_sampling_times  ADC Sampling Times
-  * @{
-  */ 
-#define ADC_SAMPLETIME_3CYCLES    ((uint32_t)0x00000000U)
-#define ADC_SAMPLETIME_15CYCLES   ((uint32_t)ADC_SMPR1_SMP10_0)
-#define ADC_SAMPLETIME_28CYCLES   ((uint32_t)ADC_SMPR1_SMP10_1)
-#define ADC_SAMPLETIME_56CYCLES   ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))
-#define ADC_SAMPLETIME_84CYCLES   ((uint32_t)ADC_SMPR1_SMP10_2)
-#define ADC_SAMPLETIME_112CYCLES  ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0))
-#define ADC_SAMPLETIME_144CYCLES  ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1))
-#define ADC_SAMPLETIME_480CYCLES  ((uint32_t)ADC_SMPR1_SMP10)
-/**
-  * @}
-  */ 
-
-  /** @defgroup ADC_EOCSelection ADC EOC Selection
-  * @{
-  */ 
-#define ADC_EOC_SEQ_CONV              ((uint32_t)0x00000000U)
-#define ADC_EOC_SINGLE_CONV           ((uint32_t)0x00000001U)
-#define ADC_EOC_SINGLE_SEQ_CONV       ((uint32_t)0x00000002U)  /*!< reserved for future use */
-/**
-  * @}
-  */ 
-
-/** @defgroup ADC_Event_type ADC Event Type
-  * @{
-  */ 
-#define ADC_AWD_EVENT             ((uint32_t)ADC_FLAG_AWD)
-#define ADC_OVR_EVENT             ((uint32_t)ADC_FLAG_OVR)
-/**
-  * @}
-  */
-
-/** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection
-  * @{
-  */ 
-#define ADC_ANALOGWATCHDOG_SINGLE_REG         ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
-#define ADC_ANALOGWATCHDOG_SINGLE_INJEC       ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
-#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC    ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
-#define ADC_ANALOGWATCHDOG_ALL_REG            ((uint32_t)ADC_CR1_AWDEN)
-#define ADC_ANALOGWATCHDOG_ALL_INJEC          ((uint32_t)ADC_CR1_JAWDEN)
-#define ADC_ANALOGWATCHDOG_ALL_REGINJEC       ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
-#define ADC_ANALOGWATCHDOG_NONE               ((uint32_t)0x00000000U)
-/**
-  * @}
-  */ 
-    
-/** @defgroup ADC_interrupts_definition ADC Interrupts Definition
-  * @{
-  */ 
-#define ADC_IT_EOC      ((uint32_t)ADC_CR1_EOCIE)
-#define ADC_IT_AWD      ((uint32_t)ADC_CR1_AWDIE)
-#define ADC_IT_JEOC     ((uint32_t)ADC_CR1_JEOCIE)
-#define ADC_IT_OVR      ((uint32_t)ADC_CR1_OVRIE)
-/**
-  * @}
-  */ 
-    
-/** @defgroup ADC_flags_definition ADC Flags Definition
-  * @{
-  */ 
-#define ADC_FLAG_AWD    ((uint32_t)ADC_SR_AWD)
-#define ADC_FLAG_EOC    ((uint32_t)ADC_SR_EOC)
-#define ADC_FLAG_JEOC   ((uint32_t)ADC_SR_JEOC)
-#define ADC_FLAG_JSTRT  ((uint32_t)ADC_SR_JSTRT)
-#define ADC_FLAG_STRT   ((uint32_t)ADC_SR_STRT)
-#define ADC_FLAG_OVR    ((uint32_t)ADC_SR_OVR)
-/**
-  * @}
-  */ 
-
-/** @defgroup ADC_channels_type ADC Channels Type
-  * @{
-  */ 
-#define ADC_ALL_CHANNELS      ((uint32_t)0x00000001U)
-#define ADC_REGULAR_CHANNELS  ((uint32_t)0x00000002U) /*!< reserved for future use */
-#define ADC_INJECTED_CHANNELS ((uint32_t)0x00000003U) /*!< reserved for future use */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup ADC_Exported_Macros ADC Exported Macros
-  * @{
-  */
-
-/** @brief Reset ADC handle state
-  * @param  __HANDLE__: ADC handle
-  * @retval None
-  */
-#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
-
-/**
-  * @brief  Enable the ADC peripheral.
-  * @param  __HANDLE__: ADC handle
-  * @retval None
-  */
-#define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |=  ADC_CR2_ADON)
-
-/**
-  * @brief  Disable the ADC peripheral.
-  * @param  __HANDLE__: ADC handle
-  * @retval None
-  */
-#define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &=  ~ADC_CR2_ADON)
-
-/**
-  * @brief  Enable the ADC end of conversion interrupt.
-  * @param  __HANDLE__: specifies the ADC Handle.
-  * @param  __INTERRUPT__: ADC Interrupt.
-  * @retval None
-  */
-#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the ADC end of conversion interrupt.
-  * @param  __HANDLE__: specifies the ADC Handle.
-  * @param  __INTERRUPT__: ADC interrupt.
-  * @retval None
-  */
-#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))
-
-/** @brief  Check if the specified ADC interrupt source is enabled or disabled.
-  * @param  __HANDLE__: specifies the ADC Handle.
-  * @param  __INTERRUPT__: specifies the ADC interrupt source to check.
-  * @retval The new state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/**
-  * @brief  Clear the ADC's pending flags.
-  * @param  __HANDLE__: specifies the ADC Handle.
-  * @param  __FLAG__: ADC flag.
-  * @retval None
-  */
-#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
-
-/**
-  * @brief  Get the selected ADC's flag status.
-  * @param  __HANDLE__: specifies the ADC Handle.
-  * @param  __FLAG__: ADC flag.
-  * @retval None
-  */
-#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/**
-  * @}
-  */
-
-/* Include ADC HAL Extension module */
-#include "stm32f4xx_hal_adc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup ADC_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup ADC_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization/de-initialization functions ***********************************/
-HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
-void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
-void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
-/**
-  * @}
-  */
-
-/** @addtogroup ADC_Exported_Functions_Group2
-  * @{
-  */
-/* I/O operation functions ******************************************************/
-HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
-
-HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
-
-HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
-
-void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
-
-HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
-HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
-
-uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
-
-void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
-void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
-void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
-void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
-/**
-  * @}
-  */
-
-/** @addtogroup ADC_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral Control functions *************************************************/
-HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
-HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
-/**
-  * @}
-  */
-
-/** @addtogroup ADC_Exported_Functions_Group4
-  * @{
-  */
-/* Peripheral State functions ***************************************************/
-uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
-uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup ADC_Private_Constants ADC Private Constants
-  * @{
-  */
-/* Delay for ADC stabilization time.                                        */
-/* Maximum delay is 1us (refer to device datasheet, parameter tSTAB).       */
-/* Unit: us                                                                 */
-#define ADC_STAB_DELAY_US               ((uint32_t) 3U)
-/* Delay for temperature sensor stabilization time.                         */
-/* Maximum delay is 10us (refer to device datasheet, parameter tSTART).     */
-/* Unit: us                                                                 */
-#define ADC_TEMPSENSOR_DELAY_US         ((uint32_t) 10U)
-/**
-  * @}
-  */
-
-/* Private macro ------------------------------------------------------------*/
-
-/** @defgroup ADC_Private_Macros ADC Private Macros
-  * @{
-  */
-/* Macro reserved for internal HAL driver usage, not intended to be used in
-   code of final user */
-
-/**
-  * @brief Verification of ADC state: enabled or disabled
-  * @param __HANDLE__: ADC handle
-  * @retval SET (ADC enabled) or RESET (ADC disabled)
-  */
-#define ADC_IS_ENABLE(__HANDLE__)                                              \
-  ((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS )            \
-  ) ? SET : RESET)
-
-/**
-  * @brief Test if conversion trigger of regular group is software start
-  *        or external trigger.
-  * @param __HANDLE__: ADC handle
-  * @retval SET (software start) or RESET (external trigger)
-  */
-#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__)                              \
-  (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
-
-/**
-  * @brief Test if conversion trigger of injected group is software start
-  *        or external trigger.
-  * @param __HANDLE__: ADC handle
-  * @retval SET (software start) or RESET (external trigger)
-  */
-#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__)                             \
-  (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)
-
-/**
-  * @brief Simultaneously clears and sets specific bits of the handle State
-  * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
-  *        the first parameter is the ADC handle State, the second parameter is the
-  *        bit field to clear, the third and last parameter is the bit field to set.
-  * @retval None
-  */
-#define ADC_STATE_CLR_SET MODIFY_REG
-
-/**
-  * @brief Clear ADC error code (set it to error code: "no error")
-  * @param __HANDLE__: ADC handle
-  * @retval None
-  */
-#define ADC_CLEAR_ERRORCODE(__HANDLE__)                                        \
-  ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
-
-    
-#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK)     (((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
-                                              ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
-                                              ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV6) || \
-                                              ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV8))
-#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES)  || \
-                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES)  || \
-                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES)  || \
-                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES)  || \
-                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES)  || \
-                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
-                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
-                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \
-                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \
-                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \
-                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \
-                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \
-                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \
-                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \
-                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \
-                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_20CYCLES))
-#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \
-                                       ((RESOLUTION) == ADC_RESOLUTION_10B) || \
-                                       ((RESOLUTION) == ADC_RESOLUTION_8B)  || \
-                                       ((RESOLUTION) == ADC_RESOLUTION_6B))
-#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE)    || \
-                                    ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING)  || \
-                                    ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
-                                    ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
-#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1)  || \
-                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2)  || \
-                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3)  || \
-                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2)  || \
-                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3)  || \
-                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC4)  || \
-                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
-                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1)  || \
-                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
-                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4)  || \
-                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1)  || \
-                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC2)  || \
-                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3)  || \
-                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1)  || \
-                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
-                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_Ext_IT11)|| \
-                                  ((REGTRIG) == ADC_SOFTWARE_START))
-#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
-                                  ((ALIGN) == ADC_DATAALIGN_LEFT))
-#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_3CYCLES)   || \
-                                  ((TIME) == ADC_SAMPLETIME_15CYCLES)  || \
-                                  ((TIME) == ADC_SAMPLETIME_28CYCLES)  || \
-                                  ((TIME) == ADC_SAMPLETIME_56CYCLES)  || \
-                                  ((TIME) == ADC_SAMPLETIME_84CYCLES)  || \
-                                  ((TIME) == ADC_SAMPLETIME_112CYCLES) || \
-                                  ((TIME) == ADC_SAMPLETIME_144CYCLES) || \
-                                  ((TIME) == ADC_SAMPLETIME_480CYCLES))
-#define IS_ADC_EOCSelection(EOCSelection) (((EOCSelection) == ADC_EOC_SINGLE_CONV)   || \
-                                           ((EOCSelection) == ADC_EOC_SEQ_CONV)  || \
-                                           ((EOCSelection) == ADC_EOC_SINGLE_SEQ_CONV))
-#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \
-                                  ((EVENT) == ADC_OVR_EVENT))
-#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG)        || \
-                                          ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC)      || \
-                                          ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)   || \
-                                          ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG)           || \
-                                          ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC)         || \
-                                          ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)      || \
-                                          ((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE))
-#define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \
-                                            ((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \
-                                            ((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS))
-#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= ((uint32_t)0xFFFU))
-
-#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1U)) && ((LENGTH) <= ((uint32_t)16U)))
-#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= ((uint32_t)1U)) && ((RANK) <= ((uint32_t)16U)))
-#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1U)) && ((NUMBER) <= ((uint32_t)8U)))
-#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE)                                     \
-   ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFFU))) || \
-    (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FFU))) || \
-    (((RESOLUTION) == ADC_RESOLUTION_8B)  && ((ADC_VALUE) <= ((uint32_t)0x00FFU))) || \
-    (((RESOLUTION) == ADC_RESOLUTION_6B)  && ((ADC_VALUE) <= ((uint32_t)0x003FU))))
-
-/**
-  * @brief  Set ADC Regular channel sequence length.
-  * @param  _NbrOfConversion_: Regular channel sequence length. 
-  * @retval None
-  */
-#define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1U) << 20U)
-
-/**
-  * @brief  Set the ADC's sample time for channel numbers between 10 and 18.
-  * @param  _SAMPLETIME_: Sample time parameter.
-  * @param  _CHANNELNB_: Channel number.  
-  * @retval None
-  */
-#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10U)))
-
-/**
-  * @brief  Set the ADC's sample time for channel numbers between 0 and 9.
-  * @param  _SAMPLETIME_: Sample time parameter.
-  * @param  _CHANNELNB_: Channel number.  
-  * @retval None
-  */
-#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * ((uint32_t)((uint16_t)(_CHANNELNB_)))))
-
-/**
-  * @brief  Set the selected regular channel rank for rank between 1 and 6.
-  * @param  _CHANNELNB_: Channel number.
-  * @param  _RANKNB_: Rank number.    
-  * @retval None
-  */
-#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 1U)))
-
-/**
-  * @brief  Set the selected regular channel rank for rank between 7 and 12.
-  * @param  _CHANNELNB_: Channel number.
-  * @param  _RANKNB_: Rank number.    
-  * @retval None
-  */
-#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 7U)))
-
-/**
-  * @brief  Set the selected regular channel rank for rank between 13 and 16.
-  * @param  _CHANNELNB_: Channel number.
-  * @param  _RANKNB_: Rank number.    
-  * @retval None
-  */
-#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 13U)))
-
-/**
-  * @brief  Enable ADC continuous conversion mode.
-  * @param  _CONTINUOUS_MODE_: Continuous mode.
-  * @retval None
-  */
-#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1U)
-
-/**
-  * @brief  Configures the number of discontinuous conversions for the regular group channels.
-  * @param  _NBR_DISCONTINUOUSCONV_: Number of discontinuous conversions.
-  * @retval None
-  */
-#define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1U) << POSITION_VAL(ADC_CR1_DISCNUM))
-
-/**
-  * @brief  Enable ADC scan mode.
-  * @param  _SCANCONV_MODE_: Scan conversion mode.
-  * @retval None
-  */
-#define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8U)
-
-/**
-  * @brief  Enable the ADC end of conversion selection.
-  * @param  _EOCSelection_MODE_: End of conversion selection mode.
-  * @retval None
-  */
-#define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10U)
-
-/**
-  * @brief  Enable the ADC DMA continuous request.
-  * @param  _DMAContReq_MODE_: DMA continuous request mode.
-  * @retval None
-  */
-#define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9U)
-
-/**
-  * @brief Return resolution bits in CR1 register.
-  * @param __HANDLE__: ADC handle
-  * @retval None
-  */
-#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup ADC_Private_Functions ADC Private Functions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_ADC_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_adc_ex.h b/stmhal/hal/f4/inc/stm32f4xx_hal_adc_ex.h
deleted file mode 100644
index 457fc5d13b..0000000000
--- a/stmhal/hal/f4/inc/stm32f4xx_hal_adc_ex.h
+++ /dev/null
@@ -1,413 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_adc_ex.h
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   Header file of ADC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_ADC_EX_H
-#define __STM32F4xx_ADC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup ADCEx
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup ADCEx_Exported_Types ADC Exported Types
-  * @{
-  */
-   
-/** 
-  * @brief  ADC Configuration injected Channel structure definition
-  * @note   Parameters of this structure are shared within 2 scopes:
-  *          - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset
-  *          - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
-  *            AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
-  * @note   The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
-  *         ADC state can be either:
-  *          - For all parameters: ADC disabled
-  *          - For all except parameters 'InjectedDiscontinuousConvMode' and 'AutoInjectedConv': ADC enabled without conversion on going on injected group.
-  *          - For parameters 'ExternalTrigInjecConv' and 'ExternalTrigInjecConvEdge': ADC enabled, even with conversion on going on injected group.
-  */
-typedef struct 
-{
-  uint32_t InjectedChannel;               /*!< Selection of ADC channel to configure
-                                               This parameter can be a value of @ref ADC_channels
-                                               Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
-  uint32_t InjectedRank;                  /*!< Rank in the injected group sequencer
-                                               This parameter must be a value of @ref ADCEx_injected_rank
-                                               Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
-  uint32_t InjectedSamplingTime;          /*!< Sampling time value to be set for the selected channel.
-                                               Unit: ADC clock cycles
-                                               Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
-                                               This parameter can be a value of @ref ADC_sampling_times
-                                               Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
-                                                        If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
-                                               Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
-                                                     sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
-                                                     Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
-  uint32_t InjectedOffset;                /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
-                                               Offset value must be a positive number.
-                                               Depending of ADC resolution selected (12, 10, 8 or 6 bits),
-                                               this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
-  uint32_t InjectedNbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
-                                               To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
-                                               This parameter must be a number between Min_Data = 1 and Max_Data = 4.
-                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 
-                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
-  uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
-                                               Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
-                                               Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
-                                               This parameter can be set to ENABLE or DISABLE.
-                                               Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
-                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 
-                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
-  uint32_t AutoInjectedConv;              /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
-                                               This parameter can be set to ENABLE or DISABLE.      
-                                               Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
-                                               Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
-                                               Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
-                                                     To maintain JAUTO always enabled, DMA must be configured in circular mode.
-                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
-                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
-  uint32_t ExternalTrigInjecConv;         /*!< Selects the external event used to trigger the conversion start of injected group.
-                                               If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
-                                               If set to external trigger source, triggering is on event rising edge.
-                                               This parameter can be a value of @ref ADCEx_External_trigger_Source_Injected
-                                               Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
-                                                     If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)
-                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
-                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
-  uint32_t ExternalTrigInjecConvEdge;     /*!< Selects the external trigger edge of injected group.
-                                               This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected.
-                                               If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
-                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 
-                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
-}ADC_InjectionConfTypeDef; 
-
-/** 
-  * @brief ADC Configuration multi-mode structure definition  
-  */ 
-typedef struct
-{
-  uint32_t Mode;              /*!< Configures the ADC to operate in independent or multi mode. 
-                                   This parameter can be a value of @ref ADCEx_Common_mode */
-  uint32_t DMAAccessMode;     /*!< Configures the Direct memory access mode for multi ADC mode.
-                                   This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multi_mode */
-  uint32_t TwoSamplingDelay;  /*!< Configures the Delay between 2 sampling phases.
-                                   This parameter can be a value of @ref ADC_delay_between_2_sampling_phases */
-}ADC_MultiModeTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup ADCEx_Exported_Constants ADC Exported Constants
-  * @{
-  */
-
-/** @defgroup ADCEx_Common_mode ADC Common Mode
-  * @{
-  */ 
-#define ADC_MODE_INDEPENDENT                  ((uint32_t)0x00000000U)
-#define ADC_DUALMODE_REGSIMULT_INJECSIMULT    ((uint32_t)ADC_CCR_MULTI_0)
-#define ADC_DUALMODE_REGSIMULT_ALTERTRIG      ((uint32_t)ADC_CCR_MULTI_1)
-#define ADC_DUALMODE_INJECSIMULT              ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
-#define ADC_DUALMODE_REGSIMULT                ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))
-#define ADC_DUALMODE_INTERL                   ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))
-#define ADC_DUALMODE_ALTERTRIG                ((uint32_t)(ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))
-#define ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT  ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0))
-#define ADC_TRIPLEMODE_REGSIMULT_AlterTrig    ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1))
-#define ADC_TRIPLEMODE_INJECSIMULT            ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
-#define ADC_TRIPLEMODE_REGSIMULT              ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))
-#define ADC_TRIPLEMODE_INTERL                 ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))
-#define ADC_TRIPLEMODE_ALTERTRIG              ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))
-/**
-  * @}
-  */ 
-
-/** @defgroup ADCEx_Direct_memory_access_mode_for_multi_mode ADC Direct Memory Access Mode For Multi Mode
-  * @{
-  */ 
-#define ADC_DMAACCESSMODE_DISABLED  ((uint32_t)0x00000000U)     /*!< DMA mode disabled */
-#define ADC_DMAACCESSMODE_1         ((uint32_t)ADC_CCR_DMA_0)  /*!< DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
-#define ADC_DMAACCESSMODE_2         ((uint32_t)ADC_CCR_DMA_1)  /*!< DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
-#define ADC_DMAACCESSMODE_3         ((uint32_t)ADC_CCR_DMA)    /*!< DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
-/**
-  * @}
-  */ 
-
-/** @defgroup ADCEx_External_trigger_edge_Injected ADC External Trigger Edge Injected
-  * @{
-  */ 
-#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE           ((uint32_t)0x00000000U)
-#define ADC_EXTERNALTRIGINJECCONVEDGE_RISING         ((uint32_t)ADC_CR2_JEXTEN_0)
-#define ADC_EXTERNALTRIGINJECCONVEDGE_FALLING        ((uint32_t)ADC_CR2_JEXTEN_1)
-#define ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING  ((uint32_t)ADC_CR2_JEXTEN)
-/**
-  * @}
-  */ 
-
-/** @defgroup ADCEx_External_trigger_Source_Injected ADC External Trigger Source Injected
-  * @{
-  */ 
-#define ADC_EXTERNALTRIGINJECCONV_T1_CC4           ((uint32_t)0x00000000U)
-#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO          ((uint32_t)ADC_CR2_JEXTSEL_0)
-#define ADC_EXTERNALTRIGINJECCONV_T2_CC1           ((uint32_t)ADC_CR2_JEXTSEL_1)
-#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO          ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
-#define ADC_EXTERNALTRIGINJECCONV_T3_CC2           ((uint32_t)ADC_CR2_JEXTSEL_2)
-#define ADC_EXTERNALTRIGINJECCONV_T3_CC4           ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
-#define ADC_EXTERNALTRIGINJECCONV_T4_CC1           ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
-#define ADC_EXTERNALTRIGINJECCONV_T4_CC2           ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
-#define ADC_EXTERNALTRIGINJECCONV_T4_CC3           ((uint32_t)ADC_CR2_JEXTSEL_3)
-#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO          ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0))
-#define ADC_EXTERNALTRIGINJECCONV_T5_CC4           ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1))
-#define ADC_EXTERNALTRIGINJECCONV_T5_TRGO          ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
-#define ADC_EXTERNALTRIGINJECCONV_T8_CC2           ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2))
-#define ADC_EXTERNALTRIGINJECCONV_T8_CC3           ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
-#define ADC_EXTERNALTRIGINJECCONV_T8_CC4           ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
-#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15         ((uint32_t)ADC_CR2_JEXTSEL)
-#define ADC_INJECTED_SOFTWARE_START                ((uint32_t)ADC_CR2_JEXTSEL + 1U)
-/**
-  * @}
-  */ 
-
-/** @defgroup ADCEx_injected_rank ADC Injected Rank
-  * @{
-  */ 
-#define ADC_INJECTED_RANK_1    ((uint32_t)0x00000001U)
-#define ADC_INJECTED_RANK_2    ((uint32_t)0x00000002U)
-#define ADC_INJECTED_RANK_3    ((uint32_t)0x00000003U)
-#define ADC_INJECTED_RANK_4    ((uint32_t)0x00000004U)
-/**
-  * @}
-  */
-
-/** @defgroup ADCEx_channels  ADC Specific Channels
-  * @{
-  */
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \
-    defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || \
-    defined(STM32F412Cx)
-#define ADC_CHANNEL_TEMPSENSOR  ((uint32_t)ADC_CHANNEL_16)
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cxs */
-
-#if defined(STM32F411xE) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
-    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 
-#define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT ((uint32_t)0x10000000U) /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */
-#define ADC_CHANNEL_TEMPSENSOR  ((uint32_t)ADC_CHANNEL_18 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT)
-#endif /* STM32F411xE || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
-/**
-  * @}
-  */ 
-
-
-/**
-  * @}
-  */ 
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup ADC_Exported_Macros ADC Exported Macros
-  * @{
-  */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
-/**
-  * @brief Disable internal path of ADC channel Vbat
-  * @Note  Use case of this macro:
-  *        On devices STM32F42x and STM32F43x, ADC internal channels
-  *        Vbat and VrefInt share the same internal path, only
-  *        one of them can be enabled.This macro is to be used when ADC 
-  *        channels Vbat and VrefInt are selected, and must be called 
-  *        before starting conversion of ADC channel VrefInt in order 
-  *        to disable ADC channel Vbat.
-  * @retval None
-  */
-#define __HAL_ADC_PATH_INTERNAL_VBAT_DISABLE() (ADC->CCR &= ~(ADC_CCR_VBATE))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
-/**
-  * @}
-  */ 
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup ADCEx_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup ADCEx_Exported_Functions_Group1
-  * @{
-  */
-
-/* I/O operation functions ******************************************************/
-HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
-HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
-uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
-HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
-HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc);
-uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc);
-void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
-
-/* Peripheral Control functions *************************************************/
-HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
-HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode);
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup ADCEx_Private_Constants ADC Private Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup ADCEx_Private_Macros ADC Private Macros
-  * @{
-  */
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \
-    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
-    defined(STM32F412Rx) || defined(STM32F412Cx)
-#define IS_ADC_CHANNEL(CHANNEL) ((CHANNEL) <= ADC_CHANNEL_18)
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
-    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
-#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) <= ADC_CHANNEL_18)  || \
-                                 ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
-
-#define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT)                 || \
-                           ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT)   || \
-                           ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG)     || \
-                           ((MODE) == ADC_DUALMODE_INJECSIMULT)             || \
-                           ((MODE) == ADC_DUALMODE_REGSIMULT)               || \
-                           ((MODE) == ADC_DUALMODE_INTERL)                  || \
-                           ((MODE) == ADC_DUALMODE_ALTERTRIG)               || \
-                           ((MODE) == ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT) || \
-                           ((MODE) == ADC_TRIPLEMODE_REGSIMULT_AlterTrig)   || \
-                           ((MODE) == ADC_TRIPLEMODE_INJECSIMULT)           || \
-                           ((MODE) == ADC_TRIPLEMODE_REGSIMULT)             || \
-                           ((MODE) == ADC_TRIPLEMODE_INTERL)                || \
-                           ((MODE) == ADC_TRIPLEMODE_ALTERTRIG))
-#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAACCESSMODE_DISABLED) || \
-                                      ((MODE) == ADC_DMAACCESSMODE_1)        || \
-                                      ((MODE) == ADC_DMAACCESSMODE_2)        || \
-                                      ((MODE) == ADC_DMAACCESSMODE_3))
-#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_NONE)    || \
-                                          ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISING)  || \
-                                          ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_FALLING) || \
-                                          ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING))
-#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4)  || \
-                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
-                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1)  || \
-                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
-                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC2)  || \
-                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)  || \
-                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC1)  || \
-                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC2)  || \
-                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3)  || \
-                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
-                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4)  || \
-                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || \
-                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2)  || \
-                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC3)  || \
-                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4)  || \
-                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15)|| \
-                                        ((INJTRIG) == ADC_INJECTED_SOFTWARE_START))
-#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1U)) && ((LENGTH) <= ((uint32_t)4U)))
-#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= ((uint32_t)1U)) && ((RANK) <= ((uint32_t)4U)))
-
-/**
-  * @brief  Set the selected injected Channel rank.
-  * @param  _CHANNELNB_: Channel number.
-  * @param  _RANKNB_: Rank number. 
-  * @param  _JSQR_JL_: Sequence length.
-  * @retval None
-  */
-#define   ADC_JSQR(_CHANNELNB_, _RANKNB_, _JSQR_JL_)  (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * (uint8_t)(((_RANKNB_) + 3U) - (_JSQR_JL_))))
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup ADCEx_Private_Functions ADC Private Functions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_ADC_EX_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_can.h b/stmhal/hal/f4/inc/stm32f4xx_hal_can.h
deleted file mode 100644
index e3fb594ae7..0000000000
--- a/stmhal/hal/f4/inc/stm32f4xx_hal_can.h
+++ /dev/null
@@ -1,777 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_can.h
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   Header file of CAN HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_CAN_H
-#define __STM32F4xx_HAL_CAN_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
-    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-  	defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)   || defined(STM32F412Zx) ||\
-    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup CAN
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup CAN_Exported_Types CAN Exported Types
-  * @{
-  */
-
-/**
-  * @brief  HAL State structures definition
-  */
-typedef enum
-{
-  HAL_CAN_STATE_RESET             = 0x00U,  /*!< CAN not yet initialized or disabled */
-  HAL_CAN_STATE_READY             = 0x01U,  /*!< CAN initialized and ready for use   */
-  HAL_CAN_STATE_BUSY              = 0x02U,  /*!< CAN process is ongoing              */
-  HAL_CAN_STATE_BUSY_TX           = 0x12U,  /*!< CAN process is ongoing              */
-  HAL_CAN_STATE_BUSY_RX           = 0x22U,  /*!< CAN process is ongoing              */
-  HAL_CAN_STATE_BUSY_TX_RX        = 0x32U,  /*!< CAN process is ongoing              */
-  HAL_CAN_STATE_TIMEOUT           = 0x03U,  /*!< Timeout state                       */
-  HAL_CAN_STATE_ERROR             = 0x04U   /*!< CAN error state                     */
-
-}HAL_CAN_StateTypeDef;
-
-/**
-  * @brief  CAN init structure definition
-  */
-typedef struct
-{
-  uint32_t Prescaler;  /*!< Specifies the length of a time quantum.
-                            This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
-
-  uint32_t Mode;       /*!< Specifies the CAN operating mode.
-                            This parameter can be a value of @ref CAN_operating_mode */
-
-  uint32_t SJW;        /*!< Specifies the maximum number of time quanta
-                            the CAN hardware is allowed to lengthen or
-                            shorten a bit to perform resynchronization.
-                            This parameter can be a value of @ref CAN_synchronisation_jump_width */
-
-  uint32_t BS1;        /*!< Specifies the number of time quanta in Bit Segment 1.
-                            This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
-
-  uint32_t BS2;        /*!< Specifies the number of time quanta in Bit Segment 2.
-                            This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
-
-  uint32_t TTCM;       /*!< Enable or disable the time triggered communication mode.
-                            This parameter can be set to ENABLE or DISABLE. */
-
-  uint32_t ABOM;       /*!< Enable or disable the automatic bus-off management.
-                            This parameter can be set to ENABLE or DISABLE */
-
-  uint32_t AWUM;       /*!< Enable or disable the automatic wake-up mode.
-                            This parameter can be set to ENABLE or DISABLE */
-
-  uint32_t NART;       /*!< Enable or disable the non-automatic retransmission mode.
-                            This parameter can be set to ENABLE or DISABLE */
-
-  uint32_t RFLM;       /*!< Enable or disable the receive FIFO Locked mode.
-                            This parameter can be set to ENABLE or DISABLE */
-
-  uint32_t TXFP;       /*!< Enable or disable the transmit FIFO priority.
-                            This parameter can be set to ENABLE or DISABLE */
-}CAN_InitTypeDef;
-
-/**
-  * @brief  CAN filter configuration structure definition
-  */
-typedef struct
-{
-  uint32_t FilterIdHigh;          /*!< Specifies the filter identification number (MSBs for a 32-bit
-                                       configuration, first one for a 16-bit configuration).
-                                       This parameter must be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
-
-  uint32_t FilterIdLow;           /*!< Specifies the filter identification number (LSBs for a 32-bit
-                                       configuration, second one for a 16-bit configuration).
-                                       This parameter must be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
-
-  uint32_t FilterMaskIdHigh;      /*!< Specifies the filter mask number or identification number,
-                                       according to the mode (MSBs for a 32-bit configuration,
-                                       first one for a 16-bit configuration).
-                                       This parameter must be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
-
-  uint32_t FilterMaskIdLow;       /*!< Specifies the filter mask number or identification number,
-                                       according to the mode (LSBs for a 32-bit configuration,
-                                       second one for a 16-bit configuration).
-                                       This parameter must be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
-
-  uint32_t FilterFIFOAssignment;  /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
-                                       This parameter can be a value of @ref CAN_filter_FIFO */
-
-  uint32_t FilterNumber;          /*!< Specifies the filter which will be initialized.
-                                       This parameter must be a number between Min_Data = 0 and Max_Data = 27 */
-
-  uint32_t FilterMode;            /*!< Specifies the filter mode to be initialized.
-                                       This parameter can be a value of @ref CAN_filter_mode */
-
-  uint32_t FilterScale;           /*!< Specifies the filter scale.
-                                       This parameter can be a value of @ref CAN_filter_scale */
-
-  uint32_t FilterActivation;      /*!< Enable or disable the filter.
-                                       This parameter can be set to ENABLE or DISABLE. */
-
-  uint32_t BankNumber;            /*!< Select the start slave bank filter.
-                                       This parameter must be a number between Min_Data = 0 and Max_Data = 28 */
-
-}CAN_FilterConfTypeDef;
-
-/**
-  * @brief  CAN Tx message structure definition
-  */
-typedef struct
-{
-  uint32_t StdId;    /*!< Specifies the standard identifier.
-                          This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
-
-  uint32_t ExtId;    /*!< Specifies the extended identifier.
-                          This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFFU */
-
-  uint32_t IDE;      /*!< Specifies the type of identifier for the message that will be transmitted.
-                          This parameter can be a value of @ref CAN_Identifier_Type */
-
-  uint32_t RTR;      /*!< Specifies the type of frame for the message that will be transmitted.
-                          This parameter can be a value of @ref CAN_remote_transmission_request */
-
-  uint32_t DLC;      /*!< Specifies the length of the frame that will be transmitted.
-                          This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
-
-  uint8_t Data[8];   /*!< Contains the data to be transmitted.
-                          This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
-
-}CanTxMsgTypeDef;
-
-/**
-  * @brief  CAN Rx message structure definition
-  */
-typedef struct
-{
-  uint32_t StdId;       /*!< Specifies the standard identifier.
-                             This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
-
-  uint32_t ExtId;       /*!< Specifies the extended identifier.
-                             This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFFU */
-
-  uint32_t IDE;         /*!< Specifies the type of identifier for the message that will be received.
-                             This parameter can be a value of @ref CAN_Identifier_Type */
-
-  uint32_t RTR;         /*!< Specifies the type of frame for the received message.
-                             This parameter can be a value of @ref CAN_remote_transmission_request */
-
-  uint32_t DLC;         /*!< Specifies the length of the frame that will be received.
-                             This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
-
-  uint8_t Data[8];      /*!< Contains the data to be received.
-                             This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
-
-  uint32_t FMI;         /*!< Specifies the index of the filter the message stored in the mailbox passes through.
-                             This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
-
-  uint32_t FIFONumber;  /*!< Specifies the receive FIFO number.
-                             This parameter can be CAN_FIFO0 or CAN_FIFO1 */
-
-}CanRxMsgTypeDef;
-
-/**
-  * @brief  CAN handle Structure definition
-  */
-typedef struct
-{
-  CAN_TypeDef                 *Instance;  /*!< Register base address          */
-
-  CAN_InitTypeDef             Init;       /*!< CAN required parameters        */
-
-  CanTxMsgTypeDef*            pTxMsg;     /*!< Pointer to transmit structure  */
-
-  CanRxMsgTypeDef*            pRxMsg;     /*!< Pointer to reception structure */
-
-  __IO HAL_CAN_StateTypeDef   State;      /*!< CAN communication state        */
-
-  HAL_LockTypeDef             Lock;       /*!< CAN locking object             */
-
-  __IO uint32_t               ErrorCode;  /*!< CAN Error code                 */
-
-}CAN_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CAN_Exported_Constants CAN Exported Constants
-  * @{
-  */
-
-/** @defgroup CAN_Error_Code CAN Error Code
-  * @{
-  */
-#define   HAL_CAN_ERROR_NONE      0x00U    /*!< No error             */
-#define   HAL_CAN_ERROR_EWG       0x01U    /*!< EWG error            */
-#define   HAL_CAN_ERROR_EPV       0x02U    /*!< EPV error            */
-#define   HAL_CAN_ERROR_BOF       0x04U    /*!< BOF error            */
-#define   HAL_CAN_ERROR_STF       0x08U    /*!< Stuff error          */
-#define   HAL_CAN_ERROR_FOR       0x10U    /*!< Form error           */
-#define   HAL_CAN_ERROR_ACK       0x20U    /*!< Acknowledgment error */
-#define   HAL_CAN_ERROR_BR        0x40U    /*!< Bit recessive        */
-#define   HAL_CAN_ERROR_BD        0x80U    /*!< LEC dominant         */
-#define   HAL_CAN_ERROR_CRC       0x100U   /*!< LEC transfer error   */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_InitStatus CAN InitStatus
-  * @{
-  */
-#define CAN_INITSTATUS_FAILED       ((uint8_t)0x00U)  /*!< CAN initialization failed */
-#define CAN_INITSTATUS_SUCCESS      ((uint8_t)0x01U)  /*!< CAN initialization OK */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_operating_mode CAN Operating Mode
-  * @{
-  */
-#define CAN_MODE_NORMAL             ((uint32_t)0x00000000U)                     /*!< Normal mode   */
-#define CAN_MODE_LOOPBACK           ((uint32_t)CAN_BTR_LBKM)                   /*!< Loopback mode */
-#define CAN_MODE_SILENT             ((uint32_t)CAN_BTR_SILM)                   /*!< Silent mode   */
-#define CAN_MODE_SILENT_LOOPBACK    ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM))  /*!< Loopback combined with silent mode */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_synchronisation_jump_width CAN Synchronisation Jump Width
-  * @{
-  */
-#define CAN_SJW_1TQ                 ((uint32_t)0x00000000U)     /*!< 1 time quantum */
-#define CAN_SJW_2TQ                 ((uint32_t)CAN_BTR_SJW_0)  /*!< 2 time quantum */
-#define CAN_SJW_3TQ                 ((uint32_t)CAN_BTR_SJW_1)  /*!< 3 time quantum */
-#define CAN_SJW_4TQ                 ((uint32_t)CAN_BTR_SJW)    /*!< 4 time quantum */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in bit segment 1
-  * @{
-  */
-#define CAN_BS1_1TQ                 ((uint32_t)0x00000000U)                                       /*!< 1 time quantum  */
-#define CAN_BS1_2TQ                 ((uint32_t)CAN_BTR_TS1_0)                                    /*!< 2 time quantum  */
-#define CAN_BS1_3TQ                 ((uint32_t)CAN_BTR_TS1_1)                                    /*!< 3 time quantum  */
-#define CAN_BS1_4TQ                 ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0))                  /*!< 4 time quantum  */
-#define CAN_BS1_5TQ                 ((uint32_t)CAN_BTR_TS1_2)                                    /*!< 5 time quantum  */
-#define CAN_BS1_6TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0))                  /*!< 6 time quantum  */
-#define CAN_BS1_7TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1))                  /*!< 7 time quantum  */
-#define CAN_BS1_8TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))  /*!< 8 time quantum  */
-#define CAN_BS1_9TQ                 ((uint32_t)CAN_BTR_TS1_3)                                    /*!< 9 time quantum  */
-#define CAN_BS1_10TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0))                  /*!< 10 time quantum */
-#define CAN_BS1_11TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1))                  /*!< 11 time quantum */
-#define CAN_BS1_12TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))  /*!< 12 time quantum */
-#define CAN_BS1_13TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2))                  /*!< 13 time quantum */
-#define CAN_BS1_14TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0))  /*!< 14 time quantum */
-#define CAN_BS1_15TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1))  /*!< 15 time quantum */
-#define CAN_BS1_16TQ                ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2
-  * @{
-  */
-#define CAN_BS2_1TQ                 ((uint32_t)0x00000000U)                       /*!< 1 time quantum */
-#define CAN_BS2_2TQ                 ((uint32_t)CAN_BTR_TS2_0)                    /*!< 2 time quantum */
-#define CAN_BS2_3TQ                 ((uint32_t)CAN_BTR_TS2_1)                    /*!< 3 time quantum */
-#define CAN_BS2_4TQ                 ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0))  /*!< 4 time quantum */
-#define CAN_BS2_5TQ                 ((uint32_t)CAN_BTR_TS2_2)                    /*!< 5 time quantum */
-#define CAN_BS2_6TQ                 ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0))  /*!< 6 time quantum */
-#define CAN_BS2_7TQ                 ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1))  /*!< 7 time quantum */
-#define CAN_BS2_8TQ                 ((uint32_t)CAN_BTR_TS2)                      /*!< 8 time quantum */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_filter_mode  CAN Filter Mode
-  * @{
-  */
-#define CAN_FILTERMODE_IDMASK       ((uint8_t)0x00U)  /*!< Identifier mask mode */
-#define CAN_FILTERMODE_IDLIST       ((uint8_t)0x01U)  /*!< Identifier list mode */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_filter_scale CAN Filter Scale
-  * @{
-  */
-#define CAN_FILTERSCALE_16BIT       ((uint8_t)0x00U)  /*!< Two 16-bit filters */
-#define CAN_FILTERSCALE_32BIT       ((uint8_t)0x01U)  /*!< One 32-bit filter  */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_filter_FIFO CAN Filter FIFO
-  * @{
-  */
-#define CAN_FILTER_FIFO0             ((uint8_t)0x00U)  /*!< Filter FIFO 0 assignment for filter x */
-#define CAN_FILTER_FIFO1             ((uint8_t)0x01U)  /*!< Filter FIFO 1 assignment for filter x */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_Identifier_Type CAN Identifier Type
-  * @{
-  */
-#define CAN_ID_STD             ((uint32_t)0x00000000U)  /*!< Standard Id */
-#define CAN_ID_EXT             ((uint32_t)0x00000004U)  /*!< Extended Id */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
-  * @{
-  */
-#define CAN_RTR_DATA                ((uint32_t)0x00000000U)  /*!< Data frame */
-#define CAN_RTR_REMOTE              ((uint32_t)0x00000002U)  /*!< Remote frame */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number Constants
-  * @{
-  */
-#define CAN_FIFO0                   ((uint8_t)0x00U)  /*!< CAN FIFO 0 used to receive */
-#define CAN_FIFO1                   ((uint8_t)0x01U)  /*!< CAN FIFO 1 used to receive */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_flags CAN Flags
-  * @{
-  */
-/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
-   and CAN_ClearFlag() functions. */
-/* If the flag is 0x1XXXXXXX, it means that it can only be used with
-   CAN_GetFlagStatus() function.  */
-
-/* Transmit Flags */
-#define CAN_FLAG_RQCP0             ((uint32_t)0x00000500U)  /*!< Request MailBox0 flag         */
-#define CAN_FLAG_RQCP1             ((uint32_t)0x00000508U)  /*!< Request MailBox1 flag         */
-#define CAN_FLAG_RQCP2             ((uint32_t)0x00000510U)  /*!< Request MailBox2 flag         */
-#define CAN_FLAG_TXOK0             ((uint32_t)0x00000501U)  /*!< Transmission OK MailBox0 flag */
-#define CAN_FLAG_TXOK1             ((uint32_t)0x00000509U)  /*!< Transmission OK MailBox1 flag */
-#define CAN_FLAG_TXOK2             ((uint32_t)0x00000511U)  /*!< Transmission OK MailBox2 flag */
-#define CAN_FLAG_TME0              ((uint32_t)0x0000051AU)  /*!< Transmit mailbox 0 empty flag */
-#define CAN_FLAG_TME1              ((uint32_t)0x0000051BU)  /*!< Transmit mailbox 0 empty flag */
-#define CAN_FLAG_TME2              ((uint32_t)0x0000051CU)  /*!< Transmit mailbox 0 empty flag */
-
-/* Receive Flags */
-#define CAN_FLAG_FF0               ((uint32_t)0x00000203U)  /*!< FIFO 0 Full flag    */
-#define CAN_FLAG_FOV0              ((uint32_t)0x00000204U)  /*!< FIFO 0 Overrun flag */
-
-#define CAN_FLAG_FF1               ((uint32_t)0x00000403U)  /*!< FIFO 1 Full flag    */
-#define CAN_FLAG_FOV1              ((uint32_t)0x00000404U)  /*!< FIFO 1 Overrun flag */
-
-/* Operating Mode Flags */
-#define CAN_FLAG_INAK              ((uint32_t)0x00000100U)  /*!<  Initialization acknowledge flag */
-#define CAN_FLAG_SLAK              ((uint32_t)0x00000101U)  /*!< Sleep acknowledge flag */
-#define CAN_FLAG_ERRI              ((uint32_t)0x00000102U)  /*!<  Error flag */
-#define CAN_FLAG_WKU               ((uint32_t)0x00000103U)  /*!< Wake up flag           */
-#define CAN_FLAG_SLAKI             ((uint32_t)0x00000104U)  /*!< Sleep acknowledge flag */
-
-/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
-         In this case the SLAK bit can be polled.*/
-
-/* Error Flags */
-#define CAN_FLAG_EWG               ((uint32_t)0x00000300U)  /*!< Error warning flag   */
-#define CAN_FLAG_EPV               ((uint32_t)0x00000301U)  /*!< Error passive flag   */
-#define CAN_FLAG_BOF               ((uint32_t)0x00000302U)  /*!< Bus-Off flag         */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_Interrupts CAN Interrupts
-  * @{
-  */
-#define CAN_IT_TME                  ((uint32_t)CAN_IER_TMEIE)   /*!< Transmit mailbox empty interrupt */
-
-/* Receive Interrupts */
-#define CAN_IT_FMP0                 ((uint32_t)CAN_IER_FMPIE0)  /*!< FIFO 0 message pending interrupt */
-#define CAN_IT_FF0                  ((uint32_t)CAN_IER_FFIE0)   /*!< FIFO 0 full interrupt            */
-#define CAN_IT_FOV0                 ((uint32_t)CAN_IER_FOVIE0)  /*!< FIFO 0 overrun interrupt         */
-#define CAN_IT_FMP1                 ((uint32_t)CAN_IER_FMPIE1)  /*!< FIFO 1 message pending interrupt */
-#define CAN_IT_FF1                  ((uint32_t)CAN_IER_FFIE1)   /*!< FIFO 1 full interrupt            */
-#define CAN_IT_FOV1                 ((uint32_t)CAN_IER_FOVIE1)  /*!< FIFO 1 overrun interrupt         */
-
-/* Operating Mode Interrupts */
-#define CAN_IT_WKU                  ((uint32_t)CAN_IER_WKUIE)  /*!< Wake-up interrupt           */
-#define CAN_IT_SLK                  ((uint32_t)CAN_IER_SLKIE)  /*!< Sleep acknowledge interrupt */
-
-/* Error Interrupts */
-#define CAN_IT_EWG                  ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt   */
-#define CAN_IT_EPV                  ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt   */
-#define CAN_IT_BOF                  ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt         */
-#define CAN_IT_LEC                  ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
-#define CAN_IT_ERR                  ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt           */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_Mailboxes_Definition CAN Mailboxes Definition
-  * @{
-  */
-#define CAN_TXMAILBOX_0   ((uint8_t)0x00U)
-#define CAN_TXMAILBOX_1   ((uint8_t)0x01U)
-#define CAN_TXMAILBOX_2   ((uint8_t)0x02U)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup CAN_Exported_Macros CAN Exported Macros
-  * @{
-  */
-
-/** @brief Reset CAN handle state
-  * @param  __HANDLE__: specifies the CAN Handle.
-  * @retval None
-  */
-#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
-
-/**
-  * @brief  Enable the specified CAN interrupts.
-  * @param  __HANDLE__: CAN handle
-  * @param  __INTERRUPT__: CAN Interrupt
-  * @retval None
-  */
-#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the specified CAN interrupts.
-  * @param  __HANDLE__: CAN handle
-  * @param  __INTERRUPT__: CAN Interrupt
-  * @retval None
-  */
-#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
-
-/**
-  * @brief  Return the number of pending received messages.
-  * @param  __HANDLE__: CAN handle
-  * @param  __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
-  * @retval The number of pending message.
-  */
-#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
-((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R & (uint32_t)0x03U)))
-
-/** @brief  Check whether the specified CAN flag is set or not.
-  * @param  __HANDLE__: CAN Handle
-  * @param  __FLAG__: specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg CAN_TSR_RQCP0: Request MailBox0 Flag
-  *            @arg CAN_TSR_RQCP1: Request MailBox1 Flag
-  *            @arg CAN_TSR_RQCP2: Request MailBox2 Flag
-  *            @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
-  *            @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
-  *            @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
-  *            @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
-  *            @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
-  *            @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
-  *            @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
-  *            @arg CAN_FLAG_FF0: FIFO 0 Full Flag
-  *            @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
-  *            @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
-  *            @arg CAN_FLAG_FF1: FIFO 1 Full Flag
-  *            @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
-  *            @arg CAN_FLAG_WKU: Wake up Flag
-  *            @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
-  *            @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
-  *            @arg CAN_FLAG_EWG: Error Warning Flag
-  *            @arg CAN_FLAG_EPV: Error Passive Flag
-  *            @arg CAN_FLAG_BOF: Bus-Off Flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
-((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
-
-/** @brief  Clear the specified CAN pending flag.
-  * @param  __HANDLE__: CAN Handle.
-  * @param  __FLAG__: specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg CAN_TSR_RQCP0: Request MailBox0 Flag
-  *            @arg CAN_TSR_RQCP1: Request MailBox1 Flag
-  *            @arg CAN_TSR_RQCP2: Request MailBox2 Flag
-  *            @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
-  *            @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
-  *            @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
-  *            @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
-  *            @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
-  *            @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
-  *            @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
-  *            @arg CAN_FLAG_FF0: FIFO 0 Full Flag
-  *            @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
-  *            @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
-  *            @arg CAN_FLAG_FF1: FIFO 1 Full Flag
-  *            @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
-  *            @arg CAN_FLAG_WKU: Wake up Flag
-  *            @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
-  *            @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
-((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = ((uint32_t)1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = ((uint32_t)1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = ((uint32_t)1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__HANDLE__)->Instance->MSR) = ((uint32_t)1U << ((__FLAG__) & CAN_FLAG_MASK))))
-
-/** @brief  Check if the specified CAN interrupt source is enabled or disabled.
-  * @param  __HANDLE__: CAN Handle
-  * @param  __INTERRUPT__: specifies the CAN interrupt source to check.
-  *          This parameter can be one of the following values:
-  *             @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
-  *             @arg CAN_IT_FMP0: FIFO0 message pending interrupt enable
-  *             @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable
-  * @retval The new state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/**
-  * @brief  Check the transmission status of a CAN Frame.
-  * @param  __HANDLE__: CAN Handle
-  * @param  __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
-  * @retval The new status of transmission  (TRUE or FALSE).
-  */
-#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
-(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\
- ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\
- ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))
-
-/**
-  * @brief  Release the specified receive FIFO.
-  * @param  __HANDLE__: CAN handle
-  * @param  __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
-  * @retval None
-  */
-#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
-((__HANDLE__)->Instance->RF0R = CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R = CAN_RF1R_RFOM1))
-
-/**
-  * @brief  Cancel a transmit request.
-  * @param  __HANDLE__: CAN Handle
-  * @param  __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
-  * @retval None
-  */
-#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
-(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ0) :\
- ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ1) :\
- ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ2))
-
-/**
-  * @brief  Enable or disable the DBG Freeze for CAN.
-  * @param  __HANDLE__: CAN Handle
-  * @param  __NEWSTATE__: new state of the CAN peripheral.
-  *          This parameter can be: ENABLE (CAN reception/transmission is frozen
-  *          during debug. Reception FIFOs can still be accessed/controlled normally)
-  *          or DISABLE (CAN is working during debug).
-  * @retval None
-  */
-#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
-((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup CAN_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup CAN_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization/de-initialization functions ***********************************/
-HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
-HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
-HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
-void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
-void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
-/**
-  * @}
-  */
-
-/** @addtogroup CAN_Exported_Functions_Group2
-  * @{
-  */
-/* I/O operation functions ******************************************************/
-HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
-HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
-HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
-HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
-void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
-void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
-void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
-void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
-/**
-  * @}
-  */
-
-/** @addtogroup CAN_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral State functions ***************************************************/
-uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
-HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/
-/** @defgroup CAN_Private_Types CAN Private Types
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup CAN_Private_Variables CAN Private Variables
-  * @{
-  */
-
-/**
-  * @}
-  */ 
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup CAN_Private_Constants CAN Private Constants
-  * @{
-  */
-#define CAN_TXSTATUS_NOMAILBOX      ((uint8_t)0x04U)  /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
-#define CAN_FLAG_MASK  ((uint32_t)0x000000FFU)
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup CAN_Private_Macros CAN Private Macros
-  * @{
-  */
-#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
-                           ((MODE) == CAN_MODE_LOOPBACK)|| \
-                           ((MODE) == CAN_MODE_SILENT) || \
-                           ((MODE) == CAN_MODE_SILENT_LOOPBACK))
-#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
-                         ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
-#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
-#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
-#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
-#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U)
-#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
-                                  ((MODE) == CAN_FILTERMODE_IDLIST))
-#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
-                                    ((SCALE) == CAN_FILTERSCALE_32BIT))
-#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
-                                  ((FIFO) == CAN_FILTER_FIFO1))
-#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U)
-
-#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02U))
-#define IS_CAN_STDID(STDID)   ((STDID) <= ((uint32_t)0x7FFU))
-#define IS_CAN_EXTID(EXTID)   ((EXTID) <= ((uint32_t)0x1FFFFFFFU))
-#define IS_CAN_DLC(DLC)       ((DLC) <= ((uint8_t)0x08U))
-
-#define IS_CAN_IDTYPE(IDTYPE)  (((IDTYPE) == CAN_ID_STD) || \
-                                ((IDTYPE) == CAN_ID_EXT))
-#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
-#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup CAN_Private_Functions CAN Private Functions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
-          STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
-          STM32F412Vx || STM32F412Rx || STM32F412Cx */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_CAN_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_cortex.h b/stmhal/hal/f4/inc/stm32f4xx_hal_cortex.h
deleted file mode 100644
index c76edb8443..0000000000
--- a/stmhal/hal/f4/inc/stm32f4xx_hal_cortex.h
+++ /dev/null
@@ -1,467 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_cortex.h
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   Header file of CORTEX HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_CORTEX_H
-#define __STM32F4xx_HAL_CORTEX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup CORTEX
-  * @{
-  */ 
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup CORTEX_Exported_Types Cortex Exported Types
-  * @{
-  */
-
-#if (__MPU_PRESENT == 1)
-/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
-  * @brief  MPU Region initialization structure 
-  * @{
-  */
-typedef struct
-{
-  uint8_t                Enable;                /*!< Specifies the status of the region. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */
-  uint8_t                Number;                /*!< Specifies the number of the region to protect. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */
-  uint32_t               BaseAddress;           /*!< Specifies the base address of the region to protect.                           */
-  uint8_t                Size;                  /*!< Specifies the size of the region to protect. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */
-  uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable. 
-                                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */         
-  uint8_t                TypeExtField;          /*!< Specifies the TEX field level.
-                                                     This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */                 
-  uint8_t                AccessPermission;      /*!< Specifies the region access permission type. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */
-  uint8_t                DisableExec;           /*!< Specifies the instruction access status. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */
-  uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */
-  uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */
-  uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */
-}MPU_Region_InitTypeDef;
-/**
-  * @}
-  */
-#endif /* __MPU_PRESENT */
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
-  * @{
-  */
-
-/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
-  * @{
-  */
-#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007U) /*!< 0 bits for pre-emption priority
-                                                                 4 bits for subpriority */
-#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006U) /*!< 1 bits for pre-emption priority
-                                                                 3 bits for subpriority */
-#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005U) /*!< 2 bits for pre-emption priority
-                                                                 2 bits for subpriority */
-#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004U) /*!< 3 bits for pre-emption priority
-                                                                 1 bits for subpriority */
-#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003U) /*!< 4 bits for pre-emption priority
-                                                                 0 bits for subpriority */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source 
-  * @{
-  */
-#define SYSTICK_CLKSOURCE_HCLK_DIV8    ((uint32_t)0x00000000U)
-#define SYSTICK_CLKSOURCE_HCLK         ((uint32_t)0x00000004U)
-
-/**
-  * @}
-  */
-
-#if (__MPU_PRESENT == 1)
-/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
-  * @{
-  */
-#define  MPU_HFNMI_PRIVDEF_NONE      ((uint32_t)0x00000000U)  
-#define  MPU_HARDFAULT_NMI           ((uint32_t)0x00000002U)
-#define  MPU_PRIVILEGED_DEFAULT      ((uint32_t)0x00000004U)
-#define  MPU_HFNMI_PRIVDEF           ((uint32_t)0x00000006U)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
-  * @{
-  */
-#define  MPU_REGION_ENABLE     ((uint8_t)0x01U)
-#define  MPU_REGION_DISABLE    ((uint8_t)0x00U)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
-  * @{
-  */
-#define  MPU_INSTRUCTION_ACCESS_ENABLE      ((uint8_t)0x00U)
-#define  MPU_INSTRUCTION_ACCESS_DISABLE     ((uint8_t)0x01U)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
-  * @{
-  */
-#define  MPU_ACCESS_SHAREABLE        ((uint8_t)0x01U)
-#define  MPU_ACCESS_NOT_SHAREABLE    ((uint8_t)0x00U)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
-  * @{
-  */
-#define  MPU_ACCESS_CACHEABLE         ((uint8_t)0x01U)
-#define  MPU_ACCESS_NOT_CACHEABLE     ((uint8_t)0x00U)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
-  * @{
-  */
-#define  MPU_ACCESS_BUFFERABLE         ((uint8_t)0x01U)
-#define  MPU_ACCESS_NOT_BUFFERABLE     ((uint8_t)0x00U)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
-  * @{
-  */
-#define  MPU_TEX_LEVEL0    ((uint8_t)0x00U)
-#define  MPU_TEX_LEVEL1    ((uint8_t)0x01U)
-#define  MPU_TEX_LEVEL2    ((uint8_t)0x02U)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
-  * @{
-  */
-#define   MPU_REGION_SIZE_32B      ((uint8_t)0x04U)
-#define   MPU_REGION_SIZE_64B      ((uint8_t)0x05U)
-#define   MPU_REGION_SIZE_128B     ((uint8_t)0x06U)
-#define   MPU_REGION_SIZE_256B     ((uint8_t)0x07U)
-#define   MPU_REGION_SIZE_512B     ((uint8_t)0x08U)
-#define   MPU_REGION_SIZE_1KB      ((uint8_t)0x09U)
-#define   MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU)
-#define   MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU)
-#define   MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU)
-#define   MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU)
-#define   MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU)
-#define   MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU)
-#define   MPU_REGION_SIZE_128KB    ((uint8_t)0x10U)
-#define   MPU_REGION_SIZE_256KB    ((uint8_t)0x11U)
-#define   MPU_REGION_SIZE_512KB    ((uint8_t)0x12U)
-#define   MPU_REGION_SIZE_1MB      ((uint8_t)0x13U)
-#define   MPU_REGION_SIZE_2MB      ((uint8_t)0x14U)
-#define   MPU_REGION_SIZE_4MB      ((uint8_t)0x15U)
-#define   MPU_REGION_SIZE_8MB      ((uint8_t)0x16U)
-#define   MPU_REGION_SIZE_16MB     ((uint8_t)0x17U)
-#define   MPU_REGION_SIZE_32MB     ((uint8_t)0x18U)
-#define   MPU_REGION_SIZE_64MB     ((uint8_t)0x19U)
-#define   MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU)
-#define   MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU)
-#define   MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU)
-#define   MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU)
-#define   MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU)
-#define   MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU)
-/**
-  * @}
-  */
-   
-/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 
-  * @{
-  */
-#define  MPU_REGION_NO_ACCESS      ((uint8_t)0x00U)
-#define  MPU_REGION_PRIV_RW        ((uint8_t)0x01U)
-#define  MPU_REGION_PRIV_RW_URO    ((uint8_t)0x02U)
-#define  MPU_REGION_FULL_ACCESS    ((uint8_t)0x03U)
-#define  MPU_REGION_PRIV_RO        ((uint8_t)0x05U)
-#define  MPU_REGION_PRIV_RO_URO    ((uint8_t)0x06U)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
-  * @{
-  */
-#define  MPU_REGION_NUMBER0    ((uint8_t)0x00U)
-#define  MPU_REGION_NUMBER1    ((uint8_t)0x01U)
-#define  MPU_REGION_NUMBER2    ((uint8_t)0x02U)
-#define  MPU_REGION_NUMBER3    ((uint8_t)0x03U)
-#define  MPU_REGION_NUMBER4    ((uint8_t)0x04U)
-#define  MPU_REGION_NUMBER5    ((uint8_t)0x05U)
-#define  MPU_REGION_NUMBER6    ((uint8_t)0x06U)
-#define  MPU_REGION_NUMBER7    ((uint8_t)0x07U)
-/**
-  * @}
-  */
-#endif /* __MPU_PRESENT */
-
-/**
-  * @}
-  */
-
-
-/* Exported Macros -----------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup CORTEX_Exported_Functions
-  * @{
-  */
-  
-/** @addtogroup CORTEX_Exported_Functions_Group1
- * @{
- */
-/* Initialization and de-initialization functions *****************************/
-void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
-void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
-void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
-void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
-void HAL_NVIC_SystemReset(void);
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
-/**
-  * @}
-  */
-
-/** @addtogroup CORTEX_Exported_Functions_Group2
- * @{
- */
-/* Peripheral Control functions ***********************************************/
-#if (__MPU_PRESENT == 1)
-void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
-#endif /* __MPU_PRESENT */
-uint32_t HAL_NVIC_GetPriorityGrouping(void);
-void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
-uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
-void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
-void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
-uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
-void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
-void HAL_SYSTICK_IRQHandler(void);
-void HAL_SYSTICK_Callback(void);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
-  * @{
-  */
-#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
-                                       ((GROUP) == NVIC_PRIORITYGROUP_1) || \
-                                       ((GROUP) == NVIC_PRIORITYGROUP_2) || \
-                                       ((GROUP) == NVIC_PRIORITYGROUP_3) || \
-                                       ((GROUP) == NVIC_PRIORITYGROUP_4))
-
-#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10U)
-
-#define IS_NVIC_SUB_PRIORITY(PRIORITY)         ((PRIORITY) < 0x10U)
-
-#define IS_NVIC_DEVICE_IRQ(IRQ)                ((IRQ) >= (IRQn_Type)0x00U)
-
-#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
-                                       ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
-
-#if (__MPU_PRESENT == 1U)
-#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
-                                     ((STATE) == MPU_REGION_DISABLE))
-
-#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
-                                          ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
-
-#define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_SHAREABLE) || \
-                                          ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
-
-#define IS_MPU_ACCESS_CACHEABLE(STATE)   (((STATE) == MPU_ACCESS_CACHEABLE) || \
-                                          ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
-
-#define IS_MPU_ACCESS_BUFFERABLE(STATE)   (((STATE) == MPU_ACCESS_BUFFERABLE) || \
-                                          ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
-
-#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0)  || \
-                                ((TYPE) == MPU_TEX_LEVEL1)  || \
-                                ((TYPE) == MPU_TEX_LEVEL2))
-
-#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS)   || \
-                                                  ((TYPE) == MPU_REGION_PRIV_RW)     || \
-                                                  ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
-                                                  ((TYPE) == MPU_REGION_FULL_ACCESS) || \
-                                                  ((TYPE) == MPU_REGION_PRIV_RO)     || \
-                                                  ((TYPE) == MPU_REGION_PRIV_RO_URO))
-
-#define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER1) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER2) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER3) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER4) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER5) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER6) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER7))
-
-#define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_32B)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_64B)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_128B)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_256B)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_512B)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_1KB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_2KB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_4KB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_8KB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_16KB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_32KB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_64KB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_128KB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_256KB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_512KB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_1MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_2MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_4MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_8MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_16MB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_32MB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_64MB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_128MB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_256MB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_512MB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_1GB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_2GB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_4GB))
-
-#define IS_MPU_SUB_REGION_DISABLE(SUBREGION)  ((SUBREGION) < (uint16_t)0x00FFU)
-#endif /* __MPU_PRESENT */
-
-/**                                                                          
-  * @}                                                                  
-  */                                                                            
-                                                                                   
-/* Private functions ---------------------------------------------------------*/   
-/** @defgroup CORTEX_Private_Functions CORTEX Private Functions
-  * @brief    CORTEX private  functions 
-  * @{
-  */
-
-#if (__MPU_PRESENT == 1)
-/**
-  * @brief  Disables the MPU
-  * @retval None
-  */
-__STATIC_INLINE void HAL_MPU_Disable(void)
-{
-  /* Disable fault exceptions */
-  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
-  
-  /* Disable the MPU */
-  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
-}
-
-/**
-  * @brief  Enables the MPU
-  * @param  MPU_Control: Specifies the control mode of the MPU during hard fault, 
-  *          NMI, FAULTMASK and privileged access to the default memory 
-  *          This parameter can be one of the following values:
-  *            @arg MPU_HFNMI_PRIVDEF_NONE
-  *            @arg MPU_HARDFAULT_NMI
-  *            @arg MPU_PRIVILEGED_DEFAULT
-  *            @arg MPU_HFNMI_PRIVDEF
-  * @retval None
-  */
-__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
-{
-  /* Enable the MPU */
-  MPU->CTRL   = MPU_Control | MPU_CTRL_ENABLE_Msk;
-  
-  /* Enable fault exceptions */
-  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
-}
-#endif /* __MPU_PRESENT */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_CORTEX_H */
- 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_dac.h b/stmhal/hal/f4/inc/stm32f4xx_hal_dac.h
deleted file mode 100644
index 6d67459f4d..0000000000
--- a/stmhal/hal/f4/inc/stm32f4xx_hal_dac.h
+++ /dev/null
@@ -1,413 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_dac.h
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   Header file of DAC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_DAC_H
-#define __STM32F4xx_HAL_DAC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
-    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup DAC
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup DAC_Exported_Types DAC Exported Types
-  * @{
-  */
-
-/** 
-  * @brief HAL State structures definition
-  */
-typedef enum
-{
-  HAL_DAC_STATE_RESET             = 0x00U,  /*!< DAC not yet initialized or disabled  */
-  HAL_DAC_STATE_READY             = 0x01U,  /*!< DAC initialized and ready for use    */
-  HAL_DAC_STATE_BUSY              = 0x02U,  /*!< DAC internal processing is ongoing   */
-  HAL_DAC_STATE_TIMEOUT           = 0x03U,  /*!< DAC timeout state                    */
-  HAL_DAC_STATE_ERROR             = 0x04U   /*!< DAC error state                      */
-}HAL_DAC_StateTypeDef;
- 
-/** 
-  * @brief DAC handle Structure definition
-  */
-typedef struct
-{
-  DAC_TypeDef                 *Instance;     /*!< Register base address             */
-
-  __IO HAL_DAC_StateTypeDef   State;         /*!< DAC communication state           */
-
-  HAL_LockTypeDef             Lock;          /*!< DAC locking object                */
-
-  DMA_HandleTypeDef           *DMA_Handle1;  /*!< Pointer DMA handler for channel 1 */
-
-  DMA_HandleTypeDef           *DMA_Handle2;  /*!< Pointer DMA handler for channel 2 */
-
-  __IO uint32_t               ErrorCode;     /*!< DAC Error code                    */
-
-}DAC_HandleTypeDef;
-
-/** 
-  * @brief DAC Configuration regular Channel structure definition
-  */
-typedef struct
-{
-  uint32_t DAC_Trigger;       /*!< Specifies the external trigger for the selected DAC channel.
-                                   This parameter can be a value of @ref DAC_trigger_selection */
-
-  uint32_t DAC_OutputBuffer;  /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
-                                   This parameter can be a value of @ref DAC_output_buffer */
-}DAC_ChannelConfTypeDef;
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup DAC_Exported_Constants DAC Exported Constants
-  * @{
-  */
-
-/** @defgroup DAC_Error_Code DAC Error Code
-  * @{
-  */
-#define  HAL_DAC_ERROR_NONE              0x00U    /*!< No error                          */
-#define  HAL_DAC_ERROR_DMAUNDERRUNCH1    0x01U    /*!< DAC channel1 DAM underrun error   */
-#define  HAL_DAC_ERROR_DMAUNDERRUNCH2    0x02U    /*!< DAC channel2 DAM underrun error   */
-#define  HAL_DAC_ERROR_DMA               0x04U    /*!< DMA error                         */
-/**
-  * @}
-  */
-
-/** @defgroup DAC_trigger_selection DAC Trigger Selection
-  * @{
-  */
-
-#define DAC_TRIGGER_NONE                   ((uint32_t)0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register 
-                                                                       has been loaded, and not by external trigger */
-#define DAC_TRIGGER_T2_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T4_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T5_TRGO                ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T6_TRGO                ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T7_TRGO                ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T8_TRGO                ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */                                                                       
-
-#define DAC_TRIGGER_EXT_IT9                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_SOFTWARE               ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
-/**
-  * @}
-  */
-
-/** @defgroup DAC_output_buffer  DAC Output Buffer
-  * @{
-  */
-#define DAC_OUTPUTBUFFER_ENABLE            ((uint32_t)0x00000000U)
-#define DAC_OUTPUTBUFFER_DISABLE           ((uint32_t)DAC_CR_BOFF1)
-/**
-  * @}
-  */
-
-/** @defgroup DAC_Channel_selection DAC Channel Selection
-  * @{
-  */
-#define DAC_CHANNEL_1                      ((uint32_t)0x00000000U)
-#define DAC_CHANNEL_2                      ((uint32_t)0x00000010U)
-/**
-  * @}
-  */
-
-/** @defgroup DAC_data_alignment DAC Data Alignment
-  * @{
-  */
-#define DAC_ALIGN_12B_R                    ((uint32_t)0x00000000U)
-#define DAC_ALIGN_12B_L                    ((uint32_t)0x00000004U)
-#define DAC_ALIGN_8B_R                     ((uint32_t)0x00000008U)
-/**
-  * @}
-  */
-
-/** @defgroup DAC_flags_definition DAC Flags Definition
-  * @{
-  */ 
-#define DAC_FLAG_DMAUDR1                   ((uint32_t)DAC_SR_DMAUDR1)
-#define DAC_FLAG_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)
-/**
-  * @}
-  */
-
-/** @defgroup DAC_IT_definition DAC IT Definition
-  * @{
-  */ 
-#define DAC_IT_DMAUDR1                   ((uint32_t)DAC_SR_DMAUDR1)
-#define DAC_IT_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup DAC_Exported_Macros DAC Exported Macros
-  * @{
-  */
-
-/** @brief Reset DAC handle state
-  * @param  __HANDLE__: specifies the DAC handle.
-  * @retval None
-  */
-#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
-
-/** @brief Enable the DAC channel
-  * @param  __HANDLE__: specifies the DAC handle.
-  * @param  __DAC_Channel__: specifies the DAC channel
-  * @retval None
-  */
-#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR |=  (DAC_CR_EN1 << (__DAC_Channel__)))
-
-/** @brief Disable the DAC channel
-  * @param  __HANDLE__: specifies the DAC handle
-  * @param  __DAC_Channel__: specifies the DAC channel.
-  * @retval None
-  */
-#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR &=  ~(DAC_CR_EN1 << (__DAC_Channel__)))
-
-/** @brief Enable the DAC interrupt
-  * @param  __HANDLE__: specifies the DAC handle
-  * @param  __INTERRUPT__: specifies the DAC interrupt.
-  * @retval None
-  */
-#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
-
-/** @brief Disable the DAC interrupt
-  * @param  __HANDLE__: specifies the DAC handle
-  * @param  __INTERRUPT__: specifies the DAC interrupt.
-  * @retval None
-  */
-#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
-
-/** @brief  Checks if the specified DAC interrupt source is enabled or disabled.
-  * @param __HANDLE__: DAC handle
-  * @param __INTERRUPT__: DAC interrupt source to check
-  *          This parameter can be any combination of the following values:
-  *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
-  *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
-  * @retval State of interruption (SET or RESET)
-  */
-#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/** @brief  Get the selected DAC's flag status.
-  * @param  __HANDLE__: specifies the DAC handle.
-  * @param  __FLAG__: specifies the flag to clear.
-  *         This parameter can be any combination of the following values:
-  *            @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag
-  *            @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag
-  * @retval None
-  */
-#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Clear the DAC's flag.
-  * @param  __HANDLE__: specifies the DAC handle.
-  * @param  __FLAG__: specifies the flag to clear.
-  *         This parameter can be any combination of the following values:
-  *            @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag
-  *            @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag
-  * @retval None
-  */
-#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
-/**
-  * @}
-  */
-
-/* Include DAC HAL Extension module */
-#include "stm32f4xx_hal_dac_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup DAC_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup DAC_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization/de-initialization functions *********************************/
-HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
-HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
-void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
-void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
-/**
-  * @}
-  */
-
-/** @addtogroup DAC_Exported_Functions_Group2
-  * @{
-  */
-/* I/O operation functions ****************************************************/
-HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
-HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
-uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
-/**
-  * @}
-  */
-
-/** @addtogroup DAC_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
-/**
-  * @}
-  */
-
-/** @addtogroup DAC_Exported_Functions_Group4
-  * @{
-  */
-/* Peripheral State functions *************************************************/
-HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
-void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
-uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
-
-void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
-void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
-void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
-void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup DAC_Private_Constants DAC Private Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup DAC_Private_Macros DAC Private Macros
-  * @{
-  */
-#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U)
-#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
-                             ((ALIGN) == DAC_ALIGN_12B_L) || \
-                             ((ALIGN) == DAC_ALIGN_8B_R))
-#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
-                                 ((CHANNEL) == DAC_CHANNEL_2))
-#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
-                                           ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
-
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
-                                 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
-
-/** @brief Set DHR12R1 alignment
-  * @param  __ALIGNMENT__: specifies the DAC alignment
-  * @retval None
-  */
-#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008U) + (__ALIGNMENT__))
-
-/** @brief  Set DHR12R2 alignment
-  * @param  __ALIGNMENT__: specifies the DAC alignment
-  * @retval None
-  */
-#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014U) + (__ALIGNMENT__))
-
-/** @brief  Set DHR12RD alignment
-  * @param  __ALIGNMENT__: specifies the DAC alignment
-  * @retval None
-  */
-#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020U) + (__ALIGNMENT__))
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup DAC_Private_Functions DAC Private Functions
-  * @{
-  */
-/**
-  * @}
-  */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
-          STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
-          STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_HAL_DAC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_dac_ex.h b/stmhal/hal/f4/inc/stm32f4xx_hal_dac_ex.h
deleted file mode 100644
index 7edb995efc..0000000000
--- a/stmhal/hal/f4/inc/stm32f4xx_hal_dac_ex.h
+++ /dev/null
@@ -1,200 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_dac.h
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   Header file of DAC HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_DAC_EX_H
-#define __STM32F4xx_HAL_DAC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
-    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup DACEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup DACEx_Exported_Constants DAC Exported Constants
-  * @{
-  */
-
-/** @defgroup DACEx_lfsrunmask_triangleamplitude DAC LFS Run Mask Triangle Amplitude
-  * @{
-  */
-#define DAC_LFSRUNMASK_BIT0                ((uint32_t)0x00000000U) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
-#define DAC_LFSRUNMASK_BITS1_0             ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS2_0             ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS3_0             ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS4_0             ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS5_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS6_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS7_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS8_0             ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS9_0             ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS10_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS11_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
-#define DAC_TRIANGLEAMPLITUDE_1            ((uint32_t)0x00000000U) /*!< Select max triangle amplitude of 1 */
-#define DAC_TRIANGLEAMPLITUDE_3            ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
-#define DAC_TRIANGLEAMPLITUDE_7            ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
-#define DAC_TRIANGLEAMPLITUDE_15           ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
-#define DAC_TRIANGLEAMPLITUDE_31           ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */
-#define DAC_TRIANGLEAMPLITUDE_63           ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
-#define DAC_TRIANGLEAMPLITUDE_127          ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */
-#define DAC_TRIANGLEAMPLITUDE_255          ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
-#define DAC_TRIANGLEAMPLITUDE_511          ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */
-#define DAC_TRIANGLEAMPLITUDE_1023         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
-#define DAC_TRIANGLEAMPLITUDE_2047         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
-#define DAC_TRIANGLEAMPLITUDE_4095         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup DACEx_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup DACEx_Exported_Functions_Group1
-  * @{
-  */
-/* Extension features functions ***********************************************/
-uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
-HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
-HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
-HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
-
-void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup DACEx_Private_Constants DAC Private Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup DACEx_Private_Macros DAC Private Macros
-  * @{
-  */
-#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup DACEx_Private_Functions DAC Private Functions
-  * @{
-  */
-void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
-void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
-void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); 
-/**
-  * @}
-  */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
-          STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
-          STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_HAL_DAC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_def.h b/stmhal/hal/f4/inc/stm32f4xx_hal_def.h
deleted file mode 100644
index e7858ac2c9..0000000000
--- a/stmhal/hal/f4/inc/stm32f4xx_hal_def.h
+++ /dev/null
@@ -1,216 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_def.h
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   This file contains HAL common defines, enumeration, macros and 
-  *          structures definitions. 
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_DEF
-#define __STM32F4xx_HAL_DEF
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-#include "Legacy/stm32_hal_legacy.h"
-#ifndef NULL
-#define NULL (void*)0
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-
-/** 
-  * @brief  HAL Status structures definition  
-  */  
-typedef enum 
-{
-  HAL_OK       = 0x00U,
-  HAL_ERROR    = 0x01U,
-  HAL_BUSY     = 0x02U,
-  HAL_TIMEOUT  = 0x03U
-} HAL_StatusTypeDef;
-
-/** 
-  * @brief  HAL Lock structures definition  
-  */
-typedef enum 
-{
-  HAL_UNLOCKED = 0x00U,
-  HAL_LOCKED   = 0x01U  
-} HAL_LockTypeDef;
-
-/* Exported macro ------------------------------------------------------------*/
-#define HAL_MAX_DELAY      0xFFFFFFFFU
-
-#define HAL_IS_BIT_SET(REG, BIT)         (((REG) & (BIT)) != RESET)
-#define HAL_IS_BIT_CLR(REG, BIT)         (((REG) & (BIT)) == RESET)
-
-#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__)               \
-                        do{                                                      \
-                              (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
-                              (__DMA_HANDLE__).Parent = (__HANDLE__);             \
-                          } while(0)
-
-#define UNUSED(x) ((void)(x))
-
-/** @brief Reset the Handle's State field.
-  * @param __HANDLE__: specifies the Peripheral Handle.
-  * @note  This macro can be used for the following purpose: 
-  *          - When the Handle is declared as local variable; before passing it as parameter
-  *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro 
-  *            to set to 0 the Handle's "State" field.
-  *            Otherwise, "State" field may have any random value and the first time the function 
-  *            HAL_PPP_Init() is called, the low level hardware initialization will be missed
-  *            (i.e. HAL_PPP_MspInit() will not be executed).
-  *          - When there is a need to reconfigure the low level hardware: instead of calling
-  *            HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
-  *            In this later function, when the Handle's "State" field is set to 0, it will execute the function
-  *            HAL_PPP_MspInit() which will reconfigure the low level hardware.
-  * @retval None
-  */
-#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
-
-#if (USE_RTOS == 1)
-  /* Reserved for future use */
-  #error "USE_RTOS should be 0 in the current HAL release"
-#else
-  #define __HAL_LOCK(__HANDLE__)                                           \
-                                do{                                        \
-                                    if((__HANDLE__)->Lock == HAL_LOCKED)   \
-                                    {                                      \
-                                       return HAL_BUSY;                    \
-                                    }                                      \
-                                    else                                   \
-                                    {                                      \
-                                       (__HANDLE__)->Lock = HAL_LOCKED;    \
-                                    }                                      \
-                                  }while (0)
-
-  #define __HAL_UNLOCK(__HANDLE__)                                          \
-                                  do{                                       \
-                                      (__HANDLE__)->Lock = HAL_UNLOCKED;    \
-                                    }while (0)
-#endif /* USE_RTOS */
-
-#if  defined ( __GNUC__ )
-  #ifndef __weak
-    #define __weak   __attribute__((weak))
-  #endif /* __weak */
-  #ifndef __packed
-    #define __packed __attribute__((__packed__))
-  #endif /* __packed */
-#endif /* __GNUC__ */
-
-
-/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
-#if defined   (__GNUC__)        /* GNU Compiler */
-  #ifndef __ALIGN_END
-    #define __ALIGN_END    __attribute__ ((aligned (4)))
-  #endif /* __ALIGN_END */
-  #ifndef __ALIGN_BEGIN  
-    #define __ALIGN_BEGIN
-  #endif /* __ALIGN_BEGIN */
-#else
-  #ifndef __ALIGN_END
-    #define __ALIGN_END
-  #endif /* __ALIGN_END */
-  #ifndef __ALIGN_BEGIN      
-    #if defined   (__CC_ARM)      /* ARM Compiler */
-      #define __ALIGN_BEGIN    __align(4)  
-    #elif defined (__ICCARM__)    /* IAR Compiler */
-      #define __ALIGN_BEGIN 
-    #endif /* __CC_ARM */
-  #endif /* __ALIGN_BEGIN */
-#endif /* __GNUC__ */
-
-
-/** 
-  * @brief  __RAM_FUNC definition
-  */ 
-#if defined ( __CC_ARM   )
-/* ARM Compiler
-   ------------
-   RAM functions are defined using the toolchain options. 
-   Functions that are executed in RAM should reside in a separate source module.
-   Using the 'Options for File' dialog you can simply change the 'Code / Const' 
-   area of a module to a memory space in physical RAM.
-   Available memory areas are declared in the 'Target' tab of the 'Options for Target'
-   dialog. 
-*/
-#define __RAM_FUNC HAL_StatusTypeDef 
-
-#elif defined ( __ICCARM__ )
-/* ICCARM Compiler
-   ---------------
-   RAM functions are defined using a specific toolchain keyword "__ramfunc". 
-*/
-#define __RAM_FUNC __ramfunc HAL_StatusTypeDef
-
-#elif defined   (  __GNUC__  )
-/* GNU Compiler
-   ------------
-  RAM functions are defined using a specific toolchain attribute 
-   "__attribute__((section(".RamFunc")))".
-*/
-#define __RAM_FUNC HAL_StatusTypeDef  __attribute__((section(".RamFunc")))
-
-#endif
-
-/** 
-  * @brief  __NOINLINE definition
-  */ 
-#if defined ( __CC_ARM   ) || defined   (  __GNUC__  )
-/* ARM & GNUCompiler 
-   ---------------- 
-*/
-#define __NOINLINE __attribute__ ( (noinline) )
-
-#elif defined ( __ICCARM__ )
-/* ICCARM Compiler
-   ---------------
-*/
-#define __NOINLINE _Pragma("optimize = no_inline")
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ___STM32F4xx_HAL_DEF */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_dma.h b/stmhal/hal/f4/inc/stm32f4xx_hal_dma.h
deleted file mode 100644
index a114c07c68..0000000000
--- a/stmhal/hal/f4/inc/stm32f4xx_hal_dma.h
+++ /dev/null
@@ -1,793 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_dma.h
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   Header file of DMA HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_DMA_H
-#define __STM32F4xx_HAL_DMA_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup DMA
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Types DMA Exported Types
-  * @brief    DMA Exported Types 
-  * @{
-  */
-   
-/** 
-  * @brief  DMA Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t Channel;              /*!< Specifies the channel used for the specified stream. 
-                                      This parameter can be a value of @ref DMA_Channel_selection                    */
-
-  uint32_t Direction;            /*!< Specifies if the data will be transferred from memory to peripheral, 
-                                      from memory to memory or from peripheral to memory.
-                                      This parameter can be a value of @ref DMA_Data_transfer_direction              */
-
-  uint32_t PeriphInc;            /*!< Specifies whether the Peripheral address register should be incremented or not.
-                                      This parameter can be a value of @ref DMA_Peripheral_incremented_mode          */
-
-  uint32_t MemInc;               /*!< Specifies whether the memory address register should be incremented or not.
-                                      This parameter can be a value of @ref DMA_Memory_incremented_mode              */
-
-  uint32_t PeriphDataAlignment;  /*!< Specifies the Peripheral data width.
-                                      This parameter can be a value of @ref DMA_Peripheral_data_size                 */
-
-  uint32_t MemDataAlignment;     /*!< Specifies the Memory data width.
-                                      This parameter can be a value of @ref DMA_Memory_data_size                     */
-
-  uint32_t Mode;                 /*!< Specifies the operation mode of the DMAy Streamx.
-                                      This parameter can be a value of @ref DMA_mode
-                                      @note The circular buffer mode cannot be used if the memory-to-memory
-                                            data transfer is configured on the selected Stream                        */
-
-  uint32_t Priority;             /*!< Specifies the software priority for the DMAy Streamx.
-                                      This parameter can be a value of @ref DMA_Priority_level                       */
-
-  uint32_t FIFOMode;             /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
-                                      This parameter can be a value of @ref DMA_FIFO_direct_mode
-                                      @note The Direct mode (FIFO mode disabled) cannot be used if the 
-                                            memory-to-memory data transfer is configured on the selected stream       */
-
-  uint32_t FIFOThreshold;        /*!< Specifies the FIFO threshold level.
-                                      This parameter can be a value of @ref DMA_FIFO_threshold_level                  */
-
-  uint32_t MemBurst;             /*!< Specifies the Burst transfer configuration for the memory transfers. 
-                                      It specifies the amount of data to be transferred in a single non interruptible
-                                      transaction.
-                                      This parameter can be a value of @ref DMA_Memory_burst 
-                                      @note The burst mode is possible only if the address Increment mode is enabled. */
-
-  uint32_t PeriphBurst;          /*!< Specifies the Burst transfer configuration for the peripheral transfers. 
-                                      It specifies the amount of data to be transferred in a single non interruptible 
-                                      transaction. 
-                                      This parameter can be a value of @ref DMA_Peripheral_burst
-                                      @note The burst mode is possible only if the address Increment mode is enabled. */
-}DMA_InitTypeDef;
-
-
-/** 
-  * @brief  HAL DMA State structures definition
-  */
-typedef enum
-{
-  HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled */
-  HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use   */
-  HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing              */
-  HAL_DMA_STATE_TIMEOUT           = 0x03U,  /*!< DMA timeout state                   */
-  HAL_DMA_STATE_ERROR             = 0x04U,  /*!< DMA error state                     */
-  HAL_DMA_STATE_ABORT             = 0x05U,  /*!< DMA Abort state                     */
-}HAL_DMA_StateTypeDef;
-
-/** 
-  * @brief  HAL DMA Error Code structure definition
-  */
-typedef enum
-{
-  HAL_DMA_FULL_TRANSFER      = 0x00U,    /*!< Full transfer     */
-  HAL_DMA_HALF_TRANSFER      = 0x01U     /*!< Half Transfer     */
-}HAL_DMA_LevelCompleteTypeDef;
-
-/** 
-  * @brief  HAL DMA Error Code structure definition
-  */
-typedef enum
-{
-  HAL_DMA_XFER_CPLT_CB_ID          = 0x00U,    /*!< Full transfer     */
-  HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01U,    /*!< Half Transfer     */
-  HAL_DMA_XFER_M1CPLT_CB_ID        = 0x02U,    /*!< M1 Full Transfer  */
-  HAL_DMA_XFER_M1HALFCPLT_CB_ID    = 0x03U,    /*!< M1 Half Transfer  */
-  HAL_DMA_XFER_ERROR_CB_ID         = 0x04U,    /*!< Error             */
-  HAL_DMA_XFER_ABORT_CB_ID         = 0x05U,    /*!< Abort             */
-  HAL_DMA_XFER_ALL_CB_ID           = 0x06U     /*!< All               */
-}HAL_DMA_CallbackIDTypeDef;
-
-/** 
-  * @brief  DMA handle Structure definition
-  */
-typedef struct __DMA_HandleTypeDef
-{
-  DMA_Stream_TypeDef         *Instance;                                                    /*!< Register base address                  */
-
-  DMA_InitTypeDef            Init;                                                         /*!< DMA communication parameters           */ 
-
-  HAL_LockTypeDef            Lock;                                                         /*!< DMA locking object                     */  
-
-  __IO HAL_DMA_StateTypeDef  State;                                                        /*!< DMA transfer state                     */
-
-  void                       *Parent;                                                      /*!< Parent object state                    */ 
-
-  void                       (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA transfer complete callback         */
-
-  void                       (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback    */
-
-  void                       (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer complete Memory1 callback */
-  
-  void                       (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer Half complete Memory1 callback */
-  
-  void                       (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer error callback            */
-  
-  void                       (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer Abort callback            */  
-
- __IO uint32_t               ErrorCode;                                                    /*!< DMA Error code                          */
-  
- uint32_t                    StreamBaseAddress;                                            /*!< DMA Stream Base Address                */
-
- uint32_t                    StreamIndex;                                                  /*!< DMA Stream Index                       */
- 
-}DMA_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Constants DMA Exported Constants
-  * @brief    DMA Exported constants 
-  * @{
-  */
-
-/** @defgroup DMA_Error_Code DMA Error Code
-  * @brief    DMA Error Code 
-  * @{
-  */ 
-#define HAL_DMA_ERROR_NONE            ((uint32_t)0x00000000U)    /*!< No error                               */
-#define HAL_DMA_ERROR_TE              ((uint32_t)0x00000001U)    /*!< Transfer error                         */
-#define HAL_DMA_ERROR_FE              ((uint32_t)0x00000002U)    /*!< FIFO error                             */
-#define HAL_DMA_ERROR_DME             ((uint32_t)0x00000004U)    /*!< Direct Mode error                      */
-#define HAL_DMA_ERROR_TIMEOUT         ((uint32_t)0x00000020U)    /*!< Timeout error                          */
-#define HAL_DMA_ERROR_PARAM           ((uint32_t)0x00000040U)    /*!< Parameter error                        */
-#define HAL_DMA_ERROR_NO_XFER         ((uint32_t)0x00000080U)    /*!< Abort requested with no Xfer ongoing   */ 
-#define HAL_DMA_ERROR_NOT_SUPPORTED   ((uint32_t)0x00000100U)    /*!< Not supported mode                     */     
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Channel_selection DMA Channel selection
-  * @brief    DMA channel selection 
-  * @{
-  */ 
-#define DMA_CHANNEL_0        ((uint32_t)0x00000000U)  /*!< DMA Channel 0 */
-#define DMA_CHANNEL_1        ((uint32_t)0x02000000U)  /*!< DMA Channel 1 */
-#define DMA_CHANNEL_2        ((uint32_t)0x04000000U)  /*!< DMA Channel 2 */
-#define DMA_CHANNEL_3        ((uint32_t)0x06000000U)  /*!< DMA Channel 3 */
-#define DMA_CHANNEL_4        ((uint32_t)0x08000000U)  /*!< DMA Channel 4 */
-#define DMA_CHANNEL_5        ((uint32_t)0x0A000000U)  /*!< DMA Channel 5 */
-#define DMA_CHANNEL_6        ((uint32_t)0x0C000000U)  /*!< DMA Channel 6 */
-#define DMA_CHANNEL_7        ((uint32_t)0x0E000000U)  /*!< DMA Channel 7 */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
-  * @brief    DMA data transfer direction 
-  * @{
-  */ 
-#define DMA_PERIPH_TO_MEMORY         ((uint32_t)0x00000000U)      /*!< Peripheral to memory direction */
-#define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_SxCR_DIR_0)  /*!< Memory to peripheral direction */
-#define DMA_MEMORY_TO_MEMORY         ((uint32_t)DMA_SxCR_DIR_1)  /*!< Memory to memory direction     */
-/**
-  * @}
-  */
-        
-/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
-  * @brief    DMA peripheral incremented mode 
-  * @{
-  */ 
-#define DMA_PINC_ENABLE        ((uint32_t)DMA_SxCR_PINC)  /*!< Peripheral increment mode enable  */
-#define DMA_PINC_DISABLE       ((uint32_t)0x00000000U)     /*!< Peripheral increment mode disable */
-/**
-  * @}
-  */ 
-
-/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
-  * @brief    DMA memory incremented mode 
-  * @{
-  */ 
-#define DMA_MINC_ENABLE         ((uint32_t)DMA_SxCR_MINC)  /*!< Memory increment mode enable  */
-#define DMA_MINC_DISABLE        ((uint32_t)0x00000000U)     /*!< Memory increment mode disable */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
-  * @brief    DMA peripheral data size 
-  * @{
-  */ 
-#define DMA_PDATAALIGN_BYTE          ((uint32_t)0x00000000U)        /*!< Peripheral data alignment: Byte     */
-#define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_SxCR_PSIZE_0)  /*!< Peripheral data alignment: HalfWord */
-#define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_SxCR_PSIZE_1)  /*!< Peripheral data alignment: Word     */
-/**
-  * @}
-  */ 
-
-/** @defgroup DMA_Memory_data_size DMA Memory data size
-  * @brief    DMA memory data size 
-  * @{ 
-  */
-#define DMA_MDATAALIGN_BYTE          ((uint32_t)0x00000000U)        /*!< Memory data alignment: Byte     */
-#define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_SxCR_MSIZE_0)  /*!< Memory data alignment: HalfWord */
-#define DMA_MDATAALIGN_WORD          ((uint32_t)DMA_SxCR_MSIZE_1)  /*!< Memory data alignment: Word     */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_mode DMA mode
-  * @brief    DMA mode 
-  * @{
-  */ 
-#define DMA_NORMAL         ((uint32_t)0x00000000U)       /*!< Normal mode                  */
-#define DMA_CIRCULAR       ((uint32_t)DMA_SxCR_CIRC)    /*!< Circular mode                */
-#define DMA_PFCTRL         ((uint32_t)DMA_SxCR_PFCTRL)  /*!< Peripheral flow control mode */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Priority_level DMA Priority level
-  * @brief    DMA priority levels 
-  * @{
-  */
-#define DMA_PRIORITY_LOW             ((uint32_t)0x00000000U)     /*!< Priority level: Low       */
-#define DMA_PRIORITY_MEDIUM          ((uint32_t)DMA_SxCR_PL_0)  /*!< Priority level: Medium    */
-#define DMA_PRIORITY_HIGH            ((uint32_t)DMA_SxCR_PL_1)  /*!< Priority level: High      */
-#define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_SxCR_PL)    /*!< Priority level: Very High */
-/**
-  * @}
-  */ 
-
-/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
-  * @brief    DMA FIFO direct mode
-  * @{
-  */
-#define DMA_FIFOMODE_DISABLE        ((uint32_t)0x00000000U)       /*!< FIFO mode disable */
-#define DMA_FIFOMODE_ENABLE         ((uint32_t)DMA_SxFCR_DMDIS)  /*!< FIFO mode enable  */
-/**
-  * @}
-  */ 
-
-/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
-  * @brief    DMA FIFO level 
-  * @{
-  */
-#define DMA_FIFO_THRESHOLD_1QUARTERFULL       ((uint32_t)0x00000000U)       /*!< FIFO threshold 1 quart full configuration  */
-#define DMA_FIFO_THRESHOLD_HALFFULL           ((uint32_t)DMA_SxFCR_FTH_0)  /*!< FIFO threshold half full configuration     */
-#define DMA_FIFO_THRESHOLD_3QUARTERSFULL      ((uint32_t)DMA_SxFCR_FTH_1)  /*!< FIFO threshold 3 quarts full configuration */
-#define DMA_FIFO_THRESHOLD_FULL               ((uint32_t)DMA_SxFCR_FTH)    /*!< FIFO threshold full configuration          */
-/**
-  * @}
-  */ 
-
-/** @defgroup DMA_Memory_burst DMA Memory burst
-  * @brief    DMA memory burst 
-  * @{
-  */ 
-#define DMA_MBURST_SINGLE       ((uint32_t)0x00000000U)  
-#define DMA_MBURST_INC4         ((uint32_t)DMA_SxCR_MBURST_0)  
-#define DMA_MBURST_INC8         ((uint32_t)DMA_SxCR_MBURST_1)  
-#define DMA_MBURST_INC16        ((uint32_t)DMA_SxCR_MBURST)  
-/**
-  * @}
-  */ 
-
-/** @defgroup DMA_Peripheral_burst DMA Peripheral burst
-  * @brief    DMA peripheral burst 
-  * @{
-  */ 
-#define DMA_PBURST_SINGLE       ((uint32_t)0x00000000U)
-#define DMA_PBURST_INC4         ((uint32_t)DMA_SxCR_PBURST_0)
-#define DMA_PBURST_INC8         ((uint32_t)DMA_SxCR_PBURST_1)
-#define DMA_PBURST_INC16        ((uint32_t)DMA_SxCR_PBURST)
-/**
-  * @}
-  */
-
-/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
-  * @brief    DMA interrupts definition 
-  * @{
-  */
-#define DMA_IT_TC                         ((uint32_t)DMA_SxCR_TCIE)
-#define DMA_IT_HT                         ((uint32_t)DMA_SxCR_HTIE)
-#define DMA_IT_TE                         ((uint32_t)DMA_SxCR_TEIE)
-#define DMA_IT_DME                        ((uint32_t)DMA_SxCR_DMEIE)
-#define DMA_IT_FE                         ((uint32_t)0x00000080U)
-/**
-  * @}
-  */
-
-/** @defgroup DMA_flag_definitions DMA flag definitions
-  * @brief    DMA flag definitions 
-  * @{
-  */ 
-#define DMA_FLAG_FEIF0_4                    ((uint32_t)0x00800001U)
-#define DMA_FLAG_DMEIF0_4                   ((uint32_t)0x00800004U)
-#define DMA_FLAG_TEIF0_4                    ((uint32_t)0x00000008U)
-#define DMA_FLAG_HTIF0_4                    ((uint32_t)0x00000010U)
-#define DMA_FLAG_TCIF0_4                    ((uint32_t)0x00000020U)
-#define DMA_FLAG_FEIF1_5                    ((uint32_t)0x00000040U)
-#define DMA_FLAG_DMEIF1_5                   ((uint32_t)0x00000100U)
-#define DMA_FLAG_TEIF1_5                    ((uint32_t)0x00000200U)
-#define DMA_FLAG_HTIF1_5                    ((uint32_t)0x00000400U)
-#define DMA_FLAG_TCIF1_5                    ((uint32_t)0x00000800U)
-#define DMA_FLAG_FEIF2_6                    ((uint32_t)0x00010000U)
-#define DMA_FLAG_DMEIF2_6                   ((uint32_t)0x00040000U)
-#define DMA_FLAG_TEIF2_6                    ((uint32_t)0x00080000U)
-#define DMA_FLAG_HTIF2_6                    ((uint32_t)0x00100000U)
-#define DMA_FLAG_TCIF2_6                    ((uint32_t)0x00200000U)
-#define DMA_FLAG_FEIF3_7                    ((uint32_t)0x00400000U)
-#define DMA_FLAG_DMEIF3_7                   ((uint32_t)0x01000000U)
-#define DMA_FLAG_TEIF3_7                    ((uint32_t)0x02000000U)
-#define DMA_FLAG_HTIF3_7                    ((uint32_t)0x04000000U)
-#define DMA_FLAG_TCIF3_7                    ((uint32_t)0x08000000U)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
- 
-/* Exported macro ------------------------------------------------------------*/
-
-/** @brief Reset DMA handle state
-  * @param  __HANDLE__: specifies the DMA handle.
-  * @retval None
-  */
-#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
-
-/**
-  * @brief  Return the current DMA Stream FIFO filled level.
-  * @param  __HANDLE__: DMA handle
-  * @retval The FIFO filling state.
-  *           - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full 
-  *                                              and not empty.
-  *           - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
-  *           - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
-  *           - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
-  *           - DMA_FIFOStatus_Empty: when FIFO is empty
-  *           - DMA_FIFOStatus_Full: when FIFO is full
-  */
-#define __HAL_DMA_GET_FS(__HANDLE__)      (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
-
-/**
-  * @brief  Enable the specified DMA Stream.
-  * @param  __HANDLE__: DMA handle
-  * @retval None
-  */
-#define __HAL_DMA_ENABLE(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  DMA_SxCR_EN)
-
-/**
-  * @brief  Disable the specified DMA Stream.
-  * @param  __HANDLE__: DMA handle
-  * @retval None
-  */
-#define __HAL_DMA_DISABLE(__HANDLE__)     ((__HANDLE__)->Instance->CR &=  ~DMA_SxCR_EN)
-
-/* Interrupt & Flag management */
-
-/**
-  * @brief  Return the current DMA Stream transfer complete flag.
-  * @param  __HANDLE__: DMA handle
-  * @retval The specified transfer complete flag index.
-  */
-#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
-   DMA_FLAG_TCIF3_7)
-
-/**
-  * @brief  Return the current DMA Stream half transfer complete flag.
-  * @param  __HANDLE__: DMA handle
-  * @retval The specified half transfer complete flag index.
-  */      
-#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
-   DMA_FLAG_HTIF3_7)
-
-/**
-  * @brief  Return the current DMA Stream transfer error flag.
-  * @param  __HANDLE__: DMA handle
-  * @retval The specified transfer error flag index.
-  */
-#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
-   DMA_FLAG_TEIF3_7)
-
-/**
-  * @brief  Return the current DMA Stream FIFO error flag.
-  * @param  __HANDLE__: DMA handle
-  * @retval The specified FIFO error flag index.
-  */
-#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
-   DMA_FLAG_FEIF3_7)
-
-/**
-  * @brief  Return the current DMA Stream direct mode error flag.
-  * @param  __HANDLE__: DMA handle
-  * @retval The specified direct mode error flag index.
-  */
-#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
-   DMA_FLAG_DMEIF3_7)
-
-/**
-  * @brief  Get the DMA Stream pending flags.
-  * @param  __HANDLE__: DMA handle
-  * @param  __FLAG__: Get the specified flag.
-  *          This parameter can be any combination of the following values:
-  *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
-  *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
-  *            @arg DMA_FLAG_TEIFx: Transfer error flag.
-  *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.
-  *            @arg DMA_FLAG_FEIFx: FIFO error flag.
-  *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.   
-  * @retval The state of FLAG (SET or RESET).
-  */
-#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
-(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
- ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
- ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
-
-/**
-  * @brief  Clear the DMA Stream pending flags.
-  * @param  __HANDLE__: DMA handle
-  * @param  __FLAG__: specifies the flag to clear.
-  *          This parameter can be any combination of the following values:
-  *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
-  *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
-  *            @arg DMA_FLAG_TEIFx: Transfer error flag.
-  *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.
-  *            @arg DMA_FLAG_FEIFx: FIFO error flag.
-  *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.   
-  * @retval None
-  */
-#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
-(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
- ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
- ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
-
-/**
-  * @brief  Enable the specified DMA Stream interrupts.
-  * @param  __HANDLE__: DMA handle
-  * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 
-  *        This parameter can be any combination of the following values:
-  *           @arg DMA_IT_TC: Transfer complete interrupt mask.
-  *           @arg DMA_IT_HT: Half transfer complete interrupt mask.
-  *           @arg DMA_IT_TE: Transfer error interrupt mask.
-  *           @arg DMA_IT_FE: FIFO error interrupt mask.
-  *           @arg DMA_IT_DME: Direct mode error interrupt.
-  * @retval None
-  */
-#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((__INTERRUPT__) != DMA_IT_FE)? \
-((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
-
-/**
-  * @brief  Disable the specified DMA Stream interrupts.
-  * @param  __HANDLE__: DMA handle
-  * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 
-  *         This parameter can be any combination of the following values:
-  *            @arg DMA_IT_TC: Transfer complete interrupt mask.
-  *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
-  *            @arg DMA_IT_TE: Transfer error interrupt mask.
-  *            @arg DMA_IT_FE: FIFO error interrupt mask.
-  *            @arg DMA_IT_DME: Direct mode error interrupt.
-  * @retval None
-  */
-#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \
-((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
-
-/**
-  * @brief  Check whether the specified DMA Stream interrupt is enabled or disabled.
-  * @param  __HANDLE__: DMA handle
-  * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
-  *         This parameter can be one of the following values:
-  *            @arg DMA_IT_TC: Transfer complete interrupt mask.
-  *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
-  *            @arg DMA_IT_TE: Transfer error interrupt mask.
-  *            @arg DMA_IT_FE: FIFO error interrupt mask.
-  *            @arg DMA_IT_DME: Direct mode error interrupt.
-  * @retval The state of DMA_IT.
-  */
-#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \
-                                                        ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
-                                                        ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
-
-/**
-  * @brief  Writes the number of data units to be transferred on the DMA Stream.
-  * @param  __HANDLE__: DMA handle
-  * @param  __COUNTER__: Number of data units to be transferred (from 0 to 65535) 
-  *          Number of data items depends only on the Peripheral data format.
-  *            
-  * @note   If Peripheral data format is Bytes: number of data units is equal 
-  *         to total number of bytes to be transferred.
-  *           
-  * @note   If Peripheral data format is Half-Word: number of data units is  
-  *         equal to total number of bytes to be transferred / 2.
-  *           
-  * @note   If Peripheral data format is Word: number of data units is equal 
-  *         to total  number of bytes to be transferred / 4.
-  *      
-  * @retval The number of remaining data units in the current DMAy Streamx transfer.
-  */
-#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
-
-/**
-  * @brief  Returns the number of remaining data units in the current DMAy Streamx transfer.
-  * @param  __HANDLE__: DMA handle
-  *   
-  * @retval The number of remaining data units in the current DMA Stream transfer.
-  */
-#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
-
-
-/* Include DMA HAL Extension module */
-#include "stm32f4xx_hal_dma_ex.h"   
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Functions DMA Exported Functions
-  * @brief    DMA Exported functions 
-  * @{
-  */
-
-/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @brief   Initialization and de-initialization functions 
-  * @{
-  */
-HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 
-HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
-  * @brief   I/O operation functions  
-  * @{
-  */
-HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
-void              HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
-HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
-
-/**
-  * @}
-  */ 
-
-/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
-  * @brief    Peripheral State functions 
-  * @{
-  */
-HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
-uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
-/**
-  * @}
-  */ 
-/**
-  * @}
-  */ 
-/* Private Constants -------------------------------------------------------------*/
-/** @defgroup DMA_Private_Constants DMA Private Constants
-  * @brief    DMA private defines and constants 
-  * @{
-  */
-/**
-  * @}
-  */ 
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup DMA_Private_Macros DMA Private Macros
-  * @brief    DMA private macros 
-  * @{
-  */
-#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
-                                 ((CHANNEL) == DMA_CHANNEL_1) || \
-                                 ((CHANNEL) == DMA_CHANNEL_2) || \
-                                 ((CHANNEL) == DMA_CHANNEL_3) || \
-                                 ((CHANNEL) == DMA_CHANNEL_4) || \
-                                 ((CHANNEL) == DMA_CHANNEL_5) || \
-                                 ((CHANNEL) == DMA_CHANNEL_6) || \
-                                 ((CHANNEL) == DMA_CHANNEL_7))
-
-#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
-                                     ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
-                                     ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 
-
-#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
-
-#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
-                                            ((STATE) == DMA_PINC_DISABLE))
-
-#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
-                                        ((STATE) == DMA_MINC_DISABLE))
-
-#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
-                                           ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
-                                           ((SIZE) == DMA_PDATAALIGN_WORD))
-
-#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
-                                       ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
-                                       ((SIZE) == DMA_MDATAALIGN_WORD ))
-
-#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
-                           ((MODE) == DMA_CIRCULAR) || \
-                           ((MODE) == DMA_PFCTRL)) 
-
-#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
-                                   ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
-                                   ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
-                                   ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 
-
-#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
-                                       ((STATE) == DMA_FIFOMODE_ENABLE))
-
-#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
-                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL)      || \
-                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
-                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
-
-#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
-                                    ((BURST) == DMA_MBURST_INC4)   || \
-                                    ((BURST) == DMA_MBURST_INC8)   || \
-                                    ((BURST) == DMA_MBURST_INC16))
-
-#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
-                                        ((BURST) == DMA_PBURST_INC4)   || \
-                                        ((BURST) == DMA_PBURST_INC8)   || \
-                                        ((BURST) == DMA_PBURST_INC16))
-/**
-  * @}
-  */ 
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup DMA_Private_Functions DMA Private Functions
-  * @brief    DMA private  functions 
-  * @{
-  */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_DMA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_dma_ex.h b/stmhal/hal/f4/inc/stm32f4xx_hal_dma_ex.h
deleted file mode 100644
index a0594862ff..0000000000
--- a/stmhal/hal/f4/inc/stm32f4xx_hal_dma_ex.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_dma_ex.h
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   Header file of DMA HAL extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_DMA_EX_H
-#define __STM32F4xx_HAL_DMA_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup DMAEx
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
-  * @brief DMAEx Exported types
-  * @{
-  */
-   
-/** 
-  * @brief  HAL DMA Memory definition  
-  */ 
-typedef enum
-{
-  MEMORY0      = 0x00U,    /*!< Memory 0     */
-  MEMORY1      = 0x01U     /*!< Memory 1     */
-}HAL_DMA_MemoryTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
-  * @brief   DMAEx Exported functions
-  * @{
-  */
-
-/** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions
-  * @brief   Extended features functions
-  * @{
-  */
-
-/* IO operation functions *******************************************************/
-HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
-HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
-HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory);
-
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-         
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup DMAEx_Private_Functions DMAEx Private Functions
-  * @brief DMAEx Private functions
-  * @{
-  */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_HAL_DMA_EX_H*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_flash.h b/stmhal/hal/f4/inc/stm32f4xx_hal_flash.h
deleted file mode 100644
index ced95b84c9..0000000000
--- a/stmhal/hal/f4/inc/stm32f4xx_hal_flash.h
+++ /dev/null
@@ -1,442 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_flash.h
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   Header file of FLASH HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_FLASH_H
-#define __STM32F4xx_HAL_FLASH_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup FLASH
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Types FLASH Exported Types
-  * @{
-  */
- 
-/**
-  * @brief  FLASH Procedure structure definition
-  */
-typedef enum 
-{
-  FLASH_PROC_NONE = 0U, 
-  FLASH_PROC_SECTERASE,
-  FLASH_PROC_MASSERASE,
-  FLASH_PROC_PROGRAM
-} FLASH_ProcedureTypeDef;
-
-/** 
-  * @brief  FLASH handle Structure definition  
-  */
-typedef struct
-{
-  __IO FLASH_ProcedureTypeDef ProcedureOnGoing;   /*Internal variable to indicate which procedure is ongoing or not in IT context*/
-  
-  __IO uint32_t               NbSectorsToErase;   /*Internal variable to save the remaining sectors to erase in IT context*/
-  
-  __IO uint8_t                VoltageForErase;    /*Internal variable to provide voltage range selected by user in IT context*/
-  
-  __IO uint32_t               Sector;             /*Internal variable to define the current sector which is erasing*/
-  
-  __IO uint32_t               Bank;               /*Internal variable to save current bank selected during mass erase*/
-  
-  __IO uint32_t               Address;            /*Internal variable to save address selected for program*/
-  
-  HAL_LockTypeDef             Lock;               /* FLASH locking object                */
-
-  __IO uint32_t               ErrorCode;          /* FLASH error code                    */
-
-}FLASH_ProcessTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
-  * @{
-  */  
-/** @defgroup FLASH_Error_Code FLASH Error Code
-  * @brief    FLASH Error Code 
-  * @{
-  */ 
-#define HAL_FLASH_ERROR_NONE         ((uint32_t)0x00000000U)    /*!< No error                      */
-#define HAL_FLASH_ERROR_RD           ((uint32_t)0x00000001U)    /*!< Read Protection error         */
-#define HAL_FLASH_ERROR_PGS          ((uint32_t)0x00000002U)    /*!< Programming Sequence error    */
-#define HAL_FLASH_ERROR_PGP          ((uint32_t)0x00000004U)    /*!< Programming Parallelism error */
-#define HAL_FLASH_ERROR_PGA          ((uint32_t)0x00000008U)    /*!< Programming Alignment error   */
-#define HAL_FLASH_ERROR_WRP          ((uint32_t)0x00000010U)    /*!< Write protection error        */
-#define HAL_FLASH_ERROR_OPERATION    ((uint32_t)0x00000020U)    /*!< Operation Error               */
-/**
-  * @}
-  */
-  
-/** @defgroup FLASH_Type_Program FLASH Type Program
-  * @{
-  */ 
-#define FLASH_TYPEPROGRAM_BYTE        ((uint32_t)0x00U)  /*!< Program byte (8-bit) at a specified address           */
-#define FLASH_TYPEPROGRAM_HALFWORD    ((uint32_t)0x01U)  /*!< Program a half-word (16-bit) at a specified address   */
-#define FLASH_TYPEPROGRAM_WORD        ((uint32_t)0x02U)  /*!< Program a word (32-bit) at a specified address        */
-#define FLASH_TYPEPROGRAM_DOUBLEWORD  ((uint32_t)0x03U)  /*!< Program a double word (64-bit) at a specified address */
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Flag_definition FLASH Flag definition
-  * @brief Flag definition
-  * @{
-  */ 
-#define FLASH_FLAG_EOP                 FLASH_SR_EOP            /*!< FLASH End of Operation flag               */
-#define FLASH_FLAG_OPERR               FLASH_SR_SOP            /*!< FLASH operation Error flag                */
-#define FLASH_FLAG_WRPERR              FLASH_SR_WRPERR         /*!< FLASH Write protected error flag          */
-#define FLASH_FLAG_PGAERR              FLASH_SR_PGAERR         /*!< FLASH Programming Alignment error flag    */
-#define FLASH_FLAG_PGPERR              FLASH_SR_PGPERR         /*!< FLASH Programming Parallelism error flag  */
-#define FLASH_FLAG_PGSERR              FLASH_SR_PGSERR         /*!< FLASH Programming Sequence error flag     */
-#define FLASH_FLAG_RDERR               ((uint32_t)0x00000100U)  /*!< Read Protection error flag (PCROP)        */
-#define FLASH_FLAG_BSY                 FLASH_SR_BSY            /*!< FLASH Busy flag                           */ 
-/**
-  * @}
-  */
-  
-/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition
-  * @brief FLASH Interrupt definition
-  * @{
-  */ 
-#define FLASH_IT_EOP                   FLASH_CR_EOPIE          /*!< End of FLASH Operation Interrupt source */
-#define FLASH_IT_ERR                   ((uint32_t)0x02000000U)  /*!< Error Interrupt source                  */
-/**
-  * @}
-  */  
-
-/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism
-  * @{
-  */
-#define FLASH_PSIZE_BYTE           ((uint32_t)0x00000000U)
-#define FLASH_PSIZE_HALF_WORD      ((uint32_t)0x00000100U)
-#define FLASH_PSIZE_WORD           ((uint32_t)0x00000200U)
-#define FLASH_PSIZE_DOUBLE_WORD    ((uint32_t)0x00000300U)
-#define CR_PSIZE_MASK              ((uint32_t)0xFFFFFCFFU)
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_Keys FLASH Keys
-  * @{
-  */ 
-#define RDP_KEY                  ((uint16_t)0x00A5U)
-#define FLASH_KEY1               ((uint32_t)0x45670123U)
-#define FLASH_KEY2               ((uint32_t)0xCDEF89ABU)
-#define FLASH_OPT_KEY1           ((uint32_t)0x08192A3BU)
-#define FLASH_OPT_KEY2           ((uint32_t)0x4C5D6E7FU)
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-  
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
-  * @{
-  */
-/**
-  * @brief  Set the FLASH Latency.
-  * @param  __LATENCY__: FLASH Latency
-  *         The value of this parameter depend on device used within the same series
-  * @retval none
-  */ 
-#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (*(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)(__LATENCY__))
-
-/**
-  * @brief  Get the FLASH Latency.
-  * @retval FLASH Latency
-  *          The value of this parameter depend on device used within the same series
-  */ 
-#define __HAL_FLASH_GET_LATENCY()     (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
-
-/**
-  * @brief  Enable the FLASH prefetch buffer.
-  * @retval none
-  */ 
-#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE()  (FLASH->ACR |= FLASH_ACR_PRFTEN)
-
-/**
-  * @brief  Disable the FLASH prefetch buffer.
-  * @retval none
-  */ 
-#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE()   (FLASH->ACR &= (~FLASH_ACR_PRFTEN))
-
-/**
-  * @brief  Enable the FLASH instruction cache.
-  * @retval none
-  */ 
-#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE()  (FLASH->ACR |= FLASH_ACR_ICEN)
-
-/**
-  * @brief  Disable the FLASH instruction cache.
-  * @retval none
-  */ 
-#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE()   (FLASH->ACR &= (~FLASH_ACR_ICEN))
-
-/**
-  * @brief  Enable the FLASH data cache.
-  * @retval none
-  */ 
-#define __HAL_FLASH_DATA_CACHE_ENABLE()  (FLASH->ACR |= FLASH_ACR_DCEN)
-
-/**
-  * @brief  Disable the FLASH data cache.
-  * @retval none
-  */ 
-#define __HAL_FLASH_DATA_CACHE_DISABLE()   (FLASH->ACR &= (~FLASH_ACR_DCEN))
-
-/**
-  * @brief  Resets the FLASH instruction Cache.
-  * @note   This function must be used only when the Instruction Cache is disabled.  
-  * @retval None
-  */
-#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_ICRST;  \
-                                                  FLASH->ACR &= ~FLASH_ACR_ICRST; \
-                                                 }while(0)
-
-/**
-  * @brief  Resets the FLASH data Cache.
-  * @note   This function must be used only when the data Cache is disabled.  
-  * @retval None
-  */
-#define __HAL_FLASH_DATA_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_DCRST;  \
-                                           FLASH->ACR &= ~FLASH_ACR_DCRST; \
-                                          }while(0)
-/**
-  * @brief  Enable the specified FLASH interrupt.
-  * @param  __INTERRUPT__ : FLASH interrupt 
-  *         This parameter can be any combination of the following values:
-  *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
-  *     @arg FLASH_IT_ERR: Error Interrupt    
-  * @retval none
-  */  
-#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)  (FLASH->CR |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the specified FLASH interrupt.
-  * @param  __INTERRUPT__ : FLASH interrupt 
-  *         This parameter can be any combination of the following values:
-  *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
-  *     @arg FLASH_IT_ERR: Error Interrupt    
-  * @retval none
-  */  
-#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)  (FLASH->CR &= ~(uint32_t)(__INTERRUPT__))
-
-/**
-  * @brief  Get the specified FLASH flag status. 
-  * @param  __FLAG__: specifies the FLASH flag to check.
-  *          This parameter can be one of the following values:
-  *            @arg FLASH_FLAG_EOP   : FLASH End of Operation flag 
-  *            @arg FLASH_FLAG_OPERR : FLASH operation Error flag 
-  *            @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag 
-  *            @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
-  *            @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
-  *            @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
-  *            @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP) 
-  *            @arg FLASH_FLAG_BSY   : FLASH Busy flag
-  * @retval The new state of __FLAG__ (SET or RESET).
-  */
-#define __HAL_FLASH_GET_FLAG(__FLAG__)   ((FLASH->SR & (__FLAG__))==(__FLAG__))
-
-/**
-  * @brief  Clear the specified FLASH flag.
-  * @param  __FLAG__: specifies the FLASH flags to clear.
-  *          This parameter can be any combination of the following values:
-  *            @arg FLASH_FLAG_EOP   : FLASH End of Operation flag 
-  *            @arg FLASH_FLAG_OPERR : FLASH operation Error flag 
-  *            @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag 
-  *            @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag 
-  *            @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
-  *            @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
-  *            @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP)   
-  * @retval none
-  */
-#define __HAL_FLASH_CLEAR_FLAG(__FLAG__)   (FLASH->SR = (__FLAG__))
-/**
-  * @}
-  */
-
-/* Include FLASH HAL Extension module */
-#include "stm32f4xx_hal_flash_ex.h"
-#include "stm32f4xx_hal_flash_ramfunc.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup FLASH_Exported_Functions
-  * @{
-  */
-/** @addtogroup FLASH_Exported_Functions_Group1
-  * @{
-  */
-/* Program operation functions  ***********************************************/
-HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
-HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
-/* FLASH IRQ handler method */
-void HAL_FLASH_IRQHandler(void);
-/* Callbacks in non blocking modes */ 
-void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
-void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
-/**
-  * @}
-  */
-
-/** @addtogroup FLASH_Exported_Functions_Group2
-  * @{
-  */
-/* Peripheral Control functions  **********************************************/
-HAL_StatusTypeDef HAL_FLASH_Unlock(void);
-HAL_StatusTypeDef HAL_FLASH_Lock(void);
-HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
-HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
-/* Option bytes control */
-HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
-/**
-  * @}
-  */
-
-/** @addtogroup FLASH_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral State functions  ************************************************/
-uint32_t HAL_FLASH_GetError(void);
-HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup FLASH_Private_Variables FLASH Private Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup FLASH_Private_Constants FLASH Private Constants
-  * @{
-  */
-
-/** 
-  * @brief   ACR register byte 0 (Bits[7:0]) base address  
-  */ 
-#define ACR_BYTE0_ADDRESS           ((uint32_t)0x40023C00U) 
-/** 
-  * @brief   OPTCR register byte 0 (Bits[7:0]) base address  
-  */ 
-#define OPTCR_BYTE0_ADDRESS         ((uint32_t)0x40023C14U)
-/** 
-  * @brief   OPTCR register byte 1 (Bits[15:8]) base address  
-  */ 
-#define OPTCR_BYTE1_ADDRESS         ((uint32_t)0x40023C15U)
-/** 
-  * @brief   OPTCR register byte 2 (Bits[23:16]) base address  
-  */ 
-#define OPTCR_BYTE2_ADDRESS         ((uint32_t)0x40023C16U)
-/** 
-  * @brief   OPTCR register byte 3 (Bits[31:24]) base address  
-  */ 
-#define OPTCR_BYTE3_ADDRESS         ((uint32_t)0x40023C17U)
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup FLASH_Private_Macros FLASH Private Macros
-  * @{
-  */
-
-/** @defgroup FLASH_IS_FLASH_Definitions FLASH Private macros to check input parameters
-  * @{
-  */
-#define IS_FLASH_TYPEPROGRAM(VALUE)(((VALUE) == FLASH_TYPEPROGRAM_BYTE) || \
-                                    ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
-                                    ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \
-                                    ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))  
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup FLASH_Private_Functions FLASH Private Functions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_FLASH_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_flash_ex.h b/stmhal/hal/f4/inc/stm32f4xx_hal_flash_ex.h
deleted file mode 100644
index 017b47c752..0000000000
--- a/stmhal/hal/f4/inc/stm32f4xx_hal_flash_ex.h
+++ /dev/null
@@ -1,984 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_flash_ex.h
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   Header file of FLASH HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_FLASH_EX_H
-#define __STM32F4xx_HAL_FLASH_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup FLASHEx
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup FLASHEx_Exported_Types FLASH Exported Types
-  * @{
-  */
-
-/**
-  * @brief  FLASH Erase structure definition
-  */
-typedef struct
-{
-  uint32_t TypeErase;   /*!< Mass erase or sector Erase.
-                             This parameter can be a value of @ref FLASHEx_Type_Erase */
-
-  uint32_t Banks;       /*!< Select banks to erase when Mass erase is enabled.
-                             This parameter must be a value of @ref FLASHEx_Banks */
-
-  uint32_t Sector;      /*!< Initial FLASH sector to erase when Mass erase is disabled
-                             This parameter must be a value of @ref FLASHEx_Sectors */
-
-  uint32_t NbSectors;   /*!< Number of sectors to be erased.
-                             This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
-
-  uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism
-                             This parameter must be a value of @ref FLASHEx_Voltage_Range */
-
-} FLASH_EraseInitTypeDef;
-
-/**
-  * @brief  FLASH Option Bytes Program structure definition
-  */
-typedef struct
-{
-  uint32_t OptionType;   /*!< Option byte to be configured.
-                              This parameter can be a value of @ref FLASHEx_Option_Type */
-
-  uint32_t WRPState;     /*!< Write protection activation or deactivation.
-                              This parameter can be a value of @ref FLASHEx_WRP_State */
-
-  uint32_t WRPSector;         /*!< Specifies the sector(s) to be write protected.
-                              The value of this parameter depend on device used within the same series */
-
-  uint32_t Banks;        /*!< Select banks for WRP activation/deactivation of all sectors.
-                              This parameter must be a value of @ref FLASHEx_Banks */        
-
-  uint32_t RDPLevel;     /*!< Set the read protection level.
-                              This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
-
-  uint32_t BORLevel;     /*!< Set the BOR Level.
-                              This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */
-
-  uint8_t  USERConfig;   /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. */
-
-} FLASH_OBProgramInitTypeDef;
-
-/**
-  * @brief  FLASH Advanced Option Bytes Program structure definition
-  */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
-    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
-    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
-    defined(STM32F412Cx)
-typedef struct
-{
-  uint32_t OptionType;     /*!< Option byte to be configured for extension.
-                                This parameter can be a value of @ref FLASHEx_Advanced_Option_Type */
-
-  uint32_t PCROPState;     /*!< PCROP activation or deactivation.
-                                This parameter can be a value of @ref FLASHEx_PCROP_State */
-
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
-    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
-  uint16_t Sectors;        /*!< specifies the sector(s) set for PCROP.
-                                This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
-#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx ||\
-          STM32F412Cx */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-  uint32_t Banks;          /*!< Select banks for PCROP activation/deactivation of all sectors.
-                                This parameter must be a value of @ref FLASHEx_Banks */
-
-  uint16_t SectorsBank1;   /*!< Specifies the sector(s) set for PCROP for Bank1.
-                                This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
-
-  uint16_t SectorsBank2;   /*!< Specifies the sector(s) set for PCROP for Bank2.
-                                This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
-
-  uint8_t BootConfig;      /*!< Specifies Option bytes for boot config.
-                                This parameter can be a value of @ref FLASHEx_Dual_Boot */
-
-#endif /*STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-}FLASH_AdvOBProgramInitTypeDef;
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants
-  * @{
-  */
-
-/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
-  * @{
-  */ 
-#define FLASH_TYPEERASE_SECTORS         ((uint32_t)0x00U)  /*!< Sectors erase only          */
-#define FLASH_TYPEERASE_MASSERASE       ((uint32_t)0x01U)  /*!< Flash Mass erase activation */
-/**
-  * @}
-  */
-  
-/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range
-  * @{
-  */ 
-#define FLASH_VOLTAGE_RANGE_1        ((uint32_t)0x00U)  /*!< Device operating range: 1.8V to 2.1V                */
-#define FLASH_VOLTAGE_RANGE_2        ((uint32_t)0x01U)  /*!< Device operating range: 2.1V to 2.7V                */
-#define FLASH_VOLTAGE_RANGE_3        ((uint32_t)0x02U)  /*!< Device operating range: 2.7V to 3.6V                */
-#define FLASH_VOLTAGE_RANGE_4        ((uint32_t)0x03U)  /*!< Device operating range: 2.7V to 3.6V + External Vpp */
-/**
-  * @}
-  */
-  
-/** @defgroup FLASHEx_WRP_State FLASH WRP State
-  * @{
-  */ 
-#define OB_WRPSTATE_DISABLE       ((uint32_t)0x00U)  /*!< Disable the write protection of the desired bank 1 sectors */
-#define OB_WRPSTATE_ENABLE        ((uint32_t)0x01U)  /*!< Enable the write protection of the desired bank 1 sectors  */
-/**
-  * @}
-  */
-  
-/** @defgroup FLASHEx_Option_Type FLASH Option Type
-  * @{
-  */ 
-#define OPTIONBYTE_WRP        ((uint32_t)0x01U)  /*!< WRP option byte configuration  */
-#define OPTIONBYTE_RDP        ((uint32_t)0x02U)  /*!< RDP option byte configuration  */
-#define OPTIONBYTE_USER       ((uint32_t)0x04U)  /*!< USER option byte configuration */
-#define OPTIONBYTE_BOR        ((uint32_t)0x08U)  /*!< BOR option byte configuration  */
-/**
-  * @}
-  */
-  
-/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection
-  * @{
-  */
-#define OB_RDP_LEVEL_0   ((uint8_t)0xAAU)
-#define OB_RDP_LEVEL_1   ((uint8_t)0x55U)
-#define OB_RDP_LEVEL_2   ((uint8_t)0xCCU) /*!< Warning: When enabling read protection level 2 
-                                              it s no more possible to go back to level 1 or 0 */
-/**
-  * @}
-  */ 
-  
-/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog
-  * @{
-  */ 
-#define OB_IWDG_SW                     ((uint8_t)0x20U)  /*!< Software IWDG selected */
-#define OB_IWDG_HW                     ((uint8_t)0x00U)  /*!< Hardware IWDG selected */
-/**
-  * @}
-  */ 
-  
-/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP
-  * @{
-  */ 
-#define OB_STOP_NO_RST                 ((uint8_t)0x40U) /*!< No reset generated when entering in STOP */
-#define OB_STOP_RST                    ((uint8_t)0x00U) /*!< Reset generated when entering in STOP    */
-/**
-  * @}
-  */ 
-
-
-/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY
-  * @{
-  */ 
-#define OB_STDBY_NO_RST                ((uint8_t)0x80U) /*!< No reset generated when entering in STANDBY */
-#define OB_STDBY_RST                   ((uint8_t)0x00U) /*!< Reset generated when entering in STANDBY    */
-/**
-  * @}
-  */    
-
-/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level
-  * @{
-  */  
-#define OB_BOR_LEVEL3          ((uint8_t)0x00U)  /*!< Supply voltage ranges from 2.70 to 3.60 V */
-#define OB_BOR_LEVEL2          ((uint8_t)0x04U)  /*!< Supply voltage ranges from 2.40 to 2.70 V */
-#define OB_BOR_LEVEL1          ((uint8_t)0x08U)  /*!< Supply voltage ranges from 2.10 to 2.40 V */
-#define OB_BOR_OFF             ((uint8_t)0x0CU)  /*!< Supply voltage ranges from 1.62 to 2.10 V */
-/**
-  * @}
-  */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
-    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
-    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
-    defined(STM32F412Cx)
-/** @defgroup FLASHEx_PCROP_State FLASH PCROP State
-  * @{
-  */ 
-#define OB_PCROP_STATE_DISABLE       ((uint32_t)0x00U)  /*!< Disable PCROP */
-#define OB_PCROP_STATE_ENABLE        ((uint32_t)0x01U)  /*!< Enable PCROP  */
-/**
-  * @}
-  */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
-          STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
-          STM32F412Vx) || defined(STM32F412Rx) ||\
-          STM32F412Cx */
-
-/** @defgroup FLASHEx_Advanced_Option_Type FLASH Advanced Option Type
-  * @{
-  */ 
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx)
-#define OPTIONBYTE_PCROP        ((uint32_t)0x01U)  /*!< PCROP option byte configuration      */
-#define OPTIONBYTE_BOOTCONFIG   ((uint32_t)0x02U)  /*!< BOOTConfig option byte configuration */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
-    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
-    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
-#define OPTIONBYTE_PCROP        ((uint32_t)0x01U)  /*!<PCROP option byte configuration */
-#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Latency FLASH Latency
-  * @{
-  */
-/*------------------------- STM32F42xxx/STM32F43xxx/STM32F446xx/STM32F469xx/STM32F479xx ----------------------*/  
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
-    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
-#define FLASH_LATENCY_0                FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero Latency cycle      */
-#define FLASH_LATENCY_1                FLASH_ACR_LATENCY_1WS   /*!< FLASH One Latency cycle       */
-#define FLASH_LATENCY_2                FLASH_ACR_LATENCY_2WS   /*!< FLASH Two Latency cycles      */
-#define FLASH_LATENCY_3                FLASH_ACR_LATENCY_3WS   /*!< FLASH Three Latency cycles    */
-#define FLASH_LATENCY_4                FLASH_ACR_LATENCY_4WS   /*!< FLASH Four Latency cycles     */
-#define FLASH_LATENCY_5                FLASH_ACR_LATENCY_5WS   /*!< FLASH Five Latency cycles     */
-#define FLASH_LATENCY_6                FLASH_ACR_LATENCY_6WS   /*!< FLASH Six Latency cycles      */
-#define FLASH_LATENCY_7                FLASH_ACR_LATENCY_7WS   /*!< FLASH Seven Latency cycles    */
-#define FLASH_LATENCY_8                FLASH_ACR_LATENCY_8WS   /*!< FLASH Eight Latency cycles    */
-#define FLASH_LATENCY_9                FLASH_ACR_LATENCY_9WS   /*!< FLASH Nine Latency cycles     */
-#define FLASH_LATENCY_10               FLASH_ACR_LATENCY_10WS  /*!< FLASH Ten Latency cycles      */
-#define FLASH_LATENCY_11               FLASH_ACR_LATENCY_11WS  /*!< FLASH Eleven Latency cycles   */
-#define FLASH_LATENCY_12               FLASH_ACR_LATENCY_12WS  /*!< FLASH Twelve Latency cycles   */
-#define FLASH_LATENCY_13               FLASH_ACR_LATENCY_13WS  /*!< FLASH Thirteen Latency cycles */
-#define FLASH_LATENCY_14               FLASH_ACR_LATENCY_14WS  /*!< FLASH Fourteen Latency cycles */
-#define FLASH_LATENCY_15               FLASH_ACR_LATENCY_15WS  /*!< FLASH Fifteen Latency cycles  */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
-/*--------------------------------------------------------------------------------------------------------------*/
-
-/*-------------------------- STM32F40xxx/STM32F41xxx/STM32F401xx/STM32F411xx -----------------------------------*/ 
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
-    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
-    defined(STM32F412Rx) || defined(STM32F412Cx)
-     
-#define FLASH_LATENCY_0                FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero Latency cycle      */
-#define FLASH_LATENCY_1                FLASH_ACR_LATENCY_1WS   /*!< FLASH One Latency cycle       */
-#define FLASH_LATENCY_2                FLASH_ACR_LATENCY_2WS   /*!< FLASH Two Latency cycles      */
-#define FLASH_LATENCY_3                FLASH_ACR_LATENCY_3WS   /*!< FLASH Three Latency cycles    */
-#define FLASH_LATENCY_4                FLASH_ACR_LATENCY_4WS   /*!< FLASH Four Latency cycles     */
-#define FLASH_LATENCY_5                FLASH_ACR_LATENCY_5WS   /*!< FLASH Five Latency cycles     */
-#define FLASH_LATENCY_6                FLASH_ACR_LATENCY_6WS   /*!< FLASH Six Latency cycles      */
-#define FLASH_LATENCY_7                FLASH_ACR_LATENCY_7WS   /*!< FLASH Seven Latency cycles    */
-#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-/*--------------------------------------------------------------------------------------------------------------*/
-
-/**
-  * @}
-  */ 
-  
-
-/** @defgroup FLASHEx_Banks FLASH Banks
-  * @{
-  */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx)
-#define FLASH_BANK_1     ((uint32_t)1U) /*!< Bank 1   */
-#define FLASH_BANK_2     ((uint32_t)2U) /*!< Bank 2   */
-#define FLASH_BANK_BOTH  ((uint32_t)FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2  */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
-    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
-    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
-#define FLASH_BANK_1     ((uint32_t)1U) /*!< Bank 1   */
-#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-/**
-  * @}
-  */ 
-    
-/** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit
-  * @{
-  */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx)
-#define FLASH_MER_BIT     (FLASH_CR_MER1 | FLASH_CR_MER2) /*!< 2 MER bits here to clear */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
-    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
-    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
-#define FLASH_MER_BIT     (FLASH_CR_MER) /*!< only 1 MER Bit */
-#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASHEx_Sectors FLASH Sectors
-  * @{
-  */
-/*-------------------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx ------------------------------------*/   
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx)
-#define FLASH_SECTOR_0     ((uint32_t)0U)  /*!< Sector Number 0   */
-#define FLASH_SECTOR_1     ((uint32_t)1U)  /*!< Sector Number 1   */
-#define FLASH_SECTOR_2     ((uint32_t)2U)  /*!< Sector Number 2   */
-#define FLASH_SECTOR_3     ((uint32_t)3U)  /*!< Sector Number 3   */
-#define FLASH_SECTOR_4     ((uint32_t)4U)  /*!< Sector Number 4   */
-#define FLASH_SECTOR_5     ((uint32_t)5U)  /*!< Sector Number 5   */
-#define FLASH_SECTOR_6     ((uint32_t)6U)  /*!< Sector Number 6   */
-#define FLASH_SECTOR_7     ((uint32_t)7U)  /*!< Sector Number 7   */
-#define FLASH_SECTOR_8     ((uint32_t)8U)  /*!< Sector Number 8   */
-#define FLASH_SECTOR_9     ((uint32_t)9U)  /*!< Sector Number 9   */
-#define FLASH_SECTOR_10    ((uint32_t)10U) /*!< Sector Number 10  */
-#define FLASH_SECTOR_11    ((uint32_t)11U) /*!< Sector Number 11  */
-#define FLASH_SECTOR_12    ((uint32_t)12U) /*!< Sector Number 12  */
-#define FLASH_SECTOR_13    ((uint32_t)13U) /*!< Sector Number 13  */
-#define FLASH_SECTOR_14    ((uint32_t)14U) /*!< Sector Number 14  */
-#define FLASH_SECTOR_15    ((uint32_t)15U) /*!< Sector Number 15  */
-#define FLASH_SECTOR_16    ((uint32_t)16U) /*!< Sector Number 16  */
-#define FLASH_SECTOR_17    ((uint32_t)17U) /*!< Sector Number 17  */
-#define FLASH_SECTOR_18    ((uint32_t)18U) /*!< Sector Number 18  */
-#define FLASH_SECTOR_19    ((uint32_t)19U) /*!< Sector Number 19  */
-#define FLASH_SECTOR_20    ((uint32_t)20U) /*!< Sector Number 20  */
-#define FLASH_SECTOR_21    ((uint32_t)21U) /*!< Sector Number 21  */
-#define FLASH_SECTOR_22    ((uint32_t)22U) /*!< Sector Number 22  */
-#define FLASH_SECTOR_23    ((uint32_t)23U) /*!< Sector Number 23  */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
-/*-----------------------------------------------------------------------------------------------------*/  
-
-/*--------------------------------------- STM32F40xxx/STM32F41xxx -------------------------------------*/ 
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
-    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
-#define FLASH_SECTOR_0     ((uint32_t)0U)  /*!< Sector Number 0   */
-#define FLASH_SECTOR_1     ((uint32_t)1U)  /*!< Sector Number 1   */
-#define FLASH_SECTOR_2     ((uint32_t)2U)  /*!< Sector Number 2   */
-#define FLASH_SECTOR_3     ((uint32_t)3U)  /*!< Sector Number 3   */
-#define FLASH_SECTOR_4     ((uint32_t)4U)  /*!< Sector Number 4   */
-#define FLASH_SECTOR_5     ((uint32_t)5U)  /*!< Sector Number 5   */
-#define FLASH_SECTOR_6     ((uint32_t)6U)  /*!< Sector Number 6   */
-#define FLASH_SECTOR_7     ((uint32_t)7U)  /*!< Sector Number 7   */
-#define FLASH_SECTOR_8     ((uint32_t)8U)  /*!< Sector Number 8   */
-#define FLASH_SECTOR_9     ((uint32_t)9U)  /*!< Sector Number 9   */
-#define FLASH_SECTOR_10    ((uint32_t)10U) /*!< Sector Number 10  */
-#define FLASH_SECTOR_11    ((uint32_t)11U) /*!< Sector Number 11  */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-/*-----------------------------------------------------------------------------------------------------*/
-
-/*--------------------------------------------- STM32F401xC -------------------------------------------*/ 
-#if defined(STM32F401xC)
-#define FLASH_SECTOR_0     ((uint32_t)0U) /*!< Sector Number 0   */
-#define FLASH_SECTOR_1     ((uint32_t)1U) /*!< Sector Number 1   */
-#define FLASH_SECTOR_2     ((uint32_t)2U) /*!< Sector Number 2   */
-#define FLASH_SECTOR_3     ((uint32_t)3U) /*!< Sector Number 3   */
-#define FLASH_SECTOR_4     ((uint32_t)4U) /*!< Sector Number 4   */
-#define FLASH_SECTOR_5     ((uint32_t)5U) /*!< Sector Number 5   */
-#endif /* STM32F401xC */
-/*-----------------------------------------------------------------------------------------------------*/
-
-/*--------------------------------------------- STM32F410xx -------------------------------------------*/ 
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-#define FLASH_SECTOR_0     ((uint32_t)0U) /*!< Sector Number 0   */
-#define FLASH_SECTOR_1     ((uint32_t)1U) /*!< Sector Number 1   */
-#define FLASH_SECTOR_2     ((uint32_t)2U) /*!< Sector Number 2   */
-#define FLASH_SECTOR_3     ((uint32_t)3U) /*!< Sector Number 3   */
-#define FLASH_SECTOR_4     ((uint32_t)4U) /*!< Sector Number 4   */
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-/*-----------------------------------------------------------------------------------------------------*/
-
-/*---------------------------------- STM32F401xE/STM32F411xE/STM32F446xx ------------------------------*/
-#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
-#define FLASH_SECTOR_0     ((uint32_t)0U) /*!< Sector Number 0   */
-#define FLASH_SECTOR_1     ((uint32_t)1U) /*!< Sector Number 1   */
-#define FLASH_SECTOR_2     ((uint32_t)2U) /*!< Sector Number 2   */
-#define FLASH_SECTOR_3     ((uint32_t)3U) /*!< Sector Number 3   */
-#define FLASH_SECTOR_4     ((uint32_t)4U) /*!< Sector Number 4   */
-#define FLASH_SECTOR_5     ((uint32_t)5U) /*!< Sector Number 5   */
-#define FLASH_SECTOR_6     ((uint32_t)6U) /*!< Sector Number 6   */
-#define FLASH_SECTOR_7     ((uint32_t)7U) /*!< Sector Number 7   */
-#endif /* STM32F401xE || STM32F411xE || STM32F446xx */
-/*-----------------------------------------------------------------------------------------------------*/
-
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
-  * @{
-  */
-/*--------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx -------------------------*/  
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx) 
-#define OB_WRP_SECTOR_0       ((uint32_t)0x00000001U) /*!< Write protection of Sector0     */
-#define OB_WRP_SECTOR_1       ((uint32_t)0x00000002U) /*!< Write protection of Sector1     */
-#define OB_WRP_SECTOR_2       ((uint32_t)0x00000004U) /*!< Write protection of Sector2     */
-#define OB_WRP_SECTOR_3       ((uint32_t)0x00000008U) /*!< Write protection of Sector3     */
-#define OB_WRP_SECTOR_4       ((uint32_t)0x00000010U) /*!< Write protection of Sector4     */
-#define OB_WRP_SECTOR_5       ((uint32_t)0x00000020U) /*!< Write protection of Sector5     */
-#define OB_WRP_SECTOR_6       ((uint32_t)0x00000040U) /*!< Write protection of Sector6     */
-#define OB_WRP_SECTOR_7       ((uint32_t)0x00000080U) /*!< Write protection of Sector7     */
-#define OB_WRP_SECTOR_8       ((uint32_t)0x00000100U) /*!< Write protection of Sector8     */
-#define OB_WRP_SECTOR_9       ((uint32_t)0x00000200U) /*!< Write protection of Sector9     */
-#define OB_WRP_SECTOR_10      ((uint32_t)0x00000400U) /*!< Write protection of Sector10    */
-#define OB_WRP_SECTOR_11      ((uint32_t)0x00000800U) /*!< Write protection of Sector11    */
-#define OB_WRP_SECTOR_12      ((uint32_t)0x00000001U << 12) /*!< Write protection of Sector12    */
-#define OB_WRP_SECTOR_13      ((uint32_t)0x00000002U << 12) /*!< Write protection of Sector13    */
-#define OB_WRP_SECTOR_14      ((uint32_t)0x00000004U << 12) /*!< Write protection of Sector14    */
-#define OB_WRP_SECTOR_15      ((uint32_t)0x00000008U << 12) /*!< Write protection of Sector15    */
-#define OB_WRP_SECTOR_16      ((uint32_t)0x00000010U << 12) /*!< Write protection of Sector16    */
-#define OB_WRP_SECTOR_17      ((uint32_t)0x00000020U << 12) /*!< Write protection of Sector17    */
-#define OB_WRP_SECTOR_18      ((uint32_t)0x00000040U << 12) /*!< Write protection of Sector18    */
-#define OB_WRP_SECTOR_19      ((uint32_t)0x00000080U << 12) /*!< Write protection of Sector19    */
-#define OB_WRP_SECTOR_20      ((uint32_t)0x00000100U << 12) /*!< Write protection of Sector20    */
-#define OB_WRP_SECTOR_21      ((uint32_t)0x00000200U << 12) /*!< Write protection of Sector21    */
-#define OB_WRP_SECTOR_22      ((uint32_t)0x00000400U << 12) /*!< Write protection of Sector22    */
-#define OB_WRP_SECTOR_23      ((uint32_t)0x00000800U << 12) /*!< Write protection of Sector23    */
-#define OB_WRP_SECTOR_All     ((uint32_t)0x00000FFFU << 12) /*!< Write protection of all Sectors */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
-/*-----------------------------------------------------------------------------------------------------*/
-
-/*--------------------------------------- STM32F40xxx/STM32F41xxx -------------------------------------*/ 
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
-    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
-#define OB_WRP_SECTOR_0       ((uint32_t)0x00000001U) /*!< Write protection of Sector0     */
-#define OB_WRP_SECTOR_1       ((uint32_t)0x00000002U) /*!< Write protection of Sector1     */
-#define OB_WRP_SECTOR_2       ((uint32_t)0x00000004U) /*!< Write protection of Sector2     */
-#define OB_WRP_SECTOR_3       ((uint32_t)0x00000008U) /*!< Write protection of Sector3     */
-#define OB_WRP_SECTOR_4       ((uint32_t)0x00000010U) /*!< Write protection of Sector4     */
-#define OB_WRP_SECTOR_5       ((uint32_t)0x00000020U) /*!< Write protection of Sector5     */
-#define OB_WRP_SECTOR_6       ((uint32_t)0x00000040U) /*!< Write protection of Sector6     */
-#define OB_WRP_SECTOR_7       ((uint32_t)0x00000080U) /*!< Write protection of Sector7     */
-#define OB_WRP_SECTOR_8       ((uint32_t)0x00000100U) /*!< Write protection of Sector8     */
-#define OB_WRP_SECTOR_9       ((uint32_t)0x00000200U) /*!< Write protection of Sector9     */
-#define OB_WRP_SECTOR_10      ((uint32_t)0x00000400U) /*!< Write protection of Sector10    */
-#define OB_WRP_SECTOR_11      ((uint32_t)0x00000800U) /*!< Write protection of Sector11    */
-#define OB_WRP_SECTOR_All     ((uint32_t)0x00000FFFU) /*!< Write protection of all Sectors */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-/*-----------------------------------------------------------------------------------------------------*/
-
-/*--------------------------------------------- STM32F401xC -------------------------------------------*/
-#if defined(STM32F401xC)
-#define OB_WRP_SECTOR_0       ((uint32_t)0x00000001U) /*!< Write protection of Sector0     */
-#define OB_WRP_SECTOR_1       ((uint32_t)0x00000002U) /*!< Write protection of Sector1     */
-#define OB_WRP_SECTOR_2       ((uint32_t)0x00000004U) /*!< Write protection of Sector2     */
-#define OB_WRP_SECTOR_3       ((uint32_t)0x00000008U) /*!< Write protection of Sector3     */
-#define OB_WRP_SECTOR_4       ((uint32_t)0x00000010U) /*!< Write protection of Sector4     */
-#define OB_WRP_SECTOR_5       ((uint32_t)0x00000020U) /*!< Write protection of Sector5     */
-#define OB_WRP_SECTOR_All     ((uint32_t)0x00000FFFU) /*!< Write protection of all Sectors */
-#endif /* STM32F401xC */
-/*-----------------------------------------------------------------------------------------------------*/
- 
-/*--------------------------------------------- STM32F410xx -------------------------------------------*/
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-#define OB_WRP_SECTOR_0       ((uint32_t)0x00000001U) /*!< Write protection of Sector0     */
-#define OB_WRP_SECTOR_1       ((uint32_t)0x00000002U) /*!< Write protection of Sector1     */
-#define OB_WRP_SECTOR_2       ((uint32_t)0x00000004U) /*!< Write protection of Sector2     */
-#define OB_WRP_SECTOR_3       ((uint32_t)0x00000008U) /*!< Write protection of Sector3     */
-#define OB_WRP_SECTOR_4       ((uint32_t)0x00000010U) /*!< Write protection of Sector4     */
-#define OB_WRP_SECTOR_All     ((uint32_t)0x00000FFFU) /*!< Write protection of all Sectors */
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-/*-----------------------------------------------------------------------------------------------------*/
-
-/*---------------------------------- STM32F401xE/STM32F411xE/STM32F446xx ------------------------------*/
-#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
-#define OB_WRP_SECTOR_0       ((uint32_t)0x00000001U) /*!< Write protection of Sector0     */
-#define OB_WRP_SECTOR_1       ((uint32_t)0x00000002U) /*!< Write protection of Sector1     */
-#define OB_WRP_SECTOR_2       ((uint32_t)0x00000004U) /*!< Write protection of Sector2     */
-#define OB_WRP_SECTOR_3       ((uint32_t)0x00000008U) /*!< Write protection of Sector3     */
-#define OB_WRP_SECTOR_4       ((uint32_t)0x00000010U) /*!< Write protection of Sector4     */
-#define OB_WRP_SECTOR_5       ((uint32_t)0x00000020U) /*!< Write protection of Sector5     */
-#define OB_WRP_SECTOR_6       ((uint32_t)0x00000040U) /*!< Write protection of Sector6     */
-#define OB_WRP_SECTOR_7       ((uint32_t)0x00000080U) /*!< Write protection of Sector7     */
-#define OB_WRP_SECTOR_All     ((uint32_t)0x00000FFFU) /*!< Write protection of all Sectors */
-#endif /* STM32F401xE || STM32F411xE || STM32F446xx */
-/*-----------------------------------------------------------------------------------------------------*/
-/**
-  * @}
-  */
-  
-/** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection FLASH Option Bytes PC ReadWrite Protection
-  * @{
-  */
-/*-------------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx ---------------------------*/   
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx) 
-#define OB_PCROP_SECTOR_0        ((uint32_t)0x00000001U) /*!< PC Read/Write protection of Sector0      */
-#define OB_PCROP_SECTOR_1        ((uint32_t)0x00000002U) /*!< PC Read/Write protection of Sector1      */
-#define OB_PCROP_SECTOR_2        ((uint32_t)0x00000004U) /*!< PC Read/Write protection of Sector2      */
-#define OB_PCROP_SECTOR_3        ((uint32_t)0x00000008U) /*!< PC Read/Write protection of Sector3      */
-#define OB_PCROP_SECTOR_4        ((uint32_t)0x00000010U) /*!< PC Read/Write protection of Sector4      */
-#define OB_PCROP_SECTOR_5        ((uint32_t)0x00000020U) /*!< PC Read/Write protection of Sector5      */
-#define OB_PCROP_SECTOR_6        ((uint32_t)0x00000040U) /*!< PC Read/Write protection of Sector6      */
-#define OB_PCROP_SECTOR_7        ((uint32_t)0x00000080U) /*!< PC Read/Write protection of Sector7      */
-#define OB_PCROP_SECTOR_8        ((uint32_t)0x00000100U) /*!< PC Read/Write protection of Sector8      */
-#define OB_PCROP_SECTOR_9        ((uint32_t)0x00000200U) /*!< PC Read/Write protection of Sector9      */
-#define OB_PCROP_SECTOR_10       ((uint32_t)0x00000400U) /*!< PC Read/Write protection of Sector10     */
-#define OB_PCROP_SECTOR_11       ((uint32_t)0x00000800U) /*!< PC Read/Write protection of Sector11     */
-#define OB_PCROP_SECTOR_12       ((uint32_t)0x00000001U) /*!< PC Read/Write protection of Sector12     */
-#define OB_PCROP_SECTOR_13       ((uint32_t)0x00000002U) /*!< PC Read/Write protection of Sector13     */
-#define OB_PCROP_SECTOR_14       ((uint32_t)0x00000004U) /*!< PC Read/Write protection of Sector14     */
-#define OB_PCROP_SECTOR_15       ((uint32_t)0x00000008U) /*!< PC Read/Write protection of Sector15     */
-#define OB_PCROP_SECTOR_16       ((uint32_t)0x00000010U) /*!< PC Read/Write protection of Sector16     */
-#define OB_PCROP_SECTOR_17       ((uint32_t)0x00000020U) /*!< PC Read/Write protection of Sector17     */
-#define OB_PCROP_SECTOR_18       ((uint32_t)0x00000040U) /*!< PC Read/Write protection of Sector18     */
-#define OB_PCROP_SECTOR_19       ((uint32_t)0x00000080U) /*!< PC Read/Write protection of Sector19     */
-#define OB_PCROP_SECTOR_20       ((uint32_t)0x00000100U) /*!< PC Read/Write protection of Sector20     */
-#define OB_PCROP_SECTOR_21       ((uint32_t)0x00000200U) /*!< PC Read/Write protection of Sector21     */
-#define OB_PCROP_SECTOR_22       ((uint32_t)0x00000400U) /*!< PC Read/Write protection of Sector22     */
-#define OB_PCROP_SECTOR_23       ((uint32_t)0x00000800U) /*!< PC Read/Write protection of Sector23     */
-#define OB_PCROP_SECTOR_All      ((uint32_t)0x00000FFFU) /*!< PC Read/Write protection of all Sectors  */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
-/*-----------------------------------------------------------------------------------------------------*/
-
-/*--------------------------------------------- STM32F401xC -------------------------------------------*/
-#if defined(STM32F401xC)
-#define OB_PCROP_SECTOR_0        ((uint32_t)0x00000001U) /*!< PC Read/Write protection of Sector0      */
-#define OB_PCROP_SECTOR_1        ((uint32_t)0x00000002U) /*!< PC Read/Write protection of Sector1      */
-#define OB_PCROP_SECTOR_2        ((uint32_t)0x00000004U) /*!< PC Read/Write protection of Sector2      */
-#define OB_PCROP_SECTOR_3        ((uint32_t)0x00000008U) /*!< PC Read/Write protection of Sector3      */
-#define OB_PCROP_SECTOR_4        ((uint32_t)0x00000010U) /*!< PC Read/Write protection of Sector4      */
-#define OB_PCROP_SECTOR_5        ((uint32_t)0x00000020U) /*!< PC Read/Write protection of Sector5      */
-#define OB_PCROP_SECTOR_All      ((uint32_t)0x00000FFFU) /*!< PC Read/Write protection of all Sectors  */
-#endif /* STM32F401xC */
-/*-----------------------------------------------------------------------------------------------------*/
-
-/*--------------------------------------------- STM32F410xx -------------------------------------------*/
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-#define OB_PCROP_SECTOR_0        ((uint32_t)0x00000001U) /*!< PC Read/Write protection of Sector0      */
-#define OB_PCROP_SECTOR_1        ((uint32_t)0x00000002U) /*!< PC Read/Write protection of Sector1      */
-#define OB_PCROP_SECTOR_2        ((uint32_t)0x00000004U) /*!< PC Read/Write protection of Sector2      */
-#define OB_PCROP_SECTOR_3        ((uint32_t)0x00000008U) /*!< PC Read/Write protection of Sector3      */
-#define OB_PCROP_SECTOR_4        ((uint32_t)0x00000010U) /*!< PC Read/Write protection of Sector4      */
-#define OB_PCROP_SECTOR_All      ((uint32_t)0x00000FFFU) /*!< PC Read/Write protection of all Sectors  */
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-/*-----------------------------------------------------------------------------------------------------*/
-
-/*-------------- STM32F401xE/STM32F411xE/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F446xx --*/
-#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
-    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
-#define OB_PCROP_SECTOR_0        ((uint32_t)0x00000001U) /*!< PC Read/Write protection of Sector0      */
-#define OB_PCROP_SECTOR_1        ((uint32_t)0x00000002U) /*!< PC Read/Write protection of Sector1      */
-#define OB_PCROP_SECTOR_2        ((uint32_t)0x00000004U) /*!< PC Read/Write protection of Sector2      */
-#define OB_PCROP_SECTOR_3        ((uint32_t)0x00000008U) /*!< PC Read/Write protection of Sector3      */
-#define OB_PCROP_SECTOR_4        ((uint32_t)0x00000010U) /*!< PC Read/Write protection of Sector4      */
-#define OB_PCROP_SECTOR_5        ((uint32_t)0x00000020U) /*!< PC Read/Write protection of Sector5      */
-#define OB_PCROP_SECTOR_6        ((uint32_t)0x00000040U) /*!< PC Read/Write protection of Sector6      */
-#define OB_PCROP_SECTOR_7        ((uint32_t)0x00000080U) /*!< PC Read/Write protection of Sector7      */
-#define OB_PCROP_SECTOR_All      ((uint32_t)0x00000FFFU) /*!< PC Read/Write protection of all Sectors  */
-#endif /* STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-/*-----------------------------------------------------------------------------------------------------*/
-
-/**
-  * @}
-  */
-  
-/** @defgroup FLASHEx_Dual_Boot FLASH Dual Boot
-  * @{
-  */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx) 
-#define OB_DUAL_BOOT_ENABLE   ((uint8_t)0x10U) /*!< Dual Bank Boot Enable                             */
-#define OB_DUAL_BOOT_DISABLE  ((uint8_t)0x00U) /*!< Dual Bank Boot Disable, always boot on User Flash */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
-/**
-  * @}
-  */
-
-/** @defgroup  FLASHEx_Selection_Protection_Mode FLASH Selection Protection Mode
-  * @{
-  */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
-    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
-    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
-    defined(STM32F412Cx)  
-#define OB_PCROP_DESELECTED     ((uint8_t)0x00U) /*!< Disabled PcROP, nWPRi bits used for Write Protection on sector i */
-#define OB_PCROP_SELECTED       ((uint8_t)0x80U) /*!< Enable PcROP, nWPRi bits used for PCRoP Protection on sector i   */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
-          STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
-          STM32F412Vx || STM32F412Rx || STM32F412Cx */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-  
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup FLASHEx_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup FLASHEx_Exported_Functions_Group1
-  * @{
-  */
-/* Extension Program operation functions  *************************************/
-HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);
-HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
-HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
-void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
-    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
-    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
-    defined(STM32F412Cx)  
-HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
-void              HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
-HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void);
-HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void);
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
-          STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
-          STM32F412Vx || STM32F412Rx || STM32F412Cx */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx)
-uint16_t          HAL_FLASHEx_OB_GetBank2WRP(void);
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup FLASHEx_Private_Constants FLASH Private Constants
-  * @{
-  */
-/*--------------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx---------------------*/ 
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-#define FLASH_SECTOR_TOTAL  24U
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-
-/*--------------------------------------- STM32F40xxx/STM32F41xxx -------------------------------------*/ 
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
-    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
-#define FLASH_SECTOR_TOTAL  12U
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-
-/*--------------------------------------------- STM32F401xC -------------------------------------------*/ 
-#if defined(STM32F401xC)
-#define FLASH_SECTOR_TOTAL  6U
-#endif /* STM32F401xC */
-
-/*--------------------------------------------- STM32F410xx -------------------------------------------*/ 
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-#define FLASH_SECTOR_TOTAL  5U
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-
-/*--------------------------------- STM32F401xE/STM32F411xE/STM32F412xG/STM32F446xx -------------------*/
-#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
-#define FLASH_SECTOR_TOTAL  8U
-#endif /* STM32F401xE || STM32F411xE || STM32F446xx */
-
-/** 
-  * @brief OPTCR1 register byte 2 (Bits[23:16]) base address  
-  */ 
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)  
-#define OPTCR1_BYTE2_ADDRESS         ((uint32_t)0x40023C1AU)
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup FLASHEx_Private_Macros FLASH Private Macros
-  * @{
-  */
-
-/** @defgroup FLASHEx_IS_FLASH_Definitions FLASH Private macros to check input parameters
-  * @{
-  */
-
-#define IS_FLASH_TYPEERASE(VALUE)(((VALUE) == FLASH_TYPEERASE_SECTORS) || \
-                                  ((VALUE) == FLASH_TYPEERASE_MASSERASE))  
-
-#define IS_VOLTAGERANGE(RANGE)(((RANGE) == FLASH_VOLTAGE_RANGE_1) || \
-                               ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \
-                               ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \
-                               ((RANGE) == FLASH_VOLTAGE_RANGE_4))  
-
-#define IS_WRPSTATE(VALUE)(((VALUE) == OB_WRPSTATE_DISABLE) || \
-                           ((VALUE) == OB_WRPSTATE_ENABLE))  
-
-#define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP|OPTIONBYTE_RDP|OPTIONBYTE_USER|OPTIONBYTE_BOR)))
-
-#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
-                                ((LEVEL) == OB_RDP_LEVEL_1) ||\
-                                ((LEVEL) == OB_RDP_LEVEL_2))
-
-#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
-
-#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
-
-#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
-
-#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
-                                ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
-    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
-    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
-    defined(STM32F412Cx)  
-#define IS_PCROPSTATE(VALUE)(((VALUE) == OB_PCROP_STATE_DISABLE) || \
-                             ((VALUE) == OB_PCROP_STATE_ENABLE))  
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
-          STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
-          STM32F412Vx || STM32F412Rx || STM32F412Cx */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx)
-#define IS_OBEX(VALUE)(((VALUE) == OPTIONBYTE_PCROP) || \
-                       ((VALUE) == OPTIONBYTE_BOOTCONFIG))  
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
-    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
-    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
-#define IS_OBEX(VALUE)(((VALUE) == OPTIONBYTE_PCROP))  
-#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx ||\
-          STM32F412Vx || STM32F412Rx || STM32F412Cx */
-  
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
-    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
-#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0)  || \
-                                   ((LATENCY) == FLASH_LATENCY_1)  || \
-                                   ((LATENCY) == FLASH_LATENCY_2)  || \
-                                   ((LATENCY) == FLASH_LATENCY_3)  || \
-                                   ((LATENCY) == FLASH_LATENCY_4)  || \
-                                   ((LATENCY) == FLASH_LATENCY_5)  || \
-                                   ((LATENCY) == FLASH_LATENCY_6)  || \
-                                   ((LATENCY) == FLASH_LATENCY_7)  || \
-                                   ((LATENCY) == FLASH_LATENCY_8)  || \
-                                   ((LATENCY) == FLASH_LATENCY_9)  || \
-                                   ((LATENCY) == FLASH_LATENCY_10) || \
-                                   ((LATENCY) == FLASH_LATENCY_11) || \
-                                   ((LATENCY) == FLASH_LATENCY_12) || \
-                                   ((LATENCY) == FLASH_LATENCY_13) || \
-                                   ((LATENCY) == FLASH_LATENCY_14) || \
-                                   ((LATENCY) == FLASH_LATENCY_15))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
-    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
-    defined(STM32F412Rx) || defined(STM32F412Cx)  
-#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0)  || \
-                                   ((LATENCY) == FLASH_LATENCY_1)  || \
-                                   ((LATENCY) == FLASH_LATENCY_2)  || \
-                                   ((LATENCY) == FLASH_LATENCY_3)  || \
-                                   ((LATENCY) == FLASH_LATENCY_4)  || \
-                                   ((LATENCY) == FLASH_LATENCY_5)  || \
-                                   ((LATENCY) == FLASH_LATENCY_6)  || \
-                                   ((LATENCY) == FLASH_LATENCY_7))
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F412Zx || STM32F412Vx ||\
-          STM32F412Rx || STM32F412Cx */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1)  || \
-                             ((BANK) == FLASH_BANK_2)  || \
-                             ((BANK) == FLASH_BANK_BOTH))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
-    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
-    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
-#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx ||\
-          STM32F412Rx || STM32F412Cx */
- 
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-#define IS_FLASH_SECTOR(SECTOR) ( ((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
-                                  ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
-                                  ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5)   ||\
-                                  ((SECTOR) == FLASH_SECTOR_6)   || ((SECTOR) == FLASH_SECTOR_7)   ||\
-                                  ((SECTOR) == FLASH_SECTOR_8)   || ((SECTOR) == FLASH_SECTOR_9)   ||\
-                                  ((SECTOR) == FLASH_SECTOR_10)  || ((SECTOR) == FLASH_SECTOR_11)  ||\
-                                  ((SECTOR) == FLASH_SECTOR_12)  || ((SECTOR) == FLASH_SECTOR_13)  ||\
-                                  ((SECTOR) == FLASH_SECTOR_14)  || ((SECTOR) == FLASH_SECTOR_15)  ||\
-                                  ((SECTOR) == FLASH_SECTOR_16)  || ((SECTOR) == FLASH_SECTOR_17)  ||\
-                                  ((SECTOR) == FLASH_SECTOR_18)  || ((SECTOR) == FLASH_SECTOR_19)  ||\
-                                  ((SECTOR) == FLASH_SECTOR_20)  || ((SECTOR) == FLASH_SECTOR_21)  ||\
-                                  ((SECTOR) == FLASH_SECTOR_22)  || ((SECTOR) == FLASH_SECTOR_23))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
-    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
-#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
-                                 ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
-                                 ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5)   ||\
-                                 ((SECTOR) == FLASH_SECTOR_6)   || ((SECTOR) == FLASH_SECTOR_7)   ||\
-                                 ((SECTOR) == FLASH_SECTOR_8)   || ((SECTOR) == FLASH_SECTOR_9)   ||\
-                                 ((SECTOR) == FLASH_SECTOR_10)  || ((SECTOR) == FLASH_SECTOR_11))
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-
-#if defined(STM32F401xC)
-#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
-                                 ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
-                                 ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5))
-#endif /* STM32F401xC */
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
-                                 ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
-                                 ((SECTOR) == FLASH_SECTOR_4))
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-
-#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
-#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
-                                 ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
-                                 ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5)   ||\
-                                 ((SECTOR) == FLASH_SECTOR_6)   || ((SECTOR) == FLASH_SECTOR_7))
-#endif /* STM32F401xE || STM32F411xE || STM32F446xx */
-
-#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END))
-#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
-  
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 
-#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFF000000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
-#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
-
-#if defined(STM32F401xC)
-#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
-#endif /* STM32F401xC */
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-
-#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
-    defined(STM32F412Rx) || defined(STM32F412Cx)  
-#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
-#endif /* STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-   
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-#define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F401xC)
-#define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
-#endif /* STM32F401xC */
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-#define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-
-#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
-    defined(STM32F412Rx) || defined(STM32F412Cx)  
-#define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
-#endif /* STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx) 
-#define IS_OB_BOOT(BOOT) (((BOOT) == OB_DUAL_BOOT_ENABLE) || ((BOOT) == OB_DUAL_BOOT_DISABLE))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
-    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
-    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
-    defined(STM32F412Cx)   
-#define IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PCROP_SELECTED) || ((PCROP) == OB_PCROP_DESELECTED))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
-          STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
-          STM32F412Vx || STM32F412Rx || STM32F412Cx */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup FLASHEx_Private_Functions FLASH Private Functions
-  * @{
-  */
-void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange);
-void FLASH_FlushCaches(void);
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_FLASH_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_flash_ramfunc.h b/stmhal/hal/f4/inc/stm32f4xx_hal_flash_ramfunc.h
deleted file mode 100644
index f9545e89bb..0000000000
--- a/stmhal/hal/f4/inc/stm32f4xx_hal_flash_ramfunc.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_flash_ramfunc.h
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   Header file of FLASH RAMFUNC driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_FLASH_RAMFUNC_H
-#define __STM32F4xx_FLASH_RAMFUNC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
-    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup FLASH_RAMFUNC
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup FLASH_RAMFUNC_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1
-  * @{
-  */   
-__RAM_FUNC HAL_FLASHEx_StopFlashInterfaceClk(void);
-__RAM_FUNC HAL_FLASHEx_StartFlashInterfaceClk(void);
-__RAM_FUNC HAL_FLASHEx_EnableFlashSleepMode(void);
-__RAM_FUNC HAL_FLASHEx_DisableFlashSleepMode(void);
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */  
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F4xx_FLASH_RAMFUNC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_gpio.h b/stmhal/hal/f4/inc/stm32f4xx_hal_gpio.h
deleted file mode 100644
index 853cf638d1..0000000000
--- a/stmhal/hal/f4/inc/stm32f4xx_hal_gpio.h
+++ /dev/null
@@ -1,327 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_gpio.h
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   Header file of GPIO HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_GPIO_H
-#define __STM32F4xx_HAL_GPIO_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup GPIO
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup GPIO_Exported_Types GPIO Exported Types
-  * @{
-  */
-
-/** 
-  * @brief GPIO Init structure definition  
-  */ 
-typedef struct
-{
-  uint32_t Pin;       /*!< Specifies the GPIO pins to be configured.
-                           This parameter can be any value of @ref GPIO_pins_define */
-
-  uint32_t Mode;      /*!< Specifies the operating mode for the selected pins.
-                           This parameter can be a value of @ref GPIO_mode_define */
-
-  uint32_t Pull;      /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
-                           This parameter can be a value of @ref GPIO_pull_define */
-
-  uint32_t Speed;     /*!< Specifies the speed for the selected pins.
-                           This parameter can be a value of @ref GPIO_speed_define */
-
-  uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins. 
-                            This parameter can be a value of @ref GPIO_Alternate_function_selection */
-}GPIO_InitTypeDef;
-
-/** 
-  * @brief  GPIO Bit SET and Bit RESET enumeration 
-  */
-typedef enum
-{
-  GPIO_PIN_RESET = 0,
-  GPIO_PIN_SET
-}GPIO_PinState;
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
-  * @{
-  */ 
-
-/** @defgroup GPIO_pins_define GPIO pins define
-  * @{
-  */
-#define GPIO_PIN_0                 ((uint16_t)0x0001U)  /* Pin 0 selected    */
-#define GPIO_PIN_1                 ((uint16_t)0x0002U)  /* Pin 1 selected    */
-#define GPIO_PIN_2                 ((uint16_t)0x0004U)  /* Pin 2 selected    */
-#define GPIO_PIN_3                 ((uint16_t)0x0008U)  /* Pin 3 selected    */
-#define GPIO_PIN_4                 ((uint16_t)0x0010U)  /* Pin 4 selected    */
-#define GPIO_PIN_5                 ((uint16_t)0x0020U)  /* Pin 5 selected    */
-#define GPIO_PIN_6                 ((uint16_t)0x0040U)  /* Pin 6 selected    */
-#define GPIO_PIN_7                 ((uint16_t)0x0080U)  /* Pin 7 selected    */
-#define GPIO_PIN_8                 ((uint16_t)0x0100U)  /* Pin 8 selected    */
-#define GPIO_PIN_9                 ((uint16_t)0x0200U)  /* Pin 9 selected    */
-#define GPIO_PIN_10                ((uint16_t)0x0400U)  /* Pin 10 selected   */
-#define GPIO_PIN_11                ((uint16_t)0x0800U)  /* Pin 11 selected   */
-#define GPIO_PIN_12                ((uint16_t)0x1000U)  /* Pin 12 selected   */
-#define GPIO_PIN_13                ((uint16_t)0x2000U)  /* Pin 13 selected   */
-#define GPIO_PIN_14                ((uint16_t)0x4000U)  /* Pin 14 selected   */
-#define GPIO_PIN_15                ((uint16_t)0x8000U)  /* Pin 15 selected   */
-#define GPIO_PIN_All               ((uint16_t)0xFFFFU)  /* All pins selected */
-
-#define GPIO_PIN_MASK              ((uint32_t)0x0000FFFFU) /* PIN mask for assert test */
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_mode_define GPIO mode define
-  * @brief GPIO Configuration Mode 
-  *        Elements values convention: 0xX0yz00YZ
-  *           - X  : GPIO mode or EXTI Mode
-  *           - y  : External IT or Event trigger detection 
-  *           - z  : IO configuration on External IT or Event
-  *           - Y  : Output type (Push Pull or Open Drain)
-  *           - Z  : IO Direction mode (Input, Output, Alternate or Analog)
-  * @{
-  */ 
-#define  GPIO_MODE_INPUT                        ((uint32_t)0x00000000U)   /*!< Input Floating Mode                   */
-#define  GPIO_MODE_OUTPUT_PP                    ((uint32_t)0x00000001U)   /*!< Output Push Pull Mode                 */
-#define  GPIO_MODE_OUTPUT_OD                    ((uint32_t)0x00000011U)   /*!< Output Open Drain Mode                */
-#define  GPIO_MODE_AF_PP                        ((uint32_t)0x00000002U)   /*!< Alternate Function Push Pull Mode     */
-#define  GPIO_MODE_AF_OD                        ((uint32_t)0x00000012U)   /*!< Alternate Function Open Drain Mode    */
-
-#define  GPIO_MODE_ANALOG                       ((uint32_t)0x00000003U)   /*!< Analog Mode  */
-    
-#define  GPIO_MODE_IT_RISING                    ((uint32_t)0x10110000U)   /*!< External Interrupt Mode with Rising edge trigger detection          */
-#define  GPIO_MODE_IT_FALLING                   ((uint32_t)0x10210000U)   /*!< External Interrupt Mode with Falling edge trigger detection         */
-#define  GPIO_MODE_IT_RISING_FALLING            ((uint32_t)0x10310000U)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
- 
-#define  GPIO_MODE_EVT_RISING                   ((uint32_t)0x10120000U)   /*!< External Event Mode with Rising edge trigger detection               */
-#define  GPIO_MODE_EVT_FALLING                  ((uint32_t)0x10220000U)   /*!< External Event Mode with Falling edge trigger detection              */
-#define  GPIO_MODE_EVT_RISING_FALLING           ((uint32_t)0x10320000U)   /*!< External Event Mode with Rising/Falling edge trigger detection       */
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_speed_define  GPIO speed define
-  * @brief GPIO Output Maximum frequency
-  * @{
-  */
-#define  GPIO_SPEED_FREQ_LOW         ((uint32_t)0x00000000U)  /*!< IO works at 2 MHz, please refer to the product datasheet */
-#define  GPIO_SPEED_FREQ_MEDIUM      ((uint32_t)0x00000001U)  /*!< range 12,5 MHz to 50 MHz, please refer to the product datasheet */
-#define  GPIO_SPEED_FREQ_HIGH        ((uint32_t)0x00000002U)  /*!< range 25 MHz to 100 MHz, please refer to the product datasheet  */
-#define  GPIO_SPEED_FREQ_VERY_HIGH   ((uint32_t)0x00000003U)  /*!< range 50 MHz to 200 MHz, please refer to the product datasheet  */
-/**
-  * @}
-  */
-
- /** @defgroup GPIO_pull_define GPIO pull define
-   * @brief GPIO Pull-Up or Pull-Down Activation
-   * @{
-   */  
-#define  GPIO_NOPULL        ((uint32_t)0x00000000U)   /*!< No Pull-up or Pull-down activation  */
-#define  GPIO_PULLUP        ((uint32_t)0x00000001U)   /*!< Pull-up activation                  */
-#define  GPIO_PULLDOWN      ((uint32_t)0x00000002U)   /*!< Pull-down activation                */
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
-  * @{
-  */
-
-/**
-  * @brief  Checks whether the specified EXTI line flag is set or not.
-  * @param  __EXTI_LINE__: specifies the EXTI line flag to check.
-  *         This parameter can be GPIO_PIN_x where x can be(0..15)
-  * @retval The new state of __EXTI_LINE__ (SET or RESET).
-  */
-#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
-
-/**
-  * @brief  Clears the EXTI's line pending flags.
-  * @param  __EXTI_LINE__: specifies the EXTI lines flags to clear.
-  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
-  * @retval None
-  */
-#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
-
-/**
-  * @brief  Checks whether the specified EXTI line is asserted or not.
-  * @param  __EXTI_LINE__: specifies the EXTI line to check.
-  *          This parameter can be GPIO_PIN_x where x can be(0..15)
-  * @retval The new state of __EXTI_LINE__ (SET or RESET).
-  */
-#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
-
-/**
-  * @brief  Clears the EXTI's line pending bits.
-  * @param  __EXTI_LINE__: specifies the EXTI lines to clear.
-  *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
-  * @retval None
-  */
-#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
-
-/**
-  * @brief  Generates a Software interrupt on selected EXTI line.
-  * @param  __EXTI_LINE__: specifies the EXTI line to check.
-  *          This parameter can be GPIO_PIN_x where x can be(0..15)
-  * @retval None
-  */
-#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
-/**
-  * @}
-  */
-
-/* Include GPIO HAL Extension module */
-#include "stm32f4xx_hal_gpio_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup GPIO_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup GPIO_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization and de-initialization functions *****************************/
-void  HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init);
-void  HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);
-/**
-  * @}
-  */
-
-/** @addtogroup GPIO_Exported_Functions_Group2
-  * @{
-  */
-/* IO operation functions *****************************************************/
-GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
-void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
-void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup GPIO_Private_Constants GPIO Private Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup GPIO_Private_Macros GPIO Private Macros
-  * @{
-  */
-#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
-#define IS_GPIO_PIN(PIN)           (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00U)
-#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT)              ||\
-                            ((MODE) == GPIO_MODE_OUTPUT_PP)          ||\
-                            ((MODE) == GPIO_MODE_OUTPUT_OD)          ||\
-                            ((MODE) == GPIO_MODE_AF_PP)              ||\
-                            ((MODE) == GPIO_MODE_AF_OD)              ||\
-                            ((MODE) == GPIO_MODE_IT_RISING)          ||\
-                            ((MODE) == GPIO_MODE_IT_FALLING)         ||\
-                            ((MODE) == GPIO_MODE_IT_RISING_FALLING)  ||\
-                            ((MODE) == GPIO_MODE_EVT_RISING)         ||\
-                            ((MODE) == GPIO_MODE_EVT_FALLING)        ||\
-                            ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
-                            ((MODE) == GPIO_MODE_ANALOG))
-#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW)  || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \
-                              ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH))
-#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
-                            ((PULL) == GPIO_PULLDOWN))
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup GPIO_Private_Functions GPIO Private Functions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_GPIO_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_gpio_ex.h b/stmhal/hal/f4/inc/stm32f4xx_hal_gpio_ex.h
deleted file mode 100644
index afdaadf71a..0000000000
--- a/stmhal/hal/f4/inc/stm32f4xx_hal_gpio_ex.h
+++ /dev/null
@@ -1,1450 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_gpio_ex.h
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   Header file of GPIO HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_GPIO_EX_H
-#define __STM32F4xx_HAL_GPIO_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup GPIOEx GPIOEx
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants
-  * @{
-  */
-  
-/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection
-  * @{
-  */
-
-/*------------------------------------------ STM32F429xx/STM32F439xx ---------*/
-#if defined(STM32F429xx) || defined(STM32F439xx)
-/** 
-  * @brief   AF 0 selection  
-  */ 
-#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */
-#define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
-#define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
-#define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */
-
-/** 
-  * @brief   AF 1 selection  
-  */ 
-#define GPIO_AF1_TIM1          ((uint8_t)0x01U)  /* TIM1 Alternate Function mapping */
-#define GPIO_AF1_TIM2          ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */
-
-/** 
-  * @brief   AF 2 selection  
-  */ 
-#define GPIO_AF2_TIM3          ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4          ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM5          ((uint8_t)0x02U)  /* TIM5 Alternate Function mapping */
-
-/** 
-  * @brief   AF 3 selection  
-  */ 
-#define GPIO_AF3_TIM8          ((uint8_t)0x03U)  /* TIM8 Alternate Function mapping  */
-#define GPIO_AF3_TIM9          ((uint8_t)0x03U)  /* TIM9 Alternate Function mapping  */
-#define GPIO_AF3_TIM10         ((uint8_t)0x03U)  /* TIM10 Alternate Function mapping */
-#define GPIO_AF3_TIM11         ((uint8_t)0x03U)  /* TIM11 Alternate Function mapping */
-
-/** 
-  * @brief   AF 4 selection  
-  */ 
-#define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */
-#define GPIO_AF4_I2C3          ((uint8_t)0x04U)  /* I2C3 Alternate Function mapping */
-
-/** 
-  * @brief   AF 5 selection  
-  */ 
-#define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1 Alternate Function mapping        */
-#define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping   */
-#define GPIO_AF5_SPI3          ((uint8_t)0x05U)  /* SPI3/I2S3 Alternate Function mapping   */
-#define GPIO_AF5_SPI4          ((uint8_t)0x05U)  /* SPI4 Alternate Function mapping        */
-#define GPIO_AF5_SPI5          ((uint8_t)0x05U)  /* SPI5 Alternate Function mapping        */
-#define GPIO_AF5_SPI6          ((uint8_t)0x05U)  /* SPI6 Alternate Function mapping        */
-#define GPIO_AF5_I2S3ext       ((uint8_t)0x05U)  /* I2S3ext_SD Alternate Function mapping  */
-
-/** 
-  * @brief   AF 6 selection  
-  */ 
-#define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping  */
-#define GPIO_AF6_I2S2ext       ((uint8_t)0x06U)  /* I2S2ext_SD Alternate Function mapping */
-#define GPIO_AF6_SAI1          ((uint8_t)0x06U)  /* SAI1 Alternate Function mapping       */
-
-/** 
-  * @brief   AF 7 selection  
-  */ 
-#define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping     */
-#define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping     */
-#define GPIO_AF7_USART3        ((uint8_t)0x07U)  /* USART3 Alternate Function mapping     */
-#define GPIO_AF7_I2S3ext       ((uint8_t)0x07U)  /* I2S3ext_SD Alternate Function mapping */
-
-/** 
-  * @brief   AF 8 selection  
-  */ 
-#define GPIO_AF8_UART4         ((uint8_t)0x08U)  /* UART4 Alternate Function mapping  */
-#define GPIO_AF8_UART5         ((uint8_t)0x08U)  /* UART5 Alternate Function mapping  */
-#define GPIO_AF8_USART6        ((uint8_t)0x08U)  /* USART6 Alternate Function mapping */
-#define GPIO_AF8_UART7         ((uint8_t)0x08U)  /* UART7 Alternate Function mapping  */
-#define GPIO_AF8_UART8         ((uint8_t)0x08U)  /* UART8 Alternate Function mapping  */
-
-/** 
-  * @brief   AF 9 selection 
-  */ 
-#define GPIO_AF9_CAN1          ((uint8_t)0x09U)  /* CAN1 Alternate Function mapping    */
-#define GPIO_AF9_CAN2          ((uint8_t)0x09U)  /* CAN2 Alternate Function mapping    */
-#define GPIO_AF9_TIM12         ((uint8_t)0x09U)  /* TIM12 Alternate Function mapping   */
-#define GPIO_AF9_TIM13         ((uint8_t)0x09U)  /* TIM13 Alternate Function mapping   */
-#define GPIO_AF9_TIM14         ((uint8_t)0x09U)  /* TIM14 Alternate Function mapping   */
-#define GPIO_AF9_LTDC          ((uint8_t)0x09U)  /* LCD-TFT Alternate Function mapping */
-
-/** 
-  * @brief   AF 10 selection  
-  */ 
-#define GPIO_AF10_OTG_FS        ((uint8_t)0x0AU)  /* OTG_FS Alternate Function mapping */
-#define GPIO_AF10_OTG_HS        ((uint8_t)0x0AU)  /* OTG_HS Alternate Function mapping */
-
-/** 
-  * @brief   AF 11 selection  
-  */ 
-#define GPIO_AF11_ETH           ((uint8_t)0x0BU)  /* ETHERNET Alternate Function mapping */
-
-/** 
-  * @brief   AF 12 selection  
-  */ 
-#define GPIO_AF12_FMC           ((uint8_t)0x0CU)  /* FMC Alternate Function mapping                      */
-#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0CU)  /* OTG HS configured in FS, Alternate Function mapping */
-#define GPIO_AF12_SDIO          ((uint8_t)0x0CU)  /* SDIO Alternate Function mapping                     */
-
-/** 
-  * @brief   AF 13 selection  
-  */ 
-#define GPIO_AF13_DCMI          ((uint8_t)0x0DU)  /* DCMI Alternate Function mapping */
-
-/** 
-  * @brief   AF 14 selection  
-  */
-#define GPIO_AF14_LTDC          ((uint8_t)0x0EU)  /* LCD-TFT Alternate Function mapping */
-
-/** 
-  * @brief   AF 15 selection  
-  */ 
-#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */
-#endif /* STM32F429xx || STM32F439xx */
-/*----------------------------------------------------------------------------*/
-
-/*---------------------------------- STM32F427xx/STM32F437xx------------------*/
-#if defined(STM32F427xx) || defined(STM32F437xx)
-/** 
-  * @brief   AF 0 selection  
-  */ 
-#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */
-#define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
-#define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
-#define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */
-
-/** 
-  * @brief   AF 1 selection  
-  */ 
-#define GPIO_AF1_TIM1          ((uint8_t)0x01U)  /* TIM1 Alternate Function mapping */
-#define GPIO_AF1_TIM2          ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */
-
-/** 
-  * @brief   AF 2 selection  
-  */ 
-#define GPIO_AF2_TIM3          ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4          ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM5          ((uint8_t)0x02U)  /* TIM5 Alternate Function mapping */
-
-/** 
-  * @brief   AF 3 selection  
-  */ 
-#define GPIO_AF3_TIM8          ((uint8_t)0x03U)  /* TIM8 Alternate Function mapping  */
-#define GPIO_AF3_TIM9          ((uint8_t)0x03U)  /* TIM9 Alternate Function mapping  */
-#define GPIO_AF3_TIM10         ((uint8_t)0x03U)  /* TIM10 Alternate Function mapping */
-#define GPIO_AF3_TIM11         ((uint8_t)0x03U)  /* TIM11 Alternate Function mapping */
-
-/** 
-  * @brief   AF 4 selection  
-  */ 
-#define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */
-#define GPIO_AF4_I2C3          ((uint8_t)0x04U)  /* I2C3 Alternate Function mapping */
-
-/** 
-  * @brief   AF 5 selection  
-  */ 
-#define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1 Alternate Function mapping        */
-#define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping   */
-#define GPIO_AF5_SPI3          ((uint8_t)0x05U)  /* SPI3/I2S3 Alternate Function mapping   */
-#define GPIO_AF5_SPI4          ((uint8_t)0x05U)  /* SPI4 Alternate Function mapping        */
-#define GPIO_AF5_SPI5          ((uint8_t)0x05U)  /* SPI5 Alternate Function mapping        */
-#define GPIO_AF5_SPI6          ((uint8_t)0x05U)  /* SPI6 Alternate Function mapping        */
-/** @brief  GPIO_Legacy 
-  */
-#define GPIO_AF5_I2S3ext       GPIO_AF5_SPI3    /* I2S3ext_SD Alternate Function mapping  */
-
-/** 
-  * @brief   AF 6 selection  
-  */ 
-#define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping  */
-#define GPIO_AF6_I2S2ext       ((uint8_t)0x06U)  /* I2S2ext_SD Alternate Function mapping */
-#define GPIO_AF6_SAI1          ((uint8_t)0x06U)  /* SAI1 Alternate Function mapping       */
-
-/** 
-  * @brief   AF 7 selection  
-  */ 
-#define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping     */
-#define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping     */
-#define GPIO_AF7_USART3        ((uint8_t)0x07U)  /* USART3 Alternate Function mapping     */
-#define GPIO_AF7_I2S3ext       ((uint8_t)0x07U)  /* I2S3ext_SD Alternate Function mapping */
-
-/** 
-  * @brief   AF 8 selection  
-  */ 
-#define GPIO_AF8_UART4         ((uint8_t)0x08U)  /* UART4 Alternate Function mapping  */
-#define GPIO_AF8_UART5         ((uint8_t)0x08U)  /* UART5 Alternate Function mapping  */
-#define GPIO_AF8_USART6        ((uint8_t)0x08U)  /* USART6 Alternate Function mapping */
-#define GPIO_AF8_UART7         ((uint8_t)0x08U)  /* UART7 Alternate Function mapping  */
-#define GPIO_AF8_UART8         ((uint8_t)0x08U)  /* UART8 Alternate Function mapping  */
-
-/** 
-  * @brief   AF 9 selection 
-  */ 
-#define GPIO_AF9_CAN1          ((uint8_t)0x09U)  /* CAN1 Alternate Function mapping  */
-#define GPIO_AF9_CAN2          ((uint8_t)0x09U)  /* CAN2 Alternate Function mapping  */
-#define GPIO_AF9_TIM12         ((uint8_t)0x09U)  /* TIM12 Alternate Function mapping */
-#define GPIO_AF9_TIM13         ((uint8_t)0x09U)  /* TIM13 Alternate Function mapping */
-#define GPIO_AF9_TIM14         ((uint8_t)0x09U)  /* TIM14 Alternate Function mapping */
-
-/** 
-  * @brief   AF 10 selection  
-  */ 
-#define GPIO_AF10_OTG_FS        ((uint8_t)0x0AU)  /* OTG_FS Alternate Function mapping */
-#define GPIO_AF10_OTG_HS        ((uint8_t)0x0AU)  /* OTG_HS Alternate Function mapping */
-
-/** 
-  * @brief   AF 11 selection  
-  */ 
-#define GPIO_AF11_ETH           ((uint8_t)0x0BU)  /* ETHERNET Alternate Function mapping */
-
-/** 
-  * @brief   AF 12 selection  
-  */ 
-#define GPIO_AF12_FMC           ((uint8_t)0x0CU)  /* FMC Alternate Function mapping                      */
-#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0CU)  /* OTG HS configured in FS, Alternate Function mapping */
-#define GPIO_AF12_SDIO          ((uint8_t)0x0CU)  /* SDIO Alternate Function mapping                     */
-
-/** 
-  * @brief   AF 13 selection  
-  */ 
-#define GPIO_AF13_DCMI          ((uint8_t)0x0DU)  /* DCMI Alternate Function mapping */
-
-/** 
-  * @brief   AF 15 selection  
-  */ 
-#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */
-#endif /* STM32F427xx || STM32F437xx */
-/*----------------------------------------------------------------------------*/
-
-/*---------------------------------- STM32F407xx/STM32F417xx------------------*/
-#if defined(STM32F407xx) || defined(STM32F417xx)
-/** 
-  * @brief   AF 0 selection  
-  */ 
-#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */
-#define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
-#define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
-#define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */
-
-/** 
-  * @brief   AF 1 selection  
-  */ 
-#define GPIO_AF1_TIM1          ((uint8_t)0x01U)  /* TIM1 Alternate Function mapping */
-#define GPIO_AF1_TIM2          ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */
-
-/** 
-  * @brief   AF 2 selection  
-  */ 
-#define GPIO_AF2_TIM3          ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4          ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM5          ((uint8_t)0x02U)  /* TIM5 Alternate Function mapping */
-
-/** 
-  * @brief   AF 3 selection  
-  */ 
-#define GPIO_AF3_TIM8          ((uint8_t)0x03U)  /* TIM8 Alternate Function mapping  */
-#define GPIO_AF3_TIM9          ((uint8_t)0x03U)  /* TIM9 Alternate Function mapping  */
-#define GPIO_AF3_TIM10         ((uint8_t)0x03U)  /* TIM10 Alternate Function mapping */
-#define GPIO_AF3_TIM11         ((uint8_t)0x03U)  /* TIM11 Alternate Function mapping */
-
-/** 
-  * @brief   AF 4 selection  
-  */ 
-#define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */
-#define GPIO_AF4_I2C3          ((uint8_t)0x04U)  /* I2C3 Alternate Function mapping */
-
-/** 
-  * @brief   AF 5 selection  
-  */ 
-#define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1 Alternate Function mapping        */
-#define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping   */
-#define GPIO_AF5_I2S3ext       ((uint8_t)0x05U)  /* I2S3ext_SD Alternate Function mapping  */
-
-/** 
-  * @brief   AF 6 selection  
-  */ 
-#define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping  */
-#define GPIO_AF6_I2S2ext       ((uint8_t)0x06U)  /* I2S2ext_SD Alternate Function mapping */
-
-/** 
-  * @brief   AF 7 selection  
-  */ 
-#define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping     */
-#define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping     */
-#define GPIO_AF7_USART3        ((uint8_t)0x07U)  /* USART3 Alternate Function mapping     */
-#define GPIO_AF7_I2S3ext       ((uint8_t)0x07U)  /* I2S3ext_SD Alternate Function mapping */
-
-/** 
-  * @brief   AF 8 selection  
-  */ 
-#define GPIO_AF8_UART4         ((uint8_t)0x08U)  /* UART4 Alternate Function mapping  */
-#define GPIO_AF8_UART5         ((uint8_t)0x08U)  /* UART5 Alternate Function mapping  */
-#define GPIO_AF8_USART6        ((uint8_t)0x08U)  /* USART6 Alternate Function mapping */
-
-/** 
-  * @brief   AF 9 selection 
-  */ 
-#define GPIO_AF9_CAN1          ((uint8_t)0x09U)  /* CAN1 Alternate Function mapping  */
-#define GPIO_AF9_CAN2          ((uint8_t)0x09U)  /* CAN2 Alternate Function mapping  */
-#define GPIO_AF9_TIM12         ((uint8_t)0x09U)  /* TIM12 Alternate Function mapping */
-#define GPIO_AF9_TIM13         ((uint8_t)0x09U)  /* TIM13 Alternate Function mapping */
-#define GPIO_AF9_TIM14         ((uint8_t)0x09U)  /* TIM14 Alternate Function mapping */
-
-/** 
-  * @brief   AF 10 selection  
-  */ 
-#define GPIO_AF10_OTG_FS        ((uint8_t)0x0AU)  /* OTG_FS Alternate Function mapping */
-#define GPIO_AF10_OTG_HS        ((uint8_t)0x0AU)  /* OTG_HS Alternate Function mapping */
-
-/** 
-  * @brief   AF 11 selection  
-  */ 
-#define GPIO_AF11_ETH           ((uint8_t)0x0BU)  /* ETHERNET Alternate Function mapping */
-
-/** 
-  * @brief   AF 12 selection  
-  */ 
-#define GPIO_AF12_FSMC          ((uint8_t)0x0CU)  /* FSMC Alternate Function mapping                     */
-#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0CU)  /* OTG HS configured in FS, Alternate Function mapping */
-#define GPIO_AF12_SDIO          ((uint8_t)0x0CU)  /* SDIO Alternate Function mapping                     */
-
-/** 
-  * @brief   AF 13 selection  
-  */ 
-#define GPIO_AF13_DCMI          ((uint8_t)0x0DU)  /* DCMI Alternate Function mapping */
-
-/** 
-  * @brief   AF 15 selection  
-  */ 
-#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */
-#endif /* STM32F407xx || STM32F417xx */
-/*----------------------------------------------------------------------------*/
-
-/*---------------------------------- STM32F405xx/STM32F415xx------------------*/
-#if defined(STM32F405xx) || defined(STM32F415xx)
-/** 
-  * @brief   AF 0 selection  
-  */ 
-#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */
-#define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
-#define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
-#define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */
-
-/** 
-  * @brief   AF 1 selection  
-  */ 
-#define GPIO_AF1_TIM1          ((uint8_t)0x01U)  /* TIM1 Alternate Function mapping */
-#define GPIO_AF1_TIM2          ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */
-
-/** 
-  * @brief   AF 2 selection  
-  */ 
-#define GPIO_AF2_TIM3          ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4          ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM5          ((uint8_t)0x02U)  /* TIM5 Alternate Function mapping */
-
-/** 
-  * @brief   AF 3 selection  
-  */ 
-#define GPIO_AF3_TIM8          ((uint8_t)0x03U)  /* TIM8 Alternate Function mapping  */
-#define GPIO_AF3_TIM9          ((uint8_t)0x03U)  /* TIM9 Alternate Function mapping  */
-#define GPIO_AF3_TIM10         ((uint8_t)0x03U)  /* TIM10 Alternate Function mapping */
-#define GPIO_AF3_TIM11         ((uint8_t)0x03U)  /* TIM11 Alternate Function mapping */
-
-/** 
-  * @brief   AF 4 selection  
-  */ 
-#define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */
-#define GPIO_AF4_I2C3          ((uint8_t)0x04U)  /* I2C3 Alternate Function mapping */
-
-/** 
-  * @brief   AF 5 selection  
-  */ 
-#define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1 Alternate Function mapping        */
-#define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping   */
-#define GPIO_AF5_I2S3ext       ((uint8_t)0x05U)  /* I2S3ext_SD Alternate Function mapping  */
-
-/** 
-  * @brief   AF 6 selection  
-  */ 
-#define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping  */
-#define GPIO_AF6_I2S2ext       ((uint8_t)0x06U)  /* I2S2ext_SD Alternate Function mapping */
-
-/** 
-  * @brief   AF 7 selection  
-  */ 
-#define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping     */
-#define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping     */
-#define GPIO_AF7_USART3        ((uint8_t)0x07U)  /* USART3 Alternate Function mapping     */
-#define GPIO_AF7_I2S3ext       ((uint8_t)0x07U)  /* I2S3ext_SD Alternate Function mapping */
-
-/** 
-  * @brief   AF 8 selection  
-  */ 
-#define GPIO_AF8_UART4         ((uint8_t)0x08U)  /* UART4 Alternate Function mapping  */
-#define GPIO_AF8_UART5         ((uint8_t)0x08U)  /* UART5 Alternate Function mapping  */
-#define GPIO_AF8_USART6        ((uint8_t)0x08U)  /* USART6 Alternate Function mapping */
-
-/** 
-  * @brief   AF 9 selection 
-  */ 
-#define GPIO_AF9_CAN1          ((uint8_t)0x09U)  /* CAN1 Alternate Function mapping  */
-#define GPIO_AF9_CAN2          ((uint8_t)0x09U)  /* CAN2 Alternate Function mapping  */
-#define GPIO_AF9_TIM12         ((uint8_t)0x09U)  /* TIM12 Alternate Function mapping */
-#define GPIO_AF9_TIM13         ((uint8_t)0x09U)  /* TIM13 Alternate Function mapping */
-#define GPIO_AF9_TIM14         ((uint8_t)0x09U)  /* TIM14 Alternate Function mapping */
-
-/** 
-  * @brief   AF 10 selection  
-  */ 
-#define GPIO_AF10_OTG_FS        ((uint8_t)0x0AU)  /* OTG_FS Alternate Function mapping */
-#define GPIO_AF10_OTG_HS        ((uint8_t)0x0AU)  /* OTG_HS Alternate Function mapping */
-
-/** 
-  * @brief   AF 12 selection  
-  */ 
-#define GPIO_AF12_FSMC          ((uint8_t)0x0CU)  /* FSMC Alternate Function mapping                     */
-#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0CU)  /* OTG HS configured in FS, Alternate Function mapping */
-#define GPIO_AF12_SDIO          ((uint8_t)0x0CU)  /* SDIO Alternate Function mapping                     */
-
-/** 
-  * @brief   AF 15 selection  
-  */ 
-#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */
-#endif /* STM32F405xx || STM32F415xx */
-
-/*----------------------------------------------------------------------------*/
-
-/*---------------------------------------- STM32F401xx------------------------*/
-#if defined(STM32F401xC) || defined(STM32F401xE) 
-/** 
-  * @brief   AF 0 selection  
-  */ 
-#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */
-#define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
-#define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
-#define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */
-
-/** 
-  * @brief   AF 1 selection  
-  */ 
-#define GPIO_AF1_TIM1          ((uint8_t)0x01U)  /* TIM1 Alternate Function mapping */
-#define GPIO_AF1_TIM2          ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */
-
-/** 
-  * @brief   AF 2 selection  
-  */ 
-#define GPIO_AF2_TIM3          ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4          ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM5          ((uint8_t)0x02U)  /* TIM5 Alternate Function mapping */
-
-/** 
-  * @brief   AF 3 selection  
-  */ 
-#define GPIO_AF3_TIM9          ((uint8_t)0x03U)  /* TIM9 Alternate Function mapping  */
-#define GPIO_AF3_TIM10         ((uint8_t)0x03U)  /* TIM10 Alternate Function mapping */
-#define GPIO_AF3_TIM11         ((uint8_t)0x03U)  /* TIM11 Alternate Function mapping */
-
-/** 
-  * @brief   AF 4 selection  
-  */ 
-#define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */
-#define GPIO_AF4_I2C3          ((uint8_t)0x04U)  /* I2C3 Alternate Function mapping */
-
-/** 
-  * @brief   AF 5 selection  
-  */ 
-#define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1 Alternate Function mapping        */
-#define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping   */
-#define GPIO_AF5_SPI4          ((uint8_t)0x05U)  /* SPI4 Alternate Function mapping        */
-#define GPIO_AF5_I2S3ext       ((uint8_t)0x05U)  /* I2S3ext_SD Alternate Function mapping   */
-
-/** 
-  * @brief   AF 6 selection  
-  */ 
-#define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping  */
-#define GPIO_AF6_I2S2ext       ((uint8_t)0x06U)  /* I2S2ext_SD Alternate Function mapping */
-
-/** 
-  * @brief   AF 7 selection  
-  */ 
-#define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping     */
-#define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping     */
-#define GPIO_AF7_I2S3ext       ((uint8_t)0x07U)  /* I2S3ext_SD Alternate Function mapping */
-
-/** 
-  * @brief   AF 8 selection  
-  */ 
-#define GPIO_AF8_USART6        ((uint8_t)0x08U)  /* USART6 Alternate Function mapping */
-
-/** 
-  * @brief   AF 9 selection 
-  */ 
-#define GPIO_AF9_TIM14         ((uint8_t)0x09U)  /* TIM14 Alternate Function mapping */
-#define GPIO_AF9_I2C2          ((uint8_t)0x09U)  /* I2C2 Alternate Function mapping  */
-#define GPIO_AF9_I2C3          ((uint8_t)0x09U)  /* I2C3 Alternate Function mapping  */
-
-
-/** 
-  * @brief   AF 10 selection  
-  */ 
-#define GPIO_AF10_OTG_FS        ((uint8_t)0x0AU)  /* OTG_FS Alternate Function mapping */
-
-/** 
-  * @brief   AF 12 selection  
-  */ 
-#define GPIO_AF12_SDIO          ((uint8_t)0x0CU)  /* SDIO Alternate Function mapping  */
-
-/** 
-  * @brief   AF 15 selection  
-  */ 
-#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */
-#endif /* STM32F401xC || STM32F401xE */
-/*----------------------------------------------------------------------------*/
-
-/*--------------- STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx-------------*/
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)   
-/** 
-  * @brief   AF 0 selection  
-  */ 
-#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */
-#define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
-#define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
-#define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */
-
-/** 
-  * @brief   AF 1 selection  
-  */ 
-#define GPIO_AF1_TIM1          ((uint8_t)0x01U)  /* TIM1 Alternate Function mapping */
-#define GPIO_AF1_TIM2          ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */
-
-/** 
-  * @brief   AF 2 selection  
-  */ 
-#define GPIO_AF2_TIM3          ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4          ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM5          ((uint8_t)0x02U)  /* TIM5 Alternate Function mapping */
-
-/** 
-  * @brief   AF 3 selection  
-  */ 
-#define GPIO_AF3_TIM8          ((uint8_t)0x03U)  /* TIM8 Alternate Function mapping  */
-#define GPIO_AF3_TIM9          ((uint8_t)0x03U)  /* TIM9 Alternate Function mapping  */
-#define GPIO_AF3_TIM10         ((uint8_t)0x03U)  /* TIM10 Alternate Function mapping */
-#define GPIO_AF3_TIM11         ((uint8_t)0x03U)  /* TIM11 Alternate Function mapping */
-
-/** 
-  * @brief   AF 4 selection  
-  */ 
-#define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping    */
-#define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping    */
-#define GPIO_AF4_I2C3          ((uint8_t)0x04U)  /* I2C3 Alternate Function mapping    */
-#define GPIO_AF4_FMPI2C1       ((uint8_t)0x04U)  /* FMPI2C1 Alternate Function mapping */
-
-/** 
-  * @brief   AF 5 selection  
-  */ 
-#define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1/I2S1 Alternate Function mapping   */
-#define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping   */
-#define GPIO_AF5_SPI3          ((uint8_t)0x05U)  /* SPI3/I2S3 Alternate Function mapping   */
-#define GPIO_AF5_SPI4          ((uint8_t)0x05U)  /* SPI4/I2S4 Alternate Function mapping   */
-#define GPIO_AF5_I2S3ext       ((uint8_t)0x05U)  /* I2S3ext_SD Alternate Function mapping  */
-
-/** 
-  * @brief   AF 6 selection  
-  */
-#define GPIO_AF6_SPI2          ((uint8_t)0x06U)  /* I2S2 Alternate Function mapping       */
-#define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping  */
-#define GPIO_AF6_SPI4          ((uint8_t)0x06U)  /* SPI4/I2S4 Alternate Function mapping  */
-#define GPIO_AF6_SPI5          ((uint8_t)0x06U)  /* SPI5/I2S5 Alternate Function mapping  */
-#define GPIO_AF6_I2S2ext       ((uint8_t)0x06U)  /* I2S2ext_SD Alternate Function mapping */
-#define GPIO_AF6_DFSDM1        ((uint8_t)0x06U)  /* DFSDM1 Alternate Function mapping     */
-/** 
-  * @brief   AF 7 selection  
-  */ 
-#define GPIO_AF7_SPI3          ((uint8_t)0x07U)  /* SPI3/I2S3 Alternate Function mapping  */
-#define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping     */
-#define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping     */
-#define GPIO_AF7_USART3        ((uint8_t)0x07U)  /* USART3 Alternate Function mapping     */
-#define GPIO_AF7_I2S3ext       ((uint8_t)0x07U)  /* I2S3ext_SD Alternate Function mapping */
-
-/** 
-  * @brief   AF 8 selection  
-  */ 
-#define GPIO_AF8_USART6        ((uint8_t)0x08U)  /* USART6 Alternate Function mapping */
-#define GPIO_AF8_USART3        ((uint8_t)0x08U)  /* USART3 Alternate Function mapping */
-#define GPIO_AF8_DFSDM1        ((uint8_t)0x08U)  /* DFSDM1 Alternate Function mapping */
-#define GPIO_AF8_CAN1          ((uint8_t)0x08U)  /* CAN1 Alternate Function mapping   */
-
-/** 
-  * @brief   AF 9 selection 
-  */ 
-#define GPIO_AF9_TIM13         ((uint8_t)0x09U)  /* TIM13 Alternate Function mapping   */
-#define GPIO_AF9_TIM14         ((uint8_t)0x09U)  /* TIM14 Alternate Function mapping   */
-#define GPIO_AF9_I2C2          ((uint8_t)0x09U)  /* I2C2 Alternate Function mapping    */
-#define GPIO_AF9_I2C3          ((uint8_t)0x09U)  /* I2C3 Alternate Function mapping    */
-#define GPIO_AF9_FMPI2C1       ((uint8_t)0x09U)  /* FMPI2C1 Alternate Function mapping */
-#define GPIO_AF9_CAN1          ((uint8_t)0x09U)  /* CAN1 Alternate Function mapping    */
-#define GPIO_AF9_CAN2          ((uint8_t)0x09U)  /* CAN1 Alternate Function mapping    */  
-#define GPIO_AF9_QSPI          ((uint8_t)0x09U)  /* QSPI Alternate Function mapping    */
-
-/** 
-  * @brief   AF 10 selection  
-  */ 
-#define GPIO_AF10_OTG_FS        ((uint8_t)0x0AU)  /* OTG_FS Alternate Function mapping */
-#define GPIO_AF10_DFSDM1        ((uint8_t)0x0AU)  /* DFSDM1 Alternate Function mapping */
-#define GPIO_AF10_QSPI          ((uint8_t)0x0AU)  /* QSPI Alternate Function mapping   */
-#define GPIO_AF10_FMC           ((uint8_t)0x0AU)  /* FMC Alternate Function mapping    */
-
-/** 
-  * @brief   AF 12 selection  
-  */ 
-#define GPIO_AF12_SDIO          ((uint8_t)0x0CU)  /* SDIO Alternate Function mapping  */
-#define GPIO_AF12_FSMC          ((uint8_t)0x0CU)  /* FMC Alternate Function mapping   */
-
-/** 
-  * @brief   AF 15 selection  
-  */ 
-#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-/*---------------------------------------- STM32F411xx------------------------*/
-#if defined(STM32F411xE) 
-/** 
-  * @brief   AF 0 selection  
-  */ 
-#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */
-#define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
-#define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
-#define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */
-
-/** 
-  * @brief   AF 1 selection  
-  */ 
-#define GPIO_AF1_TIM1          ((uint8_t)0x01U)  /* TIM1 Alternate Function mapping */
-#define GPIO_AF1_TIM2          ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */
-
-/** 
-  * @brief   AF 2 selection  
-  */ 
-#define GPIO_AF2_TIM3          ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4          ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM5          ((uint8_t)0x02U)  /* TIM5 Alternate Function mapping */
-
-/** 
-  * @brief   AF 3 selection  
-  */ 
-#define GPIO_AF3_TIM9          ((uint8_t)0x03U)  /* TIM9 Alternate Function mapping  */
-#define GPIO_AF3_TIM10         ((uint8_t)0x03U)  /* TIM10 Alternate Function mapping */
-#define GPIO_AF3_TIM11         ((uint8_t)0x03U)  /* TIM11 Alternate Function mapping */
-
-/** 
-  * @brief   AF 4 selection  
-  */ 
-#define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */
-#define GPIO_AF4_I2C3          ((uint8_t)0x04U)  /* I2C3 Alternate Function mapping */
-
-/** 
-  * @brief   AF 5 selection  
-  */ 
-#define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1/I2S1 Alternate Function mapping   */
-#define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping   */
-#define GPIO_AF5_SPI3          ((uint8_t)0x05U)  /* SPI3/I2S3 Alternate Function mapping   */
-#define GPIO_AF5_SPI4          ((uint8_t)0x05U)  /* SPI4 Alternate Function mapping        */
-#define GPIO_AF5_I2S3ext       ((uint8_t)0x05U)  /* I2S3ext_SD Alternate Function mapping  */
-
-/** 
-  * @brief   AF 6 selection  
-  */
-#define GPIO_AF6_SPI2          ((uint8_t)0x06U)  /* I2S2 Alternate Function mapping       */
-#define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping  */
-#define GPIO_AF6_SPI4          ((uint8_t)0x06U)  /* SPI4/I2S4 Alternate Function mapping  */
-#define GPIO_AF6_SPI5          ((uint8_t)0x06U)  /* SPI5/I2S5 Alternate Function mapping  */
-#define GPIO_AF6_I2S2ext       ((uint8_t)0x06U)  /* I2S2ext_SD Alternate Function mapping */
-
-/** 
-  * @brief   AF 7 selection  
-  */ 
-#define GPIO_AF7_SPI3          ((uint8_t)0x07U)  /* SPI3/I2S3 Alternate Function mapping  */
-#define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping     */
-#define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping     */
-#define GPIO_AF7_I2S3ext       ((uint8_t)0x07U)  /* I2S3ext_SD Alternate Function mapping */
-
-/** 
-  * @brief   AF 8 selection  
-  */ 
-#define GPIO_AF8_USART6        ((uint8_t)0x08U)  /* USART6 Alternate Function mapping */
-
-/** 
-  * @brief   AF 9 selection 
-  */ 
-#define GPIO_AF9_TIM14         ((uint8_t)0x09U)  /* TIM14 Alternate Function mapping */
-#define GPIO_AF9_I2C2          ((uint8_t)0x09U)  /* I2C2 Alternate Function mapping  */
-#define GPIO_AF9_I2C3          ((uint8_t)0x09U)  /* I2C3 Alternate Function mapping  */
-
-/** 
-  * @brief   AF 10 selection  
-  */ 
-#define GPIO_AF10_OTG_FS        ((uint8_t)0x0AU)  /* OTG_FS Alternate Function mapping */
-
-/** 
-  * @brief   AF 12 selection  
-  */ 
-#define GPIO_AF12_SDIO          ((uint8_t)0x0CU)  /* SDIO Alternate Function mapping  */
-
-/** 
-  * @brief   AF 15 selection  
-  */ 
-#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */
-#endif /* STM32F411xE */
-
-/*---------------------------------------- STM32F410xx------------------------*/
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-/** 
-  * @brief   AF 0 selection  
-  */ 
-#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */
-#define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
-#define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
-#define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */
-
-/** 
-  * @brief   AF 1 selection  
-  */ 
-#define GPIO_AF1_TIM1          ((uint8_t)0x01U)  /* TIM1 Alternate Function mapping */
-#define GPIO_AF1_LPTIM1        ((uint8_t)0x01U)  /* LPTIM1 Alternate Function mapping */
-
-/** 
-  * @brief   AF 2 selection  
-  */ 
-#define GPIO_AF2_TIM5          ((uint8_t)0x02U)  /* TIM5 Alternate Function mapping */
-
-/** 
-  * @brief   AF 3 selection  
-  */ 
-#define GPIO_AF3_TIM9          ((uint8_t)0x03U)  /* TIM9 Alternate Function mapping  */
-#define GPIO_AF3_TIM11         ((uint8_t)0x03U)  /* TIM11 Alternate Function mapping */
-
-/** 
-  * @brief   AF 4 selection  
-  */ 
-#define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */
-#define GPIO_AF4_FMPI2C1       ((uint8_t)0x04U)  /* FMPI2C1 Alternate Function mapping */
-
-/** 
-  * @brief   AF 5 selection  
-  */ 
-#define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1/I2S1 Alternate Function mapping   */
-#if defined(STM32F410Cx) || defined(STM32F410Rx)  
-#define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping   */
-#endif /* STM32F410Cx || STM32F410Rx */   
-
-/** 
-  * @brief   AF 6 selection  
-  */
-#define GPIO_AF6_SPI1          ((uint8_t)0x06U)  /* SPI1 Alternate Function mapping  */
-#if defined(STM32F410Cx) || defined(STM32F410Rx)   
-#define GPIO_AF6_SPI2          ((uint8_t)0x06U)  /* I2S2 Alternate Function mapping       */
-#endif /* STM32F410Cx || STM32F410Rx */   
-#define GPIO_AF6_SPI5          ((uint8_t)0x06U)  /* SPI5/I2S5 Alternate Function mapping  */
-/** 
-  * @brief   AF 7 selection  
-  */ 
-#define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping     */
-#define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping     */
-
-/** 
-  * @brief   AF 8 selection  
-  */ 
-#define GPIO_AF8_USART6        ((uint8_t)0x08U)  /* USART6 Alternate Function mapping */
-
-/** 
-  * @brief   AF 9 selection 
-  */ 
-#define GPIO_AF9_I2C2          ((uint8_t)0x09U)  /* I2C2 Alternate Function mapping  */
-#define GPIO_AF9_FMPI2C1       ((uint8_t)0x09U)  /* FMPI2C1 Alternate Function mapping */
-
-/** 
-  * @brief   AF 15 selection  
-  */ 
-#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-
-/*---------------------------------------- STM32F446xx -----------------------*/
-#if defined(STM32F446xx)
-/**
-  * @brief   AF 0 selection  
-  */ 
-#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */
-#define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
-#define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
-#define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */
-
-/** 
-  * @brief   AF 1 selection  
-  */ 
-#define GPIO_AF1_TIM1          ((uint8_t)0x01U)  /* TIM1 Alternate Function mapping */
-#define GPIO_AF1_TIM2          ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */
-
-/** 
-  * @brief   AF 2 selection  
-  */ 
-#define GPIO_AF2_TIM3          ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4          ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM5          ((uint8_t)0x02U)  /* TIM5 Alternate Function mapping */
-
-/** 
-  * @brief   AF 3 selection  
-  */ 
-#define GPIO_AF3_TIM8          ((uint8_t)0x03U)  /* TIM8 Alternate Function mapping  */
-#define GPIO_AF3_TIM9          ((uint8_t)0x03U)  /* TIM9 Alternate Function mapping  */
-#define GPIO_AF3_TIM10         ((uint8_t)0x03U)  /* TIM10 Alternate Function mapping */
-#define GPIO_AF3_TIM11         ((uint8_t)0x03U)  /* TIM11 Alternate Function mapping */
-#define GPIO_AF3_CEC           ((uint8_t)0x03U)  /* CEC Alternate Function mapping   */
-
-/** 
-  * @brief   AF 4 selection  
-  */ 
-#define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */
-#define GPIO_AF4_I2C3          ((uint8_t)0x04U)  /* I2C3 Alternate Function mapping */
-#define GPIO_AF4_FMPI2C1       ((uint8_t)0x04U)  /* FMPI2C1 Alternate Function mapping */
-#define GPIO_AF4_CEC           ((uint8_t)0x04U)  /* CEC Alternate Function mapping  */
-
-/** 
-  * @brief   AF 5 selection  
-  */ 
-#define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1/I2S1 Alternate Function mapping   */
-#define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping   */
-#define GPIO_AF5_SPI3          ((uint8_t)0x05U)  /* SPI3/I2S3 Alternate Function mapping   */
-#define GPIO_AF5_SPI4          ((uint8_t)0x05U)  /* SPI4 Alternate Function mapping        */
-
-/** 
-  * @brief   AF 6 selection  
-  */ 
-#define GPIO_AF6_SPI2          ((uint8_t)0x06U)  /* SPI2/I2S2 Alternate Function mapping  */
-#define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping  */
-#define GPIO_AF6_SPI4          ((uint8_t)0x06U)  /* SPI4 Alternate Function mapping       */
-#define GPIO_AF6_SAI1          ((uint8_t)0x06U)  /* SAI1 Alternate Function mapping       */
-
-/** 
-  * @brief   AF 7 selection  
-  */ 
-#define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping     */
-#define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping     */
-#define GPIO_AF7_USART3        ((uint8_t)0x07U)  /* USART3 Alternate Function mapping     */
-#define GPIO_AF7_UART5         ((uint8_t)0x07U)  /* UART5 Alternate Function mapping      */
-#define GPIO_AF7_SPI2          ((uint8_t)0x07U)  /* SPI2/I2S2 Alternate Function mapping  */
-#define GPIO_AF7_SPI3          ((uint8_t)0x07U)  /* SPI3/I2S3 Alternate Function mapping  */
-#define GPIO_AF7_SPDIFRX       ((uint8_t)0x07U)  /* SPDIFRX Alternate Function mapping      */
-
-/** 
-  * @brief   AF 8 selection  
-  */ 
-#define GPIO_AF8_UART4         ((uint8_t)0x08U)  /* UART4 Alternate Function mapping  */
-#define GPIO_AF8_UART5         ((uint8_t)0x08U)  /* UART5 Alternate Function mapping  */
-#define GPIO_AF8_USART6        ((uint8_t)0x08U)  /* USART6 Alternate Function mapping */
-#define GPIO_AF8_SPDIFRX       ((uint8_t)0x08U)  /* SPDIFRX Alternate Function mapping  */
-#define GPIO_AF8_SAI2          ((uint8_t)0x08U)  /* SAI2 Alternate Function mapping   */
-
-/** 
-  * @brief   AF 9 selection 
-  */ 
-#define GPIO_AF9_CAN1          ((uint8_t)0x09U)  /* CAN1 Alternate Function mapping  */
-#define GPIO_AF9_CAN2          ((uint8_t)0x09U)  /* CAN2 Alternate Function mapping  */
-#define GPIO_AF9_TIM12         ((uint8_t)0x09U)  /* TIM12 Alternate Function mapping */
-#define GPIO_AF9_TIM13         ((uint8_t)0x09U)  /* TIM13 Alternate Function mapping */
-#define GPIO_AF9_TIM14         ((uint8_t)0x09U)  /* TIM14 Alternate Function mapping */
-#define GPIO_AF9_QSPI          ((uint8_t)0x09U)  /* QSPI Alternate Function mapping  */
-
-/** 
-  * @brief   AF 10 selection  
-  */ 
-#define GPIO_AF10_OTG_FS        ((uint8_t)0x0AU)  /* OTG_FS Alternate Function mapping */
-#define GPIO_AF10_OTG_HS        ((uint8_t)0x0AU)  /* OTG_HS Alternate Function mapping */
-#define GPIO_AF10_SAI2          ((uint8_t)0x0AU)  /* SAI2 Alternate Function mapping   */
-#define GPIO_AF10_QSPI          ((uint8_t)0x0AU)  /* QSPI Alternate Function mapping  */
-
-/** 
-  * @brief   AF 11 selection  
-  */ 
-#define GPIO_AF11_ETH           ((uint8_t)0x0BU)  /* ETHERNET Alternate Function mapping */
-
-/** 
-  * @brief   AF 12 selection  
-  */ 
-#define GPIO_AF12_FMC           ((uint8_t)0x0CU)  /* FMC Alternate Function mapping                      */
-#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0CU)  /* OTG HS configured in FS, Alternate Function mapping */
-#define GPIO_AF12_SDIO          ((uint8_t)0x0CU)  /* SDIO Alternate Function mapping                     */
-
-/** 
-  * @brief   AF 13 selection  
-  */ 
-#define GPIO_AF13_DCMI          ((uint8_t)0x0DU)  /* DCMI Alternate Function mapping */
-
-/** 
-  * @brief   AF 15 selection  
-  */ 
-#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */
-
-#endif /* STM32F446xx */
-/*----------------------------------------------------------------------------*/
-
-/*-------------------------------- STM32F469xx/STM32F479xx--------------------*/
-#if defined(STM32F469xx) || defined(STM32F479xx)
-/** 
-  * @brief   AF 0 selection  
-  */ 
-#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */
-#define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
-#define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
-#define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */
-
-/** 
-  * @brief   AF 1 selection  
-  */ 
-#define GPIO_AF1_TIM1          ((uint8_t)0x01U)  /* TIM1 Alternate Function mapping */
-#define GPIO_AF1_TIM2          ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */
-
-/** 
-  * @brief   AF 2 selection  
-  */ 
-#define GPIO_AF2_TIM3          ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4          ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM5          ((uint8_t)0x02U)  /* TIM5 Alternate Function mapping */
-
-/** 
-  * @brief   AF 3 selection  
-  */ 
-#define GPIO_AF3_TIM8          ((uint8_t)0x03U)  /* TIM8 Alternate Function mapping  */
-#define GPIO_AF3_TIM9          ((uint8_t)0x03U)  /* TIM9 Alternate Function mapping  */
-#define GPIO_AF3_TIM10         ((uint8_t)0x03U)  /* TIM10 Alternate Function mapping */
-#define GPIO_AF3_TIM11         ((uint8_t)0x03U)  /* TIM11 Alternate Function mapping */
-
-/** 
-  * @brief   AF 4 selection  
-  */ 
-#define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */
-#define GPIO_AF4_I2C3          ((uint8_t)0x04U)  /* I2C3 Alternate Function mapping */
-
-/** 
-  * @brief   AF 5 selection  
-  */ 
-#define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1 Alternate Function mapping        */
-#define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping   */
-#define GPIO_AF5_SPI3          ((uint8_t)0x05U)  /* SPI3/I2S3 Alternate Function mapping   */
-#define GPIO_AF5_SPI4          ((uint8_t)0x05U)  /* SPI4 Alternate Function mapping        */
-#define GPIO_AF5_SPI5          ((uint8_t)0x05U)  /* SPI5 Alternate Function mapping        */
-#define GPIO_AF5_SPI6          ((uint8_t)0x05U)  /* SPI6 Alternate Function mapping        */
-#define GPIO_AF5_I2S3ext       ((uint8_t)0x05U)  /* I2S3ext_SD Alternate Function mapping  */
-
-/** 
-  * @brief   AF 6 selection  
-  */ 
-#define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping  */
-#define GPIO_AF6_I2S2ext       ((uint8_t)0x06U)  /* I2S2ext_SD Alternate Function mapping */
-#define GPIO_AF6_SAI1          ((uint8_t)0x06U)  /* SAI1 Alternate Function mapping       */
-
-/** 
-  * @brief   AF 7 selection  
-  */ 
-#define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping     */
-#define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping     */
-#define GPIO_AF7_USART3        ((uint8_t)0x07U)  /* USART3 Alternate Function mapping     */
-#define GPIO_AF7_I2S3ext       ((uint8_t)0x07U)  /* I2S3ext_SD Alternate Function mapping */
-
-/** 
-  * @brief   AF 8 selection  
-  */ 
-#define GPIO_AF8_UART4         ((uint8_t)0x08U)  /* UART4 Alternate Function mapping  */
-#define GPIO_AF8_UART5         ((uint8_t)0x08U)  /* UART5 Alternate Function mapping  */
-#define GPIO_AF8_USART6        ((uint8_t)0x08U)  /* USART6 Alternate Function mapping */
-#define GPIO_AF8_UART7         ((uint8_t)0x08U)  /* UART7 Alternate Function mapping  */
-#define GPIO_AF8_UART8         ((uint8_t)0x08U)  /* UART8 Alternate Function mapping  */
-
-/** 
-  * @brief   AF 9 selection 
-  */ 
-#define GPIO_AF9_CAN1          ((uint8_t)0x09U)  /* CAN1 Alternate Function mapping    */
-#define GPIO_AF9_CAN2          ((uint8_t)0x09U)  /* CAN2 Alternate Function mapping    */
-#define GPIO_AF9_TIM12         ((uint8_t)0x09U)  /* TIM12 Alternate Function mapping   */
-#define GPIO_AF9_TIM13         ((uint8_t)0x09U)  /* TIM13 Alternate Function mapping   */
-#define GPIO_AF9_TIM14         ((uint8_t)0x09U)  /* TIM14 Alternate Function mapping   */
-#define GPIO_AF9_LTDC          ((uint8_t)0x09U)  /* LCD-TFT Alternate Function mapping */
-#define GPIO_AF9_QSPI          ((uint8_t)0x09U)  /* QSPI Alternate Function mapping    */
-
-/** 
-  * @brief   AF 10 selection  
-  */ 
-#define GPIO_AF10_OTG_FS        ((uint8_t)0x0AU)  /* OTG_FS Alternate Function mapping */
-#define GPIO_AF10_OTG_HS        ((uint8_t)0x0AU)  /* OTG_HS Alternate Function mapping */
-#define GPIO_AF10_QSPI          ((uint8_t)0x0AU)  /* QSPI Alternate Function mapping   */
-
-/** 
-  * @brief   AF 11 selection  
-  */ 
-#define GPIO_AF11_ETH           ((uint8_t)0x0BU)  /* ETHERNET Alternate Function mapping */
-
-/** 
-  * @brief   AF 12 selection  
-  */ 
-#define GPIO_AF12_FMC           ((uint8_t)0x0CU)  /* FMC Alternate Function mapping                      */
-#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0CU)  /* OTG HS configured in FS, Alternate Function mapping */
-#define GPIO_AF12_SDIO          ((uint8_t)0x0CU)  /* SDIO Alternate Function mapping                     */
-
-/** 
-  * @brief   AF 13 selection  
-  */ 
-#define GPIO_AF13_DCMI          ((uint8_t)0x0DU)  /* DCMI Alternate Function mapping */
-#define GPIO_AF13_DSI           ((uint8_t)0x0DU)  /* DSI Alternate Function mapping  */
-
-/** 
-  * @brief   AF 14 selection  
-  */
-#define GPIO_AF14_LTDC          ((uint8_t)0x0EU)  /* LCD-TFT Alternate Function mapping */
-
-/** 
-  * @brief   AF 15 selection  
-  */ 
-#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */
-
-#endif /* STM32F469xx || STM32F479xx */
-/*----------------------------------------------------------------------------*/
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros
-  * @{
-  */
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions
-  * @{
-  */
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup GPIOEx_Private_Constants GPIO Private Constants
-  * @{
-  */
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup GPIOEx_Private_Macros GPIO Private Macros
-  * @{
-  */
-/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index
-  * @{
-  */
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
-#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
-                                               ((__GPIOx__) == (GPIOB))? 1U :\
-                                               ((__GPIOx__) == (GPIOC))? 2U :\
-                                               ((__GPIOx__) == (GPIOD))? 3U :\
-                                               ((__GPIOx__) == (GPIOE))? 4U :\
-                                               ((__GPIOx__) == (GPIOF))? 5U :\
-                                               ((__GPIOx__) == (GPIOG))? 6U :\
-                                               ((__GPIOx__) == (GPIOH))? 7U : 8U)
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx)
-#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
-                                               ((__GPIOx__) == (GPIOB))? 1U :\
-                                               ((__GPIOx__) == (GPIOC))? 2U :\
-                                               ((__GPIOx__) == (GPIOD))? 3U :\
-                                               ((__GPIOx__) == (GPIOE))? 4U :\
-                                               ((__GPIOx__) == (GPIOF))? 5U :\
-                                               ((__GPIOx__) == (GPIOG))? 6U :\
-                                               ((__GPIOx__) == (GPIOH))? 7U :\
-                                               ((__GPIOx__) == (GPIOI))? 8U :\
-                                               ((__GPIOx__) == (GPIOJ))? 9U : 10U)
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 
-#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
-                                               ((__GPIOx__) == (GPIOB))? 1U :\
-                                               ((__GPIOx__) == (GPIOC))? 2U : 7U)
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 
-#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
-                                               ((__GPIOx__) == (GPIOB))? 1U :\
-                                               ((__GPIOx__) == (GPIOC))? 2U :\
-                                               ((__GPIOx__) == (GPIOD))? 3U :\
-                                               ((__GPIOx__) == (GPIOE))? 4U : 7U)
-#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
-
-#if defined(STM32F446xx) || defined(STM32F412Zx) ||defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
-#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
-                                               ((__GPIOx__) == (GPIOB))? 1U :\
-                                               ((__GPIOx__) == (GPIOC))? 2U :\
-                                               ((__GPIOx__) == (GPIOD))? 3U :\
-                                               ((__GPIOx__) == (GPIOE))? 4U :\
-                                               ((__GPIOx__) == (GPIOF))? 5U :\
-                                               ((__GPIOx__) == (GPIOG))? 6U : 7U)
-#endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function
-  * @{
-  */  
-/*------------------------- STM32F429xx/STM32F439xx---------------------------*/
-#if defined(STM32F429xx) || defined(STM32F439xx)
-#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \
-                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
-                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
-                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
-                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
-                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
-                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
-                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \
-                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \
-                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \
-                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
-                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \
-                          ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \
-                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \
-                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \
-                          ((AF) == GPIO_AF11_ETH)       || ((AF) == GPIO_AF12_OTG_HS_FS) || \
-                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF13_DCMI)      || \
-                          ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF5_SPI4)       || \
-                          ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \
-                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)      || \
-                          ((AF) == GPIO_AF12_FMC)       ||  ((AF) == GPIO_AF6_SAI1)      || \
-                          ((AF) == GPIO_AF14_LTDC))
-
-#endif /* STM32F429xx || STM32F439xx */
-/*----------------------------------------------------------------------------*/
-
-/*---------------------------------- STM32F427xx/STM32F437xx------------------*/
-#if defined(STM32F427xx) || defined(STM32F437xx)
-#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \
-                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
-                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
-                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
-                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
-                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
-                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
-                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \
-                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \
-                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \
-                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
-                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \
-                          ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \
-                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \
-                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \
-                          ((AF) == GPIO_AF11_ETH)       || ((AF) == GPIO_AF12_OTG_HS_FS) || \
-                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF13_DCMI)      || \
-                          ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF5_SPI4)       || \
-                          ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \
-                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)      || \
-                          ((AF) == GPIO_AF12_FMC)       ||  ((AF) == GPIO_AF6_SAI1))
-
-#endif /* STM32F427xx || STM32F437xx */
-/*----------------------------------------------------------------------------*/
-
-/*---------------------------------- STM32F407xx/STM32F417xx------------------*/
-#if defined(STM32F407xx) || defined(STM32F417xx)
-#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \
-                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
-                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
-                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
-                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
-                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
-                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
-                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \
-                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \
-                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \
-                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
-                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \
-                          ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \
-                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \
-                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \
-                          ((AF) == GPIO_AF11_ETH)       || ((AF) == GPIO_AF12_OTG_HS_FS) || \
-                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF13_DCMI)      || \
-                          ((AF) == GPIO_AF12_FSMC)      || ((AF) == GPIO_AF15_EVENTOUT))
-
-#endif /* STM32F407xx || STM32F417xx */
-/*----------------------------------------------------------------------------*/
-
-/*---------------------------------- STM32F405xx/STM32F415xx------------------*/
-#if defined(STM32F405xx) || defined(STM32F415xx)
-#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \
-                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
-                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
-                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
-                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
-                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
-                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
-                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \
-                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \
-                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \
-                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
-                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \
-                          ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \
-                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \
-                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \
-                          ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDIO)      || \
-                          ((AF) == GPIO_AF12_FSMC)      || ((AF) == GPIO_AF15_EVENTOUT))
-
-#endif /* STM32F405xx || STM32F415xx */
-
-/*----------------------------------------------------------------------------*/
-
-/*---------------------------------------- STM32F401xx------------------------*/
-#if defined(STM32F401xC) || defined(STM32F401xE) 
-#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \
-                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
-                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
-                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
-                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
-                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF4_I2C1)       || \
-                          ((AF) == GPIO_AF4_I2C2)       || ((AF) == GPIO_AF4_I2C3)       || \
-                          ((AF) == GPIO_AF5_SPI1)       || ((AF) == GPIO_AF5_SPI2)       || \
-                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF5_SPI4)       || \
-                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
-                          ((AF) == GPIO_AF8_USART6)     || ((AF) == GPIO_AF10_OTG_FS)    || \
-                          ((AF) == GPIO_AF9_I2C2)       || ((AF) == GPIO_AF9_I2C3)       || \
-                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF15_EVENTOUT))
-
-#endif /* STM32F401xC || STM32F401xE */
-/*----------------------------------------------------------------------------*/
-/*---------------------------------------- STM32F410xx------------------------*/
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 
-#define IS_GPIO_AF(AF)   (((AF) < 10U) || ((AF) == 15U))
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-
-/*---------------------------------------- STM32F411xx------------------------*/
-#if defined(STM32F411xE) 
-#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \
-                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
-                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
-                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
-                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
-                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF4_I2C1)       || \
-                          ((AF) == GPIO_AF4_I2C2)       || ((AF) == GPIO_AF4_I2C3)       || \
-                          ((AF) == GPIO_AF5_SPI1)       || ((AF) == GPIO_AF5_SPI2)       || \
-                          ((AF) == GPIO_AF5_SPI3)       || ((AF) == GPIO_AF6_SPI4)       || \
-                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF5_SPI4)       || \
-                          ((AF) == GPIO_AF6_SPI5)       || ((AF) == GPIO_AF7_SPI3)       || \
-                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
-                          ((AF) == GPIO_AF8_USART6)     || ((AF) == GPIO_AF10_OTG_FS)    || \
-                          ((AF) == GPIO_AF9_I2C2)       || ((AF) == GPIO_AF9_I2C3)       || \
-                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF15_EVENTOUT))
-
-#endif /* STM32F411xE */
-/*----------------------------------------------------------------------------*/
-
-/*----------------------------------------------- STM32F446xx ----------------*/
-#if defined(STM32F446xx) 
-#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \
-                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
-                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
-                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
-                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
-                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
-                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
-                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \
-                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \
-                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \
-                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
-                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \
-                          ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \
-                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \
-                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \
-                          ((AF) == GPIO_AF11_ETH)       || ((AF) == GPIO_AF12_OTG_HS_FS) || \
-                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF13_DCMI)      || \
-                          ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF5_SPI4)       || \
-                          ((AF) == GPIO_AF12_FMC)       ||  ((AF) == GPIO_AF6_SAI1)      || \
-                          ((AF) == GPIO_AF3_CEC)        ||  ((AF) == GPIO_AF4_CEC)       || \
-                          ((AF) == GPIO_AF5_SPI3)       ||  ((AF) == GPIO_AF6_SPI2)      || \
-                          ((AF) == GPIO_AF6_SPI4)       ||  ((AF) == GPIO_AF7_UART5)     || \
-                          ((AF) == GPIO_AF7_SPI2)       ||  ((AF) == GPIO_AF7_SPI3)      || \
-                          ((AF) == GPIO_AF7_SPDIFRX)    ||  ((AF) == GPIO_AF8_SPDIFRX)   || \
-                          ((AF) == GPIO_AF8_SAI2)       ||  ((AF) == GPIO_AF9_QSPI)      || \
-                          ((AF) == GPIO_AF10_SAI2)      ||  ((AF) == GPIO_AF10_QSPI))
-
-#endif /* STM32F446xx */
-/*----------------------------------------------------------------------------*/
-
-/*------------------------------------------- STM32F469xx/STM32F479xx --------*/
-#if defined(STM32F469xx) || defined(STM32F479xx) 
-#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \
-                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
-                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
-                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
-                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
-                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
-                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
-                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \
-                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \
-                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \
-                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
-                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \
-                          ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \
-                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \
-                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \
-                          ((AF) == GPIO_AF11_ETH)       || ((AF) == GPIO_AF12_OTG_HS_FS) || \
-                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF13_DCMI)      || \
-                          ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF5_SPI4)       || \
-                          ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \
-                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)      || \
-                          ((AF) == GPIO_AF12_FMC)       || ((AF) == GPIO_AF6_SAI1)       || \
-                          ((AF) == GPIO_AF14_LTDC)      || ((AF) == GPIO_AF13_DSI)      || \
-                          ((AF) == GPIO_AF9_QSPI)       || ((AF) == GPIO_AF10_QSPI))
-
-#endif /* STM32F469xx || STM32F479xx */
-/*----------------------------------------------------------------------------*/
-
-/*------------------STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx-----------*/
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
-#define IS_GPIO_AF(AF)   (((AF) < 16U) && ((AF) != 11U) && ((AF) != 14U) && ((AF) != 13U))
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-/*----------------------------------------------------------------------------*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup GPIOEx_Private_Functions GPIO Private Functions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_GPIO_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_i2c.h b/stmhal/hal/f4/inc/stm32f4xx_hal_i2c.h
deleted file mode 100644
index 81e97558d0..0000000000
--- a/stmhal/hal/f4/inc/stm32f4xx_hal_i2c.h
+++ /dev/null
@@ -1,651 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_i2c.h
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   Header file of I2C HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_I2C_H
-#define __STM32F4xx_HAL_I2C_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup I2C
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup I2C_Exported_Types I2C Exported Types
-  * @{
-  */
-   
-/**
-  * @brief  I2C Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t ClockSpeed;       /*!< Specifies the clock frequency.
-                                  This parameter must be set to a value lower than 400kHz */
-
-  uint32_t DutyCycle;        /*!< Specifies the I2C fast mode duty cycle.
-                                  This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
-
-  uint32_t OwnAddress1;      /*!< Specifies the first device own address.
-                                  This parameter can be a 7-bit or 10-bit address. */
-
-  uint32_t AddressingMode;   /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
-                                  This parameter can be a value of @ref I2C_addressing_mode */
-
-  uint32_t DualAddressMode;  /*!< Specifies if dual addressing mode is selected.
-                                  This parameter can be a value of @ref I2C_dual_addressing_mode */
-
-  uint32_t OwnAddress2;      /*!< Specifies the second device own address if dual addressing mode is selected
-                                  This parameter can be a 7-bit address. */
-
-  uint32_t GeneralCallMode;  /*!< Specifies if general call mode is selected.
-                                  This parameter can be a value of @ref I2C_general_call_addressing_mode */
-
-  uint32_t NoStretchMode;    /*!< Specifies if nostretch mode is selected.
-                                  This parameter can be a value of @ref I2C_nostretch_mode */
-
-}I2C_InitTypeDef;
-
-/**
-  * @brief  HAL State structure definition
-  * @note  HAL I2C State value coding follow below described bitmap :
-  *          b7-b6  Error information 
-  *             00 : No Error
-  *             01 : Abort (Abort user request on going)
-  *             10 : Timeout
-  *             11 : Error
-  *          b5     IP initilisation status
-  *             0  : Reset (IP not initialized)
-  *             1  : Init done (IP initialized and ready to use. HAL I2C Init function called)
-  *          b4     (not used)
-  *             x  : Should be set to 0
-  *          b3
-  *             0  : Ready or Busy (No Listen mode ongoing)
-  *             1  : Listen (IP in Address Listen Mode)
-  *          b2     Intrinsic process state
-  *             0  : Ready
-  *             1  : Busy (IP busy with some configuration or internal operations)
-  *          b1     Rx state
-  *             0  : Ready (no Rx operation ongoing)
-  *             1  : Busy (Rx operation ongoing)
-  *          b0     Tx state
-  *             0  : Ready (no Tx operation ongoing)
-  *             1  : Busy (Tx operation ongoing)
-  */
-typedef enum
-{
-  HAL_I2C_STATE_RESET             = 0x00U,   /*!< Peripheral is not yet Initialized         */
-  HAL_I2C_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use  */
-  HAL_I2C_STATE_BUSY              = 0x24U,   /*!< An internal process is ongoing            */
-  HAL_I2C_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing      */
-  HAL_I2C_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing         */
-  HAL_I2C_STATE_LISTEN            = 0x28U,   /*!< Address Listen Mode is ongoing            */
-  HAL_I2C_STATE_BUSY_TX_LISTEN    = 0x29U,   /*!< Address Listen Mode and Data Transmission
-                                                 process is ongoing                         */
-  HAL_I2C_STATE_BUSY_RX_LISTEN    = 0x2AU,   /*!< Address Listen Mode and Data Reception
-                                                 process is ongoing                         */
-  HAL_I2C_STATE_ABORT             = 0x60U,   /*!< Abort user request ongoing                */
-  HAL_I2C_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state                             */
-  HAL_I2C_STATE_ERROR             = 0xE0U    /*!< Error                                     */
-
-}HAL_I2C_StateTypeDef;
-
-/**
-  * @brief  HAL Mode structure definition
-  * @note  HAL I2C Mode value coding follow below described bitmap :
-  *          b7     (not used)
-  *             x  : Should be set to 0
-  *          b6
-  *             0  : None
-  *             1  : Memory (HAL I2C communication is in Memory Mode)
-  *          b5
-  *             0  : None
-  *             1  : Slave (HAL I2C communication is in Slave Mode)
-  *          b4
-  *             0  : None
-  *             1  : Master (HAL I2C communication is in Master Mode)
-  *          b3-b2-b1-b0  (not used)
-  *             xxxx : Should be set to 0000
-  */
-typedef enum
-{
-  HAL_I2C_MODE_NONE               = 0x00U,   /*!< No I2C communication on going             */
-  HAL_I2C_MODE_MASTER             = 0x10U,   /*!< I2C communication is in Master Mode       */
-  HAL_I2C_MODE_SLAVE              = 0x20U,   /*!< I2C communication is in Slave Mode        */
-  HAL_I2C_MODE_MEM                = 0x40U    /*!< I2C communication is in Memory Mode       */
-
-}HAL_I2C_ModeTypeDef;
-
-/**
-  * @brief  I2C handle Structure definition
-  */
-typedef struct
-{
-  I2C_TypeDef                *Instance;      /*!< I2C registers base address               */
-                                             
-  I2C_InitTypeDef            Init;           /*!< I2C communication parameters             */
-                                             
-  uint8_t                    *pBuffPtr;      /*!< Pointer to I2C transfer buffer           */
-                                             
-  uint16_t                   XferSize;       /*!< I2C transfer size                        */
-                                             
-  __IO uint16_t              XferCount;      /*!< I2C transfer counter                     */
-                                             
-  __IO uint32_t              XferOptions;    /*!< I2C transfer options                     */
-                                             
-  __IO uint32_t              PreviousState;  /*!< I2C communication Previous state and mode
-                                                  context for internal usage               */
-                                             
-  DMA_HandleTypeDef          *hdmatx;        /*!< I2C Tx DMA handle parameters             */
-                                             
-  DMA_HandleTypeDef          *hdmarx;        /*!< I2C Rx DMA handle parameters             */
-                                             
-  HAL_LockTypeDef            Lock;           /*!< I2C locking object                       */
-                                             
-  __IO HAL_I2C_StateTypeDef  State;          /*!< I2C communication state                  */
-                                             
-  __IO HAL_I2C_ModeTypeDef   Mode;           /*!< I2C communication mode                   */
-                                             
-  __IO uint32_t              ErrorCode;      /*!< I2C Error code                           */
-
-  __IO uint32_t              Devaddress;     /*!< I2C Target device address                */
-
-  __IO uint32_t              Memaddress;     /*!< I2C Target memory address                */
-
-  __IO uint32_t              MemaddSize;     /*!< I2C Target memory address  size          */
-
-  __IO uint32_t              EventCount;     /*!< I2C Event counter                        */
-	
-}I2C_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup I2C_Exported_Constants I2C Exported Constants
-  * @{
-  */
-
-/** @defgroup I2C_Error_Code I2C Error Code
-  * @brief    I2C Error Code 
-  * @{
-  */ 
-#define HAL_I2C_ERROR_NONE       ((uint32_t)0x00000000U)    /*!< No error           */
-#define HAL_I2C_ERROR_BERR       ((uint32_t)0x00000001U)    /*!< BERR error         */
-#define HAL_I2C_ERROR_ARLO       ((uint32_t)0x00000002U)    /*!< ARLO error         */
-#define HAL_I2C_ERROR_AF         ((uint32_t)0x00000004U)    /*!< AF error           */
-#define HAL_I2C_ERROR_OVR        ((uint32_t)0x00000008U)    /*!< OVR error          */
-#define HAL_I2C_ERROR_DMA        ((uint32_t)0x00000010U)    /*!< DMA transfer error */
-#define HAL_I2C_ERROR_TIMEOUT    ((uint32_t)0x00000020U)    /*!< Timeout Error      */
-/**
-  * @}
-  */
-
-/** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode
-  * @{
-  */
-#define I2C_DUTYCYCLE_2                 ((uint32_t)0x00000000U)
-#define I2C_DUTYCYCLE_16_9              I2C_CCR_DUTY
-/**
-  * @}
-  */
-
-/** @defgroup I2C_addressing_mode I2C addressing mode
-  * @{
-  */
-#define I2C_ADDRESSINGMODE_7BIT         ((uint32_t)0x00004000U)
-#define I2C_ADDRESSINGMODE_10BIT        (I2C_OAR1_ADDMODE | ((uint32_t)0x00004000U))
-/**
-  * @}
-  */
-
-/** @defgroup I2C_dual_addressing_mode  I2C dual addressing mode
-  * @{
-  */
-#define I2C_DUALADDRESS_DISABLE        ((uint32_t)0x00000000U)
-#define I2C_DUALADDRESS_ENABLE         I2C_OAR2_ENDUAL
-/**
-  * @}
-  */
-
-/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
-  * @{
-  */
-#define I2C_GENERALCALL_DISABLE        ((uint32_t)0x00000000U)
-#define I2C_GENERALCALL_ENABLE         I2C_CR1_ENGC
-/**
-  * @}
-  */
-
-/** @defgroup I2C_nostretch_mode I2C nostretch mode
-  * @{
-  */
-#define I2C_NOSTRETCH_DISABLE          ((uint32_t)0x00000000U)
-#define I2C_NOSTRETCH_ENABLE           I2C_CR1_NOSTRETCH
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
-  * @{
-  */
-#define I2C_MEMADD_SIZE_8BIT            ((uint32_t)0x00000001U)
-#define I2C_MEMADD_SIZE_16BIT           ((uint32_t)0x00000010U)
-/**
-  * @}
-  */
-
-/** @defgroup I2C_XferDirection_definition I2C XferDirection definition
-  * @{
-  */
-#define I2C_DIRECTION_RECEIVE           ((uint32_t)0x00000000U) 
-#define I2C_DIRECTION_TRANSMIT          ((uint32_t)0x00000001U)
-/**
-  * @}
-  */
-
-/** @defgroup I2C_XferOptions_definition I2C XferOptions definition
-  * @{
-  */
-#define  I2C_FIRST_FRAME                ((uint32_t)0x00000001U)
-#define  I2C_NEXT_FRAME                 ((uint32_t)0x00000002U)
-#define  I2C_FIRST_AND_LAST_FRAME       ((uint32_t)0x00000004U)
-#define  I2C_LAST_FRAME                 ((uint32_t)0x00000008U)
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
-  * @{
-  */
-#define I2C_IT_BUF                      I2C_CR2_ITBUFEN
-#define I2C_IT_EVT                      I2C_CR2_ITEVTEN
-#define I2C_IT_ERR                      I2C_CR2_ITERREN
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Flag_definition I2C Flag definition
-  * @{
-  */
-#define I2C_FLAG_SMBALERT               ((uint32_t)0x00018000U)
-#define I2C_FLAG_TIMEOUT                ((uint32_t)0x00014000U)
-#define I2C_FLAG_PECERR                 ((uint32_t)0x00011000U)
-#define I2C_FLAG_OVR                    ((uint32_t)0x00010800U)
-#define I2C_FLAG_AF                     ((uint32_t)0x00010400U)
-#define I2C_FLAG_ARLO                   ((uint32_t)0x00010200U)
-#define I2C_FLAG_BERR                   ((uint32_t)0x00010100U)
-#define I2C_FLAG_TXE                    ((uint32_t)0x00010080U)
-#define I2C_FLAG_RXNE                   ((uint32_t)0x00010040U)
-#define I2C_FLAG_STOPF                  ((uint32_t)0x00010010U)
-#define I2C_FLAG_ADD10                  ((uint32_t)0x00010008U)
-#define I2C_FLAG_BTF                    ((uint32_t)0x00010004U)
-#define I2C_FLAG_ADDR                   ((uint32_t)0x00010002U)
-#define I2C_FLAG_SB                     ((uint32_t)0x00010001U)
-#define I2C_FLAG_DUALF                  ((uint32_t)0x00100080U)
-#define I2C_FLAG_SMBHOST                ((uint32_t)0x00100040U)
-#define I2C_FLAG_SMBDEFAULT             ((uint32_t)0x00100020U)
-#define I2C_FLAG_GENCALL                ((uint32_t)0x00100010U)
-#define I2C_FLAG_TRA                    ((uint32_t)0x00100004U)
-#define I2C_FLAG_BUSY                   ((uint32_t)0x00100002U)
-#define I2C_FLAG_MSL                    ((uint32_t)0x00100001U)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup I2C_Exported_Macros I2C Exported Macros
-  * @{
-  */
-
-/** @brief Reset I2C handle state
-  * @param  __HANDLE__: specifies the I2C Handle.
-  *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
-  * @retval None
-  */
-#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
-
-/** @brief  Enable or disable the specified I2C interrupts.
-  * @param  __HANDLE__: specifies the I2C Handle.
-  *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
-  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
-  *         This parameter can be one of the following values:
-  *            @arg I2C_IT_BUF: Buffer interrupt enable
-  *            @arg I2C_IT_EVT: Event interrupt enable
-  *            @arg I2C_IT_ERR: Error interrupt enable
-  * @retval None
-  */
-#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
-#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
-
-/** @brief  Checks if the specified I2C interrupt source is enabled or disabled.
-  * @param  __HANDLE__: specifies the I2C Handle.
-  *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
-  * @param  __INTERRUPT__: specifies the I2C interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg I2C_IT_BUF: Buffer interrupt enable
-  *            @arg I2C_IT_EVT: Event interrupt enable
-  *            @arg I2C_IT_ERR: Error interrupt enable
-  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
-  */
-#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief  Checks whether the specified I2C flag is set or not.
-  * @param  __HANDLE__: specifies the I2C Handle.
-  *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
-  * @param  __FLAG__: specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg I2C_FLAG_SMBALERT: SMBus Alert flag
-  *            @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
-  *            @arg I2C_FLAG_PECERR: PEC error in reception flag
-  *            @arg I2C_FLAG_OVR: Overrun/Underrun flag
-  *            @arg I2C_FLAG_AF: Acknowledge failure flag
-  *            @arg I2C_FLAG_ARLO: Arbitration lost flag
-  *            @arg I2C_FLAG_BERR: Bus error flag
-  *            @arg I2C_FLAG_TXE: Data register empty flag
-  *            @arg I2C_FLAG_RXNE: Data register not empty flag
-  *            @arg I2C_FLAG_STOPF: Stop detection flag
-  *            @arg I2C_FLAG_ADD10: 10-bit header sent flag
-  *            @arg I2C_FLAG_BTF: Byte transfer finished flag
-  *            @arg I2C_FLAG_ADDR: Address sent flag
-  *                                Address matched flag
-  *            @arg I2C_FLAG_SB: Start bit flag
-  *            @arg I2C_FLAG_DUALF: Dual flag
-  *            @arg I2C_FLAG_SMBHOST: SMBus host header
-  *            @arg I2C_FLAG_SMBDEFAULT: SMBus default header
-  *            @arg I2C_FLAG_GENCALL: General call header flag
-  *            @arg I2C_FLAG_TRA: Transmitter/Receiver flag
-  *            @arg I2C_FLAG_BUSY: Bus busy flag
-  *            @arg I2C_FLAG_MSL: Master/Slave flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \
-                                                 ((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)))
-
-/** @brief  Clears the I2C pending flags which are cleared by writing 0 in a specific bit.
-  * @param  __HANDLE__: specifies the I2C Handle.
-  *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
-  * @param  __FLAG__: specifies the flag to clear.
-  *         This parameter can be any combination of the following values:
-  *            @arg I2C_FLAG_SMBALERT: SMBus Alert flag
-  *            @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
-  *            @arg I2C_FLAG_PECERR: PEC error in reception flag
-  *            @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
-  *            @arg I2C_FLAG_AF: Acknowledge failure flag
-  *            @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
-  *            @arg I2C_FLAG_BERR: Bus error flag
-  * @retval None
-  */
-#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK))
-
-/** @brief  Clears the I2C ADDR pending flag.
-  * @param  __HANDLE__: specifies the I2C Handle.
-  *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
-  * @retval None
-  */
-#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__)    \
-  do{                                           \
-    __IO uint32_t tmpreg = 0x00U;               \
-    tmpreg = (__HANDLE__)->Instance->SR1;       \
-    tmpreg = (__HANDLE__)->Instance->SR2;       \
-    UNUSED(tmpreg);                             \
-  } while(0)
-
-/** @brief  Clears the I2C STOPF pending flag.
-  * @param  __HANDLE__: specifies the I2C Handle.
-  *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
-  * @retval None
-  */
-#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__)    \
-  do{                                           \
-    __IO uint32_t tmpreg = 0x00U;               \
-    tmpreg = (__HANDLE__)->Instance->SR1;       \
-    (__HANDLE__)->Instance->CR1 |= I2C_CR1_PE;  \
-    UNUSED(tmpreg);                             \
-  } while(0)
-    
-/** @brief  Enable the I2C peripheral.
-  * @param  __HANDLE__: specifies the I2C Handle.
-  *         This parameter can be I2Cx where x: 1 or 2  to select the I2C peripheral.
-  * @retval None
-  */
-#define __HAL_I2C_ENABLE(__HANDLE__)                             ((__HANDLE__)->Instance->CR1 |=  I2C_CR1_PE)
-
-/** @brief  Disable the I2C peripheral.
-  * @param  __HANDLE__: specifies the I2C Handle.
-  *         This parameter can be I2Cx where x: 1 or 2  to select the I2C peripheral.
-  * @retval None
-  */
-#define __HAL_I2C_DISABLE(__HANDLE__)                            ((__HANDLE__)->Instance->CR1 &=  ~I2C_CR1_PE)
-
-/**
-  * @}
-  */
-
-/* Include I2C HAL Extension module */
-#include "stm32f4xx_hal_i2c_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2C_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup I2C_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization/de-initialization functions  **********************************/
-HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
-/**
-  * @}
-  */
-
-/** @addtogroup I2C_Exported_Functions_Group2
-  * @{
-  */
-/* I/O operation functions  *****************************************************/
-/******* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
-
-/******* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-
-HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
-HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
-
-/******* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-
-/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
-void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
-void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
-/**
-  * @}
-  */
-
-/** @addtogroup I2C_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral State, Mode and Errors functions  *********************************/
-HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
-HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
-uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2C_Private_Constants I2C Private Constants
-  * @{
-  */
-#define I2C_FLAG_MASK  ((uint32_t)0x0000FFFFU)
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2C_Private_Macros I2C Private Macros
-  * @{
-  */
-    
-#define I2C_FREQRANGE(__PCLK__)                            ((__PCLK__)/1000000U)
-#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__)            (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
-#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__)            (((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
-#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3U)) : (((__PCLK__) / ((__SPEED__) * 25U)) | I2C_DUTYCYCLE_16_9))
-#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__)      (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
-                                                                  ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \
-                                                                  ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
-
-#define I2C_7BIT_ADD_WRITE(__ADDRESS__)                    ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))
-#define I2C_7BIT_ADD_READ(__ADDRESS__)                     ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
-
-#define I2C_10BIT_ADDRESS(__ADDRESS__)                     ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
-#define I2C_10BIT_HEADER_WRITE(__ADDRESS__)                ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0x00F0U))))
-#define I2C_10BIT_HEADER_READ(__ADDRESS__)                 ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0x00F1U))))
-
-#define I2C_MEM_ADD_MSB(__ADDRESS__)                       ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
-#define I2C_MEM_ADD_LSB(__ADDRESS__)                       ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
-
-/** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters
-  * @{
-  */
-#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \
-                                  ((CYCLE) == I2C_DUTYCYCLE_16_9))
-#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \
-                                         ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT))
-#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
-                                      ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
-#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
-                                   ((CALL) == I2C_GENERALCALL_ENABLE))
-#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
-                                    ((STRETCH) == I2C_NOSTRETCH_ENABLE))
-#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
-                                  ((SIZE) == I2C_MEMADD_SIZE_16BIT))
-#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= 400000U))
-#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (uint32_t)(0xFFFFFC00U)) == 0U)
-#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (uint32_t)(0xFFFFFF01U)) == 0U)
-#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)      (((REQUEST) == I2C_FIRST_FRAME)              || \
-                                                       ((REQUEST) == I2C_NEXT_FRAME)               || \
-                                                       ((REQUEST) == I2C_FIRST_AND_LAST_FRAME)     || \
-                                                       ((REQUEST) == I2C_LAST_FRAME))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup I2C_Private_Functions I2C Private Functions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F4xx_HAL_I2C_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_i2c_ex.h b/stmhal/hal/f4/inc/stm32f4xx_hal_i2c_ex.h
deleted file mode 100644
index 157d5d9a9f..0000000000
--- a/stmhal/hal/f4/inc/stm32f4xx_hal_i2c_ex.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_i2c_ex.h
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   Header file of I2C HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_I2C_EX_H
-#define __STM32F4xx_HAL_I2C_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx)
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"  
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup I2CEx
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup I2CEx_Exported_Constants I2C Exported Constants
-  * @{
-  */
-
-/** @defgroup I2CEx_Analog_Filter I2C Analog Filter
-  * @{
-  */
-#define I2C_ANALOGFILTER_ENABLE        ((uint32_t)0x00000000U)
-#define I2C_ANALOGFILTER_DISABLE       I2C_FLTR_ANOFF
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */ 
-  
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2CEx_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup I2CEx_Exported_Functions_Group1
-  * @{
-  */
-/* Peripheral Control functions  ************************************************/
-HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
-HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2CEx_Private_Constants I2C Private Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2CEx_Private_Macros I2C Private Macros
-  * @{
-  */
-#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
-                                      ((FILTER) == I2C_ANALOGFILTER_DISABLE))
-#define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000FU)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F401xC ||\
-          STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_I2C_EX_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_i2s.h b/stmhal/hal/f4/inc/stm32f4xx_hal_i2s.h
deleted file mode 100644
index 49a007c9c8..0000000000
--- a/stmhal/hal/f4/inc/stm32f4xx_hal_i2s.h
+++ /dev/null
@@ -1,494 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_i2s.h
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   Header file of I2S HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_I2S_H
-#define __STM32F4xx_HAL_I2S_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"  
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup I2S
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup I2S_Exported_Types I2S Exported Types
-  * @{
-  */
-  
-/** 
-  * @brief I2S Init structure definition  
-  */
-typedef struct
-{
-  uint32_t Mode;         /*!< Specifies the I2S operating mode.
-                              This parameter can be a value of @ref I2S_Mode */
-
-  uint32_t Standard;     /*!< Specifies the standard used for the I2S communication.
-                              This parameter can be a value of @ref I2S_Standard */
-
-  uint32_t DataFormat;   /*!< Specifies the data format for the I2S communication.
-                              This parameter can be a value of @ref I2S_Data_Format */
-
-  uint32_t MCLKOutput;   /*!< Specifies whether the I2S MCLK output is enabled or not.
-                              This parameter can be a value of @ref I2S_MCLK_Output */
-
-  uint32_t AudioFreq;    /*!< Specifies the frequency selected for the I2S communication.
-                              This parameter can be a value of @ref I2S_Audio_Frequency */
-
-  uint32_t CPOL;         /*!< Specifies the idle state of the I2S clock.
-                              This parameter can be a value of @ref I2S_Clock_Polarity */
-
-  uint32_t ClockSource;  /*!< Specifies the I2S Clock Source.
-                              This parameter can be a value of @ref I2S_Clock_Source */
-
-  uint32_t FullDuplexMode;  /*!< Specifies the I2S FullDuplex mode.
-                                 This parameter can be a value of @ref I2S_FullDuplex_Mode */
-
-}I2S_InitTypeDef;
-
-/** 
-  * @brief  HAL State structures definition
-  */ 
-typedef enum
-{
-  HAL_I2S_STATE_RESET      = 0x00U,  /*!< I2S not yet initialized or disabled                */
-  HAL_I2S_STATE_READY      = 0x01U,  /*!< I2S initialized and ready for use                  */
-  HAL_I2S_STATE_BUSY       = 0x02U,  /*!< I2S internal process is ongoing                    */
-  HAL_I2S_STATE_BUSY_TX    = 0x12U,  /*!< Data Transmission process is ongoing               */
-  HAL_I2S_STATE_BUSY_RX    = 0x22U,  /*!< Data Reception process is ongoing                  */
-  HAL_I2S_STATE_BUSY_TX_RX = 0x32U,  /*!< Data Transmission and Reception process is ongoing */
-  HAL_I2S_STATE_TIMEOUT    = 0x03U,  /*!< I2S timeout state                                  */
-  HAL_I2S_STATE_ERROR      = 0x04U   /*!< I2S error state                                    */
-
-}HAL_I2S_StateTypeDef;
-
-/** 
-  * @brief I2S handle Structure definition  
-  */
-typedef struct
-{
-  SPI_TypeDef                *Instance;    /* I2S registers base address        */
-
-  I2S_InitTypeDef            Init;         /* I2S communication parameters      */
-  
-  uint16_t                   *pTxBuffPtr;  /* Pointer to I2S Tx transfer buffer */
-  
-  __IO uint16_t              TxXferSize;   /* I2S Tx transfer size              */
-  
-  __IO uint16_t              TxXferCount;  /* I2S Tx transfer Counter           */
-  
-  uint16_t                   *pRxBuffPtr;  /* Pointer to I2S Rx transfer buffer */
-  
-  __IO uint16_t              RxXferSize;   /* I2S Rx transfer size              */
-  
-  __IO uint16_t              RxXferCount;  /* I2S Rx transfer counter           */
-
-  DMA_HandleTypeDef          *hdmatx;      /* I2S Tx DMA handle parameters      */
-
-  DMA_HandleTypeDef          *hdmarx;      /* I2S Rx DMA handle parameters      */
-  
-  __IO HAL_LockTypeDef       Lock;         /* I2S locking object                */
-  
-  __IO HAL_I2S_StateTypeDef  State;        /* I2S communication state           */
-  
-  __IO uint32_t              ErrorCode;    /* I2S Error code                    */
-  
-}I2S_HandleTypeDef;
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup I2S_Exported_Constants I2S Exported Constants
-  * @{
-  */
-
-/** @defgroup I2S_Error_Code I2S Error Code
-  * @brief    I2S Error Code 
-  * @{
-  */ 
-#define HAL_I2S_ERROR_NONE          ((uint32_t)0x00000000U)    /*!< No error                    */
-#define HAL_I2S_ERROR_UDR           ((uint32_t)0x00000001U)    /*!< I2S Underrun error          */
-#define HAL_I2S_ERROR_OVR           ((uint32_t)0x00000002U)    /*!< I2S Overrun error           */
-#define HAL_I2SEX_ERROR_UDR         ((uint32_t)0x00000004U)    /*!< I2S extended Underrun error */
-#define HAL_I2SEX_ERROR_OVR         ((uint32_t)0x00000008U)    /*!< I2S extended Overrun error  */
-#define HAL_I2S_ERROR_FRE           ((uint32_t)0x00000010U)    /*!< I2S Frame format error      */
-#define HAL_I2S_ERROR_DMA           ((uint32_t)0x00000020U)    /*!< DMA transfer error          */
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Mode I2S Mode 
-  * @{
-  */
-#define I2S_MODE_SLAVE_TX                ((uint32_t)0x00000000U)
-#define I2S_MODE_SLAVE_RX                ((uint32_t)0x00000100U)
-#define I2S_MODE_MASTER_TX               ((uint32_t)0x00000200U)
-#define I2S_MODE_MASTER_RX               ((uint32_t)0x00000300U)
-/**
-  * @}
-  */
-  
-/** @defgroup I2S_Standard I2S Standard
-  * @{
-  */
-#define I2S_STANDARD_PHILIPS             ((uint32_t)0x00000000U)
-#define I2S_STANDARD_MSB                 ((uint32_t)0x00000010U)
-#define I2S_STANDARD_LSB                 ((uint32_t)0x00000020U)
-#define I2S_STANDARD_PCM_SHORT           ((uint32_t)0x00000030U)
-#define I2S_STANDARD_PCM_LONG            ((uint32_t)0x000000B0U)
-/**
-  * @}
-  */
-  
-/** @defgroup I2S_Data_Format I2S Data Format
-  * @{
-  */
-#define I2S_DATAFORMAT_16B               ((uint32_t)0x00000000U)
-#define I2S_DATAFORMAT_16B_EXTENDED      ((uint32_t)0x00000001U)
-#define I2S_DATAFORMAT_24B               ((uint32_t)0x00000003U)
-#define I2S_DATAFORMAT_32B               ((uint32_t)0x00000005U)
-/**
-  * @}
-  */
-
-/** @defgroup I2S_MCLK_Output I2S Mclk Output
-  * @{
-  */
-#define I2S_MCLKOUTPUT_ENABLE           ((uint32_t)SPI_I2SPR_MCKOE)
-#define I2S_MCLKOUTPUT_DISABLE          ((uint32_t)0x00000000U)
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Audio_Frequency I2S Audio Frequency 
-  * @{
-  */
-#define I2S_AUDIOFREQ_192K               ((uint32_t)192000U)
-#define I2S_AUDIOFREQ_96K                ((uint32_t)96000U)
-#define I2S_AUDIOFREQ_48K                ((uint32_t)48000U)
-#define I2S_AUDIOFREQ_44K                ((uint32_t)44100U)
-#define I2S_AUDIOFREQ_32K                ((uint32_t)32000U)
-#define I2S_AUDIOFREQ_22K                ((uint32_t)22050U)
-#define I2S_AUDIOFREQ_16K                ((uint32_t)16000U)
-#define I2S_AUDIOFREQ_11K                ((uint32_t)11025U)
-#define I2S_AUDIOFREQ_8K                 ((uint32_t)8000U)
-#define I2S_AUDIOFREQ_DEFAULT            ((uint32_t)2U)
-/**
-  * @}
-  */
-
-/** @defgroup I2S_FullDuplex_Mode I2S FullDuplex Mode
-  * @{
-  */
-#define I2S_FULLDUPLEXMODE_DISABLE                   ((uint32_t)0x00000000U)
-#define I2S_FULLDUPLEXMODE_ENABLE                    ((uint32_t)0x00000001U)
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Clock_Polarity  I2S Clock Polarity
-  * @{
-  */
-#define I2S_CPOL_LOW                    ((uint32_t)0x00000000U)
-#define I2S_CPOL_HIGH                   ((uint32_t)SPI_I2SCFGR_CKPOL)
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
-  * @{
-  */
-#define I2S_IT_TXE                      SPI_CR2_TXEIE
-#define I2S_IT_RXNE                     SPI_CR2_RXNEIE
-#define I2S_IT_ERR                      SPI_CR2_ERRIE
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Flags_Definition I2S Flags Definition
-  * @{
-  */
-#define I2S_FLAG_TXE                    SPI_SR_TXE
-#define I2S_FLAG_RXNE                   SPI_SR_RXNE
-
-#define I2S_FLAG_UDR                    SPI_SR_UDR
-#define I2S_FLAG_OVR                    SPI_SR_OVR
-#define I2S_FLAG_FRE                    SPI_SR_FRE
-
-#define I2S_FLAG_CHSIDE                 SPI_SR_CHSIDE
-#define I2S_FLAG_BSY                    SPI_SR_BSY
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup I2S_Exported_Macros I2S Exported Macros
-  * @{
-  */
-
-/** @brief Reset I2S handle state
-  * @param  __HANDLE__: specifies the I2S Handle.
-  * @retval None
-  */
-#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
-
-/** @brief  Enable or disable the specified SPI peripheral (in I2S mode).
-  * @param  __HANDLE__: specifies the I2S Handle. 
-  * @retval None
-  */
-#define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)
-#define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= ~SPI_I2SCFGR_I2SE)
-
-/** @brief  Enable or disable the specified I2S interrupts.
-  * @param  __HANDLE__: specifies the I2S Handle.
-  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
-  *         This parameter can be one of the following values:
-  *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg I2S_IT_ERR: Error interrupt enable
-  * @retval None
-  */  
-#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
-#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= ~(__INTERRUPT__))
- 
-/** @brief  Checks if the specified I2S interrupt source is enabled or disabled.
-  * @param  __HANDLE__: specifies the I2S Handle.
-  *         This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
-  * @param  __INTERRUPT__: specifies the I2S interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg I2S_IT_ERR: Error interrupt enable
-  * @retval The new state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief  Checks whether the specified I2S flag is set or not.
-  * @param  __HANDLE__: specifies the I2S Handle.
-  * @param  __FLAG__: specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg I2S_FLAG_RXNE: Receive buffer not empty flag
-  *            @arg I2S_FLAG_TXE: Transmit buffer empty flag
-  *            @arg I2S_FLAG_UDR: Underrun flag
-  *            @arg I2S_FLAG_OVR: Overrun flag
-  *            @arg I2S_FLAG_FRE: Frame error flag
-  *            @arg I2S_FLAG_CHSIDE: Channel Side flag
-  *            @arg I2S_FLAG_BSY: Busy flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clears the I2S OVR pending flag.
-  * @param  __HANDLE__: specifies the I2S Handle.
-  * @retval None
-  */
-#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__)     \
-  do{                                           \
-    __IO uint32_t tmpreg = 0x00U;               \
-    tmpreg = (__HANDLE__)->Instance->DR;        \
-    tmpreg = (__HANDLE__)->Instance->SR;        \
-    UNUSED(tmpreg);                             \
-  } while(0)
-    
-/** @brief Clears the I2S UDR pending flag.
-  * @param  __HANDLE__: specifies the I2S Handle.
-  * @retval None
-  */
-#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)     \
-  do{                                           \
-  __IO uint32_t tmpreg = 0x00U;                 \
-  tmpreg = (__HANDLE__)->Instance->SR;          \
-  UNUSED(tmpreg);                               \
-  } while(0)
-/**
-  * @}
-  */
-  
-/* Include I2S Extension module */
-#include "stm32f4xx_hal_i2s_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2S_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup I2S_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization/de-initialization functions  **********************************/
-HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
-HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
-void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
-/**
-  * @}
-  */
-
-/** @addtogroup I2S_Exported_Functions_Group2
-  * @{
-  */
-/* I/O operation functions  *****************************************************/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
-
- /* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
-
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-
-HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
-HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
-HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
-
-/* Peripheral Control and State functions  **************************************/
-HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
-uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
-
-/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
-void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2S_Private_Constants I2S Private Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2S_Private_Macros I2S Private Macros
-  * @{
-  */
-#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX)  || \
-                           ((MODE) == I2S_MODE_SLAVE_RX)  || \
-                           ((MODE) == I2S_MODE_MASTER_TX) || \
-                           ((MODE) == I2S_MODE_MASTER_RX))
-                           
-#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS)   || \
-                                   ((STANDARD) == I2S_STANDARD_MSB)       || \
-                                   ((STANDARD) == I2S_STANDARD_LSB)       || \
-                                   ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
-                                   ((STANDARD) == I2S_STANDARD_PCM_LONG))
-
-#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B)          || \
-                                    ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
-                                    ((FORMAT) == I2S_DATAFORMAT_24B)          || \
-                                    ((FORMAT) == I2S_DATAFORMAT_32B))
-
-#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
-                                    ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
-                                    
-#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
-                                  ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
-                                  ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
-
-#define IS_I2S_FULLDUPLEX_MODE(MODE) (((MODE) == I2S_FULLDUPLEXMODE_DISABLE) || \
-                                      ((MODE) == I2S_FULLDUPLEXMODE_ENABLE))
-
-#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
-                           ((CPOL) == I2S_CPOL_HIGH))
- 
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup I2S_Private_Functions I2S Private Functions
-  * @{
-  */
-void              I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
-void              I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma); 
-void              I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
-void              I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
-void              I2S_DMAError(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout);
-HAL_StatusTypeDef I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
-HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */  
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F4xx_HAL_I2S_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_i2s_ex.h b/stmhal/hal/f4/inc/stm32f4xx_hal_i2s_ex.h
deleted file mode 100644
index f96e8398ff..0000000000
--- a/stmhal/hal/f4/inc/stm32f4xx_hal_i2s_ex.h
+++ /dev/null
@@ -1,211 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_i2s_ex.h
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   Header file of I2S HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_I2S_EX_H
-#define __STM32F4xx_HAL_I2S_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"  
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup I2SEx
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup I2SEx_Exported_Types I2S Exported Types
-  * @{
-  */ 
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup I2SEx_Exported_Constants I2S Exported Constants
-  * @{
-  */
-
-/** @defgroup I2S_Clock_Source I2S Clock Source 
-  * @{
-  */
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
-    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || \
-    defined(STM32F479xx)
-#define I2S_CLOCK_PLL                     ((uint32_t)0x00000000U)
-#define I2S_CLOCK_EXTERNAL                ((uint32_t)0x00000001U)      
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */    
-   
-#if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
-#define I2S_CLOCK_PLL                     ((uint32_t)0x00000000U)
-#define I2S_CLOCK_EXTERNAL                ((uint32_t)0x00000001U) 
-#define I2S_CLOCK_PLLR                    ((uint32_t)0x00000002U)
-#define I2S_CLOCK_PLLSRC                  ((uint32_t)0x00000003U)
-#endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-#define I2S_CLOCK_PLLSRC                  ((uint32_t)0x00000000U)      
-#define I2S_CLOCK_EXTERNAL                ((uint32_t)0x00000001U) 
-#define I2S_CLOCK_PLLR                    ((uint32_t)0x00000002U)
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup I2SEx_Exported_Macros I2S Exported Macros
-  * @{
-  */
-
-/**
-  * @}
-  */ 
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2SEx_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup I2SEx_Exported_Functions_Group1
-  * @{
-  */
-
-/* Extended features functions **************************************************/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size);
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2SEx_Private_Constants I2S Private Constants
-  * @{
-  */
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2SEx_Private_Macros I2S Private Macros
-  * @{
-  */
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
-    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || \
-    defined(STM32F479xx)
-#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) ||\
-                                   ((CLOCK) == I2S_CLOCK_PLL))
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
-    defined(STM32F412Rx) || defined(STM32F412Cx)  
-#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) ||\
-                                   ((CLOCK) == I2S_CLOCK_PLL)      ||\
-                                   ((CLOCK) == I2S_CLOCK_PLLSRC)   ||\
-                                   ((CLOCK) == I2S_CLOCK_PLLR))
-#endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) ||\
-                                   ((CLOCK) == I2S_CLOCK_PLLSRC)     ||\
-                                   ((CLOCK) == I2S_CLOCK_PLLR))
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
-    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Cx) || defined(STM32F410Rx) || \
-    defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || \
-    defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
-#define I2SxEXT(__INSTANCE__) ((__INSTANCE__) == (SPI2)? (SPI_TypeDef *)(I2S2ext_BASE): (SPI_TypeDef *)(I2S3ext_BASE))
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F410Cx || STM32F410Rx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || 
-          STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */      
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup I2SEx_Private_Functions I2S Private Functions
-  * @{
-  */
-HAL_StatusTypeDef I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s);
-uint32_t I2S_GetInputClock(I2S_HandleTypeDef *hi2s); 
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F4xx_HAL_I2S_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_pcd.h b/stmhal/hal/f4/inc/stm32f4xx_hal_pcd.h
deleted file mode 100644
index 74f62fcf10..0000000000
--- a/stmhal/hal/f4/inc/stm32f4xx_hal_pcd.h
+++ /dev/null
@@ -1,343 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_pcd.h
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   Header file of PCD HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_PCD_H
-#define __STM32F4xx_HAL_PCD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
-    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
-    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
-    defined(STM32F412Rx) || defined(STM32F412Cx)
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_ll_usb.h"
-   
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup PCD
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup PCD_Exported_Types PCD Exported Types
-  * @{
-  */
-   
-/**
-  * @brief  PCD State structure definition
-  */
-typedef enum 
-{
-  HAL_PCD_STATE_RESET   = 0x00U,
-  HAL_PCD_STATE_READY   = 0x01U,
-  HAL_PCD_STATE_ERROR   = 0x02U,
-  HAL_PCD_STATE_BUSY    = 0x03U,
-  HAL_PCD_STATE_TIMEOUT = 0x04U
-} PCD_StateTypeDef;
-
-#ifdef USB_OTG_GLPMCFG_LPMEN
-/* Device LPM suspend state */
-typedef enum  
-{
-  LPM_L0 = 0x00U, /* on */
-  LPM_L1 = 0x01U, /* LPM L1 sleep */
-  LPM_L2 = 0x02U, /* suspend */
-  LPM_L3 = 0x03U /* off */
-}PCD_LPM_StateTypeDef;
-#endif /* USB_OTG_GLPMCFG_LPMEN */
-
-typedef USB_OTG_GlobalTypeDef  PCD_TypeDef;
-typedef USB_OTG_CfgTypeDef     PCD_InitTypeDef;
-typedef USB_OTG_EPTypeDef      PCD_EPTypeDef ;
-
-/** 
-  * @brief  PCD Handle Structure definition  
-  */ 
-typedef struct
-{
-  PCD_TypeDef             *Instance;    /*!< Register base address              */
-  PCD_InitTypeDef         Init;         /*!< PCD required parameters            */
-  PCD_EPTypeDef           IN_ep[15];    /*!< IN endpoint parameters             */
-  PCD_EPTypeDef           OUT_ep[15];   /*!< OUT endpoint parameters            */
-  HAL_LockTypeDef         Lock;         /*!< PCD peripheral status              */
-  __IO PCD_StateTypeDef   State;        /*!< PCD communication state            */
-  uint32_t                Setup[12];    /*!< Setup packet buffer                */
-#ifdef USB_OTG_GLPMCFG_LPMEN
-  PCD_LPM_StateTypeDef    LPM_State;    /*!< LPM State                          */
-  uint32_t                BESL;
-  uint32_t                lpm_active;   /*!< Enable or disable the Link Power Management .
-                                        This parameter can be set to ENABLE or DISABLE */
-#endif /* USB_OTG_GLPMCFG_LPMEN */
-#ifdef USB_OTG_GCCFG_BCDEN
-  uint32_t battery_charging_active;     /*!< Enable or disable Battery charging.
-                                        This parameter can be set to ENABLE or DISABLE */
-#endif /* USB_OTG_GCCFG_BCDEN */
-  void                    *pData;       /*!< Pointer to upper stack Handler */
-} PCD_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Include PCD HAL Extension module */
-#include "stm32f4xx_hal_pcd_ex.h"
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup PCD_Exported_Constants PCD Exported Constants
-  * @{
-  */
-
-/** @defgroup PCD_Speed PCD Speed
-  * @{
-  */
-#define PCD_SPEED_HIGH               0U
-#define PCD_SPEED_HIGH_IN_FULL       1U
-#define PCD_SPEED_FULL               2U
-/**
-  * @}
-  */
-  
-/** @defgroup PCD_PHY_Module PCD PHY Module
-  * @{
-  */
-#define PCD_PHY_ULPI                 1U
-#define PCD_PHY_EMBEDDED             2U
-/**
-  * @}
-  */
-  
-/** @defgroup PCD_Turnaround_Timeout Turnaround Timeout Value
-  * @{
-  */
-#ifndef USBD_HS_TRDT_VALUE
- #define USBD_HS_TRDT_VALUE           9U
-#endif /* USBD_HS_TRDT_VALUE */
-#ifndef USBD_FS_TRDT_VALUE
- #define USBD_FS_TRDT_VALUE           5U
-#endif /* USBD_FS_TRDT_VALUE */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup PCD_Exported_Macros PCD Exported Macros
- *  @brief macros to handle interrupts and specific clock configurations
- * @{
- */
-#define __HAL_PCD_ENABLE(__HANDLE__)                   USB_EnableGlobalInt ((__HANDLE__)->Instance)
-#define __HAL_PCD_DISABLE(__HANDLE__)                  USB_DisableGlobalInt ((__HANDLE__)->Instance)
-
-#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
-#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__))
-#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
-
-#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__)             *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
-                                                           ~(USB_OTG_PCGCCTL_STOPCLK)
-
-#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__)               *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
-
-#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__)            ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10U)
-
-#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE                ((uint32_t)0x08U) 
-#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE               ((uint32_t)0x0CU) 
-#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE        ((uint32_t)0x10U) 
-
-#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE                ((uint32_t)0x08U) 
-#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE               ((uint32_t)0x0CU) 
-#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE        ((uint32_t)0x10U) 
-
-#define USB_OTG_HS_WAKEUP_EXTI_LINE              ((uint32_t)0x00100000U)  /*!< External interrupt line 20 Connected to the USB HS EXTI Line */
-#define USB_OTG_FS_WAKEUP_EXTI_LINE              ((uint32_t)0x00040000U)  /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
-
-#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT()    EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE)
-#define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT()   EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
-#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG()     EXTI->PR & (USB_OTG_HS_WAKEUP_EXTI_LINE)
-#define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG()   EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE)
-
-#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() do{EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
-                                                             EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\
-                                                            }while(0)
-
-#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() do{EXTI->FTSR |= (USB_OTG_HS_WAKEUP_EXTI_LINE);\
-                                                              EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
-                                                             }while(0) 
-
-#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() do{EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
-                                                                     EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
-                                                                     EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\
-                                                                     EXTI->FTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\
-                                                                    }while(0)
-
-#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT()   (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE) 
-
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT()    EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT()   EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG()     EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE)
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG()   EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE
-
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() do{EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
-                                                             EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
-                                                            }while(0)  
-
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE()  do{EXTI->FTSR |= (USB_OTG_FS_WAKEUP_EXTI_LINE);\
-                                                               EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
-                                                              }while(0)
-
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()  do{EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
-                                                                      EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
-                                                                      EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
-                                                                      EXTI->FTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
-                                                                     }while(0) 
-
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT()  (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
-/**
-  * @}
-  */ 
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PCD_Exported_Functions PCD Exported Functions
-  * @{
-  */
-
-/* Initialization/de-initialization functions  ********************************/
-/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
-/**
-  * @}
-  */
-
-/* I/O operation functions  ***************************************************/
-/* Non-Blocking mode: Interrupt */
-/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
-  * @{
-  */
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
-
-void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
-/**
-  * @}
-  */
-
-/* Peripheral Control functions  **********************************************/
-/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
-  * @{
-  */
-HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
-HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
-HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
-HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
-uint16_t          HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
-/**
-  * @}
-  */
-
-/* Peripheral State functions  ************************************************/
-/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
-  * @{
-  */
-PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
- 
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup PCD_Private_Macros PCD Private Macros
- * @{
- */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx ||
-          STM32F412Vx || STM32F412Cx */
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F4xx_HAL_PCD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_pcd_ex.h b/stmhal/hal/f4/inc/stm32f4xx_hal_pcd_ex.h
deleted file mode 100644
index 9cc9131d63..0000000000
--- a/stmhal/hal/f4/inc/stm32f4xx_hal_pcd_ex.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_pcd_ex.h
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   Header file of PCD HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_PCD_EX_H
-#define __STM32F4xx_HAL_PCD_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
-    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
-    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
-    defined(STM32F412Rx) || defined(STM32F412Cx)
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-   
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup PCDEx
-  * @{
-  */
-/* Exported types ------------------------------------------------------------*/
-#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
-    defined(STM32F412Rx) || defined(STM32F412Cx)
-typedef enum  
-{
-  PCD_LPM_L0_ACTIVE = 0x00U, /* on */
-  PCD_LPM_L1_ACTIVE = 0x01U /* LPM L1 sleep */
-}PCD_LPM_MsgTypeDef;
-#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx */
-
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
-typedef enum  
-{
-  PCD_BCD_ERROR                     = 0xFFU,
-  PCD_BCD_CONTACT_DETECTION         = 0xFEU,
-  PCD_BCD_STD_DOWNSTREAM_PORT       = 0xFDU,
-  PCD_BCD_CHARGING_DOWNSTREAM_PORT  = 0xFCU,
-  PCD_BCD_DEDICATED_CHARGING_PORT   = 0xFBU,
-  PCD_BCD_DISCOVERY_COMPLETED       = 0x00U
-}PCD_BCD_MsgTypeDef;
-#endif /* STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx */
-
-/* Exported constants --------------------------------------------------------*/
-/* Exported macros -----------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PCDEx_Exported_Functions PCD Extended Exported Functions
-  * @{
-  */
-/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
-  * @{
-  */
-HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
-HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
-#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
-    defined(STM32F412Rx) || defined(STM32F412Cx)
-HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
-void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
-#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx */
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
-HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);
-void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);
-void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
-void HAL_PCDEx_ADP_Sensing_Start(PCD_HandleTypeDef *hpcd);
-void HAL_PCDEx_ADP_Sensing_Callback(PCD_HandleTypeDef *hpcd);
-#endif /* STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx ||
-          STM32F412Vx || STM32F412Cx */
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F4xx_HAL_PCD_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_pwr.h b/stmhal/hal/f4/inc/stm32f4xx_hal_pwr.h
deleted file mode 100644
index b943a16c2f..0000000000
--- a/stmhal/hal/f4/inc/stm32f4xx_hal_pwr.h
+++ /dev/null
@@ -1,449 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_pwr.h
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   Header file of PWR HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_PWR_H
-#define __STM32F4xx_HAL_PWR_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup PWR
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup PWR_Exported_Types PWR Exported Types
-  * @{
-  */
-   
-/**
-  * @brief  PWR PVD configuration structure definition
-  */
-typedef struct
-{
-  uint32_t PVDLevel;   /*!< PVDLevel: Specifies the PVD detection level.
-                            This parameter can be a value of @ref PWR_PVD_detection_level */
-
-  uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.
-                           This parameter can be a value of @ref PWR_PVD_Mode */
-}PWR_PVDTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup PWR_Exported_Constants PWR Exported Constants
-  * @{
-  */
-  
-/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
-  * @{
-  */
-#define PWR_WAKEUP_PIN1                 ((uint32_t)0x00000100U)
-/**
-  * @}
-  */
-
-/** @defgroup PWR_PVD_detection_level PWR PVD detection level
-  * @{
-  */ 
-#define PWR_PVDLEVEL_0                  PWR_CR_PLS_LEV0
-#define PWR_PVDLEVEL_1                  PWR_CR_PLS_LEV1
-#define PWR_PVDLEVEL_2                  PWR_CR_PLS_LEV2
-#define PWR_PVDLEVEL_3                  PWR_CR_PLS_LEV3
-#define PWR_PVDLEVEL_4                  PWR_CR_PLS_LEV4
-#define PWR_PVDLEVEL_5                  PWR_CR_PLS_LEV5
-#define PWR_PVDLEVEL_6                  PWR_CR_PLS_LEV6
-#define PWR_PVDLEVEL_7                  PWR_CR_PLS_LEV7/* External input analog voltage 
-                                                          (Compare internally to VREFINT) */
-/**
-  * @}
-  */   
- 
-/** @defgroup PWR_PVD_Mode PWR PVD Mode
-  * @{
-  */
-#define PWR_PVD_MODE_NORMAL                 ((uint32_t)0x00000000U)   /*!< basic mode is used */
-#define PWR_PVD_MODE_IT_RISING              ((uint32_t)0x00010001U)   /*!< External Interrupt Mode with Rising edge trigger detection */
-#define PWR_PVD_MODE_IT_FALLING             ((uint32_t)0x00010002U)   /*!< External Interrupt Mode with Falling edge trigger detection */
-#define PWR_PVD_MODE_IT_RISING_FALLING      ((uint32_t)0x00010003U)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-#define PWR_PVD_MODE_EVENT_RISING           ((uint32_t)0x00020001U)   /*!< Event Mode with Rising edge trigger detection */
-#define PWR_PVD_MODE_EVENT_FALLING          ((uint32_t)0x00020002U)   /*!< Event Mode with Falling edge trigger detection */
-#define PWR_PVD_MODE_EVENT_RISING_FALLING   ((uint32_t)0x00020003U)   /*!< Event Mode with Rising/Falling edge trigger detection */
-/**
-  * @}
-  */
-
-
-/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
-  * @{
-  */
-#define PWR_MAINREGULATOR_ON                        ((uint32_t)0x00000000U)
-#define PWR_LOWPOWERREGULATOR_ON                    PWR_CR_LPDS
-/**
-  * @}
-  */
-    
-/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
-  * @{
-  */
-#define PWR_SLEEPENTRY_WFI              ((uint8_t)0x01U)
-#define PWR_SLEEPENTRY_WFE              ((uint8_t)0x02U)
-/**
-  * @}
-  */
-
-/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
-  * @{
-  */
-#define PWR_STOPENTRY_WFI               ((uint8_t)0x01U)
-#define PWR_STOPENTRY_WFE               ((uint8_t)0x02U)
-/**
-  * @}
-  */
-
-/** @defgroup PWR_Flag PWR Flag
-  * @{
-  */
-#define PWR_FLAG_WU                     PWR_CSR_WUF
-#define PWR_FLAG_SB                     PWR_CSR_SBF
-#define PWR_FLAG_PVDO                   PWR_CSR_PVDO
-#define PWR_FLAG_BRR                    PWR_CSR_BRR
-#define PWR_FLAG_VOSRDY                 PWR_CSR_VOSRDY
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-  
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup PWR_Exported_Macro PWR Exported Macro
-  * @{
-  */
-
-/** @brief  Check PWR flag is set or not.
-  * @param  __FLAG__: specifies the flag to check.
-  *           This parameter can be one of the following values:
-  *            @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event 
-  *                  was received from the WKUP pin or from the RTC alarm (Alarm A 
-  *                  or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
-  *                  An additional wakeup event is detected if the WKUP pin is enabled 
-  *                  (by setting the EWUP bit) when the WKUP pin level is already high.  
-  *            @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
-  *                  resumed from StandBy mode.    
-  *            @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled 
-  *                  by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode 
-  *                  For this reason, this bit is equal to 0 after Standby or reset
-  *                  until the PVDE bit is set.
-  *            @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset 
-  *                  when the device wakes up from Standby mode or by a system reset 
-  *                  or power reset.  
-  *            @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage 
-  *                 scaling output selection is ready.
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Clear the PWR's pending flags.
-  * @param  __FLAG__: specifies the flag to clear.
-  *          This parameter can be one of the following values:
-  *            @arg PWR_FLAG_WU: Wake Up flag
-  *            @arg PWR_FLAG_SB: StandBy flag
-  */
-#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |=  (__FLAG__) << 2U)
-
-/**
-  * @brief Enable the PVD Exti Line 16.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_ENABLE_IT()   (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
-
-/**
-  * @brief Disable the PVD EXTI Line 16.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_DISABLE_IT()  (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
-
-/**
-  * @brief Enable event on PVD Exti Line 16.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT()   (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
-
-/**
-  * @brief Disable event on PVD Exti Line 16.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT()  (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
-
-/**
-  * @brief Enable the PVD Extended Interrupt Rising Trigger.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
-
-/**
-  * @brief Disable the PVD Extended Interrupt Rising Trigger.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
-
-/**
-  * @brief Enable the PVD Extended Interrupt Falling Trigger.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
-
-
-/**
-  * @brief Disable the PVD Extended Interrupt Falling Trigger.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
-
-
-/**
-  * @brief  PVD EXTI line configuration: set rising & falling edge trigger.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()   do{__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();\
-                                                             __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\
-                                                            }while(0)
-
-/**
-  * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
-  * This parameter can be:
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()  do{__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();\
-                                                             __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();\
-                                                            }while(0) 
-
-/**
-  * @brief checks whether the specified PVD Exti interrupt flag is set or not.
-  * @retval EXTI PVD Line Status.
-  */
-#define __HAL_PWR_PVD_EXTI_GET_FLAG()  (EXTI->PR & (PWR_EXTI_LINE_PVD))
-
-/**
-  * @brief Clear the PVD Exti flag.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG()  (EXTI->PR = (PWR_EXTI_LINE_PVD))
-
-/**
-  * @brief  Generates a Software interrupt on PVD EXTI line.
-  * @retval None
-  */
-#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
-
-/**
-  * @}
-  */
-
-/* Include PWR HAL Extension module */
-#include "stm32f4xx_hal_pwr_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PWR_Exported_Functions PWR Exported Functions
-  * @{
-  */
-  
-/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 
-  * @{
-  */
-/* Initialization and de-initialization functions *****************************/
-void HAL_PWR_DeInit(void);
-void HAL_PWR_EnableBkUpAccess(void);
-void HAL_PWR_DisableBkUpAccess(void);
-/**
-  * @}
-  */
-
-/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions 
-  * @{
-  */
-/* Peripheral Control functions  **********************************************/
-/* PVD configuration */
-void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
-void HAL_PWR_EnablePVD(void);
-void HAL_PWR_DisablePVD(void);
-
-/* WakeUp pins configuration */
-void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
-void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
-
-/* Low Power modes entry */
-void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
-void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
-void HAL_PWR_EnterSTANDBYMode(void);
-
-/* Power PVD IRQ Handler */
-void HAL_PWR_PVD_IRQHandler(void);
-void HAL_PWR_PVDCallback(void);
-
-/* Cortex System Control functions  *******************************************/
-void HAL_PWR_EnableSleepOnExit(void);
-void HAL_PWR_DisableSleepOnExit(void);
-void HAL_PWR_EnableSEVOnPend(void);
-void HAL_PWR_DisableSEVOnPend(void);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup PWR_Private_Constants PWR Private Constants
-  * @{
-  */
-
-/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
-  * @{
-  */
-#define PWR_EXTI_LINE_PVD  ((uint32_t)EXTI_IMR_MR16)  /*!< External interrupt line 16 Connected to the PVD EXTI Line */
-/**
-  * @}
-  */
-
-/** @defgroup PWR_register_alias_address PWR Register alias address
-  * @{
-  */
-/* ------------- PWR registers bit address in the alias region ---------------*/
-#define PWR_OFFSET               (PWR_BASE - PERIPH_BASE)
-#define PWR_CR_OFFSET            0x00U
-#define PWR_CSR_OFFSET           0x04U
-#define PWR_CR_OFFSET_BB         (PWR_OFFSET + PWR_CR_OFFSET)
-#define PWR_CSR_OFFSET_BB        (PWR_OFFSET + PWR_CSR_OFFSET)
-/**
-  * @}
-  */
-
-/** @defgroup PWR_CR_register_alias PWR CR Register alias address
-  * @{
-  */
-/* --- CR Register ---*/
-/* Alias word address of DBP bit */
-#define DBP_BIT_NUMBER   POSITION_VAL(PWR_CR_DBP)
-#define CR_DBP_BB        (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U))
-
-/* Alias word address of PVDE bit */
-#define PVDE_BIT_NUMBER  POSITION_VAL(PWR_CR_PVDE)
-#define CR_PVDE_BB       (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U))
-
-/* Alias word address of PMODE bit */
-#define PMODE_BIT_NUMBER  POSITION_VAL(PWR_CR_PMODE)
-#define CR_PMODE_BB      (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PMODE_BIT_NUMBER * 4U))
-/**
-  * @}
-  */
-
-/** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
-  * @{
-  */
-/* --- CSR Register ---*/
-/* Alias word address of EWUP bit */
-#define EWUP_BIT_NUMBER  POSITION_VAL(PWR_CSR_EWUP)
-#define CSR_EWUP_BB      (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (EWUP_BIT_NUMBER * 4U))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup PWR_Private_Macros PWR Private Macros
-  * @{
-  */
-
-/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
-  * @{
-  */
-#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
-                                 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
-                                 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
-                                 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
-#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
-                              ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
-                              ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
-                              ((MODE) == PWR_PVD_MODE_NORMAL))
-#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
-                                     ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
-#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
-#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F4xx_HAL_PWR_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_pwr_ex.h b/stmhal/hal/f4/inc/stm32f4xx_hal_pwr_ex.h
deleted file mode 100644
index 32a9189112..0000000000
--- a/stmhal/hal/f4/inc/stm32f4xx_hal_pwr_ex.h
+++ /dev/null
@@ -1,370 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_pwr_ex.h
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   Header file of PWR HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_PWR_EX_H
-#define __STM32F4xx_HAL_PWR_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup PWREx
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
-  * @{
-  */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
-   
-/** @defgroup PWREx_Regulator_state_in_UnderDrive_mode PWREx Regulator state in UnderDrive mode
-  * @{
-  */
-#define PWR_MAINREGULATOR_UNDERDRIVE_ON                       PWR_CR_MRUDS
-#define PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON                   ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS))
-/**
-  * @}
-  */ 
-  
-/** @defgroup PWREx_Over_Under_Drive_Flag PWREx Over Under Drive Flag
-  * @{
-  */
-#define PWR_FLAG_ODRDY                  PWR_CSR_ODRDY
-#define PWR_FLAG_ODSWRDY                PWR_CSR_ODSWRDY
-#define PWR_FLAG_UDRDY                  PWR_CSR_UDSWRDY
-/**
-  * @}
-  */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
-
-/** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale
-  * @{
-  */
-#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)   
-#define PWR_REGULATOR_VOLTAGE_SCALE1         PWR_CR_VOS             /* Scale 1 mode(default value at reset): the maximum value of fHCLK = 168 MHz. */
-#define PWR_REGULATOR_VOLTAGE_SCALE2         ((uint32_t)0x00000000U) /* Scale 2 mode: the maximum value of fHCLK = 144 MHz. */
-#else
-#define PWR_REGULATOR_VOLTAGE_SCALE1         PWR_CR_VOS             /* Scale 1 mode(default value at reset): the maximum value of fHCLK is 168 MHz. It can be extended to
-                                                                       180 MHz by activating the over-drive mode. */
-#define PWR_REGULATOR_VOLTAGE_SCALE2         PWR_CR_VOS_1           /* Scale 2 mode: the maximum value of fHCLK is 144 MHz. It can be extended to
-                                                                       168 MHz by activating the over-drive mode. */
-#define PWR_REGULATOR_VOLTAGE_SCALE3         PWR_CR_VOS_0           /* Scale 3 mode: the maximum value of fHCLK is 120 MHz. */
-#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */ 
-/**
-  * @}
-  */
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
-    defined(STM32F412Rx) || defined(STM32F412Cx)
-/** @defgroup PWREx_WakeUp_Pins PWREx WakeUp Pins
-  * @{
-  */
-#define PWR_WAKEUP_PIN2                 ((uint32_t)0x00000080U)
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
-    defined(STM32F412Rx) || defined(STM32F412Cx) 
-#define PWR_WAKEUP_PIN3                 ((uint32_t)0x00000040U)
-#endif /* STM32F410xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Zx || STM32F412Vx || \
-          STM32F412Rx || STM32F412Cx */
-/**
-  * @}
-  */   
-#endif /* STM32F410xx || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-
-/**
-  * @}
-  */ 
-  
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
-  *  @{
-  */
-
-#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)
-/** @brief  macros configure the main internal regulator output voltage.
-  * @param  __REGULATOR__: specifies the regulator output voltage to achieve
-  *         a tradeoff between performance and power consumption when the device does
-  *         not operate at the maximum frequency (refer to the datasheets for more details).
-  *          This parameter can be one of the following values:
-  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
-  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
-  * @retval None
-  */
-#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do {                                                     \
-                                                            __IO uint32_t tmpreg = 0x00U;                        \
-                                                            MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__));   \
-                                                            /* Delay after an RCC peripheral clock enabling */  \
-                                                            tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS);             \
-                                                            UNUSED(tmpreg);                                     \
-                                                          } while(0)
-#else
-/** @brief  macros configure the main internal regulator output voltage.
-  * @param  __REGULATOR__: specifies the regulator output voltage to achieve
-  *         a tradeoff between performance and power consumption when the device does
-  *         not operate at the maximum frequency (refer to the datasheets for more details).
-  *          This parameter can be one of the following values:
-  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
-  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
-  *            @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
-  * @retval None
-  */
-#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do {                                                     \
-                                                            __IO uint32_t tmpreg = 0x00U;                        \
-                                                            MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__));   \
-                                                            /* Delay after an RCC peripheral clock enabling */  \
-                                                            tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS);             \
-                                                            UNUSED(tmpreg);                                     \
-                                                          } while(0)
-#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */ 
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
-/** @brief Macros to enable or disable the Over drive mode.
-  * @note  These macros can be used only for STM32F42xx/STM3243xx devices.
-  */
-#define __HAL_PWR_OVERDRIVE_ENABLE() (*(__IO uint32_t *) CR_ODEN_BB = ENABLE)
-#define __HAL_PWR_OVERDRIVE_DISABLE() (*(__IO uint32_t *) CR_ODEN_BB = DISABLE)
-
-/** @brief Macros to enable or disable the Over drive switching.
-  * @note  These macros can be used only for STM32F42xx/STM3243xx devices. 
-  */
-#define __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = ENABLE)
-#define __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = DISABLE)
-
-/** @brief Macros to enable or disable the Under drive mode.
-  * @note  This mode is enabled only with STOP low power mode.
-  *        In this mode, the 1.2V domain is preserved in reduced leakage mode. This 
-  *        mode is only available when the main regulator or the low power regulator 
-  *        is in low voltage mode.      
-  * @note  If the Under-drive mode was enabled, it is automatically disabled after 
-  *        exiting Stop mode. 
-  *        When the voltage regulator operates in Under-drive mode, an additional  
-  *        startup delay is induced when waking up from Stop mode.
-  */
-#define __HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR |= (uint32_t)PWR_CR_UDEN)
-#define __HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR &= (uint32_t)(~PWR_CR_UDEN))
-
-/** @brief  Check PWR flag is set or not.
-  * @note   These macros can be used only for STM32F42xx/STM3243xx devices.
-  * @param  __FLAG__: specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode
-  *                                 is ready 
-  *            @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode
-  *                                   switching is ready  
-  *            @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode
-  *                                 is enabled in Stop mode
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_PWR_GET_ODRUDR_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clear the Under-Drive Ready flag.
-  * @note  These macros can be used only for STM32F42xx/STM3243xx devices.
-  */
-#define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR |= PWR_FLAG_UDRDY)
-
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
-  *  @{
-  */
- 
-/** @addtogroup PWREx_Exported_Functions_Group1
-  * @{
-  */
-void HAL_PWREx_EnableFlashPowerDown(void);
-void HAL_PWREx_DisableFlashPowerDown(void); 
-HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);
-HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void); 
-uint32_t HAL_PWREx_GetVoltageRange(void);
-HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
-
-#if defined(STM32F469xx) || defined(STM32F479xx)
-void HAL_PWREx_EnableWakeUpPinPolarityRisingEdge(void);
-void HAL_PWREx_EnableWakeUpPinPolarityFallingEdge(void);
-#endif /* STM32F469xx || STM32F479xx */
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F401xC) ||\
-    defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
-    defined(STM32F412Rx) || defined(STM32F412Cx)
-void HAL_PWREx_EnableMainRegulatorLowVoltage(void);
-void HAL_PWREx_DisableMainRegulatorLowVoltage(void);
-void HAL_PWREx_EnableLowRegulatorLowVoltage(void);
-void HAL_PWREx_DisableLowRegulatorLowVoltage(void);
-#endif /* STM32F410xx || STM32F401xC || STM32F401xE || STM32F411xE || STM32F412Zx || STM32F412Vx ||\
-          STM32F412Rx || STM32F412Cx */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx)
-HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void);
-HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void);
-HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup PWREx_Private_Constants PWREx Private Constants
-  * @{
-  */
-
-/** @defgroup PWREx_register_alias_address PWREx Register alias address
-  * @{
-  */
-/* ------------- PWR registers bit address in the alias region ---------------*/
-/* --- CR Register ---*/
-/* Alias word address of FPDS bit */
-#define FPDS_BIT_NUMBER          POSITION_VAL(PWR_CR_FPDS)
-#define CR_FPDS_BB               (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (FPDS_BIT_NUMBER * 4U))
-
-/* Alias word address of ODEN bit   */
-#define ODEN_BIT_NUMBER          POSITION_VAL(PWR_CR_ODEN)
-#define CR_ODEN_BB               (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODEN_BIT_NUMBER * 4U))
-
-/* Alias word address of ODSWEN bit */
-#define ODSWEN_BIT_NUMBER        POSITION_VAL(PWR_CR_ODSWEN)
-#define CR_ODSWEN_BB             (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODSWEN_BIT_NUMBER * 4U))
-    
-/* Alias word address of MRLVDS bit */
-#define MRLVDS_BIT_NUMBER        POSITION_VAL(PWR_CR_MRLVDS)
-#define CR_MRLVDS_BB             (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (MRLVDS_BIT_NUMBER * 4U))
-
-/* Alias word address of LPLVDS bit */
-#define LPLVDS_BIT_NUMBER        POSITION_VAL(PWR_CR_LPLVDS)
-#define CR_LPLVDS_BB             (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPLVDS_BIT_NUMBER * 4U))
-
- /**
-  * @}
-  */
-
-/** @defgroup PWREx_CSR_register_alias PWRx CSR Register alias address
-  * @{
-  */  
-/* --- CSR Register ---*/
-/* Alias word address of BRE bit */
-#define BRE_BIT_NUMBER   POSITION_VAL(PWR_CSR_BRE)
-#define CSR_BRE_BB      (uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (BRE_BIT_NUMBER * 4U))
-
-#if defined(STM32F469xx) || defined(STM32F479xx)
-/* Alias word address of WUPP bit */
-#define WUPP_BIT_NUMBER   POSITION_VAL(PWR_CSR_WUPP)
-#define CSR_WUPP_BB      (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (WUPP_BIT_NUMBER * 4U))
-#endif /* STM32F469xx || STM32F479xx */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup PWREx_Private_Macros PWREx Private Macros
-  * @{
-  */
-
-/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters
-  * @{
-  */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
-#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || \
-                                                ((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)
-#define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
-                                               ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
-#else
-#define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
-                                               ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
-                                               ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
-#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */ 
-
-#if defined(STM32F446xx)
-#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2))
-#elif defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
-      defined(STM32F412Rx) || defined(STM32F412Cx)
-#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2) || \
-                                ((PIN) == PWR_WAKEUP_PIN3))
-#else
-#define IS_PWR_WAKEUP_PIN(PIN) ((PIN) == PWR_WAKEUP_PIN1)
-#endif /* STM32F446xx */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F4xx_HAL_PWR_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_rcc.h b/stmhal/hal/f4/inc/stm32f4xx_hal_rcc.h
deleted file mode 100644
index 38d04c3c97..0000000000
--- a/stmhal/hal/f4/inc/stm32f4xx_hal_rcc.h
+++ /dev/null
@@ -1,1424 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_rcc.h
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   Header file of RCC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_RCC_H
-#define __STM32F4xx_HAL_RCC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/* Include RCC HAL Extended module */
-/* (include on top of file since RCC structures are defined in extended file) */
-#include "stm32f4xx_hal_rcc_ex.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup RCC 
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup RCC_Exported_Types RCC Exported Types
-  * @{
-  */
-   
-/**
-  * @brief  RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition  
-  */
-typedef struct
-{
-  uint32_t OscillatorType;       /*!< The oscillators to be configured.
-                                      This parameter can be a value of @ref RCC_Oscillator_Type                   */
-
-  uint32_t HSEState;             /*!< The new state of the HSE.
-                                      This parameter can be a value of @ref RCC_HSE_Config                        */
-
-  uint32_t LSEState;             /*!< The new state of the LSE.
-                                      This parameter can be a value of @ref RCC_LSE_Config                        */
-
-  uint32_t HSIState;             /*!< The new state of the HSI.
-                                      This parameter can be a value of @ref RCC_HSI_Config                        */
-
-  uint32_t HSICalibrationValue;  /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
-                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
-
-  uint32_t LSIState;             /*!< The new state of the LSI.
-                                      This parameter can be a value of @ref RCC_LSI_Config                        */
-
-  RCC_PLLInitTypeDef PLL;        /*!< PLL structure parameters                                                    */
-}RCC_OscInitTypeDef;
-
-/**
-  * @brief  RCC System, AHB and APB busses clock configuration structure definition  
-  */
-typedef struct
-{
-  uint32_t ClockType;             /*!< The clock to be configured.
-                                       This parameter can be a value of @ref RCC_System_Clock_Type      */
-
-  uint32_t SYSCLKSource;          /*!< The clock source (SYSCLKS) used as system clock.
-                                       This parameter can be a value of @ref RCC_System_Clock_Source    */
-
-  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
-                                       This parameter can be a value of @ref RCC_AHB_Clock_Source       */
-
-  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
-                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
-
-  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
-                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
-
-}RCC_ClkInitTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RCC_Exported_Constants RCC Exported Constants
-  * @{
-  */
-
-/** @defgroup RCC_Oscillator_Type Oscillator Type
-  * @{
-  */
-#define RCC_OSCILLATORTYPE_NONE            ((uint32_t)0x00000000U)
-#define RCC_OSCILLATORTYPE_HSE             ((uint32_t)0x00000001U)
-#define RCC_OSCILLATORTYPE_HSI             ((uint32_t)0x00000002U)
-#define RCC_OSCILLATORTYPE_LSE             ((uint32_t)0x00000004U)
-#define RCC_OSCILLATORTYPE_LSI             ((uint32_t)0x00000008U)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_HSE_Config HSE Config
-  * @{
-  */
-#define RCC_HSE_OFF                      ((uint8_t)0x00U)
-#define RCC_HSE_ON                       ((uint8_t)0x01U)
-#define RCC_HSE_BYPASS                   ((uint8_t)0x05U)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LSE_Config LSE Config
-  * @{
-  */
-#define RCC_LSE_OFF                      ((uint8_t)0x00U)
-#define RCC_LSE_ON                       ((uint8_t)0x01U)
-#define RCC_LSE_BYPASS                   ((uint8_t)0x05U)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_HSI_Config HSI Config
-  * @{
-  */
-#define RCC_HSI_OFF                      ((uint8_t)0x00U)
-#define RCC_HSI_ON                       ((uint8_t)0x01U)
-
-#define RCC_HSICALIBRATION_DEFAULT       ((uint32_t)0x10U)         /* Default HSI calibration trimming value */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LSI_Config LSI Config
-  * @{
-  */
-#define RCC_LSI_OFF                      ((uint8_t)0x00U)
-#define RCC_LSI_ON                       ((uint8_t)0x01U)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PLL_Config PLL Config
-  * @{
-  */
-#define RCC_PLL_NONE                      ((uint8_t)0x00U)
-#define RCC_PLL_OFF                       ((uint8_t)0x01U)
-#define RCC_PLL_ON                        ((uint8_t)0x02U)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
-  * @{
-  */
-#define RCC_PLLP_DIV2                  ((uint32_t)0x00000002U)
-#define RCC_PLLP_DIV4                  ((uint32_t)0x00000004U)
-#define RCC_PLLP_DIV6                  ((uint32_t)0x00000006U)
-#define RCC_PLLP_DIV8                  ((uint32_t)0x00000008U)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
-  * @{
-  */
-#define RCC_PLLSOURCE_HSI                RCC_PLLCFGR_PLLSRC_HSI
-#define RCC_PLLSOURCE_HSE                RCC_PLLCFGR_PLLSRC_HSE
-/**
-  * @}
-  */
-
-/** @defgroup RCC_System_Clock_Type System Clock Type
-  * @{
-  */
-#define RCC_CLOCKTYPE_SYSCLK             ((uint32_t)0x00000001U)
-#define RCC_CLOCKTYPE_HCLK               ((uint32_t)0x00000002U)
-#define RCC_CLOCKTYPE_PCLK1              ((uint32_t)0x00000004U)
-#define RCC_CLOCKTYPE_PCLK2              ((uint32_t)0x00000008U)
-/**
-  * @}
-  */
-  
-/** @defgroup RCC_System_Clock_Source System Clock Source 
-  * @{
-  */
-#define RCC_SYSCLKSOURCE_HSI             RCC_CFGR_SW_HSI
-#define RCC_SYSCLKSOURCE_HSE             RCC_CFGR_SW_HSE
-#define RCC_SYSCLKSOURCE_PLLCLK          RCC_CFGR_SW_PLL
-#define RCC_SYSCLKSOURCE_PLLRCLK         ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
-  * @{
-  */
-#define RCC_SYSCLKSOURCE_STATUS_HSI     RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
-#define RCC_SYSCLKSOURCE_STATUS_HSE     RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
-#define RCC_SYSCLKSOURCE_STATUS_PLLCLK  RCC_CFGR_SWS_PLL   /*!< PLL used as system clock */
-#define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SWS_0 | RCC_CFGR_SWS_1))   /*!< PLLR used as system clock */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
-  * @{
-  */
-#define RCC_SYSCLK_DIV1                  RCC_CFGR_HPRE_DIV1
-#define RCC_SYSCLK_DIV2                  RCC_CFGR_HPRE_DIV2
-#define RCC_SYSCLK_DIV4                  RCC_CFGR_HPRE_DIV4
-#define RCC_SYSCLK_DIV8                  RCC_CFGR_HPRE_DIV8
-#define RCC_SYSCLK_DIV16                 RCC_CFGR_HPRE_DIV16
-#define RCC_SYSCLK_DIV64                 RCC_CFGR_HPRE_DIV64
-#define RCC_SYSCLK_DIV128                RCC_CFGR_HPRE_DIV128
-#define RCC_SYSCLK_DIV256                RCC_CFGR_HPRE_DIV256
-#define RCC_SYSCLK_DIV512                RCC_CFGR_HPRE_DIV512
-/**
-  * @}
-  */ 
-  
-/** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source
-  * @{
-  */
-#define RCC_HCLK_DIV1                    RCC_CFGR_PPRE1_DIV1
-#define RCC_HCLK_DIV2                    RCC_CFGR_PPRE1_DIV2
-#define RCC_HCLK_DIV4                    RCC_CFGR_PPRE1_DIV4
-#define RCC_HCLK_DIV8                    RCC_CFGR_PPRE1_DIV8
-#define RCC_HCLK_DIV16                   RCC_CFGR_PPRE1_DIV16
-/**
-  * @}
-  */ 
-
-/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
-  * @{
-  */
-#define RCC_RTCCLKSOURCE_LSE             ((uint32_t)0x00000100U)
-#define RCC_RTCCLKSOURCE_LSI             ((uint32_t)0x00000200U)
-#define RCC_RTCCLKSOURCE_HSE_DIV2        ((uint32_t)0x00020300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV3        ((uint32_t)0x00030300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV4        ((uint32_t)0x00040300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV5        ((uint32_t)0x00050300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV6        ((uint32_t)0x00060300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV7        ((uint32_t)0x00070300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV8        ((uint32_t)0x00080300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV9        ((uint32_t)0x00090300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV10       ((uint32_t)0x000A0300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV11       ((uint32_t)0x000B0300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV12       ((uint32_t)0x000C0300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV13       ((uint32_t)0x000D0300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV14       ((uint32_t)0x000E0300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV15       ((uint32_t)0x000F0300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV16       ((uint32_t)0x00100300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV17       ((uint32_t)0x00110300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV18       ((uint32_t)0x00120300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV19       ((uint32_t)0x00130300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV20       ((uint32_t)0x00140300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV21       ((uint32_t)0x00150300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV22       ((uint32_t)0x00160300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV23       ((uint32_t)0x00170300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV24       ((uint32_t)0x00180300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV25       ((uint32_t)0x00190300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV26       ((uint32_t)0x001A0300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV27       ((uint32_t)0x001B0300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV28       ((uint32_t)0x001C0300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV29       ((uint32_t)0x001D0300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV30       ((uint32_t)0x001E0300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV31       ((uint32_t)0x001F0300U)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_MCO_Index MCO Index
-  * @{
-  */
-#define RCC_MCO1                         ((uint32_t)0x00000000U)
-#define RCC_MCO2                         ((uint32_t)0x00000001U)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
-  * @{
-  */
-#define RCC_MCO1SOURCE_HSI               ((uint32_t)0x00000000U)
-#define RCC_MCO1SOURCE_LSE               RCC_CFGR_MCO1_0
-#define RCC_MCO1SOURCE_HSE               RCC_CFGR_MCO1_1
-#define RCC_MCO1SOURCE_PLLCLK            RCC_CFGR_MCO1
-/**
-  * @}
-  */
-
-/** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler
-  * @{
-  */
-#define RCC_MCODIV_1                    ((uint32_t)0x00000000U)
-#define RCC_MCODIV_2                    RCC_CFGR_MCO1PRE_2
-#define RCC_MCODIV_3                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
-#define RCC_MCODIV_4                    ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
-#define RCC_MCODIV_5                    RCC_CFGR_MCO1PRE
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Interrupt Interrupts
-  * @{
-  */
-#define RCC_IT_LSIRDY                    ((uint8_t)0x01U)
-#define RCC_IT_LSERDY                    ((uint8_t)0x02U)
-#define RCC_IT_HSIRDY                    ((uint8_t)0x04U)
-#define RCC_IT_HSERDY                    ((uint8_t)0x08U)
-#define RCC_IT_PLLRDY                    ((uint8_t)0x10U)
-#define RCC_IT_PLLI2SRDY                 ((uint8_t)0x20U)
-#define RCC_IT_CSS                       ((uint8_t)0x80U)
-/**
-  * @}
-  */
-  
-/** @defgroup RCC_Flag Flags
-  *        Elements values convention: 0XXYYYYYb
-  *           - YYYYY  : Flag position in the register
-  *           - 0XX  : Register index
-  *                 - 01: CR register
-  *                 - 10: BDCR register
-  *                 - 11: CSR register
-  * @{
-  */
-/* Flags in the CR register */
-#define RCC_FLAG_HSIRDY                  ((uint8_t)0x21U)
-#define RCC_FLAG_HSERDY                  ((uint8_t)0x31U)
-#define RCC_FLAG_PLLRDY                  ((uint8_t)0x39U)
-#define RCC_FLAG_PLLI2SRDY               ((uint8_t)0x3BU)
-
-/* Flags in the BDCR register */
-#define RCC_FLAG_LSERDY                  ((uint8_t)0x41U)
-
-/* Flags in the CSR register */
-#define RCC_FLAG_LSIRDY                  ((uint8_t)0x61U)
-#define RCC_FLAG_BORRST                  ((uint8_t)0x79U)
-#define RCC_FLAG_PINRST                  ((uint8_t)0x7AU)
-#define RCC_FLAG_PORRST                  ((uint8_t)0x7BU)
-#define RCC_FLAG_SFTRST                  ((uint8_t)0x7CU)
-#define RCC_FLAG_IWDGRST                 ((uint8_t)0x7DU)
-#define RCC_FLAG_WWDGRST                 ((uint8_t)0x7EU)
-#define RCC_FLAG_LPWRRST                 ((uint8_t)0x7FU)
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RCC_Exported_Macros RCC Exported Macros
-  * @{
-  */
-
-/** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.   
-  * @{
-  */
-#define __HAL_RCC_GPIOA_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
-                                        UNUSED(tmpreg); \
-                                          } while(0)
-#define __HAL_RCC_GPIOB_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
-                                        UNUSED(tmpreg); \
-                                          } while(0)
-#define __HAL_RCC_GPIOC_CLK_ENABLE()  do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
-                                        UNUSED(tmpreg); \
-                                          } while(0)
-#define __HAL_RCC_GPIOH_CLK_ENABLE()  do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
-                                        UNUSED(tmpreg); \
-                                         } while(0)
-#define __HAL_RCC_DMA1_CLK_ENABLE()  do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
-                                        UNUSED(tmpreg); \
-                                         } while(0)
-#define __HAL_RCC_DMA2_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
-                                        UNUSED(tmpreg); \
-                                          } while(0)
-
-#define __HAL_RCC_GPIOA_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
-#define __HAL_RCC_GPIOB_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
-#define __HAL_RCC_GPIOC_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
-#define __HAL_RCC_GPIOH_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
-#define __HAL_RCC_DMA1_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
-#define __HAL_RCC_DMA2_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_GPIOA_IS_CLK_ENABLED()        ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET)  
-#define __HAL_RCC_GPIOB_IS_CLK_ENABLED()        ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET)  
-#define __HAL_RCC_GPIOC_IS_CLK_ENABLED()        ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET) 
-#define __HAL_RCC_GPIOH_IS_CLK_ENABLED()        ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET) 
-#define __HAL_RCC_DMA1_IS_CLK_ENABLED()         ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET) 
-#define __HAL_RCC_DMA2_IS_CLK_ENABLED()         ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET) 
-
-#define __HAL_RCC_GPIOA_IS_CLK_DISABLED()       ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET)       
-#define __HAL_RCC_GPIOB_IS_CLK_DISABLED()       ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET) 
-#define __HAL_RCC_GPIOC_IS_CLK_DISABLED()       ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET)
-#define __HAL_RCC_GPIOH_IS_CLK_DISABLED()       ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET) 
-#define __HAL_RCC_DMA1_IS_CLK_DISABLED()        ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET)
-#define __HAL_RCC_DMA2_IS_CLK_DISABLED()        ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET) 
-/**
-  * @}
-  */  
-  
-/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_TIM5_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
-                                        UNUSED(tmpreg); \
-                                          } while(0)
-#define __HAL_RCC_WWDG_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
-                                        UNUSED(tmpreg); \
-                                          } while(0)
-#define __HAL_RCC_SPI2_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
-                                        UNUSED(tmpreg); \
-                                          } while(0)
-#define __HAL_RCC_USART2_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
-                                        UNUSED(tmpreg); \
-                                          } while(0)
-#define __HAL_RCC_I2C1_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
-                                        UNUSED(tmpreg); \
-                                          } while(0)
-#define __HAL_RCC_I2C2_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
-                                        UNUSED(tmpreg); \
-                                          } while(0)
-#define __HAL_RCC_PWR_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
-                                        UNUSED(tmpreg); \
-                                          } while(0)
-
-#define __HAL_RCC_TIM5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
-#define __HAL_RCC_WWDG_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
-#define __HAL_RCC_SPI2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
-#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
-#define __HAL_RCC_I2C1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
-#define __HAL_RCC_I2C2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
-#define __HAL_RCC_PWR_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) 
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the APB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_TIM5_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
-#define __HAL_RCC_WWDG_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
-#define __HAL_RCC_SPI2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
-#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
-#define __HAL_RCC_I2C1_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
-#define __HAL_RCC_I2C2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
-#define __HAL_RCC_PWR_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
-
-#define __HAL_RCC_TIM5_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
-#define __HAL_RCC_WWDG_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
-#define __HAL_RCC_SPI2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
-#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
-#define __HAL_RCC_I2C1_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
-#define __HAL_RCC_I2C2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
-#define __HAL_RCC_PWR_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)   
-/**
-  * @}
-  */  
-  
-/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_TIM1_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
-                                        UNUSED(tmpreg); \
-                                          } while(0)
-#define __HAL_RCC_USART1_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
-                                        UNUSED(tmpreg); \
-                                          } while(0)
-#define __HAL_RCC_USART6_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
-                                        UNUSED(tmpreg); \
-                                          } while(0)
-#define __HAL_RCC_ADC1_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
-                                        UNUSED(tmpreg); \
-                                          } while(0)
-#define __HAL_RCC_SPI1_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
-                                        UNUSED(tmpreg); \
-                                          } while(0)
-#define __HAL_RCC_SYSCFG_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
-                                        UNUSED(tmpreg); \
-                                          } while(0)
-#define __HAL_RCC_TIM9_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
-                                        UNUSED(tmpreg); \
-                                          } while(0)
-#define __HAL_RCC_TIM11_CLK_ENABLE()    do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
-                                        UNUSED(tmpreg); \
-                                          } while(0)
-
-#define __HAL_RCC_TIM1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
-#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
-#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
-#define __HAL_RCC_ADC1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
-#define __HAL_RCC_SPI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
-#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
-#define __HAL_RCC_TIM9_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
-#define __HAL_RCC_TIM11_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the APB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_TIM1_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
-#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
-#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
-#define __HAL_RCC_ADC1_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
-#define __HAL_RCC_SPI1_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
-#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
-#define __HAL_RCC_TIM9_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
-#define __HAL_RCC_TIM11_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)  
-
-#define __HAL_RCC_TIM1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
-#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
-#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
-#define __HAL_RCC_ADC1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
-#define __HAL_RCC_SPI1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
-#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
-#define __HAL_RCC_TIM9_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
-#define __HAL_RCC_TIM11_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET) 
-/**
-  * @}
-  */  
-  
-/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset 
-  * @brief  Force or release AHB1 peripheral reset.
-  * @{
-  */  
-#define __HAL_RCC_AHB1_FORCE_RESET()    (RCC->AHB1RSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_GPIOA_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
-#define __HAL_RCC_GPIOB_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
-#define __HAL_RCC_GPIOC_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
-#define __HAL_RCC_GPIOH_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
-#define __HAL_RCC_DMA1_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
-#define __HAL_RCC_DMA2_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
-
-#define __HAL_RCC_AHB1_RELEASE_RESET()  (RCC->AHB1RSTR = 0x00U)
-#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
-#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
-#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
-#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
-#define __HAL_RCC_DMA1_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
-#define __HAL_RCC_DMA2_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset 
-  * @brief  Force or release APB1 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_APB1_FORCE_RESET()     (RCC->APB1RSTR = 0xFFFFFFFFU)  
-#define __HAL_RCC_TIM5_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
-#define __HAL_RCC_WWDG_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
-#define __HAL_RCC_SPI2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
-#define __HAL_RCC_USART2_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
-#define __HAL_RCC_I2C1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
-#define __HAL_RCC_I2C2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
-#define __HAL_RCC_PWR_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
-
-#define __HAL_RCC_APB1_RELEASE_RESET()   (RCC->APB1RSTR = 0x00U) 
-#define __HAL_RCC_TIM5_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
-#define __HAL_RCC_WWDG_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
-#define __HAL_RCC_SPI2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
-#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
-#define __HAL_RCC_I2C1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
-#define __HAL_RCC_I2C2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
-#define __HAL_RCC_PWR_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset 
-  * @brief  Force or release APB2 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_APB2_FORCE_RESET()     (RCC->APB2RSTR = 0xFFFFFFFFU)  
-#define __HAL_RCC_TIM1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
-#define __HAL_RCC_USART1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
-#define __HAL_RCC_USART6_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
-#define __HAL_RCC_ADC_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
-#define __HAL_RCC_SPI1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
-#define __HAL_RCC_SYSCFG_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
-#define __HAL_RCC_TIM9_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
-#define __HAL_RCC_TIM11_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
-
-#define __HAL_RCC_APB2_RELEASE_RESET()   (RCC->APB2RSTR = 0x00U)
-#define __HAL_RCC_TIM1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
-#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
-#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
-#define __HAL_RCC_ADC_RELEASE_RESET()    (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
-#define __HAL_RCC_SPI1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
-#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
-#define __HAL_RCC_TIM9_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
-#define __HAL_RCC_TIM11_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 
-  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
-#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
-#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
-#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
-#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE()     (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
-#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE()     (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
-
-#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
-#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
-#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
-#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
-#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE()    (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
-#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE()    (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
-#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
-#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
-#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
-#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
-#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
-#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
-
-#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
-#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
-#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
-#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
-#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
-#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
-#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
-#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
-#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
-#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
-#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
-#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
-#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
-#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
-
-#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
-#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
-#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
-#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
-#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
-#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
-#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
-#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_HSI_Configuration HSI Configuration
-  * @{   
-  */ 
-                                      
-/** @brief  Macros to enable or disable the Internal High Speed oscillator (HSI).
-  * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
-  *         It is used (enabled by hardware) as system clock source after startup
-  *         from Reset, wake-up from STOP and STANDBY mode, or in case of failure
-  *         of the HSE used directly or indirectly as system clock (if the Clock
-  *         Security System CSS is enabled).             
-  * @note   HSI can not be stopped if it is used as system clock source. In this case,
-  *         you have to select another source of the system clock then stop the HSI.  
-  * @note   After enabling the HSI, the application software should wait on HSIRDY
-  *         flag to be set indicating that HSI clock is stable and can be used as
-  *         system clock source.  
-  *         This parameter can be: ENABLE or DISABLE.
-  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
-  *         clock cycles.  
-  */
-#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
-#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
-
-/** @brief  Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
-  * @note   The calibration is used to compensate for the variations in voltage
-  *         and temperature that influence the frequency of the internal HSI RC.
-  * @param  __HSICalibrationValue__: specifies the calibration trimming value.
-  *         (default is RCC_HSICALIBRATION_DEFAULT).
-  *         This parameter must be a number between 0 and 0x1F.
-  */
-#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
-        RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM)))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LSI_Configuration LSI Configuration
-  * @{   
-  */ 
-
-/** @brief  Macros to enable or disable the Internal Low Speed oscillator (LSI).
-  * @note   After enabling the LSI, the application software should wait on 
-  *         LSIRDY flag to be set indicating that LSI clock is stable and can
-  *         be used to clock the IWDG and/or the RTC.
-  * @note   LSI can not be disabled if the IWDG is running.
-  * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
-  *         clock cycles. 
-  */
-#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
-#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_HSE_Configuration HSE Configuration
-  * @{   
-  */ 
-
-/**
-  * @brief  Macro to configure the External High Speed oscillator (HSE).
-  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro. 
-  *         User should request a transition to HSE Off first and then HSE On or HSE Bypass.
-  * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
-  *         software should wait on HSERDY flag to be set indicating that HSE clock
-  *         is stable and can be used to clock the PLL and/or system clock.
-  * @note   HSE state can not be changed if it is used directly or through the
-  *         PLL as system clock. In this case, you have to select another source
-  *         of the system clock then change the HSE state (ex. disable it).
-  * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.  
-  * @note   This function reset the CSSON bit, so if the clock security system(CSS)
-  *         was previously enabled you have to enable it again after calling this
-  *         function.    
-  * @param  __STATE__: specifies the new state of the HSE.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
-  *                              6 HSE oscillator clock cycles.
-  *            @arg RCC_HSE_ON: turn ON the HSE oscillator.
-  *            @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
-  */
-#define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *) RCC_CR_BYTE2_ADDRESS = (__STATE__))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LSE_Configuration LSE Configuration
-  * @{   
-  */
-
-/**
-  * @brief  Macro to configure the External Low Speed oscillator (LSE).
-  * @note   Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. 
-  *         User should request a transition to LSE Off first and then LSE On or LSE Bypass.
-  * @note   As the LSE is in the Backup domain and write access is denied to
-  *         this domain after reset, you have to enable write access using 
-  *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
-  *         (to be done once after reset).  
-  * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
-  *         software should wait on LSERDY flag to be set indicating that LSE clock
-  *         is stable and can be used to clock the RTC.
-  * @param  __STATE__: specifies the new state of the LSE.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
-  *                              6 LSE oscillator clock cycles.
-  *            @arg RCC_LSE_ON: turn ON the LSE oscillator.
-  *            @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
-  */
-#define __HAL_RCC_LSE_CONFIG(__STATE__)  (*(__IO uint8_t *) RCC_BDCR_BYTE0_ADDRESS = (__STATE__))
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
-  * @{   
-  */
-
-/** @brief  Macros to enable or disable the RTC clock.
-  * @note   These macros must be used only after the RTC clock source was selected.
-  */
-#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
-#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
-
-/** @brief  Macros to configure the RTC clock (RTCCLK).
-  * @note   As the RTC clock configuration bits are in the Backup domain and write
-  *         access is denied to this domain after reset, you have to enable write
-  *         access using the Power Backup Access macro before to configure
-  *         the RTC clock source (to be done once after reset).    
-  * @note   Once the RTC clock is configured it can't be changed unless the  
-  *         Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
-  *         a Power On Reset (POR).
-  * @param  __RTCCLKSource__: specifies the RTC clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
-  *            @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
-  *            @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
-  *                                            as RTC clock, where x:[2,31]
-  * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
-  *         work in STOP and STANDBY modes, and can be used as wake-up source.
-  *         However, when the HSE clock is used as RTC clock source, the RTC
-  *         cannot be used in STOP and STANDBY modes.    
-  * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
-  *         RTC clock source).
-  */
-#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ?    \
-                                                 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFFU)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
-                                                   
-#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__);    \
-                                                    RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU);  \
-                                                   } while (0)
-
-/** @brief  Macros to force or release the Backup domain reset.
-  * @note   This function resets the RTC peripheral (including the backup registers)
-  *         and the RTC clock source selection in RCC_CSR register.
-  * @note   The BKPSRAM is not affected by this reset.   
-  */
-#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
-#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PLL_Configuration PLL Configuration
-  * @{   
-  */
-
-/** @brief  Macros to enable or disable the main PLL.
-  * @note   After enabling the main PLL, the application software should wait on 
-  *         PLLRDY flag to be set indicating that PLL clock is stable and can
-  *         be used as system clock source.
-  * @note   The main PLL can not be disabled if it is used as system clock source
-  * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
-  */
-#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
-#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
-
-/** @brief  Macro to configure the PLL clock source.
-  * @note   This function must be used only when the main PLL is disabled.
-  * @param  __PLLSOURCE__: specifies the PLL entry clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
-  *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
-  *      
-  */
-#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
-
-/** @brief  Macro to configure the PLL multiplication factor.
-  * @note   This function must be used only when the main PLL is disabled.
-  * @param  __PLLM__: specifies the division factor for PLL VCO input clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
-  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
-  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
-  *         of 2 MHz to limit PLL jitter.
-  *      
-  */
-#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Get_Clock_source Get Clock source
-  * @{   
-  */
-/**
-  * @brief Macro to configure the system clock source.
-  * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
-  * This parameter can be one of the following values:
-  *              - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
-  *              - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
-  *              - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
-  *              - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source.
-  */
-#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
-
-/** @brief  Macro to get the clock source used as system clock.
-  * @retval The clock source used as system clock. The returned value can be one
-  *         of the following:
-  *              - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
-  *              - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
-  *              - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
-  *              - RCC_SYSCLKSOURCE_STATUS_PLLRCLK: PLLR used as system clock.
-  */     
-#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
-
-/** @brief  Macro to get the oscillator used as PLL clock source.
-  * @retval The oscillator used as PLL clock source. The returned value can be one
-  *         of the following:
-  *              - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
-  *              - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
-  */
-#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
-  * @{   
-  */ 
-  
-/** @brief  Macro to configure the MCO1 clock.
-  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
-  *            @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
-  *            @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
-  *            @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
-  * @param  __MCODIV__ specifies the MCO clock prescaler.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_MCODIV_1: no division applied to MCOx clock
-  *            @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
-  *            @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
-  *            @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
-  *            @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
-  */
-#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
-                 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
-
-/** @brief  Macro to configure the MCO2 clock.
-  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
-  *            @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx 
-  *            @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices   
-  *            @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
-  *            @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
-  * @param  __MCODIV__ specifies the MCO clock prescaler.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_MCODIV_1: no division applied to MCOx clock
-  *            @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
-  *            @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
-  *            @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
-  *            @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
-  * @note  For STM32F410Rx devices, to output I2SCLK clock on MCO2, you should have
-  *        at least one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
-  */
-#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
-    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3U)));
-/**
-  * @}
-  */
-  
-/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
-  * @brief macros to manage the specified RCC Flags and interrupts.
-  * @{
-  */
-
-/** @brief  Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
-  *         the selected interrupts).
-  * @param  __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
-  *         This parameter can be any combination of the following values:
-  *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
-  *            @arg RCC_IT_LSERDY: LSE ready interrupt.
-  *            @arg RCC_IT_HSIRDY: HSI ready interrupt.
-  *            @arg RCC_IT_HSERDY: HSE ready interrupt.
-  *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
-  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
-  */
-#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
-
-/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable 
-  *        the selected interrupts).
-  * @param  __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
-  *         This parameter can be any combination of the following values:
-  *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
-  *            @arg RCC_IT_LSERDY: LSE ready interrupt.
-  *            @arg RCC_IT_HSIRDY: HSI ready interrupt.
-  *            @arg RCC_IT_HSERDY: HSE ready interrupt.
-  *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
-  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
-  */
-#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
-
-/** @brief  Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
-  *         bits to clear the selected interrupt pending bits.
-  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
-  *         This parameter can be any combination of the following values:
-  *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
-  *            @arg RCC_IT_LSERDY: LSE ready interrupt.
-  *            @arg RCC_IT_HSIRDY: HSI ready interrupt.
-  *            @arg RCC_IT_HSERDY: HSE ready interrupt.
-  *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
-  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.  
-  *            @arg RCC_IT_CSS: Clock Security System interrupt
-  */
-#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
-
-/** @brief  Check the RCC's interrupt has occurred or not.
-  * @param  __INTERRUPT__: specifies the RCC interrupt source to check.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
-  *            @arg RCC_IT_LSERDY: LSE ready interrupt.
-  *            @arg RCC_IT_HSIRDY: HSI ready interrupt.
-  *            @arg RCC_IT_HSERDY: HSE ready interrupt.
-  *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
-  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
-  *            @arg RCC_IT_CSS: Clock Security System interrupt
-  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
-  */
-#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, 
-  *        RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
-  */
-#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
-
-/** @brief  Check RCC flag is set or not.
-  * @param  __FLAG__: specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
-  *            @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
-  *            @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
-  *            @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
-  *            @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
-  *            @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
-  *            @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
-  *            @arg RCC_FLAG_PINRST: Pin reset.
-  *            @arg RCC_FLAG_PORRST: POR/PDR reset.
-  *            @arg RCC_FLAG_SFTRST: Software reset.
-  *            @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
-  *            @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
-  *            @arg RCC_FLAG_LPWRRST: Low Power reset.
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define RCC_FLAG_MASK  ((uint8_t)0x1FU)
-#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) & ((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
-
-/**
-  * @}
-  */
-     
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
- /** @addtogroup RCC_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup RCC_Exported_Functions_Group1
-  * @{
-  */                             
-/* Initialization and de-initialization functions  ******************************/
-void HAL_RCC_DeInit(void);
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
-/**
-  * @}
-  */
-
-/** @addtogroup RCC_Exported_Functions_Group2
-  * @{
-  */
-/* Peripheral Control functions  ************************************************/
-void     HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
-void     HAL_RCC_EnableCSS(void);
-void     HAL_RCC_DisableCSS(void);
-uint32_t HAL_RCC_GetSysClockFreq(void);
-uint32_t HAL_RCC_GetHCLKFreq(void);
-uint32_t HAL_RCC_GetPCLK1Freq(void);
-uint32_t HAL_RCC_GetPCLK2Freq(void);
-void     HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
-void     HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
-
-/* CSS NMI IRQ handler */
-void HAL_RCC_NMI_IRQHandler(void);
-
-/* User Callbacks in non blocking mode (IT mode) */ 
-void HAL_RCC_CSSCallback(void);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RCC_Private_Constants RCC Private Constants
-  * @{
-  */
-
-/** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
-  * @brief RCC registers bit address in the alias region
-  * @{
-  */
-#define RCC_OFFSET                 (RCC_BASE - PERIPH_BASE)
-/* --- CR Register ---*/
-/* Alias word address of HSION bit */
-#define RCC_CR_OFFSET              (RCC_OFFSET + 0x00U)
-#define RCC_HSION_BIT_NUMBER       0x00U
-#define RCC_CR_HSION_BB            (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U))
-/* Alias word address of CSSON bit */
-#define RCC_CSSON_BIT_NUMBER       0x13U
-#define RCC_CR_CSSON_BB            (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))
-/* Alias word address of PLLON bit */
-#define RCC_PLLON_BIT_NUMBER       0x18U
-#define RCC_CR_PLLON_BB            (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))
-
-/* --- BDCR Register ---*/
-/* Alias word address of RTCEN bit */
-#define RCC_BDCR_OFFSET            (RCC_OFFSET + 0x70U)
-#define RCC_RTCEN_BIT_NUMBER       0x0FU
-#define RCC_BDCR_RTCEN_BB          (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))
-/* Alias word address of BDRST bit */
-#define RCC_BDRST_BIT_NUMBER       0x10U
-#define RCC_BDCR_BDRST_BB          (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))
-
-/* --- CSR Register ---*/
-/* Alias word address of LSION bit */
-#define RCC_CSR_OFFSET             (RCC_OFFSET + 0x74U)
-#define RCC_LSION_BIT_NUMBER        0x00U
-#define RCC_CSR_LSION_BB           (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U))
-
-/* CR register byte 3 (Bits[23:16]) base address */
-#define RCC_CR_BYTE2_ADDRESS       ((uint32_t)0x40023802U)
-
-/* CIR register byte 2 (Bits[15:8]) base address */
-#define RCC_CIR_BYTE1_ADDRESS      ((uint32_t)(RCC_BASE + 0x0CU + 0x01U))
-
-/* CIR register byte 3 (Bits[23:16]) base address */
-#define RCC_CIR_BYTE2_ADDRESS      ((uint32_t)(RCC_BASE + 0x0CU + 0x02U))
-
-/* BDCR register base address */
-#define RCC_BDCR_BYTE0_ADDRESS     (PERIPH_BASE + RCC_BDCR_OFFSET)
-
-#define RCC_DBP_TIMEOUT_VALUE      ((uint32_t)2U)
-#define RCC_LSE_TIMEOUT_VALUE      LSE_STARTUP_TIMEOUT
-
-#define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT
-#define HSI_TIMEOUT_VALUE          ((uint32_t)2U)  /* 2 ms */
-#define LSI_TIMEOUT_VALUE          ((uint32_t)2U)  /* 2 ms */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup RCC_Private_Macros RCC Private Macros
-  * @{
-  */
-    
-/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
-  * @{
-  */  
-#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U)
-
-#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
-                         ((HSE) == RCC_HSE_BYPASS))
-
-#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
-                         ((LSE) == RCC_LSE_BYPASS))
-
-#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
-
-#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
-
-#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
-
-#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
-                                  ((SOURCE) == RCC_PLLSOURCE_HSE))
-
-#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
-                                     ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
-                                     ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
-                                     ((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK))
-
-#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31))
- 
-#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U)
-
-#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U))
-
-#define IS_RCC_PLLQ_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 15U))
-
-#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1)   || ((HCLK) == RCC_SYSCLK_DIV2)   || \
-                           ((HCLK) == RCC_SYSCLK_DIV4)   || ((HCLK) == RCC_SYSCLK_DIV8)   || \
-                           ((HCLK) == RCC_SYSCLK_DIV16)  || ((HCLK) == RCC_SYSCLK_DIV64)  || \
-                           ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
-                           ((HCLK) == RCC_SYSCLK_DIV512))
-
-#define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 15U))
-
-#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
-                           ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
-                           ((PCLK) == RCC_HCLK_DIV16))
-
-#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
-
-#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
-                                   ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
-
-#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1)  || ((DIV) == RCC_MCODIV_2) || \
-                             ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
-                             ((DIV) == RCC_MCODIV_5)) 
-#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU)
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_RCC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_rcc_ex.h b/stmhal/hal/f4/inc/stm32f4xx_hal_rcc_ex.h
deleted file mode 100644
index a5f66c7c4a..0000000000
--- a/stmhal/hal/f4/inc/stm32f4xx_hal_rcc_ex.h
+++ /dev/null
@@ -1,6590 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_rcc_ex.h
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   Header file of RCC HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_RCC_EX_H
-#define __STM32F4xx_HAL_RCC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup RCCEx
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
-  * @{
-  */
-
-/**
-  * @brief  RCC PLL configuration structure definition
-  */
-typedef struct
-{
-  uint32_t PLLState;   /*!< The new state of the PLL.
-                            This parameter can be a value of @ref RCC_PLL_Config                      */
-
-  uint32_t PLLSource;  /*!< RCC_PLLSource: PLL entry clock source.
-                            This parameter must be a value of @ref RCC_PLL_Clock_Source               */
-
-  uint32_t PLLM;       /*!< PLLM: Division factor for PLL VCO input clock.
-                            This parameter must be a number between Min_Data = 0 and Max_Data = 63    */
-
-  uint32_t PLLN;       /*!< PLLN: Multiplication factor for PLL VCO output clock.
-                            This parameter must be a number between Min_Data = 50 and Max_Data = 432 
-                            except for STM32F411xE devices where the Min_Data = 192 */
-
-  uint32_t PLLP;       /*!< PLLP: Division factor for main system clock (SYSCLK).
-                            This parameter must be a value of @ref RCC_PLLP_Clock_Divider             */
-
-  uint32_t PLLQ;       /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
-                            This parameter must be a number between Min_Data = 4 and Max_Data = 15    */
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) ||\
-    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
-  uint32_t PLLR;       /*!< PLLR: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
-                            This parameter is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx
-                            and STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices. 
-                            This parameter must be a number between Min_Data = 2 and Max_Data = 7     */
-#endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ 
-}RCC_PLLInitTypeDef;
-
-#if defined(STM32F446xx)
-/** 
-  * @brief  PLLI2S Clock structure definition  
-  */
-typedef struct
-{
-  uint32_t PLLI2SM;    /*!< Specifies division factor for PLL VCO input clock.
-                            This parameter must be a number between Min_Data = 2 and Max_Data = 63       */
-
-  uint32_t PLLI2SN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
-                            This parameter must be a number between Min_Data = 50 and Max_Data = 432    */
-
-  uint32_t PLLI2SP;    /*!< Specifies division factor for SPDIFRX Clock.
-                            This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider           */
-
-  uint32_t PLLI2SQ;    /*!< Specifies the division factor for SAI clock.
-                            This parameter must be a number between Min_Data = 2 and Max_Data = 15. 
-                            This parameter will be used only when PLLI2S is selected as Clock Source SAI */
-                           
-  uint32_t PLLI2SR;    /*!< Specifies the division factor for I2S clock.
-                            This parameter must be a number between Min_Data = 2 and Max_Data = 7. 
-                            This parameter will be used only when PLLI2S is selected as Clock Source I2S */
-}RCC_PLLI2SInitTypeDef;
-
-/** 
-  * @brief  PLLSAI Clock structure definition  
-  */
-typedef struct
-{
-  uint32_t PLLSAIM;    /*!< Spcifies division factor for PLL VCO input clock.
-                            This parameter must be a number between Min_Data = 2 and Max_Data = 63       */
-
-  uint32_t PLLSAIN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
-                            This parameter must be a number between Min_Data = 50 and Max_Data = 432    */
-
-  uint32_t PLLSAIP;    /*!< Specifies division factor for OTG FS, SDIO and RNG clocks.
-                            This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider           */
-                                                             
-  uint32_t PLLSAIQ;    /*!< Specifies the division factor for SAI clock.
-                            This parameter must be a number between Min_Data = 2 and Max_Data = 15.
-                            This parameter will be used only when PLLSAI is selected as Clock Source SAI */
-}RCC_PLLSAIInitTypeDef;
-
-/** 
-  * @brief  RCC extended clocks structure definition  
-  */
-typedef struct
-{
-  uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
-                                      This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
-
-  RCC_PLLI2SInitTypeDef PLLI2S;  /*!< PLL I2S structure parameters. 
-                                      This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
-
-  RCC_PLLSAIInitTypeDef PLLSAI;  /*!< PLL SAI structure parameters. 
-                                      This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
-
-  uint32_t PLLI2SDivQ;           /*!< Specifies the PLLI2S division factor for SAI1 clock.
-                                      This parameter must be a number between Min_Data = 1 and Max_Data = 32
-                                      This parameter will be used only when PLLI2S is selected as Clock Source SAI */
-
-  uint32_t PLLSAIDivQ;           /*!< Specifies the PLLI2S division factor for SAI1 clock.
-                                      This parameter must be a number between Min_Data = 1 and Max_Data = 32
-                                      This parameter will be used only when PLLSAI is selected as Clock Source SAI */
-
-  uint32_t Sai1ClockSelection;    /*!< Specifies SAI1 Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
-
-  uint32_t Sai2ClockSelection;    /*!< Specifies SAI2 Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
-                                      
-  uint32_t I2sApb1ClockSelection;    /*!< Specifies I2S APB1 Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */
-
-  uint32_t I2sApb2ClockSelection;    /*!< Specifies I2S APB2 Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */
-
-  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Source Selection. 
-                                      This parameter can be a value of @ref RCC_RTC_Clock_Source */
-
-  uint32_t SdioClockSelection;    /*!< Specifies SDIO Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
-
-  uint32_t CecClockSelection;      /*!< Specifies CEC Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
-
-  uint32_t Fmpi2c1ClockSelection;  /*!< Specifies FMPI2C1 Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
-
-  uint32_t SpdifClockSelection;    /*!< Specifies SPDIFRX Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */
-
-  uint32_t Clk48ClockSelection;     /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. 
-                                      This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
-  
-  uint8_t TIMPresSelection;      /*!< Specifies TIM Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
-}RCC_PeriphCLKInitTypeDef;
-#endif /* STM32F446xx */   
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-/** 
-  * @brief  RCC extended clocks structure definition
-  */
-typedef struct
-{
-  uint32_t PeriphClockSelection;   /*!< The Extended Clock to be configured.
-                                      This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
-
-  uint32_t I2SClockSelection;      /*!< Specifies RTC Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_I2S_APB_Clock_Source */
-                                      
-  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Source Selection. 
-                                      This parameter can be a value of @ref RCC_RTC_Clock_Source */
-
-  uint32_t Lptim1ClockSelection;   /*!< Specifies LPTIM1 Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
-  
-  uint32_t Fmpi2c1ClockSelection;  /*!< Specifies FMPI2C1 Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
-
-  uint8_t TIMPresSelection;        /*!< Specifies TIM Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
-}RCC_PeriphCLKInitTypeDef;
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
-/** 
-  * @brief  PLLI2S Clock structure definition  
-  */
-typedef struct
-{
-  uint32_t PLLI2SM;    /*!< Specifies division factor for PLL VCO input clock.
-                            This parameter must be a number between Min_Data = 2 and Max_Data = 63       */
-
-  uint32_t PLLI2SN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
-                            This parameter must be a number between Min_Data = 50 and Max_Data = 432    */
-
-  uint32_t PLLI2SQ;    /*!< Specifies the division factor for SAI clock.
-                            This parameter must be a number between Min_Data = 2 and Max_Data = 15. 
-                            This parameter will be used only when PLLI2S is selected as Clock Source SAI */
-                           
-  uint32_t PLLI2SR;    /*!< Specifies the division factor for I2S clock.
-                            This parameter must be a number between Min_Data = 2 and Max_Data = 7. 
-                            This parameter will be used only when PLLI2S is selected as Clock Source I2S */
-}RCC_PLLI2SInitTypeDef;
-
-/** 
-  * @brief  RCC extended clocks structure definition
-  */
-typedef struct
-{
-  uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
-                                      This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
-
-  RCC_PLLI2SInitTypeDef PLLI2S;  /*!< PLL I2S structure parameters. 
-                                      This parameter will be used only when PLLI2S is selected as Clock Source I2S */
-                                      
-  uint32_t I2sApb1ClockSelection;    /*!< Specifies I2S APB1 Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */
-
-  uint32_t I2sApb2ClockSelection;    /*!< Specifies I2S APB2 Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */
-
-  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Source Selection. 
-                                      This parameter can be a value of @ref RCC_RTC_Clock_Source */
-
-  uint32_t SdioClockSelection;    /*!< Specifies SDIO Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
-
-  uint32_t Fmpi2c1ClockSelection;  /*!< Specifies FMPI2C1 Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
-
-  uint32_t Clk48ClockSelection;     /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
-                                      This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
-  
-  uint32_t Dfsdm1ClockSelection;    /*!< Specifies DFSDM1 Clock Selection.
-                                      This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */
-
-  uint32_t Dfsdm1AudioClockSelection;/*!< Specifies DFSDM1 Audio Clock Selection.
-                                      This parameter can be a value of @ref RCCEx_DFSDM1_Audio_Clock_Source */
-
-  uint32_t PLLI2SSelection;      /*!< Specifies PLL I2S Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_PLL_I2S_Clock_Source */
-
-  uint8_t TIMPresSelection;      /*!< Specifies TIM Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
-}RCC_PeriphCLKInitTypeDef;
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-
-/** 
-  * @brief  PLLI2S Clock structure definition  
-  */
-typedef struct
-{
-  uint32_t PLLI2SN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
-                            This parameter must be a number between Min_Data = 50 and Max_Data = 432.
-                            This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
-
-  uint32_t PLLI2SR;    /*!< Specifies the division factor for I2S clock.
-                            This parameter must be a number between Min_Data = 2 and Max_Data = 7. 
-                            This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
-
-  uint32_t PLLI2SQ;    /*!< Specifies the division factor for SAI1 clock.
-                            This parameter must be a number between Min_Data = 2 and Max_Data = 15. 
-                            This parameter will be used only when PLLI2S is selected as Clock Source SAI */
-}RCC_PLLI2SInitTypeDef;
-
-/** 
-  * @brief  PLLSAI Clock structure definition  
-  */
-typedef struct
-{
-  uint32_t PLLSAIN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
-                            This parameter must be a number between Min_Data = 50 and Max_Data = 432.
-                            This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ 
-#if defined(STM32F469xx) || defined(STM32F479xx)
-  uint32_t PLLSAIP;    /*!< Specifies division factor for OTG FS and SDIO clocks.
-                            This parameter is only available in STM32F469xx/STM32F479xx devices.
-                            This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider  */  
-#endif /* STM32F469xx || STM32F479xx */
-                                 
-  uint32_t PLLSAIQ;    /*!< Specifies the division factor for SAI1 clock.
-                            This parameter must be a number between Min_Data = 2 and Max_Data = 15.
-                            This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
-                              
-  uint32_t PLLSAIR;    /*!< specifies the division factor for LTDC clock
-                            This parameter must be a number between Min_Data = 2 and Max_Data = 7.
-                            This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
-
-}RCC_PLLSAIInitTypeDef;
-
-/** 
-  * @brief  RCC extended clocks structure definition  
-  */
-typedef struct
-{
-  uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
-                                      This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
-
-  RCC_PLLI2SInitTypeDef PLLI2S;  /*!< PLL I2S structure parameters. 
-                                      This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
-
-  RCC_PLLSAIInitTypeDef PLLSAI;  /*!< PLL SAI structure parameters. 
-                                      This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
-
-  uint32_t PLLI2SDivQ;           /*!< Specifies the PLLI2S division factor for SAI1 clock.
-                                      This parameter must be a number between Min_Data = 1 and Max_Data = 32
-                                      This parameter will be used only when PLLI2S is selected as Clock Source SAI */
-
-  uint32_t PLLSAIDivQ;           /*!< Specifies the PLLI2S division factor for SAI1 clock.
-                                      This parameter must be a number between Min_Data = 1 and Max_Data = 32
-                                      This parameter will be used only when PLLSAI is selected as Clock Source SAI */
-
-  uint32_t PLLSAIDivR;           /*!< Specifies the PLLSAI division factor for LTDC clock.
-                                      This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
-
-  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection. 
-                                      This parameter can be a value of @ref RCC_RTC_Clock_Source */
-
-  uint8_t TIMPresSelection;      /*!< Specifies TIM Clock Prescalers Selection. 
-                                      This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
-#if defined(STM32F469xx) || defined(STM32F479xx)
-  uint32_t Clk48ClockSelection;  /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. 
-                                      This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
-
-  uint32_t SdioClockSelection;   /*!< Specifies SDIO Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */  
-#endif /* STM32F469xx || STM32F479xx */  
-}RCC_PeriphCLKInitTypeDef;
-
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
-/** 
-  * @brief  PLLI2S Clock structure definition  
-  */
-typedef struct
-{
-#if defined(STM32F411xE)
-  uint32_t PLLI2SM;    /*!< PLLM: Division factor for PLLI2S VCO input clock.
-                            This parameter must be a number between Min_Data = 2 and Max_Data = 62  */
-#endif /* STM32F411xE */
-                                
-  uint32_t PLLI2SN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
-                            This parameter must be a number between Min_Data = 50 and Max_Data = 432
-                            Except for STM32F411xE devices where the Min_Data = 192. 
-                            This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
-
-  uint32_t PLLI2SR;    /*!< Specifies the division factor for I2S clock.
-                            This parameter must be a number between Min_Data = 2 and Max_Data = 7. 
-                            This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
-
-}RCC_PLLI2SInitTypeDef;
- 
-/** 
-  * @brief  RCC extended clocks structure definition  
-  */
-typedef struct
-{
-  uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
-                                      This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
-
-  RCC_PLLI2SInitTypeDef PLLI2S;  /*!< PLL I2S structure parameters.
-                                      This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
-
-  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection.
-                                       This parameter can be a value of @ref RCC_RTC_Clock_Source */
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 
-  uint8_t TIMPresSelection;        /*!< Specifies TIM Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
-#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
-}RCC_PeriphCLKInitTypeDef;
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
-/**
-  * @}
-  */ 
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
-  * @{
-  */
-
-/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
-  * @{
-  */
-/* Peripheral Clock source for STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx */
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
-#define RCC_PERIPHCLK_I2S_APB1        ((uint32_t)0x00000001U)
-#define RCC_PERIPHCLK_I2S_APB2        ((uint32_t)0x00000002U)
-#define RCC_PERIPHCLK_TIM             ((uint32_t)0x00000004U)
-#define RCC_PERIPHCLK_RTC             ((uint32_t)0x00000008U)
-#define RCC_PERIPHCLK_FMPI2C1         ((uint32_t)0x00000010U)
-#define RCC_PERIPHCLK_CLK48           ((uint32_t)0x00000020U)
-#define RCC_PERIPHCLK_SDIO            ((uint32_t)0x00000040U)
-#define RCC_PERIPHCLK_PLLI2S          ((uint32_t)0x00000080U)
-#define RCC_PERIPHCLK_DFSDM1          ((uint32_t)0x00000100U)
-#define RCC_PERIPHCLK_DFSDM1_AUDIO    ((uint32_t)0x00000200U)
-#endif /* STM32F412Zx || STM32F412Vx) || STM32F412Rx || STM32F412Cx */
-/*----------------------------------------------------------------------------*/
-
-/*------------------- Peripheral Clock source for STM32F410xx ----------------*/
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-#define RCC_PERIPHCLK_I2S             ((uint32_t)0x00000001U)
-#define RCC_PERIPHCLK_TIM             ((uint32_t)0x00000002U)
-#define RCC_PERIPHCLK_RTC             ((uint32_t)0x00000004U)
-#define RCC_PERIPHCLK_FMPI2C1         ((uint32_t)0x00000008U)
-#define RCC_PERIPHCLK_LPTIM1          ((uint32_t)0x00000010U)
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-/*----------------------------------------------------------------------------*/
-
-/*------------------- Peripheral Clock source for STM32F446xx ----------------*/
-#if defined(STM32F446xx)
-#define RCC_PERIPHCLK_I2S_APB1        ((uint32_t)0x00000001U)
-#define RCC_PERIPHCLK_I2S_APB2        ((uint32_t)0x00000002U)
-#define RCC_PERIPHCLK_SAI1            ((uint32_t)0x00000004U)
-#define RCC_PERIPHCLK_SAI2            ((uint32_t)0x00000008U)
-#define RCC_PERIPHCLK_TIM             ((uint32_t)0x00000010U)
-#define RCC_PERIPHCLK_RTC             ((uint32_t)0x00000020U)
-#define RCC_PERIPHCLK_CEC             ((uint32_t)0x00000040U)
-#define RCC_PERIPHCLK_FMPI2C1         ((uint32_t)0x00000080U)
-#define RCC_PERIPHCLK_CLK48            ((uint32_t)0x00000100U)
-#define RCC_PERIPHCLK_SDIO            ((uint32_t)0x00000200U)
-#define RCC_PERIPHCLK_SPDIFRX         ((uint32_t)0x00000400U)
-#define RCC_PERIPHCLK_PLLI2S          ((uint32_t)0x00000800U)
-#endif /* STM32F446xx */
-/*-----------------------------------------------------------------------------*/
-    
-/*----------- Peripheral Clock source for STM32F469xx/STM32F479xx -------------*/
-#if defined(STM32F469xx) || defined(STM32F479xx)
-#define RCC_PERIPHCLK_I2S             ((uint32_t)0x00000001U)
-#define RCC_PERIPHCLK_SAI_PLLI2S      ((uint32_t)0x00000002U)
-#define RCC_PERIPHCLK_SAI_PLLSAI      ((uint32_t)0x00000004U)
-#define RCC_PERIPHCLK_LTDC            ((uint32_t)0x00000008U)
-#define RCC_PERIPHCLK_TIM             ((uint32_t)0x00000010U)
-#define RCC_PERIPHCLK_RTC             ((uint32_t)0x00000020U)
-#define RCC_PERIPHCLK_PLLI2S          ((uint32_t)0x00000040U)
-#define RCC_PERIPHCLK_CLK48            ((uint32_t)0x00000080U)
-#define RCC_PERIPHCLK_SDIO            ((uint32_t)0x00000100U)
-#endif /* STM32F469xx || STM32F479xx */
-/*----------------------------------------------------------------------------*/
-
-/*-------- Peripheral Clock source for STM32F42xxx/STM32F43xxx ---------------*/
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
-#define RCC_PERIPHCLK_I2S             ((uint32_t)0x00000001U)
-#define RCC_PERIPHCLK_SAI_PLLI2S      ((uint32_t)0x00000002U)
-#define RCC_PERIPHCLK_SAI_PLLSAI      ((uint32_t)0x00000004U)
-#define RCC_PERIPHCLK_LTDC            ((uint32_t)0x00000008U)
-#define RCC_PERIPHCLK_TIM             ((uint32_t)0x00000010U)
-#define RCC_PERIPHCLK_RTC             ((uint32_t)0x00000020U)
-#define RCC_PERIPHCLK_PLLI2S          ((uint32_t)0x00000040U)
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
-/*----------------------------------------------------------------------------*/
-
-/*-------- Peripheral Clock source for STM32F40xxx/STM32F41xxx ---------------*/
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 
-#define RCC_PERIPHCLK_I2S             ((uint32_t)0x00000001U)
-#define RCC_PERIPHCLK_RTC             ((uint32_t)0x00000002U)
-#define RCC_PERIPHCLK_PLLI2S          ((uint32_t)0x00000004U)
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
-#define RCC_PERIPHCLK_TIM            ((uint32_t)0x00000008U)
-#endif /* STM32F401xC || STM32F401xE || STM32F411xE */      
-/*----------------------------------------------------------------------------*/
-/**
-  * @}
-  */
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
-    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
-    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
-    defined(STM32F412Rx) || defined(STM32F412Cx)
-/** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source
-  * @{
-  */
-#define RCC_I2SCLKSOURCE_PLLI2S         ((uint32_t)0x00000000U)
-#define RCC_I2SCLKSOURCE_EXT            ((uint32_t)0x00000001U)
-/**
-  * @}
-  */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
-          STM32F412Rx || STM32F412Cx */
-
-/** @defgroup RCCEx_PLLSAI_DIVR RCC PLLSAI DIVR
-  * @{
-  */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx) 
-#define RCC_PLLSAIDIVR_2                ((uint32_t)0x00000000U)
-#define RCC_PLLSAIDIVR_4                ((uint32_t)0x00010000U)
-#define RCC_PLLSAIDIVR_8                ((uint32_t)0x00020000U)
-#define RCC_PLLSAIDIVR_16               ((uint32_t)0x00030000U)
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCC PLLI2SP Clock Divider
-  * @{
-  */
-#if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
-    defined(STM32F412Rx) || defined(STM32F412Cx)
-#define RCC_PLLI2SP_DIV2                  ((uint32_t)0x00000002U)
-#define RCC_PLLI2SP_DIV4                  ((uint32_t)0x00000004U)
-#define RCC_PLLI2SP_DIV6                  ((uint32_t)0x00000006U)
-#define RCC_PLLI2SP_DIV8                  ((uint32_t)0x00000008U)
-#endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCC PLLSAIP Clock Divider
-  * @{
-  */
-#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 
-#define RCC_PLLSAIP_DIV2                  ((uint32_t)0x00000002U)
-#define RCC_PLLSAIP_DIV4                  ((uint32_t)0x00000004U)
-#define RCC_PLLSAIP_DIV6                  ((uint32_t)0x00000006U)
-#define RCC_PLLSAIP_DIV8                  ((uint32_t)0x00000008U)
-#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
-/**
-  * @}
-  */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-/** @defgroup RCCEx_SAI_BlockA_Clock_Source  RCC SAI BlockA Clock Source
-  * @{
-  */
-#define RCC_SAIACLKSOURCE_PLLSAI             ((uint32_t)0x00000000U)
-#define RCC_SAIACLKSOURCE_PLLI2S             ((uint32_t)0x00100000U)
-#define RCC_SAIACLKSOURCE_EXT                ((uint32_t)0x00200000U)
-/**
-  * @}
-  */ 
-
-/** @defgroup RCCEx_SAI_BlockB_Clock_Source  RCC SAI BlockB Clock Source
-  * @{
-  */
-#define RCC_SAIBCLKSOURCE_PLLSAI             ((uint32_t)0x00000000U)
-#define RCC_SAIBCLKSOURCE_PLLI2S             ((uint32_t)0x00400000U)
-#define RCC_SAIBCLKSOURCE_EXT                ((uint32_t)0x00800000U)
-/**
-  * @}
-  */ 
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-      
-#if defined(STM32F469xx) || defined(STM32F479xx)
-/** @defgroup RCCEx_CLK48_Clock_Source  RCC CLK48 Clock Source
-  * @{
-  */
-#define RCC_CLK48CLKSOURCE_PLLQ              ((uint32_t)0x00000000U)
-#define RCC_CLK48CLKSOURCE_PLLSAIP           ((uint32_t)RCC_DCKCFGR_CK48MSEL)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_SDIO_Clock_Source  RCC SDIO Clock Source
-  * @{
-  */
-#define RCC_SDIOCLKSOURCE_CLK48             ((uint32_t)0x00000000U)
-#define RCC_SDIOCLKSOURCE_SYSCLK            ((uint32_t)RCC_DCKCFGR_SDIOSEL)
-/**
-  * @}
-  */    
-  
-/** @defgroup RCCEx_DSI_Clock_Source  RCC DSI Clock Source
-  * @{
-  */
-#define RCC_DSICLKSOURCE_DSIPHY             ((uint32_t)0x00000000U)
-#define RCC_DSICLKSOURCE_PLLR               ((uint32_t)RCC_DCKCFGR_DSISEL)
-/**
-  * @}
-  */
-#endif /* STM32F469xx || STM32F479xx */
-
-#if defined(STM32F446xx)
-/** @defgroup RCCEx_SAI1_Clock_Source RCC SAI1 Clock Source 
-  * @{
-  */
-#define RCC_SAI1CLKSOURCE_PLLSAI             ((uint32_t)0x00000000U)
-#define RCC_SAI1CLKSOURCE_PLLI2S             ((uint32_t)RCC_DCKCFGR_SAI1SRC_0)
-#define RCC_SAI1CLKSOURCE_PLLR               ((uint32_t)RCC_DCKCFGR_SAI1SRC_1)
-#define RCC_SAI1CLKSOURCE_EXT                ((uint32_t)RCC_DCKCFGR_SAI1SRC)
-/**
-  * @}
-  */ 
-
-/** @defgroup RCCEx_SAI2_Clock_Source  RCC SAI2 Clock Source
-  * @{
-  */
-#define RCC_SAI2CLKSOURCE_PLLSAI             ((uint32_t)0x00000000U)
-#define RCC_SAI2CLKSOURCE_PLLI2S             ((uint32_t)RCC_DCKCFGR_SAI2SRC_0)
-#define RCC_SAI2CLKSOURCE_PLLR               ((uint32_t)RCC_DCKCFGR_SAI2SRC_1)
-#define RCC_SAI2CLKSOURCE_PLLSRC             ((uint32_t)RCC_DCKCFGR_SAI2SRC)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_I2SAPB1_Clock_Source  RCC I2S APB1 Clock Source
-  * @{
-  */
-#define RCC_I2SAPB1CLKSOURCE_PLLI2S          ((uint32_t)0x00000000U)
-#define RCC_I2SAPB1CLKSOURCE_EXT             ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
-#define RCC_I2SAPB1CLKSOURCE_PLLR            ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
-#define RCC_I2SAPB1CLKSOURCE_PLLSRC          ((uint32_t)RCC_DCKCFGR_I2S1SRC)
-/**
-  * @}
-  */ 
-
-/** @defgroup RCCEx_I2SAPB2_Clock_Source  RCC I2S APB2 Clock Source
-  * @{
-  */
-#define RCC_I2SAPB2CLKSOURCE_PLLI2S          ((uint32_t)0x00000000U)
-#define RCC_I2SAPB2CLKSOURCE_EXT             ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
-#define RCC_I2SAPB2CLKSOURCE_PLLR            ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
-#define RCC_I2SAPB2CLKSOURCE_PLLSRC          ((uint32_t)RCC_DCKCFGR_I2S2SRC)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_FMPI2C1_Clock_Source  RCC FMPI2C1 Clock Source
-  * @{
-  */
-#define RCC_FMPI2C1CLKSOURCE_APB                ((uint32_t)0x00000000U)
-#define RCC_FMPI2C1CLKSOURCE_SYSCLK             ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
-#define RCC_FMPI2C1CLKSOURCE_HSI                ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_CEC_Clock_Source  RCC CEC Clock Source
-  * @{
-  */
-#define RCC_CECCLKSOURCE_HSI                ((uint32_t)0x00000000U)
-#define RCC_CECCLKSOURCE_LSE                ((uint32_t)RCC_DCKCFGR2_CECSEL)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_CLK48_Clock_Source  RCC CLK48 Clock Source
-  * @{
-  */
-#define RCC_CLK48CLKSOURCE_PLLQ              ((uint32_t)0x00000000U)
-#define RCC_CLK48CLKSOURCE_PLLSAIP           ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_SDIO_Clock_Source  RCC SDIO Clock Source
-  * @{
-  */
-#define RCC_SDIOCLKSOURCE_CLK48             ((uint32_t)0x00000000U)
-#define RCC_SDIOCLKSOURCE_SYSCLK            ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_SPDIFRX_Clock_Source   RCC SPDIFRX Clock Source
-  * @{
-  */
-#define RCC_SPDIFRXCLKSOURCE_PLLR             ((uint32_t)0x00000000U)
-#define RCC_SPDIFRXCLKSOURCE_PLLI2SP          ((uint32_t)RCC_DCKCFGR2_SPDIFRXSEL)
-/**
-  * @}
-  */
-
-#endif /* STM32F446xx */
-
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
-/** @defgroup RCCEx_PLL_I2S_Clock_Source PLL I2S Clock Source
-  * @{
-  */
-#define RCC_PLLI2SCLKSOURCE_PLLSRC         ((uint32_t)0x00000000U)
-#define RCC_PLLI2SCLKSOURCE_EXT            ((uint32_t)RCC_PLLI2SCFGR_PLLI2SSRC)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_DFSDM1_Audio_Clock_Source  RCC DFSDM1 Audio Clock Source
-  * @{
-  */
-#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1         ((uint32_t)0x00000000U)
-#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2         ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source  RCC DFSDM1 Kernel Clock Source
-  * @{
-  */
-#define RCC_DFSDM1CLKSOURCE_APB2         ((uint32_t)0x00000000U)
-#define RCC_DFSDM1CLKSOURCE_SYSCLK       ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_I2SAPB1_Clock_Source  RCC I2S APB1 Clock Source
-  * @{
-  */
-#define RCC_I2SAPB1CLKSOURCE_PLLI2S          ((uint32_t)0x00000000U)
-#define RCC_I2SAPB1CLKSOURCE_EXT             ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
-#define RCC_I2SAPB1CLKSOURCE_PLLR            ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
-#define RCC_I2SAPB1CLKSOURCE_PLLSRC          ((uint32_t)RCC_DCKCFGR_I2S1SRC)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_I2SAPB2_Clock_Source  RCC I2S APB2 Clock Source
-  * @{
-  */
-#define RCC_I2SAPB2CLKSOURCE_PLLI2S          ((uint32_t)0x00000000U)
-#define RCC_I2SAPB2CLKSOURCE_EXT             ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
-#define RCC_I2SAPB2CLKSOURCE_PLLR            ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
-#define RCC_I2SAPB2CLKSOURCE_PLLSRC          ((uint32_t)RCC_DCKCFGR_I2S2SRC)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_FMPI2C1_Clock_Source  RCC FMPI2C1 Clock Source
-  * @{
-  */
-#define RCC_FMPI2C1CLKSOURCE_APB                ((uint32_t)0x00000000U)
-#define RCC_FMPI2C1CLKSOURCE_SYSCLK             ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
-#define RCC_FMPI2C1CLKSOURCE_HSI                ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_CLK48_Clock_Source  RCC CLK48 Clock Source
-  * @{
-  */
-#define RCC_CLK48CLKSOURCE_PLLQ              ((uint32_t)0x00000000U)
-#define RCC_CLK48CLKSOURCE_PLLI2SQ           ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_SDIO_Clock_Source  RCC SDIO Clock Source
-  * @{
-  */
-#define RCC_SDIOCLKSOURCE_CLK48             ((uint32_t)0x00000000U)
-#define RCC_SDIOCLKSOURCE_SYSCLK            ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
-/**
-  * @}
-  */
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-
-/** @defgroup RCCEx_I2S_APB_Clock_Source  RCC I2S APB Clock Source
-  * @{
-  */
-#define RCC_I2SAPBCLKSOURCE_PLLR            ((uint32_t)0x00000000U)
-#define RCC_I2SAPBCLKSOURCE_EXT             ((uint32_t)RCC_DCKCFGR_I2SSRC_0)
-#define RCC_I2SAPBCLKSOURCE_PLLSRC          ((uint32_t)RCC_DCKCFGR_I2SSRC_1)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_FMPI2C1_Clock_Source  RCC FMPI2C1 Clock Source
-  * @{
-  */
-#define RCC_FMPI2C1CLKSOURCE_APB                ((uint32_t)0x00000000U)
-#define RCC_FMPI2C1CLKSOURCE_SYSCLK             ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
-#define RCC_FMPI2C1CLKSOURCE_HSI                ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_LPTIM1_Clock_Source  RCC LPTIM1 Clock Source
-  * @{
-  */
-#define RCC_LPTIM1CLKSOURCE_PCLK            ((uint32_t)0x00000000U)
-#define RCC_LPTIM1CLKSOURCE_HSI            ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
-#define RCC_LPTIM1CLKSOURCE_LSI            ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
-#define RCC_LPTIM1CLKSOURCE_LSE            ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1)
-/**
-  * @}
-  */
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
-    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
-    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
-    defined(STM32F412Cx)
-/** @defgroup RCCEx_TIM_PRescaler_Selection  RCC TIM PRescaler Selection
-  * @{
-  */
-#define RCC_TIMPRES_DESACTIVATED        ((uint8_t)0x00U)
-#define RCC_TIMPRES_ACTIVATED           ((uint8_t)0x01U)
-/**
-  * @}
-  */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
-          STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
-          STM32F412Vx || STM32F412Rx || STM32F412Cx */
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\
-    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
-    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
-/** @defgroup RCCEx_LSE_Dual_Mode_Selection  RCC LSE Dual Mode Selection
-  * @{
-  */
-#define RCC_LSE_LOWPOWER_MODE           ((uint8_t)0x00U)
-#define RCC_LSE_HIGHDRIVE_MODE          ((uint8_t)0x01U)
-/**
-  * @}
-  */
-#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||\
-          STM32F412Rx || STM32F412Cx */
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
-    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
-    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
-    defined(STM32F412Rx)  
-/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
-  * @{
-  */
-#define RCC_MCO2SOURCE_SYSCLK            ((uint32_t)0x00000000U)
-#define RCC_MCO2SOURCE_PLLI2SCLK         RCC_CFGR_MCO2_0
-#define RCC_MCO2SOURCE_HSE               RCC_CFGR_MCO2_1
-#define RCC_MCO2SOURCE_PLLCLK            RCC_CFGR_MCO2
-/**
-  * @}
-  */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
-          STM32F412Rx */
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
-  * @{
-  */
-#define RCC_MCO2SOURCE_SYSCLK            ((uint32_t)0x00000000U)
-#define RCC_MCO2SOURCE_I2SCLK            RCC_CFGR_MCO2_0
-#define RCC_MCO2SOURCE_HSE               RCC_CFGR_MCO2_1
-#define RCC_MCO2SOURCE_PLLCLK            RCC_CFGR_MCO2
-/**
-  * @}
-  */
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-
-/**
-  * @}
-  */
-     
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
-  * @{
-  */
-/*------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx --------*/
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
-  * @brief  Enables or disables the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0)
-#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0)
-#define __HAL_RCC_CRC_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0)
-#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0)
-#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0)
-#define __HAL_RCC_GPIOI_CLK_ENABLE()    do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0)
-#define __HAL_RCC_GPIOF_CLK_ENABLE()    do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0)
-#define __HAL_RCC_GPIOG_CLK_ENABLE()    do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0)
-#define __HAL_RCC_GPIOJ_CLK_ENABLE()    do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0)
-#define __HAL_RCC_GPIOK_CLK_ENABLE()    do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0)
-#define __HAL_RCC_DMA2D_CLK_ENABLE()    do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0)
-#define __HAL_RCC_ETHMAC_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0)
-#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0)
-#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
-                                         UNUSED(tmpreg); \
-                                         } while(0)
-#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
-                                         __IO uint32_t tmpreg = 0x00U; \
-                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
-                                         /* Delay after an RCC peripheral clock enabling */ \
-                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
-                                         UNUSED(tmpreg); \
-                                         } while(0)
-#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0)
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0)
-#define __HAL_RCC_GPIOD_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
-#define __HAL_RCC_GPIOE_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
-#define __HAL_RCC_GPIOF_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
-#define __HAL_RCC_GPIOG_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
-#define __HAL_RCC_GPIOI_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
-#define __HAL_RCC_GPIOJ_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
-#define __HAL_RCC_GPIOK_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
-#define __HAL_RCC_DMA2D_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
-#define __HAL_RCC_ETHMAC_CLK_DISABLE()          (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
-#define __HAL_RCC_ETHMACTX_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
-#define __HAL_RCC_ETHMACRX_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
-#define __HAL_RCC_ETHMACPTP_CLK_DISABLE()       (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
-#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()      (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
-#define __HAL_RCC_BKPSRAM_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
-#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
-#define __HAL_RCC_CRC_CLK_DISABLE()             (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
-
-/**
-  * @brief  Enable ETHERNET clock.
-  */
-#define __HAL_RCC_ETH_CLK_ENABLE() do {                                     \
-                                        __HAL_RCC_ETHMAC_CLK_ENABLE();      \
-                                        __HAL_RCC_ETHMACTX_CLK_ENABLE();    \
-                                        __HAL_RCC_ETHMACRX_CLK_ENABLE();    \
-                                      } while(0)
-/**
-  * @brief  Disable ETHERNET clock.
-  */
-#define __HAL_RCC_ETH_CLK_DISABLE()  do {                                      \
-                                          __HAL_RCC_ETHMACTX_CLK_DISABLE();    \
-                                          __HAL_RCC_ETHMACRX_CLK_DISABLE();    \
-                                          __HAL_RCC_ETHMAC_CLK_DISABLE();      \
-                                        } while(0)
-/**
-  * @}
-  */
-  
-/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 
-#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 
-#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) 
-#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
-#define __HAL_RCC_GPIOI_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET) 
-#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET) 
-#define __HAL_RCC_GPIOK_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)
-#define __HAL_RCC_DMA2D_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET) 
-#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED()          ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET) 
-#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
-#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
-#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
-#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED()      ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
-#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
-#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED()         ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
-#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) 
-#define __HAL_RCC_CRC_IS_CLK_ENABLED()             ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
-#define __HAL_RCC_ETH_IS_CLK_ENABLED()             (__HAL_RCC_ETHMAC_IS_CLK_ENABLED()   && \
-                                                    __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
-                                                    __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) 
-
-#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 
-#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 
-#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) 
-#define __HAL_RCC_GPIOG_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
-#define __HAL_RCC_GPIOI_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET) 
-#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET) 
-#define __HAL_RCC_GPIOK_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)
-#define __HAL_RCC_DMA2D_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET) 
-#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED()          ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET) 
-#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
-#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
-#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
-#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED()      ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
-#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
-#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED()         ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
-#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) 
-#define __HAL_RCC_CRC_IS_CLK_DISABLED()             ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
-#define __HAL_RCC_ETH_IS_CLK_DISABLED()             (__HAL_RCC_ETHMAC_IS_CLK_DISABLED()   && \
-                                                     __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
-                                                     __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
-/**
-  * @}
-  */
-  
-/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the AHB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{
-  */
- #define __HAL_RCC_DCMI_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_DCMI_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
-
-#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx)
-#define __HAL_RCC_CRYP_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_HASH_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_CRYP_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
-#define __HAL_RCC_HASH_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
-#endif /* STM32F437xx || STM32F439xx || STM32F479xx */
-
-#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()  do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
-                                               __HAL_RCC_SYSCFG_CLK_ENABLE();\
-                                              }while(0)
-                                        
-#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
-
-#define __HAL_RCC_RNG_CLK_ENABLE()    do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_RNG_CLK_DISABLE()   (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
-/**
-  * @}
-  */
-  
-/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */ 
-#define __HAL_RCC_DCMI_IS_CLK_ENABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
-#define __HAL_RCC_DCMI_IS_CLK_DISABLED()       ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
-
-#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx)
-#define __HAL_RCC_CRYP_IS_CLK_ENABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
-#define __HAL_RCC_CRYP_IS_CLK_DISABLED()       ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
-
-#define __HAL_RCC_HASH_IS_CLK_ENABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
-#define __HAL_RCC_HASH_IS_CLK_DISABLED()       ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
-#endif /* STM32F437xx || STM32F439xx || STM32F479xx */
-
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
-
-#define __HAL_RCC_RNG_IS_CLK_ENABLED()         ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) 
-#define __HAL_RCC_RNG_IS_CLK_DISABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)     
-/**
-  * @}
-  */   
-
-/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
-  * @brief  Enables or disables the AHB3 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{  
-  */
-#define __HAL_RCC_FMC_CLK_ENABLE()    do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_FMC_CLK_DISABLE()  (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
-#if defined(STM32F469xx) || defined(STM32F479xx)
-#define __HAL_RCC_QSPI_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_QSPI_CLK_DISABLE()  (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
-#endif /* STM32F469xx || STM32F479xx */
-/**
-  * @}
-  */
-
-
-/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB3 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_FMC_IS_CLK_ENABLED()   ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
-#define __HAL_RCC_FMC_IS_CLK_DISABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
-#if defined(STM32F469xx) || defined(STM32F479xx)
-#define __HAL_RCC_QSPI_IS_CLK_ENABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
-#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
-#endif /* STM32F469xx || STM32F479xx */  
-/**
-  * @}
-  */
-    
-/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TIM7_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TIM12_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TIM13_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TIM14_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TIM14_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_USART3_CLK_ENABLE() do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_UART4_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_UART5_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_CAN1_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_CAN2_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_DAC_CLK_ENABLE()    do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_UART7_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_UART8_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TIM2_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TIM3_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TIM4_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_SPI3_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_I2C3_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
-#define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
-#define __HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
-#define __HAL_RCC_SPI3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
-#define __HAL_RCC_I2C3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
-#define __HAL_RCC_TIM6_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
-#define __HAL_RCC_TIM7_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
-#define __HAL_RCC_TIM12_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
-#define __HAL_RCC_TIM13_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
-#define __HAL_RCC_TIM14_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
-#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
-#define __HAL_RCC_UART4_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
-#define __HAL_RCC_UART5_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
-#define __HAL_RCC_CAN1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
-#define __HAL_RCC_CAN2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
-#define __HAL_RCC_DAC_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
-#define __HAL_RCC_UART7_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
-#define __HAL_RCC_UART8_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the APB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_TIM2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)  
-#define __HAL_RCC_TIM3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 
-#define __HAL_RCC_TIM4_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
-#define __HAL_RCC_SPI3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 
-#define __HAL_RCC_I2C3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
-#define __HAL_RCC_TIM6_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 
-#define __HAL_RCC_TIM7_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) 
-#define __HAL_RCC_TIM12_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) 
-#define __HAL_RCC_TIM13_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)  
-#define __HAL_RCC_TIM14_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 
-#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) 
-#define __HAL_RCC_UART4_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) 
-#define __HAL_RCC_UART5_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) 
-#define __HAL_RCC_CAN1_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
-#define __HAL_RCC_CAN2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
-#define __HAL_RCC_DAC_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 
-#define __HAL_RCC_UART7_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
-#define __HAL_RCC_UART8_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET) 
-
-#define __HAL_RCC_TIM2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)  
-#define __HAL_RCC_TIM3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 
-#define __HAL_RCC_TIM4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
-#define __HAL_RCC_SPI3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 
-#define __HAL_RCC_I2C3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
-#define __HAL_RCC_TIM6_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 
-#define __HAL_RCC_TIM7_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) 
-#define __HAL_RCC_TIM12_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) 
-#define __HAL_RCC_TIM13_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)  
-#define __HAL_RCC_TIM14_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) 
-#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) 
-#define __HAL_RCC_UART4_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) 
-#define __HAL_RCC_UART5_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) 
-#define __HAL_RCC_CAN1_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
-#define __HAL_RCC_CAN2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
-#define __HAL_RCC_DAC_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 
-#define __HAL_RCC_UART7_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
-#define __HAL_RCC_UART8_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET) 
-/**
-  * @}
-  */
-    
-/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_TIM8_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_ADC2_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_ADC3_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_SPI5_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_SPI6_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_SAI1_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_SDIO_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_SPI4_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TIM10_CLK_ENABLE()    do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_SDIO_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
-#define __HAL_RCC_SPI4_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
-#define __HAL_RCC_TIM10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
-#define __HAL_RCC_TIM8_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
-#define __HAL_RCC_ADC2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
-#define __HAL_RCC_ADC3_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
-#define __HAL_RCC_SPI5_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
-#define __HAL_RCC_SPI6_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
-#define __HAL_RCC_SAI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
-
-#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-#define __HAL_RCC_LTDC_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
-#endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F469xx) || defined(STM32F479xx)
-#define __HAL_RCC_DSI_CLK_ENABLE() do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN))
-#endif /* STM32F469xx || STM32F479xx */
-/**
-  * @}
-  */
-  
-/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the APB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */  
-#define __HAL_RCC_TIM8_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
-#define __HAL_RCC_ADC2_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
-#define __HAL_RCC_ADC3_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) 
-#define __HAL_RCC_SPI5_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) 
-#define __HAL_RCC_SPI6_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET) 
-#define __HAL_RCC_SAI1_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) 
-#define __HAL_RCC_SDIO_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
-#define __HAL_RCC_SPI4_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
-#define __HAL_RCC_TIM10_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))!= RESET)  
-
-#define __HAL_RCC_SDIO_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
-#define __HAL_RCC_SPI4_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
-#define __HAL_RCC_TIM10_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))== RESET)
-#define __HAL_RCC_TIM8_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
-#define __HAL_RCC_ADC2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
-#define __HAL_RCC_ADC3_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
-#define __HAL_RCC_SPI5_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
-#define __HAL_RCC_SPI6_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)
-#define __HAL_RCC_SAI1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
-
-#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-#define __HAL_RCC_LTDC_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET)
-#define __HAL_RCC_LTDC_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET)
-#endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F469xx) || defined(STM32F479xx)
-#define __HAL_RCC_DSI_IS_CLK_ENABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET)
-#define __HAL_RCC_DSI_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET)
-#endif /* STM32F469xx || STM32F479xx */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 
-  * @brief  Force or release AHB1 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_GPIOD_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
-#define __HAL_RCC_GPIOE_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
-#define __HAL_RCC_GPIOF_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
-#define __HAL_RCC_GPIOG_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
-#define __HAL_RCC_GPIOI_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
-#define __HAL_RCC_ETHMAC_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
-#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
-#define __HAL_RCC_GPIOJ_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))
-#define __HAL_RCC_GPIOK_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))
-#define __HAL_RCC_DMA2D_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))
-#define __HAL_RCC_CRC_FORCE_RESET()      (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
-
-#define __HAL_RCC_GPIOD_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
-#define __HAL_RCC_GPIOE_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
-#define __HAL_RCC_GPIOF_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
-#define __HAL_RCC_GPIOG_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
-#define __HAL_RCC_GPIOI_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
-#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
-#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
-#define __HAL_RCC_GPIOJ_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
-#define __HAL_RCC_GPIOK_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
-#define __HAL_RCC_DMA2D_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
-#define __HAL_RCC_CRC_RELEASE_RESET()    (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 
-  * @brief  Force or release AHB2 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_AHB2_FORCE_RESET()    (RCC->AHB2RSTR = 0xFFFFFFFFU) 
-#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
-#define __HAL_RCC_RNG_FORCE_RESET()    (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
-#define __HAL_RCC_DCMI_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
-
-#define __HAL_RCC_AHB2_RELEASE_RESET()  (RCC->AHB2RSTR = 0x00U)
-#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
-#define __HAL_RCC_RNG_RELEASE_RESET()  (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
-#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
-
-#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) 
-#define __HAL_RCC_CRYP_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
-#define __HAL_RCC_HASH_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
-
-#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
-#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
-#endif /* STM32F437xx || STM32F439xx || STM32F479xx */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 
-  * @brief  Force or release AHB3 peripheral reset.
-  * @{
-  */ 
-#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 
-#define __HAL_RCC_FMC_FORCE_RESET()    (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
-#define __HAL_RCC_FMC_RELEASE_RESET()  (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
-
-#if defined(STM32F469xx) || defined(STM32F479xx)
-#define __HAL_RCC_QSPI_FORCE_RESET()   (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
-#define __HAL_RCC_QSPI_RELEASE_RESET()   (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))  
-#endif /* STM32F469xx || STM32F479xx */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 
-  * @brief  Force or release APB1 peripheral reset.
-  * @{
-  */ 
-#define __HAL_RCC_TIM6_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_TIM7_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
-#define __HAL_RCC_TIM12_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
-#define __HAL_RCC_TIM13_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
-#define __HAL_RCC_TIM14_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
-#define __HAL_RCC_USART3_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
-#define __HAL_RCC_UART4_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
-#define __HAL_RCC_UART5_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
-#define __HAL_RCC_CAN1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
-#define __HAL_RCC_CAN2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
-#define __HAL_RCC_DAC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
-#define __HAL_RCC_UART7_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
-#define __HAL_RCC_UART8_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
-#define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
-#define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
-
-#define __HAL_RCC_TIM2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
-#define __HAL_RCC_SPI3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_I2C3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
-#define __HAL_RCC_TIM6_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_TIM7_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
-#define __HAL_RCC_TIM12_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
-#define __HAL_RCC_TIM13_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
-#define __HAL_RCC_TIM14_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
-#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
-#define __HAL_RCC_UART4_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
-#define __HAL_RCC_UART5_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
-#define __HAL_RCC_CAN1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
-#define __HAL_RCC_CAN2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
-#define __HAL_RCC_DAC_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
-#define __HAL_RCC_UART7_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
-#define __HAL_RCC_UART8_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 
-  * @brief  Force or release APB2 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_TIM8_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
-#define __HAL_RCC_SPI5_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
-#define __HAL_RCC_SPI6_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
-#define __HAL_RCC_SAI1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
-#define __HAL_RCC_SDIO_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
-#define __HAL_RCC_SPI4_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
-#define __HAL_RCC_TIM10_FORCE_RESET()  (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
-
-#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
-#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
-#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
-#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
-#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
-#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
-#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
-
-#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-#define __HAL_RCC_LTDC_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))
-#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
-#endif /* STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F469xx) || defined(STM32F479xx)
-#define __HAL_RCC_DSI_FORCE_RESET()   (RCC->APB2RSTR |=  (RCC_APB2RSTR_DSIRST))
-#define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST))
-#endif /* STM32F469xx || STM32F479xx */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
-#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
-#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
-#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
-#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
-#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
-#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE()     (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
-#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE()   (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
-#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE()   (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
-#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
-#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
-#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))
-#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))
-#define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM3LPEN))
-#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))
-#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()        (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
-#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
-#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
-#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
-
-#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
-#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
-#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
-#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
-#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
-#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
-#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE()    (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
-#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE()  (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
-#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE()  (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
-#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
-#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
-#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
-#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
-#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
-#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()       (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
-#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
-#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
-#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
-
-#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()   (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
-#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()  (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
-
-#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
-#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
-
-#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) 
-#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
-#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
-
-#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
-#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
-#endif /* STM32F437xx || STM32F439xx || STM32F479xx */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
-#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
-
-#if defined(STM32F469xx) || defined(STM32F479xx)
-#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
-#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE()  (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
-#endif /* STM32F469xx || STM32F479xx */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */  
-#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
-#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
-#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
-#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
-#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
-#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
-#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
-#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
-#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
-#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
-#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
-#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
-#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
-#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
-#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
-#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
-#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
-#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
-
-#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
-#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
-#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
-#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
-#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
-#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
-#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
-#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
-#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
-#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
-#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
-#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
-#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
-#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
-#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
-#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
-#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
-#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
-/**
-  * @}
-  */
-                                        
-/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */ 
-#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
-#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
-#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
-#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
-#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))
-#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
-#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
-#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
-#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
-
-#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
-#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
-#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
-#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
-#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
-#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
-#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
-#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
-#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
-
-#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))
-
-#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
-#endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F469xx) || defined(STM32F479xx)
-#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |=  (RCC_APB2LPENR_DSILPEN))
-#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN))
-#endif /* STM32F469xx || STM32F479xx */
-/**
-  * @}
-  */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
-/*----------------------------------------------------------------------------*/
-
-/*----------------------------------- STM32F40xxx/STM32F41xxx-----------------*/
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
-/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
-  * @brief  Enables or disables the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0)
-#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0)
-#define __HAL_RCC_CRC_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0)
-#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_GPIOI_CLK_ENABLE()   do { \
-                                       __IO uint32_t tmpreg = 0x00U; \
-                                       SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
-                                       /* Delay after an RCC peripheral clock enabling */ \
-                                       tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
-                                       UNUSED(tmpreg); \
-                                       } while(0)
-#define __HAL_RCC_GPIOF_CLK_ENABLE()   do { \
-                                       __IO uint32_t tmpreg = 0x00U; \
-                                       SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
-                                       /* Delay after an RCC peripheral clock enabling */ \
-                                       tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
-                                       UNUSED(tmpreg); \
-                                       } while(0)
-#define __HAL_RCC_GPIOG_CLK_ENABLE()   do { \
-                                       __IO uint32_t tmpreg = 0x00U; \
-                                       SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
-                                       /* Delay after an RCC peripheral clock enabling */ \
-                                       tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
-                                       UNUSED(tmpreg); \
-                                       } while(0)
-#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()   do { \
-                                       __IO uint32_t tmpreg = 0x00U; \
-                                       SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
-                                       /* Delay after an RCC peripheral clock enabling */ \
-                                       tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
-                                       UNUSED(tmpreg); \
-                                       } while(0)
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()   do { \
-                                       __IO uint32_t tmpreg = 0x00U; \
-                                       SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
-                                       /* Delay after an RCC peripheral clock enabling */ \
-                                       tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
-                                       UNUSED(tmpreg); \
-                                       } while(0)
-#define __HAL_RCC_GPIOD_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
-#define __HAL_RCC_GPIOE_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
-#define __HAL_RCC_GPIOF_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
-#define __HAL_RCC_GPIOG_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
-#define __HAL_RCC_GPIOI_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
-#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()      (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
-#define __HAL_RCC_BKPSRAM_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
-#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
-#define __HAL_RCC_CRC_CLK_DISABLE()             (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
-#if defined(STM32F407xx)|| defined(STM32F417xx)
-/**
-  * @brief  Enable ETHERNET clock.
-  */
-#define __HAL_RCC_ETHMAC_CLK_ENABLE()  do { \
-                                       __IO uint32_t tmpreg = 0x00U; \
-                                       SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
-                                       /* Delay after an RCC peripheral clock enabling */ \
-                                       tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
-                                       UNUSED(tmpreg); \
-                                       } while(0)
-#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0)
-#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0)
-#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0)
-#define __HAL_RCC_ETH_CLK_ENABLE()      do {                            \
-                                        __HAL_RCC_ETHMAC_CLK_ENABLE();      \
-                                        __HAL_RCC_ETHMACTX_CLK_ENABLE();    \
-                                        __HAL_RCC_ETHMACRX_CLK_ENABLE();    \
-                                        } while(0)
-
-/**
-  * @brief  Disable ETHERNET clock.
-  */
-#define __HAL_RCC_ETHMAC_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
-#define __HAL_RCC_ETHMACTX_CLK_DISABLE()  (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
-#define __HAL_RCC_ETHMACRX_CLK_DISABLE()  (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
-#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))  
-#define __HAL_RCC_ETH_CLK_DISABLE()       do {                             \
-                                      __HAL_RCC_ETHMACTX_CLK_DISABLE();    \
-                                      __HAL_RCC_ETHMACRX_CLK_DISABLE();    \
-                                      __HAL_RCC_ETHMAC_CLK_DISABLE();      \
-                                     } while(0)
-#endif /* STM32F407xx || STM32F417xx */
-/**
-  * @}
-  */
-  
-/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */  
-#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED()          ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
-#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
-#define __HAL_RCC_CRC_IS_CLK_ENABLED()              ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
-#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
-#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
-#define __HAL_RCC_GPIOI_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
-#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
-#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
-#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
-#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
-
-#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
-#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
-#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
-#define __HAL_RCC_GPIOG_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
-#define __HAL_RCC_GPIOI_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
-#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED()      ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
-#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN))== RESET)
-#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED()         ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
-#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
-#define __HAL_RCC_CRC_IS_CLK_DISABLED()             ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
-#if defined(STM32F407xx)|| defined(STM32F417xx)
-/**
-  * @brief  Enable ETHERNET clock.
-  */
-#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
-#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
-#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
-#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
-#define __HAL_RCC_ETH_IS_CLK_ENABLED()        (__HAL_RCC_ETHMAC_IS_CLK_ENABLED()   && \
-                                               __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
-                                               __HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
-/**
-  * @brief  Disable ETHERNET clock.
-  */
-#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
-#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
-#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
-#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
-#define __HAL_RCC_ETH_IS_CLK_DISABLED()        (__HAL_RCC_ETHMAC_IS_CLK_DISABLED()   && \
-                                                __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
-                                                __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
-#endif /* STM32F407xx || STM32F417xx */
-/**
-  * @}
-  */
-  
-/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 
-  * @brief  Enable or disable the AHB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()  do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
-                                               __HAL_RCC_SYSCFG_CLK_ENABLE();\
-                                              }while(0)
-                                        
-#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
-
-#define __HAL_RCC_RNG_CLK_ENABLE()    do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_RNG_CLK_DISABLE()   (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
-
-#if defined(STM32F407xx)|| defined(STM32F417xx) 
-#define __HAL_RCC_DCMI_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_DCMI_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
-#endif /* STM32F407xx || STM32F417xx */
-
-#if defined(STM32F415xx) || defined(STM32F417xx)
-#define __HAL_RCC_CRYP_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_HASH_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_CRYP_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
-#define __HAL_RCC_HASH_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
-#endif /* STM32F415xx || STM32F417xx */
-/**
-  * @}
-  */
-
-
-/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) 
-
-#define __HAL_RCC_RNG_IS_CLK_ENABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)   
-#define __HAL_RCC_RNG_IS_CLK_DISABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) 
-
-#if defined(STM32F407xx)|| defined(STM32F417xx) 
-#define __HAL_RCC_DCMI_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) 
-#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) 
-#endif /* STM32F407xx || STM32F417xx */
-
-#if defined(STM32F415xx) || defined(STM32F417xx)
-#define __HAL_RCC_CRYP_IS_CLK_ENABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET) 
-#define __HAL_RCC_HASH_IS_CLK_ENABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET) 
-
-#define __HAL_RCC_CRYP_IS_CLK_DISABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET) 
-#define __HAL_RCC_HASH_IS_CLK_DISABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) 
-#endif /* STM32F415xx || STM32F417xx */  
-/**
-  * @}
-  */  
-  
-/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
-  * @brief  Enables or disables the AHB3 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{  
-  */
-#define __HAL_RCC_FSMC_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB3 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_FSMC_IS_CLK_ENABLED()   ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET) 
-#define __HAL_RCC_FSMC_IS_CLK_DISABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET) 
-/**
-  * @}
-  */   
-   
-/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{  
-  */
-#define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TIM7_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TIM12_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TIM13_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TIM14_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_USART3_CLK_ENABLE() do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_UART4_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_UART5_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_CAN1_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_CAN2_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_DAC_CLK_ENABLE()    do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TIM2_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TIM3_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TIM4_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_SPI3_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_I2C3_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
-#define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
-#define __HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
-#define __HAL_RCC_SPI3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
-#define __HAL_RCC_I2C3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
-#define __HAL_RCC_TIM6_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
-#define __HAL_RCC_TIM7_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
-#define __HAL_RCC_TIM12_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
-#define __HAL_RCC_TIM13_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
-#define __HAL_RCC_TIM14_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
-#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
-#define __HAL_RCC_UART4_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
-#define __HAL_RCC_UART5_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
-#define __HAL_RCC_CAN1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
-#define __HAL_RCC_CAN2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
-#define __HAL_RCC_DAC_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
-/**
-  * @}
-  */
- 
-/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the APB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */ 
-#define __HAL_RCC_TIM2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)  
-#define __HAL_RCC_TIM3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 
-#define __HAL_RCC_TIM4_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
-#define __HAL_RCC_SPI3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 
-#define __HAL_RCC_I2C3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) 
-#define __HAL_RCC_TIM6_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 
-#define __HAL_RCC_TIM7_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) 
-#define __HAL_RCC_TIM12_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) 
-#define __HAL_RCC_TIM13_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) 
-#define __HAL_RCC_TIM14_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 
-#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) 
-#define __HAL_RCC_UART4_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) 
-#define __HAL_RCC_UART5_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) 
-#define __HAL_RCC_CAN1_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) 
-#define __HAL_RCC_CAN2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) 
-#define __HAL_RCC_DAC_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 
-
-#define __HAL_RCC_TIM2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)  
-#define __HAL_RCC_TIM3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 
-#define __HAL_RCC_TIM4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
-#define __HAL_RCC_SPI3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 
-#define __HAL_RCC_I2C3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) 
-#define __HAL_RCC_TIM6_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 
-#define __HAL_RCC_TIM7_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) 
-#define __HAL_RCC_TIM12_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) 
-#define __HAL_RCC_TIM13_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) 
-#define __HAL_RCC_TIM14_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) 
-#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) 
-#define __HAL_RCC_UART4_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) 
-#define __HAL_RCC_UART5_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) 
-#define __HAL_RCC_CAN1_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) 
-#define __HAL_RCC_CAN2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) 
-#define __HAL_RCC_DAC_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 
-  /**
-  * @}
-  */
-  
-/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{
-  */ 
-#define __HAL_RCC_TIM8_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_ADC2_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_ADC3_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_SDIO_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_SPI4_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TIM10_CLK_ENABLE()    do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_SDIO_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
-#define __HAL_RCC_SPI4_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
-#define __HAL_RCC_TIM10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
-#define __HAL_RCC_TIM8_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
-#define __HAL_RCC_ADC2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
-#define __HAL_RCC_ADC3_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the APB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_SDIO_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)  
-#define __HAL_RCC_SPI4_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)  
-#define __HAL_RCC_TIM10_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) 
-#define __HAL_RCC_TIM8_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) 
-#define __HAL_RCC_ADC2_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) 
-#define __HAL_RCC_ADC3_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
-  
-#define __HAL_RCC_SDIO_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)  
-#define __HAL_RCC_SPI4_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)  
-#define __HAL_RCC_TIM10_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) 
-#define __HAL_RCC_TIM8_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) 
-#define __HAL_RCC_ADC2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) 
-#define __HAL_RCC_ADC3_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
-/**
-  * @}
-  */
-    
-/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 
-  * @brief  Force or release AHB1 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_GPIOD_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
-#define __HAL_RCC_GPIOE_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
-#define __HAL_RCC_GPIOF_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
-#define __HAL_RCC_GPIOG_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
-#define __HAL_RCC_GPIOI_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
-#define __HAL_RCC_ETHMAC_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
-#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
-#define __HAL_RCC_CRC_FORCE_RESET()     (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
-
-#define __HAL_RCC_GPIOD_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
-#define __HAL_RCC_GPIOE_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
-#define __HAL_RCC_GPIOF_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
-#define __HAL_RCC_GPIOG_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
-#define __HAL_RCC_GPIOI_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
-#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
-#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
-#define __HAL_RCC_CRC_RELEASE_RESET()    (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 
-  * @brief  Force or release AHB2 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_AHB2_FORCE_RESET()         (RCC->AHB2RSTR = 0xFFFFFFFFU) 
-#define __HAL_RCC_AHB2_RELEASE_RESET()       (RCC->AHB2RSTR = 0x00U)
-
-#if defined(STM32F407xx)|| defined(STM32F417xx)  
-#define __HAL_RCC_DCMI_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
-#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
-#endif /* STM32F407xx || STM32F417xx */
-
-#if defined(STM32F415xx) || defined(STM32F417xx) 
-#define __HAL_RCC_CRYP_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
-#define __HAL_RCC_HASH_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
-
-#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
-#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
-#endif /* STM32F415xx || STM32F417xx */
-   
-#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
-#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
-
-#define __HAL_RCC_RNG_FORCE_RESET()    (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
-#define __HAL_RCC_RNG_RELEASE_RESET()  (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 
-  * @brief  Force or release AHB3 peripheral reset.
-  * @{
-  */ 
-#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 
-
-#define __HAL_RCC_FSMC_FORCE_RESET()   (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST))
-#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 
-  * @brief  Force or release APB1 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_TIM6_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_TIM7_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
-#define __HAL_RCC_TIM12_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
-#define __HAL_RCC_TIM13_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
-#define __HAL_RCC_TIM14_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
-#define __HAL_RCC_USART3_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
-#define __HAL_RCC_UART4_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
-#define __HAL_RCC_UART5_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
-#define __HAL_RCC_CAN1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
-#define __HAL_RCC_CAN2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
-#define __HAL_RCC_DAC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
-#define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
-#define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
-
-#define __HAL_RCC_TIM2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
-#define __HAL_RCC_SPI3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_I2C3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
-#define __HAL_RCC_TIM6_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_TIM7_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
-#define __HAL_RCC_TIM12_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
-#define __HAL_RCC_TIM13_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
-#define __HAL_RCC_TIM14_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
-#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
-#define __HAL_RCC_UART4_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
-#define __HAL_RCC_UART5_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
-#define __HAL_RCC_CAN1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
-#define __HAL_RCC_CAN2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
-#define __HAL_RCC_DAC_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 
-  * @brief  Force or release APB2 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_TIM8_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
-#define __HAL_RCC_SDIO_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
-#define __HAL_RCC_SPI4_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
-#define __HAL_RCC_TIM10_FORCE_RESET()  (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
-                                          
-#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
-#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
-#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
-#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
-/**
-  * @}
-  */
-                                        
-/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
-#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
-#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
-#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
-#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
-#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
-#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE()     (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
-#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE()   (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
-#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE()   (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
-#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
-#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
-#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
-#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
-#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
-#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
-
-#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
-#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
-#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
-#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
-#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
-#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
-#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE()    (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
-#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE()  (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
-#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE()  (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
-#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
-#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
-#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()       (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
-#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
-#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
-#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
-
-#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()   (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
-#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()  (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
-
-#if defined(STM32F407xx)|| defined(STM32F417xx) 
-#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
-#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
-#endif /* STM32F407xx || STM32F417xx */
-
-#if defined(STM32F415xx) || defined(STM32F417xx) 
-#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
-#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
-
-#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
-#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
-#endif /* STM32F415xx || STM32F417xx */
-/**
-  * @}
-  */
-                                        
-/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN))
-#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
-/**
-  * @}
-  */
-                                        
-/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
-#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
-#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
-#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
-#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
-#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
-#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
-#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
-#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
-#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
-#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
-#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
-#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
-#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
-#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
-#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
-
-#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
-#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
-#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
-#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
-#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
-#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
-#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
-#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
-#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
-#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
-#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
-#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
-#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
-#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
-#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
-#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
-/**
-  * @}
-  */
-                                        
-/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
-#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
-#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
-#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
-#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
-#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
-
-#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
-#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
-#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
-#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
-#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
-#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
-/**
-  * @}
-  */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
-/*----------------------------------------------------------------------------*/
-
-/*------------------------- STM32F401xE/STM32F401xC --------------------------*/
-#if defined(STM32F401xC) || defined(STM32F401xE)
-/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.   
-  * @{
-  */
-#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_CRC_CLK_ENABLE()    do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_BKPSRAM_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE()  do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_GPIOD_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
-#define __HAL_RCC_GPIOE_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
-#define __HAL_RCC_CRC_CLK_DISABLE()          (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
-#define __HAL_RCC_BKPSRAM_CLK_DISABLE()      (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
-#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 
-#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)  
-#define __HAL_RCC_CRC_IS_CLK_ENABLED()          ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)  
-#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED()      ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) 
-#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)  
-
-#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 
-#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)  
-#define __HAL_RCC_CRC_IS_CLK_DISABLED()          ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)  
-#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED()      ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) 
-#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)  
-/**
-  * @}
-  */ 
-  
-/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the AHB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()  do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
-                                               __HAL_RCC_SYSCFG_CLK_ENABLE();\
-                                              }while(0)
-                                        
-#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  (RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() (RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
-/**
-  * @}
-  */  
-  
-/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_TIM2_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TIM3_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TIM4_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_SPI3_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_I2C3_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
-#define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
-#define __HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
-#define __HAL_RCC_SPI3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
-#define __HAL_RCC_I2C3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the APB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_TIM2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 
-#define __HAL_RCC_TIM3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 
-#define __HAL_RCC_TIM4_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 
-#define __HAL_RCC_SPI3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 
-#define __HAL_RCC_I2C3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
-
-#define __HAL_RCC_TIM2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 
-#define __HAL_RCC_TIM3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 
-#define __HAL_RCC_TIM4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 
-#define __HAL_RCC_SPI3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 
-#define __HAL_RCC_I2C3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
-/**
-  * @}
-  */ 
-  
-/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_SDIO_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_SPI4_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TIM10_CLK_ENABLE()    do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_SDIO_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
-#define __HAL_RCC_SPI4_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
-#define __HAL_RCC_TIM10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
-/**
-  * @}
-  */
-  
-/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the APB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */  
-#define __HAL_RCC_SDIO_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
-#define __HAL_RCC_SPI4_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) 
-#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) 
-/**
-  * @}
-  */
-/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 
-  * @brief  Force or release AHB1 peripheral reset.
-  * @{
-  */  
-#define __HAL_RCC_AHB1_FORCE_RESET()    (RCC->AHB1RSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_GPIOD_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
-#define __HAL_RCC_GPIOE_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
-#define __HAL_RCC_CRC_FORCE_RESET()     (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
-
-#define __HAL_RCC_AHB1_RELEASE_RESET()  (RCC->AHB1RSTR = 0x00U)
-#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
-#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
-#define __HAL_RCC_CRC_RELEASE_RESET()   (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 
-  * @brief  Force or release AHB2 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_AHB2_FORCE_RESET()    (RCC->AHB2RSTR = 0xFFFFFFFFU) 
-#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
-
-#define __HAL_RCC_AHB2_RELEASE_RESET()  (RCC->AHB2RSTR = 0x00U)
-#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 
-  * @brief  Force or release APB1 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_APB1_FORCE_RESET()     (RCC->APB1RSTR = 0xFFFFFFFFU)  
-#define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
-#define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
-
-#define __HAL_RCC_APB1_RELEASE_RESET()   (RCC->APB1RSTR = 0x00U) 
-#define __HAL_RCC_TIM2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
-#define __HAL_RCC_SPI3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_I2C3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 
-  * @brief  Force or release APB2 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_APB2_FORCE_RESET()     (RCC->APB2RSTR = 0xFFFFFFFFU)  
-#define __HAL_RCC_SDIO_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
-#define __HAL_RCC_SPI4_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
-#define __HAL_RCC_TIM10_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
-
-#define __HAL_RCC_APB2_RELEASE_RESET()   (RCC->APB2RSTR = 0x00U)
-#define __HAL_RCC_SDIO_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
-#define __HAL_RCC_SPI4_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
-#define __HAL_RCC_TIM10_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 
-  * @brief  Force or release AHB3 peripheral reset.
-  * @{
-  */ 
-#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 
-  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
-#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
-#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
-#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
-#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
-#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
-
-#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
-#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
-#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
-#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
-#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
-#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
-
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE()   (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
-#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
-#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
-#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
-#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
-
-#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
-#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
-#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
-#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
-#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
-#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
-#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
-
-#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
-#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
-#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
-/**
-  * @}
-  */
-#endif /* STM32F401xC || STM32F401xE*/
-/*----------------------------------------------------------------------------*/
-
-/*-------------------------------- STM32F410xx -------------------------------*/
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable     
-  * @brief  Enables or disables the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_CRC_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0)
-#define __HAL_RCC_RNG_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0)
-#define __HAL_RCC_CRC_CLK_DISABLE()     (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
-#define __HAL_RCC_RNG_CLK_DISABLE()     (RCC->AHB1ENR &= ~(RCC_AHB1ENR_RNGEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_CRC_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 
-#define __HAL_RCC_RNG_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) == RESET) 
-/**
-  * @}
-  */
-  
-/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable  
-  * @brief  Enable or disable the High Speed APB (APB1) peripheral clock.
-  * @{
-  */
-#define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_LPTIM1_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_RTCAPB_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0) 
-#define __HAL_RCC_DAC_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-                                        
-#define __HAL_RCC_TIM6_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
-#define __HAL_RCC_RTCAPB_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))
-#define __HAL_RCC_LPTIM1_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
-#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
-#define __HAL_RCC_DAC_CLK_DISABLE()     (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
-/**
-  * @}
-  */
-  
-/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the APB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */  
-#define __HAL_RCC_TIM6_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 
-#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)
-#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET) 
-#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)  
-#define __HAL_RCC_DAC_IS_CLK_ENABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 
-
-#define __HAL_RCC_TIM6_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 
-#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)
-#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET) 
-#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)  
-#define __HAL_RCC_DAC_IS_CLK_DISABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)  
-/**
-  * @}
-  */
-  
-/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable  
-  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
-  * @{
-  */  
-#define __HAL_RCC_SPI5_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_EXTIT_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_SPI5_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
-#define __HAL_RCC_EXTIT_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN))
-/**
-  * @}
-  */
-  
-/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the APB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_SPI5_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)  
-#define __HAL_RCC_EXTIT_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET)  
-  
-#define __HAL_RCC_SPI5_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)  
-#define __HAL_RCC_EXTIT_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET)  
-/**
-  * @}
-  */
-  
-/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 
-  * @brief  Force or release AHB1 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_CRC_FORCE_RESET()     (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
-#define __HAL_RCC_RNG_FORCE_RESET()     (RCC->AHB1RSTR |= (RCC_AHB1RSTR_RNGRST))
-#define __HAL_RCC_CRC_RELEASE_RESET()   (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
-#define __HAL_RCC_RNG_RELEASE_RESET()   (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_RNGRST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 
-  * @brief  Force or release AHB2 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_AHB2_FORCE_RESET()
-#define __HAL_RCC_AHB2_RELEASE_RESET()
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 
-  * @brief  Force or release AHB3 peripheral reset.
-  * @{
-  */ 
-#define __HAL_RCC_AHB3_FORCE_RESET()
-#define __HAL_RCC_AHB3_RELEASE_RESET()
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 
-  * @brief  Force or release APB1 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_TIM6_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_LPTIM1_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
-#define __HAL_RCC_FMPI2C1_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST))
-#define __HAL_RCC_DAC_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
-
-#define __HAL_RCC_TIM6_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_LPTIM1_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
-#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
-#define __HAL_RCC_DAC_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 
-  * @brief  Force or release APB2 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_SPI5_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
-#define __HAL_RCC_SPI5_RELEASE_RESET()    (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))                                        
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable  
-  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_RNGLPEN))
-#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
-#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
-#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
-
-#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_RNGLPEN))
-#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
-#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
-#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable                                         
-  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
-  * @{
-  */
-#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
-#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN))
-#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN))
-#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN))
-#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
-
-#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
-#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
-#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
-#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
-#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()     (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable                                         
-  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
-  * @{
-  */
-#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE()     (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
-#define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN))                                
-#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))                                        
-#define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN))
-/**
-  * @}
-  */
-
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-/*----------------------------------------------------------------------------*/
-
-/*-------------------------------- STM32F411xx -------------------------------*/
-#if defined(STM32F411xE)
-/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
-  * @brief  Enables or disables the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0)
-#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0)
-#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0)
-#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0)
-#define __HAL_RCC_CRC_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0)
-#define __HAL_RCC_GPIOD_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
-#define __HAL_RCC_GPIOE_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
-#define __HAL_RCC_BKPSRAM_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
-#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
-#define __HAL_RCC_CRC_CLK_DISABLE()             (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */  
-#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 
-#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 
-#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED()         ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) 
-#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) 
-#define __HAL_RCC_CRC_IS_CLK_ENABLED()             ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 
-
-#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 
-#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 
-#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED()         ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) 
-#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) 
-#define __HAL_RCC_CRC_IS_CLK_DISABLED()             ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 
-/**
-  * @}
-  */
-  
-/** @defgroup RCCEX_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the AHB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()  do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
-                                               __HAL_RCC_SYSCFG_CLK_ENABLE();\
-                                              }while(0)
-
-#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
-/**
-  * @}
-  */  
-
-/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it. 
-  * @{
-  */
-#define __HAL_RCC_TIM2_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0)
-#define __HAL_RCC_TIM3_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0)
-#define __HAL_RCC_TIM4_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0)
-#define __HAL_RCC_SPI3_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0)
-#define __HAL_RCC_I2C3_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0)
-#define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
-#define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
-#define __HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
-#define __HAL_RCC_SPI3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
-#define __HAL_RCC_I2C3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
-/**
-  * @}
-  */ 
-  
-/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the APB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_TIM2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 
-#define __HAL_RCC_TIM3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 
-#define __HAL_RCC_TIM4_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 
-#define __HAL_RCC_SPI3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 
-#define __HAL_RCC_I2C3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
-
-#define __HAL_RCC_TIM2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 
-#define __HAL_RCC_TIM3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 
-#define __HAL_RCC_TIM4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 
-#define __HAL_RCC_SPI3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 
-#define __HAL_RCC_I2C3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) 
-/**
-  * @}
-  */ 
-  
-/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
-  * @{
-  */
-#define __HAL_RCC_SPI5_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_SDIO_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_SPI4_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TIM10_CLK_ENABLE()    do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_SDIO_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
-#define __HAL_RCC_SPI4_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
-#define __HAL_RCC_TIM10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
-#define __HAL_RCC_SPI5_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
-/**
-  * @}
-  */
-  
-/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the APB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_SDIO_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)  
-#define __HAL_RCC_SPI4_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)   
-#define __HAL_RCC_TIM10_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)  
-#define __HAL_RCC_SPI5_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) 
-
-#define __HAL_RCC_SDIO_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)  
-#define __HAL_RCC_SPI4_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)   
-#define __HAL_RCC_TIM10_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)  
-#define __HAL_RCC_SPI5_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)   
-/**
-  * @}
-  */  
-  
-/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 
-  * @brief  Force or release AHB1 peripheral reset.
-  * @{
-  */ 
-#define __HAL_RCC_GPIOD_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
-#define __HAL_RCC_GPIOE_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
-#define __HAL_RCC_CRC_FORCE_RESET()     (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
-
-#define __HAL_RCC_GPIOD_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
-#define __HAL_RCC_GPIOE_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
-#define __HAL_RCC_CRC_RELEASE_RESET()    (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 
-  * @brief  Force or release AHB2 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_AHB2_FORCE_RESET()    (RCC->AHB2RSTR = 0xFFFFFFFFU) 
-#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
-
-#define __HAL_RCC_AHB2_RELEASE_RESET()  (RCC->AHB2RSTR = 0x00U)
-#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 
-  * @brief  Force or release AHB3 peripheral reset.
-  * @{
-  */ 
-#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 
-  * @brief  Force or release APB1 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
-#define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
-
-#define __HAL_RCC_TIM2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
-#define __HAL_RCC_SPI3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_I2C3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 
-  * @brief  Force or release APB2 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_SPI5_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
-#define __HAL_RCC_SDIO_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
-#define __HAL_RCC_SPI4_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
-#define __HAL_RCC_TIM10_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
-
-#define __HAL_RCC_SDIO_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
-#define __HAL_RCC_SPI4_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
-#define __HAL_RCC_TIM10_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
-#define __HAL_RCC_SPI5_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 
-  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
-#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
-#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
-#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
-#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
-                                        
-#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))                                        
-#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
-#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
-#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
-#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE()   (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable 
-  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
-  * @{
-  */
-#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
-#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
-#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
-#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
-#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
-
-#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
-#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
-#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
-#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
-#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable 
-  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
-  * @{
-  */
-#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
-#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
-#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
-#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
-
-#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
-#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
-#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
-#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
-/**
-  * @}
-  */
-#endif /* STM32F411xE */
-/*----------------------------------------------------------------------------*/
-
-/*---------------------------------- STM32F446xx -----------------------------*/
-#if defined(STM32F446xx)
-/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
-  * @brief  Enables or disables the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0)
-#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0)
-#define __HAL_RCC_CRC_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0)
-#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_GPIOF_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_GPIOG_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_GPIOD_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
-#define __HAL_RCC_GPIOE_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
-#define __HAL_RCC_GPIOF_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
-#define __HAL_RCC_GPIOG_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
-#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()      (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
-#define __HAL_RCC_BKPSRAM_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
-#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
-#define __HAL_RCC_CRC_CLK_DISABLE()             (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 
-#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 
-#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) 
-#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) 
-#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)  
-#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) 
-#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED()          ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)  
-#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN))!= RESET)  
-#define __HAL_RCC_CRC_IS_CLK_ENABLED()              ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 
-
-#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 
-#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 
-#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) 
-#define __HAL_RCC_GPIOG_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) 
-#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED()      ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)  
-#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET) 
-#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED()         ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)  
-#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)  
-#define __HAL_RCC_CRC_IS_CLK_DISABLED()             ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 
-/**
-  * @}
-  */  
-  
-/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the AHB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_DCMI_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_DCMI_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
-#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()  do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
-                                               __HAL_RCC_SYSCFG_CLK_ENABLE();\
-                                              }while(0)
-                                        
-#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
-
-#define __HAL_RCC_RNG_CLK_ENABLE()    do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_RNG_CLK_DISABLE()   (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
-/**
-  * @}
-  */
-  
-/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_DCMI_IS_CLK_ENABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
-#define __HAL_RCC_DCMI_IS_CLK_DISABLED()       ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
-
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
-
-#define __HAL_RCC_RNG_IS_CLK_ENABLED()    ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) 
-#define __HAL_RCC_RNG_IS_CLK_DISABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) 
-/**
-  * @}
-  */
-  
-/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
-  * @brief  Enables or disables the AHB3 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it. 
-  * @{
-  */
-#define __HAL_RCC_FMC_CLK_ENABLE()    do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_QSPI_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_FMC_CLK_DISABLE()    (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
-#define __HAL_RCC_QSPI_CLK_DISABLE()   (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB3 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_FMC_IS_CLK_ENABLED()   ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
-#define __HAL_RCC_QSPI_IS_CLK_ENABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
-
-#define __HAL_RCC_FMC_IS_CLK_DISABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
-#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
-/**
-  * @}
-  */
-  
-/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it. 
-  * @{
-  */
-#define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TIM7_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TIM12_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TIM13_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TIM14_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_USART3_CLK_ENABLE() do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_UART4_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_UART5_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_CAN1_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_CAN2_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_CEC_CLK_ENABLE()    do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_DAC_CLK_ENABLE()    do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TIM2_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TIM3_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TIM4_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_SPI3_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_I2C3_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
-#define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
-#define __HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
-#define __HAL_RCC_SPI3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
-#define __HAL_RCC_I2C3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
-#define __HAL_RCC_TIM6_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
-#define __HAL_RCC_TIM7_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
-#define __HAL_RCC_TIM12_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
-#define __HAL_RCC_TIM13_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
-#define __HAL_RCC_TIM14_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
-#define __HAL_RCC_SPDIFRX_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
-#define __HAL_RCC_USART3_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
-#define __HAL_RCC_UART4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
-#define __HAL_RCC_UART5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
-#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
-#define __HAL_RCC_CAN1_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
-#define __HAL_RCC_CAN2_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
-#define __HAL_RCC_CEC_CLK_DISABLE()     (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
-#define __HAL_RCC_DAC_CLK_DISABLE()     (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the APB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_TIM2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)  
-#define __HAL_RCC_TIM3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
-#define __HAL_RCC_TIM4_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 
-#define __HAL_RCC_SPI3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
-#define __HAL_RCC_I2C3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
-#define __HAL_RCC_TIM6_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
-#define __HAL_RCC_TIM7_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
-#define __HAL_RCC_TIM12_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
-#define __HAL_RCC_TIM13_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
-#define __HAL_RCC_TIM14_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
-#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)
-#define __HAL_RCC_USART3_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
-#define __HAL_RCC_UART4_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
-#define __HAL_RCC_UART5_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
-#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
-#define __HAL_RCC_CAN1_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
-#define __HAL_RCC_CAN2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
-#define __HAL_RCC_CEC_IS_CLK_ENABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
-#define __HAL_RCC_DAC_IS_CLK_ENABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
-
-#define __HAL_RCC_TIM2_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)  
-#define __HAL_RCC_TIM3_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
-#define __HAL_RCC_TIM4_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 
-#define __HAL_RCC_SPI3_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
-#define __HAL_RCC_I2C3_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
-#define __HAL_RCC_TIM6_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
-#define __HAL_RCC_TIM7_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
-#define __HAL_RCC_TIM12_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
-#define __HAL_RCC_TIM13_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
-#define __HAL_RCC_TIM14_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
-#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)
-#define __HAL_RCC_USART3_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
-#define __HAL_RCC_UART4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
-#define __HAL_RCC_UART5_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
-#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
-#define __HAL_RCC_CAN1_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
-#define __HAL_RCC_CAN2_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
-#define __HAL_RCC_CEC_IS_CLK_DISABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
-#define __HAL_RCC_DAC_IS_CLK_DISABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
-/**
-  * @}
-  */
-  
-/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_TIM8_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_ADC2_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_ADC3_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_SAI1_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_SAI2_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_SDIO_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_SPI4_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TIM10_CLK_ENABLE()    do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_SDIO_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
-#define __HAL_RCC_SPI4_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
-#define __HAL_RCC_TIM10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
-#define __HAL_RCC_TIM8_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
-#define __HAL_RCC_ADC2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
-#define __HAL_RCC_ADC3_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
-#define __HAL_RCC_SAI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
-#define __HAL_RCC_SAI2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the APB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_SDIO_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) 
-#define __HAL_RCC_SPI4_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) 
-#define __HAL_RCC_TIM10_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)  
-#define __HAL_RCC_TIM8_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
-#define __HAL_RCC_ADC2_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) 
-#define __HAL_RCC_ADC3_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) 
-#define __HAL_RCC_SAI1_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
-#define __HAL_RCC_SAI2_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)
-
-#define __HAL_RCC_SDIO_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) 
-#define __HAL_RCC_SPI4_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) 
-#define __HAL_RCC_TIM10_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)  
-#define __HAL_RCC_TIM8_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
-#define __HAL_RCC_ADC2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) 
-#define __HAL_RCC_ADC3_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) 
-#define __HAL_RCC_SAI1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
-#define __HAL_RCC_SAI2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET) 
-/**
-  * @}
-  */
-  
-/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 
-  * @brief  Force or release AHB1 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_GPIOD_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
-#define __HAL_RCC_GPIOE_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
-#define __HAL_RCC_GPIOF_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
-#define __HAL_RCC_GPIOG_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
-#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
-#define __HAL_RCC_CRC_FORCE_RESET()      (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
-
-#define __HAL_RCC_GPIOD_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
-#define __HAL_RCC_GPIOE_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
-#define __HAL_RCC_GPIOF_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
-#define __HAL_RCC_GPIOG_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
-#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
-#define __HAL_RCC_CRC_RELEASE_RESET()    (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 
-  * @brief  Force or release AHB2 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_AHB2_FORCE_RESET()    (RCC->AHB2RSTR = 0xFFFFFFFFU) 
-#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
-#define __HAL_RCC_RNG_FORCE_RESET()    (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
-#define __HAL_RCC_DCMI_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
-
-#define __HAL_RCC_AHB2_RELEASE_RESET()  (RCC->AHB2RSTR = 0x00U)
-#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
-#define __HAL_RCC_RNG_RELEASE_RESET()  (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
-#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 
-  * @brief  Force or release AHB3 peripheral reset.
-  * @{
-  */ 
-#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 
-
-#define __HAL_RCC_FMC_FORCE_RESET()    (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
-#define __HAL_RCC_QSPI_FORCE_RESET()   (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
-
-#define __HAL_RCC_FMC_RELEASE_RESET()    (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
-#define __HAL_RCC_QSPI_RELEASE_RESET()   (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 
-  * @brief  Force or release APB1 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_TIM6_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_TIM7_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
-#define __HAL_RCC_TIM12_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
-#define __HAL_RCC_TIM13_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
-#define __HAL_RCC_TIM14_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
-#define __HAL_RCC_SPDIFRX_FORCE_RESET()  (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST))
-#define __HAL_RCC_USART3_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
-#define __HAL_RCC_UART4_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
-#define __HAL_RCC_UART5_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
-#define __HAL_RCC_FMPI2C1_FORCE_RESET()  (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST))
-#define __HAL_RCC_CAN1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
-#define __HAL_RCC_CAN2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
-#define __HAL_RCC_CEC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
-#define __HAL_RCC_DAC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
-#define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
-#define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
-                                          
-#define __HAL_RCC_TIM2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
-#define __HAL_RCC_SPI3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_I2C3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
-#define __HAL_RCC_TIM6_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_TIM7_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
-#define __HAL_RCC_TIM12_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
-#define __HAL_RCC_TIM13_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
-#define __HAL_RCC_TIM14_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
-#define __HAL_RCC_SPDIFRX_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
-#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
-#define __HAL_RCC_UART4_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
-#define __HAL_RCC_UART5_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
-#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
-#define __HAL_RCC_CAN1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
-#define __HAL_RCC_CAN2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
-#define __HAL_RCC_CEC_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
-#define __HAL_RCC_DAC_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 
-  * @brief  Force or release APB2 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_TIM8_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
-#define __HAL_RCC_SAI1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) 
-#define __HAL_RCC_SAI2_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST))
-#define __HAL_RCC_SDIO_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
-#define __HAL_RCC_SPI4_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
-#define __HAL_RCC_TIM10_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
-
-#define __HAL_RCC_SDIO_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
-#define __HAL_RCC_SPI4_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
-#define __HAL_RCC_TIM10_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
-#define __HAL_RCC_TIM8_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
-#define __HAL_RCC_SAI1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
-#define __HAL_RCC_SAI2_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST)) 
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 
-  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
-#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
-#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
-#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
-#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
-#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
-#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()        (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
-#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
-#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
-#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
-
-#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
-#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
-#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
-#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
-#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
-#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
-#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()       (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
-#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
-#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
-#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
-
-#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()   (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
-#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()  (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
-
-#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
-#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE()   (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
-#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
-
-#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE()   (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
-#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE()  (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */ 
-#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
-#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
-#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
-#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
-#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
-#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN))
-#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
-#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
-#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
-#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN))
-#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
-#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
-#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN))
-#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
-#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
-#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
-#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
-#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
-#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
-
-#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
-#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
-#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
-#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
-#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
-#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
-#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
-#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
-#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
-#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
-#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
-#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
-#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
-#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
-#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
-#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
-#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
-#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
-#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
-#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
-#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
-#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
-#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN))
-#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
-#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
-#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
-
-#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
-#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
-#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
-#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
-#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
-#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
-#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
-#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
-/**
-  * @}
-  */
-
-#endif /* STM32F446xx */
-/*----------------------------------------------------------------------------*/
-
-/*----------STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx----------*/
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
-/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
-  * @brief  Enables or disables the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_CRC_CLK_ENABLE()    do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_GPIOE_CLK_ENABLE()    do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_GPIOF_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_GPIOG_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_CRC_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_GPIOD_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
-#define __HAL_RCC_GPIOE_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
-#define __HAL_RCC_GPIOF_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
-#define __HAL_RCC_GPIOG_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
-#define __HAL_RCC_CRC_CLK_DISABLE()          (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
-#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
-#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
-#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
-#define __HAL_RCC_CRC_IS_CLK_ENABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
-
-#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
-#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
-#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
-#define __HAL_RCC_GPIOG_IS_CLK_DISABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
-#define __HAL_RCC_CRC_IS_CLK_DISABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the AHB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()  do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
-                                               __HAL_RCC_SYSCFG_CLK_ENABLE();\
-                                              }while(0)
-                                        
-#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
-
-#define __HAL_RCC_RNG_CLK_ENABLE()    do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_RNG_CLK_DISABLE()   (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
-          
-#define __HAL_RCC_RNG_IS_CLK_ENABLED()         ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)   
-#define __HAL_RCC_RNG_IS_CLK_DISABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)   
-/**
-  * @}
-  */  
-
-/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
-  * @brief  Enables or disables the AHB3 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it. 
-  * @{
-  */
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
-#define __HAL_RCC_FSMC_CLK_ENABLE()    do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_QSPI_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_FSMC_CLK_DISABLE()    (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
-#define __HAL_RCC_QSPI_CLK_DISABLE()    (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx */ 
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB3 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
-#define __HAL_RCC_FSMC_IS_CLK_ENABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET) 
-#define __HAL_RCC_QSPI_IS_CLK_ENABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) 
-
-#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET)
-#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx */ 
-/**
-  * @}
-  */
-  
-/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it. 
-  * @{
-  */
-#define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TIM7_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TIM12_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TIM13_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TIM14_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_RTCAPB_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
-#define __HAL_RCC_USART3_CLK_ENABLE() do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx */
-#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_CAN1_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_CAN2_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TIM2_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TIM3_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TIM4_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_SPI3_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_I2C3_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TIM2_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
-#define __HAL_RCC_TIM3_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
-#define __HAL_RCC_TIM4_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
-#define __HAL_RCC_SPI3_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
-#define __HAL_RCC_I2C3_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
-#define __HAL_RCC_TIM6_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
-#define __HAL_RCC_TIM7_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
-#define __HAL_RCC_TIM12_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
-#define __HAL_RCC_TIM13_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
-#define __HAL_RCC_TIM14_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
-#define __HAL_RCC_RTCAPB_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
-#define __HAL_RCC_USART3_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx */
-#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
-#define __HAL_RCC_CAN1_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
-#define __HAL_RCC_CAN2_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the APB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_TIM2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 
-#define __HAL_RCC_TIM3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
-#define __HAL_RCC_TIM4_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
-#define __HAL_RCC_SPI3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
-#define __HAL_RCC_I2C3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
-#define __HAL_RCC_TIM6_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
-#define __HAL_RCC_TIM7_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
-#define __HAL_RCC_TIM12_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
-#define __HAL_RCC_TIM13_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
-#define __HAL_RCC_TIM14_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
-#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
-#define __HAL_RCC_USART3_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx */
-#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
-#define __HAL_RCC_CAN1_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN))!= RESET)
-#define __HAL_RCC_CAN2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
-
-#define __HAL_RCC_TIM2_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 
-#define __HAL_RCC_TIM3_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
-#define __HAL_RCC_TIM4_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
-#define __HAL_RCC_SPI3_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
-#define __HAL_RCC_I2C3_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
-#define __HAL_RCC_TIM6_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
-#define __HAL_RCC_TIM7_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
-#define __HAL_RCC_TIM12_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
-#define __HAL_RCC_TIM13_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
-#define __HAL_RCC_TIM14_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
-#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
-#define __HAL_RCC_USART3_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx */
-#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
-#define __HAL_RCC_CAN1_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
-#define __HAL_RCC_CAN2_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
-/**
-  * @}
-  */  
-/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_TIM8_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_SPI5_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_EXTIT_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_SDIO_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_SPI4_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_TIM10_CLK_ENABLE()    do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_SDIO_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
-#define __HAL_RCC_SPI4_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
-#define __HAL_RCC_TIM10_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
-#define __HAL_RCC_TIM8_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
-#define __HAL_RCC_SPI5_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
-#define __HAL_RCC_EXTIT_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN))
-#define __HAL_RCC_DFSDM1_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the APB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_SDIO_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) 
-#define __HAL_RCC_SPI4_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
-#define __HAL_RCC_TIM10_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
-#define __HAL_RCC_TIM8_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
-#define __HAL_RCC_SPI5_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
-#define __HAL_RCC_EXTIT_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET)
-#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET)
-
-#define __HAL_RCC_SDIO_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) 
-#define __HAL_RCC_SPI4_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
-#define __HAL_RCC_TIM10_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
-#define __HAL_RCC_TIM8_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
-#define __HAL_RCC_SPI5_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
-#define __HAL_RCC_EXTIT_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET)
-#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET)
-/**
-  * @}
-  */
-  
-/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 
-  * @brief  Force or release AHB1 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_GPIOD_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
-#define __HAL_RCC_GPIOE_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
-#define __HAL_RCC_GPIOF_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
-#define __HAL_RCC_GPIOG_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
-#define __HAL_RCC_CRC_FORCE_RESET()      (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
-
-#define __HAL_RCC_GPIOD_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
-#define __HAL_RCC_GPIOE_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
-#define __HAL_RCC_GPIOF_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
-#define __HAL_RCC_GPIOG_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
-#define __HAL_RCC_CRC_RELEASE_RESET()    (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 
-  * @brief  Force or release AHB2 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_AHB2_FORCE_RESET()    (RCC->AHB2RSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_AHB2_RELEASE_RESET()  (RCC->AHB2RSTR = 0x00U)
-
-#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
-#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
-
-#define __HAL_RCC_RNG_FORCE_RESET()    (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
-#define __HAL_RCC_RNG_RELEASE_RESET()  (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 
-  * @brief  Force or release AHB3 peripheral reset.
-  * @{
-  */ 
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
-#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 
-
-#define __HAL_RCC_FSMC_FORCE_RESET()    (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST))
-#define __HAL_RCC_QSPI_FORCE_RESET()   (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
-
-#define __HAL_RCC_FSMC_RELEASE_RESET()    (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
-#define __HAL_RCC_QSPI_RELEASE_RESET()   (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx */ 
-#if defined(STM32F412Cx)
-#define __HAL_RCC_AHB3_FORCE_RESET()
-#define __HAL_RCC_AHB3_RELEASE_RESET()
-
-#define __HAL_RCC_FSMC_FORCE_RESET()
-#define __HAL_RCC_QSPI_FORCE_RESET()
-
-#define __HAL_RCC_FSMC_RELEASE_RESET()
-#define __HAL_RCC_QSPI_RELEASE_RESET()
-#endif /* STM32F412Cx */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 
-  * @brief  Force or release APB1 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_TIM6_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_TIM7_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
-#define __HAL_RCC_TIM12_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
-#define __HAL_RCC_TIM13_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
-#define __HAL_RCC_TIM14_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
-#define __HAL_RCC_USART3_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx */
-#define __HAL_RCC_FMPI2C1_FORCE_RESET()  (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST))
-#define __HAL_RCC_CAN1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
-#define __HAL_RCC_CAN2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
-#define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
-#define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
-
-#define __HAL_RCC_TIM2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
-#define __HAL_RCC_SPI3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_I2C3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
-#define __HAL_RCC_TIM6_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_TIM7_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
-#define __HAL_RCC_TIM12_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
-#define __HAL_RCC_TIM13_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
-#define __HAL_RCC_TIM14_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
-#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx */
-#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
-#define __HAL_RCC_CAN1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
-#define __HAL_RCC_CAN2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
-  * @brief  Force or release APB2 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_TIM8_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
-#define __HAL_RCC_SPI5_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
-#define __HAL_RCC_DFSDM1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST))
-#define __HAL_RCC_SDIO_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
-#define __HAL_RCC_SPI4_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
-#define __HAL_RCC_TIM10_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
-
-#define __HAL_RCC_SDIO_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
-#define __HAL_RCC_SPI4_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
-#define __HAL_RCC_TIM10_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
-#define __HAL_RCC_TIM8_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
-#define __HAL_RCC_SPI5_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
-#define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
-#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
-#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
-#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
-#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()        (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
-#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
-#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
-
-#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
-#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
-#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
-#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
-#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()       (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
-#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
-#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
-
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE()   (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
-
-#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()   (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
-#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()  (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
-#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE()   (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN))
-#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
-
-#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE()   (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
-#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE()  (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
-#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
-#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
-#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
-#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
-#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN))
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
-#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx */
-#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN))
-#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
-#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
-#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
-#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
-#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
-#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
-#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
-
-#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
-#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
-#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
-#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
-#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
-#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
-#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
-#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
-#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
-#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
-#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
-#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx */
-#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
-#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
-#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
-#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
-#define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN))
-#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN))
-#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
-#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
-#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
-
-#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
-#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
-#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
-#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
-#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
-#define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN))
-#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN))
-/**
-  * @}
-  */
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-/*----------------------------------------------------------------------------*/
-
-/*------------------------------- PLL Configuration --------------------------*/
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
-    defined(STM32F412Rx) || defined(STM32F412Cx)
-/** @brief  Macro to configure the main PLL clock source, multiplication and division factors.
-  * @note   This function must be used only when the main PLL is disabled.
-  * @param  __RCC_PLLSource__: specifies the PLL entry clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
-  *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
-  * @note   This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.  
-  * @param  __PLLM__: specifies the division factor for PLL VCO input clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
-  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
-  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
-  *         of 2 MHz to limit PLL jitter.
-  * @param  __PLLN__: specifies the multiplication factor for PLL VCO output clock
-  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
-  * @note   You have to set the PLLN parameter correctly to ensure that the VCO
-  *         output frequency is between 100 and 432 MHz.
-  *   
-  * @param  __PLLP__: specifies the division factor for main system clock (SYSCLK)
-  *         This parameter must be a number in the range {2, 4, 6, or 8}.
-  *           
-  * @param  __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
-  * @note   If the USB OTG FS is used in your application, you have to set the
-  *         PLLQ parameter correctly to have 48 MHz clock for the USB. However,
-  *         the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
-  *         correctly.
-  *     
-  * @param  __PLLR__: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
-  * @note   This parameter is only available in STM32F446xx/STM32F469xx/STM32F479xx/
-            STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices.
-  *      
-  */
-#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__)  \
-                            (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__)                   | \
-                            ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN))                      | \
-                            ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP))          | \
-                            ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))                      | \
-                            ((__PLLR__) << POSITION_VAL(RCC_PLLCFGR_PLLR))))
-#else
-/** @brief  Macro to configure the main PLL clock source, multiplication and division factors.
-  * @note   This function must be used only when the main PLL is disabled.
-  * @param  __RCC_PLLSource__: specifies the PLL entry clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
-  *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
-  * @note   This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.  
-  * @param  __PLLM__: specifies the division factor for PLL VCO input clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
-  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
-  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
-  *         of 2 MHz to limit PLL jitter.
-  * @param  __PLLN__: specifies the multiplication factor for PLL VCO output clock
-  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432
-  *         Except for STM32F411xE devices where Min_Data = 192.
-  * @note   You have to set the PLLN parameter correctly to ensure that the VCO
-  *         output frequency is between 100 and 432 MHz, Except for STM32F411xE devices
-  *         where frequency is between 192 and 432 MHz.
-  * @param  __PLLP__: specifies the division factor for main system clock (SYSCLK)
-  *         This parameter must be a number in the range {2, 4, 6, or 8}.
-  *           
-  * @param  __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
-  * @note   If the USB OTG FS is used in your application, you have to set the
-  *         PLLQ parameter correctly to have 48 MHz clock for the USB. However,
-  *         the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
-  *         correctly.
-  *      
-  */
-#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)     \
-                            (RCC->PLLCFGR = (0x20000000U | (__RCC_PLLSource__) | (__PLLM__)| \
-                            ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN))                | \
-                            ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP))    | \
-                            ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
- #endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-/*----------------------------------------------------------------------------*/
-                             
-/*----------------------------PLLI2S Configuration ---------------------------*/
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
-    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
-    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
-    defined(STM32F412Rx) || defined(STM32F412Cx)
-
-/** @brief Macros to enable or disable the PLLI2S. 
-  * @note  The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
-  */
-#define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE)
-#define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE)
-
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || 
-          STM32F412Rx || STM32F412Cx */
-#if defined(STM32F446xx)
-/** @brief  Macro to configure the PLLI2S clock multiplication and division factors .
-  * @note   This macro must be used only when the PLLI2S is disabled.
-  * @note   PLLI2S clock source is common with the main PLL (configured in 
-  *         HAL_RCC_ClockConfig() API).
-  * @param  __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
-  * @note   You have to set the PLLI2SM parameter correctly to ensure that the VCO input
-  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
-  *         of 1 MHz to limit PLLI2S jitter.
-  *
-  * @param  __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
-  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
-  * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO 
-  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
-  *
-  * @param  __PLLI2SP__: specifies division factor for SPDIFRX Clock.
-  *         This parameter must be a number in the range {2, 4, 6, or 8}.
-  * @note   the PLLI2SP parameter is only available with STM32F446xx Devices
-  *                 
-  * @param  __PLLI2SR__: specifies the division factor for I2S clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
-  * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
-  *         on the I2S clock frequency.
-  *   
-  * @param  __PLLI2SQ__: specifies the division factor for SAI clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
-  */
-#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__)    \
-                               (RCC->PLLI2SCFGR = ((__PLLI2SM__)                                   |\
-                               ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN))             |\
-                               ((((__PLLI2SP__) >> 1) -1) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) |\
-                               ((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ))             |\
-                               ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
-#elif defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
-/** @brief  Macro to configure the PLLI2S clock multiplication and division factors .
-  * @note   This macro must be used only when the PLLI2S is disabled.
-  * @note   PLLI2S clock source is common with the main PLL (configured in 
-  *         HAL_RCC_ClockConfig() API).
-  * @param  __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
-  * @note   You have to set the PLLI2SM parameter correctly to ensure that the VCO input
-  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
-  *         of 1 MHz to limit PLLI2S jitter.
-  *
-  * @param  __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
-  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
-  * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO 
-  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
-  *
-  * @param  __PLLI2SR__: specifies the division factor for I2S clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
-  * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
-  *         on the I2S clock frequency.
-  *
-  * @param  __PLLI2SQ__: specifies the division factor for SAI clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
-  */
-#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SR__)    \
-                               (RCC->PLLI2SCFGR = ((__PLLI2SM__)                                   |\
-                               ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN))             |\
-                               ((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ))             |\
-                               ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
-#else
-/** @brief  Macro to configure the PLLI2S clock multiplication and division factors .
-  * @note   This macro must be used only when the PLLI2S is disabled.
-  * @note   PLLI2S clock source is common with the main PLL (configured in 
-  *         HAL_RCC_ClockConfig() API).
-  * @param  __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
-  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
-  * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO 
-  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
-  *
-  * @param  __PLLI2SR__: specifies the division factor for I2S clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
-  * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
-  *         on the I2S clock frequency.
-  *
-  */
-#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__)                                                    \
-                               (RCC->PLLI2SCFGR = (((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN))  |\
-                               ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
-#endif /* STM32F446xx */
-
-#if defined(STM32F411xE)
-/** @brief  Macro to configure the PLLI2S clock multiplication and division factors .
-  * @note   This macro must be used only when the PLLI2S is disabled.
-  * @note   This macro must be used only when the PLLI2S is disabled.
-  * @note   PLLI2S clock source is common with the main PLL (configured in 
-  *         HAL_RCC_ClockConfig() API).
-  * @param  __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
-  * @note   The PLLI2SM parameter is only used with STM32F411xE/STM32F410xx Devices
-  * @note   You have to set the PLLI2SM parameter correctly to ensure that the VCO input
-  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
-  *         of 2 MHz to limit PLLI2S jitter.    
-  * @param  __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
-  *         This parameter must be a number between Min_Data = 192 and Max_Data = 432.
-  * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO 
-  *         output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
-  * @param  __PLLI2SR__: specifies the division factor for I2S clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
-  * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
-  *         on the I2S clock frequency.
-  */
-#define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SM__)                                                       |\
-                                                                                                  ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN))             |\
-                                                                                                  ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
-#endif /* STM32F411xE */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-/** @brief  Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
-  * @note   This macro must be used only when the PLLI2S is disabled.
-  * @note   PLLI2S clock source is common with the main PLL (configured in 
-  *         HAL_RCC_ClockConfig() API)             
-  * @param  __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
-  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
-  * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO 
-  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
-  * @param  __PLLI2SQ__: specifies the division factor for SAI1 clock.
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15. 
-  * @note   the PLLI2SQ parameter is only available with STM32F427xx/437xx/429xx/439xx/469xx/479xx 
-  *         Devices and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
-  * @param  __PLLI2SR__: specifies the division factor for I2S clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
-  * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
-  *         on the I2S clock frequency.
-  */
-#define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6)  |\
-                                                                                                 ((__PLLI2SQ__) << 24) |\
-                                                                                                 ((__PLLI2SR__) << 28))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */   
-/*----------------------------------------------------------------------------*/
-
-/*------------------------------ PLLSAI Configuration ------------------------*/
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
-/** @brief Macros to Enable or Disable the PLLISAI. 
-  * @note  The PLLSAI is only available with STM32F429x/439x Devices.
-  * @note  The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. 
-  */
-#define __HAL_RCC_PLLSAI_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = ENABLE)
-#define __HAL_RCC_PLLSAI_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = DISABLE)
-
-#if defined(STM32F446xx)
-/** @brief  Macro to configure the PLLSAI clock multiplication and division factors.
-  *
-  * @param  __PLLSAIM__: specifies the division factor for PLLSAI VCO input clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
-  * @note   You have to set the PLLSAIM parameter correctly to ensure that the VCO input
-  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
-  *         of 1 MHz to limit PLLI2S jitter.
-  * @note   The PLLSAIM parameter is only used with STM32F446xx Devices
-  *             
-  * @param  __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
-  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
-  * @note   You have to set the PLLSAIN parameter correctly to ensure that the VCO 
-  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
-  *
-  * @param  __PLLSAIP__: specifies division factor for OTG FS, SDIO and RNG clocks.
-  *         This parameter must be a number in the range {2, 4, 6, or 8}.
-  * @note   the PLLSAIP parameter is only available with STM32F446xx Devices
-  *                 
-  * @param  __PLLSAIQ__: specifies the division factor for SAI clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
-  *           
-  * @param  __PLLSAIR__: specifies the division factor for LTDC clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
-  * @note   the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices  
-  */
-#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIM__, __PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__)     \
-                               (RCC->PLLSAICFGR = ((__PLLSAIM__)                                   | \
-                               ((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN))             | \
-                               ((((__PLLSAIP__) >> 1) -1) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) | \
-                               ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)))) 
-#endif /* STM32F446xx */
-                                 
-#if defined(STM32F469xx) || defined(STM32F479xx)
-/** @brief  Macro to configure the PLLSAI clock multiplication and division factors.
-  *             
-  * @param  __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
-  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
-  * @note   You have to set the PLLSAIN parameter correctly to ensure that the VCO 
-  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
-  *
-  * @param  __PLLSAIP__: specifies division factor for SDIO and CLK48 clocks.
-  *         This parameter must be a number in the range {2, 4, 6, or 8}.
-  *                 
-  * @param  __PLLSAIQ__: specifies the division factor for SAI clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
-  *           
-  * @param  __PLLSAIR__: specifies the division factor for LTDC clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.  
-  */
-#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
-                               (RCC->PLLSAICFGR = (((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN))             |\
-                                                   ((((__PLLSAIP__) >> 1) -1) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) |\
-                                                   ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ))             |\
-                                                   ((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR))))
-#endif /* STM32F469xx || STM32F479xx */                                 
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
-/** @brief  Macro to configure the PLLSAI clock multiplication and division factors.
-  *             
-  * @param  __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
-  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
-  * @note   You have to set the PLLSAIN parameter correctly to ensure that the VCO 
-  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
-  *
-  * @param  __PLLSAIQ__: specifies the division factor for SAI clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
-  *           
-  * @param  __PLLSAIR__: specifies the division factor for LTDC clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
-  * @note   the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices  
-  */
-#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__)                                        \
-                               (RCC->PLLSAICFGR = (((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN))  | \
-                               ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ))                      | \
-                               ((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR))))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
-
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
-/*----------------------------------------------------------------------------*/
-
-/*------------------- PLLSAI/PLLI2S Dividers Configuration -------------------*/
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)  || defined(STM32F446xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx)
-/** @brief  Macro to configure the SAI clock Divider coming from PLLI2S.
-  * @note   This function must be called before enabling the PLLI2S.
-  * @param  __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock.
-  *          This parameter must be a number between 1 and 32.
-  *          SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__ 
-  */
-#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
-
-/** @brief  Macro to configure the SAI clock Divider coming from PLLSAI.
-  * @note   This function must be called before enabling the PLLSAI.
-  * @param  __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
-  *         This parameter must be a number between Min_Data = 1 and Max_Data = 32.
-  *         SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__  
-  */
-#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-/** @brief  Macro to configure the LTDC clock Divider coming from PLLSAI.
-  * 
-  * @note   The LTDC peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
-  * @note   This function must be called before enabling the PLLSAI. 
-  * @param  __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
-  *          This parameter must be a number between Min_Data = 2 and Max_Data = 16.
-  *          LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__ 
-  */
-#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-/*----------------------------------------------------------------------------*/
-
-/*------------------------- Peripheral Clock selection -----------------------*/
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
-    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) ||\
-    defined(STM32F479xx)
-/** @brief  Macro to configure the I2S clock source (I2SCLK).
-  * @note   This function must be called before enabling the I2S APB clock.
-  * @param  __SOURCE__: specifies the I2S clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
-  *            @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
-  *                                       used as I2S clock source.
-  */
-#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_CFGR_I2SSRC_BB = (__SOURCE__))
-#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */
-                                 
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-                                 
-/** @brief  Macro to configure SAI1BlockA clock source selection.
-  * @note   The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices.      
-  * @note   This function must be called before enabling PLLSAI, PLLI2S and  
-  *         the SAI clock.
-  * @param  __SOURCE__: specifies the SAI Block A clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used 
-  *                                           as SAI1 Block A clock. 
-  *            @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used 
-  *                                           as SAI1 Block A clock.
-  *            @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
-  *                                        used as SAI1 Block A clock.
-  */
-#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
-
-/** @brief  Macro to configure SAI1BlockB clock source selection.
-  * @note   The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
-  * @note   This function must be called before enabling PLLSAI, PLLI2S and  
-  *         the SAI clock.
-  * @param  __SOURCE__: specifies the SAI Block B clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used 
-  *                                           as SAI1 Block B clock. 
-  *            @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used 
-  *                                           as SAI1 Block B clock. 
-  *            @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
-  *                                        used as SAI1 Block B clock.
-  */
-#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F446xx)
-/** @brief  Macro to configure SAI1 clock source selection.
-  * @note   This configuration is only available with STM32F446xx Devices.
-  * @note   This function must be called before enabling PLL, PLLSAI, PLLI2S and  
-  *         the SAI clock.
-  * @param  __SOURCE__: specifies the SAI1 clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock. 
-  *            @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
-  *            @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.  
-  *            @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
-  */
-#define __HAL_RCC_SAI1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC, (__SOURCE__)))
-
-/** @brief  Macro to Get SAI1 clock source selection.
-  * @note   This configuration is only available with STM32F446xx Devices.      
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock. 
-  *            @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
-  *            @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.  
-  *            @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
-  */
-#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC))
-
-/** @brief  Macro to configure SAI2 clock source selection.
-  * @note   This configuration is only available with STM32F446xx Devices.      
-  * @note   This function must be called before enabling PLL, PLLSAI, PLLI2S and  
-  *         the SAI clock.
-  * @param  __SOURCE__: specifies the SAI2 clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock. 
-  *            @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
-  *            @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.  
-  *            @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
-  */
-#define __HAL_RCC_SAI2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC, (__SOURCE__)))
-
-/** @brief  Macro to Get SAI2 clock source selection.
-  * @note   This configuration is only available with STM32F446xx Devices.      
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock. 
-  *            @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
-  *            @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.  
-  *            @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
-  */
-#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC))
-
-/** @brief  Macro to configure I2S APB1 clock source selection.
-  * @note   This function must be called before enabling PLL, PLLI2S and the I2S clock.
-  * @param  __SOURCE__: specifies the I2S APB1 clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. 
-  *            @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
-  *            @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.  
-  *            @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
-  */
-#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
-
-/** @brief  Macro to Get I2S APB1 clock source selection.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. 
-  *            @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
-  *            @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.  
-  *            @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
-  */
-#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
-
-/** @brief  Macro to configure I2S APB2 clock source selection.
-  * @note   This function must be called before enabling PLL, PLLI2S and the I2S clock.
-  * @param  __SOURCE__: specifies the SAI Block A clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. 
-  *            @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
-  *            @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.  
-  *            @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
-  */
-#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
-
-/** @brief  Macro to Get I2S APB2 clock source selection.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. 
-  *            @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
-  *            @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.  
-  *            @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
-  */
-#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
-
-/** @brief  Macro to configure the CEC clock.
-  * @param  __SOURCE__: specifies the CEC clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
-  *            @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
-  */
-#define __HAL_RCC_CEC_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__SOURCE__)))
-
-/** @brief  Macro to Get the CEC clock.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_CECCLKSOURCE_HSI488: HSI selected as CEC clock
-  *            @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
-  */
-#define __HAL_RCC_GET_CEC_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL))
-
-/** @brief  Macro to configure the FMPI2C1 clock.
-  * @param  __SOURCE__: specifies the FMPI2C1 clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as FMPI2C1 clock
-  *            @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
-  *            @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
-  */
-#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
-
-/** @brief  Macro to Get the FMPI2C1 clock.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as FMPI2C1 clock
-  *            @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
-  *            @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
-  */
-#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
-
-/** @brief  Macro to configure the CLK48 clock.
-  * @param  __SOURCE__: specifies the CLK48 clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 
-  *            @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. 
-  */
-#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
-
-/** @brief  Macro to Get the CLK48 clock.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 
-  *            @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. 
-  */
-#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
-
-/** @brief  Macro to configure the SDIO clock.
-  * @param  __SOURCE__: specifies the SDIO clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 
-  *            @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 
-  */
-#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
-
-/** @brief  Macro to Get the SDIO clock.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 
-  *            @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 
-  */
-#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
-
-/** @brief  Macro to configure the SPDIFRX clock.
-  * @param  __SOURCE__: specifies the SPDIFRX clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.  
-  *            @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock. 
-  */
-#define __HAL_RCC_SPDIFRX_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, (uint32_t)(__SOURCE__)))
-
-/** @brief  Macro to Get the SPDIFRX clock.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.  
-  *            @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock. 
-  */
-#define __HAL_RCC_GET_SPDIFRX_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL))
-#endif /* STM32F446xx */
-      
-#if defined(STM32F469xx) || defined(STM32F479xx)
-      
-/** @brief  Macro to configure the CLK48 clock.
-  * @param  __SOURCE__: specifies the CLK48 clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 
-  *            @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. 
-  */
-#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, (uint32_t)(__SOURCE__)))
-
-/** @brief  Macro to Get the CLK48 clock.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 
-  *            @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. 
-  */
-#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL))
-
-/** @brief  Macro to configure the SDIO clock.
-  * @param  __SOURCE__: specifies the SDIO clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 
-  *            @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 
-  */
-#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, (uint32_t)(__SOURCE__)))
-
-/** @brief  Macro to Get the SDIO clock.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 
-  *            @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 
-  */
-#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL))  
-      
-/** @brief  Macro to configure the DSI clock.
-  * @param  __SOURCE__: specifies the DSI clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. 
-  *            @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. 
-  */
-#define __HAL_RCC_DSI_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, (uint32_t)(__SOURCE__)))
-
-/** @brief  Macro to Get the DSI clock.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. 
-  *            @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. 
-  */
-#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL))       
-      
-#endif /* STM32F469xx || STM32F479xx */
-
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
- /** @brief  Macro to configure the DFSDM1 clock.
-  * @param  __DFSDM1_CLKSOURCE__: specifies the DFSDM1 clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_DFSDM1CLKSOURCE_APB2: APB2 clock used as kernel clock. 
-  *            @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernal clock.
-  * @retval None
-  */
-#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__)  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM1_CLKSOURCE__))
-
-/** @brief  Macro to get the DFSDM1 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_DFSDM1CLKSOURCE_APB2: APB2 clock used as kernel clock. 
-  *            @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernal clock.
-  */
-#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL)))
-
-/** @brief  Macro to configure DFSDM1 Audio clock source selection.
-  * @note   This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx Devices.
-  * @param  __SOURCE__: specifies the DFSDM1 Audio clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1: CK_I2S_APB1 selected as audio clock
-  *            @arg RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2: CK_I2S_APB2 selected as audio clock
-  */
-#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL, (__SOURCE__)))
-
-/** @brief  Macro to Get DFSDM1 Audio clock source selection.
-  * @note   This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx Devices.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1: CK_I2S_APB1 selected as audio clock
-  *            @arg RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2: CK_I2S_APB2 selected as audio clock
-  */
-#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL))
-
-/** @brief  Macro to configure I2S APB1 clock source selection.
-  * @param  __SOURCE__: specifies the I2S APB1 clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
-  *            @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
-  *            @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
-  *            @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
-  */
-#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
-
-/** @brief  Macro to Get I2S APB1 clock source selection.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
-  *            @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
-  *            @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
-  *            @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
-  */
-#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
-
-/** @brief  Macro to configure I2S APB2 clock source selection.
-  * @param  __SOURCE__: specifies the I2S APB2 clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
-  *            @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
-  *            @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
-  *            @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
-  */
-#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
-
-/** @brief  Macro to Get I2S APB2 clock source selection.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
-  *            @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
-  *            @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
-  *            @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
-  */
-#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
-
-/** @brief  Macro to configure the PLL I2S clock source (PLLI2SCLK).
-  * @note   This macro must be called before enabling the I2S APB clock.
-  * @param  __SOURCE__: specifies the I2S clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_PLLI2SCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
-  *            @arg RCC_PLLI2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
-  *                                       used as I2S clock source.
-  */
-#define __HAL_RCC_PLL_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_PLLI2SCFGR_PLLI2SSRC_BB = (__SOURCE__))
-      
-/** @brief  Macro to configure the FMPI2C1 clock.
-  * @param  __SOURCE__: specifies the FMPI2C1 clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as FMPI2C1 clock
-  *            @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
-  *            @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
-  */
-#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
-
-/** @brief  Macro to Get the FMPI2C1 clock.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as FMPI2C1 clock
-  *            @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
-  *            @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
-  */
-#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
-
-/** @brief  Macro to configure the CLK48 clock.
-  * @param  __SOURCE__: specifies the CLK48 clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 
-  *            @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock.
-  */
-#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
-
-/** @brief  Macro to Get the CLK48 clock.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 
-  *            @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock
-  */
-#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
-
-/** @brief  Macro to configure the SDIO clock.
-  * @param  __SOURCE__: specifies the SDIO clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 
-  *            @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 
-  */
-#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
-
-/** @brief  Macro to Get the SDIO clock.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 
-  *            @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 
-  */
-#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
-
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-/** @brief  Macro to configure I2S clock source selection.
-  * @param  __SOURCE__: specifies the I2S clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
-  *            @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
-  *            @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.
-  */
-#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC, (__SOURCE__)))
-
-/** @brief  Macro to Get I2S clock source selection.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
-  *            @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
-  *            @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.
-  */
-#define __HAL_RCC_GET_I2S_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC))
-
-/** @brief  Macro to configure the FMPI2C1 clock.
-  * @param  __SOURCE__: specifies the FMPI2C1 clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as FMPI2C1 clock
-  *            @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
-  *            @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
-  */
-#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
-
-/** @brief  Macro to Get the FMPI2C1 clock.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as FMPI2C1 clock
-  *            @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
-  *            @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
-  */
-#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
-
-/** @brief  Macro to configure the LPTIM1 clock.
-  * @param  __SOURCE__: specifies the LPTIM1 clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_LPTIM1CLKSOURCE_PCLK: APB selected as LPTIM1 clock
-  *            @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
-  *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
-  *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
-  */
-#define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__)))
-
-/** @brief  Macro to Get the LPTIM1 clock.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_LPTIM1CLKSOURCE_PCLK: APB selected as LPTIM1 clock
-  *            @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
-  *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
-  *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
-  */
-#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-      
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
-    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
-    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
-    defined(STM32F412Cx)
-/** @brief  Macro to configure the Timers clocks prescalers 
-  * @note   This feature is only available with STM32F429x/439x Devices.  
-  * @param  __PRESC__ : specifies the Timers clocks prescalers selection
-  *         This parameter can be one of the following values:
-  *            @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is 
-  *                 equal to HPRE if PPREx is corresponding to division by 1 or 2, 
-  *                 else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to 
-  *                 division by 4 or more.       
-  *            @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is 
-  *                 equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, 
-  *                 else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding 
-  *                 to division by 8 or more.
-  */     
-#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__))
-
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx) || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE ||\
-          STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx  || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-
-/*----------------------------------------------------------------------------*/
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
-/** @brief Enable PLLSAI_RDY interrupt.
-  */
-#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))
-
-/** @brief Disable PLLSAI_RDY interrupt.
-  */
-#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
-
-/** @brief Clear the PLLSAI RDY interrupt pending bits.
-  */
-#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))
-
-/** @brief Check the PLLSAI RDY interrupt has occurred or not.
-  * @retval The new state (TRUE or FALSE).
-  */
-#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
-
-/** @brief  Check PLLSAI RDY flag is set or not.
-  * @retval The new state (TRUE or FALSE).
-  */
-#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
-
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-/** @brief  Macros to enable or disable the RCC MCO1 feature.
-  */
-#define __HAL_RCC_MCO1_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = ENABLE)
-#define __HAL_RCC_MCO1_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = DISABLE)
-
-/** @brief  Macros to enable or disable the RCC MCO2 feature.
-  */
-#define __HAL_RCC_MCO2_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = ENABLE)
-#define __HAL_RCC_MCO2_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = DISABLE)
-
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RCCEx_Exported_Functions
-  *  @{
-  */
-
-/** @addtogroup RCCEx_Exported_Functions_Group1
-  *  @{
-  */
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
-void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
-
-#if defined(STM32F446xx)
-uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
-#endif /* STM32F446xx */
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\
-    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
-    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
-void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
-#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
-  * @{
-  */
-
-/** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion
-  * @brief RCC registers bit address in the alias region
-  * @{
-  */
-/* --- CR Register ---*/  
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
-/* Alias word address of PLLSAION bit */
-#define RCC_PLLSAION_BIT_NUMBER        0x1C
-#define RCC_CR_PLLSAION_BB            (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLSAION_BIT_NUMBER * 4))
-
-#define PLLSAI_TIMEOUT_VALUE       ((uint32_t)2)  /* Timeout value fixed to 2 ms  */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
-    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
-    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
-    defined(STM32F412Rx) || defined(STM32F412Cx)
-/* Alias word address of PLLI2SON bit */
-#define RCC_PLLI2SON_BIT_NUMBER    0x1A
-#define RCC_CR_PLLI2SON_BB         (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLI2SON_BIT_NUMBER * 4))
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
-          STM32F412Rx || STM32F412Cx */
-
-/* --- DCKCFGR Register ---*/
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F401xC) ||\
-    defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
-    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
-    defined(STM32F412Cx)
-/* Alias word address of TIMPRE bit */
-#define RCC_DCKCFGR_OFFSET            (RCC_OFFSET + 0x8C)
-#define RCC_TIMPRE_BIT_NUMBER          0x18
-#define RCC_DCKCFGR_TIMPRE_BB         (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32) + (RCC_TIMPRE_BIT_NUMBER * 4))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F410xx || STM32F401xC ||\
-          STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
-          STM32F412Vx || STM32F412Rx || STM32F412Cx */
-
-/* --- CFGR Register ---*/
-#define RCC_CFGR_OFFSET            (RCC_OFFSET + 0x08U)
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
-    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
-    defined(STM32F469xx) || defined(STM32F479xx)
-/* Alias word address of I2SSRC bit */
-#define RCC_I2SSRC_BIT_NUMBER      0x17
-#define RCC_CFGR_I2SSRC_BB         (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_I2SSRC_BIT_NUMBER * 4))
-      
-#define PLLI2S_TIMEOUT_VALUE       ((uint32_t)2)  /* Timeout value fixed to 2 ms  */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
-      
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
-/* --- PLLI2SCFGR Register ---*/
-#define RCC_PLLI2SCFGR_OFFSET            (RCC_OFFSET + 0x84U)
-/* Alias word address of PLLI2SSRC bit */
-#define RCC_PLLI2SSRC_BIT_NUMBER      0x16
-#define RCC_PLLI2SCFGR_PLLI2SSRC_BB         (PERIPH_BB_BASE + (RCC_PLLI2SCFGR_OFFSET * 32) + (RCC_PLLI2SSRC_BIT_NUMBER * 4))
-      
-#define PLLI2S_TIMEOUT_VALUE       ((uint32_t)2)  /* Timeout value fixed to 2 ms */
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-/* Alias word address of MCO1EN bit */
-#define RCC_MCO1EN_BIT_NUMBER      0x8
-#define RCC_CFGR_MCO1EN_BB         (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO1EN_BIT_NUMBER * 4))
-
-/* Alias word address of MCO2EN bit */
-#define RCC_MCO2EN_BIT_NUMBER      0x9
-#define RCC_CFGR_MCO2EN_BB         (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO2EN_BIT_NUMBER * 4))
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-
-#define PLL_TIMEOUT_VALUE          ((uint32_t)2)  /* 2 ms */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
-  * @{
-  */
-/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
-  * @{
-  */
-#if defined(STM32F411xE)
-#define IS_RCC_PLLN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U))
-#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U))      
-#else /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||
-         STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410Tx || STM32F410Cx || 
-         STM32F410Rx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Cx || STM32F412Rx || 
-         STM32F412Vx || STM32F412Zx */
-#define IS_RCC_PLLN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
-#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
-#endif  /* STM32F411xE */    
-      
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
-#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000007FU))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) 
-#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000007U))
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
-
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 
-#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000000FU))
-#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000001FU))
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-
-#if defined(STM32F446xx)
-#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000FFFU))
-#endif /* STM32F446xx */
-
-#if defined(STM32F469xx) || defined(STM32F479xx)
-#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x000001FFU))
-#endif /* STM32F469xx || STM32F479xx */
-
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
-#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x000003FFU))
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-
-#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
-    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
-#define IS_RCC_PLLI2SQ_VALUE(VALUE)     ((2U <= (VALUE)) && ((VALUE) <= 15U))
-
-#define IS_RCC_PLLSAIN_VALUE(VALUE)     ((50U <= (VALUE)) && ((VALUE) <= 432U))
-
-#define IS_RCC_PLLSAIQ_VALUE(VALUE)     ((2U <= (VALUE)) && ((VALUE) <= 15U))
-
-#define IS_RCC_PLLSAIR_VALUE(VALUE)     ((2U <= (VALUE)) && ((VALUE) <= 7U))
-
-#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
-
-#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
-
-#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2)  ||\
-                                         ((VALUE) == RCC_PLLSAIDIVR_4)  ||\
-                                         ((VALUE) == RCC_PLLSAIDIVR_8)  ||\
-                                         ((VALUE) == RCC_PLLSAIDIVR_16))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
-    defined(STM32F412Rx) || defined(STM32F412Cx)
-#define IS_RCC_PLLI2SM_VALUE(VALUE)     ((VALUE) <= 63U)
- 
-#define IS_RCC_LSE_MODE(MODE)           (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\
-                                         ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
-#endif /* STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
-
-#define IS_RCC_LSE_MODE(MODE)           (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\
-                                         ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
-
-#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_FMPI2C1CLKSOURCE_APB)    ||\
-                                           ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\
-                                           ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
-
-#define IS_RCC_LPTIM1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) ||\
-                                          ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) ||\
-                                          ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) ||\
-                                          ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
-
-#define IS_RCC_I2SAPBCLKSOURCE(SOURCE)      (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR)    ||\
-                                             ((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT)    ||\
-                                             ((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC))
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-
-#if defined(STM32F446xx)
-#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
-  
-#define IS_RCC_PLLI2SP_VALUE(VALUE)       (((VALUE) == RCC_PLLI2SP_DIV2) ||\
-                                           ((VALUE) == RCC_PLLI2SP_DIV4) ||\
-                                           ((VALUE) == RCC_PLLI2SP_DIV6) ||\
-                                           ((VALUE) == RCC_PLLI2SP_DIV8))
-
-#define IS_RCC_PLLSAIM_VALUE(VALUE)       ((VALUE) <= 63U)
-  
-#define IS_RCC_PLLSAIP_VALUE(VALUE)       (((VALUE) == RCC_PLLSAIP_DIV2) ||\
-                                           ((VALUE) == RCC_PLLSAIP_DIV4) ||\
-                                           ((VALUE) == RCC_PLLSAIP_DIV6) ||\
-                                           ((VALUE) == RCC_PLLSAIP_DIV8))
-
-#define IS_RCC_SAI1CLKSOURCE(SOURCE)      (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) ||\
-                                           ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) ||\
-                                           ((SOURCE) == RCC_SAI1CLKSOURCE_PLLR)   ||\
-                                           ((SOURCE) == RCC_SAI1CLKSOURCE_EXT))
-
-#define IS_RCC_SAI2CLKSOURCE(SOURCE)      (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) ||\
-                                           ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) ||\
-                                           ((SOURCE) == RCC_SAI2CLKSOURCE_PLLR)   ||\
-                                           ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC))
- 
-#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) ||\
-                                           ((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT)    ||\
-                                           ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR)   ||\
-                                           ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
-                                              
- #define IS_RCC_I2SAPB2CLKSOURCE(SOURCE)  (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) ||\
-                                           ((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT)    ||\
-                                           ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR)   ||\
-                                           ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
-
-#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_FMPI2C1CLKSOURCE_APB)    ||\
-                                           ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\
-                                           ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
-
-#define IS_RCC_CECCLKSOURCE(SOURCE)       (((SOURCE) == RCC_CECCLKSOURCE_HSI)   ||\
-                                           ((SOURCE) == RCC_CECCLKSOURCE_LSE))
-
-#define IS_RCC_CLK48CLKSOURCE(SOURCE)      (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\
-                                            ((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP))
-
-#define IS_RCC_SDIOCLKSOURCE(SOURCE)      (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\
-                                           ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
-
-#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE)   (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLR) ||\
-                                           ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLI2SP))  
-#endif /* STM32F446xx */
-
-#if defined(STM32F469xx) || defined(STM32F479xx)
-#define IS_RCC_PLLR_VALUE(VALUE)            ((2U <= (VALUE)) && ((VALUE) <= 7U))
-
-#define IS_RCC_PLLSAIP_VALUE(VALUE)         (((VALUE) == RCC_PLLSAIP_DIV2) ||\
-                                             ((VALUE) == RCC_PLLSAIP_DIV4) ||\
-                                             ((VALUE) == RCC_PLLSAIP_DIV6) ||\
-                                             ((VALUE) == RCC_PLLSAIP_DIV8))
- 
-#define IS_RCC_CLK48CLKSOURCE(SOURCE)        (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\
-                                              ((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP))
-
-#define IS_RCC_SDIOCLKSOURCE(SOURCE)        (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\
-                                             ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
-
-#define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR)  ||\
-                                             ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY))
-
-#define IS_RCC_LSE_MODE(MODE)               (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\
-                                             ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
-#endif /* STM32F469xx || STM32F479xx */
-
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
-#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
-
-#define IS_RCC_PLLI2SCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLI2SCLKSOURCE_PLLSRC) || \
-                                            ((__SOURCE__) == RCC_PLLI2SCLKSOURCE_EXT))
- 
-#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) ||\
-                                           ((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT)    ||\
-                                           ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR)   ||\
-                                           ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
-                                              
- #define IS_RCC_I2SAPB2CLKSOURCE(SOURCE)  (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) ||\
-                                           ((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT)    ||\
-                                           ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR)   ||\
-                                           ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
-
-#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_FMPI2C1CLKSOURCE_APB)    ||\
-                                           ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\
-                                           ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
-
-#define IS_RCC_CLK48CLKSOURCE(SOURCE)      (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\
-                                            ((SOURCE) == RCC_CLK48CLKSOURCE_PLLI2SQ))
-
-#define IS_RCC_SDIOCLKSOURCE(SOURCE)      (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\
-                                           ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
-
-#define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_APB2) || \
-                                            ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK))
-
-#define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1) || \
-                                                 ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2))
-
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
-    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
-    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
-    defined(STM32F412Rx)
-      
-#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \
-                                   ((SOURCE) == RCC_MCO2SOURCE_HSE)    || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
-
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || \
-          STM32F412Rx */
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)      
-#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_I2SCLK)|| \
-                                   ((SOURCE) == RCC_MCO2SOURCE_HSE)    || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_RCC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_rng.h b/stmhal/hal/f4/inc/stm32f4xx_hal_rng.h
deleted file mode 100644
index 0fe87bdca0..0000000000
--- a/stmhal/hal/f4/inc/stm32f4xx_hal_rng.h
+++ /dev/null
@@ -1,369 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_rng.h
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   Header file of RNG HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_RNG_H
-#define __STM32F4xx_HAL_RNG_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
-    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F469xx) ||\
-    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
-    defined(STM32F412Cx)
-      
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup RNG RNG
-  * @brief RNG HAL module driver
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/ 
-
-/** @defgroup RNG_Exported_Types RNG Exported Types
-  * @{
-  */
-
-/** @defgroup RNG_Exported_Types_Group1 RNG State Structure definition 
-  * @{
-  */
-typedef enum
-{
-  HAL_RNG_STATE_RESET     = 0x00U,  /*!< RNG not yet initialized or disabled */
-  HAL_RNG_STATE_READY     = 0x01U,  /*!< RNG initialized and ready for use   */
-  HAL_RNG_STATE_BUSY      = 0x02U,  /*!< RNG internal process is ongoing     */ 
-  HAL_RNG_STATE_TIMEOUT   = 0x03U,  /*!< RNG timeout state                   */
-  HAL_RNG_STATE_ERROR     = 0x04U   /*!< RNG error state                     */
-    
-}HAL_RNG_StateTypeDef;
-
-/** 
-  * @}
-  */
-
-/** @defgroup RNG_Exported_Types_Group2 RNG Handle Structure definition   
-  * @{
-  */ 
-typedef struct
-{
-  RNG_TypeDef                 *Instance;    /*!< Register base address   */ 
-  
-  HAL_LockTypeDef             Lock;         /*!< RNG locking object      */
-  
-  __IO HAL_RNG_StateTypeDef   State;        /*!< RNG communication state */
-  
-  uint32_t                    RandomNumber; /*!< Last Generated RNG Data */
-  
-}RNG_HandleTypeDef;
-
-/** 
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-   
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup RNG_Exported_Constants RNG Exported Constants
-  * @{
-  */
-
-/** @defgroup RNG_Exported_Constants_Group1 RNG Interrupt definition
-  * @{
-  */
-#define RNG_IT_DRDY  RNG_SR_DRDY  /*!< Data Ready interrupt  */
-#define RNG_IT_CEI   RNG_SR_CEIS  /*!< Clock error interrupt */
-#define RNG_IT_SEI   RNG_SR_SEIS  /*!< Seed error interrupt  */
-/**
-  * @}
-  */
-
-/** @defgroup RNG_Exported_Constants_Group2 RNG Flag definition
-  * @{
-  */
-#define RNG_FLAG_DRDY   RNG_SR_DRDY  /*!< Data ready                 */
-#define RNG_FLAG_CECS   RNG_SR_CECS  /*!< Clock error current status */
-#define RNG_FLAG_SECS   RNG_SR_SECS  /*!< Seed error current status  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-  
-/* Exported macros -----------------------------------------------------------*/
-
-/** @defgroup RNG_Exported_Macros RNG Exported Macros
-  * @{
-  */
-
-/** @brief Reset RNG handle state
-  * @param  __HANDLE__: RNG Handle
-  * @retval None
-  */
-#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
-
-/**
-  * @brief  Enables the RNG peripheral.
-  * @param  __HANDLE__: RNG Handle
-  * @retval None
-  */
-#define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_RNGEN)
-
-/**
-  * @brief  Disables the RNG peripheral.
-  * @param  __HANDLE__: RNG Handle
-  * @retval None
-  */
-#define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
-
-/**
-  * @brief  Check the selected RNG flag status.
-  * @param  __HANDLE__: RNG Handle
-  * @param  __FLAG__: RNG flag
-  *          This parameter can be one of the following values:
-  *            @arg RNG_FLAG_DRDY: Data ready                
-  *            @arg RNG_FLAG_CECS: Clock error current status
-  *            @arg RNG_FLAG_SECS: Seed error current status 
-  * @retval The new state of __FLAG__ (SET or RESET).
-  */
-#define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-
-/**
-  * @brief  Clears the selected RNG flag status.
-  * @param  __HANDLE__: RNG handle
-  * @param  __FLAG__: RNG flag to clear  
-  * @note   WARNING: This is a dummy macro for HAL code alignment,
-  *         flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
-  * @retval None
-  */
-#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__)                      /* dummy  macro */
-
-
-
-/**
-  * @brief  Enables the RNG interrupts.
-  * @param  __HANDLE__: RNG Handle
-  * @retval None
-  */
-#define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_IE)
-    
-/**
-  * @brief  Disables the RNG interrupts.
-  * @param  __HANDLE__: RNG Handle
-  * @retval None
-  */
-#define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
-
-/**
-  * @brief  Checks whether the specified RNG interrupt has occurred or not.
-  * @param  __HANDLE__: RNG Handle
-  * @param  __INTERRUPT__: specifies the RNG interrupt status flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg RNG_IT_DRDY: Data ready interrupt              
-  *            @arg RNG_IT_CEI: Clock error interrupt
-  *            @arg RNG_IT_SEI: Seed error interrupt
-  * @retval The new state of __INTERRUPT__ (SET or RESET).
-  */
-#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))   
-
-/**
-  * @brief  Clear the RNG interrupt status flags.
-  * @param  __HANDLE__: RNG Handle
-  * @param  __INTERRUPT__: specifies the RNG interrupt status flag to clear.
-  *          This parameter can be one of the following values:            
-  *            @arg RNG_IT_CEI: Clock error interrupt
-  *            @arg RNG_IT_SEI: Seed error interrupt
-  * @note   RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.          
-  * @retval None
-  */
-#define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
-
-/**
-  * @}
-  */ 
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup RNG_Exported_Functions RNG Exported Functions
-  * @{
-  */
-
-/** @defgroup RNG_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */  
-HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);
-HAL_StatusTypeDef HAL_RNG_DeInit (RNG_HandleTypeDef *hrng);
-void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
-void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions
-  * @{
-  */
-uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng);    /* Obsolete, use HAL_RNG_GenerateRandomNumber() instead    */
-uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber_IT() instead */
-
-HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
-HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
-uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);
-
-void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
-void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
-void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef* hrng, uint32_t random32bit);
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions
-  * @{
-  */
-HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */ 
-
-/* Private types -------------------------------------------------------------*/
-/** @defgroup RNG_Private_Types RNG Private Types
-  * @{
-  */
-
-/**
-  * @}
-  */ 
-
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup RNG_Private_Defines RNG Private Defines
-  * @{
-  */
-
-/**
-  * @}
-  */ 
-          
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup RNG_Private_Variables RNG Private Variables
-  * @{
-  */
-
-/**
-  * @}
-  */ 
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RNG_Private_Constants RNG Private Constants
-  * @{
-  */
-
-/**
-  * @}
-  */ 
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup RNG_Private_Macros RNG Private Macros
-  * @{
-  */
-#define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || \
-                       ((IT) == RNG_IT_SEI))
-
-#define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \
-                           ((FLAG) == RNG_FLAG_CECS) || \
-                           ((FLAG) == RNG_FLAG_SECS))
-
-/**
-  * @}
-  */ 
-
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup RNG_Private_Functions_Prototypes RNG Private Functions Prototypes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup RNG_Private_Functions RNG Private Functions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
-          STM32F429xx || STM32F439xx || STM32F410xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
-          STM32F412Vx || STM32F412Rx || STM32F412Cx */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F4xx_HAL_RNG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_rtc.h b/stmhal/hal/f4/inc/stm32f4xx_hal_rtc.h
deleted file mode 100644
index 1ef0090ef0..0000000000
--- a/stmhal/hal/f4/inc/stm32f4xx_hal_rtc.h
+++ /dev/null
@@ -1,833 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_rtc.h
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   Header file of RTC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_RTC_H
-#define __STM32F4xx_HAL_RTC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup RTC
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup RTC_Exported_Types RTC Exported Types
-  * @{
-  */
-
-/** 
-  * @brief  HAL State structures definition  
-  */
-typedef enum
-{
-  HAL_RTC_STATE_RESET             = 0x00U,  /*!< RTC not yet initialized or disabled */
-  HAL_RTC_STATE_READY             = 0x01U,  /*!< RTC initialized and ready for use   */
-  HAL_RTC_STATE_BUSY              = 0x02U,  /*!< RTC process is ongoing              */
-  HAL_RTC_STATE_TIMEOUT           = 0x03U,  /*!< RTC timeout state                   */
-  HAL_RTC_STATE_ERROR             = 0x04U   /*!< RTC error state                     */
-}HAL_RTCStateTypeDef;
-
-/** 
-  * @brief  RTC Configuration Structure definition  
-  */
-typedef struct
-{
-  uint32_t HourFormat;      /*!< Specifies the RTC Hour Format.
-                                 This parameter can be a value of @ref RTC_Hour_Formats */
-
-  uint32_t AsynchPrediv;    /*!< Specifies the RTC Asynchronous Predivider value.
-                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
-
-  uint32_t SynchPrediv;     /*!< Specifies the RTC Synchronous Predivider value.
-                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFFU */
-
-  uint32_t OutPut;          /*!< Specifies which signal will be routed to the RTC output.   
-                                 This parameter can be a value of @ref RTC_Output_selection_Definitions */
-
-  uint32_t OutPutPolarity;  /*!< Specifies the polarity of the output signal.  
-                                 This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
-
-  uint32_t OutPutType;      /*!< Specifies the RTC Output Pin mode.   
-                                 This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
-}RTC_InitTypeDef;
-
-/** 
-  * @brief  RTC Time structure definition  
-  */
-typedef struct
-{
-  uint8_t Hours;            /*!< Specifies the RTC Time Hour.
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected  */
-
-  uint8_t Minutes;          /*!< Specifies the RTC Time Minutes.
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
-
-  uint8_t Seconds;          /*!< Specifies the RTC Time Seconds.
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
-
-  uint8_t TimeFormat;       /*!< Specifies the RTC AM/PM Time.
-                                 This parameter can be a value of @ref RTC_AM_PM_Definitions */
-
-  uint32_t SubSeconds;     /*!< Specifies the RTC_SSR RTC Sub Second register content.
-                                 This parameter corresponds to a time unit range between [0-1] Second
-                                 with [1 Sec / SecondFraction +1] granularity */
-
-  uint32_t SecondFraction;  /*!< Specifies the range or granularity of Sub Second register content
-                                 corresponding to Synchronous pre-scaler factor value (PREDIV_S)
-                                 This parameter corresponds to a time unit range between [0-1] Second
-                                 with [1 Sec / SecondFraction +1] granularity.
-                                 This field will be used only by HAL_RTC_GetTime function */
-
-  uint32_t DayLightSaving;  /*!< Specifies DayLight Save Operation.
-                                 This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
-
-  uint32_t StoreOperation;  /*!< Specifies RTC_StoreOperation value to be written in the BCK bit 
-                                 in CR register to store the operation.
-                                 This parameter can be a value of @ref RTC_StoreOperation_Definitions */
-}RTC_TimeTypeDef; 
-
-/** 
-  * @brief  RTC Date structure definition  
-  */
-typedef struct
-{
-  uint8_t WeekDay;  /*!< Specifies the RTC Date WeekDay.
-                         This parameter can be a value of @ref RTC_WeekDay_Definitions */
-
-  uint8_t Month;    /*!< Specifies the RTC Date Month (in BCD format).
-                         This parameter can be a value of @ref RTC_Month_Date_Definitions */
-
-  uint8_t Date;     /*!< Specifies the RTC Date.
-                         This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
-
-  uint8_t Year;     /*!< Specifies the RTC Date Year.
-                         This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
-
-}RTC_DateTypeDef;
-
-/** 
-  * @brief  RTC Alarm structure definition  
-  */
-typedef struct
-{
-  RTC_TimeTypeDef AlarmTime;     /*!< Specifies the RTC Alarm Time members */
-
-  uint32_t AlarmMask;            /*!< Specifies the RTC Alarm Masks.
-                                      This parameter can be a value of @ref RTC_AlarmMask_Definitions */
-
-  uint32_t AlarmSubSecondMask;   /*!< Specifies the RTC Alarm SubSeconds Masks.
-                                      This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
-
-  uint32_t AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on Date or WeekDay.
-                                     This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
-
-  uint8_t AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Date/WeekDay.
-                                      If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
-                                      If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
-
-  uint32_t Alarm;                /*!< Specifies the alarm .
-                                      This parameter can be a value of @ref RTC_Alarms_Definitions */
-}RTC_AlarmTypeDef;
-
-/** 
-  * @brief  RTC Handle Structure definition  
-  */ 
-typedef struct
-{
-  RTC_TypeDef                 *Instance;  /*!< Register base address    */
-
-  RTC_InitTypeDef             Init;       /*!< RTC required parameters  */
-
-  HAL_LockTypeDef             Lock;       /*!< RTC locking object       */
-
-  __IO HAL_RTCStateTypeDef    State;      /*!< Time communication state */
-
-}RTC_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RTC_Exported_Constants RTC Exported Constants
-  * @{
-  */
-
-/** @defgroup RTC_Hour_Formats RTC Hour Formats
-  * @{
-  */ 
-#define RTC_HOURFORMAT_24              ((uint32_t)0x00000000U)
-#define RTC_HOURFORMAT_12              ((uint32_t)0x00000040U)
-/**
-  * @}
-  */ 
-  
-/** @defgroup RTC_Output_selection_Definitions RTC Output Selection Definitions
-  * @{
-  */ 
-#define RTC_OUTPUT_DISABLE             ((uint32_t)0x00000000U)
-#define RTC_OUTPUT_ALARMA              ((uint32_t)0x00200000U)
-#define RTC_OUTPUT_ALARMB              ((uint32_t)0x00400000U)
-#define RTC_OUTPUT_WAKEUP              ((uint32_t)0x00600000U)
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
-  * @{
-  */ 
-#define RTC_OUTPUT_POLARITY_HIGH       ((uint32_t)0x00000000U)
-#define RTC_OUTPUT_POLARITY_LOW        ((uint32_t)0x00100000U)
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
-  * @{
-  */ 
-#define RTC_OUTPUT_TYPE_OPENDRAIN      ((uint32_t)0x00000000U)
-#define RTC_OUTPUT_TYPE_PUSHPULL       ((uint32_t)0x00040000U)
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
-  * @{
-  */ 
-#define RTC_HOURFORMAT12_AM            ((uint8_t)0x00U)
-#define RTC_HOURFORMAT12_PM            ((uint8_t)0x40U)
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions
-  * @{
-  */ 
-#define RTC_DAYLIGHTSAVING_SUB1H       ((uint32_t)0x00020000U)
-#define RTC_DAYLIGHTSAVING_ADD1H       ((uint32_t)0x00010000U)
-#define RTC_DAYLIGHTSAVING_NONE        ((uint32_t)0x00000000U)
-/**
-  * @}
-  */
-
-/** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions
-  * @{
-  */ 
-#define RTC_STOREOPERATION_RESET        ((uint32_t)0x00000000U)
-#define RTC_STOREOPERATION_SET          ((uint32_t)0x00040000U)
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions
-  * @{
-  */ 
-#define RTC_FORMAT_BIN                      ((uint32_t)0x00000000U)
-#define RTC_FORMAT_BCD                      ((uint32_t)0x00000001U)
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
-  * @{
-  */ 
-/* Coded in BCD format */
-#define RTC_MONTH_JANUARY              ((uint8_t)0x01U)
-#define RTC_MONTH_FEBRUARY             ((uint8_t)0x02U)
-#define RTC_MONTH_MARCH                ((uint8_t)0x03U)
-#define RTC_MONTH_APRIL                ((uint8_t)0x04U)
-#define RTC_MONTH_MAY                  ((uint8_t)0x05U)
-#define RTC_MONTH_JUNE                 ((uint8_t)0x06U)
-#define RTC_MONTH_JULY                 ((uint8_t)0x07U)
-#define RTC_MONTH_AUGUST               ((uint8_t)0x08U)
-#define RTC_MONTH_SEPTEMBER            ((uint8_t)0x09U)
-#define RTC_MONTH_OCTOBER              ((uint8_t)0x10U)
-#define RTC_MONTH_NOVEMBER             ((uint8_t)0x11U)
-#define RTC_MONTH_DECEMBER             ((uint8_t)0x12U)
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
-  * @{
-  */   
-#define RTC_WEEKDAY_MONDAY             ((uint8_t)0x01U)
-#define RTC_WEEKDAY_TUESDAY            ((uint8_t)0x02U)
-#define RTC_WEEKDAY_WEDNESDAY          ((uint8_t)0x03U)
-#define RTC_WEEKDAY_THURSDAY           ((uint8_t)0x04U)
-#define RTC_WEEKDAY_FRIDAY             ((uint8_t)0x05U)
-#define RTC_WEEKDAY_SATURDAY           ((uint8_t)0x06U)
-#define RTC_WEEKDAY_SUNDAY             ((uint8_t)0x07U)
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions
-  * @{
-  */ 
-#define RTC_ALARMDATEWEEKDAYSEL_DATE      ((uint32_t)0x00000000U)
-#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY   ((uint32_t)0x40000000U)
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions
-  * @{
-  */ 
-#define RTC_ALARMMASK_NONE                ((uint32_t)0x00000000U)
-#define RTC_ALARMMASK_DATEWEEKDAY         RTC_ALRMAR_MSK4
-#define RTC_ALARMMASK_HOURS               RTC_ALRMAR_MSK3
-#define RTC_ALARMMASK_MINUTES             RTC_ALRMAR_MSK2
-#define RTC_ALARMMASK_SECONDS             RTC_ALRMAR_MSK1
-#define RTC_ALARMMASK_ALL                 ((uint32_t)0x80808080U)
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
-  * @{
-  */ 
-#define RTC_ALARM_A                       RTC_CR_ALRAE
-#define RTC_ALARM_B                       RTC_CR_ALRBE
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
-  * @{
-  */ 
-#define RTC_ALARMSUBSECONDMASK_ALL         ((uint32_t)0x00000000U)  /*!< All Alarm SS fields are masked. 
-                                                                        There is no comparison on sub seconds 
-                                                                        for Alarm */
-#define RTC_ALARMSUBSECONDMASK_SS14_1      ((uint32_t)0x01000000U)  /*!< SS[14:1] are don't care in Alarm 
-                                                                        comparison. Only SS[0] is compared.    */
-#define RTC_ALARMSUBSECONDMASK_SS14_2      ((uint32_t)0x02000000U)  /*!< SS[14:2] are don't care in Alarm 
-                                                                        comparison. Only SS[1:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_3      ((uint32_t)0x03000000U)  /*!< SS[14:3] are don't care in Alarm 
-                                                                        comparison. Only SS[2:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_4      ((uint32_t)0x04000000U)  /*!< SS[14:4] are don't care in Alarm 
-                                                                        comparison. Only SS[3:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_5      ((uint32_t)0x05000000U)  /*!< SS[14:5] are don't care in Alarm 
-                                                                        comparison. Only SS[4:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_6      ((uint32_t)0x06000000U)  /*!< SS[14:6] are don't care in Alarm 
-                                                                        comparison. Only SS[5:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_7      ((uint32_t)0x07000000U)  /*!< SS[14:7] are don't care in Alarm 
-                                                                        comparison. Only SS[6:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_8      ((uint32_t)0x08000000U)  /*!< SS[14:8] are don't care in Alarm 
-                                                                        comparison. Only SS[7:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_9      ((uint32_t)0x09000000U)  /*!< SS[14:9] are don't care in Alarm 
-                                                                        comparison. Only SS[8:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_10     ((uint32_t)0x0A000000U)  /*!< SS[14:10] are don't care in Alarm 
-                                                                        comparison. Only SS[9:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_11     ((uint32_t)0x0B000000U)  /*!< SS[14:11] are don't care in Alarm 
-                                                                        comparison. Only SS[10:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_12     ((uint32_t)0x0C000000U)  /*!< SS[14:12] are don't care in Alarm 
-                                                                        comparison.Only SS[11:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_13     ((uint32_t)0x0D000000U)  /*!< SS[14:13] are don't care in Alarm 
-                                                                        comparison. Only SS[12:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14        ((uint32_t)0x0E000000U)  /*!< SS[14] is don't care in Alarm 
-                                                                        comparison.Only SS[13:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_NONE        ((uint32_t)0x0F000000U)  /*!< SS[14:0] are compared and must match 
-                                                                        to activate alarm. */
-/**
-  * @}
-  */   
-
-/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
-  * @{
-  */ 
-#define RTC_IT_TS                         ((uint32_t)0x00008000U)
-#define RTC_IT_WUT                        ((uint32_t)0x00004000U)
-#define RTC_IT_ALRB                       ((uint32_t)0x00002000U)
-#define RTC_IT_ALRA                       ((uint32_t)0x00001000U)
-#define RTC_IT_TAMP                       ((uint32_t)0x00000004U) /* Used only to Enable the Tamper Interrupt */
-#define RTC_IT_TAMP1                      ((uint32_t)0x00020000U)
-#define RTC_IT_TAMP2                      ((uint32_t)0x00040000U)
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Flags_Definitions RTC Flags Definitions
-  * @{
-  */ 
-#define RTC_FLAG_RECALPF                  ((uint32_t)0x00010000U)
-#define RTC_FLAG_TAMP2F                   ((uint32_t)0x00004000U)
-#define RTC_FLAG_TAMP1F                   ((uint32_t)0x00002000U)
-#define RTC_FLAG_TSOVF                    ((uint32_t)0x00001000U)
-#define RTC_FLAG_TSF                      ((uint32_t)0x00000800U)
-#define RTC_FLAG_WUTF                     ((uint32_t)0x00000400U)
-#define RTC_FLAG_ALRBF                    ((uint32_t)0x00000200U)
-#define RTC_FLAG_ALRAF                    ((uint32_t)0x00000100U)
-#define RTC_FLAG_INITF                    ((uint32_t)0x00000040U)
-#define RTC_FLAG_RSF                      ((uint32_t)0x00000020U)
-#define RTC_FLAG_INITS                    ((uint32_t)0x00000010U)
-#define RTC_FLAG_SHPF                     ((uint32_t)0x00000008U)
-#define RTC_FLAG_WUTWF                    ((uint32_t)0x00000004U)
-#define RTC_FLAG_ALRBWF                   ((uint32_t)0x00000002U)
-#define RTC_FLAG_ALRAWF                   ((uint32_t)0x00000001U)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-  
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RTC_Exported_Macros RTC Exported Macros
-  * @{
-  */
-
-/** @brief Reset RTC handle state
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
-
-/**
-  * @brief  Disable the write protection for RTC registers.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)             \
-                        do{                                       \
-                            (__HANDLE__)->Instance->WPR = 0xCAU;  \
-                            (__HANDLE__)->Instance->WPR = 0x53U;  \
-                          } while(0)
-
-/**
-  * @brief  Enable the write protection for RTC registers.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)              \
-                        do{                                       \
-                            (__HANDLE__)->Instance->WPR = 0xFFU;  \
-                          } while(0)                            
- 
-/**
-  * @brief  Enable the RTC ALARMA peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__)                           ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
-
-/**
-  * @brief  Disable the RTC ALARMA peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__)                          ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
-
-/**
-  * @brief  Enable the RTC ALARMB peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__)                           ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
-
-/**
-  * @brief  Disable the RTC ALARMB peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__)                          ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
-
-/**
-  * @brief  Enable the RTC Alarm interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. 
-  *          This parameter can be any combination of the following values:
-  *             @arg RTC_IT_ALRA: Alarm A interrupt
-  *             @arg RTC_IT_ALRB: Alarm B interrupt  
-  * @retval None
-  */   
-#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__)          ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the RTC Alarm interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. 
-  *         This parameter can be any combination of the following values:
-  *            @arg RTC_IT_ALRA: Alarm A interrupt
-  *            @arg RTC_IT_ALRB: Alarm B interrupt  
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
-
-/**
-  * @brief  Check whether the specified RTC Alarm interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt to check.
-  *         This parameter can be:
-  *            @arg RTC_IT_ALRA: Alarm A interrupt
-  *            @arg RTC_IT_ALRB: Alarm B interrupt  
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__)           (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
-
-/**
-  * @brief  Get the selected RTC Alarm's flag status.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Alarm Flag to check.
-  *         This parameter can be:
-  *            @arg RTC_FLAG_ALRAF
-  *            @arg RTC_FLAG_ALRBF
-  *            @arg RTC_FLAG_ALRAWF     
-  *            @arg RTC_FLAG_ALRBWF    
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__)                (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
-
-/**
-  * @brief  Clear the RTC Alarm's pending flags.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
-  *          This parameter can be:
-  *             @arg RTC_FLAG_ALRAF
-  *             @arg RTC_FLAG_ALRBF 
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)                  ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-  
-  
-/**
-  * @brief  Check whether the specified RTC Alarm interrupt has been enabled or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to check.
-  *         This parameter can be:
-  *            @arg RTC_IT_ALRA: Alarm A interrupt
-  *            @arg RTC_IT_ALRB: Alarm B interrupt
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
-
-/**
-  * @brief  Enable interrupt on the RTC Alarm associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_IT()            (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
-  * @brief  Disable interrupt on the RTC Alarm associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_IT()           (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
-
-/**
-  * @brief  Enable event on the RTC Alarm associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT()         (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
-  * @brief  Disable event on the RTC Alarm associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT()         (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
-
-/**
-  * @brief  Enable falling edge trigger on the RTC Alarm associated Exti line.  
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
-  * @brief  Disable falling edge trigger on the RTC Alarm associated Exti line.  
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
-
-/**
-  * @brief  Enable rising edge trigger on the RTC Alarm associated Exti line.  
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
-  * @brief  Disable rising edge trigger on the RTC Alarm associated Exti line.  
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
-
-/**
-  * @brief  Enable rising & falling edge trigger on the RTC Alarm associated Exti line.  
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); \
-                                                               __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();\
-                                                             } while(0)  
-
-/**
-  * @brief  Disable rising & falling edge trigger on the RTC Alarm associated Exti line.  
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();\
-                                                                __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();\
-                                                              } while(0)   
-
-/**
-  * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
-  * @retval Line Status.
-  */
-#define __HAL_RTC_ALARM_EXTI_GET_FLAG()              (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
-  * @brief Clear the RTC Alarm associated Exti line flag.
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()            (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
-  * @brief Generate a Software interrupt on RTC Alarm associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()         (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT)
-/**
-  * @}
-  */
-
-/* Include RTC HAL Extension module */
-#include "stm32f4xx_hal_rtc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RTC_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup RTC_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization and de-initialization functions  ****************************/
-HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
-void       HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
-void       HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
-/**
-  * @}
-  */
-
-/** @addtogroup RTC_Exported_Functions_Group2
-  * @{
-  */
-/* RTC Time and Date functions ************************************************/
-HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
-/**
-  * @}
-  */
-
-/** @addtogroup RTC_Exported_Functions_Group3
-  * @{
-  */
-/* RTC Alarm functions ********************************************************/
-HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
-HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
-void                HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef   HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-void         HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
-/**
-  * @}
-  */
-
-/** @addtogroup RTC_Exported_Functions_Group4
-  * @{
-  */
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef   HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);
-/**
-  * @}
-  */
-
-/** @addtogroup RTC_Exported_Functions_Group5
-  * @{
-  */
-/* Peripheral State functions *************************************************/
-HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RTC_Private_Constants RTC Private Constants
-  * @{
-  */
-/* Masks Definition */
-#define RTC_TR_RESERVED_MASK    ((uint32_t)0x007F7F7FU)
-#define RTC_DR_RESERVED_MASK    ((uint32_t)0x00FFFF3FU) 
-#define RTC_INIT_MASK           ((uint32_t)0xFFFFFFFFU)  
-#define RTC_RSF_MASK            ((uint32_t)0xFFFFFF5FU)
-#define RTC_FLAGS_MASK          ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \
-                                            RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \
-                                            RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \
-                                            RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F | \
-                                            RTC_FLAG_RECALPF | RTC_FLAG_SHPF))
-
-#define RTC_TIMEOUT_VALUE       1000
-
-#define RTC_EXTI_LINE_ALARM_EVENT             ((uint32_t)EXTI_IMR_MR17)  /*!< External interrupt line 17 Connected to the RTC Alarm event */
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup RTC_Private_Macros RTC Private Macros
-  * @{
-  */
-
-/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
-  * @{
-  */
-#define IS_RTC_HOUR_FORMAT(FORMAT)     (((FORMAT) == RTC_HOURFORMAT_12) || \
-                                        ((FORMAT) == RTC_HOURFORMAT_24))
-#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
-                               ((OUTPUT) == RTC_OUTPUT_ALARMA)  || \
-                               ((OUTPUT) == RTC_OUTPUT_ALARMB)  || \
-                               ((OUTPUT) == RTC_OUTPUT_WAKEUP))
-#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
-                                ((POL) == RTC_OUTPUT_POLARITY_LOW))
-#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
-                                  ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
-#define IS_RTC_HOUR12(HOUR)            (((HOUR) > (uint32_t)0U) && ((HOUR) <= (uint32_t)12U))
-#define IS_RTC_HOUR24(HOUR)            ((HOUR) <= (uint32_t)23U)
-#define IS_RTC_ASYNCH_PREDIV(PREDIV)   ((PREDIV) <= (uint32_t)0x7FU)
-#define IS_RTC_SYNCH_PREDIV(PREDIV)    ((PREDIV) <= (uint32_t)0x7FFFU)
-#define IS_RTC_MINUTES(MINUTES)        ((MINUTES) <= (uint32_t)59U)
-#define IS_RTC_SECONDS(SECONDS)        ((SECONDS) <= (uint32_t)59U)
-
-#define IS_RTC_HOURFORMAT12(PM)  (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))
-#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
-                                      ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
-                                      ((SAVE) == RTC_DAYLIGHTSAVING_NONE))
-#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
-                                           ((OPERATION) == RTC_STOREOPERATION_SET))
-#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
-#define IS_RTC_YEAR(YEAR)              ((YEAR) <= (uint32_t)99U)
-#define IS_RTC_MONTH(MONTH)            (((MONTH) >= (uint32_t)1U) && ((MONTH) <= (uint32_t)12U))
-#define IS_RTC_DATE(DATE)              (((DATE) >= (uint32_t)1U) && ((DATE) <= (uint32_t)31U))
-#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
-                                 ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
-                                 ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
-                                 ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
-                                 ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
-                                 ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
-                                 ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
-#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0U) && ((DATE) <= (uint32_t)31U))
-#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
-                                                    ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
-                                                    ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
-                                                    ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
-                                                    ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
-                                                    ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
-                                                    ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
-#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
-                                            ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
-#define IS_RTC_ALARM_MASK(MASK)  (((MASK) & 0x7F7F7F7FU) == (uint32_t)RESET)
-#define IS_RTC_ALARM(ALARM)      (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
-#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00007FFFU)
-
-#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK)   (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_NONE))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup RTC_Private_Functions RTC Private Functions
-  * @{
-  */
-HAL_StatusTypeDef  RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
-uint8_t            RTC_ByteToBcd2(uint8_t Value);
-uint8_t            RTC_Bcd2ToByte(uint8_t Value);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_RTC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_rtc_ex.h b/stmhal/hal/f4/inc/stm32f4xx_hal_rtc_ex.h
deleted file mode 100644
index 2f1ee02b4c..0000000000
--- a/stmhal/hal/f4/inc/stm32f4xx_hal_rtc_ex.h
+++ /dev/null
@@ -1,1005 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_rtc_ex.h
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   Header file of RTC HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_RTC_EX_H
-#define __STM32F4xx_HAL_RTC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup RTCEx
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup RTCEx_Exported_Types RTCEx Exported Types
-  * @{
-  */
-
-/** 
-  * @brief  RTC Tamper structure definition  
-  */
-typedef struct 
-{
-  uint32_t Tamper;                      /*!< Specifies the Tamper Pin.
-                                             This parameter can be a value of @ref  RTCEx_Tamper_Pins_Definitions */
-
-  uint32_t PinSelection;                /*!< Specifies the Tamper Pin.
-                                             This parameter can be a value of @ref  RTCEx_Tamper_Pins_Selection */
-
-  uint32_t Trigger;                     /*!< Specifies the Tamper Trigger.
-                                             This parameter can be a value of @ref  RTCEx_Tamper_Trigger_Definitions */
-
-  uint32_t Filter;                      /*!< Specifies the RTC Filter Tamper.
-                                             This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */
-
-  uint32_t SamplingFrequency;           /*!< Specifies the sampling frequency.
-                                             This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies_Definitions */
-
-  uint32_t PrechargeDuration;           /*!< Specifies the Precharge Duration .
-                                             This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */ 
-
-  uint32_t TamperPullUp;                /*!< Specifies the Tamper PullUp .
-                                             This parameter can be a value of @ref RTCEx_Tamper_Pull_UP_Definitions */           
-
-  uint32_t TimeStampOnTamperDetection;  /*!< Specifies the TimeStampOnTamperDetection.
-                                             This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */
-}RTC_TamperTypeDef;
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants
-  * @{
-  */ 
-
-/** @defgroup RTCEx_Backup_Registers_Definitions RTC Backup Registers Definitions
-  * @{
-  */
-#define RTC_BKP_DR0                       ((uint32_t)0x00000000U)
-#define RTC_BKP_DR1                       ((uint32_t)0x00000001U)
-#define RTC_BKP_DR2                       ((uint32_t)0x00000002U)
-#define RTC_BKP_DR3                       ((uint32_t)0x00000003U)
-#define RTC_BKP_DR4                       ((uint32_t)0x00000004U)
-#define RTC_BKP_DR5                       ((uint32_t)0x00000005U)
-#define RTC_BKP_DR6                       ((uint32_t)0x00000006U)
-#define RTC_BKP_DR7                       ((uint32_t)0x00000007U)
-#define RTC_BKP_DR8                       ((uint32_t)0x00000008U)
-#define RTC_BKP_DR9                       ((uint32_t)0x00000009U)
-#define RTC_BKP_DR10                      ((uint32_t)0x0000000AU)
-#define RTC_BKP_DR11                      ((uint32_t)0x0000000BU)
-#define RTC_BKP_DR12                      ((uint32_t)0x0000000CU)
-#define RTC_BKP_DR13                      ((uint32_t)0x0000000DU)
-#define RTC_BKP_DR14                      ((uint32_t)0x0000000EU)
-#define RTC_BKP_DR15                      ((uint32_t)0x0000000FU)
-#define RTC_BKP_DR16                      ((uint32_t)0x00000010U)
-#define RTC_BKP_DR17                      ((uint32_t)0x00000011U)
-#define RTC_BKP_DR18                      ((uint32_t)0x00000012U)
-#define RTC_BKP_DR19                      ((uint32_t)0x00000013U)
-/**
-  * @}
-  */ 
-
-/** @defgroup RTCEx_Time_Stamp_Edges_definitions RTC TimeStamp Edges Definitions
-  * @{
-  */ 
-#define RTC_TIMESTAMPEDGE_RISING          ((uint32_t)0x00000000U)
-#define RTC_TIMESTAMPEDGE_FALLING         ((uint32_t)0x00000008U)
-/**
-  * @}
-  */
-  
-/** @defgroup RTCEx_Tamper_Pins_Definitions RTC Tamper Pins Definitions
-  * @{
-  */ 
-#define RTC_TAMPER_1                    RTC_TAFCR_TAMP1E
-#define RTC_TAMPER_2                    RTC_TAFCR_TAMP2E
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_Pins_Selection RTC tamper Pins Selection
-  * @{
-  */ 
-#define RTC_TAMPERPIN_DEFAULT               ((uint32_t)0x00000000U)
-#define RTC_TAMPERPIN_POS1                  ((uint32_t)0x00010000U)
-/**
-  * @}
-  */ 
-
-/** @defgroup RTCEx_TimeStamp_Pin_Selection RTC TimeStamp Pins Selection
-  * @{
-  */ 
-#define RTC_TIMESTAMPPIN_DEFAULT            ((uint32_t)0x00000000U)
-#define RTC_TIMESTAMPPIN_POS1               ((uint32_t)0x00020000U)
-/**
-  * @}
-  */ 
-
-/** @defgroup RTCEx_Tamper_Trigger_Definitions RTC Tamper Triggers Definitions
-  * @{
-  */ 
-#define RTC_TAMPERTRIGGER_RISINGEDGE       ((uint32_t)0x00000000U)
-#define RTC_TAMPERTRIGGER_FALLINGEDGE      ((uint32_t)0x00000002U)
-#define RTC_TAMPERTRIGGER_LOWLEVEL         RTC_TAMPERTRIGGER_RISINGEDGE
-#define RTC_TAMPERTRIGGER_HIGHLEVEL        RTC_TAMPERTRIGGER_FALLINGEDGE
-/**
-  * @}
-  */  
-
-/** @defgroup RTCEx_Tamper_Filter_Definitions RTC Tamper Filter Definitions
-  * @{
-  */ 
-#define RTC_TAMPERFILTER_DISABLE   ((uint32_t)0x00000000U)  /*!< Tamper filter is disabled */
-
-#define RTC_TAMPERFILTER_2SAMPLE   ((uint32_t)0x00000800U)  /*!< Tamper is activated after 2 
-                                                                consecutive samples at the active level */
-#define RTC_TAMPERFILTER_4SAMPLE   ((uint32_t)0x00001000U)  /*!< Tamper is activated after 4 
-                                                                consecutive samples at the active level */
-#define RTC_TAMPERFILTER_8SAMPLE   ((uint32_t)0x00001800U)  /*!< Tamper is activated after 8 
-                                                                consecutive samples at the active level. */
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTC Tamper Sampling Frequencies Definitions
-  * @{
-  */ 
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768  ((uint32_t)0x00000000U)  /*!< Each of the tamper inputs are sampled
-                                                                             with a frequency =  RTCCLK / 32768 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384  ((uint32_t)0x00000100U)  /*!< Each of the tamper inputs are sampled
-                                                                             with a frequency =  RTCCLK / 16384 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192   ((uint32_t)0x00000200U)  /*!< Each of the tamper inputs are sampled
-                                                                             with a frequency =  RTCCLK / 8192  */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096   ((uint32_t)0x00000300U)  /*!< Each of the tamper inputs are sampled
-                                                                             with a frequency =  RTCCLK / 4096  */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048   ((uint32_t)0x00000400U)  /*!< Each of the tamper inputs are sampled
-                                                                             with a frequency =  RTCCLK / 2048  */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024   ((uint32_t)0x00000500U)  /*!< Each of the tamper inputs are sampled
-                                                                             with a frequency =  RTCCLK / 1024  */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512    ((uint32_t)0x00000600U)  /*!< Each of the tamper inputs are sampled
-                                                                             with a frequency =  RTCCLK / 512   */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256    ((uint32_t)0x00000700U)  /*!< Each of the tamper inputs are sampled
-                                                                             with a frequency =  RTCCLK / 256   */
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTC Tamper Pin Precharge Duration Definitions
-  * @{
-  */ 
-#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000U)  /*!< Tamper pins are pre-charged before 
-                                                                         sampling during 1 RTCCLK cycle */
-#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000U)  /*!< Tamper pins are pre-charged before 
-                                                                         sampling during 2 RTCCLK cycles */
-#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000U)  /*!< Tamper pins are pre-charged before 
-                                                                         sampling during 4 RTCCLK cycles */
-#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000U)  /*!< Tamper pins are pre-charged before 
-                                                                         sampling during 8 RTCCLK cycles */
-/**
-  * @}
-  */
-  
-/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTC Tamper TimeStamp On Tamper Detection Definitions
-  * @{
-  */ 
-#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE  ((uint32_t)RTC_TAFCR_TAMPTS)  /*!< TimeStamp on Tamper Detection event saved        */
-#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000U)        /*!< TimeStamp on Tamper Detection event is not saved */
-/**
-  * @}
-  */
-  
-/** @defgroup  RTCEx_Tamper_Pull_UP_Definitions RTC Tamper Pull Up Definitions
-  * @{
-  */ 
-#define RTC_TAMPER_PULLUP_ENABLE  ((uint32_t)0x00000000U)            /*!< TimeStamp on Tamper Detection event saved        */
-#define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAFCR_TAMPPUDIS)   /*!< TimeStamp on Tamper Detection event is not saved */
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Wakeup_Timer_Definitions RTC Wake-up Timer Definitions
-  * @{
-  */ 
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV16        ((uint32_t)0x00000000U)
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV8         ((uint32_t)0x00000001U)
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV4         ((uint32_t)0x00000002U)
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV2         ((uint32_t)0x00000003U)
-#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS      ((uint32_t)0x00000004U)
-#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS      ((uint32_t)0x00000006U)
-/**
-  * @}
-  */ 
-
-/** @defgroup RTCEx_Digital_Calibration_Definitions RTC Digital Calib Definitions
-  * @{
-  */ 
-#define RTC_CALIBSIGN_POSITIVE            ((uint32_t)0x00000000U) 
-#define RTC_CALIBSIGN_NEGATIVE            ((uint32_t)0x00000080U)
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Smooth_calib_period_Definitions RTC Smooth Calib Period Definitions
-  * @{
-  */ 
-#define RTC_SMOOTHCALIB_PERIOD_32SEC   ((uint32_t)0x00000000U)  /*!< If RTCCLK = 32768 Hz, Smooth calibration
-                                                                    period is 32s,  else 2exp20 RTCCLK seconds */
-#define RTC_SMOOTHCALIB_PERIOD_16SEC   ((uint32_t)0x00002000U)  /*!< If RTCCLK = 32768 Hz, Smooth calibration 
-                                                                    period is 16s, else 2exp19 RTCCLK seconds */
-#define RTC_SMOOTHCALIB_PERIOD_8SEC    ((uint32_t)0x00004000U)  /*!< If RTCCLK = 32768 Hz, Smooth calibration 
-                                                                    period is 8s, else 2exp18 RTCCLK seconds */
-/**
-  * @}
-  */ 
-
-/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTC Smooth Calib Plus Pulses Definitions
-  * @{
-  */ 
-#define RTC_SMOOTHCALIB_PLUSPULSES_SET    ((uint32_t)0x00008000U)  /*!< The number of RTCCLK pulses added  
-                                                                       during a X -second window = Y - CALM[8:0] 
-                                                                       with Y = 512, 256, 128 when X = 32, 16, 8 */
-#define RTC_SMOOTHCALIB_PLUSPULSES_RESET  ((uint32_t)0x00000000U)  /*!< The number of RTCCLK pulses subbstited
-                                                                       during a 32-second window = CALM[8:0] */
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Add_1_Second_Parameter_Definitions RTC Add 1 Second Parameter Definitions
-  * @{
-  */ 
-#define RTC_SHIFTADD1S_RESET      ((uint32_t)0x00000000U)
-#define RTC_SHIFTADD1S_SET        ((uint32_t)0x80000000U)
-/**
-  * @}
-  */ 
-
-
- /** @defgroup RTCEx_Calib_Output_selection_Definitions RTC Calib Output Selection Definitions
-  * @{
-  */ 
-#define RTC_CALIBOUTPUT_512HZ            ((uint32_t)0x00000000U) 
-#define RTC_CALIBOUTPUT_1HZ              ((uint32_t)0x00080000U)
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-  
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros
-  * @{
-  */
-
-/* ---------------------------------WAKEUPTIMER---------------------------------*/
-/** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer
-  * @{
-  */
-
-/**
-  * @brief  Enable the RTC WakeUp Timer peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
-
-/**
-  * @brief  Disable the RTC Wake-up Timer peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__)                     ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
-
-/**
-  * @brief  Enable the RTC WakeUpTimer interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. 
-  *         This parameter can be:
-  *            @arg RTC_IT_WUT: WakeUpTimer A interrupt
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the RTC WakeUpTimer interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. 
-  *         This parameter can be:
-  *            @arg RTC_IT_WUT: WakeUpTimer A interrupt
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
-
-/**
-  * @brief  Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC WakeUpTimer interrupt to check.
-  *         This parameter can be:
-  *            @arg RTC_IT_WUT:  WakeUpTimer A interrupt
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__)            (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
-
-/**
-  * @brief  Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Wake Up timer interrupt sources to check.
-  *         This parameter can be:
-  *            @arg RTC_IT_WUT:  WakeUpTimer interrupt
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)   (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
-
-/**
-  * @brief  Get the selected RTC WakeUpTimer's flag status.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC WakeUpTimer Flag to check.
-  *          This parameter can be:
-  *             @arg RTC_FLAG_WUTF   
-  *             @arg RTC_FLAG_WUTWF     
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__)          (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
-
-/**
-  * @brief  Clear the RTC Wake Up timer's pending flags.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
-  *         This parameter can be:
-  *            @arg RTC_FLAG_WUTF   
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__)            ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) 
-
-/**
-  * @brief  Enable interrupt on the RTC Wake-up Timer associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT()       (EXTI->IMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
-  * @brief  Disable interrupt on the RTC Wake-up Timer associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT()      (EXTI->IMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
-
-/**
-  * @brief  Enable event on the RTC Wake-up Timer associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT()    (EXTI->EMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
-  * @brief  Disable event on the RTC Wake-up Timer associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT()   (EXTI->EMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
-
-/**
-  * @brief  Enable falling edge trigger on the RTC Wake-up Timer associated Exti line. 
-  * @retval None.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
-  * @brief  Disable falling edge trigger on the RTC Wake-up Timer associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
-
-/**
-  * @brief  Enable rising edge trigger on the RTC Wake-up Timer associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
-  * @brief  Disable rising edge trigger on the RTC Wake-up Timer associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
-
-/**
-  * @brief  Enable rising & falling edge trigger on the RTC Wake-up Timer associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();\
-                                                                     __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();\
-                                                                   } while(0)  
-
-/**
-  * @brief  Disable rising & falling edge trigger on the RTC Wake-up Timer associated Exti line.
-  * This parameter can be:
-  * @retval None.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();\
-                                                                      __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();\
-                                                                    } while(0)  
-
-/**
-  * @brief Check whether the RTC Wake-up Timer associated Exti line interrupt flag is set or not.
-  * @retval Line Status.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG()              (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
-  * @brief Clear the RTC Wake-up Timer associated Exti line flag.
-  * @retval None.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG()            (EXTI->PR = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
-  * @brief Generate a Software interrupt on the RTC Wake-up Timer associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT()         (EXTI->SWIER |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
-  * @}
-  */
-
-/* ---------------------------------TIMESTAMP---------------------------------*/
-/** @defgroup RTCEx_Timestamp RTC Timestamp
-  * @{
-  */
-
-/**
-  * @brief  Enable the RTC TimeStamp peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__)                        ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
-
-/**
-  * @brief  Disable the RTC TimeStamp peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__)                       ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
-
-/**
-  * @brief  Enable the RTC TimeStamp interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled. 
-  *         This parameter can be:
-  *            @arg RTC_IT_TS: TimeStamp interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the RTC TimeStamp interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled. 
-  *         This parameter can be:
-  *            @arg RTC_IT_TS: TimeStamp interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
-
-/**
-  * @brief  Check whether the specified RTC TimeStamp interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC TimeStamp interrupt to check.
-  *         This parameter can be:
-  *            @arg RTC_IT_TS: TimeStamp interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__)         (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
-
-/**
-  * @brief  Check whether the specified RTC Time Stamp interrupt has been enabled or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Time Stamp interrupt source to check.
-  *         This parameter can be:
-  *            @arg RTC_IT_TS: TimeStamp interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
-
-/**
-  * @brief  Get the selected RTC TimeStamp's flag status.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC TimeStamp flag to check.
-  *         This parameter can be:
-  *            @arg RTC_FLAG_TSF   
-  *            @arg RTC_FLAG_TSOVF     
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)            (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
-
-/**
-  * @brief  Clear the RTC Time Stamp's pending flags.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
-  *          This parameter can be:
-  *             @arg RTC_FLAG_TSF  
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)          ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-/**
-  * @}
-  */
-
-/* ---------------------------------TAMPER------------------------------------*/
-/** @defgroup RTCEx_Tamper RTC Tamper
-  * @{
-  */
-
-/**
-  * @brief  Enable the RTC Tamper1 input detection.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP1E))
-
-/**
-  * @brief  Disable the RTC Tamper1 input detection.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP1E))
-
-/**
-  * @brief  Enable the RTC Tamper2 input detection.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP2E))
-
-/**
-  * @brief  Disable the RTC Tamper2 input detection.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP2E))
-
-/**
-  * @brief  Check whether the specified RTC Tamper interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Tamper interrupt to check.
-  *         This parameter can be:
-  *            @arg  RTC_IT_TAMP1
-  *            @arg  RTC_IT_TAMP2
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)       (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
-
-/**
-  * @brief  Check whether the specified RTC Tamper interrupt has been enabled or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Tamper interrupt source to check.
-  *         This parameter can be:
-  *            @arg RTC_IT_TAMP: Tamper interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->TAFCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
-
-/**
-  * @brief  Get the selected RTC Tamper's flag status.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
-  *          This parameter can be:
-  *             @arg RTC_FLAG_TAMP1F 
-  *             @arg RTC_FLAG_TAMP2F  
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__)               (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
-
-/**
-  * @brief  Clear the RTC Tamper's pending flags.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Tamper Flag to clear.
-  *          This parameter can be:
-  *             @arg RTC_FLAG_TAMP1F
-  *             @arg RTC_FLAG_TAMP2F 
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__)         ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-/**
-  * @}
-  */
-
-/* --------------------------TAMPER/TIMESTAMP---------------------------------*/
-/** @defgroup RTCEx_Tamper_Timestamp EXTI RTC Tamper Timestamp EXTI
-  * @{
-  */
-
-/**
-  * @brief  Enable interrupt on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()        (EXTI->IMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
-  * @brief  Disable interrupt on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()       (EXTI->IMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
-
-/**
-  * @brief  Enable event on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT()    (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
-  * @brief  Disable event on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT()   (EXTI->EMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
-
-/**
-  * @brief  Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line. 
-  * @retval None.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
-  * @brief  Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
-
-/**
-  * @brief  Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
-  * @brief  Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
-
-/**
-  * @brief  Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();\
-                                                                          __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE(); \
-                                                                        } while(0)  
-
-/**
-  * @brief  Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
-  * This parameter can be:
-  * @retval None.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();\
-                                                                           __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE();\
-                                                                         } while(0)  
-
-/**
-  * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
-  * @retval Line Status.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()         (EXTI->PR & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
-  * @brief Clear the RTC Tamper and Timestamp associated Exti line flag.
-  * @retval None.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()       (EXTI->PR = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
-  * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line
-  * @retval None.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()    (EXTI->SWIER |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-/**
-  * @}
-  */
-
-/* ------------------------------Calibration----------------------------------*/
-/** @defgroup RTCEx_Calibration RTC Calibration
-  * @{
-  */
-
-/**
-  * @brief  Enable the Coarse calibration process.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_COARSE_CALIB_ENABLE(__HANDLE__)                       ((__HANDLE__)->Instance->CR |= (RTC_CR_DCE))
-
-/**
-  * @brief  Disable the Coarse calibration process.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_COARSE_CALIB_DISABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR &= ~(RTC_CR_DCE))
-
-/**
-  * @brief  Enable the RTC calibration output.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
-
-/**
-  * @brief  Disable the calibration output.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
-
-/**
-  * @brief  Enable the clock reference detection.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
-
-/**
-  * @brief  Disable the clock reference detection.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
-
-/**
-  * @brief  Get the selected RTC shift operation's flag status.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC shift operation Flag is pending or not.
-  *          This parameter can be:
-  *             @arg RTC_FLAG_SHPF   
-  * @retval None
-  */
-#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__)                (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
-  * @{
-  */
-
-/** @addtogroup RTCEx_Exported_Functions_Group1
-  * @{
-  */
-/* RTC TimeStamp and Tamper functions *****************************************/
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format);
-
-HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
-HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
-void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
-
-void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
-void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
-void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-/**
-  * @}
-  */
-
-/** @addtogroup RTCEx_Exported_Functions_Group2
-  * @{
-  */
-/* RTC Wake-up functions ******************************************************/
-HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
-HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
-uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
-uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
-void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
-void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-/**
-  * @}
-  */
-
-/** @addtogroup RTCEx_Exported_Functions_Group3
-  * @{
-  */
-/* Extension Control functions ************************************************/
-void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
-uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
-
-HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef *hrtc, uint32_t CalibSign, uint32_t Value);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue);
-HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS);
-HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);
-/**
-  * @}
-  */
-
-/** @addtogroup RTCEx_Exported_Functions_Group4
-  * @{
-  */
-/* Extension RTC features functions *******************************************/
-void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc); 
-HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RTCEx_Private_Constants RTCEx Private Constants
-  * @{
-  */
-#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT  ((uint32_t)EXTI_IMR_MR21)  /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
-#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT       ((uint32_t)EXTI_IMR_MR22)  /*!< External interrupt line 22 Connected to the RTC Wake-up event */
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup RTCEx_Private_Macros RTCEx Private Macros
-  * @{
-  */
-
-/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
-  * @{
-  */ 
-#define IS_RTC_BKP(BKP)                   (((BKP) == RTC_BKP_DR0)  || \
-                                           ((BKP) == RTC_BKP_DR1)  || \
-                                           ((BKP) == RTC_BKP_DR2)  || \
-                                           ((BKP) == RTC_BKP_DR3)  || \
-                                           ((BKP) == RTC_BKP_DR4)  || \
-                                           ((BKP) == RTC_BKP_DR5)  || \
-                                           ((BKP) == RTC_BKP_DR6)  || \
-                                           ((BKP) == RTC_BKP_DR7)  || \
-                                           ((BKP) == RTC_BKP_DR8)  || \
-                                           ((BKP) == RTC_BKP_DR9)  || \
-                                           ((BKP) == RTC_BKP_DR10) || \
-                                           ((BKP) == RTC_BKP_DR11) || \
-                                           ((BKP) == RTC_BKP_DR12) || \
-                                           ((BKP) == RTC_BKP_DR13) || \
-                                           ((BKP) == RTC_BKP_DR14) || \
-                                           ((BKP) == RTC_BKP_DR15) || \
-                                           ((BKP) == RTC_BKP_DR16) || \
-                                           ((BKP) == RTC_BKP_DR17) || \
-                                           ((BKP) == RTC_BKP_DR18) || \
-                                           ((BKP) == RTC_BKP_DR19))
-#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
-                                 ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
-#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & ((uint32_t)!(RTC_TAFCR_TAMP1E | RTC_TAFCR_TAMP2E))) == 0x00U) && ((TAMPER) != (uint32_t)RESET))
-
-#define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TAMPERPIN_DEFAULT) || \
-                                ((PIN) == RTC_TAMPERPIN_POS1))
-
-#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT) || \
-                                   ((PIN) == RTC_TIMESTAMPPIN_POS1))
-
-#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
-                                        ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
-                                        ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
-                                        ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL)) 
-#define IS_RTC_TAMPER_FILTER(FILTER)  (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \
-                                       ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \
-                                       ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \
-                                       ((FILTER) == RTC_TAMPERFILTER_8SAMPLE))
-#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
-                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
-                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
-                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
-                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
-                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
-                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512)  || \
-                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))
-#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
-                                                    ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
-                                                    ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
-                                                    ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))
-#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
-                                                              ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
-#define IS_RTC_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \
-                                           ((STATE) == RTC_TAMPER_PULLUP_DISABLE))
-#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16)   || \
-                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8)    || \
-                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4)    || \
-                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2)    || \
-                                    ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
-                                    ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
-
-#define IS_RTC_WAKEUP_COUNTER(COUNTER)  ((COUNTER) <= 0xFFFFU)
-#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CALIBSIGN_POSITIVE) || \
-                                 ((SIGN) == RTC_CALIBSIGN_NEGATIVE))
-
-#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20U)
-
-#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
-                                            ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
-                                            ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC)) 
-#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
-                                        ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
-
-#define  IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FFU)
-#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \
-                                 ((SEL) == RTC_SHIFTADD1S_SET)) 
-#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFFU)
-#define IS_RTC_CALIB_OUTPUT(OUTPUT)  (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
-                                      ((OUTPUT) == RTC_CALIBOUTPUT_1HZ))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_RTC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_sd.h b/stmhal/hal/f4/inc/stm32f4xx_hal_sd.h
deleted file mode 100644
index 03805b12cd..0000000000
--- a/stmhal/hal/f4/inc/stm32f4xx_hal_sd.h
+++ /dev/null
@@ -1,797 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_sd.h
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   Header file of SD HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_SD_H
-#define __STM32F4xx_HAL_SD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
-    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
-    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
-    defined(STM32F412Rx) || defined(STM32F412Cx)
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_ll_sdmmc.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup SD SD
-  * @brief SD HAL module driver
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup SD_Exported_Types SD Exported Types
-  * @{
-  */
-
-/** @defgroup SD_Exported_Types_Group1 SD Handle Structure definition   
-  * @{
-  */
-#define SD_InitTypeDef      SDIO_InitTypeDef 
-#define SD_TypeDef          SDIO_TypeDef
-
-typedef struct
-{
-  SD_TypeDef                   *Instance;        /*!< SDIO register base address                     */
-  
-  SD_InitTypeDef               Init;             /*!< SD required parameters                         */
-  
-  HAL_LockTypeDef              Lock;             /*!< SD locking object                              */
-  
-  uint32_t                     CardType;         /*!< SD card type                                   */
-  
-  uint32_t                     RCA;              /*!< SD relative card address                       */
-  
-  uint32_t                     CSD[4];           /*!< SD card specific data table                    */
-  
-  uint32_t                     CID[4];           /*!< SD card identification number table            */
-  
-  __IO uint32_t                SdTransferCplt;   /*!< SD transfer complete flag in non blocking mode */
-  
-  __IO uint32_t                SdTransferErr;    /*!< SD transfer error flag in non blocking mode    */
-  
-  __IO uint32_t                DmaTransferCplt;  /*!< SD DMA transfer complete flag                  */
-  
-  __IO uint32_t                SdOperation;      /*!< SD transfer operation (read/write)             */
-  
-  DMA_HandleTypeDef            *hdmarx;          /*!< SD Rx DMA handle parameters                    */
-  
-  DMA_HandleTypeDef            *hdmatx;          /*!< SD Tx DMA handle parameters                    */
-  
-}SD_HandleTypeDef;
-/** 
-  * @}
-  */
-
-/** @defgroup SD_Exported_Types_Group2 Card Specific Data: CSD Register 
-  * @{
-  */ 
-typedef struct
-{
-  __IO uint8_t  CSDStruct;            /*!< CSD structure                         */
-  __IO uint8_t  SysSpecVersion;       /*!< System specification version          */
-  __IO uint8_t  Reserved1;            /*!< Reserved                              */
-  __IO uint8_t  TAAC;                 /*!< Data read access time 1               */
-  __IO uint8_t  NSAC;                 /*!< Data read access time 2 in CLK cycles */
-  __IO uint8_t  MaxBusClkFrec;        /*!< Max. bus clock frequency              */
-  __IO uint16_t CardComdClasses;      /*!< Card command classes                  */
-  __IO uint8_t  RdBlockLen;           /*!< Max. read data block length           */
-  __IO uint8_t  PartBlockRead;        /*!< Partial blocks for read allowed       */
-  __IO uint8_t  WrBlockMisalign;      /*!< Write block misalignment              */
-  __IO uint8_t  RdBlockMisalign;      /*!< Read block misalignment               */
-  __IO uint8_t  DSRImpl;              /*!< DSR implemented                       */
-  __IO uint8_t  Reserved2;            /*!< Reserved                              */
-  __IO uint32_t DeviceSize;           /*!< Device Size                           */
-  __IO uint8_t  MaxRdCurrentVDDMin;   /*!< Max. read current @ VDD min           */
-  __IO uint8_t  MaxRdCurrentVDDMax;   /*!< Max. read current @ VDD max           */
-  __IO uint8_t  MaxWrCurrentVDDMin;   /*!< Max. write current @ VDD min          */
-  __IO uint8_t  MaxWrCurrentVDDMax;   /*!< Max. write current @ VDD max          */
-  __IO uint8_t  DeviceSizeMul;        /*!< Device size multiplier                */
-  __IO uint8_t  EraseGrSize;          /*!< Erase group size                      */
-  __IO uint8_t  EraseGrMul;           /*!< Erase group size multiplier           */
-  __IO uint8_t  WrProtectGrSize;      /*!< Write protect group size              */
-  __IO uint8_t  WrProtectGrEnable;    /*!< Write protect group enable            */
-  __IO uint8_t  ManDeflECC;           /*!< Manufacturer default ECC              */
-  __IO uint8_t  WrSpeedFact;          /*!< Write speed factor                    */
-  __IO uint8_t  MaxWrBlockLen;        /*!< Max. write data block length          */
-  __IO uint8_t  WriteBlockPaPartial;  /*!< Partial blocks for write allowed      */
-  __IO uint8_t  Reserved3;            /*!< Reserved                              */
-  __IO uint8_t  ContentProtectAppli;  /*!< Content protection application        */
-  __IO uint8_t  FileFormatGrouop;     /*!< File format group                     */
-  __IO uint8_t  CopyFlag;             /*!< Copy flag (OTP)                       */
-  __IO uint8_t  PermWrProtect;        /*!< Permanent write protection            */
-  __IO uint8_t  TempWrProtect;        /*!< Temporary write protection            */
-  __IO uint8_t  FileFormat;           /*!< File format                           */
-  __IO uint8_t  ECC;                  /*!< ECC code                              */
-  __IO uint8_t  CSD_CRC;              /*!< CSD CRC                               */
-  __IO uint8_t  Reserved4;            /*!< Always 1                              */
-
-}HAL_SD_CSDTypedef;
-/** 
-  * @}
-  */
-
-/** @defgroup SD_Exported_Types_Group3 Card Identification Data: CID Register
-  * @{
-  */ 
-typedef struct
-{
-  __IO uint8_t  ManufacturerID;  /*!< Manufacturer ID       */
-  __IO uint16_t OEM_AppliID;     /*!< OEM/Application ID    */
-  __IO uint32_t ProdName1;       /*!< Product Name part1    */
-  __IO uint8_t  ProdName2;       /*!< Product Name part2    */
-  __IO uint8_t  ProdRev;         /*!< Product Revision      */
-  __IO uint32_t ProdSN;          /*!< Product Serial Number */
-  __IO uint8_t  Reserved1;       /*!< Reserved1             */
-  __IO uint16_t ManufactDate;    /*!< Manufacturing Date    */
-  __IO uint8_t  CID_CRC;         /*!< CID CRC               */
-  __IO uint8_t  Reserved2;       /*!< Always 1              */
-
-}HAL_SD_CIDTypedef;
-/** 
-  * @}
-  */
-
-/** @defgroup SD_Exported_Types_Group4 SD Card Status returned by ACMD13 
-  * @{
-  */ 
-typedef struct
-{
-  __IO uint8_t  DAT_BUS_WIDTH;           /*!< Shows the currently defined data bus width                 */
-  __IO uint8_t  SECURED_MODE;            /*!< Card is in secured mode of operation                       */
-  __IO uint16_t SD_CARD_TYPE;            /*!< Carries information about card type                        */
-  __IO uint32_t SIZE_OF_PROTECTED_AREA;  /*!< Carries information about the capacity of protected area   */
-  __IO uint8_t  SPEED_CLASS;             /*!< Carries information about the speed class of the card      */
-  __IO uint8_t  PERFORMANCE_MOVE;        /*!< Carries information about the card's performance move      */
-  __IO uint8_t  AU_SIZE;                 /*!< Carries information about the card's allocation unit size  */
-  __IO uint16_t ERASE_SIZE;              /*!< Determines the number of AUs to be erased in one operation */
-  __IO uint8_t  ERASE_TIMEOUT;           /*!< Determines the timeout for any number of AU erase          */
-  __IO uint8_t  ERASE_OFFSET;            /*!< Carries information about the erase offset                 */
-
-}HAL_SD_CardStatusTypedef;
-/** 
-  * @}
-  */
-
-/** @defgroup SD_Exported_Types_Group5 SD Card information structure 
-  * @{
-  */ 
-typedef struct
-{
-  HAL_SD_CSDTypedef   SD_csd;         /*!< SD card specific data register         */
-  HAL_SD_CIDTypedef   SD_cid;         /*!< SD card identification number register */
-  uint64_t            CardCapacity;   /*!< Card capacity                          */
-  uint32_t            CardBlockSize;  /*!< Card block size                        */
-  uint16_t            RCA;            /*!< SD relative card address               */
-  uint8_t             CardType;       /*!< SD card type                           */
-
-}HAL_SD_CardInfoTypedef;
-/** 
-  * @}
-  */
-
-/** @defgroup SD_Exported_Types_Group6 SD Error status enumeration Structure definition 
-  * @{
-  */ 
-typedef enum
-{
-/** 
-  * @brief  SD specific error defines  
-  */   
-  SD_CMD_CRC_FAIL                    = (1U),   /*!< Command response received (but CRC check failed)              */
-  SD_DATA_CRC_FAIL                   = (2U),   /*!< Data block sent/received (CRC check failed)                   */
-  SD_CMD_RSP_TIMEOUT                 = (3U),   /*!< Command response timeout                                      */
-  SD_DATA_TIMEOUT                    = (4U),   /*!< Data timeout                                                  */
-  SD_TX_UNDERRUN                     = (5U),   /*!< Transmit FIFO underrun                                        */
-  SD_RX_OVERRUN                      = (6U),   /*!< Receive FIFO overrun                                          */
-  SD_START_BIT_ERR                   = (7U),   /*!< Start bit not detected on all data signals in wide bus mode   */
-  SD_CMD_OUT_OF_RANGE                = (8U),   /*!< Command's argument was out of range.                          */
-  SD_ADDR_MISALIGNED                 = (9U),   /*!< Misaligned address                                            */
-  SD_BLOCK_LEN_ERR                   = (10U),  /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */
-  SD_ERASE_SEQ_ERR                   = (11U),  /*!< An error in the sequence of erase command occurs.            */
-  SD_BAD_ERASE_PARAM                 = (12U),  /*!< An invalid selection for erase groups                        */
-  SD_WRITE_PROT_VIOLATION            = (13U),  /*!< Attempt to program a write protect block                     */
-  SD_LOCK_UNLOCK_FAILED              = (14U),  /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */
-  SD_COM_CRC_FAILED                  = (15U),  /*!< CRC check of the previous command failed                     */
-  SD_ILLEGAL_CMD                     = (16U),  /*!< Command is not legal for the card state                      */
-  SD_CARD_ECC_FAILED                 = (17U),  /*!< Card internal ECC was applied but failed to correct the data */
-  SD_CC_ERROR                        = (18U),  /*!< Internal card controller error                               */
-  SD_GENERAL_UNKNOWN_ERROR           = (19U),  /*!< General or unknown error                                     */
-  SD_STREAM_READ_UNDERRUN            = (20U),  /*!< The card could not sustain data transfer in stream read operation. */
-  SD_STREAM_WRITE_OVERRUN            = (21U),  /*!< The card could not sustain data programming in stream mode   */
-  SD_CID_CSD_OVERWRITE               = (22U),  /*!< CID/CSD overwrite error                                      */
-  SD_WP_ERASE_SKIP                   = (23U),  /*!< Only partial address space was erased                        */
-  SD_CARD_ECC_DISABLED               = (24U),  /*!< Command has been executed without using internal ECC         */
-  SD_ERASE_RESET                     = (25U),  /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */
-  SD_AKE_SEQ_ERROR                   = (26U),  /*!< Error in sequence of authentication.                         */
-  SD_INVALID_VOLTRANGE               = (27U),
-  SD_ADDR_OUT_OF_RANGE               = (28U),
-  SD_SWITCH_ERROR                    = (29U),
-  SD_SDIO_DISABLED                   = (30U),
-  SD_SDIO_FUNCTION_BUSY              = (31U),
-  SD_SDIO_FUNCTION_FAILED            = (32U),
-  SD_SDIO_UNKNOWN_FUNCTION           = (33U),
-
-/** 
-  * @brief  Standard error defines   
-  */ 
-  SD_INTERNAL_ERROR                  = (34U),
-  SD_NOT_CONFIGURED                  = (35U),
-  SD_REQUEST_PENDING                 = (36U),
-  SD_REQUEST_NOT_APPLICABLE          = (37U),
-  SD_INVALID_PARAMETER               = (38U),
-  SD_UNSUPPORTED_FEATURE             = (39U),
-  SD_UNSUPPORTED_HW                  = (40U),
-  SD_ERROR                           = (41U),
-  SD_OK                              = (0U) 
-
-}HAL_SD_ErrorTypedef;
-/** 
-  * @}
-  */
-
-/** @defgroup SD_Exported_Types_Group7 SD Transfer state enumeration structure
-  * @{
-  */ 
-typedef enum
-{
-  SD_TRANSFER_OK    = 0U,  /*!< Transfer success      */
-  SD_TRANSFER_BUSY  = 1U,  /*!< Transfer is occurring */
-  SD_TRANSFER_ERROR = 2U   /*!< Transfer failed       */
-
-}HAL_SD_TransferStateTypedef;
-/** 
-  * @}
-  */
-
-/** @defgroup SD_Exported_Types_Group8 SD Card State enumeration structure
-  * @{
-  */  
-typedef enum
-{
-  SD_CARD_READY                  = ((uint32_t)0x00000001U),  /*!< Card state is ready                     */
-  SD_CARD_IDENTIFICATION         = ((uint32_t)0x00000002U),  /*!< Card is in identification state         */
-  SD_CARD_STANDBY                = ((uint32_t)0x00000003U),  /*!< Card is in standby state                */
-  SD_CARD_TRANSFER               = ((uint32_t)0x00000004U),  /*!< Card is in transfer state               */  
-  SD_CARD_SENDING                = ((uint32_t)0x00000005U),  /*!< Card is sending an operation            */
-  SD_CARD_RECEIVING              = ((uint32_t)0x00000006U),  /*!< Card is receiving operation information */
-  SD_CARD_PROGRAMMING            = ((uint32_t)0x00000007U),  /*!< Card is in programming state            */
-  SD_CARD_DISCONNECTED           = ((uint32_t)0x00000008U),  /*!< Card is disconnected                    */
-  SD_CARD_ERROR                  = ((uint32_t)0x000000FFU)   /*!< Card is in error state                  */
-
-}HAL_SD_CardStateTypedef;
-/** 
-  * @}
-  */
-
-/** @defgroup SD_Exported_Types_Group9 SD Operation enumeration structure
-  * @{
-  */  
-typedef enum
-{
-  SD_READ_SINGLE_BLOCK    = 0U,  /*!< Read single block operation      */
-  SD_READ_MULTIPLE_BLOCK  = 1U,  /*!< Read multiple blocks operation   */
-  SD_WRITE_SINGLE_BLOCK   = 2U,  /*!< Write single block operation     */
-  SD_WRITE_MULTIPLE_BLOCK = 3U   /*!< Write multiple blocks operation  */
-
-}HAL_SD_OperationTypedef;
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SD_Exported_Constants SD Exported Constants
-  * @{
-  */
-
-/** 
-  * @brief SD Commands Index 
-  */
-#define SD_CMD_GO_IDLE_STATE                       ((uint8_t)0U)   /*!< Resets the SD memory card.                                                               */
-#define SD_CMD_SEND_OP_COND                        ((uint8_t)1U)   /*!< Sends host capacity support information and activates the card's initialization process. */
-#define SD_CMD_ALL_SEND_CID                        ((uint8_t)2U)   /*!< Asks any card connected to the host to send the CID numbers on the CMD line.             */
-#define SD_CMD_SET_REL_ADDR                        ((uint8_t)3U)   /*!< Asks the card to publish a new relative address (RCA).                                   */
-#define SD_CMD_SET_DSR                             ((uint8_t)4U)   /*!< Programs the DSR of all cards.                                                           */
-#define SD_CMD_SDIO_SEN_OP_COND                    ((uint8_t)5U)   /*!< Sends host capacity support information (HCS) and asks the accessed card to send its 
-                                                                       operating condition register (OCR) content in the response on the CMD line.              */
-#define SD_CMD_HS_SWITCH                           ((uint8_t)6U)   /*!< Checks switchable function (mode 0) and switch card function (mode 1).                   */
-#define SD_CMD_SEL_DESEL_CARD                      ((uint8_t)7U)   /*!< Selects the card by its own relative address and gets deselected by any other address    */
-#define SD_CMD_HS_SEND_EXT_CSD                     ((uint8_t)8U)   /*!< Sends SD Memory Card interface condition, which includes host supply voltage information 
-                                                                       and asks the card whether card supports voltage.                                         */
-#define SD_CMD_SEND_CSD                            ((uint8_t)9U)   /*!< Addressed card sends its card specific data (CSD) on the CMD line.                       */
-#define SD_CMD_SEND_CID                            ((uint8_t)10U)  /*!< Addressed card sends its card identification (CID) on the CMD line.                      */
-#define SD_CMD_READ_DAT_UNTIL_STOP                 ((uint8_t)11U)  /*!< SD card doesn't support it.                                                              */
-#define SD_CMD_STOP_TRANSMISSION                   ((uint8_t)12U)  /*!< Forces the card to stop transmission.                                                    */
-#define SD_CMD_SEND_STATUS                         ((uint8_t)13U)  /*!< Addressed card sends its status register.                                                */
-#define SD_CMD_HS_BUSTEST_READ                     ((uint8_t)14U) 
-#define SD_CMD_GO_INACTIVE_STATE                   ((uint8_t)15U)  /*!< Sends an addressed card into the inactive state.                                         */
-#define SD_CMD_SET_BLOCKLEN                        ((uint8_t)16U)  /*!< Sets the block length (in bytes for SDSC) for all following block commands 
-                                                                       (read, write, lock). Default block length is fixed to 512 Bytes. Not effective 
-                                                                       for SDHS and SDXC.                                                                       */
-#define SD_CMD_READ_SINGLE_BLOCK                   ((uint8_t)17U)  /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of 
-                                                                       fixed 512 bytes in case of SDHC and SDXC.                                                */
-#define SD_CMD_READ_MULT_BLOCK                     ((uint8_t)18U)  /*!< Continuously transfers data blocks from card to host until interrupted by 
-                                                                       STOP_TRANSMISSION command.                                                               */
-#define SD_CMD_HS_BUSTEST_WRITE                    ((uint8_t)19U)  /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104.                                    */
-#define SD_CMD_WRITE_DAT_UNTIL_STOP                ((uint8_t)20U)  /*!< Speed class control command.                                                             */
-#define SD_CMD_SET_BLOCK_COUNT                     ((uint8_t)23U)  /*!< Specify block count for CMD18 and CMD25.                                                 */
-#define SD_CMD_WRITE_SINGLE_BLOCK                  ((uint8_t)24U)  /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of 
-                                                                       fixed 512 bytes in case of SDHC and SDXC.                                                */
-#define SD_CMD_WRITE_MULT_BLOCK                    ((uint8_t)25U)  /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows.                    */
-#define SD_CMD_PROG_CID                            ((uint8_t)26U)  /*!< Reserved for manufacturers.                                                              */
-#define SD_CMD_PROG_CSD                            ((uint8_t)27U)  /*!< Programming of the programmable bits of the CSD.                                         */
-#define SD_CMD_SET_WRITE_PROT                      ((uint8_t)28U)  /*!< Sets the write protection bit of the addressed group.                                    */
-#define SD_CMD_CLR_WRITE_PROT                      ((uint8_t)29U)  /*!< Clears the write protection bit of the addressed group.                                  */
-#define SD_CMD_SEND_WRITE_PROT                     ((uint8_t)30U)  /*!< Asks the card to send the status of the write protection bits.                           */
-#define SD_CMD_SD_ERASE_GRP_START                  ((uint8_t)32U)  /*!< Sets the address of the first write block to be erased. (For SD card only).              */
-#define SD_CMD_SD_ERASE_GRP_END                    ((uint8_t)33U)  /*!< Sets the address of the last write block of the continuous range to be erased.           */
-#define SD_CMD_ERASE_GRP_START                     ((uint8_t)35U)  /*!< Sets the address of the first write block to be erased. Reserved for each command 
-                                                                       system set by switch function command (CMD6).                                            */
-#define SD_CMD_ERASE_GRP_END                       ((uint8_t)36U)  /*!< Sets the address of the last write block of the continuous range to be erased. 
-                                                                       Reserved for each command system set by switch function command (CMD6).                  */
-#define SD_CMD_ERASE                               ((uint8_t)38U)  /*!< Reserved for SD security applications.                                                   */
-#define SD_CMD_FAST_IO                             ((uint8_t)39U)  /*!< SD card doesn't support it (Reserved).                                                   */
-#define SD_CMD_GO_IRQ_STATE                        ((uint8_t)40U)  /*!< SD card doesn't support it (Reserved).                                                   */
-#define SD_CMD_LOCK_UNLOCK                         ((uint8_t)42U)  /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by 
-                                                                       the SET_BLOCK_LEN command.                                                               */
-#define SD_CMD_APP_CMD                             ((uint8_t)55U)  /*!< Indicates to the card that the next command is an application specific command rather 
-                                                                       than a standard command.                                                                 */
-#define SD_CMD_GEN_CMD                             ((uint8_t)56U)  /*!< Used either to transfer a data block to the card or to get a data block from the card 
-                                                                       for general purpose/application specific commands.                                       */
-#define SD_CMD_NO_CMD                              ((uint8_t)64U) 
-
-/** 
-  * @brief Following commands are SD Card Specific commands.
-  *        SDIO_APP_CMD should be sent before sending these commands. 
-  */
-#define SD_CMD_APP_SD_SET_BUSWIDTH                 ((uint8_t)6U)   /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus 
-                                                                       widths are given in SCR register.                                                          */
-#define SD_CMD_SD_APP_STATUS                       ((uint8_t)13U)  /*!< (ACMD13) Sends the SD status.                                                              */
-#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS        ((uint8_t)22U)  /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 
-                                                                       32bit+CRC data block.                                                                      */
-#define SD_CMD_SD_APP_OP_COND                      ((uint8_t)41U)  /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to 
-                                                                       send its operating condition register (OCR) content in the response on the CMD line.       */
-#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT          ((uint8_t)42U)  /*!< (ACMD42) Connects/Disconnects the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card. */
-#define SD_CMD_SD_APP_SEND_SCR                     ((uint8_t)51U)  /*!< Reads the SD Configuration Register (SCR).                                                 */
-#define SD_CMD_SDIO_RW_DIRECT                      ((uint8_t)52U)  /*!< For SD I/O card only, reserved for security specification.                                 */
-#define SD_CMD_SDIO_RW_EXTENDED                    ((uint8_t)53U)  /*!< For SD I/O card only, reserved for security specification.                                 */
-
-/** 
-  * @brief Following commands are SD Card Specific security commands.
-  *        SD_CMD_APP_CMD should be sent before sending these commands. 
-  */
-#define SD_CMD_SD_APP_GET_MKB                      ((uint8_t)43U)  /*!< For SD card only */
-#define SD_CMD_SD_APP_GET_MID                      ((uint8_t)44U)  /*!< For SD card only */
-#define SD_CMD_SD_APP_SET_CER_RN1                  ((uint8_t)45U)  /*!< For SD card only */
-#define SD_CMD_SD_APP_GET_CER_RN2                  ((uint8_t)46U)  /*!< For SD card only */
-#define SD_CMD_SD_APP_SET_CER_RES2                 ((uint8_t)47U)  /*!< For SD card only */
-#define SD_CMD_SD_APP_GET_CER_RES1                 ((uint8_t)48U)  /*!< For SD card only */
-#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK   ((uint8_t)18U)  /*!< For SD card only */
-#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK  ((uint8_t)25U)  /*!< For SD card only */
-#define SD_CMD_SD_APP_SECURE_ERASE                 ((uint8_t)38U)  /*!< For SD card only */
-#define SD_CMD_SD_APP_CHANGE_SECURE_AREA           ((uint8_t)49U)  /*!< For SD card only */
-#define SD_CMD_SD_APP_SECURE_WRITE_MKB             ((uint8_t)48U)  /*!< For SD card only */
-
-/** 
-  * @brief Supported SD Memory Cards 
-  */
-#define STD_CAPACITY_SD_CARD_V1_1             ((uint32_t)0x00000000U)
-#define STD_CAPACITY_SD_CARD_V2_0             ((uint32_t)0x00000001U)
-#define HIGH_CAPACITY_SD_CARD                 ((uint32_t)0x00000002U)
-#define MULTIMEDIA_CARD                       ((uint32_t)0x00000003U)
-#define SECURE_DIGITAL_IO_CARD                ((uint32_t)0x00000004U)
-#define HIGH_SPEED_MULTIMEDIA_CARD            ((uint32_t)0x00000005U)
-#define SECURE_DIGITAL_IO_COMBO_CARD          ((uint32_t)0x00000006U)
-#define HIGH_CAPACITY_MMC_CARD                ((uint32_t)0x00000007U)
-/**
-  * @}
-  */
-  
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup SD_Exported_macros SD Exported Macros
-  * @brief macros to handle interrupts and specific clock configurations
-  * @{
-  */
- 
-/**
-  * @brief  Enable the SD device.
-  * @retval None
-  */ 
-#define __HAL_SD_SDIO_ENABLE() __SDIO_ENABLE()
-
-/**
-  * @brief  Disable the SD device.
-  * @retval None
-  */
-#define __HAL_SD_SDIO_DISABLE() __SDIO_DISABLE()
-
-/**
-  * @brief  Enable the SDIO DMA transfer.
-  * @retval None
-  */ 
-#define __HAL_SD_SDIO_DMA_ENABLE() __SDIO_DMA_ENABLE()
-
-/**
-  * @brief  Disable the SDIO DMA transfer.
-  * @retval None
-  */
-#define __HAL_SD_SDIO_DMA_DISABLE()  __SDIO_DMA_DISABLE()
- 
-/**
-  * @brief  Enable the SD device interrupt.
-  * @param  __HANDLE__: SD Handle  
-  * @param  __INTERRUPT__: specifies the SDIO interrupt sources to be enabled.
-  *         This parameter can be one or a combination of the following values:
-  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
-  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
-  *                                   bus mode interrupt
-  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
-  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
-  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
-  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
-  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
-  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
-  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
-  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
-  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
-  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
-  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
-  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt     
-  * @retval None
-  */
-#define __HAL_SD_SDIO_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
-  * @brief  Disable the SD device interrupt.
-  * @param  __HANDLE__: SD Handle   
-  * @param  __INTERRUPT__: specifies the SDIO interrupt sources to be disabled.
-  *          This parameter can be one or a combination of the following values:
-  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
-  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
-  *                                   bus mode interrupt
-  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
-  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
-  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
-  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
-  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
-  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
-  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
-  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
-  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
-  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
-  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
-  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt     
-  * @retval None
-  */
-#define __HAL_SD_SDIO_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
-  * @brief  Check whether the specified SD flag is set or not. 
-  * @param  __HANDLE__: SD Handle   
-  * @param  __FLAG__: specifies the flag to check. 
-  *          This parameter can be one of the following values:
-  *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
-  *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
-  *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout
-  *            @arg SDIO_FLAG_DTIMEOUT: Data timeout
-  *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
-  *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
-  *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
-  *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
-  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
-  *            @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
-  *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
-  *            @arg SDIO_FLAG_CMDACT:   Command transfer in progress
-  *            @arg SDIO_FLAG_TXACT:    Data transmit in progress
-  *            @arg SDIO_FLAG_RXACT:    Data receive in progress
-  *            @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
-  *            @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
-  *            @arg SDIO_FLAG_TXFIFOF:  Transmit FIFO full
-  *            @arg SDIO_FLAG_RXFIFOF:  Receive FIFO full
-  *            @arg SDIO_FLAG_TXFIFOE:  Transmit FIFO empty
-  *            @arg SDIO_FLAG_RXFIFOE:  Receive FIFO empty
-  *            @arg SDIO_FLAG_TXDAVL:   Data available in transmit FIFO
-  *            @arg SDIO_FLAG_RXDAVL:   Data available in receive FIFO
-  *            @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
-  *            @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
-  * @retval The new state of SD FLAG (SET or RESET).
-  */
-#define __HAL_SD_SDIO_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
-
-/**
-  * @brief  Clear the SD's pending flags.
-  * @param  __HANDLE__: SD Handle  
-  * @param  __FLAG__: specifies the flag to clear.  
-  *          This parameter can be one or a combination of the following values:
-  *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
-  *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
-  *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout
-  *            @arg SDIO_FLAG_DTIMEOUT: Data timeout
-  *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
-  *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
-  *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
-  *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
-  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
-  *            @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
-  *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
-  *            @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
-  *            @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
-  * @retval None
-  */
-#define __HAL_SD_SDIO_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
-
-/**
-  * @brief  Check whether the specified SD interrupt has occurred or not.
-  * @param  __HANDLE__: SD Handle   
-  * @param  __INTERRUPT__: specifies the SDIO interrupt source to check. 
-  *          This parameter can be one of the following values:
-  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
-  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
-  *                                   bus mode interrupt
-  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
-  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
-  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
-  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
-  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
-  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
-  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
-  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
-  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
-  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
-  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
-  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
-  * @retval The new state of SD IT (SET or RESET).
-  */
-#define __HAL_SD_SDIO_GET_IT  (__HANDLE__, __INTERRUPT__) __SDIO_GET_IT  ((__HANDLE__)->Instance, __INTERRUPT__)
-
-/**
-  * @brief  Clear the SD's interrupt pending bits.
-  * @param  __HANDLE__: SD Handle
-  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. 
-  *          This parameter can be one or a combination of the following values:
-  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIO_DCOUNT, is zero) interrupt
-  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
-  *                                   bus mode interrupt
-  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
-  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
-  * @retval None
-  */
-#define __HAL_SD_SDIO_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-/**
-  * @}
-  */
-  
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup SD_Exported_Functions SD Exported Functions
-  * @{
-  */
-
-/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo);
-HAL_StatusTypeDef   HAL_SD_DeInit (SD_HandleTypeDef *hsd);
-void HAL_SD_MspInit(SD_HandleTypeDef *hsd);
-void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
-/**
-  * @}
-  */
-
-/** @defgroup SD_Exported_Functions_Group2 I/O operation functions
-  * @{
-  */
-/* Blocking mode: Polling */
-// dpgeorge: read/write functions renamed to emphasise that address is given by block number
-HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_BlockNumber(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint32_t BlockNumber, uint32_t BlockSize, uint32_t NumberOfBlocks);
-HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_BlockNumber(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint32_t BlockNumber, uint32_t BlockSize, uint32_t NumberOfBlocks);
-HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr);
-
-/* Non-Blocking mode: Interrupt */
-void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
-
-/* Callback in non blocking modes (DMA) */
-void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma);
-void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma);
-void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma);
-void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma);
-void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd);
-void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd);
-
-/* Non-Blocking mode: DMA */
-// dpgeorge: read/write functions renamed to emphasise that address is given by block number
-HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_BlockNumber_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint32_t BlockNumber, uint32_t BlockSize, uint32_t NumberOfBlocks);
-HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_BlockNumber_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint32_t BlockNumber, uint32_t BlockSize, uint32_t NumberOfBlocks);
-HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);
-HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);
-/**
-  * @}
-  */
-
-/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions
-  * @{
-  */
-HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo);
-HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode);
-HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd);
-HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd);
-/**
-  * @}
-  */
-  
-/* Peripheral State functions  ************************************************/
-/** @defgroup SD_Exported_Functions_Group4 Peripheral State functions
-  * @{
-  */
-HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
-HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus);
-HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd);
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-    
-/* Private types -------------------------------------------------------------*/
-/** @defgroup SD_Private_Types SD Private Types
-  * @{
-  */
-
-/**
-  * @}
-  */ 
-
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup SD_Private_Defines SD Private Defines
-  * @{
-  */
-
-/**
-  * @}
-  */ 
-          
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup SD_Private_Variables SD Private Variables
-  * @{
-  */
-
-/**
-  * @}
-  */ 
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup SD_Private_Constants SD Private Constants
-  * @{
-  */
-
-/**
-  * @}
-  */ 
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SD_Private_Macros SD Private Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup SD_Private_Functions SD Private Functions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
-          STM32F412Rx || STM32F412Cx */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_SD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_spi.h b/stmhal/hal/f4/inc/stm32f4xx_hal_spi.h
deleted file mode 100644
index e2b243ea20..0000000000
--- a/stmhal/hal/f4/inc/stm32f4xx_hal_spi.h
+++ /dev/null
@@ -1,583 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_spi.h
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   Header file of SPI HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_SPI_H
-#define __STM32F4xx_HAL_SPI_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup SPI
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup SPI_Exported_Types SPI Exported Types
-  * @{
-  */
-
-/**
-  * @brief  SPI Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t Mode;               /*!< Specifies the SPI operating mode.
-                                     This parameter can be a value of @ref SPI_Mode */
-
-  uint32_t Direction;           /*!< Specifies the SPI bidirectional mode state.
-                                     This parameter can be a value of @ref SPI_Direction */
-
-  uint32_t DataSize;           /*!< Specifies the SPI data size.
-                                     This parameter can be a value of @ref SPI_Data_Size */
-
-  uint32_t CLKPolarity;        /*!< Specifies the serial clock steady state.
-                                    This parameter can be a value of @ref SPI_Clock_Polarity */
-
-  uint32_t CLKPhase;           /*!< Specifies the clock active edge for the bit capture.
-                                    This parameter can be a value of @ref SPI_Clock_Phase */
-
-  uint32_t NSS;                /*!< Specifies whether the NSS signal is managed by
-                                    hardware (NSS pin) or by software using the SSI bit.
-                                    This parameter can be a value of @ref SPI_Slave_Select_management */
-
-  uint32_t BaudRatePrescaler;  /*!< Specifies the Baud Rate prescaler value which will be
-                                    used to configure the transmit and receive SCK clock.
-                                    This parameter can be a value of @ref SPI_BaudRate_Prescaler
-                                    @note The communication clock is derived from the master
-                                     clock. The slave clock does not need to be set. */
-
-  uint32_t FirstBit;           /*!< Specifies whether data transfers start from MSB or LSB bit.
-                                    This parameter can be a value of @ref SPI_MSB_LSB_transmission */
-
-  uint32_t TIMode;             /*!< Specifies if the TI mode is enabled or not.
-                                    This parameter can be a value of @ref SPI_TI_mode */
-
-  uint32_t CRCCalculation;     /*!< Specifies if the CRC calculation is enabled or not.
-                                    This parameter can be a value of @ref SPI_CRC_Calculation */
-
-  uint32_t CRCPolynomial;      /*!< Specifies the polynomial used for the CRC calculation.
-                                    This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
-}SPI_InitTypeDef;
-
-/**
-  * @brief  HAL SPI State structure definition
-  */
-typedef enum
-{
-  HAL_SPI_STATE_RESET      = 0x00U,    /*!< Peripheral not Initialized                         */
-  HAL_SPI_STATE_READY      = 0x01U,    /*!< Peripheral Initialized and ready for use           */
-  HAL_SPI_STATE_BUSY       = 0x02U,    /*!< an internal process is ongoing                     */
-  HAL_SPI_STATE_BUSY_TX    = 0x03U,    /*!< Data Transmission process is ongoing               */
-  HAL_SPI_STATE_BUSY_RX    = 0x04U,    /*!< Data Reception process is ongoing                  */
-  HAL_SPI_STATE_BUSY_TX_RX = 0x05U,    /*!< Data Transmission and Reception process is ongoing */
-  HAL_SPI_STATE_ERROR      = 0x06U     /*!< SPI error state                                    */
-}HAL_SPI_StateTypeDef;
-
-/**
-  * @brief  SPI handle Structure definition
-  */
-typedef struct __SPI_HandleTypeDef
-{
-  SPI_TypeDef                *Instance;    /* SPI registers base address */
-
-  SPI_InitTypeDef            Init;         /* SPI communication parameters */
-
-  uint8_t                    *pTxBuffPtr;  /* Pointer to SPI Tx transfer Buffer */
-
-  uint16_t                   TxXferSize;   /* SPI Tx Transfer size */
-
-  __IO uint16_t              TxXferCount;  /* SPI Tx Transfer Counter */
-
-  uint8_t                    *pRxBuffPtr;  /* Pointer to SPI Rx transfer Buffer */
-
-  uint16_t                   RxXferSize;   /* SPI Rx Transfer size */
-
-  __IO uint16_t              RxXferCount;  /* SPI Rx Transfer Counter */
-
-  void                       (*RxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Rx ISR */
-
-  void                       (*TxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Tx ISR */
-
-  DMA_HandleTypeDef          *hdmatx;      /* SPI Tx DMA Handle parameters   */
-
-  DMA_HandleTypeDef          *hdmarx;      /* SPI Rx DMA Handle parameters   */
-
-  HAL_LockTypeDef            Lock;         /* Locking object                 */
-
-  __IO HAL_SPI_StateTypeDef  State;        /* SPI communication state */
-
-  __IO uint32_t              ErrorCode;    /* SPI Error code */
-
-}SPI_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SPI_Exported_Constants SPI Exported Constants
-  * @{
-  */
-
-/** @defgroup SPI_Error_Code SPI Error Code
-  * @{
-  */
-#define HAL_SPI_ERROR_NONE              ((uint32_t)0x00000000U)   /*!< No error             */
-#define HAL_SPI_ERROR_MODF              ((uint32_t)0x00000001U)   /*!< MODF error           */
-#define HAL_SPI_ERROR_CRC               ((uint32_t)0x00000002U)   /*!< CRC error            */
-#define HAL_SPI_ERROR_OVR               ((uint32_t)0x00000004U)   /*!< OVR error            */
-#define HAL_SPI_ERROR_FRE               ((uint32_t)0x00000008U)   /*!< FRE error            */
-#define HAL_SPI_ERROR_DMA               ((uint32_t)0x00000010U)   /*!< DMA transfer error   */
-#define HAL_SPI_ERROR_FLAG              ((uint32_t)0x00000020U)   /*!< Flag: RXNE,TXE, BSY  */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Mode SPI Mode
-  * @{
-  */
-#define SPI_MODE_SLAVE                  ((uint32_t)0x00000000U)
-#define SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Direction SPI Direction Mode
-  * @{
-  */
-#define SPI_DIRECTION_2LINES            ((uint32_t)0x00000000U)
-#define SPI_DIRECTION_2LINES_RXONLY     SPI_CR1_RXONLY
-#define SPI_DIRECTION_1LINE             SPI_CR1_BIDIMODE
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Data_Size SPI Data Size
-  * @{
-  */
-#define SPI_DATASIZE_8BIT               ((uint32_t)0x00000000U)
-#define SPI_DATASIZE_16BIT              SPI_CR1_DFF
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
-  * @{
-  */
-#define SPI_POLARITY_LOW                ((uint32_t)0x00000000U)
-#define SPI_POLARITY_HIGH               SPI_CR1_CPOL
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Clock_Phase SPI Clock Phase
-  * @{
-  */
-#define SPI_PHASE_1EDGE                 ((uint32_t)0x00000000U)
-#define SPI_PHASE_2EDGE                 SPI_CR1_CPHA
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Slave_Select_management SPI Slave Select Management
-  * @{
-  */
-#define SPI_NSS_SOFT                    SPI_CR1_SSM
-#define SPI_NSS_HARD_INPUT              ((uint32_t)0x00000000U)
-#define SPI_NSS_HARD_OUTPUT             ((uint32_t)0x00040000U)
-/**
-  * @}
-  */
-
-/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
-  * @{
-  */
-#define SPI_BAUDRATEPRESCALER_2         ((uint32_t)0x00000000U)
-#define SPI_BAUDRATEPRESCALER_4         ((uint32_t)0x00000008U)
-#define SPI_BAUDRATEPRESCALER_8         ((uint32_t)0x00000010U)
-#define SPI_BAUDRATEPRESCALER_16        ((uint32_t)0x00000018U)
-#define SPI_BAUDRATEPRESCALER_32        ((uint32_t)0x00000020U)
-#define SPI_BAUDRATEPRESCALER_64        ((uint32_t)0x00000028U)
-#define SPI_BAUDRATEPRESCALER_128       ((uint32_t)0x00000030U)
-#define SPI_BAUDRATEPRESCALER_256       ((uint32_t)0x00000038U)
-/**
-  * @}
-  */
-
-/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
-  * @{
-  */
-#define SPI_FIRSTBIT_MSB                ((uint32_t)0x00000000U)
-#define SPI_FIRSTBIT_LSB                SPI_CR1_LSBFIRST
-/**
-  * @}
-  */
-
-/** @defgroup SPI_TI_mode SPI TI Mode
-  * @{
-  */
-#define SPI_TIMODE_DISABLE             ((uint32_t)0x00000000U)
-#define SPI_TIMODE_ENABLE              SPI_CR2_FRF
-/**
-  * @}
-  */
-
-/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
-  * @{
-  */
-#define SPI_CRCCALCULATION_DISABLE     ((uint32_t)0x00000000U)
-#define SPI_CRCCALCULATION_ENABLE      SPI_CR1_CRCEN
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
-  * @{
-  */
-#define SPI_IT_TXE                      SPI_CR2_TXEIE
-#define SPI_IT_RXNE                     SPI_CR2_RXNEIE
-#define SPI_IT_ERR                      SPI_CR2_ERRIE
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Flags_definition SPI Flags Definition
-  * @{
-  */
-#define SPI_FLAG_RXNE                   SPI_SR_RXNE   /* SPI status flag: Rx buffer not empty flag */
-#define SPI_FLAG_TXE                    SPI_SR_TXE    /* SPI status flag: Tx buffer empty flag */
-#define SPI_FLAG_BSY                    SPI_SR_BSY    /* SPI status flag: Busy flag */
-#define SPI_FLAG_CRCERR                 SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
-#define SPI_FLAG_MODF                   SPI_SR_MODF   /* SPI Error flag: Mode fault flag */
-#define SPI_FLAG_OVR                    SPI_SR_OVR    /* SPI Error flag: Overrun flag */
-#define SPI_FLAG_FRE                    SPI_SR_FRE    /* SPI Error flag: TI mode frame format error flag */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup SPI_Exported_Macros SPI Exported Macros
-  * @{
-  */
-
-/** @brief  Reset SPI handle state.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
-
-/** @brief  Enable or disable the specified SPI interrupts.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
-  *         This parameter can be one of the following values:
-  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg SPI_IT_ERR: Error interrupt enable
-  * @retval None
-  */
-#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
-#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
-
-/** @brief  Check whether the specified SPI interrupt source is enabled or not.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @param  __INTERRUPT__: specifies the SPI interrupt source to check.
-  *          This parameter can be one of the following values:
-  *             @arg SPI_IT_TXE: Tx buffer empty interrupt enable
-  *             @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
-  *             @arg SPI_IT_ERR: Error interrupt enable
-  * @retval The new state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief  Check whether the specified SPI flag is set or not.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @param  __FLAG__: specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag
-  *            @arg SPI_FLAG_TXE: Transmit buffer empty flag
-  *            @arg SPI_FLAG_CRCERR: CRC error flag
-  *            @arg SPI_FLAG_MODF: Mode fault flag
-  *            @arg SPI_FLAG_OVR: Overrun flag
-  *            @arg SPI_FLAG_BSY: Busy flag
-  *            @arg SPI_FLAG_FRE: Frame format error flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Clear the SPI CRCERR pending flag.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
-
-/** @brief  Clear the SPI MODF pending flag.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)       \
-  do{                                              \
-    __IO uint32_t tmpreg_modf = 0x00U;             \
-    tmpreg_modf = (__HANDLE__)->Instance->SR;      \
-    (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
-    UNUSED(tmpreg_modf);                           \
-  } while(0)
-
-/** @brief  Clear the SPI OVR pending flag.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)        \
-  do{                                              \
-    __IO uint32_t tmpreg_ovr = 0x00U;              \
-    tmpreg_ovr = (__HANDLE__)->Instance->DR;       \
-    tmpreg_ovr = (__HANDLE__)->Instance->SR;       \
-    UNUSED(tmpreg_ovr);                            \
-  } while(0)
-
-/** @brief  Clear the SPI FRE pending flag.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)        \
-  do{                                              \
-  __IO uint32_t tmpreg_fre = 0x00U;                \
-  tmpreg_fre = (__HANDLE__)->Instance->SR;         \
-  UNUSED(tmpreg_fre);                              \
-  }while(0)
-
-/** @brief  Enable the SPI peripheral.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |=  SPI_CR1_SPE)
-
-/** @brief  Disable the SPI peripheral.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SPI_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup SPI_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization/de-initialization functions  **********************************/
-HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
-void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
-void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
-/**
-  * @}
-  */
-
-/** @addtogroup SPI_Exported_Functions_Group2
-  * @{
-  */
-/* I/O operation functions  *****************************************************/
-HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
-
-void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
-/**
-  * @}
-  */
-
-/** @addtogroup SPI_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral State and Error functions ***************************************/
-HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
-uint32_t             HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SPI_Private_Macros SPI Private Macros
-  * @{
-  */
-
-/** @brief  Set the SPI transmit-only mode.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
-
-/** @brief  Set the SPI receive-only mode.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
-
-/** @brief  Reset the CRC calculation of the SPI.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
-                                     (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
-
-#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
-                           ((MODE) == SPI_MODE_MASTER))
-
-#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES)        || \
-                                ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
-                                ((MODE) == SPI_DIRECTION_1LINE))
-
-#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
-
-#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES)  || \
-                                                ((MODE) == SPI_DIRECTION_1LINE))
-
-#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
-                                   ((DATASIZE) == SPI_DATASIZE_8BIT))
-
-#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
-                           ((CPOL) == SPI_POLARITY_HIGH))
-
-#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
-                           ((CPHA) == SPI_PHASE_2EDGE))
-
-#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT)       || \
-                         ((NSS) == SPI_NSS_HARD_INPUT) || \
-                         ((NSS) == SPI_NSS_HARD_OUTPUT))
-
-#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2)   || \
-                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_4)   || \
-                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_8)   || \
-                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_16)  || \
-                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_32)  || \
-                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_64)  || \
-                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
-                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
-
-#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
-                               ((BIT) == SPI_FIRSTBIT_LSB))
-
-#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
-                             ((MODE) == SPI_TIMODE_ENABLE))
-
-#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
-                                             ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
-
-#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x01U) && ((POLYNOMIAL) <= 0xFFFFU))
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup SPI_Private_Functions SPI Private Functions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_SPI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_tim.h b/stmhal/hal/f4/inc/stm32f4xx_hal_tim.h
deleted file mode 100644
index f485a7b2b3..0000000000
--- a/stmhal/hal/f4/inc/stm32f4xx_hal_tim.h
+++ /dev/null
@@ -1,1609 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_tim.h
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   Header file of TIM HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_TIM_H
-#define __STM32F4xx_HAL_TIM_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup TIM
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup TIM_Exported_Types TIM Exported Types
-  * @{
-  */
-  
-/** 
-  * @brief  TIM Time base Configuration Structure definition  
-  */
-typedef struct
-{
-  uint32_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
-                                   This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
-
-  uint32_t CounterMode;       /*!< Specifies the counter mode.
-                                   This parameter can be a value of @ref TIM_Counter_Mode */
-
-  uint32_t Period;            /*!< Specifies the period value to be loaded into the active
-                                   Auto-Reload Register at the next update event.
-                                   This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFF.  */
-
-  uint32_t ClockDivision;     /*!< Specifies the clock division.
-                                   This parameter can be a value of @ref TIM_ClockDivision */
-
-  uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
-                                    reaches zero, an update event is generated and counting restarts
-                                    from the RCR value (N).
-                                    This means in PWM mode that (N+1) corresponds to:
-                                        - the number of PWM periods in edge-aligned mode
-                                        - the number of half PWM period in center-aligned mode
-                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. 
-                                     @note This parameter is valid only for TIM1 and TIM8. */
-} TIM_Base_InitTypeDef;
-
-/** 
-  * @brief  TIM Output Compare Configuration Structure definition  
-  */
-
-typedef struct
-{
-  uint32_t OCMode;        /*!< Specifies the TIM mode.
-                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
-
-  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 
-                               This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
-
-  uint32_t OCPolarity;    /*!< Specifies the output polarity.
-                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */
-
-  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
-                               This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
-                               @note This parameter is valid only for TIM1 and TIM8. */
-  
-  uint32_t OCFastMode;   /*!< Specifies the Fast mode state.
-                               This parameter can be a value of @ref TIM_Output_Fast_State
-                               @note This parameter is valid only in PWM1 and PWM2 mode. */
-
-
-  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
-                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State
-                               @note This parameter is valid only for TIM1 and TIM8. */
-
-  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
-                               This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
-                               @note This parameter is valid only for TIM1 and TIM8. */
-} TIM_OC_InitTypeDef;  
-
-/** 
-  * @brief  TIM One Pulse Mode Configuration Structure definition  
-  */
-typedef struct
-{
-  uint32_t OCMode;        /*!< Specifies the TIM mode.
-                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
-
-  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 
-                               This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
-
-  uint32_t OCPolarity;    /*!< Specifies the output polarity.
-                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */
-
-  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
-                               This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
-                               @note This parameter is valid only for TIM1 and TIM8. */
-
-  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
-                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State
-                               @note This parameter is valid only for TIM1 and TIM8. */
-
-  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
-                               This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
-                               @note This parameter is valid only for TIM1 and TIM8. */
-
-  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
-                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
-  uint32_t ICSelection;   /*!< Specifies the input.
-                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
-  uint32_t ICFilter;      /*!< Specifies the input capture filter.
-                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */  
-} TIM_OnePulse_InitTypeDef;  
-
-
-/** 
-  * @brief  TIM Input Capture Configuration Structure definition  
-  */
-
-typedef struct
-{
-  uint32_t  ICPolarity;   /*!< Specifies the active edge of the input signal.
-                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
-  uint32_t ICSelection;  /*!< Specifies the input.
-                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
-  uint32_t ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
-                              This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
-  uint32_t ICFilter;     /*!< Specifies the input capture filter.
-                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_IC_InitTypeDef;
-
-/** 
-  * @brief  TIM Encoder Configuration Structure definition  
-  */
-
-typedef struct
-{
-  uint32_t EncoderMode;   /*!< Specifies the active edge of the input signal.
-                               This parameter can be a value of @ref TIM_Encoder_Mode */
-                                  
-  uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.
-                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
-  uint32_t IC1Selection;  /*!< Specifies the input.
-                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
-  uint32_t IC1Prescaler;  /*!< Specifies the Input Capture Prescaler.
-                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
-  uint32_t IC1Filter;     /*!< Specifies the input capture filter.
-                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-                                  
-  uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.
-                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
-  uint32_t IC2Selection;  /*!< Specifies the input.
-                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
-  uint32_t IC2Prescaler;  /*!< Specifies the Input Capture Prescaler.
-                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
-  uint32_t IC2Filter;     /*!< Specifies the input capture filter.
-                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_Encoder_InitTypeDef;
-
-/** 
-  * @brief  Clock Configuration Handle Structure definition  
-  */ 
-typedef struct
-{
-  uint32_t ClockSource;     /*!< TIM clock sources. 
-                                 This parameter can be a value of @ref TIM_Clock_Source */ 
-  uint32_t ClockPolarity;   /*!< TIM clock polarity. 
-                                 This parameter can be a value of @ref TIM_Clock_Polarity */
-  uint32_t ClockPrescaler;  /*!< TIM clock prescaler. 
-                                 This parameter can be a value of @ref TIM_Clock_Prescaler */
-  uint32_t ClockFilter;    /*!< TIM clock filter. 
-                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-}TIM_ClockConfigTypeDef;
-
-/** 
-  * @brief  Clear Input Configuration Handle Structure definition  
-  */ 
-typedef struct
-{ 
-  uint32_t ClearInputState;      /*!< TIM clear Input state. 
-                                      This parameter can be ENABLE or DISABLE */  
-  uint32_t ClearInputSource;     /*!< TIM clear Input sources. 
-                                      This parameter can be a value of @ref TIM_ClearInput_Source */ 
-  uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity. 
-                                      This parameter can be a value of @ref TIM_ClearInput_Polarity */
-  uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler. 
-                                      This parameter can be a value of @ref TIM_ClearInput_Prescaler */
-  uint32_t ClearInputFilter;    /*!< TIM Clear Input filter. 
-                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-}TIM_ClearInputConfigTypeDef;
-
-/** 
-  * @brief  TIM Slave configuration Structure definition  
-  */ 
-typedef struct {
-  uint32_t  SlaveMode;         /*!< Slave mode selection 
-                                  This parameter can be a value of @ref TIM_Slave_Mode */ 
-  uint32_t  InputTrigger;      /*!< Input Trigger source 
-                                  This parameter can be a value of @ref TIM_Trigger_Selection */
-  uint32_t  TriggerPolarity;   /*!< Input Trigger polarity 
-                                  This parameter can be a value of @ref TIM_Trigger_Polarity */
-  uint32_t  TriggerPrescaler;  /*!< Input trigger prescaler 
-                                  This parameter can be a value of @ref TIM_Trigger_Prescaler */
-  uint32_t  TriggerFilter;     /*!< Input trigger filter 
-                                  This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */  
-
-}TIM_SlaveConfigTypeDef;
-
-/** 
-  * @brief  HAL State structures definition  
-  */ 
-typedef enum
-{
-  HAL_TIM_STATE_RESET             = 0x00U,    /*!< Peripheral not yet initialized or disabled  */
-  HAL_TIM_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */
-  HAL_TIM_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */
-  HAL_TIM_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */
-  HAL_TIM_STATE_ERROR             = 0x04U     /*!< Reception process is ongoing                */
-}HAL_TIM_StateTypeDef;
-
-/** 
-  * @brief  HAL Active channel structures definition  
-  */ 
-typedef enum
-{
-  HAL_TIM_ACTIVE_CHANNEL_1        = 0x01U,    /*!< The active channel is 1     */
-  HAL_TIM_ACTIVE_CHANNEL_2        = 0x02U,    /*!< The active channel is 2     */
-  HAL_TIM_ACTIVE_CHANNEL_3        = 0x04U,    /*!< The active channel is 3     */
-  HAL_TIM_ACTIVE_CHANNEL_4        = 0x08U,    /*!< The active channel is 4     */
-  HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00U     /*!< All active channels cleared */
-}HAL_TIM_ActiveChannel;
-
-/** 
-  * @brief  TIM Time Base Handle Structure definition  
-  */ 
-typedef struct
-{
-  TIM_TypeDef                 *Instance;     /*!< Register base address             */
-  TIM_Base_InitTypeDef        Init;          /*!< TIM Time Base required parameters */
-  HAL_TIM_ActiveChannel       Channel;       /*!< Active channel                    */
-  DMA_HandleTypeDef           *hdma[7];      /*!< DMA Handlers array
-                                             This array is accessed by a @ref DMA_Handle_index */
-  HAL_LockTypeDef             Lock;          /*!< Locking object                    */
-  __IO HAL_TIM_StateTypeDef   State;         /*!< TIM operation state               */
-}TIM_HandleTypeDef;
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIM_Exported_Constants  TIM Exported Constants
-  * @{
-  */
-
-/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
-  * @{
-  */
-#define  TIM_INPUTCHANNELPOLARITY_RISING      ((uint32_t)0x00000000U)            /*!< Polarity for TIx source */
-#define  TIM_INPUTCHANNELPOLARITY_FALLING     (TIM_CCER_CC1P)                   /*!< Polarity for TIx source */
-#define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_ETR_Polarity  TIM ETR Polarity
-  * @{
-  */
-#define TIM_ETRPOLARITY_INVERTED              (TIM_SMCR_ETP)                    /*!< Polarity for ETR source */
-#define TIM_ETRPOLARITY_NONINVERTED           ((uint32_t)0x00000000U)                /*!< Polarity for ETR source */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_ETR_Prescaler  TIM ETR Prescaler
-  * @{
-  */
-#define TIM_ETRPRESCALER_DIV1                 ((uint32_t)0x00000000U)                /*!< No prescaler is used */
-#define TIM_ETRPRESCALER_DIV2                 (TIM_SMCR_ETPS_0)                 /*!< ETR input source is divided by 2 */
-#define TIM_ETRPRESCALER_DIV4                 (TIM_SMCR_ETPS_1)                 /*!< ETR input source is divided by 4 */
-#define TIM_ETRPRESCALER_DIV8                 (TIM_SMCR_ETPS)                   /*!< ETR input source is divided by 8 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Counter_Mode  TIM Counter Mode
-  * @{
-  */
-#define TIM_COUNTERMODE_UP                 ((uint32_t)0x00000000U)
-#define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR
-#define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0
-#define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1
-#define TIM_COUNTERMODE_CENTERALIGNED3     TIM_CR1_CMS
-/**
-  * @}
-  */
-
-/** @defgroup TIM_ClockDivision TIM Clock Division
-  * @{
-  */
-#define TIM_CLOCKDIVISION_DIV1                       ((uint32_t)0x00000000U)
-#define TIM_CLOCKDIVISION_DIV2                       (TIM_CR1_CKD_0)
-#define TIM_CLOCKDIVISION_DIV4                       (TIM_CR1_CKD_1)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Compare_and_PWM_modes  TIM Output Compare and PWM modes
-  * @{
-  */
-#define TIM_OCMODE_TIMING                   ((uint32_t)0x00000000U)
-#define TIM_OCMODE_ACTIVE                   (TIM_CCMR1_OC1M_0)
-#define TIM_OCMODE_INACTIVE                 (TIM_CCMR1_OC1M_1)
-#define TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
-#define TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
-#define TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M)
-#define TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
-#define TIM_OCMODE_FORCED_INACTIVE          (TIM_CCMR1_OC1M_2)
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Fast_State  TIM Output Fast State 
-  * @{
-  */
-#define TIM_OCFAST_DISABLE                ((uint32_t)0x00000000U)
-#define TIM_OCFAST_ENABLE                 (TIM_CCMR1_OC1FE)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Compare_Polarity  TIM Output Compare Polarity
-  * @{
-  */
-#define TIM_OCPOLARITY_HIGH                ((uint32_t)0x00000000U)
-#define TIM_OCPOLARITY_LOW                 (TIM_CCER_CC1P)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Compare_N_Polarity  TIM Output CompareN Polarity 
-  * @{
-  */
-#define TIM_OCNPOLARITY_HIGH               ((uint32_t)0x00000000U)
-#define TIM_OCNPOLARITY_LOW                (TIM_CCER_CC1NP)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Compare_Idle_State  TIM Output Compare Idle State
-  * @{
-  */
-#define TIM_OCIDLESTATE_SET                (TIM_CR2_OIS1)
-#define TIM_OCIDLESTATE_RESET              ((uint32_t)0x00000000U)
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Output_Compare_N_Idle_State  TIM Output Compare N Idle State
-  * @{
-  */
-#define TIM_OCNIDLESTATE_SET               (TIM_CR2_OIS1N)
-#define TIM_OCNIDLESTATE_RESET             ((uint32_t)0x00000000U)
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Channel  TIM Channel
-  * @{
-  */
-#define TIM_CHANNEL_1                      ((uint32_t)0x00000000U)
-#define TIM_CHANNEL_2                      ((uint32_t)0x00000004U)
-#define TIM_CHANNEL_3                      ((uint32_t)0x00000008U)
-#define TIM_CHANNEL_4                      ((uint32_t)0x0000000CU)
-#define TIM_CHANNEL_ALL                    ((uint32_t)0x00000018U)
-                                 
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Input_Capture_Polarity  TIM Input Capture Polarity 
-  * @{
-  */
-#define  TIM_ICPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING
-#define  TIM_ICPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING
-#define  TIM_ICPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Input_Capture_Selection  TIM Input Capture Selection
-  * @{
-  */
-#define TIM_ICSELECTION_DIRECTTI           (TIM_CCMR1_CC1S_0)   /*!< TIM Input 1, 2, 3 or 4 is selected to be 
-                                                                     connected to IC1, IC2, IC3 or IC4, respectively */
-#define TIM_ICSELECTION_INDIRECTTI         (TIM_CCMR1_CC1S_1)   /*!< TIM Input 1, 2, 3 or 4 is selected to be
-                                                                     connected to IC2, IC1, IC4 or IC3, respectively */
-#define TIM_ICSELECTION_TRC                (TIM_CCMR1_CC1S)     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Input_Capture_Prescaler  TIM Input Capture Prescaler
-  * @{
-  */
-#define TIM_ICPSC_DIV1                     ((uint32_t)0x00000000U)       /*!< Capture performed each time an edge is detected on the capture input */
-#define TIM_ICPSC_DIV2                     (TIM_CCMR1_IC1PSC_0)     /*!< Capture performed once every 2 events */
-#define TIM_ICPSC_DIV4                     (TIM_CCMR1_IC1PSC_1)     /*!< Capture performed once every 4 events */
-#define TIM_ICPSC_DIV8                     (TIM_CCMR1_IC1PSC)       /*!< Capture performed once every 8 events */
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
-  * @{
-  */
-#define TIM_OPMODE_SINGLE                  (TIM_CR1_OPM)
-#define TIM_OPMODE_REPETITIVE              ((uint32_t)0x00000000U)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
-  * @{
-  */
-#define TIM_ENCODERMODE_TI1                (TIM_SMCR_SMS_0)
-#define TIM_ENCODERMODE_TI2                (TIM_SMCR_SMS_1)
-#define TIM_ENCODERMODE_TI12               (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
-   
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Interrupt_definition  TIM Interrupt definition
-  * @{
-  */ 
-#define TIM_IT_UPDATE           (TIM_DIER_UIE)
-#define TIM_IT_CC1              (TIM_DIER_CC1IE)
-#define TIM_IT_CC2              (TIM_DIER_CC2IE)
-#define TIM_IT_CC3              (TIM_DIER_CC3IE)
-#define TIM_IT_CC4              (TIM_DIER_CC4IE)
-#define TIM_IT_COM              (TIM_DIER_COMIE)
-#define TIM_IT_TRIGGER          (TIM_DIER_TIE)
-#define TIM_IT_BREAK            (TIM_DIER_BIE)
-/**
-  * @}
-  */
-  
-/** @defgroup TIM_Commutation_Source  TIM Commutation Source 
-  * @{
-  */  
-#define TIM_COMMUTATION_TRGI              (TIM_CR2_CCUS)
-#define TIM_COMMUTATION_SOFTWARE          ((uint32_t)0x00000000U)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_DMA_sources  TIM DMA sources
-  * @{
-  */
-#define TIM_DMA_UPDATE                     (TIM_DIER_UDE)
-#define TIM_DMA_CC1                        (TIM_DIER_CC1DE)
-#define TIM_DMA_CC2                        (TIM_DIER_CC2DE)
-#define TIM_DMA_CC3                        (TIM_DIER_CC3DE)
-#define TIM_DMA_CC4                        (TIM_DIER_CC4DE)
-#define TIM_DMA_COM                        (TIM_DIER_COMDE)
-#define TIM_DMA_TRIGGER                    (TIM_DIER_TDE)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Event_Source  TIM Event Source 
-  * @{
-  */
-#define TIM_EVENTSOURCE_UPDATE              TIM_EGR_UG  
-#define TIM_EVENTSOURCE_CC1                 TIM_EGR_CC1G
-#define TIM_EVENTSOURCE_CC2                 TIM_EGR_CC2G
-#define TIM_EVENTSOURCE_CC3                 TIM_EGR_CC3G
-#define TIM_EVENTSOURCE_CC4                 TIM_EGR_CC4G
-#define TIM_EVENTSOURCE_COM                 TIM_EGR_COMG
-#define TIM_EVENTSOURCE_TRIGGER             TIM_EGR_TG
-#define TIM_EVENTSOURCE_BREAK               TIM_EGR_BG
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Flag_definition  TIM Flag definition
-  * @{
-  */
-#define TIM_FLAG_UPDATE                    (TIM_SR_UIF)
-#define TIM_FLAG_CC1                       (TIM_SR_CC1IF)
-#define TIM_FLAG_CC2                       (TIM_SR_CC2IF)
-#define TIM_FLAG_CC3                       (TIM_SR_CC3IF)
-#define TIM_FLAG_CC4                       (TIM_SR_CC4IF)
-#define TIM_FLAG_COM                       (TIM_SR_COMIF)
-#define TIM_FLAG_TRIGGER                   (TIM_SR_TIF)
-#define TIM_FLAG_BREAK                     (TIM_SR_BIF)
-#define TIM_FLAG_CC1OF                     (TIM_SR_CC1OF)
-#define TIM_FLAG_CC2OF                     (TIM_SR_CC2OF)
-#define TIM_FLAG_CC3OF                     (TIM_SR_CC3OF)
-#define TIM_FLAG_CC4OF                     (TIM_SR_CC4OF)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Clock_Source  TIM Clock Source
-  * @{
-  */
-#define	TIM_CLOCKSOURCE_ETRMODE2    (TIM_SMCR_ETPS_1) 
-#define	TIM_CLOCKSOURCE_INTERNAL    (TIM_SMCR_ETPS_0) 
-#define	TIM_CLOCKSOURCE_ITR0        ((uint32_t)0x00000000U)
-#define	TIM_CLOCKSOURCE_ITR1        (TIM_SMCR_TS_0)
-#define	TIM_CLOCKSOURCE_ITR2        (TIM_SMCR_TS_1)
-#define	TIM_CLOCKSOURCE_ITR3        (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
-#define	TIM_CLOCKSOURCE_TI1ED       (TIM_SMCR_TS_2)
-#define	TIM_CLOCKSOURCE_TI1         (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
-#define	TIM_CLOCKSOURCE_TI2         (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
-#define	TIM_CLOCKSOURCE_ETRMODE1    (TIM_SMCR_TS)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Clock_Polarity  TIM Clock Polarity
-  * @{
-  */
-#define TIM_CLOCKPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED          /*!< Polarity for ETRx clock sources */ 
-#define TIM_CLOCKPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED       /*!< Polarity for ETRx clock sources */ 
-#define TIM_CLOCKPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING   /*!< Polarity for TIx clock sources */ 
-#define TIM_CLOCKPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING   /*!< Polarity for TIx clock sources */ 
-#define TIM_CLOCKPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE  /*!< Polarity for TIx clock sources */ 
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Clock_Prescaler  TIM Clock Prescaler
-  * @{
-  */
-#define TIM_CLOCKPRESCALER_DIV1              TIM_ETRPRESCALER_DIV1     /*!< No prescaler is used */
-#define TIM_CLOCKPRESCALER_DIV2              TIM_ETRPRESCALER_DIV2     /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
-#define TIM_CLOCKPRESCALER_DIV4              TIM_ETRPRESCALER_DIV4     /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
-#define TIM_CLOCKPRESCALER_DIV8              TIM_ETRPRESCALER_DIV8     /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
-  * @{
-  */
-#define TIM_CLEARINPUTSOURCE_ETR           ((uint32_t)0x00000001U) 
-#define TIM_CLEARINPUTSOURCE_NONE          ((uint32_t)0x00000000U)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_ClearInput_Polarity  TIM Clear Input Polarity
-  * @{
-  */
-#define TIM_CLEARINPUTPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED                    /*!< Polarity for ETRx pin */ 
-#define TIM_CLEARINPUTPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED                 /*!< Polarity for ETRx pin */ 
-/**
-  * @}
-  */
-
-/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
-  * @{
-  */
-#define TIM_CLEARINPUTPRESCALER_DIV1                    TIM_ETRPRESCALER_DIV1      /*!< No prescaler is used */
-#define TIM_CLEARINPUTPRESCALER_DIV2                    TIM_ETRPRESCALER_DIV2      /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
-#define TIM_CLEARINPUTPRESCALER_DIV4                    TIM_ETRPRESCALER_DIV4      /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
-#define TIM_CLEARINPUTPRESCALER_DIV8                    TIM_ETRPRESCALER_DIV8        /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
-  * @{
-  */  
-#define TIM_OSSR_ENABLE         (TIM_BDTR_OSSR)
-#define TIM_OSSR_DISABLE        ((uint32_t)0x00000000U)
-/**
-  * @}
-  */
-  
-/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
-  * @{
-  */
-#define TIM_OSSI_ENABLE             (TIM_BDTR_OSSI)
-#define TIM_OSSI_DISABLE            ((uint32_t)0x00000000U)
-/**
-  * @}
-  */
-  
-/** @defgroup TIM_Lock_level  TIM Lock level
-  * @{
-  */
-#define TIM_LOCKLEVEL_OFF          ((uint32_t)0x00000000U)
-#define TIM_LOCKLEVEL_1            (TIM_BDTR_LOCK_0)
-#define TIM_LOCKLEVEL_2            (TIM_BDTR_LOCK_1)
-#define TIM_LOCKLEVEL_3            (TIM_BDTR_LOCK)
-/**
-  * @}
-  */  
-/** @defgroup TIM_Break_Input_enable_disable  TIM Break Input State
-  * @{
-  */
-#define TIM_BREAK_ENABLE          (TIM_BDTR_BKE)
-#define TIM_BREAK_DISABLE         ((uint32_t)0x00000000U)
-/**
-  * @}
-  */
-  
-/** @defgroup TIM_Break_Polarity  TIM Break Polarity 
-  * @{
-  */
-#define TIM_BREAKPOLARITY_LOW        ((uint32_t)0x00000000U)
-#define TIM_BREAKPOLARITY_HIGH       (TIM_BDTR_BKP)
-/**
-  * @}
-  */
-  
-/** @defgroup TIM_AOE_Bit_Set_Reset  TIM AOE Bit State
-  * @{
-  */
-#define TIM_AUTOMATICOUTPUT_ENABLE           (TIM_BDTR_AOE)
-#define	TIM_AUTOMATICOUTPUT_DISABLE          ((uint32_t)0x00000000U)
-/**
-  * @}
-  */  
-  
-/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
-  * @{
-  */  
-#define	TIM_TRGO_RESET            ((uint32_t)0x00000000U)
-#define	TIM_TRGO_ENABLE           (TIM_CR2_MMS_0)
-#define	TIM_TRGO_UPDATE           (TIM_CR2_MMS_1)
-#define	TIM_TRGO_OC1              ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
-#define	TIM_TRGO_OC1REF           (TIM_CR2_MMS_2)
-#define	TIM_TRGO_OC2REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
-#define	TIM_TRGO_OC3REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
-#define	TIM_TRGO_OC4REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
-/**
-  * @}
-  */ 
-  
-/** @defgroup TIM_Slave_Mode TIM Slave Mode
-  * @{
-  */
-#define TIM_SLAVEMODE_DISABLE              ((uint32_t)0x00000000U)
-#define TIM_SLAVEMODE_RESET                ((uint32_t)0x00000004U)
-#define TIM_SLAVEMODE_GATED                ((uint32_t)0x00000005U)
-#define TIM_SLAVEMODE_TRIGGER              ((uint32_t)0x00000006U)
-#define TIM_SLAVEMODE_EXTERNAL1            ((uint32_t)0x00000007U)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Master_Slave_Mode  TIM Master Slave Mode
-  * @{
-  */
-#define TIM_MASTERSLAVEMODE_ENABLE          ((uint32_t)0x00000080U)
-#define TIM_MASTERSLAVEMODE_DISABLE         ((uint32_t)0x00000000U)
-/**
-  * @}
-  */ 
-  
-/** @defgroup TIM_Trigger_Selection  TIM Trigger Selection
-  * @{
-  */
-#define TIM_TS_ITR0                        ((uint32_t)0x00000000U)
-#define TIM_TS_ITR1                        ((uint32_t)0x00000010U)
-#define TIM_TS_ITR2                        ((uint32_t)0x00000020U)
-#define TIM_TS_ITR3                        ((uint32_t)0x00000030U)
-#define TIM_TS_TI1F_ED                     ((uint32_t)0x00000040U)
-#define TIM_TS_TI1FP1                      ((uint32_t)0x00000050U)
-#define TIM_TS_TI2FP2                      ((uint32_t)0x00000060U)
-#define TIM_TS_ETRF                        ((uint32_t)0x00000070U)
-#define TIM_TS_NONE                        ((uint32_t)0x0000FFFFU)
-/**
-  * @}
-  */  
-
-/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
-  * @{
-  */
-#define TIM_TRIGGERPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx trigger sources */ 
-#define TIM_TRIGGERPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx trigger sources */ 
-#define TIM_TRIGGERPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING        /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 
-#define TIM_TRIGGERPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING       /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 
-#define TIM_TRIGGERPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE      /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
-  * @{
-  */
-#define TIM_TRIGGERPRESCALER_DIV1             TIM_ETRPRESCALER_DIV1     /*!< No prescaler is used */
-#define TIM_TRIGGERPRESCALER_DIV2             TIM_ETRPRESCALER_DIV2     /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
-#define TIM_TRIGGERPRESCALER_DIV4             TIM_ETRPRESCALER_DIV4     /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
-#define TIM_TRIGGERPRESCALER_DIV8             TIM_ETRPRESCALER_DIV8     /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
-/**
-  * @}
-  */
-
-
-/** @defgroup TIM_TI1_Selection TIM TI1 Selection
-  * @{
-  */
-#define TIM_TI1SELECTION_CH1                ((uint32_t)0x00000000U)
-#define TIM_TI1SELECTION_XORCOMBINATION     (TIM_CR2_TI1S)
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_DMA_Base_address  TIM DMA Base address
-  * @{
-  */
-#define TIM_DMABASE_CR1                    (0x00000000U)
-#define TIM_DMABASE_CR2                    (0x00000001U)
-#define TIM_DMABASE_SMCR                   (0x00000002U)
-#define TIM_DMABASE_DIER                   (0x00000003U)
-#define TIM_DMABASE_SR                     (0x00000004U)
-#define TIM_DMABASE_EGR                    (0x00000005U)
-#define TIM_DMABASE_CCMR1                  (0x00000006U)
-#define TIM_DMABASE_CCMR2                  (0x00000007U)
-#define TIM_DMABASE_CCER                   (0x00000008U)
-#define TIM_DMABASE_CNT                    (0x00000009U)
-#define TIM_DMABASE_PSC                    (0x0000000AU)
-#define TIM_DMABASE_ARR                    (0x0000000BU)
-#define TIM_DMABASE_RCR                    (0x0000000CU)
-#define TIM_DMABASE_CCR1                   (0x0000000DU)
-#define TIM_DMABASE_CCR2                   (0x0000000EU)
-#define TIM_DMABASE_CCR3                   (0x0000000FU)
-#define TIM_DMABASE_CCR4                   (0x00000010U)
-#define TIM_DMABASE_BDTR                   (0x00000011U)
-#define TIM_DMABASE_DCR                    (0x00000012U)
-#define TIM_DMABASE_OR                     (0x00000013U)
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_DMA_Burst_Length  TIM DMA Burst Length 
-  * @{
-  */
-#define TIM_DMABURSTLENGTH_1TRANSFER           (0x00000000U)
-#define TIM_DMABURSTLENGTH_2TRANSFERS          (0x00000100U)
-#define TIM_DMABURSTLENGTH_3TRANSFERS          (0x00000200U)
-#define TIM_DMABURSTLENGTH_4TRANSFERS          (0x00000300U)
-#define TIM_DMABURSTLENGTH_5TRANSFERS          (0x00000400U)
-#define TIM_DMABURSTLENGTH_6TRANSFERS          (0x00000500U)
-#define TIM_DMABURSTLENGTH_7TRANSFERS          (0x00000600U)
-#define TIM_DMABURSTLENGTH_8TRANSFERS          (0x00000700U)
-#define TIM_DMABURSTLENGTH_9TRANSFERS          (0x00000800U)
-#define TIM_DMABURSTLENGTH_10TRANSFERS         (0x00000900U)
-#define TIM_DMABURSTLENGTH_11TRANSFERS         (0x00000A00U)
-#define TIM_DMABURSTLENGTH_12TRANSFERS         (0x00000B00U)
-#define TIM_DMABURSTLENGTH_13TRANSFERS         (0x00000C00U)
-#define TIM_DMABURSTLENGTH_14TRANSFERS         (0x00000D00U)
-#define TIM_DMABURSTLENGTH_15TRANSFERS         (0x00000E00U)
-#define TIM_DMABURSTLENGTH_16TRANSFERS         (0x00000F00U)
-#define TIM_DMABURSTLENGTH_17TRANSFERS         (0x00001000U)
-#define TIM_DMABURSTLENGTH_18TRANSFERS         (0x00001100U)
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Handle_index  DMA Handle index
-  * @{
-  */
-#define TIM_DMA_ID_UPDATE                ((uint16_t) 0x0000U)       /*!< Index of the DMA handle used for Update DMA requests */
-#define TIM_DMA_ID_CC1                   ((uint16_t) 0x0001U)       /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
-#define TIM_DMA_ID_CC2                   ((uint16_t) 0x0002U)       /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
-#define TIM_DMA_ID_CC3                   ((uint16_t) 0x0003U)       /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
-#define TIM_DMA_ID_CC4                   ((uint16_t) 0x0004U)       /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
-#define TIM_DMA_ID_COMMUTATION           ((uint16_t) 0x0005U)       /*!< Index of the DMA handle used for Commutation DMA requests */
-#define TIM_DMA_ID_TRIGGER               ((uint16_t) 0x0006U)       /*!< Index of the DMA handle used for Trigger DMA requests */
-/**
-  * @}
-  */ 
-
-/** @defgroup Channel_CC_State  Channel CC State
-  * @{
-  */
-#define TIM_CCx_ENABLE                   ((uint32_t)0x00000001U)
-#define TIM_CCx_DISABLE                  ((uint32_t)0x00000000U)
-#define TIM_CCxN_ENABLE                  ((uint32_t)0x00000004U)
-#define TIM_CCxN_DISABLE                 ((uint32_t)0x00000000U)
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */   
-  
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup TIM_Exported_Macros TIM Exported Macros
-  * @{
-  */
-/** @brief Reset TIM handle state
-  * @param  __HANDLE__: TIM handle
-  * @retval None
-  */
-#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
-
-/**
-  * @brief  Enable the TIM peripheral.
-  * @param  __HANDLE__: TIM handle
-  * @retval None
- */
-#define __HAL_TIM_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
-
-/**
-  * @brief  Enable the TIM main Output.
-  * @param  __HANDLE__: TIM handle
-  * @retval None
-  */
-#define __HAL_TIM_MOE_ENABLE(__HANDLE__)             ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
-
-
-/**
-  * @brief  Disable the TIM peripheral.
-  * @param  __HANDLE__: TIM handle
-  * @retval None
-  */
-#define __HAL_TIM_DISABLE(__HANDLE__) \
-                        do { \
-                          if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
-                          { \
-                            if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
-                            { \
-                              (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
-                            } \
-                          } \
-                        } while(0)
-
-/* The Main Output of a timer instance is disabled only if all the CCx and CCxN
-   channels have been disabled */
-/**
-  * @brief  Disable the TIM main Output.
-  * @param  __HANDLE__: TIM handle
-  * @retval None
-  */
-#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
-                        do { \
-                          if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
-                          { \
-                            if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
-                            { \
-                              (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
-                            } \
-                          } \
-                        } while(0)
-
-#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
-#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)         ((__HANDLE__)->Instance->DIER |= (__DMA__))
-#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
-#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)        ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
-#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
-#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-
-#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
-
-#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__)            (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
-#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__)       ((__HANDLE__)->Instance->PSC = (__PRESC__))
-
-#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
- ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
-
-#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
- ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
-
-#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
- ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U) & TIM_CCER_CC4P)))
-
-#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
- ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
-
-/**
-  * @brief  Sets the TIM Capture Compare Register value on runtime without
-  *         calling another time ConfigChannel function.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CHANNEL__ : TIM Channels to be configured.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  __COMPARE__: specifies the Capture Compare register new value.
-  * @retval None
-  */
-#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
-(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
-
-/**
-  * @brief  Gets the TIM Capture Compare Register value on runtime
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CHANNEL__ : TIM Channel associated with the capture compare register
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: get capture/compare 1 register value
-  *            @arg TIM_CHANNEL_2: get capture/compare 2 register value
-  *            @arg TIM_CHANNEL_3: get capture/compare 3 register value
-  *            @arg TIM_CHANNEL_4: get capture/compare 4 register value
-  * @retval None
-  */
-#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
-  (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
-
-/**
-  * @brief  Sets the TIM Counter Register value on runtime.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __COUNTER__: specifies the Counter register new value.
-  * @retval None
-  */
-#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
-
-/**
-  * @brief  Gets the TIM Counter Register value on runtime.
-  * @param  __HANDLE__: TIM handle.
-  * @retval None
-  */
-#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
-
-/**
-  * @brief  Sets the TIM Autoreload Register value on runtime without calling 
-  *         another time any Init function.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __AUTORELOAD__: specifies the Counter register new value.
-  * @retval None
-  */
-#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__)                  \
-                        do{                                                  \
-                            (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
-                            (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
-                          } while(0)
-/**
-  * @brief  Gets the TIM Autoreload Register value on runtime
-  * @param  __HANDLE__: TIM handle.
-  * @retval None
-  */
-#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
-
-/**
-  * @brief  Sets the TIM Clock Division value on runtime without calling 
-  *         another time any Init function. 
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CKD__: specifies the clock division value.
-  *          This parameter can be one of the following value:
-  *            @arg TIM_CLOCKDIVISION_DIV1
-  *            @arg TIM_CLOCKDIVISION_DIV2
-  *            @arg TIM_CLOCKDIVISION_DIV4
-  * @retval None
-  */
-#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
-                        do{                                                             \
-                              (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD);  \
-                              (__HANDLE__)->Instance->CR1 |= (__CKD__);                 \
-                              (__HANDLE__)->Init.ClockDivision = (__CKD__);             \
-                          } while(0)
-/**
-  * @brief  Gets the TIM Clock Division value on runtime
-  * @param  __HANDLE__: TIM handle.
-  * @retval None
-  */
-#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
-
-/**
-  * @brief  Sets the TIM Input Capture prescaler on runtime without calling 
-  *         another time HAL_TIM_IC_ConfigChannel() function.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CHANNEL__ : TIM Channels to be configured.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  __ICPSC__: specifies the Input Capture4 prescaler new value.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPSC_DIV1: no prescaler
-  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
-  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
-  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
-  * @retval None
-  */
-#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
-                        do{                                                    \
-                              TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
-                              TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
-                          } while(0)
-
-/**
-  * @brief  Gets the TIM Input Capture prescaler on runtime
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CHANNEL__ : TIM Channels to be configured.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value
-  *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value
-  *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value
-  *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value
-  * @retval None
-  */
-#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)  \
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
-   (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
-    
-/**
-  * @brief  Set the Update Request Source (URS) bit of the TIMx_CR1 register
-  * @param  __HANDLE__: TIM handle.
-  * @note  When the USR bit of the TIMx_CR1 register is set, only counter 
-  *        overflow/underflow generates an update interrupt or DMA request (if
-  *        enabled)
-  * @retval None
-  */
-#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
-    ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
-
-/**
-  * @brief  Reset the Update Request Source (URS) bit of the TIMx_CR1 register
-  * @param  __HANDLE__: TIM handle.
-  * @note  When the USR bit of the TIMx_CR1 register is reset, any of the 
-  *        following events generate an update interrupt or DMA request (if 
-  *        enabled):
-  *          _ Counter overflow/underflow
-  *          _ Setting the UG bit
-  *          _ Update generation through the slave mode controller
-  * @retval None
-  */
-#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
-      ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
-
-/**
-  * @brief  Sets the TIM Capture x input polarity on runtime.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CHANNEL__: TIM Channels to be configured.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  __POLARITY__: Polarity for TIx source   
-  *            @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
-  *            @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
-  *            @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
-  * @note  The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized  for TIM Channel 4.     
-  * @retval None
-  */
-#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)                          \
-                       do{                                                                            \
-                           TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
-                           TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
-                         }while(0)
-/**
-  * @}
-  */
-
-/* Include TIM HAL Extension module */
-#include "stm32f4xx_hal_tim_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIM_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group1
-  * @{
-  */
-
-/* Time Base functions ********************************************************/
-HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group2
-  * @{
-  */
-/* Timer Output Compare functions **********************************************/
-HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group3
-  * @{
-  */
-/* Timer PWM functions *********************************************************/
-HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group4
-  * @{
-  */
-/* Timer Input Capture functions ***********************************************/
-HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group5
-  * @{
-  */
-/* Timer One Pulse functions ***************************************************/
-HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
-HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group6
-  * @{
-  */
-/* Timer Encoder functions *****************************************************/
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef* sConfig);
-HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
- /* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group7
-  * @{
-  */
-/* Interrupt Handler functions  **********************************************/
-void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
-
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group8
-  * @{
-  */
-/* Control functions  *********************************************************/
-HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel,  uint32_t InputChannel);
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);    
-HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
-                                              uint32_t  *BurstBuffer, uint32_t  BurstLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
-                                              uint32_t  *BurstBuffer, uint32_t  BurstLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
-HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
-uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group9
-  * @{
-  */
-/* Callback in non blocking modes (Interrupt and DMA) *************************/
-void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
-
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group10
-  * @{
-  */
-/* Peripheral State functions  **************************************************/
-HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-  
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup TIM_Private_Macros TIM Private Macros
-  * @{
-  */
-
-/** @defgroup TIM_IS_TIM_Definitions TIM Private macros to check input parameters
-  * @{
-  */
-#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP)              || \
-                                   ((MODE) == TIM_COUNTERMODE_DOWN)            || \
-                                   ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
-                                   ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
-                                   ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
-
-#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
-                                       ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
-                                       ((DIV) == TIM_CLOCKDIVISION_DIV4))
-
-#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
-                               ((MODE) == TIM_OCMODE_PWM2))
-                              
-#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING)       || \
-                          ((MODE) == TIM_OCMODE_ACTIVE)           || \
-                          ((MODE) == TIM_OCMODE_INACTIVE)         || \
-                          ((MODE) == TIM_OCMODE_TOGGLE)           || \
-                          ((MODE) == TIM_OCMODE_FORCED_ACTIVE)    || \
-                          ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
-
-#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
-                                  ((STATE) == TIM_OCFAST_ENABLE))
-
-#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
-                                      ((POLARITY) == TIM_OCPOLARITY_LOW))
-
-#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
-                                       ((POLARITY) == TIM_OCNPOLARITY_LOW))
-
-#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
-                                    ((STATE) == TIM_OCIDLESTATE_RESET))
-
-#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
-                                    ((STATE) == TIM_OCNIDLESTATE_RESET))
-
-#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
-                                  ((CHANNEL) == TIM_CHANNEL_2) || \
-                                  ((CHANNEL) == TIM_CHANNEL_3) || \
-                                  ((CHANNEL) == TIM_CHANNEL_4) || \
-                                  ((CHANNEL) == TIM_CHANNEL_ALL))
-
-#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
-                                      ((CHANNEL) == TIM_CHANNEL_2))
-
-#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
-                                                ((CHANNEL) == TIM_CHANNEL_2) || \
-                                                ((CHANNEL) == TIM_CHANNEL_3))
-
-#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING)   || \
-                                      ((POLARITY) == TIM_ICPOLARITY_FALLING)  || \
-                                      ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
-
-#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
-                                        ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
-                                        ((SELECTION) == TIM_ICSELECTION_TRC))
-
-#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
-                                        ((PRESCALER) == TIM_ICPSC_DIV2) || \
-                                        ((PRESCALER) == TIM_ICPSC_DIV4) || \
-                                        ((PRESCALER) == TIM_ICPSC_DIV8))
-
-#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
-                               ((MODE) == TIM_OPMODE_REPETITIVE))
-
-#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))
-
-#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
-                                   ((MODE) == TIM_ENCODERMODE_TI2) || \
-                                   ((MODE) == TIM_ENCODERMODE_TI12))
-
-#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
-
-#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_ITR0)     || \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_ITR1)     || \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_ITR2)     || \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_ITR3)     || \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_TI1ED)    || \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_TI1)      || \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_TI2)      || \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
-
-#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED)    || \
-                                        ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
-                                        ((POLARITY) == TIM_CLOCKPOLARITY_RISING)      || \
-                                        ((POLARITY) == TIM_CLOCKPOLARITY_FALLING)     || \
-                                        ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
-
-#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
-                                          ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
-                                          ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
-                                          ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
-
-#define IS_TIM_CLOCKFILTER(ICFILTER)      ((ICFILTER) <= 0x0FU) 
-
-#define IS_TIM_CLEARINPUT_SOURCE(SOURCE)  (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
-                                         ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR)) 
-
-#define IS_TIM_CLEARINPUT_POLARITY(POLARITY)   (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
-                                               ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
-
-#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER)   (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
-                                                 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
-                                                 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
-                                                 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
-
-#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU) 
-
-#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
-                                  ((STATE) == TIM_OSSR_DISABLE))
-
-#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
-                                  ((STATE) == TIM_OSSI_DISABLE))
-
-#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
-                                  ((LEVEL) == TIM_LOCKLEVEL_1) || \
-                                  ((LEVEL) == TIM_LOCKLEVEL_2) || \
-                                  ((LEVEL) == TIM_LOCKLEVEL_3))
-
-#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
-                                   ((STATE) == TIM_BREAK_DISABLE))
-
-#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
-                                         ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
-
-#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
-                                              ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
-
-#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
-                                    ((SOURCE) == TIM_TRGO_ENABLE) || \
-                                    ((SOURCE) == TIM_TRGO_UPDATE) || \
-                                    ((SOURCE) == TIM_TRGO_OC1) || \
-                                    ((SOURCE) == TIM_TRGO_OC1REF) || \
-                                    ((SOURCE) == TIM_TRGO_OC2REF) || \
-                                    ((SOURCE) == TIM_TRGO_OC3REF) || \
-                                    ((SOURCE) == TIM_TRGO_OC4REF))
-
-#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
-                                 ((MODE) == TIM_SLAVEMODE_GATED) || \
-                                 ((MODE) == TIM_SLAVEMODE_RESET) || \
-                                 ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
-                                 ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
-
-#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
-                                 ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
-
-#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
-                                             ((SELECTION) == TIM_TS_ITR1) || \
-                                             ((SELECTION) == TIM_TS_ITR2) || \
-                                             ((SELECTION) == TIM_TS_ITR3) || \
-                                             ((SELECTION) == TIM_TS_TI1F_ED) || \
-                                             ((SELECTION) == TIM_TS_TI1FP1) || \
-                                             ((SELECTION) == TIM_TS_TI2FP2) || \
-                                             ((SELECTION) == TIM_TS_ETRF))
-
-#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
-                                                           ((SELECTION) == TIM_TS_ITR1) || \
-                                                           ((SELECTION) == TIM_TS_ITR2) || \
-                                                           ((SELECTION) == TIM_TS_ITR3) || \
-                                                           ((SELECTION) == TIM_TS_NONE))
-
-#define IS_TIM_TRIGGERPOLARITY(POLARITY)     (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
-                                              ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
-                                              ((POLARITY) == TIM_TRIGGERPOLARITY_RISING     ) || \
-                                              ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING    ) || \
-                                              ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))
-
-#define IS_TIM_TRIGGERPRESCALER(PRESCALER)  (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
-                                             ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
-                                             ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
-                                             ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
-
-#define IS_TIM_TRIGGERFILTER(ICFILTER)     ((ICFILTER) <= 0x0FU) 
-
-#define IS_TIM_TI1SELECTION(TI1SELECTION)   (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
-                                             ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
-
-#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \
-                               ((BASE) == TIM_DMABASE_CR2) || \
-                               ((BASE) == TIM_DMABASE_SMCR) || \
-                               ((BASE) == TIM_DMABASE_DIER) || \
-                               ((BASE) == TIM_DMABASE_SR) || \
-                               ((BASE) == TIM_DMABASE_EGR) || \
-                               ((BASE) == TIM_DMABASE_CCMR1) || \
-                               ((BASE) == TIM_DMABASE_CCMR2) || \
-                               ((BASE) == TIM_DMABASE_CCER) || \
-                               ((BASE) == TIM_DMABASE_CNT) || \
-                               ((BASE) == TIM_DMABASE_PSC) || \
-                               ((BASE) == TIM_DMABASE_ARR) || \
-                               ((BASE) == TIM_DMABASE_RCR) || \
-                               ((BASE) == TIM_DMABASE_CCR1) || \
-                               ((BASE) == TIM_DMABASE_CCR2) || \
-                               ((BASE) == TIM_DMABASE_CCR3) || \
-                               ((BASE) == TIM_DMABASE_CCR4) || \
-                               ((BASE) == TIM_DMABASE_BDTR) || \
-                               ((BASE) == TIM_DMABASE_DCR) || \
-                               ((BASE) == TIM_DMABASE_OR))
-
-#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
-
-#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0x0F)
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Mask_Definitions TIM Mask Definition
-  * @{
-  */  
-/* The counter of a timer instance is disabled only if all the CCx and CCxN
-   channels have been disabled */
-#define TIM_CCER_CCxE_MASK  ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
-#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup TIM_Private_Functions TIM Private Functions
-  * @{
-  */
-void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
-void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
-void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
-void TIM_DMAError(DMA_HandleTypeDef *hdma);
-void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
-void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);  
-/**
-  * @}
-  */ 
-      
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_TIM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_tim_ex.h b/stmhal/hal/f4/inc/stm32f4xx_hal_tim_ex.h
deleted file mode 100644
index bff94e1d5b..0000000000
--- a/stmhal/hal/f4/inc/stm32f4xx_hal_tim_ex.h
+++ /dev/null
@@ -1,344 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_tim_ex.h
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   Header file of TIM HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_TIM_EX_H
-#define __STM32F4xx_HAL_TIM_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup TIMEx
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup TIMEx_Exported_Types TIM Exported Types
-  * @{
-  */
-  
-/** 
-  * @brief  TIM Hall sensor Configuration Structure definition  
-  */
-
-typedef struct
-{
-
-  uint32_t IC1Polarity;            /*!< Specifies the active edge of the input signal.
-                                        This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
-  uint32_t IC1Prescaler;        /*!< Specifies the Input Capture Prescaler.
-                                     This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
-  uint32_t IC1Filter;           /*!< Specifies the input capture filter.
-                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-
-  uint32_t Commutation_Delay;  /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 
-                                    This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
-} TIM_HallSensor_InitTypeDef;
-
-/** 
-  * @brief  TIM Master configuration Structure definition  
-  */ 
-typedef struct {
-  uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection. 
-                                      This parameter can be a value of @ref TIM_Master_Mode_Selection */
-
-  uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection. 
-                                      This parameter can be a value of @ref TIM_Master_Slave_Mode */
-}TIM_MasterConfigTypeDef;
-
-/** 
-  * @brief  TIM Break and Dead time configuration Structure definition  
-  */ 
-typedef struct
-{
-  uint32_t OffStateRunMode;            /*!< TIM off state in run mode.
-                                         This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
-  uint32_t OffStateIDLEMode;          /*!< TIM off state in IDLE mode.
-                                         This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
-  uint32_t LockLevel;                     /*!< TIM Lock level.
-                                         This parameter can be a value of @ref TIM_Lock_level */                             
-  uint32_t DeadTime;                     /*!< TIM dead Time. 
-                                         This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
-  uint32_t BreakState;                   /*!< TIM Break State. 
-                                         This parameter can be a value of @ref TIM_Break_Input_enable_disable */
-  uint32_t BreakPolarity;                 /*!< TIM Break input polarity. 
-                                         This parameter can be a value of @ref TIM_Break_Polarity */
-  uint32_t AutomaticOutput;               /*!< TIM Automatic Output Enable state. 
-                                         This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */           
-}TIM_BreakDeadTimeConfigTypeDef;
-/**
-  * @}
-  */
-  
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Constants  TIM Exported Constants
-  * @{
-  */
-  
-/** @defgroup TIMEx_Remap  TIM Remap
-  * @{
-  */
-#define TIM_TIM2_TIM8_TRGO                     (0x00000000U)
-#define TIM_TIM2_ETH_PTP                       (0x00000400U)
-#define TIM_TIM2_USBFS_SOF                     (0x00000800U)
-#define TIM_TIM2_USBHS_SOF                     (0x00000C00U)
-#define TIM_TIM5_GPIO                          (0x00000000U)
-#define TIM_TIM5_LSI                           (0x00000040U)
-#define TIM_TIM5_LSE                           (0x00000080U)
-#define TIM_TIM5_RTC                           (0x000000C0U)
-#define TIM_TIM11_GPIO                         (0x00000000U)
-#define TIM_TIM11_HSE                          (0x00000002U)
-
-#if defined (STM32F446xx) 
-#define TIM_TIM11_SPDIFRX                        (0x00000001U)
-#endif /* STM32F446xx */
-/**
-  * @}
-  */
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 
-/** @defgroup TIMEx_SystemBreakInput  TIM System Break Input
-  * @{
-  */
-#define TIM_SYSTEMBREAKINPUT_HARDFAULT     ((uint32_t)0x00000001U) /* Core Lockup lock output(Hardfault) is connected to Break Input of TIM1 and TIM8 */
-#define TIM_SYSTEMBREAKINPUT_PVD           ((uint32_t)0x00000004U) /* PVD Interrupt is connected to Break Input of TIM1 and TIM8 */
-#define TIM_SYSTEMBREAKINPUT_HARDFAULT_PVD ((uint32_t)0x00000005U) /* Core Lockup lock output(Hardfault) and PVD Interrupt are connected to Break Input of TIM1 and TIM8 */   
-/**
-  * @}
-  */
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-
-/**
-  * @}
-  */ 
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIMEx_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup TIMEx_Exported_Functions_Group1
-  * @{
-  */
-/*  Timer Hall Sensor functions  **********************************************/
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef* htim, TIM_HallSensor_InitTypeDef* sConfig);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef* htim);
-
-void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef* htim);
-void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef* htim);
-
- /* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef* htim);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef* htim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef* htim);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef* htim);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef* htim, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef* htim);
-/**
-  * @}
-  */
-
-/** @addtogroup TIMEx_Exported_Functions_Group2
-  * @{
-  */
-/*  Timer Complementary Output Compare functions  *****************************/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);
-
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
-
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);
-/**
-  * @}
-  */
-
-/** @addtogroup TIMEx_Exported_Functions_Group3
-  * @{
-  */
-/*  Timer Complementary PWM functions  ****************************************/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);
-
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);
-/**
-  * @}
-  */
-
-/** @addtogroup TIMEx_Exported_Functions_Group4
-  * @{
-  */
-/*  Timer Complementary One Pulse functions  **********************************/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
-
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
-/**
-  * @}
-  */
-
-/** @addtogroup TIMEx_Exported_Functions_Group5
-  * @{
-  */
-/* Extension Control functions  ************************************************/
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef* htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef* htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef* htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef* htim, TIM_MasterConfigTypeDef * sMasterConfig);
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef* htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
-HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef* htim, uint32_t Remap);
-/**
-  * @}
-  */
-
-/** @addtogroup TIMEx_Exported_Functions_Group6
-  * @{
-  */ 
-/* Extension Callback *********************************************************/
-void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef* htim);
-void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef* htim);
-void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
-/**
-  * @}
-  */
-
-/** @addtogroup TIMEx_Exported_Functions_Group7
-  * @{
-  */
-/* Extension Peripheral State functions  **************************************/
-HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef* htim);
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup TIMEx_Private_Macros TIM Private Macros
-  * @{
-  */
-#if defined (STM32F446xx) 
-#define IS_TIM_REMAP(TIM_REMAP)   (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO)||\
-                                  ((TIM_REMAP) == TIM_TIM2_ETH_PTP)||\
-                                  ((TIM_REMAP) == TIM_TIM2_USBFS_SOF)||\
-                                  ((TIM_REMAP) == TIM_TIM2_USBHS_SOF)||\
-                                  ((TIM_REMAP) == TIM_TIM5_GPIO)||\
-                                  ((TIM_REMAP) == TIM_TIM5_LSI)||\
-                                  ((TIM_REMAP) == TIM_TIM5_LSE)||\
-                                  ((TIM_REMAP) == TIM_TIM5_RTC)||\
-                                  ((TIM_REMAP) == TIM_TIM11_GPIO)||\
-                                  ((TIM_REMAP) == TIM_TIM11_SPDIFRX)||\
-                                  ((TIM_REMAP) == TIM_TIM11_HSE))
-#else
-#define IS_TIM_REMAP(TIM_REMAP)   (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO)||\
-                                  ((TIM_REMAP) == TIM_TIM2_ETH_PTP)||\
-                                  ((TIM_REMAP) == TIM_TIM2_USBFS_SOF)||\
-                                  ((TIM_REMAP) == TIM_TIM2_USBHS_SOF)||\
-                                  ((TIM_REMAP) == TIM_TIM5_GPIO)||\
-                                  ((TIM_REMAP) == TIM_TIM5_LSI)||\
-                                  ((TIM_REMAP) == TIM_TIM5_LSE)||\
-                                  ((TIM_REMAP) == TIM_TIM5_RTC)||\
-                                  ((TIM_REMAP) == TIM_TIM11_GPIO)||\
-                                  ((TIM_REMAP) == TIM_TIM11_HSE))
-#endif /* STM32F446xx */
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-#define IS_TIM_SYSTEMBREAKINPUT(BREAKINPUT)   (((BREAKINPUT) == TIM_SYSTEMBREAKINPUT_HARDFAULT)||\
-                                               ((BREAKINPUT) == TIM_SYSTEMBREAKINPUT_PVD)||\
-                                               ((BREAKINPUT) == TIM_SYSTEMBREAKINPUT_HARDFAULT_PVD))
-
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 
-
-#define IS_TIM_DEADTIME(DEADTIME)      ((DEADTIME) <= 0xFFU) 
-/**
-  * @}
-  */  
-  
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup TIMEx_Private_Functions TIM Private Functions
-  * @{
-  */
-  
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-    
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_TIM_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_uart.h b/stmhal/hal/f4/inc/stm32f4xx_hal_uart.h
deleted file mode 100644
index 2e40e0faf1..0000000000
--- a/stmhal/hal/f4/inc/stm32f4xx_hal_uart.h
+++ /dev/null
@@ -1,784 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_uart.h
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   Header file of UART HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_UART_H
-#define __STM32F4xx_HAL_UART_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup UART
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup UART_Exported_Types UART Exported Types
-  * @{
-  */
-
-/** 
-  * @brief UART Init Structure definition  
-  */ 
-typedef struct
-{
-  uint32_t BaudRate;                  /*!< This member configures the UART communication baud rate.
-                                           The baud rate is computed using the following formula:
-                                           - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (huart->Init.BaudRate)))
-                                           - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8 * (OVR8+1)) + 0.5 
-                                           Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */
-
-  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
-                                           This parameter can be a value of @ref UART_Word_Length */
-
-  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
-                                           This parameter can be a value of @ref UART_Stop_Bits */
-
-  uint32_t Parity;                    /*!< Specifies the parity mode.
-                                           This parameter can be a value of @ref UART_Parity
-                                           @note When parity is enabled, the computed parity is inserted
-                                                 at the MSB position of the transmitted data (9th bit when
-                                                 the word length is set to 9 data bits; 8th bit when the
-                                                 word length is set to 8 data bits). */
- 
-  uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
-                                           This parameter can be a value of @ref UART_Mode */
-
-  uint32_t HwFlowCtl;                 /*!< Specifies whether the hardware flow control mode is enabled
-                                           or disabled.
-                                           This parameter can be a value of @ref UART_Hardware_Flow_Control */
-  
-  uint32_t OverSampling;              /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
-                                           This parameter can be a value of @ref UART_Over_Sampling */ 
-}UART_InitTypeDef;
-
-/** 
-  * @brief HAL UART State structures definition  
-  * @note  HAL UART State value is a combination of 2 different substates: gState and RxState.
-  *        - gState contains UART state information related to global Handle management 
-  *          and also information related to Tx operations.
-  *          gState value coding follow below described bitmap :
-  *          b7-b6  Error information 
-  *             00 : No Error
-  *             01 : (Not Used)
-  *             10 : Timeout
-  *             11 : Error
-  *          b5     IP initilisation status
-  *             0  : Reset (IP not initialized)
-  *             1  : Init done (IP not initialized. HAL UART Init function already called)
-  *          b4-b3  (not used)
-  *             xx : Should be set to 00
-  *          b2     Intrinsic process state
-  *             0  : Ready
-  *             1  : Busy (IP busy with some configuration or internal operations)
-  *          b1     (not used)
-  *             x  : Should be set to 0
-  *          b0     Tx state
-  *             0  : Ready (no Tx operation ongoing)
-  *             1  : Busy (Tx operation ongoing)
-  *        - RxState contains information related to Rx operations.
-  *          RxState value coding follow below described bitmap :
-  *          b7-b6  (not used)
-  *             xx : Should be set to 00
-  *          b5     IP initilisation status
-  *             0  : Reset (IP not initialized)
-  *             1  : Init done (IP not initialized)
-  *          b4-b2  (not used)
-  *            xxx : Should be set to 000
-  *          b1     Rx state
-  *             0  : Ready (no Rx operation ongoing)
-  *             1  : Busy (Rx operation ongoing)
-  *          b0     (not used)
-  *             x  : Should be set to 0.
-  */ 
-typedef enum
-{
-  HAL_UART_STATE_RESET             = 0x00U,    /*!< Peripheral is not yet Initialized 
-                                                   Value is allowed for gState and RxState */
-  HAL_UART_STATE_READY             = 0x20U,    /*!< Peripheral Initialized and ready for use
-                                                   Value is allowed for gState and RxState */
-  HAL_UART_STATE_BUSY              = 0x24U,    /*!< an internal process is ongoing
-                                                   Value is allowed for gState only */
-  HAL_UART_STATE_BUSY_TX           = 0x21U,    /*!< Data Transmission process is ongoing 
-                                                   Value is allowed for gState only */
-  HAL_UART_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing
-                                                   Value is allowed for RxState only */
-  HAL_UART_STATE_BUSY_TX_RX        = 0x23U,    /*!< Data Transmission and Reception process is ongoing 
-                                                   Not to be used for neither gState nor RxState.
-                                                   Value is result of combination (Or) between gState and RxState values */
-  HAL_UART_STATE_TIMEOUT           = 0xA0U,    /*!< Timeout state    
-                                                   Value is allowed for gState only */
-  HAL_UART_STATE_ERROR             = 0xE0U     /*!< Error   
-                                                   Value is allowed for gState only */
-}HAL_UART_StateTypeDef;
-
-/** 
-  * @brief  UART handle Structure definition  
-  */  
-typedef struct
-{
-  USART_TypeDef                 *Instance;        /*!< UART registers base address        */
-  
-  UART_InitTypeDef              Init;             /*!< UART communication parameters      */
-  
-  uint8_t                       *pTxBuffPtr;      /*!< Pointer to UART Tx transfer Buffer */
-  
-  uint16_t                      TxXferSize;       /*!< UART Tx Transfer size              */
-  
-  __IO uint16_t                 TxXferCount;      /*!< UART Tx Transfer Counter           */
-  
-  uint8_t                       *pRxBuffPtr;      /*!< Pointer to UART Rx transfer Buffer */
-  
-  uint16_t                      RxXferSize;       /*!< UART Rx Transfer size              */
-  
-  __IO uint16_t                 RxXferCount;      /*!< UART Rx Transfer Counter           */  
-  
-  DMA_HandleTypeDef             *hdmatx;          /*!< UART Tx DMA Handle parameters      */
-    
-  DMA_HandleTypeDef             *hdmarx;          /*!< UART Rx DMA Handle parameters      */
-  
-  HAL_LockTypeDef               Lock;             /*!< Locking object                     */
-
-  __IO HAL_UART_StateTypeDef    gState;           /*!< UART state information related to global Handle management 
-                                                       and also related to Tx operations.
-                                                       This parameter can be a value of @ref HAL_UART_StateTypeDef */
-  
-  __IO HAL_UART_StateTypeDef    RxState;          /*!< UART state information related to Rx operations.
-                                                       This parameter can be a value of @ref HAL_UART_StateTypeDef */
-  
-  __IO uint32_t                 ErrorCode;        /*!< UART Error code                    */
-
-}UART_HandleTypeDef;
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup UART_Exported_Constants UART Exported constants
-  * @{
-  */
-
-/** @defgroup UART_Error_Code UART Error Code
-  * @brief    UART Error Code 
-  * @{
-  */ 
-#define HAL_UART_ERROR_NONE         ((uint32_t)0x00000000U)   /*!< No error            */
-#define HAL_UART_ERROR_PE           ((uint32_t)0x00000001U)   /*!< Parity error        */
-#define HAL_UART_ERROR_NE           ((uint32_t)0x00000002U)   /*!< Noise error         */
-#define HAL_UART_ERROR_FE           ((uint32_t)0x00000004U)   /*!< Frame error         */
-#define HAL_UART_ERROR_ORE          ((uint32_t)0x00000008U)   /*!< Overrun error       */
-#define HAL_UART_ERROR_DMA          ((uint32_t)0x00000010U)   /*!< DMA transfer error  */
-/**
-  * @}
-  */
-
-/** @defgroup UART_Word_Length UART Word Length
-  * @{
-  */
-#define UART_WORDLENGTH_8B                  ((uint32_t)0x00000000U)
-#define UART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M)
-/**
-  * @}
-  */
-
-/** @defgroup UART_Stop_Bits UART Number of Stop Bits
-  * @{
-  */
-#define UART_STOPBITS_1                     ((uint32_t)0x00000000U)
-#define UART_STOPBITS_2                     ((uint32_t)USART_CR2_STOP_1)
-/**
-  * @}
-  */ 
-
-/** @defgroup UART_Parity UART Parity
-  * @{
-  */ 
-#define UART_PARITY_NONE                    ((uint32_t)0x00000000U)
-#define UART_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)
-#define UART_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) 
-/**
-  * @}
-  */ 
-
-/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
-  * @{
-  */ 
-#define UART_HWCONTROL_NONE                  ((uint32_t)0x00000000U)
-#define UART_HWCONTROL_RTS                   ((uint32_t)USART_CR3_RTSE)
-#define UART_HWCONTROL_CTS                   ((uint32_t)USART_CR3_CTSE)
-#define UART_HWCONTROL_RTS_CTS               ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
-/**
-  * @}
-  */
-
-/** @defgroup UART_Mode UART Transfer Mode
-  * @{
-  */ 
-#define UART_MODE_RX                        ((uint32_t)USART_CR1_RE)
-#define UART_MODE_TX                        ((uint32_t)USART_CR1_TE)
-#define UART_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
-/**
-  * @}
-  */
-    
- /** @defgroup UART_State UART State
-  * @{
-  */ 
-#define UART_STATE_DISABLE                  ((uint32_t)0x00000000U)
-#define UART_STATE_ENABLE                   ((uint32_t)USART_CR1_UE)
-/**
-  * @}
-  */
-
-/** @defgroup UART_Over_Sampling UART Over Sampling
-  * @{
-  */
-#define UART_OVERSAMPLING_16                    ((uint32_t)0x00000000U)
-#define UART_OVERSAMPLING_8                     ((uint32_t)USART_CR1_OVER8)
-/**
-  * @}
-  */
-
-/** @defgroup UART_LIN_Break_Detection_Length  UART LIN Break Detection Length
-  * @{
-  */  
-#define UART_LINBREAKDETECTLENGTH_10B      ((uint32_t)0x00000000U)
-#define UART_LINBREAKDETECTLENGTH_11B      ((uint32_t)0x00000020U)
-/**
-  * @}
-  */
-                                         
-/** @defgroup UART_WakeUp_functions  UART Wakeup Functions
-  * @{
-  */
-#define UART_WAKEUPMETHOD_IDLELINE                ((uint32_t)0x00000000U)
-#define UART_WAKEUPMETHOD_ADDRESSMARK             ((uint32_t)0x00000800U)
-/**
-  * @}
-  */
-
-/** @defgroup UART_Flags   UART FLags
-  *        Elements values convention: 0xXXXX
-  *           - 0xXXXX  : Flag mask in the SR register
-  * @{
-  */
-#define UART_FLAG_CTS                       ((uint32_t)USART_SR_CTS)
-#define UART_FLAG_LBD                       ((uint32_t)USART_SR_LBD)
-#define UART_FLAG_TXE                       ((uint32_t)USART_SR_TXE)
-#define UART_FLAG_TC                        ((uint32_t)USART_SR_TC)
-#define UART_FLAG_RXNE                      ((uint32_t)USART_SR_RXNE)
-#define UART_FLAG_IDLE                      ((uint32_t)USART_SR_IDLE)
-#define UART_FLAG_ORE                       ((uint32_t)USART_SR_ORE)
-#define UART_FLAG_NE                        ((uint32_t)USART_SR_NE)
-#define UART_FLAG_FE                        ((uint32_t)USART_SR_FE)
-#define UART_FLAG_PE                        ((uint32_t)USART_SR_PE)
-/**
-  * @}
-  */
-
-/** @defgroup UART_Interrupt_definition  UART Interrupt Definitions
-  *        Elements values convention: 0xY000XXXX
-  *           - XXXX  : Interrupt mask (16 bits) in the Y register
-  *           - Y  : Interrupt source register (2bits)
-  *                 - 0001: CR1 register
-  *                 - 0010: CR2 register
-  *                 - 0011: CR3 register
-  *
-  * @{
-  */ 
-
-#define UART_IT_PE                       ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
-#define UART_IT_TXE                      ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
-#define UART_IT_TC                       ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
-#define UART_IT_RXNE                     ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
-#define UART_IT_IDLE                     ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
-
-#define UART_IT_LBD                      ((uint32_t)(UART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
-
-#define UART_IT_CTS                      ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
-#define UART_IT_ERR                      ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_EIE))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup UART_Exported_Macros UART Exported Macros
-  * @{
-  */
-
-/** @brief Reset UART handle gstate & RxState
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
-  * @retval None
-  */
-#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
-                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
-                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
-                                                     } while(0)
-
-/** @brief  Flushes the UART DR register 
-  * @param  __HANDLE__: specifies the UART Handle.
-  */
-#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
-
-/** @brief  Checks whether the specified UART flag is set or not.
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
-  * @param  __FLAG__: specifies the flag to check.
-  *        This parameter can be one of the following values:
-  *            @arg UART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5)
-  *            @arg UART_FLAG_LBD:  LIN Break detection flag
-  *            @arg UART_FLAG_TXE:  Transmit data register empty flag
-  *            @arg UART_FLAG_TC:   Transmission Complete flag
-  *            @arg UART_FLAG_RXNE: Receive data register not empty flag
-  *            @arg UART_FLAG_IDLE: Idle Line detection flag
-  *            @arg UART_FLAG_ORE:  Overrun Error flag
-  *            @arg UART_FLAG_NE:   Noise Error flag
-  *            @arg UART_FLAG_FE:   Framing Error flag
-  *            @arg UART_FLAG_PE:   Parity Error flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-
-#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))   
-     
-/** @brief  Clears the specified UART pending flag.
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
-  * @param  __FLAG__: specifies the flag to check.
-  *          This parameter can be any combination of the following values:
-  *            @arg UART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5).
-  *            @arg UART_FLAG_LBD:  LIN Break detection flag.
-  *            @arg UART_FLAG_TC:   Transmission Complete flag.
-  *            @arg UART_FLAG_RXNE: Receive data register not empty flag.
-  *   
-  * @note   PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun 
-  *          error) and IDLE (Idle line detected) flags are cleared by software 
-  *          sequence: a read operation to USART_SR register followed by a read
-  *          operation to USART_DR register.
-  * @note   RXNE flag can be also cleared by a read to the USART_DR register.
-  * @note   TC flag can be also cleared by software sequence: a read operation to 
-  *          USART_SR register followed by a write operation to USART_DR register.
-  * @note   TXE flag is cleared only by a write to the USART_DR register.
-  *   
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-
-/** @brief  Clear the UART PE pending flag.
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__)     \
-  do{                                           \
-    __IO uint32_t tmpreg = 0x00U;                \
-    tmpreg = (__HANDLE__)->Instance->SR;        \
-    tmpreg = (__HANDLE__)->Instance->DR;        \
-    UNUSED(tmpreg);                             \
-  } while(0)
-                                              
-/** @brief  Clear the UART FE pending flag.
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Clear the UART NE pending flag.
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Clear the UART ORE pending flag.
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Clear the UART IDLE pending flag.
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
-                                                 
-/** @brief  Enable the specified UART interrupt.
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
-  * @param  __INTERRUPT__: specifies the UART interrupt source to enable.
-  *          This parameter can be one of the following values:
-  *            @arg UART_IT_CTS:  CTS change interrupt
-  *            @arg UART_IT_LBD:  LIN Break detection interrupt
-  *            @arg UART_IT_TXE:  Transmit Data Register empty interrupt
-  *            @arg UART_IT_TC:   Transmission complete interrupt
-  *            @arg UART_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg UART_IT_IDLE: Idle line detection interrupt
-  *            @arg UART_IT_PE:   Parity Error interrupt
-  *            @arg UART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
-  * @retval None
-  */
-#define UART_IT_MASK  ((uint32_t)0x0000FFFFU)
-#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \
-                                                           (((__INTERRUPT__) >> 28U) == 2U)? ((__HANDLE__)->Instance->CR2 |=  ((__INTERRUPT__) & UART_IT_MASK)): \
-                                                        ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK)))
-/** @brief  Disable the specified UART interrupt.
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
-  * @param  __INTERRUPT__: specifies the UART interrupt source to disable.
-  *          This parameter can be one of the following values:
-  *            @arg UART_IT_CTS:  CTS change interrupt
-  *            @arg UART_IT_LBD:  LIN Break detection interrupt
-  *            @arg UART_IT_TXE:  Transmit Data Register empty interrupt
-  *            @arg UART_IT_TC:   Transmission complete interrupt
-  *            @arg UART_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg UART_IT_IDLE: Idle line detection interrupt
-  *            @arg UART_IT_PE:   Parity Error interrupt
-  *            @arg UART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
-  * @retval None
-  */
-#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
-                                                           (((__INTERRUPT__) >> 28U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
-                                                        ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK)))
-
-/** @brief  Checks whether the specified UART interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
-  * @param  __IT__: specifies the UART interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
-  *            @arg UART_IT_LBD: LIN Break detection interrupt
-  *            @arg UART_IT_TXE: Transmit Data Register empty interrupt
-  *            @arg UART_IT_TC:  Transmission complete interrupt
-  *            @arg UART_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg UART_IT_IDLE: Idle line detection interrupt
-  *            @arg USART_IT_ERR: Error interrupt
-  * @retval The new state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == 2U)? \
-                                                      (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK))
-
-/** @brief  Enable CTS flow control 
-  *         This macro allows to enable CTS hardware flow control for a given UART instance, 
-  *         without need to call HAL_UART_Init() function.
-  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
-  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
-  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
-  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
-  *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
-  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).                                                                                                                  
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         The Handle Instance can be USART1, USART2 or LPUART.
-  * @retval None
-  */
-#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)        \
-  do{                                                      \
-    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \
-    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;        \
-  } while(0)
-
-/** @brief  Disable CTS flow control 
-  *         This macro allows to disable CTS hardware flow control for a given UART instance, 
-  *         without need to call HAL_UART_Init() function.
-  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
-  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
-  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
-  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
-  *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
-  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). 
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         The Handle Instance can be USART1, USART2 or LPUART.
-  * @retval None
-  */
-#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)        \
-  do{                                                       \
-    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
-    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);      \
-  } while(0)
-
-/** @brief  Enable RTS flow control 
-  *         This macro allows to enable RTS hardware flow control for a given UART instance, 
-  *         without need to call HAL_UART_Init() function.
-  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
-  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
-  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
-  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
-  *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
-  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). 
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         The Handle Instance can be USART1, USART2 or LPUART.
-  * @retval None
-  */
-#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)       \
-  do{                                                     \
-    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
-    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;       \
-  } while(0)
-
-/** @brief  Disable RTS flow control 
-  *         This macro allows to disable RTS hardware flow control for a given UART instance, 
-  *         without need to call HAL_UART_Init() function.
-  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
-  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
-  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
-  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
-  *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
-  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). 
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         The Handle Instance can be USART1, USART2 or LPUART.
-  * @retval None
-  */
-#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)       \
-  do{                                                      \
-    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
-    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);     \
-  } while(0)
-
-/** @brief  macros to enables the UART's one bit sample method
-  * @param  __HANDLE__: specifies the UART Handle.  
-  * @retval None
-  */     
-#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
-
-/** @brief  macros to disables the UART's one bit sample method
-  * @param  __HANDLE__: specifies the UART Handle.  
-  * @retval None
-  */      
-#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
-
-/** @brief  Enable UART
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @retval None
-  */    
-#define __HAL_UART_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
-
-/** @brief  Disable UART
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @retval None
-  */    
-#define __HAL_UART_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
-/**
-  * @}
-  */
-    
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup UART_Exported_Functions
-  * @{
-  */
-  
-/** @addtogroup UART_Exported_Functions_Group1
-  * @{
-  */    
-/* Initialization/de-initialization functions  **********************************/
-HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
-HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
-HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);
-void HAL_UART_MspInit(UART_HandleTypeDef *huart);
-void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
-/**
-  * @}
-  */
-
-/** @addtogroup UART_Exported_Functions_Group2
-  * @{
-  */
-/* IO operation functions *******************************************************/
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
-
-void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
-void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
-/**
-  * @}
-  */
-
-/** @addtogroup UART_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral Control functions  ************************************************/
-HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
-/**
-  * @}
-  */
-
-/** @addtogroup UART_Exported_Functions_Group4
-  * @{
-  */
-/* Peripheral State functions  **************************************************/
-HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
-uint32_t              HAL_UART_GetError(UART_HandleTypeDef *huart);
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup UART_Private_Constants UART Private Constants
-  * @{
-  */
-/** @brief UART interruptions flag mask
-  * 
-  */ 
-#define UART_CR1_REG_INDEX               1U
-#define UART_CR2_REG_INDEX               2U
-#define UART_CR3_REG_INDEX               3U
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup UART_Private_Macros UART Private Macros
-  * @{
-  */
-#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \
-                                     ((LENGTH) == UART_WORDLENGTH_9B))
-#define IS_UART_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B))
-#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \
-                                    ((STOPBITS) == UART_STOPBITS_2))
-#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \
-                                ((PARITY) == UART_PARITY_EVEN) || \
-                                ((PARITY) == UART_PARITY_ODD))
-#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
-                              (((CONTROL) == UART_HWCONTROL_NONE) || \
-                               ((CONTROL) == UART_HWCONTROL_RTS) || \
-                               ((CONTROL) == UART_HWCONTROL_CTS) || \
-                               ((CONTROL) == UART_HWCONTROL_RTS_CTS))
-#define IS_UART_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3U) == 0x00U) && ((MODE) != (uint32_t)0x00U))
-#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \
-                              ((STATE) == UART_STATE_ENABLE))
-#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \
-                                        ((SAMPLING) == UART_OVERSAMPLING_8))
-#define IS_UART_LIN_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16))
-#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \
-                                                 ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))
-#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \
-                                      ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK))
-#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001U)
-#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0x0FU)
-
-#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_)            (((_PCLK_)*25U)/(4U*(_BAUD_)))
-#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_)        (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U)
-#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_)        (((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
-/* UART BRR = mantissa + overflow + fraction
-            = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */
-#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_)            (((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4U) + \
-                                                        (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0U)) + \
-                                                        (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0FU))
-
-#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_)             (((_PCLK_)*25U)/(2U*(_BAUD_)))
-#define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_)         (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U)
-#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_)         (((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U + 50U) / 100U)
-/* UART BRR = mantissa + overflow + fraction
-            = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */
-#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_)             (((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4U) + \
-                                                        ((UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0xF8U) << 1U)) + \
-                                                        (UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x07U))
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup UART_Private_Functions UART Private Functions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_UART_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/inc/stm32f4xx_ll_sdmmc.h b/stmhal/hal/f4/inc/stm32f4xx_ll_sdmmc.h
deleted file mode 100644
index 8f2477462f..0000000000
--- a/stmhal/hal/f4/inc/stm32f4xx_ll_sdmmc.h
+++ /dev/null
@@ -1,919 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_ll_sdmmc.h
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   Header file of SDMMC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_LL_SDMMC_H
-#define __STM32F4xx_LL_SDMMC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
-    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
-    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
-    defined(STM32F412Rx) || defined(STM32F412Cx)
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/** @addtogroup STM32F4xx_Driver
-  * @{
-  */
-
-/** @addtogroup SDMMC_LL
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
-  * @{
-  */
-  
-/** 
-  * @brief  SDMMC Configuration Structure definition  
-  */
-typedef struct
-{
-  uint32_t ClockEdge;            /*!< Specifies the clock transition on which the bit capture is made.
-                                      This parameter can be a value of @ref SDIO_Clock_Edge                 */
-
-  uint32_t ClockBypass;          /*!< Specifies whether the SDIO Clock divider bypass is
-                                      enabled or disabled.
-                                      This parameter can be a value of @ref SDIO_Clock_Bypass               */
-
-  uint32_t ClockPowerSave;       /*!< Specifies whether SDIO Clock output is enabled or
-                                      disabled when the bus is idle.
-                                      This parameter can be a value of @ref SDIO_Clock_Power_Save           */
-
-  uint32_t BusWide;              /*!< Specifies the SDIO bus width.
-                                      This parameter can be a value of @ref SDIO_Bus_Wide                   */
-
-  uint32_t HardwareFlowControl;  /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
-                                      This parameter can be a value of @ref SDIO_Hardware_Flow_Control      */
-
-  uint32_t ClockDiv;             /*!< Specifies the clock frequency of the SDIO controller.
-                                      This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
-  
-}SDIO_InitTypeDef;
-  
-
-/** 
-  * @brief  SDIO Command Control structure 
-  */
-typedef struct
-{
-  uint32_t Argument;            /*!< Specifies the SDIO command argument which is sent
-                                     to a card as part of a command message. If a command
-                                     contains an argument, it must be loaded into this register
-                                     before writing the command to the command register.              */
-
-  uint32_t CmdIndex;            /*!< Specifies the SDIO command index. It must be Min_Data = 0 and 
-                                     Max_Data = 64                                                    */
-
-  uint32_t Response;            /*!< Specifies the SDIO response type.
-                                     This parameter can be a value of @ref SDIO_Response_Type         */
-
-  uint32_t WaitForInterrupt;    /*!< Specifies whether SDIO wait for interrupt request is 
-                                     enabled or disabled.
-                                     This parameter can be a value of @ref SDIO_Wait_Interrupt_State  */
-
-  uint32_t CPSM;                /*!< Specifies whether SDIO Command path state machine (CPSM)
-                                     is enabled or disabled.
-                                     This parameter can be a value of @ref SDIO_CPSM_State            */
-}SDIO_CmdInitTypeDef;
-
-
-/** 
-  * @brief  SDIO Data Control structure 
-  */
-typedef struct
-{
-  uint32_t DataTimeOut;         /*!< Specifies the data timeout period in card bus clock periods.  */
-
-  uint32_t DataLength;          /*!< Specifies the number of data bytes to be transferred.         */
- 
-  uint32_t DataBlockSize;       /*!< Specifies the data block size for block transfer.
-                                     This parameter can be a value of @ref SDIO_Data_Block_Size    */
- 
-  uint32_t TransferDir;         /*!< Specifies the data transfer direction, whether the transfer
-                                     is a read or write.
-                                     This parameter can be a value of @ref SDIO_Transfer_Direction */
- 
-  uint32_t TransferMode;        /*!< Specifies whether data transfer is in stream or block mode.
-                                     This parameter can be a value of @ref SDIO_Transfer_Type      */
- 
-  uint32_t DPSM;                /*!< Specifies whether SDIO Data path state machine (DPSM)
-                                     is enabled or disabled.
-                                     This parameter can be a value of @ref SDIO_DPSM_State         */
-}SDIO_DataInitTypeDef;
-
-/**
-  * @}
-  */
-  
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
-  * @{
-  */
-
-/** @defgroup SDIO_Clock_Edge Clock Edge
-  * @{
-  */
-#define SDIO_CLOCK_EDGE_RISING               ((uint32_t)0x00000000U)
-#define SDIO_CLOCK_EDGE_FALLING              SDIO_CLKCR_NEGEDGE
-
-#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \
-                                  ((EDGE) == SDIO_CLOCK_EDGE_FALLING))
-/**
-  * @}
-  */
-
-/** @defgroup SDIO_Clock_Bypass Clock Bypass
-  * @{
-  */
-#define SDIO_CLOCK_BYPASS_DISABLE             ((uint32_t)0x00000000U)
-#define SDIO_CLOCK_BYPASS_ENABLE              SDIO_CLKCR_BYPASS   
-
-#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \
-                                      ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
-/**
-  * @}
-  */ 
-
-/** @defgroup SDIO_Clock_Power_Save Clock Power Saving
-  * @{
-  */
-#define SDIO_CLOCK_POWER_SAVE_DISABLE         ((uint32_t)0x00000000U)
-#define SDIO_CLOCK_POWER_SAVE_ENABLE          SDIO_CLKCR_PWRSAV
-
-#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \
-                                        ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
-/**
-  * @}
-  */
-
-/** @defgroup SDIO_Bus_Wide Bus Width
-  * @{
-  */
-#define SDIO_BUS_WIDE_1B                      ((uint32_t)0x00000000U)
-#define SDIO_BUS_WIDE_4B                      SDIO_CLKCR_WIDBUS_0
-#define SDIO_BUS_WIDE_8B                      SDIO_CLKCR_WIDBUS_1
-
-#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \
-                                ((WIDE) == SDIO_BUS_WIDE_4B) || \
-                                ((WIDE) == SDIO_BUS_WIDE_8B))
-/**
-  * @}
-  */
-
-/** @defgroup SDIO_Hardware_Flow_Control Hardware Flow Control
-  * @{
-  */
-#define SDIO_HARDWARE_FLOW_CONTROL_DISABLE    ((uint32_t)0x00000000U)
-#define SDIO_HARDWARE_FLOW_CONTROL_ENABLE     SDIO_CLKCR_HWFC_EN
-
-#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \
-                                                ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
-/**
-  * @}
-  */
-  
-/** @defgroup SDIO_Clock_Division Clock Division
-  * @{
-  */
-#define IS_SDIO_CLKDIV(DIV)   ((DIV) <= 0xFFU)
-/**
-  * @}
-  */  
-    
-/** @defgroup SDIO_Command_Index Command Index
-  * @{
-  */
-#define IS_SDIO_CMD_INDEX(INDEX)            ((INDEX) < 0x40U)
-/**
-  * @}
-  */
-
-/** @defgroup SDIO_Response_Type Response Type
-  * @{
-  */
-#define SDIO_RESPONSE_NO                    ((uint32_t)0x00000000U)
-#define SDIO_RESPONSE_SHORT                 SDIO_CMD_WAITRESP_0
-#define SDIO_RESPONSE_LONG                  SDIO_CMD_WAITRESP
-
-#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO)    || \
-                                    ((RESPONSE) == SDIO_RESPONSE_SHORT) || \
-                                    ((RESPONSE) == SDIO_RESPONSE_LONG))
-/**
-  * @}
-  */
-
-/** @defgroup SDIO_Wait_Interrupt_State Wait Interrupt
-  * @{
-  */
-#define SDIO_WAIT_NO                        ((uint32_t)0x00000000U)
-#define SDIO_WAIT_IT                        SDIO_CMD_WAITINT 
-#define SDIO_WAIT_PEND                      SDIO_CMD_WAITPEND
-
-#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \
-                            ((WAIT) == SDIO_WAIT_IT) || \
-                            ((WAIT) == SDIO_WAIT_PEND))
-/**
-  * @}
-  */
-
-/** @defgroup SDIO_CPSM_State CPSM State
-  * @{
-  */
-#define SDIO_CPSM_DISABLE                   ((uint32_t)0x00000000U)
-#define SDIO_CPSM_ENABLE                    SDIO_CMD_CPSMEN
-
-#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \
-                            ((CPSM) == SDIO_CPSM_ENABLE))
-/**
-  * @}
-  */  
-
-/** @defgroup SDIO_Response_Registers Response Register
-  * @{
-  */
-#define SDIO_RESP1                          ((uint32_t)0x00000000U)
-#define SDIO_RESP2                          ((uint32_t)0x00000004U)
-#define SDIO_RESP3                          ((uint32_t)0x00000008U)
-#define SDIO_RESP4                          ((uint32_t)0x0000000CU)
-
-#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \
-                            ((RESP) == SDIO_RESP2) || \
-                            ((RESP) == SDIO_RESP3) || \
-                            ((RESP) == SDIO_RESP4))
-/**
-  * @}
-  */
-
-/** @defgroup SDIO_Data_Length Data Lenght
-  * @{
-  */
-#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)
-/**
-  * @}
-  */
-
-/** @defgroup SDIO_Data_Block_Size Data Block Size
-  * @{
-  */
-#define SDIO_DATABLOCK_SIZE_1B               ((uint32_t)0x00000000U)
-#define SDIO_DATABLOCK_SIZE_2B               SDIO_DCTRL_DBLOCKSIZE_0
-#define SDIO_DATABLOCK_SIZE_4B               SDIO_DCTRL_DBLOCKSIZE_1
-#define SDIO_DATABLOCK_SIZE_8B               ((uint32_t)0x00000030U)
-#define SDIO_DATABLOCK_SIZE_16B              SDIO_DCTRL_DBLOCKSIZE_2
-#define SDIO_DATABLOCK_SIZE_32B              ((uint32_t)0x00000050U)
-#define SDIO_DATABLOCK_SIZE_64B              ((uint32_t)0x00000060U)
-#define SDIO_DATABLOCK_SIZE_128B             ((uint32_t)0x00000070U)
-#define SDIO_DATABLOCK_SIZE_256B             SDIO_DCTRL_DBLOCKSIZE_3
-#define SDIO_DATABLOCK_SIZE_512B             ((uint32_t)0x00000090U)
-#define SDIO_DATABLOCK_SIZE_1024B            ((uint32_t)0x000000A0U)
-#define SDIO_DATABLOCK_SIZE_2048B            ((uint32_t)0x000000B0U)
-#define SDIO_DATABLOCK_SIZE_4096B            ((uint32_t)0x000000C0U)
-#define SDIO_DATABLOCK_SIZE_8192B            ((uint32_t)0x000000D0U)
-#define SDIO_DATABLOCK_SIZE_16384B           ((uint32_t)0x000000E0U)
-
-#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B)    || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_2B)    || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_4B)    || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_8B)    || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_16B)   || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_32B)   || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_64B)   || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_128B)  || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_256B)  || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_512B)  || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_16384B)) 
-/**
-  * @}
-  */
-
-/** @defgroup SDIO_Transfer_Direction Transfer Direction
-  * @{
-  */
-#define SDIO_TRANSFER_DIR_TO_CARD            ((uint32_t)0x00000000U)
-#define SDIO_TRANSFER_DIR_TO_SDIO            SDIO_DCTRL_DTDIR
-
-#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \
-                                   ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
-/**
-  * @}
-  */
-
-/** @defgroup SDIO_Transfer_Type Transfer Type
-  * @{
-  */
-#define SDIO_TRANSFER_MODE_BLOCK             ((uint32_t)0x00000000U)
-#define SDIO_TRANSFER_MODE_STREAM            SDIO_DCTRL_DTMODE
-
-#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \
-                                     ((MODE) == SDIO_TRANSFER_MODE_STREAM))
-/**
-  * @}
-  */
-
-/** @defgroup SDIO_DPSM_State DPSM State
-  * @{
-  */
-#define SDIO_DPSM_DISABLE                    ((uint32_t)0x00000000U)
-#define SDIO_DPSM_ENABLE                     SDIO_DCTRL_DTEN
-
-#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\
-                            ((DPSM) == SDIO_DPSM_ENABLE))
-/**
-  * @}
-  */
-  
-/** @defgroup SDIO_Read_Wait_Mode Read Wait Mode
-  * @{
-  */
-#define SDIO_READ_WAIT_MODE_DATA2             ((uint32_t)0x00000000U)
-#define SDIO_READ_WAIT_MODE_CLK               ((uint32_t)0x00000001U)
-
-#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
-                                     ((MODE) == SDIO_READ_WAIT_MODE_DATA2))
-/**
-  * @}
-  */  
-
-/** @defgroup SDIO_Interrupt_sources Interrupt Sources
-  * @{
-  */
-#define SDIO_IT_CCRCFAIL                    SDIO_STA_CCRCFAIL
-#define SDIO_IT_DCRCFAIL                    SDIO_STA_DCRCFAIL
-#define SDIO_IT_CTIMEOUT                    SDIO_STA_CTIMEOUT
-#define SDIO_IT_DTIMEOUT                    SDIO_STA_DTIMEOUT
-#define SDIO_IT_TXUNDERR                    SDIO_STA_TXUNDERR
-#define SDIO_IT_RXOVERR                     SDIO_STA_RXOVERR
-#define SDIO_IT_CMDREND                     SDIO_STA_CMDREND
-#define SDIO_IT_CMDSENT                     SDIO_STA_CMDSENT
-#define SDIO_IT_DATAEND                     SDIO_STA_DATAEND
-#define SDIO_IT_STBITERR                    SDIO_STA_STBITERR
-#define SDIO_IT_DBCKEND                     SDIO_STA_DBCKEND
-#define SDIO_IT_CMDACT                      SDIO_STA_CMDACT
-#define SDIO_IT_TXACT                       SDIO_STA_TXACT
-#define SDIO_IT_RXACT                       SDIO_STA_RXACT
-#define SDIO_IT_TXFIFOHE                    SDIO_STA_TXFIFOHE
-#define SDIO_IT_RXFIFOHF                    SDIO_STA_RXFIFOHF
-#define SDIO_IT_TXFIFOF                     SDIO_STA_TXFIFOF
-#define SDIO_IT_RXFIFOF                     SDIO_STA_RXFIFOF
-#define SDIO_IT_TXFIFOE                     SDIO_STA_TXFIFOE
-#define SDIO_IT_RXFIFOE                     SDIO_STA_RXFIFOE
-#define SDIO_IT_TXDAVL                      SDIO_STA_TXDAVL
-#define SDIO_IT_RXDAVL                      SDIO_STA_RXDAVL
-#define SDIO_IT_SDIOIT                      SDIO_STA_SDIOIT
-#define SDIO_IT_CEATAEND                    SDIO_STA_CEATAEND
-/**
-  * @}
-  */ 
-
-/** @defgroup SDIO_Flags Flags
-  * @{
-  */
-#define SDIO_FLAG_CCRCFAIL                  SDIO_STA_CCRCFAIL
-#define SDIO_FLAG_DCRCFAIL                  SDIO_STA_DCRCFAIL
-#define SDIO_FLAG_CTIMEOUT                  SDIO_STA_CTIMEOUT
-#define SDIO_FLAG_DTIMEOUT                  SDIO_STA_DTIMEOUT
-#define SDIO_FLAG_TXUNDERR                  SDIO_STA_TXUNDERR
-#define SDIO_FLAG_RXOVERR                   SDIO_STA_RXOVERR
-#define SDIO_FLAG_CMDREND                   SDIO_STA_CMDREND
-#define SDIO_FLAG_CMDSENT                   SDIO_STA_CMDSENT
-#define SDIO_FLAG_DATAEND                   SDIO_STA_DATAEND
-#define SDIO_FLAG_STBITERR                  SDIO_STA_STBITERR
-#define SDIO_FLAG_DBCKEND                   SDIO_STA_DBCKEND
-#define SDIO_FLAG_CMDACT                    SDIO_STA_CMDACT
-#define SDIO_FLAG_TXACT                     SDIO_STA_TXACT
-#define SDIO_FLAG_RXACT                     SDIO_STA_RXACT
-#define SDIO_FLAG_TXFIFOHE                  SDIO_STA_TXFIFOHE
-#define SDIO_FLAG_RXFIFOHF                  SDIO_STA_RXFIFOHF
-#define SDIO_FLAG_TXFIFOF                   SDIO_STA_TXFIFOF
-#define SDIO_FLAG_RXFIFOF                   SDIO_STA_RXFIFOF
-#define SDIO_FLAG_TXFIFOE                   SDIO_STA_TXFIFOE
-#define SDIO_FLAG_RXFIFOE                   SDIO_STA_RXFIFOE
-#define SDIO_FLAG_TXDAVL                    SDIO_STA_TXDAVL
-#define SDIO_FLAG_RXDAVL                    SDIO_STA_RXDAVL
-#define SDIO_FLAG_SDIOIT                    SDIO_STA_SDIOIT
-#define SDIO_FLAG_CEATAEND                  SDIO_STA_CEATAEND
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
-  * @{
-  */
-
-/** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region
-  * @{
-  */
-/* ------------ SDIO registers bit address in the alias region -------------- */
-#define SDIO_OFFSET               (SDIO_BASE - PERIPH_BASE)
-
-/* --- CLKCR Register ---*/
-/* Alias word address of CLKEN bit */
-#define CLKCR_OFFSET              (SDIO_OFFSET + 0x04U)
-#define CLKEN_BITNUMBER           0x08U
-#define CLKCR_CLKEN_BB            (PERIPH_BB_BASE + (CLKCR_OFFSET * 32U) + (CLKEN_BITNUMBER * 4U))
-
-/* --- CMD Register ---*/
-/* Alias word address of SDIOSUSPEND bit */
-#define CMD_OFFSET                (SDIO_OFFSET + 0x0CU)
-#define SDIOSUSPEND_BITNUMBER     0x0BU
-#define CMD_SDIOSUSPEND_BB        (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (SDIOSUSPEND_BITNUMBER * 4U))
-
-/* Alias word address of ENCMDCOMPL bit */
-#define ENCMDCOMPL_BITNUMBER      0x0CU
-#define CMD_ENCMDCOMPL_BB         (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ENCMDCOMPL_BITNUMBER * 4U))
-
-/* Alias word address of NIEN bit */
-#define NIEN_BITNUMBER            0x0DU
-#define CMD_NIEN_BB               (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (NIEN_BITNUMBER * 4U))
-
-/* Alias word address of ATACMD bit */
-#define ATACMD_BITNUMBER          0x0EU
-#define CMD_ATACMD_BB             (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ATACMD_BITNUMBER * 4U))
-
-/* --- DCTRL Register ---*/
-/* Alias word address of DMAEN bit */
-#define DCTRL_OFFSET              (SDIO_OFFSET + 0x2CU)
-#define DMAEN_BITNUMBER           0x03U
-#define DCTRL_DMAEN_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (DMAEN_BITNUMBER * 4U))
-
-/* Alias word address of RWSTART bit */
-#define RWSTART_BITNUMBER         0x08U
-#define DCTRL_RWSTART_BB          (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTART_BITNUMBER * 4U))
-
-/* Alias word address of RWSTOP bit */
-#define RWSTOP_BITNUMBER          0x09U
-#define DCTRL_RWSTOP_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTOP_BITNUMBER * 4U))
-
-/* Alias word address of RWMOD bit */
-#define RWMOD_BITNUMBER           0x0AU
-#define DCTRL_RWMOD_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWMOD_BITNUMBER * 4U))
-
-/* Alias word address of SDIOEN bit */
-#define SDIOEN_BITNUMBER          0x0BU
-#define DCTRL_SDIOEN_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (SDIOEN_BITNUMBER * 4U))
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
-  * @brief SDMMC_LL registers bit address in the alias region
-  * @{
-  */
-
-/* ---------------------- SDIO registers bit mask --------------------------- */
-/* --- CLKCR Register ---*/
-/* CLKCR register clear mask */ 
-#define CLKCR_CLEAR_MASK         ((uint32_t)(SDIO_CLKCR_CLKDIV  | SDIO_CLKCR_PWRSAV |\
-                                             SDIO_CLKCR_BYPASS  | SDIO_CLKCR_WIDBUS |\
-                                             SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN))
-
-/* --- PWRCTRL Register ---*/
-/* --- DCTRL Register ---*/
-/* SDIO DCTRL Clear Mask */
-#define DCTRL_CLEAR_MASK         ((uint32_t)(SDIO_DCTRL_DTEN    | SDIO_DCTRL_DTDIR |\
-                                             SDIO_DCTRL_DTMODE  | SDIO_DCTRL_DBLOCKSIZE))
-
-/* --- CMD Register ---*/
-/* CMD Register clear mask */
-#define CMD_CLEAR_MASK           ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\
-                                             SDIO_CMD_WAITINT  | SDIO_CMD_WAITPEND |\
-                                             SDIO_CMD_CPSMEN   | SDIO_CMD_SDIOSUSPEND))
-
-/* SDIO RESP Registers Address */
-#define SDIO_RESP_ADDR           ((uint32_t)(SDIO_BASE + 0x14U))
-
-/* SDIO Initialization Frequency (400KHz max) */
-#define SDIO_INIT_CLK_DIV ((uint8_t)0x76U)
-
-/* SDIO Data Transfer Frequency (25MHz max) */
-#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x00U)
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
-  * @brief macros to handle interrupts and specific clock configurations
-  * @{
-  */
-
-/**
-  * @brief  Enable the SDIO device.
-  * @retval None
-  */ 
-#define __SDIO_ENABLE()   (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)
-
-/**
-  * @brief  Disable the SDIO device.
-  * @retval None
-  */
-#define __SDIO_DISABLE()   (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)
-
-/**
-  * @brief  Enable the SDIO DMA transfer.
-  * @retval None
-  */ 
-#define __SDIO_DMA_ENABLE()   (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)
-
-/**
-  * @brief  Disable the SDIO DMA transfer.
-  * @retval None
-  */
-#define __SDIO_DMA_DISABLE()   (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)
- 
-/**
-  * @brief  Enable the SDIO device interrupt.
-  * @param  __INSTANCE__ : Pointer to SDIO register base  
-  * @param  __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled.
-  *         This parameter can be one or a combination of the following values:
-  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
-  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
-  *                                   bus mode interrupt
-  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
-  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
-  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
-  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
-  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
-  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
-  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
-  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
-  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
-  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
-  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
-  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt     
-  * @retval None
-  */
-#define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the SDIO device interrupt.
-  * @param  __INSTANCE__ : Pointer to SDIO register base   
-  * @param  __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled.
-  *          This parameter can be one or a combination of the following values:
-  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
-  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
-  *                                   bus mode interrupt
-  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
-  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
-  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
-  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
-  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
-  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
-  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
-  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
-  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
-  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
-  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
-  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt     
-  * @retval None
-  */
-#define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
-
-/**
-  * @brief  Checks whether the specified SDIO flag is set or not. 
-  * @param  __INSTANCE__ : Pointer to SDIO register base   
-  * @param  __FLAG__: specifies the flag to check. 
-  *          This parameter can be one of the following values:
-  *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
-  *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
-  *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout
-  *            @arg SDIO_FLAG_DTIMEOUT: Data timeout
-  *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
-  *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
-  *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
-  *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
-  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
-  *            @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
-  *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
-  *            @arg SDIO_FLAG_CMDACT:   Command transfer in progress
-  *            @arg SDIO_FLAG_TXACT:    Data transmit in progress
-  *            @arg SDIO_FLAG_RXACT:    Data receive in progress
-  *            @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
-  *            @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
-  *            @arg SDIO_FLAG_TXFIFOF:  Transmit FIFO full
-  *            @arg SDIO_FLAG_RXFIFOF:  Receive FIFO full
-  *            @arg SDIO_FLAG_TXFIFOE:  Transmit FIFO empty
-  *            @arg SDIO_FLAG_RXFIFOE:  Receive FIFO empty
-  *            @arg SDIO_FLAG_TXDAVL:   Data available in transmit FIFO
-  *            @arg SDIO_FLAG_RXDAVL:   Data available in receive FIFO
-  *            @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
-  *            @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
-  * @retval The new state of SDIO_FLAG (SET or RESET).
-  */
-#define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__)   (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
-
-
-/**
-  * @brief  Clears the SDIO pending flags.
-  * @param  __INSTANCE__ : Pointer to SDIO register base  
-  * @param  __FLAG__: specifies the flag to clear.  
-  *          This parameter can be one or a combination of the following values:
-  *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
-  *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
-  *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout
-  *            @arg SDIO_FLAG_DTIMEOUT: Data timeout
-  *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
-  *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
-  *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
-  *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
-  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
-  *            @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
-  *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
-  *            @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
-  *            @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
-  * @retval None
-  */
-#define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__)   ((__INSTANCE__)->ICR = (__FLAG__))
-
-/**
-  * @brief  Checks whether the specified SDIO interrupt has occurred or not.
-  * @param  __INSTANCE__ : Pointer to SDIO register base   
-  * @param  __INTERRUPT__: specifies the SDIO interrupt source to check. 
-  *          This parameter can be one of the following values:
-  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
-  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
-  *                                   bus mode interrupt
-  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
-  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
-  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
-  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
-  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
-  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
-  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
-  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
-  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
-  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
-  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
-  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
-  * @retval The new state of SDIO_IT (SET or RESET).
-  */
-#define __SDIO_GET_IT  (__INSTANCE__, __INTERRUPT__)   (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
-
-/**
-  * @brief  Clears the SDIO's interrupt pending bits.
-  * @param  __INSTANCE__ : Pointer to SDIO register base 
-  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. 
-  *          This parameter can be one or a combination of the following values:
-  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIO_DCOUNT, is zero) interrupt
-  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
-  *                                   bus mode interrupt
-  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
-  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
-  * @retval None
-  */
-#define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__)   ((__INSTANCE__)->ICR = (__INTERRUPT__))
-
-/**
-  * @brief  Enable Start the SD I/O Read Wait operation.
-  * @retval None
-  */  
-#define __SDIO_START_READWAIT_ENABLE()   (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)
-
-/**
-  * @brief  Disable Start the SD I/O Read Wait operations.
-  * @retval None
-  */  
-#define __SDIO_START_READWAIT_DISABLE()   (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)
-
-/**
-  * @brief  Enable Start the SD I/O Read Wait operation.
-  * @retval None
-  */  
-#define __SDIO_STOP_READWAIT_ENABLE()   (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)
-
-/**
-  * @brief  Disable Stop the SD I/O Read Wait operations.
-  * @retval None
-  */  
-#define __SDIO_STOP_READWAIT_DISABLE()   (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)
-
-/**
-  * @brief  Enable the SD I/O Mode Operation.
-  * @retval None
-  */  
-#define __SDIO_OPERATION_ENABLE()   (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)
-
-/**
-  * @brief  Disable the SD I/O Mode Operation.
-  * @retval None
-  */  
-#define __SDIO_OPERATION_DISABLE()   (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)
-
-/**
-  * @brief  Enable the SD I/O Suspend command sending.
-  * @retval None
-  */  
-#define __SDIO_SUSPEND_CMD_ENABLE()   (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE)
-
-/**
-  * @brief  Disable the SD I/O Suspend command sending.
-  * @retval None
-  */  
-#define __SDIO_SUSPEND_CMD_DISABLE()   (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
-    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F412Zx) ||\
-    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
-/**
-  * @brief  Enable the command completion signal.
-  * @retval None
-  */    
-#define __SDIO_CEATA_CMD_COMPLETION_ENABLE()   (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE)
-
-/**
-  * @brief  Disable the command completion signal.
-  * @retval None
-  */  
-#define __SDIO_CEATA_CMD_COMPLETION_DISABLE()   (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE)
-
-/**
-  * @brief  Enable the CE-ATA interrupt.
-  * @retval None
-  */    
-#define __SDIO_CEATA_ENABLE_IT()   (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0U)
-
-/**
-  * @brief  Disable the CE-ATA interrupt.
-  * @retval None
-  */  
-#define __SDIO_CEATA_DISABLE_IT()   (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1U)
-
-/**
-  * @brief  Enable send CE-ATA command (CMD61).
-  * @retval None
-  */  
-#define __SDIO_CEATA_SENDCMD_ENABLE()   (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE)
-
-/**
-  * @brief  Disable send CE-ATA command (CMD61).
-  * @retval None
-  */  
-#define __SDIO_CEATA_SENDCMD_DISABLE()   (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE ||\
-          STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F412Zx || STM32F412Vx || STM32F412Rx ||\
-          STM32F412Cx */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */  
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SDMMC_LL_Exported_Functions
-  * @{
-  */
-  
-/* Initialization/de-initialization functions  **********************************/
-/** @addtogroup HAL_SDMMC_LL_Group1
-  * @{
-  */
-HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
-/**
-  * @}
-  */
-  
-/* I/O operation functions  *****************************************************/
-/** @addtogroup HAL_SDMMC_LL_Group2
-  * @{
-  */
-/* Blocking mode: Polling */
-uint32_t          SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
-HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData);
-/**
-  * @}
-  */
-  
-/* Peripheral Control functions  ************************************************/
-/** @addtogroup HAL_SDMMC_LL_Group3
-  * @{
-  */
-HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
-HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
-uint32_t          SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
-
-/* Command path state machine (CPSM) management functions */
-HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
-uint8_t           SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
-uint32_t          SDIO_GetResponse(uint32_t SDIO_RESP);
-
-/* Data path state machine (DPSM) management functions */
-HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDIO_DataInitStruct);
-uint32_t          SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
-uint32_t          SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
-
-/* SDIO IO Cards mode management functions */
-HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
-          STM32F412Rx || STM32F412Cx */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_LL_SDMMC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/inc/stm32f4xx_ll_usb.h b/stmhal/hal/f4/inc/stm32f4xx_ll_usb.h
deleted file mode 100644
index 15dc5c9a14..0000000000
--- a/stmhal/hal/f4/inc/stm32f4xx_ll_usb.h
+++ /dev/null
@@ -1,477 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_ll_usb.h
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   Header file of USB Core HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_LL_USB_H
-#define __STM32F4xx_LL_USB_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
-    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
-    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
-    defined(STM32F412Rx) || defined(STM32F412Cx)
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/** @addtogroup STM32F4xx_HAL
-  * @{
-  */
-
-/** @addtogroup USB_Core
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-
-/** 
-  * @brief  USB Mode definition  
-  */  
-typedef enum 
-{
-   USB_OTG_DEVICE_MODE  = 0U,
-   USB_OTG_HOST_MODE    = 1U,
-   USB_OTG_DRD_MODE     = 2U
-   
-}USB_OTG_ModeTypeDef;
-
-/** 
-  * @brief  URB States definition  
-  */ 
-typedef enum {
-  URB_IDLE = 0U,
-  URB_DONE,
-  URB_NOTREADY,
-  URB_NYET,
-  URB_ERROR,
-  URB_STALL
-    
-}USB_OTG_URBStateTypeDef;
-
-/** 
-  * @brief  Host channel States  definition  
-  */ 
-typedef enum {
-  HC_IDLE = 0U,
-  HC_XFRC,
-  HC_HALTED,
-  HC_NAK,
-  HC_NYET,
-  HC_STALL,
-  HC_XACTERR,  
-  HC_BBLERR,   
-  HC_DATATGLERR
-    
-}USB_OTG_HCStateTypeDef;
-
-/** 
-  * @brief  PCD Initialization Structure definition  
-  */
-typedef struct
-{
-  uint32_t dev_endpoints;        /*!< Device Endpoints number.
-                                      This parameter depends on the used USB core.   
-                                      This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
-
-  uint32_t Host_channels;        /*!< Host Channels number.
-                                      This parameter Depends on the used USB core.   
-                                      This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
-
-  uint32_t speed;                /*!< USB Core speed.
-                                      This parameter can be any value of @ref USB_Core_Speed_                */
-
-  uint32_t dma_enable;           /*!< Enable or disable of the USB embedded DMA.                             */
-
-  uint32_t ep0_mps;              /*!< Set the Endpoint 0 Max Packet size. 
-                                      This parameter can be any value of @ref USB_EP0_MPS_                   */
-
-  uint32_t phy_itface;           /*!< Select the used PHY interface.
-                                      This parameter can be any value of @ref USB_Core_PHY_                  */
-
-  uint32_t Sof_enable;           /*!< Enable or disable the output of the SOF signal.                        */
-
-  uint32_t low_power_enable;     /*!< Enable or disable the low power mode.                                  */
-
-  uint32_t lpm_enable;           /*!< Enable or disable Link Power Management.                               */
-
-  uint32_t battery_charging_enable; /*!< Enable or disable Battery charging.                                 */
-
-  uint32_t vbus_sensing_enable;  /*!< Enable or disable the VBUS Sensing feature.                            */ 
-
-  uint32_t use_dedicated_ep1;    /*!< Enable or disable the use of the dedicated EP1 interrupt.              */
-
-  uint32_t use_external_vbus;    /*!< Enable or disable the use of the external VBUS.                        */
-
-}USB_OTG_CfgTypeDef;
-
-/** 
-  * @brief  OTG End Point Initialization Structure definition 
-  */
-typedef struct
-{
-  uint8_t   num;            /*!< Endpoint number
-                                This parameter must be a number between Min_Data = 1 and Max_Data = 15    */
-
-  uint8_t   is_in;          /*!< Endpoint direction
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 1     */
-
-  uint8_t   is_stall;       /*!< Endpoint stall condition
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 1     */
-
-  uint8_t   type;           /*!< Endpoint type
-                                 This parameter can be any value of @ref USB_EP_Type_                     */
-
-  uint8_t   data_pid_start; /*!< Initial data PID
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 1     */
-
-  uint8_t   even_odd_frame; /*!< IFrame parity
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 1    */
-
-  uint16_t  tx_fifo_num;    /*!< Transmission FIFO number
-                                 This parameter must be a number between Min_Data = 1 and Max_Data = 15   */
-
-  uint32_t  maxpacket;      /*!< Endpoint Max packet size
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
-
-  uint8_t   *xfer_buff;     /*!< Pointer to transfer buffer                                               */
-
-  uint32_t  dma_addr;       /*!< 32 bits aligned transfer buffer address                                  */
-
-  uint32_t  xfer_len;       /*!< Current transfer length                                                  */
-
-  uint32_t  xfer_count;     /*!< Partial transfer length in case of multi packet transfer                 */
-
-}USB_OTG_EPTypeDef;
-
-/** 
-  * @brief  OTG HC Initialization Structure definition 
-  */
-typedef struct
-{
-  uint8_t   dev_addr ;     /*!< USB device address.
-                                This parameter must be a number between Min_Data = 1 and Max_Data = 255    */
-
-  uint8_t   ch_num;        /*!< Host channel number.
-                                This parameter must be a number between Min_Data = 1 and Max_Data = 15     */
-
-  uint8_t   ep_num;        /*!< Endpoint number.
-                                This parameter must be a number between Min_Data = 1 and Max_Data = 15     */
-
-  uint8_t   ep_is_in;      /*!< Endpoint direction
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
-
-  uint8_t   speed;         /*!< USB Host speed.
-                                This parameter can be any value of @ref USB_Core_Speed_                    */
-
-  uint8_t   do_ping;       /*!< Enable or disable the use of the PING protocol for HS mode.                */
-
-  uint8_t   process_ping;  /*!< Execute the PING protocol for HS mode.                                     */
-
-  uint8_t   ep_type;       /*!< Endpoint Type.
-                                This parameter can be any value of @ref USB_EP_Type_                       */
-
-  uint16_t  max_packet;    /*!< Endpoint Max packet size.
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 64KB   */
-
-  uint8_t   data_pid;      /*!< Initial data PID.
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
-
-  uint8_t   *xfer_buff;    /*!< Pointer to transfer buffer.                                                */
-
-  uint32_t  xfer_len;      /*!< Current transfer length.                                                   */
-
-  uint32_t  xfer_count;    /*!< Partial transfer length in case of multi packet transfer.                  */
-
-  uint8_t   toggle_in;     /*!< IN transfer current toggle flag.
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
-
-  uint8_t   toggle_out;    /*!< OUT transfer current toggle flag
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
-
-  uint32_t  dma_addr;      /*!< 32 bits aligned transfer buffer address.                                   */
-
-  uint32_t  ErrCnt;        /*!< Host channel error count.*/
-
-  USB_OTG_URBStateTypeDef  urb_state;  /*!< URB state. 
-                                           This parameter can be any value of @ref USB_OTG_URBStateTypeDef */
-
-  USB_OTG_HCStateTypeDef   state;     /*!< Host Channel state. 
-                                           This parameter can be any value of @ref USB_OTG_HCStateTypeDef  */
-
-}USB_OTG_HCTypeDef;
-  
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup PCD_Exported_Constants PCD Exported Constants
-  * @{
-  */
-
-/** @defgroup USB_Core_Mode_ USB Core Mode
-  * @{
-  */
-#define USB_OTG_MODE_DEVICE                    0U
-#define USB_OTG_MODE_HOST                      1U
-#define USB_OTG_MODE_DRD                       2U
-/**
-  * @}
-  */
-
-/** @defgroup USB_Core_Speed_   USB Core Speed
-  * @{
-  */  
-#define USB_OTG_SPEED_HIGH                     0U
-#define USB_OTG_SPEED_HIGH_IN_FULL             1U
-#define USB_OTG_SPEED_LOW                      2U
-#define USB_OTG_SPEED_FULL                     3U
-/**
-  * @}
-  */
-  
-/** @defgroup USB_Core_PHY_   USB Core PHY
-  * @{
-  */   
-#define USB_OTG_ULPI_PHY                       1U
-#define USB_OTG_EMBEDDED_PHY                   2U
-/**
-  * @}
-  */
-  
-/** @defgroup USB_Core_MPS_   USB Core MPS
-  * @{
-  */
-#define USB_OTG_HS_MAX_PACKET_SIZE           512U
-#define USB_OTG_FS_MAX_PACKET_SIZE           64U
-#define USB_OTG_MAX_EP0_SIZE                 64U
-/**
-  * @}
-  */
-
-/** @defgroup USB_Core_Phy_Frequency_   USB Core Phy Frequency
-  * @{
-  */
-#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ     (0U << 1U)
-#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ     (1U << 1U)
-#define DSTS_ENUMSPD_LS_PHY_6MHZ               (2U << 1U)
-#define DSTS_ENUMSPD_FS_PHY_48MHZ              (3U << 1U)
-/**
-  * @}
-  */
-  
-/** @defgroup USB_CORE_Frame_Interval_   USB CORE Frame Interval
-  * @{
-  */  
-#define DCFG_FRAME_INTERVAL_80                 0U
-#define DCFG_FRAME_INTERVAL_85                 1U
-#define DCFG_FRAME_INTERVAL_90                 2U
-#define DCFG_FRAME_INTERVAL_95                 3U
-/**
-  * @}
-  */
-
-/** @defgroup USB_EP0_MPS_  USB EP0 MPS
-  * @{
-  */
-#define DEP0CTL_MPS_64                         0U
-#define DEP0CTL_MPS_32                         1U
-#define DEP0CTL_MPS_16                         2U
-#define DEP0CTL_MPS_8                          3U
-/**
-  * @}
-  */
-
-/** @defgroup USB_EP_Speed_  USB EP Speed
-  * @{
-  */
-#define EP_SPEED_LOW                           0U
-#define EP_SPEED_FULL                          1U
-#define EP_SPEED_HIGH                          2U
-/**
-  * @}
-  */
-
-/** @defgroup USB_EP_Type_  USB EP Type
-  * @{
-  */
-#define EP_TYPE_CTRL                           0U
-#define EP_TYPE_ISOC                           1U
-#define EP_TYPE_BULK                           2U
-#define EP_TYPE_INTR                           3U
-#define EP_TYPE_MSK                            3U
-/**
-  * @}
-  */
-
-/** @defgroup USB_STS_Defines_   USB STS Defines
-  * @{
-  */
-#define STS_GOUT_NAK                           1U
-#define STS_DATA_UPDT                          2U
-#define STS_XFER_COMP                          3U
-#define STS_SETUP_COMP                         4U
-#define STS_SETUP_UPDT                         6U
-/**
-  * @}
-  */
-
-/** @defgroup HCFG_SPEED_Defines_   HCFG SPEED Defines
-  * @{
-  */  
-#define HCFG_30_60_MHZ                         0U
-#define HCFG_48_MHZ                            1U
-#define HCFG_6_MHZ                             2U
-/**
-  * @}
-  */
-    
-/** @defgroup HPRT0_PRTSPD_SPEED_Defines_  HPRT0 PRTSPD SPEED Defines
-  * @{
-  */    
-#define HPRT0_PRTSPD_HIGH_SPEED                0U
-#define HPRT0_PRTSPD_FULL_SPEED                1U
-#define HPRT0_PRTSPD_LOW_SPEED                 2U
-/**
-  * @}
-  */  
-   
-#define HCCHAR_CTRL                            0U
-#define HCCHAR_ISOC                            1U
-#define HCCHAR_BULK                            2U
-#define HCCHAR_INTR                            3U
-       
-#define HC_PID_DATA0                           0U
-#define HC_PID_DATA2                           1U
-#define HC_PID_DATA1                           2U
-#define HC_PID_SETUP                           3U
-
-#define GRXSTS_PKTSTS_IN                       2
-#define GRXSTS_PKTSTS_IN_XFER_COMP             3
-#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR          5
-#define GRXSTS_PKTSTS_CH_HALTED                7
-    
-#define USBx_PCGCCTL    *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_PCGCCTL_BASE)
-#define USBx_HPRT0      *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_HOST_PORT_BASE)
-
-#define USBx_DEVICE     ((USB_OTG_DeviceTypeDef *)((uint32_t )USBx + USB_OTG_DEVICE_BASE)) 
-#define USBx_INEP(i)    ((USB_OTG_INEndpointTypeDef *)((uint32_t)USBx + USB_OTG_IN_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE))
-#define USBx_OUTEP(i)   ((USB_OTG_OUTEndpointTypeDef *)((uint32_t)USBx + USB_OTG_OUT_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE))
-#define USBx_DFIFO(i)   *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_FIFO_BASE + (i) * USB_OTG_FIFO_SIZE)
-
-#define USBx_HOST       ((USB_OTG_HostTypeDef *)((uint32_t )USBx + USB_OTG_HOST_BASE))
-#define USBx_HC(i)      ((USB_OTG_HostChannelTypeDef *)((uint32_t)USBx + USB_OTG_HOST_CHANNEL_BASE + (i)*USB_OTG_HOST_CHANNEL_SIZE))
-/**
-  * @}
-  */
-/* Exported macro ------------------------------------------------------------*/
-#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__)     ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))
-#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__)   ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))
-    
-#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__)          (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))
-#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__)         (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))
-
-/* Exported functions --------------------------------------------------------*/
-HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
-HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
-HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode);
-HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed);
-HAL_StatusTypeDef USB_FlushRxFifo (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num );
-HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma);
-HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma);
-HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma);
-void *            USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
-HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address);
-HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup);
-uint8_t           USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);
-uint32_t          USB_GetMode(USB_OTG_GlobalTypeDef *USBx);
-uint32_t          USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx);
-uint32_t          USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx);
-uint32_t          USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);
-uint32_t          USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx);
-uint32_t          USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);
-void              USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
-
-HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
-HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq);
-HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state);
-uint32_t          USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx);
-uint32_t          USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,  
-                                  uint8_t ch_num,
-                                  uint8_t epnum,
-                                  uint8_t dev_address,
-                                  uint8_t speed,
-                                  uint8_t ep_type,
-                                  uint16_t mps);
-HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma);
-uint32_t          USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num);
-HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num);
-HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx ||
-          STM32F412Vx || STM32F412Cx */
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F4xx_LL_USB_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal.c b/stmhal/hal/f4/src/stm32f4xx_hal.c
deleted file mode 100644
index c0965368ed..0000000000
--- a/stmhal/hal/f4/src/stm32f4xx_hal.c
+++ /dev/null
@@ -1,535 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal.c
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   HAL module driver.
-  *          This is the common part of the HAL initialization
-  *
-  @verbatim
-  ==============================================================================
-                     ##### How to use this driver #####
-  ==============================================================================
-    [..]
-    The common HAL driver contains a set of generic and common APIs that can be
-    used by the PPP peripheral drivers and the user to start using the HAL. 
-    [..]
-    The HAL contains two APIs' categories: 
-         (+) Common HAL APIs
-         (+) Services HAL APIs
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup HAL HAL
-  * @brief HAL module driver.
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup HAL_Private_Constants
-  * @{
-  */
-/**
-  * @brief STM32F4xx HAL Driver version number V1.5.2
-  */
-#define __STM32F4xx_HAL_VERSION_MAIN   (0x01) /*!< [31:24] main version */
-#define __STM32F4xx_HAL_VERSION_SUB1   (0x05) /*!< [23:16] sub1 version */
-#define __STM32F4xx_HAL_VERSION_SUB2   (0x02) /*!< [15:8]  sub2 version */
-#define __STM32F4xx_HAL_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
-#define __STM32F4xx_HAL_VERSION         ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\
-                                        |(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\
-                                        |(__STM32F4xx_HAL_VERSION_SUB2 << 8U )\
-                                        |(__STM32F4xx_HAL_VERSION_RC))
-
-#define IDCODE_DEVID_MASK    ((uint32_t)0x00000FFFU)
-
-/* ------------ RCC registers bit address in the alias region ----------- */
-#define SYSCFG_OFFSET             (SYSCFG_BASE - PERIPH_BASE)
-/* ---  MEMRMP Register ---*/ 
-/* Alias word address of UFB_MODE bit */ 
-#define MEMRMP_OFFSET             SYSCFG_OFFSET 
-#define UFB_MODE_BIT_NUMBER       POSITION_VAL(SYSCFG_MEMRMP_UFB_MODE)
-#define UFB_MODE_BB               (uint32_t)(PERIPH_BB_BASE + (MEMRMP_OFFSET * 32U) + (UFB_MODE_BIT_NUMBER * 4U)) 
-
-/* ---  CMPCR Register ---*/ 
-/* Alias word address of CMP_PD bit */ 
-#define CMPCR_OFFSET              (SYSCFG_OFFSET + 0x20U) 
-#define CMP_PD_BIT_NUMBER         POSITION_VAL(SYSCFG_CMPCR_CMP_PD)
-#define CMPCR_CMP_PD_BB           (uint32_t)(PERIPH_BB_BASE + (CMPCR_OFFSET * 32U) + (CMP_PD_BIT_NUMBER * 4U))
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @addtogroup HAL_Private_Variables
-  * @{
-  */
-__IO uint32_t uwTick;
-/**
-  * @}
-  */
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup HAL_Exported_Functions HAL Exported Functions
-  * @{
-  */
-
-/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions 
- *  @brief    Initialization and de-initialization functions
- *
-@verbatim    
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Initializes the Flash interface the NVIC allocation and initial clock 
-          configuration. It initializes the systick also when timeout is needed 
-          and the backup domain when enabled.
-      (+) de-Initializes common part of the HAL
-      (+) Configure The time base source to have 1ms time base with a dedicated 
-          Tick interrupt priority. 
-        (++) Systick timer is used by default as source of time base, but user 
-             can eventually implement his proper time base source (a general purpose 
-             timer for example or other time source), keeping in mind that Time base 
-             duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
-             handled in milliseconds basis.
-        (++) Time base configuration function (HAL_InitTick ()) is called automatically 
-             at the beginning of the program after reset by HAL_Init() or at any time 
-             when clock is configured, by HAL_RCC_ClockConfig(). 
-        (++) Source of time base is configured  to generate interrupts at regular 
-             time intervals. Care must be taken if HAL_Delay() is called from a 
-             peripheral ISR process, the Tick interrupt line must have higher priority 
-            (numerically lower) than the peripheral interrupt. Otherwise the caller 
-            ISR process will be blocked. 
-       (++) functions affecting time base configurations are declared as __weak  
-             to make  override possible  in case of other  implementations in user file.
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  This function is used to initialize the HAL Library; it must be the first 
-  *         instruction to be executed in the main program (before to call any other
-  *         HAL function), it performs the following:
-  *           Configure the Flash prefetch, instruction and Data caches.
-  *           Configures the SysTick to generate an interrupt each 1 millisecond,
-  *           which is clocked by the HSI (at this stage, the clock is not yet
-  *           configured and thus the system is running from the internal HSI at 16 MHz).
-  *           Set NVIC Group Priority to 4.
-  *           Calls the HAL_MspInit() callback function defined in user file 
-  *           "stm32f4xx_hal_msp.c" to do the global low level hardware initialization 
-  *            
-  * @note   SysTick is used as time base for the HAL_Delay() function, the application
-  *         need to ensure that the SysTick time base is always set to 1 millisecond
-  *         to have correct HAL operation.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_Init(void)
-{
-  /* Configure Flash prefetch, Instruction cache, Data cache */ 
-#if (INSTRUCTION_CACHE_ENABLE != 0U)
-   __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
-#endif /* INSTRUCTION_CACHE_ENABLE */
-
-#if (DATA_CACHE_ENABLE != 0U)
-   __HAL_FLASH_DATA_CACHE_ENABLE();
-#endif /* DATA_CACHE_ENABLE */
-
-#if (PREFETCH_ENABLE != 0U)
-  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
-#endif /* PREFETCH_ENABLE */
-
-  /* Set Interrupt Group Priority */
-  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
-
-  /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
-  HAL_InitTick(TICK_INT_PRIORITY);
-  
-  /* Init the low level hardware */
-  HAL_MspInit();
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function de-Initializes common part of the HAL and stops the systick.
-  *         This function is optional.   
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DeInit(void)
-{
-  /* Reset of all peripherals */
-  __HAL_RCC_APB1_FORCE_RESET();
-  __HAL_RCC_APB1_RELEASE_RESET();
-
-  __HAL_RCC_APB2_FORCE_RESET();
-  __HAL_RCC_APB2_RELEASE_RESET();
-
-  __HAL_RCC_AHB1_FORCE_RESET();
-  __HAL_RCC_AHB1_RELEASE_RESET();
-
-  __HAL_RCC_AHB2_FORCE_RESET();
-  __HAL_RCC_AHB2_RELEASE_RESET();
-
-  __HAL_RCC_AHB3_FORCE_RESET();
-  __HAL_RCC_AHB3_RELEASE_RESET();
-
-  /* De-Init the low level hardware */
-  HAL_MspDeInit();
-    
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the MSP.
-  * @retval None
-  */
-__weak void HAL_MspInit(void)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes the MSP.
-  * @retval None
-  */
-__weak void HAL_MspDeInit(void)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_MspDeInit could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief This function configures the source of the time base.
-  *        The time source is configured  to have 1ms time base with a dedicated 
-  *        Tick interrupt priority.
-  * @note This function is called  automatically at the beginning of program after
-  *       reset by HAL_Init() or at any time when clock is reconfigured  by HAL_RCC_ClockConfig().
-  * @note In the default implementation, SysTick timer is the source of time base. 
-  *       It is used to generate interrupts at regular time intervals. 
-  *       Care must be taken if HAL_Delay() is called from a peripheral ISR process, 
-  *       The the SysTick interrupt must have higher priority (numerically lower) 
-  *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
-  *       The function is declared as __weak  to be overwritten  in case of other
-  *       implementation  in user file.
-  * @param TickPriority: Tick interrupt priority.
-  * @retval HAL status
-  */
-__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
-{
-  /*Configure the SysTick to have interrupt in 1ms time basis*/
-  HAL_SYSTICK_Config(SystemCoreClock/1000U);
-
-  /*Configure the SysTick IRQ priority */
-  HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0U);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions 
- *  @brief    HAL Control functions
- *
-@verbatim
- ===============================================================================
-                      ##### HAL Control functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Provide a tick value in millisecond
-      (+) Provide a blocking delay in millisecond
-      (+) Suspend the time base source interrupt
-      (+) Resume the time base source interrupt
-      (+) Get the HAL API driver version
-      (+) Get the device identifier
-      (+) Get the device revision identifier
-      (+) Enable/Disable Debug module during SLEEP mode
-      (+) Enable/Disable Debug module during STOP mode
-      (+) Enable/Disable Debug module during STANDBY mode
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief This function is called to increment  a global variable "uwTick"
-  *        used as application time base.
-  * @note In the default implementation, this variable is incremented each 1ms
-  *       in Systick ISR.
- * @note This function is declared as __weak to be overwritten in case of other 
-  *      implementations in user file.
-  * @retval None
-  */
-__weak void HAL_IncTick(void)
-{
-  uwTick++;
-}
-
-/**
-  * @brief Provides a tick value in millisecond.
-  * @note This function is declared as __weak to be overwritten in case of other 
-  *       implementations in user file.
-  * @retval tick value
-  */
-__weak uint32_t HAL_GetTick(void)
-{
-  return uwTick;
-}
-
-/**
-  * @brief This function provides accurate delay (in milliseconds) based 
-  *        on variable incremented.
-  * @note In the default implementation , SysTick timer is the source of time base.
-  *       It is used to generate interrupts at regular time intervals where uwTick
-  *       is incremented.
-  * @note This function is declared as __weak to be overwritten in case of other
-  *       implementations in user file.
-  * @param Delay: specifies the delay time length, in milliseconds.
-  * @retval None
-  */
-__weak void HAL_Delay(__IO uint32_t Delay)
-{
-    uint32_t start = HAL_GetTick();
-   
-    // Note that the following works (due to the magic of 2's complement numbers)
-    // even when Delay causes wraparound.
-   
-    while (HAL_GetTick() - start <= Delay) {
-      __WFI();  // enter sleep mode, waiting for interrupt
-    }
-}
-
-/**
-  * @brief Suspend Tick increment.
-  * @note In the default implementation , SysTick timer is the source of time base. It is
-  *       used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
-  *       is called, the SysTick interrupt will be disabled and so Tick increment 
-  *       is suspended.
-  * @note This function is declared as __weak to be overwritten in case of other
-  *       implementations in user file.
-  * @retval None
-  */
-__weak void HAL_SuspendTick(void)
-{
-  /* Disable SysTick Interrupt */
-  SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
-}
-
-/**
-  * @brief Resume Tick increment.
-  * @note In the default implementation , SysTick timer is the source of time base. It is
-  *       used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
-  *       is called, the SysTick interrupt will be enabled and so Tick increment 
-  *       is resumed.
-  * @note This function is declared as __weak to be overwritten in case of other
-  *       implementations in user file.
-  * @retval None
-  */
-__weak void HAL_ResumeTick(void)
-{
-  /* Enable SysTick Interrupt */
-  SysTick->CTRL  |= SysTick_CTRL_TICKINT_Msk;
-}
-
-/**
-  * @brief  Returns the HAL revision
-  * @retval version : 0xXYZR (8bits for each decimal, R for RC)
-  */
-uint32_t HAL_GetHalVersion(void)
-{
- return __STM32F4xx_HAL_VERSION;
-}
-
-/**
-  * @brief  Returns the device revision identifier.
-  * @retval Device revision identifier
-  */
-uint32_t HAL_GetREVID(void)
-{
-   return((DBGMCU->IDCODE) >> 16U);
-}
-
-/**
-  * @brief  Returns the device identifier.
-  * @retval Device identifier
-  */
-uint32_t HAL_GetDEVID(void)
-{
-   return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
-}
-
-/**
-  * @brief  Enable the Debug Module during SLEEP mode
-  * @retval None
-  */
-void HAL_DBGMCU_EnableDBGSleepMode(void)
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
-  * @brief  Disable the Debug Module during SLEEP mode
-  * @retval None
-  */
-void HAL_DBGMCU_DisableDBGSleepMode(void)
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
-  * @brief  Enable the Debug Module during STOP mode
-  * @retval None
-  */
-void HAL_DBGMCU_EnableDBGStopMode(void)
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
-}
-
-/**
-  * @brief  Disable the Debug Module during STOP mode
-  * @retval None
-  */
-void HAL_DBGMCU_DisableDBGStopMode(void)
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
-}
-
-/**
-  * @brief  Enable the Debug Module during STANDBY mode
-  * @retval None
-  */
-void HAL_DBGMCU_EnableDBGStandbyMode(void)
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
-}
-
-/**
-  * @brief  Disable the Debug Module during STANDBY mode
-  * @retval None
-  */
-void HAL_DBGMCU_DisableDBGStandbyMode(void)
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
-}
-
-/**
-  * @brief  Enables the I/O Compensation Cell.
-  * @note   The I/O compensation cell can be used only when the device supply
-  *         voltage ranges from 2.4 to 3.6 V.  
-  * @retval None
-  */
-void HAL_EnableCompensationCell(void)
-{
-  *(__IO uint32_t *)CMPCR_CMP_PD_BB = (uint32_t)ENABLE;
-}
-
-/**
-  * @brief  Power-down the I/O Compensation Cell.
-  * @note   The I/O compensation cell can be used only when the device supply
-  *         voltage ranges from 2.4 to 3.6 V.  
-  * @retval None
-  */
-void HAL_DisableCompensationCell(void)
-{
-  *(__IO uint32_t *)CMPCR_CMP_PD_BB = (uint32_t)DISABLE;
-}
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx)
-/**
-  * @brief  Enables the Internal FLASH Bank Swapping.
-  *   
-  * @note   This function can be used only for STM32F42xxx/43xxx devices. 
-  *
-  * @note   Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000) 
-  *         and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000)   
-  *
-  * @retval None
-  */
-void HAL_EnableMemorySwappingBank(void)
-{
-  *(__IO uint32_t *)UFB_MODE_BB = (uint32_t)ENABLE;
-}
-
-/**
-  * @brief  Disables the Internal FLASH Bank Swapping.
-  *   
-  * @note   This function can be used only for STM32F42xxx/43xxx devices. 
-  *
-  * @note   The default state : Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000) 
-  *         and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000) 
-  *           
-  * @retval None
-  */
-void HAL_DisableMemorySwappingBank(void)
-{
-
-  *(__IO uint32_t *)UFB_MODE_BB = (uint32_t)DISABLE;
-}
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_adc.c b/stmhal/hal/f4/src/stm32f4xx_hal_adc.c
deleted file mode 100644
index 18fe59d4ea..0000000000
--- a/stmhal/hal/f4/src/stm32f4xx_hal_adc.c
+++ /dev/null
@@ -1,1672 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_adc.c
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   This file provides firmware functions to manage the following 
-  *          functionalities of the Analog to Digital Convertor (ADC) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + State and errors functions
-  *         
-  @verbatim
-  ==============================================================================
-                    ##### ADC Peripheral features #####
-  ==============================================================================
-  [..] 
-  (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
-  (#) Interrupt generation at the end of conversion, end of injected conversion,  
-      and in case of analog watchdog or overrun events
-  (#) Single and continuous conversion modes.
-  (#) Scan mode for automatic conversion of channel 0 to channel x.
-  (#) Data alignment with in-built data coherency.
-  (#) Channel-wise programmable sampling time.
-  (#) External trigger option with configurable polarity for both regular and 
-      injected conversion.
-  (#) Dual/Triple mode (on devices with 2 ADCs or more).
-  (#) Configurable DMA data storage in Dual/Triple ADC mode. 
-  (#) Configurable delay between conversions in Dual/Triple interleaved mode.
-  (#) ADC conversion type (refer to the datasheets).
-  (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at 
-      slower speed.
-  (#) ADC input range: VREF(minus) = VIN = VREF(plus).
-  (#) DMA request generation during regular channel conversion.
-
-
-                     ##### How to use this driver #####
-  ==============================================================================
-  [..]
-  (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():
-       (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()
-       (##) ADC pins configuration
-             (+++) Enable the clock for the ADC GPIOs using the following function:
-                   __HAL_RCC_GPIOx_CLK_ENABLE()  
-             (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init() 
-       (##) In case of using interrupts (e.g. HAL_ADC_Start_IT())
-             (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()
-             (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()
-             (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()
-       (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())
-             (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()
-             (+++) Configure and enable two DMA streams stream for managing data
-                 transfer from peripheral to memory (output stream)
-             (+++) Associate the initialized DMA handle to the CRYP DMA handle
-                 using  __HAL_LINKDMA()
-             (+++) Configure the priority and enable the NVIC for the transfer complete
-                 interrupt on the two DMA Streams. The output stream should have higher
-                 priority than the input stream.
-                       
-    *** Configuration of ADC, groups regular/injected, channels parameters ***
-  ==============================================================================
-  [..]
-  (#) Configure the ADC parameters (resolution, data alignment, ...)
-      and regular group parameters (conversion trigger, sequencer, ...)
-      using function HAL_ADC_Init().
-
-  (#) Configure the channels for regular group parameters (channel number, 
-      channel rank into sequencer, ..., into regular group)
-      using function HAL_ADC_ConfigChannel().
-
-  (#) Optionally, configure the injected group parameters (conversion trigger, 
-      sequencer, ..., of injected group)
-      and the channels for injected group parameters (channel number, 
-      channel rank into sequencer, ..., into injected group)
-      using function HAL_ADCEx_InjectedConfigChannel().
-
-  (#) Optionally, configure the analog watchdog parameters (channels
-      monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig().
-
-  (#) Optionally, for devices with several ADC instances: configure the 
-      multimode parameters using function HAL_ADCEx_MultiModeConfigChannel().
-
-                       *** Execution of ADC conversions ***
-  ==============================================================================
-  [..]  
-  (#) ADC driver can be used among three modes: polling, interruption,
-      transfer by DMA.    
-
-     *** Polling mode IO operation ***
-     =================================
-     [..]    
-       (+) Start the ADC peripheral using HAL_ADC_Start() 
-       (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage
-           user can specify the value of timeout according to his end application      
-       (+) To read the ADC converted values, use the HAL_ADC_GetValue() function.
-       (+) Stop the ADC peripheral using HAL_ADC_Stop()
-       
-     *** Interrupt mode IO operation ***    
-     ===================================
-     [..]    
-       (+) Start the ADC peripheral using HAL_ADC_Start_IT() 
-       (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine
-       (+) At ADC end of conversion HAL_ADC_ConvCpltCallback() function is executed and user can 
-           add his own code by customization of function pointer HAL_ADC_ConvCpltCallback 
-       (+) In case of ADC Error, HAL_ADC_ErrorCallback() function is executed and user can 
-           add his own code by customization of function pointer HAL_ADC_ErrorCallback
-       (+) Stop the ADC peripheral using HAL_ADC_Stop_IT()     
-
-     *** DMA mode IO operation ***    
-     ==============================
-     [..]    
-       (+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the length 
-           of data to be transferred at each end of conversion 
-       (+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user can 
-           add his own code by customization of function pointer HAL_ADC_ConvCpltCallback 
-       (+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can 
-           add his own code by customization of function pointer HAL_ADC_ErrorCallback
-       (+) Stop the ADC peripheral using HAL_ADC_Stop_DMA()
-                    
-     *** ADC HAL driver macros list ***
-     ============================================= 
-     [..]
-       Below the list of most used macros in ADC HAL driver.
-       
-      (+) __HAL_ADC_ENABLE : Enable the ADC peripheral
-      (+) __HAL_ADC_DISABLE : Disable the ADC peripheral
-      (+) __HAL_ADC_ENABLE_IT: Enable the ADC end of conversion interrupt
-      (+) __HAL_ADC_DISABLE_IT: Disable the ADC end of conversion interrupt
-      (+) __HAL_ADC_GET_IT_SOURCE: Check if the specified ADC interrupt source is enabled or disabled
-      (+) __HAL_ADC_CLEAR_FLAG: Clear the ADC's pending flags
-      (+) __HAL_ADC_GET_FLAG: Get the selected ADC's flag status
-      (+) ADC_GET_RESOLUTION: Return resolution bits in CR1 register 
-      
-     [..] 
-       (@) You can refer to the ADC HAL driver header file for more useful macros 
-
-                      *** Deinitialization of ADC ***
-  ==============================================================================
-  [..]
-  (#) Disable the ADC interface
-     (++) ADC clock can be hard reset and disabled at RCC top level.
-     (++) Hard reset of ADC peripherals
-          using macro __HAL_RCC_ADC_FORCE_RESET(), __HAL_RCC_ADC_RELEASE_RESET().
-     (++) ADC clock disable using the equivalent macro/functions as configuration step.
-               (+++) Example:
-                   Into HAL_ADC_MspDeInit() (recommended code location) or with
-                   other device clock parameters configuration:
-               (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure);
-               (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI;
-               (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock)
-               (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
-
-  (#) ADC pins configuration
-     (++) Disable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_DISABLE()
-
-  (#) Optionally, in case of usage of ADC with interruptions:
-     (++) Disable the NVIC for ADC using function HAL_NVIC_DisableIRQ(ADCx_IRQn)
-
-  (#) Optionally, in case of usage of DMA:
-        (++) Deinitialize the DMA using function HAL_DMA_DeInit().
-        (++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn)   
-
-    @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup ADC ADC
-  * @brief ADC driver modules
-  * @{
-  */ 
-
-#ifdef HAL_ADC_MODULE_ENABLED
-    
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @addtogroup ADC_Private_Functions
-  * @{
-  */
-/* Private function prototypes -----------------------------------------------*/
-static void ADC_Init(ADC_HandleTypeDef* hadc);
-static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
-static void ADC_DMAError(DMA_HandleTypeDef *hdma);
-static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
-/**
-  * @}
-  */
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup ADC_Exported_Functions ADC Exported Functions
-  * @{
-  */
-
-/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions 
- *
-@verbatim    
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Initialize and configure the ADC. 
-      (+) De-initialize the ADC. 
-         
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the ADCx peripheral according to the specified parameters 
-  *         in the ADC_InitStruct and initializes the ADC MSP.
-  *           
-  * @note   This function is used to configure the global features of the ADC ( 
-  *         ClockPrescaler, Resolution, Data Alignment and number of conversion), however,
-  *         the rest of the configuration parameters are specific to the regular
-  *         channels group (scan mode activation, continuous mode activation,
-  *         External trigger source and edge, DMA continuous request after the  
-  *         last transfer and End of conversion selection).
-  *             
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-  
-  /* Check ADC handle */
-  if(hadc == NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
-  assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
-  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ScanConvMode));
-  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
-  assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv));
-  assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
-  assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
-  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
-  assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
-  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
-  
-  if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
-  {
-    assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
-  }
-  
-  if(hadc->State == HAL_ADC_STATE_RESET)
-  {
-    /* Initialize ADC error code */
-    ADC_CLEAR_ERRORCODE(hadc);
-    
-    /* Allocate lock resource and initialize it */
-    hadc->Lock = HAL_UNLOCKED;
-    
-    /* Init the low level hardware */
-    HAL_ADC_MspInit(hadc);
-  }
-  
-  /* Configuration of ADC parameters if previous preliminary actions are      */ 
-  /* correctly completed.                                                     */
-  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
-  {
-    /* Set ADC state */
-    ADC_STATE_CLR_SET(hadc->State,
-                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
-                      HAL_ADC_STATE_BUSY_INTERNAL);
-    
-    /* Set ADC parameters */
-    ADC_Init(hadc);
-    
-    /* Set ADC error code to none */
-    ADC_CLEAR_ERRORCODE(hadc);
-    
-    /* Set the ADC state */
-    ADC_STATE_CLR_SET(hadc->State,
-                      HAL_ADC_STATE_BUSY_INTERNAL,
-                      HAL_ADC_STATE_READY);
-  }
-  else
-  {
-    tmp_hal_status = HAL_ERROR;
-  }
-  
-  /* Release Lock */
-  __HAL_UNLOCK(hadc);
-
-  /* Return function status */
-  return tmp_hal_status;
-}
-
-/**
-  * @brief  Deinitializes the ADCx peripheral registers to their default reset values. 
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-  
-  /* Check ADC handle */
-  if(hadc == NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  /* Set ADC state */
-  SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
-  
-  /* Stop potential conversion on going, on regular and injected groups */
-  /* Disable ADC peripheral */
-  __HAL_ADC_DISABLE(hadc);
-  
-  /* Configuration of ADC parameters if previous preliminary actions are      */ 
-  /* correctly completed.                                                     */
-  if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
-  {
-    /* DeInit the low level hardware */
-    HAL_ADC_MspDeInit(hadc);
-    
-    /* Set ADC error code to none */
-    ADC_CLEAR_ERRORCODE(hadc);
-    
-    /* Set ADC state */
-    hadc->State = HAL_ADC_STATE_RESET;
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmp_hal_status;
-}
-
-/**
-  * @brief  Initializes the ADC MSP.
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.  
-  * @retval None
-  */
-__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_ADC_MspInit could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  DeInitializes the ADC MSP.
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.  
-  * @retval None
-  */
-__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_ADC_MspDeInit could be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Exported_Functions_Group2 IO operation functions
- *  @brief    IO operation functions 
- *
-@verbatim   
- ===============================================================================
-             ##### IO operation functions #####
- ===============================================================================  
-    [..]  This section provides functions allowing to:
-      (+) Start conversion of regular channel.
-      (+) Stop conversion of regular channel.
-      (+) Start conversion of regular channel and enable interrupt.
-      (+) Stop conversion of regular channel and disable interrupt.
-      (+) Start conversion of regular channel and enable DMA transfer.
-      (+) Stop conversion of regular channel and disable DMA transfer.
-      (+) Handle ADC interrupt request. 
-               
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables ADC and starts conversion of the regular channels.
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
-{
-  __IO uint32_t counter = 0U;
-  
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
-  assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); 
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  /* Enable the ADC peripheral */
-  /* Check if ADC peripheral is disabled in order to enable it and wait during 
-  Tstab time the ADC's stabilization */
-  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
-  {  
-    /* Enable the Peripheral */
-    __HAL_ADC_ENABLE(hadc);
-    
-    /* Delay for ADC stabilization time */
-    /* Compute number of CPU cycles to wait for */
-    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
-    while(counter != 0U)
-    {
-      counter--;
-    }
-  }
-  
-  /* Start conversion if ADC is effectively enabled */
-  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
-  {
-    /* Set ADC state                                                          */
-    /* - Clear state bitfield related to regular group conversion results     */
-    /* - Set state bitfield related to regular group operation                */
-    ADC_STATE_CLR_SET(hadc->State,
-                      HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
-                      HAL_ADC_STATE_REG_BUSY);
-    
-    /* If conversions on group regular are also triggering group injected,    */
-    /* update ADC state.                                                      */
-    if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
-    {
-      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  
-    }
-    
-    /* State machine update: Check if an injected conversion is ongoing */
-    if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
-    {
-      /* Reset ADC error code fields related to conversions on group regular */
-      CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));         
-    }
-    else
-    {
-      /* Reset ADC all error code fields */
-      ADC_CLEAR_ERRORCODE(hadc);
-    }
-    
-    /* Process unlocked */
-    /* Unlock before starting ADC conversions: in case of potential           */
-    /* interruption, to let the process to ADC IRQ Handler.                   */
-    __HAL_UNLOCK(hadc);
-    
-    /* Clear regular group conversion flag and overrun flag */
-    /* (To ensure of no unknown state from potential previous ADC operations) */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
-    
-    /* Check if Multimode enabled */
-    if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
-    {
-      /* if no external trigger present enable software conversion of regular channels */
-      if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) 
-      {
-        /* Enable the selected ADC software conversion for regular group */
-        hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
-      }
-    }
-    else
-    {
-      /* if instance of handle correspond to ADC1 and  no external trigger present enable software conversion of regular channels */
-      if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
-      {
-        /* Enable the selected ADC software conversion for regular group */
-          hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
-      }
-    }
-  }
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disables ADC and stop conversion of regular channels.
-  * 
-  * @note   Caution: This function will stop also injected channels.  
-  *
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  *
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  /* Stop potential conversion on going, on regular and injected groups */
-  /* Disable ADC peripheral */
-  __HAL_ADC_DISABLE(hadc);
-  
-  /* Check if ADC is effectively disabled */
-  if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
-  {
-    /* Set ADC state */
-    ADC_STATE_CLR_SET(hadc->State,
-                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
-                      HAL_ADC_STATE_READY);
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Poll for regular conversion complete
-  * @note   ADC conversion flags EOS (end of sequence) and EOC (end of
-  *         conversion) are cleared by this function.
-  * @note   This function cannot be used in a particular setup: ADC configured 
-  *         in DMA mode and polling for end of each conversion (ADC init
-  *         parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
-  *         In this case, DMA resets the flag EOC and polling cannot be
-  *         performed on each conversion. Nevertheless, polling can still 
-  *         be performed on the complete sequence.
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @param  Timeout: Timeout value in millisecond.  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
-{
-  uint32_t tickstart = 0U;
- 
-  /* Verification that ADC configuration is compliant with polling for      */
-  /* each conversion:                                                       */
-  /* Particular case is ADC configured in DMA mode and ADC sequencer with   */
-  /* several ranks and polling for end of each conversion.                  */
-  /* For code simplicity sake, this particular case is generalized to       */
-  /* ADC configured in DMA mode and polling for end of each conversion.     */
-  if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&
-      HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA)    )
-  {
-    /* Update ADC state machine to error */
-    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-    
-    /* Process unlocked */
-    __HAL_UNLOCK(hadc);
-    
-    return HAL_ERROR;
-  }
-
-  /* Get tick */ 
-  tickstart = HAL_GetTick();
-
-  /* Check End of conversion flag */
-  while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
-  {
-    /* Check if timeout is disabled (set to infinite wait) */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        /* Update ADC state machine to timeout */
-        SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
-        
-        /* Process unlocked */
-        __HAL_UNLOCK(hadc);
-        
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  
-  /* Clear regular group conversion flag */
-  __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
-  
-  /* Update ADC state machine */
-  SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
-  
-  /* Determine whether any further conversion upcoming on group regular       */
-  /* by external trigger, continuous mode or scan sequence on going.          */
-  /* Note: On STM32F4, there is no independent flag of end of sequence.       */
-  /*       The test of scan sequence on going is done either with scan        */
-  /*       sequence disabled or with end of conversion flag set to            */
-  /*       of end of sequence.                                                */
-  if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&
-     (hadc->Init.ContinuousConvMode == DISABLE)            &&
-     (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
-      HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )
-  {
-    /* Set ADC state */
-    CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);   
-    
-    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
-    { 
-      SET_BIT(hadc->State, HAL_ADC_STATE_READY);
-    }
-  }
-  
-  /* Return ADC state */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Poll for conversion event
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @param  EventType: the ADC event type.
-  *          This parameter can be one of the following values:
-  *            @arg ADC_AWD_EVENT: ADC Analog watch Dog event.
-  *            @arg ADC_OVR_EVENT: ADC Overrun event.
-  * @param  Timeout: Timeout value in millisecond.   
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
-{
-  uint32_t tickstart = 0U;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  assert_param(IS_ADC_EVENT_TYPE(EventType));
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  /* Check selected event flag */
-  while(!(__HAL_ADC_GET_FLAG(hadc,EventType)))
-  {
-    /* Check for the Timeout */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        /* Update ADC state machine to timeout */
-        SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
-        
-        /* Process unlocked */
-        __HAL_UNLOCK(hadc);
-        
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  
-  /* Analog watchdog (level out of window) event */
-  if(EventType == ADC_AWD_EVENT)
-  {
-    /* Set ADC state */
-    SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
-      
-    /* Clear ADC analog watchdog flag */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
-  }
-  /* Overrun event */
-  else
-  {
-    /* Set ADC state */
-    SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
-    /* Set ADC error code to overrun */
-    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
-    
-    /* Clear ADC overrun flag */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
-  }
-  
-  /* Return ADC state */
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  Enables the interrupt and starts ADC conversion of regular channels.
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
-{
-  __IO uint32_t counter = 0U;
-  
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
-  assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); 
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  /* Enable the ADC peripheral */
-  /* Check if ADC peripheral is disabled in order to enable it and wait during 
-  Tstab time the ADC's stabilization */
-  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
-  {  
-    /* Enable the Peripheral */
-    __HAL_ADC_ENABLE(hadc);
-    
-    /* Delay for ADC stabilization time */
-    /* Compute number of CPU cycles to wait for */
-    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
-    while(counter != 0U)
-    {
-      counter--;
-    }
-  }
-  
-  /* Start conversion if ADC is effectively enabled */
-  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
-  {
-    /* Set ADC state                                                          */
-    /* - Clear state bitfield related to regular group conversion results     */
-    /* - Set state bitfield related to regular group operation                */
-    ADC_STATE_CLR_SET(hadc->State,
-                      HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
-                      HAL_ADC_STATE_REG_BUSY);
-    
-    /* If conversions on group regular are also triggering group injected,    */
-    /* update ADC state.                                                      */
-    if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
-    {
-      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  
-    }
-    
-    /* State machine update: Check if an injected conversion is ongoing */
-    if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
-    {
-      /* Reset ADC error code fields related to conversions on group regular */
-      CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));         
-    }
-    else
-    {
-      /* Reset ADC all error code fields */
-      ADC_CLEAR_ERRORCODE(hadc);
-    }
-    
-    /* Process unlocked */
-    /* Unlock before starting ADC conversions: in case of potential           */
-    /* interruption, to let the process to ADC IRQ Handler.                   */
-    __HAL_UNLOCK(hadc);
-    
-    /* Clear regular group conversion flag and overrun flag */
-    /* (To ensure of no unknown state from potential previous ADC operations) */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
-    
-    /* Enable end of conversion interrupt for regular group */
-    __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
-    
-    /* Check if Multimode enabled */
-    if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
-    {
-      /* if no external trigger present enable software conversion of regular channels */
-      if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) 
-      {
-        /* Enable the selected ADC software conversion for regular group */
-        hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
-      }
-    }
-    else
-    {
-      /* if instance of handle correspond to ADC1 and  no external trigger present enable software conversion of regular channels */
-      if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
-      {
-        /* Enable the selected ADC software conversion for regular group */
-          hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
-      }
-    }
-  }
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disables the interrupt and stop ADC conversion of regular channels.
-  * 
-  * @note   Caution: This function will stop also injected channels.  
-  *
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  /* Stop potential conversion on going, on regular and injected groups */
-  /* Disable ADC peripheral */
-  __HAL_ADC_DISABLE(hadc);
-  
-  /* Check if ADC is effectively disabled */
-  if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
-  {
-  	/* Disable ADC end of conversion interrupt for regular group */
-    __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
-
-    /* Set ADC state */
-    ADC_STATE_CLR_SET(hadc->State,
-                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
-                      HAL_ADC_STATE_READY);
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handles ADC interrupt request  
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @retval None
-  */
-void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
-{
-  uint32_t tmp1 = 0U, tmp2 = 0U;
-  
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
-  assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
-  assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
-  
-  tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC);
-  tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC);
-  /* Check End of conversion flag for regular channels */
-  if(tmp1 && tmp2)
-  {
-    /* Update state machine on conversion status if not in error state */
-    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
-    {
-      /* Set ADC state */
-      SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 
-    }
-    
-    /* Determine whether any further conversion upcoming on group regular   */
-    /* by external trigger, continuous mode or scan sequence on going.      */
-    /* Note: On STM32F4, there is no independent flag of end of sequence.   */
-    /*       The test of scan sequence on going is done either with scan    */
-    /*       sequence disabled or with end of conversion flag set to        */
-    /*       of end of sequence.                                            */
-    if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&
-       (hadc->Init.ContinuousConvMode == DISABLE)            &&
-       (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || 
-        HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )
-    {
-      /* Disable ADC end of single conversion interrupt on group regular */
-      /* Note: Overrun interrupt was enabled with EOC interrupt in          */
-      /* HAL_ADC_Start_IT(), but is not disabled here because can be used   */
-      /* by overrun IRQ process below.                                      */
-      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
-      
-      /* Set ADC state */
-      CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
-      
-      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
-      {
-        SET_BIT(hadc->State, HAL_ADC_STATE_READY);
-      }
-    }
-    
-    /* Conversion complete callback */ 
-    HAL_ADC_ConvCpltCallback(hadc);
-    
-    /* Clear regular group conversion flag */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
-  }
-  
-  tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC);
-  tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC);                               
-  /* Check End of conversion flag for injected channels */
-  if(tmp1 && tmp2)
-  {
-    /* Update state machine on conversion status if not in error state */
-    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
-    {
-      /* Set ADC state */
-      SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
-    }
-
-    /* Determine whether any further conversion upcoming on group injected  */
-    /* by external trigger, scan sequence on going or by automatic injected */
-    /* conversion from group regular (same conditions as group regular      */
-    /* interruption disabling above).                                       */
-    if(ADC_IS_SOFTWARE_START_INJECTED(hadc)                    &&
-       (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL)  ||
-        HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)    ) &&
-       (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
-        (ADC_IS_SOFTWARE_START_REGULAR(hadc)       &&
-        (hadc->Init.ContinuousConvMode == DISABLE)   )       )   )
-    {
-      /* Disable ADC end of single conversion interrupt on group injected */
-      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
-      
-      /* Set ADC state */
-      CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);   
-
-      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
-      { 
-        SET_BIT(hadc->State, HAL_ADC_STATE_READY);
-      }
-    }
-
-    /* Conversion complete callback */ 
-    HAL_ADCEx_InjectedConvCpltCallback(hadc);
-    
-    /* Clear injected group conversion flag */
-    __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
-  }
-  
-  tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD);
-  tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD);                          
-  /* Check Analog watchdog flag */
-  if(tmp1 && tmp2)
-  {
-    if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))
-    {
-      /* Set ADC state */
-      SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
-      
-      /* Level out of window callback */ 
-      HAL_ADC_LevelOutOfWindowCallback(hadc);
-      
-      /* Clear the ADC analog watchdog flag */
-      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
-    }
-  }
-  
-  tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR);
-  tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR);
-  /* Check Overrun flag */
-  if(tmp1 && tmp2)
-  {
-    /* Note: On STM32F4, ADC overrun can be set through other parameters    */
-    /*       refer to description of parameter "EOCSelection" for more      */
-    /*       details.                                                       */
-    
-    /* Set ADC error code to overrun */
-    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
-    
-    /* Clear ADC overrun flag */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
-    
-    /* Error callback */ 
-    HAL_ADC_ErrorCallback(hadc);
-    
-    /* Clear the Overrun flag */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
-  }
-}
-
-/**
-  * @brief  Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral  
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @param  pData: The destination Buffer address.
-  * @param  Length: The length of data to be transferred from ADC peripheral to memory.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
-{
-  __IO uint32_t counter = 0U;
-  
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
-  assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); 
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  /* Enable the ADC peripheral */
-  /* Check if ADC peripheral is disabled in order to enable it and wait during 
-  Tstab time the ADC's stabilization */
-  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
-  {  
-    /* Enable the Peripheral */
-    __HAL_ADC_ENABLE(hadc);
-    
-    /* Delay for ADC stabilization time */
-    /* Compute number of CPU cycles to wait for */
-    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
-    while(counter != 0U)
-    {
-      counter--;
-    }
-  }
-  
-  /* Start conversion if ADC is effectively enabled */
-  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
-  {
-    /* Set ADC state                                                          */
-    /* - Clear state bitfield related to regular group conversion results     */
-    /* - Set state bitfield related to regular group operation                */
-    ADC_STATE_CLR_SET(hadc->State,
-                      HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
-                      HAL_ADC_STATE_REG_BUSY);
-    
-    /* If conversions on group regular are also triggering group injected,    */
-    /* update ADC state.                                                      */
-    if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
-    {
-      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  
-    }
-    
-    /* State machine update: Check if an injected conversion is ongoing */
-    if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
-    {
-      /* Reset ADC error code fields related to conversions on group regular */
-      CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));         
-    }
-    else
-    {
-      /* Reset ADC all error code fields */
-      ADC_CLEAR_ERRORCODE(hadc);
-    }
-    
-    /* Process unlocked */
-    /* Unlock before starting ADC conversions: in case of potential           */
-    /* interruption, to let the process to ADC IRQ Handler.                   */
-    __HAL_UNLOCK(hadc);   
-
-    /* Set the DMA transfer complete callback */
-    hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
-
-    /* Set the DMA half transfer complete callback */
-    hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
-    
-    /* Set the DMA error callback */
-    hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
-
-    
-    /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */
-    /* start (in case of SW start):                                           */
-    
-    /* Clear regular group conversion flag and overrun flag */
-    /* (To ensure of no unknown state from potential previous ADC operations) */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
-
-    /* Enable ADC overrun interrupt */
-    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
-    
-    /* Enable ADC DMA mode */
-    hadc->Instance->CR2 |= ADC_CR2_DMA;
-    
-    /* Start the DMA channel */
-    HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
-    
-    /* Check if Multimode enabled */
-    if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
-    {
-      /* if no external trigger present enable software conversion of regular channels */
-      if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) 
-      {
-        /* Enable the selected ADC software conversion for regular group */
-        hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
-      }
-    }
-    else
-    {
-      /* if instance of handle correspond to ADC1 and  no external trigger present enable software conversion of regular channels */
-      if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
-      {
-        /* Enable the selected ADC software conversion for regular group */
-          hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
-      }
-    }
-  }
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disables ADC DMA (Single-ADC mode) and disables ADC peripheral    
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  /* Stop potential conversion on going, on regular and injected groups */
-  /* Disable ADC peripheral */
-  __HAL_ADC_DISABLE(hadc);
-  
-  /* Check if ADC is effectively disabled */
-  if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
-  {
-    /* Disable the selected ADC DMA mode */
-    hadc->Instance->CR2 &= ~ADC_CR2_DMA;
-    
-    /* Disable the DMA channel (in case of DMA in circular mode or stop while */
-    /* DMA transfer is on going)                                              */
-    tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
-    
-    /* Disable ADC overrun interrupt */
-    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
-    
-    /* Set ADC state */
-    ADC_STATE_CLR_SET(hadc->State,
-                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
-                      HAL_ADC_STATE_READY);
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmp_hal_status;
-}
-
-/**
-  * @brief  Gets the converted value from data register of regular channel.
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @retval Converted value
-  */
-uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
-{       
-  /* Return the selected ADC converted value */ 
-  return hadc->Instance->DR;
-}
-
-/**
-  * @brief  Regular conversion complete callback in non blocking mode 
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @retval None
-  */
-__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_ADC_ConvCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Regular conversion half DMA transfer callback in non blocking mode 
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @retval None
-  */
-__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_ADC_ConvHalfCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Analog watchdog callback in non blocking mode 
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @retval None
-  */
-__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_ADC_LevelOoutOfWindowCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Error ADC callback.
-  * @note   In case of error due to overrun when using ADC with DMA transfer 
-  *         (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
-  *         - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
-  *         - If needed, restart a new ADC conversion using function
-  *           "HAL_ADC_Start_DMA()"
-  *           (this function is also clearing overrun flag)
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @retval None
-  */
-__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_ADC_ErrorCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-  
-/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
- *  @brief   	Peripheral Control functions 
- *
-@verbatim   
- ===============================================================================
-             ##### Peripheral Control functions #####
- ===============================================================================  
-    [..]  This section provides functions allowing to:
-      (+) Configure regular channels. 
-      (+) Configure injected channels.
-      (+) Configure multimode.
-      (+) Configure the analog watch dog.
-      
-@endverbatim
-  * @{
-  */
-
-  /**
-  * @brief  Configures for the selected ADC regular channel its corresponding
-  *         rank in the sequencer and its sample time.
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @param  sConfig: ADC configuration structure. 
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
-{
-  __IO uint32_t counter = 0U;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_CHANNEL(sConfig->Channel));
-  assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
-  assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-    
-  /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
-  if (sConfig->Channel > ADC_CHANNEL_9)
-  {
-    /* Clear the old sample time */
-    hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);
-    
-    /* Set the new sample time */
-    hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);
-  }
-  else /* ADC_Channel include in ADC_Channel_[0..9] */
-  {
-    /* Clear the old sample time */
-    hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel);
-    
-    /* Set the new sample time */
-    hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel);
-  }
-  
-  /* For Rank 1 to 6 */
-  if (sConfig->Rank < 7U)
-  {
-    /* Clear the old SQx bits for the selected rank */
-    hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank);
-    
-    /* Set the SQx bits for the selected rank */
-    hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank);
-  }
-  /* For Rank 7 to 12 */
-  else if (sConfig->Rank < 13U)
-  {
-    /* Clear the old SQx bits for the selected rank */
-    hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank);
-    
-    /* Set the SQx bits for the selected rank */
-    hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank);
-  }
-  /* For Rank 13 to 16 */
-  else
-  {
-    /* Clear the old SQx bits for the selected rank */
-    hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank);
-    
-    /* Set the SQx bits for the selected rank */
-    hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);
-  }
-  
-  /* if ADC1 Channel_18 is selected enable VBAT Channel */
-  if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT))
-  {
-    /* Enable the VBAT channel*/
-    ADC->CCR |= ADC_CCR_VBATE;
-  }
-  
-  /* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */
-  if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT)))
-  {
-    /* Enable the TSVREFE channel*/
-    ADC->CCR |= ADC_CCR_TSVREFE;
-    
-    if((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
-    {
-      /* Delay for temperature sensor stabilization time */
-      /* Compute number of CPU cycles to wait for */
-      counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
-      while(counter != 0U)
-      {
-        counter--;
-      }
-    }
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the analog watchdog.
-  * @note Analog watchdog thresholds can be modified while ADC conversion
-  * is on going.
-  * In this case, some constraints must be taken into account:
-  * The programmed threshold values are effective from the next
-  * ADC EOC (end of unitary conversion).
-  * Considering that registers write delay may happen due to
-  * bus activity, this might cause an uncertainty on the
-  * effective timing of the new programmed threshold values.
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @param  AnalogWDGConfig : pointer to an ADC_AnalogWDGConfTypeDef structure 
-  *         that contains the configuration information of ADC analog watchdog.
-  * @retval HAL status	  
-  */
-HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
-{
-#ifdef USE_FULL_ASSERT  
-  uint32_t tmp = 0U;
-#endif /* USE_FULL_ASSERT  */  
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ANALOG_WATCHDOG(AnalogWDGConfig->WatchdogMode));
-  assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
-  assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
-
-#ifdef USE_FULL_ASSERT  
-  tmp = ADC_GET_RESOLUTION(hadc);
-  assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->HighThreshold));
-  assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->LowThreshold));
-#endif /* USE_FULL_ASSERT  */
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  if(AnalogWDGConfig->ITMode == ENABLE)
-  {
-    /* Enable the ADC Analog watchdog interrupt */
-    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
-  }
-  else
-  {
-    /* Disable the ADC Analog watchdog interrupt */
-    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
-  }
-  
-  /* Clear AWDEN, JAWDEN and AWDSGL bits */
-  hadc->Instance->CR1 &=  ~(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN | ADC_CR1_AWDEN);
-  
-  /* Set the analog watchdog enable mode */
-  hadc->Instance->CR1 |= AnalogWDGConfig->WatchdogMode;
-  
-  /* Set the high threshold */
-  hadc->Instance->HTR = AnalogWDGConfig->HighThreshold;
-  
-  /* Set the low threshold */
-  hadc->Instance->LTR = AnalogWDGConfig->LowThreshold;
-  
-  /* Clear the Analog watchdog channel select bits */
-  hadc->Instance->CR1 &= ~ADC_CR1_AWDCH;
-  
-  /* Set the Analog watchdog channel */
-  hadc->Instance->CR1 |= (uint32_t)((uint16_t)(AnalogWDGConfig->Channel));
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Exported_Functions_Group4 ADC Peripheral State functions
- *  @brief   ADC Peripheral State functions 
- *
-@verbatim   
- ===============================================================================
-            ##### Peripheral State and errors functions #####
- ===============================================================================  
-    [..]
-    This subsection provides functions allowing to
-      (+) Check the ADC state
-      (+) Check the ADC Error
-         
-@endverbatim
-  * @{
-  */
-  
-/**
-  * @brief  return the ADC state
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @retval HAL state
-  */
-uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
-{
-  /* Return ADC state */
-  return hadc->State;
-}
-
-/**
-  * @brief  Return the ADC error code
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @retval ADC Error Code
-  */
-uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
-{
-  return hadc->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup ADC_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Initializes the ADCx peripheral according to the specified parameters 
-  *         in the ADC_InitStruct without initializing the ADC MSP.       
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.  
-  * @retval None
-  */
-static void ADC_Init(ADC_HandleTypeDef* hadc)
-{
-  /* Set ADC parameters */
-  /* Set the ADC clock prescaler */
-  ADC->CCR &= ~(ADC_CCR_ADCPRE);
-  ADC->CCR |=  hadc->Init.ClockPrescaler;
-  
-  /* Set ADC scan mode */
-  hadc->Instance->CR1 &= ~(ADC_CR1_SCAN);
-  hadc->Instance->CR1 |=  ADC_CR1_SCANCONV(hadc->Init.ScanConvMode);
-  
-  /* Set ADC resolution */
-  hadc->Instance->CR1 &= ~(ADC_CR1_RES);
-  hadc->Instance->CR1 |=  hadc->Init.Resolution;
-  
-  /* Set ADC data alignment */
-  hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN);
-  hadc->Instance->CR2 |= hadc->Init.DataAlign;
-  
-  /* Enable external trigger if trigger selection is different of software  */
-  /* start.                                                                 */
-  /* Note: This configuration keeps the hardware feature of parameter       */
-  /*       ExternalTrigConvEdge "trigger edge none" equivalent to           */
-  /*       software start.                                                  */
-  if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
-  {
-    /* Select external trigger to start conversion */
-    hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
-    hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv;
-    
-    /* Select external trigger polarity */
-    hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
-    hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge;
-  }
-  else
-  {
-    /* Reset the external trigger */
-    hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
-    hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
-  }
-  
-  /* Enable or disable ADC continuous conversion mode */
-  hadc->Instance->CR2 &= ~(ADC_CR2_CONT);
-  hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode);
-  
-  if(hadc->Init.DiscontinuousConvMode != DISABLE)
-  {
-    assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion));
-  
-    /* Enable the selected ADC regular discontinuous mode */
-    hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN;
-    
-    /* Set the number of channels to be converted in discontinuous mode */
-    hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM);
-    hadc->Instance->CR1 |=  ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion);
-  }
-  else
-  {
-    /* Disable the selected ADC regular discontinuous mode */
-    hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN);
-  }
-  
-  /* Set ADC number of conversion */
-  hadc->Instance->SQR1 &= ~(ADC_SQR1_L);
-  hadc->Instance->SQR1 |=  ADC_SQR1(hadc->Init.NbrOfConversion);
-  
-  /* Enable or disable ADC DMA continuous request */
-  hadc->Instance->CR2 &= ~(ADC_CR2_DDS);
-  hadc->Instance->CR2 |= ADC_CR2_DMAContReq(hadc->Init.DMAContinuousRequests);
-  
-  /* Enable or disable ADC end of conversion selection */
-  hadc->Instance->CR2 &= ~(ADC_CR2_EOCS);
-  hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection);
-}
-
-/**
-  * @brief  DMA transfer complete callback. 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)   
-{
-  /* Retrieve ADC handle corresponding to current DMA handle */
-  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  /* Update state machine on conversion status if not in error state */
-  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
-  {
-    /* Update ADC state machine */
-    SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
-    
-    /* Determine whether any further conversion upcoming on group regular   */
-    /* by external trigger, continuous mode or scan sequence on going.      */
-    /* Note: On STM32F4, there is no independent flag of end of sequence.   */
-    /*       The test of scan sequence on going is done either with scan    */
-    /*       sequence disabled or with end of conversion flag set to        */
-    /*       of end of sequence.                                            */
-    if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&
-       (hadc->Init.ContinuousConvMode == DISABLE)            &&
-       (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || 
-        HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )
-    {
-      /* Disable ADC end of single conversion interrupt on group regular */
-      /* Note: Overrun interrupt was enabled with EOC interrupt in          */
-      /* HAL_ADC_Start_IT(), but is not disabled here because can be used   */
-      /* by overrun IRQ process below.                                      */
-      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
-      
-      /* Set ADC state */
-      CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);   
-      
-      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
-      {
-        SET_BIT(hadc->State, HAL_ADC_STATE_READY);
-      }
-    }
-    
-    /* Conversion complete callback */
-    HAL_ADC_ConvCpltCallback(hadc);
-  }
-  else
-  {
-    /* Call DMA error callback */
-    hadc->DMA_Handle->XferErrorCallback(hdma);
-  }
-}
-
-/**
-  * @brief  DMA half transfer complete callback. 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)   
-{
-  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  /* Conversion complete callback */
-  HAL_ADC_ConvHalfCpltCallback(hadc); 
-}
-
-/**
-  * @brief  DMA error callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void ADC_DMAError(DMA_HandleTypeDef *hdma)   
-{
-  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  hadc->State= HAL_ADC_STATE_ERROR_DMA;
-  /* Set ADC error code to DMA error */
-  hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
-  HAL_ADC_ErrorCallback(hadc); 
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_ADC_MODULE_ENABLED */
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_adc_ex.c b/stmhal/hal/f4/src/stm32f4xx_hal_adc_ex.c
deleted file mode 100644
index 81f1826c3b..0000000000
--- a/stmhal/hal/f4/src/stm32f4xx_hal_adc_ex.c
+++ /dev/null
@@ -1,1069 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_adc_ex.c
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   This file provides firmware functions to manage the following 
-  *          functionalities of the ADC extension peripheral:
-  *           + Extended features functions
-  *         
-  @verbatim
-  ==============================================================================
-                    ##### How to use this driver #####
-  ==============================================================================
-    [..]
-    (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():
-       (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()
-       (##) ADC pins configuration
-             (+++) Enable the clock for the ADC GPIOs using the following function:
-                   __HAL_RCC_GPIOx_CLK_ENABLE()  
-             (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init() 
-       (##) In case of using interrupts (e.g. HAL_ADC_Start_IT())
-             (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()
-             (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()
-             (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()
-      (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())
-             (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()
-             (+++) Configure and enable two DMA streams stream for managing data
-                 transfer from peripheral to memory (output stream)
-             (+++) Associate the initialized DMA handle to the ADC DMA handle
-                 using  __HAL_LINKDMA()
-             (+++) Configure the priority and enable the NVIC for the transfer complete
-                 interrupt on the two DMA Streams. The output stream should have higher
-                 priority than the input stream.
-     (#) Configure the ADC Prescaler, conversion resolution and data alignment 
-         using the HAL_ADC_Init() function. 
-  
-     (#) Configure the ADC Injected channels group features, use HAL_ADC_Init()
-         and HAL_ADC_ConfigChannel() functions.
-         
-     (#) Three operation modes are available within this driver :     
-  
-     *** Polling mode IO operation ***
-     =================================
-     [..]    
-       (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart() 
-       (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage
-           user can specify the value of timeout according to his end application      
-       (+) To read the ADC converted values, use the HAL_ADCEx_InjectedGetValue() function.
-       (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop()
-  
-     *** Interrupt mode IO operation ***    
-     ===================================
-     [..]    
-       (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_IT() 
-       (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine
-       (+) At ADC end of conversion HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can 
-            add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback 
-       (+) In case of ADC Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can 
-            add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback
-       (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_IT()
-       
-            
-     *** DMA mode IO operation ***    
-     ==============================
-     [..]    
-       (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_DMA(), at this stage the user specify the length 
-           of data to be transferred at each end of conversion 
-       (+) At The end of data transfer ba HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can 
-            add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback 
-       (+) In case of transfer Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can 
-            add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback
-        (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_DMA()
-        
-     *** Multi mode ADCs Regular channels configuration ***
-     ======================================================
-     [..]        
-       (+) Select the Multi mode ADC regular channels features (dual or triple mode)  
-          and configure the DMA mode using HAL_ADCEx_MultiModeConfigChannel() functions. 
-       (+) Start the ADC peripheral using HAL_ADCEx_MultiModeStart_DMA(), at this stage the user specify the length 
-           of data to be transferred at each end of conversion           
-       (+) Read the ADCs converted values using the HAL_ADCEx_MultiModeGetValue() function.
-  
-  
-    @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup ADCEx ADCEx
-  * @brief ADC Extended driver modules
-  * @{
-  */ 
-
-#ifdef HAL_ADC_MODULE_ENABLED
-    
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/ 
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @addtogroup ADCEx_Private_Functions
-  * @{
-  */
-/* Private function prototypes -----------------------------------------------*/
-static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma);
-static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma);
-static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma); 
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup ADCEx_Exported_Functions ADC Exported Functions
-  * @{
-  */
-
-/** @defgroup ADCEx_Exported_Functions_Group1  Extended features functions 
-  *  @brief    Extended features functions  
-  *
-@verbatim   
- ===============================================================================
-                 ##### Extended features functions #####
- ===============================================================================  
-    [..]  This section provides functions allowing to:
-      (+) Start conversion of injected channel.
-      (+) Stop conversion of injected channel.
-      (+) Start multimode and enable DMA transfer.
-      (+) Stop multimode and disable DMA transfer.
-      (+) Get result of injected channel conversion.
-      (+) Get result of multimode conversion.
-      (+) Configure injected channels.
-      (+) Configure multimode.
-               
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables the selected ADC software start conversion of the injected channels.
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
-{
-  __IO uint32_t counter = 0U;
-  uint32_t tmp1 = 0U, tmp2 = 0U;
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  /* Enable the ADC peripheral */
-  
-  /* Check if ADC peripheral is disabled in order to enable it and wait during 
-     Tstab time the ADC's stabilization */
-  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
-  {  
-    /* Enable the Peripheral */
-    __HAL_ADC_ENABLE(hadc);
-    
-    /* Delay for ADC stabilization time */
-    /* Compute number of CPU cycles to wait for */
-    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
-    while(counter != 0U)
-    {
-      counter--;
-    }
-  }
-  
-  /* Start conversion if ADC is effectively enabled */
-  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
-  {
-    /* Set ADC state                                                          */
-    /* - Clear state bitfield related to injected group conversion results    */
-    /* - Set state bitfield related to injected operation                     */
-    ADC_STATE_CLR_SET(hadc->State,
-                      HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
-                      HAL_ADC_STATE_INJ_BUSY);
-    
-    /* Check if a regular conversion is ongoing */
-    /* Note: On this device, there is no ADC error code fields related to     */
-    /*       conversions on group injected only. In case of conversion on     */
-    /*       going on group regular, no error code is reset.                  */
-    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
-    {
-      /* Reset ADC all error code fields */
-      ADC_CLEAR_ERRORCODE(hadc);
-    }
-    
-    /* Process unlocked */
-    /* Unlock before starting ADC conversions: in case of potential           */
-    /* interruption, to let the process to ADC IRQ Handler.                   */
-    __HAL_UNLOCK(hadc);
-    
-    /* Clear injected group conversion flag */
-    /* (To ensure of no unknown state from potential previous ADC operations) */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
-    
-    /* Check if Multimode enabled */
-    if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
-    {
-      tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
-      tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
-      if(tmp1 && tmp2)
-      {
-        /* Enable the selected ADC software conversion for injected group */
-        hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
-      }
-    }
-    else
-    {
-      tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
-      tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
-      if((hadc->Instance == ADC1) && tmp1 && tmp2)  
-      {
-        /* Enable the selected ADC software conversion for injected group */
-        hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
-      }
-    }
-  }
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enables the interrupt and starts ADC conversion of injected channels.
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  *
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
-{
-  __IO uint32_t counter = 0U;
-  uint32_t tmp1 = 0U, tmp2 = 0U;
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  /* Enable the ADC peripheral */
-  
-  /* Check if ADC peripheral is disabled in order to enable it and wait during 
-     Tstab time the ADC's stabilization */
-  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
-  {  
-    /* Enable the Peripheral */
-    __HAL_ADC_ENABLE(hadc);
-    
-    /* Delay for ADC stabilization time */
-    /* Compute number of CPU cycles to wait for */
-    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
-    while(counter != 0U)
-    {
-      counter--;
-    }
-  }
-  
-  /* Start conversion if ADC is effectively enabled */
-  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
-  {
-    /* Set ADC state                                                          */
-    /* - Clear state bitfield related to injected group conversion results    */
-    /* - Set state bitfield related to injected operation                     */
-    ADC_STATE_CLR_SET(hadc->State,
-                      HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
-                      HAL_ADC_STATE_INJ_BUSY);
-    
-    /* Check if a regular conversion is ongoing */
-    /* Note: On this device, there is no ADC error code fields related to     */
-    /*       conversions on group injected only. In case of conversion on     */
-    /*       going on group regular, no error code is reset.                  */
-    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
-    {
-      /* Reset ADC all error code fields */
-      ADC_CLEAR_ERRORCODE(hadc);
-    }
-    
-    /* Process unlocked */
-    /* Unlock before starting ADC conversions: in case of potential           */
-    /* interruption, to let the process to ADC IRQ Handler.                   */
-    __HAL_UNLOCK(hadc);
-    
-    /* Clear injected group conversion flag */
-    /* (To ensure of no unknown state from potential previous ADC operations) */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
-    
-    /* Enable end of conversion interrupt for injected channels */
-    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
-    
-    /* Check if Multimode enabled */
-    if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
-    {
-      tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
-      tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
-      if(tmp1 && tmp2)
-      {
-        /* Enable the selected ADC software conversion for injected group */
-        hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
-      }
-    }
-    else
-    {
-      tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
-      tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
-      if((hadc->Instance == ADC1) && tmp1 && tmp2)  
-      {
-        /* Enable the selected ADC software conversion for injected group */
-        hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
-      }
-    }
-  }
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stop conversion of injected channels. Disable ADC peripheral if
-  *         no regular conversion is on going.
-  * @note   If ADC must be disabled and if conversion is on going on 
-  *         regular group, function HAL_ADC_Stop must be used to stop both
-  *         injected and regular groups, and disable the ADC.
-  * @note   If injected group mode auto-injection is enabled,
-  *         function HAL_ADC_Stop must be used.
-  * @note   In case of auto-injection mode, HAL_ADC_Stop must be used.
-  * @param  hadc: ADC handle
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
-  /* Process locked */
-  __HAL_LOCK(hadc);
-    
-  /* Stop potential conversion and disable ADC peripheral                     */
-  /* Conditioned to:                                                          */
-  /* - No conversion on the other group (regular group) is intended to        */
-  /*   continue (injected and regular groups stop conversion and ADC disable  */
-  /*   are common)                                                            */
-  /* - In case of auto-injection mode, HAL_ADC_Stop must be used.             */
-  if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET)  &&
-     HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )
-  {
-    /* Stop potential conversion on going, on regular and injected groups */
-    /* Disable ADC peripheral */
-    __HAL_ADC_DISABLE(hadc);
-    
-    /* Check if ADC is effectively disabled */
-    if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
-    {
-      /* Set ADC state */
-      ADC_STATE_CLR_SET(hadc->State,
-                        HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
-                        HAL_ADC_STATE_READY);
-    }
-  }
-  else
-  {
-    /* Update ADC state machine to error */
-    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-      
-    tmp_hal_status = HAL_ERROR;
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmp_hal_status;
-}
-
-/**
-  * @brief  Poll for injected conversion complete
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @param  Timeout: Timeout value in millisecond.  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
-{
-  uint32_t tickstart = 0U;
-
-  /* Get tick */ 
-  tickstart = HAL_GetTick();
-
-  /* Check End of conversion flag */
-  while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)))
-  {
-    /* Check for the Timeout */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        hadc->State= HAL_ADC_STATE_TIMEOUT;
-        /* Process unlocked */
-        __HAL_UNLOCK(hadc);
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  
-  /* Clear injected group conversion flag */
-  __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC);
-    
-  /* Update ADC state machine */
-  SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
-  
-  /* Determine whether any further conversion upcoming on group injected      */
-  /* by external trigger, continuous mode or scan sequence on going.          */
-  /* Note: On STM32F4, there is no independent flag of end of sequence.       */
-  /*       The test of scan sequence on going is done either with scan        */
-  /*       sequence disabled or with end of conversion flag set to            */
-  /*       of end of sequence.                                                */
-  if(ADC_IS_SOFTWARE_START_INJECTED(hadc)                    &&
-     (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL)  ||
-      HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)    ) &&
-     (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
-      (ADC_IS_SOFTWARE_START_REGULAR(hadc)       &&
-      (hadc->Init.ContinuousConvMode == DISABLE)   )       )   )
-  {
-    /* Set ADC state */
-    CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
-    
-    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
-    { 
-      SET_BIT(hadc->State, HAL_ADC_STATE_READY);
-    }
-  }
-  
-  /* Return ADC state */
-  return HAL_OK;
-}      
-  
-/**
-  * @brief  Stop conversion of injected channels, disable interruption of 
-  *         end-of-conversion. Disable ADC peripheral if no regular conversion
-  *         is on going.
-  * @note   If ADC must be disabled and if conversion is on going on 
-  *         regular group, function HAL_ADC_Stop must be used to stop both
-  *         injected and regular groups, and disable the ADC.
-  * @note   If injected group mode auto-injection is enabled,
-  *         function HAL_ADC_Stop must be used.
-  * @param  hadc: ADC handle
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
-  /* Process locked */
-  __HAL_LOCK(hadc);
-    
-  /* Stop potential conversion and disable ADC peripheral                     */
-  /* Conditioned to:                                                          */
-  /* - No conversion on the other group (regular group) is intended to        */
-  /*   continue (injected and regular groups stop conversion and ADC disable  */
-  /*   are common)                                                            */
-  /* - In case of auto-injection mode, HAL_ADC_Stop must be used.             */ 
-  if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET)  &&
-     HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )
-  {
-    /* Stop potential conversion on going, on regular and injected groups */
-    /* Disable ADC peripheral */
-    __HAL_ADC_DISABLE(hadc);
-    
-    /* Check if ADC is effectively disabled */
-    if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
-    {
-      /* Disable ADC end of conversion interrupt for injected channels */
-      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
-      
-      /* Set ADC state */
-      ADC_STATE_CLR_SET(hadc->State,
-                        HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
-                        HAL_ADC_STATE_READY);
-    }
-  }
-  else
-  {
-    /* Update ADC state machine to error */
-    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-      
-    tmp_hal_status = HAL_ERROR;
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmp_hal_status;
-}
-
-/**
-  * @brief  Gets the converted value from data register of injected channel.
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @param  InjectedRank: the ADC injected rank.
-  *          This parameter can be one of the following values:
-  *            @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
-  *            @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
-  *            @arg ADC_INJECTED_RANK_3: Injected Channel3 selected
-  *            @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
-  * @retval None
-  */
-uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
-{
-  __IO uint32_t tmp = 0U;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
-  
-  /* Clear injected group conversion flag to have similar behaviour as        */
-  /* regular group: reading data register also clears end of conversion flag. */
-  __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
-  
-  /* Return the selected ADC converted value */ 
-  switch(InjectedRank)
-  {  
-    case ADC_INJECTED_RANK_4:
-    {
-      tmp =  hadc->Instance->JDR4;
-    }  
-    break;
-    case ADC_INJECTED_RANK_3: 
-    {  
-      tmp =  hadc->Instance->JDR3;
-    }  
-    break;
-    case ADC_INJECTED_RANK_2: 
-    {  
-      tmp =  hadc->Instance->JDR2;
-    }
-    break;
-    case ADC_INJECTED_RANK_1:
-    {
-      tmp =  hadc->Instance->JDR1;
-    }
-    break;
-    default:
-    break;  
-  }
-  return tmp;
-}
-
-/**
-  * @brief  Enables ADC DMA request after last transfer (Multi-ADC mode) and enables ADC peripheral
-  * 
-  * @note   Caution: This function must be used only with the ADC master.  
-  *
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @param  pData:   Pointer to buffer in which transferred from ADC peripheral to memory will be stored. 
-  * @param  Length:  The length of data to be transferred from ADC peripheral to memory.  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
-{
-  __IO uint32_t counter = 0U;
-  
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
-  assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
-  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  /* Check if ADC peripheral is disabled in order to enable it and wait during 
-     Tstab time the ADC's stabilization */
-  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
-  {  
-    /* Enable the Peripheral */
-    __HAL_ADC_ENABLE(hadc);
-    
-    /* Delay for temperature sensor stabilization time */
-    /* Compute number of CPU cycles to wait for */
-    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
-    while(counter != 0U)
-    {
-      counter--;
-    }
-  }
-  
-  /* Start conversion if ADC is effectively enabled */
-  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
-  {
-    /* Set ADC state                                                          */
-    /* - Clear state bitfield related to regular group conversion results     */
-    /* - Set state bitfield related to regular group operation                */
-    ADC_STATE_CLR_SET(hadc->State,
-                      HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
-                      HAL_ADC_STATE_REG_BUSY);
-    
-    /* If conversions on group regular are also triggering group injected,    */
-    /* update ADC state.                                                      */
-    if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
-    {
-      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  
-    }
-    
-    /* State machine update: Check if an injected conversion is ongoing */
-    if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
-    {
-      /* Reset ADC error code fields related to conversions on group regular */
-      CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));         
-    }
-    else
-    {
-      /* Reset ADC all error code fields */
-      ADC_CLEAR_ERRORCODE(hadc);
-    }
-    
-    /* Process unlocked */
-    /* Unlock before starting ADC conversions: in case of potential           */
-    /* interruption, to let the process to ADC IRQ Handler.                   */
-    __HAL_UNLOCK(hadc);
-    
-    /* Set the DMA transfer complete callback */
-    hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt;
-    
-    /* Set the DMA half transfer complete callback */
-    hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt;
-    
-    /* Set the DMA error callback */
-    hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ;
-    
-    /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */
-    /* start (in case of SW start):                                           */
-    
-    /* Clear regular group conversion flag and overrun flag */
-    /* (To ensure of no unknown state from potential previous ADC operations) */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
-
-    /* Enable ADC overrun interrupt */
-    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
-    
-    if (hadc->Init.DMAContinuousRequests != DISABLE)
-    {
-      /* Enable the selected ADC DMA request after last transfer */
-      ADC->CCR |= ADC_CCR_DDS;
-    }
-    else
-    {
-      /* Disable the selected ADC EOC rising on each regular channel conversion */
-      ADC->CCR &= ~ADC_CCR_DDS;
-    }
-    
-    /* Enable the DMA Stream */
-    HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&ADC->CDR, (uint32_t)pData, Length);
-    
-    /* if no external trigger present enable software conversion of regular channels */
-    if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) 
-    {
-      /* Enable the selected ADC software conversion for regular group */
-      hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
-    }
-  }
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disables ADC DMA (multi-ADC mode) and disables ADC peripheral    
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  /* Stop potential conversion on going, on regular and injected groups */
-  /* Disable ADC peripheral */
-  __HAL_ADC_DISABLE(hadc);
-  
-  /* Check if ADC is effectively disabled */
-  if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
-  {
-    /* Disable the selected ADC DMA mode for multimode */
-    ADC->CCR &= ~ADC_CCR_DDS;
-    
-    /* Disable the DMA channel (in case of DMA in circular mode or stop while */
-    /* DMA transfer is on going)                                              */
-    tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
-    
-    /* Disable ADC overrun interrupt */
-    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
-    
-    /* Set ADC state */
-    ADC_STATE_CLR_SET(hadc->State,
-                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
-                      HAL_ADC_STATE_READY);
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmp_hal_status;
-}
-
-/**
-  * @brief  Returns the last ADC1, ADC2 and ADC3 regular conversions results 
-  *         data in the selected multi mode.
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @retval The converted data value.
-  */
-uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
-{
-  /* Return the multi mode conversion value */
-  return ADC->CDR;
-}
-
-/**
-  * @brief  Injected conversion complete callback in non blocking mode 
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @retval None
-  */
-__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_ADC_InjectedConvCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Configures for the selected ADC injected channel its corresponding
-  *         rank in the sequencer and its sample time.
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @param  sConfigInjected: ADC configuration structure for injected channel. 
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
-{
-  
-#ifdef USE_FULL_ASSERT  
-  uint32_t tmp = 0U;
-#endif /* USE_FULL_ASSERT  */
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
-  assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
-  assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
-  assert_param(IS_ADC_EXT_INJEC_TRIG(sConfigInjected->ExternalTrigInjecConv));
-  assert_param(IS_ADC_INJECTED_LENGTH(sConfigInjected->InjectedNbrOfConversion));
-  assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
-  assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
-
-#ifdef USE_FULL_ASSERT
-  tmp = ADC_GET_RESOLUTION(hadc);
-  assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset));
-#endif /* USE_FULL_ASSERT  */
-
-  if(sConfigInjected->ExternalTrigInjecConvEdge != ADC_INJECTED_SOFTWARE_START)
-  {
-    assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
-  }
-
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
-  if (sConfigInjected->InjectedChannel > ADC_CHANNEL_9)
-  {
-    /* Clear the old sample time */
-    hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel);
-    
-    /* Set the new sample time */
-    hadc->Instance->SMPR1 |= ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
-  }
-  else /* ADC_Channel include in ADC_Channel_[0..9] */
-  {
-    /* Clear the old sample time */
-    hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel);
-    
-    /* Set the new sample time */
-    hadc->Instance->SMPR2 |= ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
-  }
-  
-  /*---------------------------- ADCx JSQR Configuration -----------------*/
-  hadc->Instance->JSQR &= ~(ADC_JSQR_JL);
-  hadc->Instance->JSQR |=  ADC_SQR1(sConfigInjected->InjectedNbrOfConversion);
-  
-  /* Rank configuration */
-  
-  /* Clear the old SQx bits for the selected rank */
-  hadc->Instance->JSQR &= ~ADC_JSQR(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);
-   
-  /* Set the SQx bits for the selected rank */
-  hadc->Instance->JSQR |= ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);
-
-  /* Enable external trigger if trigger selection is different of software  */
-  /* start.                                                                 */
-  /* Note: This configuration keeps the hardware feature of parameter       */
-  /*       ExternalTrigConvEdge "trigger edge none" equivalent to           */
-  /*       software start.                                                  */ 
-  if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
-  {  
-    /* Select external trigger to start conversion */
-    hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
-    hadc->Instance->CR2 |=  sConfigInjected->ExternalTrigInjecConv;
-    
-    /* Select external trigger polarity */
-    hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);
-    hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge;
-  }
-  else
-  {
-    /* Reset the external trigger */
-    hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
-    hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);  
-  }
-  
-  if (sConfigInjected->AutoInjectedConv != DISABLE)
-  {
-    /* Enable the selected ADC automatic injected group conversion */
-    hadc->Instance->CR1 |= ADC_CR1_JAUTO;
-  }
-  else
-  {
-    /* Disable the selected ADC automatic injected group conversion */
-    hadc->Instance->CR1 &= ~(ADC_CR1_JAUTO);
-  }
-  
-  if (sConfigInjected->InjectedDiscontinuousConvMode != DISABLE)
-  {
-    /* Enable the selected ADC injected discontinuous mode */
-    hadc->Instance->CR1 |= ADC_CR1_JDISCEN;
-  }
-  else
-  {
-    /* Disable the selected ADC injected discontinuous mode */
-    hadc->Instance->CR1 &= ~(ADC_CR1_JDISCEN);
-  }
-  
-  switch(sConfigInjected->InjectedRank)
-  {
-    case 1U:
-      /* Set injected channel 1 offset */
-      hadc->Instance->JOFR1 &= ~(ADC_JOFR1_JOFFSET1);
-      hadc->Instance->JOFR1 |= sConfigInjected->InjectedOffset;
-      break;
-    case 2U:
-      /* Set injected channel 2 offset */
-      hadc->Instance->JOFR2 &= ~(ADC_JOFR2_JOFFSET2);
-      hadc->Instance->JOFR2 |= sConfigInjected->InjectedOffset;
-      break;
-    case 3U:
-      /* Set injected channel 3 offset */
-      hadc->Instance->JOFR3 &= ~(ADC_JOFR3_JOFFSET3);
-      hadc->Instance->JOFR3 |= sConfigInjected->InjectedOffset;
-      break;
-    default:
-      /* Set injected channel 4 offset */
-      hadc->Instance->JOFR4 &= ~(ADC_JOFR4_JOFFSET4);
-      hadc->Instance->JOFR4 |= sConfigInjected->InjectedOffset;
-      break;
-  }
-  
-  /* if ADC1 Channel_18 is selected enable VBAT Channel */
-  if ((hadc->Instance == ADC1) && (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT))
-  {
-    /* Enable the VBAT channel*/
-    ADC->CCR |= ADC_CCR_VBATE;
-  }
-  
-  /* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */
-  if ((hadc->Instance == ADC1) && ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)))
-  {
-    /* Enable the TSVREFE channel*/
-    ADC->CCR |= ADC_CCR_TSVREFE;
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the ADC multi-mode 
-  * @param  hadc      : pointer to a ADC_HandleTypeDef structure that contains
-  *                     the configuration information for the specified ADC.  
-  * @param  multimode : pointer to an ADC_MultiModeTypeDef structure that contains 
-  *                     the configuration information for  multimode.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_MODE(multimode->Mode));
-  assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode));
-  assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  /* Set ADC mode */
-  ADC->CCR &= ~(ADC_CCR_MULTI);
-  ADC->CCR |= multimode->Mode;
-  
-  /* Set the ADC DMA access mode */
-  ADC->CCR &= ~(ADC_CCR_DMA);
-  ADC->CCR |= multimode->DMAAccessMode;
-  
-  /* Set delay between two sampling phases */
-  ADC->CCR &= ~(ADC_CCR_DELAY);
-  ADC->CCR |= multimode->TwoSamplingDelay;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @brief  DMA transfer complete callback. 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma)   
-{
-  /* Retrieve ADC handle corresponding to current DMA handle */
-  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  /* Update state machine on conversion status if not in error state */
-  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
-  {
-    /* Update ADC state machine */
-    SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
-    
-    /* Determine whether any further conversion upcoming on group regular   */
-    /* by external trigger, continuous mode or scan sequence on going.      */
-    /* Note: On STM32F4, there is no independent flag of end of sequence.   */
-    /*       The test of scan sequence on going is done either with scan    */
-    /*       sequence disabled or with end of conversion flag set to        */
-    /*       of end of sequence.                                            */
-    if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&
-       (hadc->Init.ContinuousConvMode == DISABLE)            &&
-       (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || 
-        HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )
-    {
-      /* Disable ADC end of single conversion interrupt on group regular */
-      /* Note: Overrun interrupt was enabled with EOC interrupt in          */
-      /* HAL_ADC_Start_IT(), but is not disabled here because can be used   */
-      /* by overrun IRQ process below.                                      */
-      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
-      
-      /* Set ADC state */
-      CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);   
-      
-      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
-      {
-        SET_BIT(hadc->State, HAL_ADC_STATE_READY);
-      }
-    }
-    
-    /* Conversion complete callback */
-    HAL_ADC_ConvCpltCallback(hadc);
-  }
-  else
-  {
-    /* Call DMA error callback */
-    hadc->DMA_Handle->XferErrorCallback(hdma);
-  }
-}
-
-/**
-  * @brief  DMA half transfer complete callback. 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma)   
-{
-    ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-    /* Conversion complete callback */
-    HAL_ADC_ConvHalfCpltCallback(hadc); 
-}
-
-/**
-  * @brief  DMA error callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma)   
-{
-    ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-    hadc->State= HAL_ADC_STATE_ERROR_DMA;
-    /* Set ADC error code to DMA error */
-    hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
-    HAL_ADC_ErrorCallback(hadc); 
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_ADC_MODULE_ENABLED */
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_can.c b/stmhal/hal/f4/src/stm32f4xx_hal_can.c
deleted file mode 100644
index 752840c985..0000000000
--- a/stmhal/hal/f4/src/stm32f4xx_hal_can.c
+++ /dev/null
@@ -1,1440 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_can.c
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   This file provides firmware functions to manage the following 
-  *          functionalities of the Controller Area Network (CAN) peripheral:
-  *           + Initialization and de-initialization functions 
-  *           + IO operation functions
-  *           + Peripheral Control functions
-  *           + Peripheral State and Error functions
-  *
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-    [..]            
-      (#) Enable the CAN controller interface clock using 
-          __HAL_RCC_CAN1_CLK_ENABLE() for CAN1 and __HAL_RCC_CAN2_CLK_ENABLE() for CAN2
-      -@- In case you are using CAN2 only, you have to enable the CAN1 clock.
-       
-      (#) CAN pins configuration
-        (++) Enable the clock for the CAN GPIOs using the following function:
-             __GPIOx_CLK_ENABLE()   
-        (++) Connect and configure the involved CAN pins to AF9 using the 
-              following function HAL_GPIO_Init() 
-              
-      (#) Initialize and configure the CAN using CAN_Init() function.   
-                 
-      (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.
-           
-      (#) Receive a CAN frame using HAL_CAN_Receive() function.
-
-     *** Polling mode IO operation ***
-     =================================
-     [..]    
-       (+) Start the CAN peripheral transmission and wait the end of this operation 
-           using HAL_CAN_Transmit(), at this stage user can specify the value of timeout
-           according to his end application
-       (+) Start the CAN peripheral reception and wait the end of this operation 
-           using HAL_CAN_Receive(), at this stage user can specify the value of timeout
-           according to his end application 
-       
-     *** Interrupt mode IO operation ***    
-     ===================================
-     [..]    
-       (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()
-       (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT()         
-       (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine
-       (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can 
-            add his own code by customization of function pointer HAL_CAN_TxCpltCallback 
-       (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can 
-            add his own code by customization of function pointer HAL_CAN_ErrorCallback
- 
-     *** CAN HAL driver macros list ***
-     ============================================= 
-     [..]
-       Below the list of most used macros in CAN HAL driver.
-       
-      (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts
-      (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts
-      (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled
-      (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags
-      (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status
-      
-     [..] 
-      (@) You can refer to the CAN HAL driver header file for more useful macros 
-                
-  @endverbatim
-           
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup CAN CAN
-  * @brief CAN driver modules
-  * @{
-  */ 
-  
-#ifdef HAL_CAN_MODULE_ENABLED  
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
-    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
-    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
-  
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup CAN_Private_Constants
-  * @{
-  */
-#define CAN_TIMEOUT_VALUE  10U
-/**
-  * @}
-  */
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup CAN_Private_Functions
-  * @{
-  */
-static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);
-static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup CAN_Exported_Functions CAN Exported Functions
-  * @{
-  */
-
-/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions 
- *
-@verbatim    
-  ==============================================================================
-              ##### Initialization and de-initialization functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Initialize and configure the CAN. 
-      (+) De-initialize the CAN. 
-         
-@endverbatim
-  * @{
-  */
-  
-/**
-  * @brief  Initializes the CAN peripheral according to the specified
-  *         parameters in the CAN_InitStruct.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
-{
-  uint32_t InitStatus = 3U;
-  uint32_t tickstart = 0U;
-  
-  /* Check CAN handle */
-  if(hcan == NULL)
-  {
-     return HAL_ERROR;
-  }
-  
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
-  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM));
-  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM));
-  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM));
-  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART));
-  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM));
-  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP));
-  assert_param(IS_CAN_MODE(hcan->Init.Mode));
-  assert_param(IS_CAN_SJW(hcan->Init.SJW));
-  assert_param(IS_CAN_BS1(hcan->Init.BS1));
-  assert_param(IS_CAN_BS2(hcan->Init.BS2));
-  assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
-  
-
-  if(hcan->State == HAL_CAN_STATE_RESET)
-  {    
-    /* Allocate lock resource and initialize it */
-    hcan->Lock = HAL_UNLOCKED;
-    /* Init the low level hardware */
-    HAL_CAN_MspInit(hcan);
-  }
-  
-  /* Initialize the CAN state*/
-  hcan->State = HAL_CAN_STATE_BUSY;
-  
-  /* Exit from sleep mode */
-  hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
-
-  /* Request initialisation */
-  hcan->Instance->MCR |= CAN_MCR_INRQ ;
-  
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  /* Wait the acknowledge */
-  while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
-  {
-    if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE)
-    {
-      hcan->State= HAL_CAN_STATE_TIMEOUT;
-      /* Process unlocked */
-      __HAL_UNLOCK(hcan);
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Check acknowledge */
-  if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
-  {
-    InitStatus = CAN_INITSTATUS_FAILED;
-  }
-  else 
-  {
-    /* Set the time triggered communication mode */
-    if (hcan->Init.TTCM == ENABLE)
-    {
-      hcan->Instance->MCR |= CAN_MCR_TTCM;
-    }
-    else
-    {
-      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM;
-    }
-
-    /* Set the automatic bus-off management */
-    if (hcan->Init.ABOM == ENABLE)
-    {
-      hcan->Instance->MCR |= CAN_MCR_ABOM;
-    }
-    else
-    {
-      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM;
-    }
-
-    /* Set the automatic wake-up mode */
-    if (hcan->Init.AWUM == ENABLE)
-    {
-      hcan->Instance->MCR |= CAN_MCR_AWUM;
-    }
-    else
-    {
-      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM;
-    }
-
-    /* Set the no automatic retransmission */
-    if (hcan->Init.NART == ENABLE)
-    {
-      hcan->Instance->MCR |= CAN_MCR_NART;
-    }
-    else
-    {
-      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART;
-    }
-
-    /* Set the receive FIFO locked mode */
-    if (hcan->Init.RFLM == ENABLE)
-    {
-      hcan->Instance->MCR |= CAN_MCR_RFLM;
-    }
-    else
-    {
-      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM;
-    }
-
-    /* Set the transmit FIFO priority */
-    if (hcan->Init.TXFP == ENABLE)
-    {
-      hcan->Instance->MCR |= CAN_MCR_TXFP;
-    }
-    else
-    {
-      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP;
-    }
-
-    /* Set the bit timing register */
-    hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \
-                ((uint32_t)hcan->Init.SJW) | \
-                ((uint32_t)hcan->Init.BS1) | \
-                ((uint32_t)hcan->Init.BS2) | \
-               ((uint32_t)hcan->Init.Prescaler - 1U);
-
-    /* Request leave initialisation */
-    hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ;
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-   /* Wait the acknowledge */
-   while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
-   {
-    if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE)
-     {
-       hcan->State= HAL_CAN_STATE_TIMEOUT;
-       /* Process unlocked */
-       __HAL_UNLOCK(hcan);
-       return HAL_TIMEOUT;
-     }
-   }
-
-    /* Check acknowledged */
-    if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
-    {
-      InitStatus = CAN_INITSTATUS_FAILED;
-    }
-    else
-    {
-      InitStatus = CAN_INITSTATUS_SUCCESS;
-    }
-  }
- 
-  if(InitStatus == CAN_INITSTATUS_SUCCESS)
-  {
-    /* Set CAN error code to none */
-    hcan->ErrorCode = HAL_CAN_ERROR_NONE;
-    
-    /* Initialize the CAN state */
-    hcan->State = HAL_CAN_STATE_READY;
-  
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Initialize the CAN state */
-    hcan->State = HAL_CAN_STATE_ERROR;
-    
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Configures the CAN reception filter according to the specified
-  *         parameters in the CAN_FilterInitStruct.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @param  sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that
-  *         contains the filter configuration information.
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)
-{
-  uint32_t filternbrbitpos = 0U;
-  
-  /* Check the parameters */
-  assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
-  assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
-  assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
-  assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
-  assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
-  assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber));
-  
-  filternbrbitpos = ((uint32_t)1U) << sFilterConfig->FilterNumber;
-
-  /* Initialisation mode for the filter */
-  CAN1->FMR |= (uint32_t)CAN_FMR_FINIT;
-  
-  /* Select the start slave bank */
-  CAN1->FMR &= ~((uint32_t)CAN_FMR_CAN2SB);
-  CAN1->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8U);
-     
-  /* Filter Deactivation */
-  CAN1->FA1R &= ~(uint32_t)filternbrbitpos;
-
-  /* Filter Scale */
-  if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
-  {
-    /* 16-bit scale for the filter */
-    CAN1->FS1R &= ~(uint32_t)filternbrbitpos;
-
-    /* First 16-bit identifier and First 16-bit mask */
-    /* Or First 16-bit identifier and Second 16-bit identifier */
-    CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 = 
-       ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
-        (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
-
-    /* Second 16-bit identifier and Second 16-bit mask */
-    /* Or Third 16-bit identifier and Fourth 16-bit identifier */
-    CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 = 
-       ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
-        (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
-  }
-
-  if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
-  {
-    /* 32-bit scale for the filter */
-    CAN1->FS1R |= filternbrbitpos;
-    /* 32-bit identifier or First 32-bit identifier */
-    CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 = 
-       ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
-        (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
-    /* 32-bit mask or Second 32-bit identifier */
-    CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 = 
-       ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
-        (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
-  }
-
-  /* Filter Mode */
-  if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
-  {
-    /*Id/Mask mode for the filter*/
-    CAN1->FM1R &= ~(uint32_t)filternbrbitpos;
-  }
-  else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
-  {
-    /*Identifier list mode for the filter*/
-    CAN1->FM1R |= (uint32_t)filternbrbitpos;
-  }
-
-  /* Filter FIFO assignment */
-  if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
-  {
-    /* FIFO 0 assignation for the filter */
-    CAN1->FFA1R &= ~(uint32_t)filternbrbitpos;
-  }
-
-  if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1)
-  {
-    /* FIFO 1 assignation for the filter */
-    CAN1->FFA1R |= (uint32_t)filternbrbitpos;
-  }
-  
-  /* Filter activation */
-  if (sFilterConfig->FilterActivation == ENABLE)
-  {
-    CAN1->FA1R |= filternbrbitpos;
-  }
-
-  /* Leave the initialisation mode for the filter */
-  CAN1->FMR &= ~((uint32_t)CAN_FMR_FINIT);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deinitializes the CANx peripheral registers to their default reset values. 
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)
-{
-  /* Check CAN handle */
-  if(hcan == NULL)
-  {
-     return HAL_ERROR;
-  }
-  
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
-  
-  /* Change CAN state */
-  hcan->State = HAL_CAN_STATE_BUSY;
-  
-  /* DeInit the low level hardware */
-  HAL_CAN_MspDeInit(hcan);
-  
-  /* Change CAN state */
-  hcan->State = HAL_CAN_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hcan);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the CAN MSP.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.  
-  * @retval None
-  */
-__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcan);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_CAN_MspInit could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  DeInitializes the CAN MSP.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.  
-  * @retval None
-  */
-__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcan);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_CAN_MspDeInit could be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_Exported_Functions_Group2 IO operation functions
- *  @brief    IO operation functions 
- *
-@verbatim   
-  ==============================================================================
-                      ##### IO operation functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Transmit a CAN frame message.
-      (+) Receive a CAN frame message.
-      (+) Enter CAN peripheral in sleep mode. 
-      (+) Wake up the CAN peripheral from sleep mode.
-               
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initiates and transmits a CAN frame message.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.  
-  * @param  Timeout: Specify Timeout value   
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
-{
-  uint32_t  transmitmailbox = 5U;
-  uint32_t tickstart = 0U;
-
-  /* Check the parameters */
-  assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
-  assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
-  assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
-
-  if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
-     ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
-     ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
-  {  
-    /* Process locked */
-    __HAL_LOCK(hcan);
-  
-    if(hcan->State == HAL_CAN_STATE_BUSY_RX) 
-    {
-      /* Change CAN state */
-      hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      /* Change CAN state */
-      hcan->State = HAL_CAN_STATE_BUSY_TX;
-    }
-  
-    /* Select one empty transmit mailbox */
-    if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
-    {
-      transmitmailbox = 0U;
-    }
-    else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
-    {
-      transmitmailbox = 1U;
-    }
-    else
-    {
-      transmitmailbox = 2U;
-    }
-
-    /* Set up the Id */
-    hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
-    if (hcan->pTxMsg->IDE == CAN_ID_STD)
-    {
-      assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));  
-      hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \
-                                                  hcan->pTxMsg->RTR);
-    }
-    else
-    {
-      assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
-      hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \
-                                                  hcan->pTxMsg->IDE | \
-                                                  hcan->pTxMsg->RTR);
-    }
-    
-    /* Set up the DLC */
-    hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;
-    hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U;
-    hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
-
-    /* Set up the data field */
-    hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3U] << 24U) | 
-                                             ((uint32_t)hcan->pTxMsg->Data[2U] << 16U) |
-                                             ((uint32_t)hcan->pTxMsg->Data[1U] << 8U) | 
-                                             ((uint32_t)hcan->pTxMsg->Data[0U]));
-    hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7U] << 24U) | 
-                                             ((uint32_t)hcan->pTxMsg->Data[6U] << 16U) |
-                                             ((uint32_t)hcan->pTxMsg->Data[5U] << 8U) |
-                                             ((uint32_t)hcan->pTxMsg->Data[4U]));
-    /* Request transmission */
-    hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
-  
-    /* Get tick */ 
-    tickstart = HAL_GetTick();
-  
-    /* Check End of transmission flag */
-    while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))
-    {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-       if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
-       {
-         hcan->State = HAL_CAN_STATE_TIMEOUT;
-         /* Process unlocked */
-         __HAL_UNLOCK(hcan);
-         return HAL_TIMEOUT;
-        }
-      }
-    }
-    if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) 
-    {
-      /* Change CAN state */
-      hcan->State = HAL_CAN_STATE_BUSY_RX;
-    }
-    else
-    {
-      /* Change CAN state */
-      hcan->State = HAL_CAN_STATE_READY;
-    }
-    
-    /* Process unlocked */
-    __HAL_UNLOCK(hcan);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_ERROR; 
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Initiates and transmits a CAN frame message.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
-{
-  uint32_t  transmitmailbox = 5U;
-  
-  /* Check the parameters */
-  assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
-  assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
-  assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
-  
-  if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
-     ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
-     ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcan);
-    
-    /* Select one empty transmit mailbox */
-    if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
-    {
-      transmitmailbox = 0U;
-    }
-    else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
-    {
-      transmitmailbox = 1U;
-    }
-    else
-    {
-      transmitmailbox = 2U;
-    }
-
-    /* Set up the Id */
-    hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
-    if(hcan->pTxMsg->IDE == CAN_ID_STD)
-    {
-      assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));  
-      hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \
-                                                hcan->pTxMsg->RTR);
-    }
-    else
-    {
-      assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
-      hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \
-                                                hcan->pTxMsg->IDE | \
-                                                hcan->pTxMsg->RTR);
-    }
-    
-    /* Set up the DLC */
-    hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;
-    hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U;
-    hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
-
-    /* Set up the data field */
-    hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3U] << 24U) | 
-                                           ((uint32_t)hcan->pTxMsg->Data[2U] << 16U) |
-                                           ((uint32_t)hcan->pTxMsg->Data[1U] << 8U) | 
-                                           ((uint32_t)hcan->pTxMsg->Data[0U]));
-    hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7U] << 24U) | 
-                                           ((uint32_t)hcan->pTxMsg->Data[6U] << 16U) |
-                                           ((uint32_t)hcan->pTxMsg->Data[5U] << 8U) |
-                                           ((uint32_t)hcan->pTxMsg->Data[4U]));
-    
-    if(hcan->State == HAL_CAN_STATE_BUSY_RX) 
-    {
-      /* Change CAN state */
-      hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      /* Change CAN state */
-      hcan->State = HAL_CAN_STATE_BUSY_TX;
-    }
-      
-    /* Set CAN error code to none */
-    hcan->ErrorCode = HAL_CAN_ERROR_NONE;
-      
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcan);
-      
-    /* Enable Error warning Interrupt */
-    __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG);
-      
-    /* Enable Error passive Interrupt */
-    __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV);
-      
-    /* Enable Bus-off Interrupt */
-    __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF);
-      
-    /* Enable Last error code Interrupt */
-    __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC);
-      
-    /* Enable Error Interrupt */
-    __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR);
-      
-    /* Enable Transmit mailbox empty Interrupt */
-    __HAL_CAN_ENABLE_IT(hcan, CAN_IT_TME);
-      
-    /* Request transmission */
-    hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
-  }
-  else
-  {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_ERROR; 
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Receives a correct CAN frame.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.  
-  * @param  FIFONumber: FIFO Number value
-  * @param  Timeout: Specify Timeout value 
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
-{
-  uint32_t tickstart = 0U;
-   
-  /* Check the parameters */
-  assert_param(IS_CAN_FIFO(FIFONumber));
-  
-  /* Process locked */
-  __HAL_LOCK(hcan);
-  
-  if(hcan->State == HAL_CAN_STATE_BUSY_TX) 
-  {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
-  }
-  else
-  {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_BUSY_RX;
-  }
-    
-  /* Get tick */ 
-  tickstart = HAL_GetTick();
-  
-  /* Check pending message */
-  while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0U)
-  {
-    /* Check for the Timeout */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        hcan->State = HAL_CAN_STATE_TIMEOUT;
-        /* Process unlocked */
-        __HAL_UNLOCK(hcan);
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  
-  /* Get the Id */
-  hcan->pRxMsg->IDE = (uint8_t)0x04U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
-  if (hcan->pRxMsg->IDE == CAN_ID_STD)
-  {
-    hcan->pRxMsg->StdId = (uint32_t)0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
-  }
-  else
-  {
-    hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
-  }
-  
-  hcan->pRxMsg->RTR = (uint8_t)0x02U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
-  /* Get the DLC */
-  hcan->pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
-  /* Get the FMI */
-  hcan->pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
-  /* Get the FIFONumber */
-  hcan->pRxMsg->FIFONumber = FIFONumber;
-  /* Get the data field */
-  hcan->pRxMsg->Data[0U] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
-  hcan->pRxMsg->Data[1U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
-  hcan->pRxMsg->Data[2U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
-  hcan->pRxMsg->Data[3U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
-  hcan->pRxMsg->Data[4U] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
-  hcan->pRxMsg->Data[5U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
-  hcan->pRxMsg->Data[6U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
-  hcan->pRxMsg->Data[7U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
-  
-  /* Release the FIFO */
-  if(FIFONumber == CAN_FIFO0)
-  {
-    /* Release FIFO0 */
-    __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
-  }
-  else /* FIFONumber == CAN_FIFO1 */
-  {
-    /* Release FIFO1 */
-    __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
-  }
-  
-  if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) 
-  {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_BUSY_TX;
-    
-    /* Process unlocked */
-    __HAL_UNLOCK(hcan);
-  }
-  else
-  {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_READY;
-    
-    /* Process unlocked */
-    __HAL_UNLOCK(hcan);
-  }
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Receives a correct CAN frame.
-  * @param  hcan:       Pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.  
-  * @param  FIFONumber: Specify the FIFO number    
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
-{
-  uint32_t tmp = 0U;
-  
-  /* Check the parameters */
-  assert_param(IS_CAN_FIFO(FIFONumber));
-  
-  tmp = hcan->State;
-  if((tmp == HAL_CAN_STATE_READY) || (tmp == HAL_CAN_STATE_BUSY_TX))
-  {
-    /* Process locked */
-    __HAL_LOCK(hcan);
-  
-    if(hcan->State == HAL_CAN_STATE_BUSY_TX) 
-    {
-      /* Change CAN state */
-      hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      /* Change CAN state */
-      hcan->State = HAL_CAN_STATE_BUSY_RX;
-    }
-    
-    /* Set CAN error code to none */
-    hcan->ErrorCode = HAL_CAN_ERROR_NONE;
-    
-    /* Enable Error warning Interrupt */
-    __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG);
-      
-    /* Enable Error passive Interrupt */
-    __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV);
-      
-    /* Enable Bus-off Interrupt */
-    __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF);
-      
-    /* Enable Last error code Interrupt */
-    __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC);
-      
-    /* Enable Error Interrupt */
-    __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR);
-
-    /* Process unlocked */
-    __HAL_UNLOCK(hcan);
-
-    if(FIFONumber == CAN_FIFO0)
-    {
-      /* Enable FIFO 0 message pending Interrupt */
-      __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP0);
-    }
-    else
-    {
-      /* Enable FIFO 1 message pending Interrupt */
-      __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP1);
-    }
-    
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enters the Sleep (low power) mode.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
-{
-  uint32_t tickstart = 0U;
-   
-  /* Process locked */
-  __HAL_LOCK(hcan);
-  
-  /* Change CAN state */
-  hcan->State = HAL_CAN_STATE_BUSY; 
-    
-  /* Request Sleep mode */
-   hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
-   
-  /* Sleep mode status */
-  if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
-  {
-    /* Process unlocked */
-    __HAL_UNLOCK(hcan);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  /* Get tick */ 
-  tickstart = HAL_GetTick();
-  
-  /* Wait the acknowledge */
-  while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
-  {
-    if((HAL_GetTick()  - tickstart) > CAN_TIMEOUT_VALUE)
-    {
-      hcan->State = HAL_CAN_STATE_TIMEOUT;
-      /* Process unlocked */
-      __HAL_UNLOCK(hcan);
-      return HAL_TIMEOUT;
-    }
-  }
-  
-  /* Change CAN state */
-  hcan->State = HAL_CAN_STATE_READY;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hcan);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral
-  *         is in the normal mode.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
-{
-  uint32_t tickstart = 0U;
-    
-  /* Process locked */
-  __HAL_LOCK(hcan);
-  
-  /* Change CAN state */
-  hcan->State = HAL_CAN_STATE_BUSY;  
- 
-  /* Wake up request */
-  hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
-
-  /* Get tick */ 
-  tickstart = HAL_GetTick();
-
-  /* Sleep mode status */
-  while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
-  {
-    if((HAL_GetTick()  - tickstart) > CAN_TIMEOUT_VALUE)
-    {
-      hcan->State= HAL_CAN_STATE_TIMEOUT;
-      /* Process unlocked */
-      __HAL_UNLOCK(hcan);
-      return HAL_TIMEOUT;
-    }
-  }
-  if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
-  {
-    /* Process unlocked */
-    __HAL_UNLOCK(hcan);
- 
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  /* Change CAN state */
-  hcan->State = HAL_CAN_STATE_READY; 
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hcan);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handles CAN interrupt request  
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval None
-  */
-void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
-{
-  uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U;
-  
-  /* Check End of transmission flag */
-  if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))
-  {
-    tmp1 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0);
-    tmp2 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1);
-    tmp3 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2);
-    if(tmp1 || tmp2 || tmp3)  
-    {
-      /* Call transmit function */
-      CAN_Transmit_IT(hcan);
-    }
-  }
-  
-  tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0);
-  tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0);
-  /* Check End of reception flag for FIFO0 */
-  if((tmp1 != 0U) && tmp2)
-  {
-    /* Call receive function */
-    CAN_Receive_IT(hcan, CAN_FIFO0);
-  }
-  
-  tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1);
-  tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1);
-  /* Check End of reception flag for FIFO1 */
-  if((tmp1 != 0U) && tmp2)
-  {
-    /* Call receive function */
-    CAN_Receive_IT(hcan, CAN_FIFO1);
-  }
-  
-  tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG);
-  tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG);
-  tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
-  /* Check Error Warning Flag */
-  if(tmp1 && tmp2 && tmp3)
-  {
-    /* Set CAN error code to EWG error */
-    hcan->ErrorCode |= HAL_CAN_ERROR_EWG;
-  }
-  
-  tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV);
-  tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV);
-  tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); 
-  /* Check Error Passive Flag */
-  if(tmp1 && tmp2 && tmp3)
-  {
-    /* Set CAN error code to EPV error */
-    hcan->ErrorCode |= HAL_CAN_ERROR_EPV;
-  }
-  
-  tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF);
-  tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF);
-  tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);  
-  /* Check Bus-Off Flag */
-  if(tmp1 && tmp2 && tmp3)
-  {
-    /* Set CAN error code to BOF error */
-    hcan->ErrorCode |= HAL_CAN_ERROR_BOF;
-  }
-  
-  tmp1 = HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC);
-  tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC);
-  tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
-  /* Check Last error code Flag */
-  if((!tmp1) && tmp2 && tmp3)
-  {
-    tmp1 = (hcan->Instance->ESR) & CAN_ESR_LEC;
-    switch(tmp1)
-    {
-      case(CAN_ESR_LEC_0):
-          /* Set CAN error code to STF error */
-          hcan->ErrorCode |= HAL_CAN_ERROR_STF;
-          break;
-      case(CAN_ESR_LEC_1):
-          /* Set CAN error code to FOR error */
-          hcan->ErrorCode |= HAL_CAN_ERROR_FOR;
-          break;
-      case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
-          /* Set CAN error code to ACK error */
-          hcan->ErrorCode |= HAL_CAN_ERROR_ACK;
-          break;
-      case(CAN_ESR_LEC_2):
-          /* Set CAN error code to BR error */
-          hcan->ErrorCode |= HAL_CAN_ERROR_BR;
-          break;
-      case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
-          /* Set CAN error code to BD error */
-          hcan->ErrorCode |= HAL_CAN_ERROR_BD;
-          break;
-      case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
-          /* Set CAN error code to CRC error */
-          hcan->ErrorCode |= HAL_CAN_ERROR_CRC;
-          break;
-      default:
-          break;
-    }
-
-    /* Clear Last error code Flag */ 
-    hcan->Instance->ESR &= ~(CAN_ESR_LEC);
-  }
-  
-  /* Call the Error call Back in case of Errors */
-  if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)
-  {
-    /* Clear ERRI Flag */ 
-    hcan->Instance->MSR = CAN_MSR_ERRI; 
-    /* Set the CAN state ready to be able to start again the process */
-    hcan->State = HAL_CAN_STATE_READY;
-    /* Call Error callback function */
-    HAL_CAN_ErrorCallback(hcan);
-  }  
-}
-
-/**
-  * @brief  Transmission  complete callback in non blocking mode 
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval None
-  */
-__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcan);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_CAN_TxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Transmission  complete callback in non blocking mode 
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval None
-  */
-__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcan);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_CAN_RxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Error CAN callback.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval None
-  */
-__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcan);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_CAN_ErrorCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
- *  @brief   CAN Peripheral State functions 
- *
-@verbatim   
-  ==============================================================================
-            ##### Peripheral State and Error functions #####
-  ==============================================================================
-    [..]
-    This subsection provides functions allowing to :
-      (+) Check the CAN state.
-      (+) Check CAN Errors detected during interrupt process
-         
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  return the CAN state
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval HAL state
-  */
-HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan)
-{
-  /* Return CAN state */
-  return hcan->State;
-}
-
-/**
-  * @brief  Return the CAN error code
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval CAN Error Code
-  */
-uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
-{
-  return hcan->ErrorCode;
-}
-
-/**
-  * @}
-  */
-/**
-  * @brief  Initiates and transmits a CAN frame message.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.  
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
-{
-  /* Disable Transmit mailbox empty Interrupt */
-  __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME);
-  
-  if(hcan->State == HAL_CAN_STATE_BUSY_TX)
-  {   
-    /* Disable Error warning Interrupt */
-    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG);
-    
-    /* Disable Error passive Interrupt */
-    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV);
-    
-    /* Disable Bus-off Interrupt */
-    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF);
-    
-    /* Disable Last error code Interrupt */
-    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC);
-    
-    /* Disable Error Interrupt */
-    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR);
-  }
-  
-  if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) 
-  {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_BUSY_RX;
-  }
-  else
-  {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_READY;
-  }
-  
-  /* Transmission complete callback */ 
-  HAL_CAN_TxCpltCallback(hcan);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Receives a correct CAN frame.
-  * @param  hcan:       Pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.  
-  * @param  FIFONumber: Specify the FIFO number    
-  * @retval HAL status
-  * @retval None
-  */
-static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
-{
-  /* Get the Id */
-  hcan->pRxMsg->IDE = (uint8_t)0x04U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
-  if (hcan->pRxMsg->IDE == CAN_ID_STD)
-  {
-    hcan->pRxMsg->StdId = (uint32_t)0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
-  }
-  else
-  {
-    hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
-  }
-  
-  hcan->pRxMsg->RTR = (uint8_t)0x02U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
-  /* Get the DLC */
-  hcan->pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
-  /* Get the FIFONumber */
-  hcan->pRxMsg->FIFONumber = FIFONumber;
-  /* Get the FMI */
-  hcan->pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
-  /* Get the data field */
-  hcan->pRxMsg->Data[0U] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
-  hcan->pRxMsg->Data[1U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
-  hcan->pRxMsg->Data[2U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
-  hcan->pRxMsg->Data[3U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
-  hcan->pRxMsg->Data[4U] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
-  hcan->pRxMsg->Data[5U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
-  hcan->pRxMsg->Data[6U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
-  hcan->pRxMsg->Data[7U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
-  /* Release the FIFO */
-  /* Release FIFO0 */
-  if (FIFONumber == CAN_FIFO0)
-  {
-    __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
-    
-    /* Disable FIFO 0 message pending Interrupt */
-    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP0);
-  }
-  /* Release FIFO1 */
-  else /* FIFONumber == CAN_FIFO1 */
-  {
-    __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
-    
-    /* Disable FIFO 1 message pending Interrupt */
-    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP1);
-  }
-  
-  if(hcan->State == HAL_CAN_STATE_BUSY_RX)
-  {   
-    /* Disable Error warning Interrupt */
-    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG);
-    
-    /* Disable Error passive Interrupt */
-    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV);
-    
-    /* Disable Bus-off Interrupt */
-    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF);
-    
-    /* Disable Last error code Interrupt */
-    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC);
-    
-    /* Disable Error Interrupt */
-    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR);
-  }
-  
-  if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) 
-  {
-    /* Disable CAN state */
-    hcan->State = HAL_CAN_STATE_BUSY_TX;
-  }
-  else
-  {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_READY;
-  }
-
-  /* Receive complete callback */ 
-  HAL_CAN_RxCpltCallback(hcan);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
-          STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
-          STM32F412Vx || STM32F412Rx || STM32F412Cx */
-
-#endif /* HAL_CAN_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_cortex.c b/stmhal/hal/f4/src/stm32f4xx_hal_cortex.c
deleted file mode 100644
index fe4524b3b8..0000000000
--- a/stmhal/hal/f4/src/stm32f4xx_hal_cortex.c
+++ /dev/null
@@ -1,483 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_cortex.c
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   CORTEX HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the CORTEX:
-  *           + Initialization and de-initialization functions
-  *           + Peripheral Control functions 
-  *
-  @verbatim  
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-
-    [..]  
-    *** How to configure Interrupts using CORTEX HAL driver ***
-    ===========================================================
-    [..]     
-    This section provides functions allowing to configure the NVIC interrupts (IRQ).
-    The Cortex-M4 exceptions are managed by CMSIS functions.
-   
-    (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
-        function according to the following table.
-    (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). 
-    (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
-    (#) please refer to programing manual for details in how to configure priority. 
-      
-     -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. 
-         The pending IRQ priority will be managed only by the sub priority.
-   
-     -@- IRQ priority order (sorted by highest to lowest priority):
-        (+@) Lowest preemption priority
-        (+@) Lowest sub priority
-        (+@) Lowest hardware priority (IRQ number)
- 
-    [..]  
-    *** How to configure Systick using CORTEX HAL driver ***
-    ========================================================
-    [..]
-    Setup SysTick Timer for time base.
-           
-   (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
-       is a CMSIS function that:
-        (++) Configures the SysTick Reload register with value passed as function parameter.
-        (++) Configures the SysTick IRQ priority to the lowest value (0x0FU).
-        (++) Resets the SysTick Counter register.
-        (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
-        (++) Enables the SysTick Interrupt.
-        (++) Starts the SysTick Counter.
-    
-   (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
-       __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
-       HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
-       inside the stm32f4xx_hal_cortex.h file.
-
-   (+) You can change the SysTick IRQ priority by calling the
-       HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function 
-       call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
-
-   (+) To adjust the SysTick time base, use the following formula:
-                            
-       Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
-       (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
-       (++) Reload Value should not exceed 0xFFFFFF
-   
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup CORTEX CORTEX
-  * @brief CORTEX HAL module driver
-  * @{
-  */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
-  * @{
-  */
-
-
-/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @brief    Initialization and Configuration functions 
- *
-@verbatim    
-  ==============================================================================
-              ##### Initialization and de-initialization functions #####
-  ==============================================================================
-    [..]
-      This section provides the CORTEX HAL driver functions allowing to configure Interrupts
-      Systick functionalities 
-
-@endverbatim
-  * @{
-  */
-
-
-/**
-  * @brief  Sets the priority grouping field (preemption priority and subpriority)
-  *         using the required unlock sequence.
-  * @param  PriorityGroup: The priority grouping bits length. 
-  *         This parameter can be one of the following values:
-  *         @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
-  *                                    4 bits for subpriority
-  *         @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
-  *                                    3 bits for subpriority
-  *         @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
-  *                                    2 bits for subpriority
-  *         @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
-  *                                    1 bits for subpriority
-  *         @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
-  *                                    0 bits for subpriority
-  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. 
-  *         The pending IRQ priority will be managed only by the subpriority. 
-  * @retval None
-  */
-void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
-  
-  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
-  NVIC_SetPriorityGrouping(PriorityGroup);
-}
-
-/**
-  * @brief  Sets the priority of an interrupt.
-  * @param  IRQn: External interrupt number.
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
-  * @param  PreemptPriority: The preemption priority for the IRQn channel.
-  *         This parameter can be a value between 0 and 15
-  *         A lower priority value indicates a higher priority 
-  * @param  SubPriority: the subpriority level for the IRQ channel.
-  *         This parameter can be a value between 0 and 15
-  *         A lower priority value indicates a higher priority.          
-  * @retval None
-  */
-void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
-{ 
-  uint32_t prioritygroup = 0x00U;
-  
-  /* Check the parameters */
-  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
-  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
-  
-  prioritygroup = NVIC_GetPriorityGrouping();
-  
-  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
-}
-
-/**
-  * @brief  Enables a device specific interrupt in the NVIC interrupt controller.
-  * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
-  *         function should be called before. 
-  * @param  IRQn External interrupt number.
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
-  * @retval None
-  */
-void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-  
-  /* Enable interrupt */
-  NVIC_EnableIRQ(IRQn);
-}
-
-/**
-  * @brief  Disables a device specific interrupt in the NVIC interrupt controller.
-  * @param  IRQn External interrupt number.
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
-  * @retval None
-  */
-void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-  
-  /* Disable interrupt */
-  NVIC_DisableIRQ(IRQn);
-}
-
-/**
-  * @brief  Initiates a system reset request to reset the MCU.
-  * @retval None
-  */
-void HAL_NVIC_SystemReset(void)
-{
-  /* System Reset */
-  NVIC_SystemReset();
-}
-
-/**
-  * @brief  Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-  *         Counter is in free running mode to generate periodic interrupts.
-  * @param  TicksNumb: Specifies the ticks Number of ticks between two interrupts.
-  * @retval status:  - 0  Function succeeded.
-  *                  - 1  Function failed.
-  */
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
-{
-   return SysTick_Config(TicksNumb);
-}
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
- *  @brief   Cortex control functions 
- *
-@verbatim   
-  ==============================================================================
-                      ##### Peripheral Control functions #####
-  ==============================================================================  
-    [..]
-      This subsection provides a set of functions allowing to control the CORTEX
-      (NVIC, SYSTICK, MPU) functionalities. 
- 
-      
-@endverbatim
-  * @{
-  */
-
-#if (__MPU_PRESENT == 1U)
-/**
-  * @brief  Initializes and configures the Region and the memory to be protected.
-  * @param  MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
-  *                the initialization and configuration information.
-  * @retval None
-  */
-void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
-{
-  /* Check the parameters */
-  assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
-  assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
-
-  /* Set the Region number */
-  MPU->RNR = MPU_Init->Number;
-
-  if ((MPU_Init->Enable) != RESET)
-  {
-    /* Check the parameters */
-    assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
-    assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
-    assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
-    assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
-    assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
-    assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
-    assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
-    assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
-    
-    MPU->RBAR = MPU_Init->BaseAddress;
-    MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
-                ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
-                ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
-                ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
-                ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
-                ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
-                ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
-                ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
-                ((uint32_t)MPU_Init->Enable                  << MPU_RASR_ENABLE_Pos);
-  }
-  else
-  {
-    MPU->RBAR = 0x00U;
-    MPU->RASR = 0x00U;
-  }
-}
-#endif /* __MPU_PRESENT */
-
-/**
-  * @brief  Gets the priority grouping field from the NVIC Interrupt Controller.
-  * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
-  */
-uint32_t HAL_NVIC_GetPriorityGrouping(void)
-{
-  /* Get the PRIGROUP[10:8] field value */
-  return NVIC_GetPriorityGrouping();
-}
-
-/**
-  * @brief  Gets the priority of an interrupt.
-  * @param  IRQn: External interrupt number.
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
-  * @param   PriorityGroup: the priority grouping bits length.
-  *         This parameter can be one of the following values:
-  *           @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
-  *                                      4 bits for subpriority
-  *           @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
-  *                                      3 bits for subpriority
-  *           @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
-  *                                      2 bits for subpriority
-  *           @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
-  *                                      1 bits for subpriority
-  *           @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
-  *                                      0 bits for subpriority
-  * @param  pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
-  * @param  pSubPriority: Pointer on the Subpriority value (starting from 0).
-  * @retval None
-  */
-void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
- /* Get priority for Cortex-M system or device specific interrupts */
-  NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
-}
-
-/**
-  * @brief  Sets Pending bit of an external interrupt.
-  * @param  IRQn External interrupt number
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
-  * @retval None
-  */
-void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-  
-  /* Set interrupt pending */
-  NVIC_SetPendingIRQ(IRQn);
-}
-
-/**
-  * @brief  Gets Pending Interrupt (reads the pending register in the NVIC 
-  *         and returns the pending bit for the specified interrupt).
-  * @param  IRQn External interrupt number.
-  *          This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
-  * @retval status: - 0  Interrupt status is not pending.
-  *                 - 1  Interrupt status is pending.
-  */
-uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-  
-  /* Return 1 if pending else 0 */
-  return NVIC_GetPendingIRQ(IRQn);
-}
-
-/**
-  * @brief  Clears the pending bit of an external interrupt.
-  * @param  IRQn External interrupt number.
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
-  * @retval None
-  */
-void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-  
-  /* Clear pending interrupt */
-  NVIC_ClearPendingIRQ(IRQn);
-}
-
-/**
-  * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
-  * @param IRQn External interrupt number
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
-  * @retval status: - 0  Interrupt status is not pending.
-  *                 - 1  Interrupt status is pending.
-  */
-uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-  
-  /* Return 1 if active else 0 */
-  return NVIC_GetActive(IRQn);
-}
-
-/**
-  * @brief  Configures the SysTick clock source.
-  * @param  CLKSource: specifies the SysTick clock source.
-  *          This parameter can be one of the following values:
-  *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
-  *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
-  * @retval None
-  */
-void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
-{
-  /* Check the parameters */
-  assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
-  if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
-  {
-    SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
-  }
-  else
-  {
-    SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
-  }
-}
-
-/**
-  * @brief  This function handles SYSTICK interrupt request.
-  * @retval None
-  */
-void HAL_SYSTICK_IRQHandler(void)
-{
-  HAL_SYSTICK_Callback();
-}
-
-/**
-  * @brief  SYSTICK callback.
-  * @retval None
-  */
-__weak void HAL_SYSTICK_Callback(void)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SYSTICK_Callback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_dac.c b/stmhal/hal/f4/src/stm32f4xx_hal_dac.c
deleted file mode 100644
index f702e01cac..0000000000
--- a/stmhal/hal/f4/src/stm32f4xx_hal_dac.c
+++ /dev/null
@@ -1,965 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_dac.c
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   DAC HAL module driver.
-  *         This file provides firmware functions to manage the following 
-  *         functionalities of the Digital to Analog Converter (DAC) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions
-  *           + Peripheral State and Errors functions      
-  *     
-  *
-  @verbatim      
-  ==============================================================================
-                      ##### DAC Peripheral features #####
-  ==============================================================================
-    [..]        
-      *** DAC Channels ***
-      ====================  
-    [..]
-    The device integrates two 12-bit Digital Analog Converters that can 
-    be used independently or simultaneously (dual mode):
-      (#) DAC channel1 with DAC_OUT1 (PA4) as output
-      (#) DAC channel2 with DAC_OUT2 (PA5) as output
-      
-      *** DAC Triggers ***
-      ====================
-    [..]
-    Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
-    and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register. 
-    [..] 
-    Digital to Analog conversion can be triggered by:
-      (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_TRIGGER_EXT_IT9.
-          The used pin (GPIOx_Pin9) must be configured in input mode.
-  
-      (#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8 
-          (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T4_TRGO...)
-  
-      (#) Software using DAC_TRIGGER_SOFTWARE
-  
-      *** DAC Buffer mode feature ***
-      =============================== 
-      [..] 
-      Each DAC channel integrates an output buffer that can be used to 
-      reduce the output impedance, and to drive external loads directly
-      without having to add an external operational amplifier.
-      To enable, the output buffer use  
-      sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
-      [..]           
-      (@) Refer to the device datasheet for more details about output 
-          impedance value with and without output buffer.
-            
-       *** DAC wave generation feature ***
-       =================================== 
-       [..]     
-       Both DAC channels can be used to generate
-         (#) Noise wave 
-         (#) Triangle wave
-            
-       *** DAC data format ***
-       =======================
-       [..]   
-       The DAC data format can be:
-         (#) 8-bit right alignment using DAC_ALIGN_8B_R
-         (#) 12-bit left alignment using DAC_ALIGN_12B_L
-         (#) 12-bit right alignment using DAC_ALIGN_12B_R
-  
-       *** DAC data value to voltage correspondence ***  
-       ================================================ 
-       [..] 
-       The analog output voltage on each DAC channel pin is determined
-       by the following equation: 
-       DAC_OUTx = VREF+ * DOR / 4095
-       with  DOR is the Data Output Register
-          VEF+ is the input voltage reference (refer to the device datasheet)
-        e.g. To set DAC_OUT1 to 0.7V, use
-          Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
-  
-       *** DMA requests  ***
-       =====================
-       [..]    
-       A DMA1 request can be generated when an external trigger (but not
-       a software trigger) occurs if DMA1 requests are enabled using
-       HAL_DAC_Start_DMA()
-       [..]
-       DMA1 requests are mapped as following:
-         (#) DAC channel1 : mapped on DMA1 Stream5 channel7 which must be 
-             already configured
-         (#) DAC channel2 : mapped on DMA1 Stream6 channel7 which must be 
-             already configured
-       
-    -@- For Dual mode and specific signal (Triangle and noise) generation please 
-        refer to Extension Features Driver description        
-  
-      
-                      ##### How to use this driver #####
-  ==============================================================================
-    [..]          
-      (+) DAC APB clock must be enabled to get write access to DAC
-          registers using HAL_DAC_Init()
-      (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
-      (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
-      (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA functions
-
-     *** Polling mode IO operation ***
-     =================================
-     [..]    
-       (+) Start the DAC peripheral using HAL_DAC_Start() 
-       (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
-       (+) Stop the DAC peripheral using HAL_DAC_Stop()
-       
-     *** DMA mode IO operation ***    
-     ==============================
-     [..]    
-       (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length 
-           of data to be transferred at each end of conversion 
-       (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2()  
-           function is executed and user can add his own code by customization of function pointer 
-           HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2
-       (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can 
-            add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
-       (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
-                    
-     *** DAC HAL driver macros list ***
-     ============================================= 
-     [..]
-       Below the list of most used macros in DAC HAL driver.
-       
-      (+) __HAL_DAC_ENABLE : Enable the DAC peripheral
-      (+) __HAL_DAC_DISABLE : Disable the DAC peripheral
-      (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
-      (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
-      
-     [..]
-      (@) You can refer to the DAC HAL driver header file for more useful macros  
-   
- @endverbatim    
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup DAC DAC
-  * @brief DAC driver modules
-  * @{
-  */ 
-
-#ifdef HAL_DAC_MODULE_ENABLED
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
-    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx)
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @addtogroup DAC_Private_Functions
-  * @{
-  */
-/* Private function prototypes -----------------------------------------------*/
-static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
-static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
-static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); 
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup DAC_Exported_Functions DAC Exported Functions
-  * @{
-  */
-
-/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions 
- *
-@verbatim    
-  ==============================================================================
-              ##### Initialization and de-initialization functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Initialize and configure the DAC. 
-      (+) De-initialize the DAC. 
-         
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the DAC peripheral according to the specified parameters
-  *         in the DAC_InitStruct.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
-{ 
-  /* Check DAC handle */
-  if(hdac == NULL)
-  {
-     return HAL_ERROR;
-  }
-  /* Check the parameters */
-  assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
-  
-  if(hdac->State == HAL_DAC_STATE_RESET)
-  {  
-    /* Allocate lock resource and initialize it */
-    hdac->Lock = HAL_UNLOCKED;
-    /* Init the low level hardware */
-    HAL_DAC_MspInit(hdac);
-  }
-  
-  /* Initialize the DAC state*/
-  hdac->State = HAL_DAC_STATE_BUSY;
-  
-  /* Set DAC error code to none */
-  hdac->ErrorCode = HAL_DAC_ERROR_NONE;
-  
-  /* Initialize the DAC state*/
-  hdac->State = HAL_DAC_STATE_READY;
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deinitializes the DAC peripheral registers to their default reset values.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
-{
-  /* Check DAC handle */
-  if(hdac == NULL)
-  {
-     return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_BUSY;
-
-  /* DeInit the low level hardware */
-  HAL_DAC_MspDeInit(hdac);
-
-  /* Set DAC error code to none */
-  hdac->ErrorCode = HAL_DAC_ERROR_NONE;
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hdac);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the DAC MSP.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_DAC_MspInit could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  DeInitializes the DAC MSP.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.  
-  * @retval None
-  */
-__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_DAC_MspDeInit could be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_Exported_Functions_Group2 IO operation functions
- *  @brief    IO operation functions 
- *
-@verbatim   
-  ==============================================================================
-             ##### IO operation functions #####
-  ==============================================================================  
-    [..]  This section provides functions allowing to:
-      (+) Start conversion.
-      (+) Stop conversion.
-      (+) Start conversion and enable DMA transfer.
-      (+) Stop conversion and disable DMA transfer.
-      (+) Get result of conversion.
-                     
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables DAC and starts conversion of channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
-  uint32_t tmp1 = 0U, tmp2 = 0U;
-  
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  
-  /* Process locked */
-  __HAL_LOCK(hdac);
-  
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_BUSY;
-  
-  /* Enable the Peripheral */
-  __HAL_DAC_ENABLE(hdac, Channel);
-  
-  if(Channel == DAC_CHANNEL_1)
-  {
-    tmp1 = hdac->Instance->CR & DAC_CR_TEN1;
-    tmp2 = hdac->Instance->CR & DAC_CR_TSEL1;
-    /* Check if software trigger enabled */
-    if((tmp1 ==  DAC_CR_TEN1) && (tmp2 ==  DAC_CR_TSEL1))
-    {
-      /* Enable the selected DAC software conversion */
-      hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1;
-    }
-  }
-  else
-  {
-    tmp1 = hdac->Instance->CR & DAC_CR_TEN2;
-    tmp2 = hdac->Instance->CR & DAC_CR_TSEL2;    
-    /* Check if software trigger enabled */
-    if((tmp1 == DAC_CR_TEN2) && (tmp2 == DAC_CR_TSEL2))
-    {
-      /* Enable the selected DAC software conversion*/
-      hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG2;
-    }
-  }
-  
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_READY;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hdac);
-    
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disables DAC and stop conversion of channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  
-  /* Disable the Peripheral */
-  __HAL_DAC_DISABLE(hdac, Channel);
- 
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_READY;
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enables DAC and starts conversion of channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @param  pData: The destination peripheral Buffer address.
-  * @param  Length: The length of data to be transferred from memory to DAC peripheral
-  * @param  Alignment: Specifies the data alignment for DAC channel.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
-  *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
-  *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
-{
-  uint32_t tmpreg = 0U;
-    
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  assert_param(IS_DAC_ALIGN(Alignment));
-  
-  /* Process locked */
-  __HAL_LOCK(hdac);
-  
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_BUSY;
-
-  if(Channel == DAC_CHANNEL_1)
-  {
-    /* Set the DMA transfer complete callback for channel1 */
-    hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
-
-    /* Set the DMA half transfer complete callback for channel1 */
-    hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
-
-    /* Set the DMA error callback for channel1 */
-    hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
-
-    /* Enable the selected DAC channel1 DMA request */
-    hdac->Instance->CR |= DAC_CR_DMAEN1;
-    
-    /* Case of use of channel 1 */
-    switch(Alignment)
-    {
-      case DAC_ALIGN_12B_R:
-        /* Get DHR12R1 address */
-        tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
-        break;
-      case DAC_ALIGN_12B_L:
-        /* Get DHR12L1 address */
-        tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
-        break;
-      case DAC_ALIGN_8B_R:
-        /* Get DHR8R1 address */
-        tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
-        break;
-      default:
-        break;
-    }
-  }
-  else
-  {
-    /* Set the DMA transfer complete callback for channel2 */
-    hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
-
-    /* Set the DMA half transfer complete callback for channel2 */
-    hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
-
-    /* Set the DMA error callback for channel2 */
-    hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
-
-    /* Enable the selected DAC channel2 DMA request */
-    hdac->Instance->CR |= DAC_CR_DMAEN2;
-
-    /* Case of use of channel 2 */
-    switch(Alignment)
-    {
-      case DAC_ALIGN_12B_R:
-        /* Get DHR12R2 address */
-        tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
-        break;
-      case DAC_ALIGN_12B_L:
-        /* Get DHR12L2 address */
-        tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
-        break;
-      case DAC_ALIGN_8B_R:
-        /* Get DHR8R2 address */
-        tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
-        break;
-      default:
-        break;
-    }
-  }
-  
-  /* Enable the DMA Stream */
-  if(Channel == DAC_CHANNEL_1)
-  {
-    /* Enable the DAC DMA underrun interrupt */
-    __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
-    
-    /* Enable the DMA Stream */
-    HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
-  } 
-  else
-  {
-    /* Enable the DAC DMA underrun interrupt */
-    __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
-    
-    /* Enable the DMA Stream */
-    HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
-  }
-  
-  /* Enable the Peripheral */
-  __HAL_DAC_ENABLE(hdac, Channel);
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hdac);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disables DAC and stop conversion of channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected   
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  
-  /* Disable the selected DAC channel DMA request */
-   hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel);
-    
-  /* Disable the Peripheral */
-  __HAL_DAC_DISABLE(hdac, Channel);
-  
-  /* Disable the DMA Channel */
-  /* Channel1 is used */
-  if(Channel == DAC_CHANNEL_1)
-  { 
-    status = HAL_DMA_Abort(hdac->DMA_Handle1);
-  }
-  else /* Channel2 is used for */
-  { 
-    status = HAL_DMA_Abort(hdac->DMA_Handle2); 
-  }
-
-  /* Check if DMA Channel effectively disabled */
-  if(status != HAL_OK)
-  {
-    /* Update DAC state machine to error */
-    hdac->State = HAL_DAC_STATE_ERROR;      
-  }
-  else
-  {
-    /* Change DAC state */
-    hdac->State = HAL_DAC_STATE_READY;
-  }
-
-  /* Return function status */
-  return status;
-}
-
-/**
-  * @brief  Returns the last data output value of the selected DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @retval The selected DAC channel data output value.
-  */
-uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  
-  /* Returns the DAC channel data output register value */
-  if(Channel == DAC_CHANNEL_1)
-  {
-    return hdac->Instance->DOR1;
-  }
-  else
-  {
-    return hdac->Instance->DOR2;
-  }
-}
-
-/**
-  * @brief  Handles DAC interrupt request  
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
-{
-  /* Check underrun channel 1 flag */
-  if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
-  {
-    /* Change DAC state to error state */
-    hdac->State = HAL_DAC_STATE_ERROR;
-    
-    /* Set DAC error code to channel1 DMA underrun error */
-    hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
-    
-    /* Clear the underrun flag */
-    __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
-    
-    /* Disable the selected DAC channel1 DMA request */
-    hdac->Instance->CR &= ~DAC_CR_DMAEN1;
-    
-    /* Error callback */ 
-    HAL_DAC_DMAUnderrunCallbackCh1(hdac);
-  }
-  /* Check underrun channel 2 flag */
-  if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
-  {
-    /* Change DAC state to error state */
-    hdac->State = HAL_DAC_STATE_ERROR;
-    
-    /* Set DAC error code to channel2 DMA underrun error */
-    hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH2;
-    
-    /* Clear the underrun flag */
-    __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
-    
-    /* Disable the selected DAC channel1 DMA request */
-    hdac->Instance->CR &= ~DAC_CR_DMAEN2;
-    
-    /* Error callback */ 
-    HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
-  }
-}
-
-/**
-  * @brief  Conversion complete callback in non blocking mode for Channel1 
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_DAC_ConvCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Conversion half DMA transfer callback in non blocking mode for Channel1 
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Error DAC callback for Channel1.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DMA underrun DAC callback for channel1.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-  
-/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
- *  @brief   	Peripheral Control functions 
- *
-@verbatim   
-  ==============================================================================
-             ##### Peripheral Control functions #####
-  ==============================================================================  
-    [..]  This section provides functions allowing to:
-      (+) Configure channels. 
-      (+) Set the specified data holding register value for DAC channel.
-      
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configures the selected DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  sConfig: DAC configuration structure.
-  * @param  Channel: The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
-{
-  uint32_t tmpreg1 = 0U, tmpreg2 = 0U;
-
-  /* Check the DAC parameters */
-  assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
-  assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
-  assert_param(IS_DAC_CHANNEL(Channel));
-  
-  /* Process locked */
-  __HAL_LOCK(hdac);
-  
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_BUSY;
-  
-  /* Get the DAC CR value */
-  tmpreg1 = hdac->Instance->CR;
-  /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
-  tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
-  /* Configure for the selected DAC channel: buffer output, trigger */
-  /* Set TSELx and TENx bits according to DAC_Trigger value */
-  /* Set BOFFx bit according to DAC_OutputBuffer value */   
-  tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
-  /* Calculate CR register value depending on DAC_Channel */
-  tmpreg1 |= tmpreg2 << Channel;
-  /* Write to DAC CR */
-  hdac->Instance->CR = tmpreg1;
-  /* Disable wave generation */
-  hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel);
-  
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_READY;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hdac);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set the specified data holding register value for DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected  
-  * @param  Alignment: Specifies the data alignment.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
-  *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
-  *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
-  * @param  Data: Data to be loaded in the selected data holding register.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
-{  
-  __IO uint32_t tmp = 0U;
-  
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  assert_param(IS_DAC_ALIGN(Alignment));
-  assert_param(IS_DAC_DATA(Data));
-  
-  tmp = (uint32_t)hdac->Instance; 
-  if(Channel == DAC_CHANNEL_1)
-  {
-    tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
-  }
-  else
-  {
-    tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
-  }
-
-  /* Set the DAC channel1 selected data holding register */
-  *(__IO uint32_t *) tmp = Data;
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
- *  @brief   Peripheral State and Errors functions 
- *
-@verbatim   
-  ==============================================================================
-            ##### Peripheral State and Errors functions #####
-  ==============================================================================  
-    [..]
-    This subsection provides functions allowing to
-      (+) Check the DAC state.
-      (+) Check the DAC Errors.
-        
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  return the DAC state
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval HAL state
-  */
-HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)
-{
-  /* Return DAC state */
-  return hdac->State;
-}
-
-
-/**
-  * @brief  Return the DAC error code
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval DAC Error Code
-  */
-uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
-{
-  return hdac->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @brief  DMA conversion complete callback. 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)   
-{
-  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  HAL_DAC_ConvCpltCallbackCh1(hdac); 
-  
-  hdac->State= HAL_DAC_STATE_READY;
-}
-
-/**
-  * @brief  DMA half transfer complete callback. 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)   
-{
-    DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-    /* Conversion complete callback */
-    HAL_DAC_ConvHalfCpltCallbackCh1(hdac); 
-}
-
-/**
-  * @brief  DMA error callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)   
-{
-  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-    
-  /* Set DAC error code to DMA error */
-  hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
-    
-  HAL_DAC_ErrorCallbackCh1(hdac); 
-    
-  hdac->State= HAL_DAC_STATE_READY;
-}
-
-/**
-  * @}
-  */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
-          STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
-          STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx */
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_dac_ex.c b/stmhal/hal/f4/src/stm32f4xx_hal_dac_ex.c
deleted file mode 100644
index f4b872f5d2..0000000000
--- a/stmhal/hal/f4/src/stm32f4xx_hal_dac_ex.c
+++ /dev/null
@@ -1,390 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_dac_ex.c
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   DAC HAL module driver.
-  *         This file provides firmware functions to manage the following 
-  *         functionalities of DAC extension peripheral:
-  *           + Extended features functions
-  *     
-  *
-  @verbatim      
-  ==============================================================================
-                      ##### How to use this driver #####
-  ==============================================================================
-    [..]          
-      (+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) :
-          Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
-          HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.  
-      (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
-      (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
-   
- @endverbatim    
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup DACEx DACEx
-  * @brief DAC driver modules
-  * @{
-  */ 
-
-#ifdef HAL_DAC_MODULE_ENABLED
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
-    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx)
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup DACEx_Exported_Functions DAC Exported Functions
-  * @{
-  */
-
-/** @defgroup DACEx_Exported_Functions_Group1 Extended features functions
- *  @brief    Extended features functions 
- *
-@verbatim   
-  ==============================================================================
-                 ##### Extended features functions #####
-  ==============================================================================  
-    [..]  This section provides functions allowing to:
-      (+) Start conversion.
-      (+) Stop conversion.
-      (+) Start conversion and enable DMA transfer.
-      (+) Stop conversion and disable DMA transfer.
-      (+) Get result of conversion.
-      (+) Get result of dual mode conversion.
-                     
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Returns the last data output value of the selected DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval The selected DAC channel data output value.
-  */
-uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
-{
-  uint32_t tmp = 0U;
-  
-  tmp |= hdac->Instance->DOR1;
-  
-  tmp |= hdac->Instance->DOR2 << 16U;
-  
-  /* Returns the DAC channel data output register value */
-  return tmp;
-}
-
-/**
-  * @brief  Enables or disables the selected DAC channel wave generation.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            DAC_CHANNEL_1 / DAC_CHANNEL_2
-  * @param  Amplitude: Select max triangle amplitude. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
-  *            @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
-  *            @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
-  *            @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
-  *            @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
-  *            @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
-  *            @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
-  *            @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
-  *            @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
-  *            @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
-  *            @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
-  *            @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095                               
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
-{  
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
-  
-  /* Process locked */
-  __HAL_LOCK(hdac);
-  
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_BUSY;
-  
-  /* Enable the selected wave generation for the selected DAC channel */
-  MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1 | DAC_CR_MAMP1) << Channel, (DAC_CR_WAVE1_1 | Amplitude) << Channel);
-  
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_READY;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hdac);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enables or disables the selected DAC channel wave generation.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC. 
-  * @param  Channel: The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            DAC_CHANNEL_1 / DAC_CHANNEL_2
-  * @param  Amplitude: Unmask DAC channel LFSR for noise wave generation. 
-  *          This parameter can be one of the following values: 
-  *            @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation  
-  *            @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation 
-  *            @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation 
-  *            @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation 
-  *            @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation 
-  *            @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation 
-  *            @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation 
-  *            @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation 
-  *            @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation 
-  *            @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation 
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
-{  
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
-  
-  /* Process locked */
-  __HAL_LOCK(hdac);
-  
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_BUSY;
-  
-  /* Enable the selected wave generation for the selected DAC channel */
-  MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1 | DAC_CR_MAMP1) << Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel);
-  
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_READY;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hdac);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set the specified data holding register value for dual DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *               the configuration information for the specified DAC.
-  * @param  Alignment: Specifies the data alignment for dual channel DAC.
-  *          This parameter can be one of the following values:
-  *            DAC_ALIGN_8B_R: 8bit right data alignment selected
-  *            DAC_ALIGN_12B_L: 12bit left data alignment selected
-  *            DAC_ALIGN_12B_R: 12bit right data alignment selected
-  * @param  Data1: Data for DAC Channel2 to be loaded in the selected data holding register.
-  * @param  Data2: Data for DAC Channel1 to be loaded in the selected data  holding register.
-  * @note   In dual mode, a unique register access is required to write in both
-  *          DAC channels at the same time.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
-{  
-  uint32_t data = 0U, tmp = 0U;
-  
-  /* Check the parameters */
-  assert_param(IS_DAC_ALIGN(Alignment));
-  assert_param(IS_DAC_DATA(Data1));
-  assert_param(IS_DAC_DATA(Data2));
-  
-  /* Calculate and set dual DAC data holding register value */
-  if (Alignment == DAC_ALIGN_8B_R)
-  {
-    data = ((uint32_t)Data2 << 8U) | Data1; 
-  }
-  else
-  {
-    data = ((uint32_t)Data2 << 16U) | Data1;
-  }
-  
-  tmp = (uint32_t)hdac->Instance;
-  tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
-
-  /* Set the dual DAC selected data holding register */
-  *(__IO uint32_t *)tmp = data;
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @brief  Conversion complete callback in non blocking mode for Channel2 
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_DAC_ConvCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Conversion half DMA transfer callback in non blocking mode for Channel2 
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_DAC_ConvHalfCpltCallbackCh2 could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Error DAC callback for Channel2.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_DAC_ErrorCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DMA underrun DAC callback for channel2.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_DAC_DMAUnderrunCallbackCh2 could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DMA conversion complete callback. 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)   
-{
-  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  HAL_DACEx_ConvCpltCallbackCh2(hdac); 
-  
-  hdac->State= HAL_DAC_STATE_READY;
-}
-
-/**
-  * @brief  DMA half transfer complete callback. 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)   
-{
-    DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-    /* Conversion complete callback */
-    HAL_DACEx_ConvHalfCpltCallbackCh2(hdac); 
-}
-
-/**
-  * @brief  DMA error callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)   
-{
-  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-    
-  /* Set DAC error code to DMA error */
-  hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
-    
-  HAL_DACEx_ErrorCallbackCh2(hdac); 
-    
-  hdac->State= HAL_DAC_STATE_READY;
-}
-
-/**
-  * @}
-  */
-
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
-          STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
-          STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx */
-
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_dma.c b/stmhal/hal/f4/src/stm32f4xx_hal_dma.c
deleted file mode 100644
index 326aa0afb9..0000000000
--- a/stmhal/hal/f4/src/stm32f4xx_hal_dma.c
+++ /dev/null
@@ -1,1319 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_dma.c
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   DMA HAL module driver.
-  *    
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the Direct Memory Access (DMA) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral State and errors functions
-  @verbatim     
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-  [..]
-   (#) Enable and configure the peripheral to be connected to the DMA Stream
-       (except for internal SRAM/FLASH memories: no initialization is 
-       necessary) please refer to Reference manual for connection between peripherals
-       and DMA requests.
-
-   (#) For a given Stream, program the required configuration through the following parameters:
-       Transfer Direction, Source and Destination data formats, 
-       Circular, Normal or peripheral flow control mode, Stream Priority level, 
-       Source and Destination Increment mode, FIFO mode and its Threshold (if needed), 
-       Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.
-
-   -@-   Prior to HAL_DMA_Init() the clock must be enabled for DMA through the following macros:
-         __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE().
-
-     *** Polling mode IO operation ***
-     =================================
-    [..]
-          (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source 
-              address and destination address and the Length of data to be transferred.
-          (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this  
-              case a fixed Timeout can be configured by User depending from his application.
-          (+) Use HAL_DMA_Abort() function to abort the current transfer.
-
-     *** Interrupt mode IO operation ***
-     ===================================
-    [..]
-          (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
-          (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() 
-          (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of  
-              Source address and destination address and the Length of data to be transferred. In this 
-              case the DMA interrupt is configured 
-          (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
-          (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can 
-              add his own function by customization of function pointer XferCpltCallback and 
-              XferErrorCallback (i.e a member of DMA handle structure).
-    [..]
-     (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error 
-         detection.
-
-     (#) Use HAL_DMA_Abort_IT() function to abort the current transfer
-
-     -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.
-
-     -@-   The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
-           possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
-           Half-Word data size for the peripheral to access its data register and set Word data size
-           for the Memory to gain in access time. Each two half words will be packed and written in
-           a single access to a Word in the Memory).
-
-     -@-   When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
-           and Destination. In this case the Peripheral Data Size will be applied to both Source
-           and Destination.
-
-     *** DMA HAL driver macros list ***
-     =============================================
-     [..]
-       Below the list of most used macros in DMA HAL driver.
-       
-      (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
-      (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
-      (+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level.
-      (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts.
-      (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts.
-      (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not. 
-
-     [..]
-      (@) You can refer to the DMA HAL driver header file for more useful macros
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup DMA DMA
-  * @brief DMA HAL module driver
-  * @{
-  */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-
-/* Private types -------------------------------------------------------------*/
-typedef struct
-{
-  __IO uint32_t ISR;   /*!< DMA interrupt status register */
-  __IO uint32_t Reserved0;
-  __IO uint32_t IFCR;  /*!< DMA interrupt flag clear register */
-} DMA_Base_Registers;
-
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @addtogroup DMA_Private_Constants
- * @{
- */
- #define HAL_TIMEOUT_DMA_ABORT    ((uint32_t)5)  /* 5 ms */
-/**
-  * @}
-  */
-/* Private macros ------------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/** @addtogroup DMA_Private_Functions
-  * @{
-  */
-static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);
-
-/**
-  * @}
-  */  
-  
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup DMA_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup DMA_Exported_Functions_Group1
-  *
-@verbatim
- ===============================================================================
-             ##### Initialization and de-initialization functions  #####
- ===============================================================================
-    [..]
-    This section provides functions allowing to initialize the DMA Stream source
-    and destination addresses, incrementation and data sizes, transfer direction, 
-    circular/normal mode selection, memory-to-memory mode selection and Stream priority value.
-    [..]
-    The HAL_DMA_Init() function follows the DMA configuration procedures as described in
-    reference manual.
-
-@endverbatim
-  * @{
-  */
-  
-/**
-  * @brief  Initializes the DMA according to the specified
-  *         parameters in the DMA_InitTypeDef and create the associated handle.
-  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Stream.  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
-{
-  uint32_t tmp = 0U;
-  uint32_t tickstart = HAL_GetTick();
-  DMA_Base_Registers *regs;
-
-  /* Check the DMA peripheral state */
-  if(hdma == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
-  assert_param(IS_DMA_CHANNEL(hdma->Init.Channel));
-  assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
-  assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
-  assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
-  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
-  assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
-  assert_param(IS_DMA_MODE(hdma->Init.Mode));
-  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
-  assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode));
-  /* Check the memory burst, peripheral burst and FIFO threshold parameters only
-     when FIFO mode is enabled */
-  if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE)
-  {
-    assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold));
-    assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
-    assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
-  }
-  
-  /* Allocate lock resource */
-  __HAL_UNLOCK(hdma);
-
-  /* Change DMA peripheral state */
-  hdma->State = HAL_DMA_STATE_BUSY;
-  
-  /* Disable the peripheral */
-  __HAL_DMA_DISABLE(hdma);
-  
-  /* Check if the DMA Stream is effectively disabled */
-  while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
-  {
-    /* Check for the Timeout */
-    if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
-    {
-      /* Update error code */
-      hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
-      
-      /* Change the DMA state */
-      hdma->State = HAL_DMA_STATE_TIMEOUT;
-      
-      return HAL_TIMEOUT;
-    }
-  }
-  
-  /* Get the CR register value */
-  tmp = hdma->Instance->CR;
-
-  /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
-  tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
-                      DMA_SxCR_PL    | DMA_SxCR_MSIZE  | DMA_SxCR_PSIZE  | \
-                      DMA_SxCR_MINC  | DMA_SxCR_PINC   | DMA_SxCR_CIRC   | \
-                      DMA_SxCR_DIR   | DMA_SxCR_CT     | DMA_SxCR_DBM));
-
-  /* Prepare the DMA Stream configuration */
-  tmp |=  hdma->Init.Channel             | hdma->Init.Direction        |
-          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
-          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
-          hdma->Init.Mode                | hdma->Init.Priority;
-
-  /* the Memory burst and peripheral burst are not used when the FIFO is disabled */
-  if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
-  {
-    /* Get memory burst and peripheral burst */
-    tmp |=  hdma->Init.MemBurst | hdma->Init.PeriphBurst;
-  }
-  
-  /* Write to DMA Stream CR register */
-  hdma->Instance->CR = tmp;  
-
-  /* Get the FCR register value */
-  tmp = hdma->Instance->FCR;
-
-  /* Clear Direct mode and FIFO threshold bits */
-  tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
-
-  /* Prepare the DMA Stream FIFO configuration */
-  tmp |= hdma->Init.FIFOMode;
-
-  /* the FIFO threshold is not used when the FIFO mode is disabled */
-  if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
-  {
-    /* Get the FIFO threshold */
-    tmp |= hdma->Init.FIFOThreshold;
-    
-    if(DMA_CheckFifoParam(hdma) != HAL_OK)
-    {
-      /* Update error code */
-      hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
-      
-      /* Change the DMA state */
-      hdma->State = HAL_DMA_STATE_READY;
-      
-      return HAL_ERROR; 
-    }
-  }
-  
-  /* Write to DMA Stream FCR */
-  hdma->Instance->FCR = tmp;
-
-  /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
-     DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
-  regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
-  
-  /* Clear all interrupt flags */
-  regs->IFCR = 0x3FU << hdma->StreamIndex;
-
-  /* Initialize the error code */
-  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-                                                                                     
-  /* Initialize the DMA state */
-  hdma->State = HAL_DMA_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the DMA peripheral 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Stream.  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
-{
-  DMA_Base_Registers *regs;
-
-  /* Check the DMA peripheral state */
-  if(hdma == NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  /* Check the DMA peripheral state */
-  if(hdma->State == HAL_DMA_STATE_BUSY)
-  {
-    /* Return error status */
-    return HAL_BUSY;
-  }
-
-  /* Disable the selected DMA Streamx */
-  __HAL_DMA_DISABLE(hdma);
-
-  /* Reset DMA Streamx control register */
-  hdma->Instance->CR   = 0U;
-
-  /* Reset DMA Streamx number of data to transfer register */
-  hdma->Instance->NDTR = 0U;
-
-  /* Reset DMA Streamx peripheral address register */
-  hdma->Instance->PAR  = 0U;
-
-  /* Reset DMA Streamx memory 0 address register */
-  hdma->Instance->M0AR = 0U;
-  
-  /* Reset DMA Streamx memory 1 address register */
-  hdma->Instance->M1AR = 0U;
-  
-  /* Reset DMA Streamx FIFO control register */
-  hdma->Instance->FCR  = (uint32_t)0x00000021U;
-  
-  /* Get DMA steam Base Address */  
-  regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
-  
-  /* Clear all interrupt flags at correct offset within the register */
-  regs->IFCR = 0x3FU << hdma->StreamIndex;
-
-  /* Initialize the error code */
-  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
-  /* Initialize the DMA state */
-  hdma->State = HAL_DMA_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hdma);
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup DMA_Exported_Functions_Group2
-  *
-@verbatim   
- ===============================================================================
-                      #####  IO operation functions  #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Configure the source, destination address and data length and Start DMA transfer
-      (+) Configure the source, destination address and data length and 
-          Start DMA transfer with interrupt
-      (+) Abort DMA transfer
-      (+) Poll for transfer complete
-      (+) Handle DMA interrupt request  
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Starts the DMA Transfer.
-  * @param  hdma      : pointer to a DMA_HandleTypeDef structure that contains
-  *                     the configuration information for the specified DMA Stream.
-  * @param  SrcAddress: The source memory Buffer address
-  * @param  DstAddress: The destination memory Buffer address
-  * @param  DataLength: The length of data to be transferred from source to destination
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-
-  /* Process locked */
-  __HAL_LOCK(hdma);
-
-  if(HAL_DMA_STATE_READY == hdma->State)
-  {
-    /* Change DMA peripheral state */
-    hdma->State = HAL_DMA_STATE_BUSY;
-    
-    /* Initialize the error code */
-    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-    
-    /* Configure the source, destination address and the data length */
-    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
-
-    /* Enable the Peripheral */
-    __HAL_DMA_ENABLE(hdma);
-  }
-  else
-  {
-    /* Process unlocked */
-    __HAL_UNLOCK(hdma);
-    
-    /* Return error status */
-    status = HAL_BUSY;
-  } 
-  return status; 
-}
-
-/**
-  * @brief  Starts the DMA Transfer with interrupt enabled.
-  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
-  *                     the configuration information for the specified DMA Stream.  
-  * @param  SrcAddress: The source memory Buffer address
-  * @param  DstAddress: The destination memory Buffer address
-  * @param  DataLength: The length of data to be transferred from source to destination
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* calculate DMA base and stream number */
-  DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
-  
-  /* Check the parameters */
-  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
- 
-  /* Process locked */
-  __HAL_LOCK(hdma);
-  
-  if(HAL_DMA_STATE_READY == hdma->State)
-  {
-    /* Change DMA peripheral state */
-    hdma->State = HAL_DMA_STATE_BUSY;
-    
-    /* Initialize the error code */
-    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-    
-    /* Configure the source, destination address and the data length */
-    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
-    
-    /* Clear all interrupt flags at correct offset within the register */
-    regs->IFCR = 0x3FU << hdma->StreamIndex;
-    
-    /* Enable Common interrupts*/
-    hdma->Instance->CR  |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
-    hdma->Instance->FCR |= DMA_IT_FE;
-    
-    if(hdma->XferHalfCpltCallback != NULL)
-    {
-      hdma->Instance->CR  |= DMA_IT_HT;
-    }
-    
-    /* Enable the Peripheral */
-    __HAL_DMA_ENABLE(hdma);
-  }
-  else
-  {
-    /* Process unlocked */
-    __HAL_UNLOCK(hdma);	  
-    
-    /* Return error status */
-    status = HAL_BUSY;
-  }
-  
-  return status;
-}
-
-/**
-  * @brief  Aborts the DMA Transfer.
-  * @param  hdma  : pointer to a DMA_HandleTypeDef structure that contains
-  *                 the configuration information for the specified DMA Stream.
-  *                   
-  * @note  After disabling a DMA Stream, a check for wait until the DMA Stream is 
-  *        effectively disabled is added. If a Stream is disabled 
-  *        while a data transfer is ongoing, the current data will be transferred
-  *        and the Stream will be effectively disabled only after the transfer of
-  *        this single data is finished.  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
-{
-  /* calculate DMA base and stream number */
-  DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
-  
-  uint32_t tickstart = HAL_GetTick();
-  
-  if(hdma->State != HAL_DMA_STATE_BUSY)
-  {
-    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hdma);
-    
-    return HAL_ERROR;
-  }
-  else
-  {
-    /* Disable all the transfer interrupts */
-    hdma->Instance->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
-    hdma->Instance->FCR &= ~(DMA_IT_FE);
-    
-    if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
-    {
-      hdma->Instance->CR  &= ~(DMA_IT_HT);
-    }
-    
-    /* Disable the stream */
-    __HAL_DMA_DISABLE(hdma);
-    
-    /* Check if the DMA Stream is effectively disabled */
-    while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
-    {
-      /* Check for the Timeout */
-      if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
-      {
-        /* Update error code */
-        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
-        
-        /* Process Unlocked */
-        __HAL_UNLOCK(hdma);
-        
-        /* Change the DMA state */
-        hdma->State = HAL_DMA_STATE_TIMEOUT;
-        
-        return HAL_TIMEOUT;
-      }
-    }
-    
-    /* Clear all interrupt flags at correct offset within the register */
-    regs->IFCR = 0x3FU << hdma->StreamIndex;
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hdma);
-    
-    /* Change the DMA state*/
-    hdma->State = HAL_DMA_STATE_READY;
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Aborts the DMA Transfer in Interrupt mode.
-  * @param  hdma  : pointer to a DMA_HandleTypeDef structure that contains
-  *                 the configuration information for the specified DMA Stream.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
-{
-  if(hdma->State != HAL_DMA_STATE_BUSY)
-  {
-    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
-    return HAL_ERROR;
-  }
-  else
-  {
-    /* Set Abort State  */
-    hdma->State = HAL_DMA_STATE_ABORT;
-    
-    /* Disable the stream */
-    __HAL_DMA_DISABLE(hdma);
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Polling for transfer complete.
-  * @param  hdma:          pointer to a DMA_HandleTypeDef structure that contains
-  *                        the configuration information for the specified DMA Stream.
-  * @param  CompleteLevel: Specifies the DMA level complete.
-  * @note   The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead.
-  *         This model could be used for debug purpose.
-  * @note   The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode). 
-  * @param  Timeout:       Timeout duration.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
-{
-  HAL_StatusTypeDef status = HAL_OK; 
-  uint32_t mask_cpltlevel;
-  uint32_t tickstart = HAL_GetTick(); 
-  uint32_t tmpisr;
-  
-  /* calculate DMA base and stream number */
-  DMA_Base_Registers *regs;
-
-  if(HAL_DMA_STATE_BUSY != hdma->State)
-  {
-    /* No transfer ongoing */
-    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
-    __HAL_UNLOCK(hdma);
-    return HAL_ERROR;
-  }
-
-  /* Polling mode not supported in circular mode and double buffering mode */
-  if ((hdma->Instance->CR & DMA_SxCR_CIRC) != RESET)
-  {
-    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
-    return HAL_ERROR;
-  }
-  
-  /* Get the level transfer complete flag */
-  if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
-  {
-    /* Transfer Complete flag */
-    mask_cpltlevel = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
-  }
-  else
-  {
-    /* Half Transfer Complete flag */
-    mask_cpltlevel = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
-  }
-  
-  regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
-  tmpisr = regs->ISR;
-  
-  while(((tmpisr & mask_cpltlevel) == RESET) && ((hdma->ErrorCode & HAL_DMA_ERROR_TE) == RESET))
-  {
-    /* Check for the Timeout (Not applicable in circular mode)*/
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        /* Update error code */
-        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hdma);
-        
-        /* Change the DMA state */
-        hdma->State = HAL_DMA_STATE_READY;
-        
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Get the ISR register value */
-    tmpisr = regs->ISR;
-
-    if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
-    {
-      /* Update error code */
-      hdma->ErrorCode |= HAL_DMA_ERROR_TE;
-      
-      /* Clear the transfer error flag */
-      regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
-    }
-    
-    if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
-    {
-      /* Update error code */
-      hdma->ErrorCode |= HAL_DMA_ERROR_FE;
-      
-      /* Clear the FIFO error flag */
-      regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
-    }
-    
-    if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
-    {
-      /* Update error code */
-      hdma->ErrorCode |= HAL_DMA_ERROR_DME;
-      
-      /* Clear the Direct Mode error flag */
-      regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
-    }
-  }
-  
-  if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
-  {
-    if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
-    {
-      HAL_DMA_Abort(hdma);
-    
-      /* Clear the half transfer and transfer complete flags */
-      regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
-    
-      /* Process Unlocked */
-      __HAL_UNLOCK(hdma);
-
-      /* Change the DMA state */
-      hdma->State= HAL_DMA_STATE_READY;
-
-      return HAL_ERROR;
-   }
-
-  }
-
-  /* Get the level transfer complete flag */
-  if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
-  {
-    /* Clear the half transfer and transfer complete flags */
-    regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hdma);
-
-    hdma->State = HAL_DMA_STATE_READY;
-  }
-  else
-  {
-    /* Clear the half transfer and transfer complete flags */
-    regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex;
-  }
-  
-  return status;
-}
-
-/**
-  * @brief  Handles DMA interrupt request.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Stream.  
-  * @retval None
-  */
-void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
-{
-  uint32_t tmpisr;
-  __IO uint32_t count = 0;
-  uint32_t timeout = SystemCoreClock / 9600;
-
-  /* calculate DMA base and stream number */
-  DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
-
-  tmpisr = regs->ISR;
-
-  /* Transfer Error Interrupt management ***************************************/
-  if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
-  {
-    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
-    {
-      /* Disable the transfer error interrupt */
-      hdma->Instance->CR  &= ~(DMA_IT_TE);
-      
-      /* Clear the transfer error flag */
-      regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
-      
-      /* Update error code */
-      hdma->ErrorCode |= HAL_DMA_ERROR_TE;
-    }
-  }
-  /* FIFO Error Interrupt management ******************************************/
-  if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
-  {
-    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)
-    {
-      /* Clear the FIFO error flag */
-      regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
-
-      /* Update error code */
-      hdma->ErrorCode |= HAL_DMA_ERROR_FE;
-    }
-  }
-  /* Direct Mode Error Interrupt management ***********************************/
-  if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
-  {
-    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)
-    {
-      /* Clear the direct mode error flag */
-      regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
-
-      /* Update error code */
-      hdma->ErrorCode |= HAL_DMA_ERROR_DME;
-    }
-  }
-  /* Half Transfer Complete Interrupt management ******************************/
-  if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)
-  {
-    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
-    {
-      /* Clear the half transfer complete flag */
-      regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
-      
-      /* Multi_Buffering mode enabled */
-      if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
-      {
-        /* Current memory buffer used is Memory 0 */
-        if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
-        {
-          if(hdma->XferHalfCpltCallback != NULL)
-          {
-            /* Half transfer callback */
-            hdma->XferHalfCpltCallback(hdma);
-          }
-        }
-        /* Current memory buffer used is Memory 1 */
-        else
-        {
-          if(hdma->XferM1HalfCpltCallback != NULL)
-          {
-            /* Half transfer callback */
-            hdma->XferM1HalfCpltCallback(hdma);
-          }
-        }
-      }
-      else
-      {
-        /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
-        if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
-        {
-          /* Disable the half transfer interrupt */
-          hdma->Instance->CR  &= ~(DMA_IT_HT);
-        }
-        
-        if(hdma->XferHalfCpltCallback != NULL)
-        {
-          /* Half transfer callback */
-          hdma->XferHalfCpltCallback(hdma);
-        }
-      }
-    }
-  }
-  /* Transfer Complete Interrupt management ***********************************/
-  if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)
-  {
-    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
-    {
-      /* Clear the transfer complete flag */
-      regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
-      
-      if(HAL_DMA_STATE_ABORT == hdma->State)
-      {
-        /* Disable all the transfer interrupts */
-        hdma->Instance->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
-        hdma->Instance->FCR &= ~(DMA_IT_FE);
-        
-        if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
-        {
-          hdma->Instance->CR  &= ~(DMA_IT_HT);
-        }
-
-        /* Clear all interrupt flags at correct offset within the register */
-        regs->IFCR = 0x3FU << hdma->StreamIndex;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hdma);
-
-        /* Change the DMA state */
-        hdma->State = HAL_DMA_STATE_READY;
-
-        if(hdma->XferAbortCallback != NULL)
-        {
-          hdma->XferAbortCallback(hdma);
-        }
-        return;
-      }
-
-      if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
-      {
-        /* Current memory buffer used is Memory 0 */
-        if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
-        {
-          if(hdma->XferM1CpltCallback != NULL)
-          {
-            /* Transfer complete Callback for memory1 */
-            hdma->XferM1CpltCallback(hdma);
-          }
-        }
-        /* Current memory buffer used is Memory 1 */
-        else
-        {
-          if(hdma->XferCpltCallback != NULL)
-          {
-            /* Transfer complete Callback for memory0 */
-            hdma->XferCpltCallback(hdma);
-          }
-        }
-      }
-      /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
-      else
-      {
-        if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
-        {
-          /* Disable the transfer complete interrupt */
-          hdma->Instance->CR  &= ~(DMA_IT_TC);
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hdma);
-
-          /* Change the DMA state */
-          hdma->State = HAL_DMA_STATE_READY;
-        }
-
-        if(hdma->XferCpltCallback != NULL)
-        {
-          /* Transfer complete callback */
-          hdma->XferCpltCallback(hdma);
-        }
-      }
-    }
-  }
-  
-  /* manage error case */
-  if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
-  {
-    if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
-    {
-      hdma->State = HAL_DMA_STATE_ABORT;
-
-      /* Disable the stream */
-      __HAL_DMA_DISABLE(hdma);
-
-      do
-      {
-        if (++count > timeout)
-        {
-          break;
-        }
-      }
-      while((hdma->Instance->CR & DMA_SxCR_EN) != RESET);
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hdma);
-
-      /* Change the DMA state */
-      hdma->State = HAL_DMA_STATE_READY;
-    }
-
-    if(hdma->XferErrorCallback != NULL)
-    {
-      /* Transfer error callback */
-      hdma->XferErrorCallback(hdma);
-    }
-  }
-}
-
-/**
-  * @brief  Register callbacks
-  * @param  hdma:                 pointer to a DMA_HandleTypeDef structure that contains
-  *                               the configuration information for the specified DMA Stream.
-  * @param  CallbackID:           User Callback identifer
-  *                               a DMA_HandleTypeDef structure as parameter.
-  * @param  pCallback:            pointer to private callbacsk function which has pointer to 
-  *                               a DMA_HandleTypeDef structure as parameter.
-  * @retval HAL status
-  */                      
-HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))
-{
-
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hdma);
-
-  if(HAL_DMA_STATE_READY == hdma->State)
-  {
-    switch (CallbackID)
-    {
-    case  HAL_DMA_XFER_CPLT_CB_ID:
-      hdma->XferCpltCallback = pCallback;
-      break;
-
-    case  HAL_DMA_XFER_HALFCPLT_CB_ID:
-      hdma->XferHalfCpltCallback = pCallback;
-      break;
-
-    case  HAL_DMA_XFER_M1CPLT_CB_ID:
-      hdma->XferM1CpltCallback = pCallback;
-      break;
-
-    case  HAL_DMA_XFER_M1HALFCPLT_CB_ID:
-      hdma->XferM1HalfCpltCallback = pCallback;
-      break;
-
-    case  HAL_DMA_XFER_ERROR_CB_ID:
-      hdma->XferErrorCallback = pCallback;
-      break;
-
-    case  HAL_DMA_XFER_ABORT_CB_ID:
-      hdma->XferAbortCallback = pCallback;
-      break;
-
-    default:
-      break;
-    }
-  }
-  else
-  {
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hdma);
-  
-  return status;
-}
-
-/**
-  * @brief  UnRegister callbacks
-  * @param  hdma:                 pointer to a DMA_HandleTypeDef structure that contains
-  *                               the configuration information for the specified DMA Stream.
-  * @param  CallbackID:           User Callback identifer
-  *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
-  * @retval HAL status
-  */              
-HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Process locked */
-  __HAL_LOCK(hdma);
-  
-  if(HAL_DMA_STATE_READY == hdma->State)
-  {
-    switch (CallbackID)
-    {
-    case  HAL_DMA_XFER_CPLT_CB_ID:
-      hdma->XferCpltCallback = NULL;
-      break;
-      
-    case  HAL_DMA_XFER_HALFCPLT_CB_ID:
-      hdma->XferHalfCpltCallback = NULL;
-      break;
-      
-    case  HAL_DMA_XFER_M1CPLT_CB_ID:
-      hdma->XferM1CpltCallback = NULL;
-      break;
-      
-    case  HAL_DMA_XFER_M1HALFCPLT_CB_ID:
-      hdma->XferM1HalfCpltCallback = NULL;
-      break;
-      
-    case  HAL_DMA_XFER_ERROR_CB_ID:
-      hdma->XferErrorCallback = NULL;
-      break;
-      
-    case  HAL_DMA_XFER_ABORT_CB_ID:
-      hdma->XferAbortCallback = NULL;
-      break; 
-      
-    case   HAL_DMA_XFER_ALL_CB_ID:
-      hdma->XferCpltCallback = NULL;
-      hdma->XferHalfCpltCallback = NULL;
-      hdma->XferM1CpltCallback = NULL;
-      hdma->XferM1HalfCpltCallback = NULL;
-      hdma->XferErrorCallback = NULL;
-      hdma->XferAbortCallback = NULL;
-      break; 
-      
-    default:
-      status = HAL_ERROR;
-      break;
-    }
-  }
-  else
-  {
-    status = HAL_ERROR;
-  }
-  
-  /* Release Lock */
-  __HAL_UNLOCK(hdma);
-  
-  return status;
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup DMA_Exported_Functions_Group3
-  *
-@verbatim
- ===============================================================================
-                    ##### State and Errors functions #####
- ===============================================================================
-    [..]
-    This subsection provides functions allowing to
-      (+) Check the DMA state
-      (+) Get error code
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Returns the DMA state.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Stream.
-  * @retval HAL state
-  */
-HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
-{
-  return hdma->State;
-}
-
-/**
-  * @brief  Return the DMA error code
-  * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains
-  *              the configuration information for the specified DMA Stream.
-  * @retval DMA Error Code
-  */
-uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
-{
-  return hdma->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup DMA_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Sets the DMA Transfer parameter.
-  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
-  *                     the configuration information for the specified DMA Stream.
-  * @param  SrcAddress: The source memory Buffer address
-  * @param  DstAddress: The destination memory Buffer address
-  * @param  DataLength: The length of data to be transferred from source to destination
-  * @retval HAL status
-  */
-static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{
-  /* Clear DBM bit */
-  hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM);
-
-  /* Configure DMA Stream data length */
-  hdma->Instance->NDTR = DataLength;
-
-  /* Peripheral to Memory */
-  if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
-  {
-    /* Configure DMA Stream destination address */
-    hdma->Instance->PAR = DstAddress;
-
-    /* Configure DMA Stream source address */
-    hdma->Instance->M0AR = SrcAddress;
-  }
-  /* Memory to Peripheral */
-  else
-  {
-    /* Configure DMA Stream source address */
-    hdma->Instance->PAR = SrcAddress;
-
-    /* Configure DMA Stream destination address */
-    hdma->Instance->M0AR = DstAddress;
-  }
-}
-
-/**
-  * @brief  Returns the DMA Stream base address depending on stream number
-  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
-  *                     the configuration information for the specified DMA Stream. 
-  * @retval Stream base address
-  */
-uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
-{
-  uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U;
-  
-  /* lookup table for necessary bitshift of flags within status registers */
-  static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};
-  hdma->StreamIndex = flagBitshiftOffset[stream_number];
-  
-  if (stream_number > 3U)
-  {
-    /* return pointer to HISR and HIFCR */
-    hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U);
-  }
-  else
-  {
-    /* return pointer to LISR and LIFCR */
-    hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU));
-  }
-  
-  return hdma->StreamBaseAddress;
-}
-
-/**
-  * @brief  Checks compatibility between FIFO threshold level and size of the memory burst
-  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
-  *                     the configuration information for the specified DMA Stream. 
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  uint32_t tmp = hdma->Init.FIFOThreshold;
-  
-  /* Memory Data size equal to Byte */
-  if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)
-  {
-    switch (tmp)
-    {
-      case DMA_FIFO_THRESHOLD_1QUARTERFULL:
-        if((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
-        {
-          status = HAL_ERROR;
-        }
-        break;
-      case DMA_FIFO_THRESHOLD_HALFFULL:
-        if(hdma->Init.MemBurst == DMA_MBURST_INC16)
-        {
-          status = HAL_ERROR;
-        }
-        break;
-      case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
-        if((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
-        {
-          status = HAL_ERROR;
-        }
-        break;
-      case DMA_FIFO_THRESHOLD_FULL:
-        break;
-      default:
-        break;
-    }
-  }
-  
-  /* Memory Data size equal to Half-Word */
-  else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
-  {
-    switch (tmp)
-    {
-      case DMA_FIFO_THRESHOLD_1QUARTERFULL:
-        status = HAL_ERROR;
-        break;
-      case DMA_FIFO_THRESHOLD_HALFFULL:
-        if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
-        {
-          status = HAL_ERROR;
-        }
-        break;
-      case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
-        status = HAL_ERROR;
-        break;
-      case DMA_FIFO_THRESHOLD_FULL:
-        if (hdma->Init.MemBurst == DMA_MBURST_INC16)
-        {
-          status = HAL_ERROR;
-        }
-        break;   
-      default:
-        break;
-    }
-  }
-  
-  /* Memory Data size equal to Word */
-  else
-  {
-    switch (tmp)
-    {
-      case DMA_FIFO_THRESHOLD_1QUARTERFULL:
-      case DMA_FIFO_THRESHOLD_HALFFULL:
-      case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
-        status = HAL_ERROR;
-        break;
-      case DMA_FIFO_THRESHOLD_FULL:
-        if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
-        {
-          status = HAL_ERROR;
-        }
-		break;
-      default:
-        break;
-    }
-  } 
-  
-  return status; 
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_DMA_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_flash.c b/stmhal/hal/f4/src/stm32f4xx_hal_flash.c
deleted file mode 100644
index e14f236564..0000000000
--- a/stmhal/hal/f4/src/stm32f4xx_hal_flash.c
+++ /dev/null
@@ -1,775 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_flash.c
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   FLASH HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the internal FLASH memory:
-  *           + Program operations functions
-  *           + Memory Control functions 
-  *           + Peripheral Errors functions
-  *         
-  @verbatim
-  ==============================================================================
-                        ##### FLASH peripheral features #####
-  ==============================================================================
-           
-  [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses 
-       to the Flash memory. It implements the erase and program Flash memory operations 
-       and the read and write protection mechanisms.
-      
-  [..] The Flash memory interface accelerates code execution with a system of instruction
-       prefetch and cache lines. 
-
-  [..] The FLASH main features are:
-      (+) Flash memory read operations
-      (+) Flash memory program/erase operations
-      (+) Read / write protections
-      (+) Prefetch on I-Code
-      (+) 64 cache lines of 128 bits on I-Code
-      (+) 8 cache lines of 128 bits on D-Code
-      
-      
-                     ##### How to use this driver #####
-  ==============================================================================
-    [..]                             
-      This driver provides functions and macros to configure and program the FLASH 
-      memory of all STM32F4xx devices.
-    
-      (#) FLASH Memory IO Programming functions: 
-           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and 
-                HAL_FLASH_Lock() functions
-           (++) Program functions: byte, half word, word and double word
-           (++) There Two modes of programming :
-            (+++) Polling mode using HAL_FLASH_Program() function
-            (+++) Interrupt mode using HAL_FLASH_Program_IT() function
-    
-      (#) Interrupts and flags management functions : 
-           (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
-           (++) Wait for last FLASH operation according to its status
-           (++) Get error flag status by calling HAL_SetErrorCode()          
-
-    [..] 
-      In addition to these functions, this driver includes a set of macros allowing
-      to handle the following operations:
-       (+) Set the latency
-       (+) Enable/Disable the prefetch buffer
-       (+) Enable/Disable the Instruction cache and the Data cache
-       (+) Reset the Instruction cache and the Data cache
-       (+) Enable/Disable the FLASH interrupts
-       (+) Monitor the FLASH flags status
-          
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup FLASH FLASH
-  * @brief FLASH HAL module driver
-  * @{
-  */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup FLASH_Private_Constants
-  * @{
-  */
-#define FLASH_TIMEOUT_VALUE       ((uint32_t)50000U)/* 50 s */
-/**
-  * @}
-  */         
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @addtogroup FLASH_Private_Variables
-  * @{
-  */
-/* Variable used for Erase sectors under interruption */
-FLASH_ProcessTypeDef pFlash;
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup FLASH_Private_Functions
-  * @{
-  */
-/* Program operations */
-static void   FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);
-static void   FLASH_Program_Word(uint32_t Address, uint32_t Data);
-static void   FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);
-static void   FLASH_Program_Byte(uint32_t Address, uint8_t Data);
-static void   FLASH_SetErrorCode(void);
-
-HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
-  * @{
-  */
-  
-/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions 
- *  @brief   Programming operation functions 
- *
-@verbatim   
- ===============================================================================
-                  ##### Programming operation functions #####
- ===============================================================================  
-    [..]
-    This subsection provides a set of functions allowing to manage the FLASH 
-    program operations.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Program byte, halfword, word or double word at a specified address
-  * @param  TypeProgram:  Indicate the way to program at a specified address.
-  *                           This parameter can be a value of @ref FLASH_Type_Program
-  * @param  Address:  specifies the address to be programmed.
-  * @param  Data: specifies the data to be programmed
-  * 
-  * @retval HAL_StatusTypeDef HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
-{
-  HAL_StatusTypeDef status = HAL_ERROR;
-  
-  /* Process Locked */
-  __HAL_LOCK(&pFlash);
-  
-  /* Check the parameters */
-  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
-  
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-  
-  if(status == HAL_OK)
-  {
-    if(TypeProgram == FLASH_TYPEPROGRAM_BYTE)
-    {
-      /*Program byte (8-bit) at a specified address.*/
-      FLASH_Program_Byte(Address, (uint8_t) Data);
-    }
-    else if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
-    {
-      /*Program halfword (16-bit) at a specified address.*/
-      FLASH_Program_HalfWord(Address, (uint16_t) Data);
-    }
-    else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
-    {
-      /*Program word (32-bit) at a specified address.*/
-      FLASH_Program_Word(Address, (uint32_t) Data);
-    }
-    else
-    {
-      /*Program double word (64-bit) at a specified address.*/
-      FLASH_Program_DoubleWord(Address, Data);
-    }
-    
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-    
-    /* If the program operation is completed, disable the PG Bit */
-    FLASH->CR &= (~FLASH_CR_PG);  
-  }
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(&pFlash);
-  
-  return status;
-}
-
-/**
-  * @brief   Program byte, halfword, word or double word at a specified address  with interrupt enabled.
-  * @param  TypeProgram:  Indicate the way to program at a specified address.
-  *                           This parameter can be a value of @ref FLASH_Type_Program
-  * @param  Address:  specifies the address to be programmed.
-  * @param  Data: specifies the data to be programmed
-  * 
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Process Locked */
-  __HAL_LOCK(&pFlash);
-
-  /* Check the parameters */
-  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
-
-  /* Enable End of FLASH Operation interrupt */
-  __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
-  
-  /* Enable Error source interrupt */
-  __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
-
-  pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;
-  pFlash.Address = Address;
-
-  if(TypeProgram == FLASH_TYPEPROGRAM_BYTE)
-  {
-    /*Program byte (8-bit) at a specified address.*/
-      FLASH_Program_Byte(Address, (uint8_t) Data);
-  }
-  else if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
-  {
-    /*Program halfword (16-bit) at a specified address.*/
-    FLASH_Program_HalfWord(Address, (uint16_t) Data);
-  }
-  else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
-  {
-    /*Program word (32-bit) at a specified address.*/
-    FLASH_Program_Word(Address, (uint32_t) Data);
-  }
-  else
-  {
-    /*Program double word (64-bit) at a specified address.*/
-    FLASH_Program_DoubleWord(Address, Data);
-  }
-
-  return status;
-}
-
-/**
-  * @brief This function handles FLASH interrupt request.
-  * @retval None
-  */
-void HAL_FLASH_IRQHandler(void)
-{
-  uint32_t addresstmp = 0U;
-  
-  /* Check FLASH operation error flags */
-  if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
-    FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR)) != RESET)
-  {
-    if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE)
-    {
-      /*return the faulty sector*/
-      addresstmp = pFlash.Sector;
-      pFlash.Sector = 0xFFFFFFFFU;
-    }
-    else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
-    {
-      /*return the faulty bank*/
-      addresstmp = pFlash.Bank;
-    }
-    else
-    {
-      /*return the faulty address*/
-      addresstmp = pFlash.Address;
-    }
-    
-    /*Save the Error code*/
-    FLASH_SetErrorCode();
-    
-    /* FLASH error interrupt user callback */
-    HAL_FLASH_OperationErrorCallback(addresstmp);
-    
-    /*Stop the procedure ongoing*/
-    pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
-  }
-  
-  /* Check FLASH End of Operation flag  */
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)
-  {
-    /* Clear FLASH End of Operation pending bit */
-    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
-    
-    if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE)
-    {
-      /*Nb of sector to erased can be decreased*/
-      pFlash.NbSectorsToErase--;
-      
-      /* Check if there are still sectors to erase*/
-      if(pFlash.NbSectorsToErase != 0U)
-      {
-        addresstmp = pFlash.Sector;
-        /*Indicate user which sector has been erased*/
-        HAL_FLASH_EndOfOperationCallback(addresstmp);
-        
-        /*Increment sector number*/
-        pFlash.Sector++;
-        addresstmp = pFlash.Sector;
-        FLASH_Erase_Sector(addresstmp, pFlash.VoltageForErase);
-      }
-      else
-      {
-        /*No more sectors to Erase, user callback can be called.*/
-        /*Reset Sector and stop Erase sectors procedure*/
-        pFlash.Sector = addresstmp = 0xFFFFFFFFU;
-        pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
-        
-        /* Flush the caches to be sure of the data consistency */
-        FLASH_FlushCaches() ;
-                
-        /* FLASH EOP interrupt user callback */
-        HAL_FLASH_EndOfOperationCallback(addresstmp);
-      }
-    }
-    else 
-    {
-      if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) 
-      {
-        /* MassErase ended. Return the selected bank */
-        /* Flush the caches to be sure of the data consistency */
-        FLASH_FlushCaches() ;
-
-        /* FLASH EOP interrupt user callback */
-        HAL_FLASH_EndOfOperationCallback(pFlash.Bank);
-      }
-      else
-      {
-        /*Program ended. Return the selected address*/
-        /* FLASH EOP interrupt user callback */
-        HAL_FLASH_EndOfOperationCallback(pFlash.Address);
-      }
-      pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
-    }
-  }
-  
-  if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
-  {
-    /* Operation is completed, disable the PG, SER, SNB and MER Bits */
-    CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_SER | FLASH_CR_SNB | FLASH_MER_BIT));
-
-    /* Disable End of FLASH Operation interrupt */
-    __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP);
-    
-    /* Disable Error source interrupt */
-    __HAL_FLASH_DISABLE_IT(FLASH_IT_ERR);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(&pFlash);
-  }
-}
-
-/**
-  * @brief  FLASH end of operation interrupt callback
-  * @param  ReturnValue: The value saved in this parameter depends on the ongoing procedure
-  *                  Mass Erase: Bank number which has been requested to erase
-  *                  Sectors Erase: Sector which has been erased 
-  *                    (if 0xFFFFFFFFU, it means that all the selected sectors have been erased)
-  *                  Program: Address which was selected for data program
-  * @retval None
-  */
-__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(ReturnValue);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  FLASH operation error interrupt callback
-  * @param  ReturnValue: The value saved in this parameter depends on the ongoing procedure
-  *                 Mass Erase: Bank number which has been requested to erase
-  *                 Sectors Erase: Sector number which returned an error
-  *                 Program: Address which was selected for data program
-  * @retval None
-  */
-__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(ReturnValue);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_FLASH_OperationErrorCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions 
- *  @brief   management functions 
- *
-@verbatim   
- ===============================================================================
-                      ##### Peripheral Control functions #####
- ===============================================================================  
-    [..]
-    This subsection provides a set of functions allowing to control the FLASH 
-    memory operations.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Unlock the FLASH control register access
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_Unlock(void)
-{
-  if((FLASH->CR & FLASH_CR_LOCK) != RESET)
-  {
-    /* Authorize the FLASH Registers access */
-    FLASH->KEYR = FLASH_KEY1;
-    FLASH->KEYR = FLASH_KEY2;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-  
-  return HAL_OK; 
-}
-
-/**
-  * @brief  Locks the FLASH control register access
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_Lock(void)
-{
-  /* Set the LOCK Bit to lock the FLASH Registers access */
-  FLASH->CR |= FLASH_CR_LOCK;
-  
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Unlock the FLASH Option Control Registers access.
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
-{
-  if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET)
-  {
-    /* Authorizes the Option Byte register programming */
-    FLASH->OPTKEYR = FLASH_OPT_KEY1;
-    FLASH->OPTKEYR = FLASH_OPT_KEY2;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }  
-  
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Lock the FLASH Option Control Registers access.
-  * @retval HAL Status 
-  */
-HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
-{
-  /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
-  FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;
-  
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Launch the option byte loading.
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
-{
-  /* Set the OPTSTRT bit in OPTCR register */
-  *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= FLASH_OPTCR_OPTSTRT;
-
-  /* Wait for last operation to be completed */
-  return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE)); 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions 
- *  @brief   Peripheral Errors functions 
- *
-@verbatim   
- ===============================================================================
-                ##### Peripheral Errors functions #####
- ===============================================================================  
-    [..]
-    This subsection permits to get in run-time Errors of the FLASH peripheral.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Get the specific FLASH error flag.
-  * @retval FLASH_ErrorCode: The returned value can be a combination of:
-  *            @arg HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP)
-  *            @arg HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag 
-  *            @arg HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag  
-  *            @arg HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag
-  *            @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag
-  *            @arg HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag 
-  */
-uint32_t HAL_FLASH_GetError(void)
-{ 
-   return pFlash.ErrorCode;
-}  
-  
-/**
-  * @}
-  */    
-
-/**
-  * @brief  Wait for a FLASH operation to complete.
-  * @param  Timeout: maximum flash operationtimeout
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
-{ 
-  uint32_t tickstart = 0U;
-  
-  /* Clear Error Code */
-  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-  
-  /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
-     Even if the FLASH operation fails, the BUSY flag will be reset and an error
-     flag will be set */
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET) 
-  { 
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        return HAL_TIMEOUT;
-      }
-    } 
-  }
-
-  /* Check FLASH End of Operation flag  */
-  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
-  {
-    /* Clear FLASH End of Operation pending bit */
-    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
-  }
-  
-  if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
-                           FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR)) != RESET)
-  {
-    /*Save the error code*/
-    FLASH_SetErrorCode();
-    return HAL_ERROR;
-  }
-
-  /* If there is no error flag set */
-  return HAL_OK;
-  
-}  
-
-/**
-  * @brief  Program a double word (64-bit) at a specified address.
-  * @note   This function must be used when the device voltage range is from
-  *         2.7V to 3.6V and Vpp in the range 7V to 9V.
-  *
-  * @note   If an erase and a program operations are requested simultaneously,    
-  *         the erase operation is performed before the program one.
-  *  
-  * @param  Address: specifies the address to be programmed.
-  * @param  Data: specifies the data to be programmed.
-  * @retval None
-  */
-static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
-{
-  /* Check the parameters */
-  assert_param(IS_FLASH_ADDRESS(Address));
-  
-  /* If the previous operation is completed, proceed to program the new data */
-  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
-  FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;
-  FLASH->CR |= FLASH_CR_PG;
-
-  *(__IO uint64_t*)Address = Data;
-}
-
-
-/**
-  * @brief  Program word (32-bit) at a specified address.
-  * @note   This function must be used when the device voltage range is from
-  *         2.7V to 3.6V.
-  *
-  * @note   If an erase and a program operations are requested simultaneously,    
-  *         the erase operation is performed before the program one.
-  *  
-  * @param  Address: specifies the address to be programmed.
-  * @param  Data: specifies the data to be programmed.
-  * @retval None
-  */
-static void FLASH_Program_Word(uint32_t Address, uint32_t Data)
-{
-  /* Check the parameters */
-  assert_param(IS_FLASH_ADDRESS(Address));
-  
-  /* If the previous operation is completed, proceed to program the new data */
-  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
-  FLASH->CR |= FLASH_PSIZE_WORD;
-  FLASH->CR |= FLASH_CR_PG;
-
-  *(__IO uint32_t*)Address = Data;
-}
-
-/**
-  * @brief  Program a half-word (16-bit) at a specified address.
-  * @note   This function must be used when the device voltage range is from
-  *         2.1V to 3.6V.
-  *
-  * @note   If an erase and a program operations are requested simultaneously,    
-  *         the erase operation is performed before the program one.
-  *  
-  * @param  Address: specifies the address to be programmed.
-  * @param  Data: specifies the data to be programmed.
-  * @retval None
-  */
-static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
-{
-  /* Check the parameters */
-  assert_param(IS_FLASH_ADDRESS(Address));
-  
-  /* If the previous operation is completed, proceed to program the new data */
-  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
-  FLASH->CR |= FLASH_PSIZE_HALF_WORD;
-  FLASH->CR |= FLASH_CR_PG;
-
-  *(__IO uint16_t*)Address = Data;
-}
-
-/**
-  * @brief  Program byte (8-bit) at a specified address.
-  * @note   This function must be used when the device voltage range is from
-  *         1.8V to 3.6V.
-  *
-  * @note   If an erase and a program operations are requested simultaneously,    
-  *         the erase operation is performed before the program one.
-  *  
-  * @param  Address: specifies the address to be programmed.
-  * @param  Data: specifies the data to be programmed.
-  * @retval None
-  */
-static void FLASH_Program_Byte(uint32_t Address, uint8_t Data)
-{
-  /* Check the parameters */
-  assert_param(IS_FLASH_ADDRESS(Address));
-  
-  /* If the previous operation is completed, proceed to program the new data */
-  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
-  FLASH->CR |= FLASH_PSIZE_BYTE;
-  FLASH->CR |= FLASH_CR_PG;
-
-  *(__IO uint8_t*)Address = Data;
-}
-
-/**
-  * @brief  Set the specific FLASH error flag.
-  * @retval None
-  */
-static void FLASH_SetErrorCode(void)
-{ 
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET)
-  {
-   pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
-   
-   /* Clear FLASH write protection error pending bit */
-   __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR);
-  }
-  
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET)
-  {
-   pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;
-   
-   /* Clear FLASH Programming alignment error pending bit */
-   __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGAERR);
-  }
-  
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGPERR) != RESET)
-  {
-    pFlash.ErrorCode |= HAL_FLASH_ERROR_PGP;
-    
-    /* Clear FLASH Programming parallelism error pending bit */
-    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGPERR);
-  }
-  
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR) != RESET)
-  {
-    pFlash.ErrorCode |= HAL_FLASH_ERROR_PGS;
-    
-    /* Clear FLASH Programming sequence error pending bit */
-    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGSERR);
-  }
-  
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET)
-  {
-    pFlash.ErrorCode |= HAL_FLASH_ERROR_RD;
-    
-    /* Clear FLASH Proprietary readout protection error pending bit */
-    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_RDERR);
-  }
-  
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET)
-  {
-    pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION;
-    
-    /* Clear FLASH Operation error pending bit */
-    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPERR);
-  }
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_flash_ex.c b/stmhal/hal/f4/src/stm32f4xx_hal_flash_ex.c
deleted file mode 100644
index 859fdbc026..0000000000
--- a/stmhal/hal/f4/src/stm32f4xx_hal_flash_ex.c
+++ /dev/null
@@ -1,1359 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_flash_ex.c
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   Extended FLASH HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the FLASH extension peripheral:
-  *           + Extended programming operations functions
-  *  
-  @verbatim
-  ==============================================================================
-                   ##### Flash Extension features #####
-  ==============================================================================
-           
-  [..] Comparing to other previous devices, the FLASH interface for STM32F427xx/437xx and 
-       STM32F429xx/439xx devices contains the following additional features 
-       
-       (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
-           capability (RWW)
-       (+) Dual bank memory organization       
-       (+) PCROP protection for all banks
-   
-                      ##### How to use this driver #####
-  ==============================================================================
-  [..] This driver provides functions to configure and program the FLASH memory 
-       of all STM32F427xx/437xx, STM32F429xx/439xx, STM32F469xx/479xx and STM32F446xx 
-       devices. It includes
-      (#) FLASH Memory Erase functions: 
-           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and 
-                HAL_FLASH_Lock() functions
-           (++) Erase function: Erase sector, erase all sectors
-           (++) There are two modes of erase :
-             (+++) Polling Mode using HAL_FLASHEx_Erase()
-             (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
-             
-      (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to :
-           (++) Set/Reset the write protection
-           (++) Set the Read protection Level
-           (++) Set the BOR level
-           (++) Program the user Option Bytes
-      (#) Advanced Option Bytes Programming functions: Use HAL_FLASHEx_AdvOBProgram() to :  
-       (++) Extended space (bank 2) erase function
-       (++) Full FLASH space (2 Mo) erase (bank 1 and bank 2)
-       (++) Dual Boot activation
-       (++) Write protection configuration for bank 2
-       (++) PCROP protection configuration and control for both banks
-  
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup FLASHEx FLASHEx
-  * @brief FLASH HAL Extension module driver
-  * @{
-  */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup FLASHEx_Private_Constants
-  * @{
-  */    
-#define FLASH_TIMEOUT_VALUE       ((uint32_t)50000U)/* 50 s */
-/**
-  * @}
-  */
-    
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @addtogroup FLASHEx_Private_Variables
-  * @{
-  */    
-extern FLASH_ProcessTypeDef pFlash;
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup FLASHEx_Private_Functions
-  * @{
-  */
-/* Option bytes control */
-static void               FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks);
-static HAL_StatusTypeDef  FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks);
-static HAL_StatusTypeDef  FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks);
-static HAL_StatusTypeDef  FLASH_OB_RDP_LevelConfig(uint8_t Level);
-static HAL_StatusTypeDef  FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t Stdby);
-static HAL_StatusTypeDef  FLASH_OB_BOR_LevelConfig(uint8_t Level);
-static uint8_t            FLASH_OB_GetUser(void);
-static uint16_t           FLASH_OB_GetWRP(void);
-static uint8_t            FLASH_OB_GetRDP(void);
-static uint8_t            FLASH_OB_GetBOR(void);
-
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\
-    defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
-static HAL_StatusTypeDef  FLASH_OB_EnablePCROP(uint32_t Sector);
-static HAL_StatusTypeDef  FLASH_OB_DisablePCROP(uint32_t Sector);
-#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 
-static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks);
-static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks);
-static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t BootConfig);
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-
-extern HAL_StatusTypeDef         FLASH_WaitForLastOperation(uint32_t Timeout);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
-  * @{
-  */
-
-/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
- *  @brief   Extended IO operation functions 
- *
-@verbatim   
- ===============================================================================
-                ##### Extended programming operation functions #####
- ===============================================================================  
-    [..]
-    This subsection provides a set of functions allowing to manage the Extension FLASH 
-    programming operations.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Perform a mass erase or erase the specified FLASH memory sectors 
-  * @param[in]  pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
-  *         contains the configuration information for the erasing.
-  * 
-  * @param[out]  SectorError: pointer to variable  that
-  *         contains the configuration information on faulty sector in case of error 
-  *         (0xFFFFFFFFU means that all the sectors have been correctly erased)
-  * 
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
-{
-  HAL_StatusTypeDef status = HAL_ERROR;
-  uint32_t index = 0U;
-  
-  /* Process Locked */
-  __HAL_LOCK(&pFlash);
-
-  /* Check the parameters */
-  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-  if(status == HAL_OK)
-  {
-    /*Initialization of SectorError variable*/
-    *SectorError = 0xFFFFFFFFU;
-    
-    if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
-    {
-      /*Mass erase to be done*/
-      FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);
-
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-      
-      /* if the erase operation is completed, disable the MER Bit */
-      FLASH->CR &= (~FLASH_MER_BIT);
-    }
-    else
-    {
-      /* Check the parameters */
-      assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
-
-      /* Erase by sector by sector to be done*/
-      for(index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++)
-      {
-        FLASH_Erase_Sector(index, (uint8_t) pEraseInit->VoltageRange);
-
-        /* Wait for last operation to be completed */
-        status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-        
-        /* If the erase operation is completed, disable the SER and SNB Bits */
-        CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB));
-
-        if(status != HAL_OK) 
-        {
-          /* In case of error, stop erase procedure and return the faulty sector*/
-          *SectorError = index;
-          break;
-        }
-      }
-    }
-    /* Flush the caches to be sure of the data consistency */
-    FLASH_FlushCaches();    
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(&pFlash);
-
-  return status;
-}
-
-/**
-  * @brief  Perform a mass erase or erase the specified FLASH memory sectors  with interrupt enabled
-  * @param  pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
-  *         contains the configuration information for the erasing.
-  * 
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process Locked */
-  __HAL_LOCK(&pFlash);
-
-  /* Check the parameters */
-  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
-
-  /* Enable End of FLASH Operation interrupt */
-  __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
-  
-  /* Enable Error source interrupt */
-  __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
-  
-  /* Clear pending flags (if any) */  
-  __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP    | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\
-                         FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_PGSERR);  
-  
-  if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
-  {
-    /*Mass erase to be done*/
-    pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;
-    pFlash.Bank = pEraseInit->Banks;
-    FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);
-  }
-  else
-  {
-    /* Erase by sector to be done*/
-
-    /* Check the parameters */
-    assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
-
-    pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE;
-    pFlash.NbSectorsToErase = pEraseInit->NbSectors;
-    pFlash.Sector = pEraseInit->Sector;
-    pFlash.VoltageForErase = (uint8_t)pEraseInit->VoltageRange;
-
-    /*Erase 1st sector and wait for IT*/
-    FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->VoltageRange);
-  }
-
-  return status;
-}
-
-/**
-  * @brief   Program option bytes
-  * @param  pOBInit: pointer to an FLASH_OBInitStruct structure that
-  *         contains the configuration information for the programming.
-  * 
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
-{
-  HAL_StatusTypeDef status = HAL_ERROR;
-  
-  /* Process Locked */
-  __HAL_LOCK(&pFlash);
-
-  /* Check the parameters */
-  assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
-
-  /*Write protection configuration*/
-  if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
-  {
-    assert_param(IS_WRPSTATE(pOBInit->WRPState));
-    if(pOBInit->WRPState == OB_WRPSTATE_ENABLE)
-    {
-      /*Enable of Write protection on the selected Sector*/
-      status = FLASH_OB_EnableWRP(pOBInit->WRPSector, pOBInit->Banks);
-    }
-    else
-    {
-      /*Disable of Write protection on the selected Sector*/
-      status = FLASH_OB_DisableWRP(pOBInit->WRPSector, pOBInit->Banks);
-    }
-  }
-
-  /*Read protection configuration*/
-  if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)
-  {
-    status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel);
-  }
-
-  /*USER  configuration*/
-  if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)
-  {
-    status = FLASH_OB_UserConfig(pOBInit->USERConfig&OB_IWDG_SW, 
-                                     pOBInit->USERConfig&OB_STOP_NO_RST,
-                                     pOBInit->USERConfig&OB_STDBY_NO_RST);
-  }
-
-  /*BOR Level  configuration*/
-  if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR)
-  {
-    status = FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel);
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(&pFlash);
-
-  return status;
-}
-
-/**
-  * @brief   Get the Option byte configuration
-  * @param  pOBInit: pointer to an FLASH_OBInitStruct structure that
-  *         contains the configuration information for the programming.
-  * 
-  * @retval None
-  */
-void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
-{
-  pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_BOR;
-
-  /*Get WRP*/
-  pOBInit->WRPSector = (uint32_t)FLASH_OB_GetWRP();
-
-  /*Get RDP Level*/
-  pOBInit->RDPLevel = (uint32_t)FLASH_OB_GetRDP();
-
-  /*Get USER*/
-  pOBInit->USERConfig = (uint8_t)FLASH_OB_GetUser();
-
-  /*Get BOR Level*/
-  pOBInit->BORLevel = (uint32_t)FLASH_OB_GetBOR();
-}
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
-    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
-    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
-    defined(STM32F412Cx)
-/**
-  * @brief   Program option bytes
-  * @param  pAdvOBInit: pointer to an FLASH_AdvOBProgramInitTypeDef structure that
-  *         contains the configuration information for the programming.
-  * 
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
-{
-  HAL_StatusTypeDef status = HAL_ERROR;
-  
-  /* Check the parameters */
-  assert_param(IS_OBEX(pAdvOBInit->OptionType));
-
-  /*Program PCROP option byte*/
-  if(((pAdvOBInit->OptionType) & OPTIONBYTE_PCROP) == OPTIONBYTE_PCROP)
-  {
-    /* Check the parameters */
-    assert_param(IS_PCROPSTATE(pAdvOBInit->PCROPState));
-    if((pAdvOBInit->PCROPState) == OB_PCROP_STATE_ENABLE)
-    {
-      /*Enable of Write protection on the selected Sector*/
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
-    defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
-    defined(STM32F412Cx)
-      status = FLASH_OB_EnablePCROP(pAdvOBInit->Sectors);
-#else  /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
-      status = FLASH_OB_EnablePCROP(pAdvOBInit->SectorsBank1, pAdvOBInit->SectorsBank2, pAdvOBInit->Banks);
-#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-    }
-    else
-    {
-      /*Disable of Write protection on the selected Sector*/
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
-    defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
-    defined(STM32F412Cx) 
-      status = FLASH_OB_DisablePCROP(pAdvOBInit->Sectors);
-#else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
-      status = FLASH_OB_DisablePCROP(pAdvOBInit->SectorsBank1, pAdvOBInit->SectorsBank2, pAdvOBInit->Banks);
-#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-    }
-  }
-   
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-  /*Program BOOT config option byte*/
-  if(((pAdvOBInit->OptionType) & OPTIONBYTE_BOOTCONFIG) == OPTIONBYTE_BOOTCONFIG)
-  {
-    status = FLASH_OB_BootConfig(pAdvOBInit->BootConfig);
-  }
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-
-  return status;
-}
-
-/**
-  * @brief   Get the OBEX byte configuration
-  * @param  pAdvOBInit: pointer to an FLASH_AdvOBProgramInitTypeDef structure that
-  *         contains the configuration information for the programming.
-  * 
-  * @retval None
-  */
-void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
-{
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
-    defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
-    defined(STM32F412Cx)
-  /*Get Sector*/
-  pAdvOBInit->Sectors = (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
-#else  /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
-  /*Get Sector for Bank1*/
-  pAdvOBInit->SectorsBank1 = (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
-
-  /*Get Sector for Bank2*/
-  pAdvOBInit->SectorsBank2 = (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS));
-
-  /*Get Boot config OB*/
-  pAdvOBInit->BootConfig = *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS;
-#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-}
-
-/**
-  * @brief  Select the Protection Mode 
-  * 
-  * @note   After PCROP activated Option Byte modification NOT POSSIBLE! excepted 
-  *         Global Read Out Protection modification (from level1 to level0) 
-  * @note   Once SPRMOD bit is active unprotection of a protected sector is not possible 
-  * @note   Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
-  * @note   This function can be used only for STM32F42xxx/STM32F43xxx/STM32F401xx/STM32F411xx/STM32F446xx/
-  *         STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices.
-  * 
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void)
-{
-  uint8_t optiontmp = 0xFFU;
-
-  /* Mask SPRMOD bit */
-  optiontmp =  (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7FU); 
-  
-  /* Update Option Byte */
-  *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PCROP_SELECTED | optiontmp); 
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deselect the Protection Mode 
-  * 
-  * @note   After PCROP activated Option Byte modification NOT POSSIBLE! excepted 
-  *         Global Read Out Protection modification (from level1 to level0) 
-  * @note   Once SPRMOD bit is active unprotection of a protected sector is not possible 
-  * @note   Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
-  * @note   This function can be used only for STM32F42xxx/STM32F43xxx/STM32F401xx/STM32F411xx/STM32F446xx/
-  *         STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices.
-  * 
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void)
-{
-  uint8_t optiontmp = 0xFFU;
-  
-  /* Mask SPRMOD bit */
-  optiontmp =  (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7FU); 
-  
-  /* Update Option Byte */
-  *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PCROP_DESELECTED | optiontmp);  
-  
-  return HAL_OK;
-}
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410xx ||\
-          STM32F411xE || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-/**
-  * @brief  Returns the FLASH Write Protection Option Bytes value for Bank 2
-  * @note   This function can be used only for STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx devices.  
-  * @retval The FLASH Write Protection  Option Bytes value
-  */
-uint16_t HAL_FLASHEx_OB_GetBank2WRP(void)
-{                            
-  /* Return the FLASH write protection Register value */
-  return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS));
-}
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-
-/**
-  * @}
-  */
-  
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-/**
-  * @brief  Full erase of FLASH memory sectors 
-  * @param  VoltageRange: The device voltage range which defines the erase parallelism.  
-  *          This parameter can be one of the following values:
-  *            @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, 
-  *                                  the operation will be done by byte (8-bit) 
-  *            @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
-  *                                  the operation will be done by half word (16-bit)
-  *            @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
-  *                                  the operation will be done by word (32-bit)
-  *            @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, 
-  *                                  the operation will be done by double word (64-bit)
-  * 
-  * @param  Banks: Banks to be erased
-  *          This parameter can be one of the following values:
-  *            @arg FLASH_BANK_1: Bank1 to be erased
-  *            @arg FLASH_BANK_2: Bank2 to be erased
-  *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
-  *
-  * @retval HAL Status
-  */
-static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)
-{
-  /* Check the parameters */
-  assert_param(IS_VOLTAGERANGE(VoltageRange));
-  assert_param(IS_FLASH_BANK(Banks));
-
-  /* if the previous operation is completed, proceed to erase all sectors */
-  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
-
-  if(Banks == FLASH_BANK_BOTH)
-  {
-    /* bank1 & bank2 will be erased*/
-    FLASH->CR |= FLASH_MER_BIT;
-  }
-  else if(Banks == FLASH_BANK_1)
-  {
-    /*Only bank1 will be erased*/
-    FLASH->CR |= FLASH_CR_MER1;
-  }
-  else
-  {
-    /*Only bank2 will be erased*/
-    FLASH->CR |= FLASH_CR_MER2;
-  }
-  FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8U);
-}
-
-/**
-  * @brief  Erase the specified FLASH memory sector
-  * @param  Sector: FLASH sector to erase
-  *         The value of this parameter depend on device used within the same series      
-  * @param  VoltageRange: The device voltage range which defines the erase parallelism.  
-  *          This parameter can be one of the following values:
-  *            @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, 
-  *                                  the operation will be done by byte (8-bit) 
-  *            @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
-  *                                  the operation will be done by half word (16-bit)
-  *            @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
-  *                                  the operation will be done by word (32-bit)
-  *            @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, 
-  *                                  the operation will be done by double word (64-bit)
-  * 
-  * @retval None
-  */
-void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
-{
-  uint32_t tmp_psize = 0U;
-
-  /* Check the parameters */
-  assert_param(IS_FLASH_SECTOR(Sector));
-  assert_param(IS_VOLTAGERANGE(VoltageRange));
-  
-  if(VoltageRange == FLASH_VOLTAGE_RANGE_1)
-  {
-     tmp_psize = FLASH_PSIZE_BYTE;
-  }
-  else if(VoltageRange == FLASH_VOLTAGE_RANGE_2)
-  {
-    tmp_psize = FLASH_PSIZE_HALF_WORD;
-  }
-  else if(VoltageRange == FLASH_VOLTAGE_RANGE_3)
-  {
-    tmp_psize = FLASH_PSIZE_WORD;
-  }
-  else
-  {
-    tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
-  }
-
-  /* Need to add offset of 4 when sector higher than FLASH_SECTOR_11 */
-  if(Sector > FLASH_SECTOR_11) 
-  {
-    Sector += 4U;
-  }
-  /* If the previous operation is completed, proceed to erase the sector */
-  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
-  FLASH->CR |= tmp_psize;
-  CLEAR_BIT(FLASH->CR, FLASH_CR_SNB);
-  FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB));
-  FLASH->CR |= FLASH_CR_STRT;
-}
-
-/**
-  * @brief  Enable the write protection of the desired bank1 or bank 2 sectors
-  *
-  * @note   When the memory read protection level is selected (RDP level = 1), 
-  *         it is not possible to program or erase the flash sector i if CortexM4  
-  *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1 
-  * @note   Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).   
-  * 
-  * @param  WRPSector: specifies the sector(s) to be write protected.
-  *          This parameter can be one of the following values:
-  *            @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_23
-  *            @arg OB_WRP_SECTOR_All
-  * @note   BANK2 starts from OB_WRP_SECTOR_12
-  *
-  * @param  Banks: Enable write protection on all the sectors for the specific bank
-  *          This parameter can be one of the following values:
-  *            @arg FLASH_BANK_1: WRP on all sectors of bank1
-  *            @arg FLASH_BANK_2: WRP on all sectors of bank2
-  *            @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2
-  *
-  * @retval HAL FLASH State   
-  */
-static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_OB_WRP_SECTOR(WRPSector));
-  assert_param(IS_FLASH_BANK(Banks));
-    
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-  if(status == HAL_OK)
-  {
-    if(((WRPSector == OB_WRP_SECTOR_All) && ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))) ||
-         (WRPSector < OB_WRP_SECTOR_12))
-    {
-       if(WRPSector == OB_WRP_SECTOR_All)
-       {
-          /*Write protection on all sector of BANK1*/
-          *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~(WRPSector>>12U));  
-       }
-       else
-       {
-          /*Write protection done on sectors of BANK1*/
-          *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~WRPSector);  
-       }
-    }
-    else 
-    {
-      /*Write protection done on sectors of BANK2*/
-      *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~(WRPSector>>12U));  
-    }
-
-    /*Write protection on all sector of BANK2*/
-    if((WRPSector == OB_WRP_SECTOR_All) && (Banks == FLASH_BANK_BOTH))
-    {
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-      
-      if(status == HAL_OK)
-      { 
-        *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~(WRPSector>>12U));  
-      }
-    }
-    
-  }
-  return status;
-}
-
-/**
-  * @brief  Disable the write protection of the desired bank1 or bank 2 sectors
-  *
-  * @note   When the memory read protection level is selected (RDP level = 1), 
-  *         it is not possible to program or erase the flash sector i if CortexM4  
-  *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1 
-  * @note   Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).   
-  * 
-  * @param  WRPSector: specifies the sector(s) to be write protected.
-  *          This parameter can be one of the following values:
-  *            @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_23
-  *            @arg OB_WRP_Sector_All
-  * @note   BANK2 starts from OB_WRP_SECTOR_12
-  *
-  * @param  Banks: Disable write protection on all the sectors for the specific bank
-  *          This parameter can be one of the following values:
-  *            @arg FLASH_BANK_1: Bank1 to be erased
-  *            @arg FLASH_BANK_2: Bank2 to be erased
-  *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
-  *
-  * @retval HAL Status   
-  */
-static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_OB_WRP_SECTOR(WRPSector));
-  assert_param(IS_FLASH_BANK(Banks));
-    
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-  if(status == HAL_OK)
-  {
-    if(((WRPSector == OB_WRP_SECTOR_All) && ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))) ||
-         (WRPSector < OB_WRP_SECTOR_12))
-    {
-       if(WRPSector == OB_WRP_SECTOR_All)
-       {
-          /*Write protection on all sector of BANK1*/
-          *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)(WRPSector>>12U); 
-       }
-       else
-       {
-          /*Write protection done on sectors of BANK1*/
-          *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)WRPSector; 
-       }
-    }
-    else 
-    {
-      /*Write protection done on sectors of BANK2*/
-      *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)(WRPSector>>12U); 
-    }
-
-    /*Write protection on all sector  of BANK2*/
-    if((WRPSector == OB_WRP_SECTOR_All) && (Banks == FLASH_BANK_BOTH))
-    {
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-      
-      if(status == HAL_OK)
-      { 
-        *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)(WRPSector>>12U); 
-      }
-    }
-    
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Configure the Dual Bank Boot.
-  *   
-  * @note   This function can be used only for STM32F42xxx/43xxx devices.
-  *      
-  * @param  BootConfig specifies the Dual Bank Boot Option byte.
-  *          This parameter can be one of the following values:
-  *            @arg OB_Dual_BootEnabled: Dual Bank Boot Enable
-  *            @arg OB_Dual_BootDisabled: Dual Bank Boot Disabled
-  * @retval None
-  */
-static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t BootConfig)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_OB_BOOT(BootConfig));
-
-  /* Wait for last operation to be completed */  
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-  if(status == HAL_OK)
-  { 
-    /* Set Dual Bank Boot */
-    *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BFB2);
-    *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= BootConfig;
-  }
-  
-  return status;
-}
-
-/**
-  * @brief  Enable the read/write protection (PCROP) of the desired 
-  *         sectors of Bank 1 and/or Bank 2.
-  * @note   This function can be used only for STM32F42xxx/43xxx devices.
-  * @param  SectorBank1 Specifies the sector(s) to be read/write protected or unprotected for bank1.
-  *          This parameter can be one of the following values:
-  *            @arg OB_PCROP: A value between OB_PCROP_SECTOR_0 and OB_PCROP_SECTOR_11
-  *            @arg OB_PCROP_SECTOR__All                         
-  * @param  SectorBank2 Specifies the sector(s) to be read/write protected or unprotected for bank2.
-  *          This parameter can be one of the following values:
-  *            @arg OB_PCROP: A value between OB_PCROP_SECTOR_12 and OB_PCROP_SECTOR_23
-  *            @arg OB_PCROP_SECTOR__All                         
-  * @param  Banks Enable PCROP protection on all the sectors for the specific bank
-  *          This parameter can be one of the following values:
-  *            @arg FLASH_BANK_1: WRP on all sectors of bank1
-  *            @arg FLASH_BANK_2: WRP on all sectors of bank2
-  *            @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2
-  *
-  * @retval HAL Status  
-  */
-static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  assert_param(IS_FLASH_BANK(Banks));
-    
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-  if(status == HAL_OK)
-  {
-    if((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))
-    {
-      assert_param(IS_OB_PCROP(SectorBank1));
-      /*Write protection done on sectors of BANK1*/
-      *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)SectorBank1; 
-    }
-    else 
-    {
-      assert_param(IS_OB_PCROP(SectorBank2));
-      /*Write protection done on sectors of BANK2*/
-      *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)SectorBank2; 
-    }
-
-    /*Write protection on all sector  of BANK2*/
-    if(Banks == FLASH_BANK_BOTH)
-    {
-      assert_param(IS_OB_PCROP(SectorBank2));
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-      
-      if(status == HAL_OK)
-      { 
-        /*Write protection done on sectors of BANK2*/
-        *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)SectorBank2; 
-      }
-    }
-    
-  }
-
-  return status;
-}
-
-
-/**
-  * @brief  Disable the read/write protection (PCROP) of the desired 
-  *         sectors  of Bank 1 and/or Bank 2.
-  * @note   This function can be used only for STM32F42xxx/43xxx devices.
-  * @param  SectorBank1 specifies the sector(s) to be read/write protected or unprotected for bank1.
-  *          This parameter can be one of the following values:
-  *            @arg OB_PCROP: A value between OB_PCROP_SECTOR_0 and OB_PCROP_SECTOR_11
-  *            @arg OB_PCROP_SECTOR__All                         
-  * @param  SectorBank2 Specifies the sector(s) to be read/write protected or unprotected for bank2.
-  *          This parameter can be one of the following values:
-  *            @arg OB_PCROP: A value between OB_PCROP_SECTOR_12 and OB_PCROP_SECTOR_23
-  *            @arg OB_PCROP_SECTOR__All                         
-  * @param  Banks Disable PCROP protection on all the sectors for the specific bank
-  *          This parameter can be one of the following values:
-  *            @arg FLASH_BANK_1: WRP on all sectors of bank1
-  *            @arg FLASH_BANK_2: WRP on all sectors of bank2
-  *            @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2
-  *
-  * @retval HAL Status  
-  */
-static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks)
-{  
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_FLASH_BANK(Banks));
-    
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-  if(status == HAL_OK)
-  {
-    if((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))
-    {
-      assert_param(IS_OB_PCROP(SectorBank1));
-      /*Write protection done on sectors of BANK1*/
-      *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~SectorBank1); 
-    }
-    else 
-    {
-      /*Write protection done on sectors of BANK2*/
-      assert_param(IS_OB_PCROP(SectorBank2));
-      *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~SectorBank2); 
-    }
-
-    /*Write protection on all sector  of BANK2*/
-    if(Banks == FLASH_BANK_BOTH)
-    {
-      assert_param(IS_OB_PCROP(SectorBank2));
-     /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-      
-      if(status == HAL_OK)
-      { 
-        /*Write protection done on sectors of BANK2*/
-        *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~SectorBank2); 
-      }
-    }
-    
-  }
-  
-  return status;
-
-}
-
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
-    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
-    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
-/**
-  * @brief  Mass erase of FLASH memory
-  * @param  VoltageRange: The device voltage range which defines the erase parallelism.  
-  *          This parameter can be one of the following values:
-  *            @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, 
-  *                                  the operation will be done by byte (8-bit) 
-  *            @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
-  *                                  the operation will be done by half word (16-bit)
-  *            @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
-  *                                  the operation will be done by word (32-bit)
-  *            @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, 
-  *                                  the operation will be done by double word (64-bit)
-  * 
-  * @param  Banks: Banks to be erased
-  *          This parameter can be one of the following values:
-  *            @arg FLASH_BANK_1: Bank1 to be erased
-  *
-  * @retval None
-  */
-static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)
-{
-  /* Check the parameters */
-  assert_param(IS_VOLTAGERANGE(VoltageRange));
-  assert_param(IS_FLASH_BANK(Banks));
-  
-  /* If the previous operation is completed, proceed to erase all sectors */
-  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
-  FLASH->CR |= FLASH_CR_MER;
-  FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8U);
-}
-
-/**
-  * @brief  Erase the specified FLASH memory sector
-  * @param  Sector: FLASH sector to erase
-  *         The value of this parameter depend on device used within the same series      
-  * @param  VoltageRange: The device voltage range which defines the erase parallelism.  
-  *          This parameter can be one of the following values:
-  *            @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, 
-  *                                  the operation will be done by byte (8-bit) 
-  *            @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
-  *                                  the operation will be done by half word (16-bit)
-  *            @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
-  *                                  the operation will be done by word (32-bit)
-  *            @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, 
-  *                                  the operation will be done by double word (64-bit)
-  * 
-  * @retval None
-  */
-void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
-{
-  uint32_t tmp_psize = 0U;
-
-  /* Check the parameters */
-  assert_param(IS_FLASH_SECTOR(Sector));
-  assert_param(IS_VOLTAGERANGE(VoltageRange));
-  
-  if(VoltageRange == FLASH_VOLTAGE_RANGE_1)
-  {
-     tmp_psize = FLASH_PSIZE_BYTE;
-  }
-  else if(VoltageRange == FLASH_VOLTAGE_RANGE_2)
-  {
-    tmp_psize = FLASH_PSIZE_HALF_WORD;
-  }
-  else if(VoltageRange == FLASH_VOLTAGE_RANGE_3)
-  {
-    tmp_psize = FLASH_PSIZE_WORD;
-  }
-  else
-  {
-    tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
-  }
-
-  /* If the previous operation is completed, proceed to erase the sector */
-  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
-  FLASH->CR |= tmp_psize;
-  CLEAR_BIT(FLASH->CR, FLASH_CR_SNB);
-  FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB));
-  FLASH->CR |= FLASH_CR_STRT;
-}
-
-/**
-  * @brief  Enable the write protection of the desired bank 1 sectors
-  *
-  * @note   When the memory read protection level is selected (RDP level = 1), 
-  *         it is not possible to program or erase the flash sector i if CortexM4  
-  *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1 
-  * @note   Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).   
-  * 
-  * @param  WRPSector: specifies the sector(s) to be write protected.
-  *         The value of this parameter depend on device used within the same series 
-  * 
-  * @param  Banks: Enable write protection on all the sectors for the specific bank
-  *          This parameter can be one of the following values:
-  *            @arg FLASH_BANK_1: WRP on all sectors of bank1
-  *
-  * @retval HAL Status 
-  */
-static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_OB_WRP_SECTOR(WRPSector));
-  assert_param(IS_FLASH_BANK(Banks));
-    
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-  if(status == HAL_OK)
-  { 
-    *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~WRPSector);  
-  }
-  
-  return status;
-}
-
-/**
-  * @brief  Disable the write protection of the desired bank 1 sectors
-  *
-  * @note   When the memory read protection level is selected (RDP level = 1), 
-  *         it is not possible to program or erase the flash sector i if CortexM4  
-  *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1 
-  * @note   Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).   
-  * 
-  * @param  WRPSector: specifies the sector(s) to be write protected.
-  *         The value of this parameter depend on device used within the same series 
-  * 
-  * @param  Banks: Enable write protection on all the sectors for the specific bank
-  *          This parameter can be one of the following values:
-  *            @arg FLASH_BANK_1: WRP on all sectors of bank1
-  *
-  * @retval HAL Status 
-  */
-static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_OB_WRP_SECTOR(WRPSector));
-  assert_param(IS_FLASH_BANK(Banks));
-    
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-  if(status == HAL_OK)
-  { 
-    *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)WRPSector; 
-  }
-  
-  return status;
-}
-#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
-    defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
-    defined(STM32F412Cx)
-/**
-  * @brief  Enable the read/write protection (PCROP) of the desired sectors.
-  * @note   This function can be used only for STM32F401xx devices.
-  * @param  Sector specifies the sector(s) to be read/write protected or unprotected.
-  *          This parameter can be one of the following values:
-  *            @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector5
-  *            @arg OB_PCROP_Sector_All                         
-  * @retval HAL Status  
-  */
-static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t Sector)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_OB_PCROP(Sector));
-    
-  /* Wait for last operation to be completed */  
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-  if(status == HAL_OK)
-  { 
-    *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)Sector;
-  }
-  
-  return status;
-}
-
-
-/**
-  * @brief  Disable the read/write protection (PCROP) of the desired sectors.
-  * @note   This function can be used only for STM32F401xx devices.
-  * @param  Sector specifies the sector(s) to be read/write protected or unprotected.
-  *          This parameter can be one of the following values:
-  *            @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector5
-  *            @arg OB_PCROP_Sector_All                         
-  * @retval HAL Status  
-  */
-static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t Sector)
-{  
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_OB_PCROP(Sector));
-    
-  /* Wait for last operation to be completed */  
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-  if(status == HAL_OK)
-  { 
-    *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~Sector);
-  }
-  
-  return status;
-
-}
-#endif /* STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-
-/**
-  * @brief  Set the read protection level.
-  * @param  Level: specifies the read protection level.
-  *          This parameter can be one of the following values:
-  *            @arg OB_RDP_LEVEL_0: No protection
-  *            @arg OB_RDP_LEVEL_1: Read protection of the memory
-  *            @arg OB_RDP_LEVEL_2: Full chip protection
-  *   
-  * @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
-  *    
-  * @retval HAL Status
-  */
-static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_OB_RDP_LEVEL(Level));
-    
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-  if(status == HAL_OK)
-  { 
-    *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = Level;
-  }
-  
-  return status;
-}
-
-/**
-  * @brief  Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.    
-  * @param  Iwdg: Selects the IWDG mode
-  *          This parameter can be one of the following values:
-  *            @arg OB_IWDG_SW: Software IWDG selected
-  *            @arg OB_IWDG_HW: Hardware IWDG selected
-  * @param  Stop: Reset event when entering STOP mode.
-  *          This parameter  can be one of the following values:
-  *            @arg OB_STOP_NO_RST: No reset generated when entering in STOP
-  *            @arg OB_STOP_RST: Reset generated when entering in STOP
-  * @param  Stdby: Reset event when entering Standby mode.
-  *          This parameter  can be one of the following values:
-  *            @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY
-  *            @arg OB_STDBY_RST: Reset generated when entering in STANDBY
-  * @retval HAL Status
-  */
-static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t Stdby)
-{
-  uint8_t optiontmp = 0xFFU;
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_OB_IWDG_SOURCE(Iwdg));
-  assert_param(IS_OB_STOP_SOURCE(Stop));
-  assert_param(IS_OB_STDBY_SOURCE(Stdby));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-  
-  if(status == HAL_OK)
-  {     
-    /* Mask OPTLOCK, OPTSTRT, BOR_LEV and BFB2 bits */
-    optiontmp =  (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x1FU);
-
-    /* Update User Option Byte */
-    *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = Iwdg | (uint8_t)(Stdby | (uint8_t)(Stop | ((uint8_t)optiontmp))); 
-  }
-  
-  return status; 
-}
-
-/**
-  * @brief  Set the BOR Level. 
-  * @param  Level: specifies the Option Bytes BOR Reset Level.
-  *          This parameter can be one of the following values:
-  *            @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
-  *            @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
-  *            @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
-  *            @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V
-  * @retval HAL Status
-  */
-static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level)
-{
-  /* Check the parameters */
-  assert_param(IS_OB_BOR_LEVEL(Level));
-
-  /* Set the BOR Level */
-  *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BOR_LEV);
-  *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= Level;
-  
-  return HAL_OK;
-  
-}
-
-/**
-  * @brief  Return the FLASH User Option Byte value.
-  * @retval uint8_t FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1)
-  *         and RST_STDBY(Bit2).
-  */
-static uint8_t FLASH_OB_GetUser(void)
-{
-  /* Return the User Option Byte */
-  return ((uint8_t)(FLASH->OPTCR & 0xE0U));
-}
-
-/**
-  * @brief  Return the FLASH Write Protection Option Bytes value.
-  * @retval uint16_t FLASH Write Protection Option Bytes value
-  */
-static uint16_t FLASH_OB_GetWRP(void)
-{
-  /* Return the FLASH write protection Register value */
-  return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
-}
-
-/**
-  * @brief  Returns the FLASH Read Protection level.
-  * @retval FLASH ReadOut Protection Status:
-  *         This parameter can be one of the following values:
-  *            @arg OB_RDP_LEVEL_0: No protection
-  *            @arg OB_RDP_LEVEL_1: Read protection of the memory
-  *            @arg OB_RDP_LEVEL_2: Full chip protection
-  */
-static uint8_t FLASH_OB_GetRDP(void)
-{
-  uint8_t readstatus = OB_RDP_LEVEL_0;
-
-  if((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_2))
-  {
-    readstatus = OB_RDP_LEVEL_2;
-  }
-  else if((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_1))
-  {
-    readstatus = OB_RDP_LEVEL_1;
-  }
-  else 
-  {
-    readstatus = OB_RDP_LEVEL_0;
-  }
-
-  return readstatus;
-}
-
-/**
-  * @brief  Returns the FLASH BOR level.
-  * @retval uint8_t The FLASH BOR level:
-  *           - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
-  *           - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
-  *           - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
-  *           - OB_BOR_OFF   : Supply voltage ranges from 1.62 to 2.1 V  
-  */
-static uint8_t FLASH_OB_GetBOR(void)
-{
-  /* Return the FLASH BOR level */
-  return (uint8_t)(*(__IO uint8_t *)(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0CU);
-}
-
-/**
-  * @brief  Flush the instruction and data caches
-  * @retval None
-  */
-void FLASH_FlushCaches(void)
-{
-  /* Flush instruction cache  */
-  if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN)!= RESET)
-  {
-    /* Disable instruction cache  */
-    __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
-    /* Reset instruction cache */
-    __HAL_FLASH_INSTRUCTION_CACHE_RESET();
-    /* Enable instruction cache */
-    __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
-  }
-  
-  /* Flush data cache */
-  if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET)
-  {
-    /* Disable data cache  */
-    __HAL_FLASH_DATA_CACHE_DISABLE();
-    /* Reset data cache */
-    __HAL_FLASH_DATA_CACHE_RESET();
-    /* Enable data cache */
-    __HAL_FLASH_DATA_CACHE_ENABLE();
-  }
-}
-
-/**
-  * @}
-  */
-  
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_gpio.c b/stmhal/hal/f4/src/stm32f4xx_hal_gpio.c
deleted file mode 100644
index 44d76609bd..0000000000
--- a/stmhal/hal/f4/src/stm32f4xx_hal_gpio.c
+++ /dev/null
@@ -1,547 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_gpio.c
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   GPIO HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *
-  @verbatim
-  ==============================================================================
-                    ##### GPIO Peripheral features #####
-  ==============================================================================
-  [..] 
-  Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
-  port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
-  in several modes:
-  (+) Input mode 
-  (+) Analog mode
-  (+) Output mode
-  (+) Alternate function mode
-  (+) External interrupt/event lines
-
-  [..]  
-  During and just after reset, the alternate functions and external interrupt  
-  lines are not active and the I/O ports are configured in input floating mode.
-  
-  [..]   
-  All GPIO pins have weak internal pull-up and pull-down resistors, which can be 
-  activated or not.
-
-  [..]
-  In Output or Alternate mode, each IO can be configured on open-drain or push-pull
-  type and the IO speed can be selected depending on the VDD value.
-
-  [..]  
-  All ports have external interrupt/event capability. To use external interrupt 
-  lines, the port must be configured in input mode. All available GPIO pins are 
-  connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
-  
-  [..]
-  The external interrupt/event controller consists of up to 23 edge detectors 
-  (16 lines are connected to GPIO) for generating event/interrupt requests (each 
-  input line can be independently configured to select the type (interrupt or event) 
-  and the corresponding trigger event (rising or falling or both). Each line can 
-  also be masked independently. 
-
-                     ##### How to use this driver #####
-  ==============================================================================  
-  [..]
-    (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). 
-
-    (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
-        (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
-        (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef 
-             structure.
-        (++) In case of Output or alternate function mode selection: the speed is 
-             configured through "Speed" member from GPIO_InitTypeDef structure.
-        (++) In alternate mode is selection, the alternate function connected to the IO
-             is configured through "Alternate" member from GPIO_InitTypeDef structure.
-        (++) Analog mode is required when a pin is to be used as ADC channel 
-             or DAC output.
-        (++) In case of external interrupt/event selection the "Mode" member from 
-             GPIO_InitTypeDef structure select the type (interrupt or event) and 
-             the corresponding trigger event (rising or falling or both).
-
-    (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority 
-        mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
-        HAL_NVIC_EnableIRQ().
-         
-    (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
-            
-    (#) To set/reset the level of a pin configured in output mode use 
-        HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
-    
-    (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
-
-                 
-    (#) During and just after reset, the alternate functions are not 
-        active and the GPIO pins are configured in input floating mode (except JTAG
-        pins).
-  
-    (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose 
-        (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has 
-        priority over the GPIO function.
-  
-    (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as 
-        general purpose PH0 and PH1, respectively, when the HSE oscillator is off. 
-        The HSE has priority over the GPIO function.
-  
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup GPIO GPIO
-  * @brief GPIO HAL module driver
-  * @{
-  */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup GPIO_Private_Constants GPIO Private Constants
-  * @{
-  */
-#define GPIO_MODE             ((uint32_t)0x00000003U)
-#define EXTI_MODE             ((uint32_t)0x10000000U)
-#define GPIO_MODE_IT          ((uint32_t)0x00010000U)
-#define GPIO_MODE_EVT         ((uint32_t)0x00020000U)
-#define RISING_EDGE           ((uint32_t)0x00100000U)
-#define FALLING_EDGE          ((uint32_t)0x00200000U)
-#define GPIO_OUTPUT_TYPE      ((uint32_t)0x00000010U)
-
-#define GPIO_NUMBER           ((uint32_t)16U)
-/**
-  * @}
-  */
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
-  * @{
-  */
-
-/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
-  *  @brief    Initialization and Configuration functions
-  *
-@verbatim    
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-  [..]
-    This section provides functions allowing to initialize and de-initialize the GPIOs
-    to be ready for use.
- 
-@endverbatim
-  * @{
-  */
-
-
-/**
-  * @brief  Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
-  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F429X device or
-  *                      x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
-  * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
-  *         the configuration information for the specified GPIO peripheral.
-  * @retval None
-  */
-void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
-{
-  uint32_t position;
-  uint32_t ioposition = 0x00U;
-  uint32_t iocurrent = 0x00U;
-  uint32_t temp = 0x00U;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
-  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
-  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
-  assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
-
-  /* Configure the port pins */
-  for(position = 0U; position < GPIO_NUMBER; position++)
-  {
-    /* Get the IO position */
-    ioposition = ((uint32_t)0x01U) << position;
-    /* Get the current IO position */
-    iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
-
-    if(iocurrent == ioposition)
-    {
-      /*--------------------- GPIO Mode Configuration ------------------------*/
-      /* In case of Alternate function mode selection */
-      if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
-      {
-        /* Check the Alternate function parameter */
-        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
-        /* Configure Alternate function mapped with the current IO */
-        temp = GPIOx->AFR[position >> 3U];
-        temp &= ~((uint32_t)0xFU << ((uint32_t)(position & (uint32_t)0x07U) * 4U)) ;
-        temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07U) * 4U));
-        GPIOx->AFR[position >> 3U] = temp;
-      }
-
-      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
-      temp = GPIOx->MODER;
-      temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
-      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
-      GPIOx->MODER = temp;
-
-      /* In case of Output or Alternate function mode selection */
-      if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
-         (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
-      {
-        /* Check the Speed parameter */
-        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
-        /* Configure the IO Speed */
-        temp = GPIOx->OSPEEDR; 
-        temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
-        temp |= (GPIO_Init->Speed << (position * 2U));
-        GPIOx->OSPEEDR = temp;
-
-        /* Configure the IO Output Type */
-        temp = GPIOx->OTYPER;
-        temp &= ~(GPIO_OTYPER_OT_0 << position) ;
-        temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
-        GPIOx->OTYPER = temp;
-      }
-
-      /* Activate the Pull-up or Pull down resistor for the current IO */
-      temp = GPIOx->PUPDR;
-      temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
-      temp |= ((GPIO_Init->Pull) << (position * 2U));
-      GPIOx->PUPDR = temp;
-
-      /*--------------------- EXTI Mode Configuration ------------------------*/
-      /* Configure the External Interrupt or event for the current IO */
-      if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
-      {
-        /* Enable SYSCFG Clock */
-        __HAL_RCC_SYSCFG_CLK_ENABLE();
-
-        temp = SYSCFG->EXTICR[position >> 2U];
-        temp &= ~(((uint32_t)0x0FU) << (4U * (position & 0x03U)));
-        temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
-        SYSCFG->EXTICR[position >> 2U] = temp;
-
-        /* Clear EXTI line configuration */
-        temp = EXTI->IMR;
-        temp &= ~((uint32_t)iocurrent);
-        if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
-        {
-          temp |= iocurrent;
-        }
-        EXTI->IMR = temp;
-
-        temp = EXTI->EMR;
-        temp &= ~((uint32_t)iocurrent);
-        if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
-        {
-          temp |= iocurrent;
-        }
-        EXTI->EMR = temp;
-
-        /* Clear Rising Falling edge configuration */
-        temp = EXTI->RTSR;
-        temp &= ~((uint32_t)iocurrent);
-        if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
-        {
-          temp |= iocurrent;
-        }
-        EXTI->RTSR = temp;
-
-        temp = EXTI->FTSR;
-        temp &= ~((uint32_t)iocurrent);
-        if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
-        {
-          temp |= iocurrent;
-        }
-        EXTI->FTSR = temp;
-      }
-    }
-  }
-}
-
-/**
-  * @brief  De-initializes the GPIOx peripheral registers to their default reset values.
-  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F429X device or
-  *                      x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
-  * @param  GPIO_Pin: specifies the port bit to be written.
-  *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
-  * @retval None
-  */
-void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
-{
-  uint32_t position;
-  uint32_t ioposition = 0x00U;
-  uint32_t iocurrent = 0x00U;
-  uint32_t tmp = 0x00U;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
-  
-  /* Configure the port pins */
-  for(position = 0U; position < GPIO_NUMBER; position++)
-  {
-    /* Get the IO position */
-    ioposition = ((uint32_t)0x01U) << position;
-    /* Get the current IO position */
-    iocurrent = (GPIO_Pin) & ioposition;
-
-    if(iocurrent == ioposition)
-    {
-      /*------------------------- GPIO Mode Configuration --------------------*/
-      /* Configure IO Direction in Input Floating Mode */
-      GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2U));
-
-      /* Configure the default Alternate Function in current IO */
-      GPIOx->AFR[position >> 3U] &= ~((uint32_t)0xFU << ((uint32_t)(position & (uint32_t)0x07U) * 4U)) ;
-
-      /* Configure the default value for IO Speed */
-      GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
-
-      /* Configure the default value IO Output Type */
-      GPIOx->OTYPER  &= ~(GPIO_OTYPER_OT_0 << position) ;
-
-      /* Deactivate the Pull-up and Pull-down resistor for the current IO */
-      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
-
-      /*------------------------- EXTI Mode Configuration --------------------*/
-      tmp = SYSCFG->EXTICR[position >> 2U];
-      tmp &= (((uint32_t)0x0FU) << (4U * (position & 0x03U)));
-      if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))))
-      {
-        /* Configure the External Interrupt or event for the current IO */
-        tmp = ((uint32_t)0x0FU) << (4U * (position & 0x03U));
-        SYSCFG->EXTICR[position >> 2U] &= ~tmp;
-
-        /* Clear EXTI line configuration */
-        EXTI->IMR &= ~((uint32_t)iocurrent);
-        EXTI->EMR &= ~((uint32_t)iocurrent);
-        
-        /* Clear Rising Falling edge configuration */
-        EXTI->RTSR &= ~((uint32_t)iocurrent);
-        EXTI->FTSR &= ~((uint32_t)iocurrent);
-      }
-    }
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions 
-  *  @brief   GPIO Read and Write
-  *
-@verbatim
- ===============================================================================
-                       ##### IO operation functions #####
- ===============================================================================
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Reads the specified input port pin.
-  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F429X device or
-  *                      x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
-  * @param  GPIO_Pin: specifies the port bit to read.
-  *         This parameter can be GPIO_PIN_x where x can be (0..15).
-  * @retval The input port pin value.
-  */
-GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
-  GPIO_PinState bitstatus;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-
-  if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
-  {
-    bitstatus = GPIO_PIN_SET;
-  }
-  else
-  {
-    bitstatus = GPIO_PIN_RESET;
-  }
-  return bitstatus;
-}
-
-/**
-  * @brief  Sets or clears the selected data port bit.
-  *
-  * @note   This function uses GPIOx_BSRR register to allow atomic read/modify
-  *         accesses. In this way, there is no risk of an IRQ occurring between
-  *         the read and the modify access.
-  *
-  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F429X device or
-  *                      x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
-  * @param  GPIO_Pin: specifies the port bit to be written.
-  *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
-  * @param  PinState: specifies the value to be written to the selected bit.
-  *          This parameter can be one of the GPIO_PinState enum values:
-  *            @arg GPIO_PIN_RESET: to clear the port pin
-  *            @arg GPIO_PIN_SET: to set the port pin
-  * @retval None
-  */
-void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
-{
-  /* Check the parameters */
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-  assert_param(IS_GPIO_PIN_ACTION(PinState));
-
-  if(PinState != GPIO_PIN_RESET)
-  {
-    GPIOx->BSRR = GPIO_Pin;
-  }
-  else
-  {
-    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
-  }
-}
-
-/**
-  * @brief  Toggles the specified GPIO pins.
-  * @param  GPIOx: Where x can be (A..K) to select the GPIO peripheral for STM32F429X device or
-  *                      x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
-  * @param  GPIO_Pin: Specifies the pins to be toggled.
-  * @retval None
-  */
-void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
-  /* Check the parameters */
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-
-  GPIOx->ODR ^= GPIO_Pin;
-}
-
-/**
-  * @brief  Locks GPIO Pins configuration registers.
-  * @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
-  *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
-  * @note   The configuration of the locked GPIO pins can no longer be modified
-  *         until the next reset.
-  * @param  GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F4 family
-  * @param  GPIO_Pin: specifies the port bit to be locked.
-  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
-  __IO uint32_t tmp = GPIO_LCKR_LCKK;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-
-  /* Apply lock key write sequence */
-  tmp |= GPIO_Pin;
-  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
-  GPIOx->LCKR = tmp;
-  /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
-  GPIOx->LCKR = GPIO_Pin;
-  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
-  GPIOx->LCKR = tmp;
-  /* Read LCKK bit*/
-  tmp = GPIOx->LCKR;
-
- if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
-  {
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  This function handles EXTI interrupt request.
-  * @param  GPIO_Pin: Specifies the pins connected EXTI line
-  * @retval None
-  */
-void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
-{
-  /* EXTI line interrupt detected */
-  if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
-  {
-    __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
-    HAL_GPIO_EXTI_Callback(GPIO_Pin);
-  }
-}
-
-/**
-  * @brief  EXTI line detection callbacks.
-  * @param  GPIO_Pin: Specifies the pins connected EXTI line
-  * @retval None
-  */
-__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(GPIO_Pin);
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_GPIO_EXTI_Callback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-#endif /* HAL_GPIO_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_i2c.c b/stmhal/hal/f4/src/stm32f4xx_hal_i2c.c
deleted file mode 100644
index 29d18bbb9b..0000000000
--- a/stmhal/hal/f4/src/stm32f4xx_hal_i2c.c
+++ /dev/null
@@ -1,5508 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_i2c.c
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   I2C HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Inter Integrated Circuit (I2C) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral State, Mode and Error functions
-  *
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-  [..]
-    The I2C HAL driver can be used as follows:
-
-    (#) Declare a I2C_HandleTypeDef handle structure, for example:
-        I2C_HandleTypeDef  hi2c;
-
-    (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
-        (##) Enable the I2Cx interface clock
-        (##) I2C pins configuration
-            (+++) Enable the clock for the I2C GPIOs
-            (+++) Configure I2C pins as alternate function open-drain
-        (##) NVIC configuration if you need to use interrupt process
-            (+++) Configure the I2Cx interrupt priority
-            (+++) Enable the NVIC I2C IRQ Channel
-        (##) DMA Configuration if you need to use DMA process
-            (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
-            (+++) Enable the DMAx interface clock using
-            (+++) Configure the DMA handle parameters
-            (+++) Configure the DMA Tx or Rx Stream
-            (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
-            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on 
-                  the DMA Tx or Rx Stream
-
-    (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1,
-        Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure.
-
-    (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware 
-        (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
-
-    (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
-
-    (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
-
-    *** Polling mode IO operation ***
-    =================================
-    [..]
-      (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
-      (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
-      (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
-      (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
-
-    *** Polling mode IO MEM operation ***
-    =====================================
-    [..]
-      (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
-      (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
-
-
-    *** Interrupt mode IO operation ***
-    ===================================
-    [..]
-      (+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT()
-      (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
-      (+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT()
-      (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
-      (+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT()
-      (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
-           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
-      (+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT()
-      (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
-           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
-      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
-           add his own code by customization of function pointer HAL_I2C_ErrorCallback
-      (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
-      (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
-
-    *** Interrupt mode IO sequential operation ***
-    ==============================================
-    [..]
-      (@) These interfaces allow to manage a sequential transfer with a repeated start condition
-          when a direction change during transfer
-    [..]
-      (+) A specific option field manage the different steps of a sequential transfer
-      (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
-      (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode 
-      (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
-                            and data to transfer without a final stop condition
-      (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
-                            and with new data to transfer if the direction change or manage only the new data to transfer
-                            if no direction change and without a final stop condition in both cases
-      (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
-                            and with new data to transfer if the direction change or manage only the new data to transfer
-                            if no direction change and with a final stop condition in both cases
-
-      (+) Differents sequential I2C interfaces are listed below:
-      (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT()
-      (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
-      (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT()
-      (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
-      (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
-      (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
-      (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
-      (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
-           add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
-      (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
-      (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT()
-      (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
-      (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT()
-      (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
-      (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
-           add his own code by customization of function pointer HAL_I2C_ErrorCallback()
-      (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
-      (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
-
-    *** Interrupt mode IO MEM operation ***
-    =======================================
-    [..]
-      (+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using
-          HAL_I2C_Mem_Write_IT()
-      (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
-      (+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using
-          HAL_I2C_Mem_Read_IT()
-      (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
-      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
-           add his own code by customization of function pointer HAL_I2C_ErrorCallback
-
-    *** DMA mode IO operation ***
-    ==============================
-    [..]
-      (+) Transmit in master mode an amount of data in non blocking mode (DMA) using
-          HAL_I2C_Master_Transmit_DMA()
-      (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
-      (+) Receive in master mode an amount of data in non blocking mode (DMA) using
-          HAL_I2C_Master_Receive_DMA()
-      (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
-      (+) Transmit in slave mode an amount of data in non blocking mode (DMA) using
-          HAL_I2C_Slave_Transmit_DMA()
-      (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
-           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
-      (+) Receive in slave mode an amount of data in non blocking mode (DMA) using
-          HAL_I2C_Slave_Receive_DMA()
-      (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
-           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
-      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
-           add his own code by customization of function pointer HAL_I2C_ErrorCallback
-      (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
-      (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
-
-    *** DMA mode IO MEM operation ***
-    =================================
-    [..]
-      (+) Write an amount of data in no-blocking mode with DMA to a specific memory address using
-          HAL_I2C_Mem_Write_DMA()
-      (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
-      (+) Read an amount of data in no-blocking mode with DMA from a specific memory address using
-          HAL_I2C_Mem_Read_DMA()
-      (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
-      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
-           add his own code by customization of function pointer HAL_I2C_ErrorCallback
-
-
-     *** I2C HAL driver macros list ***
-     ==================================
-     [..]
-       Below the list of most used macros in I2C HAL driver.
-
-      (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
-      (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
-      (+) __HAL_I2C_GET_FLAG : Checks whether the specified I2C flag is set or not
-      (+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag
-      (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
-      (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
-
-     [..]
-       (@) You can refer to the I2C HAL driver header file for more useful macros
-
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup I2C I2C
-  * @brief I2C HAL module driver
-  * @{
-  */
-
-#ifdef HAL_I2C_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup I2C_Private_Define
-  * @{
-  */    
-#define I2C_TIMEOUT_FLAG          ((uint32_t)35U)         /*!< Timeout 35 ms             */
-#define I2C_TIMEOUT_BUSY_FLAG     ((uint32_t)25U)         /*!< Timeout 25 ms             */
-#define I2C_NO_OPTION_FRAME       ((uint32_t)0xFFFF0000U) /*!< XferOptions default value */
-
-/* Private define for @ref PreviousState usage */
-#define I2C_STATE_MSK             ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~(uint32_t)HAL_I2C_STATE_READY))) /*!< Mask State define, keep only RX and TX bits            */
-#define I2C_STATE_NONE            ((uint32_t)(HAL_I2C_MODE_NONE))                                                        /*!< Default Value                                          */
-#define I2C_STATE_MASTER_BUSY_TX  ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))            /*!< Master Busy TX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_MASTER_BUSY_RX  ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))            /*!< Master Busy RX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_SLAVE_BUSY_TX   ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))             /*!< Slave Busy TX, combinaison of State LSB and Mode enum  */
-#define I2C_STATE_SLAVE_BUSY_RX   ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))             /*!< Slave Busy RX, combinaison of State LSB and Mode enum  */
-
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup I2C_Private_Functions
-  * @{
-  */
-/* Private functions to handle DMA transfer */
-static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMAError(DMA_HandleTypeDef *hdma);
-static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
-
-static void I2C_ITError(I2C_HandleTypeDef *hi2c);
-
-static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c);
-
-/* Private functions for I2C transfer IRQ handler */
-static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c);
-
-static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup I2C_Exported_Functions I2C Exported Functions
-  * @{
-  */
-
-/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @brief    Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This subsection provides a set of functions allowing to initialize and
-          de-initialize the I2Cx peripheral:
-
-      (+) User must Implement HAL_I2C_MspInit() function in which he configures
-          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC).
-
-      (+) Call the function HAL_I2C_Init() to configure the selected device with
-          the selected configuration:
-        (++) Communication Speed
-        (++) Duty cycle
-        (++) Addressing mode
-        (++) Own Address 1
-        (++) Dual Addressing mode
-        (++) Own Address 2
-        (++) General call mode
-        (++) Nostretch mode
-
-      (+) Call the function HAL_I2C_DeInit() to restore the default configuration
-          of the selected I2Cx peripheral.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the I2C according to the specified parameters
-  *         in the I2C_InitTypeDef and create the associated handle.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
-{
-  uint32_t freqrange = 0U;
-  uint32_t pclk1 = 0U;
-
-  /* Check the I2C handle allocation */
-  if(hi2c == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
-  assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed));
-  assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle));
-  assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
-  assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
-  assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
-  assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
-  assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
-  assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
-
-  if(hi2c->State == HAL_I2C_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hi2c->Lock = HAL_UNLOCKED;
-    /* Init the low level hardware : GPIO, CLOCK, NVIC */
-    HAL_I2C_MspInit(hi2c);
-  }
-
-  hi2c->State = HAL_I2C_STATE_BUSY;
-
-  /* Disable the selected I2C peripheral */
-  __HAL_I2C_DISABLE(hi2c);
-
-  /* Get PCLK1 frequency */
-  pclk1 = HAL_RCC_GetPCLK1Freq();
-
-  /* Calculate frequency range */
-  freqrange = I2C_FREQRANGE(pclk1);
-
-  /*---------------------------- I2Cx CR2 Configuration ----------------------*/
-  /* Configure I2Cx: Frequency range */
-  hi2c->Instance->CR2 = freqrange;
-
-  /*---------------------------- I2Cx TRISE Configuration --------------------*/
-  /* Configure I2Cx: Rise Time */
-  hi2c->Instance->TRISE = I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed);
-
-  /*---------------------------- I2Cx CCR Configuration ----------------------*/
-  /* Configure I2Cx: Speed */
-  hi2c->Instance->CCR = I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle);
-
-  /*---------------------------- I2Cx CR1 Configuration ----------------------*/
-  /* Configure I2Cx: Generalcall and NoStretch mode */
-  hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
-
-  /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
-  /* Configure I2Cx: Own Address1 and addressing mode */
-  hi2c->Instance->OAR1 = (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1);
-
-  /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
-  /* Configure I2Cx: Dual mode and Own Address2 */
-  hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2);
-
-  /* Enable the selected I2C peripheral */
-  __HAL_I2C_ENABLE(hi2c);
-
-  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-  hi2c->State = HAL_I2C_STATE_READY;
-  hi2c->PreviousState = I2C_STATE_NONE;
-  hi2c->Mode = HAL_I2C_MODE_NONE;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the I2C peripheral.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
-{
-  /* Check the I2C handle allocation */
-  if(hi2c == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
-
-  hi2c->State = HAL_I2C_STATE_BUSY;
-
-  /* Disable the I2C Peripheral Clock */
-  __HAL_I2C_DISABLE(hi2c);
-
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
-  HAL_I2C_MspDeInit(hi2c);
-
-  hi2c->ErrorCode     = HAL_I2C_ERROR_NONE;
-  hi2c->State         = HAL_I2C_STATE_RESET;
-  hi2c->PreviousState = I2C_STATE_NONE;
-  hi2c->Mode          = HAL_I2C_MODE_NONE;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hi2c);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief I2C MSP Init.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval None
-  */
- __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2C_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief I2C MSP DeInit
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval None
-  */
- __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2C_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Exported_Functions_Group2 IO operation functions
- *  @brief   Data transfers functions
- *
-@verbatim
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to manage the I2C data
-    transfers.
-
-    (#) There are two modes of transfer:
-       (++) Blocking mode : The communication is performed in the polling mode.
-            The status of all data processing is returned by the same function
-            after finishing transfer.
-       (++) No-Blocking mode : The communication is performed using Interrupts
-            or DMA. These functions return the status of the transfer startup.
-            The end of the data processing will be indicated through the
-            dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
-            using DMA mode.
-
-    (#) Blocking mode functions are :
-        (++) HAL_I2C_Master_Transmit()
-        (++) HAL_I2C_Master_Receive()
-        (++) HAL_I2C_Slave_Transmit()
-        (++) HAL_I2C_Slave_Receive()
-        (++) HAL_I2C_Mem_Write()
-        (++) HAL_I2C_Mem_Read()
-        (++) HAL_I2C_IsDeviceReady()
-
-    (#) No-Blocking mode functions with Interrupt are :
-        (++) HAL_I2C_Master_Transmit_IT()
-        (++) HAL_I2C_Master_Receive_IT()
-        (++) HAL_I2C_Slave_Transmit_IT()
-        (++) HAL_I2C_Slave_Receive_IT()
-        (++) HAL_I2C_Master_Sequential_Transmit_IT()
-        (++) HAL_I2C_Master_Sequential_Receive_IT()
-        (++) HAL_I2C_Slave_Sequential_Transmit_IT()
-        (++) HAL_I2C_Slave_Sequential_Receive_IT()
-        (++) HAL_I2C_Mem_Write_IT()
-        (++) HAL_I2C_Mem_Read_IT()
-
-    (#) No-Blocking mode functions with DMA are :
-        (++) HAL_I2C_Master_Transmit_DMA()
-        (++) HAL_I2C_Master_Receive_DMA()
-        (++) HAL_I2C_Slave_Transmit_DMA()
-        (++) HAL_I2C_Slave_Receive_DMA()
-        (++) HAL_I2C_Mem_Write_DMA()
-        (++) HAL_I2C_Mem_Read_DMA()
-
-    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
-        (++) HAL_I2C_MemTxCpltCallback()
-        (++) HAL_I2C_MemRxCpltCallback()
-        (++) HAL_I2C_MasterTxCpltCallback()
-        (++) HAL_I2C_MasterRxCpltCallback()
-        (++) HAL_I2C_SlaveTxCpltCallback()
-        (++) HAL_I2C_SlaveRxCpltCallback()
-        (++) HAL_I2C_ErrorCallback()
-        (++) HAL_I2C_AbortCpltCallback()
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Transmits in master mode an amount of data in blocking mode.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shift at right before call interface
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint32_t tickstart = 0x00U;
-
-  /* Init tickstart for timeout management*/
-  tickstart = HAL_GetTick();
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Check if the I2C is already enabled */
-    if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode      = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->XferSize    = hi2c->XferCount;
-
-    /* Send Slave Address */
-    if(I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_ERROR;
-      }
-      else
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-    while(hi2c->XferSize > 0U)
-    {
-      /* Wait until TXE flag is set */
-      if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-      {
-        if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-        {
-          /* Generate Stop */
-          hi2c->Instance->CR1 |= I2C_CR1_STOP;
-          return HAL_ERROR;
-        }
-        else
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-
-      /* Write data to DR */
-      hi2c->Instance->DR = (*hi2c->pBuffPtr++);
-      hi2c->XferCount--;
-      hi2c->XferSize--;
-
-      if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0U))
-      {
-        /* Write data to DR */
-        hi2c->Instance->DR = (*hi2c->pBuffPtr++);
-        hi2c->XferCount--;
-        hi2c->XferSize--;
-      }
-      
-      /* Wait until BTF flag is set */
-      if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-      {
-        if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-        {
-          /* Generate Stop */
-          hi2c->Instance->CR1 |= I2C_CR1_STOP;
-          return HAL_ERROR;
-        }
-        else
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-
-    /* Generate Stop */
-    hi2c->Instance->CR1 |= I2C_CR1_STOP;
-
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode = HAL_I2C_MODE_NONE;
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receives in master mode an amount of data in blocking mode. 
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shift at right before call interface
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint32_t tickstart = 0x00U;
-
-  /* Init tickstart for timeout management*/
-  tickstart = HAL_GetTick();
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Check if the I2C is already enabled */
-    if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
-    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode        = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->XferSize    = hi2c->XferCount;
-
-    /* Send Slave Address */
-    if(I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_ERROR;
-      }
-      else
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_TIMEOUT;
-      }
-    }
-
-    if(hi2c->XferSize == 0U)
-    {
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-      /* Generate Stop */
-      hi2c->Instance->CR1 |= I2C_CR1_STOP;
-    }
-    else if(hi2c->XferSize == 1U)
-    {
-      /* Disable Acknowledge */
-      hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-      /* Generate Stop */
-      hi2c->Instance->CR1 |= I2C_CR1_STOP;
-    }
-    else if(hi2c->XferSize == 2U)
-    {
-      /* Disable Acknowledge */
-      hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
-      /* Enable Pos */
-      hi2c->Instance->CR1 |= I2C_CR1_POS;
-
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-    }
-    else
-    {
-      /* Enable Acknowledge */
-      hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-    }
-
-    while(hi2c->XferSize > 0U)
-    {
-      if(hi2c->XferSize <= 3U)
-      {
-        /* One byte */
-        if(hi2c->XferSize == 1U)
-        {
-          /* Wait until RXNE flag is set */
-          if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)      
-          {
-            if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
-            {
-              return HAL_TIMEOUT;
-            }
-            else
-            {
-              return HAL_ERROR;
-            }
-          }
-
-          /* Read data from DR */
-          (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-          hi2c->XferSize--;
-          hi2c->XferCount--;
-        }
-        /* Two bytes */
-        else if(hi2c->XferSize == 2U)
-        {
-          /* Wait until BTF flag is set */
-          if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
-          {
-            return HAL_TIMEOUT;
-          }
-
-          /* Generate Stop */
-          hi2c->Instance->CR1 |= I2C_CR1_STOP;
-
-          /* Read data from DR */
-          (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-          hi2c->XferSize--;
-          hi2c->XferCount--;
-
-          /* Read data from DR */
-          (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-          hi2c->XferSize--;
-          hi2c->XferCount--;
-        }
-        /* 3 Last bytes */
-        else
-        {
-          /* Wait until BTF flag is set */
-          if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
-          {
-            return HAL_TIMEOUT;
-          }
-
-          /* Disable Acknowledge */
-          hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
-          /* Read data from DR */
-          (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-          hi2c->XferSize--;
-          hi2c->XferCount--;
-
-          /* Wait until BTF flag is set */
-          if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
-          {
-            return HAL_TIMEOUT;
-          }
-
-          /* Generate Stop */
-          hi2c->Instance->CR1 |= I2C_CR1_STOP;
-
-          /* Read data from DR */
-          (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-          hi2c->XferSize--;
-          hi2c->XferCount--;
-
-          /* Read data from DR */
-          (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-          hi2c->XferSize--;
-          hi2c->XferCount--;
-        }
-      }
-      else
-      {
-        /* Wait until RXNE flag is set */
-        if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)      
-        {
-          if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
-          {
-            return HAL_TIMEOUT;
-          }
-          else
-          {
-            return HAL_ERROR;
-          }
-        }
-
-        /* Read data from DR */
-        (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-        hi2c->XferSize--;
-        hi2c->XferCount--;
-
-        if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
-        {
-          /* Read data from DR */
-          (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-          hi2c->XferSize--;
-          hi2c->XferCount--;
-        }
-      }
-    }
-
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode = HAL_I2C_MODE_NONE;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Transmits in slave mode an amount of data in blocking mode. 
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint32_t tickstart = 0x00U;
-  
-  /* Init tickstart for timeout management*/
-  tickstart = HAL_GetTick();
-  
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-    
-    /* Check if the I2C is already enabled */
-    if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
-    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->XferSize    = hi2c->XferCount;
-
-    /* Enable Address Acknowledge */
-    hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
-    /* Wait until ADDR flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-    /* If 10bit addressing mode is selected */
-    if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
-    {
-      /* Wait until ADDR flag is set */
-      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
-
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-    }
-
-    while(hi2c->XferSize > 0U)
-    {
-      /* Wait until TXE flag is set */
-      if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-      {
-        /* Disable Address Acknowledge */
-        hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
-        if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-        {
-          return HAL_ERROR;
-        }
-        else
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-
-      /* Write data to DR */
-      hi2c->Instance->DR = (*hi2c->pBuffPtr++);
-      hi2c->XferCount--;
-      hi2c->XferSize--;
-
-      if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0U))
-      {
-        /* Write data to DR */
-        hi2c->Instance->DR = (*hi2c->pBuffPtr++);
-        hi2c->XferCount--;
-        hi2c->XferSize--;
-      }
-    }
-
-    /* Wait until AF flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    /* Clear AF flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-    /* Disable Address Acknowledge */
-    hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode = HAL_I2C_MODE_NONE;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receive in slave mode an amount of data in blocking mode 
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for the specified I2C.
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint32_t tickstart = 0x00U;
-
-  /* Init tickstart for timeout management*/
-  tickstart = HAL_GetTick();
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Check if the I2C is already enabled */
-    if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
-    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->XferSize    = hi2c->XferCount;
-
-    /* Enable Address Acknowledge */
-    hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
-    /* Wait until ADDR flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-    while(hi2c->XferSize > 0U)
-    {
-      /* Wait until RXNE flag is set */
-      if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)      
-      {
-        /* Disable Address Acknowledge */
-        hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
-        if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
-        {
-          return HAL_TIMEOUT;
-        }
-        else
-        {
-          return HAL_ERROR;
-        }
-      }
-
-      /* Read data from DR */
-      (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-      hi2c->XferSize--;
-      hi2c->XferCount--;
-
-      if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0U))
-      {
-        /* Read data from DR */
-      (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-      hi2c->XferSize--;
-      hi2c->XferCount--;
-      }
-    }
-
-    /* Wait until STOP flag is set */
-    if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-    {
-      /* Disable Address Acknowledge */
-      hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Clear STOP flag */
-    __HAL_I2C_CLEAR_STOPFLAG(hi2c);
-
-    /* Disable Address Acknowledge */
-    hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode = HAL_I2C_MODE_NONE;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Transmit in master mode an amount of data in non-blocking mode with Interrupt
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shift at right before call interface
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
-{
-  __IO uint32_t count = 0U;
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Wait until BUSY flag is reset */
-    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
-    do
-    {
-      if(count-- == 0U)
-      {
-        hi2c->PreviousState = I2C_STATE_NONE;
-        hi2c->State= HAL_I2C_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_TIMEOUT;
-      }
-    }
-    while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-    
-    /* Check if the I2C is already enabled */
-    if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode      = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->Devaddress  = DevAddress;
-
-    /* Generate Start */
-    hi2c->Instance->CR1 |= I2C_CR1_START;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-    /* Enable EVT, BUF and ERR interrupt */
-    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receive in master mode an amount of data in non-blocking mode with Interrupt
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shift at right before call interface
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
-{
-  __IO uint32_t count = 0U;
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Wait until BUSY flag is reset */
-    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
-    do
-    {
-      if(count-- == 0U)
-      {
-        hi2c->PreviousState = I2C_STATE_NONE;
-        hi2c->State= HAL_I2C_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_TIMEOUT; 
-      }
-    }
-    while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-    
-    /* Check if the I2C is already enabled */
-    if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode      = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->Devaddress  = DevAddress;
-
-    /* Enable Acknowledge */
-    hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
-    /* Generate Start */
-    hi2c->Instance->CR1 |= I2C_CR1_START;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-    to avoid the risk of I2C interrupt handle execution before current
-    process unlock */
-
-    /* Enable EVT, BUF and ERR interrupt */
-    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Sequential transmit in master mode an amount of data in non-blocking mode with Interrupt
-  * @note   This interface allow to manage repeated start condition when a direction change during transfer
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shift at right before call interface
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
-  __IO uint32_t Prev_State = 0x00U;
-  __IO uint32_t count      = 0x00U;
-  
-  /* Check the parameters */
-  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Check Busy Flag only if FIRST call of Master interface */
-    if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
-    {
-      /* Wait until BUSY flag is reset */
-      count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
-      do
-      {
-        if(count-- == 0U)
-        {
-          hi2c->PreviousState = I2C_STATE_NONE;
-          hi2c->State= HAL_I2C_STATE_READY;
-          
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2c);
-          
-          return HAL_TIMEOUT; 
-        }
-      }
-      while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Check if the I2C is already enabled */
-    if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode      = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferOptions = XferOptions;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->Devaddress  = DevAddress;
-
-    Prev_State = hi2c->PreviousState;
-    
-    /* Generate Start */    
-    if((Prev_State == I2C_STATE_MASTER_BUSY_RX) || (Prev_State == I2C_STATE_NONE))
-    {
-      /* Generate Start condition if first transfer */
-      if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
-      {
-        /* Generate Start */
-        hi2c->Instance->CR1 |= I2C_CR1_START;
-      }
-      else if(Prev_State == I2C_STATE_MASTER_BUSY_RX)
-      {
-        /* Generate ReStart */
-        hi2c->Instance->CR1 |= I2C_CR1_START;
-      }
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-    to avoid the risk of I2C interrupt handle execution before current
-    process unlock */
-
-    /* Enable EVT, BUF and ERR interrupt */
-    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Sequential receive in master mode an amount of data in non-blocking mode with Interrupt
-  * @note   This interface allow to manage repeated start condition when a direction change during transfer
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shift at right before call interface
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
-  __IO uint32_t count = 0U;
-    
-  /* Check the parameters */
-  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Check Busy Flag only if FIRST call of Master interface */
-    if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
-    {
-      /* Wait until BUSY flag is reset */
-      count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
-      do
-      {
-        if(count-- == 0U)
-        {
-          hi2c->PreviousState = I2C_STATE_NONE;
-          hi2c->State= HAL_I2C_STATE_READY;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2c);
-
-          return HAL_TIMEOUT; 
-        }
-      }
-      while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Check if the I2C is already enabled */
-    if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode      = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr = pData;
-    hi2c->XferCount = Size;
-    hi2c->XferOptions = XferOptions;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->Devaddress = DevAddress;
-    
-    if((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) || (hi2c->PreviousState == I2C_STATE_NONE))
-    {
-      /* Generate Start condition if first transfer */
-      if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)  || (XferOptions == I2C_NO_OPTION_FRAME))
-      {
-        /* Enable Acknowledge */
-        hi2c->Instance->CR1 |= I2C_CR1_ACK;
-        
-        /* Generate Start */
-        hi2c->Instance->CR1 |= I2C_CR1_START;
-      }
-      else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
-      {
-        /* Enable Acknowledge */
-        hi2c->Instance->CR1 |= I2C_CR1_ACK;
-        
-        /* Generate ReStart */
-        hi2c->Instance->CR1 |= I2C_CR1_START;
-      }
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-    to avoid the risk of I2C interrupt handle execution before current
-    process unlock */
-
-    /* Enable EVT, BUF and ERR interrupt */
-    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Transmit in slave mode an amount of data in non-blocking mode with Interrupt
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for the specified I2C.
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
-{
-  __IO uint32_t count = 0U;
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Wait until BUSY flag is reset */
-    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
-    do
-    {
-      if(count-- == 0U)
-      {
-        hi2c->PreviousState = I2C_STATE_NONE;
-        hi2c->State= HAL_I2C_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_TIMEOUT; 
-      }
-    }
-    while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Check if the I2C is already enabled */
-    if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->XferSize    = hi2c->XferCount;
-
-    /* Enable Address Acknowledge */
-    hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-
-    /* Enable EVT, BUF and ERR interrupt */
-    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receive in slave mode an amount of data in non-blocking mode with Interrupt 
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
-{
-  __IO uint32_t count = 0U;
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Wait until BUSY flag is reset */
-    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
-    do
-    {
-      if(count-- == 0U)
-      {
-        hi2c->PreviousState = I2C_STATE_NONE;
-        hi2c->State= HAL_I2C_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_TIMEOUT; 
-      }
-    }
-    while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Check if the I2C is already enabled */
-    if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr = pData;
-    hi2c->XferSize = Size;
-    hi2c->XferCount = Size;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-
-    /* Enable Address Acknowledge */
-    hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-
-    /* Enable EVT, BUF and ERR interrupt */
-    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Sequential transmit in slave mode an amount of data in no-blocking mode with Interrupt
-  * @note   This interface allow to manage repeated start condition when a direction change during transfer
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
-  if(hi2c->State == HAL_I2C_STATE_LISTEN)
-  {
-    if((pData == NULL) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Check if the I2C is already enabled */
-    if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
-    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferOptions = XferOptions;
-    hi2c->XferSize    = hi2c->XferCount;
-
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-
-    /* Enable EVT, BUF and ERR interrupt */
-    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt
-  * @note   This interface allow to manage repeated start condition when a direction change during transfer
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for the specified I2C.
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
-  if(hi2c->State == HAL_I2C_STATE_LISTEN)
-  {
-    if((pData == NULL) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Check if the I2C is already enabled */
-    if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
-    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr   = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferOptions = XferOptions;
-    hi2c->XferSize    = hi2c->XferCount;
-
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-
-    /* Enable EVT, BUF and ERR interrupt */
-    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Enable the Address listen mode with Interrupt.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
-{
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    hi2c->State = HAL_I2C_STATE_LISTEN;
-    
-    /* Check if the I2C is already enabled */
-    if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Enable Address Acknowledge */
-    hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
-    /* Enable EVT and ERR interrupt */
-    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Disable the Address listen mode with Interrupt.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
-{
-  /* Declaration of tmp to prevent undefined behavior of volatile usage */
-  uint32_t tmp;
-
-  /* Disable Address listen mode only if a transfer is not ongoing */
-  if(hi2c->State == HAL_I2C_STATE_LISTEN)
-  {
-    tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
-    hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode = HAL_I2C_MODE_NONE;
-
-    /* Disable Address Acknowledge */
-    hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
-    /* Disable EVT and ERR interrupt */
-    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
-  
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Transmit in master mode an amount of data in non-blocking mode with DMA
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shift at right before call interface
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
-{
-  __IO uint32_t count = 0U;
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Wait until BUSY flag is reset */
-    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
-    do
-    {
-      if(count-- == 0U)
-      {
-        hi2c->PreviousState = I2C_STATE_NONE;
-        hi2c->State= HAL_I2C_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_TIMEOUT; 
-      }
-    }
-    while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Check if the I2C is already enabled */
-    if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode      = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->Devaddress  = DevAddress;
-
-    if(hi2c->XferSize > 0U)
-    {
-      /* Set the I2C DMA transfer complete callback */
-      hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
-
-      /* Set the DMA error callback */      
-      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
-
-      /* Set the unused DMA callbacks to NULL */
-      hi2c->hdmatx->XferHalfCpltCallback = NULL;
-      hi2c->hdmatx->XferM1CpltCallback = NULL;
-      hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
-      hi2c->hdmatx->XferAbortCallback = NULL;
-
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
-
-      /* Enable Acknowledge */
-      hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
-      /* Generate Start */
-      hi2c->Instance->CR1 |= I2C_CR1_START;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      /* Note : The I2C interrupts must be enabled after unlocking current process
-      to avoid the risk of I2C interrupt handle execution before current
-      process unlock */
-
-      /* Enable EVT and ERR interrupt */
-      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
-
-      /* Enable DMA Request */
-      hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
-    }
-    else
-    {
-      /* Enable Acknowledge */
-      hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
-      /* Generate Start */
-      hi2c->Instance->CR1 |= I2C_CR1_START;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      /* Note : The I2C interrupts must be enabled after unlocking current process
-      to avoid the risk of I2C interrupt handle execution before current
-      process unlock */
-
-     /* Enable EVT, BUF and ERR interrupt */
-    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-    }
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receive in master mode an amount of data in non-blocking mode with DMA 
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shift at right before call interface
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
-{
-  __IO uint32_t count = 0U;
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Wait until BUSY flag is reset */
-    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
-    do
-    {
-      if(count-- == 0U)
-      {
-        hi2c->PreviousState = I2C_STATE_NONE;
-        hi2c->State= HAL_I2C_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_TIMEOUT; 
-      }
-    }
-    while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-    
-    /* Check if the I2C is already enabled */
-    if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-    
-    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode      = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-    
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->Devaddress  = DevAddress;
-    
-    if(hi2c->XferSize > 0U)
-    {
-      /* Set the I2C DMA transfer complete callback */
-      hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
-
-      /* Set the DMA error callback */
-      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-
-      /* Set the unused DMA callbacks to NULL */
-      hi2c->hdmarx->XferHalfCpltCallback = NULL;
-      hi2c->hdmarx->XferM1CpltCallback = NULL;
-      hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
-      hi2c->hdmarx->XferAbortCallback = NULL;
-
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
-
-      /* Enable Acknowledge */
-      hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
-      /* Generate Start */
-      hi2c->Instance->CR1 |= I2C_CR1_START;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      /* Note : The I2C interrupts must be enabled after unlocking current process
-                to avoid the risk of I2C interrupt handle execution before current
-                process unlock */
-
-      /* Enable EVT and ERR interrupt */
-      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
-
-      /* Enable DMA Request */
-      hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
-    }
-    else
-    {
-      /* Enable Acknowledge */
-      hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
-      /* Generate Start */
-      hi2c->Instance->CR1 |= I2C_CR1_START;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      /* Note : The I2C interrupts must be enabled after unlocking current process
-      to avoid the risk of I2C interrupt handle execution before current
-      process unlock */
-
-      /* Enable EVT, BUF and ERR interrupt */
-      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-    }
-    
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Abort a master I2C process communication with Interrupt.
-  * @note   This abort can be called only if state is ready
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shift at right before call interface
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
-{
-  /* Abort Master transfer during Receive or Transmit process    */
-  if(hi2c->Mode == HAL_I2C_MODE_MASTER)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->PreviousState = I2C_STATE_NONE;
-    hi2c->State = HAL_I2C_STATE_ABORT;
-
-    /* Disable Acknowledge */
-    hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
-    /* Generate Stop */
-    hi2c->Instance->CR1 |= I2C_CR1_STOP;
-
-    hi2c->XferCount = 0U;
-
-    /* Disable EVT, BUF and ERR interrupt */
-    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Call the corresponding callback to inform upper layer of End of Transfer */
-    I2C_ITError(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    /* Wrong usage of abort function */
-    /* This function should be used only in case of abort monitored by master device */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Transmit in slave mode an amount of data in non-blocking mode with DMA 
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
-{
-  __IO uint32_t count = 0U;
-  
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Wait until BUSY flag is reset */
-    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
-    do
-    {
-      if(count-- == 0U)
-      {
-        hi2c->PreviousState = I2C_STATE_NONE;
-        hi2c->State= HAL_I2C_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_TIMEOUT; 
-      }
-    }
-    while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Check if the I2C is already enabled */
-    if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->XferSize    = hi2c->XferCount;
-
-    /* Set the I2C DMA transfer complete callback */
-    hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
-    
-    /* Set the DMA error callback */
-    hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
-
-    /* Set the unused DMA callbacks to NULL */
-    hi2c->hdmatx->XferHalfCpltCallback = NULL;
-    hi2c->hdmatx->XferM1CpltCallback = NULL;
-    hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
-    hi2c->hdmatx->XferAbortCallback = NULL;
-
-    /* Enable the DMA Stream */
-    HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
-
-    /* Enable Address Acknowledge */
-    hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-      /* Note : The I2C interrupts must be enabled after unlocking current process
-                to avoid the risk of I2C interrupt handle execution before current
-                process unlock */
-    /* Enable EVT and ERR interrupt */
-    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
-
-    /* Enable DMA Request */
-    hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receive in slave mode an amount of data in non-blocking mode with DMA 
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
-{
-  __IO uint32_t count = 0U;
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Wait until BUSY flag is reset */
-    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
-    do
-    {
-      if(count-- == 0U)
-      {
-        hi2c->PreviousState = I2C_STATE_NONE;
-        hi2c->State= HAL_I2C_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_TIMEOUT; 
-      }
-    }
-    while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Check if the I2C is already enabled */
-    if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->XferSize    = hi2c->XferCount;
-
-    /* Set the I2C DMA transfer complete callback */
-    hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
-
-    /* Set the DMA error callback */
-    hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-
-    /* Set the unused DMA callbacks to NULL */
-    hi2c->hdmarx->XferHalfCpltCallback = NULL;
-    hi2c->hdmarx->XferM1CpltCallback = NULL;
-    hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
-    hi2c->hdmarx->XferAbortCallback = NULL;
-
-    /* Enable the DMA Stream */
-    HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
-
-    /* Enable Address Acknowledge */
-    hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-    /* Enable EVT and ERR interrupt */
-    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
-
-    /* Enable DMA Request */
-    hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-/**
-  * @brief  Write an amount of data in blocking mode to a specific memory address
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address
-  * @param  MemAddress Internal memory address
-  * @param  MemAddSize Size of internal memory address
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint32_t tickstart = 0x00U;
-
-  /* Init tickstart for timeout management*/
-  tickstart = HAL_GetTick();
-  
-  /* Check the parameters */
-  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-    
-    /* Check if the I2C is already enabled */
-    if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode      = HAL_I2C_MODE_MEM;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->XferSize    = hi2c->XferCount;
-    
-    /* Send Slave Address and Memory Address */
-    if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_ERROR;
-      }
-      else
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_TIMEOUT;
-      }
-    }
-
-    while(hi2c->XferSize > 0U)
-    {
-      /* Wait until TXE flag is set */
-      if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-      {
-        if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-        {
-          /* Generate Stop */
-          hi2c->Instance->CR1 |= I2C_CR1_STOP;
-          return HAL_ERROR;
-        }
-        else
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-
-      /* Write data to DR */
-      hi2c->Instance->DR = (*hi2c->pBuffPtr++);
-      hi2c->XferSize--;
-      hi2c->XferCount--;
-
-      if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
-      {
-        /* Write data to DR */
-        hi2c->Instance->DR = (*hi2c->pBuffPtr++);
-        hi2c->XferSize--;
-        hi2c->XferCount--;
-      }
-    }
-    
-    /* Wait until BTF flag is set */
-    if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        /* Generate Stop */
-        hi2c->Instance->CR1 |= I2C_CR1_STOP;
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Generate Stop */
-    hi2c->Instance->CR1 |= I2C_CR1_STOP;
-
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode = HAL_I2C_MODE_NONE;
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Read an amount of data in blocking mode from a specific memory address
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address
-  * @param  MemAddress Internal memory address
-  * @param  MemAddSize Size of internal memory address
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint32_t tickstart = 0x00U;
-
-  /* Init tickstart for timeout management*/
-  tickstart = HAL_GetTick();
-  
-  /* Check the parameters */
-  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-    
-    /* Check if the I2C is already enabled */
-    if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode      = HAL_I2C_MODE_MEM;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->XferSize    = hi2c->XferCount;
-
-    /* Send Slave Address and Memory Address */
-    if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_ERROR;
-      }
-      else
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_TIMEOUT;
-      }
-    }
-
-    if(hi2c->XferSize == 0U)
-    {
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-      
-      /* Generate Stop */
-      hi2c->Instance->CR1 |= I2C_CR1_STOP;
-    }
-    else if(hi2c->XferSize == 1U)
-    {
-      /* Disable Acknowledge */
-      hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-      /* Generate Stop */
-      hi2c->Instance->CR1 |= I2C_CR1_STOP;
-    }
-    else if(hi2c->XferSize == 2U)
-    {
-      /* Disable Acknowledge */
-      hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
-      /* Enable Pos */
-      hi2c->Instance->CR1 |= I2C_CR1_POS;
-
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-    }
-    else
-    {
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-    }
-
-    while(hi2c->XferSize > 0U)
-    {
-      if(hi2c->XferSize <= 3U)
-      {
-        /* One byte */
-        if(hi2c->XferSize== 1U)
-        {
-          /* Wait until RXNE flag is set */
-          if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)      
-          {
-            if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
-            {
-              return HAL_TIMEOUT;
-            }
-            else
-            {
-              return HAL_ERROR;
-            }
-          }
-
-          /* Read data from DR */
-          (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-          hi2c->XferSize--;
-          hi2c->XferCount--;
-        }
-        /* Two bytes */
-        else if(Size == 2U)
-        {
-          /* Wait until BTF flag is set */
-          if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
-          {
-            return HAL_TIMEOUT;
-          }
-
-          /* Generate Stop */
-          hi2c->Instance->CR1 |= I2C_CR1_STOP;
-
-          /* Read data from DR */
-          (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-          hi2c->XferSize--;
-          hi2c->XferCount--;
-
-          /* Read data from DR */
-          (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-          hi2c->XferSize--;
-          hi2c->XferCount--;
-        }
-        /* 3 Last bytes */
-        else
-        {
-          /* Wait until BTF flag is set */
-          if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
-          {
-            return HAL_TIMEOUT;
-          }
-
-          /* Disable Acknowledge */
-          hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
-          /* Read data from DR */
-          (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-          hi2c->XferSize--;
-          hi2c->XferCount--;
-
-          /* Wait until BTF flag is set */
-          if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
-          {
-            return HAL_TIMEOUT;
-          }
-
-          /* Generate Stop */
-          hi2c->Instance->CR1 |= I2C_CR1_STOP;
-
-          /* Read data from DR */
-          (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-          hi2c->XferSize--;
-          hi2c->XferCount--;
-
-          /* Read data from DR */
-          (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-          hi2c->XferSize--;
-          hi2c->XferCount--;
-        }
-      }
-      else
-      {
-        /* Wait until RXNE flag is set */
-        if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-        {
-          if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
-          {
-            return HAL_TIMEOUT;
-          }
-          else
-          {
-            return HAL_ERROR;
-          }
-        }
-
-        /* Read data from DR */
-        (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-        hi2c->XferSize--;
-        hi2c->XferCount--;
-
-        if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
-        {
-          /* Read data from DR */
-          (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-          hi2c->XferSize--;
-          hi2c->XferCount--;
-        }
-      }
-    }
-
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode = HAL_I2C_MODE_NONE;
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Write an amount of data in non-blocking mode with Interrupt to a specific memory address
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address
-  * @param  MemAddress Internal memory address
-  * @param  MemAddSize Size of internal memory address
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
-{
-  __IO uint32_t count = 0U;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Wait until BUSY flag is reset */
-    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
-    do
-    {
-      if(count-- == 0U)
-      {
-        hi2c->PreviousState = I2C_STATE_NONE;
-        hi2c->State= HAL_I2C_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_TIMEOUT; 
-      }
-    }
-    while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Check if the I2C is already enabled */
-    if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
-    hi2c->State = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode = HAL_I2C_MODE_MEM;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr = pData;
-    hi2c->XferSize = Size;
-    hi2c->XferCount = Size;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->Devaddress = DevAddress;
-    hi2c->Memaddress = MemAddress;
-    hi2c->MemaddSize = MemAddSize;
-    hi2c->EventCount = 0U;
-
-    /* Generate Start */
-    hi2c->Instance->CR1 |= I2C_CR1_START;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-    to avoid the risk of I2C interrupt handle execution before current
-    process unlock */
-
-    /* Enable EVT, BUF and ERR interrupt */
-    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Read an amount of data in non-blocking mode with Interrupt from a specific memory address
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address
-  * @param  MemAddress Internal memory address
-  * @param  MemAddSize Size of internal memory address
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
-{
-  __IO uint32_t count = 0U;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Wait until BUSY flag is reset */
-    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
-    do
-    {
-      if(count-- == 0U)
-      {
-        hi2c->PreviousState = I2C_STATE_NONE;
-        hi2c->State= HAL_I2C_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_TIMEOUT; 
-      }
-    }
-    while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Check if the I2C is already enabled */
-    if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
-    hi2c->State = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode = HAL_I2C_MODE_MEM;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr = pData;
-    hi2c->XferSize = Size;
-    hi2c->XferCount = Size;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->Devaddress = DevAddress;
-    hi2c->Memaddress = MemAddress;
-    hi2c->MemaddSize = MemAddSize;
-    hi2c->EventCount = 0U;
-
-    /* Enable Acknowledge */
-    hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
-    /* Generate Start */
-    hi2c->Instance->CR1 |= I2C_CR1_START;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    if(hi2c->XferSize > 0U)
-    {
-      /* Note : The I2C interrupts must be enabled after unlocking current process
-      to avoid the risk of I2C interrupt handle execution before current
-      process unlock */
-      
-      /* Enable EVT, BUF and ERR interrupt */
-      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-    }
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Write an amount of data in non-blocking mode with DMA to a specific memory address
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address
-  * @param  MemAddress Internal memory address
-  * @param  MemAddSize Size of internal memory address
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
-{
-  __IO uint32_t count = 0U;
-
-  uint32_t tickstart = 0x00U;
-
-  /* Init tickstart for timeout management*/
-  tickstart = HAL_GetTick();
-  
-  /* Check the parameters */
-  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Wait until BUSY flag is reset */
-    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
-    do
-    {
-      if(count-- == 0U)
-      {
-        hi2c->PreviousState = I2C_STATE_NONE;
-        hi2c->State= HAL_I2C_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_TIMEOUT; 
-      }
-    }
-    while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Check if the I2C is already enabled */
-    if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode      = HAL_I2C_MODE_MEM;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr = pData;
-    hi2c->XferSize = Size;
-    hi2c->XferCount = Size;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-
-    if(hi2c->XferSize > 0U)
-    {    
-      /* Send Slave Address and Memory Address */
-      if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
-      {
-        if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-        {
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2c);
-          return HAL_ERROR;
-        }
-        else
-        {
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2c);
-          return HAL_TIMEOUT;
-        }
-      }
-      
-      /* message from ea040a4f9ace1c50abc22ab755415305fd2bda41 */
-      /* dpgeorge: DMA initialisation is moved to after sending the address */
-      
-      /* Set the I2C DMA transfer complete callback */
-      hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
-
-      /* Set the DMA error callback */
-      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
-
-      /* Set the unused DMA callbacks to NULL */
-      hi2c->hdmatx->XferHalfCpltCallback = NULL;
-      hi2c->hdmatx->XferM1CpltCallback = NULL;
-      hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
-      hi2c->hdmatx->XferAbortCallback = NULL;
-
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->DR, Size);
-
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-      
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-      
-      /* Note : The I2C interrupts must be enabled after unlocking current process
-      to avoid the risk of I2C interrupt handle execution before current
-      process unlock */
-      /* Enable ERR interrupt */
-      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
-
-      /* Enable DMA Request */
-      hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
-    }
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Reads an amount of data in non-blocking mode with DMA from a specific memory address.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address
-  * @param  MemAddress Internal memory address
-  * @param  MemAddSize Size of internal memory address
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be read
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
-{
-  uint32_t tickstart = 0x00U;
-
-  /* Init tickstart for timeout management*/
-  tickstart = HAL_GetTick();
-
-  __IO uint32_t count = 0U;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Wait until BUSY flag is reset */
-    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
-    do
-    {
-      if(count-- == 0U)
-      {
-        hi2c->PreviousState = I2C_STATE_NONE;
-        hi2c->State= HAL_I2C_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_TIMEOUT; 
-      }
-    }
-    while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Check if the I2C is already enabled */
-    if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode      = HAL_I2C_MODE_MEM;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr = pData;
-    hi2c->XferCount = Size;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->XferSize    = hi2c->XferCount;
-
-    if(hi2c->XferSize > 0U)
-    {
-      /* Send Slave Address and Memory Address */
-      if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
-      {
-        if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-        {
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2c);
-          return HAL_ERROR;
-        }
-        else
-        {
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2c);
-          return HAL_TIMEOUT;
-        }
-      }
-      
-      /* Set the I2C DMA transfer complete callback */
-      hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
-
-      /* Set the DMA error callback */
-      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-
-      /* Set the unused DMA callbacks to NULL */
-      hi2c->hdmarx->XferHalfCpltCallback = NULL;
-      hi2c->hdmarx->XferM1CpltCallback = NULL;
-      hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
-      hi2c->hdmarx->XferAbortCallback = NULL;
-
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)pData, Size);
-
-      if(Size == 1U)
-      {
-        /* Disable Acknowledge */
-        hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-      }
-      else
-      {
-        /* Enable Last DMA bit */
-        hi2c->Instance->CR2 |= I2C_CR2_LAST;
-      }
-
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      /* Note : The I2C interrupts must be enabled after unlocking current process
-                to avoid the risk of I2C interrupt handle execution before current
-                process unlock */
-      /* Enable ERR interrupt */
-      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
-      
-     /* Enable DMA Request */
-      hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
-    }
-    else
-    {
-      /* Send Slave Address and Memory Address */
-      if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
-      {
-        if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-        {
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2c);
-          return HAL_ERROR;
-        }
-        else
-        {
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2c);
-          return HAL_TIMEOUT;
-        }
-      }
-
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-      /* Generate Stop */
-      hi2c->Instance->CR1 |= I2C_CR1_STOP;
-
-      hi2c->State = HAL_I2C_STATE_READY;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-    }
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Checks if target device is ready for communication.
-  * @note   This function is used with Memory devices
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address
-  * @param  Trials Number of trials
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
-{
-  uint32_t tickstart = 0U, tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, I2C_Trials = 1U;
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-    
-    /* Check if the I2C is already enabled */
-    if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
-    hi2c->State = HAL_I2C_STATE_BUSY;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    
-    do
-    {
-      /* Generate Start */
-      hi2c->Instance->CR1 |= I2C_CR1_START;
-
-      /* Wait until SB flag is set */
-      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
-
-      /* Send slave address */
-      hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
-
-      /* Wait until ADDR or AF flag are set */
-      /* Get tick */
-      tickstart = HAL_GetTick();
-
-      tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
-      tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
-      tmp3 = hi2c->State;
-      while((tmp1 == RESET) && (tmp2 == RESET) && (tmp3 != HAL_I2C_STATE_TIMEOUT))
-      {
-        if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          hi2c->State = HAL_I2C_STATE_TIMEOUT;
-        }
-        tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
-        tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
-        tmp3 = hi2c->State;
-      }
-
-      hi2c->State = HAL_I2C_STATE_READY;
-
-      /* Check if the ADDR flag has been set */
-      if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)
-      {
-        /* Generate Stop */
-        hi2c->Instance->CR1 |= I2C_CR1_STOP;
-
-        /* Clear ADDR Flag */
-        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-        /* Wait until BUSY flag is reset */
-        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-
-        hi2c->State = HAL_I2C_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_OK;
-      }
-      else
-      {
-        /* Generate Stop */
-        hi2c->Instance->CR1 |= I2C_CR1_STOP;
-
-        /* Clear AF Flag */
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-        /* Wait until BUSY flag is reset */
-        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }while(I2C_Trials++ < Trials);
-
-    hi2c->State = HAL_I2C_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_ERROR;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  This function handles I2C event interrupt request.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
-{
-  uint32_t sr2itflags   = READ_REG(hi2c->Instance->SR2);
-  uint32_t sr1itflags   = READ_REG(hi2c->Instance->SR1);
-  uint32_t itsources    = READ_REG(hi2c->Instance->CR2);
-
-  uint32_t CurrentMode  = hi2c->Mode;
-
-  /* Master or Memory mode selected */
-  if((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM))
-  {
-    /* SB Set ----------------------------------------------------------------*/
-    if(((sr1itflags & I2C_FLAG_SB) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
-    {
-      I2C_Master_SB(hi2c);
-    }
-    /* ADD10 Set -------------------------------------------------------------*/
-    else if(((sr1itflags & I2C_FLAG_ADD10) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
-    {
-      I2C_Master_ADD10(hi2c);
-    }
-    /* ADDR Set --------------------------------------------------------------*/
-    else if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
-    {
-      I2C_Master_ADDR(hi2c);
-    }
-
-    /* I2C in mode Transmitter -----------------------------------------------*/
-    if((sr2itflags & I2C_FLAG_TRA) != RESET)
-    {
-      /* TXE set and BTF reset -----------------------------------------------*/
-      if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
-      {
-        I2C_MasterTransmit_TXE(hi2c);
-      }
-      /* BTF set -------------------------------------------------------------*/
-      else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
-      {
-        I2C_MasterTransmit_BTF(hi2c);
-      }
-    }
-    /* I2C in mode Receiver --------------------------------------------------*/
-    else
-    {
-      /* RXNE set and BTF reset -----------------------------------------------*/
-      if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
-      {
-        I2C_MasterReceive_RXNE(hi2c);
-      }
-      /* BTF set -------------------------------------------------------------*/
-      else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
-      {
-        I2C_MasterReceive_BTF(hi2c);
-      }
-    }
-  }
-  /* Slave mode selected */
-  else
-  {
-    /* ADDR set --------------------------------------------------------------*/
-    if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
-    {
-      I2C_Slave_ADDR(hi2c);
-    }
-    /* STOPF set --------------------------------------------------------------*/
-    else if(((sr1itflags & I2C_FLAG_STOPF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
-    {
-      I2C_Slave_STOPF(hi2c);
-    }
-    /* I2C in mode Transmitter -----------------------------------------------*/
-    else if((sr2itflags & I2C_FLAG_TRA) != RESET)
-    {
-      /* TXE set and BTF reset -----------------------------------------------*/
-      if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
-      {
-        I2C_SlaveTransmit_TXE(hi2c);
-      }
-      /* BTF set -------------------------------------------------------------*/
-      else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
-      {
-        I2C_SlaveTransmit_BTF(hi2c);
-      }
-    }
-    /* I2C in mode Receiver --------------------------------------------------*/
-    else
-    {
-      /* RXNE set and BTF reset ----------------------------------------------*/
-      if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
-      {
-        I2C_SlaveReceive_RXNE(hi2c);
-      }
-      /* BTF set -------------------------------------------------------------*/
-      else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
-      {
-        I2C_SlaveReceive_BTF(hi2c);
-      }
-    }
-  }
-}
-
-/**
-  * @brief  This function handles I2C error interrupt request.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
-{
-  uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, tmp4 = 0U;
-  uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1);
-  uint32_t itsources  = READ_REG(hi2c->Instance->CR2);
-
-  /* I2C Bus error interrupt occurred ----------------------------------------*/
-  if(((sr1itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
-  {
-    hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
-
-    /* Clear BERR flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
-  }
-
-  /* I2C Arbitration Loss error interrupt occurred ---------------------------*/
-  if(((sr1itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
-  {
-    hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
-
-    /* Clear ARLO flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
-  }
-
-  /* I2C Acknowledge failure error interrupt occurred ------------------------*/
-  if(((sr1itflags & I2C_FLAG_AF) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
-  {
-    tmp1 = hi2c->Mode;
-    tmp2 = hi2c->XferCount;
-    tmp3 = hi2c->State;
-    tmp4 = hi2c->PreviousState;
-    if((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \
-      ((tmp3 == HAL_I2C_STATE_BUSY_TX) || (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) || \
-      ((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX))))
-    {
-      I2C_Slave_AF(hi2c);
-    }
-    else
-    {
-      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-
-      /* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */
-      if(hi2c->Mode == HAL_I2C_MODE_MASTER)
-      {
-        /* Generate Stop */
-        SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
-      }
-
-      /* Clear AF flag */
-      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-    }
-  }
-
-  /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/
-  if(((sr1itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
-  {
-    hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
-    /* Clear OVR flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
-  }
-
-  /* Call the Error Callback in case of Error detected -----------------------*/
-  if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
-  {
-    I2C_ITError(hi2c);
-  }
-}
-
-/**
-  * @brief  Master Tx Transfer completed callback.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_MasterTxCpltCallback can be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Master Rx Transfer completed callback.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_MasterRxCpltCallback can be implemented in the user file
-   */
-}
-
-/** @brief  Slave Tx Transfer completed callback.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_SlaveTxCpltCallback can be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Slave Rx Transfer completed callback.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_SlaveRxCpltCallback can be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Slave Address Match callback.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferOptions_definition
-  * @param  AddrMatchCode Address Match Code
-  * @retval None
-  */
-__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-  UNUSED(TransferDirection);
-  UNUSED(AddrMatchCode);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_AddrCallback can be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Listen Complete callback.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-    /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_ListenCpltCallback can be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Memory Tx Transfer completed callback.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_MemTxCpltCallback can be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Memory Rx Transfer completed callback.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_MemRxCpltCallback can be implemented in the user file
-   */
-}
-
-/**
-  * @brief  I2C error callback.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_ErrorCallback can be implemented in the user file
-   */
-}
-
-/**
-  * @brief  I2C abort callback.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_AbortCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
-  *  @brief   Peripheral State and Errors functions
-  *
-@verbatim
- ===============================================================================
-            ##### Peripheral State, Mode and Error functions #####
- ===============================================================================
-    [..]
-    This subsection permits to get in run-time the status of the peripheral
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the I2C handle state.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval HAL state
-  */
-HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
-{
-  /* Return I2C handle state */
-  return hi2c->State;
-}
-
-/**
-  * @brief  Return the I2C Master, Slave, Memory or no mode.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL mode
-  */
-HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
-{
-  return hi2c->Mode;
-}
-
-/**
-  * @brief  Return the I2C error code
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *              the configuration information for the specified I2C.
-  * @retval I2C Error Code
-  */
-uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
-{
-  return hi2c->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @brief  Handle TXE flag for Master
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
-{
-  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
-  uint32_t CurrentState       = hi2c->State;
-  uint32_t CurrentMode        = hi2c->Mode;
-  uint32_t CurrentXferOptions = hi2c->XferOptions;
-
-  if((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
-  {
-    /* Call TxCpltCallback() directly if no stop mode is set */
-    if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
-    {
-      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-      hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
-      hi2c->Mode = HAL_I2C_MODE_NONE;
-      hi2c->State = HAL_I2C_STATE_READY;
-
-      HAL_I2C_MasterTxCpltCallback(hi2c);
-    }
-    else /* Generate Stop condition then Call TxCpltCallback() */
-    {
-      /* Disable EVT, BUF and ERR interrupt */
-      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-      /* Generate Stop */
-      hi2c->Instance->CR1 |= I2C_CR1_STOP;
-
-      hi2c->PreviousState = I2C_STATE_NONE;
-      hi2c->State = HAL_I2C_STATE_READY;
-
-      if(hi2c->Mode == HAL_I2C_MODE_MEM)
-      {
-        hi2c->Mode = HAL_I2C_MODE_NONE;
-        HAL_I2C_MemTxCpltCallback(hi2c);
-      }
-      else
-      {
-        hi2c->Mode = HAL_I2C_MODE_NONE;
-        HAL_I2C_MasterTxCpltCallback(hi2c);
-      }
-    }
-  }
-  else if((CurrentState == HAL_I2C_STATE_BUSY_TX) || \
-    ((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX)))
-  {
-    if(hi2c->XferCount == 0U)
-    {
-      /* Disable BUF interrupt */
-      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
-    }
-    else
-    {
-      if(hi2c->Mode == HAL_I2C_MODE_MEM)
-      {
-        if(hi2c->EventCount == 0)
-        {
-          /* If Memory address size is 8Bit */
-          if(hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT)
-          {
-            /* Send Memory Address */
-            hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
-            
-            hi2c->EventCount += 2;
-          }
-          /* If Memory address size is 16Bit */
-          else
-          {
-            /* Send MSB of Memory Address */
-            hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress);
-            
-            hi2c->EventCount++;
-          }
-        }
-        else if(hi2c->EventCount == 1)
-        {
-          /* Send LSB of Memory Address */
-          hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
-          
-          hi2c->EventCount++;
-        }
-        else if(hi2c->EventCount == 2)
-        {
-          if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
-          {
-            /* Generate Restart */
-            hi2c->Instance->CR1 |= I2C_CR1_START;
-          }
-          else if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
-          {
-            /* Write data to DR */
-            hi2c->Instance->DR = (*hi2c->pBuffPtr++);
-            hi2c->XferCount--;
-          }
-        }
-      }
-      else
-      {
-        /* Write data to DR */
-        hi2c->Instance->DR = (*hi2c->pBuffPtr++);
-        hi2c->XferCount--;
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle BTF flag for Master transmitter
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
-{
-  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
-  uint32_t CurrentXferOptions = hi2c->XferOptions;
-
-  if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
-  {    
-    if(hi2c->XferCount != 0U)
-    {
-      /* Write data to DR */
-      hi2c->Instance->DR = (*hi2c->pBuffPtr++);
-      hi2c->XferCount--;
-    }
-    else
-    {
-      /* Call TxCpltCallback() directly if no stop mode is set */
-      if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
-      {
-        __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-        
-        hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
-        hi2c->Mode = HAL_I2C_MODE_NONE;
-        hi2c->State = HAL_I2C_STATE_READY;
-        
-        HAL_I2C_MasterTxCpltCallback(hi2c);
-      }
-      else /* Generate Stop condition then Call TxCpltCallback() */
-      {
-        /* Disable EVT, BUF and ERR interrupt */
-        __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-        
-        /* Generate Stop */
-        hi2c->Instance->CR1 |= I2C_CR1_STOP;
-        
-        hi2c->PreviousState = I2C_STATE_NONE;
-        hi2c->State = HAL_I2C_STATE_READY;
-        
-        if(hi2c->Mode == HAL_I2C_MODE_MEM)
-        {
-          hi2c->Mode = HAL_I2C_MODE_NONE;
-          
-          HAL_I2C_MemTxCpltCallback(hi2c);
-        }
-        else
-        {
-          hi2c->Mode = HAL_I2C_MODE_NONE;
-          
-          HAL_I2C_MasterTxCpltCallback(hi2c);
-        }
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle RXNE flag for Master
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
-{
-  if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
-  {
-    uint32_t tmp = 0U;
-    
-    tmp = hi2c->XferCount;
-    if(tmp > 3U)
-    {
-      /* Read data from DR */
-      (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-      hi2c->XferCount--;
-    }
-    else if((tmp == 2U) || (tmp == 3U))
-    {
-      if(hi2c->XferOptions != I2C_NEXT_FRAME)
-      {
-        /* Disable Acknowledge */
-        hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-        
-        /* Enable Pos */
-        hi2c->Instance->CR1 |= I2C_CR1_POS;
-      }
-      else
-      {
-        /* Enable Acknowledge */
-        hi2c->Instance->CR1 |= I2C_CR1_ACK;
-      }
-      
-      /* Disable BUF interrupt */
-      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
-    }
-    else
-    {
-      if(hi2c->XferOptions != I2C_NEXT_FRAME)
-      {
-        /* Disable Acknowledge */
-        hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-      }
-      else
-      {
-        /* Enable Acknowledge */
-        hi2c->Instance->CR1 |= I2C_CR1_ACK;
-      }
-
-      /* Disable EVT, BUF and ERR interrupt */
-      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-      
-      /* Read data from DR */
-      (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-      hi2c->XferCount--;
-
-      hi2c->State = HAL_I2C_STATE_READY;
-
-      if(hi2c->Mode == HAL_I2C_MODE_MEM)
-      {
-        hi2c->PreviousState = I2C_STATE_NONE;
-        hi2c->Mode = HAL_I2C_MODE_NONE;
-        HAL_I2C_MemRxCpltCallback(hi2c);
-      }
-      else
-      {
-        hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
-        hi2c->Mode = HAL_I2C_MODE_NONE;
-        HAL_I2C_MasterRxCpltCallback(hi2c);
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle BTF flag for Master receiver
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
-{
-  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
-  uint32_t CurrentXferOptions = hi2c->XferOptions;
-
-  if(hi2c->XferCount == 3U)
-  {
-    if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
-    {
-      /* Disable Acknowledge */
-      hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-    }
-
-    /* Read data from DR */
-    (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-    hi2c->XferCount--;
-  }
-  else if(hi2c->XferCount == 2U)
-  {
-    /* Prepare next transfer or stop current transfer */
-    if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
-    {
-      if(CurrentXferOptions != I2C_NEXT_FRAME)
-      {
-        /* Disable Acknowledge */
-        hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-      }
-      else
-      {
-        /* Enable Acknowledge */
-        hi2c->Instance->CR1 |= I2C_CR1_ACK;
-      }
-    }
-    else
-    {
-      /* Generate Stop */
-      hi2c->Instance->CR1 |= I2C_CR1_STOP;
-    }
-
-    /* Read data from DR */
-    (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-    hi2c->XferCount--;
-
-    /* Read data from DR */
-    (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-    hi2c->XferCount--;
-
-    /* Disable EVT and ERR interrupt */
-    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
-
-    hi2c->State = HAL_I2C_STATE_READY;
-    
-    if(hi2c->Mode == HAL_I2C_MODE_MEM)
-    {
-      hi2c->PreviousState = I2C_STATE_NONE;
-      hi2c->Mode = HAL_I2C_MODE_NONE;
-
-      HAL_I2C_MemRxCpltCallback(hi2c);
-    }
-    else
-    {
-      hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
-      hi2c->Mode = HAL_I2C_MODE_NONE;
-
-      HAL_I2C_MasterRxCpltCallback(hi2c);
-    }
-  }
-  else
-  {
-    /* Read data from DR */
-    (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-    hi2c->XferCount--;
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle SB flag for Master
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c)
-{
-  if(hi2c->Mode == HAL_I2C_MODE_MEM)
-  {
-    if(hi2c->EventCount == 0U)
-    {
-      /* Send slave address */
-      hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
-    }
-    else
-    {
-      hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
-    }
-  }
-  else
-  {
-    if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
-    {
-      /* Send slave 7 Bits address */
-      if(hi2c->State == HAL_I2C_STATE_BUSY_TX) 
-      {
-        hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
-      }
-      else
-      {
-        hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
-      }
-    }
-    else
-    {
-      if(hi2c->EventCount == 0U)
-      {
-        /* Send header of slave address */
-        hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress);
-      }
-      else if(hi2c->EventCount == 1U)
-      {
-        /* Send header of slave address */
-        hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress);
-      }
-    }
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle ADD10 flag for Master
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c)
-{
-  /* Send slave address */
-  hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle ADDR flag for Master
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c)
-{
-  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
-  uint32_t CurrentMode        = hi2c->Mode;
-  uint32_t CurrentXferOptions = hi2c->XferOptions;
-  uint32_t Prev_State         = hi2c->PreviousState;
-
-  if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
-  {
-    if((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM))
-    {
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-    }
-    else if((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT))
-    {
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-      
-      /* Generate Restart */
-      hi2c->Instance->CR1 |= I2C_CR1_START;
-      
-      hi2c->EventCount++;
-    }
-    else
-    {
-      if(hi2c->XferCount == 0U)
-      {
-        /* Clear ADDR flag */
-        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-        
-        /* Generate Stop */
-        hi2c->Instance->CR1 |= I2C_CR1_STOP;
-      }
-      else if(hi2c->XferCount == 1U)   
-      {
-        if(CurrentXferOptions == I2C_NO_OPTION_FRAME)
-        {
-          /* Disable Acknowledge */
-            hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
-          if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
-          {
-            /* Disable Acknowledge */
-            hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
-            /* Clear ADDR flag */
-            __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-          }
-          else
-          {
-            /* Clear ADDR flag */
-            __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-            /* Generate Stop */
-            hi2c->Instance->CR1 |= I2C_CR1_STOP;
-          }
-        }
-        /* Prepare next transfer or stop current transfer */
-        else if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \
-          && (Prev_State != I2C_STATE_MASTER_BUSY_RX))
-        {
-          if(hi2c->XferOptions != I2C_NEXT_FRAME)
-          {
-            /* Disable Acknowledge */
-            hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-          }
-          else
-          {
-            /* Enable Acknowledge */
-            hi2c->Instance->CR1 |= I2C_CR1_ACK;
-          }
-          
-          /* Clear ADDR flag */
-          __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-        }
-        else
-        {
-          /* Disable Acknowledge */
-          hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-          
-          /* Clear ADDR flag */
-          __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-          
-          /* Generate Stop */
-          hi2c->Instance->CR1 |= I2C_CR1_STOP;
-        }
-      }
-      else if(hi2c->XferCount == 2U)
-      {
-        if(hi2c->XferOptions != I2C_NEXT_FRAME)
-        {
-          /* Disable Acknowledge */
-          hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-          
-          /* Enable Pos */
-          hi2c->Instance->CR1 |= I2C_CR1_POS;
-        }
-        else
-        {
-          /* Enable Acknowledge */
-          hi2c->Instance->CR1 |= I2C_CR1_ACK;
-        }
-
-        if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
-        {
-          /* Enable Last DMA bit */
-          hi2c->Instance->CR2 |= I2C_CR2_LAST;
-        }
-
-        /* Clear ADDR flag */
-        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-      }
-      else
-      {
-        /* Enable Acknowledge */
-        hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
-        if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
-        {
-          /* Enable Last DMA bit */
-          hi2c->Instance->CR2 |= I2C_CR2_LAST;
-        }
-
-        /* Clear ADDR flag */
-        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-      }
-      
-      /* Reset Event counter  */
-      hi2c->EventCount = 0U;
-    }
-  }
-  else
-  {
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle TXE flag for Slave
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c)
-{
-  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
-  uint32_t CurrentState = hi2c->State;
-
-  if(hi2c->XferCount != 0U)
-  {
-    /* Write data to DR */
-    hi2c->Instance->DR = (*hi2c->pBuffPtr++);
-    hi2c->XferCount--;
-
-    if((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
-    {
-      /* Last Byte is received, disable Interrupt */
-      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
-      
-      /* Set state at HAL_I2C_STATE_LISTEN */
-      hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
-      hi2c->State = HAL_I2C_STATE_LISTEN;
-      
-      /* Call the Tx complete callback to inform upper layer of the end of receive process */
-      HAL_I2C_SlaveTxCpltCallback(hi2c);
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle BTF flag for Slave transmitter
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c)
-{
-  if(hi2c->XferCount != 0U)
-  {
-    /* Write data to DR */
-    hi2c->Instance->DR = (*hi2c->pBuffPtr++);
-    hi2c->XferCount--;
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle RXNE flag for Slave
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c)
-{
-  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
-  uint32_t CurrentState = hi2c->State;
-
-  if(hi2c->XferCount != 0U)
-  {
-    /* Read data from DR */
-    (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-    hi2c->XferCount--;
-
-    if((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
-    {
-      /* Last Byte is received, disable Interrupt */
-      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
-
-      /* Set state at HAL_I2C_STATE_LISTEN */
-      hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
-      hi2c->State = HAL_I2C_STATE_LISTEN;
-
-      /* Call the Rx complete callback to inform upper layer of the end of receive process */
-      HAL_I2C_SlaveRxCpltCallback(hi2c);
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle BTF flag for Slave receiver
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c)
-{
-  if(hi2c->XferCount != 0U)
-  {
-    /* Read data from DR */
-    (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-    hi2c->XferCount--;
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle ADD flag for Slave
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c)
-{
-  uint8_t TransferDirection = I2C_DIRECTION_RECEIVE;
-  uint16_t SlaveAddrCode = 0U;
-
-  /* Transfer Direction requested by Master */
-  if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA) == RESET)
-  {
-    TransferDirection = I2C_DIRECTION_TRANSMIT;
-  }
-  
-  if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_DUALF) == RESET)
-  {
-    SlaveAddrCode = hi2c->Init.OwnAddress1;
-  }
-  else
-  {
-    SlaveAddrCode = hi2c->Init.OwnAddress2;
-  }
-
-  /* Call Slave Addr callback */
-  HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle STOPF flag for Slave
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
-{
-  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
-  uint32_t CurrentState = hi2c->State;
-  
-  /* Disable EVT, BUF and ERR interrupt */
-  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-  /* Clear STOPF flag */
-  __HAL_I2C_CLEAR_STOPFLAG(hi2c);
-
-  /* Disable Acknowledge */
-  hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
-  /* If a DMA is ongoing, Update handle size context */
-  if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
-  {
-    if((hi2c->State == HAL_I2C_STATE_BUSY_RX) || (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))
-    {
-      hi2c->XferCount = __HAL_DMA_GET_COUNTER(hi2c->hdmarx);
-    }
-    else
-    {
-      hi2c->XferCount = __HAL_DMA_GET_COUNTER(hi2c->hdmatx);
-    }
-  }
-
-  /* All data are not transferred, so set error code accordingly */
-  if(hi2c->XferCount != 0U)
-  {
-    /* Store Last receive data if any */
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
-    {
-      /* Read data from DR */
-      (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-      hi2c->XferCount--;
-    }
-
-    /* Store Last receive data if any */
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
-    {
-      /* Read data from DR */
-      (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-      hi2c->XferCount--;
-    }
-
-    /* Set ErrorCode corresponding to a Non-Acknowledge */
-    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-  }
-
-  if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
-  {
-    /* Call the corresponding callback to inform upper layer of End of Transfer */
-    I2C_ITError(hi2c);
-  }
-  else
-  {
-    if((CurrentState == HAL_I2C_STATE_LISTEN ) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) || \
-       (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
-    {
-      hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-      hi2c->PreviousState = I2C_STATE_NONE;
-      hi2c->State = HAL_I2C_STATE_READY;
-      hi2c->Mode = HAL_I2C_MODE_NONE;
-
-      /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
-      HAL_I2C_ListenCpltCallback(hi2c);
-    }
-    else
-    {
-      if((hi2c->PreviousState  == I2C_STATE_SLAVE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX))
-      {
-        hi2c->PreviousState = I2C_STATE_NONE;
-        hi2c->State = HAL_I2C_STATE_READY;
-        hi2c->Mode = HAL_I2C_MODE_NONE;
-
-        HAL_I2C_SlaveRxCpltCallback(hi2c);
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
-{
-  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
-  uint32_t CurrentState       = hi2c->State;
-  uint32_t CurrentXferOptions = hi2c->XferOptions;
-
-  if(((CurrentXferOptions ==  I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) && \
-          (CurrentState == HAL_I2C_STATE_LISTEN))
-  {
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-
-    /* Disable EVT, BUF and ERR interrupt */
-    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-    /* Clear AF flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-    /* Disable Acknowledge */
-    hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
-    hi2c->PreviousState = I2C_STATE_NONE;
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode = HAL_I2C_MODE_NONE;
-      
-    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
-    HAL_I2C_ListenCpltCallback(hi2c);
-  }
-  else if(CurrentState == HAL_I2C_STATE_BUSY_TX)
-  {
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode = HAL_I2C_MODE_NONE;
-    
-    /* Disable EVT, BUF and ERR interrupt */
-    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-    /* Clear AF flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-    /* Disable Acknowledge */
-    hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
-    HAL_I2C_SlaveTxCpltCallback(hi2c);
-  }
-  else
-  {
-    /* Clear AF flag only */
-    /* State Listen, but XferOptions == FIRST or NEXT */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-  }
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  I2C interrupts error process
-  * @param  hi2c I2C handle.
-  * @retval None
-  */
-static void I2C_ITError(I2C_HandleTypeDef *hi2c)
-{
-  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
-  uint32_t CurrentState = hi2c->State;
-
-  if((CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
-  {
-    /* keep HAL_I2C_STATE_LISTEN */
-    hi2c->PreviousState = I2C_STATE_NONE;
-    hi2c->State = HAL_I2C_STATE_LISTEN;
-  }
-  else
-  {
-    /* If state is an abort treatment on going, don't change state */
-    /* This change will be do later */
-    if((hi2c->State != HAL_I2C_STATE_ABORT) && ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) != I2C_CR2_DMAEN))
-    {
-      hi2c->State = HAL_I2C_STATE_READY;
-    }
-    hi2c->PreviousState = I2C_STATE_NONE;
-    hi2c->Mode = HAL_I2C_MODE_NONE;
-  }
-
-  /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */
-  hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
-  /* Abort DMA transfer */
-  if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
-  {
-    hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
-
-    if(hi2c->hdmatx->State != HAL_DMA_STATE_READY)
-    {
-      /* Set the DMA Abort callback : 
-      will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
-      hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
-
-      if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
-      {
-        /* Disable I2C peripheral to prevent dummy data in buffer */
-        __HAL_I2C_DISABLE(hi2c);
-
-        hi2c->State = HAL_I2C_STATE_READY;
-
-        /* Call Directly XferAbortCallback function in case of error */
-        hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
-      }
-    }
-    else
-    {
-      /* Set the DMA Abort callback : 
-      will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
-      hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
-
-      if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
-      {
-        /* Store Last receive data if any */
-        if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
-        {
-          /* Read data from DR */
-          (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-        }
-
-        /* Disable I2C peripheral to prevent dummy data in buffer */
-        __HAL_I2C_DISABLE(hi2c);
-
-        hi2c->State = HAL_I2C_STATE_READY;
-
-        /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
-        hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
-      }
-    }
-  }
-  else if(hi2c->State == HAL_I2C_STATE_ABORT)
-  {
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Store Last receive data if any */
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
-    {
-      /* Read data from DR */
-      (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-    }
-
-    /* Disable I2C peripheral to prevent dummy data in buffer */
-    __HAL_I2C_DISABLE(hi2c);
-
-    /* Call the corresponding callback to inform upper layer of End of Transfer */
-    HAL_I2C_AbortCpltCallback(hi2c);
-  }
-  else
-  {
-    /* Store Last receive data if any */
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
-    {
-      /* Read data from DR */
-      (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-    }
-
-    /* Call user error callback */
-    HAL_I2C_ErrorCallback(hi2c);
-  }
-  /* STOP Flag is not set after a NACK reception */
-  /* So may inform upper layer that listen phase is stopped */
-  /* during NACK error treatment */
-  if((hi2c->State == HAL_I2C_STATE_LISTEN) && ((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF))
-  {
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->PreviousState = I2C_STATE_NONE;
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode = HAL_I2C_MODE_NONE;
-    
-    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
-    HAL_I2C_ListenCpltCallback(hi2c);
-  }
-}
-
-/**
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shift at right before call interface
-  * @param  Timeout Timeout duration
-  * @param  Tickstart Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
-{
-  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
-  uint32_t CurrentXferOptions = hi2c->XferOptions;
-
-  /* Generate Start condition if first transfer */
-  if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
-  {
-    /* Generate Start */
-    hi2c->Instance->CR1 |= I2C_CR1_START;
-  }
-  else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
-  {
-    /* Generate ReStart */
-    hi2c->Instance->CR1 |= I2C_CR1_START;
-  }
-
-  /* Wait until SB flag is set */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
-  {
-    /* Send slave address */
-    hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
-  }
-  else
-  {
-    /* Send header of slave address */
-    hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
-
-    /* Wait until ADD10 flag is set */
-    if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Send slave address */
-    hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
-  }
-
-  /* Wait until ADDR flag is set */
-  if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
-  {
-    if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Master sends target device address for read request.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shift at right before call interface
-  * @param  Timeout Timeout duration
-  * @param  Tickstart Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
-{
-  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
-  uint32_t CurrentXferOptions = hi2c->XferOptions;
-
-  /* Enable Acknowledge */
-  hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
-  /* Generate Start condition if first transfer */
-  if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME)  || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
-  {
-    /* Generate Start */
-    hi2c->Instance->CR1 |= I2C_CR1_START;
-  }
-  else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
-  {
-    /* Generate ReStart */
-    hi2c->Instance->CR1 |= I2C_CR1_START;
-  }
-
-  /* Wait until SB flag is set */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
-  {
-    /* Send slave address */
-    hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
-  }
-  else
-  {
-    /* Send header of slave address */
-    hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
-
-    /* Wait until ADD10 flag is set */
-    if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Send slave address */
-    hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
-
-    /* Wait until ADDR flag is set */
-    if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-    /* Generate Restart */
-    hi2c->Instance->CR1 |= I2C_CR1_START;
-
-    /* Wait until SB flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    /* Send header of slave address */
-    hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress);
-  }
-
-  /* Wait until ADDR flag is set */
-  if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
-  {
-    if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Master sends target device address followed by internal memory address for write request.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  DevAddress Target device address
-  * @param  MemAddress Internal memory address
-  * @param  MemAddSize Size of internal memory address
-  * @param  Timeout Timeout duration
-  * @param  Tickstart Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
-{
-  /* Generate Start */
-  hi2c->Instance->CR1 |= I2C_CR1_START;
-
-  /* Wait until SB flag is set */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Send slave address */
-  hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
-
-  /* Wait until ADDR flag is set */
-  if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
-  {
-    if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Clear ADDR flag */
-  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-  /* Wait until TXE flag is set */
-  if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
-  {
-    if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-    {
-      /* Generate Stop */
-      hi2c->Instance->CR1 |= I2C_CR1_STOP;
-      return HAL_ERROR;
-    }
-    else
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* If Memory address size is 8Bit */
-  if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
-  {
-    /* Send Memory Address */
-    hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
-  }
-  /* If Memory address size is 16Bit */
-  else
-  {
-    /* Send MSB of Memory Address */
-    hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
-
-    /* Wait until TXE flag is set */
-    if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        /* Generate Stop */
-        hi2c->Instance->CR1 |= I2C_CR1_STOP;
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Send LSB of Memory Address */
-    hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Master sends target device address followed by internal memory address for read request.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  DevAddress Target device address
-  * @param  MemAddress Internal memory address
-  * @param  MemAddSize Size of internal memory address
-  * @param  Timeout Timeout duration
-  * @param  Tickstart Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
-{
-  /* Enable Acknowledge */
-  hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
-  /* Generate Start */
-  hi2c->Instance->CR1 |= I2C_CR1_START;
-
-  /* Wait until SB flag is set */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Send slave address */
-  hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
-
-  /* Wait until ADDR flag is set */
-  if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
-  {
-    if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Clear ADDR flag */
-  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-  /* Wait until TXE flag is set */
-  if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
-  {
-    if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-    {
-      /* Generate Stop */
-      hi2c->Instance->CR1 |= I2C_CR1_STOP;
-      return HAL_ERROR;
-    }
-    else
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* If Memory address size is 8Bit */
-  if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
-  {
-    /* Send Memory Address */
-    hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
-  }
-  /* If Memory address size is 16Bit */
-  else
-  {
-    /* Send MSB of Memory Address */
-    hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
-
-    /* Wait until TXE flag is set */
-    if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        /* Generate Stop */
-        hi2c->Instance->CR1 |= I2C_CR1_STOP;
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Send LSB of Memory Address */
-    hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
-  }
-
-  /* Wait until TXE flag is set */
-  if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
-  {
-    if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-    {
-      /* Generate Stop */
-      hi2c->Instance->CR1 |= I2C_CR1_STOP;
-      return HAL_ERROR;
-    }
-    else
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Generate Restart */
-  hi2c->Instance->CR1 |= I2C_CR1_START;
-
-  /* Wait until SB flag is set */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Send slave address */
-  hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
-
-  /* Wait until ADDR flag is set */
-  if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
-  {
-    if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DMA I2C process complete callback.
-  * @param  hdma DMA handle
-  * @retval None
-  */
-static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma)
-{
-  I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-  
-  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
-  uint32_t CurrentState = hi2c->State;
-  uint32_t CurrentMode  = hi2c->Mode;
-
-  if((CurrentState == HAL_I2C_STATE_BUSY_TX) || ((CurrentState == HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE))) 
-  {
-    /* Disable DMA Request */
-    hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
-    
-    hi2c->XferCount = 0U;
-    
-    /* Enable EVT and ERR interrupt */
-    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
-  }
-  else
-  {
-    /* Disable Acknowledge */
-    hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-    
-    /* Generate Stop */
-    hi2c->Instance->CR1 |= I2C_CR1_STOP;
-    
-    /* Disable Last DMA */
-    hi2c->Instance->CR2 &= ~I2C_CR2_LAST;
-    
-    /* Disable DMA Request */
-    hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
-    
-    hi2c->XferCount = 0U;
-
-    /* Check if Errors has been detected during transfer */
-    if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
-    {
-      HAL_I2C_ErrorCallback(hi2c);
-    }
-    else
-    {
-      hi2c->State = HAL_I2C_STATE_READY;
-
-      if(hi2c->Mode == HAL_I2C_MODE_MEM)
-      {
-        hi2c->Mode = HAL_I2C_MODE_NONE;
-
-        HAL_I2C_MemRxCpltCallback(hi2c);
-      }
-      else
-      {
-        hi2c->Mode = HAL_I2C_MODE_NONE;
-
-        HAL_I2C_MasterRxCpltCallback(hi2c);
-      }
-    }
-  }
-}
-
-/**
-  * @brief  DMA I2C communication error callback.
-  * @param  hdma DMA handle
-  * @retval None
-  */
-static void I2C_DMAError(DMA_HandleTypeDef *hdma)
-{
-  I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  /* Disable Acknowledge */
-  hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
-  hi2c->XferCount = 0U;
-
-  hi2c->State = HAL_I2C_STATE_READY;
-  hi2c->Mode = HAL_I2C_MODE_NONE;
-
-  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
-
-  HAL_I2C_ErrorCallback(hi2c);
-}
-
-/**
-  * @brief DMA I2C communication abort callback
-  *        (To be called at end of DMA Abort procedure).
-  * @param hdma: DMA handle.
-  * @retval None
-  */
-static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
-{
-  I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  /* Disable Acknowledge */
-  hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
-  hi2c->XferCount = 0U;
-
-  /* Reset XferAbortCallback */
-  hi2c->hdmatx->XferAbortCallback = NULL;
-  hi2c->hdmarx->XferAbortCallback = NULL;
-
-  /* Check if come from abort from user */
-  if(hi2c->State == HAL_I2C_STATE_ABORT)
-  {
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode = HAL_I2C_MODE_NONE;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Disable I2C peripheral to prevent dummy data in buffer */
-    __HAL_I2C_DISABLE(hi2c);
-
-    /* Call the corresponding callback to inform upper layer of End of Transfer */
-    HAL_I2C_AbortCpltCallback(hi2c);
-  }
-  else
-  {
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode = HAL_I2C_MODE_NONE;
-
-    /* Disable I2C peripheral to prevent dummy data in buffer */
-    __HAL_I2C_DISABLE(hi2c);
-
-    /* Call the corresponding callback to inform upper layer of End of Transfer */
-    HAL_I2C_ErrorCallback(hi2c);
-  }
-}
-
-/**
-  * @brief  This function handles I2C Communication Timeout.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  Flag specifies the I2C flag to check.
-  * @param  Status The new Flag status (SET or RESET).
-  * @param  Timeout Timeout duration
-  * @param  Tickstart Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
-{
-  /* Wait until flag is set */
-  while((__HAL_I2C_GET_FLAG(hi2c, Flag) ? SET : RESET) == Status) 
-  {
-    /* Check for the Timeout */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
-      {
-        hi2c->PreviousState = I2C_STATE_NONE;
-        hi2c->State= HAL_I2C_STATE_READY;
-        hi2c->Mode = HAL_I2C_MODE_NONE;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles I2C Communication Timeout for Master addressing phase.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  Flag specifies the I2C flag to check.
-  * @param  Timeout Timeout duration
-  * @param  Tickstart Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart)
-{
-  while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
-  {
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
-    {
-      /* Generate Stop */
-      hi2c->Instance->CR1 |= I2C_CR1_STOP;
-
-      /* Clear AF Flag */
-      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-      hi2c->ErrorCode = HAL_I2C_ERROR_AF;
-      hi2c->PreviousState = I2C_STATE_NONE;
-      hi2c->State= HAL_I2C_STATE_READY;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      return HAL_ERROR;
-    }
-
-    /* Check for the Timeout */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
-      {
-        hi2c->PreviousState = I2C_STATE_NONE;
-        hi2c->State= HAL_I2C_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles I2C Communication Timeout for specific usage of TXE flag.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  Timeout Timeout duration
-  * @param  Tickstart Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
-{    
-  while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
-  {
-    /* Check if a NACK is detected */
-    if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
-    {
-      return HAL_ERROR;
-    }
-		
-    /* Check for the Timeout */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
-      {
-        hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-        hi2c->PreviousState = I2C_STATE_NONE;
-        hi2c->State= HAL_I2C_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  return HAL_OK;      
-}
-
-/**
-  * @brief  This function handles I2C Communication Timeout for specific usage of BTF flag.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  Timeout Timeout duration
-  * @param  Tickstart Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
-{  
-  while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)
-  {
-    /* Check if a NACK is detected */
-    if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
-    {
-      return HAL_ERROR;
-    }
-
-    /* Check for the Timeout */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
-      {
-        hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-        hi2c->PreviousState = I2C_STATE_NONE;
-        hi2c->State= HAL_I2C_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles I2C Communication Timeout for specific usage of STOP flag.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  Timeout Timeout duration
-  * @param  Tickstart Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
-{  
-  while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
-  {
-    /* Check if a NACK is detected */
-    if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
-    {
-      return HAL_ERROR;
-    }
-
-    /* Check for the Timeout */
-    if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
-    {
-      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-      hi2c->PreviousState = I2C_STATE_NONE;
-      hi2c->State= HAL_I2C_STATE_READY;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      return HAL_TIMEOUT;
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles I2C Communication Timeout for specific usage of RXNE flag.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  Timeout Timeout duration
-  * @param  Tickstart Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
-{  
-
-  while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
-  {
-    /* Check if a STOPF is detected */
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
-    {
-      /* Clear STOP Flag */
-      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-      hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-      hi2c->PreviousState = I2C_STATE_NONE;
-      hi2c->State= HAL_I2C_STATE_READY;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      return HAL_ERROR;
-    }
-
-    /* Check for the Timeout */
-    if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
-    {
-      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-      hi2c->State= HAL_I2C_STATE_READY;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      return HAL_TIMEOUT;
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles Acknowledge failed detection during an I2C Communication.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c)
-{
-  if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
-  {
-    /* Clear NACKF Flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-    hi2c->ErrorCode = HAL_I2C_ERROR_AF;
-    hi2c->PreviousState = I2C_STATE_NONE;
-    hi2c->State= HAL_I2C_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_ERROR;
-  }
-  return HAL_OK;
-}
-/**
-  * @}
-  */
-
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_i2s.c b/stmhal/hal/f4/src/stm32f4xx_hal_i2s.c
deleted file mode 100644
index f368557097..0000000000
--- a/stmhal/hal/f4/src/stm32f4xx_hal_i2s.c
+++ /dev/null
@@ -1,1410 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_i2s.c
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   I2S HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the Integrated Interchip Sound (I2S) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral State and Errors functions
-  @verbatim
- ===============================================================================
-                  ##### How to use this driver #####
- ===============================================================================
- [..]
-    The I2S HAL driver can be used as follow:
-    
-    (#) Declare a I2S_HandleTypeDef handle structure.
-    (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
-        (##) Enable the SPIx interface clock.                      
-        (##) I2S pins configuration:
-            (+++) Enable the clock for the I2S GPIOs.
-            (+++) Configure these I2S pins as alternate function pull-up.
-        (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
-             and HAL_I2S_Receive_IT() APIs).
-            (+++) Configure the I2Sx interrupt priority.
-            (+++) Enable the NVIC I2S IRQ handle.
-        (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
-             and HAL_I2S_Receive_DMA() APIs:
-            (+++) Declare a DMA handle structure for the Tx/Rx stream.
-            (+++) Enable the DMAx interface clock.
-            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
-            (+++) Configure the DMA Tx/Rx Stream.
-            (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
-            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the 
-                DMA Tx/Rx Stream.
-  
-   (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
-       using HAL_I2S_Init() function.
-
-   -@- The specific I2S interrupts (Transmission complete interrupt, 
-       RXNE interrupt and Error Interrupts) will be managed using the macros
-       __I2S_ENABLE_IT() and __I2S_DISABLE_IT() inside the transmit and receive process.
-   -@- Make sure that either:
-        (+@) I2S PLL is configured or 
-        (+@) External clock source is configured after setting correctly 
-             the define constant EXTERNAL_CLOCK_VALUE in the stm32f4xx_hal_conf.h file. 
-             
-   (#) Three operation modes are available within this driver :
-  
-   *** Polling mode IO operation ***
-   =================================
-   [..]    
-     (+) Send an amount of data in blocking mode using HAL_I2S_Transmit() 
-     (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
-   
-   *** Interrupt mode IO operation ***
-   ===================================
-   [..]    
-     (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT() 
-     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can 
-         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback 
-     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can 
-         add his own code by customization of function pointer HAL_I2S_TxCpltCallback
-     (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT() 
-     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can 
-         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback 
-     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can 
-         add his own code by customization of function pointer HAL_I2S_RxCpltCallback
-     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can 
-         add his own code by customization of function pointer HAL_I2S_ErrorCallback
-
-   *** DMA mode IO operation ***
-   ==============================
-   [..] 
-     (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA() 
-     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can 
-         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback 
-     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can 
-         add his own code by customization of function pointer HAL_I2S_TxCpltCallback
-     (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA() 
-     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can 
-         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback 
-     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can 
-         add his own code by customization of function pointer HAL_I2S_RxCpltCallback
-     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can 
-         add his own code by customization of function pointer HAL_I2S_ErrorCallback
-     (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
-     (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
-     (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
-
-   *** I2S HAL driver macros list ***
-   =============================================
-   [..]
-     Below the list of most used macros in USART HAL driver.
-       
-      (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode) 
-      (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
-      (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
-      (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
-      (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
-
-    [..]
-      (@) You can refer to the I2S HAL driver header file for more useful macros
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup I2S I2S
-  * @brief I2S HAL module driver
-  * @{
-  */
-
-#ifdef HAL_I2S_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup I2S_Private_Functions
-  * @{
-  */
-
-/**
-  * @}
-  */
-  
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup I2S_Exported_Functions I2S Exported Functions
-  * @{
-  */
-
-/** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions 
- *
-@verbatim     
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This subsection provides a set of functions allowing to initialize and 
-          de-initialize the I2Sx peripheral in simplex mode:
-
-      (+) User must Implement HAL_I2S_MspInit() function in which he configures 
-          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
-
-      (+) Call the function HAL_I2S_Init() to configure the selected device with 
-          the selected configuration:
-        (++) Mode
-        (++) Standard 
-        (++) Data Format
-        (++) MCLK Output
-        (++) Audio frequency
-        (++) Polarity
-
-      (+) Call the function HAL_I2S_DeInit() to restore the default configuration 
-          of the selected I2Sx peripheral. 
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Initializes the I2S according to the specified parameters 
-  *         in the I2S_InitTypeDef and create the associated handle.
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval HAL status
-  */
-__weak HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
-{
-  uint32_t tmpreg = 0U, i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
-  uint32_t tmp = 0U, i2sclk = 0U;
-  
-  /* Check the I2S handle allocation */
-  if(hi2s == NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  /* Check the I2S parameters */
-  assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
-  assert_param(IS_I2S_MODE(hi2s->Init.Mode));
-  assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
-  assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
-  assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
-  assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
-  assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));  
-  assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource));
-  
-  if(hi2s->State == HAL_I2S_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hi2s->Lock = HAL_UNLOCKED;
-    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
-    HAL_I2S_MspInit(hi2s);
-  }
-  
-  hi2s->State = HAL_I2S_STATE_BUSY;
-  
-  /*----------------------- SPIx I2SCFGR & I2SPR Configuration ---------------*/
-  /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
-  hi2s->Instance->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
-                               SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
-                               SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD); 
-  hi2s->Instance->I2SPR = 0x0002U;
-
-  /* Get the I2SCFGR register value */
-  tmpreg = hi2s->Instance->I2SCFGR;
-
-  /* If the default frequency value has to be written, reinitialize i2sdiv and i2sodd */
-  /* If the requested audio frequency is not the default, compute the prescaler */
-  if(hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
-  {
-    /* Check the frame length (For the Prescaler computing) *******************/
-    if(hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
-    {
-      /* Packet length is 32 bits */
-      packetlength = 2U;
-    }
-
-    /* Get I2S source Clock frequency  ****************************************/
-    /* If an external I2S clock has to be used, the specific define should be set  
-    in the project configuration or in the stm32f4xx_conf.h file */
-    i2sclk = I2S_GetInputClock(hi2s);
-
-    /* Compute the Real divider depending on the MCLK output state, with a floating point */
-    if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
-    {
-      /* MCLK output is enabled */
-      tmp = (uint32_t)(((((i2sclk / 256U) * 10U) / hi2s->Init.AudioFreq)) + 5U);
-    }
-    else
-    {
-      /* MCLK output is disabled */
-      tmp = (uint32_t)(((((i2sclk / (32U * packetlength)) *10U) / hi2s->Init.AudioFreq)) + 5U);
-    }
-
-    /* Remove the flatting point */
-    tmp = tmp / 10U;  
-
-    /* Check the parity of the divider */
-    i2sodd = (uint32_t)(tmp & (uint32_t)1U);
-
-    /* Compute the i2sdiv prescaler */
-    i2sdiv = (uint32_t)((tmp - i2sodd) / 2U);
-
-    /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
-    i2sodd = (uint32_t) (i2sodd << 8U);
-  }
-
-  /* Test if the divider is 1 or 0 or greater than 0xFF */
-  if((i2sdiv < 2U) || (i2sdiv > 0xFFU))
-  {
-    /* Set the default values */
-    i2sdiv = 2U;
-    i2sodd = 0U;
-  }
-  
-  /* Write to SPIx I2SPR register the computed value */
-  hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
-  
-  /* Configure the I2S with the I2S_InitStruct values */
-  tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL);
-  
-#if defined(SPI_I2SCFGR_ASTRTEN)
-  if (hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT) 
-  {
-  /* Write to SPIx I2SCFGR */  
-  hi2s->Instance->I2SCFGR = tmpreg | SPI_I2SCFGR_ASTRTEN;
-  }
-  else
-  {
-  /* Write to SPIx I2SCFGR */  
-  hi2s->Instance->I2SCFGR = tmpreg;    
-  }
-#else
-  /* Write to SPIx I2SCFGR */  
-  hi2s->Instance->I2SCFGR = tmpreg;
-#endif
-  
-  hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-  hi2s->State= HAL_I2S_STATE_READY;
-  
-  return HAL_OK;
-}
-           
-/**
-  * @brief DeInitializes the I2S peripheral 
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
-{
-  /* Check the I2S handle allocation */
-  if(hi2s == NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  hi2s->State = HAL_I2S_STATE_BUSY;
-  
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
-  HAL_I2S_MspDeInit(hi2s);
-
-  hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-  hi2s->State = HAL_I2S_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hi2s);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief I2S MSP Init
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
- __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2s);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2S_MspInit could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief I2S MSP DeInit
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
- __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2s);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2S_MspDeInit could be implemented in the user file
-   */ 
-}
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Exported_Functions_Group2 IO operation functions
- *  @brief    Data transfers functions  
- *
-@verbatim   
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to manage the I2S data 
-    transfers.
-
-    (#) There are two modes of transfer:
-       (++) Blocking mode : The communication is performed in the polling mode. 
-            The status of all data processing is returned by the same function 
-            after finishing transfer.  
-       (++) No-Blocking mode : The communication is performed using Interrupts 
-            or DMA. These functions return the status of the transfer startup.
-            The end of the data processing will be indicated through the 
-            dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when 
-            using DMA mode.
-
-    (#) Blocking mode functions are :
-        (++) HAL_I2S_Transmit()
-        (++) HAL_I2S_Receive()
-        
-    (#) No-Blocking mode functions with Interrupt are :
-        (++) HAL_I2S_Transmit_IT()
-        (++) HAL_I2S_Receive_IT()
-
-    (#) No-Blocking mode functions with DMA are :
-        (++) HAL_I2S_Transmit_DMA()
-        (++) HAL_I2S_Receive_DMA()
-
-    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
-        (++) HAL_I2S_TxCpltCallback()
-        (++) HAL_I2S_RxCpltCallback()
-        (++) HAL_I2S_ErrorCallback()
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Transmit an amount of data in blocking mode
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @param pData: a 16-bit pointer to data buffer.
-  * @param Size: number of data sample to be sent:
-  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
-  *       configuration phase, the Size parameter means the number of 16-bit data length 
-  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
-  *       the Size parameter means the number of 16-bit data length. 
-  * @param  Timeout: Timeout duration
-  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 
-  *       between Master and Slave(example: audio streaming).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint32_t tmp1 = 0U;  
-  if((pData == NULL ) || (Size == 0U)) 
-  {
-    return  HAL_ERROR;
-  }
-  
-  if(hi2s->State == HAL_I2S_STATE_READY)
-  { 
-    tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
-    if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
-    {
-      hi2s->TxXferSize = Size*2U;
-      hi2s->TxXferCount = Size*2U;
-    }
-    else
-    {
-      hi2s->TxXferSize = Size;
-      hi2s->TxXferCount = Size;
-    }
-    
-    /* Process Locked */
-    __HAL_LOCK(hi2s);
-    
-    hi2s->State = HAL_I2S_STATE_BUSY_TX;
-   
-    /* Check if the I2S is already enabled */ 
-    if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
-    {
-      /* Enable I2S peripheral */
-      __HAL_I2S_ENABLE(hi2s);
-    }
-    
-    while(hi2s->TxXferCount > 0U)
-    {
-      hi2s->Instance->DR = (*pData++);
-      hi2s->TxXferCount--;   
-      /* Wait until TXE flag is set */
-      if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
-    } 
-    /* Check if Slave mode is selected */
-    if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
-    {
-      /* Wait until Busy flag is reset */
-      if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-    hi2s->State = HAL_I2S_STATE_READY; 
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2s);
-    
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Receive an amount of data in blocking mode 
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @param pData: a 16-bit pointer to data buffer.
-  * @param Size: number of data sample to be sent:
-  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
-  *       configuration phase, the Size parameter means the number of 16-bit data length 
-  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
-  *       the Size parameter means the number of 16-bit data length. 
-  * @param Timeout: Timeout duration
-  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 
-  *       between Master and Slave(example: audio streaming).
-  * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
-  *       in continuous way and as the I2S is not disabled at the end of the I2S transaction.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint32_t tmp1 = 0U;   
-  if((pData == NULL ) || (Size == 0U)) 
-  {
-    return  HAL_ERROR;
-  }
-  
-  if(hi2s->State == HAL_I2S_STATE_READY)
-  { 
-    tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
-    if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
-    {
-      hi2s->RxXferSize = Size*2U;
-      hi2s->RxXferCount = Size*2U;
-    }
-    else
-    {
-      hi2s->RxXferSize = Size;
-      hi2s->RxXferCount = Size;
-    }
-    /* Process Locked */
-    __HAL_LOCK(hi2s);
-
-    hi2s->State = HAL_I2S_STATE_BUSY_RX;
-
-    /* Check if the I2S is already enabled */ 
-    if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
-    {
-      /* Enable I2S peripheral */
-      __HAL_I2S_ENABLE(hi2s);
-    }
-
-    /* Check if Master Receiver mode is selected */
-    if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
-    {
-      /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
-      access to the SPI_SR register. */ 
-      __HAL_I2S_CLEAR_OVRFLAG(hi2s);
-    }
-
-    /* Receive data */
-    while(hi2s->RxXferCount > 0U)
-    {
-      /* Wait until RXNE flag is set */
-      if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
-
-      (*pData++) = hi2s->Instance->DR;
-      hi2s->RxXferCount--;
-    }
-
-    hi2s->State = HAL_I2S_STATE_READY; 
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2s);
-    
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Transmit an amount of data in non-blocking mode with Interrupt
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @param pData: a 16-bit pointer to data buffer.
-  * @param Size: number of data sample to be sent:
-  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
-  *       configuration phase, the Size parameter means the number of 16-bit data length 
-  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
-  *       the Size parameter means the number of 16-bit data length. 
-  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 
-  *       between Master and Slave(example: audio streaming).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
-{
-  uint32_t tmp1 = 0U;     
-  if(hi2s->State == HAL_I2S_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0U)) 
-    {
-      return  HAL_ERROR;
-    }
-
-    hi2s->pTxBuffPtr = pData;
-    tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
-    if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
-    {
-      hi2s->TxXferSize = Size*2U;
-      hi2s->TxXferCount = Size*2U;
-    }
-    else
-    {
-      hi2s->TxXferSize = Size;
-      hi2s->TxXferCount = Size;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2s);
-
-    hi2s->State = HAL_I2S_STATE_BUSY_TX;
-    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-
-    /* Enable TXE and ERR interrupt */
-    __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
-    /* Check if the I2S is already enabled */ 
-    if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
-    {
-      /* Enable I2S peripheral */
-      __HAL_I2S_ENABLE(hi2s);
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2s);
-    
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Receive an amount of data in non-blocking mode with Interrupt
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @param pData: a 16-bit pointer to the Receive data buffer.
-  * @param Size: number of data sample to be sent:
-  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
-  *       configuration phase, the Size parameter means the number of 16-bit data length 
-  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
-  *       the Size parameter means the number of 16-bit data length. 
-  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 
-  *       between Master and Slave(example: audio streaming).
-  * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation 
-  * between Master and Slave otherwise the I2S interrupt should be optimized. 
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
-{
-  uint32_t tmp1 = 0U;     
-  if(hi2s->State == HAL_I2S_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0U)) 
-    {
-      return  HAL_ERROR;
-    }
-
-    hi2s->pRxBuffPtr = pData;
-    tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
-    if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
-    {
-      hi2s->RxXferSize = Size*2U;
-      hi2s->RxXferCount = Size*2U;
-    }
-    else
-    {
-      hi2s->RxXferSize = Size;
-      hi2s->RxXferCount = Size;
-    }
-    /* Process Locked */
-    __HAL_LOCK(hi2s);
-    
-    hi2s->State = HAL_I2S_STATE_BUSY_RX;
-    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-    
-    /* Enable TXE and ERR interrupt */
-    __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-    
-    /* Check if the I2S is already enabled */ 
-    if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
-    {
-      /* Enable I2S peripheral */
-      __HAL_I2S_ENABLE(hi2s);
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2s);
-
-    return HAL_OK;
-  }
-
-  else
-  {
-    return HAL_BUSY; 
-  } 
-}
-
-/**
-  * @brief Transmit an amount of data in non-blocking mode with DMA
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @param pData: a 16-bit pointer to the Transmit data buffer.
-  * @param Size: number of data sample to be sent:
-  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
-  *       configuration phase, the Size parameter means the number of 16-bit data length 
-  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
-  *       the Size parameter means the number of 16-bit data length. 
-  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 
-  *       between Master and Slave(example: audio streaming).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
-{
-  uint32_t *tmp;
-  uint32_t tmp1 = 0U;     
-  
-  if((pData == NULL) || (Size == 0U)) 
-  {
-    return  HAL_ERROR;
-  }
-
-  if(hi2s->State == HAL_I2S_STATE_READY)
-  {  
-    hi2s->pTxBuffPtr = pData;
-    tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
-    if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
-    {
-      hi2s->TxXferSize = Size*2U;
-      hi2s->TxXferCount = Size*2U;
-    }
-    else
-    {
-      hi2s->TxXferSize = Size;
-      hi2s->TxXferCount = Size;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2s);
-
-    hi2s->State = HAL_I2S_STATE_BUSY_TX;
-    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-
-    /* Set the I2S Tx DMA Half transfer complete callback */
-    hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
-
-    /* Set the I2S Tx DMA transfer complete callback */
-    hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
-
-    /* Set the DMA error callback */
-    hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
-
-    /* Enable the Tx DMA Stream */
-    tmp = (uint32_t*)&pData;
-    HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
-
-    /* Check if the I2S is already enabled */ 
-    if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
-    {
-      /* Enable I2S peripheral */
-      __HAL_I2S_ENABLE(hi2s);
-    }
-
-     /* Check if the I2S Tx request is already enabled */ 
-    if((hi2s->Instance->CR2 & SPI_CR2_TXDMAEN) != SPI_CR2_TXDMAEN)
-    {
-      /* Enable Tx DMA Request */  
-      hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2s);
-    
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Receive an amount of data in non-blocking mode with DMA 
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @param pData: a 16-bit pointer to the Receive data buffer.
-  * @param Size: number of data sample to be sent:
-  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
-  *       configuration phase, the Size parameter means the number of 16-bit data length 
-  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
-  *       the Size parameter means the number of 16-bit data length. 
-  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 
-  *       between Master and Slave(example: audio streaming).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
-{
-  uint32_t *tmp;
-  uint32_t tmp1 = 0U;  
-  
-  if((pData == NULL) || (Size == 0U))
-  {
-    return  HAL_ERROR;
-  }
-
-  if(hi2s->State == HAL_I2S_STATE_READY)
-  {
-    hi2s->pRxBuffPtr = pData;
-    tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
-    if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
-    {
-      hi2s->RxXferSize = Size*2U;
-      hi2s->RxXferCount = Size*2U;
-    }
-    else
-    {
-      hi2s->RxXferSize = Size;
-      hi2s->RxXferCount = Size;
-    }
-    /* Process Locked */
-    __HAL_LOCK(hi2s);
-    
-    hi2s->State = HAL_I2S_STATE_BUSY_RX;
-    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-    
-    /* Set the I2S Rx DMA Half transfer complete callback */
-    hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
-    
-    /* Set the I2S Rx DMA transfer complete callback */
-    hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
-    
-    /* Set the DMA error callback */
-    hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
-    
-    /* Check if Master Receiver mode is selected */
-    if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
-    {
-      /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
-      access to the SPI_SR register. */ 
-      __HAL_I2S_CLEAR_OVRFLAG(hi2s);
-    }
-    
-    /* Enable the Rx DMA Stream */
-    tmp = (uint32_t*)&pData;
-    HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
-    
-    /* Check if the I2S is already enabled */ 
-    if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
-    {
-      /* Enable I2S peripheral */
-      __HAL_I2S_ENABLE(hi2s);
-    }
-
-     /* Check if the I2S Rx request is already enabled */ 
-    if((hi2s->Instance->CR2 &SPI_CR2_RXDMAEN) != SPI_CR2_RXDMAEN)
-    {
-      /* Enable Rx DMA Request */  
-      hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2s);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Pauses the audio stream playing from the Media.
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval HAL status
-  */
-__weak HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
-{
-  /* Process Locked */
-  __HAL_LOCK(hi2s);
-  
-  if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
-  {
-    /* Disable the I2S DMA Tx request */
-    hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
-  }
-  else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
-  {
-    /* Disable the I2S DMA Rx request */
-    hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
-  }
-  else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
-  {
-    if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
-    {
-      /* Disable the I2S DMA Tx request */
-      hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
-    }
-    else
-    {
-      /* Disable the I2S DMA Rx request */
-      hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
-    }
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hi2s);
-  
-  return HAL_OK; 
-}
-
-/**
-  * @brief Resumes the audio stream playing from the Media.
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval HAL status
-  */
-__weak HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
-{
-  /* Process Locked */
-  __HAL_LOCK(hi2s);
-  
-  if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
-  {
-    /* Enable the I2S DMA Tx request */
-    hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
-  }
-  else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
-  {
-    /* Enable the I2S DMA Rx request */
-    hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
-  }
-  else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
-  {
-    if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
-    {
-      /* Enable the I2S DMA Tx request */
-      hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
-    }
-    else
-    {
-      /* Enable the I2S DMA Rx request */
-      hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
-    }
-  }
-
-  /* If the I2S peripheral is still not enabled, enable it */
-  if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U)
-  {
-    /* Enable I2S peripheral */    
-    __HAL_I2S_ENABLE(hi2s);
-  }
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hi2s);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief Resumes the audio stream playing from the Media.
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval HAL status
-  */
-__weak HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
-{
-  /* Process Locked */
-  __HAL_LOCK(hi2s);
-  
-  /* Disable the I2S Tx/Rx DMA requests */
-  hi2s->Instance->CR2 &= ~SPI_CR2_TXDMAEN;
-  hi2s->Instance->CR2 &= ~SPI_CR2_RXDMAEN;
-
-  /* Abort the I2S DMA Stream tx */
-  if(hi2s->hdmatx != NULL)
-  {
-    HAL_DMA_Abort(hi2s->hdmatx);
-  }
-  /* Abort the I2S DMA Stream rx */
-  if(hi2s->hdmarx != NULL)
-  {
-    HAL_DMA_Abort(hi2s->hdmarx);
-  }
-
-  /* Disable I2S peripheral */
-  __HAL_I2S_DISABLE(hi2s);
-  
-  hi2s->State = HAL_I2S_STATE_READY;
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hi2s);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles I2S interrupt request.
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
-__weak void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
-{  
-  uint32_t tmp1 = 0U, tmp2 = 0U; 
-
-    if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
-    {
-      tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE);
-      tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE);
-      /* I2S in mode Receiver ------------------------------------------------*/
-      if((tmp1 != RESET) && (tmp2 != RESET))
-      {
-        I2S_Receive_IT(hi2s);
-      }
-
-      tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR);
-      tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
-      /* I2S Overrun error interrupt occurred ---------------------------------*/
-      if((tmp1 != RESET) && (tmp2 != RESET))
-      {
-        __HAL_I2S_CLEAR_OVRFLAG(hi2s);
-        hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
-      }
-    }
-
-    if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
-    {
-      tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE);
-      tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE);
-      /* I2S in mode Transmitter -----------------------------------------------*/
-      if((tmp1 != RESET) && (tmp2 != RESET))
-      {
-        I2S_Transmit_IT(hi2s);
-      }
-
-      tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR);
-      tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
-      /* I2S Underrun error interrupt occurred --------------------------------*/
-      if((tmp1 != RESET) && (tmp2 != RESET))
-      {
-        __HAL_I2S_CLEAR_UDRFLAG(hi2s);
-        hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
-    }
-  }
-
-  /* Call the Error call Back in case of Errors */
-  if(hi2s->ErrorCode != HAL_I2S_ERROR_NONE)
-  {
-    /* Set the I2S state ready to be able to start again the process */
-    hi2s->State= HAL_I2S_STATE_READY;
-    HAL_I2S_ErrorCallback(hi2s);
-  }
-}
-
-/**
-  * @brief Tx Transfer Half completed callbacks
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
- __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2s);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief Tx Transfer completed callbacks
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
- __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2s);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2S_TxCpltCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief Rx Transfer half completed callbacks
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
-__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2s);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2S_RxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief Rx Transfer completed callbacks
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
-__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2s);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2S_RxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief I2S error callbacks
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
- __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2s);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2S_ErrorCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions 
-  *  @brief   Peripheral State functions
-@verbatim   
- ===============================================================================
-                      ##### Peripheral State and Errors functions #####
- ===============================================================================  
-    [..]
-    This subsection permits to get in run-time the status of the peripheral 
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the I2S state
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval HAL state
-  */
-HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
-{
-  return hi2s->State;
-}
-
-/**
-  * @brief  Return the I2S error code
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval I2S Error Code
-  */
-uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
-{
-  return hi2s->ErrorCode;
-}
-/**
-  * @}
-  */
-
-/**
-  * @brief DMA I2S transmit process half complete callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
- void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  HAL_I2S_TxHalfCpltCallback(hi2s);
-}
-
-/**
-  * @brief DMA I2S receive process half complete callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  HAL_I2S_RxHalfCpltCallback(hi2s); 
-}
-
-/**
-  * @brief DMA I2S communication error callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-void I2S_DMAError(DMA_HandleTypeDef *hdma)
-{
-  I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  hi2s->TxXferCount = 0U;
-  hi2s->RxXferCount = 0U;
-
-  hi2s->State= HAL_I2S_STATE_READY;
-
-  hi2s->ErrorCode |= HAL_I2S_ERROR_DMA;
-  HAL_I2S_ErrorCallback(hi2s);
-}
-
-/**
-  * @brief Transmit an amount of data in non-blocking mode with Interrupt
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
-{
- if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hi2s);
-
-    /* Transmit data */
-    hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
-
-    hi2s->TxXferCount--;	
-    
-    if(hi2s->TxXferCount == 0U)
-    {
-      /* Disable TXE and ERR interrupt */
-      __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-      
-      hi2s->State = HAL_I2S_STATE_READY;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2s);
-      HAL_I2S_TxCpltCallback(hi2s);
-    }
-    else
-    {
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2s);
-    }
-
-    return HAL_OK;
-  }
-  
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Receive an amount of data in non-blocking mode with Interrupt
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
-{
-  if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hi2s);
-
-    /* Receive data */
-    (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
-
-    hi2s->RxXferCount--;
-
-    /* Check if Master Receiver mode is selected */
-    if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
-    {
-      /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
-      access to the SPI_SR register. */ 
-      __HAL_I2S_CLEAR_OVRFLAG(hi2s);
-    }
-
-    if(hi2s->RxXferCount == 0U)
-    {
-      /* Disable RXNE and ERR interrupt */
-      __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_RXNE | I2S_IT_ERR);
-
-      hi2s->State = HAL_I2S_STATE_READY;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2s);
-
-      HAL_I2S_RxCpltCallback(hi2s);
-    }
-    else
-    {
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2s);
-    }
-
-    return HAL_OK; 
-  }
-  else
-  {
-    return HAL_BUSY; 
-  } 
-}
-
-/**
-  * @brief This function handles I2S Communication Timeout.
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @param Flag: Flag checked
-  * @param Status: Value of the flag expected
-  * @param Timeout: Duration of the timeout
-  * @retval HAL status
-  */
-HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout)
-{
-  uint32_t tickstart = 0U;
-  
-  /* Get tick */
-  tickstart = HAL_GetTick();
-  
-  /* Wait until flag is set */
-  if(Status == RESET)
-  {
-    while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)
-    {
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Set the I2S State ready */
-          hi2s->State= HAL_I2S_STATE_READY;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2s);
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  else
-  {
-    while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)
-    {
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Set the I2S State ready */
-          hi2s->State= HAL_I2S_STATE_READY;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2s);
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-  
-#endif /* HAL_I2S_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_i2s_ex.c b/stmhal/hal/f4/src/stm32f4xx_hal_i2s_ex.c
deleted file mode 100644
index dfc4daf43f..0000000000
--- a/stmhal/hal/f4/src/stm32f4xx_hal_i2s_ex.c
+++ /dev/null
@@ -1,1478 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_i2s_ex.c
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   I2S HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of I2S extension peripheral:
-  *           + Extension features Functions
-  *         
-  @verbatim
-  ==============================================================================
-                    ##### I2S Extension features #####
-  ==============================================================================
-  [..]
-     (#) In I2S full duplex mode, each SPI peripheral is able to manage sending and receiving 
-         data simultaneously using two data lines. Each SPI peripheral has an extended block 
-         called I2Sxext (i.e I2S2ext for SPI2 and I2S3ext for SPI3).
-     (#) The extension block is not a full SPI IP, it is used only as I2S slave to
-         implement full duplex mode. The extension block uses the same clock sources
-         as its master.
-
-     (#) Both I2Sx and I2Sx_ext can be configured as transmitters or receivers.
-
-     [..]
-       (@) Only I2Sx can deliver SCK and WS to I2Sx_ext in full duplex mode, where 
-         I2Sx can be I2S2 or I2S3.
-
-                  ##### How to use this driver #####
- ===============================================================================
- [..]    
-   Three operation modes are available within this driver :     
-  
-   *** Polling mode IO operation ***
-   =================================
-   [..]    
-     (+) Send and receive in the same time an amount of data in blocking mode using HAL_I2S_TransmitReceive() 
-   
-   *** Interrupt mode IO operation ***    
-   ===================================
-   [..]    
-     (+) Send and receive in the same time an amount of data in non blocking mode using HAL_I2S_TransmitReceive_IT() 
-     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can 
-         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback 
-     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can 
-         add his own code by customization of function pointer HAL_I2S_TxCpltCallback
-     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can 
-         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback 
-     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can 
-         add his own code by customization of function pointer HAL_I2S_RxCpltCallback                                      
-     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can 
-         add his own code by customization of function pointer HAL_I2S_ErrorCallback
-
-   *** DMA mode IO operation ***    
-   ==============================
-   [..] 
-     (+) Send and receive an amount of data in non blocking mode (DMA) using HAL_I2S_TransmitReceive_DMA() 
-     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can 
-         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback 
-     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can 
-         add his own code by customization of function pointer HAL_I2S_TxCpltCallback
-     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can 
-         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback 
-     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can 
-         add his own code by customization of function pointer HAL_I2S_RxCpltCallback                                     
-     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can 
-         add his own code by customization of function pointer HAL_I2S_ErrorCallback
-     (+) Pause the DMA Transfer using HAL_I2S_DMAPause()      
-     (+) Resume the DMA Transfer using HAL_I2S_DMAResume()  
-     (+) Stop the DMA Transfer using HAL_I2S_DMAStop()  
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup I2SEx I2SEx
-  * @brief I2S HAL module driver
-  * @{
-  */
-
-#ifdef HAL_I2S_MODULE_ENABLED
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/** @addtogroup I2SEx_Private_Functions
-  * @{
-  */
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup I2SEx_Exported_Functions I2S Exported Functions
-  * @{
-  */
-
-/** @defgroup I2SEx_Group1 Extension features functions 
-  *  @brief   Extension features functions
-  *
-@verbatim    
- ===============================================================================
-                       ##### Extension features Functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to manage the I2S data 
-    transfers.
-
-    (#) There are two modes of transfer:
-       (++) Blocking mode : The communication is performed in the polling mode. 
-            The status of all data processing is returned by the same function 
-            after finishing transfer.  
-       (++) No-Blocking mode : The communication is performed using Interrupts 
-            or DMA. These functions return the status of the transfer startup.
-            The end of the data processing will be indicated through the 
-            dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when 
-            using DMA mode.
-
-    (#) Blocking mode functions are :
-        (++) HAL_I2S_TransmitReceive()
-        
-    (#) No-Blocking mode functions with Interrupt are :
-        (++) HAL_I2S_TransmitReceive_IT()
-
-    (#) No-Blocking mode functions with DMA are :
-        (++) HAL_I2S_TransmitReceive_DMA()
-
-    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
-        (++) HAL_I2S_TxCpltCallback()
-        (++) HAL_I2S_RxCpltCallback()
-        (++) HAL_I2S_ErrorCallback()
-
-@endverbatim
-  * @{
-  */
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
-    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) ||\
-    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
-    defined(STM32F412Cx)
-/**
-  * @brief Initializes the I2S according to the specified parameters 
-  *         in the I2S_InitTypeDef and create the associated handle.
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
-{
-  uint32_t tmpreg = 0U, i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
-  uint32_t tmp = 0U, i2sclk = 0U;
-  
-  /* Check the I2S handle allocation */
-  if(hi2s == NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  /* Check the I2S parameters */
-  assert_param(IS_I2S_MODE(hi2s->Init.Mode));
-  assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
-  assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
-  assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
-  assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
-  assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));  
-  assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource));
-  
-  if(hi2s->State == HAL_I2S_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hi2s->Lock = HAL_UNLOCKED;
-    /* Init the low level hardware : GPIO, CLOCK, CORTEX */
-    HAL_I2S_MspInit(hi2s);
-  }
-  
-  hi2s->State = HAL_I2S_STATE_BUSY;
-  
-  /*----------------------- SPIx I2SCFGR & I2SPR Configuration ---------------*/
-  /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
-  hi2s->Instance->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
-                               SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
-                               SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD); 
-  hi2s->Instance->I2SPR = 0x0002U;
-
-  /* Get the I2SCFGR register value */
-  tmpreg = hi2s->Instance->I2SCFGR;
-
-  /* If the default frequency value has to be written, reinitialize i2sdiv and i2sodd */
-  /* If the requested audio frequency is not the default, compute the prescaler */
-  if(hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
-  {
-    /* Check the frame length (For the Prescaler computing) *******************/
-    if(hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
-    {
-      /* Packet length is 32 bits */
-      packetlength = 2U;
-    }
-
-    /* Get I2S source Clock frequency  ****************************************/
-    i2sclk = I2S_GetInputClock(hi2s);
-
-    /* Compute the Real divider depending on the MCLK output state, with a floating point */
-    if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
-    {
-      /* MCLK output is enabled */
-      tmp = (uint32_t)(((((i2sclk / 256U) * 10U) / hi2s->Init.AudioFreq)) + 5U);
-    }
-    else
-    {
-      /* MCLK output is disabled */
-      tmp = (uint32_t)(((((i2sclk / (32U * packetlength)) * 10U) / hi2s->Init.AudioFreq)) + 5U);
-    }
-
-    /* Remove the flatting point */
-    tmp = tmp / 10U;  
-
-    /* Check the parity of the divider */
-    i2sodd = (uint32_t)(tmp & (uint32_t)1U);
-
-    /* Compute the i2sdiv prescaler */
-    i2sdiv = (uint32_t)((tmp - i2sodd) / 2U);
-
-    /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
-    i2sodd = (uint32_t) (i2sodd << 8U);
-  }
-
-  /* Test if the divider is 1 or 0 or greater than 0xFF */
-  if((i2sdiv < 2U) || (i2sdiv > 0xFFU))
-  {
-    /* Set the default values */
-    i2sdiv = 2U;
-    i2sodd = 0U;
-  }
-  
-  /* Write to SPIx I2SPR register the computed value */
-  hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
-  
-  /* Configure the I2S with the I2S_InitStruct values */
-  tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL);
-  
-#if defined(SPI_I2SCFGR_ASTRTEN)
-  if (hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT) 
-  {
-  /* Write to SPIx I2SCFGR */  
-  hi2s->Instance->I2SCFGR = tmpreg | SPI_I2SCFGR_ASTRTEN;
-  }
-  else
-  {
-  /* Write to SPIx I2SCFGR */  
-  hi2s->Instance->I2SCFGR = tmpreg;    
-  }
-#else
-  /* Write to SPIx I2SCFGR */  
-  hi2s->Instance->I2SCFGR = tmpreg;
-#endif
-      
-  /* Configure the I2S extended if the full duplex mode is enabled */
-  assert_param(IS_I2S_FULLDUPLEX_MODE(hi2s->Init.FullDuplexMode));
-  if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
-  {    
-    /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
-    I2SxEXT(hi2s->Instance)->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
-                                          SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
-                                          SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD);
-    I2SxEXT(hi2s->Instance)->I2SPR = 2U;
-    
-    /* Get the I2SCFGR register value */
-    tmpreg = I2SxEXT(hi2s->Instance)->I2SCFGR;
-    
-    /* Get the mode to be configured for the extended I2S */
-    if((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
-    {
-      tmp = I2S_MODE_SLAVE_RX;
-    }
-    else
-    {
-      if((hi2s->Init.Mode == I2S_MODE_MASTER_RX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_RX))
-      {
-        tmp = I2S_MODE_SLAVE_TX;
-      }
-    }
-    
-    /* Configure the I2S Slave with the I2S Master parameter values */
-    tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | tmp | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL);
-    
-    /* Write to SPIx I2SCFGR */  
-    I2SxEXT(hi2s->Instance)->I2SCFGR = tmpreg;
-  }
-  
-  hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-  hi2s->State= HAL_I2S_STATE_READY;
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief Full-Duplex Transmit/Receive data in blocking mode.
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @param pTxData: a 16-bit pointer to the Transmit data buffer.
-  * @param pRxData: a 16-bit pointer to the Receive data buffer.
-  * @param Size: number of data sample to be sent:
-  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
-  *       configuration phase, the Size parameter means the number of 16-bit data length 
-  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
-  *       the Size parameter means the number of 16-bit data length. 
-  * @param Timeout: Timeout duration
-  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 
-  *       between Master and Slave(example: audio streaming).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout)
-{
-  uint32_t tickstart = 0U;
-  uint32_t tmp1 = 0U;
- 
-  if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U)) 
-  {
-    return  HAL_ERROR;
-  }
-
-  /* Check the I2S State */
-  if(hi2s->State == HAL_I2S_STATE_READY)
-  {  
-    tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
-    /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended 
-       is selected during the I2S configuration phase, the Size parameter means the number
-       of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data 
-       frame is selected the Size parameter means the number of 16-bit data length. */
-    if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
-    {
-      hi2s->TxXferSize = Size*2U;
-      hi2s->TxXferCount = Size*2U;
-      hi2s->RxXferSize = Size*2U;
-      hi2s->RxXferCount = Size*2U;
-    }
-    else
-    {
-      hi2s->TxXferSize = Size;
-      hi2s->TxXferCount = Size;
-      hi2s->RxXferSize = Size;
-      hi2s->RxXferCount = Size;
-    }
-    
-    /* Process Locked */
-    __HAL_LOCK(hi2s);
-    
-    /* Set the I2S State busy TX/RX */
-    hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
-    
-    tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
-    /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
-    if((tmp1 == I2S_MODE_MASTER_TX) || (tmp1 == I2S_MODE_SLAVE_TX))
-    { 
-      /* Check if the I2S is already enabled: The I2S is kept enabled at the end of transaction
-      to avoid the clock de-synchronization between Master and Slave. */ 
-      if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
-      {
-        /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
-        I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
-
-        /* Enable I2Sx peripheral */
-        __HAL_I2S_ENABLE(hi2s);
-      }
-      
-      while(hi2s->TxXferCount > 0U)
-      {
-        /* Wait until TXE flag is set */
-        if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-        hi2s->Instance->DR = (*pTxData++);
-
-        /* Get tick */
-        tickstart = HAL_GetTick();
-
-        /* Wait until RXNE flag is set */
-        while((I2SxEXT(hi2s->Instance)->SR & SPI_SR_RXNE) != SPI_SR_RXNE)
-        {
-          if(Timeout != HAL_MAX_DELAY)
-          {
-            if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
-            {
-              /* Process Unlocked */
-              __HAL_UNLOCK(hi2s);
-
-              return HAL_TIMEOUT;
-            }
-          }
-        }
-        (*pRxData++) = I2SxEXT(hi2s->Instance)->DR;
-        
-        hi2s->TxXferCount--;
-        hi2s->RxXferCount--;
-      }
-    }
-    /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
-    else
-    {
-      /* Check if the I2S is already enabled */ 
-      if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
-      {
-        /* Enable I2S peripheral before the I2Sext*/
-        __HAL_I2S_ENABLE(hi2s);
-
-        /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
-        I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
-      }
-      else
-      {
-        /* Check if Master Receiver mode is selected */
-        if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
-        {
-          /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
-          access to the SPI_SR register. */ 
-          __HAL_I2S_CLEAR_OVRFLAG(hi2s);
-        }
-      }
-      while(hi2s->TxXferCount > 0U)
-      {
-        /* Get tick */
-        tickstart = HAL_GetTick();
-
-        /* Wait until TXE flag is set */
-        while((I2SxEXT(hi2s->Instance)->SR & SPI_SR_TXE) != SPI_SR_TXE)
-        {
-          if(Timeout != HAL_MAX_DELAY)
-          {
-            if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
-            {
-              /* Process Unlocked */
-              __HAL_UNLOCK(hi2s);
-
-              return HAL_TIMEOUT;
-            }
-          }
-        }
-        I2SxEXT(hi2s->Instance)->DR = (*pTxData++);
-        
-        /* Wait until RXNE flag is set */
-        if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-        (*pRxData++) = hi2s->Instance->DR;
-
-        hi2s->TxXferCount--;
-        hi2s->RxXferCount--;
-      }
-    }
-
-    /* Set the I2S State ready */
-    hi2s->State = HAL_I2S_STATE_READY; 
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2s);
-    
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt 
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @param pTxData: a 16-bit pointer to the Transmit data buffer.
-  * @param pRxData: a 16-bit pointer to the Receive data buffer.
-  * @param Size: number of data sample to be sent:
-  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
-  *       configuration phase, the Size parameter means the number of 16-bit data length 
-  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
-  *       the Size parameter means the number of 16-bit data length. 
-  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 
-  *       between Master and Slave(example: audio streaming).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
-{
-  uint32_t tmp1 = 0U;
-  
-  if(hi2s->State == HAL_I2S_STATE_READY)
-  {
-    if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U)) 
-    {
-      return  HAL_ERROR;
-    }
-
-    hi2s->pTxBuffPtr = pTxData;
-    hi2s->pRxBuffPtr = pRxData;
-
-    tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
-    /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended 
-       is selected during the I2S configuration phase, the Size parameter means the number
-       of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data 
-       frame is selected the Size parameter means the number of 16-bit data length. */
-    if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
-    {
-      hi2s->TxXferSize = Size*2U;
-      hi2s->TxXferCount = Size*2U;
-      hi2s->RxXferSize = Size*2U;
-      hi2s->RxXferCount = Size*2U;
-    }  
-    else
-    {
-      hi2s->TxXferSize = Size;
-      hi2s->TxXferCount = Size;
-      hi2s->RxXferSize = Size;
-      hi2s->RxXferCount = Size;
-    }
-    
-    /* Process Locked */
-    __HAL_LOCK(hi2s);
-    
-    hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
-    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-
-    tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
-    /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
-    if((tmp1 == I2S_MODE_MASTER_TX) || (tmp1 == I2S_MODE_SLAVE_TX))
-    { 
-      /* Enable I2Sext RXNE and ERR interrupts */
-      I2SxEXT(hi2s->Instance)->CR2 |= (I2S_IT_RXNE | I2S_IT_ERR);
-
-      /* Enable I2Sx TXE and ERR interrupts */
-      __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
-      /* Check if the I2S is already enabled */ 
-      if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
-      {
-        /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
-        I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
-
-        /* Enable I2Sx peripheral */
-        __HAL_I2S_ENABLE(hi2s);
-      }
-    }
-    /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
-    else
-    {
-      /* Enable I2Sext TXE and ERR interrupts */
-      I2SxEXT(hi2s->Instance)->CR2 |= (I2S_IT_TXE |I2S_IT_ERR);
-
-      /* Enable I2Sext RXNE and ERR interrupts */
-      __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
-      /* Check if the I2S is already enabled */ 
-      if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
-      {
-        /* Check if the I2S_MODE_MASTER_RX is selected */
-        if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX) 
-        {
-          /* Prepare the First Data before enabling the I2S */
-          if(hi2s->TxXferCount != 0U)
-          {
-            /* Transmit First data */
-            I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
-            hi2s->TxXferCount--;	
-
-            if(hi2s->TxXferCount == 0U)
-            {
-              /* Disable I2Sext TXE interrupt */
-              I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_TXE;
-            }
-          }
-        }
-        /* Enable I2S peripheral */
-        __HAL_I2S_ENABLE(hi2s);
-        
-        /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
-        I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
-      }
-    }
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2s);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Full-Duplex Transmit/Receive data in non-blocking mode using DMA  
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @param pTxData: a 16-bit pointer to the Transmit data buffer.
-  * @param pRxData: a 16-bit pointer to the Receive data buffer.
-  * @param Size: number of data sample to be sent:
-  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
-  *       configuration phase, the Size parameter means the number of 16-bit data length 
-  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
-  *       the Size parameter means the number of 16-bit data length. 
-  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 
-  *       between Master and Slave(example: audio streaming).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
-{
-  uint32_t *tmp;
-  uint32_t tmp1 = 0U;
-    
-  if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U)) 
-  {
-    return  HAL_ERROR;
-  }
-
-  if(hi2s->State == HAL_I2S_STATE_READY)
-  {
-    hi2s->pTxBuffPtr = pTxData;
-    hi2s->pRxBuffPtr = pRxData;
-
-    tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
-    /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended 
-       is selected during the I2S configuration phase, the Size parameter means the number
-       of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data 
-       frame is selected the Size parameter means the number of 16-bit data length. */
-    if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
-    {
-      hi2s->TxXferSize = Size*2U;
-      hi2s->TxXferCount = Size*2U;
-      hi2s->RxXferSize = Size*2U;
-      hi2s->RxXferCount = Size*2U;
-    }
-    else
-    {
-      hi2s->TxXferSize = Size;
-      hi2s->TxXferCount = Size;
-      hi2s->RxXferSize = Size;
-      hi2s->RxXferCount = Size;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2s);
-
-    hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
-    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-
-    /* Set the I2S Rx DMA Half transfer complete callback */
-    hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
-
-    /* Set the I2S Rx DMA transfer complete callback */
-    hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
-
-    /* Set the I2S Rx DMA error callback */
-    hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
-
-    /* Set the I2S Tx DMA Half transfer complete callback */
-    hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
-
-    /* Set the I2S Tx DMA transfer complete callback */
-    hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
-
-    /* Set the I2S Tx DMA error callback */
-    hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
-
-    tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
-    /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
-    if((tmp1 == I2S_MODE_MASTER_TX) || (tmp1 == I2S_MODE_SLAVE_TX))
-    {
-      /* Enable the Rx DMA Stream */
-      tmp = (uint32_t*)&pRxData;
-      HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
-
-      /* Enable Rx DMA Request */  
-      I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_RXDMAEN;
-
-      /* Enable the Tx DMA Stream */
-      tmp = (uint32_t*)&pTxData;
-      HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
-
-      /* Enable Tx DMA Request */  
-      hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
-
-      /* Check if the I2S is already enabled */ 
-      if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
-      {
-        /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
-        I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
-
-        /* Enable I2S peripheral after the I2Sext */
-        __HAL_I2S_ENABLE(hi2s);
-      }
-    }
-    else
-    {
-      /* Enable the Tx DMA Stream */
-      tmp = (uint32_t*)&pTxData;
-      HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, hi2s->TxXferSize);
-
-      /* Enable Tx DMA Request */  
-      I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_TXDMAEN;
-
-      /* Enable the Rx DMA Stream */
-      tmp = (uint32_t*)&pRxData;
-      HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
-
-      /* Enable Rx DMA Request */  
-      hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
-
-      /* Check if the I2S is already enabled */ 
-      if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
-      {
-        /* Enable I2S peripheral before the I2Sext */
-        __HAL_I2S_ENABLE(hi2s);
-
-        /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
-        I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
-      }
-      else
-      {
-        /* Check if Master Receiver mode is selected */
-        if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
-        {
-          /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
-          access to the SPI_SR register. */ 
-          __HAL_I2S_CLEAR_OVRFLAG(hi2s);
-        }
-      }
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2s);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Pauses the audio stream playing from the Media.
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
-{
-  /* Process Locked */
-  __HAL_LOCK(hi2s);
-  
-  if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
-  {
-    /* Disable the I2S DMA Tx request */
-    hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
-  }
-  else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
-  {
-    /* Disable the I2S DMA Rx request */
-    hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
-  }
-  else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
-  {
-    if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
-    {
-      /* Disable the I2S DMA Tx request */
-      hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
-      /* Disable the I2SEx Rx DMA Request */
-      I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
-    }
-    else
-    {
-      /* Disable the I2S DMA Rx request */
-      hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
-      /* Disable the I2SEx Tx DMA Request */
-      I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);      
-    }
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hi2s);
-  
-  return HAL_OK; 
-}
-
-/**
-  * @brief Resumes the audio stream playing from the Media.
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
-{
-  /* Process Locked */
-  __HAL_LOCK(hi2s);
-  
-  if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
-  {
-    /* Enable the I2S DMA Tx request */
-    hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
-  }
-  else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
-  {
-    /* Enable the I2S DMA Rx request */
-    hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
-  }
-  else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
-  {
-    if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
-    {
-      /* Enable the I2S DMA Tx request */
-      hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
-      /* Disable the I2SEx Rx DMA Request */  
-      I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_RXDMAEN;
-    }
-    else
-    {
-      /* Enable the I2S DMA Rx request */
-      hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
-      /* Enable the I2SEx Tx DMA Request */  
-      I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_TXDMAEN;
-    }
-  }
-
-  /* If the I2S peripheral is still not enabled, enable it */
-  if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U)
-  {
-    /* Enable I2S peripheral */    
-    __HAL_I2S_ENABLE(hi2s);
-  }
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hi2s);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief Resumes the audio stream playing from the Media.
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
-{
-  /* Process Locked */
-  __HAL_LOCK(hi2s);
-  
-  /* Disable the I2S Tx/Rx DMA requests */
-  hi2s->Instance->CR2 &= ~SPI_CR2_TXDMAEN;
-  hi2s->Instance->CR2 &= ~SPI_CR2_RXDMAEN;
-  
-  if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
-  {
-    /* Disable the I2S extended Tx/Rx DMA requests */  
-    I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
-    I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
-  }
-  
-  /* Abort the I2S DMA Stream tx */
-  if(hi2s->hdmatx != NULL)
-  {
-    HAL_DMA_Abort(hi2s->hdmatx);
-  }
-  /* Abort the I2S DMA Stream rx */
-  if(hi2s->hdmarx != NULL)
-  {
-    HAL_DMA_Abort(hi2s->hdmarx);
-  }
-
-  /* Disable I2S peripheral */
-  __HAL_I2S_DISABLE(hi2s);
- 
-  if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
-  {
-    /* Disable the I2Sext peripheral */
-    I2SxEXT(hi2s->Instance)->I2SCFGR &= ~SPI_I2SCFGR_I2SE;
-  }
-  hi2s->State = HAL_I2S_STATE_READY;
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hi2s);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles I2S interrupt request.
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
-void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
-{  
-  uint32_t tmp1 = 0U, tmp2 = 0U;
-  __IO uint32_t tmpreg1 = 0U;    
-  if(hi2s->Init.FullDuplexMode != I2S_FULLDUPLEXMODE_ENABLE)
-  {
-    if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
-    {
-      tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE);
-      tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE);
-      /* I2S in mode Receiver ------------------------------------------------*/
-      if((tmp1 != RESET) && (tmp2 != RESET))
-      {
-        I2S_Receive_IT(hi2s);
-      }
-
-      tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR);
-      tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
-      /* I2S Overrun error interrupt occurred ---------------------------------*/
-      if((tmp1 != RESET) && (tmp2 != RESET))
-      {
-        __HAL_I2S_CLEAR_OVRFLAG(hi2s);
-        hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
-      }
-    }
-
-    if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
-    {
-      tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE);
-      tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE);
-      /* I2S in mode Tramitter -----------------------------------------------*/
-      if((tmp1 != RESET) && (tmp2 != RESET))
-      {
-        I2S_Transmit_IT(hi2s);
-      } 
-
-      tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR);
-      tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
-      /* I2S Underrun error interrupt occurred --------------------------------*/
-      if((tmp1 != RESET) && (tmp2 != RESET))
-      {
-        __HAL_I2S_CLEAR_UDRFLAG(hi2s);
-        hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
-      }
-    }
-  }
-  else
-  {
-    tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
-    /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
-    if((tmp1 == I2S_MODE_MASTER_TX) || (tmp1 == I2S_MODE_SLAVE_TX))
-    { 
-      tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_RXNE; 
-      tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_RXNE;  
-      /* I2Sext in mode Receiver ---------------------------------------------*/
-      if((tmp1 == SPI_SR_RXNE) && (tmp2 == I2S_IT_RXNE))
-      {
-        /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
-        the I2Sext RXNE interrupt will be generated to manage the full-duplex receive phase. */
-        I2SEx_TransmitReceive_IT(hi2s);
-      }
-
-      tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_OVR;
-      tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_ERR;
-      /* I2Sext Overrun error interrupt occurred -----------------------------*/
-      if((tmp1 == SPI_SR_OVR) && (tmp2 == I2S_IT_ERR))
-      {
-        /* Clear I2Sext OVR Flag */ 
-        tmpreg1 = I2SxEXT(hi2s->Instance)->DR;
-        tmpreg1 = I2SxEXT(hi2s->Instance)->SR;
-        hi2s->ErrorCode |= HAL_I2SEX_ERROR_OVR;
-        UNUSED(tmpreg1);
-      }
-
-      tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE);
-      tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE);
-      /* I2S in mode Tramitter -----------------------------------------------*/
-      if((tmp1 != RESET) && (tmp2 != RESET))
-      {
-        /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
-        the I2S TXE interrupt will be generated to manage the full-duplex transmit phase. */
-        I2SEx_TransmitReceive_IT(hi2s);
-      }
-
-      tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR);
-      tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
-      /* I2S Underrun error interrupt occurred -------------------------------*/
-      if((tmp1 != RESET) && (tmp2 != RESET))
-      {
-        __HAL_I2S_CLEAR_UDRFLAG(hi2s);
-        hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
-      }
-    }
-    /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
-    else
-    {
-      tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE);
-      tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE);
-      /* I2S in mode Receiver ------------------------------------------------*/
-      if((tmp1 != RESET) && (tmp2 != RESET))
-      {
-        /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
-        the I2S RXNE interrupt will be generated to manage the full-duplex receive phase. */
-        I2SEx_TransmitReceive_IT(hi2s);
-      }
-
-      tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR);
-      tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
-      /* I2S Overrun error interrupt occurred --------------------------------*/
-      if((tmp1 != RESET) && (tmp2 != RESET))
-      {
-        __HAL_I2S_CLEAR_OVRFLAG(hi2s);
-        hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
-      }
-
-      tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_TXE;
-      tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_TXE; 
-      /* I2Sext in mode Tramitter --------------------------------------------*/
-      if((tmp1 == SPI_SR_TXE) && (tmp2 == I2S_IT_TXE))
-      {
-        /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
-        the I2Sext TXE interrupt will be generated to manage the full-duplex transmit phase. */
-        I2SEx_TransmitReceive_IT(hi2s);
-      }
-
-      tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_UDR;
-      tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_ERR;
-      /* I2Sext Underrun error interrupt occurred ----------------------------*/
-      if((tmp1 == SPI_SR_UDR) && (tmp2 == I2S_IT_ERR))
-      {
-        /* Clear I2Sext UDR Flag */ 
-        tmpreg1 = I2SxEXT(hi2s->Instance)->SR;
-        hi2s->ErrorCode |= HAL_I2SEX_ERROR_UDR;
-        UNUSED(tmpreg1);
-      }
-    }
-  }
-
-  /* Call the Error call Back in case of Errors */
-  if(hi2s->ErrorCode != HAL_I2S_ERROR_NONE)
-  {
-    /* Set the I2S state ready to be able to start again the process */
-    hi2s->State= HAL_I2S_STATE_READY;
-    HAL_I2S_ErrorCallback(hi2s);
-  }
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt 
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s)
-{
-  uint32_t tmp1 = 0U, tmp2 = 0U;
-  
-  if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hi2s);
-
-    tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
-    /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
-    if((tmp1 == I2S_MODE_MASTER_TX) || (tmp1 == I2S_MODE_SLAVE_TX))
-    {
-      if(hi2s->TxXferCount != 0U)
-      {
-        if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE) != RESET)
-        {        
-          /* Transmit data */
-          hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
-          hi2s->TxXferCount--;
-
-          if(hi2s->TxXferCount == 0U)
-          {
-            /* Disable TXE interrupt */
-            __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_TXE);
-          }
-        }
-      }
-
-      if(hi2s->RxXferCount != 0U)
-      {
-        if((I2SxEXT(hi2s->Instance)->SR & SPI_SR_RXNE) == SPI_SR_RXNE)
-        {
-          /* Receive data */
-          (*hi2s->pRxBuffPtr++) = I2SxEXT(hi2s->Instance)->DR;
-          hi2s->RxXferCount--;
-
-          if(hi2s->RxXferCount == 0U)
-          {
-            /* Disable I2Sext RXNE interrupt */
-            I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_RXNE;
-          }
-        }
-      }
-    }
-    /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */ 
-    else
-    {
-      if(hi2s->TxXferCount != 0U)
-      {
-        if((I2SxEXT(hi2s->Instance)->SR & SPI_SR_TXE) == SPI_SR_TXE)
-        {        
-          /* Transmit data */
-          I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
-          hi2s->TxXferCount--;
-
-          if(hi2s->TxXferCount == 0U)
-          {
-            /* Disable I2Sext TXE interrupt */
-            I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_TXE;
-
-            HAL_I2S_TxCpltCallback(hi2s);
-          }
-        }
-      }
-      if(hi2s->RxXferCount != 0U)
-      {
-        if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE) != RESET)
-        {
-          /* Receive data */
-          (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
-          hi2s->RxXferCount--;
-
-          if(hi2s->RxXferCount == 0U)
-          {
-            /* Disable RXNE interrupt */
-            __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_RXNE);
-
-            HAL_I2S_RxCpltCallback(hi2s);
-          }
-        }
-      }
-    }
-
-    tmp1 = hi2s->RxXferCount;
-    tmp2 = hi2s->TxXferCount;
-    if((tmp1 == 0U) && (tmp2 == 0U))
-    {
-      /* Disable I2Sx ERR interrupt */
-      __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_ERR);
-      /* Disable I2Sext ERR interrupt */
-      I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_ERR;
-      
-      hi2s->State = HAL_I2S_STATE_READY; 
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2s);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY; 
-  }
-}
-#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F401xx ||\
-          STM32F411xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || \
-          STM32F412Rx || STM32F412Cx */
-/**
-  * @brief DMA I2S transmit process complete callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
-{
-  I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-  
-  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
-  {
-    if(hi2s->Init.FullDuplexMode != I2S_FULLDUPLEXMODE_ENABLE)
-    {    
-       hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
-    }
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) ||\
-    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
-    defined(STM32F412Cx)
-    
-    /* FullDuplexMode feature enabled */   
-    else
-    {
-      if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
-      {
-        /* Disable Tx DMA Request for the I2S Master*/  
-        hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
-      }
-      else
-      {
-        /* Disable Tx DMA Request for the I2SEx Slave */  
-        I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
-      }
-    }
-#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F401xx || STM32F411xx ||\
-          STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-    hi2s->TxXferCount = 0U;
-    if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
-    {
-      if(hi2s->RxXferCount == 0U)
-      {
-        hi2s->State = HAL_I2S_STATE_READY;
-      }
-    }
-    else
-    {
-      hi2s->State = HAL_I2S_STATE_READY; 
-    }
-  }
-  HAL_I2S_TxCpltCallback(hi2s);
-}
-
-/**
-  * @brief DMA I2S receive process complete callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
-{
-  I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-  
-  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
-  {
-    if(hi2s->Init.FullDuplexMode != I2S_FULLDUPLEXMODE_ENABLE)
-    {    
-       hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
-    }
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) ||\
-    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
-    defined(STM32F412Cx)
-   /* FullDuplexMode feature enabled */   
-    else
-    {
-      if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
-      {
-        /* Disable Rx DMA Request for the I2SEx Slave */  
-        I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
-      }
-      else
-      {
-        /* Disable Rx DMA Request for the I2S Master*/  
-        hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
-      }
-    }
-#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F401xx || STM32F411xx ||\
-          STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-    hi2s->RxXferCount = 0U;
-    if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
-    {
-      if(hi2s->TxXferCount == 0U)
-      {
-        hi2s->State = HAL_I2S_STATE_READY;
-      }
-    }
-    else
-    {
-      hi2s->State = HAL_I2S_STATE_READY; 
-    }
-  }
-  HAL_I2S_RxCpltCallback(hi2s); 
-}
-
-/**
-  * @brief  Get I2S clock Input based on Source clock selection in RCC
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval I2S Clock Input
-  */
-uint32_t I2S_GetInputClock(I2S_HandleTypeDef *hi2s)
-{
-  /* This variable used to store the VCO Input (value in Hz) */
-  uint32_t vcoinput = 0U;
-  /* This variable used to store the VCO Output (value in Hz) */
-  uint32_t vcooutput = 0U;
-  /* This variable used to store the I2S_CK_x (value in Hz) */
-  uint32_t i2ssourceclock = 0U;
-
-  /* Configure 12S Clock based on I2S source clock selection */ 
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
-    defined(STM32F412Rx) || defined(STM32F412Cx)
-  switch(hi2s->Init.ClockSource)
-  {
-    case I2S_CLOCK_EXTERNAL :
-    {
-      /* Set the I2S clock to the external clock  value */
-      i2ssourceclock = EXTERNAL_CLOCK_VALUE;
-      break;
-    }
-#if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
-    case I2S_CLOCK_PLL :
-    { 
-      /* Configure the PLLI2S division factor */
-      /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */
-      if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
-      {
-        /* Get the I2S source clock value */
-        vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
-      }
-      else
-      {
-        /* Get the I2S source clock value */
-        vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
-      }
-      
-      /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
-      vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
-      /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
-      i2ssourceclock = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
-      break;
-    }
-#endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-    case I2S_CLOCK_PLLR :
-    { 
-      /* Configure the PLLI2S division factor */
-      /* PLL_VCO Input  = PLL_SOURCE/PLLM */
-      if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
-      {
-        /* Get the I2S source clock value */
-        vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
-      }
-      else
-      {
-        /* Get the I2S source clock value */
-        vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
-      }
-      
-      /* PLL_VCO Output = PLL_VCO Input * PLLN */
-      vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
-      /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
-      i2ssourceclock = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
-      break;
-    }
-    case I2S_CLOCK_PLLSRC :
-    { 
-      /* Configure the PLLI2S division factor */
-      /* PLL_VCO Input  = PLL_SOURCE/PLLM */
-      if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
-      {
-        /* Get the I2S source clock value */
-        i2ssourceclock = (uint32_t)(HSE_VALUE);
-      }
-      else
-      {
-        /* Get the I2S source clock value */
-        i2ssourceclock = (uint32_t)(HSI_VALUE);
-      }
-      break;
-    }
-    default :
-    {
-      break;
-    }
-  }
-#endif /* STM32F410xx || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
-    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F469xx) || defined(STM32F479xx)
-      
-  /* If an external I2S clock has to be used, the specific define should be set  
-  in the project configuration or in the stm32f4xx_conf.h file */
-  if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL)
-  {
-    /* Set the I2S clock to the external clock  value */
-    i2ssourceclock = EXTERNAL_CLOCK_VALUE;
-  }
-  else
-  { 
-    /* Configure the PLLI2S division factor */
-    /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */
-    if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
-    {
-      /* Get the I2S source clock value */
-      vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
-    }
-    else
-    {
-      /* Get the I2S source clock value */
-      vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
-    }
-    
-    /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
-    vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
-    /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
-    i2ssourceclock = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
-  }
-#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F411xE)
-      
-  /* If an external I2S clock has to be used, the specific define should be set  
-  in the project configuration or in the stm32f4xx_conf.h file */
-  if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL)
-  {
-    /* Set the I2S clock to the external clock  value */
-    i2ssourceclock = EXTERNAL_CLOCK_VALUE;
-  }
-  else
-  { 
-    /* Configure the PLLI2S division factor */
-    /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */
-    if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
-    {
-      /* Get the I2S source clock value */
-      vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
-    }
-    else
-    {
-      /* Get the I2S source clock value */
-      vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
-    }
-    
-    /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
-    vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
-    /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
-    i2ssourceclock = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
-  }
-#endif /* STM32F411xE */
-
-  /* the return result is the value of I2S clock */
-  return i2ssourceclock; 
-}
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */  
-  
-#endif /* HAL_I2S_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_pcd.c b/stmhal/hal/f4/src/stm32f4xx_hal_pcd.c
deleted file mode 100644
index b867ff92a0..0000000000
--- a/stmhal/hal/f4/src/stm32f4xx_hal_pcd.c
+++ /dev/null
@@ -1,1332 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_pcd.c
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   PCD HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the USB Peripheral Controller:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions 
-  *           + Peripheral State functions
-  *         
-  @verbatim
-  ==============================================================================
-                    ##### How to use this driver #####
-  ==============================================================================
-    [..]
-      The PCD HAL driver can be used as follows:
-
-     (#) Declare a PCD_HandleTypeDef handle structure, for example:
-         PCD_HandleTypeDef  hpcd;
-        
-     (#) Fill parameters of Init structure in HCD handle
-  
-     (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...) 
-
-     (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
-         (##) Enable the PCD/USB Low Level interface clock using 
-              (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
-              (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)
-           
-         (##) Initialize the related GPIO clocks
-         (##) Configure PCD pin-out
-         (##) Configure PCD NVIC interrupt
-    
-     (#)Associate the Upper USB device stack to the HAL PCD Driver:
-         (##) hpcd.pData = pdev;
-
-     (#)Enable PCD transmission and reception:
-         (##) HAL_PCD_Start();
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup PCD PCD
-  * @brief PCD HAL module driver
-  * @{
-  */
-
-#ifdef HAL_PCD_MODULE_ENABLED
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
-    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
-    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
-    defined(STM32F412Rx) || defined(STM32F412Cx)
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup PCD_Private_Macros PCD Private Macros
-  * @{
-  */ 
-#define PCD_MIN(a, b)  (((a) < (b)) ? (a) : (b))
-#define PCD_MAX(a, b)  (((a) > (b)) ? (a) : (b))
-/**
-  * @}
-  */
-
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup PCD_Private_Functions PCD Private Functions
-  * @{
-  */
-static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup PCD_Exported_Functions PCD Exported Functions
-  * @{
-  */
-
-/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions 
- *
-@verbatim 
- ===============================================================================
-            ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
- 
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the PCD according to the specified
-  *         parameters in the PCD_InitTypeDef and initialize the associated handle.
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
-{ 
-  uint32_t i = 0U;
-  
-  /* Check the PCD handle allocation */
-  if(hpcd == NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  /* Check the parameters */
-  assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
-
-  hpcd->State = HAL_PCD_STATE_BUSY;
-  
-  /* Init the low level hardware : GPIO, CLOCK, NVIC... */
-  HAL_PCD_MspInit(hpcd);
-
-  /* Disable the Interrupts */
- __HAL_PCD_DISABLE(hpcd);
- 
- /*Init the Core (common init.) */
- USB_CoreInit(hpcd->Instance, hpcd->Init);
- 
- /* Force Device Mode*/
- USB_SetCurrentMode(hpcd->Instance , USB_OTG_DEVICE_MODE);
- 
- /* Init endpoints structures */
- for (i = 0U; i < 15U; i++)
- {
-   /* Init ep structure */
-   hpcd->IN_ep[i].is_in = 1U;
-   hpcd->IN_ep[i].num = i;
-   hpcd->IN_ep[i].tx_fifo_num = i;
-   /* Control until ep is activated */
-   hpcd->IN_ep[i].type = EP_TYPE_CTRL;
-   hpcd->IN_ep[i].maxpacket = 0U;
-   hpcd->IN_ep[i].xfer_buff = 0U;
-   hpcd->IN_ep[i].xfer_len = 0U;
- }
- 
- for (i = 0U; i < 15U; i++)
- {
-   hpcd->OUT_ep[i].is_in = 0U;
-   hpcd->OUT_ep[i].num = i;
-   hpcd->IN_ep[i].tx_fifo_num = i;
-   /* Control until ep is activated */
-   hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
-   hpcd->OUT_ep[i].maxpacket = 0U;
-   hpcd->OUT_ep[i].xfer_buff = 0U;
-   hpcd->OUT_ep[i].xfer_len = 0U;
-   
-   hpcd->Instance->DIEPTXF[i] = 0U;
- }
- 
- /* Init Device */
- USB_DevInit(hpcd->Instance, hpcd->Init);
- 
- hpcd->State= HAL_PCD_STATE_READY;
- 
-#ifdef USB_OTG_GLPMCFG_LPMEN
- /* Activate LPM */
- if (hpcd->Init.lpm_enable == 1U)
- {
-   HAL_PCDEx_ActivateLPM(hpcd);
- }
-#endif /* USB_OTG_GLPMCFG_LPMEN */
- 
-#ifdef USB_OTG_GCCFG_BCDEN
- /* Activate Battery charging */
- if (hpcd->Init.battery_charging_enable == 1U)
- {
-   HAL_PCDEx_ActivateBCD(hpcd);
- }
-#endif /* USB_OTG_GCCFG_BCDEN */
- 
- USB_DevDisconnect (hpcd->Instance);  
- return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the PCD peripheral. 
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
-{
-  /* Check the PCD handle allocation */
-  if(hpcd == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  hpcd->State = HAL_PCD_STATE_BUSY;
-  
-  /* Stop Device */
-  HAL_PCD_Stop(hpcd);
-    
-  /* DeInit the low level hardware */
-  HAL_PCD_MspDeInit(hpcd);
-  
-  hpcd->State = HAL_PCD_STATE_RESET; 
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the PCD MSP.
-  * @param  hpcd: PCD handle
-  * @retval None
-  */
-__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCD_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes PCD MSP.
-  * @param  hpcd: PCD handle
-  * @retval None
-  */
-__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCD_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions 
- *  @brief   Data transfers functions 
- *
-@verbatim 
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================  
-    [..]
-    This subsection provides a set of functions allowing to manage the PCD data 
-    transfers.
-
-@endverbatim
-  * @{
-  */
-  
-/**
-  * @brief  Start The USB OTG Device.
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
-{ 
-  __HAL_LOCK(hpcd); 
-  USB_DevConnect (hpcd->Instance);  
-  __HAL_PCD_ENABLE(hpcd);
-  __HAL_UNLOCK(hpcd); 
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stop The USB OTG Device.
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
-{ 
-  __HAL_LOCK(hpcd); 
-  __HAL_PCD_DISABLE(hpcd);
-  USB_StopDevice(hpcd->Instance);
-  USB_DevDisconnect(hpcd->Instance);
-  __HAL_UNLOCK(hpcd); 
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handles PCD interrupt request.
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
-{
-  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
-  uint32_t i = 0U, ep_intr = 0U, epint = 0U, epnum = 0U;
-  uint32_t fifoemptymsk = 0U, temp = 0U;
-  USB_OTG_EPTypeDef *ep;
-  uint32_t hclk = 180000000;
-  
-  /* ensure that we are in device mode */
-  if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
-  {    
-    /* avoid spurious interrupt */
-    if(__HAL_PCD_IS_INVALID_INTERRUPT(hpcd)) 
-    {
-      return;
-    }
-    
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))
-    {
-     /* incorrect mode, acknowledge the interrupt */
-      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);
-    }
-    
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
-    {
-      epnum = 0U;
-      
-      /* Read in the device interrupt bits */
-      ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance);
-      
-      while ( ep_intr )
-      {
-        if (ep_intr & 0x1U)
-        {
-          epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, epnum);
-          
-          if(( epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)
-          {
-            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC);
-            
-            if(hpcd->Init.dma_enable == 1U)
-            {
-              hpcd->OUT_ep[epnum].xfer_count = hpcd->OUT_ep[epnum].maxpacket- (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); 
-              hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket;            
-            }
-            
-            HAL_PCD_DataOutStageCallback(hpcd, epnum);
-            if(hpcd->Init.dma_enable == 1U)
-            {
-              if((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U))
-              {
-                 /* this is ZLP, so prepare EP0 for next setup */
-                USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
-              }              
-            }
-          }
-          
-          if(( epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
-          {
-            /* Inform the upper layer that a setup packet is available */
-            HAL_PCD_SetupStageCallback(hpcd);
-            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
-          }
-          
-          if(( epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)
-          {
-            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);
-          }
-
-#ifdef USB_OTG_DOEPINT_OTEPSPR 
-          /* Clear Status Phase Received interrupt */
-          if(( epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
-          {
-            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
-          }
-#endif /* USB_OTG_DOEPINT_OTEPSPR */
-        }
-        epnum++;
-        ep_intr >>= 1U;
-      }
-    }
-    
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))
-    {
-      /* Read in the device interrupt bits */
-      ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance);
-      
-      epnum = 0U;
-      
-      while ( ep_intr )
-      {
-        if (ep_intr & 0x1U) /* In ITR */
-        {
-          epint = USB_ReadDevInEPInterrupt(hpcd->Instance, epnum);
-
-           if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)
-          {
-            fifoemptymsk = 0x1U << epnum;
-            USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
-            
-            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);
-            
-            if (hpcd->Init.dma_enable == 1U)
-            {
-              hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket; 
-            }
-                                      
-            HAL_PCD_DataInStageCallback(hpcd, epnum);
-
-            if (hpcd->Init.dma_enable == 1U)
-            {
-              /* this is ZLP, so prepare EP0 for next setup */
-              if((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U))
-              {
-                /* prepare to rx more setup packets */
-                USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
-              }
-            }           
-          }
-           if(( epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)
-          {
-            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC);
-          }
-          if(( epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE)
-          {
-            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE);
-          }
-          if(( epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE)
-          {
-            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE);
-          }
-          if(( epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)
-          {
-            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);
-          }       
-          if(( epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)
-          {
-            PCD_WriteEmptyTxFifo(hpcd , epnum);
-          }
-        }
-        epnum++;
-        ep_intr >>= 1U;
-      }
-    }
-    
-    /* Handle Resume Interrupt */
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))
-    {    
-      /* Clear the Remote Wake-up Signaling */
-      USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
-
-#ifdef USB_OTG_GLPMCFG_LPMEN
-      if(hpcd->LPM_State == LPM_L1)
-      {
-        hpcd->LPM_State = LPM_L0;
-        HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);
-      }
-      else
-#endif /* USB_OTG_GLPMCFG_LPMEN */
-      {
-        HAL_PCD_ResumeCallback(hpcd);
-      }
-      
-      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);
-    }
-    
-    /* Handle Suspend Interrupt */
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
-    {
-      if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
-      {
-        
-        HAL_PCD_SuspendCallback(hpcd);
-      }
-      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
-    }
-
-#ifdef USB_OTG_GLPMCFG_LPMEN
-    /* Handle LPM Interrupt */ 
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT))
-    {
-      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT);      
-      if( hpcd->LPM_State == LPM_L0)
-      {
-        hpcd->LPM_State = LPM_L1;
-        hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >>2 ;
-        HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
-      }
-      else
-      {
-        HAL_PCD_SuspendCallback(hpcd);
-      }
-    }
-#endif /* USB_OTG_GLPMCFG_LPMEN */
-
-    /* Handle Reset Interrupt */
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
-    {
-      USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; 
-      USB_FlushTxFifo(hpcd->Instance , 0U);
-      
-      for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
-      {
-        USBx_INEP(i)->DIEPINT = 0xFFU;
-        USBx_OUTEP(i)->DOEPINT = 0xFFU;
-      }
-      USBx_DEVICE->DAINT = 0xFFFFFFFFU;
-      USBx_DEVICE->DAINTMSK |= 0x10001U;
-      
-      if(hpcd->Init.use_dedicated_ep1)
-      {
-        USBx_DEVICE->DOUTEP1MSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM); 
-        USBx_DEVICE->DINEP1MSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);  
-      }
-      else
-      {
-#ifdef USB_OTG_DOEPINT_OTEPSPR
-        USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM | USB_OTG_DOEPMSK_OTEPSPRM);
-#else
-        USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM);
-#endif /* USB_OTG_DOEPINT_OTEPSPR */
-        USBx_DEVICE->DIEPMSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);
-      }
-      
-      /* Set Default Address to 0 */
-      USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD;
-      
-      /* setup EP0 to receive SETUP packets */
-      USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
-        
-      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);
-    }
-    
-    /* Handle Enumeration done Interrupt */
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))
-    {
-      USB_ActivateSetup(hpcd->Instance);
-      hpcd->Instance->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
-      
-      if ( USB_GetDevSpeed(hpcd->Instance) == USB_OTG_SPEED_HIGH)
-      {
-        hpcd->Init.speed            = USB_OTG_SPEED_HIGH;
-        hpcd->Init.ep0_mps          = USB_OTG_HS_MAX_PACKET_SIZE ;    
-        hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_HS_TRDT_VALUE << 10U) & USB_OTG_GUSBCFG_TRDT);
-      }
-      else
-      {
-        hpcd->Init.speed            = USB_OTG_SPEED_FULL;
-        hpcd->Init.ep0_mps          = USB_OTG_FS_MAX_PACKET_SIZE ;  
-        
-        /* The USBTRD is configured according to the tables below, depending on AHB frequency 
-        used by application. In the low AHB frequency range it is used to stretch enough the USB response 
-        time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access 
-        latency to the Data FIFO */
-        
-        /* Get hclk frequency value */
-        hclk = HAL_RCC_GetHCLKFreq();
-		
-        if((hclk >= 14200000)&&(hclk < 15000000))
-        {
-          /* hclk Clock Range between 14.2-15 MHz */
-          hpcd->Instance->GUSBCFG |= (uint32_t)((0xF << 10) & USB_OTG_GUSBCFG_TRDT);
-        }
-        
-        else if((hclk >= 15000000)&&(hclk < 16000000))
-        {
-          /* hclk Clock Range between 15-16 MHz */
-          hpcd->Instance->GUSBCFG |= (uint32_t)((0xE << 10) & USB_OTG_GUSBCFG_TRDT);
-        }
-        
-        else if((hclk >= 16000000)&&(hclk < 17200000))
-        {
-          /* hclk Clock Range between 16-17.2 MHz */
-          hpcd->Instance->GUSBCFG |= (uint32_t)((0xD << 10) & USB_OTG_GUSBCFG_TRDT);
-        }
-        
-        else if((hclk >= 17200000)&&(hclk < 18500000))
-        {
-          /* hclk Clock Range between 17.2-18.5 MHz */
-          hpcd->Instance->GUSBCFG |= (uint32_t)((0xC << 10) & USB_OTG_GUSBCFG_TRDT);
-        }
-        
-        else if((hclk >= 18500000)&&(hclk < 20000000))
-        {
-          /* hclk Clock Range between 18.5-20 MHz */
-          hpcd->Instance->GUSBCFG |= (uint32_t)((0xB << 10) & USB_OTG_GUSBCFG_TRDT);
-        }
-        
-        else if((hclk >= 20000000)&&(hclk < 21800000))
-        {
-          /* hclk Clock Range between 20-21.8 MHz */
-          hpcd->Instance->GUSBCFG |= (uint32_t)((0xA << 10) & USB_OTG_GUSBCFG_TRDT);
-        }
-        
-        else if((hclk >= 21800000)&&(hclk < 24000000))
-        {
-          /* hclk Clock Range between 21.8-24 MHz */
-          hpcd->Instance->GUSBCFG |= (uint32_t)((0x9 << 10) & USB_OTG_GUSBCFG_TRDT);
-        }
-        
-        else if((hclk >= 24000000)&&(hclk < 27700000))
-        {
-          /* hclk Clock Range between 24-27.7 MHz */
-          hpcd->Instance->GUSBCFG |= (uint32_t)((0x8 << 10) & USB_OTG_GUSBCFG_TRDT);
-        }
-        
-        else if((hclk >= 27700000)&&(hclk < 32000000))
-        {
-          /* hclk Clock Range between 27.7-32 MHz */
-          hpcd->Instance->GUSBCFG |= (uint32_t)((0x7 << 10) & USB_OTG_GUSBCFG_TRDT);
-        }
-        
-        else /* if(hclk >= 32000000) */
-        {
-          /* hclk Clock Range between 32-180 MHz */
-          hpcd->Instance->GUSBCFG |= (uint32_t)((0x6 << 10) & USB_OTG_GUSBCFG_TRDT);
-        }  
-      }
-      
-      HAL_PCD_ResetCallback(hpcd);
-      
-      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
-    }
-
-    /* Handle RxQLevel Interrupt */
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
-    {
-      USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
-      
-      temp = USBx->GRXSTSP;
-      
-      ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];
-      
-      if(((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17U) ==  STS_DATA_UPDT)
-      {
-        if((temp & USB_OTG_GRXSTSP_BCNT) != 0U)
-        {
-          USB_ReadPacket(USBx, ep->xfer_buff, (temp & USB_OTG_GRXSTSP_BCNT) >> 4U);
-          ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4U;
-          ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4U;
-        }
-      }
-      else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17U) ==  STS_SETUP_UPDT)
-      {
-        USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U);
-        ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4U;
-      }
-      USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
-    }
-    
-    /* Handle SOF Interrupt */
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
-    {
-      HAL_PCD_SOFCallback(hpcd);
-      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);
-    }
-    
-    /* Handle Incomplete ISO IN Interrupt */
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
-    {
-      HAL_PCD_ISOINIncompleteCallback(hpcd, epnum);
-      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);
-    } 
-    
-    /* Handle Incomplete ISO OUT Interrupt */
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
-    {
-      HAL_PCD_ISOOUTIncompleteCallback(hpcd, epnum);
-      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
-    } 
-    
-    /* Handle Connection event Interrupt */
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))
-    {
-      HAL_PCD_ConnectCallback(hpcd);
-      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT);
-    } 
-    
-    /* Handle Disconnection event Interrupt */
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))
-    {
-      temp = hpcd->Instance->GOTGINT;
-      
-      if((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)
-      {
-        HAL_PCD_DisconnectCallback(hpcd);
-      }
-      hpcd->Instance->GOTGINT |= temp;
-    }
-  }
-}
-
-/**
-  * @brief  Data OUT stage callback.
-  * @param  hpcd: PCD handle
-  * @param  epnum: endpoint number  
-  * @retval None
-  */
- __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-  UNUSED(epnum);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCD_DataOutStageCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  Data IN stage callback.
-  * @param  hpcd: PCD handle
-  * @param  epnum: endpoint number
-  * @retval None
-  */
- __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-  UNUSED(epnum);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCD_DataInStageCallback could be implemented in the user file
-   */ 
-}
-/**
-  * @brief  Setup stage callback.
-  * @param  hpcd: PCD handle
-  * @retval None
-  */
- __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCD_SetupStageCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  USB Start Of Frame callback.
-  * @param  hpcd: PCD handle
-  * @retval None
-  */
- __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCD_SOFCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  USB Reset callback.
-  * @param  hpcd: PCD handle
-  * @retval None
-  */
- __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCD_ResetCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  Suspend event callback.
-  * @param  hpcd: PCD handle
-  * @retval None
-  */
- __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCD_SuspendCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  Resume event callback.
-  * @param  hpcd: PCD handle
-  * @retval None
-  */
- __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCD_ResumeCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  Incomplete ISO OUT callback.
-  * @param  hpcd: PCD handle
-  * @param  epnum: endpoint number
-  * @retval None
-  */
- __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-  UNUSED(epnum);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  Incomplete ISO IN callback.
-  * @param  hpcd: PCD handle
-  * @param  epnum: endpoint number  
-  * @retval None
-  */
- __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-  UNUSED(epnum);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  Connection event callback.
-  * @param  hpcd: PCD handle
-  * @retval None
-  */
- __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCD_ConnectCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  Disconnection event callback.
-  * @param  hpcd: PCD handle
-  * @retval None
-  */
- __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCD_DisconnectCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
- *  @brief   management functions
- *
-@verbatim 
- ===============================================================================
-                      ##### Peripheral Control functions #####
- ===============================================================================  
-    [..]
-    This subsection provides a set of functions allowing to control the PCD data 
-    transfers.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Connect the USB device.
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
-{
-  __HAL_LOCK(hpcd); 
-  USB_DevConnect(hpcd->Instance);
-  __HAL_UNLOCK(hpcd); 
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disconnect the USB device.
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
-{
-  __HAL_LOCK(hpcd); 
-  USB_DevDisconnect(hpcd->Instance);
-  __HAL_UNLOCK(hpcd); 
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set the USB Device address. 
-  * @param  hpcd: PCD handle
-  * @param  address: new device address
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
-{
-  __HAL_LOCK(hpcd); 
-  USB_SetDevAddress(hpcd->Instance, address);
-  __HAL_UNLOCK(hpcd);   
-  return HAL_OK;
-}
-/**
-  * @brief  Open and configure an endpoint.
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
-  * @param  ep_mps: endpoint max packet size
-  * @param  ep_type: endpoint type   
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
-{
-  HAL_StatusTypeDef  ret = HAL_OK;
-  USB_OTG_EPTypeDef *ep;
-  
-  if ((ep_addr & 0x80U) == 0x80U)
-  {
-    ep = &hpcd->IN_ep[ep_addr & 0x7FU];
-  }
-  else
-  {
-    ep = &hpcd->OUT_ep[ep_addr & 0x7FU];
-  }
-  ep->num   = ep_addr & 0x7FU;
-  
-  ep->is_in = (0x80U & ep_addr) != 0U;
-  ep->maxpacket = ep_mps;
-  ep->type = ep_type;
-  if (ep->is_in)
-  {
-    /* Assign a Tx FIFO */
-    ep->tx_fifo_num = ep->num;
-  }
-  /* Set initial data PID. */
-  if (ep_type == EP_TYPE_BULK )
-  {
-    ep->data_pid_start = 0U;
-  }
-  
-  __HAL_LOCK(hpcd); 
-  USB_ActivateEndpoint(hpcd->Instance , ep);
-  __HAL_UNLOCK(hpcd);   
-  return ret;
-}
-
-
-/**
-  * @brief  Deactivate an endpoint.
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{  
-  USB_OTG_EPTypeDef *ep;
-  
-  if ((ep_addr & 0x80U) == 0x80U)
-  {
-    ep = &hpcd->IN_ep[ep_addr & 0x7FU];
-  }
-  else
-  {
-    ep = &hpcd->OUT_ep[ep_addr & 0x7FU];
-  }
-  ep->num   = ep_addr & 0x7FU;
-  
-  ep->is_in = (0x80U & ep_addr) != 0U;
-  
-  __HAL_LOCK(hpcd); 
-  USB_DeactivateEndpoint(hpcd->Instance , ep);
-  __HAL_UNLOCK(hpcd);   
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  Receive an amount of data.  
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
-  * @param  pBuf: pointer to the reception buffer   
-  * @param  len: amount of data to be received
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
-{
-  USB_OTG_EPTypeDef *ep;
-  
-  ep = &hpcd->OUT_ep[ep_addr & 0x7FU];
-  
-  /*setup and start the Xfer */
-  ep->xfer_buff = pBuf;  
-  ep->xfer_len = len;
-  ep->xfer_count = 0U;
-  ep->is_in = 0U;
-  ep->num = ep_addr & 0x7FU;
-  
-  if (hpcd->Init.dma_enable == 1U)
-  {
-    ep->dma_addr = (uint32_t)pBuf;  
-  }
-  
-  __HAL_LOCK(hpcd); 
-  
-  if ((ep_addr & 0x7FU) == 0U)
-  {
-    USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
-  }
-  else
-  {
-    USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
-  }
-  __HAL_UNLOCK(hpcd); 
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Get Received Data Size.
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
-  * @retval Data Size
-  */
-uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
-  return hpcd->OUT_ep[ep_addr & 0x7FU].xfer_count;
-}
-/**
-  * @brief  Send an amount of data.  
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
-  * @param  pBuf: pointer to the transmission buffer   
-  * @param  len: amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
-{
-  USB_OTG_EPTypeDef *ep;
-  
-  ep = &hpcd->IN_ep[ep_addr & 0x7FU];
-  
-  /*setup and start the Xfer */
-  ep->xfer_buff = pBuf;  
-  ep->xfer_len = len;
-  ep->xfer_count = 0U;
-  ep->is_in = 1U;
-  ep->num = ep_addr & 0x7FU;
-  
-  if (hpcd->Init.dma_enable == 1U)
-  {
-    ep->dma_addr = (uint32_t)pBuf;  
-  }
-  
-  __HAL_LOCK(hpcd); 
-  
-  if ((ep_addr & 0x7FU) == 0U)
-  {
-    USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
-  }
-  else
-  {
-    USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
-  }
-  
-  __HAL_UNLOCK(hpcd);
-     
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set a STALL condition over an endpoint.
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
-  USB_OTG_EPTypeDef *ep;
-  
-  if ((0x80U & ep_addr) == 0x80U)
-  {
-    ep = &hpcd->IN_ep[ep_addr & 0x7FU];
-  }
-  else
-  {
-    ep = &hpcd->OUT_ep[ep_addr];
-  }
-  
-  ep->is_stall = 1U;
-  ep->num   = ep_addr & 0x7FU;
-  ep->is_in = ((ep_addr & 0x80U) == 0x80U);
-  
-  
-  __HAL_LOCK(hpcd); 
-  USB_EPSetStall(hpcd->Instance , ep);
-  if((ep_addr & 0x7FU) == 0U)
-  {
-    USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
-  }
-  __HAL_UNLOCK(hpcd); 
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Clear a STALL condition over in an endpoint.
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
-  USB_OTG_EPTypeDef *ep;
-  
-  if ((0x80U & ep_addr) == 0x80U)
-  {
-    ep = &hpcd->IN_ep[ep_addr & 0x7FU];
-  }
-  else
-  {
-    ep = &hpcd->OUT_ep[ep_addr];
-  }
-  
-  ep->is_stall = 0U;
-  ep->num   = ep_addr & 0x7FU;
-  ep->is_in = ((ep_addr & 0x80U) == 0x80U);
-  
-  __HAL_LOCK(hpcd); 
-  USB_EPClearStall(hpcd->Instance , ep);
-  __HAL_UNLOCK(hpcd); 
-    
-  return HAL_OK;
-}
-
-/**
-  * @brief  Flush an endpoint.
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
-  __HAL_LOCK(hpcd); 
-  
-  if ((ep_addr & 0x80U) == 0x80U)
-  {
-    USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7FU);
-  }
-  else
-  {
-    USB_FlushRxFifo(hpcd->Instance);
-  }
-  
-  __HAL_UNLOCK(hpcd); 
-    
-  return HAL_OK;
-}
-
-/**
-  * @brief  Activate remote wakeup signalling.
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
-{
-  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;  
-    
-  if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
-  {
-    /* Activate Remote wakeup signaling */
-    USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;
-  }
-  return HAL_OK;  
-}
-
-/**
-  * @brief  De-activate remote wakeup signalling.
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
-{
-  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;  
-  
-  /* De-activate Remote wakeup signaling */
-  USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);
-  return HAL_OK;  
-}
-/**
-  * @}
-  */
-  
-/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions 
- *  @brief   Peripheral State functions
- *
-@verbatim  
- ===============================================================================
-                      ##### Peripheral State functions #####
- ===============================================================================  
-    [..]
-    This subsection permits to get in run-time the status of the peripheral 
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the PCD handle state.
-  * @param  hpcd: PCD handle
-  * @retval HAL state
-  */
-PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
-{
-  return hpcd->State;
-}
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @addtogroup PCD_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Check FIFO for the next packet to be loaded.
-  * @param  hpcd: PCD handle
-  * @param  epnum : endpoint number   
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)
-{
-  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;  
-  USB_OTG_EPTypeDef *ep;
-  int32_t len = 0U;
-  uint32_t len32b;
-  uint32_t fifoemptymsk = 0U;
-
-  ep = &hpcd->IN_ep[epnum];
-  len = ep->xfer_len - ep->xfer_count;
-  
-  if (len > ep->maxpacket)
-  {
-    len = ep->maxpacket;
-  }
-  
-  
-  len32b = (len + 3U) / 4U;
- 
-  while  ( (USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b &&
-          ep->xfer_count < ep->xfer_len &&
-            ep->xfer_len != 0U)
-  {
-    /* Write the FIFO */
-    len = ep->xfer_len - ep->xfer_count;
-    
-    if (len > ep->maxpacket)
-    {
-      len = ep->maxpacket;
-    }
-    len32b = (len + 3U) / 4U;
-    
-    USB_WritePacket(USBx, ep->xfer_buff, epnum, len, hpcd->Init.dma_enable); 
-    
-    ep->xfer_buff  += len;
-    ep->xfer_count += len;
-  }
-  
-  if(len <= 0U)
-  {
-    fifoemptymsk = 0x1U << epnum;
-    USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
-    
-  }
-  
-  return HAL_OK;  
-}
-
-/**
-  * @}
-  */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx ||
-          STM32F412Vx || STM32F412Cx */
-#endif /* HAL_PCD_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_pcd_ex.c b/stmhal/hal/f4/src/stm32f4xx_hal_pcd_ex.c
deleted file mode 100644
index 9f9b49384a..0000000000
--- a/stmhal/hal/f4/src/stm32f4xx_hal_pcd_ex.c
+++ /dev/null
@@ -1,324 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_pcd_ex.c
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   PCD HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the USB Peripheral Controller:
-  *           + Extended features functions
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup PCDEx PCDEx
-  * @brief PCD Extended HAL module driver
-  * @{
-  */
-#ifdef HAL_PCD_MODULE_ENABLED
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
-    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
-    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
-    defined(STM32F412Rx) || defined(STM32F412Cx)
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup PCDEx_Exported_Functions PCD Extended Exported Functions
-  * @{
-  */
-
-/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
-  * @brief    PCDEx control functions 
-  *
-@verbatim  
- ===============================================================================
-                 ##### Extended features functions #####
- ===============================================================================  
-    [..]  This section provides functions allowing to:
-      (+) Update FIFO configuration
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Set Tx FIFO
-  * @param  hpcd: PCD handle
-  * @param  fifo: The number of Tx fifo
-  * @param  size: Fifo size
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
-{
-  uint8_t i = 0U;
-  uint32_t Tx_Offset = 0U;
-
-  /*  TXn min size = 16 words. (n  : Transmit FIFO index)
-      When a TxFIFO is not used, the Configuration should be as follows: 
-          case 1 :  n > m    and Txn is not used    (n,m  : Transmit FIFO indexes)
-         --> Txm can use the space allocated for Txn.
-         case2  :  n < m    and Txn is not used    (n,m  : Transmit FIFO indexes)
-         --> Txn should be configured with the minimum space of 16 words
-     The FIFO is used optimally when used TxFIFOs are allocated in the top 
-         of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
-     When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
-  
-  Tx_Offset = hpcd->Instance->GRXFSIZ;
-  
-  if(fifo == 0U)
-  {
-    hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((uint32_t)size << 16U) | Tx_Offset);
-  }
-  else
-  {
-    Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16U;
-    for (i = 0U; i < (fifo - 1U); i++)
-    {
-      Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16U);
-    }
-    
-    /* Multiply Tx_Size by 2 to get higher performance */
-    hpcd->Instance->DIEPTXF[fifo - 1U] = (uint32_t)(((uint32_t)size << 16U) | Tx_Offset);        
-  }
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set Rx FIFO
-  * @param  hpcd: PCD handle
-  * @param  size: Size of Rx fifo
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
-{
-  hpcd->Instance->GRXFSIZ = size;
-  
-  return HAL_OK;
-}
-
-#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
-    defined(STM32F412Rx) || defined(STM32F412Cx)
-/**
-  * @brief  Activate LPM feature
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
-{
-  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;  
-  
-  hpcd->lpm_active = ENABLE;
-  hpcd->LPM_State = LPM_L0;
-  USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
-  USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
-  
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Deactivate LPM feature.
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
-{
-  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;  
-  
-  hpcd->lpm_active = DISABLE;
-  USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM;
-  USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
-  
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Send LPM message to user layer callback.
-  * @param  hpcd: PCD handle
-  * @param  msg: LPM message
-  * @retval HAL status
-  */
-__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-  UNUSED(msg);
-}
-#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx */
-
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
-/**
-  * @brief  HAL_PCDEx_BCD_VBUSDetect : handle BatteryCharging Process
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
-{
-  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;  
-  uint32_t tickstart = HAL_GetTick();
-  
-  /* Start BCD When device is connected */
-  if (USBx_DEVICE->DCTL & USB_OTG_DCTL_SDIS)
-  {
-    /* Enable DCD : Data Contact Detect */
-    USBx->GCCFG |= USB_OTG_GCCFG_DCDEN;
-    
-    /* Wait Detect flag or a timeout is happen*/
-    while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0U)
-    {
-      /* Check for the Timeout */
-      if((HAL_GetTick() - tickstart ) > 1000U)
-      {
-        HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
-        return;
-      }
-    }
-    
-    /* Right response got */
-    HAL_Delay(100U); 
-    
-    /* Check Detect flag*/
-    if (USBx->GCCFG & USB_OTG_GCCFG_DCDET)
-    {
-      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
-    }
-    
-    /*Primary detection: checks if connected to Standard Downstream Port  
-    (without charging capability) */
-    USBx->GCCFG &=~ USB_OTG_GCCFG_DCDEN;
-    USBx->GCCFG |=  USB_OTG_GCCFG_PDEN;
-    HAL_Delay(100U); 
-    
-    if (!(USBx->GCCFG & USB_OTG_GCCFG_PDET))
-    {
-      /* Case of Standard Downstream Port */
-      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
-    }
-    else  
-    {
-      /* start secondary detection to check connection to Charging Downstream 
-      Port or Dedicated Charging Port */
-      USBx->GCCFG &=~ USB_OTG_GCCFG_PDEN;
-      USBx->GCCFG |=  USB_OTG_GCCFG_SDEN;
-      HAL_Delay(100U); 
-      
-      if ((USBx->GCCFG) & USB_OTG_GCCFG_SDET)
-      { 
-        /* case Dedicated Charging Port  */
-        HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
-      }
-      else
-      {
-        /* case Charging Downstream Port  */
-        HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
-      }
-    }
-    /* Battery Charging capability discovery finished */
-    HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
-  }
-}
-
-/**
-  * @brief  HAL_PCDEx_ActivateBCD : active BatteryCharging feature
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
-{
-  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;  
-
-  hpcd->battery_charging_active = ENABLE; 
-  USBx->GCCFG |= (USB_OTG_GCCFG_BCDEN);
-  
-  return HAL_OK;  
-}
-
-/**
-  * @brief  HAL_PCDEx_DeActivateBCD : de-active BatteryCharging feature
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
-{
-  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;  
-  hpcd->battery_charging_active = DISABLE; 
-  USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);
-  return HAL_OK;  
-}
-
-/**
-  * @brief  HAL_PCDEx_BatteryCharging_Callback : Send BatteryCharging message to user layer
-  * @param  hpcd: PCD handle
-  * @param  msg: LPM message
-  * @retval HAL status
-  */
-__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-  UNUSED(msg);
-}
-
-#endif /* STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx ||
-          STM32F412Vx || STM32F412Cx */
-#endif /* HAL_PCD_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_pwr.c b/stmhal/hal/f4/src/stm32f4xx_hal_pwr.c
deleted file mode 100644
index 2cb927eef6..0000000000
--- a/stmhal/hal/f4/src/stm32f4xx_hal_pwr.c
+++ /dev/null
@@ -1,577 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_pwr.c
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   PWR HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the Power Controller (PWR) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + Peripheral Control functions 
-  *         
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup PWR PWR
-  * @brief PWR HAL module driver
-  * @{
-  */
-
-#ifdef HAL_PWR_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup PWR_Private_Constants
-  * @{
-  */
-  
-/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
-  * @{
-  */     
-#define PVD_MODE_IT               ((uint32_t)0x00010000U)
-#define PVD_MODE_EVT              ((uint32_t)0x00020000U)
-#define PVD_RISING_EDGE           ((uint32_t)0x00000001U)
-#define PVD_FALLING_EDGE          ((uint32_t)0x00000002U)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */    
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup PWR_Exported_Functions PWR Exported Functions
-  * @{
-  */
-
-/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 
-  *  @brief    Initialization and de-initialization functions
-  *
-@verbatim
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]
-      After reset, the backup domain (RTC registers, RTC backup data 
-      registers and backup SRAM) is protected against possible unwanted 
-      write accesses. 
-      To enable access to the RTC Domain and RTC registers, proceed as follows:
-        (+) Enable the Power Controller (PWR) APB1 interface clock using the
-            __HAL_RCC_PWR_CLK_ENABLE() macro.
-        (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
- 
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Deinitializes the HAL PWR peripheral registers to their default reset values.
-  * @retval None
-  */
-void HAL_PWR_DeInit(void)
-{
-  __HAL_RCC_PWR_FORCE_RESET();
-  __HAL_RCC_PWR_RELEASE_RESET();
-}
-
-/**
-  * @brief Enables access to the backup domain (RTC registers, RTC 
-  *         backup data registers and backup SRAM).
-  * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the 
-  *         Backup Domain Access should be kept enabled.
-  * @retval None
-  */
-void HAL_PWR_EnableBkUpAccess(void)
-{
-  *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;
-}
-
-/**
-  * @brief Disables access to the backup domain (RTC registers, RTC 
-  *         backup data registers and backup SRAM).
-  * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the 
-  *         Backup Domain Access should be kept enabled.
-  * @retval None
-  */
-void HAL_PWR_DisableBkUpAccess(void)
-{
-  *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions 
-  *  @brief Low Power modes configuration functions 
-  *
-@verbatim
-
- ===============================================================================
-                 ##### Peripheral Control functions #####
- ===============================================================================
-     
-    *** PVD configuration ***
-    =========================
-    [..]
-      (+) The PVD is used to monitor the VDD power supply by comparing it to a 
-          threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
-      (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower 
-          than the PVD threshold. This event is internally connected to the EXTI 
-          line16 and can generate an interrupt if enabled. This is done through
-          __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
-      (+) The PVD is stopped in Standby mode.
-
-    *** Wake-up pin configuration ***
-    ================================
-    [..]
-      (+) Wake-up pin is used to wake up the system from Standby mode. This pin is 
-          forced in input pull-down configuration and is active on rising edges.
-      (+) There is one Wake-up pin: Wake-up Pin 1 on PA.00.
-	   (++) For STM32F446xx there are two Wake-Up pins: Pin1 on PA.00 and Pin2 on PC.13
-           (++) For STM32F410xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx  there are three Wake-Up pins: Pin1 on PA.00, Pin2 on PC.00 and Pin3 on PC.01 
-
-    *** Low Power modes configuration ***
-    =====================================
-    [..]
-      The devices feature 3 low-power modes:
-      (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.
-      (+) Stop mode: all clocks are stopped, regulator running, regulator 
-          in low power mode
-      (+) Standby mode: 1.2V domain powered off.
-   
-   *** Sleep mode ***
-   ==================
-    [..]
-      (+) Entry:
-        The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI)
-              functions with
-          (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
-          (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
-      
-      -@@- The Regulator parameter is not used for the STM32F4 family 
-              and is kept as parameter just to maintain compatibility with the 
-              lower power families (STM32L).
-      (+) Exit:
-        Any peripheral interrupt acknowledged by the nested vectored interrupt 
-              controller (NVIC) can wake up the device from Sleep mode.
-
-   *** Stop mode ***
-   =================
-    [..]
-      In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
-      and the HSE RC oscillators are disabled. Internal SRAM and register contents 
-      are preserved.
-      The voltage regulator can be configured either in normal or low-power mode.
-      To minimize the consumption In Stop mode, FLASH can be powered off before 
-      entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.
-      It can be switched on again by software after exiting the Stop mode using
-      the HAL_PWREx_DisableFlashPowerDown() function. 
-
-      (+) Entry:
-         The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON) 
-             function with:
-          (++) Main regulator ON.
-          (++) Low Power regulator ON.
-      (+) Exit:
-        Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
-
-   *** Standby mode ***
-   ====================
-    [..]
-    (+)
-      The Standby mode allows to achieve the lowest power consumption. It is based 
-      on the Cortex-M4 deep sleep mode, with the voltage regulator disabled. 
-      The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and 
-      the HSE oscillator are also switched off. SRAM and register contents are lost 
-      except for the RTC registers, RTC backup registers, backup SRAM and Standby 
-      circuitry.
-   
-      The voltage regulator is OFF.
-      
-      (++) Entry:
-        (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
-      (++) Exit:
-        (+++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wake-up,
-             tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
-
-   *** Auto-wake-up (AWU) from low-power mode ***
-   =============================================
-    [..]
-    
-     (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC 
-      Wake-up event, a tamper event or a time-stamp event, without depending on 
-      an external interrupt (Auto-wake-up mode).
-
-      (+) RTC auto-wake-up (AWU) from the Stop and Standby modes
-       
-        (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to 
-              configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
-
-        (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it 
-             is necessary to configure the RTC to detect the tamper or time stamp event using the
-                HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
-                  
-        (++) To wake up from the Stop mode with an RTC Wake-up event, it is necessary to
-              configure the RTC to generate the RTC Wake-up event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
-  * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
-  *        information for the PVD.
-  * @note Refer to the electrical characteristics of your device datasheet for
-  *         more details about the voltage threshold corresponding to each 
-  *         detection level.
-  * @retval None
-  */
-void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
-{
-  /* Check the parameters */
-  assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
-  assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
-  
-  /* Set PLS[7:5] bits according to PVDLevel value */
-  MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
-  
-  /* Clear any previous config. Keep it clear if no event or IT mode is selected */
-  __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
-  __HAL_PWR_PVD_EXTI_DISABLE_IT();
-  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
-  __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); 
-
-  /* Configure interrupt mode */
-  if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
-  {
-    __HAL_PWR_PVD_EXTI_ENABLE_IT();
-  }
-  
-  /* Configure event mode */
-  if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
-  {
-    __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
-  }
-  
-  /* Configure the edge */
-  if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
-  {
-    __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
-  }
-  
-  if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
-  {
-    __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
-  }
-}
-
-/**
-  * @brief Enables the Power Voltage Detector(PVD).
-  * @retval None
-  */
-void HAL_PWR_EnablePVD(void)
-{
-  *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE;
-}
-
-/**
-  * @brief Disables the Power Voltage Detector(PVD).
-  * @retval None
-  */
-void HAL_PWR_DisablePVD(void)
-{
-  *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE;
-}
-
-/**
-  * @brief Enables the Wake-up PINx functionality.
-  * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
-  *         This parameter can be one of the following values:
-  *           @arg PWR_WAKEUP_PIN1
-  *           @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx devices
-  *           @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx devices
-  * @retval None
-  */
-void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
-{
-  /* Check the parameter */
-  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
-
-  /* Enable the wake up pin */
-  SET_BIT(PWR->CSR, WakeUpPinx);
-}
-
-/**
-  * @brief Disables the Wake-up PINx functionality.
-  * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
-  *         This parameter can be one of the following values:
-  *           @arg PWR_WAKEUP_PIN1
-  *           @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx devices
-  *           @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx devices
-  * @retval None
-  */
-void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
-{
-  /* Check the parameter */
-  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));  
-
-  /* Disable the wake up pin */
-  CLEAR_BIT(PWR->CSR, WakeUpPinx);
-}
-  
-/**
-  * @brief Enters Sleep mode.
-  *   
-  * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
-  * 
-  * @note In Sleep mode, the systick is stopped to avoid exit from this mode with
-  *       systick interrupt when used as time base for Timeout 
-  *                
-  * @param Regulator: Specifies the regulator state in SLEEP mode.
-  *            This parameter can be one of the following values:
-  *            @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
-  *            @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
-  * @note This parameter is not used for the STM32F4 family and is kept as parameter
-  *       just to maintain compatibility with the lower power families.
-  * @param SLEEPEntry: Specifies if SLEEP mode in entered with WFI or WFE instruction.
-  *          This parameter can be one of the following values:
-  *            @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
-  *            @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
-  * @retval None
-  */
-void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
-{
-  /* Check the parameters */
-  assert_param(IS_PWR_REGULATOR(Regulator));
-  assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
-
-  /* Clear SLEEPDEEP bit of Cortex System Control Register */
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-
-  /* Select SLEEP mode entry -------------------------------------------------*/
-  if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
-  {   
-    /* Request Wait For Interrupt */
-    __WFI();
-  }
-  else
-  {
-    /* Request Wait For Event */
-    __SEV();
-    __WFE();
-    __WFE();
-  }
-}
-
-/**
-  * @brief Enters Stop mode. 
-  * @note In Stop mode, all I/O pins keep the same state as in Run mode.
-  * @note When exiting Stop mode by issuing an interrupt or a wake-up event, 
-  *         the HSI RC oscillator is selected as system clock.
-  * @note When the voltage regulator operates in low power mode, an additional 
-  *         startup delay is incurred when waking up from Stop mode. 
-  *         By keeping the internal regulator ON during Stop mode, the consumption 
-  *         is higher although the startup time is reduced.    
-  * @param Regulator: Specifies the regulator state in Stop mode.
-  *          This parameter can be one of the following values:
-  *            @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
-  *            @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
-  * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
-  *          This parameter can be one of the following values:
-  *            @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
-  *            @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
-  * @retval None
-  */
-void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
-{
-  /* Check the parameters */
-  assert_param(IS_PWR_REGULATOR(Regulator));
-  assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
-  
-  /* Select the regulator state in Stop mode: Set PDDS and LPDS bits according to PWR_Regulator value */
-  MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS), Regulator);
-  
-  /* Set SLEEPDEEP bit of Cortex System Control Register */
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-  
-  /* Select Stop mode entry --------------------------------------------------*/
-  if(STOPEntry == PWR_STOPENTRY_WFI)
-  {   
-    /* Request Wait For Interrupt */
-    __WFI();
-  }
-  else
-  {
-    /* Request Wait For Event */
-    __SEV();
-    __WFE();
-    __WFE();
-  }
-  /* Reset SLEEPDEEP bit of Cortex System Control Register */
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));  
-}
-
-/**
-  * @brief Enters Standby mode.
-  * @note In Standby mode, all I/O pins are high impedance except for:
-  *          - Reset pad (still available) 
-  *          - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC 
-  *            Alarm out, or RTC clock calibration out.
-  *          - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.  
-  *          - WKUP pin 1 (PA0) if enabled.       
-  * @retval None
-  */
-void HAL_PWR_EnterSTANDBYMode(void)
-{
-  /* Select Standby mode */
-  SET_BIT(PWR->CR, PWR_CR_PDDS);
-
-  /* Set SLEEPDEEP bit of Cortex System Control Register */
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-  
-  /* This option is used to ensure that store operations are completed */
-#if defined ( __CC_ARM)
-  __force_stores();
-#endif
-  /* Request Wait For Interrupt */
-  __WFI();
-}
-
-/**
-  * @brief This function handles the PWR PVD interrupt request.
-  * @note This API should be called under the PVD_IRQHandler().
-  * @retval None
-  */
-void HAL_PWR_PVD_IRQHandler(void)
-{
-  /* Check PWR Exti flag */
-  if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
-  {
-    /* PWR PVD interrupt user callback */
-    HAL_PWR_PVDCallback();
-    
-    /* Clear PWR Exti pending bit */
-    __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
-  }
-}
-
-/**
-  * @brief  PWR PVD interrupt callback
-  * @retval None
-  */
-__weak void HAL_PWR_PVDCallback(void)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PWR_PVDCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. 
-  * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor 
-  *       re-enters SLEEP mode when an interruption handling is over.
-  *       Setting this bit is useful when the processor is expected to run only on
-  *       interruptions handling.         
-  * @retval None
-  */
-void HAL_PWR_EnableSleepOnExit(void)
-{
-  /* Set SLEEPONEXIT bit of Cortex System Control Register */
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
-}
-
-/**
-  * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. 
-  * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor 
-  *       re-enters SLEEP mode when an interruption handling is over.          
-  * @retval None
-  */
-void HAL_PWR_DisableSleepOnExit(void)
-{
-  /* Clear SLEEPONEXIT bit of Cortex System Control Register */
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
-}
-
-/**
-  * @brief Enables CORTEX M4 SEVONPEND bit. 
-  * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes 
-  *       WFE to wake up when an interrupt moves from inactive to pended.
-  * @retval None
-  */
-void HAL_PWR_EnableSEVOnPend(void)
-{
-  /* Set SEVONPEND bit of Cortex System Control Register */
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
-}
-
-/**
-  * @brief Disables CORTEX M4 SEVONPEND bit. 
-  * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes 
-  *       WFE to wake up when an interrupt moves from inactive to pended.         
-  * @retval None
-  */
-void HAL_PWR_DisableSEVOnPend(void)
-{
-  /* Clear SEVONPEND bit of Cortex System Control Register */
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
-}
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-
-#endif /* HAL_PWR_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_pwr_ex.c b/stmhal/hal/f4/src/stm32f4xx_hal_pwr_ex.c
deleted file mode 100644
index 06c7e631a2..0000000000
--- a/stmhal/hal/f4/src/stm32f4xx_hal_pwr_ex.c
+++ /dev/null
@@ -1,649 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_pwr_ex.c
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   Extended PWR HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of PWR extension peripheral:           
-  *           + Peripheral Extended features functions
-  *         
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup PWREx PWREx
-  * @brief PWR HAL module driver
-  * @{
-  */
-
-#ifdef HAL_PWR_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup PWREx_Private_Constants
-  * @{
-  */    
-#define PWR_OVERDRIVE_TIMEOUT_VALUE  1000U
-#define PWR_UDERDRIVE_TIMEOUT_VALUE  1000U
-#define PWR_BKPREG_TIMEOUT_VALUE     1000U
-#define PWR_VOSRDY_TIMEOUT_VALUE     1000U
-/**
-  * @}
-  */
-
-   
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup PWREx_Exported_Functions PWREx Exported Functions
-  *  @{
-  */
-
-/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions 
-  *  @brief Peripheral Extended features functions 
-  *
-@verbatim   
-
- ===============================================================================
-                 ##### Peripheral extended features functions #####
- ===============================================================================
-
-    *** Main and Backup Regulators configuration ***
-    ================================================
-    [..] 
-      (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from 
-          the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is 
-          retained even in Standby or VBAT mode when the low power backup regulator
-          is enabled. It can be considered as an internal EEPROM when VBAT is 
-          always present. You can use the HAL_PWREx_EnableBkUpReg() function to 
-          enable the low power backup regulator. 
-
-      (+) When the backup domain is supplied by VDD (analog switch connected to VDD) 
-          the backup SRAM is powered from VDD which replaces the VBAT power supply to 
-          save battery life.
-
-      (+) The backup SRAM is not mass erased by a tamper event. It is read 
-          protected to prevent confidential data, such as cryptographic private 
-          key, from being accessed. The backup SRAM can be erased only through 
-          the Flash interface when a protection level change from level 1 to 
-          level 0 is requested. 
-      -@- Refer to the description of Read protection (RDP) in the Flash 
-          programming manual.
-
-      (+) The main internal regulator can be configured to have a tradeoff between 
-          performance and power consumption when the device does not operate at 
-          the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG() 
-          macro which configure VOS bit in PWR_CR register
-          
-        Refer to the product datasheets for more details.
-
-    *** FLASH Power Down configuration ****
-    =======================================
-    [..] 
-      (+) By setting the FPDS bit in the PWR_CR register by using the 
-          HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power 
-          down mode when the device enters Stop mode. When the Flash memory 
-          is in power down mode, an additional startup delay is incurred when 
-          waking up from Stop mode.
-          
-           (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, the scale can be modified only when the PLL 
-           is OFF and the HSI or HSE clock source is selected as system clock. 
-           The new value programmed is active only when the PLL is ON.
-           When the PLL is OFF, the voltage scale 3 is automatically selected. 
-        Refer to the datasheets for more details.
-
-    *** Over-Drive and Under-Drive configuration ****
-    =================================================
-    [..]         
-       (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Run mode: the main regulator has
-           2 operating modes available:
-        (++) Normal mode: The CPU and core logic operate at maximum frequency at a given 
-             voltage scaling (scale 1, scale 2 or scale 3)
-        (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a 
-            higher frequency than the normal mode for a given voltage scaling (scale 1,  
-            scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and
-            disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow 
-            the sequence described in Reference manual.
-             
-       (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Stop mode: the main regulator or low power regulator 
-           supplies a low power voltage to the 1.2V domain, thus preserving the content of registers 
-           and internal SRAM. 2 operating modes are available:
-         (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only 
-              available when the main regulator or the low power regulator is used in Scale 3 or 
-              low voltage mode.
-         (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only
-              available when the main regulator or the low power regulator is in low voltage mode.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Enables the Backup Regulator.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)
-{
-  uint32_t tickstart = 0U;
-
-  *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)ENABLE;
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  /* Wait till Backup regulator ready flag is set */  
-  while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET)
-  {
-    if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
-    {
-      return HAL_TIMEOUT;
-    } 
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief Disables the Backup Regulator.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)
-{
-  uint32_t tickstart = 0U;
-
-  *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)DISABLE;
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  /* Wait till Backup regulator ready flag is set */  
-  while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET)
-  {
-    if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
-    {
-      return HAL_TIMEOUT;
-    } 
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief Enables the Flash Power Down in Stop mode.
-  * @retval None
-  */
-void HAL_PWREx_EnableFlashPowerDown(void)
-{
-  *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)ENABLE;
-}
-
-/**
-  * @brief Disables the Flash Power Down in Stop mode.
-  * @retval None
-  */
-void HAL_PWREx_DisableFlashPowerDown(void)
-{
-  *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)DISABLE;
-}
-
-/**
-  * @brief Return Voltage Scaling Range.
-  * @retval The configured scale for the regulator voltage(VOS bit field).
-  *         The returned value can be one of the following:
-  *            - @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
-  *            - @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
-  *            - @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
-  */  
-uint32_t HAL_PWREx_GetVoltageRange(void)
-{
-  return (PWR->CR & PWR_CR_VOS);
-}
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
-/**
-  * @brief Configures the main internal regulator output voltage.
-  * @param  VoltageScaling: specifies the regulator output voltage to achieve
-  *         a tradeoff between performance and power consumption.
-  *          This parameter can be one of the following values:
-  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
-  *                                               the maximum value of fHCLK = 168 MHz.
-  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,
-  *                                               the maximum value of fHCLK = 144 MHz.
-  * @note  When moving from Range 1 to Range 2, the system frequency must be decreased to
-  *        a value below 144 MHz before calling HAL_PWREx_ConfigVoltageScaling() API.
-  *        When moving from Range 2 to Range 1, the system frequency can be increased to
-  *        a value up to 168 MHz after calling HAL_PWREx_ConfigVoltageScaling() API.
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
-{
-  uint32_t tickstart = 0U;
-  
-  assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
-  
-  /* Enable PWR RCC Clock Peripheral */
-  __HAL_RCC_PWR_CLK_ENABLE();
-  
-  /* Set Range */
-  __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);
-  
-  /* Get Start Tick*/
-  tickstart = HAL_GetTick();
-  while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))
-  {
-    if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)
-    {
-      return HAL_TIMEOUT;
-    } 
-  }
-
-  return HAL_OK;
-}
-
-#elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
-      defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \
-      defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || \
-      defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || \
-      defined(STM32F412Cx)
-/**
-  * @brief Configures the main internal regulator output voltage.
-  * @param  VoltageScaling: specifies the regulator output voltage to achieve
-  *         a tradeoff between performance and power consumption.
-  *          This parameter can be one of the following values:
-  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
-  *                                               the maximum value of fHCLK is 168 MHz. It can be extended to
-  *                                               180 MHz by activating the over-drive mode.
-  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,
-  *                                               the maximum value of fHCLK is 144 MHz. It can be extended to,                
-  *                                               168 MHz by activating the over-drive mode.
-  *            @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 3 mode,
-  *                                               the maximum value of fHCLK is 120 MHz.
-  * @note To update the system clock frequency(SYSCLK):
-  *        - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig().
-  *        - Call the HAL_RCC_OscConfig() to configure the PLL.
-  *        - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale.
-  *        - Set the new system clock frequency using the HAL_RCC_ClockConfig().
-  * @note The scale can be modified only when the HSI or HSE clock source is selected 
-  *        as system clock source, otherwise the API returns HAL_ERROR.  
-  * @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits
-  *       value in the PWR_CR1 register are not taken in account.
-  * @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2.
-  * @note The new voltage scale is active only when the PLL is ON.  
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
-{
-  uint32_t tickstart = 0U;
-  
-  assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
-  
-  /* Enable PWR RCC Clock Peripheral */
-  __HAL_RCC_PWR_CLK_ENABLE();
-  
-  /* Check if the PLL is used as system clock or not */
-  if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
-  {
-    /* Disable the main PLL */
-    __HAL_RCC_PLL_DISABLE();
-    
-    /* Get Start Tick */
-    tickstart = HAL_GetTick();    
-    /* Wait till PLL is disabled */  
-    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-    
-    /* Set Range */
-    __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);
-    
-    /* Enable the main PLL */
-    __HAL_RCC_PLL_ENABLE();
-    
-    /* Get Start Tick */
-    tickstart = HAL_GetTick();
-    /* Wait till PLL is ready */  
-    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
-      {
-        return HAL_TIMEOUT;
-      } 
-    }
-    
-    /* Get Start Tick */
-    tickstart = HAL_GetTick();
-    while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))
-    {
-      if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)
-      {
-        return HAL_TIMEOUT;
-      } 
-    }
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-
-  return HAL_OK;
-}
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
-
-#if defined(STM32F469xx) || defined(STM32F479xx)
-/**
-  * @brief Enables Wakeup Pin Detection on high level (rising edge).
-  * @retval None
-  */
-void HAL_PWREx_EnableWakeUpPinPolarityRisingEdge(void)
-{
-  *(__IO uint32_t *) CSR_WUPP_BB = (uint32_t)DISABLE;
-}
-
-/**
-  * @brief Enables Wakeup Pin Detection on low level (falling edge).
-  * @retval None
-  */
-void HAL_PWREx_EnableWakeUpPinPolarityFallingEdge(void)
-{
-  *(__IO uint32_t *) CSR_WUPP_BB = (uint32_t)ENABLE;
-}
-#endif /* STM32F469xx || STM32F479xx */
-
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
-    defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
-/**
-  * @brief Enables Main Regulator low voltage mode.
-  * @note  This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx devices.   
-  * @retval None
-  */
-void HAL_PWREx_EnableMainRegulatorLowVoltage(void)
-{
-  *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)ENABLE;
-}
-
-/**
-  * @brief Disables Main Regulator low voltage mode.
-  * @note  This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx devices. 
-  * @retval None
-  */
-void HAL_PWREx_DisableMainRegulatorLowVoltage(void)
-{
-  *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)DISABLE;
-}
-
-/**
-  * @brief Enables Low Power Regulator low voltage mode.
-  * @note  This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx devices.   
-  * @retval None
-  */
-void HAL_PWREx_EnableLowRegulatorLowVoltage(void)
-{
-  *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)ENABLE;
-}
-
-/**
-  * @brief Disables Low Power Regulator low voltage mode.
-  * @note  This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx devices.   
-  * @retval None
-  */
-void HAL_PWREx_DisableLowRegulatorLowVoltage(void)
-{
-  *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)DISABLE;
-}
-
-#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
-/**
-  * @brief  Activates the Over-Drive mode.
-  * @note   This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices.
-  *         This mode allows the CPU and the core logic to operate at a higher frequency
-  *         than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).   
-  * @note   It is recommended to enter or exit Over-drive mode when the application is not running 
-  *         critical tasks and when the system clock source is either HSI or HSE. 
-  *         During the Over-drive switch activation, no peripheral clocks should be enabled.   
-  *         The peripheral clocks must be enabled once the Over-drive mode is activated.   
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)
-{
-  uint32_t tickstart = 0U;
-
-  __HAL_RCC_PWR_CLK_ENABLE();
-  
-  /* Enable the Over-drive to extend the clock frequency to 180 Mhz */
-  __HAL_PWR_OVERDRIVE_ENABLE();
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
-  {
-    if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE)
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-  
-  /* Enable the Over-drive switch */
-  __HAL_PWR_OVERDRIVESWITCHING_ENABLE();
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
-  {
-    if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
-    {
-      return HAL_TIMEOUT;
-    }
-  } 
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deactivates the Over-Drive mode.
-  * @note   This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices.
-  *         This mode allows the CPU and the core logic to operate at a higher frequency
-  *         than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).    
-  * @note   It is recommended to enter or exit Over-drive mode when the application is not running 
-  *         critical tasks and when the system clock source is either HSI or HSE. 
-  *         During the Over-drive switch activation, no peripheral clocks should be enabled.   
-  *         The peripheral clocks must be enabled once the Over-drive mode is activated.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void)
-{
-  uint32_t tickstart = 0U;
-  
-  __HAL_RCC_PWR_CLK_ENABLE();
-    
-  /* Disable the Over-drive switch */
-  __HAL_PWR_OVERDRIVESWITCHING_DISABLE();
-  
-  /* Get tick */
-  tickstart = HAL_GetTick();
- 
-  while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
-  {
-    if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE)
-    {
-      return HAL_TIMEOUT;
-    }
-  } 
-  
-  /* Disable the Over-drive */
-  __HAL_PWR_OVERDRIVE_DISABLE();
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
-  {
-    if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE)
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enters in Under-Drive STOP mode.
-  *  
-  * @note   This mode is only available for STM32F42xxx/STM324F3xxx/STM32F446xx/STM32F469xx/STM32F479xx devices. 
-  * 
-  * @note    This mode can be selected only when the Under-Drive is already active 
-  *   
-  * @note    This mode is enabled only with STOP low power mode.
-  *          In this mode, the 1.2V domain is preserved in reduced leakage mode. This 
-  *          mode is only available when the main regulator or the low power regulator 
-  *          is in low voltage mode
-  *        
-  * @note   If the Under-drive mode was enabled, it is automatically disabled after 
-  *         exiting Stop mode. 
-  *         When the voltage regulator operates in Under-drive mode, an additional  
-  *         startup delay is induced when waking up from Stop mode.
-  *                    
-  * @note   In Stop mode, all I/O pins keep the same state as in Run mode.
-  *   
-  * @note   When exiting Stop mode by issuing an interrupt or a wake-up event, 
-  *         the HSI RC oscillator is selected as system clock.
-  *           
-  * @note   When the voltage regulator operates in low power mode, an additional 
-  *         startup delay is incurred when waking up from Stop mode. 
-  *         By keeping the internal regulator ON during Stop mode, the consumption 
-  *         is higher although the startup time is reduced.
-  *     
-  * @param  Regulator: specifies the regulator state in STOP mode.
-  *          This parameter can be one of the following values:
-  *            @arg PWR_MAINREGULATOR_UNDERDRIVE_ON:  Main Regulator in under-drive mode 
-  *                 and Flash memory in power-down when the device is in Stop under-drive mode
-  *            @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON:  Low Power Regulator in under-drive mode 
-  *                and Flash memory in power-down when the device is in Stop under-drive mode
-  * @param  STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
-  *          This parameter can be one of the following values:
-  *            @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction
-  *            @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
-{
-  uint32_t tmpreg1 = 0U;
-  uint32_t tickstart = 0U;
-  
-  /* Check the parameters */
-  assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator));
-  assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
-  
-  /* Enable Power ctrl clock */
-  __HAL_RCC_PWR_CLK_ENABLE();
-  /* Enable the Under-drive Mode ---------------------------------------------*/
-  /* Clear Under-drive flag */
-  __HAL_PWR_CLEAR_ODRUDR_FLAG();
-  
-  /* Enable the Under-drive */ 
-  __HAL_PWR_UNDERDRIVE_ENABLE();
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  /* Wait for UnderDrive mode is ready */
-  while(__HAL_PWR_GET_FLAG(PWR_FLAG_UDRDY))
-  {
-    if((HAL_GetTick() - tickstart) > PWR_UDERDRIVE_TIMEOUT_VALUE)
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-  
-  /* Select the regulator state in STOP mode ---------------------------------*/
-  tmpreg1 = PWR->CR;
-  /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */
-  tmpreg1 &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_MRUDS);
-  
-  /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */
-  tmpreg1 |= Regulator;
-  
-  /* Store the new value */
-  PWR->CR = tmpreg1;
-  
-  /* Set SLEEPDEEP bit of Cortex System Control Register */
-  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-  
-  /* Select STOP mode entry --------------------------------------------------*/
-  if(STOPEntry == PWR_SLEEPENTRY_WFI)
-  {   
-    /* Request Wait For Interrupt */
-    __WFI();
-  }
-  else
-  {
-    /* Request Wait For Event */
-    __WFE();
-  }
-  /* Reset SLEEPDEEP bit of Cortex System Control Register */
-  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
-
-  return HAL_OK;  
-}
-
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_PWR_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_rcc.c b/stmhal/hal/f4/src/stm32f4xx_hal_rcc.c
deleted file mode 100644
index 3861b52665..0000000000
--- a/stmhal/hal/f4/src/stm32f4xx_hal_rcc.c
+++ /dev/null
@@ -1,1113 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_rcc.c
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   RCC HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the Reset and Clock Control (RCC) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + Peripheral Control functions
-  *       
-  @verbatim                
-  ==============================================================================
-                      ##### RCC specific features #####
-  ==============================================================================
-    [..]  
-      After reset the device is running from Internal High Speed oscillator 
-      (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache 
-      and I-Cache are disabled, and all peripherals are off except internal
-      SRAM, Flash and JTAG.
-      (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
-          all peripherals mapped on these busses are running at HSI speed.
-      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
-      (+) All GPIOs are in input floating state, except the JTAG pins which
-          are assigned to be used for debug purpose.
-    
-    [..]          
-      Once the device started from reset, the user application has to:        
-      (+) Configure the clock source to be used to drive the System clock
-          (if the application needs higher frequency/performance)
-      (+) Configure the System clock frequency and Flash settings  
-      (+) Configure the AHB and APB busses prescalers
-      (+) Enable the clock for the peripheral(s) to be used
-      (+) Configure the clock source(s) for peripherals which clocks are not
-          derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
-
-                      ##### RCC Limitations #####
-  ==============================================================================
-    [..]  
-      A delay between an RCC peripheral clock enable and the effective peripheral 
-      enabling should be taken into account in order to manage the peripheral read/write 
-      from/to registers.
-      (+) This delay depends on the peripheral mapping.
-      (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle 
-          after the clock enable bit is set on the hardware register
-      (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle 
-          after the clock enable bit is set on the hardware register
-
-    [..]  
-      Implemented Workaround:
-      (+) For AHB & APB peripherals, a dummy read to the peripheral register has been
-          inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup RCC RCC
-  * @brief RCC HAL module driver
-  * @{
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup RCC_Private_Constants
-  * @{
-  */
-#define CLOCKSWITCH_TIMEOUT_VALUE  ((uint32_t)5000U) /* 5 s    */
-
-/* Private macro -------------------------------------------------------------*/
-#define __MCO1_CLK_ENABLE()   __HAL_RCC_GPIOA_CLK_ENABLE()
-#define MCO1_GPIO_PORT        GPIOA
-#define MCO1_PIN              GPIO_PIN_8 
-
-#define __MCO2_CLK_ENABLE()   __HAL_RCC_GPIOC_CLK_ENABLE()
-#define MCO2_GPIO_PORT         GPIOC
-#define MCO2_PIN               GPIO_PIN_9
-/**
-  * @}
-  */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup RCC_Private_Variables RCC Private Variables
-  * @{
-  */    
-const uint8_t APBAHBPrescTable[16] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup RCC_Exported_Functions RCC Exported Functions
-  *  @{
-  */
-
-/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions 
- *
-@verbatim    
- ===============================================================================
-           ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]
-      This section provides functions allowing to configure the internal/external oscillators
-      (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1 
-       and APB2).
-
-    [..] Internal/external clock and PLL configuration
-         (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
-             the PLL as System clock source.
-
-         (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
-             clock source.
-
-         (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
-             through the PLL as System clock source. Can be used also as RTC clock source.
-
-         (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.   
-
-         (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
-           (++) The first output is used to generate the high speed system clock (up to 168 MHz)
-           (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
-                the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
-
-         (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
-             and if a HSE clock failure occurs(HSE used directly or through PLL as System 
-             clock source), the System clocks automatically switched to HSI and an interrupt
-             is generated if enabled. The interrupt is linked to the Cortex-M4 NMI 
-             (Non-Maskable Interrupt) exception vector.   
-
-         (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
-             clock (through a configurable prescaler) on PA8 pin.
-
-         (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
-             clock (through a configurable prescaler) on PC9 pin.
-
-    [..] System, AHB and APB busses clocks configuration  
-         (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
-             HSE and PLL.
-             The AHB clock (HCLK) is derived from System clock through configurable 
-             prescaler and used to clock the CPU, memory and peripherals mapped 
-             on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived 
-             from AHB clock through configurable prescalers and used to clock 
-             the peripherals mapped on these busses. You can use 
-             "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.  
-
-         (#) For the STM32F405xx/07xx and STM32F415xx/17xx devices, the maximum
-             frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz. 
-             Depending on the device voltage range, the maximum frequency should
-             be adapted accordingly (refer to the product datasheets for more details).
-
-         (#) For the STM32F42xxx, STM32F43xxx, STM32F446xx, STM32F469xx and STM32F479xx devices,
-             the maximum frequency of the SYSCLK and HCLK is 180 MHz, PCLK2 90 MHz and PCLK1 45 MHz. 
-             Depending on the device voltage range, the maximum frequency should
-             be adapted accordingly (refer to the product datasheets for more details).
-             
-         (#) For the STM32F401xx, the maximum frequency of the SYSCLK and HCLK is 84 MHz,
-             PCLK2 84 MHz and PCLK1 42 MHz. 
-             Depending on the device voltage range, the maximum frequency should
-             be adapted accordingly (refer to the product datasheets for more details).
-             
-         (#) For the STM32F41xxx, the maximum frequency of the SYSCLK and HCLK is 100 MHz,
-             PCLK2 100 MHz and PCLK1 50 MHz. 
-             Depending on the device voltage range, the maximum frequency should
-             be adapted accordingly (refer to the product datasheets for more details).
-             
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Resets the RCC clock configuration to the default reset state.
-  * @note   The default reset state of the clock configuration is given below:
-  *            - HSI ON and used as system clock source
-  *            - HSE and PLL OFF
-  *            - AHB, APB1 and APB2 prescaler set to 1.
-  *            - CSS, MCO1 and MCO2 OFF
-  *            - All interrupts disabled
-  * @note   This function doesn't modify the configuration of the
-  *            - Peripheral clocks  
-  *            - LSI, LSE and RTC clocks 
-  * @retval None
-  */
-__weak void HAL_RCC_DeInit(void)
-{}
-
-/**
-  * @brief  Initializes the RCC Oscillators according to the specified parameters in the
-  *         RCC_OscInitTypeDef.
-  * @param  RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
-  *         contains the configuration information for the RCC Oscillators.
-  * @note   The PLL is not disabled when used as system clock.
-  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
-  *         supported by this API. User should request a transition to LSE Off
-  *         first and then LSE On or LSE Bypass.
-  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
-  *         supported by this API. User should request a transition to HSE Off
-  *         first and then HSE On or HSE Bypass.
-  * @retval HAL status
-  */
-__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
-{
- uint32_t tickstart = 0U;  
- 
-  /* Check the parameters */
-  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
-  /*------------------------------- HSE Configuration ------------------------*/ 
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
-    /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
-    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
-      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
-    {
-      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
-      {
-        return HAL_ERROR;
-      }
-    }
-    else
-    {
-      /* Set the new HSE configuration ---------------------------------------*/
-      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
-      
-      /* Check the HSE State */
-      if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
-      {
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-      
-        /* Wait till HSE is ready */  
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          } 
-        }
-      }
-      else
-      {
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-
-        /* Wait till HSE is bypassed or disabled */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          } 
-        }
-      }
-    }
-  }
-  /*----------------------------- HSI Configuration --------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
-    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
-    
-    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
-    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
-      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
-    {
-      /* When HSI is used as system clock it will not disabled */
-      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
-      {
-        return HAL_ERROR;
-      }
-      /* Otherwise, just the calibration is allowed */
-      else
-      {
-        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
-        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
-      }
-    }
-    else
-    {
-      /* Check the HSI State */
-      if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
-      {
-        /* Enable the Internal High Speed oscillator (HSI). */
-        __HAL_RCC_HSI_ENABLE();
-
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-
-        /* Wait till HSI is ready */  
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }       
-        } 
-                
-        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
-        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
-      }
-      else
-      {
-        /* Disable the Internal High Speed oscillator (HSI). */
-        __HAL_RCC_HSI_DISABLE();
-
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-      
-        /* Wait till HSI is ready */  
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          } 
-        } 
-      }
-    }
-  }
-  /*------------------------------ LSI Configuration -------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
-
-    /* Check the LSI State */
-    if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
-    {
-      /* Enable the Internal Low Speed oscillator (LSI). */
-      __HAL_RCC_LSI_ENABLE();
-      
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
-      
-      /* Wait till LSI is ready */
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
-      {
-        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        } 
-      }
-    }
-    else
-    {
-      /* Disable the Internal Low Speed oscillator (LSI). */
-      __HAL_RCC_LSI_DISABLE();
-      
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
-      
-      /* Wait till LSI is ready */  
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
-      {
-        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }       
-      } 
-    }
-  }
-  /*------------------------------ LSE Configuration -------------------------*/ 
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
-    
-    /* Enable Power Clock*/
-    __HAL_RCC_PWR_CLK_ENABLE();
-    
-    /* Enable write access to Backup domain */
-    PWR->CR |= PWR_CR_DBP;
-    
-    /* Wait for Backup domain Write protection enable */
-    tickstart = HAL_GetTick();
-    
-    while((PWR->CR & PWR_CR_DBP) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
-      {
-        return HAL_TIMEOUT;
-      }      
-    }
-
-    /* Set the new LSE configuration -----------------------------------------*/
-    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
-    /* Check the LSE State */
-    if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
-    {
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
-      
-      /* Wait till LSE is ready */  
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
-      {
-        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }       
-      }
-    }
-    else
-    {
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
-      
-      /* Wait till LSE is ready */  
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
-      {
-        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }       
-      }
-    }
-  }
-  /*-------------------------------- PLL Configuration -----------------------*/
-  /* Check the parameters */
-  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
-  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
-  {
-    /* Check if the PLL is used as system clock or not */
-    if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
-    { 
-      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
-      {
-        /* Check the parameters */
-        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
-        assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
-        assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
-        assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
-        assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
-      
-        /* Disable the main PLL. */
-        __HAL_RCC_PLL_DISABLE();
-        
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-        
-        /* Wait till PLL is ready */  
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }        
-
-        /* Configure the main PLL clock source, multiplication and division factors. */
-        WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource                                            | \
-                                 RCC_OscInitStruct->PLL.PLLM                                                 | \
-                                 (RCC_OscInitStruct->PLL.PLLN << POSITION_VAL(RCC_PLLCFGR_PLLN))             | \
-                                 (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
-                                 (RCC_OscInitStruct->PLL.PLLQ << POSITION_VAL(RCC_PLLCFGR_PLLQ))));
-        /* Enable the main PLL. */
-        __HAL_RCC_PLL_ENABLE();
-
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-        
-        /* Wait till PLL is ready */  
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          } 
-        }
-      }
-      else
-      {
-        /* Disable the main PLL. */
-        __HAL_RCC_PLL_DISABLE();
- 
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-        
-        /* Wait till PLL is ready */  
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }
-    else
-    {
-      return HAL_ERROR;
-    }
-  }
-  return HAL_OK;
-}
- 
-/**
-  * @brief  Initializes the CPU, AHB and APB busses clocks according to the specified 
-  *         parameters in the RCC_ClkInitStruct.
-  * @param  RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
-  *         contains the configuration information for the RCC peripheral.
-  * @param  FLatency: FLASH Latency, this parameter depend on device selected
-  * 
-  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency 
-  *         and updated by HAL_RCC_GetHCLKFreq() function called within this function
-  *
-  * @note   The HSI is used (enabled by hardware) as system clock source after
-  *         startup from Reset, wake-up from STOP and STANDBY mode, or in case
-  *         of failure of the HSE used directly or indirectly as system clock
-  *         (if the Clock Security System CSS is enabled).
-  *           
-  * @note   A switch from one clock source to another occurs only if the target
-  *         clock source is ready (clock stable after startup delay or PLL locked). 
-  *         If a clock source which is not yet ready is selected, the switch will
-  *         occur when the clock source will be ready. 
-  *           
-  * @note   Depending on the device voltage range, the software has to set correctly
-  *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
-  *         (for more details refer to section above "Initialization/de-initialization functions")
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
-{
-  uint32_t tickstart = 0U;   
- 
-  /* Check the parameters */
-  assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
-  assert_param(IS_FLASH_LATENCY(FLatency));
- 
-  /* To correctly read data from FLASH memory, the number of wait states (LATENCY) 
-    must be correctly programmed according to the frequency of the CPU clock 
-    (HCLK) and the supply voltage of the device. */
-  
-  /* Increasing the number of wait states because of higher CPU frequency */
-  if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
-  {    
-    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
-    __HAL_FLASH_SET_LATENCY(FLatency);
-    
-    /* Check that the new number of wait states is taken into account to access the Flash
-    memory by reading the FLASH_ACR register */
-    if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
-    {
-      return HAL_ERROR;
-    }
-  }
- 
-  /*-------------------------- HCLK Configuration --------------------------*/
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
-  {
-    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
-  }
-  
-  /*------------------------- SYSCLK Configuration ---------------------------*/ 
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
-  {    
-    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
-    
-    /* HSE is selected as System Clock Source */
-    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
-    {
-      /* Check the HSE ready flag */  
-      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
-      {
-        return HAL_ERROR;
-      }
-    }
-    /* PLL is selected as System Clock Source */
-    else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)   || 
-            (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
-    {
-      /* Check the PLL ready flag */  
-      if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
-      {
-        return HAL_ERROR;
-      }
-    }
-    /* HSI is selected as System Clock Source */
-    else
-    {
-      /* Check the HSI ready flag */  
-      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
-      {
-        return HAL_ERROR;
-      }
-    }
-    
-    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
-    /* Get Start Tick*/
-    tickstart = HAL_GetTick();
-    
-    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
-    {
-      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
-      {
-        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
-    {
-      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
-      {
-        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)
-    {
-      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLRCLK)
-      {
-        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-    else
-    {
-      while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
-      {
-        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }    
-  
-  /* Decreasing the number of wait states because of lower CPU frequency */
-  if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
-  { 
-     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
-    __HAL_FLASH_SET_LATENCY(FLatency);
-    
-    /* Check that the new number of wait states is taken into account to access the Flash
-    memory by reading the FLASH_ACR register */
-    if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
-    {
-      return HAL_ERROR;
-    }
- }
-
-  /*-------------------------- PCLK1 Configuration ---------------------------*/ 
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
-  {
-    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
-  }
-  
-  /*-------------------------- PCLK2 Configuration ---------------------------*/ 
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
-  {
-    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
-  }
-
-  /* Update the SystemCoreClock global variable */
-  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
-
-  /* Configure the source of time base considering new system clocks settings*/
-  HAL_InitTick (TICK_INT_PRIORITY);
-  
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions 
- *  @brief   RCC clocks control functions 
- *
-@verbatim   
- ===============================================================================
-                      ##### Peripheral Control functions #####
- ===============================================================================  
-    [..]
-    This subsection provides a set of functions allowing to control the RCC Clocks 
-    frequencies.
-      
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
-  * @note   PA8/PC9 should be configured in alternate function mode.
-  * @param  RCC_MCOx: specifies the output direction for the clock source.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
-  *            @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
-  * @param  RCC_MCOSource: specifies the clock source to output.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
-  *            @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
-  *            @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
-  *            @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
-  *            @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
-  *            @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx 
-  *            @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices   
-  *            @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
-  *            @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
-  * @param  RCC_MCODiv: specifies the MCOx prescaler.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_MCODIV_1: no division applied to MCOx clock
-  *            @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
-  *            @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
-  *            @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
-  *            @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
-  * @note  For STM32F410Rx devices to output I2SCLK clock on MCO2 you should have
-  *        at last one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
-  * @retval None
-  */
-void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
-{
-  GPIO_InitTypeDef GPIO_InitStruct;
-  /* Check the parameters */
-  assert_param(IS_RCC_MCO(RCC_MCOx));
-  assert_param(IS_RCC_MCODIV(RCC_MCODiv));
-  /* RCC_MCO1 */
-  if(RCC_MCOx == RCC_MCO1)
-  {
-    assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
-    
-    /* MCO1 Clock Enable */
-    __MCO1_CLK_ENABLE();
-    
-    /* Configure the MCO1 pin in alternate function mode */    
-    GPIO_InitStruct.Pin = MCO1_PIN;
-    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
-    GPIO_InitStruct.Pull = GPIO_NOPULL;
-    GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
-    HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
-    
-    /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
-    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
-    
-   /* This RCC MCO1 enable feature is available only on STM32F410xx devices */
-#if defined(RCC_CFGR_MCO1EN)
-    __HAL_RCC_MCO1_ENABLE();
-#endif /* RCC_CFGR_MCO1EN */    
-  }
-#if defined(RCC_CFGR_MCO2)
-  else
-  {
-    assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
-    
-    /* MCO2 Clock Enable */
-    __MCO2_CLK_ENABLE();
-    
-    /* Configure the MCO2 pin in alternate function mode */
-    GPIO_InitStruct.Pin = MCO2_PIN;
-    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
-    GPIO_InitStruct.Pull = GPIO_NOPULL;
-    GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
-    HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
-    
-    /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */
-    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3U)));
-
-   /* This RCC MCO2 enable feature is available only on STM32F410Rx devices */
-#if defined(RCC_CFGR_MCO2EN)
-    __HAL_RCC_MCO2_ENABLE();
-#endif /* RCC_CFGR_MCO2EN */
-  }
-#endif /* RCC_CFGR_MCO2 */
-}
-
-/**
-  * @brief  Enables the Clock Security System.
-  * @note   If a failure is detected on the HSE oscillator clock, this oscillator
-  *         is automatically disabled and an interrupt is generated to inform the
-  *         software about the failure (Clock Security System Interrupt, CSSI),
-  *         allowing the MCU to perform rescue operations. The CSSI is linked to 
-  *         the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.  
-  * @retval None
-  */
-void HAL_RCC_EnableCSS(void)
-{
-  *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
-}
-
-/**
-  * @brief  Disables the Clock Security System.
-  * @retval None
-  */
-void HAL_RCC_DisableCSS(void)
-{
-  *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
-}
-
-/**
-  * @brief  Returns the SYSCLK frequency
-  *        
-  * @note   The system frequency computed by this function is not the real 
-  *         frequency in the chip. It is calculated based on the predefined 
-  *         constant and the selected clock source:
-  * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
-  * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
-  * @note     If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) 
-  *           or HSI_VALUE(*) multiplied/divided by the PLL factors.         
-  * @note     (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
-  *               16 MHz) but the real value may vary depending on the variations
-  *               in voltage and temperature.
-  * @note     (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
-  *                25 MHz), user has to ensure that HSE_VALUE is same as the real
-  *                frequency of the crystal used. Otherwise, this function may
-  *                have wrong result.
-  *                  
-  * @note   The result of this function could be not correct when using fractional
-  *         value for HSE crystal.
-  *           
-  * @note   This function can be used by the user application to compute the 
-  *         baudrate for the communication peripherals or configure other parameters.
-  *           
-  * @note   Each time SYSCLK changes, this function must be called to update the
-  *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
-  *         
-  *               
-  * @retval SYSCLK frequency
-  */
-__weak uint32_t HAL_RCC_GetSysClockFreq(void)
-{
-  uint32_t pllm = 0U, pllvco = 0U, pllp = 0U;
-  uint32_t sysclockfreq = 0U;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  switch (RCC->CFGR & RCC_CFGR_SWS)
-  {
-    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
-    {
-      sysclockfreq = HSI_VALUE;
-       break;
-    }
-    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
-    {
-      sysclockfreq = HSE_VALUE;
-      break;
-    }
-    case RCC_CFGR_SWS_PLL:  /* PLL used as system clock  source */
-    {
-      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
-      SYSCLK = PLL_VCO / PLLP */
-      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
-      if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
-      {
-        /* HSE used as PLL clock source */
-        //pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
-        // dpgeorge: Adjust the way the arithmetic is done so it retains
-        // precision for the case that pllm doesn't evenly divide HSE_VALUE.
-        // Must be sure not to overflow, so divide by 4 first.  HSE_VALUE
-        // should be a multiple of 4 (being a multiple of 100 is enough).
-        pllvco = ((HSE_VALUE / 4) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))) / pllm * 4;
-      }
-      else
-      {
-        /* HSI used as PLL clock source */
-        pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));    
-      }
-      pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1U) *2U);
-      
-      sysclockfreq = pllvco/pllp;
-      break;
-    }
-    default:
-    {
-      sysclockfreq = HSI_VALUE;
-      break;
-    }
-  }
-  return sysclockfreq;
-}
-
-/**
-  * @brief  Returns the HCLK frequency     
-  * @note   Each time HCLK changes, this function must be called to update the
-  *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.
-  * 
-  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency 
-  *         and updated within this function
-  * @retval HCLK frequency
-  */
-uint32_t HAL_RCC_GetHCLKFreq(void)
-{
-  return SystemCoreClock;
-}
-
-/**
-  * @brief  Returns the PCLK1 frequency     
-  * @note   Each time PCLK1 changes, this function must be called to update the
-  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
-  * @retval PCLK1 frequency
-  */
-uint32_t HAL_RCC_GetPCLK1Freq(void)
-{  
-  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
-  return (HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
-}
-
-/**
-  * @brief  Returns the PCLK2 frequency     
-  * @note   Each time PCLK2 changes, this function must be called to update the
-  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
-  * @retval PCLK2 frequency
-  */
-uint32_t HAL_RCC_GetPCLK2Freq(void)
-{
-  /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
-  return (HAL_RCC_GetHCLKFreq()>> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
-} 
-
-/**
-  * @brief  Configures the RCC_OscInitStruct according to the internal 
-  * RCC configuration registers.
-  * @param  RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that 
-  * will be configured.
-  * @retval None
-  */
-__weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
-{
-  /* Set all possible values for the Oscillator type parameter ---------------*/
-  RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
-  
-  /* Get the HSE configuration -----------------------------------------------*/
-  if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
-  {
-    RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
-  }
-  else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
-  {
-    RCC_OscInitStruct->HSEState = RCC_HSE_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
-  }
-  
-  /* Get the HSI configuration -----------------------------------------------*/
-  if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
-  {
-    RCC_OscInitStruct->HSIState = RCC_HSI_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
-  }
-  
-  RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
-  
-  /* Get the LSE configuration -----------------------------------------------*/
-  if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
-  {
-    RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
-  }
-  else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
-  {
-    RCC_OscInitStruct->LSEState = RCC_LSE_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
-  }
-  
-  /* Get the LSI configuration -----------------------------------------------*/
-  if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
-  {
-    RCC_OscInitStruct->LSIState = RCC_LSI_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
-  }
-  
-  /* Get the PLL configuration -----------------------------------------------*/
-  if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
-  {
-    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
-  }
-  RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
-  RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
-  RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
-  RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> POSITION_VAL(RCC_PLLCFGR_PLLP));
-  RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ));
-}
-
-/**
-  * @brief  Configures the RCC_ClkInitStruct according to the internal 
-  * RCC configuration registers.
-  * @param  RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that 
-  * will be configured.
-  * @param  pFLatency: Pointer on the Flash Latency.
-  * @retval None
-  */
-void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
-{
-  /* Set all possible values for the Clock type parameter --------------------*/
-  RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
-   
-  /* Get the SYSCLK configuration --------------------------------------------*/ 
-  RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
-  
-  /* Get the HCLK configuration ----------------------------------------------*/ 
-  RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); 
-  
-  /* Get the APB1 configuration ----------------------------------------------*/ 
-  RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);   
-  
-  /* Get the APB2 configuration ----------------------------------------------*/ 
-  RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U);
-  
-  /* Get the Flash Wait State (Latency) configuration ------------------------*/   
-  *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); 
-}
-
-/**
-  * @brief This function handles the RCC CSS interrupt request.
-  * @note This API should be called under the NMI_Handler().
-  * @retval None
-  */
-void HAL_RCC_NMI_IRQHandler(void)
-{
-  /* Check RCC CSSF flag  */
-  if(__HAL_RCC_GET_IT(RCC_IT_CSS))
-  {
-    /* RCC Clock Security System interrupt user callback */
-    HAL_RCC_CSSCallback();
-
-    /* Clear RCC CSS pending bit */
-    __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
-  }
-}
-
-/**
-  * @brief  RCC Clock Security System interrupt callback
-  * @retval None
-  */
-__weak void HAL_RCC_CSSCallback(void)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_RCC_CSSCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_RCC_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_rcc_ex.c b/stmhal/hal/f4/src/stm32f4xx_hal_rcc_ex.c
deleted file mode 100644
index 2f36a0e193..0000000000
--- a/stmhal/hal/f4/src/stm32f4xx_hal_rcc_ex.c
+++ /dev/null
@@ -1,2603 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_rcc_ex.c
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   Extension RCC HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities RCC extension peripheral:
-  *           + Extended Peripheral Control functions
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup RCCEx RCCEx
-  * @brief RCCEx HAL module driver
-  * @{
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup RCCEx_Private_Constants
-  * @{
-  */
-/**
-  * @}
-  */ 
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
-  *  @{
-  */
-
-/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions 
- *  @brief  Extended Peripheral Control functions  
- *
-@verbatim   
- ===============================================================================
-                ##### Extended Peripheral Control functions  #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to control the RCC Clocks 
-    frequencies.
-    [..] 
-    (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
-        select the RTC clock source; in this case the Backup domain will be reset in  
-        order to modify the RTC Clock source, as consequence RTC registers (including 
-        the backup registers) and RCC_BDCR register are set to their reset values.
-      
-@endverbatim
-  * @{
-  */
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
-    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
-    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
-    defined(STM32F412Rx) || defined(STM32F412Cx)
-/**
-  * @brief  Resets the RCC clock configuration to the default reset state.
-  * @note   The default reset state of the clock configuration is given below:
-  *            - HSI ON and used as system clock source
-  *            - HSE, PLL and PLLI2S OFF
-  *            - AHB, APB1 and APB2 prescaler set to 1.
-  *            - CSS, MCO1 and MCO2 OFF
-  *            - All interrupts disabled
-  * @note   This function doesn't modify the configuration of the
-  *            - Peripheral clocks  
-  *            - LSI, LSE and RTC clocks 
-  * @retval None
-  */
-void HAL_RCC_DeInit(void)
-{
-  /* Set HSION bit */
-  SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4); 
-  
-  /* Reset CFGR register */
-  CLEAR_REG(RCC->CFGR);
-  
-  /* Reset HSEON, CSSON, PLLON, PLLI2S */
-  CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON| RCC_CR_PLLI2SON); 
-  
-  /* Reset PLLCFGR register */
-  CLEAR_REG(RCC->PLLCFGR);
-  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2); 
-  
-  /* Reset PLLI2SCFGR register */
-  CLEAR_REG(RCC->PLLI2SCFGR);
-  SET_BIT(RCC->PLLI2SCFGR,  RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1);
-  
-  /* Reset HSEBYP bit */
-  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
-  
-  /* Disable all interrupts */
-  CLEAR_REG(RCC->CIR);
-  
-  /* Update the SystemCoreClock global variable */
-  SystemCoreClock = HSI_VALUE;
-}
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
-          STM32F412Rx || STM32F412Cx */
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-/**
-  * @brief  Resets the RCC clock configuration to the default reset state.
-  * @note   The default reset state of the clock configuration is given below:
-  *            - HSI ON and used as system clock source
-  *            - HSE and PLL OFF
-  *            - AHB, APB1 and APB2 prescaler set to 1.
-  *            - CSS, MCO1 and MCO2 OFF
-  *            - All interrupts disabled
-  * @note   This function doesn't modify the configuration of the
-  *            - Peripheral clocks  
-  *            - LSI, LSE and RTC clocks 
-  * @retval None
-  */
-void HAL_RCC_DeInit(void)
-{
-  /* Set HSION bit */
-  SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4); 
-  
-  /* Reset CFGR register */
-  CLEAR_REG(RCC->CFGR);
-  
-  /* Reset HSEON, CSSON, PLLON */
-  CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON); 
-  
-  /* Reset PLLCFGR register */
-  CLEAR_REG(RCC->PLLCFGR);
-  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR_1 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2); 
-  
-  /* Reset HSEBYP bit */
-  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
-  
-  /* Disable all interrupts */
-  CLEAR_REG(RCC->CIR);
-  
-  /* Update the SystemCoreClock global variable */
-  SystemCoreClock = HSI_VALUE;
-}
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-
-#if defined(STM32F446xx) 
-/**
-  * @brief  Initializes the RCC extended peripherals clocks according to the specified
-  *         parameters in the RCC_PeriphCLKInitTypeDef.
-  * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
-  *         contains the configuration information for the Extended Peripherals
-  *         clocks(I2S, SAI, LTDC RTC and TIM).
-  *         
-  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select 
-  *         the RTC clock source; in this case the Backup domain will be reset in  
-  *         order to modify the RTC Clock source, as consequence RTC registers (including 
-  *         the backup registers) and RCC_BDCR register are set to their reset values.
-  *
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
-{
-  uint32_t tickstart = 0U;
-  uint32_t tmpreg1 = 0U;
-  uint32_t plli2sp = 0U;
-  uint32_t plli2sq = 0U;
-  uint32_t plli2sr = 0U;
-  uint32_t pllsaip = 0U;
-  uint32_t pllsaiq = 0U;
-  uint32_t plli2sused = 0U;
-  uint32_t pllsaiused = 0U;
-    
-  /* Check the peripheral clock selection parameters */
-  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
-     
-  /*------------------------ I2S APB1 configuration --------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1))
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection));
-    
-    /* Configure I2S Clock source */
-    __HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection);
-    /* Enable the PLLI2S when it's used as clock source for I2S */
-    if(PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)
-    {
-      plli2sused = 1U; 
-    }
-  }
-  /*--------------------------------------------------------------------------*/
-    
-  /*---------------------------- I2S APB2 configuration ----------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2))
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection));
-    
-    /* Configure I2S Clock source */
-    __HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection);
-    /* Enable the PLLI2S when it's used as clock source for I2S */
-    if(PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)
-    {
-      plli2sused = 1U; 
-    }
-  }
-  /*--------------------------------------------------------------------------*/
-    
-  /*--------------------------- SAI1 configuration ---------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
-    
-    /* Configure SAI1 Clock source */
-    __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
-    /* Enable the PLLI2S when it's used as clock source for SAI */
-    if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
-    {
-      plli2sused = 1U; 
-    }
-    /* Enable the PLLSAI when it's used as clock source for SAI */
-    if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
-    {
-      pllsaiused = 1U; 
-    }
-  }
-  /*--------------------------------------------------------------------------*/
-    
-  /*-------------------------- SAI2 configuration ----------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
-    
-    /* Configure SAI2 Clock source */
-    __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
-    
-    /* Enable the PLLI2S when it's used as clock source for SAI */
-    if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
-    {
-      plli2sused = 1U; 
-    }
-    /* Enable the PLLSAI when it's used as clock source for SAI */
-    if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
-    {
-      pllsaiused = 1U; 
-    }
-  }
-  /*--------------------------------------------------------------------------*/
-    
-  /*----------------------------- RTC configuration --------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
-  {
-    /* Check for RTC Parameters used to output RTCCLK */
-    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
-    
-    /* Enable Power Clock*/
-    __HAL_RCC_PWR_CLK_ENABLE();
-    
-    /* Enable write access to Backup domain */
-    PWR->CR |= PWR_CR_DBP;
-    
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    
-    while((PWR->CR & PWR_CR_DBP) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ 
-    tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
-    if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
-    {
-      /* Store the content of BDCR register before the reset of Backup Domain */
-      tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
-      /* RTC Clock selection can be changed only if the Backup Domain is reset */
-      __HAL_RCC_BACKUPRESET_FORCE();
-      __HAL_RCC_BACKUPRESET_RELEASE();
-      /* Restore the Content of BDCR register */
-      RCC->BDCR = tmpreg1;
-
-      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
-      if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
-      {
-        /* Get tick */
-        tickstart = HAL_GetTick();
-        
-        /* Wait till LSE is ready */  
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }
-    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
-  }
-  /*--------------------------------------------------------------------------*/
-    
-  /*---------------------------- TIM configuration ---------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
-  {
-    /* Configure Timer Prescaler */
-    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
-  }
-  /*--------------------------------------------------------------------------*/
-    
-  /*---------------------------- FMPI2C1 Configuration -----------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
-    
-    /* Configure the FMPI2C1 clock source */
-    __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
-  }
-  /*--------------------------------------------------------------------------*/
-    
-  /*------------------------------ CEC Configuration -------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
-    
-    /* Configure the CEC clock source */
-    __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
-  }
-  /*--------------------------------------------------------------------------*/
-    
-  /*----------------------------- CLK48 Configuration ------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
-    
-    /* Configure the CLK48 clock source */
-    __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
-
-    /* Enable the PLLSAI when it's used as clock source for CLK48 */
-    if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)
-    {
-      pllsaiused = 1U; 
-    }
-  }
-  /*--------------------------------------------------------------------------*/
-    
-  /*----------------------------- SDIO Configuration -------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
-    
-    /* Configure the SDIO clock source */
-    __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
-  }
-  /*--------------------------------------------------------------------------*/
-    
-  /*------------------------------ SPDIFRX Configuration ---------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifClockSelection));
-    
-    /* Configure the SPDIFRX clock source */
-    __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifClockSelection);
-    /* Enable the PLLI2S when it's used as clock source for SPDIFRX */
-    if(PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP)
-    {
-      plli2sused = 1U; 
-    }
-  }
-  /*--------------------------------------------------------------------------*/
-    
-  /*---------------------------- PLLI2S Configuration ------------------------*/
-  /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S on APB1,
-     I2S on APB2 or SPDIFRX */
-  if((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
-  {
-    /* Disable the PLLI2S */
-    __HAL_RCC_PLLI2S_DISABLE();    
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    /* Wait till PLLI2S is disabled */
-    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
-      {
-        /* return in case of Timeout detected */
-        return HAL_TIMEOUT;
-      } 
-    }
-    
-    /* check for common PLLI2S Parameters */
-    assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
-    assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
-      
-    /*------ In Case of PLLI2S is selected as source clock for I2S -----------*/ 
-    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) ||
-       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)))
-    {
-      /* check for Parameters */
-      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
-    
-      /* Read PLLI2SP/PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
-      plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1U) << 1U);
-      plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
-      /* Configure the PLLI2S division factors */
-      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
-      /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
-      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, plli2sq, PeriphClkInit->PLLI2S.PLLI2SR);
-    }
-  
-    /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/  
-    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
-       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) 
-    {
-      /* Check for PLLI2S Parameters */
-      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
-      /* Check for PLLI2S/DIVQ parameters */
-      assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
-            
-      /* Read PLLI2SP/PLLI2SR value from PLLI2SCFGR register (this value is not needed for SAI configuration) */
-      plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1U) << 1U);
-      plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
-      /* Configure the PLLI2S division factors */      
-      /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */
-      /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
-      /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
-      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, PeriphClkInit->PLLI2S.PLLI2SQ, plli2sr);
-   
-      /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ 
-      __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);   
-    }          
-
-    /*------ In Case of PLLI2S is selected as source clock for SPDIFRX -------*/  
-    if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) && (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
-    {
-      /* check for Parameters */
-      assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
-      /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
-      plli2sq = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1U) << 1U);
-      plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
-      /* Configure the PLLI2S division factors */
-      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
-      /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
-      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, plli2sq, plli2sr);
-    } 
-    
-     /*----------------- In Case of PLLI2S is just selected  -----------------*/  
-    if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
-    {
-      /* Check for Parameters */
-      assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
-      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
-      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
-
-      /* Configure the PLLI2S division factors */
-      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
-      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
-    }    
-   
-    /* Enable the PLLI2S */
-    __HAL_RCC_PLLI2S_ENABLE();
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    /* Wait till PLLI2S is ready */
-    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
-      {
-        /* return in case of Timeout detected */
-        return HAL_TIMEOUT;
-      }
-    }
-  } 
-  /*--------------------------------------------------------------------------*/
-    
-  /*----------------------------- PLLSAI Configuration -----------------------*/
-  /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, CLK48 or SDIO */
-  if(pllsaiused == 1U)
-  {
-    /* Disable PLLSAI Clock */
-    __HAL_RCC_PLLSAI_DISABLE(); 
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    /* Wait till PLLSAI is disabled */
-    while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
-      { 
-        /* return in case of Timeout detected */
-        return HAL_TIMEOUT;
-      }
-    }
-    
-    /* Check the PLLSAI division factors */
-    assert_param(IS_RCC_PLLSAIM_VALUE(PeriphClkInit->PLLSAI.PLLSAIM));
-    assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
-    
-    /*------ In Case of PLLSAI is selected as source clock for SAI -----------*/  
-    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||
-       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
-    {
-      /* check for PLLSAIQ Parameter */
-      assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
-      /* check for PLLSAI/DIVQ Parameter */
-      assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
-    
-      /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
-      pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1U) << 1U);
-      /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
-      /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
-      /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
-      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, 0U);
-      
-      /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ 
-      __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
-    }           
-
-    /*------ In Case of PLLSAI is selected as source clock for CLK48 ---------*/   
-    /* In Case of PLLI2S is selected as source clock for CLK48 */ 
-    if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP))
-    {
-      /* check for Parameters */
-      assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
-      /* Read PLLSAIQ value from PLLI2SCFGR register (this value is not need for SAI configuration) */
-      pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
-      /* Configure the PLLSAI division factors */
-      /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLI2SN/PLLSAIM) */
-      /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
-      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, 0U);
-    }        
-
-    /* Enable PLLSAI Clock */
-    __HAL_RCC_PLLSAI_ENABLE();
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    /* Wait till PLLSAI is ready */
-    while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
-      { 
-        /* return in case of Timeout detected */
-        return HAL_TIMEOUT;
-      }
-    }  
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Get the RCC_PeriphCLKInitTypeDef according to the internal
-  *         RCC configuration registers.
-  * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that 
-  *         will be configured.
-  * @retval None
-  */
-void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
-{
-  uint32_t tempreg;
-  
-  /* Set all possible values for the extended clock type parameter------------*/
-  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 | RCC_PERIPHCLK_I2S_APB2 |\
-                                        RCC_PERIPHCLK_SAI1     | RCC_PERIPHCLK_SAI2     |\
-                                        RCC_PERIPHCLK_TIM      | RCC_PERIPHCLK_RTC      |\
-                                        RCC_PERIPHCLK_CEC      | RCC_PERIPHCLK_FMPI2C1  |\
-                                        RCC_PERIPHCLK_CLK48     | RCC_PERIPHCLK_SDIO     |\
-                                        RCC_PERIPHCLK_SPDIFRX;
-  
-  /* Get the PLLI2S Clock configuration --------------------------------------*/
-  PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SM));
-  PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
-  PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1U) << 1U);
-  PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
-  PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
-  /* Get the PLLSAI Clock configuration --------------------------------------*/
-  PeriphClkInit->PLLSAI.PLLSAIM = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIM));
-  PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
-  PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1U) << 1U);
-  PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)); 
-  /* Get the PLLSAI/PLLI2S division factors ----------------------------------*/
-  PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ));
-  PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ));
-
-  /* Get the SAI1 clock configuration ----------------------------------------*/
-  PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
-  
-  /* Get the SAI2 clock configuration ----------------------------------------*/
-  PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
-  
-  /* Get the I2S APB1 clock configuration ------------------------------------*/
-  PeriphClkInit->I2sApb1ClockSelection = __HAL_RCC_GET_I2S_APB1_SOURCE();
-  
-  /* Get the I2S APB2 clock configuration ------------------------------------*/
-  PeriphClkInit->I2sApb2ClockSelection = __HAL_RCC_GET_I2S_APB2_SOURCE();
-  
-  /* Get the RTC Clock configuration -----------------------------------------*/
-  tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
-  PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
-  
-  /* Get the CEC clock configuration -----------------------------------------*/
-  PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
-  
-  /* Get the FMPI2C1 clock configuration -------------------------------------*/
-  PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE();
-  
-  /* Get the CLK48 clock configuration ----------------------------------------*/
-  PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
-  
-  /* Get the SDIO clock configuration ----------------------------------------*/
-  PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE();
-  
-  /* Get the SPDIFRX clock configuration -------------------------------------*/
-  PeriphClkInit->SpdifClockSelection = __HAL_RCC_GET_SPDIFRX_SOURCE();
-  
-  /* Get the TIM Prescaler configuration -------------------------------------*/
-  if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
-  {
-    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
-  }
-  else
-  {
-    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
-  }
-}
-
-/**
-  * @brief  Return the peripheral clock frequency for a given peripheral(SAI..) 
-  * @note   Return 0 if peripheral clock identifier not managed by this API
-  * @param  PeriphClk: Peripheral clock identifier
-  *         This parameter can be one of the following values:
-  *            @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock
-  *            @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock
-  * @retval Frequency in KHz
-  */
-uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
-{
-  uint32_t tmpreg1 = 0U;
-  /* This variable used to store the SAI clock frequency (value in Hz) */
-  uint32_t frequency = 0U;
-  /* This variable used to store the VCO Input (value in Hz) */
-  uint32_t vcoinput = 0U;
-  /* This variable used to store the SAI clock source */
-  uint32_t saiclocksource = 0U;
-  if ((PeriphClk == RCC_PERIPHCLK_SAI1) || (PeriphClk == RCC_PERIPHCLK_SAI2))
-  {
-    saiclocksource = RCC->DCKCFGR;   
-    saiclocksource &= (RCC_DCKCFGR_SAI1SRC | RCC_DCKCFGR_SAI2SRC);
-    switch (saiclocksource)
-    {
-    case 0U: /* PLLSAI is the clock source for SAI*/ 
-      {
-        /* Configure the PLLSAI division factor */
-        /* PLLSAI_VCO Input  = PLL_SOURCE/PLLSAIM */ 
-        if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
-        {
-          /* In Case the PLL Source is HSI (Internal Clock) */
-          vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM));
-        }
-        else
-        {
-          /* In Case the PLL Source is HSE (External Clock) */
-          vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM)));
-        }   
-        /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
-        /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
-        tmpreg1 = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24U;
-        frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6U))/(tmpreg1);
-        
-        /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
-        tmpreg1 = (((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> 8U) + 1U);
-        frequency = frequency/(tmpreg1); 
-        break;       
-      }
-    case RCC_DCKCFGR_SAI1SRC_0: /* PLLI2S is the clock source for SAI*/
-    case RCC_DCKCFGR_SAI2SRC_0: /* PLLI2S is the clock source for SAI*/
-      {  
-        /* Configure the PLLI2S division factor */
-        /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */ 
-        if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
-        {
-          /* In Case the PLL Source is HSI (Internal Clock) */
-          vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
-        }
-        else
-        {
-          /* In Case the PLL Source is HSE (External Clock) */
-          vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)));
-        }
-        
-        /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
-        /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
-        tmpreg1 = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24U;
-        frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U))/(tmpreg1);
-        
-        /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
-        tmpreg1 = ((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) + 1U); 
-        frequency = frequency/(tmpreg1);
-        break;   
-      }
-    case RCC_DCKCFGR_SAI1SRC_1: /* PLLR is the clock source for SAI*/
-    case RCC_DCKCFGR_SAI2SRC_1: /* PLLR is the clock source for SAI*/
-      {
-        /* Configure the PLLI2S division factor */
-        /* PLL_VCO Input  = PLL_SOURCE/PLLM */ 
-        if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
-        {
-          /* In Case the PLL Source is HSI (Internal Clock) */
-          vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
-        }
-        else
-        {
-          /* In Case the PLL Source is HSE (External Clock) */
-          vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
-        }
-        
-        /* PLL_VCO Output = PLL_VCO Input * PLLN */
-        /* SAI_CLK_x = PLL_VCO Output/PLLR */
-        tmpreg1 = (RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U;
-        frequency = (vcoinput * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U))/(tmpreg1);
-        break;       
-      }
-    case RCC_DCKCFGR_SAI1SRC: /* External clock is the clock source for SAI*/
-      {
-        frequency = EXTERNAL_CLOCK_VALUE;
-        break;      
-      }
-    case RCC_DCKCFGR_SAI2SRC: /* PLLSRC(HSE or HSI) is the clock source for SAI*/
-      {
-        if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
-        {
-          /* In Case the PLL Source is HSI (Internal Clock) */
-          frequency = (uint32_t)(HSI_VALUE);
-        }
-        else
-        {
-          /* In Case the PLL Source is HSE (External Clock) */
-          frequency = (uint32_t)(HSE_VALUE);
-        }
-        break;      
-      }     
-    default :
-      {
-        break;
-      }     
-    }
-  }
-  return frequency;  
-}
-
-#endif /* STM32F446xx */
-
-#if defined(STM32F469xx) || defined(STM32F479xx)
-/**
-  * @brief  Initializes the RCC extended peripherals clocks according to the specified
-  *         parameters in the RCC_PeriphCLKInitTypeDef.
-  * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
-  *         contains the configuration information for the Extended Peripherals
-  *         clocks(I2S, SAI, LTDC, RTC and TIM).
-  *         
-  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select 
-  *         the RTC clock source; in this case the Backup domain will be reset in  
-  *         order to modify the RTC Clock source, as consequence RTC registers (including 
-  *         the backup registers) and RCC_BDCR register are set to their reset values.
-  *
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
-{
-  uint32_t tickstart = 0U;
-  uint32_t tmpreg1 = 0U;
-  uint32_t pllsaip = 0U;
-  uint32_t pllsaiq = 0U;
-  uint32_t pllsair = 0U;
-    
-  /* Check the parameters */
-  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
-                                  
-  /*--------------------------- CLK48 Configuration --------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
-    
-    /* Configure the CLK48 clock source */
-    __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
-  }                                  
-  /*--------------------------------------------------------------------------*/
-    
-  /*------------------------------ SDIO Configuration ------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
-    
-    /* Configure the SDIO clock source */
-    __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
-  }
-  /*--------------------------------------------------------------------------*/
-    
-  /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------*/
-  /*------------------- Common configuration SAI/I2S -------------------------*/
-  /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division   
-     factor is common parameters for both peripherals */ 
-  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || 
-     (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) ||
-     (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
-  {
-    /* check for Parameters */
-    assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
-        
-    /* Disable the PLLI2S */
-    __HAL_RCC_PLLI2S_DISABLE();    
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    /* Wait till PLLI2S is disabled */
-    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
-      {
-        /* return in case of Timeout detected */
-        return HAL_TIMEOUT;
-      }
-    }
-    
-    /*---------------------- I2S configuration -------------------------------*/
-    /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added   
-      only for I2S configuration */     
-    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
-    {
-      /* check for Parameters */
-      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
-      /* Configure the PLLI2S division factors */
-      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
-      /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
-      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
-    }
-  
-    /*---------------------------- SAI configuration -------------------------*/ 
-    /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must  
-       be added only for SAI configuration */     
-    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
-    {
-      /* Check the PLLI2S division factors */
-      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
-      assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
-      
-      /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
-      tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
-      /* Configure the PLLI2S division factors */      
-      /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */
-      /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
-      /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
-      __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1);
-      /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ 
-      __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
-    }
-    
-    /*----------------- In Case of PLLI2S is just selected  -----------------*/  
-    if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
-    {
-      /* Check for Parameters */
-      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
-      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
-      
-      /* Configure the PLLI2S multiplication and division factors */
-      __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
-    } 
-    
-    /* Enable the PLLI2S */
-    __HAL_RCC_PLLI2S_ENABLE();
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    /* Wait till PLLI2S is ready */
-    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
-      {
-        /* return in case of Timeout detected */
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  /*--------------------------------------------------------------------------*/
-    
-  /*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/
-  /*----------------------- Common configuration SAI/LTDC --------------------*/
-  /* In Case of SAI, LTDC or CLK48 Clock Configuration through PLLSAI, PLLSAIN division
-     factor is common parameters for these peripherals */ 
-  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) || 
-     (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)             || 
-     ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)          &&
-      (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)))
-  {
-    /* Check the PLLSAI division factors */
-    assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
- 
-    /* Disable PLLSAI Clock */
-    __HAL_RCC_PLLSAI_DISABLE(); 
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    /* Wait till PLLSAI is disabled */
-    while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
-      { 
-        /* return in case of Timeout detected */
-        return HAL_TIMEOUT;
-      }
-    }
-    
-    /*---------------------------- SAI configuration -------------------------*/
-    /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must  
-       be added only for SAI configuration */     
-    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
-    {
-      assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
-      assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
- 
-      /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
-      pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1U) << 1U);     
-      /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
-      pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));      
-      /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
-      /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
-      /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
-      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, pllsair);      
-      /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ 
-      __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
-    }
-    
-    /*---------------------------- LTDC configuration ------------------------*/
-    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
-    {
-      assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
-      assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
-
-      /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
-      pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1U) << 1U);
-      /* Read PLLSAIQ value from PLLSAICFGR register (this value is not need for SAI configuration) */
-      pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));     
-      /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
-      /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
-      /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
-      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, pllsaiq, PeriphClkInit->PLLSAI.PLLSAIR);
-      /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ 
-      __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
-    }    
-    
-    /*---------------------------- CLK48 configuration ------------------------*/
-    /* Configure the PLLSAI when it is used as clock source for CLK48 */
-    if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == (RCC_PERIPHCLK_CLK48)) &&        
-       (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP))
-    {
-      assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
-      
-      /* Read PLLSAIQ value from PLLSAICFGR register (this value is not need for SAI configuration) */
-      pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
-      /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
-      pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
-      /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
-      /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
-      /* CLK48_CLK(first level) = PLLSAI_VCO Output/PLLSAIP */
-      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, pllsair);
-    }
-    
-    /* Enable PLLSAI Clock */
-    __HAL_RCC_PLLSAI_ENABLE();
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    /* Wait till PLLSAI is ready */
-    while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
-      { 
-        /* return in case of Timeout detected */
-        return HAL_TIMEOUT;
-      }
-    }  
-  }
-
-  /*--------------------------------------------------------------------------*/
-     
-  /*---------------------------- RTC configuration ---------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
-  {
-    /* Check for RTC Parameters used to output RTCCLK */
-    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
-    
-    /* Enable Power Clock*/
-    __HAL_RCC_PWR_CLK_ENABLE();
-    
-    /* Enable write access to Backup domain */
-    PWR->CR |= PWR_CR_DBP;
-    
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    
-    while((PWR->CR & PWR_CR_DBP) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ 
-    tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
-    if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
-    {
-      /* Store the content of BDCR register before the reset of Backup Domain */
-      tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
-      /* RTC Clock selection can be changed only if the Backup Domain is reset */
-      __HAL_RCC_BACKUPRESET_FORCE();
-      __HAL_RCC_BACKUPRESET_RELEASE();
-      /* Restore the Content of BDCR register */
-      RCC->BDCR = tmpreg1;
-   
-      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
-      if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
-      {
-        /* Get tick */
-        tickstart = HAL_GetTick();
-        
-        /* Wait till LSE is ready */  
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }
-    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
-  }
-  /*--------------------------------------------------------------------------*/
-
-  /*---------------------------- TIM configuration ---------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
-  {
-    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the RCC_PeriphCLKInitTypeDef according to the internal 
-  * RCC configuration registers.
-  * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that 
-  *         will be configured.
-  * @retval None
-  */
-void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
-{
-  uint32_t tempreg;
-  
-  /* Set all possible values for the extended clock type parameter------------*/
-  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S        | RCC_PERIPHCLK_SAI_PLLSAI |\
-                                        RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC       |\
-                                        RCC_PERIPHCLK_TIM        | RCC_PERIPHCLK_RTC        |\
-                                        RCC_PERIPHCLK_CLK48       | RCC_PERIPHCLK_SDIO;
-  
-  /* Get the PLLI2S Clock configuration --------------------------------------*/
-  PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
-  PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
-  PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
-  /* Get the PLLSAI Clock configuration --------------------------------------*/
-  PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
-  PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
-  PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)); 
-  /* Get the PLLSAI/PLLI2S division factors ----------------------------------*/
-  PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ));
-  PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ));
-  PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR);
-  /* Get the RTC Clock configuration -----------------------------------------*/
-  tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
-  PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
-  
-    /* Get the CLK48 clock configuration -------------------------------------*/
-  PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
-  
-  /* Get the SDIO clock configuration ----------------------------------------*/
-  PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE();
-  
-  if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
-  {
-    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
-  }
-  else
-  {
-    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
-  }
-}
-#endif /* STM32F469xx || STM32F479xx */
-
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) 
-/**
-  * @brief  Initializes the RCC extended peripherals clocks according to the specified
-  *         parameters in the RCC_PeriphCLKInitTypeDef.
-  * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
-  *         contains the configuration information for the Extended Peripherals
-  *         clocks(I2S, LTDC RTC and TIM).
-  *         
-  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select 
-  *         the RTC clock source; in this case the Backup domain will be reset in  
-  *         order to modify the RTC Clock source, as consequence RTC registers (including 
-  *         the backup registers) and RCC_BDCR register are set to their reset values.
-  *
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
-{
-  uint32_t tickstart = 0U;
-  uint32_t tmpreg1 = 0U;
-  uint32_t plli2sq = 0U;
-  uint32_t plli2sused = 0U;
-
-  /* Check the peripheral clock selection parameters */
-  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
-    
-  /*----------------------------------- I2S APB1 configuration ---------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1))
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection));
-    
-    /* Configure I2S Clock source */
-    __HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection);
-    /* Enable the PLLI2S when it's used as clock source for I2S */
-    if(PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)
-    {
-      plli2sused = 1U; 
-    }
-  }
-  /*--------------------------------------------------------------------------*/
-    
-  /*----------------------------------- I2S APB2 configuration ---------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2))
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection));
-    
-    /* Configure I2S Clock source */
-    __HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection);
-    /* Enable the PLLI2S when it's used as clock source for I2S */
-    if(PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)
-    {
-      plli2sused = 1U; 
-    }
-  }
-  /*--------------------------------------------------------------------------*/
-    
-  /*------------------------------------ RTC configuration -------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
-  {
-    /* Check for RTC Parameters used to output RTCCLK */
-    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
-    
-    /* Enable Power Clock*/
-    __HAL_RCC_PWR_CLK_ENABLE();
-    
-    /* Enable write access to Backup domain */
-    PWR->CR |= PWR_CR_DBP;
-    
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    
-    while((PWR->CR & PWR_CR_DBP) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ 
-    tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
-    if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
-    {
-      /* Store the content of BDCR register before the reset of Backup Domain */
-      tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
-      /* RTC Clock selection can be changed only if the Backup Domain is reset */
-      __HAL_RCC_BACKUPRESET_FORCE();
-      __HAL_RCC_BACKUPRESET_RELEASE();
-      /* Restore the Content of BDCR register */
-      RCC->BDCR = tmpreg1;
-
-      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
-      if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
-      {
-        /* Get tick */
-        tickstart = HAL_GetTick();
-        
-        /* Wait till LSE is ready */  
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }
-    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
-  }
-  /*--------------------------------------------------------------------------*/
-    
-  /*------------------------------------ TIM configuration -------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
-  {
-    /* Configure Timer Prescaler */
-    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
-  }
-  /*--------------------------------------------------------------------------*/
-    
-  /*------------------------------------- FMPI2C1 Configuration --------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
-    
-    /* Configure the FMPI2C1 clock source */
-    __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
-  }
-  /*--------------------------------------------------------------------------*/
-    
-  /*------------------------------------- CLK48 Configuration ----------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
-    
-    /* Configure the SDIO clock source */
-    __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
-
-    /* Enable the PLLI2S when it's used as clock source for CLK48 */
-    if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)
-    {
-      plli2sused = 1U; 
-    }
-  }
-  /*--------------------------------------------------------------------------*/
-    
-  /*------------------------------------- SDIO Configuration -----------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
-    
-    /* Configure the SDIO clock source */
-    __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
-  }
-  /*--------------------------------------------------------------------------*/
-    
-  /*-------------------------------------- PLLI2S Configuration --------------*/
-  /* PLLI2S is configured when a peripheral will use it as source clock : I2S on APB1 or
-     I2S on APB2*/
-  if((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
-  {
-    /* Disable the PLLI2S */
-    __HAL_RCC_PLLI2S_DISABLE();
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    /* Wait till PLLI2S is disabled */
-    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
-      {
-        /* return in case of Timeout detected */
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* check for common PLLI2S Parameters */
-    assert_param(IS_RCC_PLLI2SCLKSOURCE(PeriphClkInit->PLLI2SSelection));
-    assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
-    assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
-    /*-------------------- Set the PLL I2S clock -----------------------------*/
-    __HAL_RCC_PLL_I2S_CONFIG(PeriphClkInit->PLLI2SSelection);
-    
-    /*------- In Case of PLLI2S is selected as source clock for I2S ----------*/ 
-    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) ||
-       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)) ||
-       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)) ||
-       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) && (PeriphClkInit->SdioClockSelection == RCC_SDIOCLKSOURCE_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)))
-    {
-      /* check for Parameters */
-      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
-
-      /* Read PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
-      plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
-      /* Configure the PLLI2S division factors */
-      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/
-      /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
-      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sq, PeriphClkInit->PLLI2S.PLLI2SR);
-    }
-
-    /*----------------- In Case of PLLI2S is just selected  ------------------*/
-    if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
-    {
-      /* Check for Parameters */
-      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
-      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
-
-      /* Configure the PLLI2S division factors */
-      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/
-      /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
-      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
-    }
-
-    /* Enable the PLLI2S */
-    __HAL_RCC_PLLI2S_ENABLE();
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    /* Wait till PLLI2S is ready */
-    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
-      {
-        /* return in case of Timeout detected */
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  /*--------------------------------------------------------------------------*/
-
-  /*-------------------- DFSDM1 clock source configuration -------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
-
-    /* Configure the DFSDM1 interface clock source */
-    __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
-  }
-  /*--------------------------------------------------------------------------*/
-
-  /*-------------------- DFSDM1 Audio clock source configuration -------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection));
-
-    /* Configure the DFSDM1 Audio interface clock source */
-    __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection);
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Get the RCC_PeriphCLKInitTypeDef according to the internal
-  *         RCC configuration registers.
-  * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that 
-  *         will be configured.
-  * @retval None
-  */
-void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
-{
-  uint32_t tempreg;
-  
-  /* Set all possible values for the extended clock type parameter------------*/
-  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 | RCC_PERIPHCLK_I2S_APB2 |\
-                                        RCC_PERIPHCLK_TIM      | RCC_PERIPHCLK_RTC      |\
-                                        RCC_PERIPHCLK_FMPI2C1  | RCC_PERIPHCLK_CLK48     |\
-                                        RCC_PERIPHCLK_SDIO;
-  
-  /* Get the PLLI2S Clock configuration --------------------------------------*/
-  PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SM));
-  PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
-  PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
-  PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
-
-  /* Get the I2S APB1 clock configuration ------------------------------------*/
-  PeriphClkInit->I2sApb1ClockSelection = __HAL_RCC_GET_I2S_APB1_SOURCE();
-  
-  /* Get the I2S APB2 clock configuration ------------------------------------*/
-  PeriphClkInit->I2sApb2ClockSelection = __HAL_RCC_GET_I2S_APB2_SOURCE();
-  
-  /* Get the RTC Clock configuration -----------------------------------------*/
-  tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
-  PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
-
-  /* Get the FMPI2C1 clock configuration -------------------------------------*/
-  PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE();
-
-  /* Get the CLK48 clock configuration ----------------------------------------*/
-  PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
-  
-  /* Get the SDIO clock configuration ----------------------------------------*/
-  PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE();
-
-  /* Get the TIM Prescaler configuration -------------------------------------*/
-  if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
-  {
-    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
-  }
-  else
-  {
-    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
-  }
-}
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-/**
-  * @brief  Initializes the RCC extended peripherals clocks according to the specified parameters in the
-  *         RCC_PeriphCLKInitTypeDef.
-  * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
-  *         contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).
-  *         
-  * @note   A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case 
-  *         the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup 
-  *        domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset
-  *              
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
-{
-  uint32_t tickstart = 0U;
-  uint32_t tmpreg1 = 0U;
-    
-  /* Check the parameters */
-  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
-  
-  /*---------------------------- RTC configuration ---------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
-  {
-    /* Check for RTC Parameters used to output RTCCLK */
-    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
-    
-    /* Enable Power Clock*/
-    __HAL_RCC_PWR_CLK_ENABLE();
-    
-    /* Enable write access to Backup domain */
-    PWR->CR |= PWR_CR_DBP;
-    
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    
-    while((PWR->CR & PWR_CR_DBP) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ 
-    tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
-    if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
-    {
-      /* Store the content of BDCR register before the reset of Backup Domain */
-      tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
-      /* RTC Clock selection can be changed only if the Backup Domain is reset */
-      __HAL_RCC_BACKUPRESET_FORCE();
-      __HAL_RCC_BACKUPRESET_RELEASE();
-      /* Restore the Content of BDCR register */
-      RCC->BDCR = tmpreg1;
-
-      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
-      if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
-      {
-        /* Get tick */
-        tickstart = HAL_GetTick();
-        
-        /* Wait till LSE is ready */  
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }
-    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
-  }
-  /*--------------------------------------------------------------------------*/
-
-  /*---------------------------- TIM configuration ---------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
-  {
-    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
-  }
-  /*--------------------------------------------------------------------------*/
-    
-  /*---------------------------- FMPI2C1 Configuration -----------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
-    
-    /* Configure the FMPI2C1 clock source */
-    __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
-  }
-  /*--------------------------------------------------------------------------*/
-  
-  /*---------------------------- LPTIM1 Configuration ------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
-    
-    /* Configure the LPTIM1 clock source */
-    __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
-  }
-
-  /*---------------------------- I2S Configuration ------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_I2SAPBCLKSOURCE(PeriphClkInit->I2SClockSelection));
-    
-    /* Configure the I2S clock source */
-    __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2SClockSelection);
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the RCC_OscInitStruct according to the internal 
-  * RCC configuration registers.
-  * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that 
-  * will be configured.
-  * @retval None
-  */
-void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
-{
-  uint32_t tempreg;
-
-  /* Set all possible values for the extended clock type parameter------------*/
-  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_FMPI2C1 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC;
-  
-  tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
-  PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
-  
-  if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
-  {
-    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
-  }
-  else
-  {
-    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
-  }
-  /* Get the FMPI2C1 clock configuration -------------------------------------*/
-  PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE();
-
-  /* Get the I2S clock configuration -----------------------------------------*/
-  PeriphClkInit->I2SClockSelection = __HAL_RCC_GET_I2S_SOURCE();
-
-  
-}
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
-/**
-  * @brief  Initializes the RCC extended peripherals clocks according to the specified
-  *         parameters in the RCC_PeriphCLKInitTypeDef.
-  * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
-  *         contains the configuration information for the Extended Peripherals
-  *         clocks(I2S, SAI, LTDC RTC and TIM).
-  *         
-  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select 
-  *         the RTC clock source; in this case the Backup domain will be reset in  
-  *         order to modify the RTC Clock source, as consequence RTC registers (including 
-  *         the backup registers) and RCC_BDCR register are set to their reset values.
-  *
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
-{
-  uint32_t tickstart = 0U;
-  uint32_t tmpreg1 = 0U;
-    
-  /* Check the parameters */
-  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
-  
-  /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------*/
-  /*----------------------- Common configuration SAI/I2S ----------------------*/
-  /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division   
-     factor is common parameters for both peripherals */ 
-  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || 
-     (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S))
-  {
-    /* check for Parameters */
-    assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
-        
-    /* Disable the PLLI2S */
-    __HAL_RCC_PLLI2S_DISABLE();    
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    /* Wait till PLLI2S is disabled */
-    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
-      {
-        /* return in case of Timeout detected */
-        return HAL_TIMEOUT;
-      }
-    }
-    
-    /*---------------------------- I2S configuration -------------------------------*/
-    /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added   
-      only for I2S configuration */     
-    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
-    {
-      /* check for Parameters */
-      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
-      /* Configure the PLLI2S division factors */
-      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */
-      /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
-      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
-    }
-  
-    /*---------------------------- SAI configuration -------------------------------*/ 
-    /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must  
-       be added only for SAI configuration */     
-    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
-    {
-      /* Check the PLLI2S division factors */
-      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
-      assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
-      
-      /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
-      tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
-      /* Configure the PLLI2S division factors */      
-      /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */
-      /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
-      /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
-      __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1);
-      /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ 
-      __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
-    }
-    
-    /* Enable the PLLI2S */
-    __HAL_RCC_PLLI2S_ENABLE();
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    /* Wait till PLLI2S is ready */
-    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
-      {
-        /* return in case of Timeout detected */
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  /*--------------------------------------------------------------------------*/
-    
-  /*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/
-  /*----------------------- Common configuration SAI/LTDC --------------------*/
-  /* In Case of SAI or LTDC Clock Configuration through PLLSAI, PLLSAIN division
-     factor is common parameters for both peripherals */ 
-  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) || 
-     (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC))
-  {
-    /* Check the PLLSAI division factors */
-    assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
- 
-    /* Disable PLLSAI Clock */
-    __HAL_RCC_PLLSAI_DISABLE(); 
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    /* Wait till PLLSAI is disabled */
-    while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
-      { 
-        /* return in case of Timeout detected */
-        return HAL_TIMEOUT;
-      }
-    }
-    
-    /*---------------------------- SAI configuration -------------------------*/
-    /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must  
-       be added only for SAI configuration */     
-    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
-    {
-      assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
-      assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
-      
-      /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
-      tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
-      /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
-      /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
-      /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
-      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
-      /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ 
-      __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
-    }
-    
-    /*---------------------------- LTDC configuration ------------------------*/
-    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
-    {
-      assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
-      assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
-      
-      /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
-      tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
-      /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
-      /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
-      /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
-      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, PeriphClkInit->PLLSAI.PLLSAIR);
-      /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ 
-      __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
-    }    
-    /* Enable PLLSAI Clock */
-    __HAL_RCC_PLLSAI_ENABLE();
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    /* Wait till PLLSAI is ready */
-    while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
-      { 
-        /* return in case of Timeout detected */
-        return HAL_TIMEOUT;
-      }
-    }  
-  }
-  /*--------------------------------------------------------------------------*/
-    
-  /*---------------------------- RTC configuration ---------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
-  {
-    /* Check for RTC Parameters used to output RTCCLK */
-    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
-    
-    /* Enable Power Clock*/
-    __HAL_RCC_PWR_CLK_ENABLE();
-      
-    /* Enable write access to Backup domain */
-    PWR->CR |= PWR_CR_DBP;
-      
-    /* Get tick */
-    tickstart = HAL_GetTick();
-      
-    while((PWR->CR & PWR_CR_DBP) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ 
-    tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
-    if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
-    {
-      /* Store the content of BDCR register before the reset of Backup Domain */
-      tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
-      /* RTC Clock selection can be changed only if the Backup Domain is reset */
-      __HAL_RCC_BACKUPRESET_FORCE();
-      __HAL_RCC_BACKUPRESET_RELEASE();
-      /* Restore the Content of BDCR register */
-      RCC->BDCR = tmpreg1;
-
-      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
-      if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
-      {
-        /* Get tick */
-        tickstart = HAL_GetTick();
-        
-        /* Wait till LSE is ready */  
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }
-    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
-  }
-  /*--------------------------------------------------------------------------*/
-
-  /*---------------------------- TIM configuration ---------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
-  {
-    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the PeriphClkInit according to the internal 
-  * RCC configuration registers.
-  * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that 
-  *         will be configured.
-  * @retval None
-  */
-void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
-{
-  uint32_t tempreg;
-  
-  /* Set all possible values for the extended clock type parameter------------*/
-  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_SAI_PLLSAI | RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC;
-  
-  /* Get the PLLI2S Clock configuration -----------------------------------------------*/
-  PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
-  PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
-  PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
-  /* Get the PLLSAI Clock configuration -----------------------------------------------*/
-  PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
-  PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
-  PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)); 
-  /* Get the PLLSAI/PLLI2S division factors -----------------------------------------------*/
-  PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ));
-  PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ));
-  PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR);
-  /* Get the RTC Clock configuration -----------------------------------------------*/
-  tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
-  PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
-  
-  if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
-  {
-    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
-  }
-  else
-  {
-    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
-  }
-}
-
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
-/**
-  * @brief  Initializes the RCC extended peripherals clocks according to the specified parameters in the
-  *         RCC_PeriphCLKInitTypeDef.
-  * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
-  *         contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).
-  *         
-  * @note   A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case 
-  *         the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup 
-  *        domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset
-  *              
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
-{
-  uint32_t tickstart = 0U;
-  uint32_t tmpreg1 = 0U;
-    
-  /* Check the parameters */
-  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
-  
-  /*---------------------------- I2S configuration ---------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
-  {
-    /* check for Parameters */
-    assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
-    assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
-#if defined(STM32F411xE)    
-    assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
-#endif /* STM32F411xE */
-    /* Disable the PLLI2S */
-    __HAL_RCC_PLLI2S_DISABLE();
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    /* Wait till PLLI2S is disabled */
-    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
-      {
-        /* return in case of Timeout detected */
-        return HAL_TIMEOUT;
-      } 
-    }
-
-#if defined(STM32F411xE)
-    /* Configure the PLLI2S division factors */
-    /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
-    /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */    
-    __HAL_RCC_PLLI2S_I2SCLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR);
-#else
-    /* Configure the PLLI2S division factors */
-    /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */
-    /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
-    __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
-#endif /* STM32F411xE */
-    
-    /* Enable the PLLI2S */
-    __HAL_RCC_PLLI2S_ENABLE();
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    /* Wait till PLLI2S is ready */
-    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
-      {
-        /* return in case of Timeout detected */
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  
-  /*---------------------------- RTC configuration ---------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
-  {
-    /* Check for RTC Parameters used to output RTCCLK */
-    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
-    
-    /* Enable Power Clock*/
-    __HAL_RCC_PWR_CLK_ENABLE();
-    
-    /* Enable write access to Backup domain */
-    PWR->CR |= PWR_CR_DBP;
-    
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    
-    while((PWR->CR & PWR_CR_DBP) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ 
-    tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
-    if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
-    {
-      /* Store the content of BDCR register before the reset of Backup Domain */
-      tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
-      /* RTC Clock selection can be changed only if the Backup Domain is reset */
-      __HAL_RCC_BACKUPRESET_FORCE();
-      __HAL_RCC_BACKUPRESET_RELEASE();
-      /* Restore the Content of BDCR register */
-      RCC->BDCR = tmpreg1;
-
-      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
-      if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
-      {
-        /* Get tick */
-        tickstart = HAL_GetTick();
-        
-        /* Wait till LSE is ready */  
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }
-    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
-  }
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
-  /*---------------------------- TIM configuration ---------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
-  {
-    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
-  }
-#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the RCC_OscInitStruct according to the internal 
-  * RCC configuration registers.
-  * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that 
-  * will be configured.
-  * @retval None
-  */
-void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
-{
-  uint32_t tempreg;
-  
-  /* Set all possible values for the extended clock type parameter------------*/
-  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_RTC;
-  
-  /* Get the PLLI2S Clock configuration --------------------------------------*/
-  PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
-  PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
-#if defined(STM32F411xE)
-  PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM);
-#endif /* STM32F411xE */
-  /* Get the RTC Clock configuration -----------------------------------------*/
-  tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
-  PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
-
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
-  /* Get the TIM Prescaler configuration -------------------------------------*/
-  if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
-  {
-    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
-  }
-  else
-  {
-    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
-  }
-#endif /* STM32F401xC || STM32F401xE || STM32F411xE */  
-}
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE  || STM32F411xE */
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
-    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
-/**
-  * @brief  Initializes the RCC Oscillators according to the specified parameters in the
-  *         RCC_OscInitTypeDef.
-  * @param  RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
-  *         contains the configuration information for the RCC Oscillators.
-  * @note   The PLL is not disabled when used as system clock.
-  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
-  *         supported by this API. User should request a transition to LSE Off
-  *         first and then LSE On or LSE Bypass.
-  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
-  *         supported by this API. User should request a transition to HSE Off
-  *         first and then HSE On or HSE Bypass.
-  * @note   This function add the PLL/PLLR factor management during PLL configuration this feature 
-  *         is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices 
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
-{
-  uint32_t tickstart = 0U;  
- 
-  /* Check the parameters */
-  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
-  /*------------------------------- HSE Configuration ------------------------*/ 
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
-    /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
-#if defined(STM32F446xx)
-    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)                                                                     ||\
-      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) ||\
-      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
-#else
-    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)                                                                     ||\
-      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
-#endif /* STM32F446xx */
-    {
-      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
-      {
-        return HAL_ERROR;
-      }
-    }
-    else
-    {
-      /* Set the new HSE configuration ---------------------------------------*/
-      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
-      
-      /* Check the HSE State */
-      if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
-      {
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-      
-        /* Wait till HSE is ready */  
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          } 
-        }
-      }
-      else
-      {
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-
-        /* Wait till HSE is bypassed or disabled */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          } 
-        }
-      }
-    }
-  }
-  /*----------------------------- HSI Configuration --------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
-    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
-    
-    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
-#if defined(STM32F446xx)
-    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)                                                                     ||\
-      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) ||\
-      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
-#else
-    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)                                                                     ||\
-      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
-#endif /* STM32F446xx */
-    {
-      /* When HSI is used as system clock it will not disabled */
-      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
-      {
-        return HAL_ERROR;
-      }
-      /* Otherwise, just the calibration is allowed */
-      else
-      {
-        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
-        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
-      }
-    }
-    else
-    {
-      /* Check the HSI State */
-      if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
-      {
-        /* Enable the Internal High Speed oscillator (HSI). */
-        __HAL_RCC_HSI_ENABLE();
-
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-
-        /* Wait till HSI is ready */  
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }       
-        } 
-                
-        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
-        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
-      }
-      else
-      {
-        /* Disable the Internal High Speed oscillator (HSI). */
-        __HAL_RCC_HSI_DISABLE();
-
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-      
-        /* Wait till HSI is ready */  
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          } 
-        } 
-      }
-    }
-  }
-  /*------------------------------ LSI Configuration -------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
-
-    /* Check the LSI State */
-    if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
-    {
-      /* Enable the Internal Low Speed oscillator (LSI). */
-      __HAL_RCC_LSI_ENABLE();
-      
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
-      
-      /* Wait till LSI is ready */
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
-      {
-        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        } 
-      }
-    }
-    else
-    {
-      /* Disable the Internal Low Speed oscillator (LSI). */
-      __HAL_RCC_LSI_DISABLE();
-      
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
-      
-      /* Wait till LSI is ready */  
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
-      {
-        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }       
-      } 
-    }
-  }
-  /*------------------------------ LSE Configuration -------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
-    
-    /* Enable Power Clock*/
-    __HAL_RCC_PWR_CLK_ENABLE();
-    
-    /* Enable write access to Backup domain */
-    PWR->CR |= PWR_CR_DBP;
-    
-    /* Wait for Backup domain Write protection disable */
-    tickstart = HAL_GetTick();
-    
-    while((PWR->CR & PWR_CR_DBP) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-    
-    /* Set the new LSE configuration -----------------------------------------*/
-    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
-    /* Check the LSE State */
-    if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
-    {
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
-      
-      /* Wait till LSE is ready */  
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
-      {
-        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-    else
-    {
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
-      
-      /* Wait till LSE is ready */  
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
-      {
-        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }       
-      }
-    }
-  }
-  /*-------------------------------- PLL Configuration -----------------------*/
-  /* Check the parameters */
-  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
-  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
-  {
-    /* Check if the PLL is used as system clock or not */
-    if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
-    { 
-      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
-      {
-        /* Check the parameters */
-        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
-        assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
-        assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
-        assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
-        assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
-        assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
-      
-        /* Disable the main PLL. */
-        __HAL_RCC_PLL_DISABLE();
-        
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-        
-        /* Wait till PLL is ready */  
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }        
-
-        /* Configure the main PLL clock source, multiplication and division factors. */
-        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
-                             RCC_OscInitStruct->PLL.PLLM,
-                             RCC_OscInitStruct->PLL.PLLN,
-                             RCC_OscInitStruct->PLL.PLLP,
-                             RCC_OscInitStruct->PLL.PLLQ,
-                             RCC_OscInitStruct->PLL.PLLR);
-
-        /* Enable the main PLL. */
-        __HAL_RCC_PLL_ENABLE();
-
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-        
-        /* Wait till PLL is ready */  
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          } 
-        }
-      }
-      else
-      {
-        /* Disable the main PLL. */
-        __HAL_RCC_PLL_DISABLE();
- 
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-        
-        /* Wait till PLL is ready */  
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }
-    else
-    {
-      return HAL_ERROR;
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the RCC_OscInitStruct according to the internal 
-  * RCC configuration registers.
-  * @param  RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that will be configured.
-  *
-  * @note   This function is only available in case of STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices.
-  * @note   This function add the PLL/PLLR factor management
-  * @retval None
-  */
-void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
-{
-  /* Set all possible values for the Oscillator type parameter ---------------*/
-  RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
-  
-  /* Get the HSE configuration -----------------------------------------------*/
-  if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
-  {
-    RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
-  }
-  else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
-  {
-    RCC_OscInitStruct->HSEState = RCC_HSE_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
-  }
-  
-  /* Get the HSI configuration -----------------------------------------------*/
-  if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
-  {
-    RCC_OscInitStruct->HSIState = RCC_HSI_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
-  }
-  
-  RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
-  
-  /* Get the LSE configuration -----------------------------------------------*/
-  if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
-  {
-    RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
-  }
-  else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
-  {
-    RCC_OscInitStruct->LSEState = RCC_LSE_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
-  }
-  
-  /* Get the LSI configuration -----------------------------------------------*/
-  if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
-  {
-    RCC_OscInitStruct->LSIState = RCC_LSI_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
-  }
-  
-  /* Get the PLL configuration -----------------------------------------------*/
-  if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
-  {
-    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
-  }
-  RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
-  RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
-  RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
-  RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> POSITION_VAL(RCC_PLLCFGR_PLLP));
-  RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ));
-  RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR));
-}
-#endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
-    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
-/**
-  * @brief  Select LSE mode
-  *   
-  * @note   This mode is only available for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx  devices.
-  *     
-  * @param  Mode: specifies the LSE mode.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_LSE_LOWPOWER_MODE:  LSE oscillator in low power mode selection
-  *            @arg RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode selection
-  * @retval None
-  */
-void HAL_RCCEx_SelectLSEMode(uint8_t Mode)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_LSE_MODE(Mode));
-  if(Mode == RCC_LSE_HIGHDRIVE_MODE)
-  {
-    SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
-  }
-  else
-  {
-    CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
-  }
-}
-
-#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-
-#if defined(STM32F446xx)
-/**
-  * @brief  Returns the SYSCLK frequency
-  *        
-  * @note   This function implementation is valid only for STM32F446xx devices.
-  * @note   This function add the PLL/PLLR System clock source
-  *
-  * @note   The system frequency computed by this function is not the real 
-  *         frequency in the chip. It is calculated based on the predefined 
-  *         constant and the selected clock source:
-  * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
-  * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
-  * @note     If SYSCLK source is PLL or PLLR, function returns values based on HSE_VALUE(**) 
-  *           or HSI_VALUE(*) multiplied/divided by the PLL factors.         
-  * @note     (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
-  *               16 MHz) but the real value may vary depending on the variations
-  *               in voltage and temperature.
-  * @note     (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
-  *                25 MHz), user has to ensure that HSE_VALUE is same as the real
-  *                frequency of the crystal used. Otherwise, this function may
-  *                have wrong result.
-  *                  
-  * @note   The result of this function could be not correct when using fractional
-  *         value for HSE crystal.
-  *           
-  * @note   This function can be used by the user application to compute the 
-  *         baudrate for the communication peripherals or configure other parameters.
-  *           
-  * @note   Each time SYSCLK changes, this function must be called to update the
-  *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
-  *         
-  *               
-  * @retval SYSCLK frequency
-  */
-uint32_t HAL_RCC_GetSysClockFreq(void)
-{
-  uint32_t pllm = 0U;
-  uint32_t pllvco = 0U;
-  uint32_t pllp = 0U;
-  uint32_t pllr = 0U;
-  uint32_t sysclockfreq = 0U;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  switch (RCC->CFGR & RCC_CFGR_SWS)
-  {
-    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
-    {
-      sysclockfreq = HSI_VALUE;
-       break;
-    }
-    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
-    {
-      sysclockfreq = HSE_VALUE;
-      break;
-    }
-    case RCC_CFGR_SWS_PLL:  /* PLL/PLLP used as system clock  source */
-    {
-      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
-      SYSCLK = PLL_VCO / PLLP */
-      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
-      if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
-      {
-        /* HSE used as PLL clock source */
-        pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
-      }
-      else
-      {
-        /* HSI used as PLL clock source */
-        pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));    
-      }
-      pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1U) *2U);
-      
-      sysclockfreq = pllvco/pllp;
-      break;
-    }
-    case RCC_CFGR_SWS_PLLR:  /* PLL/PLLR used as system clock  source */
-    {
-      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
-      SYSCLK = PLL_VCO / PLLR */
-      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
-      if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
-      {
-        /* HSE used as PLL clock source */
-        pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
-      }
-      else
-      {
-        /* HSI used as PLL clock source */
-        pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
-      }
-      pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR));
-      
-      sysclockfreq = pllvco/pllr;
-      break;
-    }
-    default:
-    {
-      sysclockfreq = HSI_VALUE;
-      break;
-    }
-  }
-  return sysclockfreq;
-}
-#endif /* STM32F446xx */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_RCC_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_rng.c b/stmhal/hal/f4/src/stm32f4xx_hal_rng.c
deleted file mode 100644
index 7c61096ffd..0000000000
--- a/stmhal/hal/f4/src/stm32f4xx_hal_rng.c
+++ /dev/null
@@ -1,529 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_rng.c
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   RNG HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the Random Number Generator (RNG) peripheral:
-  *           + Initialization/de-initialization functions
-  *           + Peripheral Control functions 
-  *           + Peripheral State functions
-  *         
-  @verbatim
-  ==============================================================================
-                     ##### How to use this driver #####
-  ==============================================================================
-  [..]
-      The RNG HAL driver can be used as follows:
-
-      (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro 
-          in HAL_RNG_MspInit().
-      (#) Activate the RNG peripheral using HAL_RNG_Init() function.
-      (#) Wait until the 32 bit Random Number Generator contains a valid 
-          random data using (polling/interrupt) mode.   
-      (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function.
-  
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup RNG 
-  * @{
-  */
-
-#ifdef HAL_RNG_MODULE_ENABLED
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
-    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F469xx) ||\
-    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
-    defined(STM32F412Cx)
-
-
-/* Private types -------------------------------------------------------------*/
-/* Private defines -----------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @addtogroup RNG_Private_Constants
-  * @{
-  */
-#define RNG_TIMEOUT_VALUE     2U
-/**
-  * @}
-  */ 
-/* Private macros ------------------------------------------------------------*/
-/* Private functions prototypes ----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup RNG_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup RNG_Exported_Functions_Group1
- *  @brief   Initialization and de-initialization functions
- *
-@verbatim
- ===============================================================================
-          ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Initialize the RNG according to the specified parameters 
-          in the RNG_InitTypeDef and create the associated handle
-      (+) DeInitialize the RNG peripheral
-      (+) Initialize the RNG MSP
-      (+) DeInitialize RNG MSP 
-
-@endverbatim
-  * @{
-  */
-  
-/**
-  * @brief  Initializes the RNG peripheral and creates the associated handle.
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
-  *                the configuration information for RNG.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
-{ 
-  /* Check the RNG handle allocation */
-  if(hrng == NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  __HAL_LOCK(hrng);
-  
-  if(hrng->State == HAL_RNG_STATE_RESET)
-  {  
-    /* Allocate lock resource and initialize it */
-    hrng->Lock = HAL_UNLOCKED;
-    /* Init the low level hardware */
-    HAL_RNG_MspInit(hrng);
-  }
-  
-  /* Change RNG peripheral state */
-  hrng->State = HAL_RNG_STATE_BUSY;
-
-  /* Enable the RNG Peripheral */
-  __HAL_RNG_ENABLE(hrng);
-
-  /* Initialize the RNG state */
-  hrng->State = HAL_RNG_STATE_READY;
-  
-  __HAL_UNLOCK(hrng);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the RNG peripheral. 
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
-  *                the configuration information for RNG.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)
-{ 
-  /* Check the RNG handle allocation */
-  if(hrng == NULL)
-  {
-    return HAL_ERROR;
-  }
-  /* Disable the RNG Peripheral */
-  CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN);
-  
-  /* Clear RNG interrupt status flags */
-  CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS);
-  
-  /* DeInit the low level hardware */
-  HAL_RNG_MspDeInit(hrng);
-  
-  /* Update the RNG state */
-  hrng->State = HAL_RNG_STATE_RESET; 
-
-  /* Release Lock */
-  __HAL_UNLOCK(hrng);
-  
-  /* Return the function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the RNG MSP.
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
-  *                the configuration information for RNG.
-  * @retval None
-  */
-__weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrng);
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_RNG_MspInit must be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  DeInitializes the RNG MSP.
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
-  *                the configuration information for RNG.
-  * @retval None
-  */
-__weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrng);
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_RNG_MspDeInit must be implemented in the user file.
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup RNG_Exported_Functions_Group2
- *  @brief   Peripheral Control functions 
- *
-@verbatim   
- ===============================================================================
-                      ##### Peripheral Control functions #####
- ===============================================================================  
-    [..]  This section provides functions allowing to:
-      (+) Get the 32 bit Random number
-      (+) Get the 32 bit Random number with interrupt enabled
-      (+) Handle RNG interrupt request 
-
-@endverbatim
-  * @{
-  */
-   
-/**
-  * @brief  Generates a 32-bit random number.
-  * @note   Each time the random number data is read the RNG_FLAG_DRDY flag 
-  *         is automatically cleared.
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
-  *                the configuration information for RNG.
-  * @param  random32bit: pointer to generated random number variable if successful.
-  * @retval HAL status
-  */
-
-HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit)
-{
-  uint32_t tickstart = 0U;    
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process Locked */
-  __HAL_LOCK(hrng); 
-  
-  /* Check RNG peripheral state */
-  if(hrng->State == HAL_RNG_STATE_READY)
-  {
-    /* Change RNG peripheral state */  
-    hrng->State = HAL_RNG_STATE_BUSY;  
-
-    /* Get tick */
-    tickstart = HAL_GetTick();
-  
-    /* Check if data register contains valid random data */
-    while(__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RNG_TIMEOUT_VALUE)
-      {    
-        hrng->State = HAL_RNG_STATE_ERROR;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrng);
-      
-        return HAL_TIMEOUT;
-      } 
-    }
-  
-    /* Get a 32bit Random number */
-    hrng->RandomNumber = hrng->Instance->DR;
-    *random32bit = hrng->RandomNumber;
-  
-    hrng->State = HAL_RNG_STATE_READY;
-  }
-  else
-  {
-    status = HAL_ERROR;
-  }
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrng);
-  
-  return status;
-}
-
-/**
-  * @brief  Generates a 32-bit random number in interrupt mode.
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
-  *                the configuration information for RNG.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Process Locked */
-  __HAL_LOCK(hrng);
-  
-  /* Check RNG peripheral state */
-  if(hrng->State == HAL_RNG_STATE_READY)
-  {
-    /* Change RNG peripheral state */  
-    hrng->State = HAL_RNG_STATE_BUSY;  
-  
-    /* Process Unlocked */
-    __HAL_UNLOCK(hrng);
-    
-    /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */ 
-    __HAL_RNG_ENABLE_IT(hrng);
-  }
-  else
-  {
-    /* Process Unlocked */
-    __HAL_UNLOCK(hrng);
-    
-    status = HAL_ERROR;
-  }
-  
-  return status;
-}
-
-/**
-  * @brief  Handles RNG interrupt request.
-  * @note   In the case of a clock error, the RNG is no more able to generate 
-  *         random numbers because the PLL48CLK clock is not correct. User has 
-  *         to check that the clock controller is correctly configured to provide
-  *         the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT(). 
-  *         The clock error has no impact on the previously generated 
-  *         random numbers, and the RNG_DR register contents can be used.
-  * @note   In the case of a seed error, the generation of random numbers is 
-  *         interrupted as long as the SECS bit is '1'. If a number is 
-  *         available in the RNG_DR register, it must not be used because it may 
-  *         not have enough entropy. In this case, it is recommended to clear the 
-  *         SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable 
-  *         the RNG peripheral to reinitialize and restart the RNG.
-  * @note   User-written HAL_RNG_ErrorCallback() API is called once whether SEIS
-  *         or CEIS are set.  
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
-  *                the configuration information for RNG.
-  * @retval None
-
-  */
-void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
-{
-  /* RNG clock error interrupt occurred */
-  if((__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET) ||  (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET))
-  { 
-    /* Change RNG peripheral state */
-    hrng->State = HAL_RNG_STATE_ERROR;
-  
-    HAL_RNG_ErrorCallback(hrng);
-    
-    /* Clear the clock error flag */
-    __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI|RNG_IT_SEI);
-    
-  }
-  
-  /* Check RNG data ready interrupt occurred */    
-  if(__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET)
-  {
-    /* Generate random number once, so disable the IT */
-    __HAL_RNG_DISABLE_IT(hrng);
-    
-    /* Get the 32bit Random number (DRDY flag automatically cleared) */ 
-    hrng->RandomNumber = hrng->Instance->DR;
-    
-    if(hrng->State != HAL_RNG_STATE_ERROR)
-    {
-      /* Change RNG peripheral state */
-      hrng->State = HAL_RNG_STATE_READY; 
-      
-      /* Data Ready callback */ 
-      HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber);
-    } 
-  }
-} 
-
-/**
-  * @brief  Returns generated random number in polling mode (Obsolete)
-  *         Use HAL_RNG_GenerateRandomNumber() API instead.
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
-  *                the configuration information for RNG.
-  * @retval Random value
-  */
-uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng)
-{
-  if(HAL_RNG_GenerateRandomNumber(hrng, &(hrng->RandomNumber)) == HAL_OK)
-  {
-    return hrng->RandomNumber; 
-  }
-  else
-  {
-    return 0U;
-  }
-}
-
-/**
-  * @brief  Returns a 32-bit random number with interrupt enabled (Obsolete),
-  *         Use HAL_RNG_GenerateRandomNumber_IT() API instead.
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
-  *                the configuration information for RNG.
-  * @retval 32-bit random number
-  */
-uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng)
-{
-  uint32_t random32bit = 0U;
-  
-  /* Process locked */
-  __HAL_LOCK(hrng);
-  
-  /* Change RNG peripheral state */  
-  hrng->State = HAL_RNG_STATE_BUSY;  
-  
-  /* Get a 32bit Random number */ 
-  random32bit = hrng->Instance->DR;
-  
-  /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */ 
-  __HAL_RNG_ENABLE_IT(hrng); 
-  
-  /* Return the 32 bit random number */   
-  return random32bit;
-}
-
-/**
-  * @brief  Read latest generated random number. 
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
-  *                the configuration information for RNG.
-  * @retval random value
-  */
-uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng)
-{
-  return(hrng->RandomNumber);
-}
-
-/**
-  * @brief  Data Ready callback in non-blocking mode. 
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
-  *                the configuration information for RNG.
-  * @param  random32bit: generated random number.
-  * @retval None
-  */
-__weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrng);
-  UNUSED(random32bit);
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_RNG_ReadyDataCallback must be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  RNG error callbacks.
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
-  *                the configuration information for RNG.
-  * @retval None
-  */
-__weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrng);
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_RNG_ErrorCallback must be implemented in the user file.
-   */
-}
-/**
-  * @}
-  */ 
-
-  
-/** @addtogroup RNG_Exported_Functions_Group3
- *  @brief   Peripheral State functions 
- *
-@verbatim   
- ===============================================================================
-                      ##### Peripheral State functions #####
- ===============================================================================  
-    [..]
-    This subsection permits to get in run-time the status of the peripheral 
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-  
-/**
-  * @brief  Returns the RNG state.
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
-  *                the configuration information for RNG.
-  * @retval HAL state
-  */
-HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
-{
-  return hrng->State;
-}
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
-          STM32F429xx || STM32F439xx || STM32F410xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
-          STM32F412Vx || STM32F412Rx || STM32F412Cx */
-
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_rtc.c b/stmhal/hal/f4/src/stm32f4xx_hal_rtc.c
deleted file mode 100644
index 663192b3a0..0000000000
--- a/stmhal/hal/f4/src/stm32f4xx_hal_rtc.c
+++ /dev/null
@@ -1,1547 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_rtc.c
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   RTC HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the Real Time Clock (RTC) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + RTC Time and Date functions
-  *           + RTC Alarm functions
-  *           + Peripheral Control functions   
-  *           + Peripheral State functions
-  *         
-  @verbatim
-  ==============================================================================
-              ##### Backup Domain Operating Condition #####
-  ==============================================================================
-  [..] The real-time clock (RTC), the RTC backup registers, and the backup 
-       SRAM (BKP SRAM) can be powered from the VBAT voltage when the main 
-       VDD supply is powered off.
-       To retain the content of the RTC backup registers, backup SRAM, and supply 
-       the RTC when VDD is turned off, VBAT pin can be connected to an optional 
-       standby voltage supplied by a battery or by another source.
-
-  [..] To allow the RTC operating even when the main digital supply (VDD) is turned
-       off, the VBAT pin powers the following blocks:
-    (#) The RTC
-    (#) The LSE oscillator
-    (#) The backup SRAM when the low power backup regulator is enabled
-    (#) PC13 to PC15 I/Os, plus PI8 I/O (when available)
-  
-  [..] When the backup domain is supplied by VDD (analog switch connected to VDD),
-       the following pins are available:
-    (#) PC14 and PC15 can be used as either GPIO or LSE pins
-    (#) PC13 can be used as a GPIO or as the RTC_AF1 pin
-    (#) PI8 can be used as a GPIO or as the RTC_AF2 pin
-  
-  [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT 
-       because VDD is not present), the following pins are available:
-    (#) PC14 and PC15 can be used as LSE pins only
-    (#) PC13 can be used as the RTC_AF1 pin 
-    (#) PI8 can be used as the RTC_AF2 pin
-             
-                   ##### Backup Domain Reset #####
-  ==================================================================
-  [..] The backup domain reset sets all RTC registers and the RCC_BDCR register 
-       to their reset values. The BKPSRAM is not affected by this reset. The only
-       way to reset the BKPSRAM is through the Flash interface by requesting 
-       a protection level change from 1 to 0.
-  [..] A backup domain reset is generated when one of the following events occurs:
-    (#) Software reset, triggered by setting the BDRST bit in the 
-        RCC Backup domain control register (RCC_BDCR). 
-    (#) VDD or VBAT power on, if both supplies have previously been powered off.  
-
-                   ##### Backup Domain Access #####
-  ==================================================================
-  [..] After reset, the backup domain (RTC registers, RTC backup data 
-       registers and backup SRAM) is protected against possible unwanted write 
-       accesses. 
-  [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
-    (+) Enable the Power Controller (PWR) APB1 interface clock using the
-        __HAL_RCC_PWR_CLK_ENABLE() function.
-    (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
-    (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function.
-    (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function.
-  
-  
-                  ##### How to use this driver #####
-  ==================================================================
-  [..] 
-    (+) Enable the RTC domain access (see description in the section above).
-    (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour 
-        format using the HAL_RTC_Init() function.
-  
-  *** Time and Date configuration ***
-  ===================================
-  [..] 
-    (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime() 
-        and HAL_RTC_SetDate() functions.
-    (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions. 
-  
-  *** Alarm configuration ***
-  ===========================
-  [..]
-    (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function. 
-        You can also configure the RTC Alarm with interrupt mode using the HAL_RTC_SetAlarm_IT() function.
-    (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.
-  
-                  ##### RTC and low power modes #####
-  ==================================================================
-  [..] The MCU can be woken up from a low power mode by an RTC alternate 
-       function.
-  [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), 
-       RTC wake-up, RTC tamper event detection and RTC time stamp event detection.
-       These RTC alternate functions can wake up the system from the Stop and 
-       Standby low power modes.
-  [..] The system can also wake up from low power modes without depending 
-       on an external interrupt (Auto-wake-up mode), by using the RTC alarm 
-       or the RTC wake-up events.
-  [..] The RTC provides a programmable time base for waking up from the 
-       Stop or Standby mode at regular intervals.
-       Wake-up from STOP and STANDBY modes is possible only when the RTC clock source
-       is LSE or LSI.
-     
-   @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup RTC RTC
-  * @brief RTC HAL module driver
-  * @{
-  */
-
-#ifdef HAL_RTC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup RTC_Exported_Functions RTC Exported Functions
-  * @{
-  */
-  
-/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions 
- *
-@verbatim    
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-   [..] This section provides functions allowing to initialize and configure the 
-         RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable 
-         RTC registers Write protection, enter and exit the RTC initialization mode, 
-         RTC registers synchronization check and reference clock detection enable.
-         (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. 
-             It is split into 2 programmable prescalers to minimize power consumption.
-             (++) A 7-bit asynchronous prescaler and a 13-bit synchronous prescaler.
-             (++) When both prescalers are used, it is recommended to configure the 
-                 asynchronous prescaler to a high value to minimize power consumption.
-         (#) All RTC registers are Write protected. Writing to the RTC registers
-             is enabled by writing a key into the Write Protection register, RTC_WPR.
-         (#) To configure the RTC Calendar, user application should enter 
-             initialization mode. In this mode, the calendar counter is stopped 
-             and its value can be updated. When the initialization sequence is 
-             complete, the calendar restarts counting after 4 RTCCLK cycles.
-         (#) To read the calendar through the shadow registers after Calendar 
-             initialization, calendar update or after wake-up from low power modes 
-             the software must first clear the RSF flag. The software must then 
-             wait until it is set again before reading the calendar, which means 
-             that the calendar registers have been correctly copied into the 
-             RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function 
-             implements the above software sequence (RSF clear and RSF check).
- 
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the RTC peripheral 
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
-{
-  /* Check the RTC peripheral state */
-  if(hrtc == NULL)
-  {
-     return HAL_ERROR;
-  }
-  
-  /* Check the parameters */
-  assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat));
-  assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv));
-  assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv));
-  assert_param (IS_RTC_OUTPUT(hrtc->Init.OutPut));
-  assert_param (IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity));
-  assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType));
-    
-  if(hrtc->State == HAL_RTC_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hrtc->Lock = HAL_UNLOCKED;
-    /* Initialize RTC MSP */
-    HAL_RTC_MspInit(hrtc);
-  }
-  
-  /* Set RTC state */  
-  hrtc->State = HAL_RTC_STATE_BUSY;  
-       
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Set Initialization mode */
-  if(RTC_EnterInitMode(hrtc) != HAL_OK)
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
-    
-    /* Set RTC state */
-    hrtc->State = HAL_RTC_STATE_ERROR;
-    
-    return HAL_ERROR;
-  } 
-  else
-  { 
-    /* Clear RTC_CR FMT, OSEL and POL Bits */
-    hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));
-    /* Set RTC_CR register */
-    hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
-    
-    /* Configure the RTC PRER */
-    hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
-    hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16U);
-    
-    /* Exit Initialization mode */
-    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; 
-    
-    hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_ALARMOUTTYPE;
-    hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType); 
-    
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
-    
-    /* Set RTC state */
-    hrtc->State = HAL_RTC_STATE_READY;
-    
-    return HAL_OK;
-  }
-}
-
-/**
-  * @brief  DeInitializes the RTC peripheral 
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @note   This function doesn't reset the RTC Backup Data registers.   
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
-{
-  uint32_t tickstart = 0U;
-
-  /* Set RTC state */
-  hrtc->State = HAL_RTC_STATE_BUSY; 
-  
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  
-  /* Set Initialization mode */
-  if(RTC_EnterInitMode(hrtc) != HAL_OK)
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
-    
-    /* Set RTC state */
-    hrtc->State = HAL_RTC_STATE_ERROR;
-    
-    return HAL_ERROR;
-  }  
-  else
-  {
-    /* Reset TR, DR and CR registers */
-    hrtc->Instance->TR = (uint32_t)0x00000000U;
-    hrtc->Instance->DR = (uint32_t)0x00002101U;
-    /* Reset All CR bits except CR[2:0] */
-    hrtc->Instance->CR &= (uint32_t)0x00000007U;
-
-    /* Get tick */
-    tickstart = HAL_GetTick();
-
-    /* Wait till WUTWF flag is set and if Time out is reached exit */
-    while(((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-      { 
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
-        
-        /* Set RTC state */
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-        
-        return HAL_TIMEOUT;
-      }      
-    }
-    
-    /* Reset all RTC CR register bits */
-    hrtc->Instance->CR &= (uint32_t)0x00000000U;
-    hrtc->Instance->WUTR = (uint32_t)0x0000FFFFU;
-    hrtc->Instance->PRER = (uint32_t)0x007F00FFU;
-    hrtc->Instance->CALIBR = (uint32_t)0x00000000U;
-    hrtc->Instance->ALRMAR = (uint32_t)0x00000000U;
-    hrtc->Instance->ALRMBR = (uint32_t)0x00000000U;
-    hrtc->Instance->SHIFTR = (uint32_t)0x00000000U;
-    hrtc->Instance->CALR = (uint32_t)0x00000000U;
-    hrtc->Instance->ALRMASSR = (uint32_t)0x00000000U;
-    hrtc->Instance->ALRMBSSR = (uint32_t)0x00000000U;
-    
-    /* Reset ISR register and exit initialization mode */
-    hrtc->Instance->ISR = (uint32_t)0x00000000U;
-    
-    /* Reset Tamper and alternate functions configuration register */
-    hrtc->Instance->TAFCR = 0x00000000U;
-    
-    /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
-    if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
-    {
-      if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  
-        
-        hrtc->State = HAL_RTC_STATE_ERROR;
-        
-        return HAL_ERROR;
-      }
-    }    
-  }
-  
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-  
-  /* De-Initialize RTC MSP */
-  HAL_RTC_MspDeInit(hrtc);
-  
-  hrtc->State = HAL_RTC_STATE_RESET; 
-
-  /* Release Lock */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the RTC MSP.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.  
-  * @retval None
-  */
-__weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_RTC_MspInit could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  DeInitializes the RTC MSP.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC. 
-  * @retval None
-  */
-__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_RTC_MspDeInit could be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions
- *  @brief   RTC Time and Date functions
- *
-@verbatim   
- ===============================================================================
-                 ##### RTC Time and Date functions #####
- ===============================================================================  
- 
- [..] This section provides functions allowing to configure Time and Date features
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Sets RTC current time.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  sTime: Pointer to Time structure
-  * @param  Format: Specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *            @arg RTC_FORMAT_BIN: Binary data format 
-  *            @arg RTC_FORMAT_BCD: BCD data format
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
-{
-  uint32_t tmpreg = 0U;
-  
- /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-  assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving));
-  assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation));
-  
-  /* Process Locked */ 
-  __HAL_LOCK(hrtc);
-  
-  hrtc->State = HAL_RTC_STATE_BUSY;
-  
-  if(Format == RTC_FORMAT_BIN)
-  {
-    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
-    {
-      assert_param(IS_RTC_HOUR12(sTime->Hours));
-      assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
-    } 
-    else
-    {
-      sTime->TimeFormat = 0x00U;
-      assert_param(IS_RTC_HOUR24(sTime->Hours));
-    }
-    assert_param(IS_RTC_MINUTES(sTime->Minutes));
-    assert_param(IS_RTC_SECONDS(sTime->Seconds));
-    
-    tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16U) | \
-                        ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8U) | \
-                        ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \
-                        (((uint32_t)sTime->TimeFormat) << 16U));  
-  }
-  else
-  {
-    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
-    {
-      tmpreg = RTC_Bcd2ToByte(sTime->Hours);
-      assert_param(IS_RTC_HOUR12(tmpreg));
-      assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); 
-    } 
-    else
-    {
-      sTime->TimeFormat = 0x00U;
-      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours)));
-    }
-    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));
-    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));
-    tmpreg = (((uint32_t)(sTime->Hours) << 16U) | \
-              ((uint32_t)(sTime->Minutes) << 8U) | \
-              ((uint32_t)sTime->Seconds) | \
-              ((uint32_t)(sTime->TimeFormat) << 16U));   
-  }
-  
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  
-  /* Set Initialization mode */
-  if(RTC_EnterInitMode(hrtc) != HAL_OK)
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
-    
-    /* Set RTC state */
-    hrtc->State = HAL_RTC_STATE_ERROR;
-    
-    /* Process Unlocked */ 
-    __HAL_UNLOCK(hrtc);
-    
-    return HAL_ERROR;
-  } 
-  else
-  {
-    /* Set the RTC_TR register */
-    hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
-     
-    /* Clear the bits to be configured */
-    hrtc->Instance->CR &= (uint32_t)~RTC_CR_BCK;
-    
-    /* Configure the RTC_CR register */
-    hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
-    
-    /* Exit Initialization mode */
-    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;  
-    
-    /* If  CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
-    if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
-    {
-      if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
-      {        
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  
-        
-        hrtc->State = HAL_RTC_STATE_ERROR;
-        
-        /* Process Unlocked */ 
-        __HAL_UNLOCK(hrtc);
-        
-        return HAL_ERROR;
-      }
-    }
-    
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-    
-   hrtc->State = HAL_RTC_STATE_READY;
-  
-   __HAL_UNLOCK(hrtc); 
-     
-   return HAL_OK;
-  }
-}
-
-/**
-  * @brief  Gets RTC current time.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  sTime: Pointer to Time structure
-  * @param  Format: Specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *            @arg RTC_FORMAT_BIN: Binary data format 
-  *            @arg RTC_FORMAT_BCD: BCD data format
-  * @note  You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds
-  *        value in second fraction ratio with time unit following generic formula:
-  *        Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
-  *        This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS
-  * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values 
-  *        in the higher-order calendar shadow registers to ensure consistency between the time and date values.
-  *        Reading RTC current time locks the values in calendar shadow registers until current date is read.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
-{
-  uint32_t tmpreg = 0U;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-  
-  /* Get subseconds structure field from the corresponding register */
-  sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR);
-  
-  /* Get SecondFraction structure field from the corresponding register field*/
-  sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S);
-
-  /* Get the TR register */
-  tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK); 
-  
-  /* Fill the structure fields with the read parameters */
-  sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16U);
-  sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8U);
-  sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
-  sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16U); 
-  
-  /* Check the input parameters format */
-  if(Format == RTC_FORMAT_BIN)
-  {
-    /* Convert the time structure parameters to Binary format */
-    sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours);
-    sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes);
-    sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds);  
-  }
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Sets RTC current date.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  sDate: Pointer to date structure
-  * @param  Format: specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *            @arg RTC_FORMAT_BIN: Binary data format 
-  *            @arg RTC_FORMAT_BCD: BCD data format
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
-{
-  uint32_t datetmpreg = 0U;
-  
- /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-  
- /* Process Locked */ 
- __HAL_LOCK(hrtc);
-  
-  hrtc->State = HAL_RTC_STATE_BUSY; 
-  
-  if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U))
-  {
-    sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU);
-  }
-  
-  assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));
-  
-  if(Format == RTC_FORMAT_BIN)
-  {   
-    assert_param(IS_RTC_YEAR(sDate->Year));
-    assert_param(IS_RTC_MONTH(sDate->Month));
-    assert_param(IS_RTC_DATE(sDate->Date)); 
-    
-   datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16U) | \
-                 ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8U) | \
-                 ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \
-                 ((uint32_t)sDate->WeekDay << 13U));   
-  }
-  else
-  {   
-    assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));
-    datetmpreg = RTC_Bcd2ToByte(sDate->Month);
-    assert_param(IS_RTC_MONTH(datetmpreg));
-    datetmpreg = RTC_Bcd2ToByte(sDate->Date);
-    assert_param(IS_RTC_DATE(datetmpreg));
-    
-    datetmpreg = ((((uint32_t)sDate->Year) << 16U) | \
-                  (((uint32_t)sDate->Month) << 8U) | \
-                  ((uint32_t)sDate->Date) | \
-                  (((uint32_t)sDate->WeekDay) << 13U));  
-  }
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  
-  /* Set Initialization mode */
-  if(RTC_EnterInitMode(hrtc) != HAL_OK)
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
-    
-    /* Set RTC state*/
-    hrtc->State = HAL_RTC_STATE_ERROR;
-    
-    /* Process Unlocked */ 
-    __HAL_UNLOCK(hrtc);
-    
-    return HAL_ERROR;
-  } 
-  else
-  {
-    /* Set the RTC_DR register */
-    hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK);
-    
-    /* Exit Initialization mode */
-    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;  
-    
-    /* If  CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
-    if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
-    {
-      if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
-      { 
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  
-        
-        hrtc->State = HAL_RTC_STATE_ERROR;
-        
-        /* Process Unlocked */ 
-        __HAL_UNLOCK(hrtc);
-        
-        return HAL_ERROR;
-      }
-    }
-    
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  
-    
-    hrtc->State = HAL_RTC_STATE_READY ;
-    
-    /* Process Unlocked */ 
-    __HAL_UNLOCK(hrtc);
-    
-    return HAL_OK;    
-  }
-}
-
-/**
-  * @brief  Gets RTC current date.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  sDate: Pointer to Date structure
-  * @param  Format: Specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *            @arg RTC_FORMAT_BIN:  Binary data format 
-  *            @arg RTC_FORMAT_BCD:  BCD data format
-  * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values 
-  * in the higher-order calendar shadow registers to ensure consistency between the time and date values.
-  * Reading RTC current time locks the values in calendar shadow registers until Current date is read.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
-{
-  uint32_t datetmpreg = 0U;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-          
-  /* Get the DR register */
-  datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK); 
-
-  /* Fill the structure fields with the read parameters */
-  sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16U);
-  sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8U);
-  sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU));
-  sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13U); 
-
-  /* Check the input parameters format */
-  if(Format == RTC_FORMAT_BIN)
-  {    
-    /* Convert the date structure parameters to Binary format */
-    sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);
-    sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month);
-    sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date);  
-  }
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions
- *  @brief   RTC Alarm functions
- *
-@verbatim   
- ===============================================================================
-                 ##### RTC Alarm functions #####
- ===============================================================================  
- 
- [..] This section provides functions allowing to configure Alarm feature
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Sets the specified RTC Alarm.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  sAlarm: Pointer to Alarm structure
-  * @param  Format: Specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_FORMAT_BIN: Binary data format 
-  *             @arg RTC_FORMAT_BCD: BCD data format
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
-{
-  uint32_t tickstart = 0U;
-  uint32_t tmpreg = 0U, subsecondtmpreg = 0U;
-  
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-  assert_param(IS_RTC_ALARM(sAlarm->Alarm));
-  assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
-  assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
-  assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
-  assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
-  
-  /* Process Locked */ 
-  __HAL_LOCK(hrtc);
-  
-  hrtc->State = HAL_RTC_STATE_BUSY;
-  
-  if(Format == RTC_FORMAT_BIN)
-  {
-    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
-    {
-      assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
-      assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
-    } 
-    else
-    {
-      sAlarm->AlarmTime.TimeFormat = 0x00U;
-      assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
-    }
-    assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
-    assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
-    
-    if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
-    {
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
-    }
-    else
-    {
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
-    }
-    
-    tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \
-              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \
-              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
-              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
-              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \
-              ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
-              ((uint32_t)sAlarm->AlarmMask)); 
-  }
-  else
-  {
-    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
-    {
-      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
-      assert_param(IS_RTC_HOUR12(tmpreg));
-      assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
-    } 
-    else
-    {
-      sAlarm->AlarmTime.TimeFormat = 0x00U;
-      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
-    }
-    
-    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
-    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
-    
-    if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
-    {
-      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));    
-    }
-    else
-    {
-      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));      
-    }  
-    
-    tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \
-              ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \
-              ((uint32_t) sAlarm->AlarmTime.Seconds) | \
-              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
-              ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \
-              ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
-              ((uint32_t)sAlarm->AlarmMask));   
-  }
-  
-  /* Configure the Alarm A or Alarm B Sub Second registers */
-  subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
-  
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Configure the Alarm register */
-  if(sAlarm->Alarm == RTC_ALARM_A)
-  {
-    /* Disable the Alarm A interrupt */
-    __HAL_RTC_ALARMA_DISABLE(hrtc);
-    
-    /* In case of interrupt mode is used, the interrupt source must disabled */ 
-    __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
-
-    /* Get tick */
-    tickstart = HAL_GetTick();
-
-    /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
-    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-        
-        hrtc->State = HAL_RTC_STATE_TIMEOUT; 
-        
-        /* Process Unlocked */ 
-        __HAL_UNLOCK(hrtc);
-        
-        return HAL_TIMEOUT;
-      }   
-    }
-    
-    hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
-    /* Configure the Alarm A Sub Second register */
-    hrtc->Instance->ALRMASSR = subsecondtmpreg;
-    /* Configure the Alarm state: Enable Alarm */
-    __HAL_RTC_ALARMA_ENABLE(hrtc);
-  }
-  else
-  {
-    /* Disable the Alarm B interrupt */
-    __HAL_RTC_ALARMB_DISABLE(hrtc);
-    
-    /* In case of interrupt mode is used, the interrupt source must disabled */ 
-    __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB);
-
-    /* Get tick */
-    tickstart = HAL_GetTick();
-
-    /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
-    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-        
-        hrtc->State = HAL_RTC_STATE_TIMEOUT; 
-        
-        /* Process Unlocked */ 
-        __HAL_UNLOCK(hrtc);
-        
-        return HAL_TIMEOUT;
-      }  
-    }    
-    
-    hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
-    /* Configure the Alarm B Sub Second register */
-    hrtc->Instance->ALRMBSSR = subsecondtmpreg;
-    /* Configure the Alarm state: Enable Alarm */
-    __HAL_RTC_ALARMB_ENABLE(hrtc); 
-  }
-  
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);   
-  
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY; 
-  
-  /* Process Unlocked */ 
-  __HAL_UNLOCK(hrtc);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Sets the specified RTC Alarm with Interrupt 
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  sAlarm: Pointer to Alarm structure
-  * @param  Format: Specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_FORMAT_BIN: Binary data format 
-  *             @arg RTC_FORMAT_BCD: BCD data format
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
-{
-  uint32_t tmpreg = 0U, subsecondtmpreg = 0U;
-  __IO uint32_t count = RTC_TIMEOUT_VALUE  * (SystemCoreClock / 32U / 1000U) ;
-  
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-  assert_param(IS_RTC_ALARM(sAlarm->Alarm));
-  assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
-  assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
-  assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
-  assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
-      
-  /* Process Locked */ 
-  __HAL_LOCK(hrtc);
-  
-  hrtc->State = HAL_RTC_STATE_BUSY;
-  
-  if(Format == RTC_FORMAT_BIN)
-  {
-    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
-    {
-      assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
-      assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
-    } 
-    else
-    {
-      sAlarm->AlarmTime.TimeFormat = 0x00U;
-      assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
-    }
-    assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
-    assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
-    
-    if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
-    {
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
-    }
-    else
-    {
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
-    }
-    tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \
-              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \
-              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
-              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
-              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \
-              ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
-              ((uint32_t)sAlarm->AlarmMask)); 
-  }
-  else
-  {
-    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
-    {
-      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
-      assert_param(IS_RTC_HOUR12(tmpreg));
-      assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
-    } 
-    else
-    {
-      sAlarm->AlarmTime.TimeFormat = 0x00U;
-      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
-    }
-    
-    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
-    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
-    
-    if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
-    {
-      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));    
-    }
-    else
-    {
-      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));      
-    }
-    tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \
-              ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \
-              ((uint32_t) sAlarm->AlarmTime.Seconds) | \
-              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
-              ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \
-              ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
-              ((uint32_t)sAlarm->AlarmMask));     
-  }
-  /* Configure the Alarm A or Alarm B Sub Second registers */
-  subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
-  
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  
-  /* Configure the Alarm register */
-  if(sAlarm->Alarm == RTC_ALARM_A)
-  {
-    /* Disable the Alarm A interrupt */
-    __HAL_RTC_ALARMA_DISABLE(hrtc);
-
-    /* Clear flag alarm A */
-    __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
-
-    /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
-    do
-    {
-      if (count-- == 0)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    } 
-    while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET);
-
-    hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
-    /* Configure the Alarm A Sub Second register */
-    hrtc->Instance->ALRMASSR = subsecondtmpreg;
-    /* Configure the Alarm state: Enable Alarm */
-    __HAL_RTC_ALARMA_ENABLE(hrtc);
-    /* Configure the Alarm interrupt */
-    __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA);
-  }
-  else
-  {
-    /* Disable the Alarm B interrupt */
-    __HAL_RTC_ALARMB_DISABLE(hrtc);
-
-    /* Clear flag alarm B */
-    __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
-
-    /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
-    do
-    {
-      if (count-- == 0)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    } 
-    while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET);
-    
-    hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
-    /* Configure the Alarm B Sub Second register */
-    hrtc->Instance->ALRMBSSR = subsecondtmpreg;
-    /* Configure the Alarm state: Enable Alarm */
-    __HAL_RTC_ALARMB_ENABLE(hrtc);
-    /* Configure the Alarm interrupt */
-    __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB);
-  }
-
-  /* RTC Alarm Interrupt Configuration: EXTI configuration */
-  __HAL_RTC_ALARM_EXTI_ENABLE_IT();
-  
-  EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT;
-  
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  
-  
-  hrtc->State = HAL_RTC_STATE_READY; 
-  
-  /* Process Unlocked */ 
-  __HAL_UNLOCK(hrtc);  
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deactivate the specified RTC Alarm 
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  Alarm: Specifies the Alarm.
-  *          This parameter can be one of the following values:
-  *            @arg RTC_ALARM_A:  AlarmA
-  *            @arg RTC_ALARM_B:  AlarmB
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
-{
-  uint32_t tickstart = 0U;
-  
-  /* Check the parameters */
-  assert_param(IS_RTC_ALARM(Alarm));
-  
-  /* Process Locked */ 
-  __HAL_LOCK(hrtc);
-  
-  hrtc->State = HAL_RTC_STATE_BUSY;
-  
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  
-  if(Alarm == RTC_ALARM_A)
-  {
-    /* AlarmA */
-    __HAL_RTC_ALARMA_DISABLE(hrtc);
-    
-    /* In case of interrupt mode is used, the interrupt source must disabled */ 
-    __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
-
-    /* Get tick */
-    tickstart = HAL_GetTick();
-
-    /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
-    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-      { 
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-        
-        hrtc->State = HAL_RTC_STATE_TIMEOUT; 
-        
-        /* Process Unlocked */ 
-        __HAL_UNLOCK(hrtc);
-        
-        return HAL_TIMEOUT;
-      }      
-    }
-  }
-  else
-  {
-    /* AlarmB */
-    __HAL_RTC_ALARMB_DISABLE(hrtc);
-    
-    /* In case of interrupt mode is used, the interrupt source must disabled */ 
-    __HAL_RTC_ALARM_DISABLE_IT(hrtc,RTC_IT_ALRB);
-
-    /* Get tick */
-    tickstart = HAL_GetTick();
-
-    /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
-    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-        
-        hrtc->State = HAL_RTC_STATE_TIMEOUT; 
-        
-        /* Process Unlocked */ 
-        __HAL_UNLOCK(hrtc);
-        
-        return HAL_TIMEOUT;
-      }    
-    }
-  }
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-  
-  hrtc->State = HAL_RTC_STATE_READY; 
-  
-  /* Process Unlocked */ 
-  __HAL_UNLOCK(hrtc);  
-  
-  return HAL_OK; 
-}
-           
-/**
-  * @brief  Gets the RTC Alarm value and masks.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  sAlarm: Pointer to Date structure
-  * @param  Alarm: Specifies the Alarm.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_ALARM_A: AlarmA
-  *             @arg RTC_ALARM_B: AlarmB  
-  * @param  Format: Specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_FORMAT_BIN: Binary data format 
-  *             @arg RTC_FORMAT_BCD: BCD data format
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
-{
-  uint32_t tmpreg = 0U, subsecondtmpreg = 0U;
-  
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-  assert_param(IS_RTC_ALARM(Alarm));
-  
-  if(Alarm == RTC_ALARM_A)
-  {
-    /* AlarmA */
-    sAlarm->Alarm = RTC_ALARM_A;
-    
-    tmpreg = (uint32_t)(hrtc->Instance->ALRMAR);
-    subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR ) & RTC_ALRMASSR_SS);
-  }
-  else
-  {
-    sAlarm->Alarm = RTC_ALARM_B;
-    
-    tmpreg = (uint32_t)(hrtc->Instance->ALRMBR);
-    subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS);
-  }
-    
-  /* Fill the structure with the read parameters */
-  sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16U);
-  sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8U);
-  sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
-  sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16U);
-  sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;
-  sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24U);
-  sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
-  sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
-    
-  if(Format == RTC_FORMAT_BIN)
-  {
-    sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
-    sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes);
-    sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds);
-    sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
-  }  
-    
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles Alarm interrupt request.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval None
-  */
-void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
-{  
-  if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRA))
-  {
-    /* Get the status of the Interrupt */
-    if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRA) != (uint32_t)RESET)
-    {
-      /* AlarmA callback */ 
-      HAL_RTC_AlarmAEventCallback(hrtc);
-      
-      /* Clear the Alarm interrupt pending bit */
-      __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRAF);
-    }
-  }
-  
-  if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRB))
-  {
-    /* Get the status of the Interrupt */
-    if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRB) != (uint32_t)RESET)
-    {
-      /* AlarmB callback */ 
-      HAL_RTCEx_AlarmBEventCallback(hrtc);
-      
-      /* Clear the Alarm interrupt pending bit */
-      __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRBF);
-    }
-  }
-  
-  /* Clear the EXTI's line Flag for RTC Alarm */
-  __HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
-  
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY; 
-}
-
-/**
-  * @brief  Alarm A callback.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval None
-  */
-__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_RTC_AlarmAEventCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  This function handles AlarmA Polling request.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
-  uint32_t tickstart = 0U; 
-
-    /* Get tick */
-    tickstart = HAL_GetTick();
-
-  while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET)
-  {
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  
-  /* Clear the Alarm interrupt pending bit */
-  __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
-  
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY; 
-  
-  return HAL_OK;  
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions 
- *  @brief   Peripheral Control functions 
- *
-@verbatim   
- ===============================================================================
-                     ##### Peripheral Control functions #####
- ===============================================================================  
-    [..]
-    This subsection provides functions allowing to
-      (+) Wait for RTC Time and Date Synchronization
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are 
-  *         synchronized with RTC APB clock.
-  * @note   The RTC Resynchronization mode is write protected, use the 
-  *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. 
-  * @note   To read the calendar through the shadow registers after Calendar 
-  *         initialization, calendar update or after wake-up from low power modes 
-  *         the software must first clear the RSF flag. 
-  *         The software must then wait until it is set again before reading 
-  *         the calendar, which means that the calendar registers have been 
-  *         correctly copied into the RTC_TR and RTC_DR shadow registers.   
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
-{
-  uint32_t tickstart = 0U;
-
-  /* Clear RSF flag */
-  hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;
-
-    /* Get tick */
-    tickstart = HAL_GetTick();
-
-  /* Wait the registers to be synchronised */
-  while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET)
-  {
-    if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-    {       
-      return HAL_TIMEOUT;
-    } 
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions 
- *  @brief   Peripheral State functions 
- *
-@verbatim   
- ===============================================================================
-                     ##### Peripheral State functions #####
- ===============================================================================  
-    [..]
-    This subsection provides functions allowing to
-      (+) Get RTC state
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Returns the RTC state.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval HAL state
-  */
-HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)
-{
-  return hrtc->State;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @brief  Enters the RTC Initialization mode.
-  * @note   The RTC Initialization mode is write protected, use the
-  *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)
-{
-  uint32_t tickstart = 0U; 
-  
-  /* Check if the Initialization mode is set */
-  if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
-  {
-    /* Set the Initialization mode */
-    hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
-
-    /* Get tick */
-    tickstart = HAL_GetTick();
-
-    /* Wait till RTC is in INIT state and if Time out is reached exit */
-    while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-      {       
-        return HAL_TIMEOUT;
-      } 
-    }
-  }
-  
-  return HAL_OK;  
-}
-
-
-/**
-  * @brief  Converts a 2 digit decimal to BCD format.
-  * @param  Value: Byte to be converted
-  * @retval Converted byte
-  */
-uint8_t RTC_ByteToBcd2(uint8_t Value)
-{
-  uint32_t bcdhigh = 0U;
-  
-  while(Value >= 10U)
-  {
-    bcdhigh++;
-    Value -= 10U;
-  }
-  
-  return  ((uint8_t)(bcdhigh << 4U) | Value);
-}
-
-/**
-  * @brief  Converts from 2 digit BCD to Binary.
-  * @param  Value: BCD value to be converted
-  * @retval Converted word
-  */
-uint8_t RTC_Bcd2ToByte(uint8_t Value)
-{
-  uint32_t tmp = 0U;
-  tmp = ((uint8_t)(Value & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U;
-  return (tmp + (Value & (uint8_t)0x0FU));
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_RTC_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_rtc_ex.c b/stmhal/hal/f4/src/stm32f4xx_hal_rtc_ex.c
deleted file mode 100644
index 871c87c9e7..0000000000
--- a/stmhal/hal/f4/src/stm32f4xx_hal_rtc_ex.c
+++ /dev/null
@@ -1,1781 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_rtc_ex.c
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   RTC HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the Real Time Clock (RTC) Extension peripheral:
-  *           + RTC Time Stamp functions
-  *           + RTC Tamper functions 
-  *           + RTC Wake-up functions
-  *           + Extension Control functions
-  *           + Extension RTC features functions    
-  *         
-  @verbatim
-  ==============================================================================
-                  ##### How to use this driver #####
-  ==============================================================================
-  [..] 
-    (+) Enable the RTC domain access.
-    (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour 
-        format using the HAL_RTC_Init() function.
-  
-  *** RTC Wake-up configuration ***
-  ================================
-  [..] 
-    (+) To configure the RTC Wake-up Clock source and Counter use the HAL_RTC_SetWakeUpTimer()
-        function. You can also configure the RTC Wake-up timer in interrupt mode 
-        using the HAL_RTC_SetWakeUpTimer_IT() function.
-    (+) To read the RTC Wake-up Counter register, use the HAL_RTC_GetWakeUpTimer() 
-        function.
-  
-  *** TimeStamp configuration ***
-  ===============================
-  [..]
-    (+) Configure the RTC_AFx trigger and enable the RTC TimeStamp using the 
-        HAL_RTC_SetTimeStamp() function. You can also configure the RTC TimeStamp with 
-        interrupt mode using the HAL_RTC_SetTimeStamp_IT() function.
-    (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTC_GetTimeStamp()
-        function.
-    (+) The TIMESTAMP alternate function can be mapped either to RTC_AF1 (PC13)
-        or RTC_AF2 (PI8 or PA0 only for STM32F446xx devices) depending on the value of TSINSEL bit in 
-        RTC_TAFCR register. The corresponding pin is also selected by HAL_RTC_SetTimeStamp()
-        or HAL_RTC_SetTimeStamp_IT() function.
-  
-  *** Tamper configuration ***
-  ============================
-  [..]
-    (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge 
-        or Level according to the Tamper filter (if equal to 0 Edge else Level) 
-        value, sampling frequency, precharge or discharge and Pull-UP using the 
-        HAL_RTC_SetTamper() function. You can configure RTC Tamper in interrupt 
-        mode using HAL_RTC_SetTamper_IT() function.
-    (+) The TAMPER1 alternate function can be mapped either to RTC_AF1 (PC13)
-        or RTC_AF2 (PI8 or PA0 only for STM32F446xx devices) depending on the value of TAMP1INSEL bit in 
-        RTC_TAFCR register. The corresponding pin is also selected by HAL_RTC_SetTamper()
-        or HAL_RTC_SetTamper_IT() function.
-  
-  *** Backup Data Registers configuration ***
-  ===========================================
-  [..]
-    (+) To write to the RTC Backup Data registers, use the HAL_RTC_BKUPWrite()
-        function.  
-    (+) To read the RTC Backup Data registers, use the HAL_RTC_BKUPRead()
-        function.
-     
-   @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup RTCEx RTCEx
-  * @brief RTC HAL module driver
-  * @{
-  */
-
-#ifdef HAL_RTC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
-  * @{
-  */  
-
-/** @defgroup RTCEx_Exported_Functions_Group1 RTC TimeStamp and Tamper functions
- *  @brief   RTC TimeStamp and Tamper functions
- *
-@verbatim   
- ===============================================================================
-                 ##### RTC TimeStamp and Tamper functions #####
- ===============================================================================  
- 
- [..] This section provides functions allowing to configure TimeStamp feature
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Sets TimeStamp.
-  * @note   This API must be called before enabling the TimeStamp feature. 
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  TimeStampEdge: Specifies the pin edge on which the TimeStamp is 
-  *         activated.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the  
-  *                                        rising edge of the related pin.
-  *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the 
-  *                                         falling edge of the related pin.
-  * @param  RTC_TimeStampPin: specifies the RTC TimeStamp Pin.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
-  *             @arg RTC_TIMESTAMPPIN_POS1: PI8/PA0 is selected as RTC TimeStamp Pin.
-  *             (PI8 for all STM32 devices except for STM32F446xx devices the PA0 is used) 
-  *             @arg RTC_TIMESTAMPPIN_PA0: PA0 is selected as RTC TimeStamp Pin only for STM32F446xx devices  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
-{
-  uint32_t tmpreg = 0U;
-  
-  /* Check the parameters */
-  assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
-  assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
-  
-  /* Process Locked */ 
-  __HAL_LOCK(hrtc);
-  
-  hrtc->State = HAL_RTC_STATE_BUSY;
-  
-  /* Get the RTC_CR register and clear the bits to be configured */
-  tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
-    
-  tmpreg|= TimeStampEdge;
-  
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  
-  hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_TSINSEL;
-  hrtc->Instance->TAFCR |= (uint32_t)(RTC_TimeStampPin); 
-  
-  /* Configure the Time Stamp TSEDGE and Enable bits */
-  hrtc->Instance->CR = (uint32_t)tmpreg;
-  
-  __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
-  
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);    
-  
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY; 
-  
-  /* Process Unlocked */ 
-  __HAL_UNLOCK(hrtc);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Sets TimeStamp with Interrupt. 
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @note   This API must be called before enabling the TimeStamp feature.
-  * @param  TimeStampEdge: Specifies the pin edge on which the TimeStamp is 
-  *         activated.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the  
-  *                                        rising edge of the related pin.
-  *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the 
-  *                                         falling edge of the related pin.
-  * @param  RTC_TimeStampPin: Specifies the RTC TimeStamp Pin.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
-  *             @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin. (not applicable in the case of STM32F446xx devices) 
-  *             @arg RTC_TIMESTAMPPIN_PA0: PA0 is selected as RTC TimeStamp Pin only for STM32F446xx devices   
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
-{
-  uint32_t tmpreg = 0U;
-  
-  /* Check the parameters */
-  assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
-  assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
-  
-  /* Process Locked */ 
-  __HAL_LOCK(hrtc);
-  
-  hrtc->State = HAL_RTC_STATE_BUSY;
-  
-  /* Get the RTC_CR register and clear the bits to be configured */
-  tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
-  
-  tmpreg |= TimeStampEdge;
-  
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  
-  /* Configure the Time Stamp TSEDGE and Enable bits */
-  hrtc->Instance->CR = (uint32_t)tmpreg;
-  
-  hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_TSINSEL;
-  hrtc->Instance->TAFCR |= (uint32_t)(RTC_TimeStampPin); 
-
-  /* Clear RTC Timestamp flag */
-  __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
-
-  __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
-  
-  /* Enable IT timestamp */ 
-  __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS);
-  
-  /* RTC timestamp Interrupt Configuration: EXTI configuration */
-  __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
-  
-  EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT;
-  
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  
-  
-  hrtc->State = HAL_RTC_STATE_READY;  
-  
-  /* Process Unlocked */ 
-  __HAL_UNLOCK(hrtc);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deactivates TimeStamp. 
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
-{
-  uint32_t tmpreg = 0U;
-  
-  /* Process Locked */ 
-  __HAL_LOCK(hrtc);
-  
-  hrtc->State = HAL_RTC_STATE_BUSY;
-  
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  
-  /* In case of interrupt mode is used, the interrupt source must disabled */ 
-  __HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS);
-  
-  /* Get the RTC_CR register and clear the bits to be configured */
-  tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
-  
-  /* Configure the Time Stamp TSEDGE and Enable bits */
-  hrtc->Instance->CR = (uint32_t)tmpreg;
-  
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
- 
-  hrtc->State = HAL_RTC_STATE_READY;  
-  
-  /* Process Unlocked */ 
-  __HAL_UNLOCK(hrtc);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Gets the RTC TimeStamp value.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  sTimeStamp: Pointer to Time structure
-  * @param  sTimeStampDate: Pointer to Date structure  
-  * @param  Format: specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *             RTC_FORMAT_BIN: Binary data format 
-  *             RTC_FORMAT_BCD: BCD data format
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format)
-{
-  uint32_t tmptime = 0U, tmpdate = 0U;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-
-  /* Get the TimeStamp time and date registers values */
-  tmptime = (uint32_t)(hrtc->Instance->TSTR & RTC_TR_RESERVED_MASK);
-  tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK);
-
-  /* Fill the Time structure fields with the read parameters */
-  sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16U);
-  sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8U);
-  sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));
-  sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16U);  
-  sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR;
-  
-  /* Fill the Date structure fields with the read parameters */
-  sTimeStampDate->Year = 0U;
-  sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8U);
-  sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
-  sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13U);
-
-  /* Check the input parameters format */
-  if(Format == RTC_FORMAT_BIN)
-  {
-    /* Convert the TimeStamp structure parameters to Binary format */
-    sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours);
-    sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes);
-    sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds);
-    
-    /* Convert the DateTimeStamp structure parameters to Binary format */
-    sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month);
-    sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date);
-    sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay);
-  }
-  
-  /* Clear the TIMESTAMP Flag */
-  __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
-    
-  return HAL_OK;
-}
-
-/**
-  * @brief  Sets Tamper
-  * @note   By calling this API we disable the tamper interrupt for all tampers. 
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  sTamper: Pointer to Tamper Structure.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
-{
-  uint32_t tmpreg = 0U;
-  
-  /* Check the parameters */
-  assert_param(IS_RTC_TAMPER(sTamper->Tamper)); 
-  assert_param(IS_RTC_TAMPER_PIN(sTamper->PinSelection));
-  assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
-  assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
-  assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));         
-  assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
-  assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
-  assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
- 
-  /* Process Locked */ 
-  __HAL_LOCK(hrtc);
-    
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
-  { 
-    sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1U); 
-  } 
-        
-  tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->PinSelection | (uint32_t)sTamper->Trigger  |\
-            (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration |\
-            (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
-  
-  hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1U) | (uint32_t)RTC_TAFCR_TAMPTS |\
-                                       (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH |\
-                                       (uint32_t)RTC_TAFCR_TAMPPUDIS | (uint32_t)RTC_TAFCR_TAMPINSEL | (uint32_t)RTC_TAFCR_TAMPIE);
-
-  hrtc->Instance->TAFCR |= tmpreg;
-  
-  hrtc->State = HAL_RTC_STATE_READY; 
-
-  /* Process Unlocked */ 
-  __HAL_UNLOCK(hrtc);
-    
-  return HAL_OK;
-}
-
-/**
-  * @brief  Sets Tamper with interrupt.
-  * @note   By calling this API we force the tamper interrupt for all tampers.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  sTamper: Pointer to RTC Tamper.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
-{
-  uint32_t tmpreg = 0U;
-  
-  /* Check the parameters */
-  assert_param(IS_RTC_TAMPER(sTamper->Tamper)); 
-  assert_param(IS_RTC_TAMPER_PIN(sTamper->PinSelection));
-  assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
-  assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
-  assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));         
-  assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
-  assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
-  assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
- 
-  /* Process Locked */ 
-  __HAL_LOCK(hrtc);
-      
-  hrtc->State = HAL_RTC_STATE_BUSY;
-  
-  /* Configure the tamper trigger */
-  if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
-  { 
-    sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1U); 
-  } 
-       
-  tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->PinSelection | (uint32_t)sTamper->Trigger  |\
-            (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration |\
-            (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
-  
-  hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1U) | (uint32_t)RTC_TAFCR_TAMPTS |\
-                                       (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH |\
-                                       (uint32_t)RTC_TAFCR_TAMPPUDIS | (uint32_t)RTC_TAFCR_TAMPINSEL);
-    
-  hrtc->Instance->TAFCR |= tmpreg;
-  
-  /* Configure the Tamper Interrupt in the RTC_TAFCR */
-  hrtc->Instance->TAFCR |= (uint32_t)RTC_TAFCR_TAMPIE;
-
-  if(sTamper->Tamper == RTC_TAMPER_1)
-  {
-    /* Clear RTC Tamper 1 flag */
-    __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
-  }
-  else
-  {
-    /* Clear RTC Tamper 2 flag */
-    __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);    
-  }
-
-  /* RTC Tamper Interrupt Configuration: EXTI configuration */
-  __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
-  
-  EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT;
-  
-  hrtc->State = HAL_RTC_STATE_READY;   
-  
-  /* Process Unlocked */ 
-  __HAL_UNLOCK(hrtc);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deactivates Tamper.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  Tamper: Selected tamper pin.
-  *          This parameter can be RTC_Tamper_1 and/or RTC_TAMPER_2.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)
-{
-  assert_param(IS_RTC_TAMPER(Tamper)); 
-  
-  /* Process Locked */ 
-  __HAL_LOCK(hrtc);
-      
-  hrtc->State = HAL_RTC_STATE_BUSY;
-  
-  /* Disable the selected Tamper pin */
-  hrtc->Instance->TAFCR &= (uint32_t)~Tamper;  
-  
-  hrtc->State = HAL_RTC_STATE_READY;   
-  
-  /* Process Unlocked */  
-  __HAL_UNLOCK(hrtc);
-  
-  return HAL_OK; 
-}
-
-/**
-  * @brief  This function handles TimeStamp interrupt request.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval None
-  */
-void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
-{  
-  if(__HAL_RTC_TIMESTAMP_GET_IT(hrtc, RTC_IT_TS))
-  {
-    /* Get the status of the Interrupt */
-    if((uint32_t)(hrtc->Instance->CR & RTC_IT_TS) != (uint32_t)RESET)
-    {
-      /* TIMESTAMP callback */ 
-      HAL_RTCEx_TimeStampEventCallback(hrtc);
-  
-      /* Clear the TIMESTAMP interrupt pending bit */
-      __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc,RTC_FLAG_TSF);
-    }
-  }
-  
-  /* Get the status of the Interrupt */
-  if(__HAL_RTC_TAMPER_GET_IT(hrtc,RTC_IT_TAMP1))
-  {
-    /* Get the TAMPER Interrupt enable bit and pending bit */
-    if(((hrtc->Instance->TAFCR & (RTC_TAFCR_TAMPIE))) != (uint32_t)RESET) 
-    {
-      /* Tamper callback */ 
-      HAL_RTCEx_Tamper1EventCallback(hrtc);
-  
-      /* Clear the Tamper interrupt pending bit */
-      __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
-    }
-  }
-  
-  /* Get the status of the Interrupt */
-  if(__HAL_RTC_TAMPER_GET_IT(hrtc, RTC_IT_TAMP2))
-  {
-    /* Get the TAMPER Interrupt enable bit and pending bit */
-    if(((hrtc->Instance->TAFCR & RTC_TAFCR_TAMPIE)) != (uint32_t)RESET) 
-    {
-      /* Tamper callback */ 
-      HAL_RTCEx_Tamper2EventCallback(hrtc);
-  
-      /* Clear the Tamper interrupt pending bit */
-      __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
-    }
-  }
-  /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */
-  __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();
-  
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY; 
-}
-
-/**
-  * @brief  TimeStamp callback. 
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval None
-  */
-__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_RTC_TimeStampEventCallback could be implemented in the user file
-  */
-}
-
-/**
-  * @brief  Tamper 1 callback. 
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval None
-  */
-__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_RTC_Tamper1EventCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Tamper 2 callback. 
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval None
-  */
-__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_RTC_Tamper2EventCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  This function handles TimeStamp polling request.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{ 
-  uint32_t tickstart = 0U; 
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET)
-  {
-    if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET)
-    {
-      /* Clear the TIMESTAMP Overrun Flag */
-      __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
-      
-      /* Change TIMESTAMP state */
-      hrtc->State = HAL_RTC_STATE_ERROR; 
-      
-      return HAL_ERROR; 
-    }
-    
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY; 
-  
-  return HAL_OK; 
-}
-  
-/**
-  * @brief  This function handles Tamper1 Polling.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{  
-  uint32_t tickstart = 0U; 
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-  
-  /* Get the status of the Interrupt */
-  while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== RESET)
-  {
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  
-  /* Clear the Tamper Flag */
-  __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
-  
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-  
-  return HAL_OK; 
-}
-
-/**
-  * @brief  This function handles Tamper2 Polling.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{  
-  uint32_t tickstart = 0U; 
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-  
-  /* Get the status of the Interrupt */
-  while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == RESET)
-  {
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  
-  /* Clear the Tamper Flag */
-  __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP2F);
-  
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-  
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-  
-/** @defgroup RTCEx_Exported_Functions_Group2 RTC Wake-up functions
- *  @brief   RTC Wake-up functions
- *
-@verbatim   
- ===============================================================================
-                        ##### RTC Wake-up functions #####
- ===============================================================================  
- 
- [..] This section provides functions allowing to configure Wake-up feature
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Sets wake up timer. 
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  WakeUpCounter: Wake up counter
-  * @param  WakeUpClock: Wake up clock  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
-{
-  uint32_t tickstart = 0U;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
-  assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
- 
-  /* Process Locked */ 
-  __HAL_LOCK(hrtc);
-    
-  hrtc->State = HAL_RTC_STATE_BUSY;
-  
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
-  if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)
-  {
-    tickstart = HAL_GetTick();
-
-    /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
-    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET)
-    {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-        
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        /* Process Unlocked */ 
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
-
-  tickstart = HAL_GetTick();
-
-  /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
-  while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
-  {
-    if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-    {
-      /* Enable the write protection for RTC registers */
-      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-      hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-      /* Process Unlocked */ 
-      __HAL_UNLOCK(hrtc);
-
-      return HAL_TIMEOUT;
-    }
-  }
-  
-  /* Clear the Wake-up Timer clock source bits in CR register */
-  hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
-  
-  /* Configure the clock source */
-  hrtc->Instance->CR |= (uint32_t)WakeUpClock;
-  
-  /* Configure the Wake-up Timer counter */
-  hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
-  
-   /* Enable the Wake-up Timer */
-  __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);   
-  
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
-  
-  hrtc->State = HAL_RTC_STATE_READY;   
-  
-  /* Process Unlocked */ 
-  __HAL_UNLOCK(hrtc);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Sets wake up timer with interrupt
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  WakeUpCounter: Wake up counter
-  * @param  WakeUpClock: Wake up clock  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
-{
-  __IO uint32_t count;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
-  assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
-
-  /* Process Locked */ 
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Check RTC WUTWF flag is reset only when wake up timer enabled */
-  if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)
-  {
-    /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
-    count = RTC_TIMEOUT_VALUE  * (SystemCoreClock / 32U / 1000U);
-    do
-    {
-      if(count-- == 0U)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET);
-  }
-
-  __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
-
-  /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
-  count = RTC_TIMEOUT_VALUE  * (SystemCoreClock / 32U / 1000U);
-  do
-  {
-    if(count-- == 0U)
-    {
-      /* Enable the write protection for RTC registers */
-      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-      hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hrtc);
-
-      return HAL_TIMEOUT;
-    }
-  }
-  while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET);
-        
-  /* Configure the Wake-up Timer counter */
-  hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
-
-  /* Clear the Wake-up Timer clock source bits in CR register */
-  hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
-
-  /* Configure the clock source */
-  hrtc->Instance->CR |= (uint32_t)WakeUpClock;
-
-  /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
-  __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
-
-  EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT;
-  
-  /* Clear RTC Wake Up timer Flag */
-  __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
-  
-  /* Configure the Interrupt in the RTC_CR register */
-  __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT);
-
-  /* Enable the Wake-up Timer */
-  __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */ 
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deactivates wake up timer counter.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC. 
-  * @retval HAL status
-  */
-uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
-{
-  uint32_t tickstart = 0U;
-  
-  /* Process Locked */ 
-  __HAL_LOCK(hrtc);
-  
-  hrtc->State = HAL_RTC_STATE_BUSY;
-  
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  
-  /* Disable the Wake-up Timer */
-  __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
-  
-  /* In case of interrupt mode is used, the interrupt source must disabled */ 
-  __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT);
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
-  while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
-  {
-    if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-    {
-      /* Enable the write protection for RTC registers */
-      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-      
-      hrtc->State = HAL_RTC_STATE_TIMEOUT; 
-      
-      /* Process Unlocked */ 
-      __HAL_UNLOCK(hrtc);
-      
-      return HAL_TIMEOUT;
-    }   
-  }
-  
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-  
-  hrtc->State = HAL_RTC_STATE_READY;   
-  
-  /* Process Unlocked */ 
-  __HAL_UNLOCK(hrtc);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Gets wake up timer counter.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC. 
-  * @retval Counter value
-  */
-uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
-{
-  /* Get the counter value */
-  return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT)); 
-}
-
-/**
-  * @brief  This function handles Wake Up Timer interrupt request.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval None
-  */
-void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
-{  
-  if(__HAL_RTC_WAKEUPTIMER_GET_IT(hrtc, RTC_IT_WUT))
-  {
-    /* Get the status of the Interrupt */
-    if((uint32_t)(hrtc->Instance->CR & RTC_IT_WUT) != (uint32_t)RESET)
-    {
-      /* WAKEUPTIMER callback */ 
-      HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
-      
-      /* Clear the WAKEUPTIMER interrupt pending bit */
-      __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
-    }
-  }
-  
-  /* Clear the EXTI's line Flag for RTC WakeUpTimer */
-  __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY; 
-}
-
-/**
-  * @brief  Wake Up Timer callback.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval None
-  */
-__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_RTC_WakeUpTimerEventCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  This function handles Wake Up Timer Polling.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{  
-  uint32_t tickstart = 0U; 
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET)
-  {
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-      
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  
-  /* Clear the WAKEUPTIMER Flag */
-  __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
-  
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-  
-  return HAL_OK; 
-}
-
-/**
-  * @}
-  */
-
-
-/** @defgroup RTCEx_Exported_Functions_Group3 Extension Peripheral Control functions 
- *  @brief   Extension Peripheral Control functions 
- *
-@verbatim   
- ===============================================================================
-              ##### Extension Peripheral Control functions #####
- ===============================================================================  
-    [..]
-    This subsection provides functions allowing to
-      (+) Write a data in a specified RTC Backup data register
-      (+) Read a data in a specified RTC Backup data register
-      (+) Set the Coarse calibration parameters.
-      (+) Deactivate the Coarse calibration parameters
-      (+) Set the Smooth calibration parameters.
-      (+) Configure the Synchronization Shift Control Settings.
-      (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
-      (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
-      (+) Enable the RTC reference clock detection.
-      (+) Disable the RTC reference clock detection.
-      (+) Enable the Bypass Shadow feature.
-      (+) Disable the Bypass Shadow feature.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Writes a data in a specified RTC Backup data register.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC. 
-  * @param  BackupRegister: RTC Backup data Register number.
-  *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to 
-  *                                 specify the register.
-  * @param  Data: Data to be written in the specified RTC Backup data register.                     
-  * @retval None
-  */
-void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
-{
-  uint32_t tmp = 0U;
-  
-  /* Check the parameters */
-  assert_param(IS_RTC_BKP(BackupRegister));
-  
-  tmp = (uint32_t)&(hrtc->Instance->BKP0R);
-  tmp += (BackupRegister * 4U);
-  
-  /* Write the specified register */
-  *(__IO uint32_t *)tmp = (uint32_t)Data;
-}
-
-/**
-  * @brief  Reads data from the specified RTC Backup data Register.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC. 
-  * @param  BackupRegister: RTC Backup data Register number.
-  *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to 
-  *                                 specify the register.                   
-  * @retval Read value
-  */
-uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
-{
-  uint32_t tmp = 0U;
-  
-  /* Check the parameters */
-  assert_param(IS_RTC_BKP(BackupRegister));
-
-  tmp = (uint32_t)&(hrtc->Instance->BKP0R);
-  tmp += (BackupRegister * 4U);
-  
-  /* Read the specified register */
-  return (*(__IO uint32_t *)tmp);
-}
-      
-/**
-  * @brief  Sets the Coarse calibration parameters.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.  
-  * @param  CalibSign: Specifies the sign of the coarse calibration value.
-  *          This parameter can be  one of the following values :
-  *             @arg RTC_CALIBSIGN_POSITIVE: The value sign is positive 
-  *             @arg RTC_CALIBSIGN_NEGATIVE: The value sign is negative
-  * @param  Value: value of coarse calibration expressed in ppm (coded on 5 bits).
-  *    
-  * @note   This Calibration value should be between 0 and 63 when using negative
-  *         sign with a 2-ppm step.
-  *           
-  * @note   This Calibration value should be between 0 and 126 when using positive
-  *         sign with a 4-ppm step.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef* hrtc, uint32_t CalibSign, uint32_t Value)
-{
-  /* Check the parameters */
-  assert_param(IS_RTC_CALIB_SIGN(CalibSign));
-  assert_param(IS_RTC_CALIB_VALUE(Value)); 
-  
-  /* Process Locked */ 
-  __HAL_LOCK(hrtc);
-  
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Set Initialization mode */
-  if(RTC_EnterInitMode(hrtc) != HAL_OK)
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
-    
-    /* Set RTC state*/
-    hrtc->State = HAL_RTC_STATE_ERROR;
-    
-    /* Process Unlocked */ 
-    __HAL_UNLOCK(hrtc);
-    
-    return HAL_ERROR;
-  } 
-  else
-  { 
-    /* Enable the Coarse Calibration */
-    __HAL_RTC_COARSE_CALIB_ENABLE(hrtc);
-    
-    /* Set the coarse calibration value */
-    hrtc->Instance->CALIBR = (uint32_t)(CalibSign|Value);
-    
-    /* Exit Initialization mode */
-    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; 
-  } 
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-  
-  /* Change state */
-  hrtc->State = HAL_RTC_STATE_READY; 
-  
-  /* Process Unlocked */ 
-  __HAL_UNLOCK(hrtc);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deactivates the Coarse calibration parameters.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef* hrtc)
-{ 
-  /* Process Locked */ 
-  __HAL_LOCK(hrtc);
-  
-  hrtc->State = HAL_RTC_STATE_BUSY;
-  
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Set Initialization mode */
-  if(RTC_EnterInitMode(hrtc) != HAL_OK)
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
-    
-    /* Set RTC state*/
-    hrtc->State = HAL_RTC_STATE_ERROR;
-    
-    /* Process Unlocked */ 
-    __HAL_UNLOCK(hrtc);
-    
-    return HAL_ERROR;
-  } 
-  else
-  { 
-    /* Enable the Coarse Calibration */
-    __HAL_RTC_COARSE_CALIB_DISABLE(hrtc);
-    
-    /* Exit Initialization mode */
-    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; 
-  } 
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-  
-  /* Change state */
-  hrtc->State = HAL_RTC_STATE_READY; 
-  
-  /* Process Unlocked */ 
-  __HAL_UNLOCK(hrtc);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Sets the Smooth calibration parameters.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.  
-  * @param  SmoothCalibPeriod: Select the Smooth Calibration Period.
-  *          This parameter can be can be one of the following values :
-  *             @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
-  *             @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
-  *             @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
-  * @param  SmoothCalibPlusPulses: Select to Set or reset the CALP bit.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses.
-  *             @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
-  * @param  SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits.
-  *          This parameter can be one any value from 0 to 0x000001FF.
-  * @note   To deactivate the smooth calibration, the field SmoothCalibPlusPulses 
-  *         must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field 
-  *         SmouthCalibMinusPulsesValue must be equal to 0.  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue)
-{
-  uint32_t tickstart = 0U;
-  
-  /* Check the parameters */
-  assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod));
-  assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses));
-  assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmouthCalibMinusPulsesValue));
-  
-  /* Process Locked */ 
-  __HAL_LOCK(hrtc);
-  
-  hrtc->State = HAL_RTC_STATE_BUSY;
-  
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  
-  /* check if a calibration is pending*/
-  if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
-  {
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-    /* check if a calibration is pending*/
-    while((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-        
-        /* Change RTC state */
-        hrtc->State = HAL_RTC_STATE_TIMEOUT; 
-        
-        /* Process Unlocked */ 
-        __HAL_UNLOCK(hrtc);
-        
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  
-  /* Configure the Smooth calibration settings */
-  hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmouthCalibMinusPulsesValue);
-  
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-  
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY; 
-  
-  /* Process Unlocked */ 
-  __HAL_UNLOCK(hrtc);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the Synchronization Shift Control Settings.
-  * @note   When REFCKON is set, firmware must not write to Shift control register. 
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.    
-  * @param  ShiftAdd1S: Select to add or not 1 second to the time calendar.
-  *          This parameter can be one of the following values :
-  *             @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar. 
-  *             @arg RTC_SHIFTADD1S_RESET: No effect.
-  * @param  ShiftSubFS: Select the number of Second Fractions to substitute.
-  *          This parameter can be one any value from 0 to 0x7FFF.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
-{
-  uint32_t tickstart = 0U;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S));
-  assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS));
-
-  /* Process Locked */ 
-  __HAL_LOCK(hrtc);
-  
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-    /* Wait until the shift is completed*/
-    while((hrtc->Instance->ISR & RTC_ISR_SHPF) != RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-      {  
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  
-        
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-        
-        /* Process Unlocked */ 
-        __HAL_UNLOCK(hrtc);
-        
-        return HAL_TIMEOUT;
-      }
-    }
-  
-    /* Check if the reference clock detection is disabled */
-    if((hrtc->Instance->CR & RTC_CR_REFCKON) == RESET)
-    {
-      /* Configure the Shift settings */
-      hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S);
-      
-      /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
-      if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
-      {
-        if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
-        {
-          /* Enable the write protection for RTC registers */
-          __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  
-          
-          hrtc->State = HAL_RTC_STATE_ERROR;
-          
-          /* Process Unlocked */ 
-          __HAL_UNLOCK(hrtc);
-          
-          return HAL_ERROR;
-        }
-      }
-    }
-    else
-    {
-      /* Enable the write protection for RTC registers */
-      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-      
-      /* Change RTC state */
-      hrtc->State = HAL_RTC_STATE_ERROR; 
-      
-      /* Process Unlocked */ 
-      __HAL_UNLOCK(hrtc);
-      
-      return HAL_ERROR;
-    }
-  
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-  
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY; 
-  
-  /* Process Unlocked */ 
-  __HAL_UNLOCK(hrtc);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.    
-  * @param  CalibOutput: Select the Calibration output Selection .
-  *          This parameter can be one of the following values:
-  *             @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz. 
-  *             @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32_t CalibOutput)
-{
-  /* Check the parameters */
-  assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput));
-  
-  /* Process Locked */ 
-  __HAL_LOCK(hrtc);
-  
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  
-  /* Clear flags before config */
-  hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL;
-  
-  /* Configure the RTC_CR register */
-  hrtc->Instance->CR |= (uint32_t)CalibOutput;
-  
-  __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc);
-  
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-  
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY; 
-  
-  /* Process Unlocked */ 
-  __HAL_UNLOCK(hrtc);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.    
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc)
-{
-  /* Process Locked */ 
-  __HAL_LOCK(hrtc);
-  
-  hrtc->State = HAL_RTC_STATE_BUSY;
-  
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  
-  __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc);
-    
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-  
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY; 
-  
-  /* Process Unlocked */ 
-  __HAL_UNLOCK(hrtc);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enables the RTC reference clock detection.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.    
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc)
-{
-  /* Process Locked */ 
-  __HAL_LOCK(hrtc);
-  
-  hrtc->State = HAL_RTC_STATE_BUSY;
-  
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  
-  /* Set Initialization mode */
-  if(RTC_EnterInitMode(hrtc) != HAL_OK)
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
-    
-    /* Set RTC state*/
-    hrtc->State = HAL_RTC_STATE_ERROR;
-    
-    /* Process Unlocked */ 
-    __HAL_UNLOCK(hrtc);
-    
-    return HAL_ERROR;
-  } 
-  else
-  {
-    __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc);
-
-    /* Exit Initialization mode */
-    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; 
-  }
-  
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-  
-   /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY; 
-  
-  /* Process Unlocked */ 
-  __HAL_UNLOCK(hrtc);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disable the RTC reference clock detection.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.    
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc)
-{ 
-  /* Process Locked */ 
-  __HAL_LOCK(hrtc);
-  
-  hrtc->State = HAL_RTC_STATE_BUSY;
-  
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  
-  /* Set Initialization mode */
-  if(RTC_EnterInitMode(hrtc) != HAL_OK)
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
-    
-    /* Set RTC state*/
-    hrtc->State = HAL_RTC_STATE_ERROR;
-    
-    /* Process Unlocked */ 
-    __HAL_UNLOCK(hrtc);
-    
-    return HAL_ERROR;
-  } 
-  else
-  {
-    __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc);
-    
-    /* Exit Initialization mode */
-    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; 
-  }
-  
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-  
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY; 
-  
-  /* Process Unlocked */ 
-  __HAL_UNLOCK(hrtc);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enables the Bypass Shadow feature.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.  
-  * @note   When the Bypass Shadow is enabled the calendar value are taken 
-  *         directly from the Calendar counter.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc)
-{
-  /* Process Locked */ 
-  __HAL_LOCK(hrtc);
-  
-  hrtc->State = HAL_RTC_STATE_BUSY;
-  
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  
-  /* Set the BYPSHAD bit */
-  hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD;
-  
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-  
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY; 
-  
-  /* Process Unlocked */ 
-  __HAL_UNLOCK(hrtc);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disables the Bypass Shadow feature.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.  
-  * @note   When the Bypass Shadow is enabled the calendar value are taken 
-  *         directly from the Calendar counter.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc)
-{
-  /* Process Locked */ 
-  __HAL_LOCK(hrtc);
-  
-  hrtc->State = HAL_RTC_STATE_BUSY;
-  
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  
-  /* Reset the BYPSHAD bit */
-  hrtc->Instance->CR &= (uint8_t)~RTC_CR_BYPSHAD;
-  
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-  
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY; 
-  
-  /* Process Unlocked */ 
-  __HAL_UNLOCK(hrtc);
-  
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-  /** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions 
- *  @brief    Extended features functions  
- *
-@verbatim   
- ===============================================================================
-                 ##### Extended features functions #####
- ===============================================================================  
-    [..]  This section provides functions allowing to:
-      (+) RTC Alarm B callback
-      (+) RTC Poll for Alarm B request
-               
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Alarm B callback.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval None
-  */
-__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_RTC_AlarmBEventCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  This function handles AlarmB Polling request.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{  
-  uint32_t tickstart = 0U; 
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == RESET)
-  {
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  
-  /* Clear the Alarm Flag */
-  __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
-  
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY; 
-  
-  return HAL_OK; 
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_RTC_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_sd.c b/stmhal/hal/f4/src/stm32f4xx_hal_sd.c
deleted file mode 100644
index c5912f0cc9..0000000000
--- a/stmhal/hal/f4/src/stm32f4xx_hal_sd.c
+++ /dev/null
@@ -1,3534 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_sd.c
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   SD card HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the Secure Digital (SD) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions 
-  *           + Peripheral State functions
-  *         
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-  [..]
-    This driver implements a high level communication layer for read and write from/to 
-    this memory. The needed STM32 hardware resources (SDIO and GPIO) are performed by 
-    the user in HAL_SD_MspInit() function (MSP layer).                             
-    Basically, the MSP layer configuration should be the same as we provide in the 
-    examples.
-    You can easily tailor this configuration according to hardware resources.
-
-  [..]
-    This driver is a generic layered driver for SDIO memories which uses the HAL 
-    SDIO driver functions to interface with SD and uSD cards devices. 
-    It is used as follows:
- 
-    (#)Initialize the SDIO low level resources by implement the HAL_SD_MspInit() API:
-        (##) Enable the SDIO interface clock using __HAL_RCC_SDIO_CLK_ENABLE(); 
-        (##) SDIO pins configuration for SD card
-            (+++) Enable the clock for the SDIO GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();   
-            (+++) Configure these SDIO pins as alternate function pull-up using HAL_GPIO_Init()
-                  and according to your pin assignment;
-        (##) DMA Configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA()
-             and HAL_SD_WriteBlocks_DMA() APIs).
-            (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE(); 
-            (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled. 
-        (##) NVIC configuration if you need to use interrupt process when using DMA transfer.
-            (+++) Configure the SDIO and DMA interrupt priorities using functions
-                  HAL_NVIC_SetPriority(); DMA priority is superior to SDIO's priority
-            (+++) Enable the NVIC DMA and SDIO IRQs using function HAL_NVIC_EnableIRQ()
-            (+++) SDIO interrupts are managed using the macros __HAL_SD_SDIO_ENABLE_IT() 
-                  and __HAL_SD_SDIO_DISABLE_IT() inside the communication process.
-            (+++) SDIO interrupts pending bits are managed using the macros __HAL_SD_SDIO_GET_IT()
-                  and __HAL_SD_SDIO_CLEAR_IT()
-    (#) At this stage, you can perform SD read/write/erase operations after SD card initialization  
-
-         
-  *** SD Card Initialization and configuration ***
-  ================================================    
-  [..]
-    To initialize the SD Card, use the HAL_SD_Init() function.  It Initializes 
-    the SD Card and put it into Standby State (Ready for data transfer). 
-    This function provide the following operations:
-  
-    (#) Apply the SD Card initialization process at 400KHz and check the SD Card 
-        type (Standard Capacity or High Capacity). You can change or adapt this 
-        frequency by adjusting the "ClockDiv" field. 
-        The SD Card frequency (SDIO_CK) is computed as follows:
-  
-           SDIO_CK = SDIOCLK / (ClockDiv + 2)
-  
-        In initialization mode and according to the SD Card standard, 
-        make sure that the SDIO_CK frequency doesn't exceed 400KHz.
-  
-    (#) Get the SD CID and CSD data. All these information are managed by the SDCardInfo 
-        structure. This structure provide also ready computed SD Card capacity 
-        and Block size.
-        
-        -@- These information are stored in SD handle structure in case of future use.  
-  
-    (#) Configure the SD Card Data transfer frequency. By Default, the card transfer 
-        frequency is set to 24MHz. You can change or adapt this frequency by adjusting 
-        the "ClockDiv" field.
-        In transfer mode and according to the SD Card standard, make sure that the 
-        SDIO_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch.
-        To be able to use a frequency higher than 24MHz, you should use the SDIO 
-        peripheral in bypass mode. Refer to the corresponding reference manual 
-        for more details.
-  
-    (#) Select the corresponding SD Card according to the address read with the step 2.
-    
-    (#) Configure the SD Card in wide bus mode: 4-bits data.
-  
-  *** SD Card Read operation ***
-  ==============================
-  [..] 
-    (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks(). 
-        This function support only 512-bytes block length (the block size should be 
-        chosen as 512 bytes).
-        You can choose either one block read operation or multiple block read operation 
-        by adjusting the "NumberOfBlocks" parameter.
-
-    (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().
-        This function support only 512-bytes block length (the block size should be 
-        chosen as 512 bytes).
-        You can choose either one block read operation or multiple block read operation 
-        by adjusting the "NumberOfBlocks" parameter.
-        After this, you have to call the function HAL_SD_CheckReadOperation(), to insure
-        that the read transfer is done correctly in both DMA and SD sides.
-  
-  *** SD Card Write operation ***
-  =============================== 
-  [..] 
-    (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks(). 
-        This function support only 512-bytes block length (the block size should be 
-        chosen as 512 bytes).
-        You can choose either one block read operation or multiple block read operation 
-        by adjusting the "NumberOfBlocks" parameter.
-
-    (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().
-        This function support only 512-bytes block length (the block size should be 
-        chosen as 512 byte).
-        You can choose either one block read operation or multiple block read operation 
-        by adjusting the "NumberOfBlocks" parameter.
-        After this, you have to call the function HAL_SD_CheckWriteOperation(), to insure
-        that the write transfer is done correctly in both DMA and SD sides.  
-  
-  *** SD card status ***
-  ====================== 
-  [..]
-    (+) At any time, you can check the SD Card status and get the SD card state 
-        by using the HAL_SD_GetStatus() function. This function checks first if the 
-        SD card is still connected and then get the internal SD Card transfer state.     
-    (+) You can also get the SD card SD Status register by using the HAL_SD_SendSDStatus() 
-        function.    
-
-  *** SD HAL driver macros list ***
-  ==================================
-  [..]
-    Below the list of most used macros in SD HAL driver.
-
-    (+) __HAL_SD_SDIO_ENABLE : Enable the SD device
-    (+) __HAL_SD_SDIO_DISABLE : Disable the SD device
-    (+) __HAL_SD_SDIO_DMA_ENABLE: Enable the SDIO DMA transfer
-    (+) __HAL_SD_SDIO_DMA_DISABLE: Disable the SDIO DMA transfer
-    (+) __HAL_SD_SDIO_ENABLE_IT: Enable the SD device interrupt
-    (+) __HAL_SD_SDIO_DISABLE_IT: Disable the SD device interrupt
-    (+) __HAL_SD_SDIO_GET_FLAG:Check whether the specified SD flag is set or not
-    (+) __HAL_SD_SDIO_CLEAR_FLAG: Clear the SD's pending flags
-      
-    (@) You can refer to the SD HAL driver header file for more useful macros 
-      
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-#ifdef HAL_SD_MODULE_ENABLED
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
-    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
-    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
-    defined(STM32F412Rx) || defined(STM32F412Cx)
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup SD 
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup SD_Private_Defines
-  * @{
-  */
-/** 
-  * @brief  SDIO Data block size 
-  */ 
-#define DATA_BLOCK_SIZE                  ((uint32_t)(9U << 4U))
-/** 
-  * @brief  SDIO Static flags, Timeout, FIFO Address  
-  */
-#define SDIO_STATIC_FLAGS               ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_CTIMEOUT |\
-                                                    SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR | SDIO_FLAG_RXOVERR  |\
-                                                    SDIO_FLAG_CMDREND  | SDIO_FLAG_CMDSENT  | SDIO_FLAG_DATAEND  |\
-                                                    SDIO_FLAG_DBCKEND))  
-
-#define SDIO_CMD0TIMEOUT                ((uint32_t)0x00010000U)
-
-/** 
-  * @brief  Mask for errors Card Status R1 (OCR Register) 
-  */
-#define SD_OCR_ADDR_OUT_OF_RANGE        ((uint32_t)0x80000000U)
-#define SD_OCR_ADDR_MISALIGNED          ((uint32_t)0x40000000U)
-#define SD_OCR_BLOCK_LEN_ERR            ((uint32_t)0x20000000U)
-#define SD_OCR_ERASE_SEQ_ERR            ((uint32_t)0x10000000U)
-#define SD_OCR_BAD_ERASE_PARAM          ((uint32_t)0x08000000U)
-#define SD_OCR_WRITE_PROT_VIOLATION     ((uint32_t)0x04000000U)
-#define SD_OCR_LOCK_UNLOCK_FAILED       ((uint32_t)0x01000000U)
-#define SD_OCR_COM_CRC_FAILED           ((uint32_t)0x00800000U)
-#define SD_OCR_ILLEGAL_CMD              ((uint32_t)0x00400000U)
-#define SD_OCR_CARD_ECC_FAILED          ((uint32_t)0x00200000U)
-#define SD_OCR_CC_ERROR                 ((uint32_t)0x00100000U)
-#define SD_OCR_GENERAL_UNKNOWN_ERROR    ((uint32_t)0x00080000U)
-#define SD_OCR_STREAM_READ_UNDERRUN     ((uint32_t)0x00040000U)
-#define SD_OCR_STREAM_WRITE_OVERRUN     ((uint32_t)0x00020000U)
-#define SD_OCR_CID_CSD_OVERWRITE        ((uint32_t)0x00010000U)
-#define SD_OCR_WP_ERASE_SKIP            ((uint32_t)0x00008000U)
-#define SD_OCR_CARD_ECC_DISABLED        ((uint32_t)0x00004000U)
-#define SD_OCR_ERASE_RESET              ((uint32_t)0x00002000U)
-#define SD_OCR_AKE_SEQ_ERROR            ((uint32_t)0x00000008U)
-#define SD_OCR_ERRORBITS                ((uint32_t)0xFDFFE008U)
-
-/** 
-  * @brief  Masks for R6 Response 
-  */
-#define SD_R6_GENERAL_UNKNOWN_ERROR     ((uint32_t)0x00002000U)
-#define SD_R6_ILLEGAL_CMD               ((uint32_t)0x00004000U)
-#define SD_R6_COM_CRC_FAILED            ((uint32_t)0x00008000U)
-
-#define SD_VOLTAGE_WINDOW_SD            ((uint32_t)0x80100000U)
-#define SD_HIGH_CAPACITY                ((uint32_t)0x40000000U)
-#define SD_STD_CAPACITY                 ((uint32_t)0x00000000U)
-#define SD_CHECK_PATTERN                ((uint32_t)0x000001AAU)
-
-#define SD_MAX_VOLT_TRIAL               ((uint32_t)0x0000FFFFU)
-#define SD_ALLZERO                      ((uint32_t)0x00000000U)
-
-#define SD_WIDE_BUS_SUPPORT             ((uint32_t)0x00040000U)
-#define SD_SINGLE_BUS_SUPPORT           ((uint32_t)0x00010000U)
-#define SD_CARD_LOCKED                  ((uint32_t)0x02000000U)
-
-#define SD_DATATIMEOUT                  ((uint32_t)0xFFFFFFFFU)
-#define SD_0TO7BITS                     ((uint32_t)0x000000FFU)
-#define SD_8TO15BITS                    ((uint32_t)0x0000FF00U)
-#define SD_16TO23BITS                   ((uint32_t)0x00FF0000U)
-#define SD_24TO31BITS                   ((uint32_t)0xFF000000U)
-#define SD_MAX_DATA_LENGTH              ((uint32_t)0x01FFFFFFU)
-
-#define SD_HALFFIFO                     ((uint32_t)0x00000008U)
-#define SD_HALFFIFOBYTES                ((uint32_t)0x00000020U)
-
-/** 
-  * @brief  Command Class Supported 
-  */
-#define SD_CCCC_LOCK_UNLOCK             ((uint32_t)0x00000080U)
-#define SD_CCCC_WRITE_PROT              ((uint32_t)0x00000040U)
-#define SD_CCCC_ERASE                   ((uint32_t)0x00000020U)
-
-/** 
-  * @brief  Following commands are SD Card Specific commands.
-  *         SDIO_APP_CMD should be sent before sending these commands. 
-  */
-#define SD_SDIO_SEND_IF_COND            ((uint32_t)SD_CMD_HS_SEND_EXT_CSD)
-
-/**
-  * @}
-  */
-  
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup SD_Private_Functions_Prototypes
-  * @{
-  */
-static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t addr);
-static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd); 
-static HAL_SD_ErrorTypedef SD_PowerOFF(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus);
-static HAL_SD_CardStateTypedef SD_GetState(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *pStatus);
-static HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD);
-static HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA);
-static HAL_SD_ErrorTypedef SD_WideBus_Enable(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_WideBus_Disable(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR);  
-static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma);
-static void SD_DMA_RxError(DMA_HandleTypeDef *hdma);
-static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma);
-static void SD_DMA_TxError(DMA_HandleTypeDef *hdma);
-/**
-  * @}
-  */
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SD_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup SD_Exported_Functions_Group1
- *  @brief   Initialization and de-initialization functions 
- *
-@verbatim  
-  ==============================================================================
-          ##### Initialization and de-initialization functions #####
-  ==============================================================================
-  [..]  
-    This section provides functions allowing to initialize/de-initialize the SD
-    card device to be ready for use.
-      
- 
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the SD card according to the specified parameters in the 
-            SD_HandleTypeDef and create the associated handle.
-  * @param  hsd: SD handle
-  * @param  SDCardInfo: HAL_SD_CardInfoTypedef structure for SD card information   
-  * @retval HAL SD error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo)
-{ 
-  __IO HAL_SD_ErrorTypedef errorstate = SD_OK;
-  SD_InitTypeDef tmpinit;
-  
-  /* Allocate lock resource and initialize it */
-  hsd->Lock = HAL_UNLOCKED;
-  /* Initialize the low level hardware (MSP) */
-  HAL_SD_MspInit(hsd);
-  
-  /* Default SDIO peripheral configuration for SD card initialization */
-  tmpinit.ClockEdge           = SDIO_CLOCK_EDGE_RISING;
-  tmpinit.ClockBypass         = SDIO_CLOCK_BYPASS_DISABLE;
-  tmpinit.ClockPowerSave      = SDIO_CLOCK_POWER_SAVE_DISABLE;
-  tmpinit.BusWide             = SDIO_BUS_WIDE_1B;
-  tmpinit.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
-  tmpinit.ClockDiv            = SDIO_INIT_CLK_DIV;
-  
-  /* Initialize SDIO peripheral interface with default configuration */
-  SDIO_Init(hsd->Instance, tmpinit);
-  
-  /* Identify card operating voltage */
-  errorstate = SD_PowerON(hsd); 
-  
-  if(errorstate != SD_OK)     
-  {
-    return errorstate;
-  }
-  
-  /* Initialize the present SDIO card(s) and put them in idle state */
-  errorstate = SD_Initialize_Cards(hsd);
-  
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Read CSD/CID MSD registers */
-  errorstate = HAL_SD_Get_CardInfo(hsd, SDCardInfo);
-  
-  if (errorstate == SD_OK)
-  {
-    /* Select the Card */
-    errorstate = SD_Select_Deselect(hsd, (uint32_t)(((uint32_t)SDCardInfo->RCA) << 16U));
-  }
-  
-  /* Configure SDIO peripheral interface */
-  SDIO_Init(hsd->Instance, hsd->Init);   
-  
-  return errorstate;
-}
-
-/**
-  * @brief  De-Initializes the SD card.
-  * @param  hsd: SD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)
-{
-  
-  /* Set SD power state to off */ 
-  SD_PowerOFF(hsd);
-  
-  /* De-Initialize the MSP layer */
-  HAL_SD_MspDeInit(hsd);
-  
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  Initializes the SD MSP.
-  * @param  hsd: SD handle
-  * @retval None
-  */
-__weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsd);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SD_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  De-Initialize SD MSP.
-  * @param  hsd: SD handle
-  * @retval None
-  */
-__weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsd);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SD_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup SD_Exported_Functions_Group2
- *  @brief   Data transfer functions 
- *
-@verbatim   
-  ==============================================================================
-                        ##### IO operation functions #####
-  ==============================================================================  
-  [..]
-    This subsection provides a set of functions allowing to manage the data 
-    transfer from/to SD card.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Reads block(s) from a specified address in a card. The Data transfer 
-  *         is managed by polling mode.  
-  * @param  hsd: SD handle
-  * @param  pReadBuffer: pointer to the buffer that will contain the received data
-  * @param  BlockNumber: Block number from where data is to be read (byte address = BlockNumber * BlockSize)
-  * @param  BlockSize: SD card Data block size 
-  * @note   BlockSize must be 512 bytes.
-  * @param  NumberOfBlocks: Number of SD blocks to read   
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_BlockNumber(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint32_t BlockNumber, uint32_t BlockSize, uint32_t NumberOfBlocks)
-{
-  SDIO_CmdInitTypeDef  sdio_cmdinitstructure;
-  SDIO_DataInitTypeDef sdio_datainitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t count = 0U, *tempbuff = (uint32_t *)pReadBuffer;
-  
-  /* Initialize data control register */
-  hsd->Instance->DCTRL = 0U;
-  
-  uint32_t ReadAddr;
-  if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
-  {
-    BlockSize = 512;
-    ReadAddr = BlockNumber;
-  }
-  else
-  {
-    // should not overflow for standard-capacity cards
-    ReadAddr = BlockNumber * BlockSize;
-  }
-  
-  /* Set Block Size for Card */ 
-  sdio_cmdinitstructure.Argument         = (uint32_t) BlockSize;
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
-  sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-  sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-  sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
-  
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Configure the SD DPSM (Data Path State Machine) */
-  sdio_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
-  sdio_datainitstructure.DataLength    = NumberOfBlocks * BlockSize;
-  sdio_datainitstructure.DataBlockSize = DATA_BLOCK_SIZE;
-  sdio_datainitstructure.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
-  sdio_datainitstructure.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
-  sdio_datainitstructure.DPSM          = SDIO_DPSM_ENABLE;
-  SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
-  
-  if(NumberOfBlocks > 1U)
-  {
-    /* Send CMD18 READ_MULT_BLOCK with argument data address */
-    sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_MULT_BLOCK;
-  }
-  else
-  {
-    /* Send CMD17 READ_SINGLE_BLOCK */
-    sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK;    
-  }
-  
-  sdio_cmdinitstructure.Argument         = ReadAddr;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Read block(s) in polling mode */
-  if(NumberOfBlocks > 1U)
-  {
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK);
-    
-    if (errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-    
-    /* Poll on SDIO flags */
-#ifdef SDIO_STA_STBITERR
-    while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))
-#else /* SDIO_STA_STBITERR not defined */
-    while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND))
-#endif /* SDIO_STA_STBITERR */
-    {
-      if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
-      {
-        /* Read data from SDIO Rx FIFO */
-        for (count = 0U; count < 8U; count++)
-        {
-          *(tempbuff + count) = SDIO_ReadFIFO(hsd->Instance);
-        }
-        
-        tempbuff += 8U;
-      }
-    }      
-  }
-  else
-  {
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK); 
-    
-    if (errorstate != SD_OK)
-    {
-      return errorstate;
-    }    
-    
-    /* In case of single block transfer, no need of stop transfer at all */
-#ifdef SDIO_STA_STBITERR
-    while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
-#else /* SDIO_STA_STBITERR not defined */
-    while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))      
-#endif /* SDIO_STA_STBITERR */
-    {
-      if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
-      {
-        /* Read data from SDIO Rx FIFO */
-        for (count = 0U; count < 8U; count++)
-        {
-          *(tempbuff + count) = SDIO_ReadFIFO(hsd->Instance);
-        }
-        
-        tempbuff += 8U;
-      }
-    }
-  }
-  
-  /* Send stop transmission command in case of multiblock read */
-  if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U))
-  {    
-    if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) ||\
-      (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
-        (hsd->CardType == HIGH_CAPACITY_SD_CARD))
-    {
-      /* Send stop transmission command */
-      errorstate = HAL_SD_StopTransfer(hsd);
-    }
-  }
-  
-  /* Get error state */
-  if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
-    
-    errorstate = SD_DATA_TIMEOUT;
-    
-    return errorstate;
-  }
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
-    
-    errorstate = SD_DATA_CRC_FAIL;
-    
-    return errorstate;
-  }
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
-    
-    errorstate = SD_RX_OVERRUN;
-    
-    return errorstate;
-  }
-#ifdef SDIO_STA_STBITERR
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
-    
-    errorstate = SD_START_BIT_ERR;
-    
-    return errorstate;
-  }
-#endif /* SDIO_STA_STBITERR */ 
-  else
-  {
-    /* No error flag set */
-  }
-  
-  count = SD_DATATIMEOUT;
-  
-  /* Empty FIFO if there is still any data */
-  while ((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (count > 0U))
-  {
-    *tempbuff = SDIO_ReadFIFO(hsd->Instance);
-    tempbuff++;
-    count--;
-  }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Allows to write block(s) to a specified address in a card. The Data
-  *         transfer is managed by polling mode.  
-  * @param  hsd: SD handle
-  * @param  pWriteBuffer: pointer to the buffer that will contain the data to transmit
-  * @param  BlockNumber: Block number to where data is to be written (byte address = BlockNumber * BlockSize)
-  * @param  BlockSize: SD card Data block size 
-  * @note   BlockSize must be 512 bytes.
-  * @param  NumberOfBlocks: Number of SD blocks to write 
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_BlockNumber(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint32_t BlockNumber, uint32_t BlockSize, uint32_t NumberOfBlocks)
-{
-  SDIO_CmdInitTypeDef sdio_cmdinitstructure;
-  SDIO_DataInitTypeDef sdio_datainitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t totalnumberofbytes = 0U, bytestransferred = 0U, count = 0U, restwords = 0U;
-  uint32_t *tempbuff = (uint32_t *)pWriteBuffer;
-  uint8_t cardstate  = 0U;
-  
-  /* Initialize data control register */
-  hsd->Instance->DCTRL = 0U;
-  
-  uint32_t WriteAddr;
-  if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
-  {
-    BlockSize = 512;
-    WriteAddr = BlockNumber;
-  }
-  else
-  {
-    // should not overflow for standard-capacity cards
-    WriteAddr = BlockNumber * BlockSize;
-  }
-  
-  /* Set Block Size for Card */ 
-  sdio_cmdinitstructure.Argument         = (uint32_t)BlockSize;
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
-  sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-  sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-  sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
-  
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  if(NumberOfBlocks > 1U)
-  {
-    /* Send CMD25 WRITE_MULT_BLOCK with argument data address */
-    sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK;
-  }
-  else
-  {
-    /* Send CMD24 WRITE_SINGLE_BLOCK */
-    sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK;
-  }
-  
-  sdio_cmdinitstructure.Argument         = WriteAddr;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  if(NumberOfBlocks > 1U)
-  {
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK);
-  }
-  else
-  {
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK);
-  }  
-  
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Set total number of bytes to write */
-  totalnumberofbytes = NumberOfBlocks * BlockSize;
-  
-  /* Configure the SD DPSM (Data Path State Machine) */ 
-  sdio_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
-  sdio_datainitstructure.DataLength    = NumberOfBlocks * BlockSize;
-  sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
-  sdio_datainitstructure.TransferDir   = SDIO_TRANSFER_DIR_TO_CARD;
-  sdio_datainitstructure.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
-  sdio_datainitstructure.DPSM          = SDIO_DPSM_ENABLE;
-  SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
-  
-  /* Write block(s) in polling mode */
-  if(NumberOfBlocks > 1U)
-  {
-#ifdef SDIO_STA_STBITERR
-    while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))
-#else /* SDIO_STA_STBITERR not defined */
-    while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND))
-#endif /* SDIO_STA_STBITERR */     
-    {
-      if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE))
-      {
-        if ((totalnumberofbytes - bytestransferred) < 32U)
-        {
-          restwords = ((totalnumberofbytes - bytestransferred) % 4U == 0U) ? ((totalnumberofbytes - bytestransferred) / 4U) : (( totalnumberofbytes -  bytestransferred) / 4U + 1U);
-          
-          /* Write data to SDIO Tx FIFO */
-          for (count = 0U; count < restwords; count++)
-          {
-            SDIO_WriteFIFO(hsd->Instance, tempbuff);
-            tempbuff++;
-            bytestransferred += 4U;
-          }
-        }
-        else
-        {
-          /* Write data to SDIO Tx FIFO */
-          for (count = 0U; count < 8U; count++)
-          {
-            SDIO_WriteFIFO(hsd->Instance, (tempbuff + count));
-          }
-          
-          tempbuff += 8U;
-          bytestransferred += 32U;
-        }
-      }
-    }   
-  }
-  else
-  {
-    /* In case of single data block transfer no need of stop command at all */
-#ifdef SDIO_STA_STBITERR
-    while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
-#else /* SDIO_STA_STBITERR not defined */
-    while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))
-#endif /* SDIO_STA_STBITERR */
-    {
-      if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE))
-      {
-        if ((totalnumberofbytes - bytestransferred) < 32U)
-        {
-          restwords = ((totalnumberofbytes - bytestransferred) % 4U == 0U) ? ((totalnumberofbytes - bytestransferred) / 4U) : (( totalnumberofbytes -  bytestransferred) / 4U + 1U);
-          
-          /* Write data to SDIO Tx FIFO */
-          for (count = 0U; count < restwords; count++)
-          {
-            SDIO_WriteFIFO(hsd->Instance, tempbuff);
-            tempbuff++; 
-            bytestransferred += 4U;
-          }
-        }
-        else
-        {
-          /* Write data to SDIO Tx FIFO */
-          for (count = 0U; count < 8U; count++)
-          {
-            SDIO_WriteFIFO(hsd->Instance, (tempbuff + count));
-          }
-          
-          tempbuff += 8U;
-          bytestransferred += 32U;
-        }
-      }
-    }  
-  }
-  
-  /* Send stop transmission command in case of multiblock write */
-  if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U))
-  {    
-    if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
-      (hsd->CardType == HIGH_CAPACITY_SD_CARD))
-    {
-      /* Send stop transmission command */
-      errorstate = HAL_SD_StopTransfer(hsd);
-    }
-  }
-  
-  /* Get error state */
-  if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
-    
-    errorstate = SD_DATA_TIMEOUT;
-    
-    return errorstate;
-  }
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
-    
-    errorstate = SD_DATA_CRC_FAIL;
-    
-    return errorstate;
-  }
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_TXUNDERR);
-    
-    errorstate = SD_TX_UNDERRUN;
-    
-    return errorstate;
-  }
-#ifdef SDIO_STA_STBITERR
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
-    
-    errorstate = SD_START_BIT_ERR;
-    
-    return errorstate;
-  }
-#endif /* SDIO_STA_STBITERR */
-  else
-  {
-    /* No error flag set */
-  }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-  
-  /* Wait till the card is in programming state */
-  errorstate = SD_IsCardProgramming(hsd, &cardstate);
-  
-  while ((errorstate == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING)))
-  {
-    errorstate = SD_IsCardProgramming(hsd, &cardstate);
-  }
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Reads block(s) from a specified address in a card. The Data transfer 
-  *         is managed by DMA mode. 
-  * @note   This API should be followed by the function HAL_SD_CheckReadOperation()
-  *         to check the completion of the read process   
-  * @param  hsd: SD handle                 
-  * @param  pReadBuffer: Pointer to the buffer that will contain the received data
-  * @param  BlockNumber: Block number from where data is to be read (byte address = BlockNumber * BlockSize)
-  * @param  BlockSize: SD card Data block size 
-  * @note   BlockSize must be 512 bytes.
-  * @param  NumberOfBlocks: Number of blocks to read.
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_BlockNumber_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint32_t BlockNumber, uint32_t BlockSize, uint32_t NumberOfBlocks)
-{
-  SDIO_CmdInitTypeDef sdio_cmdinitstructure;
-  SDIO_DataInitTypeDef sdio_datainitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  
-  /* Initialize data control register */
-  hsd->Instance->DCTRL = 0U;
-  
-  /* Initialize handle flags */
-  hsd->SdTransferCplt  = 0U;
-  hsd->DmaTransferCplt = 0U;
-  hsd->SdTransferErr   = SD_OK; 
-  
-  /* Initialize SD Read operation */
-  if(NumberOfBlocks > 1U)
-  {
-    hsd->SdOperation = SD_READ_MULTIPLE_BLOCK;
-  }
-  else
-  {
-    hsd->SdOperation = SD_READ_SINGLE_BLOCK;
-  }
-  
-  /* Enable transfer interrupts */
-#ifdef SDIO_STA_STBITERR
-  __HAL_SD_SDIO_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL |\
-                                SDIO_IT_DTIMEOUT |\
-                                SDIO_IT_DATAEND  |\
-                                SDIO_IT_RXOVERR  |\
-                                SDIO_IT_STBITERR));
-#else /* SDIO_STA_STBITERR not defined */
-  __HAL_SD_SDIO_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL |\
-                                SDIO_IT_DTIMEOUT |\
-                                SDIO_IT_DATAEND  |\
-                                SDIO_IT_RXOVERR));
-#endif /* SDIO_STA_STBITERR */
-  
-  /* Enable SDIO DMA transfer */
-  __HAL_SD_SDIO_DMA_ENABLE();
-  
-  /* Configure DMA user callbacks */
-  hsd->hdmarx->XferCpltCallback  = SD_DMA_RxCplt;
-  hsd->hdmarx->XferErrorCallback = SD_DMA_RxError;
-  
-  /* Enable the DMA Stream */
-  HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pReadBuffer, (uint32_t)(BlockSize * NumberOfBlocks)/4);
-  
-  uint32_t ReadAddr;
-  if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
-  {
-    BlockSize = 512;
-    ReadAddr = BlockNumber;
-  }
-  else
-  {
-    // should not overflow for standard-capacity cards
-    ReadAddr = BlockNumber * BlockSize;
-  }
-  
-  /* Set Block Size for Card */ 
-  sdio_cmdinitstructure.Argument         = (uint32_t)BlockSize;
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
-  sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-  sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-  sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
-  
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Configure the SD DPSM (Data Path State Machine) */ 
-  sdio_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
-  sdio_datainitstructure.DataLength    = BlockSize * NumberOfBlocks;
-  sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
-  sdio_datainitstructure.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
-  sdio_datainitstructure.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
-  sdio_datainitstructure.DPSM          = SDIO_DPSM_ENABLE;
-  SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
-  
-  /* Check number of blocks command */
-  if(NumberOfBlocks > 1U)
-  {
-    /* Send CMD18 READ_MULT_BLOCK with argument data address */
-    sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_MULT_BLOCK;
-  }
-  else
-  {
-    /* Send CMD17 READ_SINGLE_BLOCK */
-    sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK;
-  }
-  
-  sdio_cmdinitstructure.Argument         = ReadAddr;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  if(NumberOfBlocks > 1U)
-  {
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK);
-  }
-  else
-  {
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK);
-  }
-  
-  /* Update the SD transfer error in SD handle */
-  hsd->SdTransferErr = errorstate;
-  
-  return errorstate;
-}
-
-
-/**
-  * @brief  Writes block(s) to a specified address in a card. The Data transfer 
-  *         is managed by DMA mode. 
-  * @note   This API should be followed by the function HAL_SD_CheckWriteOperation()
-  *         to check the completion of the write process (by SD current status polling).  
-  * @param  hsd: SD handle
-  * @param  pWriteBuffer: pointer to the buffer that will contain the data to transmit
-  * @param  BlockNumber: Block number to where data is to be written (byte address = BlockNumber * BlockSize)
-  * @param  BlockSize: the SD card Data block size 
-  * @note   BlockSize must be 512 bytes.
-  * @param  NumberOfBlocks: Number of blocks to write
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_BlockNumber_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint32_t BlockNumber, uint32_t BlockSize, uint32_t NumberOfBlocks)
-{
-  SDIO_CmdInitTypeDef sdio_cmdinitstructure;
-  SDIO_DataInitTypeDef sdio_datainitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  
-  /* Initialize data control register */
-  hsd->Instance->DCTRL = 0U;
-  
-  /* Initialize handle flags */
-  hsd->SdTransferCplt  = 0U;
-  hsd->DmaTransferCplt = 0U;
-  hsd->SdTransferErr   = SD_OK;
-  
-  /* Initialize SD Write operation */
-  if(NumberOfBlocks > 1U)
-  {
-    hsd->SdOperation = SD_WRITE_MULTIPLE_BLOCK;
-  }
-  else
-  {
-    hsd->SdOperation = SD_WRITE_SINGLE_BLOCK;
-  }  
-  
-  /* Enable transfer interrupts */
-#ifdef SDIO_STA_STBITERR
-  __HAL_SD_SDIO_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL |\
-                                SDIO_IT_DTIMEOUT |\
-                                SDIO_IT_DATAEND  |\
-                                SDIO_IT_TXUNDERR |\
-                                SDIO_IT_STBITERR));
-#else /* SDIO_STA_STBITERR not defined */
-  __HAL_SD_SDIO_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL |\
-                                SDIO_IT_DTIMEOUT |\
-                                SDIO_IT_DATAEND  |\
-                                SDIO_IT_TXUNDERR));
-#endif /* SDIO_STA_STBITERR */
-  
-  /* Configure DMA user callbacks */
-  hsd->hdmatx->XferCpltCallback  = SD_DMA_TxCplt;
-  hsd->hdmatx->XferErrorCallback = SD_DMA_TxError;
-  
-  /* Enable the DMA Stream */
-  HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pWriteBuffer, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BlockSize * NumberOfBlocks)/4);
-
-  /* Enable SDIO DMA transfer */
-  __HAL_SD_SDIO_DMA_ENABLE();
-  
-  uint32_t WriteAddr;
-  if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
-  {
-    BlockSize = 512;
-    WriteAddr = BlockNumber;
-  }
-  else
-  {
-    // should not overflow for standard-capacity cards
-    WriteAddr = BlockNumber * BlockSize;
-  }
-
-  /* Set Block Size for Card */ 
-  sdio_cmdinitstructure.Argument         = (uint32_t)BlockSize;
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
-  sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-  sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-  sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
-
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Check number of blocks command */
-  if(NumberOfBlocks <= 1U)
-  {
-    /* Send CMD24 WRITE_SINGLE_BLOCK */
-    sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK;
-  }
-  else
-  {
-    /* Send CMD25 WRITE_MULT_BLOCK with argument data address */
-    sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK;
-  }
-  
-  sdio_cmdinitstructure.Argument         = WriteAddr;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-
-  /* Check for error conditions */
-  if(NumberOfBlocks > 1U)
-  {
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK);
-  }
-  else
-  {
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK);
-  }
-  
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Configure the SD DPSM (Data Path State Machine) */ 
-  sdio_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
-  sdio_datainitstructure.DataLength    = BlockSize * NumberOfBlocks;
-  sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
-  sdio_datainitstructure.TransferDir   = SDIO_TRANSFER_DIR_TO_CARD;
-  sdio_datainitstructure.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
-  sdio_datainitstructure.DPSM          = SDIO_DPSM_ENABLE;
-  SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
-  
-  hsd->SdTransferErr = errorstate;
-  
-  return errorstate;
-}
-
-/**
-  * @brief  This function waits until the SD DMA data read transfer is finished. 
-  *         This API should be called after HAL_SD_ReadBlocks_DMA() function
-  *         to insure that all data sent by the card is already transferred by the 
-  *         DMA controller.
-  * @param  hsd: SD handle
-  * @param  Timeout: Timeout duration  
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t timeout = Timeout;
-  uint32_t tmp1, tmp2;
-  HAL_SD_ErrorTypedef tmp3;
-  
-  /* Wait for DMA/SD transfer end or SD error variables to be in SD handle */
-  tmp1 = hsd->DmaTransferCplt; 
-  tmp2 = hsd->SdTransferCplt;
-  tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;
-    
-  while ((tmp1 == 0U) && (tmp2 == 0U) && (tmp3 == SD_OK) && (timeout > 0U))
-  {
-    tmp1 = hsd->DmaTransferCplt; 
-    tmp2 = hsd->SdTransferCplt;
-    tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;    
-    timeout--;
-  }
-  
-  timeout = Timeout;
-  
-  /* Wait until the Rx transfer is no longer active */
-  while((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXACT)) && (timeout > 0U))
-  {
-    timeout--;  
-  }
-  
-  /* Send stop command in multiblock read */
-  if (hsd->SdOperation == SD_READ_MULTIPLE_BLOCK)
-  {
-    errorstate = HAL_SD_StopTransfer(hsd);
-  }
-  
-  if ((timeout == 0U) && (errorstate == SD_OK))
-  {
-    errorstate = SD_DATA_TIMEOUT;
-  }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-  
-  /* Return error state */
-  if (hsd->SdTransferErr != SD_OK)
-  {
-    return (HAL_SD_ErrorTypedef)(hsd->SdTransferErr);
-  }
-  
-  return errorstate;
-}
-
-/**
-  * @brief  This function waits until the SD DMA data write transfer is finished. 
-  *         This API should be called after HAL_SD_WriteBlocks_DMA() function
-  *         to insure that all data sent by the card is already transferred by the 
-  *         DMA controller.
-  * @param  hsd: SD handle
-  * @param  Timeout: Timeout duration  
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t timeout = Timeout;
-  uint32_t tmp1, tmp2;
-  HAL_SD_ErrorTypedef tmp3;
-
-  /* Wait for DMA/SD transfer end or SD error variables to be in SD handle */
-  tmp1 = hsd->DmaTransferCplt; 
-  tmp2 = hsd->SdTransferCplt;
-  tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;
-    
-  while ((tmp1 == 0U) && (tmp2 == 0U) && (tmp3 == SD_OK) && (timeout > 0U))
-  {
-    tmp1 = hsd->DmaTransferCplt; 
-    tmp2 = hsd->SdTransferCplt;
-    tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;
-    timeout--;
-  }
-  
-  timeout = Timeout;
-  
-  /* Wait until the Tx transfer is no longer active */
-  while((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXACT))  && (timeout > 0U))
-  {
-    timeout--;  
-  }
-
-  /* Send stop command in multiblock write */
-  if (hsd->SdOperation == SD_WRITE_MULTIPLE_BLOCK)
-  {
-    errorstate = HAL_SD_StopTransfer(hsd);
-  }
-  
-  if ((timeout == 0U) && (errorstate == SD_OK))
-  {
-    errorstate = SD_DATA_TIMEOUT;
-  }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-  
-  /* Return error state */
-  if (hsd->SdTransferErr != SD_OK)
-  {
-    return (HAL_SD_ErrorTypedef)(hsd->SdTransferErr);
-  }
-  
-  /* Wait until write is complete */
-  while(HAL_SD_GetStatus(hsd) != SD_TRANSFER_OK)
-  {    
-  }
-
-  return errorstate; 
-}
-
-/**
-  * @brief  Erases the specified memory area of the given SD card.
-  * @param  hsd: SD handle 
-  * @param  startaddr: Start byte address
-  * @param  endaddr: End byte address
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  SDIO_CmdInitTypeDef sdio_cmdinitstructure;
-  
-  uint32_t delay         = 0U;
-  __IO uint32_t maxdelay = 0U;
-  uint8_t cardstate      = 0U;
-  
-  /* Check if the card command class supports erase command */
-  if (((hsd->CSD[1U] >> 20U) & SD_CCCC_ERASE) == 0U)
-  {
-    errorstate = SD_REQUEST_NOT_APPLICABLE;
-    
-    return errorstate;
-  }
-  
-  /* Get max delay value */
-  maxdelay = 120000U / (((hsd->Instance->CLKCR) & 0xFFU) + 2U);
-  
-  if((SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
-  {
-    errorstate = SD_LOCK_UNLOCK_FAILED;
-    
-    return errorstate;
-  }
-  
-  /* Get start and end block for high capacity cards */
-  if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
-  {
-    startaddr /= 512U;
-    endaddr   /= 512U;
-  }
-  
-  /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */
-  if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
-    (hsd->CardType == HIGH_CAPACITY_SD_CARD))
-  {
-    /* Send CMD32 SD_ERASE_GRP_START with argument as addr  */
-    sdio_cmdinitstructure.Argument         =(uint32_t)startaddr;
-    sdio_cmdinitstructure.CmdIndex         = SD_CMD_SD_ERASE_GRP_START;
-    sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-    sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-    sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-    SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_START);
-    
-    if (errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-    
-    /* Send CMD33 SD_ERASE_GRP_END with argument as addr  */
-    sdio_cmdinitstructure.Argument         = (uint32_t)endaddr;
-    sdio_cmdinitstructure.CmdIndex         = SD_CMD_SD_ERASE_GRP_END;
-    SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_END);
-    
-    if (errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-  }
-  
-  /* Send CMD38 ERASE */
-  sdio_cmdinitstructure.Argument         = 0U;
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_ERASE;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_ERASE);
-  
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  for (; delay < maxdelay; delay++)
-  {
-  }
-  
-  /* Wait until the card is in programming state */
-  errorstate = SD_IsCardProgramming(hsd, &cardstate);
-  
-  delay = SD_DATATIMEOUT;
-  
-  while ((delay > 0U) && (errorstate == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING)))
-  {
-    errorstate = SD_IsCardProgramming(hsd, &cardstate);
-    delay--;
-  }
-  
-  return errorstate;
-}
-
-/**
-  * @brief  This function handles SD card interrupt request.
-  * @param  hsd: SD handle
-  * @retval None
-  */
-void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
-{  
-  /* Check for SDIO interrupt flags */
-  if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_DATAEND))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_IT_DATAEND);  
-      
-    /* SD transfer is complete */
-    hsd->SdTransferCplt = 1U;
-
-    /* No transfer error */ 
-    hsd->SdTransferErr  = SD_OK;
-
-    HAL_SD_XferCpltCallback(hsd);  
-  }  
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_DCRCFAIL))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
-    
-    hsd->SdTransferErr = SD_DATA_CRC_FAIL;
-    
-    HAL_SD_XferErrorCallback(hsd);
-    
-  }
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_DTIMEOUT))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
-    
-    hsd->SdTransferErr = SD_DATA_TIMEOUT;
-    
-    HAL_SD_XferErrorCallback(hsd);
-  }
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_RXOVERR))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
-    
-    hsd->SdTransferErr = SD_RX_OVERRUN;
-    
-    HAL_SD_XferErrorCallback(hsd);
-  }
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_TXUNDERR))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_TXUNDERR);
-    
-    hsd->SdTransferErr = SD_TX_UNDERRUN;
-    
-    HAL_SD_XferErrorCallback(hsd);
-  }
-#ifdef SDIO_STA_STBITERR
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_STBITERR))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
-    
-    hsd->SdTransferErr = SD_START_BIT_ERR;
-    
-    HAL_SD_XferErrorCallback(hsd);
-  }
-#endif /* SDIO_STA_STBITERR */
-  else
-  {
-    /* No error flag set */
-  }
-
-  /* Disable all SDIO peripheral interrupt sources */
-#ifdef SDIO_STA_STBITERR
-  __HAL_SD_SDIO_DISABLE_IT(hsd, SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND  |\
-                                SDIO_IT_TXFIFOHE | SDIO_IT_RXFIFOHF | SDIO_IT_TXUNDERR |\
-                                SDIO_IT_RXOVERR  | SDIO_IT_STBITERR);
-#else /* SDIO_STA_STBITERR not defined */
-  __HAL_SD_SDIO_DISABLE_IT(hsd, SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND  |\
-                                SDIO_IT_TXFIFOHE | SDIO_IT_RXFIFOHF | SDIO_IT_TXUNDERR |\
-                                SDIO_IT_RXOVERR);
-#endif /* SDIO_STA_STBITERR */
-}
-
-
-/**
-  * @brief  SD end of transfer callback.
-  * @param  hsd: SD handle 
-  * @retval None
-  */
-__weak void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsd);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SD_XferCpltCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  SD Transfer Error callback.
-  * @param  hsd: SD handle
-  * @retval None
-  */
-__weak void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsd);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SD_XferErrorCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  SD Transfer complete Rx callback in non blocking mode.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-__weak void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdma);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SD_DMA_RxCpltCallback could be implemented in the user file
-   */ 
-}  
-
-/**
-  * @brief  SD DMA transfer complete Rx error callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-__weak void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdma);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SD_DMA_RxErrorCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  SD Transfer complete Tx callback in non blocking mode.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-__weak void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdma);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SD_DMA_TxCpltCallback could be implemented in the user file
-   */ 
-}  
-
-/**
-  * @brief  SD DMA transfer complete error Tx callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-__weak void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdma);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SD_DMA_TxErrorCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup SD_Exported_Functions_Group3
- *  @brief   management functions 
- *
-@verbatim   
-  ==============================================================================
-                      ##### Peripheral Control functions #####
-  ==============================================================================  
-  [..]
-    This subsection provides a set of functions allowing to control the SD card 
-    operations.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Returns information about specific card.
-  * @param  hsd: SD handle
-  * @param  pCardInfo: Pointer to a HAL_SD_CardInfoTypedef structure that  
-  *         contains all SD cardinformation  
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t tmp = 0U;
-  
-  pCardInfo->CardType = (uint8_t)(hsd->CardType);
-  pCardInfo->RCA      = (uint16_t)(hsd->RCA);
-  
-  /* Byte 0 */
-  tmp = (hsd->CSD[0U] & 0xFF000000U) >> 24U;
-  pCardInfo->SD_csd.CSDStruct      = (uint8_t)((tmp & 0xC0U) >> 6U);
-  pCardInfo->SD_csd.SysSpecVersion = (uint8_t)((tmp & 0x3CU) >> 2U);
-  pCardInfo->SD_csd.Reserved1      = tmp & 0x03U;
-  
-  /* Byte 1 */
-  tmp = (hsd->CSD[0U] & 0x00FF0000U) >> 16U;
-  pCardInfo->SD_csd.TAAC = (uint8_t)tmp;
-  
-  /* Byte 2 */
-  tmp = (hsd->CSD[0U] & 0x0000FF00U) >> 8U;
-  pCardInfo->SD_csd.NSAC = (uint8_t)tmp;
-  
-  /* Byte 3 */
-  tmp = hsd->CSD[0U] & 0x000000FFU;
-  pCardInfo->SD_csd.MaxBusClkFrec = (uint8_t)tmp;
-  
-  /* Byte 4 */
-  tmp = (hsd->CSD[1U] & 0xFF000000U) >> 24U;
-  pCardInfo->SD_csd.CardComdClasses = (uint16_t)(tmp << 4U);
-  
-  /* Byte 5 */
-  tmp = (hsd->CSD[1U] & 0x00FF0000U) >> 16U;
-  pCardInfo->SD_csd.CardComdClasses |= (uint16_t)((tmp & 0xF0) >> 4U);
-  pCardInfo->SD_csd.RdBlockLen       = (uint8_t)(tmp & 0x0FU);
-  
-  /* Byte 6 */
-  tmp = (hsd->CSD[1U] & 0x0000FF00U) >> 8U;
-  pCardInfo->SD_csd.PartBlockRead   = (uint8_t)((tmp & 0x80U) >> 7U);
-  pCardInfo->SD_csd.WrBlockMisalign = (uint8_t)((tmp & 0x40U) >> 6U);
-  pCardInfo->SD_csd.RdBlockMisalign = (uint8_t)((tmp & 0x20U) >> 5U);
-  pCardInfo->SD_csd.DSRImpl         = (uint8_t)((tmp & 0x10U) >> 4U);
-  pCardInfo->SD_csd.Reserved2       = 0U; /*!< Reserved */
-  
-  if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0))
-  {
-    pCardInfo->SD_csd.DeviceSize = (tmp & 0x03U) << 10U;
-    
-    /* Byte 7 */
-    tmp = (uint8_t)(hsd->CSD[1U] & 0x000000FFU);
-    pCardInfo->SD_csd.DeviceSize |= (tmp) << 2U;
-    
-    /* Byte 8 */
-    tmp = (uint8_t)((hsd->CSD[2U] & 0xFF000000U) >> 24U);
-    pCardInfo->SD_csd.DeviceSize |= (tmp & 0xC0U) >> 6U;
-    
-    pCardInfo->SD_csd.MaxRdCurrentVDDMin = (tmp & 0x38U) >> 3U;
-    pCardInfo->SD_csd.MaxRdCurrentVDDMax = (tmp & 0x07U);
-    
-    /* Byte 9 */
-    tmp = (uint8_t)((hsd->CSD[2U] & 0x00FF0000U) >> 16U);
-    pCardInfo->SD_csd.MaxWrCurrentVDDMin = (tmp & 0xE0U) >> 5U;
-    pCardInfo->SD_csd.MaxWrCurrentVDDMax = (tmp & 0x1CU) >> 2U;
-    pCardInfo->SD_csd.DeviceSizeMul      = (tmp & 0x03U) << 1U;
-    /* Byte 10 */
-    tmp = (uint8_t)((hsd->CSD[2U] & 0x0000FF00U) >> 8U);
-    pCardInfo->SD_csd.DeviceSizeMul |= (tmp & 0x80U) >> 7U;
-    
-    pCardInfo->CardCapacity  = (pCardInfo->SD_csd.DeviceSize + 1U) ;
-    pCardInfo->CardCapacity *= (1U << (pCardInfo->SD_csd.DeviceSizeMul + 2U));
-    pCardInfo->CardBlockSize = 1U << (pCardInfo->SD_csd.RdBlockLen);
-    pCardInfo->CardCapacity *= pCardInfo->CardBlockSize;
-  }
-  else if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
-  {
-    /* Byte 7 */
-    tmp = (uint8_t)(hsd->CSD[1U] & 0x000000FFU);
-    pCardInfo->SD_csd.DeviceSize = (tmp & 0x3FU) << 16U;
-    
-    /* Byte 8 */
-    tmp = (uint8_t)((hsd->CSD[2U] & 0xFF000000U) >> 24U);
-    
-    pCardInfo->SD_csd.DeviceSize |= (tmp << 8U);
-    
-    /* Byte 9 */
-    tmp = (uint8_t)((hsd->CSD[2U] & 0x00FF0000U) >> 16U);
-    
-    pCardInfo->SD_csd.DeviceSize |= (tmp);
-    
-    /* Byte 10 */
-    tmp = (uint8_t)((hsd->CSD[2U] & 0x0000FF00U) >> 8U);
-    
-    pCardInfo->CardCapacity = (uint64_t)((((uint64_t)pCardInfo->SD_csd.DeviceSize + 1ULL)) * 512U * 1024U);
-    pCardInfo->CardBlockSize = 512U;    
-  }
-  else
-  {
-    /* Not supported card type */
-    errorstate = SD_ERROR;
-  }
-    
-  pCardInfo->SD_csd.EraseGrSize = (tmp & 0x40U) >> 6U;
-  pCardInfo->SD_csd.EraseGrMul  = (tmp & 0x3FU) << 1U;
-  
-  /* Byte 11 */
-  tmp = (uint8_t)(hsd->CSD[2U] & 0x000000FFU);
-  pCardInfo->SD_csd.EraseGrMul     |= (tmp & 0x80U) >> 7U;
-  pCardInfo->SD_csd.WrProtectGrSize = (tmp & 0x7FU);
-  
-  /* Byte 12 */
-  tmp = (uint8_t)((hsd->CSD[3U] & 0xFF000000U) >> 24U);
-  pCardInfo->SD_csd.WrProtectGrEnable = (tmp & 0x80U) >> 7U;
-  pCardInfo->SD_csd.ManDeflECC        = (tmp & 0x60U) >> 5U;
-  pCardInfo->SD_csd.WrSpeedFact       = (tmp & 0x1CU) >> 2U;
-  pCardInfo->SD_csd.MaxWrBlockLen     = (tmp & 0x03U) << 2U;
-  
-  /* Byte 13 */
-  tmp = (uint8_t)((hsd->CSD[3U] & 0x00FF0000U) >> 16U);
-  pCardInfo->SD_csd.MaxWrBlockLen      |= (tmp & 0xC0U) >> 6U;
-  pCardInfo->SD_csd.WriteBlockPaPartial = (tmp & 0x20U) >> 5U;
-  pCardInfo->SD_csd.Reserved3           = 0U;
-  pCardInfo->SD_csd.ContentProtectAppli = (tmp & 0x01U);
-  
-  /* Byte 14 */
-  tmp = (uint8_t)((hsd->CSD[3U] & 0x0000FF00U) >> 8U);
-  pCardInfo->SD_csd.FileFormatGrouop = (tmp & 0x80U) >> 7U;
-  pCardInfo->SD_csd.CopyFlag         = (tmp & 0x40U) >> 6U;
-  pCardInfo->SD_csd.PermWrProtect    = (tmp & 0x20U) >> 5U;
-  pCardInfo->SD_csd.TempWrProtect    = (tmp & 0x10U) >> 4U;
-  pCardInfo->SD_csd.FileFormat       = (tmp & 0x0CU) >> 2U;
-  pCardInfo->SD_csd.ECC              = (tmp & 0x03U);
-  
-  /* Byte 15 */
-  tmp = (uint8_t)(hsd->CSD[3U] & 0x000000FFU);
-  pCardInfo->SD_csd.CSD_CRC   = (tmp & 0xFEU) >> 1U;
-  pCardInfo->SD_csd.Reserved4 = 1U;
-  
-  /* Byte 0 */
-  tmp = (uint8_t)((hsd->CID[0U] & 0xFF000000U) >> 24U);
-  pCardInfo->SD_cid.ManufacturerID = tmp;
-  
-  /* Byte 1 */
-  tmp = (uint8_t)((hsd->CID[0U] & 0x00FF0000U) >> 16U);
-  pCardInfo->SD_cid.OEM_AppliID = tmp << 8U;
-  
-  /* Byte 2 */
-  tmp = (uint8_t)((hsd->CID[0U] & 0x0000FF00U) >> 8U);
-  pCardInfo->SD_cid.OEM_AppliID |= tmp;
-  
-  /* Byte 3 */
-  tmp = (uint8_t)(hsd->CID[0U] & 0x000000FFU);
-  pCardInfo->SD_cid.ProdName1 = tmp << 24U;
-  
-  /* Byte 4 */
-  tmp = (uint8_t)((hsd->CID[1U] & 0xFF000000U) >> 24U);
-  pCardInfo->SD_cid.ProdName1 |= tmp << 16U;
-  
-  /* Byte 5 */
-  tmp = (uint8_t)((hsd->CID[1U] & 0x00FF0000U) >> 16U);
-  pCardInfo->SD_cid.ProdName1 |= tmp << 8U;
-  
-  /* Byte 6 */
-  tmp = (uint8_t)((hsd->CID[1U] & 0x0000FF00U) >> 8U);
-  pCardInfo->SD_cid.ProdName1 |= tmp;
-  
-  /* Byte 7 */
-  tmp = (uint8_t)(hsd->CID[1U] & 0x000000FFU);
-  pCardInfo->SD_cid.ProdName2 = tmp;
-  
-  /* Byte 8 */
-  tmp = (uint8_t)((hsd->CID[2U] & 0xFF000000U) >> 24U);
-  pCardInfo->SD_cid.ProdRev = tmp;
-  
-  /* Byte 9 */
-  tmp = (uint8_t)((hsd->CID[2U] & 0x00FF0000U) >> 16U);
-  pCardInfo->SD_cid.ProdSN = tmp << 24U;
-  
-  /* Byte 10 */
-  tmp = (uint8_t)((hsd->CID[2U] & 0x0000FF00U) >> 8U);
-  pCardInfo->SD_cid.ProdSN |= tmp << 16U;
-  
-  /* Byte 11 */
-  tmp = (uint8_t)(hsd->CID[2U] & 0x000000FFU);
-  pCardInfo->SD_cid.ProdSN |= tmp << 8U;
-  
-  /* Byte 12 */
-  tmp = (uint8_t)((hsd->CID[3U] & 0xFF000000U) >> 24U);
-  pCardInfo->SD_cid.ProdSN |= tmp;
-  
-  /* Byte 13 */
-  tmp = (uint8_t)((hsd->CID[3U] & 0x00FF0000U) >> 16U);
-  pCardInfo->SD_cid.Reserved1   |= (tmp & 0xF0U) >> 4U;
-  pCardInfo->SD_cid.ManufactDate = (tmp & 0x0FU) << 8U;
-  
-  /* Byte 14 */
-  tmp = (uint8_t)((hsd->CID[3U] & 0x0000FF00U) >> 8U);
-  pCardInfo->SD_cid.ManufactDate |= tmp;
-  
-  /* Byte 15 */
-  tmp = (uint8_t)(hsd->CID[3U] & 0x000000FFU);
-  pCardInfo->SD_cid.CID_CRC   = (tmp & 0xFEU) >> 1U;
-  pCardInfo->SD_cid.Reserved2 = 1U;
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Enables wide bus operation for the requested card if supported by 
-  *         card.
-  * @param  hsd: SD handle       
-  * @param  WideMode: Specifies the SD card wide bus mode 
-  *          This parameter can be one of the following values:
-  *            @arg SDIO_BUS_WIDE_8B: 8-bit data transfer (Only for MMC)
-  *            @arg SDIO_BUS_WIDE_4B: 4-bit data transfer
-  *            @arg SDIO_BUS_WIDE_1B: 1-bit data transfer
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  SDIO_InitTypeDef tmpinit;
-  
-  /* MMC Card does not support this feature */
-  if (hsd->CardType == MULTIMEDIA_CARD)
-  {
-    errorstate = SD_UNSUPPORTED_FEATURE;
-    
-    return errorstate;
-  }
-  else if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
-    (hsd->CardType == HIGH_CAPACITY_SD_CARD))
-  {
-    if (WideMode == SDIO_BUS_WIDE_8B)
-    {
-      errorstate = SD_UNSUPPORTED_FEATURE;
-    }
-    else if (WideMode == SDIO_BUS_WIDE_4B)
-    {
-      errorstate = SD_WideBus_Enable(hsd);
-    }
-    else if (WideMode == SDIO_BUS_WIDE_1B)
-    {
-      errorstate = SD_WideBus_Disable(hsd);
-    }
-    else
-    {
-      /* WideMode is not a valid argument*/
-      errorstate = SD_INVALID_PARAMETER;
-    }
-      
-    if (errorstate == SD_OK)
-    {
-      /* Configure the SDIO peripheral */
-      tmpinit.ClockEdge           = hsd->Init.ClockEdge;
-      tmpinit.ClockBypass         = hsd->Init.ClockBypass;
-      tmpinit.ClockPowerSave      = hsd->Init.ClockPowerSave;
-      tmpinit.BusWide             = WideMode;
-      tmpinit.HardwareFlowControl = hsd->Init.HardwareFlowControl;
-      tmpinit.ClockDiv            = hsd->Init.ClockDiv;
-      SDIO_Init(hsd->Instance, tmpinit);
-    }
-  }
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Aborts an ongoing data transfer.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd)
-{
-  SDIO_CmdInitTypeDef sdio_cmdinitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  
-  /* Send CMD12 STOP_TRANSMISSION  */
-  sdio_cmdinitstructure.Argument         = 0U;
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_STOP_TRANSMISSION;
-  sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-  sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-  sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_STOP_TRANSMISSION);
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Switches the SD card to High Speed mode.
-  *         This API must be used after "Transfer State"
-  * @note   This operation should be followed by the configuration 
-  *         of PLL to have SDIOCK clock between 67 and 75 MHz
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  SDIO_CmdInitTypeDef sdio_cmdinitstructure;
-  SDIO_DataInitTypeDef sdio_datainitstructure;
-  
-  uint8_t SD_hs[64U]  = {0U};
-  uint32_t SD_scr[2U] = {0U, 0U};
-  uint32_t SD_SPEC    = 0U;
-  uint32_t count = 0U, *tempbuff = (uint32_t *)SD_hs;
-  
-  /* Initialize the Data control register */
-  hsd->Instance->DCTRL = 0U;
-  
-  /* Get SCR Register */
-  errorstate = SD_FindSCR(hsd, SD_scr);
-  
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Test the Version supported by the card*/ 
-  SD_SPEC = (SD_scr[1U]  & 0x01000000U) | (SD_scr[1U]  & 0x02000000U);
-  
-  if (SD_SPEC != SD_ALLZERO)
-  {
-    /* Set Block Size for Card */
-    sdio_cmdinitstructure.Argument         = (uint32_t)64U;
-    sdio_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
-    sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-    sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-    sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-    SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
-    
-    if (errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-    
-    /* Configure the SD DPSM (Data Path State Machine) */
-    sdio_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
-    sdio_datainitstructure.DataLength    = 64U;
-    sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_64B ;
-    sdio_datainitstructure.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
-    sdio_datainitstructure.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
-    sdio_datainitstructure.DPSM          = SDIO_DPSM_ENABLE;
-    SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
-    
-    /* Send CMD6 switch mode */
-    sdio_cmdinitstructure.Argument         = 0x80FFFF01U;
-    sdio_cmdinitstructure.CmdIndex         = SD_CMD_HS_SWITCH;
-    SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); 
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_HS_SWITCH);
-    
-    if (errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-#ifdef SDIO_STA_STBITERR        
-    while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
-#else /* SDIO_STA_STBITERR */
-    while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))      
-#endif /* SDIO_STA_STBITERR */
-    {
-      if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
-      {
-        for (count = 0U; count < 8U; count++)
-        {
-          *(tempbuff + count) = SDIO_ReadFIFO(hsd->Instance);
-        }
-        
-        tempbuff += 8U;
-      }
-    }
-    
-    if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
-    {
-      __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
-      
-      errorstate = SD_DATA_TIMEOUT;
-      
-      return errorstate;
-    }
-    else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
-    {
-      __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
-      
-      errorstate = SD_DATA_CRC_FAIL;
-      
-      return errorstate;
-    }
-    else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
-    {
-      __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
-      
-      errorstate = SD_RX_OVERRUN;
-      
-      return errorstate;
-    }
-#ifdef SDIO_STA_STBITERR
-    else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
-    {
-      __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
-      
-      errorstate = SD_START_BIT_ERR;
-      
-      return errorstate;
-    }
-#endif /* SDIO_STA_STBITERR */
-    else
-    {
-      /* No error flag set */
-    }
-    
-    count = SD_DATATIMEOUT;
-    
-    while ((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (count > 0U))
-    {
-      *tempbuff = SDIO_ReadFIFO(hsd->Instance);
-      tempbuff++;
-      count--;
-    }
-    
-    /* Clear all the static flags */
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-    
-    /* Test if the switch mode HS is ok */
-    if ((SD_hs[13U]& 2U) != 2U)
-    {
-      errorstate = SD_UNSUPPORTED_FEATURE;
-    } 
-  }
-  
-  return errorstate;
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup SD_Exported_Functions_Group4
- *  @brief   Peripheral State functions 
- *
-@verbatim   
-  ==============================================================================
-                      ##### Peripheral State functions #####
-  ==============================================================================  
-  [..]
-    This subsection permits to get in runtime the status of the peripheral 
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Returns the current SD card's status.
-  * @param  hsd: SD handle
-  * @param  pSDstatus: Pointer to the buffer that will contain the SD card status 
-  *         SD Status register)
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
-{
-  SDIO_CmdInitTypeDef  sdio_cmdinitstructure;
-  SDIO_DataInitTypeDef sdio_datainitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t count = 0U;
-  
-  /* Check SD response */
-  if ((SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
-  {
-    errorstate = SD_LOCK_UNLOCK_FAILED;
-    
-    return errorstate;
-  }
-  
-  /* Set block size for card if it is not equal to current block size for card */
-  sdio_cmdinitstructure.Argument         = 64U;
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
-  sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-  sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-  sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
-  
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Send CMD55 */
-  sdio_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16U);
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
-  
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Configure the SD DPSM (Data Path State Machine) */ 
-  sdio_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
-  sdio_datainitstructure.DataLength    = 64U;
-  sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_64B;
-  sdio_datainitstructure.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
-  sdio_datainitstructure.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
-  sdio_datainitstructure.DPSM          = SDIO_DPSM_ENABLE;
-  SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
-  
-  /* Send ACMD13 (SD_APP_STATUS)  with argument as card's RCA */
-  sdio_cmdinitstructure.Argument         = 0U;
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_SD_APP_STATUS;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_STATUS);
-  
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Get status data */
-#ifdef SDIO_STA_STBITERR 
-  while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
-#else /* SDIO_STA_STBITERR not defined */
-  while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))    
-#endif /* SDIO_STA_STBITERR */
-  {
-    if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
-    {
-      for (count = 0U; count < 8U; count++)
-      {
-        *(pSDstatus + count) = SDIO_ReadFIFO(hsd->Instance);
-      }
-      
-      pSDstatus += 8U;
-    }
-  }
-  
-  if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
-    
-    errorstate = SD_DATA_TIMEOUT;
-    
-    return errorstate;
-  }
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
-    
-    errorstate = SD_DATA_CRC_FAIL;
-    
-    return errorstate;
-  }
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
-    
-    errorstate = SD_RX_OVERRUN;
-    
-    return errorstate;
-  }
-#ifdef SDIO_STA_STBITERR
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
-    
-    errorstate = SD_START_BIT_ERR;
-    
-    return errorstate;
-  }
-#endif /* SDIO_STA_STBITERR */
-  else
-  {
-    /* No error flag set */
-  }  
-  
-  count = SD_DATATIMEOUT;
-  while ((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (count > 0U))
-  {
-    *pSDstatus = SDIO_ReadFIFO(hsd->Instance);
-    pSDstatus++;
-    count--;
-  }
-  
-  /* Clear all the static status flags*/
-  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Gets the current sd card data status.
-  * @param  hsd: SD handle
-  * @retval Data Transfer state
-  */
-HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd)
-{
-  HAL_SD_CardStateTypedef cardstate =  SD_CARD_TRANSFER;
-
-  /* Get SD card state */
-  cardstate = SD_GetState(hsd);
-  
-  /* Find SD status according to card state*/
-  if (cardstate == SD_CARD_TRANSFER)
-  {
-    return SD_TRANSFER_OK;
-  }
-  else if(cardstate == SD_CARD_ERROR)
-  {
-    return SD_TRANSFER_ERROR;
-  }
-  else
-  {
-    return SD_TRANSFER_BUSY;
-  }
-}
-
-/**
-  * @brief  Gets the SD card status.
-  * @param  hsd: SD handle      
-  * @param  pCardStatus: Pointer to the HAL_SD_CardStatusTypedef structure that 
-  *         will contain the SD card status information 
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t tmp = 0U;
-  uint32_t sd_status[16U];
-  
-  errorstate = HAL_SD_SendSDStatus(hsd, sd_status);
-  
-  if (errorstate  != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Byte 0 */
-  tmp = (sd_status[0U] & 0xC0U) >> 6U;
-  pCardStatus->DAT_BUS_WIDTH = (uint8_t)tmp;
-  
-  /* Byte 0 */
-  tmp = (sd_status[0U] & 0x20U) >> 5U;
-  pCardStatus->SECURED_MODE = (uint8_t)tmp;
-  
-  /* Byte 2 */
-  tmp = (sd_status[2U] & 0xFFU);
-  pCardStatus->SD_CARD_TYPE = (uint8_t)(tmp << 8U);
-  
-  /* Byte 3 */
-  tmp = (sd_status[3U] & 0xFFU);
-  pCardStatus->SD_CARD_TYPE |= (uint8_t)tmp;
-  
-  /* Byte 4 */
-  tmp = (sd_status[4U] & 0xFFU);
-  pCardStatus->SIZE_OF_PROTECTED_AREA = (uint8_t)(tmp << 24U);
-  
-  /* Byte 5 */
-  tmp = (sd_status[5U] & 0xFFU);
-  pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)(tmp << 16U);
-  
-  /* Byte 6 */
-  tmp = (sd_status[6U] & 0xFFU);
-  pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)(tmp << 8U);
-  
-  /* Byte 7 */
-  tmp = (sd_status[7U] & 0xFFU);
-  pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)tmp;
-  
-  /* Byte 8 */
-  tmp = (sd_status[8U] & 0xFFU);
-  pCardStatus->SPEED_CLASS = (uint8_t)tmp;
-  
-  /* Byte 9 */
-  tmp = (sd_status[9U] & 0xFFU);
-  pCardStatus->PERFORMANCE_MOVE = (uint8_t)tmp;
-  
-  /* Byte 10 */
-  tmp = (sd_status[10U] & 0xF0U) >> 4U;
-  pCardStatus->AU_SIZE = (uint8_t)tmp;
-  
-  /* Byte 11 */
-  tmp = (sd_status[11U] & 0xFFU);
-  pCardStatus->ERASE_SIZE = (uint8_t)(tmp << 8U);
-  
-  /* Byte 12 */
-  tmp = (sd_status[12U] & 0xFFU);
-  pCardStatus->ERASE_SIZE |= (uint8_t)tmp;
-  
-  /* Byte 13 */
-  tmp = (sd_status[13U] & 0xFCU) >> 2U;
-  pCardStatus->ERASE_TIMEOUT = (uint8_t)tmp;
-  
-  /* Byte 13 */
-  tmp = (sd_status[13U] & 0x3U);
-  pCardStatus->ERASE_OFFSET = (uint8_t)tmp;
-  
-  return errorstate;
-}
-         
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-
-/* Private function ----------------------------------------------------------*/  
-/** @addtogroup SD_Private_Functions
-  * @{
-  */
-  
-/**
-  * @brief  SD DMA transfer complete Rx callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma)
-{
-  SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-  
-  /* DMA transfer is complete */
-  hsd->DmaTransferCplt = 1U;
-  
-  /* Wait until SD transfer is complete */
-  while(hsd->SdTransferCplt == 0U)
-  {
-  }
-  
-  /* Disable the DMA channel */
-  HAL_DMA_Abort(hdma);
-
-  /* Transfer complete user callback */
-  HAL_SD_DMA_RxCpltCallback(hsd->hdmarx);   
-}
-
-/**
-  * @brief  SD DMA transfer Error Rx callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SD_DMA_RxError(DMA_HandleTypeDef *hdma)
-{
-  SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-  
-  /* Transfer complete user callback */
-  HAL_SD_DMA_RxErrorCallback(hsd->hdmarx);
-}
-
-/**
-  * @brief  SD DMA transfer complete Tx callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma)
-{
-  SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-  
-  /* DMA transfer is complete */
-  hsd->DmaTransferCplt = 1U;
-  
-  /* Wait until SD transfer is complete */
-  while(hsd->SdTransferCplt == 0U)
-  {
-  }
- 
-  /* Disable the DMA channel */
-  HAL_DMA_Abort(hdma);
-
-  /* Transfer complete user callback */
-  HAL_SD_DMA_TxCpltCallback(hsd->hdmatx);  
-}
-
-/**
-  * @brief  SD DMA transfer Error Tx callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SD_DMA_TxError(DMA_HandleTypeDef *hdma)
-{
-  SD_HandleTypeDef *hsd = ( SD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  /* Transfer complete user callback */
-  HAL_SD_DMA_TxErrorCallback(hsd->hdmatx);
-}
-
-/**
-  * @brief  Returns the SD current state.
-  * @param  hsd: SD handle
-  * @retval SD card current state
-  */
-static HAL_SD_CardStateTypedef SD_GetState(SD_HandleTypeDef *hsd)
-{
-  uint32_t resp1 = 0U;
-  
-  if (SD_SendStatus(hsd, &resp1) != SD_OK)
-  {
-    return SD_CARD_ERROR;
-  }
-  else
-  {
-    return (HAL_SD_CardStateTypedef)((resp1 >> 9U) & 0x0FU);
-  }
-}
-
-/**
-  * @brief  Initializes all cards or single card as the case may be Card(s) come 
-  *         into standby state.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd)
-{
-  SDIO_CmdInitTypeDef sdio_cmdinitstructure; 
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint16_t sd_rca = 1U;
-  
-  if(SDIO_GetPowerState(hsd->Instance) == 0U) /* Power off */
-  {
-    errorstate = SD_REQUEST_NOT_APPLICABLE;
-    
-    return errorstate;
-  }
-  
-  if(hsd->CardType != SECURE_DIGITAL_IO_CARD)
-  {
-    /* Send CMD2 ALL_SEND_CID */
-    sdio_cmdinitstructure.Argument         = 0U;
-    sdio_cmdinitstructure.CmdIndex         = SD_CMD_ALL_SEND_CID;
-    sdio_cmdinitstructure.Response         = SDIO_RESPONSE_LONG;
-    sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-    sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-    SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp2Error(hsd);
-    
-    if(errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-    
-    /* Get Card identification number data */
-    hsd->CID[0U] = SDIO_GetResponse(SDIO_RESP1);
-    hsd->CID[1U] = SDIO_GetResponse(SDIO_RESP2);
-    hsd->CID[2U] = SDIO_GetResponse(SDIO_RESP3);
-    hsd->CID[3U] = SDIO_GetResponse(SDIO_RESP4);
-  }
-  
-  if((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1)    || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
-     (hsd->CardType == SECURE_DIGITAL_IO_COMBO_CARD) || (hsd->CardType == HIGH_CAPACITY_SD_CARD))
-  {
-    /* Send CMD3 SET_REL_ADDR with argument 0 */
-    /* SD Card publishes its RCA. */
-    sdio_cmdinitstructure.CmdIndex         = SD_CMD_SET_REL_ADDR;
-    sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-    SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp6Error(hsd, SD_CMD_SET_REL_ADDR, &sd_rca);
-    
-    if(errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-  }
-  
-  if (hsd->CardType != SECURE_DIGITAL_IO_CARD)
-  {
-    /* Get the SD card RCA */
-    hsd->RCA = sd_rca;
-    
-    /* Send CMD9 SEND_CSD with argument as card's RCA */
-    sdio_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16U);
-    sdio_cmdinitstructure.CmdIndex         = SD_CMD_SEND_CSD;
-    sdio_cmdinitstructure.Response         = SDIO_RESPONSE_LONG;
-    SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp2Error(hsd);
-    
-    if(errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-    
-    /* Get Card Specific Data */
-    hsd->CSD[0U] = SDIO_GetResponse(SDIO_RESP1);
-    hsd->CSD[1U] = SDIO_GetResponse(SDIO_RESP2);
-    hsd->CSD[2U] = SDIO_GetResponse(SDIO_RESP3);
-    hsd->CSD[3U] = SDIO_GetResponse(SDIO_RESP4);
-  }
-  
-  /* All cards are initialized */
-  return errorstate;
-}
-
-/**
-  * @brief  Selects of Deselects the corresponding card.
-  * @param  hsd: SD handle
-  * @param  addr: Address of the card to be selected  
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t addr)
-{
-  SDIO_CmdInitTypeDef sdio_cmdinitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  
-  /* Send CMD7 SDIO_SEL_DESEL_CARD */
-  sdio_cmdinitstructure.Argument         = (uint32_t)addr;
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_SEL_DESEL_CARD;
-  sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-  sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-  sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SEL_DESEL_CARD);
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Enquires cards about their operating voltage and configures clock
-  *         controls and stores SD information that will be needed in future
-  *         in the SD handle.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd)
-{
-  SDIO_CmdInitTypeDef sdio_cmdinitstructure; 
-  __IO HAL_SD_ErrorTypedef errorstate = SD_OK; 
-  uint32_t response = 0U, count = 0U, validvoltage = 0U;
-  uint32_t sdtype = SD_STD_CAPACITY;
-  
-  /* Power ON Sequence -------------------------------------------------------*/
-  /* Disable SDIO Clock */
-  __HAL_SD_SDIO_DISABLE(); 
-  
-  /* Set Power State to ON */
-  SDIO_PowerState_ON(hsd->Instance);
-  
-  /* 1ms: required power up waiting time before starting the SD initialization 
-     sequence */
-  HAL_Delay(1);
-  
-  /* Enable SDIO Clock */
-  __HAL_SD_SDIO_ENABLE();
-  
-  /* CMD0: GO_IDLE_STATE -----------------------------------------------------*/
-  /* No CMD response required */
-  sdio_cmdinitstructure.Argument         = 0U;
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_GO_IDLE_STATE;
-  sdio_cmdinitstructure.Response         = SDIO_RESPONSE_NO;
-  sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-  sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdError(hsd);
-  
-  if(errorstate != SD_OK)
-  {
-    /* CMD Response Timeout (wait for CMDSENT flag) */
-    return errorstate;
-  }
-  
-  /* CMD8: SEND_IF_COND ------------------------------------------------------*/
-  /* Send CMD8 to verify SD card interface operating condition */
-  /* Argument: - [31:12]: Reserved (shall be set to '0')
-  - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V)
-  - [7:0]: Check Pattern (recommended 0xAA) */
-  /* CMD Response: R7 */
-  sdio_cmdinitstructure.Argument         = SD_CHECK_PATTERN;
-  sdio_cmdinitstructure.CmdIndex         = SD_SDIO_SEND_IF_COND;
-  sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */ 
-  errorstate = SD_CmdResp7Error(hsd);
-  
-  if (errorstate == SD_OK)
-  {
-    /* SD Card 2.0 */
-    hsd->CardType = STD_CAPACITY_SD_CARD_V2_0; 
-    sdtype        = SD_HIGH_CAPACITY;
-  }
-  
-  /* Send CMD55 */
-  sdio_cmdinitstructure.Argument         = 0U;
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
-  
-  /* If errorstate is Command Timeout, it is a MMC card */
-  /* If errorstate is SD_OK it is a SD card: SD card 2.0 (voltage range mismatch)
-     or SD card 1.x */
-  if(errorstate == SD_OK)
-  {
-    /* SD CARD */
-    /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
-    while((!validvoltage) && (count < SD_MAX_VOLT_TRIAL))
-    {
-      
-      /* SEND CMD55 APP_CMD with RCA as 0 */
-      sdio_cmdinitstructure.Argument         = 0U;
-      sdio_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
-      sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-      sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-      sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-      SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-      
-      /* Check for error conditions */
-      errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
-      
-      if(errorstate != SD_OK)
-      {
-        return errorstate;
-      }
-      
-      /* Send CMD41 */
-      sdio_cmdinitstructure.Argument         = SD_VOLTAGE_WINDOW_SD | sdtype;
-      sdio_cmdinitstructure.CmdIndex         = SD_CMD_SD_APP_OP_COND;
-      sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-      sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-      sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-      SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-      
-      /* Check for error conditions */
-      errorstate = SD_CmdResp3Error(hsd);
-      
-      if(errorstate != SD_OK)
-      {
-        return errorstate;
-      }
-      
-      /* Get command response */
-      response = SDIO_GetResponse(SDIO_RESP1);
-      
-      /* Get operating voltage*/
-      validvoltage = (((response >> 31U) == 1U) ? 1U : 0U);
-      
-      count++;
-    }
-    
-    if(count >= SD_MAX_VOLT_TRIAL)
-    {
-      errorstate = SD_INVALID_VOLTRANGE;
-      
-      return errorstate;
-    }
-    
-    if((response & SD_HIGH_CAPACITY) == SD_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */
-    {
-      hsd->CardType = HIGH_CAPACITY_SD_CARD;
-    }
-    
-  } /* else MMC Card */
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Turns the SDIO output signals off.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_PowerOFF(SD_HandleTypeDef *hsd)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  
-  /* Set Power State to OFF */
-  SDIO_PowerState_OFF(hsd->Instance);
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Returns the current card's status.
-  * @param  hsd: SD handle
-  * @param  pCardStatus: pointer to the buffer that will contain the SD card 
-  *         status (Card Status register)  
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
-{
-  SDIO_CmdInitTypeDef sdio_cmdinitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  
-  if(pCardStatus == NULL)
-  {
-    errorstate = SD_INVALID_PARAMETER;
-    
-    return errorstate;
-  }
-  
-  /* Send Status command */
-  sdio_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16U);
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_SEND_STATUS;
-  sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-  sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-  sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SEND_STATUS);
-  
-  if(errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Get SD card status */
-  *pCardStatus = SDIO_GetResponse(SDIO_RESP1);
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Checks for error conditions for CMD0.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t timeout, tmp;
-  
-  timeout = SDIO_CMD0TIMEOUT;
-  
-  tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CMDSENT);
-    
-  while((timeout > 0U) && (!tmp))
-  {
-    tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CMDSENT);
-    timeout--;
-  }
-  
-  if(timeout == 0U)
-  {
-    errorstate = SD_CMD_RSP_TIMEOUT;
-    return errorstate;
-  }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Checks for error conditions for R7 response.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_ERROR;
-  uint32_t timeout = SDIO_CMD0TIMEOUT, tmp;
-  
-  tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT); 
-  
-  while((!tmp) && (timeout > 0U))
-  {
-    tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT);
-    timeout--;
-  }
-  
-  tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT); 
-  
-  if((timeout == 0U) || tmp)
-  {
-    /* Card is not V2.0 compliant or card does not support the set voltage range */
-    errorstate = SD_CMD_RSP_TIMEOUT;
-    
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
-    
-    return errorstate;
-  }
-  
-  if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CMDREND))
-  {
-    /* Card is SD V2.0 compliant */
-    errorstate = SD_OK;
-    
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CMDREND);
-    
-    return errorstate;
-  }
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Checks for error conditions for R1 response.
-  * @param  hsd: SD handle
-  * @param  SD_CMD: The sent command index  
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t response_r1;
-  
-  while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))
-  {
-  }
-  
-  if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT))
-  {
-    errorstate = SD_CMD_RSP_TIMEOUT;
-    
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
-    
-    return errorstate;
-  }
-  else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL))
-  {
-    errorstate = SD_CMD_CRC_FAIL;
-    
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL);
-    
-    return errorstate;
-  }
-  
-  /* Check response received is of desired command */
-  if(SDIO_GetCommandResponse(hsd->Instance) != SD_CMD)
-  {
-    errorstate = SD_ILLEGAL_CMD;
-    
-    return errorstate;
-  }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-  
-  /* We have received response, retrieve it for analysis  */
-  response_r1 = SDIO_GetResponse(SDIO_RESP1);
-  
-  if((response_r1 & SD_OCR_ERRORBITS) == SD_ALLZERO)
-  {
-    return errorstate;
-  }
-  
-  if((response_r1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE)
-  {
-    return(SD_ADDR_OUT_OF_RANGE);
-  }
-  
-  if((response_r1 & SD_OCR_ADDR_MISALIGNED) == SD_OCR_ADDR_MISALIGNED)
-  {
-    return(SD_ADDR_MISALIGNED);
-  }
-  
-  if((response_r1 & SD_OCR_BLOCK_LEN_ERR) == SD_OCR_BLOCK_LEN_ERR)
-  {
-    return(SD_BLOCK_LEN_ERR);
-  }
-  
-  if((response_r1 & SD_OCR_ERASE_SEQ_ERR) == SD_OCR_ERASE_SEQ_ERR)
-  {
-    return(SD_ERASE_SEQ_ERR);
-  }
-  
-  if((response_r1 & SD_OCR_BAD_ERASE_PARAM) == SD_OCR_BAD_ERASE_PARAM)
-  {
-    return(SD_BAD_ERASE_PARAM);
-  }
-  
-  if((response_r1 & SD_OCR_WRITE_PROT_VIOLATION) == SD_OCR_WRITE_PROT_VIOLATION)
-  {
-    return(SD_WRITE_PROT_VIOLATION);
-  }
-  
-  if((response_r1 & SD_OCR_LOCK_UNLOCK_FAILED) == SD_OCR_LOCK_UNLOCK_FAILED)
-  {
-    return(SD_LOCK_UNLOCK_FAILED);
-  }
-  
-  if((response_r1 & SD_OCR_COM_CRC_FAILED) == SD_OCR_COM_CRC_FAILED)
-  {
-    return(SD_COM_CRC_FAILED);
-  }
-  
-  if((response_r1 & SD_OCR_ILLEGAL_CMD) == SD_OCR_ILLEGAL_CMD)
-  {
-    return(SD_ILLEGAL_CMD);
-  }
-  
-  if((response_r1 & SD_OCR_CARD_ECC_FAILED) == SD_OCR_CARD_ECC_FAILED)
-  {
-    return(SD_CARD_ECC_FAILED);
-  }
-  
-  if((response_r1 & SD_OCR_CC_ERROR) == SD_OCR_CC_ERROR)
-  {
-    return(SD_CC_ERROR);
-  }
-  
-  if((response_r1 & SD_OCR_GENERAL_UNKNOWN_ERROR) == SD_OCR_GENERAL_UNKNOWN_ERROR)
-  {
-    return(SD_GENERAL_UNKNOWN_ERROR);
-  }
-  
-  if((response_r1 & SD_OCR_STREAM_READ_UNDERRUN) == SD_OCR_STREAM_READ_UNDERRUN)
-  {
-    return(SD_STREAM_READ_UNDERRUN);
-  }
-  
-  if((response_r1 & SD_OCR_STREAM_WRITE_OVERRUN) == SD_OCR_STREAM_WRITE_OVERRUN)
-  {
-    return(SD_STREAM_WRITE_OVERRUN);
-  }
-  
-  if((response_r1 & SD_OCR_CID_CSD_OVERWRITE) == SD_OCR_CID_CSD_OVERWRITE)
-  {
-    return(SD_CID_CSD_OVERWRITE);
-  }
-  
-  if((response_r1 & SD_OCR_WP_ERASE_SKIP) == SD_OCR_WP_ERASE_SKIP)
-  {
-    return(SD_WP_ERASE_SKIP);
-  }
-  
-  if((response_r1 & SD_OCR_CARD_ECC_DISABLED) == SD_OCR_CARD_ECC_DISABLED)
-  {
-    return(SD_CARD_ECC_DISABLED);
-  }
-  
-  if((response_r1 & SD_OCR_ERASE_RESET) == SD_OCR_ERASE_RESET)
-  {
-    return(SD_ERASE_RESET);
-  }
-  
-  if((response_r1 & SD_OCR_AKE_SEQ_ERROR) == SD_OCR_AKE_SEQ_ERROR)
-  {
-    return(SD_AKE_SEQ_ERROR);
-  }
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Checks for error conditions for R3 (OCR) response.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  
-  while (!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))
-  {
-  }
-  
-  if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT))
-  {
-    errorstate = SD_CMD_RSP_TIMEOUT;
-    
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
-    
-    return errorstate;
-  }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Checks for error conditions for R2 (CID or CSD) response.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  
-  while (!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))
-  {
-  }
-    
-  if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT))
-  {
-    errorstate = SD_CMD_RSP_TIMEOUT;
-    
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
-    
-    return errorstate;
-  }
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL))
-  {
-    errorstate = SD_CMD_CRC_FAIL;
-    
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL);
-    
-    return errorstate;
-  }
-  else
-  {
-    /* No error flag set */
-  }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Checks for error conditions for R6 (RCA) response.
-  * @param  hsd: SD handle
-  * @param  SD_CMD: The sent command index
-  * @param  pRCA: Pointer to the variable that will contain the SD card relative 
-  *         address RCA   
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t response_r1;
-  
-  while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))
-  {
-  }
-  
-  if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT))
-  {
-    errorstate = SD_CMD_RSP_TIMEOUT;
-    
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
-    
-    return errorstate;
-  }
-  else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL))
-  {
-    errorstate = SD_CMD_CRC_FAIL;
-    
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL);
-    
-    return errorstate;
-  }
-  else
-  {
-    /* No error flag set */
-  }
-  
-  /* Check response received is of desired command */
-  if(SDIO_GetCommandResponse(hsd->Instance) != SD_CMD)
-  {
-    errorstate = SD_ILLEGAL_CMD;
-    
-    return errorstate;
-  }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-  
-  /* We have received response, retrieve it.  */
-  response_r1 = SDIO_GetResponse(SDIO_RESP1);
-  
-  if((response_r1 & (SD_R6_GENERAL_UNKNOWN_ERROR | SD_R6_ILLEGAL_CMD | SD_R6_COM_CRC_FAILED)) == SD_ALLZERO)
-  {
-    *pRCA = (uint16_t) (response_r1 >> 16U);
-    
-    return errorstate;
-  }
-  
-  if((response_r1 & SD_R6_GENERAL_UNKNOWN_ERROR) == SD_R6_GENERAL_UNKNOWN_ERROR)
-  {
-    return(SD_GENERAL_UNKNOWN_ERROR);
-  }
-  
-  if((response_r1 & SD_R6_ILLEGAL_CMD) == SD_R6_ILLEGAL_CMD)
-  {
-    return(SD_ILLEGAL_CMD);
-  }
-  
-  if((response_r1 & SD_R6_COM_CRC_FAILED) == SD_R6_COM_CRC_FAILED)
-  {
-    return(SD_COM_CRC_FAILED);
-  }
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Enables the SDIO wide bus mode.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_WideBus_Enable(SD_HandleTypeDef *hsd)
-{
-  SDIO_CmdInitTypeDef sdio_cmdinitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  
-  uint32_t scr[2U] = {0U, 0U};
-  
-  if((SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
-  {
-    errorstate = SD_LOCK_UNLOCK_FAILED;
-    
-    return errorstate;
-  }
-  
-  /* Get SCR Register */
-  errorstate = SD_FindSCR(hsd, scr);
-  
-  if(errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* If requested card supports wide bus operation */
-  if((scr[1U] & SD_WIDE_BUS_SUPPORT) != SD_ALLZERO)
-  {
-    /* Send CMD55 APP_CMD with argument as card's RCA.*/
-    sdio_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16U);
-    sdio_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
-    sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-    sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-    sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-    SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
-    
-    if(errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-    
-    /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
-    sdio_cmdinitstructure.Argument         = 2U;
-    sdio_cmdinitstructure.CmdIndex         = SD_CMD_APP_SD_SET_BUSWIDTH;
-    SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH);
-    
-    if(errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-    
-    return errorstate;
-  }
-  else
-  {
-    errorstate = SD_REQUEST_NOT_APPLICABLE;
-    
-    return errorstate;
-  }
-}   
-
-/**
-  * @brief  Disables the SDIO wide bus mode.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_WideBus_Disable(SD_HandleTypeDef *hsd)
-{
-  SDIO_CmdInitTypeDef sdio_cmdinitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  
-  uint32_t scr[2U] = {0U, 0U};
-  
-  if((SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
-  {
-    errorstate = SD_LOCK_UNLOCK_FAILED;
-    
-    return errorstate;
-  }
-  
-  /* Get SCR Register */
-  errorstate = SD_FindSCR(hsd, scr);
-  
-  if(errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* If requested card supports 1 bit mode operation */
-  if((scr[1U] & SD_SINGLE_BUS_SUPPORT) != SD_ALLZERO)
-  {
-    /* Send CMD55 APP_CMD with argument as card's RCA */
-    sdio_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16U);
-    sdio_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
-    sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-    sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-    sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-    SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
-    
-    if(errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-    
-    /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */
-    sdio_cmdinitstructure.Argument         = 0U;
-    sdio_cmdinitstructure.CmdIndex         = SD_CMD_APP_SD_SET_BUSWIDTH;
-    SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH);
-    
-    if(errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-    
-    return errorstate;
-  }
-  else
-  {
-    errorstate = SD_REQUEST_NOT_APPLICABLE;
-    
-    return errorstate;
-  }
-}
-  
-  
-/**
-  * @brief  Finds the SD card SCR register value.
-  * @param  hsd: SD handle
-  * @param  pSCR: pointer to the buffer that will contain the SCR value  
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
-{
-  SDIO_CmdInitTypeDef  sdio_cmdinitstructure;
-  SDIO_DataInitTypeDef sdio_datainitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t index = 0U;
-  uint32_t tempscr[2U] = {0U, 0U};
-  
-  /* Set Block Size To 8 Bytes */
-  /* Send CMD55 APP_CMD with argument as card's RCA */
-  sdio_cmdinitstructure.Argument         = (uint32_t)8U;
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
-  sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-  sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-  sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
-  
-  if(errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Send CMD55 APP_CMD with argument as card's RCA */
-  sdio_cmdinitstructure.Argument         = (uint32_t)((hsd->RCA) << 16U);
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
-  
-  if(errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  sdio_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
-  sdio_datainitstructure.DataLength    = 8U;
-  sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_8B;
-  sdio_datainitstructure.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
-  sdio_datainitstructure.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
-  sdio_datainitstructure.DPSM          = SDIO_DPSM_ENABLE;
-  SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
-  
-  /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */
-  sdio_cmdinitstructure.Argument         = 0U;
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_SD_APP_SEND_SCR;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_SEND_SCR);
-  
-  if(errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-#ifdef SDIO_STA_STBITERR  
-  while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
-#else /* SDIO_STA_STBITERR not defined */
-  while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))
-#endif /* SDIO_STA_STBITERR */
-  {
-    if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL))
-    {
-      *(tempscr + index) = SDIO_ReadFIFO(hsd->Instance);
-      index++;
-    }
-  }
-  
-  if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
-    
-    errorstate = SD_DATA_TIMEOUT;
-    
-    return errorstate;
-  }
-  else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
-    
-    errorstate = SD_DATA_CRC_FAIL;
-    
-    return errorstate;
-  }
-  else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
-    
-    errorstate = SD_RX_OVERRUN;
-    
-    return errorstate;
-  }
-#ifdef SDIO_STA_STBITERR
-  else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
-    
-    errorstate = SD_START_BIT_ERR;
-    
-    return errorstate;
-  }
-#endif /* SDIO_STA_STBITERR */
-  else
-  {
-    /* No error flag set */
-  }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-  
-  *(pSCR + 1U) = ((tempscr[0U] & SD_0TO7BITS) << 24U)  | ((tempscr[0U] & SD_8TO15BITS) << 8U) |\
-    ((tempscr[0U] & SD_16TO23BITS) >> 8U) | ((tempscr[0U] & SD_24TO31BITS) >> 24U);
-  
-  *(pSCR) = ((tempscr[1U] & SD_0TO7BITS) << 24U)  | ((tempscr[1U] & SD_8TO15BITS) << 8U) |\
-    ((tempscr[1U] & SD_16TO23BITS) >> 8U) | ((tempscr[1U] & SD_24TO31BITS) >> 24U);
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Checks if the SD card is in programming state.
-  * @param  hsd: SD handle
-  * @param  pStatus: pointer to the variable that will contain the SD card state  
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *pStatus)
-{
-  SDIO_CmdInitTypeDef sdio_cmdinitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  __IO uint32_t responseR1 = 0U;
-  
-  sdio_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16U);
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_SEND_STATUS;
-  sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-  sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-  sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))
-  {
-  }
-  
-  if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT))
-  {
-    errorstate = SD_CMD_RSP_TIMEOUT;
-    
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
-    
-    return errorstate;
-  }
-  else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL))
-  {
-    errorstate = SD_CMD_CRC_FAIL;
-    
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL);
-    
-    return errorstate;
-  }
-  else
-  {
-    /* No error flag set */
-  }
-  
-  /* Check response received is of desired command */
-  if((uint32_t)SDIO_GetCommandResponse(hsd->Instance) != SD_CMD_SEND_STATUS)
-  {
-    errorstate = SD_ILLEGAL_CMD;
-    
-    return errorstate;
-  }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-  
-  
-  /* We have received response, retrieve it for analysis */
-  responseR1 = SDIO_GetResponse(SDIO_RESP1);
-  
-  /* Find out card status */
-  *pStatus = (uint8_t)((responseR1 >> 9U) & 0x0000000FU);
-  
-  if((responseR1 & SD_OCR_ERRORBITS) == SD_ALLZERO)
-  {
-    return errorstate;
-  }
-  
-  if((responseR1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE)
-  {
-    return(SD_ADDR_OUT_OF_RANGE);
-  }
-  
-  if((responseR1 & SD_OCR_ADDR_MISALIGNED) == SD_OCR_ADDR_MISALIGNED)
-  {
-    return(SD_ADDR_MISALIGNED);
-  }
-  
-  if((responseR1 & SD_OCR_BLOCK_LEN_ERR) == SD_OCR_BLOCK_LEN_ERR)
-  {
-    return(SD_BLOCK_LEN_ERR);
-  }
-  
-  if((responseR1 & SD_OCR_ERASE_SEQ_ERR) == SD_OCR_ERASE_SEQ_ERR)
-  {
-    return(SD_ERASE_SEQ_ERR);
-  }
-  
-  if((responseR1 & SD_OCR_BAD_ERASE_PARAM) == SD_OCR_BAD_ERASE_PARAM)
-  {
-    return(SD_BAD_ERASE_PARAM);
-  }
-  
-  if((responseR1 & SD_OCR_WRITE_PROT_VIOLATION) == SD_OCR_WRITE_PROT_VIOLATION)
-  {
-    return(SD_WRITE_PROT_VIOLATION);
-  }
-  
-  if((responseR1 & SD_OCR_LOCK_UNLOCK_FAILED) == SD_OCR_LOCK_UNLOCK_FAILED)
-  {
-    return(SD_LOCK_UNLOCK_FAILED);
-  }
-  
-  if((responseR1 & SD_OCR_COM_CRC_FAILED) == SD_OCR_COM_CRC_FAILED)
-  {
-    return(SD_COM_CRC_FAILED);
-  }
-  
-  if((responseR1 & SD_OCR_ILLEGAL_CMD) == SD_OCR_ILLEGAL_CMD)
-  {
-    return(SD_ILLEGAL_CMD);
-  }
-  
-  if((responseR1 & SD_OCR_CARD_ECC_FAILED) == SD_OCR_CARD_ECC_FAILED)
-  {
-    return(SD_CARD_ECC_FAILED);
-  }
-  
-  if((responseR1 & SD_OCR_CC_ERROR) == SD_OCR_CC_ERROR)
-  {
-    return(SD_CC_ERROR);
-  }
-  
-  if((responseR1 & SD_OCR_GENERAL_UNKNOWN_ERROR) == SD_OCR_GENERAL_UNKNOWN_ERROR)
-  {
-    return(SD_GENERAL_UNKNOWN_ERROR);
-  }
-  
-  if((responseR1 & SD_OCR_STREAM_READ_UNDERRUN) == SD_OCR_STREAM_READ_UNDERRUN)
-  {
-    return(SD_STREAM_READ_UNDERRUN);
-  }
-  
-  if((responseR1 & SD_OCR_STREAM_WRITE_OVERRUN) == SD_OCR_STREAM_WRITE_OVERRUN)
-  {
-    return(SD_STREAM_WRITE_OVERRUN);
-  }
-  
-  if((responseR1 & SD_OCR_CID_CSD_OVERWRITE) == SD_OCR_CID_CSD_OVERWRITE)
-  {
-    return(SD_CID_CSD_OVERWRITE);
-  }
-  
-  if((responseR1 & SD_OCR_WP_ERASE_SKIP) == SD_OCR_WP_ERASE_SKIP)
-  {
-    return(SD_WP_ERASE_SKIP);
-  }
-  
-  if((responseR1 & SD_OCR_CARD_ECC_DISABLED) == SD_OCR_CARD_ECC_DISABLED)
-  {
-    return(SD_CARD_ECC_DISABLED);
-  }
-  
-  if((responseR1 & SD_OCR_ERASE_RESET) == SD_OCR_ERASE_RESET)
-  {
-    return(SD_ERASE_RESET);
-  }
-  
-  if((responseR1 & SD_OCR_AKE_SEQ_ERROR) == SD_OCR_AKE_SEQ_ERROR)
-  {
-    return(SD_AKE_SEQ_ERROR);
-  }
-  
-  return errorstate;
-}   
-
-/**
-  * @}
-  */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || 
-          STM32F412Rx || STM32F412Cx */
-#endif /* HAL_SD_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_spi.c b/stmhal/hal/f4/src/stm32f4xx_hal_spi.c
deleted file mode 100644
index 93387d13aa..0000000000
--- a/stmhal/hal/f4/src/stm32f4xx_hal_spi.c
+++ /dev/null
@@ -1,2778 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_spi.c
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   SPI HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Serial Peripheral Interface (SPI) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions
-  *           + Peripheral State functions
-  *
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-    [..]
-      The SPI HAL driver can be used as follows:
-
-      (#) Declare a SPI_HandleTypeDef handle structure, for example:
-          SPI_HandleTypeDef  hspi;
-
-      (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
-          (##) Enable the SPIx interface clock
-          (##) SPI pins configuration
-              (+++) Enable the clock for the SPI GPIOs
-              (+++) Configure these SPI pins as alternate function push-pull
-          (##) NVIC configuration if you need to use interrupt process
-              (+++) Configure the SPIx interrupt priority
-              (+++) Enable the NVIC SPI IRQ handle
-          (##) DMA Configuration if you need to use DMA process
-              (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
-              (+++) Enable the DMAx clock
-              (+++) Configure the DMA handle parameters
-              (+++) Configure the DMA Tx or Rx stream
-              (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
-              (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx stream
-
-      (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
-          management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
-
-      (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
-          (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
-              by calling the customized HAL_SPI_MspInit() API.
-     [..]
-       Circular mode restriction:
-      (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
-          (##) Master 2Lines RxOnly
-          (##) Master 1Line Rx
-      (#) The CRC feature is not managed when the DMA circular mode is enabled
-      (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
-          the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
-     [..]
-       Master Receive mode restriction:
-      (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=0) or
-          bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
-          does not initiate a new transfer the following procedure has to be respected:
-          (##) HAL_SPI_DeInit()
-          (##) HAL_SPI_Init()
-     [..]
-       Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,
-       the following table resume the max SPI frequency reached with data size 8bits/16bits,
-       according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance :
-
-       DataSize = SPI_DATASIZE_8BIT:
-       +----------------------------------------------------------------------------------------------+
-       |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |
-       | Process | Tranfert mode  |---------------------|----------------------|----------------------|
-       |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |
-       |==============================================================================================|
-       |    T    |     Polling    | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
-       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
-       |    /    |     Interrupt  | Fpclk/4  | Fpclk/8  |    NA     |    NA    |    NA     |   NA     |
-       |    R    |----------------|----------|----------|-----------|----------|-----------|----------|
-       |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
-       |=========|================|==========|==========|===========|==========|===========|==========|
-       |         |     Polling    | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/64  | Fpclk/2  |
-       |         |----------------|----------|----------|-----------|----------|-----------|----------|
-       |    R    |     Interrupt  | Fpclk/8  | Fpclk/8  | Fpclk/64  | Fpclk/2  | Fpclk/64  | Fpclk/2  |
-       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
-       |         |       DMA      | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/128 | Fpclk/2  |
-       |=========|================|==========|==========|===========|==========|===========|==========|
-       |         |     Polling    | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/2   | Fpclk/64 |
-       |         |----------------|----------|----------|-----------|----------|-----------|----------|
-       |    T    |     Interrupt  | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/2   | Fpclk/64 |
-       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
-       |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/128|
-       +----------------------------------------------------------------------------------------------+
-
-       DataSize = SPI_DATASIZE_16BIT:
-       +----------------------------------------------------------------------------------------------+
-       |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |
-       | Process | Tranfert mode  |---------------------|----------------------|----------------------|
-       |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |
-       |==============================================================================================|
-       |    T    |     Polling    | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
-       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
-       |    /    |     Interrupt  | Fpclk/4  | Fpclk/4  |    NA     |    NA    |    NA     |   NA     |
-       |    R    |----------------|----------|----------|-----------|----------|-----------|----------|
-       |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
-       |=========|================|==========|==========|===========|==========|===========|==========|
-       |         |     Polling    | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/32  | Fpclk/2  |
-       |         |----------------|----------|----------|-----------|----------|-----------|----------|
-       |    R    |     Interrupt  | Fpclk/4  | Fpclk/4  | Fpclk/64  | Fpclk/2  | Fpclk/64  | Fpclk/2  |
-       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
-       |         |       DMA      | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/128 | Fpclk/2  |
-       |=========|================|==========|==========|===========|==========|===========|==========|
-       |         |     Polling    | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/32 |
-       |         |----------------|----------|----------|-----------|----------|-----------|----------|
-       |    T    |     Interrupt  | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/64 |
-       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
-       |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/128|
-       +----------------------------------------------------------------------------------------------+
-       @note The max SPI frequency depend on SPI data size (8bits, 16bits),
-             SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
-       @note
-            (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
-            (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
-            (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-/** @defgroup SPI SPI
-  * @brief SPI HAL module driver
-  * @{
-  */
-#ifdef HAL_SPI_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup SPI_Private_Constants SPI Private Constants
-  * @{
-  */
-#define SPI_DEFAULT_TIMEOUT 100U
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup SPI_Private_Functions
-  * @{
-  */
-static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAError(DMA_HandleTypeDef *hdma);
-static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart);
-static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
-#if (USE_SPI_CRC != 0U)
-static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
-static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
-#endif /* USE_SPI_CRC */
-static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
-static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
-static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
-static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup SPI_Exported_Functions SPI Exported Functions
-  * @{
-  */
-
-/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @brief    Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This subsection provides a set of functions allowing to initialize and
-          de-initialize the SPIx peripheral:
-
-      (+) User must implement HAL_SPI_MspInit() function in which he configures
-          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
-
-      (+) Call the function HAL_SPI_Init() to configure the selected device with
-          the selected configuration:
-        (++) Mode
-        (++) Direction
-        (++) Data Size
-        (++) Clock Polarity and Phase
-        (++) NSS Management
-        (++) BaudRate Prescaler
-        (++) FirstBit
-        (++) TIMode
-        (++) CRC Calculation
-        (++) CRC Polynomial if CRC enabled
-
-      (+) Call the function HAL_SPI_DeInit() to restore the default configuration
-          of the selected SPIx peripheral.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initialize the SPI according to the specified parameters
-  *         in the SPI_InitTypeDef and initialize the associated handle.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
-{
-  /* Check the SPI handle allocation */
-  if(hspi == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
-  assert_param(IS_SPI_MODE(hspi->Init.Mode));
-  assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
-  assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
-  assert_param(IS_SPI_NSS(hspi->Init.NSS));
-  assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
-  assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
-  assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
-  if(hspi->Init.TIMode == SPI_TIMODE_DISABLE)
-  {
-    assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
-    assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
-  }
-#if (USE_SPI_CRC != 0U)
-  assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
-  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
-  }
-#else
-  hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
-#endif /* USE_SPI_CRC */
-
-  if(hspi->State == HAL_SPI_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hspi->Lock = HAL_UNLOCKED;
-
-    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
-    HAL_SPI_MspInit(hspi);
-  }
-
-  hspi->State = HAL_SPI_STATE_BUSY;
-
-  /* Disable the selected SPI peripheral */
-  __HAL_SPI_DISABLE(hspi);
-
-  /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
-  /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
-  Communication speed, First bit and CRC calculation state */
-  WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize |
-                                  hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
-                                  hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit  | hspi->Init.CRCCalculation) );
-
-  /* Configure : NSS management */
-  WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode));
-
-#if (USE_SPI_CRC != 0U)
-  /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
-  /* Configure : CRC Polynomial */
-  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
-  }
-#endif /* USE_SPI_CRC */
-
-#if defined(SPI_I2SCFGR_I2SMOD)
-  /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
-  CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
-#endif /* USE_SPI_CRC */
-
-  hspi->ErrorCode = HAL_SPI_ERROR_NONE;
-  hspi->State     = HAL_SPI_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  De Initialize the SPI peripheral.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
-{
-  /* Check the SPI handle allocation */
-  if(hspi == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check SPI Instance parameter */
-  assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
-
-  hspi->State = HAL_SPI_STATE_BUSY;
-
-  /* Disable the SPI Peripheral Clock */
-  __HAL_SPI_DISABLE(hspi);
-
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
-  HAL_SPI_MspDeInit(hspi);
-
-  hspi->ErrorCode = HAL_SPI_ERROR_NONE;
-  hspi->State = HAL_SPI_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hspi);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initialize the SPI MSP.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_MspInit should be implemented in the user file
-  */
-}
-
-/**
-  * @brief  De-Initialize the SPI MSP.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_MspDeInit should be implemented in the user file
-  */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
- *  @brief   Data transfers functions
- *
-@verbatim
-  ==============================================================================
-                      ##### IO operation functions #####
- ===============================================================================
- [..]
-    This subsection provides a set of functions allowing to manage the SPI
-    data transfers.
-
-    [..] The SPI supports master and slave mode :
-
-    (#) There are two modes of transfer:
-       (++) Blocking mode: The communication is performed in polling mode.
-            The HAL status of all data processing is returned by the same function
-            after finishing transfer.
-       (++) No-Blocking mode: The communication is performed using Interrupts
-            or DMA, These APIs return the HAL status.
-            The end of the data processing will be indicated through the
-            dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
-            using DMA mode.
-            The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
-            will be executed respectively at the end of the transmit or Receive process
-            The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
-
-    (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
-        exist for 1Line (simplex) and 2Lines (full duplex) modes.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Transmit an amount of data in blocking mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pData: pointer to data buffer
-  * @param  Size: amount of data to be sent
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint32_t tickstart = 0U;
-  HAL_StatusTypeDef errorcode = HAL_OK;
-
-  /* Check Direction parameter */
-  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
-
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  /* Init tickstart for timeout management*/
-  tickstart = HAL_GetTick();
-
-  if(hspi->State != HAL_SPI_STATE_READY)
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  if((pData == NULL ) || (Size == 0U))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  /* Set the transaction information */
-  hspi->State       = HAL_SPI_STATE_BUSY_TX;
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pTxBuffPtr  = (uint8_t *)pData;
-  hspi->TxXferSize  = Size;
-  hspi->TxXferCount = Size;
-
-  /*Init field not used in handle to zero */
-  hspi->pRxBuffPtr  = (uint8_t *)NULL;
-  hspi->RxXferSize  = 0U;
-  hspi->RxXferCount = 0U;
-  hspi->TxISR       = NULL;
-  hspi->RxISR       = NULL;
-
-  /* Configure communication direction : 1Line */
-  if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
-  {
-    SPI_1LINE_TX(hspi);
-  }
-
-#if (USE_SPI_CRC != 0U)
-  /* Reset CRC Calculation */
-  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Check if the SPI is already enabled */
-  if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-
-  /* Transmit data in 16 Bit mode */
-  if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
-  {
-    if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01))
-    {
-      hspi->Instance->DR = *((uint16_t *)pData);
-      pData += sizeof(uint16_t);
-      hspi->TxXferCount--;
-    }
-    /* Transmit data in 16 Bit mode */
-    while (hspi->TxXferCount > 0U)
-    {
-      /* Wait until TXE flag is set to send data */
-      if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
-      {
-          hspi->Instance->DR = *((uint16_t *)pData);
-          pData += sizeof(uint16_t);
-          hspi->TxXferCount--;
-      }
-      else
-      {
-        /* Timeout management */
-        if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout)))
-        {
-          errorcode = HAL_TIMEOUT;
-          goto error;
-        }
-      }
-    }
-  }
-  /* Transmit data in 8 Bit mode */
-  else
-  {
-    if((hspi->Init.Mode == SPI_MODE_SLAVE)|| (hspi->TxXferCount == 0x01))
-    {
-      *((__IO uint8_t*)&hspi->Instance->DR) = (*pData);
-      pData += sizeof(uint8_t);
-      hspi->TxXferCount--;
-    }
-    while (hspi->TxXferCount > 0U)
-    {
-      /* Wait until TXE flag is set to send data */
-      if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
-      {
-        *((__IO uint8_t*)&hspi->Instance->DR) = (*pData);
-        pData += sizeof(uint8_t);
-        hspi->TxXferCount--;
-      }
-      else
-      {
-        /* Timeout management */
-        if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout)))
-        {
-          errorcode = HAL_TIMEOUT;
-          goto error;
-        }
-      }
-    }
-  }
-
-  /* Wait until TXE flag */
-  if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, tickstart) != HAL_OK)
-  {
-    errorcode = HAL_TIMEOUT;
-    goto error;
-  }
-  
-  /* Check Busy flag */
-  if(SPI_CheckFlag_BSY(hspi, Timeout, tickstart) != HAL_OK)
-  {
-    errorcode = HAL_ERROR;
-    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
-    goto error;
-  }
-
-  /* Clear overrun flag in 2 Lines communication mode because received is not read */
-  if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
-  {
-    __HAL_SPI_CLEAR_OVRFLAG(hspi);
-  }
-#if (USE_SPI_CRC != 0U)
-  /* Enable CRC Transmission */
-  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-     SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-  }
-#endif /* USE_SPI_CRC */
-
-  if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
-  {
-    errorcode = HAL_ERROR;
-  }
-
-error:
-  hspi->State = HAL_SPI_STATE_READY;
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Receive an amount of data in blocking mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pData: pointer to data buffer
-  * @param  Size: amount of data to be received
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-#if (USE_SPI_CRC != 0U)
-  __IO uint16_t tmpreg = 0U;
-#endif /* USE_SPI_CRC */
-  uint32_t tickstart = 0U;
-  HAL_StatusTypeDef errorcode = HAL_OK;
-
-  if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
-  {
-     hspi->State = HAL_SPI_STATE_BUSY_RX;
-     /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
-    return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout);
-  }
-
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  /* Init tickstart for timeout management*/
-  tickstart = HAL_GetTick();
-
-  if(hspi->State != HAL_SPI_STATE_READY)
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  if((pData == NULL ) || (Size == 0U))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  /* Set the transaction information */
-  hspi->State       = HAL_SPI_STATE_BUSY_RX;
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pRxBuffPtr  = (uint8_t *)pData;
-  hspi->RxXferSize  = Size;
-  hspi->RxXferCount = Size;
-
-  /*Init field not used in handle to zero */
-  hspi->pTxBuffPtr  = (uint8_t *)NULL;
-  hspi->TxXferSize  = 0U;
-  hspi->TxXferCount = 0U;
-  hspi->RxISR       = NULL;
-  hspi->TxISR       = NULL;
-
-#if (USE_SPI_CRC != 0U)
-  /* Reset CRC Calculation */
-  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-    /* this is done to handle the CRCNEXT before the latest data */
-    hspi->RxXferCount--;
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Configure communication direction: 1Line */
-  if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
-  {
-    SPI_1LINE_RX(hspi);
-  }
-
-  /* Check if the SPI is already enabled */
-  if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-
-    /* Receive data in 8 Bit mode */
-  if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
-  {
-    /* Transfer loop */
-    while(hspi->RxXferCount > 0U)
-    {
-      /* Check the RXNE flag */
-      if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
-      {
-        /* read the received data */
-        (* (uint8_t *)pData)= *(__IO uint8_t *)&hspi->Instance->DR;
-        pData += sizeof(uint8_t);
-        hspi->RxXferCount--;
-      }
-      else
-      {
-        /* Timeout management */
-        if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout)))
-        {
-          errorcode = HAL_TIMEOUT;
-          goto error;
-        }
-      }
-    }
-  }
-  else
-  {
-    /* Transfer loop */
-    while(hspi->RxXferCount > 0U)
-    {
-      /* Check the RXNE flag */
-      if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
-      {
-        *((uint16_t*)pData) = hspi->Instance->DR;
-        pData += sizeof(uint16_t);
-        hspi->RxXferCount--;
-      }
-      else
-      {
-        /* Timeout management */
-        if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout)))
-        {
-          errorcode = HAL_TIMEOUT;
-          goto error;
-        }
-      }
-    }
-  }
-
-#if (USE_SPI_CRC != 0U)
-  /* Handle the CRC Transmission */
-  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    /* freeze the CRC before the latest data */
-    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-
-    /* Read the latest data */
-    if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
-    {
-      /* the latest data has not been received */
-      errorcode = HAL_TIMEOUT;
-      goto error;
-    }
-
-    /* Receive last data in 16 Bit mode */
-    if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
-    {
-      *((uint16_t*)pData) = hspi->Instance->DR;
-    }
-    /* Receive last data in 8 Bit mode */
-    else
-    {
-      (*(uint8_t *)pData) = *(__IO uint8_t *)&hspi->Instance->DR;
-    }
-
-    /* Wait the CRC data */
-    if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-      errorcode = HAL_TIMEOUT;
-      goto error;
-    }
-
-    /* Read CRC to Flush DR and RXNE flag */
-    tmpreg = hspi->Instance->DR;
-    /* To avoid GCC warning */
-    UNUSED(tmpreg);
-  }
-#endif /* USE_SPI_CRC */
-
-  if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
-  {
-    /* Disable SPI peripheral */
-    __HAL_SPI_DISABLE(hspi);
-  }
-
-#if (USE_SPI_CRC != 0U)
-  /* Check if CRC error occurred */
-  if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
-  {
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-  }
-#endif /* USE_SPI_CRC */
-
-  if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
-  {
-    errorcode = HAL_ERROR;
-  }
-
-error :
-  hspi->State = HAL_SPI_STATE_READY;
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Transmit and Receive an amount of data in blocking mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pTxData: pointer to transmission data buffer
-  * @param  pRxData: pointer to reception data buffer
-  * @param  Size: amount of data to be sent and received
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
-{
-  uint32_t tmp = 0U, tmp1 = 0U;
-#if (USE_SPI_CRC != 0U)
-  __IO uint16_t tmpreg1 = 0U;
-#endif /* USE_SPI_CRC */
-  uint32_t tickstart = 0U;
-  /* Variable used to alternate Rx and Tx during transfer */
-  uint32_t txallowed = 1U;
-  HAL_StatusTypeDef errorcode = HAL_OK;
-
-  /* Check Direction parameter */
-  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
-
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  /* Init tickstart for timeout management*/
-  tickstart = HAL_GetTick();
-  
-  tmp  = hspi->State;
-  tmp1 = hspi->Init.Mode;
-  
-  if(!((tmp == HAL_SPI_STATE_READY) || \
-    ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
-  if(hspi->State == HAL_SPI_STATE_READY)
-  {
-    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
-  }
-
-  /* Set the transaction information */
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pRxBuffPtr  = (uint8_t *)pRxData;
-  hspi->RxXferCount = Size;
-  hspi->RxXferSize  = Size;
-  hspi->pTxBuffPtr  = (uint8_t *)pTxData;
-  hspi->TxXferCount = Size;
-  hspi->TxXferSize  = Size;
-
-  /*Init field not used in handle to zero */
-  hspi->RxISR       = NULL;
-  hspi->TxISR       = NULL;
-
-#if (USE_SPI_CRC != 0U)
-  /* Reset CRC Calculation */
-  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Check if the SPI is already enabled */
-  if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-
-  /* Transmit and Receive data in 16 Bit mode */
-  if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
-  {
-    if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01))
-    {
-      hspi->Instance->DR = *((uint16_t *)pTxData);
-      pTxData += sizeof(uint16_t);
-      hspi->TxXferCount--;
-    }
-    while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
-    {
-      /* Check TXE flag */
-      if(txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
-      {
-        hspi->Instance->DR = *((uint16_t *)pTxData);
-        pTxData += sizeof(uint16_t);
-        hspi->TxXferCount--;
-        /* Next Data is a reception (Rx). Tx not allowed */ 
-        txallowed = 0U;
-
-#if (USE_SPI_CRC != 0U)
-        /* Enable CRC Transmission */
-        if((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
-        {
-          SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-        }
-#endif /* USE_SPI_CRC */
-      }
-
-      /* Check RXNE flag */
-      if((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
-      {
-        *((uint16_t *)pRxData) = hspi->Instance->DR;
-        pRxData += sizeof(uint16_t);
-        hspi->RxXferCount--;
-        /* Next Data is a Transmission (Tx). Tx is allowed */ 
-        txallowed = 1U;
-      }
-      if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout))
-      {
-        errorcode = HAL_TIMEOUT;
-        goto error;
-      }
-    }
-  }
-  /* Transmit and Receive data in 8 Bit mode */
-  else
-  {
-    if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01))
-    {
-      *((__IO uint8_t*)&hspi->Instance->DR) = (*pTxData);
-      pTxData += sizeof(uint8_t);
-      hspi->TxXferCount--;
-    }
-    while((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
-    {
-      /* check TXE flag */
-      if(txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
-      {
-        *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++);
-        hspi->TxXferCount--;
-        /* Next Data is a reception (Rx). Tx not allowed */ 
-        txallowed = 0U;
-
-#if (USE_SPI_CRC != 0U)
-        /* Enable CRC Transmission */
-        if((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
-        {
-          SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-        }
-#endif /* USE_SPI_CRC */
-      }
-
-      /* Wait until RXNE flag is reset */
-      if((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
-      {
-        (*(uint8_t *)pRxData++) = hspi->Instance->DR;
-        hspi->RxXferCount--;
-        /* Next Data is a Transmission (Tx). Tx is allowed */ 
-        txallowed = 1U;
-      }
-      if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout))
-      {
-        errorcode = HAL_TIMEOUT;
-        goto error;
-      }
-    }
-  }
-
-#if (USE_SPI_CRC != 0U)
-  /* Read CRC from DR to close CRC calculation process */
-  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    /* Wait until TXE flag */
-    if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
-    {
-      /* Error on the CRC reception */
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-      errorcode = HAL_TIMEOUT;
-      goto error;
-    }
-    /* Read CRC */
-    tmpreg1 = hspi->Instance->DR;
-    /* To avoid GCC warning */
-    UNUSED(tmpreg1);
-  }
-
-  /* Check if CRC error occurred */
-  if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
-  {
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-    /* Clear CRC Flag */
-    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-
-    errorcode = HAL_ERROR;
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Wait until TXE flag */
-  if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, tickstart) != HAL_OK)
-  {
-    errorcode = HAL_TIMEOUT;
-    goto error;
-  }
-  
-  /* Check Busy flag */
-  if(SPI_CheckFlag_BSY(hspi, Timeout, tickstart) != HAL_OK)
-  {
-    errorcode = HAL_ERROR;
-    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
-    goto error;
-  }
-
-  /* Clear overrun flag in 2 Lines communication mode because received is not read */
-  if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
-  {
-    __HAL_SPI_CLEAR_OVRFLAG(hspi);
-  }
-  
-error :
-  hspi->State = HAL_SPI_STATE_READY;
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Transmit an amount of data in non-blocking mode with Interrupt.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pData: pointer to data buffer
-  * @param  Size: amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
-{
-  HAL_StatusTypeDef errorcode = HAL_OK;
-
-  /* Check Direction parameter */
-  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
-
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  if((pData == NULL) || (Size == 0U))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  if(hspi->State != HAL_SPI_STATE_READY)
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  /* Set the transaction information */
-  hspi->State       = HAL_SPI_STATE_BUSY_TX;
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pTxBuffPtr  = (uint8_t *)pData;
-  hspi->TxXferSize  = Size;
-  hspi->TxXferCount = Size;
-
-  /* Init field not used in handle to zero */
-  hspi->pRxBuffPtr  = (uint8_t *)NULL;
-  hspi->RxXferSize  = 0U;
-  hspi->RxXferCount = 0U;
-  hspi->RxISR       = NULL;
-
-  /* Set the function for IT treatment */
-  if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
-  {
-    hspi->TxISR = SPI_TxISR_16BIT;
-  }
-  else
-  {
-    hspi->TxISR = SPI_TxISR_8BIT;
-  }
-
-  /* Configure communication direction : 1Line */
-  if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
-  {
-    SPI_1LINE_TX(hspi);
-  }
-
-#if (USE_SPI_CRC != 0U)
-  /* Reset CRC Calculation */
-  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-  }
-#endif /* USE_SPI_CRC */
-
-  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
-  {
-    /* Enable TXE interrupt */
-    __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE));
-  }
-  else
-  {
-    /* Enable TXE and ERR interrupt */
-    __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
-  }
-
-  /* Check if the SPI is already enabled */
-  if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-
-error :
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Receive an amount of data in non-blocking mode with Interrupt.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pData: pointer to data buffer
-  * @param  Size: amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
-{
-  HAL_StatusTypeDef errorcode = HAL_OK;
-
-  if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
-  {
-     hspi->State = HAL_SPI_STATE_BUSY_RX;
-     /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
-     return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
-  }
-
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  if(hspi->State != HAL_SPI_STATE_READY)
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  if((pData == NULL) || (Size == 0U))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  /* Set the transaction information */
-  hspi->State       = HAL_SPI_STATE_BUSY_RX;
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pRxBuffPtr  = (uint8_t *)pData;
-  hspi->RxXferSize  = Size;
-  hspi->RxXferCount = Size;
-
-  /* Init field not used in handle to zero */
-  hspi->pTxBuffPtr  = (uint8_t *)NULL;
-  hspi->TxXferSize  = 0U;
-  hspi->TxXferCount = 0U;
-  hspi->TxISR       = NULL;
-
-  /* Set the function for IT treatment */
-  if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
-  {
-    hspi->RxISR = SPI_RxISR_16BIT;
-  }
-  else
-  {
-    hspi->RxISR = SPI_RxISR_8BIT;
-  }
-
-  /* Configure communication direction : 1Line */
-  if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
-  {
-    SPI_1LINE_RX(hspi);
-  }
-
-#if (USE_SPI_CRC != 0U)
-  /* Reset CRC Calculation */
-  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Enable TXE and ERR interrupt */
-  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
-  /* Note : The SPI must be enabled after unlocking current process
-            to avoid the risk of SPI interrupt handle execution before current
-            process unlock */
-
-  /* Check if the SPI is already enabled */
-  if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-
-error :
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Transmit and Receive an amount of data in non-blocking mode with Interrupt.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pTxData: pointer to transmission data buffer
-  * @param  pRxData: pointer to reception data buffer
-  * @param  Size: amount of data to be sent and received
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
-{
-  uint32_t tmp = 0U, tmp1 = 0U;
-  HAL_StatusTypeDef errorcode = HAL_OK;
-
-  /* Check Direction parameter */
-  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
-
-  /* Process locked */
-  __HAL_LOCK(hspi);
-
-  tmp  = hspi->State;
-  tmp1 = hspi->Init.Mode;
-  
-  if(!((tmp == HAL_SPI_STATE_READY) || \
-    ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
-  if(hspi->State == HAL_SPI_STATE_READY)
-  {
-    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
-  }
-
-  /* Set the transaction information */
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pTxBuffPtr  = (uint8_t *)pTxData;
-  hspi->TxXferSize  = Size;
-  hspi->TxXferCount = Size;
-  hspi->pRxBuffPtr  = (uint8_t *)pRxData;
-  hspi->RxXferSize  = Size;
-  hspi->RxXferCount = Size;
-
-  /* Set the function for IT treatment */
-  if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
-  {
-    hspi->RxISR     = SPI_2linesRxISR_16BIT;
-    hspi->TxISR     = SPI_2linesTxISR_16BIT;
-  }
-  else
-  {
-    hspi->RxISR     = SPI_2linesRxISR_8BIT;
-    hspi->TxISR     = SPI_2linesTxISR_8BIT;
-  }
-
-#if (USE_SPI_CRC != 0U)
-  /* Reset CRC Calculation */
-  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Enable TXE, RXNE and ERR interrupt */
-  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
-
-  /* Check if the SPI is already enabled */
-  if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-
-error :
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Transmit an amount of data in non-blocking mode with DMA.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pData: pointer to data buffer
-  * @param  Size: amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
-{
-  HAL_StatusTypeDef errorcode = HAL_OK;
-
-  /* Check Direction parameter */
-  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
-
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  if(hspi->State != HAL_SPI_STATE_READY)
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  if((pData == NULL) || (Size == 0U))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  /* Set the transaction information */
-  hspi->State       = HAL_SPI_STATE_BUSY_TX;
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pTxBuffPtr  = (uint8_t *)pData;
-  hspi->TxXferSize  = Size;
-  hspi->TxXferCount = Size;
-
-  /* Init field not used in handle to zero */
-  hspi->pRxBuffPtr  = (uint8_t *)NULL;
-  hspi->TxISR       = NULL;
-  hspi->RxISR       = NULL;
-  hspi->RxXferSize  = 0U;
-  hspi->RxXferCount = 0U;
-
-  /* Configure communication direction : 1Line */
-  if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
-  {
-    SPI_1LINE_TX(hspi);
-  }
-
-#if (USE_SPI_CRC != 0U)
-  /* Reset CRC Calculation */
-  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Set the SPI TxDMA Half transfer complete callback */
-  hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
-
-  /* Set the SPI TxDMA transfer complete callback */
-  hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
-
-  /* Set the DMA error callback */
-  hspi->hdmatx->XferErrorCallback = SPI_DMAError;
-
-  /* Set the DMA AbortCpltCallback */
-  hspi->hdmatx->XferAbortCallback = NULL;
-
-  /* Enable the Tx DMA Stream */
-  HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
-
-  /* Check if the SPI is already enabled */
-  if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-
-  /* Enable the SPI Error Interrupt Bit */
-  SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
-
-  /* Enable Tx DMA Request */
-  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
-error :
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Receive an amount of data in non-blocking mode with DMA.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pData: pointer to data buffer
-  * @note   When the CRC feature is enabled the pData Length must be Size + 1.
-  * @param  Size: amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
-{
-  HAL_StatusTypeDef errorcode = HAL_OK;
-
-  if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
-  {
-     hspi->State = HAL_SPI_STATE_BUSY_RX;
-     /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
-     return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
-  }
-
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  if(hspi->State != HAL_SPI_STATE_READY)
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  if((pData == NULL) || (Size == 0U))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  /* Set the transaction information */
-  hspi->State       = HAL_SPI_STATE_BUSY_RX;
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pRxBuffPtr  = (uint8_t *)pData;
-  hspi->RxXferSize  = Size;
-  hspi->RxXferCount = Size;
-
-  /*Init field not used in handle to zero */
-  hspi->RxISR       = NULL;
-  hspi->TxISR       = NULL;
-  hspi->TxXferSize  = 0U;
-  hspi->TxXferCount = 0U;
-
-  /* Configure communication direction : 1Line */
-  if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
-  {
-    SPI_1LINE_RX(hspi);
-  }
-
-#if (USE_SPI_CRC != 0U)
-  /* Reset CRC Calculation */
-  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Set the SPI RxDMA Half transfer complete callback */
-  hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
-
-  /* Set the SPI Rx DMA transfer complete callback */
-  hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
-
-  /* Set the DMA error callback */
-  hspi->hdmarx->XferErrorCallback = SPI_DMAError;
-
- /* Set the DMA AbortCpltCallback */
-  hspi->hdmarx->XferAbortCallback = NULL;
-
-  /* Enable the Rx DMA Stream */
-  HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
-
-  /* Check if the SPI is already enabled */
-  if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-
-  /* Enable the SPI Error Interrupt Bit */
-  SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
-
-  /* Enable Rx DMA Request */
-  SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-
-error:
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Transmit and Receive an amount of data in non-blocking mode with DMA.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pTxData: pointer to transmission data buffer
-  * @param  pRxData: pointer to reception data buffer
-  * @note   When the CRC feature is enabled the pRxData Length must be Size + 1
-  * @param  Size: amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
-{
-  uint32_t tmp = 0U, tmp1 = 0U;
-  HAL_StatusTypeDef errorcode = HAL_OK;
-
-  /* Check Direction parameter */
-  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
-
-  /* Process locked */
-  __HAL_LOCK(hspi);
-
-  tmp  = hspi->State;
-  tmp1 = hspi->Init.Mode;
-  if(!((tmp == HAL_SPI_STATE_READY) ||
-      ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
-  if(hspi->State == HAL_SPI_STATE_READY)
-  {
-    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
-  }
-
-  /* Set the transaction information */
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pTxBuffPtr  = (uint8_t*)pTxData;
-  hspi->TxXferSize  = Size;
-  hspi->TxXferCount = Size;
-  hspi->pRxBuffPtr  = (uint8_t*)pRxData;
-  hspi->RxXferSize  = Size;
-  hspi->RxXferCount = Size;
-
-  /* Init field not used in handle to zero */
-  hspi->RxISR       = NULL;
-  hspi->TxISR       = NULL;
-
-#if (USE_SPI_CRC != 0U)
-  /* Reset CRC Calculation */
-  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
-  if(hspi->State == HAL_SPI_STATE_BUSY_RX)
-  {
-    /* Set the SPI Rx DMA Half transfer complete callback */
-    hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
-    hspi->hdmarx->XferCpltCallback     = SPI_DMAReceiveCplt;
-  }
-  else
-  {
-    /* Set the SPI Tx/Rx DMA Half transfer complete callback */
-    hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
-    hspi->hdmarx->XferCpltCallback     = SPI_DMATransmitReceiveCplt;
-  }
-
-  /* Set the DMA error callback */
-  hspi->hdmarx->XferErrorCallback = SPI_DMAError;
-
-  /* Set the DMA AbortCpltCallback */
-  hspi->hdmarx->XferAbortCallback = NULL;
-
-  /* Enable the Rx DMA Stream */
-  HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
-
-  /* Enable Rx DMA Request */
-  SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-
-  /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
-  is performed in DMA reception complete callback  */
-  hspi->hdmatx->XferHalfCpltCallback = NULL;
-  hspi->hdmatx->XferCpltCallback     = NULL;
-  hspi->hdmatx->XferErrorCallback    = NULL;
-  hspi->hdmatx->XferAbortCallback    = NULL;
-
-  /* Enable the Tx DMA Stream */
-  HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
-
-  /* Check if the SPI is already enabled */
-  if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-  /* Enable the SPI Error Interrupt Bit */
-  SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
-
-  /* Enable Tx DMA Request */
-  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
-error :
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Pause the DMA Transfer.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for the specified SPI module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
-{
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  /* Disable the SPI DMA Tx & Rx requests */
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Resume the DMA Transfer.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for the specified SPI module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
-{
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  /* Enable the SPI DMA Tx & Rx requests */
-  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Stop the DMA Transfer.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for the specified SPI module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
-{
-  /* The Lock is not implemented on this API to allow the user application
-     to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
-     when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
-     and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
-     */
-
-  /* Abort the SPI DMA tx Stream */
-  if(hspi->hdmatx != NULL)
-  {
-    HAL_DMA_Abort(hspi->hdmatx);
-  }
-  /* Abort the SPI DMA rx Stream */
-  if(hspi->hdmarx != NULL)
-  {
-    HAL_DMA_Abort(hspi->hdmarx);
-  }
-
-  /* Disable the SPI DMA Tx & Rx requests */
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-  hspi->State = HAL_SPI_STATE_READY;
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle SPI interrupt request.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for the specified SPI module.
-  * @retval None
-  */
-void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
-{
-  uint32_t itsource = hspi->Instance->CR2;
-  uint32_t itflag   = hspi->Instance->SR;
-
-  /* SPI in mode Receiver ----------------------------------------------------*/
-  if(((itflag & SPI_FLAG_OVR) == RESET) &&
-     ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
-  {
-    hspi->RxISR(hspi);
-    return;
-  }
-
-  /* SPI in mode Transmitter -------------------------------------------------*/
-  if(((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
-  {
-    hspi->TxISR(hspi);
-    return;
-  }
-
-  /* SPI in Error Treatment --------------------------------------------------*/
-  if(((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET) && ((itsource & SPI_IT_ERR) != RESET))
-  {
-    /* SPI Overrun error interrupt occurred ----------------------------------*/
-    if((itflag & SPI_FLAG_OVR) != RESET)
-    {
-      if(hspi->State != HAL_SPI_STATE_BUSY_TX)
-      {
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
-        __HAL_SPI_CLEAR_OVRFLAG(hspi);
-      }
-      else
-      {
-        __HAL_SPI_CLEAR_OVRFLAG(hspi);
-        return;
-      }
-    }
-
-    /* SPI Mode Fault error interrupt occurred -------------------------------*/
-    if((itflag & SPI_FLAG_MODF) != RESET)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
-      __HAL_SPI_CLEAR_MODFFLAG(hspi);
-    }
-
-    /* SPI Frame error interrupt occurred ------------------------------------*/
-    if((itflag & SPI_FLAG_FRE) != RESET)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
-      __HAL_SPI_CLEAR_FREFLAG(hspi);
-    }
-
-    if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
-    {
-      /* Disable all interrupts */
-      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
-
-      hspi->State = HAL_SPI_STATE_READY;
-      /* Disable the SPI DMA requests if enabled */
-      if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN))||(HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
-      {
-        CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
-
-        /* Abort the SPI DMA Rx channel */
-        if(hspi->hdmarx != NULL)
-        {
-          /* Set the SPI DMA Abort callback :
-          will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
-          hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
-          HAL_DMA_Abort_IT(hspi->hdmarx);
-        }
-        /* Abort the SPI DMA Tx channel */
-        if(hspi->hdmatx != NULL)
-        {
-          /* Set the SPI DMA Abort callback :
-          will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
-          hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
-          HAL_DMA_Abort_IT(hspi->hdmatx);
-        }
-      }
-      else
-      {
-        /* Call user error callback */
-        HAL_SPI_ErrorCallback(hspi);
-      }
-    }
-    return;
-  }
-}
-
-/**
-  * @brief Tx Transfer completed callback.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_TxCpltCallback should be implemented in the user file
-  */
-}
-
-/**
-  * @brief Rx Transfer completed callback.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_RxCpltCallback should be implemented in the user file
-  */
-}
-
-/**
-  * @brief Tx and Rx Transfer completed callback.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_TxRxCpltCallback should be implemented in the user file
-  */
-}
-
-/**
-  * @brief Tx Half Transfer completed callback.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
-  */
-}
-
-/**
-  * @brief Rx Half Transfer completed callback.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
-  */
-}
-
-/**
-  * @brief Tx and Rx Half Transfer callback.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
-  */
-}
-
-/**
-  * @brief SPI error callback.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
- __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_ErrorCallback should be implemented in the user file
-   */
-  /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
-            and user can use HAL_SPI_GetError() API to check the latest error occurred
-  */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
-  * @brief   SPI control functions
-  *
-@verbatim
- ===============================================================================
-                      ##### Peripheral State and Errors functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to control the SPI.
-     (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
-     (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the SPI handle state.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval SPI state
-  */
-HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
-{
-  /* Return SPI handle state */
-  return hspi->State;
-}
-
-/**
-  * @brief  Return the SPI error code.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval SPI error code in bitmap format
-  */
-uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
-{
-  /* Return SPI ErrorCode */
-  return hspi->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup SPI_Private_Functions
-  * @brief   Private functions
-  * @{
-  */
-
-/**
-  * @brief DMA SPI transmit process complete callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  uint32_t tickstart = 0U;
-
-  /* Init tickstart for timeout managment*/
-  tickstart = HAL_GetTick();
-
-  /* DMA Normal Mode */
-  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
-  {
-    /* Disable Tx DMA Request */
-    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
-    /* Check the end of the transaction */
-    if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-    }
-
-    /* Clear overrun flag in 2 Lines communication mode because received data is not read */
-    if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
-    {
-      __HAL_SPI_CLEAR_OVRFLAG(hspi);
-    }
-
-    hspi->TxXferCount = 0U;
-    hspi->State = HAL_SPI_STATE_READY;
-
-    if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
-    {
-      HAL_SPI_ErrorCallback(hspi);
-      return;
-    }
-  }
-  HAL_SPI_TxCpltCallback(hspi);
-}
-
-/**
-  * @brief DMA SPI receive process complete callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-#if (USE_SPI_CRC != 0U)
-  uint32_t tickstart = 0U;
-  __IO uint16_t tmpreg = 0U;
-
-  /* Init tickstart for timeout management*/
-  tickstart = HAL_GetTick();
-#endif /* USE_SPI_CRC */
-
-  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
-  {
-#if (USE_SPI_CRC != 0U)
-    /* CRC handling */
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      /* Wait until RXNE flag */
-      if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
-      {
-        /* Error on the CRC reception */
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-      }
-      /* Read CRC */
-      tmpreg = hspi->Instance->DR;
-      /* To avoid GCC warning */
-      UNUSED(tmpreg);
-    }
-#endif /* USE_SPI_CRC */
-
-    /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
-    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
-    if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
-    {
-      /* Disable SPI peripheral */
-      __HAL_SPI_DISABLE(hspi);
-    }
-
-    hspi->RxXferCount = 0U;
-    hspi->State = HAL_SPI_STATE_READY;
-
-#if (USE_SPI_CRC != 0U)
-    /* Check if CRC error occurred */
-    if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-    }
-#endif /* USE_SPI_CRC */
-
-    if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
-    {
-      HAL_SPI_ErrorCallback(hspi);
-      return;
-    }
-  }
-  HAL_SPI_RxCpltCallback(hspi);
-}
-
-/**
-  * @brief  DMA SPI transmit receive process complete callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  uint32_t tickstart = 0U;
-#if (USE_SPI_CRC != 0U)
-  __IO int16_t tmpreg = 0U;
-#endif /* USE_SPI_CRC */
-  /* Init tickstart for timeout management*/
-  tickstart = HAL_GetTick();
-
-  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
-  {
-#if (USE_SPI_CRC != 0U)
-    /* CRC handling */
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      /* Wait the CRC data */
-      if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
-      {
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-      }
-      /* Read CRC to Flush DR and RXNE flag */
-      tmpreg = hspi->Instance->DR;
-      /* To avoid GCC warning */
-      UNUSED(tmpreg);
-    }
-#endif /* USE_SPI_CRC */
-    /* Check the end of the transaction */
-    if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-    }
-
-    /* Disable Rx/Tx DMA Request */
-    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
-    hspi->TxXferCount = 0U;
-    hspi->RxXferCount = 0U;
-    hspi->State = HAL_SPI_STATE_READY;
-
-#if (USE_SPI_CRC != 0U)
-    /* Check if CRC error occurred */
-    if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-    }
-#endif /* USE_SPI_CRC */
-
-    if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
-    {
-      HAL_SPI_ErrorCallback(hspi);
-      return;
-    }
-  }
-  HAL_SPI_TxRxCpltCallback(hspi);
-}
-
-/**
-  * @brief  DMA SPI half transmit process complete callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  HAL_SPI_TxHalfCpltCallback(hspi);
-}
-
-/**
-  * @brief  DMA SPI half receive process complete callback
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  HAL_SPI_RxHalfCpltCallback(hspi);
-}
-
-/**
-  * @brief  DMA SPI half transmit receive process complete callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  HAL_SPI_TxRxHalfCpltCallback(hspi);
-}
-
-/**
-  * @brief  DMA SPI communication error callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SPI_DMAError(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-/* Stop the disable DMA transfer on SPI side */
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
-  SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
-  hspi->State = HAL_SPI_STATE_READY;
-  HAL_SPI_ErrorCallback(hspi);
-}
-
-/**
-  * @brief  DMA SPI communication abort callback, when initiated by HAL services on Error
-  *         (To be called at end of DMA Abort procedure following error occurrence).
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  hspi->RxXferCount = 0;
-  hspi->TxXferCount = 0;
-
-  HAL_SPI_ErrorCallback(hspi);
-}
-
-/**
-  * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
-{
-  /* Receive data in 8bit mode */
-  *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR);
-  hspi->RxXferCount--;
-
-  /* check end of the reception */
-  if(hspi->RxXferCount == 0U)
-  {
-#if (USE_SPI_CRC != 0U)
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      hspi->RxISR =  SPI_2linesRxISR_8BITCRC;
-      return;
-    }
-#endif /* USE_SPI_CRC */
-
-    /* Disable RXNE interrupt */
-    __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
-    if(hspi->TxXferCount == 0U)
-    {
-      SPI_CloseRxTx_ISR(hspi);
-    }
-  }
-}
-
-#if (USE_SPI_CRC != 0U)
-/**
-  * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
-{
-  __IO uint8_t tmpreg = 0U;
-
-  /* Read data register to flush CRC */
-  tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
-
-  /* To avoid GCC warning */
-
-  UNUSED(tmpreg);
-
-   /* Disable RXNE interrupt */
-  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
-  if(hspi->TxXferCount == 0U)
-  {
-    SPI_CloseRxTx_ISR(hspi);
-  }
-}
-#endif /* USE_SPI_CRC */
-
-/**
-  * @brief  Tx 8-bit handler for Transmit and Receive in Interrupt mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
-{
-  *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
-  hspi->TxXferCount--;
-
-  /* check the end of the transmission */
-  if(hspi->TxXferCount == 0U)
-  {
-#if (USE_SPI_CRC != 0U)
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
-      return;
-    }
-#endif /* USE_SPI_CRC */
-
-    /* Disable TXE interrupt */
-    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
-
-    if(hspi->RxXferCount == 0U)
-    {
-      SPI_CloseRxTx_ISR(hspi);
-    }
-  }
-}
-
-/**
-  * @brief  Rx 16-bit handler for Transmit and Receive in Interrupt mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
-{
-  /* Receive data in 16 Bit mode */
-  *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
-  hspi->pRxBuffPtr += sizeof(uint16_t);
-  hspi->RxXferCount--;
-
-  if(hspi->RxXferCount == 0U)
-  {
-#if (USE_SPI_CRC != 0U)
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      hspi->RxISR =  SPI_2linesRxISR_16BITCRC;
-      return;
-    }
-#endif /* USE_SPI_CRC */
-
-    /* Disable RXNE interrupt */
-    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
-
-    if(hspi->TxXferCount == 0U)
-    {
-      SPI_CloseRxTx_ISR(hspi);
-    }
-  }
-}
-
-#if (USE_SPI_CRC != 0U)
-/**
-  * @brief  Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
-{
-  /* Receive data in 16 Bit mode */
-  __IO uint16_t tmpreg = 0U;
-
-  /* Read data register to flush CRC */
-  tmpreg = hspi->Instance->DR;
-
-  /* To avoid GCC warning */
-  UNUSED(tmpreg);
-
-  /* Disable RXNE interrupt */
-  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
-
-  SPI_CloseRxTx_ISR(hspi);
-}
-#endif /* USE_SPI_CRC */
-
-/**
-  * @brief  Tx 16-bit handler for Transmit and Receive in Interrupt mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
-{
-  /* Transmit data in 16 Bit mode */
-  hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
-  hspi->pTxBuffPtr += sizeof(uint16_t);
-  hspi->TxXferCount--;
-
-  /* Enable CRC Transmission */
-  if(hspi->TxXferCount == 0U)
-  {
-#if (USE_SPI_CRC != 0U)
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
-      return;
-    }
-#endif /* USE_SPI_CRC */
-
-    /* Disable TXE interrupt */
-    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
-
-    if(hspi->RxXferCount == 0U)
-    {
-      SPI_CloseRxTx_ISR(hspi);
-    }
-  }
-}
-
-#if (USE_SPI_CRC != 0U)
-/**
-  * @brief  Manage the CRC 8-bit receive in Interrupt context.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
-{
-  __IO uint8_t tmpreg = 0U;
-
-  /* Read data register to flush CRC */
-  tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
-
-  /* To avoid GCC warning */
-  UNUSED(tmpreg);
-
-  SPI_CloseRx_ISR(hspi);
-}
-#endif /* USE_SPI_CRC */
-
-/**
-  * @brief  Manage the receive 8-bit in Interrupt context.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
-{
-  *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);
-  hspi->RxXferCount--;
-
-#if (USE_SPI_CRC != 0U)
-  /* Enable CRC Transmission */
-  if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
-  {
-    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-  }
-#endif /* USE_SPI_CRC */
-
-  if(hspi->RxXferCount == 0U)
-  {
-#if (USE_SPI_CRC != 0U)
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      hspi->RxISR =  SPI_RxISR_8BITCRC;
-      return;
-    }
-#endif /* USE_SPI_CRC */
-    SPI_CloseRx_ISR(hspi);
-  }
-}
-
-#if (USE_SPI_CRC != 0U)
-/**
-  * @brief  Manage the CRC 16-bit receive in Interrupt context.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
-{
-  __IO uint16_t tmpreg = 0U;
-
-  /* Read data register to flush CRC */
-  tmpreg = hspi->Instance->DR;
-
-  /* To avoid GCC warning */
-  UNUSED(tmpreg);
-
-  /* Disable RXNE and ERR interrupt */
-  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
-  SPI_CloseRx_ISR(hspi);
-}
-#endif /* USE_SPI_CRC */
-
-/**
-  * @brief  Manage the 16-bit receive in Interrupt context.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
-{
-  *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
-  hspi->pRxBuffPtr += sizeof(uint16_t);
-  hspi->RxXferCount--;
-
-#if (USE_SPI_CRC != 0U)
-  /* Enable CRC Transmission */
-  if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
-  {
-    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-  }
-#endif /* USE_SPI_CRC */
-
-  if(hspi->RxXferCount == 0U)
-  {
-#if (USE_SPI_CRC != 0U)
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      hspi->RxISR = SPI_RxISR_16BITCRC;
-      return;
-    }
-#endif /* USE_SPI_CRC */
-    SPI_CloseRx_ISR(hspi);
-  }
-}
-
-/**
-  * @brief  Handle the data 8-bit transmit in Interrupt mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
-{
-  *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
-  hspi->TxXferCount--;
-
-  if(hspi->TxXferCount == 0U)
-  {
-#if (USE_SPI_CRC != 0U)
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      /* Enable CRC Transmission */
-      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-    }
-#endif /* USE_SPI_CRC */
-    SPI_CloseTx_ISR(hspi);
-  }
-}
-
-/**
-  * @brief  Handle the data 16-bit transmit in Interrupt mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
-{
-  /* Transmit data in 16 Bit mode */
-  hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
-  hspi->pTxBuffPtr += sizeof(uint16_t);
-  hspi->TxXferCount--;
-
-  if(hspi->TxXferCount == 0U)
-  {
-#if (USE_SPI_CRC != 0U)
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      /* Enable CRC Transmission */
-      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-    }
-#endif /* USE_SPI_CRC */
-    SPI_CloseTx_ISR(hspi);
-  }
-}
-
-/**
-  * @brief Handle SPI Communication Timeout.
-  * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *              the configuration information for SPI module.
-  * @param Flag: SPI flag to check
-  * @param State: flag state to check
-  * @param Timeout: Timeout duration
-  * @param Tickstart: tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart)
-{
-  while((((hspi->Instance->SR & Flag) == (Flag)) ? SET : RESET) != State)
-  {
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) >= Timeout))
-      {
-        /* Disable the SPI and reset the CRC: the CRC value should be cleared
-        on both master and slave sides in order to resynchronize the master
-        and slave for their respective CRC calculation */
-
-        /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
-        __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
-
-        if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
-        {
-          /* Disable SPI peripheral */
-          __HAL_SPI_DISABLE(hspi);
-        }
-
-        /* Reset CRC Calculation */
-        if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-        {
-          SPI_RESET_CRC(hspi);
-        }
-
-        hspi->State= HAL_SPI_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hspi);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  return HAL_OK;
-}
-/**
-  * @brief Handle to check BSY flag before start a new transaction.
-  * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *              the configuration information for SPI module.
-  * @param Timeout: Timeout duration
-  * @param Tickstart: tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
-{
-  /* Control the BSY flag */
-  if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
-  {
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-    return HAL_TIMEOUT;
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle the end of the RXTX transaction.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
-{
-  uint32_t tickstart = 0U;
-  __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24 / 1000);
-  /* Init tickstart for timeout managment*/
-  tickstart = HAL_GetTick();
-
-  /* Disable ERR interrupt */
-  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
-
-  /* Wait until TXE flag is set */
-  do
-  {
-    if(count-- == 0)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-      break;
-    }
-  }
-  while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
-  
-  /* Check the end of the transaction */
-  if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart)!=HAL_OK)
-  {
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-  }
-
-  /* Clear overrun flag in 2 Lines communication mode because received is not read */
-  if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
-  {
-    __HAL_SPI_CLEAR_OVRFLAG(hspi);
-  }
-
-#if (USE_SPI_CRC != 0U)
-  /* Check if CRC error occurred */
-  if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
-  {
-    hspi->State = HAL_SPI_STATE_READY;
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-    HAL_SPI_ErrorCallback(hspi);
-  }
-  else
-  {
-#endif /* USE_SPI_CRC */
-    if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
-    {
-      if(hspi->State == HAL_SPI_STATE_BUSY_RX)
-      {
-      	hspi->State = HAL_SPI_STATE_READY;
-        HAL_SPI_RxCpltCallback(hspi);
-      }
-      else
-      {
-      	hspi->State = HAL_SPI_STATE_READY;
-        HAL_SPI_TxRxCpltCallback(hspi);
-      }
-    }
-    else
-    {
-      hspi->State = HAL_SPI_STATE_READY;
-      HAL_SPI_ErrorCallback(hspi);
-    }
-#if (USE_SPI_CRC != 0U)
-  }
-#endif /* USE_SPI_CRC */
-}
-
-/**
-  * @brief  Handle the end of the RX transaction.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
-{
-    /* Disable RXNE and ERR interrupt */
-    __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
-    /* Check the end of the transaction */
-    if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
-    {
-      /* Disable SPI peripheral */
-      __HAL_SPI_DISABLE(hspi);
-    }
-
-    /* Clear overrun flag in 2 Lines communication mode because received is not read */
-    if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
-    {
-      __HAL_SPI_CLEAR_OVRFLAG(hspi);
-    }
-    hspi->State = HAL_SPI_STATE_READY;
-
-#if (USE_SPI_CRC != 0U)
-    /* Check if CRC error occurred */
-    if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-      HAL_SPI_ErrorCallback(hspi);
-    }
-    else
-    {
-#endif /* USE_SPI_CRC */
-      if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
-      {
-        HAL_SPI_RxCpltCallback(hspi);
-      }
-      else
-      {
-        HAL_SPI_ErrorCallback(hspi);
-      }
-#if (USE_SPI_CRC != 0U)
-    }
-#endif /* USE_SPI_CRC */
-}
-
-/**
-  * @brief  Handle the end of the TX transaction.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
-{
-  uint32_t tickstart = 0U;
-  __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24 / 1000);
-
-  /* Init tickstart for timeout management*/
-  tickstart = HAL_GetTick();
-
-  /* Wait until TXE flag is set */
-  do
-  {
-    if(count-- == 0)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-      break;
-    }
-  }
-  while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
-
-  /* Disable TXE and ERR interrupt */
-  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
-
-  /* Check Busy flag */
-  if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
-  {
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-  }
-
-  /* Clear overrun flag in 2 Lines communication mode because received is not read */
-  if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
-  {
-    __HAL_SPI_CLEAR_OVRFLAG(hspi);
-  }
-
-  hspi->State = HAL_SPI_STATE_READY;
-  if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
-  {
-    HAL_SPI_ErrorCallback(hspi);
-  }
-  else
-  {
-    HAL_SPI_TxCpltCallback(hspi);
-  }
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_tim.c b/stmhal/hal/f4/src/stm32f4xx_hal_tim.c
deleted file mode 100644
index 72d9abb447..0000000000
--- a/stmhal/hal/f4/src/stm32f4xx_hal_tim.c
+++ /dev/null
@@ -1,5387 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_tim.c
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   TIM HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the Timer (TIM) peripheral:
-  *           + Time Base Initialization
-  *           + Time Base Start
-  *           + Time Base Start Interruption
-  *           + Time Base Start DMA
-  *           + Time Output Compare/PWM Initialization
-  *           + Time Output Compare/PWM Channel Configuration
-  *           + Time Output Compare/PWM  Start
-  *           + Time Output Compare/PWM  Start Interruption
-  *           + Time Output Compare/PWM Start DMA
-  *           + Time Input Capture Initialization
-  *           + Time Input Capture Channel Configuration
-  *           + Time Input Capture Start
-  *           + Time Input Capture Start Interruption 
-  *           + Time Input Capture Start DMA
-  *           + Time One Pulse Initialization
-  *           + Time One Pulse Channel Configuration
-  *           + Time One Pulse Start 
-  *           + Time Encoder Interface Initialization
-  *           + Time Encoder Interface Start
-  *           + Time Encoder Interface Start Interruption
-  *           + Time Encoder Interface Start DMA
-  *           + Commutation Event configuration with Interruption and DMA
-  *           + Time OCRef clear configuration
-  *           + Time External Clock configuration
-  @verbatim 
-  ==============================================================================
-                      ##### TIMER Generic features #####
-  ==============================================================================
-  [..] The Timer features include: 
-       (#) 16-bit up, down, up/down auto-reload counter.
-       (#) 16-bit programmable prescaler allowing dividing (also on the fly) the 
-           counter clock frequency either by any factor between 1 and 65536.
-       (#) Up to 4 independent channels for:
-           (++) Input Capture
-           (++) Output Compare
-           (++) PWM generation (Edge and Center-aligned Mode)
-           (++) One-pulse mode output               
-   
-                        ##### How to use this driver #####
-  ==============================================================================
-    [..]
-     (#) Initialize the TIM low level resources by implementing the following functions 
-         depending from feature used :
-           (++) Time Base : HAL_TIM_Base_MspInit() 
-           (++) Input Capture : HAL_TIM_IC_MspInit()
-           (++) Output Compare : HAL_TIM_OC_MspInit()
-           (++) PWM generation : HAL_TIM_PWM_MspInit()
-           (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
-           (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
-           
-     (#) Initialize the TIM low level resources :
-        (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE(); 
-        (##) TIM pins configuration
-            (+++) Enable the clock for the TIM GPIOs using the following function:
-                 __GPIOx_CLK_ENABLE();   
-            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();  
-
-     (#) The external Clock can be configured, if needed (the default clock is the 
-         internal clock from the APBx), using the following function:
-         HAL_TIM_ConfigClockSource, the clock configuration should be done before 
-         any start function.
-  
-     (#) Configure the TIM in the desired functioning mode using one of the 
-         initialization function of this driver:
-         (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
-         (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an 
-              Output Compare signal.
-         (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a 
-              PWM signal.
-         (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an 
-              external signal.
-         (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer 
-              in One Pulse Mode.
-         (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
-         
-     (#) Activate the TIM peripheral using one of the start functions depending from the feature used: 
-           (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
-           (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
-           (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
-           (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
-           (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
-           (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
-
-     (#) The DMA Burst is managed with the two following functions:
-         HAL_TIM_DMABurst_WriteStart()
-         HAL_TIM_DMABurst_ReadStart()
-  
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup TIM TIM
-  * @brief TIM HAL module driver
-  * @{
-  */
-
-#ifdef HAL_TIM_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @addtogroup TIM_Private_Functions
-  * @{
-  */
-/* Private function prototypes -----------------------------------------------*/
-static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-
-static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
-static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                       uint32_t TIM_ICFilter);
-static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
-static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                       uint32_t TIM_ICFilter);
-static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                       uint32_t TIM_ICFilter);
-
-static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
-                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
-
-static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t TIM_ITRx);
-static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
-static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
-static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
-                                     TIM_SlaveConfigTypeDef * sSlaveConfig);
-/**
-  * @}
-  */
-  
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup TIM_Exported_Functions TIM Exported Functions
-  * @{
-  */
-
-/** @defgroup TIM_Exported_Functions_Group1 Time Base functions 
- *  @brief    Time Base functions 
- *
-@verbatim    
-  ==============================================================================
-              ##### Time Base functions #####
-  ==============================================================================
-  [..]  
-    This section provides functions allowing to:
-    (+) Initialize and configure the TIM base. 
-    (+) De-initialize the TIM base.
-    (+) Start the Time Base.
-    (+) Stop the Time Base.
-    (+) Start the Time Base and enable interrupt.
-    (+) Stop the Time Base and disable interrupt.
-    (+) Start the Time Base and enable DMA transfer.
-    (+) Stop the Time Base and disable DMA transfer.
- 
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIM Time base Unit according to the specified
-  *         parameters in the TIM_HandleTypeDef and create the associated handle.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
-{ 
-  /* Check the TIM handle allocation */
-  if(htim == NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance)); 
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-  
-  if(htim->State == HAL_TIM_STATE_RESET)
-  {  
-    /* Allocate lock resource and initialize it */
-    htim->Lock = HAL_UNLOCKED;
-    /* Init the low level hardware : GPIO, CLOCK, NVIC */
-    HAL_TIM_Base_MspInit(htim);
-  }
-  
-  /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;
-  
-  /* Set the Time Base configuration */
-  TIM_Base_SetConfig(htim->Instance, &htim->Init); 
-  
-  /* Initialize the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the TIM Base peripheral 
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
-{  
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  htim->State = HAL_TIM_STATE_BUSY;
-   
-  /* Disable the TIM Peripheral Clock */
-  __HAL_TIM_DISABLE(htim);
-    
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
-  HAL_TIM_Base_MspDeInit(htim);
-  
-  /* Change TIM state */  
-  htim->State = HAL_TIM_STATE_RESET; 
-  
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM Base MSP.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_Base_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes TIM Base MSP.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_Base_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Starts the TIM Base generation.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  
-  /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;
-  
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-  
-  /* Change the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Base generation.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  
-  /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;
-  
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-  
-  /* Change the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Base generation in interrupt mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  
-  /* Enable the TIM Update interrupt */
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
-      
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-      
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Base generation in interrupt mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  /* Disable the TIM Update interrupt */
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
-      
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-    
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Base generation in DMA mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  pData: The source Buffer address.
-  * @param  Length: The length of data to be transferred from memory to peripheral.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); 
-  
-  if((htim->State == HAL_TIM_STATE_BUSY))
-  {
-     return HAL_BUSY;
-  }
-  else if((htim->State == HAL_TIM_STATE_READY))
-  {
-    if((pData == 0U) && (Length > 0U)) 
-    {
-      return HAL_ERROR;                                    
-    }
-    else
-    {
-      htim->State = HAL_TIM_STATE_BUSY;
-    }
-  }  
-  /* Set the DMA Period elapsed callback */
-  htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
-     
-  /* Set the DMA error callback */
-  htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
-  
-  /* Enable the DMA Stream */
-  HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
-  
-  /* Enable the TIM Update DMA request */
-  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);  
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Base generation in DMA mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
-  
-  /* Disable the TIM Update DMA request */
-  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
-      
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-    
-  /* Change the htim state */
-  htim->State = HAL_TIM_STATE_READY;
-      
-  /* Return function status */
-  return HAL_OK;
-}
-/**
-  * @}
-  */
-  
-/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions 
- *  @brief    Time Output Compare functions 
- *
-@verbatim    
-  ==============================================================================
-                  ##### Time Output Compare functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Initialize and configure the TIM Output Compare. 
-    (+) De-initialize the TIM Output Compare.
-    (+) Start the Time Output Compare.
-    (+) Stop the Time Output Compare.
-    (+) Start the Time Output Compare and enable interrupt.
-    (+) Stop the Time Output Compare and disable interrupt.
-    (+) Start the Time Output Compare and enable DMA transfer.
-    (+) Stop the Time Output Compare and disable DMA transfer.
- 
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIM Output Compare according to the specified
-  *         parameters in the TIM_HandleTypeDef and create the associated handle.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
-{
-  /* Check the TIM handle allocation */
-  if(htim == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- 
-  if(htim->State == HAL_TIM_STATE_RESET)
-  { 
-    /* Allocate lock resource and initialize it */
-    htim->Lock = HAL_UNLOCKED;
-    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
-    HAL_TIM_OC_MspInit(htim);
-  }
-  
-  /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;
-  
-  /* Init the base time for the Output Compare */  
-  TIM_Base_SetConfig(htim->Instance,  &htim->Init); 
-  
-  /* Initialize the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the TIM peripheral 
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  
-   htim->State = HAL_TIM_STATE_BUSY;
-   
-  /* Disable the TIM Peripheral Clock */
-  __HAL_TIM_DISABLE(htim);
-  
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
-  HAL_TIM_OC_MspDeInit(htim);
-    
-  /* Change TIM state */  
-  htim->State = HAL_TIM_STATE_RESET; 
-
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM Output Compare MSP.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_OC_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes TIM Output Compare MSP.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_OC_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Starts the TIM Output Compare signal generation.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.  
-  * @param  Channel: TIM Channel to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected   
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-  
-  /* Enable the Output compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-  
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
-  {
-    /* Enable the main output */
-    __HAL_TIM_MOE_ENABLE(htim);
-  }
-  
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim); 
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Output Compare signal generation.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be disabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-  
-  /* Disable the Output compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-  
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
-  {
-    /* Disable the Main Output */
-    __HAL_TIM_MOE_DISABLE(htim);
-  }  
-  
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);  
-  
-  /* Return function status */
-  return HAL_OK;
-}  
-
-/**
-  * @brief  Starts the TIM Output Compare signal generation in interrupt mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-  
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {       
-      /* Enable the TIM Capture/Compare 1 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-    }
-    break;
-    
-    case TIM_CHANNEL_2:
-    {
-      /* Enable the TIM Capture/Compare 2 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-    }
-    break;
-    
-    case TIM_CHANNEL_3:
-    {
-      /* Enable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
-    }
-    break;
-    
-    case TIM_CHANNEL_4:
-    {
-      /* Enable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
-    }
-    break;
-    
-    default:
-    break;
-  } 
-
-  /* Enable the Output compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-  
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
-  {
-    /* Enable the main output */
-    __HAL_TIM_MOE_ENABLE(htim);
-  }
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Output Compare signal generation in interrupt mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be disabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-  
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {       
-      /* Disable the TIM Capture/Compare 1 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-    }
-    break;
-    
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Capture/Compare 2 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-    }
-    break;
-    
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
-    }
-    break;
-    
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
-    }
-    break;
-    
-    default:
-    break; 
-  } 
-  
-  /* Disable the Output compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 
-  
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
-  {
-    /* Disable the Main Output */
-    __HAL_TIM_MOE_DISABLE(htim);
-  }
-  
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);  
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Output Compare signal generation in DMA mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  pData: The source Buffer address.
-  * @param  Length: The length of data to be transferred from memory to TIM peripheral
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-  
-  if((htim->State == HAL_TIM_STATE_BUSY))
-  {
-     return HAL_BUSY;
-  }
-  else if((htim->State == HAL_TIM_STATE_READY))
-  {
-    if(((uint32_t)pData == 0U) && (Length > 0U)) 
-    {
-      return HAL_ERROR;                                    
-    }
-    else
-    {
-      htim->State = HAL_TIM_STATE_BUSY;
-    }
-  }    
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {      
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
-     
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
-      
-      /* Enable the TIM Capture/Compare 1 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-    }
-    break;
-    
-    case TIM_CHANNEL_2:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
-     
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
-      
-      /* Enable the TIM Capture/Compare 2 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-    }
-    break;
-    
-    case TIM_CHANNEL_3:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
-     
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-      
-      /* Enable the TIM Capture/Compare 3 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
-    }
-    break;
-    
-    case TIM_CHANNEL_4:
-    {
-     /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
-     
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-      
-      /* Enable the TIM Capture/Compare 4 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
-    }
-    break;
-    
-    default:
-    break;
-  }
-
-  /* Enable the Output compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-  
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
-  {
-    /* Enable the main output */
-    __HAL_TIM_MOE_ENABLE(htim);
-  }  
-  
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim); 
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Output Compare signal generation in DMA mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be disabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-  
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {       
-      /* Disable the TIM Capture/Compare 1 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-    }
-    break;
-    
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Capture/Compare 2 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
-    }
-    break;
-    
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Capture/Compare 3 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
-    }
-    break;
-    
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
-    }
-    break;
-    
-    default:
-    break;
-  } 
-  
-  /* Disable the Output compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-  
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
-  {
-    /* Disable the Main Output */
-    __HAL_TIM_MOE_DISABLE(htim);
-  }
-  
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-  
-  /* Change the htim state */
-  htim->State = HAL_TIM_STATE_READY;
-  
-  /* Return function status */
-  return HAL_OK;
-}
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions 
- *  @brief    Time PWM functions 
- *
-@verbatim    
-  ==============================================================================
-                          ##### Time PWM functions #####
-  ==============================================================================
-  [..]  
-    This section provides functions allowing to:
-    (+) Initialize and configure the TIM OPWM. 
-    (+) De-initialize the TIM PWM.
-    (+) Start the Time PWM.
-    (+) Stop the Time PWM.
-    (+) Start the Time PWM and enable interrupt.
-    (+) Stop the Time PWM and disable interrupt.
-    (+) Start the Time PWM and enable DMA transfer.
-    (+) Stop the Time PWM and disable DMA transfer.
- 
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIM PWM Time Base according to the specified
-  *         parameters in the TIM_HandleTypeDef and create the associated handle.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
-{
-  /* Check the TIM handle allocation */
-  if(htim == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-
-  if(htim->State == HAL_TIM_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    htim->Lock = HAL_UNLOCKED;
-    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
-    HAL_TIM_PWM_MspInit(htim);
-  }
-
-  /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;  
-  
-  /* Init the base time for the PWM */  
-  TIM_Base_SetConfig(htim->Instance, &htim->Init); 
-   
-  /* Initialize the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-  
-  return HAL_OK;
-}  
-
-/**
-  * @brief  DeInitializes the TIM peripheral 
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  
-  htim->State = HAL_TIM_STATE_BUSY;
-  
-  /* Disable the TIM Peripheral Clock */
-  __HAL_TIM_DISABLE(htim);
-    
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
-  HAL_TIM_PWM_MspDeInit(htim);
-    
-  /* Change TIM state */  
-  htim->State = HAL_TIM_STATE_RESET; 
-
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM PWM MSP.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_PWM_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes TIM PWM MSP.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_PWM_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Starts the PWM signal generation.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  /* Enable the Capture compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-  
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
-  {
-    /* Enable the main output */
-    __HAL_TIM_MOE_ENABLE(htim);
-  }
-    
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-  
-  /* Return function status */
-  return HAL_OK;
-} 
-
-/**
-  * @brief  Stops the PWM signal generation.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be disabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{ 
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-    
-  /* Disable the Capture compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-  
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
-  {
-    /* Disable the Main Output */
-    __HAL_TIM_MOE_DISABLE(htim);
-  }
-  
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-  
-  /* Change the htim state */
-  htim->State = HAL_TIM_STATE_READY;
-  
-  /* Return function status */
-  return HAL_OK;
-} 
-
-/**
-  * @brief  Starts the PWM signal generation in interrupt mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be disabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-  
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {       
-      /* Enable the TIM Capture/Compare 1 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-    }
-    break;
-    
-    case TIM_CHANNEL_2:
-    {
-      /* Enable the TIM Capture/Compare 2 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-    }
-    break;
-    
-    case TIM_CHANNEL_3:
-    {
-      /* Enable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
-    }
-    break;
-    
-    case TIM_CHANNEL_4:
-    {
-      /* Enable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
-    }
-    break;
-    
-    default:
-    break;
-  } 
-  
-  /* Enable the Capture compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-  
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
-  {
-    /* Enable the main output */
-    __HAL_TIM_MOE_ENABLE(htim);
-  }
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-  
-  /* Return function status */
-  return HAL_OK;
-} 
-
-/**
-  * @brief  Stops the PWM signal generation in interrupt mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be disabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-  
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {       
-      /* Disable the TIM Capture/Compare 1 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-    }
-    break;
-    
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Capture/Compare 2 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-    }
-    break;
-    
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
-    }
-    break;
-    
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
-    }
-    break;
-    
-    default:
-    break; 
-  }
-  
-  /* Disable the Capture compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-  
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
-  {
-    /* Disable the Main Output */
-    __HAL_TIM_MOE_DISABLE(htim);
-  }
-  
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-  
-  /* Return function status */
-  return HAL_OK;
-} 
-
-/**
-  * @brief  Starts the TIM PWM signal generation in DMA mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  pData: The source Buffer address.
-  * @param  Length: The length of data to be transferred from memory to TIM peripheral
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-  
-  if((htim->State == HAL_TIM_STATE_BUSY))
-  {
-     return HAL_BUSY;
-  }
-  else if((htim->State == HAL_TIM_STATE_READY))
-  {
-    if(((uint32_t)pData == 0U) && (Length > 0U)) 
-    {
-      return HAL_ERROR;                                    
-    }
-    else
-    {
-      htim->State = HAL_TIM_STATE_BUSY;
-    }
-  }    
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {      
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
-     
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
-      
-      /* Enable the TIM Capture/Compare 1 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-    }
-    break;
-    
-    case TIM_CHANNEL_2:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
-     
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
-      
-      /* Enable the TIM Capture/Compare 2 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-    }
-    break;
-    
-    case TIM_CHANNEL_3:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
-     
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-      
-      /* Enable the TIM Output Capture/Compare 3 request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
-    }
-    break;
-    
-    case TIM_CHANNEL_4:
-    {
-     /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
-     
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-      
-      /* Enable the TIM Capture/Compare 4 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
-    }
-    break;
-    
-    default:
-    break;
-  }
-
-  /* Enable the Capture compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-    
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
-  {
-    /* Enable the main output */
-    __HAL_TIM_MOE_ENABLE(htim);
-  }
-  
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim); 
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM PWM signal generation in DMA mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be disabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-  
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {       
-      /* Disable the TIM Capture/Compare 1 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-    }
-    break;
-    
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Capture/Compare 2 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
-    }
-    break;
-    
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Capture/Compare 3 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
-    }
-    break;
-    
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
-    }
-    break;
-    
-    default:
-    break;
-  } 
-  
-  /* Disable the Capture compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-  
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
-  {
-    /* Disable the Main Output */
-    __HAL_TIM_MOE_DISABLE(htim);
-  }
-  
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-  
-  /* Change the htim state */
-  htim->State = HAL_TIM_STATE_READY;
-  
-  /* Return function status */
-  return HAL_OK;
-}
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions 
- *  @brief    Time Input Capture functions 
- *
-@verbatim    
-  ==============================================================================
-              ##### Time Input Capture functions #####
-  ==============================================================================
- [..]  
-   This section provides functions allowing to:
-   (+) Initialize and configure the TIM Input Capture. 
-   (+) De-initialize the TIM Input Capture.
-   (+) Start the Time Input Capture.
-   (+) Stop the Time Input Capture.
-   (+) Start the Time Input Capture and enable interrupt.
-   (+) Stop the Time Input Capture and disable interrupt.
-   (+) Start the Time Input Capture and enable DMA transfer.
-   (+) Stop the Time Input Capture and disable DMA transfer.
- 
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIM Input Capture Time base according to the specified
-  *         parameters in the TIM_HandleTypeDef and create the associated handle.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
-{
-  /* Check the TIM handle allocation */
-  if(htim == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); 
-
-  if(htim->State == HAL_TIM_STATE_RESET)
-  { 
-    /* Allocate lock resource and initialize it */
-    htim->Lock = HAL_UNLOCKED;
-    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
-    HAL_TIM_IC_MspInit(htim);
-  }
-  
-  /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;   
-  
-  /* Init the base time for the input capture */  
-  TIM_Base_SetConfig(htim->Instance, &htim->Init); 
-   
-  /* Initialize the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the TIM peripheral 
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  htim->State = HAL_TIM_STATE_BUSY;
-  
-  /* Disable the TIM Peripheral Clock */
-  __HAL_TIM_DISABLE(htim);
-    
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
-  HAL_TIM_IC_MspDeInit(htim);
-    
-  /* Change TIM state */  
-  htim->State = HAL_TIM_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM INput Capture MSP.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_IC_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes TIM Input Capture MSP.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_IC_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Starts the TIM Input Capture measurement.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-  
-  /* Enable the Input Capture channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-    
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);  
-
-  /* Return function status */
-  return HAL_OK;  
-} 
-
-/**
-  * @brief  Stops the TIM Input Capture measurement.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be disabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{ 
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-  
-  /* Disable the Input Capture channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-  
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim); 
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Input Capture measurement in interrupt mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-  
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {       
-      /* Enable the TIM Capture/Compare 1 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-    }
-    break;
-    
-    case TIM_CHANNEL_2:
-    {
-      /* Enable the TIM Capture/Compare 2 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-    }
-    break;
-    
-    case TIM_CHANNEL_3:
-    {
-      /* Enable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
-    }
-    break;
-    
-    case TIM_CHANNEL_4:
-    {
-      /* Enable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
-    }
-    break;
-    
-    default:
-    break;
-  }  
-  /* Enable the Input Capture channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-    
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);  
-
-  /* Return function status */
-  return HAL_OK;  
-} 
-
-/**
-  * @brief  Stops the TIM Input Capture measurement in interrupt mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be disabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-  
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {       
-      /* Disable the TIM Capture/Compare 1 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-    }
-    break;
-    
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Capture/Compare 2 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-    }
-    break;
-    
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
-    }
-    break;
-    
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
-    }
-    break;
-    
-    default:
-    break; 
-  } 
-  
-  /* Disable the Input Capture channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 
-  
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim); 
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Input Capture measurement on in DMA mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  pData: The destination Buffer address.
-  * @param  Length: The length of data to be transferred from TIM peripheral to memory.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-  
-  if((htim->State == HAL_TIM_STATE_BUSY))
-  {
-     return HAL_BUSY;
-  }
-  else if((htim->State == HAL_TIM_STATE_READY))
-  {
-    if((pData == 0U) && (Length > 0U)) 
-    {
-      return HAL_ERROR;                                    
-    }
-    else
-    {
-      htim->State = HAL_TIM_STATE_BUSY;
-    }
-  }  
-   
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
-     
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); 
-      
-      /* Enable the TIM Capture/Compare 1 DMA request */      
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-    }
-    break;
-    
-    case TIM_CHANNEL_2:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
-     
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
-      
-      /* Enable the TIM Capture/Compare 2  DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-    }
-    break;
-    
-    case TIM_CHANNEL_3:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
-     
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
-      
-      /* Enable the TIM Capture/Compare 3  DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
-    }
-    break;
-    
-    case TIM_CHANNEL_4:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
-     
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
-      
-      /* Enable the TIM Capture/Compare 4  DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
-    }
-    break;
-    
-    default:
-    break;
-  }
-
-  /* Enable the Input Capture channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-   
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim); 
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Input Capture measurement on in DMA mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be disabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-  
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {       
-      /* Disable the TIM Capture/Compare 1 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-    }
-    break;
-    
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Capture/Compare 2 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
-    }
-    break;
-    
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Capture/Compare 3  DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
-    }
-    break;
-    
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 4  DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
-    }
-    break;
-    
-    default:
-    break;
-  }
-
-  /* Disable the Input Capture channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-  
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim); 
-  
-  /* Change the htim state */
-  htim->State = HAL_TIM_STATE_READY;
-  
-  /* Return function status */
-  return HAL_OK;
-}  
-/**
-  * @}
-  */
-  
-/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions 
- *  @brief    Time One Pulse functions 
- *
-@verbatim    
-  ==============================================================================
-                        ##### Time One Pulse functions #####
-  ==============================================================================
-  [..]  
-    This section provides functions allowing to:
-    (+) Initialize and configure the TIM One Pulse. 
-    (+) De-initialize the TIM One Pulse.
-    (+) Start the Time One Pulse.
-    (+) Stop the Time One Pulse.
-    (+) Start the Time One Pulse and enable interrupt.
-    (+) Stop the Time One Pulse and disable interrupt.
-    (+) Start the Time One Pulse and enable DMA transfer.
-    (+) Stop the Time One Pulse and disable DMA transfer.
- 
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIM One Pulse Time Base according to the specified
-  *         parameters in the TIM_HandleTypeDef and create the associated handle.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  OnePulseMode: Select the One pulse mode.
-  *         This parameter can be one of the following values:
-  *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
-  *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
-{
-  /* Check the TIM handle allocation */
-  if(htim == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-  assert_param(IS_TIM_OPM_MODE(OnePulseMode));
-  
-  if(htim->State == HAL_TIM_STATE_RESET)
-  { 
-    /* Allocate lock resource and initialize it */
-    htim->Lock = HAL_UNLOCKED;
-    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
-    HAL_TIM_OnePulse_MspInit(htim);
-  }
-  
-  /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;  
-  
-  /* Configure the Time base in the One Pulse Mode */
-  TIM_Base_SetConfig(htim->Instance, &htim->Init);
-  
-  /* Reset the OPM Bit */
-  htim->Instance->CR1 &= ~TIM_CR1_OPM;
-
-  /* Configure the OPM Mode */
-  htim->Instance->CR1 |= OnePulseMode;
-   
-  /* Initialize the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the TIM One Pulse  
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  
-  htim->State = HAL_TIM_STATE_BUSY;
-  
-  /* Disable the TIM Peripheral Clock */
-  __HAL_TIM_DISABLE(htim);
-  
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
-  HAL_TIM_OnePulse_MspDeInit(htim);
-    
-  /* Change TIM state */  
-  htim->State = HAL_TIM_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM One Pulse MSP.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_OnePulse_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes TIM One Pulse MSP.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Starts the TIM One Pulse signal generation.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  OutputChannel : TIM Channels to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
-  /* Enable the Capture compare and the Input Capture channels 
-    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
-    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
-    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output 
-    in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together 
-    
-    No need to enable the counter, it's enabled automatically by hardware 
-    (the counter starts in response to a stimulus and generate a pulse */
-  
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 
-  
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
-  {
-    /* Enable the main output */
-    __HAL_TIM_MOE_ENABLE(htim);
-  }
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM One Pulse signal generation.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  OutputChannel : TIM Channels to be disable.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
-  /* Disable the Capture compare and the Input Capture channels 
-  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
-  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
-  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output 
-  in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
-  
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 
-    
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
-  {
-    /* Disable the Main Output */
-    __HAL_TIM_MOE_DISABLE(htim);
-  }
-    
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim); 
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  OutputChannel : TIM Channels to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
-  /* Enable the Capture compare and the Input Capture channels 
-    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
-    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
-    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output 
-    in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together 
-    
-    No need to enable the counter, it's enabled automatically by hardware 
-    (the counter starts in response to a stimulus and generate a pulse */
- 
-  /* Enable the TIM Capture/Compare 1 interrupt */
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-  
-  /* Enable the TIM Capture/Compare 2 interrupt */
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-  
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 
-  
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
-  {
-    /* Enable the main output */
-    __HAL_TIM_MOE_ENABLE(htim);
-  }
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  OutputChannel : TIM Channels to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
-  /* Disable the TIM Capture/Compare 1 interrupt */
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);  
-  
-  /* Disable the TIM Capture/Compare 2 interrupt */
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-  
-  /* Disable the Capture compare and the Input Capture channels 
-  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
-  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
-  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output 
-  in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */  
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 
-    
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
-  {
-    /* Disable the Main Output */
-    __HAL_TIM_MOE_DISABLE(htim);
-  }
-    
-  /* Disable the Peripheral */
-   __HAL_TIM_DISABLE(htim);  
-  
-  /* Return function status */
-  return HAL_OK;
-}
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions 
- *  @brief    Time Encoder functions 
- *
-@verbatim    
-  ==============================================================================
-                          ##### Time Encoder functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Initialize and configure the TIM Encoder. 
-    (+) De-initialize the TIM Encoder.
-    (+) Start the Time Encoder.
-    (+) Stop the Time Encoder.
-    (+) Start the Time Encoder and enable interrupt.
-    (+) Stop the Time Encoder and disable interrupt.
-    (+) Start the Time Encoder and enable DMA transfer.
-    (+) Stop the Time Encoder and disable DMA transfer.
- 
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIM Encoder Interface and create the associated handle.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  sConfig: TIM Encoder Interface configuration structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef* sConfig)
-{
-  uint32_t tmpsmcr = 0U;
-  uint32_t tmpccmr1 = 0U;
-  uint32_t tmpccer = 0U;
-  
-  /* Check the TIM handle allocation */
-  if(htim == NULL)
-  {
-    return HAL_ERROR;
-  }
-   
-  /* Check the parameters */
-  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
-  assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
-  assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
-  assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
-  assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
-  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
-  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
-  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
-  assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
-
-  if(htim->State == HAL_TIM_STATE_RESET)
-  { 
-    /* Allocate lock resource and initialize it */
-    htim->Lock = HAL_UNLOCKED;
-    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
-    HAL_TIM_Encoder_MspInit(htim);
-  }
-  
-  /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;   
-    
-  /* Reset the SMS bits */
-  htim->Instance->SMCR &= ~TIM_SMCR_SMS;
-  
-  /* Configure the Time base in the Encoder Mode */
-  TIM_Base_SetConfig(htim->Instance, &htim->Init);  
-  
-  /* Get the TIMx SMCR register value */
-  tmpsmcr = htim->Instance->SMCR;
-
-  /* Get the TIMx CCMR1 register value */
-  tmpccmr1 = htim->Instance->CCMR1;
-
-  /* Get the TIMx CCER register value */
-  tmpccer = htim->Instance->CCER;
-
-  /* Set the encoder Mode */
-  tmpsmcr |= sConfig->EncoderMode;
-
-  /* Select the Capture Compare 1 and the Capture Compare 2 as input */
-  tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
-  tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
-  
-  /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
-  tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
-  tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
-  tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
-  tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
-
-  /* Set the TI1 and the TI2 Polarities */
-  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
-  tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
-  tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
-  
-  /* Write to TIMx SMCR */
-  htim->Instance->SMCR = tmpsmcr;
-
-  /* Write to TIMx CCMR1 */
-  htim->Instance->CCMR1 = tmpccmr1;
-
-  /* Write to TIMx CCER */
-  htim->Instance->CCER = tmpccer;
-  
-  /* Initialize the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the TIM Encoder interface  
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  
-  htim->State = HAL_TIM_STATE_BUSY;
-  
-  /* Disable the TIM Peripheral Clock */
-  __HAL_TIM_DISABLE(htim);
-  
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
-  HAL_TIM_Encoder_MspDeInit(htim);
-    
-  /* Change TIM state */  
-  htim->State = HAL_TIM_STATE_RESET;
- 
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM Encoder Interface MSP.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_Encoder_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes TIM Encoder Interface MSP.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Starts the TIM Encoder Interface.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-  
-  /* Enable the encoder interface channels */
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-      break; 
-    }
-    case TIM_CHANNEL_2:
-    { 
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 
-      break;
-    }  
-    default :
-    {
-     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-     break; 
-    }
-  }  
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Encoder Interface.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be disabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-    assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-    
-   /* Disable the Input Capture channels 1 and 2
-    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ 
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-      break; 
-    }
-    case TIM_CHANNEL_2:
-    { 
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 
-      break;
-    }  
-    default :
-    {
-     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-     break; 
-    }
-  }  
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Encoder Interface in interrupt mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-  
-  /* Enable the encoder interface channels */
-  /* Enable the capture compare Interrupts 1 and/or 2 */
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-      break; 
-    }
-    case TIM_CHANNEL_2:
-    { 
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); 
-      break;
-    }  
-    default :
-    {
-     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-     __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-     __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-     break; 
-    }
-  }
-  
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Encoder Interface in interrupt mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be disabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-    
-  /* Disable the Input Capture channels 1 and 2
-    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ 
-  if(Channel == TIM_CHANNEL_1)
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 
-    
-    /* Disable the capture compare Interrupts 1 */
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-  }  
-  else if(Channel == TIM_CHANNEL_2)
-  {  
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 
-    
-    /* Disable the capture compare Interrupts 2 */
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-  }  
-  else
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 
-    
-    /* Disable the capture compare Interrupts 1 and 2 */
-    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-  }
-    
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-  
-  /* Change the htim state */
-  htim->State = HAL_TIM_STATE_READY;
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Encoder Interface in DMA mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
-  * @param  pData1: The destination Buffer address for IC1.
-  * @param  pData2: The destination Buffer address for IC2.
-  * @param  Length: The length of data to be transferred from TIM peripheral to memory.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-  
-  if((htim->State == HAL_TIM_STATE_BUSY))
-  {
-     return HAL_BUSY;
-  }
-  else if((htim->State == HAL_TIM_STATE_READY))
-  {
-    if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0U)) 
-    {
-      return HAL_ERROR;                                    
-    }
-    else
-    {
-      htim->State = HAL_TIM_STATE_BUSY;
-    }
-  }  
-   
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
-     
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length); 
-      
-      /* Enable the TIM Input Capture DMA request */      
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-            
-      /* Enable the Peripheral */
-      __HAL_TIM_ENABLE(htim);
-      
-      /* Enable the Capture compare channel */
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-    }
-    break;
-    
-    case TIM_CHANNEL_2:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
-     
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
-      
-      /* Enable the TIM Input Capture  DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-     
-      /* Enable the Peripheral */
-      __HAL_TIM_ENABLE(htim);
-      
-      /* Enable the Capture compare channel */
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-    }
-    break;
-    
-    case TIM_CHANNEL_ALL:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
-     
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
-      
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
-     
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
-          
-     /* Enable the Peripheral */
-      __HAL_TIM_ENABLE(htim);
-      
-      /* Enable the Capture compare channel */
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-      
-      /* Enable the TIM Input Capture  DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-      /* Enable the TIM Input Capture  DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-    }
-    break;
-    
-    default:
-    break;
-  }  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Encoder Interface in DMA mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-  
-  /* Disable the Input Capture channels 1 and 2
-    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ 
-  if(Channel == TIM_CHANNEL_1)
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 
-    
-    /* Disable the capture compare DMA Request 1 */
-    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-  }  
-  else if(Channel == TIM_CHANNEL_2)
-  {  
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 
-    
-    /* Disable the capture compare DMA Request 2 */
-    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
-  }  
-  else
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 
-    
-    /* Disable the capture compare DMA Request 1 and 2 */
-    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
-  }
-  
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-  
-  /* Change the htim state */
-  htim->State = HAL_TIM_STATE_READY;
-  
-  /* Return function status */
-  return HAL_OK;
-}
-/**
-  * @}
-  */
-  
-/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management 
- *  @brief    IRQ handler management 
- *
-@verbatim   
-  ==============================================================================
-                        ##### IRQ handler management #####
-  ==============================================================================  
-  [..]  
-    This section provides Timer IRQ handler function.
-               
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  This function handles TIM interrupts requests.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
-{
-  /* Capture compare 1 event */
-  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
-  {
-    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
-    {
-      {
-        __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
-        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-        
-        /* Input capture event */
-        if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
-        {
-          HAL_TIM_IC_CaptureCallback(htim);
-        }
-        /* Output compare event */
-        else
-        {
-          HAL_TIM_OC_DelayElapsedCallback(htim);
-          HAL_TIM_PWM_PulseFinishedCallback(htim);
-        }
-        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-      }
-    }
-  }
-  /* Capture compare 2 event */
-  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
-  {
-    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
-    {
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-      /* Input capture event */
-      if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
-      {          
-        HAL_TIM_IC_CaptureCallback(htim);
-      }
-      /* Output compare event */
-      else
-      {
-        HAL_TIM_OC_DelayElapsedCallback(htim);
-        HAL_TIM_PWM_PulseFinishedCallback(htim);
-      }
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-    }
-  }
-  /* Capture compare 3 event */
-  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
-  {
-    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
-    {
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-      /* Input capture event */
-      if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
-      {          
-        HAL_TIM_IC_CaptureCallback(htim);
-      }
-      /* Output compare event */
-      else
-      {
-        HAL_TIM_OC_DelayElapsedCallback(htim);
-        HAL_TIM_PWM_PulseFinishedCallback(htim); 
-      }
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-    }
-  }
-  /* Capture compare 4 event */
-  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
-  {
-    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
-    {
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-      /* Input capture event */
-      if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
-      {          
-        HAL_TIM_IC_CaptureCallback(htim);
-      }
-      /* Output compare event */
-      else
-      {
-        HAL_TIM_OC_DelayElapsedCallback(htim);
-        HAL_TIM_PWM_PulseFinishedCallback(htim);
-      }
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-    }
-  }
-  /* TIM Update event */
-  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
-  {
-    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
-    {
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
-      HAL_TIM_PeriodElapsedCallback(htim);
-    }
-  }
-  /* TIM Break input event */
-  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
-  {
-    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
-    {
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
-      HAL_TIMEx_BreakCallback(htim);
-    }
-  }
-  /* TIM Trigger detection event */
-  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
-  {
-    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
-    {
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
-      HAL_TIM_TriggerCallback(htim);
-    }
-  }
-  /* TIM commutation event */
-  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
-  {
-    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
-    {
-      __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
-      HAL_TIMEx_CommutationCallback(htim);
-    }
-  }
-}
-/**
-  * @}
-  */
-  
-/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
- *  @brief   	Peripheral Control functions 
- *
-@verbatim   
-  ==============================================================================
-                   ##### Peripheral Control functions #####
-  ==============================================================================  
- [..] 
-   This section provides functions allowing to:
-   (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. 
-   (+) Configure External Clock source.
-   (+) Configure Complementary channels, break features and dead time.
-   (+) Configure Master and the Slave synchronization.
-   (+) Configure the DMA Burst Mode.
-      
-@endverbatim
-  * @{
-  */
-  
-/**
-  * @brief  Initializes the TIM Output Compare Channels according to the specified
-  *         parameters in the TIM_OC_InitTypeDef.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  sConfig: TIM Output Compare configuration structure
-  * @param  Channel: TIM Channels to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected 
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
-{
-  /* Check the parameters */ 
-  assert_param(IS_TIM_CHANNELS(Channel)); 
-  assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
-  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
-  
-  /* Check input state */
-  __HAL_LOCK(htim); 
-  
-  htim->State = HAL_TIM_STATE_BUSY;
-  
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-      /* Configure the TIM Channel 1 in Output Compare */
-      TIM_OC1_SetConfig(htim->Instance, sConfig);
-    }
-    break;
-    
-    case TIM_CHANNEL_2:
-    {
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-      /* Configure the TIM Channel 2 in Output Compare */
-      TIM_OC2_SetConfig(htim->Instance, sConfig);
-    }
-    break;
-    
-    case TIM_CHANNEL_3:
-    {
-       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-      /* Configure the TIM Channel 3 in Output Compare */
-      TIM_OC3_SetConfig(htim->Instance, sConfig);
-    }
-    break;
-    
-    case TIM_CHANNEL_4:
-    {
-      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-      /* Configure the TIM Channel 4 in Output Compare */
-      TIM_OC4_SetConfig(htim->Instance, sConfig);
-    }
-    break;
-    
-    default:
-    break;    
-  }
-  htim->State = HAL_TIM_STATE_READY;
-  
-  __HAL_UNLOCK(htim); 
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM Input Capture Channels according to the specified
-  *         parameters in the TIM_IC_InitTypeDef.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  sConfig: TIM Input Capture configuration structure
-  * @param  Channel: TIM Channels to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected 
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
-  assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
-  assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
-  assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
-  
-  __HAL_LOCK(htim);
-  
-  htim->State = HAL_TIM_STATE_BUSY;
-  
-  if (Channel == TIM_CHANNEL_1)
-  {
-    /* TI1 Configuration */
-    TIM_TI1_SetConfig(htim->Instance,
-               sConfig->ICPolarity,
-               sConfig->ICSelection,
-               sConfig->ICFilter);
-               
-    /* Reset the IC1PSC Bits */
-    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
-
-    /* Set the IC1PSC value */
-    htim->Instance->CCMR1 |= sConfig->ICPrescaler;
-  }
-  else if (Channel == TIM_CHANNEL_2)
-  {
-    /* TI2 Configuration */
-    assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-    
-    TIM_TI2_SetConfig(htim->Instance, 
-                      sConfig->ICPolarity,
-                      sConfig->ICSelection,
-                      sConfig->ICFilter);
-               
-    /* Reset the IC2PSC Bits */
-    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
-
-    /* Set the IC2PSC value */
-    htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
-  }
-  else if (Channel == TIM_CHANNEL_3)
-  {
-    /* TI3 Configuration */
-    assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-    
-    TIM_TI3_SetConfig(htim->Instance,  
-               sConfig->ICPolarity,
-               sConfig->ICSelection,
-               sConfig->ICFilter);
-               
-    /* Reset the IC3PSC Bits */
-    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
-
-    /* Set the IC3PSC value */
-    htim->Instance->CCMR2 |= sConfig->ICPrescaler;
-  }
-  else
-  {
-    /* TI4 Configuration */
-    assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-    
-    TIM_TI4_SetConfig(htim->Instance, 
-               sConfig->ICPolarity,
-               sConfig->ICSelection,
-               sConfig->ICFilter);
-               
-    /* Reset the IC4PSC Bits */
-    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
-
-    /* Set the IC4PSC value */
-    htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
-  }
-  
-  htim->State = HAL_TIM_STATE_READY;
-    
-  __HAL_UNLOCK(htim);
-  
-  return HAL_OK; 
-}
-
-/**
-  * @brief  Initializes the TIM PWM  channels according to the specified
-  *         parameters in the TIM_OC_InitTypeDef.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  sConfig: TIM PWM configuration structure
-  * @param  Channel: TIM Channels to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
-{
-  __HAL_LOCK(htim);
-  
-  /* Check the parameters */ 
-  assert_param(IS_TIM_CHANNELS(Channel)); 
-  assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
-  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
-  assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
-
-  htim->State = HAL_TIM_STATE_BUSY;
-    
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-      /* Configure the Channel 1 in PWM mode */
-      TIM_OC1_SetConfig(htim->Instance, sConfig);
-      
-      /* Set the Preload enable bit for channel1 */
-      htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
-      
-      /* Configure the Output Fast mode */
-      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
-      htim->Instance->CCMR1 |= sConfig->OCFastMode;
-    }
-    break;
-    
-    case TIM_CHANNEL_2:
-    {
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-      /* Configure the Channel 2 in PWM mode */
-      TIM_OC2_SetConfig(htim->Instance, sConfig);
-      
-      /* Set the Preload enable bit for channel2 */
-      htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
-      
-      /* Configure the Output Fast mode */
-      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
-      htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
-    }
-    break;
-    
-    case TIM_CHANNEL_3:
-    {
-      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-      /* Configure the Channel 3 in PWM mode */
-      TIM_OC3_SetConfig(htim->Instance, sConfig);
-      
-      /* Set the Preload enable bit for channel3 */
-      htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
-      
-     /* Configure the Output Fast mode */
-      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
-      htim->Instance->CCMR2 |= sConfig->OCFastMode;  
-    }
-    break;
-    
-    case TIM_CHANNEL_4:
-    {
-      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-      /* Configure the Channel 4 in PWM mode */
-      TIM_OC4_SetConfig(htim->Instance, sConfig);
-      
-      /* Set the Preload enable bit for channel4 */
-      htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
-      
-     /* Configure the Output Fast mode */
-      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
-      htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;  
-    }
-    break;
-    
-    default:
-    break;    
-  }
-  
-  htim->State = HAL_TIM_STATE_READY;
-    
-  __HAL_UNLOCK(htim);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM One Pulse Channels according to the specified
-  *         parameters in the TIM_OnePulse_InitTypeDef.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  sConfig: TIM One Pulse configuration structure
-  * @param  OutputChannel: TIM Channels to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @param  InputChannel: TIM Channels to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel,  uint32_t InputChannel)
-{
-  TIM_OC_InitTypeDef temp1;
-  
-  /* Check the parameters */
-  assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
-  assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
-
-  if(OutputChannel != InputChannel)  
-  {
-    __HAL_LOCK(htim);
-  
-    htim->State = HAL_TIM_STATE_BUSY;
-
-    /* Extract the Output compare configuration from sConfig structure */  
-    temp1.OCMode = sConfig->OCMode;
-    temp1.Pulse = sConfig->Pulse;
-    temp1.OCPolarity = sConfig->OCPolarity;
-    temp1.OCNPolarity = sConfig->OCNPolarity;
-    temp1.OCIdleState = sConfig->OCIdleState;
-    temp1.OCNIdleState = sConfig->OCNIdleState; 
-    
-    switch (OutputChannel)
-    {
-      case TIM_CHANNEL_1:
-      {
-        assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-      
-        TIM_OC1_SetConfig(htim->Instance, &temp1); 
-      }
-      break;
-      case TIM_CHANNEL_2:
-      {
-        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-      
-        TIM_OC2_SetConfig(htim->Instance, &temp1);
-      }
-      break;
-      default:
-      break;  
-    } 
-    switch (InputChannel)
-    {
-      case TIM_CHANNEL_1:
-      {
-        assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-      
-        TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
-                        sConfig->ICSelection, sConfig->ICFilter);
-               
-        /* Reset the IC1PSC Bits */
-        htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
-
-        /* Select the Trigger source */
-        htim->Instance->SMCR &= ~TIM_SMCR_TS;
-        htim->Instance->SMCR |= TIM_TS_TI1FP1;
-      
-        /* Select the Slave Mode */      
-        htim->Instance->SMCR &= ~TIM_SMCR_SMS;
-        htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
-      }
-      break;
-      case TIM_CHANNEL_2:
-      {
-        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-      
-        TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
-                 sConfig->ICSelection, sConfig->ICFilter);
-               
-        /* Reset the IC2PSC Bits */
-        htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
-
-        /* Select the Trigger source */
-        htim->Instance->SMCR &= ~TIM_SMCR_TS;
-        htim->Instance->SMCR |= TIM_TS_TI2FP2;
-      
-        /* Select the Slave Mode */      
-        htim->Instance->SMCR &= ~TIM_SMCR_SMS;
-        htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
-      }
-      break;
-    
-      default:
-      break;  
-    }
-  
-    htim->State = HAL_TIM_STATE_READY;
-    
-    __HAL_UNLOCK(htim);
-  
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-} 
-
-/**
-  * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral  
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  BurstBaseAddress: TIM Base address from when the DMA will starts the Data write.
-  *         This parameters can be on of the following values:
-  *            @arg TIM_DMABASE_CR1  
-  *            @arg TIM_DMABASE_CR2
-  *            @arg TIM_DMABASE_SMCR
-  *            @arg TIM_DMABASE_DIER
-  *            @arg TIM_DMABASE_SR
-  *            @arg TIM_DMABASE_EGR
-  *            @arg TIM_DMABASE_CCMR1
-  *            @arg TIM_DMABASE_CCMR2
-  *            @arg TIM_DMABASE_CCER
-  *            @arg TIM_DMABASE_CNT   
-  *            @arg TIM_DMABASE_PSC   
-  *            @arg TIM_DMABASE_ARR
-  *            @arg TIM_DMABASE_RCR
-  *            @arg TIM_DMABASE_CCR1
-  *            @arg TIM_DMABASE_CCR2
-  *            @arg TIM_DMABASE_CCR3  
-  *            @arg TIM_DMABASE_CCR4
-  *            @arg TIM_DMABASE_BDTR
-  *            @arg TIM_DMABASE_DCR
-  * @param  BurstRequestSrc: TIM DMA Request sources.
-  *         This parameters can be on of the following values:
-  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
-  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
-  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
-  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
-  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
-  *            @arg TIM_DMA_COM: TIM Commutation DMA source
-  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
-  * @param  BurstBuffer: The Buffer address.
-  * @param  BurstLength: DMA Burst length. This parameter can be one value
-  *         between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
-                                              uint32_t* BurstBuffer, uint32_t  BurstLength)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
-  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
-  assert_param(IS_TIM_DMA_LENGTH(BurstLength));
-  
-  if((htim->State == HAL_TIM_STATE_BUSY))
-  {
-     return HAL_BUSY;
-  }
-  else if((htim->State == HAL_TIM_STATE_READY))
-  {
-    if((BurstBuffer == 0U) && (BurstLength > 0U)) 
-    {
-      return HAL_ERROR;                                    
-    }
-    else
-    {
-      htim->State = HAL_TIM_STATE_BUSY;
-    }
-  }
-  switch(BurstRequestSrc)
-  {
-    case TIM_DMA_UPDATE:
-    {  
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
-     
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
-  
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U); 
-    }
-    break;
-    case TIM_DMA_CC1:
-    {  
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
-     
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-  
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);     
-    }
-    break;
-    case TIM_DMA_CC2:
-    {  
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
-     
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-  
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);     
-    }
-    break;
-    case TIM_DMA_CC3:
-    {  
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
-     
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-  
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);     
-    }
-    break;
-    case TIM_DMA_CC4:
-    {  
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
-     
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-  
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);     
-    }
-    break;
-    case TIM_DMA_COM:
-    {  
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
-     
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
-  
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);     
-    }
-    break;
-    case TIM_DMA_TRIGGER:
-    {  
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
-     
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
-  
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);     
-    }
-    break;
-    default:
-    break;  
-  }
-   /* configure the DMA Burst Mode */
-   htim->Instance->DCR = BurstBaseAddress | BurstLength;  
-   
-   /* Enable the TIM DMA Request */
-   __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);  
-   
-   htim->State = HAL_TIM_STATE_READY;
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM DMA Burst mode 
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  BurstRequestSrc: TIM DMA Request sources to disable
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
-  
-  /* Abort the DMA transfer (at least disable the DMA channel) */
-  switch(BurstRequestSrc)
-  {
-    case TIM_DMA_UPDATE:
-    {  
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
-    }
-    break;
-    case TIM_DMA_CC1:
-    {  
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
-    }
-    break;
-    case TIM_DMA_CC2:
-    {  
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
-    }
-    break;
-    case TIM_DMA_CC3:
-    {  
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
-    }
-    break;
-    case TIM_DMA_CC4:
-    {  
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
-    }
-    break;
-    case TIM_DMA_COM:
-    {  
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
-    }
-    break;
-    case TIM_DMA_TRIGGER:
-    {  
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
-    }
-    break;
-    default:
-    break;
-  }
-
-  /* Disable the TIM Update DMA request */
-  __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
-      
-  /* Return function status */
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory 
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  BurstBaseAddress: TIM Base address from when the DMA will starts the Data read.
-  *         This parameters can be on of the following values:
-  *            @arg TIM_DMABASE_CR1  
-  *            @arg TIM_DMABASE_CR2
-  *            @arg TIM_DMABASE_SMCR
-  *            @arg TIM_DMABASE_DIER
-  *            @arg TIM_DMABASE_SR
-  *            @arg TIM_DMABASE_EGR
-  *            @arg TIM_DMABASE_CCMR1
-  *            @arg TIM_DMABASE_CCMR2
-  *            @arg TIM_DMABASE_CCER
-  *            @arg TIM_DMABASE_CNT   
-  *            @arg TIM_DMABASE_PSC   
-  *            @arg TIM_DMABASE_ARR
-  *            @arg TIM_DMABASE_RCR
-  *            @arg TIM_DMABASE_CCR1
-  *            @arg TIM_DMABASE_CCR2
-  *            @arg TIM_DMABASE_CCR3  
-  *            @arg TIM_DMABASE_CCR4
-  *            @arg TIM_DMABASE_BDTR
-  *            @arg TIM_DMABASE_DCR
-  * @param  BurstRequestSrc: TIM DMA Request sources.
-  *         This parameters can be on of the following values:
-  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
-  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
-  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
-  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
-  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
-  *            @arg TIM_DMA_COM: TIM Commutation DMA source
-  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
-  * @param  BurstBuffer: The Buffer address.
-  * @param  BurstLength: DMA Burst length. This parameter can be one value
-  *         between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
-                                             uint32_t  *BurstBuffer, uint32_t  BurstLength)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
-  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
-  assert_param(IS_TIM_DMA_LENGTH(BurstLength));
-  
-  if((htim->State == HAL_TIM_STATE_BUSY))
-  {
-     return HAL_BUSY;
-  }
-  else if((htim->State == HAL_TIM_STATE_READY))
-  {
-    if((BurstBuffer == 0U) && (BurstLength > 0U)) 
-    {
-      return HAL_ERROR;                                    
-    }
-    else
-    {
-      htim->State = HAL_TIM_STATE_BUSY;
-    }
-  }  
-  switch(BurstRequestSrc)
-  {
-    case TIM_DMA_UPDATE:
-    {  
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
-     
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
-  
-      /* Enable the DMA Stream */
-       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);     
-    }
-    break;
-    case TIM_DMA_CC1:
-    {  
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
-     
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-  
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);      
-    }
-    break;
-    case TIM_DMA_CC2:
-    {  
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
-     
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-  
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);     
-    }
-    break;
-    case TIM_DMA_CC3:
-    {  
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
-     
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-  
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);      
-    }
-    break;
-    case TIM_DMA_CC4:
-    {  
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
-     
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-  
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);      
-    }
-    break;
-    case TIM_DMA_COM:
-    {  
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
-     
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
-  
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);      
-    }
-    break;
-    case TIM_DMA_TRIGGER:
-    {  
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
-     
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
-  
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1);      
-    }
-    break;
-    default:
-    break;  
-  }
-
-  /* configure the DMA Burst Mode */
-  htim->Instance->DCR = BurstBaseAddress | BurstLength;  
-  
-  /* Enable the TIM DMA Request */
-  __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
-  
-  htim->State = HAL_TIM_STATE_READY;
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stop the DMA burst reading 
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  BurstRequestSrc: TIM DMA Request sources to disable.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
-  
-  /* Abort the DMA transfer (at least disable the DMA channel) */
-  switch(BurstRequestSrc)
-  {
-    case TIM_DMA_UPDATE:
-    {  
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
-    }
-    break;
-    case TIM_DMA_CC1:
-    {  
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
-    }
-    break;
-    case TIM_DMA_CC2:
-    {  
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
-    }
-    break;
-    case TIM_DMA_CC3:
-    {  
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
-    }
-    break;
-    case TIM_DMA_CC4:
-    {  
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
-    }
-    break;
-    case TIM_DMA_COM:
-    {  
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
-    }
-    break;
-    case TIM_DMA_TRIGGER:
-    {  
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
-    }
-    break;
-    default:
-    break;  
-  }
-  
-  /* Disable the TIM Update DMA request */
-  __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
-      
-  /* Return function status */
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Generate a software event
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  EventSource: specifies the event source.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
-  *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
-  *            @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
-  *            @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
-  *            @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
-  *            @arg TIM_EVENTSOURCE_COM: Timer COM event source  
-  *            @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
-  *            @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
-  * @note   TIM6 and TIM7 can only generate an update event. 
-  * @note   TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1 and TIM8.
-  * @retval HAL status
-  */ 
-
-HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_EVENT_SOURCE(EventSource));
-  
-  /* Process Locked */
-  __HAL_LOCK(htim);
-  
-  /* Change the TIM state */
-  htim->State = HAL_TIM_STATE_BUSY;
-  
-  /* Set the event sources */
-  htim->Instance->EGR = EventSource;
-  
-  /* Change the TIM state */
-  htim->State = HAL_TIM_STATE_READY;
-  
-  __HAL_UNLOCK(htim);
-  
-  /* Return function status */
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Configures the OCRef clear feature
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
-  *         contains the OCREF clear feature and parameters for the TIM peripheral. 
-  * @param  Channel: specifies the TIM Channel.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */ 
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
-{ 
-  /* Check the parameters */
-  assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_CHANNELS(Channel));
-  assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
-  assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
-  assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
-  assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
-   
-  /* Process Locked */
-  __HAL_LOCK(htim);
-  
-  htim->State = HAL_TIM_STATE_BUSY;
-  
-  if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
-  {
-    TIM_ETR_SetConfig(htim->Instance, 
-                      sClearInputConfig->ClearInputPrescaler,
-                      sClearInputConfig->ClearInputPolarity,
-                      sClearInputConfig->ClearInputFilter);
-  }
-  
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {        
-      if(sClearInputConfig->ClearInputState != RESET)  
-      {
-        /* Enable the Ocref clear feature for Channel 1 */
-        htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
-      }
-      else
-      {
-        /* Disable the Ocref clear feature for Channel 1 */
-        htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;      
-      }
-    }    
-    break;
-    case TIM_CHANNEL_2:    
-    { 
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 
-      if(sClearInputConfig->ClearInputState != RESET)  
-      {
-        /* Enable the Ocref clear feature for Channel 2 */
-        htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
-      }
-      else
-      {
-        /* Disable the Ocref clear feature for Channel 2 */
-        htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;      
-      }
-    } 
-    break;
-    case TIM_CHANNEL_3:   
-    {  
-      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-      if(sClearInputConfig->ClearInputState != RESET)  
-      {
-        /* Enable the Ocref clear feature for Channel 3 */
-        htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
-      }
-      else
-      {
-        /* Disable the Ocref clear feature for Channel 3 */
-        htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;      
-      }
-    } 
-    break;
-    case TIM_CHANNEL_4:    
-    {  
-      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-      if(sClearInputConfig->ClearInputState != RESET)  
-      {
-        /* Enable the Ocref clear feature for Channel 4 */
-        htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
-      }
-      else
-      {
-        /* Disable the Ocref clear feature for Channel 4 */
-        htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;      
-      }
-    } 
-    break;
-    default:  
-    break;
-  } 
-
-  htim->State = HAL_TIM_STATE_READY;
-  
-  __HAL_UNLOCK(htim);
-  
-  return HAL_OK;  
-}  
-
-/**
-  * @brief   Configures the clock source to be used
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
-  *         contains the clock source information for the TIM peripheral. 
-  * @retval HAL status
-  */ 
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)    
-{
-  uint32_t tmpsmcr = 0U;
-    
-  /* Process Locked */
-  __HAL_LOCK(htim);
-  
-  htim->State = HAL_TIM_STATE_BUSY;
-  
-  /* Check the parameters */
-  assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
-  
-  /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
-  tmpsmcr = htim->Instance->SMCR;
-  tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
-  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
-  htim->Instance->SMCR = tmpsmcr;
-  
-  switch (sClockSourceConfig->ClockSource)
-  {
-    case TIM_CLOCKSOURCE_INTERNAL:
-    { 
-      assert_param(IS_TIM_INSTANCE(htim->Instance));
-      
-      /* Disable slave mode to clock the prescaler directly with the internal clock */
-      htim->Instance->SMCR &= ~TIM_SMCR_SMS;
-    }
-    break;
-    
-    case TIM_CLOCKSOURCE_ETRMODE1:
-    {
-      assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
-
-      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
-      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
-      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
-      /* Configure the ETR Clock source */
-      TIM_ETR_SetConfig(htim->Instance, 
-                        sClockSourceConfig->ClockPrescaler, 
-                        sClockSourceConfig->ClockPolarity, 
-                        sClockSourceConfig->ClockFilter);
-      /* Get the TIMx SMCR register value */
-      tmpsmcr = htim->Instance->SMCR;
-      /* Reset the SMS and TS Bits */
-      tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
-      /* Select the External clock mode1 and the ETRF trigger */
-      tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
-      /* Write to TIMx SMCR */
-      htim->Instance->SMCR = tmpsmcr;
-    }
-    break;
-    
-    case TIM_CLOCKSOURCE_ETRMODE2:
-    {
-      assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
-
-      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
-      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
-      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
-      /* Configure the ETR Clock source */
-      TIM_ETR_SetConfig(htim->Instance, 
-                        sClockSourceConfig->ClockPrescaler, 
-                        sClockSourceConfig->ClockPolarity,
-                        sClockSourceConfig->ClockFilter);
-      /* Enable the External clock mode2 */
-      htim->Instance->SMCR |= TIM_SMCR_ECE;
-    }
-    break;
-    
-    case TIM_CLOCKSOURCE_TI1:
-    {
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
-      /* Check TI1 input conditioning related parameters */
-      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
-      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
-      TIM_TI1_ConfigInputStage(htim->Instance, 
-                        sClockSourceConfig->ClockPolarity, 
-                        sClockSourceConfig->ClockFilter);
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
-    }
-    break;
-    case TIM_CLOCKSOURCE_TI2:
-    {
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-      /* Check TI1 input conditioning related parameters */
-      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
-      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
-      TIM_TI2_ConfigInputStage(htim->Instance, 
-                        sClockSourceConfig->ClockPolarity, 
-                        sClockSourceConfig->ClockFilter);
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
-    }
-    break;
-    case TIM_CLOCKSOURCE_TI1ED:
-    {
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
-      /* Check TI1 input conditioning related parameters */
-      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
-      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
-      TIM_TI1_ConfigInputStage(htim->Instance, 
-                        sClockSourceConfig->ClockPolarity,
-                        sClockSourceConfig->ClockFilter);
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
-    }
-    break;
-    case TIM_CLOCKSOURCE_ITR0:
-    {
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
-    }
-    break;
-    case TIM_CLOCKSOURCE_ITR1:
-    {
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
-    }
-    break;
-    case TIM_CLOCKSOURCE_ITR2:
-    {
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
-    }
-    break;
-    case TIM_CLOCKSOURCE_ITR3:
-    {
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
-    }
-    break;
-    
-    default:
-    break;    
-  }
-  htim->State = HAL_TIM_STATE_READY;
-  
-  __HAL_UNLOCK(htim);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
-  *         or a XOR combination between CH1_input, CH2_input & CH3_input
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  TI1_Selection: Indicate whether or not channel 1 is connected to the
-  *         output of a XOR gate.
-  *         This parameter can be one of the following values:
-  *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
-  *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
-  *            pins are connected to the TI1 input (XOR combination)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
-{
-  uint32_t tmpcr2 = 0U;
-  
-  /* Check the parameters */
-  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); 
-  assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
-
-  /* Get the TIMx CR2 register value */
-  tmpcr2 = htim->Instance->CR2;
-
-  /* Reset the TI1 selection */
-  tmpcr2 &= ~TIM_CR2_TI1S;
-
-  /* Set the TI1 selection */
-  tmpcr2 |= TI1_Selection;
-  
-  /* Write to TIMxCR2 */
-  htim->Instance->CR2 = tmpcr2;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the TIM in Slave mode
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
-  *         contains the selected trigger (internal trigger input, filtered
-  *         timer input or external trigger input) and the ) and the Slave 
-  *         mode (Disable, Reset, Gated, Trigger, External clock mode 1). 
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
-  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
-   
-  __HAL_LOCK(htim);
-  
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
-  
-  /* Disable Trigger Interrupt */
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
-  
-  /* Disable Trigger DMA request */
-  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
-  
-  htim->State = HAL_TIM_STATE_READY;
-     
-  __HAL_UNLOCK(htim);  
-  
-  return HAL_OK;
-} 
-
-/**
-  * @brief  Configures the TIM in Slave mode in interrupt mode
-  * @param  htim: TIM handle.
-  * @param  sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
-  *         contains the selected trigger (internal trigger input, filtered
-  *         timer input or external trigger input) and the ) and the Slave 
-  *         mode (Disable, Reset, Gated, Trigger, External clock mode 1). 
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, 
-                                                        TIM_SlaveConfigTypeDef * sSlaveConfig)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
-  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
-  
-  __HAL_LOCK(htim);
-
-  htim->State = HAL_TIM_STATE_BUSY;
-  
-  TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
-  
-  /* Enable Trigger Interrupt */
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
-  
-  /* Disable Trigger DMA request */
-  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
-  
-  htim->State = HAL_TIM_STATE_READY;
-     
-  __HAL_UNLOCK(htim);  
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Read the captured value from Capture Compare unit
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval Captured value
-  */
-uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  uint32_t tmpreg = 0U;
-  
-  __HAL_LOCK(htim);
-  
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-      
-      /* Return the capture 1 value */
-      tmpreg = htim->Instance->CCR1;
-      
-      break;
-    }
-    case TIM_CHANNEL_2:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-      
-      /* Return the capture 2 value */
-      tmpreg = htim->Instance->CCR2;
-      
-      break;
-    }
-    
-    case TIM_CHANNEL_3:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-      
-      /* Return the capture 3 value */
-      tmpreg = htim->Instance->CCR3;
-      
-      break;
-    }
-    
-    case TIM_CHANNEL_4:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-      
-      /* Return the capture 4 value */
-      tmpreg = htim->Instance->CCR4;
-      
-      break;
-    }
-    
-    default:
-    break;  
-  }
-     
-  __HAL_UNLOCK(htim);  
-  return tmpreg;
-}
-/**
-  * @}
-  */
-  
-/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
- *  @brief    TIM Callbacks functions 
- *
-@verbatim   
-  ==============================================================================
-                        ##### TIM Callbacks functions #####
-  ==============================================================================  
- [..]  
-   This section provides TIM callback functions:
-   (+) Timer Period elapsed callback
-   (+) Timer Output Compare callback
-   (+) Timer Input capture callback
-   (+) Timer Trigger callback
-   (+) Timer Error callback
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Period elapsed callback in non blocking mode 
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Output Compare callback in non blocking mode 
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Input Capture callback in non blocking mode 
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  PWM Pulse finished callback in non blocking mode 
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Hall Trigger detection callback in non blocking mode 
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_TriggerCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Timer error callback in non blocking mode 
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_ErrorCallback could be implemented in the user file
-   */
-}
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions 
- *  @brief   Peripheral State functions 
- *
-@verbatim   
-  ==============================================================================
-                        ##### Peripheral State functions #####
-  ==============================================================================  
-  [..]
-    This subsection permits to get in run-time the status of the peripheral 
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the TIM Base state
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL state
-  */
-HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
-{
-  return htim->State;
-}
-
-/**
-  * @brief  Return the TIM OC state
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL state
-  */
-HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
-{
-  return htim->State;
-}
-
-/**
-  * @brief  Return the TIM PWM state
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL state
-  */
-HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
-{
-  return htim->State;
-}
-
-/**
-  * @brief  Return the TIM Input Capture state
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL state
-  */
-HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
-{
-  return htim->State;
-}
-
-/**
-  * @brief  Return the TIM One Pulse Mode state
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL state
-  */
-HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
-{
-  return htim->State;
-}
-
-/**
-  * @brief  Return the TIM Encoder Mode state
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL state
-  */
-HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
-{
-  return htim->State;
-}
-/**
-  * @}
-  */
-
-/**
-  * @brief  Time Base configuration
-  * @param  TIMx: TIM peripheral
-  * @param  Structure: pointer on TIM Time Base required parameters  
-  * @retval None
-  */
-void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
-{
-  uint32_t tmpcr1 = 0U;
-  tmpcr1 = TIMx->CR1;
-  
-  /* Set TIM Time Base Unit parameters ---------------------------------------*/
-  if(IS_TIM_CC3_INSTANCE(TIMx) != RESET)   
-  {
-    /* Select the Counter Mode */
-    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
-    tmpcr1 |= Structure->CounterMode;
-  }
- 
-  if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)  
-  {
-    /* Set the clock division */
-    tmpcr1 &= ~TIM_CR1_CKD;
-    tmpcr1 |= (uint32_t)Structure->ClockDivision;
-  }
-
-  TIMx->CR1 = tmpcr1;
-
-  /* Set the Auto-reload value */
-  TIMx->ARR = (uint32_t)Structure->Period ;
- 
-  /* Set the Prescaler value */
-  TIMx->PSC = (uint32_t)Structure->Prescaler;
-    
-  if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)  
-  {
-    /* Set the Repetition Counter value */
-    TIMx->RCR = Structure->RepetitionCounter;
-  }
-
-  /* Generate an update event to reload the Prescaler 
-     and the repetition counter(only for TIM1 and TIM8) value immediately */
-  TIMx->EGR = TIM_EGR_UG;
-}
-
-/**
-  * @brief  Configure the TI1 as Input.
-  * @param  TIMx to select the TIM peripheral.
-  * @param  TIM_ICPolarity : The Input Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPolarity_Rising
-  *            @arg TIM_ICPolarity_Falling
-  *            @arg TIM_ICPolarity_BothEdge  
-  * @param  TIM_ICSelection: specifies the input to be used.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
-  *            @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
-  *            @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
-  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
-  *          This parameter must be a value between 0x00 and 0x0F.
-  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 
-  *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be 
-  *        protected against un-initialized filter and polarity values.
-  * @retval None
-  */
-void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                       uint32_t TIM_ICFilter)
-{
-  uint32_t tmpccmr1 = 0U;
-  uint32_t tmpccer = 0U;
-  
-  /* Disable the Channel 1: Reset the CC1E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC1E;
-  tmpccmr1 = TIMx->CCMR1;
-  tmpccer = TIMx->CCER;
-
-  /* Select the Input */
-  if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
-  {
-    tmpccmr1 &= ~TIM_CCMR1_CC1S;
-    tmpccmr1 |= TIM_ICSelection;
-  } 
-  else
-  {
-    tmpccmr1 &= ~TIM_CCMR1_CC1S;
-    tmpccmr1 |= TIM_CCMR1_CC1S_0;
-  }
-
-  /* Set the filter */
-  tmpccmr1 &= ~TIM_CCMR1_IC1F;
-  tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
-
-  /* Select the Polarity and set the CC1E Bit */
-  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
-  tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
-
-  /* Write to TIMx CCMR1 and CCER registers */
-  TIMx->CCMR1 = tmpccmr1;
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Time Output Compare 2 configuration
-  * @param  TIMx to select the TIM peripheral
-  * @param  OC_Config: The output configuration structure
-  * @retval None
-  */
-void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
-  uint32_t tmpccmrx = 0U;
-  uint32_t tmpccer = 0U;
-  uint32_t tmpcr2 = 0U;
-   
-  /* Disable the Channel 2: Reset the CC2E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC2E;
-  
-  /* Get the TIMx CCER register value */  
-  tmpccer = TIMx->CCER;
-  /* Get the TIMx CR2 register value */
-  tmpcr2 = TIMx->CR2;
-  
-  /* Get the TIMx CCMR1 register value */
-  tmpccmrx = TIMx->CCMR1;
-    
-  /* Reset the Output Compare mode and Capture/Compare selection Bits */
-  tmpccmrx &= ~TIM_CCMR1_OC2M;
-  tmpccmrx &= ~TIM_CCMR1_CC2S;
-  
-  /* Select the Output Compare Mode */
-  tmpccmrx |= (OC_Config->OCMode << 8U);
-  
-  /* Reset the Output Polarity level */
-  tmpccer &= ~TIM_CCER_CC2P;
-  /* Set the Output Compare Polarity */
-  tmpccer |= (OC_Config->OCPolarity << 4U);
-    
-  if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
-  {
-    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-    
-    /* Reset the Output N Polarity level */
-    tmpccer &= ~TIM_CCER_CC2NP;
-    /* Set the Output N Polarity */
-    tmpccer |= (OC_Config->OCNPolarity << 4U);
-    /* Reset the Output N State */
-    tmpccer &= ~TIM_CCER_CC2NE;
-    
-    /* Reset the Output Compare and Output Compare N IDLE State */
-    tmpcr2 &= ~TIM_CR2_OIS2;
-    tmpcr2 &= ~TIM_CR2_OIS2N;
-    /* Set the Output Idle state */
-    tmpcr2 |= (OC_Config->OCIdleState << 2U);
-    /* Set the Output N Idle state */
-    tmpcr2 |= (OC_Config->OCNIdleState << 2U);
-  }
-  /* Write to TIMx CR2 */
-  TIMx->CR2 = tmpcr2;
-  
-  /* Write to TIMx CCMR1 */
-  TIMx->CCMR1 = tmpccmrx;
-  
-  /* Set the Capture Compare Register value */
-  TIMx->CCR2 = OC_Config->Pulse;
-  
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  TIM DMA Delay Pulse complete callback. 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  htim->State= HAL_TIM_STATE_READY; 
-  
-  if(hdma == htim->hdma[TIM_DMA_ID_CC1])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-  }
-  else if(hdma == htim->hdma[TIM_DMA_ID_CC2])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-  }
-  else if(hdma == htim->hdma[TIM_DMA_ID_CC3])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-  }
-  else if(hdma == htim->hdma[TIM_DMA_ID_CC4])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-  }
-
-  HAL_TIM_PWM_PulseFinishedCallback(htim);
-
-  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;  
-}
-
-/**
-  * @brief  TIM DMA error callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-void TIM_DMAError(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  htim->State= HAL_TIM_STATE_READY;
-   
-  HAL_TIM_ErrorCallback(htim);
-}
-
-/**
-  * @brief  TIM DMA Capture complete callback. 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  htim->State= HAL_TIM_STATE_READY;
-  
-  if(hdma == htim->hdma[TIM_DMA_ID_CC1])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-  }
-  else if(hdma == htim->hdma[TIM_DMA_ID_CC2])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-  }
-  else if(hdma == htim->hdma[TIM_DMA_ID_CC3])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-  }
-  else if(hdma == htim->hdma[TIM_DMA_ID_CC4])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-  }
-  
-  HAL_TIM_IC_CaptureCallback(htim); 
-  
-  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-
-/**
-  * @brief  Enables or disables the TIM Capture Compare Channel x.
-  * @param  TIMx to select the TIM peripheral
-  * @param  Channel: specifies the TIM Channel
-  *          This parameter can be one of the following values:
-  *            @arg TIM_Channel_1: TIM Channel 1
-  *            @arg TIM_Channel_2: TIM Channel 2
-  *            @arg TIM_Channel_3: TIM Channel 3
-  *            @arg TIM_Channel_4: TIM Channel 4
-  * @param  ChannelState: specifies the TIM Channel CCxE bit new state.
-  *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable. 
-  * @retval None
-  */
-void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
-{
-  uint32_t tmp = 0U;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CC1_INSTANCE(TIMx)); 
-  assert_param(IS_TIM_CHANNELS(Channel));
-
-  tmp = TIM_CCER_CC1E << Channel;
-
-  /* Reset the CCxE Bit */
-  TIMx->CCER &= ~tmp;
-
-  /* Set or reset the CCxE Bit */ 
-  TIMx->CCER |= (uint32_t)(ChannelState << Channel);
-}
-
-/**
-  * @brief  TIM DMA Period Elapse complete callback. 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  htim->State= HAL_TIM_STATE_READY;
-  
-  HAL_TIM_PeriodElapsedCallback(htim);
-}
-
-/**
-  * @brief  TIM DMA Trigger callback. 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;  
-  
-  htim->State= HAL_TIM_STATE_READY; 
-  
-  HAL_TIM_TriggerCallback(htim);
-}
-
-/**
-  * @brief  Time Output Compare 1 configuration
-  * @param  TIMx to select the TIM peripheral
-  * @param  OC_Config: The output configuration structure
-  * @retval None
-  */
-static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
-  uint32_t tmpccmrx = 0U;
-  uint32_t tmpccer = 0U;
-  uint32_t tmpcr2 = 0U;  
-
-  /* Disable the Channel 1: Reset the CC1E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC1E;
-  
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
-  /* Get the TIMx CR2 register value */
-  tmpcr2 = TIMx->CR2;
-  
-  /* Get the TIMx CCMR1 register value */
-  tmpccmrx = TIMx->CCMR1;
-    
-  /* Reset the Output Compare Mode Bits */
-  tmpccmrx &= ~TIM_CCMR1_OC1M;
-  tmpccmrx &= ~TIM_CCMR1_CC1S;
-  /* Select the Output Compare Mode */
-  tmpccmrx |= OC_Config->OCMode;
-  
-  /* Reset the Output Polarity level */
-  tmpccer &= ~TIM_CCER_CC1P;
-  /* Set the Output Compare Polarity */
-  tmpccer |= OC_Config->OCPolarity;
-
-    
-  if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
-  {   
-    /* Reset the Output N Polarity level */
-    tmpccer &= ~TIM_CCER_CC1NP;
-    /* Set the Output N Polarity */
-    tmpccer |= OC_Config->OCNPolarity;
-    /* Reset the Output N State */
-    tmpccer &= ~TIM_CCER_CC1NE;
-    
-    /* Reset the Output Compare and Output Compare N IDLE State */
-    tmpcr2 &= ~TIM_CR2_OIS1;
-    tmpcr2 &= ~TIM_CR2_OIS1N;
-    /* Set the Output Idle state */
-    tmpcr2 |= OC_Config->OCIdleState;
-    /* Set the Output N Idle state */
-    tmpcr2 |= OC_Config->OCNIdleState;
-  }
-  /* Write to TIMx CR2 */
-  TIMx->CR2 = tmpcr2;
-  
-  /* Write to TIMx CCMR1 */
-  TIMx->CCMR1 = tmpccmrx;
-  
-  /* Set the Capture Compare Register value */
-  TIMx->CCR1 = OC_Config->Pulse;
-  
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;  
-} 
-
-/**
-  * @brief  Time Output Compare 3 configuration
-  * @param  TIMx to select the TIM peripheral
-  * @param  OC_Config: The output configuration structure
-  * @retval None
-  */
-static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
-  uint32_t tmpccmrx = 0U;
-  uint32_t tmpccer = 0U;
-  uint32_t tmpcr2 = 0U;   
-
-  /* Disable the Channel 3: Reset the CC2E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC3E;
-  
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
-  /* Get the TIMx CR2 register value */
-  tmpcr2 = TIMx->CR2;
-  
-  /* Get the TIMx CCMR2 register value */
-  tmpccmrx = TIMx->CCMR2;
-    
-  /* Reset the Output Compare mode and Capture/Compare selection Bits */
-  tmpccmrx &= ~TIM_CCMR2_OC3M;
-  tmpccmrx &= ~TIM_CCMR2_CC3S;  
-  /* Select the Output Compare Mode */
-  tmpccmrx |= OC_Config->OCMode;
-  
-  /* Reset the Output Polarity level */
-  tmpccer &= ~TIM_CCER_CC3P;
-  /* Set the Output Compare Polarity */
-  tmpccer |= (OC_Config->OCPolarity << 8U);
-    
-  if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
-  {
-    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
-    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-    
-    /* Reset the Output N Polarity level */
-    tmpccer &= ~TIM_CCER_CC3NP;
-    /* Set the Output N Polarity */
-    tmpccer |= (OC_Config->OCNPolarity << 8U);
-    /* Reset the Output N State */
-    tmpccer &= ~TIM_CCER_CC3NE;
-    
-    /* Reset the Output Compare and Output Compare N IDLE State */
-    tmpcr2 &= ~TIM_CR2_OIS3;
-    tmpcr2 &= ~TIM_CR2_OIS3N;
-    /* Set the Output Idle state */
-    tmpcr2 |= (OC_Config->OCIdleState << 4U);
-    /* Set the Output N Idle state */
-    tmpcr2 |= (OC_Config->OCNIdleState << 4U);
-  }
-  /* Write to TIMx CR2 */
-  TIMx->CR2 = tmpcr2;
-  
-  /* Write to TIMx CCMR2 */
-  TIMx->CCMR2 = tmpccmrx;
-  
-  /* Set the Capture Compare Register value */
-  TIMx->CCR3 = OC_Config->Pulse;
-  
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Time Output Compare 4 configuration
-  * @param  TIMx to select the TIM peripheral
-  * @param  OC_Config: The output configuration structure
-  * @retval None
-  */
-static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
-  uint32_t tmpccmrx = 0U;
-  uint32_t tmpccer = 0U;
-  uint32_t tmpcr2 = 0U;
-
-  /* Disable the Channel 4: Reset the CC4E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC4E;
-  
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
-  /* Get the TIMx CR2 register value */
-  tmpcr2 = TIMx->CR2;
-  
-  /* Get the TIMx CCMR2 register value */
-  tmpccmrx = TIMx->CCMR2;
-    
-  /* Reset the Output Compare mode and Capture/Compare selection Bits */
-  tmpccmrx &= ~TIM_CCMR2_OC4M;
-  tmpccmrx &= ~TIM_CCMR2_CC4S;
-  
-  /* Select the Output Compare Mode */
-  tmpccmrx |= (OC_Config->OCMode << 8U);
-  
-  /* Reset the Output Polarity level */
-  tmpccer &= ~TIM_CCER_CC4P;
-  /* Set the Output Compare Polarity */
-  tmpccer |= (OC_Config->OCPolarity << 12U);
-   
-  /*if((TIMx == TIM1) || (TIMx == TIM8))*/
-  if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
-  {
-    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-    /* Reset the Output Compare IDLE State */
-    tmpcr2 &= ~TIM_CR2_OIS4;
-    /* Set the Output Idle state */
-    tmpcr2 |= (OC_Config->OCIdleState << 6U);
-  }
-  /* Write to TIMx CR2 */
-  TIMx->CR2 = tmpcr2;
-  
-  /* Write to TIMx CCMR2 */  
-  TIMx->CCMR2 = tmpccmrx;
-    
-  /* Set the Capture Compare Register value */
-  TIMx->CCR4 = OC_Config->Pulse;
-  
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Time Output Compare 4 configuration
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  sSlaveConfig: The slave configuration structure
-  * @retval None
-  */
-static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
-                              TIM_SlaveConfigTypeDef * sSlaveConfig)
-{
-  uint32_t tmpsmcr = 0U;
-  uint32_t tmpccmr1 = 0U;
-  uint32_t tmpccer = 0U;
-
- /* Get the TIMx SMCR register value */
-  tmpsmcr = htim->Instance->SMCR;
-
-  /* Reset the Trigger Selection Bits */
-  tmpsmcr &= ~TIM_SMCR_TS;
-  /* Set the Input Trigger source */
-  tmpsmcr |= sSlaveConfig->InputTrigger;
-
-  /* Reset the slave mode Bits */
-  tmpsmcr &= ~TIM_SMCR_SMS;
-  /* Set the slave mode */
-  tmpsmcr |= sSlaveConfig->SlaveMode;
-
-  /* Write to TIMx SMCR */
-  htim->Instance->SMCR = tmpsmcr;
-  
-  /* Configure the trigger prescaler, filter, and polarity */
-  switch (sSlaveConfig->InputTrigger)
-  {
-  case TIM_TS_ETRF:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
-      assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
-      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
-      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-      /* Configure the ETR Trigger source */
-      TIM_ETR_SetConfig(htim->Instance, 
-                        sSlaveConfig->TriggerPrescaler, 
-                        sSlaveConfig->TriggerPolarity, 
-                        sSlaveConfig->TriggerFilter);
-    }
-    break;
-    
-  case TIM_TS_TI1F_ED:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-      
-      /* Disable the Channel 1: Reset the CC1E Bit */
-      tmpccer = htim->Instance->CCER;
-      htim->Instance->CCER &= ~TIM_CCER_CC1E;
-      tmpccmr1 = htim->Instance->CCMR1;    
-      
-      /* Set the filter */
-      tmpccmr1 &= ~TIM_CCMR1_IC1F;
-      tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
-      
-      /* Write to TIMx CCMR1 and CCER registers */
-      htim->Instance->CCMR1 = tmpccmr1;
-      htim->Instance->CCER = tmpccer;                               
-                               
-    }
-    break;
-    
-  case TIM_TS_TI1FP1:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
-      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
-      /* Configure TI1 Filter and Polarity */
-      TIM_TI1_ConfigInputStage(htim->Instance,
-                               sSlaveConfig->TriggerPolarity,
-                               sSlaveConfig->TriggerFilter);
-    }
-    break;
-    
-  case TIM_TS_TI2FP2:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
-      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-      
-      /* Configure TI2 Filter and Polarity */
-      TIM_TI2_ConfigInputStage(htim->Instance,
-                                sSlaveConfig->TriggerPolarity,
-                                sSlaveConfig->TriggerFilter);
-    }
-    break;
-    
-  case TIM_TS_ITR0:
-    {
-      /* Check the parameter */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-    }
-    break;
-    
-  case TIM_TS_ITR1:
-    {
-      /* Check the parameter */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-    }
-    break;
-    
-  case TIM_TS_ITR2:
-    {
-      /* Check the parameter */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-    }
-    break;
-    
-  case TIM_TS_ITR3:
-    {
-      /* Check the parameter */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-    }
-    break;
-       
-  default:
-    break;
-  }
-}
-
-
-/**
-  * @brief  Configure the Polarity and Filter for TI1.
-  * @param  TIMx to select the TIM peripheral.
-  * @param  TIM_ICPolarity : The Input Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPolarity_Rising
-  *            @arg TIM_ICPolarity_Falling
-  *            @arg TIM_ICPolarity_BothEdge
-  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
-  *          This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  */
-static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
-{
-  uint32_t tmpccmr1 = 0U;
-  uint32_t tmpccer = 0U;
-  
-  /* Disable the Channel 1: Reset the CC1E Bit */
-  tmpccer = TIMx->CCER;
-  TIMx->CCER &= ~TIM_CCER_CC1E;
-  tmpccmr1 = TIMx->CCMR1;    
-  
-  /* Set the filter */
-  tmpccmr1 &= ~TIM_CCMR1_IC1F;
-  tmpccmr1 |= (TIM_ICFilter << 4U);
-  
-  /* Select the Polarity and set the CC1E Bit */
-  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
-  tmpccer |= TIM_ICPolarity;
-  
-  /* Write to TIMx CCMR1 and CCER registers */
-  TIMx->CCMR1 = tmpccmr1;
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configure the TI2 as Input.
-  * @param  TIMx to select the TIM peripheral
-  * @param  TIM_ICPolarity : The Input Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPolarity_Rising
-  *            @arg TIM_ICPolarity_Falling
-  *            @arg TIM_ICPolarity_BothEdge   
-  * @param  TIM_ICSelection: specifies the input to be used.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
-  *            @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
-  *            @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
-  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
-  *          This parameter must be a value between 0x00 and 0x0F.
-  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 
-  *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be 
-  *        protected against un-initialized filter and polarity values.
-  * @retval None
-  */
-static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                       uint32_t TIM_ICFilter)
-{
-  uint32_t tmpccmr1 = 0U;
-  uint32_t tmpccer = 0U;
-
-  /* Disable the Channel 2: Reset the CC2E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC2E;
-  tmpccmr1 = TIMx->CCMR1;
-  tmpccer = TIMx->CCER;
-  
-  /* Select the Input */
-  tmpccmr1 &= ~TIM_CCMR1_CC2S;
-  tmpccmr1 |= (TIM_ICSelection << 8U);
-  
-  /* Set the filter */
-  tmpccmr1 &= ~TIM_CCMR1_IC2F;
-  tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
-
-  /* Select the Polarity and set the CC2E Bit */
-  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
-  tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
-
-  /* Write to TIMx CCMR1 and CCER registers */
-  TIMx->CCMR1 = tmpccmr1 ;
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configure the Polarity and Filter for TI2.
-  * @param  TIMx to select the TIM peripheral.
-  * @param  TIM_ICPolarity : The Input Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPolarity_Rising
-  *            @arg TIM_ICPolarity_Falling
-  *            @arg TIM_ICPolarity_BothEdge
-  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
-  *          This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  */
-static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
-{
-  uint32_t tmpccmr1 = 0U;
-  uint32_t tmpccer = 0U;
-  
-  /* Disable the Channel 2: Reset the CC2E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC2E;
-  tmpccmr1 = TIMx->CCMR1;
-  tmpccer = TIMx->CCER;
-  
-  /* Set the filter */
-  tmpccmr1 &= ~TIM_CCMR1_IC2F;
-  tmpccmr1 |= (TIM_ICFilter << 12U);
-
-  /* Select the Polarity and set the CC2E Bit */
-  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
-  tmpccer |= (TIM_ICPolarity << 4U);
-
-  /* Write to TIMx CCMR1 and CCER registers */
-  TIMx->CCMR1 = tmpccmr1 ;
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configure the TI3 as Input.
-  * @param  TIMx to select the TIM peripheral
-  * @param  TIM_ICPolarity : The Input Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPolarity_Rising
-  *            @arg TIM_ICPolarity_Falling
-  *            @arg TIM_ICPolarity_BothEdge         
-  * @param  TIM_ICSelection: specifies the input to be used.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
-  *            @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
-  *            @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
-  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
-  *          This parameter must be a value between 0x00 and 0x0F.
-  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 
-  *       (on channel4 path) is used as the input signal. Therefore CCMR2 must be 
-  *        protected against un-initialized filter and polarity values.
-  * @retval None
-  */
-static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                       uint32_t TIM_ICFilter)
-{
-  uint32_t tmpccmr2 = 0U;
-  uint32_t tmpccer = 0U;
-
-  /* Disable the Channel 3: Reset the CC3E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC3E;
-  tmpccmr2 = TIMx->CCMR2;
-  tmpccer = TIMx->CCER;
-
-  /* Select the Input */
-  tmpccmr2 &= ~TIM_CCMR2_CC3S;
-  tmpccmr2 |= TIM_ICSelection;
-
-  /* Set the filter */
-  tmpccmr2 &= ~TIM_CCMR2_IC3F;
-  tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
-
-  /* Select the Polarity and set the CC3E Bit */
-  tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
-  tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
-
-  /* Write to TIMx CCMR2 and CCER registers */
-  TIMx->CCMR2 = tmpccmr2;
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configure the TI4 as Input.
-  * @param  TIMx to select the TIM peripheral
-  * @param  TIM_ICPolarity : The Input Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPolarity_Rising
-  *            @arg TIM_ICPolarity_Falling
-  *            @arg TIM_ICPolarity_BothEdge     
-  * @param  TIM_ICSelection: specifies the input to be used.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
-  *            @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
-  *            @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
-  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
-  *          This parameter must be a value between 0x00 and 0x0F.
-  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 
-  *       (on channel3 path) is used as the input signal. Therefore CCMR2 must be 
-  *        protected against un-initialized filter and polarity values.
-  * @retval None
-  */
-static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                       uint32_t TIM_ICFilter)
-{
-  uint32_t tmpccmr2 = 0U;
-  uint32_t tmpccer = 0U;
-
-  /* Disable the Channel 4: Reset the CC4E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC4E;
-  tmpccmr2 = TIMx->CCMR2;
-  tmpccer = TIMx->CCER;
-
-  /* Select the Input */
-  tmpccmr2 &= ~TIM_CCMR2_CC4S;
-  tmpccmr2 |= (TIM_ICSelection << 8U);
-
-  /* Set the filter */
-  tmpccmr2 &= ~TIM_CCMR2_IC4F;
-  tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
-
-  /* Select the Polarity and set the CC4E Bit */
-  tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
-  tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
-
-  /* Write to TIMx CCMR2 and CCER registers */
-  TIMx->CCMR2 = tmpccmr2;
-  TIMx->CCER = tmpccer ;
-}
-
-/**
-  * @brief  Selects the Input Trigger source
-  * @param  TIMx to select the TIM peripheral
-  * @param  TIM_ITRx: The Input Trigger source.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_TS_ITR0: Internal Trigger 0
-  *            @arg TIM_TS_ITR1: Internal Trigger 1
-  *            @arg TIM_TS_ITR2: Internal Trigger 2
-  *            @arg TIM_TS_ITR3: Internal Trigger 3
-  *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
-  *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
-  *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
-  *            @arg TIM_TS_ETRF: External Trigger input
-  * @retval None
-  */
-static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t TIM_ITRx)
-{
-  uint32_t tmpsmcr = 0U;
-  
-   /* Get the TIMx SMCR register value */
-   tmpsmcr = TIMx->SMCR;
-   /* Reset the TS Bits */
-   tmpsmcr &= ~TIM_SMCR_TS;
-   /* Set the Input Trigger source and the slave mode*/
-   tmpsmcr |= TIM_ITRx | TIM_SLAVEMODE_EXTERNAL1;
-   /* Write to TIMx SMCR */
-   TIMx->SMCR = tmpsmcr;
-}
-
-/**
-  * @brief  Configures the TIMx External Trigger (ETR).
-  * @param  TIMx to select the TIM peripheral
-  * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF.
-  *            @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2.
-  *            @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4.
-  *            @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8.
-  * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active.
-  *            @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active.
-  * @param  ExtTRGFilter: External Trigger Filter.
-  *          This parameter must be a value between 0x00 and 0x0F
-  * @retval None
-  */
-static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
-                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
-{
-  uint32_t tmpsmcr = 0U;
-
-  tmpsmcr = TIMx->SMCR;
-
-  /* Reset the ETR Bits */
-  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
-
-  /* Set the Prescaler, the Filter value and the Polarity */
-  tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
-
-  /* Write to TIMx SMCR */
-  TIMx->SMCR = tmpsmcr;
-} 
-
-/**
-  * @}
-  */
-
-#endif /* HAL_TIM_MODULE_ENABLED */
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_tim_ex.c b/stmhal/hal/f4/src/stm32f4xx_hal_tim_ex.c
deleted file mode 100644
index 607a963333..0000000000
--- a/stmhal/hal/f4/src/stm32f4xx_hal_tim_ex.c
+++ /dev/null
@@ -1,1873 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_tim_ex.c
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   TIM HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the Timer extension peripheral:
-  *           + Time Hall Sensor Interface Initialization
-  *           + Time Hall Sensor Interface Start
-  *           + Time Complementary signal bread and dead time configuration  
-  *           + Time Master and Slave synchronization configuration
-  @verbatim 
-  ==============================================================================
-                      ##### TIMER Extended features #####
-  ==============================================================================
-  [..] 
-    The Timer Extension features include: 
-    (#) Complementary outputs with programmable dead-time for :
-        (++) Input Capture
-        (++) Output Compare
-        (++) PWM generation (Edge and Center-aligned Mode)
-        (++) One-pulse mode output
-    (#) Synchronization circuit to control the timer with external signals and to 
-        interconnect several timers together.
-    (#) Break input to put the timer output signals in reset state or in a known state.
-    (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for 
-        positioning purposes                
-   
-                        ##### How to use this driver #####
-  ==============================================================================
-  [..]
-     (#) Initialize the TIM low level resources by implementing the following functions 
-         depending from feature used :
-           (++) Complementary Output Compare : HAL_TIM_OC_MspInit()
-           (++) Complementary PWM generation : HAL_TIM_PWM_MspInit()
-           (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()
-           (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit()
-           
-     (#) Initialize the TIM low level resources :
-        (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE(); 
-        (##) TIM pins configuration
-            (+++) Enable the clock for the TIM GPIOs using the following function:
-                 __GPIOx_CLK_ENABLE();   
-            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();  
-
-     (#) The external Clock can be configured, if needed (the default clock is the 
-         internal clock from the APBx), using the following function:
-         HAL_TIM_ConfigClockSource, the clock configuration should be done before 
-         any start function.
-  
-    (#) Configure the TIM in the desired functioning mode using one of the 
-        initialization function of this driver:
-        (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the 
-             Timer Hall Sensor Interface and the commutation event with the corresponding 
-             Interrupt and DMA request if needed (Note that One Timer is used to interface 
-             with the Hall sensor Interface and another Timer should be used to use 
-             the commutation event).
-
-    (#) Activate the TIM peripheral using one of the start functions: 
-           (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
-           (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
-           (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
-           (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
-
-  
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup TIMEx  TIMEx
-  * @brief TIM HAL module driver
-  * @{
-  */
-
-#ifdef HAL_TIM_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @addtogroup TIMEx_Private_Functions
-  * @{
-  */
-/* Private function prototypes -----------------------------------------------*/
-static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
-/**
-  * @}
-  */
-      
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Functions TIM Exported Functions
-  * @{
-  */
-
-/** @defgroup TIMEx_Exported_Functions_Group1 Timer Hall Sensor functions 
- *  @brief    Timer Hall Sensor functions 
- *
-@verbatim    
-  ==============================================================================
-                      ##### Timer Hall Sensor functions #####
-  ==============================================================================
-  [..]  
-    This section provides functions allowing to:
-    (+) Initialize and configure TIM HAL Sensor. 
-    (+) De-initialize TIM HAL Sensor.
-    (+) Start the Hall Sensor Interface.
-    (+) Stop the Hall Sensor Interface.
-    (+) Start the Hall Sensor Interface and enable interrupts.
-    (+) Stop the Hall Sensor Interface and disable interrupts.
-    (+) Start the Hall Sensor Interface and enable DMA transfers.
-    (+) Stop the Hall Sensor Interface and disable DMA transfers.
- 
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIM Hall Sensor Interface and create the associated handle.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  sConfig: TIM Hall Sensor configuration structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
-{
-  TIM_OC_InitTypeDef OC_Config;
-    
-  /* Check the TIM handle allocation */
-  if(htim == NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-  assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
-  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
-  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
-
-  /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;
-  
-  /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
-  HAL_TIMEx_HallSensor_MspInit(htim);
-  
-  /* Configure the Time base in the Encoder Mode */
-  TIM_Base_SetConfig(htim->Instance, &htim->Init);
-  
-  /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the  Hall sensor */
-  TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
-  
-  /* Reset the IC1PSC Bits */
-  htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
-  /* Set the IC1PSC value */
-  htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
-  
-  /* Enable the Hall sensor interface (XOR function of the three inputs) */
-  htim->Instance->CR2 |= TIM_CR2_TI1S;
-  
-  /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
-  htim->Instance->SMCR &= ~TIM_SMCR_TS;
-  htim->Instance->SMCR |= TIM_TS_TI1F_ED;
-  
-  /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */  
-  htim->Instance->SMCR &= ~TIM_SMCR_SMS;
-  htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
-  
-  /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
-  OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
-  OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
-  OC_Config.OCMode = TIM_OCMODE_PWM2;
-  OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
-  OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
-  OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
-  OC_Config.Pulse = sConfig->Commutation_Delay; 
-    
-  TIM_OC2_SetConfig(htim->Instance, &OC_Config);
-  
-  /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
-    register to 101 */
-  htim->Instance->CR2 &= ~TIM_CR2_MMS;
-  htim->Instance->CR2 |= TIM_TRGO_OC2REF; 
-  
-  /* Initialize the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the TIM Hall Sensor interface  
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  htim->State = HAL_TIM_STATE_BUSY;
-  
-  /* Disable the TIM Peripheral Clock */
-  __HAL_TIM_DISABLE(htim);
-    
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
-  HAL_TIMEx_HallSensor_MspDeInit(htim);
-    
-  /* Change TIM state */  
-  htim->State = HAL_TIM_STATE_RESET; 
-
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM Hall Sensor MSP.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes TIM Hall Sensor MSP.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Starts the TIM Hall Sensor Interface.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-  
-  /* Enable the Input Capture channels 1
-    (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */  
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 
-  
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Hall sensor Interface.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-  
-  /* Disable the Input Capture channels 1, 2 and 3
-    (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */  
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Hall Sensor Interface in interrupt mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
-{ 
-  /* Check the parameters */
-  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-  
-  /* Enable the capture compare Interrupts 1 event */
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-  
-  /* Enable the Input Capture channels 1
-    (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */  
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);  
-  
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Hall Sensor Interface in interrupt mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-  
-  /* Disable the Input Capture channels 1
-    (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */  
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 
-  
-  /* Disable the capture compare Interrupts event */
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-  
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Hall Sensor Interface in DMA mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  pData: The destination Buffer address.
-  * @param  Length: The length of data to be transferred from TIM peripheral to memory.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-  
-   if((htim->State == HAL_TIM_STATE_BUSY))
-  {
-     return HAL_BUSY;
-  }
-  else if((htim->State == HAL_TIM_STATE_READY))
-  {
-    if(((uint32_t)pData == 0U) && (Length > 0U)) 
-    {
-      return HAL_ERROR;                                    
-    }
-    else
-    {
-      htim->State = HAL_TIM_STATE_BUSY;
-    }
-  }
-  /* Enable the Input Capture channels 1
-    (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */  
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 
-  
-  /* Set the DMA Input Capture 1 Callback */
-  htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;     
-  /* Set the DMA error callback */
-  htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-  
-  /* Enable the DMA Stream for Capture 1*/
-  HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);    
-  
-  /* Enable the capture compare 1 Interrupt */
-  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
- 
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Hall Sensor Interface in DMA mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-  
-  /* Disable the Input Capture channels 1
-    (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */  
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 
- 
-  
-  /* Disable the capture compare Interrupts 1 event */
-  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- 
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-/**
-  * @}
-  */
-  
-/** @defgroup TIMEx_Exported_Functions_Group2 Timer Complementary Output Compare functions
- *  @brief    Timer Complementary Output Compare functions 
- *
-@verbatim   
-  ==============================================================================
-              ##### Timer Complementary Output Compare functions #####
-  ==============================================================================  
-  [..]  
-    This section provides functions allowing to:
-    (+) Start the Complementary Output Compare/PWM.
-    (+) Stop the Complementary Output Compare/PWM.
-    (+) Start the Complementary Output Compare/PWM and enable interrupts.
-    (+) Stop the Complementary Output Compare/PWM and disable interrupts.
-    (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
-    (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
-               
-@endverbatim
-  * @{
-  */
-  
-/**
-  * @brief  Starts the TIM Output Compare signal generation on the complementary
-  *         output.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.  
-  * @param  Channel: TIM Channel to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 
-  
-     /* Enable the Capture compare channel N */
-     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-    
-  /* Enable the Main Output */
-    __HAL_TIM_MOE_ENABLE(htim);
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-  
-  /* Return function status */
-  return HAL_OK;
-} 
-
-/**
-  * @brief  Stops the TIM Output Compare signal generation on the complementary
-  *         output.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be disabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{ 
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 
-  
-    /* Disable the Capture compare channel N */
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-    
-  /* Disable the Main Output */
-    __HAL_TIM_MOE_DISABLE(htim);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-  
-  /* Return function status */
-  return HAL_OK;
-} 
-
-/**
-  * @brief  Starts the TIM Output Compare signal generation in interrupt mode 
-  *         on the complementary output.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 
-  
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {       
-      /* Enable the TIM Output Compare interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-    }
-    break;
-    
-    case TIM_CHANNEL_2:
-    {
-      /* Enable the TIM Output Compare interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-    }
-    break;
-    
-    case TIM_CHANNEL_3:
-    {
-      /* Enable the TIM Output Compare interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
-    }
-    break;
-    
-    case TIM_CHANNEL_4:
-    {
-      /* Enable the TIM Output Compare interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
-    }
-    break;
-    
-    default:
-    break;
-  } 
-  
-  /* Enable the TIM Break interrupt */
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
-  
-  /* Enable the Capture compare channel N */
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-  
-  /* Enable the Main Output */
-  __HAL_TIM_MOE_ENABLE(htim);
-  
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-  
-  /* Return function status */
-  return HAL_OK;
-} 
-
-/**
-  * @brief  Stops the TIM Output Compare signal generation in interrupt mode 
-  *         on the complementary output.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be disabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 
-  
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {       
-      /* Disable the TIM Output Compare interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-    }
-    break;
-    
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Output Compare interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-    }
-    break;
-    
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Output Compare interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
-    }
-    break;
-    
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Output Compare interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
-    }
-    break;
-    
-    default:
-    break; 
-  }
-  
-  /* Disable the Capture compare channel N */
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
-  /* Disable the TIM Break interrupt (only if no more channel is active) */
-  if((READ_REG(htim->Instance->CCER) & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
-  {
-    __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
-  }
-  
-  /* Disable the Main Output */
-  __HAL_TIM_MOE_DISABLE(htim);
-  
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-  
-  /* Return function status */
-  return HAL_OK;
-} 
-
-/**
-  * @brief  Starts the TIM Output Compare signal generation in DMA mode 
-  *         on the complementary output.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  pData: The source Buffer address.
-  * @param  Length: The length of data to be transferred from memory to TIM peripheral
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 
-  
-  if((htim->State == HAL_TIM_STATE_BUSY))
-  {
-     return HAL_BUSY;
-  }
-  else if((htim->State == HAL_TIM_STATE_READY))
-  {
-    if(((uint32_t)pData == 0U) && (Length > 0U)) 
-    {
-      return HAL_ERROR;                                    
-    }
-    else
-    {
-      htim->State = HAL_TIM_STATE_BUSY;
-    }
-  }    
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {      
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
-     
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
-      
-      /* Enable the TIM Output Compare DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-    }
-    break;
-    
-    case TIM_CHANNEL_2:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
-     
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
-      
-      /* Enable the TIM Output Compare DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-    }
-    break;
-    
-    case TIM_CHANNEL_3:
-{
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
-     
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-      
-      /* Enable the TIM Output Compare DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
-    }
-    break;
-    
-    case TIM_CHANNEL_4:
-    {
-     /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
-     
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-      
-      /* Enable the TIM Output Compare DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
-    }
-    break;
-    
-    default:
-    break;
-  }
-
-  /* Enable the Capture compare channel N */
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-  
-  /* Enable the Main Output */
-  __HAL_TIM_MOE_ENABLE(htim);
-  
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim); 
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Output Compare signal generation in DMA mode 
-  *         on the complementary output.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be disabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 
-  
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {       
-      /* Disable the TIM Output Compare DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-    }
-    break;
-    
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Output Compare DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
-    }
-    break;
-    
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Output Compare DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
-    }
-    break;
-    
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Output Compare interrupt */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
-    }
-    break;
-    
-    default:
-    break;
-  } 
-  
-  /* Disable the Capture compare channel N */
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-  
-  /* Disable the Main Output */
-  __HAL_TIM_MOE_DISABLE(htim);
-  
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-  
-  /* Change the htim state */
-  htim->State = HAL_TIM_STATE_READY;
-  
-  /* Return function status */
-  return HAL_OK;
-}
-/**
-  * @}
-  */
-  
-/** @defgroup TIMEx_Exported_Functions_Group3 Timer Complementary PWM functions
- *  @brief    Timer Complementary PWM functions 
- *
-@verbatim   
-  ==============================================================================
-                 ##### Timer Complementary PWM functions #####
-  ==============================================================================  
-  [..]  
-    This section provides functions allowing to:
-    (+) Start the Complementary PWM.
-    (+) Stop the Complementary PWM.
-    (+) Start the Complementary PWM and enable interrupts.
-    (+) Stop the Complementary PWM and disable interrupts.
-    (+) Start the Complementary PWM and enable DMA transfers.
-    (+) Stop the Complementary PWM and disable DMA transfers.
-    (+) Start the Complementary Input Capture measurement.
-    (+) Stop the Complementary Input Capture.
-    (+) Start the Complementary Input Capture and enable interrupts.
-    (+) Stop the Complementary Input Capture and disable interrupts.
-    (+) Start the Complementary Input Capture and enable DMA transfers.
-    (+) Stop the Complementary Input Capture and disable DMA transfers.
-    (+) Start the Complementary One Pulse generation.
-    (+) Stop the Complementary One Pulse.
-    (+) Start the Complementary One Pulse and enable interrupts.
-    (+) Stop the Complementary One Pulse and disable interrupts.
-               
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Starts the PWM signal generation on the complementary output.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 
-  
-  /* Enable the complementary PWM output  */
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-  
-  /* Enable the Main Output */
-  __HAL_TIM_MOE_ENABLE(htim);
-  
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-  
-  /* Return function status */
-  return HAL_OK;
-} 
-
-/**
-  * @brief  Stops the PWM signal generation on the complementary output.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be disabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{ 
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 
-  
-  /* Disable the complementary PWM output  */
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);  
-  
-  /* Disable the Main Output */
-  __HAL_TIM_MOE_DISABLE(htim);
-  
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-  
-  /* Return function status */
-  return HAL_OK;
-} 
-
-/**
-  * @brief  Starts the PWM signal generation in interrupt mode on the 
-  *         complementary output.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be disabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 
-  
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {       
-      /* Enable the TIM Capture/Compare 1 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-    }
-    break;
-    
-    case TIM_CHANNEL_2:
-    {
-      /* Enable the TIM Capture/Compare 2 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-    }
-    break;
-    
-    case TIM_CHANNEL_3:
-    {
-      /* Enable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
-    }
-    break;
-    
-    case TIM_CHANNEL_4:
-    {
-      /* Enable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
-    }
-    break;
-    
-    default:
-    break;
-  } 
-  
-  /* Enable the TIM Break interrupt */
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
-  
-  /* Enable the complementary PWM output  */
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-  
-  /* Enable the Main Output */
-  __HAL_TIM_MOE_ENABLE(htim);
-  
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-  
-  /* Return function status */
-  return HAL_OK;
-} 
-
-/**
-  * @brief  Stops the PWM signal generation in interrupt mode on the 
-  *         complementary output.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be disabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {       
-      /* Disable the TIM Capture/Compare 1 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-    }
-    break;
-    
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Capture/Compare 2 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-    }
-    break;
-    
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
-    }
-    break;
-    
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
-    }
-    break;
-    
-    default:
-    break; 
-  }
-  
-  /* Disable the complementary PWM output  */
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-  
-  /* Disable the TIM Break interrupt (only if no more channel is active) */
-  if((READ_REG(htim->Instance->CCER) & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
-  {
-    __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
-  }
-  
-  /* Disable the Main Output */
-  __HAL_TIM_MOE_DISABLE(htim);
-  
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-  
-  /* Return function status */
-  return HAL_OK;
-} 
-
-/**
-  * @brief  Starts the TIM PWM signal generation in DMA mode on the 
-  *         complementary output
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  pData: The source Buffer address.
-  * @param  Length: The length of data to be transferred from memory to TIM peripheral
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 
-  
-  if((htim->State == HAL_TIM_STATE_BUSY))
-  {
-     return HAL_BUSY;
-  }
-  else if((htim->State == HAL_TIM_STATE_READY))
-  {
-    if(((uint32_t)pData == 0U) && (Length > 0U)) 
-    {
-      return HAL_ERROR;                                    
-    }
-    else
-    {
-      htim->State = HAL_TIM_STATE_BUSY;
-    }
-  }    
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {      
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
-     
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
-      
-      /* Enable the TIM Capture/Compare 1 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-    }
-    break;
-    
-    case TIM_CHANNEL_2:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
-     
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
-      
-      /* Enable the TIM Capture/Compare 2 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-    }
-    break;
-    
-    case TIM_CHANNEL_3:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
-     
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-      
-      /* Enable the TIM Capture/Compare 3 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
-    }
-    break;
-    
-    case TIM_CHANNEL_4:
-    {
-     /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
-     
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-      
-      /* Enable the TIM Capture/Compare 4 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
-    }
-    break;
-    
-    default:
-    break;
-  }
-
-  /* Enable the complementary PWM output  */
-     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-    
-  /* Enable the Main Output */
-    __HAL_TIM_MOE_ENABLE(htim);
-  
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim); 
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM PWM signal generation in DMA mode on the complementary
-  *         output
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be disabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 
-  
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {       
-      /* Disable the TIM Capture/Compare 1 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-    }
-    break;
-    
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Capture/Compare 2 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
-    }
-    break;
-    
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Capture/Compare 3 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
-    }
-    break;
-    
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 4 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
-    }
-    break;
-    
-    default:
-    break;
-  } 
-  
-  /* Disable the complementary PWM output */
-    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-     
-  /* Disable the Main Output */
-    __HAL_TIM_MOE_DISABLE(htim);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-  
-  /* Change the htim state */
-  htim->State = HAL_TIM_STATE_READY;
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-  
-/** @defgroup TIMEx_Exported_Functions_Group4 Timer Complementary One Pulse functions
- *  @brief    Timer Complementary One Pulse functions 
- *
-@verbatim   
-  ==============================================================================
-                ##### Timer Complementary One Pulse functions #####
-  ==============================================================================  
-  [..]  
-    This section provides functions allowing to:
-    (+) Start the Complementary One Pulse generation.
-    (+) Stop the Complementary One Pulse.
-    (+) Start the Complementary One Pulse and enable interrupts.
-    (+) Stop the Complementary One Pulse and disable interrupts.
-               
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Starts the TIM One Pulse signal generation on the complementary 
-  *         output.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  OutputChannel: TIM Channel to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-  {
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); 
-  
-  /* Enable the complementary One Pulse output */
-  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); 
-  
-  /* Enable the Main Output */
-  __HAL_TIM_MOE_ENABLE(htim);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM One Pulse signal generation on the complementary 
-  *         output.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  OutputChannel: TIM Channel to be disabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); 
-
-  /* Disable the complementary One Pulse output */
-    TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
-  
-  /* Disable the Main Output */
-    __HAL_TIM_MOE_DISABLE(htim);
-  
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim); 
-   
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM One Pulse signal generation in interrupt mode on the
-  *         complementary channel.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  OutputChannel: TIM Channel to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); 
-
-  /* Enable the TIM Capture/Compare 1 interrupt */
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-  
-  /* Enable the TIM Capture/Compare 2 interrupt */
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-  
-  /* Enable the complementary One Pulse output */
-  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); 
-  
-  /* Enable the Main Output */
-  __HAL_TIM_MOE_ENABLE(htim);
-  
-  /* Return function status */
-  return HAL_OK;
-  } 
-  
-/**
-  * @brief  Stops the TIM One Pulse signal generation in interrupt mode on the
-  *         complementary channel.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  OutputChannel: TIM Channel to be disabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); 
-
-  /* Disable the TIM Capture/Compare 1 interrupt */
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-  
-  /* Disable the TIM Capture/Compare 2 interrupt */
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-  
-  /* Disable the complementary One Pulse output */
-  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
-  
-  /* Disable the Main Output */
-  __HAL_TIM_MOE_DISABLE(htim);
-  
-  /* Disable the Peripheral */
-   __HAL_TIM_DISABLE(htim);  
-  
-  /* Return function status */
-  return HAL_OK;
-}
-/**
-  * @}
-  */
-  
-/** @defgroup TIMEx_Exported_Functions_Group5 Peripheral Control functions
- *  @brief   	Peripheral Control functions 
- *
-@verbatim   
-  ==============================================================================
-                    ##### Peripheral Control functions #####
-  ==============================================================================  
-  [..]  
-    This section provides functions allowing to:
-    (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. 
-    (+) Configure External Clock source.
-    (+) Configure Complementary channels, break features and dead time.
-    (+) Configure Master and the Slave synchronization.
-    (+) Configure the commutation event in case of use of the Hall sensor interface.
-    (+) Configure the DMA Burst Mode.
-      
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Configure the TIM commutation event sequence.
-  * @note  This function is mandatory to use the commutation event in order to 
-  *        update the configuration at each commutation detection on the TRGI input of the Timer,
-  *        the typical use of this feature is with the use of another Timer(interface Timer) 
-  *        configured in Hall sensor interface, this interface Timer will generate the 
-  *        commutation at its TRGO output (connected to Timer used in this function) each time 
-  *        the TI1 of the Interface Timer detect a commutation at its input TI1.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_TS_ITR0: Internal trigger 0 selected
-  *            @arg TIM_TS_ITR1: Internal trigger 1 selected
-  *            @arg TIM_TS_ITR2: Internal trigger 2 selected
-  *            @arg TIM_TS_ITR3: Internal trigger 3 selected
-  *            @arg TIM_TS_NONE: No trigger is needed  
-  * @param  CommutationSource: the Commutation Event source.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
-  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
-  
-  __HAL_LOCK(htim);
-  
-  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
-      (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
-  {    
-    /* Select the Input trigger */
-    htim->Instance->SMCR &= ~TIM_SMCR_TS;
-    htim->Instance->SMCR |= InputTrigger;
-  }
-    
-  /* Select the Capture Compare preload feature */
-  htim->Instance->CR2 |= TIM_CR2_CCPC;
-  /* Select the Commutation event source */
-  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
-  htim->Instance->CR2 |= CommutationSource;
-    
-  __HAL_UNLOCK(htim);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configure the TIM commutation event sequence with interrupt.
-  * @note  This function is mandatory to use the commutation event in order to 
-  *        update the configuration at each commutation detection on the TRGI input of the Timer,
-  *        the typical use of this feature is with the use of another Timer(interface Timer) 
-  *        configured in Hall sensor interface, this interface Timer will generate the 
-  *        commutation at its TRGO output (connected to Timer used in this function) each time 
-  *        the TI1 of the Interface Timer detect a commutation at its input TI1.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_TS_ITR0: Internal trigger 0 selected
-  *            @arg TIM_TS_ITR1: Internal trigger 1 selected
-  *            @arg TIM_TS_ITR2: Internal trigger 2 selected
-  *            @arg TIM_TS_ITR3: Internal trigger 3 selected
-  *            @arg TIM_TS_NONE: No trigger is needed
-  * @param  CommutationSource: the Commutation Event source.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
-  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
-  
-  __HAL_LOCK(htim);
-  
-  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
-      (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
-  {    
-    /* Select the Input trigger */
-    htim->Instance->SMCR &= ~TIM_SMCR_TS;
-    htim->Instance->SMCR |= InputTrigger;
-  }
-  
-  /* Select the Capture Compare preload feature */
-  htim->Instance->CR2 |= TIM_CR2_CCPC;
-  /* Select the Commutation event source */
-  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
-  htim->Instance->CR2 |= CommutationSource;
-    
-  /* Enable the Commutation Interrupt Request */
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
-
-  __HAL_UNLOCK(htim);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configure the TIM commutation event sequence with DMA.
-  * @note  This function is mandatory to use the commutation event in order to 
-  *        update the configuration at each commutation detection on the TRGI input of the Timer,
-  *        the typical use of this feature is with the use of another Timer(interface Timer) 
-  *        configured in Hall sensor interface, this interface Timer will generate the 
-  *        commutation at its TRGO output (connected to Timer used in this function) each time 
-  *        the TI1 of the Interface Timer detect a commutation at its input TI1.
-  * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_TS_ITR0: Internal trigger 0 selected
-  *            @arg TIM_TS_ITR1: Internal trigger 1 selected
-  *            @arg TIM_TS_ITR2: Internal trigger 2 selected
-  *            @arg TIM_TS_ITR3: Internal trigger 3 selected
-  *            @arg TIM_TS_NONE: No trigger is needed
-  * @param  CommutationSource: the Commutation Event source.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
-  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
-  
-  __HAL_LOCK(htim);
-  
-  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
-      (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
-  {    
-    /* Select the Input trigger */
-    htim->Instance->SMCR &= ~TIM_SMCR_TS;
-    htim->Instance->SMCR |= InputTrigger;
-  }
-  
-  /* Select the Capture Compare preload feature */
-  htim->Instance->CR2 |= TIM_CR2_CCPC;
-  /* Select the Commutation event source */
-  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
-  htim->Instance->CR2 |= CommutationSource;
-  
-  /* Enable the Commutation DMA Request */
-  /* Set the DMA Commutation Callback */
-  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;     
-  /* Set the DMA error callback */
-  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
-  
-  /* Enable the Commutation DMA Request */
-  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
-
-  __HAL_UNLOCK(htim);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the TIM in master mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.   
-  * @param  sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that
-  *         contains the selected trigger output (TRGO) and the Master/Slave 
-  *         mode. 
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
-  assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
-  
-  __HAL_LOCK(htim);
-  
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Reset the MMS Bits */
-  htim->Instance->CR2 &= ~TIM_CR2_MMS;
-  /* Select the TRGO source */
-  htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger;
-
-  /* Reset the MSM Bit */
-  htim->Instance->SMCR &= ~TIM_SMCR_MSM;
-  /* Set or Reset the MSM Bit */
-  htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode;
-  
-  htim->State = HAL_TIM_STATE_READY;
-  
-  __HAL_UNLOCK(htim);
-  
-  return HAL_OK;
-} 
-                                                     
-/**
-  * @brief   Configures the Break feature, dead time, Lock level, OSSI/OSSR State
-  *         and the AOE(automatic output enable).
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfig_TypeDef structure that
-  *         contains the BDTR Register configuration  information for the TIM peripheral. 
-  * @retval HAL status
-  */    
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, 
-                                              TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
-  assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
-  assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
-  assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
-  assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
-  assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
-  assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
-  
-  /* Process Locked */
-  __HAL_LOCK(htim);
-  
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
-     the OSSI State, the dead time value and the Automatic Output Enable Bit */
-  htim->Instance->BDTR = (uint32_t)sBreakDeadTimeConfig->OffStateRunMode  | 
-                                   sBreakDeadTimeConfig->OffStateIDLEMode |
-                                   sBreakDeadTimeConfig->LockLevel        |
-                                   sBreakDeadTimeConfig->DeadTime         |
-                                   sBreakDeadTimeConfig->BreakState       |
-                                   sBreakDeadTimeConfig->BreakPolarity    |
-                                   sBreakDeadTimeConfig->AutomaticOutput;
-  
-                                   
-  htim->State = HAL_TIM_STATE_READY;                                 
-  
-  __HAL_UNLOCK(htim);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Remap: specifies the TIM input remapping source.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default)
-  *            @arg TIM_TIM2_ETH_PTP:   TIM2 ITR1 input is connected to ETH PTP trigger output.
-  *            @arg TIM_TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF. 
-  *            @arg TIM_TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF. 
-  *            @arg TIM_TIM5_GPIO:      TIM5 CH4 input is connected to dedicated Timer pin(default)
-  *            @arg TIM_TIM5_LSI:       TIM5 CH4 input is connected to LSI clock.
-  *            @arg TIM_TIM5_LSE:       TIM5 CH4 input is connected to LSE clock.
-  *            @arg TIM_TIM5_RTC:       TIM5 CH4 input is connected to RTC Output event.
-  *            @arg TIM_TIM11_GPIO:     TIM11 CH4 input is connected to dedicated Timer pin(default) 
-  *            @arg TIM_TIM11_HSE:      TIM11 CH4 input is connected to HSE_RTC clock
-  *                                     (HSE divided by a programmable prescaler)  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
-{
-  __HAL_LOCK(htim);
-    
-  /* Check parameters */
-  assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_REMAP(Remap));
-  
-  /* Set the Timer remapping configuration */
-  htim->Instance->OR = Remap;
-  
-  htim->State = HAL_TIM_STATE_READY;
-  
-  __HAL_UNLOCK(htim);  
-  
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions 
- *  @brief   Extension Callbacks functions 
- *
-@verbatim   
-  ==============================================================================
-                    ##### Extension Callbacks functions #####
-  ==============================================================================  
-  [..]  
-    This section provides Extension TIM callback functions:
-    (+) Timer Commutation callback
-    (+) Timer Break callback
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Hall commutation changed callback in non blocking mode 
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIMEx_CommutationCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Hall Break detection callback in non blocking mode 
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIMEx_BreakCallback could be implemented in the user file
-   */
-}
-/**
-  * @}
-  */
-
-/** @defgroup TIMEx_Exported_Functions_Group7 Extension Peripheral State functions 
- *  @brief   Extension Peripheral State functions 
- *
-@verbatim   
-  ==============================================================================
-                ##### Extension Peripheral State functions #####
-  ==============================================================================  
-  [..]
-    This subsection permits to get in run-time the status of the peripheral 
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the TIM Hall Sensor interface state
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL state
-  */
-HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
-{
-  return htim->State;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @brief  TIM DMA Commutation callback. 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  htim->State= HAL_TIM_STATE_READY;
-    
-  HAL_TIMEx_CommutationCallback(htim); 
-}
-/**
-  * @}
-  */
-  
-/**
-  * @brief  Enables or disables the TIM Capture Compare Channel xN.
-  * @param  TIMx to select the TIM peripheral
-  * @param  Channel: specifies the TIM Channel
-  *          This parameter can be one of the following values:
-  *            @arg TIM_Channel_1: TIM Channel 1
-  *            @arg TIM_Channel_2: TIM Channel 2
-  *            @arg TIM_Channel_3: TIM Channel 3
-  * @param  ChannelNState: specifies the TIM Channel CCxNE bit new state.
-  *          This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. 
-  * @retval None
-  */
-static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
-{
-  uint32_t tmp = 0U;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CC4_INSTANCE(TIMx));
-  assert_param(IS_TIM_COMPLEMENTARY_CHANNELS(Channel));
-
-  tmp = TIM_CCER_CC1NE << Channel;
-
-  /* Reset the CCxNE Bit */
-  TIMx->CCER &= ~tmp;
-
-  /* Set or reset the CCxNE Bit */ 
-  TIMx->CCER |= (uint32_t)(ChannelNState << Channel);
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_TIM_MODULE_ENABLED */
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_uart.c b/stmhal/hal/f4/src/stm32f4xx_hal_uart.c
deleted file mode 100644
index 350af3b770..0000000000
--- a/stmhal/hal/f4/src/stm32f4xx_hal_uart.c
+++ /dev/null
@@ -1,1954 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_uart.c
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   UART HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions  
-  *           + Peripheral State and Errors functions  
-  *           
-  @verbatim       
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-  [..]
-    The UART HAL driver can be used as follows:
-    
-    (#) Declare a UART_HandleTypeDef handle structure.
-  
-    (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
-        (##) Enable the USARTx interface clock.
-        (##) UART pins configuration:
-            (+++) Enable the clock for the UART GPIOs.
-            (+++) Configure these UART pins as alternate function pull-up.
-        (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
-             and HAL_UART_Receive_IT() APIs):
-            (+++) Configure the USARTx interrupt priority.
-            (+++) Enable the NVIC USART IRQ handle.
-        (##) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
-             and HAL_UART_Receive_DMA() APIs):
-            (+++) Declare a DMA handle structure for the Tx/Rx stream.
-            (+++) Enable the DMAx interface clock.
-            (+++) Configure the declared DMA handle structure with the required 
-                  Tx/Rx parameters.                
-            (+++) Configure the DMA Tx/Rx Stream.
-            (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
-            (+++) Configure the priority and enable the NVIC for the transfer complete 
-                  interrupt on the DMA Tx/Rx Stream.
-
-    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware 
-        flow control and Mode(Receiver/Transmitter) in the Init structure.
-
-    (#) For the UART asynchronous mode, initialize the UART registers by calling
-        the HAL_UART_Init() API.
-    
-    (#) For the UART Half duplex mode, initialize the UART registers by calling 
-        the HAL_HalfDuplex_Init() API.
-    
-    (#) For the LIN mode, initialize the UART registers by calling the HAL_LIN_Init() API.
-    
-    (#) For the Multi-Processor mode, initialize the UART registers by calling 
-        the HAL_MultiProcessor_Init() API.
-        
-     [..] 
-       (@) The specific UART interrupts (Transmission complete interrupt, 
-            RXNE interrupt and Error Interrupts) will be managed using the macros
-            __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit 
-            and receive process.
-          
-     [..] 
-       (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the 
-            low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized 
-            HAL_UART_MspInit() API.
-          
-     [..] 
-        Three operation modes are available within this driver :     
-  
-     *** Polling mode IO operation ***
-     =================================
-     [..]    
-       (+) Send an amount of data in blocking mode using HAL_UART_Transmit() 
-       (+) Receive an amount of data in blocking mode using HAL_UART_Receive()
-       
-     *** Interrupt mode IO operation ***    
-     ===================================
-     [..]    
-       (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT() 
-       (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can 
-            add his own code by customization of function pointer HAL_UART_TxCpltCallback
-       (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT() 
-       (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can 
-            add his own code by customization of function pointer HAL_UART_RxCpltCallback
-       (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can 
-            add his own code by customization of function pointer HAL_UART_ErrorCallback
-
-     *** DMA mode IO operation ***    
-     ==============================
-     [..] 
-       (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA() 
-       (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can 
-            add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback 
-       (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can 
-            add his own code by customization of function pointer HAL_UART_TxCpltCallback
-       (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA() 
-       (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can 
-            add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback 
-       (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can 
-            add his own code by customization of function pointer HAL_UART_RxCpltCallback
-       (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can 
-            add his own code by customization of function pointer HAL_UART_ErrorCallback
-       (+) Pause the DMA Transfer using HAL_UART_DMAPause()      
-       (+) Resume the DMA Transfer using HAL_UART_DMAResume()  
-       (+) Stop the DMA Transfer using HAL_UART_DMAStop()      
-    
-     *** UART HAL driver macros list ***
-     ============================================= 
-     [..]
-       Below the list of most used macros in UART HAL driver.
-       
-      (+) __HAL_UART_ENABLE: Enable the UART peripheral 
-      (+) __HAL_UART_DISABLE: Disable the UART peripheral     
-      (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not
-      (+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag
-      (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt
-      (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt
-      (+) __HAL_UART_GET_IT_SOURCE: Check whether the specified UART interrupt has occurred or not
-      
-     [..] 
-       (@) You can refer to the UART HAL driver header file for more useful macros 
-      
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup UART UART
-  * @brief HAL UART module driver
-  * @{
-  */
-#ifdef HAL_UART_MODULE_ENABLED
-    
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup UART_Private_Constants
-  * @{
-  */
-/**
-  * @}
-  */
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup UART_Private_Functions   UART Private Functions
-  * @{
-  */
-static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
-static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
-static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMAError(DMA_HandleTypeDef *hdma); 
-static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
-static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
-static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
-static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
-static void UART_SetConfig (UART_HandleTypeDef *huart);
-/**
-  * @}
-  */
-
-/* Exported functions ---------------------------------------------------------*/
-/** @defgroup UART_Exported_Functions UART Exported Functions
-  * @{
-  */
-
-/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions 
-  *  @brief    Initialization and Configuration functions 
-  *
-@verbatim    
-===============================================================================
-            ##### Initialization and Configuration functions #####
- ===============================================================================  
-    [..]
-    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy 
-    in asynchronous mode.
-      (+) For the asynchronous mode only these parameters can be configured: 
-        (++) Baud Rate
-        (++) Word Length 
-        (++) Stop Bit
-        (++) Parity: If the parity is enabled, then the MSB bit of the data written
-             in the data register is transmitted but is changed by the parity bit.
-             Depending on the frame length defined by the M bit (8-bits or 9-bits),
-             please refer to Reference manual for possible UART frame formats.           
-        (++) Hardware flow control
-        (++) Receiver/transmitter modes
-        (++) Over Sampling Method
-    [..]
-    The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs 
-    follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor
-    configuration procedures (details for the procedures are available in reference manual (RM0329)).
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the UART mode according to the specified parameters in
-  *         the UART_InitTypeDef and create the associated handle.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
-{
-  /* Check the UART handle allocation */
-  if(huart == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
-  { 
-    /* The hardware flow control is available only for USART1, USART2, USART3 and USART6 */
-    assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
-    assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
-  }
-  else
-  {
-    assert_param(IS_UART_INSTANCE(huart->Instance));
-  }
-  assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
-  assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
-  
-  if(huart->gState == HAL_UART_STATE_RESET)
-  {  
-    /* Allocate lock resource and initialize it */
-    huart->Lock = HAL_UNLOCKED;
-    /* Init the low level hardware */
-    HAL_UART_MspInit(huart);
-  }
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /* Disable the peripheral */
-  __HAL_UART_DISABLE(huart);
-  
-  /* Set the UART Communication parameters */
-  UART_SetConfig(huart);
-  
-  /* In asynchronous mode, the following bits must be kept cleared: 
-     - LINEN and CLKEN bits in the USART_CR2 register,
-     - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
-  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
-  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
-  
-  /* Enable the peripheral */
-  __HAL_UART_ENABLE(huart);
-  
-  /* Initialize the UART state */
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
-  huart->gState= HAL_UART_STATE_READY;
-  huart->RxState= HAL_UART_STATE_READY;
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the half-duplex mode according to the specified
-  *         parameters in the UART_InitTypeDef and create the associated handle.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
-{
-  /* Check the UART handle allocation */
-  if(huart == NULL)
-  {
-    return HAL_ERROR;
-  }
- 
-  /* Check the parameters */ 
-  assert_param(IS_UART_INSTANCE(huart->Instance));
-  assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
-  assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
-
-  if(huart->gState == HAL_UART_STATE_RESET)
-  { 
-    /* Allocate lock resource and initialize it */
-    huart->Lock = HAL_UNLOCKED;
-    /* Init the low level hardware */
-    HAL_UART_MspInit(huart);
-  }
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /* Disable the peripheral */
-  __HAL_UART_DISABLE(huart);
-  
-  /* Set the UART Communication parameters */
-  UART_SetConfig(huart);
-  
-  /* In half-duplex mode, the following bits must be kept cleared: 
-     - LINEN and CLKEN bits in the USART_CR2 register,
-     - SCEN and IREN bits in the USART_CR3 register.*/
-  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
-  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));
-  
-  /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
-  SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
- 
-  /* Enable the peripheral */
-  __HAL_UART_ENABLE(huart);
-  
-  /* Initialize the UART state*/
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
-  huart->gState= HAL_UART_STATE_READY;
-  huart->RxState= HAL_UART_STATE_READY;
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the LIN mode according to the specified
-  *         parameters in the UART_InitTypeDef and create the associated handle.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @param  BreakDetectLength: Specifies the LIN break detection length.
-  *         This parameter can be one of the following values:
-  *            @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection
-  *            @arg UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
-{
-  /* Check the UART handle allocation */
-  if(huart == NULL)
-  {
-    return HAL_ERROR;
-  }
-   
-  /* Check the parameters */
-  assert_param(IS_UART_INSTANCE(huart->Instance));
-  assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
-  assert_param(IS_UART_LIN_WORD_LENGTH(huart->Init.WordLength));
-  assert_param(IS_UART_LIN_OVERSAMPLING(huart->Init.OverSampling));
-  
-  if(huart->gState == HAL_UART_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    huart->Lock = HAL_UNLOCKED;
-    /* Init the low level hardware */
-    HAL_UART_MspInit(huart);
-  }
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /* Disable the peripheral */
-  __HAL_UART_DISABLE(huart);
-  
-  /* Set the UART Communication parameters */
-  UART_SetConfig(huart);
-  
-  /* In LIN mode, the following bits must be kept cleared: 
-     - LINEN and CLKEN bits in the USART_CR2 register,
-     - SCEN and IREN bits in the USART_CR3 register.*/
-  CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
-  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));
-  
-  /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
-  SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);
-  
-  /* Set the USART LIN Break detection length. */
-  CLEAR_BIT(huart->Instance->CR2, USART_CR2_LBDL);
-  SET_BIT(huart->Instance->CR2, BreakDetectLength);
-  
-  /* Enable the peripheral */
-  __HAL_UART_ENABLE(huart);
-  
-  /* Initialize the UART state*/
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
-  huart->gState= HAL_UART_STATE_READY;
-  huart->RxState= HAL_UART_STATE_READY;
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the Multi-Processor mode according to the specified
-  *         parameters in the UART_InitTypeDef and create the associated handle.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @param  Address: USART address
-  * @param  WakeUpMethod: specifies the USART wake-up method.
-  *          This parameter can be one of the following values:
-  *            @arg UART_WAKEUPMETHOD_IDLELINE: Wake-up by an idle line detection
-  *            @arg UART_WAKEUPMETHOD_ADDRESSMARK: Wake-up by an address mark
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
-{
-  /* Check the UART handle allocation */
-  if(huart == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_UART_INSTANCE(huart->Instance));
-  assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
-  assert_param(IS_UART_ADDRESS(Address));
-  assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
-  assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
-
-  if(huart->gState == HAL_UART_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    huart->Lock = HAL_UNLOCKED;
-    /* Init the low level hardware */
-    HAL_UART_MspInit(huart);
-  }
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /* Disable the peripheral */
-  __HAL_UART_DISABLE(huart);
-  
-  /* Set the UART Communication parameters */
-  UART_SetConfig(huart);
-  
-  /* In Multi-Processor mode, the following bits must be kept cleared: 
-     - LINEN and CLKEN bits in the USART_CR2 register,
-     - SCEN, HDSEL and IREN  bits in the USART_CR3 register */
-  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
-  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
-  
-  /* Clear the USART address */
-  CLEAR_BIT(huart->Instance->CR2, USART_CR2_ADD);
-  /* Set the USART address node */
-  SET_BIT(huart->Instance->CR2, Address);
-  
-  /* Set the wake up method by setting the WAKE bit in the CR1 register */
-  CLEAR_BIT(huart->Instance->CR1, USART_CR1_WAKE);
-  SET_BIT(huart->Instance->CR1, WakeUpMethod);
-  
-  /* Enable the peripheral */
-  __HAL_UART_ENABLE(huart);
-  
-  /* Initialize the UART state */
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
-  huart->gState= HAL_UART_STATE_READY;
-  huart->RxState= HAL_UART_STATE_READY;
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the UART peripheral. 
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
-{
-  /* Check the UART handle allocation */
-  if(huart == NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  /* Check the parameters */
-  assert_param(IS_UART_INSTANCE(huart->Instance));
-
-  huart->gState = HAL_UART_STATE_BUSY;
-  
-  /* DeInit the low level hardware */
-  HAL_UART_MspDeInit(huart);
-  
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
-  huart->gState = HAL_UART_STATE_RESET;
-  huart->RxState = HAL_UART_STATE_RESET;
-
-  /* Process Lock */
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  UART MSP Init.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval None
-  */
- __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
-{
-   /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_UART_MspInit could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  UART MSP DeInit.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval None
-  */
- __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_UART_MspDeInit could be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup UART_Exported_Functions_Group2 IO operation functions 
-  *  @brief UART Transmit and Receive functions 
-  *
-@verbatim   
-  ==============================================================================
-                      ##### IO operation functions #####
-  ==============================================================================  
-  [..]
-    This subsection provides a set of functions allowing to manage the UART asynchronous
-    and Half duplex data transfers.
-
-    (#) There are two modes of transfer:
-       (++) Blocking mode: The communication is performed in polling mode. 
-            The HAL status of all data processing is returned by the same function 
-            after finishing transfer.  
-       (++) Non blocking mode: The communication is performed using Interrupts 
-            or DMA, these APIs return the HAL status.
-            The end of the data processing will be indicated through the 
-            dedicated UART IRQ when using Interrupt mode or the DMA IRQ when 
-            using DMA mode.
-            The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks 
-            will be executed respectively at the end of the transmit or receive process.
-            The HAL_UART_ErrorCallback() user callback will be executed when 
-            a communication error is detected.
-
-    (#) Blocking mode APIs are:
-        (++) HAL_UART_Transmit()
-        (++) HAL_UART_Receive() 
-        
-    (#) Non Blocking mode APIs with Interrupt are:
-        (++) HAL_UART_Transmit_IT()
-        (++) HAL_UART_Receive_IT()
-        (++) HAL_UART_IRQHandler()
-
-    (#) Non Blocking mode functions with DMA are:
-        (++) HAL_UART_Transmit_DMA()
-        (++) HAL_UART_Receive_DMA()
-
-    (#) A set of Transfer Complete Callbacks are provided in non blocking mode:
-        (++) HAL_UART_TxCpltCallback()
-        (++) HAL_UART_RxCpltCallback()
-        (++) HAL_UART_ErrorCallback()
-
-    [..] 
-      (@) In the Half duplex communication, it is forbidden to run the transmit 
-          and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX 
-          can't be useful.
-      
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Sends an amount of data in blocking mode. 
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @param  Timeout: Timeout duration  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint16_t* tmp;
-  uint32_t tickstart = 0U;
-  
-  /* Check that a Tx process is not already ongoing */
-  if(huart->gState == HAL_UART_STATE_READY) 
-  {
-    if((pData == NULL ) || (Size == 0U)) 
-    {
-      return  HAL_ERROR;
-    }
-    
-    /* Process Locked */
-    __HAL_LOCK(huart);
-    
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
-    huart->gState = HAL_UART_STATE_BUSY_TX;
-	
-    /* Init tickstart for timeout managment */
-    tickstart = HAL_GetTick();
-
-    huart->TxXferSize = Size;
-    huart->TxXferCount = Size;
-    while(huart->TxXferCount > 0U)
-    {
-      huart->TxXferCount--;
-      if(huart->Init.WordLength == UART_WORDLENGTH_9B)
-      {
-        if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
-        { 
-          return HAL_TIMEOUT;
-        }
-        tmp = (uint16_t*) pData;
-        huart->Instance->DR = (*tmp & (uint16_t)0x01FFU);
-        if(huart->Init.Parity == UART_PARITY_NONE)
-        {
-          pData +=2U;
-        }
-        else
-        { 
-          pData +=1U;
-        }
-      } 
-      else
-      {
-        if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-        huart->Instance->DR = (*pData++ & (uint8_t)0xFFU);
-      } 
-    }
-    
-    if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
-    { 
-      return HAL_TIMEOUT;
-    }
-    
-    /* At end of Tx process, restore huart->gState to Ready */
-      huart->gState = HAL_UART_STATE_READY;
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(huart);
-    
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receives an amount of data in blocking mode. 
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be received
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{ 
-  uint16_t* tmp;
-  uint32_t tickstart = 0U;
-  
-  /* Check that a Rx process is not already ongoing */
-  if(huart->RxState == HAL_UART_STATE_READY) 
-  { 
-    if((pData == NULL ) || (Size == 0U)) 
-    {
-      return  HAL_ERROR;
-    }
-    
-    /* Process Locked */
-    __HAL_LOCK(huart);
-    
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
-    huart->RxState = HAL_UART_STATE_BUSY_RX;
-	
-    /* Init tickstart for timeout managment */
-    tickstart = HAL_GetTick();
-        
-    huart->RxXferSize = Size; 
-    huart->RxXferCount = Size;
-    
-    /* Check the remain data to be received */
-    while(huart->RxXferCount > 0U)
-    {
-      huart->RxXferCount--;
-      if(huart->Init.WordLength == UART_WORDLENGTH_9B)
-      {
-        if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
-        { 
-          return HAL_TIMEOUT;
-        }
-        tmp = (uint16_t*) pData;
-        if(huart->Init.Parity == UART_PARITY_NONE)
-        {
-          *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FFU);
-          pData +=2U;
-        }
-        else
-        {
-          *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FFU);
-          pData +=1U;
-        }
-
-      } 
-      else
-      {
-        if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
-        { 
-          return HAL_TIMEOUT;
-        }
-        if(huart->Init.Parity == UART_PARITY_NONE)
-        {
-          *pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FFU);
-        }
-        else
-        {
-          *pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007FU);
-        }
-        
-      }
-    }
-    
-    /* At end of Rx process, restore huart->RxState to Ready */
-    huart->RxState = HAL_UART_STATE_READY;
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(huart);
-    
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;   
-  }
-}
-
-/**
-  * @brief  Sends an amount of data in non blocking mode.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
-  /* Check that a Tx process is not already ongoing */
-  if(huart->gState == HAL_UART_STATE_READY)
-  {
-    if((pData == NULL ) || (Size == 0U)) 
-    {
-      return HAL_ERROR;
-    }
-    
-    /* Process Locked */
-    __HAL_LOCK(huart);
-    
-    huart->pTxBuffPtr = pData;
-    huart->TxXferSize = Size;
-    huart->TxXferCount = Size;
-
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
-    huart->gState = HAL_UART_STATE_BUSY_TX;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(huart);
-
-    /* Enable the UART Transmit data register empty Interrupt */
-    SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
-    
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;   
-  }
-}
-
-/**
-  * @brief  Receives an amount of data in non blocking mode 
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be received
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
-  /* Check that a Rx process is not already ongoing */ 
-  if(huart->RxState == HAL_UART_STATE_READY)
-  {
-    if((pData == NULL ) || (Size == 0U)) 
-    {
-      return HAL_ERROR;
-    }
-    
-    /* Process Locked */
-    __HAL_LOCK(huart);
-    
-    huart->pRxBuffPtr = pData;
-    huart->RxXferSize = Size;
-    huart->RxXferCount = Size;
-    
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
-    huart->RxState = HAL_UART_STATE_BUSY_RX;
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(huart);
-
-    /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
-    SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-    /* Enable the UART Parity Error and Data Register not empty Interrupts */
-    SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
-    
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY; 
-  }
-}
-
-/**
-  * @brief  Sends an amount of data in non blocking mode. 
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
-  uint32_t *tmp;
-  
-  /* Check that a Tx process is not already ongoing */
-  if(huart->gState == HAL_UART_STATE_READY)
-  {
-    if((pData == NULL ) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(huart);
-
-    huart->pTxBuffPtr = pData;
-    huart->TxXferSize = Size;
-    huart->TxXferCount = Size;
-
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
-    huart->gState = HAL_UART_STATE_BUSY_TX;
-
-    /* Set the UART DMA transfer complete callback */
-    huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
-
-    /* Set the UART DMA Half transfer complete callback */
-    huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
-
-    /* Set the DMA error callback */
-    huart->hdmatx->XferErrorCallback = UART_DMAError;
-
-    /* Set the DMA abort callback */
-    huart->hdmatx->XferAbortCallback = NULL;
-
-    /* Enable the UART transmit DMA Stream */
-    tmp = (uint32_t*)&pData;
-    HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t*)tmp, (uint32_t)&huart->Instance->DR, Size);
-    
-    /* Clear the TC flag in the SR register by writing 0 to it */
-    __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(huart);
-    
-    /* Enable the DMA transfer for transmit request by setting the DMAT bit
-       in the UART CR3 register */
-    SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-    
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receives an amount of data in non blocking mode. 
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be received
-  * @note   When the UART parity is enabled (PCE = 1) the data received contain the parity bit.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{  
-  uint32_t *tmp;
-  
-  /* Check that a Rx process is not already ongoing */
-  if(huart->RxState == HAL_UART_STATE_READY) 
-  {
-    if((pData == NULL ) || (Size == 0U)) 
-    {
-      return HAL_ERROR;
-    }
-    
-    /* Process Locked */
-    __HAL_LOCK(huart);
-    
-    huart->pRxBuffPtr = pData;
-    huart->RxXferSize = Size;
-    
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
-    huart->RxState = HAL_UART_STATE_BUSY_RX;
-        
-    /* Set the UART DMA transfer complete callback */
-    huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
-    
-    /* Set the UART DMA Half transfer complete callback */
-    huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
-    
-    /* Set the DMA error callback */
-    huart->hdmarx->XferErrorCallback = UART_DMAError;
-    
-    /* Set the DMA abort callback */
-    huart->hdmarx->XferAbortCallback = NULL;
-
-    /* Enable the DMA Stream */
-    tmp = (uint32_t*)&pData;
-    HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t*)tmp, Size); 
-
-    /* Enable the UART Parity Error Interrupt */
-    SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
-
-    /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
-    SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
-    
-    /* Enable the DMA transfer for the receiver request by setting the DMAR bit 
-    in the UART CR3 register */
-    SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(huart);
-    
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY; 
-  }
-}
-    
-/**
-  * @brief Pauses the DMA Transfer.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
-{
-   uint32_t dmarequest = 0x00U;
-
-  /* Process Locked */
-  __HAL_LOCK(huart);
-  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
-  if((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
-  {
-    /* Disable the UART DMA Tx request */
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-  }
-  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
-  if((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
-  {
-    /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-    CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-    
-    /* Disable the UART DMA Rx request */
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-  }
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-  
-  return HAL_OK; 
-}
-
-/**
-  * @brief Resumes the DMA Transfer.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
-{
-  /* Process Locked */
-  __HAL_LOCK(huart);
-  
-  if(huart->gState == HAL_UART_STATE_BUSY_TX)
-  {
-    /* Enable the UART DMA Tx request */
-    SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-  }
-  if(huart->RxState == HAL_UART_STATE_BUSY_RX)
-  {
-    /* Clear the Overrun flag before resuming the Rx transfer*/
-    __HAL_UART_CLEAR_OREFLAG(huart);
-    
-    /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
-    SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
-    SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
-    
-    /* Enable the UART DMA Rx request */
-    SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-  }
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief Stops the DMA Transfer.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
-{
-  uint32_t dmarequest = 0x00U;
-  /* The Lock is not implemented on this API to allow the user application
-     to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback():
-     when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
-     and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback()
-     */
-  
-  /* Stop UART DMA Tx request if ongoing */
-  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
-  if((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
-  {
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
-    /* Abort the UART DMA Tx channel */
-    if(huart->hdmatx != NULL)
-    {
-      HAL_DMA_Abort(huart->hdmatx);
-    }
-    UART_EndTxTransfer(huart);
-  }
-
-  /* Stop UART DMA Rx request if ongoing */
-  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
-  if((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
-  {
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
-    /* Abort the UART DMA Rx channel */
-    if(huart->hdmarx != NULL)
-    {
-      HAL_DMA_Abort(huart->hdmarx);
-    }
-    UART_EndRxTransfer(huart);
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles UART interrupt request.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval None
-  */
-void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
-{
-   uint32_t isrflags   = READ_REG(huart->Instance->SR);
-   uint32_t cr1its     = READ_REG(huart->Instance->CR1);
-   uint32_t cr3its     = READ_REG(huart->Instance->CR3);
-   uint32_t errorflags = 0x00U;
-   uint32_t dmarequest = 0x00U;
-
-  /* If no error occurs */
-  errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
-  if(errorflags == RESET)
-  {
-    /* UART in mode Receiver -------------------------------------------------*/
-    if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
-    {
-      UART_Receive_IT(huart);
-      return;
-    }
-  }
-
-  /* If some errors occur */
-  if((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
-  {
-    /* UART parity error interrupt occurred ----------------------------------*/
-    if(((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
-    {
-      huart->ErrorCode |= HAL_UART_ERROR_PE;
-    }
-    
-    /* UART noise error interrupt occurred -----------------------------------*/
-    if(((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
-    {
-      huart->ErrorCode |= HAL_UART_ERROR_NE;
-    }
-    
-    /* UART frame error interrupt occurred -----------------------------------*/
-    if(((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
-    {
-      huart->ErrorCode |= HAL_UART_ERROR_FE;
-    }
-    
-    /* UART Over-Run interrupt occurred --------------------------------------*/
-    if(((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
-    { 
-      huart->ErrorCode |= HAL_UART_ERROR_ORE;
-    }
-
-    /* Call UART Error Call back function if need be --------------------------*/    
-    if(huart->ErrorCode != HAL_UART_ERROR_NONE)
-    {
-      /* UART in mode Receiver -----------------------------------------------*/
-      if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
-      {
-        UART_Receive_IT(huart);
-      }
-
-      /* If Overrun error occurs, or if any error occurs in DMA mode reception,
-         consider error as blocking */
-      dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
-      if(((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest)
-      {
-        /* Blocking error : transfer is aborted
-           Set the UART state ready to be able to start again the process,
-           Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
-        UART_EndRxTransfer(huart);
-        
-        /* Disable the UART DMA Rx request if enabled */
-        if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
-        {
-          CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-          
-          /* Abort the UART DMA Rx channel */
-          if(huart->hdmarx != NULL)
-          {
-            /* Set the UART DMA Abort callback : 
-               will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
-            huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
-            if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
-            {
-              /* Call Directly XferAbortCallback function in case of error */
-              huart->hdmarx->XferAbortCallback(huart->hdmarx);
-            }
-          }
-          else
-          {
-            /* Call user error callback */
-            HAL_UART_ErrorCallback(huart);
-          }
-        }
-        else
-        {
-          /* Call user error callback */
-          HAL_UART_ErrorCallback(huart);
-        }
-      }
-      else
-      {
-        /* Non Blocking error : transfer could go on. 
-           Error is notified to user through user error callback */
-        HAL_UART_ErrorCallback(huart);
-        huart->ErrorCode = HAL_UART_ERROR_NONE;
-      }
-    }
-    return;
-  } /* End if some error occurs */
-
-  /* UART in mode Transmitter ------------------------------------------------*/
-  if(((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
-  {
-    UART_Transmit_IT(huart);
-    return;
-  }
-  
-  /* UART in mode Transmitter end --------------------------------------------*/
-  if(((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
-  {
-    UART_EndTransmit_IT(huart);
-    return;
-  }
-}
-
-/**
-  * @brief  Tx Transfer completed callbacks.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval None
-  */
- __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_UART_TxCpltCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  Tx Half Transfer completed callbacks.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval None
-  */
- __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_UART_TxCpltCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  Rx Transfer completed callbacks.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval None
-  */
-__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_UART_TxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Rx Half Transfer completed callbacks.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval None
-  */
-__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_UART_TxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  UART error callbacks.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval None
-  */
- __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart); 
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_UART_ErrorCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions 
-  *  @brief   UART control functions 
-  *
-@verbatim   
-  ==============================================================================
-                      ##### Peripheral Control functions #####
-  ==============================================================================  
-  [..]
-    This subsection provides a set of functions allowing to control the UART:
-    (+) HAL_LIN_SendBreak() API can be helpful to transmit the break character.
-    (+) HAL_MultiProcessor_EnterMuteMode() API can be helpful to enter the UART in mute mode. 
-    (+) HAL_MultiProcessor_ExitMuteMode() API can be helpful to exit the UART mute mode by software.
-    
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Transmits break characters.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
-{
-  /* Check the parameters */
-  assert_param(IS_UART_INSTANCE(huart->Instance));
-  
-  /* Process Locked */
-  __HAL_LOCK(huart);
-  
-  huart->gState = HAL_UART_STATE_BUSY;
-  
-  /* Send break characters */
-  SET_BIT(huart->Instance->CR1, USART_CR1_SBK);
- 
-  huart->gState = HAL_UART_STATE_READY;
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-  
-  return HAL_OK; 
-}
-
-/**
-  * @brief  Enters the UART in mute mode. 
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
-{
-  /* Check the parameters */
-  assert_param(IS_UART_INSTANCE(huart->Instance));
-  
-  /* Process Locked */
-  __HAL_LOCK(huart);
-  
-  huart->gState = HAL_UART_STATE_BUSY;
-  
-  /* Enable the USART mute mode  by setting the RWU bit in the CR1 register */
-  SET_BIT(huart->Instance->CR1, USART_CR1_RWU);
-  
-  huart->gState = HAL_UART_STATE_READY;
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-  
-  return HAL_OK; 
-}
-
-/**
-  * @brief  Exits the UART mute mode: wake up software. 
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart)
-{
-  /* Check the parameters */
-  assert_param(IS_UART_INSTANCE(huart->Instance));
-  
-  /* Process Locked */
-  __HAL_LOCK(huart);
-  
-  huart->gState = HAL_UART_STATE_BUSY;
-  
-  /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */
-  CLEAR_BIT(huart->Instance->CR1, USART_CR1_RWU);
-  
-  huart->gState = HAL_UART_STATE_READY;
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-  
-  return HAL_OK; 
-}
-
-/**
-  * @brief  Enables the UART transmitter and disables the UART receiver.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
-{
-  uint32_t tmpreg = 0x00U;
-
-  /* Process Locked */
-  __HAL_LOCK(huart);
-  
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /*-------------------------- USART CR1 Configuration -----------------------*/
-  tmpreg = huart->Instance->CR1;
-  
-  /* Clear TE and RE bits */
-  tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE));
-  
-  /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
-  tmpreg |= (uint32_t)USART_CR1_TE;
-  
-  /* Write to USART CR1 */
-  WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg);
- 
-  huart->gState = HAL_UART_STATE_READY;
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-  
-  return HAL_OK; 
-}
-
-/**
-  * @brief  Enables the UART receiver and disables the UART transmitter.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
-{
-  uint32_t tmpreg = 0x00U;
-
-  /* Process Locked */
-  __HAL_LOCK(huart);
-  
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /*-------------------------- USART CR1 Configuration -----------------------*/
-  tmpreg = huart->Instance->CR1;
-  
-  /* Clear TE and RE bits */
-  tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE));
-  
-  /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
-  tmpreg |= (uint32_t)USART_CR1_RE;
-  
-  /* Write to USART CR1 */
-  WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg);
-  
-  huart->gState = HAL_UART_STATE_READY;
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-  
-  return HAL_OK; 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Errors functions 
-  *  @brief   UART State and Errors functions 
-  *
-@verbatim   
-  ==============================================================================
-                 ##### Peripheral State and Errors functions #####
-  ==============================================================================  
- [..]
-   This subsection provides a set of functions allowing to return the State of 
-   UART communication process, return Peripheral Errors occurred during communication 
-   process
-   (+) HAL_UART_GetState() API can be helpful to check in run-time the state of the UART peripheral.
-   (+) HAL_UART_GetError() check in run-time errors that could be occurred during communication. 
-
-@endverbatim
-  * @{
-  */
-  
-/**
-  * @brief  Returns the UART state.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL state
-  */
-HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
-{
-  uint32_t temp1= 0x00U, temp2 = 0x00U;
-  temp1 = huart->gState;
-  temp2 = huart->RxState;
-  
-  return (HAL_UART_StateTypeDef)(temp1 | temp2);
-}
-
-/**
-  * @brief  Return the UART error code
-  * @param  huart : pointer to a UART_HandleTypeDef structure that contains
-  *              the configuration information for the specified UART.
-  * @retval UART Error Code
-  */
-uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
-{
-  return huart->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @brief  DMA UART transmit process complete callback. 
-  * @param  hdma: DMA handle
-  * @retval None
-  */
-static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  /* DMA Normal mode*/
-  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
-  {
-    huart->TxXferCount = 0U;
-
-    /* Disable the DMA transfer for transmit request by setting the DMAT bit
-       in the UART CR3 register */
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
-    /* Enable the UART Transmit Complete Interrupt */
-    SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
-
-  }
-  /* DMA Circular mode */
-  else
-  {
-    HAL_UART_TxCpltCallback(huart);
-  }
-}
-
-/**
-  * @brief DMA UART transmit process half complete callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  HAL_UART_TxHalfCpltCallback(huart);
-}
-
-/**
-  * @brief  DMA UART receive process complete callback. 
-  * @param  hdma: DMA handle
-  * @retval None
-  */
-static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  /* DMA Normal mode*/
-  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
-  {
-    huart->RxXferCount = 0U;
-  
-    /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-    CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-    
-    /* Disable the DMA transfer for the receiver request by setting the DMAR bit 
-       in the UART CR3 register */
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-	
-    /* At end of Rx process, restore huart->RxState to Ready */
-    huart->RxState = HAL_UART_STATE_READY;
-  }
-  HAL_UART_RxCpltCallback(huart);
-}
-
-/**
-  * @brief DMA UART receive process half complete callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  HAL_UART_RxHalfCpltCallback(huart); 
-}
-
-/**
-  * @brief  DMA UART communication error callback.
-  * @param  hdma: DMA handle
-  * @retval None
-  */
-static void UART_DMAError(DMA_HandleTypeDef *hdma)
-{
-  uint32_t dmarequest = 0x00U;
-  UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  /* Stop UART DMA Tx request if ongoing */
-  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
-  if((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
-  {
-    huart->TxXferCount = 0U;
-    UART_EndTxTransfer(huart);
-  }
-
-  /* Stop UART DMA Rx request if ongoing */
-  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 
-  if((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
-  {
-    huart->RxXferCount = 0U;
-    UART_EndRxTransfer(huart);
-  }
-
-  huart->ErrorCode |= HAL_UART_ERROR_DMA;
-  HAL_UART_ErrorCallback(huart);
-}
-
-/**
-  * @brief  This function handles UART Communication Timeout.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @param  Flag: specifies the UART flag to check.
-  * @param  Status: The new Flag status (SET or RESET).
-  * @param  Tickstart Tick start value
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
-{
-  /* Wait until flag is set */
-  while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 
-  {
-    /* Check for the Timeout */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
-      {
-        /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
-        CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
-        CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-        
-        huart->gState  = HAL_UART_STATE_READY;
-        huart->RxState = HAL_UART_STATE_READY;
-        
-        /* Process Unlocked */
-        __HAL_UNLOCK(huart);
-        
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
-  * @param  huart: UART handle.
-  * @retval None
-  */
-static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
-{
-  /* Disable TXEIE and TCIE interrupts */
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
-  /* At end of Tx process, restore huart->gState to Ready */
-  huart->gState = HAL_UART_STATE_READY;
-}
-
-/**
-  * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
-  * @param  huart: UART handle.
-  * @retval None
-  */
-static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
-{
-  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
-  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-  /* At end of Rx process, restore huart->RxState to Ready */
-  huart->RxState = HAL_UART_STATE_READY;
-}
-
-/**
-  * @brief  DMA UART communication abort callback, when initiated by HAL services on Error
-  *         (To be called at end of DMA Abort procedure following error occurrence).
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  huart->RxXferCount = 0;
-  huart->TxXferCount = 0;
-
-  HAL_UART_ErrorCallback(huart);
-}
-
-/**
-  * @brief  Sends an amount of data in non blocking mode.
-  * @param  huart: Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
-{
-  uint16_t* tmp;
-  
-  /* Check that a Tx process is ongoing */
-  if(huart->gState == HAL_UART_STATE_BUSY_TX)
-  {
-    if(huart->Init.WordLength == UART_WORDLENGTH_9B)
-    {
-      tmp = (uint16_t*) huart->pTxBuffPtr;
-      huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FFU);
-      if(huart->Init.Parity == UART_PARITY_NONE)
-      {
-        huart->pTxBuffPtr += 2U;
-      }
-      else
-      {
-        huart->pTxBuffPtr += 1U;
-      }
-    } 
-    else
-    {
-      huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FFU);
-    }
-
-    if(--huart->TxXferCount == 0U)
-    {
-      /* Disable the UART Transmit Complete Interrupt */
-      CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
-
-      /* Enable the UART Transmit Complete Interrupt */    
-      SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
-    }
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Wraps up transmission in non blocking mode.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
-{
-  /* Disable the UART Transmit Complete Interrupt */    
-  CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
-  
-  /* Tx process is ended, restore huart->gState to Ready */
-  huart->gState = HAL_UART_STATE_READY;
-    
-  HAL_UART_TxCpltCallback(huart);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Receives an amount of data in non blocking mode 
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
-{
-  uint16_t* tmp;
-  
-  /* Check that a Rx process is ongoing */
-  if(huart->RxState == HAL_UART_STATE_BUSY_RX) 
-  {
-    if(huart->Init.WordLength == UART_WORDLENGTH_9B)
-    {
-      tmp = (uint16_t*) huart->pRxBuffPtr;
-      if(huart->Init.Parity == UART_PARITY_NONE)
-      {
-        *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FFU);
-        huart->pRxBuffPtr += 2U;
-      }
-      else
-      {
-        *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FFU);
-        huart->pRxBuffPtr += 1U;
-      }
-    }
-    else
-    {
-      if(huart->Init.Parity == UART_PARITY_NONE)
-      {
-        *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FFU);
-      }
-      else
-      {
-        *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007FU);
-      }
-    }
-
-    if(--huart->RxXferCount == 0U)
-    {
-      /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
-      CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
-
-      /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
-      CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-      /* Rx process is completed, restore huart->RxState to Ready */
-      huart->RxState = HAL_UART_STATE_READY;
-     
-      HAL_UART_RxCpltCallback(huart);
-
-      return HAL_OK;
-    }
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Configures the UART peripheral. 
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval None
-  */
-static void UART_SetConfig(UART_HandleTypeDef *huart)
-{
-  uint32_t tmpreg = 0x00U;
-  
-  /* Check the parameters */
-  assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
-  assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
-  assert_param(IS_UART_PARITY(huart->Init.Parity));
-  assert_param(IS_UART_MODE(huart->Init.Mode));
-
-  /*-------------------------- USART CR2 Configuration -----------------------*/
-  tmpreg = huart->Instance->CR2;
-
-  /* Clear STOP[13:12] bits */
-  tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP);
-
-  /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */
-  tmpreg |= (uint32_t)huart->Init.StopBits;
-  
-  /* Write to USART CR2 */
-  WRITE_REG(huart->Instance->CR2, (uint32_t)tmpreg);
-
-  /*-------------------------- USART CR1 Configuration -----------------------*/
-  tmpreg = huart->Instance->CR1;
-
-  /* Clear M, PCE, PS, TE and RE bits */
-  tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
-                                   USART_CR1_RE | USART_CR1_OVER8));
-
-  /* Configure the UART Word Length, Parity and mode: 
-     Set the M bits according to huart->Init.WordLength value 
-     Set PCE and PS bits according to huart->Init.Parity value
-     Set TE and RE bits according to huart->Init.Mode value
-     Set OVER8 bit according to huart->Init.OverSampling value */
-  tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
-  
-  /* Write to USART CR1 */
-  WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg);
-  
-  /*-------------------------- USART CR3 Configuration -----------------------*/  
-  tmpreg = huart->Instance->CR3;
-  
-  /* Clear CTSE and RTSE bits */
-  tmpreg &= (uint32_t)~((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE));
-  
-  /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
-  tmpreg |= huart->Init.HwFlowCtl;
-  
-  /* Write to USART CR3 */
-  WRITE_REG(huart->Instance->CR3, (uint32_t)tmpreg);
-  
-  /* Check the Over Sampling */
-  if(huart->Init.OverSampling == UART_OVERSAMPLING_8)
-  {
-    /*-------------------------- USART BRR Configuration ---------------------*/
-    if((huart->Instance == USART1) || (huart->Instance == USART6))
-    {
-      huart->Instance->BRR = UART_BRR_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
-    }
-    else
-    {
-      huart->Instance->BRR = UART_BRR_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
-    }
-  }
-  else
-  {
-    /*-------------------------- USART BRR Configuration ---------------------*/
-    if((huart->Instance == USART1) || (huart->Instance == USART6))
-    {
-      huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
-    }
-    else
-    {
-      huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
-    }
-  }
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_UART_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/src/stm32f4xx_ll_sdmmc.c b/stmhal/hal/f4/src/stm32f4xx_ll_sdmmc.c
deleted file mode 100644
index cf5997676c..0000000000
--- a/stmhal/hal/f4/src/stm32f4xx_ll_sdmmc.c
+++ /dev/null
@@ -1,511 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_ll_sdmmc.c
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   SDMMC Low Layer HAL module driver.
-  *    
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the SDMMC peripheral:
-  *           + Initialization/de-initialization functions
-  *           + I/O operation functions
-  *           + Peripheral Control functions 
-  *           + Peripheral State functions
-  *         
-  @verbatim
-  ==============================================================================
-                       ##### SDMMC peripheral features #####
-  ==============================================================================        
-    [..] The SD/SDIO MMC card host interface (SDIO) provides an interface between the APB2
-         peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDIO cards and CE-ATA
-         devices.
-
-    [..] The SDIO features include the following:
-         (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support
-             for three different databus modes: 1-bit (default), 4-bit and 8-bit
-         (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility)
-         (+) Full compliance with SD Memory Card Specifications Version 2.0
-         (+) Full compliance with SD I/O Card Specification Version 2.0: card support for two
-             different data bus modes: 1-bit (default) and 4-bit
-         (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol
-             Rev1.1)
-         (+) Data transfer up to 48 MHz for the 8 bit mode
-         (+) Data and command output enable signals to control external bidirectional drivers.
-                 
-   
-                           ##### How to use this driver #####
-  ==============================================================================
-    [..]
-      This driver is a considered as a driver of service for external devices drivers 
-      that interfaces with the SDIO peripheral.
-      According to the device used (SD card/ MMC card / SDIO card ...), a set of APIs 
-      is used in the device's driver to perform SDIO operations and functionalities.
-   
-      This driver is almost transparent for the final user, it is only used to implement other
-      functionalities of the external device.
-   
-    [..]
-      (+) The SDIO clock (SDIOCLK = 48 MHz) is coming from a specific output of PLL 
-          (PLL48CLK). Before start working with SDIO peripheral make sure that the
-          PLL is well configured.
-          The SDIO peripheral uses two clock signals:
-          (++) SDIO adapter clock (SDIOCLK = 48 MHz)
-          (++) APB2 bus clock (PCLK2)
-       
-          -@@- PCLK2 and SDIO_CK clock frequencies must respect the following condition:
-               Frequency(PCLK2) >= (3 / 8 x Frequency(SDIO_CK))
-  
-      (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDIO
-          peripheral.
-
-      (+) Enable the Power ON State using the SDIO_PowerState_ON(SDIOx) 
-          function and disable it using the function SDIO_PowerState_OFF(SDIOx).
-                
-      (+) Enable/Disable the clock using the __SDIO_ENABLE()/__SDIO_DISABLE() macros.
-  
-      (+) Enable/Disable the peripheral interrupts using the macros __SDIO_ENABLE_IT(hsdio, IT) 
-          and __SDIO_DISABLE_IT(hsdio, IT) if you need to use interrupt mode. 
-  
-      (+) When using the DMA mode 
-          (++) Configure the DMA in the MSP layer of the external device
-          (++) Active the needed channel Request 
-          (++) Enable the DMA using __SDIO_DMA_ENABLE() macro or Disable it using the macro
-               __SDIO_DMA_DISABLE().
-  
-      (+) To control the CPSM (Command Path State Machine) and send 
-          commands to the card use the SDIO_SendCommand(SDIOx), 
-          SDIO_GetCommandResponse() and SDIO_GetResponse() functions. First, user has
-          to fill the command structure (pointer to SDIO_CmdInitTypeDef) according 
-          to the selected command to be sent.
-          The parameters that should be filled are:
-           (++) Command Argument
-           (++) Command Index
-           (++) Command Response type
-           (++) Command Wait
-           (++) CPSM Status (Enable or Disable).
-  
-          -@@- To check if the command is well received, read the SDIO_CMDRESP
-              register using the SDIO_GetCommandResponse().
-              The SDIO responses registers (SDIO_RESP1 to SDIO_RESP2), use the
-              SDIO_GetResponse() function.
-  
-      (+) To control the DPSM (Data Path State Machine) and send/receive 
-           data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(), 
-          SDIO_ReadFIFO(), DIO_WriteFIFO() and SDIO_GetFIFOCount() functions.
-  
-    *** Read Operations ***
-    =======================
-    [..]
-      (#) First, user has to fill the data structure (pointer to
-          SDIO_DataInitTypeDef) according to the selected data type to be received.
-          The parameters that should be filled are:
-           (++) Data Timeout
-           (++) Data Length
-           (++) Data Block size
-           (++) Data Transfer direction: should be from card (To SDIO)
-           (++) Data Transfer mode
-           (++) DPSM Status (Enable or Disable)
-                                     
-      (#) Configure the SDIO resources to receive the data from the card
-          according to selected transfer mode (Refer to Step 8, 9 and 10).
-  
-      (#) Send the selected Read command (refer to step 11).
-                    
-      (#) Use the SDIO flags/interrupts to check the transfer status.
-  
-    *** Write Operations ***
-    ========================
-    [..]
-     (#) First, user has to fill the data structure (pointer to
-         SDIO_DataInitTypeDef) according to the selected data type to be received.
-         The parameters that should be filled are:
-          (++) Data Timeout
-          (++) Data Length
-          (++) Data Block size
-          (++) Data Transfer direction:  should be to card (To CARD)
-          (++) Data Transfer mode
-          (++) DPSM Status (Enable or Disable)
-  
-     (#) Configure the SDIO resources to send the data to the card according to 
-         selected transfer mode.
-                     
-     (#) Send the selected Write command.
-                    
-     (#) Use the SDIO flags/interrupts to check the transfer status.
-  
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup SDMMC_LL SDMMC Low Layer
-  * @brief Low layer module for SD and MMC driver
-  * @{
-  */
-
-#if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED)
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
-    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
-    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
-    defined(STM32F412Rx) || defined(STM32F412Cx)
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup SDMMC_LL_Exported_Functions SDMMC_LL Exported Functions
-  * @{
-  */
-
-/** @defgroup HAL_SDMMC_LL_Group1 Initialization/de-initialization functions 
- *  @brief    Initialization and Configuration functions 
- *
-@verbatim    
- ===============================================================================
-              ##### Initialization/de-initialization functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
- 
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the SDIO according to the specified
-  *         parameters in the SDIO_InitTypeDef and create the associated handle.
-  * @param  SDIOx: Pointer to SDIO register base
-  * @param  Init: SDIO initialization structure   
-  * @retval HAL status
-  */
-HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init)
-{
-  uint32_t tmpreg = 0U; 
-
-  /* Check the parameters */
-  assert_param(IS_SDIO_ALL_INSTANCE(SDIOx));
-  assert_param(IS_SDIO_CLOCK_EDGE(Init.ClockEdge)); 
-  assert_param(IS_SDIO_CLOCK_BYPASS(Init.ClockBypass));
-  assert_param(IS_SDIO_CLOCK_POWER_SAVE(Init.ClockPowerSave));
-  assert_param(IS_SDIO_BUS_WIDE(Init.BusWide));
-  assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl));
-  assert_param(IS_SDIO_CLKDIV(Init.ClockDiv));
-  
-  /* Set SDIO configuration parameters */
-  tmpreg |= (Init.ClockEdge           |\
-             Init.ClockBypass         |\
-             Init.ClockPowerSave      |\
-             Init.BusWide             |\
-             Init.HardwareFlowControl |\
-             Init.ClockDiv
-             ); 
-  
-  /* Write to SDIO CLKCR */
-  MODIFY_REG(SDIOx->CLKCR, CLKCR_CLEAR_MASK, tmpreg);  
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SDMMC_LL_Group2 I/O operation functions 
- *  @brief   Data transfers functions 
- *
-@verbatim   
- ===============================================================================
-                      ##### I/O operation functions #####
- ===============================================================================  
-    [..]
-    This subsection provides a set of functions allowing to manage the SDIO data 
-    transfers.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Read data (word) from Rx FIFO in blocking mode (polling) 
-  * @param  SDIOx: Pointer to SDIO register base
-  * @retval HAL status
-  */
-uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx)
-{
-  /* Read data from Rx FIFO */ 
-  return (SDIOx->FIFO);
-}
-
-/**
-  * @brief  Write data (word) to Tx FIFO in blocking mode (polling) 
-  * @param  SDIOx: Pointer to SDIO register base
-  * @param  pWriteData: pointer to data to write
-  * @retval HAL status
-  */
-HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData)
-{ 
-  /* Write data to FIFO */ 
-  SDIOx->FIFO = *pWriteData;
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions 
- *  @brief   management functions 
- *
-@verbatim   
- ===============================================================================
-                      ##### Peripheral Control functions #####
- ===============================================================================  
-    [..]
-    This subsection provides a set of functions allowing to control the SDIO data 
-    transfers.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Set SDIO Power state to ON. 
-  * @param  SDIOx: Pointer to SDIO register base
-  * @retval HAL status
-  */
-HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx)
-{  
-  /* Set power state to ON */ 
-  SDIOx->POWER = SDIO_POWER_PWRCTRL;
-  
-  return HAL_OK; 
-}
-
-/**
-  * @brief  Set SDIO Power state to OFF. 
-  * @param  SDIOx: Pointer to SDIO register base
-  * @retval HAL status
-  */
-HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx)
-{
-  /* Set power state to OFF */
-  SDIOx->POWER = (uint32_t)0x00000000U;
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Get SDIO Power state. 
-  * @param  SDIOx: Pointer to SDIO register base
-  * @retval Power status of the controller. The returned value can be one of the 
-  *         following values:
-  *            - 0x00: Power OFF
-  *            - 0x02: Power UP
-  *            - 0x03: Power ON 
-  */
-uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx)  
-{
-  return (SDIOx->POWER & SDIO_POWER_PWRCTRL);
-}
-
-/**
-  * @brief  Configure the SDIO command path according to the specified parameters in
-  *         SDIO_CmdInitTypeDef structure and send the command 
-  * @param  SDIOx: Pointer to SDIO register base
-  * @param  SDIO_CmdInitStruct: pointer to a SDIO_CmdInitTypeDef structure that contains 
-  *         the configuration information for the SDIO command
-  * @retval HAL status
-  */
-HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
-{
-  uint32_t tmpreg = 0U;
-  
-  /* Check the parameters */
-  assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->CmdIndex));
-  assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->Response));
-  assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->WaitForInterrupt));
-  assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->CPSM));
-
-  /* Set the SDIO Argument value */
-  SDIOx->ARG = SDIO_CmdInitStruct->Argument;
-
-  /* Set SDIO command parameters */
-  tmpreg |= (uint32_t)(SDIO_CmdInitStruct->CmdIndex         |\
-                       SDIO_CmdInitStruct->Response         |\
-                       SDIO_CmdInitStruct->WaitForInterrupt |\
-                       SDIO_CmdInitStruct->CPSM);
-  
-  /* Write to SDIO CMD register */
-  MODIFY_REG(SDIOx->CMD, CMD_CLEAR_MASK, tmpreg); 
-  
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Return the command index of last command for which response received
-  * @param  SDIOx: Pointer to SDIO register base
-  * @retval Command index of the last command response received
-  */
-uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx)
-{
-  return (uint8_t)(SDIOx->RESPCMD);
-}
-
-
-/**
-  * @brief  Return the response received from the card for the last command
-  * @param  SDIO_RESP: Specifies the SDIO response register. 
-  *          This parameter can be one of the following values:
-  *            @arg SDIO_RESP1: Response Register 1
-  *            @arg SDIO_RESP2: Response Register 2
-  *            @arg SDIO_RESP3: Response Register 3
-  *            @arg SDIO_RESP4: Response Register 4  
-  * @retval The Corresponding response register value
-  */
-uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
-{
-  __IO uint32_t tmp = 0U;
-
-  /* Check the parameters */
-  assert_param(IS_SDIO_RESP(SDIO_RESP));
-
-  /* Get the response */
-  tmp = SDIO_RESP_ADDR + SDIO_RESP;
-  
-  return (*(__IO uint32_t *) tmp);
-}  
-
-/**
-  * @brief  Configure the SDIO data path according to the specified 
-  *         parameters in the SDIO_DataInitTypeDef.
-  * @param  SDIOx: Pointer to SDIO register base  
-  * @param  SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure 
-  *         that contains the configuration information for the SDIO command.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDIO_DataInitStruct)
-{
-  uint32_t tmpreg = 0U;
-  
-  /* Check the parameters */
-  assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->DataLength));
-  assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->DataBlockSize));
-  assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->TransferDir));
-  assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->TransferMode));
-  assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->DPSM));
-
-  /* Set the SDIO Data Timeout value */
-  SDIOx->DTIMER = SDIO_DataInitStruct->DataTimeOut;
-
-  /* Set the SDIO DataLength value */
-  SDIOx->DLEN = SDIO_DataInitStruct->DataLength;
-
-  /* Set the SDIO data configuration parameters */
-  tmpreg |= (uint32_t)(SDIO_DataInitStruct->DataBlockSize |\
-                       SDIO_DataInitStruct->TransferDir   |\
-                       SDIO_DataInitStruct->TransferMode  |\
-                       SDIO_DataInitStruct->DPSM);
-  
-  /* Write to SDIO DCTRL */
-  MODIFY_REG(SDIOx->DCTRL, DCTRL_CLEAR_MASK, tmpreg);
-
-  return HAL_OK;
-
-}
-
-/**
-  * @brief  Returns number of remaining data bytes to be transferred.
-  * @param  SDIOx: Pointer to SDIO register base
-  * @retval Number of remaining data bytes to be transferred
-  */
-uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx)
-{
-  return (SDIOx->DCOUNT);
-}
-
-/**
-  * @brief  Get the FIFO data
-  * @param  SDIOx: Pointer to SDIO register base 
-  * @retval Data received
-  */
-uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx)
-{
-  return (SDIOx->FIFO);
-}
-
-
-/**
-  * @brief  Sets one of the two options of inserting read wait interval.
-  * @param  SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
-  *          This parameter can be:
-  *            @arg SDIO_READ_WAIT_MODE_CLK: Read Wait control by stopping SDIOCLK
-  *            @arg SDIO_READ_WAIT_MODE_DATA2: Read Wait control using SDIO_DATA2
-  * @retval None
-  */
-HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
-{
-  /* Check the parameters */
-  assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
-  
-  *(__IO uint32_t *)DCTRL_RWMOD_BB = SDIO_ReadWaitMode;
-  
-  return HAL_OK;  
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
-          STM32F412Rx || STM32F412Cx */
-#endif /* (HAL_SD_MODULE_ENABLED) || (HAL_MMC_MODULE_ENABLED) */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f4/src/stm32f4xx_ll_usb.c b/stmhal/hal/f4/src/stm32f4xx_ll_usb.c
deleted file mode 100644
index 93ba19fcf1..0000000000
--- a/stmhal/hal/f4/src/stm32f4xx_ll_usb.c
+++ /dev/null
@@ -1,1710 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_ll_usb.c
-  * @author  MCD Application Team
-  * @version V1.5.2
-  * @date    22-September-2016
-  * @brief   USB Low Layer HAL module driver.
-  *    
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the USB Peripheral Controller:
-  *           + Initialization/de-initialization functions
-  *           + I/O operation functions
-  *           + Peripheral Control functions 
-  *           + Peripheral State functions
-  *         
-  @verbatim
-  ==============================================================================
-                    ##### How to use this driver #####
-  ==============================================================================
-    [..]
-      (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.
-  
-      (#) Call USB_CoreInit() API to initialize the USB Core peripheral.
-
-      (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_LL_USB_DRIVER
-  * @{
-  */
-
-#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED)
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
-    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
-    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
-    defined(STM32F412Rx) || defined(STM32F412Cx)
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx);
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup LL_USB_Exported_Functions USB Low Layer Exported Functions
-  * @{
-  */
-
-/** @defgroup LL_USB_Group1 Initialization/de-initialization functions 
- *  @brief    Initialization and Configuration functions 
- *
-@verbatim    
- ===============================================================================
-              ##### Initialization/de-initialization functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
- 
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the USB Core
-  * @param  USBx: USB Instance
-  * @param  cfg : pointer to a USB_OTG_CfgTypeDef structure that contains
-  *         the configuration information for the specified USBx peripheral.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
-{
-  if (cfg.phy_itface == USB_OTG_ULPI_PHY)
-  {
-    
-    USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
-
-    /* Init The ULPI Interface */
-    USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
-   
-    /* Select vbus source */
-    USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
-    if(cfg.use_external_vbus == 1U)
-    {
-      USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;
-    }
-    /* Reset after a PHY select  */
-    USB_CoreReset(USBx); 
-  }
-  else /* FS interface (embedded Phy) */
-  {
-    /* Select FS Embedded PHY */
-    USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
-    
-    /* Reset after a PHY select and set Host mode */
-    USB_CoreReset(USBx);
-    
-    /* Deactivate the power down*/
-    USBx->GCCFG = USB_OTG_GCCFG_PWRDWN;
-  }
- 
-  if(cfg.dma_enable == ENABLE)
-  {
-    USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;
-  }  
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_EnableGlobalInt
-  *         Enables the controller's Global Int in the AHB Config reg
-  * @param  USBx : Selected device
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
-{
-  USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  USB_DisableGlobalInt
-  *         Disable the controller's Global Int in the AHB Config reg
-  * @param  USBx : Selected device
-  * @retval HAL status
-*/
-HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
-{
-  USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
-  return HAL_OK;
-}
-   
-/**
-  * @brief  USB_SetCurrentMode : Set functional mode
-  * @param  USBx : Selected device
-  * @param  mode :  current core mode
-  *          This parameter can be one of these values:
-  *            @arg USB_OTG_DEVICE_MODE: Peripheral mode
-  *            @arg USB_OTG_HOST_MODE: Host mode
-  *            @arg USB_OTG_DRD_MODE: Dual Role Device mode  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode)
-{
-  USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); 
-  
-  if ( mode == USB_OTG_HOST_MODE)
-  {
-    USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; 
-  }
-  else if ( mode == USB_OTG_DEVICE_MODE)
-  {
-    USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; 
-  }
-  HAL_Delay(50U);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_DevInit : Initializes the USB_OTG controller registers 
-  *         for device mode
-  * @param  USBx : Selected device
-  * @param  cfg  : pointer to a USB_OTG_CfgTypeDef structure that contains
-  *         the configuration information for the specified USBx peripheral.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
-{
-  uint32_t i = 0U;
-
-  /*Activate VBUS Sensing B */
-#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
-    defined(STM32F412Rx) || defined(STM32F412Cx)
-  USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
-  
-  if (cfg.vbus_sensing_enable == 0U)
-  {
-    /* Deactivate VBUS Sensing B */
-    USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
-    
-    /* B-peripheral session valid override enable*/ 
-    USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
-    USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
-  }
-#else
-  USBx->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
-  
-  if (cfg.vbus_sensing_enable == 0U)
-  {
-    USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
-  }
-#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx */
-
-  /* Restart the Phy Clock */
-  USBx_PCGCCTL = 0U;
-
-  /* Device mode configuration */
-  USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80;
-  
-  if(cfg.phy_itface  == USB_OTG_ULPI_PHY)
-  {
-    if(cfg.speed == USB_OTG_SPEED_HIGH)
-    {      
-      /* Set High speed phy */
-      USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH);
-    }
-    else 
-    {
-      /* set High speed phy in Full speed mode */
-      USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH_IN_FULL);
-    }
-  }
-  else
-  {
-    /* Set Full speed phy */
-    USB_SetDevSpeed (USBx , USB_OTG_SPEED_FULL);
-  }
-
-  /* Flush the FIFOs */
-  USB_FlushTxFifo(USBx , 0x10U); /* all Tx FIFOs */
-  USB_FlushRxFifo(USBx);
-  
-  /* Clear all pending Device Interrupts */
-  USBx_DEVICE->DIEPMSK = 0U;
-  USBx_DEVICE->DOEPMSK = 0U;
-  USBx_DEVICE->DAINT = 0xFFFFFFFFU;
-  USBx_DEVICE->DAINTMSK = 0U;
-  
-  for (i = 0U; i < cfg.dev_endpoints; i++)
-  {
-    if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
-    {
-      USBx_INEP(i)->DIEPCTL = (USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK);
-    }
-    else
-    {
-      USBx_INEP(i)->DIEPCTL = 0U;
-    }
-    
-    USBx_INEP(i)->DIEPTSIZ = 0U;
-    USBx_INEP(i)->DIEPINT  = 0xFFU;
-  }
-  
-  for (i = 0U; i < cfg.dev_endpoints; i++)
-  {
-    if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
-    {
-      USBx_OUTEP(i)->DOEPCTL = (USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK);
-    }
-    else
-    {
-      USBx_OUTEP(i)->DOEPCTL = 0U;
-    }
-    
-    USBx_OUTEP(i)->DOEPTSIZ = 0U;
-    USBx_OUTEP(i)->DOEPINT  = 0xFFU;
-  }
-  
-  USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
-  
-  if (cfg.dma_enable == 1U)
-  {
-    /*Set threshold parameters */
-    USBx_DEVICE->DTHRCTL = (USB_OTG_DTHRCTL_TXTHRLEN_6 | USB_OTG_DTHRCTL_RXTHRLEN_6);
-    USBx_DEVICE->DTHRCTL |= (USB_OTG_DTHRCTL_RXTHREN | USB_OTG_DTHRCTL_ISOTHREN | USB_OTG_DTHRCTL_NONISOTHREN);
-    
-    i= USBx_DEVICE->DTHRCTL;
-  }
-  
-  /* Disable all interrupts. */
-  USBx->GINTMSK = 0U;
-  
-  /* Clear any pending interrupts */
-  USBx->GINTSTS = 0xBFFFFFFFU;
-
-  /* Enable the common interrupts */
-  if (cfg.dma_enable == DISABLE)
-  {
-    USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; 
-  }
-  
-  /* Enable interrupts matching to the Device mode ONLY */
-  USBx->GINTMSK |= (USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |\
-                    USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |\
-                    USB_OTG_GINTMSK_OEPINT   | USB_OTG_GINTMSK_IISOIXFRM|\
-                    USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM);
-  
-  if(cfg.Sof_enable)
-  {
-    USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
-  }
-
-  if (cfg.vbus_sensing_enable == ENABLE)
-  {
-    USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); 
-  }
-  
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  USB_OTG_FlushTxFifo : Flush a Tx FIFO
-  * @param  USBx : Selected device
-  * @param  num : FIFO number
-  *         This parameter can be a value from 1 to 15
-            15 means Flush all Tx FIFOs
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num )
-{
-  uint32_t count = 0U;
- 
-  USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)( num << 6)); 
- 
-  do
-  {
-    if (++count > 200000U)
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
-  
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  USB_FlushRxFifo : Flush Rx FIFO
-  * @param  USBx : Selected device
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
-{
-  uint32_t count = 0U;
-  
-  USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
-  
-  do
-  {
-    if (++count > 200000U)
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_SetDevSpeed :Initializes the DevSpd field of DCFG register 
-  *         depending the PHY type and the enumeration speed of the device.
-  * @param  USBx : Selected device
-  * @param  speed : device speed
-  *          This parameter can be one of these values:
-  *            @arg USB_OTG_SPEED_HIGH: High speed mode
-  *            @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode
-  *            @arg USB_OTG_SPEED_FULL: Full speed mode
-  *            @arg USB_OTG_SPEED_LOW: Low speed mode
-  * @retval  Hal status
-  */
-HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed)
-{
-  USBx_DEVICE->DCFG |= speed;
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_GetDevSpeed :Return the  Dev Speed 
-  * @param  USBx : Selected device
-  * @retval speed : device speed
-  *          This parameter can be one of these values:
-  *            @arg USB_OTG_SPEED_HIGH: High speed mode
-  *            @arg USB_OTG_SPEED_FULL: Full speed mode
-  *            @arg USB_OTG_SPEED_LOW: Low speed mode
-  */
-uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
-{
-  uint8_t speed = 0U;
-  
-  if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)
-  {
-    speed = USB_OTG_SPEED_HIGH;
-  }
-  else if (((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ)||
-           ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_48MHZ))
-  {
-    speed = USB_OTG_SPEED_FULL;
-  }
-  else if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
-  {
-    speed = USB_OTG_SPEED_LOW;
-  }
-  
-  return speed;
-}
-
-/**
-  * @brief  Activate and configure an endpoint
-  * @param  USBx : Selected device
-  * @param  ep: pointer to endpoint structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
-{
-  if (ep->is_in == 1U)
-  {
-   USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & ((1U << (ep->num)));
-   
-    if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U)
-    {
-      USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18U) |\
-        ((ep->num) << 22U) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); 
-    } 
-  }
-  else
-  {
-     USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((1U << (ep->num)) << 16U);
-     
-    if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)
-    {
-      USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18U) |\
-       (USB_OTG_DIEPCTL_SD0PID_SEVNFRM)| (USB_OTG_DOEPCTL_USBAEP));
-    } 
-  }
-  return HAL_OK;
-}
-/**
-  * @brief  Activate and configure a dedicated endpoint
-  * @param  USBx : Selected device
-  * @param  ep: pointer to endpoint structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
-{
-  static __IO uint32_t debug = 0U;
-  
-  /* Read DEPCTLn register */
-  if (ep->is_in == 1U)
-  {
-    if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U)
-    {
-      USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18U) |\
-        ((ep->num) << 22U) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); 
-    } 
-    
-    
-    debug  |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18U) |\
-        ((ep->num) << 22U) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); 
-    
-   USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & ((1U << (ep->num)));
-  }
-  else
-  {
-    if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)
-    {
-      USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18U) |\
-        ((ep->num) << 22U) | (USB_OTG_DOEPCTL_USBAEP));
-      
-      debug = (uint32_t)(((uint32_t )USBx) + USB_OTG_OUT_ENDPOINT_BASE + (0U)*USB_OTG_EP_REG_SIZE);
-      debug = (uint32_t )&USBx_OUTEP(ep->num)->DOEPCTL;
-      debug |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18U) |\
-        ((ep->num) << 22U) | (USB_OTG_DOEPCTL_USBAEP)); 
-    } 
-    
-     USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((1U << (ep->num)) << 16U);
-  }
-
-  return HAL_OK;
-}
-/**
-  * @brief  De-activate and de-initialize an endpoint
-  * @param  USBx : Selected device
-  * @param  ep: pointer to endpoint structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
-{
-  /* Read DEPCTLn register */
-  if (ep->is_in == 1U)
-  {
-   USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1U << (ep->num))));
-   USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1U << (ep->num))));   
-   USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;   
-  }
-  else
-  {
-     USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1U << (ep->num)) << 16U));
-     USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1U << (ep->num)) << 16U));     
-     USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;      
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  De-activate and de-initialize a dedicated endpoint
-  * @param  USBx : Selected device
-  * @param  ep: pointer to endpoint structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
-{
-  /* Read DEPCTLn register */
-  if (ep->is_in == 1U)
-  {
-   USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
-   USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1U << (ep->num))));
-  }
-  else
-  {
-     USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; 
-     USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1U << (ep->num)) << 16U));
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_EPStartXfer : setup and starts a transfer over an EP
-  * @param  USBx : Selected device
-  * @param  ep: pointer to endpoint structure
-  * @param  dma: USB dma enabled or disabled 
-  *          This parameter can be one of these values:
-  *           0 : DMA feature not used 
-  *           1 : DMA feature used  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma)
-{
-  uint16_t pktcnt = 0U;
-  
-  /* IN endpoint */
-  if (ep->is_in == 1U)
-  {
-    /* Zero Length Packet? */
-    if (ep->xfer_len == 0U)
-    {
-      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 
-      USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19U)) ;
-      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 
-    }
-    else
-    {
-      /* Program the transfer size and packet count
-      * as follows: xfersize = N * maxpacket +
-      * short_packet pktcnt = N + (short_packet
-      * exist ? 1 : 0)
-      */
-      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
-      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 
-      USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket -1U)/ ep->maxpacket) << 19U)) ;
-      USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); 
-      
-      if (ep->type == EP_TYPE_ISOC)
-      {
-        USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); 
-        USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29U)); 
-      }       
-    }
-
-    if (dma == 1U)
-    {
-      USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr);
-    }
-    else
-    {
-      if (ep->type != EP_TYPE_ISOC)
-      {
-        /* Enable the Tx FIFO Empty Interrupt for this EP */
-        if (ep->xfer_len > 0U)
-        {
-          USBx_DEVICE->DIEPEMPMSK |= 1U << ep->num;
-        }
-      }
-    }
-
-    if (ep->type == EP_TYPE_ISOC)
-    {
-      if ((USBx_DEVICE->DSTS & ( 1U << 8U )) == 0U)
-      {
-        USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
-      }
-      else
-      {
-        USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
-      }
-    } 
-    
-    /* EP enable, IN data in FIFO */
-    USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
-    
-    if (ep->type == EP_TYPE_ISOC)
-    {
-      USB_WritePacket(USBx, ep->xfer_buff, ep->num, ep->xfer_len, dma);   
-    }    
-  }
-  else /* OUT endpoint */
-  {
-    /* Program the transfer size and packet count as follows:
-    * pktcnt = N
-    * xfersize = N * maxpacket
-    */  
-    USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); 
-    USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); 
-
-    if (ep->xfer_len == 0U)
-    {
-      USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);
-      USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19U));
-    }
-    else
-    {
-      pktcnt = (ep->xfer_len + ep->maxpacket -1U)/ ep->maxpacket; 
-      USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (pktcnt << 19U));
-      USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt));
-    }
-
-    if (dma == 1U)
-    {
-      USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)ep->xfer_buff;
-    }
-    
-    if (ep->type == EP_TYPE_ISOC)
-    {
-      if ((USBx_DEVICE->DSTS & ( 1U << 8U )) == 0U)
-      {
-        USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;
-      }
-      else
-      {
-        USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
-      }
-    }
-    /* EP enable */
-    USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_EP0StartXfer : setup and starts a transfer over the EP  0
-  * @param  USBx : Selected device
-  * @param  ep: pointer to endpoint structure
-  * @param  dma: USB dma enabled or disabled 
-  *          This parameter can be one of these values:
-  *           0 : DMA feature not used 
-  *           1 : DMA feature used  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma)
-{
-  /* IN endpoint */
-  if (ep->is_in == 1U)
-  {
-    /* Zero Length Packet? */
-    if (ep->xfer_len == 0U)
-    {
-      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 
-      USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19U)) ;
-      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 
-    }
-    else
-    {
-      /* Program the transfer size and packet count
-      * as follows: xfersize = N * maxpacket +
-      * short_packet pktcnt = N + (short_packet
-      * exist ? 1 : 0)
-      */
-      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
-      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 
-      
-      if(ep->xfer_len > ep->maxpacket)
-      {
-        ep->xfer_len = ep->maxpacket;
-      }
-      USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19U)) ;
-      USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); 
-    
-    }
-    
-    if (dma == 1)
-    {
-      USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr);
-    }
-    else
-    {
-      /* Enable the Tx FIFO Empty Interrupt for this EP */
-      if (ep->xfer_len > 0U)
-      {
-        USBx_DEVICE->DIEPEMPMSK |= 1U << (ep->num);
-      }
-    }
-    
-    /* EP enable, IN data in FIFO */
-    USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);   
-  }
-  else /* OUT endpoint */
-  {
-    /* Program the transfer size and packet count as follows:
-    * pktcnt = N
-    * xfersize = N * maxpacket
-    */
-    USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); 
-    USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); 
-      
-    if (ep->xfer_len > 0U)
-    {
-      ep->xfer_len = ep->maxpacket;
-    }
-    
-    USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19U));
-    USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket)); 
-    
-
-    if (dma == 1U)
-    {
-      USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)(ep->xfer_buff);
-    }
-    
-    /* EP enable */
-    USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);    
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_WritePacket : Writes a packet into the Tx FIFO associated 
-  *         with the EP/channel
-  * @param  USBx : Selected device           
-  * @param  src :  pointer to source buffer
-  * @param  ch_ep_num : endpoint or host channel number
-  * @param  len : Number of bytes to write
-  * @param  dma: USB dma enabled or disabled 
-  *          This parameter can be one of these values:
-  *           0 : DMA feature not used 
-  *           1 : DMA feature used  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma)
-{
-  uint32_t count32b = 0U , i = 0U;
-  
-  if (dma == 0U)
-  {
-    count32b =  (len + 3U) / 4U;
-    for (i = 0U; i < count32b; i++, src += 4U)
-    {
-      USBx_DFIFO(ch_ep_num) = *((__packed uint32_t *)src);
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_ReadPacket : read a packet from the Tx FIFO associated 
-  *         with the EP/channel
-  * @param  USBx : Selected device  
-  * @param  src : source pointer
-  * @param  ch_ep_num : endpoint or host channel number
-  * @param  len : Number of bytes to read
-  * @param  dma: USB dma enabled or disabled 
-  *          This parameter can be one of these values:
-  *           0 : DMA feature not used 
-  *           1 : DMA feature used  
-  * @retval pointer to destination buffer
-  */
-void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
-{
-  uint32_t i=0U;
-  uint32_t count32b = (len + 3U) / 4U;
-  
-  for ( i = 0U; i < count32b; i++, dest += 4U )
-  {
-    *(__packed uint32_t *)dest = USBx_DFIFO(0U);
-    
-  }
-  return ((void *)dest);
-}
-
-/**
-  * @brief  USB_EPSetStall : set a stall condition over an EP
-  * @param  USBx : Selected device
-  * @param  ep: pointer to endpoint structure   
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep)
-{
-  if (ep->is_in == 1U)
-  {
-    if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == 0U)
-    {
-      USBx_INEP(ep->num)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); 
-    } 
-    USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;
-  }
-  else
-  {
-    if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == 0U)
-    {
-      USBx_OUTEP(ep->num)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); 
-    } 
-    USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;
-  }
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  USB_EPClearStall : Clear a stall condition over an EP
-  * @param  USBx : Selected device
-  * @param  ep: pointer to endpoint structure   
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
-{
-  if (ep->is_in == 1U)
-  {
-    USBx_INEP(ep->num)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
-    if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)
-    {
-       USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */
-    }    
-  }
-  else
-  {
-    USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
-    if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)
-    {
-      USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */
-    }    
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_StopDevice : Stop the usb device mode
-  * @param  USBx : Selected device
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)
-{
-  uint32_t i;
-  
-  /* Clear Pending interrupt */
-  for (i = 0U; i < 15U ; i++)
-  {
-    USBx_INEP(i)->DIEPINT  = 0xFFU;
-    USBx_OUTEP(i)->DOEPINT  = 0xFFU;
-  }
-  USBx_DEVICE->DAINT = 0xFFFFFFFFU;
-  
-  /* Clear interrupt masks */
-  USBx_DEVICE->DIEPMSK  = 0U;
-  USBx_DEVICE->DOEPMSK  = 0U;
-  USBx_DEVICE->DAINTMSK = 0U;
-  
-  /* Flush the FIFO */
-  USB_FlushRxFifo(USBx);
-  USB_FlushTxFifo(USBx ,  0x10U);  
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_SetDevAddress : Stop the usb device mode
-  * @param  USBx : Selected device
-  * @param  address : new device address to be assigned
-  *          This parameter can be a value from 0 to 255
-  * @retval HAL status
-  */
-HAL_StatusTypeDef  USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address)
-{
-  USBx_DEVICE->DCFG &= ~ (USB_OTG_DCFG_DAD);
-  USBx_DEVICE->DCFG |= (address << 4U) & USB_OTG_DCFG_DAD ;
-  
-  return HAL_OK;  
-}
-
-/**
-  * @brief  USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down
-  * @param  USBx : Selected device
-  * @retval HAL status
-  */
-HAL_StatusTypeDef  USB_DevConnect (USB_OTG_GlobalTypeDef *USBx)
-{
-  USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS ;
-  HAL_Delay(3U);
-  
-  return HAL_OK;  
-}
-
-/**
-  * @brief  USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down
-  * @param  USBx : Selected device
-  * @retval HAL status
-  */
-HAL_StatusTypeDef  USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx)
-{
-  USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS ;
-  HAL_Delay(3U);
-  
-  return HAL_OK;  
-}
-
-/**
-  * @brief  USB_ReadInterrupts: return the global USB interrupt status
-  * @param  USBx : Selected device
-  * @retval HAL status
-  */
-uint32_t  USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx)
-{
-  uint32_t v = 0U;
-  
-  v = USBx->GINTSTS;
-  v &= USBx->GINTMSK;
-  return v;  
-}
-
-/**
-  * @brief  USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
-  * @param  USBx : Selected device
-  * @retval HAL status
-  */
-uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
-{
-  uint32_t v;
-  v  = USBx_DEVICE->DAINT;
-  v &= USBx_DEVICE->DAINTMSK;
-  return ((v & 0xffff0000U) >> 16U);
-}
-
-/**
-  * @brief  USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
-  * @param  USBx : Selected device
-  * @retval HAL status
-  */
-uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
-{
-  uint32_t v;
-  v  = USBx_DEVICE->DAINT;
-  v &= USBx_DEVICE->DAINTMSK;
-  return ((v & 0xFFFFU));
-}
-
-/**
-  * @brief  Returns Device OUT EP Interrupt register
-  * @param  USBx : Selected device
-  * @param  epnum : endpoint number
-  *          This parameter can be a value from 0 to 15
-  * @retval Device OUT EP Interrupt register
-  */
-uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)
-{
-  uint32_t v;
-  v  = USBx_OUTEP(epnum)->DOEPINT;
-  v &= USBx_DEVICE->DOEPMSK;
-  return v;
-}
-
-/**
-  * @brief  Returns Device IN EP Interrupt register
-  * @param  USBx : Selected device
-  * @param  epnum : endpoint number
-  *          This parameter can be a value from 0 to 15
-  * @retval Device IN EP Interrupt register
-  */
-uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)
-{
-  uint32_t v, msk, emp;
-  
-  msk = USBx_DEVICE->DIEPMSK;
-  emp = USBx_DEVICE->DIEPEMPMSK;
-  msk |= ((emp >> epnum) & 0x1U) << 7U;
-  v = USBx_INEP(epnum)->DIEPINT & msk;
-  return v;
-}
-
-/**
-  * @brief  USB_ClearInterrupts: clear a USB interrupt
-  * @param  USBx : Selected device
-  * @param  interrupt : interrupt flag
-  * @retval None
-  */
-void  USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
-{
-  USBx->GINTSTS |= interrupt; 
-}
-
-/**
-  * @brief  Returns USB core mode
-  * @param  USBx : Selected device
-  * @retval return core mode : Host or Device
-  *          This parameter can be one of these values:
-  *           0 : Host 
-  *           1 : Device
-  */
-uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)
-{
-  return ((USBx->GINTSTS ) & 0x1U);
-}
-
-
-/**
-  * @brief  Activate EP0 for Setup transactions
-  * @param  USBx : Selected device
-  * @retval HAL status
-  */
-HAL_StatusTypeDef  USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx)
-{
-  /* Set the MPS of the IN EP based on the enumeration speed */
-  USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
-  
-  if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
-  {
-    USBx_INEP(0U)->DIEPCTL |= 3U;
-  }
-  USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;
-
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  Prepare the EP0 to start the first control setup
-  * @param  USBx : Selected device
-  * @param  dma: USB dma enabled or disabled 
-  *          This parameter can be one of these values:
-  *           0 : DMA feature not used 
-  *           1 : DMA feature used  
-  * @param  psetup : pointer to setup packet
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup)
-{
-  USBx_OUTEP(0U)->DOEPTSIZ = 0U;
-  USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19U)) ;
-  USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U);
-  USBx_OUTEP(0U)->DOEPTSIZ |=  USB_OTG_DOEPTSIZ_STUPCNT;  
-  
-  if (dma == 1U)
-  {
-    USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup;
-    /* EP enable */
-    USBx_OUTEP(0U)->DOEPCTL = 0x80008000U;
-  }
-  
-  return HAL_OK;  
-}
-
-
-/**
-  * @brief  Reset the USB Core (needed after USB clock settings change)
-  * @param  USBx : Selected device
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
-{
-  uint32_t count = 0U;
-
-  /* Wait for AHB master IDLE state. */
-  do
-  {
-    if (++count > 200000U)
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
-  
-  /* Core Soft Reset */
-  count = 0U;
-  USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
-
-  do
-  {
-    if (++count > 200000U)
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
-  
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  USB_HostInit : Initializes the USB OTG controller registers 
-  *         for Host mode 
-  * @param  USBx : Selected device
-  * @param  cfg  : pointer to a USB_OTG_CfgTypeDef structure that contains
-  *         the configuration information for the specified USBx peripheral.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
-{
-  uint32_t i;
-  
-  /* Restart the Phy Clock */
-  USBx_PCGCCTL = 0U;
-  
-  /* Activate VBUS Sensing B */
-#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
-    defined(STM32F412Rx) || defined(STM32F412Cx)
-  USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
-#else
-  USBx->GCCFG &=~ (USB_OTG_GCCFG_VBUSASEN);
-  USBx->GCCFG &=~ (USB_OTG_GCCFG_VBUSBSEN);
-  USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
-#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx */
-
-  /* Disable the FS/LS support mode only */
-  if((cfg.speed == USB_OTG_SPEED_FULL)&&
-     (USBx != USB_OTG_FS))
-  {
-    USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS; 
-  }
-  else
-  {
-    USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);  
-  }
-
-  /* Make sure the FIFOs are flushed. */
-  USB_FlushTxFifo(USBx, 0x10U); /* all Tx FIFOs */
-  USB_FlushRxFifo(USBx);
-
-  /* Clear all pending HC Interrupts */
-  for (i = 0U; i < cfg.Host_channels; i++)
-  {
-    USBx_HC(i)->HCINT = 0xFFFFFFFFU;
-    USBx_HC(i)->HCINTMSK = 0U;
-  }
-  
-  /* Enable VBUS driving */
-  USB_DriveVbus(USBx, 1U);
-  
-  HAL_Delay(200U);
-  
-  /* Disable all interrupts. */
-  USBx->GINTMSK = 0U;
-  
-  /* Clear any pending interrupts */
-  USBx->GINTSTS = 0xFFFFFFFFU;
-  
-  if(USBx == USB_OTG_FS)
-  {
-    /* set Rx FIFO size */
-    USBx->GRXFSIZ  = (uint32_t )0x80U; 
-    USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x60U << 16U)& USB_OTG_NPTXFD) | 0x80U);
-    USBx->HPTXFSIZ = (uint32_t )(((0x40U << 16U)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U);
-  }
-  else
-  {
-    /* set Rx FIFO size */
-    USBx->GRXFSIZ  = (uint32_t )0x200U; 
-    USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x100U << 16U)& USB_OTG_NPTXFD) | 0x200U);
-    USBx->HPTXFSIZ = (uint32_t )(((0xE0U << 16U)& USB_OTG_HPTXFSIZ_PTXFD) | 0x300U);
-  }
-  
-  /* Enable the common interrupts */
-  if (cfg.dma_enable == DISABLE)
-  {
-    USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; 
-  }
-  
-  /* Enable interrupts matching to the Host mode ONLY */
-  USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM            | USB_OTG_GINTMSK_HCIM |\
-                    USB_OTG_GINTMSK_SOFM             |USB_OTG_GINTSTS_DISCINT|\
-                    USB_OTG_GINTMSK_PXFRM_IISOOXFRM  | USB_OTG_GINTMSK_WUIM);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the 
-  *         HCFG register on the PHY type and set the right frame interval
-  * @param  USBx : Selected device
-  * @param  freq : clock frequency
-  *          This parameter can be one of these values:
-  *           HCFG_48_MHZ : Full Speed 48 MHz Clock 
-  *           HCFG_6_MHZ : Low Speed 6 MHz Clock 
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq)
-{
-  USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS);
-  USBx_HOST->HCFG |= (freq & USB_OTG_HCFG_FSLSPCS);
-  
-  if (freq ==  HCFG_48_MHZ)
-  {
-    USBx_HOST->HFIR = (uint32_t)48000U;
-  }
-  else if (freq ==  HCFG_6_MHZ)
-  {
-    USBx_HOST->HFIR = (uint32_t)6000U;
-  } 
-  return HAL_OK;  
-}
-
-/**
-* @brief  USB_OTG_ResetPort : Reset Host Port
-  * @param  USBx : Selected device
-  * @retval HAL status
-  * @note   (1)The application must wait at least 10 ms
-  *   before clearing the reset bit.
-  */
-HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
-{
-  __IO uint32_t hprt0;
-  
-  hprt0 = USBx_HPRT0;
-  
-  hprt0 &= ~(USB_OTG_HPRT_PENA    | USB_OTG_HPRT_PCDET |\
-    USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
-  
-  USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0);  
-  HAL_Delay (10U);                                /* See Note #1 */
-  USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0); 
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_DriveVbus : activate or de-activate vbus
-  * @param  state : VBUS state
-  *          This parameter can be one of these values:
-  *           0 : VBUS Active 
-  *           1 : VBUS Inactive
-  * @retval HAL status
-*/
-HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state)
-{
-  __IO uint32_t hprt0;
-
-  hprt0 = USBx_HPRT0;
-  hprt0 &= ~(USB_OTG_HPRT_PENA    | USB_OTG_HPRT_PCDET |\
-                         USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
-  
-  if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U))
-  {
-    USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0); 
-  }
-  if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0U))
-  {
-    USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0); 
-  }
-  return HAL_OK; 
-}
-
-/**
-  * @brief  Return Host Core speed
-  * @param  USBx : Selected device
-  * @retval speed : Host speed
-  *          This parameter can be one of these values:
-  *            @arg USB_OTG_SPEED_HIGH: High speed mode
-  *            @arg USB_OTG_SPEED_FULL: Full speed mode
-  *            @arg USB_OTG_SPEED_LOW: Low speed mode
-  */
-uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx)
-{
-  __IO uint32_t hprt0;
-  
-  hprt0 = USBx_HPRT0;
-  return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17U);
-}
-
-/**
-  * @brief  Return Host Current Frame number
-  * @param  USBx : Selected device
-  * @retval current frame number
-*/
-uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx)
-{
-  return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM);
-}
-
-/**
-  * @brief  Initialize a host channel
-  * @param  USBx : Selected device
-  * @param  ch_num : Channel number
-  *         This parameter can be a value from 1 to 15
-  * @param  epnum : Endpoint number
-  *          This parameter can be a value from 1 to 15
-  * @param  dev_address : Current device address
-  *          This parameter can be a value from 0 to 255
-  * @param  speed : Current device speed
-  *          This parameter can be one of these values:
-  *            @arg USB_OTG_SPEED_HIGH: High speed mode
-  *            @arg USB_OTG_SPEED_FULL: Full speed mode
-  *            @arg USB_OTG_SPEED_LOW: Low speed mode
-  * @param  ep_type : Endpoint Type
-  *          This parameter can be one of these values:
-  *            @arg EP_TYPE_CTRL: Control type
-  *            @arg EP_TYPE_ISOC: Isochronous type
-  *            @arg EP_TYPE_BULK: Bulk type
-  *            @arg EP_TYPE_INTR: Interrupt type
-  * @param  mps : Max Packet Size
-  *          This parameter can be a value from 0 to32K
-  * @retval HAL state
-  */
-HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,  
-                              uint8_t ch_num,
-                              uint8_t epnum,
-                              uint8_t dev_address,
-                              uint8_t speed,
-                              uint8_t ep_type,
-                              uint16_t mps)
-{
-    
-  /* Clear old interrupt conditions for this host channel. */
-  USBx_HC(ch_num)->HCINT = 0xFFFFFFFFU;
-  
-  /* Enable channel interrupts required for this transfer. */
-  switch (ep_type) 
-  {
-  case EP_TYPE_CTRL:
-  case EP_TYPE_BULK:
-    
-    USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |\
-                                USB_OTG_HCINTMSK_STALLM |\
-                                USB_OTG_HCINTMSK_TXERRM |\
-                                USB_OTG_HCINTMSK_DTERRM |\
-                                USB_OTG_HCINTMSK_AHBERR |\
-                                USB_OTG_HCINTMSK_NAKM ;
- 
-    if (epnum & 0x80U) 
-    {
-      USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
-    } 
-    else 
-    {
-      if(USBx != USB_OTG_FS)
-      {
-        USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
-      }
-    }
-    break;
-    
-  case EP_TYPE_INTR:
-    
-    USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |\
-                                USB_OTG_HCINTMSK_STALLM |\
-                                USB_OTG_HCINTMSK_TXERRM |\
-                                USB_OTG_HCINTMSK_DTERRM |\
-                                USB_OTG_HCINTMSK_NAKM   |\
-                                USB_OTG_HCINTMSK_AHBERR |\
-                                USB_OTG_HCINTMSK_FRMORM ;    
-    
-    if (epnum & 0x80U) 
-    {
-      USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
-    }
-    
-    break;
-  case EP_TYPE_ISOC:
-    
-    USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |\
-                                USB_OTG_HCINTMSK_ACKM   |\
-                                USB_OTG_HCINTMSK_AHBERR |\
-                                USB_OTG_HCINTMSK_FRMORM ;   
-    
-    if (epnum & 0x80U) 
-    {
-      USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM);      
-    }
-    break;
-  }
-  
-  /* Enable the top level host channel interrupt. */
-  USBx_HOST->HAINTMSK |= (1 << ch_num);
-  
-  /* Make sure host channel interrupts are enabled. */
-  USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM;
-  
-  /* Program the HCCHAR register */
-  USBx_HC(ch_num)->HCCHAR = (((dev_address << 22U) & USB_OTG_HCCHAR_DAD)  |\
-                             (((epnum & 0x7FU)<< 11U) & USB_OTG_HCCHAR_EPNUM)|\
-                             ((((epnum & 0x80U) == 0x80U)<< 15U) & USB_OTG_HCCHAR_EPDIR)|\
-                             (((speed == USB_OTG_SPEED_LOW)<< 17U) & USB_OTG_HCCHAR_LSDEV)|\
-                             ((ep_type << 18U) & USB_OTG_HCCHAR_EPTYP)|\
-                             (mps & USB_OTG_HCCHAR_MPSIZ));
-    
-  if (ep_type == EP_TYPE_INTR)
-  {
-    USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ;
-  }
-
-  return HAL_OK; 
-}
-
-/**
-  * @brief  Start a transfer over a host channel
-  * @param  USBx : Selected device
-  * @param  hc : pointer to host channel structure
-  * @param  dma: USB dma enabled or disabled 
-  *          This parameter can be one of these values:
-  *           0 : DMA feature not used 
-  *           1 : DMA feature used  
-  * @retval HAL state
-  */
-#if defined   (__CC_ARM) /*!< ARM Compiler */
-#pragma O0
-#elif defined (__GNUC__) /*!< GNU Compiler */
-#pragma GCC optimize ("O0")
-#endif /* __CC_ARM */
-HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma)
-{
-  uint8_t  is_oddframe = 0U; 
-  uint16_t len_words = 0U;   
-  uint16_t num_packets = 0U;
-  uint16_t max_hc_pkt_count = 256U;
-  uint32_t tmpreg = 0U;
-    
-  if((USBx != USB_OTG_FS) && (hc->speed == USB_OTG_SPEED_HIGH))
-  {
-    if((dma == 0U) && (hc->do_ping == 1U))
-    {
-      USB_DoPing(USBx, hc->ch_num);
-      return HAL_OK;
-    }
-    else if(dma == 1U)
-    {
-      USBx_HC(hc->ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
-      hc->do_ping = 0U;
-    }
-  }
-  
-  /* Compute the expected number of packets associated to the transfer */
-  if (hc->xfer_len > 0U)
-  {
-    num_packets = (hc->xfer_len + hc->max_packet - 1U) / hc->max_packet;
-    
-    if (num_packets > max_hc_pkt_count)
-    {
-      num_packets = max_hc_pkt_count;
-      hc->xfer_len = num_packets * hc->max_packet;
-    }
-  }
-  else
-  {
-    num_packets = 1U;
-  }
-  if (hc->ep_is_in)
-  {
-    hc->xfer_len = num_packets * hc->max_packet;
-  }
-  
-  /* Initialize the HCTSIZn register */
-  USBx_HC(hc->ch_num)->HCTSIZ = (((hc->xfer_len) & USB_OTG_HCTSIZ_XFRSIZ)) |\
-    ((num_packets << 19U) & USB_OTG_HCTSIZ_PKTCNT) |\
-      (((hc->data_pid) << 29U) & USB_OTG_HCTSIZ_DPID);
-  
-  if (dma)
-  {
-    /* xfer_buff MUST be 32-bits aligned */
-    USBx_HC(hc->ch_num)->HCDMA = (uint32_t)hc->xfer_buff;
-  }
-  
-  is_oddframe = (USBx_HOST->HFNUM & 0x01U) ? 0U : 1U;
-  USBx_HC(hc->ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;
-  USBx_HC(hc->ch_num)->HCCHAR |= (is_oddframe << 29U);
-  
-  /* Set host channel enable */
-  tmpreg = USBx_HC(hc->ch_num)->HCCHAR;
-  tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
-  tmpreg |= USB_OTG_HCCHAR_CHENA;
-  USBx_HC(hc->ch_num)->HCCHAR = tmpreg;
-  
-  if (dma == 0U) /* Slave mode */
-  {  
-    if((hc->ep_is_in == 0U) && (hc->xfer_len > 0U))
-    {
-      switch(hc->ep_type) 
-      {
-        /* Non periodic transfer */
-      case EP_TYPE_CTRL:
-      case EP_TYPE_BULK:
-        
-        len_words = (hc->xfer_len + 3U) / 4U;
-        
-        /* check if there is enough space in FIFO space */
-        if(len_words > (USBx->HNPTXSTS & 0xFFFFU))
-        {
-          /* need to process data in nptxfempty interrupt */
-          USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM;
-        }
-        break;
-        /* Periodic transfer */
-      case EP_TYPE_INTR:
-      case EP_TYPE_ISOC:
-        len_words = (hc->xfer_len + 3U) / 4U;
-        /* check if there is enough space in FIFO space */
-        if(len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */
-        {
-          /* need to process data in ptxfempty interrupt */
-          USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM;          
-        }
-        break;
-        
-      default:
-        break;
-      }
-      
-      /* Write packet into the Tx FIFO. */
-      USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, hc->xfer_len, 0);
-    }
-  }
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief Read all host channel interrupts status
-  * @param  USBx : Selected device
-  * @retval HAL state
-  */
-uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx)
-{
-  return ((USBx_HOST->HAINT) & 0xFFFFU);
-}
-
-/**
-  * @brief  Halt a host channel
-  * @param  USBx : Selected device
-  * @param  hc_num : Host Channel number
-  *         This parameter can be a value from 1 to 15
-  * @retval HAL state
-  */
-HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num)
-{
-  uint32_t count = 0U;
-  
-  /* Check for space in the request queue to issue the halt. */
-  if (((((USBx_HC(hc_num)->HCCHAR) & USB_OTG_HCCHAR_EPTYP) >> 18) == HCCHAR_CTRL) || (((((USBx_HC(hc_num)->HCCHAR) & 
-  USB_OTG_HCCHAR_EPTYP) >> 18) == HCCHAR_BULK)))
-  {
-    USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
-    
-    if ((USBx->HNPTXSTS & 0xFF0000U) == 0U)
-    {
-      USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
-      USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;  
-      do 
-      {
-        if (++count > 1000U) 
-        {
-          break;
-        }
-      } 
-      while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);     
-    }
-    else
-    {
-      USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; 
-    }
-  }
-  else
-  {
-    USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
-    
-    if ((USBx_HOST->HPTXSTS & 0xFFFFU) == 0U)
-    {
-      USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
-      USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;  
-      do 
-      {
-        if (++count > 1000U) 
-        {
-          break;
-        }
-      } 
-      while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);     
-    }
-    else
-    {
-       USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; 
-    }
-  }
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initiate Do Ping protocol
-  * @param  USBx : Selected device
-  * @param  hc_num : Host Channel number
-  *         This parameter can be a value from 1 to 15
-  * @retval HAL state
-  */
-HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num)
-{
-  uint8_t  num_packets = 1U;
-  uint32_t tmpreg = 0U;
-
-  USBx_HC(ch_num)->HCTSIZ = ((num_packets << 19U) & USB_OTG_HCTSIZ_PKTCNT) |\
-                                USB_OTG_HCTSIZ_DOPING;
-  
-  /* Set host channel enable */
-  tmpreg = USBx_HC(ch_num)->HCCHAR;
-  tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
-  tmpreg |= USB_OTG_HCCHAR_CHENA;
-  USBx_HC(ch_num)->HCCHAR = tmpreg;
-  
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Stop Host Core
-  * @param  USBx : Selected device
-  * @retval HAL state
-  */
-HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
-{
-  uint8_t i;
-  uint32_t count = 0U;
-  uint32_t value;
-  
-  USB_DisableGlobalInt(USBx);
-  
-    /* Flush FIFO */
-  USB_FlushTxFifo(USBx, 0x10U);
-  USB_FlushRxFifo(USBx);
-  
-  /* Flush out any leftover queued requests. */
-  for (i = 0U; i <= 15U; i++)
-  {   
-
-    value = USBx_HC(i)->HCCHAR ;
-    value |=  USB_OTG_HCCHAR_CHDIS;
-    value &= ~USB_OTG_HCCHAR_CHENA;  
-    value &= ~USB_OTG_HCCHAR_EPDIR;
-    USBx_HC(i)->HCCHAR = value;
-  }
-  
-  /* Halt all channels to put them into a known state. */  
-  for (i = 0U; i <= 15U; i++)
-  {
-    value = USBx_HC(i)->HCCHAR ;
-    
-    value |= USB_OTG_HCCHAR_CHDIS;
-    value |= USB_OTG_HCCHAR_CHENA;  
-    value &= ~USB_OTG_HCCHAR_EPDIR;
-    
-    USBx_HC(i)->HCCHAR = value;
-    do 
-    {
-      if (++count > 1000U) 
-      {
-        break;
-      }
-    } 
-    while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
-  }
-
-  /* Clear any pending Host interrupts */  
-  USBx_HOST->HAINT = 0xFFFFFFFFU;
-  USBx->GINTSTS = 0xFFFFFFFFU;
-  USB_EnableGlobalInt(USBx);
-  return HAL_OK;  
-}
-/**
-  * @}
-  */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx ||
-          STM32F412Vx || STM32F412Cx */
-#endif /* defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/inc/Legacy/stm32_hal_legacy.h b/stmhal/hal/f7/inc/Legacy/stm32_hal_legacy.h
deleted file mode 100644
index bd8104e2d7..0000000000
--- a/stmhal/hal/f7/inc/Legacy/stm32_hal_legacy.h
+++ /dev/null
@@ -1,3150 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32_hal_legacy.h
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   This file contains aliases definition for the STM32Cube HAL constants
-  *          macros and functions maintained for legacy purpose.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32_HAL_LEGACY
-#define __STM32_HAL_LEGACY
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define AES_FLAG_RDERR                  CRYP_FLAG_RDERR
-#define AES_FLAG_WRERR                  CRYP_FLAG_WRERR
-#define AES_CLEARFLAG_CCF               CRYP_CLEARFLAG_CCF
-#define AES_CLEARFLAG_RDERR             CRYP_CLEARFLAG_RDERR
-#define AES_CLEARFLAG_WRERR             CRYP_CLEARFLAG_WRERR
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define ADC_RESOLUTION12b               ADC_RESOLUTION_12B
-#define ADC_RESOLUTION10b               ADC_RESOLUTION_10B
-#define ADC_RESOLUTION8b                ADC_RESOLUTION_8B
-#define ADC_RESOLUTION6b                ADC_RESOLUTION_6B
-#define OVR_DATA_OVERWRITTEN            ADC_OVR_DATA_OVERWRITTEN
-#define OVR_DATA_PRESERVED              ADC_OVR_DATA_PRESERVED
-#define EOC_SINGLE_CONV                 ADC_EOC_SINGLE_CONV
-#define EOC_SEQ_CONV                    ADC_EOC_SEQ_CONV
-#define EOC_SINGLE_SEQ_CONV             ADC_EOC_SINGLE_SEQ_CONV
-#define REGULAR_GROUP                   ADC_REGULAR_GROUP
-#define INJECTED_GROUP                  ADC_INJECTED_GROUP
-#define REGULAR_INJECTED_GROUP          ADC_REGULAR_INJECTED_GROUP
-#define AWD_EVENT                       ADC_AWD_EVENT
-#define AWD1_EVENT                      ADC_AWD1_EVENT
-#define AWD2_EVENT                      ADC_AWD2_EVENT
-#define AWD3_EVENT                      ADC_AWD3_EVENT
-#define OVR_EVENT                       ADC_OVR_EVENT
-#define JQOVF_EVENT                     ADC_JQOVF_EVENT
-#define ALL_CHANNELS                    ADC_ALL_CHANNELS
-#define REGULAR_CHANNELS                ADC_REGULAR_CHANNELS
-#define INJECTED_CHANNELS               ADC_INJECTED_CHANNELS
-#define SYSCFG_FLAG_SENSOR_ADC          ADC_FLAG_SENSOR
-#define SYSCFG_FLAG_VREF_ADC            ADC_FLAG_VREFINT
-#define ADC_CLOCKPRESCALER_PCLK_DIV1    ADC_CLOCK_SYNC_PCLK_DIV1
-#define ADC_CLOCKPRESCALER_PCLK_DIV2    ADC_CLOCK_SYNC_PCLK_DIV2
-#define ADC_CLOCKPRESCALER_PCLK_DIV4    ADC_CLOCK_SYNC_PCLK_DIV4
-#define ADC_CLOCKPRESCALER_PCLK_DIV6    ADC_CLOCK_SYNC_PCLK_DIV6
-#define ADC_CLOCKPRESCALER_PCLK_DIV8    ADC_CLOCK_SYNC_PCLK_DIV8
-#define ADC_EXTERNALTRIG0_T6_TRGO       ADC_EXTERNALTRIGCONV_T6_TRGO
-#define ADC_EXTERNALTRIG1_T21_CC2       ADC_EXTERNALTRIGCONV_T21_CC2
-#define ADC_EXTERNALTRIG2_T2_TRGO       ADC_EXTERNALTRIGCONV_T2_TRGO
-#define ADC_EXTERNALTRIG3_T2_CC4        ADC_EXTERNALTRIGCONV_T2_CC4
-#define ADC_EXTERNALTRIG4_T22_TRGO      ADC_EXTERNALTRIGCONV_T22_TRGO
-#define ADC_EXTERNALTRIG7_EXT_IT11      ADC_EXTERNALTRIGCONV_EXT_IT11
-#define ADC_CLOCK_ASYNC                 ADC_CLOCK_ASYNC_DIV1
-#define ADC_EXTERNALTRIG_EDGE_NONE      ADC_EXTERNALTRIGCONVEDGE_NONE
-#define ADC_EXTERNALTRIG_EDGE_RISING    ADC_EXTERNALTRIGCONVEDGE_RISING
-#define ADC_EXTERNALTRIG_EDGE_FALLING   ADC_EXTERNALTRIGCONVEDGE_FALLING
-#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
-#define ADC_SAMPLETIME_2CYCLE_5         ADC_SAMPLETIME_2CYCLES_5
-
-#define HAL_ADC_STATE_BUSY_REG          HAL_ADC_STATE_REG_BUSY
-#define HAL_ADC_STATE_BUSY_INJ          HAL_ADC_STATE_INJ_BUSY
-#define HAL_ADC_STATE_EOC_REG           HAL_ADC_STATE_REG_EOC
-#define HAL_ADC_STATE_EOC_INJ           HAL_ADC_STATE_INJ_EOC
-#define HAL_ADC_STATE_ERROR             HAL_ADC_STATE_ERROR_INTERNAL
-#define HAL_ADC_STATE_BUSY              HAL_ADC_STATE_BUSY_INTERNAL
-#define HAL_ADC_STATE_AWD               HAL_ADC_STATE_AWD1
-/**
-  * @}
-  */
-
-/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define COMP_WINDOWMODE_DISABLED       COMP_WINDOWMODE_DISABLE
-#define COMP_WINDOWMODE_ENABLED        COMP_WINDOWMODE_ENABLE
-#define COMP_EXTI_LINE_COMP1_EVENT     COMP_EXTI_LINE_COMP1
-#define COMP_EXTI_LINE_COMP2_EVENT     COMP_EXTI_LINE_COMP2
-#define COMP_EXTI_LINE_COMP3_EVENT     COMP_EXTI_LINE_COMP3
-#define COMP_EXTI_LINE_COMP4_EVENT     COMP_EXTI_LINE_COMP4
-#define COMP_EXTI_LINE_COMP5_EVENT     COMP_EXTI_LINE_COMP5
-#define COMP_EXTI_LINE_COMP6_EVENT     COMP_EXTI_LINE_COMP6
-#define COMP_EXTI_LINE_COMP7_EVENT     COMP_EXTI_LINE_COMP7
-#define COMP_LPTIMCONNECTION_ENABLED   COMP_LPTIMCONNECTION_IN1_ENABLED    /*!< COMPX output is connected to LPTIM input 1 */
-#define COMP_OUTPUT_COMP6TIM2OCREFCLR  COMP_OUTPUT_COMP6_TIM2OCREFCLR
-#if defined(STM32F373xC) || defined(STM32F378xx)
-#define COMP_OUTPUT_TIM3IC1            COMP_OUTPUT_COMP1_TIM3IC1
-#define COMP_OUTPUT_TIM3OCREFCLR       COMP_OUTPUT_COMP1_TIM3OCREFCLR
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32L0) || defined(STM32L4)
-#define COMP_WINDOWMODE_ENABLE         COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
-
-#define COMP_NONINVERTINGINPUT_IO1      COMP_INPUT_PLUS_IO1
-#define COMP_NONINVERTINGINPUT_IO2      COMP_INPUT_PLUS_IO2
-#define COMP_NONINVERTINGINPUT_IO3      COMP_INPUT_PLUS_IO3
-#define COMP_NONINVERTINGINPUT_IO4      COMP_INPUT_PLUS_IO4
-#define COMP_NONINVERTINGINPUT_IO5      COMP_INPUT_PLUS_IO5
-#define COMP_NONINVERTINGINPUT_IO6      COMP_INPUT_PLUS_IO6
-
-#define COMP_INVERTINGINPUT_1_4VREFINT  COMP_INPUT_MINUS_1_4VREFINT
-#define COMP_INVERTINGINPUT_1_2VREFINT  COMP_INPUT_MINUS_1_2VREFINT
-#define COMP_INVERTINGINPUT_3_4VREFINT  COMP_INPUT_MINUS_3_4VREFINT
-#define COMP_INVERTINGINPUT_VREFINT     COMP_INPUT_MINUS_VREFINT
-#define COMP_INVERTINGINPUT_DAC1_CH1    COMP_INPUT_MINUS_DAC1_CH1
-#define COMP_INVERTINGINPUT_DAC1_CH2    COMP_INPUT_MINUS_DAC1_CH2
-#define COMP_INVERTINGINPUT_DAC1        COMP_INPUT_MINUS_DAC1_CH1
-#define COMP_INVERTINGINPUT_DAC2        COMP_INPUT_MINUS_DAC1_CH2
-#define COMP_INVERTINGINPUT_IO1         COMP_INPUT_MINUS_IO1
-#if defined(STM32L0)
-/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2),     */
-/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding   */
-/* to the second dedicated IO (only for COMP2).                               */
-#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_DAC1_CH2
-#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO2
-#else
-#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_IO2
-#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO3
-#endif
-#define COMP_INVERTINGINPUT_IO4         COMP_INPUT_MINUS_IO4
-#define COMP_INVERTINGINPUT_IO5         COMP_INPUT_MINUS_IO5
-
-#define COMP_OUTPUTLEVEL_LOW            COMP_OUTPUT_LEVEL_LOW
-#define COMP_OUTPUTLEVEL_HIGH           COMP_OUTPUT_LEVEL_HIGH
-
-/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose.                    */
-/*       To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()".        */
-#if defined(COMP_CSR_LOCK)
-#define COMP_FLAG_LOCK                 COMP_CSR_LOCK
-#elif defined(COMP_CSR_COMP1LOCK)
-#define COMP_FLAG_LOCK                 COMP_CSR_COMP1LOCK
-#elif defined(COMP_CSR_COMPxLOCK)
-#define COMP_FLAG_LOCK                 COMP_CSR_COMPxLOCK
-#endif
-
-#if defined(STM32L4)
-#define COMP_BLANKINGSRCE_TIM1OC5        COMP_BLANKINGSRC_TIM1_OC5_COMP1
-#define COMP_BLANKINGSRCE_TIM2OC3        COMP_BLANKINGSRC_TIM2_OC3_COMP1
-#define COMP_BLANKINGSRCE_TIM3OC3        COMP_BLANKINGSRC_TIM3_OC3_COMP1
-#define COMP_BLANKINGSRCE_TIM3OC4        COMP_BLANKINGSRC_TIM3_OC4_COMP2
-#define COMP_BLANKINGSRCE_TIM8OC5        COMP_BLANKINGSRC_TIM8_OC5_COMP2
-#define COMP_BLANKINGSRCE_TIM15OC1       COMP_BLANKINGSRC_TIM15_OC1_COMP2
-#define COMP_BLANKINGSRCE_NONE           COMP_BLANKINGSRC_NONE
-#endif
-
-#if defined(STM32L0)
-#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_MEDIUMSPEED
-#define COMP_MODE_LOWSPEED               COMP_POWERMODE_ULTRALOWPOWER
-#else
-#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_HIGHSPEED
-#define COMP_MODE_MEDIUMSPEED            COMP_POWERMODE_MEDIUMSPEED
-#define COMP_MODE_LOWPOWER               COMP_POWERMODE_LOWPOWER
-#define COMP_MODE_ULTRALOWPOWER          COMP_POWERMODE_ULTRALOWPOWER
-#endif
-
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
-/**
-  * @}
-  */
-
-/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define CRC_OUTPUTDATA_INVERSION_DISABLED    CRC_OUTPUTDATA_INVERSION_DISABLE
-#define CRC_OUTPUTDATA_INVERSION_ENABLED     CRC_OUTPUTDATA_INVERSION_ENABLE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define DAC1_CHANNEL_1                                  DAC_CHANNEL_1
-#define DAC1_CHANNEL_2                                  DAC_CHANNEL_2
-#define DAC2_CHANNEL_1                                  DAC_CHANNEL_1
-#define DAC_WAVE_NONE                                   ((uint32_t)0x00000000U)
-#define DAC_WAVE_NOISE                                  ((uint32_t)DAC_CR_WAVE1_0)
-#define DAC_WAVE_TRIANGLE                               ((uint32_t)DAC_CR_WAVE1_1)
-#define DAC_WAVEGENERATION_NONE                         DAC_WAVE_NONE
-#define DAC_WAVEGENERATION_NOISE                        DAC_WAVE_NOISE
-#define DAC_WAVEGENERATION_TRIANGLE                     DAC_WAVE_TRIANGLE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define HAL_REMAPDMA_ADC_DMA_CH2                DMA_REMAP_ADC_DMA_CH2
-#define HAL_REMAPDMA_USART1_TX_DMA_CH4          DMA_REMAP_USART1_TX_DMA_CH4
-#define HAL_REMAPDMA_USART1_RX_DMA_CH5          DMA_REMAP_USART1_RX_DMA_CH5
-#define HAL_REMAPDMA_TIM16_DMA_CH4              DMA_REMAP_TIM16_DMA_CH4
-#define HAL_REMAPDMA_TIM17_DMA_CH2              DMA_REMAP_TIM17_DMA_CH2
-#define HAL_REMAPDMA_USART3_DMA_CH32            DMA_REMAP_USART3_DMA_CH32
-#define HAL_REMAPDMA_TIM16_DMA_CH6              DMA_REMAP_TIM16_DMA_CH6
-#define HAL_REMAPDMA_TIM17_DMA_CH7              DMA_REMAP_TIM17_DMA_CH7
-#define HAL_REMAPDMA_SPI2_DMA_CH67              DMA_REMAP_SPI2_DMA_CH67
-#define HAL_REMAPDMA_USART2_DMA_CH67            DMA_REMAP_USART2_DMA_CH67
-#define HAL_REMAPDMA_USART3_DMA_CH32            DMA_REMAP_USART3_DMA_CH32
-#define HAL_REMAPDMA_I2C1_DMA_CH76              DMA_REMAP_I2C1_DMA_CH76
-#define HAL_REMAPDMA_TIM1_DMA_CH6               DMA_REMAP_TIM1_DMA_CH6
-#define HAL_REMAPDMA_TIM2_DMA_CH7               DMA_REMAP_TIM2_DMA_CH7
-#define HAL_REMAPDMA_TIM3_DMA_CH6               DMA_REMAP_TIM3_DMA_CH6
-
-#define IS_HAL_REMAPDMA                          IS_DMA_REMAP
-#define __HAL_REMAPDMA_CHANNEL_ENABLE            __HAL_DMA_REMAP_CHANNEL_ENABLE
-#define __HAL_REMAPDMA_CHANNEL_DISABLE           __HAL_DMA_REMAP_CHANNEL_DISABLE
-
-
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define TYPEPROGRAM_BYTE              FLASH_TYPEPROGRAM_BYTE
-#define TYPEPROGRAM_HALFWORD          FLASH_TYPEPROGRAM_HALFWORD
-#define TYPEPROGRAM_WORD              FLASH_TYPEPROGRAM_WORD
-#define TYPEPROGRAM_DOUBLEWORD        FLASH_TYPEPROGRAM_DOUBLEWORD
-#define TYPEERASE_SECTORS             FLASH_TYPEERASE_SECTORS
-#define TYPEERASE_PAGES               FLASH_TYPEERASE_PAGES
-#define TYPEERASE_PAGEERASE           FLASH_TYPEERASE_PAGES
-#define TYPEERASE_MASSERASE           FLASH_TYPEERASE_MASSERASE
-#define WRPSTATE_DISABLE              OB_WRPSTATE_DISABLE
-#define WRPSTATE_ENABLE               OB_WRPSTATE_ENABLE
-#define HAL_FLASH_TIMEOUT_VALUE       FLASH_TIMEOUT_VALUE
-#define OBEX_PCROP                    OPTIONBYTE_PCROP
-#define OBEX_BOOTCONFIG               OPTIONBYTE_BOOTCONFIG
-#define PCROPSTATE_DISABLE            OB_PCROP_STATE_DISABLE
-#define PCROPSTATE_ENABLE             OB_PCROP_STATE_ENABLE
-#define TYPEERASEDATA_BYTE            FLASH_TYPEERASEDATA_BYTE
-#define TYPEERASEDATA_HALFWORD        FLASH_TYPEERASEDATA_HALFWORD
-#define TYPEERASEDATA_WORD            FLASH_TYPEERASEDATA_WORD
-#define TYPEPROGRAMDATA_BYTE          FLASH_TYPEPROGRAMDATA_BYTE
-#define TYPEPROGRAMDATA_HALFWORD      FLASH_TYPEPROGRAMDATA_HALFWORD
-#define TYPEPROGRAMDATA_WORD          FLASH_TYPEPROGRAMDATA_WORD
-#define TYPEPROGRAMDATA_FASTBYTE      FLASH_TYPEPROGRAMDATA_FASTBYTE
-#define TYPEPROGRAMDATA_FASTHALFWORD  FLASH_TYPEPROGRAMDATA_FASTHALFWORD
-#define TYPEPROGRAMDATA_FASTWORD      FLASH_TYPEPROGRAMDATA_FASTWORD
-#define PAGESIZE                      FLASH_PAGE_SIZE
-#define TYPEPROGRAM_FASTBYTE          FLASH_TYPEPROGRAM_BYTE
-#define TYPEPROGRAM_FASTHALFWORD      FLASH_TYPEPROGRAM_HALFWORD
-#define TYPEPROGRAM_FASTWORD          FLASH_TYPEPROGRAM_WORD
-#define VOLTAGE_RANGE_1               FLASH_VOLTAGE_RANGE_1
-#define VOLTAGE_RANGE_2               FLASH_VOLTAGE_RANGE_2
-#define VOLTAGE_RANGE_3               FLASH_VOLTAGE_RANGE_3
-#define VOLTAGE_RANGE_4               FLASH_VOLTAGE_RANGE_4
-#define TYPEPROGRAM_FAST              FLASH_TYPEPROGRAM_FAST
-#define TYPEPROGRAM_FAST_AND_LAST     FLASH_TYPEPROGRAM_FAST_AND_LAST
-#define WRPAREA_BANK1_AREAA           OB_WRPAREA_BANK1_AREAA
-#define WRPAREA_BANK1_AREAB           OB_WRPAREA_BANK1_AREAB
-#define WRPAREA_BANK2_AREAA           OB_WRPAREA_BANK2_AREAA
-#define WRPAREA_BANK2_AREAB           OB_WRPAREA_BANK2_AREAB
-#define IWDG_STDBY_FREEZE             OB_IWDG_STDBY_FREEZE
-#define IWDG_STDBY_ACTIVE             OB_IWDG_STDBY_RUN
-#define IWDG_STOP_FREEZE              OB_IWDG_STOP_FREEZE
-#define IWDG_STOP_ACTIVE              OB_IWDG_STOP_RUN
-#define FLASH_ERROR_NONE              HAL_FLASH_ERROR_NONE
-#define FLASH_ERROR_RD                HAL_FLASH_ERROR_RD
-#define FLASH_ERROR_PG                HAL_FLASH_ERROR_PROG
-#define FLASH_ERROR_PGP               HAL_FLASH_ERROR_PGS
-#define FLASH_ERROR_WRP               HAL_FLASH_ERROR_WRP
-#define FLASH_ERROR_OPTV              HAL_FLASH_ERROR_OPTV
-#define FLASH_ERROR_OPTVUSR           HAL_FLASH_ERROR_OPTVUSR
-#define FLASH_ERROR_PROG              HAL_FLASH_ERROR_PROG
-#define FLASH_ERROR_OP                HAL_FLASH_ERROR_OPERATION
-#define FLASH_ERROR_PGA               HAL_FLASH_ERROR_PGA
-#define FLASH_ERROR_SIZE              HAL_FLASH_ERROR_SIZE
-#define FLASH_ERROR_SIZ               HAL_FLASH_ERROR_SIZE
-#define FLASH_ERROR_PGS               HAL_FLASH_ERROR_PGS
-#define FLASH_ERROR_MIS               HAL_FLASH_ERROR_MIS
-#define FLASH_ERROR_FAST              HAL_FLASH_ERROR_FAST
-#define FLASH_ERROR_FWWERR            HAL_FLASH_ERROR_FWWERR
-#define FLASH_ERROR_NOTZERO           HAL_FLASH_ERROR_NOTZERO
-#define FLASH_ERROR_OPERATION         HAL_FLASH_ERROR_OPERATION
-#define FLASH_ERROR_ERS               HAL_FLASH_ERROR_ERS
-#define OB_WDG_SW                     OB_IWDG_SW
-#define OB_WDG_HW                     OB_IWDG_HW
-#define OB_SDADC12_VDD_MONITOR_SET    OB_SDACD_VDD_MONITOR_SET
-#define OB_SDADC12_VDD_MONITOR_RESET  OB_SDACD_VDD_MONITOR_RESET
-#define OB_RAM_PARITY_CHECK_SET       OB_SRAM_PARITY_SET
-#define OB_RAM_PARITY_CHECK_RESET     OB_SRAM_PARITY_RESET
-#define IS_OB_SDADC12_VDD_MONITOR     IS_OB_SDACD_VDD_MONITOR
-#define OB_RDP_LEVEL0                 OB_RDP_LEVEL_0
-#define OB_RDP_LEVEL1                 OB_RDP_LEVEL_1
-#define OB_RDP_LEVEL2                 OB_RDP_LEVEL_2
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9    I2C_FASTMODEPLUS_PA9
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10   I2C_FASTMODEPLUS_PA10
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6    I2C_FASTMODEPLUS_PB6
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7    I2C_FASTMODEPLUS_PB7
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8    I2C_FASTMODEPLUS_PB8
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9    I2C_FASTMODEPLUS_PB9
-#define HAL_SYSCFG_FASTMODEPLUS_I2C1       I2C_FASTMODEPLUS_I2C1
-#define HAL_SYSCFG_FASTMODEPLUS_I2C2       I2C_FASTMODEPLUS_I2C2
-#define HAL_SYSCFG_FASTMODEPLUS_I2C3       I2C_FASTMODEPLUS_I2C3
-/**
-  * @}
-  */
-
-
-/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
-  * @{
-  */
-#if defined(STM32L4) || defined(STM32F7)
-#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE       FMC_NAND_WAIT_FEATURE_DISABLE
-#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE        FMC_NAND_WAIT_FEATURE_ENABLE
-#define FMC_NAND_PCC_MEM_BUS_WIDTH_8            FMC_NAND_MEM_BUS_WIDTH_8
-#define FMC_NAND_PCC_MEM_BUS_WIDTH_16           FMC_NAND_MEM_BUS_WIDTH_16
-#else
-#define FMC_NAND_WAIT_FEATURE_DISABLE           FMC_NAND_PCC_WAIT_FEATURE_DISABLE
-#define FMC_NAND_WAIT_FEATURE_ENABLE            FMC_NAND_PCC_WAIT_FEATURE_ENABLE
-#define FMC_NAND_MEM_BUS_WIDTH_8                FMC_NAND_PCC_MEM_BUS_WIDTH_8
-#define FMC_NAND_MEM_BUS_WIDTH_16               FMC_NAND_PCC_MEM_BUS_WIDTH_16
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define FSMC_NORSRAM_TYPEDEF                      FSMC_NORSRAM_TypeDef
-#define FSMC_NORSRAM_EXTENDED_TYPEDEF             FSMC_NORSRAM_EXTENDED_TypeDef
-/**
-  * @}
-  */
-
-/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define GET_GPIO_SOURCE                           GPIO_GET_INDEX
-#define GET_GPIO_INDEX                            GPIO_GET_INDEX
-
-#if defined(STM32F4)
-#define GPIO_AF12_SDMMC                           GPIO_AF12_SDIO
-#define GPIO_AF12_SDMMC1                          GPIO_AF12_SDIO
-#endif
-
-#if defined(STM32F7)
-#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1
-#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
-#endif
-
-#if defined(STM32L4)
-#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1
-#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
-#endif
-
-#define GPIO_AF0_LPTIM                            GPIO_AF0_LPTIM1
-#define GPIO_AF1_LPTIM                            GPIO_AF1_LPTIM1
-#define GPIO_AF2_LPTIM                            GPIO_AF2_LPTIM1
-
-#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7)
-#define  GPIO_SPEED_LOW                           GPIO_SPEED_FREQ_LOW
-#define  GPIO_SPEED_MEDIUM                        GPIO_SPEED_FREQ_MEDIUM
-#define  GPIO_SPEED_FAST                          GPIO_SPEED_FREQ_HIGH
-#define  GPIO_SPEED_HIGH                          GPIO_SPEED_FREQ_VERY_HIGH
-#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */
-
-#if defined(STM32L1)
- #define  GPIO_SPEED_VERY_LOW    GPIO_SPEED_FREQ_LOW
- #define  GPIO_SPEED_LOW         GPIO_SPEED_FREQ_MEDIUM
- #define  GPIO_SPEED_MEDIUM      GPIO_SPEED_FREQ_HIGH
- #define  GPIO_SPEED_HIGH        GPIO_SPEED_FREQ_VERY_HIGH
-#endif /* STM32L1 */
-
-#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
- #define  GPIO_SPEED_LOW    GPIO_SPEED_FREQ_LOW
- #define  GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
- #define  GPIO_SPEED_HIGH   GPIO_SPEED_FREQ_HIGH
-#endif /* STM32F0 || STM32F3 || STM32F1 */
-
-#define GPIO_AF6_DFSDM                            GPIO_AF6_DFSDM1
-/**
-  * @}
-  */
-
-/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define HRTIM_TIMDELAYEDPROTECTION_DISABLED           HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
-#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
-
-#define __HAL_HRTIM_SetCounter        __HAL_HRTIM_SETCOUNTER
-#define __HAL_HRTIM_GetCounter        __HAL_HRTIM_GETCOUNTER
-#define __HAL_HRTIM_SetPeriod         __HAL_HRTIM_SETPERIOD
-#define __HAL_HRTIM_GetPeriod         __HAL_HRTIM_GETPERIOD
-#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
-#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
-#define __HAL_HRTIM_SetCompare        __HAL_HRTIM_SETCOMPARE
-#define __HAL_HRTIM_GetCompare        __HAL_HRTIM_GETCOMPARE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define I2C_DUALADDRESS_DISABLED                I2C_DUALADDRESS_DISABLE
-#define I2C_DUALADDRESS_ENABLED                 I2C_DUALADDRESS_ENABLE
-#define I2C_GENERALCALL_DISABLED                I2C_GENERALCALL_DISABLE
-#define I2C_GENERALCALL_ENABLED                 I2C_GENERALCALL_ENABLE
-#define I2C_NOSTRETCH_DISABLED                  I2C_NOSTRETCH_DISABLE
-#define I2C_NOSTRETCH_ENABLED                   I2C_NOSTRETCH_ENABLE
-#define I2C_ANALOGFILTER_ENABLED                I2C_ANALOGFILTER_ENABLE
-#define I2C_ANALOGFILTER_DISABLED               I2C_ANALOGFILTER_DISABLE
-#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
-#define HAL_I2C_STATE_MEM_BUSY_TX               HAL_I2C_STATE_BUSY_TX
-#define HAL_I2C_STATE_MEM_BUSY_RX               HAL_I2C_STATE_BUSY_RX
-#define HAL_I2C_STATE_MASTER_BUSY_TX            HAL_I2C_STATE_BUSY_TX
-#define HAL_I2C_STATE_MASTER_BUSY_RX            HAL_I2C_STATE_BUSY_RX
-#define HAL_I2C_STATE_SLAVE_BUSY_TX             HAL_I2C_STATE_BUSY_TX
-#define HAL_I2C_STATE_SLAVE_BUSY_RX             HAL_I2C_STATE_BUSY_RX
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define IRDA_ONE_BIT_SAMPLE_DISABLED            IRDA_ONE_BIT_SAMPLE_DISABLE
-#define IRDA_ONE_BIT_SAMPLE_ENABLED             IRDA_ONE_BIT_SAMPLE_ENABLE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define KR_KEY_RELOAD                   IWDG_KEY_RELOAD
-#define KR_KEY_ENABLE                   IWDG_KEY_ENABLE
-#define KR_KEY_EWA                      IWDG_KEY_WRITE_ACCESS_ENABLE
-#define KR_KEY_DWA                      IWDG_KEY_WRITE_ACCESS_DISABLE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
-#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
-#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
-#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
-
-#define LPTIM_CLOCKPOLARITY_RISINGEDGE          LPTIM_CLOCKPOLARITY_RISING
-#define LPTIM_CLOCKPOLARITY_FALLINGEDGE         LPTIM_CLOCKPOLARITY_FALLING
-#define LPTIM_CLOCKPOLARITY_BOTHEDGES           LPTIM_CLOCKPOLARITY_RISING_FALLING
-
-#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION  LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
-#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS      LPTIM_TRIGSAMPLETIME_2TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS      LPTIM_TRIGSAMPLETIME_4TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS      LPTIM_TRIGSAMPLETIME_8TRANSITIONS
-
-/* The following 3 definition have also been present in a temporary version of lptim.h */
-/* They need to be renamed also to the right name, just in case */
-#define LPTIM_TRIGSAMPLETIME_2TRANSITION        LPTIM_TRIGSAMPLETIME_2TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_4TRANSITION        LPTIM_TRIGSAMPLETIME_4TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_8TRANSITION        LPTIM_TRIGSAMPLETIME_8TRANSITIONS
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define HAL_NAND_Read_Page              HAL_NAND_Read_Page_8b
-#define HAL_NAND_Write_Page             HAL_NAND_Write_Page_8b
-#define HAL_NAND_Read_SpareArea         HAL_NAND_Read_SpareArea_8b
-#define HAL_NAND_Write_SpareArea        HAL_NAND_Write_SpareArea_8b
-
-#define NAND_AddressTypedef             NAND_AddressTypeDef
-
-#define __ARRAY_ADDRESS                 ARRAY_ADDRESS
-#define __ADDR_1st_CYCLE                ADDR_1ST_CYCLE
-#define __ADDR_2nd_CYCLE                ADDR_2ND_CYCLE
-#define __ADDR_3rd_CYCLE                ADDR_3RD_CYCLE
-#define __ADDR_4th_CYCLE                ADDR_4TH_CYCLE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define NOR_StatusTypedef              HAL_NOR_StatusTypeDef
-#define NOR_SUCCESS                    HAL_NOR_STATUS_SUCCESS
-#define NOR_ONGOING                    HAL_NOR_STATUS_ONGOING
-#define NOR_ERROR                      HAL_NOR_STATUS_ERROR
-#define NOR_TIMEOUT                    HAL_NOR_STATUS_TIMEOUT
-
-#define __NOR_WRITE                    NOR_WRITE
-#define __NOR_ADDR_SHIFT               NOR_ADDR_SHIFT
-/**
-  * @}
-  */
-
-/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define OPAMP_NONINVERTINGINPUT_VP0           OPAMP_NONINVERTINGINPUT_IO0
-#define OPAMP_NONINVERTINGINPUT_VP1           OPAMP_NONINVERTINGINPUT_IO1
-#define OPAMP_NONINVERTINGINPUT_VP2           OPAMP_NONINVERTINGINPUT_IO2
-#define OPAMP_NONINVERTINGINPUT_VP3           OPAMP_NONINVERTINGINPUT_IO3
-
-#define OPAMP_SEC_NONINVERTINGINPUT_VP0       OPAMP_SEC_NONINVERTINGINPUT_IO0
-#define OPAMP_SEC_NONINVERTINGINPUT_VP1       OPAMP_SEC_NONINVERTINGINPUT_IO1
-#define OPAMP_SEC_NONINVERTINGINPUT_VP2       OPAMP_SEC_NONINVERTINGINPUT_IO2
-#define OPAMP_SEC_NONINVERTINGINPUT_VP3       OPAMP_SEC_NONINVERTINGINPUT_IO3
-
-#define OPAMP_INVERTINGINPUT_VM0              OPAMP_INVERTINGINPUT_IO0
-#define OPAMP_INVERTINGINPUT_VM1              OPAMP_INVERTINGINPUT_IO1
-
-#define IOPAMP_INVERTINGINPUT_VM0             OPAMP_INVERTINGINPUT_IO0
-#define IOPAMP_INVERTINGINPUT_VM1             OPAMP_INVERTINGINPUT_IO1
-
-#define OPAMP_SEC_INVERTINGINPUT_VM0          OPAMP_SEC_INVERTINGINPUT_IO0
-#define OPAMP_SEC_INVERTINGINPUT_VM1          OPAMP_SEC_INVERTINGINPUT_IO1
-
-#define OPAMP_INVERTINGINPUT_VINM             OPAMP_SEC_INVERTINGINPUT_IO1
-
-#define OPAMP_PGACONNECT_NO                   OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
-#define OPAMP_PGACONNECT_VM0                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
-#define OPAMP_PGACONNECT_VM1                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define I2S_STANDARD_PHILLIPS      I2S_STANDARD_PHILIPS
-#if defined(STM32F7)
-  #define I2S_CLOCK_SYSCLK           I2S_CLOCK_PLL
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-/* Compact Flash-ATA registers description */
-#define CF_DATA                       ATA_DATA
-#define CF_SECTOR_COUNT               ATA_SECTOR_COUNT
-#define CF_SECTOR_NUMBER              ATA_SECTOR_NUMBER
-#define CF_CYLINDER_LOW               ATA_CYLINDER_LOW
-#define CF_CYLINDER_HIGH              ATA_CYLINDER_HIGH
-#define CF_CARD_HEAD                  ATA_CARD_HEAD
-#define CF_STATUS_CMD                 ATA_STATUS_CMD
-#define CF_STATUS_CMD_ALTERNATE       ATA_STATUS_CMD_ALTERNATE
-#define CF_COMMON_DATA_AREA           ATA_COMMON_DATA_AREA
-
-/* Compact Flash-ATA commands */
-#define CF_READ_SECTOR_CMD            ATA_READ_SECTOR_CMD
-#define CF_WRITE_SECTOR_CMD           ATA_WRITE_SECTOR_CMD
-#define CF_ERASE_SECTOR_CMD           ATA_ERASE_SECTOR_CMD
-#define CF_IDENTIFY_CMD               ATA_IDENTIFY_CMD
-
-#define PCCARD_StatusTypedef          HAL_PCCARD_StatusTypeDef
-#define PCCARD_SUCCESS                HAL_PCCARD_STATUS_SUCCESS
-#define PCCARD_ONGOING                HAL_PCCARD_STATUS_ONGOING
-#define PCCARD_ERROR                  HAL_PCCARD_STATUS_ERROR
-#define PCCARD_TIMEOUT                HAL_PCCARD_STATUS_TIMEOUT
-/**
-  * @}
-  */
-
-/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define FORMAT_BIN                  RTC_FORMAT_BIN
-#define FORMAT_BCD                  RTC_FORMAT_BCD
-
-#define RTC_ALARMSUBSECONDMASK_None     RTC_ALARMSUBSECONDMASK_NONE
-#define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE
-#define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE
-#define RTC_TAMPERMASK_FLAG_DISABLED    RTC_TAMPERMASK_FLAG_DISABLE
-#define RTC_TAMPERMASK_FLAG_ENABLED     RTC_TAMPERMASK_FLAG_ENABLE
-
-#define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE
-#define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE
-#define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE
-#define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE
-#define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE
-#define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE
-#define RTC_TAMPER1_2_INTERRUPT         RTC_ALL_TAMPER_INTERRUPT
-#define RTC_TAMPER1_2_3_INTERRUPT       RTC_ALL_TAMPER_INTERRUPT
-
-#define RTC_TIMESTAMPPIN_PC13  RTC_TIMESTAMPPIN_DEFAULT
-#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
-#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
-#define RTC_TIMESTAMPPIN_PC1   RTC_TIMESTAMPPIN_POS2
-
-#define RTC_OUTPUT_REMAP_PC13  RTC_OUTPUT_REMAP_NONE
-#define RTC_OUTPUT_REMAP_PB14  RTC_OUTPUT_REMAP_POS1
-#define RTC_OUTPUT_REMAP_PB2   RTC_OUTPUT_REMAP_POS1
-
-#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
-#define RTC_TAMPERPIN_PA0  RTC_TAMPERPIN_POS1
-#define RTC_TAMPERPIN_PI8  RTC_TAMPERPIN_POS1
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define SMARTCARD_NACK_ENABLED                  SMARTCARD_NACK_ENABLE
-#define SMARTCARD_NACK_DISABLED                 SMARTCARD_NACK_DISABLE
-
-#define SMARTCARD_ONEBIT_SAMPLING_DISABLED      SMARTCARD_ONE_BIT_SAMPLE_DISABLE
-#define SMARTCARD_ONEBIT_SAMPLING_ENABLED       SMARTCARD_ONE_BIT_SAMPLE_ENABLE
-#define SMARTCARD_ONEBIT_SAMPLING_DISABLE       SMARTCARD_ONE_BIT_SAMPLE_DISABLE
-#define SMARTCARD_ONEBIT_SAMPLING_ENABLE        SMARTCARD_ONE_BIT_SAMPLE_ENABLE
-
-#define SMARTCARD_TIMEOUT_DISABLED              SMARTCARD_TIMEOUT_DISABLE
-#define SMARTCARD_TIMEOUT_ENABLED               SMARTCARD_TIMEOUT_ENABLE
-
-#define SMARTCARD_LASTBIT_DISABLED              SMARTCARD_LASTBIT_DISABLE
-#define SMARTCARD_LASTBIT_ENABLED               SMARTCARD_LASTBIT_ENABLE
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define SMBUS_DUALADDRESS_DISABLED      SMBUS_DUALADDRESS_DISABLE
-#define SMBUS_DUALADDRESS_ENABLED       SMBUS_DUALADDRESS_ENABLE
-#define SMBUS_GENERALCALL_DISABLED      SMBUS_GENERALCALL_DISABLE
-#define SMBUS_GENERALCALL_ENABLED       SMBUS_GENERALCALL_ENABLE
-#define SMBUS_NOSTRETCH_DISABLED        SMBUS_NOSTRETCH_DISABLE
-#define SMBUS_NOSTRETCH_ENABLED         SMBUS_NOSTRETCH_ENABLE
-#define SMBUS_ANALOGFILTER_ENABLED      SMBUS_ANALOGFILTER_ENABLE
-#define SMBUS_ANALOGFILTER_DISABLED     SMBUS_ANALOGFILTER_DISABLE
-#define SMBUS_PEC_DISABLED              SMBUS_PEC_DISABLE
-#define SMBUS_PEC_ENABLED               SMBUS_PEC_ENABLE
-#define HAL_SMBUS_STATE_SLAVE_LISTEN    HAL_SMBUS_STATE_LISTEN
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define SPI_TIMODE_DISABLED             SPI_TIMODE_DISABLE
-#define SPI_TIMODE_ENABLED              SPI_TIMODE_ENABLE
-
-#define SPI_CRCCALCULATION_DISABLED     SPI_CRCCALCULATION_DISABLE
-#define SPI_CRCCALCULATION_ENABLED      SPI_CRCCALCULATION_ENABLE
-
-#define SPI_NSS_PULSE_DISABLED          SPI_NSS_PULSE_DISABLE
-#define SPI_NSS_PULSE_ENABLED           SPI_NSS_PULSE_ENABLE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define CCER_CCxE_MASK                   TIM_CCER_CCxE_MASK
-#define CCER_CCxNE_MASK                  TIM_CCER_CCxNE_MASK
-
-#define TIM_DMABase_CR1                  TIM_DMABASE_CR1
-#define TIM_DMABase_CR2                  TIM_DMABASE_CR2
-#define TIM_DMABase_SMCR                 TIM_DMABASE_SMCR
-#define TIM_DMABase_DIER                 TIM_DMABASE_DIER
-#define TIM_DMABase_SR                   TIM_DMABASE_SR
-#define TIM_DMABase_EGR                  TIM_DMABASE_EGR
-#define TIM_DMABase_CCMR1                TIM_DMABASE_CCMR1
-#define TIM_DMABase_CCMR2                TIM_DMABASE_CCMR2
-#define TIM_DMABase_CCER                 TIM_DMABASE_CCER
-#define TIM_DMABase_CNT                  TIM_DMABASE_CNT
-#define TIM_DMABase_PSC                  TIM_DMABASE_PSC
-#define TIM_DMABase_ARR                  TIM_DMABASE_ARR
-#define TIM_DMABase_RCR                  TIM_DMABASE_RCR
-#define TIM_DMABase_CCR1                 TIM_DMABASE_CCR1
-#define TIM_DMABase_CCR2                 TIM_DMABASE_CCR2
-#define TIM_DMABase_CCR3                 TIM_DMABASE_CCR3
-#define TIM_DMABase_CCR4                 TIM_DMABASE_CCR4
-#define TIM_DMABase_BDTR                 TIM_DMABASE_BDTR
-#define TIM_DMABase_DCR                  TIM_DMABASE_DCR
-#define TIM_DMABase_DMAR                 TIM_DMABASE_DMAR
-#define TIM_DMABase_OR1                  TIM_DMABASE_OR1
-#define TIM_DMABase_CCMR3                TIM_DMABASE_CCMR3
-#define TIM_DMABase_CCR5                 TIM_DMABASE_CCR5
-#define TIM_DMABase_CCR6                 TIM_DMABASE_CCR6
-#define TIM_DMABase_OR2                  TIM_DMABASE_OR2
-#define TIM_DMABase_OR3                  TIM_DMABASE_OR3
-#define TIM_DMABase_OR                   TIM_DMABASE_OR
-
-#define TIM_EventSource_Update           TIM_EVENTSOURCE_UPDATE
-#define TIM_EventSource_CC1              TIM_EVENTSOURCE_CC1
-#define TIM_EventSource_CC2              TIM_EVENTSOURCE_CC2
-#define TIM_EventSource_CC3              TIM_EVENTSOURCE_CC3
-#define TIM_EventSource_CC4              TIM_EVENTSOURCE_CC4
-#define TIM_EventSource_COM              TIM_EVENTSOURCE_COM
-#define TIM_EventSource_Trigger          TIM_EVENTSOURCE_TRIGGER
-#define TIM_EventSource_Break            TIM_EVENTSOURCE_BREAK
-#define TIM_EventSource_Break2           TIM_EVENTSOURCE_BREAK2
-
-#define TIM_DMABurstLength_1Transfer     TIM_DMABURSTLENGTH_1TRANSFER
-#define TIM_DMABurstLength_2Transfers    TIM_DMABURSTLENGTH_2TRANSFERS
-#define TIM_DMABurstLength_3Transfers    TIM_DMABURSTLENGTH_3TRANSFERS
-#define TIM_DMABurstLength_4Transfers    TIM_DMABURSTLENGTH_4TRANSFERS
-#define TIM_DMABurstLength_5Transfers    TIM_DMABURSTLENGTH_5TRANSFERS
-#define TIM_DMABurstLength_6Transfers    TIM_DMABURSTLENGTH_6TRANSFERS
-#define TIM_DMABurstLength_7Transfers    TIM_DMABURSTLENGTH_7TRANSFERS
-#define TIM_DMABurstLength_8Transfers    TIM_DMABURSTLENGTH_8TRANSFERS
-#define TIM_DMABurstLength_9Transfers    TIM_DMABURSTLENGTH_9TRANSFERS
-#define TIM_DMABurstLength_10Transfers   TIM_DMABURSTLENGTH_10TRANSFERS
-#define TIM_DMABurstLength_11Transfers   TIM_DMABURSTLENGTH_11TRANSFERS
-#define TIM_DMABurstLength_12Transfers   TIM_DMABURSTLENGTH_12TRANSFERS
-#define TIM_DMABurstLength_13Transfers   TIM_DMABURSTLENGTH_13TRANSFERS
-#define TIM_DMABurstLength_14Transfers   TIM_DMABURSTLENGTH_14TRANSFERS
-#define TIM_DMABurstLength_15Transfers   TIM_DMABURSTLENGTH_15TRANSFERS
-#define TIM_DMABurstLength_16Transfers   TIM_DMABURSTLENGTH_16TRANSFERS
-#define TIM_DMABurstLength_17Transfers   TIM_DMABURSTLENGTH_17TRANSFERS
-#define TIM_DMABurstLength_18Transfers   TIM_DMABURSTLENGTH_18TRANSFERS
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define TSC_SYNC_POL_FALL        TSC_SYNC_POLARITY_FALLING
-#define TSC_SYNC_POL_RISE_HIGH   TSC_SYNC_POLARITY_RISING
-/**
-  * @}
-  */
-
-/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define UART_ONEBIT_SAMPLING_DISABLED   UART_ONE_BIT_SAMPLE_DISABLE
-#define UART_ONEBIT_SAMPLING_ENABLED    UART_ONE_BIT_SAMPLE_ENABLE
-#define UART_ONE_BIT_SAMPLE_DISABLED    UART_ONE_BIT_SAMPLE_DISABLE
-#define UART_ONE_BIT_SAMPLE_ENABLED     UART_ONE_BIT_SAMPLE_ENABLE
-
-#define __HAL_UART_ONEBIT_ENABLE        __HAL_UART_ONE_BIT_SAMPLE_ENABLE
-#define __HAL_UART_ONEBIT_DISABLE       __HAL_UART_ONE_BIT_SAMPLE_DISABLE
-
-#define __DIV_SAMPLING16                UART_DIV_SAMPLING16
-#define __DIVMANT_SAMPLING16            UART_DIVMANT_SAMPLING16
-#define __DIVFRAQ_SAMPLING16            UART_DIVFRAQ_SAMPLING16
-#define __UART_BRR_SAMPLING16           UART_BRR_SAMPLING16
-
-#define __DIV_SAMPLING8                 UART_DIV_SAMPLING8
-#define __DIVMANT_SAMPLING8             UART_DIVMANT_SAMPLING8
-#define __DIVFRAQ_SAMPLING8             UART_DIVFRAQ_SAMPLING8
-#define __UART_BRR_SAMPLING8            UART_BRR_SAMPLING8
-
-#define __DIV_LPUART                    UART_DIV_LPUART
-
-#define UART_WAKEUPMETHODE_IDLELINE     UART_WAKEUPMETHOD_IDLELINE
-#define UART_WAKEUPMETHODE_ADDRESSMARK  UART_WAKEUPMETHOD_ADDRESSMARK
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define USART_CLOCK_DISABLED            USART_CLOCK_DISABLE
-#define USART_CLOCK_ENABLED             USART_CLOCK_ENABLE
-
-#define USARTNACK_ENABLED               USART_NACK_ENABLE
-#define USARTNACK_DISABLED              USART_NACK_DISABLE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define CFR_BASE                    WWDG_CFR_BASE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define CAN_FilterFIFO0             CAN_FILTER_FIFO0
-#define CAN_FilterFIFO1             CAN_FILTER_FIFO1
-#define CAN_IT_RQCP0                CAN_IT_TME
-#define CAN_IT_RQCP1                CAN_IT_TME
-#define CAN_IT_RQCP2                CAN_IT_TME
-#define INAK_TIMEOUT                CAN_TIMEOUT_VALUE
-#define SLAK_TIMEOUT                CAN_TIMEOUT_VALUE
-#define CAN_TXSTATUS_FAILED         ((uint8_t)0x00U)
-#define CAN_TXSTATUS_OK             ((uint8_t)0x01U)
-#define CAN_TXSTATUS_PENDING        ((uint8_t)0x02U)
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define VLAN_TAG                ETH_VLAN_TAG
-#define MIN_ETH_PAYLOAD         ETH_MIN_ETH_PAYLOAD
-#define MAX_ETH_PAYLOAD         ETH_MAX_ETH_PAYLOAD
-#define JUMBO_FRAME_PAYLOAD     ETH_JUMBO_FRAME_PAYLOAD
-#define MACMIIAR_CR_MASK        ETH_MACMIIAR_CR_MASK
-#define MACCR_CLEAR_MASK        ETH_MACCR_CLEAR_MASK
-#define MACFCR_CLEAR_MASK       ETH_MACFCR_CLEAR_MASK
-#define DMAOMR_CLEAR_MASK       ETH_DMAOMR_CLEAR_MASK
-
-#define ETH_MMCCR              ((uint32_t)0x00000100U)
-#define ETH_MMCRIR             ((uint32_t)0x00000104U)
-#define ETH_MMCTIR             ((uint32_t)0x00000108U)
-#define ETH_MMCRIMR            ((uint32_t)0x0000010CU)
-#define ETH_MMCTIMR            ((uint32_t)0x00000110U)
-#define ETH_MMCTGFSCCR         ((uint32_t)0x0000014CU)
-#define ETH_MMCTGFMSCCR        ((uint32_t)0x00000150U)
-#define ETH_MMCTGFCR           ((uint32_t)0x00000168U)
-#define ETH_MMCRFCECR          ((uint32_t)0x00000194U)
-#define ETH_MMCRFAECR          ((uint32_t)0x00000198U)
-#define ETH_MMCRGUFCR          ((uint32_t)0x000001C4U)
-
-#define ETH_MAC_TXFIFO_FULL          ((uint32_t)0x02000000)  /* Tx FIFO full */
-#define ETH_MAC_TXFIFONOT_EMPTY      ((uint32_t)0x01000000)  /* Tx FIFO not empty */
-#define ETH_MAC_TXFIFO_WRITE_ACTIVE  ((uint32_t)0x00400000)  /* Tx FIFO write active */
-#define ETH_MAC_TXFIFO_IDLE     ((uint32_t)0x00000000)  /* Tx FIFO read status: Idle */
-#define ETH_MAC_TXFIFO_READ     ((uint32_t)0x00100000)  /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
-#define ETH_MAC_TXFIFO_WAITING  ((uint32_t)0x00200000)  /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
-#define ETH_MAC_TXFIFO_WRITING  ((uint32_t)0x00300000)  /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
-#define ETH_MAC_TRANSMISSION_PAUSE     ((uint32_t)0x00080000)  /* MAC transmitter in pause */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE            ((uint32_t)0x00000000)  /* MAC transmit frame controller: Idle */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING         ((uint32_t)0x00020000)  /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF   ((uint32_t)0x00040000)  /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING    ((uint32_t)0x00060000)  /* MAC transmit frame controller: Transferring input frame for transmission */
-#define ETH_MAC_MII_TRANSMIT_ACTIVE      ((uint32_t)0x00010000)  /* MAC MII transmit engine active */
-#define ETH_MAC_RXFIFO_EMPTY             ((uint32_t)0x00000000)  /* Rx FIFO fill level: empty */
-#define ETH_MAC_RXFIFO_BELOW_THRESHOLD   ((uint32_t)0x00000100)  /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
-#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD   ((uint32_t)0x00000200)  /* Rx FIFO fill level: fill-level above flow-control activate threshold */
-#define ETH_MAC_RXFIFO_FULL              ((uint32_t)0x00000300)  /* Rx FIFO fill level: full */
-#if defined(STM32F1)
-#else
-#define ETH_MAC_READCONTROLLER_IDLE               ((uint32_t)0x00000000)  /* Rx FIFO read controller IDLE state */
-#define ETH_MAC_READCONTROLLER_READING_DATA       ((uint32_t)0x00000020)  /* Rx FIFO read controller Reading frame data */
-#define ETH_MAC_READCONTROLLER_READING_STATUS     ((uint32_t)0x00000040)  /* Rx FIFO read controller Reading frame status (or time-stamp) */
-#endif
-#define ETH_MAC_READCONTROLLER_FLUSHING           ((uint32_t)0x00000060)  /* Rx FIFO read controller Flushing the frame data and status */
-#define ETH_MAC_RXFIFO_WRITE_ACTIVE     ((uint32_t)0x00000010)  /* Rx FIFO write controller active */
-#define ETH_MAC_SMALL_FIFO_NOTACTIVE    ((uint32_t)0x00000000)  /* MAC small FIFO read / write controllers not active */
-#define ETH_MAC_SMALL_FIFO_READ_ACTIVE  ((uint32_t)0x00000002)  /* MAC small FIFO read controller active */
-#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004)  /* MAC small FIFO write controller active */
-#define ETH_MAC_SMALL_FIFO_RW_ACTIVE    ((uint32_t)0x00000006)  /* MAC small FIFO read / write controllers active */
-#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE   ((uint32_t)0x00000001)  /* MAC MII receive protocol engine active */
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define HAL_DCMI_ERROR_OVF      HAL_DCMI_ERROR_OVR
-#define DCMI_IT_OVF             DCMI_IT_OVR
-#define DCMI_FLAG_OVFRI         DCMI_FLAG_OVRRI
-#define DCMI_FLAG_OVFMI         DCMI_FLAG_OVRMI
-
-#define HAL_DCMI_ConfigCROP     HAL_DCMI_ConfigCrop
-#define HAL_DCMI_EnableCROP     HAL_DCMI_EnableCrop
-#define HAL_DCMI_DisableCROP    HAL_DCMI_DisableCrop
-
-/**
-  * @}
-  */
-
-#if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
-    defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define DMA2D_ARGB8888          DMA2D_OUTPUT_ARGB8888
-#define DMA2D_RGB888            DMA2D_OUTPUT_RGB888
-#define DMA2D_RGB565            DMA2D_OUTPUT_RGB565
-#define DMA2D_ARGB1555          DMA2D_OUTPUT_ARGB1555
-#define DMA2D_ARGB4444          DMA2D_OUTPUT_ARGB4444
-
-#define CM_ARGB8888             DMA2D_INPUT_ARGB8888
-#define CM_RGB888               DMA2D_INPUT_RGB888
-#define CM_RGB565               DMA2D_INPUT_RGB565
-#define CM_ARGB1555             DMA2D_INPUT_ARGB1555
-#define CM_ARGB4444             DMA2D_INPUT_ARGB4444
-#define CM_L8                   DMA2D_INPUT_L8
-#define CM_AL44                 DMA2D_INPUT_AL44
-#define CM_AL88                 DMA2D_INPUT_AL88
-#define CM_L4                   DMA2D_INPUT_L4
-#define CM_A8                   DMA2D_INPUT_A8
-#define CM_A4                   DMA2D_INPUT_A4
-/**
-  * @}
-  */
-#endif  /* STM32L4xx ||  STM32F7*/
-
-/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_CRYP_ComputationCpltCallback     HAL_CRYPEx_ComputationCpltCallback
-/**
-  * @}
-  */
-
-/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_HASH_STATETypeDef        HAL_HASH_StateTypeDef
-#define HAL_HASHPhaseTypeDef         HAL_HASH_PhaseTypeDef
-#define HAL_HMAC_MD5_Finish          HAL_HASH_MD5_Finish
-#define HAL_HMAC_SHA1_Finish         HAL_HASH_SHA1_Finish
-#define HAL_HMAC_SHA224_Finish       HAL_HASH_SHA224_Finish
-#define HAL_HMAC_SHA256_Finish       HAL_HASH_SHA256_Finish
-
-/*HASH Algorithm Selection*/
-
-#define HASH_AlgoSelection_SHA1      HASH_ALGOSELECTION_SHA1
-#define HASH_AlgoSelection_SHA224    HASH_ALGOSELECTION_SHA224
-#define HASH_AlgoSelection_SHA256    HASH_ALGOSELECTION_SHA256
-#define HASH_AlgoSelection_MD5       HASH_ALGOSELECTION_MD5
-
-#define HASH_AlgoMode_HASH         HASH_ALGOMODE_HASH
-#define HASH_AlgoMode_HMAC         HASH_ALGOMODE_HMAC
-
-#define HASH_HMACKeyType_ShortKey  HASH_HMAC_KEYTYPE_SHORTKEY
-#define HASH_HMACKeyType_LongKey   HASH_HMAC_KEYTYPE_LONGKEY
-/**
-  * @}
-  */
-
-/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
-#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
-#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
-#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
-#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
-#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
-#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
-#define HAL_VREFINT_OutputSelect  HAL_SYSCFG_VREFINT_OutputSelect
-#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
-#if defined(STM32L0)
-#else
-#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
-#endif
-#define HAL_ADC_EnableBuffer_Cmd(cmd)  (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
-#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
-/**
-  * @}
-  */
-
-/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define FLASH_HalfPageProgram      HAL_FLASHEx_HalfPageProgram
-#define FLASH_EnableRunPowerDown   HAL_FLASHEx_EnableRunPowerDown
-#define FLASH_DisableRunPowerDown  HAL_FLASHEx_DisableRunPowerDown
-#define HAL_DATA_EEPROMEx_Unlock   HAL_FLASHEx_DATAEEPROM_Unlock
-#define HAL_DATA_EEPROMEx_Lock     HAL_FLASHEx_DATAEEPROM_Lock
-#define HAL_DATA_EEPROMEx_Erase    HAL_FLASHEx_DATAEEPROM_Erase
-#define HAL_DATA_EEPROMEx_Program  HAL_FLASHEx_DATAEEPROM_Program
-
- /**
-  * @}
-  */
-
-/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_I2CEx_AnalogFilter_Config         HAL_I2CEx_ConfigAnalogFilter
-#define HAL_I2CEx_DigitalFilter_Config        HAL_I2CEx_ConfigDigitalFilter
-#define HAL_FMPI2CEx_AnalogFilter_Config      HAL_FMPI2CEx_ConfigAnalogFilter
-#define HAL_FMPI2CEx_DigitalFilter_Config     HAL_FMPI2CEx_ConfigDigitalFilter
-
-#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
- /**
-  * @}
-  */
-
-/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
-  * @{
-  */
-#define HAL_PWR_PVDConfig                             HAL_PWR_ConfigPVD
-#define HAL_PWR_DisableBkUpReg                        HAL_PWREx_DisableBkUpReg
-#define HAL_PWR_DisableFlashPowerDown                 HAL_PWREx_DisableFlashPowerDown
-#define HAL_PWR_DisableVddio2Monitor                  HAL_PWREx_DisableVddio2Monitor
-#define HAL_PWR_EnableBkUpReg                         HAL_PWREx_EnableBkUpReg
-#define HAL_PWR_EnableFlashPowerDown                  HAL_PWREx_EnableFlashPowerDown
-#define HAL_PWR_EnableVddio2Monitor                   HAL_PWREx_EnableVddio2Monitor
-#define HAL_PWR_PVD_PVM_IRQHandler                    HAL_PWREx_PVD_PVM_IRQHandler
-#define HAL_PWR_PVDLevelConfig                        HAL_PWR_ConfigPVD
-#define HAL_PWR_Vddio2Monitor_IRQHandler              HAL_PWREx_Vddio2Monitor_IRQHandler
-#define HAL_PWR_Vddio2MonitorCallback                 HAL_PWREx_Vddio2MonitorCallback
-#define HAL_PWREx_ActivateOverDrive                   HAL_PWREx_EnableOverDrive
-#define HAL_PWREx_DeactivateOverDrive                 HAL_PWREx_DisableOverDrive
-#define HAL_PWREx_DisableSDADCAnalog                  HAL_PWREx_DisableSDADC
-#define HAL_PWREx_EnableSDADCAnalog                   HAL_PWREx_EnableSDADC
-#define HAL_PWREx_PVMConfig                           HAL_PWREx_ConfigPVM
-
-#define PWR_MODE_NORMAL                               PWR_PVD_MODE_NORMAL
-#define PWR_MODE_IT_RISING                            PWR_PVD_MODE_IT_RISING
-#define PWR_MODE_IT_FALLING                           PWR_PVD_MODE_IT_FALLING
-#define PWR_MODE_IT_RISING_FALLING                    PWR_PVD_MODE_IT_RISING_FALLING
-#define PWR_MODE_EVENT_RISING                         PWR_PVD_MODE_EVENT_RISING
-#define PWR_MODE_EVENT_FALLING                        PWR_PVD_MODE_EVENT_FALLING
-#define PWR_MODE_EVENT_RISING_FALLING                 PWR_PVD_MODE_EVENT_RISING_FALLING
-
-#define CR_OFFSET_BB                                  PWR_CR_OFFSET_BB
-#define CSR_OFFSET_BB                                 PWR_CSR_OFFSET_BB
-
-#define DBP_BitNumber                                 DBP_BIT_NUMBER
-#define PVDE_BitNumber                                PVDE_BIT_NUMBER
-#define PMODE_BitNumber                               PMODE_BIT_NUMBER
-#define EWUP_BitNumber                                EWUP_BIT_NUMBER
-#define FPDS_BitNumber                                FPDS_BIT_NUMBER
-#define ODEN_BitNumber                                ODEN_BIT_NUMBER
-#define ODSWEN_BitNumber                              ODSWEN_BIT_NUMBER
-#define MRLVDS_BitNumber                              MRLVDS_BIT_NUMBER
-#define LPLVDS_BitNumber                              LPLVDS_BIT_NUMBER
-#define BRE_BitNumber                                 BRE_BIT_NUMBER
-
-#define PWR_MODE_EVT                                  PWR_PVD_MODE_NORMAL
-
- /**
-  * @}
-  */
-
-/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_SMBUS_Slave_Listen_IT          HAL_SMBUS_EnableListen_IT
-#define HAL_SMBUS_SlaveAddrCallback        HAL_SMBUS_AddrCallback
-#define HAL_SMBUS_SlaveListenCpltCallback  HAL_SMBUS_ListenCpltCallback
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_SPI_FlushRxFifo                HAL_SPIEx_FlushRxFifo
-/**
-  * @}
-  */
-
-/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_TIM_DMADelayPulseCplt                       TIM_DMADelayPulseCplt
-#define HAL_TIM_DMAError                                TIM_DMAError
-#define HAL_TIM_DMACaptureCplt                          TIM_DMACaptureCplt
-#define HAL_TIMEx_DMACommutationCplt                    TIMEx_DMACommutationCplt
-/**
-  * @}
-  */
-
-/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
-/**
-  * @}
-  */
-
-/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros ------------------------------------------------------------*/
-
-/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define AES_IT_CC                      CRYP_IT_CC
-#define AES_IT_ERR                     CRYP_IT_ERR
-#define AES_FLAG_CCF                   CRYP_FLAG_CCF
-/**
-  * @}
-  */
-
-/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_GET_BOOT_MODE                   __HAL_SYSCFG_GET_BOOT_MODE
-#define __HAL_REMAPMEMORY_FLASH               __HAL_SYSCFG_REMAPMEMORY_FLASH
-#define __HAL_REMAPMEMORY_SYSTEMFLASH         __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
-#define __HAL_REMAPMEMORY_SRAM                __HAL_SYSCFG_REMAPMEMORY_SRAM
-#define __HAL_REMAPMEMORY_FMC                 __HAL_SYSCFG_REMAPMEMORY_FMC
-#define __HAL_REMAPMEMORY_FMC_SDRAM           __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
-#define __HAL_REMAPMEMORY_FSMC                __HAL_SYSCFG_REMAPMEMORY_FSMC
-#define __HAL_REMAPMEMORY_QUADSPI             __HAL_SYSCFG_REMAPMEMORY_QUADSPI
-#define __HAL_FMC_BANK                        __HAL_SYSCFG_FMC_BANK
-#define __HAL_GET_FLAG                        __HAL_SYSCFG_GET_FLAG
-#define __HAL_CLEAR_FLAG                      __HAL_SYSCFG_CLEAR_FLAG
-#define __HAL_VREFINT_OUT_ENABLE              __HAL_SYSCFG_VREFINT_OUT_ENABLE
-#define __HAL_VREFINT_OUT_DISABLE             __HAL_SYSCFG_VREFINT_OUT_DISABLE
-
-#define SYSCFG_FLAG_VREF_READY                SYSCFG_FLAG_VREFINT_READY
-#define SYSCFG_FLAG_RC48                      RCC_FLAG_HSI48
-#define IS_SYSCFG_FASTMODEPLUS_CONFIG         IS_I2C_FASTMODEPLUS
-#define UFB_MODE_BitNumber                    UFB_MODE_BIT_NUMBER
-#define CMP_PD_BitNumber                      CMP_PD_BIT_NUMBER
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __ADC_ENABLE                                     __HAL_ADC_ENABLE
-#define __ADC_DISABLE                                    __HAL_ADC_DISABLE
-#define __HAL_ADC_ENABLING_CONDITIONS                    ADC_ENABLING_CONDITIONS
-#define __HAL_ADC_DISABLING_CONDITIONS                   ADC_DISABLING_CONDITIONS
-#define __HAL_ADC_IS_ENABLED                             ADC_IS_ENABLE
-#define __ADC_IS_ENABLED                                 ADC_IS_ENABLE
-#define __HAL_ADC_IS_SOFTWARE_START_REGULAR              ADC_IS_SOFTWARE_START_REGULAR
-#define __HAL_ADC_IS_SOFTWARE_START_INJECTED             ADC_IS_SOFTWARE_START_INJECTED
-#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
-#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR          ADC_IS_CONVERSION_ONGOING_REGULAR
-#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED         ADC_IS_CONVERSION_ONGOING_INJECTED
-#define __HAL_ADC_IS_CONVERSION_ONGOING                  ADC_IS_CONVERSION_ONGOING
-#define __HAL_ADC_CLEAR_ERRORCODE                        ADC_CLEAR_ERRORCODE
-
-#define __HAL_ADC_GET_RESOLUTION                         ADC_GET_RESOLUTION
-#define __HAL_ADC_JSQR_RK                                ADC_JSQR_RK
-#define __HAL_ADC_CFGR_AWD1CH                            ADC_CFGR_AWD1CH_SHIFT
-#define __HAL_ADC_CFGR_AWD23CR                           ADC_CFGR_AWD23CR
-#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION            ADC_CFGR_INJECT_AUTO_CONVERSION
-#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE              ADC_CFGR_INJECT_CONTEXT_QUEUE
-#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS             ADC_CFGR_INJECT_DISCCONTINUOUS
-#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS                ADC_CFGR_REG_DISCCONTINUOUS
-#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM                 ADC_CFGR_DISCONTINUOUS_NUM
-#define __HAL_ADC_CFGR_AUTOWAIT                          ADC_CFGR_AUTOWAIT
-#define __HAL_ADC_CFGR_CONTINUOUS                        ADC_CFGR_CONTINUOUS
-#define __HAL_ADC_CFGR_OVERRUN                           ADC_CFGR_OVERRUN
-#define __HAL_ADC_CFGR_DMACONTREQ                        ADC_CFGR_DMACONTREQ
-#define __HAL_ADC_CFGR_EXTSEL                            ADC_CFGR_EXTSEL_SET
-#define __HAL_ADC_JSQR_JEXTSEL                           ADC_JSQR_JEXTSEL_SET
-#define __HAL_ADC_OFR_CHANNEL                            ADC_OFR_CHANNEL
-#define __HAL_ADC_DIFSEL_CHANNEL                         ADC_DIFSEL_CHANNEL
-#define __HAL_ADC_CALFACT_DIFF_SET                       ADC_CALFACT_DIFF_SET
-#define __HAL_ADC_CALFACT_DIFF_GET                       ADC_CALFACT_DIFF_GET
-#define __HAL_ADC_TRX_HIGHTHRESHOLD                      ADC_TRX_HIGHTHRESHOLD
-
-#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION                ADC_OFFSET_SHIFT_RESOLUTION
-#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION         ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
-#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION        ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
-#define __HAL_ADC_COMMON_REGISTER                        ADC_COMMON_REGISTER
-#define __HAL_ADC_COMMON_CCR_MULTI                       ADC_COMMON_CCR_MULTI
-#define __HAL_ADC_MULTIMODE_IS_ENABLED                   ADC_MULTIMODE_IS_ENABLE
-#define __ADC_MULTIMODE_IS_ENABLED                       ADC_MULTIMODE_IS_ENABLE
-#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER        ADC_NONMULTIMODE_OR_MULTIMODEMASTER
-#define __HAL_ADC_COMMON_ADC_OTHER                       ADC_COMMON_ADC_OTHER
-#define __HAL_ADC_MULTI_SLAVE                            ADC_MULTI_SLAVE
-
-#define __HAL_ADC_SQR1_L                                 ADC_SQR1_L_SHIFT
-#define __HAL_ADC_JSQR_JL                                ADC_JSQR_JL_SHIFT
-#define __HAL_ADC_JSQR_RK_JL                             ADC_JSQR_RK_JL
-#define __HAL_ADC_CR1_DISCONTINUOUS_NUM                  ADC_CR1_DISCONTINUOUS_NUM
-#define __HAL_ADC_CR1_SCAN                               ADC_CR1_SCAN_SET
-#define __HAL_ADC_CONVCYCLES_MAX_RANGE                   ADC_CONVCYCLES_MAX_RANGE
-#define __HAL_ADC_CLOCK_PRESCALER_RANGE                  ADC_CLOCK_PRESCALER_RANGE
-#define __HAL_ADC_GET_CLOCK_PRESCALER                    ADC_GET_CLOCK_PRESCALER
-
-#define __HAL_ADC_SQR1                                   ADC_SQR1
-#define __HAL_ADC_SMPR1                                  ADC_SMPR1
-#define __HAL_ADC_SMPR2                                  ADC_SMPR2
-#define __HAL_ADC_SQR3_RK                                ADC_SQR3_RK
-#define __HAL_ADC_SQR2_RK                                ADC_SQR2_RK
-#define __HAL_ADC_SQR1_RK                                ADC_SQR1_RK
-#define __HAL_ADC_CR2_CONTINUOUS                         ADC_CR2_CONTINUOUS
-#define __HAL_ADC_CR1_DISCONTINUOUS                      ADC_CR1_DISCONTINUOUS
-#define __HAL_ADC_CR1_SCANCONV                           ADC_CR1_SCANCONV
-#define __HAL_ADC_CR2_EOCSelection                       ADC_CR2_EOCSelection
-#define __HAL_ADC_CR2_DMAContReq                         ADC_CR2_DMAContReq
-#define __HAL_ADC_GET_RESOLUTION                         ADC_GET_RESOLUTION
-#define __HAL_ADC_JSQR                                   ADC_JSQR
-
-#define __HAL_ADC_CHSELR_CHANNEL                         ADC_CHSELR_CHANNEL
-#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS               ADC_CFGR1_REG_DISCCONTINUOUS
-#define __HAL_ADC_CFGR1_AUTOOFF                          ADC_CFGR1_AUTOOFF
-#define __HAL_ADC_CFGR1_AUTOWAIT                         ADC_CFGR1_AUTOWAIT
-#define __HAL_ADC_CFGR1_CONTINUOUS                       ADC_CFGR1_CONTINUOUS
-#define __HAL_ADC_CFGR1_OVERRUN                          ADC_CFGR1_OVERRUN
-#define __HAL_ADC_CFGR1_SCANDIR                          ADC_CFGR1_SCANDIR
-#define __HAL_ADC_CFGR1_DMACONTREQ                       ADC_CFGR1_DMACONTREQ
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_DHR12R1_ALIGNEMENT                        DAC_DHR12R1_ALIGNMENT
-#define __HAL_DHR12R2_ALIGNEMENT                        DAC_DHR12R2_ALIGNMENT
-#define __HAL_DHR12RD_ALIGNEMENT                        DAC_DHR12RD_ALIGNMENT
-#define IS_DAC_GENERATE_WAVE                            IS_DAC_WAVE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
-#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
-#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
-#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
-#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
-#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
-#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
-#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
-#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
-#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
-#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
-#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
-#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
-#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
-#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
-#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
-
-#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
-#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
-#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
-#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
-#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
-#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
-#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
-#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
-#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
-#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
-#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
-#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
-#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
-#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
-
-
-#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
-#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
-#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
-#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
-#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
-#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
-#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
-#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
-#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
-#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
-#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
-#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
-#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
-#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
-#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
-#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
-#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
-#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
-#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
-#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
-#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
-#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
-#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
-#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#if defined(STM32F3)
-#define COMP_START                                       __HAL_COMP_ENABLE
-#define COMP_STOP                                        __HAL_COMP_DISABLE
-#define COMP_LOCK                                        __HAL_COMP_LOCK
-
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
-                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F302xE) || defined(STM32F302xC)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
-                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
-                                                          __HAL_COMP_COMP7_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
-                                                          __HAL_COMP_COMP7_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
-                                                          __HAL_COMP_COMP7_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F373xC) ||defined(STM32F378xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
-                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
-# endif
-#else
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
-                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
-#endif
-
-#define __HAL_COMP_GET_EXTI_LINE  COMP_GET_EXTI_LINE
-
-#if defined(STM32L0) || defined(STM32L4)
-/* Note: On these STM32 families, the only argument of this macro             */
-/*       is COMP_FLAG_LOCK.                                                   */
-/*       This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle  */
-/*       argument.                                                            */
-#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__)  (__HAL_COMP_IS_LOCKED(__HANDLE__))
-#endif
-/**
-  * @}
-  */
-
-#if defined(STM32L0) || defined(STM32L4)
-/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_COMP_Start_IT       HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
-#define HAL_COMP_Stop_IT        HAL_COMP_Stop  /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
-/**
-  * @}
-  */
-#endif
-
-/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
-                          ((WAVE) == DAC_WAVE_NOISE)|| \
-                          ((WAVE) == DAC_WAVE_TRIANGLE))
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define IS_WRPAREA          IS_OB_WRPAREA
-#define IS_TYPEPROGRAM      IS_FLASH_TYPEPROGRAM
-#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
-#define IS_TYPEERASE        IS_FLASH_TYPEERASE
-#define IS_NBSECTORS        IS_FLASH_NBSECTORS
-#define IS_OB_WDG_SOURCE    IS_OB_IWDG_SOURCE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __HAL_I2C_RESET_CR2             I2C_RESET_CR2
-#define __HAL_I2C_GENERATE_START        I2C_GENERATE_START
-#define __HAL_I2C_FREQ_RANGE            I2C_FREQ_RANGE
-#define __HAL_I2C_RISE_TIME             I2C_RISE_TIME
-#define __HAL_I2C_SPEED_STANDARD        I2C_SPEED_STANDARD
-#define __HAL_I2C_SPEED_FAST            I2C_SPEED_FAST
-#define __HAL_I2C_SPEED                 I2C_SPEED
-#define __HAL_I2C_7BIT_ADD_WRITE        I2C_7BIT_ADD_WRITE
-#define __HAL_I2C_7BIT_ADD_READ         I2C_7BIT_ADD_READ
-#define __HAL_I2C_10BIT_ADDRESS         I2C_10BIT_ADDRESS
-#define __HAL_I2C_10BIT_HEADER_WRITE    I2C_10BIT_HEADER_WRITE
-#define __HAL_I2C_10BIT_HEADER_READ     I2C_10BIT_HEADER_READ
-#define __HAL_I2C_MEM_ADD_MSB           I2C_MEM_ADD_MSB
-#define __HAL_I2C_MEM_ADD_LSB           I2C_MEM_ADD_LSB
-#define __HAL_I2C_FREQRANGE             I2C_FREQRANGE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define IS_I2S_INSTANCE                 IS_I2S_ALL_INSTANCE
-#define IS_I2S_INSTANCE_EXT             IS_I2S_ALL_INSTANCE_EXT
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __IRDA_DISABLE                  __HAL_IRDA_DISABLE
-#define __IRDA_ENABLE                   __HAL_IRDA_ENABLE
-
-#define __HAL_IRDA_GETCLOCKSOURCE       IRDA_GETCLOCKSOURCE
-#define __HAL_IRDA_MASK_COMPUTATION     IRDA_MASK_COMPUTATION
-#define __IRDA_GETCLOCKSOURCE           IRDA_GETCLOCKSOURCE
-#define __IRDA_MASK_COMPUTATION         IRDA_MASK_COMPUTATION
-
-#define IS_IRDA_ONEBIT_SAMPLE           IS_IRDA_ONE_BIT_SAMPLE
-
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_IWDG_ENABLE_WRITE_ACCESS  IWDG_ENABLE_WRITE_ACCESS
-#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __HAL_LPTIM_ENABLE_INTERRUPT    __HAL_LPTIM_ENABLE_IT
-#define __HAL_LPTIM_DISABLE_INTERRUPT   __HAL_LPTIM_DISABLE_IT
-#define __HAL_LPTIM_GET_ITSTATUS        __HAL_LPTIM_GET_IT_SOURCE
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __OPAMP_CSR_OPAXPD                OPAMP_CSR_OPAXPD
-#define __OPAMP_CSR_S3SELX                OPAMP_CSR_S3SELX
-#define __OPAMP_CSR_S4SELX                OPAMP_CSR_S4SELX
-#define __OPAMP_CSR_S5SELX                OPAMP_CSR_S5SELX
-#define __OPAMP_CSR_S6SELX                OPAMP_CSR_S6SELX
-#define __OPAMP_CSR_OPAXCAL_L             OPAMP_CSR_OPAXCAL_L
-#define __OPAMP_CSR_OPAXCAL_H             OPAMP_CSR_OPAXCAL_H
-#define __OPAMP_CSR_OPAXLPM               OPAMP_CSR_OPAXLPM
-#define __OPAMP_CSR_ALL_SWITCHES          OPAMP_CSR_ALL_SWITCHES
-#define __OPAMP_CSR_ANAWSELX              OPAMP_CSR_ANAWSELX
-#define __OPAMP_CSR_OPAXCALOUT            OPAMP_CSR_OPAXCALOUT
-#define __OPAMP_OFFSET_TRIM_BITSPOSITION  OPAMP_OFFSET_TRIM_BITSPOSITION
-#define __OPAMP_OFFSET_TRIM_SET           OPAMP_OFFSET_TRIM_SET
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_PVD_EVENT_DISABLE                                  __HAL_PWR_PVD_EXTI_DISABLE_EVENT
-#define __HAL_PVD_EVENT_ENABLE                                   __HAL_PWR_PVD_EXTI_ENABLE_EVENT
-#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
-#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
-#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PVM_EVENT_DISABLE                                  __HAL_PWR_PVM_EVENT_DISABLE
-#define __HAL_PVM_EVENT_ENABLE                                   __HAL_PWR_PVM_EVENT_ENABLE
-#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
-#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
-#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
-#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
-#define __HAL_PWR_INTERNALWAKEUP_DISABLE                         HAL_PWREx_DisableInternalWakeUpLine
-#define __HAL_PWR_INTERNALWAKEUP_ENABLE                          HAL_PWREx_EnableInternalWakeUpLine
-#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE                    HAL_PWREx_DisablePullUpPullDownConfig
-#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE                     HAL_PWREx_EnablePullUpPullDownConfig
-#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER()                  do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
-#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE                         __HAL_PWR_PVD_EXTI_DISABLE_EVENT
-#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE                          __HAL_PWR_PVD_EXTI_ENABLE_EVENT
-#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE                __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
-#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE                 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE                 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
-#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE                  __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER              __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER               __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PWR_PVM_DISABLE()                                  do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
-#define __HAL_PWR_PVM_ENABLE()                                   do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
-#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE                  HAL_PWREx_DisableSRAM2ContentRetention
-#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE                   HAL_PWREx_EnableSRAM2ContentRetention
-#define __HAL_PWR_VDDIO2_DISABLE                                 HAL_PWREx_DisableVddIO2
-#define __HAL_PWR_VDDIO2_ENABLE                                  HAL_PWREx_EnableVddIO2
-#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER                 __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
-#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER           __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PWR_VDDUSB_DISABLE                                 HAL_PWREx_DisableVddUSB
-#define __HAL_PWR_VDDUSB_ENABLE                                  HAL_PWREx_EnableVddUSB
-
-#if defined (STM32F4)
-#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD)         __HAL_PWR_PVD_EXTI_ENABLE_IT()
-#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_DISABLE_IT()
-#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD)          __HAL_PWR_PVD_EXTI_GET_FLAG()
-#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
-#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD)     __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
-#else
-#define __HAL_PVD_EXTI_CLEAR_FLAG                                __HAL_PWR_PVD_EXTI_CLEAR_FLAG
-#define __HAL_PVD_EXTI_DISABLE_IT                                __HAL_PWR_PVD_EXTI_DISABLE_IT
-#define __HAL_PVD_EXTI_ENABLE_IT                                 __HAL_PWR_PVD_EXTI_ENABLE_IT
-#define __HAL_PVD_EXTI_GENERATE_SWIT                             __HAL_PWR_PVD_EXTI_GENERATE_SWIT
-#define __HAL_PVD_EXTI_GET_FLAG                                  __HAL_PWR_PVD_EXTI_GET_FLAG
-#endif /* STM32F4 */
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
-  * @{
-  */
-
-#define RCC_StopWakeUpClock_MSI     RCC_STOP_WAKEUPCLOCK_MSI
-#define RCC_StopWakeUpClock_HSI     RCC_STOP_WAKEUPCLOCK_HSI
-
-#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
-#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
-
-#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
-#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
-#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
-#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
-#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
-#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
-#define __ADC1_CLK_DISABLE        __HAL_RCC_ADC1_CLK_DISABLE
-#define __ADC1_CLK_ENABLE         __HAL_RCC_ADC1_CLK_ENABLE
-#define __ADC1_FORCE_RESET        __HAL_RCC_ADC1_FORCE_RESET
-#define __ADC1_RELEASE_RESET      __HAL_RCC_ADC1_RELEASE_RESET
-#define __ADC1_CLK_SLEEP_ENABLE   __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
-#define __ADC1_CLK_SLEEP_DISABLE  __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
-#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
-#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
-#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
-#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
-#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
-#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
-#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
-#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
-#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
-#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
-#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
-#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
-#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
-#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
-#define __CRYP_CLK_SLEEP_ENABLE      __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
-#define __CRYP_CLK_SLEEP_DISABLE  __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
-#define __CRYP_CLK_ENABLE  __HAL_RCC_CRYP_CLK_ENABLE
-#define __CRYP_CLK_DISABLE  __HAL_RCC_CRYP_CLK_DISABLE
-#define __CRYP_FORCE_RESET  __HAL_RCC_CRYP_FORCE_RESET
-#define __CRYP_RELEASE_RESET  __HAL_RCC_CRYP_RELEASE_RESET
-#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
-#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
-#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
-#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
-#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
-#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
-#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
-#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
-#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
-#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
-#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
-#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
-#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
-#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
-#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
-#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
-#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
-#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
-#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
-#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
-#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
-#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
-#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
-#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
-#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
-#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
-#define __CAN_CLK_DISABLE         __HAL_RCC_CAN1_CLK_DISABLE
-#define __CAN_CLK_ENABLE          __HAL_RCC_CAN1_CLK_ENABLE
-#define __CAN_FORCE_RESET         __HAL_RCC_CAN1_FORCE_RESET
-#define __CAN_RELEASE_RESET       __HAL_RCC_CAN1_RELEASE_RESET
-#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
-#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
-#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
-#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
-#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
-#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
-#define __COMP_CLK_DISABLE        __HAL_RCC_COMP_CLK_DISABLE
-#define __COMP_CLK_ENABLE         __HAL_RCC_COMP_CLK_ENABLE
-#define __COMP_FORCE_RESET        __HAL_RCC_COMP_FORCE_RESET
-#define __COMP_RELEASE_RESET      __HAL_RCC_COMP_RELEASE_RESET
-#define __COMP_CLK_SLEEP_ENABLE   __HAL_RCC_COMP_CLK_SLEEP_ENABLE
-#define __COMP_CLK_SLEEP_DISABLE  __HAL_RCC_COMP_CLK_SLEEP_DISABLE
-#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
-#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
-#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
-#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
-#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
-#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
-#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
-#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
-#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
-#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
-#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
-#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
-#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
-#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
-#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
-#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
-#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
-#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
-#define __DBGMCU_CLK_ENABLE     __HAL_RCC_DBGMCU_CLK_ENABLE
-#define __DBGMCU_CLK_DISABLE     __HAL_RCC_DBGMCU_CLK_DISABLE
-#define __DBGMCU_FORCE_RESET    __HAL_RCC_DBGMCU_FORCE_RESET
-#define __DBGMCU_RELEASE_RESET  __HAL_RCC_DBGMCU_RELEASE_RESET
-#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
-#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
-#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
-#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
-#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
-#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
-#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
-#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
-#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
-#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
-#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
-#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
-#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
-#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
-#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
-#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
-#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
-#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
-#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
-#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
-#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
-#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
-#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
-#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
-#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
-#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
-#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
-#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
-#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
-#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
-#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
-#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
-#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
-#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
-#define __FLITF_CLK_DISABLE       __HAL_RCC_FLITF_CLK_DISABLE
-#define __FLITF_CLK_ENABLE        __HAL_RCC_FLITF_CLK_ENABLE
-#define __FLITF_FORCE_RESET       __HAL_RCC_FLITF_FORCE_RESET
-#define __FLITF_RELEASE_RESET     __HAL_RCC_FLITF_RELEASE_RESET
-#define __FLITF_CLK_SLEEP_ENABLE  __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
-#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
-#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
-#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
-#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
-#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
-#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
-#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
-#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
-#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
-#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
-#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
-#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
-#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
-#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
-#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
-#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
-#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
-#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
-#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
-#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
-#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
-#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
-#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
-#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
-#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
-#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
-#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
-#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
-#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
-#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
-#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
-#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
-#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
-#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
-#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
-#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
-#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
-#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
-#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
-#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
-#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
-#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
-#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
-#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
-#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
-#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
-#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
-#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
-#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
-#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
-#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
-#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
-#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
-#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
-#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
-#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
-#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
-#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
-#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
-#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
-#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
-#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
-#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
-#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
-#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
-#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
-#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
-#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
-#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
-#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
-#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
-#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
-#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
-#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
-#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
-#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
-#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
-#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
-#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
-#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
-#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
-#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
-#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
-#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
-#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
-#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
-#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
-#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
-#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
-#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
-#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
-#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
-#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
-#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
-#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
-#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
-#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
-#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
-#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
-#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
-#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
-#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
-#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
-#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
-#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
-#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
-#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
-#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
-#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
-#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
-#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
-#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
-#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
-#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
-#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
-#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
-#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
-#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
-#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
-#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
-#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
-#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
-#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
-#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
-#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
-#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
-#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
-#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
-#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
-#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
-#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
-#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
-#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
-#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
-#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
-#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
-#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
-#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
-#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
-#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
-#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
-#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
-#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
-#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
-#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
-#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
-#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
-#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
-#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
-#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
-#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
-#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
-#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
-#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
-#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
-#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
-#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
-#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
-#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
-#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
-#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
-#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
-#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
-#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
-#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
-#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
-#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
-#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
-#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
-#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
-#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
-#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
-#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
-#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
-#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
-#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
-#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
-#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
-#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
-#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
-#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
-#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
-#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
-#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
-#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
-#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
-#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
-#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
-#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
-#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
-#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
-#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
-#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
-#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
-#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
-#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
-#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
-#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
-#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
-#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
-#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
-#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
-#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
-#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
-#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
-#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
-#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
-#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
-#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
-#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
-#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
-#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
-#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
-#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
-#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
-#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
-#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
-#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
-#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
-#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
-#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
-#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
-#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
-#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
-#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
-#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
-#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
-#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
-#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
-#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
-#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
-#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
-#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
-#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
-#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
-#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
-#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
-#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
-#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
-#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
-#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
-#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
-#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
-#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
-#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
-#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
-#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
-#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
-#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
-#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
-#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
-#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
-#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
-#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
-#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
-#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
-#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
-#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
-#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
-#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
-#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
-#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
-#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
-#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
-#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
-#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
-#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
-#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
-#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
-#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
-#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
-#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
-#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
-#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
-#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
-#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
-#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
-#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
-#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
-#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
-#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
-#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
-#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
-#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
-#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
-#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
-#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
-#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
-#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
-#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
-#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
-#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
-#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
-#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
-#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
-#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
-#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
-#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
-#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
-#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
-#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
-#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
-#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
-#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
-#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
-#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
-#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
-#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
-#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
-#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
-#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
-#define __USART4_CLK_DISABLE        __HAL_RCC_USART4_CLK_DISABLE
-#define __USART4_CLK_ENABLE         __HAL_RCC_USART4_CLK_ENABLE
-#define __USART4_CLK_SLEEP_ENABLE   __HAL_RCC_USART4_CLK_SLEEP_ENABLE
-#define __USART4_CLK_SLEEP_DISABLE  __HAL_RCC_USART4_CLK_SLEEP_DISABLE
-#define __USART4_FORCE_RESET        __HAL_RCC_USART4_FORCE_RESET
-#define __USART4_RELEASE_RESET      __HAL_RCC_USART4_RELEASE_RESET
-#define __USART5_CLK_DISABLE        __HAL_RCC_USART5_CLK_DISABLE
-#define __USART5_CLK_ENABLE         __HAL_RCC_USART5_CLK_ENABLE
-#define __USART5_CLK_SLEEP_ENABLE   __HAL_RCC_USART5_CLK_SLEEP_ENABLE
-#define __USART5_CLK_SLEEP_DISABLE  __HAL_RCC_USART5_CLK_SLEEP_DISABLE
-#define __USART5_FORCE_RESET        __HAL_RCC_USART5_FORCE_RESET
-#define __USART5_RELEASE_RESET      __HAL_RCC_USART5_RELEASE_RESET
-#define __USART7_CLK_DISABLE        __HAL_RCC_USART7_CLK_DISABLE
-#define __USART7_CLK_ENABLE         __HAL_RCC_USART7_CLK_ENABLE
-#define __USART7_FORCE_RESET        __HAL_RCC_USART7_FORCE_RESET
-#define __USART7_RELEASE_RESET      __HAL_RCC_USART7_RELEASE_RESET
-#define __USART8_CLK_DISABLE        __HAL_RCC_USART8_CLK_DISABLE
-#define __USART8_CLK_ENABLE         __HAL_RCC_USART8_CLK_ENABLE
-#define __USART8_FORCE_RESET        __HAL_RCC_USART8_FORCE_RESET
-#define __USART8_RELEASE_RESET      __HAL_RCC_USART8_RELEASE_RESET
-#define __USB_CLK_DISABLE         __HAL_RCC_USB_CLK_DISABLE
-#define __USB_CLK_ENABLE          __HAL_RCC_USB_CLK_ENABLE
-#define __USB_FORCE_RESET         __HAL_RCC_USB_FORCE_RESET
-#define __USB_CLK_SLEEP_ENABLE    __HAL_RCC_USB_CLK_SLEEP_ENABLE
-#define __USB_CLK_SLEEP_DISABLE   __HAL_RCC_USB_CLK_SLEEP_DISABLE
-#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
-#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
-#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
-#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
-#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
-#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
-#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
-#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
-#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
-#define __TIM21_CLK_ENABLE   __HAL_RCC_TIM21_CLK_ENABLE
-#define __TIM21_CLK_DISABLE   __HAL_RCC_TIM21_CLK_DISABLE
-#define __TIM21_FORCE_RESET   __HAL_RCC_TIM21_FORCE_RESET
-#define __TIM21_RELEASE_RESET  __HAL_RCC_TIM21_RELEASE_RESET
-#define __TIM21_CLK_SLEEP_ENABLE   __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
-#define __TIM21_CLK_SLEEP_DISABLE   __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
-#define __TIM22_CLK_ENABLE   __HAL_RCC_TIM22_CLK_ENABLE
-#define __TIM22_CLK_DISABLE   __HAL_RCC_TIM22_CLK_DISABLE
-#define __TIM22_FORCE_RESET   __HAL_RCC_TIM22_FORCE_RESET
-#define __TIM22_RELEASE_RESET  __HAL_RCC_TIM22_RELEASE_RESET
-#define __TIM22_CLK_SLEEP_ENABLE   __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
-#define __TIM22_CLK_SLEEP_DISABLE   __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
-#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
-#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
-#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
-#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
-#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
-#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
-#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
-#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
-
-#define __USB_OTG_FS_FORCE_RESET  __HAL_RCC_USB_OTG_FS_FORCE_RESET
-#define __USB_OTG_FS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
-#define __USB_OTG_FS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
-#define __USB_OTG_FS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
-#define __USB_OTG_HS_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_DISABLE
-#define __USB_OTG_HS_CLK_ENABLE          __HAL_RCC_USB_OTG_HS_CLK_ENABLE
-#define __USB_OTG_HS_ULPI_CLK_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
-#define __USB_OTG_HS_ULPI_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
-#define __TIM9_CLK_SLEEP_ENABLE          __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
-#define __TIM9_CLK_SLEEP_DISABLE  __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
-#define __TIM10_CLK_SLEEP_ENABLE  __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
-#define __TIM10_CLK_SLEEP_DISABLE  __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
-#define __TIM11_CLK_SLEEP_ENABLE  __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
-#define __TIM11_CLK_SLEEP_DISABLE  __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
-#define __ETHMACPTP_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
-#define __ETHMACPTP_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
-#define __ETHMACPTP_CLK_ENABLE          __HAL_RCC_ETHMACPTP_CLK_ENABLE
-#define __ETHMACPTP_CLK_DISABLE          __HAL_RCC_ETHMACPTP_CLK_DISABLE
-#define __HASH_CLK_ENABLE          __HAL_RCC_HASH_CLK_ENABLE
-#define __HASH_FORCE_RESET          __HAL_RCC_HASH_FORCE_RESET
-#define __HASH_RELEASE_RESET          __HAL_RCC_HASH_RELEASE_RESET
-#define __HASH_CLK_SLEEP_ENABLE          __HAL_RCC_HASH_CLK_SLEEP_ENABLE
-#define __HASH_CLK_SLEEP_DISABLE  __HAL_RCC_HASH_CLK_SLEEP_DISABLE
-#define __HASH_CLK_DISABLE            __HAL_RCC_HASH_CLK_DISABLE
-#define __SPI5_CLK_ENABLE          __HAL_RCC_SPI5_CLK_ENABLE
-#define __SPI5_CLK_DISABLE              __HAL_RCC_SPI5_CLK_DISABLE
-#define __SPI5_FORCE_RESET          __HAL_RCC_SPI5_FORCE_RESET
-#define __SPI5_RELEASE_RESET          __HAL_RCC_SPI5_RELEASE_RESET
-#define __SPI5_CLK_SLEEP_ENABLE          __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
-#define __SPI5_CLK_SLEEP_DISABLE  __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
-#define __SPI6_CLK_ENABLE          __HAL_RCC_SPI6_CLK_ENABLE
-#define __SPI6_CLK_DISABLE          __HAL_RCC_SPI6_CLK_DISABLE
-#define __SPI6_FORCE_RESET          __HAL_RCC_SPI6_FORCE_RESET
-#define __SPI6_RELEASE_RESET         __HAL_RCC_SPI6_RELEASE_RESET
-#define __SPI6_CLK_SLEEP_ENABLE          __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
-#define __SPI6_CLK_SLEEP_DISABLE  __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
-#define __LTDC_CLK_ENABLE          __HAL_RCC_LTDC_CLK_ENABLE
-#define __LTDC_CLK_DISABLE          __HAL_RCC_LTDC_CLK_DISABLE
-#define __LTDC_FORCE_RESET          __HAL_RCC_LTDC_FORCE_RESET
-#define __LTDC_RELEASE_RESET          __HAL_RCC_LTDC_RELEASE_RESET
-#define __LTDC_CLK_SLEEP_ENABLE          __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
-#define __ETHMAC_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
-#define __ETHMAC_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
-#define __ETHMACTX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
-#define __ETHMACTX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
-#define __ETHMACRX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
-#define __ETHMACRX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
-#define __TIM12_CLK_SLEEP_ENABLE  __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
-#define __TIM12_CLK_SLEEP_DISABLE  __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
-#define __TIM13_CLK_SLEEP_ENABLE  __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
-#define __TIM13_CLK_SLEEP_DISABLE  __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
-#define __TIM14_CLK_SLEEP_ENABLE  __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
-#define __TIM14_CLK_SLEEP_DISABLE  __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
-#define __BKPSRAM_CLK_ENABLE          __HAL_RCC_BKPSRAM_CLK_ENABLE
-#define __BKPSRAM_CLK_DISABLE          __HAL_RCC_BKPSRAM_CLK_DISABLE
-#define __BKPSRAM_CLK_SLEEP_ENABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
-#define __BKPSRAM_CLK_SLEEP_DISABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
-#define __CCMDATARAMEN_CLK_ENABLE  __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
-#define __CCMDATARAMEN_CLK_DISABLE  __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
-#define __USART6_CLK_ENABLE          __HAL_RCC_USART6_CLK_ENABLE
-#define __USART6_CLK_DISABLE          __HAL_RCC_USART6_CLK_DISABLE
-#define __USART6_FORCE_RESET        __HAL_RCC_USART6_FORCE_RESET
-#define __USART6_RELEASE_RESET        __HAL_RCC_USART6_RELEASE_RESET
-#define __USART6_CLK_SLEEP_ENABLE  __HAL_RCC_USART6_CLK_SLEEP_ENABLE
-#define __USART6_CLK_SLEEP_DISABLE  __HAL_RCC_USART6_CLK_SLEEP_DISABLE
-#define __SPI4_CLK_ENABLE          __HAL_RCC_SPI4_CLK_ENABLE
-#define __SPI4_CLK_DISABLE          __HAL_RCC_SPI4_CLK_DISABLE
-#define __SPI4_FORCE_RESET          __HAL_RCC_SPI4_FORCE_RESET
-#define __SPI4_RELEASE_RESET        __HAL_RCC_SPI4_RELEASE_RESET
-#define __SPI4_CLK_SLEEP_ENABLE   __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
-#define __SPI4_CLK_SLEEP_DISABLE  __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
-#define __GPIOI_CLK_ENABLE          __HAL_RCC_GPIOI_CLK_ENABLE
-#define __GPIOI_CLK_DISABLE          __HAL_RCC_GPIOI_CLK_DISABLE
-#define __GPIOI_FORCE_RESET          __HAL_RCC_GPIOI_FORCE_RESET
-#define __GPIOI_RELEASE_RESET          __HAL_RCC_GPIOI_RELEASE_RESET
-#define __GPIOI_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
-#define __GPIOI_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
-#define __GPIOJ_CLK_ENABLE          __HAL_RCC_GPIOJ_CLK_ENABLE
-#define __GPIOJ_CLK_DISABLE          __HAL_RCC_GPIOJ_CLK_DISABLE
-#define __GPIOJ_FORCE_RESET         __HAL_RCC_GPIOJ_FORCE_RESET
-#define __GPIOJ_RELEASE_RESET          __HAL_RCC_GPIOJ_RELEASE_RESET
-#define __GPIOJ_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
-#define __GPIOJ_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
-#define __GPIOK_CLK_ENABLE          __HAL_RCC_GPIOK_CLK_ENABLE
-#define __GPIOK_CLK_DISABLE          __HAL_RCC_GPIOK_CLK_DISABLE
-#define __GPIOK_RELEASE_RESET          __HAL_RCC_GPIOK_RELEASE_RESET
-#define __GPIOK_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
-#define __GPIOK_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
-#define __ETH_CLK_ENABLE          __HAL_RCC_ETH_CLK_ENABLE
-#define __ETH_CLK_DISABLE          __HAL_RCC_ETH_CLK_DISABLE
-#define __DCMI_CLK_ENABLE          __HAL_RCC_DCMI_CLK_ENABLE
-#define __DCMI_CLK_DISABLE          __HAL_RCC_DCMI_CLK_DISABLE
-#define __DCMI_FORCE_RESET          __HAL_RCC_DCMI_FORCE_RESET
-#define __DCMI_RELEASE_RESET          __HAL_RCC_DCMI_RELEASE_RESET
-#define __DCMI_CLK_SLEEP_ENABLE   __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
-#define __DCMI_CLK_SLEEP_DISABLE  __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
-#define __UART7_CLK_ENABLE          __HAL_RCC_UART7_CLK_ENABLE
-#define __UART7_CLK_DISABLE          __HAL_RCC_UART7_CLK_DISABLE
-#define __UART7_RELEASE_RESET       __HAL_RCC_UART7_RELEASE_RESET
-#define __UART7_FORCE_RESET       __HAL_RCC_UART7_FORCE_RESET
-#define __UART7_CLK_SLEEP_ENABLE  __HAL_RCC_UART7_CLK_SLEEP_ENABLE
-#define __UART7_CLK_SLEEP_DISABLE  __HAL_RCC_UART7_CLK_SLEEP_DISABLE
-#define __UART8_CLK_ENABLE          __HAL_RCC_UART8_CLK_ENABLE
-#define __UART8_CLK_DISABLE          __HAL_RCC_UART8_CLK_DISABLE
-#define __UART8_FORCE_RESET          __HAL_RCC_UART8_FORCE_RESET
-#define __UART8_RELEASE_RESET          __HAL_RCC_UART8_RELEASE_RESET
-#define __UART8_CLK_SLEEP_ENABLE  __HAL_RCC_UART8_CLK_SLEEP_ENABLE
-#define __UART8_CLK_SLEEP_DISABLE  __HAL_RCC_UART8_CLK_SLEEP_DISABLE
-#define __OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
-#define __OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
-#define __OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
-#define __OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET
-#define __OTGHSULPI_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
-#define __OTGHSULPI_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
-#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
-#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
-#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
-#define __HAL_RCC_OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
-#define __HAL_RCC_OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE      __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE     __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
-#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED  __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
-#define __CRYP_FORCE_RESET             __HAL_RCC_CRYP_FORCE_RESET
-#define __SRAM3_CLK_SLEEP_ENABLE       __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
-#define __CAN2_CLK_SLEEP_ENABLE        __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
-#define __CAN2_CLK_SLEEP_DISABLE       __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
-#define __DAC_CLK_SLEEP_ENABLE         __HAL_RCC_DAC_CLK_SLEEP_ENABLE
-#define __DAC_CLK_SLEEP_DISABLE        __HAL_RCC_DAC_CLK_SLEEP_DISABLE
-#define __ADC2_CLK_SLEEP_ENABLE        __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
-#define __ADC2_CLK_SLEEP_DISABLE       __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
-#define __ADC3_CLK_SLEEP_ENABLE        __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
-#define __ADC3_CLK_SLEEP_DISABLE       __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
-#define __FSMC_FORCE_RESET             __HAL_RCC_FSMC_FORCE_RESET
-#define __FSMC_RELEASE_RESET           __HAL_RCC_FSMC_RELEASE_RESET
-#define __FSMC_CLK_SLEEP_ENABLE        __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
-#define __FSMC_CLK_SLEEP_DISABLE       __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
-#define __SDIO_FORCE_RESET             __HAL_RCC_SDIO_FORCE_RESET
-#define __SDIO_RELEASE_RESET           __HAL_RCC_SDIO_RELEASE_RESET
-#define __SDIO_CLK_SLEEP_DISABLE       __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
-#define __SDIO_CLK_SLEEP_ENABLE        __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
-#define __DMA2D_CLK_ENABLE             __HAL_RCC_DMA2D_CLK_ENABLE
-#define __DMA2D_CLK_DISABLE            __HAL_RCC_DMA2D_CLK_DISABLE
-#define __DMA2D_FORCE_RESET            __HAL_RCC_DMA2D_FORCE_RESET
-#define __DMA2D_RELEASE_RESET          __HAL_RCC_DMA2D_RELEASE_RESET
-#define __DMA2D_CLK_SLEEP_ENABLE       __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
-#define __DMA2D_CLK_SLEEP_DISABLE      __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
-
-/* alias define maintained for legacy */
-#define __HAL_RCC_OTGFS_FORCE_RESET    __HAL_RCC_USB_OTG_FS_FORCE_RESET
-#define __HAL_RCC_OTGFS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
-
-#define __ADC12_CLK_ENABLE          __HAL_RCC_ADC12_CLK_ENABLE
-#define __ADC12_CLK_DISABLE         __HAL_RCC_ADC12_CLK_DISABLE
-#define __ADC34_CLK_ENABLE          __HAL_RCC_ADC34_CLK_ENABLE
-#define __ADC34_CLK_DISABLE         __HAL_RCC_ADC34_CLK_DISABLE
-#define __ADC12_CLK_ENABLE          __HAL_RCC_ADC12_CLK_ENABLE
-#define __ADC12_CLK_DISABLE         __HAL_RCC_ADC12_CLK_DISABLE
-#define __DAC2_CLK_ENABLE           __HAL_RCC_DAC2_CLK_ENABLE
-#define __DAC2_CLK_DISABLE          __HAL_RCC_DAC2_CLK_DISABLE
-#define __TIM18_CLK_ENABLE          __HAL_RCC_TIM18_CLK_ENABLE
-#define __TIM18_CLK_DISABLE         __HAL_RCC_TIM18_CLK_DISABLE
-#define __TIM19_CLK_ENABLE          __HAL_RCC_TIM19_CLK_ENABLE
-#define __TIM19_CLK_DISABLE         __HAL_RCC_TIM19_CLK_DISABLE
-#define __TIM20_CLK_ENABLE          __HAL_RCC_TIM20_CLK_ENABLE
-#define __TIM20_CLK_DISABLE         __HAL_RCC_TIM20_CLK_DISABLE
-#define __HRTIM1_CLK_ENABLE         __HAL_RCC_HRTIM1_CLK_ENABLE
-#define __HRTIM1_CLK_DISABLE        __HAL_RCC_HRTIM1_CLK_DISABLE
-#define __SDADC1_CLK_ENABLE         __HAL_RCC_SDADC1_CLK_ENABLE
-#define __SDADC2_CLK_ENABLE         __HAL_RCC_SDADC2_CLK_ENABLE
-#define __SDADC3_CLK_ENABLE         __HAL_RCC_SDADC3_CLK_ENABLE
-#define __SDADC1_CLK_DISABLE        __HAL_RCC_SDADC1_CLK_DISABLE
-#define __SDADC2_CLK_DISABLE        __HAL_RCC_SDADC2_CLK_DISABLE
-#define __SDADC3_CLK_DISABLE        __HAL_RCC_SDADC3_CLK_DISABLE
-
-#define __ADC12_FORCE_RESET         __HAL_RCC_ADC12_FORCE_RESET
-#define __ADC12_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET
-#define __ADC34_FORCE_RESET         __HAL_RCC_ADC34_FORCE_RESET
-#define __ADC34_RELEASE_RESET       __HAL_RCC_ADC34_RELEASE_RESET
-#define __ADC12_FORCE_RESET         __HAL_RCC_ADC12_FORCE_RESET
-#define __ADC12_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET
-#define __DAC2_FORCE_RESET          __HAL_RCC_DAC2_FORCE_RESET
-#define __DAC2_RELEASE_RESET        __HAL_RCC_DAC2_RELEASE_RESET
-#define __TIM18_FORCE_RESET         __HAL_RCC_TIM18_FORCE_RESET
-#define __TIM18_RELEASE_RESET       __HAL_RCC_TIM18_RELEASE_RESET
-#define __TIM19_FORCE_RESET         __HAL_RCC_TIM19_FORCE_RESET
-#define __TIM19_RELEASE_RESET       __HAL_RCC_TIM19_RELEASE_RESET
-#define __TIM20_FORCE_RESET         __HAL_RCC_TIM20_FORCE_RESET
-#define __TIM20_RELEASE_RESET       __HAL_RCC_TIM20_RELEASE_RESET
-#define __HRTIM1_FORCE_RESET        __HAL_RCC_HRTIM1_FORCE_RESET
-#define __HRTIM1_RELEASE_RESET      __HAL_RCC_HRTIM1_RELEASE_RESET
-#define __SDADC1_FORCE_RESET        __HAL_RCC_SDADC1_FORCE_RESET
-#define __SDADC2_FORCE_RESET        __HAL_RCC_SDADC2_FORCE_RESET
-#define __SDADC3_FORCE_RESET        __HAL_RCC_SDADC3_FORCE_RESET
-#define __SDADC1_RELEASE_RESET      __HAL_RCC_SDADC1_RELEASE_RESET
-#define __SDADC2_RELEASE_RESET      __HAL_RCC_SDADC2_RELEASE_RESET
-#define __SDADC3_RELEASE_RESET      __HAL_RCC_SDADC3_RELEASE_RESET
-
-#define __ADC1_IS_CLK_ENABLED       __HAL_RCC_ADC1_IS_CLK_ENABLED
-#define __ADC1_IS_CLK_DISABLED      __HAL_RCC_ADC1_IS_CLK_DISABLED
-#define __ADC12_IS_CLK_ENABLED      __HAL_RCC_ADC12_IS_CLK_ENABLED
-#define __ADC12_IS_CLK_DISABLED     __HAL_RCC_ADC12_IS_CLK_DISABLED
-#define __ADC34_IS_CLK_ENABLED      __HAL_RCC_ADC34_IS_CLK_ENABLED
-#define __ADC34_IS_CLK_DISABLED     __HAL_RCC_ADC34_IS_CLK_DISABLED
-#define __CEC_IS_CLK_ENABLED        __HAL_RCC_CEC_IS_CLK_ENABLED
-#define __CEC_IS_CLK_DISABLED       __HAL_RCC_CEC_IS_CLK_DISABLED
-#define __CRC_IS_CLK_ENABLED        __HAL_RCC_CRC_IS_CLK_ENABLED
-#define __CRC_IS_CLK_DISABLED       __HAL_RCC_CRC_IS_CLK_DISABLED
-#define __DAC1_IS_CLK_ENABLED       __HAL_RCC_DAC1_IS_CLK_ENABLED
-#define __DAC1_IS_CLK_DISABLED      __HAL_RCC_DAC1_IS_CLK_DISABLED
-#define __DAC2_IS_CLK_ENABLED       __HAL_RCC_DAC2_IS_CLK_ENABLED
-#define __DAC2_IS_CLK_DISABLED      __HAL_RCC_DAC2_IS_CLK_DISABLED
-#define __DMA1_IS_CLK_ENABLED       __HAL_RCC_DMA1_IS_CLK_ENABLED
-#define __DMA1_IS_CLK_DISABLED      __HAL_RCC_DMA1_IS_CLK_DISABLED
-#define __DMA2_IS_CLK_ENABLED       __HAL_RCC_DMA2_IS_CLK_ENABLED
-#define __DMA2_IS_CLK_DISABLED      __HAL_RCC_DMA2_IS_CLK_DISABLED
-#define __FLITF_IS_CLK_ENABLED      __HAL_RCC_FLITF_IS_CLK_ENABLED
-#define __FLITF_IS_CLK_DISABLED     __HAL_RCC_FLITF_IS_CLK_DISABLED
-#define __FMC_IS_CLK_ENABLED        __HAL_RCC_FMC_IS_CLK_ENABLED
-#define __FMC_IS_CLK_DISABLED       __HAL_RCC_FMC_IS_CLK_DISABLED
-#define __GPIOA_IS_CLK_ENABLED      __HAL_RCC_GPIOA_IS_CLK_ENABLED
-#define __GPIOA_IS_CLK_DISABLED     __HAL_RCC_GPIOA_IS_CLK_DISABLED
-#define __GPIOB_IS_CLK_ENABLED      __HAL_RCC_GPIOB_IS_CLK_ENABLED
-#define __GPIOB_IS_CLK_DISABLED     __HAL_RCC_GPIOB_IS_CLK_DISABLED
-#define __GPIOC_IS_CLK_ENABLED      __HAL_RCC_GPIOC_IS_CLK_ENABLED
-#define __GPIOC_IS_CLK_DISABLED     __HAL_RCC_GPIOC_IS_CLK_DISABLED
-#define __GPIOD_IS_CLK_ENABLED      __HAL_RCC_GPIOD_IS_CLK_ENABLED
-#define __GPIOD_IS_CLK_DISABLED     __HAL_RCC_GPIOD_IS_CLK_DISABLED
-#define __GPIOE_IS_CLK_ENABLED      __HAL_RCC_GPIOE_IS_CLK_ENABLED
-#define __GPIOE_IS_CLK_DISABLED     __HAL_RCC_GPIOE_IS_CLK_DISABLED
-#define __GPIOF_IS_CLK_ENABLED      __HAL_RCC_GPIOF_IS_CLK_ENABLED
-#define __GPIOF_IS_CLK_DISABLED     __HAL_RCC_GPIOF_IS_CLK_DISABLED
-#define __GPIOG_IS_CLK_ENABLED      __HAL_RCC_GPIOG_IS_CLK_ENABLED
-#define __GPIOG_IS_CLK_DISABLED     __HAL_RCC_GPIOG_IS_CLK_DISABLED
-#define __GPIOH_IS_CLK_ENABLED      __HAL_RCC_GPIOH_IS_CLK_ENABLED
-#define __GPIOH_IS_CLK_DISABLED     __HAL_RCC_GPIOH_IS_CLK_DISABLED
-#define __HRTIM1_IS_CLK_ENABLED     __HAL_RCC_HRTIM1_IS_CLK_ENABLED
-#define __HRTIM1_IS_CLK_DISABLED    __HAL_RCC_HRTIM1_IS_CLK_DISABLED
-#define __I2C1_IS_CLK_ENABLED       __HAL_RCC_I2C1_IS_CLK_ENABLED
-#define __I2C1_IS_CLK_DISABLED      __HAL_RCC_I2C1_IS_CLK_DISABLED
-#define __I2C2_IS_CLK_ENABLED       __HAL_RCC_I2C2_IS_CLK_ENABLED
-#define __I2C2_IS_CLK_DISABLED      __HAL_RCC_I2C2_IS_CLK_DISABLED
-#define __I2C3_IS_CLK_ENABLED       __HAL_RCC_I2C3_IS_CLK_ENABLED
-#define __I2C3_IS_CLK_DISABLED      __HAL_RCC_I2C3_IS_CLK_DISABLED
-#define __PWR_IS_CLK_ENABLED        __HAL_RCC_PWR_IS_CLK_ENABLED
-#define __PWR_IS_CLK_DISABLED       __HAL_RCC_PWR_IS_CLK_DISABLED
-#define __SYSCFG_IS_CLK_ENABLED     __HAL_RCC_SYSCFG_IS_CLK_ENABLED
-#define __SYSCFG_IS_CLK_DISABLED    __HAL_RCC_SYSCFG_IS_CLK_DISABLED
-#define __SPI1_IS_CLK_ENABLED       __HAL_RCC_SPI1_IS_CLK_ENABLED
-#define __SPI1_IS_CLK_DISABLED      __HAL_RCC_SPI1_IS_CLK_DISABLED
-#define __SPI2_IS_CLK_ENABLED       __HAL_RCC_SPI2_IS_CLK_ENABLED
-#define __SPI2_IS_CLK_DISABLED      __HAL_RCC_SPI2_IS_CLK_DISABLED
-#define __SPI3_IS_CLK_ENABLED       __HAL_RCC_SPI3_IS_CLK_ENABLED
-#define __SPI3_IS_CLK_DISABLED      __HAL_RCC_SPI3_IS_CLK_DISABLED
-#define __SPI4_IS_CLK_ENABLED       __HAL_RCC_SPI4_IS_CLK_ENABLED
-#define __SPI4_IS_CLK_DISABLED      __HAL_RCC_SPI4_IS_CLK_DISABLED
-#define __SDADC1_IS_CLK_ENABLED     __HAL_RCC_SDADC1_IS_CLK_ENABLED
-#define __SDADC1_IS_CLK_DISABLED    __HAL_RCC_SDADC1_IS_CLK_DISABLED
-#define __SDADC2_IS_CLK_ENABLED     __HAL_RCC_SDADC2_IS_CLK_ENABLED
-#define __SDADC2_IS_CLK_DISABLED    __HAL_RCC_SDADC2_IS_CLK_DISABLED
-#define __SDADC3_IS_CLK_ENABLED     __HAL_RCC_SDADC3_IS_CLK_ENABLED
-#define __SDADC3_IS_CLK_DISABLED    __HAL_RCC_SDADC3_IS_CLK_DISABLED
-#define __SRAM_IS_CLK_ENABLED       __HAL_RCC_SRAM_IS_CLK_ENABLED
-#define __SRAM_IS_CLK_DISABLED      __HAL_RCC_SRAM_IS_CLK_DISABLED
-#define __TIM1_IS_CLK_ENABLED       __HAL_RCC_TIM1_IS_CLK_ENABLED
-#define __TIM1_IS_CLK_DISABLED      __HAL_RCC_TIM1_IS_CLK_DISABLED
-#define __TIM2_IS_CLK_ENABLED       __HAL_RCC_TIM2_IS_CLK_ENABLED
-#define __TIM2_IS_CLK_DISABLED      __HAL_RCC_TIM2_IS_CLK_DISABLED
-#define __TIM3_IS_CLK_ENABLED       __HAL_RCC_TIM3_IS_CLK_ENABLED
-#define __TIM3_IS_CLK_DISABLED      __HAL_RCC_TIM3_IS_CLK_DISABLED
-#define __TIM4_IS_CLK_ENABLED       __HAL_RCC_TIM4_IS_CLK_ENABLED
-#define __TIM4_IS_CLK_DISABLED      __HAL_RCC_TIM4_IS_CLK_DISABLED
-#define __TIM5_IS_CLK_ENABLED       __HAL_RCC_TIM5_IS_CLK_ENABLED
-#define __TIM5_IS_CLK_DISABLED      __HAL_RCC_TIM5_IS_CLK_DISABLED
-#define __TIM6_IS_CLK_ENABLED       __HAL_RCC_TIM6_IS_CLK_ENABLED
-#define __TIM6_IS_CLK_DISABLED      __HAL_RCC_TIM6_IS_CLK_DISABLED
-#define __TIM7_IS_CLK_ENABLED       __HAL_RCC_TIM7_IS_CLK_ENABLED
-#define __TIM7_IS_CLK_DISABLED      __HAL_RCC_TIM7_IS_CLK_DISABLED
-#define __TIM8_IS_CLK_ENABLED       __HAL_RCC_TIM8_IS_CLK_ENABLED
-#define __TIM8_IS_CLK_DISABLED      __HAL_RCC_TIM8_IS_CLK_DISABLED
-#define __TIM12_IS_CLK_ENABLED      __HAL_RCC_TIM12_IS_CLK_ENABLED
-#define __TIM12_IS_CLK_DISABLED     __HAL_RCC_TIM12_IS_CLK_DISABLED
-#define __TIM13_IS_CLK_ENABLED      __HAL_RCC_TIM13_IS_CLK_ENABLED
-#define __TIM13_IS_CLK_DISABLED     __HAL_RCC_TIM13_IS_CLK_DISABLED
-#define __TIM14_IS_CLK_ENABLED      __HAL_RCC_TIM14_IS_CLK_ENABLED
-#define __TIM14_IS_CLK_DISABLED     __HAL_RCC_TIM14_IS_CLK_DISABLED
-#define __TIM15_IS_CLK_ENABLED      __HAL_RCC_TIM15_IS_CLK_ENABLED
-#define __TIM15_IS_CLK_DISABLED     __HAL_RCC_TIM15_IS_CLK_DISABLED
-#define __TIM16_IS_CLK_ENABLED      __HAL_RCC_TIM16_IS_CLK_ENABLED
-#define __TIM16_IS_CLK_DISABLED     __HAL_RCC_TIM16_IS_CLK_DISABLED
-#define __TIM17_IS_CLK_ENABLED      __HAL_RCC_TIM17_IS_CLK_ENABLED
-#define __TIM17_IS_CLK_DISABLED     __HAL_RCC_TIM17_IS_CLK_DISABLED
-#define __TIM18_IS_CLK_ENABLED      __HAL_RCC_TIM18_IS_CLK_ENABLED
-#define __TIM18_IS_CLK_DISABLED     __HAL_RCC_TIM18_IS_CLK_DISABLED
-#define __TIM19_IS_CLK_ENABLED      __HAL_RCC_TIM19_IS_CLK_ENABLED
-#define __TIM19_IS_CLK_DISABLED     __HAL_RCC_TIM19_IS_CLK_DISABLED
-#define __TIM20_IS_CLK_ENABLED      __HAL_RCC_TIM20_IS_CLK_ENABLED
-#define __TIM20_IS_CLK_DISABLED     __HAL_RCC_TIM20_IS_CLK_DISABLED
-#define __TSC_IS_CLK_ENABLED        __HAL_RCC_TSC_IS_CLK_ENABLED
-#define __TSC_IS_CLK_DISABLED       __HAL_RCC_TSC_IS_CLK_DISABLED
-#define __UART4_IS_CLK_ENABLED      __HAL_RCC_UART4_IS_CLK_ENABLED
-#define __UART4_IS_CLK_DISABLED     __HAL_RCC_UART4_IS_CLK_DISABLED
-#define __UART5_IS_CLK_ENABLED      __HAL_RCC_UART5_IS_CLK_ENABLED
-#define __UART5_IS_CLK_DISABLED     __HAL_RCC_UART5_IS_CLK_DISABLED
-#define __USART1_IS_CLK_ENABLED     __HAL_RCC_USART1_IS_CLK_ENABLED
-#define __USART1_IS_CLK_DISABLED    __HAL_RCC_USART1_IS_CLK_DISABLED
-#define __USART2_IS_CLK_ENABLED     __HAL_RCC_USART2_IS_CLK_ENABLED
-#define __USART2_IS_CLK_DISABLED    __HAL_RCC_USART2_IS_CLK_DISABLED
-#define __USART3_IS_CLK_ENABLED     __HAL_RCC_USART3_IS_CLK_ENABLED
-#define __USART3_IS_CLK_DISABLED    __HAL_RCC_USART3_IS_CLK_DISABLED
-#define __USB_IS_CLK_ENABLED        __HAL_RCC_USB_IS_CLK_ENABLED
-#define __USB_IS_CLK_DISABLED       __HAL_RCC_USB_IS_CLK_DISABLED
-#define __WWDG_IS_CLK_ENABLED       __HAL_RCC_WWDG_IS_CLK_ENABLED
-#define __WWDG_IS_CLK_DISABLED      __HAL_RCC_WWDG_IS_CLK_DISABLED
-
-#if defined(STM32F4)
-#define __HAL_RCC_SDMMC1_FORCE_RESET       __HAL_RCC_SDIO_FORCE_RESET
-#define __HAL_RCC_SDMMC1_RELEASE_RESET     __HAL_RCC_SDIO_RELEASE_RESET
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE  __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
-#define __HAL_RCC_SDMMC1_CLK_ENABLE        __HAL_RCC_SDIO_CLK_ENABLE
-#define __HAL_RCC_SDMMC1_CLK_DISABLE       __HAL_RCC_SDIO_CLK_DISABLE
-#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED    __HAL_RCC_SDIO_IS_CLK_ENABLED
-#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED   __HAL_RCC_SDIO_IS_CLK_DISABLED
-#define Sdmmc1ClockSelection               SdioClockSelection
-#define RCC_PERIPHCLK_SDMMC1               RCC_PERIPHCLK_SDIO
-#define RCC_SDMMC1CLKSOURCE_CLK48          RCC_SDIOCLKSOURCE_CK48
-#define RCC_SDMMC1CLKSOURCE_SYSCLK         RCC_SDIOCLKSOURCE_SYSCLK
-#define __HAL_RCC_SDMMC1_CONFIG            __HAL_RCC_SDIO_CONFIG
-#define __HAL_RCC_GET_SDMMC1_SOURCE        __HAL_RCC_GET_SDIO_SOURCE
-#endif
-
-#if defined(STM32F7) || defined(STM32L4)
-#define __HAL_RCC_SDIO_FORCE_RESET         __HAL_RCC_SDMMC1_FORCE_RESET
-#define __HAL_RCC_SDIO_RELEASE_RESET       __HAL_RCC_SDMMC1_RELEASE_RESET
-#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE    __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
-#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE   __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
-#define __HAL_RCC_SDIO_CLK_ENABLE          __HAL_RCC_SDMMC1_CLK_ENABLE
-#define __HAL_RCC_SDIO_CLK_DISABLE         __HAL_RCC_SDMMC1_CLK_DISABLE
-#define __HAL_RCC_SDIO_IS_CLK_ENABLED      __HAL_RCC_SDMMC1_IS_CLK_ENABLED
-#define __HAL_RCC_SDIO_IS_CLK_DISABLED     __HAL_RCC_SDMMC1_IS_CLK_DISABLED
-#define SdioClockSelection                 Sdmmc1ClockSelection
-#define RCC_PERIPHCLK_SDIO                 RCC_PERIPHCLK_SDMMC1
-#define __HAL_RCC_SDIO_CONFIG              __HAL_RCC_SDMMC1_CONFIG
-#define __HAL_RCC_GET_SDIO_SOURCE          __HAL_RCC_GET_SDMMC1_SOURCE
-#endif
-
-#if defined(STM32F7)
-#define RCC_SDIOCLKSOURCE_CLK48             RCC_SDMMC1CLKSOURCE_CLK48
-#define RCC_SDIOCLKSOURCE_SYSCLK           RCC_SDMMC1CLKSOURCE_SYSCLK
-#endif
-
-#define __HAL_RCC_I2SCLK            __HAL_RCC_I2S_CONFIG
-#define __HAL_RCC_I2SCLK_CONFIG     __HAL_RCC_I2S_CONFIG
-
-#define __RCC_PLLSRC                RCC_GET_PLL_OSCSOURCE
-
-#define IS_RCC_MSIRANGE             IS_RCC_MSI_CLOCK_RANGE
-#define IS_RCC_RTCCLK_SOURCE        IS_RCC_RTCCLKSOURCE
-#define IS_RCC_SYSCLK_DIV           IS_RCC_HCLK
-#define IS_RCC_HCLK_DIV             IS_RCC_PCLK
-#define IS_RCC_PERIPHCLK            IS_RCC_PERIPHCLOCK
-
-#define RCC_IT_HSI14                RCC_IT_HSI14RDY
-
-#define RCC_IT_CSSLSE               RCC_IT_LSECSS
-#define RCC_IT_CSSHSE               RCC_IT_CSS
-
-#define RCC_PLLMUL_3                RCC_PLL_MUL3
-#define RCC_PLLMUL_4                RCC_PLL_MUL4
-#define RCC_PLLMUL_6                RCC_PLL_MUL6
-#define RCC_PLLMUL_8                RCC_PLL_MUL8
-#define RCC_PLLMUL_12               RCC_PLL_MUL12
-#define RCC_PLLMUL_16               RCC_PLL_MUL16
-#define RCC_PLLMUL_24               RCC_PLL_MUL24
-#define RCC_PLLMUL_32               RCC_PLL_MUL32
-#define RCC_PLLMUL_48               RCC_PLL_MUL48
-
-#define RCC_PLLDIV_2                RCC_PLL_DIV2
-#define RCC_PLLDIV_3                RCC_PLL_DIV3
-#define RCC_PLLDIV_4                RCC_PLL_DIV4
-
-#define IS_RCC_MCOSOURCE            IS_RCC_MCO1SOURCE
-#define __HAL_RCC_MCO_CONFIG        __HAL_RCC_MCO1_CONFIG
-#define RCC_MCO_NODIV               RCC_MCODIV_1
-#define RCC_MCO_DIV1                RCC_MCODIV_1
-#define RCC_MCO_DIV2                RCC_MCODIV_2
-#define RCC_MCO_DIV4                RCC_MCODIV_4
-#define RCC_MCO_DIV8                RCC_MCODIV_8
-#define RCC_MCO_DIV16               RCC_MCODIV_16
-#define RCC_MCO_DIV32               RCC_MCODIV_32
-#define RCC_MCO_DIV64               RCC_MCODIV_64
-#define RCC_MCO_DIV128              RCC_MCODIV_128
-#define RCC_MCOSOURCE_NONE          RCC_MCO1SOURCE_NOCLOCK
-#define RCC_MCOSOURCE_LSI           RCC_MCO1SOURCE_LSI
-#define RCC_MCOSOURCE_LSE           RCC_MCO1SOURCE_LSE
-#define RCC_MCOSOURCE_SYSCLK        RCC_MCO1SOURCE_SYSCLK
-#define RCC_MCOSOURCE_HSI           RCC_MCO1SOURCE_HSI
-#define RCC_MCOSOURCE_HSI14         RCC_MCO1SOURCE_HSI14
-#define RCC_MCOSOURCE_HSI48         RCC_MCO1SOURCE_HSI48
-#define RCC_MCOSOURCE_HSE           RCC_MCO1SOURCE_HSE
-#define RCC_MCOSOURCE_PLLCLK_DIV1   RCC_MCO1SOURCE_PLLCLK
-#define RCC_MCOSOURCE_PLLCLK_NODIV  RCC_MCO1SOURCE_PLLCLK
-#define RCC_MCOSOURCE_PLLCLK_DIV2   RCC_MCO1SOURCE_PLLCLK_DIV2
-
-#define RCC_RTCCLKSOURCE_NONE       RCC_RTCCLKSOURCE_NO_CLK
-
-#define RCC_USBCLK_PLLSAI1          RCC_USBCLKSOURCE_PLLSAI1
-#define RCC_USBCLK_PLL              RCC_USBCLKSOURCE_PLL
-#define RCC_USBCLK_MSI              RCC_USBCLKSOURCE_MSI
-#define RCC_USBCLKSOURCE_PLLCLK     RCC_USBCLKSOURCE_PLL
-#define RCC_USBPLLCLK_DIV1          RCC_USBCLKSOURCE_PLL
-#define RCC_USBPLLCLK_DIV1_5        RCC_USBCLKSOURCE_PLL_DIV1_5
-#define RCC_USBPLLCLK_DIV2          RCC_USBCLKSOURCE_PLL_DIV2
-#define RCC_USBPLLCLK_DIV3          RCC_USBCLKSOURCE_PLL_DIV3
-
-#define HSION_BitNumber        RCC_HSION_BIT_NUMBER
-#define HSION_BITNUMBER        RCC_HSION_BIT_NUMBER
-#define HSEON_BitNumber        RCC_HSEON_BIT_NUMBER
-#define HSEON_BITNUMBER        RCC_HSEON_BIT_NUMBER
-#define MSION_BITNUMBER        RCC_MSION_BIT_NUMBER
-#define CSSON_BitNumber        RCC_CSSON_BIT_NUMBER
-#define CSSON_BITNUMBER        RCC_CSSON_BIT_NUMBER
-#define PLLON_BitNumber        RCC_PLLON_BIT_NUMBER
-#define PLLON_BITNUMBER        RCC_PLLON_BIT_NUMBER
-#define PLLI2SON_BitNumber     RCC_PLLI2SON_BIT_NUMBER
-#define I2SSRC_BitNumber       RCC_I2SSRC_BIT_NUMBER
-#define RTCEN_BitNumber        RCC_RTCEN_BIT_NUMBER
-#define RTCEN_BITNUMBER        RCC_RTCEN_BIT_NUMBER
-#define BDRST_BitNumber        RCC_BDRST_BIT_NUMBER
-#define BDRST_BITNUMBER        RCC_BDRST_BIT_NUMBER
-#define RTCRST_BITNUMBER       RCC_RTCRST_BIT_NUMBER
-#define LSION_BitNumber        RCC_LSION_BIT_NUMBER
-#define LSION_BITNUMBER        RCC_LSION_BIT_NUMBER
-#define LSEON_BitNumber        RCC_LSEON_BIT_NUMBER
-#define LSEON_BITNUMBER        RCC_LSEON_BIT_NUMBER
-#define LSEBYP_BITNUMBER       RCC_LSEBYP_BIT_NUMBER
-#define PLLSAION_BitNumber     RCC_PLLSAION_BIT_NUMBER
-#define TIMPRE_BitNumber       RCC_TIMPRE_BIT_NUMBER
-#define RMVF_BitNumber         RCC_RMVF_BIT_NUMBER
-#define RMVF_BITNUMBER         RCC_RMVF_BIT_NUMBER
-#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
-#define CR_BYTE2_ADDRESS       RCC_CR_BYTE2_ADDRESS
-#define CIR_BYTE1_ADDRESS      RCC_CIR_BYTE1_ADDRESS
-#define CIR_BYTE2_ADDRESS      RCC_CIR_BYTE2_ADDRESS
-#define BDCR_BYTE0_ADDRESS     RCC_BDCR_BYTE0_ADDRESS
-#define DBP_TIMEOUT_VALUE      RCC_DBP_TIMEOUT_VALUE
-#define LSE_TIMEOUT_VALUE      RCC_LSE_TIMEOUT_VALUE
-
-#define CR_HSION_BB            RCC_CR_HSION_BB
-#define CR_CSSON_BB            RCC_CR_CSSON_BB
-#define CR_PLLON_BB            RCC_CR_PLLON_BB
-#define CR_PLLI2SON_BB         RCC_CR_PLLI2SON_BB
-#define CR_MSION_BB            RCC_CR_MSION_BB
-#define CSR_LSION_BB           RCC_CSR_LSION_BB
-#define CSR_LSEON_BB           RCC_CSR_LSEON_BB
-#define CSR_LSEBYP_BB          RCC_CSR_LSEBYP_BB
-#define CSR_RTCEN_BB           RCC_CSR_RTCEN_BB
-#define CSR_RTCRST_BB          RCC_CSR_RTCRST_BB
-#define CFGR_I2SSRC_BB         RCC_CFGR_I2SSRC_BB
-#define BDCR_RTCEN_BB          RCC_BDCR_RTCEN_BB
-#define BDCR_BDRST_BB          RCC_BDCR_BDRST_BB
-#define CR_HSEON_BB            RCC_CR_HSEON_BB
-#define CSR_RMVF_BB            RCC_CSR_RMVF_BB
-#define CR_PLLSAION_BB         RCC_CR_PLLSAION_BB
-#define DCKCFGR_TIMPRE_BB      RCC_DCKCFGR_TIMPRE_BB
-
-#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER     __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
-#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER    __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
-#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB        __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
-#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB       __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
-#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE         __HAL_RCC_CRS_RELOADVALUE_CALCULATE
-
-#define __HAL_RCC_GET_IT_SOURCE                     __HAL_RCC_GET_IT
-
-#define RCC_CRS_SYNCWARM       RCC_CRS_SYNCWARN
-#define RCC_CRS_TRIMOV         RCC_CRS_TRIMOVF
-
-#define RCC_PERIPHCLK_CK48               RCC_PERIPHCLK_CLK48
-#define RCC_CK48CLKSOURCE_PLLQ           RCC_CLK48CLKSOURCE_PLLQ
-#define RCC_CK48CLKSOURCE_PLLSAIP        RCC_CLK48CLKSOURCE_PLLSAIP
-#define RCC_CK48CLKSOURCE_PLLI2SQ        RCC_CLK48CLKSOURCE_PLLI2SQ
-#define IS_RCC_CK48CLKSOURCE             IS_RCC_CLK48CLKSOURCE
-#define RCC_SDIOCLKSOURCE_CK48           RCC_SDIOCLKSOURCE_CLK48
-
-#define __HAL_RCC_DFSDM_CLK_ENABLE             __HAL_RCC_DFSDM1_CLK_ENABLE
-#define __HAL_RCC_DFSDM_CLK_DISABLE            __HAL_RCC_DFSDM1_CLK_DISABLE
-#define __HAL_RCC_DFSDM_IS_CLK_ENABLED         __HAL_RCC_DFSDM1_IS_CLK_ENABLED
-#define __HAL_RCC_DFSDM_IS_CLK_DISABLED        __HAL_RCC_DFSDM1_IS_CLK_DISABLED
-#define __HAL_RCC_DFSDM_FORCE_RESET            __HAL_RCC_DFSDM1_FORCE_RESET
-#define __HAL_RCC_DFSDM_RELEASE_RESET          __HAL_RCC_DFSDM1_RELEASE_RESET
-#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE       __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
-#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE      __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
-#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED   __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED  __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
-#define DfsdmClockSelection         Dfsdm1ClockSelection
-#define RCC_PERIPHCLK_DFSDM         RCC_PERIPHCLK_DFSDM1
-#define RCC_DFSDMCLKSOURCE_PCLK     RCC_DFSDM1CLKSOURCE_PCLK
-#define RCC_DFSDMCLKSOURCE_SYSCLK   RCC_DFSDM1CLKSOURCE_SYSCLK
-#define __HAL_RCC_DFSDM_CONFIG      __HAL_RCC_DFSDM1_CONFIG
-#define __HAL_RCC_GET_DFSDM_SOURCE  __HAL_RCC_GET_DFSDM1_SOURCE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define  HAL_RNG_ReadyCallback(__HANDLE__)  HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG
-#define __HAL_RTC_DISABLE_IT                      __HAL_RTC_EXTI_DISABLE_IT
-#define __HAL_RTC_ENABLE_IT                       __HAL_RTC_EXTI_ENABLE_IT
-
-#if defined (STM32F1)
-#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
-
-#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_ENABLE_IT()
-
-#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_DISABLE_IT()
-
-#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT)    __HAL_RTC_ALARM_EXTI_GET_FLAG()
-
-#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
-#else
-#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
-                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
-                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
-#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__)   (((__EXTI_LINE__)  == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
-                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
-                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
-#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
-                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
-                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
-#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__)    (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
-                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
-                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
-#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__)   (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
-                                                      (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() :  \
-                                                          __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
-#endif   /* STM32F1 */
-
-#define IS_ALARM                                  IS_RTC_ALARM
-#define IS_ALARM_MASK                             IS_RTC_ALARM_MASK
-#define IS_TAMPER                                 IS_RTC_TAMPER
-#define IS_TAMPER_ERASE_MODE                      IS_RTC_TAMPER_ERASE_MODE
-#define IS_TAMPER_FILTER                          IS_RTC_TAMPER_FILTER
-#define IS_TAMPER_INTERRUPT                       IS_RTC_TAMPER_INTERRUPT
-#define IS_TAMPER_MASKFLAG_STATE                  IS_RTC_TAMPER_MASKFLAG_STATE
-#define IS_TAMPER_PRECHARGE_DURATION              IS_RTC_TAMPER_PRECHARGE_DURATION
-#define IS_TAMPER_PULLUP_STATE                    IS_RTC_TAMPER_PULLUP_STATE
-#define IS_TAMPER_SAMPLING_FREQ                   IS_RTC_TAMPER_SAMPLING_FREQ
-#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION     IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
-#define IS_TAMPER_TRIGGER                         IS_RTC_TAMPER_TRIGGER
-#define IS_WAKEUP_CLOCK                           IS_RTC_WAKEUP_CLOCK
-#define IS_WAKEUP_COUNTER                         IS_RTC_WAKEUP_COUNTER
-
-#define __RTC_WRITEPROTECTION_ENABLE  __HAL_RTC_WRITEPROTECTION_ENABLE
-#define __RTC_WRITEPROTECTION_DISABLE  __HAL_RTC_WRITEPROTECTION_DISABLE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define SD_OCR_CID_CSD_OVERWRIETE   SD_OCR_CID_CSD_OVERWRITE
-#define SD_CMD_SD_APP_STAUS         SD_CMD_SD_APP_STATUS
-
-#if defined(STM32F4)
-#define  SD_SDMMC_DISABLED          SD_SDIO_DISABLED
-#define  SD_SDMMC_FUNCTION_BUSY     SD_SDIO_FUNCTION_BUSY
-#define  SD_SDMMC_FUNCTION_FAILED   SD_SDIO_FUNCTION_FAILED
-#define  SD_SDMMC_UNKNOWN_FUNCTION  SD_SDIO_UNKNOWN_FUNCTION
-#define  SD_CMD_SDMMC_SEN_OP_COND   SD_CMD_SDIO_SEN_OP_COND
-#define  SD_CMD_SDMMC_RW_DIRECT     SD_CMD_SDIO_RW_DIRECT
-#define  SD_CMD_SDMMC_RW_EXTENDED   SD_CMD_SDIO_RW_EXTENDED
-#define  __HAL_SD_SDMMC_ENABLE      __HAL_SD_SDIO_ENABLE
-#define  __HAL_SD_SDMMC_DISABLE     __HAL_SD_SDIO_DISABLE
-#define  __HAL_SD_SDMMC_DMA_ENABLE  __HAL_SD_SDIO_DMA_ENABLE
-#define  __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
-#define  __HAL_SD_SDMMC_ENABLE_IT   __HAL_SD_SDIO_ENABLE_IT
-#define  __HAL_SD_SDMMC_DISABLE_IT  __HAL_SD_SDIO_DISABLE_IT
-#define  __HAL_SD_SDMMC_GET_FLAG    __HAL_SD_SDIO_GET_FLAG
-#define  __HAL_SD_SDMMC_CLEAR_FLAG  __HAL_SD_SDIO_CLEAR_FLAG
-#define  __HAL_SD_SDMMC_GET_IT      __HAL_SD_SDIO_GET_IT
-#define  __HAL_SD_SDMMC_CLEAR_IT    __HAL_SD_SDIO_CLEAR_IT
-#define  SDMMC_STATIC_FLAGS         SDIO_STATIC_FLAGS
-#define  SDMMC_CMD0TIMEOUT          SDIO_CMD0TIMEOUT
-#define  SD_SDMMC_SEND_IF_COND      SD_SDIO_SEND_IF_COND
-/* alias CMSIS */
-#define  SDMMC1_IRQn                SDIO_IRQn
-#define  SDMMC1_IRQHandler          SDIO_IRQHandler
-#endif
-
-#if defined(STM32F7) || defined(STM32L4)
-#define  SD_SDIO_DISABLED           SD_SDMMC_DISABLED
-#define  SD_SDIO_FUNCTION_BUSY      SD_SDMMC_FUNCTION_BUSY
-#define  SD_SDIO_FUNCTION_FAILED    SD_SDMMC_FUNCTION_FAILED
-#define  SD_SDIO_UNKNOWN_FUNCTION   SD_SDMMC_UNKNOWN_FUNCTION
-#define  SD_CMD_SDIO_SEN_OP_COND    SD_CMD_SDMMC_SEN_OP_COND
-#define  SD_CMD_SDIO_RW_DIRECT      SD_CMD_SDMMC_RW_DIRECT
-#define  SD_CMD_SDIO_RW_EXTENDED    SD_CMD_SDMMC_RW_EXTENDED
-#define  __HAL_SD_SDIO_ENABLE       __HAL_SD_SDMMC_ENABLE
-#define  __HAL_SD_SDIO_DISABLE      __HAL_SD_SDMMC_DISABLE
-#define  __HAL_SD_SDIO_DMA_ENABLE   __HAL_SD_SDMMC_DMA_ENABLE
-#define  __HAL_SD_SDIO_DMA_DISABL   __HAL_SD_SDMMC_DMA_DISABLE
-#define  __HAL_SD_SDIO_ENABLE_IT    __HAL_SD_SDMMC_ENABLE_IT
-#define  __HAL_SD_SDIO_DISABLE_IT   __HAL_SD_SDMMC_DISABLE_IT
-#define  __HAL_SD_SDIO_GET_FLAG     __HAL_SD_SDMMC_GET_FLAG
-#define  __HAL_SD_SDIO_CLEAR_FLAG   __HAL_SD_SDMMC_CLEAR_FLAG
-#define  __HAL_SD_SDIO_GET_IT       __HAL_SD_SDMMC_GET_IT
-#define  __HAL_SD_SDIO_CLEAR_IT     __HAL_SD_SDMMC_CLEAR_IT
-#define  SDIO_STATIC_FLAGS	        SDMMC_STATIC_FLAGS
-#define  SDIO_CMD0TIMEOUT	          SDMMC_CMD0TIMEOUT
-#define  SD_SDIO_SEND_IF_COND	      SD_SDMMC_SEND_IF_COND
-/* alias CMSIS for compatibilities */
-#define  SDIO_IRQn                  SDMMC1_IRQn
-#define  SDIO_IRQHandler            SDMMC1_IRQHandler
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __SMARTCARD_ENABLE_IT           __HAL_SMARTCARD_ENABLE_IT
-#define __SMARTCARD_DISABLE_IT          __HAL_SMARTCARD_DISABLE_IT
-#define __SMARTCARD_ENABLE              __HAL_SMARTCARD_ENABLE
-#define __SMARTCARD_DISABLE             __HAL_SMARTCARD_DISABLE
-#define __SMARTCARD_DMA_REQUEST_ENABLE  __HAL_SMARTCARD_DMA_REQUEST_ENABLE
-#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
-
-#define __HAL_SMARTCARD_GETCLOCKSOURCE  SMARTCARD_GETCLOCKSOURCE
-#define __SMARTCARD_GETCLOCKSOURCE      SMARTCARD_GETCLOCKSOURCE
-
-#define IS_SMARTCARD_ONEBIT_SAMPLING    IS_SMARTCARD_ONE_BIT_SAMPLE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_SMBUS_RESET_CR1           SMBUS_RESET_CR1
-#define __HAL_SMBUS_RESET_CR2           SMBUS_RESET_CR2
-#define __HAL_SMBUS_GENERATE_START      SMBUS_GENERATE_START
-#define __HAL_SMBUS_GET_ADDR_MATCH      SMBUS_GET_ADDR_MATCH
-#define __HAL_SMBUS_GET_DIR             SMBUS_GET_DIR
-#define __HAL_SMBUS_GET_STOP_MODE       SMBUS_GET_STOP_MODE
-#define __HAL_SMBUS_GET_PEC_MODE        SMBUS_GET_PEC_MODE
-#define __HAL_SMBUS_GET_ALERT_ENABLED   SMBUS_GET_ALERT_ENABLED
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __HAL_SPI_1LINE_TX              SPI_1LINE_TX
-#define __HAL_SPI_1LINE_RX              SPI_1LINE_RX
-#define __HAL_SPI_RESET_CRC             SPI_RESET_CRC
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __HAL_UART_GETCLOCKSOURCE       UART_GETCLOCKSOURCE
-#define __HAL_UART_MASK_COMPUTATION     UART_MASK_COMPUTATION
-#define __UART_GETCLOCKSOURCE           UART_GETCLOCKSOURCE
-#define __UART_MASK_COMPUTATION         UART_MASK_COMPUTATION
-
-#define IS_UART_WAKEUPMETHODE           IS_UART_WAKEUPMETHOD
-
-#define IS_UART_ONEBIT_SAMPLE           IS_UART_ONE_BIT_SAMPLE
-#define IS_UART_ONEBIT_SAMPLING         IS_UART_ONE_BIT_SAMPLE
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __USART_ENABLE_IT               __HAL_USART_ENABLE_IT
-#define __USART_DISABLE_IT              __HAL_USART_DISABLE_IT
-#define __USART_ENABLE                  __HAL_USART_ENABLE
-#define __USART_DISABLE                 __HAL_USART_DISABLE
-
-#define __HAL_USART_GETCLOCKSOURCE      USART_GETCLOCKSOURCE
-#define __USART_GETCLOCKSOURCE          USART_GETCLOCKSOURCE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define USB_EXTI_LINE_WAKEUP                               USB_WAKEUP_EXTI_LINE
-
-#define USB_FS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
-#define USB_FS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
-#define USB_FS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
-#define USB_FS_EXTI_LINE_WAKEUP                            USB_OTG_FS_WAKEUP_EXTI_LINE
-
-#define USB_HS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
-#define USB_HS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
-#define USB_HS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
-#define USB_HS_EXTI_LINE_WAKEUP                            USB_OTG_HS_WAKEUP_EXTI_LINE
-
-#define __HAL_USB_EXTI_ENABLE_IT                           __HAL_USB_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_USB_EXTI_DISABLE_IT                          __HAL_USB_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_USB_EXTI_GET_FLAG                            __HAL_USB_WAKEUP_EXTI_GET_FLAG
-#define __HAL_USB_EXTI_CLEAR_FLAG                          __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER             __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
-#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER            __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER           __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
-
-#define __HAL_USB_FS_EXTI_ENABLE_IT                        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_USB_FS_EXTI_DISABLE_IT                       __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_USB_FS_EXTI_GET_FLAG                         __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
-#define __HAL_USB_FS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
-#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
-#define __HAL_USB_FS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
-
-#define __HAL_USB_HS_EXTI_ENABLE_IT                        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_USB_HS_EXTI_DISABLE_IT                       __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_USB_HS_EXTI_GET_FLAG                         __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
-#define __HAL_USB_HS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
-#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
-#define __HAL_USB_HS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
-
-#define HAL_PCD_ActiveRemoteWakeup                         HAL_PCD_ActivateRemoteWakeup
-#define HAL_PCD_DeActiveRemoteWakeup                       HAL_PCD_DeActivateRemoteWakeup
-
-#define HAL_PCD_SetTxFiFo                                  HAL_PCDEx_SetTxFiFo
-#define HAL_PCD_SetRxFiFo                                  HAL_PCDEx_SetRxFiFo
-/**
-  * @}
-  */
-
-/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_TIM_SetICPrescalerValue   TIM_SET_ICPRESCALERVALUE
-#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
-
-#define TIM_GET_ITSTATUS                __HAL_TIM_GET_IT_SOURCE
-#define TIM_GET_CLEAR_IT                __HAL_TIM_CLEAR_IT
-
-#define __HAL_TIM_GET_ITSTATUS          __HAL_TIM_GET_IT_SOURCE
-
-#define __HAL_TIM_DIRECTION_STATUS      __HAL_TIM_IS_TIM_COUNTING_DOWN
-#define __HAL_TIM_PRESCALER             __HAL_TIM_SET_PRESCALER
-#define __HAL_TIM_SetCounter            __HAL_TIM_SET_COUNTER
-#define __HAL_TIM_GetCounter            __HAL_TIM_GET_COUNTER
-#define __HAL_TIM_SetAutoreload         __HAL_TIM_SET_AUTORELOAD
-#define __HAL_TIM_GetAutoreload         __HAL_TIM_GET_AUTORELOAD
-#define __HAL_TIM_SetClockDivision      __HAL_TIM_SET_CLOCKDIVISION
-#define __HAL_TIM_GetClockDivision      __HAL_TIM_GET_CLOCKDIVISION
-#define __HAL_TIM_SetICPrescaler        __HAL_TIM_SET_ICPRESCALER
-#define __HAL_TIM_GetICPrescaler        __HAL_TIM_GET_ICPRESCALER
-#define __HAL_TIM_SetCompare            __HAL_TIM_SET_COMPARE
-#define __HAL_TIM_GetCompare            __HAL_TIM_GET_COMPARE
-
-#define TIM_BREAKINPUTSOURCE_DFSDM  TIM_BREAKINPUTSOURCE_DFSDM1
-/**
-  * @}
-  */
-
-/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __HAL_ETH_EXTI_ENABLE_IT                   __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_ETH_EXTI_DISABLE_IT                  __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_ETH_EXTI_GET_FLAG                    __HAL_ETH_WAKEUP_EXTI_GET_FLAG
-#define __HAL_ETH_EXTI_CLEAR_FLAG                  __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER     __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
-#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER    __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
-#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER   __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
-
-#define ETH_PROMISCIOUSMODE_ENABLE   ETH_PROMISCUOUS_MODE_ENABLE
-#define ETH_PROMISCIOUSMODE_DISABLE  ETH_PROMISCUOUS_MODE_DISABLE
-#define IS_ETH_PROMISCIOUS_MODE      IS_ETH_PROMISCUOUS_MODE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_LTDC_LAYER LTDC_LAYER
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define SAI_OUTPUTDRIVE_DISABLED          SAI_OUTPUTDRIVE_DISABLE
-#define SAI_OUTPUTDRIVE_ENABLED           SAI_OUTPUTDRIVE_ENABLE
-#define SAI_MASTERDIVIDER_ENABLED         SAI_MASTERDIVIDER_ENABLE
-#define SAI_MASTERDIVIDER_DISABLED        SAI_MASTERDIVIDER_DISABLE
-#define SAI_STREOMODE                     SAI_STEREOMODE
-#define SAI_FIFOStatus_Empty              SAI_FIFOSTATUS_EMPTY
-#define SAI_FIFOStatus_Less1QuarterFull   SAI_FIFOSTATUS_LESS1QUARTERFULL
-#define SAI_FIFOStatus_1QuarterFull       SAI_FIFOSTATUS_1QUARTERFULL
-#define SAI_FIFOStatus_HalfFull           SAI_FIFOSTATUS_HALFFULL
-#define SAI_FIFOStatus_3QuartersFull      SAI_FIFOSTATUS_3QUARTERFULL
-#define SAI_FIFOStatus_Full               SAI_FIFOSTATUS_FULL
-#define IS_SAI_BLOCK_MONO_STREO_MODE      IS_SAI_BLOCK_MONO_STEREO_MODE
-#define SAI_SYNCHRONOUS_EXT               SAI_SYNCHRONOUS_EXT_SAI1
-#define SAI_SYNCEXT_IN_ENABLE             SAI_SYNCEXT_OUTBLOCKA_ENABLE
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ___STM32_HAL_LEGACY */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal.h b/stmhal/hal/f7/inc/stm32f7xx_hal.h
deleted file mode 100644
index 47335ee8f1..0000000000
--- a/stmhal/hal/f7/inc/stm32f7xx_hal.h
+++ /dev/null
@@ -1,253 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal.h
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   This file contains all the functions prototypes for the HAL
-  *          module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_H
-#define __STM32F7xx_HAL_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal_conf.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup HAL
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
-  * @{
-  */
-
-/** @defgroup SYSCFG_BootMode Boot Mode
-  * @{
-  */
-#define SYSCFG_MEM_BOOT_ADD0          ((uint32_t)0x00000000U)
-#define SYSCFG_MEM_BOOT_ADD1          SYSCFG_MEMRMP_MEM_BOOT
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup HAL_Exported_Macros HAL Exported Macros
-  * @{
-  */
-
-/** @brief  Freeze/Unfreeze Peripherals in Debug mode
-  */
-#define __HAL_DBGMCU_FREEZE_TIM2()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM3()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM4()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM5()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM6()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM7()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM12()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM13()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM14()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
-#define __HAL_DBGMCU_FREEZE_LPTIM1()         (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_LPTIM1_STOP))
-#define __HAL_DBGMCU_FREEZE_RTC()            (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
-#define __HAL_DBGMCU_FREEZE_WWDG()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
-#define __HAL_DBGMCU_FREEZE_IWDG()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
-#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
-#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
-#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
-#define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT))
-#define __HAL_DBGMCU_FREEZE_CAN1()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP))
-#define __HAL_DBGMCU_FREEZE_CAN2()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM1()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM8()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM9()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM10()          (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM11()          (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP))
-
-#define __HAL_DBGMCU_UNFREEZE_TIM2()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM3()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM4()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM5()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM6()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM7()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM12()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM13()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM14()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
-#define __HAL_DBGMCU_UNFREEZE_LPTIM1()         (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_LPTIM1_STOP))
-#define __HAL_DBGMCU_UNFREEZE_RTC()            (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
-#define __HAL_DBGMCU_UNFREEZE_WWDG()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
-#define __HAL_DBGMCU_UNFREEZE_IWDG()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
-#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
-#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
-#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
-#define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT))
-#define __HAL_DBGMCU_UNFREEZE_CAN1()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP))
-#define __HAL_DBGMCU_UNFREEZE_CAN2()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM1()           (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM8()           (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM9()           (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM10()          (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM11()          (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP))
-
-
-/** @brief  FMC (NOR/RAM) mapped at 0x60000000 and SDRAM mapped at 0xC0000000
-  */
-#define __HAL_SYSCFG_REMAPMEMORY_FMC()          (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_SWP_FMC))
-
-
-/** @brief  FMC/SDRAM  mapped at 0x60000000 (NOR/RAM) mapped at 0xC0000000
-  */
-#define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_SWP_FMC);\
-                                          SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_SWP_FMC_0);\
-                                         }while(0);
-/**
-  * @brief  Return the memory boot mapping as configured by user.
-  * @retval The boot mode as configured by user. The returned value can be one
-  *         of the following values:
-  *           @arg @ref SYSCFG_MEM_BOOT_ADD0
-  *           @arg @ref SYSCFG_MEM_BOOT_ADD1
-  */
-#define __HAL_SYSCFG_GET_BOOT_MODE()           READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_BOOT)
-
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-/** @brief  SYSCFG Break Cortex-M7 Lockup lock.
-  *         Enable and lock the connection of Cortex-M7 LOCKUP (Hardfault) output to TIM1/8 Break input.
-  * @note   The selected configuration is locked and can be unlocked only by system reset.
-  */
-#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK()     SET_BIT(SYSCFG->CBR, SYSCFG_CBR_CLL)
-
-/** @brief  SYSCFG Break PVD lock.
-  *         Enable and lock the PVD connection to Timer1/8 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR1 register.
-  * @note   The selected configuration is locked and can be unlocked only by system reset.
-  */
-#define __HAL_SYSCFG_BREAK_PVD_LOCK()        SET_BIT(SYSCFG->CBR, SYSCFG_CBR_PVDL)
-#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup HAL_Exported_Functions
-  * @{
-  */
-/** @addtogroup HAL_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization and de-initialization functions  ******************************/
-HAL_StatusTypeDef HAL_Init(void);
-HAL_StatusTypeDef HAL_DeInit(void);
-void HAL_MspInit(void);
-void HAL_MspDeInit(void);
-HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
-/**
-  * @}
-  */
-
-/** @addtogroup HAL_Exported_Functions_Group2
-  * @{
-  */
-/* Peripheral Control functions  ************************************************/
-void HAL_IncTick(void);
-void HAL_Delay(__IO uint32_t Delay);
-uint32_t HAL_GetTick(void);
-void HAL_SuspendTick(void);
-void HAL_ResumeTick(void);
-uint32_t HAL_GetHalVersion(void);
-uint32_t HAL_GetREVID(void);
-uint32_t HAL_GetDEVID(void);
-void HAL_DBGMCU_EnableDBGSleepMode(void);
-void HAL_DBGMCU_DisableDBGSleepMode(void);
-void HAL_DBGMCU_EnableDBGStopMode(void);
-void HAL_DBGMCU_DisableDBGStopMode(void);
-void HAL_DBGMCU_EnableDBGStandbyMode(void);
-void HAL_DBGMCU_DisableDBGStandbyMode(void);
-void HAL_EnableCompensationCell(void);
-void HAL_DisableCompensationCell(void);
-void HAL_EnableFMCMemorySwapping(void);
-void HAL_DisableFMCMemorySwapping(void);
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-void HAL_EnableMemorySwappingBank(void);
-void HAL_DisableMemorySwappingBank(void);
-#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup HAL_Private_Variables HAL Private Variables
-  * @{
-  */
-/**
-  * @}
-  */
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup HAL_Private_Constants HAL Private Constants
-  * @{
-  */
-/**
-  * @}
-  */
-/* Private macros ------------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F7xx_HAL_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_adc.h b/stmhal/hal/f7/inc/stm32f7xx_hal_adc.h
deleted file mode 100644
index 83c0f5864b..0000000000
--- a/stmhal/hal/f7/inc/stm32f7xx_hal_adc.h
+++ /dev/null
@@ -1,860 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_adc.h
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   Header file of ADC HAL extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_ADC_H
-#define __STM32F7xx_ADC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal_def.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup ADC
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup ADC_Exported_Types ADC Exported Types
-  * @{
-  */
-
-/**
-  * @brief  Structure definition of ADC and regular group initialization
-  * @note   Parameters of this structure are shared within 2 scopes:
-  *          - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank.
-  *          - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
-  * @note   The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
-  *         ADC state can be either:
-  *          - For all parameters: ADC disabled
-  *          - For all parameters except 'Resolution', 'ScanConvMode', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group.
-  *          - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going.
-  *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
-  *         without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fullfills the ADC state condition) on the fly).
-  */
-typedef struct
-{
-  uint32_t ClockPrescaler;        /*!< Select ADC clock prescaler. The clock is common for
-                                       all the ADCs.
-                                       This parameter can be a value of @ref ADC_ClockPrescaler */
-  uint32_t Resolution;            /*!< Configures the ADC resolution.
-                                       This parameter can be a value of @ref ADC_Resolution */
-  uint32_t DataAlign;             /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
-                                       or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
-                                       This parameter can be a value of @ref ADC_Data_Align */
-  uint32_t ScanConvMode;          /*!< Configures the sequencer of regular and injected groups.
-                                       This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
-                                       If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
-                                                    Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
-                                       If enabled:  Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
-                                                    Scan direction is upward: from rank1 to rank 'n'.
-                                       This parameter can be set to ENABLE or DISABLE */
-  uint32_t EOCSelection;          /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
-                                       This parameter can be a value of @ref ADC_EOCSelection.
-                                       Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence.
-                                             Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT)
-                                             or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion.
-                                       Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()).
-                                             If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */
-  uint32_t ContinuousConvMode;    /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
-                                       after the selected trigger occurred (software start or external trigger).
-                                       This parameter can be set to ENABLE or DISABLE. */
-  uint32_t NbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
-                                       To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
-                                       This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
-  uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
-                                       Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
-                                       Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
-                                       This parameter can be set to ENABLE or DISABLE. */
-  uint32_t NbrOfDiscConversion;   /*!< Specifies the number of discontinuous conversions in which the  main sequence of regular group (parameter NbrOfConversion) will be subdivided.
-                                       If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
-                                       This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
-  uint32_t ExternalTrigConv;      /*!< Selects the external event used to trigger the conversion start of regular group.
-                                       If set to ADC_SOFTWARE_START, external triggers are disabled.
-                                       If set to external trigger source, triggering is on event rising edge by default.
-                                       This parameter can be a value of @ref ADC_External_trigger_Source_Regular */
-  uint32_t ExternalTrigConvEdge;  /*!< Selects the external trigger edge of regular group.
-                                       If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
-                                       This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
-  uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
-                                       or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
-                                       Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
-                                       Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).
-                                       This parameter can be set to ENABLE or DISABLE. */
-}ADC_InitTypeDef;
-
-
-
-/**
-  * @brief  Structure definition of ADC channel for regular group
-  * @note   The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
-  *         ADC can be either disabled or enabled without conversion on going on regular group.
-  */
-typedef struct
-{
-  uint32_t Channel;                /*!< Specifies the channel to configure into ADC regular group.
-                                        This parameter can be a value of @ref ADC_channels */
-  uint32_t Rank;                   /*!< Specifies the rank in the regular group sequencer.
-                                        This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
-  uint32_t SamplingTime;           /*!< Sampling time value to be set for the selected channel.
-                                        Unit: ADC clock cycles
-                                        Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
-                                        This parameter can be a value of @ref ADC_sampling_times
-                                        Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
-                                                 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
-                                        Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
-                                              sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
-                                              Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
-  uint32_t Offset;                 /*!< Reserved for future use, can be set to 0 */
-}ADC_ChannelConfTypeDef;
-
-/**
-  * @brief ADC Configuration multi-mode structure definition
-  */
-typedef struct
-{
-  uint32_t WatchdogMode;      /*!< Configures the ADC analog watchdog mode.
-                                   This parameter can be a value of @ref ADC_analog_watchdog_selection */
-  uint32_t HighThreshold;     /*!< Configures the ADC analog watchdog High threshold value.
-                                   This parameter must be a 12-bit value. */
-  uint32_t LowThreshold;      /*!< Configures the ADC analog watchdog High threshold value.
-                                   This parameter must be a 12-bit value. */
-  uint32_t Channel;           /*!< Configures ADC channel for the analog watchdog.
-                                   This parameter has an effect only if watchdog mode is configured on single channel
-                                   This parameter can be a value of @ref ADC_channels */
-  uint32_t ITMode;            /*!< Specifies whether the analog watchdog is configured
-                                   is interrupt mode or in polling mode.
-                                   This parameter can be set to ENABLE or DISABLE */
-  uint32_t WatchdogNumber;    /*!< Reserved for future use, can be set to 0 */
-}ADC_AnalogWDGConfTypeDef;
-
-/**
-  * @brief  HAL ADC state machine: ADC states definition (bitfields)
-  */
-/* States of ADC global scope */
-#define HAL_ADC_STATE_RESET             ((uint32_t)0x00000000U)    /*!< ADC not yet initialized or disabled */
-#define HAL_ADC_STATE_READY             ((uint32_t)0x00000001U)    /*!< ADC peripheral ready for use */
-#define HAL_ADC_STATE_BUSY_INTERNAL     ((uint32_t)0x00000002U)    /*!< ADC is busy to internal process (initialization, calibration) */
-#define HAL_ADC_STATE_TIMEOUT           ((uint32_t)0x00000004U)    /*!< TimeOut occurrence */
-
-/* States of ADC errors */
-#define HAL_ADC_STATE_ERROR_INTERNAL    ((uint32_t)0x00000010U)    /*!< Internal error occurrence */
-#define HAL_ADC_STATE_ERROR_CONFIG      ((uint32_t)0x00000020U)    /*!< Configuration error occurrence */
-#define HAL_ADC_STATE_ERROR_DMA         ((uint32_t)0x00000040U)    /*!< DMA error occurrence */
-
-/* States of ADC group regular */
-#define HAL_ADC_STATE_REG_BUSY          ((uint32_t)0x00000100U)    /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
-                                                                       external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
-#define HAL_ADC_STATE_REG_EOC           ((uint32_t)0x00000200U)    /*!< Conversion data available on group regular */
-#define HAL_ADC_STATE_REG_OVR           ((uint32_t)0x00000400U)    /*!< Overrun occurrence */
-
-/* States of ADC group injected */
-#define HAL_ADC_STATE_INJ_BUSY          ((uint32_t)0x00001000U)    /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
-                                                                       external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
-#define HAL_ADC_STATE_INJ_EOC           ((uint32_t)0x00002000U)    /*!< Conversion data available on group injected */
-
-/* States of ADC analog watchdogs */
-#define HAL_ADC_STATE_AWD1              ((uint32_t)0x00010000U)    /*!< Out-of-window occurrence of analog watchdog 1 */
-#define HAL_ADC_STATE_AWD2              ((uint32_t)0x00020000U)    /*!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 2 */
-#define HAL_ADC_STATE_AWD3              ((uint32_t)0x00040000U)    /*!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 3 */
-
-/* States of ADC multi-mode */
-#define HAL_ADC_STATE_MULTIMODE_SLAVE   ((uint32_t)0x00100000U)    /*!< Not available on STM32F7 device: ADC in multimode slave state, controlled by another ADC master ( */
-
-
-/**
-  * @brief  ADC handle Structure definition
-  */
-typedef struct
-{
-  ADC_TypeDef                   *Instance;                   /*!< Register base address */
-
-  ADC_InitTypeDef               Init;                        /*!< ADC required parameters */
-
-  __IO uint32_t                 NbrOfCurrentConversionRank;  /*!< ADC number of current conversion rank */
-
-  DMA_HandleTypeDef             *DMA_Handle;                 /*!< Pointer DMA Handler */
-
-  HAL_LockTypeDef               Lock;                        /*!< ADC locking object */
-
-  __IO uint32_t                 State;                       /*!< ADC communication state */
-
-  __IO uint32_t                 ErrorCode;                   /*!< ADC Error code */
-}ADC_HandleTypeDef;
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup ADC_Exported_Constants ADC Exported Constants
-  * @{
-  */
-
-/** @defgroup ADC_Error_Code ADC Error Code
-  * @{
-  */
-#define HAL_ADC_ERROR_NONE        ((uint32_t)0x00U)   /*!< No error                                              */
-#define HAL_ADC_ERROR_INTERNAL    ((uint32_t)0x01U)   /*!< ADC IP internal error: if problem of clocking,
-                                                          enable/disable, erroneous state                       */
-#define HAL_ADC_ERROR_OVR         ((uint32_t)0x02U)   /*!< Overrun error                                         */
-#define HAL_ADC_ERROR_DMA         ((uint32_t)0x04U)   /*!< DMA transfer error                                    */
-/**
-  * @}
-  */
-
-
-/** @defgroup ADC_ClockPrescaler  ADC Clock Prescaler
-  * @{
-  */
-#define ADC_CLOCK_SYNC_PCLK_DIV2    ((uint32_t)0x00000000U)
-#define ADC_CLOCK_SYNC_PCLK_DIV4    ((uint32_t)ADC_CCR_ADCPRE_0)
-#define ADC_CLOCK_SYNC_PCLK_DIV6    ((uint32_t)ADC_CCR_ADCPRE_1)
-#define ADC_CLOCK_SYNC_PCLK_DIV8    ((uint32_t)ADC_CCR_ADCPRE)
-/**
-  * @}
-  */
-
-/** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases
-  * @{
-  */
-#define ADC_TWOSAMPLINGDELAY_5CYCLES    ((uint32_t)0x00000000U)
-#define ADC_TWOSAMPLINGDELAY_6CYCLES    ((uint32_t)ADC_CCR_DELAY_0)
-#define ADC_TWOSAMPLINGDELAY_7CYCLES    ((uint32_t)ADC_CCR_DELAY_1)
-#define ADC_TWOSAMPLINGDELAY_8CYCLES    ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
-#define ADC_TWOSAMPLINGDELAY_9CYCLES    ((uint32_t)ADC_CCR_DELAY_2)
-#define ADC_TWOSAMPLINGDELAY_10CYCLES   ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
-#define ADC_TWOSAMPLINGDELAY_11CYCLES   ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
-#define ADC_TWOSAMPLINGDELAY_12CYCLES   ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
-#define ADC_TWOSAMPLINGDELAY_13CYCLES   ((uint32_t)ADC_CCR_DELAY_3)
-#define ADC_TWOSAMPLINGDELAY_14CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))
-#define ADC_TWOSAMPLINGDELAY_15CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))
-#define ADC_TWOSAMPLINGDELAY_16CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
-#define ADC_TWOSAMPLINGDELAY_17CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))
-#define ADC_TWOSAMPLINGDELAY_18CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
-#define ADC_TWOSAMPLINGDELAY_19CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
-#define ADC_TWOSAMPLINGDELAY_20CYCLES   ((uint32_t)ADC_CCR_DELAY)
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Resolution ADC Resolution
-  * @{
-  */
-#define ADC_RESOLUTION_12B  ((uint32_t)0x00000000U)
-#define ADC_RESOLUTION_10B  ((uint32_t)ADC_CR1_RES_0)
-#define ADC_RESOLUTION_8B   ((uint32_t)ADC_CR1_RES_1)
-#define ADC_RESOLUTION_6B   ((uint32_t)ADC_CR1_RES)
-/**
-  * @}
-  */
-
-/** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular
-  * @{
-  */
-#define ADC_EXTERNALTRIGCONVEDGE_NONE           ((uint32_t)0x00000000U)
-#define ADC_EXTERNALTRIGCONVEDGE_RISING         ((uint32_t)ADC_CR2_EXTEN_0)
-#define ADC_EXTERNALTRIGCONVEDGE_FALLING        ((uint32_t)ADC_CR2_EXTEN_1)
-#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING  ((uint32_t)ADC_CR2_EXTEN)
-/**
-  * @}
-  */
-
-/** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular
-  * @{
-  */
-/* Note: Parameter ADC_SOFTWARE_START is a software parameter used for        */
-/*       compatibility with other STM32 devices.                              */
-
-
-#define ADC_EXTERNALTRIGCONV_T1_CC1    ((uint32_t)0x00000000U)
-#define ADC_EXTERNALTRIGCONV_T1_CC2    ((uint32_t)ADC_CR2_EXTSEL_0)
-#define ADC_EXTERNALTRIGCONV_T1_CC3    ((uint32_t)ADC_CR2_EXTSEL_1)
-#define ADC_EXTERNALTRIGCONV_T2_CC2    ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
-#define ADC_EXTERNALTRIGCONV_T5_TRGO   ((uint32_t)ADC_CR2_EXTSEL_2)
-#define ADC_EXTERNALTRIGCONV_T4_CC4    ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
-#define ADC_EXTERNALTRIGCONV_T3_CC4    ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
-#define ADC_EXTERNALTRIGCONV_T8_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
-#define ADC_EXTERNALTRIGCONV_T8_TRGO2  ((uint32_t)ADC_CR2_EXTSEL_3)
-#define ADC_EXTERNALTRIGCONV_T1_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0))
-#define ADC_EXTERNALTRIGCONV_T1_TRGO2  ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1))
-#define ADC_EXTERNALTRIGCONV_T2_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
-#define ADC_EXTERNALTRIGCONV_T4_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2))
-#define ADC_EXTERNALTRIGCONV_T6_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
-
-#define ADC_EXTERNALTRIGCONV_EXT_IT11  ((uint32_t)ADC_CR2_EXTSEL)
-#define ADC_SOFTWARE_START             ((uint32_t)ADC_CR2_EXTSEL + 1)
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Data_Align ADC Data Align
-  * @{
-  */
-#define ADC_DATAALIGN_RIGHT      ((uint32_t)0x00000000U)
-#define ADC_DATAALIGN_LEFT       ((uint32_t)ADC_CR2_ALIGN)
-/**
-  * @}
-  */
-
-/** @defgroup ADC_channels ADC Common Channels
-  * @{
-  */
-#define ADC_CHANNEL_0           ((uint32_t)0x00000000U)
-#define ADC_CHANNEL_1           ((uint32_t)ADC_CR1_AWDCH_0)
-#define ADC_CHANNEL_2           ((uint32_t)ADC_CR1_AWDCH_1)
-#define ADC_CHANNEL_3           ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
-#define ADC_CHANNEL_4           ((uint32_t)ADC_CR1_AWDCH_2)
-#define ADC_CHANNEL_5           ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
-#define ADC_CHANNEL_6           ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
-#define ADC_CHANNEL_7           ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
-#define ADC_CHANNEL_8           ((uint32_t)ADC_CR1_AWDCH_3)
-#define ADC_CHANNEL_9           ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0))
-#define ADC_CHANNEL_10          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1))
-#define ADC_CHANNEL_11          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
-#define ADC_CHANNEL_12          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2))
-#define ADC_CHANNEL_13          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
-#define ADC_CHANNEL_14          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
-#define ADC_CHANNEL_15          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
-#define ADC_CHANNEL_16          ((uint32_t)ADC_CR1_AWDCH_4)
-#define ADC_CHANNEL_17          ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))
-#define ADC_CHANNEL_18          ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))
-
-#define ADC_CHANNEL_VREFINT     ((uint32_t)ADC_CHANNEL_17)
-#define ADC_CHANNEL_VBAT        ((uint32_t)ADC_CHANNEL_18)
-/**
-  * @}
-  */
-
-/** @defgroup ADC_sampling_times ADC Sampling Times
-  * @{
-  */
-#define ADC_SAMPLETIME_3CYCLES    ((uint32_t)0x00000000U)
-#define ADC_SAMPLETIME_15CYCLES   ((uint32_t)ADC_SMPR1_SMP10_0)
-#define ADC_SAMPLETIME_28CYCLES   ((uint32_t)ADC_SMPR1_SMP10_1)
-#define ADC_SAMPLETIME_56CYCLES   ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))
-#define ADC_SAMPLETIME_84CYCLES   ((uint32_t)ADC_SMPR1_SMP10_2)
-#define ADC_SAMPLETIME_112CYCLES  ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0))
-#define ADC_SAMPLETIME_144CYCLES  ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1))
-#define ADC_SAMPLETIME_480CYCLES  ((uint32_t)ADC_SMPR1_SMP10)
-/**
-  * @}
-  */
-
-  /** @defgroup ADC_EOCSelection ADC EOC Selection
-  * @{
-  */
-#define ADC_EOC_SEQ_CONV              ((uint32_t)0x00000000U)
-#define ADC_EOC_SINGLE_CONV           ((uint32_t)0x00000001U)
-#define ADC_EOC_SINGLE_SEQ_CONV       ((uint32_t)0x00000002U)  /*!< reserved for future use */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Event_type ADC Event Type
-  * @{
-  */
-#define ADC_AWD_EVENT             ((uint32_t)ADC_FLAG_AWD)
-#define ADC_OVR_EVENT             ((uint32_t)ADC_FLAG_OVR)
-/**
-  * @}
-  */
-
-/** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection
-  * @{
-  */
-#define ADC_ANALOGWATCHDOG_SINGLE_REG         ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
-#define ADC_ANALOGWATCHDOG_SINGLE_INJEC       ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
-#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC    ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
-#define ADC_ANALOGWATCHDOG_ALL_REG            ((uint32_t)ADC_CR1_AWDEN)
-#define ADC_ANALOGWATCHDOG_ALL_INJEC          ((uint32_t)ADC_CR1_JAWDEN)
-#define ADC_ANALOGWATCHDOG_ALL_REGINJEC       ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
-#define ADC_ANALOGWATCHDOG_NONE               ((uint32_t)0x00000000U)
-/**
-  * @}
-  */
-
-/** @defgroup ADC_interrupts_definition ADC Interrupts Definition
-  * @{
-  */
-#define ADC_IT_EOC      ((uint32_t)ADC_CR1_EOCIE)
-#define ADC_IT_AWD      ((uint32_t)ADC_CR1_AWDIE)
-#define ADC_IT_JEOC     ((uint32_t)ADC_CR1_JEOCIE)
-#define ADC_IT_OVR      ((uint32_t)ADC_CR1_OVRIE)
-/**
-  * @}
-  */
-
-/** @defgroup ADC_flags_definition ADC Flags Definition
-  * @{
-  */
-#define ADC_FLAG_AWD    ((uint32_t)ADC_SR_AWD)
-#define ADC_FLAG_EOC    ((uint32_t)ADC_SR_EOC)
-#define ADC_FLAG_JEOC   ((uint32_t)ADC_SR_JEOC)
-#define ADC_FLAG_JSTRT  ((uint32_t)ADC_SR_JSTRT)
-#define ADC_FLAG_STRT   ((uint32_t)ADC_SR_STRT)
-#define ADC_FLAG_OVR    ((uint32_t)ADC_SR_OVR)
-/**
-  * @}
-  */
-
-/** @defgroup ADC_channels_type ADC Channels Type
-  * @{
-  */
-#define ADC_ALL_CHANNELS      ((uint32_t)0x00000001U)
-#define ADC_REGULAR_CHANNELS  ((uint32_t)0x00000002U) /*!< reserved for future use */
-#define ADC_INJECTED_CHANNELS ((uint32_t)0x00000003U) /*!< reserved for future use */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup ADC_Exported_Macros ADC Exported Macros
-  * @{
-  */
-
-/** @brief Reset ADC handle state
-  * @param  __HANDLE__: ADC handle
-  * @retval None
-  */
-#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
-
-/**
-  * @brief  Enable the ADC peripheral.
-  * @param  __HANDLE__: ADC handle
-  * @retval None
-  */
-#define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |=  ADC_CR2_ADON)
-
-/**
-  * @brief  Disable the ADC peripheral.
-  * @param  __HANDLE__: ADC handle
-  * @retval None
-  */
-#define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &=  ~ADC_CR2_ADON)
-
-/**
-  * @brief  Enable the ADC end of conversion interrupt.
-  * @param  __HANDLE__: specifies the ADC Handle.
-  * @param  __INTERRUPT__: ADC Interrupt.
-  * @retval None
-  */
-#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the ADC end of conversion interrupt.
-  * @param  __HANDLE__: specifies the ADC Handle.
-  * @param  __INTERRUPT__: ADC interrupt.
-  * @retval None
-  */
-#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))
-
-/** @brief  Check if the specified ADC interrupt source is enabled or disabled.
-  * @param  __HANDLE__: specifies the ADC Handle.
-  * @param  __INTERRUPT__: specifies the ADC interrupt source to check.
-  * @retval The new state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/**
-  * @brief  Clear the ADC's pending flags.
-  * @param  __HANDLE__: specifies the ADC Handle.
-  * @param  __FLAG__: ADC flag.
-  * @retval None
-  */
-#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
-
-/**
-  * @brief  Get the selected ADC's flag status.
-  * @param  __HANDLE__: specifies the ADC Handle.
-  * @param  __FLAG__: ADC flag.
-  * @retval None
-  */
-#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/**
-  * @}
-  */
-
-/* Include ADC HAL Extension module */
-#include "stm32f7xx_hal_adc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup ADC_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup ADC_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization/de-initialization functions ***********************************/
-HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
-void       HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
-void       HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
-/**
-  * @}
-  */
-
-/** @addtogroup ADC_Exported_Functions_Group2
-  * @{
-  */
-/* I/O operation functions ******************************************************/
-HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
-
-HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
-
-HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
-
-void              HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
-
-HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
-HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
-
-uint32_t          HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
-
-void       HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
-void       HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
-void       HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
-void       HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
-/**
-  * @}
-  */
-
-/** @addtogroup ADC_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral Control functions *************************************************/
-HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
-HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
-/**
-  * @}
-  */
-
-/** @addtogroup ADC_Exported_Functions_Group4
-  * @{
-  */
-/* Peripheral State functions ***************************************************/
-uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
-uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup ADC_Private_Constants ADC Private Constants
-  * @{
-  */
-/* Delay for ADC stabilization time.                                        */
-/* Maximum delay is 1us (refer to device datasheet, parameter tSTAB).       */
-/* Unit: us                                                                 */
-#define ADC_STAB_DELAY_US               ((uint32_t) 3U)
-/* Delay for temperature sensor stabilization time.                         */
-/* Maximum delay is 10us (refer to device datasheet, parameter tSTART).     */
-/* Unit: us                                                                 */
-#define ADC_TEMPSENSOR_DELAY_US         ((uint32_t) 10U)
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup ADC_Private_Macros ADC Private Macros
-  * @{
-  */
-/* Macro reserved for internal HAL driver usage, not intended to be used in
-   code of final user */
-
-/**
-  * @brief Verification of ADC state: enabled or disabled
-  * @param __HANDLE__: ADC handle
-  * @retval SET (ADC enabled) or RESET (ADC disabled)
-  */
-#define ADC_IS_ENABLE(__HANDLE__)                                              \
-  ((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS )            \
-  ) ? SET : RESET)
-
-/**
-  * @brief Test if conversion trigger of regular group is software start
-  *        or external trigger.
-  * @param __HANDLE__: ADC handle
-  * @retval SET (software start) or RESET (external trigger)
-  */
-#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__)                              \
-  (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
-
-/**
-  * @brief Test if conversion trigger of injected group is software start
-  *        or external trigger.
-  * @param __HANDLE__: ADC handle
-  * @retval SET (software start) or RESET (external trigger)
-  */
-#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__)                             \
-  (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)
-
-/**
-  * @brief Simultaneously clears and sets specific bits of the handle State
-  * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
-  *        the first parameter is the ADC handle State, the second parameter is the
-  *        bit field to clear, the third and last parameter is the bit field to set.
-  * @retval None
-  */
-#define ADC_STATE_CLR_SET MODIFY_REG
-
-/**
-  * @brief Clear ADC error code (set it to error code: "no error")
-  * @param __HANDLE__: ADC handle
-  * @retval None
-  */
-#define ADC_CLEAR_ERRORCODE(__HANDLE__)                                        \
-  ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
-#define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__)     (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
-                                                  ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
-                                                  ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV6) || \
-                                                  ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV8))
-#define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES)  || \
-                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES)  || \
-                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES)  || \
-                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES)  || \
-                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES)  || \
-                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
-                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
-                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \
-                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \
-                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \
-                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \
-                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \
-                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \
-                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \
-                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \
-                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_20CYCLES))
-#define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
-                                           ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
-                                           ((__RESOLUTION__) == ADC_RESOLUTION_8B)  || \
-                                           ((__RESOLUTION__) == ADC_RESOLUTION_6B))
-#define IS_ADC_EXT_TRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE)    || \
-                                        ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING)  || \
-                                        ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
-                                        ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
-#define IS_ADC_EXT_TRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC1)   || \
-                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC2)   || \
-                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC3)   || \
-                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T2_CC2)   || \
-                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T5_TRGO)  || \
-                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T4_CC4)   || \
-                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T3_CC4) || \
-                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T8_TRGO)  || \
-                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T8_TRGO2) || \
-                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_TRGO)  || \
-                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
-                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T2_TRGO)  || \
-                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T4_TRGO)  || \
-                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T6_TRGO)  || \
-                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
-																			((__REGTRIG__) == ADC_SOFTWARE_START))
-#define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \
-                                      ((__ALIGN__) == ADC_DATAALIGN_LEFT))
-
-#define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_3CYCLES)   || \
-                                      ((__TIME__) == ADC_SAMPLETIME_15CYCLES)  || \
-                                      ((__TIME__) == ADC_SAMPLETIME_28CYCLES)  || \
-                                      ((__TIME__) == ADC_SAMPLETIME_56CYCLES)  || \
-                                      ((__TIME__) == ADC_SAMPLETIME_84CYCLES)  || \
-                                      ((__TIME__) == ADC_SAMPLETIME_112CYCLES) || \
-                                      ((__TIME__) == ADC_SAMPLETIME_144CYCLES) || \
-                                      ((__TIME__) == ADC_SAMPLETIME_480CYCLES))
-#define IS_ADC_EOCSelection(__EOCSelection__) (((__EOCSelection__) == ADC_EOC_SINGLE_CONV)   || \
-                                               ((__EOCSelection__) == ADC_EOC_SEQ_CONV)  || \
-                                               ((__EOCSelection__) == ADC_EOC_SINGLE_SEQ_CONV))
-#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_AWD_EVENT) || \
-                                      ((__EVENT__) == ADC_OVR_EVENT))
-#define IS_ADC_ANALOG_WATCHDOG(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_REG)        || \
-                                              ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC)      || \
-                                              ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)   || \
-                                              ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_REG)           || \
-                                              ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_INJEC)         || \
-                                              ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)      || \
-                                              ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_NONE))
-#define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \
-                                            ((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \
-                                            ((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS))
-#define IS_ADC_THRESHOLD(__THRESHOLD__) ((__THRESHOLD__) <= ((uint32_t)0xFFF))
-#define IS_ADC_REGULAR_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)16)))
-#define IS_ADC_REGULAR_RANK(__RANK__) (((__RANK__) >= ((uint32_t)1)) && ((__RANK__) <= ((uint32_t)16)))
-#define IS_ADC_REGULAR_DISC_NUMBER(__NUMBER__) (((__NUMBER__) >= ((uint32_t)1)) && ((__NUMBER__) <= ((uint32_t)8)))
-#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__)                                     \
-   ((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_VALUE__) <= ((uint32_t)0x0FFF))) || \
-    (((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_VALUE__) <= ((uint32_t)0x03FF))) || \
-    (((__RESOLUTION__) == ADC_RESOLUTION_8B)  && ((__ADC_VALUE__) <= ((uint32_t)0x00FF))) || \
-    (((__RESOLUTION__) == ADC_RESOLUTION_6B)  && ((__ADC_VALUE__) <= ((uint32_t)0x003F))))
-
-/**
-  * @brief  Set ADC Regular channel sequence length.
-  * @param  _NbrOfConversion_: Regular channel sequence length.
-  * @retval None
-  */
-#define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20)
-
-/**
-  * @brief  Set the ADC's sample time for channel numbers between 10 and 18.
-  * @param  _SAMPLETIME_: Sample time parameter.
-  * @param  _CHANNELNB_: Channel number.
-  * @retval None
-  */
-#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10)))
-
-/**
-  * @brief  Set the ADC's sample time for channel numbers between 0 and 9.
-  * @param  _SAMPLETIME_: Sample time parameter.
-  * @param  _CHANNELNB_: Channel number.
-  * @retval None
-  */
-#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((uint32_t)((uint16_t)(_CHANNELNB_)))))
-
-/**
-  * @brief  Set the selected regular channel rank for rank between 1 and 6.
-  * @param  _CHANNELNB_: Channel number.
-  * @param  _RANKNB_: Rank number.
-  * @retval None
-  */
-#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 1)))
-
-/**
-  * @brief  Set the selected regular channel rank for rank between 7 and 12.
-  * @param  _CHANNELNB_: Channel number.
-  * @param  _RANKNB_: Rank number.
-  * @retval None
-  */
-#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 7)))
-
-/**
-  * @brief  Set the selected regular channel rank for rank between 13 and 16.
-  * @param  _CHANNELNB_: Channel number.
-  * @param  _RANKNB_: Rank number.
-  * @retval None
-  */
-#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 13)))
-
-/**
-  * @brief  Enable ADC continuous conversion mode.
-  * @param  _CONTINUOUS_MODE_: Continuous mode.
-  * @retval None
-  */
-#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1)
-
-/**
-  * @brief  Configures the number of discontinuous conversions for the regular group channels.
-  * @param  _NBR_DISCONTINUOUSCONV_: Number of discontinuous conversions.
-  * @retval None
-  */
-#define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM))
-
-/**
-  * @brief  Enable ADC scan mode.
-  * @param  _SCANCONV_MODE_: Scan conversion mode.
-  * @retval None
-  */
-#define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8)
-
-/**
-  * @brief  Enable the ADC end of conversion selection.
-  * @param  _EOCSelection_MODE_: End of conversion selection mode.
-  * @retval None
-  */
-#define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10)
-
-/**
-  * @brief  Enable the ADC DMA continuous request.
-  * @param  _DMAContReq_MODE_: DMA continuous request mode.
-  * @retval None
-  */
-#define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9)
-
-/**
-  * @brief Return resolution bits in CR1 register.
-  * @param __HANDLE__: ADC handle
-  * @retval None
-  */
-#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup ADC_Private_Functions ADC Private Functions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F7xx_ADC_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_adc_ex.h b/stmhal/hal/f7/inc/stm32f7xx_hal_adc_ex.h
deleted file mode 100644
index 9ffe390e7e..0000000000
--- a/stmhal/hal/f7/inc/stm32f7xx_hal_adc_ex.h
+++ /dev/null
@@ -1,376 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_adc.h
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   Header file of ADC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_ADC_EX_H
-#define __STM32F7xx_ADC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal_def.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup ADCEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup ADCEx_Exported_Types ADC Exported Types
-  * @{
-  */
-
-/**
-  * @brief  ADC Configuration injected Channel structure definition
-  * @note   Parameters of this structure are shared within 2 scopes:
-  *          - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset
-  *          - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
-  *            AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
-  * @note   The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
-  *         ADC state can be either:
-  *          - For all parameters: ADC disabled
-  *          - For all except parameters 'InjectedDiscontinuousConvMode' and 'AutoInjectedConv': ADC enabled without conversion on going on injected group.
-  *          - For parameters 'ExternalTrigInjecConv' and 'ExternalTrigInjecConvEdge': ADC enabled, even with conversion on going on injected group.
-  */
-typedef struct
-{
-  uint32_t InjectedChannel;               /*!< Selection of ADC channel to configure
-                                               This parameter can be a value of @ref ADC_channels
-                                               Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
-  uint32_t InjectedRank;                  /*!< Rank in the injected group sequencer
-                                               This parameter must be a value of @ref ADCEx_injected_rank
-                                               Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
-  uint32_t InjectedSamplingTime;          /*!< Sampling time value to be set for the selected channel.
-                                               Unit: ADC clock cycles
-                                               Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
-                                               This parameter can be a value of @ref ADC_sampling_times
-                                               Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
-                                                        If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
-                                               Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
-                                                     sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
-                                                     Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
-  uint32_t InjectedOffset;                /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
-                                               Offset value must be a positive number.
-                                               Depending of ADC resolution selected (12, 10, 8 or 6 bits),
-                                               this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
-  uint32_t InjectedNbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
-                                               To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
-                                               This parameter must be a number between Min_Data = 1 and Max_Data = 4.
-                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
-                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
-  uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
-                                               Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
-                                               Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
-                                               This parameter can be set to ENABLE or DISABLE.
-                                               Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
-                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
-                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
-  uint32_t AutoInjectedConv;              /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
-                                               This parameter can be set to ENABLE or DISABLE.
-                                               Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
-                                               Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
-                                               Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
-                                                     To maintain JAUTO always enabled, DMA must be configured in circular mode.
-                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
-                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
-  uint32_t ExternalTrigInjecConv;         /*!< Selects the external event used to trigger the conversion start of injected group.
-                                               If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
-                                               If set to external trigger source, triggering is on event rising edge.
-                                               This parameter can be a value of @ref ADCEx_External_trigger_Source_Injected
-                                               Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
-                                                     If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)
-                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
-                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
-  uint32_t ExternalTrigInjecConvEdge;     /*!< Selects the external trigger edge of injected group.
-                                               This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected.
-                                               If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
-                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
-                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
-}ADC_InjectionConfTypeDef;
-/**
-  * @}
-  */
-
-/**
-  * @brief ADC Configuration multi-mode structure definition
-  */
-typedef struct
-{
-  uint32_t Mode;              /*!< Configures the ADC to operate in independent or multi mode.
-                                   This parameter can be a value of @ref ADCEx_Common_mode */
-  uint32_t DMAAccessMode;     /*!< Configures the Direct memory access mode for multi ADC mode.
-                                   This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multi_mode */
-  uint32_t TwoSamplingDelay;  /*!< Configures the Delay between 2 sampling phases.
-                                   This parameter can be a value of @ref ADC_delay_between_2_sampling_phases */
-}ADC_MultiModeTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup ADCEx_Exported_Constants ADC Exported Constants
-  * @{
-  */
-
-/** @defgroup ADCEx_Common_mode ADC Common Mode
-  * @{
-  */
-#define ADC_MODE_INDEPENDENT                  ((uint32_t)0x00000000U)
-#define ADC_DUALMODE_REGSIMULT_INJECSIMULT    ((uint32_t)ADC_CCR_MULTI_0)
-#define ADC_DUALMODE_REGSIMULT_ALTERTRIG      ((uint32_t)ADC_CCR_MULTI_1)
-#define ADC_DUALMODE_INJECSIMULT              ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
-#define ADC_DUALMODE_REGSIMULT                ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))
-#define ADC_DUALMODE_INTERL                   ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))
-#define ADC_DUALMODE_ALTERTRIG                ((uint32_t)(ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))
-#define ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT  ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0))
-#define ADC_TRIPLEMODE_REGSIMULT_AlterTrig    ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1))
-#define ADC_TRIPLEMODE_INJECSIMULT            ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
-#define ADC_TRIPLEMODE_REGSIMULT              ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))
-#define ADC_TRIPLEMODE_INTERL                 ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))
-#define ADC_TRIPLEMODE_ALTERTRIG              ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))
-/**
-  * @}
-  */
-
-/** @defgroup ADCEx_Direct_memory_access_mode_for_multi_mode ADC Direct Memory Access Mode For Multi Mode
-  * @{
-  */
-#define ADC_DMAACCESSMODE_DISABLED  ((uint32_t)0x00000000U)     /*!< DMA mode disabled */
-#define ADC_DMAACCESSMODE_1         ((uint32_t)ADC_CCR_DMA_0)  /*!< DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
-#define ADC_DMAACCESSMODE_2         ((uint32_t)ADC_CCR_DMA_1)  /*!< DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
-#define ADC_DMAACCESSMODE_3         ((uint32_t)ADC_CCR_DMA)    /*!< DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
-/**
-  * @}
-  */
-
-/** @defgroup ADCEx_External_trigger_edge_Injected ADC External Trigger Edge Injected
-  * @{
-  */
-#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE           ((uint32_t)0x00000000U)
-#define ADC_EXTERNALTRIGINJECCONVEDGE_RISING         ((uint32_t)ADC_CR2_JEXTEN_0)
-#define ADC_EXTERNALTRIGINJECCONVEDGE_FALLING        ((uint32_t)ADC_CR2_JEXTEN_1)
-#define ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING  ((uint32_t)ADC_CR2_JEXTEN)
-/**
-  * @}
-  */
-
-/** @defgroup ADCEx_External_trigger_Source_Injected ADC External Trigger Source Injected
-  * @{
-  */
-#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO         ((uint32_t)0x00000000U)
-#define ADC_EXTERNALTRIGINJECCONV_T1_CC4          ((uint32_t)ADC_CR2_JEXTSEL_0)
-#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO         ((uint32_t)ADC_CR2_JEXTSEL_1)
-#define ADC_EXTERNALTRIGINJECCONV_T2_CC1          ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
-#define ADC_EXTERNALTRIGINJECCONV_T3_CC4          ((uint32_t)ADC_CR2_JEXTSEL_2)
-#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO         ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
-
-#define ADC_EXTERNALTRIGINJECCONV_T8_CC4          ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
-#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2        ((uint32_t)ADC_CR2_JEXTSEL_3)
-#define ADC_EXTERNALTRIGINJECCONV_T8_TRGO         ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0))
-#define ADC_EXTERNALTRIGINJECCONV_T8_TRGO2        ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1))
-#define ADC_EXTERNALTRIGINJECCONV_T3_CC3          ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
-#define ADC_EXTERNALTRIGINJECCONV_T5_TRGO         ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2))
-#define ADC_EXTERNALTRIGINJECCONV_T3_CC1          ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
-#define ADC_EXTERNALTRIGINJECCONV_T6_TRGO         ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
-#define ADC_INJECTED_SOFTWARE_START                ((uint32_t)ADC_CR2_JEXTSEL + 1)
-/**
-  * @}
-  */
-
-/** @defgroup ADCEx_injected_rank ADC Injected Rank
-  * @{
-  */
-#define ADC_INJECTED_RANK_1    ((uint32_t)0x00000001U)
-#define ADC_INJECTED_RANK_2    ((uint32_t)0x00000002U)
-#define ADC_INJECTED_RANK_3    ((uint32_t)0x00000003U)
-#define ADC_INJECTED_RANK_4    ((uint32_t)0x00000004U)
-/**
-  * @}
-  */
-
-/** @defgroup ADCEx_channels  ADC Specific Channels
-  * @{
-  */
-#define ADC_CHANNEL_TEMPSENSOR  ((uint32_t)ADC_CHANNEL_18 | 0x10000000U)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup ADC_Exported_Macros ADC Exported Macros
-  * @{
-  */
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup ADCEx_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup ADCEx_Exported_Functions_Group1
-  * @{
-  */
-
-/* I/O operation functions ******************************************************/
-HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
-HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
-uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
-HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
-HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc);
-uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc);
-void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
-
-/* Peripheral Control functions *************************************************/
-HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
-HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup ADCEx_Private_Constants ADC Private Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup ADCEx_Private_Macros ADC Private Macros
-  * @{
-  */
-#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) <= ADC_CHANNEL_18)  || \
-                                 ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR))
-
-#define IS_ADC_MODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT)                 || \
-                               ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT)   || \
-                               ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG)     || \
-                               ((__MODE__) == ADC_DUALMODE_INJECSIMULT)             || \
-                               ((__MODE__) == ADC_DUALMODE_REGSIMULT)               || \
-                               ((__MODE__) == ADC_DUALMODE_INTERL)                  || \
-                               ((__MODE__) == ADC_DUALMODE_ALTERTRIG)               || \
-                               ((__MODE__) == ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT) || \
-                               ((__MODE__) == ADC_TRIPLEMODE_REGSIMULT_AlterTrig)   || \
-                               ((__MODE__) == ADC_TRIPLEMODE_INJECSIMULT)           || \
-                               ((__MODE__) == ADC_TRIPLEMODE_REGSIMULT)             || \
-                               ((__MODE__) == ADC_TRIPLEMODE_INTERL)                || \
-                               ((__MODE__) == ADC_TRIPLEMODE_ALTERTRIG))
-#define IS_ADC_DMA_ACCESS_MODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED) || \
-                                          ((__MODE__) == ADC_DMAACCESSMODE_1)        || \
-                                          ((__MODE__) == ADC_DMAACCESSMODE_2)        || \
-                                          ((__MODE__) == ADC_DMAACCESSMODE_3))
-#define IS_ADC_EXT_INJEC_TRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_NONE)    || \
-                                              ((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_RISING)  || \
-                                              ((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_FALLING) || \
-                                              ((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING))
-#define IS_ADC_EXT_INJEC_TRIG(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO)  || \
-                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T1_CC4)   || \
-                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO)  || \
-                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T2_CC1)   || \
-                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)   || \
-                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO)  || \
-                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4)   || \
-                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
-                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO)  || \
-                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || \
-                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC3)   || \
-                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO)  || \
-                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC1)   || \
-                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO)  || \
-											((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START))
-#define IS_ADC_INJECTED_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)4)))
-#define IS_ADC_INJECTED_RANK(__RANK__) (((__RANK__) >= ((uint32_t)1)) && ((__RANK__) <= ((uint32_t)4)))
-
-/**
-  * @brief  Set the selected injected Channel rank.
-  * @param  _CHANNELNB_: Channel number.
-  * @param  _RANKNB_: Rank number.
-  * @param  _JSQR_JL_: Sequence length.
-  * @retval None
-  */
-#define   ADC_JSQR(_CHANNELNB_, _RANKNB_,_JSQR_JL_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * (uint8_t)(((_RANKNB_) + 3) - (_JSQR_JL_))))
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup ADCEx_Private_Functions ADC Private Functions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F7xx_ADC_EX_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_can.h b/stmhal/hal/f7/inc/stm32f7xx_hal_can.h
deleted file mode 100644
index 02c1bff3bd..0000000000
--- a/stmhal/hal/f7/inc/stm32f7xx_hal_can.h
+++ /dev/null
@@ -1,768 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_can.h
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   Header file of CAN HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_CAN_H
-#define __STM32F7xx_HAL_CAN_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal_def.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup CAN
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup CAN_Exported_Types CAN Exported Types
-  * @{
-  */
-
-/**
-  * @brief  HAL State structures definition
-  */
-typedef enum
-{
-  HAL_CAN_STATE_RESET             = 0x00U,  /*!< CAN not yet initialized or disabled */
-  HAL_CAN_STATE_READY             = 0x01U,  /*!< CAN initialized and ready for use   */
-  HAL_CAN_STATE_BUSY              = 0x02U,  /*!< CAN process is ongoing              */
-  HAL_CAN_STATE_BUSY_TX           = 0x12U,  /*!< CAN process is ongoing              */
-  HAL_CAN_STATE_BUSY_RX           = 0x22U,  /*!< CAN process is ongoing              */
-  HAL_CAN_STATE_BUSY_TX_RX        = 0x32U,  /*!< CAN process is ongoing              */
-  HAL_CAN_STATE_TIMEOUT           = 0x03U,  /*!< Timeout state                       */
-  HAL_CAN_STATE_ERROR             = 0x04U   /*!< CAN error state                     */
-
-}HAL_CAN_StateTypeDef;
-
-/**
-  * @brief  CAN init structure definition
-  */
-typedef struct
-{
-  uint32_t Prescaler;  /*!< Specifies the length of a time quantum.
-                            This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
-
-  uint32_t Mode;       /*!< Specifies the CAN operating mode.
-                            This parameter can be a value of @ref CAN_operating_mode */
-
-  uint32_t SJW;        /*!< Specifies the maximum number of time quanta
-                            the CAN hardware is allowed to lengthen or
-                            shorten a bit to perform resynchronization.
-                            This parameter can be a value of @ref CAN_synchronisation_jump_width */
-
-  uint32_t BS1;        /*!< Specifies the number of time quanta in Bit Segment 1.
-                            This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
-
-  uint32_t BS2;        /*!< Specifies the number of time quanta in Bit Segment 2.
-                            This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
-
-  uint32_t TTCM;       /*!< Enable or disable the time triggered communication mode.
-                            This parameter can be set to ENABLE or DISABLE. */
-
-  uint32_t ABOM;       /*!< Enable or disable the automatic bus-off management.
-                            This parameter can be set to ENABLE or DISABLE */
-
-  uint32_t AWUM;       /*!< Enable or disable the automatic wake-up mode.
-                            This parameter can be set to ENABLE or DISABLE */
-
-  uint32_t NART;       /*!< Enable or disable the non-automatic retransmission mode.
-                            This parameter can be set to ENABLE or DISABLE */
-
-  uint32_t RFLM;       /*!< Enable or disable the receive FIFO Locked mode.
-                            This parameter can be set to ENABLE or DISABLE */
-
-  uint32_t TXFP;       /*!< Enable or disable the transmit FIFO priority.
-                            This parameter can be set to ENABLE or DISABLE */
-}CAN_InitTypeDef;
-
-/**
-  * @brief  CAN filter configuration structure definition
-  */
-typedef struct
-{
-  uint32_t FilterIdHigh;          /*!< Specifies the filter identification number (MSBs for a 32-bit
-                                       configuration, first one for a 16-bit configuration).
-                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
-  uint32_t FilterIdLow;           /*!< Specifies the filter identification number (LSBs for a 32-bit
-                                       configuration, second one for a 16-bit configuration).
-                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
-  uint32_t FilterMaskIdHigh;      /*!< Specifies the filter mask number or identification number,
-                                       according to the mode (MSBs for a 32-bit configuration,
-                                       first one for a 16-bit configuration).
-                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
-  uint32_t FilterMaskIdLow;       /*!< Specifies the filter mask number or identification number,
-                                       according to the mode (LSBs for a 32-bit configuration,
-                                       second one for a 16-bit configuration).
-                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
-  uint32_t FilterFIFOAssignment;  /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
-                                       This parameter can be a value of @ref CAN_filter_FIFO */
-
-  uint32_t FilterNumber;          /*!< Specifies the filter which will be initialized.
-                                       This parameter must be a number between Min_Data = 0 and Max_Data = 27 */
-
-  uint32_t FilterMode;            /*!< Specifies the filter mode to be initialized.
-                                       This parameter can be a value of @ref CAN_filter_mode */
-
-  uint32_t FilterScale;           /*!< Specifies the filter scale.
-                                       This parameter can be a value of @ref CAN_filter_scale */
-
-  uint32_t FilterActivation;      /*!< Enable or disable the filter.
-                                       This parameter can be set to ENABLE or DISABLE. */
-
-  uint32_t BankNumber;            /*!< Select the start slave bank filter.
-                                       This parameter must be a number between Min_Data = 0 and Max_Data = 28 */
-
-}CAN_FilterConfTypeDef;
-
-/**
-  * @brief  CAN Tx message structure definition
-  */
-typedef struct
-{
-  uint32_t StdId;    /*!< Specifies the standard identifier.
-                          This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
-
-  uint32_t ExtId;    /*!< Specifies the extended identifier.
-                          This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
-
-  uint32_t IDE;      /*!< Specifies the type of identifier for the message that will be transmitted.
-                          This parameter can be a value of @ref CAN_Identifier_Type */
-
-  uint32_t RTR;      /*!< Specifies the type of frame for the message that will be transmitted.
-                          This parameter can be a value of @ref CAN_remote_transmission_request */
-
-  uint32_t DLC;      /*!< Specifies the length of the frame that will be transmitted.
-                          This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
-
-  uint8_t Data[8];  /*!< Contains the data to be transmitted.
-                          This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
-
-}CanTxMsgTypeDef;
-
-/**
-  * @brief  CAN Rx message structure definition
-  */
-typedef struct
-{
-  uint32_t StdId;       /*!< Specifies the standard identifier.
-                             This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
-
-  uint32_t ExtId;       /*!< Specifies the extended identifier.
-                             This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
-
-  uint32_t IDE;         /*!< Specifies the type of identifier for the message that will be received.
-                             This parameter can be a value of @ref CAN_Identifier_Type */
-
-  uint32_t RTR;         /*!< Specifies the type of frame for the received message.
-                             This parameter can be a value of @ref CAN_remote_transmission_request */
-
-  uint32_t DLC;         /*!< Specifies the length of the frame that will be received.
-                             This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
-
-  uint8_t Data[8];      /*!< Contains the data to be received.
-                             This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
-
-  uint32_t FMI;         /*!< Specifies the index of the filter the message stored in the mailbox passes through.
-                             This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
-
-  uint32_t FIFONumber;  /*!< Specifies the receive FIFO number.
-                             This parameter can be CAN_FIFO0 or CAN_FIFO1 */
-
-}CanRxMsgTypeDef;
-
-/**
-  * @brief  CAN handle Structure definition
-  */
-typedef struct
-{
-  CAN_TypeDef                 *Instance;  /*!< Register base address          */
-
-  CAN_InitTypeDef             Init;       /*!< CAN required parameters        */
-
-  CanTxMsgTypeDef*            pTxMsg;     /*!< Pointer to transmit structure  */
-
-  CanRxMsgTypeDef*            pRxMsg;     /*!< Pointer to reception structure */
-
-  __IO HAL_CAN_StateTypeDef   State;      /*!< CAN communication state        */
-
-  HAL_LockTypeDef             Lock;       /*!< CAN locking object             */
-
-  __IO uint32_t               ErrorCode;  /*!< CAN Error code                 */
-
-}CAN_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CAN_Exported_Constants CAN Exported Constants
-  * @{
-  */
-
-/** @defgroup HAL_CAN_Error_Code HAL CAN Error Code
-  * @{
-  */
-#define   HAL_CAN_ERROR_NONE      0x00U    /*!< No error             */
-#define   HAL_CAN_ERROR_EWG       0x01U    /*!< EWG error            */
-#define   HAL_CAN_ERROR_EPV       0x02U    /*!< EPV error            */
-#define   HAL_CAN_ERROR_BOF       0x04U    /*!< BOF error            */
-#define   HAL_CAN_ERROR_STF       0x08U    /*!< Stuff error          */
-#define   HAL_CAN_ERROR_FOR       0x10U    /*!< Form error           */
-#define   HAL_CAN_ERROR_ACK       0x20U    /*!< Acknowledgment error */
-#define   HAL_CAN_ERROR_BR        0x40U    /*!< Bit recessive        */
-#define   HAL_CAN_ERROR_BD        0x80U    /*!< LEC dominant         */
-#define   HAL_CAN_ERROR_CRC       0x100U   /*!< LEC transfer error   */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_InitStatus CAN InitStatus
-  * @{
-  */
-#define CAN_INITSTATUS_FAILED       ((uint8_t)0x00U)  /*!< CAN initialization failed */
-#define CAN_INITSTATUS_SUCCESS      ((uint8_t)0x01U)  /*!< CAN initialization OK */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_operating_mode CAN Operating Mode
-  * @{
-  */
-#define CAN_MODE_NORMAL             ((uint32_t)0x00000000U)                     /*!< Normal mode   */
-#define CAN_MODE_LOOPBACK           ((uint32_t)CAN_BTR_LBKM)                   /*!< Loopback mode */
-#define CAN_MODE_SILENT             ((uint32_t)CAN_BTR_SILM)                   /*!< Silent mode   */
-#define CAN_MODE_SILENT_LOOPBACK    ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM))  /*!< Loopback combined with silent mode */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_synchronisation_jump_width CAN Synchronisation Jump Width
-  * @{
-  */
-#define CAN_SJW_1TQ                 ((uint32_t)0x00000000U)     /*!< 1 time quantum */
-#define CAN_SJW_2TQ                 ((uint32_t)CAN_BTR_SJW_0)  /*!< 2 time quantum */
-#define CAN_SJW_3TQ                 ((uint32_t)CAN_BTR_SJW_1)  /*!< 3 time quantum */
-#define CAN_SJW_4TQ                 ((uint32_t)CAN_BTR_SJW)    /*!< 4 time quantum */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in bit segment 1
-  * @{
-  */
-#define CAN_BS1_1TQ                 ((uint32_t)0x00000000U)                                       /*!< 1 time quantum  */
-#define CAN_BS1_2TQ                 ((uint32_t)CAN_BTR_TS1_0)                                    /*!< 2 time quantum  */
-#define CAN_BS1_3TQ                 ((uint32_t)CAN_BTR_TS1_1)                                    /*!< 3 time quantum  */
-#define CAN_BS1_4TQ                 ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0))                  /*!< 4 time quantum  */
-#define CAN_BS1_5TQ                 ((uint32_t)CAN_BTR_TS1_2)                                    /*!< 5 time quantum  */
-#define CAN_BS1_6TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0))                  /*!< 6 time quantum  */
-#define CAN_BS1_7TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1))                  /*!< 7 time quantum  */
-#define CAN_BS1_8TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))  /*!< 8 time quantum  */
-#define CAN_BS1_9TQ                 ((uint32_t)CAN_BTR_TS1_3)                                    /*!< 9 time quantum  */
-#define CAN_BS1_10TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0))                  /*!< 10 time quantum */
-#define CAN_BS1_11TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1))                  /*!< 11 time quantum */
-#define CAN_BS1_12TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))  /*!< 12 time quantum */
-#define CAN_BS1_13TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2))                  /*!< 13 time quantum */
-#define CAN_BS1_14TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0))  /*!< 14 time quantum */
-#define CAN_BS1_15TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1))  /*!< 15 time quantum */
-#define CAN_BS1_16TQ                ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2
-  * @{
-  */
-#define CAN_BS2_1TQ                 ((uint32_t)0x00000000U)                       /*!< 1 time quantum */
-#define CAN_BS2_2TQ                 ((uint32_t)CAN_BTR_TS2_0)                    /*!< 2 time quantum */
-#define CAN_BS2_3TQ                 ((uint32_t)CAN_BTR_TS2_1)                    /*!< 3 time quantum */
-#define CAN_BS2_4TQ                 ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0))  /*!< 4 time quantum */
-#define CAN_BS2_5TQ                 ((uint32_t)CAN_BTR_TS2_2)                    /*!< 5 time quantum */
-#define CAN_BS2_6TQ                 ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0))  /*!< 6 time quantum */
-#define CAN_BS2_7TQ                 ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1))  /*!< 7 time quantum */
-#define CAN_BS2_8TQ                 ((uint32_t)CAN_BTR_TS2)                      /*!< 8 time quantum */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_filter_mode  CAN Filter Mode
-  * @{
-  */
-#define CAN_FILTERMODE_IDMASK       ((uint8_t)0x00U)  /*!< Identifier mask mode */
-#define CAN_FILTERMODE_IDLIST       ((uint8_t)0x01U)  /*!< Identifier list mode */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_filter_scale CAN Filter Scale
-  * @{
-  */
-#define CAN_FILTERSCALE_16BIT       ((uint8_t)0x00U)  /*!< Two 16-bit filters */
-#define CAN_FILTERSCALE_32BIT       ((uint8_t)0x01U)  /*!< One 32-bit filter  */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_filter_FIFO CAN Filter FIFO
-  * @{
-  */
-#define CAN_FILTER_FIFO0             ((uint8_t)0x00U)  /*!< Filter FIFO 0 assignment for filter x */
-#define CAN_FILTER_FIFO1             ((uint8_t)0x01U)  /*!< Filter FIFO 1 assignment for filter x */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_Identifier_Type CAN Identifier Type
-  * @{
-  */
-#define CAN_ID_STD             ((uint32_t)0x00000000U)  /*!< Standard Id */
-#define CAN_ID_EXT             ((uint32_t)0x00000004U)  /*!< Extended Id */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
-  * @{
-  */
-#define CAN_RTR_DATA                ((uint32_t)0x00000000U)  /*!< Data frame */
-#define CAN_RTR_REMOTE              ((uint32_t)0x00000002U)  /*!< Remote frame */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number Constants
-  * @{
-  */
-#define CAN_FIFO0                   ((uint8_t)0x00U)  /*!< CAN FIFO 0 used to receive */
-#define CAN_FIFO1                   ((uint8_t)0x01U)  /*!< CAN FIFO 1 used to receive */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_flags CAN Flags
-  * @{
-  */
-/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
-   and CAN_ClearFlag() functions. */
-/* If the flag is 0x1XXXXXXX, it means that it can only be used with
-   CAN_GetFlagStatus() function.  */
-
-/* Transmit Flags */
-#define CAN_FLAG_RQCP0             ((uint32_t)0x00000500U)  /*!< Request MailBox0 flag         */
-#define CAN_FLAG_RQCP1             ((uint32_t)0x00000508U)  /*!< Request MailBox1 flag         */
-#define CAN_FLAG_RQCP2             ((uint32_t)0x00000510U)  /*!< Request MailBox2 flag         */
-#define CAN_FLAG_TXOK0             ((uint32_t)0x00000501U)  /*!< Transmission OK MailBox0 flag */
-#define CAN_FLAG_TXOK1             ((uint32_t)0x00000509U)  /*!< Transmission OK MailBox1 flag */
-#define CAN_FLAG_TXOK2             ((uint32_t)0x00000511U)  /*!< Transmission OK MailBox2 flag */
-#define CAN_FLAG_TME0              ((uint32_t)0x0000051AU)  /*!< Transmit mailbox 0 empty flag */
-#define CAN_FLAG_TME1              ((uint32_t)0x0000051BU)  /*!< Transmit mailbox 0 empty flag */
-#define CAN_FLAG_TME2              ((uint32_t)0x0000051CU)  /*!< Transmit mailbox 0 empty flag */
-
-/* Receive Flags */
-#define CAN_FLAG_FF0               ((uint32_t)0x00000203U)  /*!< FIFO 0 Full flag    */
-#define CAN_FLAG_FOV0              ((uint32_t)0x00000204U)  /*!< FIFO 0 Overrun flag */
-
-#define CAN_FLAG_FF1               ((uint32_t)0x00000403U)  /*!< FIFO 1 Full flag    */
-#define CAN_FLAG_FOV1              ((uint32_t)0x00000404U)  /*!< FIFO 1 Overrun flag */
-
-/* Operating Mode Flags */
-#define CAN_FLAG_INAK              ((uint32_t)0x00000100U)  /*!<  Initialization acknowledge flag */
-#define CAN_FLAG_SLAK              ((uint32_t)0x00000101U)  /*!< Sleep acknowledge flag */
-#define CAN_FLAG_ERRI              ((uint32_t)0x00000102U)  /*!<  Error flag */
-#define CAN_FLAG_WKU               ((uint32_t)0x00000103U)  /*!< Wake up flag           */
-#define CAN_FLAG_SLAKI             ((uint32_t)0x00000104U)  /*!< Sleep acknowledge flag */
-
-/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
-         In this case the SLAK bit can be polled.*/
-
-/* Error Flags */
-#define CAN_FLAG_EWG               ((uint32_t)0x00000300U)  /*!< Error warning flag   */
-#define CAN_FLAG_EPV               ((uint32_t)0x00000301U)  /*!< Error passive flag   */
-#define CAN_FLAG_BOF               ((uint32_t)0x00000302U)  /*!< Bus-Off flag         */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_Interrupts CAN Interrupts
-  * @{
-  */
-#define CAN_IT_TME                  ((uint32_t)CAN_IER_TMEIE)   /*!< Transmit mailbox empty interrupt */
-
-/* Receive Interrupts */
-#define CAN_IT_FMP0                 ((uint32_t)CAN_IER_FMPIE0)  /*!< FIFO 0 message pending interrupt */
-#define CAN_IT_FF0                  ((uint32_t)CAN_IER_FFIE0)   /*!< FIFO 0 full interrupt            */
-#define CAN_IT_FOV0                 ((uint32_t)CAN_IER_FOVIE0)  /*!< FIFO 0 overrun interrupt         */
-#define CAN_IT_FMP1                 ((uint32_t)CAN_IER_FMPIE1)  /*!< FIFO 1 message pending interrupt */
-#define CAN_IT_FF1                  ((uint32_t)CAN_IER_FFIE1)   /*!< FIFO 1 full interrupt            */
-#define CAN_IT_FOV1                 ((uint32_t)CAN_IER_FOVIE1)  /*!< FIFO 1 overrun interrupt         */
-
-/* Operating Mode Interrupts */
-#define CAN_IT_WKU                  ((uint32_t)CAN_IER_WKUIE)  /*!< Wake-up interrupt           */
-#define CAN_IT_SLK                  ((uint32_t)CAN_IER_SLKIE)  /*!< Sleep acknowledge interrupt */
-
-/* Error Interrupts */
-#define CAN_IT_EWG                  ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt   */
-#define CAN_IT_EPV                  ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt   */
-#define CAN_IT_BOF                  ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt         */
-#define CAN_IT_LEC                  ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
-#define CAN_IT_ERR                  ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt           */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_Mailboxes_Definition CAN Mailboxes Definition
-  * @{
-  */
-#define CAN_TXMAILBOX_0   ((uint8_t)0x00U)
-#define CAN_TXMAILBOX_1   ((uint8_t)0x01U)
-#define CAN_TXMAILBOX_2   ((uint8_t)0x02U)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup CAN_Exported_Macros CAN Exported Macros
-  * @{
-  */
-
-/** @brief Reset CAN handle state
-  * @param  __HANDLE__: specifies the CAN Handle.
-  * @retval None
-  */
-#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
-
-/**
-  * @brief  Enable the specified CAN interrupts.
-  * @param  __HANDLE__: CAN handle
-  * @param  __INTERRUPT__: CAN Interrupt
-  * @retval None
-  */
-#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the specified CAN interrupts.
-  * @param  __HANDLE__: CAN handle
-  * @param  __INTERRUPT__: CAN Interrupt
-  * @retval None
-  */
-#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
-
-/**
-  * @brief  Return the number of pending received messages.
-  * @param  __HANDLE__: CAN handle
-  * @param  __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
-  * @retval The number of pending message.
-  */
-#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
-((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&(uint32_t)0x03)))
-
-/** @brief  Check whether the specified CAN flag is set or not.
-  * @param  __HANDLE__: CAN Handle
-  * @param  __FLAG__: specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg CAN_TSR_RQCP0: Request MailBox0 Flag
-  *            @arg CAN_TSR_RQCP1: Request MailBox1 Flag
-  *            @arg CAN_TSR_RQCP2: Request MailBox2 Flag
-  *            @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
-  *            @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
-  *            @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
-  *            @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
-  *            @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
-  *            @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
-  *            @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
-  *            @arg CAN_FLAG_FF0: FIFO 0 Full Flag
-  *            @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
-  *            @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
-  *            @arg CAN_FLAG_FF1: FIFO 1 Full Flag
-  *            @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
-  *            @arg CAN_FLAG_WKU: Wake up Flag
-  *            @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
-  *            @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
-  *            @arg CAN_FLAG_EWG: Error Warning Flag
-  *            @arg CAN_FLAG_EPV: Error Passive Flag
-  *            @arg CAN_FLAG_BOF: Bus-Off Flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
-((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8) == 4)? ((((__HANDLE__)->Instance->RF1R) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8) == 1)? ((((__HANDLE__)->Instance->MSR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
- ((((__HANDLE__)->Instance->ESR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))))
-
-/** @brief  Clear the specified CAN pending flag.
-  * @param  __HANDLE__: CAN Handle.
-  * @param  __FLAG__: specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg CAN_TSR_RQCP0: Request MailBox0 Flag
-  *            @arg CAN_TSR_RQCP1: Request MailBox1 Flag
-  *            @arg CAN_TSR_RQCP2: Request MailBox2 Flag
-  *            @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
-  *            @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
-  *            @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
-  *            @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
-  *            @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
-  *            @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
-  *            @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
-  *            @arg CAN_FLAG_FF0: FIFO 0 Full Flag
-  *            @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
-  *            @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
-  *            @arg CAN_FLAG_FF1: FIFO 1 Full Flag
-  *            @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
-  *            @arg CAN_FLAG_WKU: Wake up Flag
-  *            @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
-  *            @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
-((((__FLAG__) >> 8) == 5)? (((__HANDLE__)->Instance->TSR) = ((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8) == 2)? (((__HANDLE__)->Instance->RF0R) = ((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8) == 4)? (((__HANDLE__)->Instance->RF1R) = ((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__HANDLE__)->Instance->MSR) = ((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))))
-
-/** @brief  Check if the specified CAN interrupt source is enabled or disabled.
-  * @param  __HANDLE__: CAN Handle
-  * @param  __INTERRUPT__: specifies the CAN interrupt source to check.
-  *          This parameter can be one of the following values:
-  *             @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
-  *             @arg CAN_IT_FMP0: FIFO0 message pending interrupt enable
-  *             @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable
-  * @retval The new state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/**
-  * @brief  Check the transmission status of a CAN Frame.
-  * @param  __HANDLE__: CAN Handle
-  * @param  __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
-  * @retval The new status of transmission  (TRUE or FALSE).
-  */
-#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
-(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\
- ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\
- ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))
-
-/**
-  * @brief  Release the specified receive FIFO.
-  * @param  __HANDLE__: CAN handle
-  * @param  __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
-  * @retval None
-  */
-#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
-((__HANDLE__)->Instance->RF0R = CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R = CAN_RF1R_RFOM1))
-
-/**
-  * @brief  Cancel a transmit request.
-  * @param  __HANDLE__: CAN Handle
-  * @param  __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
-  * @retval None
-  */
-#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
-(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ0) :\
- ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ1) :\
- ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ2))
-
-/**
-  * @brief  Enable or disable the DBG Freeze for CAN.
-  * @param  __HANDLE__: CAN Handle
-  * @param  __NEWSTATE__: new state of the CAN peripheral.
-  *          This parameter can be: ENABLE (CAN reception/transmission is frozen
-  *          during debug. Reception FIFOs can still be accessed/controlled normally)
-  *          or DISABLE (CAN is working during debug).
-  * @retval None
-  */
-#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
-((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup CAN_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup CAN_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization/de-initialization functions ***********************************/
-HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
-HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
-HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
-void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
-void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
-/**
-  * @}
-  */
-
-/** @addtogroup CAN_Exported_Functions_Group2
-  * @{
-  */
-/* I/O operation functions ******************************************************/
-HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
-HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
-HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
-HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
-void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
-void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
-void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
-void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
-/**
-  * @}
-  */
-
-/** @addtogroup CAN_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral State functions ***************************************************/
-uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
-HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/
-/** @defgroup CAN_Private_Types CAN Private Types
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup CAN_Private_Variables CAN Private Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup CAN_Private_Constants CAN Private Constants
-  * @{
-  */
-#define CAN_TXSTATUS_NOMAILBOX      ((uint8_t)0x04U)  /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
-#define CAN_FLAG_MASK  ((uint32_t)0x000000FFU)
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup CAN_Private_Macros CAN Private Macros
-  * @{
-  */
-#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
-                           ((MODE) == CAN_MODE_LOOPBACK)|| \
-                           ((MODE) == CAN_MODE_SILENT) || \
-                           ((MODE) == CAN_MODE_SILENT_LOOPBACK))
-#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
-                         ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
-#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
-#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
-#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
-#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
-#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
-                                  ((MODE) == CAN_FILTERMODE_IDLIST))
-#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
-                                    ((SCALE) == CAN_FILTERSCALE_32BIT))
-#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
-                                  ((FIFO) == CAN_FILTER_FIFO1))
-#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28)
-
-#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
-#define IS_CAN_STDID(STDID)   ((STDID) <= ((uint32_t)0x7FF))
-#define IS_CAN_EXTID(EXTID)   ((EXTID) <= ((uint32_t)0x1FFFFFFF))
-#define IS_CAN_DLC(DLC)       ((DLC) <= ((uint8_t)0x08))
-
-#define IS_CAN_IDTYPE(IDTYPE)  (((IDTYPE) == CAN_ID_STD) || \
-                                ((IDTYPE) == CAN_ID_EXT))
-#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
-#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup CAN_Private_Functions CAN Private Functions
-  * @{
-  */
-
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F7xx_CAN_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_cortex.h b/stmhal/hal/f7/inc/stm32f7xx_hal_cortex.h
deleted file mode 100644
index 1bf5d8ec45..0000000000
--- a/stmhal/hal/f7/inc/stm32f7xx_hal_cortex.h
+++ /dev/null
@@ -1,424 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_cortex.h
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   Header file of CORTEX HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_CORTEX_H
-#define __STM32F7xx_HAL_CORTEX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal_def.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup CORTEX
-  * @{
-  */
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup CORTEX_Exported_Types Cortex Exported Types
-  * @{
-  */
-
-#if (__MPU_PRESENT == 1)
-/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
-  * @brief  MPU Region initialization structure
-  * @{
-  */
-typedef struct
-{
-  uint8_t                Enable;                /*!< Specifies the status of the region.
-                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */
-  uint8_t                Number;                /*!< Specifies the number of the region to protect.
-                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */
-  uint32_t               BaseAddress;           /*!< Specifies the base address of the region to protect.                           */
-  uint8_t                Size;                  /*!< Specifies the size of the region to protect.
-                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */
-  uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable.
-                                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */
-  uint8_t                TypeExtField;          /*!< Specifies the TEX field level.
-                                                     This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */
-  uint8_t                AccessPermission;      /*!< Specifies the region access permission type.
-                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */
-  uint8_t                DisableExec;           /*!< Specifies the instruction access status.
-                                                     This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */
-  uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region.
-                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */
-  uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected.
-                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */
-  uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region.
-                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */
-}MPU_Region_InitTypeDef;
-/**
-  * @}
-  */
-#endif /* __MPU_PRESENT */
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
-  * @{
-  */
-
-/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
-  * @{
-  */
-#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007U) /*!< 0 bits for pre-emption priority
-                                                                 4 bits for subpriority */
-#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006U) /*!< 1 bits for pre-emption priority
-                                                                 3 bits for subpriority */
-#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005U) /*!< 2 bits for pre-emption priority
-                                                                 2 bits for subpriority */
-#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004U) /*!< 3 bits for pre-emption priority
-                                                                 1 bits for subpriority */
-#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003U) /*!< 4 bits for pre-emption priority
-                                                                 0 bits for subpriority */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
-  * @{
-  */
-#define SYSTICK_CLKSOURCE_HCLK_DIV8    ((uint32_t)0x00000000U)
-#define SYSTICK_CLKSOURCE_HCLK         ((uint32_t)0x00000004U)
-
-/**
-  * @}
-  */
-
-#if (__MPU_PRESENT == 1)
-/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
-  * @{
-  */
-#define  MPU_HFNMI_PRIVDEF_NONE      ((uint32_t)0x00000000U)
-#define  MPU_HARDFAULT_NMI           ((uint32_t)0x00000002U)
-#define  MPU_PRIVILEGED_DEFAULT      ((uint32_t)0x00000004U)
-#define  MPU_HFNMI_PRIVDEF           ((uint32_t)0x00000006U)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
-  * @{
-  */
-#define  MPU_REGION_ENABLE     ((uint8_t)0x01U)
-#define  MPU_REGION_DISABLE    ((uint8_t)0x00U)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
-  * @{
-  */
-#define  MPU_INSTRUCTION_ACCESS_ENABLE      ((uint8_t)0x00U)
-#define  MPU_INSTRUCTION_ACCESS_DISABLE     ((uint8_t)0x01U)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
-  * @{
-  */
-#define  MPU_ACCESS_SHAREABLE        ((uint8_t)0x01U)
-#define  MPU_ACCESS_NOT_SHAREABLE    ((uint8_t)0x00U)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
-  * @{
-  */
-#define  MPU_ACCESS_CACHEABLE         ((uint8_t)0x01U)
-#define  MPU_ACCESS_NOT_CACHEABLE     ((uint8_t)0x00U)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
-  * @{
-  */
-#define  MPU_ACCESS_BUFFERABLE         ((uint8_t)0x01U)
-#define  MPU_ACCESS_NOT_BUFFERABLE     ((uint8_t)0x00U)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
-  * @{
-  */
-#define  MPU_TEX_LEVEL0    ((uint8_t)0x00U)
-#define  MPU_TEX_LEVEL1    ((uint8_t)0x01U)
-#define  MPU_TEX_LEVEL2    ((uint8_t)0x02U)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
-  * @{
-  */
-#define   MPU_REGION_SIZE_32B      ((uint8_t)0x04U)
-#define   MPU_REGION_SIZE_64B      ((uint8_t)0x05U)
-#define   MPU_REGION_SIZE_128B     ((uint8_t)0x06U)
-#define   MPU_REGION_SIZE_256B     ((uint8_t)0x07U)
-#define   MPU_REGION_SIZE_512B     ((uint8_t)0x08U)
-#define   MPU_REGION_SIZE_1KB      ((uint8_t)0x09U)
-#define   MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU)
-#define   MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU)
-#define   MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU)
-#define   MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU)
-#define   MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU)
-#define   MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU)
-#define   MPU_REGION_SIZE_128KB    ((uint8_t)0x10U)
-#define   MPU_REGION_SIZE_256KB    ((uint8_t)0x11U)
-#define   MPU_REGION_SIZE_512KB    ((uint8_t)0x12U)
-#define   MPU_REGION_SIZE_1MB      ((uint8_t)0x13U)
-#define   MPU_REGION_SIZE_2MB      ((uint8_t)0x14U)
-#define   MPU_REGION_SIZE_4MB      ((uint8_t)0x15U)
-#define   MPU_REGION_SIZE_8MB      ((uint8_t)0x16U)
-#define   MPU_REGION_SIZE_16MB     ((uint8_t)0x17U)
-#define   MPU_REGION_SIZE_32MB     ((uint8_t)0x18U)
-#define   MPU_REGION_SIZE_64MB     ((uint8_t)0x19U)
-#define   MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU)
-#define   MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU)
-#define   MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU)
-#define   MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU)
-#define   MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU)
-#define   MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
-  * @{
-  */
-#define  MPU_REGION_NO_ACCESS      ((uint8_t)0x00U)
-#define  MPU_REGION_PRIV_RW        ((uint8_t)0x01U)
-#define  MPU_REGION_PRIV_RW_URO    ((uint8_t)0x02U)
-#define  MPU_REGION_FULL_ACCESS    ((uint8_t)0x03U)
-#define  MPU_REGION_PRIV_RO        ((uint8_t)0x05U)
-#define  MPU_REGION_PRIV_RO_URO    ((uint8_t)0x06U)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
-  * @{
-  */
-#define  MPU_REGION_NUMBER0    ((uint8_t)0x00U)
-#define  MPU_REGION_NUMBER1    ((uint8_t)0x01U)
-#define  MPU_REGION_NUMBER2    ((uint8_t)0x02U)
-#define  MPU_REGION_NUMBER3    ((uint8_t)0x03U)
-#define  MPU_REGION_NUMBER4    ((uint8_t)0x04U)
-#define  MPU_REGION_NUMBER5    ((uint8_t)0x05U)
-#define  MPU_REGION_NUMBER6    ((uint8_t)0x06U)
-#define  MPU_REGION_NUMBER7    ((uint8_t)0x07U)
-/**
-  * @}
-  */
-#endif /* __MPU_PRESENT */
-
-/**
-  * @}
-  */
-
-
-/* Exported Macros -----------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup CORTEX_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup CORTEX_Exported_Functions_Group1
- * @{
- */
-/* Initialization and de-initialization functions *****************************/
-void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
-void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
-void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
-void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
-void HAL_NVIC_SystemReset(void);
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
-/**
-  * @}
-  */
-
-/** @addtogroup CORTEX_Exported_Functions_Group2
- * @{
- */
-/* Peripheral Control functions ***********************************************/
-#if (__MPU_PRESENT == 1)
-void HAL_MPU_Enable(uint32_t MPU_Control);
-void HAL_MPU_Disable(void);
-void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
-#endif /* __MPU_PRESENT */
-uint32_t HAL_NVIC_GetPriorityGrouping(void);
-void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
-uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
-void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
-void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
-uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
-void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
-void HAL_SYSTICK_IRQHandler(void);
-void HAL_SYSTICK_Callback(void);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
-  * @{
-  */
-#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
-                                       ((GROUP) == NVIC_PRIORITYGROUP_1) || \
-                                       ((GROUP) == NVIC_PRIORITYGROUP_2) || \
-                                       ((GROUP) == NVIC_PRIORITYGROUP_3) || \
-                                       ((GROUP) == NVIC_PRIORITYGROUP_4))
-
-#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10U)
-
-#define IS_NVIC_SUB_PRIORITY(PRIORITY)         ((PRIORITY) < 0x10U)
-
-#define IS_NVIC_DEVICE_IRQ(IRQ)                ((IRQ) >= 0x00)
-
-#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
-                                       ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
-
-#if (__MPU_PRESENT == 1)
-#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
-                                     ((STATE) == MPU_REGION_DISABLE))
-
-#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
-                                          ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
-
-#define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_SHAREABLE) || \
-                                          ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
-
-#define IS_MPU_ACCESS_CACHEABLE(STATE)   (((STATE) == MPU_ACCESS_CACHEABLE) || \
-                                          ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
-
-#define IS_MPU_ACCESS_BUFFERABLE(STATE)   (((STATE) == MPU_ACCESS_BUFFERABLE) || \
-                                          ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
-
-#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0)  || \
-                                ((TYPE) == MPU_TEX_LEVEL1)  || \
-                                ((TYPE) == MPU_TEX_LEVEL2))
-
-#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS)   || \
-                                                  ((TYPE) == MPU_REGION_PRIV_RW)     || \
-                                                  ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
-                                                  ((TYPE) == MPU_REGION_FULL_ACCESS) || \
-                                                  ((TYPE) == MPU_REGION_PRIV_RO)     || \
-                                                  ((TYPE) == MPU_REGION_PRIV_RO_URO))
-
-#define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER1) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER2) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER3) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER4) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER5) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER6) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER7))
-
-#define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_32B)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_64B)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_128B)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_256B)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_512B)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_1KB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_2KB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_4KB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_8KB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_16KB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_32KB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_64KB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_128KB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_256KB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_512KB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_1MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_2MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_4MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_8MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_16MB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_32MB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_64MB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_128MB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_256MB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_512MB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_1GB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_2GB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_4GB))
-
-#define IS_MPU_SUB_REGION_DISABLE(SUBREGION)  ((SUBREGION) < (uint16_t)0x00FFU)
-#endif /* __MPU_PRESENT */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F7xx_HAL_CORTEX_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_dac.h b/stmhal/hal/f7/inc/stm32f7xx_hal_dac.h
deleted file mode 100644
index d604e9be33..0000000000
--- a/stmhal/hal/f7/inc/stm32f7xx_hal_dac.h
+++ /dev/null
@@ -1,408 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_dac.h
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   Header file of DAC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_DAC_H
-#define __STM32F7xx_HAL_DAC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal_def.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup DAC
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup DAC_Exported_Types DAC Exported Types
-  * @{
-  */
-
-/**
-  * @brief HAL State structures definition
-  */
-typedef enum
-{
-  HAL_DAC_STATE_RESET             = 0x00U,  /*!< DAC not yet initialized or disabled  */
-  HAL_DAC_STATE_READY             = 0x01U,  /*!< DAC initialized and ready for use    */
-  HAL_DAC_STATE_BUSY              = 0x02U,  /*!< DAC internal processing is ongoing   */
-  HAL_DAC_STATE_TIMEOUT           = 0x03U,  /*!< DAC timeout state                    */
-  HAL_DAC_STATE_ERROR             = 0x04U   /*!< DAC error state                      */
-}HAL_DAC_StateTypeDef;
-
-/**
-  * @brief DAC handle Structure definition
-  */
-typedef struct
-{
-  DAC_TypeDef                 *Instance;     /*!< Register base address             */
-
-  __IO HAL_DAC_StateTypeDef   State;         /*!< DAC communication state           */
-
-  HAL_LockTypeDef             Lock;          /*!< DAC locking object                */
-
-  DMA_HandleTypeDef           *DMA_Handle1;  /*!< Pointer DMA handler for channel 1 */
-
-  DMA_HandleTypeDef           *DMA_Handle2;  /*!< Pointer DMA handler for channel 2 */
-
-  __IO uint32_t               ErrorCode;     /*!< DAC Error code                    */
-
-}DAC_HandleTypeDef;
-
-/**
-  * @brief DAC Configuration regular Channel structure definition
-  */
-typedef struct
-{
-  uint32_t DAC_Trigger;       /*!< Specifies the external trigger for the selected DAC channel.
-                                   This parameter can be a value of @ref DAC_trigger_selection */
-
-  uint32_t DAC_OutputBuffer;  /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
-                                   This parameter can be a value of @ref DAC_output_buffer */
-}DAC_ChannelConfTypeDef;
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup DAC_Exported_Constants DAC Exported Constants
-  * @{
-  */
-
-/** @defgroup DAC_Error_Code DAC Error Code
-  * @{
-  */
-#define  HAL_DAC_ERROR_NONE              0x00U    /*!< No error                          */
-#define  HAL_DAC_ERROR_DMAUNDERRUNCH1    0x01U    /*!< DAC channel1 DAM underrun error   */
-#define  HAL_DAC_ERROR_DMAUNDERRUNCH2    0x02U    /*!< DAC channel2 DAM underrun error   */
-#define  HAL_DAC_ERROR_DMA               0x04U    /*!< DMA error                         */
-/**
-  * @}
-  */
-
-/** @defgroup DAC_trigger_selection DAC Trigger Selection
-  * @{
-  */
-
-#define DAC_TRIGGER_NONE                   ((uint32_t)0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
-                                                                       has been loaded, and not by external trigger */
-#define DAC_TRIGGER_T2_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T4_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T5_TRGO                ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T6_TRGO                ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T7_TRGO                ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T8_TRGO                ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
-
-#define DAC_TRIGGER_EXT_IT9                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_SOFTWARE               ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
-/**
-  * @}
-  */
-
-/** @defgroup DAC_output_buffer  DAC Output Buffer
-  * @{
-  */
-#define DAC_OUTPUTBUFFER_ENABLE            ((uint32_t)0x00000000U)
-#define DAC_OUTPUTBUFFER_DISABLE           ((uint32_t)DAC_CR_BOFF1)
-/**
-  * @}
-  */
-
-/** @defgroup DAC_Channel_selection DAC Channel Selection
-  * @{
-  */
-#define DAC_CHANNEL_1                      ((uint32_t)0x00000000U)
-#define DAC_CHANNEL_2                      ((uint32_t)0x00000010U)
-/**
-  * @}
-  */
-
-/** @defgroup DAC_data_alignment DAC Data Alignment
-  * @{
-  */
-#define DAC_ALIGN_12B_R                    ((uint32_t)0x00000000U)
-#define DAC_ALIGN_12B_L                    ((uint32_t)0x00000004U)
-#define DAC_ALIGN_8B_R                     ((uint32_t)0x00000008U)
-/**
-  * @}
-  */
-
-/** @defgroup DAC_flags_definition DAC Flags Definition
-  * @{
-  */
-#define DAC_FLAG_DMAUDR1                   ((uint32_t)DAC_SR_DMAUDR1)
-#define DAC_FLAG_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)
-/**
-  * @}
-  */
-
-/** @defgroup DAC_IT_definition DAC IT Definition
-  * @{
-  */
-#define DAC_IT_DMAUDR1                   ((uint32_t)DAC_SR_DMAUDR1)
-#define DAC_IT_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup DAC_Exported_Macros DAC Exported Macros
-  * @{
-  */
-
-/** @brief Reset DAC handle state
-  * @param  __HANDLE__: specifies the DAC handle.
-  * @retval None
-  */
-#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
-
-/** @brief Enable the DAC channel
-  * @param  __HANDLE__: specifies the DAC handle.
-  * @param  __DAC_CHANNEL__: specifies the DAC channel
-  * @retval None
-  */
-#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_CHANNEL__) \
-((__HANDLE__)->Instance->CR |=  (DAC_CR_EN1 << (__DAC_CHANNEL__)))
-
-/** @brief Disable the DAC channel
-  * @param  __HANDLE__: specifies the DAC handle
-  * @param  __DAC_CHANNEL__: specifies the DAC channel.
-  * @retval None
-  */
-#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_CHANNEL__) \
-((__HANDLE__)->Instance->CR &=  ~(DAC_CR_EN1 << (__DAC_CHANNEL__)))
-
-
-/** @brief Enable the DAC interrupt
-  * @param  __HANDLE__: specifies the DAC handle
-  * @param  __INTERRUPT__: specifies the DAC interrupt.
-  * @retval None
-  */
-#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
-
-/** @brief Disable the DAC interrupt
-  * @param  __HANDLE__: specifies the DAC handle
-  * @param  __INTERRUPT__: specifies the DAC interrupt.
-  * @retval None
-  */
-#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
-
-/** @brief  Checks if the specified DAC interrupt source is enabled or disabled.
-  * @param __HANDLE__: DAC handle
-  * @param __INTERRUPT__: DAC interrupt source to check
-  *          This parameter can be any combination of the following values:
-  *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
-  *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
-  * @retval State of interruption (SET or RESET)
-  */
-#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/** @brief  Get the selected DAC's flag status.
-  * @param  __HANDLE__: specifies the DAC handle.
-  * @param  __FLAG__: specifies the flag to clear.
-  *         This parameter can be any combination of the following values:
-  *            @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag
-  *            @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag
-  * @retval None
-  */
-#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Clear the DAC's flag.
-  * @param  __HANDLE__: specifies the DAC handle.
-  * @param  __FLAG__: specifies the flag to clear.
-  *         This parameter can be any combination of the following values:
-  *            @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag
-  *            @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag
-  * @retval None
-  */
-#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
-/**
-  * @}
-  */
-
-/* Include DAC HAL Extension module */
-#include "stm32f7xx_hal_dac_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup DAC_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup DAC_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization/de-initialization functions *********************************/
-HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
-HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
-void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
-void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
-/**
-  * @}
-  */
-
-/** @addtogroup DAC_Exported_Functions_Group2
-  * @{
-  */
-/* I/O operation functions ****************************************************/
-HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
-HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
-uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
-/**
-  * @}
-  */
-
-/** @addtogroup DAC_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
-/**
-  * @}
-  */
-
-/** @addtogroup DAC_Exported_Functions_Group4
-  * @{
-  */
-/* Peripheral State functions *************************************************/
-HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
-void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
-uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
-
-void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
-void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
-void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
-void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup DAC_Private_Constants DAC Private Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup DAC_Private_Macros DAC Private Macros
-  * @{
-  */
-#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U)
-#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
-                             ((ALIGN) == DAC_ALIGN_12B_L) || \
-                             ((ALIGN) == DAC_ALIGN_8B_R))
-#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
-                                 ((CHANNEL) == DAC_CHANNEL_2))
-#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
-                                           ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
-
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
-                                 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
-
-/** @brief Set DHR12R1 alignment
-  * @param  __ALIGNMENT__: specifies the DAC alignment
-  * @retval None
-  */
-#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008U) + (__ALIGNMENT__))
-
-/** @brief  Set DHR12R2 alignment
-  * @param  __ALIGNMENT__: specifies the DAC alignment
-  * @retval None
-  */
-#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014U) + (__ALIGNMENT__))
-
-/** @brief  Set DHR12RD alignment
-  * @param  __ALIGNMENT__: specifies the DAC alignment
-  * @retval None
-  */
-#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020U) + (__ALIGNMENT__))
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup DAC_Private_Functions DAC Private Functions
-  * @{
-  */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F7xx_HAL_DAC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_dac_ex.h b/stmhal/hal/f7/inc/stm32f7xx_hal_dac_ex.h
deleted file mode 100644
index fc1506eeb4..0000000000
--- a/stmhal/hal/f7/inc/stm32f7xx_hal_dac_ex.h
+++ /dev/null
@@ -1,191 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_dac.h
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   Header file of DAC HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_DAC_EX_H
-#define __STM32F7xx_HAL_DAC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal_def.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup DACEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup DACEx_Exported_Constants DAC Exported Constants
-  * @{
-  */
-
-/** @defgroup DACEx_lfsrunmask_triangleamplitude DAC LFS Run Mask Triangle Amplitude
-  * @{
-  */
-#define DAC_LFSRUNMASK_BIT0                ((uint32_t)0x00000000U) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
-#define DAC_LFSRUNMASK_BITS1_0             ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS2_0             ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS3_0             ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS4_0             ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS5_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS6_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS7_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS8_0             ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS9_0             ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS10_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS11_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
-#define DAC_TRIANGLEAMPLITUDE_1            ((uint32_t)0x00000000U) /*!< Select max triangle amplitude of 1 */
-#define DAC_TRIANGLEAMPLITUDE_3            ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
-#define DAC_TRIANGLEAMPLITUDE_7            ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
-#define DAC_TRIANGLEAMPLITUDE_15           ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
-#define DAC_TRIANGLEAMPLITUDE_31           ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */
-#define DAC_TRIANGLEAMPLITUDE_63           ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
-#define DAC_TRIANGLEAMPLITUDE_127          ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */
-#define DAC_TRIANGLEAMPLITUDE_255          ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
-#define DAC_TRIANGLEAMPLITUDE_511          ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */
-#define DAC_TRIANGLEAMPLITUDE_1023         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
-#define DAC_TRIANGLEAMPLITUDE_2047         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
-#define DAC_TRIANGLEAMPLITUDE_4095         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup DACEx_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup DACEx_Exported_Functions_Group1
-  * @{
-  */
-/* Extension features functions ***********************************************/
-uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
-HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
-HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
-HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
-
-void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup DACEx_Private_Constants DAC Private Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup DACEx_Private_Macros DAC Private Macros
-  * @{
-  */
-#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup DACEx_Private_Functions DAC Private Functions
-  * @{
-  */
-void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
-void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
-void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F7xx_HAL_DAC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_def.h b/stmhal/hal/f7/inc/stm32f7xx_hal_def.h
deleted file mode 100644
index 66e0af0386..0000000000
--- a/stmhal/hal/f7/inc/stm32f7xx_hal_def.h
+++ /dev/null
@@ -1,213 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_def.h
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   This file contains HAL common defines, enumeration, macros and
-  *          structures definitions.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_DEF
-#define __STM32F7xx_HAL_DEF
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx.h"
-#include "Legacy/stm32_hal_legacy.h"
-#include <stdio.h>
-/* Exported types ------------------------------------------------------------*/
-
-/**
-  * @brief  HAL Status structures definition
-  */
-typedef enum
-{
-  HAL_OK       = 0x00U,
-  HAL_ERROR    = 0x01U,
-  HAL_BUSY     = 0x02U,
-  HAL_TIMEOUT  = 0x03U
-} HAL_StatusTypeDef;
-
-/**
-  * @brief  HAL Lock structures definition
-  */
-typedef enum
-{
-  HAL_UNLOCKED = 0x00,
-  HAL_LOCKED   = 0x01
-} HAL_LockTypeDef;
-
-/* Exported macro ------------------------------------------------------------*/
-#define HAL_MAX_DELAY      0xFFFFFFFFU
-
-#define HAL_IS_BIT_SET(REG, BIT)         (((REG) & (BIT)) != RESET)
-#define HAL_IS_BIT_CLR(REG, BIT)         (((REG) & (BIT)) == RESET)
-
-#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__)               \
-                        do{                                                      \
-                              (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
-                              (__DMA_HANDLE__).Parent = (__HANDLE__);             \
-                          } while(0)
-
-#define UNUSED(x) ((void)(x))
-
-/** @brief Reset the Handle's State field.
-  * @param __HANDLE__: specifies the Peripheral Handle.
-  * @note  This macro can be used for the following purpose:
-  *          - When the Handle is declared as local variable; before passing it as parameter
-  *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro
-  *            to set to 0 the Handle's "State" field.
-  *            Otherwise, "State" field may have any random value and the first time the function
-  *            HAL_PPP_Init() is called, the low level hardware initialization will be missed
-  *            (i.e. HAL_PPP_MspInit() will not be executed).
-  *          - When there is a need to reconfigure the low level hardware: instead of calling
-  *            HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
-  *            In this later function, when the Handle's "State" field is set to 0, it will execute the function
-  *            HAL_PPP_MspInit() which will reconfigure the low level hardware.
-  * @retval None
-  */
-#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
-
-#if (USE_RTOS == 1)
-  /* Reserved for future use */
-  #error "USE_RTOS should be 0 in the current HAL release"
-#else
-  #define __HAL_LOCK(__HANDLE__)                                           \
-                                do{                                        \
-                                    if((__HANDLE__)->Lock == HAL_LOCKED)   \
-                                    {                                      \
-                                       return HAL_BUSY;                    \
-                                    }                                      \
-                                    else                                   \
-                                    {                                      \
-                                       (__HANDLE__)->Lock = HAL_LOCKED;    \
-                                    }                                      \
-                                  }while (0)
-
-  #define __HAL_UNLOCK(__HANDLE__)                                          \
-                                  do{                                       \
-                                      (__HANDLE__)->Lock = HAL_UNLOCKED;    \
-                                    }while (0)
-#endif /* USE_RTOS */
-
-#if  defined ( __GNUC__ )
-  #ifndef __weak
-    #define __weak   __attribute__((weak))
-  #endif /* __weak */
-  #ifndef __packed
-    #define __packed __attribute__((__packed__))
-  #endif /* __packed */
-#endif /* __GNUC__ */
-
-
-/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
-#if defined   (__GNUC__)        /* GNU Compiler */
-  #ifndef __ALIGN_END
-    #define __ALIGN_END    __attribute__ ((aligned (4)))
-  #endif /* __ALIGN_END */
-  #ifndef __ALIGN_BEGIN
-    #define __ALIGN_BEGIN
-  #endif /* __ALIGN_BEGIN */
-#else
-  #ifndef __ALIGN_END
-    #define __ALIGN_END
-  #endif /* __ALIGN_END */
-  #ifndef __ALIGN_BEGIN
-    #if defined   (__CC_ARM)      /* ARM Compiler */
-      #define __ALIGN_BEGIN    __align(4)
-    #elif defined (__ICCARM__)    /* IAR Compiler */
-      #define __ALIGN_BEGIN
-    #endif /* __CC_ARM */
-  #endif /* __ALIGN_BEGIN */
-#endif /* __GNUC__ */
-
-
-/**
-  * @brief  __RAM_FUNC definition
-  */
-#if defined ( __CC_ARM   )
-/* ARM Compiler
-   ------------
-   RAM functions are defined using the toolchain options.
-   Functions that are executed in RAM should reside in a separate source module.
-   Using the 'Options for File' dialog you can simply change the 'Code / Const'
-   area of a module to a memory space in physical RAM.
-   Available memory areas are declared in the 'Target' tab of the 'Options for Target'
-   dialog.
-*/
-#define __RAM_FUNC HAL_StatusTypeDef
-
-#elif defined ( __ICCARM__ )
-/* ICCARM Compiler
-   ---------------
-   RAM functions are defined using a specific toolchain keyword "__ramfunc".
-*/
-#define __RAM_FUNC __ramfunc HAL_StatusTypeDef
-
-#elif defined   (  __GNUC__  )
-/* GNU Compiler
-   ------------
-  RAM functions are defined using a specific toolchain attribute
-   "__attribute__((section(".RamFunc")))".
-*/
-#define __RAM_FUNC HAL_StatusTypeDef  __attribute__((section(".RamFunc")))
-
-#endif
-
-/**
-  * @brief  __NOINLINE definition
-  */
-#if defined ( __CC_ARM   ) || defined   (  __GNUC__  )
-/* ARM & GNUCompiler
-   ----------------
-*/
-#define __NOINLINE __attribute__ ( (noinline) )
-
-#elif defined ( __ICCARM__ )
-/* ICCARM Compiler
-   ---------------
-*/
-#define __NOINLINE _Pragma("optimize = no_inline")
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ___STM32F7xx_HAL_DEF */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_dma.h b/stmhal/hal/f7/inc/stm32f7xx_hal_dma.h
deleted file mode 100644
index e9ecae8a21..0000000000
--- a/stmhal/hal/f7/inc/stm32f7xx_hal_dma.h
+++ /dev/null
@@ -1,768 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_dma.h
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   Header file of DMA HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_DMA_H
-#define __STM32F7xx_HAL_DMA_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal_def.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup DMA
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Types DMA Exported Types
-  * @brief    DMA Exported Types
-  * @{
-  */
-
-/**
-  * @brief  DMA Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t Channel;              /*!< Specifies the channel used for the specified stream.
-                                      This parameter can be a value of @ref DMAEx_Channel_selection                  */
-
-  uint32_t Direction;            /*!< Specifies if the data will be transferred from memory to peripheral,
-                                      from memory to memory or from peripheral to memory.
-                                      This parameter can be a value of @ref DMA_Data_transfer_direction              */
-
-  uint32_t PeriphInc;            /*!< Specifies whether the Peripheral address register should be incremented or not.
-                                      This parameter can be a value of @ref DMA_Peripheral_incremented_mode          */
-
-  uint32_t MemInc;               /*!< Specifies whether the memory address register should be incremented or not.
-                                      This parameter can be a value of @ref DMA_Memory_incremented_mode              */
-
-  uint32_t PeriphDataAlignment;  /*!< Specifies the Peripheral data width.
-                                      This parameter can be a value of @ref DMA_Peripheral_data_size                 */
-
-  uint32_t MemDataAlignment;     /*!< Specifies the Memory data width.
-                                      This parameter can be a value of @ref DMA_Memory_data_size                     */
-
-  uint32_t Mode;                 /*!< Specifies the operation mode of the DMAy Streamx.
-                                      This parameter can be a value of @ref DMA_mode
-                                      @note The circular buffer mode cannot be used if the memory-to-memory
-                                            data transfer is configured on the selected Stream                        */
-
-  uint32_t Priority;             /*!< Specifies the software priority for the DMAy Streamx.
-                                      This parameter can be a value of @ref DMA_Priority_level                       */
-
-  uint32_t FIFOMode;             /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
-                                      This parameter can be a value of @ref DMA_FIFO_direct_mode
-                                      @note The Direct mode (FIFO mode disabled) cannot be used if the
-                                            memory-to-memory data transfer is configured on the selected stream       */
-
-  uint32_t FIFOThreshold;        /*!< Specifies the FIFO threshold level.
-                                      This parameter can be a value of @ref DMA_FIFO_threshold_level                  */
-
-  uint32_t MemBurst;             /*!< Specifies the Burst transfer configuration for the memory transfers.
-                                      It specifies the amount of data to be transferred in a single non interruptible
-                                      transaction.
-                                      This parameter can be a value of @ref DMA_Memory_burst
-                                      @note The burst mode is possible only if the address Increment mode is enabled. */
-
-  uint32_t PeriphBurst;          /*!< Specifies the Burst transfer configuration for the peripheral transfers.
-                                      It specifies the amount of data to be transferred in a single non interruptible
-                                      transaction.
-                                      This parameter can be a value of @ref DMA_Peripheral_burst
-                                      @note The burst mode is possible only if the address Increment mode is enabled. */
-}DMA_InitTypeDef;
-
-/**
-  * @brief  HAL DMA State structures definition
-  */
-typedef enum
-{
-  HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled */
-  HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use   */
-  HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing              */
-  HAL_DMA_STATE_TIMEOUT           = 0x03U,  /*!< DMA timeout state                   */
-  HAL_DMA_STATE_ERROR             = 0x04U,  /*!< DMA error state                     */
-  HAL_DMA_STATE_ABORT             = 0x05U,  /*!< DMA Abort state                     */
-}HAL_DMA_StateTypeDef;
-
-/**
-  * @brief  HAL DMA Error Code structure definition
-  */
-typedef enum
-{
-  HAL_DMA_FULL_TRANSFER      = 0x00U,    /*!< Full transfer     */
-  HAL_DMA_HALF_TRANSFER      = 0x01U,    /*!< Half Transfer     */
-}HAL_DMA_LevelCompleteTypeDef;
-
-/**
-  * @brief  HAL DMA Error Code structure definition
-  */
-typedef enum
-{
-  HAL_DMA_XFER_CPLT_CB_ID          = 0x00U,    /*!< Full transfer     */
-  HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01U,    /*!< Half Transfer     */
-  HAL_DMA_XFER_M1CPLT_CB_ID        = 0x02U,    /*!< M1 Full Transfer  */
-  HAL_DMA_XFER_M1HALFCPLT_CB_ID    = 0x03U,    /*!< M1 Half Transfer  */
-  HAL_DMA_XFER_ERROR_CB_ID         = 0x04U,    /*!< Error             */
-  HAL_DMA_XFER_ABORT_CB_ID         = 0x05U,    /*!< Abort             */
-  HAL_DMA_XFER_ALL_CB_ID           = 0x06U     /*!< All               */
-}HAL_DMA_CallbackIDTypeDef;
-
-/**
-  * @brief  DMA handle Structure definition
-  */
-typedef struct __DMA_HandleTypeDef
-{
-  DMA_Stream_TypeDef         *Instance;                                                    /*!< Register base address                  */
-
-  DMA_InitTypeDef            Init;                                                         /*!< DMA communication parameters           */
-
-  HAL_LockTypeDef            Lock;                                                         /*!< DMA locking object                     */
-
-  __IO HAL_DMA_StateTypeDef  State;                                                        /*!< DMA transfer state                     */
-
-  void                       *Parent;                                                      /*!< Parent object state                    */
-
-  void                       (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA transfer complete callback         */
-
-  void                       (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback    */
-
-  void                       (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer complete Memory1 callback */
-
-  void                       (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer Half complete Memory1 callback */
-
-  void                       (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer error callback            */
-
-  void                       (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer Abort callback            */
-
- __IO uint32_t               ErrorCode;                                                    /*!< DMA Error code                          */
-
- uint32_t                    StreamBaseAddress;                                            /*!< DMA Stream Base Address                */
-
- uint32_t                    StreamIndex;                                                  /*!< DMA Stream Index                       */
-
-}DMA_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Constants DMA Exported Constants
-  * @brief    DMA Exported constants
-  * @{
-  */
-
-/** @defgroup DMA_Error_Code DMA Error Code
-  * @brief    DMA Error Code
-  * @{
-  */
-#define HAL_DMA_ERROR_NONE            ((uint32_t)0x00000000U)    /*!< No error                               */
-#define HAL_DMA_ERROR_TE              ((uint32_t)0x00000001U)    /*!< Transfer error                         */
-#define HAL_DMA_ERROR_FE              ((uint32_t)0x00000002U)    /*!< FIFO error                             */
-#define HAL_DMA_ERROR_DME             ((uint32_t)0x00000004U)    /*!< Direct Mode error                      */
-#define HAL_DMA_ERROR_TIMEOUT         ((uint32_t)0x00000020U)    /*!< Timeout error                          */
-#define HAL_DMA_ERROR_PARAM           ((uint32_t)0x00000040U)    /*!< Parameter error                        */
-#define HAL_DMA_ERROR_NO_XFER         ((uint32_t)0x00000080U)    /*!< Abort requested with no Xfer ongoing   */
-#define HAL_DMA_ERROR_NOT_SUPPORTED   ((uint32_t)0x00000100U)    /*!< Not supported mode                     */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
-  * @brief    DMA data transfer direction
-  * @{
-  */
-#define DMA_PERIPH_TO_MEMORY         ((uint32_t)0x00000000U)      /*!< Peripheral to memory direction */
-#define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_SxCR_DIR_0)  /*!< Memory to peripheral direction */
-#define DMA_MEMORY_TO_MEMORY         ((uint32_t)DMA_SxCR_DIR_1)  /*!< Memory to memory direction     */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
-  * @brief    DMA peripheral incremented mode
-  * @{
-  */
-#define DMA_PINC_ENABLE        ((uint32_t)DMA_SxCR_PINC)  /*!< Peripheral increment mode enable  */
-#define DMA_PINC_DISABLE       ((uint32_t)0x00000000U)     /*!< Peripheral increment mode disable */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
-  * @brief    DMA memory incremented mode
-  * @{
-  */
-#define DMA_MINC_ENABLE         ((uint32_t)DMA_SxCR_MINC)  /*!< Memory increment mode enable  */
-#define DMA_MINC_DISABLE        ((uint32_t)0x00000000U)     /*!< Memory increment mode disable */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
-  * @brief    DMA peripheral data size
-  * @{
-  */
-#define DMA_PDATAALIGN_BYTE          ((uint32_t)0x00000000U)        /*!< Peripheral data alignment: Byte     */
-#define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_SxCR_PSIZE_0)  /*!< Peripheral data alignment: HalfWord */
-#define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_SxCR_PSIZE_1)  /*!< Peripheral data alignment: Word     */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Memory_data_size DMA Memory data size
-  * @brief    DMA memory data size
-  * @{
-  */
-#define DMA_MDATAALIGN_BYTE          ((uint32_t)0x00000000U)        /*!< Memory data alignment: Byte     */
-#define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_SxCR_MSIZE_0)  /*!< Memory data alignment: HalfWord */
-#define DMA_MDATAALIGN_WORD          ((uint32_t)DMA_SxCR_MSIZE_1)  /*!< Memory data alignment: Word     */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_mode DMA mode
-  * @brief    DMA mode
-  * @{
-  */
-#define DMA_NORMAL         ((uint32_t)0x00000000U)       /*!< Normal mode                  */
-#define DMA_CIRCULAR       ((uint32_t)DMA_SxCR_CIRC)    /*!< Circular mode                */
-#define DMA_PFCTRL         ((uint32_t)DMA_SxCR_PFCTRL)  /*!< Peripheral flow control mode */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Priority_level DMA Priority level
-  * @brief    DMA priority levels
-  * @{
-  */
-#define DMA_PRIORITY_LOW             ((uint32_t)0x00000000U)     /*!< Priority level: Low       */
-#define DMA_PRIORITY_MEDIUM          ((uint32_t)DMA_SxCR_PL_0)  /*!< Priority level: Medium    */
-#define DMA_PRIORITY_HIGH            ((uint32_t)DMA_SxCR_PL_1)  /*!< Priority level: High      */
-#define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_SxCR_PL)    /*!< Priority level: Very High */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
-  * @brief    DMA FIFO direct mode
-  * @{
-  */
-#define DMA_FIFOMODE_DISABLE        ((uint32_t)0x00000000U)       /*!< FIFO mode disable */
-#define DMA_FIFOMODE_ENABLE         ((uint32_t)DMA_SxFCR_DMDIS)  /*!< FIFO mode enable  */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
-  * @brief    DMA FIFO level
-  * @{
-  */
-#define DMA_FIFO_THRESHOLD_1QUARTERFULL       ((uint32_t)0x00000000U)       /*!< FIFO threshold 1 quart full configuration  */
-#define DMA_FIFO_THRESHOLD_HALFFULL           ((uint32_t)DMA_SxFCR_FTH_0)  /*!< FIFO threshold half full configuration     */
-#define DMA_FIFO_THRESHOLD_3QUARTERSFULL      ((uint32_t)DMA_SxFCR_FTH_1)  /*!< FIFO threshold 3 quarts full configuration */
-#define DMA_FIFO_THRESHOLD_FULL               ((uint32_t)DMA_SxFCR_FTH)    /*!< FIFO threshold full configuration          */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Memory_burst DMA Memory burst
-  * @brief    DMA memory burst
-  * @{
-  */
-#define DMA_MBURST_SINGLE       ((uint32_t)0x00000000U)
-#define DMA_MBURST_INC4         ((uint32_t)DMA_SxCR_MBURST_0)
-#define DMA_MBURST_INC8         ((uint32_t)DMA_SxCR_MBURST_1)
-#define DMA_MBURST_INC16        ((uint32_t)DMA_SxCR_MBURST)
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Peripheral_burst DMA Peripheral burst
-  * @brief    DMA peripheral burst
-  * @{
-  */
-#define DMA_PBURST_SINGLE       ((uint32_t)0x00000000U)
-#define DMA_PBURST_INC4         ((uint32_t)DMA_SxCR_PBURST_0)
-#define DMA_PBURST_INC8         ((uint32_t)DMA_SxCR_PBURST_1)
-#define DMA_PBURST_INC16        ((uint32_t)DMA_SxCR_PBURST)
-/**
-  * @}
-  */
-
-/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
-  * @brief    DMA interrupts definition
-  * @{
-  */
-#define DMA_IT_TC                         ((uint32_t)DMA_SxCR_TCIE)
-#define DMA_IT_HT                         ((uint32_t)DMA_SxCR_HTIE)
-#define DMA_IT_TE                         ((uint32_t)DMA_SxCR_TEIE)
-#define DMA_IT_DME                        ((uint32_t)DMA_SxCR_DMEIE)
-#define DMA_IT_FE                         ((uint32_t)0x00000080U)
-/**
-  * @}
-  */
-
-/** @defgroup DMA_flag_definitions DMA flag definitions
-  * @brief    DMA flag definitions
-  * @{
-  */
-#define DMA_FLAG_FEIF0_4                    ((uint32_t)0x00800001U)
-#define DMA_FLAG_DMEIF0_4                   ((uint32_t)0x00800004U)
-#define DMA_FLAG_TEIF0_4                    ((uint32_t)0x00000008U)
-#define DMA_FLAG_HTIF0_4                    ((uint32_t)0x00000010U)
-#define DMA_FLAG_TCIF0_4                    ((uint32_t)0x00000020U)
-#define DMA_FLAG_FEIF1_5                    ((uint32_t)0x00000040U)
-#define DMA_FLAG_DMEIF1_5                   ((uint32_t)0x00000100U)
-#define DMA_FLAG_TEIF1_5                    ((uint32_t)0x00000200U)
-#define DMA_FLAG_HTIF1_5                    ((uint32_t)0x00000400U)
-#define DMA_FLAG_TCIF1_5                    ((uint32_t)0x00000800U)
-#define DMA_FLAG_FEIF2_6                    ((uint32_t)0x00010000U)
-#define DMA_FLAG_DMEIF2_6                   ((uint32_t)0x00040000U)
-#define DMA_FLAG_TEIF2_6                    ((uint32_t)0x00080000U)
-#define DMA_FLAG_HTIF2_6                    ((uint32_t)0x00100000U)
-#define DMA_FLAG_TCIF2_6                    ((uint32_t)0x00200000U)
-#define DMA_FLAG_FEIF3_7                    ((uint32_t)0x00400000U)
-#define DMA_FLAG_DMEIF3_7                   ((uint32_t)0x01000000U)
-#define DMA_FLAG_TEIF3_7                    ((uint32_t)0x02000000U)
-#define DMA_FLAG_HTIF3_7                    ((uint32_t)0x04000000U)
-#define DMA_FLAG_TCIF3_7                    ((uint32_t)0x08000000U)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @brief Reset DMA handle state
-  * @param  __HANDLE__: specifies the DMA handle.
-  * @retval None
-  */
-#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
-
-/**
-  * @brief  Return the current DMA Stream FIFO filled level.
-  * @param  __HANDLE__: DMA handle
-  * @retval The FIFO filling state.
-  *           - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
-  *                                              and not empty.
-  *           - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
-  *           - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
-  *           - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
-  *           - DMA_FIFOStatus_Empty: when FIFO is empty
-  *           - DMA_FIFOStatus_Full: when FIFO is full
-  */
-#define __HAL_DMA_GET_FS(__HANDLE__)      (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
-
-/**
-  * @brief  Enable the specified DMA Stream.
-  * @param  __HANDLE__: DMA handle
-  * @retval None
-  */
-#define __HAL_DMA_ENABLE(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  DMA_SxCR_EN)
-
-/**
-  * @brief  Disable the specified DMA Stream.
-  * @param  __HANDLE__: DMA handle
-  * @retval None
-  */
-#define __HAL_DMA_DISABLE(__HANDLE__)     ((__HANDLE__)->Instance->CR &=  ~DMA_SxCR_EN)
-
-/* Interrupt & Flag management */
-
-/**
-  * @brief  Return the current DMA Stream transfer complete flag.
-  * @param  __HANDLE__: DMA handle
-  * @retval The specified transfer complete flag index.
-  */
-#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
-   DMA_FLAG_TCIF3_7)
-
-/**
-  * @brief  Return the current DMA Stream half transfer complete flag.
-  * @param  __HANDLE__: DMA handle
-  * @retval The specified half transfer complete flag index.
-  */
-#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
-   DMA_FLAG_HTIF3_7)
-
-/**
-  * @brief  Return the current DMA Stream transfer error flag.
-  * @param  __HANDLE__: DMA handle
-  * @retval The specified transfer error flag index.
-  */
-#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
-   DMA_FLAG_TEIF3_7)
-
-/**
-  * @brief  Return the current DMA Stream FIFO error flag.
-  * @param  __HANDLE__: DMA handle
-  * @retval The specified FIFO error flag index.
-  */
-#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
-   DMA_FLAG_FEIF3_7)
-
-/**
-  * @brief  Return the current DMA Stream direct mode error flag.
-  * @param  __HANDLE__: DMA handle
-  * @retval The specified direct mode error flag index.
-  */
-#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
-   DMA_FLAG_DMEIF3_7)
-
-/**
-  * @brief  Get the DMA Stream pending flags.
-  * @param  __HANDLE__: DMA handle
-  * @param  __FLAG__: Get the specified flag.
-  *          This parameter can be any combination of the following values:
-  *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
-  *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
-  *            @arg DMA_FLAG_TEIFx: Transfer error flag.
-  *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.
-  *            @arg DMA_FLAG_FEIFx: FIFO error flag.
-  *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
-  * @retval The state of FLAG (SET or RESET).
-  */
-#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
-(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
- ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
- ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
-
-/**
-  * @brief  Clear the DMA Stream pending flags.
-  * @param  __HANDLE__: DMA handle
-  * @param  __FLAG__: specifies the flag to clear.
-  *          This parameter can be any combination of the following values:
-  *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
-  *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
-  *            @arg DMA_FLAG_TEIFx: Transfer error flag.
-  *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.
-  *            @arg DMA_FLAG_FEIFx: FIFO error flag.
-  *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
-  * @retval None
-  */
-#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
-(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
- ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
- ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
-
-/**
-  * @brief  Enable the specified DMA Stream interrupts.
-  * @param  __HANDLE__: DMA handle
-  * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
-  *        This parameter can be one of the following values:
-  *           @arg DMA_IT_TC: Transfer complete interrupt mask.
-  *           @arg DMA_IT_HT: Half transfer complete interrupt mask.
-  *           @arg DMA_IT_TE: Transfer error interrupt mask.
-  *           @arg DMA_IT_FE: FIFO error interrupt mask.
-  *           @arg DMA_IT_DME: Direct mode error interrupt.
-  * @retval None
-  */
-#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((__INTERRUPT__) != DMA_IT_FE)? \
-((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
-
-/**
-  * @brief  Disable the specified DMA Stream interrupts.
-  * @param  __HANDLE__: DMA handle
-  * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
-  *         This parameter can be one of the following values:
-  *            @arg DMA_IT_TC: Transfer complete interrupt mask.
-  *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
-  *            @arg DMA_IT_TE: Transfer error interrupt mask.
-  *            @arg DMA_IT_FE: FIFO error interrupt mask.
-  *            @arg DMA_IT_DME: Direct mode error interrupt.
-  * @retval None
-  */
-#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \
-((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
-
-/**
-  * @brief  Check whether the specified DMA Stream interrupt is enabled or not.
-  * @param  __HANDLE__: DMA handle
-  * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
-  *         This parameter can be one of the following values:
-  *            @arg DMA_IT_TC: Transfer complete interrupt mask.
-  *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
-  *            @arg DMA_IT_TE: Transfer error interrupt mask.
-  *            @arg DMA_IT_FE: FIFO error interrupt mask.
-  *            @arg DMA_IT_DME: Direct mode error interrupt.
-  * @retval The state of DMA_IT.
-  */
-#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \
-                                                        ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
-                                                        ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
-
-/**
-  * @brief  Writes the number of data units to be transferred on the DMA Stream.
-  * @param  __HANDLE__: DMA handle
-  * @param  __COUNTER__: Number of data units to be transferred (from 0 to 65535)
-  *          Number of data items depends only on the Peripheral data format.
-  *
-  * @note   If Peripheral data format is Bytes: number of data units is equal
-  *         to total number of bytes to be transferred.
-  *
-  * @note   If Peripheral data format is Half-Word: number of data units is
-  *         equal to total number of bytes to be transferred / 2.
-  *
-  * @note   If Peripheral data format is Word: number of data units is equal
-  *         to total  number of bytes to be transferred / 4.
-  *
-  * @retval The number of remaining data units in the current DMAy Streamx transfer.
-  */
-#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
-
-/**
-  * @brief  Returns the number of remaining data units in the current DMAy Streamx transfer.
-  * @param  __HANDLE__: DMA handle
-  *
-  * @retval The number of remaining data units in the current DMA Stream transfer.
-  */
-#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
-
-
-/* Include DMA HAL Extension module */
-#include "stm32f7xx_hal_dma_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Functions DMA Exported Functions
-  * @brief    DMA Exported functions
-  * @{
-  */
-
-/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @brief   Initialization and de-initialization functions
-  * @{
-  */
-HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
-  * @brief   I/O operation functions
-  * @{
-  */
-HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
-void              HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
-HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
-  * @brief    Peripheral State functions
-  * @{
-  */
-HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
-uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-/* Private Constants -------------------------------------------------------------*/
-/** @defgroup DMA_Private_Constants DMA Private Constants
-  * @brief    DMA private defines and constants
-  * @{
-  */
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup DMA_Private_Macros DMA Private Macros
-  * @brief    DMA private macros
-  * @{
-  */
-#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
-                                     ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
-                                     ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
-
-#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
-
-#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
-                                            ((STATE) == DMA_PINC_DISABLE))
-
-#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
-                                        ((STATE) == DMA_MINC_DISABLE))
-
-#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
-                                           ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
-                                           ((SIZE) == DMA_PDATAALIGN_WORD))
-
-#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
-                                       ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
-                                       ((SIZE) == DMA_MDATAALIGN_WORD ))
-
-#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
-                           ((MODE) == DMA_CIRCULAR) || \
-                           ((MODE) == DMA_PFCTRL))
-
-#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
-                                   ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
-                                   ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
-                                   ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
-
-#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
-                                       ((STATE) == DMA_FIFOMODE_ENABLE))
-
-#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
-                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL)      || \
-                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
-                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
-
-#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
-                                    ((BURST) == DMA_MBURST_INC4)   || \
-                                    ((BURST) == DMA_MBURST_INC8)   || \
-                                    ((BURST) == DMA_MBURST_INC16))
-
-#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
-                                        ((BURST) == DMA_PBURST_INC4)   || \
-                                        ((BURST) == DMA_PBURST_INC8)   || \
-                                        ((BURST) == DMA_PBURST_INC16))
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup DMA_Private_Functions DMA Private Functions
-  * @brief    DMA private  functions
-  * @{
-  */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F7xx_HAL_DMA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_dma_ex.h b/stmhal/hal/f7/inc/stm32f7xx_hal_dma_ex.h
deleted file mode 100644
index 433d279c4c..0000000000
--- a/stmhal/hal/f7/inc/stm32f7xx_hal_dma_ex.h
+++ /dev/null
@@ -1,197 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_dma_ex.h
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   Header file of DMA HAL extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_DMA_EX_H
-#define __STM32F7xx_HAL_DMA_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal_def.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup DMAEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
-  * @brief DMAEx Exported types
-  * @{
-  */
-
-/**
-  * @brief  HAL DMA Memory definition
-  */
-typedef enum
-{
-  MEMORY0      = 0x00U,    /*!< Memory 0     */
-  MEMORY1      = 0x01U,    /*!< Memory 1     */
-
-}HAL_DMA_MemoryTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Constants DMA Exported Constants
-  * @brief    DMA Exported constants
-  * @{
-  */
-
-/** @defgroup DMAEx_Channel_selection DMA Channel selection
-  * @brief    DMAEx channel selection
-  * @{
-  */
-#define DMA_CHANNEL_0        ((uint32_t)0x00000000U)  /*!< DMA Channel 0 */
-#define DMA_CHANNEL_1        ((uint32_t)0x02000000U)  /*!< DMA Channel 1 */
-#define DMA_CHANNEL_2        ((uint32_t)0x04000000U)  /*!< DMA Channel 2 */
-#define DMA_CHANNEL_3        ((uint32_t)0x06000000U)  /*!< DMA Channel 3 */
-#define DMA_CHANNEL_4        ((uint32_t)0x08000000U)  /*!< DMA Channel 4 */
-#define DMA_CHANNEL_5        ((uint32_t)0x0A000000U)  /*!< DMA Channel 5 */
-#define DMA_CHANNEL_6        ((uint32_t)0x0C000000U)  /*!< DMA Channel 6 */
-#define DMA_CHANNEL_7        ((uint32_t)0x0E000000U)  /*!< DMA Channel 7 */
-#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
-#define DMA_CHANNEL_8        ((uint32_t)0x10000000U)  /*!< DMA Channel 8 */
-#define DMA_CHANNEL_9        ((uint32_t)0x12000000U)  /*!< DMA Channel 9 */
-#define DMA_CHANNEL_10       ((uint32_t)0x14000000U)  /*!< DMA Channel 10*/
-#define DMA_CHANNEL_11       ((uint32_t)0x16000000U)  /*!< DMA Channel 11*/
-#define DMA_CHANNEL_12       ((uint32_t)0x18000000U)  /*!< DMA Channel 12*/
-#define DMA_CHANNEL_13       ((uint32_t)0x1A000000U)  /*!< DMA Channel 13*/
-#define DMA_CHANNEL_14       ((uint32_t)0x1C000000U)  /*!< DMA Channel 14*/
-#define DMA_CHANNEL_15       ((uint32_t)0x1E000000U)  /*!< DMA Channel 15*/
-#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
-  * @brief   DMAEx Exported functions
-  * @{
-  */
-
-/** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions
-  * @brief   Extended features functions
-  * @{
-  */
-
-/* IO operation functions *******************************************************/
-HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
-HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
-HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory);
-
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup DMAEx_Private_Macros DMA Private Macros
-  * @brief    DMAEx private macros
-  * @{
-  */
-#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
-#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0)  || \
-                                 ((CHANNEL) == DMA_CHANNEL_1)  || \
-                                 ((CHANNEL) == DMA_CHANNEL_2)  || \
-                                 ((CHANNEL) == DMA_CHANNEL_3)  || \
-                                 ((CHANNEL) == DMA_CHANNEL_4)  || \
-                                 ((CHANNEL) == DMA_CHANNEL_5)  || \
-                                 ((CHANNEL) == DMA_CHANNEL_6)  || \
-                                 ((CHANNEL) == DMA_CHANNEL_7)  || \
-                                 ((CHANNEL) == DMA_CHANNEL_8)  || \
-                                 ((CHANNEL) == DMA_CHANNEL_9)  || \
-                                 ((CHANNEL) == DMA_CHANNEL_10) || \
-                                 ((CHANNEL) == DMA_CHANNEL_11) || \
-                                 ((CHANNEL) == DMA_CHANNEL_12) || \
-                                 ((CHANNEL) == DMA_CHANNEL_13) || \
-                                 ((CHANNEL) == DMA_CHANNEL_14) || \
-                                 ((CHANNEL) == DMA_CHANNEL_15))
-#else
-#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
-                                 ((CHANNEL) == DMA_CHANNEL_1) || \
-                                 ((CHANNEL) == DMA_CHANNEL_2) || \
-                                 ((CHANNEL) == DMA_CHANNEL_3) || \
-                                 ((CHANNEL) == DMA_CHANNEL_4) || \
-                                 ((CHANNEL) == DMA_CHANNEL_5) || \
-                                 ((CHANNEL) == DMA_CHANNEL_6) || \
-                                 ((CHANNEL) == DMA_CHANNEL_7))
-#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup DMAEx_Private_Functions DMAEx Private Functions
-  * @brief DMAEx Private functions
-  * @{
-  */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F7xx_HAL_DMA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_flash.h b/stmhal/hal/f7/inc/stm32f7xx_hal_flash.h
deleted file mode 100644
index eaa215d0cc..0000000000
--- a/stmhal/hal/f7/inc/stm32f7xx_hal_flash.h
+++ /dev/null
@@ -1,420 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_flash.h
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   Header file of FLASH HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_FLASH_H
-#define __STM32F7xx_HAL_FLASH_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal_def.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup FLASH
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Types FLASH Exported Types
-  * @{
-  */
-
-/**
-  * @brief  FLASH Procedure structure definition
-  */
-typedef enum
-{
-  FLASH_PROC_NONE = 0U,
-  FLASH_PROC_SECTERASE,
-  FLASH_PROC_MASSERASE,
-  FLASH_PROC_PROGRAM
-} FLASH_ProcedureTypeDef;
-
-
-/**
-  * @brief  FLASH handle Structure definition
-  */
-typedef struct
-{
-  __IO FLASH_ProcedureTypeDef ProcedureOnGoing;   /* Internal variable to indicate which procedure is ongoing or not in IT context */
-
-  __IO uint32_t               NbSectorsToErase;   /* Internal variable to save the remaining sectors to erase in IT context        */
-
-  __IO uint8_t                VoltageForErase;    /* Internal variable to provide voltage range selected by user in IT context     */
-
-  __IO uint32_t               Sector;             /* Internal variable to define the current sector which is erasing               */
-
-  __IO uint32_t               Address;            /* Internal variable to save address selected for program                        */
-
-  HAL_LockTypeDef             Lock;               /* FLASH locking object                                                          */
-
-  __IO uint32_t               ErrorCode;          /* FLASH error code                                                              */
-
-}FLASH_ProcessTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
-  * @{
-  */
-
-/** @defgroup FLASH_Error_Code FLASH Error Code
-  * @brief    FLASH Error Code
-  * @{
-  */
-#define HAL_FLASH_ERROR_NONE         ((uint32_t)0x00000000U)    /*!< No error                      */
-#define HAL_FLASH_ERROR_ERS          ((uint32_t)0x00000002U)    /*!< Programming Sequence error    */
-#define HAL_FLASH_ERROR_PGP          ((uint32_t)0x00000004U)    /*!< Programming Parallelism error */
-#define HAL_FLASH_ERROR_PGA          ((uint32_t)0x00000008U)    /*!< Programming Alignment error   */
-#define HAL_FLASH_ERROR_WRP          ((uint32_t)0x00000010U)    /*!< Write protection error        */
-#define HAL_FLASH_ERROR_OPERATION    ((uint32_t)0x00000020U)    /*!< Operation Error               */
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Type_Program FLASH Type Program
-  * @{
-  */
-#define FLASH_TYPEPROGRAM_BYTE        ((uint32_t)0x00U)  /*!< Program byte (8-bit) at a specified address           */
-#define FLASH_TYPEPROGRAM_HALFWORD    ((uint32_t)0x01U)  /*!< Program a half-word (16-bit) at a specified address   */
-#define FLASH_TYPEPROGRAM_WORD        ((uint32_t)0x02U)  /*!< Program a word (32-bit) at a specified address        */
-#define FLASH_TYPEPROGRAM_DOUBLEWORD  ((uint32_t)0x03U)  /*!< Program a double word (64-bit) at a specified address */
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Flag_definition FLASH Flag definition
-  * @brief Flag definition
-  * @{
-  */
-#define FLASH_FLAG_EOP                 FLASH_SR_EOP            /*!< FLASH End of Operation flag               */
-#define FLASH_FLAG_OPERR               FLASH_SR_OPERR          /*!< FLASH operation Error flag                */
-#define FLASH_FLAG_WRPERR              FLASH_SR_WRPERR         /*!< FLASH Write protected error flag          */
-#define FLASH_FLAG_PGAERR              FLASH_SR_PGAERR         /*!< FLASH Programming Alignment error flag    */
-#define FLASH_FLAG_PGPERR              FLASH_SR_PGPERR         /*!< FLASH Programming Parallelism error flag  */
-#define FLASH_FLAG_ERSERR              FLASH_SR_ERSERR         /*!< FLASH Erasing Sequence error flag         */
-#define FLASH_FLAG_BSY                 FLASH_SR_BSY            /*!< FLASH Busy flag                           */
-
-
-#define FLASH_FLAG_ALL_ERRORS     (FLASH_FLAG_OPERR   | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
-                                   FLASH_FLAG_PGPERR  | FLASH_FLAG_ERSERR)
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition
-  * @brief FLASH Interrupt definition
-  * @{
-  */
-#define FLASH_IT_EOP                   FLASH_CR_EOPIE          /*!< End of FLASH Operation Interrupt source */
-#define FLASH_IT_ERR                   ((uint32_t)0x02000000U)  /*!< Error Interrupt source                  */
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism
-  * @{
-  */
-#define FLASH_PSIZE_BYTE           ((uint32_t)0x00000000U)
-#define FLASH_PSIZE_HALF_WORD      ((uint32_t)FLASH_CR_PSIZE_0)
-#define FLASH_PSIZE_WORD           ((uint32_t)FLASH_CR_PSIZE_1)
-#define FLASH_PSIZE_DOUBLE_WORD    ((uint32_t)FLASH_CR_PSIZE)
-#define CR_PSIZE_MASK              ((uint32_t)0xFFFFFCFFU)
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Keys FLASH Keys
-  * @{
-  */
-#define FLASH_KEY1               ((uint32_t)0x45670123U)
-#define FLASH_KEY2               ((uint32_t)0xCDEF89ABU)
-#define FLASH_OPT_KEY1           ((uint32_t)0x08192A3BU)
-#define FLASH_OPT_KEY2           ((uint32_t)0x4C5D6E7FU)
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Sectors FLASH Sectors
-  * @{
-  */
-#define FLASH_SECTOR_0           ((uint32_t)0U) /*!< Sector Number 0   */
-#define FLASH_SECTOR_1           ((uint32_t)1U) /*!< Sector Number 1   */
-#define FLASH_SECTOR_2           ((uint32_t)2U) /*!< Sector Number 2   */
-#define FLASH_SECTOR_3           ((uint32_t)3U) /*!< Sector Number 3   */
-#define FLASH_SECTOR_4           ((uint32_t)4U) /*!< Sector Number 4   */
-#define FLASH_SECTOR_5           ((uint32_t)5U) /*!< Sector Number 5   */
-#define FLASH_SECTOR_6           ((uint32_t)6U) /*!< Sector Number 6   */
-#define FLASH_SECTOR_7           ((uint32_t)7U) /*!< Sector Number 7   */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
-  * @{
-  */
-/**
-  * @brief  Set the FLASH Latency.
-  * @param  __LATENCY__: FLASH Latency
-  *         The value of this parameter depend on device used within the same series
-  * @retval none
-  */
-#define __HAL_FLASH_SET_LATENCY(__LATENCY__) \
-                  MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__))
-
-/**
-  * @brief  Get the FLASH Latency.
-  * @retval FLASH Latency
-  *          The value of this parameter depend on device used within the same series
-  */
-#define __HAL_FLASH_GET_LATENCY()     (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
-
-/**
-  * @brief  Enable the FLASH prefetch buffer.
-  * @retval none
-  */
-#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE()  (FLASH->ACR |= FLASH_ACR_PRFTEN)
-
-/**
-  * @brief  Disable the FLASH prefetch buffer.
-  * @retval none
-  */
-#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE()   (FLASH->ACR &= (~FLASH_ACR_PRFTEN))
-
-/**
-  * @brief  Enable the FLASH Adaptive Real-Time memory accelerator.
-  * @note   The ART accelerator is available only for flash access on ITCM interface.
-  * @retval none
-  */
-#define __HAL_FLASH_ART_ENABLE()  SET_BIT(FLASH->ACR, FLASH_ACR_ARTEN)
-
-/**
-  * @brief  Disable the FLASH Adaptive Real-Time memory accelerator.
-  * @retval none
-  */
-#define __HAL_FLASH_ART_DISABLE()   CLEAR_BIT(FLASH->ACR, FLASH_ACR_ARTEN)
-
-/**
-  * @brief  Resets the FLASH Adaptive Real-Time memory accelerator.
-  * @note   This function must be used only when the Adaptive Real-Time memory accelerator
-  *         is disabled.
-  * @retval None
-  */
-#define __HAL_FLASH_ART_RESET()  (FLASH->ACR |= FLASH_ACR_ARTRST)
-
-/**
-  * @brief  Enable the specified FLASH interrupt.
-  * @param  __INTERRUPT__ : FLASH interrupt
-  *         This parameter can be any combination of the following values:
-  *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
-  *     @arg FLASH_IT_ERR: Error Interrupt
-  * @retval none
-  */
-#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)  (FLASH->CR |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the specified FLASH interrupt.
-  * @param  __INTERRUPT__ : FLASH interrupt
-  *         This parameter can be any combination of the following values:
-  *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
-  *     @arg FLASH_IT_ERR: Error Interrupt
-  * @retval none
-  */
-#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)  (FLASH->CR &= ~(uint32_t)(__INTERRUPT__))
-
-/**
-  * @brief  Get the specified FLASH flag status.
-  * @param  __FLAG__: specifies the FLASH flag to check.
-  *          This parameter can be one of the following values:
-  *            @arg FLASH_FLAG_EOP   : FLASH End of Operation flag
-  *            @arg FLASH_FLAG_OPERR : FLASH operation Error flag
-  *            @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
-  *            @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
-  *            @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
-  *            @arg FLASH_FLAG_ERSERR : FLASH Erasing Sequence error flag
-  *            @arg FLASH_FLAG_BSY   : FLASH Busy flag
-  * @retval The new state of __FLAG__ (SET or RESET).
-  */
-#define __HAL_FLASH_GET_FLAG(__FLAG__)   ((FLASH->SR & (__FLAG__)))
-
-/**
-  * @brief  Clear the specified FLASH flag.
-  * @param  __FLAG__: specifies the FLASH flags to clear.
-  *          This parameter can be any combination of the following values:
-  *            @arg FLASH_FLAG_EOP   : FLASH End of Operation flag
-  *            @arg FLASH_FLAG_OPERR : FLASH operation Error flag
-  *            @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
-  *            @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
-  *            @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
-  *            @arg FLASH_FLAG_ERSERR : FLASH Erasing Sequence error flag
-  * @retval none
-  */
-#define __HAL_FLASH_CLEAR_FLAG(__FLAG__)   (FLASH->SR = (__FLAG__))
-/**
-  * @}
-  */
-
-/* Include FLASH HAL Extension module */
-#include "stm32f7xx_hal_flash_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup FLASH_Exported_Functions
-  * @{
-  */
-/** @addtogroup FLASH_Exported_Functions_Group1
-  * @{
-  */
-/* Program operation functions  ***********************************************/
-HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
-HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
-/* FLASH IRQ handler method */
-void HAL_FLASH_IRQHandler(void);
-/* Callbacks in non blocking modes */
-void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
-void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
-/**
-  * @}
-  */
-
-/** @addtogroup FLASH_Exported_Functions_Group2
-  * @{
-  */
-/* Peripheral Control functions  **********************************************/
-HAL_StatusTypeDef HAL_FLASH_Unlock(void);
-HAL_StatusTypeDef HAL_FLASH_Lock(void);
-HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
-HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
-/* Option bytes control */
-HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
-/**
-  * @}
-  */
-
-/** @addtogroup FLASH_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral State functions  ************************************************/
-uint32_t HAL_FLASH_GetError(void);
-HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup FLASH_Private_Variables FLASH Private Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup FLASH_Private_Constants FLASH Private Constants
-  * @{
-  */
-
-/**
-  * @brief   OPTCR register byte 1 (Bits[15:8]) base address
-  */
-#define OPTCR_BYTE1_ADDRESS         ((uint32_t)0x40023C15)
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup FLASH_Private_Macros FLASH Private Macros
-  * @{
-  */
-
-/** @defgroup FLASH_IS_FLASH_Definitions FLASH Private macros to check input parameters
-  * @{
-  */
-#define IS_FLASH_TYPEPROGRAM(VALUE)(((VALUE) == FLASH_TYPEPROGRAM_BYTE) || \
-                                    ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
-                                    ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \
-                                    ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup FLASH_Private_Functions FLASH Private Functions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F7xx_HAL_FLASH_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_flash_ex.h b/stmhal/hal/f7/inc/stm32f7xx_hal_flash_ex.h
deleted file mode 100644
index 5ad4894754..0000000000
--- a/stmhal/hal/f7/inc/stm32f7xx_hal_flash_ex.h
+++ /dev/null
@@ -1,608 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_flash_ex.h
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   Header file of FLASH HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_FLASH_EX_H
-#define __STM32F7xx_HAL_FLASH_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal_def.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup FLASHEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup FLASHEx_Exported_Types FLASH Exported Types
-  * @{
-  */
-
-/**
-  * @brief  FLASH Erase structure definition
-  */
-typedef struct
-{
-  uint32_t TypeErase;   /*!< Mass erase or sector Erase.
-                             This parameter can be a value of @ref FLASHEx_Type_Erase */
-
-#if defined (FLASH_OPTCR_nDBANK)
-  uint32_t Banks;       /*!< Select banks to erase when Mass erase is enabled.
-                             This parameter must be a value of @ref FLASHEx_Banks */
-#endif /* FLASH_OPTCR_nDBANK */
-
-  uint32_t Sector;      /*!< Initial FLASH sector to erase when Mass erase is disabled
-                             This parameter must be a value of @ref FLASHEx_Sectors */
-
-  uint32_t NbSectors;   /*!< Number of sectors to be erased.
-                             This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
-
-  uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism
-                             This parameter must be a value of @ref FLASHEx_Voltage_Range */
-
-} FLASH_EraseInitTypeDef;
-
-/**
-  * @brief  FLASH Option Bytes Program structure definition
-  */
-typedef struct
-{
-  uint32_t OptionType;   /*!< Option byte to be configured.
-                              This parameter can be a value of @ref FLASHEx_Option_Type */
-
-  uint32_t WRPState;     /*!< Write protection activation or deactivation.
-                              This parameter can be a value of @ref FLASHEx_WRP_State */
-
-  uint32_t WRPSector;    /*!< Specifies the sector(s) to be write protected.
-                              The value of this parameter depend on device used within the same series */
-
-  uint32_t RDPLevel;     /*!< Set the read protection level.
-                              This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
-
-  uint32_t BORLevel;     /*!< Set the BOR Level.
-                              This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */
-
-  uint32_t USERConfig;   /*!< Program the FLASH User Option Byte: WWDG_SW / IWDG_SW / RST_STOP / RST_STDBY /
-                              IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / nDBANK / nDBOOT.
-                              nDBANK / nDBOOT are only available for STM32F76xxx/STM32F77xxx devices */
-
-  uint32_t BootAddr0;    /*!< Boot base address when Boot pin = 0.
-                              This parameter can be a value of @ref FLASHEx_Boot_Address */
-
-  uint32_t BootAddr1;    /*!< Boot base address when Boot pin = 1.
-                              This parameter can be a value of @ref FLASHEx_Boot_Address */
-
-} FLASH_OBProgramInitTypeDef;
-
-/**
-  * @}
-  */
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants
-  * @{
-  */
-
-/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
-  * @{
-  */
-#define FLASH_TYPEERASE_SECTORS         ((uint32_t)0x00U)  /*!< Sectors erase only          */
-#define FLASH_TYPEERASE_MASSERASE       ((uint32_t)0x01U)  /*!< Flash Mass erase activation */
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range
-  * @{
-  */
-#define FLASH_VOLTAGE_RANGE_1        ((uint32_t)0x00U)  /*!< Device operating range: 1.8V to 2.1V                */
-#define FLASH_VOLTAGE_RANGE_2        ((uint32_t)0x01U)  /*!< Device operating range: 2.1V to 2.7V                */
-#define FLASH_VOLTAGE_RANGE_3        ((uint32_t)0x02U)  /*!< Device operating range: 2.7V to 3.6V                */
-#define FLASH_VOLTAGE_RANGE_4        ((uint32_t)0x03U)  /*!< Device operating range: 2.7V to 3.6V + External Vpp */
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_WRP_State FLASH WRP State
-  * @{
-  */
-#define OB_WRPSTATE_DISABLE       ((uint32_t)0x00U)  /*!< Disable the write protection of the desired bank 1 sectors */
-#define OB_WRPSTATE_ENABLE        ((uint32_t)0x01U)  /*!< Enable the write protection of the desired bank 1 sectors  */
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_Option_Type FLASH Option Type
-  * @{
-  */
-#define OPTIONBYTE_WRP         ((uint32_t)0x01U)  /*!< WRP option byte configuration  */
-#define OPTIONBYTE_RDP         ((uint32_t)0x02U)  /*!< RDP option byte configuration  */
-#define OPTIONBYTE_USER        ((uint32_t)0x04U)  /*!< USER option byte configuration */
-#define OPTIONBYTE_BOR         ((uint32_t)0x08U)  /*!< BOR option byte configuration  */
-#define OPTIONBYTE_BOOTADDR_0  ((uint32_t)0x10U)  /*!< Boot 0 Address configuration   */
-#define OPTIONBYTE_BOOTADDR_1  ((uint32_t)0x20U)  /*!< Boot 1 Address configuration   */
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection
-  * @{
-  */
-#define OB_RDP_LEVEL_0       ((uint8_t)0xAAU)
-#define OB_RDP_LEVEL_1       ((uint8_t)0x55U)
-#define OB_RDP_LEVEL_2       ((uint8_t)0xCCU)   /*!< Warning: When enabling read protection level 2
-                                                  it s no more possible to go back to level 1 or 0 */
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_Option_Bytes_WWatchdog FLASH Option Bytes WWatchdog
-  * @{
-  */
-#define OB_WWDG_SW           ((uint32_t)0x10U)  /*!< Software WWDG selected */
-#define OB_WWDG_HW           ((uint32_t)0x00U)  /*!< Hardware WWDG selected */
-/**
-  * @}
-  */
-
-
-/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog
-  * @{
-  */
-#define OB_IWDG_SW           ((uint32_t)0x20U)  /*!< Software IWDG selected */
-#define OB_IWDG_HW           ((uint32_t)0x00U)  /*!< Hardware IWDG selected */
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP
-  * @{
-  */
-#define OB_STOP_NO_RST       ((uint32_t)0x40U) /*!< No reset generated when entering in STOP */
-#define OB_STOP_RST          ((uint32_t)0x00U) /*!< Reset generated when entering in STOP    */
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY
-  * @{
-  */
-#define OB_STDBY_NO_RST      ((uint32_t)0x80U) /*!< No reset generated when entering in STANDBY */
-#define OB_STDBY_RST         ((uint32_t)0x00U) /*!< Reset generated when entering in STANDBY    */
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP
-  * @{
-  */
-#define OB_IWDG_STOP_FREEZE      ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STOP mode */
-#define OB_IWDG_STOP_ACTIVE      ((uint32_t)0x80000000U) /*!< IWDG counter active in STOP mode */
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY
-  * @{
-  */
-#define OB_IWDG_STDBY_FREEZE      ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STANDBY mode */
-#define OB_IWDG_STDBY_ACTIVE      ((uint32_t)0x40000000U) /*!< IWDG counter active in STANDBY mode */
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level
-  * @{
-  */
-#define OB_BOR_LEVEL3          ((uint32_t)0x00U)  /*!< Supply voltage ranges from 2.70 to 3.60 V */
-#define OB_BOR_LEVEL2          ((uint32_t)0x04U)  /*!< Supply voltage ranges from 2.40 to 2.70 V */
-#define OB_BOR_LEVEL1          ((uint32_t)0x08U)  /*!< Supply voltage ranges from 2.10 to 2.40 V */
-#define OB_BOR_OFF             ((uint32_t)0x0CU)  /*!< Supply voltage ranges from 1.62 to 2.10 V */
-/**
-  * @}
-  */
-
-#if defined (FLASH_OPTCR_nDBOOT)
-/** @defgroup FLASHEx_Option_Bytes_nDBOOT FLASH Option Bytes nDBOOT
-  * @{
-  */
-#define OB_DUAL_BOOT_DISABLE      ((uint32_t)0x10000000U) /* !< Dual Boot disable. Boot according to boot address option */
-#define OB_DUAL_BOOT_ENABLE       ((uint32_t)0x00000000U) /* !< Dual Boot enable. Boot always from system memory if boot address in flash
-                                                              (Dual bank Boot mode), or RAM if Boot address option in RAM    */
-/**
-  * @}
-  */
-#endif /* FLASH_OPTCR_nDBOOT */
-
-#if defined (FLASH_OPTCR_nDBANK)
-/** @defgroup FLASHEx_Option_Bytes_nDBank FLASH Single Bank or Dual Bank
-  * @{
-  */
-#define OB_NDBANK_SINGLE_BANK      ((uint32_t)0x20000000U) /*!< NDBANK bit is set : Single Bank mode */
-#define OB_NDBANK_DUAL_BANK        ((uint32_t)0x00000000U) /*!< NDBANK bit is reset : Dual Bank mode */
-/**
-  * @}
-  */
-#endif /* FLASH_OPTCR_nDBANK */
-
-/** @defgroup FLASHEx_Boot_Address FLASH Boot Address
-  * @{
-  */
-#define OB_BOOTADDR_ITCM_RAM         ((uint32_t)0x0000U)  /*!< Boot from ITCM RAM (0x00000000)                 */
-#define OB_BOOTADDR_SYSTEM           ((uint32_t)0x0040U)  /*!< Boot from System memory bootloader (0x00100000) */
-#define OB_BOOTADDR_ITCM_FLASH       ((uint32_t)0x0080U)  /*!< Boot from Flash on ITCM interface (0x00200000)  */
-#define OB_BOOTADDR_AXIM_FLASH       ((uint32_t)0x2000U)  /*!< Boot from Flash on AXIM interface (0x08000000)  */
-#define OB_BOOTADDR_DTCM_RAM         ((uint32_t)0x8000U)  /*!< Boot from DTCM RAM (0x20000000)                 */
-#define OB_BOOTADDR_SRAM1            ((uint32_t)0x8004U)  /*!< Boot from SRAM1 (0x20010000)                    */
-#define OB_BOOTADDR_SRAM2            ((uint32_t)0x8013U)  /*!< Boot from SRAM2 (0x2004C000)                    */
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Latency FLASH Latency
-  * @{
-  */
-#define FLASH_LATENCY_0                FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero Latency cycle      */
-#define FLASH_LATENCY_1                FLASH_ACR_LATENCY_1WS   /*!< FLASH One Latency cycle       */
-#define FLASH_LATENCY_2                FLASH_ACR_LATENCY_2WS   /*!< FLASH Two Latency cycles      */
-#define FLASH_LATENCY_3                FLASH_ACR_LATENCY_3WS   /*!< FLASH Three Latency cycles    */
-#define FLASH_LATENCY_4                FLASH_ACR_LATENCY_4WS   /*!< FLASH Four Latency cycles     */
-#define FLASH_LATENCY_5                FLASH_ACR_LATENCY_5WS   /*!< FLASH Five Latency cycles     */
-#define FLASH_LATENCY_6                FLASH_ACR_LATENCY_6WS   /*!< FLASH Six Latency cycles      */
-#define FLASH_LATENCY_7                FLASH_ACR_LATENCY_7WS   /*!< FLASH Seven Latency cycles    */
-#define FLASH_LATENCY_8                FLASH_ACR_LATENCY_8WS   /*!< FLASH Eight Latency cycles    */
-#define FLASH_LATENCY_9                FLASH_ACR_LATENCY_9WS   /*!< FLASH Nine Latency cycles     */
-#define FLASH_LATENCY_10               FLASH_ACR_LATENCY_10WS  /*!< FLASH Ten Latency cycles      */
-#define FLASH_LATENCY_11               FLASH_ACR_LATENCY_11WS  /*!< FLASH Eleven Latency cycles   */
-#define FLASH_LATENCY_12               FLASH_ACR_LATENCY_12WS  /*!< FLASH Twelve Latency cycles   */
-#define FLASH_LATENCY_13               FLASH_ACR_LATENCY_13WS  /*!< FLASH Thirteen Latency cycles */
-#define FLASH_LATENCY_14               FLASH_ACR_LATENCY_14WS  /*!< FLASH Fourteen Latency cycles */
-#define FLASH_LATENCY_15               FLASH_ACR_LATENCY_15WS  /*!< FLASH Fifteen Latency cycles  */
-/**
-  * @}
-  */
-
-#if defined (FLASH_OPTCR_nDBANK)
-/** @defgroup FLASHEx_Banks FLASH Banks
-  * @{
-  */
-#define FLASH_BANK_1                       ((uint32_t)0x01U)                          /*!< Bank 1   */
-#define FLASH_BANK_2                       ((uint32_t)0x02U)                          /*!< Bank 2   */
-#define FLASH_BANK_BOTH                    ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2)) /*!< Bank1 and Bank2  */
-/**
-  * @}
-  */
-#endif /* FLASH_OPTCR_nDBANK */
-
-/** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit
-  * @{
-  */
-#if defined (FLASH_OPTCR_nDBANK)
-#define FLASH_MER_BIT     (FLASH_CR_MER1 | FLASH_CR_MER2) /*!< 2 MER bits */
-#else
-#define FLASH_MER_BIT     (FLASH_CR_MER) /*!< only 1 MER bit */
-#endif /* FLASH_OPTCR_nDBANK */
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_Sectors FLASH Sectors
-  * @{
-  */
-#if (FLASH_SECTOR_TOTAL == 24)
-#define FLASH_SECTOR_8     ((uint32_t)8U)  /*!< Sector Number 8   */
-#define FLASH_SECTOR_9     ((uint32_t)9U)  /*!< Sector Number 9   */
-#define FLASH_SECTOR_10    ((uint32_t)10U) /*!< Sector Number 10  */
-#define FLASH_SECTOR_11    ((uint32_t)11U) /*!< Sector Number 11  */
-#define FLASH_SECTOR_12    ((uint32_t)12U) /*!< Sector Number 12  */
-#define FLASH_SECTOR_13    ((uint32_t)13U) /*!< Sector Number 13  */
-#define FLASH_SECTOR_14    ((uint32_t)14U) /*!< Sector Number 14  */
-#define FLASH_SECTOR_15    ((uint32_t)15U) /*!< Sector Number 15  */
-#define FLASH_SECTOR_16    ((uint32_t)16U) /*!< Sector Number 16  */
-#define FLASH_SECTOR_17    ((uint32_t)17U) /*!< Sector Number 17  */
-#define FLASH_SECTOR_18    ((uint32_t)18U) /*!< Sector Number 18  */
-#define FLASH_SECTOR_19    ((uint32_t)19U) /*!< Sector Number 19  */
-#define FLASH_SECTOR_20    ((uint32_t)20U) /*!< Sector Number 20  */
-#define FLASH_SECTOR_21    ((uint32_t)21U) /*!< Sector Number 21  */
-#define FLASH_SECTOR_22    ((uint32_t)22U) /*!< Sector Number 22  */
-#define FLASH_SECTOR_23    ((uint32_t)23U) /*!< Sector Number 23  */
-#endif /* FLASH_SECTOR_TOTAL == 24 */
-/**
-  * @}
-  */
-
-#if (FLASH_SECTOR_TOTAL == 24)
-/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
-  * @note For Single Bank mode, use OB_WRP_SECTOR_x defines: In fact, in FLASH_OPTCR register,
-  *       nWRP[11:0] bits contain the value of the write-protection option bytes for sectors 0 to 11.
-  *       For Dual Bank mode, use OB_WRP_DB_SECTOR_x defines: In fact, in FLASH_OPTCR register,
-  *       nWRP[11:0] bits are divided on two groups, one group dedicated for bank 1 and
-  *       a second one dedicated for bank 2 (nWRP[i] activates Write protection on sector 2*i and 2*i+1).
-  *       This behavior is applicable only for STM32F76xxx / STM32F77xxx devices.
-  * @{
-  */
-/* Single Bank Sectors */
-#define OB_WRP_SECTOR_0       ((uint32_t)0x00010000U) /*!< Write protection of Single Bank Sector0   */
-#define OB_WRP_SECTOR_1       ((uint32_t)0x00020000U) /*!< Write protection of Single Bank Sector1   */
-#define OB_WRP_SECTOR_2       ((uint32_t)0x00040000U) /*!< Write protection of Single Bank Sector2   */
-#define OB_WRP_SECTOR_3       ((uint32_t)0x00080000U) /*!< Write protection of Single Bank Sector3   */
-#define OB_WRP_SECTOR_4       ((uint32_t)0x00100000U) /*!< Write protection of Single Bank Sector4   */
-#define OB_WRP_SECTOR_5       ((uint32_t)0x00200000U) /*!< Write protection of Single Bank Sector5   */
-#define OB_WRP_SECTOR_6       ((uint32_t)0x00400000U) /*!< Write protection of Single Bank Sector6   */
-#define OB_WRP_SECTOR_7       ((uint32_t)0x00800000U) /*!< Write protection of Single Bank Sector7   */
-#define OB_WRP_SECTOR_8       ((uint32_t)0x01000000U) /*!< Write protection of Single Bank Sector8   */
-#define OB_WRP_SECTOR_9       ((uint32_t)0x02000000U) /*!< Write protection of Single Bank Sector9   */
-#define OB_WRP_SECTOR_10      ((uint32_t)0x04000000U) /*!< Write protection of Single Bank Sector10  */
-#define OB_WRP_SECTOR_11      ((uint32_t)0x08000000U) /*!< Write protection of Single Bank Sector11  */
-#define OB_WRP_SECTOR_All     ((uint32_t)0x0FFF0000U) /*!< Write protection of all Sectors for Single Bank Flash */
-
-/* Dual Bank Sectors */
-#define OB_WRP_DB_SECTOR_0    ((uint32_t)0x00010000U) /*!< Write protection of Dual Bank Sector0     */
-#define OB_WRP_DB_SECTOR_1    ((uint32_t)0x00010000U) /*!< Write protection of Dual Bank Sector1     */
-#define OB_WRP_DB_SECTOR_2    ((uint32_t)0x00020000U) /*!< Write protection of Dual Bank Sector2     */
-#define OB_WRP_DB_SECTOR_3    ((uint32_t)0x00020000U) /*!< Write protection of Dual Bank Sector3     */
-#define OB_WRP_DB_SECTOR_4    ((uint32_t)0x00040000U) /*!< Write protection of Dual Bank Sector4     */
-#define OB_WRP_DB_SECTOR_5    ((uint32_t)0x00040000U) /*!< Write protection of Dual Bank Sector5     */
-#define OB_WRP_DB_SECTOR_6    ((uint32_t)0x00080000U) /*!< Write protection of Dual Bank Sector6     */
-#define OB_WRP_DB_SECTOR_7    ((uint32_t)0x00080000U) /*!< Write protection of Dual Bank Sector7     */
-#define OB_WRP_DB_SECTOR_8    ((uint32_t)0x00100000U) /*!< Write protection of Dual Bank Sector8     */
-#define OB_WRP_DB_SECTOR_9    ((uint32_t)0x00100000U) /*!< Write protection of Dual Bank Sector9     */
-#define OB_WRP_DB_SECTOR_10   ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector10    */
-#define OB_WRP_DB_SECTOR_11   ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector11    */
-#define OB_WRP_DB_SECTOR_12   ((uint32_t)0x00400000U) /*!< Write protection of Dual Bank Sector12    */
-#define OB_WRP_DB_SECTOR_13   ((uint32_t)0x00400000U) /*!< Write protection of Dual Bank Sector13    */
-#define OB_WRP_DB_SECTOR_14   ((uint32_t)0x00800000U) /*!< Write protection of Dual Bank Sector14    */
-#define OB_WRP_DB_SECTOR_15   ((uint32_t)0x00800000U) /*!< Write protection of Dual Bank Sector15    */
-#define OB_WRP_DB_SECTOR_16   ((uint32_t)0x01000000U) /*!< Write protection of Dual Bank Sector16    */
-#define OB_WRP_DB_SECTOR_17   ((uint32_t)0x01000000U) /*!< Write protection of Dual Bank Sector17    */
-#define OB_WRP_DB_SECTOR_18   ((uint32_t)0x02000000U) /*!< Write protection of Dual Bank Sector18    */
-#define OB_WRP_DB_SECTOR_19   ((uint32_t)0x02000000U) /*!< Write protection of Dual Bank Sector19    */
-#define OB_WRP_DB_SECTOR_20   ((uint32_t)0x04000000U) /*!< Write protection of Dual Bank Sector20    */
-#define OB_WRP_DB_SECTOR_21   ((uint32_t)0x04000000U) /*!< Write protection of Dual Bank Sector21    */
-#define OB_WRP_DB_SECTOR_22   ((uint32_t)0x08000000U) /*!< Write protection of Dual Bank Sector22    */
-#define OB_WRP_DB_SECTOR_23   ((uint32_t)0x08000000U) /*!< Write protection of Dual Bank Sector23    */
-#define OB_WRP_DB_SECTOR_All  ((uint32_t)0x0FFF0000U) /*!< Write protection of all Sectors for Dual Bank Flash */
-/**
-  * @}
-  */
-#endif /* FLASH_SECTOR_TOTAL == 24 */
-
-#if (FLASH_SECTOR_TOTAL == 8)
-/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
-  * @{
-  */
-#define OB_WRP_SECTOR_0       ((uint32_t)0x00010000U) /*!< Write protection of Sector0     */
-#define OB_WRP_SECTOR_1       ((uint32_t)0x00020000U) /*!< Write protection of Sector1     */
-#define OB_WRP_SECTOR_2       ((uint32_t)0x00040000U) /*!< Write protection of Sector2     */
-#define OB_WRP_SECTOR_3       ((uint32_t)0x00080000U) /*!< Write protection of Sector3     */
-#define OB_WRP_SECTOR_4       ((uint32_t)0x00100000U) /*!< Write protection of Sector4     */
-#define OB_WRP_SECTOR_5       ((uint32_t)0x00200000U) /*!< Write protection of Sector5     */
-#define OB_WRP_SECTOR_6       ((uint32_t)0x00400000U) /*!< Write protection of Sector6     */
-#define OB_WRP_SECTOR_7       ((uint32_t)0x00800000U) /*!< Write protection of Sector7     */
-#define OB_WRP_SECTOR_All     ((uint32_t)0x00FF0000U) /*!< Write protection of all Sectors */
-/**
-  * @}
-  */
-#endif /* FLASH_SECTOR_TOTAL == 8 */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
-  * @{
-  */
-/**
-  * @brief  Calculate the FLASH Boot Base Adress (BOOT_ADD0 or BOOT_ADD1)
-  * @note   Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14].
-  * @param  __ADDRESS__: FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB)
-  * @retval The FLASH Boot Base Adress
-  */
-#define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14)
- /**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup FLASHEx_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup FLASHEx_Exported_Functions_Group1
-  * @{
-  */
-/* Extension Program operation functions  *************************************/
-HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);
-HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
-HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
-void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup FLASHEx_Private_Macros FLASH Private Macros
-  * @{
-  */
-
-/** @defgroup FLASHEx_IS_FLASH_Definitions FLASH Private macros to check input parameters
-  * @{
-  */
-
-#define IS_FLASH_TYPEERASE(VALUE)(((VALUE) == FLASH_TYPEERASE_SECTORS) || \
-                                  ((VALUE) == FLASH_TYPEERASE_MASSERASE))
-
-#define IS_VOLTAGERANGE(RANGE)(((RANGE) == FLASH_VOLTAGE_RANGE_1) || \
-                               ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \
-                               ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \
-                               ((RANGE) == FLASH_VOLTAGE_RANGE_4))
-
-#define IS_WRPSTATE(VALUE)(((VALUE) == OB_WRPSTATE_DISABLE) || \
-                           ((VALUE) == OB_WRPSTATE_ENABLE))
-
-#define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP        | OPTIONBYTE_USER |\
-                                          OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1)))
-
-#define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013)
-
-#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0)   ||\
-                                ((LEVEL) == OB_RDP_LEVEL_1)   ||\
-                                ((LEVEL) == OB_RDP_LEVEL_2))
-
-#define IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))
-
-#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
-
-#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
-
-#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
-
-#define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))
-
-#define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))
-
-#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
-                                ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
-
-#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0)  || \
-                                   ((LATENCY) == FLASH_LATENCY_1)  || \
-                                   ((LATENCY) == FLASH_LATENCY_2)  || \
-                                   ((LATENCY) == FLASH_LATENCY_3)  || \
-                                   ((LATENCY) == FLASH_LATENCY_4)  || \
-                                   ((LATENCY) == FLASH_LATENCY_5)  || \
-                                   ((LATENCY) == FLASH_LATENCY_6)  || \
-                                   ((LATENCY) == FLASH_LATENCY_7)  || \
-                                   ((LATENCY) == FLASH_LATENCY_8)  || \
-                                   ((LATENCY) == FLASH_LATENCY_9)  || \
-                                   ((LATENCY) == FLASH_LATENCY_10) || \
-                                   ((LATENCY) == FLASH_LATENCY_11) || \
-                                   ((LATENCY) == FLASH_LATENCY_12) || \
-                                   ((LATENCY) == FLASH_LATENCY_13) || \
-                                   ((LATENCY) == FLASH_LATENCY_14) || \
-                                   ((LATENCY) == FLASH_LATENCY_15))
-
-#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END))
-
-#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0U) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
-
-#if (FLASH_SECTOR_TOTAL == 8)
-#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
-                                 ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
-                                 ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5)   ||\
-                                 ((SECTOR) == FLASH_SECTOR_6)   || ((SECTOR) == FLASH_SECTOR_7))
-
-#define IS_OB_WRP_SECTOR(SECTOR)  ((((SECTOR) & 0xFF00FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U))
-#endif /* FLASH_SECTOR_TOTAL == 8 */
-
-#if (FLASH_SECTOR_TOTAL == 24)
-#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
-                                 ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
-                                 ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5)   ||\
-                                 ((SECTOR) == FLASH_SECTOR_6)   || ((SECTOR) == FLASH_SECTOR_7)   ||\
-                                 ((SECTOR) == FLASH_SECTOR_8)   || ((SECTOR) == FLASH_SECTOR_9)   ||\
-                                 ((SECTOR) == FLASH_SECTOR_10)  || ((SECTOR) == FLASH_SECTOR_11)  ||\
-                                 ((SECTOR) == FLASH_SECTOR_12)  || ((SECTOR) == FLASH_SECTOR_13)  ||\
-                                 ((SECTOR) == FLASH_SECTOR_14)  || ((SECTOR) == FLASH_SECTOR_15)  ||\
-                                 ((SECTOR) == FLASH_SECTOR_16)  || ((SECTOR) == FLASH_SECTOR_17)  ||\
-                                 ((SECTOR) == FLASH_SECTOR_18)  || ((SECTOR) == FLASH_SECTOR_19)  ||\
-                                 ((SECTOR) == FLASH_SECTOR_20)  || ((SECTOR) == FLASH_SECTOR_21)  ||\
-                                 ((SECTOR) == FLASH_SECTOR_22)  || ((SECTOR) == FLASH_SECTOR_23))
-
-#define IS_OB_WRP_SECTOR(SECTOR)  ((((SECTOR) & 0xF000FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U))
-#endif /* FLASH_SECTOR_TOTAL == 24 */
-
-#if defined (FLASH_OPTCR_nDBANK)
-#define IS_OB_NDBANK(VALUE)        (((VALUE) == OB_NDBANK_SINGLE_BANK) || \
-                                    ((VALUE) == OB_NDBANK_DUAL_BANK))
-
-#define IS_FLASH_BANK(BANK)        (((BANK) == FLASH_BANK_1)  || \
-                                    ((BANK) == FLASH_BANK_2)  || \
-                                    ((BANK) == FLASH_BANK_BOTH))
-#endif /* FLASH_OPTCR_nDBANK */
-
-#if defined (FLASH_OPTCR_nDBOOT)
-#define IS_OB_NDBOOT(VALUE)        (((VALUE) == OB_DUAL_BOOT_DISABLE) || \
-                                    ((VALUE) == OB_DUAL_BOOT_ENABLE))
-#endif /* FLASH_OPTCR_nDBOOT */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup FLASHEx_Private_Functions FLASH Private Functions
-  * @{
-  */
-void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F7xx_HAL_FLASH_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_gpio.h b/stmhal/hal/f7/inc/stm32f7xx_hal_gpio.h
deleted file mode 100644
index ae8d7eafef..0000000000
--- a/stmhal/hal/f7/inc/stm32f7xx_hal_gpio.h
+++ /dev/null
@@ -1,327 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_gpio.h
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   Header file of GPIO HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_GPIO_H
-#define __STM32F7xx_HAL_GPIO_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal_def.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup GPIO
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup GPIO_Exported_Types GPIO Exported Types
-  * @{
-  */
-
-/**
-  * @brief GPIO Init structure definition
-  */
-typedef struct
-{
-  uint32_t Pin;       /*!< Specifies the GPIO pins to be configured.
-                           This parameter can be any value of @ref GPIO_pins_define */
-
-  uint32_t Mode;      /*!< Specifies the operating mode for the selected pins.
-                           This parameter can be a value of @ref GPIO_mode_define */
-
-  uint32_t Pull;      /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
-                           This parameter can be a value of @ref GPIO_pull_define */
-
-  uint32_t Speed;     /*!< Specifies the speed for the selected pins.
-                           This parameter can be a value of @ref GPIO_speed_define */
-
-  uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins.
-                            This parameter can be a value of @ref GPIO_Alternate_function_selection */
-}GPIO_InitTypeDef;
-
-/**
-  * @brief  GPIO Bit SET and Bit RESET enumeration
-  */
-typedef enum
-{
-  GPIO_PIN_RESET = 0,
-  GPIO_PIN_SET
-}GPIO_PinState;
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
-  * @{
-  */
-
-/** @defgroup GPIO_pins_define GPIO pins define
-  * @{
-  */
-#define GPIO_PIN_0                 ((uint16_t)0x0001U)  /* Pin 0 selected    */
-#define GPIO_PIN_1                 ((uint16_t)0x0002U)  /* Pin 1 selected    */
-#define GPIO_PIN_2                 ((uint16_t)0x0004U)  /* Pin 2 selected    */
-#define GPIO_PIN_3                 ((uint16_t)0x0008U)  /* Pin 3 selected    */
-#define GPIO_PIN_4                 ((uint16_t)0x0010U)  /* Pin 4 selected    */
-#define GPIO_PIN_5                 ((uint16_t)0x0020U)  /* Pin 5 selected    */
-#define GPIO_PIN_6                 ((uint16_t)0x0040U)  /* Pin 6 selected    */
-#define GPIO_PIN_7                 ((uint16_t)0x0080U)  /* Pin 7 selected    */
-#define GPIO_PIN_8                 ((uint16_t)0x0100U)  /* Pin 8 selected    */
-#define GPIO_PIN_9                 ((uint16_t)0x0200U)  /* Pin 9 selected    */
-#define GPIO_PIN_10                ((uint16_t)0x0400U)  /* Pin 10 selected   */
-#define GPIO_PIN_11                ((uint16_t)0x0800U)  /* Pin 11 selected   */
-#define GPIO_PIN_12                ((uint16_t)0x1000U)  /* Pin 12 selected   */
-#define GPIO_PIN_13                ((uint16_t)0x2000U)  /* Pin 13 selected   */
-#define GPIO_PIN_14                ((uint16_t)0x4000U)  /* Pin 14 selected   */
-#define GPIO_PIN_15                ((uint16_t)0x8000U)  /* Pin 15 selected   */
-#define GPIO_PIN_All               ((uint16_t)0xFFFFU)  /* All pins selected */
-
-#define GPIO_PIN_MASK              ((uint32_t)0x0000FFFFU) /* PIN mask for assert test */
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_mode_define GPIO mode define
-  * @brief GPIO Configuration Mode
-  *        Elements values convention: 0xX0yz00YZ
-  *           - X  : GPIO mode or EXTI Mode
-  *           - y  : External IT or Event trigger detection
-  *           - z  : IO configuration on External IT or Event
-  *           - Y  : Output type (Push Pull or Open Drain)
-  *           - Z  : IO Direction mode (Input, Output, Alternate or Analog)
-  * @{
-  */
-#define  GPIO_MODE_INPUT                        ((uint32_t)0x00000000U)   /*!< Input Floating Mode                   */
-#define  GPIO_MODE_OUTPUT_PP                    ((uint32_t)0x00000001U)   /*!< Output Push Pull Mode                 */
-#define  GPIO_MODE_OUTPUT_OD                    ((uint32_t)0x00000011U)   /*!< Output Open Drain Mode                */
-#define  GPIO_MODE_AF_PP                        ((uint32_t)0x00000002U)   /*!< Alternate Function Push Pull Mode     */
-#define  GPIO_MODE_AF_OD                        ((uint32_t)0x00000012U)   /*!< Alternate Function Open Drain Mode    */
-
-#define  GPIO_MODE_ANALOG                       ((uint32_t)0x00000003U)   /*!< Analog Mode  */
-
-#define  GPIO_MODE_IT_RISING                    ((uint32_t)0x10110000U)   /*!< External Interrupt Mode with Rising edge trigger detection          */
-#define  GPIO_MODE_IT_FALLING                   ((uint32_t)0x10210000U)   /*!< External Interrupt Mode with Falling edge trigger detection         */
-#define  GPIO_MODE_IT_RISING_FALLING            ((uint32_t)0x10310000U)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
-
-#define  GPIO_MODE_EVT_RISING                   ((uint32_t)0x10120000U)   /*!< External Event Mode with Rising edge trigger detection               */
-#define  GPIO_MODE_EVT_FALLING                  ((uint32_t)0x10220000U)   /*!< External Event Mode with Falling edge trigger detection              */
-#define  GPIO_MODE_EVT_RISING_FALLING           ((uint32_t)0x10320000U)   /*!< External Event Mode with Rising/Falling edge trigger detection       */
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_speed_define  GPIO speed define
-  * @brief GPIO Output Maximum frequency
-  * @{
-  */
-#define  GPIO_SPEED_FREQ_LOW         ((uint32_t)0x00000000U)  /*!< Low speed     */
-#define  GPIO_SPEED_FREQ_MEDIUM      ((uint32_t)0x00000001U)  /*!< Medium speed  */
-#define  GPIO_SPEED_FREQ_HIGH        ((uint32_t)0x00000002U)  /*!< Fast speed    */
-#define  GPIO_SPEED_FREQ_VERY_HIGH   ((uint32_t)0x00000003U)  /*!< High speed    */
-/**
-  * @}
-  */
-
- /** @defgroup GPIO_pull_define GPIO pull define
-   * @brief GPIO Pull-Up or Pull-Down Activation
-   * @{
-   */
-#define  GPIO_NOPULL        ((uint32_t)0x00000000U)   /*!< No Pull-up or Pull-down activation  */
-#define  GPIO_PULLUP        ((uint32_t)0x00000001U)   /*!< Pull-up activation                  */
-#define  GPIO_PULLDOWN      ((uint32_t)0x00000002U)   /*!< Pull-down activation                */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
-  * @{
-  */
-
-/**
-  * @brief  Checks whether the specified EXTI line flag is set or not.
-  * @param  __EXTI_LINE__: specifies the EXTI line flag to check.
-  *         This parameter can be GPIO_PIN_x where x can be(0..15)
-  * @retval The new state of __EXTI_LINE__ (SET or RESET).
-  */
-#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
-
-/**
-  * @brief  Clears the EXTI's line pending flags.
-  * @param  __EXTI_LINE__: specifies the EXTI lines flags to clear.
-  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
-  * @retval None
-  */
-#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
-
-/**
-  * @brief  Checks whether the specified EXTI line is asserted or not.
-  * @param  __EXTI_LINE__: specifies the EXTI line to check.
-  *          This parameter can be GPIO_PIN_x where x can be(0..15)
-  * @retval The new state of __EXTI_LINE__ (SET or RESET).
-  */
-#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
-
-/**
-  * @brief  Clears the EXTI's line pending bits.
-  * @param  __EXTI_LINE__: specifies the EXTI lines to clear.
-  *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
-  * @retval None
-  */
-#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
-
-/**
-  * @brief  Generates a Software interrupt on selected EXTI line.
-  * @param  __EXTI_LINE__: specifies the EXTI line to check.
-  *          This parameter can be GPIO_PIN_x where x can be(0..15)
-  * @retval None
-  */
-#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
-/**
-  * @}
-  */
-
-/* Include GPIO HAL Extension module */
-#include "stm32f7xx_hal_gpio_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup GPIO_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup GPIO_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization and de-initialization functions *****************************/
-void  HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init);
-void  HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);
-/**
-  * @}
-  */
-
-/** @addtogroup GPIO_Exported_Functions_Group2
-  * @{
-  */
-/* IO operation functions *****************************************************/
-GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
-void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
-void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup GPIO_Private_Constants GPIO Private Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup GPIO_Private_Macros GPIO Private Macros
-  * @{
-  */
-#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
-#define IS_GPIO_PIN(__PIN__)        ((((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00))
-#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT)              ||\
-                            ((MODE) == GPIO_MODE_OUTPUT_PP)          ||\
-                            ((MODE) == GPIO_MODE_OUTPUT_OD)          ||\
-                            ((MODE) == GPIO_MODE_AF_PP)              ||\
-                            ((MODE) == GPIO_MODE_AF_OD)              ||\
-                            ((MODE) == GPIO_MODE_IT_RISING)          ||\
-                            ((MODE) == GPIO_MODE_IT_FALLING)         ||\
-                            ((MODE) == GPIO_MODE_IT_RISING_FALLING)  ||\
-                            ((MODE) == GPIO_MODE_EVT_RISING)         ||\
-                            ((MODE) == GPIO_MODE_EVT_FALLING)        ||\
-                            ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
-                            ((MODE) == GPIO_MODE_ANALOG))
-#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_LOW)  || ((SPEED) == GPIO_SPEED_MEDIUM) || \
-                              ((SPEED) == GPIO_SPEED_FAST) || ((SPEED) == GPIO_SPEED_HIGH))
-#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
-                            ((PULL) == GPIO_PULLDOWN))
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup GPIO_Private_Functions GPIO Private Functions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F7xx_HAL_GPIO_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_gpio_ex.h b/stmhal/hal/f7/inc/stm32f7xx_hal_gpio_ex.h
deleted file mode 100644
index 474c24ff71..0000000000
--- a/stmhal/hal/f7/inc/stm32f7xx_hal_gpio_ex.h
+++ /dev/null
@@ -1,522 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_gpio_ex.h
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   Header file of GPIO HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_GPIO_EX_H
-#define __STM32F7xx_HAL_GPIO_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal_def.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup GPIOEx GPIOEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants
-  * @{
-  */
-
-/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection
-  * @{
-  */
-/*--------------- STM32F74xxx/STM32F75xxx/STM32F76xxx/STM32F77xxx -------------*/
-#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) ||\
-    defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-/**
-  * @brief   AF 0 selection
-  */
-#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */
-#define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
-#define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
-#define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */
-
-/**
-  * @brief   AF 1 selection
-  */
-#define GPIO_AF1_TIM1          ((uint8_t)0x01U)  /* TIM1 Alternate Function mapping */
-#define GPIO_AF1_TIM2          ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */
-#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
-#define GPIO_AF1_UART5         ((uint8_t)0x01U)  /* UART5 Alternate Function mapping */
-#define GPIO_AF1_I2C4          ((uint8_t)0x01U)  /* I2C4 Alternate Function mapping  */
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
-/**
-  * @brief   AF 2 selection
-  */
-#define GPIO_AF2_TIM3          ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4          ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM5          ((uint8_t)0x02U)  /* TIM5 Alternate Function mapping */
-
-/**
-  * @brief   AF 3 selection
-  */
-#define GPIO_AF3_TIM8          ((uint8_t)0x03U)  /* TIM8 Alternate Function mapping  */
-#define GPIO_AF3_TIM9          ((uint8_t)0x03U)  /* TIM9 Alternate Function mapping  */
-#define GPIO_AF3_TIM10         ((uint8_t)0x03U)  /* TIM10 Alternate Function mapping */
-#define GPIO_AF3_TIM11         ((uint8_t)0x03U)  /* TIM11 Alternate Function mapping */
-#define GPIO_AF3_LPTIM1        ((uint8_t)0x03U)  /* LPTIM1 Alternate Function mapping */
-#define GPIO_AF3_CEC           ((uint8_t)0x03U)  /* CEC Alternate Function mapping */
-#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
-#define GPIO_AF3_DFSDM1         ((uint8_t)0x03U)  /* DFSDM1 Alternate Function mapping */
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-/**
-  * @brief   AF 4 selection
-  */
-#define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */
-#define GPIO_AF4_I2C3          ((uint8_t)0x04U)  /* I2C3 Alternate Function mapping */
-#define GPIO_AF4_I2C4          ((uint8_t)0x04U)  /* I2C4 Alternate Function mapping */
-#define GPIO_AF4_CEC           ((uint8_t)0x04U)  /* CEC Alternate Function mapping */
-#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
-#define GPIO_AF4_USART1        ((uint8_t)0x04)  /* USART1 Alternate Function mapping */
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
-/**
-  * @brief   AF 5 selection
-  */
-#define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1 Alternate Function mapping        */
-#define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping   */
-#define GPIO_AF5_SPI3          ((uint8_t)0x05U)  /* SPI3/I2S3 Alternate Function mapping   */
-#define GPIO_AF5_SPI4          ((uint8_t)0x05U)  /* SPI4 Alternate Function mapping        */
-#define GPIO_AF5_SPI5          ((uint8_t)0x05U)  /* SPI5 Alternate Function mapping        */
-#define GPIO_AF5_SPI6          ((uint8_t)0x05U)  /* SPI6 Alternate Function mapping        */
-
-/**
-  * @brief   AF 6 selection
-  */
-#define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping  */
-#define GPIO_AF6_SAI1          ((uint8_t)0x06U)  /* SAI1 Alternate Function mapping       */
-#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
-#define GPIO_AF6_UART4         ((uint8_t)0x06U)   /* UART4 Alternate Function mapping     */
-#define GPIO_AF6_DFSDM1        ((uint8_t)0x06U)  /* DFSDM1 Alternate Function mapping     */
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
-/**
-  * @brief   AF 7 selection
-  */
-#define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping     */
-#define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping     */
-#define GPIO_AF7_USART3        ((uint8_t)0x07U)  /* USART3 Alternate Function mapping     */
-#define GPIO_AF7_UART5         ((uint8_t)0x07U)  /* UART5 Alternate Function mapping      */
-#define GPIO_AF7_SPDIFRX       ((uint8_t)0x07U)  /* SPDIF-RX Alternate Function mapping   */
-#define GPIO_AF7_SPI2          ((uint8_t)0x07U)  /* SPI2 Alternate Function mapping       */
-#define GPIO_AF7_SPI3          ((uint8_t)0x07U)  /* SPI3 Alternate Function mapping       */
-#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
-#define GPIO_AF7_SPI6          ((uint8_t)0x07U)  /* SPI6 Alternate Function mapping       */
-#define GPIO_AF7_DFSDM1         ((uint8_t)0x07U) /* DFSDM1 Alternate Function mapping      */
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
-/**
-  * @brief   AF 8 selection
-  */
-#define GPIO_AF8_UART4         ((uint8_t)0x08U)  /* UART4 Alternate Function mapping  */
-#define GPIO_AF8_UART5         ((uint8_t)0x08U)  /* UART5 Alternate Function mapping  */
-#define GPIO_AF8_USART6        ((uint8_t)0x08U)  /* USART6 Alternate Function mapping */
-#define GPIO_AF8_UART7         ((uint8_t)0x08U)  /* UART7 Alternate Function mapping  */
-#define GPIO_AF8_UART8         ((uint8_t)0x08U)  /* UART8 Alternate Function mapping  */
-#define GPIO_AF8_SPDIFRX       ((uint8_t)0x08U)  /* SPIDIF-RX Alternate Function mapping */
-#define GPIO_AF8_SAI2          ((uint8_t)0x08U)  /* SAI2 Alternate Function mapping   */
-#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
-#define GPIO_AF8_SPI6          ((uint8_t)0x08U)  /* SPI6 Alternate Function mapping   */
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
-
-/**
-  * @brief   AF 9 selection
-  */
-#define GPIO_AF9_CAN1          ((uint8_t)0x09U)  /* CAN1 Alternate Function mapping    */
-#define GPIO_AF9_CAN2          ((uint8_t)0x09U)  /* CAN2 Alternate Function mapping    */
-#define GPIO_AF9_TIM12         ((uint8_t)0x09U)  /* TIM12 Alternate Function mapping   */
-#define GPIO_AF9_TIM13         ((uint8_t)0x09U)  /* TIM13 Alternate Function mapping   */
-#define GPIO_AF9_TIM14         ((uint8_t)0x09U)  /* TIM14 Alternate Function mapping   */
-#define GPIO_AF9_QUADSPI       ((uint8_t)0x09U)  /* QUADSPI Alternate Function mapping */
-#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
-#define GPIO_AF9_LTDC          ((uint8_t)0x09U)  /* LCD-TFT Alternate Function mapping */
-#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F765xx) || defined(STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
-#define GPIO_AF9_FMC           ((uint8_t)0x09U)   /* FMC Alternate Function mapping     */
-#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-/**
-  * @brief   AF 10 selection
-  */
-#define GPIO_AF10_OTG_FS        ((uint8_t)0xAU)  /* OTG_FS Alternate Function mapping */
-#define GPIO_AF10_OTG_HS        ((uint8_t)0xAU)  /* OTG_HS Alternate Function mapping */
-#define GPIO_AF10_QUADSPI       ((uint8_t)0xAU)  /* QUADSPI Alternate Function mapping */
-#define GPIO_AF10_SAI2          ((uint8_t)0xAU)  /* SAI2 Alternate Function mapping */
-#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
-#define GPIO_AF10_DFSDM1         ((uint8_t)0x0AU)  /* DFSDM1 Alternate Function mapping  */
-#define GPIO_AF10_SDMMC2         ((uint8_t)0x0AU)  /* SDMMC2 Alternate Function mapping */
-#define GPIO_AF10_LTDC           ((uint8_t)0x0AU)  /* LCD-TFT Alternate Function mapping */
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
-/**
-  * @brief   AF 11 selection
-  */
-#define GPIO_AF11_ETH           ((uint8_t)0x0BU)  /* ETHERNET Alternate Function mapping */
-#if defined(STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define GPIO_AF11_CAN3          ((uint8_t)0x0BU)  /* CAN3 Alternate Function mapping     */
-#define GPIO_AF11_SDMMC2        ((uint8_t)0x0BU)  /* SDMMC2 Alternate Function mapping   */
-#define GPIO_AF11_I2C4          ((uint8_t)0x0BU)  /* I2C4 Alternate Function mapping     */
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
-/**
-  * @brief   AF 12 selection
-  */
-#define GPIO_AF12_FMC           ((uint8_t)0xCU)  /* FMC Alternate Function mapping                      */
-#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0xCU)  /* OTG HS configured in FS, Alternate Function mapping */
-#define GPIO_AF12_SDMMC1        ((uint8_t)0xCU)  /* SDMMC1 Alternate Function mapping                   */
-#if defined(STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define GPIO_AF12_MDIOS        ((uint8_t)0xCU)  /* SDMMC1 Alternate Function mapping                    */
-#define GPIO_AF12_UART7        ((uint8_t)0xCU)  /* UART7 Alternate Function mapping                     */
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
-/**
-  * @brief   AF 13 selection
-  */
-#define GPIO_AF13_DCMI          ((uint8_t)0x0DU)  /* DCMI Alternate Function mapping */
-#if defined (STM32F769xx) || defined (STM32F779xx)
-#define GPIO_AF13_DSI           ((uint8_t)0x0DU)  /* DSI Alternate Function mapping  */
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
-#define GPIO_AF13_LTDC          ((uint8_t)0x0DU)  /* LTDC Alternate Function mapping */
-
-/**
-  * @brief   AF 14 selection
-  */
-#define GPIO_AF14_LTDC          ((uint8_t)0x0EU)  /* LCD-TFT Alternate Function mapping */
-#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-/**
-  * @brief   AF 15 selection
-  */
-#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */
-#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-/*----------------------------------------------------------------------------*/
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros
-  * @{
-  */
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions
-  * @{
-  */
-/**
-  * @}
-  */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup GPIOEx_Private_Constants GPIO Private Constants
-  * @{
-  */
-
-/**
-  * @brief   GPIO pin available on the platform
-  */
-/* Defines the available pins per GPIOs */
-#define GPIOA_PIN_AVAILABLE  GPIO_PIN_All
-#define GPIOB_PIN_AVAILABLE  GPIO_PIN_All
-#define GPIOC_PIN_AVAILABLE  GPIO_PIN_All
-#define GPIOD_PIN_AVAILABLE  GPIO_PIN_All
-#define GPIOE_PIN_AVAILABLE  GPIO_PIN_All
-#define GPIOF_PIN_AVAILABLE  GPIO_PIN_All
-#define GPIOG_PIN_AVAILABLE  GPIO_PIN_All
-#define GPIOI_PIN_AVAILABLE  GPIO_PIN_All
-#define GPIOJ_PIN_AVAILABLE  GPIO_PIN_All
-#define GPIOH_PIN_AVAILABLE  GPIO_PIN_All
-#define GPIOK_PIN_AVAILABLE  (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_4 | \
-                              GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup GPIOEx_Private_Macros GPIO Private Macros
-  * @{
-  */
-/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index
-  * @{
-  */
-#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
-    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define GPIO_GET_INDEX(__GPIOx__)   (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
-                                              ((__GPIOx__) == (GPIOB))? 1U :\
-                                              ((__GPIOx__) == (GPIOC))? 2U :\
-                                              ((__GPIOx__) == (GPIOD))? 3U :\
-                                              ((__GPIOx__) == (GPIOE))? 4U :\
-                                              ((__GPIOx__) == (GPIOF))? 5U :\
-                                              ((__GPIOx__) == (GPIOG))? 6U :\
-                                              ((__GPIOx__) == (GPIOH))? 7U :\
-                                              ((__GPIOx__) == (GPIOI))? 8U :\
-                                              ((__GPIOx__) == (GPIOJ))? 9U : 10U)
-#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
-/**
-  * @}
-  */
-
-#define IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__)  \
-           ((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \
-            (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \
-            (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || \
-            (((__INSTANCE__) == GPIOD) && (((__PIN__) & (GPIOD_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOD_PIN_AVAILABLE)) == (GPIOD_PIN_AVAILABLE))) || \
-            (((__INSTANCE__) == GPIOE) && (((__PIN__) & (GPIOE_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOE_PIN_AVAILABLE)) == (GPIOE_PIN_AVAILABLE))) || \
-            (((__INSTANCE__) == GPIOF) && (((__PIN__) & (GPIOF_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOF_PIN_AVAILABLE)) == (GPIOF_PIN_AVAILABLE))) || \
-			(((__INSTANCE__) == GPIOG) && (((__PIN__) & (GPIOG_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOG_PIN_AVAILABLE)) == (GPIOG_PIN_AVAILABLE))) || \
-			(((__INSTANCE__) == GPIOI) && (((__PIN__) & (GPIOI_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOI_PIN_AVAILABLE)) == (GPIOI_PIN_AVAILABLE))) || \
-			(((__INSTANCE__) == GPIOJ) && (((__PIN__) & (GPIOJ_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOJ_PIN_AVAILABLE)) == (GPIOJ_PIN_AVAILABLE))) || \
-			(((__INSTANCE__) == GPIOK) && (((__PIN__) & (GPIOK_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOK_PIN_AVAILABLE)) == (GPIOK_PIN_AVAILABLE))) || \
-			(((__INSTANCE__) == GPIOH) && (((__PIN__) & (GPIOH_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOH_PIN_AVAILABLE)) == (GPIOH_PIN_AVAILABLE))))
-/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function
-  * @{
-  */
-#if defined(STM32F756xx) || defined(STM32F746xx)
-#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF1_TIM1)        || \
-                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
-                          ((AF) == GPIO_AF0_MCO)       || ((AF) == GPIO_AF1_TIM2)       || \
-                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
-                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
-                          ((AF) == GPIO_AF3_TIM9)       || ((AF) == GPIO_AF3_TIM10)      || \
-                          ((AF) == GPIO_AF3_TIM11)      || ((AF) == GPIO_AF3_LPTIM1)     || \
-                          ((AF) == GPIO_AF3_CEC)        || ((AF) == GPIO_AF4_CEC)        || \
-                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
-                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF4_I2C4)       || \
-                          ((AF) == GPIO_AF5_SPI1)       || ((AF) == GPIO_AF5_SPI2)       || \
-                          ((AF) == GPIO_AF5_SPI3)       || ((AF) == GPIO_AF5_SPI4)       || \
-                          ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \
-                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF6_SAI1)       || \
-                          ((AF) == GPIO_AF7_SPI3)       || ((AF) == GPIO_AF7_SPI2)        || \
-                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)      || \
-                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF7_UART5)       || \
-                          ((AF) == GPIO_AF7_SPDIFRX)    || ((AF) == GPIO_AF8_SPDIFRX)     || \
-                          ((AF) == GPIO_AF8_SAI2)       || ((AF) == GPIO_AF8_USART6)      || \
-                          ((AF) == GPIO_AF8_UART4)      || ((AF) == GPIO_AF8_UART5)       || \
-                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)       || \
-                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)        || \
-                          ((AF) == GPIO_AF9_TIM12)      || ((AF) == GPIO_AF9_TIM12)      || \
-                          ((AF) == GPIO_AF9_TIM14)      || ((AF) == GPIO_AF9_QUADSPI)    || \
-                          ((AF) == GPIO_AF9_LTDC)       || ((AF) == GPIO_AF10_OTG_FS)    || \
-                          ((AF) == GPIO_AF10_OTG_HS)    || ((AF) == GPIO_AF10_SAI2)      || \
-                          ((AF) == GPIO_AF10_QUADSPI)   || ((AF) == GPIO_AF11_ETH)       || \
-                          ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1)     || \
-                          ((AF) == GPIO_AF12_FMC)       || ((AF) == GPIO_AF15_EVENTOUT)  || \
-                          ((AF) == GPIO_AF13_DCMI)      || ((AF) == GPIO_AF14_LTDC))
-#elif defined(STM32F745xx)
-#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF1_TIM1)       || \
-                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
-                          ((AF) == GPIO_AF0_MCO)       || ((AF) == GPIO_AF1_TIM2)        || \
-                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
-                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
-                          ((AF) == GPIO_AF3_TIM9)       || ((AF) == GPIO_AF3_TIM10)      || \
-                          ((AF) == GPIO_AF3_TIM11)      || ((AF) == GPIO_AF3_LPTIM1)     || \
-                          ((AF) == GPIO_AF3_CEC)        || ((AF) == GPIO_AF4_CEC)        || \
-                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
-                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF4_I2C4)       || \
-                          ((AF) == GPIO_AF5_SPI1)       || ((AF) == GPIO_AF5_SPI2)       || \
-                          ((AF) == GPIO_AF5_SPI3)       || ((AF) == GPIO_AF5_SPI4)       || \
-                          ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \
-                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF6_SAI1)       || \
-                          ((AF) == GPIO_AF7_SPI3)       || ((AF) == GPIO_AF7_SPI2)        || \
-                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)      || \
-                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF7_UART5)       || \
-                          ((AF) == GPIO_AF7_SPDIFRX)    || ((AF) == GPIO_AF8_SPDIFRX)     || \
-                          ((AF) == GPIO_AF8_SAI2)       || ((AF) == GPIO_AF8_USART6)      || \
-                          ((AF) == GPIO_AF8_UART4)      || ((AF) == GPIO_AF8_UART5)       || \
-                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)       || \
-                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)        || \
-                          ((AF) == GPIO_AF9_TIM12)      || ((AF) == GPIO_AF9_TIM12)      || \
-                          ((AF) == GPIO_AF9_TIM14)      || ((AF) == GPIO_AF9_QUADSPI)    || \
-                          ((AF) == GPIO_AF13_DCMI)      || ((AF) == GPIO_AF10_OTG_FS)    || \
-                          ((AF) == GPIO_AF10_OTG_HS)    || ((AF) == GPIO_AF10_SAI2)      || \
-                          ((AF) == GPIO_AF10_QUADSPI)   || ((AF) == GPIO_AF11_ETH)       || \
-                          ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1)    || \
-                          ((AF) == GPIO_AF12_FMC)       || ((AF) == GPIO_AF15_EVENTOUT))
-#elif defined(STM32F767xx) || defined(STM32F777xx)
-#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF1_TIM1)        || \
-                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
-                          ((AF) == GPIO_AF0_MCO)       || ((AF) == GPIO_AF1_TIM2)       || \
-                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
-                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
-                          ((AF) == GPIO_AF3_TIM9)       || ((AF) == GPIO_AF3_TIM10)      || \
-                          ((AF) == GPIO_AF3_TIM11)      || ((AF) == GPIO_AF3_LPTIM1)     || \
-                          ((AF) == GPIO_AF3_CEC)        || ((AF) == GPIO_AF4_CEC)        || \
-                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
-                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF4_I2C4)       || \
-                          ((AF) == GPIO_AF5_SPI1)       || ((AF) == GPIO_AF5_SPI2)       || \
-                          ((AF) == GPIO_AF5_SPI3)       || ((AF) == GPIO_AF5_SPI4)       || \
-                          ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \
-                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF6_SAI1)       || \
-                          ((AF) == GPIO_AF7_SPI3)       || ((AF) == GPIO_AF7_SPI2)       || \
-                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
-                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF7_UART5)      || \
-                          ((AF) == GPIO_AF7_SPDIFRX)    || ((AF) == GPIO_AF8_SPDIFRX)    || \
-                          ((AF) == GPIO_AF8_SAI2)       || ((AF) == GPIO_AF8_USART6)     || \
-                          ((AF) == GPIO_AF8_UART4)      || ((AF) == GPIO_AF8_UART5)      || \
-                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)      || \
-                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \
-                          ((AF) == GPIO_AF9_TIM12)      || ((AF) == GPIO_AF9_TIM12)      || \
-                          ((AF) == GPIO_AF9_TIM14)      || ((AF) == GPIO_AF9_QUADSPI)    || \
-                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF9_LTDC)       || \
-                          ((AF) == GPIO_AF10_OTG_HS)    || ((AF) == GPIO_AF10_SAI2)      || \
-                          ((AF) == GPIO_AF10_QUADSPI)   || ((AF) == GPIO_AF11_ETH)       || \
-                          ((AF) == GPIO_AF10_SDMMC2)    || ((AF) == GPIO_AF11_SDMMC2)    || \
-                          ((AF) == GPIO_AF11_CAN3)      || ((AF) == GPIO_AF12_OTG_HS_FS) || \
-                          ((AF) == GPIO_AF12_SDMMC1)    || ((AF) == GPIO_AF12_FMC)       || \
-                          ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF13_DCMI)      || \
-		                  ((AF) == GPIO_AF14_LTDC))
-#elif defined(STM32F769xx) || defined(STM32F779xx)
-#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF1_TIM1)        || \
-                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
-                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF1_TIM2)       || \
-                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
-                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
-                          ((AF) == GPIO_AF3_TIM9)       || ((AF) == GPIO_AF3_TIM10)      || \
-                          ((AF) == GPIO_AF3_TIM11)      || ((AF) == GPIO_AF3_LPTIM1)     || \
-                          ((AF) == GPIO_AF3_CEC)        || ((AF) == GPIO_AF4_CEC)        || \
-                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
-                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF4_I2C4)       || \
-                          ((AF) == GPIO_AF5_SPI1)       || ((AF) == GPIO_AF5_SPI2)       || \
-                          ((AF) == GPIO_AF5_SPI3)       || ((AF) == GPIO_AF5_SPI4)       || \
-                          ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \
-                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF6_SAI1)       || \
-                          ((AF) == GPIO_AF7_SPI3)       || ((AF) == GPIO_AF7_SPI2)       || \
-                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
-                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF7_UART5)      || \
-                          ((AF) == GPIO_AF7_SPDIFRX)    || ((AF) == GPIO_AF8_SPDIFRX)    || \
-                          ((AF) == GPIO_AF8_SAI2)       || ((AF) == GPIO_AF8_USART6)     || \
-                          ((AF) == GPIO_AF8_UART4)      || ((AF) == GPIO_AF8_UART5)      || \
-                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)      || \
-                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \
-                          ((AF) == GPIO_AF9_TIM12)      || ((AF) == GPIO_AF9_TIM12)      || \
-                          ((AF) == GPIO_AF9_TIM14)      || ((AF) == GPIO_AF9_QUADSPI)    || \
-                          ((AF) == GPIO_AF9_LTDC)       || ((AF) == GPIO_AF10_OTG_FS)    || \
-                          ((AF) == GPIO_AF10_OTG_HS)    || ((AF) == GPIO_AF10_SAI2)      || \
-                          ((AF) == GPIO_AF10_QUADSPI)   || ((AF) == GPIO_AF11_ETH)       || \
-                          ((AF) == GPIO_AF10_SDMMC2)    || ((AF) == GPIO_AF11_SDMMC2)    || \
-                          ((AF) == GPIO_AF11_CAN3)      || ((AF) == GPIO_AF12_OTG_HS_FS) || \
-                          ((AF) == GPIO_AF12_SDMMC1)    || ((AF) == GPIO_AF12_FMC)       || \
-                          ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF13_DCMI)      || \
-                          ((AF) == GPIO_AF14_LTDC)      || ((AF) == GPIO_AF13_DSI))
-#elif defined(STM32F765xx)
-#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF1_TIM1)        || \
-                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
-                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF1_TIM2)       || \
-                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
-                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
-                          ((AF) == GPIO_AF3_TIM9)       || ((AF) == GPIO_AF3_TIM10)      || \
-                          ((AF) == GPIO_AF3_TIM11)      || ((AF) == GPIO_AF3_LPTIM1)     || \
-                          ((AF) == GPIO_AF3_CEC)        || ((AF) == GPIO_AF4_CEC)        || \
-                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
-                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF4_I2C4)       || \
-                          ((AF) == GPIO_AF5_SPI1)       || ((AF) == GPIO_AF5_SPI2)       || \
-                          ((AF) == GPIO_AF5_SPI3)       || ((AF) == GPIO_AF5_SPI4)       || \
-                          ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \
-                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF6_SAI1)       || \
-                          ((AF) == GPIO_AF7_SPI3)       || ((AF) == GPIO_AF7_SPI2)       || \
-                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
-                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF7_UART5)      || \
-                          ((AF) == GPIO_AF7_SPDIFRX)    || ((AF) == GPIO_AF8_SPDIFRX)    || \
-                          ((AF) == GPIO_AF8_SAI2)       || ((AF) == GPIO_AF8_USART6)     || \
-                          ((AF) == GPIO_AF8_UART4)      || ((AF) == GPIO_AF8_UART5)      || \
-                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)      || \
-                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \
-                          ((AF) == GPIO_AF9_TIM12)      || ((AF) == GPIO_AF9_TIM12)      || \
-                          ((AF) == GPIO_AF9_TIM14)      || ((AF) == GPIO_AF9_QUADSPI)    || \
-                          ((AF) == GPIO_AF10_OTG_HS)    || ((AF) == GPIO_AF10_SAI2)      || \
-                          ((AF) == GPIO_AF10_QUADSPI)   || ((AF) == GPIO_AF11_ETH)       || \
-                          ((AF) == GPIO_AF10_SDMMC2)    || ((AF) == GPIO_AF11_SDMMC2)    || \
-                          ((AF) == GPIO_AF11_CAN3)      || ((AF) == GPIO_AF12_OTG_HS_FS) || \
-                          ((AF) == GPIO_AF12_SDMMC1)    || ((AF) == GPIO_AF12_FMC)       || \
-                          ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF13_DCMI)      || \
-                          ((AF) == GPIO_AF10_OTG_FS))
-#endif /* STM32F756xx || STM32F746xx */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup GPIOEx_Private_Functions GPIO Private Functions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F7xx_HAL_GPIO_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_i2c.h b/stmhal/hal/f7/inc/stm32f7xx_hal_i2c.h
deleted file mode 100644
index 11f56df00b..0000000000
--- a/stmhal/hal/f7/inc/stm32f7xx_hal_i2c.h
+++ /dev/null
@@ -1,712 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_i2c.h
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   Header file of I2C HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_I2C_H
-#define __STM32F7xx_HAL_I2C_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal_def.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup I2C
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup I2C_Exported_Types I2C Exported Types
-  * @{
-  */
-
-/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
-  * @brief  I2C Configuration Structure definition
-  * @{
-  */
-typedef struct
-{
-  uint32_t Timing;              /*!< Specifies the I2C_TIMINGR_register value.
-                                  This parameter calculated by referring to I2C initialization
-                                         section in Reference manual */
-
-  uint32_t OwnAddress1;         /*!< Specifies the first device own address.
-                                  This parameter can be a 7-bit or 10-bit address. */
-
-  uint32_t AddressingMode;      /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
-                                  This parameter can be a value of @ref I2C_ADDRESSING_MODE */
-
-  uint32_t DualAddressMode;     /*!< Specifies if dual addressing mode is selected.
-                                  This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
-
-  uint32_t OwnAddress2;         /*!< Specifies the second device own address if dual addressing mode is selected
-                                  This parameter can be a 7-bit address. */
-
-  uint32_t OwnAddress2Masks;    /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
-                                  This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
-
-  uint32_t GeneralCallMode;     /*!< Specifies if general call mode is selected.
-                                  This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
-
-  uint32_t NoStretchMode;       /*!< Specifies if nostretch mode is selected.
-                                  This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
-
-}I2C_InitTypeDef;
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_state_structure_definition HAL state structure definition
-  * @brief  HAL State structure definition
-  * @note  HAL I2C State value coding follow below described bitmap :
-  *          b7-b6  Error information
-  *             00 : No Error
-  *             01 : Abort (Abort user request on going)
-  *             10 : Timeout
-  *             11 : Error
-  *          b5     IP initilisation status
-  *             0  : Reset (IP not initialized)
-  *             1  : Init done (IP initialized and ready to use. HAL I2C Init function called)
-  *          b4     (not used)
-  *             x  : Should be set to 0
-  *          b3
-  *             0  : Ready or Busy (No Listen mode ongoing)
-  *             1  : Listen (IP in Address Listen Mode)
-  *          b2     Intrinsic process state
-  *             0  : Ready
-  *             1  : Busy (IP busy with some configuration or internal operations)
-  *          b1     Rx state
-  *             0  : Ready (no Rx operation ongoing)
-  *             1  : Busy (Rx operation ongoing)
-  *          b0     Tx state
-  *             0  : Ready (no Tx operation ongoing)
-  *             1  : Busy (Tx operation ongoing)
-  * @{
-  */
-
-typedef enum
-{
-  HAL_I2C_STATE_RESET             = 0x00U,   /*!< Peripheral is not yet Initialized         */
-  HAL_I2C_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use  */
-  HAL_I2C_STATE_BUSY              = 0x24U,   /*!< An internal process is ongoing            */
-  HAL_I2C_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing      */
-  HAL_I2C_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing         */
-  HAL_I2C_STATE_LISTEN            = 0x28U,   /*!< Address Listen Mode is ongoing            */
-  HAL_I2C_STATE_BUSY_TX_LISTEN    = 0x29U,   /*!< Address Listen Mode and Data Transmission
-                                                 process is ongoing                        */
-  HAL_I2C_STATE_BUSY_RX_LISTEN    = 0x2AU,   /*!< Address Listen Mode and Data Reception
-                                                 process is ongoing                        */
-  HAL_I2C_STATE_ABORT             = 0x60,    /*!< Abort user request ongoing                */
-  HAL_I2C_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state                             */
-  HAL_I2C_STATE_ERROR             = 0xE0U    /*!< Error                                     */
-
-}HAL_I2C_StateTypeDef;
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_mode_structure_definition HAL mode structure definition
-  * @brief  HAL Mode structure definition
-  * @note  HAL I2C Mode value coding follow below described bitmap :
-  *          b7     (not used)
-  *             x  : Should be set to 0
-  *          b6
-  *             0  : None
-  *             1  : Memory (HAL I2C communication is in Memory Mode)
-  *          b5
-  *             0  : None
-  *             1  : Slave (HAL I2C communication is in Slave Mode)
-  *          b4
-  *             0  : None
-  *             1  : Master (HAL I2C communication is in Master Mode)
-  *          b3-b2-b1-b0  (not used)
-  *             xxxx : Should be set to 0000
-  * @{
-  */
-typedef enum
-{
-  HAL_I2C_MODE_NONE               = 0x00U,   /*!< No I2C communication on going             */
-  HAL_I2C_MODE_MASTER             = 0x10U,   /*!< I2C communication is in Master Mode       */
-  HAL_I2C_MODE_SLAVE              = 0x20U,   /*!< I2C communication is in Slave Mode        */
-  HAL_I2C_MODE_MEM                = 0x40U    /*!< I2C communication is in Memory Mode       */
-
-}HAL_I2C_ModeTypeDef;
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Error_Code_definition I2C Error Code definition
-  * @brief  I2C Error Code definition
-  * @{
-  */
-#define HAL_I2C_ERROR_NONE      ((uint32_t)0x00000000U)    /*!< No error              */
-#define HAL_I2C_ERROR_BERR      ((uint32_t)0x00000001U)    /*!< BERR error            */
-#define HAL_I2C_ERROR_ARLO      ((uint32_t)0x00000002U)    /*!< ARLO error            */
-#define HAL_I2C_ERROR_AF        ((uint32_t)0x00000004U)    /*!< ACKF error            */
-#define HAL_I2C_ERROR_OVR       ((uint32_t)0x00000008U)    /*!< OVR error             */
-#define HAL_I2C_ERROR_DMA       ((uint32_t)0x00000010U)    /*!< DMA transfer error    */
-#define HAL_I2C_ERROR_TIMEOUT   ((uint32_t)0x00000020U)    /*!< Timeout error         */
-#define HAL_I2C_ERROR_SIZE      ((uint32_t)0x00000040U)    /*!< Size Management error */
-#define HAL_I2C_ERROR_ABORT     ((uint32_t)0x00000080U)    /*!< Abort user request    */
-/**
-  * @}
-  */
-
-/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
-  * @brief  I2C handle Structure definition
-  * @{
-  */
-typedef struct __I2C_HandleTypeDef
-{
-  I2C_TypeDef                *Instance;      /*!< I2C registers base address                */
-
-  I2C_InitTypeDef            Init;           /*!< I2C communication parameters              */
-
-  uint8_t                    *pBuffPtr;      /*!< Pointer to I2C transfer buffer            */
-
-  uint16_t                   XferSize;       /*!< I2C transfer size                         */
-
-  __IO uint16_t              XferCount;      /*!< I2C transfer counter                      */
-
-  __IO uint32_t              XferOptions;    /*!< I2C sequantial transfer options, this parameter can
-                                                  be a value of @ref I2C_XFEROPTIONS */
-
-  __IO uint32_t              PreviousState;  /*!< I2C communication Previous state          */
-
-  HAL_StatusTypeDef (*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */
-
-  DMA_HandleTypeDef          *hdmatx;        /*!< I2C Tx DMA handle parameters              */
-
-  DMA_HandleTypeDef          *hdmarx;        /*!< I2C Rx DMA handle parameters              */
-
-  HAL_LockTypeDef            Lock;           /*!< I2C locking object                        */
-
-  __IO HAL_I2C_StateTypeDef  State;          /*!< I2C communication state                   */
-
-  __IO HAL_I2C_ModeTypeDef   Mode;           /*!< I2C communication mode                    */
-
-  __IO uint32_t              ErrorCode;      /*!< I2C Error code                            */
-
-  __IO uint32_t              AddrEventCount; /*!< I2C Address Event counter                 */
-}I2C_HandleTypeDef;
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup I2C_Exported_Constants I2C Exported Constants
-  * @{
-  */
-
-/** @defgroup I2C_XFEROPTIONS  I2C Sequential Transfer Options
-  * @{
-  */
-#define I2C_FIRST_FRAME                 ((uint32_t)I2C_SOFTEND_MODE)
-#define I2C_FIRST_AND_NEXT_FRAME        ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
-#define I2C_NEXT_FRAME                  ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
-#define I2C_FIRST_AND_LAST_FRAME        ((uint32_t)I2C_AUTOEND_MODE)
-#define I2C_LAST_FRAME                  ((uint32_t)I2C_AUTOEND_MODE)
-/**
-  * @}
-  */
-
-/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
-  * @{
-  */
-#define I2C_ADDRESSINGMODE_7BIT         ((uint32_t)0x00000001U)
-#define I2C_ADDRESSINGMODE_10BIT        ((uint32_t)0x00000002U)
-/**
-  * @}
-  */
-
-/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
-  * @{
-  */
-#define I2C_DUALADDRESS_DISABLE         ((uint32_t)0x00000000U)
-#define I2C_DUALADDRESS_ENABLE          I2C_OAR2_OA2EN
-/**
-  * @}
-  */
-
-/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
-  * @{
-  */
-#define I2C_OA2_NOMASK                  ((uint8_t)0x00U)
-#define I2C_OA2_MASK01                  ((uint8_t)0x01U)
-#define I2C_OA2_MASK02                  ((uint8_t)0x02U)
-#define I2C_OA2_MASK03                  ((uint8_t)0x03U)
-#define I2C_OA2_MASK04                  ((uint8_t)0x04U)
-#define I2C_OA2_MASK05                  ((uint8_t)0x05U)
-#define I2C_OA2_MASK06                  ((uint8_t)0x06U)
-#define I2C_OA2_MASK07                  ((uint8_t)0x07U)
-/**
-  * @}
-  */
-
-/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
-  * @{
-  */
-#define I2C_GENERALCALL_DISABLE         ((uint32_t)0x00000000U)
-#define I2C_GENERALCALL_ENABLE          I2C_CR1_GCEN
-/**
-  * @}
-  */
-
-/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
-  * @{
-  */
-#define I2C_NOSTRETCH_DISABLE           ((uint32_t)0x00000000U)
-#define I2C_NOSTRETCH_ENABLE            I2C_CR1_NOSTRETCH
-/**
-  * @}
-  */
-
-/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
-  * @{
-  */
-#define I2C_MEMADD_SIZE_8BIT            ((uint32_t)0x00000001U)
-#define I2C_MEMADD_SIZE_16BIT           ((uint32_t)0x00000002U)
-/**
-  * @}
-  */
-
-/** @defgroup I2C_XferDirection I2C Transfer Direction
-  * @{
-  */
-#define I2C_DIRECTION_TRANSMIT          ((uint32_t)0x00000000U)
-#define I2C_DIRECTION_RECEIVE           ((uint32_t)0x00000001U)
-/**
-  * @}
-  */
-
-/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
-  * @{
-  */
-#define  I2C_RELOAD_MODE                I2C_CR2_RELOAD
-#define  I2C_AUTOEND_MODE               I2C_CR2_AUTOEND
-#define  I2C_SOFTEND_MODE               ((uint32_t)0x00000000U)
-/**
-  * @}
-  */
-
-/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
-  * @{
-  */
-#define  I2C_NO_STARTSTOP               ((uint32_t)0x00000000U)
-#define  I2C_GENERATE_STOP              I2C_CR2_STOP
-#define  I2C_GENERATE_START_READ        (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
-#define  I2C_GENERATE_START_WRITE       I2C_CR2_START
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
-  * @brief I2C Interrupt definition
-  *        Elements values convention: 0xXXXXXXXX
-  *           - XXXXXXXX  : Interrupt control mask
-  * @{
-  */
-#define I2C_IT_ERRI                     I2C_CR1_ERRIE
-#define I2C_IT_TCI                      I2C_CR1_TCIE
-#define I2C_IT_STOPI                    I2C_CR1_STOPIE
-#define I2C_IT_NACKI                    I2C_CR1_NACKIE
-#define I2C_IT_ADDRI                    I2C_CR1_ADDRIE
-#define I2C_IT_RXI                      I2C_CR1_RXIE
-#define I2C_IT_TXI                      I2C_CR1_TXIE
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Flag_definition I2C Flag definition
-  * @{
-  */
-#define I2C_FLAG_TXE                    I2C_ISR_TXE
-#define I2C_FLAG_TXIS                   I2C_ISR_TXIS
-#define I2C_FLAG_RXNE                   I2C_ISR_RXNE
-#define I2C_FLAG_ADDR                   I2C_ISR_ADDR
-#define I2C_FLAG_AF                     I2C_ISR_NACKF
-#define I2C_FLAG_STOPF                  I2C_ISR_STOPF
-#define I2C_FLAG_TC                     I2C_ISR_TC
-#define I2C_FLAG_TCR                    I2C_ISR_TCR
-#define I2C_FLAG_BERR                   I2C_ISR_BERR
-#define I2C_FLAG_ARLO                   I2C_ISR_ARLO
-#define I2C_FLAG_OVR                    I2C_ISR_OVR
-#define I2C_FLAG_PECERR                 I2C_ISR_PECERR
-#define I2C_FLAG_TIMEOUT                I2C_ISR_TIMEOUT
-#define I2C_FLAG_ALERT                  I2C_ISR_ALERT
-#define I2C_FLAG_BUSY                   I2C_ISR_BUSY
-#define I2C_FLAG_DIR                    I2C_ISR_DIR
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-
-/** @defgroup I2C_Exported_Macros I2C Exported Macros
-  * @{
-  */
-
-/** @brief Reset I2C handle state.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @retval None
-  */
-#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
-
-/** @brief  Enable the specified I2C interrupt.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @param  __INTERRUPT__ specifies the interrupt source to enable.
-  *        This parameter can be one of the following values:
-  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
-  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
-  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
-  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
-  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
-  *            @arg @ref I2C_IT_RXI   RX interrupt enable
-  *            @arg @ref I2C_IT_TXI   TX interrupt enable
-  *
-  * @retval None
-  */
-#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)          ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
-
-/** @brief  Disable the specified I2C interrupt.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @param  __INTERRUPT__ specifies the interrupt source to disable.
-  *        This parameter can be one of the following values:
-  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
-  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
-  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
-  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
-  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
-  *            @arg @ref I2C_IT_RXI   RX interrupt enable
-  *            @arg @ref I2C_IT_TXI   TX interrupt enable
-  *
-  * @retval None
-  */
-#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
-
-/** @brief  Check whether the specified I2C interrupt source is enabled or not.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @param  __INTERRUPT__ specifies the I2C interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
-  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
-  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
-  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
-  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
-  *            @arg @ref I2C_IT_RXI   RX interrupt enable
-  *            @arg @ref I2C_IT_TXI   TX interrupt enable
-  *
-  * @retval The new state of __INTERRUPT__ (SET or RESET).
-  */
-#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)      ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief  Check whether the specified I2C flag is set or not.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @param  __FLAG__ specifies the flag to check.
-  *        This parameter can be one of the following values:
-  *            @arg @ref I2C_FLAG_TXE     Transmit data register empty
-  *            @arg @ref I2C_FLAG_TXIS    Transmit interrupt status
-  *            @arg @ref I2C_FLAG_RXNE    Receive data register not empty
-  *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)
-  *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag
-  *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
-  *            @arg @ref I2C_FLAG_TC      Transfer complete (master mode)
-  *            @arg @ref I2C_FLAG_TCR     Transfer complete reload
-  *            @arg @ref I2C_FLAG_BERR    Bus error
-  *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
-  *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun
-  *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
-  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
-  *            @arg @ref I2C_FLAG_ALERT   SMBus alert
-  *            @arg @ref I2C_FLAG_BUSY    Bus busy
-  *            @arg @ref I2C_FLAG_DIR     Transfer direction (slave mode)
-  *
-  * @retval The new state of __FLAG__ (SET or RESET).
-  */
-#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
-
-/** @brief  Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @param  __FLAG__ specifies the flag to clear.
-  *          This parameter can be any combination of the following values:
-  *            @arg @ref I2C_FLAG_TXE     Transmit data register empty
-  *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)
-  *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag
-  *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
-  *            @arg @ref I2C_FLAG_BERR    Bus error
-  *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
-  *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun
-  *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
-  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
-  *            @arg @ref I2C_FLAG_ALERT   SMBus alert
-  *
-  * @retval None
-  */
-#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
-                                                                                 : ((__HANDLE__)->Instance->ICR = (__FLAG__)))
-
-/** @brief  Enable the specified I2C peripheral.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @retval None
-  */
-#define __HAL_I2C_ENABLE(__HANDLE__)                            (SET_BIT((__HANDLE__)->Instance->CR1,  I2C_CR1_PE))
-
-/** @brief  Disable the specified I2C peripheral.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @retval None
-  */
-#define __HAL_I2C_DISABLE(__HANDLE__)                           (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
-
-/** @brief  Generate a Non-Acknowledge I2C peripheral in Slave mode.
-  * @param  __HANDLE__: specifies the I2C Handle.
-  * @retval None
-  */
-#define __HAL_I2C_GENERATE_NACK(__HANDLE__)                     (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
-/**
-  * @}
-  */
-
-/* Include I2C HAL Extended module */
-#include "stm32f7xx_hal_i2c_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2C_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-/* Initialization and de-initialization functions******************************/
-HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
-/**
-  * @}
-  */
-
-/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
-  * @{
-  */
-/* IO operation functions  ****************************************************/
- /******* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
-
- /******* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-
-HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
-
- /******* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-/**
-  * @}
-  */
-
-/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
- * @{
- */
-/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
-void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
-void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
-/**
-  * @}
-  */
-
-/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
-  * @{
-  */
-/* Peripheral State, Mode and Error functions  *********************************/
-HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
-HAL_I2C_ModeTypeDef  HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
-uint32_t             HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2C_Private_Constants I2C Private Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2C_Private_Macro I2C Private Macros
-  * @{
-  */
-
-#define IS_I2C_ADDRESSING_MODE(MODE)    (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
-                                         ((MODE) == I2C_ADDRESSINGMODE_10BIT))
-
-#define IS_I2C_DUAL_ADDRESS(ADDRESS)    (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
-                                         ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
-
-#define IS_I2C_OWN_ADDRESS2_MASK(MASK)  (((MASK) == I2C_OA2_NOMASK)  || \
-                                         ((MASK) == I2C_OA2_MASK01) || \
-                                         ((MASK) == I2C_OA2_MASK02) || \
-                                         ((MASK) == I2C_OA2_MASK03) || \
-                                         ((MASK) == I2C_OA2_MASK04) || \
-                                         ((MASK) == I2C_OA2_MASK05) || \
-                                         ((MASK) == I2C_OA2_MASK06) || \
-                                         ((MASK) == I2C_OA2_MASK07))
-
-#define IS_I2C_GENERAL_CALL(CALL)       (((CALL) == I2C_GENERALCALL_DISABLE) || \
-                                         ((CALL) == I2C_GENERALCALL_ENABLE))
-
-#define IS_I2C_NO_STRETCH(STRETCH)      (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
-                                         ((STRETCH) == I2C_NOSTRETCH_ENABLE))
-
-#define IS_I2C_MEMADD_SIZE(SIZE)        (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
-                                         ((SIZE) == I2C_MEMADD_SIZE_16BIT))
-
-#define IS_TRANSFER_MODE(MODE)          (((MODE) == I2C_RELOAD_MODE)   || \
-                                         ((MODE) == I2C_AUTOEND_MODE) || \
-                                         ((MODE) == I2C_SOFTEND_MODE))
-
-#define IS_TRANSFER_REQUEST(REQUEST)    (((REQUEST) == I2C_GENERATE_STOP)        || \
-                                         ((REQUEST) == I2C_GENERATE_START_READ)  || \
-                                         ((REQUEST) == I2C_GENERATE_START_WRITE) || \
-                                         ((REQUEST) == I2C_NO_STARTSTOP))
-
-#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)  (((REQUEST) == I2C_FIRST_FRAME)          || \
-                                                   ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
-                                                   ((REQUEST) == I2C_NEXT_FRAME)           || \
-                                                   ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
-                                                   ((REQUEST) == I2C_LAST_FRAME))
-
-#define I2C_RESET_CR2(__HANDLE__)                 ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
-
-#define I2C_GET_ADDR_MATCH(__HANDLE__)            (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16)
-#define I2C_GET_DIR(__HANDLE__)                   (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16)
-#define I2C_GET_STOP_MODE(__HANDLE__)             ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
-#define I2C_GET_OWN_ADDRESS1(__HANDLE__)          ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)
-#define I2C_GET_OWN_ADDRESS2(__HANDLE__)          ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)
-
-#define IS_I2C_OWN_ADDRESS1(ADDRESS1)             ((ADDRESS1) <= (uint32_t)0x000003FF)
-#define IS_I2C_OWN_ADDRESS2(ADDRESS2)             ((ADDRESS2) <= (uint16_t)0x00FF)
-
-#define I2C_MEM_ADD_MSB(__ADDRESS__)              ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))
-#define I2C_MEM_ADD_LSB(__ADDRESS__)              ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
-
-#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
-                                                          (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
-/**
-  * @}
-  */
-
-/* Private Functions ---------------------------------------------------------*/
-/** @defgroup I2C_Private_Functions I2C Private Functions
-  * @{
-  */
-/* Private functions are defined in stm32f7xx_hal_i2c.c file */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F7xx_HAL_I2C_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_i2c_ex.h b/stmhal/hal/f7/inc/stm32f7xx_hal_i2c_ex.h
deleted file mode 100644
index f1e1e7c165..0000000000
--- a/stmhal/hal/f7/inc/stm32f7xx_hal_i2c_ex.h
+++ /dev/null
@@ -1,188 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_i2c_ex.h
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   Header file of I2C HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_I2C_EX_H
-#define __STM32F7xx_HAL_I2C_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal_def.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup I2CEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup I2CEx_Exported_Constants I2CEx Exported Constants
-  * @{
-  */
-
-/** @defgroup I2CEx_Analog_Filter I2CEx Analog Filter
-  * @{
-  */
-#define I2C_ANALOGFILTER_ENABLE        ((uint32_t)0x00000000U)
-#define I2C_ANALOGFILTER_DISABLE       I2C_CR1_ANFOFF
-/**
-  * @}
-  */
-
-/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
-  * @{
-  */
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-
-#define I2C_FASTMODEPLUS_PB6          SYSCFG_PMC_I2C_PB6_FMP
-#define I2C_FASTMODEPLUS_PB7          SYSCFG_PMC_I2C_PB7_FMP
-#define I2C_FASTMODEPLUS_PB8          SYSCFG_PMC_I2C_PB8_FMP
-#define I2C_FASTMODEPLUS_PB9          SYSCFG_PMC_I2C_PB9_FMP
-
-#define I2C_FASTMODEPLUS_I2C1         SYSCFG_PMC_I2C1_FMP
-#define I2C_FASTMODEPLUS_I2C2         SYSCFG_PMC_I2C2_FMP
-#define I2C_FASTMODEPLUS_I2C3         SYSCFG_PMC_I2C3_FMP
-#define I2C_FASTMODEPLUS_I2C4         SYSCFG_PMC_I2C4_FMP
-
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx  */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Peripheral Control methods  ************************************************/
-HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
-HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
-void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2C_Private_Constants I2C Private Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2C_Private_Macro I2C Private Macros
-  * @{
-  */
-#define IS_I2C_ANALOG_FILTER(FILTER)    (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
-                                          ((FILTER) == I2C_ANALOGFILTER_DISABLE))
-
-#define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000FU)
-
-#if defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP) && defined(SYSCFG_PMC_I2C3_FMP) && defined(SYSCFG_PMC_I2C4_FMP)
-#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \
-                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \
-                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \
-                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \
-                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
-                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \
-										 (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || \
-                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C4) == I2C_FASTMODEPLUS_I2C4))
-#elif defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP) && defined(SYSCFG_PMC_I2C3_FMP)
-#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \
-                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \
-                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \
-                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \
-                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
-										 (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \
-                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3))
-#elif defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP)
-#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \
-                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \
-                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \
-                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \
-                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
-                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2))
-#elif defined(SYSCFG_PMC_I2C1_FMP)
-#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \
-                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \
-                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \
-                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \
-                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1))
-#endif /* SYSCFG_PMC_I2C1_FMP && SYSCFG_PMC_I2C2_FMP && SYSCFG_PMC_I2C3_FMP && SYSCFG_PMC_I2C4_FMP */
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-
-/* Private Functions ---------------------------------------------------------*/
-/** @defgroup I2C_Private_Functions I2C Private Functions
-  * @{
-  */
-/* Private functions are defined in stm32f7xx_hal_i2c_ex.c file */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F7xx_HAL_I2C_EX_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_i2s.h b/stmhal/hal/f7/inc/stm32f7xx_hal_i2s.h
deleted file mode 100644
index af492784d4..0000000000
--- a/stmhal/hal/f7/inc/stm32f7xx_hal_i2s.h
+++ /dev/null
@@ -1,483 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_i2s.h
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   Header file of I2S HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_I2S_H
-#define __STM32F7xx_HAL_I2S_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal_def.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup I2S
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup I2S_Exported_Types I2S Exported Types
-  * @{
-  */
-
-/**
-  * @brief I2S Init structure definition
-  */
-typedef struct
-{
-  uint32_t Mode;                /*!< Specifies the I2S operating mode.
-                                     This parameter can be a value of @ref I2S_Mode */
-
-  uint32_t Standard;            /*!< Specifies the standard used for the I2S communication.
-                                     This parameter can be a value of @ref I2S_Standard */
-
-  uint32_t DataFormat;          /*!< Specifies the data format for the I2S communication.
-                                     This parameter can be a value of @ref I2S_Data_Format */
-
-  uint32_t MCLKOutput;          /*!< Specifies whether the I2S MCLK output is enabled or not.
-                                     This parameter can be a value of @ref I2S_MCLK_Output */
-
-  uint32_t AudioFreq;           /*!< Specifies the frequency selected for the I2S communication.
-                                     This parameter can be a value of @ref I2S_Audio_Frequency */
-
-  uint32_t CPOL;                /*!< Specifies the idle state of the I2S clock.
-                                     This parameter can be a value of @ref I2S_Clock_Polarity */
-
-  uint32_t ClockSource;         /*!< Specifies the I2S Clock Source.
-                                     This parameter can be a value of @ref I2S_Clock_Source */
-}I2S_InitTypeDef;
-
-/**
-  * @brief  HAL State structures definition
-  */
-typedef enum
-{
-  HAL_I2S_STATE_RESET      = 0x00U,  /*!< I2S not yet initialized or disabled                */
-  HAL_I2S_STATE_READY      = 0x01U,  /*!< I2S initialized and ready for use                  */
-  HAL_I2S_STATE_BUSY       = 0x02U,  /*!< I2S internal process is ongoing                    */
-  HAL_I2S_STATE_BUSY_TX    = 0x03U,  /*!< Data Transmission process is ongoing               */
-  HAL_I2S_STATE_BUSY_RX    = 0x04U,  /*!< Data Reception process is ongoing                  */
-  HAL_I2S_STATE_BUSY_TX_RX = 0x05U,  /*!< Data Transmission and Reception process is ongoing */
-  HAL_I2S_STATE_TIMEOUT    = 0x06U,  /*!< I2S timeout state                                  */
-  HAL_I2S_STATE_ERROR      = 0x07U   /*!< I2S error state                                    */
-
-}HAL_I2S_StateTypeDef;
-
-/**
-  * @brief I2S handle Structure definition
-  */
-typedef struct
-{
-  SPI_TypeDef                *Instance;    /* I2S registers base address */
-
-  I2S_InitTypeDef            Init;         /* I2S communication parameters */
-
-  uint16_t                   *pTxBuffPtr;  /* Pointer to I2S Tx transfer buffer */
-
-  __IO uint16_t              TxXferSize;   /* I2S Tx transfer size */
-
-  __IO uint16_t              TxXferCount;  /* I2S Tx transfer Counter */
-
-  uint16_t                   *pRxBuffPtr;  /* Pointer to I2S Rx transfer buffer */
-
-  __IO uint16_t              RxXferSize;   /* I2S Rx transfer size */
-
-  __IO uint16_t              RxXferCount;  /* I2S Rx transfer counter
-                                              (This field is initialized at the
-                                               same value as transfer size at the
-                                               beginning of the transfer and
-                                               decremented when a sample is received.
-                                               NbSamplesReceived = RxBufferSize-RxBufferCount) */
-
-  DMA_HandleTypeDef          *hdmatx;      /* I2S Tx DMA handle parameters */
-
-  DMA_HandleTypeDef          *hdmarx;      /* I2S Rx DMA handle parameters */
-
-  __IO HAL_LockTypeDef       Lock;         /* I2S locking object */
-
-  __IO HAL_I2S_StateTypeDef  State;        /* I2S communication state */
-
-  __IO uint32_t  ErrorCode;                /* I2S Error code                 */
-
-}I2S_HandleTypeDef;
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup I2S_Exported_Constants I2S Exported Constants
-  * @{
-  */
-
-/** @defgroup I2S_Error_Defintion I2S_Error_Defintion
-  *@brief     I2S Error Code
-  * @{
-  */
-#define HAL_I2S_ERROR_NONE      ((uint32_t)0x00000000U)  /*!< No error           */
-#define HAL_I2S_ERROR_TIMEOUT   ((uint32_t)0x00000001U)  /*!< Timeout error      */
-#define HAL_I2S_ERROR_OVR       ((uint32_t)0x00000002U)  /*!< OVR error          */
-#define HAL_I2S_ERROR_UDR       ((uint32_t)0x00000004U)  /*!< UDR error          */
-#define HAL_I2S_ERROR_DMA       ((uint32_t)0x00000008U)  /*!< DMA transfer error */
-#define HAL_I2S_ERROR_UNKNOW    ((uint32_t)0x00000010U)  /*!< Unknow Error error */
-
-/**
-  * @}
-  */
-/** @defgroup I2S_Clock_Source I2S Clock Source
-  * @{
-  */
-#define I2S_CLOCK_EXTERNAL                ((uint32_t)0x00000001U)
-#define I2S_CLOCK_PLL                     ((uint32_t)0x00000002U)
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Mode I2S Mode
-  * @{
-  */
-#define I2S_MODE_SLAVE_TX                ((uint32_t)0x00000000U)
-#define I2S_MODE_SLAVE_RX                ((uint32_t)0x00000100U)
-#define I2S_MODE_MASTER_TX               ((uint32_t)0x00000200U)
-#define I2S_MODE_MASTER_RX               ((uint32_t)0x00000300U)
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Standard I2S Standard
-  * @{
-  */
-#define I2S_STANDARD_PHILIPS             ((uint32_t)0x00000000U)
-#define I2S_STANDARD_MSB                 ((uint32_t)0x00000010U)
-#define I2S_STANDARD_LSB                 ((uint32_t)0x00000020U)
-#define I2S_STANDARD_PCM_SHORT           ((uint32_t)0x00000030U)
-#define I2S_STANDARD_PCM_LONG            ((uint32_t)0x000000B0U)
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Data_Format I2S Data Format
-  * @{
-  */
-#define I2S_DATAFORMAT_16B               ((uint32_t)0x00000000U)
-#define I2S_DATAFORMAT_16B_EXTENDED      ((uint32_t)0x00000001U)
-#define I2S_DATAFORMAT_24B               ((uint32_t)0x00000003U)
-#define I2S_DATAFORMAT_32B               ((uint32_t)0x00000005U)
-/**
-  * @}
-  */
-
-/** @defgroup I2S_MCLK_Output I2S Mclk Output
-  * @{
-  */
-#define I2S_MCLKOUTPUT_ENABLE           ((uint32_t)SPI_I2SPR_MCKOE)
-#define I2S_MCLKOUTPUT_DISABLE          ((uint32_t)0x00000000U)
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
-  * @{
-  */
-#define I2S_AUDIOFREQ_192K               ((uint32_t)192000U)
-#define I2S_AUDIOFREQ_96K                ((uint32_t)96000U)
-#define I2S_AUDIOFREQ_48K                ((uint32_t)48000U)
-#define I2S_AUDIOFREQ_44K                ((uint32_t)44100U)
-#define I2S_AUDIOFREQ_32K                ((uint32_t)32000U)
-#define I2S_AUDIOFREQ_22K                ((uint32_t)22050U)
-#define I2S_AUDIOFREQ_16K                ((uint32_t)16000U)
-#define I2S_AUDIOFREQ_11K                ((uint32_t)11025U)
-#define I2S_AUDIOFREQ_8K                 ((uint32_t)8000U)
-#define I2S_AUDIOFREQ_DEFAULT            ((uint32_t)2U)
-/**
-  * @}
-  */
-
-
-/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
-  * @{
-  */
-#define I2S_CPOL_LOW                    ((uint32_t)0x00000000U)
-#define I2S_CPOL_HIGH                   ((uint32_t)SPI_I2SCFGR_CKPOL)
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
-  * @{
-  */
-#define I2S_IT_TXE                      SPI_CR2_TXEIE
-#define I2S_IT_RXNE                     SPI_CR2_RXNEIE
-#define I2S_IT_ERR                      SPI_CR2_ERRIE
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Flags_Definition I2S Flags Definition
-  * @{
-  */
-#define I2S_FLAG_TXE                    SPI_SR_TXE
-#define I2S_FLAG_RXNE                   SPI_SR_RXNE
-
-#define I2S_FLAG_UDR                    SPI_SR_UDR
-#define I2S_FLAG_OVR                    SPI_SR_OVR
-#define I2S_FLAG_FRE                    SPI_SR_FRE
-
-#define I2S_FLAG_CHSIDE                 SPI_SR_CHSIDE
-#define I2S_FLAG_BSY                    SPI_SR_BSY
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup I2S_Exported_Macros I2S Exported Macros
-  * @{
-  */
-
-/** @brief  Reset I2S handle state
-  * @param  __HANDLE__: specifies the I2S handle.
-  * @retval None
-  */
-#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
-
-/** @brief  Enable or disable the specified SPI peripheral (in I2S mode).
-  * @param  __HANDLE__: specifies the I2S Handle.
-  * @retval None
-  */
-#define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)
-#define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= ~SPI_I2SCFGR_I2SE)
-
-/** @brief  Enable or disable the specified I2S interrupts.
-  * @param  __HANDLE__: specifies the I2S Handle.
-  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
-  *        This parameter can be one of the following values:
-  *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg I2S_IT_ERR: Error interrupt enable
-  * @retval None
-  */
-#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
-#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= ~(__INTERRUPT__))
-
-/** @brief  Checks if the specified I2S interrupt source is enabled or disabled.
-  * @param  __HANDLE__: specifies the I2S Handle.
-  *         This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
-  * @param  __INTERRUPT__: specifies the I2S interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg I2S_IT_ERR: Error interrupt enable
-  * @retval The new state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief  Checks whether the specified I2S flag is set or not.
-  * @param  __HANDLE__: specifies the I2S Handle.
-  * @param  __FLAG__: specifies the flag to check.
-  *        This parameter can be one of the following values:
-  *            @arg I2S_FLAG_RXNE: Receive buffer not empty flag
-  *            @arg I2S_FLAG_TXE: Transmit buffer empty flag
-  *            @arg I2S_FLAG_UDR: Underrun flag
-  *            @arg I2S_FLAG_OVR: Overrun flag
-  *            @arg I2S_FLAG_FRE: Frame error flag
-  *            @arg I2S_FLAG_CHSIDE: Channel Side flag
-  *            @arg I2S_FLAG_BSY: Busy flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clears the I2S OVR pending flag.
-  * @param  __HANDLE__: specifies the I2S Handle.
-  * @retval None
-  */
-#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__)     \
-  do{                                           \
-    __IO uint32_t tmpreg;                       \
-    tmpreg = (__HANDLE__)->Instance->DR;        \
-    tmpreg = (__HANDLE__)->Instance->SR;        \
-    UNUSED(tmpreg);                             \
-  } while(0)
-
-/** @brief Clears the I2S UDR pending flag.
-  * @param  __HANDLE__: specifies the I2S Handle.
-  * @retval None
-  */
-#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)     \
-  do{                                             \
-  __IO uint32_t tmpreg;                         \
-  tmpreg = (__HANDLE__)->Instance->SR;          \
-  UNUSED(tmpreg);                               \
-  } while(0)
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2S_Exported_Functions  I2S Exported Functions
-  * @{
-  */
-
-/** @addtogroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-
-/* Initialization and de-initialization functions *****************************/
-HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
-HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
-void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
-/**
-  * @}
-  */
-
-/** @addtogroup I2S_Exported_Functions_Group2 Input and Output operation functions
-  * @{
-  */
-/* I/O operation functions  ***************************************************/
- /* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
-
- /* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
-
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-
-HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
-HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
-HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
-
-/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
-void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
-/**
-  * @}
-  */
-
-/** @addtogroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
-  * @{
-  */
-/* Peripheral Control and State functions  ************************************/
-HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
-uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2S_Private_Constants I2S Private Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2S_Private_Macros I2S Private Macros
-  * @{
-  */
-#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \
-                                   ((CLOCK) == I2S_CLOCK_PLL))
-
-#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
-                           ((MODE) == I2S_MODE_SLAVE_RX) || \
-                           ((MODE) == I2S_MODE_MASTER_TX)|| \
-                           ((MODE) == I2S_MODE_MASTER_RX))
-
-#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS)   || \
-                                   ((STANDARD) == I2S_STANDARD_MSB)       || \
-                                   ((STANDARD) == I2S_STANDARD_LSB)       || \
-                                   ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
-                                   ((STANDARD) == I2S_STANDARD_PCM_LONG))
-
-#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B)          || \
-                                    ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
-                                    ((FORMAT) == I2S_DATAFORMAT_24B)          || \
-                                    ((FORMAT) == I2S_DATAFORMAT_32B))
-
-#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
-                                    ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
-
-#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
-                                 ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
-                                 ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
-
-#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
-                           ((CPOL) == I2S_CPOL_HIGH))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F7xx_HAL_I2S_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_pcd.h b/stmhal/hal/f7/inc/stm32f7xx_hal_pcd.h
deleted file mode 100644
index 53861137de..0000000000
--- a/stmhal/hal/f7/inc/stm32f7xx_hal_pcd.h
+++ /dev/null
@@ -1,333 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_pcd.h
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   Header file of PCD HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_PCD_H
-#define __STM32F7xx_HAL_PCD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_ll_usb.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup PCD
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup PCD_Exported_Types PCD Exported Types
-  * @{
-  */
-
-/**
-  * @brief  PCD State structure definition
-  */
-typedef enum
-{
-  HAL_PCD_STATE_RESET   = 0x00U,
-  HAL_PCD_STATE_READY   = 0x01U,
-  HAL_PCD_STATE_ERROR   = 0x02U,
-  HAL_PCD_STATE_BUSY    = 0x03U,
-  HAL_PCD_STATE_TIMEOUT = 0x04U
-} PCD_StateTypeDef;
-
-/* Device LPM suspend state */
-typedef enum
-{
-  LPM_L0 = 0x00U, /* on */
-  LPM_L1 = 0x01U, /* LPM L1 sleep */
-  LPM_L2 = 0x02U, /* suspend */
-  LPM_L3 = 0x03U, /* off */
-}PCD_LPM_StateTypeDef;
-
-typedef USB_OTG_GlobalTypeDef  PCD_TypeDef;
-typedef USB_OTG_CfgTypeDef     PCD_InitTypeDef;
-typedef USB_OTG_EPTypeDef      PCD_EPTypeDef ;
-
-/**
-  * @brief  PCD Handle Structure definition
-  */
-typedef struct
-{
-  PCD_TypeDef             *Instance;   /*!< Register base address              */
-  PCD_InitTypeDef         Init;       /*!< PCD required parameters            */
-  PCD_EPTypeDef           IN_ep[15];  /*!< IN endpoint parameters             */
-  PCD_EPTypeDef           OUT_ep[15]; /*!< OUT endpoint parameters            */
-  HAL_LockTypeDef         Lock;       /*!< PCD peripheral status              */
-  __IO PCD_StateTypeDef   State;      /*!< PCD communication state            */
-  uint32_t                Setup[12];  /*!< Setup packet buffer                */
-  PCD_LPM_StateTypeDef    LPM_State;    /*!< LPM State                          */
-  uint32_t                BESL;
-  uint32_t                lpm_active;   /*!< Enable or disable the Link Power Management .
-                                        This parameter can be set to ENABLE or DISABLE */
-  void                    *pData;       /*!< Pointer to upper stack Handler */
-} PCD_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Include PCD HAL Extension module */
-#include "stm32f7xx_hal_pcd_ex.h"
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup PCD_Exported_Constants PCD Exported Constants
-  * @{
-  */
-
-/** @defgroup PCD_Speed PCD Speed
-  * @{
-  */
-#define PCD_SPEED_HIGH               0U
-#define PCD_SPEED_HIGH_IN_FULL       1U
-#define PCD_SPEED_FULL               2U
-/**
-  * @}
-  */
-
-/** @defgroup PCD_PHY_Module PCD PHY Module
-  * @{
-  */
-#define PCD_PHY_ULPI                 1U
-#define PCD_PHY_EMBEDDED             2U
-/**
-  * @}
-  */
-
-/** @defgroup PCD_Turnaround_Timeout Turnaround Timeout Value
-  * @{
-  */
-#ifndef USBD_HS_TRDT_VALUE
- #define USBD_HS_TRDT_VALUE           9U
-#endif /* USBD_HS_TRDT_VALUE */
-#ifndef USBD_FS_TRDT_VALUE
- #define USBD_FS_TRDT_VALUE           5U
-#endif /* USBD_HS_TRDT_VALUE */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup PCD_Exported_Macros PCD Exported Macros
- *  @brief macros to handle interrupts and specific clock configurations
- * @{
- */
-#define __HAL_PCD_ENABLE(__HANDLE__)                   USB_EnableGlobalInt ((__HANDLE__)->Instance)
-#define __HAL_PCD_DISABLE(__HANDLE__)                  USB_DisableGlobalInt ((__HANDLE__)->Instance)
-
-#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
-#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
-#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
-
-
-#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__)             *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
-                                                       ~(USB_OTG_PCGCCTL_STOPCLK)
-
-#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__)               *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
-
-#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__)            ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10)
-
-#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE                ((uint32_t)0x08U)
-#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE               ((uint32_t)0x0CU)
-#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE        ((uint32_t)0x10U)
-
-#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE                ((uint32_t)0x08U)
-#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE               ((uint32_t)0x0CU)
-#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE        ((uint32_t)0x10U)
-
-#define USB_OTG_HS_WAKEUP_EXTI_LINE                       ((uint32_t)0x00100000U)  /*!< External interrupt line 20 Connected to the USB HS EXTI Line */
-#define USB_OTG_FS_WAKEUP_EXTI_LINE                       ((uint32_t)0x00040000U)  /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
-
-#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT()    EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE)
-#define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT()   EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
-#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG()     EXTI->PR & (USB_OTG_HS_WAKEUP_EXTI_LINE)
-#define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG()   EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE)
-
-#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
-                                                          EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE
-
-#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE()  EXTI->FTSR |= (USB_OTG_HS_WAKEUP_EXTI_LINE);\
-                                                            EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
-
-#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()   EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
-                                                                    EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE;)\
-                                                                    EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\
-                                                                    EXTI->FTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE
-
-#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT()   (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
-
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT()    EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT()   EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG()     EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE)
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG()   EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE
-
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
-                                                          EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE
-
-
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE()  EXTI->FTSR |= (USB_OTG_FS_WAKEUP_EXTI_LINE);\
-                                                            EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
-
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()  EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
-                                                                   EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
-                                                                   EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
-                                                                   EXTI->FTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE
-
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT()  (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PCD_Exported_Functions PCD Exported Functions
-  * @{
-  */
-
-/* Initialization/de-initialization functions  ********************************/
-/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd);
-void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
-/**
-  * @}
-  */
-
-/* I/O operation functions  ***************************************************/
-/* Non-Blocking mode: Interrupt */
-/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
-  * @{
-  */
-HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
-
-void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
-/**
-  * @}
-  */
-
-/* Peripheral Control functions  **********************************************/
-/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
-  * @{
-  */
-HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
-HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
-HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
-HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
-uint16_t          HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
-/**
-  * @}
-  */
-
-/* Peripheral State functions  ************************************************/
-/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
-  * @{
-  */
-PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup PCD_Private_Macros PCD Private Macros
- * @{
- */
-/** @defgroup PCD_Instance_definition PCD Instance definition
-  * @{
-  */
-#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
-                                       ((INSTANCE) == USB_OTG_HS))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F7xx_HAL_PCD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_pcd_ex.h b/stmhal/hal/f7/inc/stm32f7xx_hal_pcd_ex.h
deleted file mode 100644
index bd0a24aa27..0000000000
--- a/stmhal/hal/f7/inc/stm32f7xx_hal_pcd_ex.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_pcd_ex.h
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   Header file of PCD HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_PCD_EX_H
-#define __STM32F7xx_HAL_PCD_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal_def.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup PCDEx
-  * @{
-  */
-/* Exported types ------------------------------------------------------------*/
-typedef enum
-{
-  PCD_LPM_L0_ACTIVE = 0x00U, /* on */
-  PCD_LPM_L1_ACTIVE = 0x01U, /* LPM L1 sleep */
-}PCD_LPM_MsgTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-/* Exported macros -----------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
-  * @{
-  */
-/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
-  * @{
-  */
-HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
-HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
-HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
-void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F7xx_HAL_PCD_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_pwr.h b/stmhal/hal/f7/inc/stm32f7xx_hal_pwr.h
deleted file mode 100644
index d04517d403..0000000000
--- a/stmhal/hal/f7/inc/stm32f7xx_hal_pwr.h
+++ /dev/null
@@ -1,422 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_pwr.h
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   Header file of PWR HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_PWR_H
-#define __STM32F7xx_HAL_PWR_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal_def.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup PWR
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup PWR_Exported_Types PWR Exported Types
-  * @{
-  */
-
-/**
-  * @brief  PWR PVD configuration structure definition
-  */
-typedef struct
-{
-  uint32_t PVDLevel;   /*!< PVDLevel: Specifies the PVD detection level.
-                            This parameter can be a value of @ref PWR_PVD_detection_level */
-
-  uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.
-                           This parameter can be a value of @ref PWR_PVD_Mode */
-}PWR_PVDTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup PWR_Exported_Constants PWR Exported Constants
-  * @{
-  */
-
-/** @defgroup PWR_PVD_detection_level PWR PVD detection level
-  * @{
-  */
-#define PWR_PVDLEVEL_0                  PWR_CR1_PLS_LEV0
-#define PWR_PVDLEVEL_1                  PWR_CR1_PLS_LEV1
-#define PWR_PVDLEVEL_2                  PWR_CR1_PLS_LEV2
-#define PWR_PVDLEVEL_3                  PWR_CR1_PLS_LEV3
-#define PWR_PVDLEVEL_4                  PWR_CR1_PLS_LEV4
-#define PWR_PVDLEVEL_5                  PWR_CR1_PLS_LEV5
-#define PWR_PVDLEVEL_6                  PWR_CR1_PLS_LEV6
-#define PWR_PVDLEVEL_7                  PWR_CR1_PLS_LEV7/* External input analog voltage
-                                                          (Compare internally to VREFINT) */
-
-/**
-  * @}
-  */
-
-/** @defgroup PWR_PVD_Mode PWR PVD Mode
-  * @{
-  */
-#define PWR_PVD_MODE_NORMAL                 ((uint32_t)0x00000000U)   /*!< basic mode is used */
-#define PWR_PVD_MODE_IT_RISING              ((uint32_t)0x00010001U)   /*!< External Interrupt Mode with Rising edge trigger detection */
-#define PWR_PVD_MODE_IT_FALLING             ((uint32_t)0x00010002U)   /*!< External Interrupt Mode with Falling edge trigger detection */
-#define PWR_PVD_MODE_IT_RISING_FALLING      ((uint32_t)0x00010003U)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-#define PWR_PVD_MODE_EVENT_RISING           ((uint32_t)0x00020001U)   /*!< Event Mode with Rising edge trigger detection */
-#define PWR_PVD_MODE_EVENT_FALLING          ((uint32_t)0x00020002U)   /*!< Event Mode with Falling edge trigger detection */
-#define PWR_PVD_MODE_EVENT_RISING_FALLING   ((uint32_t)0x00020003U)   /*!< Event Mode with Rising/Falling edge trigger detection */
-/**
-  * @}
-  */
-
-/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
-  * @{
-  */
-#define PWR_MAINREGULATOR_ON                        ((uint32_t)0x00000000U)
-#define PWR_LOWPOWERREGULATOR_ON                    PWR_CR1_LPDS
-/**
-  * @}
-  */
-
-/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
-  * @{
-  */
-#define PWR_SLEEPENTRY_WFI              ((uint8_t)0x01U)
-#define PWR_SLEEPENTRY_WFE              ((uint8_t)0x02U)
-/**
-  * @}
-  */
-
-/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
-  * @{
-  */
-#define PWR_STOPENTRY_WFI               ((uint8_t)0x01U)
-#define PWR_STOPENTRY_WFE               ((uint8_t)0x02U)
-/**
-  * @}
-  */
-
-/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale
-  * @{
-  */
-#define PWR_REGULATOR_VOLTAGE_SCALE1         PWR_CR1_VOS
-#define PWR_REGULATOR_VOLTAGE_SCALE2         PWR_CR1_VOS_1
-#define PWR_REGULATOR_VOLTAGE_SCALE3         PWR_CR1_VOS_0
-/**
-  * @}
-  */
-
-/** @defgroup PWR_Flag PWR Flag
-  * @{
-  */
-#define PWR_FLAG_WU                     PWR_CSR1_WUIF
-#define PWR_FLAG_SB                     PWR_CSR1_SBF
-#define PWR_FLAG_PVDO                   PWR_CSR1_PVDO
-#define PWR_FLAG_BRR                    PWR_CSR1_BRR
-#define PWR_FLAG_VOSRDY                 PWR_CSR1_VOSRDY
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup PWR_Exported_Macro PWR Exported Macro
-  * @{
-  */
-
-/** @brief  macros configure the main internal regulator output voltage.
-  * @param  __REGULATOR__: specifies the regulator output voltage to achieve
-  *         a tradeoff between performance and power consumption when the device does
-  *         not operate at the maximum frequency (refer to the datasheets for more details).
-  *          This parameter can be one of the following values:
-  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
-  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
-  *            @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
-  * @retval None
-  */
-#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do {                                                     \
-                                                            __IO uint32_t tmpreg;                               \
-                                                            MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \
-                                                            /* Delay after an RCC peripheral clock enabling */  \
-                                                            tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS);           \
-                                                            UNUSED(tmpreg);                                     \
-				                                                	} while(0)
-
-/** @brief  Check PWR flag is set or not.
-  * @param  __FLAG__: specifies the flag to check.
-  *           This parameter can be one of the following values:
-  *            @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
-  *                  was received on the internal wakeup line in standby mode (RTC alarm (Alarm A or Alarm B),
-  *                  RTC Tamper event, RTC TimeStamp event or RTC Wakeup)).
-  *            @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
-  *                  resumed from StandBy mode.
-  *            @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
-  *                  by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
-  *                  For this reason, this bit is equal to 0 after Standby or reset
-  *                  until the PVDE bit is set.
-  *            @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
-  *                  when the device wakes up from Standby mode or by a system reset
-  *                  or power reset.
-  *            @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
-  *                 scaling output selection is ready.
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Clear the PWR's pending flags.
-  * @param  __FLAG__: specifies the flag to clear.
-  *          This parameter can be one of the following values:
-  *            @arg PWR_FLAG_SB: StandBy flag
-  */
-#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR1 |=  (__FLAG__) << 2)
-
-/**
-  * @brief Enable the PVD Exti Line 16.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_ENABLE_IT()   (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
-
-/**
-  * @brief Disable the PVD EXTI Line 16.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_DISABLE_IT()  (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
-
-/**
-  * @brief Enable event on PVD Exti Line 16.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT()   (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
-
-/**
-  * @brief Disable event on PVD Exti Line 16.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT()  (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
-
-/**
-  * @brief Enable the PVD Extended Interrupt Rising Trigger.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
-
-/**
-  * @brief Disable the PVD Extended Interrupt Rising Trigger.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
-
-/**
-  * @brief Enable the PVD Extended Interrupt Falling Trigger.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
-
-
-/**
-  * @brief Disable the PVD Extended Interrupt Falling Trigger.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
-
-
-/**
-  * @brief  PVD EXTI line configuration: set rising & falling edge trigger.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()   __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
-
-/**
-  * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
-
-/**
-  * @brief checks whether the specified PVD Exti interrupt flag is set or not.
-  * @retval EXTI PVD Line Status.
-  */
-#define __HAL_PWR_PVD_EXTI_GET_FLAG()  (EXTI->PR & (PWR_EXTI_LINE_PVD))
-
-/**
-  * @brief Clear the PVD Exti flag.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG()  (EXTI->PR = (PWR_EXTI_LINE_PVD))
-
-/**
-  * @brief  Generates a Software interrupt on PVD EXTI line.
-  * @retval None
-  */
-#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
-
-/**
-  * @}
-  */
-
-/* Include PWR HAL Extension module */
-#include "stm32f7xx_hal_pwr_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PWR_Exported_Functions PWR Exported Functions
-  * @{
-  */
-
-/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-/* Initialization and de-initialization functions *****************************/
-void HAL_PWR_DeInit(void);
-void HAL_PWR_EnableBkUpAccess(void);
-void HAL_PWR_DisableBkUpAccess(void);
-/**
-  * @}
-  */
-
-/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
-  * @{
-  */
-/* Peripheral Control functions  **********************************************/
-/* PVD configuration */
-void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
-void HAL_PWR_EnablePVD(void);
-void HAL_PWR_DisablePVD(void);
-
-/* WakeUp pins configuration */
-void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
-void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
-
-/* Low Power modes entry */
-void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
-void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
-void HAL_PWR_EnterSTANDBYMode(void);
-
-/* Power PVD IRQ Handler */
-void HAL_PWR_PVD_IRQHandler(void);
-void HAL_PWR_PVDCallback(void);
-
-/* Cortex System Control functions  *******************************************/
-void HAL_PWR_EnableSleepOnExit(void);
-void HAL_PWR_DisableSleepOnExit(void);
-void HAL_PWR_EnableSEVOnPend(void);
-void HAL_PWR_DisableSEVOnPend(void);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup PWR_Private_Constants PWR Private Constants
-  * @{
-  */
-
-/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
-  * @{
-  */
-#define PWR_EXTI_LINE_PVD  ((uint32_t)EXTI_IMR_IM16)  /*!< External interrupt line 16 Connected to the PVD EXTI Line */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup PWR_Private_Macros PWR Private Macros
-  * @{
-  */
-
-/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
-  * @{
-  */
-#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
-                                 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
-                                 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
-                                 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
-#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
-                              ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
-                              ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
-                              ((MODE) == PWR_PVD_MODE_NORMAL))
-#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
-                                     ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
-#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
-#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
-#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
-                                           ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
-                                           ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F7xx_HAL_PWR_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_pwr_ex.h b/stmhal/hal/f7/inc/stm32f7xx_hal_pwr_ex.h
deleted file mode 100644
index d6faa04a18..0000000000
--- a/stmhal/hal/f7/inc/stm32f7xx_hal_pwr_ex.h
+++ /dev/null
@@ -1,280 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_pwr_ex.h
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   Header file of PWR HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_PWR_EX_H
-#define __STM32F7xx_HAL_PWR_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal_def.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup PWREx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
-  * @{
-  */
-/** @defgroup PWREx_WakeUp_Pins PWREx Wake Up Pins
-  * @{
-  */
-#define PWR_WAKEUP_PIN1                PWR_CSR2_EWUP1
-#define PWR_WAKEUP_PIN2                PWR_CSR2_EWUP2
-#define PWR_WAKEUP_PIN3                PWR_CSR2_EWUP3
-#define PWR_WAKEUP_PIN4                PWR_CSR2_EWUP4
-#define PWR_WAKEUP_PIN5                PWR_CSR2_EWUP5
-#define PWR_WAKEUP_PIN6                PWR_CSR2_EWUP6
-#define PWR_WAKEUP_PIN1_HIGH           PWR_CSR2_EWUP1
-#define PWR_WAKEUP_PIN2_HIGH           PWR_CSR2_EWUP2
-#define PWR_WAKEUP_PIN3_HIGH           PWR_CSR2_EWUP3
-#define PWR_WAKEUP_PIN4_HIGH           PWR_CSR2_EWUP4
-#define PWR_WAKEUP_PIN5_HIGH           PWR_CSR2_EWUP5
-#define PWR_WAKEUP_PIN6_HIGH           PWR_CSR2_EWUP6
-#define PWR_WAKEUP_PIN1_LOW            (uint32_t)((PWR_CR2_WUPP1<<6) | PWR_CSR2_EWUP1)
-#define PWR_WAKEUP_PIN2_LOW            (uint32_t)((PWR_CR2_WUPP2<<6) | PWR_CSR2_EWUP2)
-#define PWR_WAKEUP_PIN3_LOW            (uint32_t)((PWR_CR2_WUPP3<<6) | PWR_CSR2_EWUP3)
-#define PWR_WAKEUP_PIN4_LOW            (uint32_t)((PWR_CR2_WUPP4<<6) | PWR_CSR2_EWUP4)
-#define PWR_WAKEUP_PIN5_LOW            (uint32_t)((PWR_CR2_WUPP5<<6) | PWR_CSR2_EWUP5)
-#define PWR_WAKEUP_PIN6_LOW            (uint32_t)((PWR_CR2_WUPP6<<6) | PWR_CSR2_EWUP6)
-
-/**
-  * @}
-  */
-
-/** @defgroup PWREx_Regulator_state_in_UnderDrive_mode PWREx Regulator state in UnderDrive mode
-  * @{
-  */
-#define PWR_MAINREGULATOR_UNDERDRIVE_ON                       PWR_CR1_MRUDS
-#define PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON                   ((uint32_t)(PWR_CR1_LPDS | PWR_CR1_LPUDS))
-/**
-  * @}
-  */
-
-/** @defgroup PWREx_Over_Under_Drive_Flag PWREx Over Under Drive Flag
-  * @{
-  */
-#define PWR_FLAG_ODRDY                  PWR_CSR1_ODRDY
-#define PWR_FLAG_ODSWRDY                PWR_CSR1_ODSWRDY
-#define PWR_FLAG_UDRDY                  PWR_CSR1_UDRDY
-/**
-  * @}
-  */
-
-/** @defgroup PWREx_Wakeup_Pins_Flag PWREx Wake Up Pin Flags
-  * @{
-  */
-#define PWR_WAKEUP_PIN_FLAG1            PWR_CSR2_WUPF1
-#define PWR_WAKEUP_PIN_FLAG2            PWR_CSR2_WUPF2
-#define PWR_WAKEUP_PIN_FLAG3            PWR_CSR2_WUPF3
-#define PWR_WAKEUP_PIN_FLAG4            PWR_CSR2_WUPF4
-#define PWR_WAKEUP_PIN_FLAG5            PWR_CSR2_WUPF5
-#define PWR_WAKEUP_PIN_FLAG6            PWR_CSR2_WUPF6
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup PWREx_Exported_Macro PWREx Exported Macro
-  *  @{
-  */
-/** @brief Macros to enable or disable the Over drive mode.
-  */
-#define __HAL_PWR_OVERDRIVE_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_ODEN)
-#define __HAL_PWR_OVERDRIVE_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODEN))
-
-/** @brief Macros to enable or disable the Over drive switching.
-  */
-#define __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_ODSWEN)
-#define __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODSWEN))
-
-/** @brief Macros to enable or disable the Under drive mode.
-  * @note  This mode is enabled only with STOP low power mode.
-  *        In this mode, the 1.2V domain is preserved in reduced leakage mode. This
-  *        mode is only available when the main regulator or the low power regulator
-  *        is in low voltage mode.
-  * @note  If the Under-drive mode was enabled, it is automatically disabled after
-  *        exiting Stop mode.
-  *        When the voltage regulator operates in Under-drive mode, an additional
-  *        startup delay is induced when waking up from Stop mode.
-  */
-#define __HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_UDEN)
-#define __HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_UDEN))
-
-/** @brief  Check PWR flag is set or not.
-  * @param  __FLAG__: specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode
-  *                                 is ready
-  *            @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode
-  *                                   switching is ready
-  *            @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode
-  *                                 is enabled in Stop mode
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_PWR_GET_ODRUDR_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clear the Under-Drive Ready flag.
-  */
-#define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR1 |= PWR_FLAG_UDRDY)
-
-/** @brief  Check Wake Up flag is set or not.
-  * @param  __WUFLAG__: specifies the Wake Up flag to check.
-  *          This parameter can be one of the following values:
-  *            @arg PWR_WAKEUP_PIN_FLAG1: Wakeup Pin Flag for PA0
-  *            @arg PWR_WAKEUP_PIN_FLAG2: Wakeup Pin Flag for PA2
-  *            @arg PWR_WAKEUP_PIN_FLAG3: Wakeup Pin Flag for PC1
-  *            @arg PWR_WAKEUP_PIN_FLAG4: Wakeup Pin Flag for PC13
-  *            @arg PWR_WAKEUP_PIN_FLAG5: Wakeup Pin Flag for PI8
-  *            @arg PWR_WAKEUP_PIN_FLAG6: Wakeup Pin Flag for PI11
-  */
-#define __HAL_PWR_GET_WAKEUP_FLAG(__WUFLAG__) (PWR->CSR2 & (__WUFLAG__))
-
-/** @brief  Clear the WakeUp pins flags.
-  * @param  __WUFLAG__: specifies the Wake Up pin flag to clear.
-  *          This parameter can be one of the following values:
-  *            @arg PWR_WAKEUP_PIN_FLAG1: Wakeup Pin Flag for PA0
-  *            @arg PWR_WAKEUP_PIN_FLAG2: Wakeup Pin Flag for PA2
-  *            @arg PWR_WAKEUP_PIN_FLAG3: Wakeup Pin Flag for PC1
-  *            @arg PWR_WAKEUP_PIN_FLAG4: Wakeup Pin Flag for PC13
-  *            @arg PWR_WAKEUP_PIN_FLAG5: Wakeup Pin Flag for PI8
-  *            @arg PWR_WAKEUP_PIN_FLAG6: Wakeup Pin Flag for PI11
-  */
-#define __HAL_PWR_CLEAR_WAKEUP_FLAG(__WUFLAG__) (PWR->CR2 |=  (__WUFLAG__))
-/**
-  * @}
-  */
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
-  *  @{
-  */
-
-/** @addtogroup PWREx_Exported_Functions_Group1
-  * @{
-  */
-uint32_t HAL_PWREx_GetVoltageRange(void);
-HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
-
-void HAL_PWREx_EnableFlashPowerDown(void);
-void HAL_PWREx_DisableFlashPowerDown(void);
-HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);
-HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
-
-void HAL_PWREx_EnableMainRegulatorLowVoltage(void);
-void HAL_PWREx_DisableMainRegulatorLowVoltage(void);
-void HAL_PWREx_EnableLowRegulatorLowVoltage(void);
-void HAL_PWREx_DisableLowRegulatorLowVoltage(void);
-
-HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void);
-HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void);
-HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup PWREx_Private_Macros PWREx Private Macros
-  * @{
-  */
-
-/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters
-  * @{
-  */
-#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || \
-                                                ((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON))
-#define IS_PWR_WAKEUP_PIN(__PIN__)         (((__PIN__) == PWR_WAKEUP_PIN1)       || \
-                                            ((__PIN__) == PWR_WAKEUP_PIN2)       || \
-                                            ((__PIN__) == PWR_WAKEUP_PIN3)       || \
-                                            ((__PIN__) == PWR_WAKEUP_PIN4)       || \
-                                            ((__PIN__) == PWR_WAKEUP_PIN5)       || \
-                                            ((__PIN__) == PWR_WAKEUP_PIN6)  		 || \
-                                            ((__PIN__) == PWR_WAKEUP_PIN1_HIGH)  || \
-                                            ((__PIN__) == PWR_WAKEUP_PIN2_HIGH)  || \
-                                            ((__PIN__) == PWR_WAKEUP_PIN3_HIGH)  || \
-                                            ((__PIN__) == PWR_WAKEUP_PIN4_HIGH)  || \
-                                            ((__PIN__) == PWR_WAKEUP_PIN5_HIGH)  || \
-                                            ((__PIN__) == PWR_WAKEUP_PIN6_HIGH)  || \
-                                            ((__PIN__) == PWR_WAKEUP_PIN1_LOW)   || \
-                                            ((__PIN__) == PWR_WAKEUP_PIN2_LOW)   || \
-                                            ((__PIN__) == PWR_WAKEUP_PIN3_LOW)   || \
-                                            ((__PIN__) == PWR_WAKEUP_PIN4_LOW)   || \
-                                            ((__PIN__) == PWR_WAKEUP_PIN5_LOW)	 || \
-                                            ((__PIN__) == PWR_WAKEUP_PIN6_LOW))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F7xx_HAL_PWR_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_rcc.h b/stmhal/hal/f7/inc/stm32f7xx_hal_rcc.h
deleted file mode 100644
index fe7153f8b1..0000000000
--- a/stmhal/hal/f7/inc/stm32f7xx_hal_rcc.h
+++ /dev/null
@@ -1,1306 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_rcc.h
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   Header file of RCC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_RCC_H
-#define __STM32F7xx_HAL_RCC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal_def.h"
-
-/* Include RCC HAL Extended module */
-/* (include on top of file since RCC structures are defined in extended file) */
-#include "stm32f7xx_hal_rcc_ex.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup RCC
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup RCC_Exported_Types RCC Exported Types
-  * @{
-  */
-
-/**
-  * @brief  RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
-  */
-typedef struct
-{
-  uint32_t OscillatorType;       /*!< The oscillators to be configured.
-                                      This parameter can be a value of @ref RCC_Oscillator_Type                   */
-
-  uint32_t HSEState;             /*!< The new state of the HSE.
-                                      This parameter can be a value of @ref RCC_HSE_Config                        */
-
-  uint32_t LSEState;             /*!< The new state of the LSE.
-                                      This parameter can be a value of @ref RCC_LSE_Config                        */
-
-  uint32_t HSIState;             /*!< The new state of the HSI.
-                                      This parameter can be a value of @ref RCC_HSI_Config                        */
-
-  uint32_t HSICalibrationValue;   /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
-                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
-
-  uint32_t LSIState;             /*!< The new state of the LSI.
-                                      This parameter can be a value of @ref RCC_LSI_Config                        */
-
-  RCC_PLLInitTypeDef PLL;        /*!< PLL structure parameters                                                    */
-
-}RCC_OscInitTypeDef;
-
-/**
-  * @brief  RCC System, AHB and APB busses clock configuration structure definition
-  */
-typedef struct
-{
-  uint32_t ClockType;             /*!< The clock to be configured.
-                                       This parameter can be a value of @ref RCC_System_Clock_Type */
-
-  uint32_t SYSCLKSource;          /*!< The clock source (SYSCLKS) used as system clock.
-                                       This parameter can be a value of @ref RCC_System_Clock_Source    */
-
-  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
-                                       This parameter can be a value of @ref RCC_AHB_Clock_Source       */
-
-  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
-                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
-
-  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
-                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
-
-}RCC_ClkInitTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RCC_Exported_Constants RCC Exported Constants
-  * @{
-  */
-
-/** @defgroup RCC_Oscillator_Type Oscillator Type
-  * @{
-  */
-#define RCC_OSCILLATORTYPE_NONE            ((uint32_t)0x00000000U)
-#define RCC_OSCILLATORTYPE_HSE             ((uint32_t)0x00000001U)
-#define RCC_OSCILLATORTYPE_HSI             ((uint32_t)0x00000002U)
-#define RCC_OSCILLATORTYPE_LSE             ((uint32_t)0x00000004U)
-#define RCC_OSCILLATORTYPE_LSI             ((uint32_t)0x00000008U)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_HSE_Config RCC HSE Config
-  * @{
-  */
-#define RCC_HSE_OFF                      ((uint32_t)0x00000000U)
-#define RCC_HSE_ON                       RCC_CR_HSEON
-#define RCC_HSE_BYPASS                   ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LSE_Config RCC LSE Config
-  * @{
-  */
-#define RCC_LSE_OFF                    ((uint32_t)0x00000000U)
-#define RCC_LSE_ON                     RCC_BDCR_LSEON
-#define RCC_LSE_BYPASS                 ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_HSI_Config RCC HSI Config
-  * @{
-  */
-#define RCC_HSI_OFF                    ((uint32_t)0x00000000U)
-#define RCC_HSI_ON                     RCC_CR_HSION
-
-#define RCC_HSICALIBRATION_DEFAULT     ((uint32_t)0x10U)         /* Default HSI calibration trimming value */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LSI_Config RCC LSI Config
-  * @{
-  */
-#define RCC_LSI_OFF                    ((uint32_t)0x00000000U)
-#define RCC_LSI_ON                     RCC_CSR_LSION
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PLL_Config RCC PLL Config
-  * @{
-  */
-#define RCC_PLL_NONE                   ((uint32_t)0x00000000U)
-#define RCC_PLL_OFF                    ((uint32_t)0x00000001U)
-#define RCC_PLL_ON                     ((uint32_t)0x00000002U)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
-  * @{
-  */
-#define RCC_PLLP_DIV2                  ((uint32_t)0x00000002U)
-#define RCC_PLLP_DIV4                  ((uint32_t)0x00000004U)
-#define RCC_PLLP_DIV6                  ((uint32_t)0x00000006U)
-#define RCC_PLLP_DIV8                  ((uint32_t)0x00000008U)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
-  * @{
-  */
-#define RCC_PLLSOURCE_HSI                RCC_PLLCFGR_PLLSRC_HSI
-#define RCC_PLLSOURCE_HSE                RCC_PLLCFGR_PLLSRC_HSE
-/**
-  * @}
-  */
-
-/** @defgroup RCC_System_Clock_Type RCC System Clock Type
-  * @{
-  */
-#define RCC_CLOCKTYPE_SYSCLK             ((uint32_t)0x00000001U)
-#define RCC_CLOCKTYPE_HCLK               ((uint32_t)0x00000002U)
-#define RCC_CLOCKTYPE_PCLK1              ((uint32_t)0x00000004U)
-#define RCC_CLOCKTYPE_PCLK2              ((uint32_t)0x00000008U)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_System_Clock_Source RCC System Clock Source
-  * @{
-  */
-#define RCC_SYSCLKSOURCE_HSI             RCC_CFGR_SW_HSI
-#define RCC_SYSCLKSOURCE_HSE             RCC_CFGR_SW_HSE
-#define RCC_SYSCLKSOURCE_PLLCLK          RCC_CFGR_SW_PLL
-/**
-  * @}
-  */
-
-
-/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
-  * @{
-  */
-#define RCC_SYSCLKSOURCE_STATUS_HSI      RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
-#define RCC_SYSCLKSOURCE_STATUS_HSE      RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
-#define RCC_SYSCLKSOURCE_STATUS_PLLCLK   RCC_CFGR_SWS_PLL   /*!< PLL used as system clock */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source
-  * @{
-  */
-#define RCC_SYSCLK_DIV1                  RCC_CFGR_HPRE_DIV1
-#define RCC_SYSCLK_DIV2                  RCC_CFGR_HPRE_DIV2
-#define RCC_SYSCLK_DIV4                  RCC_CFGR_HPRE_DIV4
-#define RCC_SYSCLK_DIV8                  RCC_CFGR_HPRE_DIV8
-#define RCC_SYSCLK_DIV16                 RCC_CFGR_HPRE_DIV16
-#define RCC_SYSCLK_DIV64                 RCC_CFGR_HPRE_DIV64
-#define RCC_SYSCLK_DIV128                RCC_CFGR_HPRE_DIV128
-#define RCC_SYSCLK_DIV256                RCC_CFGR_HPRE_DIV256
-#define RCC_SYSCLK_DIV512                RCC_CFGR_HPRE_DIV512
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1/APB2 Clock Source
-  * @{
-  */
-#define RCC_HCLK_DIV1                    RCC_CFGR_PPRE1_DIV1
-#define RCC_HCLK_DIV2                    RCC_CFGR_PPRE1_DIV2
-#define RCC_HCLK_DIV4                    RCC_CFGR_PPRE1_DIV4
-#define RCC_HCLK_DIV8                    RCC_CFGR_PPRE1_DIV8
-#define RCC_HCLK_DIV16                   RCC_CFGR_PPRE1_DIV16
-/**
-  * @}
-  */
-
-/** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source
-  * @{
-  */
-#define RCC_RTCCLKSOURCE_LSE             ((uint32_t)0x00000100U)
-#define RCC_RTCCLKSOURCE_LSI             ((uint32_t)0x00000200U)
-#define RCC_RTCCLKSOURCE_HSE_DIV2        ((uint32_t)0x00020300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV3        ((uint32_t)0x00030300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV4        ((uint32_t)0x00040300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV5        ((uint32_t)0x00050300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV6        ((uint32_t)0x00060300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV7        ((uint32_t)0x00070300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV8        ((uint32_t)0x00080300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV9        ((uint32_t)0x00090300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV10       ((uint32_t)0x000A0300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV11       ((uint32_t)0x000B0300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV12       ((uint32_t)0x000C0300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV13       ((uint32_t)0x000D0300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV14       ((uint32_t)0x000E0300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV15       ((uint32_t)0x000F0300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV16       ((uint32_t)0x00100300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV17       ((uint32_t)0x00110300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV18       ((uint32_t)0x00120300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV19       ((uint32_t)0x00130300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV20       ((uint32_t)0x00140300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV21       ((uint32_t)0x00150300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV22       ((uint32_t)0x00160300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV23       ((uint32_t)0x00170300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV24       ((uint32_t)0x00180300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV25       ((uint32_t)0x00190300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV26       ((uint32_t)0x001A0300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV27       ((uint32_t)0x001B0300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV28       ((uint32_t)0x001C0300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV29       ((uint32_t)0x001D0300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV30       ((uint32_t)0x001E0300U)
-#define RCC_RTCCLKSOURCE_HSE_DIV31       ((uint32_t)0x001F0300U)
-/**
-  * @}
-  */
-
-
-
-/** @defgroup RCC_MCO_Index RCC MCO Index
-  * @{
-  */
-#define RCC_MCO1                         ((uint32_t)0x00000000U)
-#define RCC_MCO2                         ((uint32_t)0x00000001U)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source
-  * @{
-  */
-#define RCC_MCO1SOURCE_HSI               ((uint32_t)0x00000000U)
-#define RCC_MCO1SOURCE_LSE               RCC_CFGR_MCO1_0
-#define RCC_MCO1SOURCE_HSE               RCC_CFGR_MCO1_1
-#define RCC_MCO1SOURCE_PLLCLK            RCC_CFGR_MCO1
-/**
-  * @}
-  */
-
-/** @defgroup RCC_MCO2_Clock_Source RCC MCO2 Clock Source
-  * @{
-  */
-#define RCC_MCO2SOURCE_SYSCLK            ((uint32_t)0x00000000U)
-#define RCC_MCO2SOURCE_PLLI2SCLK         RCC_CFGR_MCO2_0
-#define RCC_MCO2SOURCE_HSE               RCC_CFGR_MCO2_1
-#define RCC_MCO2SOURCE_PLLCLK            RCC_CFGR_MCO2
-/**
-  * @}
-  */
-
-/** @defgroup RCC_MCOx_Clock_Prescaler RCC MCO1 Clock Prescaler
-  * @{
-  */
-#define RCC_MCODIV_1                    ((uint32_t)0x00000000U)
-#define RCC_MCODIV_2                    RCC_CFGR_MCO1PRE_2
-#define RCC_MCODIV_3                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
-#define RCC_MCODIV_4                    ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
-#define RCC_MCODIV_5                    RCC_CFGR_MCO1PRE
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Interrupt RCC Interrupt
-  * @{
-  */
-#define RCC_IT_LSIRDY                    ((uint8_t)0x01U)
-#define RCC_IT_LSERDY                    ((uint8_t)0x02U)
-#define RCC_IT_HSIRDY                    ((uint8_t)0x04U)
-#define RCC_IT_HSERDY                    ((uint8_t)0x08U)
-#define RCC_IT_PLLRDY                    ((uint8_t)0x10U)
-#define RCC_IT_PLLI2SRDY                 ((uint8_t)0x20U)
-#define RCC_IT_PLLSAIRDY                 ((uint8_t)0x40U)
-#define RCC_IT_CSS                       ((uint8_t)0x80U)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Flag RCC Flags
-  *        Elements values convention: 0XXYYYYYb
-  *           - YYYYY  : Flag position in the register
-  *           - 0XX  : Register index
-  *                 - 01: CR register
-  *                 - 10: BDCR register
-  *                 - 11: CSR register
-  * @{
-  */
-/* Flags in the CR register */
-#define RCC_FLAG_HSIRDY                  ((uint8_t)0x21U)
-#define RCC_FLAG_HSERDY                  ((uint8_t)0x31U)
-#define RCC_FLAG_PLLRDY                  ((uint8_t)0x39U)
-#define RCC_FLAG_PLLI2SRDY               ((uint8_t)0x3BU)
-#define RCC_FLAG_PLLSAIRDY               ((uint8_t)0x3CU)
-
-/* Flags in the BDCR register */
-#define RCC_FLAG_LSERDY                  ((uint8_t)0x41U)
-
-/* Flags in the CSR register */
-#define RCC_FLAG_LSIRDY                  ((uint8_t)0x61U)
-#define RCC_FLAG_BORRST                  ((uint8_t)0x79U)
-#define RCC_FLAG_PINRST                  ((uint8_t)0x7AU)
-#define RCC_FLAG_PORRST                  ((uint8_t)0x7BU)
-#define RCC_FLAG_SFTRST                  ((uint8_t)0x7CU)
-#define RCC_FLAG_IWDGRST                 ((uint8_t)0x7DU)
-#define RCC_FLAG_WWDGRST                 ((uint8_t)0x7EU)
-#define RCC_FLAG_LPWRRST                 ((uint8_t)0x7FU)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LSEDrive_Configuration RCC LSE Drive configurations
-  * @{
-  */
-#define RCC_LSEDRIVE_LOW                 ((uint32_t)0x00000000U)
-#define RCC_LSEDRIVE_MEDIUMLOW           RCC_BDCR_LSEDRV_1
-#define RCC_LSEDRIVE_MEDIUMHIGH          RCC_BDCR_LSEDRV_0
-#define RCC_LSEDRIVE_HIGH                RCC_BDCR_LSEDRV
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RCC_Exported_Macros RCC Exported Macros
-  * @{
-  */
-
-/** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_CRC_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_DMA1_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_CRC_CLK_DISABLE()          (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
-#define __HAL_RCC_DMA1_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_WWDG_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_PWR_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_WWDG_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
-#define __HAL_RCC_PWR_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_SYSCFG_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_CRC_IS_CLK_ENABLED()         ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
-#define __HAL_RCC_DMA1_IS_CLK_ENABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) != RESET)
-
-#define __HAL_RCC_CRC_IS_CLK_DISABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
-#define __HAL_RCC_DMA1_IS_CLK_DISABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) == RESET)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable  Status
-  * @brief  Get the enable or disable status of the APB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_WWDG_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
-#define __HAL_RCC_PWR_IS_CLK_ENABLED()         ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
-
-#define __HAL_RCC_WWDG_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
-#define __HAL_RCC_PWR_IS_CLK_DISABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
-  * @brief  EGet the enable or disable status of the APB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
-#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release
-  * @brief  Force or release AHB peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_AHB1_FORCE_RESET()    (RCC->AHB1RSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_CRC_FORCE_RESET()     (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
-#define __HAL_RCC_DMA1_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
-
-#define __HAL_RCC_AHB1_RELEASE_RESET()  (RCC->AHB1RSTR = 0x00U)
-#define __HAL_RCC_CRC_RELEASE_RESET()   (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
-#define __HAL_RCC_DMA1_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
-  * @brief  Force or release APB1 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_APB1_FORCE_RESET()     (RCC->APB1RSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_WWDG_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
-#define __HAL_RCC_PWR_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
-
-#define __HAL_RCC_APB1_RELEASE_RESET()   (RCC->APB1RSTR = 0x00U)
-#define __HAL_RCC_WWDG_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
-#define __HAL_RCC_PWR_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
-  * @brief  Force or release APB2 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_APB2_FORCE_RESET()     (RCC->APB2RSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_SYSCFG_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
-
-#define __HAL_RCC_APB2_RELEASE_RESET()   (RCC->APB2RSTR = 0x00U)
-#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
-#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE()     (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
-
-#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
-#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE()    (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
-
-/** @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  */
-#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
-#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
-
-#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
-#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
-
-/** @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  */
-#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
-#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != RESET)
-#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != RESET)
-
-#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == RESET)
-#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED()   ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == RESET)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enable Disable Status
-  * @brief  Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED()      ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != RESET)
-#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != RESET)
-
-#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED()     ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == RESET)
-#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED()      ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == RESET)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enable Disable Status
-  * @brief  Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != RESET)
-#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == RESET)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_HSI_Configuration HSI Configuration
-  * @{
-  */
-
-/** @brief  Macros to enable or disable the Internal High Speed oscillator (HSI).
-  * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
-  *         It is used (enabled by hardware) as system clock source after startup
-  *         from Reset, wakeup from STOP and STANDBY mode, or in case of failure
-  *         of the HSE used directly or indirectly as system clock (if the Clock
-  *         Security System CSS is enabled).
-  * @note   HSI can not be stopped if it is used as system clock source. In this case,
-  *         you have to select another source of the system clock then stop the HSI.
-  * @note   After enabling the HSI, the application software should wait on HSIRDY
-  *         flag to be set indicating that HSI clock is stable and can be used as
-  *         system clock source.
-  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
-  *         clock cycles.
-  */
-#define __HAL_RCC_HSI_ENABLE() (RCC->CR |= (RCC_CR_HSION))
-#define __HAL_RCC_HSI_DISABLE() (RCC->CR &= ~(RCC_CR_HSION))
-
-/** @brief  Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
-  * @note   The calibration is used to compensate for the variations in voltage
-  *         and temperature that influence the frequency of the internal HSI RC.
-  * @param  __HSICALIBRATIONVALUE__: specifies the calibration trimming value.
-  *         (default is RCC_HSICALIBRATION_DEFAULT).
-  */
-#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) (MODIFY_REG(RCC->CR,\
-        RCC_CR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_CR_HSITRIM)))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LSI_Configuration LSI Configuration
-  * @{
-  */
-
-/** @brief  Macros to enable or disable the Internal Low Speed oscillator (LSI).
-  * @note   After enabling the LSI, the application software should wait on
-  *         LSIRDY flag to be set indicating that LSI clock is stable and can
-  *         be used to clock the IWDG and/or the RTC.
-  * @note   LSI can not be disabled if the IWDG is running.
-  * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
-  *         clock cycles.
-  */
-#define __HAL_RCC_LSI_ENABLE()  (RCC->CSR |= (RCC_CSR_LSION))
-#define __HAL_RCC_LSI_DISABLE() (RCC->CSR &= ~(RCC_CSR_LSION))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_HSE_Configuration HSE Configuration
-  * @{
-  */
-/**
-  * @brief  Macro to configure the External High Speed oscillator (HSE).
-  * @note   Transitions HSE Bypass to HSE On and HSE On to HSE Bypass are not
-  *         supported by this macro. User should request a transition to HSE Off
-  *         first and then HSE On or HSE Bypass.
-  * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
-  *         software should wait on HSERDY flag to be set indicating that HSE clock
-  *         is stable and can be used to clock the PLL and/or system clock.
-  * @note   HSE state can not be changed if it is used directly or through the
-  *         PLL as system clock. In this case, you have to select another source
-  *         of the system clock then change the HSE state (ex. disable it).
-  * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
-  * @note   This function reset the CSSON bit, so if the clock security system(CSS)
-  *         was previously enabled you have to enable it again after calling this
-  *         function.
-  * @param  __STATE__: specifies the new state of the HSE.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
-  *                              6 HSE oscillator clock cycles.
-  *            @arg RCC_HSE_ON: turn ON the HSE oscillator.
-  *            @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
-  */
-#define __HAL_RCC_HSE_CONFIG(__STATE__)                         \
-                    do {                                        \
-                      if ((__STATE__) == RCC_HSE_ON)            \
-                      {                                         \
-                        SET_BIT(RCC->CR, RCC_CR_HSEON);         \
-                      }                                         \
-                      else if ((__STATE__) == RCC_HSE_OFF)      \
-                      {                                         \
-                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);       \
-                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);      \
-                      }                                         \
-                      else if ((__STATE__) == RCC_HSE_BYPASS)   \
-                      {                                         \
-                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);        \
-                        SET_BIT(RCC->CR, RCC_CR_HSEON);         \
-                      }                                         \
-                      else                                      \
-                      {                                         \
-                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);       \
-                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);      \
-                      }                                         \
-                    } while(0)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LSE_Configuration LSE Configuration
-  * @{
-  */
-
-/**
-  * @brief  Macro to configure the External Low Speed oscillator (LSE).
-  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
-  *         User should request a transition to LSE Off first and then LSE On or LSE Bypass.
-  * @note   As the LSE is in the Backup domain and write access is denied to
-  *         this domain after reset, you have to enable write access using
-  *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
-  *         (to be done once after reset).
-  * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
-  *         software should wait on LSERDY flag to be set indicating that LSE clock
-  *         is stable and can be used to clock the RTC.
-  * @param  __STATE__: specifies the new state of the LSE.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
-  *                              6 LSE oscillator clock cycles.
-  *            @arg RCC_LSE_ON: turn ON the LSE oscillator.
-  *            @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
-  */
-#define __HAL_RCC_LSE_CONFIG(__STATE__) \
-                    do {                                       \
-                      if((__STATE__) == RCC_LSE_ON)            \
-                      {                                        \
-                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
-                      }                                        \
-                      else if((__STATE__) == RCC_LSE_OFF)      \
-                      {                                        \
-                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \
-                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
-                      }                                        \
-                      else if((__STATE__) == RCC_LSE_BYPASS)   \
-                      {                                        \
-                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);   \
-                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
-                      }                                        \
-                      else                                     \
-                      {                                        \
-                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \
-                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
-                      }                                        \
-                    } while(0)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
-  * @{
-  */
-
-/** @brief  Macros to enable or disable the RTC clock.
-  * @note   These macros must be used only after the RTC clock source was selected.
-  */
-#define __HAL_RCC_RTC_ENABLE()  (RCC->BDCR |= (RCC_BDCR_RTCEN))
-#define __HAL_RCC_RTC_DISABLE() (RCC->BDCR &= ~(RCC_BDCR_RTCEN))
-
-/** @brief  Macros to configure the RTC clock (RTCCLK).
-  * @note   As the RTC clock configuration bits are in the Backup domain and write
-  *         access is denied to this domain after reset, you have to enable write
-  *         access using the Power Backup Access macro before to configure
-  *         the RTC clock source (to be done once after reset).
-  * @note   Once the RTC clock is configured it can't be changed unless the
-  *         Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
-  *         a Power On Reset (POR).
-  * @param  __RTCCLKSource__: specifies the RTC clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
-  *            @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
-  *            @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
-  *                                            as RTC clock, where x:[2,31]
-  * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
-  *         work in STOP and STANDBY modes, and can be used as wakeup source.
-  *         However, when the HSE clock is used as RTC clock source, the RTC
-  *         cannot be used in STOP and STANDBY modes.
-  * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
-  *         RTC clock source).
-  */
-#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ?    \
-                                                 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
-
-#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__);    \
-                                                    RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF);  \
-                                                   } while (0)
-
-/** @brief  Macros to force or release the Backup domain reset.
-  * @note   This function resets the RTC peripheral (including the backup registers)
-  *         and the RTC clock source selection in RCC_CSR register.
-  * @note   The BKPSRAM is not affected by this reset.
-  */
-#define __HAL_RCC_BACKUPRESET_FORCE()   (RCC->BDCR |= (RCC_BDCR_BDRST))
-#define __HAL_RCC_BACKUPRESET_RELEASE() (RCC->BDCR &= ~(RCC_BDCR_BDRST))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PLL_Configuration PLL Configuration
-  * @{
-  */
-
-/** @brief  Macros to enable or disable the main PLL.
-  * @note   After enabling the main PLL, the application software should wait on
-  *         PLLRDY flag to be set indicating that PLL clock is stable and can
-  *         be used as system clock source.
-  * @note   The main PLL can not be disabled if it is used as system clock source
-  * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
-  */
-#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
-#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
-
-/** @brief  Macro to configure the PLL clock source.
-  * @note   This function must be used only when the main PLL is disabled.
-  * @param  __PLLSOURCE__: specifies the PLL entry clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
-  *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
-  *
-  */
-#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
-
-/** @brief  Macro to configure the PLL multiplication factor.
-  * @note   This function must be used only when the main PLL is disabled.
-  * @param  __PLLM__: specifies the division factor for PLL VCO input clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
-  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
-  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
-  *         of 2 MHz to limit PLL jitter.
-  *
-  */
-#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PLL_I2S_Configuration PLL I2S Configuration
-  * @{
-  */
-
-/** @brief  Macro to configure the I2S clock source (I2SCLK).
-  * @note   This function must be called before enabling the I2S APB clock.
-  * @param  __SOURCE__: specifies the I2S clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
-  *            @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
-  *                                       used as I2S clock source.
-  */
-#define __HAL_RCC_I2S_CONFIG(__SOURCE__) do {RCC->CFGR &= ~(RCC_CFGR_I2SSRC); \
-                                             RCC->CFGR |= (__SOURCE__);       \
-                                            }while(0)
-
-/** @brief Macros to enable or disable the PLLI2S.
-  * @note  The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
-  */
-#define __HAL_RCC_PLLI2S_ENABLE() (RCC->CR |= (RCC_CR_PLLI2SON))
-#define __HAL_RCC_PLLI2S_DISABLE() (RCC->CR &= ~(RCC_CR_PLLI2SON))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Get_Clock_source Get Clock source
-  * @{
-  */
-/**
-  * @brief Macro to configure the system clock source.
-  * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
-  * This parameter can be one of the following values:
-  *              - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
-  *              - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
-  *              - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
-  */
-#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
-
-/** @brief  Macro to get the clock source used as system clock.
-  * @retval The clock source used as system clock. The returned value can be one
-  *         of the following:
-  *              - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
-  *              - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
-  *              - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
-  */
-#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
-
-/**
-  * @brief  Macro to configures the External Low Speed oscillator (LSE) drive capability.
-  * @note   As the LSE is in the Backup domain and write access is denied to
-  *         this domain after reset, you have to enable write access using
-  *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
-  *         (to be done once after reset).
-  * @param  __RCC_LSEDRIVE__: specifies the new state of the LSE drive capability.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.
-  *            @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.
-  *            @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.
-  *            @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.
-  * @retval None
-  */
-#define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) \
-                  (MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) ))
-
-/** @brief  Macro to get the oscillator used as PLL clock source.
-  * @retval The oscillator used as PLL clock source. The returned value can be one
-  *         of the following:
-  *              - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
-  *              - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
-  */
-#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
-  * @{
-  */
-
-/** @brief  Macro to configure the MCO1 clock.
-  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
-  *            @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
-  *            @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
-  *            @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
-  * @param  __MCODIV__ specifies the MCO clock prescaler.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_MCODIV_1: no division applied to MCOx clock
-  *            @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
-  *            @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
-  *            @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
-  *            @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
-  */
-
-#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
-        MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
-
-/** @brief  Macro to configure the MCO2 clock.
-  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
-  *            @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source
-  *            @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
-  *            @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
-  * @param  __MCODIV__ specifies the MCO clock prescaler.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_MCODIV_1: no division applied to MCOx clock
-  *            @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
-  *            @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
-  *            @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
-  *            @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
-  */
-
-#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
-        MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3)));
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
-  * @brief macros to manage the specified RCC Flags and interrupts.
-  * @{
-  */
-
-/** @brief  Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
-  *         the selected interrupts).
-  * @param  __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
-  *         This parameter can be any combination of the following values:
-  *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
-  *            @arg RCC_IT_LSERDY: LSE ready interrupt.
-  *            @arg RCC_IT_HSIRDY: HSI ready interrupt.
-  *            @arg RCC_IT_HSERDY: HSE ready interrupt.
-  *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
-  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
-  */
-#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
-
-/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
-  *        the selected interrupts).
-  * @param  __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
-  *         This parameter can be any combination of the following values:
-  *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
-  *            @arg RCC_IT_LSERDY: LSE ready interrupt.
-  *            @arg RCC_IT_HSIRDY: HSI ready interrupt.
-  *            @arg RCC_IT_HSERDY: HSE ready interrupt.
-  *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
-  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
-  */
-#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
-
-/** @brief  Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
-  *         bits to clear the selected interrupt pending bits.
-  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
-  *         This parameter can be any combination of the following values:
-  *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
-  *            @arg RCC_IT_LSERDY: LSE ready interrupt.
-  *            @arg RCC_IT_HSIRDY: HSI ready interrupt.
-  *            @arg RCC_IT_HSERDY: HSE ready interrupt.
-  *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
-  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
-  *            @arg RCC_IT_CSS: Clock Security System interrupt
-  */
-#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
-
-/** @brief  Check the RCC's interrupt has occurred or not.
-  * @param  __INTERRUPT__: specifies the RCC interrupt source to check.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
-  *            @arg RCC_IT_LSERDY: LSE ready interrupt.
-  *            @arg RCC_IT_HSIRDY: HSI ready interrupt.
-  *            @arg RCC_IT_HSERDY: HSE ready interrupt.
-  *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
-  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
-  *            @arg RCC_IT_CSS: Clock Security System interrupt
-  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
-  */
-#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
-  *        RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
-  */
-#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
-
-/** @brief  Check RCC flag is set or not.
-  * @param  __FLAG__: specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
-  *            @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
-  *            @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
-  *            @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
-  *            @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
-  *            @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
-  *            @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
-  *            @arg RCC_FLAG_PINRST: Pin reset.
-  *            @arg RCC_FLAG_PORRST: POR/PDR reset.
-  *            @arg RCC_FLAG_SFTRST: Software reset.
-  *            @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
-  *            @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
-  *            @arg RCC_FLAG_LPWRRST: Low Power reset.
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define RCC_FLAG_MASK  ((uint8_t)0x1F)
-#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Include RCC HAL Extension module */
-#include "stm32f7xx_hal_rcc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
- /** @addtogroup RCC_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup RCC_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization and de-initialization functions  ******************************/
-void HAL_RCC_DeInit(void);
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
-/**
-  * @}
-  */
-
-/** @addtogroup RCC_Exported_Functions_Group2
-  * @{
-  */
-/* Peripheral Control functions  ************************************************/
-void     HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
-void     HAL_RCC_EnableCSS(void);
-void     HAL_RCC_DisableCSS(void);
-uint32_t HAL_RCC_GetSysClockFreq(void);
-uint32_t HAL_RCC_GetHCLKFreq(void);
-uint32_t HAL_RCC_GetPCLK1Freq(void);
-uint32_t HAL_RCC_GetPCLK2Freq(void);
-void     HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
-void     HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
-
-/* CSS NMI IRQ handler */
-void HAL_RCC_NMI_IRQHandler(void);
-
-/* User Callbacks in non blocking mode (IT mode) */
-void HAL_RCC_CSSCallback(void);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RCC_Private_Constants RCC Private Constants
-  * @{
-  */
-#define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT
-#define HSI_TIMEOUT_VALUE          ((uint32_t)2)  /* 2 ms */
-#define LSI_TIMEOUT_VALUE          ((uint32_t)2)  /* 2 ms */
-#define PLL_TIMEOUT_VALUE          ((uint32_t)2)  /* 2 ms */
-#define CLOCKSWITCH_TIMEOUT_VALUE  ((uint32_t)5000) /* 5 s    */
-
-/** @defgroup RCC_BitAddress_Alias RCC BitAddress Alias
-  * @brief RCC registers bit address alias
-  * @{
-  */
-/* CIR register byte 2 (Bits[15:8]) base address */
-#define RCC_CIR_BYTE1_ADDRESS         ((uint32_t)(RCC_BASE + 0x0C + 0x01))
-
-/* CIR register byte 3 (Bits[23:16]) base address */
-#define RCC_CIR_BYTE2_ADDRESS         ((uint32_t)(RCC_BASE + 0x0C + 0x02))
-
-#define RCC_DBP_TIMEOUT_VALUE      ((uint32_t)100)
-#define RCC_LSE_TIMEOUT_VALUE      LSE_STARTUP_TIMEOUT
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup RCC_Private_Macros RCC Private Macros
-  * @{
-  */
-
-/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
-  * @{
-  */
-#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)
-
-#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
-                         ((HSE) == RCC_HSE_BYPASS))
-
-#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
-                         ((LSE) == RCC_LSE_BYPASS))
-
-#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
-
-#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
-
-#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
-
-#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
-                                  ((SOURCE) == RCC_PLLSOURCE_HSE))
-
-#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
-                                     ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
-                                     ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
-#define IS_RCC_PLLM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63))
-
-#define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
-
-#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == RCC_PLLP_DIV2) || ((VALUE) == RCC_PLLP_DIV4) || \
-                                  ((VALUE) == RCC_PLLP_DIV6) || ((VALUE) == RCC_PLLP_DIV8))
-#define IS_RCC_PLLQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
-
-#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1)   || ((HCLK) == RCC_SYSCLK_DIV2)   || \
-                           ((HCLK) == RCC_SYSCLK_DIV4)   || ((HCLK) == RCC_SYSCLK_DIV8)   || \
-                           ((HCLK) == RCC_SYSCLK_DIV16)  || ((HCLK) == RCC_SYSCLK_DIV64)  || \
-                           ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
-                           ((HCLK) == RCC_SYSCLK_DIV512))
-
-#define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
-
-#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
-                           ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
-                           ((PCLK) == RCC_HCLK_DIV16))
-
-#define IS_RCC_MCO(MCOX) (((MCOX) == RCC_MCO1) || ((MCOX) == RCC_MCO2))
-
-
-#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
-                                   ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
-
-#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \
-                                   ((SOURCE) == RCC_MCO2SOURCE_HSE)    || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
-
-#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1)  || ((DIV) == RCC_MCODIV_2) || \
-                             ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
-                             ((DIV) == RCC_MCODIV_5))
-#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
-
-#define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \
-                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \
-                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || \
-                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || \
-                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || \
-                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
-                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
-                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
-                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
-                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
-                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
-                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
-                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
-                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
-                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
-                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31))
-
-
-#define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDRIVE_LOW)        || \
-                                 ((DRIVE) == RCC_LSEDRIVE_MEDIUMLOW)  || \
-                                 ((DRIVE) == RCC_LSEDRIVE_MEDIUMHIGH) || \
-                                 ((DRIVE) == RCC_LSEDRIVE_HIGH))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F7xx_HAL_RCC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_rcc_ex.h b/stmhal/hal/f7/inc/stm32f7xx_hal_rcc_ex.h
deleted file mode 100644
index 3af7f21567..0000000000
--- a/stmhal/hal/f7/inc/stm32f7xx_hal_rcc_ex.h
+++ /dev/null
@@ -1,3242 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_rcc_ex.h
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   Header file of RCC HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_RCC_EX_H
-#define __STM32F7xx_HAL_RCC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal_def.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup RCCEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
-  * @{
-  */
-
-/**
-  * @brief  RCC PLL configuration structure definition
-  */
-typedef struct
-{
-  uint32_t PLLState;   /*!< The new state of the PLL.
-                            This parameter can be a value of @ref RCC_PLL_Config                      */
-
-  uint32_t PLLSource;  /*!< RCC_PLLSource: PLL entry clock source.
-                            This parameter must be a value of @ref RCC_PLL_Clock_Source               */
-
-  uint32_t PLLM;       /*!< PLLM: Division factor for PLL VCO input clock.
-                            This parameter must be a number between Min_Data = 2 and Max_Data = 63    */
-
-  uint32_t PLLN;       /*!< PLLN: Multiplication factor for PLL VCO output clock.
-                            This parameter must be a number between Min_Data = 50 and Max_Data = 432  */
-
-  uint32_t PLLP;       /*!< PLLP: Division factor for main system clock (SYSCLK).
-                            This parameter must be a value of @ref RCC_PLLP_Clock_Divider             */
-
-  uint32_t PLLQ;       /*!< PLLQ: Division factor for OTG FS, SDMMC and RNG clocks.
-                            This parameter must be a number between Min_Data = 2 and Max_Data = 15    */
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-  uint32_t PLLR;       /*!< PLLR: Division factor for DSI clock.
-                            This parameter must be a number between Min_Data = 2 and Max_Data = 7    */
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
-}RCC_PLLInitTypeDef;
-
-/**
-  * @brief  PLLI2S Clock structure definition
-  */
-typedef struct
-{
-  uint32_t PLLI2SN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
-                            This parameter must be a number between Min_Data = 50 and Max_Data = 432.
-                            This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
-
-  uint32_t PLLI2SR;    /*!< Specifies the division factor for I2S clock.
-                            This parameter must be a number between Min_Data = 2 and Max_Data = 7.
-                            This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
-
-  uint32_t PLLI2SQ;    /*!< Specifies the division factor for SAI1 clock.
-                            This parameter must be a number between Min_Data = 2 and Max_Data = 15.
-                            This parameter will be used only when PLLI2S is selected as Clock Source SAI */
-
-#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \
-    defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-  uint32_t PLLI2SP;    /*!< Specifies the division factor for SPDIF-RX clock.
-                            This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider.
-                            This parameter will be used only when PLLI2S is selected as Clock Source SPDIF-RX */
-#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-}RCC_PLLI2SInitTypeDef;
-
-/**
-  * @brief  PLLSAI Clock structure definition
-  */
-typedef struct
-{
-  uint32_t PLLSAIN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
-                            This parameter must be a number between Min_Data = 50 and Max_Data = 432.
-                            This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
-
-  uint32_t PLLSAIQ;    /*!< Specifies the division factor for SAI1 clock.
-                            This parameter must be a number between Min_Data = 2 and Max_Data = 15.
-                            This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
-
-#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \
-    defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-  uint32_t PLLSAIR;    /*!< specifies the division factor for LTDC clock
-                            This parameter must be a number between Min_Data = 2 and Max_Data = 7.
-                            This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
-#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
-  uint32_t PLLSAIP;    /*!< Specifies the division factor for 48MHz clock.
-                            This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider
-                            This parameter will be used only when PLLSAI is disabled */
-}RCC_PLLSAIInitTypeDef;
-
-/**
-  * @brief  RCC extended clocks structure definition
-  */
-typedef struct
-{
-  uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
-                                      This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
-
-  RCC_PLLI2SInitTypeDef PLLI2S;  /*!< PLL I2S structure parameters.
-                                      This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
-
-  RCC_PLLSAIInitTypeDef PLLSAI;  /*!< PLL SAI structure parameters.
-                                      This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
-
-  uint32_t PLLI2SDivQ;           /*!< Specifies the PLLI2S division factor for SAI1 clock.
-                                      This parameter must be a number between Min_Data = 1 and Max_Data = 32
-                                      This parameter will be used only when PLLI2S is selected as Clock Source SAI */
-
-  uint32_t PLLSAIDivQ;           /*!< Specifies the PLLI2S division factor for SAI1 clock.
-                                      This parameter must be a number between Min_Data = 1 and Max_Data = 32
-                                      This parameter will be used only when PLLSAI is selected as Clock Source SAI */
-
-  uint32_t PLLSAIDivR;           /*!< Specifies the PLLSAI division factor for LTDC clock.
-                                      This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
-
-  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock source Selection.
-                                        This parameter can be a value of @ref RCC_RTC_Clock_Source */
-
-  uint32_t I2sClockSelection;      /*!< Specifies I2S Clock source Selection.
-                                        This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
-
-  uint32_t TIMPresSelection;      /*!< Specifies TIM Clock Prescalers Selection.
-                                       This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */
-
-  uint32_t Sai1ClockSelection;     /*!< Specifies SAI1 Clock Prescalers Selection
-                                        This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
-
-  uint32_t Sai2ClockSelection;     /*!< Specifies SAI2 Clock Prescalers Selection
-                                        This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
-
-  uint32_t Usart1ClockSelection; /*!< USART1 clock source
-                                      This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
-
-  uint32_t Usart2ClockSelection; /*!< USART2 clock source
-                                      This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
-
-  uint32_t Usart3ClockSelection; /*!< USART3 clock source
-                                      This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
-
-  uint32_t Uart4ClockSelection;  /*!< UART4 clock source
-                                      This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
-
-  uint32_t Uart5ClockSelection;  /*!< UART5 clock source
-                                      This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
-
-  uint32_t Usart6ClockSelection;  /*!< USART6 clock source
-                                      This parameter can be a value of @ref RCCEx_USART6_Clock_Source */
-
-  uint32_t Uart7ClockSelection;  /*!< UART7 clock source
-                                      This parameter can be a value of @ref RCCEx_UART7_Clock_Source */
-
-  uint32_t Uart8ClockSelection;  /*!< UART8 clock source
-                                      This parameter can be a value of @ref RCCEx_UART8_Clock_Source */
-
-  uint32_t I2c1ClockSelection;   /*!< I2C1 clock source
-                                      This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
-
-  uint32_t I2c2ClockSelection;   /*!< I2C2 clock source
-                                      This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
-
-  uint32_t I2c3ClockSelection;   /*!< I2C3 clock source
-                                      This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
-
-  uint32_t I2c4ClockSelection;   /*!< I2C4 clock source
-                                      This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */
-
-  uint32_t Lptim1ClockSelection;   /*!< Specifies LPTIM1 clock source
-                                        This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
-
-  uint32_t CecClockSelection;      /*!< CEC clock source
-                                        This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
-
-  uint32_t Clk48ClockSelection;    /*!< Specifies 48Mhz clock source used by USB OTG FS, RNG and SDMMC
-                                        This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
-
-  uint32_t Sdmmc1ClockSelection;     /*!< SDMMC1 clock source
-                                        This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */
-
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-  uint32_t Sdmmc2ClockSelection;     /*!< SDMMC2 clock source
-                                        This parameter can be a value of @ref RCCEx_SDMMC2_Clock_Source */
-
-  uint32_t Dfsdm1ClockSelection;     /*!< DFSDM1 clock source
-                                        This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */
-
-  uint32_t Dfsdm1AudioClockSelection; /*!< DFSDM1 clock source
-                                        This parameter can be a value of @ref RCCEx_DFSDM1_AUDIO_Clock_Source */
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-}RCC_PeriphCLKInitTypeDef;
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
-  * @{
-  */
-
-/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
-  * @{
-  */
-#define RCC_PERIPHCLK_I2S             ((uint32_t)0x00000001U)
-#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define RCC_PERIPHCLK_LTDC            ((uint32_t)0x00000008U)
-#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-#define RCC_PERIPHCLK_TIM             ((uint32_t)0x00000010U)
-#define RCC_PERIPHCLK_RTC             ((uint32_t)0x00000020U)
-#define RCC_PERIPHCLK_USART1          ((uint32_t)0x00000040U)
-#define RCC_PERIPHCLK_USART2          ((uint32_t)0x00000080U)
-#define RCC_PERIPHCLK_USART3          ((uint32_t)0x00000100U)
-#define RCC_PERIPHCLK_UART4           ((uint32_t)0x00000200U)
-#define RCC_PERIPHCLK_UART5           ((uint32_t)0x00000400U)
-#define RCC_PERIPHCLK_USART6          ((uint32_t)0x00000800U)
-#define RCC_PERIPHCLK_UART7           ((uint32_t)0x00001000U)
-#define RCC_PERIPHCLK_UART8           ((uint32_t)0x00002000U)
-#define RCC_PERIPHCLK_I2C1            ((uint32_t)0x00004000U)
-#define RCC_PERIPHCLK_I2C2            ((uint32_t)0x00008000U)
-#define RCC_PERIPHCLK_I2C3            ((uint32_t)0x00010000U)
-#define RCC_PERIPHCLK_I2C4            ((uint32_t)0x00020000U)
-#define RCC_PERIPHCLK_LPTIM1          ((uint32_t)0x00040000U)
-#define RCC_PERIPHCLK_SAI1            ((uint32_t)0x00080000U)
-#define RCC_PERIPHCLK_SAI2            ((uint32_t)0x00100000U)
-#define RCC_PERIPHCLK_CLK48           ((uint32_t)0x00200000U)
-#define RCC_PERIPHCLK_CEC             ((uint32_t)0x00400000U)
-#define RCC_PERIPHCLK_SDMMC1          ((uint32_t)0x00800000U)
-#define RCC_PERIPHCLK_SPDIFRX         ((uint32_t)0x01000000U)
-#define RCC_PERIPHCLK_PLLI2S          ((uint32_t)0x02000000U)
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define RCC_PERIPHCLK_SDMMC2          ((uint32_t)0x04000000U)
-#define RCC_PERIPHCLK_DFSDM1           ((uint32_t)0x08000000U)
-#define RCC_PERIPHCLK_DFSDM1_AUDIO      ((uint32_t)0x10000000U)
-#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
-/**
-  * @}
-  */
-
-#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \
-    defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCCEx PLLI2SP Clock Divider
-  * @{
-  */
-#define RCC_PLLI2SP_DIV2                  ((uint32_t)0x00000000U)
-#define RCC_PLLI2SP_DIV4                  ((uint32_t)0x00000001U)
-#define RCC_PLLI2SP_DIV6                  ((uint32_t)0x00000002U)
-#define RCC_PLLI2SP_DIV8                  ((uint32_t)0x00000003U)
-/**
-  * @}
-  */
-#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
-/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCCEx PLLSAIP Clock Divider
-  * @{
-  */
-#define RCC_PLLSAIP_DIV2                  ((uint32_t)0x00000000U)
-#define RCC_PLLSAIP_DIV4                  ((uint32_t)0x00000001U)
-#define RCC_PLLSAIP_DIV6                  ((uint32_t)0x00000002U)
-#define RCC_PLLSAIP_DIV8                  ((uint32_t)0x00000003U)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_PLLSAI_DIVR RCCEx PLLSAI DIVR
-  * @{
-  */
-#define RCC_PLLSAIDIVR_2                ((uint32_t)0x00000000U)
-#define RCC_PLLSAIDIVR_4                RCC_DCKCFGR1_PLLSAIDIVR_0
-#define RCC_PLLSAIDIVR_8                RCC_DCKCFGR1_PLLSAIDIVR_1
-#define RCC_PLLSAIDIVR_16               RCC_DCKCFGR1_PLLSAIDIVR
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_I2S_Clock_Source RCCEx I2S Clock Source
-  * @{
-  */
-#define RCC_I2SCLKSOURCE_PLLI2S             ((uint32_t)0x00000000U)
-#define RCC_I2SCLKSOURCE_EXT                RCC_CFGR_I2SSRC
-
-/**
-  * @}
-  */
-
-
-/** @defgroup RCCEx_SAI1_Clock_Source RCCEx SAI1 Clock Source
-  * @{
-  */
-#define RCC_SAI1CLKSOURCE_PLLSAI             ((uint32_t)0x00000000U)
-#define RCC_SAI1CLKSOURCE_PLLI2S             RCC_DCKCFGR1_SAI1SEL_0
-#define RCC_SAI1CLKSOURCE_PIN                RCC_DCKCFGR1_SAI1SEL_1
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define RCC_SAI1CLKSOURCE_PLLSRC             RCC_DCKCFGR1_SAI1SEL
-#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_SAI2_Clock_Source RCCEx SAI2 Clock Source
-  * @{
-  */
-#define RCC_SAI2CLKSOURCE_PLLSAI             ((uint32_t)0x00000000U)
-#define RCC_SAI2CLKSOURCE_PLLI2S             RCC_DCKCFGR1_SAI2SEL_0
-#define RCC_SAI2CLKSOURCE_PIN                RCC_DCKCFGR1_SAI2SEL_1
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define RCC_SAI2CLKSOURCE_PLLSRC             RCC_DCKCFGR1_SAI2SEL
-#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source
-  * @{
-  */
-#define RCC_CECCLKSOURCE_LSE             ((uint32_t)0x00000000U)
-#define RCC_CECCLKSOURCE_HSI             RCC_DCKCFGR2_CECSEL /* CEC clock is HSI/488*/
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source
-  * @{
-  */
-#define RCC_USART1CLKSOURCE_PCLK2      ((uint32_t)0x00000000U)
-#define RCC_USART1CLKSOURCE_SYSCLK     RCC_DCKCFGR2_USART1SEL_0
-#define RCC_USART1CLKSOURCE_HSI        RCC_DCKCFGR2_USART1SEL_1
-#define RCC_USART1CLKSOURCE_LSE        RCC_DCKCFGR2_USART1SEL
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
-  * @{
-  */
-#define RCC_USART2CLKSOURCE_PCLK1       ((uint32_t)0x00000000U)
-#define RCC_USART2CLKSOURCE_SYSCLK     RCC_DCKCFGR2_USART2SEL_0
-#define RCC_USART2CLKSOURCE_HSI        RCC_DCKCFGR2_USART2SEL_1
-#define RCC_USART2CLKSOURCE_LSE        RCC_DCKCFGR2_USART2SEL
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source
-  * @{
-  */
-#define RCC_USART3CLKSOURCE_PCLK1       ((uint32_t)0x00000000U)
-#define RCC_USART3CLKSOURCE_SYSCLK     RCC_DCKCFGR2_USART3SEL_0
-#define RCC_USART3CLKSOURCE_HSI        RCC_DCKCFGR2_USART3SEL_1
-#define RCC_USART3CLKSOURCE_LSE        RCC_DCKCFGR2_USART3SEL
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_UART4_Clock_Source RCCEx UART4 Clock Source
-  * @{
-  */
-#define RCC_UART4CLKSOURCE_PCLK1        ((uint32_t)0x00000000U)
-#define RCC_UART4CLKSOURCE_SYSCLK       RCC_DCKCFGR2_UART4SEL_0
-#define RCC_UART4CLKSOURCE_HSI          RCC_DCKCFGR2_UART4SEL_1
-#define RCC_UART4CLKSOURCE_LSE          RCC_DCKCFGR2_UART4SEL
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_UART5_Clock_Source RCCEx UART5 Clock Source
-  * @{
-  */
-#define RCC_UART5CLKSOURCE_PCLK1        ((uint32_t)0x00000000U)
-#define RCC_UART5CLKSOURCE_SYSCLK       RCC_DCKCFGR2_UART5SEL_0
-#define RCC_UART5CLKSOURCE_HSI          RCC_DCKCFGR2_UART5SEL_1
-#define RCC_UART5CLKSOURCE_LSE          RCC_DCKCFGR2_UART5SEL
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_USART6_Clock_Source RCCEx USART6 Clock Source
-  * @{
-  */
-#define RCC_USART6CLKSOURCE_PCLK2       ((uint32_t)0x00000000U)
-#define RCC_USART6CLKSOURCE_SYSCLK      RCC_DCKCFGR2_USART6SEL_0
-#define RCC_USART6CLKSOURCE_HSI         RCC_DCKCFGR2_USART6SEL_1
-#define RCC_USART6CLKSOURCE_LSE         RCC_DCKCFGR2_USART6SEL
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_UART7_Clock_Source RCCEx UART7 Clock Source
-  * @{
-  */
-#define RCC_UART7CLKSOURCE_PCLK1       ((uint32_t)0x00000000U)
-#define RCC_UART7CLKSOURCE_SYSCLK      RCC_DCKCFGR2_UART7SEL_0
-#define RCC_UART7CLKSOURCE_HSI         RCC_DCKCFGR2_UART7SEL_1
-#define RCC_UART7CLKSOURCE_LSE         RCC_DCKCFGR2_UART7SEL
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_UART8_Clock_Source RCCEx UART8 Clock Source
-  * @{
-  */
-#define RCC_UART8CLKSOURCE_PCLK1        ((uint32_t)0x00000000U)
-#define RCC_UART8CLKSOURCE_SYSCLK      RCC_DCKCFGR2_UART8SEL_0
-#define RCC_UART8CLKSOURCE_HSI         RCC_DCKCFGR2_UART8SEL_1
-#define RCC_UART8CLKSOURCE_LSE         RCC_DCKCFGR2_UART8SEL
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source
-  * @{
-  */
-#define RCC_I2C1CLKSOURCE_PCLK1        ((uint32_t)0x00000000U)
-#define RCC_I2C1CLKSOURCE_SYSCLK       RCC_DCKCFGR2_I2C1SEL_0
-#define RCC_I2C1CLKSOURCE_HSI          RCC_DCKCFGR2_I2C1SEL_1
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_I2C2_Clock_Source RCCEx I2C2 Clock Source
-  * @{
-  */
-#define RCC_I2C2CLKSOURCE_PCLK1        ((uint32_t)0x00000000U)
-#define RCC_I2C2CLKSOURCE_SYSCLK       RCC_DCKCFGR2_I2C2SEL_0
-#define RCC_I2C2CLKSOURCE_HSI          RCC_DCKCFGR2_I2C2SEL_1
-
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source
-  * @{
-  */
-#define RCC_I2C3CLKSOURCE_PCLK1        ((uint32_t)0x00000000U)
-#define RCC_I2C3CLKSOURCE_SYSCLK       RCC_DCKCFGR2_I2C3SEL_0
-#define RCC_I2C3CLKSOURCE_HSI          RCC_DCKCFGR2_I2C3SEL_1
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_I2C4_Clock_Source RCCEx I2C4 Clock Source
-  * @{
-  */
-#define RCC_I2C4CLKSOURCE_PCLK1        ((uint32_t)0x00000000U)
-#define RCC_I2C4CLKSOURCE_SYSCLK       RCC_DCKCFGR2_I2C4SEL_0
-#define RCC_I2C4CLKSOURCE_HSI          RCC_DCKCFGR2_I2C4SEL_1
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source
-  * @{
-  */
-#define RCC_LPTIM1CLKSOURCE_PCLK       ((uint32_t)0x00000000U)
-#define RCC_LPTIM1CLKSOURCE_LSI        RCC_DCKCFGR2_LPTIM1SEL_0
-#define RCC_LPTIM1CLKSOURCE_HSI        RCC_DCKCFGR2_LPTIM1SEL_1
-#define RCC_LPTIM1CLKSOURCE_LSE        RCC_DCKCFGR2_LPTIM1SEL
-
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_CLK48_Clock_Source RCCEx CLK48 Clock Source
-  * @{
-  */
-#define RCC_CLK48SOURCE_PLL         ((uint32_t)0x00000000U)
-#define RCC_CLK48SOURCE_PLLSAIP     RCC_DCKCFGR2_CK48MSEL
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection
-  * @{
-  */
-#define RCC_TIMPRES_DESACTIVATED        ((uint32_t)0x00000000U)
-#define RCC_TIMPRES_ACTIVATED           RCC_DCKCFGR1_TIMPRE
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_SDMMC1_Clock_Source RCCEx SDMMC1 Clock Source
-  * @{
-  */
-#define RCC_SDMMC1CLKSOURCE_CLK48              ((uint32_t)0x00000000U)
-#define RCC_SDMMC1CLKSOURCE_SYSCLK             RCC_DCKCFGR2_SDMMC1SEL
-/**
-  * @}
-  */
-
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-/** @defgroup RCCEx_SDMMC2_Clock_Source RCCEx SDMMC2 Clock Source
-  * @{
-  */
-#define RCC_SDMMC2CLKSOURCE_CLK48              ((uint32_t)0x00000000U)
-#define RCC_SDMMC2CLKSOURCE_SYSCLK             RCC_DCKCFGR2_SDMMC2SEL
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source  RCCEx DFSDM1 Kernel Clock Source
-  * @{
-  */
-#define RCC_DFSDM1CLKSOURCE_PCLK             ((uint32_t)0x00000000U)
-#define RCC_DFSDM1CLKSOURCE_SYSCLK           RCC_DCKCFGR1_DFSDM1SEL
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_DFSDM1_AUDIO_Clock_Source RCCEx DFSDM1 AUDIO Clock Source
-  * @{
-  */
-#define RCC_DFSDM1AUDIOCLKSOURCE_SAI1        ((uint32_t)0x00000000U)
-#define RCC_DFSDM1AUDIOCLKSOURCE_SAI2        RCC_DCKCFGR1_ADFSDM1SEL
-/**
-  * @}
-  */
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
-#if defined (STM32F769xx) || defined (STM32F779xx)
-/** @defgroup RCCEx_DSI_Clock_Source  RCC DSI Clock Source
-  * @{
-  */
-#define RCC_DSICLKSOURCE_DSIPHY             ((uint32_t)0x00000000U)
-#define RCC_DSICLKSOURCE_PLLR               ((uint32_t)RCC_DCKCFGR2_DSISEL)
-/**
-  * @}
-  */
-#endif /* STM32F769xx || STM32F779xx */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
-  * @{
-  */
-/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
-  * @brief  Enables or disables the AHB/APB peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-
-/** @brief  Enables or disables the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  */
-#define __HAL_RCC_BKPSRAM_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_DTCMRAMEN_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_DMA2_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_DMA2D_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_GPIOA_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_GPIOB_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_GPIOC_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_GPIOF_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_GPIOG_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_GPIOH_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_GPIOI_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_GPIOJ_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_GPIOK_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_BKPSRAM_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
-#define __HAL_RCC_DTCMRAMEN_CLK_DISABLE()       (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN))
-#define __HAL_RCC_DMA2_CLK_DISABLE()            (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
-#define __HAL_RCC_DMA2D_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
-#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()      (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
-#define __HAL_RCC_GPIOA_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
-#define __HAL_RCC_GPIOB_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
-#define __HAL_RCC_GPIOC_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
-#define __HAL_RCC_GPIOD_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
-#define __HAL_RCC_GPIOE_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
-#define __HAL_RCC_GPIOF_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
-#define __HAL_RCC_GPIOG_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
-#define __HAL_RCC_GPIOH_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
-#define __HAL_RCC_GPIOI_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
-#define __HAL_RCC_GPIOJ_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
-#define __HAL_RCC_GPIOK_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
-/**
-  * @brief  Enable ETHERNET clock.
-  */
-#define __HAL_RCC_ETHMAC_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_ETHMACTX_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_ETHMACRX_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_ETHMACPTP_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_ETH_CLK_ENABLE()       do {                            \
-                                     __HAL_RCC_ETHMAC_CLK_ENABLE();      \
-                                     __HAL_RCC_ETHMACTX_CLK_ENABLE();    \
-                                     __HAL_RCC_ETHMACRX_CLK_ENABLE();    \
-                                    } while(0)
-/**
-  * @brief  Disable ETHERNET clock.
-  */
-#define __HAL_RCC_ETHMAC_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
-#define __HAL_RCC_ETHMACTX_CLK_DISABLE()  (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
-#define __HAL_RCC_ETHMACRX_CLK_DISABLE()  (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
-#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
-#define __HAL_RCC_ETH_CLK_DISABLE()       do {                             \
-                                      __HAL_RCC_ETHMACTX_CLK_DISABLE();    \
-                                      __HAL_RCC_ETHMACRX_CLK_DISABLE();    \
-                                      __HAL_RCC_ETHMAC_CLK_DISABLE();      \
-                                     } while(0)
-
-/** @brief  Enable or disable the AHB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  */
-#define __HAL_RCC_DCMI_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define __HAL_RCC_JPEG_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#define __HAL_RCC_JPEG_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_JPEGEN))
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
-#define __HAL_RCC_RNG_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
-                                        UNUSED(tmpreg); \
-                                        __HAL_RCC_SYSCFG_CLK_ENABLE();\
-                                      } while(0)
-
-#define __HAL_RCC_DCMI_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
-#define __HAL_RCC_RNG_CLK_DISABLE()   (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
-
-#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
-#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define __HAL_RCC_CRYP_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_HASH_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_CRYP_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
-#define __HAL_RCC_HASH_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
-#endif /* STM32F756x || STM32F777xx || STM32F779xx */
-
-/** @brief  Enables or disables the AHB3 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  */
-#define __HAL_RCC_FMC_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_QSPI_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_FMC_CLK_DISABLE()   (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
-#define __HAL_RCC_QSPI_CLK_DISABLE()  (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
-
-/** @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  */
-#define __HAL_RCC_TIM2_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_TIM3_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_TIM4_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_TIM5_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_TIM7_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_TIM12_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_TIM13_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_TIM14_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_LPTIM1_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define __HAL_RCC_RTC_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_CAN3_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
-#define __HAL_RCC_SPI2_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_SPI3_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_SPDIFRX_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_USART2_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_USART3_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_UART4_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_UART5_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_I2C1_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_I2C2_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_I2C3_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_I2C4_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_CAN1_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_CAN2_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_CEC_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_DAC_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_UART7_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_UART8_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
-#define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
-#define __HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
-#define __HAL_RCC_TIM5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
-#define __HAL_RCC_TIM6_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
-#define __HAL_RCC_TIM7_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
-#define __HAL_RCC_TIM12_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
-#define __HAL_RCC_TIM13_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
-#define __HAL_RCC_TIM14_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
-#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define __HAL_RCC_RTC_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCEN))
-#define __HAL_RCC_CAN3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN))
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-#define __HAL_RCC_SPI2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
-#define __HAL_RCC_SPI3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
-#define __HAL_RCC_SPDIFRX_CLK_DISABLE()(RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
-#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
-#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
-#define __HAL_RCC_UART4_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
-#define __HAL_RCC_UART5_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
-#define __HAL_RCC_I2C1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
-#define __HAL_RCC_I2C2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
-#define __HAL_RCC_I2C3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
-#define __HAL_RCC_I2C4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN))
-#define __HAL_RCC_CAN1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
-#define __HAL_RCC_CAN2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
-#define __HAL_RCC_CEC_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
-#define __HAL_RCC_DAC_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
-#define __HAL_RCC_UART7_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
-#define __HAL_RCC_UART8_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
-
-/** @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  */
-#define __HAL_RCC_TIM1_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_TIM8_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_USART1_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_USART6_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define __HAL_RCC_SDMMC2_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
-#define __HAL_RCC_ADC1_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_ADC2_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_ADC3_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_SDMMC1_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_SPI1_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_SPI4_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_TIM9_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_TIM10_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_TIM11_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_SPI5_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_SPI6_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_SAI1_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_SAI2_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define __HAL_RCC_LTDC_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
-#if defined (STM32F769xx) || defined (STM32F779xx)
-#define __HAL_RCC_DSI_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#endif /* STM32F769xx || STM32F779xx */
-
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define __HAL_RCC_DFSDM1_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-
-#define __HAL_RCC_MDIO_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0)
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
-#define __HAL_RCC_TIM1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
-#define __HAL_RCC_TIM8_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
-#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
-#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC2EN))
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-#define __HAL_RCC_ADC1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
-#define __HAL_RCC_ADC2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
-#define __HAL_RCC_ADC3_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
-#define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN))
-#define __HAL_RCC_SPI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
-#define __HAL_RCC_SPI4_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
-#define __HAL_RCC_TIM9_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
-#define __HAL_RCC_TIM10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
-#define __HAL_RCC_TIM11_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
-#define __HAL_RCC_SPI5_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
-#define __HAL_RCC_SPI6_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
-#define __HAL_RCC_SAI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
-#define __HAL_RCC_SAI2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
-#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define __HAL_RCC_LTDC_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
-#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-#if defined (STM32F769xx) || defined (STM32F779xx)
-#define __HAL_RCC_DSI_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN))
-#endif /* STM32F769xx || STM32F779xx */
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define __HAL_RCC_DFSDM1_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN))
-#define __HAL_RCC_MDIO_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_MDIOEN))
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
-/**
-  * @}
-  */
-
-
-/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB/APB peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-
-/** @brief  Get the enable or disable status of the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  */
-#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED()          ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
-#define __HAL_RCC_DTCMRAMEN_IS_CLK_ENABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) != RESET)
-#define __HAL_RCC_DMA2_IS_CLK_ENABLED()             ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET)
-#define __HAL_RCC_DMA2D_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET)
-#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
-#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
-#define __HAL_RCC_GPIOA_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) != RESET)
-#define __HAL_RCC_GPIOB_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) != RESET)
-#define __HAL_RCC_GPIOC_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) != RESET)
-#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
-#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
-#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
-#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
-#define __HAL_RCC_GPIOH_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET)
-#define __HAL_RCC_GPIOI_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
-#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET)
-#define __HAL_RCC_GPIOK_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)
-
-#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED()         ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
-#define __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET)
-#define __HAL_RCC_DMA2_IS_CLK_DISABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) == RESET)
-#define __HAL_RCC_DMA2D_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET)
-#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED()      ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
-#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
-#define __HAL_RCC_GPIOA_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) == RESET)
-#define __HAL_RCC_GPIOB_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) == RESET)
-#define __HAL_RCC_GPIOC_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) == RESET)
-#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
-#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
-#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
-#define __HAL_RCC_GPIOG_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
-#define __HAL_RCC_GPIOH_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET)
-#define __HAL_RCC_GPIOI_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
-#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET)
-#define __HAL_RCC_GPIOK_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)
-/**
-  * @brief  Enable ETHERNET clock.
-  */
-#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
-#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
-#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
-#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
-#define __HAL_RCC_ETH_IS_CLK_ENABLED()        (__HAL_RCC_ETHMAC_IS_CLK_ENABLED()   && \
-                                               __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
-                                               __HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
-
-/**
-  * @brief  Disable ETHERNET clock.
-  */
-#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
-#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
-#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
-#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
-#define __HAL_RCC_ETH_IS_CLK_DISABLED()        (__HAL_RCC_ETHMAC_IS_CLK_DISABLED()   && \
-                                                __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
-                                                __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
-
-/** @brief  Get the enable or disable status of the AHB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  */
-#define __HAL_RCC_DCMI_IS_CLK_ENABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
-#define __HAL_RCC_RNG_IS_CLK_ENABLED()         ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
-
-#define __HAL_RCC_DCMI_IS_CLK_DISABLED()       ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
-#define __HAL_RCC_RNG_IS_CLK_DISABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
-#define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
-
-#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define __HAL_RCC_CRYP_IS_CLK_ENABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
-#define __HAL_RCC_HASH_IS_CLK_ENABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
-#define __HAL_RCC_CRYP_IS_CLK_DISABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
-#define __HAL_RCC_HASH_IS_CLK_DISABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
-#endif /* STM32F756xx || STM32F777xx || STM32F779xx */
-
-#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define __HAL_RCC_JPEG_IS_CLK_ENABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) != RESET)
-#define __HAL_RCC_JPEG_IS_CLK_DISABLED()       ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) == RESET)
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
-/** @brief  Get the enable or disable status of the AHB3 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  */
-#define __HAL_RCC_FMC_IS_CLK_ENABLED()   ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
-#define __HAL_RCC_QSPI_IS_CLK_ENABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
-
-#define __HAL_RCC_FMC_IS_CLK_DISABLED()   ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
-#define __HAL_RCC_QSPI_IS_CLK_DISABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
-
-/** @brief  Get the enable or disable status of the APB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  */
-#define __HAL_RCC_TIM2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
-#define __HAL_RCC_TIM3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
-#define __HAL_RCC_TIM4_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
-#define __HAL_RCC_TIM5_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
-#define __HAL_RCC_TIM6_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
-#define __HAL_RCC_TIM7_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
-#define __HAL_RCC_TIM12_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
-#define __HAL_RCC_TIM13_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
-#define __HAL_RCC_TIM14_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
-#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define __HAL_RCC_RTC_IS_CLK_ENABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) != RESET)
-#define __HAL_RCC_CAN3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET)
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-#define __HAL_RCC_SPI2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
-#define __HAL_RCC_SPI3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
-#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)
-#define __HAL_RCC_USART2_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
-#define __HAL_RCC_USART3_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
-#define __HAL_RCC_UART4_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
-#define __HAL_RCC_UART5_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
-#define __HAL_RCC_I2C1_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
-#define __HAL_RCC_I2C2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
-#define __HAL_RCC_I2C3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
-#define __HAL_RCC_I2C4_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) != RESET)
-#define __HAL_RCC_CAN1_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
-#define __HAL_RCC_CAN2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
-#define __HAL_RCC_CEC_IS_CLK_ENABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
-#define __HAL_RCC_DAC_IS_CLK_ENABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
-#define __HAL_RCC_UART7_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
-#define __HAL_RCC_UART8_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
-
-#define __HAL_RCC_TIM2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
-#define __HAL_RCC_TIM3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
-#define __HAL_RCC_TIM4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
-#define __HAL_RCC_TIM5_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
-#define __HAL_RCC_TIM6_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
-#define __HAL_RCC_TIM7_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
-#define __HAL_RCC_TIM12_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
-#define __HAL_RCC_TIM13_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
-#define __HAL_RCC_TIM14_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
-#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define __HAL_RCC_RTC_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) == RESET)
-#define __HAL_RCC_CAN3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET)
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-#define __HAL_RCC_SPI2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
-#define __HAL_RCC_SPI3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
-#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED()((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)
-#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
-#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
-#define __HAL_RCC_UART4_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
-#define __HAL_RCC_UART5_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
-#define __HAL_RCC_I2C1_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
-#define __HAL_RCC_I2C2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
-#define __HAL_RCC_I2C3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
-#define __HAL_RCC_I2C4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET)
-#define __HAL_RCC_CAN1_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
-#define __HAL_RCC_CAN2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
-#define __HAL_RCC_CEC_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
-#define __HAL_RCC_DAC_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
-#define __HAL_RCC_UART7_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
-#define __HAL_RCC_UART8_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
-
-/** @brief  Get the enable or disable status of the APB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  */
-#define __HAL_RCC_TIM1_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
-#define __HAL_RCC_TIM8_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
-#define __HAL_RCC_USART1_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
-#define __HAL_RCC_USART6_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
-#define __HAL_RCC_ADC1_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
-#define __HAL_RCC_ADC2_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
-#define __HAL_RCC_ADC3_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
-#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) != RESET)
-#define __HAL_RCC_SPI1_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
-#define __HAL_RCC_SPI4_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
-#define __HAL_RCC_TIM9_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
-#define __HAL_RCC_TIM10_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
-#define __HAL_RCC_TIM11_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
-#define __HAL_RCC_SPI5_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
-#define __HAL_RCC_SPI6_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)
-#define __HAL_RCC_SAI1_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
-#define __HAL_RCC_SAI2_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)
-#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define __HAL_RCC_LTDC_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET)
-#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-#if defined (STM32F769xx) || defined (STM32F779xx)
-#define __HAL_RCC_DSI_IS_CLK_ENABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET)
-#endif /* STM32F769xx || STM32F779xx */
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define __HAL_RCC_SDMMC2_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) != RESET)
-#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET)
-#define __HAL_RCC_MDIO_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) != RESET)
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-#define __HAL_RCC_TIM1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
-#define __HAL_RCC_TIM8_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
-#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
-#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
-#define __HAL_RCC_ADC1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
-#define __HAL_RCC_ADC2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
-#define __HAL_RCC_ADC3_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
-#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) == RESET)
-#define __HAL_RCC_SPI1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
-#define __HAL_RCC_SPI4_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
-#define __HAL_RCC_TIM9_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
-#define __HAL_RCC_TIM10_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
-#define __HAL_RCC_TIM11_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
-#define __HAL_RCC_SPI5_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
-#define __HAL_RCC_SPI6_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)
-#define __HAL_RCC_SAI1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
-#define __HAL_RCC_SAI2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)
-#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define __HAL_RCC_LTDC_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET)
-#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-#if defined (STM32F769xx) || defined (STM32F779xx)
-#define __HAL_RCC_DSI_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET)
-#endif /* STM32F769xx || STM32F779xx */
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) == RESET)
-#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET)
-#define __HAL_RCC_MDIO_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) == RESET)
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
-  * @brief  Forces or releases AHB/APB peripheral reset.
-  * @{
-  */
-
-/** @brief  Force or release AHB1 peripheral reset.
-  */
-#define __HAL_RCC_DMA2_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
-#define __HAL_RCC_DMA2D_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))
-#define __HAL_RCC_ETHMAC_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
-#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
-#define __HAL_RCC_GPIOA_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
-#define __HAL_RCC_GPIOB_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
-#define __HAL_RCC_GPIOC_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
-#define __HAL_RCC_GPIOD_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
-#define __HAL_RCC_GPIOE_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
-#define __HAL_RCC_GPIOF_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
-#define __HAL_RCC_GPIOG_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
-#define __HAL_RCC_GPIOH_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
-#define __HAL_RCC_GPIOI_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
-#define __HAL_RCC_GPIOJ_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))
-#define __HAL_RCC_GPIOK_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))
-
-#define __HAL_RCC_DMA2_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
-#define __HAL_RCC_DMA2D_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
-#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
-#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
-#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
-#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
-#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
-#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
-#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
-#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
-#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
-#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
-#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
-#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
-#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
-
-/** @brief  Force or release AHB2 peripheral reset.
-  */
-#define __HAL_RCC_AHB2_FORCE_RESET()    (RCC->AHB2RSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_DCMI_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
-#define __HAL_RCC_RNG_FORCE_RESET()    (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
-#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
-
-#define __HAL_RCC_AHB2_RELEASE_RESET()  (RCC->AHB2RSTR = 0x00U)
-#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
-#define __HAL_RCC_RNG_RELEASE_RESET()  (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
-#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
-
-#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define __HAL_RCC_JPEG_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_JPEGRST))
-#define __HAL_RCC_JPEG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_JPEGRST))
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
-#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define __HAL_RCC_CRYP_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
-#define __HAL_RCC_HASH_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
-#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
-#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
-#endif /* STM32F756xx || STM32F777xx || STM32F779xx */
-
-/** @brief  Force or release AHB3 peripheral reset
-  */
-#define __HAL_RCC_AHB3_FORCE_RESET()   (RCC->AHB3RSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_FMC_FORCE_RESET()    (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
-#define __HAL_RCC_QSPI_FORCE_RESET()   (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
-
-#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
-#define __HAL_RCC_FMC_RELEASE_RESET()  (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
-#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
-
-/** @brief  Force or release APB1 peripheral reset.
-  */
-#define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
-#define __HAL_RCC_TIM5_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
-#define __HAL_RCC_TIM6_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_TIM7_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
-#define __HAL_RCC_TIM12_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
-#define __HAL_RCC_TIM13_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
-#define __HAL_RCC_TIM14_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
-#define __HAL_RCC_LPTIM1_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define __HAL_RCC_CAN3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN3RST))
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-#define __HAL_RCC_SPI2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
-#define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_SPDIFRX_FORCE_RESET()  (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST))
-#define __HAL_RCC_USART2_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
-#define __HAL_RCC_USART3_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
-#define __HAL_RCC_UART4_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
-#define __HAL_RCC_UART5_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
-#define __HAL_RCC_I2C1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
-#define __HAL_RCC_I2C2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
-#define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
-#define __HAL_RCC_I2C4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C4RST))
-#define __HAL_RCC_CAN1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
-#define __HAL_RCC_CAN2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
-#define __HAL_RCC_CEC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
-#define __HAL_RCC_DAC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
-#define __HAL_RCC_UART7_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
-#define __HAL_RCC_UART8_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
-
-#define __HAL_RCC_TIM2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
-#define __HAL_RCC_TIM5_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
-#define __HAL_RCC_TIM6_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_TIM7_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
-#define __HAL_RCC_TIM12_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
-#define __HAL_RCC_TIM13_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
-#define __HAL_RCC_TIM14_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
-#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define __HAL_RCC_CAN3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST))
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-#define __HAL_RCC_SPI2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
-#define __HAL_RCC_SPI3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_SPDIFRX_RELEASE_RESET()(RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
-#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
-#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
-#define __HAL_RCC_UART4_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
-#define __HAL_RCC_UART5_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
-#define __HAL_RCC_I2C1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
-#define __HAL_RCC_I2C2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
-#define __HAL_RCC_I2C3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
-#define __HAL_RCC_I2C4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C4RST))
-#define __HAL_RCC_CAN1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
-#define __HAL_RCC_CAN2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
-#define __HAL_RCC_CEC_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
-#define __HAL_RCC_DAC_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
-#define __HAL_RCC_UART7_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
-#define __HAL_RCC_UART8_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
-
-/** @brief  Force or release APB2 peripheral reset.
-  */
-#define __HAL_RCC_TIM1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
-#define __HAL_RCC_TIM8_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
-#define __HAL_RCC_USART1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
-#define __HAL_RCC_USART6_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
-#define __HAL_RCC_ADC_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
-#define __HAL_RCC_SDMMC1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC1RST))
-#define __HAL_RCC_SPI1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
-#define __HAL_RCC_SPI4_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
-#define __HAL_RCC_TIM9_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
-#define __HAL_RCC_TIM10_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
-#define __HAL_RCC_TIM11_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
-#define __HAL_RCC_SPI5_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
-#define __HAL_RCC_SPI6_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
-#define __HAL_RCC_SAI1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
-#define __HAL_RCC_SAI2_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST))
-#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define __HAL_RCC_LTDC_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))
-#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
-#define __HAL_RCC_TIM1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
-#define __HAL_RCC_TIM8_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
-#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
-#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
-#define __HAL_RCC_ADC_RELEASE_RESET()    (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
-#define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC1RST))
-#define __HAL_RCC_SPI1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
-#define __HAL_RCC_SPI4_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
-#define __HAL_RCC_TIM9_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
-#define __HAL_RCC_TIM10_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
-#define __HAL_RCC_TIM11_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
-#define __HAL_RCC_SPI5_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
-#define __HAL_RCC_SPI6_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
-#define __HAL_RCC_SAI1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
-#define __HAL_RCC_SAI2_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))
-#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define __HAL_RCC_LTDC_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
-#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
-#if defined (STM32F769xx) || defined (STM32F779xx)
-#define __HAL_RCC_DSI_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST))
-#define __HAL_RCC_DSI_RELEASE_RESET()    (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST))
-#endif /* STM32F769xx || STM32F779xx */
-
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define __HAL_RCC_SDMMC2_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC2RST))
-#define __HAL_RCC_DFSDM1_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST))
-#define __HAL_RCC_MDIO_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_MDIORST))
-
-#define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC2RST))
-#define __HAL_RCC_DFSDM1_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST))
-#define __HAL_RCC_MDIO_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_MDIORST))
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable
-  * @brief  Enables or disables the AHB/APB peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-
-/** @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
-  */
-#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
-#define __HAL_RCC_AXI_CLK_SLEEP_ENABLE()        (RCC->AHB1LPENR |= (RCC_AHB1LPENR_AXILPEN))
-#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
-#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
-#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
-#define __HAL_RCC_DTCM_CLK_SLEEP_ENABLE()       (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DTCMLPEN))
-#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE()       (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
-#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))
-#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE()     (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
-#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE()   (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
-#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE()   (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
-#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
-#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
-#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
-#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
-#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
-#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
-#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
-#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
-#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
-#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
-#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
-#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))
-#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))
-
-#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
-#define __HAL_RCC_AXI_CLK_SLEEP_DISABLE()       (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_AXILPEN))
-#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
-#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
-#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
-#define __HAL_RCC_DTCM_CLK_SLEEP_DISABLE()      (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DTCMLPEN))
-#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE()      (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
-#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
-#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE()    (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
-#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE()  (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
-#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE()  (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
-#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
-#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()      (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
-#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
-#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
-#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
-#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
-#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
-#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
-#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
-#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
-#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
-#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
-#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
-
-/** @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  */
-#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()        (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
-#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE()       (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
-
-#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE()        (RCC->AHB2LPENR |= (RCC_AHB2LPENR_JPEGLPEN))
-#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE()       (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_JPEGLPEN))
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
-#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()         (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
-#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()        (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
-
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
-
-#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE()        (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
-#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE()        (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
-
-#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE()       (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
-#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE()       (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
-#endif /* STM32F756xx || STM32F777xx || STM32F779xx */
-
-/** @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  */
-#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
-#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
-
-#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
-#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
-
-/** @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  */
-#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
-#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
-#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
-#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
-#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
-#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
-#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
-#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
-#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
-#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN))
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define __HAL_RCC_RTC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCLPEN))
-#define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN3LPEN))
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
-#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
-#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN))
-#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
-#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
-#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
-#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
-#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
-#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
-#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
-#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C4LPEN))
-#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
-#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
-#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN))
-#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
-#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
-#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
-
-#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
-#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
-#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
-#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
-#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
-#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
-#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
-#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
-#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
-#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define __HAL_RCC_RTC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCLPEN))
-#define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN))
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
-#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
-#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
-#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
-#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
-#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
-#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
-#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
-#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
-#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
-#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C4LPEN))
-#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
-#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
-#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
-#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
-#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
-#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
-
-/** @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  */
-#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
-#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
-#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
-#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
-#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
-#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
-#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC1LPEN))
-#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
-#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
-#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
-#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
-#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
-#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
-#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))
-#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
-#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN))
-#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))
-#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
-#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
-#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
-#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
-#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
-#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
-#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
-#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC1LPEN))
-#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
-#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
-#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
-#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
-#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
-#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
-#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
-#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
-#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
-#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
-#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-#if defined (STM32F769xx) || defined (STM32F779xx)
-#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE()     (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN))
-#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN))
-#endif /* STM32F769xx || STM32F779xx */
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC2LPEN))
-#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN))
-#define __HAL_RCC_MDIO_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_MDIOLPEN))
-
-#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC2LPEN))
-#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN))
-#define __HAL_RCC_MDIO_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_MDIOLPEN))
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Clock_Sleep_Enable_Disable_Status AHB/APB Peripheral Clock Sleep Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB/APB peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-
-/** @brief  Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  */
-#define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) != RESET)
-#define __HAL_RCC_AXI_IS_CLK_SLEEP_ENABLED()        ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) != RESET)
-#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) != RESET)
-#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) != RESET)
-#define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_ENABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) != RESET)
-#define __HAL_RCC_DTCM_IS_CLK_SLEEP_ENABLED()       ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) != RESET)
-#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED()       ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != RESET)
-#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET)
-#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET)
-#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED()   ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET)
-#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_ENABLED()   ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) != RESET)
-#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_ENABLED()  ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) != RESET)
-#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) != RESET)
-#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) != RESET)
-#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) != RESET)
-#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) != RESET)
-#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) != RESET)
-#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) != RESET)
-#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) != RESET)
-#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) != RESET)
-#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) != RESET)
-#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) != RESET)
-#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) != RESET)
-#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) != RESET)
-#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) != RESET)
-
-#define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) == RESET)
-#define __HAL_RCC_AXI_IS_CLK_SLEEP_DISABLED()       ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) == RESET)
-#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) == RESET)
-#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) == RESET)
-#define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_DISABLED()   ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) == RESET)
-#define __HAL_RCC_DTCM_IS_CLK_SLEEP_DISABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) == RESET)
-#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == RESET)
-#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) == RESET)
-#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_DISABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) == RESET)
-#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_DISABLED()  ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) == RESET)
-#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_DISABLED()  ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) == RESET)
-#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET)
-#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) == RESET)
-#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) == RESET)
-#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) == RESET)
-#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) == RESET)
-#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) == RESET)
-#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) == RESET)
-#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) == RESET)
-#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) == RESET)
-#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) == RESET)
-#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) == RESET)
-#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) == RESET)
-#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) == RESET)
-#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) == RESET)
-
-/** @brief  Get the enable or disable status of the AHB2 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  */
-#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED()        ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET)
-#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED()       ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET)
-
-#if defined(STM32F767xx) || defined(STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define __HAL_RCC_JPEG_IS_CLK_SLEEP_ENABLED()        ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) != RESET)
-#define __HAL_RCC_JPEG_IS_CLK_SLEEP_DISABLED()       ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) == RESET)
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
-#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED()         ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET)
-#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED()        ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET)
-
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED()  ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET)
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET)
-
-#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED()        ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != RESET)
-#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED()        ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != RESET)
-
-#define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED()       ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == RESET)
-#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED()       ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == RESET)
-#endif /* STM32F756xx || STM32F777xx || STM32F779xx */
-
-/** @brief  Get the enable or disable status of the AHB3 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  */
-#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED()  ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) != RESET)
-#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) == RESET)
-
-#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED()  ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) != RESET)
-#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) == RESET)
-
-/** @brief  Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  */
-#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != RESET)
-#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != RESET)
-#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != RESET)
-#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != RESET)
-#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != RESET)
-#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != RESET)
-#define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) != RESET)
-#define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) != RESET)
-#define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) != RESET)
-#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET)
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED()     ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) != RESET)
-#define __HAL_RCC_CAN3_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) != RESET)
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET)
-#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET)
-#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET)
-#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != RESET)
-#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != RESET)
-#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != RESET)
-#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != RESET)
-#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != RESET)
-#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != RESET)
-#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) != RESET)
-#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET)
-#define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) != RESET)
-#define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) != RESET)
-#define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED()     ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) != RESET)
-#define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED()     ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != RESET)
-#define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) != RESET)
-#define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) != RESET)
-
-#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == RESET)
-#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == RESET)
-#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == RESET)
-#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == RESET)
-#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == RESET)
-#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == RESET)
-#define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) == RESET)
-#define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) == RESET)
-#define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) == RESET)
-#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET)
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) == RESET)
-#define __HAL_RCC_CAN3_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) == RESET)
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET)
-#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET)
-#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET)
-#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == RESET)
-#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == RESET)
-#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == RESET)
-#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == RESET)
-#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == RESET)
-#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == RESET)
-#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) == RESET)
-#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET)
-#define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) == RESET)
-#define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET)
-#define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET)
-#define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == RESET)
-#define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) == RESET)
-#define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) == RESET)
-
-/** @brief  Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  */
-#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != RESET)
-#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != RESET)
-#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED()  ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != RESET)
-#define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED()  ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != RESET)
-#define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != RESET)
-#define __HAL_RCC_ADC2_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) != RESET)
-#define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) != RESET)
-#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED()  ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) != RESET)
-#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != RESET)
-#define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != RESET)
-#define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != RESET)
-#define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != RESET)
-#define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != RESET)
-#define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != RESET)
-#define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET)
-#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET)
-#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET)
-#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) != RESET)
-#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-#if defined (STM32F769xx) || defined (STM32F779xx)
-#define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED()     ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) != RESET)
-#endif /* STM32F769xx || STM32F779xx */
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED()  ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) != RESET)
-#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != RESET)
-#define __HAL_RCC_MDIO_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) != RESET)
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
-#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET)
-#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET)
-#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == RESET)
-#define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == RESET)
-#define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == RESET)
-#define __HAL_RCC_ADC2_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) == RESET)
-#define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) == RESET)
-#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) == RESET)
-#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == RESET)
-#define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == RESET)
-#define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == RESET)
-#define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED()  ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == RESET)
-#define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED()  ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == RESET)
-#define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == RESET)
-#define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET)
-#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET)
-#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET)
-#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) == RESET)
-#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-#if defined (STM32F769xx) || defined (STM32F779xx)
-#define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED()     ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) == RESET)
-#endif /* STM32F769xx || STM32F779xx */
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED()  ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) == RESET)
-#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == RESET)
-#define __HAL_RCC_MDIO_IS_CLK_SLEEP_DISABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) == RESET)
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-/**
-  * @}
-  */
-
-/*------------------------------- PLL Configuration --------------------------*/
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-/** @brief  Macro to configure the main PLL clock source, multiplication and division factors.
-  * @note   This function must be used only when the main PLL is disabled.
-  * @param  __RCC_PLLSource__: specifies the PLL entry clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
-  *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
-  * @note   This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
-  * @param  __PLLM__: specifies the division factor for PLL VCO input clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
-  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
-  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
-  *         of 2 MHz to limit PLL jitter.
-  * @param  __PLLN__: specifies the multiplication factor for PLL VCO output clock
-  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
-  * @note   You have to set the PLLN parameter correctly to ensure that the VCO
-  *         output frequency is between 100 and 432 MHz.
-  * @param  __PLLP__: specifies the division factor for main system clock (SYSCLK)
-  *         This parameter must be a number in the range {2, 4, 6, or 8}.
-  * @note   You have to set the PLLP parameter correctly to not exceed 216 MHz on
-  *         the System clock frequency.
-  * @param  __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
-  * @note   If the USB OTG FS is used in your application, you have to set the
-  *         PLLQ parameter correctly to have 48 MHz clock for the USB. However,
-  *         the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work
-  *         correctly.
-  * @param  __PLLR__: specifies the division factor for DSI clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
-  */
-#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__)  \
-                            (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__)                   | \
-                            ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN))                      | \
-                            ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP))          | \
-                            ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))                      | \
-                            ((__PLLR__) << POSITION_VAL(RCC_PLLCFGR_PLLR))))
-#else
-/** @brief  Macro to configure the main PLL clock source, multiplication and division factors.
-  * @note   This function must be used only when the main PLL is disabled.
-  * @param  __RCC_PLLSource__: specifies the PLL entry clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
-  *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
-  * @note   This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
-  * @param  __PLLM__: specifies the division factor for PLL VCO input clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
-  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
-  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
-  *         of 2 MHz to limit PLL jitter.
-  * @param  __PLLN__: specifies the multiplication factor for PLL VCO output clock
-  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
-  * @note   You have to set the PLLN parameter correctly to ensure that the VCO
-  *         output frequency is between 100 and 432 MHz.
-  * @param  __PLLP__: specifies the division factor for main system clock (SYSCLK)
-  *         This parameter must be a number in the range {2, 4, 6, or 8}.
-  * @note   You have to set the PLLP parameter correctly to not exceed 216 MHz on
-  *         the System clock frequency.
-  * @param  __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
-  * @note   If the USB OTG FS is used in your application, you have to set the
-  *         PLLQ parameter correctly to have 48 MHz clock for the USB. However,
-  *         the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work
-  *         correctly.
-  */
-#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)     \
-                            (RCC->PLLCFGR = (0x20000000 | (__RCC_PLLSource__) | (__PLLM__)| \
-                            ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN))                | \
-                            ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP))    | \
-                            ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-/*---------------------------------------------------------------------------------------------*/
-
-/** @brief  Macro to configure the Timers clocks prescalers
-  * @param  __PRESC__ : specifies the Timers clocks prescalers selection
-  *         This parameter can be one of the following values:
-  *            @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
-  *                 equal to HPRE if PPREx is corresponding to division by 1 or 2,
-  *                 else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
-  *                 division by 4 or more.
-  *            @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
-  *                 equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
-  *                 else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
-  *                 to division by 8 or more.
-  */
-#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->DCKCFGR1 &= ~(RCC_DCKCFGR1_TIMPRE);\
-                                                 RCC->DCKCFGR1 |= (__PRESC__);           \
-                                                }while(0)
-
-/** @brief Macros to Enable or Disable the PLLISAI.
-  * @note  The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
-  */
-#define __HAL_RCC_PLLSAI_ENABLE() (RCC->CR |= (RCC_CR_PLLSAION))
-#define __HAL_RCC_PLLSAI_DISABLE() (RCC->CR &= ~(RCC_CR_PLLSAION))
-
-/** @brief  Macro to configure the PLLSAI clock multiplication and division factors.
-  * @note   This function must be used only when the PLLSAI is disabled.
-  * @note   PLLSAI clock source is common with the main PLL (configured in
-  *         RCC_PLLConfig function )
-  * @param  __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
-  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
-  * @note   You have to set the PLLSAIN parameter correctly to ensure that the VCO
-  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
-  * @param  __PLLSAIP__: specifies the division factor for USB, RNG, SDMMC clocks
-  *         This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider.
-  * @param  __PLLSAIQ__: specifies the division factor for SAI clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
-  * @param  __PLLSAIR__: specifies the division factor for LTDC clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
-  */
-#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__)                        \
-                               (RCC->PLLSAICFGR = ((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) |\
-                               ((__PLLSAIP__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP))                    |\
-                               ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ))                    |\
-                               ((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)))
-
-/** @brief  Macro to configure the PLLI2S clock multiplication and division factors.
-  * @note   This macro must be used only when the PLLI2S is disabled.
-  * @note   PLLI2S clock source is common with the main PLL (configured in
-  *         HAL_RCC_ClockConfig() API)
-  * @param  __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
-  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
-  * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO
-  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
-  * @param  __PLLI2SP__: specifies the division factor for SPDDIF-RX clock.
-  *         This parameter can be a value of @ref RCCEx_PLLI2SP_Clock_Divider.
-  * @param  __PLLI2SQ__: specifies the division factor for SAI clock.
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
-  * @param  __PLLI2SR__: specifies the division factor for I2S clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
-  * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
-  *         on the I2S clock frequency.
-  */
-#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__)                        \
-                               (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\
-                               ((__PLLI2SP__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP))                    |\
-                               ((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ))                    |\
-                               ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))
-
-/** @brief  Macro to configure the SAI clock Divider coming from PLLI2S.
-  * @note   This function must be called before enabling the PLLI2S.
-  * @param  __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock .
-  *          This parameter must be a number between 1 and 32.
-  *          SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
-  */
-#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
-
-/** @brief  Macro to configure the SAI clock Divider coming from PLLSAI.
-  * @note   This function must be called before enabling the PLLSAI.
-  * @param  __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
-  *         This parameter must be a number between Min_Data = 1 and Max_Data = 32.
-  *         SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
-  */
-#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
-
-/** @brief  Macro to configure the LTDC clock Divider coming from PLLSAI.
-  *
-  * @note   This function must be called before enabling the PLLSAI.
-  * @param  __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
-  *          This parameter can be a value of @ref RCCEx_PLLSAI_DIVR.
-  *          LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
-  */
-#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__)\
-                            MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, (uint32_t)(__PLLSAIDivR__))
-
-/** @brief  Macro to configure SAI1 clock source selection.
-  * @note   This function must be called before enabling PLLSAI, PLLI2S and
-  *         the SAI clock.
-  * @param  __SOURCE__: specifies the SAI1 clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
-  *                                           as SAI1 clock.
-  *            @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
-  *                                           as SAI1 clock.
-  *            @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
-  *                                        used as SAI1 clock.
-  *            @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock
-  *                                           used as SAI1 clock.
-  * @note      The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices
-  */
-#define __HAL_RCC_SAI1_CONFIG(__SOURCE__)\
-                             MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__))
-
-/** @brief  Macro to get the SAI1 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
-  *                                           as SAI1 clock.
-  *            @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
-  *                                           as SAI1 clock.
-  *            @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
-  *                                        used as SAI1 clock.
-  *            @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock
-  *                                           used as SAI1 clock.
-  * @note      The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices
-  */
-#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL)))
-
-
-/** @brief  Macro to configure SAI2 clock source selection.
-  * @note   This function must be called before enabling PLLSAI, PLLI2S and
-  *         the SAI clock.
-  * @param  __SOURCE__: specifies the SAI2 clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
-  *                                           as SAI2 clock.
-  *            @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
-  *                                           as SAI2 clock.
-  *            @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
-  *                                        used as SAI2 clock.
-  *            @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock
-  *                                           used as SAI2 clock.
-  * @note      The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices
-  */
-#define __HAL_RCC_SAI2_CONFIG(__SOURCE__)\
-                            MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__))
-
-
-/** @brief  Macro to get the SAI2 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
-  *                                           as SAI2 clock.
-  *            @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
-  *                                           as SAI2 clock.
-  *            @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
-  *                                        used as SAI2 clock.
-  *            @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock
-  *                                           used as SAI2 clock.
-  * @note      The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices
-  */
-#define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL)))
-
-
-/** @brief Enable PLLSAI_RDY interrupt.
-  */
-#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))
-
-/** @brief Disable PLLSAI_RDY interrupt.
-  */
-#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
-
-/** @brief Clear the PLLSAI RDY interrupt pending bits.
-  */
-#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))
-
-/** @brief Check the PLLSAI RDY interrupt has occurred or not.
-  * @retval The new state (TRUE or FALSE).
-  */
-#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
-
-/** @brief  Check PLLSAI RDY flag is set or not.
-  * @retval The new state (TRUE or FALSE).
-  */
-#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
-
-/** @brief  Macro to Get I2S clock source selection.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
-  *            @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S clock source
-  */
-#define __HAL_RCC_GET_I2SCLKSOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))
-
-/** @brief  Macro to configure the I2C1 clock (I2C1CLK).
-  *
-  * @param  __I2C1_CLKSOURCE__: specifies the I2C1 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
-  *            @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
-  *            @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
-  */
-#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
-                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
-
-/** @brief  Macro to get the I2C1 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
-  *            @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
-  *            @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
-  */
-#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL)))
-
-/** @brief  Macro to configure the I2C2 clock (I2C2CLK).
-  *
-  * @param  __I2C2_CLKSOURCE__: specifies the I2C2 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock
-  *            @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
-  *            @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
-  */
-#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \
-                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))
-
-/** @brief  Macro to get the I2C2 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock
-  *            @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
-  *            @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
-  */
-#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL)))
-
-/** @brief  Macro to configure the I2C3 clock (I2C3CLK).
-  *
-  * @param  __I2C3_CLKSOURCE__: specifies the I2C3 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
-  *            @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
-  *            @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
-  */
-#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
-                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
-
-/** @brief  macro to get the I2C3 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
-  *            @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
-  *            @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
-  */
-#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL)))
-
-/** @brief  Macro to configure the I2C4 clock (I2C4CLK).
-  *
-  * @param  __I2C4_CLKSOURCE__: specifies the I2C4 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock
-  *            @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
-  *            @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock
-  */
-#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \
-                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__))
-
-/** @brief  macro to get the I2C4 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock
-  *            @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
-  *            @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock
-  */
-#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL)))
-
-/** @brief  Macro to configure the USART1 clock (USART1CLK).
-  *
-  * @param  __USART1_CLKSOURCE__: specifies the USART1 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
-  *            @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
-  *            @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
-  *            @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
-  */
-#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
-                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
-
-/** @brief  macro to get the USART1 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
-  *            @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
-  *            @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
-  *            @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
-  */
-#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL)))
-
-/** @brief  Macro to configure the USART2 clock (USART2CLK).
-  *
-  * @param  __USART2_CLKSOURCE__: specifies the USART2 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
-  *            @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
-  *            @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
-  *            @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
-  */
-#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
-                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
-
-/** @brief  macro to get the USART2 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
-  *            @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
-  *            @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
-  *            @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
-  */
-#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL)))
-
-/** @brief  Macro to configure the USART3 clock (USART3CLK).
-  *
-  * @param  __USART3_CLKSOURCE__: specifies the USART3 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
-  *            @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
-  *            @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
-  *            @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
-  */
-#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \
-                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))
-
-/** @brief  macro to get the USART3 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
-  *            @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
-  *            @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
-  *            @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
-  */
-#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL)))
-
- /** @brief  Macro to configure the UART4 clock (UART4CLK).
-  *
-  * @param  __UART4_CLKSOURCE__: specifies the UART4 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
-  *            @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
-  *            @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
-  *            @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
-  */
-#define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \
-                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))
-
-/** @brief  macro to get the UART4 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
-  *            @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
-  *            @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
-  *            @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
-  */
-#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL)))
-
- /** @brief  Macro to configure the UART5 clock (UART5CLK).
-  *
-  * @param  __UART5_CLKSOURCE__: specifies the UART5 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
-  *            @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
-  *            @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
-  *            @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
-  */
-#define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \
-                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))
-
-/** @brief  macro to get the UART5 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
-  *            @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
-  *            @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
-  *            @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
-  */
-#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL)))
-
- /** @brief  Macro to configure the USART6 clock (USART6CLK).
-  *
-  * @param  __USART6_CLKSOURCE__: specifies the USART6 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock
-  *            @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
-  *            @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock
-  *            @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
-  */
-#define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \
-                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__))
-
-/** @brief  macro to get the USART6 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock
-  *            @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
-  *            @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock
-  *            @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
-  */
-#define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL)))
-
- /** @brief  Macro to configure the UART7 clock (UART7CLK).
-  *
-  * @param  __UART7_CLKSOURCE__: specifies the UART7 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock
-  *            @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
-  *            @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock
-  *            @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
-  */
-#define __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__) \
-                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__))
-
-/** @brief  macro to get the UART7 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock
-  *            @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
-  *            @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock
-  *            @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
-  */
-#define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL)))
-
-/** @brief  Macro to configure the UART8 clock (UART8CLK).
-  *
-  * @param  __UART8_CLKSOURCE__: specifies the UART8 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock
-  *            @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
-  *            @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock
-  *            @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
-  */
-#define __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__) \
-                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__))
-
-/** @brief  macro to get the UART8 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock
-  *            @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
-  *            @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock
-  *            @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
-  */
-#define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL)))
-
-/** @brief  Macro to configure the LPTIM1 clock (LPTIM1CLK).
-  *
-  * @param  __LPTIM1_CLKSOURCE__: specifies the LPTIM1 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock
-  *            @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock
-  *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
-  *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
-  */
-#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
-                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
-
-/** @brief  macro to get the LPTIM1 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock
-  *            @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock
-  *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
-  *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
-  */
-#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)))
-
-/** @brief  Macro to configure the CEC clock (CECCLK).
-  *
-  * @param  __CEC_CLKSOURCE__: specifies the CEC clock source.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
-  *            @arg RCC_CECCLKSOURCE_HSI: HSI divided by 488 selected as CEC clock
-  */
-#define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) \
-                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__))
-
-/** @brief  macro to get the CEC clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
-  *            @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
-  */
-#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL)))
-
-/** @brief  Macro to configure the CLK48 source (CLK48CLK).
-  *
-  * @param  __CLK48_SOURCE__: specifies the CLK48 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_CLK48SOURCE_PLL: PLL selected as CLK48 source
-  *            @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP selected as CLK48 source
-  */
-#define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) \
-                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__CLK48_SOURCE__))
-
-/** @brief  macro to get the CLK48 source.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_CLK48SOURCE_PLL: PLL used as CLK48 source
-  *            @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP used as CLK48 source
-  */
-#define __HAL_RCC_GET_CLK48_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)))
-
-/** @brief  Macro to configure the SDMMC1 clock (SDMMC1CLK).
-  *
-  * @param  __SDMMC1_CLKSOURCE__: specifies the SDMMC1 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC clock
-  *            @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC clock
-  */
-#define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \
-                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL, (uint32_t)(__SDMMC1_CLKSOURCE__))
-
-/** @brief  macro to get the SDMMC1 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC1 clock
-  *            @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC1 clock
-  */
-#define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL)))
-
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-/** @brief  Macro to configure the SDMMC2 clock (SDMMC2CLK).
-  * @param  __SDMMC2_CLKSOURCE__: specifies the SDMMC2 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock
-  *            @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock
-  */
-#define __HAL_RCC_SDMMC2_CONFIG(__SDMMC2_CLKSOURCE__) \
-                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL, (uint32_t)(__SDMMC2_CLKSOURCE__))
-
-/** @brief  macro to get the SDMMC2 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock
-  *            @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock
-  */
-#define __HAL_RCC_GET_SDMMC2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL)))
-
-/** @brief  Macro to configure the DFSDM1 clock
-  * @param  __DFSDM1_CLKSOURCE__: specifies the DFSDM1  clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_DFSDM1CLKSOURCE_PCLK: PCLK2 Clock selected as DFSDM clock
-  *            @arg RCC_DFSDMCLKSOURCE_SYSCLK: System Clock selected as DFSDM clock
-  */
-#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \
-                  MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL, (uint32_t)(__DFSDM1_CLKSOURCE__))
-
-/** @brief  Macro to get the DFSDM1 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_DFSDM1CLKSOURCE_PCLK:  PCLK2 Clock selected as DFSDM1 clock
-  *            @arg RCC_DFSDM1CLKSOURCE_SYSCLK:   System Clock selected as DFSDM1 clock
-  */
-#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL)))
-
-/** @brief  Macro to configure the DFSDM1 Audio clock
-  * @param  __DFSDM1AUDIO_CLKSOURCE__: specifies the DFSDM1 Audio clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1:  SAI1 Clock selected as DFSDM1 Audio clock
-  *            @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2:  SAI2 Clock selected as DFSDM1 Audio clock
-  */
-#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \
-                  MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL, (uint32_t)(__DFSDM1AUDIO_CLKSOURCE__))
-
-/** @brief  Macro to get the DFSDM1 Audio clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1:  SAI1 Clock selected as DFSDM1 Audio clock
-  *            @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2:  SAI2 Clock selected as DFSDM1 Audio clock
-  */
-#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL)))
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
-#if defined (STM32F769xx) || defined (STM32F779xx)
-/** @brief  Macro to configure the DSI clock.
-  * @param  __DSI_CLKSOURCE__: specifies the DSI clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
-  *            @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
-  */
-#define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL, (uint32_t)(__DSI_CLKSOURCE__)))
-
-/** @brief  Macro to Get the DSI clock.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
-  *            @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
-  */
-#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL))
-#endif /* STM32F769xx || STM32F779xx */
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RCCEx_Exported_Functions_Group1
-  * @{
-  */
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
-void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
-uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
-
-/**
-  * @}
-  */
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup RCCEx_Private_Macros RCCEx Private Macros
-  * @{
-  */
-/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
-  * @{
-  */
-#if defined(STM32F756xx) || defined(STM32F746xx)
-#define IS_RCC_PERIPHCLOCK(SELECTION)  \
-               ((((SELECTION) & RCC_PERIPHCLK_I2S)         == RCC_PERIPHCLK_I2S)     || \
-                (((SELECTION) & RCC_PERIPHCLK_LTDC)        == RCC_PERIPHCLK_LTDC)    || \
-                (((SELECTION) & RCC_PERIPHCLK_TIM)         == RCC_PERIPHCLK_TIM)     || \
-                (((SELECTION) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)  || \
-                (((SELECTION) & RCC_PERIPHCLK_USART2)      == RCC_PERIPHCLK_USART2)  || \
-                (((SELECTION) & RCC_PERIPHCLK_USART3)      == RCC_PERIPHCLK_USART3)  || \
-                (((SELECTION) & RCC_PERIPHCLK_UART4)       == RCC_PERIPHCLK_UART4)   || \
-                (((SELECTION) & RCC_PERIPHCLK_UART5)       == RCC_PERIPHCLK_UART5)   || \
-                (((SELECTION) & RCC_PERIPHCLK_USART6)      == RCC_PERIPHCLK_USART6)  || \
-                (((SELECTION) & RCC_PERIPHCLK_UART7)       == RCC_PERIPHCLK_UART7)   || \
-                (((SELECTION) & RCC_PERIPHCLK_UART8)       == RCC_PERIPHCLK_UART8)   || \
-                (((SELECTION) & RCC_PERIPHCLK_I2C1)        == RCC_PERIPHCLK_I2C1)    || \
-                (((SELECTION) & RCC_PERIPHCLK_I2C2)        == RCC_PERIPHCLK_I2C2)    || \
-                (((SELECTION) & RCC_PERIPHCLK_I2C3)        == RCC_PERIPHCLK_I2C3)    || \
-                (((SELECTION) & RCC_PERIPHCLK_I2C4)        == RCC_PERIPHCLK_I2C4)    || \
-                (((SELECTION) & RCC_PERIPHCLK_LPTIM1)      == RCC_PERIPHCLK_LPTIM1)  || \
-                (((SELECTION) & RCC_PERIPHCLK_SAI1)        == RCC_PERIPHCLK_SAI1)    || \
-                (((SELECTION) & RCC_PERIPHCLK_SAI2)        == RCC_PERIPHCLK_SAI2)    || \
-                (((SELECTION) & RCC_PERIPHCLK_CLK48)       == RCC_PERIPHCLK_CLK48)   || \
-                (((SELECTION) & RCC_PERIPHCLK_CEC)         == RCC_PERIPHCLK_CEC)     || \
-                (((SELECTION) & RCC_PERIPHCLK_SDMMC1)      == RCC_PERIPHCLK_SDMMC1)  || \
-                (((SELECTION) & RCC_PERIPHCLK_SPDIFRX)     == RCC_PERIPHCLK_SPDIFRX) || \
-                (((SELECTION) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC))
-#elif defined(STM32F745xx)
-#define IS_RCC_PERIPHCLOCK(SELECTION)  \
-               ((((SELECTION) & RCC_PERIPHCLK_I2S)         == RCC_PERIPHCLK_I2S)     || \
-                (((SELECTION) & RCC_PERIPHCLK_TIM)         == RCC_PERIPHCLK_TIM)     || \
-                (((SELECTION) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)  || \
-                (((SELECTION) & RCC_PERIPHCLK_USART2)      == RCC_PERIPHCLK_USART2)  || \
-                (((SELECTION) & RCC_PERIPHCLK_USART3)      == RCC_PERIPHCLK_USART3)  || \
-                (((SELECTION) & RCC_PERIPHCLK_UART4)       == RCC_PERIPHCLK_UART4)   || \
-                (((SELECTION) & RCC_PERIPHCLK_UART5)       == RCC_PERIPHCLK_UART5)   || \
-                (((SELECTION) & RCC_PERIPHCLK_USART6)      == RCC_PERIPHCLK_USART6)  || \
-                (((SELECTION) & RCC_PERIPHCLK_UART7)       == RCC_PERIPHCLK_UART7)   || \
-                (((SELECTION) & RCC_PERIPHCLK_UART8)       == RCC_PERIPHCLK_UART8)   || \
-                (((SELECTION) & RCC_PERIPHCLK_I2C1)        == RCC_PERIPHCLK_I2C1)    || \
-                (((SELECTION) & RCC_PERIPHCLK_I2C2)        == RCC_PERIPHCLK_I2C2)    || \
-                (((SELECTION) & RCC_PERIPHCLK_I2C3)        == RCC_PERIPHCLK_I2C3)    || \
-                (((SELECTION) & RCC_PERIPHCLK_I2C4)        == RCC_PERIPHCLK_I2C4)    || \
-                (((SELECTION) & RCC_PERIPHCLK_LPTIM1)      == RCC_PERIPHCLK_LPTIM1)  || \
-                (((SELECTION) & RCC_PERIPHCLK_SAI1)        == RCC_PERIPHCLK_SAI1)    || \
-                (((SELECTION) & RCC_PERIPHCLK_SAI2)        == RCC_PERIPHCLK_SAI2)    || \
-                (((SELECTION) & RCC_PERIPHCLK_CLK48)       == RCC_PERIPHCLK_CLK48)   || \
-                (((SELECTION) & RCC_PERIPHCLK_CEC)         == RCC_PERIPHCLK_CEC)     || \
-                (((SELECTION) & RCC_PERIPHCLK_SDMMC1)      == RCC_PERIPHCLK_SDMMC1)  || \
-                (((SELECTION) & RCC_PERIPHCLK_SPDIFRX)     == RCC_PERIPHCLK_SPDIFRX) || \
-                (((SELECTION) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC))
-#elif defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define IS_RCC_PERIPHCLOCK(SELECTION)  \
-               ((((SELECTION) & RCC_PERIPHCLK_I2S)         == RCC_PERIPHCLK_I2S)     || \
-                (((SELECTION) & RCC_PERIPHCLK_LTDC)        == RCC_PERIPHCLK_LTDC)    || \
-                (((SELECTION) & RCC_PERIPHCLK_TIM)         == RCC_PERIPHCLK_TIM)     || \
-                (((SELECTION) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)  || \
-                (((SELECTION) & RCC_PERIPHCLK_USART2)      == RCC_PERIPHCLK_USART2)  || \
-                (((SELECTION) & RCC_PERIPHCLK_USART3)      == RCC_PERIPHCLK_USART3)  || \
-                (((SELECTION) & RCC_PERIPHCLK_UART4)       == RCC_PERIPHCLK_UART4)   || \
-                (((SELECTION) & RCC_PERIPHCLK_UART5)       == RCC_PERIPHCLK_UART5)   || \
-                (((SELECTION) & RCC_PERIPHCLK_USART6)      == RCC_PERIPHCLK_USART6)  || \
-                (((SELECTION) & RCC_PERIPHCLK_UART7)       == RCC_PERIPHCLK_UART7)   || \
-                (((SELECTION) & RCC_PERIPHCLK_UART8)       == RCC_PERIPHCLK_UART8)   || \
-                (((SELECTION) & RCC_PERIPHCLK_I2C1)        == RCC_PERIPHCLK_I2C1)    || \
-                (((SELECTION) & RCC_PERIPHCLK_I2C2)        == RCC_PERIPHCLK_I2C2)    || \
-                (((SELECTION) & RCC_PERIPHCLK_I2C3)        == RCC_PERIPHCLK_I2C3)    || \
-                (((SELECTION) & RCC_PERIPHCLK_I2C4)        == RCC_PERIPHCLK_I2C4)    || \
-                (((SELECTION) & RCC_PERIPHCLK_LPTIM1)      == RCC_PERIPHCLK_LPTIM1)  || \
-                (((SELECTION) & RCC_PERIPHCLK_SAI1)        == RCC_PERIPHCLK_SAI1)    || \
-                (((SELECTION) & RCC_PERIPHCLK_SAI2)        == RCC_PERIPHCLK_SAI2)    || \
-                (((SELECTION) & RCC_PERIPHCLK_CLK48)       == RCC_PERIPHCLK_CLK48)   || \
-                (((SELECTION) & RCC_PERIPHCLK_CEC)         == RCC_PERIPHCLK_CEC)     || \
-                (((SELECTION) & RCC_PERIPHCLK_SDMMC1)      == RCC_PERIPHCLK_SDMMC1)  || \
-                (((SELECTION) & RCC_PERIPHCLK_SDMMC2)      == RCC_PERIPHCLK_SDMMC2)  || \
-                (((SELECTION) & RCC_PERIPHCLK_DFSDM1)       == RCC_PERIPHCLK_DFSDM1)   || \
-                (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \
-                (((SELECTION) & RCC_PERIPHCLK_SPDIFRX)     == RCC_PERIPHCLK_SPDIFRX) || \
-                (((SELECTION) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC))
-#elif defined (STM32F765xx)
-#define IS_RCC_PERIPHCLOCK(SELECTION)  \
-               ((((SELECTION) & RCC_PERIPHCLK_I2S)         == RCC_PERIPHCLK_I2S)     || \
-                (((SELECTION) & RCC_PERIPHCLK_TIM)         == RCC_PERIPHCLK_TIM)     || \
-                (((SELECTION) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)  || \
-                (((SELECTION) & RCC_PERIPHCLK_USART2)      == RCC_PERIPHCLK_USART2)  || \
-                (((SELECTION) & RCC_PERIPHCLK_USART3)      == RCC_PERIPHCLK_USART3)  || \
-                (((SELECTION) & RCC_PERIPHCLK_UART4)       == RCC_PERIPHCLK_UART4)   || \
-                (((SELECTION) & RCC_PERIPHCLK_UART5)       == RCC_PERIPHCLK_UART5)   || \
-                (((SELECTION) & RCC_PERIPHCLK_USART6)      == RCC_PERIPHCLK_USART6)  || \
-                (((SELECTION) & RCC_PERIPHCLK_UART7)       == RCC_PERIPHCLK_UART7)   || \
-                (((SELECTION) & RCC_PERIPHCLK_UART8)       == RCC_PERIPHCLK_UART8)   || \
-                (((SELECTION) & RCC_PERIPHCLK_I2C1)        == RCC_PERIPHCLK_I2C1)    || \
-                (((SELECTION) & RCC_PERIPHCLK_I2C2)        == RCC_PERIPHCLK_I2C2)    || \
-                (((SELECTION) & RCC_PERIPHCLK_I2C3)        == RCC_PERIPHCLK_I2C3)    || \
-                (((SELECTION) & RCC_PERIPHCLK_I2C4)        == RCC_PERIPHCLK_I2C4)    || \
-                (((SELECTION) & RCC_PERIPHCLK_LPTIM1)      == RCC_PERIPHCLK_LPTIM1)  || \
-                (((SELECTION) & RCC_PERIPHCLK_SAI1)        == RCC_PERIPHCLK_SAI1)    || \
-                (((SELECTION) & RCC_PERIPHCLK_SAI2)        == RCC_PERIPHCLK_SAI2)    || \
-                (((SELECTION) & RCC_PERIPHCLK_CLK48)       == RCC_PERIPHCLK_CLK48)   || \
-                (((SELECTION) & RCC_PERIPHCLK_CEC)         == RCC_PERIPHCLK_CEC)     || \
-                (((SELECTION) & RCC_PERIPHCLK_SDMMC1)      == RCC_PERIPHCLK_SDMMC1)  || \
-                (((SELECTION) & RCC_PERIPHCLK_SDMMC2)      == RCC_PERIPHCLK_SDMMC2)  || \
-                (((SELECTION) & RCC_PERIPHCLK_DFSDM1)       == RCC_PERIPHCLK_DFSDM1)   || \
-                (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \
-                (((SELECTION) & RCC_PERIPHCLK_SPDIFRX)     == RCC_PERIPHCLK_SPDIFRX) || \
-                (((SELECTION) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC))
-#endif /* STM32F746xx || STM32F756xx */
-#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
-#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\
-                                     ((VALUE) == RCC_PLLI2SP_DIV4) ||\
-                                     ((VALUE) == RCC_PLLI2SP_DIV6) ||\
-                                     ((VALUE) == RCC_PLLI2SP_DIV8))
-#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
-#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
-
-#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
-#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\
-                                     ((VALUE) == RCC_PLLSAIP_DIV4) ||\
-                                     ((VALUE) == RCC_PLLSAIP_DIV6) ||\
-                                     ((VALUE) == RCC_PLLSAIP_DIV8))
-#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
-#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
-
-#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
-
-#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
-
-#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\
-                                         ((VALUE) == RCC_PLLSAIDIVR_4) ||\
-                                         ((VALUE) == RCC_PLLSAIDIVR_8) ||\
-                                         ((VALUE) == RCC_PLLSAIDIVR_16))
-#define IS_RCC_I2SCLKSOURCE(SOURCE)  (((SOURCE) == RCC_I2SCLKSOURCE_PLLI2S) || \
-                                      ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
-
-#define IS_RCC_SDMMC1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC1CLKSOURCE_SYSCLK) || \
-                                        ((SOURCE) == RCC_SDMMC1CLKSOURCE_CLK48))
-
-#define IS_RCC_CECCLKSOURCE(SOURCE)  (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \
-                                      ((SOURCE) == RCC_CECCLKSOURCE_LSE))
-#define IS_RCC_USART1CLKSOURCE(SOURCE)  \
-               (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2)  || \
-                ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
-                ((SOURCE) == RCC_USART1CLKSOURCE_LSE)    || \
-                ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
-
-#define IS_RCC_USART2CLKSOURCE(SOURCE)  \
-               (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1)  || \
-                ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \
-                ((SOURCE) == RCC_USART2CLKSOURCE_LSE)    || \
-                ((SOURCE) == RCC_USART2CLKSOURCE_HSI))
-#define IS_RCC_USART3CLKSOURCE(SOURCE)  \
-               (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1)  || \
-                ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \
-                ((SOURCE) == RCC_USART3CLKSOURCE_LSE)    || \
-                ((SOURCE) == RCC_USART3CLKSOURCE_HSI))
-
-#define IS_RCC_UART4CLKSOURCE(SOURCE)  \
-               (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1)  || \
-                ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \
-                ((SOURCE) == RCC_UART4CLKSOURCE_LSE)    || \
-                ((SOURCE) == RCC_UART4CLKSOURCE_HSI))
-
-#define IS_RCC_UART5CLKSOURCE(SOURCE)  \
-               (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1)  || \
-                ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \
-                ((SOURCE) == RCC_UART5CLKSOURCE_LSE)    || \
-                ((SOURCE) == RCC_UART5CLKSOURCE_HSI))
-
-#define IS_RCC_USART6CLKSOURCE(SOURCE)  \
-               (((SOURCE) == RCC_USART6CLKSOURCE_PCLK2)  || \
-                ((SOURCE) == RCC_USART6CLKSOURCE_SYSCLK) || \
-                ((SOURCE) == RCC_USART6CLKSOURCE_LSE)    || \
-                ((SOURCE) == RCC_USART6CLKSOURCE_HSI))
-
-#define IS_RCC_UART7CLKSOURCE(SOURCE)  \
-               (((SOURCE) == RCC_UART7CLKSOURCE_PCLK1)  || \
-                ((SOURCE) == RCC_UART7CLKSOURCE_SYSCLK) || \
-                ((SOURCE) == RCC_UART7CLKSOURCE_LSE)    || \
-                ((SOURCE) == RCC_UART7CLKSOURCE_HSI))
-
-#define IS_RCC_UART8CLKSOURCE(SOURCE)  \
-               (((SOURCE) == RCC_UART8CLKSOURCE_PCLK1)  || \
-                ((SOURCE) == RCC_UART8CLKSOURCE_SYSCLK) || \
-                ((SOURCE) == RCC_UART8CLKSOURCE_LSE)    || \
-                ((SOURCE) == RCC_UART8CLKSOURCE_HSI))
-#define IS_RCC_I2C1CLKSOURCE(SOURCE)   \
-               (((SOURCE) == RCC_I2C1CLKSOURCE_PCLK1) || \
-                ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
-                ((SOURCE) == RCC_I2C1CLKSOURCE_HSI))
-#define IS_RCC_I2C2CLKSOURCE(SOURCE)   \
-               (((SOURCE) == RCC_I2C2CLKSOURCE_PCLK1) || \
-                ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)|| \
-                ((SOURCE) == RCC_I2C2CLKSOURCE_HSI))
-
-#define IS_RCC_I2C3CLKSOURCE(SOURCE)   \
-               (((SOURCE) == RCC_I2C3CLKSOURCE_PCLK1) || \
-                ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
-                ((SOURCE) == RCC_I2C3CLKSOURCE_HSI))
-#define IS_RCC_I2C4CLKSOURCE(SOURCE)   \
-               (((SOURCE) == RCC_I2C4CLKSOURCE_PCLK1) || \
-                ((SOURCE) == RCC_I2C4CLKSOURCE_SYSCLK)|| \
-                ((SOURCE) == RCC_I2C4CLKSOURCE_HSI))
-#define IS_RCC_LPTIM1CLK(SOURCE)  \
-               (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) || \
-                ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI)  || \
-                ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI)  || \
-                ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
-#define IS_RCC_CLK48SOURCE(SOURCE)  \
-               (((SOURCE) == RCC_CLK48SOURCE_PLLSAIP) || \
-                ((SOURCE) == RCC_CLK48SOURCE_PLL))
-#define IS_RCC_TIMPRES(VALUE)  \
-               (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \
-                ((VALUE) == RCC_TIMPRES_ACTIVATED))
-
-#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx)
-#define IS_RCC_SAI1CLKSOURCE(SOURCE)  (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \
-                                       ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \
-                                       ((SOURCE) == RCC_SAI1CLKSOURCE_PIN))
-#define IS_RCC_SAI2CLKSOURCE(SOURCE)  (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \
-                                       ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \
-                                       ((SOURCE) == RCC_SAI2CLKSOURCE_PIN))
-#endif /* STM32F745xx || STM32F746xx || STM32F756xx */
-
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define IS_RCC_PLLR_VALUE(VALUE)            ((2 <= (VALUE)) && ((VALUE) <= 7))
-
-#define IS_RCC_SAI1CLKSOURCE(SOURCE)  (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \
-                                       ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \
-                                       ((SOURCE) == RCC_SAI1CLKSOURCE_PIN)    || \
-                                       ((SOURCE) == RCC_SAI1CLKSOURCE_PLLSRC))
-
-#define IS_RCC_SAI2CLKSOURCE(SOURCE)  (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \
-                                       ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \
-                                       ((SOURCE) == RCC_SAI2CLKSOURCE_PIN)    || \
-                                       ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC))
-
-#define IS_RCC_SDMMC2CLKSOURCE(SOURCE)  (((SOURCE) == RCC_SDMMC2CLKSOURCE_SYSCLK) || \
-                                         ((SOURCE) == RCC_SDMMC2CLKSOURCE_CLK48))
-
-#define IS_RCC_DFSDM1CLKSOURCE(SOURCE)  (((SOURCE) == RCC_DFSDM1CLKSOURCE_PCLK) || \
-                                        ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYSCLK))
-
-#define IS_RCC_DFSDM1AUDIOCLKSOURCE(SOURCE)  (((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \
-                                             ((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI2))
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
-#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-#define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR)  ||\
-                                             ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY))
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F7xx_HAL_RCC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_rng.h b/stmhal/hal/f7/inc/stm32f7xx_hal_rng.h
deleted file mode 100644
index 385aacdcfd..0000000000
--- a/stmhal/hal/f7/inc/stm32f7xx_hal_rng.h
+++ /dev/null
@@ -1,358 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_rng.h
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   Header file of RNG HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_RNG_H
-#define __STM32F7xx_HAL_RNG_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal_def.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup RNG RNG
-  * @brief RNG HAL module driver
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup RNG_Exported_Types RNG Exported Types
-  * @{
-  */
-
-/** @defgroup RNG_Exported_Types_Group1 RNG State Structure definition
-  * @{
-  */
-typedef enum
-{
-  HAL_RNG_STATE_RESET     = 0x00U,  /*!< RNG not yet initialized or disabled */
-  HAL_RNG_STATE_READY     = 0x01U,  /*!< RNG initialized and ready for use   */
-  HAL_RNG_STATE_BUSY      = 0x02U,  /*!< RNG internal process is ongoing     */
-  HAL_RNG_STATE_TIMEOUT   = 0x03U,  /*!< RNG timeout state                   */
-  HAL_RNG_STATE_ERROR     = 0x04U   /*!< RNG error state                     */
-
-}HAL_RNG_StateTypeDef;
-
-/**
-  * @}
-  */
-
-/** @defgroup RNG_Exported_Types_Group2 RNG Handle Structure definition
-  * @{
-  */
-typedef struct
-{
-  RNG_TypeDef                 *Instance;    /*!< Register base address   */
-
-  uint32_t                    RandomNumber; /*!< Last Generated random number */
-
-  HAL_LockTypeDef             Lock;         /*!< RNG locking object      */
-
-  __IO HAL_RNG_StateTypeDef   State;        /*!< RNG communication state */
-
-}RNG_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup RNG_Exported_Constants RNG Exported Constants
-  * @{
-  */
-
-/** @defgroup RNG_Exported_Constants_Group1 RNG Interrupt definition
-  * @{
-  */
-#define RNG_IT_DRDY  RNG_SR_DRDY  /*!< Data Ready interrupt  */
-#define RNG_IT_CEI   RNG_SR_CEIS  /*!< Clock error interrupt */
-#define RNG_IT_SEI   RNG_SR_SEIS  /*!< Seed error interrupt  */
-/**
-  * @}
-  */
-
-/** @defgroup RNG_Exported_Constants_Group2 RNG Flag definition
-  * @{
-  */
-#define RNG_FLAG_DRDY   RNG_SR_DRDY  /*!< Data ready                 */
-#define RNG_FLAG_CECS   RNG_SR_CECS  /*!< Clock error current status */
-#define RNG_FLAG_SECS   RNG_SR_SECS  /*!< Seed error current status  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-
-/** @defgroup RNG_Exported_Macros RNG Exported Macros
-  * @{
-  */
-
-/** @brief Reset RNG handle state
-  * @param  __HANDLE__: RNG Handle
-  * @retval None
-  */
-#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
-
-/**
-  * @brief  Enables the RNG peripheral.
-  * @param  __HANDLE__: RNG Handle
-  * @retval None
-  */
-#define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_RNGEN)
-
-/**
-  * @brief  Disables the RNG peripheral.
-  * @param  __HANDLE__: RNG Handle
-  * @retval None
-  */
-#define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
-
-/**
-  * @brief  Check the selected RNG flag status.
-  * @param  __HANDLE__: RNG Handle
-  * @param  __FLAG__: RNG flag
-  *          This parameter can be one of the following values:
-  *            @arg RNG_FLAG_DRDY: Data ready
-  *            @arg RNG_FLAG_CECS: Clock error current status
-  *            @arg RNG_FLAG_SECS: Seed error current status
-  * @retval The new state of __FLAG__ (SET or RESET).
-  */
-#define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-
-/**
-  * @brief  Clears the selected RNG flag status.
-  * @param  __HANDLE__: RNG handle
-  * @param  __FLAG__: RNG flag to clear
-  * @note   WARNING: This is a dummy macro for HAL code alignment,
-  *         flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
-  * @retval None
-  */
-#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__)                      /* dummy  macro */
-
-
-
-/**
-  * @brief  Enables the RNG interrupts.
-  * @param  __HANDLE__: RNG Handle
-  * @retval None
-  */
-#define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_IE)
-
-/**
-  * @brief  Disables the RNG interrupts.
-  * @param  __HANDLE__: RNG Handle
-  * @retval None
-  */
-#define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
-
-/**
-  * @brief  Checks whether the specified RNG interrupt has occurred or not.
-  * @param  __HANDLE__: RNG Handle
-  * @param  __INTERRUPT__: specifies the RNG interrupt status flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg RNG_IT_DRDY: Data ready interrupt
-  *            @arg RNG_IT_CEI: Clock error interrupt
-  *            @arg RNG_IT_SEI: Seed error interrupt
-  * @retval The new state of __INTERRUPT__ (SET or RESET).
-  */
-#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/**
-  * @brief  Clear the RNG interrupt status flags.
-  * @param  __HANDLE__: RNG Handle
-  * @param  __INTERRUPT__: specifies the RNG interrupt status flag to clear.
-  *          This parameter can be one of the following values:
-  *            @arg RNG_IT_CEI: Clock error interrupt
-  *            @arg RNG_IT_SEI: Seed error interrupt
-  * @note   RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.
-  * @retval None
-  */
-#define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup RNG_Exported_Functions RNG Exported Functions
-  * @{
-  */
-
-/** @defgroup RNG_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);
-HAL_StatusTypeDef HAL_RNG_DeInit (RNG_HandleTypeDef *hrng);
-void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
-void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
-
-/**
-  * @}
-  */
-
-/** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions
-  * @{
-  */
-uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng);    /* Obsolete, use HAL_RNG_GenerateRandomNumber() instead    */
-uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber_IT() instead */
-
-HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
-HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
-uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);
-
-void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
-void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
-void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef* hrng, uint32_t random32bit);
-
-/**
-  * @}
-  */
-
-/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions
-  * @{
-  */
-HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/
-/** @defgroup RNG_Private_Types RNG Private Types
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup RNG_Private_Defines RNG Private Defines
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup RNG_Private_Variables RNG Private Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RNG_Private_Constants RNG Private Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup RNG_Private_Macros RNG Private Macros
-  * @{
-  */
-#define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || \
-                       ((IT) == RNG_IT_SEI))
-
-#define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \
-                           ((FLAG) == RNG_FLAG_CECS) || \
-                           ((FLAG) == RNG_FLAG_SECS))
-
-/**
-  * @}
-  */
-
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup RNG_Private_Functions_Prototypes RNG Private Functions Prototypes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup RNG_Private_Functions RNG Private Functions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F7xx_HAL_RNG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_rtc.h b/stmhal/hal/f7/inc/stm32f7xx_hal_rtc.h
deleted file mode 100644
index a508fce6be..0000000000
--- a/stmhal/hal/f7/inc/stm32f7xx_hal_rtc.h
+++ /dev/null
@@ -1,813 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_rtc.h
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   Header file of RTC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_RTC_H
-#define __STM32F7xx_HAL_RTC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal_def.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup RTC
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup RTC_Exported_Types RTC Exported Types
-  * @{
-  */
-
-/**
-  * @brief  HAL State structures definition
-  */
-typedef enum
-{
-  HAL_RTC_STATE_RESET             = 0x00U,  /*!< RTC not yet initialized or disabled */
-  HAL_RTC_STATE_READY             = 0x01U,  /*!< RTC initialized and ready for use   */
-  HAL_RTC_STATE_BUSY              = 0x02U,  /*!< RTC process is ongoing              */
-  HAL_RTC_STATE_TIMEOUT           = 0x03U,  /*!< RTC timeout state                   */
-  HAL_RTC_STATE_ERROR             = 0x04U   /*!< RTC error state                     */
-
-}HAL_RTCStateTypeDef;
-
-/**
-  * @brief  RTC Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t HourFormat;      /*!< Specifies the RTC Hour Format.
-                                 This parameter can be a value of @ref RTC_Hour_Formats */
-
-  uint32_t AsynchPrediv;    /*!< Specifies the RTC Asynchronous Predivider value.
-                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
-
-  uint32_t SynchPrediv;     /*!< Specifies the RTC Synchronous Predivider value.
-                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
-
-  uint32_t OutPut;          /*!< Specifies which signal will be routed to the RTC output.
-                                 This parameter can be a value of @ref RTCEx_Output_selection_Definitions */
-
-  uint32_t OutPutPolarity;  /*!< Specifies the polarity of the output signal.
-                                 This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
-
-  uint32_t OutPutType;      /*!< Specifies the RTC Output Pin mode.
-                                 This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
-}RTC_InitTypeDef;
-
-/**
-  * @brief  RTC Time structure definition
-  */
-typedef struct
-{
-  uint8_t Hours;            /*!< Specifies the RTC Time Hour.
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected  */
-
-  uint8_t Minutes;          /*!< Specifies the RTC Time Minutes.
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
-
-  uint8_t Seconds;          /*!< Specifies the RTC Time Seconds.
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
-
-  uint32_t SubSeconds;      /*!< Specifies the RTC_SSR RTC Sub Second register content.
-                                 This parameter corresponds to a time unit range between [0-1] Second
-                                 with [1 Sec / SecondFraction +1] granularity */
-
-  uint32_t SecondFraction;  /*!< Specifies the range or granularity of Sub Second register content
-                                 corresponding to Synchronous pre-scaler factor value (PREDIV_S)
-                                 This parameter corresponds to a time unit range between [0-1] Second
-                                 with [1 Sec / SecondFraction +1] granularity.
-                                 This field will be used only by HAL_RTC_GetTime function */
-
-  uint8_t TimeFormat;       /*!< Specifies the RTC AM/PM Time.
-                                 This parameter can be a value of @ref RTC_AM_PM_Definitions */
-
-  uint32_t DayLightSaving;  /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment.
-                                 This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
-
-  uint32_t StoreOperation;  /*!< Specifies RTC_StoreOperation value to be written in the BCK bit
-                                 in CR register to store the operation.
-                                 This parameter can be a value of @ref RTC_StoreOperation_Definitions */
-}RTC_TimeTypeDef;
-
-/**
-  * @brief  RTC Date structure definition
-  */
-typedef struct
-{
-  uint8_t WeekDay;  /*!< Specifies the RTC Date WeekDay.
-                         This parameter can be a value of @ref RTC_WeekDay_Definitions */
-
-  uint8_t Month;    /*!< Specifies the RTC Date Month (in BCD format).
-                         This parameter can be a value of @ref RTC_Month_Date_Definitions */
-
-  uint8_t Date;     /*!< Specifies the RTC Date.
-                         This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
-
-  uint8_t Year;     /*!< Specifies the RTC Date Year.
-                         This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
-
-}RTC_DateTypeDef;
-
-/**
-  * @brief  RTC Alarm structure definition
-  */
-typedef struct
-{
-  RTC_TimeTypeDef AlarmTime;     /*!< Specifies the RTC Alarm Time members */
-
-  uint32_t AlarmMask;            /*!< Specifies the RTC Alarm Masks.
-                                      This parameter can be a value of @ref RTC_AlarmMask_Definitions */
-
-  uint32_t AlarmSubSecondMask;   /*!< Specifies the RTC Alarm SubSeconds Masks.
-                                      This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
-
-  uint32_t AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on Date or WeekDay.
-                                     This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
-
-  uint8_t AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Date/WeekDay.
-                                      If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
-                                      If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
-
-  uint32_t Alarm;                /*!< Specifies the alarm .
-                                      This parameter can be a value of @ref RTC_Alarms_Definitions */
-}RTC_AlarmTypeDef;
-
-/**
-  * @brief  RTC Handle Structure definition
-  */
-typedef struct
-{
-  RTC_TypeDef                 *Instance;  /*!< Register base address    */
-
-  RTC_InitTypeDef             Init;       /*!< RTC required parameters  */
-
-  HAL_LockTypeDef             Lock;       /*!< RTC locking object       */
-
-  __IO HAL_RTCStateTypeDef    State;      /*!< Time communication state */
-
-}RTC_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RTC_Exported_Constants RTC Exported Constants
-  * @{
-  */
-
-/** @defgroup RTC_Hour_Formats RTC Hour Formats
-  * @{
-  */
-#define RTC_HOURFORMAT_24              ((uint32_t)0x00000000U)
-#define RTC_HOURFORMAT_12              ((uint32_t)0x00000040U)
-/**
-  * @}
-  */
-
-
-/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
-  * @{
-  */
-#define RTC_OUTPUT_POLARITY_HIGH       ((uint32_t)0x00000000U)
-#define RTC_OUTPUT_POLARITY_LOW        ((uint32_t)0x00100000U)
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
-  * @{
-  */
-#define RTC_OUTPUT_TYPE_OPENDRAIN      ((uint32_t)0x00000000U)
-#define RTC_OUTPUT_TYPE_PUSHPULL       ((uint32_t)RTC_OR_ALARMTYPE)  /* 0x00000008 */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
-  * @{
-  */
-#define RTC_HOURFORMAT12_AM            ((uint8_t)0x00U)
-#define RTC_HOURFORMAT12_PM            ((uint8_t)0x40U)
-/**
-  * @}
-  */
-
-/** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions
-  * @{
-  */
-#define RTC_DAYLIGHTSAVING_SUB1H       ((uint32_t)0x00020000U)
-#define RTC_DAYLIGHTSAVING_ADD1H       ((uint32_t)0x00010000U)
-#define RTC_DAYLIGHTSAVING_NONE        ((uint32_t)0x00000000U)
-/**
-  * @}
-  */
-
-/** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions
-  * @{
-  */
-#define RTC_STOREOPERATION_RESET        ((uint32_t)0x00000000U)
-#define RTC_STOREOPERATION_SET          ((uint32_t)0x00040000U)
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions
-  * @{
-  */
-#define RTC_FORMAT_BIN                      ((uint32_t)0x00000000U)
-#define RTC_FORMAT_BCD                      ((uint32_t)0x00000001U)
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
-  * @{
-  */
-/* Coded in BCD format */
-#define RTC_MONTH_JANUARY              ((uint8_t)0x01U)
-#define RTC_MONTH_FEBRUARY             ((uint8_t)0x02U)
-#define RTC_MONTH_MARCH                ((uint8_t)0x03U)
-#define RTC_MONTH_APRIL                ((uint8_t)0x04U)
-#define RTC_MONTH_MAY                  ((uint8_t)0x05U)
-#define RTC_MONTH_JUNE                 ((uint8_t)0x06U)
-#define RTC_MONTH_JULY                 ((uint8_t)0x07U)
-#define RTC_MONTH_AUGUST               ((uint8_t)0x08U)
-#define RTC_MONTH_SEPTEMBER            ((uint8_t)0x09U)
-#define RTC_MONTH_OCTOBER              ((uint8_t)0x10U)
-#define RTC_MONTH_NOVEMBER             ((uint8_t)0x11U)
-#define RTC_MONTH_DECEMBER             ((uint8_t)0x12U)
-/**
-  * @}
-  */
-
-/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
-  * @{
-  */
-#define RTC_WEEKDAY_MONDAY             ((uint8_t)0x01U)
-#define RTC_WEEKDAY_TUESDAY            ((uint8_t)0x02U)
-#define RTC_WEEKDAY_WEDNESDAY          ((uint8_t)0x03U)
-#define RTC_WEEKDAY_THURSDAY           ((uint8_t)0x04U)
-#define RTC_WEEKDAY_FRIDAY             ((uint8_t)0x05U)
-#define RTC_WEEKDAY_SATURDAY           ((uint8_t)0x06U)
-#define RTC_WEEKDAY_SUNDAY             ((uint8_t)0x07U)
-/**
-  * @}
-  */
-
-/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions
-  * @{
-  */
-#define RTC_ALARMDATEWEEKDAYSEL_DATE      ((uint32_t)0x00000000U)
-#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY   ((uint32_t)0x40000000U)
-/**
-  * @}
-  */
-
-/** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions
-  * @{
-  */
-#define RTC_ALARMMASK_NONE                ((uint32_t)0x00000000U)
-#define RTC_ALARMMASK_DATEWEEKDAY         RTC_ALRMAR_MSK4
-#define RTC_ALARMMASK_HOURS               RTC_ALRMAR_MSK3
-#define RTC_ALARMMASK_MINUTES             RTC_ALRMAR_MSK2
-#define RTC_ALARMMASK_SECONDS             RTC_ALRMAR_MSK1
-#define RTC_ALARMMASK_ALL                 ((uint32_t)0x80808080U)
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
-  * @{
-  */
-#define RTC_ALARM_A                       RTC_CR_ALRAE
-#define RTC_ALARM_B                       RTC_CR_ALRBE
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
-  * @{
-  */
-#define RTC_ALARMSUBSECONDMASK_ALL         ((uint32_t)0x00000000U)  /*!< All Alarm SS fields are masked.
-                                                                        There is no comparison on sub seconds
-                                                                        for Alarm */
-#define RTC_ALARMSUBSECONDMASK_SS14_1      ((uint32_t)0x01000000U)  /*!< SS[14:1] are don't care in Alarm
-                                                                        comparison. Only SS[0] is compared.    */
-#define RTC_ALARMSUBSECONDMASK_SS14_2      ((uint32_t)0x02000000U)  /*!< SS[14:2] are don't care in Alarm
-                                                                        comparison. Only SS[1:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_3      ((uint32_t)0x03000000U)  /*!< SS[14:3] are don't care in Alarm
-                                                                        comparison. Only SS[2:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_4      ((uint32_t)0x04000000U)  /*!< SS[14:4] are don't care in Alarm
-                                                                        comparison. Only SS[3:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_5      ((uint32_t)0x05000000U)  /*!< SS[14:5] are don't care in Alarm
-                                                                        comparison. Only SS[4:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_6      ((uint32_t)0x06000000U)  /*!< SS[14:6] are don't care in Alarm
-                                                                        comparison. Only SS[5:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_7      ((uint32_t)0x07000000U)  /*!< SS[14:7] are don't care in Alarm
-                                                                        comparison. Only SS[6:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_8      ((uint32_t)0x08000000U)  /*!< SS[14:8] are don't care in Alarm
-                                                                        comparison. Only SS[7:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_9      ((uint32_t)0x09000000U)  /*!< SS[14:9] are don't care in Alarm
-                                                                        comparison. Only SS[8:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_10     ((uint32_t)0x0A000000U)  /*!< SS[14:10] are don't care in Alarm
-                                                                        comparison. Only SS[9:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_11     ((uint32_t)0x0B000000U)  /*!< SS[14:11] are don't care in Alarm
-                                                                        comparison. Only SS[10:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_12     ((uint32_t)0x0C000000U)  /*!< SS[14:12] are don't care in Alarm
-                                                                        comparison.Only SS[11:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_13     ((uint32_t)0x0D000000U)  /*!< SS[14:13] are don't care in Alarm
-                                                                        comparison. Only SS[12:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14        ((uint32_t)0x0E000000U)  /*!< SS[14] is don't care in Alarm
-                                                                        comparison.Only SS[13:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_NONE        ((uint32_t)0x0F000000U)  /*!< SS[14:0] are compared and must match
-                                                                        to activate alarm. */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
-  * @{
-  */
-#define RTC_IT_TS                         ((uint32_t)RTC_CR_TSIE)
-#define RTC_IT_WUT                        ((uint32_t)RTC_CR_WUTIE)
-#define RTC_IT_ALRA                       ((uint32_t)RTC_CR_ALRAIE)
-#define RTC_IT_ALRB                       ((uint32_t)RTC_CR_ALRBIE)
-#define RTC_IT_TAMP                       ((uint32_t)RTC_TAMPCR_TAMPIE) /* Used only to Enable the Tamper Interrupt */
-#define RTC_IT_TAMP1                      ((uint32_t)RTC_TAMPCR_TAMP1IE)
-#define RTC_IT_TAMP2                      ((uint32_t)RTC_TAMPCR_TAMP2IE)
-#define RTC_IT_TAMP3                      ((uint32_t)RTC_TAMPCR_TAMP3IE)
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Flags_Definitions RTC Flags Definitions
-  * @{
-  */
-#define RTC_FLAG_RECALPF                  ((uint32_t)RTC_ISR_RECALPF)
-#define RTC_FLAG_TAMP3F                   ((uint32_t)RTC_ISR_TAMP3F)
-#define RTC_FLAG_TAMP2F                   ((uint32_t)RTC_ISR_TAMP2F)
-#define RTC_FLAG_TAMP1F                   ((uint32_t)RTC_ISR_TAMP1F)
-#define RTC_FLAG_TSOVF                    ((uint32_t)RTC_ISR_TSOVF)
-#define RTC_FLAG_TSF                      ((uint32_t)RTC_ISR_TSF)
-#define RTC_FLAG_ITSF                     ((uint32_t)RTC_ISR_ITSF)
-#define RTC_FLAG_WUTF                     ((uint32_t)RTC_ISR_WUTF)
-#define RTC_FLAG_ALRBF                    ((uint32_t)RTC_ISR_ALRBF)
-#define RTC_FLAG_ALRAF                    ((uint32_t)RTC_ISR_ALRAF)
-#define RTC_FLAG_INITF                    ((uint32_t)RTC_ISR_INITF)
-#define RTC_FLAG_RSF                      ((uint32_t)RTC_ISR_RSF)
-#define RTC_FLAG_INITS                    ((uint32_t)RTC_ISR_INITS)
-#define RTC_FLAG_SHPF                     ((uint32_t)RTC_ISR_SHPF)
-#define RTC_FLAG_WUTWF                    ((uint32_t)RTC_ISR_WUTWF)
-#define RTC_FLAG_ALRBWF                   ((uint32_t)RTC_ISR_ALRBWF)
-#define RTC_FLAG_ALRAWF                   ((uint32_t)RTC_ISR_ALRAWF)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RTC_Exported_Macros RTC Exported Macros
-  * @{
-  */
-
-/** @brief Reset RTC handle state
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
-
-/**
-  * @brief  Disable the write protection for RTC registers.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)             \
-                        do{                                       \
-                            (__HANDLE__)->Instance->WPR = 0xCA;   \
-                            (__HANDLE__)->Instance->WPR = 0x53;   \
-                          } while(0)
-
-/**
-  * @brief  Enable the write protection for RTC registers.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)              \
-                        do{                                       \
-                            (__HANDLE__)->Instance->WPR = 0xFF;   \
-                          } while(0)
-
-/**
-  * @brief  Enable the RTC ALARMA peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__)                           ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
-
-/**
-  * @brief  Disable the RTC ALARMA peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__)                          ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
-
-/**
-  * @brief  Enable the RTC ALARMB peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__)                           ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
-
-/**
-  * @brief  Disable the RTC ALARMB peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__)                          ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
-
-/**
-  * @brief  Enable the RTC Alarm interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
-  *          This parameter can be any combination of the following values:
-  *             @arg RTC_IT_ALRA: Alarm A interrupt
-  *             @arg RTC_IT_ALRB: Alarm B interrupt
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__)          ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the RTC Alarm interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
-  *         This parameter can be any combination of the following values:
-  *            @arg RTC_IT_ALRA: Alarm A interrupt
-  *            @arg RTC_IT_ALRB: Alarm B interrupt
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
-
-/**
-  * @brief  Check whether the specified RTC Alarm interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt to check.
-  *         This parameter can be:
-  *            @arg RTC_IT_ALRA: Alarm A interrupt
-  *            @arg RTC_IT_ALRB: Alarm B interrupt
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__)                  ((((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) & 0x0000FFFF) != RESET)? SET : RESET)
-
-/**
-  * @brief  Get the selected RTC Alarm's flag status.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Alarm Flag to check.
-  *         This parameter can be:
-  *            @arg RTC_FLAG_ALRAF
-  *            @arg RTC_FLAG_ALRBF
-  *            @arg RTC_FLAG_ALRAWF
-  *            @arg RTC_FLAG_ALRBWF
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__)                (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
-
-/**
-  * @brief  Clear the RTC Alarm's pending flags.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
-  *          This parameter can be:
-  *             @arg RTC_FLAG_ALRAF
-  *             @arg RTC_FLAG_ALRBF
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)                  ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-/**
-  * @brief  Check whether the specified RTC Alarm interrupt has been enabled or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to check.
-  *         This parameter can be:
-  *            @arg RTC_IT_ALRA: Alarm A interrupt
-  *            @arg RTC_IT_ALRB: Alarm B interrupt
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
-
-/**
-  * @brief  Enable interrupt on the RTC Alarm associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_IT()            (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
-  * @brief  Disable interrupt on the RTC Alarm associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_IT()           (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
-
-/**
-  * @brief  Enable event on the RTC Alarm associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT()         (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
-  * @brief  Disable event on the RTC Alarm associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT()         (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
-
-/**
-  * @brief  Enable falling edge trigger on the RTC Alarm associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
-  * @brief  Disable falling edge trigger on the RTC Alarm associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
-
-/**
-  * @brief  Enable rising edge trigger on the RTC Alarm associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
-  * @brief  Disable rising edge trigger on the RTC Alarm associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
-
-/**
-  * @brief  Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();
-
-/**
-  * @brief  Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();
-
-/**
-  * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
-  * @retval Line Status.
-  */
-#define __HAL_RTC_ALARM_EXTI_GET_FLAG()              (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
-  * @brief Clear the RTC Alarm associated Exti line flag.
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()            (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
-  * @brief Generate a Software interrupt on RTC Alarm associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()         (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT)
-/**
-  * @}
-  */
-
-/* Include RTC HAL Extension module */
-#include "stm32f7xx_hal_rtc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RTC_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup RTC_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization and de-initialization functions  ****************************/
-HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
-void       HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
-void       HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
-/**
-  * @}
-  */
-
-/** @addtogroup RTC_Exported_Functions_Group2
-  * @{
-  */
-/* RTC Time and Date functions ************************************************/
-HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
-/**
-  * @}
-  */
-
-/** @addtogroup RTC_Exported_Functions_Group3
-  * @{
-  */
-/* RTC Alarm functions ********************************************************/
-HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
-HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
-void                HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef   HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-void         HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
-/**
-  * @}
-  */
-
-/** @addtogroup RTC_Exported_Functions_Group4
-  * @{
-  */
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef   HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);
-/**
-  * @}
-  */
-
-/** @addtogroup RTC_Exported_Functions_Group5
-  * @{
-  */
-/* Peripheral State functions *************************************************/
-HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RTC_Private_Constants RTC Private Constants
-  * @{
-  */
-/* Masks Definition */
-#define RTC_TR_RESERVED_MASK    ((uint32_t)0x007F7F7FU)
-#define RTC_DR_RESERVED_MASK    ((uint32_t)0x00FFFF3FU)
-#define RTC_INIT_MASK           ((uint32_t)0xFFFFFFFFU)
-#define RTC_RSF_MASK            ((uint32_t)0xFFFFFF5FU)
-
-#define RTC_TIMEOUT_VALUE       1000
-
-#define RTC_EXTI_LINE_ALARM_EVENT             ((uint32_t)EXTI_IMR_IM17)  /*!< External interrupt line 17 Connected to the RTC Alarm event */
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup RTC_Private_Macros RTC Private Macros
-  * @{
-  */
-
-/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
-  * @{
-  */
-#define IS_RTC_HOUR_FORMAT(__FORMAT__) (((__FORMAT__) == RTC_HOURFORMAT_12) || \
-                                        ((__FORMAT__) == RTC_HOURFORMAT_24))
-#define IS_RTC_OUTPUT_POL(__POL__)     (((__POL__) == RTC_OUTPUT_POLARITY_HIGH) || \
-                                        ((__POL__) == RTC_OUTPUT_POLARITY_LOW))
-#define IS_RTC_OUTPUT_TYPE(__TYPE__)   (((__TYPE__) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
-                                        ((__TYPE__) == RTC_OUTPUT_TYPE_PUSHPULL))
-#define IS_RTC_ASYNCH_PREDIV(__PREDIV__)   ((__PREDIV__) <= (uint32_t)0x7F)
-#define IS_RTC_SYNCH_PREDIV(__PREDIV__)    ((__PREDIV__) <= (uint32_t)0x7FFF)
-#define IS_RTC_HOUR12(__HOUR__)            (((__HOUR__) > (uint32_t)0) && ((__HOUR__) <= (uint32_t)12))
-#define IS_RTC_HOUR24(__HOUR__)            ((__HOUR__) <= (uint32_t)23)
-#define IS_RTC_MINUTES(__MINUTES__)        ((__MINUTES__) <= (uint32_t)59)
-#define IS_RTC_SECONDS(__SECONDS__)        ((__SECONDS__) <= (uint32_t)59)
-#define IS_RTC_HOURFORMAT12(__PM__)  (((__PM__) == RTC_HOURFORMAT12_AM) || ((__PM__) == RTC_HOURFORMAT12_PM))
-#define IS_RTC_DAYLIGHT_SAVING(__SAVE__) (((__SAVE__) == RTC_DAYLIGHTSAVING_SUB1H) || \
-                                          ((__SAVE__) == RTC_DAYLIGHTSAVING_ADD1H) || \
-                                          ((__SAVE__) == RTC_DAYLIGHTSAVING_NONE))
-#define IS_RTC_STORE_OPERATION(__OPERATION__) (((__OPERATION__) == RTC_STOREOPERATION_RESET) || \
-                                               ((__OPERATION__) == RTC_STOREOPERATION_SET))
-#define IS_RTC_FORMAT(__FORMAT__) (((__FORMAT__) == RTC_FORMAT_BIN) || ((__FORMAT__) == RTC_FORMAT_BCD))
-#define IS_RTC_YEAR(__YEAR__)              ((__YEAR__) <= (uint32_t)99)
-#define IS_RTC_MONTH(__MONTH__)            (((__MONTH__) >= (uint32_t)1) && ((__MONTH__) <= (uint32_t)12))
-#define IS_RTC_DATE(__DATE__)              (((__DATE__) >= (uint32_t)1) && ((__DATE__) <= (uint32_t)31))
-#define IS_RTC_WEEKDAY(__WEEKDAY__) (((__WEEKDAY__) == RTC_WEEKDAY_MONDAY)    || \
-                                     ((__WEEKDAY__) == RTC_WEEKDAY_TUESDAY)   || \
-                                     ((__WEEKDAY__) == RTC_WEEKDAY_WEDNESDAY) || \
-                                     ((__WEEKDAY__) == RTC_WEEKDAY_THURSDAY)  || \
-                                     ((__WEEKDAY__) == RTC_WEEKDAY_FRIDAY)    || \
-                                     ((__WEEKDAY__) == RTC_WEEKDAY_SATURDAY)  || \
-                                     ((__WEEKDAY__) == RTC_WEEKDAY_SUNDAY))
-
-#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(__DATE__) (((__DATE__) >(uint32_t) 0) && ((__DATE__) <= (uint32_t)31))
-#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(__WEEKDAY__) (((__WEEKDAY__) == RTC_WEEKDAY_MONDAY)    || \
-                                                        ((__WEEKDAY__) == RTC_WEEKDAY_TUESDAY)   || \
-                                                        ((__WEEKDAY__) == RTC_WEEKDAY_WEDNESDAY) || \
-                                                        ((__WEEKDAY__) == RTC_WEEKDAY_THURSDAY)  || \
-                                                        ((__WEEKDAY__) == RTC_WEEKDAY_FRIDAY)    || \
-                                                        ((__WEEKDAY__) == RTC_WEEKDAY_SATURDAY)  || \
-                                                        ((__WEEKDAY__) == RTC_WEEKDAY_SUNDAY))
-#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
-                                                ((__SEL__) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
-#define IS_RTC_ALARM_MASK(__MASK__)  (((__MASK__) & 0x7F7F7F7F) == (uint32_t)RESET)
-#define IS_RTC_ALARM(__ALARM__)      (((__ALARM__) == RTC_ALARM_A) || ((__ALARM__) == RTC_ALARM_B))
-#define IS_RTC_ALARM_SUB_SECOND_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)0x00007FFF)
-#define IS_RTC_ALARM_SUB_SECOND_MASK(__MASK__)   (((__MASK__) == RTC_ALARMSUBSECONDMASK_ALL) || \
-                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
-                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
-                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
-                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
-                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
-                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
-                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
-                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
-                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
-                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
-                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
-                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
-                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
-                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14) || \
-                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_NONE))
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup RTC_Private_Functions RTC Private Functions
-  * @{
-  */
-HAL_StatusTypeDef  RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
-uint8_t            RTC_ByteToBcd2(uint8_t Value);
-uint8_t            RTC_Bcd2ToByte(uint8_t Value);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F7xx_HAL_RTC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_rtc_ex.h b/stmhal/hal/f7/inc/stm32f7xx_hal_rtc_ex.h
deleted file mode 100644
index 7f22612184..0000000000
--- a/stmhal/hal/f7/inc/stm32f7xx_hal_rtc_ex.h
+++ /dev/null
@@ -1,1035 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_rtc_ex.h
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   Header file of RTC HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_RTC_EX_H
-#define __STM32F7xx_HAL_RTC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal_def.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup RTCEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Types RTCEx Exported Types
-  * @{
-  */
-
-/**
-  * @brief  RTC Tamper structure definition
-  */
-typedef struct
-{
-  uint32_t Tamper;                      /*!< Specifies the Tamper Pin.
-                                             This parameter can be a value of @ref  RTCEx_Tamper_Pins_Definitions */
-
-  uint32_t Interrupt;                   /*!< Specifies the Tamper Interrupt.
-                                             This parameter can be a value of @ref  RTCEx_Tamper_Interrupt_Definitions */
-
-  uint32_t Trigger;                     /*!< Specifies the Tamper Trigger.
-                                             This parameter can be a value of @ref  RTCEx_Tamper_Trigger_Definitions */
-
-  uint32_t NoErase;                     /*!< Specifies the Tamper no erase mode.
-                                             This parameter can be a value of @ref  RTCEx_Tamper_EraseBackUp_Definitions */
-
-  uint32_t MaskFlag;                     /*!< Specifies the Tamper Flag masking.
-                                             This parameter can be a value of @ref RTCEx_Tamper_MaskFlag_Definitions   */
-
-  uint32_t Filter;                      /*!< Specifies the RTC Filter Tamper.
-                                             This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */
-
-  uint32_t SamplingFrequency;           /*!< Specifies the sampling frequency.
-                                             This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies_Definitions */
-
-  uint32_t PrechargeDuration;           /*!< Specifies the Precharge Duration .
-                                             This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */
-
-  uint32_t TamperPullUp;                /*!< Specifies the Tamper PullUp .
-                                             This parameter can be a value of @ref RTCEx_Tamper_Pull_UP_Definitions */
-
-  uint32_t TimeStampOnTamperDetection;  /*!< Specifies the TimeStampOnTamperDetection.
-                                             This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */
-}RTC_TamperTypeDef;
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants
-  * @{
-  */
-
-/** @defgroup RTCEx_Output_selection_Definitions RTCEx Output selection Definitions
-  * @{
-  */
-#define RTC_OUTPUT_DISABLE             ((uint32_t)0x00000000U)
-#define RTC_OUTPUT_ALARMA              ((uint32_t)0x00200000U)
-#define RTC_OUTPUT_ALARMB              ((uint32_t)0x00400000U)
-#define RTC_OUTPUT_WAKEUP              ((uint32_t)0x00600000U)
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Backup_Registers_Definitions RTC Backup Registers Definitions
-  * @{
-  */
-#define RTC_BKP_DR0                       ((uint32_t)0x00000000U)
-#define RTC_BKP_DR1                       ((uint32_t)0x00000001U)
-#define RTC_BKP_DR2                       ((uint32_t)0x00000002U)
-#define RTC_BKP_DR3                       ((uint32_t)0x00000003U)
-#define RTC_BKP_DR4                       ((uint32_t)0x00000004U)
-#define RTC_BKP_DR5                       ((uint32_t)0x00000005U)
-#define RTC_BKP_DR6                       ((uint32_t)0x00000006U)
-#define RTC_BKP_DR7                       ((uint32_t)0x00000007U)
-#define RTC_BKP_DR8                       ((uint32_t)0x00000008U)
-#define RTC_BKP_DR9                       ((uint32_t)0x00000009U)
-#define RTC_BKP_DR10                      ((uint32_t)0x0000000AU)
-#define RTC_BKP_DR11                      ((uint32_t)0x0000000BU)
-#define RTC_BKP_DR12                      ((uint32_t)0x0000000CU)
-#define RTC_BKP_DR13                      ((uint32_t)0x0000000DU)
-#define RTC_BKP_DR14                      ((uint32_t)0x0000000EU)
-#define RTC_BKP_DR15                      ((uint32_t)0x0000000FU)
-#define RTC_BKP_DR16                      ((uint32_t)0x00000010U)
-#define RTC_BKP_DR17                      ((uint32_t)0x00000011U)
-#define RTC_BKP_DR18                      ((uint32_t)0x00000012U)
-#define RTC_BKP_DR19                      ((uint32_t)0x00000013U)
-#define RTC_BKP_DR20                      ((uint32_t)0x00000014U)
-#define RTC_BKP_DR21                      ((uint32_t)0x00000015U)
-#define RTC_BKP_DR22                      ((uint32_t)0x00000016U)
-#define RTC_BKP_DR23                      ((uint32_t)0x00000017U)
-#define RTC_BKP_DR24                      ((uint32_t)0x00000018U)
-#define RTC_BKP_DR25                      ((uint32_t)0x00000019U)
-#define RTC_BKP_DR26                      ((uint32_t)0x0000001AU)
-#define RTC_BKP_DR27                      ((uint32_t)0x0000001BU)
-#define RTC_BKP_DR28                      ((uint32_t)0x0000001CU)
-#define RTC_BKP_DR29                      ((uint32_t)0x0000001DU)
-#define RTC_BKP_DR30                      ((uint32_t)0x0000001EU)
-#define RTC_BKP_DR31                      ((uint32_t)0x0000001FU)
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Time_Stamp_Edges_definitions RTCEx Time Stamp Edges definitions
-  * @{
-  */
-#define RTC_TIMESTAMPEDGE_RISING          ((uint32_t)0x00000000U)
-#define RTC_TIMESTAMPEDGE_FALLING         ((uint32_t)0x00000008U)
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_Pins_Definitions RTCEx Tamper Pins Definitions
-  * @{
-  */
-#define RTC_TAMPER_1                    RTC_TAMPCR_TAMP1E
-#define RTC_TAMPER_2                    RTC_TAMPCR_TAMP2E
-#define RTC_TAMPER_3                    RTC_TAMPCR_TAMP3E
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_Interrupt_Definitions RTCEx Tamper Interrupt Definitions
-  * @{
-  */
-#define RTC_TAMPER1_INTERRUPT                RTC_TAMPCR_TAMP1IE
-#define RTC_TAMPER2_INTERRUPT                RTC_TAMPCR_TAMP2IE
-#define RTC_TAMPER3_INTERRUPT                RTC_TAMPCR_TAMP3IE
-#define RTC_ALL_TAMPER_INTERRUPT             RTC_TAMPCR_TAMPIE
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_TimeStamp_Pin_Selection RTCEx TimeStamp Pin Selection
-  * @{
-  */
-#define RTC_TIMESTAMPPIN_DEFAULT            ((uint32_t)0x00000000U)
-#define RTC_TIMESTAMPPIN_POS1               ((uint32_t)0x00000002U)
-#define RTC_TIMESTAMPPIN_POS2               ((uint32_t)0x00000004U)
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_Trigger_Definitions RTCEx Tamper Trigger Definitions
-  * @{
-  */
-#define RTC_TAMPERTRIGGER_RISINGEDGE       ((uint32_t)0x00000000U)
-#define RTC_TAMPERTRIGGER_FALLINGEDGE      ((uint32_t)0x00000002U)
-#define RTC_TAMPERTRIGGER_LOWLEVEL         RTC_TAMPERTRIGGER_RISINGEDGE
-#define RTC_TAMPERTRIGGER_HIGHLEVEL        RTC_TAMPERTRIGGER_FALLINGEDGE
-/**
-  * @}
-  */
-
-  /** @defgroup RTCEx_Tamper_EraseBackUp_Definitions RTCEx Tamper EraseBackUp Definitions
-* @{
-*/
-#define RTC_TAMPER_ERASE_BACKUP_ENABLE               ((uint32_t)0x00000000U)
-#define RTC_TAMPER_ERASE_BACKUP_DISABLE              ((uint32_t)0x00020000U)
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_MaskFlag_Definitions RTCEx Tamper MaskFlag Definitions
-  * @{
-  */
-#define RTC_TAMPERMASK_FLAG_DISABLE                ((uint32_t)0x00000000U)
-#define RTC_TAMPERMASK_FLAG_ENABLE                 ((uint32_t)0x00040000U)
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_Filter_Definitions RTCEx Tamper Filter Definitions
-  * @{
-  */
-#define RTC_TAMPERFILTER_DISABLE   ((uint32_t)0x00000000U)  /*!< Tamper filter is disabled */
-
-#define RTC_TAMPERFILTER_2SAMPLE   ((uint32_t)0x00000800U)  /*!< Tamper is activated after 2
-                                                                consecutive samples at the active level */
-#define RTC_TAMPERFILTER_4SAMPLE   ((uint32_t)0x00001000U)  /*!< Tamper is activated after 4
-                                                                consecutive samples at the active level */
-#define RTC_TAMPERFILTER_8SAMPLE   ((uint32_t)0x00001800U)  /*!< Tamper is activated after 8
-                                                                consecutive samples at the active leve. */
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTCEx Tamper Sampling Frequencies Definitions
-  * @{
-  */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768  ((uint32_t)0x00000000U)  /*!< Each of the tamper inputs are sampled
-                                                                             with a frequency =  RTCCLK / 32768 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384  ((uint32_t)0x00000100U)  /*!< Each of the tamper inputs are sampled
-                                                                             with a frequency =  RTCCLK / 16384 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192   ((uint32_t)0x00000200U)  /*!< Each of the tamper inputs are sampled
-                                                                             with a frequency =  RTCCLK / 8192  */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096   ((uint32_t)0x00000300U)  /*!< Each of the tamper inputs are sampled
-                                                                             with a frequency =  RTCCLK / 4096  */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048   ((uint32_t)0x00000400U)  /*!< Each of the tamper inputs are sampled
-                                                                             with a frequency =  RTCCLK / 2048  */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024   ((uint32_t)0x00000500U)  /*!< Each of the tamper inputs are sampled
-                                                                             with a frequency =  RTCCLK / 1024  */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512    ((uint32_t)0x00000600U)  /*!< Each of the tamper inputs are sampled
-                                                                             with a frequency =  RTCCLK / 512   */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256    ((uint32_t)0x00000700U)  /*!< Each of the tamper inputs are sampled
-                                                                             with a frequency =  RTCCLK / 256   */
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTCEx Tamper Pin Precharge Duration Definitions
-  * @{
-  */
-#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000U)  /*!< Tamper pins are pre-charged before
-                                                                         sampling during 1 RTCCLK cycle */
-#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000U)  /*!< Tamper pins are pre-charged before
-                                                                         sampling during 2 RTCCLK cycles */
-#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000U)  /*!< Tamper pins are pre-charged before
-                                                                         sampling during 4 RTCCLK cycles */
-#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000U)  /*!< Tamper pins are pre-charged before
-                                                                         sampling during 8 RTCCLK cycles */
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTCEx Tamper TimeStampOnTamperDetection Definitions
-  * @{
-  */
-#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE  ((uint32_t)RTC_TAMPCR_TAMPTS)  /*!< TimeStamp on Tamper Detection event saved        */
-#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000U)        /*!< TimeStamp on Tamper Detection event is not saved */
-/**
-  * @}
-  */
-
-/** @defgroup  RTCEx_Tamper_Pull_UP_Definitions RTCEx Tamper Pull UP Definitions
-  * @{
-  */
-#define RTC_TAMPER_PULLUP_ENABLE  ((uint32_t)0x00000000U)            /*!< TimeStamp on Tamper Detection event saved        */
-#define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAMPCR_TAMPPUDIS)   /*!< TimeStamp on Tamper Detection event is not saved */
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Wakeup_Timer_Definitions RTCEx Wakeup Timer Definitions
-  * @{
-  */
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV16        ((uint32_t)0x00000000U)
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV8         ((uint32_t)0x00000001U)
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV4         ((uint32_t)0x00000002U)
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV2         ((uint32_t)0x00000003U)
-#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS      ((uint32_t)0x00000004U)
-#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS      ((uint32_t)0x00000006U)
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth calib period Definitions
-  * @{
-  */
-#define RTC_SMOOTHCALIB_PERIOD_32SEC   ((uint32_t)0x00000000U)  /*!< If RTCCLK = 32768 Hz, Smooth calibration
-                                                                    period is 32s,  else 2exp20 RTCCLK seconds */
-#define RTC_SMOOTHCALIB_PERIOD_16SEC   ((uint32_t)0x00002000U)  /*!< If RTCCLK = 32768 Hz, Smooth calibration
-                                                                    period is 16s, else 2exp19 RTCCLK seconds */
-#define RTC_SMOOTHCALIB_PERIOD_8SEC    ((uint32_t)0x00004000U)  /*!< If RTCCLK = 32768 Hz, Smooth calibration
-                                                                    period is 8s, else 2exp18 RTCCLK seconds */
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTCEx Smooth calib Plus pulses Definitions
-  * @{
-  */
-#define RTC_SMOOTHCALIB_PLUSPULSES_SET    ((uint32_t)0x00008000U)  /*!< The number of RTCCLK pulses added
-                                                                       during a X -second window = Y - CALM[8:0]
-                                                                       with Y = 512, 256, 128 when X = 32, 16, 8 */
-#define RTC_SMOOTHCALIB_PLUSPULSES_RESET  ((uint32_t)0x00000000U)  /*!< The number of RTCCLK pulses subbstited
-                                                                       during a 32-second window = CALM[8:0] */
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Add_1_Second_Parameter_Definitions RTCEx Add 1 Second Parameter Definitions
-  * @{
-  */
-#define RTC_SHIFTADD1S_RESET      ((uint32_t)0x00000000U)
-#define RTC_SHIFTADD1S_SET        ((uint32_t)0x80000000U)
-/**
-  * @}
-  */
-
- /** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output selection Definitions
-  * @{
-  */
-#define RTC_CALIBOUTPUT_512HZ            ((uint32_t)0x00000000U)
-#define RTC_CALIBOUTPUT_1HZ              ((uint32_t)0x00080000U)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros
-  * @{
-  */
-
-/**
-  * @brief  Enable the RTC WakeUp Timer peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__)                     ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
-
-/**
-  * @brief  Disable the RTC WakeUp Timer peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__)                    ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
-
-/**
-  * @brief  Enable the RTC WakeUpTimer interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
-  *         This parameter can be:
-  *            @arg RTC_IT_WUT: WakeUpTimer interrupt
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the RTC WakeUpTimer interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
-  *         This parameter can be:
-  *            @arg RTC_IT_WUT: WakeUpTimer interrupt
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
-
-/**
-  * @brief  Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to check.
-  *         This parameter can be:
-  *            @arg RTC_IT_WUT:  WakeUpTimer interrupt
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__)       (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
-
-/**
-  * @brief  Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Wake Up timer interrupt sources to check.
-  *         This parameter can be:
-  *            @arg RTC_IT_WUT:  WakeUpTimer interrupt
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)   (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
-
-/**
-  * @brief  Get the selected RTC WakeUpTimer's flag status.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC WakeUpTimer Flag is pending or not.
-  *          This parameter can be:
-  *             @arg RTC_FLAG_WUTF
-  *             @arg RTC_FLAG_WUTWF
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__)   (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
-
-/**
-  * @brief  Clear the RTC Wake Up timer's pending flags.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC WakeUpTimer Flag to clear.
-  *         This parameter can be:
-  *            @arg RTC_FLAG_WUTF
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-/**
-  * @brief  Enable the RTC Tamper1 input detection.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP1E))
-
-/**
-  * @brief  Disable the RTC Tamper1 input detection.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP1E))
-
-/**
-  * @brief  Enable the RTC Tamper2 input detection.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E))
-
-/**
-  * @brief  Disable the RTC Tamper2 input detection.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E))
-
-/**
-  * @brief  Enable the RTC Tamper3 input detection.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP3E))
-
-/**
-  * @brief  Disable the RTC Tamper3 input detection.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP3E))
-
-/**
-  * @brief  Check whether the specified RTC Tamper interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Tamper interrupt to check.
-  *         This parameter can be:
-  *            @arg  RTC_IT_TAMP: All tampers interrupts
-  *            @arg  RTC_IT_TAMP1: Tamper1 interrupt
-  *            @arg  RTC_IT_TAMP2: Tamper2 interrupt
-  *            @arg  RTC_IT_TAMP3: Tamper3 interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)           (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3)) != RESET) ? SET : RESET) : \
-                                                                      ((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5)) != RESET) ? SET : RESET) : \
-                                                                                                          (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7)) != RESET) ? SET : RESET))
-
-/**
-  * @brief  Check whether the specified RTC Tamper interrupt has been enabled or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Tamper interrupt source to check.
-  *         This parameter can be:
-  *            @arg  RTC_IT_TAMP: All tampers interrupts
-  *            @arg  RTC_IT_TAMP1: Tamper1 interrupt
-  *            @arg  RTC_IT_TAMP2: Tamper2 interrupt
-  *            @arg  RTC_IT_TAMP3: Tamper3 interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)    (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
-
-/**
-  * @brief  Get the selected RTC Tamper's flag status.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Tamper Flag is pending or not.
-  *          This parameter can be:
-  *             @arg RTC_FLAG_TAMP1F: Tamper1 flag
-  *             @arg RTC_FLAG_TAMP2F: Tamper2 flag
-  *             @arg RTC_FLAG_TAMP3F: Tamper3 flag
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__)        (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
-
-/**
-  * @brief  Clear the RTC Tamper's pending flags.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Tamper Flag sources to clear.
-  *          This parameter can be:
-  *             @arg RTC_FLAG_TAMP1F: Tamper1 flag
-  *             @arg RTC_FLAG_TAMP2F: Tamper2 flag
-  *             @arg RTC_FLAG_TAMP3F: Tamper3 flag
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-/**
-  * @brief  Enable the RTC TimeStamp peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__)                       ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
-
-/**
-  * @brief  Disable the RTC TimeStamp peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
-
-/**
-  * @brief  Enable the RTC TimeStamp interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
-  *         This parameter can be:
-  *            @arg RTC_IT_TS: TimeStamp interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the RTC TimeStamp interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
-  *         This parameter can be:
-  *            @arg RTC_IT_TS: TimeStamp interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
-
-/**
-  * @brief  Check whether the specified RTC TimeStamp interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to check.
-  *         This parameter can be:
-  *            @arg RTC_IT_TS: TimeStamp interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__)        (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
-
-/**
-  * @brief  Check whether the specified RTC Time Stamp interrupt has been enabled or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Time Stamp interrupt source to check.
-  *         This parameter can be:
-  *            @arg RTC_IT_TS: TimeStamp interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
-
-/**
-  * @brief  Get the selected RTC TimeStamp's flag status.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC TimeStamp Flag is pending or not.
-  *         This parameter can be:
-  *            @arg RTC_FLAG_TSF
-  *            @arg RTC_FLAG_TSOVF
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)     (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
-
-/**
-  * @brief  Clear the RTC Time Stamp's pending flags.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Alarm Flag sources to clear.
-  *          This parameter can be:
-  *             @arg RTC_FLAG_TSF
-  *             @arg RTC_FLAG_TSOVF
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)   ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-/**
-  * @brief  Enable the RTC internal TimeStamp peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE))
-
-/**
-  * @brief  Disable the RTC internal TimeStamp peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE))
-
-/**
-  * @brief  Get the selected RTC Internal Time Stamp's flag status.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Internal Time Stamp Flag is pending or not.
-  *         This parameter can be:
-  *            @arg RTC_FLAG_ITSF
-  * @retval None
-  */
-#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)    (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
-
-/**
-  * @brief  Clear the RTC Internal Time Stamp's pending flags.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Internal Time Stamp Flag source to clear.
-  *          This parameter can be:
-  *             @arg RTC_FLAG_ITSF
-  * @retval None
-  */
-#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)  ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0003FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-/**
-  * @brief  Enable the RTC calibration output.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
-
-/**
-  * @brief  Disable the calibration output.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
-
-/**
-  * @brief  Enable the clock reference detection.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
-
-/**
-  * @brief  Disable the clock reference detection.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
-
-/**
-  * @brief  Get the selected RTC shift operation's flag status.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC shift operation Flag is pending or not.
-  *          This parameter can be:
-  *             @arg RTC_FLAG_SHPF
-  * @retval None
-  */
-#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__)         (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
-
-/**
-  * @brief  Enable interrupt on the RTC WakeUp Timer associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT()       (EXTI->IMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
-  * @brief  Disable interrupt on the RTC WakeUp Timer associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT()      (EXTI->IMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
-
-/**
-  * @brief  Enable event on the RTC WakeUp Timer associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT()    (EXTI->EMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
-  * @brief  Disable event on the RTC WakeUp Timer associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT()   (EXTI->EMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
-
-/**
-  * @brief  Enable falling edge trigger on the RTC WakeUp Timer associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
-  * @brief  Disable falling edge trigger on the RTC WakeUp Timer associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
-
-/**
-  * @brief  Enable rising edge trigger on the RTC WakeUp Timer associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
-  * @brief  Disable rising edge trigger on the RTC WakeUp Timer associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
-
-/**
-  * @brief  Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();
-
-/**
-  * @brief  Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
-  * This parameter can be:
-  * @retval None.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();
-
-/**
-  * @brief Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not.
-  * @retval Line Status.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG()              (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
-  * @brief Clear the RTC WakeUp Timer associated Exti line flag.
-  * @retval None.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG()            (EXTI->PR = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
-  * @brief Generate a Software interrupt on the RTC WakeUp Timer associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT()         (EXTI->SWIER |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
-  * @brief  Enable interrupt on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()        (EXTI->IMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
-  * @brief  Disable interrupt on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()       (EXTI->IMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
-
-/**
-  * @brief  Enable event on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT()    (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
-  * @brief  Disable event on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT()   (EXTI->EMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
-
-/**
-  * @brief  Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
-  * @brief  Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
-
-/**
-  * @brief  Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
-  * @brief  Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
-
-/**
-  * @brief  Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE();
-
-/**
-  * @brief  Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
-  * This parameter can be:
-  * @retval None.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE();
-
-/**
-  * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
-  * @retval Line Status.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()         (EXTI->PR & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
-  * @brief Clear the RTC Tamper and Timestamp associated Exti line flag.
-  * @retval None.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()       (EXTI->PR = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
-  * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line
-  * @retval None.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()    (EXTI->SWIER |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
-  * @{
-  */
-
-/** @addtogroup RTCEx_Exported_Functions_Group1
-  * @{
-  */
-
-/* RTC TimeStamp and Tamper functions *****************************************/
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format);
-
-HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
-HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
-void              HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
-
-void              HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
-void              HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
-void              HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc);
-void              HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-/**
-  * @}
-  */
-
-/** @addtogroup RTCEx_Exported_Functions_Group2
-  * @{
-  */
-/* RTC Wake-up functions ******************************************************/
-HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
-HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
-uint32_t          HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
-uint32_t          HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
-void              HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
-void              HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-/**
-  * @}
-  */
-
-/** @addtogroup RTCEx_Exported_Functions_Group3
-  * @{
-  */
-/* Extension Control functions ************************************************/
-void              HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
-uint32_t          HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
-
-HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue);
-HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS);
-HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);
-/**
-  * @}
-  */
-
-/** @addtogroup RTCEx_Exported_Functions_Group4
-  * @{
-  */
-/* Extension RTC features functions *******************************************/
-void              HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RTCEx_Private_Constants RTCEx Private Constants
-  * @{
-  */
-#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT  ((uint32_t)EXTI_IMR_IM21)  /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
-#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT       ((uint32_t)EXTI_IMR_IM22)  /*!< External interrupt line 22 Connected to the RTC Wake-up event */
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RTCEx_Private_Constants RTCEx Private Constants
-  * @{
-  */
-/* Masks Definition */
-#define RTC_TAMPCR_TAMPXE     ((uint32_t) (RTC_TAMPCR_TAMP3E | RTC_TAMPCR_TAMP2E | RTC_TAMPCR_TAMP1E))
-#define RTC_TAMPCR_TAMPXIE    ((uint32_t) (RTC_TAMPER1_INTERRUPT | RTC_TAMPER2_INTERRUPT | RTC_TAMPER3_INTERRUPT | RTC_ALL_TAMPER_INTERRUPT))
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup RTCEx_Private_Macros RTCEx Private Macros
-  * @{
-  */
-
-/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
-  * @{
-  */
-#define IS_RTC_OUTPUT(__OUTPUT__)      (((__OUTPUT__) == RTC_OUTPUT_DISABLE) || \
-                                        ((__OUTPUT__) == RTC_OUTPUT_ALARMA)  || \
-                                        ((__OUTPUT__) == RTC_OUTPUT_ALARMB)  || \
-                                        ((__OUTPUT__) == RTC_OUTPUT_WAKEUP))
-#define IS_RTC_BKP(__BKP__)               ((__BKP__) < (uint32_t) RTC_BKP_NUMBER)
-#define IS_TIMESTAMP_EDGE(__EDGE__) (((__EDGE__) == RTC_TIMESTAMPEDGE_RISING) || \
-                                     ((__EDGE__) == RTC_TIMESTAMPEDGE_FALLING))
-#define IS_RTC_TAMPER(__TAMPER__)   ((((__TAMPER__) & ((uint32_t)(0xFFFFFFFFU ^ RTC_TAMPCR_TAMPXE))) == 0x00U) && ((__TAMPER__) != (uint32_t)RESET))
-
-#define IS_RTC_TAMPER_INTERRUPT(__INTERRUPT__)  ((((__INTERRUPT__) & (uint32_t)(0xFFFFFFFFU ^ RTC_TAMPCR_TAMPXIE)) == 0x00U) && ((__INTERRUPT__) != (uint32_t)RESET))
-
-#define IS_RTC_TIMESTAMP_PIN(__PIN__) (((__PIN__) == RTC_TIMESTAMPPIN_DEFAULT) || \
-                                       ((__PIN__) == RTC_TIMESTAMPPIN_POS1)  || \
-                                       ((__PIN__) == RTC_TIMESTAMPPIN_POS2))
-#define IS_RTC_TAMPER_TRIGGER(__TRIGGER__) (((__TRIGGER__) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
-                                        ((__TRIGGER__) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
-                                        ((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
-                                        ((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL))
-#define IS_RTC_TAMPER_ERASE_MODE(__MODE__)             (((__MODE__) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \
-                                                        ((__MODE__) == RTC_TAMPER_ERASE_BACKUP_DISABLE))
-#define IS_RTC_TAMPER_MASKFLAG_STATE(__STATE__)     (((__STATE__) == RTC_TAMPERMASK_FLAG_ENABLE) || \
-                                                     ((__STATE__) == RTC_TAMPERMASK_FLAG_DISABLE))
-#define IS_RTC_TAMPER_FILTER(__FILTER__)  (((__FILTER__) == RTC_TAMPERFILTER_DISABLE) || \
-                                       ((__FILTER__) == RTC_TAMPERFILTER_2SAMPLE) || \
-                                       ((__FILTER__) == RTC_TAMPERFILTER_4SAMPLE) || \
-                                       ((__FILTER__) == RTC_TAMPERFILTER_8SAMPLE))
-#define IS_RTC_TAMPER_SAMPLING_FREQ(__FREQ__) (((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
-                                           ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
-                                           ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
-                                           ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
-                                           ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
-                                           ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
-                                           ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512)  || \
-                                           ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))
-#define IS_RTC_TAMPER_PRECHARGE_DURATION(__DURATION__) (((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
-                                                    ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
-                                                    ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
-                                                    ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))
-#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(__DETECTION__) (((__DETECTION__) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
-                                                              ((__DETECTION__) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
-#define IS_RTC_TAMPER_PULLUP_STATE(__STATE__) (((__STATE__) == RTC_TAMPER_PULLUP_ENABLE) || \
-                                       ((__STATE__) == RTC_TAMPER_PULLUP_DISABLE))
-#define IS_RTC_WAKEUP_CLOCK(__CLOCK__) (((__CLOCK__) == RTC_WAKEUPCLOCK_RTCCLK_DIV16)       || \
-                                    ((__CLOCK__) == RTC_WAKEUPCLOCK_RTCCLK_DIV8)    || \
-                                    ((__CLOCK__) == RTC_WAKEUPCLOCK_RTCCLK_DIV4)    || \
-                                    ((__CLOCK__) == RTC_WAKEUPCLOCK_RTCCLK_DIV2)    || \
-                                    ((__CLOCK__) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
-                                    ((__CLOCK__) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
-
-#define IS_RTC_WAKEUP_COUNTER(__COUNTER__)  ((__COUNTER__) <= 0xFFFF)
-#define IS_RTC_SMOOTH_CALIB_PERIOD(__PERIOD__) (((__PERIOD__) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
-                                                ((__PERIOD__) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
-                                                ((__PERIOD__) == RTC_SMOOTHCALIB_PERIOD_8SEC))
-#define IS_RTC_SMOOTH_CALIB_PLUS(__PLUS__) (((__PLUS__) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
-                                            ((__PLUS__) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
-#define  IS_RTC_SMOOTH_CALIB_MINUS(__VALUE__) ((__VALUE__) <= 0x000001FF)
-#define IS_RTC_SHIFT_ADD1S(__SEL__) (((__SEL__) == RTC_SHIFTADD1S_RESET) || \
-                                     ((__SEL__) == RTC_SHIFTADD1S_SET))
-#define IS_RTC_SHIFT_SUBFS(__FS__) ((__FS__) <= 0x00007FFF)
-#define IS_RTC_CALIB_OUTPUT(__OUTPUT__)  (((__OUTPUT__) == RTC_CALIBOUTPUT_512HZ) || \
-                                          ((__OUTPUT__) == RTC_CALIBOUTPUT_1HZ))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F7xx_HAL_RTC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_sd.h b/stmhal/hal/f7/inc/stm32f7xx_hal_sd.h
deleted file mode 100644
index 4faa545988..0000000000
--- a/stmhal/hal/f7/inc/stm32f7xx_hal_sd.h
+++ /dev/null
@@ -1,776 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_sd.h
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   Header file of SD HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_SD_H
-#define __STM32F7xx_HAL_SD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_ll_sdmmc.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup SD SD
-  * @brief SD HAL module driver
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup SD_Exported_Types SD Exported Types
-  * @{
-  */
-
-/** @defgroup SD_Exported_Types_Group1 SD Handle Structure definition
-  * @{
-  */
-#define SD_InitTypeDef      SDMMC_InitTypeDef
-#define SD_TypeDef          SDMMC_TypeDef
-
-typedef struct
-{
-  SD_TypeDef                   *Instance;        /*!< SDMMC register base address                     */
-
-  SD_InitTypeDef               Init;             /*!< SD required parameters                         */
-
-  HAL_LockTypeDef              Lock;             /*!< SD locking object                              */
-
-  uint32_t                     CardType;         /*!< SD card type                                   */
-
-  uint32_t                     RCA;              /*!< SD relative card address                       */
-
-  uint32_t                     CSD[4];           /*!< SD card specific data table                    */
-
-  uint32_t                     CID[4];           /*!< SD card identification number table            */
-
-  __IO uint32_t                SdTransferCplt;   /*!< SD transfer complete flag in non blocking mode */
-
-  __IO uint32_t                SdTransferErr;    /*!< SD transfer error flag in non blocking mode    */
-
-  __IO uint32_t                DmaTransferCplt;  /*!< SD DMA transfer complete flag                  */
-
-  __IO uint32_t                SdOperation;      /*!< SD transfer operation (read/write)             */
-
-  DMA_HandleTypeDef            *hdmarx;          /*!< SD Rx DMA handle parameters                    */
-
-  DMA_HandleTypeDef            *hdmatx;          /*!< SD Tx DMA handle parameters                    */
-
-}SD_HandleTypeDef;
-/**
-  * @}
-  */
-
-/** @defgroup SD_Exported_Types_Group2 Card Specific Data: CSD Register
-  * @{
-  */
-typedef struct
-{
-  __IO uint8_t  CSDStruct;            /*!< CSD structure                         */
-  __IO uint8_t  SysSpecVersion;       /*!< System specification version          */
-  __IO uint8_t  Reserved1;            /*!< Reserved                              */
-  __IO uint8_t  TAAC;                 /*!< Data read access time 1               */
-  __IO uint8_t  NSAC;                 /*!< Data read access time 2 in CLK cycles */
-  __IO uint8_t  MaxBusClkFrec;        /*!< Max. bus clock frequency              */
-  __IO uint16_t CardComdClasses;      /*!< Card command classes                  */
-  __IO uint8_t  RdBlockLen;           /*!< Max. read data block length           */
-  __IO uint8_t  PartBlockRead;        /*!< Partial blocks for read allowed       */
-  __IO uint8_t  WrBlockMisalign;      /*!< Write block misalignment              */
-  __IO uint8_t  RdBlockMisalign;      /*!< Read block misalignment               */
-  __IO uint8_t  DSRImpl;              /*!< DSR implemented                       */
-  __IO uint8_t  Reserved2;            /*!< Reserved                              */
-  __IO uint32_t DeviceSize;           /*!< Device Size                           */
-  __IO uint8_t  MaxRdCurrentVDDMin;   /*!< Max. read current @ VDD min           */
-  __IO uint8_t  MaxRdCurrentVDDMax;   /*!< Max. read current @ VDD max           */
-  __IO uint8_t  MaxWrCurrentVDDMin;   /*!< Max. write current @ VDD min          */
-  __IO uint8_t  MaxWrCurrentVDDMax;   /*!< Max. write current @ VDD max          */
-  __IO uint8_t  DeviceSizeMul;        /*!< Device size multiplier                */
-  __IO uint8_t  EraseGrSize;          /*!< Erase group size                      */
-  __IO uint8_t  EraseGrMul;           /*!< Erase group size multiplier           */
-  __IO uint8_t  WrProtectGrSize;      /*!< Write protect group size              */
-  __IO uint8_t  WrProtectGrEnable;    /*!< Write protect group enable            */
-  __IO uint8_t  ManDeflECC;           /*!< Manufacturer default ECC              */
-  __IO uint8_t  WrSpeedFact;          /*!< Write speed factor                    */
-  __IO uint8_t  MaxWrBlockLen;        /*!< Max. write data block length          */
-  __IO uint8_t  WriteBlockPaPartial;  /*!< Partial blocks for write allowed      */
-  __IO uint8_t  Reserved3;            /*!< Reserved                              */
-  __IO uint8_t  ContentProtectAppli;  /*!< Content protection application        */
-  __IO uint8_t  FileFormatGrouop;     /*!< File format group                     */
-  __IO uint8_t  CopyFlag;             /*!< Copy flag (OTP)                       */
-  __IO uint8_t  PermWrProtect;        /*!< Permanent write protection            */
-  __IO uint8_t  TempWrProtect;        /*!< Temporary write protection            */
-  __IO uint8_t  FileFormat;           /*!< File format                           */
-  __IO uint8_t  ECC;                  /*!< ECC code                              */
-  __IO uint8_t  CSD_CRC;              /*!< CSD CRC                               */
-  __IO uint8_t  Reserved4;            /*!< Always 1                              */
-
-}HAL_SD_CSDTypedef;
-/**
-  * @}
-  */
-
-/** @defgroup SD_Exported_Types_Group3 Card Identification Data: CID Register
-  * @{
-  */
-typedef struct
-{
-  __IO uint8_t  ManufacturerID;  /*!< Manufacturer ID       */
-  __IO uint16_t OEM_AppliID;     /*!< OEM/Application ID    */
-  __IO uint32_t ProdName1;       /*!< Product Name part1    */
-  __IO uint8_t  ProdName2;       /*!< Product Name part2    */
-  __IO uint8_t  ProdRev;         /*!< Product Revision      */
-  __IO uint32_t ProdSN;          /*!< Product Serial Number */
-  __IO uint8_t  Reserved1;       /*!< Reserved1             */
-  __IO uint16_t ManufactDate;    /*!< Manufacturing Date    */
-  __IO uint8_t  CID_CRC;         /*!< CID CRC               */
-  __IO uint8_t  Reserved2;       /*!< Always 1              */
-
-}HAL_SD_CIDTypedef;
-/**
-  * @}
-  */
-
-/** @defgroup SD_Exported_Types_Group4 SD Card Status returned by ACMD13
-  * @{
-  */
-typedef struct
-{
-  __IO uint8_t  DAT_BUS_WIDTH;           /*!< Shows the currently defined data bus width                 */
-  __IO uint8_t  SECURED_MODE;            /*!< Card is in secured mode of operation                       */
-  __IO uint16_t SD_CARD_TYPE;            /*!< Carries information about card type                        */
-  __IO uint32_t SIZE_OF_PROTECTED_AREA;  /*!< Carries information about the capacity of protected area   */
-  __IO uint8_t  SPEED_CLASS;             /*!< Carries information about the speed class of the card      */
-  __IO uint8_t  PERFORMANCE_MOVE;        /*!< Carries information about the card's performance move      */
-  __IO uint8_t  AU_SIZE;                 /*!< Carries information about the card's allocation unit size  */
-  __IO uint16_t ERASE_SIZE;              /*!< Determines the number of AUs to be erased in one operation */
-  __IO uint8_t  ERASE_TIMEOUT;           /*!< Determines the timeout for any number of AU erase          */
-  __IO uint8_t  ERASE_OFFSET;            /*!< Carries information about the erase offset                 */
-
-}HAL_SD_CardStatusTypedef;
-/**
-  * @}
-  */
-
-/** @defgroup SD_Exported_Types_Group5 SD Card information structure
-  * @{
-  */
-typedef struct
-{
-  HAL_SD_CSDTypedef   SD_csd;         /*!< SD card specific data register         */
-  HAL_SD_CIDTypedef   SD_cid;         /*!< SD card identification number register */
-  uint64_t            CardCapacity;   /*!< Card capacity                          */
-  uint32_t            CardBlockSize;  /*!< Card block size                        */
-  uint16_t            RCA;            /*!< SD relative card address               */
-  uint8_t             CardType;       /*!< SD card type                           */
-
-}HAL_SD_CardInfoTypedef;
-/**
-  * @}
-  */
-
-/** @defgroup SD_Exported_Types_Group6 SD Error status enumeration Structure definition
-  * @{
-  */
-typedef enum
-{
-/**
-  * @brief  SD specific error defines
-  */
-  SD_CMD_CRC_FAIL                    = (1),   /*!< Command response received (but CRC check failed)              */
-  SD_DATA_CRC_FAIL                   = (2),   /*!< Data block sent/received (CRC check failed)                   */
-  SD_CMD_RSP_TIMEOUT                 = (3),   /*!< Command response timeout                                      */
-  SD_DATA_TIMEOUT                    = (4),   /*!< Data timeout                                                  */
-  SD_TX_UNDERRUN                     = (5),   /*!< Transmit FIFO underrun                                        */
-  SD_RX_OVERRUN                      = (6),   /*!< Receive FIFO overrun                                          */
-  SD_START_BIT_ERR                   = (7),   /*!< Start bit not detected on all data signals in wide bus mode   */
-  SD_CMD_OUT_OF_RANGE                = (8),   /*!< Command's argument was out of range.                          */
-  SD_ADDR_MISALIGNED                 = (9),   /*!< Misaligned address                                            */
-  SD_BLOCK_LEN_ERR                   = (10),  /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */
-  SD_ERASE_SEQ_ERR                   = (11),  /*!< An error in the sequence of erase command occurs.            */
-  SD_BAD_ERASE_PARAM                 = (12),  /*!< An invalid selection for erase groups                        */
-  SD_WRITE_PROT_VIOLATION            = (13),  /*!< Attempt to program a write protect block                     */
-  SD_LOCK_UNLOCK_FAILED              = (14),  /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */
-  SD_COM_CRC_FAILED                  = (15),  /*!< CRC check of the previous command failed                     */
-  SD_ILLEGAL_CMD                     = (16),  /*!< Command is not legal for the card state                      */
-  SD_CARD_ECC_FAILED                 = (17),  /*!< Card internal ECC was applied but failed to correct the data */
-  SD_CC_ERROR                        = (18),  /*!< Internal card controller error                               */
-  SD_GENERAL_UNKNOWN_ERROR           = (19),  /*!< General or unknown error                                     */
-  SD_STREAM_READ_UNDERRUN            = (20),  /*!< The card could not sustain data transfer in stream read operation. */
-  SD_STREAM_WRITE_OVERRUN            = (21),  /*!< The card could not sustain data programming in stream mode   */
-  SD_CID_CSD_OVERWRITE               = (22),  /*!< CID/CSD overwrite error                                      */
-  SD_WP_ERASE_SKIP                   = (23),  /*!< Only partial address space was erased                        */
-  SD_CARD_ECC_DISABLED               = (24),  /*!< Command has been executed without using internal ECC         */
-  SD_ERASE_RESET                     = (25),  /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */
-  SD_AKE_SEQ_ERROR                   = (26),  /*!< Error in sequence of authentication.                         */
-  SD_INVALID_VOLTRANGE               = (27),
-  SD_ADDR_OUT_OF_RANGE               = (28),
-  SD_SWITCH_ERROR                    = (29),
-  SD_SDMMC_DISABLED                  = (30),
-  SD_SDMMC_FUNCTION_BUSY             = (31),
-  SD_SDMMC_FUNCTION_FAILED           = (32),
-  SD_SDMMC_UNKNOWN_FUNCTION          = (33),
-
-/**
-  * @brief  Standard error defines
-  */
-  SD_INTERNAL_ERROR                  = (34),
-  SD_NOT_CONFIGURED                  = (35),
-  SD_REQUEST_PENDING                 = (36),
-  SD_REQUEST_NOT_APPLICABLE          = (37),
-  SD_INVALID_PARAMETER               = (38),
-  SD_UNSUPPORTED_FEATURE             = (39),
-  SD_UNSUPPORTED_HW                  = (40),
-  SD_ERROR                           = (41),
-  SD_OK                              = (0)
-
-}HAL_SD_ErrorTypedef;
-/**
-  * @}
-  */
-
-/** @defgroup SD_Exported_Types_Group7 SD Transfer state enumeration structure
-  * @{
-  */
-typedef enum
-{
-  SD_TRANSFER_OK    = 0,  /*!< Transfer success      */
-  SD_TRANSFER_BUSY  = 1,  /*!< Transfer is occurring */
-  SD_TRANSFER_ERROR = 2   /*!< Transfer failed       */
-
-}HAL_SD_TransferStateTypedef;
-/**
-  * @}
-  */
-
-/** @defgroup SD_Exported_Types_Group8 SD Card State enumeration structure
-  * @{
-  */
-typedef enum
-{
-  SD_CARD_READY                  = ((uint32_t)0x00000001U),  /*!< Card state is ready                     */
-  SD_CARD_IDENTIFICATION         = ((uint32_t)0x00000002U),  /*!< Card is in identification state         */
-  SD_CARD_STANDBY                = ((uint32_t)0x00000003U),  /*!< Card is in standby state                */
-  SD_CARD_TRANSFER               = ((uint32_t)0x00000004U),  /*!< Card is in transfer state               */
-  SD_CARD_SENDING                = ((uint32_t)0x00000005U),  /*!< Card is sending an operation            */
-  SD_CARD_RECEIVING              = ((uint32_t)0x00000006U),  /*!< Card is receiving operation information */
-  SD_CARD_PROGRAMMING            = ((uint32_t)0x00000007U),  /*!< Card is in programming state            */
-  SD_CARD_DISCONNECTED           = ((uint32_t)0x00000008U),  /*!< Card is disconnected                    */
-  SD_CARD_ERROR                  = ((uint32_t)0x000000FFU)   /*!< Card is in error state                  */
-
-}HAL_SD_CardStateTypedef;
-/**
-  * @}
-  */
-
-/** @defgroup SD_Exported_Types_Group9 SD Operation enumeration structure
-  * @{
-  */
-typedef enum
-{
-  SD_READ_SINGLE_BLOCK    = 0U,  /*!< Read single block operation      */
-  SD_READ_MULTIPLE_BLOCK  = 1U,  /*!< Read multiple blocks operation   */
-  SD_WRITE_SINGLE_BLOCK   = 2U,  /*!< Write single block operation     */
-  SD_WRITE_MULTIPLE_BLOCK = 3U   /*!< Write multiple blocks operation  */
-
-}HAL_SD_OperationTypedef;
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SD_Exported_Constants SD Exported Constants
-  * @{
-  */
-
-/**
-  * @brief SD Commands Index
-  */
-#define SD_CMD_GO_IDLE_STATE                       ((uint8_t)0U)   /*!< Resets the SD memory card.                                                               */
-#define SD_CMD_SEND_OP_COND                        ((uint8_t)1U)   /*!< Sends host capacity support information and activates the card's initialization process. */
-#define SD_CMD_ALL_SEND_CID                        ((uint8_t)2U)   /*!< Asks any card connected to the host to send the CID numbers on the CMD line.             */
-#define SD_CMD_SET_REL_ADDR                        ((uint8_t)3U)   /*!< Asks the card to publish a new relative address (RCA).                                   */
-#define SD_CMD_SET_DSR                             ((uint8_t)4U)   /*!< Programs the DSR of all cards.                                                           */
-#define SD_CMD_SDMMC_SEN_OP_COND                   ((uint8_t)5U)   /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
-                                                                       operating condition register (OCR) content in the response on the CMD line.              */
-#define SD_CMD_HS_SWITCH                           ((uint8_t)6U)   /*!< Checks switchable function (mode 0) and switch card function (mode 1).                   */
-#define SD_CMD_SEL_DESEL_CARD                      ((uint8_t)7U)   /*!< Selects the card by its own relative address and gets deselected by any other address    */
-#define SD_CMD_HS_SEND_EXT_CSD                     ((uint8_t)8U)   /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
-                                                                       and asks the card whether card supports voltage.                                         */
-#define SD_CMD_SEND_CSD                            ((uint8_t)9U)   /*!< Addressed card sends its card specific data (CSD) on the CMD line.                       */
-#define SD_CMD_SEND_CID                            ((uint8_t)10U)  /*!< Addressed card sends its card identification (CID) on the CMD line.                      */
-#define SD_CMD_READ_DAT_UNTIL_STOP                 ((uint8_t)11U)  /*!< SD card doesn't support it.                                                              */
-#define SD_CMD_STOP_TRANSMISSION                   ((uint8_t)12U)  /*!< Forces the card to stop transmission.                                                    */
-#define SD_CMD_SEND_STATUS                         ((uint8_t)13U)  /*!< Addressed card sends its status register.                                                */
-#define SD_CMD_HS_BUSTEST_READ                     ((uint8_t)14U)
-#define SD_CMD_GO_INACTIVE_STATE                   ((uint8_t)15U)  /*!< Sends an addressed card into the inactive state.                                         */
-#define SD_CMD_SET_BLOCKLEN                        ((uint8_t)16U)  /*!< Sets the block length (in bytes for SDSC) for all following block commands
-                                                                       (read, write, lock). Default block length is fixed to 512 Bytes. Not effective
-                                                                       for SDHS and SDXC.                                                                       */
-#define SD_CMD_READ_SINGLE_BLOCK                   ((uint8_t)17U)  /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
-                                                                       fixed 512 bytes in case of SDHC and SDXC.                                                */
-#define SD_CMD_READ_MULT_BLOCK                     ((uint8_t)18U)  /*!< Continuously transfers data blocks from card to host until interrupted by
-                                                                       STOP_TRANSMISSION command.                                                               */
-#define SD_CMD_HS_BUSTEST_WRITE                    ((uint8_t)19U)  /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104.                                    */
-#define SD_CMD_WRITE_DAT_UNTIL_STOP                ((uint8_t)20U)  /*!< Speed class control command.                                                             */
-#define SD_CMD_SET_BLOCK_COUNT                     ((uint8_t)23U)  /*!< Specify block count for CMD18 and CMD25.                                                 */
-#define SD_CMD_WRITE_SINGLE_BLOCK                  ((uint8_t)24U)  /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
-                                                                       fixed 512 bytes in case of SDHC and SDXC.                                                */
-#define SD_CMD_WRITE_MULT_BLOCK                    ((uint8_t)25U)  /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows.                    */
-#define SD_CMD_PROG_CID                            ((uint8_t)26U)  /*!< Reserved for manufacturers.                                                              */
-#define SD_CMD_PROG_CSD                            ((uint8_t)27U)  /*!< Programming of the programmable bits of the CSD.                                         */
-#define SD_CMD_SET_WRITE_PROT                      ((uint8_t)28U)  /*!< Sets the write protection bit of the addressed group.                                    */
-#define SD_CMD_CLR_WRITE_PROT                      ((uint8_t)29U)  /*!< Clears the write protection bit of the addressed group.                                  */
-#define SD_CMD_SEND_WRITE_PROT                     ((uint8_t)30U)  /*!< Asks the card to send the status of the write protection bits.                           */
-#define SD_CMD_SD_ERASE_GRP_START                  ((uint8_t)32U)  /*!< Sets the address of the first write block to be erased. (For SD card only).              */
-#define SD_CMD_SD_ERASE_GRP_END                    ((uint8_t)33U)  /*!< Sets the address of the last write block of the continuous range to be erased.           */
-#define SD_CMD_ERASE_GRP_START                     ((uint8_t)35U)  /*!< Sets the address of the first write block to be erased. Reserved for each command
-                                                                       system set by switch function command (CMD6).                                            */
-#define SD_CMD_ERASE_GRP_END                       ((uint8_t)36U)  /*!< Sets the address of the last write block of the continuous range to be erased.
-                                                                       Reserved for each command system set by switch function command (CMD6).                  */
-#define SD_CMD_ERASE                               ((uint8_t)38U)  /*!< Reserved for SD security applications.                                                   */
-#define SD_CMD_FAST_IO                             ((uint8_t)39U)  /*!< SD card doesn't support it (Reserved).                                                   */
-#define SD_CMD_GO_IRQ_STATE                        ((uint8_t)40U)  /*!< SD card doesn't support it (Reserved).                                                   */
-#define SD_CMD_LOCK_UNLOCK                         ((uint8_t)42U)  /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
-                                                                       the SET_BLOCK_LEN command.                                                               */
-#define SD_CMD_APP_CMD                             ((uint8_t)55U)  /*!< Indicates to the card that the next command is an application specific command rather
-                                                                       than a standard command.                                                                 */
-#define SD_CMD_GEN_CMD                             ((uint8_t)56U)  /*!< Used either to transfer a data block to the card or to get a data block from the card
-                                                                       for general purpose/application specific commands.                                       */
-#define SD_CMD_NO_CMD                              ((uint8_t)64U)
-
-/**
-  * @brief Following commands are SD Card Specific commands.
-  *        SDMMC_APP_CMD should be sent before sending these commands.
-  */
-#define SD_CMD_APP_SD_SET_BUSWIDTH                 ((uint8_t)6U)   /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
-                                                                       widths are given in SCR register.                                                          */
-#define SD_CMD_SD_APP_STATUS                       ((uint8_t)13U)  /*!< (ACMD13) Sends the SD status.                                                              */
-#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS        ((uint8_t)22U)  /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
-                                                                       32bit+CRC data block.                                                                      */
-#define SD_CMD_SD_APP_OP_COND                      ((uint8_t)41U)  /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
-                                                                       send its operating condition register (OCR) content in the response on the CMD line.       */
-#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT          ((uint8_t)42U)  /*!< (ACMD42) Connects/Disconnects the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card. */
-#define SD_CMD_SD_APP_SEND_SCR                     ((uint8_t)51U)  /*!< Reads the SD Configuration Register (SCR).                                                 */
-#define SD_CMD_SDMMC_RW_DIRECT                     ((uint8_t)52U)  /*!< For SD I/O card only, reserved for security specification.                                 */
-#define SD_CMD_SDMMC_RW_EXTENDED                   ((uint8_t)53U)  /*!< For SD I/O card only, reserved for security specification.                                 */
-
-/**
-  * @brief Following commands are SD Card Specific security commands.
-  *        SD_CMD_APP_CMD should be sent before sending these commands.
-  */
-#define SD_CMD_SD_APP_GET_MKB                      ((uint8_t)43U)  /*!< For SD card only */
-#define SD_CMD_SD_APP_GET_MID                      ((uint8_t)44U)  /*!< For SD card only */
-#define SD_CMD_SD_APP_SET_CER_RN1                  ((uint8_t)45U)  /*!< For SD card only */
-#define SD_CMD_SD_APP_GET_CER_RN2                  ((uint8_t)46U)  /*!< For SD card only */
-#define SD_CMD_SD_APP_SET_CER_RES2                 ((uint8_t)47U)  /*!< For SD card only */
-#define SD_CMD_SD_APP_GET_CER_RES1                 ((uint8_t)48U)  /*!< For SD card only */
-#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK   ((uint8_t)18U)  /*!< For SD card only */
-#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK  ((uint8_t)25U)  /*!< For SD card only */
-#define SD_CMD_SD_APP_SECURE_ERASE                 ((uint8_t)38U)  /*!< For SD card only */
-#define SD_CMD_SD_APP_CHANGE_SECURE_AREA           ((uint8_t)49U)  /*!< For SD card only */
-#define SD_CMD_SD_APP_SECURE_WRITE_MKB             ((uint8_t)48U)  /*!< For SD card only */
-
-/**
-  * @brief Supported SD Memory Cards
-  */
-#define STD_CAPACITY_SD_CARD_V1_1             ((uint32_t)0x00000000U)
-#define STD_CAPACITY_SD_CARD_V2_0             ((uint32_t)0x00000001U)
-#define HIGH_CAPACITY_SD_CARD                 ((uint32_t)0x00000002U)
-#define MULTIMEDIA_CARD                       ((uint32_t)0x00000003U)
-#define SECURE_DIGITAL_IO_CARD                ((uint32_t)0x00000004U)
-#define HIGH_SPEED_MULTIMEDIA_CARD            ((uint32_t)0x00000005U)
-#define SECURE_DIGITAL_IO_COMBO_CARD          ((uint32_t)0x00000006U)
-#define HIGH_CAPACITY_MMC_CARD                ((uint32_t)0x00000007U)
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup SD_Exported_macros SD Exported Macros
- *  @brief macros to handle interrupts and specific clock configurations
- * @{
- */
-
-/**
-  * @brief  Enable the SD device.
-  * @retval None
-  */
-#define __HAL_SD_SDMMC_ENABLE(__HANDLE__) __SDMMC_ENABLE((__HANDLE__)->Instance)
-
-/**
-  * @brief  Disable the SD device.
-  * @retval None
-  */
-#define __HAL_SD_SDMMC_DISABLE(__HANDLE__) __SDMMC_DISABLE((__HANDLE__)->Instance)
-
-/**
-  * @brief  Enable the SDMMC DMA transfer.
-  * @retval None
-  */
-#define __HAL_SD_SDMMC_DMA_ENABLE(__HANDLE__) __SDMMC_DMA_ENABLE((__HANDLE__)->Instance)
-
-/**
-  * @brief  Disable the SDMMC DMA transfer.
-  * @retval None
-  */
-#define __HAL_SD_SDMMC_DMA_DISABLE(__HANDLE__)  __SDMMC_DMA_DISABLE((__HANDLE__)->Instance)
-
-/**
-  * @brief  Enable the SD device interrupt.
-  * @param  __HANDLE__: SD Handle
-  * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
-  *         This parameter can be one or a combination of the following values:
-  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
-  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
-  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt
-  *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt
-  *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt
-  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
-  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
-  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt
-  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt
-  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt
-  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt
-  *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt
-  *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt
-  * @retval None
-  */
-#define __HAL_SD_SDMMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
-  * @brief  Disable the SD device interrupt.
-  * @param  __HANDLE__: SD Handle
-  * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
-  *          This parameter can be one or a combination of the following values:
-  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
-  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
-  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt
-  *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt
-  *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt
-  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
-  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
-  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt
-  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt
-  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt
-  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt
-  *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt
-  *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt
-  * @retval None
-  */
-#define __HAL_SD_SDMMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
-  * @brief  Check whether the specified SD flag is set or not.
-  * @param  __HANDLE__: SD Handle
-  * @param  __FLAG__: specifies the flag to check.
-  *          This parameter can be one of the following values:
-  *            @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
-  *            @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
-  *            @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
-  *            @arg SDMMC_FLAG_DTIMEOUT: Data timeout
-  *            @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
-  *            @arg SDMMC_FLAG_RXOVERR:  Received FIFO overrun error
-  *            @arg SDMMC_FLAG_CMDREND:  Command response received (CRC check passed)
-  *            @arg SDMMC_FLAG_CMDSENT:  Command sent (no response required)
-  *            @arg SDMMC_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
-  *            @arg SDMMC_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
-  *            @arg SDMMC_FLAG_CMDACT:   Command transfer in progress
-  *            @arg SDMMC_FLAG_TXACT:    Data transmit in progress
-  *            @arg SDMMC_FLAG_RXACT:    Data receive in progress
-  *            @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
-  *            @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
-  *            @arg SDMMC_FLAG_TXFIFOF:  Transmit FIFO full
-  *            @arg SDMMC_FLAG_RXFIFOF:  Receive FIFO full
-  *            @arg SDMMC_FLAG_TXFIFOE:  Transmit FIFO empty
-  *            @arg SDMMC_FLAG_RXFIFOE:  Receive FIFO empty
-  *            @arg SDMMC_FLAG_TXDAVL:   Data available in transmit FIFO
-  *            @arg SDMMC_FLAG_RXDAVL:   Data available in receive FIFO
-  *            @arg SDMMC_FLAG_SDIOIT:   SD I/O interrupt received
-  * @retval The new state of SD FLAG (SET or RESET).
-  */
-#define __HAL_SD_SDMMC_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
-
-/**
-  * @brief  Clear the SD's pending flags.
-  * @param  __HANDLE__: SD Handle
-  * @param  __FLAG__: specifies the flag to clear.
-  *          This parameter can be one or a combination of the following values:
-  *            @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
-  *            @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
-  *            @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
-  *            @arg SDMMC_FLAG_DTIMEOUT: Data timeout
-  *            @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
-  *            @arg SDMMC_FLAG_RXOVERR:  Received FIFO overrun error
-  *            @arg SDMMC_FLAG_CMDREND:  Command response received (CRC check passed)
-  *            @arg SDMMC_FLAG_CMDSENT:  Command sent (no response required)
-  *            @arg SDMMC_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
-  *            @arg SDMMC_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
-  *            @arg SDMMC_FLAG_SDIOIT:   SD I/O interrupt received
-  * @retval None
-  */
-#define __HAL_SD_SDMMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
-
-/**
-  * @brief  Check whether the specified SD interrupt has occurred or not.
-  * @param  __HANDLE__: SD Handle
-  * @param  __INTERRUPT__: specifies the SDMMC interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
-  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
-  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt
-  *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt
-  *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt
-  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
-  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
-  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt
-  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt
-  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt
-  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt
-  *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt
-  *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt
-  * @retval The new state of SD IT (SET or RESET).
-  */
-#define __HAL_SD_SDMMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
-  * @brief  Clear the SD's interrupt pending bits.
-  * @param  __HANDLE__: SD Handle
-  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
-  *          This parameter can be one or a combination of the following values:
-  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
-  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt
-  * @retval None
-  */
-#define __HAL_SD_SDMMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup SD_Exported_Functions SD Exported Functions
-  * @{
-  */
-
-/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo);
-HAL_StatusTypeDef   HAL_SD_DeInit (SD_HandleTypeDef *hsd);
-void HAL_SD_MspInit(SD_HandleTypeDef *hsd);
-void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
-/**
-  * @}
-  */
-
-/** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions
-  * @{
-  */
-/* Blocking mode: Polling */
-// dpgeorge: read/write functions renamed to emphasise that address is given by block number
-HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_BlockNumber(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint32_t BlockNumber, uint32_t BlockSize, uint32_t NumberOfBlocks);
-HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_BlockNumber(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint32_t BlockNumber, uint32_t BlockSize, uint32_t NumberOfBlocks);
-HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr);
-
-/* Non-Blocking mode: Interrupt */
-void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
-
-/* Callback in non blocking modes (DMA) */
-void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma);
-void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma);
-void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma);
-void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma);
-void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd);
-void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd);
-
-/* Non-Blocking mode: DMA */
-// dpgeorge: read/write functions renamed to emphasise that address is given by block number
-HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_BlockNumber_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint32_t BlockNumber, uint32_t BlockSize, uint32_t NumberOfBlocks);
-HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_BlockNumber_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint32_t BlockNumber, uint32_t BlockSize, uint32_t NumberOfBlocks);
-HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);
-HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);
-/**
-  * @}
-  */
-
-/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions
-  * @{
-  */
-HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo);
-HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode);
-HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd);
-HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd);
-/**
-  * @}
-  */
-
-/* Peripheral State functions  ************************************************/
-/** @defgroup SD_Exported_Functions_Group4 Peripheral State functions
-  * @{
-  */
-HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
-HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus);
-HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/
-/** @defgroup SD_Private_Types SD Private Types
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup SD_Private_Defines SD Private Defines
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup SD_Private_Variables SD Private Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup SD_Private_Constants SD Private Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SD_Private_Macros SD Private Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup SD_Private_Functions SD Private Functions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F7xx_HAL_SD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_spi.h b/stmhal/hal/f7/inc/stm32f7xx_hal_spi.h
deleted file mode 100644
index abda07e7de..0000000000
--- a/stmhal/hal/f7/inc/stm32f7xx_hal_spi.h
+++ /dev/null
@@ -1,689 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_spi.h
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   Header file of SPI HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_SPI_H
-#define __STM32F7xx_HAL_SPI_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal_def.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup SPI
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup SPI_Exported_Types SPI Exported Types
-  * @{
-  */
-
-/**
-  * @brief  SPI Configuration Structure definition
-  */
-typedef struct
-{
-    uint32_t Mode;                /*!< Specifies the SPI operating mode.
-                                     This parameter can be a value of @ref SPI_Mode */
-
-    uint32_t Direction;           /*!< Specifies the SPI bidirectional mode state.
-                                     This parameter can be a value of @ref SPI_Direction */
-
-    uint32_t DataSize;            /*!< Specifies the SPI data size.
-                                     This parameter can be a value of @ref SPI_Data_Size */
-
-    uint32_t CLKPolarity;         /*!< Specifies the serial clock steady state.
-                                     This parameter can be a value of @ref SPI_Clock_Polarity */
-
-    uint32_t CLKPhase;            /*!< Specifies the clock active edge for the bit capture.
-                                     This parameter can be a value of @ref SPI_Clock_Phase */
-
-    uint32_t NSS;                 /*!< Specifies whether the NSS signal is managed by
-                                     hardware (NSS pin) or by software using the SSI bit.
-                                     This parameter can be a value of @ref SPI_Slave_Select_management */
-
-    uint32_t BaudRatePrescaler;   /*!< Specifies the Baud Rate prescaler value which will be
-                                     used to configure the transmit and receive SCK clock.
-                                     This parameter can be a value of @ref SPI_BaudRate_Prescaler
-                                     @note The communication clock is derived from the master
-                                     clock. The slave clock does not need to be set. */
-
-    uint32_t FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.
-                                     This parameter can be a value of @ref SPI_MSB_LSB_transmission */
-
-    uint32_t TIMode;              /*!< Specifies if the TI mode is enabled or not.
-                                     This parameter can be a value of @ref SPI_TI_mode */
-
-    uint32_t CRCCalculation;      /*!< Specifies if the CRC calculation is enabled or not.
-                                     This parameter can be a value of @ref SPI_CRC_Calculation */
-
-    uint32_t CRCPolynomial;       /*!< Specifies the polynomial used for the CRC calculation.
-                                     This parameter must be an odd number between Min_Data = 0 and Max_Data = 65535 */
-
-    uint32_t CRCLength;           /*!< Specifies the CRC Length used for the CRC calculation.
-                                     CRC Length is only used with Data8 and Data16, not other data size
-                                     This parameter can be a value of @ref SPI_CRC_length */
-
-    uint32_t NSSPMode;            /*!< Specifies whether the NSSP signal is enabled or not .
-                                     This parameter can be a value of @ref SPI_NSSP_Mode
-                                     This mode is activated by the NSSP bit in the SPIx_CR2 register and
-                                     it takes effect only if the SPI interface is configured as Motorola SPI
-                                     master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,
-                                     CPOL setting is ignored).. */
-} SPI_InitTypeDef;
-
-/**
-  * @brief  HAL SPI State structure definition
-  */
-typedef enum
-{
-    HAL_SPI_STATE_RESET      = 0x00U,    /*!< Peripheral not Initialized                         */
-    HAL_SPI_STATE_READY      = 0x01U,    /*!< Peripheral Initialized and ready for use           */
-    HAL_SPI_STATE_BUSY       = 0x02U,    /*!< an internal process is ongoing                     */
-    HAL_SPI_STATE_BUSY_TX    = 0x03U,    /*!< Data Transmission process is ongoing               */
-    HAL_SPI_STATE_BUSY_RX    = 0x04U,    /*!< Data Reception process is ongoing                  */
-    HAL_SPI_STATE_BUSY_TX_RX = 0x05U,    /*!< Data Transmission and Reception process is ongoing */
-    HAL_SPI_STATE_ERROR      = 0x06U,    /*!< SPI error state                                    */
-    HAL_SPI_STATE_ABORT      = 0x07U     /*!< SPI abort is ongoing                               */
-} HAL_SPI_StateTypeDef;
-
-/**
-  * @brief  SPI handle Structure definition
-  */
-typedef struct __SPI_HandleTypeDef
-{
-    SPI_TypeDef                *Instance;      /*!< SPI registers base address               */
-
-    SPI_InitTypeDef            Init;           /*!< SPI communication parameters             */
-
-    uint8_t                    *pTxBuffPtr;    /*!< Pointer to SPI Tx transfer Buffer        */
-
-    uint16_t                   TxXferSize;     /*!< SPI Tx Transfer size                     */
-
-    __IO uint16_t              TxXferCount;    /*!< SPI Tx Transfer Counter                  */
-
-    uint8_t                    *pRxBuffPtr;    /*!< Pointer to SPI Rx transfer Buffer        */
-
-    uint16_t                   RxXferSize;     /*!< SPI Rx Transfer size                     */
-
-    __IO uint16_t              RxXferCount;    /*!< SPI Rx Transfer Counter                  */
-
-    uint32_t                   CRCSize;        /*!< SPI CRC size used for the transfer       */
-
-    void (*RxISR)(struct __SPI_HandleTypeDef *hspi);                       /*!< function pointer on Rx ISR */
-
-    void (*TxISR)(struct __SPI_HandleTypeDef *hspi);                       /*!< function pointer on Tx ISR */
-
-    DMA_HandleTypeDef          *hdmatx;        /*!< SPI Tx DMA Handle parameters             */
-
-    DMA_HandleTypeDef          *hdmarx;        /*!< SPI Rx DMA Handle parameters             */
-
-    HAL_LockTypeDef            Lock;           /*!< Locking object                           */
-
-    __IO HAL_SPI_StateTypeDef  State;          /*!< SPI communication state                  */
-
-    __IO uint32_t              ErrorCode;      /*!< SPI Error code                           */
-
-} SPI_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup SPI_Exported_Constants SPI Exported Constants
-  * @{
-  */
-
-/** @defgroup SPI_Error_Code SPI Error Code
-  * @{
-  */
-#define HAL_SPI_ERROR_NONE              ((uint32_t)0x00000000U)   /*!< No error                               */
-#define HAL_SPI_ERROR_MODF              ((uint32_t)0x00000001U)   /*!< MODF error                             */
-#define HAL_SPI_ERROR_CRC               ((uint32_t)0x00000002U)   /*!< CRC error                              */
-#define HAL_SPI_ERROR_OVR               ((uint32_t)0x00000004U)   /*!< OVR error                              */
-#define HAL_SPI_ERROR_FRE               ((uint32_t)0x00000008U)   /*!< FRE error                              */
-#define HAL_SPI_ERROR_DMA               ((uint32_t)0x00000010U)   /*!< DMA transfer error                     */
-#define HAL_SPI_ERROR_FLAG              ((uint32_t)0x00000020U)   /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */
-#define HAL_SPI_ERROR_ABORT             ((uint32_t)0x00000040U)   /*!< Error during SPI Abort procedure       */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Mode SPI Mode
-  * @{
-  */
-#define SPI_MODE_SLAVE                  ((uint32_t)0x00000000U)
-#define SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Direction SPI Direction Mode
-  * @{
-  */
-#define SPI_DIRECTION_2LINES            ((uint32_t)0x00000000U)
-#define SPI_DIRECTION_2LINES_RXONLY     SPI_CR1_RXONLY
-#define SPI_DIRECTION_1LINE             SPI_CR1_BIDIMODE
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Data_Size SPI Data Size
-  * @{
-  */
-#define SPI_DATASIZE_4BIT               ((uint32_t)0x00000300U)
-#define SPI_DATASIZE_5BIT               ((uint32_t)0x00000400U)
-#define SPI_DATASIZE_6BIT               ((uint32_t)0x00000500U)
-#define SPI_DATASIZE_7BIT               ((uint32_t)0x00000600U)
-#define SPI_DATASIZE_8BIT               ((uint32_t)0x00000700U)
-#define SPI_DATASIZE_9BIT               ((uint32_t)0x00000800U)
-#define SPI_DATASIZE_10BIT              ((uint32_t)0x00000900U)
-#define SPI_DATASIZE_11BIT              ((uint32_t)0x00000A00U)
-#define SPI_DATASIZE_12BIT              ((uint32_t)0x00000B00U)
-#define SPI_DATASIZE_13BIT              ((uint32_t)0x00000C00U)
-#define SPI_DATASIZE_14BIT              ((uint32_t)0x00000D00U)
-#define SPI_DATASIZE_15BIT              ((uint32_t)0x00000E00U)
-#define SPI_DATASIZE_16BIT              ((uint32_t)0x00000F00U)
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
-  * @{
-  */
-#define SPI_POLARITY_LOW                ((uint32_t)0x00000000U)
-#define SPI_POLARITY_HIGH               SPI_CR1_CPOL
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Clock_Phase SPI Clock Phase
-  * @{
-  */
-#define SPI_PHASE_1EDGE                 ((uint32_t)0x00000000U)
-#define SPI_PHASE_2EDGE                 SPI_CR1_CPHA
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Slave_Select_management SPI Slave Select Management
-  * @{
-  */
-#define SPI_NSS_SOFT                    SPI_CR1_SSM
-#define SPI_NSS_HARD_INPUT              ((uint32_t)0x00000000U)
-#define SPI_NSS_HARD_OUTPUT             ((uint32_t)0x00040000U)
-/**
-  * @}
-  */
-
-/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
-  * @{
-  */
-#define SPI_NSS_PULSE_ENABLE            SPI_CR2_NSSP
-#define SPI_NSS_PULSE_DISABLE           ((uint32_t)0x00000000U)
-/**
-  * @}
-  */
-
-/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
-  * @{
-  */
-#define SPI_BAUDRATEPRESCALER_2         ((uint32_t)0x00000000U)
-#define SPI_BAUDRATEPRESCALER_4         ((uint32_t)0x00000008U)
-#define SPI_BAUDRATEPRESCALER_8         ((uint32_t)0x00000010U)
-#define SPI_BAUDRATEPRESCALER_16        ((uint32_t)0x00000018U)
-#define SPI_BAUDRATEPRESCALER_32        ((uint32_t)0x00000020U)
-#define SPI_BAUDRATEPRESCALER_64        ((uint32_t)0x00000028U)
-#define SPI_BAUDRATEPRESCALER_128       ((uint32_t)0x00000030U)
-#define SPI_BAUDRATEPRESCALER_256       ((uint32_t)0x00000038U)
-/**
-  * @}
-  */
-
-/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
-  * @{
-  */
-#define SPI_FIRSTBIT_MSB                ((uint32_t)0x00000000U)
-#define SPI_FIRSTBIT_LSB                SPI_CR1_LSBFIRST
-/**
-  * @}
-  */
-
-/** @defgroup SPI_TI_mode SPI TI Mode
-  * @{
-  */
-#define SPI_TIMODE_DISABLE              ((uint32_t)0x00000000U)
-#define SPI_TIMODE_ENABLE               SPI_CR2_FRF
-/**
-  * @}
-  */
-
-/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
-  * @{
-  */
-#define SPI_CRCCALCULATION_DISABLE      ((uint32_t)0x00000000U)
-#define SPI_CRCCALCULATION_ENABLE       SPI_CR1_CRCEN
-/**
-  * @}
-  */
-
-/** @defgroup SPI_CRC_length SPI CRC Length
-  * @{
-  * This parameter can be one of the following values:
-  *     SPI_CRC_LENGTH_DATASIZE: aligned with the data size
-  *     SPI_CRC_LENGTH_8BIT    : CRC 8bit
-  *     SPI_CRC_LENGTH_16BIT   : CRC 16bit
-  */
-#define SPI_CRC_LENGTH_DATASIZE         ((uint32_t)0x00000000U)
-#define SPI_CRC_LENGTH_8BIT             ((uint32_t)0x00000001U)
-#define SPI_CRC_LENGTH_16BIT            ((uint32_t)0x00000002U)
-/**
-  * @}
-  */
-
-/** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold
-  * @{
-  * This parameter can be one of the following values:
-  *     SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :
-  *          RXNE event is generated if the FIFO
-  *          level is greater or equal to 1/2(16-bits).
-  *     SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO
-  *          level is greater or equal to 1/4(8 bits). */
-#define SPI_RXFIFO_THRESHOLD            SPI_CR2_FRXTH
-#define SPI_RXFIFO_THRESHOLD_QF         SPI_CR2_FRXTH
-#define SPI_RXFIFO_THRESHOLD_HF         ((uint32_t)0x00000000U)
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
-  * @{
-  */
-#define SPI_IT_TXE                      SPI_CR2_TXEIE
-#define SPI_IT_RXNE                     SPI_CR2_RXNEIE
-#define SPI_IT_ERR                      SPI_CR2_ERRIE
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Flags_definition SPI Flags Definition
-  * @{
-  */
-#define SPI_FLAG_RXNE                   SPI_SR_RXNE   /* SPI status flag: Rx buffer not empty flag       */
-#define SPI_FLAG_TXE                    SPI_SR_TXE    /* SPI status flag: Tx buffer empty flag           */
-#define SPI_FLAG_BSY                    SPI_SR_BSY    /* SPI status flag: Busy flag                      */
-#define SPI_FLAG_CRCERR                 SPI_SR_CRCERR /* SPI Error flag: CRC error flag                  */
-#define SPI_FLAG_MODF                   SPI_SR_MODF   /* SPI Error flag: Mode fault flag                 */
-#define SPI_FLAG_OVR                    SPI_SR_OVR    /* SPI Error flag: Overrun flag                    */
-#define SPI_FLAG_FRE                    SPI_SR_FRE    /* SPI Error flag: TI mode frame format error flag */
-#define SPI_FLAG_FTLVL                  SPI_SR_FTLVL  /* SPI fifo transmission level                     */
-#define SPI_FLAG_FRLVL                  SPI_SR_FRLVL  /* SPI fifo reception level                        */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level
-  * @{
-  */
-#define SPI_FTLVL_EMPTY           ((uint32_t)0x00000000U)
-#define SPI_FTLVL_QUARTER_FULL    ((uint32_t)0x00000800U)
-#define SPI_FTLVL_HALF_FULL       ((uint32_t)0x00001000U)
-#define SPI_FTLVL_FULL            ((uint32_t)0x00001800U)
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
-  * @{
-  */
-#define SPI_FRLVL_EMPTY           ((uint32_t)0x00000000U)
-#define SPI_FRLVL_QUARTER_FULL    ((uint32_t)0x00000200U)
-#define SPI_FRLVL_HALF_FULL       ((uint32_t)0x00000400U)
-#define SPI_FRLVL_FULL            ((uint32_t)0x00000600U)
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup SPI_Exported_Macros SPI Exported Macros
-  * @{
-  */
-
-/** @brief  Reset SPI handle state.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
-
-/** @brief  Enable or disable the specified SPI interrupts.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
-  *         This parameter can be one of the following values:
-  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg SPI_IT_ERR: Error interrupt enable
-  * @retval None
-  */
-#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
-#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
-
-/** @brief  Check whether the specified SPI interrupt source is enabled or not.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @param  __INTERRUPT__: specifies the SPI interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg SPI_IT_ERR: Error interrupt enable
-  * @retval The new state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief  Check whether the specified SPI flag is set or not.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @param  __FLAG__: specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag
-  *            @arg SPI_FLAG_TXE: Transmit buffer empty flag
-  *            @arg SPI_FLAG_CRCERR: CRC error flag
-  *            @arg SPI_FLAG_MODF: Mode fault flag
-  *            @arg SPI_FLAG_OVR: Overrun flag
-  *            @arg SPI_FLAG_BSY: Busy flag
-  *            @arg SPI_FLAG_FRE: Frame format error flag
-  *            @arg SPI_FLAG_FTLVL: SPI fifo transmission level
-  *            @arg SPI_FLAG_FRLVL: SPI fifo reception level
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Clear the SPI CRCERR pending flag.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
-
-/** @brief  Clear the SPI MODF pending flag.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)       \
-  do{                                              \
-    __IO uint32_t tmpreg_modf = 0x00U;             \
-    tmpreg_modf = (__HANDLE__)->Instance->SR;      \
-    (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
-    UNUSED(tmpreg_modf);                           \
-  } while(0)
-
-/** @brief  Clear the SPI OVR pending flag.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)        \
-  do{                                              \
-    __IO uint32_t tmpreg_ovr = 0x00U;              \
-    tmpreg_ovr = (__HANDLE__)->Instance->DR;       \
-    tmpreg_ovr = (__HANDLE__)->Instance->SR;       \
-    UNUSED(tmpreg_ovr);                            \
-  } while(0)
-
-/** @brief  Clear the SPI FRE pending flag.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)        \
-  do{                                              \
-  __IO uint32_t tmpreg_fre = 0x00U;                \
-  tmpreg_fre = (__HANDLE__)->Instance->SR;         \
-  UNUSED(tmpreg_fre);                              \
-  }while(0)
-
-/** @brief  Enable the SPI peripheral.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |=  SPI_CR1_SPE)
-
-/** @brief  Disable the SPI peripheral.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SPI_Private_Macros SPI Private Macros
-  * @{
-  */
-
-/** @brief  Set the SPI transmit-only mode.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
-
-/** @brief  Set the SPI receive-only mode.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
-
-/** @brief  Reset the CRC calculation of the SPI.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
-                                     (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
-
-#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
-                           ((MODE) == SPI_MODE_MASTER))
-
-#define IS_SPI_DIRECTION(MODE)   (((MODE) == SPI_DIRECTION_2LINES)        || \
-                                  ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
-                                  ((MODE) == SPI_DIRECTION_1LINE))
-
-#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
-
-#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
-                                                ((MODE) == SPI_DIRECTION_1LINE))
-
-#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
-                                   ((DATASIZE) == SPI_DATASIZE_15BIT) || \
-                                   ((DATASIZE) == SPI_DATASIZE_14BIT) || \
-                                   ((DATASIZE) == SPI_DATASIZE_13BIT) || \
-                                   ((DATASIZE) == SPI_DATASIZE_12BIT) || \
-                                   ((DATASIZE) == SPI_DATASIZE_11BIT) || \
-                                   ((DATASIZE) == SPI_DATASIZE_10BIT) || \
-                                   ((DATASIZE) == SPI_DATASIZE_9BIT)  || \
-                                   ((DATASIZE) == SPI_DATASIZE_8BIT)  || \
-                                   ((DATASIZE) == SPI_DATASIZE_7BIT)  || \
-                                   ((DATASIZE) == SPI_DATASIZE_6BIT)  || \
-                                   ((DATASIZE) == SPI_DATASIZE_5BIT)  || \
-                                   ((DATASIZE) == SPI_DATASIZE_4BIT))
-
-#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
-                           ((CPOL) == SPI_POLARITY_HIGH))
-
-#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
-                           ((CPHA) == SPI_PHASE_2EDGE))
-
-#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT)       || \
-                         ((NSS) == SPI_NSS_HARD_INPUT) || \
-                         ((NSS) == SPI_NSS_HARD_OUTPUT))
-
-#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \
-                           ((NSSP) == SPI_NSS_PULSE_DISABLE))
-
-#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2)   || \
-                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_4)   || \
-                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_8)   || \
-                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_16)  || \
-                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_32)  || \
-                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_64)  || \
-                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
-                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
-
-#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
-                               ((BIT) == SPI_FIRSTBIT_LSB))
-
-#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
-                             ((MODE) == SPI_TIMODE_ENABLE))
-
-#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
-                                             ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
-
-#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\
-                                   ((LENGTH) == SPI_CRC_LENGTH_8BIT)  ||   \
-                                   ((LENGTH) == SPI_CRC_LENGTH_16BIT))
-
-#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFFU) && (((POLYNOMIAL)&0x1U) != 0))
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SPI_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-/* Initialization/de-initialization functions  ********************************/
-HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
-void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
-void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
-/**
-  * @}
-  */
-
-/** @addtogroup SPI_Exported_Functions_Group2 IO operation functions
-  * @{
-  */
-/* I/O operation functions  ***************************************************/
-HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
-        uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
-        uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
-        uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
-/* Transfer Abort functions */
-HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
-
-void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
-/**
-  * @}
-  */
-
-/** @addtogroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
-  * @{
-  */
-
-/* Peripheral State and Error functions ***************************************/
-HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
-uint32_t             HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F7xx_HAL_SPI_H */
-
-/**
-  * @}
-  */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_tim.h b/stmhal/hal/f7/inc/stm32f7xx_hal_tim.h
deleted file mode 100644
index 7a6a69b3ba..0000000000
--- a/stmhal/hal/f7/inc/stm32f7xx_hal_tim.h
+++ /dev/null
@@ -1,1546 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_tim.h
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   Header file of TIM HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_TIM_H
-#define __STM32F7xx_HAL_TIM_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal_def.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup TIM
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup TIM_Exported_Types TIM Exported Types
-  * @{
-  */
-
-/**
-  * @brief  TIM Time base Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
-                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
-  uint32_t CounterMode;       /*!< Specifies the counter mode.
-                                   This parameter can be a value of @ref TIM_Counter_Mode */
-
-  uint32_t Period;            /*!< Specifies the period value to be loaded into the active
-                                   Auto-Reload Register at the next update event.
-                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.  */
-
-  uint32_t ClockDivision;     /*!< Specifies the clock division.
-                                   This parameter can be a value of @ref TIM_ClockDivision */
-
-  uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR down-counter
-                                    reaches zero, an update event is generated and counting restarts
-                                    from the RCR value (N).
-                                    This means in PWM mode that (N+1) corresponds to:
-                                        - the number of PWM periods in edge-aligned mode
-                                        - the number of half PWM period in center-aligned mode
-                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
-                                     @note This parameter is valid only for TIM1 and TIM8. */
-} TIM_Base_InitTypeDef;
-
-/**
-  * @brief  TIM Output Compare Configuration Structure definition
-  */
-
-typedef struct
-{
-  uint32_t OCMode;        /*!< Specifies the TIM mode.
-                               This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */
-
-  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
-                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
-  uint32_t OCPolarity;    /*!< Specifies the output polarity.
-                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */
-
-  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
-                               This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
-                               @note This parameter is valid only for TIM1 and TIM8. */
-
-  uint32_t OCFastMode;   /*!< Specifies the Fast mode state.
-                               This parameter can be a value of @ref TIM_Output_Fast_State
-                               @note This parameter is valid only in PWM1 and PWM2 mode. */
-
-
-  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
-                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State
-                               @note This parameter is valid only for TIM1 and TIM8. */
-
-  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
-                               This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
-                               @note This parameter is valid only for TIM1 and TIM8. */
-} TIM_OC_InitTypeDef;
-
-/**
-  * @brief  TIM One Pulse Mode Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t OCMode;        /*!< Specifies the TIM mode.
-                               This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */
-
-  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
-                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
-  uint32_t OCPolarity;    /*!< Specifies the output polarity.
-                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */
-
-  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
-                               This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
-                               @note This parameter is valid only for TIM1 and TIM8. */
-
-  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
-                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State
-                               @note This parameter is valid only for TIM1 and TIM8. */
-
-  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
-                               This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
-                               @note This parameter is valid only for TIM1 and TIM8. */
-
-  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
-                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
-  uint32_t ICSelection;   /*!< Specifies the input.
-                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
-  uint32_t ICFilter;      /*!< Specifies the input capture filter.
-                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_OnePulse_InitTypeDef;
-
-
-/**
-  * @brief  TIM Input Capture Configuration Structure definition
-  */
-
-typedef struct
-{
-  uint32_t  ICPolarity;   /*!< Specifies the active edge of the input signal.
-                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
-  uint32_t ICSelection;  /*!< Specifies the input.
-                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
-  uint32_t ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
-                              This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
-  uint32_t ICFilter;     /*!< Specifies the input capture filter.
-                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_IC_InitTypeDef;
-
-/**
-  * @brief  TIM Encoder Configuration Structure definition
-  */
-
-typedef struct
-{
-  uint32_t EncoderMode;   /*!< Specifies the active edge of the input signal.
-                               This parameter can be a value of @ref TIM_Encoder_Mode */
-
-  uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.
-                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
-  uint32_t IC1Selection;  /*!< Specifies the input.
-                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
-  uint32_t IC1Prescaler;  /*!< Specifies the Input Capture Prescaler.
-                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
-  uint32_t IC1Filter;     /*!< Specifies the input capture filter.
-                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-
-  uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.
-                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
-  uint32_t IC2Selection;  /*!< Specifies the input.
-                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
-  uint32_t IC2Prescaler;  /*!< Specifies the Input Capture Prescaler.
-                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
-  uint32_t IC2Filter;     /*!< Specifies the input capture filter.
-                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_Encoder_InitTypeDef;
-
-/**
-  * @brief  Clock Configuration Handle Structure definition
-  */
-typedef struct
-{
-  uint32_t ClockSource;     /*!< TIM clock sources.
-                                 This parameter can be a value of @ref TIM_Clock_Source */
-  uint32_t ClockPolarity;   /*!< TIM clock polarity.
-                                 This parameter can be a value of @ref TIM_Clock_Polarity */
-  uint32_t ClockPrescaler;  /*!< TIM clock prescaler.
-                                 This parameter can be a value of @ref TIM_Clock_Prescaler */
-  uint32_t ClockFilter;    /*!< TIM clock filter.
-                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-}TIM_ClockConfigTypeDef;
-
-/**
-  * @brief  Clear Input Configuration Handle Structure definition
-  */
-typedef struct
-{
-  uint32_t ClearInputState;      /*!< TIM clear Input state.
-                                      This parameter can be ENABLE or DISABLE */
-  uint32_t ClearInputSource;     /*!< TIM clear Input sources.
-                                      This parameter can be a value of @ref TIMEx_ClearInput_Source */
-  uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity.
-                                      This parameter can be a value of @ref TIM_ClearInput_Polarity */
-  uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler.
-                                      This parameter can be a value of @ref TIM_ClearInput_Prescaler */
-  uint32_t ClearInputFilter;    /*!< TIM Clear Input filter.
-                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-}TIM_ClearInputConfigTypeDef;
-
-/**
-  * @brief  TIM Slave configuration Structure definition
-  */
-typedef struct {
-  uint32_t  SlaveMode;         /*!< Slave mode selection
-                                  This parameter can be a value of @ref TIMEx_Slave_Mode */
-  uint32_t  InputTrigger;      /*!< Input Trigger source
-                                  This parameter can be a value of @ref TIM_Trigger_Selection */
-  uint32_t  TriggerPolarity;   /*!< Input Trigger polarity
-                                  This parameter can be a value of @ref TIM_Trigger_Polarity */
-  uint32_t  TriggerPrescaler;  /*!< Input trigger prescaler
-                                  This parameter can be a value of @ref TIM_Trigger_Prescaler */
-  uint32_t  TriggerFilter;     /*!< Input trigger filter
-                                  This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-
-}TIM_SlaveConfigTypeDef;
-
-/**
-  * @brief  HAL State structures definition
-  */
-typedef enum
-{
-  HAL_TIM_STATE_RESET             = 0x00U,    /*!< Peripheral not yet initialized or disabled  */
-  HAL_TIM_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */
-  HAL_TIM_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */
-  HAL_TIM_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */
-  HAL_TIM_STATE_ERROR             = 0x04U     /*!< Reception process is ongoing                */
-}HAL_TIM_StateTypeDef;
-
-/**
-  * @brief  HAL Active channel structures definition
-  */
-typedef enum
-{
-  HAL_TIM_ACTIVE_CHANNEL_1        = 0x01U,    /*!< The active channel is 1     */
-  HAL_TIM_ACTIVE_CHANNEL_2        = 0x02U,    /*!< The active channel is 2     */
-  HAL_TIM_ACTIVE_CHANNEL_3        = 0x04U,    /*!< The active channel is 3     */
-  HAL_TIM_ACTIVE_CHANNEL_4        = 0x08U,    /*!< The active channel is 4     */
-  HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00U     /*!< All active channels cleared */
-}HAL_TIM_ActiveChannel;
-
-/**
-  * @brief  TIM Time Base Handle Structure definition
-  */
-typedef struct
-{
-  TIM_TypeDef                 *Instance;     /*!< Register base address             */
-  TIM_Base_InitTypeDef        Init;          /*!< TIM Time Base required parameters */
-  HAL_TIM_ActiveChannel       Channel;       /*!< Active channel                    */
-  DMA_HandleTypeDef           *hdma[7];      /*!< DMA Handlers array
-                                             This array is accessed by a @ref DMA_Handle_index */
-  HAL_LockTypeDef             Lock;          /*!< Locking object                    */
-  __IO HAL_TIM_StateTypeDef   State;         /*!< TIM operation state               */
-}TIM_HandleTypeDef;
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIM_Exported_Constants  TIM Exported Constants
-  * @{
-  */
-
-/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
-  * @{
-  */
-#define  TIM_INPUTCHANNELPOLARITY_RISING      ((uint32_t)0x00000000U)            /*!< Polarity for TIx source */
-#define  TIM_INPUTCHANNELPOLARITY_FALLING     (TIM_CCER_CC1P)                   /*!< Polarity for TIx source */
-#define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_ETR_Polarity  TIM ETR Polarity
-  * @{
-  */
-#define TIM_ETRPOLARITY_INVERTED              (TIM_SMCR_ETP)                    /*!< Polarity for ETR source */
-#define TIM_ETRPOLARITY_NONINVERTED           ((uint32_t)0x0000U)                /*!< Polarity for ETR source */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_ETR_Prescaler  TIM ETR Prescaler
-  * @{
-  */
-#define TIM_ETRPRESCALER_DIV1                 ((uint32_t)0x0000U)                /*!< No prescaler is used */
-#define TIM_ETRPRESCALER_DIV2                 (TIM_SMCR_ETPS_0)                 /*!< ETR input source is divided by 2 */
-#define TIM_ETRPRESCALER_DIV4                 (TIM_SMCR_ETPS_1)                 /*!< ETR input source is divided by 4 */
-#define TIM_ETRPRESCALER_DIV8                 (TIM_SMCR_ETPS)                   /*!< ETR input source is divided by 8 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Counter_Mode  TIM Counter Mode
-  * @{
-  */
-#define TIM_COUNTERMODE_UP                 ((uint32_t)0x0000U)
-#define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR
-#define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0
-#define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1
-#define TIM_COUNTERMODE_CENTERALIGNED3     TIM_CR1_CMS
-/**
-  * @}
-  */
-
-/** @defgroup TIM_ClockDivision TIM Clock Division
-  * @{
-  */
-#define TIM_CLOCKDIVISION_DIV1                       ((uint32_t)0x0000U)
-#define TIM_CLOCKDIVISION_DIV2                       (TIM_CR1_CKD_0)
-#define TIM_CLOCKDIVISION_DIV4                       (TIM_CR1_CKD_1)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Compare_State TIM Output Compare State
-  * @{
-  */
-#define TIM_OUTPUTSTATE_DISABLE            ((uint32_t)0x0000U)
-#define TIM_OUTPUTSTATE_ENABLE             (TIM_CCER_CC1E)
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Fast_State  TIM Output Fast State
-  * @{
-  */
-#define TIM_OCFAST_DISABLE                ((uint32_t)0x0000U)
-#define TIM_OCFAST_ENABLE                 (TIM_CCMR1_OC1FE)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
-  * @{
-  */
-#define TIM_OUTPUTNSTATE_DISABLE            ((uint32_t)0x0000U)
-#define TIM_OUTPUTNSTATE_ENABLE             (TIM_CCER_CC1NE)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
-  * @{
-  */
-#define TIM_OCPOLARITY_HIGH                ((uint32_t)0x0000U)
-#define TIM_OCPOLARITY_LOW                 (TIM_CCER_CC1P)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
-  * @{
-  */
-#define TIM_OCNPOLARITY_HIGH               ((uint32_t)0x0000U)
-#define TIM_OCNPOLARITY_LOW                (TIM_CCER_CC1NP)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Compare_Idle_State  TIM Output Compare Idle State
-  * @{
-  */
-#define TIM_OCIDLESTATE_SET                (TIM_CR2_OIS1)
-#define TIM_OCIDLESTATE_RESET              ((uint32_t)0x0000U)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Compare_N_Idle_State  TIM Output Compare N Idle State
-  * @{
-  */
-#define TIM_OCNIDLESTATE_SET               (TIM_CR2_OIS1N)
-#define TIM_OCNIDLESTATE_RESET             ((uint32_t)0x0000U)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Input_Capture_Polarity  TIM Input Capture Polarity
-  * @{
-  */
-#define  TIM_ICPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING
-#define  TIM_ICPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING
-#define  TIM_ICPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Input_Capture_Selection  TIM Input Capture Selection
-  * @{
-  */
-#define TIM_ICSELECTION_DIRECTTI           (TIM_CCMR1_CC1S_0)   /*!< TIM Input 1, 2, 3 or 4 is selected to be
-                                                                     connected to IC1, IC2, IC3 or IC4, respectively */
-#define TIM_ICSELECTION_INDIRECTTI         (TIM_CCMR1_CC1S_1)   /*!< TIM Input 1, 2, 3 or 4 is selected to be
-                                                                     connected to IC2, IC1, IC4 or IC3, respectively */
-#define TIM_ICSELECTION_TRC                (TIM_CCMR1_CC1S)     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Input_Capture_Prescaler  TIM Input Capture Prescaler
-  * @{
-  */
-#define TIM_ICPSC_DIV1                     ((uint32_t)0x0000U)       /*!< Capture performed each time an edge is detected on the capture input */
-#define TIM_ICPSC_DIV2                     (TIM_CCMR1_IC1PSC_0)     /*!< Capture performed once every 2 events */
-#define TIM_ICPSC_DIV4                     (TIM_CCMR1_IC1PSC_1)     /*!< Capture performed once every 4 events */
-#define TIM_ICPSC_DIV8                     (TIM_CCMR1_IC1PSC)       /*!< Capture performed once every 8 events */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
-  * @{
-  */
-#define TIM_OPMODE_SINGLE                  (TIM_CR1_OPM)
-#define TIM_OPMODE_REPETITIVE              ((uint32_t)0x0000U)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
-  * @{
-  */
-#define TIM_ENCODERMODE_TI1                (TIM_SMCR_SMS_0)
-#define TIM_ENCODERMODE_TI2                (TIM_SMCR_SMS_1)
-#define TIM_ENCODERMODE_TI12               (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Interrupt_definition  TIM Interrupt definition
-  * @{
-  */
-#define TIM_IT_UPDATE           (TIM_DIER_UIE)
-#define TIM_IT_CC1              (TIM_DIER_CC1IE)
-#define TIM_IT_CC2              (TIM_DIER_CC2IE)
-#define TIM_IT_CC3              (TIM_DIER_CC3IE)
-#define TIM_IT_CC4              (TIM_DIER_CC4IE)
-#define TIM_IT_COM              (TIM_DIER_COMIE)
-#define TIM_IT_TRIGGER          (TIM_DIER_TIE)
-#define TIM_IT_BREAK            (TIM_DIER_BIE)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Commutation_Source  TIM Commutation Source
-  * @{
-  */
-#define TIM_COMMUTATION_TRGI              (TIM_CR2_CCUS)
-#define TIM_COMMUTATION_SOFTWARE          ((uint32_t)0x0000U)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_DMA_sources  TIM DMA sources
-  * @{
-  */
-#define TIM_DMA_UPDATE                     (TIM_DIER_UDE)
-#define TIM_DMA_CC1                        (TIM_DIER_CC1DE)
-#define TIM_DMA_CC2                        (TIM_DIER_CC2DE)
-#define TIM_DMA_CC3                        (TIM_DIER_CC3DE)
-#define TIM_DMA_CC4                        (TIM_DIER_CC4DE)
-#define TIM_DMA_COM                        (TIM_DIER_COMDE)
-#define TIM_DMA_TRIGGER                    (TIM_DIER_TDE)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Event_Source  TIM Event Source
-  * @{
-  */
-#define TIM_EVENTSOURCE_UPDATE              TIM_EGR_UG
-#define TIM_EVENTSOURCE_CC1                 TIM_EGR_CC1G
-#define TIM_EVENTSOURCE_CC2                 TIM_EGR_CC2G
-#define TIM_EVENTSOURCE_CC3                 TIM_EGR_CC3G
-#define TIM_EVENTSOURCE_CC4                 TIM_EGR_CC4G
-#define TIM_EVENTSOURCE_COM                 TIM_EGR_COMG
-#define TIM_EVENTSOURCE_TRIGGER             TIM_EGR_TG
-#define TIM_EVENTSOURCE_BREAK               TIM_EGR_BG
-#define TIM_EVENTSOURCE_BREAK2              TIM_EGR_B2G
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Flag_definition  TIM Flag definition
-  * @{
-  */
-#define TIM_FLAG_UPDATE                    (TIM_SR_UIF)
-#define TIM_FLAG_CC1                       (TIM_SR_CC1IF)
-#define TIM_FLAG_CC2                       (TIM_SR_CC2IF)
-#define TIM_FLAG_CC3                       (TIM_SR_CC3IF)
-#define TIM_FLAG_CC4                       (TIM_SR_CC4IF)
-#define TIM_FLAG_COM                       (TIM_SR_COMIF)
-#define TIM_FLAG_TRIGGER                   (TIM_SR_TIF)
-#define TIM_FLAG_BREAK                     (TIM_SR_BIF)
-#define TIM_FLAG_BREAK2                    (TIM_SR_B2IF)
-#define TIM_FLAG_CC1OF                     (TIM_SR_CC1OF)
-#define TIM_FLAG_CC2OF                     (TIM_SR_CC2OF)
-#define TIM_FLAG_CC3OF                     (TIM_SR_CC3OF)
-#define TIM_FLAG_CC4OF                     (TIM_SR_CC4OF)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Clock_Source  TIM Clock Source
-  * @{
-  */
-#define	TIM_CLOCKSOURCE_ETRMODE2    (TIM_SMCR_ETPS_1)
-#define	TIM_CLOCKSOURCE_INTERNAL    (TIM_SMCR_ETPS_0)
-#define	TIM_CLOCKSOURCE_ITR0        ((uint32_t)0x0000U)
-#define	TIM_CLOCKSOURCE_ITR1        (TIM_SMCR_TS_0)
-#define	TIM_CLOCKSOURCE_ITR2        (TIM_SMCR_TS_1)
-#define	TIM_CLOCKSOURCE_ITR3        (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
-#define	TIM_CLOCKSOURCE_TI1ED       (TIM_SMCR_TS_2)
-#define	TIM_CLOCKSOURCE_TI1         (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
-#define	TIM_CLOCKSOURCE_TI2         (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
-#define	TIM_CLOCKSOURCE_ETRMODE1    (TIM_SMCR_TS)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Clock_Polarity  TIM Clock Polarity
-  * @{
-  */
-#define TIM_CLOCKPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED          /*!< Polarity for ETRx clock sources */
-#define TIM_CLOCKPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED       /*!< Polarity for ETRx clock sources */
-#define TIM_CLOCKPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING   /*!< Polarity for TIx clock sources */
-#define TIM_CLOCKPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING   /*!< Polarity for TIx clock sources */
-#define TIM_CLOCKPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE  /*!< Polarity for TIx clock sources */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Clock_Prescaler  TIM Clock Prescaler
-  * @{
-  */
-#define TIM_CLOCKPRESCALER_DIV1              TIM_ETRPRESCALER_DIV1     /*!< No prescaler is used */
-#define TIM_CLOCKPRESCALER_DIV2              TIM_ETRPRESCALER_DIV2     /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
-#define TIM_CLOCKPRESCALER_DIV4              TIM_ETRPRESCALER_DIV4     /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
-#define TIM_CLOCKPRESCALER_DIV8              TIM_ETRPRESCALER_DIV8     /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_ClearInput_Polarity  TIM Clear Input Polarity
-  * @{
-  */
-#define TIM_CLEARINPUTPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED                    /*!< Polarity for ETRx pin */
-#define TIM_CLEARINPUTPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED                 /*!< Polarity for ETRx pin */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
-  * @{
-  */
-#define TIM_CLEARINPUTPRESCALER_DIV1                    TIM_ETRPRESCALER_DIV1      /*!< No prescaler is used */
-#define TIM_CLEARINPUTPRESCALER_DIV2                    TIM_ETRPRESCALER_DIV2      /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
-#define TIM_CLEARINPUTPRESCALER_DIV4                    TIM_ETRPRESCALER_DIV4      /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
-#define TIM_CLEARINPUTPRESCALER_DIV8                    TIM_ETRPRESCALER_DIV8        /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
-  * @{
-  */
-#define TIM_OSSR_ENABLE 	      (TIM_BDTR_OSSR)
-#define TIM_OSSR_DISABLE          ((uint32_t)0x0000U)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
-  * @{
-  */
-#define TIM_OSSI_ENABLE	 	    (TIM_BDTR_OSSI)
-#define TIM_OSSI_DISABLE            ((uint32_t)0x0000U)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Lock_level  TIM Lock level
-  * @{
-  */
-#define TIM_LOCKLEVEL_OFF	   ((uint32_t)0x0000U)
-#define TIM_LOCKLEVEL_1            (TIM_BDTR_LOCK_0)
-#define TIM_LOCKLEVEL_2            (TIM_BDTR_LOCK_1)
-#define TIM_LOCKLEVEL_3            (TIM_BDTR_LOCK)
-/**
-  * @}
-  */
-/** @defgroup TIM_Break_Input_enable_disable  TIM Break Input State
-  * @{
-  */
-#define TIM_BREAK_ENABLE          (TIM_BDTR_BKE)
-#define TIM_BREAK_DISABLE         ((uint32_t)0x0000U)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Break_Polarity  TIM Break Polarity
-  * @{
-  */
-#define TIM_BREAKPOLARITY_LOW        ((uint32_t)0x0000U)
-#define TIM_BREAKPOLARITY_HIGH       (TIM_BDTR_BKP)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_AOE_Bit_Set_Reset  TIM AOE Bit State
-  * @{
-  */
-#define TIM_AUTOMATICOUTPUT_ENABLE           (TIM_BDTR_AOE)
-#define	TIM_AUTOMATICOUTPUT_DISABLE          ((uint32_t)0x0000U)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
-  * @{
-  */
-#define	TIM_TRGO_RESET            ((uint32_t)0x0000U)
-#define	TIM_TRGO_ENABLE           (TIM_CR2_MMS_0)
-#define	TIM_TRGO_UPDATE           (TIM_CR2_MMS_1)
-#define	TIM_TRGO_OC1              ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
-#define	TIM_TRGO_OC1REF           (TIM_CR2_MMS_2)
-#define	TIM_TRGO_OC2REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
-#define	TIM_TRGO_OC3REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
-#define	TIM_TRGO_OC4REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Master_Slave_Mode  TIM Master Slave Mode
-  * @{
-  */
-#define TIM_MASTERSLAVEMODE_ENABLE          ((uint32_t)0x0080)
-#define TIM_MASTERSLAVEMODE_DISABLE         ((uint32_t)0x0000U)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Trigger_Selection  TIM Trigger Selection
-  * @{
-  */
-#define TIM_TS_ITR0                        ((uint32_t)0x0000U)
-#define TIM_TS_ITR1                        ((uint32_t)0x0010U)
-#define TIM_TS_ITR2                        ((uint32_t)0x0020U)
-#define TIM_TS_ITR3                        ((uint32_t)0x0030U)
-#define TIM_TS_TI1F_ED                     ((uint32_t)0x0040U)
-#define TIM_TS_TI1FP1                      ((uint32_t)0x0050U)
-#define TIM_TS_TI2FP2                      ((uint32_t)0x0060U)
-#define TIM_TS_ETRF                        ((uint32_t)0x0070U)
-#define TIM_TS_NONE                        ((uint32_t)0xFFFFU)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
-  * @{
-  */
-#define TIM_TRIGGERPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx trigger sources */
-#define TIM_TRIGGERPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx trigger sources */
-#define TIM_TRIGGERPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING        /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-#define TIM_TRIGGERPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING       /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-#define TIM_TRIGGERPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE      /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
-  * @{
-  */
-#define TIM_TRIGGERPRESCALER_DIV1             TIM_ETRPRESCALER_DIV1     /*!< No prescaler is used */
-#define TIM_TRIGGERPRESCALER_DIV2             TIM_ETRPRESCALER_DIV2     /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
-#define TIM_TRIGGERPRESCALER_DIV4             TIM_ETRPRESCALER_DIV4     /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
-#define TIM_TRIGGERPRESCALER_DIV8             TIM_ETRPRESCALER_DIV8     /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
-/**
-  * @}
-  */
-
-
-/** @defgroup TIM_TI1_Selection TIM TI1 Selection
-  * @{
-  */
-#define TIM_TI1SELECTION_CH1                ((uint32_t)0x0000U)
-#define TIM_TI1SELECTION_XORCOMBINATION     (TIM_CR2_TI1S)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_DMA_Base_address  TIM DMA Base address
-  * @{
-  */
-#define TIM_DMABASE_CR1                    (0x00000000U)
-#define TIM_DMABASE_CR2                    (0x00000001U)
-#define TIM_DMABASE_SMCR                   (0x00000002U)
-#define TIM_DMABASE_DIER                   (0x00000003U)
-#define TIM_DMABASE_SR                     (0x00000004U)
-#define TIM_DMABASE_EGR                    (0x00000005U)
-#define TIM_DMABASE_CCMR1                  (0x00000006U)
-#define TIM_DMABASE_CCMR2                  (0x00000007U)
-#define TIM_DMABASE_CCER                   (0x00000008U)
-#define TIM_DMABASE_CNT                    (0x00000009U)
-#define TIM_DMABASE_PSC                    (0x0000000AU)
-#define TIM_DMABASE_ARR                    (0x0000000BU)
-#define TIM_DMABASE_RCR                    (0x0000000CU)
-#define TIM_DMABASE_CCR1                   (0x0000000DU)
-#define TIM_DMABASE_CCR2                   (0x0000000EU)
-#define TIM_DMABASE_CCR3                   (0x0000000FU)
-#define TIM_DMABASE_CCR4                   (0x00000010U)
-#define TIM_DMABASE_BDTR                   (0x00000011U)
-#define TIM_DMABASE_DCR                    (0x00000012U)
-#define TIM_DMABASE_OR                     (0x00000013U)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_DMA_Burst_Length  TIM DMA Burst Length
-  * @{
-  */
-#define TIM_DMABURSTLENGTH_1TRANSFER           (0x00000000U)
-#define TIM_DMABURSTLENGTH_2TRANSFERS          (0x00000100U)
-#define TIM_DMABURSTLENGTH_3TRANSFERS          (0x00000200U)
-#define TIM_DMABURSTLENGTH_4TRANSFERS          (0x00000300U)
-#define TIM_DMABURSTLENGTH_5TRANSFERS          (0x00000400U)
-#define TIM_DMABURSTLENGTH_6TRANSFERS          (0x00000500U)
-#define TIM_DMABURSTLENGTH_7TRANSFERS          (0x00000600U)
-#define TIM_DMABURSTLENGTH_8TRANSFERS          (0x00000700U)
-#define TIM_DMABURSTLENGTH_9TRANSFERS          (0x00000800U)
-#define TIM_DMABURSTLENGTH_10TRANSFERS         (0x00000900U)
-#define TIM_DMABURSTLENGTH_11TRANSFERS         (0x00000A00U)
-#define TIM_DMABURSTLENGTH_12TRANSFERS         (0x00000B00U)
-#define TIM_DMABURSTLENGTH_13TRANSFERS         (0x00000C00U)
-#define TIM_DMABURSTLENGTH_14TRANSFERS         (0x00000D00U)
-#define TIM_DMABURSTLENGTH_15TRANSFERS         (0x00000E00U)
-#define TIM_DMABURSTLENGTH_16TRANSFERS         (0x00000F00U)
-#define TIM_DMABURSTLENGTH_17TRANSFERS         (0x00001000U)
-#define TIM_DMABURSTLENGTH_18TRANSFERS         (0x00001100U)
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Handle_index  DMA Handle index
-  * @{
-  */
-#define TIM_DMA_ID_UPDATE                ((uint16_t) 0x0U)       /*!< Index of the DMA handle used for Update DMA requests */
-#define TIM_DMA_ID_CC1                   ((uint16_t) 0x1U)       /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
-#define TIM_DMA_ID_CC2                   ((uint16_t) 0x2U)       /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
-#define TIM_DMA_ID_CC3                   ((uint16_t) 0x3U)       /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
-#define TIM_DMA_ID_CC4                   ((uint16_t) 0x4U)       /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
-#define TIM_DMA_ID_COMMUTATION           ((uint16_t) 0x5U)       /*!< Index of the DMA handle used for Commutation DMA requests */
-#define TIM_DMA_ID_TRIGGER               ((uint16_t) 0x6U)       /*!< Index of the DMA handle used for Trigger DMA requests */
-/**
-  * @}
-  */
-
-/** @defgroup Channel_CC_State  Channel CC State
-  * @{
-  */
-#define TIM_CCx_ENABLE                   ((uint32_t)0x0001U)
-#define TIM_CCx_DISABLE                  ((uint32_t)0x0000U)
-#define TIM_CCxN_ENABLE                  ((uint32_t)0x0004U)
-#define TIM_CCxN_DISABLE                 ((uint32_t)0x0000U)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup TIM_Exported_Macros TIM Exported Macros
-  * @{
-  */
-/** @brief Reset TIM handle state
-  * @param  __HANDLE__: TIM handle
-  * @retval None
-  */
-#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
-
-/**
-  * @brief  Enable the TIM peripheral.
-  * @param  __HANDLE__: TIM handle
-  * @retval None
- */
-#define __HAL_TIM_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
-
-/**
-  * @brief  Enable the TIM update source request.
-  * @param  __HANDLE__: TIM handle
-  * @retval None
- */
-#define __HAL_TIM_URS_ENABLE(__HANDLE__)             ((__HANDLE__)->Instance->CR1|=(TIM_CR1_URS))
-
-/**
-  * @brief  Enable the TIM main Output.
-  * @param  __HANDLE__: TIM handle
-  * @retval None
-  */
-#define __HAL_TIM_MOE_ENABLE(__HANDLE__)             ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
-
-
-/* The counter of a timer instance is disabled only if all the CCx and CCxN
-   channels have been disabled */
-#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
-#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
-
-/**
-  * @brief  Disable the TIM peripheral.
-  * @param  __HANDLE__: TIM handle
-  * @retval None
-  */
-#define __HAL_TIM_DISABLE(__HANDLE__) \
-                        do { \
-                          if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
-                          { \
-                            if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
-                            { \
-                              (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
-                            } \
-                          } \
-                        } while(0)
-
-/**
-  * @brief  Disable the TIM update source request.
-  * @param  __HANDLE__: TIM handle
-  * @retval None
- */
-#define __HAL_TIM_URS_DISABLE(__HANDLE__)            ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
-
-
-/* The Main Output of a timer instance is disabled only if all the CCx and CCxN
-   channels have been disabled */
-/**
-  * @brief  Disable the TIM main Output.
-  * @param  __HANDLE__: TIM handle
-  * @retval None
-  */
-#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
-                        do { \
-                          if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
-                          { \
-                            if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
-                            { \
-                              (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
-                            } \
-                          } \
-                        } while(0)
-
-#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
-#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)         ((__HANDLE__)->Instance->DIER |= (__DMA__))
-#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
-#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)        ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
-#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
-#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-
-#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
-
-#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__)            (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
-#define __HAL_TIM_SET_PRESCALER (__HANDLE__, __PRESC__)       ((__HANDLE__)->Instance->PSC = (__PRESC__))
-
-#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
- ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
-
-#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
- ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
-
-#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\
- ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12) & TIM_CCER_CC4P)))
-
-#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
- ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
-
-/**
-  * @brief  Sets the TIM Counter Register value on runtime.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __COUNTER__: specifies the Counter register new value.
-  * @retval None
-  */
-#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
-
-/**
-  * @brief  Gets the TIM Counter Register value on runtime.
-  * @param  __HANDLE__: TIM handle.
-  * @retval None
-  */
-#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
-
-/**
-  * @brief  Sets the TIM Autoreload Register value on runtime without calling
-  *         another time any Init function.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __AUTORELOAD__: specifies the Counter register new value.
-  * @retval None
-  */
-#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__)                  \
-                        do{                                                  \
-                            (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
-                            (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
-                          } while(0)
-/**
-  * @brief  Gets the TIM Autoreload Register value on runtime
-  * @param  __HANDLE__: TIM handle.
-  * @retval None
-  */
-#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
-
-/**
-  * @brief  Sets the TIM Clock Division value on runtime without calling
-  *         another time any Init function.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CKD__: specifies the clock division value.
-  *          This parameter can be one of the following value:
-  *            @arg TIM_CLOCKDIVISION_DIV1
-  *            @arg TIM_CLOCKDIVISION_DIV2
-  *            @arg TIM_CLOCKDIVISION_DIV4
-  * @retval None
-  */
-#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
-                        do{                                                             \
-                              (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD);  \
-                              (__HANDLE__)->Instance->CR1 |= (__CKD__);                 \
-                              (__HANDLE__)->Init.ClockDivision = (__CKD__);             \
-                          } while(0)
-/**
-  * @brief  Gets the TIM Clock Division value on runtime
-  * @param  __HANDLE__: TIM handle.
-  * @retval None
-  */
-#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
-
-/**
-  * @brief  Sets the TIM Input Capture prescaler on runtime without calling
-  *         another time HAL_TIM_IC_ConfigChannel() function.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CHANNEL__ : TIM Channels to be configured.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  __ICPSC__: specifies the Input Capture4 prescaler new value.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPSC_DIV1: no prescaler
-  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
-  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
-  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
-  * @retval None
-  */
-#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
-                        do{                                                    \
-                              TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
-                              TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
-                          } while(0)
-
-/**
-  * @brief  Gets the TIM Input Capture prescaler on runtime
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CHANNEL__ : TIM Channels to be configured.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value
-  *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value
-  *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value
-  *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value
-  * @retval None
-  */
-#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)  \
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
-   (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
-
-/**
-  * @brief  Sets the TIM Capture x input polarity on runtime.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CHANNEL__: TIM Channels to be configured.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  __POLARITY__: Polarity for TIx source
-  *            @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
-  *            @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
-  *            @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
-  * @note  The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized  for TIM Channel 4.
-  * @retval None
-  */
-#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)                          \
-                       do{                                                                            \
-                           TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
-                           TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
-                         }while(0)
-
-/**
-  * @}
-  */
-
-/* Include TIM HAL Extension module */
-#include "stm32f7xx_hal_tim_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIM_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group1
-  * @{
-  */
-
-/* Time Base functions ********************************************************/
-HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group2
-  * @{
-  */
-/* Timer Output Compare functions **********************************************/
-HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group3
-  * @{
-  */
-/* Timer PWM functions *********************************************************/
-HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group4
-  * @{
-  */
-/* Timer Input Capture functions ***********************************************/
-HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group5
-  * @{
-  */
-/* Timer One Pulse functions ***************************************************/
-HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
-HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group6
-  * @{
-  */
-/* Timer Encoder functions *****************************************************/
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef* sConfig);
-HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
- /* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group7
-  * @{
-  */
-/* Interrupt Handler functions  **********************************************/
-void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
-
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group8
-  * @{
-  */
-/* Control functions  *********************************************************/
-HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel,  uint32_t InputChannel);
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
-HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
-                                              uint32_t  *BurstBuffer, uint32_t  BurstLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
-                                              uint32_t  *BurstBuffer, uint32_t  BurstLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
-HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
-uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group9
-  * @{
-  */
-/* Callback in non blocking modes (Interrupt and DMA) *************************/
-void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
-
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group10
-  * @{
-  */
-/* Peripheral State functions  **************************************************/
-HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup TIM_Private_Macros TIM Private Macros
-  * @{
-  */
-
-/** @defgroup TIM_IS_TIM_Definitions TIM Private macros to check input parameters
-  * @{
-  */
-#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP)              || \
-                                       ((__MODE__) == TIM_COUNTERMODE_DOWN)            || \
-                                       ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
-                                       ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
-                                       ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
-
-#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
-                                           ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
-                                           ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
-
-#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \
-                                      ((__STATE__) == TIM_OCFAST_ENABLE))
-
-#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \
-                                    ((STATE) == TIM_OUTPUTSTATE_ENABLE))
-
-#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \
-                                     ((STATE) == TIM_OUTPUTNSTATE_ENABLE))
-
-#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
-                                          ((__POLARITY__) == TIM_OCPOLARITY_LOW))
-
-#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
-                                           ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
-
-#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \
-                                        ((__STATE__) == TIM_OCIDLESTATE_RESET))
-
-#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
-                                         ((__STATE__) == TIM_OCNIDLESTATE_RESET))
-
-#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \
-                                          ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \
-                                          ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
-
-#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
-                                            ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
-                                            ((__SELECTION__) == TIM_ICSELECTION_TRC))
-
-#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
-                                            ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
-                                            ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
-                                            ((__PRESCALER__) == TIM_ICPSC_DIV8))
-
-#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
-                                   ((__MODE__) == TIM_OPMODE_REPETITIVE))
-
-#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \
-                                       ((__MODE__) == TIM_ENCODERMODE_TI2) || \
-                                       ((__MODE__) == TIM_ENCODERMODE_TI12))
-
-#define IS_TIM_IT(__IT__) ((((__IT__) & 0xFFFFFF00U) == 0x00000000U) && ((__IT__) != 0x00000000U))
-
-
-#define IS_TIM_GET_IT(__IT__) (((__IT__) == TIM_IT_UPDATE)  || \
-                               ((__IT__) == TIM_IT_CC1)     || \
-                               ((__IT__) == TIM_IT_CC2)     || \
-                               ((__IT__) == TIM_IT_CC3)     || \
-                               ((__IT__) == TIM_IT_CC4)     || \
-                               ((__IT__) == TIM_IT_COM)     || \
-                               ((__IT__) == TIM_IT_TRIGGER) || \
-                               ((__IT__) == TIM_IT_BREAK))
-
-#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
-
-#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
-
-#define IS_TIM_FLAG(__FLAG__) (((__FLAG__) == TIM_FLAG_UPDATE) || \
-                               ((__FLAG__) == TIM_FLAG_CC1)     || \
-                               ((__FLAG__) == TIM_FLAG_CC2)     || \
-                               ((__FLAG__) == TIM_FLAG_CC3)     || \
-                               ((__FLAG__) == TIM_FLAG_CC4)     || \
-                               ((__FLAG__) == TIM_FLAG_COM)     || \
-                               ((__FLAG__) == TIM_FLAG_TRIGGER) || \
-                               ((__FLAG__) == TIM_FLAG_BREAK)   || \
-                               ((__FLAG__) == TIM_FLAG_BREAK2)  || \
-                               ((__FLAG__) == TIM_FLAG_CC1OF)   || \
-                               ((__FLAG__) == TIM_FLAG_CC2OF)   || \
-                               ((__FLAG__) == TIM_FLAG_CC3OF)   || \
-                               ((__FLAG__) == TIM_FLAG_CC4OF))
-
-#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)     || \
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
-
-#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED)    || \
-                                        ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
-                                        ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING)      || \
-                                        ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING)     || \
-                                        ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
-
-#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
-                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
-                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
-                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
-
-#define IS_TIM_CLOCKFILTER(__ICFILTER__)      ((__ICFILTER__) <= 0xF)
-
-#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
-                                                    ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
-
-#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__)   (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
-                                                 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
-                                                 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
-                                                 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
-
-#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
-
-#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \
-                                      ((__STATE__) == TIM_OSSR_DISABLE))
-
-#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \
-                                      ((__STATE__) == TIM_OSSI_DISABLE))
-
-#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
-                                      ((__LEVEL__) == TIM_LOCKLEVEL_1) || \
-                                      ((__LEVEL__) == TIM_LOCKLEVEL_2) || \
-                                      ((__LEVEL__) == TIM_LOCKLEVEL_3))
-
-#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
-                                       ((__STATE__) == TIM_BREAK_DISABLE))
-
-#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
-                                             ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
-
-#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
-                                                  ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
-
-#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \
-                                        ((__SOURCE__) == TIM_TRGO_ENABLE) || \
-                                        ((__SOURCE__) == TIM_TRGO_UPDATE) || \
-                                        ((__SOURCE__) == TIM_TRGO_OC1) || \
-                                        ((__SOURCE__) == TIM_TRGO_OC1REF) || \
-                                        ((__SOURCE__) == TIM_TRGO_OC2REF) || \
-                                        ((__SOURCE__) == TIM_TRGO_OC3REF) || \
-                                        ((__SOURCE__) == TIM_TRGO_OC4REF))
-
-#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
-                                     ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
-
-#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
-                                                 ((__SELECTION__) == TIM_TS_ITR1) || \
-                                                 ((__SELECTION__) == TIM_TS_ITR2) || \
-                                                 ((__SELECTION__) == TIM_TS_ITR3) || \
-                                                 ((__SELECTION__) == TIM_TS_TI1F_ED) || \
-                                                 ((__SELECTION__) == TIM_TS_TI1FP1) || \
-                                                 ((__SELECTION__) == TIM_TS_TI2FP2) || \
-                                                 ((__SELECTION__) == TIM_TS_ETRF))
-
-#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
-                                                      ((SELECTION) == TIM_TS_ITR1) || \
-                                                      ((SELECTION) == TIM_TS_ITR2) || \
-                                                      ((SELECTION) == TIM_TS_ITR3))
-
-#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
-                                                               ((__SELECTION__) == TIM_TS_ITR1) || \
-                                                               ((__SELECTION__) == TIM_TS_ITR2) || \
-                                                               ((__SELECTION__) == TIM_TS_ITR3) || \
-                                                               ((__SELECTION__) == TIM_TS_NONE))
-
-#define IS_TIM_TRIGGERPOLARITY(__POLARITY__)     (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
-                                                  ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
-                                                  ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING     ) || \
-                                                  ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING    ) || \
-                                                  ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))
-
-#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__)  (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
-                                                 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
-                                                 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
-                                                 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
-
-#define IS_TIM_TRIGGERFILTER(__ICFILTER__)     ((__ICFILTER__) <= 0xF)
-
-#define IS_TIM_TI1SELECTION(__TI1SELECTION__)   (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
-                                                 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
-
-#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
-                                   ((__BASE__) == TIM_DMABASE_CR2) || \
-                                   ((__BASE__) == TIM_DMABASE_SMCR) || \
-                                   ((__BASE__) == TIM_DMABASE_DIER) || \
-                                   ((__BASE__) == TIM_DMABASE_SR) || \
-                                   ((__BASE__) == TIM_DMABASE_EGR) || \
-                                   ((__BASE__) == TIM_DMABASE_CCMR1) || \
-                                   ((__BASE__) == TIM_DMABASE_CCMR2) || \
-                                   ((__BASE__) == TIM_DMABASE_CCER) || \
-                                   ((__BASE__) == TIM_DMABASE_CNT) || \
-                                   ((__BASE__) == TIM_DMABASE_PSC) || \
-                                   ((__BASE__) == TIM_DMABASE_ARR) || \
-                                   ((__BASE__) == TIM_DMABASE_RCR) || \
-                                   ((__BASE__) == TIM_DMABASE_CCR1) || \
-                                   ((__BASE__) == TIM_DMABASE_CCR2) || \
-                                   ((__BASE__) == TIM_DMABASE_CCR3) || \
-                                   ((__BASE__) == TIM_DMABASE_CCR4) || \
-                                   ((__BASE__) == TIM_DMABASE_BDTR) || \
-                                   ((__BASE__) == TIM_DMABASE_DCR) || \
-                                   ((__BASE__) == TIM_DMABASE_OR))
-
-#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
-                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
-                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
-                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
-                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
-                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
-                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
-                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
-                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
-                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
-                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
-                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
-                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
-                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
-                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
-                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
-                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
-                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
-
-#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup TIM_Private_Functions TIM Private Functions
-  * @{
-  */
-void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
-void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
-void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
-
-void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
-void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma);
-void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
-void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F7xx_HAL_TIM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_tim_ex.h b/stmhal/hal/f7/inc/stm32f7xx_hal_tim_ex.h
deleted file mode 100644
index d8bdef6772..0000000000
--- a/stmhal/hal/f7/inc/stm32f7xx_hal_tim_ex.h
+++ /dev/null
@@ -1,608 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_tim_ex.h
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   Header file of TIM HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_TIM_EX_H
-#define __STM32F7xx_HAL_TIM_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal_def.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup TIMEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Types TIM Exported Types
-  * @{
-  */
-
-/**
-  * @brief  TIM Hall sensor Configuration Structure definition
-  */
-
-typedef struct
-{
-
-  uint32_t IC1Polarity;            /*!< Specifies the active edge of the input signal.
-                                        This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
-  uint32_t IC1Prescaler;        /*!< Specifies the Input Capture Prescaler.
-                                     This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
-  uint32_t IC1Filter;           /*!< Specifies the input capture filter.
-                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-  uint32_t Commutation_Delay;  /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
-                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-} TIM_HallSensor_InitTypeDef;
-
-/**
-  * @brief  TIM Master configuration Structure definition
-  */
-typedef struct {
-  uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection.
-                                      This parameter can be a value of @ref TIM_Master_Mode_Selection */
-  uint32_t  MasterOutputTrigger2;  /*!< Trigger output2 (TRGO2) selection
-                                      This parameter can be a value of @ref TIMEx_Master_Mode_Selection_2 */
-  uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection.
-                                      This parameter can be a value of @ref TIM_Master_Slave_Mode */
-}TIM_MasterConfigTypeDef;
-
-/**
-  * @brief  TIM Break input(s) and Dead time configuration Structure definition
-  * @note   2 break inputs can be configured (BKIN and BKIN2) with configurable
-  *        filter and polarity.
-  */
-typedef struct
-{
-  uint32_t OffStateRunMode;	    /*!< TIM off state in run mode.
-                                       This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
-  uint32_t OffStateIDLEMode;	    /*!< TIM off state in IDLE mode.
-                                       This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
-  uint32_t LockLevel;	 	        /*!< TIM Lock level.
-                                       This parameter can be a value of @ref TIM_Lock_level */
-  uint32_t DeadTime;	 	        /*!< TIM dead Time.
-                                       This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
-  uint32_t BreakState;	 	        /*!< TIM Break State.
-                                       This parameter can be a value of @ref TIM_Break_Input_enable_disable */
-  uint32_t BreakPolarity;           /*!< TIM Break input polarity.
-                                       This parameter can be a value of @ref TIM_Break_Polarity */
-  uint32_t BreakFilter;             /*!< Specifies the break input filter.
-                                       This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-  uint32_t Break2State;	 	        /*!< TIM Break2 State
-                                       This parameter can be a value of @ref TIMEx_Break2_Input_enable_disable */
-  uint32_t Break2Polarity;          /*!< TIM Break2 input polarity
-                                       This parameter can be a value of @ref TIMEx_Break2_Polarity */
-  uint32_t Break2Filter;            /*!< TIM break2 input filter.
-                                       This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-  uint32_t AutomaticOutput;         /*!< TIM Automatic Output Enable state
-                                       This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
-} TIM_BreakDeadTimeConfigTypeDef;
-
-#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
-/**
-  * @brief  TIM Break/Break2 input configuration
-  */
-typedef struct {
-  uint32_t Source;         /*!< Specifies the source of the timer break input.
-                                This parameter can be a value of @ref TIMEx_Break_Input_Source */
-  uint32_t Enable;         /*!< Specifies whether or not the break input source is enabled.
-                                This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */
-} TIMEx_BreakInputConfigTypeDef;
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-/**
-  * @}
-  */
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Constants  TIMEx Exported Constants
-  * @{
-  */
-
-/** @defgroup TIMEx_Channel TIMEx Channel
-  * @{
-  */
-
-#define TIM_CHANNEL_1                      ((uint32_t)0x0000U)
-#define TIM_CHANNEL_2                      ((uint32_t)0x0004U)
-#define TIM_CHANNEL_3                      ((uint32_t)0x0008U)
-#define TIM_CHANNEL_4                      ((uint32_t)0x000CU)
-#define TIM_CHANNEL_5                      ((uint32_t)0x0010U)
-#define TIM_CHANNEL_6                      ((uint32_t)0x0014U)
-#define TIM_CHANNEL_ALL                    ((uint32_t)0x003CU)
-
-/**
-  * @}
-  */
-
-/** @defgroup TIMEx_Output_Compare_and_PWM_modes TIMEx Output Compare and PWM Modes
-  * @{
-  */
-#define TIM_OCMODE_TIMING                   ((uint32_t)0x0000U)
-#define TIM_OCMODE_ACTIVE                   ((uint32_t)TIM_CCMR1_OC1M_0)
-#define TIM_OCMODE_INACTIVE                 ((uint32_t)TIM_CCMR1_OC1M_1)
-#define TIM_OCMODE_TOGGLE                   ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
-#define TIM_OCMODE_PWM1                     ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
-#define TIM_OCMODE_PWM2                     ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
-#define TIM_OCMODE_FORCED_ACTIVE            ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
-#define TIM_OCMODE_FORCED_INACTIVE          ((uint32_t)TIM_CCMR1_OC1M_2)
-
-#define TIM_OCMODE_RETRIGERRABLE_OPM1      ((uint32_t)TIM_CCMR1_OC1M_3)
-#define TIM_OCMODE_RETRIGERRABLE_OPM2      ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
-#define TIM_OCMODE_COMBINED_PWM1           ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
-#define TIM_OCMODE_COMBINED_PWM2           ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
-#define TIM_OCMODE_ASSYMETRIC_PWM1         ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
-#define TIM_OCMODE_ASSYMETRIC_PWM2         ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)
-/**
-  * @}
-  */
-
-/** @defgroup TIMEx_Remap  TIMEx Remap
-  * @{
-  */
-#define TIM_TIM2_TIM8_TRGO                     (0x00000000U)
-#define TIM_TIM2_ETH_PTP                       (0x00000400U)
-#define TIM_TIM2_USBFS_SOF                     (0x00000800U)
-#define TIM_TIM2_USBHS_SOF                     (0x00000C00U)
-#define TIM_TIM5_GPIO                          (0x00000000U)
-#define TIM_TIM5_LSI                           (0x00000040U)
-#define TIM_TIM5_LSE                           (0x00000080U)
-#define TIM_TIM5_RTC                           (0x000000C0U)
-#define TIM_TIM11_GPIO                         (0x00000000U)
-#define TIM_TIM11_SPDIFRX                      (0x00000001U)
-#define TIM_TIM11_HSE                          (0x00000002U)
-#define TIM_TIM11_MCO1                         (0x00000003U)
-/**
-  * @}
-  */
-
-/** @defgroup TIMEx_ClearInput_Source TIMEx Clear Input Source
-  * @{
-  */
-#define TIM_CLEARINPUTSOURCE_ETR            ((uint32_t)0x0001U)
-#define TIM_CLEARINPUTSOURCE_OCREFCLR       ((uint32_t)0x0002U)
-#define TIM_CLEARINPUTSOURCE_NONE           ((uint32_t)0x0000U)
-/**
-  * @}
-  */
-
-/** @defgroup TIMEx_Break2_Input_enable_disable  TIMEx Break input 2 Enable
-  * @{
-  */
-#define TIM_BREAK2_DISABLE         ((uint32_t)0x00000000U)
-#define TIM_BREAK2_ENABLE          ((uint32_t)TIM_BDTR_BK2E)
-/**
-  * @}
-  */
-
-/** @defgroup TIMEx_Break2_Polarity TIMEx Break2 Polarity
-  * @{
-  */
-#define TIM_BREAK2POLARITY_LOW        ((uint32_t)0x00000000U)
-#define TIM_BREAK2POLARITY_HIGH       (TIM_BDTR_BK2P)
-/**
-  * @}
-  */
-
-/** @defgroup TIMEx_Group_Channel5 TIMEx Group Channel 5 and Channel 1, 2 or 3
-  * @{
-  */
-#define TIM_GROUPCH5_NONE       ((uint32_t)0x00000000U)  /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
-#define TIM_GROUPCH5_OC1REFC    (TIM_CCR5_GC5C1)      /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
-#define TIM_GROUPCH5_OC2REFC    (TIM_CCR5_GC5C2)      /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
-#define TIM_GROUPCH5_OC3REFC    (TIM_CCR5_GC5C3)       /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */
-/**
-  * @}
-  */
-
-/** @defgroup TIMEx_Master_Mode_Selection_2 TIMEx Master Mode Selection 2 (TRGO2)
-  * @{
-  */
-#define	TIM_TRGO2_RESET                          ((uint32_t)0x00000000U)
-#define	TIM_TRGO2_ENABLE                         ((uint32_t)(TIM_CR2_MMS2_0))
-#define	TIM_TRGO2_UPDATE                         ((uint32_t)(TIM_CR2_MMS2_1))
-#define	TIM_TRGO2_OC1                            ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
-#define	TIM_TRGO2_OC1REF                         ((uint32_t)(TIM_CR2_MMS2_2))
-#define	TIM_TRGO2_OC2REF                         ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
-#define	TIM_TRGO2_OC3REF                         ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1))
-#define	TIM_TRGO2_OC4REF                         ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
-#define	TIM_TRGO2_OC5REF                         ((uint32_t)(TIM_CR2_MMS2_3))
-#define	TIM_TRGO2_OC6REF                         ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0))
-#define	TIM_TRGO2_OC4REF_RISINGFALLING           ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1))
-#define	TIM_TRGO2_OC6REF_RISINGFALLING           ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
-#define	TIM_TRGO2_OC4REF_RISING_OC6REF_RISING    ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2))
-#define	TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING   ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
-#define	TIM_TRGO2_OC5REF_RISING_OC6REF_RISING    ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1))
-#define	TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING   ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
-/**
-  * @}
-  */
-
-/** @defgroup TIMEx_Slave_Mode TIMEx Slave mode
-  * @{
-  */
-#define TIM_SLAVEMODE_DISABLE                ((uint32_t)0x0000U)
-#define TIM_SLAVEMODE_RESET                  ((uint32_t)(TIM_SMCR_SMS_2))
-#define TIM_SLAVEMODE_GATED                  ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))
-#define TIM_SLAVEMODE_TRIGGER                ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))
-#define TIM_SLAVEMODE_EXTERNAL1              ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))
-#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER  ((uint32_t)(TIM_SMCR_SMS_3))
-/**
-  * @}
-  */
-#if defined(STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
-/** @defgroup TIMEx_Break_Input TIM  Extended Break input
-  * @{
-  */
-#define TIM_BREAKINPUT_BRK     ((uint32_t)0x00000001U) /* !< Timer break input  */
-#define TIM_BREAKINPUT_BRK2    ((uint32_t)0x00000002U) /* !< Timer break2 input */
-/**
-  * @}
-  */
-
-/** @defgroup TIMEx_Break_Input_Source TIM  Extended Break input source
-  * @{
-  */
-#define TIM_BREAKINPUTSOURCE_BKIN     ((uint32_t)0x00000001U) /* !< An external source (GPIO) is connected to the BKIN pin  */
-#define TIM_BREAKINPUTSOURCE_DFSDM1    ((uint32_t)0x00000008U) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */
-/**
-  * @}
-  */
-
-/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling
-  * @{
-  */
-#define TIM_BREAKINPUTSOURCE_DISABLE     ((uint32_t)0x00000000U) /* !< Break input source is disabled */
-#define TIM_BREAKINPUTSOURCE_ENABLE      ((uint32_t)0x00000001U) /* !< Break input source is enabled */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Macros TIMEx Exported Macros
-  * @{
-  */
-
-/**
-  * @brief  Sets the TIM Capture Compare Register value on runtime without
-  *         calling another time ConfigChannel function.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CHANNEL__ : TIM Channels to be configured.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
-  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
-  * @param  __COMPARE__: specifies the Capture Compare register new value.
-  * @retval None
-  */
-#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
- ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
-
-/**
-  * @brief  Gets the TIM Capture Compare Register value on runtime
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CHANNEL__ : TIM Channel associated with the capture compare register
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: get capture/compare 1 register value
-  *            @arg TIM_CHANNEL_2: get capture/compare 2 register value
-  *            @arg TIM_CHANNEL_3: get capture/compare 3 register value
-  *            @arg TIM_CHANNEL_4: get capture/compare 4 register value
-  *            @arg TIM_CHANNEL_5: get capture/compare 5 register value
-  *            @arg TIM_CHANNEL_6: get capture/compare 6 register value
-  * @retval None
-  */
-#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
- ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
- ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
- ((__HANDLE__)->Instance->CCR6))
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIMEx_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup TIMEx_Exported_Functions_Group1
-  * @{
-  */
-/*  Timer Hall Sensor functions  **********************************************/
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef* htim, TIM_HallSensor_InitTypeDef* sConfig);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef* htim);
-
-void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef* htim);
-void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef* htim);
-
- /* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef* htim);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef* htim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef* htim);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef* htim);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef* htim, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef* htim);
-/**
-  * @}
-  */
-
-/** @addtogroup TIMEx_Exported_Functions_Group2
-  * @{
-  */
-/*  Timer Complementary Output Compare functions  *****************************/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);
-
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
-
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);
-/**
-  * @}
-  */
-
-/** @addtogroup TIMEx_Exported_Functions_Group3
-  * @{
-  */
-/*  Timer Complementary PWM functions  ****************************************/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);
-
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);
-/**
-  * @}
-  */
-
-/** @addtogroup TIMEx_Exported_Functions_Group4
-  * @{
-  */
-/*  Timer Complementary One Pulse functions  **********************************/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
-
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
-/**
-  * @}
-  */
-
-/** @addtogroup TIMEx_Exported_Functions_Group5
-  * @{
-  */
-/* Extension Control functions  ************************************************/
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef* htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef* htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef* htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef* htim, TIM_MasterConfigTypeDef * sMasterConfig);
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef* htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
-#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef* htim, uint32_t Remap);
-HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t OCRef);
-/**
-  * @}
-  */
-
-/** @addtogroup TIMEx_Exported_Functions_Group6
-  * @{
-  */
-/* Extension Callback *********************************************************/
-void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef* htim);
-void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef* htim);
-void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
-/**
-  * @}
-  */
-
-/** @addtogroup TIMEx_Exported_Functions_Group7
-  * @{
-  */
-/* Extension Peripheral State functions  **************************************/
-HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef* htim);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup TIMEx_Private_Macros TIMEx Private Macros
-  * @{
-  */
-#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
-                                  ((CHANNEL) == TIM_CHANNEL_2) || \
-                                  ((CHANNEL) == TIM_CHANNEL_3) || \
-                                  ((CHANNEL) == TIM_CHANNEL_4) || \
-                                  ((CHANNEL) == TIM_CHANNEL_5) || \
-                                  ((CHANNEL) == TIM_CHANNEL_6) || \
-                                  ((CHANNEL) == TIM_CHANNEL_ALL))
-
-#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
-                                       ((CHANNEL) == TIM_CHANNEL_2))
-
-#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
-                                      ((CHANNEL) == TIM_CHANNEL_2))
-
-#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
-                                                ((CHANNEL) == TIM_CHANNEL_2) || \
-                                                ((CHANNEL) == TIM_CHANNEL_3))
-#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1)               || \
-	                       ((MODE) == TIM_OCMODE_PWM2)               || \
-                               ((MODE) == TIM_OCMODE_COMBINED_PWM1)      || \
-                               ((MODE) == TIM_OCMODE_COMBINED_PWM2)      || \
-                               ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM1)    || \
-                               ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM2))
-
-#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING)             || \
-                             ((MODE) == TIM_OCMODE_ACTIVE)             || \
-                             ((MODE) == TIM_OCMODE_INACTIVE)           || \
-                             ((MODE) == TIM_OCMODE_TOGGLE)             || \
-                             ((MODE) == TIM_OCMODE_FORCED_ACTIVE)      || \
-                             ((MODE) == TIM_OCMODE_FORCED_INACTIVE)    || \
-                             ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
-                             ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM2))
-#define IS_TIM_REMAP(__TIM_REMAP__)	 (((__TIM_REMAP__) == TIM_TIM2_TIM8_TRGO)||\
-                                      ((__TIM_REMAP__) == TIM_TIM2_ETH_PTP)||\
-                                      ((__TIM_REMAP__) == TIM_TIM2_USBFS_SOF)||\
-                                      ((__TIM_REMAP__) == TIM_TIM2_USBHS_SOF)||\
-                                      ((__TIM_REMAP__) == TIM_TIM5_GPIO)||\
-                                      ((__TIM_REMAP__) == TIM_TIM5_LSI)||\
-                                      ((__TIM_REMAP__) == TIM_TIM5_LSE)||\
-                                      ((__TIM_REMAP__) == TIM_TIM5_RTC)||\
-                                      ((__TIM_REMAP__) == TIM_TIM11_GPIO)||\
-                                      ((__TIM_REMAP__) == TIM_TIM11_SPDIFRX)||\
-                                      ((__TIM_REMAP__) == TIM_TIM11_HSE)||\
-                                      ((__TIM_REMAP__) == TIM_TIM11_MCO1))
-#define IS_TIM_DEADTIME(__DEADTIME__)      ((__DEADTIME__) <= 0xFF)
-#define IS_TIM_BREAK_FILTER(__FILTER__) ((__FILTER__) <= 0xF)
-#define IS_TIM_CLEARINPUT_SOURCE(MODE) (((MODE) == TIM_CLEARINPUTSOURCE_ETR)      || \
-                                        ((MODE) == TIM_CLEARINPUTSOURCE_OCREFCLR)  || \
-                                        ((MODE) == TIM_CLEARINPUTSOURCE_NONE))
-#define IS_TIM_BREAK2_STATE(STATE) (((STATE) == TIM_BREAK2_ENABLE) || \
-                                    ((STATE) == TIM_BREAK2_DISABLE))
-#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
-                                              ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
-#define IS_TIM_GROUPCH5(OCREF) ((((OCREF) & 0x1FFFFFFF) == 0x00000000))
-#define IS_TIM_TRGO2_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO2_RESET)                        || \
-                                     ((SOURCE) == TIM_TRGO2_ENABLE)                       || \
-                                     ((SOURCE) == TIM_TRGO2_UPDATE)                       || \
-                                     ((SOURCE) == TIM_TRGO2_OC1)                          || \
-                                     ((SOURCE) == TIM_TRGO2_OC1REF)                       || \
-                                     ((SOURCE) == TIM_TRGO2_OC2REF)                       || \
-                                     ((SOURCE) == TIM_TRGO2_OC3REF)                       || \
-                                     ((SOURCE) == TIM_TRGO2_OC3REF)                       || \
-                                     ((SOURCE) == TIM_TRGO2_OC4REF)                       || \
-                                     ((SOURCE) == TIM_TRGO2_OC5REF)                       || \
-                                     ((SOURCE) == TIM_TRGO2_OC6REF)                       || \
-                                     ((SOURCE) == TIM_TRGO2_OC4REF_RISINGFALLING)         || \
-                                     ((SOURCE) == TIM_TRGO2_OC6REF_RISINGFALLING)         || \
-                                     ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING)  || \
-                                     ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
-                                     ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING)  || \
-                                     ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
-#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE)   || \
-                                 ((MODE) == TIM_SLAVEMODE_RESET)     || \
-                                 ((MODE) == TIM_SLAVEMODE_GATED)     || \
-                                 ((MODE) == TIM_SLAVEMODE_TRIGGER)   || \
-                                 ((MODE) == TIM_SLAVEMODE_EXTERNAL1) || \
-                                 ((MODE) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
-
-#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
-#define IS_TIM_BREAKINPUT(__BREAKINPUT__)  (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK)  || \
-                                            ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
-
-#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__)  (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)  || \
-                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM))
-
-#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__)  (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE)  || \
-                                                   ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
-
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F7xx_HAL_TIM_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_uart.h b/stmhal/hal/f7/inc/stm32f7xx_hal_uart.h
deleted file mode 100644
index 96050a2b00..0000000000
--- a/stmhal/hal/f7/inc/stm32f7xx_hal_uart.h
+++ /dev/null
@@ -1,1221 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_uart.h
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   Header file of UART HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_UART_H
-#define __STM32F7xx_HAL_UART_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal_def.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup UART
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup UART_Exported_Types UART Exported Types
-  * @{
-  */
-
-/**
-  * @brief UART Init Structure definition
-  */
-typedef struct
-{
-  uint32_t BaudRate;                  /*!< This member configures the UART communication baud rate.
-                                           The baud rate register is computed using the following formula:
-                                           - If oversampling is 16 or in LIN mode,
-                                              Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate)))
-                                           - If oversampling is 8,
-                                              Baud Rate Register[15:4] = ((2 * PCLKx) / ((huart->Init.BaudRate)))[15:4]
-                                              Baud Rate Register[3] =  0
-                                              Baud Rate Register[2:0] =  (((2 * PCLKx) / ((huart->Init.BaudRate)))[3:0]) >> 1      */
-
-  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
-                                           This parameter can be a value of @ref UARTEx_Word_Length */
-
-  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
-                                           This parameter can be a value of @ref UART_Stop_Bits */
-
-  uint32_t Parity;                    /*!< Specifies the parity mode.
-                                           This parameter can be a value of @ref UART_Parity
-                                           @note When parity is enabled, the computed parity is inserted
-                                                 at the MSB position of the transmitted data (9th bit when
-                                                 the word length is set to 9 data bits; 8th bit when the
-                                                 word length is set to 8 data bits). */
-
-  uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
-                                           This parameter can be a value of @ref UART_Mode */
-
-  uint32_t HwFlowCtl;                 /*!< Specifies whether the hardware flow control mode is enabled
-                                           or disabled.
-                                           This parameter can be a value of @ref UART_Hardware_Flow_Control */
-
-  uint32_t OverSampling;              /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
-                                           This parameter can be a value of @ref UART_Over_Sampling */
-
-  uint32_t OneBitSampling;            /*!< Specifies whether a single sample or three samples' majority vote is selected.
-                                           Selecting the single sample method increases the receiver tolerance to clock
-                                           deviations. This parameter can be a value of @ref UART_OneBit_Sampling */
-}UART_InitTypeDef;
-
-/**
-  * @brief  UART Advanced Features initialization structure definition
-  */
-typedef struct
-{
-  uint32_t AdvFeatureInit;        /*!< Specifies which advanced UART features is initialized. Several
-                                       Advanced Features may be initialized at the same time .
-                                       This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type */
-
-  uint32_t TxPinLevelInvert;      /*!< Specifies whether the TX pin active level is inverted.
-                                       This parameter can be a value of @ref UART_Tx_Inv  */
-
-  uint32_t RxPinLevelInvert;      /*!< Specifies whether the RX pin active level is inverted.
-                                       This parameter can be a value of @ref UART_Rx_Inv  */
-
-  uint32_t DataInvert;            /*!< Specifies whether data are inverted (positive/direct logic
-                                       vs negative/inverted logic).
-                                       This parameter can be a value of @ref UART_Data_Inv */
-
-  uint32_t Swap;                  /*!< Specifies whether TX and RX pins are swapped.
-                                       This parameter can be a value of @ref UART_Rx_Tx_Swap */
-
-  uint32_t OverrunDisable;        /*!< Specifies whether the reception overrun detection is disabled.
-                                       This parameter can be a value of @ref UART_Overrun_Disable */
-
-  uint32_t DMADisableonRxError;   /*!< Specifies whether the DMA is disabled in case of reception error.
-                                       This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error */
-
-  uint32_t AutoBaudRateEnable;    /*!< Specifies whether auto Baud rate detection is enabled.
-                                       This parameter can be a value of @ref UART_AutoBaudRate_Enable */
-
-  uint32_t AutoBaudRateMode;      /*!< If auto Baud rate detection is enabled, specifies how the rate
-                                       detection is carried out.
-                                       This parameter can be a value of @ref UART_AutoBaud_Rate_Mode */
-
-  uint32_t MSBFirst;              /*!< Specifies whether MSB is sent first on UART line.
-                                       This parameter can be a value of @ref UART_MSB_First */
-} UART_AdvFeatureInitTypeDef;
-
-
-
-/**
-  * @brief HAL UART State structures definition
-  * @note  HAL UART State value is a combination of 2 different substates: gState and RxState.
-  *        - gState contains UART state information related to global Handle management
-  *          and also information related to Tx operations.
-  *          gState value coding follow below described bitmap :
-  *          b7-b6  Error information
-  *             00 : No Error
-  *             01 : (Not Used)
-  *             10 : Timeout
-  *             11 : Error
-  *          b5     IP initilisation status
-  *             0  : Reset (IP not initialized)
-  *             1  : Init done (IP not initialized. HAL UART Init function already called)
-  *          b4-b3  (not used)
-  *             xx : Should be set to 00
-  *          b2     Intrinsic process state
-  *             0  : Ready
-  *             1  : Busy (IP busy with some configuration or internal operations)
-  *          b1     (not used)
-  *             x  : Should be set to 0
-  *          b0     Tx state
-  *             0  : Ready (no Tx operation ongoing)
-  *             1  : Busy (Tx operation ongoing)
-  *        - RxState contains information related to Rx operations.
-  *          RxState value coding follow below described bitmap :
-  *          b7-b6  (not used)
-  *             xx : Should be set to 00
-  *          b5     IP initilisation status
-  *             0  : Reset (IP not initialized)
-  *             1  : Init done (IP not initialized)
-  *          b4-b2  (not used)
-  *            xxx : Should be set to 000
-  *          b1     Rx state
-  *             0  : Ready (no Rx operation ongoing)
-  *             1  : Busy (Rx operation ongoing)
-  *          b0     (not used)
-  *             x  : Should be set to 0.
-  */
-typedef enum
-{
-  HAL_UART_STATE_RESET             = 0x00U,   /*!< Peripheral is not initialized
-                                                   Value is allowed for gState and RxState */
-  HAL_UART_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use
-                                                   Value is allowed for gState and RxState */
-  HAL_UART_STATE_BUSY              = 0x24U,   /*!< an internal process is ongoing
-                                                   Value is allowed for gState only */
-  HAL_UART_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing
-                                                   Value is allowed for gState only */
-  HAL_UART_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing
-                                                   Value is allowed for RxState only */
-  HAL_UART_STATE_BUSY_TX_RX        = 0x23U,   /*!< Data Transmission and Reception process is ongoing
-                                                   Not to be used for neither gState nor RxState.
-                                                   Value is result of combination (Or) between gState and RxState values */
-  HAL_UART_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state
-                                                   Value is allowed for gState only */
-  HAL_UART_STATE_ERROR             = 0xE0U    /*!< Error
-                                                   Value is allowed for gState only */
-}HAL_UART_StateTypeDef;
-
-/**
-  * @brief UART clock sources definition
-  */
-typedef enum
-{
-  UART_CLOCKSOURCE_PCLK1      = 0x00U,    /*!< PCLK1 clock source  */
-  UART_CLOCKSOURCE_PCLK2      = 0x01U,    /*!< PCLK2 clock source  */
-  UART_CLOCKSOURCE_HSI        = 0x02U,    /*!< HSI clock source    */
-  UART_CLOCKSOURCE_SYSCLK     = 0x04U,    /*!< SYSCLK clock source */
-  UART_CLOCKSOURCE_LSE        = 0x08U,    /*!< LSE clock source       */
-  UART_CLOCKSOURCE_UNDEFINED  = 0x10U     /*!< Undefined clock source */
-}UART_ClockSourceTypeDef;
-
-/**
-  * @brief  UART handle Structure definition
-  */
-typedef struct
-{
-  USART_TypeDef            *Instance;        /*!< UART registers base address        */
-
-  UART_InitTypeDef         Init;             /*!< UART communication parameters      */
-
-  UART_AdvFeatureInitTypeDef AdvancedInit;   /*!< UART Advanced Features initialization parameters */
-
-  uint8_t                  *pTxBuffPtr;      /*!< Pointer to UART Tx transfer Buffer */
-
-  uint16_t                 TxXferSize;       /*!< UART Tx Transfer size              */
-
-  __IO uint16_t            TxXferCount;      /*!< UART Tx Transfer Counter           */
-
-  uint8_t                  *pRxBuffPtr;      /*!< Pointer to UART Rx transfer Buffer */
-
-  uint16_t                 RxXferSize;       /*!< UART Rx Transfer size              */
-
-  __IO uint16_t            RxXferCount;      /*!< UART Rx Transfer Counter           */
-
-  uint16_t                 Mask;             /*!< UART Rx RDR register mask          */
-
-  DMA_HandleTypeDef        *hdmatx;          /*!< UART Tx DMA Handle parameters      */
-
-  DMA_HandleTypeDef        *hdmarx;          /*!< UART Rx DMA Handle parameters      */
-
-  HAL_LockTypeDef           Lock;            /*!< Locking object                     */
-
-  __IO HAL_UART_StateTypeDef    gState;      /*!< UART state information related to global Handle management
-                                                  and also related to Tx operations.
-                                                  This parameter can be a value of @ref HAL_UART_StateTypeDef */
-
-  __IO HAL_UART_StateTypeDef    RxState;     /*!< UART state information related to Rx operations.
-                                                  This parameter can be a value of @ref HAL_UART_StateTypeDef */
-
-  __IO uint32_t             ErrorCode;   /*!< UART Error code                    */
-
-}UART_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup UART_Exported_Constants UART Exported Constants
-  * @{
-  */
-/** @defgroup UART_Error_Definition   UART Error Definition
-  * @{
-  */
-#define  HAL_UART_ERROR_NONE       ((uint32_t)0x00000000U)    /*!< No error            */
-#define  HAL_UART_ERROR_PE         ((uint32_t)0x00000001U)    /*!< Parity error        */
-#define  HAL_UART_ERROR_NE         ((uint32_t)0x00000002U)    /*!< Noise error         */
-#define  HAL_UART_ERROR_FE         ((uint32_t)0x00000004U)    /*!< frame error         */
-#define  HAL_UART_ERROR_ORE        ((uint32_t)0x00000008U)    /*!< Overrun error       */
-#define  HAL_UART_ERROR_DMA        ((uint32_t)0x00000010U)    /*!< DMA transfer error  */
-/**
-  * @}
-  */
-/** @defgroup UART_Stop_Bits   UART Number of Stop Bits
-  * @{
-  */
-#define UART_STOPBITS_1                     ((uint32_t)0x00000000U)
-#define UART_STOPBITS_2                     ((uint32_t)USART_CR2_STOP_1)
-/**
-  * @}
-  */
-
-/** @defgroup UART_Parity  UART Parity
-  * @{
-  */
-#define UART_PARITY_NONE                    ((uint32_t)0x00000000U)
-#define UART_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)
-#define UART_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
-/**
-  * @}
-  */
-
-/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
-  * @{
-  */
-#define UART_HWCONTROL_NONE                  ((uint32_t)0x00000000U)
-#define UART_HWCONTROL_RTS                   ((uint32_t)USART_CR3_RTSE)
-#define UART_HWCONTROL_CTS                   ((uint32_t)USART_CR3_CTSE)
-#define UART_HWCONTROL_RTS_CTS               ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
-/**
-  * @}
-  */
-
-/** @defgroup UART_Mode UART Transfer Mode
-  * @{
-  */
-#define UART_MODE_RX                        ((uint32_t)USART_CR1_RE)
-#define UART_MODE_TX                        ((uint32_t)USART_CR1_TE)
-#define UART_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
-/**
-  * @}
-  */
-
- /** @defgroup UART_State  UART State
-  * @{
-  */
-#define UART_STATE_DISABLE                  ((uint32_t)0x00000000U)
-#define UART_STATE_ENABLE                   ((uint32_t)USART_CR1_UE)
-/**
-  * @}
-  */
-
-/** @defgroup UART_Over_Sampling UART Over Sampling
-  * @{
-  */
-#define UART_OVERSAMPLING_16                ((uint32_t)0x00000000U)
-#define UART_OVERSAMPLING_8                 ((uint32_t)USART_CR1_OVER8)
-/**
-  * @}
-  */
-
-/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method
-  * @{
-  */
-#define UART_ONE_BIT_SAMPLE_DISABLE         ((uint32_t)0x00000000U)
-#define UART_ONE_BIT_SAMPLE_ENABLE          ((uint32_t)USART_CR3_ONEBIT)
-/**
-  * @}
-  */
-
-/** @defgroup UART_AutoBaud_Rate_Mode    UART Advanced Feature AutoBaud Rate Mode
-  * @{
-  */
-#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT    ((uint32_t)0x0000U)
-#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0)
-#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME   ((uint32_t)USART_CR2_ABRMODE_1)
-#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME   ((uint32_t)USART_CR2_ABRMODE)
-/**
-  * @}
-  */
-
-/** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut
-  * @{
-  */
-#define UART_RECEIVER_TIMEOUT_DISABLE       ((uint32_t)0x00000000U)
-#define UART_RECEIVER_TIMEOUT_ENABLE        ((uint32_t)USART_CR2_RTOEN)
-/**
-  * @}
-  */
-
-/** @defgroup UART_LIN    UART Local Interconnection Network mode
-  * @{
-  */
-#define UART_LIN_DISABLE                    ((uint32_t)0x00000000U)
-#define UART_LIN_ENABLE                     ((uint32_t)USART_CR2_LINEN)
-/**
-  * @}
-  */
-
-/** @defgroup UART_LIN_Break_Detection  UART LIN Break Detection
-  * @{
-  */
-#define UART_LINBREAKDETECTLENGTH_10B       ((uint32_t)0x00000000U)
-#define UART_LINBREAKDETECTLENGTH_11B       ((uint32_t)USART_CR2_LBDL)
-/**
-  * @}
-  */
-
-/** @defgroup UART_DMA_Tx    UART DMA Tx
-  * @{
-  */
-#define UART_DMA_TX_DISABLE                 ((uint32_t)0x00000000U)
-#define UART_DMA_TX_ENABLE                  ((uint32_t)USART_CR3_DMAT)
-/**
-  * @}
-  */
-
-/** @defgroup UART_DMA_Rx   UART DMA Rx
-  * @{
-  */
-#define UART_DMA_RX_DISABLE                 ((uint32_t)0x0000U)
-#define UART_DMA_RX_ENABLE                  ((uint32_t)USART_CR3_DMAR)
-/**
-  * @}
-  */
-
-/** @defgroup UART_Half_Duplex_Selection  UART Half Duplex Selection
-  * @{
-  */
-#define UART_HALF_DUPLEX_DISABLE            ((uint32_t)0x0000U)
-#define UART_HALF_DUPLEX_ENABLE             ((uint32_t)USART_CR3_HDSEL)
-/**
-  * @}
-  */
-
-/** @defgroup UART_WakeUp_Methods   UART WakeUp Methods
-  * @{
-  */
-#define UART_WAKEUPMETHOD_IDLELINE          ((uint32_t)0x00000000U)
-#define UART_WAKEUPMETHOD_ADDRESSMARK       ((uint32_t)USART_CR1_WAKE)
-/**
-  * @}
-  */
-
-/** @defgroup UART_Request_Parameters UART Request Parameters
-  * @{
-  */
-#define UART_AUTOBAUD_REQUEST               ((uint32_t)USART_RQR_ABRRQ)        /*!< Auto-Baud Rate Request */
-#define UART_SENDBREAK_REQUEST              ((uint32_t)USART_RQR_SBKRQ)        /*!< Send Break Request */
-#define UART_MUTE_MODE_REQUEST              ((uint32_t)USART_RQR_MMRQ)         /*!< Mute Mode Request */
-#define UART_RXDATA_FLUSH_REQUEST           ((uint32_t)USART_RQR_RXFRQ)        /*!< Receive Data flush Request */
-#define UART_TXDATA_FLUSH_REQUEST           ((uint32_t)USART_RQR_TXFRQ)        /*!< Transmit data flush Request */
-/**
-  * @}
-  */
-
-/** @defgroup UART_Advanced_Features_Initialization_Type  UART Advanced Feature Initialization Type
-  * @{
-  */
-#define UART_ADVFEATURE_NO_INIT                 ((uint32_t)0x00000000U)
-#define UART_ADVFEATURE_TXINVERT_INIT           ((uint32_t)0x00000001U)
-#define UART_ADVFEATURE_RXINVERT_INIT           ((uint32_t)0x00000002U)
-#define UART_ADVFEATURE_DATAINVERT_INIT         ((uint32_t)0x00000004U)
-#define UART_ADVFEATURE_SWAP_INIT               ((uint32_t)0x00000008U)
-#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT   ((uint32_t)0x00000010U)
-#define UART_ADVFEATURE_DMADISABLEONERROR_INIT  ((uint32_t)0x00000020U)
-#define UART_ADVFEATURE_AUTOBAUDRATE_INIT       ((uint32_t)0x00000040U)
-#define UART_ADVFEATURE_MSBFIRST_INIT           ((uint32_t)0x00000080U)
-/**
-  * @}
-  */
-
-/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion
-  * @{
-  */
-#define UART_ADVFEATURE_TXINV_DISABLE       ((uint32_t)0x00000000U)
-#define UART_ADVFEATURE_TXINV_ENABLE        ((uint32_t)USART_CR2_TXINV)
-/**
-  * @}
-  */
-
-/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion
-  * @{
-  */
-#define UART_ADVFEATURE_RXINV_DISABLE       ((uint32_t)0x00000000U)
-#define UART_ADVFEATURE_RXINV_ENABLE        ((uint32_t)USART_CR2_RXINV)
-/**
-  * @}
-  */
-
-/** @defgroup UART_Data_Inv  UART Advanced Feature Binary Data Inversion
-  * @{
-  */
-#define UART_ADVFEATURE_DATAINV_DISABLE     ((uint32_t)0x00000000U)
-#define UART_ADVFEATURE_DATAINV_ENABLE      ((uint32_t)USART_CR2_DATAINV)
-/**
-  * @}
-  */
-
-/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap
-  * @{
-  */
-#define UART_ADVFEATURE_SWAP_DISABLE        ((uint32_t)0x00000000U)
-#define UART_ADVFEATURE_SWAP_ENABLE         ((uint32_t)USART_CR2_SWAP)
-/**
-  * @}
-  */
-
-/** @defgroup UART_Overrun_Disable  UART Advanced Feature Overrun Disable
-  * @{
-  */
-#define UART_ADVFEATURE_OVERRUN_ENABLE      ((uint32_t)0x00000000U)
-#define UART_ADVFEATURE_OVERRUN_DISABLE     ((uint32_t)USART_CR3_OVRDIS)
-/**
-  * @}
-  */
-
-/** @defgroup UART_AutoBaudRate_Enable  UART Advanced Feature Auto BaudRate Enable
-  * @{
-  */
-#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE   ((uint32_t)0x00000000U)
-#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE    ((uint32_t)USART_CR2_ABREN)
-/**
-  * @}
-  */
-
-/** @defgroup UART_DMA_Disable_on_Rx_Error   UART Advanced Feature DMA Disable On Rx Error
-  * @{
-  */
-#define UART_ADVFEATURE_DMA_ENABLEONRXERROR    ((uint32_t)0x00000000U)
-#define UART_ADVFEATURE_DMA_DISABLEONRXERROR   ((uint32_t)USART_CR3_DDRE)
-/**
-  * @}
-  */
-
-/** @defgroup UART_MSB_First   UART Advanced Feature MSB First
-  * @{
-  */
-#define UART_ADVFEATURE_MSBFIRST_DISABLE    ((uint32_t)0x00000000U)
-#define UART_ADVFEATURE_MSBFIRST_ENABLE     ((uint32_t)USART_CR2_MSBFIRST)
-/**
-  * @}
-  */
-
-/** @defgroup UART_Mute_Mode   UART Advanced Feature Mute Mode Enable
-  * @{
-  */
-#define UART_ADVFEATURE_MUTEMODE_DISABLE    ((uint32_t)0x00000000U)
-#define UART_ADVFEATURE_MUTEMODE_ENABLE     ((uint32_t)USART_CR1_MME)
-/**
-  * @}
-  */
-
-/** @defgroup UART_CR2_ADDRESS_LSB_POS    UART Address-matching LSB Position In CR2 Register
-  * @{
-  */
-#define UART_CR2_ADDRESS_LSB_POS            ((uint32_t) 24U)
-/**
-  * @}
-  */
-
-/** @defgroup UART_DriverEnable_Polarity      UART DriverEnable Polarity
-  * @{
-  */
-#define UART_DE_POLARITY_HIGH               ((uint32_t)0x00000000U)
-#define UART_DE_POLARITY_LOW                ((uint32_t)USART_CR3_DEP)
-/**
-  * @}
-  */
-
-/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS    UART Driver Enable Assertion Time LSB Position In CR1 Register
-  * @{
-  */
-#define UART_CR1_DEAT_ADDRESS_LSB_POS       ((uint32_t) 21U)
-/**
-  * @}
-  */
-
-/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS    UART Driver Enable DeAssertion Time LSB Position In CR1 Register
-  * @{
-  */
-#define UART_CR1_DEDT_ADDRESS_LSB_POS       ((uint32_t) 16U)
-/**
-  * @}
-  */
-
-/** @defgroup UART_Interruption_Mask    UART Interruptions Flag Mask
-  * @{
-  */
-#define UART_IT_MASK                        ((uint32_t)0x001FU)
-/**
-  * @}
-  */
-
-/** @defgroup UART_TimeOut_Value    UART polling-based communications time-out value
-  * @{
-  */
-#define HAL_UART_TIMEOUT_VALUE              0x1FFFFFFU
-/**
-  * @}
-  */
-
-/** @defgroup UART_Flags     UART Status Flags
-  *        Elements values convention: 0xXXXX
-  *           - 0xXXXX  : Flag mask in the ISR register
-  * @{
-  */
-#define UART_FLAG_TEACK                     ((uint32_t)0x00200000U)
-#define UART_FLAG_SBKF                      ((uint32_t)0x00040000U)
-#define UART_FLAG_CMF                       ((uint32_t)0x00020000U)
-#define UART_FLAG_BUSY                      ((uint32_t)0x00010000U)
-#define UART_FLAG_ABRF                      ((uint32_t)0x00008000U)
-#define UART_FLAG_ABRE                      ((uint32_t)0x00004000U)
-#define UART_FLAG_EOBF                      ((uint32_t)0x00001000U)
-#define UART_FLAG_RTOF                      ((uint32_t)0x00000800U)
-#define UART_FLAG_CTS                       ((uint32_t)0x00000400U)
-#define UART_FLAG_CTSIF                     ((uint32_t)0x00000200U)
-#define UART_FLAG_LBDF                      ((uint32_t)0x00000100U)
-#define UART_FLAG_TXE                       ((uint32_t)0x00000080U)
-#define UART_FLAG_TC                        ((uint32_t)0x00000040U)
-#define UART_FLAG_RXNE                      ((uint32_t)0x00000020U)
-#define UART_FLAG_IDLE                      ((uint32_t)0x00000010U)
-#define UART_FLAG_ORE                       ((uint32_t)0x00000008U)
-#define UART_FLAG_NE                        ((uint32_t)0x00000004U)
-#define UART_FLAG_FE                        ((uint32_t)0x00000002U)
-#define UART_FLAG_PE                        ((uint32_t)0x00000001U)
-/**
-  * @}
-  */
-
-/** @defgroup UART_Interrupt_definition   UART Interrupts Definition
-  *        Elements values convention: 0000ZZZZ0XXYYYYYb
-  *           - YYYYY  : Interrupt source position in the XX register (5bits)
-  *           - XX  : Interrupt source register (2bits)
-  *                 - 01: CR1 register
-  *                 - 10: CR2 register
-  *                 - 11: CR3 register
-  *           - ZZZZ  : Flag position in the ISR register(4bits)
-  * @{
-  */
-#define UART_IT_PE                          ((uint32_t)0x0028U)
-#define UART_IT_TXE                         ((uint32_t)0x0727U)
-#define UART_IT_TC                          ((uint32_t)0x0626U)
-#define UART_IT_RXNE                        ((uint32_t)0x0525U)
-#define UART_IT_IDLE                        ((uint32_t)0x0424U)
-#define UART_IT_LBD                         ((uint32_t)0x0846U)
-#define UART_IT_CTS                         ((uint32_t)0x096AU)
-#define UART_IT_CM                          ((uint32_t)0x112EU)
-
-/**       Elements values convention: 000000000XXYYYYYb
-  *           - YYYYY  : Interrupt source position in the XX register (5bits)
-  *           - XX  : Interrupt source register (2bits)
-  *                 - 01: CR1 register
-  *                 - 10: CR2 register
-  *                 - 11: CR3 register
-  */
-#define UART_IT_ERR                         ((uint32_t)0x0060U)
-
-/**       Elements values convention: 0000ZZZZ00000000b
-  *           - ZZZZ  : Flag position in the ISR register(4bits)
-  */
-#define UART_IT_ORE                         ((uint32_t)0x0300U)
-#define UART_IT_NE                          ((uint32_t)0x0200U)
-#define UART_IT_FE                          ((uint32_t)0x0100U)
-/**
-  * @}
-  */
-
-/** @defgroup UART_IT_CLEAR_Flags  UART Interruption Clear Flags
-  * @{
-  */
-#define UART_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag */
-#define UART_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag */
-#define UART_CLEAR_NEF                       USART_ICR_NCF             /*!< Noise detected Clear Flag */
-#define UART_CLEAR_OREF                      USART_ICR_ORECF           /*!< OverRun Error Clear Flag */
-#define UART_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag */
-#define UART_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag */
-#define UART_CLEAR_LBDF                      USART_ICR_LBDCF           /*!< LIN Break Detection Clear Flag */
-#define UART_CLEAR_CTSF                      USART_ICR_CTSCF           /*!< CTS Interrupt Clear Flag */
-#define UART_CLEAR_RTOF                      USART_ICR_RTOCF           /*!< Receiver Time Out Clear Flag */
-#define UART_CLEAR_EOBF                      USART_ICR_EOBCF           /*!< End Of Block Clear Flag */
-#define UART_CLEAR_CMF                       USART_ICR_CMCF            /*!< Character Match Clear Flag */
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup UART_Exported_Macros UART Exported Macros
-  * @{
-  */
-
-/** @brief Reset UART handle state
-  * @param  __HANDLE__: UART handle.
-  * @retval None
-  */
-#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
-                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
-                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
-                                                     } while(0)
-
-/** @brief  Flush the UART Data registers
-  * @param  __HANDLE__: specifies the UART Handle.
-  */
-#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__)  \
-  do{                \
-      SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
-      SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
-    }  while(0)
-
-/** @brief  Clears the specified UART ISR flag, in setting the proper ICR register flag.
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @param  __FLAG__: specifies the interrupt clear register flag that needs to be set
-  *                       to clear the corresponding interrupt
-  *          This parameter can be one of the following values:
-  *            @arg UART_CLEAR_PEF: Parity Error Clear Flag
-  *            @arg UART_CLEAR_FEF: Framing Error Clear Flag
-  *            @arg UART_CLEAR_NEF: Noise detected Clear Flag
-  *            @arg UART_CLEAR_OREF: OverRun Error Clear Flag
-  *            @arg UART_CLEAR_IDLEF: IDLE line detected Clear Flag
-  *            @arg UART_CLEAR_TCF: Transmission Complete Clear Flag
-  *            @arg UART_CLEAR_LBDF: LIN Break Detection Clear Flag
-  *            @arg UART_CLEAR_CTSF: CTS Interrupt Clear Flag
-  *            @arg UART_CLEAR_RTOF: Receiver Time Out Clear Flag
-  *            @arg UART_CLEAR_EOBF: End Of Block Clear Flag
-  *            @arg UART_CLEAR_CMF: Character Match Clear Flag
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_IT(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__FLAG__))
-
-/** @brief  Clear the UART PE pending flag.
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__)   __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_PEF)
-
-/** @brief  Clear the UART FE pending flag.
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__)   __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_FEF)
-
-/** @brief  Clear the UART NE pending flag.
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__)  __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_NEF)
-
-/** @brief  Clear the UART ORE pending flag.
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__)   __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_OREF)
-
-/** @brief  Clear the UART IDLE pending flag.
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_IDLEF)
-
-/** @brief  Checks whether the specified UART flag is set or not.
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @param  __FLAG__: specifies the flag to check.
-  *        This parameter can be one of the following values:
-  *            @arg UART_FLAG_REACK: Receive enable acknowledge flag
-  *            @arg UART_FLAG_TEACK: Transmit enable acknowledge flag
-  *            @arg UART_FLAG_WUF:   Wake up from stop mode flag
-  *            @arg UART_FLAG_RWU:   Receiver wake up flag (is the UART in mute mode)
-  *            @arg UART_FLAG_SBKF:  Send Break flag
-  *            @arg UART_FLAG_CMF:   Character match flag
-  *            @arg UART_FLAG_BUSY:  Busy flag
-  *            @arg UART_FLAG_ABRF:  Auto Baud rate detection flag
-  *            @arg UART_FLAG_ABRE:  Auto Baud rate detection error flag
-  *            @arg UART_FLAG_EOBF:  End of block flag
-  *            @arg UART_FLAG_RTOF:  Receiver timeout flag
-  *            @arg UART_FLAG_CTS:   CTS Change flag (not available for UART4 and UART5)
-  *            @arg UART_FLAG_LBD:   LIN Break detection flag
-  *            @arg UART_FLAG_TXE:   Transmit data register empty flag
-  *            @arg UART_FLAG_TC:    Transmission Complete flag
-  *            @arg UART_FLAG_RXNE:  Receive data register not empty flag
-  *            @arg UART_FLAG_IDLE:  Idle Line detection flag
-  *            @arg UART_FLAG_ORE:   OverRun Error flag
-  *            @arg UART_FLAG_NE:    Noise Error flag
-  *            @arg UART_FLAG_FE:    Framing Error flag
-  *            @arg UART_FLAG_PE:    Parity Error flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Enables the specified UART interrupt.
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @param  __INTERRUPT__: specifies the UART interrupt source to enable.
-  *          This parameter can be one of the following values:
-  *            @arg UART_IT_WUF:  Wakeup from stop mode interrupt
-  *            @arg UART_IT_CM:   Character match interrupt
-  *            @arg UART_IT_CTS:  CTS change interrupt
-  *            @arg UART_IT_LBD:  LIN Break detection interrupt
-  *            @arg UART_IT_TXE:  Transmit Data Register empty interrupt
-  *            @arg UART_IT_TC:   Transmission complete interrupt
-  *            @arg UART_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg UART_IT_IDLE: Idle line detection interrupt
-  *            @arg UART_IT_PE:   Parity Error interrupt
-  *            @arg UART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
-  * @retval None
-  */
-#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
-                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
-                                                           ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))))
-
-
-/** @brief  Disables the specified UART interrupt.
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @param  __INTERRUPT__: specifies the UART interrupt source to disable.
-  *          This parameter can be one of the following values:
-  *            @arg UART_IT_CM:   Character match interrupt
-  *            @arg UART_IT_CTS:  CTS change interrupt
-  *            @arg UART_IT_LBD:  LIN Break detection interrupt
-  *            @arg UART_IT_TXE:  Transmit Data Register empty interrupt
-  *            @arg UART_IT_TC:   Transmission complete interrupt
-  *            @arg UART_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg UART_IT_IDLE: Idle line detection interrupt
-  *            @arg UART_IT_PE:   Parity Error interrupt
-  *            @arg UART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
-  * @retval None
-  */
-#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
-                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
-                                                           ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))
-
-/** @brief  Checks whether the specified UART interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @param  __IT__: specifies the UART interrupt to check.
-  *          This parameter can be one of the following values:
-  *            @arg UART_IT_CM:   Character match interrupt
-  *            @arg UART_IT_CTS:  CTS change interrupt (not available for UART4 and UART5)
-  *            @arg UART_IT_LBD:  LIN Break detection interrupt
-  *            @arg UART_IT_TXE:  Transmit Data Register empty interrupt
-  *            @arg UART_IT_TC:   Transmission complete interrupt
-  *            @arg UART_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg UART_IT_IDLE: Idle line detection interrupt
-  *            @arg UART_IT_ORE:  OverRun Error interrupt
-  *            @arg UART_IT_NE:   Noise Error interrupt
-  *            @arg UART_IT_FE:   Framing Error interrupt
-  *            @arg UART_IT_PE:   Parity Error interrupt
-  * @retval The new state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
-
-/** @brief  Checks whether the specified UART interrupt source is enabled.
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @param  __IT__: specifies the UART interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
-  *            @arg UART_IT_LBD: LIN Break detection interrupt
-  *            @arg UART_IT_TXE: Transmit Data Register empty interrupt
-  *            @arg UART_IT_TC:  Transmission complete interrupt
-  *            @arg UART_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg UART_IT_IDLE: Idle line detection interrupt
-  *            @arg UART_IT_ORE: OverRun Error interrupt
-  *            @arg UART_IT_NE: Noise Error interrupt
-  *            @arg UART_IT_FE: Framing Error interrupt
-  *            @arg UART_IT_PE: Parity Error interrupt
-  * @retval The new state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \
-                                                       (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & UART_IT_MASK)))
-
-/** @brief  Set a specific UART request flag.
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @param  __REQ__: specifies the request flag to set
-  *          This parameter can be one of the following values:
-  *            @arg UART_AUTOBAUD_REQUEST: Auto-Baud Rate Request
-  *            @arg UART_SENDBREAK_REQUEST: Send Break Request
-  *            @arg UART_MUTE_MODE_REQUEST: Mute Mode Request
-  *            @arg UART_RXDATA_FLUSH_REQUEST: Receive Data flush Request
-  *            @arg UART_TXDATA_FLUSH_REQUEST: Transmit data flush Request
-  * @retval None
-  */
-#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__))
-
-/** @brief  Enables the UART one bit sample method
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @retval None
-  */
-#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
-
-/** @brief  Disables the UART one bit sample method
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @retval None
-  */
-#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
-
-/** @brief  Enable UART
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @retval None
-  */
-#define __HAL_UART_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
-
-/** @brief  Disable UART
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @retval None
-  */
-#define __HAL_UART_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
-
-/** @brief  Enable CTS flow control
-  *         This macro allows to enable CTS hardware flow control for a given UART instance,
-  *         without need to call HAL_UART_Init() function.
-  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
-  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
-  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
-  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
-  *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
-  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         The Handle Instance can be USART1, USART2 or LPUART.
-  * @retval None
-  */
-#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)        \
-  do{                                                      \
-    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \
-    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;        \
-  } while(0)
-
-/** @brief  Disable CTS flow control
-  *         This macro allows to disable CTS hardware flow control for a given UART instance,
-  *         without need to call HAL_UART_Init() function.
-  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
-  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
-  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
-  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
-  *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
-  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         The Handle Instance can be USART1, USART2 or LPUART.
-  * @retval None
-  */
-#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)        \
-  do{                                                       \
-    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
-    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);      \
-  } while(0)
-
-/** @brief  Enable RTS flow control
-  *         This macro allows to enable RTS hardware flow control for a given UART instance,
-  *         without need to call HAL_UART_Init() function.
-  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
-  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
-  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
-  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
-  *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
-  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         The Handle Instance can be USART1, USART2 or LPUART.
-  * @retval None
-  */
-#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)       \
-  do{                                                     \
-    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
-    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;       \
-  } while(0)
-
-/** @brief  Disable RTS flow control
-  *         This macro allows to disable RTS hardware flow control for a given UART instance,
-  *         without need to call HAL_UART_Init() function.
-  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
-  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
-  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
-  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
-  *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
-  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         The Handle Instance can be USART1, USART2 or LPUART.
-  * @retval None
-  */
-#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)       \
-  do{                                                      \
-    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
-    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);     \
-  } while(0)
-
-/**
-  * @}
-  */
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup UART_Private_Macros   UART Private Macros
-  * @{
-  */
-/** @brief  BRR division operation to set BRR register with LPUART
-  * @param  _PCLK_: LPUART clock
-  * @param  _BAUD_: Baud rate set by the user
-  * @retval Division result
-  */
-#define UART_DIV_LPUART(_PCLK_, _BAUD_)                ((((_PCLK_)*256)+((_BAUD_)/2))/((_BAUD_)))
-
-/** @brief  BRR division operation to set BRR register in 8-bit oversampling mode
-  * @param  _PCLK_: UART clock
-  * @param  _BAUD_: Baud rate set by the user
-  * @retval Division result
-  */
-#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_)             ((((_PCLK_)*2)+((_BAUD_)/2))/((_BAUD_)))
-
-/** @brief  BRR division operation to set BRR register in 16-bit oversampling mode
-  * @param  _PCLK_: UART clock
-  * @param  _BAUD_: Baud rate set by the user
-  * @retval Division result
-  */
-#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_)             ((((_PCLK_))+((_BAUD_)/2))/((_BAUD_)))
-
-/** @brief  Check UART Baud rate
-  * @param  BAUDRATE: Baudrate specified by the user
-  *         The maximum Baud Rate is derived from the maximum clock on F7 (i.e. 216 MHz)
-  *         divided by the smallest oversampling used on the USART (i.e. 8)
-  * @retval Test result (TRUE or FALSE).
-  */
-#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 9000001)
-
-/** @brief  Check UART assertion time
-  * @param  TIME: 5-bit value assertion time
-  * @retval Test result (TRUE or FALSE).
-  */
-#define IS_UART_ASSERTIONTIME(TIME)    ((TIME) <= 0x1F)
-
-/** @brief  Check UART deassertion time
-  * @param  TIME: 5-bit value deassertion time
-  * @retval Test result (TRUE or FALSE).
-  */
-#define IS_UART_DEASSERTIONTIME(TIME) ((TIME) <= 0x1F)
-
-#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \
-                                    ((STOPBITS) == UART_STOPBITS_2))
-
-#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \
-                                ((PARITY) == UART_PARITY_EVEN) || \
-                                ((PARITY) == UART_PARITY_ODD))
-
-#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
-                              (((CONTROL) == UART_HWCONTROL_NONE) || \
-                               ((CONTROL) == UART_HWCONTROL_RTS) || \
-                               ((CONTROL) == UART_HWCONTROL_CTS) || \
-                               ((CONTROL) == UART_HWCONTROL_RTS_CTS))
-
-#define IS_UART_MODE(MODE) ((((MODE) & (~((uint32_t)(UART_MODE_TX_RX)))) == (uint32_t)0x00) && ((MODE) != (uint32_t)0x00))
-
-#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \
-                              ((STATE) == UART_STATE_ENABLE))
-
-#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \
-                                        ((SAMPLING) == UART_OVERSAMPLING_8))
-
-#define IS_UART_ONE_BIT_SAMPLE(ONEBIT) (((ONEBIT) == UART_ONE_BIT_SAMPLE_DISABLE) || \
-                                        ((ONEBIT) == UART_ONE_BIT_SAMPLE_ENABLE))
-
-#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(MODE)  (((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \
-                                                    ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
-                                                    ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \
-                                                    ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
-
-#define IS_UART_RECEIVER_TIMEOUT(TIMEOUT) (((TIMEOUT) == UART_RECEIVER_TIMEOUT_DISABLE) || \
-                                           ((TIMEOUT) == UART_RECEIVER_TIMEOUT_ENABLE))
-
-#define IS_UART_LIN(LIN)            (((LIN) == UART_LIN_DISABLE) || \
-                                     ((LIN) == UART_LIN_ENABLE))
-
-#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \
-                                      ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK))
-
-#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \
-                                                 ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))
-
-#define IS_UART_DMA_TX(DMATX)         (((DMATX) == UART_DMA_TX_DISABLE) || \
-                                       ((DMATX) == UART_DMA_TX_ENABLE))
-
-#define IS_UART_DMA_RX(DMARX)         (((DMARX) == UART_DMA_RX_DISABLE) || \
-                                       ((DMARX) == UART_DMA_RX_ENABLE))
-
-#define IS_UART_HALF_DUPLEX(HDSEL)         (((HDSEL) == UART_HALF_DUPLEX_DISABLE) || \
-                                            ((HDSEL) == UART_HALF_DUPLEX_ENABLE))
-
-#define IS_UART_REQUEST_PARAMETER(PARAM) (((PARAM) == UART_AUTOBAUD_REQUEST) || \
-                                          ((PARAM) == UART_SENDBREAK_REQUEST) || \
-                                          ((PARAM) == UART_MUTE_MODE_REQUEST) || \
-                                          ((PARAM) == UART_RXDATA_FLUSH_REQUEST) || \
-                                          ((PARAM) == UART_TXDATA_FLUSH_REQUEST))
-
-#define IS_UART_ADVFEATURE_INIT(INIT)           ((INIT) <= (UART_ADVFEATURE_NO_INIT | \
-                                                            UART_ADVFEATURE_TXINVERT_INIT | \
-                                                            UART_ADVFEATURE_RXINVERT_INIT | \
-                                                            UART_ADVFEATURE_DATAINVERT_INIT | \
-                                                            UART_ADVFEATURE_SWAP_INIT | \
-                                                            UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \
-                                                            UART_ADVFEATURE_DMADISABLEONERROR_INIT   | \
-                                                            UART_ADVFEATURE_AUTOBAUDRATE_INIT | \
-                                                            UART_ADVFEATURE_MSBFIRST_INIT))
-
-#define IS_UART_ADVFEATURE_TXINV(TXINV) (((TXINV) == UART_ADVFEATURE_TXINV_DISABLE) || \
-                                         ((TXINV) == UART_ADVFEATURE_TXINV_ENABLE))
-
-#define IS_UART_ADVFEATURE_RXINV(RXINV) (((RXINV) == UART_ADVFEATURE_RXINV_DISABLE) || \
-                                         ((RXINV) == UART_ADVFEATURE_RXINV_ENABLE))
-
-#define IS_UART_ADVFEATURE_DATAINV(DATAINV) (((DATAINV) == UART_ADVFEATURE_DATAINV_DISABLE) || \
-                                             ((DATAINV) == UART_ADVFEATURE_DATAINV_ENABLE))
-
-#define IS_UART_ADVFEATURE_SWAP(SWAP) (((SWAP) == UART_ADVFEATURE_SWAP_DISABLE) || \
-                                       ((SWAP) == UART_ADVFEATURE_SWAP_ENABLE))
-
-#define IS_UART_OVERRUN(OVERRUN)         (((OVERRUN) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
-                                          ((OVERRUN) == UART_ADVFEATURE_OVERRUN_DISABLE))
-
-#define IS_UART_ADVFEATURE_AUTOBAUDRATE(AUTOBAUDRATE)  (((AUTOBAUDRATE) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
-                                                        ((AUTOBAUDRATE) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
-
-#define IS_UART_ADVFEATURE_DMAONRXERROR(DMA)      (((DMA) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
-                                                   ((DMA) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))
-
-#define IS_UART_ADVFEATURE_MSBFIRST(MSBFIRST) (((MSBFIRST) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
-                                               ((MSBFIRST) == UART_ADVFEATURE_MSBFIRST_ENABLE))
-
-#define IS_UART_MUTE_MODE(MUTE)           (((MUTE) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
-                                           ((MUTE) == UART_ADVFEATURE_MUTEMODE_ENABLE))
-
-#define IS_UART_DE_POLARITY(POLARITY)    (((POLARITY) == UART_DE_POLARITY_HIGH) || \
-                                          ((POLARITY) == UART_DE_POLARITY_LOW))
-
-/**
-  * @}
-  */
-/* Include UART HAL Extension module */
-#include "stm32f7xx_hal_uart_ex.h"
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup UART_Exported_Functions UART Exported Functions
-  * @{
-  */
-
-/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-
-/* Initialization and de-initialization functions  ****************************/
-HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
-HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
-HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime);
-HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);
-void HAL_UART_MspInit(UART_HandleTypeDef *huart);
-void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
-
-/**
-  * @}
-  */
-
-/** @addtogroup UART_Exported_Functions_Group2 IO operation functions
-  * @{
-  */
-
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
-
-void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
-void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
-
-/**
-  * @}
-  */
-
-/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions
-  * @{
-  */
-
-/* Peripheral Control functions  ************************************************/
-HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
-HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);
-void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
-
-/**
-  * @}
-  */
-
-/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions
-  * @{
-  */
-
-/* Peripheral State and Errors functions  **************************************************/
-HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
-uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions -----------------------------------------------------------*/
-/** @addtogroup UART_Private_Functions UART Private Functions
-  * @{
-  */
-
-HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
-void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F7xx_HAL_UART_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_uart_ex.h b/stmhal/hal/f7/inc/stm32f7xx_hal_uart_ex.h
deleted file mode 100644
index 3d83232f44..0000000000
--- a/stmhal/hal/f7/inc/stm32f7xx_hal_uart_ex.h
+++ /dev/null
@@ -1,365 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_uart_ex.h
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   Header file of UART HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_UART_EX_H
-#define __STM32F7xx_HAL_UART_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal_def.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup UARTEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
-  * @{
-  */
-
-/** @defgroup UARTEx_Word_Length UARTEx Word Length
-  * @{
-  */
-#define UART_WORDLENGTH_7B                  ((uint32_t)USART_CR1_M_1)
-#define UART_WORDLENGTH_8B                  ((uint32_t)0x0000U)
-#define UART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M_0)
-#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
-                                         ((__LENGTH__) == UART_WORDLENGTH_8B) || \
-                                         ((__LENGTH__) == UART_WORDLENGTH_9B))
-#define IS_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B))
-/**
-  * @}
-  */
-
-
-/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length
-  * @{
-  */
-#define UART_ADDRESS_DETECT_4B                ((uint32_t)0x00000000U)
-#define UART_ADDRESS_DETECT_7B                ((uint32_t)USART_CR2_ADDM7)
-#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
-                                                   ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup UARTEx_Exported_Macros UARTEx Exported Macros
-  * @{
-  */
-
-/** @brief  Reports the UART clock source.
-  * @param  __HANDLE__: specifies the UART Handle
-  * @param  __CLOCKSOURCE__: output variable
-  * @retval UART clocking source, written in __CLOCKSOURCE__.
-  */
-#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
-  do {                                                        \
-    if((__HANDLE__)->Instance == USART1)                      \
-    {                                                         \
-       switch(__HAL_RCC_GET_USART1_SOURCE())                  \
-       {                                                      \
-        case RCC_USART1CLKSOURCE_PCLK2:                       \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \
-          break;                                              \
-        case RCC_USART1CLKSOURCE_HSI:                         \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
-          break;                                              \
-        case RCC_USART1CLKSOURCE_SYSCLK:                      \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
-          break;                                              \
-        case RCC_USART1CLKSOURCE_LSE:                         \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
-          break;                                              \
-        default:                                              \
-          break;                                              \
-       }                                                      \
-    }                                                         \
-    else if((__HANDLE__)->Instance == USART2)                 \
-    {                                                         \
-       switch(__HAL_RCC_GET_USART2_SOURCE())                  \
-       {                                                      \
-        case RCC_USART2CLKSOURCE_PCLK1:                       \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
-          break;                                              \
-        case RCC_USART2CLKSOURCE_HSI:                         \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
-          break;                                              \
-        case RCC_USART2CLKSOURCE_SYSCLK:                      \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
-          break;                                              \
-        case RCC_USART2CLKSOURCE_LSE:                         \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
-          break;                                              \
-        default:                                              \
-          break;                                              \
-       }                                                      \
-    }                                                         \
-    else if((__HANDLE__)->Instance == USART3)                 \
-    {                                                         \
-       switch(__HAL_RCC_GET_USART3_SOURCE())                  \
-       {                                                      \
-        case RCC_USART3CLKSOURCE_PCLK1:                       \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
-          break;                                              \
-        case RCC_USART3CLKSOURCE_HSI:                         \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
-          break;                                              \
-        case RCC_USART3CLKSOURCE_SYSCLK:                      \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
-          break;                                              \
-        case RCC_USART3CLKSOURCE_LSE:                         \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
-          break;                                              \
-        default:                                              \
-          break;                                              \
-       }                                                      \
-    }                                                         \
-    else if((__HANDLE__)->Instance == UART4)                  \
-    {                                                         \
-       switch(__HAL_RCC_GET_UART4_SOURCE())                   \
-       {                                                      \
-        case RCC_UART4CLKSOURCE_PCLK1:                        \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
-          break;                                              \
-        case RCC_UART4CLKSOURCE_HSI:                          \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
-          break;                                              \
-        case RCC_UART4CLKSOURCE_SYSCLK:                       \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
-          break;                                              \
-        case RCC_UART4CLKSOURCE_LSE:                          \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
-          break;                                              \
-        default:                                              \
-          break;                                              \
-       }                                                      \
-    }                                                         \
-    else if ((__HANDLE__)->Instance == UART5)                 \
-    {                                                         \
-       switch(__HAL_RCC_GET_UART5_SOURCE())                   \
-       {                                                      \
-        case RCC_UART5CLKSOURCE_PCLK1:                        \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
-          break;                                              \
-        case RCC_UART5CLKSOURCE_HSI:                          \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
-          break;                                              \
-        case RCC_UART5CLKSOURCE_SYSCLK:                       \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
-          break;                                              \
-        case RCC_UART5CLKSOURCE_LSE:                          \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
-          break;                                              \
-        default:                                              \
-          break;                                              \
-       }                                                      \
-    }                                                         \
-    else if((__HANDLE__)->Instance == USART6)                 \
-    {                                                         \
-       switch(__HAL_RCC_GET_USART6_SOURCE())                  \
-       {                                                      \
-        case RCC_USART6CLKSOURCE_PCLK2:                       \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \
-          break;                                              \
-        case RCC_USART6CLKSOURCE_HSI:                         \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
-          break;                                              \
-        case RCC_USART6CLKSOURCE_SYSCLK:                      \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
-          break;                                              \
-        case RCC_USART6CLKSOURCE_LSE:                         \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
-          break;                                              \
-        default:                                              \
-          break;                                              \
-       }                                                      \
-    }                                                         \
-    else if ((__HANDLE__)->Instance == UART7)                 \
-    {                                                         \
-       switch(__HAL_RCC_GET_UART7_SOURCE())                   \
-       {                                                      \
-        case RCC_UART7CLKSOURCE_PCLK1:                        \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
-          break;                                              \
-        case RCC_UART7CLKSOURCE_HSI:                          \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
-          break;                                              \
-        case RCC_UART7CLKSOURCE_SYSCLK:                       \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
-          break;                                              \
-        case RCC_UART7CLKSOURCE_LSE:                          \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
-          break;                                              \
-        default:                                              \
-          break;                                              \
-       }                                                      \
-    } 																												\
-    else if ((__HANDLE__)->Instance == UART8)                 \
-    {                                                         \
-       switch(__HAL_RCC_GET_UART8_SOURCE())                   \
-       {                                                      \
-        case RCC_UART8CLKSOURCE_PCLK1:                        \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
-          break;                                              \
-        case RCC_UART8CLKSOURCE_HSI:                          \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
-          break;                                              \
-        case RCC_UART8CLKSOURCE_SYSCLK:                       \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
-          break;                                              \
-        case RCC_UART8CLKSOURCE_LSE:                          \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
-          break;                                              \
-        default:                                              \
-          break;                                              \
-       }                                                      \
-    } 																												\
-  } while(0)
-
-/** @brief  Reports the UART mask to apply to retrieve the received data
-  *         according to the word length and to the parity bits activation.
-  *         If PCE = 1, the parity bit is not included in the data extracted
-  *         by the reception API().
-  *         This masking operation is not carried out in the case of
-  *         DMA transfers.
-  * @param  __HANDLE__: specifies the UART Handle
-  * @retval mask to apply to UART RDR register value.
-  */
-#define UART_MASK_COMPUTATION(__HANDLE__)                       \
-  do {                                                                \
-  if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B)            \
-  {                                                                   \
-     if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)               \
-     {                                                                \
-        (__HANDLE__)->Mask = 0x01FF ;                                 \
-     }                                                                \
-     else                                                             \
-     {                                                                \
-        (__HANDLE__)->Mask = 0x00FF ;                                 \
-     }                                                                \
-  }                                                                   \
-  else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B)       \
-  {                                                                   \
-     if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)               \
-     {                                                                \
-        (__HANDLE__)->Mask = 0x00FF ;                                 \
-     }                                                                \
-     else                                                             \
-     {                                                                \
-        (__HANDLE__)->Mask = 0x007F ;                                 \
-     }                                                                \
-  }                                                                   \
-  else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B)       \
-  {                                                                   \
-     if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)               \
-     {                                                                \
-        (__HANDLE__)->Mask = 0x007F ;                                 \
-     }                                                                \
-     else                                                             \
-     {                                                                \
-        (__HANDLE__)->Mask = 0x003F ;                                 \
-     }                                                                \
-  }                                                                   \
-} while(0)
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup UARTEx_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup UARTEx_Exported_Functions_Group1
-  * @{
-  */
-
-/* Initialization and de-initialization functions  ****************************/
-HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup UARTEx_Exported_Functions_Group3
-  * @{
-  */
-
-/* Peripheral Control functions  **********************************************/
-HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F7xx_HAL_UART_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/inc/stm32f7xx_ll_sdmmc.h b/stmhal/hal/f7/inc/stm32f7xx_ll_sdmmc.h
deleted file mode 100644
index 5c33e87eaa..0000000000
--- a/stmhal/hal/f7/inc/stm32f7xx_ll_sdmmc.h
+++ /dev/null
@@ -1,804 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_ll_sdmmc.h
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   Header file of SDMMC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_LL_SDMMC_H
-#define __STM32F7xx_LL_SDMMC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal_def.h"
-
-/** @addtogroup STM32F7xx_Driver
-  * @{
-  */
-
-/** @addtogroup SDMMC_LL
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
-  * @{
-  */
-
-/**
-  * @brief  SDMMC Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t ClockEdge;            /*!< Specifies the clock transition on which the bit capture is made.
-                                      This parameter can be a value of @ref SDMMC_LL_Clock_Edge                 */
-
-  uint32_t ClockBypass;          /*!< Specifies whether the SDMMC Clock divider bypass is
-                                      enabled or disabled.
-                                      This parameter can be a value of @ref SDMMC_LL_Clock_Bypass               */
-
-  uint32_t ClockPowerSave;       /*!< Specifies whether SDMMC Clock output is enabled or
-                                      disabled when the bus is idle.
-                                      This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save           */
-
-  uint32_t BusWide;              /*!< Specifies the SDMMC bus width.
-                                      This parameter can be a value of @ref SDMMC_LL_Bus_Wide                   */
-
-  uint32_t HardwareFlowControl;  /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.
-                                      This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control      */
-
-  uint32_t ClockDiv;             /*!< Specifies the clock frequency of the SDMMC controller.
-                                      This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
-
-}SDMMC_InitTypeDef;
-
-
-/**
-  * @brief  SDMMC Command Control structure
-  */
-typedef struct
-{
-  uint32_t Argument;            /*!< Specifies the SDMMC command argument which is sent
-                                     to a card as part of a command message. If a command
-                                     contains an argument, it must be loaded into this register
-                                     before writing the command to the command register.              */
-
-  uint32_t CmdIndex;            /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and
-                                     Max_Data = 64                                                    */
-
-  uint32_t Response;            /*!< Specifies the SDMMC response type.
-                                     This parameter can be a value of @ref SDMMC_LL_Response_Type         */
-
-  uint32_t WaitForInterrupt;    /*!< Specifies whether SDMMC wait for interrupt request is
-                                     enabled or disabled.
-                                     This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State  */
-
-  uint32_t CPSM;                /*!< Specifies whether SDMMC Command path state machine (CPSM)
-                                     is enabled or disabled.
-                                     This parameter can be a value of @ref SDMMC_LL_CPSM_State            */
-}SDMMC_CmdInitTypeDef;
-
-
-/**
-  * @brief  SDMMC Data Control structure
-  */
-typedef struct
-{
-  uint32_t DataTimeOut;         /*!< Specifies the data timeout period in card bus clock periods.  */
-
-  uint32_t DataLength;          /*!< Specifies the number of data bytes to be transferred.         */
-
-  uint32_t DataBlockSize;       /*!< Specifies the data block size for block transfer.
-                                     This parameter can be a value of @ref SDMMC_LL_Data_Block_Size    */
-
-  uint32_t TransferDir;         /*!< Specifies the data transfer direction, whether the transfer
-                                     is a read or write.
-                                     This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
-
-  uint32_t TransferMode;        /*!< Specifies whether data transfer is in stream or block mode.
-                                     This parameter can be a value of @ref SDMMC_LL_Transfer_Type      */
-
-  uint32_t DPSM;                /*!< Specifies whether SDMMC Data path state machine (DPSM)
-                                     is enabled or disabled.
-                                     This parameter can be a value of @ref SDMMC_LL_DPSM_State         */
-}SDMMC_DataInitTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
-  * @{
-  */
-
-/** @defgroup SDMMC_LL_Clock_Edge Clock Edge
-  * @{
-  */
-#define SDMMC_CLOCK_EDGE_RISING               ((uint32_t)0x00000000U)
-#define SDMMC_CLOCK_EDGE_FALLING              SDMMC_CLKCR_NEGEDGE
-
-#define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \
-                                  ((EDGE) == SDMMC_CLOCK_EDGE_FALLING))
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass
-  * @{
-  */
-#define SDMMC_CLOCK_BYPASS_DISABLE             ((uint32_t)0x00000000U)
-#define SDMMC_CLOCK_BYPASS_ENABLE              SDMMC_CLKCR_BYPASS
-
-#define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) || \
-                                      ((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE))
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving
-  * @{
-  */
-#define SDMMC_CLOCK_POWER_SAVE_DISABLE         ((uint32_t)0x00000000U)
-#define SDMMC_CLOCK_POWER_SAVE_ENABLE          SDMMC_CLKCR_PWRSAV
-
-#define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \
-                                        ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE))
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Bus_Wide Bus Width
-  * @{
-  */
-#define SDMMC_BUS_WIDE_1B                      ((uint32_t)0x00000000U)
-#define SDMMC_BUS_WIDE_4B                      SDMMC_CLKCR_WIDBUS_0
-#define SDMMC_BUS_WIDE_8B                      SDMMC_CLKCR_WIDBUS_1
-
-#define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \
-                                ((WIDE) == SDMMC_BUS_WIDE_4B) || \
-                                ((WIDE) == SDMMC_BUS_WIDE_8B))
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control
-  * @{
-  */
-#define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE    ((uint32_t)0x00000000U)
-#define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE     SDMMC_CLKCR_HWFC_EN
-
-#define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \
-                                                ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE))
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Clock_Division Clock Division
-  * @{
-  */
-#define IS_SDMMC_CLKDIV(DIV)   ((DIV) <= 0xFF)
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Command_Index Command Index
-  * @{
-  */
-#define IS_SDMMC_CMD_INDEX(INDEX)            ((INDEX) < 0x40)
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Response_Type Response Type
-  * @{
-  */
-#define SDMMC_RESPONSE_NO                    ((uint32_t)0x00000000U)
-#define SDMMC_RESPONSE_SHORT                 SDMMC_CMD_WAITRESP_0
-#define SDMMC_RESPONSE_LONG                  SDMMC_CMD_WAITRESP
-
-#define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO)    || \
-                                    ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \
-                                    ((RESPONSE) == SDMMC_RESPONSE_LONG))
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt
-  * @{
-  */
-#define SDMMC_WAIT_NO                        ((uint32_t)0x00000000U)
-#define SDMMC_WAIT_IT                        SDMMC_CMD_WAITINT
-#define SDMMC_WAIT_PEND                      SDMMC_CMD_WAITPEND
-
-#define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \
-                            ((WAIT) == SDMMC_WAIT_IT) || \
-                            ((WAIT) == SDMMC_WAIT_PEND))
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_CPSM_State CPSM State
-  * @{
-  */
-#define SDMMC_CPSM_DISABLE                   ((uint32_t)0x00000000U)
-#define SDMMC_CPSM_ENABLE                    SDMMC_CMD_CPSMEN
-
-#define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \
-                            ((CPSM) == SDMMC_CPSM_ENABLE))
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Response_Registers Response Register
-  * @{
-  */
-#define SDMMC_RESP1                          ((uint32_t)0x00000000U)
-#define SDMMC_RESP2                          ((uint32_t)0x00000004U)
-#define SDMMC_RESP3                          ((uint32_t)0x00000008U)
-#define SDMMC_RESP4                          ((uint32_t)0x0000000C)
-
-#define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \
-                            ((RESP) == SDMMC_RESP2) || \
-                            ((RESP) == SDMMC_RESP3) || \
-                            ((RESP) == SDMMC_RESP4))
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Data_Length Data Lenght
-  * @{
-  */
-#define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Data_Block_Size  Data Block Size
-  * @{
-  */
-#define SDMMC_DATABLOCK_SIZE_1B               ((uint32_t)0x00000000U)
-#define SDMMC_DATABLOCK_SIZE_2B               SDMMC_DCTRL_DBLOCKSIZE_0
-#define SDMMC_DATABLOCK_SIZE_4B               SDMMC_DCTRL_DBLOCKSIZE_1
-#define SDMMC_DATABLOCK_SIZE_8B               (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1)
-#define SDMMC_DATABLOCK_SIZE_16B              SDMMC_DCTRL_DBLOCKSIZE_2
-#define SDMMC_DATABLOCK_SIZE_32B              (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2)
-#define SDMMC_DATABLOCK_SIZE_64B              (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
-#define SDMMC_DATABLOCK_SIZE_128B             (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
-#define SDMMC_DATABLOCK_SIZE_256B             SDMMC_DCTRL_DBLOCKSIZE_3
-#define SDMMC_DATABLOCK_SIZE_512B             (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3)
-#define SDMMC_DATABLOCK_SIZE_1024B            (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
-#define SDMMC_DATABLOCK_SIZE_2048B            (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
-#define SDMMC_DATABLOCK_SIZE_4096B            (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
-#define SDMMC_DATABLOCK_SIZE_8192B            (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
-#define SDMMC_DATABLOCK_SIZE_16384B           (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
-
-#define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B)    || \
-                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_2B)    || \
-                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_4B)    || \
-                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_8B)    || \
-                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_16B)   || \
-                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_32B)   || \
-                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_64B)   || \
-                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_128B)  || \
-                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_256B)  || \
-                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_512B)  || \
-                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \
-                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \
-                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \
-                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \
-                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B))
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction
-  * @{
-  */
-#define SDMMC_TRANSFER_DIR_TO_CARD            ((uint32_t)0x00000000U)
-#define SDMMC_TRANSFER_DIR_TO_SDMMC            SDMMC_DCTRL_DTDIR
-
-#define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \
-                                   ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC))
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Transfer_Type Transfer Type
-  * @{
-  */
-#define SDMMC_TRANSFER_MODE_BLOCK             ((uint32_t)0x00000000U)
-#define SDMMC_TRANSFER_MODE_STREAM            SDMMC_DCTRL_DTMODE
-
-#define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \
-                                     ((MODE) == SDMMC_TRANSFER_MODE_STREAM))
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_DPSM_State DPSM State
-  * @{
-  */
-#define SDMMC_DPSM_DISABLE                    ((uint32_t)0x00000000U)
-#define SDMMC_DPSM_ENABLE                     SDMMC_DCTRL_DTEN
-
-#define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\
-                            ((DPSM) == SDMMC_DPSM_ENABLE))
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode
-  * @{
-  */
-#define SDMMC_READ_WAIT_MODE_DATA2                ((uint32_t)0x00000000U)
-#define SDMMC_READ_WAIT_MODE_CLK                  (SDMMC_DCTRL_RWMOD)
-
-#define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \
-                                     ((MODE) == SDMMC_READ_WAIT_MODE_DATA2))
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources
-  * @{
-  */
-#define SDMMC_IT_CCRCFAIL                    SDMMC_STA_CCRCFAIL
-#define SDMMC_IT_DCRCFAIL                    SDMMC_STA_DCRCFAIL
-#define SDMMC_IT_CTIMEOUT                    SDMMC_STA_CTIMEOUT
-#define SDMMC_IT_DTIMEOUT                    SDMMC_STA_DTIMEOUT
-#define SDMMC_IT_TXUNDERR                    SDMMC_STA_TXUNDERR
-#define SDMMC_IT_RXOVERR                     SDMMC_STA_RXOVERR
-#define SDMMC_IT_CMDREND                     SDMMC_STA_CMDREND
-#define SDMMC_IT_CMDSENT                     SDMMC_STA_CMDSENT
-#define SDMMC_IT_DATAEND                     SDMMC_STA_DATAEND
-#define SDMMC_IT_DBCKEND                     SDMMC_STA_DBCKEND
-#define SDMMC_IT_CMDACT                      SDMMC_STA_CMDACT
-#define SDMMC_IT_TXACT                       SDMMC_STA_TXACT
-#define SDMMC_IT_RXACT                       SDMMC_STA_RXACT
-#define SDMMC_IT_TXFIFOHE                    SDMMC_STA_TXFIFOHE
-#define SDMMC_IT_RXFIFOHF                    SDMMC_STA_RXFIFOHF
-#define SDMMC_IT_TXFIFOF                     SDMMC_STA_TXFIFOF
-#define SDMMC_IT_RXFIFOF                     SDMMC_STA_RXFIFOF
-#define SDMMC_IT_TXFIFOE                     SDMMC_STA_TXFIFOE
-#define SDMMC_IT_RXFIFOE                     SDMMC_STA_RXFIFOE
-#define SDMMC_IT_TXDAVL                      SDMMC_STA_TXDAVL
-#define SDMMC_IT_RXDAVL                      SDMMC_STA_RXDAVL
-#define SDMMC_IT_SDIOIT                      SDMMC_STA_SDIOIT
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Flags Flags
-  * @{
-  */
-#define SDMMC_FLAG_CCRCFAIL                  SDMMC_STA_CCRCFAIL
-#define SDMMC_FLAG_DCRCFAIL                  SDMMC_STA_DCRCFAIL
-#define SDMMC_FLAG_CTIMEOUT                  SDMMC_STA_CTIMEOUT
-#define SDMMC_FLAG_DTIMEOUT                  SDMMC_STA_DTIMEOUT
-#define SDMMC_FLAG_TXUNDERR                  SDMMC_STA_TXUNDERR
-#define SDMMC_FLAG_RXOVERR                   SDMMC_STA_RXOVERR
-#define SDMMC_FLAG_CMDREND                   SDMMC_STA_CMDREND
-#define SDMMC_FLAG_CMDSENT                   SDMMC_STA_CMDSENT
-#define SDMMC_FLAG_DATAEND                   SDMMC_STA_DATAEND
-#define SDMMC_FLAG_DBCKEND                   SDMMC_STA_DBCKEND
-#define SDMMC_FLAG_CMDACT                    SDMMC_STA_CMDACT
-#define SDMMC_FLAG_TXACT                     SDMMC_STA_TXACT
-#define SDMMC_FLAG_RXACT                     SDMMC_STA_RXACT
-#define SDMMC_FLAG_TXFIFOHE                  SDMMC_STA_TXFIFOHE
-#define SDMMC_FLAG_RXFIFOHF                  SDMMC_STA_RXFIFOHF
-#define SDMMC_FLAG_TXFIFOF                   SDMMC_STA_TXFIFOF
-#define SDMMC_FLAG_RXFIFOF                   SDMMC_STA_RXFIFOF
-#define SDMMC_FLAG_TXFIFOE                   SDMMC_STA_TXFIFOE
-#define SDMMC_FLAG_RXFIFOE                   SDMMC_STA_RXFIFOE
-#define SDMMC_FLAG_TXDAVL                    SDMMC_STA_TXDAVL
-#define SDMMC_FLAG_RXDAVL                    SDMMC_STA_RXDAVL
-#define SDMMC_FLAG_SDIOIT                    SDMMC_STA_SDIOIT
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
-  * @{
-  */
-
-/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
-  * @brief SDMMC_LL registers bit address in the alias region
-  * @{
-  */
-/* ---------------------- SDMMC registers bit mask --------------------------- */
-/* --- CLKCR Register ---*/
-/* CLKCR register clear mask */
-#define CLKCR_CLEAR_MASK         ((uint32_t)(SDMMC_CLKCR_CLKDIV  | SDMMC_CLKCR_PWRSAV |\
-                                             SDMMC_CLKCR_BYPASS  | SDMMC_CLKCR_WIDBUS |\
-                                             SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN))
-
-/* --- DCTRL Register ---*/
-/* SDMMC DCTRL Clear Mask */
-#define DCTRL_CLEAR_MASK         ((uint32_t)(SDMMC_DCTRL_DTEN    | SDMMC_DCTRL_DTDIR |\
-                                             SDMMC_DCTRL_DTMODE  | SDMMC_DCTRL_DBLOCKSIZE))
-
-/* --- CMD Register ---*/
-/* CMD Register clear mask */
-#define CMD_CLEAR_MASK           ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\
-                                             SDMMC_CMD_WAITINT  | SDMMC_CMD_WAITPEND |\
-                                             SDMMC_CMD_CPSMEN   | SDMMC_CMD_SDIOSUSPEND))
-
-/* SDMMC Initialization Frequency (400KHz max) */
-#define SDMMC_INIT_CLK_DIV ((uint8_t)0x76)
-
-/* SDMMC Data Transfer Frequency (25MHz max) */
-#define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0)
-
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
- *  @brief macros to handle interrupts and specific clock configurations
- * @{
- */
-
-/**
-  * @brief  Enable the SDMMC device.
-  * @param  __INSTANCE__: SDMMC Instance
-  * @retval None
-  */
-#define __SDMMC_ENABLE(__INSTANCE__)  ((__INSTANCE__)->CLKCR |= SDMMC_CLKCR_CLKEN)
-
-/**
-  * @brief  Disable the SDMMC device.
-  * @param  __INSTANCE__: SDMMC Instance
-  * @retval None
-  */
-#define __SDMMC_DISABLE(__INSTANCE__)  ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN)
-
-/**
-  * @brief  Enable the SDMMC DMA transfer.
-  * @param  __INSTANCE__: SDMMC Instance
-  * @retval None
-  */
-#define __SDMMC_DMA_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_DMAEN)
-/**
-  * @brief  Disable the SDMMC DMA transfer.
-  * @param  __INSTANCE__: SDMMC Instance
-  * @retval None
-  */
-#define __SDMMC_DMA_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN)
-
-/**
-  * @brief  Enable the SDMMC device interrupt.
-  * @param  __INSTANCE__ : Pointer to SDMMC register base
-  * @param  __INTERRUPT__ : specifies the SDMMC interrupt sources to be enabled.
-  *         This parameter can be one or a combination of the following values:
-  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
-  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
-  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt
-  *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt
-  *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt
-  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
-  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
-  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt
-  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt
-  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt
-  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt
-  *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt
-  *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt
-  * @retval None
-  */
-#define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the SDMMC device interrupt.
-  * @param  __INSTANCE__ : Pointer to SDMMC register base
-  * @param  __INTERRUPT__ : specifies the SDMMC interrupt sources to be disabled.
-  *          This parameter can be one or a combination of the following values:
-  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
-  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
-  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt
-  *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt
-  *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt
-  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
-  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
-  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt
-  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt
-  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt
-  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt
-  *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt
-  *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt
-  * @retval None
-  */
-#define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
-
-/**
-  * @brief  Checks whether the specified SDMMC flag is set or not.
-  * @param  __INSTANCE__ : Pointer to SDMMC register base
-  * @param  __FLAG__: specifies the flag to check.
-  *          This parameter can be one of the following values:
-  *            @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
-  *            @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
-  *            @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
-  *            @arg SDMMC_FLAG_DTIMEOUT: Data timeout
-  *            @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
-  *            @arg SDMMC_FLAG_RXOVERR:  Received FIFO overrun error
-  *            @arg SDMMC_FLAG_CMDREND:  Command response received (CRC check passed)
-  *            @arg SDMMC_FLAG_CMDSENT:  Command sent (no response required)
-  *            @arg SDMMC_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
-  *            @arg SDMMC_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
-  *            @arg SDMMC_FLAG_CMDACT:   Command transfer in progress
-  *            @arg SDMMC_FLAG_TXACT:    Data transmit in progress
-  *            @arg SDMMC_FLAG_RXACT:    Data receive in progress
-  *            @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
-  *            @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
-  *            @arg SDMMC_FLAG_TXFIFOF:  Transmit FIFO full
-  *            @arg SDMMC_FLAG_RXFIFOF:  Receive FIFO full
-  *            @arg SDMMC_FLAG_TXFIFOE:  Transmit FIFO empty
-  *            @arg SDMMC_FLAG_RXFIFOE:  Receive FIFO empty
-  *            @arg SDMMC_FLAG_TXDAVL:   Data available in transmit FIFO
-  *            @arg SDMMC_FLAG_RXDAVL:   Data available in receive FIFO
-  *            @arg SDMMC_FLAG_SDMMCIT:   SD I/O interrupt received
-  * @retval The new state of SDMMC_FLAG (SET or RESET).
-  */
-#define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__)  (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
-
-
-/**
-  * @brief  Clears the SDMMC pending flags.
-  * @param  __INSTANCE__ : Pointer to SDMMC register base
-  * @param  __FLAG__: specifies the flag to clear.
-  *          This parameter can be one or a combination of the following values:
-  *            @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
-  *            @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
-  *            @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
-  *            @arg SDMMC_FLAG_DTIMEOUT: Data timeout
-  *            @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
-  *            @arg SDMMC_FLAG_RXOVERR:  Received FIFO overrun error
-  *            @arg SDMMC_FLAG_CMDREND:  Command response received (CRC check passed)
-  *            @arg SDMMC_FLAG_CMDSENT:  Command sent (no response required)
-  *            @arg SDMMC_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
-  *            @arg SDMMC_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
-  *            @arg SDMMC_FLAG_SDMMCIT:   SD I/O interrupt received
-  * @retval None
-  */
-#define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__)  ((__INSTANCE__)->ICR = (__FLAG__))
-
-/**
-  * @brief  Checks whether the specified SDMMC interrupt has occurred or not.
-  * @param  __INSTANCE__ : Pointer to SDMMC register base
-  * @param  __INTERRUPT__: specifies the SDMMC interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
-  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
-  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt
-  *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt
-  *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt
-  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
-  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
-  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt
-  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt
-  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt
-  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt
-  *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt
-  *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt
-  * @retval The new state of SDMMC_IT (SET or RESET).
-  */
-#define __SDMMC_GET_IT  (__INSTANCE__, __INTERRUPT__)  (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
-
-/**
-  * @brief  Clears the SDMMC's interrupt pending bits.
-  * @param  __INSTANCE__ : Pointer to SDMMC register base
-  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
-  *          This parameter can be one or a combination of the following values:
-  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
-  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt
-  * @retval None
-  */
-#define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->ICR = (__INTERRUPT__))
-
-/**
-  * @brief  Enable Start the SD I/O Read Wait operation.
-  * @param  __INSTANCE__ : Pointer to SDMMC register base
-  * @retval None
-  */
-#define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART)
-
-/**
-  * @brief  Disable Start the SD I/O Read Wait operations.
-  * @param  __INSTANCE__ : Pointer to SDMMC register base
-  * @retval None
-  */
-#define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART)
-
-/**
-  * @brief  Enable Start the SD I/O Read Wait operation.
-  * @param  __INSTANCE__ : Pointer to SDMMC register base
-  * @retval None
-  */
-#define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP)
-
-/**
-  * @brief  Disable Stop the SD I/O Read Wait operations.
-  * @param  __INSTANCE__ : Pointer to SDMMC register base
-  * @retval None
-  */
-#define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP)
-
-/**
-  * @brief  Enable the SD I/O Mode Operation.
-  * @param  __INSTANCE__ : Pointer to SDMMC register base
-  * @retval None
-  */
-#define __SDMMC_OPERATION_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN)
-
-/**
-  * @brief  Disable the SD I/O Mode Operation.
-  * @param  __INSTANCE__ : Pointer to SDMMC register base
-  * @retval None
-  */
-#define __SDMMC_OPERATION_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN)
-
-/**
-  * @brief  Enable the SD I/O Suspend command sending.
-  * @param  __INSTANCE__ : Pointer to SDMMC register base
-  * @retval None
-  */
-#define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__)  ((__INSTANCE__)->CMD |= SDMMC_CMD_SDIOSUSPEND)
-
-/**
-  * @brief  Disable the SD I/O Suspend command sending.
-  * @param  __INSTANCE__ : Pointer to SDMMC register base
-  * @retval None
-  */
-#define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__)  ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND)
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SDMMC_LL_Exported_Functions
-  * @{
-  */
-
-/* Initialization/de-initialization functions  **********************************/
-/** @addtogroup HAL_SDMMC_LL_Group1
-  * @{
-  */
-HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init);
-/**
-  * @}
-  */
-
-/* I/O operation functions  *****************************************************/
-/** @addtogroup HAL_SDMMC_LL_Group2
-  * @{
-  */
-/* Blocking mode: Polling */
-uint32_t          SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx);
-HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData);
-/**
-  * @}
-  */
-
-/* Peripheral Control functions  ************************************************/
-/** @addtogroup HAL_SDMMC_LL_Group3
-  * @{
-  */
-HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx);
-HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx);
-uint32_t          SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx);
-
-/* Command path state machine (CPSM) management functions */
-HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command);
-uint8_t           SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx);
-uint32_t          SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response);
-
-/* Data path state machine (DPSM) management functions */
-HAL_StatusTypeDef SDMMC_DataConfig(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data);
-uint32_t          SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx);
-uint32_t          SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx);
-
-/* SDMMC Cards mode management functions */
-HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F7xx_LL_SDMMC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/inc/stm32f7xx_ll_usb.h b/stmhal/hal/f7/inc/stm32f7xx_ll_usb.h
deleted file mode 100644
index 63f37f15dd..0000000000
--- a/stmhal/hal/f7/inc/stm32f7xx_ll_usb.h
+++ /dev/null
@@ -1,463 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_ll_usb.h
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   Header file of USB Core HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_LL_USB_H
-#define __STM32F7xx_LL_USB_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal_def.h"
-
-/** @addtogroup STM32F7xx_HAL
-  * @{
-  */
-
-/** @addtogroup USB_Core
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
-  * @brief  USB Mode definition
-  */
-typedef enum
-{
-   USB_OTG_DEVICE_MODE  = 0U,
-   USB_OTG_HOST_MODE    = 1U,
-   USB_OTG_DRD_MODE     = 2U
-
-}USB_OTG_ModeTypeDef;
-
-/**
-  * @brief  URB States definition
-  */
-typedef enum {
-  URB_IDLE = 0U,
-  URB_DONE,
-  URB_NOTREADY,
-  URB_NYET,
-  URB_ERROR,
-  URB_STALL
-
-}USB_OTG_URBStateTypeDef;
-
-/**
-  * @brief  Host channel States  definition
-  */
-typedef enum {
-  HC_IDLE = 0U,
-  HC_XFRC,
-  HC_HALTED,
-  HC_NAK,
-  HC_NYET,
-  HC_STALL,
-  HC_XACTERR,
-  HC_BBLERR,
-  HC_DATATGLERR
-
-}USB_OTG_HCStateTypeDef;
-
-/**
-  * @brief  PCD Initialization Structure definition
-  */
-typedef struct
-{
-  uint32_t dev_endpoints;        /*!< Device Endpoints number.
-                                      This parameter depends on the used USB core.
-                                      This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
-
-  uint32_t Host_channels;        /*!< Host Channels number.
-                                      This parameter Depends on the used USB core.
-                                      This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
-
-  uint32_t speed;                /*!< USB Core speed.
-                                      This parameter can be any value of @ref USB_Core_Speed_                */
-
-  uint32_t dma_enable;           /*!< Enable or disable of the USB embedded DMA.                             */
-
-  uint32_t ep0_mps;              /*!< Set the Endpoint 0 Max Packet size.
-                                      This parameter can be any value of @ref USB_EP0_MPS_                   */
-
-  uint32_t phy_itface;           /*!< Select the used PHY interface.
-                                      This parameter can be any value of @ref USB_Core_PHY_                  */
-
-  uint32_t Sof_enable;           /*!< Enable or disable the output of the SOF signal.                        */
-
-  uint32_t low_power_enable;     /*!< Enable or disable the low power mode.                                  */
-
-  uint32_t lpm_enable;           /*!< Enable or disable Link Power Management.                               */
-
-  uint32_t vbus_sensing_enable;  /*!< Enable or disable the VBUS Sensing feature.                            */
-
-  uint32_t use_dedicated_ep1;    /*!< Enable or disable the use of the dedicated EP1 interrupt.              */
-
-  uint32_t use_external_vbus;    /*!< Enable or disable the use of the external VBUS.                        */
-
-}USB_OTG_CfgTypeDef;
-
-typedef struct
-{
-  uint8_t   num;            /*!< Endpoint number
-                                This parameter must be a number between Min_Data = 1 and Max_Data = 15    */
-
-  uint8_t   is_in;          /*!< Endpoint direction
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 1     */
-
-  uint8_t   is_stall;       /*!< Endpoint stall condition
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 1     */
-
-  uint8_t   type;           /*!< Endpoint type
-                                 This parameter can be any value of @ref USB_EP_Type_                     */
-
-  uint8_t   data_pid_start; /*!< Initial data PID
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 1     */
-
-  uint8_t   even_odd_frame; /*!< IFrame parity
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 1    */
-
-  uint16_t  tx_fifo_num;    /*!< Transmission FIFO number
-                                 This parameter must be a number between Min_Data = 1 and Max_Data = 15   */
-
-  uint32_t  maxpacket;      /*!< Endpoint Max packet size
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
-
-  uint8_t   *xfer_buff;     /*!< Pointer to transfer buffer                                               */
-
-  uint32_t  dma_addr;       /*!< 32 bits aligned transfer buffer address                                  */
-
-  uint32_t  xfer_len;       /*!< Current transfer length                                                  */
-
-  uint32_t  xfer_count;     /*!< Partial transfer length in case of multi packet transfer                 */
-
-}USB_OTG_EPTypeDef;
-
-typedef struct
-{
-  uint8_t   dev_addr ;     /*!< USB device address.
-                                This parameter must be a number between Min_Data = 1 and Max_Data = 255    */
-
-  uint8_t   ch_num;        /*!< Host channel number.
-                                This parameter must be a number between Min_Data = 1 and Max_Data = 15     */
-
-  uint8_t   ep_num;        /*!< Endpoint number.
-                                This parameter must be a number between Min_Data = 1 and Max_Data = 15     */
-
-  uint8_t   ep_is_in;      /*!< Endpoint direction
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
-
-  uint8_t   speed;         /*!< USB Host speed.
-                                This parameter can be any value of @ref USB_Core_Speed_                    */
-
-  uint8_t   do_ping;       /*!< Enable or disable the use of the PING protocol for HS mode.                */
-
-  uint8_t   process_ping;  /*!< Execute the PING protocol for HS mode.                                     */
-
-  uint8_t   ep_type;       /*!< Endpoint Type.
-                                This parameter can be any value of @ref USB_EP_Type_                       */
-
-  uint16_t  max_packet;    /*!< Endpoint Max packet size.
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 64KB   */
-
-  uint8_t   data_pid;      /*!< Initial data PID.
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
-
-  uint8_t   *xfer_buff;    /*!< Pointer to transfer buffer.                                                */
-
-  uint32_t  xfer_len;      /*!< Current transfer length.                                                   */
-
-  uint32_t  xfer_count;    /*!< Partial transfer length in case of multi packet transfer.                  */
-
-  uint8_t   toggle_in;     /*!< IN transfer current toggle flag.
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
-
-  uint8_t   toggle_out;    /*!< OUT transfer current toggle flag
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
-
-  uint32_t  dma_addr;      /*!< 32 bits aligned transfer buffer address.                                   */
-
-  uint32_t  ErrCnt;        /*!< Host channel error count.*/
-
-  USB_OTG_URBStateTypeDef  urb_state;  /*!< URB state.
-                                           This parameter can be any value of @ref USB_OTG_URBStateTypeDef */
-
-  USB_OTG_HCStateTypeDef   state;     /*!< Host Channel state.
-                                           This parameter can be any value of @ref USB_OTG_HCStateTypeDef  */
-
-}USB_OTG_HCTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup PCD_Exported_Constants PCD Exported Constants
-  * @{
-  */
-
-/** @defgroup USB_Core_Mode_ USB Core Mode
-  * @{
-  */
-#define USB_OTG_MODE_DEVICE                    0U
-#define USB_OTG_MODE_HOST                      1U
-#define USB_OTG_MODE_DRD                       2U
-/**
-  * @}
-  */
-
-/** @defgroup USB_Core_Speed_   USB Core Speed
-  * @{
-  */
-#define USB_OTG_SPEED_HIGH                     0U
-#define USB_OTG_SPEED_HIGH_IN_FULL             1U
-#define USB_OTG_SPEED_LOW                      2U
-#define USB_OTG_SPEED_FULL                     3U
-/**
-  * @}
-  */
-
-/** @defgroup USB_Core_PHY_   USB Core PHY
-  * @{
-  */
-#define USB_OTG_ULPI_PHY                       1U
-#define USB_OTG_EMBEDDED_PHY                   2U
-/**
-  * @}
-  */
-
-/** @defgroup USB_Core_MPS_   USB Core MPS
-  * @{
-  */
-#define USB_OTG_HS_MAX_PACKET_SIZE           512U
-#define USB_OTG_FS_MAX_PACKET_SIZE           64U
-#define USB_OTG_MAX_EP0_SIZE                 64U
-/**
-  * @}
-  */
-
-/** @defgroup USB_Core_Phy_Frequency_   USB Core Phy Frequency
-  * @{
-  */
-#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ     (0 << 1)
-#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ     (1 << 1)
-#define DSTS_ENUMSPD_LS_PHY_6MHZ               (2 << 1)
-#define DSTS_ENUMSPD_FS_PHY_48MHZ              (3 << 1)
-/**
-  * @}
-  */
-
-/** @defgroup USB_CORE_Frame_Interval_   USB CORE Frame Interval
-  * @{
-  */
-#define DCFG_FRAME_INTERVAL_80                 0U
-#define DCFG_FRAME_INTERVAL_85                 1U
-#define DCFG_FRAME_INTERVAL_90                 2U
-#define DCFG_FRAME_INTERVAL_95                 3U
-/**
-  * @}
-  */
-
-/** @defgroup USB_EP0_MPS_  USB EP0 MPS
-  * @{
-  */
-#define DEP0CTL_MPS_64                         0U
-#define DEP0CTL_MPS_32                         1U
-#define DEP0CTL_MPS_16                         2U
-#define DEP0CTL_MPS_8                          3U
-/**
-  * @}
-  */
-
-/** @defgroup USB_EP_Speed_  USB EP Speed
-  * @{
-  */
-#define EP_SPEED_LOW                           0U
-#define EP_SPEED_FULL                          1U
-#define EP_SPEED_HIGH                          2U
-/**
-  * @}
-  */
-
-/** @defgroup USB_EP_Type_  USB EP Type
-  * @{
-  */
-#define EP_TYPE_CTRL                           0U
-#define EP_TYPE_ISOC                           1U
-#define EP_TYPE_BULK                           2U
-#define EP_TYPE_INTR                           3U
-#define EP_TYPE_MSK                            3U
-/**
-  * @}
-  */
-
-/** @defgroup USB_STS_Defines_   USB STS Defines
-  * @{
-  */
-#define STS_GOUT_NAK                           1U
-#define STS_DATA_UPDT                          2U
-#define STS_XFER_COMP                          3U
-#define STS_SETUP_COMP                         4U
-#define STS_SETUP_UPDT                         6U
-/**
-  * @}
-  */
-
-/** @defgroup HCFG_SPEED_Defines_   HCFG SPEED Defines
-  * @{
-  */
-#define HCFG_30_60_MHZ                         0U
-#define HCFG_48_MHZ                            1U
-#define HCFG_6_MHZ                             2U
-/**
-  * @}
-  */
-
-/** @defgroup HPRT0_PRTSPD_SPEED_Defines_  HPRT0 PRTSPD SPEED Defines
-  * @{
-  */
-#define HPRT0_PRTSPD_HIGH_SPEED                0U
-#define HPRT0_PRTSPD_FULL_SPEED                1U
-#define HPRT0_PRTSPD_LOW_SPEED                 2U
-/**
-  * @}
-  */
-
-#define HCCHAR_CTRL                            0U
-#define HCCHAR_ISOC                            1U
-#define HCCHAR_BULK                            2U
-#define HCCHAR_INTR                            3U
-
-#define HC_PID_DATA0                           0U
-#define HC_PID_DATA2                           1U
-#define HC_PID_DATA1                           2U
-#define HC_PID_SETUP                           3U
-
-#define GRXSTS_PKTSTS_IN                       2U
-#define GRXSTS_PKTSTS_IN_XFER_COMP             3U
-#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR          5U
-#define GRXSTS_PKTSTS_CH_HALTED                7U
-
-#define USBx_PCGCCTL    *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_PCGCCTL_BASE)
-#define USBx_HPRT0      *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_HOST_PORT_BASE)
-
-#define USBx_DEVICE     ((USB_OTG_DeviceTypeDef *)((uint32_t )USBx + USB_OTG_DEVICE_BASE))
-#define USBx_INEP(i)    ((USB_OTG_INEndpointTypeDef *)((uint32_t)USBx + USB_OTG_IN_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE))
-#define USBx_OUTEP(i)   ((USB_OTG_OUTEndpointTypeDef *)((uint32_t)USBx + USB_OTG_OUT_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE))
-#define USBx_DFIFO(i)   *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_FIFO_BASE + (i) * USB_OTG_FIFO_SIZE)
-
-#define USBx_HOST       ((USB_OTG_HostTypeDef *)((uint32_t )USBx + USB_OTG_HOST_BASE))
-#define USBx_HC(i)      ((USB_OTG_HostChannelTypeDef *)((uint32_t)USBx + USB_OTG_HOST_CHANNEL_BASE + (i)*USB_OTG_HOST_CHANNEL_SIZE))
-/**
-  * @}
-  */
-/* Exported macro ------------------------------------------------------------*/
-#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__)     ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))
-#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__)   ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))
-
-#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__)          (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))
-#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__)         (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))
-
-/* Exported functions --------------------------------------------------------*/
-HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
-HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
-HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode);
-HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed);
-HAL_StatusTypeDef USB_FlushRxFifo (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num );
-HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma);
-HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma);
-HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma);
-void *            USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
-HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address);
-HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup);
-uint8_t           USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);
-uint32_t          USB_GetMode(USB_OTG_GlobalTypeDef *USBx);
-uint32_t          USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx);
-uint32_t          USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx);
-uint32_t          USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);
-uint32_t          USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx);
-uint32_t          USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);
-void              USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
-
-HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
-HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq);
-HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state);
-uint32_t          USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx);
-uint32_t          USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
-                                  uint8_t ch_num,
-                                  uint8_t epnum,
-                                  uint8_t dev_address,
-                                  uint8_t speed,
-                                  uint8_t ep_type,
-                                  uint16_t mps);
-HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma);
-uint32_t          USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num);
-HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num);
-HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F7xx_LL_USB_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal.c b/stmhal/hal/f7/src/stm32f7xx_hal.c
deleted file mode 100644
index a790e7a859..0000000000
--- a/stmhal/hal/f7/src/stm32f7xx_hal.c
+++ /dev/null
@@ -1,536 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal.c
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   HAL module driver.
-  *          This is the common part of the HAL initialization
-  *
-  @verbatim
-  ==============================================================================
-                     ##### How to use this driver #####
-  ==============================================================================
-    [..]
-    The common HAL driver contains a set of generic and common APIs that can be
-    used by the PPP peripheral drivers and the user to start using the HAL.
-    [..]
-    The HAL contains two APIs' categories:
-         (+) Common HAL APIs
-         (+) Services HAL APIs
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup HAL HAL
-  * @brief HAL module driver.
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup HAL_Private_Constants
-  * @{
-  */
-/**
- * @brief STM32F7xx HAL Driver version number V1.1.2
-   */
-#define __STM32F7xx_HAL_VERSION_MAIN   (0x01) /*!< [31:24] main version */
-#define __STM32F7xx_HAL_VERSION_SUB1   (0x01) /*!< [23:16] sub1 version */
-#define __STM32F7xx_HAL_VERSION_SUB2   (0x02) /*!< [15:8]  sub2 version */
-#define __STM32F7xx_HAL_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
-#define __STM32F7xx_HAL_VERSION         ((__STM32F7xx_HAL_VERSION_MAIN << 24)\
-                                        |(__STM32F7xx_HAL_VERSION_SUB1 << 16)\
-                                        |(__STM32F7xx_HAL_VERSION_SUB2 << 8 )\
-                                        |(__STM32F7xx_HAL_VERSION_RC))
-
-#define IDCODE_DEVID_MASK    ((uint32_t)0x00000FFF)
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @addtogroup HAL_Private_Variables
-  * @{
-  */
-__IO uint32_t uwTick;
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup HAL_Exported_Functions HAL Exported Functions
-  * @{
-  */
-
-/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
- *  @brief    Initialization and de-initialization functions
- *
-@verbatim
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Initializes the Flash interface the NVIC allocation and initial clock
-          configuration. It initializes the systick also when timeout is needed
-          and the backup domain when enabled.
-      (+) de-Initializes common part of the HAL
-      (+) Configure The time base source to have 1ms time base with a dedicated
-          Tick interrupt priority.
-        (++) Systick timer is used by default as source of time base, but user
-             can eventually implement his proper time base source (a general purpose
-             timer for example or other time source), keeping in mind that Time base
-             duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
-             handled in milliseconds basis.
-        (++) Time base configuration function (HAL_InitTick ()) is called automatically
-             at the beginning of the program after reset by HAL_Init() or at any time
-             when clock is configured, by HAL_RCC_ClockConfig().
-        (++) Source of time base is configured  to generate interrupts at regular
-             time intervals. Care must be taken if HAL_Delay() is called from a
-             peripheral ISR process, the Tick interrupt line must have higher priority
-            (numerically lower) than the peripheral interrupt. Otherwise the caller
-            ISR process will be blocked.
-       (++) functions affecting time base configurations are declared as __weak
-             to make  override possible  in case of other  implementations in user file.
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  This function is used to initialize the HAL Library; it must be the first
-  *         instruction to be executed in the main program (before to call any other
-  *         HAL function), it performs the following:
-  *           Configure the Flash prefetch, and instruction cache through ART accelerator.
-  *           Configures the SysTick to generate an interrupt each 1 millisecond,
-  *           which is clocked by the HSI (at this stage, the clock is not yet
-  *           configured and thus the system is running from the internal HSI at 16 MHz).
-  *           Set NVIC Group Priority to 4.
-  *           Calls the HAL_MspInit() callback function defined in user file
-  *           "stm32f7xx_hal_msp.c" to do the global low level hardware initialization
-  *
-  * @note   SysTick is used as time base for the HAL_Delay() function, the application
-  *         need to ensure that the SysTick time base is always set to 1 millisecond
-  *         to have correct HAL operation.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_Init(void)
-{
-  /* Configure Flash prefetch and Instruction cache through ART accelerator */
-#if (ART_ACCLERATOR_ENABLE != 0)
-   __HAL_FLASH_ART_ENABLE();
-#endif /* ART_ACCLERATOR_ENABLE */
-
-  /* Set Interrupt Group Priority */
-  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
-
-  /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
-  HAL_InitTick(TICK_INT_PRIORITY);
-
-  /* Init the low level hardware */
-  HAL_MspInit();
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function de-Initializes common part of the HAL and stops the systick.
-  *         This function is optional.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DeInit(void)
-{
-  /* Reset of all peripherals */
-  __HAL_RCC_APB1_FORCE_RESET();
-  __HAL_RCC_APB1_RELEASE_RESET();
-
-  __HAL_RCC_APB2_FORCE_RESET();
-  __HAL_RCC_APB2_RELEASE_RESET();
-
-  __HAL_RCC_AHB1_FORCE_RESET();
-  __HAL_RCC_AHB1_RELEASE_RESET();
-
-  __HAL_RCC_AHB2_FORCE_RESET();
-  __HAL_RCC_AHB2_RELEASE_RESET();
-
-  __HAL_RCC_AHB3_FORCE_RESET();
-  __HAL_RCC_AHB3_RELEASE_RESET();
-
-  /* De-Init the low level hardware */
-  HAL_MspDeInit();
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the MSP.
-  * @retval None
-  */
-__weak void HAL_MspInit(void)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes the MSP.
-  * @retval None
-  */
-__weak void HAL_MspDeInit(void)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief This function configures the source of the time base.
-  *        The time source is configured  to have 1ms time base with a dedicated
-  *        Tick interrupt priority.
-  * @note This function is called  automatically at the beginning of program after
-  *       reset by HAL_Init() or at any time when clock is reconfigured  by HAL_RCC_ClockConfig().
-  * @note In the default implementation, SysTick timer is the source of time base.
-  *       It is used to generate interrupts at regular time intervals.
-  *       Care must be taken if HAL_Delay() is called from a peripheral ISR process,
-  *       The the SysTick interrupt must have higher priority (numerically lower)
-  *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
-  *       The function is declared as __weak  to be overwritten  in case of other
-  *       implementation  in user file.
-  * @param TickPriority: Tick interrupt priority.
-  * @retval HAL status
-  */
-__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
-{
-  /*Configure the SysTick to have interrupt in 1ms time basis*/
-  HAL_SYSTICK_Config(SystemCoreClock/1000);
-
-  /*Configure the SysTick IRQ priority */
-  HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
- *  @brief    HAL Control functions
- *
-@verbatim
- ===============================================================================
-                      ##### HAL Control functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Provide a tick value in millisecond
-      (+) Provide a blocking delay in millisecond
-      (+) Suspend the time base source interrupt
-      (+) Resume the time base source interrupt
-      (+) Get the HAL API driver version
-      (+) Get the device identifier
-      (+) Get the device revision identifier
-      (+) Enable/Disable Debug module during SLEEP mode
-      (+) Enable/Disable Debug module during STOP mode
-      (+) Enable/Disable Debug module during STANDBY mode
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief This function is called to increment  a global variable "uwTick"
-  *        used as application time base.
-  * @note In the default implementation, this variable is incremented each 1ms
-  *       in Systick ISR.
- * @note This function is declared as __weak to be overwritten in case of other
-  *      implementations in user file.
-  * @retval None
-  */
-__weak void HAL_IncTick(void)
-{
-  uwTick++;
-}
-
-/**
-  * @brief Provides a tick value in millisecond.
-  * @note This function is declared as __weak to be overwritten in case of other
-  *       implementations in user file.
-  * @retval tick value
-  */
-__weak uint32_t HAL_GetTick(void)
-{
-  return uwTick;
-}
-
-/**
-  * @brief This function provides accurate delay (in milliseconds) based
-  *        on variable incremented.
-  * @note In the default implementation , SysTick timer is the source of time base.
-  *       It is used to generate interrupts at regular time intervals where uwTick
-  *       is incremented.
-  * @note This function is declared as __weak to be overwritten in case of other
-  *       implementations in user file.
-  * @param Delay: specifies the delay time length, in milliseconds.
-  * @retval None
-  */
-__weak void HAL_Delay(__IO uint32_t Delay)
-{
-  uint32_t tickstart = 0;
-  tickstart = HAL_GetTick();
-  while((HAL_GetTick() - tickstart) < Delay)
-  {
-  }
-}
-
-/**
-  * @brief Suspend Tick increment.
-  * @note In the default implementation , SysTick timer is the source of time base. It is
-  *       used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
-  *       is called, the SysTick interrupt will be disabled and so Tick increment
-  *       is suspended.
-  * @note This function is declared as __weak to be overwritten in case of other
-  *       implementations in user file.
-  * @retval None
-  */
-__weak void HAL_SuspendTick(void)
-{
-  /* Disable SysTick Interrupt */
-  SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
-}
-
-/**
-  * @brief Resume Tick increment.
-  * @note In the default implementation , SysTick timer is the source of time base. It is
-  *       used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
-  *       is called, the SysTick interrupt will be enabled and so Tick increment
-  *       is resumed.
-  * @note This function is declared as __weak to be overwritten in case of other
-  *       implementations in user file.
-  * @retval None
-  */
-__weak void HAL_ResumeTick(void)
-{
-  /* Enable SysTick Interrupt */
-  SysTick->CTRL  |= SysTick_CTRL_TICKINT_Msk;
-}
-
-/**
-  * @brief  Returns the HAL revision
-  * @retval version : 0xXYZR (8bits for each decimal, R for RC)
-  */
-uint32_t HAL_GetHalVersion(void)
-{
- return __STM32F7xx_HAL_VERSION;
-}
-
-/**
-  * @brief  Returns the device revision identifier.
-  * @retval Device revision identifier
-  */
-uint32_t HAL_GetREVID(void)
-{
-   return((DBGMCU->IDCODE) >> 16U);
-}
-
-/**
-  * @brief  Returns the device identifier.
-  * @retval Device identifier
-  */
-uint32_t HAL_GetDEVID(void)
-{
-   return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
-}
-
-/**
-  * @brief  Enable the Debug Module during SLEEP mode
-  * @retval None
-  */
-void HAL_DBGMCU_EnableDBGSleepMode(void)
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
-  * @brief  Disable the Debug Module during SLEEP mode
-  * @retval None
-  */
-void HAL_DBGMCU_DisableDBGSleepMode(void)
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
-  * @brief  Enable the Debug Module during STOP mode
-  * @retval None
-  */
-void HAL_DBGMCU_EnableDBGStopMode(void)
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
-}
-
-/**
-  * @brief  Disable the Debug Module during STOP mode
-  * @retval None
-  */
-void HAL_DBGMCU_DisableDBGStopMode(void)
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
-}
-
-/**
-  * @brief  Enable the Debug Module during STANDBY mode
-  * @retval None
-  */
-void HAL_DBGMCU_EnableDBGStandbyMode(void)
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
-}
-
-/**
-  * @brief  Disable the Debug Module during STANDBY mode
-  * @retval None
-  */
-void HAL_DBGMCU_DisableDBGStandbyMode(void)
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
-}
-
-/**
-  * @brief  Enables the I/O Compensation Cell.
-  * @note   The I/O compensation cell can be used only when the device supply
-  *         voltage ranges from 2.4 to 3.6 V.
-  * @retval None
-  */
-void HAL_EnableCompensationCell(void)
-{
-  SYSCFG->CMPCR |= SYSCFG_CMPCR_CMP_PD;
-}
-
-/**
-  * @brief  Power-down the I/O Compensation Cell.
-  * @note   The I/O compensation cell can be used only when the device supply
-  *         voltage ranges from 2.4 to 3.6 V.
-  * @retval None
-  */
-void HAL_DisableCompensationCell(void)
-{
-  SYSCFG->CMPCR &= (uint32_t)~((uint32_t)SYSCFG_CMPCR_CMP_PD);
-}
-
-/**
-  * @brief  Enables the FMC Memory Mapping Swapping.
-  *
-  * @note   SDRAM is accessible at 0x60000000
-  *         and NOR/RAM is accessible at 0xC0000000
-  *
-  * @retval None
-  */
-void HAL_EnableFMCMemorySwapping(void)
-{
-  SYSCFG->MEMRMP |= SYSCFG_MEMRMP_SWP_FMC_0;
-}
-
-/**
-  * @brief  Disables the FMC Memory Mapping Swapping
-  *
-  * @note   SDRAM is accessible at 0xC0000000 (default mapping)
-  *         and NOR/RAM is accessible at 0x60000000 (default mapping)
-  *
-  * @retval None
-  */
-void HAL_DisableFMCMemorySwapping(void)
-{
-
-  SYSCFG->MEMRMP &= (uint32_t)~((uint32_t)SYSCFG_MEMRMP_SWP_FMC);
-}
-
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-/**
-* @brief  Enable the Internal FLASH Bank Swapping.
-*
-* @note   This function can be used only for STM32F77xx/STM32F76xx devices.
-*
-* @note   Flash Bank2 mapped at 0x08000000 (AXI) (aliased at 0x00200000 (TCM))
-*         and Flash Bank1 mapped at 0x08100000 (AXI) (aliased at 0x00300000 (TCM))
-*
-* @retval None
-*/
-void HAL_EnableMemorySwappingBank(void)
-{
-  SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB);
-}
-
-/**
-* @brief  Disable the Internal FLASH Bank Swapping.
-*
-* @note   This function can be used only for STM32F77xx/STM32F76xx devices.
-*
-* @note   The default state : Flash Bank1 mapped at 0x08000000 (AXI) (aliased at 0x00200000 (TCM))
-*         and Flash Bank2 mapped at 0x08100000 (AXI)( aliased at 0x00300000 (TCM))
-*
-* @retval None
-*/
-void HAL_DisableMemorySwappingBank(void)
-{
-  CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB);
-}
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_adc.c b/stmhal/hal/f7/src/stm32f7xx_hal_adc.c
deleted file mode 100644
index b8da090f06..0000000000
--- a/stmhal/hal/f7/src/stm32f7xx_hal_adc.c
+++ /dev/null
@@ -1,1686 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_adc.c
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   This file provides firmware functions to manage the following
-  *          functionalities of the Analog to Digital Convertor (ADC) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + State and errors functions
-  *
-  @verbatim
-  ==============================================================================
-                    ##### ADC Peripheral features #####
-  ==============================================================================
-  [..]
-  (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
-  (#) Interrupt generation at the end of conversion, end of injected conversion,
-      and in case of analog watchdog or overrun events
-  (#) Single and continuous conversion modes.
-  (#) Scan mode for automatic conversion of channel 0 to channel x.
-  (#) Data alignment with in-built data coherency.
-  (#) Channel-wise programmable sampling time.
-  (#) External trigger option with configurable polarity for both regular and
-      injected conversion.
-  (#) Dual/Triple mode (on devices with 2 ADCs or more).
-  (#) Configurable DMA data storage in Dual/Triple ADC mode.
-  (#) Configurable delay between conversions in Dual/Triple interleaved mode.
-  (#) ADC conversion type (refer to the datasheets).
-  (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
-      slower speed.
-  (#) ADC input range: VREF(minus) = VIN = VREF(plus).
-  (#) DMA request generation during regular channel conversion.
-
-
-                     ##### How to use this driver #####
-  ==============================================================================
-  [..]
-  (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():
-       (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()
-       (##) ADC pins configuration
-             (+++) Enable the clock for the ADC GPIOs using the following function:
-                   __HAL_RCC_GPIOx_CLK_ENABLE()
-             (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init()
-       (##) In case of using interrupts (e.g. HAL_ADC_Start_IT())
-             (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()
-             (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()
-             (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()
-       (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())
-             (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()
-             (+++) Configure and enable two DMA streams stream for managing data
-                 transfer from peripheral to memory (output stream)
-             (+++) Associate the initialized DMA handle to the CRYP DMA handle
-                 using  __HAL_LINKDMA()
-             (+++) Configure the priority and enable the NVIC for the transfer complete
-                 interrupt on the two DMA Streams. The output stream should have higher
-                 priority than the input stream.
-
-    *** Configuration of ADC, groups regular/injected, channels parameters ***
-  ==============================================================================
-  [..]
-  (#) Configure the ADC parameters (resolution, data alignment, ...)
-      and regular group parameters (conversion trigger, sequencer, ...)
-      using function HAL_ADC_Init().
-
-  (#) Configure the channels for regular group parameters (channel number,
-      channel rank into sequencer, ..., into regular group)
-      using function HAL_ADC_ConfigChannel().
-
-  (#) Optionally, configure the injected group parameters (conversion trigger,
-      sequencer, ..., of injected group)
-      and the channels for injected group parameters (channel number,
-      channel rank into sequencer, ..., into injected group)
-      using function HAL_ADCEx_InjectedConfigChannel().
-
-  (#) Optionally, configure the analog watchdog parameters (channels
-      monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig().
-
-  (#) Optionally, for devices with several ADC instances: configure the
-      multimode parameters using function HAL_ADCEx_MultiModeConfigChannel().
-
-                       *** Execution of ADC conversions ***
-  ==============================================================================
-  [..]
-  (#) ADC driver can be used among three modes: polling, interruption,
-      transfer by DMA.
-
-     *** Polling mode IO operation ***
-     =================================
-     [..]
-       (+) Start the ADC peripheral using HAL_ADC_Start()
-       (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage
-           user can specify the value of timeout according to his end application
-       (+) To read the ADC converted values, use the HAL_ADC_GetValue() function.
-       (+) Stop the ADC peripheral using HAL_ADC_Stop()
-
-     *** Interrupt mode IO operation ***
-     ===================================
-     [..]
-       (+) Start the ADC peripheral using HAL_ADC_Start_IT()
-       (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine
-       (+) At ADC end of conversion HAL_ADC_ConvCpltCallback() function is executed and user can
-           add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
-       (+) In case of ADC Error, HAL_ADC_ErrorCallback() function is executed and user can
-           add his own code by customization of function pointer HAL_ADC_ErrorCallback
-       (+) Stop the ADC peripheral using HAL_ADC_Stop_IT()
-
-     *** DMA mode IO operation ***
-     ==============================
-     [..]
-       (+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the length
-           of data to be transferred at each end of conversion
-       (+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user can
-           add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
-       (+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can
-           add his own code by customization of function pointer HAL_ADC_ErrorCallback
-       (+) Stop the ADC peripheral using HAL_ADC_Stop_DMA()
-
-     *** ADC HAL driver macros list ***
-     =============================================
-     [..]
-       Below the list of most used macros in ADC HAL driver.
-
-      (+) __HAL_ADC_ENABLE : Enable the ADC peripheral
-      (+) __HAL_ADC_DISABLE : Disable the ADC peripheral
-      (+) __HAL_ADC_ENABLE_IT: Enable the ADC end of conversion interrupt
-      (+) __HAL_ADC_DISABLE_IT: Disable the ADC end of conversion interrupt
-      (+) __HAL_ADC_GET_IT_SOURCE: Check if the specified ADC interrupt source is enabled or disabled
-      (+) __HAL_ADC_CLEAR_FLAG: Clear the ADC's pending flags
-      (+) __HAL_ADC_GET_FLAG: Get the selected ADC's flag status
-      (+) ADC_GET_RESOLUTION: Return resolution bits in CR1 register
-
-     [..]
-       (@) You can refer to the ADC HAL driver header file for more useful macros
-
-                      *** Deinitialization of ADC ***
-  ==============================================================================
-  [..]
-  (#) Disable the ADC interface
-     (++) ADC clock can be hard reset and disabled at RCC top level.
-     (++) Hard reset of ADC peripherals
-          using macro __HAL_RCC_ADC_FORCE_RESET(), __HAL_RCC_ADC_RELEASE_RESET().
-     (++) ADC clock disable using the equivalent macro/functions as configuration step.
-               (+++) Example:
-                   Into HAL_ADC_MspDeInit() (recommended code location) or with
-                   other device clock parameters configuration:
-               (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure);
-               (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI;
-               (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock)
-               (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
-
-  (#) ADC pins configuration
-     (++) Disable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_DISABLE()
-
-  (#) Optionally, in case of usage of ADC with interruptions:
-     (++) Disable the NVIC for ADC using function HAL_NVIC_DisableIRQ(ADCx_IRQn)
-
-  (#) Optionally, in case of usage of DMA:
-        (++) Deinitialize the DMA using function HAL_DMA_DeInit().
-        (++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn)
-
-    @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup ADC ADC
-  * @brief ADC driver modules
-  * @{
-  */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @addtogroup ADC_Private_Functions
-  * @{
-  */
-/* Private function prototypes -----------------------------------------------*/
-static void ADC_Init(ADC_HandleTypeDef* hadc);
-static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
-static void ADC_DMAError(DMA_HandleTypeDef *hdma);
-static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup ADC_Exported_Functions ADC Exported Functions
-  * @{
-  */
-
-/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @brief    Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Initialize and configure the ADC.
-      (+) De-initialize the ADC.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the ADCx peripheral according to the specified parameters
-  *         in the ADC_InitStruct and initializes the ADC MSP.
-  *
-  * @note   This function is used to configure the global features of the ADC (
-  *         ClockPrescaler, Resolution, Data Alignment and number of conversion), however,
-  *         the rest of the configuration parameters are specific to the regular
-  *         channels group (scan mode activation, continuous mode activation,
-  *         External trigger source and edge, DMA continuous request after the
-  *         last transfer and End of conversion selection).
-  *
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
-  /* Check ADC handle */
-  if(hadc == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
-  assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
-  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ScanConvMode));
-  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
-  assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv));
-  assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
-  assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
-  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
-  assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
-  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
-
-  if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
-  {
-    assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
-  }
-
-  if(hadc->State == HAL_ADC_STATE_RESET)
-  {
-    /* Initialize ADC error code */
-    ADC_CLEAR_ERRORCODE(hadc);
-
-    /* Allocate lock resource and initialize it */
-    hadc->Lock = HAL_UNLOCKED;
-    /* Init the low level hardware */
-    HAL_ADC_MspInit(hadc);
-  }
-
-  /* Configuration of ADC parameters if previous preliminary actions are      */
-  /* correctly completed.                                                     */
-  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
-  {
-    /* Set ADC state */
-    ADC_STATE_CLR_SET(hadc->State,
-                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
-                      HAL_ADC_STATE_BUSY_INTERNAL);
-
-    /* Set ADC parameters */
-    ADC_Init(hadc);
-
-    /* Set ADC error code to none */
-    ADC_CLEAR_ERRORCODE(hadc);
-
-    /* Set the ADC state */
-    ADC_STATE_CLR_SET(hadc->State,
-                      HAL_ADC_STATE_BUSY_INTERNAL,
-                      HAL_ADC_STATE_READY);
-  }
-  else
-  {
-    tmp_hal_status = HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hadc);
-
-  /* Return function status */
-  return tmp_hal_status;
-}
-
-/**
-  * @brief  Deinitializes the ADCx peripheral registers to their default reset values.
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
-  /* Check ADC handle */
-  if(hadc == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
-  /* Set ADC state */
-  SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
-
-  /* Stop potential conversion on going, on regular and injected groups */
-  /* Disable ADC peripheral */
-  __HAL_ADC_DISABLE(hadc);
-
-  /* Configuration of ADC parameters if previous preliminary actions are      */
-  /* correctly completed.                                                     */
-  if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
-  {
-    /* DeInit the low level hardware */
-    HAL_ADC_MspDeInit(hadc);
-
-    /* Set ADC error code to none */
-    ADC_CLEAR_ERRORCODE(hadc);
-
-    /* Set ADC state */
-    hadc->State = HAL_ADC_STATE_RESET;
-  }
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-
-  /* Return function status */
-  return tmp_hal_status;
-}
-
-/**
-  * @brief  Initializes the ADC MSP.
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @retval None
-  */
-__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_ADC_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes the ADC MSP.
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @retval None
-  */
-__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_ADC_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Exported_Functions_Group2 IO operation functions
- *  @brief    IO operation functions
- *
-@verbatim
- ===============================================================================
-             ##### IO operation functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Start conversion of regular channel.
-      (+) Stop conversion of regular channel.
-      (+) Start conversion of regular channel and enable interrupt.
-      (+) Stop conversion of regular channel and disable interrupt.
-      (+) Start conversion of regular channel and enable DMA transfer.
-      (+) Stop conversion of regular channel and disable DMA transfer.
-      (+) Handle ADC interrupt request.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables ADC and starts conversion of the regular channels.
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
-{
-  __IO uint32_t counter = 0;
-
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
-  assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
-
-  /* Process locked */
-  __HAL_LOCK(hadc);
-
-  /* Enable the ADC peripheral */
-  /* Check if ADC peripheral is disabled in order to enable it and wait during
-  Tstab time the ADC's stabilization */
-  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
-  {
-    /* Enable the Peripheral */
-    __HAL_ADC_ENABLE(hadc);
-
-    /* Delay for ADC stabilization time */
-    /* Compute number of CPU cycles to wait for */
-    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
-    while(counter != 0)
-    {
-      counter--;
-    }
-  }
-
-  /* Start conversion if ADC is effectively enabled */
-  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
-  {
-    /* Set ADC state                                                          */
-    /* - Clear state bitfield related to regular group conversion results     */
-    /* - Set state bitfield related to regular group operation                */
-    ADC_STATE_CLR_SET(hadc->State,
-                      HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
-                      HAL_ADC_STATE_REG_BUSY);
-
-    /* If conversions on group regular are also triggering group injected,    */
-    /* update ADC state.                                                      */
-    if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
-    {
-      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
-    }
-
-    /* State machine update: Check if an injected conversion is ongoing */
-    if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
-    {
-      /* Reset ADC error code fields related to conversions on group regular */
-      CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
-    }
-    else
-    {
-      /* Reset ADC all error code fields */
-      ADC_CLEAR_ERRORCODE(hadc);
-    }
-
-    /* Process unlocked */
-    /* Unlock before starting ADC conversions: in case of potential           */
-    /* interruption, to let the process to ADC IRQ Handler.                   */
-    __HAL_UNLOCK(hadc);
-
-    /* Clear regular group conversion flag and overrun flag */
-    /* (To ensure of no unknown state from potential previous ADC operations) */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
-
-    /* Check if Multimode enabled */
-    if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
-    {
-      /* if no external trigger present enable software conversion of regular channels */
-      if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
-      {
-        /* Enable the selected ADC software conversion for regular group */
-        hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
-      }
-    }
-    else
-    {
-      /* if instance of handle correspond to ADC1 and  no external trigger present enable software conversion of regular channels */
-      if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
-      {
-        /* Enable the selected ADC software conversion for regular group */
-          hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
-      }
-    }
-  }
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disables ADC and stop conversion of regular channels.
-  *
-  * @note   Caution: This function will stop also injected channels.
-  *
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  *
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
-  /* Process locked */
-  __HAL_LOCK(hadc);
-
-  /* Stop potential conversion on going, on regular and injected groups */
-  /* Disable ADC peripheral */
-  __HAL_ADC_DISABLE(hadc);
-
-  /* Check if ADC is effectively disabled */
-  if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
-  {
-    /* Set ADC state */
-    ADC_STATE_CLR_SET(hadc->State,
-                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
-                      HAL_ADC_STATE_READY);
-  }
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Poll for regular conversion complete
-  * @note   ADC conversion flags EOS (end of sequence) and EOC (end of
-  *         conversion) are cleared by this function.
-  * @note   This function cannot be used in a particular setup: ADC configured
-  *         in DMA mode and polling for end of each conversion (ADC init
-  *         parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
-  *         In this case, DMA resets the flag EOC and polling cannot be
-  *         performed on each conversion. Nevertheless, polling can still
-  *         be performed on the complete sequence.
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @param  Timeout: Timeout value in millisecond.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
-{
-  uint32_t tickstart = 0;
-
-  /* Verification that ADC configuration is compliant with polling for      */
-  /* each conversion:                                                       */
-  /* Particular case is ADC configured in DMA mode and ADC sequencer with   */
-  /* several ranks and polling for end of each conversion.                  */
-  /* For code simplicity sake, this particular case is generalized to       */
-  /* ADC configured in DMA mode and polling for end of each conversion.     */
-  if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&
-      HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA)    )
-  {
-    /* Update ADC state machine to error */
-    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
-    /* Process unlocked */
-    __HAL_UNLOCK(hadc);
-
-    return HAL_ERROR;
-  }
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  /* Check End of conversion flag */
-  while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
-  {
-    /* Check if timeout is disabled (set to infinite wait) */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        /* Update ADC state machine to timeout */
-        SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
-
-        /* Process unlocked */
-        __HAL_UNLOCK(hadc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Clear regular group conversion flag */
-  __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
-
-  /* Update ADC state machine */
-  SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
-
-  /* Determine whether any further conversion upcoming on group regular       */
-  /* by external trigger, continuous mode or scan sequence on going.          */
-  /* Note: On STM32F7, there is no independent flag of end of sequence.       */
-  /*       The test of scan sequence on going is done either with scan        */
-  /*       sequence disabled or with end of conversion flag set to            */
-  /*       of end of sequence.                                                */
-  if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&
-     (hadc->Init.ContinuousConvMode == DISABLE)            &&
-     (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
-      HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )
-  {
-    /* Set ADC state */
-    CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
-
-    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
-    {
-      SET_BIT(hadc->State, HAL_ADC_STATE_READY);
-    }
-  }
-
-  /* Return ADC state */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Poll for conversion event
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @param  EventType: the ADC event type.
-  *          This parameter can be one of the following values:
-  *            @arg ADC_AWD_EVENT: ADC Analog watch Dog event.
-  *            @arg ADC_OVR_EVENT: ADC Overrun event.
-  * @param  Timeout: Timeout value in millisecond.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
-{
-  uint32_t tickstart = 0;
-
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  assert_param(IS_ADC_EVENT_TYPE(EventType));
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  /* Check selected event flag */
-  while(!(__HAL_ADC_GET_FLAG(hadc,EventType)))
-  {
-    /* Check for the Timeout */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        /* Update ADC state machine to timeout */
-        SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
-
-        /* Process unlocked */
-        __HAL_UNLOCK(hadc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Analog watchdog (level out of window) event */
-  if(EventType == ADC_AWD_EVENT)
-  {
-    /* Set ADC state */
-    SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
-
-    /* Clear ADC analog watchdog flag */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
-  }
-  /* Overrun event */
-  else
-  {
-    /* Set ADC state */
-    SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
-    /* Set ADC error code to overrun */
-    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
-
-    /* Clear ADC overrun flag */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
-  }
-
-  /* Return ADC state */
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  Enables the interrupt and starts ADC conversion of regular channels.
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
-{
-  __IO uint32_t counter = 0;
-
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
-  assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
-
-  /* Process locked */
-  __HAL_LOCK(hadc);
-
-  /* Enable the ADC peripheral */
-  /* Check if ADC peripheral is disabled in order to enable it and wait during
-     Tstab time the ADC's stabilization */
-  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
-  {
-    /* Enable the Peripheral */
-    __HAL_ADC_ENABLE(hadc);
-
-    /* Delay for ADC stabilization time */
-    /* Compute number of CPU cycles to wait for */
-    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
-    while(counter != 0)
-    {
-      counter--;
-    }
-  }
-
-  /* Start conversion if ADC is effectively enabled */
-  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
-  {
-    /* Set ADC state                                                          */
-    /* - Clear state bitfield related to regular group conversion results     */
-    /* - Set state bitfield related to regular group operation                */
-    ADC_STATE_CLR_SET(hadc->State,
-                      HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
-                      HAL_ADC_STATE_REG_BUSY);
-
-    /* If conversions on group regular are also triggering group injected,    */
-    /* update ADC state.                                                      */
-    if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
-    {
-      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
-    }
-
-    /* State machine update: Check if an injected conversion is ongoing */
-    if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
-    {
-      /* Reset ADC error code fields related to conversions on group regular */
-      CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
-    }
-    else
-    {
-      /* Reset ADC all error code fields */
-      ADC_CLEAR_ERRORCODE(hadc);
-    }
-
-    /* Process unlocked */
-    /* Unlock before starting ADC conversions: in case of potential           */
-    /* interruption, to let the process to ADC IRQ Handler.                   */
-    __HAL_UNLOCK(hadc);
-
-    /* Clear regular group conversion flag and overrun flag */
-    /* (To ensure of no unknown state from potential previous ADC operations) */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
-
-    /* Enable end of conversion interrupt for regular group */
-    __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
-
-    /* Check if Multimode enabled */
-    if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
-    {
-      /* if no external trigger present enable software conversion of regular channels */
-      if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
-      {
-        /* Enable the selected ADC software conversion for regular group */
-        hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
-      }
-    }
-    else
-    {
-      /* if instance of handle correspond to ADC1 and  no external trigger present enable software conversion of regular channels */
-      if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
-      {
-        /* Enable the selected ADC software conversion for regular group */
-          hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
-      }
-    }
-  }
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disables the interrupt and stop ADC conversion of regular channels.
-  *
-  * @note   Caution: This function will stop also injected channels.
-  *
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
-  /* Process locked */
-  __HAL_LOCK(hadc);
-
-  /* Stop potential conversion on going, on regular and injected groups */
-  /* Disable ADC peripheral */
-  __HAL_ADC_DISABLE(hadc);
-
-  /* Check if ADC is effectively disabled */
-  if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
-  {
-  	/* Disable ADC end of conversion interrupt for regular group */
-    __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
-
-    /* Set ADC state */
-    ADC_STATE_CLR_SET(hadc->State,
-                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
-                      HAL_ADC_STATE_READY);
-  }
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handles ADC interrupt request
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @retval None
-  */
-void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
-{
-  uint32_t tmp1 = 0, tmp2 = 0;
-
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
-  assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
-  assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
-
-  tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC);
-  tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC);
-  /* Check End of conversion flag for regular channels */
-  if(tmp1 && tmp2)
-  {
-    /* Update state machine on conversion status if not in error state */
-    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
-    {
-      /* Set ADC state */
-      SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
-    }
-
-    /* Determine whether any further conversion upcoming on group regular   */
-    /* by external trigger, continuous mode or scan sequence on going.      */
-    /* Note: On STM32F7, there is no independent flag of end of sequence.   */
-    /*       The test of scan sequence on going is done either with scan    */
-    /*       sequence disabled or with end of conversion flag set to        */
-    /*       of end of sequence.                                            */
-    if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&
-       (hadc->Init.ContinuousConvMode == DISABLE)            &&
-       (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
-        HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )
-    {
-      /* Disable ADC end of single conversion interrupt on group regular */
-      /* Note: Overrun interrupt was enabled with EOC interrupt in          */
-      /* HAL_ADC_Start_IT(), but is not disabled here because can be used   */
-      /* by overrun IRQ process below.                                      */
-      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
-
-      /* Set ADC state */
-      CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
-
-      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
-      {
-        SET_BIT(hadc->State, HAL_ADC_STATE_READY);
-      }
-    }
-
-    /* Conversion complete callback */
-    HAL_ADC_ConvCpltCallback(hadc);
-
-    /* Clear regular group conversion flag */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
-  }
-
-  tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC);
-  tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC);
-  /* Check End of conversion flag for injected channels */
-  if(tmp1 && tmp2)
-  {
-    /* Update state machine on conversion status if not in error state */
-    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
-    {
-      /* Set ADC state */
-      SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
-    }
-
-    /* Determine whether any further conversion upcoming on group injected  */
-    /* by external trigger, scan sequence on going or by automatic injected */
-    /* conversion from group regular (same conditions as group regular      */
-    /* interruption disabling above).                                       */
-    if(ADC_IS_SOFTWARE_START_INJECTED(hadc)                    &&
-       (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) ||
-        HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)) &&
-       (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
-       (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
-       (hadc->Init.ContinuousConvMode == DISABLE))))
-    {
-      /* Disable ADC end of single conversion interrupt on group injected */
-      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
-
-      /* Set ADC state */
-      CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
-
-      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
-      {
-        SET_BIT(hadc->State, HAL_ADC_STATE_READY);
-      }
-    }
-
-    /* Conversion complete callback */
-    HAL_ADCEx_InjectedConvCpltCallback(hadc);
-
-    /* Clear injected group conversion flag */
-    __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
-  }
-
-  tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD);
-  tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD);
-  /* Check Analog watchdog flag */
-  if(tmp1 && tmp2)
-  {
-    if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))
-    {
-      /* Set ADC state */
-      SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
-
-      /* Level out of window callback */
-      HAL_ADC_LevelOutOfWindowCallback(hadc);
-
-      /* Clear the ADC analog watchdog flag */
-      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
-    }
-  }
-
-  tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR);
-  tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR);
-  /* Check Overrun flag */
-  if(tmp1 && tmp2)
-  {
-    /* Note: On STM32F7, ADC overrun can be set through other parameters    */
-    /*       refer to description of parameter "EOCSelection" for more      */
-    /*       details.                                                       */
-
-    /* Set ADC error code to overrun */
-    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
-
-    /* Clear ADC overrun flag */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
-
-    /* Error callback */
-    HAL_ADC_ErrorCallback(hadc);
-
-    /* Clear the Overrun flag */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
-  }
-}
-
-/**
-  * @brief  Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @param  pData: The destination Buffer address.
-  * @param  Length: The length of data to be transferred from ADC peripheral to memory.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
-{
-  __IO uint32_t counter = 0;
-
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
-  assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
-
-  /* Process locked */
-  __HAL_LOCK(hadc);
-
-  /* Enable the ADC peripheral */
-  /* Check if ADC peripheral is disabled in order to enable it and wait during
-     Tstab time the ADC's stabilization */
-  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
-  {
-    /* Enable the Peripheral */
-    __HAL_ADC_ENABLE(hadc);
-
-    /* Delay for ADC stabilization time */
-    /* Compute number of CPU cycles to wait for */
-    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
-    while(counter != 0)
-    {
-      counter--;
-    }
-  }
-
-  /* Start conversion if ADC is effectively enabled */
-  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
-  {
-    /* Set ADC state                                                          */
-    /* - Clear state bitfield related to regular group conversion results     */
-    /* - Set state bitfield related to regular group operation                */
-    ADC_STATE_CLR_SET(hadc->State,
-                      HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
-                      HAL_ADC_STATE_REG_BUSY);
-
-    /* If conversions on group regular are also triggering group injected,    */
-    /* update ADC state.                                                      */
-    if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
-    {
-      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
-    }
-
-    /* State machine update: Check if an injected conversion is ongoing */
-    if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
-    {
-      /* Reset ADC error code fields related to conversions on group regular */
-      CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
-    }
-    else
-    {
-      /* Reset ADC all error code fields */
-      ADC_CLEAR_ERRORCODE(hadc);
-    }
-
-    /* Process unlocked */
-    /* Unlock before starting ADC conversions: in case of potential           */
-    /* interruption, to let the process to ADC IRQ Handler.                   */
-    __HAL_UNLOCK(hadc);
-
-    /* Set the DMA transfer complete callback */
-    hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
-
-    /* Set the DMA half transfer complete callback */
-    hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
-
-    /* Set the DMA error callback */
-    hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
-
-
-    /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */
-    /* start (in case of SW start):                                           */
-
-    /* Clear regular group conversion flag and overrun flag */
-    /* (To ensure of no unknown state from potential previous ADC operations) */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
-
-    /* Enable ADC overrun interrupt */
-    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
-
-    /* Enable ADC DMA mode */
-    hadc->Instance->CR2 |= ADC_CR2_DMA;
-
-    /* Start the DMA channel */
-    HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
-
-    /* Check if Multimode enabled */
-    if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
-    {
-      /* if no external trigger present enable software conversion of regular channels */
-      if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
-      {
-        /* Enable the selected ADC software conversion for regular group */
-        hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
-      }
-    }
-    else
-    {
-      /* if instance of handle correspond to ADC1 and  no external trigger present enable software conversion of regular channels */
-      if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
-      {
-        /* Enable the selected ADC software conversion for regular group */
-          hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
-      }
-    }
-  }
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disables ADC DMA (Single-ADC mode) and disables ADC peripheral
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
-  /* Process locked */
-  __HAL_LOCK(hadc);
-
-  /* Stop potential conversion on going, on regular and injected groups */
-  /* Disable ADC peripheral */
-  __HAL_ADC_DISABLE(hadc);
-
-  /* Check if ADC is effectively disabled */
-  if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
-  {
-    /* Disable the selected ADC DMA mode */
-    hadc->Instance->CR2 &= ~ADC_CR2_DMA;
-
-    /* Disable the DMA channel (in case of DMA in circular mode or stop while */
-    /* DMA transfer is on going)                                              */
-    tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
-
-    /* Disable ADC overrun interrupt */
-    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
-
-    /* Set ADC state */
-    ADC_STATE_CLR_SET(hadc->State,
-                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
-                      HAL_ADC_STATE_READY);
-  }
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-
-  /* Return function status */
-  return tmp_hal_status;
-}
-
-/**
-  * @brief  Gets the converted value from data register of regular channel.
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @retval Converted value
-  */
-uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
-{
-  /* Return the selected ADC converted value */
-  return hadc->Instance->DR;
-}
-
-/**
-  * @brief  Regular conversion complete callback in non blocking mode
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @retval None
-  */
-__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_ADC_ConvCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Regular conversion half DMA transfer callback in non blocking mode
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @retval None
-  */
-__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_ADC_ConvHalfCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Analog watchdog callback in non blocking mode
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @retval None
-  */
-__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_ADC_LevelOoutOfWindowCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Error ADC callback.
-  * @note   In case of error due to overrun when using ADC with DMA transfer
-  *         (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
-  *         - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
-  *         - If needed, restart a new ADC conversion using function
-  *           "HAL_ADC_Start_DMA()"
-  *           (this function is also clearing overrun flag)
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @retval None
-  */
-__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_ADC_ErrorCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
- *  @brief   	Peripheral Control functions
- *
-@verbatim
- ===============================================================================
-             ##### Peripheral Control functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Configure regular channels.
-      (+) Configure injected channels.
-      (+) Configure multimode.
-      (+) Configure the analog watch dog.
-
-@endverbatim
-  * @{
-  */
-
-  /**
-  * @brief  Configures for the selected ADC regular channel its corresponding
-  *         rank in the sequencer and its sample time.
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @param  sConfig: ADC configuration structure.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
-{
-  __IO uint32_t counter = 0;
-
-  /* Check the parameters */
-  assert_param(IS_ADC_CHANNEL(sConfig->Channel));
-  assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
-  assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
-
-  /* Process locked */
-  __HAL_LOCK(hadc);
-
-	/* if ADC_Channel_10 ... ADC_Channel_18 is selected */
-	if (sConfig->Channel > ADC_CHANNEL_9)
-	{
-		/* Clear the old sample time */
-		hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);
-
-		if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
-		{
-			/* Set the new sample time */
-			hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, ADC_CHANNEL_18);
-		}
-	  else
-	  {
-		  /* Set the new sample time */
-		  hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);
-	  }
-  }
-  else /* ADC_Channel include in ADC_Channel_[0..9] */
-  {
-    /* Clear the old sample time */
-    hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel);
-
-    /* Set the new sample time */
-    hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel);
-  }
-
-  /* For Rank 1 to 6 */
-  if (sConfig->Rank < 7)
-  {
-    /* Clear the old SQx bits for the selected rank */
-    hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank);
-
-    /* Set the SQx bits for the selected rank */
-    hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank);
-  }
-  /* For Rank 7 to 12 */
-  else if (sConfig->Rank < 13)
-  {
-    /* Clear the old SQx bits for the selected rank */
-    hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank);
-
-    /* Set the SQx bits for the selected rank */
-    hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank);
-  }
-  /* For Rank 13 to 16 */
-  else
-  {
-    /* Clear the old SQx bits for the selected rank */
-    hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank);
-
-    /* Set the SQx bits for the selected rank */
-    hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);
-  }
-
-  /* if ADC1 Channel_18 is selected enable VBAT Channel */
-  if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT))
-  {
-    /* Enable the VBAT channel*/
-    ADC->CCR |= ADC_CCR_VBATE;
-  }
-
-  /* if ADC1 Channel_18 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */
-  if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT)))
-  {
-    /* Enable the TSVREFE channel*/
-    ADC->CCR |= ADC_CCR_TSVREFE;
-
-    if(sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
-    {
-      /* Delay for temperature sensor stabilization time */
-      /* Compute number of CPU cycles to wait for */
-      counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
-      while(counter != 0)
-      {
-        counter--;
-      }
-    }
-  }
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the analog watchdog.
-  * @note   Analog watchdog thresholds can be modified while ADC conversion
-  *         is on going.
-  *         In this case, some constraints must be taken into account:
-  *         the programmed threshold values are effective from the next
-  *         ADC EOC (end of unitary conversion).
-  *         Considering that registers write delay may happen due to
-  *         bus activity, this might cause an uncertainty on the
-  *         effective timing of the new programmed threshold values.
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @param  AnalogWDGConfig : pointer to an ADC_AnalogWDGConfTypeDef structure
-  *         that contains the configuration information of ADC analog watchdog.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
-{
-#ifdef USE_FULL_ASSERT
-  uint32_t tmp = 0;
-#endif /* USE_FULL_ASSERT  */
-
-  /* Check the parameters */
-  assert_param(IS_ADC_ANALOG_WATCHDOG(AnalogWDGConfig->WatchdogMode));
-  assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
-  assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
-
-#ifdef USE_FULL_ASSERT
-  tmp = ADC_GET_RESOLUTION(hadc);
-  assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->HighThreshold));
-  assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->LowThreshold));
-#endif /* USE_FULL_ASSERT  */
-
-  /* Process locked */
-  __HAL_LOCK(hadc);
-
-  if(AnalogWDGConfig->ITMode == ENABLE)
-  {
-    /* Enable the ADC Analog watchdog interrupt */
-    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
-  }
-  else
-  {
-    /* Disable the ADC Analog watchdog interrupt */
-    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
-  }
-
-  /* Clear AWDEN, JAWDEN and AWDSGL bits */
-  hadc->Instance->CR1 &=  ~(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN | ADC_CR1_AWDEN);
-
-  /* Set the analog watchdog enable mode */
-  hadc->Instance->CR1 |= AnalogWDGConfig->WatchdogMode;
-
-  /* Set the high threshold */
-  hadc->Instance->HTR = AnalogWDGConfig->HighThreshold;
-
-  /* Set the low threshold */
-  hadc->Instance->LTR = AnalogWDGConfig->LowThreshold;
-
-  /* Clear the Analog watchdog channel select bits */
-  hadc->Instance->CR1 &= ~ADC_CR1_AWDCH;
-
-  /* Set the Analog watchdog channel */
-  hadc->Instance->CR1 |= (uint32_t)((uint16_t)(AnalogWDGConfig->Channel));
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Exported_Functions_Group4 ADC Peripheral State functions
- *  @brief   ADC Peripheral State functions
- *
-@verbatim
- ===============================================================================
-            ##### Peripheral State and errors functions #####
- ===============================================================================
-    [..]
-    This subsection provides functions allowing to
-      (+) Check the ADC state
-      (+) Check the ADC Error
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  return the ADC state
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @retval HAL state
-  */
-uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
-{
-  /* Return ADC state */
-  return hadc->State;
-}
-
-/**
-  * @brief  Return the ADC error code
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @retval ADC Error Code
-  */
-uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
-{
-  return hadc->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup ADC_Private_Functions ADC Private Functions
-  * @{
-  */
-
-/**
-  * @brief  Initializes the ADCx peripheral according to the specified parameters
-  *         in the ADC_InitStruct without initializing the ADC MSP.
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @retval None
-  */
-static void ADC_Init(ADC_HandleTypeDef* hadc)
-{
-  /* Set ADC parameters */
-  /* Set the ADC clock prescaler */
-  ADC->CCR &= ~(ADC_CCR_ADCPRE);
-  ADC->CCR |=  hadc->Init.ClockPrescaler;
-
-  /* Set ADC scan mode */
-  hadc->Instance->CR1 &= ~(ADC_CR1_SCAN);
-  hadc->Instance->CR1 |=  ADC_CR1_SCANCONV(hadc->Init.ScanConvMode);
-
-  /* Set ADC resolution */
-  hadc->Instance->CR1 &= ~(ADC_CR1_RES);
-  hadc->Instance->CR1 |=  hadc->Init.Resolution;
-
-  /* Set ADC data alignment */
-  hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN);
-  hadc->Instance->CR2 |= hadc->Init.DataAlign;
-
-  /* Enable external trigger if trigger selection is different of software  */
-  /* start.                                                                 */
-  /* Note: This configuration keeps the hardware feature of parameter       */
-  /*       ExternalTrigConvEdge "trigger edge none" equivalent to           */
-  /*       software start.                                                  */
-  if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
-  {
-    /* Select external trigger to start conversion */
-    hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
-    hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv;
-
-    /* Select external trigger polarity */
-    hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
-    hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge;
-  }
-  else
-  {
-    /* Reset the external trigger */
-    hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
-    hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
-  }
-
-  /* Enable or disable ADC continuous conversion mode */
-  hadc->Instance->CR2 &= ~(ADC_CR2_CONT);
-  hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode);
-
-  if(hadc->Init.DiscontinuousConvMode != DISABLE)
-  {
-    assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion));
-
-    /* Enable the selected ADC regular discontinuous mode */
-    hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN;
-
-    /* Set the number of channels to be converted in discontinuous mode */
-    hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM);
-    hadc->Instance->CR1 |=  ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion);
-  }
-  else
-  {
-    /* Disable the selected ADC regular discontinuous mode */
-    hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN);
-  }
-
-  /* Set ADC number of conversion */
-  hadc->Instance->SQR1 &= ~(ADC_SQR1_L);
-  hadc->Instance->SQR1 |=  ADC_SQR1(hadc->Init.NbrOfConversion);
-
-  /* Enable or disable ADC DMA continuous request */
-  hadc->Instance->CR2 &= ~(ADC_CR2_DDS);
-  hadc->Instance->CR2 |= ADC_CR2_DMAContReq(hadc->Init.DMAContinuousRequests);
-
-  /* Enable or disable ADC end of conversion selection */
-  hadc->Instance->CR2 &= ~(ADC_CR2_EOCS);
-  hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection);
-}
-
-/**
-  * @brief  DMA transfer complete callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
-{
-  /* Retrieve ADC handle corresponding to current DMA handle */
-  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  /* Update state machine on conversion status if not in error state */
-  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
-  {
-    /* Update ADC state machine */
-    SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
-
-    /* Determine whether any further conversion upcoming on group regular   */
-    /* by external trigger, continuous mode or scan sequence on going.      */
-    /* Note: On STM32F7, there is no independent flag of end of sequence.   */
-    /*       The test of scan sequence on going is done either with scan    */
-    /*       sequence disabled or with end of conversion flag set to        */
-    /*       of end of sequence.                                            */
-    if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&
-       (hadc->Init.ContinuousConvMode == DISABLE)            &&
-       (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
-        HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )
-    {
-      /* Disable ADC end of single conversion interrupt on group regular */
-      /* Note: Overrun interrupt was enabled with EOC interrupt in          */
-      /* HAL_ADC_Start_IT(), but is not disabled here because can be used   */
-      /* by overrun IRQ process below.                                      */
-      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
-
-      /* Set ADC state */
-      CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
-
-      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
-      {
-        SET_BIT(hadc->State, HAL_ADC_STATE_READY);
-      }
-    }
-
-    /* Conversion complete callback */
-    HAL_ADC_ConvCpltCallback(hadc);
-  }
-  else
-  {
-    /* Call DMA error callback */
-    hadc->DMA_Handle->XferErrorCallback(hdma);
-  }
-}
-
-/**
-  * @brief  DMA half transfer complete callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
-{
-  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  /* Conversion complete callback */
-  HAL_ADC_ConvHalfCpltCallback(hadc);
-}
-
-/**
-  * @brief  DMA error callback
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void ADC_DMAError(DMA_HandleTypeDef *hdma)
-{
-  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  hadc->State= HAL_ADC_STATE_ERROR_DMA;
-  /* Set ADC error code to DMA error */
-  hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
-  HAL_ADC_ErrorCallback(hadc);
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_ADC_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_adc_ex.c b/stmhal/hal/f7/src/stm32f7xx_hal_adc_ex.c
deleted file mode 100644
index cee4e1c554..0000000000
--- a/stmhal/hal/f7/src/stm32f7xx_hal_adc_ex.c
+++ /dev/null
@@ -1,1069 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_adc_ex.c
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   This file provides firmware functions to manage the following
-  *          functionalities of the ADC extension peripheral:
-  *           + Extended features functions
-  *
-  @verbatim
-  ==============================================================================
-                    ##### How to use this driver #####
-  ==============================================================================
-    [..]
-    (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():
-       (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()
-       (##) ADC pins configuration
-             (+++) Enable the clock for the ADC GPIOs using the following function:
-                   __HAL_RCC_GPIOx_CLK_ENABLE()
-             (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init()
-       (##) In case of using interrupts (e.g. HAL_ADC_Start_IT())
-             (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()
-             (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()
-             (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()
-      (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())
-             (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()
-             (+++) Configure and enable two DMA streams stream for managing data
-                 transfer from peripheral to memory (output stream)
-             (+++) Associate the initialized DMA handle to the ADC DMA handle
-                 using  __HAL_LINKDMA()
-             (+++) Configure the priority and enable the NVIC for the transfer complete
-                 interrupt on the two DMA Streams. The output stream should have higher
-                 priority than the input stream.
-     (#) Configure the ADC Prescaler, conversion resolution and data alignment
-         using the HAL_ADC_Init() function.
-
-     (#) Configure the ADC Injected channels group features, use HAL_ADC_Init()
-         and HAL_ADC_ConfigChannel() functions.
-
-     (#) Three operation modes are available within this driver :
-
-     *** Polling mode IO operation ***
-     =================================
-     [..]
-       (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart()
-       (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage
-           user can specify the value of timeout according to his end application
-       (+) To read the ADC converted values, use the HAL_ADCEx_InjectedGetValue() function.
-       (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop()
-
-     *** Interrupt mode IO operation ***
-     ===================================
-     [..]
-       (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_IT()
-       (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine
-       (+) At ADC end of conversion HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can
-            add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback
-       (+) In case of ADC Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can
-            add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback
-       (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_IT()
-
-
-     *** DMA mode IO operation ***
-     ==============================
-     [..]
-       (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_DMA(), at this stage the user specify the length
-           of data to be transferred at each end of conversion
-       (+) At The end of data transfer ba HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can
-            add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback
-       (+) In case of transfer Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can
-            add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback
-        (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_DMA()
-
-     *** Multi mode ADCs Regular channels configuration ***
-     ======================================================
-     [..]
-       (+) Select the Multi mode ADC regular channels features (dual or triple mode)
-          and configure the DMA mode using HAL_ADCEx_MultiModeConfigChannel() functions.
-       (+) Start the ADC peripheral using HAL_ADCEx_MultiModeStart_DMA(), at this stage the user specify the length
-           of data to be transferred at each end of conversion
-       (+) Read the ADCs converted values using the HAL_ADCEx_MultiModeGetValue() function.
-
-
-    @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup ADCEx ADCEx
-  * @brief ADC Extended driver modules
-  * @{
-  */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @addtogroup ADCEx_Private_Functions
-  * @{
-  */
-/* Private function prototypes -----------------------------------------------*/
-static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma);
-static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma);
-static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup ADCEx_Exported_Functions ADC Exported Functions
-  * @{
-  */
-
-/** @defgroup ADCEx_Exported_Functions_Group1  Extended features functions
-  *  @brief    Extended features functions
-  *
-@verbatim
- ===============================================================================
-                 ##### Extended features functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Start conversion of injected channel.
-      (+) Stop conversion of injected channel.
-      (+) Start multimode and enable DMA transfer.
-      (+) Stop multimode and disable DMA transfer.
-      (+) Get result of injected channel conversion.
-      (+) Get result of multimode conversion.
-      (+) Configure injected channels.
-      (+) Configure multimode.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables the selected ADC software start conversion of the injected channels.
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
-{
-  __IO uint32_t counter = 0;
-  uint32_t tmp1 = 0, tmp2 = 0;
-
-  /* Process locked */
-  __HAL_LOCK(hadc);
-
-  /* Enable the ADC peripheral */
-
-  /* Check if ADC peripheral is disabled in order to enable it and wait during
-     Tstab time the ADC's stabilization */
-  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
-  {
-    /* Enable the Peripheral */
-    __HAL_ADC_ENABLE(hadc);
-
-    /* Delay for ADC stabilization time */
-    /* Compute number of CPU cycles to wait for */
-    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
-    while(counter != 0)
-    {
-      counter--;
-    }
-  }
-
-  /* Start conversion if ADC is effectively enabled */
-  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
-  {
-    /* Set ADC state                                                          */
-    /* - Clear state bitfield related to injected group conversion results    */
-    /* - Set state bitfield related to injected operation                     */
-    ADC_STATE_CLR_SET(hadc->State,
-                      HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
-                      HAL_ADC_STATE_INJ_BUSY);
-
-    /* Check if a regular conversion is ongoing */
-    /* Note: On this device, there is no ADC error code fields related to     */
-    /*       conversions on group injected only. In case of conversion on     */
-    /*       going on group regular, no error code is reset.                  */
-    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
-    {
-      /* Reset ADC all error code fields */
-      ADC_CLEAR_ERRORCODE(hadc);
-    }
-
-    /* Process unlocked */
-    /* Unlock before starting ADC conversions: in case of potential           */
-    /* interruption, to let the process to ADC IRQ Handler.                   */
-    __HAL_UNLOCK(hadc);
-
-    /* Clear injected group conversion flag */
-    /* (To ensure of no unknown state from potential previous ADC operations) */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
-
-    /* Check if Multimode enabled */
-    if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
-    {
-      tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
-      tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
-      if(tmp1 && tmp2)
-      {
-        /* Enable the selected ADC software conversion for injected group */
-        hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
-      }
-    }
-    else
-    {
-      tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
-      tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
-      if((hadc->Instance == ADC1) && tmp1 && tmp2)
-      {
-        /* Enable the selected ADC software conversion for injected group */
-        hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
-      }
-    }
-  }
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enables the interrupt and starts ADC conversion of injected channels.
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  *
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
-{
-  __IO uint32_t counter = 0;
-  uint32_t tmp1 = 0, tmp2 = 0;
-
-  /* Process locked */
-  __HAL_LOCK(hadc);
-
-  /* Enable the ADC peripheral */
-
-  /* Check if ADC peripheral is disabled in order to enable it and wait during
-     Tstab time the ADC's stabilization */
-  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
-  {
-    /* Enable the Peripheral */
-    __HAL_ADC_ENABLE(hadc);
-
-    /* Delay for ADC stabilization time */
-    /* Compute number of CPU cycles to wait for */
-    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
-    while(counter != 0)
-    {
-      counter--;
-    }
-  }
-
-  /* Start conversion if ADC is effectively enabled */
-  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
-  {
-    /* Set ADC state                                                          */
-    /* - Clear state bitfield related to injected group conversion results    */
-    /* - Set state bitfield related to injected operation                     */
-    ADC_STATE_CLR_SET(hadc->State,
-                      HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
-                      HAL_ADC_STATE_INJ_BUSY);
-
-    /* Check if a regular conversion is ongoing */
-    /* Note: On this device, there is no ADC error code fields related to     */
-    /*       conversions on group injected only. In case of conversion on     */
-    /*       going on group regular, no error code is reset.                  */
-    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
-    {
-      /* Reset ADC all error code fields */
-      ADC_CLEAR_ERRORCODE(hadc);
-    }
-
-    /* Process unlocked */
-    /* Unlock before starting ADC conversions: in case of potential           */
-    /* interruption, to let the process to ADC IRQ Handler.                   */
-    __HAL_UNLOCK(hadc);
-
-    /* Clear injected group conversion flag */
-    /* (To ensure of no unknown state from potential previous ADC operations) */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
-
-    /* Enable end of conversion interrupt for injected channels */
-    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
-
-    /* Check if Multimode enabled */
-    if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
-    {
-      tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
-      tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
-      if(tmp1 && tmp2)
-      {
-        /* Enable the selected ADC software conversion for injected group */
-        hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
-      }
-    }
-    else
-    {
-      tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
-      tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
-      if((hadc->Instance == ADC1) && tmp1 && tmp2)
-      {
-        /* Enable the selected ADC software conversion for injected group */
-        hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
-      }
-    }
-  }
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stop conversion of injected channels. Disable ADC peripheral if
-  *         no regular conversion is on going.
-  * @note   If ADC must be disabled and if conversion is on going on
-  *         regular group, function HAL_ADC_Stop must be used to stop both
-  *         injected and regular groups, and disable the ADC.
-  * @note   If injected group mode auto-injection is enabled,
-  *         function HAL_ADC_Stop must be used.
-  * @note   In case of auto-injection mode, HAL_ADC_Stop must be used.
-  * @param  hadc: ADC handle
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
-  /* Process locked */
-  __HAL_LOCK(hadc);
-
-  /* Stop potential conversion and disable ADC peripheral                     */
-  /* Conditioned to:                                                          */
-  /* - No conversion on the other group (regular group) is intended to        */
-  /*   continue (injected and regular groups stop conversion and ADC disable  */
-  /*   are common)                                                            */
-  /* - In case of auto-injection mode, HAL_ADC_Stop must be used.             */
-  if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET)  &&
-     HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )
-  {
-    /* Stop potential conversion on going, on regular and injected groups */
-    /* Disable ADC peripheral */
-    __HAL_ADC_DISABLE(hadc);
-
-    /* Check if ADC is effectively disabled */
-    if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
-    {
-      /* Set ADC state */
-      ADC_STATE_CLR_SET(hadc->State,
-                        HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
-                        HAL_ADC_STATE_READY);
-    }
-  }
-  else
-  {
-    /* Update ADC state machine to error */
-    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
-    tmp_hal_status = HAL_ERROR;
-  }
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-
-  /* Return function status */
-  return tmp_hal_status;
-}
-
-/**
-  * @brief  Poll for injected conversion complete
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @param  Timeout: Timeout value in millisecond.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
-{
-  uint32_t tickstart = 0;
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  /* Check End of conversion flag */
-  while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)))
-  {
-    /* Check for the Timeout */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        hadc->State= HAL_ADC_STATE_TIMEOUT;
-        /* Process unlocked */
-        __HAL_UNLOCK(hadc);
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Clear injected group conversion flag */
-  __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC);
-
-  /* Update ADC state machine */
-  SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
-
-  /* Determine whether any further conversion upcoming on group injected      */
-  /* by external trigger, continuous mode or scan sequence on going.          */
-  /* Note: On STM32F7, there is no independent flag of end of sequence.       */
-  /*       The test of scan sequence on going is done either with scan        */
-  /*       sequence disabled or with end of conversion flag set to            */
-  /*       of end of sequence.                                                */
-  if(ADC_IS_SOFTWARE_START_INJECTED(hadc)                    &&
-     (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL)  ||
-      HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)    ) &&
-     (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
-      (ADC_IS_SOFTWARE_START_REGULAR(hadc)       &&
-      (hadc->Init.ContinuousConvMode == DISABLE)   )       )   )
-  {
-    /* Set ADC state */
-    CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
-
-    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
-    {
-      SET_BIT(hadc->State, HAL_ADC_STATE_READY);
-    }
-  }
-
-  /* Return ADC state */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stop conversion of injected channels, disable interruption of
-  *         end-of-conversion. Disable ADC peripheral if no regular conversion
-  *         is on going.
-  * @note   If ADC must be disabled and if conversion is on going on
-  *         regular group, function HAL_ADC_Stop must be used to stop both
-  *         injected and regular groups, and disable the ADC.
-  * @note   If injected group mode auto-injection is enabled,
-  *         function HAL_ADC_Stop must be used.
-  * @param  hadc: ADC handle
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
-  /* Process locked */
-  __HAL_LOCK(hadc);
-
-  /* Stop potential conversion and disable ADC peripheral                     */
-  /* Conditioned to:                                                          */
-  /* - No conversion on the other group (regular group) is intended to        */
-  /*   continue (injected and regular groups stop conversion and ADC disable  */
-  /*   are common)                                                            */
-  /* - In case of auto-injection mode, HAL_ADC_Stop must be used.             */
-  if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET)  &&
-     HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )
-  {
-    /* Stop potential conversion on going, on regular and injected groups */
-    /* Disable ADC peripheral */
-    __HAL_ADC_DISABLE(hadc);
-
-    /* Check if ADC is effectively disabled */
-    if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
-    {
-      /* Disable ADC end of conversion interrupt for injected channels */
-      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
-
-      /* Set ADC state */
-      ADC_STATE_CLR_SET(hadc->State,
-                        HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
-                        HAL_ADC_STATE_READY);
-    }
-  }
-  else
-  {
-    /* Update ADC state machine to error */
-    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
-    tmp_hal_status = HAL_ERROR;
-  }
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-
-  /* Return function status */
-  return tmp_hal_status;
-}
-
-/**
-  * @brief  Gets the converted value from data register of injected channel.
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @param  InjectedRank: the ADC injected rank.
-  *          This parameter can be one of the following values:
-  *            @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
-  *            @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
-  *            @arg ADC_INJECTED_RANK_3: Injected Channel3 selected
-  *            @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
-  * @retval None
-  */
-uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
-{
-  __IO uint32_t tmp = 0;
-
-  /* Check the parameters */
-  assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
-
-  /* Clear injected group conversion flag to have similar behaviour as        */
-  /* regular group: reading data register also clears end of conversion flag. */
-  __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
-
-  /* Return the selected ADC converted value */
-  switch(InjectedRank)
-  {
-    case ADC_INJECTED_RANK_4:
-    {
-      tmp =  hadc->Instance->JDR4;
-    }
-    break;
-    case ADC_INJECTED_RANK_3:
-    {
-      tmp =  hadc->Instance->JDR3;
-    }
-    break;
-    case ADC_INJECTED_RANK_2:
-    {
-      tmp =  hadc->Instance->JDR2;
-    }
-    break;
-    case ADC_INJECTED_RANK_1:
-    {
-      tmp =  hadc->Instance->JDR1;
-    }
-    break;
-    default:
-    break;
-  }
-  return tmp;
-}
-
-/**
-  * @brief  Enables ADC DMA request after last transfer (Multi-ADC mode) and enables ADC peripheral
-  *
-  * @note   Caution: This function must be used only with the ADC master.
-  *
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @param  pData:   Pointer to buffer in which transferred from ADC peripheral to memory will be stored.
-  * @param  Length:  The length of data to be transferred from ADC peripheral to memory.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
-{
-  __IO uint32_t counter = 0;
-
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
-  assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
-  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
-
-  /* Process locked */
-  __HAL_LOCK(hadc);
-
-  /* Check if ADC peripheral is disabled in order to enable it and wait during
-     Tstab time the ADC's stabilization */
-  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
-  {
-    /* Enable the Peripheral */
-    __HAL_ADC_ENABLE(hadc);
-
-    /* Delay for temperature sensor stabilization time */
-    /* Compute number of CPU cycles to wait for */
-    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
-    while(counter != 0)
-    {
-      counter--;
-    }
-  }
-
-  /* Start conversion if ADC is effectively enabled */
-  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
-  {
-    /* Set ADC state                                                          */
-    /* - Clear state bitfield related to regular group conversion results     */
-    /* - Set state bitfield related to regular group operation                */
-    ADC_STATE_CLR_SET(hadc->State,
-                      HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
-                      HAL_ADC_STATE_REG_BUSY);
-
-    /* If conversions on group regular are also triggering group injected,    */
-    /* update ADC state.                                                      */
-    if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
-    {
-      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
-    }
-
-    /* State machine update: Check if an injected conversion is ongoing */
-    if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
-    {
-      /* Reset ADC error code fields related to conversions on group regular */
-      CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
-    }
-    else
-    {
-      /* Reset ADC all error code fields */
-      ADC_CLEAR_ERRORCODE(hadc);
-    }
-
-    /* Process unlocked */
-    /* Unlock before starting ADC conversions: in case of potential           */
-    /* interruption, to let the process to ADC IRQ Handler.                   */
-    __HAL_UNLOCK(hadc);
-
-    /* Set the DMA transfer complete callback */
-    hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt;
-
-    /* Set the DMA half transfer complete callback */
-    hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt;
-
-    /* Set the DMA error callback */
-    hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ;
-
-    /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */
-    /* start (in case of SW start):                                           */
-
-    /* Clear regular group conversion flag and overrun flag */
-    /* (To ensure of no unknown state from potential previous ADC operations) */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
-
-    /* Enable ADC overrun interrupt */
-    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
-
-    if (hadc->Init.DMAContinuousRequests != DISABLE)
-    {
-      /* Enable the selected ADC DMA request after last transfer */
-      ADC->CCR |= ADC_CCR_DDS;
-    }
-    else
-    {
-      /* Disable the selected ADC EOC rising on each regular channel conversion */
-      ADC->CCR &= ~ADC_CCR_DDS;
-    }
-
-    /* Enable the DMA Stream */
-    HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&ADC->CDR, (uint32_t)pData, Length);
-
-    /* if no external trigger present enable software conversion of regular channels */
-    if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
-    {
-      /* Enable the selected ADC software conversion for regular group */
-      hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
-    }
-  }
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disables ADC DMA (multi-ADC mode) and disables ADC peripheral
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
-  /* Process locked */
-  __HAL_LOCK(hadc);
-
-  /* Stop potential conversion on going, on regular and injected groups */
-  /* Disable ADC peripheral */
-  __HAL_ADC_DISABLE(hadc);
-
-  /* Check if ADC is effectively disabled */
-  if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
-  {
-    /* Disable the selected ADC DMA mode for multimode */
-    ADC->CCR &= ~ADC_CCR_DDS;
-
-    /* Disable the DMA channel (in case of DMA in circular mode or stop while */
-    /* DMA transfer is on going)                                              */
-    tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
-
-    /* Disable ADC overrun interrupt */
-    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
-
-    /* Set ADC state */
-    ADC_STATE_CLR_SET(hadc->State,
-                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
-                      HAL_ADC_STATE_READY);
-  }
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-
-  /* Return function status */
-  return tmp_hal_status;
-}
-
-/**
-  * @brief  Returns the last ADC1, ADC2 and ADC3 regular conversions results
-  *         data in the selected multi mode.
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @retval The converted data value.
-  */
-uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
-{
-  /* Return the multi mode conversion value */
-  return ADC->CDR;
-}
-
-/**
-  * @brief  Injected conversion complete callback in non blocking mode
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @retval None
-  */
-__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_ADC_InjectedConvCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Configures for the selected ADC injected channel its corresponding
-  *         rank in the sequencer and its sample time.
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
-  *         the configuration information for the specified ADC.
-  * @param  sConfigInjected: ADC configuration structure for injected channel.
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
-{
-
-#ifdef USE_FULL_ASSERT
-  uint32_t tmp = 0;
-#endif /* USE_FULL_ASSERT  */
-
-  /* Check the parameters */
-  assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
-  assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
-  assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
-  assert_param(IS_ADC_EXT_INJEC_TRIG(sConfigInjected->ExternalTrigInjecConv));
-  assert_param(IS_ADC_INJECTED_LENGTH(sConfigInjected->InjectedNbrOfConversion));
-  assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
-  assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
-
-#ifdef USE_FULL_ASSERT
-  tmp = ADC_GET_RESOLUTION(hadc);
-  assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset));
-#endif /* USE_FULL_ASSERT  */
-
-  if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
-  {
-    assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
-  }
-
-  /* Process locked */
-  __HAL_LOCK(hadc);
-
-  /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
-  if (sConfigInjected->InjectedChannel > ADC_CHANNEL_9)
-  {
-    /* Clear the old sample time */
-    hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel);
-
-    /* Set the new sample time */
-    hadc->Instance->SMPR1 |= ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
-  }
-  else /* ADC_Channel include in ADC_Channel_[0..9] */
-  {
-    /* Clear the old sample time */
-    hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel);
-
-    /* Set the new sample time */
-    hadc->Instance->SMPR2 |= ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
-  }
-
-  /*---------------------------- ADCx JSQR Configuration -----------------*/
-  hadc->Instance->JSQR &= ~(ADC_JSQR_JL);
-  hadc->Instance->JSQR |=  ADC_SQR1(sConfigInjected->InjectedNbrOfConversion);
-
-  /* Rank configuration */
-
-  /* Clear the old SQx bits for the selected rank */
-  hadc->Instance->JSQR &= ~ADC_JSQR(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);
-
-  /* Set the SQx bits for the selected rank */
-  hadc->Instance->JSQR |= ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);
-
-  /* Enable external trigger if trigger selection is different of software  */
-  /* start.                                                                 */
-  /* Note: This configuration keeps the hardware feature of parameter       */
-  /*       ExternalTrigConvEdge "trigger edge none" equivalent to           */
-  /*       software start.                                                  */
-  if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
-  {
-    /* Select external trigger to start conversion */
-    hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
-    hadc->Instance->CR2 |=  sConfigInjected->ExternalTrigInjecConv;
-
-    /* Select external trigger polarity */
-    hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);
-    hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge;
-  }
-  else
-  {
-    /* Reset the external trigger */
-    hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
-    hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);
-  }
-
-  if (sConfigInjected->AutoInjectedConv != DISABLE)
-  {
-    /* Enable the selected ADC automatic injected group conversion */
-    hadc->Instance->CR1 |= ADC_CR1_JAUTO;
-  }
-  else
-  {
-    /* Disable the selected ADC automatic injected group conversion */
-    hadc->Instance->CR1 &= ~(ADC_CR1_JAUTO);
-  }
-
-  if (sConfigInjected->InjectedDiscontinuousConvMode != DISABLE)
-  {
-    /* Enable the selected ADC injected discontinuous mode */
-    hadc->Instance->CR1 |= ADC_CR1_JDISCEN;
-  }
-  else
-  {
-    /* Disable the selected ADC injected discontinuous mode */
-    hadc->Instance->CR1 &= ~(ADC_CR1_JDISCEN);
-  }
-
-  switch(sConfigInjected->InjectedRank)
-  {
-    case 1:
-      /* Set injected channel 1 offset */
-      hadc->Instance->JOFR1 &= ~(ADC_JOFR1_JOFFSET1);
-      hadc->Instance->JOFR1 |= sConfigInjected->InjectedOffset;
-      break;
-    case 2:
-      /* Set injected channel 2 offset */
-      hadc->Instance->JOFR2 &= ~(ADC_JOFR2_JOFFSET2);
-      hadc->Instance->JOFR2 |= sConfigInjected->InjectedOffset;
-      break;
-    case 3:
-      /* Set injected channel 3 offset */
-      hadc->Instance->JOFR3 &= ~(ADC_JOFR3_JOFFSET3);
-      hadc->Instance->JOFR3 |= sConfigInjected->InjectedOffset;
-      break;
-    default:
-      /* Set injected channel 4 offset */
-      hadc->Instance->JOFR4 &= ~(ADC_JOFR4_JOFFSET4);
-      hadc->Instance->JOFR4 |= sConfigInjected->InjectedOffset;
-      break;
-  }
-
-  /* if ADC1 Channel_18 is selected enable VBAT Channel */
-  if ((hadc->Instance == ADC1) && (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT))
-  {
-    /* Enable the VBAT channel*/
-    ADC->CCR |= ADC_CCR_VBATE;
-  }
-
-  /* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */
-  if ((hadc->Instance == ADC1) && ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)))
-  {
-    /* Enable the TSVREFE channel*/
-    ADC->CCR |= ADC_CCR_TSVREFE;
-  }
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the ADC multi-mode
-  * @param  hadc      : pointer to a ADC_HandleTypeDef structure that contains
-  *                     the configuration information for the specified ADC.
-  * @param  multimode : pointer to an ADC_MultiModeTypeDef structure that contains
-  *                     the configuration information for  multimode.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_MODE(multimode->Mode));
-  assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode));
-  assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
-
-  /* Process locked */
-  __HAL_LOCK(hadc);
-
-  /* Set ADC mode */
-  ADC->CCR &= ~(ADC_CCR_MULTI);
-  ADC->CCR |= multimode->Mode;
-
-  /* Set the ADC DMA access mode */
-  ADC->CCR &= ~(ADC_CCR_DMA);
-  ADC->CCR |= multimode->DMAAccessMode;
-
-  /* Set delay between two sampling phases */
-  ADC->CCR &= ~(ADC_CCR_DELAY);
-  ADC->CCR |= multimode->TwoSamplingDelay;
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-  /**
-  * @brief  DMA transfer complete callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma)
-{
-  /* Retrieve ADC handle corresponding to current DMA handle */
-  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  /* Update state machine on conversion status if not in error state */
-  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
-  {
-    /* Update ADC state machine */
-    SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
-
-    /* Determine whether any further conversion upcoming on group regular   */
-    /* by external trigger, continuous mode or scan sequence on going.      */
-    /* Note: On STM32F7, there is no independent flag of end of sequence.   */
-    /*       The test of scan sequence on going is done either with scan    */
-    /*       sequence disabled or with end of conversion flag set to        */
-    /*       of end of sequence.                                            */
-    if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&
-       (hadc->Init.ContinuousConvMode == DISABLE)            &&
-       (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
-        HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )
-    {
-      /* Disable ADC end of single conversion interrupt on group regular */
-      /* Note: Overrun interrupt was enabled with EOC interrupt in          */
-      /* HAL_ADC_Start_IT(), but is not disabled here because can be used   */
-      /* by overrun IRQ process below.                                      */
-      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
-
-      /* Set ADC state */
-      CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
-
-      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
-      {
-        SET_BIT(hadc->State, HAL_ADC_STATE_READY);
-      }
-    }
-
-    /* Conversion complete callback */
-    HAL_ADC_ConvCpltCallback(hadc);
-  }
-  else
-  {
-    /* Call DMA error callback */
-    hadc->DMA_Handle->XferErrorCallback(hdma);
-  }
-}
-
-/**
-  * @brief  DMA half transfer complete callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma)
-{
-    ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-    /* Conversion complete callback */
-    HAL_ADC_ConvHalfCpltCallback(hadc);
-}
-
-/**
-  * @brief  DMA error callback
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma)
-{
-    ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-    hadc->State= HAL_ADC_STATE_ERROR_DMA;
-    /* Set ADC error code to DMA error */
-    hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
-    HAL_ADC_ErrorCallback(hadc);
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_ADC_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_can.c b/stmhal/hal/f7/src/stm32f7xx_hal_can.c
deleted file mode 100644
index 100336e447..0000000000
--- a/stmhal/hal/f7/src/stm32f7xx_hal_can.c
+++ /dev/null
@@ -1,1412 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_can.c
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   CAN HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Controller Area Network (CAN) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions
-  *           + Peripheral State and Error functions
-  *
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-    [..]
-      (#) Enable the CAN controller interface clock using
-          __HAL_RCC_CAN1_CLK_ENABLE() for CAN1,  __HAL_RCC_CAN2_CLK_ENABLE() for CAN2
-         and  __HAL_RCC_CAN3_CLK_ENABLE() for CAN3
-      -@- In case you are using CAN2 only, you have to enable the CAN1 clock.
-
-      (#) CAN pins configuration
-        (++) Enable the clock for the CAN GPIOs using the following function:
-             __HAL_RCC_GPIOx_CLK_ENABLE()
-        (++) Connect and configure the involved CAN pins to AF9 using the
-              following function HAL_GPIO_Init()
-
-      (#) Initialize and configure the CAN using HAL_CAN_Init() function.
-
-      (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.
-
-      (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function.
-
-      (#) Receive a CAN frame using HAL_CAN_Receive() function.
-
-      (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function.
-
-     *** Polling mode IO operation ***
-     =================================
-     [..]
-       (+) Start the CAN peripheral transmission and wait the end of this operation
-           using HAL_CAN_Transmit(), at this stage user can specify the value of timeout
-           according to his end application
-       (+) Start the CAN peripheral reception and wait the end of this operation
-           using HAL_CAN_Receive(), at this stage user can specify the value of timeout
-           according to his end application
-
-     *** Interrupt mode IO operation ***
-     ===================================
-     [..]
-       (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()
-       (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT()
-       (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine
-       (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can
-            add his own code by customization of function pointer HAL_CAN_TxCpltCallback
-       (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can
-            add his own code by customization of function pointer HAL_CAN_ErrorCallback
-
-     *** CAN HAL driver macros list ***
-     =============================================
-     [..]
-       Below the list of most used macros in CAN HAL driver.
-
-      (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts
-      (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts
-      (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled
-      (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags
-      (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status
-
-     [..]
-      (@) You can refer to the CAN HAL driver header file for more useful macros
-
-  @endverbatim
-
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup CAN CAN
-  * @brief CAN driver modules
-  * @{
-  */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup CAN_Private_Constants
-  * @{
-  */
-#define CAN_TIMEOUT_VALUE  10
-/**
-  * @}
-  */
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup CAN_Private_Functions
-  * @{
-  */
-static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);
-static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup CAN_Exported_Functions CAN Exported Functions
-  * @{
-  */
-
-/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @brief    Initialization and Configuration functions
- *
-@verbatim
-  ==============================================================================
-              ##### Initialization and de-initialization functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Initialize and configure the CAN.
-      (+) De-initialize the CAN.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the CAN peripheral according to the specified
-  *         parameters in the CAN_InitStruct.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
-{
-  uint32_t InitStatus = CAN_INITSTATUS_FAILED;
-  uint32_t tickstart = 0;
-
-  /* Check CAN handle */
-  if(hcan == NULL)
-  {
-     return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
-  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM));
-  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM));
-  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM));
-  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART));
-  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM));
-  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP));
-  assert_param(IS_CAN_MODE(hcan->Init.Mode));
-  assert_param(IS_CAN_SJW(hcan->Init.SJW));
-  assert_param(IS_CAN_BS1(hcan->Init.BS1));
-  assert_param(IS_CAN_BS2(hcan->Init.BS2));
-  assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
-
-
-  if(hcan->State == HAL_CAN_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hcan->Lock = HAL_UNLOCKED;
-    /* Init the low level hardware */
-    HAL_CAN_MspInit(hcan);
-  }
-
-  /* Initialize the CAN state*/
-  hcan->State = HAL_CAN_STATE_BUSY;
-
-  /* Exit from sleep mode */
-  hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
-
-  /* Request initialisation */
-  hcan->Instance->MCR |= CAN_MCR_INRQ ;
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  /* Wait the acknowledge */
-  while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
-  {
-    if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE)
-    {
-      hcan->State= HAL_CAN_STATE_TIMEOUT;
-      /* Process unlocked */
-      __HAL_UNLOCK(hcan);
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Check acknowledge */
-  if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
-  {
-    /* Set the time triggered communication mode */
-    if (hcan->Init.TTCM == ENABLE)
-    {
-      hcan->Instance->MCR |= CAN_MCR_TTCM;
-    }
-    else
-    {
-      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM;
-    }
-
-    /* Set the automatic bus-off management */
-    if (hcan->Init.ABOM == ENABLE)
-    {
-      hcan->Instance->MCR |= CAN_MCR_ABOM;
-    }
-    else
-    {
-      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM;
-    }
-
-    /* Set the automatic wake-up mode */
-    if (hcan->Init.AWUM == ENABLE)
-    {
-      hcan->Instance->MCR |= CAN_MCR_AWUM;
-    }
-    else
-    {
-      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM;
-    }
-
-    /* Set the no automatic retransmission */
-    if (hcan->Init.NART == ENABLE)
-    {
-      hcan->Instance->MCR |= CAN_MCR_NART;
-    }
-    else
-    {
-      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART;
-    }
-
-    /* Set the receive FIFO locked mode */
-    if (hcan->Init.RFLM == ENABLE)
-    {
-      hcan->Instance->MCR |= CAN_MCR_RFLM;
-    }
-    else
-    {
-      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM;
-    }
-
-    /* Set the transmit FIFO priority */
-    if (hcan->Init.TXFP == ENABLE)
-    {
-      hcan->Instance->MCR |= CAN_MCR_TXFP;
-    }
-    else
-    {
-      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP;
-    }
-
-    /* Set the bit timing register */
-    hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \
-                ((uint32_t)hcan->Init.SJW) | \
-                ((uint32_t)hcan->Init.BS1) | \
-                ((uint32_t)hcan->Init.BS2) | \
-                ((uint32_t)hcan->Init.Prescaler - 1);
-
-    /* Request leave initialisation */
-    hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ;
-
-    /* Get tick */
-    tickstart = HAL_GetTick();
-
-    /* Wait the acknowledge */
-    while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
-    {
-      if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE)
-      {
-        hcan->State= HAL_CAN_STATE_TIMEOUT;
-        /* Process unlocked */
-        __HAL_UNLOCK(hcan);
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Check acknowledged */
-    if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
-    {
-      InitStatus = CAN_INITSTATUS_SUCCESS;
-    }
-  }
-
-  if(InitStatus == CAN_INITSTATUS_SUCCESS)
-  {
-    /* Set CAN error code to none */
-    hcan->ErrorCode = HAL_CAN_ERROR_NONE;
-
-    /* Initialize the CAN state */
-    hcan->State = HAL_CAN_STATE_READY;
-
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Initialize the CAN state */
-    hcan->State = HAL_CAN_STATE_ERROR;
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Configures the CAN reception filter according to the specified
-  *         parameters in the CAN_FilterInitStruct.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @param  sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that
-  *         contains the filter configuration information.
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)
-{
-  uint32_t filternbrbitpos = 0;
-  CAN_TypeDef *can_ip;
-
-  /* Check the parameters */
-  assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
-  assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
-  assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
-  assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
-  assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
-  assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber));
-
-  filternbrbitpos = ((uint32_t)1) << sFilterConfig->FilterNumber;
-#if defined (CAN3)
-  /* Check the CAN instance */
-  if(hcan->Instance == CAN3)
-  {
-    can_ip = CAN3;
-  }
-  else
-  {
-    can_ip = CAN1;
-  }
-#else
-  can_ip = CAN1;
-#endif
-
-  /* Initialisation mode for the filter */
-  can_ip->FMR |= (uint32_t)CAN_FMR_FINIT;
-
-#if defined (CAN2)
-  /* Select the start slave bank */
-  can_ip->FMR &= ~((uint32_t)CAN_FMR_CAN2SB);
-  can_ip->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8);
-#endif
-
-  /* Filter Deactivation */
-  can_ip->FA1R &= ~(uint32_t)filternbrbitpos;
-
-  /* Filter Scale */
-  if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
-  {
-    /* 16-bit scale for the filter */
-    can_ip->FS1R &= ~(uint32_t)filternbrbitpos;
-
-    /* First 16-bit identifier and First 16-bit mask */
-    /* Or First 16-bit identifier and Second 16-bit identifier */
-    can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
-     ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16) |
-      (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
-
-    /* Second 16-bit identifier and Second 16-bit mask */
-    /* Or Third 16-bit identifier and Fourth 16-bit identifier */
-    can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
-     ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |
-      (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh);
-  }
-
-  if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
-  {
-    /* 32-bit scale for the filter */
-    can_ip->FS1R |= filternbrbitpos;
-
-    /* 32-bit identifier or First 32-bit identifier */
-    can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
-     ((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16) |
-      (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
-
-    /* 32-bit mask or Second 32-bit identifier */
-    can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
-     ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |
-      (0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow);
-  }
-
-  /* Filter Mode */
-  if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
-  {
-    /*Id/Mask mode for the filter*/
-    can_ip->FM1R &= ~(uint32_t)filternbrbitpos;
-  }
-  else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
-  {
-    /*Identifier list mode for the filter*/
-    can_ip->FM1R |= (uint32_t)filternbrbitpos;
-  }
-
-  /* Filter FIFO assignment */
-  if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
-  {
-    /* FIFO 0 assignation for the filter */
-    can_ip->FFA1R &= ~(uint32_t)filternbrbitpos;
-  }
-
-  if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1)
-  {
-    /* FIFO 1 assignation for the filter */
-    can_ip->FFA1R |= (uint32_t)filternbrbitpos;
-  }
-
-  /* Filter activation */
-  if (sFilterConfig->FilterActivation == ENABLE)
-  {
-    can_ip->FA1R |= filternbrbitpos;
-  }
-
-  /* Leave the initialisation mode for the filter */
-  can_ip->FMR &= ~((uint32_t)CAN_FMR_FINIT);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deinitializes the CANx peripheral registers to their default reset values.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)
-{
-  /* Check CAN handle */
-  if(hcan == NULL)
-  {
-     return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
-
-  /* Change CAN state */
-  hcan->State = HAL_CAN_STATE_BUSY;
-
-  /* DeInit the low level hardware */
-  HAL_CAN_MspDeInit(hcan);
-
-  /* Change CAN state */
-  hcan->State = HAL_CAN_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hcan);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the CAN MSP.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval None
-  */
-__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcan);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_CAN_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes the CAN MSP.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval None
-  */
-__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcan);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_CAN_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_Exported_Functions_Group2 IO operation functions
- *  @brief    IO operation functions
- *
-@verbatim
-  ==============================================================================
-                      ##### IO operation functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Transmit a CAN frame message.
-      (+) Receive a CAN frame message.
-      (+) Enter CAN peripheral in sleep mode.
-      (+) Wake up the CAN peripheral from sleep mode.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initiates and transmits a CAN frame message.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @param  Timeout: Specify Timeout value
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
-{
-  uint32_t  transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
-  uint32_t tickstart = 0;
-
-  /* Check the parameters */
-  assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
-  assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
-  assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
-
-  if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
-     ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
-     ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
-  {
-    /* Process locked */
-    __HAL_LOCK(hcan);
-
-    if(hcan->State == HAL_CAN_STATE_BUSY_RX)
-    {
-      /* Change CAN state */
-      hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      /* Change CAN state */
-      hcan->State = HAL_CAN_STATE_BUSY_TX;
-    }
-
-    /* Select one empty transmit mailbox */
-    if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
-    {
-      transmitmailbox = CAN_TXMAILBOX_0;
-    }
-    else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
-    {
-      transmitmailbox = CAN_TXMAILBOX_1;
-    }
-    else
-    {
-      transmitmailbox = CAN_TXMAILBOX_2;
-    }
-
-    /* Set up the Id */
-    hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
-    if (hcan->pTxMsg->IDE == CAN_ID_STD)
-    {
-      assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
-      hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \
-                                                  hcan->pTxMsg->RTR);
-    }
-    else
-    {
-      assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
-      hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \
-                                                  hcan->pTxMsg->IDE | \
-                                                  hcan->pTxMsg->RTR);
-    }
-
-    /* Set up the DLC */
-    hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;
-    hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U;
-    hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
-
-    /* Set up the data field */
-    hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) |
-                                             ((uint32_t)hcan->pTxMsg->Data[2] << 16) |
-                                             ((uint32_t)hcan->pTxMsg->Data[1] << 8) |
-                                             ((uint32_t)hcan->pTxMsg->Data[0]));
-    hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) |
-                                             ((uint32_t)hcan->pTxMsg->Data[6] << 16) |
-                                             ((uint32_t)hcan->pTxMsg->Data[5] << 8) |
-                                             ((uint32_t)hcan->pTxMsg->Data[4]));
-    /* Request transmission */
-    hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
-
-    /* Get tick */
-    tickstart = HAL_GetTick();
-
-    /* Check End of transmission flag */
-    while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))
-    {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-       {
-         hcan->State = HAL_CAN_STATE_TIMEOUT;
-         /* Process unlocked */
-         __HAL_UNLOCK(hcan);
-         return HAL_TIMEOUT;
-        }
-      }
-    }
-    if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
-    {
-      /* Change CAN state */
-      hcan->State = HAL_CAN_STATE_BUSY_RX;
-    }
-    else
-    {
-      /* Change CAN state */
-      hcan->State = HAL_CAN_STATE_READY;
-    }
-
-    /* Process unlocked */
-    __HAL_UNLOCK(hcan);
-
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_ERROR;
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Initiates and transmits a CAN frame message.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
-{
-  uint32_t  transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
-
-  /* Check the parameters */
-  assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
-  assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
-  assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
-
-  if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
-     ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
-     ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcan);
-
-    /* Select one empty transmit mailbox */
-    if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
-    {
-      transmitmailbox = CAN_TXMAILBOX_0;
-    }
-    else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
-    {
-      transmitmailbox = CAN_TXMAILBOX_1;
-    }
-    else
-    {
-      transmitmailbox = CAN_TXMAILBOX_2;
-    }
-
-    /* Set up the Id */
-    hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
-    if(hcan->pTxMsg->IDE == CAN_ID_STD)
-    {
-      assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
-      hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \
-                                                hcan->pTxMsg->RTR);
-    }
-    else
-    {
-      assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
-      hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \
-                                                hcan->pTxMsg->IDE | \
-                                                hcan->pTxMsg->RTR);
-    }
-
-    /* Set up the DLC */
-    hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;
-    hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U;
-    hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
-
-    /* Set up the data field */
-    hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) |
-                                           ((uint32_t)hcan->pTxMsg->Data[2] << 16) |
-                                           ((uint32_t)hcan->pTxMsg->Data[1] << 8) |
-                                           ((uint32_t)hcan->pTxMsg->Data[0]));
-    hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) |
-                                           ((uint32_t)hcan->pTxMsg->Data[6] << 16) |
-                                           ((uint32_t)hcan->pTxMsg->Data[5] << 8) |
-                                           ((uint32_t)hcan->pTxMsg->Data[4]));
-
-    if(hcan->State == HAL_CAN_STATE_BUSY_RX)
-    {
-      /* Change CAN state */
-      hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      /* Change CAN state */
-      hcan->State = HAL_CAN_STATE_BUSY_TX;
-    }
-
-    /* Set CAN error code to none */
-    hcan->ErrorCode = HAL_CAN_ERROR_NONE;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcan);
-
-    /* Enable Error warning, Error passive, Bus-off,
-       Last error and Error Interrupts */
-    __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
-                              CAN_IT_EPV |
-                              CAN_IT_BOF |
-                              CAN_IT_LEC |
-                              CAN_IT_ERR |
-							  CAN_IT_TME);
-
-    /* Request transmission */
-    hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
-  }
-  else
-  {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_ERROR;
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Receives a correct CAN frame.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @param  FIFONumber: FIFO Number value
-  * @param  Timeout: Specify Timeout value
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
-{
-  uint32_t tickstart = 0;
-
-  /* Check the parameters */
-  assert_param(IS_CAN_FIFO(FIFONumber));
-
-  /* Process locked */
-  __HAL_LOCK(hcan);
-
-  if(hcan->State == HAL_CAN_STATE_BUSY_TX)
-  {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
-  }
-  else
-  {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_BUSY_RX;
-  }
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  /* Check pending message */
-  while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0)
-  {
-    /* Check for the Timeout */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        hcan->State = HAL_CAN_STATE_TIMEOUT;
-        /* Process unlocked */
-        __HAL_UNLOCK(hcan);
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Get the Id */
-  hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
-  if (hcan->pRxMsg->IDE == CAN_ID_STD)
-  {
-    hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21);
-  }
-  else
-  {
-    hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3);
-  }
-
-  hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
-  /* Get the DLC */
-  hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
-  /* Get the FMI */
-  hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8);
-  /* Get the data field */
-  hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
-  hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8);
-  hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16);
-  hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24);
-  hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
-  hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8);
-  hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16);
-  hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24);
-
-  /* Release the FIFO */
-  if(FIFONumber == CAN_FIFO0)
-  {
-    /* Release FIFO0 */
-    __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
-  }
-  else /* FIFONumber == CAN_FIFO1 */
-  {
-    /* Release FIFO1 */
-    __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
-  }
-
-  if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
-  {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_BUSY_TX;
-  }
-  else
-  {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_READY;
-  }
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hcan);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Receives a correct CAN frame.
-  * @param  hcan:       Pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @param  FIFONumber: Specify the FIFO number
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
-{
-  uint32_t tmp = 0;
-
-  /* Check the parameters */
-  assert_param(IS_CAN_FIFO(FIFONumber));
-
-  tmp = hcan->State;
-  if((tmp == HAL_CAN_STATE_READY) || (tmp == HAL_CAN_STATE_BUSY_TX))
-  {
-    /* Process locked */
-    __HAL_LOCK(hcan);
-
-    if(hcan->State == HAL_CAN_STATE_BUSY_TX)
-    {
-      /* Change CAN state */
-      hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      /* Change CAN state */
-      hcan->State = HAL_CAN_STATE_BUSY_RX;
-    }
-
-    /* Set CAN error code to none */
-    hcan->ErrorCode = HAL_CAN_ERROR_NONE;
-
-    /* Enable Error warning, Error passive, Bus-off,
-       Last error and Error Interrupts */
-    __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
-                              CAN_IT_EPV |
-                              CAN_IT_BOF |
-                              CAN_IT_LEC |
-                              CAN_IT_ERR);
-
-    /* Process unlocked */
-    __HAL_UNLOCK(hcan);
-
-    if(FIFONumber == CAN_FIFO0)
-    {
-      /* Enable FIFO 0 message pending Interrupt */
-      __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP0);
-    }
-    else
-    {
-      /* Enable FIFO 1 message pending Interrupt */
-      __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP1);
-    }
-
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enters the Sleep (low power) mode.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
-{
-  uint32_t tickstart = 0;
-
-  /* Process locked */
-  __HAL_LOCK(hcan);
-
-  /* Change CAN state */
-  hcan->State = HAL_CAN_STATE_BUSY;
-
-  /* Request Sleep mode */
-   hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
-
-  /* Sleep mode status */
-  if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
-  {
-    /* Process unlocked */
-    __HAL_UNLOCK(hcan);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  /* Wait the acknowledge */
-  while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
-  {
-    if((HAL_GetTick()  - tickstart) > CAN_TIMEOUT_VALUE)
-    {
-      hcan->State = HAL_CAN_STATE_TIMEOUT;
-      /* Process unlocked */
-      __HAL_UNLOCK(hcan);
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Change CAN state */
-  hcan->State = HAL_CAN_STATE_READY;
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hcan);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral
-  *         is in the normal mode.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
-{
-  uint32_t tickstart = 0;
-
-  /* Process locked */
-  __HAL_LOCK(hcan);
-
-  /* Change CAN state */
-  hcan->State = HAL_CAN_STATE_BUSY;
-
-  /* Wake up request */
-  hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  /* Sleep mode status */
-  while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
-  {
-    if((HAL_GetTick()  - tickstart) > CAN_TIMEOUT_VALUE)
-    {
-      hcan->State= HAL_CAN_STATE_TIMEOUT;
-      /* Process unlocked */
-      __HAL_UNLOCK(hcan);
-      return HAL_TIMEOUT;
-    }
-  }
-  if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
-  {
-    /* Process unlocked */
-    __HAL_UNLOCK(hcan);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-
-  /* Change CAN state */
-  hcan->State = HAL_CAN_STATE_READY;
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hcan);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handles CAN interrupt request
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval None
-  */
-void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
-{
-  uint32_t tmp1 = 0, tmp2 = 0, tmp3 = 0;
-
-  /* Check End of transmission flag */
-  if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))
-  {
-    tmp1 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0);
-    tmp2 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1);
-    tmp3 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2);
-    if(tmp1 || tmp2 || tmp3)
-    {
-      /* Call transmit function */
-      CAN_Transmit_IT(hcan);
-    }
-  }
-
-  tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0);
-  tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0);
-  /* Check End of reception flag for FIFO0 */
-  if((tmp1 != 0) && tmp2)
-  {
-    /* Call receive function */
-    CAN_Receive_IT(hcan, CAN_FIFO0);
-  }
-
-  tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1);
-  tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1);
-  /* Check End of reception flag for FIFO1 */
-  if((tmp1 != 0) && tmp2)
-  {
-    /* Call receive function */
-    CAN_Receive_IT(hcan, CAN_FIFO1);
-  }
-
-  tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG);
-  tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG);
-  tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
-  /* Check Error Warning Flag */
-  if(tmp1 && tmp2 && tmp3)
-  {
-    /* Set CAN error code to EWG error */
-    hcan->ErrorCode |= HAL_CAN_ERROR_EWG;
-  }
-
-  tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV);
-  tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV);
-  tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
-  /* Check Error Passive Flag */
-  if(tmp1 && tmp2 && tmp3)
-  {
-    /* Set CAN error code to EPV error */
-    hcan->ErrorCode |= HAL_CAN_ERROR_EPV;
-  }
-
-  tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF);
-  tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF);
-  tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
-  /* Check Bus-Off Flag */
-  if(tmp1 && tmp2 && tmp3)
-  {
-    /* Set CAN error code to BOF error */
-    hcan->ErrorCode |= HAL_CAN_ERROR_BOF;
-  }
-
-  tmp1 = HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC);
-  tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC);
-  tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
-  /* Check Last error code Flag */
-  if((!tmp1) && tmp2 && tmp3)
-  {
-    tmp1 = (hcan->Instance->ESR) & CAN_ESR_LEC;
-    switch(tmp1)
-    {
-      case(CAN_ESR_LEC_0):
-          /* Set CAN error code to STF error */
-          hcan->ErrorCode |= HAL_CAN_ERROR_STF;
-          break;
-      case(CAN_ESR_LEC_1):
-          /* Set CAN error code to FOR error */
-          hcan->ErrorCode |= HAL_CAN_ERROR_FOR;
-          break;
-      case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
-          /* Set CAN error code to ACK error */
-          hcan->ErrorCode |= HAL_CAN_ERROR_ACK;
-          break;
-      case(CAN_ESR_LEC_2):
-          /* Set CAN error code to BR error */
-          hcan->ErrorCode |= HAL_CAN_ERROR_BR;
-          break;
-      case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
-          /* Set CAN error code to BD error */
-          hcan->ErrorCode |= HAL_CAN_ERROR_BD;
-          break;
-      case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
-          /* Set CAN error code to CRC error */
-          hcan->ErrorCode |= HAL_CAN_ERROR_CRC;
-          break;
-      default:
-          break;
-    }
-
-    /* Clear Last error code Flag */
-    hcan->Instance->ESR &= ~(CAN_ESR_LEC);
-  }
-
-  /* Call the Error call Back in case of Errors */
-  if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)
-  {
-    /* Clear ERRI Flag */
-    hcan->Instance->MSR = CAN_MSR_ERRI;
-    /* Set the CAN state ready to be able to start again the process */
-    hcan->State = HAL_CAN_STATE_READY;
-    /* Call Error callback function */
-    HAL_CAN_ErrorCallback(hcan);
-  }
-}
-
-/**
-  * @brief  Transmission  complete callback in non blocking mode
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval None
-  */
-__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcan);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_CAN_TxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Transmission  complete callback in non blocking mode
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval None
-  */
-__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcan);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_CAN_RxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Error CAN callback.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval None
-  */
-__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcan);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_CAN_ErrorCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
- *  @brief   CAN Peripheral State functions
- *
-@verbatim
-  ==============================================================================
-            ##### Peripheral State and Error functions #####
-  ==============================================================================
-    [..]
-    This subsection provides functions allowing to :
-      (+) Check the CAN state.
-      (+) Check CAN Errors detected during interrupt process
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  return the CAN state
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval HAL state
-  */
-HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan)
-{
-  /* Return CAN state */
-  return hcan->State;
-}
-
-/**
-  * @brief  Return the CAN error code
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval CAN Error Code
-  */
-uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
-{
-  return hcan->ErrorCode;
-}
-
-/**
-  * @}
-  */
-/**
-  * @brief  Initiates and transmits a CAN frame message.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
-{
-  /* Disable Transmit mailbox empty Interrupt */
-  __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME);
-
-  if(hcan->State == HAL_CAN_STATE_BUSY_TX)
-  {
-    /* Disable Error warning, Error passive, Bus-off, Last error code
-       and Error Interrupts */
-	__HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
-                               CAN_IT_EPV |
-                               CAN_IT_BOF |
-                               CAN_IT_LEC |
-                               CAN_IT_ERR );
-  }
-
-  if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
-  {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_BUSY_RX;
-  }
-  else
-  {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_READY;
-  }
-
-  /* Transmission complete callback */
-  HAL_CAN_TxCpltCallback(hcan);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Receives a correct CAN frame.
-  * @param  hcan:       Pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @param  FIFONumber: Specify the FIFO number
-  * @retval HAL status
-  * @retval None
-  */
-static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
-{
-  /* Get the Id */
-  hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
-  if (hcan->pRxMsg->IDE == CAN_ID_STD)
-  {
-    hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21);
-  }
-  else
-  {
-    hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3);
-  }
-
-  hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
-  /* Get the DLC */
-  hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
-  /* Get the FMI */
-  hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8);
-  /* Get the data field */
-  hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
-  hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8);
-  hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16);
-  hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24);
-  hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
-  hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8);
-  hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16);
-  hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24);
-  /* Release the FIFO */
-  /* Release FIFO0 */
-  if (FIFONumber == CAN_FIFO0)
-  {
-    __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
-
-    /* Disable FIFO 0 message pending Interrupt */
-    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP0);
-  }
-  /* Release FIFO1 */
-  else /* FIFONumber == CAN_FIFO1 */
-  {
-    __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
-
-    /* Disable FIFO 1 message pending Interrupt */
-    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP1);
-  }
-
-  if(hcan->State == HAL_CAN_STATE_BUSY_RX)
-  {
-    /* Disable Error warning, Error passive, Bus-off, Last error code
-       and Error Interrupts */
-	__HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
-                               CAN_IT_EPV |
-                               CAN_IT_BOF |
-                               CAN_IT_LEC |
-                               CAN_IT_ERR);
-  }
-
-  if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
-  {
-    /* Disable CAN state */
-    hcan->State = HAL_CAN_STATE_BUSY_TX;
-  }
-  else
-  {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_READY;
-  }
-
-  /* Receive complete callback */
-  HAL_CAN_RxCpltCallback(hcan);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_CAN_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_cortex.c b/stmhal/hal/f7/src/stm32f7xx_hal_cortex.c
deleted file mode 100644
index b7dd19ad57..0000000000
--- a/stmhal/hal/f7/src/stm32f7xx_hal_cortex.c
+++ /dev/null
@@ -1,523 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_cortex.c
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   CORTEX HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the CORTEX:
-  *           + Initialization and de-initialization functions
-  *           + Peripheral Control functions
-  *
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-
-    [..]
-    *** How to configure Interrupts using CORTEX HAL driver ***
-    ===========================================================
-    [..]
-    This section provides functions allowing to configure the NVIC interrupts (IRQ).
-    The Cortex-M4 exceptions are managed by CMSIS functions.
-
-    (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
-        function according to the following table.
-    (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
-    (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
-    (#) please refer to programming manual for details in how to configure priority.
-
-     -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
-         The pending IRQ priority will be managed only by the sub priority.
-
-     -@- IRQ priority order (sorted by highest to lowest priority):
-        (+@) Lowest preemption priority
-        (+@) Lowest sub priority
-        (+@) Lowest hardware priority (IRQ number)
-
-    [..]
-    *** How to configure Systick using CORTEX HAL driver ***
-    ========================================================
-    [..]
-    Setup SysTick Timer for time base.
-
-   (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
-       is a CMSIS function that:
-        (++) Configures the SysTick Reload register with value passed as function parameter.
-        (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
-        (++) Resets the SysTick Counter register.
-        (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
-        (++) Enables the SysTick Interrupt.
-        (++) Starts the SysTick Counter.
-
-   (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
-       __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
-       HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
-       inside the stm32f7xx_hal_cortex.h file.
-
-   (+) You can change the SysTick IRQ priority by calling the
-       HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
-       call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
-
-   (+) To adjust the SysTick time base, use the following formula:
-
-       Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
-       (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
-       (++) Reload Value should not exceed 0xFFFFFF
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup CORTEX CORTEX
-  * @brief CORTEX HAL module driver
-  * @{
-  */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
-  * @{
-  */
-
-
-/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @brief    Initialization and Configuration functions
- *
-@verbatim
-  ==============================================================================
-              ##### Initialization and de-initialization functions #####
-  ==============================================================================
-    [..]
-      This section provides the CORTEX HAL driver functions allowing to configure Interrupts
-      Systick functionalities
-
-@endverbatim
-  * @{
-  */
-
-
-/**
-  * @brief  Sets the priority grouping field (preemption priority and subpriority)
-  *         using the required unlock sequence.
-  * @param  PriorityGroup: The priority grouping bits length.
-  *         This parameter can be one of the following values:
-  *         @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
-  *                                    4 bits for subpriority
-  *         @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
-  *                                    3 bits for subpriority
-  *         @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
-  *                                    2 bits for subpriority
-  *         @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
-  *                                    1 bits for subpriority
-  *         @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
-  *                                    0 bits for subpriority
-  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
-  *         The pending IRQ priority will be managed only by the subpriority.
-  * @retval None
-  */
-void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
-
-  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
-  NVIC_SetPriorityGrouping(PriorityGroup);
-}
-
-/**
-  * @brief  Sets the priority of an interrupt.
-  * @param  IRQn: External interrupt number.
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
-  * @param  PreemptPriority: The preemption priority for the IRQn channel.
-  *         This parameter can be a value between 0 and 15
-  *         A lower priority value indicates a higher priority
-  * @param  SubPriority: the subpriority level for the IRQ channel.
-  *         This parameter can be a value between 0 and 15
-  *         A lower priority value indicates a higher priority.
-  * @retval None
-  */
-void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t prioritygroup = 0x00;
-
-  /* Check the parameters */
-  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
-  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
-
-  prioritygroup = NVIC_GetPriorityGrouping();
-
-  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
-}
-
-/**
-  * @brief  Enables a device specific interrupt in the NVIC interrupt controller.
-  * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
-  *         function should be called before.
-  * @param  IRQn External interrupt number.
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
-  * @retval None
-  */
-void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
-  /* Enable interrupt */
-  NVIC_EnableIRQ(IRQn);
-}
-
-/**
-  * @brief  Disables a device specific interrupt in the NVIC interrupt controller.
-  * @param  IRQn External interrupt number.
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
-  * @retval None
-  */
-void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
-  /* Disable interrupt */
-  NVIC_DisableIRQ(IRQn);
-}
-
-/**
-  * @brief  Initiates a system reset request to reset the MCU.
-  * @retval None
-  */
-void HAL_NVIC_SystemReset(void)
-{
-  /* System Reset */
-  NVIC_SystemReset();
-}
-
-/**
-  * @brief  Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-  *         Counter is in free running mode to generate periodic interrupts.
-  * @param  TicksNumb: Specifies the ticks Number of ticks between two interrupts.
-  * @retval status:  - 0  Function succeeded.
-  *                  - 1  Function failed.
-  */
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
-{
-   return SysTick_Config(TicksNumb);
-}
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
- *  @brief   Cortex control functions
- *
-@verbatim
-  ==============================================================================
-                      ##### Peripheral Control functions #####
-  ==============================================================================
-    [..]
-      This subsection provides a set of functions allowing to control the CORTEX
-      (NVIC, SYSTICK, MPU) functionalities.
-
-
-@endverbatim
-  * @{
-  */
-
-#if (__MPU_PRESENT == 1)
-/**
-  * @brief  Disables the MPU
-  * @retval None
-  */
-void HAL_MPU_Disable(void)
-{
-  /* Make sure outstanding transfers are done */
-  __DMB();
-
-  /* Disable fault exceptions */
-  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
-
-  /* Disable the MPU and clear the control register*/
-  MPU->CTRL = 0;
-}
-
-/**
-  * @brief  Enables the MPU
-  * @param  MPU_Control: Specifies the control mode of the MPU during hard fault,
-  *          NMI, FAULTMASK and privileged access to the default memory
-  *          This parameter can be one of the following values:
-  *            @arg MPU_HFNMI_PRIVDEF_NONE
-  *            @arg MPU_HARDFAULT_NMI
-  *            @arg MPU_PRIVILEGED_DEFAULT
-  *            @arg MPU_HFNMI_PRIVDEF
-  * @retval None
-  */
-void HAL_MPU_Enable(uint32_t MPU_Control)
-{
-  /* Enable the MPU */
-  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
-
-  /* Enable fault exceptions */
-  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
-
-  /* Ensure MPU setting take effects */
-  __DSB();
-  __ISB();
-}
-
-/**
-  * @brief  Initializes and configures the Region and the memory to be protected.
-  * @param  MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
-  *                the initialization and configuration information.
-  * @retval None
-  */
-void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
-{
-  /* Check the parameters */
-  assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
-  assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
-
-  /* Set the Region number */
-  MPU->RNR = MPU_Init->Number;
-
-  if ((MPU_Init->Enable) != RESET)
-  {
-    /* Check the parameters */
-    assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
-    assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
-    assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
-    assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
-    assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
-    assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
-    assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
-    assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
-
-    MPU->RBAR = MPU_Init->BaseAddress;
-    MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
-                ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
-                ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
-                ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
-                ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
-                ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
-                ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
-                ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
-                ((uint32_t)MPU_Init->Enable                  << MPU_RASR_ENABLE_Pos);
-  }
-  else
-  {
-    MPU->RBAR = 0x00;
-    MPU->RASR = 0x00;
-  }
-}
-#endif /* __MPU_PRESENT */
-
-/**
-  * @brief  Gets the priority grouping field from the NVIC Interrupt Controller.
-  * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
-  */
-uint32_t HAL_NVIC_GetPriorityGrouping(void)
-{
-  /* Get the PRIGROUP[10:8] field value */
-  return NVIC_GetPriorityGrouping();
-}
-
-/**
-  * @brief  Gets the priority of an interrupt.
-  * @param  IRQn: External interrupt number.
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
-  * @param   PriorityGroup: the priority grouping bits length.
-  *         This parameter can be one of the following values:
-  *           @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
-  *                                      4 bits for subpriority
-  *           @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
-  *                                      3 bits for subpriority
-  *           @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
-  *                                      2 bits for subpriority
-  *           @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
-  *                                      1 bits for subpriority
-  *           @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
-  *                                      0 bits for subpriority
-  * @param  pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
-  * @param  pSubPriority: Pointer on the Subpriority value (starting from 0).
-  * @retval None
-  */
-void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
- /* Get priority for Cortex-M system or device specific interrupts */
-  NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
-}
-
-/**
-  * @brief  Sets Pending bit of an external interrupt.
-  * @param  IRQn External interrupt number
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
-  * @retval None
-  */
-void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
-  /* Set interrupt pending */
-  NVIC_SetPendingIRQ(IRQn);
-}
-
-/**
-  * @brief  Gets Pending Interrupt (reads the pending register in the NVIC
-  *         and returns the pending bit for the specified interrupt).
-  * @param  IRQn External interrupt number.
-  *          This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
-  * @retval status: - 0  Interrupt status is not pending.
-  *                 - 1  Interrupt status is pending.
-  */
-uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
-  /* Return 1 if pending else 0 */
-  return NVIC_GetPendingIRQ(IRQn);
-}
-
-/**
-  * @brief  Clears the pending bit of an external interrupt.
-  * @param  IRQn External interrupt number.
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
-  * @retval None
-  */
-void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
-  /* Clear pending interrupt */
-  NVIC_ClearPendingIRQ(IRQn);
-}
-
-/**
-  * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
-  * @param IRQn External interrupt number
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
-  * @retval status: - 0  Interrupt status is not pending.
-  *                 - 1  Interrupt status is pending.
-  */
-uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
-  /* Return 1 if active else 0 */
-  return NVIC_GetActive(IRQn);
-}
-
-/**
-  * @brief  Configures the SysTick clock source.
-  * @param  CLKSource: specifies the SysTick clock source.
-  *          This parameter can be one of the following values:
-  *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
-  *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
-  * @retval None
-  */
-void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
-{
-  /* Check the parameters */
-  assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
-  if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
-  {
-    SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
-  }
-  else
-  {
-    SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
-  }
-}
-
-/**
-  * @brief  This function handles SYSTICK interrupt request.
-  * @retval None
-  */
-void HAL_SYSTICK_IRQHandler(void)
-{
-  HAL_SYSTICK_Callback();
-}
-
-/**
-  * @brief  SYSTICK callback.
-  * @retval None
-  */
-__weak void HAL_SYSTICK_Callback(void)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SYSTICK_Callback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_dac.c b/stmhal/hal/f7/src/stm32f7xx_hal_dac.c
deleted file mode 100644
index a37465bcd8..0000000000
--- a/stmhal/hal/f7/src/stm32f7xx_hal_dac.c
+++ /dev/null
@@ -1,967 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_dac.c
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   DAC HAL module driver.
-  *         This file provides firmware functions to manage the following
-  *         functionalities of the Digital to Analog Converter (DAC) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions
-  *           + Peripheral State and Errors functions
-  *
-  *
-  @verbatim
-  ==============================================================================
-                      ##### DAC Peripheral features #####
-  ==============================================================================
-    [..]
-      *** DAC Channels ***
-      ====================
-    [..]
-    The device integrates two 12-bit Digital Analog Converters that can
-    be used independently or simultaneously (dual mode):
-      (#) DAC channel1 with DAC_OUT1 (PA4) as output
-      (#) DAC channel2 with DAC_OUT2 (PA5) as output
-
-      *** DAC Triggers ***
-      ====================
-    [..]
-    Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
-    and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
-    [..]
-    Digital to Analog conversion can be triggered by:
-      (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_TRIGGER_EXT_IT9.
-          The used pin (GPIOx_Pin9) must be configured in input mode.
-
-      (#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8
-          (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T4_TRGO...)
-
-      (#) Software using DAC_TRIGGER_SOFTWARE
-
-      *** DAC Buffer mode feature ***
-      ===============================
-      [..]
-      Each DAC channel integrates an output buffer that can be used to
-      reduce the output impedance, and to drive external loads directly
-      without having to add an external operational amplifier.
-      To enable, the output buffer use
-      sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
-      [..]
-      (@) Refer to the device datasheet for more details about output
-          impedance value with and without output buffer.
-
-       *** DAC wave generation feature ***
-       ===================================
-       [..]
-       Both DAC channels can be used to generate
-         (#) Noise wave using HAL_DACEx_NoiseWaveGenerate()
-         (#) Triangle wave using HAL_DACEx_TriangleWaveGenerate()
-
-       *** DAC data format ***
-       =======================
-       [..]
-       The DAC data format can be:
-         (#) 8-bit right alignment using DAC_ALIGN_8B_R
-         (#) 12-bit left alignment using DAC_ALIGN_12B_L
-         (#) 12-bit right alignment using DAC_ALIGN_12B_R
-
-       *** DAC data value to voltage correspondence ***
-       ================================================
-       [..]
-       The analog output voltage on each DAC channel pin is determined
-       by the following equation:
-       DAC_OUTx = VREF+ * DOR / 4095
-       with  DOR is the Data Output Register
-          VEF+ is the input voltage reference (refer to the device datasheet)
-        e.g. To set DAC_OUT1 to 0.7V, use
-          Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
-
-       *** DMA requests  ***
-       =====================
-       [..]
-       A DMA1 request can be generated when an external trigger (but not
-       a software trigger) occurs if DMA1 requests are enabled using
-       HAL_DAC_Start_DMA()
-       [..]
-       DMA1 requests are mapped as following:
-         (#) DAC channel1 : mapped on DMA1 Stream5 channel7 which must be
-             already configured
-         (#) DAC channel2 : mapped on DMA1 Stream6 channel7 which must be
-             already configured
-
-    -@- For Dual mode and specific signal (Triangle and noise) generation please
-        refer to Extension Features Driver description
-
-
-                      ##### How to use this driver #####
-  ==============================================================================
-    [..]
-      (+) DAC APB clock must be enabled to get write access to DAC
-          registers using HAL_DAC_Init()
-      (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
-      (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
-      (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA functions
-
-     *** Polling mode IO operation ***
-     =================================
-     [..]
-       (+) Start the DAC peripheral using HAL_DAC_Start()
-       (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
-       (+) Stop the DAC peripheral using HAL_DAC_Stop()
-
-
-     *** DMA mode IO operation ***
-     ==============================
-     [..]
-       (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
-           of data to be transferred at each end of conversion
-       (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2()
-           function is executed and user can add his own code by customization of function pointer
-           HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2
-       (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
-            add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
-       (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
-
-
-     *** DAC HAL driver macros list ***
-     =============================================
-     [..]
-       Below the list of most used macros in DAC HAL driver.
-
-      (+) __HAL_DAC_ENABLE : Enable the DAC peripheral
-      (+) __HAL_DAC_DISABLE : Disable the DAC peripheral
-      (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
-      (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
-
-     [..]
-      (@) You can refer to the DAC HAL driver header file for more useful macros
-
- @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup DAC DAC
-  * @brief DAC driver modules
-  * @{
-  */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @addtogroup DAC_Private_Functions
-  * @{
-  */
-/* Private function prototypes -----------------------------------------------*/
-static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
-static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
-static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup DAC_Exported_Functions DAC Exported Functions
-  * @{
-  */
-
-/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @brief    Initialization and Configuration functions
- *
-@verbatim
-  ==============================================================================
-              ##### Initialization and de-initialization functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Initialize and configure the DAC.
-      (+) De-initialize the DAC.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the DAC peripheral according to the specified parameters
-  *         in the DAC_InitStruct.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
-{
-  /* Check DAC handle */
-  if(hdac == NULL)
-  {
-     return HAL_ERROR;
-  }
-  /* Check the parameters */
-  assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
-
-  if(hdac->State == HAL_DAC_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hdac->Lock = HAL_UNLOCKED;
-    /* Init the low level hardware */
-    HAL_DAC_MspInit(hdac);
-  }
-
-  /* Initialize the DAC state*/
-  hdac->State = HAL_DAC_STATE_BUSY;
-
-  /* Set DAC error code to none */
-  hdac->ErrorCode = HAL_DAC_ERROR_NONE;
-
-  /* Initialize the DAC state*/
-  hdac->State = HAL_DAC_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deinitializes the DAC peripheral registers to their default reset values.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
-{
-  /* Check DAC handle */
-  if(hdac == NULL)
-  {
-     return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_BUSY;
-
-  /* DeInit the low level hardware */
-  HAL_DAC_MspDeInit(hdac);
-
-  /* Set DAC error code to none */
-  hdac->ErrorCode = HAL_DAC_ERROR_NONE;
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hdac);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the DAC MSP.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_DAC_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes the DAC MSP.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_DAC_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_Exported_Functions_Group2 IO operation functions
- *  @brief    IO operation functions
- *
-@verbatim
-  ==============================================================================
-             ##### IO operation functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Start conversion.
-      (+) Stop conversion.
-      (+) Start conversion and enable DMA transfer.
-      (+) Stop conversion and disable DMA transfer.
-      (+) Get result of conversion.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables DAC and starts conversion of channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
-  uint32_t tmp1 = 0, tmp2 = 0;
-
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-
-  /* Process locked */
-  __HAL_LOCK(hdac);
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_BUSY;
-
-  /* Enable the Peripheral */
-  __HAL_DAC_ENABLE(hdac, Channel);
-
-  if(Channel == DAC_CHANNEL_1)
-  {
-    tmp1 = hdac->Instance->CR & DAC_CR_TEN1;
-    tmp2 = hdac->Instance->CR & DAC_CR_TSEL1;
-    /* Check if software trigger enabled */
-    if((tmp1 ==  DAC_CR_TEN1) && (tmp2 ==  DAC_CR_TSEL1))
-    {
-      /* Enable the selected DAC software conversion */
-      hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1;
-    }
-  }
-  else
-  {
-    tmp1 = hdac->Instance->CR & DAC_CR_TEN2;
-    tmp2 = hdac->Instance->CR & DAC_CR_TSEL2;
-    /* Check if software trigger enabled */
-    if((tmp1 == DAC_CR_TEN2) && (tmp2 == DAC_CR_TSEL2))
-    {
-      /* Enable the selected DAC software conversion*/
-      hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG2;
-    }
-  }
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_READY;
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hdac);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disables DAC and stop conversion of channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-
-  /* Disable the Peripheral */
-  __HAL_DAC_DISABLE(hdac, Channel);
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enables DAC and starts conversion of channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @param  pData: The destination peripheral Buffer address.
-  * @param  Length: The length of data to be transferred from memory to DAC peripheral
-  * @param  Alignment: Specifies the data alignment for DAC channel.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
-  *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
-  *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  assert_param(IS_DAC_ALIGN(Alignment));
-
-  /* Process locked */
-  __HAL_LOCK(hdac);
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_BUSY;
-
-  if(Channel == DAC_CHANNEL_1)
-  {
-    /* Set the DMA transfer complete callback for channel1 */
-    hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
-
-    /* Set the DMA half transfer complete callback for channel1 */
-    hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
-
-    /* Set the DMA error callback for channel1 */
-    hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
-
-    /* Enable the selected DAC channel1 DMA request */
-    hdac->Instance->CR |= DAC_CR_DMAEN1;
-
-    /* Case of use of channel 1 */
-    switch(Alignment)
-    {
-      case DAC_ALIGN_12B_R:
-        /* Get DHR12R1 address */
-        tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
-        break;
-      case DAC_ALIGN_12B_L:
-        /* Get DHR12L1 address */
-        tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
-        break;
-      case DAC_ALIGN_8B_R:
-        /* Get DHR8R1 address */
-        tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
-        break;
-      default:
-        break;
-    }
-  }
-  else
-  {
-    /* Set the DMA transfer complete callback for channel2 */
-    hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
-
-    /* Set the DMA half transfer complete callback for channel2 */
-    hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
-
-    /* Set the DMA error callback for channel2 */
-    hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
-
-    /* Enable the selected DAC channel2 DMA request */
-    hdac->Instance->CR |= DAC_CR_DMAEN2;
-
-    /* Case of use of channel 2 */
-    switch(Alignment)
-    {
-      case DAC_ALIGN_12B_R:
-        /* Get DHR12R2 address */
-        tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
-        break;
-      case DAC_ALIGN_12B_L:
-        /* Get DHR12L2 address */
-        tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
-        break;
-      case DAC_ALIGN_8B_R:
-        /* Get DHR8R2 address */
-        tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
-        break;
-      default:
-        break;
-    }
-  }
-
-  /* Enable the DMA Stream */
-  if(Channel == DAC_CHANNEL_1)
-  {
-    /* Enable the DAC DMA underrun interrupt */
-    __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
-
-    /* Enable the DMA Stream */
-    HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
-  }
-  else
-  {
-    /* Enable the DAC DMA underrun interrupt */
-    __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
-
-    /* Enable the DMA Stream */
-    HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
-  }
-
-  /* Enable the Peripheral */
-  __HAL_DAC_ENABLE(hdac, Channel);
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hdac);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disables DAC and stop conversion of channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-
-  /* Disable the selected DAC channel DMA request */
-   hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel);
-
-  /* Disable the Peripheral */
-  __HAL_DAC_DISABLE(hdac, Channel);
-
-  /* Disable the DMA Channel */
-  /* Channel1 is used */
-  if(Channel == DAC_CHANNEL_1)
-  {
-    status = HAL_DMA_Abort(hdac->DMA_Handle1);
-  }
-  else /* Channel2 is used for */
-  {
-    status = HAL_DMA_Abort(hdac->DMA_Handle2);
-  }
-
-  /* Check if DMA Channel effectively disabled */
-  if(status != HAL_OK)
-  {
-    /* Update DAC state machine to error */
-    hdac->State = HAL_DAC_STATE_ERROR;
-  }
-  else
-  {
-    /* Change DAC state */
-    hdac->State = HAL_DAC_STATE_READY;
-  }
-
-  /* Return function status */
-  return status;
-}
-
-/**
-  * @brief  Returns the last data output value of the selected DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @retval The selected DAC channel data output value.
-  */
-uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-
-  /* Returns the DAC channel data output register value */
-  if(Channel == DAC_CHANNEL_1)
-  {
-    return hdac->Instance->DOR1;
-  }
-  else
-  {
-    return hdac->Instance->DOR2;
-  }
-}
-
-/**
-  * @brief  Handles DAC interrupt request
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
-{
-  /* Check underrun channel 1 flag */
-  if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
-  {
-    /* Change DAC state to error state */
-    hdac->State = HAL_DAC_STATE_ERROR;
-
-    /* Set DAC error code to channel1 DMA underrun error */
-    hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
-
-    /* Clear the underrun flag */
-    __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
-
-    /* Disable the selected DAC channel1 DMA request */
-    hdac->Instance->CR &= ~DAC_CR_DMAEN1;
-
-    /* Error callback */
-    HAL_DAC_DMAUnderrunCallbackCh1(hdac);
-  }
-  /* Check underrun channel 2 flag */
-  if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
-  {
-    /* Change DAC state to error state */
-    hdac->State = HAL_DAC_STATE_ERROR;
-
-    /* Set DAC error code to channel2 DMA underrun error */
-    hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH2;
-
-    /* Clear the underrun flag */
-    __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
-
-    /* Disable the selected DAC channel1 DMA request */
-    hdac->Instance->CR &= ~DAC_CR_DMAEN2;
-
-    /* Error callback */
-    HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
-  }
-}
-
-/**
-  * @brief  Conversion complete callback in non blocking mode for Channel1
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_DAC_ConvCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Conversion half DMA transfer callback in non blocking mode for Channel1
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Error DAC callback for Channel1.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DMA underrun DAC callback for channel1.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
- *  @brief   	Peripheral Control functions
- *
-@verbatim
-  ==============================================================================
-             ##### Peripheral Control functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Configure channels.
-      (+) Set the specified data holding register value for DAC channel.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configures the selected DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  sConfig: DAC configuration structure.
-  * @param  Channel: The selected DAC channel.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
-{
-  uint32_t tmpreg1 = 0, tmpreg2 = 0;
-
-  /* Check the DAC parameters */
-  assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
-  assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
-  assert_param(IS_DAC_CHANNEL(Channel));
-
-  /* Process locked */
-  __HAL_LOCK(hdac);
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_BUSY;
-
-  /* Get the DAC CR value */
-  tmpreg1 = hdac->Instance->CR;
-  /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
-  tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
-  /* Configure for the selected DAC channel: buffer output, trigger */
-  /* Set TSELx and TENx bits according to DAC_Trigger value */
-  /* Set BOFFx bit according to DAC_OutputBuffer value */
-  tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
-  /* Calculate CR register value depending on DAC_Channel */
-  tmpreg1 |= tmpreg2 << Channel;
-  /* Write to DAC CR */
-  hdac->Instance->CR = tmpreg1;
-  /* Disable wave generation */
-  hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel);
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_READY;
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hdac);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set the specified data holding register value for DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @param  Alignment: Specifies the data alignment.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
-  *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
-  *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
-  * @param  Data: Data to be loaded in the selected data holding register.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
-{
-  __IO uint32_t tmp = 0;
-
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  assert_param(IS_DAC_ALIGN(Alignment));
-  assert_param(IS_DAC_DATA(Data));
-
-  tmp = (uint32_t)hdac->Instance;
-  if(Channel == DAC_CHANNEL_1)
-  {
-    tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
-  }
-  else
-  {
-    tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
-  }
-
-  /* Set the DAC channel1 selected data holding register */
-  *(__IO uint32_t *) tmp = Data;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
- *  @brief   Peripheral State and Errors functions
- *
-@verbatim
-  ==============================================================================
-            ##### Peripheral State and Errors functions #####
-  ==============================================================================
-    [..]
-    This subsection provides functions allowing to
-      (+) Check the DAC state.
-      (+) Check the DAC Errors.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  return the DAC state
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval HAL state
-  */
-HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)
-{
-  /* Return DAC state */
-  return hdac->State;
-}
-
-
-/**
-  * @brief  Return the DAC error code
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval DAC Error Code
-  */
-uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
-{
-  return hdac->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @brief  DMA conversion complete callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
-{
-  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  HAL_DAC_ConvCpltCallbackCh1(hdac);
-
-  hdac->State= HAL_DAC_STATE_READY;
-}
-
-/**
-  * @brief  DMA half transfer complete callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
-{
-    DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-    /* Conversion complete callback */
-    HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
-}
-
-/**
-  * @brief  DMA error callback
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
-{
-  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  /* Set DAC error code to DMA error */
-  hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
-
-  HAL_DAC_ErrorCallbackCh1(hdac);
-
-  hdac->State= HAL_DAC_STATE_READY;
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_dac_ex.c b/stmhal/hal/f7/src/stm32f7xx_hal_dac_ex.c
deleted file mode 100644
index a7b803e9b6..0000000000
--- a/stmhal/hal/f7/src/stm32f7xx_hal_dac_ex.c
+++ /dev/null
@@ -1,388 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_dac_ex.c
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   Extended DAC HAL module driver.
-  *         This file provides firmware functions to manage the following
-  *         functionalities of DAC extension peripheral:
-  *           + Extended features functions
-  *
-  *
-  @verbatim
-  ==============================================================================
-                      ##### How to use this driver #####
-  ==============================================================================
-    [..]
-      (+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) :
-          Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
-          HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.
-      (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
-      (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
-
- @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup DACEx DACEx
-  * @brief DAC driver modules
-  * @{
-  */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup DACEx_Exported_Functions DAC Exported Functions
-  * @{
-  */
-
-/** @defgroup DACEx_Exported_Functions_Group1 Extended features functions
- *  @brief    Extended features functions
- *
-@verbatim
-  ==============================================================================
-                 ##### Extended features functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Start conversion.
-      (+) Stop conversion.
-      (+) Start conversion and enable DMA transfer.
-      (+) Stop conversion and disable DMA transfer.
-      (+) Get result of conversion.
-      (+) Get result of dual mode conversion.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Returns the last data output value of the selected DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval The selected DAC channel data output value.
-  */
-uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
-{
-  uint32_t tmp = 0;
-
-  tmp |= hdac->Instance->DOR1;
-
-  tmp |= hdac->Instance->DOR2 << 16;
-
-  /* Returns the DAC channel data output register value */
-  return tmp;
-}
-
-/**
-  * @brief  Enables or disables the selected DAC channel wave generation.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @param  Amplitude: Select max triangle amplitude.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
-  *            @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
-  *            @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
-  *            @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
-  *            @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
-  *            @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
-  *            @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
-  *            @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
-  *            @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
-  *            @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
-  *            @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
-  *            @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
-{
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
-
-  /* Process locked */
-  __HAL_LOCK(hdac);
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_BUSY;
-
-  /* Enable the selected wave generation for the selected DAC channel */
-  MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1 | DAC_CR_MAMP1) << Channel, (DAC_CR_WAVE1_1 | Amplitude) << Channel);
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_READY;
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hdac);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enables or disables the selected DAC channel wave generation.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @param  Amplitude: Unmask DAC channel LFSR for noise wave generation.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
-{
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
-
-  /* Process locked */
-  __HAL_LOCK(hdac);
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_BUSY;
-
-  /* Enable the selected wave generation for the selected DAC channel */
-  MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1 | DAC_CR_MAMP1) << Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel);
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_READY;
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hdac);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set the specified data holding register value for dual DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *               the configuration information for the specified DAC.
-  * @param  Alignment: Specifies the data alignment for dual channel DAC.
-  *          This parameter can be one of the following values:
-  *            DAC_ALIGN_8B_R: 8bit right data alignment selected
-  *            DAC_ALIGN_12B_L: 12bit left data alignment selected
-  *            DAC_ALIGN_12B_R: 12bit right data alignment selected
-  * @param  Data1: Data for DAC Channel2 to be loaded in the selected data holding register.
-  * @param  Data2: Data for DAC Channel1 to be loaded in the selected data  holding register.
-  * @note   In dual mode, a unique register access is required to write in both
-  *          DAC channels at the same time.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
-{
-  uint32_t data = 0, tmp = 0;
-
-  /* Check the parameters */
-  assert_param(IS_DAC_ALIGN(Alignment));
-  assert_param(IS_DAC_DATA(Data1));
-  assert_param(IS_DAC_DATA(Data2));
-
-  /* Calculate and set dual DAC data holding register value */
-  if (Alignment == DAC_ALIGN_8B_R)
-  {
-    data = ((uint32_t)Data2 << 8) | Data1;
-  }
-  else
-  {
-    data = ((uint32_t)Data2 << 16) | Data1;
-  }
-
-  tmp = (uint32_t)hdac->Instance;
-  tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
-
-  /* Set the dual DAC selected data holding register */
-  *(__IO uint32_t *)tmp = data;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @brief  Conversion complete callback in non blocking mode for Channel2
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_DAC_ConvCpltCallbackCh2 could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Conversion half DMA transfer callback in non blocking mode for Channel2
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Error DAC callback for Channel2.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DMA underrun DAC callback for channel2.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DMA conversion complete callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
-{
-  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  HAL_DACEx_ConvCpltCallbackCh2(hdac);
-
-  hdac->State= HAL_DAC_STATE_READY;
-}
-
-/**
-  * @brief  DMA half transfer complete callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
-{
-    DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-    /* Conversion complete callback */
-    HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
-}
-
-/**
-  * @brief  DMA error callback
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
-{
-  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  /* Set DAC error code to DMA error */
-  hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
-
-  HAL_DACEx_ErrorCallbackCh2(hdac);
-
-  hdac->State= HAL_DAC_STATE_READY;
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_dma.c b/stmhal/hal/f7/src/stm32f7xx_hal_dma.c
deleted file mode 100644
index df915ce529..0000000000
--- a/stmhal/hal/f7/src/stm32f7xx_hal_dma.c
+++ /dev/null
@@ -1,1318 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_dma.c
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   DMA HAL module driver.
-  *
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Direct Memory Access (DMA) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral State and errors functions
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-  [..]
-   (#) Enable and configure the peripheral to be connected to the DMA Stream
-       (except for internal SRAM/FLASH memories: no initialization is
-       necessary) please refer to Reference manual for connection between peripherals
-       and DMA requests.
-
-   (#) For a given Stream, program the required configuration through the following parameters:
-       Transfer Direction, Source and Destination data formats,
-       Circular, Normal or peripheral flow control mode, Stream Priority level,
-       Source and Destination Increment mode, FIFO mode and its Threshold (if needed),
-       Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.
-
-   -@-   Prior to HAL_DMA_Init() the clock must be enabled for DMA through the following macros:
-         __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE().
-
-     *** Polling mode IO operation ***
-     =================================
-    [..]
-          (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
-              address and destination address and the Length of data to be transferred.
-          (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
-              case a fixed Timeout can be configured by User depending from his application.
-          (+) Use HAL_DMA_Abort() function to abort the current transfer.
-
-     *** Interrupt mode IO operation ***
-     ===================================
-    [..]
-          (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
-          (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
-          (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
-              Source address and destination address and the Length of data to be transferred. In this
-              case the DMA interrupt is configured
-          (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
-          (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
-              add his own function by customization of function pointer XferCpltCallback and
-              XferErrorCallback (i.e a member of DMA handle structure).
-    [..]
-     (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
-         detection.
-
-     (#) Use HAL_DMA_Abort_IT() function to abort the current transfer
-
-     -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.
-
-     -@-   The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
-           possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
-           Half-Word data size for the peripheral to access its data register and set Word data size
-           for the Memory to gain in access time. Each two half words will be packed and written in
-           a single access to a Word in the Memory).
-
-     -@-   When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
-           and Destination. In this case the Peripheral Data Size will be applied to both Source
-           and Destination.
-
-     *** DMA HAL driver macros list ***
-     =============================================
-     [..]
-       Below the list of most used macros in DMA HAL driver.
-
-      (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
-      (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
-      (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not.
-
-     [..]
-      (@) You can refer to the DMA HAL driver header file for more useful macros
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup DMA DMA
-  * @brief DMA HAL module driver
-  * @{
-  */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-
-/* Private types -------------------------------------------------------------*/
-typedef struct
-{
-  __IO uint32_t ISR;   /*!< DMA interrupt status register */
-  __IO uint32_t Reserved0;
-  __IO uint32_t IFCR;  /*!< DMA interrupt flag clear register */
-} DMA_Base_Registers;
-
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @addtogroup DMA_Private_Constants
- * @{
- */
- #define HAL_TIMEOUT_DMA_ABORT    ((uint32_t)5)  /* 5 ms */
-/**
-  * @}
-  */
-/* Private macros ------------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/** @addtogroup DMA_Private_Functions
-  * @{
-  */
-static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);
-
-/**
-  * @}
-  */
-
-/* Exported functions ---------------------------------------------------------*/
-/** @addtogroup DMA_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup DMA_Exported_Functions_Group1
-  *
-@verbatim
- ===============================================================================
-             ##### Initialization and de-initialization functions  #####
- ===============================================================================
-    [..]
-    This section provides functions allowing to initialize the DMA Stream source
-    and destination addresses, incrementation and data sizes, transfer direction,
-    circular/normal mode selection, memory-to-memory mode selection and Stream priority value.
-    [..]
-    The HAL_DMA_Init() function follows the DMA configuration procedures as described in
-    reference manual.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initialize the DMA according to the specified
-  *         parameters in the DMA_InitTypeDef and create the associated handle.
-  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Stream.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
-{
-  uint32_t tmp = 0U;
-  uint32_t tickstart = HAL_GetTick();
-  DMA_Base_Registers *regs;
-
-  /* Check the DMA peripheral state */
-  if(hdma == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
-  assert_param(IS_DMA_CHANNEL(hdma->Init.Channel));
-  assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
-  assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
-  assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
-  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
-  assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
-  assert_param(IS_DMA_MODE(hdma->Init.Mode));
-  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
-  assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode));
-  /* Check the memory burst, peripheral burst and FIFO threshold parameters only
-     when FIFO mode is enabled */
-  if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE)
-  {
-    assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold));
-    assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
-    assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
-  }
-
-  /* Allocate lock resource */
-  __HAL_UNLOCK(hdma);
-
-  /* Change DMA peripheral state */
-  hdma->State = HAL_DMA_STATE_BUSY;
-
-  /* Disable the peripheral */
-  __HAL_DMA_DISABLE(hdma);
-
-  /* Check if the DMA Stream is effectively disabled */
-  while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
-  {
-    /* Check for the Timeout */
-    if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
-    {
-      /* Update error code */
-      hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
-
-      /* Change the DMA state */
-      hdma->State = HAL_DMA_STATE_TIMEOUT;
-
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Get the CR register value */
-  tmp = hdma->Instance->CR;
-
-  /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
-  tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
-                      DMA_SxCR_PL    | DMA_SxCR_MSIZE  | DMA_SxCR_PSIZE  | \
-                      DMA_SxCR_MINC  | DMA_SxCR_PINC   | DMA_SxCR_CIRC   | \
-                      DMA_SxCR_DIR   | DMA_SxCR_CT     | DMA_SxCR_DBM));
-
-  /* Prepare the DMA Stream configuration */
-  tmp |=  hdma->Init.Channel             | hdma->Init.Direction        |
-          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
-          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
-          hdma->Init.Mode                | hdma->Init.Priority;
-
-  /* the Memory burst and peripheral burst are not used when the FIFO is disabled */
-  if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
-  {
-    /* Get memory burst and peripheral burst */
-    tmp |=  hdma->Init.MemBurst | hdma->Init.PeriphBurst;
-  }
-
-  /* Write to DMA Stream CR register */
-  hdma->Instance->CR = tmp;
-
-  /* Get the FCR register value */
-  tmp = hdma->Instance->FCR;
-
-  /* Clear Direct mode and FIFO threshold bits */
-  tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
-
-  /* Prepare the DMA Stream FIFO configuration */
-  tmp |= hdma->Init.FIFOMode;
-
-  /* the FIFO threshold is not used when the FIFO mode is disabled */
-  if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
-  {
-    /* Get the FIFO threshold */
-    tmp |= hdma->Init.FIFOThreshold;
-
-    if (DMA_CheckFifoParam(hdma) != HAL_OK)
-    {
-      /* Update error code */
-      hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
-
-      /* Change the DMA state */
-      hdma->State = HAL_DMA_STATE_READY;
-
-      return HAL_ERROR;
-    }
-  }
-
-  /* Write to DMA Stream FCR */
-  hdma->Instance->FCR = tmp;
-
-  /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
-     DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
-  regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
-
-  /* Clear all interrupt flags */
-  regs->IFCR = 0x3FU << hdma->StreamIndex;
-
-  /* Initialize the error code */
-  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
-  /* Initialize the DMA state */
-  hdma->State = HAL_DMA_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the DMA peripheral
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Stream.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
-{
-  DMA_Base_Registers *regs;
-
-  /* Check the DMA peripheral state */
-  if(hdma == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the DMA peripheral state */
-  if(hdma->State == HAL_DMA_STATE_BUSY)
-  {
-    /* Return error status */
-    return HAL_BUSY;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
-
-  /* Disable the selected DMA Streamx */
-  __HAL_DMA_DISABLE(hdma);
-
-  /* Reset DMA Streamx control register */
-  hdma->Instance->CR   = 0U;
-
-  /* Reset DMA Streamx number of data to transfer register */
-  hdma->Instance->NDTR = 0U;
-
-  /* Reset DMA Streamx peripheral address register */
-  hdma->Instance->PAR  = 0U;
-
-  /* Reset DMA Streamx memory 0 address register */
-  hdma->Instance->M0AR = 0U;
-
-  /* Reset DMA Streamx memory 1 address register */
-  hdma->Instance->M1AR = 0U;
-
-  /* Reset DMA Streamx FIFO control register */
-  hdma->Instance->FCR  = (uint32_t)0x00000021U;
-
-  /* Get DMA steam Base Address */
-  regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
-
-  /* Clear all interrupt flags at correct offset within the register */
-  regs->IFCR = 0x3FU << hdma->StreamIndex;
-
-  /* Initialize the error code */
-  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
-  /* Initialize the DMA state */
-  hdma->State = HAL_DMA_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hdma);
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup DMA_Exported_Functions_Group2
-  *
-@verbatim
- ===============================================================================
-                      #####  IO operation functions  #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Configure the source, destination address and data length and Start DMA transfer
-      (+) Configure the source, destination address and data length and
-          Start DMA transfer with interrupt
-      (+) Abort DMA transfer
-      (+) Poll for transfer complete
-      (+) Handle DMA interrupt request
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Starts the DMA Transfer.
-  * @param  hdma      : pointer to a DMA_HandleTypeDef structure that contains
-  *                     the configuration information for the specified DMA Stream.
-  * @param  SrcAddress: The source memory Buffer address
-  * @param  DstAddress: The destination memory Buffer address
-  * @param  DataLength: The length of data to be transferred from source to destination
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-
-  /* Process locked */
-  __HAL_LOCK(hdma);
-
-  if(HAL_DMA_STATE_READY == hdma->State)
-  {
-    /* Change DMA peripheral state */
-    hdma->State = HAL_DMA_STATE_BUSY;
-
-    /* Initialize the error code */
-    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
-    /* Configure the source, destination address and the data length */
-    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
-
-    /* Enable the Peripheral */
-    __HAL_DMA_ENABLE(hdma);
-  }
-  else
-  {
-    /* Process unlocked */
-    __HAL_UNLOCK(hdma);
-
-    /* Return error status */
-    status = HAL_BUSY;
-  }
-  return status;
-}
-
-/**
-  * @brief  Start the DMA Transfer with interrupt enabled.
-  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
-  *                     the configuration information for the specified DMA Stream.
-  * @param  SrcAddress: The source memory Buffer address
-  * @param  DstAddress: The destination memory Buffer address
-  * @param  DataLength: The length of data to be transferred from source to destination
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* calculate DMA base and stream number */
-  DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
-
-  /* Check the parameters */
-  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-
-  /* Process locked */
-  __HAL_LOCK(hdma);
-
-  if(HAL_DMA_STATE_READY == hdma->State)
-  {
-    /* Change DMA peripheral state */
-    hdma->State = HAL_DMA_STATE_BUSY;
-
-    /* Initialize the error code */
-    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
-    /* Configure the source, destination address and the data length */
-    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
-
-    /* Clear all interrupt flags at correct offset within the register */
-    regs->IFCR = 0x3FU << hdma->StreamIndex;
-
-    /* Enable Common interrupts*/
-    hdma->Instance->CR  |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
-    hdma->Instance->FCR |= DMA_IT_FE;
-
-    if(hdma->XferHalfCpltCallback != NULL)
-    {
-      hdma->Instance->CR  |= DMA_IT_HT;
-    }
-
-    /* Enable the Peripheral */
-    __HAL_DMA_ENABLE(hdma);
-  }
-  else
-  {
-    /* Process unlocked */
-    __HAL_UNLOCK(hdma);
-
-    /* Return error status */
-    status = HAL_BUSY;
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Aborts the DMA Transfer.
-  * @param  hdma  : pointer to a DMA_HandleTypeDef structure that contains
-  *                 the configuration information for the specified DMA Stream.
-  *
-  * @note  After disabling a DMA Stream, a check for wait until the DMA Stream is
-  *        effectively disabled is added. If a Stream is disabled
-  *        while a data transfer is ongoing, the current data will be transferred
-  *        and the Stream will be effectively disabled only after the transfer of
-  *        this single data is finished.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
-{
-  /* calculate DMA base and stream number */
-  DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
-
-  uint32_t tickstart = HAL_GetTick();
-
-  if(hdma->State != HAL_DMA_STATE_BUSY)
-  {
-    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hdma);
-
-    return HAL_ERROR;
-  }
-  else
-  {
-    /* Disable all the transfer interrupts */
-    hdma->Instance->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
-    hdma->Instance->FCR &= ~(DMA_IT_FE);
-
-    if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
-    {
-      hdma->Instance->CR  &= ~(DMA_IT_HT);
-    }
-
-    /* Disable the stream */
-    __HAL_DMA_DISABLE(hdma);
-
-    /* Check if the DMA Stream is effectively disabled */
-    while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
-    {
-      /* Check for the Timeout */
-      if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
-      {
-        /* Update error code */
-        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hdma);
-
-        /* Change the DMA state */
-        hdma->State = HAL_DMA_STATE_TIMEOUT;
-
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Clear all interrupt flags at correct offset within the register */
-    regs->IFCR = 0x3FU << hdma->StreamIndex;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hdma);
-
-    /* Change the DMA state*/
-    hdma->State = HAL_DMA_STATE_READY;
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Aborts the DMA Transfer in Interrupt mode.
-  * @param  hdma  : pointer to a DMA_HandleTypeDef structure that contains
-  *                 the configuration information for the specified DMA Stream.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
-{
-  if(hdma->State != HAL_DMA_STATE_BUSY)
-  {
-    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
-    return HAL_ERROR;
-  }
-  else
-  {
-    /* Set Abort State  */
-    hdma->State = HAL_DMA_STATE_ABORT;
-
-    /* Disable the stream */
-    __HAL_DMA_DISABLE(hdma);
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Polling for transfer complete.
-  * @param  hdma:          pointer to a DMA_HandleTypeDef structure that contains
-  *                        the configuration information for the specified DMA Stream.
-  * @param  CompleteLevel: Specifies the DMA level complete.
-  * @note   The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead.
-  *         This model could be used for debug purpose.
-  * @note   The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode).
-  * @param  Timeout:       Timeout duration.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  uint32_t mask_cpltlevel;
-  uint32_t tickstart = HAL_GetTick();
-  uint32_t tmpisr;
-
-  /* calculate DMA base and stream number */
-  DMA_Base_Registers *regs;
-
-  if(HAL_DMA_STATE_BUSY != hdma->State)
-  {
-    /* No transfer ongoing */
-    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
-    __HAL_UNLOCK(hdma);
-    return HAL_ERROR;
-  }
-
-  /* Polling mode not supported in circular mode and double buffering mode */
-  if ((hdma->Instance->CR & DMA_SxCR_CIRC) != RESET)
-  {
-    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
-    return HAL_ERROR;
-  }
-
-  /* Get the level transfer complete flag */
-  if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
-  {
-    /* Transfer Complete flag */
-    mask_cpltlevel = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
-  }
-  else
-  {
-    /* Half Transfer Complete flag */
-    mask_cpltlevel = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
-  }
-
-  regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
-  tmpisr = regs->ISR;
-
-  while(((tmpisr & mask_cpltlevel) == RESET) && ((hdma->ErrorCode & HAL_DMA_ERROR_TE) == RESET))
-  {
-    /* Check for the Timeout (Not applicable in circular mode)*/
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        /* Update error code */
-        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hdma);
-
-        /* Change the DMA state */
-        hdma->State = HAL_DMA_STATE_READY;
-
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Get the ISR register value */
-    tmpisr = regs->ISR;
-
-    if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
-    {
-      /* Update error code */
-      hdma->ErrorCode |= HAL_DMA_ERROR_TE;
-
-      /* Clear the transfer error flag */
-      regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
-    }
-
-    if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
-    {
-      /* Update error code */
-      hdma->ErrorCode |= HAL_DMA_ERROR_FE;
-
-      /* Clear the FIFO error flag */
-      regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
-    }
-
-    if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
-    {
-      /* Update error code */
-      hdma->ErrorCode |= HAL_DMA_ERROR_DME;
-
-      /* Clear the Direct Mode error flag */
-      regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
-    }
-  }
-
-  if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
-  {
-    if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
-    {
-      HAL_DMA_Abort(hdma);
-
-      /* Clear the half transfer and transfer complete flags */
-      regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hdma);
-
-      /* Change the DMA state */
-      hdma->State= HAL_DMA_STATE_READY;
-
-      return HAL_ERROR;
-   }
-  }
-
-  /* Get the level transfer complete flag */
-  if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
-  {
-    /* Clear the half transfer and transfer complete flags */
-    regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hdma);
-
-    hdma->State = HAL_DMA_STATE_READY;
-  }
-  else
-  {
-    /* Clear the half transfer and transfer complete flags */
-    regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex;
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Handles DMA interrupt request.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Stream.
-  * @retval None
-  */
-void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
-{
-  uint32_t tmpisr;
-  __IO uint32_t count = 0;
-  uint32_t timeout = SystemCoreClock / 9600;
-
-  /* calculate DMA base and stream number */
-  DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
-
-  tmpisr = regs->ISR;
-
-  /* Transfer Error Interrupt management ***************************************/
-  if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
-  {
-    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
-    {
-      /* Disable the transfer error interrupt */
-      hdma->Instance->CR  &= ~(DMA_IT_TE);
-
-      /* Clear the transfer error flag */
-      regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
-
-      /* Update error code */
-      hdma->ErrorCode |= HAL_DMA_ERROR_TE;
-    }
-  }
-  /* FIFO Error Interrupt management ******************************************/
-  if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
-  {
-    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)
-    {
-      /* Clear the FIFO error flag */
-      regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
-
-      /* Update error code */
-      hdma->ErrorCode |= HAL_DMA_ERROR_FE;
-    }
-  }
-  /* Direct Mode Error Interrupt management ***********************************/
-  if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
-  {
-    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)
-    {
-      /* Clear the direct mode error flag */
-      regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
-
-      /* Update error code */
-      hdma->ErrorCode |= HAL_DMA_ERROR_DME;
-    }
-  }
-  /* Half Transfer Complete Interrupt management ******************************/
-  if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)
-  {
-    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
-    {
-      /* Clear the half transfer complete flag */
-      regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
-
-      /* Multi_Buffering mode enabled */
-      if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
-      {
-        /* Current memory buffer used is Memory 0 */
-        if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
-        {
-          if(hdma->XferHalfCpltCallback != NULL)
-          {
-            /* Half transfer callback */
-            hdma->XferHalfCpltCallback(hdma);
-          }
-        }
-        /* Current memory buffer used is Memory 1 */
-        else
-        {
-          if(hdma->XferM1HalfCpltCallback != NULL)
-          {
-            /* Half transfer callback */
-            hdma->XferM1HalfCpltCallback(hdma);
-          }
-        }
-      }
-      else
-      {
-        /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
-        if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
-        {
-          /* Disable the half transfer interrupt */
-          hdma->Instance->CR  &= ~(DMA_IT_HT);
-        }
-
-        if(hdma->XferHalfCpltCallback != NULL)
-        {
-          /* Half transfer callback */
-          hdma->XferHalfCpltCallback(hdma);
-        }
-      }
-    }
-  }
-  /* Transfer Complete Interrupt management ***********************************/
-  if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)
-  {
-    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
-    {
-      /* Clear the transfer complete flag */
-      regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
-
-      if(HAL_DMA_STATE_ABORT == hdma->State)
-      {
-        /* Disable all the transfer interrupts */
-        hdma->Instance->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
-        hdma->Instance->FCR &= ~(DMA_IT_FE);
-
-        if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
-        {
-          hdma->Instance->CR  &= ~(DMA_IT_HT);
-        }
-
-        /* Clear all interrupt flags at correct offset within the register */
-        regs->IFCR = 0x3FU << hdma->StreamIndex;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hdma);
-
-        /* Change the DMA state */
-        hdma->State = HAL_DMA_STATE_READY;
-
-        if(hdma->XferAbortCallback != NULL)
-        {
-          hdma->XferAbortCallback(hdma);
-        }
-        return;
-      }
-
-      if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
-      {
-        /* Current memory buffer used is Memory 0 */
-        if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
-        {
-          if(hdma->XferM1CpltCallback != NULL)
-          {
-            /* Transfer complete Callback for memory1 */
-            hdma->XferM1CpltCallback(hdma);
-          }
-        }
-        /* Current memory buffer used is Memory 1 */
-        else
-        {
-          if(hdma->XferCpltCallback != NULL)
-          {
-            /* Transfer complete Callback for memory0 */
-            hdma->XferCpltCallback(hdma);
-          }
-        }
-      }
-      /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
-      else
-      {
-        if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
-        {
-          /* Disable the transfer complete interrupt */
-          hdma->Instance->CR  &= ~(DMA_IT_TC);
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hdma);
-
-          /* Change the DMA state */
-          hdma->State = HAL_DMA_STATE_READY;
-        }
-
-        if(hdma->XferCpltCallback != NULL)
-        {
-          /* Transfer complete callback */
-          hdma->XferCpltCallback(hdma);
-        }
-      }
-    }
-  }
-
-  /* manage error case */
-  if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
-  {
-    if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
-    {
-      hdma->State = HAL_DMA_STATE_ABORT;
-
-      /* Disable the stream */
-      __HAL_DMA_DISABLE(hdma);
-
-      do
-      {
-        if (++count > timeout)
-        {
-          break;
-        }
-      }
-      while((hdma->Instance->CR & DMA_SxCR_EN) != RESET);
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hdma);
-
-      /* Change the DMA state */
-      hdma->State = HAL_DMA_STATE_READY;
-    }
-
-    if(hdma->XferErrorCallback != NULL)
-    {
-      /* Transfer error callback */
-      hdma->XferErrorCallback(hdma);
-    }
-  }
-}
-
-/**
-  * @brief  Register callbacks
-  * @param  hdma:                 pointer to a DMA_HandleTypeDef structure that contains
-  *                               the configuration information for the specified DMA Stream.
-  * @param  CallbackID:           User Callback identifer
-  *                               a DMA_HandleTypeDef structure as parameter.
-  * @param  pCallback:            pointer to private callbacsk function which has pointer to
-  *                               a DMA_HandleTypeDef structure as parameter.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))
-{
-
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hdma);
-
-  if(HAL_DMA_STATE_READY == hdma->State)
-  {
-    switch (CallbackID)
-    {
-    case  HAL_DMA_XFER_CPLT_CB_ID:
-      hdma->XferCpltCallback = pCallback;
-      break;
-
-    case  HAL_DMA_XFER_HALFCPLT_CB_ID:
-      hdma->XferHalfCpltCallback = pCallback;
-      break;
-
-    case  HAL_DMA_XFER_M1CPLT_CB_ID:
-      hdma->XferM1CpltCallback = pCallback;
-      break;
-
-    case  HAL_DMA_XFER_M1HALFCPLT_CB_ID:
-      hdma->XferM1HalfCpltCallback = pCallback;
-      break;
-
-    case  HAL_DMA_XFER_ERROR_CB_ID:
-      hdma->XferErrorCallback = pCallback;
-      break;
-
-    case  HAL_DMA_XFER_ABORT_CB_ID:
-      hdma->XferAbortCallback = pCallback;
-      break;
-
-    default:
-      break;
-    }
-  }
-  else
-  {
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hdma);
-
-  return status;
-}
-
-/**
-  * @brief  UnRegister callbacks
-  * @param  hdma:                 pointer to a DMA_HandleTypeDef structure that contains
-  *                               the configuration information for the specified DMA Stream.
-  * @param  CallbackID:           User Callback identifer
-  *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hdma);
-
-  if(HAL_DMA_STATE_READY == hdma->State)
-  {
-    switch (CallbackID)
-    {
-    case  HAL_DMA_XFER_CPLT_CB_ID:
-      hdma->XferCpltCallback = NULL;
-      break;
-
-    case  HAL_DMA_XFER_HALFCPLT_CB_ID:
-      hdma->XferHalfCpltCallback = NULL;
-      break;
-
-    case  HAL_DMA_XFER_M1CPLT_CB_ID:
-      hdma->XferM1CpltCallback = NULL;
-      break;
-
-    case  HAL_DMA_XFER_M1HALFCPLT_CB_ID:
-      hdma->XferM1HalfCpltCallback = NULL;
-      break;
-
-    case  HAL_DMA_XFER_ERROR_CB_ID:
-      hdma->XferErrorCallback = NULL;
-      break;
-
-    case  HAL_DMA_XFER_ABORT_CB_ID:
-      hdma->XferAbortCallback = NULL;
-      break;
-
-    case   HAL_DMA_XFER_ALL_CB_ID:
-      hdma->XferCpltCallback = NULL;
-      hdma->XferHalfCpltCallback = NULL;
-      hdma->XferM1CpltCallback = NULL;
-      hdma->XferM1HalfCpltCallback = NULL;
-      hdma->XferErrorCallback = NULL;
-      hdma->XferAbortCallback = NULL;
-      break;
-
-    default:
-      status = HAL_ERROR;
-      break;
-    }
-  }
-  else
-  {
-    status = HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hdma);
-
-  return status;
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup DMA_Exported_Functions_Group3
-  *
-@verbatim
- ===============================================================================
-                    ##### State and Errors functions #####
- ===============================================================================
-    [..]
-    This subsection provides functions allowing to
-      (+) Check the DMA state
-      (+) Get error code
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Returns the DMA state.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Stream.
-  * @retval HAL state
-  */
-HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
-{
-  return hdma->State;
-}
-
-/**
-  * @brief  Return the DMA error code
-  * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains
-  *              the configuration information for the specified DMA Stream.
-  * @retval DMA Error Code
-  */
-uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
-{
-  return hdma->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup DMA_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Sets the DMA Transfer parameter.
-  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
-  *                     the configuration information for the specified DMA Stream.
-  * @param  SrcAddress: The source memory Buffer address
-  * @param  DstAddress: The destination memory Buffer address
-  * @param  DataLength: The length of data to be transferred from source to destination
-  * @retval HAL status
-  */
-static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{
-  /* Clear DBM bit */
-  hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM);
-
-  /* Configure DMA Stream data length */
-  hdma->Instance->NDTR = DataLength;
-
-  /* Peripheral to Memory */
-  if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
-  {
-    /* Configure DMA Stream destination address */
-    hdma->Instance->PAR = DstAddress;
-
-    /* Configure DMA Stream source address */
-    hdma->Instance->M0AR = SrcAddress;
-  }
-  /* Memory to Peripheral */
-  else
-  {
-    /* Configure DMA Stream source address */
-    hdma->Instance->PAR = SrcAddress;
-
-    /* Configure DMA Stream destination address */
-    hdma->Instance->M0AR = DstAddress;
-  }
-}
-
-/**
-  * @brief  Returns the DMA Stream base address depending on stream number
-  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
-  *                     the configuration information for the specified DMA Stream.
-  * @retval Stream base address
-  */
-uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
-{
-  uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U;
-
-  /* lookup table for necessary bitshift of flags within status registers */
-  static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};
-  hdma->StreamIndex = flagBitshiftOffset[stream_number];
-
-  if (stream_number > 3U)
-  {
-    /* return pointer to HISR and HIFCR */
-    hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U);
-  }
-  else
-  {
-    /* return pointer to LISR and LIFCR */
-    hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU));
-  }
-
-  return hdma->StreamBaseAddress;
-}
-
-/**
-  * @brief  Check compatibility between FIFO threshold level and size of the memory burst
-  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
-  *                     the configuration information for the specified DMA Stream.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  uint32_t tmp = hdma->Init.FIFOThreshold;
-
-  /* Memory Data size equal to Byte */
-  if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)
-  {
-    switch (tmp)
-    {
-      case DMA_FIFO_THRESHOLD_1QUARTERFULL:
-        if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
-        {
-          status = HAL_ERROR;
-        }
-        break;
-      case DMA_FIFO_THRESHOLD_HALFFULL:
-        if (hdma->Init.MemBurst == DMA_MBURST_INC16)
-        {
-          status = HAL_ERROR;
-        }
-        break;
-      case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
-        if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
-        {
-          status = HAL_ERROR;
-        }
-        break;
-      case DMA_FIFO_THRESHOLD_FULL:
-        break;
-      default:
-        break;
-    }
-  }
-
-  /* Memory Data size equal to Half-Word */
-  else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
-  {
-    switch (tmp)
-    {
-      case DMA_FIFO_THRESHOLD_1QUARTERFULL:
-        status = HAL_ERROR;
-        break;
-      case DMA_FIFO_THRESHOLD_HALFFULL:
-        if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
-        {
-          status = HAL_ERROR;
-        }
-        break;
-      case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
-        status = HAL_ERROR;
-        break;
-      case DMA_FIFO_THRESHOLD_FULL:
-        if (hdma->Init.MemBurst == DMA_MBURST_INC16)
-        {
-          status = HAL_ERROR;
-        }
-        break;
-      default:
-        break;
-    }
-  }
-
-  /* Memory Data size equal to Word */
-  else
-  {
-    switch (tmp)
-    {
-      case DMA_FIFO_THRESHOLD_1QUARTERFULL:
-      case DMA_FIFO_THRESHOLD_HALFFULL:
-      case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
-        status = HAL_ERROR;
-        break;
-      case DMA_FIFO_THRESHOLD_FULL:
-        if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
-        {
-          status = HAL_ERROR;
-        }
-		break;
-      default:
-        break;
-    }
-  }
-
-  return status;
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_DMA_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_flash.c b/stmhal/hal/f7/src/stm32f7xx_hal_flash.c
deleted file mode 100644
index b28b2768dd..0000000000
--- a/stmhal/hal/f7/src/stm32f7xx_hal_flash.c
+++ /dev/null
@@ -1,822 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_flash.c
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   FLASH HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the internal FLASH memory:
-  *           + Program operations functions
-  *           + Memory Control functions
-  *           + Peripheral Errors functions
-  *
-  @verbatim
-  ==============================================================================
-                        ##### FLASH peripheral features #####
-  ==============================================================================
-
-  [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
-       to the Flash memory. It implements the erase and program Flash memory operations
-       and the read and write protection mechanisms.
-
-  [..] The Flash memory interface accelerates code execution with a system of instruction
-       prefetch and cache lines.
-
-  [..] The FLASH main features are:
-      (+) Flash memory read operations
-      (+) Flash memory program/erase operations
-      (+) Read / write protections
-      (+) Prefetch on I-Code
-      (+) 64 cache lines of 128 bits on I-Code
-      (+) 8 cache lines of 128 bits on D-Code
-
-                     ##### How to use this driver #####
-  ==============================================================================
-    [..]
-      This driver provides functions and macros to configure and program the FLASH
-      memory of all STM32F7xx devices.
-
-      (#) FLASH Memory IO Programming functions:
-           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
-                HAL_FLASH_Lock() functions
-           (++) Program functions: byte, half word, word and double word
-           (++) There Two modes of programming :
-            (+++) Polling mode using HAL_FLASH_Program() function
-            (+++) Interrupt mode using HAL_FLASH_Program_IT() function
-
-      (#) Interrupts and flags management functions :
-           (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
-           (++) Wait for last FLASH operation according to its status
-           (++) Get error flag status by calling HAL_SetErrorCode()
-    [..]
-      In addition to these functions, this driver includes a set of macros allowing
-      to handle the following operations:
-       (+) Set the latency
-       (+) Enable/Disable the prefetch buffer
-       (+) Enable/Disable the Instruction cache and the Data cache
-       (+) Reset the Instruction cache and the Data cache
-       (+) Enable/Disable the FLASH interrupts
-       (+) Monitor the FLASH flags status
-    [..]
-	(@) For any Flash memory program operation (erase or program), the CPU clock frequency
-        (HCLK) must be at least 1MHz.
-	(@) The contents of the Flash memory are not guaranteed if a device reset occurs during
-	    a Flash memory operation.
-    (@) Any attempt to read the Flash memory while it is being written or erased, causes the
-	    bus to stall. Read operations are processed correctly once the program operation has
-		completed. This means that code or data fetches cannot be performed while a write/erase
-		operation is ongoing.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup FLASH FLASH
-  * @brief FLASH HAL module driver
-  * @{
-  */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup FLASH_Private_Constants
-  * @{
-  */
-#define SECTOR_MASK               ((uint32_t)0xFFFFFF07U)
-#define FLASH_TIMEOUT_VALUE       ((uint32_t)50000U)/* 50 s */
-/**
-  * @}
-  */
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @addtogroup FLASH_Private_Variables
-  * @{
-  */
-/* Variable used for Erase sectors under interruption */
-FLASH_ProcessTypeDef pFlash;
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup FLASH_Private_Functions
-  * @{
-  */
-/* Program operations */
-static void   FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);
-static void   FLASH_Program_Word(uint32_t Address, uint32_t Data);
-static void   FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);
-static void   FLASH_Program_Byte(uint32_t Address, uint8_t Data);
-static void   FLASH_SetErrorCode(void);
-
-HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
-  * @{
-  */
-
-/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
- *  @brief   Programming operation functions
- *
-@verbatim
- ===============================================================================
-                  ##### Programming operation functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to manage the FLASH
-    program operations.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Program byte, halfword, word or double word at a specified address
-  * @param  TypeProgram:  Indicate the way to program at a specified address.
-  *                           This parameter can be a value of @ref FLASH_Type_Program
-  * @param  Address:  specifies the address to be programmed.
-  * @param  Data: specifies the data to be programmed
-  *
-  * @retval HAL_StatusTypeDef HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
-{
-  HAL_StatusTypeDef status = HAL_ERROR;
-
-  /* Process Locked */
-  __HAL_LOCK(&pFlash);
-
-  /* Check the parameters */
-  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-  if(status == HAL_OK)
-  {
-    switch(TypeProgram)
-    {
-      case FLASH_TYPEPROGRAM_BYTE :
-      {
-        /*Program byte (8-bit) at a specified address.*/
-        FLASH_Program_Byte(Address, (uint8_t) Data);
-        break;
-      }
-
-      case FLASH_TYPEPROGRAM_HALFWORD :
-      {
-        /*Program halfword (16-bit) at a specified address.*/
-        FLASH_Program_HalfWord(Address, (uint16_t) Data);
-        break;
-      }
-
-      case FLASH_TYPEPROGRAM_WORD :
-      {
-        /*Program word (32-bit) at a specified address.*/
-        FLASH_Program_Word(Address, (uint32_t) Data);
-        break;
-      }
-
-      case FLASH_TYPEPROGRAM_DOUBLEWORD :
-      {
-        /*Program double word (64-bit) at a specified address.*/
-        FLASH_Program_DoubleWord(Address, Data);
-        break;
-      }
-      default :
-        break;
-    }
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-    /* If the program operation is completed, disable the PG Bit */
-    FLASH->CR &= (~FLASH_CR_PG);
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(&pFlash);
-
-  return status;
-}
-
-/**
-  * @brief   Program byte, halfword, word or double word at a specified address  with interrupt enabled.
-  * @param  TypeProgram:  Indicate the way to program at a specified address.
-  *                           This parameter can be a value of @ref FLASH_Type_Program
-  * @param  Address:  specifies the address to be programmed.
-  * @param  Data: specifies the data to be programmed
-  *
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process Locked */
-  __HAL_LOCK(&pFlash);
-
-  /* Check the parameters */
-  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
-
-  /* Enable End of FLASH Operation interrupt */
-  __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
-
-  /* Enable Error source interrupt */
-  __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
-
-  /* Clear pending flags (if any) */
-  __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP    | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\
-                         FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_ERSERR);
-
-  pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;
-  pFlash.Address = Address;
-
-  switch(TypeProgram)
-  {
-    case FLASH_TYPEPROGRAM_BYTE :
-    {
-      /*Program byte (8-bit) at a specified address.*/
-      FLASH_Program_Byte(Address, (uint8_t) Data);
-      break;
-    }
-
-    case FLASH_TYPEPROGRAM_HALFWORD :
-    {
-      /*Program halfword (16-bit) at a specified address.*/
-      FLASH_Program_HalfWord(Address, (uint16_t) Data);
-      break;
-    }
-
-    case FLASH_TYPEPROGRAM_WORD :
-    {
-      /*Program word (32-bit) at a specified address.*/
-      FLASH_Program_Word(Address, (uint32_t) Data);
-      break;
-    }
-
-    case FLASH_TYPEPROGRAM_DOUBLEWORD :
-    {
-      /*Program double word (64-bit) at a specified address.*/
-      FLASH_Program_DoubleWord(Address, Data);
-      break;
-    }
-    default :
-      break;
-  }
-  return status;
-}
-
-/**
-  * @brief This function handles FLASH interrupt request.
-  * @retval None
-  */
-void HAL_FLASH_IRQHandler(void)
-{
-  uint32_t temp = 0;
-
-  /* If the program operation is completed, disable the PG Bit */
-  FLASH->CR &= (~FLASH_CR_PG);
-
-  /* If the erase operation is completed, disable the SER Bit */
-  FLASH->CR &= (~FLASH_CR_SER);
-  FLASH->CR &= SECTOR_MASK;
-
-  /* if the erase operation is completed, disable the MER Bit */
-  FLASH->CR &= (~FLASH_MER_BIT);
-
-  /* Check FLASH End of Operation flag  */
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)
-  {
-    /* Clear FLASH End of Operation pending bit */
-    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
-
-    switch (pFlash.ProcedureOnGoing)
-    {
-      case FLASH_PROC_SECTERASE :
-      {
-        /* Nb of sector to erased can be decreased */
-        pFlash.NbSectorsToErase--;
-
-        /* Check if there are still sectors to erase */
-        if(pFlash.NbSectorsToErase != 0)
-        {
-          temp = pFlash.Sector;
-          /* Indicate user which sector has been erased */
-          HAL_FLASH_EndOfOperationCallback(temp);
-
-          /* Increment sector number */
-          temp = ++pFlash.Sector;
-          FLASH_Erase_Sector(temp, pFlash.VoltageForErase);
-        }
-        else
-        {
-          /* No more sectors to Erase, user callback can be called.*/
-          /* Reset Sector and stop Erase sectors procedure */
-          pFlash.Sector = temp = 0xFFFFFFFFU;
-          /* FLASH EOP interrupt user callback */
-          HAL_FLASH_EndOfOperationCallback(temp);
-          /* Sector Erase procedure is completed */
-          pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
-        }
-        break;
-      }
-
-      case FLASH_PROC_MASSERASE :
-      {
-        /* MassErase ended. Return the selected bank : in this product we don't have Banks */
-        /* FLASH EOP interrupt user callback */
-        HAL_FLASH_EndOfOperationCallback(0);
-        /* MAss Erase procedure is completed */
-        pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
-        break;
-      }
-
-      case FLASH_PROC_PROGRAM :
-      {
-        /*Program ended. Return the selected address*/
-        /* FLASH EOP interrupt user callback */
-        HAL_FLASH_EndOfOperationCallback(pFlash.Address);
-        /* Programming procedure is completed */
-        pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
-        break;
-      }
-      default :
-        break;
-    }
-  }
-
-  /* Check FLASH operation error flags */
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ALL_ERRORS) != RESET)
-  {
-    switch (pFlash.ProcedureOnGoing)
-    {
-      case FLASH_PROC_SECTERASE :
-      {
-        /* return the faulty sector */
-        temp = pFlash.Sector;
-        pFlash.Sector = 0xFFFFFFFFU;
-        break;
-      }
-      case FLASH_PROC_MASSERASE :
-      {
-        /* No return in case of Mass Erase */
-        temp = 0;
-        break;
-      }
-      case FLASH_PROC_PROGRAM :
-      {
-        /*return the faulty address*/
-        temp = pFlash.Address;
-        break;
-      }
-    default :
-      break;
-    }
-    /*Save the Error code*/
-    FLASH_SetErrorCode();
-
-    /* FLASH error interrupt user callback */
-    HAL_FLASH_OperationErrorCallback(temp);
-
-    /*Stop the procedure ongoing */
-    pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
-  }
-
-  if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
-  {
-    /* Disable End of FLASH Operation interrupt */
-    __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP);
-
-    /* Disable Error source interrupt */
-    __HAL_FLASH_DISABLE_IT(FLASH_IT_ERR);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(&pFlash);
-  }
-
-}
-
-/**
-  * @brief  FLASH end of operation interrupt callback
-  * @param  ReturnValue: The value saved in this parameter depends on the ongoing procedure
-  *                 - Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that
-  *                                  all the selected sectors have been erased)
-  *                 - Program      : Address which was selected for data program
-  *                 - Mass Erase   : No return value expected
-  * @retval None
-  */
-__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(ReturnValue);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-  the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
-  */
-}
-
-/**
-  * @brief  FLASH operation error interrupt callback
-  * @param  ReturnValue: The value saved in this parameter depends on the ongoing procedure
-  *                 - Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that
-  *                                  all the selected sectors have been erased)
-  *                 - Program      : Address which was selected for data program
-  *                 - Mass Erase   : No return value expected
-  * @retval None
-  */
-__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(ReturnValue);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-  the HAL_FLASH_OperationErrorCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
- *  @brief   management functions
- *
-@verbatim
- ===============================================================================
-                      ##### Peripheral Control functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to control the FLASH
-    memory operations.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Unlock the FLASH control register access
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_Unlock(void)
-{
-  if((FLASH->CR & FLASH_CR_LOCK) != RESET)
-  {
-    /* Authorize the FLASH Registers access */
-    FLASH->KEYR = FLASH_KEY1;
-    FLASH->KEYR = FLASH_KEY2;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Locks the FLASH control register access
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_Lock(void)
-{
-  /* Set the LOCK Bit to lock the FLASH Registers access */
-  FLASH->CR |= FLASH_CR_LOCK;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Unlock the FLASH Option Control Registers access.
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
-{
-  if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET)
-  {
-    /* Authorizes the Option Byte register programming */
-    FLASH->OPTKEYR = FLASH_OPT_KEY1;
-    FLASH->OPTKEYR = FLASH_OPT_KEY2;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Lock the FLASH Option Control Registers access.
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
-{
-  /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
-  FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Launch the option byte loading.
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
-{
-  /* Set the OPTSTRT bit in OPTCR register */
-  FLASH->OPTCR |= FLASH_OPTCR_OPTSTRT;
-
-  /* Wait for last operation to be completed */
-  return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions
- *  @brief   Peripheral Errors functions
- *
-@verbatim
- ===============================================================================
-                ##### Peripheral Errors functions #####
- ===============================================================================
-    [..]
-    This subsection permits to get in run-time Errors of the FLASH peripheral.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Get the specific FLASH error flag.
-  * @retval FLASH_ErrorCode: The returned value can be:
-  *            @arg FLASH_ERROR_ERS: FLASH Erasing Sequence error flag
-  *            @arg FLASH_ERROR_PGP: FLASH Programming Parallelism error flag
-  *            @arg FLASH_ERROR_PGA: FLASH Programming Alignment error flag
-  *            @arg FLASH_ERROR_WRP: FLASH Write protected error flag
-  *            @arg FLASH_ERROR_OPERATION: FLASH operation Error flag
-  */
-uint32_t HAL_FLASH_GetError(void)
-{
-   return pFlash.ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @brief  Wait for a FLASH operation to complete.
-  * @param  Timeout: maximum flash operationtimeout
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
-{
-  uint32_t tickstart = 0;
-
-  /* Clear Error Code */
-  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
-  /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
-     Even if the FLASH operation fails, the BUSY flag will be reset and an error
-     flag will be set */
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET)
-  {
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ALL_ERRORS) != RESET)
-  {
-    /*Save the error code*/
-    FLASH_SetErrorCode();
-    return HAL_ERROR;
-  }
-
-  /* Check FLASH End of Operation flag  */
-  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)
-  {
-    /* Clear FLASH End of Operation pending bit */
-    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
-  }
-
-  /* If there is an error flag set */
-  return HAL_OK;
-
-}
-
-/**
-  * @brief  Program a double word (64-bit) at a specified address.
-  * @note   This function must be used when the device voltage range is from
-  *         2.7V to 3.6V and an External Vpp is present.
-  *
-  * @note   If an erase and a program operations are requested simultaneously,
-  *         the erase operation is performed before the program one.
-  *
-  * @param  Address: specifies the address to be programmed.
-  * @param  Data: specifies the data to be programmed.
-  * @retval None
-  */
-static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
-{
-  /* Check the parameters */
-  assert_param(IS_FLASH_ADDRESS(Address));
-
-  /* If the previous operation is completed, proceed to program the new data */
-  FLASH->CR &= CR_PSIZE_MASK;
-  FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;
-  FLASH->CR |= FLASH_CR_PG;
-
-  *(__IO uint64_t*)Address = Data;
-
-  /* Data synchronous Barrier (DSB) Just after the write operation
-     This will force the CPU to respect the sequence of instruction (no optimization).*/
-  __DSB();
-}
-
-
-/**
-  * @brief  Program word (32-bit) at a specified address.
-  * @note   This function must be used when the device voltage range is from
-  *         2.7V to 3.6V.
-  *
-  * @note   If an erase and a program operations are requested simultaneously,
-  *         the erase operation is performed before the program one.
-  *
-  * @param  Address: specifies the address to be programmed.
-  * @param  Data: specifies the data to be programmed.
-  * @retval None
-  */
-static void FLASH_Program_Word(uint32_t Address, uint32_t Data)
-{
-  /* Check the parameters */
-  assert_param(IS_FLASH_ADDRESS(Address));
-
-  /* If the previous operation is completed, proceed to program the new data */
-  FLASH->CR &= CR_PSIZE_MASK;
-  FLASH->CR |= FLASH_PSIZE_WORD;
-  FLASH->CR |= FLASH_CR_PG;
-
-  *(__IO uint32_t*)Address = Data;
-
-  /* Data synchronous Barrier (DSB) Just after the write operation
-     This will force the CPU to respect the sequence of instruction (no optimization).*/
-  __DSB();
-}
-
-/**
-  * @brief  Program a half-word (16-bit) at a specified address.
-  * @note   This function must be used when the device voltage range is from
-  *         2.7V to 3.6V.
-  *
-  * @note   If an erase and a program operations are requested simultaneously,
-  *         the erase operation is performed before the program one.
-  *
-  * @param  Address: specifies the address to be programmed.
-  * @param  Data: specifies the data to be programmed.
-  * @retval None
-  */
-static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
-{
-  /* Check the parameters */
-  assert_param(IS_FLASH_ADDRESS(Address));
-
-  /* If the previous operation is completed, proceed to program the new data */
-  FLASH->CR &= CR_PSIZE_MASK;
-  FLASH->CR |= FLASH_PSIZE_HALF_WORD;
-  FLASH->CR |= FLASH_CR_PG;
-
-  *(__IO uint16_t*)Address = Data;
-
-  /* Data synchronous Barrier (DSB) Just after the write operation
-     This will force the CPU to respect the sequence of instruction (no optimization).*/
-  __DSB();
-
-}
-
-/**
-  * @brief  Program byte (8-bit) at a specified address.
-  * @note   This function must be used when the device voltage range is from
-  *         2.7V to 3.6V.
-  *
-  * @note   If an erase and a program operations are requested simultaneously,
-  *         the erase operation is performed before the program one.
-  *
-  * @param  Address: specifies the address to be programmed.
-  * @param  Data: specifies the data to be programmed.
-  * @retval None
-  */
-static void FLASH_Program_Byte(uint32_t Address, uint8_t Data)
-{
-  /* Check the parameters */
-  assert_param(IS_FLASH_ADDRESS(Address));
-
-  /* If the previous operation is completed, proceed to program the new data */
-  FLASH->CR &= CR_PSIZE_MASK;
-  FLASH->CR |= FLASH_PSIZE_BYTE;
-  FLASH->CR |= FLASH_CR_PG;
-
-  *(__IO uint8_t*)Address = Data;
-
-  /* Data synchronous Barrier (DSB) Just after the write operation
-     This will force the CPU to respect the sequence of instruction (no optimization).*/
-  __DSB();
-}
-
-/**
-  * @brief  Set the specific FLASH error flag.
-  * @retval None
-  */
-static void FLASH_SetErrorCode(void)
-{
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET)
-  {
-    pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION;
-  }
-
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET)
-  {
-   pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
-  }
-
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET)
-  {
-   pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;
-  }
-
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGPERR) != RESET)
-  {
-    pFlash.ErrorCode |= HAL_FLASH_ERROR_PGP;
-  }
-
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ERSERR) != RESET)
-  {
-    pFlash.ErrorCode |= HAL_FLASH_ERROR_ERS;
-  }
-
-  /* Clear error programming flags */
-  __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS);
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_flash_ex.c b/stmhal/hal/f7/src/stm32f7xx_hal_flash_ex.c
deleted file mode 100644
index b6f2a3e3c5..0000000000
--- a/stmhal/hal/f7/src/stm32f7xx_hal_flash_ex.c
+++ /dev/null
@@ -1,1038 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_flash_ex.c
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   Extended FLASH HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the FLASH extension peripheral:
-  *           + Extended programming operations functions
-  *
-  @verbatim
-  ==============================================================================
-                   ##### Flash Extension features #####
-  ==============================================================================
-
-  [..] Comparing to other previous devices, the FLASH interface for STM32F76xx/STM32F77xx
-       devices contains the following additional features
-
-       (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
-           capability (RWW)
-       (+) Dual bank memory organization
-       (+) Dual boot mode
-
-                      ##### How to use this driver #####
-  ==============================================================================
-  [..] This driver provides functions to configure and program the FLASH memory
-       of all STM32F7xx devices. It includes
-      (#) FLASH Memory Erase functions:
-           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
-                HAL_FLASH_Lock() functions
-           (++) Erase function: Erase sector, erase all sectors
-           (++) There are two modes of erase :
-             (+++) Polling Mode using HAL_FLASHEx_Erase()
-             (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
-
-      (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to :
-           (++) Set/Reset the write protection
-           (++) Set the Read protection Level
-           (++) Set the BOR level
-           (++) Program the user Option Bytes
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup FLASHEx FLASHEx
-  * @brief FLASH HAL Extension module driver
-  * @{
-  */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup FLASHEx_Private_Constants
-  * @{
-  */
-#define SECTOR_MASK               0xFFFFFF07U
-#define FLASH_TIMEOUT_VALUE       50000U/* 50 s */
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @addtogroup FLASHEx_Private_Variables
-  * @{
-  */
-extern FLASH_ProcessTypeDef pFlash;
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup FLASHEx_Private_Functions
-  * @{
-  */
-/* Option bytes control */
-static HAL_StatusTypeDef  FLASH_OB_EnableWRP(uint32_t WRPSector);
-static HAL_StatusTypeDef  FLASH_OB_DisableWRP(uint32_t WRPSector);
-static HAL_StatusTypeDef  FLASH_OB_RDP_LevelConfig(uint8_t Level);
-static HAL_StatusTypeDef  FLASH_OB_BOR_LevelConfig(uint8_t Level);
-static HAL_StatusTypeDef  FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address);
-static uint32_t           FLASH_OB_GetUser(void);
-static uint32_t           FLASH_OB_GetWRP(void);
-static uint8_t            FLASH_OB_GetRDP(void);
-static uint32_t           FLASH_OB_GetBOR(void);
-static uint32_t           FLASH_OB_GetBootAddress(uint32_t BootOption);
-
-#if defined (FLASH_OPTCR_nDBANK)
-static void               FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks);
-static HAL_StatusTypeDef  FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, \
-                                              uint32_t Iwdgstdby, uint32_t NDBank, uint32_t NDBoot);
-#else
-static void               FLASH_MassErase(uint8_t VoltageRange);
-static HAL_StatusTypeDef  FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby);
-#endif /* FLASH_OPTCR_nDBANK */
-
-extern HAL_StatusTypeDef  FLASH_WaitForLastOperation(uint32_t Timeout);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
-  * @{
-  */
-
-/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
- *  @brief   Extended IO operation functions
- *
-@verbatim
- ===============================================================================
-                ##### Extended programming operation functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to manage the Extension FLASH
-    programming operations Operations.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Perform a mass erase or erase the specified FLASH memory sectors
-  * @param[in]  pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
-  *         contains the configuration information for the erasing.
-  *
-  * @param[out]  SectorError: pointer to variable  that
-  *         contains the configuration information on faulty sector in case of error
-  *         (0xFFFFFFFF means that all the sectors have been correctly erased)
-  *
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
-{
-  HAL_StatusTypeDef status = HAL_ERROR;
-  uint32_t index = 0;
-
-  /* Process Locked */
-  __HAL_LOCK(&pFlash);
-
-  /* Check the parameters */
-  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-  if(status == HAL_OK)
-  {
-    /*Initialization of SectorError variable*/
-    *SectorError = 0xFFFFFFFFU;
-
-    if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
-    {
-      /*Mass erase to be done*/
-#if defined (FLASH_OPTCR_nDBANK)
-      FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);
-#else
-      FLASH_MassErase((uint8_t) pEraseInit->VoltageRange);
-#endif /* FLASH_OPTCR_nDBANK */
-
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-      /* if the erase operation is completed, disable the MER Bit */
-      FLASH->CR &= (~FLASH_MER_BIT);
-    }
-    else
-    {
-      /* Check the parameters */
-      assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
-
-      /* Erase by sector by sector to be done*/
-      for(index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++)
-      {
-        FLASH_Erase_Sector(index, (uint8_t) pEraseInit->VoltageRange);
-
-        /* Wait for last operation to be completed */
-        status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-        /* If the erase operation is completed, disable the SER Bit and SNB Bits */
-        CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB));
-
-        if(status != HAL_OK)
-        {
-          /* In case of error, stop erase procedure and return the faulty sector*/
-          *SectorError = index;
-          break;
-        }
-      }
-    }
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(&pFlash);
-
-  return status;
-}
-
-/**
-  * @brief  Perform a mass erase or erase the specified FLASH memory sectors  with interrupt enabled
-  * @param  pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
-  *         contains the configuration information for the erasing.
-  *
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process Locked */
-  __HAL_LOCK(&pFlash);
-
-  /* Check the parameters */
-  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
-
-  /* Enable End of FLASH Operation interrupt */
-  __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
-
-  /* Enable Error source interrupt */
-  __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
-
-  /* Clear pending flags (if any) */
-  __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP    | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\
-                         FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_ERSERR);
-
-  if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
-  {
-    /*Mass erase to be done*/
-    pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;
-#if defined (FLASH_OPTCR_nDBANK)
-    FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);
-#else
-    FLASH_MassErase((uint8_t) pEraseInit->VoltageRange);
-#endif /* FLASH_OPTCR_nDBANK */
-  }
-  else
-  {
-    /* Erase by sector to be done*/
-
-    /* Check the parameters */
-    assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
-
-    pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE;
-    pFlash.NbSectorsToErase = pEraseInit->NbSectors;
-    pFlash.Sector = pEraseInit->Sector;
-    pFlash.VoltageForErase = (uint8_t)pEraseInit->VoltageRange;
-
-    /*Erase 1st sector and wait for IT*/
-    FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->VoltageRange);
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Program option bytes
-  * @param  pOBInit: pointer to an FLASH_OBInitStruct structure that
-  *         contains the configuration information for the programming.
-  *
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
-{
-  HAL_StatusTypeDef status = HAL_ERROR;
-
-  /* Process Locked */
-  __HAL_LOCK(&pFlash);
-
-  /* Check the parameters */
-  assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
-
-  /* Write protection configuration */
-  if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
-  {
-    assert_param(IS_WRPSTATE(pOBInit->WRPState));
-    if(pOBInit->WRPState == OB_WRPSTATE_ENABLE)
-    {
-      /*Enable of Write protection on the selected Sector*/
-      status = FLASH_OB_EnableWRP(pOBInit->WRPSector);
-    }
-    else
-    {
-      /*Disable of Write protection on the selected Sector*/
-      status = FLASH_OB_DisableWRP(pOBInit->WRPSector);
-    }
-  }
-
-  /* Read protection configuration */
-  if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)
-  {
-    status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel);
-  }
-
-  /* USER  configuration */
-  if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)
-  {
-#if defined (FLASH_OPTCR_nDBANK)
-    status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW,
-                                 pOBInit->USERConfig & OB_IWDG_SW,
-                                 pOBInit->USERConfig & OB_STOP_NO_RST,
-                                 pOBInit->USERConfig & OB_STDBY_NO_RST,
-                                 pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE,
-                                 pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE,
-                                 pOBInit->USERConfig & OB_NDBANK_SINGLE_BANK,
-                                 pOBInit->USERConfig & OB_DUAL_BOOT_DISABLE);
-#else
-    status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW,
-                                 pOBInit->USERConfig & OB_IWDG_SW,
-                                 pOBInit->USERConfig & OB_STOP_NO_RST,
-                                 pOBInit->USERConfig & OB_STDBY_NO_RST,
-                                 pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE,
-                                 pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE);
-#endif /* FLASH_OPTCR_nDBANK */
-  }
-
-  /* BOR Level  configuration */
-  if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR)
-  {
-    status = FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel);
-  }
-
-  /* Boot 0 Address configuration */
-  if((pOBInit->OptionType & OPTIONBYTE_BOOTADDR_0) == OPTIONBYTE_BOOTADDR_0)
-  {
-    status = FLASH_OB_BootAddressConfig(OPTIONBYTE_BOOTADDR_0, pOBInit->BootAddr0);
-  }
-
-  /* Boot 1 Address configuration */
-  if((pOBInit->OptionType & OPTIONBYTE_BOOTADDR_1) == OPTIONBYTE_BOOTADDR_1)
-  {
-    status = FLASH_OB_BootAddressConfig(OPTIONBYTE_BOOTADDR_1, pOBInit->BootAddr1);
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(&pFlash);
-
-  return status;
-}
-
-/**
-  * @brief  Get the Option byte configuration
-  * @param  pOBInit: pointer to an FLASH_OBInitStruct structure that
-  *         contains the configuration information for the programming.
-  *
-  * @retval None
-  */
-void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
-{
-  pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
-	                OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1;
-
-  /*Get WRP*/
-  pOBInit->WRPSector = FLASH_OB_GetWRP();
-
-  /*Get RDP Level*/
-  pOBInit->RDPLevel = FLASH_OB_GetRDP();
-
-  /*Get USER*/
-  pOBInit->USERConfig = FLASH_OB_GetUser();
-
-  /*Get BOR Level*/
-  pOBInit->BORLevel = FLASH_OB_GetBOR();
-
-  /*Get Boot Address when Boot pin = 0 */
-  pOBInit->BootAddr0 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_0);
-
-  /*Get Boot Address when Boot pin = 1 */
-  pOBInit->BootAddr1 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_1);
-}
-/**
-  * @}
-  */
-
-#if defined (FLASH_OPTCR_nDBANK)
-/**
-  * @brief  Full erase of FLASH memory sectors
-  * @param  VoltageRange: The device voltage range which defines the erase parallelism.
-  *          This parameter can be one of the following values:
-  *            @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
-  *                                  the operation will be done by byte (8-bit)
-  *            @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
-  *                                  the operation will be done by half word (16-bit)
-  *            @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
-  *                                  the operation will be done by word (32-bit)
-  *            @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
-  *                                  the operation will be done by double word (64-bit)
-  * @param  Banks: Banks to be erased
-  *          This parameter can be one of the following values:
-  *            @arg FLASH_BANK_1: Bank1 to be erased
-  *            @arg FLASH_BANK_2: Bank2 to be erased
-  *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
-  *
-  * @retval HAL Status
-  */
-static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)
-{
-  /* Check the parameters */
-  assert_param(IS_VOLTAGERANGE(VoltageRange));
-  assert_param(IS_FLASH_BANK(Banks));
-
-  /* if the previous operation is completed, proceed to erase all sectors */
-  FLASH->CR &= CR_PSIZE_MASK;
-  if(Banks == FLASH_BANK_BOTH)
-  {
-    /* bank1 & bank2 will be erased*/
-    FLASH->CR |= FLASH_MER_BIT;
-  }
-  else if(Banks == FLASH_BANK_2)
-  {
-    /*Only bank2 will be erased*/
-    FLASH->CR |= FLASH_CR_MER2;
-  }
-  else
-  {
-    /*Only bank1 will be erased*/
-    FLASH->CR |= FLASH_CR_MER1;
-  }
-  FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8);
-  /* Data synchronous Barrier (DSB) Just after the write operation
-     This will force the CPU to respect the sequence of instruction (no optimization).*/
-  __DSB();
-}
-
-/**
-  * @brief  Erase the specified FLASH memory sector
-  * @param  Sector: FLASH sector to erase
-  *         The value of this parameter depend on device used within the same series
-  * @param  VoltageRange: The device voltage range which defines the erase parallelism.
-  *          This parameter can be one of the following values:
-  *            @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
-  *                                  the operation will be done by byte (8-bit)
-  *            @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
-  *                                  the operation will be done by half word (16-bit)
-  *            @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
-  *                                  the operation will be done by word (32-bit)
-  *            @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
-  *                                  the operation will be done by double word (64-bit)
-  *
-  * @retval None
-  */
-void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
-{
-  uint32_t tmp_psize = 0;
-
-  /* Check the parameters */
-  assert_param(IS_FLASH_SECTOR(Sector));
-  assert_param(IS_VOLTAGERANGE(VoltageRange));
-
-  if(VoltageRange == FLASH_VOLTAGE_RANGE_1)
-  {
-     tmp_psize = FLASH_PSIZE_BYTE;
-  }
-  else if(VoltageRange == FLASH_VOLTAGE_RANGE_2)
-  {
-    tmp_psize = FLASH_PSIZE_HALF_WORD;
-  }
-  else if(VoltageRange == FLASH_VOLTAGE_RANGE_3)
-  {
-    tmp_psize = FLASH_PSIZE_WORD;
-  }
-  else
-  {
-    tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
-  }
-
-  /* Need to add offset of 4 when sector higher than FLASH_SECTOR_11 */
-  if(Sector > FLASH_SECTOR_11)
-  {
-    Sector += 4;
-  }
-
-  /* If the previous operation is completed, proceed to erase the sector */
-  FLASH->CR &= CR_PSIZE_MASK;
-  FLASH->CR |= tmp_psize;
-  CLEAR_BIT(FLASH->CR, FLASH_CR_SNB);
-  FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB));
-  FLASH->CR |= FLASH_CR_STRT;
-
-  /* Data synchronous Barrier (DSB) Just after the write operation
-     This will force the CPU to respect the sequence of instruction (no optimization).*/
-  __DSB();
-}
-
-/**
-  * @brief  Return the FLASH Write Protection Option Bytes value.
-  * @retval uint32_t FLASH Write Protection Option Bytes value
-  */
-static uint32_t FLASH_OB_GetWRP(void)
-{
-  /* Return the FLASH write protection Register value */
-  return ((uint32_t)(FLASH->OPTCR & 0x0FFF0000));
-}
-
-/**
-  * @brief  Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
-  * @param  Wwdg: Selects the IWDG mode
-  *          This parameter can be one of the following values:
-  *            @arg OB_WWDG_SW: Software WWDG selected
-  *            @arg OB_WWDG_HW: Hardware WWDG selected
-  * @param  Iwdg: Selects the WWDG mode
-  *          This parameter can be one of the following values:
-  *            @arg OB_IWDG_SW: Software IWDG selected
-  *            @arg OB_IWDG_HW: Hardware IWDG selected
-  * @param  Stop: Reset event when entering STOP mode.
-  *          This parameter  can be one of the following values:
-  *            @arg OB_STOP_NO_RST: No reset generated when entering in STOP
-  *            @arg OB_STOP_RST: Reset generated when entering in STOP
-  * @param  Stdby: Reset event when entering Standby mode.
-  *          This parameter  can be one of the following values:
-  *            @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY
-  *            @arg OB_STDBY_RST: Reset generated when entering in STANDBY
-  * @param  Iwdgstop: Independent watchdog counter freeze in Stop mode.
-  *          This parameter  can be one of the following values:
-  *            @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP
-  *            @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP
-  * @param  Iwdgstdby: Independent watchdog counter freeze in standby mode.
-  *          This parameter  can be one of the following values:
-  *            @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY
-  *            @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY
-  * @param  NDBank: Flash Single Bank mode enabled.
-  *          This parameter  can be one of the following values:
-  *            @arg OB_NDBANK_SINGLE_BANK: enable 256 bits mode (Flash is a single bank)
-  *            @arg OB_NDBANK_DUAL_BANK: disable 256 bits mode (Flash is a dual bank in 128 bits mode)
-  * @param  NDBoot: Flash Dual boot mode disable.
-  *          This parameter  can be one of the following values:
-  *            @arg OB_DUAL_BOOT_DISABLE: Disable Dual Boot
-  *            @arg OB_DUAL_BOOT_ENABLE: Enable Dual Boot
-
-  * @retval HAL Status
-  */
-static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, \
-                                             uint32_t Iwdgstdby, uint32_t NDBank, uint32_t NDBoot)
-{
-  uint32_t useroptionmask = 0x00;
-  uint32_t useroptionvalue = 0x00;
-
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_OB_WWDG_SOURCE(Wwdg));
-  assert_param(IS_OB_IWDG_SOURCE(Iwdg));
-  assert_param(IS_OB_STOP_SOURCE(Stop));
-  assert_param(IS_OB_STDBY_SOURCE(Stdby));
-  assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop));
-  assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby));
-  assert_param(IS_OB_NDBANK(NDBank));
-  assert_param(IS_OB_NDBOOT(NDBoot));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-  if(status == HAL_OK)
-  {
-    useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \
-                      FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY | \
-                      FLASH_OPTCR_nDBOOT | FLASH_OPTCR_nDBANK);
-
-    useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby | NDBoot | NDBank);
-
-    /* Update User Option Byte */
-    MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue);
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Return the FLASH User Option Byte value.
-  * @retval uint32_t FLASH User Option Bytes values: WWDG_SW(Bit4), IWDG_SW(Bit5), nRST_STOP(Bit6),
-  *         nRST_STDBY(Bit7), nDBOOT(Bit28), nDBANK(Bit29), IWDG_STDBY(Bit30) and IWDG_STOP(Bit31).
-  */
-static uint32_t FLASH_OB_GetUser(void)
-{
-  /* Return the User Option Byte */
-  return ((uint32_t)(FLASH->OPTCR & 0xF00000F0U));
-}
-#else
-
-/**
-  * @brief  Full erase of FLASH memory sectors
-  * @param  VoltageRange: The device voltage range which defines the erase parallelism.
-  *          This parameter can be one of the following values:
-  *            @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
-  *                                  the operation will be done by byte (8-bit)
-  *            @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
-  *                                  the operation will be done by half word (16-bit)
-  *            @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
-  *                                  the operation will be done by word (32-bit)
-  *            @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
-  *                                  the operation will be done by double word (64-bit)
-  *
-  * @retval HAL Status
-  */
-static void FLASH_MassErase(uint8_t VoltageRange)
-{
-  /* Check the parameters */
-  assert_param(IS_VOLTAGERANGE(VoltageRange));
-
-  /* if the previous operation is completed, proceed to erase all sectors */
-  FLASH->CR &= CR_PSIZE_MASK;
-  FLASH->CR |= FLASH_CR_MER;
-  FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8);
-  /* Data synchronous Barrier (DSB) Just after the write operation
-     This will force the CPU to respect the sequence of instruction (no optimization).*/
-  __DSB();
-}
-
-/**
-  * @brief  Erase the specified FLASH memory sector
-  * @param  Sector: FLASH sector to erase
-  *         The value of this parameter depend on device used within the same series
-  * @param  VoltageRange: The device voltage range which defines the erase parallelism.
-  *          This parameter can be one of the following values:
-  *            @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
-  *                                  the operation will be done by byte (8-bit)
-  *            @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
-  *                                  the operation will be done by half word (16-bit)
-  *            @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
-  *                                  the operation will be done by word (32-bit)
-  *            @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
-  *                                  the operation will be done by double word (64-bit)
-  *
-  * @retval None
-  */
-void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
-{
-  uint32_t tmp_psize = 0;
-
-  /* Check the parameters */
-  assert_param(IS_FLASH_SECTOR(Sector));
-  assert_param(IS_VOLTAGERANGE(VoltageRange));
-
-  if(VoltageRange == FLASH_VOLTAGE_RANGE_1)
-  {
-     tmp_psize = FLASH_PSIZE_BYTE;
-  }
-  else if(VoltageRange == FLASH_VOLTAGE_RANGE_2)
-  {
-    tmp_psize = FLASH_PSIZE_HALF_WORD;
-  }
-  else if(VoltageRange == FLASH_VOLTAGE_RANGE_3)
-  {
-    tmp_psize = FLASH_PSIZE_WORD;
-  }
-  else
-  {
-    tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
-  }
-
-  /* If the previous operation is completed, proceed to erase the sector */
-  FLASH->CR &= CR_PSIZE_MASK;
-  FLASH->CR |= tmp_psize;
-  FLASH->CR &= SECTOR_MASK;
-  FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB));
-  FLASH->CR |= FLASH_CR_STRT;
-
-  /* Data synchronous Barrier (DSB) Just after the write operation
-     This will force the CPU to respect the sequence of instruction (no optimization).*/
-  __DSB();
-}
-
-/**
-  * @brief  Return the FLASH Write Protection Option Bytes value.
-  * @retval uint32_t FLASH Write Protection Option Bytes value
-  */
-static uint32_t FLASH_OB_GetWRP(void)
-{
-  /* Return the FLASH write protection Register value */
-  return ((uint32_t)(FLASH->OPTCR & 0x00FF0000));
-}
-
-/**
-  * @brief  Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
-  * @param  Wwdg: Selects the IWDG mode
-  *          This parameter can be one of the following values:
-  *            @arg OB_WWDG_SW: Software WWDG selected
-  *            @arg OB_WWDG_HW: Hardware WWDG selected
-  * @param  Iwdg: Selects the WWDG mode
-  *          This parameter can be one of the following values:
-  *            @arg OB_IWDG_SW: Software IWDG selected
-  *            @arg OB_IWDG_HW: Hardware IWDG selected
-  * @param  Stop: Reset event when entering STOP mode.
-  *          This parameter  can be one of the following values:
-  *            @arg OB_STOP_NO_RST: No reset generated when entering in STOP
-  *            @arg OB_STOP_RST: Reset generated when entering in STOP
-  * @param  Stdby: Reset event when entering Standby mode.
-  *          This parameter  can be one of the following values:
-  *            @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY
-  *            @arg OB_STDBY_RST: Reset generated when entering in STANDBY
-  * @param  Iwdgstop: Independent watchdog counter freeze in Stop mode.
-  *          This parameter  can be one of the following values:
-  *            @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP
-  *            @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP
-  * @param  Iwdgstdby: Independent watchdog counter freeze in standby mode.
-  *          This parameter  can be one of the following values:
-  *            @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY
-  *            @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY
-  * @retval HAL Status
-  */
-static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby)
-{
-  uint32_t useroptionmask = 0x00;
-  uint32_t useroptionvalue = 0x00;
-
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_OB_WWDG_SOURCE(Wwdg));
-  assert_param(IS_OB_IWDG_SOURCE(Iwdg));
-  assert_param(IS_OB_STOP_SOURCE(Stop));
-  assert_param(IS_OB_STDBY_SOURCE(Stdby));
-  assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop));
-  assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-  if(status == HAL_OK)
-  {
-    useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \
-                      FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY);
-
-    useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby);
-
-    /* Update User Option Byte */
-    MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue);
-  }
-
-  return status;
-
-}
-
-/**
-  * @brief  Return the FLASH User Option Byte value.
-  * @retval uint32_t FLASH User Option Bytes values: WWDG_SW(Bit4), IWDG_SW(Bit5), nRST_STOP(Bit6),
-  *         nRST_STDBY(Bit7), IWDG_STDBY(Bit30) and IWDG_STOP(Bit31).
-  */
-static uint32_t FLASH_OB_GetUser(void)
-{
-  /* Return the User Option Byte */
-  return ((uint32_t)(FLASH->OPTCR & 0xC00000F0U));
-}
-#endif /* FLASH_OPTCR_nDBANK */
-
-/**
-  * @brief  Enable the write protection of the desired bank1 or bank2 sectors
-  *
-  * @note   When the memory read protection level is selected (RDP level = 1),
-  *         it is not possible to program or erase the flash sector i if CortexM7
-  *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1
-  *
-  * @param  WRPSector: specifies the sector(s) to be write protected.
-  *          This parameter can be one of the following values:
-  *            @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx/STM32F75xxx devices)
-  *              or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for STM32F76xxx/STM32F77xxx devices)
-  *              or a value between OB_WRP_DB_SECTOR_0 and OB_WRP_DB_SECTOR_23 (in Dual Bank mode for STM32F76xxx/STM32F77xxx devices)
-  *            @arg OB_WRP_SECTOR_All
-  *
-  * @retval HAL FLASH State
-  */
-static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_OB_WRP_SECTOR(WRPSector));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-  if(status == HAL_OK)
-  {
-    /*Write protection enabled on sectors */
-    FLASH->OPTCR &= (~WRPSector);
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Disable the write protection of the desired bank1 or bank 2 sectors
-  *
-  * @note   When the memory read protection level is selected (RDP level = 1),
-  *         it is not possible to program or erase the flash sector i if CortexM4
-  *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1
-  *
-  * @param  WRPSector: specifies the sector(s) to be write protected.
-  *          This parameter can be one of the following values:
-  *            @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx/STM32F75xxx devices)
-  *              or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for STM32F76xxx/STM32F77xxx devices)
-  *              or a value between OB_WRP_DB_SECTOR_0 and OB_WRP_DB_SECTOR_23 (in Dual Bank mode for STM32F76xxx/STM32F77xxx devices)
-  *            @arg OB_WRP_Sector_All
-  *
-  *
-  * @retval HAL Status
-  */
-static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_OB_WRP_SECTOR(WRPSector));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-  if(status == HAL_OK)
-  {
-    /* Write protection disabled on sectors */
-    FLASH->OPTCR |= (WRPSector);
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Set the read protection level.
-  * @param  Level: specifies the read protection level.
-  *          This parameter can be one of the following values:
-  *            @arg OB_RDP_LEVEL_0: No protection
-  *            @arg OB_RDP_LEVEL_1: Read protection of the memory
-  *            @arg OB_RDP_LEVEL_2: Full chip protection
-  *
-  * @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
-  *
-  * @retval HAL Status
-  */
-static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_OB_RDP_LEVEL(Level));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-  if(status == HAL_OK)
-  {
-    *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = Level;
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Set the BOR Level.
-  * @param  Level: specifies the Option Bytes BOR Reset Level.
-  *          This parameter can be one of the following values:
-  *            @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
-  *            @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
-  *            @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
-  *            @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V
-  * @retval HAL Status
-  */
-static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level)
-{
-  /* Check the parameters */
-  assert_param(IS_OB_BOR_LEVEL(Level));
-
-  /* Set the BOR Level */
-  MODIFY_REG(FLASH->OPTCR, FLASH_OPTCR_BOR_LEV, Level);
-
-  return HAL_OK;
-
-}
-
-/**
-  * @brief  Configure Boot base address.
-  *
-  * @param   BootOption : specifies Boot base address depending from Boot pin = 0 or pin = 1
-  *          This parameter can be one of the following values:
-  *            @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0
-  *            @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1
-  * @param   Address: specifies Boot base address
-  *          This parameter can be one of the following values:
-  *            @arg OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000)
-  *            @arg OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000)
-  *            @arg OB_BOOTADDR_ITCM_FLASH : Boot from Flash on ITCM interface (0x00200000)
-  *            @arg OB_BOOTADDR_AXIM_FLASH : Boot from Flash on AXIM interface (0x08000000)
-  *            @arg OB_BOOTADDR_DTCM_RAM : Boot from DTCM RAM (0x20000000)
-  *            @arg OB_BOOTADDR_SRAM1 : Boot from SRAM1 (0x20010000)
-  *            @arg OB_BOOTADDR_SRAM2 : Boot from SRAM2 (0x2004C000)
-  *
-  * @retval HAL Status
-  */
-static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_OB_BOOT_ADDRESS(Address));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-  if(status == HAL_OK)
-  {
-    if(BootOption == OPTIONBYTE_BOOTADDR_0)
-    {
-      MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD0, Address);
-    }
-    else
-    {
-      MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD1, (Address << 16));
-    }
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Returns the FLASH Read Protection level.
-  * @retval FlagStatus FLASH ReadOut Protection Status:
-  *         This parameter can be one of the following values:
-  *            @arg OB_RDP_LEVEL_0: No protection
-  *            @arg OB_RDP_LEVEL_1: Read protection of the memory
-  *            @arg OB_RDP_LEVEL_2: Full chip protection
-  */
-static uint8_t FLASH_OB_GetRDP(void)
-{
-  uint8_t readstatus = OB_RDP_LEVEL_0;
-
-  if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS)) == OB_RDP_LEVEL_0)
-  {
-    readstatus = OB_RDP_LEVEL_0;
-  }
-  else if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS)) == OB_RDP_LEVEL_2)
-  {
-    readstatus = OB_RDP_LEVEL_2;
-  }
-  else
-  {
-    readstatus = OB_RDP_LEVEL_1;
-  }
-
-  return readstatus;
-}
-
-/**
-  * @brief  Returns the FLASH BOR level.
-  * @retval uint32_t The FLASH BOR level:
-  *           - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
-  *           - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
-  *           - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
-  *           - OB_BOR_OFF   : Supply voltage ranges from 1.62 to 2.1 V
-  */
-static uint32_t FLASH_OB_GetBOR(void)
-{
-  /* Return the FLASH BOR level */
-  return ((uint32_t)(FLASH->OPTCR & 0x0C));
-}
-
-/**
-  * @brief  Configure Boot base address.
-  *
-  * @param   BootOption : specifies Boot base address depending from Boot pin = 0 or pin = 1
-  *          This parameter can be one of the following values:
-  *            @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0
-  *            @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1
-  *
-  * @retval uint32_t Boot Base Address:
-  *            - OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000)
-  *            - OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000)
-  *            - OB_BOOTADDR_ITCM_FLASH : Boot from Flash on ITCM interface (0x00200000)
-  *            - OB_BOOTADDR_AXIM_FLASH : Boot from Flash on AXIM interface (0x08000000)
-  *            - OB_BOOTADDR_DTCM_RAM : Boot from DTCM RAM (0x20000000)
-  *            - OB_BOOTADDR_SRAM1 : Boot from SRAM1 (0x20010000)
-  *            - OB_BOOTADDR_SRAM2 : Boot from SRAM2 (0x2004C000)
-  */
-static uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption)
-{
-  uint32_t Address = 0;
-
-	/* Return the Boot base Address */
-  if(BootOption == OPTIONBYTE_BOOTADDR_0)
-  {
-    Address = FLASH->OPTCR1 & FLASH_OPTCR1_BOOT_ADD0;
-	}
-  else
-	{
-		Address = ((FLASH->OPTCR1 & FLASH_OPTCR1_BOOT_ADD1) >> 16);
-	}
-
-  return Address;
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_gpio.c b/stmhal/hal/f7/src/stm32f7xx_hal_gpio.c
deleted file mode 100644
index 1cba15df6b..0000000000
--- a/stmhal/hal/f7/src/stm32f7xx_hal_gpio.c
+++ /dev/null
@@ -1,543 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_gpio.c
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   GPIO HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *
-  @verbatim
-  ==============================================================================
-                    ##### GPIO Peripheral features #####
-  ==============================================================================
-  [..]
-  Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
-  port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
-  in several modes:
-  (+) Input mode
-  (+) Analog mode
-  (+) Output mode
-  (+) Alternate function mode
-  (+) External interrupt/event lines
-
-  [..]
-  During and just after reset, the alternate functions and external interrupt
-  lines are not active and the I/O ports are configured in input floating mode.
-
-  [..]
-  All GPIO pins have weak internal pull-up and pull-down resistors, which can be
-  activated or not.
-
-  [..]
-  In Output or Alternate mode, each IO can be configured on open-drain or push-pull
-  type and the IO speed can be selected depending on the VDD value.
-
-  [..]
-  All ports have external interrupt/event capability. To use external interrupt
-  lines, the port must be configured in input mode. All available GPIO pins are
-  connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
-
-  [..]
-  The external interrupt/event controller consists of up to 23 edge detectors
-  (16 lines are connected to GPIO) for generating event/interrupt requests (each
-  input line can be independently configured to select the type (interrupt or event)
-  and the corresponding trigger event (rising or falling or both). Each line can
-  also be masked independently.
-
-                     ##### How to use this driver #####
-  ==============================================================================
-  [..]
-    (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
-
-    (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
-        (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
-        (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
-             structure.
-        (++) In case of Output or alternate function mode selection: the speed is
-             configured through "Speed" member from GPIO_InitTypeDef structure.
-        (++) In alternate mode is selection, the alternate function connected to the IO
-             is configured through "Alternate" member from GPIO_InitTypeDef structure.
-        (++) Analog mode is required when a pin is to be used as ADC channel
-             or DAC output.
-        (++) In case of external interrupt/event selection the "Mode" member from
-             GPIO_InitTypeDef structure select the type (interrupt or event) and
-             the corresponding trigger event (rising or falling or both).
-
-    (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
-        mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
-        HAL_NVIC_EnableIRQ().
-
-    (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
-
-    (#) To set/reset the level of a pin configured in output mode use
-        HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
-
-    (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
-
-
-    (#) During and just after reset, the alternate functions are not
-        active and the GPIO pins are configured in input floating mode (except JTAG
-        pins).
-
-    (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
-        (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
-        priority over the GPIO function.
-
-    (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
-        general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
-        The HSE has priority over the GPIO function.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup GPIO GPIO
-  * @brief GPIO HAL module driver
-  * @{
-  */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup GPIO_Private_Constants GPIO Private Constants
-  * @{
-  */
-#define GPIO_MODE             ((uint32_t)0x00000003U)
-#define EXTI_MODE             ((uint32_t)0x10000000U)
-#define GPIO_MODE_IT          ((uint32_t)0x00010000U)
-#define GPIO_MODE_EVT         ((uint32_t)0x00020000U)
-#define RISING_EDGE           ((uint32_t)0x00100000U)
-#define FALLING_EDGE          ((uint32_t)0x00200000U)
-#define GPIO_OUTPUT_TYPE      ((uint32_t)0x00000010U)
-
-#define GPIO_NUMBER           ((uint32_t)16U)
-/**
-  * @}
-  */
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
-  * @{
-  */
-
-/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @brief    Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-  [..]
-    This section provides functions allowing to initialize and de-initialize the GPIOs
-    to be ready for use.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
-  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral.
-  * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
-  *         the configuration information for the specified GPIO peripheral.
-  * @retval None
-  */
-void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
-{
-  uint32_t position = 0x00;
-  uint32_t ioposition = 0x00;
-  uint32_t iocurrent = 0x00;
-  uint32_t temp = 0x00;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
-  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
-  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
-  assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
-
-  /* Configure the port pins */
-  for(position = 0; position < GPIO_NUMBER; position++)
-  {
-    /* Get the IO position */
-    ioposition = ((uint32_t)0x01) << position;
-    /* Get the current IO position */
-    iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
-
-    if(iocurrent == ioposition)
-    {
-      /*--------------------- GPIO Mode Configuration ------------------------*/
-      /* In case of Alternate function mode selection */
-      if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
-      {
-        /* Check the Alternate function parameter */
-        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
-
-        /* Configure Alternate function mapped with the current IO */
-        temp = GPIOx->AFR[position >> 3];
-        temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
-        temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
-        GPIOx->AFR[position >> 3] = temp;
-      }
-
-      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
-      temp = GPIOx->MODER;
-      temp &= ~(GPIO_MODER_MODER0 << (position * 2));
-      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
-      GPIOx->MODER = temp;
-
-      /* In case of Output or Alternate function mode selection */
-      if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
-         (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
-      {
-        /* Check the Speed parameter */
-        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
-        /* Configure the IO Speed */
-        temp = GPIOx->OSPEEDR;
-        temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
-        temp |= (GPIO_Init->Speed << (position * 2));
-        GPIOx->OSPEEDR = temp;
-
-        /* Configure the IO Output Type */
-        temp = GPIOx->OTYPER;
-        temp &= ~(GPIO_OTYPER_OT_0 << position) ;
-        temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
-        GPIOx->OTYPER = temp;
-      }
-
-      /* Activate the Pull-up or Pull down resistor for the current IO */
-      temp = GPIOx->PUPDR;
-      temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
-      temp |= ((GPIO_Init->Pull) << (position * 2));
-      GPIOx->PUPDR = temp;
-
-      /*--------------------- EXTI Mode Configuration ------------------------*/
-      /* Configure the External Interrupt or event for the current IO */
-      if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
-      {
-        /* Enable SYSCFG Clock */
-        __HAL_RCC_SYSCFG_CLK_ENABLE();
-
-        temp = SYSCFG->EXTICR[position >> 2];
-        temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
-        temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
-        SYSCFG->EXTICR[position >> 2] = temp;
-
-        /* Clear EXTI line configuration */
-        temp = EXTI->IMR;
-        temp &= ~((uint32_t)iocurrent);
-        if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
-        {
-          temp |= iocurrent;
-        }
-        EXTI->IMR = temp;
-
-        temp = EXTI->EMR;
-        temp &= ~((uint32_t)iocurrent);
-        if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
-        {
-          temp |= iocurrent;
-        }
-        EXTI->EMR = temp;
-
-        /* Clear Rising Falling edge configuration */
-        temp = EXTI->RTSR;
-        temp &= ~((uint32_t)iocurrent);
-        if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
-        {
-          temp |= iocurrent;
-        }
-        EXTI->RTSR = temp;
-
-        temp = EXTI->FTSR;
-        temp &= ~((uint32_t)iocurrent);
-        if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
-        {
-          temp |= iocurrent;
-        }
-        EXTI->FTSR = temp;
-      }
-    }
-  }
-}
-
-/**
-  * @brief  De-initializes the GPIOx peripheral registers to their default reset values.
-  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral.
-  * @param  GPIO_Pin: specifies the port bit to be written.
-  *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
-  * @retval None
-  */
-void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
-{
-  uint32_t position;
-  uint32_t ioposition = 0x00;
-  uint32_t iocurrent = 0x00;
-  uint32_t tmp = 0x00;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
-
-  /* Configure the port pins */
-  for(position = 0; position < GPIO_NUMBER; position++)
-  {
-    /* Get the IO position */
-    ioposition = ((uint32_t)0x01) << position;
-    /* Get the current IO position */
-    iocurrent = (GPIO_Pin) & ioposition;
-
-    if(iocurrent == ioposition)
-    {
-      /*------------------------- GPIO Mode Configuration --------------------*/
-      /* Configure IO Direction in Input Floating Mode */
-      GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2));
-
-      /* Configure the default Alternate Function in current IO */
-      GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
-
-      /* Configure the default value for IO Speed */
-      GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
-
-      /* Configure the default value IO Output Type */
-      GPIOx->OTYPER  &= ~(GPIO_OTYPER_OT_0 << position) ;
-
-      /* Deactivate the Pull-up and Pull-down resistor for the current IO */
-      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
-
-      /*------------------------- EXTI Mode Configuration --------------------*/
-      tmp = SYSCFG->EXTICR[position >> 2];
-      tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
-      if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))))
-      {
-        /* Configure the External Interrupt or event for the current IO */
-        tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
-        SYSCFG->EXTICR[position >> 2] &= ~tmp;
-
-        /* Clear EXTI line configuration */
-        EXTI->IMR &= ~((uint32_t)iocurrent);
-        EXTI->EMR &= ~((uint32_t)iocurrent);
-
-        /* Clear Rising Falling edge configuration */
-        EXTI->RTSR &= ~((uint32_t)iocurrent);
-        EXTI->FTSR &= ~((uint32_t)iocurrent);
-	  }
-    }
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
- *  @brief   GPIO Read and Write
- *
-@verbatim
- ===============================================================================
-                       ##### IO operation functions #####
- ===============================================================================
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Reads the specified input port pin.
-  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral.
-  * @param  GPIO_Pin: specifies the port bit to read.
-  *         This parameter can be GPIO_PIN_x where x can be (0..15).
-  * @retval The input port pin value.
-  */
-GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
-  GPIO_PinState bitstatus;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-
-  if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
-  {
-    bitstatus = GPIO_PIN_SET;
-  }
-  else
-  {
-    bitstatus = GPIO_PIN_RESET;
-  }
-  return bitstatus;
-}
-
-/**
-  * @brief  Sets or clears the selected data port bit.
-  *
-  * @note   This function uses GPIOx_BSRR register to allow atomic read/modify
-  *         accesses. In this way, there is no risk of an IRQ occurring between
-  *         the read and the modify access.
-  *
-  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral.
-  * @param  GPIO_Pin: specifies the port bit to be written.
-  *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
-  * @param  PinState: specifies the value to be written to the selected bit.
-  *          This parameter can be one of the GPIO_PinState enum values:
-  *            @arg GPIO_PIN_RESET: to clear the port pin
-  *            @arg GPIO_PIN_SET: to set the port pin
-  * @retval None
-  */
-void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
-{
-  /* Check the parameters */
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-  assert_param(IS_GPIO_PIN_ACTION(PinState));
-
-  if(PinState != GPIO_PIN_RESET)
-  {
-    GPIOx->BSRR = GPIO_Pin;
-  }
-  else
-  {
-    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
-  }
-}
-
-/**
-  * @brief  Toggles the specified GPIO pins.
-  * @param  GPIOx: Where x can be (A..I) to select the GPIO peripheral.
-  * @param  GPIO_Pin: Specifies the pins to be toggled.
-  * @retval None
-  */
-void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
-  /* Check the parameters */
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-
-  GPIOx->ODR ^= GPIO_Pin;
-}
-
-/**
-  * @brief  Locks GPIO Pins configuration registers.
-  * @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
-  *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
-  * @note   The configuration of the locked GPIO pins can no longer be modified
-  *         until the next reset.
-  * @param  GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F7 family
-  * @param  GPIO_Pin: specifies the port bit to be locked.
-  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
-  __IO uint32_t tmp = GPIO_LCKR_LCKK;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-
-  /* Apply lock key write sequence */
-  tmp |= GPIO_Pin;
-  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
-  GPIOx->LCKR = tmp;
-  /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
-  GPIOx->LCKR = GPIO_Pin;
-  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
-  GPIOx->LCKR = tmp;
-  /* Read LCKK bit*/
-  tmp = GPIOx->LCKR;
-
- if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
-  {
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  This function handles EXTI interrupt request.
-  * @param  GPIO_Pin: Specifies the pins connected EXTI line
-  * @retval None
-  */
-void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
-{
-  /* EXTI line interrupt detected */
-  if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
-  {
-    __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
-    HAL_GPIO_EXTI_Callback(GPIO_Pin);
-  }
-}
-
-/**
-  * @brief  EXTI line detection callbacks.
-  * @param  GPIO_Pin: Specifies the pins connected EXTI line
-  * @retval None
-  */
-__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(GPIO_Pin);
-
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_GPIO_EXTI_Callback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-#endif /* HAL_GPIO_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_i2c.c b/stmhal/hal/f7/src/stm32f7xx_hal_i2c.c
deleted file mode 100644
index 66a154edc3..0000000000
--- a/stmhal/hal/f7/src/stm32f7xx_hal_i2c.c
+++ /dev/null
@@ -1,4774 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_i2c.c
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   I2C HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Inter Integrated Circuit (I2C) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral State and Errors functions
-  *
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-    [..]
-    The I2C HAL driver can be used as follows:
-
-    (#) Declare a I2C_HandleTypeDef handle structure, for example:
-        I2C_HandleTypeDef  hi2c;
-
-    (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
-        (##) Enable the I2Cx interface clock
-        (##) I2C pins configuration
-            (+++) Enable the clock for the I2C GPIOs
-            (+++) Configure I2C pins as alternate function open-drain
-        (##) NVIC configuration if you need to use interrupt process
-            (+++) Configure the I2Cx interrupt priority
-            (+++) Enable the NVIC I2C IRQ Channel
-        (##) DMA Configuration if you need to use DMA process
-            (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
-            (+++) Enable the DMAx interface clock using
-            (+++) Configure the DMA handle parameters
-            (+++) Configure the DMA Tx or Rx stream
-            (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
-            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
-                  the DMA Tx or Rx stream
-
-    (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
-        Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
-
-    (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
-        (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
-
-    (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
-
-    (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
-
-    *** Polling mode IO operation ***
-    =================================
-    [..]
-      (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
-      (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
-      (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
-      (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
-
-    *** Polling mode IO MEM operation ***
-    =====================================
-    [..]
-      (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
-      (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
-
-
-    *** Interrupt mode IO operation ***
-    ===================================
-    [..]
-      (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
-      (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
-      (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
-      (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
-      (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
-      (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
-      (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
-      (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
-      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
-           add his own code by customization of function pointer HAL_I2C_ErrorCallback()
-      (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
-      (+) End of abort process, HAL_I2C_MasterRxCpltCallback() or HAL_I2C_MasterTxCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() or HAL_I2C_MasterTxCpltCallback()
-      (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
-           This action will inform Master to generate a Stop condition to discard the communication.
-
-
-    *** Interrupt mode IO sequential operation ***
-    ===================================
-    [..]
-      (@) These interfaces allow to manage a sequential transfer with a repeated start condition
-          when a direction change during transfer
-    [..]
-      (+) A specific option field manage the different steps of a sequential transfer
-      (+) Option field values are defined through I2C_XFEROPTIONS and are listed below:
-      (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
-      (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
-                            and data to transfer without a final stop condition
-	  (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
-                            and data to transfer without a final stop condition, an then permit a call the same master sequential interface
-                            several times (like HAL_I2C_Master_Sequential_Transmit_IT() then HAL_I2C_Master_Sequential_Transmit_IT())
-      (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
-                            and with new data to transfer if the direction change or manage only the new data to transfer
-                            if no direction change and without a final stop condition in both cases
-      (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
-                            and with new data to transfer if the direction change or manage only the new data to transfer
-                            if no direction change and with a final stop condition in both cases
-
-      (+) Differents sequential I2C interfaces are listed below:
-      (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT()
-      (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
-      (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT()
-      (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
-      (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
-      (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
-      (+++) mean HAL_I2C_MasterTxCpltCallback() in case of previous state was master transmit
-      (+++) mean HAL_I2c_MasterRxCpltCallback() in case of previous state was master receive
-      (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
-      (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
-           add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
-      (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
-      (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT()
-      (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
-      (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT()
-      (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
-      (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
-           add his own code by customization of function pointer HAL_I2C_ErrorCallback()
-      (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
-      (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
-      (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
-           This action will inform Master to generate a Stop condition to discard the communication.
-
-    *** Interrupt mode IO MEM operation ***
-    =======================================
-    [..]
-      (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
-          HAL_I2C_Mem_Write_IT()
-      (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
-      (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
-          HAL_I2C_Mem_Read_IT()
-      (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
-      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
-           add his own code by customization of function pointer HAL_I2C_ErrorCallback()
-
-    *** DMA mode IO operation ***
-    ==============================
-    [..]
-      (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
-          HAL_I2C_Master_Transmit_DMA()
-      (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
-      (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
-          HAL_I2C_Master_Receive_DMA()
-      (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
-      (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
-          HAL_I2C_Slave_Transmit_DMA()
-      (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
-      (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
-          HAL_I2C_Slave_Receive_DMA()
-      (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
-      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
-           add his own code by customization of function pointer HAL_I2C_ErrorCallback()
-      (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
-      (+) End of abort process, HAL_I2C_MasterRxCpltCallback() or HAL_I2C_MasterTxCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() or HAL_I2C_MasterTxCpltCallback()
-      (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
-           This action will inform Master to generate a Stop condition to discard the communication.
-
-    *** DMA mode IO MEM operation ***
-    =================================
-    [..]
-      (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
-          HAL_I2C_Mem_Write_DMA()
-      (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
-      (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
-          HAL_I2C_Mem_Read_DMA()
-      (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
-      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
-           add his own code by customization of function pointer HAL_I2C_ErrorCallback()
-
-
-     *** I2C HAL driver macros list ***
-     ==================================
-     [..]
-       Below the list of most used macros in I2C HAL driver.
-
-      (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
-      (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
-      (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
-      (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
-      (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
-      (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
-      (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
-
-     [..]
-       (@) You can refer to the I2C HAL driver header file for more useful macros
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup I2C I2C
-  * @brief I2C HAL module driver
-  * @{
-  */
-
-#ifdef HAL_I2C_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/** @defgroup I2C_Private_Define I2C Private Define
-  * @{
-  */
-#define TIMING_CLEAR_MASK   ((uint32_t)0xF0FFFFFFU)  /*!<  I2C TIMING clear register Mask */
-#define I2C_TIMEOUT_ADDR    ((uint32_t)10000U)       /*!< 10 s  */
-#define I2C_TIMEOUT_BUSY    ((uint32_t)25U)          /*!< 25 ms */
-#define I2C_TIMEOUT_DIR     ((uint32_t)25U)          /*!< 25 ms */
-#define I2C_TIMEOUT_RXNE    ((uint32_t)25U)          /*!< 25 ms */
-#define I2C_TIMEOUT_STOPF   ((uint32_t)25U)          /*!< 25 ms */
-#define I2C_TIMEOUT_TC      ((uint32_t)25U)          /*!< 25 ms */
-#define I2C_TIMEOUT_TCR     ((uint32_t)25U)          /*!< 25 ms */
-#define I2C_TIMEOUT_TXIS    ((uint32_t)25U)          /*!< 25 ms */
-#define I2C_TIMEOUT_FLAG    ((uint32_t)25U)          /*!< 25 ms */
-
-#define MAX_NBYTE_SIZE      255U
-#define SlaveAddr_SHIFT     7U
-#define SlaveAddr_MSK       0x06U
-
-/* Private define for @ref PreviousState usage */
-#define I2C_STATE_MSK             ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits            */
-#define I2C_STATE_NONE            ((uint32_t)(HAL_I2C_MODE_NONE))                                                        /*!< Default Value                                          */
-#define I2C_STATE_MASTER_BUSY_TX  ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))            /*!< Master Busy TX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_MASTER_BUSY_RX  ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))            /*!< Master Busy RX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_SLAVE_BUSY_TX   ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))             /*!< Slave Busy TX, combinaison of State LSB and Mode enum  */
-#define I2C_STATE_SLAVE_BUSY_RX   ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))             /*!< Slave Busy RX, combinaison of State LSB and Mode enum  */
-#define I2C_STATE_MEM_BUSY_TX     ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM))               /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_MEM_BUSY_RX     ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM))               /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
-
-/* Private define to centralize the enable/disable of Interrupts */
-#define I2C_XFER_TX_IT          ((uint32_t)0x00000001U)
-#define I2C_XFER_RX_IT          ((uint32_t)0x00000002U)
-#define I2C_XFER_LISTEN_IT      ((uint32_t)0x00000004U)
-
-#define I2C_XFER_ERROR_IT       ((uint32_t)0x00000011U)
-#define I2C_XFER_CPLT_IT        ((uint32_t)0x00000012U)
-#define I2C_XFER_RELOAD_IT      ((uint32_t)0x00000012U)
-
-/* Private define Sequential Transfer Options default/reset value */
-#define I2C_NO_OPTION_FRAME     ((uint32_t)0xFFFF0000U)
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) ((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX)   ? \
-                                            ((uint32_t)((__HANDLE__)->hdmatx->Instance->NDTR)) : \
-                                            ((uint32_t)((__HANDLE__)->hdmarx->Instance->NDTR)))
-
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
-/** @defgroup I2C_Private_Functions I2C Private Functions
-  * @{
-  */
-/* Private functions to handle DMA transfer */
-static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMAError(DMA_HandleTypeDef *hdma);
-static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
-
-/* Private functions to handle IT transfer */
-static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
-static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c);
-static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c);
-static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
-static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
-static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
-static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
-
-/* Private functions to handle IT transfer */
-static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
-
-/* Private functions for I2C transfer IRQ handler */
-static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
-static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
-static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
-static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
-
-/* Private functions to handle flags during polling transfer */
-static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
-
-/* Private functions to centralize the enable/disable of Interrupts */
-static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
-static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
-
-/* Private functions to flush TXDR register */
-static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
-
-/* Private functions to handle  start, restart or stop a transfer */
-static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c,  uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup I2C_Exported_Functions I2C Exported Functions
-  * @{
-  */
-
-/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @brief    Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This subsection provides a set of functions allowing to initialize and
-          deinitialize the I2Cx peripheral:
-
-      (+) User must Implement HAL_I2C_MspInit() function in which he configures
-          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
-
-      (+) Call the function HAL_I2C_Init() to configure the selected device with
-          the selected configuration:
-        (++) Clock Timing
-        (++) Own Address 1
-        (++) Addressing mode (Master, Slave)
-        (++) Dual Addressing mode
-        (++) Own Address 2
-        (++) Own Address 2 Mask
-        (++) General call mode
-        (++) Nostretch mode
-
-      (+) Call the function HAL_I2C_DeInit() to restore the default configuration
-          of the selected I2Cx peripheral.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the I2C according to the specified parameters
-  *         in the I2C_InitTypeDef and initialize the associated handle.
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
-{
-  /* Check the I2C handle allocation */
-  if(hi2c == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
-  assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
-  assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
-  assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
-  assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
-  assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
-  assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
-  assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
-
-  if(hi2c->State == HAL_I2C_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hi2c->Lock = HAL_UNLOCKED;
-
-    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
-    HAL_I2C_MspInit(hi2c);
-  }
-
-  hi2c->State = HAL_I2C_STATE_BUSY;
-
-  /* Disable the selected I2C peripheral */
-  __HAL_I2C_DISABLE(hi2c);
-
-  /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
-  /* Configure I2Cx: Frequency range */
-  hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
-
-  /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
-  /* Disable Own Address1 before set the Own Address1 configuration */
-  hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
-
-  /* Configure I2Cx: Own Address1 and ack own address1 mode */
-  if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
-  {
-    hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
-  }
-  else /* I2C_ADDRESSINGMODE_10BIT */
-  {
-    hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
-  }
-
-  /*---------------------------- I2Cx CR2 Configuration ----------------------*/
-  /* Configure I2Cx: Addressing Master mode */
-  if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
-  {
-    hi2c->Instance->CR2 = (I2C_CR2_ADD10);
-  }
-  /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
-  hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
-
-  /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
-  /* Disable Own Address2 before set the Own Address2 configuration */
-  hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
-
-  /* Configure I2Cx: Dual mode and Own Address2 */
-  hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));
-
-  /*---------------------------- I2Cx CR1 Configuration ----------------------*/
-  /* Configure I2Cx: Generalcall and NoStretch mode */
-  hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
-
-  /* Enable the selected I2C peripheral */
-  __HAL_I2C_ENABLE(hi2c);
-
-  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-  hi2c->State = HAL_I2C_STATE_READY;
-  hi2c->PreviousState = I2C_STATE_NONE;
-  hi2c->Mode = HAL_I2C_MODE_NONE;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitialize the I2C peripheral.
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
-{
-  /* Check the I2C handle allocation */
-  if(hi2c == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
-
-  hi2c->State = HAL_I2C_STATE_BUSY;
-
-  /* Disable the I2C Peripheral Clock */
-  __HAL_I2C_DISABLE(hi2c);
-
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
-  HAL_I2C_MspDeInit(hi2c);
-
-  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-  hi2c->State = HAL_I2C_STATE_RESET;
-  hi2c->PreviousState = I2C_STATE_NONE;
-  hi2c->Mode = HAL_I2C_MODE_NONE;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hi2c);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Initialize the I2C MSP.
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief DeInitialize the I2C MSP.
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
- *  @brief   Data transfers functions
- *
-@verbatim
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to manage the I2C data
-    transfers.
-
-    (#) There are two modes of transfer:
-       (++) Blocking mode : The communication is performed in the polling mode.
-            The status of all data processing is returned by the same function
-            after finishing transfer.
-       (++) No-Blocking mode : The communication is performed using Interrupts
-            or DMA. These functions return the status of the transfer startup.
-            The end of the data processing will be indicated through the
-            dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
-            using DMA mode.
-
-    (#) Blocking mode functions are :
-        (++) HAL_I2C_Master_Transmit()
-        (++) HAL_I2C_Master_Receive()
-        (++) HAL_I2C_Slave_Transmit()
-        (++) HAL_I2C_Slave_Receive()
-        (++) HAL_I2C_Mem_Write()
-        (++) HAL_I2C_Mem_Read()
-        (++) HAL_I2C_IsDeviceReady()
-
-    (#) No-Blocking mode functions with Interrupt are :
-        (++) HAL_I2C_Master_Transmit_IT()
-        (++) HAL_I2C_Master_Receive_IT()
-        (++) HAL_I2C_Slave_Transmit_IT()
-        (++) HAL_I2C_Slave_Receive_IT()
-        (++) HAL_I2C_Mem_Write_IT()
-        (++) HAL_I2C_Mem_Read_IT()
-
-    (#) No-Blocking mode functions with DMA are :
-        (++) HAL_I2C_Master_Transmit_DMA()
-        (++) HAL_I2C_Master_Receive_DMA()
-        (++) HAL_I2C_Slave_Transmit_DMA()
-        (++) HAL_I2C_Slave_Receive_DMA()
-        (++) HAL_I2C_Mem_Write_DMA()
-        (++) HAL_I2C_Mem_Read_DMA()
-
-    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
-        (++) HAL_I2C_MemTxCpltCallback()
-        (++) HAL_I2C_MemRxCpltCallback()
-        (++) HAL_I2C_MasterTxCpltCallback()
-        (++) HAL_I2C_MasterRxCpltCallback()
-        (++) HAL_I2C_SlaveTxCpltCallback()
-        (++) HAL_I2C_SlaveRxCpltCallback()
-        (++) HAL_I2C_ErrorCallback()
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Transmits in master mode an amount of data in blocking mode.
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @param  DevAddress: Target device address. The device 7 bits address value
-  *         in datasheet must be shift at right before call interface
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint32_t tickstart = 0;
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Init tickstart for timeout management*/
-    tickstart = HAL_GetTick();
-
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode      = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr  = pData;
-    hi2c->XferCount = Size;
-    hi2c->XferISR   = NULL;
-
-    /* Send Slave Address */
-    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
-    if(hi2c->XferCount > MAX_NBYTE_SIZE)
-    {
-      hi2c->XferSize = MAX_NBYTE_SIZE;
-      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
-    }
-    else
-    {
-      hi2c->XferSize = hi2c->XferCount;
-      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
-    }
-
-    while(hi2c->XferSize > 0)
-    {
-      /* Wait until TXIS flag is set */
-      if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-      {
-        if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-        {
-          return HAL_ERROR;
-        }
-        else
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-      /* Write data to TXDR */
-      hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
-      hi2c->XferCount--;
-      hi2c->XferSize--;
-
-      if((hi2c->XferSize == 0) && (hi2c->XferCount!=0))
-      {
-        /* Wait until TCR flag is set */
-        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-
-        if(hi2c->XferCount > MAX_NBYTE_SIZE)
-        {
-          hi2c->XferSize = MAX_NBYTE_SIZE;
-          I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
-        }
-        else
-        {
-          hi2c->XferSize = hi2c->XferCount;
-          I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
-        }
-      }
-    }
-
-    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
-    /* Wait until STOPF flag is set */
-    if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Clear STOP Flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-    /* Clear Configuration Register 2 */
-    I2C_RESET_CR2(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode  = HAL_I2C_MODE_NONE;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receives in master mode an amount of data in blocking mode.
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @param  DevAddress: Target device address. The device 7 bits address value
-  *         in datasheet must be shift at right before call interface
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint32_t tickstart = 0;
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Init tickstart for timeout management*/
-    tickstart = HAL_GetTick();
-
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode      = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr  = pData;
-    hi2c->XferCount = Size;
-    hi2c->XferISR   = NULL;
-
-    /* Send Slave Address */
-    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
-    if(hi2c->XferCount > MAX_NBYTE_SIZE)
-    {
-      hi2c->XferSize = MAX_NBYTE_SIZE;
-      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
-    }
-    else
-    {
-      hi2c->XferSize = hi2c->XferCount;
-      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
-    }
-
-    while(hi2c->XferSize > 0)
-    {
-      /* Wait until RXNE flag is set */
-      if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-      {
-        if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-        {
-          return HAL_ERROR;
-        }
-        else
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-
-      /* Read data from RXDR */
-      (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
-      hi2c->XferSize--;
-      hi2c->XferCount--;
-
-      if((hi2c->XferSize == 0) && (hi2c->XferCount != 0))
-      {
-        /* Wait until TCR flag is set */
-        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-
-        if(hi2c->XferCount > MAX_NBYTE_SIZE)
-        {
-          hi2c->XferSize = MAX_NBYTE_SIZE;
-          I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
-        }
-        else
-        {
-          hi2c->XferSize = hi2c->XferCount;
-          I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
-        }
-      }
-    }
-
-    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
-    /* Wait until STOPF flag is set */
-    if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Clear STOP Flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-    /* Clear Configuration Register 2 */
-    I2C_RESET_CR2(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode  = HAL_I2C_MODE_NONE;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Transmits in slave mode an amount of data in blocking mode.
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint32_t tickstart = 0;
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == NULL ) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Init tickstart for timeout management*/
-    tickstart = HAL_GetTick();
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr  = pData;
-    hi2c->XferCount = Size;
-    hi2c->XferISR   = NULL;
-
-    /* Enable Address Acknowledge */
-    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
-    /* Wait until ADDR flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
-    {
-      /* Disable Address Acknowledge */
-      hi2c->Instance->CR2 |= I2C_CR2_NACK;
-      return HAL_TIMEOUT;
-    }
-
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
-
-    /* If 10bit addressing mode is selected */
-    if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
-    {
-      /* Wait until ADDR flag is set */
-      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
-      {
-        /* Disable Address Acknowledge */
-        hi2c->Instance->CR2 |= I2C_CR2_NACK;
-        return HAL_TIMEOUT;
-      }
-
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
-    }
-
-    /* Wait until DIR flag is set Transmitter mode */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
-    {
-      /* Disable Address Acknowledge */
-      hi2c->Instance->CR2 |= I2C_CR2_NACK;
-      return HAL_TIMEOUT;
-    }
-
-    while(hi2c->XferCount > 0)
-    {
-      /* Wait until TXIS flag is set */
-      if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-      {
-        /* Disable Address Acknowledge */
-        hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
-        if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-        {
-          return HAL_ERROR;
-        }
-        else
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-
-      /* Write data to TXDR */
-      hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
-      hi2c->XferCount--;
-    }
-
-    /* Wait until STOP flag is set */
-    if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-    {
-      /* Disable Address Acknowledge */
-      hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        /* Normal use case for Transmitter mode */
-        /* A NACK is generated to confirm the end of transfer */
-        hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Clear STOP flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
-
-    /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
-    {
-      /* Disable Address Acknowledge */
-      hi2c->Instance->CR2 |= I2C_CR2_NACK;
-      return HAL_TIMEOUT;
-    }
-
-    /* Disable Address Acknowledge */
-    hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode  = HAL_I2C_MODE_NONE;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receive in slave mode an amount of data in blocking mode
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint32_t tickstart = 0;
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == NULL ) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-        /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Init tickstart for timeout management*/
-    tickstart = HAL_GetTick();
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr  = pData;
-    hi2c->XferCount = Size;
-    hi2c->XferISR   = NULL;
-
-    /* Enable Address Acknowledge */
-    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
-    /* Wait until ADDR flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
-    {
-      /* Disable Address Acknowledge */
-      hi2c->Instance->CR2 |= I2C_CR2_NACK;
-      return HAL_TIMEOUT;
-    }
-
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
-
-    /* Wait until DIR flag is reset Receiver mode */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
-    {
-      /* Disable Address Acknowledge */
-      hi2c->Instance->CR2 |= I2C_CR2_NACK;
-      return HAL_TIMEOUT;
-    }
-
-    while(hi2c->XferCount > 0)
-    {
-      /* Wait until RXNE flag is set */
-      if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-      {
-        /* Disable Address Acknowledge */
-        hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
-        /* Store Last receive data if any */
-        if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
-        {
-          /* Read data from RXDR */
-          (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
-          hi2c->XferCount--;
-        }
-
-        if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
-        {
-          return HAL_TIMEOUT;
-        }
-        else
-        {
-          return HAL_ERROR;
-        }
-      }
-
-      /* Read data from RXDR */
-      (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
-      hi2c->XferCount--;
-    }
-
-    /* Wait until STOP flag is set */
-    if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-    {
-      /* Disable Address Acknowledge */
-      hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Clear STOP flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
-
-    /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
-    {
-      /* Disable Address Acknowledge */
-      hi2c->Instance->CR2 |= I2C_CR2_NACK;
-      return HAL_TIMEOUT;
-    }
-
-    /* Disable Address Acknowledge */
-    hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode  = HAL_I2C_MODE_NONE;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Transmit in master mode an amount of data in non-blocking mode with Interrupt
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @param  DevAddress: Target device address. The device 7 bits address value
-  *         in datasheet must be shift at right before call interface
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
-{
-  uint32_t xfermode = 0;
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode        = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->XferISR     = I2C_Master_ISR_IT;
-
-    if(hi2c->XferCount > MAX_NBYTE_SIZE)
-    {
-      hi2c->XferSize = MAX_NBYTE_SIZE;
-      xfermode = I2C_RELOAD_MODE;
-    }
-    else
-    {
-      hi2c->XferSize = hi2c->XferCount;
-      xfermode = I2C_AUTOEND_MODE;
-    }
-
-    /* Send Slave Address */
-    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
-    I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-
-    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
-    /* possible to enable all of these */
-    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receive in master mode an amount of data in non-blocking mode with Interrupt
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @param  DevAddress: Target device address. The device 7 bits address value
-  *         in datasheet must be shift at right before call interface
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
-{
-  uint32_t xfermode = 0;
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode        = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->XferISR     = I2C_Master_ISR_IT;
-
-    if(hi2c->XferCount > MAX_NBYTE_SIZE)
-    {
-      hi2c->XferSize = MAX_NBYTE_SIZE;
-      xfermode = I2C_RELOAD_MODE;
-    }
-    else
-    {
-      hi2c->XferSize = hi2c->XferCount;
-      xfermode = I2C_AUTOEND_MODE;
-    }
-
-    /* Send Slave Address */
-    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
-    I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-
-    /* Enable ERR, TC, STOP, NACK, RXI interrupt */
-    /* possible to enable all of these */
-    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Transmit in slave mode an amount of data in non-blocking mode with Interrupt
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
-{
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-
-    /* Enable Address Acknowledge */
-    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->XferISR     = I2C_Slave_ISR_IT;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-
-    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
-    /* possible to enable all of these */
-    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receive in slave mode an amount of data in non-blocking mode with Interrupt
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
-{
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-
-    /* Enable Address Acknowledge */
-    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->XferISR     = I2C_Slave_ISR_IT;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-
-    /* Enable ERR, TC, STOP, NACK, RXI interrupt */
-    /* possible to enable all of these */
-    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Transmit in master mode an amount of data in non-blocking mode with DMA
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @param  DevAddress: Target device address. The device 7 bits address value
-  *         in datasheet must be shift at right before call interface
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
-{
-  uint32_t xfermode = 0;
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode        = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->XferISR     = I2C_Master_ISR_DMA;
-
-    if(hi2c->XferCount > MAX_NBYTE_SIZE)
-    {
-      hi2c->XferSize = MAX_NBYTE_SIZE;
-      xfermode = I2C_RELOAD_MODE;
-    }
-    else
-    {
-      hi2c->XferSize = hi2c->XferCount;
-      xfermode = I2C_AUTOEND_MODE;
-    }
-
-    /* Set the I2C DMA transfer complete callback */
-    hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
-
-    /* Set the DMA error callback */
-    hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
-
-    /* Set the unused DMA callbacks to NULL */
-    hi2c->hdmatx->XferHalfCpltCallback = NULL;
-    hi2c->hdmatx->XferAbortCallback = NULL;
-
-    /* Enable the DMA channel */
-    HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
-
-    /* Send Slave Address */
-    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
-    I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
-
-    /* Update XferCount value */
-    hi2c->XferCount -= hi2c->XferSize;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-    /* Enable ERR and NACK interrupts */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
-
-    /* Enable DMA Request */
-    hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receive in master mode an amount of data in non-blocking mode with DMA
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @param  DevAddress: Target device address. The device 7 bits address value
-  *         in datasheet must be shift at right before call interface
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
-{
-  uint32_t xfermode = 0;
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode        = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->XferISR     = I2C_Master_ISR_DMA;
-
-    if(hi2c->XferCount > MAX_NBYTE_SIZE)
-    {
-      hi2c->XferSize = MAX_NBYTE_SIZE;
-      xfermode = I2C_RELOAD_MODE;
-    }
-    else
-    {
-      hi2c->XferSize = hi2c->XferCount;
-      xfermode = I2C_AUTOEND_MODE;
-    }
-
-    if(hi2c->XferSize > 0)
-    {
-      /* Set the I2C DMA transfer complete callback */
-      hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
-
-      /* Set the DMA error callback */
-      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-
-      /* Set the unused DMA callbacks to NULL */
-      hi2c->hdmarx->XferHalfCpltCallback = NULL;
-      hi2c->hdmarx->XferAbortCallback = NULL;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
-
-      /* Send Slave Address */
-      /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
-      I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
-
-      /* Update XferCount value */
-      hi2c->XferCount -= hi2c->XferSize;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      /* Note : The I2C interrupts must be enabled after unlocking current process
-                to avoid the risk of I2C interrupt handle execution before current
-                process unlock */
-      /* Enable ERR and NACK interrupts */
-      I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
-
-      /* Enable DMA Request */
-      hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
-    }
-    else
-    {
-      hi2c->State = HAL_I2C_STATE_READY;
-      hi2c->Mode = HAL_I2C_MODE_NONE;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-    }
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Transmit in slave mode an amount of data in non-blocking mode with DMA
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
-{
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->XferISR     = I2C_Slave_ISR_DMA;
-
-    /* Set the I2C DMA transfer complete callback */
-    hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
-
-    /* Set the DMA error callback */
-    hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
-
-    /* Set the unused DMA callbacks to NULL */
-    hi2c->hdmatx->XferHalfCpltCallback = NULL;
-    hi2c->hdmatx->XferAbortCallback = NULL;
-
-    /* Enable the DMA channel */
-    HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
-
-    /* Enable Address Acknowledge */
-    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-    /* Enable ERR, STOP, NACK, ADDR interrupts */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
-
-    /* Enable DMA Request */
-    hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receive in slave mode an amount of data in non-blocking mode with DMA
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
-{
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->XferISR     = I2C_Slave_ISR_DMA;
-
-    /* Set the I2C DMA transfer complete callback */
-    hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
-
-    /* Set the DMA error callback */
-    hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-
-    /* Set the unused DMA callbacks to NULL */
-    hi2c->hdmarx->XferHalfCpltCallback = NULL;
-    hi2c->hdmarx->XferAbortCallback = NULL;
-
-    /* Enable the DMA channel */
-    HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
-
-    /* Enable Address Acknowledge */
-    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-    /* Enable ERR, STOP, NACK, ADDR interrupts */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
-
-    /* Enable DMA Request */
-    hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-/**
-  * @brief  Write an amount of data in blocking mode to a specific memory address
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @param  DevAddress: Target device address
-  * @param  MemAddress: Internal memory address
-  * @param  MemAddSize: Size of internal memory address
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint32_t tickstart = 0;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Init tickstart for timeout management*/
-    tickstart = HAL_GetTick();
-
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode      = HAL_I2C_MODE_MEM;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr  = pData;
-    hi2c->XferCount = Size;
-    hi2c->XferISR   = NULL;
-
-    /* Send Slave Address and Memory Address */
-    if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_ERROR;
-      }
-      else
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
-    if(hi2c->XferCount > MAX_NBYTE_SIZE)
-    {
-      hi2c->XferSize = MAX_NBYTE_SIZE;
-      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
-    }
-    else
-    {
-      hi2c->XferSize = hi2c->XferCount;
-      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
-    }
-
-    do
-    {
-      /* Wait until TXIS flag is set */
-      if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-      {
-        if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-        {
-          return HAL_ERROR;
-        }
-        else
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-
-      /* Write data to TXDR */
-      hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
-      hi2c->XferCount--;
-      hi2c->XferSize--;
-
-      if((hi2c->XferSize == 0) && (hi2c->XferCount!=0))
-      {
-        /* Wait until TCR flag is set */
-        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-
-        if(hi2c->XferCount > MAX_NBYTE_SIZE)
-        {
-          hi2c->XferSize = MAX_NBYTE_SIZE;
-          I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
-        }
-        else
-        {
-          hi2c->XferSize = hi2c->XferCount;
-          I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
-        }
-      }
-
-    }while(hi2c->XferCount > 0);
-
-    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
-    /* Wait until STOPF flag is reset */
-    if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Clear STOP Flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-    /* Clear Configuration Register 2 */
-    I2C_RESET_CR2(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode  = HAL_I2C_MODE_NONE;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Read an amount of data in blocking mode from a specific memory address
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @param  DevAddress: Target device address
-  * @param  MemAddress: Internal memory address
-  * @param  MemAddSize: Size of internal memory address
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint32_t tickstart = 0;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Init tickstart for timeout management*/
-    tickstart = HAL_GetTick();
-
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode      = HAL_I2C_MODE_MEM;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr  = pData;
-    hi2c->XferCount = Size;
-    hi2c->XferISR   = NULL;
-
-    /* Send Slave Address and Memory Address */
-    if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_ERROR;
-      }
-      else
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Send Slave Address */
-    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
-    if(hi2c->XferCount > MAX_NBYTE_SIZE)
-    {
-      hi2c->XferSize = MAX_NBYTE_SIZE;
-      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
-    }
-    else
-    {
-      hi2c->XferSize = hi2c->XferCount;
-      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
-    }
-
-    do
-    {
-      /* Wait until RXNE flag is set */
-      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
-
-      /* Read data from RXDR */
-      (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
-      hi2c->XferSize--;
-      hi2c->XferCount--;
-
-      if((hi2c->XferSize == 0) && (hi2c->XferCount != 0))
-      {
-        /* Wait until TCR flag is set */
-        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-
-        if(hi2c->XferCount > MAX_NBYTE_SIZE)
-        {
-          hi2c->XferSize = MAX_NBYTE_SIZE;
-          I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
-        }
-        else
-        {
-          hi2c->XferSize = hi2c->XferCount;
-          I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
-        }
-      }
-    }while(hi2c->XferCount > 0);
-
-    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
-    /* Wait until STOPF flag is reset */
-    if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Clear STOP Flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-    /* Clear Configuration Register 2 */
-    I2C_RESET_CR2(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode  = HAL_I2C_MODE_NONE;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-/**
-  * @brief  Write an amount of data in non-blocking mode with Interrupt to a specific memory address
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @param  DevAddress: Target device address
-  * @param  MemAddress: Internal memory address
-  * @param  MemAddSize: Size of internal memory address
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
-{
-  uint32_t tickstart = 0;
-  uint32_t xfermode = 0;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Init tickstart for timeout management*/
-    tickstart = HAL_GetTick();
-
-    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode        = HAL_I2C_MODE_MEM;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->XferISR     = I2C_Master_ISR_IT;
-
-    if(hi2c->XferCount > MAX_NBYTE_SIZE)
-    {
-      hi2c->XferSize = MAX_NBYTE_SIZE;
-      xfermode = I2C_RELOAD_MODE;
-    }
-    else
-    {
-      hi2c->XferSize = hi2c->XferCount;
-      xfermode = I2C_AUTOEND_MODE;
-    }
-
-    /* Send Slave Address and Memory Address */
-    if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_ERROR;
-      }
-      else
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
-    I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-
-    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
-    /* possible to enable all of these */
-    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Read an amount of data in non-blocking mode with Interrupt from a specific memory address
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @param  DevAddress: Target device address
-  * @param  MemAddress: Internal memory address
-  * @param  MemAddSize: Size of internal memory address
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
-{
-  uint32_t tickstart = 0;
-  uint32_t xfermode = 0;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Init tickstart for timeout management*/
-    tickstart = HAL_GetTick();
-
-    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode        = HAL_I2C_MODE_MEM;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->XferISR     = I2C_Master_ISR_IT;
-
-    if(hi2c->XferCount > MAX_NBYTE_SIZE)
-    {
-      hi2c->XferSize = MAX_NBYTE_SIZE;
-      xfermode = I2C_RELOAD_MODE;
-    }
-    else
-    {
-      hi2c->XferSize = hi2c->XferCount;
-      xfermode = I2C_AUTOEND_MODE;
-    }
-
-    /* Send Slave Address and Memory Address */
-    if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_ERROR;
-      }
-      else
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
-    I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-
-    /* Enable ERR, TC, STOP, NACK, RXI interrupt */
-    /* possible to enable all of these */
-    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-/**
-  * @brief  Write an amount of data in non-blocking mode with DMA to a specific memory address
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @param  DevAddress: Target device address
-  * @param  MemAddress: Internal memory address
-  * @param  MemAddSize: Size of internal memory address
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
-{
-  uint32_t tickstart = 0;
-  uint32_t xfermode = 0;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Init tickstart for timeout management*/
-    tickstart = HAL_GetTick();
-
-    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode        = HAL_I2C_MODE_MEM;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->XferISR     = I2C_Master_ISR_DMA;
-
-    if(hi2c->XferCount > MAX_NBYTE_SIZE)
-    {
-      hi2c->XferSize = MAX_NBYTE_SIZE;
-      xfermode = I2C_RELOAD_MODE;
-    }
-    else
-    {
-      hi2c->XferSize = hi2c->XferCount;
-      xfermode = I2C_AUTOEND_MODE;
-    }
-
-    /* Send Slave Address and Memory Address */
-    if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_ERROR;
-      }
-      else
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Set the I2C DMA transfer complete callback */
-    hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
-
-    /* Set the DMA error callback */
-    hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
-
-    /* Set the unused DMA callbacks to NULL */
-    hi2c->hdmatx->XferHalfCpltCallback = NULL;
-    hi2c->hdmatx->XferAbortCallback = NULL;
-
-    /* Enable the DMA channel */
-    HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
-
-    /* Send Slave Address */
-    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
-    I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
-
-    /* Update XferCount value */
-    hi2c->XferCount -= hi2c->XferSize;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-    /* Enable ERR and NACK interrupts */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
-
-    /* Enable DMA Request */
-    hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Reads an amount of data in non-blocking mode with DMA from a specific memory address.
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @param  DevAddress: Target device address
-  * @param  MemAddress: Internal memory address
-  * @param  MemAddSize: Size of internal memory address
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be read
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
-{
-  uint32_t tickstart = 0;
-  uint32_t xfermode = 0;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Init tickstart for timeout management*/
-    tickstart = HAL_GetTick();
-
-    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode        = HAL_I2C_MODE_MEM;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->XferISR     = I2C_Master_ISR_DMA;
-
-    if(hi2c->XferCount > MAX_NBYTE_SIZE)
-    {
-      hi2c->XferSize = MAX_NBYTE_SIZE;
-      xfermode = I2C_RELOAD_MODE;
-    }
-    else
-    {
-      hi2c->XferSize = hi2c->XferCount;
-      xfermode = I2C_AUTOEND_MODE;
-    }
-
-    /* Send Slave Address and Memory Address */
-    if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_ERROR;
-      }
-      else
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Set the I2C DMA transfer complete callback */
-    hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
-
-    /* Set the DMA error callback */
-    hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-
-    /* Set the unused DMA callbacks to NULL */
-    hi2c->hdmarx->XferHalfCpltCallback = NULL;
-    hi2c->hdmarx->XferAbortCallback = NULL;
-
-    /* Enable the DMA channel */
-    HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
-
-    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
-    I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
-
-    /* Update XferCount value */
-    hi2c->XferCount -= hi2c->XferSize;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Enable DMA Request */
-    hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-    /* Enable ERR and NACK interrupts */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Checks if target device is ready for communication.
-  * @note   This function is used with Memory devices
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @param  DevAddress: Target device address
-  * @param  Trials: Number of trials
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
-{
-  uint32_t tickstart = 0;
-
-  __IO uint32_t I2C_Trials = 0;
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_BUSY;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    do
-    {
-      /* Generate Start */
-      hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode,DevAddress);
-
-      /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
-      /* Wait until STOPF flag is set or a NACK flag is set*/
-      tickstart = HAL_GetTick();
-      while((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT))
-      {
-      	if(Timeout != HAL_MAX_DELAY)
-      	{
-          if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-          {
-            /* Device is ready */
-            hi2c->State = HAL_I2C_STATE_READY;
-            /* Process Unlocked */
-            __HAL_UNLOCK(hi2c);
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-
-      /* Check if the NACKF flag has not been set */
-      if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
-      {
-        /* Wait until STOPF flag is reset */
-        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-
-        /* Clear STOP Flag */
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-        /* Device is ready */
-        hi2c->State = HAL_I2C_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_OK;
-      }
-      else
-      {
-        /* Wait until STOPF flag is reset */
-        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-
-        /* Clear NACK Flag */
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-        /* Clear STOP Flag, auto generated with autoend*/
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-      }
-
-      /* Check if the maximum allowed number of trials has been reached */
-      if (I2C_Trials++ == Trials)
-      {
-        /* Generate Stop */
-        hi2c->Instance->CR2 |= I2C_CR2_STOP;
-
-        /* Wait until STOPF flag is reset */
-        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-
-        /* Clear STOP Flag */
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-      }
-    }while(I2C_Trials < Trials);
-
-    hi2c->State = HAL_I2C_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_TIMEOUT;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
-  * @note   This interface allow to manage repeated start condition when a direction change during transfer
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @param  DevAddress: Target device address. The device 7 bits address value
-  *         in datasheet must be shift at right before call interface
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @param  XferOptions: Options of Transfer, value of @ref I2C_XFEROPTIONS
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
-  uint32_t xfermode = 0;
-  uint32_t xferrequest = I2C_GENERATE_START_WRITE;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode      = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferOptions = XferOptions;
-    hi2c->XferISR     = I2C_Master_ISR_IT;
-
-    /* If size > MAX_NBYTE_SIZE, use reload mode */
-    if(hi2c->XferCount > MAX_NBYTE_SIZE)
-    {
-      hi2c->XferSize = MAX_NBYTE_SIZE;
-      xfermode = I2C_RELOAD_MODE;
-    }
-    else
-    {
-      hi2c->XferSize = hi2c->XferCount;
-      xfermode = hi2c->XferOptions;
-	}
-
-    /* If transfer direction not change, do not generate Restart Condition */
-    /* Mean Previous state is same as current state */
-    if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
-    {
-    xferrequest = I2C_NO_STARTSTOP;
-    }
-
-    /* Send Slave Address and set NBYTES to write */
-    I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
-  * @note   This interface allow to manage repeated start condition when a direction change during transfer
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @param  DevAddress: Target device address. The device 7 bits address value
-  *         in datasheet must be shift at right before call interface
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @param  XferOptions: Options of Transfer, value of @ref I2C_XFEROPTIONS
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
-  uint32_t xfermode = 0;
-  uint32_t xferrequest = I2C_GENERATE_START_READ;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode      = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferOptions = XferOptions;
-    hi2c->XferISR     = I2C_Master_ISR_IT;
-
-    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
-    if(hi2c->XferCount > MAX_NBYTE_SIZE)
-    {
-      hi2c->XferSize = MAX_NBYTE_SIZE;
-      xfermode = I2C_RELOAD_MODE;
-    }
-    else
-    {
-      hi2c->XferSize = hi2c->XferCount;
-      xfermode = hi2c->XferOptions;
-	}
-
-    /* If transfer direction not change, do not generate Restart Condition */
-    /* Mean Previous state is same as current state */
-    if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
-    {
-      xferrequest = I2C_NO_STARTSTOP;
-    }
-
-    /* Send Slave Address and set NBYTES to read */
-    I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, xferrequest);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
-  * @note   This interface allow to manage repeated start condition when a direction change during transfer
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @param  XferOptions: Options of Transfer, value of @ref I2C_XFEROPTIONS
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
-  if(hi2c->State == HAL_I2C_STATE_LISTEN)
-  {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
-    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
-    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Enable Address Acknowledge */
-    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->XferOptions = XferOptions;
-    hi2c->XferISR     = I2C_Slave_ISR_IT;
-
-    if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
-    {
-      /* Clear ADDR flag after prepare the transfer parameters */
-      /* This action will generate an acknowledge to the Master */
-      __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-    to avoid the risk of I2C interrupt handle execution before current
-    process unlock */
-    /* REnable ADDR interrupt */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
-  * @note   This interface allow to manage repeated start condition when a direction change during transfer
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @param  XferOptions: Options of Transfer, value of @ref I2C_XFEROPTIONS
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
-  if(hi2c->State == HAL_I2C_STATE_LISTEN)
-  {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
-    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
-    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Enable Address Acknowledge */
-    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->XferOptions = XferOptions;
-    hi2c->XferISR     = I2C_Slave_ISR_IT;
-
-    if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
-    {
-      /* Clear ADDR flag after prepare the transfer parameters */
-      /* This action will generate an acknowledge to the Master */
-      __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-    to avoid the risk of I2C interrupt handle execution before current
-    process unlock */
-    /* REnable ADDR interrupt */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Enable the Address listen mode with Interrupt.
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
-{
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    hi2c->State = HAL_I2C_STATE_LISTEN;
-    hi2c->XferISR = I2C_Slave_ISR_IT;
-
-    /* Enable the Address Match interrupt */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Disable the Address listen mode with Interrupt.
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
-{
-  /* Declaration of tmp to prevent undefined behavior of volatile usage */
-  uint32_t tmp;
-
-  /* Disable Address listen mode only if a transfer is not ongoing */
-  if(hi2c->State == HAL_I2C_STATE_LISTEN)
-  {
-    tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
-    hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode = HAL_I2C_MODE_NONE;
-    hi2c->XferISR = NULL;
-
-    /* Disable the Address Match interrupt */
-    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Abort a master I2C IT or DMA process communication with Interrupt.
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shift at right before call interface
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
-{
-  if(hi2c->Mode == HAL_I2C_MODE_MASTER)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Disable Interrupts */
-    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
-    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
-
-    /* Set State at HAL_I2C_STATE_ABORT */
-    hi2c->State = HAL_I2C_STATE_ABORT;
-
-    /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
-    /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
-    I2C_TransferConfig(hi2c, 0, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    /* Wrong usage of abort function */
-    /* This function should be used only in case of abort monitored by master device */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
- * @{
- */
-
-/**
-  * @brief  This function handles I2C event interrupt request.
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @retval None
-  */
-void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
-{
-  /* Get current IT Flags and IT sources value */
-  uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
-  uint32_t itsources = READ_REG(hi2c->Instance->CR1);
-
-  /* I2C events treatment -------------------------------------*/
-  if(hi2c->XferISR != NULL)
-  {
-    hi2c->XferISR(hi2c, itflags, itsources);
-  }
-}
-
-/**
-  * @brief  This function handles I2C error interrupt request.
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @retval None
-  */
-void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
-{
-  uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
-  uint32_t itsources = READ_REG(hi2c->Instance->CR1);
-
-  /* I2C Bus error interrupt occurred ------------------------------------*/
-  if(((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
-  {
-    hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
-
-    /* Clear BERR flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
-  }
-
-  /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
-  if(((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
-  {
-    hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
-
-    /* Clear OVR flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
-  }
-
-  /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
-  if(((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
-  {
-    hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
-
-    /* Clear ARLO flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
-  }
-
-  /* Call the Error Callback in case of Error detected */
-  if((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) !=  HAL_I2C_ERROR_NONE)
-  {
-    I2C_ITError(hi2c, hi2c->ErrorCode);
-  }
-}
-
-/**
-  * @brief  Master Tx Transfer completed callback.
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Master Rx Transfer completed callback.
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
-   */
-}
-
-/** @brief  Slave Tx Transfer completed callback.
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Slave Rx Transfer completed callback.
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Slave Address Match callback.
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @param  TransferDirection: Master request Transfer Direction (Write/Read), value of @ref I2C_XFEROPTIONS
-  * @param  AddrMatchCode: Address Match Code
-  * @retval None
-  */
-__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-  UNUSED(TransferDirection);
-  UNUSED(AddrMatchCode);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_AddrCallback() could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Listen Complete callback.
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_ListenCpltCallback() could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Memory Tx Transfer completed callback.
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_MemTxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Memory Rx Transfer completed callback.
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_MemRxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  I2C error callback.
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_ErrorCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  I2C abort callback.
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_AbortCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
- *  @brief   Peripheral State, Mode and Error functions
- *
-@verbatim
- ===============================================================================
-            ##### Peripheral State, Mode and Error functions #####
- ===============================================================================
-    [..]
-    This subsection permit to get in run-time the status of the peripheral
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the I2C handle state.
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @retval HAL state
-  */
-HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
-{
-  /* Return I2C handle state */
-  return hi2c->State;
-}
-
-/**
-  * @brief  Returns the I2C Master, Slave, Memory or no mode.
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL mode
-  */
-HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
-{
-  return hi2c->Mode;
-}
-
-/**
-* @brief  Return the I2C error code.
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *              the configuration information for the specified I2C.
-* @retval I2C Error Code
-*/
-uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
-{
-  return hi2c->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup I2C_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @param  ITFlags: Interrupt flags to handle.
-  * @param  ITSources: Interrupt sources enabled.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
-{
-  uint16_t devaddress = 0;
-
-  /* Process Locked */
-  __HAL_LOCK(hi2c);
-
-  if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
-  {
-    /* Clear NACK Flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-    /* Set corresponding Error Code */
-    /* No need to generate STOP, it is automatically done */
-    /* Error callback will be send during stop flag treatment */
-    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-
-    /* Flush TX register */
-    I2C_Flush_TXDR(hi2c);
-  }
-  else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
-  {
-    /* Read data from RXDR */
-    (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
-    hi2c->XferSize--;
-    hi2c->XferCount--;
-  }
-  else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
-  {
-    /* Write data to TXDR */
-    hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
-    hi2c->XferSize--;
-    hi2c->XferCount--;
-  }
-  else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
-  {
-    if((hi2c->XferSize == 0) && (hi2c->XferCount != 0))
-    {
-      devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
-
-      if(hi2c->XferCount > MAX_NBYTE_SIZE)
-      {
-        hi2c->XferSize = MAX_NBYTE_SIZE;
-        I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
-      }
-      else
-      {
-        hi2c->XferSize = hi2c->XferCount;
-        if(hi2c->XferOptions != I2C_NO_OPTION_FRAME)
-        {
-          I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP);
-        }
-        else
-        {
-          I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
-        }
-      }
-    }
-    else
-    {
-      /* Call TxCpltCallback() if no stop mode is set */
-      if((I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)&&(hi2c->Mode == HAL_I2C_MODE_MASTER))
-      {
-        /* Call I2C Master Sequential complete process */
-        I2C_ITMasterSequentialCplt(hi2c);
-      }
-      else
-      {
-        /* Wrong size Status regarding TCR flag event */
-        /* Call the corresponding callback to inform upper layer of End of Transfer */
-        I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
-      }
-    }
-  }
-  else if(((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
-  {
-    if(hi2c->XferCount == 0)
-    {
-      if((I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)&&(hi2c->Mode == HAL_I2C_MODE_MASTER))
-      {
-        /* Call I2C Master Sequential complete process */
-        I2C_ITMasterSequentialCplt(hi2c);
-      }
-    }
-    else
-    {
-      /* Wrong size Status regarding TC flag event */
-      /* Call the corresponding callback to inform upper layer of End of Transfer */
-      I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
-    }
-  }
-
-  if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
-  {
-    /* Call I2C Master complete process */
-    I2C_ITMasterCplt(hi2c, ITFlags);
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hi2c);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @param  ITFlags: Interrupt flags to handle.
-  * @param  ITSources: Interrupt sources enabled.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
-{
-  /* Process locked */
-  __HAL_LOCK(hi2c);
-
-  if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
-  {
-    /* Check that I2C transfer finished */
-    /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
-    /* Mean XferCount == 0*/
-    /* So clear Flag NACKF only */
-    if(hi2c->XferCount == 0)
-    {
-      if(((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \
-        (hi2c->State == HAL_I2C_STATE_LISTEN))
-      {
-        /* Call I2C Listen complete process */
-        I2C_ITListenCplt(hi2c, ITFlags);
-      }
-      else if((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN))
-      {
-        /* Clear NACK Flag */
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-        /* Flush TX register */
-        I2C_Flush_TXDR(hi2c);
-
-        /* Last Byte is Transmitted */
-        /* Call I2C Slave Sequential complete process */
-        I2C_ITSlaveSequentialCplt(hi2c);
-      }
-      else
-      {
-        /* Clear NACK Flag */
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-      }
-    }
-    else
-    {
-      /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
-      /* Clear NACK Flag */
-      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-      /* Set ErrorCode corresponding to a Non-Acknowledge */
-      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-    }
-  }
-  else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
-  {
-    if(hi2c->XferCount > 0)
-    {
-      /* Read data from RXDR */
-      (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
-      hi2c->XferSize--;
-      hi2c->XferCount--;
-    }
-
-    if((hi2c->XferCount == 0) && \
-       (hi2c->XferOptions != I2C_NO_OPTION_FRAME))
-    {
-      /* Call I2C Slave Sequential complete process */
-      I2C_ITSlaveSequentialCplt(hi2c);
-   }
-  }
-  else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
-  {
-    I2C_ITAddrCplt(hi2c, ITFlags);
-  }
-  else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
-  {
-    /* Write data to TXDR only if XferCount not reach "0" */
-    /* A TXIS flag can be set, during STOP treatment      */
-    /* Check if all Datas have already been sent */
-    /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
-    if(hi2c->XferCount > 0)
-    {
-      /* Write data to TXDR */
-      hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
-      hi2c->XferCount--;
-      hi2c->XferSize--;
-    }
-    else
-    {
-      if((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME))
-      {
-        /* Last Byte is Transmitted */
-        /* Call I2C Slave Sequential complete process */
-        I2C_ITSlaveSequentialCplt(hi2c);
-      }
-    }
-  }
-
-  /* Check if STOPF is set */
-  if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
-  {
-    /* Call I2C Slave complete process */
-    I2C_ITSlaveCplt(hi2c, ITFlags);
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hi2c);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @param  ITFlags: Interrupt flags to handle.
-  * @param  ITSources: Interrupt sources enabled.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
-{
-  uint16_t devaddress = 0;
-  uint32_t xfermode = 0;
-
-  /* Process Locked */
-  __HAL_LOCK(hi2c);
-
-  if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
-  {
-    /* Clear NACK Flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-    /* Set corresponding Error Code */
-    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-
-    /* No need to generate STOP, it is automatically done */
-    /* But enable STOP interrupt, to treat it */
-    /* Error callback will be send during stop flag treatment */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
-
-    /* Flush TX register */
-    I2C_Flush_TXDR(hi2c);
-  }
-  else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
-  {
-    /* Disable TC interrupt */
-    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
-
-    if(hi2c->XferCount != 0)
-    {
-      /* Recover Slave address */
-      devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
-
-      /* Prepare the new XferSize to transfer */
-      if(hi2c->XferCount > MAX_NBYTE_SIZE)
-      {
-        hi2c->XferSize = MAX_NBYTE_SIZE;
-        xfermode = I2C_RELOAD_MODE;
-      }
-      else
-      {
-        hi2c->XferSize = hi2c->XferCount;
-        xfermode = I2C_AUTOEND_MODE;
-      }
-
-      /* Set the new XferSize in Nbytes register */
-      I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
-
-      /* Update XferCount value */
-      hi2c->XferCount -= hi2c->XferSize;
-
-      /* Enable DMA Request */
-      if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
-      {
-        hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
-      }
-      else
-      {
-        hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
-      }
-    }
-    else
-    {
-      /* Wrong size Status regarding TCR flag event */
-      /* Call the corresponding callback to inform upper layer of End of Transfer */
-      I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
-    }
-  }
-  else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
-  {
-    /* Call I2C Master complete process */
-    I2C_ITMasterCplt(hi2c, ITFlags);
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hi2c);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @param  ITFlags: Interrupt flags to handle.
-  * @param  ITSources: Interrupt sources enabled.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
-{
-  /* Process locked */
-  __HAL_LOCK(hi2c);
-
-  if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
-  {
-    /* Check that I2C transfer finished */
-    /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
-    /* Mean XferCount == 0 */
-    /* So clear Flag NACKF only */
-    if(I2C_GET_DMA_REMAIN_DATA(hi2c) == 0)
-    {
-      /* Clear NACK Flag */
-      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-    }
-    else
-    {
-      /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
-      /* Clear NACK Flag */
-      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-      /* Set ErrorCode corresponding to a Non-Acknowledge */
-      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-    }
-  }
-  else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
-  {
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
-  }
-  else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
-  {
-    /* Call I2C Slave complete process */
-    I2C_ITSlaveCplt(hi2c, ITFlags);
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hi2c);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Master sends target device address followed by internal memory address for write request.
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @param  DevAddress: Target device address
-  * @param  MemAddress: Internal memory address
-  * @param  MemAddSize: Size of internal memory address
-  * @param  Timeout: Timeout duration
-  * @param  Tickstart Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
-{
-  I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
-
-  /* Wait until TXIS flag is set */
-  if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
-  {
-    if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* If Memory address size is 8Bit */
-  if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
-  {
-    /* Send Memory Address */
-    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
-  }
-  /* If Memory address size is 16Bit */
-  else
-  {
-    /* Send MSB of Memory Address */
-    hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
-
-    /* Wait until TXIS flag is set */
-    if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Send LSB of Memory Address */
-    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
-  }
-
-  /* Wait until TCR flag is set */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
-  {
-    return HAL_TIMEOUT;
-  }
-
-return HAL_OK;
-}
-
-/**
-  * @brief  Master sends target device address followed by internal memory address for read request.
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @param  DevAddress: Target device address
-  * @param  MemAddress: Internal memory address
-  * @param  MemAddSize: Size of internal memory address
-  * @param  Timeout: Timeout duration
-  * @param  Tickstart Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
-{
-  I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
-
-  /* Wait until TXIS flag is set */
-  if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
-  {
-    if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* If Memory address size is 8Bit */
-  if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
-  {
-    /* Send Memory Address */
-    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
-  }
-  /* If Memory address size is 16Bit */
-  else
-  {
-    /* Send MSB of Memory Address */
-    hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
-
-    /* Wait until TXIS flag is set */
-    if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Send LSB of Memory Address */
-    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
-  }
-
-  /* Wait until TC flag is set */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  I2C Address complete process callback.
-  * @param  hi2c: I2C handle.
-  * @param  ITFlags: Interrupt flags to handle.
-  * @retval None
-  */
-static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
-{
-  uint8_t transferdirection = 0;
-  uint16_t slaveaddrcode = 0;
-  uint16_t ownadd1code = 0;
-  uint16_t ownadd2code = 0;
-
-  /* In case of Listen state, need to inform upper layer of address match code event */
-  if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
-  {
-    transferdirection = I2C_GET_DIR(hi2c);
-    slaveaddrcode     = I2C_GET_ADDR_MATCH(hi2c);
-    ownadd1code       = I2C_GET_OWN_ADDRESS1(hi2c);
-    ownadd2code       = I2C_GET_OWN_ADDRESS2(hi2c);
-
-    /* If 10bits addressing mode is selected */
-    if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
-    {
-      if((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))
-      {
-        slaveaddrcode = ownadd1code;
-        hi2c->AddrEventCount++;
-        if(hi2c->AddrEventCount == 2)
-        {
-          /* Reset Address Event counter  */
-          hi2c->AddrEventCount = 0;
-
-          /* Clear ADDR flag */
-          __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2c);
-
-          /* Call Slave Addr callback */
-          HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
-        }
-      }
-      else
-      {
-        slaveaddrcode = ownadd2code;
-
-        /* Disable ADDR Interrupts */
-        I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        /* Call Slave Addr callback */
-        HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
-      }
-    }
-    /* else 7 bits addressing mode is selected */
-    else
-    {
-      /* Disable ADDR Interrupts */
-      I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      /* Call Slave Addr callback */
-      HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
-    }
-  }
-  /* Else clear address flag only */
-  else
-  {
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-  }
-}
-
-/**
-  * @brief  I2C Master sequential complete process.
-  * @param  hi2c: I2C handle.
-  * @retval None
-  */
-static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c)
-{
-  /* Reset I2C handle mode */
-  hi2c->Mode = HAL_I2C_MODE_NONE;
-
-  /* No Generate Stop, to permit restart mode */
-  /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
-  if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
-  {
-    hi2c->State         = HAL_I2C_STATE_READY;
-    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
-    hi2c->XferISR       = NULL;
-
-    /* Disable Interrupts */
-    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Call the corresponding callback to inform upper layer of End of Transfer */
-    HAL_I2C_MasterTxCpltCallback(hi2c);
-  }
-  /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
-  else
-  {
-    hi2c->State         = HAL_I2C_STATE_READY;
-    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
-    hi2c->XferISR       = NULL;
-
-    /* Disable Interrupts */
-    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Call the corresponding callback to inform upper layer of End of Transfer */
-    HAL_I2C_MasterRxCpltCallback(hi2c);
-  }
-}
-
-/**
-  * @brief  I2C Slave sequential complete process.
-  * @param  hi2c: I2C handle.
-  * @retval None
-  */
-static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c)
-{
-  /* Reset I2C handle mode */
-  hi2c->Mode = HAL_I2C_MODE_NONE;
-
-  if(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
-  {
-    /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
-    hi2c->State         = HAL_I2C_STATE_LISTEN;
-    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
-
-    /* Disable Interrupts */
-    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Call the Tx complete callback to inform upper layer of the end of transmit process */
-    HAL_I2C_SlaveTxCpltCallback(hi2c);
-  }
-
-  else if(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
-  {
-    /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
-    hi2c->State         = HAL_I2C_STATE_LISTEN;
-    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
-
-    /* Disable Interrupts */
-    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Call the Rx complete callback to inform upper layer of the end of receive process */
-    HAL_I2C_SlaveRxCpltCallback(hi2c);
-  }
-}
-
-/**
-  * @brief  I2C Master complete process.
-  * @param  hi2c: I2C handle.
-  * @param  ITFlags: Interrupt flags to handle.
-  * @retval None
-  */
-static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
-{
-  /* Clear STOP Flag */
-  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-  /* Clear Configuration Register 2 */
-  I2C_RESET_CR2(hi2c);
-
-  /* Reset handle parameters */
-  hi2c->PreviousState = I2C_STATE_NONE;
-  hi2c->XferISR       = NULL;
-  hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
-
-  if((ITFlags & I2C_FLAG_AF) != RESET)
-  {
-    /* Clear NACK Flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-    /* Set acknowledge error code */
-    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-  }
-
-  /* Flush TX register */
-  I2C_Flush_TXDR(hi2c);
-
-  /* Disable Interrupts */
-  I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT| I2C_XFER_RX_IT);
-
-  /* Call the corresponding callback to inform upper layer of End of Transfer */
-  if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
-  {
-    /* Call the corresponding callback to inform upper layer of End of Transfer */
-    I2C_ITError(hi2c, hi2c->ErrorCode);
-  }
-  /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
-  else if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
-  {
-    hi2c->State = HAL_I2C_STATE_READY;
-
-    if (hi2c->Mode == HAL_I2C_MODE_MEM)
-    {
-      hi2c->Mode = HAL_I2C_MODE_NONE;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      /* Call the corresponding callback to inform upper layer of End of Transfer */
-      HAL_I2C_MemTxCpltCallback(hi2c);
-    }
-    else
-    {
-      hi2c->Mode = HAL_I2C_MODE_NONE;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      /* Call the corresponding callback to inform upper layer of End of Transfer */
-      HAL_I2C_MasterTxCpltCallback(hi2c);
-    }
-  }
-  /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
-  else if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
-  {
-    hi2c->State = HAL_I2C_STATE_READY;
-
-    if (hi2c->Mode == HAL_I2C_MODE_MEM)
-    {
-      hi2c->Mode = HAL_I2C_MODE_NONE;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      HAL_I2C_MemRxCpltCallback(hi2c);
-    }
-    else
-    {
-      hi2c->Mode = HAL_I2C_MODE_NONE;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      HAL_I2C_MasterRxCpltCallback(hi2c);
-    }
-  }
-}
-
-/**
-  * @brief  I2C Slave complete process.
-  * @param  hi2c: I2C handle.
-  * @param  ITFlags: Interrupt flags to handle.
-  * @retval None
-  */
-static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
-{
-  /* Clear STOP Flag */
-  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-  /* Clear ADDR flag */
-  __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
-
-  /* Disable all interrupts */
-  I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
-
-  /* Disable Address Acknowledge */
-  hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
-  /* Clear Configuration Register 2 */
-  I2C_RESET_CR2(hi2c);
-
-  /* Flush TX register */
-  I2C_Flush_TXDR(hi2c);
-
-  /* If a DMA is ongoing, Update handle size context */
-  if(((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) ||
-     ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN))
-  {
-    if((hi2c->XferSize - I2C_GET_DMA_REMAIN_DATA(hi2c)) != hi2c->XferSize)
-    {
-      hi2c->XferSize = I2C_GET_DMA_REMAIN_DATA(hi2c);
-      hi2c->XferCount += hi2c->XferSize;
-
-      /* Set ErrorCode corresponding to a Non-Acknowledge */
-      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-    }
-  }
-
-  /* Store Last receive data if any */
-  if(((ITFlags & I2C_FLAG_RXNE) != RESET))
-  {
-    /* Read data from RXDR */
-    (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
-
-    if((hi2c->XferSize > 0))
-    {
-      hi2c->XferSize--;
-      hi2c->XferCount--;
-
-      /* Set ErrorCode corresponding to a Non-Acknowledge */
-      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-    }
-  }
-
-  hi2c->PreviousState = I2C_STATE_NONE;
-  hi2c->Mode = HAL_I2C_MODE_NONE;
-  hi2c->XferISR = NULL;
-
-  if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
-  {
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->State = HAL_I2C_STATE_READY;
-
-    /* Call the corresponding callback to inform upper layer of End of Transfer */
-    I2C_ITError(hi2c, hi2c->ErrorCode);
-  }
-  else if(hi2c->XferOptions != I2C_NO_OPTION_FRAME)
-  {
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->State = HAL_I2C_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
-    HAL_I2C_ListenCpltCallback(hi2c);
-  }
-  /* Call the corresponding callback to inform upper layer of End of Transfer */
-  else if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
-  {
-    hi2c->State = HAL_I2C_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Call the Slave Rx Complete callback */
-    HAL_I2C_SlaveRxCpltCallback(hi2c);
-  }
-  else
-  {
-    hi2c->State = HAL_I2C_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Call the Slave Tx Complete callback */
-    HAL_I2C_SlaveTxCpltCallback(hi2c);
-  }
-}
-
-/**
-  * @brief  I2C Listen complete process.
-  * @param  hi2c: I2C handle.
-  * @param  ITFlags: Interrupt flags to handle.
-  * @retval None
-  */
-static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
-{
-  /* Reset handle parameters */
-  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-  hi2c->PreviousState = I2C_STATE_NONE;
-  hi2c->State = HAL_I2C_STATE_READY;
-  hi2c->Mode = HAL_I2C_MODE_NONE;
-  hi2c->XferISR = NULL;
-
-  /* Store Last receive data if any */
-  if(((ITFlags & I2C_FLAG_RXNE) != RESET))
-  {
-    /* Read data from RXDR */
-    (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
-
-    if((hi2c->XferSize > 0))
-    {
-      hi2c->XferSize--;
-      hi2c->XferCount--;
-
-      /* Set ErrorCode corresponding to a Non-Acknowledge */
-      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-    }
-  }
-
-  /* Disable all Interrupts*/
-  I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
-
-  /* Clear NACK Flag */
-  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hi2c);
-
-  /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
-  HAL_I2C_ListenCpltCallback(hi2c);
-}
-
-/**
-  * @brief  I2C interrupts error process.
-  * @param  hi2c: I2C handle.
-  * @param  ErrorCode: Error code to handle.
-  * @retval None
-  */
-static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
-{
-  /* Reset handle parameters */
-  hi2c->Mode          = HAL_I2C_MODE_NONE;
-  hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
-  hi2c->XferCount     = 0;
-
-  /* Set new error code */
-  hi2c->ErrorCode |= ErrorCode;
-
-  /* Disable Interrupts */
-  if((hi2c->State == HAL_I2C_STATE_LISTEN)         ||
-     (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
-     (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))
-  {
-    /* Disable all interrupts, except interrupts related to LISTEN state */
-    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
-
-    /* keep HAL_I2C_STATE_LISTEN if set */
-    hi2c->State         = HAL_I2C_STATE_LISTEN;
-    hi2c->PreviousState = I2C_STATE_NONE;
-    hi2c->XferISR       = I2C_Slave_ISR_IT;
-  }
-  else
-  {
-    /* Disable all interrupts */
-    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
-
-    /* Set HAL_I2C_STATE_READY */
-    hi2c->State         = HAL_I2C_STATE_READY;
-    hi2c->PreviousState = I2C_STATE_NONE;
-    hi2c->XferISR       = NULL;
-  }
-
-  /* Abort DMA TX transfer if any */
-  if((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
-  {
-    hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
-
-    /* Set the I2C DMA Abort callback :
-       will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
-    hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Abort DMA TX */
-    if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
-    {
-      /* Call Directly XferAbortCallback function in case of error */
-      hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
-    }
-  }
-  /* Abort DMA RX transfer if any */
-  else if((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
-  {
-    hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
-
-    /* Set the I2C DMA Abort callback :
-       will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
-    hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Abort DMA RX */
-    if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
-    {
-      /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
-      hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
-    }
-  }
-  else if(hi2c->ErrorCode == HAL_I2C_ERROR_ABORT)
-  {
-    hi2c->ErrorCode &= ~HAL_I2C_ERROR_ABORT;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Call the corresponding callback to inform upper layer of End of Transfer */
-    HAL_I2C_AbortCpltCallback(hi2c);
-  }
-  else
-  {
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Call the corresponding callback to inform upper layer of End of Transfer */
-    HAL_I2C_ErrorCallback(hi2c);
-  }
-}
-
-/**
-  * @brief  I2C Tx data register flush process.
-  * @param  hi2c: I2C handle.
-  * @retval None
-  */
-static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
-{
-  /* If a pending TXIS flag is set */
-  /* Write a dummy data in TXDR to clear it */
-  if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
-  {
-     hi2c->Instance->TXDR = 0x00;
-  }
-
-  /* Flush TX register if not empty */
-  if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
-  {
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
-  }
-}
-
-/**
-  * @brief  DMA I2C master transmit process complete callback.
-  * @param  hdma: DMA handle
-  * @retval None
-  */
-static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
-{
-  I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  /* Disable DMA Request */
-  hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
-
-  /* If last transfer, enable STOP interrupt */
-  if(hi2c->XferCount == 0)
-  {
-    /* Enable STOP interrupt */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
-  }
-  /* else prepare a new DMA transfer and enable TCReload interrupt */
-  else
-  {
-    /* Update Buffer pointer */
-    hi2c->pBuffPtr += hi2c->XferSize;
-
-    /* Set the XferSize to transfer */
-    if(hi2c->XferCount > MAX_NBYTE_SIZE)
-    {
-      hi2c->XferSize = MAX_NBYTE_SIZE;
-    }
-    else
-    {
-      hi2c->XferSize = hi2c->XferCount;
-    }
-
-    /* Enable the DMA channel */
-    HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
-
-    /* Enable TC interrupts */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
-  }
-}
-
-/**
-  * @brief  DMA I2C slave transmit process complete callback.
-  * @param  hdma: DMA handle
-  * @retval None
-  */
-static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
-{
-  /* No specific action, Master fully manage the generation of STOP condition */
-  /* Mean that this generation can arrive at any time, at the end or during DMA process */
-  /* So STOP condition should be manage through Interrupt treatment */
-}
-
-/**
-  * @brief DMA I2C master receive process complete callback.
-  * @param  hdma: DMA handle
-  * @retval None
-  */
-static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  /* Disable DMA Request */
-  hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
-
-  /* If last transfer, enable STOP interrupt */
-  if(hi2c->XferCount == 0)
-  {
-    /* Enable STOP interrupt */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
-  }
-  /* else prepare a new DMA transfer and enable TCReload interrupt */
-  else
-  {
-    /* Update Buffer pointer */
-    hi2c->pBuffPtr += hi2c->XferSize;
-
-    /* Set the XferSize to transfer */
-    if(hi2c->XferCount > MAX_NBYTE_SIZE)
-    {
-      hi2c->XferSize = MAX_NBYTE_SIZE;
-    }
-    else
-    {
-      hi2c->XferSize = hi2c->XferCount;
-    }
-
-    /* Enable the DMA channel */
-    HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
-
-    /* Enable TC interrupts */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
-  }
-}
-
-/**
-  * @brief  DMA I2C slave receive process complete callback.
-  * @param hdma: DMA handle
-  * @retval None
-  */
-static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  /* No specific action, Master fully manage the generation of STOP condition */
-  /* Mean that this generation can arrive at any time, at the end or during DMA process */
-  /* So STOP condition should be manage through Interrupt treatment */
-}
-
-/**
-  * @brief  DMA I2C communication error callback.
-  * @param hdma: DMA handle
-  * @retval None
-  */
-static void I2C_DMAError(DMA_HandleTypeDef *hdma)
-{
-  I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  /* Disable Acknowledge */
-  hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
-  /* Call the corresponding callback to inform upper layer of End of Transfer */
-  I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
-}
-
-/**
-  * @brief DMA I2C communication abort callback
-  *        (To be called at end of DMA Abort procedure).
-  * @param hdma: DMA handle.
-  * @retval None
-  */
-static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
-{
-  I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  /* Disable Acknowledge */
-  hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
-  /* Reset AbortCpltCallback */
-  hi2c->hdmatx->XferAbortCallback = NULL;
-  hi2c->hdmarx->XferAbortCallback = NULL;
-
-  /* Check if come from abort from user */
-  if(hi2c->ErrorCode == HAL_I2C_ERROR_ABORT)
-  {
-    hi2c->ErrorCode &= ~HAL_I2C_ERROR_ABORT;
-
-    /* Call the corresponding callback to inform upper layer of End of Transfer */
-    HAL_I2C_AbortCpltCallback(hi2c);
-  }
-  else
-  {
-    /* Call the corresponding callback to inform upper layer of End of Transfer */
-    HAL_I2C_ErrorCallback(hi2c);
-  }
-}
-
-/**
-  * @brief  This function handles I2C Communication Timeout.
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @param  Flag: Specifies the I2C flag to check.
-  * @param  Status: The new Flag status (SET or RESET).
-  * @param  Timeout: Timeout duration
-  * @param  Tickstart: Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
-{
-  while((__HAL_I2C_GET_FLAG(hi2c, Flag) ? SET : RESET) == Status)
-  {
-    /* Check for the Timeout */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0)||((HAL_GetTick() - Tickstart ) > Timeout))
-      {
-        hi2c->State= HAL_I2C_STATE_READY;
-        hi2c->Mode = HAL_I2C_MODE_NONE;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles I2C Communication Timeout for specific usage of TXIS flag.
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @param  Timeout: Timeout duration
-  * @param  Tickstart: Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
-{
-  while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
-  {
-    /* Check if a NACK is detected */
-    if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
-    {
-      return HAL_ERROR;
-    }
-
-    /* Check for the Timeout */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout))
-      {
-        hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-        hi2c->State= HAL_I2C_STATE_READY;
-        hi2c->Mode = HAL_I2C_MODE_NONE;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles I2C Communication Timeout for specific usage of STOP flag.
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @param  Timeout: Timeout duration
-  * @param  Tickstart: Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
-{
-  while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
-  {
-    /* Check if a NACK is detected */
-    if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
-    {
-      return HAL_ERROR;
-    }
-
-    /* Check for the Timeout */
-    if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout))
-    {
-      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-      hi2c->State= HAL_I2C_STATE_READY;
-      hi2c->Mode = HAL_I2C_MODE_NONE;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      return HAL_TIMEOUT;
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles I2C Communication Timeout for specific usage of RXNE flag.
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @param  Timeout: Timeout duration
-  * @param  Tickstart: Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
-{
-  while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
-  {
-    /* Check if a NACK is detected */
-    if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
-    {
-      return HAL_ERROR;
-    }
-
-    /* Check if a STOPF is detected */
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
-    {
-      /* Clear STOP Flag */
-      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-      /* Clear Configuration Register 2 */
-      I2C_RESET_CR2(hi2c);
-
-      hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-      hi2c->State= HAL_I2C_STATE_READY;
-      hi2c->Mode = HAL_I2C_MODE_NONE;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      return HAL_ERROR;
-    }
-
-    /* Check for the Timeout */
-    if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout))
-    {
-      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-      hi2c->State= HAL_I2C_STATE_READY;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      return HAL_TIMEOUT;
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles Acknowledge failed detection during an I2C Communication.
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @param  Timeout: Timeout duration
-  * @param  Tickstart: Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
-{
-  if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
-  {
-    /* Wait until STOP Flag is reset */
-    /* AutoEnd should be initiate after AF */
-    while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
-    {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-      if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout))
-        {
-          hi2c->State= HAL_I2C_STATE_READY;
-          hi2c->Mode = HAL_I2C_MODE_NONE;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2c);
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-
-    /* Clear NACKF Flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-    /* Clear STOP Flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-    /* Flush TX register */
-    I2C_Flush_TXDR(hi2c);
-
-    /* Clear Configuration Register 2 */
-    I2C_RESET_CR2(hi2c);
-
-    hi2c->ErrorCode = HAL_I2C_ERROR_AF;
-    hi2c->State= HAL_I2C_STATE_READY;
-    hi2c->Mode = HAL_I2C_MODE_NONE;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_ERROR;
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
-  * @param  hi2c: I2C handle.
-  * @param  DevAddress: Specifies the slave address to be programmed.
-  * @param  Size: Specifies the number of bytes to be programmed.
-  *   This parameter must be a value between 0 and 255.
-  * @param  Mode: New state of the I2C START condition generation.
-  *   This parameter can be a value of @ref I2C_RELOAD_END_MODE.
-  * @param  Request: New state of the I2C START condition generation.
-  *   This parameter can be a value of I2C_START_STOP_MODE.
-  * @retval None
-  */
-static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c,  uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
-  assert_param(IS_TRANSFER_MODE(Mode));
-  assert_param(IS_TRANSFER_REQUEST(Request));
-
-  /* Get the CR2 register value */
-  tmpreg = hi2c->Instance->CR2;
-
-  /* clear tmpreg specific bits */
-  tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP));
-
-  /* update tmpreg */
-  tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \
-            (uint32_t)Mode | (uint32_t)Request);
-
-  /* update CR2 register */
-  hi2c->Instance->CR2 = tmpreg;
-}
-
-/**
-  * @brief  Manage the enabling of Interrupts.
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @param  InterruptRequest: Value of @ref I2C_Interrupt_configuration_definition.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
-{
-  uint32_t tmpisr = 0;
-
-  if((hi2c->XferISR == I2C_Master_ISR_DMA) || \
-     (hi2c->XferISR == I2C_Slave_ISR_DMA))
-  {
-    if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
-    {
-      /* Enable ERR, STOP, NACK and ADDR interrupts */
-      tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
-    }
-
-    if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
-    {
-      /* Enable ERR and NACK interrupts */
-      tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
-    }
-
-    if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
-    {
-      /* Enable STOP interrupts */
-      tmpisr |= I2C_IT_STOPI;
-    }
-
-    if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
-    {
-      /* Enable TC interrupts */
-      tmpisr |= I2C_IT_TCI;
-    }
-  }
-  else
-  {
-    if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
-    {
-      /* Enable ERR, STOP, NACK, and ADDR interrupts */
-      tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
-    }
-
-    if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
-    {
-      /* Enable ERR, TC, STOP, NACK and RXI interrupts */
-      tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
-    }
-
-    if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
-    {
-      /* Enable ERR, TC, STOP, NACK and TXI interrupts */
-      tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
-    }
-
-    if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
-    {
-      /* Enable STOP interrupts */
-      tmpisr |= I2C_IT_STOPI;
-    }
-  }
-
-  /* Enable interrupts only at the end */
-  /* to avoid the risk of I2C interrupt handle execution before */
-  /* all interrupts requested done */
-  __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Manage the disabling of Interrupts.
-  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains
-  *               the configuration information for the specified I2C.
-  * @param  InterruptRequest: Value of @ref I2C_Interrupt_configuration_definition.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
-{
-  uint32_t tmpisr = 0;
-
-  if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
-  {
-    /* Disable TC and TXI interrupts */
-    tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
-
-    if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
-    {
-      /* Disable NACK and STOP interrupts */
-      tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
-    }
-  }
-
-  if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
-  {
-    /* Disable TC and RXI interrupts */
-    tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
-
-    if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
-    {
-      /* Disable NACK and STOP interrupts */
-      tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
-    }
-  }
-
-  if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
-  {
-    /* Disable ADDR, NACK and STOP interrupts */
-    tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
-  }
-
-  if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
-  {
-    /* Enable ERR and NACK interrupts */
-    tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
-  }
-
-  if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
-  {
-    /* Enable STOP interrupts */
-    tmpisr |= I2C_IT_STOPI;
-  }
-
-  if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
-  {
-    /* Enable TC interrupts */
-    tmpisr |= I2C_IT_TCI;
-  }
-
-  /* Disable interrupts only at the end */
-  /* to avoid a breaking situation like at "t" time */
-  /* all disable interrupts request are not done */
-  __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_I2C_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_i2s.c b/stmhal/hal/f7/src/stm32f7xx_hal_i2s.c
deleted file mode 100644
index 9d56dbf77e..0000000000
--- a/stmhal/hal/f7/src/stm32f7xx_hal_i2s.c
+++ /dev/null
@@ -1,1556 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_i2s.c
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   I2S HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Integrated Interchip Sound (I2S) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral State and Errors functions
-  @verbatim
- ===============================================================================
-                  ##### How to use this driver #####
- ===============================================================================
- [..]
-    The I2S HAL driver can be used as follows:
-
-    (#) Declare a I2S_HandleTypeDef handle structure.
-    (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
-        (##) Enable the SPIx interface clock.
-        (##) I2S pins configuration:
-            (+++) Enable the clock for the I2S GPIOs.
-            (+++) Configure these I2S pins as alternate function pull-up.
-        (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
-             and HAL_I2S_Receive_IT() APIs).
-            (+++) Configure the I2Sx interrupt priority.
-            (+++) Enable the NVIC I2S IRQ handle.
-        (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
-             and HAL_I2S_Receive_DMA() APIs:
-            (+++) Declare a DMA handle structure for the Tx/Rx channel.
-            (+++) Enable the DMAx interface clock.
-            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
-            (+++) Configure the DMA Tx/Rx Channel.
-            (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
-            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
-                DMA Tx/Rx Channel.
-
-   (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
-       using HAL_I2S_Init() function.
-
-   -@- The specific I2S interrupts (Transmission complete interrupt,
-       RXNE interrupt and Error Interrupts) will be managed using the macros
-       __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
-   -@- Make sure that either:
-       (+@) I2S clock is configured based on SYSCLK or
-       (+@) External clock source is configured after setting correctly
-            the define constant EXTERNAL_CLOCK_VALUE in the stm32f3xx_hal_conf.h file.
-
-   (#) Three mode of operations are available within this driver :
-
-   *** Polling mode IO operation ***
-   =================================
-   [..]
-     (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
-     (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
-
-   *** Interrupt mode IO operation ***
-   ===================================
-   [..]
-     (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
-     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
-         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
-     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
-         add his own code by customization of function pointer HAL_I2S_TxCpltCallback
-     (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
-     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
-         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
-     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
-         add his own code by customization of function pointer HAL_I2S_RxCpltCallback
-     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
-         add his own code by customization of function pointer HAL_I2S_ErrorCallback
-
-   *** DMA mode IO operation ***
-   ==============================
-   [..]
-     (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
-     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
-         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
-     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
-         add his own code by customization of function pointer HAL_I2S_TxCpltCallback
-     (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
-     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
-         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
-     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
-         add his own code by customization of function pointer HAL_I2S_RxCpltCallback
-     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
-         add his own code by customization of function pointer HAL_I2S_ErrorCallback
-     (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
-     (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
-     (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
-
-   *** I2S HAL driver macros list ***
-   =============================================
-   [..]
-     Below the list of most used macros in I2S HAL driver.
-
-      (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
-      (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
-      (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
-      (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
-      (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
-
-    [..]
-      (@) You can refer to the I2S HAL driver header file for more useful macros
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup I2S I2S
-  * @brief I2S HAL module driver
-  * @{
-  */
-
-#ifdef HAL_I2S_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup I2S_Private_Functions I2S Private Functions
-  * @{
-  */
-static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
-static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
-static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
-static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
-static void I2S_DMAError(DMA_HandleTypeDef *hdma);
-static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
-static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
-static uint32_t I2S_GetClockFreq(I2S_HandleTypeDef *hi2s);
-static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout);
-/**
-  * @}
-  */
-
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup I2S_Exported_Functions I2S Exported Functions
-  * @{
-  */
-
-/** @defgroup  I2S_Exported_Functions_Group1 Initialization and de-initialization functions
-  *  @brief    Initialization and Configuration functions
-  *
-@verbatim
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This subsection provides a set of functions allowing to initialize and
-          de-initialize the I2Sx peripheral in simplex mode:
-
-      (+) User must Implement HAL_I2S_MspInit() function in which he configures
-          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
-
-      (+) Call the function HAL_I2S_Init() to configure the selected device with
-          the selected configuration:
-        (++) Mode
-        (++) Standard
-        (++) Data Format
-        (++) MCLK Output
-        (++) Audio frequency
-        (++) Polarity
-        (++) Full duplex mode
-
-      (+) Call the function HAL_I2S_DeInit() to restore the default configuration
-          of the selected I2Sx peripheral.
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Initializes the I2S according to the specified parameters
-  *         in the I2S_InitTypeDef and create the associated handle.
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
-{
-  uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
-  uint32_t tmp = 0, i2sclk = 0;
-
-  /* Check the I2S handle allocation */
-  if(hi2s == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
-  assert_param(IS_I2S_MODE(hi2s->Init.Mode));
-  assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
-  assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
-  assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
-  assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
-  assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
-  assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource));
-
-  if(hi2s->State == HAL_I2S_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hi2s->Lock = HAL_UNLOCKED;
-    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
-    HAL_I2S_MspInit(hi2s);
-  }
-
-  hi2s->State = HAL_I2S_STATE_BUSY;
-
-  /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
-  /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
-  hi2s->Instance->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
-                               SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
-                               SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD);
-  hi2s->Instance->I2SPR = 0x0002;
-
-  /* Get the I2SCFGR register value */
-  tmpreg = hi2s->Instance->I2SCFGR;
-
-  /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
-  if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT)
-  {
-    i2sodd = (uint16_t)0;
-    i2sdiv = (uint16_t)2;
-  }
-  /* If the requested audio frequency is not the default, compute the prescaler */
-  else
-  {
-    /* Check the frame length (For the Prescaler computing) *******************/
-    if(hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
-    {
-      /* Packet length is 16 bits */
-      packetlength = 1;
-    }
-    else
-    {
-      /* Packet length is 32 bits */
-      packetlength = 2;
-    }
-
-    /* Get I2S source Clock frequency  ****************************************/
-
-    /* If an external I2S clock has to be used, the specific define should be set
-    in the project configuration or in the stm32f3xx_conf.h file */
-    if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL)
-    {
-      /* Set the I2S clock to the external clock  value */
-      i2sclk = EXTERNAL_CLOCK_VALUE;
-    }
-    else
-    {
-      /* Get the I2S source clock value */
-			i2sclk = I2S_GetClockFreq(hi2s);
-    }
-
-    /* Compute the Real divider depending on the MCLK output state, with a floating point */
-    if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
-    {
-      /* MCLK output is enabled */
-      tmp = (uint16_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5);
-    }
-    else
-    {
-      /* MCLK output is disabled */
-      tmp = (uint16_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5);
-    }
-
-    /* Remove the flatting point */
-    tmp = tmp / 10;
-
-    /* Check the parity of the divider */
-    i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
-
-    /* Compute the i2sdiv prescaler */
-    i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
-
-    /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
-    i2sodd = (uint16_t) (i2sodd << 8);
-  }
-
-  /* Test if the divider is 1 or 0 or greater than 0xFF */
-  if((i2sdiv < 2) || (i2sdiv > 0xFF))
-  {
-    /* Set the default values */
-    i2sdiv = 2;
-    i2sodd = 0;
-  }
-
-  /* Write to SPIx I2SPR register the computed value */
-  hi2s->Instance->I2SPR = (uint16_t)((uint16_t)i2sdiv | (uint16_t)(i2sodd | (uint16_t)hi2s->Init.MCLKOutput));
-
-  /* Configure the I2S with the I2S_InitStruct values */
-  tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(hi2s->Init.Mode | \
-                       (uint16_t)(hi2s->Init.Standard | (uint16_t)(hi2s->Init.DataFormat | \
-                       (uint16_t)hi2s->Init.CPOL))));
-
-  /* Write to SPIx I2SCFGR */
-  hi2s->Instance->I2SCFGR = tmpreg;
-
-  hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-  hi2s->State= HAL_I2S_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief DeInitializes the I2S peripheral
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
-{
-  /* Check the I2S handle allocation */
-  if(hi2s == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
-
-  hi2s->State = HAL_I2S_STATE_BUSY;
-
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
-  HAL_I2S_MspDeInit(hi2s);
-
-  hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-  hi2s->State = HAL_I2S_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hi2s);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief I2S MSP Init
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
- __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2s);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2S_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief I2S MSP DeInit
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
- __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2s);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2S_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Exported_Functions_Group2 Input and Output operation functions
-  *  @brief Data transfers functions
-  *
-@verbatim
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to manage the I2S data
-    transfers.
-
-    (#) There are two modes of transfer:
-       (++) Blocking mode : The communication is performed in the polling mode.
-            The status of all data processing is returned by the same function
-            after finishing transfer.
-       (++) No-Blocking mode : The communication is performed using Interrupts
-            or DMA. These functions return the status of the transfer startup.
-            The end of the data processing will be indicated through the
-            dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
-            using DMA mode.
-
-    (#) Blocking mode functions are :
-        (++) HAL_I2S_Transmit()
-        (++) HAL_I2S_Receive()
-
-    (#) No-Blocking mode functions with Interrupt are :
-        (++) HAL_I2S_Transmit_IT()
-        (++) HAL_I2S_Receive_IT()
-
-    (#) No-Blocking mode functions with DMA are :
-        (++) HAL_I2S_Transmit_DMA()
-        (++) HAL_I2S_Receive_DMA()
-
-    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
-        (++) HAL_I2S_TxCpltCallback()
-        (++) HAL_I2S_RxCpltCallback()
-        (++) HAL_I2S_ErrorCallback()
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Transmit an amount of data in blocking mode
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @param pData: a 16-bit pointer to data buffer.
-  * @param Size: number of data sample to be sent:
-  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
-  *       configuration phase, the Size parameter means the number of 16-bit data length
-  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
-  *       the Size parameter means the number of 16-bit data length.
-  * @param  Timeout: Timeout duration
-  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
-  *       between Master and Slave(example: audio streaming).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  if((pData == NULL ) || (Size == 0))
-  {
-    return  HAL_ERROR;
-  }
-
-  if(hi2s->State == HAL_I2S_STATE_READY)
-  {
-    if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
-       ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
-    {
-      hi2s->TxXferSize = (Size << 1);
-      hi2s->TxXferCount = (Size << 1);
-    }
-    else
-    {
-      hi2s->TxXferSize = Size;
-      hi2s->TxXferCount = Size;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2s);
-
-    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-    hi2s->State = HAL_I2S_STATE_BUSY_TX;
-
-    /* Check if the I2S is already enabled */
-    if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
-    {
-      /* Enable I2S peripheral */
-      __HAL_I2S_ENABLE(hi2s);
-    }
-
-    while(hi2s->TxXferCount > 0)
-    {
-      hi2s->Instance->DR = (*pData++);
-      hi2s->TxXferCount--;
-      /* Wait until TXE flag is set */
-      if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
-      {
-        /* Set the error code and execute error callback*/
-        hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
-        HAL_I2S_ErrorCallback(hi2s);
-        return HAL_TIMEOUT;
-      }
-
-      /* Check if an underrun occurs */
-      if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
-      {
-        /* Set the I2S State ready */
-        hi2s->State = HAL_I2S_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2s);
-
-        /* Set the error code and execute error callback*/
-        hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
-        HAL_I2S_ErrorCallback(hi2s);
-
-        return HAL_ERROR;
-      }
-    }
-
-    /* Check if Slave mode is selected */
-    if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
-    {
-      /* Wait until Busy flag is reset */
-      if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK)
-      {
-        /* Set the error code and execute error callback*/
-        hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
-        HAL_I2S_ErrorCallback(hi2s);
-        return HAL_TIMEOUT;
-      }
-    }
-
-    hi2s->State = HAL_I2S_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2s);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Receive an amount of data in blocking mode
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @param pData: a 16-bit pointer to data buffer.
-  * @param Size: number of data sample to be sent:
-  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
-  *       configuration phase, the Size parameter means the number of 16-bit data length
-  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
-  *       the Size parameter means the number of 16-bit data length.
-  * @param Timeout: Timeout duration
-  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
-  *       between Master and Slave(example: audio streaming).
-  * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
-  *       in continuous way and as the I2S is not disabled at the end of the I2S transaction.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  if((pData == NULL ) || (Size == 0))
-  {
-    return  HAL_ERROR;
-  }
-
-  if(hi2s->State == HAL_I2S_STATE_READY)
-  {
-    if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
-       ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
-    {
-      hi2s->RxXferSize = (Size << 1);
-      hi2s->RxXferCount = (Size << 1);
-    }
-    else
-    {
-      hi2s->RxXferSize = Size;
-      hi2s->RxXferCount = Size;
-    }
-    /* Process Locked */
-    __HAL_LOCK(hi2s);
-
-    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-    hi2s->State = HAL_I2S_STATE_BUSY_RX;
-
-    /* Check if the I2S is already enabled */
-    if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
-    {
-      /* Enable I2S peripheral */
-      __HAL_I2S_ENABLE(hi2s);
-    }
-
-    /* Check if Master Receiver mode is selected */
-    if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
-    {
-      /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
-      access to the SPI_SR register. */
-      __HAL_I2S_CLEAR_OVRFLAG(hi2s);
-    }
-
-    /* Receive data */
-    while(hi2s->RxXferCount > 0)
-    {
-      /* Wait until RXNE flag is set */
-      if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout) != HAL_OK)
-      {
-        /* Set the error code and execute error callback*/
-        hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
-        HAL_I2S_ErrorCallback(hi2s);
-        return HAL_TIMEOUT;
-      }
-
-      /* Check if an overrun occurs */
-      if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
-      {
-        /* Set the I2S State ready */
-        hi2s->State = HAL_I2S_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2s);
-
-        /* Set the error code and execute error callback*/
-        hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
-        HAL_I2S_ErrorCallback(hi2s);
-
-        return HAL_ERROR;
-      }
-
-      (*pData++) = hi2s->Instance->DR;
-      hi2s->RxXferCount--;
-    }
-
-    hi2s->State = HAL_I2S_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2s);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Transmit an amount of data in non-blocking mode with Interrupt
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @param pData: a 16-bit pointer to data buffer.
-  * @param Size: number of data sample to be sent:
-  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
-  *       configuration phase, the Size parameter means the number of 16-bit data length
-  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
-  *       the Size parameter means the number of 16-bit data length.
-  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
-  *       between Master and Slave(example: audio streaming).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
-{
-  if(hi2s->State == HAL_I2S_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    hi2s->pTxBuffPtr = pData;
-    if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
-      ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
-    {
-      hi2s->TxXferSize = (Size << 1);
-      hi2s->TxXferCount = (Size << 1);
-    }
-    else
-    {
-      hi2s->TxXferSize = Size;
-      hi2s->TxXferCount = Size;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2s);
-
-    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-    hi2s->State = HAL_I2S_STATE_BUSY_TX;
-
-    /* Enable TXE and ERR interrupt */
-    __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
-    /* Check if the I2S is already enabled */
-    if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
-    {
-      /* Enable I2S peripheral */
-      __HAL_I2S_ENABLE(hi2s);
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2s);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Receive an amount of data in non-blocking mode with Interrupt
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @param pData: a 16-bit pointer to the Receive data buffer.
-  * @param Size: number of data sample to be sent:
-  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
-  *       configuration phase, the Size parameter means the number of 16-bit data length
-  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
-  *       the Size parameter means the number of 16-bit data length.
-  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
-  *       between Master and Slave(example: audio streaming).
-  * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation
-  * between Master and Slave otherwise the I2S interrupt should be optimized.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
-{
-  if(hi2s->State == HAL_I2S_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    hi2s->pRxBuffPtr = pData;
-    if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
-      ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
-    {
-      hi2s->RxXferSize = (Size << 1);
-      hi2s->RxXferCount = (Size << 1);
-    }
-    else
-    {
-      hi2s->RxXferSize = Size;
-      hi2s->RxXferCount = Size;
-    }
-    /* Process Locked */
-    __HAL_LOCK(hi2s);
-
-    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-    hi2s->State = HAL_I2S_STATE_BUSY_RX;
-
-    /* Enable TXE and ERR interrupt */
-    __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
-    /* Check if the I2S is already enabled */
-    if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
-    {
-      /* Enable I2S peripheral */
-      __HAL_I2S_ENABLE(hi2s);
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2s);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Transmit an amount of data in non-blocking mode with DMA
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @param pData: a 16-bit pointer to the Transmit data buffer.
-  * @param Size: number of data sample to be sent:
-  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
-  *       configuration phase, the Size parameter means the number of 16-bit data length
-  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
-  *       the Size parameter means the number of 16-bit data length.
-  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
-  *       between Master and Slave(example: audio streaming).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
-{
-  uint32_t *tmp;
-
-  if((pData == NULL) || (Size == 0))
-  {
-    return  HAL_ERROR;
-  }
-
-  if(hi2s->State == HAL_I2S_STATE_READY)
-  {
-    hi2s->pTxBuffPtr = pData;
-    if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
-      ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
-    {
-      hi2s->TxXferSize = (Size << 1);
-      hi2s->TxXferCount = (Size << 1);
-    }
-    else
-    {
-      hi2s->TxXferSize = Size;
-      hi2s->TxXferCount = Size;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2s);
-
-    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-    hi2s->State = HAL_I2S_STATE_BUSY_TX;
-
-    /* Set the I2S Tx DMA Half transfer complete callback */
-    hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
-
-    /* Set the I2S TxDMA transfer complete callback */
-    hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
-
-    /* Set the DMA error callback */
-    hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
-
-    /* Enable the Tx DMA Channel */
-    tmp = (uint32_t*)&pData;
-    HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
-
-    /* Check if the I2S is already enabled */
-    if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
-    {
-      /* Enable I2S peripheral */
-      __HAL_I2S_ENABLE(hi2s);
-    }
-
-    /* Enable Tx DMA Request */
-    hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2s);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Receive an amount of data in non-blocking mode with DMA
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @param pData: a 16-bit pointer to the Receive data buffer.
-  * @param Size: number of data sample to be sent:
-  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
-  *       configuration phase, the Size parameter means the number of 16-bit data length
-  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
-  *       the Size parameter means the number of 16-bit data length.
-  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
-  *       between Master and Slave(example: audio streaming).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
-{
-  uint32_t *tmp;
-
-  if((pData == NULL) || (Size == 0))
-  {
-    return  HAL_ERROR;
-  }
-
-  if(hi2s->State == HAL_I2S_STATE_READY)
-  {
-    hi2s->pRxBuffPtr = pData;
-    if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
-      ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
-    {
-      hi2s->RxXferSize = (Size << 1);
-      hi2s->RxXferCount = (Size << 1);
-    }
-    else
-    {
-      hi2s->RxXferSize = Size;
-      hi2s->RxXferCount = Size;
-    }
-    /* Process Locked */
-    __HAL_LOCK(hi2s);
-
-    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-    hi2s->State = HAL_I2S_STATE_BUSY_RX;
-
-    /* Set the I2S Rx DMA Half transfer complete callback */
-    hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
-
-    /* Set the I2S Rx DMA transfer complete callback */
-    hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
-
-    /* Set the DMA error callback */
-    hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
-
-    /* Check if Master Receiver mode is selected */
-    if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
-    {
-      /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
-      access to the SPI_SR register. */
-      __HAL_I2S_CLEAR_OVRFLAG(hi2s);
-    }
-
-    /* Enable the Rx DMA Channel */
-    tmp = (uint32_t*)&pData;
-    HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
-
-    /* Check if the I2S is already enabled */
-    if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
-    {
-      /* Enable I2S peripheral */
-      __HAL_I2S_ENABLE(hi2s);
-    }
-
-    /* Enable Rx DMA Request */
-    hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2s);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Pauses the audio stream playing from the Media.
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
-{
-  /* Process Locked */
-  __HAL_LOCK(hi2s);
-
-  if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
-  {
-    /* Disable the I2S DMA Tx request */
-    hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
-  }
-  else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
-  {
-    /* Disable the I2S DMA Rx request */
-    hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
-  }
-  else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
-  {
-    if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
-    {
-      /* Disable the I2S DMA Tx request */
-      hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
-    }
-    else
-    {
-      /* Disable the I2S DMA Rx request */
-      hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
-    }
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hi2s);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Resumes the audio stream playing from the Media.
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
-{
-  /* Process Locked */
-  __HAL_LOCK(hi2s);
-
-  if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
-  {
-    /* Enable the I2S DMA Tx request */
-    SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
-  }
-  else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
-  {
-    /* Enable the I2S DMA Rx request */
-    SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
-  }
-
-  /* If the I2S peripheral is still not enabled, enable it */
-  if(HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
-  {
-    /* Enable I2S peripheral */
-    __HAL_I2S_ENABLE(hi2s);
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hi2s);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Stops the audio stream playing from the Media.
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
-{
-  /* Process Locked */
-  __HAL_LOCK(hi2s);
-
-  /* Disable the I2S Tx/Rx DMA requests */
-  CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
-  CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
-
-  /* Abort the I2S DMA Channel tx */
-  if(hi2s->hdmatx != NULL)
-  {
-    /* Disable the I2S DMA channel */
-    __HAL_DMA_DISABLE(hi2s->hdmatx);
-    HAL_DMA_Abort(hi2s->hdmatx);
-  }
-  /* Abort the I2S DMA Channel rx */
-  if(hi2s->hdmarx != NULL)
-  {
-    /* Disable the I2S DMA channel */
-    __HAL_DMA_DISABLE(hi2s->hdmarx);
-    HAL_DMA_Abort(hi2s->hdmarx);
-  }
-
-  /* Disable I2S peripheral */
-  __HAL_I2S_DISABLE(hi2s);
-
-  hi2s->State = HAL_I2S_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hi2s);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles I2S interrupt request.
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval HAL status
-  */
-void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
-{
-  __IO uint32_t i2ssr = hi2s->Instance->SR;
-
-  if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
-  {
-    /* I2S in mode Receiver ----------------------------------------------------*/
-    if(((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
-    {
-      I2S_Receive_IT(hi2s);
-    }
-
-    /* I2S Overrun error interrupt occurred -------------------------------------*/
-    if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
-    {
-      /* Disable RXNE and ERR interrupt */
-      __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
-      /* Set the I2S State ready */
-      hi2s->State = HAL_I2S_STATE_READY;
-
-      /* Set the error code and execute error callback*/
-      hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
-      HAL_I2S_ErrorCallback(hi2s);
-    }
-  }
-  else if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
-  {
-    /* I2S in mode Transmitter ---------------------------------------------------*/
-    if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
-    {
-      I2S_Transmit_IT(hi2s);
-    }
-
-    /* I2S Underrun error interrupt occurred ------------------------------------*/
-    if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
-    {
-      /* Disable TXE and ERR interrupt */
-      __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
-      /* Set the I2S State ready */
-      hi2s->State = HAL_I2S_STATE_READY;
-
-      /* Set the error code and execute error callback*/
-      hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
-      HAL_I2S_ErrorCallback(hi2s);
-    }
-  }
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup I2S_Private_Functions I2S Private Functions
-  * @{
-  */
-/**
-  * @brief This function handles I2S Communication Timeout.
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @param Flag: Flag checked
-  * @param State: Value of the flag expected
-  * @param Timeout: Duration of the timeout
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag,
-                                                       uint32_t State, uint32_t Timeout)
-{
-  uint32_t tickstart = 0;
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  /* Wait until flag is set */
-  if(State == RESET)
-  {
-    while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)
-    {
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Set the I2S State ready */
-          hi2s->State= HAL_I2S_STATE_READY;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2s);
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  else
-  {
-    while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)
-    {
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Set the I2S State ready */
-          hi2s->State= HAL_I2S_STATE_READY;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2s);
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  return HAL_OK;
-}
-/**
-  * @}
-  */
-
-/** @addtogroup I2S_Exported_Functions I2S Exported Functions
-  * @{
-  */
-
-/** @addtogroup  I2S_Exported_Functions_Group2 Input and Output operation functions
-  * @{
-  */
-/**
-  * @brief Tx Transfer Half completed callbacks
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
- __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2s);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief Tx Transfer completed callbacks
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
- __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2s);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2S_TxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief Rx Transfer half completed callbacks
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
-__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2s);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2S_RxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief Rx Transfer completed callbacks
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
-__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2s);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2S_RxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief I2S error callbacks
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
- __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2s);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2S_ErrorCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
-  *  @brief   Peripheral State functions
-  *
-@verbatim
- ===============================================================================
-                      ##### Peripheral State and Errors functions #####
- ===============================================================================
-    [..]
-    This subsection permits to get in run-time the status of the peripheral
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the I2S state
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval HAL state
-  */
-HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
-{
-  return hi2s->State;
-}
-
-/**
-  * @brief  Return the I2S error code
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval I2S Error Code
-  */
-uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
-{
-  return hi2s->ErrorCode;
-}
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-  /**
-  * @brief  Get I2S Input Clock based on I2S source clock selection
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *               the configuration information for I2S module.
-  * @retval I2S Clock Input
-  */
-static uint32_t I2S_GetClockFreq(I2S_HandleTypeDef *hi2s)
-{
-  uint32_t tmpreg = 0;
-  /* This variable used to store the VCO Input (value in Hz) */
-  uint32_t vcoinput = 0;
-  /* This variable used to store the I2S_CK_x (value in Hz) */
-  uint32_t i2sclocksource = 0;
-
-  /* Configure I2S Clock based on I2S source clock selection */
-
-  /* I2S_CLK_x : I2S Block Clock configuration for different clock sources selected */
-  switch(hi2s->Init.ClockSource)
-  {
-    case I2S_CLOCK_PLL :
-    {
-      /* Configure the PLLI2S division factor */
-      /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */
-      if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
-      {
-        /* In Case the PLL Source is HSI (Internal Clock) */
-        vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
-      }
-      else
-      {
-        /* In Case the PLL Source is HSE (External Clock) */
-        vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
-      }
-
-      /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
-      /* I2S_CLK(first level) = PLLI2S_VCO Output/PLLI2SR */
-      tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28;
-      i2sclocksource = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);
-
-      break;
-    }
-    case I2S_CLOCK_EXTERNAL :
-    {
-      i2sclocksource = EXTERNAL_CLOCK_VALUE;
-      break;
-    }
-    default :
-    {
-      break;
-    }
-  }
-
-  /* the return result is the value of I2S clock */
-  return i2sclocksource;
-}
-
-/** @addtogroup I2S_Private_Functions I2S Private Functions
-  * @{
-  */
-/**
-  * @brief DMA I2S transmit process complete callback
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
-{
-  I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
-  {
-    hi2s->TxXferCount = 0;
-
-    /* Disable Tx DMA Request */
-    hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
-
-    if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
-    {
-      if(hi2s->RxXferCount == 0)
-      {
-        hi2s->State = HAL_I2S_STATE_READY;
-      }
-    }
-    else
-    {
-      hi2s->State = HAL_I2S_STATE_READY;
-    }
-  }
-  HAL_I2S_TxCpltCallback(hi2s);
-}
-
-/**
-  * @brief DMA I2S transmit process half complete callback
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  HAL_I2S_TxHalfCpltCallback(hi2s);
-}
-
-/**
-  * @brief DMA I2S receive process complete callback
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
-{
-  I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
-  {
-    /* Disable Rx DMA Request */
-    hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
-
-    hi2s->RxXferCount = 0;
-    if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
-    {
-      if(hi2s->TxXferCount == 0)
-      {
-        hi2s->State = HAL_I2S_STATE_READY;
-      }
-    }
-    else
-    {
-      hi2s->State = HAL_I2S_STATE_READY;
-    }
-  }
-  HAL_I2S_RxCpltCallback(hi2s);
-}
-
-/**
-  * @brief DMA I2S receive process half complete callback
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  HAL_I2S_RxHalfCpltCallback(hi2s);
-}
-
-/**
-  * @brief DMA I2S communication error callback
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void I2S_DMAError(DMA_HandleTypeDef *hdma)
-{
-  I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  /* Disable Rx and Tx DMA Request */
-  hi2s->Instance->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
-  hi2s->TxXferCount = 0;
-  hi2s->RxXferCount = 0;
-
-  hi2s->State= HAL_I2S_STATE_READY;
-
-  /* Set the error code and execute error callback*/
-  hi2s->ErrorCode |= HAL_I2S_ERROR_DMA;
-  HAL_I2S_ErrorCallback(hi2s);
-}
-
-/**
-  * @brief Transmit an amount of data in non-blocking mode with Interrupt
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
-static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
-{
-  /* Transmit data */
-  hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
-  hi2s->TxXferCount--;
-
-  if(hi2s->TxXferCount == 0)
-  {
-    /* Disable TXE and ERR interrupt */
-    __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
-    hi2s->State = HAL_I2S_STATE_READY;
-    HAL_I2S_TxCpltCallback(hi2s);
-  }
-}
-
-/**
-  * @brief Receive an amount of data in non-blocking mode with Interrupt
-  * @param hi2s: I2S handle
-  * @retval None
-  */
-static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
-{
-  /* Receive data */
-  (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
-  hi2s->RxXferCount--;
-
-  if(hi2s->RxXferCount == 0)
-  {
-    /* Disable RXNE and ERR interrupt */
-    __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
-    hi2s->State = HAL_I2S_STATE_READY;
-    HAL_I2S_RxCpltCallback(hi2s);
-  }
-}
-/**
-  * @}
-  */
-
-#endif /* HAL_I2S_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_pcd.c b/stmhal/hal/f7/src/stm32f7xx_hal_pcd.c
deleted file mode 100644
index 09943a6a8e..0000000000
--- a/stmhal/hal/f7/src/stm32f7xx_hal_pcd.c
+++ /dev/null
@@ -1,1311 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_pcd.c
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   PCD HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the USB Peripheral Controller:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions
-  *           + Peripheral State functions
-  *
-  @verbatim
-  ==============================================================================
-                    ##### How to use this driver #####
-  ==============================================================================
-    [..]
-      The PCD HAL driver can be used as follows:
-
-     (#) Declare a PCD_HandleTypeDef handle structure, for example:
-         PCD_HandleTypeDef  hpcd;
-
-     (#) Fill parameters of Init structure in HCD handle
-
-     (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...)
-
-     (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
-         (##) Enable the PCD/USB Low Level interface clock using
-              (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
-              (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)
-
-         (##) Initialize the related GPIO clocks
-         (##) Configure PCD pin-out
-         (##) Configure PCD NVIC interrupt
-
-     (#)Associate the Upper USB device stack to the HAL PCD Driver:
-         (##) hpcd.pData = pdev;
-
-     (#)Enable PCD transmission and reception:
-         (##) HAL_PCD_Start();
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup PCD PCD
-  * @brief PCD HAL module driver
-  * @{
-  */
-
-#ifdef HAL_PCD_MODULE_ENABLED
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup PCD_Private_Macros PCD Private Macros
-  * @{
-  */
-#define PCD_MIN(a, b)  (((a) < (b)) ? (a) : (b))
-#define PCD_MAX(a, b)  (((a) > (b)) ? (a) : (b))
-/**
-  * @}
-  */
-
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup PCD_Private_Functions PCD Private Functions
-  * @{
-  */
-static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup PCD_Exported_Functions PCD Exported Functions
-  * @{
-  */
-
-/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @brief    Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
-            ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the PCD according to the specified
-  *         parameters in the PCD_InitTypeDef and create the associated handle.
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
-{
-  uint32_t i = 0;
-
-  /* Check the PCD handle allocation */
-  if(hpcd == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
-
-  hpcd->State = HAL_PCD_STATE_BUSY;
-
-  /* Init the low level hardware : GPIO, CLOCK, NVIC... */
-  HAL_PCD_MspInit(hpcd);
-
-  /* Disable the Interrupts */
- __HAL_PCD_DISABLE(hpcd);
-
- /*Init the Core (common init.) */
- USB_CoreInit(hpcd->Instance, hpcd->Init);
-
- /* Force Device Mode*/
- USB_SetCurrentMode(hpcd->Instance , USB_OTG_DEVICE_MODE);
-
- /* Init endpoints structures */
- for (i = 0; i < 15 ; i++)
- {
-   /* Init ep structure */
-   hpcd->IN_ep[i].is_in = 1;
-   hpcd->IN_ep[i].num = i;
-   hpcd->IN_ep[i].tx_fifo_num = i;
-   /* Control until ep is activated */
-   hpcd->IN_ep[i].type = EP_TYPE_CTRL;
-   hpcd->IN_ep[i].maxpacket =  0;
-   hpcd->IN_ep[i].xfer_buff = 0;
-   hpcd->IN_ep[i].xfer_len = 0;
- }
-
- for (i = 0; i < 15 ; i++)
- {
-   hpcd->OUT_ep[i].is_in = 0;
-   hpcd->OUT_ep[i].num = i;
-   hpcd->IN_ep[i].tx_fifo_num = i;
-   /* Control until ep is activated */
-   hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
-   hpcd->OUT_ep[i].maxpacket = 0;
-   hpcd->OUT_ep[i].xfer_buff = 0;
-   hpcd->OUT_ep[i].xfer_len = 0;
-
-   hpcd->Instance->DIEPTXF[i] = 0;
- }
-
- /* Init Device */
- USB_DevInit(hpcd->Instance, hpcd->Init);
-
- hpcd->State= HAL_PCD_STATE_READY;
-
- /* Activate LPM */
- if (hpcd->Init.lpm_enable ==1)
- {
-   HAL_PCDEx_ActivateLPM(hpcd);
- }
-
- USB_DevDisconnect (hpcd->Instance);
- return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the PCD peripheral.
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
-{
-  /* Check the PCD handle allocation */
-  if(hpcd == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  hpcd->State = HAL_PCD_STATE_BUSY;
-
-  /* Stop Device */
-  HAL_PCD_Stop(hpcd);
-
-  /* DeInit the low level hardware */
-  HAL_PCD_MspDeInit(hpcd);
-
-  hpcd->State = HAL_PCD_STATE_RESET;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the PCD MSP.
-  * @param  hpcd: PCD handle
-  * @retval None
-  */
-__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCD_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes PCD MSP.
-  * @param  hpcd: PCD handle
-  * @retval None
-  */
-__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCD_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions
- *  @brief   Data transfers functions
- *
-@verbatim
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to manage the PCD data
-    transfers.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Start The USB OTG Device.
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
-{
-  __HAL_LOCK(hpcd);
-  USB_DevConnect (hpcd->Instance);
-  __HAL_PCD_ENABLE(hpcd);
-  __HAL_UNLOCK(hpcd);
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stop The USB OTG Device.
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
-{
-  __HAL_LOCK(hpcd);
-  __HAL_PCD_DISABLE(hpcd);
-  USB_StopDevice(hpcd->Instance);
-  USB_DevDisconnect (hpcd->Instance);
-  __HAL_UNLOCK(hpcd);
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle PCD interrupt request.
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
-{
-  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
-  uint32_t i = 0, ep_intr = 0, epint = 0, epnum = 0;
-  uint32_t fifoemptymsk = 0, temp = 0;
-  USB_OTG_EPTypeDef *ep = NULL;
-  uint32_t hclk = 200000000;
-
-  /* ensure that we are in device mode */
-  if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
-  {
-    /* avoid spurious interrupt */
-    if(__HAL_PCD_IS_INVALID_INTERRUPT(hpcd))
-    {
-      return;
-    }
-
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))
-    {
-     /* incorrect mode, acknowledge the interrupt */
-      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);
-    }
-
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
-    {
-      epnum = 0;
-
-      /* Read in the device interrupt bits */
-      ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance);
-
-      while ( ep_intr )
-      {
-        if (ep_intr & 0x1)
-        {
-          epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, epnum);
-
-          if(( epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)
-          {
-            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC);
-
-            if(hpcd->Init.dma_enable == 1)
-            {
-              hpcd->OUT_ep[epnum].xfer_count = hpcd->OUT_ep[epnum].maxpacket- (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ);
-              hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket;
-            }
-
-            HAL_PCD_DataOutStageCallback(hpcd, epnum);
-            if(hpcd->Init.dma_enable == 1)
-            {
-              if((epnum == 0) && (hpcd->OUT_ep[epnum].xfer_len == 0))
-              {
-                 /* this is ZLP, so prepare EP0 for next setup */
-                USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup);
-              }
-            }
-          }
-
-          if(( epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
-          {
-            /* Inform the upper layer that a setup packet is available */
-            HAL_PCD_SetupStageCallback(hpcd);
-            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
-          }
-
-          if(( epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)
-          {
-            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);
-          }
-          /* Clear Status Phase Received interrupt */
-          if(( epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
-          {
-            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
-          }
-        }
-        epnum++;
-        ep_intr >>= 1;
-      }
-    }
-
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))
-    {
-      /* Read in the device interrupt bits */
-      ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance);
-
-      epnum = 0;
-
-      while ( ep_intr )
-      {
-        if (ep_intr & 0x1) /* In ITR */
-        {
-          epint = USB_ReadDevInEPInterrupt(hpcd->Instance, epnum);
-
-           if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)
-          {
-            fifoemptymsk = 0x1 << epnum;
-            USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
-
-            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);
-
-            if (hpcd->Init.dma_enable == 1)
-            {
-              hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket;
-            }
-
-            HAL_PCD_DataInStageCallback(hpcd, epnum);
-
-            if (hpcd->Init.dma_enable == 1)
-            {
-              /* this is ZLP, so prepare EP0 for next setup */
-              if((epnum == 0) && (hpcd->IN_ep[epnum].xfer_len == 0))
-              {
-                /* prepare to rx more setup packets */
-                USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup);
-              }
-            }
-          }
-           if(( epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)
-          {
-            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC);
-          }
-          if(( epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE)
-          {
-            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE);
-          }
-          if(( epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE)
-          {
-            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE);
-          }
-          if(( epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)
-          {
-            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);
-          }
-          if(( epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)
-          {
-            PCD_WriteEmptyTxFifo(hpcd , epnum);
-          }
-        }
-        epnum++;
-        ep_intr >>= 1;
-      }
-    }
-
-    /* Handle Resume Interrupt */
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))
-    {
-      /* Clear the Remote Wake-up Signaling */
-      USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
-
-      if(hpcd->LPM_State == LPM_L1)
-      {
-        hpcd->LPM_State = LPM_L0;
-        HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);
-      }
-      else
-      {
-        HAL_PCD_ResumeCallback(hpcd);
-      }
-      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);
-    }
-
-    /* Handle Suspend Interrupt */
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
-    {
-      if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
-      {
-
-        HAL_PCD_SuspendCallback(hpcd);
-      }
-      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
-    }
-
-    /* Handle LPM Interrupt */
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT))
-    {
-      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT);
-      if( hpcd->LPM_State == LPM_L0)
-      {
-        hpcd->LPM_State = LPM_L1;
-        hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >>2 ;
-        HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
-      }
-      else
-      {
-        HAL_PCD_SuspendCallback(hpcd);
-      }
-    }
-
-    /* Handle Reset Interrupt */
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
-    {
-      USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
-      USB_FlushTxFifo(hpcd->Instance ,  0 );
-
-      for (i = 0; i < hpcd->Init.dev_endpoints ; i++)
-      {
-        USBx_INEP(i)->DIEPINT = 0xFF;
-        USBx_OUTEP(i)->DOEPINT = 0xFF;
-      }
-      USBx_DEVICE->DAINT = 0xFFFFFFFF;
-      USBx_DEVICE->DAINTMSK |= 0x10001;
-
-      if(hpcd->Init.use_dedicated_ep1)
-      {
-        USBx_DEVICE->DOUTEP1MSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM);
-        USBx_DEVICE->DINEP1MSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);
-      }
-      else
-      {
-        USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM | USB_OTG_DOEPMSK_OTEPSPRM);
-        USBx_DEVICE->DIEPMSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);
-      }
-
-      /* Set Default Address to 0 */
-      USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD;
-
-      /* setup EP0 to receive SETUP packets */
-      USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
-
-      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);
-    }
-
-    /* Handle Enumeration done Interrupt */
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))
-    {
-      USB_ActivateSetup(hpcd->Instance);
-      hpcd->Instance->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
-
-      if ( USB_GetDevSpeed(hpcd->Instance) == USB_OTG_SPEED_HIGH)
-      {
-        hpcd->Init.speed            = USB_OTG_SPEED_HIGH;
-        hpcd->Init.ep0_mps          = USB_OTG_HS_MAX_PACKET_SIZE ;
-        hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_HS_TRDT_VALUE << 10) & USB_OTG_GUSBCFG_TRDT);
-      }
-      else
-      {
-        hpcd->Init.speed            = USB_OTG_SPEED_FULL;
-        hpcd->Init.ep0_mps          = USB_OTG_FS_MAX_PACKET_SIZE ;
-
-        /* The USBTRD is configured according to the tables below, depending on AHB frequency
-        used by application. In the low AHB frequency range it is used to stretch enough the USB response
-        time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access
-        latency to the Data FIFO */
-
-        /* Get hclk frequency value */
-        hclk = HAL_RCC_GetHCLKFreq();
-
-		if((hclk >= 14200000)&&(hclk < 15000000))
-        {
-          /* hclk Clock Range between 14.2-15 MHz */
-          hpcd->Instance->GUSBCFG |= (uint32_t)((0xF << 10) & USB_OTG_GUSBCFG_TRDT);
-        }
-
-        else if((hclk >= 15000000)&&(hclk < 16000000))
-        {
-          /* hclk Clock Range between 15-16 MHz */
-          hpcd->Instance->GUSBCFG |= (uint32_t)((0xE << 10) & USB_OTG_GUSBCFG_TRDT);
-        }
-
-        else if((hclk >= 16000000)&&(hclk < 17200000))
-        {
-          /* hclk Clock Range between 16-17.2 MHz */
-          hpcd->Instance->GUSBCFG |= (uint32_t)((0xD << 10) & USB_OTG_GUSBCFG_TRDT);
-        }
-
-        else if((hclk >= 17200000)&&(hclk < 18500000))
-        {
-          /* hclk Clock Range between 17.2-18.5 MHz */
-          hpcd->Instance->GUSBCFG |= (uint32_t)((0xC << 10) & USB_OTG_GUSBCFG_TRDT);
-        }
-
-        else if((hclk >= 18500000)&&(hclk < 20000000))
-        {
-          /* hclk Clock Range between 18.5-20 MHz */
-          hpcd->Instance->GUSBCFG |= (uint32_t)((0xB << 10) & USB_OTG_GUSBCFG_TRDT);
-        }
-
-        else if((hclk >= 20000000)&&(hclk < 21800000))
-        {
-          /* hclk Clock Range between 20-21.8 MHz */
-          hpcd->Instance->GUSBCFG |= (uint32_t)((0xA << 10) & USB_OTG_GUSBCFG_TRDT);
-        }
-
-        else if((hclk >= 21800000)&&(hclk < 24000000))
-        {
-          /* hclk Clock Range between 21.8-24 MHz */
-          hpcd->Instance->GUSBCFG |= (uint32_t)((0x9 << 10) & USB_OTG_GUSBCFG_TRDT);
-        }
-
-        else if((hclk >= 24000000)&&(hclk < 27700000))
-        {
-          /* hclk Clock Range between 24-27.7 MHz */
-          hpcd->Instance->GUSBCFG |= (uint32_t)((0x8 << 10) & USB_OTG_GUSBCFG_TRDT);
-        }
-
-        else if((hclk >= 27700000)&&(hclk < 32000000))
-        {
-          /* hclk Clock Range between 27.7-32 MHz */
-          hpcd->Instance->GUSBCFG |= (uint32_t)((0x7 << 10) & USB_OTG_GUSBCFG_TRDT);
-        }
-
-        else /* if(hclk >= 32000000) */
-        {
-          /* hclk Clock Range between 32-200 MHz */
-          hpcd->Instance->GUSBCFG |= (uint32_t)((0x6 << 10) & USB_OTG_GUSBCFG_TRDT);
-        }
-      }
-
-      HAL_PCD_ResetCallback(hpcd);
-
-      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
-    }
-
-    /* Handle RxQLevel Interrupt */
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
-    {
-      USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
-      temp = USBx->GRXSTSP;
-      ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];
-
-      if(((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) ==  STS_DATA_UPDT)
-      {
-        if((temp & USB_OTG_GRXSTSP_BCNT) != 0)
-        {
-          USB_ReadPacket(USBx, ep->xfer_buff, (temp & USB_OTG_GRXSTSP_BCNT) >> 4);
-          ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
-          ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
-        }
-      }
-      else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) ==  STS_SETUP_UPDT)
-      {
-        USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8);
-        ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
-      }
-      USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
-    }
-
-    /* Handle SOF Interrupt */
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
-    {
-      HAL_PCD_SOFCallback(hpcd);
-      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);
-    }
-
-    /* Handle Incomplete ISO IN Interrupt */
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
-    {
-      HAL_PCD_ISOINIncompleteCallback(hpcd, epnum);
-      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);
-    }
-
-    /* Handle Incomplete ISO OUT Interrupt */
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
-    {
-      HAL_PCD_ISOOUTIncompleteCallback(hpcd, epnum);
-      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
-    }
-
-    /* Handle Connection event Interrupt */
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))
-    {
-      HAL_PCD_ConnectCallback(hpcd);
-      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT);
-    }
-
-    /* Handle Disconnection event Interrupt */
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))
-    {
-      temp = hpcd->Instance->GOTGINT;
-
-      if((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)
-      {
-        HAL_PCD_DisconnectCallback(hpcd);
-      }
-      hpcd->Instance->GOTGINT |= temp;
-    }
-  }
-}
-
-/**
-  * @brief  Data OUT stage callback.
-  * @param  hpcd: PCD handle
-  * @param  epnum: endpoint number
-  * @retval None
-  */
- __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-  UNUSED(epnum);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCD_DataOutStageCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Data IN stage callback.
-  * @param  hpcd: PCD handle
-  * @param  epnum: endpoint number
-  * @retval None
-  */
- __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-  UNUSED(epnum);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCD_DataInStageCallback could be implemented in the user file
-   */
-}
-/**
-  * @brief  Setup stage callback.
-  * @param  hpcd: PCD handle
-  * @retval None
-  */
- __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCD_SetupStageCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  USB Start Of Frame callback.
-  * @param  hpcd: PCD handle
-  * @retval None
-  */
- __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCD_SOFCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  USB Reset callback.
-  * @param  hpcd: PCD handle
-  * @retval None
-  */
- __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCD_ResetCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Suspend event callback.
-  * @param  hpcd: PCD handle
-  * @retval None
-  */
- __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCD_SuspendCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Resume event callback.
-  * @param  hpcd: PCD handle
-  * @retval None
-  */
- __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCD_ResumeCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Incomplete ISO OUT callback.
-  * @param  hpcd: PCD handle
-  * @param  epnum: endpoint number
-  * @retval None
-  */
- __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-  UNUSED(epnum);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Incomplete ISO IN  callback.
-  * @param  hpcd: PCD handle
-  * @param  epnum: endpoint number
-  * @retval None
-  */
- __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-  UNUSED(epnum);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Connection event callback.
-  * @param  hpcd: PCD handle
-  * @retval None
-  */
- __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCD_ConnectCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Disconnection event callback.
-  * @param  hpcd: PCD handle
-  * @retval None
-  */
- __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCD_DisconnectCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
- *  @brief   management functions
- *
-@verbatim
- ===============================================================================
-                      ##### Peripheral Control functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to control the PCD data
-    transfers.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Connect the USB device.
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
-{
-  __HAL_LOCK(hpcd);
-  USB_DevConnect(hpcd->Instance);
-  __HAL_UNLOCK(hpcd);
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disconnect the USB device.
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
-{
-  __HAL_LOCK(hpcd);
-  USB_DevDisconnect(hpcd->Instance);
-  __HAL_UNLOCK(hpcd);
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set the USB Device address.
-  * @param  hpcd: PCD handle
-  * @param  address: new device address
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
-{
-  __HAL_LOCK(hpcd);
-  USB_SetDevAddress(hpcd->Instance, address);
-  __HAL_UNLOCK(hpcd);
-  return HAL_OK;
-}
-/**
-  * @brief  Open and configure an endpoint.
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
-  * @param  ep_mps: endpoint max packet size
-  * @param  ep_type: endpoint type
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
-{
-  HAL_StatusTypeDef  ret = HAL_OK;
-  USB_OTG_EPTypeDef *ep;
-
-  if ((ep_addr & 0x80) == 0x80)
-  {
-    ep = &hpcd->IN_ep[ep_addr & 0x7F];
-  }
-  else
-  {
-    ep = &hpcd->OUT_ep[ep_addr & 0x7F];
-  }
-  ep->num   = ep_addr & 0x7F;
-
-  ep->is_in = (0x80 & ep_addr) != 0;
-  ep->maxpacket = ep_mps;
-  ep->type = ep_type;
-  if (ep->is_in)
-  {
-    /* Assign a Tx FIFO */
-    ep->tx_fifo_num = ep->num;
-  }
-  /* Set initial data PID. */
-  if (ep_type == EP_TYPE_BULK )
-  {
-    ep->data_pid_start = 0;
-  }
-
-  __HAL_LOCK(hpcd);
-  USB_ActivateEndpoint(hpcd->Instance , ep);
-  __HAL_UNLOCK(hpcd);
-  return ret;
-}
-
-
-/**
-  * @brief  Deactivate an endpoint.
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
-  USB_OTG_EPTypeDef *ep;
-
-  if ((ep_addr & 0x80) == 0x80)
-  {
-    ep = &hpcd->IN_ep[ep_addr & 0x7F];
-  }
-  else
-  {
-    ep = &hpcd->OUT_ep[ep_addr & 0x7F];
-  }
-  ep->num   = ep_addr & 0x7F;
-
-  ep->is_in = (0x80 & ep_addr) != 0;
-
-  __HAL_LOCK(hpcd);
-  USB_DeactivateEndpoint(hpcd->Instance , ep);
-  __HAL_UNLOCK(hpcd);
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  Receive an amount of data.
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
-  * @param  pBuf: pointer to the reception buffer
-  * @param  len: amount of data to be received
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
-{
-  USB_OTG_EPTypeDef *ep;
-
-  ep = &hpcd->OUT_ep[ep_addr & 0x7F];
-
-  /*setup and start the Xfer */
-  ep->xfer_buff = pBuf;
-  ep->xfer_len = len;
-  ep->xfer_count = 0;
-  ep->is_in = 0;
-  ep->num = ep_addr & 0x7F;
-
-  if (hpcd->Init.dma_enable == 1)
-  {
-    ep->dma_addr = (uint32_t)pBuf;
-  }
-
-  __HAL_LOCK(hpcd);
-
-  if ((ep_addr & 0x7F) == 0 )
-  {
-    USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
-  }
-  else
-  {
-    USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
-  }
-  __HAL_UNLOCK(hpcd);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Get Received Data Size.
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
-  * @retval Data Size
-  */
-uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
-  return hpcd->OUT_ep[ep_addr & 0x7F].xfer_count;
-}
-/**
-  * @brief  Send an amount of data.
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
-  * @param  pBuf: pointer to the transmission buffer
-  * @param  len: amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
-{
-  USB_OTG_EPTypeDef *ep;
-
-  ep = &hpcd->IN_ep[ep_addr & 0x7F];
-
-  /*setup and start the Xfer */
-  ep->xfer_buff = pBuf;
-  ep->xfer_len = len;
-  ep->xfer_count = 0;
-  ep->is_in = 1;
-  ep->num = ep_addr & 0x7F;
-
-  if (hpcd->Init.dma_enable == 1)
-  {
-    ep->dma_addr = (uint32_t)pBuf;
-  }
-
-  __HAL_LOCK(hpcd);
-
-  if ((ep_addr & 0x7F) == 0 )
-  {
-    USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
-  }
-  else
-  {
-    USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
-  }
-
-  __HAL_UNLOCK(hpcd);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set a STALL condition over an endpoint.
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
-  USB_OTG_EPTypeDef *ep;
-
-  if ((0x80 & ep_addr) == 0x80)
-  {
-    ep = &hpcd->IN_ep[ep_addr & 0x7F];
-  }
-  else
-  {
-    ep = &hpcd->OUT_ep[ep_addr];
-  }
-
-  ep->is_stall = 1;
-  ep->num   = ep_addr & 0x7F;
-  ep->is_in = ((ep_addr & 0x80) == 0x80);
-
-
-  __HAL_LOCK(hpcd);
-  USB_EPSetStall(hpcd->Instance , ep);
-  if((ep_addr & 0x7F) == 0)
-  {
-    USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
-  }
-  __HAL_UNLOCK(hpcd);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Clear a STALL condition over in an endpoint.
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
-  USB_OTG_EPTypeDef *ep;
-
-  if ((0x80 & ep_addr) == 0x80)
-  {
-    ep = &hpcd->IN_ep[ep_addr & 0x7F];
-  }
-  else
-  {
-    ep = &hpcd->OUT_ep[ep_addr];
-  }
-
-  ep->is_stall = 0;
-  ep->num   = ep_addr & 0x7F;
-  ep->is_in = ((ep_addr & 0x80) == 0x80);
-
-  __HAL_LOCK(hpcd);
-  USB_EPClearStall(hpcd->Instance , ep);
-  __HAL_UNLOCK(hpcd);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Flush an endpoint.
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
-  __HAL_LOCK(hpcd);
-
-  if ((ep_addr & 0x80) == 0x80)
-  {
-    USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7F);
-  }
-  else
-  {
-    USB_FlushRxFifo(hpcd->Instance);
-  }
-
-  __HAL_UNLOCK(hpcd);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Activate remote wakeup signalling.
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
-{
-  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
-
-  if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
-  {
-    /* Activate Remote wakeup signaling */
-    USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  De-activate remote wakeup signalling.
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
-{
-  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
-
-  /* De-activate Remote wakeup signaling */
-   USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);
-  return HAL_OK;
-}
-/**
-  * @}
-  */
-
-/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
- *  @brief   Peripheral State functions
- *
-@verbatim
- ===============================================================================
-                      ##### Peripheral State functions #####
- ===============================================================================
-    [..]
-    This subsection permits to get in run-time the status of the peripheral
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the PCD handle state.
-  * @param  hpcd: PCD handle
-  * @retval HAL state
-  */
-PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
-{
-  return hpcd->State;
-}
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @addtogroup PCD_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Check FIFO for the next packet to be loaded.
-  * @param  hpcd: PCD handle
-  * @param  epnum : endpoint number
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)
-{
-  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
-  USB_OTG_EPTypeDef *ep;
-  int32_t len = 0;
-  uint32_t len32b;
-  uint32_t fifoemptymsk = 0;
-
-  ep = &hpcd->IN_ep[epnum];
-  len = ep->xfer_len - ep->xfer_count;
-
-  if (len > ep->maxpacket)
-  {
-    len = ep->maxpacket;
-  }
-
-
-  len32b = (len + 3) / 4;
-
-  while  ( (USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b &&
-          ep->xfer_count < ep->xfer_len &&
-            ep->xfer_len != 0)
-  {
-    /* Write the FIFO */
-    len = ep->xfer_len - ep->xfer_count;
-
-    if (len > ep->maxpacket)
-    {
-      len = ep->maxpacket;
-    }
-    len32b = (len + 3) / 4;
-
-    USB_WritePacket(USBx, ep->xfer_buff, epnum, len, hpcd->Init.dma_enable);
-
-    ep->xfer_buff  += len;
-    ep->xfer_count += len;
-  }
-
-  if(len <= 0)
-  {
-    fifoemptymsk = 0x1 << epnum;
-    USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
-
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_PCD_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_pcd_ex.c b/stmhal/hal/f7/src/stm32f7xx_hal_pcd_ex.c
deleted file mode 100644
index 12fca17458..0000000000
--- a/stmhal/hal/f7/src/stm32f7xx_hal_pcd_ex.c
+++ /dev/null
@@ -1,203 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_pcd_ex.c
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   PCD HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the USB Peripheral Controller:
-  *           + Extended features functions
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup PCDEx PCDEx
-  * @brief PCD Extended HAL module driver
-  * @{
-  */
-#ifdef HAL_PCD_MODULE_ENABLED
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
-  * @{
-  */
-
-/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
-  * @brief    PCDEx control functions
- *
-@verbatim
- ===============================================================================
-                 ##### Extended features functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Update FIFO configuration
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Set Tx FIFO
-  * @param  hpcd: PCD handle
-  * @param  fifo: The number of Tx fifo
-  * @param  size: Fifo size
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
-{
-  uint8_t i = 0;
-  uint32_t Tx_Offset = 0;
-
-  /*  TXn min size = 16 words. (n  : Transmit FIFO index)
-      When a TxFIFO is not used, the Configuration should be as follows:
-          case 1 :  n > m    and Txn is not used    (n,m  : Transmit FIFO indexes)
-         --> Txm can use the space allocated for Txn.
-         case2  :  n < m    and Txn is not used    (n,m  : Transmit FIFO indexes)
-         --> Txn should be configured with the minimum space of 16 words
-     The FIFO is used optimally when used TxFIFOs are allocated in the top
-         of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
-     When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
-
-  Tx_Offset = hpcd->Instance->GRXFSIZ;
-
-  if(fifo == 0)
-  {
-    hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((uint32_t)size << 16) | Tx_Offset);
-  }
-  else
-  {
-    Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;
-    for (i = 0; i < (fifo - 1); i++)
-    {
-      Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);
-    }
-
-    /* Multiply Tx_Size by 2 to get higher performance */
-    hpcd->Instance->DIEPTXF[fifo - 1] = (uint32_t)(((uint32_t)size << 16) | Tx_Offset);
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set Rx FIFO
-  * @param  hpcd: PCD handle
-  * @param  size: Size of Rx fifo
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
-{
-  hpcd->Instance->GRXFSIZ = size;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Activate LPM Feature
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
-{
-  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
-
-  hpcd->lpm_active = ENABLE;
-  hpcd->LPM_State = LPM_L0;
-  USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
-  USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeActivate LPM feature.
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
-{
-  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
-
-  hpcd->lpm_active = DISABLE;
-  USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM;
-  USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Send LPM message to user layer callback.
-  * @param  hpcd: PCD handle
-  * @param  msg: LPM message
-  * @retval HAL status
-  */
-__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-  UNUSED(msg);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCDEx_LPM_Callback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_PCD_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_pwr.c b/stmhal/hal/f7/src/stm32f7xx_hal_pwr.c
deleted file mode 100644
index e8258192fb..0000000000
--- a/stmhal/hal/f7/src/stm32f7xx_hal_pwr.c
+++ /dev/null
@@ -1,609 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_pwr.c
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   PWR HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Power Controller (PWR) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + Peripheral Control functions
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup PWR PWR
-  * @brief PWR HAL module driver
-  * @{
-  */
-
-#ifdef HAL_PWR_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup PWR_Private_Constants
-  * @{
-  */
-
-/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
-  * @{
-  */
-#define PVD_MODE_IT               ((uint32_t)0x00010000U)
-#define PVD_MODE_EVT              ((uint32_t)0x00020000U)
-#define PVD_RISING_EDGE           ((uint32_t)0x00000001U)
-#define PVD_FALLING_EDGE          ((uint32_t)0x00000002U)
-/**
-  * @}
-  */
-
-/** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask
-  * @{
-  */
-#define  PWR_EWUP_MASK                          ((uint32_t)0x00003F00)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup PWR_Exported_Functions PWR Exported Functions
-  * @{
-  */
-
-/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
-  *  @brief    Initialization and de-initialization functions
-  *
-@verbatim
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]
-      After reset, the backup domain (RTC registers, RTC backup data
-      registers and backup SRAM) is protected against possible unwanted
-      write accesses.
-      To enable access to the RTC Domain and RTC registers, proceed as follows:
-        (+) Enable the Power Controller (PWR) APB1 interface clock using the
-            __HAL_RCC_PWR_CLK_ENABLE() macro.
-        (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Deinitializes the HAL PWR peripheral registers to their default reset values.
-  * @retval None
-  */
-void HAL_PWR_DeInit(void)
-{
-  __HAL_RCC_PWR_FORCE_RESET();
-  __HAL_RCC_PWR_RELEASE_RESET();
-}
-
-/**
-  * @brief Enables access to the backup domain (RTC registers, RTC
-  *         backup data registers and backup SRAM).
-  * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
-  *         Backup Domain Access should be kept enabled.
-  * @retval None
-  */
-void HAL_PWR_EnableBkUpAccess(void)
-{
-  /* Enable access to RTC and backup registers */
-  SET_BIT(PWR->CR1, PWR_CR1_DBP);
-}
-
-/**
-  * @brief Disables access to the backup domain (RTC registers, RTC
-  *         backup data registers and backup SRAM).
-  * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
-  *         Backup Domain Access should be kept enabled.
-  * @retval None
-  */
-void HAL_PWR_DisableBkUpAccess(void)
-{
-  /* Disable access to RTC and backup registers */
-	CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
-  *  @brief Low Power modes configuration functions
-  *
-@verbatim
-
- ===============================================================================
-                 ##### Peripheral Control functions #####
- ===============================================================================
-
-    *** PVD configuration ***
-    =========================
-    [..]
-      (+) The PVD is used to monitor the VDD power supply by comparing it to a
-          threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
-      (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
-          than the PVD threshold. This event is internally connected to the EXTI
-          line16 and can generate an interrupt if enabled. This is done through
-          __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
-      (+) The PVD is stopped in Standby mode.
-
-    *** Wake-up pin configuration ***
-    ================================
-    [..]
-      (+) Wake-up pin is used to wake up the system from Standby mode. This pin is
-          forced in input pull-down configuration and is active on rising edges.
-      (+) There are to 6 Wake-up pin in the STM32F7 devices family
-
-    *** Low Power modes configuration ***
-    =====================================
-    [..]
-      The devices feature 3 low-power modes:
-      (+) Sleep mode: Cortex-M7 core stopped, peripherals kept running.
-      (+) Stop mode: all clocks are stopped, regulator running, regulator
-          in low power mode
-      (+) Standby mode: 1.2V domain powered off.
-
-   *** Sleep mode ***
-   ==================
-    [..]
-      (+) Entry:
-        The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI)
-              functions with
-          (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
-          (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
-
-      -@@- The Regulator parameter is not used for the STM32F7 family
-              and is kept as parameter just to maintain compatibility with the
-              lower power families (STM32L).
-      (+) Exit:
-        Any peripheral interrupt acknowledged by the nested vectored interrupt
-              controller (NVIC) can wake up the device from Sleep mode.
-
-   *** Stop mode ***
-   =================
-    [..]
-      In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
-      and the HSE RC oscillators are disabled. Internal SRAM and register contents
-      are preserved.
-      The voltage regulator can be configured either in normal or low-power mode.
-      To minimize the consumption In Stop mode, FLASH can be powered off before
-      entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.
-      It can be switched on again by software after exiting the Stop mode using
-      the HAL_PWREx_DisableFlashPowerDown() function.
-
-      (+) Entry:
-         The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON)
-             function with:
-          (++) Main regulator ON.
-          (++) Low Power regulator ON.
-      (+) Exit:
-        Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
-
-   *** Standby mode ***
-   ====================
-    [..]
-    (+)
-      The Standby mode allows to achieve the lowest power consumption. It is based
-      on the Cortex-M7 deep sleep mode, with the voltage regulator disabled.
-      The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and
-      the HSE oscillator are also switched off. SRAM and register contents are lost
-      except for the RTC registers, RTC backup registers, backup SRAM and Standby
-      circuitry.
-
-      The voltage regulator is OFF.
-
-      (++) Entry:
-        (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
-      (++) Exit:
-        (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC
-             wakeup, tamper event, time stamp event, external reset in NRST pin, IWDG reset.
-
-   *** Auto-wakeup (AWU) from low-power mode ***
-   =============================================
-    [..]
-
-     (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
-      Wakeup event, a tamper event or a time-stamp event, without depending on
-      an external interrupt (Auto-wakeup mode).
-
-      (+) RTC auto-wakeup (AWU) from the Stop and Standby modes
-
-        (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
-              configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
-
-        (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
-             is necessary to configure the RTC to detect the tamper or time stamp event using the
-                HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
-
-        (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
-              configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
-  * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
-  *        information for the PVD.
-  * @note Refer to the electrical characteristics of your device datasheet for
-  *         more details about the voltage threshold corresponding to each
-  *         detection level.
-  * @retval None
-  */
-void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
-{
-  /* Check the parameters */
-  assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
-  assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
-
-  /* Set PLS[7:5] bits according to PVDLevel value */
-  MODIFY_REG(PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel);
-
-  /* Clear any previous config. Keep it clear if no event or IT mode is selected */
-  __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
-  __HAL_PWR_PVD_EXTI_DISABLE_IT();
-  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
-  __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
-
-  /* Configure interrupt mode */
-  if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
-  {
-    __HAL_PWR_PVD_EXTI_ENABLE_IT();
-  }
-
-  /* Configure event mode */
-  if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
-  {
-    __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
-  }
-
-  /* Configure the edge */
-  if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
-  {
-    __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
-  }
-
-  if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
-  {
-    __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
-  }
-}
-
-/**
-  * @brief Enables the Power Voltage Detector(PVD).
-  * @retval None
-  */
-void HAL_PWR_EnablePVD(void)
-{
-  /* Enable the power voltage detector */
-	SET_BIT(PWR->CR1, PWR_CR1_PVDE);
-}
-
-/**
-  * @brief Disables the Power Voltage Detector(PVD).
-  * @retval None
-  */
-void HAL_PWR_DisablePVD(void)
-{
-  /* Disable the power voltage detector */
-	CLEAR_BIT(PWR->CR1, PWR_CR1_PVDE);
-}
-
-/**
-  * @brief Enable the WakeUp PINx functionality.
-  * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable.
-  *         This parameter can be one of the following legacy values, which sets the default polarity:
-  *         detection on high level (rising edge):
-  *           @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6
-  *         or one of the following value where the user can explicitly states the enabled pin and
-  *         the chosen polarity
-  *           @arg PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
-  *           @arg PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
-  *           @arg PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
-  *           @arg PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
-  *           @arg PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
-  *           @arg PWR_WAKEUP_PIN6_HIGH or PWR_WAKEUP_PIN6_LOW
-  * @note  PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
-  * @retval None
-  */
-void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
-{
-  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
-
-  /* Enable wake-up pin */
-  SET_BIT(PWR->CSR2, (PWR_EWUP_MASK & WakeUpPinPolarity));
-
-  /* Specifies the Wake-Up pin polarity for the event detection
-    (rising or falling edge) */
-  MODIFY_REG(PWR->CR2, (PWR_EWUP_MASK & WakeUpPinPolarity), (WakeUpPinPolarity >> 0x06));
-}
-
-/**
-  * @brief Disables the WakeUp PINx functionality.
-  * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
-  *         This parameter can be one of the following values:
-  *           @arg PWR_WAKEUP_PIN1
-  *           @arg PWR_WAKEUP_PIN2
-  *           @arg PWR_WAKEUP_PIN3
-  *           @arg PWR_WAKEUP_PIN4
-  *           @arg PWR_WAKEUP_PIN5
-  *           @arg PWR_WAKEUP_PIN6
-  * @retval None
-  */
-void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
-{
-  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
-
-  CLEAR_BIT(PWR->CSR2, WakeUpPinx);
-}
-
-/**
-  * @brief Enters Sleep mode.
-  *
-  * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
-  *
-  * @note In Sleep mode, the systick is stopped to avoid exit from this mode with
-  *       systick interrupt when used as time base for Timeout
-  *
-  * @param Regulator: Specifies the regulator state in SLEEP mode.
-  *            This parameter can be one of the following values:
-  *            @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
-  *            @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
-  * @note This parameter is not used for the STM32F7 family and is kept as parameter
-  *       just to maintain compatibility with the lower power families.
-  * @param SLEEPEntry: Specifies if SLEEP mode in entered with WFI or WFE instruction.
-  *          This parameter can be one of the following values:
-  *            @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
-  *            @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
-  * @retval None
-  */
-void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
-{
-  /* Check the parameters */
-  assert_param(IS_PWR_REGULATOR(Regulator));
-  assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
-
-  /* Clear SLEEPDEEP bit of Cortex System Control Register */
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-
-  /* Select SLEEP mode entry -------------------------------------------------*/
-  if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
-  {
-    /* Request Wait For Interrupt */
-    __WFI();
-  }
-  else
-  {
-    /* Request Wait For Event */
-    __SEV();
-    __WFE();
-    __WFE();
-  }
-}
-
-/**
-  * @brief Enters Stop mode.
-  * @note In Stop mode, all I/O pins keep the same state as in Run mode.
-  * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
-  *         the HSI RC oscillator is selected as system clock.
-  * @note When the voltage regulator operates in low power mode, an additional
-  *         startup delay is incurred when waking up from Stop mode.
-  *         By keeping the internal regulator ON during Stop mode, the consumption
-  *         is higher although the startup time is reduced.
-  * @param Regulator: Specifies the regulator state in Stop mode.
-  *          This parameter can be one of the following values:
-  *            @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
-  *            @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
-  * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
-  *          This parameter can be one of the following values:
-  *            @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
-  *            @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
-  * @retval None
-  */
-void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_PWR_REGULATOR(Regulator));
-  assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
-
-  /* Select the regulator state in Stop mode ---------------------------------*/
-  tmpreg = PWR->CR1;
-  /* Clear PDDS and LPDS bits */
-  tmpreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS);
-
-  /* Set LPDS, MRLVDS and LPLVDS bits according to Regulator value */
-  tmpreg |= Regulator;
-
-  /* Store the new value */
-  PWR->CR1 = tmpreg;
-
-  /* Set SLEEPDEEP bit of Cortex System Control Register */
-  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-
-  /* Select Stop mode entry --------------------------------------------------*/
-  if(STOPEntry == PWR_STOPENTRY_WFI)
-  {
-    /* Request Wait For Interrupt */
-    __WFI();
-  }
-  else
-  {
-    /* Request Wait For Event */
-    __SEV();
-    __WFE();
-    __WFE();
-  }
-  /* Reset SLEEPDEEP bit of Cortex System Control Register */
-  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
-}
-
-/**
-  * @brief Enters Standby mode.
-  * @note In Standby mode, all I/O pins are high impedance except for:
-  *          - Reset pad (still available)
-  *          - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC
-  *            Alarm out, or RTC clock calibration out.
-  *          - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.
-  *          - WKUP pins if enabled.
-  * @retval None
-  */
-void HAL_PWR_EnterSTANDBYMode(void)
-{
-  /* Select Standby mode */
-  PWR->CR1 |= PWR_CR1_PDDS;
-
-  /* Set SLEEPDEEP bit of Cortex System Control Register */
-  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-
-  /* This option is used to ensure that store operations are completed */
-#if defined ( __CC_ARM)
-  __force_stores();
-#endif
-  /* Request Wait For Interrupt */
-  __WFI();
-}
-
-/**
-  * @brief This function handles the PWR PVD interrupt request.
-  * @note This API should be called under the PVD_IRQHandler().
-  * @retval None
-  */
-void HAL_PWR_PVD_IRQHandler(void)
-{
-  /* Check PWR Exti flag */
-  if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
-  {
-    /* PWR PVD interrupt user callback */
-    HAL_PWR_PVDCallback();
-
-    /* Clear PWR Exti pending bit */
-    __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
-  }
-}
-
-/**
-  * @brief  PWR PVD interrupt callback
-  * @retval None
-  */
-__weak void HAL_PWR_PVDCallback(void)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PWR_PVDCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
-  * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
-  *       re-enters SLEEP mode when an interruption handling is over.
-  *       Setting this bit is useful when the processor is expected to run only on
-  *       interruptions handling.
-  * @retval None
-  */
-void HAL_PWR_EnableSleepOnExit(void)
-{
-  /* Set SLEEPONEXIT bit of Cortex System Control Register */
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
-}
-
-/**
-  * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
-  * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
-  *       re-enters SLEEP mode when an interruption handling is over.
-  * @retval None
-  */
-void HAL_PWR_DisableSleepOnExit(void)
-{
-  /* Clear SLEEPONEXIT bit of Cortex System Control Register */
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
-}
-
-/**
-  * @brief Enables CORTEX M4 SEVONPEND bit.
-  * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
-  *       WFE to wake up when an interrupt moves from inactive to pended.
-  * @retval None
-  */
-void HAL_PWR_EnableSEVOnPend(void)
-{
-  /* Set SEVONPEND bit of Cortex System Control Register */
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
-}
-
-/**
-  * @brief Disables CORTEX M4 SEVONPEND bit.
-  * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
-  *       WFE to wake up when an interrupt moves from inactive to pended.
-  * @retval None
-  */
-void HAL_PWR_DisableSEVOnPend(void)
-{
-  /* Clear SEVONPEND bit of Cortex System Control Register */
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_PWR_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_pwr_ex.c b/stmhal/hal/f7/src/stm32f7xx_hal_pwr_ex.c
deleted file mode 100644
index e77873b40d..0000000000
--- a/stmhal/hal/f7/src/stm32f7xx_hal_pwr_ex.c
+++ /dev/null
@@ -1,572 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_pwr_ex.c
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   Extended PWR HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of PWR extension peripheral:
-  *           + Peripheral Extended features functions
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup PWREx PWREx
-  * @brief PWR HAL module driver
-  * @{
-  */
-
-#ifdef HAL_PWR_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup PWREx_Private_Constants
-  * @{
-  */
-#define PWR_OVERDRIVE_TIMEOUT_VALUE  1000
-#define PWR_UDERDRIVE_TIMEOUT_VALUE  1000
-#define PWR_BKPREG_TIMEOUT_VALUE     1000
-#define PWR_VOSRDY_TIMEOUT_VALUE     1000
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup PWREx_Exported_Functions PWREx Exported Functions
-  *  @{
-  */
-
-/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions
-  *  @brief Peripheral Extended features functions
-  *
-@verbatim
-
- ===============================================================================
-                 ##### Peripheral extended features functions #####
- ===============================================================================
-
-    *** Main and Backup Regulators configuration ***
-    ================================================
-    [..]
-      (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from
-          the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is
-          retained even in Standby or VBAT mode when the low power backup regulator
-          is enabled. It can be considered as an internal EEPROM when VBAT is
-          always present. You can use the HAL_PWREx_EnableBkUpReg() function to
-          enable the low power backup regulator.
-
-      (+) When the backup domain is supplied by VDD (analog switch connected to VDD)
-          the backup SRAM is powered from VDD which replaces the VBAT power supply to
-          save battery life.
-
-      (+) The backup SRAM is not mass erased by a tamper event. It is read
-          protected to prevent confidential data, such as cryptographic private
-          key, from being accessed. The backup SRAM can be erased only through
-          the Flash interface when a protection level change from level 1 to
-          level 0 is requested.
-      -@- Refer to the description of Read protection (RDP) in the Flash
-          programming manual.
-
-      (+) The main internal regulator can be configured to have a tradeoff between
-          performance and power consumption when the device does not operate at
-          the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG()
-          macro which configure VOS bit in PWR_CR register
-
-        Refer to the product datasheets for more details.
-
-    *** FLASH Power Down configuration ****
-    =======================================
-    [..]
-      (+) By setting the FPDS bit in the PWR_CR register by using the
-          HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power
-          down mode when the device enters Stop mode. When the Flash memory
-          is in power down mode, an additional startup delay is incurred when
-          waking up from Stop mode.
-
-    *** Over-Drive and Under-Drive configuration ****
-    =================================================
-    [..]
-       (+) In Run mode: the main regulator has 2 operating modes available:
-        (++) Normal mode: The CPU and core logic operate at maximum frequency at a given
-             voltage scaling (scale 1, scale 2 or scale 3)
-        (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a
-            higher frequency than the normal mode for a given voltage scaling (scale 1,
-            scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and
-            disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow
-            the sequence described in Reference manual.
-
-       (+) In Stop mode: the main regulator or low power regulator supplies a low power
-           voltage to the 1.2V domain, thus preserving the content of registers
-           and internal SRAM. 2 operating modes are available:
-         (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only
-              available when the main regulator or the low power regulator is used in Scale 3 or
-              low voltage mode.
-         (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only
-              available when the main regulator or the low power regulator is in low voltage mode.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Enables the Backup Regulator.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)
-{
-  uint32_t tickstart = 0;
-
-  /* Enable Backup regulator */
-  PWR->CSR1 |= PWR_CSR1_BRE;
-
-  /* Workaround for the following hardware bug: */
-  /* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */
-  PWR->CSR1 |= PWR_CSR1_EIWUP;
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  /* Wait till Backup regulator ready flag is set */
-  while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET)
-  {
-    if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief Disables the Backup Regulator.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)
-{
-  uint32_t tickstart = 0;
-
-  /* Disable Backup regulator */
-  PWR->CSR1 &= (uint32_t)~((uint32_t)PWR_CSR1_BRE);
-
-  /* Workaround for the following hardware bug: */
-  /* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */
-  PWR->CSR1 |= PWR_CSR1_EIWUP;
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  /* Wait till Backup regulator ready flag is set */
-  while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET)
-  {
-    if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief Enables the Flash Power Down in Stop mode.
-  * @retval None
-  */
-void HAL_PWREx_EnableFlashPowerDown(void)
-{
-  /* Enable the Flash Power Down */
-  PWR->CR1 |= PWR_CR1_FPDS;
-}
-
-/**
-  * @brief Disables the Flash Power Down in Stop mode.
-  * @retval None
-  */
-void HAL_PWREx_DisableFlashPowerDown(void)
-{
-  /* Disable the Flash Power Down */
-  PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_FPDS);
-}
-
-/**
-  * @brief Enables Main Regulator low voltage mode.
-  * @retval None
-  */
-void HAL_PWREx_EnableMainRegulatorLowVoltage(void)
-{
-  /* Enable Main regulator low voltage */
-  PWR->CR1 |= PWR_CR1_MRUDS;
-}
-
-/**
-  * @brief Disables Main Regulator low voltage mode.
-  * @retval None
-  */
-void HAL_PWREx_DisableMainRegulatorLowVoltage(void)
-{
-  /* Disable Main regulator low voltage */
-  PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_MRUDS);
-}
-
-/**
-  * @brief Enables Low Power Regulator low voltage mode.
-  * @retval None
-  */
-void HAL_PWREx_EnableLowRegulatorLowVoltage(void)
-{
-  /* Enable low power regulator */
-  PWR->CR1 |= PWR_CR1_LPUDS;
-}
-
-/**
-  * @brief Disables Low Power Regulator low voltage mode.
-  * @retval None
-  */
-void HAL_PWREx_DisableLowRegulatorLowVoltage(void)
-{
-  /* Disable low power regulator */
-  PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_LPUDS);
-}
-
-/**
-  * @brief  Activates the Over-Drive mode.
-  * @note   This mode allows the CPU and the core logic to operate at a higher frequency
-  *         than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
-  * @note   It is recommended to enter or exit Over-drive mode when the application is not running
-  *         critical tasks and when the system clock source is either HSI or HSE.
-  *         During the Over-drive switch activation, no peripheral clocks should be enabled.
-  *         The peripheral clocks must be enabled once the Over-drive mode is activated.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)
-{
-  uint32_t tickstart = 0;
-
-  __HAL_RCC_PWR_CLK_ENABLE();
-
-  /* Enable the Over-drive to extend the clock frequency to 216 MHz */
-  __HAL_PWR_OVERDRIVE_ENABLE();
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
-  {
-    if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Enable the Over-drive switch */
-  __HAL_PWR_OVERDRIVESWITCHING_ENABLE();
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
-  {
-    if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deactivates the Over-Drive mode.
-  * @note   This mode allows the CPU and the core logic to operate at a higher frequency
-  *         than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
-  * @note   It is recommended to enter or exit Over-drive mode when the application is not running
-  *         critical tasks and when the system clock source is either HSI or HSE.
-  *         During the Over-drive switch activation, no peripheral clocks should be enabled.
-  *         The peripheral clocks must be enabled once the Over-drive mode is activated.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void)
-{
-  uint32_t tickstart = 0;
-
-  __HAL_RCC_PWR_CLK_ENABLE();
-
-  /* Disable the Over-drive switch */
-  __HAL_PWR_OVERDRIVESWITCHING_DISABLE();
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
-  {
-    if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Disable the Over-drive */
-  __HAL_PWR_OVERDRIVE_DISABLE();
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
-  {
-    if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enters in Under-Drive STOP mode.
-  *
-  * @note    This mode can be selected only when the Under-Drive is already active
-  *
-  * @note    This mode is enabled only with STOP low power mode.
-  *          In this mode, the 1.2V domain is preserved in reduced leakage mode. This
-  *          mode is only available when the main regulator or the low power regulator
-  *          is in low voltage mode
-  *
-  * @note   If the Under-drive mode was enabled, it is automatically disabled after
-  *         exiting Stop mode.
-  *         When the voltage regulator operates in Under-drive mode, an additional
-  *         startup delay is induced when waking up from Stop mode.
-  *
-  * @note   In Stop mode, all I/O pins keep the same state as in Run mode.
-  *
-  * @note   When exiting Stop mode by issuing an interrupt or a wakeup event,
-  *         the HSI RC oscillator is selected as system clock.
-  *
-  * @note   When the voltage regulator operates in low power mode, an additional
-  *         startup delay is incurred when waking up from Stop mode.
-  *         By keeping the internal regulator ON during Stop mode, the consumption
-  *         is higher although the startup time is reduced.
-  *
-  * @param  Regulator: specifies the regulator state in STOP mode.
-  *          This parameter can be one of the following values:
-  *            @arg PWR_MAINREGULATOR_UNDERDRIVE_ON:  Main Regulator in under-drive mode
-  *                 and Flash memory in power-down when the device is in Stop under-drive mode
-  *            @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON:  Low Power Regulator in under-drive mode
-  *                and Flash memory in power-down when the device is in Stop under-drive mode
-  * @param  STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
-  *          This parameter can be one of the following values:
-  *            @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction
-  *            @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
-{
-  uint32_t tempreg = 0;
-  uint32_t tickstart = 0;
-
-  /* Check the parameters */
-  assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator));
-  assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
-
-  /* Enable Power ctrl clock */
-  __HAL_RCC_PWR_CLK_ENABLE();
-  /* Enable the Under-drive Mode ---------------------------------------------*/
-  /* Clear Under-drive flag */
-  __HAL_PWR_CLEAR_ODRUDR_FLAG();
-
-  /* Enable the Under-drive */
-  __HAL_PWR_UNDERDRIVE_ENABLE();
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  /* Wait for UnderDrive mode is ready */
-  while(__HAL_PWR_GET_FLAG(PWR_FLAG_UDRDY))
-  {
-    if((HAL_GetTick() - tickstart ) > PWR_UDERDRIVE_TIMEOUT_VALUE)
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Select the regulator state in STOP mode ---------------------------------*/
-  tempreg = PWR->CR1;
-  /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */
-  tempreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS | PWR_CR1_LPUDS | PWR_CR1_MRUDS);
-
-  /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */
-  tempreg |= Regulator;
-
-  /* Store the new value */
-  PWR->CR1 = tempreg;
-
-  /* Set SLEEPDEEP bit of Cortex System Control Register */
-  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-
-  /* Select STOP mode entry --------------------------------------------------*/
-  if(STOPEntry == PWR_SLEEPENTRY_WFI)
-  {
-    /* Request Wait For Interrupt */
-    __WFI();
-  }
-  else
-  {
-    /* Request Wait For Event */
-    __WFE();
-  }
-  /* Reset SLEEPDEEP bit of Cortex System Control Register */
-  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Returns Voltage Scaling Range.
-  * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1, PWR_REGULATOR_VOLTAGE_SCALE2 or
-  *            PWR_REGULATOR_VOLTAGE_SCALE3)PWR_REGULATOR_VOLTAGE_SCALE1
-  */
-uint32_t HAL_PWREx_GetVoltageRange(void)
-{
-  return  (PWR->CR1 & PWR_CR1_VOS);
-}
-
-/**
-  * @brief Configures the main internal regulator output voltage.
-  * @param  VoltageScaling: specifies the regulator output voltage to achieve
-  *         a tradeoff between performance and power consumption.
-  *          This parameter can be one of the following values:
-  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
-  *                                                typical output voltage at 1.4 V,
-  *                                                system frequency up to 216 MHz.
-  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,
-  *                                                typical output voltage at 1.2 V,
-  *                                                system frequency up to 180 MHz.
-  *            @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 2 mode,
-  *                                                typical output voltage at 1.00 V,
-  *                                                system frequency up to 151 MHz.
-  * @note To update the system clock frequency(SYSCLK):
-  *        - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig().
-  *        - Call the HAL_RCC_OscConfig() to configure the PLL.
-  *        - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale.
-  *        - Set the new system clock frequency using the HAL_RCC_ClockConfig().
-  * @note The scale can be modified only when the HSI or HSE clock source is selected
-  *        as system clock source, otherwise the API returns HAL_ERROR.
-  * @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits
-  *       value in the PWR_CR1 register are not taken in account.
-  * @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2.
-  * @note The new voltage scale is active only when the PLL is ON.
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
-{
-  uint32_t tickstart = 0;
-
-  assert_param(IS_PWR_REGULATOR_VOLTAGE(VoltageScaling));
-
-  /* Enable Power ctrl clock */
-  __HAL_RCC_PWR_CLK_ENABLE();
-
-  /* Check if the PLL is used as system clock or not */
-  if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
-  {
-    /* Disable the main PLL */
-    __HAL_RCC_PLL_DISABLE();
-
-    /* Get Start Tick */
-    tickstart = HAL_GetTick();
-    /* Wait till PLL is disabled */
-    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Set Range */
-    __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);
-
-    /* Enable the main PLL */
-    __HAL_RCC_PLL_ENABLE();
-
-    /* Get Start Tick */
-    tickstart = HAL_GetTick();
-    /* Wait till PLL is ready */
-    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Get Start Tick */
-    tickstart = HAL_GetTick();
-    while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))
-    {
-      if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_PWR_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_rcc.c b/stmhal/hal/f7/src/stm32f7xx_hal_rcc.c
deleted file mode 100644
index 4dd70c7fc5..0000000000
--- a/stmhal/hal/f7/src/stm32f7xx_hal_rcc.c
+++ /dev/null
@@ -1,1119 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_rcc.c
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   RCC HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Reset and Clock Control (RCC) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + Peripheral Control functions
-  *
-  @verbatim
-  ==============================================================================
-                      ##### RCC specific features #####
-  ==============================================================================
-    [..]
-      After reset the device is running from Internal High Speed oscillator
-      (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
-      and I-Cache are disabled, and all peripherals are off except internal
-      SRAM, Flash and JTAG.
-      (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
-          all peripherals mapped on these busses are running at HSI speed.
-      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
-      (+) All GPIOs are in input floating state, except the JTAG pins which
-          are assigned to be used for debug purpose.
-
-    [..]
-      Once the device started from reset, the user application has to:
-      (+) Configure the clock source to be used to drive the System clock
-          (if the application needs higher frequency/performance)
-      (+) Configure the System clock frequency and Flash settings
-      (+) Configure the AHB and APB busses prescalers
-      (+) Enable the clock for the peripheral(s) to be used
-      (+) Configure the clock source(s) for peripherals which clocks are not
-          derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
-
-                      ##### RCC Limitations #####
-  ==============================================================================
-    [..]
-      A delay between an RCC peripheral clock enable and the effective peripheral
-      enabling should be taken into account in order to manage the peripheral read/write
-      from/to registers.
-      (+) This delay depends on the peripheral mapping.
-      (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
-          after the clock enable bit is set on the hardware register
-      (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
-          after the clock enable bit is set on the hardware register
-
-    [..]
-      Implemented Workaround:
-      (+) For AHB & APB peripherals, a dummy read to the peripheral register has been
-          inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup RCC RCC
-  * @brief RCC HAL module driver
-  * @{
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup RCC_Private_Macros RCC Private Macros
-  * @{
-  */
-
-#define MCO1_CLK_ENABLE()   __HAL_RCC_GPIOA_CLK_ENABLE()
-#define MCO1_GPIO_PORT        GPIOA
-#define MCO1_PIN              GPIO_PIN_8
-
-#define MCO2_CLK_ENABLE()   __HAL_RCC_GPIOC_CLK_ENABLE()
-#define MCO2_GPIO_PORT         GPIOC
-#define MCO2_PIN               GPIO_PIN_9
-
-/**
-  * @}
-  */
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup RCC_Private_Variables RCC Private Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup RCC_Exported_Functions RCC Exported Functions
-  * @{
-  */
-
-/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
-  *  @brief    Initialization and Configuration functions
-  *
-  @verbatim
-  ===============================================================================
-##### Initialization and de-initialization functions #####
-  ===============================================================================
-    [..]
-      This section provides functions allowing to configure the internal/external oscillators
-      (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
-      and APB2).
-
-    [..] Internal/external clock and PLL configuration
-      (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
-          the PLL as System clock source.
-
-      (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
-          clock source.
-
-      (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
-          through the PLL as System clock source. Can be used also as RTC clock source.
-
-      (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
-
-      (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
-        (++) The first output is used to generate the high speed system clock (up to 216 MHz)
-        (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
-             the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
-
-      (#) CSS (Clock security system), once enable using the function HAL_RCC_EnableCSS()
-          and if a HSE clock failure occurs(HSE used directly or through PLL as System
-          clock source), the System clock is automatically switched to HSI and an interrupt
-          is generated if enabled. The interrupt is linked to the Cortex-M7 NMI
-          (Non-Maskable Interrupt) exception vector.
-
-      (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
-          clock (through a configurable prescaler) on PA8 pin.
-
-      (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
-          clock (through a configurable prescaler) on PC9 pin.
-
-    [..] System, AHB and APB busses clocks configuration
-      (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
-          HSE and PLL.
-          The AHB clock (HCLK) is derived from System clock through configurable
-          prescaler and used to clock the CPU, memory and peripherals mapped
-          on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
-          from AHB clock through configurable prescalers and used to clock
-          the peripherals mapped on these busses. You can use
-          "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
-
-      -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
-          (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
-              from an external clock mapped on the I2S_CKIN pin.
-              You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
-          (+@)  SAI: the SAI clock can be derived either from a specific PLL (PLLI2S) or (PLLSAI) or
-              from an external clock mapped on the I2S_CKIN pin.
-               You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
-          (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
-              divided by 2 to 31. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE()
-              macros to configure this clock.
-          (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
-              to work correctly, while the SDIO require a frequency equal or lower than
-              to 48. This clock is derived of the main PLL through PLLQ divider.
-          (+@) IWDG clock which is always the LSI clock.
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Resets the RCC clock configuration to the default reset state.
-  * @note   The default reset state of the clock configuration is given below:
-  *            - HSI ON and used as system clock source
-  *            - HSE, PLL and PLLI2S OFF
-  *            - AHB, APB1 and APB2 prescaler set to 1.
-  *            - CSS, MCO1 and MCO2 OFF
-  *            - All interrupts disabled
-  * @note   This function doesn't modify the configuration of the
-  *            - Peripheral clocks
-  *            - LSI, LSE and RTC clocks
-  * @retval None
-  */
-void HAL_RCC_DeInit(void)
-{
-  /* Set HSION bit */
-  SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4);
-
-  /* Reset CFGR register */
-  CLEAR_REG(RCC->CFGR);
-
-  /* Reset HSEON, CSSON, PLLON, PLLI2S */
-  CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON| RCC_CR_PLLI2SON);
-
-  /* Reset PLLCFGR register */
-  CLEAR_REG(RCC->PLLCFGR);
-  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 | ((uint32_t)0x20000000U));
-
-  /* Reset PLLI2SCFGR register */
-  CLEAR_REG(RCC->PLLI2SCFGR);
-  SET_BIT(RCC->PLLI2SCFGR,  RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1);
-
-  /* Reset HSEBYP bit */
-  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
-
-  /* Disable all interrupts */
-  CLEAR_REG(RCC->CIR);
-
-  /* Update the SystemCoreClock global variable */
-  SystemCoreClock = HSI_VALUE;
-}
-
-/**
-  * @brief  Initializes the RCC Oscillators according to the specified parameters in the
-  *         RCC_OscInitTypeDef.
-  * @param  RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
-  *         contains the configuration information for the RCC Oscillators.
-  * @note   The PLL is not disabled when used as system clock.
-  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
-  *         supported by this function. User should request a transition to LSE Off
-  *         first and then LSE On or LSE Bypass.
-  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
-  *         supported by this function. User should request a transition to HSE Off
-  *         first and then HSE On or HSE Bypass.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
-{
-  uint32_t tickstart = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
-
-  /*------------------------------- HSE Configuration ------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
-    /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */
-    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
-       || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
-    {
-	  if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
-      {
-        return HAL_ERROR;
-      }
-    }
-    else
-    {
-      /* Set the new HSE configuration ---------------------------------------*/
-      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
-
-      /* Check the HSE State */
-      if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
-      {
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-
-        /* Wait till HSE is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-      else
-      {
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-
-        /* Wait till HSE is bypassed or disabled */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
-        {
-           if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }
-  }
-  /*----------------------------- HSI Configuration --------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
-    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
-
-    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
-    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
-       || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
-    {
-      /* When HSI is used as system clock it will not disabled */
-      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
-      {
-        return HAL_ERROR;
-      }
-      /* Otherwise, just the calibration is allowed */
-      else
-      {
-        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
-        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
-      }
-    }
-    else
-    {
-      /* Check the HSI State */
-      if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
-      {
-        /* Enable the Internal High Speed oscillator (HSI). */
-        __HAL_RCC_HSI_ENABLE();
-
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-
-        /* Wait till HSI is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-
-        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
-        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
-      }
-      else
-      {
-        /* Disable the Internal High Speed oscillator (HSI). */
-        __HAL_RCC_HSI_DISABLE();
-
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-
-        /* Wait till HSI is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }
-  }
-  /*------------------------------ LSI Configuration -------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
-
-    /* Check the LSI State */
-    if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
-    {
-      /* Enable the Internal Low Speed oscillator (LSI). */
-      __HAL_RCC_LSI_ENABLE();
-
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
-
-      /* Wait till LSI is ready */
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
-      {
-        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-    else
-    {
-      /* Disable the Internal Low Speed oscillator (LSI). */
-      __HAL_RCC_LSI_DISABLE();
-
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
-
-      /* Wait till LSI is ready */
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
-      {
-        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  /*------------------------------ LSE Configuration -------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
-
-    /* Enable Power Clock*/
-    __HAL_RCC_PWR_CLK_ENABLE();
-
-    /* Enable write access to Backup domain */
-    PWR->CR1 |= PWR_CR1_DBP;
-
-    /* Wait for Backup domain Write protection disable */
-    tickstart = HAL_GetTick();
-
-    while((PWR->CR1 & PWR_CR1_DBP) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Set the new LSE configuration -----------------------------------------*/
-    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
-    /* Check the LSE State */
-    if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
-    {
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
-
-      /* Wait till LSE is ready */
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
-      {
-        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-    else
-    {
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
-
-      /* Wait till LSE is ready */
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
-      {
-        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  /*-------------------------------- PLL Configuration -----------------------*/
-  /* Check the parameters */
-  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
-  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
-  {
-    /* Check if the PLL is used as system clock or not */
-    if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
-    {
-      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
-      {
-        /* Check the parameters */
-        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
-        assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
-        assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
-        assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
-        assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
-#if defined (RCC_PLLCFGR_PLLR)
-        assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
-#endif
-
-        /* Disable the main PLL. */
-        __HAL_RCC_PLL_DISABLE();
-
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-
-        /* Wait till PLL is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-
-        /* Configure the main PLL clock source, multiplication and division factors. */
-#if defined (RCC_PLLCFGR_PLLR)
-        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
-                             RCC_OscInitStruct->PLL.PLLM,
-                             RCC_OscInitStruct->PLL.PLLN,
-                             RCC_OscInitStruct->PLL.PLLP,
-                             RCC_OscInitStruct->PLL.PLLQ,
-                             RCC_OscInitStruct->PLL.PLLR);
-#else
-        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
-                             RCC_OscInitStruct->PLL.PLLM,
-                             RCC_OscInitStruct->PLL.PLLN,
-                             RCC_OscInitStruct->PLL.PLLP,
-                             RCC_OscInitStruct->PLL.PLLQ);
-#endif
-
-        /* Enable the main PLL. */
-        __HAL_RCC_PLL_ENABLE();
-
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-
-        /* Wait till PLL is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-      else
-      {
-        /* Disable the main PLL. */
-        __HAL_RCC_PLL_DISABLE();
-
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-
-        /* Wait till PLL is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }
-    else
-    {
-      return HAL_ERROR;
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the CPU, AHB and APB busses clocks according to the specified
-  *         parameters in the RCC_ClkInitStruct.
-  * @param  RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
-  *         contains the configuration information for the RCC peripheral.
-  * @param  FLatency: FLASH Latency, this parameter depend on device selected
-  *
-  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
-  *         and updated by HAL_RCC_GetHCLKFreq() function called within this function
-  *
-  * @note   The HSI is used (enabled by hardware) as system clock source after
-  *         startup from Reset, wake-up from STOP and STANDBY mode, or in case
-  *         of failure of the HSE used directly or indirectly as system clock
-  *         (if the Clock Security System CSS is enabled).
-  *
-  * @note   A switch from one clock source to another occurs only if the target
-  *         clock source is ready (clock stable after startup delay or PLL locked).
-  *         If a clock source which is not yet ready is selected, the switch will
-  *         occur when the clock source will be ready.
-  *         You can use HAL_RCC_GetClockConfig() function to know which clock is
-  *         currently used as system clock source.
-  * @note   Depending on the device voltage range, the software has to set correctly
-  *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
-  *         (for more details refer to section above "Initialization/de-initialization functions")
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
-{
-  uint32_t tickstart = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
-  assert_param(IS_FLASH_LATENCY(FLatency));
-
-  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
-  must be correctly programmed according to the frequency of the CPU clock
-  (HCLK) and the supply voltage of the device. */
-
-  /* Increasing the CPU frequency */
-  if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
-  {
-    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
-    __HAL_FLASH_SET_LATENCY(FLatency);
-
-    /* Check that the new number of wait states is taken into account to access the Flash
-    memory by reading the FLASH_ACR register */
-    if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
-    {
-      return HAL_ERROR;
-    }
-  }
-
-  /*-------------------------- HCLK Configuration --------------------------*/
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
-  {
-    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
-  }
-
-  /*------------------------- SYSCLK Configuration ---------------------------*/
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
-  {
-    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
-
-    /* HSE is selected as System Clock Source */
-    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
-    {
-      /* Check the HSE ready flag */
-      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
-      {
-        return HAL_ERROR;
-      }
-    }
-    /* PLL is selected as System Clock Source */
-    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
-    {
-      /* Check the PLL ready flag */
-      if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
-      {
-        return HAL_ERROR;
-      }
-    }
-    /* HSI is selected as System Clock Source */
-    else
-    {
-      /* Check the HSI ready flag */
-      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
-      {
-        return HAL_ERROR;
-      }
-    }
-
-    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
-    /* Get Start Tick*/
-    tickstart = HAL_GetTick();
-
-    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
-    {
-      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
-      {
-        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
-    {
-      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
-      {
-        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-    else
-    {
-      while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
-      {
-        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-
-  /* Decreasing the number of wait states because of lower CPU frequency */
-  if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
-  {
-    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
-    __HAL_FLASH_SET_LATENCY(FLatency);
-
-    /* Check that the new number of wait states is taken into account to access the Flash
-    memory by reading the FLASH_ACR register */
-    if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
-    {
-      return HAL_ERROR;
-    }
-  }
-
-  /*-------------------------- PCLK1 Configuration ---------------------------*/
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
-  {
-    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
-  }
-
-  /*-------------------------- PCLK2 Configuration ---------------------------*/
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
-  {
-    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
-  }
-
-  /* Update the SystemCoreClock global variable */
-  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
-
-  /* Configure the source of time base considering new system clocks settings*/
-  HAL_InitTick (TICK_INT_PRIORITY);
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
-  *  @brief   RCC clocks control functions
-  *
-  @verbatim
-  ===============================================================================
-                  ##### Peripheral Control functions #####
-  ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to control the RCC Clocks
-    frequencies.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
-  * @note   PA8/PC9 should be configured in alternate function mode.
-  * @param  RCC_MCOx: specifies the output direction for the clock source.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
-  *            @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
-  * @param  RCC_MCOSource: specifies the clock source to output.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
-  *            @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
-  *            @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
-  *            @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
-  *            @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
-  *            @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source
-  *            @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
-  *            @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
-  * @param  RCC_MCODiv: specifies the MCOx prescaler.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_MCODIV_1: no division applied to MCOx clock
-  *            @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
-  *            @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
-  *            @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
-  *            @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
-  * @retval None
-  */
-void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
-{
-  GPIO_InitTypeDef GPIO_InitStruct;
-  /* Check the parameters */
-  assert_param(IS_RCC_MCO(RCC_MCOx));
-  assert_param(IS_RCC_MCODIV(RCC_MCODiv));
-  /* RCC_MCO1 */
-  if(RCC_MCOx == RCC_MCO1)
-  {
-    assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
-
-    /* MCO1 Clock Enable */
-    MCO1_CLK_ENABLE();
-
-    /* Configure the MCO1 pin in alternate function mode */
-    GPIO_InitStruct.Pin = MCO1_PIN;
-    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-    GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
-    GPIO_InitStruct.Pull = GPIO_NOPULL;
-    GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
-    HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
-
-    /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
-    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
-  }
-  else
-  {
-    assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
-
-    /* MCO2 Clock Enable */
-    MCO2_CLK_ENABLE();
-
-    /* Configure the MCO2 pin in alternate function mode */
-    GPIO_InitStruct.Pin = MCO2_PIN;
-    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-    GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
-    GPIO_InitStruct.Pull = GPIO_NOPULL;
-    GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
-    HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
-
-    /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */
-    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3)));
-  }
-}
-
-/**
-  * @brief  Enables the Clock Security System.
-  * @note   If a failure is detected on the HSE oscillator clock, this oscillator
-  *         is automatically disabled and an interrupt is generated to inform the
-  *         software about the failure (Clock Security System Interrupt, CSSI),
-  *         allowing the MCU to perform rescue operations. The CSSI is linked to
-  *         the Cortex-M7 NMI (Non-Maskable Interrupt) exception vector.
-  * @retval None
-  */
-void HAL_RCC_EnableCSS(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_CSSON);
-}
-
-/**
-  * @brief  Disables the Clock Security System.
-  * @retval None
-  */
-void HAL_RCC_DisableCSS(void)
-{
-  CLEAR_BIT(RCC->CR, RCC_CR_CSSON);
-}
-
-/**
-  * @brief  Returns the SYSCLK frequency
-  *
-  * @note   The system frequency computed by this function is not the real
-  *         frequency in the chip. It is calculated based on the predefined
-  *         constant and the selected clock source:
-  * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
-  * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
-  * @note     If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
-  *           or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  * @note     (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
-  *               16 MHz) but the real value may vary depending on the variations
-  *               in voltage and temperature.
-  * @note     (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
-  *                25 MHz), user has to ensure that HSE_VALUE is same as the real
-  *                frequency of the crystal used. Otherwise, this function may
-  *                have wrong result.
-  *
-  * @note   The result of this function could be not correct when using fractional
-  *         value for HSE crystal.
-  *
-  * @note   This function can be used by the user application to compute the
-  *         baudrate for the communication peripherals or configure other parameters.
-  *
-  * @note   Each time SYSCLK changes, this function must be called to update the
-  *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
-  *
-  *
-  * @retval SYSCLK frequency
-  */
-uint32_t HAL_RCC_GetSysClockFreq(void)
-{
-  uint32_t pllm = 0, pllvco = 0, pllp = 0;
-  uint32_t sysclockfreq = 0;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  switch (RCC->CFGR & RCC_CFGR_SWS)
-  {
-    case RCC_SYSCLKSOURCE_STATUS_HSI:  /* HSI used as system clock source */
-    {
-      sysclockfreq = HSI_VALUE;
-       break;
-    }
-    case RCC_SYSCLKSOURCE_STATUS_HSE:  /* HSE used as system clock  source */
-    {
-      sysclockfreq = HSE_VALUE;
-      break;
-    }
-    case RCC_SYSCLKSOURCE_STATUS_PLLCLK:  /* PLL used as system clock  source */
-    {
-      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
-      SYSCLK = PLL_VCO / PLLP */
-      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
-      if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)
-      {
-        /* HSE used as PLL clock source */
-        //pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
-        // dpgeorge: Adjust the way the arithmetic is done so it retains
-        // precision for the case that pllm doesn't evenly divide HSE_VALUE.
-        // Must be sure not to overflow, so divide by 4 first.  HSE_VALUE
-        // should be a multiple of 4 (being a multiple of 100 is enough).
-        pllvco = ((HSE_VALUE / 4) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))) / pllm * 4;
-      }
-      else
-      {
-        /* HSI used as PLL clock source */
-        pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
-      }
-      pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1 ) *2);
-
-      sysclockfreq = pllvco/pllp;
-      break;
-    }
-    default:
-    {
-      sysclockfreq = HSI_VALUE;
-      break;
-    }
-  }
-  return sysclockfreq;
-}
-
-/**
-  * @brief  Returns the HCLK frequency
-  * @note   Each time HCLK changes, this function must be called to update the
-  *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.
-  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
-  * @retval HCLK frequency
-  */
-uint32_t HAL_RCC_GetHCLKFreq(void)
-{
-  return SystemCoreClock;
-}
-
-/**
-  * @brief  Returns the PCLK1 frequency
-  * @note   Each time PCLK1 changes, this function must be called to update the
-  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
-  * @retval PCLK1 frequency
-  */
-uint32_t HAL_RCC_GetPCLK1Freq(void)
-{
-  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
-  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
-}
-
-/**
-  * @brief  Returns the PCLK2 frequency
-  * @note   Each time PCLK2 changes, this function must be called to update the
-  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
-  * @retval PCLK2 frequency
-  */
-uint32_t HAL_RCC_GetPCLK2Freq(void)
-{
-  /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
-  return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
-}
-
-/**
-  * @brief  Configures the RCC_OscInitStruct according to the internal
-  * RCC configuration registers.
-  * @param  RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
-  * will be configured.
-  * @retval None
-  */
-void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
-{
-  /* Set all possible values for the Oscillator type parameter ---------------*/
-  RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
-
-  /* Get the HSE configuration -----------------------------------------------*/
-  if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
-  {
-    RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
-  }
-  else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
-  {
-    RCC_OscInitStruct->HSEState = RCC_HSE_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
-  }
-
-  /* Get the HSI configuration -----------------------------------------------*/
-  if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
-  {
-    RCC_OscInitStruct->HSIState = RCC_HSI_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
-  }
-
-  RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
-
-  /* Get the LSE configuration -----------------------------------------------*/
-  if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
-  {
-    RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
-  }
-  else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
-  {
-    RCC_OscInitStruct->LSEState = RCC_LSE_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
-  }
-
-  /* Get the LSI configuration -----------------------------------------------*/
-  if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
-  {
-    RCC_OscInitStruct->LSIState = RCC_LSI_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
-  }
-
-  /* Get the PLL configuration -----------------------------------------------*/
-  if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
-  {
-    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
-  }
-  RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
-  RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
-  RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
-  RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1) >> POSITION_VAL(RCC_PLLCFGR_PLLP));
-  RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ));
-}
-
-/**
-  * @brief  Configures the RCC_ClkInitStruct according to the internal
-  * RCC configuration registers.
-  * @param  RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
-  * will be configured.
-  * @param  pFLatency: Pointer on the Flash Latency.
-  * @retval None
-  */
-void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
-{
-  /* Set all possible values for the Clock type parameter --------------------*/
-  RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
-
-  /* Get the SYSCLK configuration --------------------------------------------*/
-  RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
-
-  /* Get the HCLK configuration ----------------------------------------------*/
-  RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
-
-  /* Get the APB1 configuration ----------------------------------------------*/
-  RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
-
-  /* Get the APB2 configuration ----------------------------------------------*/
-  RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
-
-  /* Get the Flash Wait State (Latency) configuration ------------------------*/
-  *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
-}
-
-/**
-  * @brief This function handles the RCC CSS interrupt request.
-  * @note This API should be called under the NMI_Handler().
-  * @retval None
-  */
-void HAL_RCC_NMI_IRQHandler(void)
-{
-  /* Check RCC CSSF flag  */
-  if(__HAL_RCC_GET_IT(RCC_IT_CSS))
-  {
-    /* RCC Clock Security System interrupt user callback */
-    HAL_RCC_CSSCallback();
-
-    /* Clear RCC CSS pending bit */
-    __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
-  }
-}
-
-/**
-  * @brief  RCC Clock Security System interrupt callback
-  * @retval None
-  */
-__weak void HAL_RCC_CSSCallback(void)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_RCC_CSSCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_RCC_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_rcc_ex.c b/stmhal/hal/f7/src/stm32f7xx_hal_rcc_ex.c
deleted file mode 100644
index 0cc2395f41..0000000000
--- a/stmhal/hal/f7/src/stm32f7xx_hal_rcc_ex.c
+++ /dev/null
@@ -1,1026 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_rcc_ex.c
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   Extension RCC HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities RCC extension peripheral:
-  *           + Extended Peripheral Control functions
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup RCCEx RCCEx
-  * @brief RCCEx HAL module driver
-  * @{
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup RCCEx_Private_Defines RCCEx Private Defines
-  * @{
-  */
-
-#define PLLI2S_TIMEOUT_VALUE    100 /* Timeout value fixed to 100 ms  */
-#define PLLSAI_TIMEOUT_VALUE    100 /* Timeout value fixed to 100 ms  */
-
-/**
-  * @}
-  */
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
- * @{
- */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
- * @{
- */
-
-/**
-  * @}
-  */
-
-
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
-  * @{
-  */
-
-/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
- *  @brief  Extended Peripheral Control functions
- *
-@verbatim
- ===============================================================================
-                ##### Extended Peripheral Control functions  #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to control the RCC Clocks
-    frequencies.
-    [..]
-    (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
-        select the RTC clock source; in this case the Backup domain will be reset in
-        order to modify the RTC Clock source, as consequence RTC registers (including
-        the backup registers) and RCC_BDCR register will be set to their reset values.
-
-@endverbatim
-  * @{
-  */
-#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || \
-    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-/**
-  * @brief  Initializes the RCC extended peripherals clocks according to the specified
-  *         parameters in the RCC_PeriphCLKInitTypeDef.
-  * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
-  *         contains the configuration information for the Extended Peripherals
-  *         clocks(I2S, SAI, LTDC, RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...).
-  *
-  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
-  *         the RTC clock source; in this case the Backup domain will be reset in
-  *         order to modify the RTC Clock source, as consequence RTC registers (including
-  *         the backup registers) are set to their reset values.
-  *
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
-{
-  uint32_t tickstart = 0;
-  uint32_t tmpreg0 = 0;
-  uint32_t tmpreg1 = 0;
-  uint32_t plli2sused = 0;
-  uint32_t pllsaiused = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
-
-  /*----------------------------------- I2S configuration ----------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
-
-    /* Configure I2S Clock source */
-    __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
-
-    /* Enable the PLLI2S when it's used as clock source for I2S */
-    if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)
-    {
-      plli2sused = 1;
-    }
-  }
-
-  /*------------------------------------ SAI1 configuration --------------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
-
-    /* Configure SAI1 Clock source */
-    __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
-    /* Enable the PLLI2S when it's used as clock source for SAI */
-    if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
-    {
-      plli2sused = 1;
-    }
-    /* Enable the PLLSAI when it's used as clock source for SAI */
-    if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
-    {
-      pllsaiused = 1;
-    }
-  }
-
-  /*------------------------------------ SAI2 configuration --------------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
-
-    /* Configure SAI2 Clock source */
-    __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
-
-    /* Enable the PLLI2S when it's used as clock source for SAI */
-    if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
-    {
-      plli2sused = 1;
-    }
-    /* Enable the PLLSAI when it's used as clock source for SAI */
-    if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
-    {
-      pllsaiused = 1;
-    }
-  }
-
-  /*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
-  {
-      plli2sused = 1;
-  }
-
-  /*------------------------------------ RTC configuration --------------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
-  {
-    /* Check for RTC Parameters used to output RTCCLK */
-    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
-
-    /* Enable Power Clock*/
-    __HAL_RCC_PWR_CLK_ENABLE();
-
-    /* Enable write access to Backup domain */
-    PWR->CR1 |= PWR_CR1_DBP;
-
-    /* Get Start Tick*/
-    tickstart = HAL_GetTick();
-
-    /* Wait for Backup domain Write protection disable */
-    while((PWR->CR1 & PWR_CR1_DBP) == RESET)
-    {
-      if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Reset the Backup domain only if the RTC Clock source selection is modified */
-    tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL);
-
-    if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
-    {
-      /* Store the content of BDCR register before the reset of Backup Domain */
-      tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
-
-      /* RTC Clock selection can be changed only if the Backup Domain is reset */
-      __HAL_RCC_BACKUPRESET_FORCE();
-      __HAL_RCC_BACKUPRESET_RELEASE();
-
-      /* Restore the Content of BDCR register */
-      RCC->BDCR = tmpreg0;
-
-      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
-      if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
-      {
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-
-        /* Wait till LSE is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }
-    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
-  }
-
-  /*------------------------------------ TIM configuration --------------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
-
-    /* Configure Timer Prescaler */
-    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
-  }
-
-  /*-------------------------------------- I2C1 Configuration -----------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
-
-    /* Configure the I2C1 clock source */
-    __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
-  }
-
-  /*-------------------------------------- I2C2 Configuration -----------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
-
-    /* Configure the I2C2 clock source */
-    __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
-  }
-
-  /*-------------------------------------- I2C3 Configuration -----------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
-
-    /* Configure the I2C3 clock source */
-    __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
-  }
-
-  /*-------------------------------------- I2C4 Configuration -----------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
-
-    /* Configure the I2C4 clock source */
-    __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
-  }
-
-  /*-------------------------------------- USART1 Configuration -----------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
-
-    /* Configure the USART1 clock source */
-    __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
-  }
-
-  /*-------------------------------------- USART2 Configuration -----------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
-
-    /* Configure the USART2 clock source */
-    __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
-  }
-
-  /*-------------------------------------- USART3 Configuration -----------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
-
-    /* Configure the USART3 clock source */
-    __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
-  }
-
-  /*-------------------------------------- UART4 Configuration -----------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
-
-    /* Configure the UART4 clock source */
-    __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
-  }
-
-  /*-------------------------------------- UART5 Configuration -----------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
-
-    /* Configure the UART5 clock source */
-    __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
-  }
-
-  /*-------------------------------------- USART6 Configuration -----------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));
-
-    /* Configure the USART6 clock source */
-    __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);
-  }
-
-  /*-------------------------------------- UART7 Configuration -----------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection));
-
-    /* Configure the UART7 clock source */
-    __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection);
-  }
-
-  /*-------------------------------------- UART8 Configuration -----------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection));
-
-    /* Configure the UART8 clock source */
-    __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection);
-  }
-
-  /*--------------------------------------- CEC Configuration -----------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
-
-    /* Configure the CEC clock source */
-    __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
-  }
-
-  /*-------------------------------------- CK48 Configuration -----------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection));
-
-    /* Configure the CLK48 source */
-    __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
-
-    /* Enable the PLLSAI when it's used as clock source for CK48 */
-    if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)
-    {
-      pllsaiused = 1;
-    }
-  }
-
-  /*-------------------------------------- LTDC Configuration -----------------------------------*/
-#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
-  {
-    pllsaiused = 1;
-  }
-#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
-  /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
-
-    /* Configure the LTPIM1 clock source */
-    __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
-   }
-
-  /*------------------------------------- SDMMC1 Configuration ------------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
-
-    /* Configure the SDMMC1 clock source */
-    __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
-  }
-
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-  /*------------------------------------- SDMMC2 Configuration ------------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection));
-
-    /* Configure the SDMMC2 clock source */
-    __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection);
-  }
-
-  /*------------------------------------- DFSDM1 Configuration -------------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
-
-    /* Configure the DFSDM1 interface clock source */
-    __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
-  }
-
-  /*------------------------------------- DFSDM AUDIO Configuration -------------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection));
-
-    /* Configure the DFSDM interface clock source */
-    __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection);
-  }
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
-  /*-------------------------------------- PLLI2S Configuration ---------------------------------*/
-  /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */
-  if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
-  {
-    /* Disable the PLLI2S */
-    __HAL_RCC_PLLI2S_DISABLE();
-
-    /* Get Start Tick*/
-    tickstart = HAL_GetTick();
-
-    /* Wait till PLLI2S is disabled */
-    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
-    {
-      if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
-      {
-        /* return in case of Timeout detected */
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* check for common PLLI2S Parameters */
-    assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
-
-    /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/
-    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)))
-    {
-      /* check for Parameters */
-      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
-
-      /* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
-      tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP));
-      tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
-      /* Configure the PLLI2S division factors */
-      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
-      /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
-      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR);
-    }
-
-    /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/
-    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
-       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
-    {
-      /* Check for PLLI2S Parameters */
-      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
-      /* Check for PLLI2S/DIVQ parameters */
-      assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
-
-      /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */
-      tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP));
-      tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
-      /* Configure the PLLI2S division factors */
-      /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */
-      /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
-      /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
-      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1);
-
-      /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
-      __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
-    }
-
-    /*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/
-    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
-    {
-      /* check for Parameters */
-      assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
-
-     /* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */
-      tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
-      tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
-      /* Configure the PLLI2S division factors */
-      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
-      /* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
-      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1);
-    }
-
-    /*----------------- In Case of PLLI2S is just selected  -----------------*/
-    if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
-    {
-      /* Check for Parameters */
-      assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
-      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
-      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
-
-      /* Configure the PLLI2S division factors */
-      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */
-      /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
-      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
-    }
-
-    /* Enable the PLLI2S */
-    __HAL_RCC_PLLI2S_ENABLE();
-
-    /* Get Start Tick*/
-    tickstart = HAL_GetTick();
-
-    /* Wait till PLLI2S is ready */
-    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
-    {
-      if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
-      {
-        /* return in case of Timeout detected */
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /*-------------------------------------- PLLSAI Configuration ---------------------------------*/
-  /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */
-  if(pllsaiused == 1)
-  {
-    /* Disable PLLSAI Clock */
-    __HAL_RCC_PLLSAI_DISABLE();
-
-    /* Get Start Tick*/
-    tickstart = HAL_GetTick();
-
-    /* Wait till PLLSAI is disabled */
-    while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
-    {
-      if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
-      {
-        /* return in case of Timeout detected */
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Check the PLLSAI division factors */
-    assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
-
-    /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/
-    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
-       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
-    {
-      /* check for PLLSAIQ Parameter */
-      assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
-      /* check for PLLSAI/DIVQ Parameter */
-      assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
-
-      /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
-      tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP));
-      tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
-      /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
-      /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
-      /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
-      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
-
-      /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
-      __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
-    }
-
-    /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/
-    /* In Case of PLLI2S is selected as source clock for CK48 */
-    if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP))
-    {
-      /* check for Parameters */
-      assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
-      /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */
-      tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
-      tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
-
-      /* Configure the PLLSAI division factors */
-      /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */
-      /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
-      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1);
-    }
-
-#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-    /*---------------------------- LTDC configuration -------------------------------*/
-    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
-    {
-      assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
-      assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
-
-      /* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */
-      tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
-      tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP));
-
-      /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
-      /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
-      /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
-      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR);
-
-      /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
-      __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
-    }
-#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
-    /* Enable PLLSAI Clock */
-    __HAL_RCC_PLLSAI_ENABLE();
-
-    /* Get Start Tick*/
-    tickstart = HAL_GetTick();
-
-    /* Wait till PLLSAI is ready */
-    while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
-    {
-      if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
-      {
-        /* return in case of Timeout detected */
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Get the RCC_PeriphCLKInitTypeDef according to the internal
-  *         RCC configuration registers.
-  * @param  PeriphClkInit: pointer to the configured RCC_PeriphCLKInitTypeDef structure
-  * @retval None
-  */
-void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
-{
-  uint32_t tempreg = 0;
-
-  /* Set all possible values for the extended clock type parameter------------*/
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S      | RCC_PERIPHCLK_LPTIM1   |\
-                                        RCC_PERIPHCLK_SAI1     | RCC_PERIPHCLK_SAI2     |\
-                                        RCC_PERIPHCLK_TIM      | RCC_PERIPHCLK_RTC      |\
-                                        RCC_PERIPHCLK_CEC      | RCC_PERIPHCLK_I2C4     |\
-                                        RCC_PERIPHCLK_I2C1     | RCC_PERIPHCLK_I2C2     |\
-                                        RCC_PERIPHCLK_I2C3     | RCC_PERIPHCLK_USART1   |\
-                                        RCC_PERIPHCLK_USART2   | RCC_PERIPHCLK_USART3   |\
-                                        RCC_PERIPHCLK_UART4    | RCC_PERIPHCLK_UART5    |\
-                                        RCC_PERIPHCLK_USART6   | RCC_PERIPHCLK_UART7    |\
-                                        RCC_PERIPHCLK_UART8    | RCC_PERIPHCLK_SDMMC1   |\
-                                        RCC_PERIPHCLK_CLK48    | RCC_PERIPHCLK_SDMMC2   |\
-                                        RCC_PERIPHCLK_DFSDM1   | RCC_PERIPHCLK_DFSDM1_AUDIO;
-#else
-  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S      | RCC_PERIPHCLK_LPTIM1   |\
-                                        RCC_PERIPHCLK_SAI1     | RCC_PERIPHCLK_SAI2     |\
-                                        RCC_PERIPHCLK_TIM      | RCC_PERIPHCLK_RTC      |\
-                                        RCC_PERIPHCLK_CEC      | RCC_PERIPHCLK_I2C4     |\
-                                        RCC_PERIPHCLK_I2C1     | RCC_PERIPHCLK_I2C2     |\
-                                        RCC_PERIPHCLK_I2C3     | RCC_PERIPHCLK_USART1   |\
-                                        RCC_PERIPHCLK_USART2   | RCC_PERIPHCLK_USART3   |\
-                                        RCC_PERIPHCLK_UART4    | RCC_PERIPHCLK_UART5    |\
-                                        RCC_PERIPHCLK_USART6   | RCC_PERIPHCLK_UART7    |\
-                                        RCC_PERIPHCLK_UART8    | RCC_PERIPHCLK_SDMMC1   |\
-                                        RCC_PERIPHCLK_CLK48;
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
-  /* Get the PLLI2S Clock configuration -----------------------------------------------*/
-  PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
-  PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP));
-  PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
-  PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
-
-  /* Get the PLLSAI Clock configuration -----------------------------------------------*/
-  PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
-  PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP));
-  PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
-  PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
-
-  /* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/
-  PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR1_PLLI2SDIVQ));
-  PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR1_PLLSAIDIVQ));
-  PeriphClkInit->PLLSAIDivR = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVR) >> POSITION_VAL(RCC_DCKCFGR1_PLLSAIDIVR));
-
-  /* Get the SAI1 clock configuration ----------------------------------------------*/
-  PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
-
-  /* Get the SAI2 clock configuration ----------------------------------------------*/
-  PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
-
-  /* Get the I2S clock configuration ------------------------------------------*/
-  PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2SCLKSOURCE();
-
-  /* Get the I2C1 clock configuration ------------------------------------------*/
-  PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
-
-  /* Get the I2C2 clock configuration ------------------------------------------*/
-  PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();
-
-  /* Get the I2C3 clock configuration ------------------------------------------*/
-  PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
-
-  /* Get the I2C4 clock configuration ------------------------------------------*/
-  PeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE();
-
-  /* Get the USART1 clock configuration ------------------------------------------*/
-  PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
-
-  /* Get the USART2 clock configuration ------------------------------------------*/
-  PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
-
-  /* Get the USART3 clock configuration ------------------------------------------*/
-  PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
-
-  /* Get the UART4 clock configuration ------------------------------------------*/
-  PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();
-
-  /* Get the UART5 clock configuration ------------------------------------------*/
-  PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();
-
-  /* Get the USART6 clock configuration ------------------------------------------*/
-  PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE();
-
-  /* Get the UART7 clock configuration ------------------------------------------*/
-  PeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE();
-
-  /* Get the UART8 clock configuration ------------------------------------------*/
-  PeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE();
-
-  /* Get the LPTIM1 clock configuration ------------------------------------------*/
-  PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
-
-  /* Get the CEC clock configuration -----------------------------------------------*/
-  PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
-
-  /* Get the CK48 clock configuration -----------------------------------------------*/
-  PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
-
-  /* Get the SDMMC1 clock configuration -----------------------------------------------*/
-  PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE();
-
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-  /* Get the SDMMC2 clock configuration -----------------------------------------------*/
-  PeriphClkInit->Sdmmc2ClockSelection = __HAL_RCC_GET_SDMMC2_SOURCE();
-
-  /* Get the DFSDM clock configuration -----------------------------------------------*/
-  PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE();
-
-  /* Get the DFSDM AUDIO clock configuration -----------------------------------------------*/
-  PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE();
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
-  /* Get the RTC Clock configuration -----------------------------------------------*/
-  tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
-  PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
-
-  /* Get the TIM Prescaler configuration --------------------------------------------*/
-  if ((RCC->DCKCFGR1 & RCC_DCKCFGR1_TIMPRE) == RESET)
-  {
-    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
-  }
-  else
-  {
-    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
-  }
-}
-#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
-/**
-  * @brief  Return the peripheral clock frequency for a given peripheral(SAI..)
-  * @note   Return 0 if peripheral clock identifier not managed by this API
-  * @param  PeriphClk: Peripheral clock identifier
-  *         This parameter can be one of the following values:
-  *            @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock
-  *            @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock
-  * @retval Frequency in KHz
-  */
-uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
-{
-  uint32_t tmpreg = 0;
-  /* This variable is used to store the SAI clock frequency (value in Hz) */
-  uint32_t frequency = 0;
-  /* This variable is used to store the VCO Input (value in Hz) */
-  uint32_t vcoinput = 0;
-  /* This variable is used to store the SAI clock source */
-  uint32_t saiclocksource = 0;
-
-  if (PeriphClk == RCC_PERIPHCLK_SAI1)
-  {
-    saiclocksource = RCC->DCKCFGR1;
-    saiclocksource &= RCC_DCKCFGR1_SAI1SEL;
-    switch (saiclocksource)
-    {
-    case 0: /* PLLSAI is the clock source for SAI1 */
-      {
-        /* Configure the PLLSAI division factor */
-        /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
-        if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
-        {
-          /* In Case the PLL Source is HSI (Internal Clock) */
-          vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
-        }
-        else
-        {
-          /* In Case the PLL Source is HSE (External Clock) */
-          vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
-        }
-        /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
-        /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
-        tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24;
-        frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg);
-
-        /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
-        tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1);
-        frequency = frequency/(tmpreg);
-        break;
-      }
-    case RCC_DCKCFGR1_SAI1SEL_0: /* PLLI2S is the clock source for SAI1 */
-      {
-        /* Configure the PLLI2S division factor */
-        /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */
-        if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
-        {
-          /* In Case the PLL Source is HSI (Internal Clock) */
-          vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
-        }
-        else
-        {
-          /* In Case the PLL Source is HSE (External Clock) */
-          vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
-        }
-
-        /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
-        /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
-        tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;
-        frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);
-
-        /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
-        tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1);
-        frequency = frequency/(tmpreg);
-        break;
-      }
-    case RCC_DCKCFGR1_SAI1SEL_1: /* External clock is the clock source for SAI1 */
-      {
-        frequency = EXTERNAL_CLOCK_VALUE;
-        break;
-      }
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-    case RCC_DCKCFGR1_SAI1SEL: /* HSI or HSE is the clock source for SAI*/
-      {
-        if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
-        {
-          /* In Case the main PLL Source is HSI */
-          frequency = HSI_VALUE;
-        }
-        else
-        {
-          /* In Case the main PLL Source is HSE */
-          frequency = HSE_VALUE;
-        }
-        break;
-      }
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-    default :
-      {
-        break;
-      }
-    }
-  }
-
-  if (PeriphClk == RCC_PERIPHCLK_SAI2)
-  {
-    saiclocksource = RCC->DCKCFGR1;
-    saiclocksource &= RCC_DCKCFGR1_SAI2SEL;
-    switch (saiclocksource)
-    {
-    case 0: /* PLLSAI is the clock source for SAI*/
-      {
-        /* Configure the PLLSAI division factor */
-        /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
-        if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
-        {
-          /* In Case the PLL Source is HSI (Internal Clock) */
-          vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
-        }
-        else
-        {
-          /* In Case the PLL Source is HSE (External Clock) */
-          vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
-        }
-        /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
-        /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
-        tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24;
-        frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg);
-
-        /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
-        tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1);
-        frequency = frequency/(tmpreg);
-        break;
-      }
-    case RCC_DCKCFGR1_SAI2SEL_0: /* PLLI2S is the clock source for SAI2 */
-      {
-        /* Configure the PLLI2S division factor */
-        /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */
-        if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
-        {
-          /* In Case the PLL Source is HSI (Internal Clock) */
-          vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
-        }
-        else
-        {
-          /* In Case the PLL Source is HSE (External Clock) */
-          vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
-        }
-
-        /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
-        /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
-        tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;
-        frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);
-
-        /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
-        tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1);
-        frequency = frequency/(tmpreg);
-        break;
-      }
-    case RCC_DCKCFGR1_SAI2SEL_1: /* External clock is the clock source for SAI2 */
-      {
-        frequency = EXTERNAL_CLOCK_VALUE;
-        break;
-      }
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
-    case RCC_DCKCFGR1_SAI2SEL: /* HSI or HSE is the clock source for SAI2 */
-      {
-        if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
-        {
-          /* In Case the main PLL Source is HSI */
-          frequency = HSI_VALUE;
-        }
-        else
-        {
-          /* In Case the main PLL Source is HSE */
-          frequency = HSE_VALUE;
-        }
-        break;
-      }
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-    default :
-      {
-        break;
-      }
-    }
-  }
-
-  return frequency;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_RCC_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_rng.c b/stmhal/hal/f7/src/stm32f7xx_hal_rng.c
deleted file mode 100644
index a9c1169536..0000000000
--- a/stmhal/hal/f7/src/stm32f7xx_hal_rng.c
+++ /dev/null
@@ -1,522 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_rng.c
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   RNG HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Random Number Generator (RNG) peripheral:
-  *           + Initialization/de-initialization functions
-  *           + Peripheral Control functions
-  *           + Peripheral State functions
-  *
-  @verbatim
-  ==============================================================================
-                     ##### How to use this driver #####
-  ==============================================================================
-  [..]
-      The RNG HAL driver can be used as follows:
-
-      (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro
-          in HAL_RNG_MspInit().
-      (#) Activate the RNG peripheral using HAL_RNG_Init() function.
-      (#) Wait until the 32 bit Random Number Generator contains a valid
-          random data using (polling/interrupt) mode.
-      (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup RNG
-  * @{
-  */
-
-#ifdef HAL_RNG_MODULE_ENABLED
-
-/* Private types -------------------------------------------------------------*/
-/* Private defines -----------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @addtogroup RNG_Private_Constants
-  * @{
-  */
-#define RNG_TIMEOUT_VALUE     2
-/**
-  * @}
-  */
-/* Private macros ------------------------------------------------------------*/
-/* Private functions prototypes ----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup RNG_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup RNG_Exported_Functions_Group1
- *  @brief   Initialization and de-initialization functions
- *
-@verbatim
- ===============================================================================
-          ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Initialize the RNG according to the specified parameters
-          in the RNG_InitTypeDef and create the associated handle
-      (+) DeInitialize the RNG peripheral
-      (+) Initialize the RNG MSP
-      (+) DeInitialize RNG MSP
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the RNG peripheral and creates the associated handle.
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
-  *                the configuration information for RNG.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
-{
-  /* Check the RNG handle allocation */
-  if(hrng == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  __HAL_LOCK(hrng);
-
-  if(hrng->State == HAL_RNG_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hrng->Lock = HAL_UNLOCKED;
-
-    /* Init the low level hardware */
-    HAL_RNG_MspInit(hrng);
-  }
-
-  /* Change RNG peripheral state */
-  hrng->State = HAL_RNG_STATE_BUSY;
-
-  /* Enable the RNG Peripheral */
-  __HAL_RNG_ENABLE(hrng);
-
-  /* Initialize the RNG state */
-  hrng->State = HAL_RNG_STATE_READY;
-
-  __HAL_UNLOCK(hrng);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the RNG peripheral.
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
-  *                the configuration information for RNG.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)
-{
-  /* Check the RNG handle allocation */
-  if(hrng == NULL)
-  {
-    return HAL_ERROR;
-  }
-  /* Disable the RNG Peripheral */
-  CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN);
-
-  /* Clear RNG interrupt status flags */
-  CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS);
-
-  /* DeInit the low level hardware */
-  HAL_RNG_MspDeInit(hrng);
-
-  /* Update the RNG state */
-  hrng->State = HAL_RNG_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hrng);
-
-  /* Return the function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the RNG MSP.
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
-  *                the configuration information for RNG.
-  * @retval None
-  */
-__weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrng);
-
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_RNG_MspInit must be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  DeInitializes the RNG MSP.
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
-  *                the configuration information for RNG.
-  * @retval None
-  */
-__weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrng);
-
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_RNG_MspDeInit must be implemented in the user file.
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup RNG_Exported_Functions_Group2
- *  @brief   Peripheral Control functions
- *
-@verbatim
- ===============================================================================
-                      ##### Peripheral Control functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Get the 32 bit Random number
-      (+) Get the 32 bit Random number with interrupt enabled
-      (+) Handle RNG interrupt request
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Generates a 32-bit random number.
-  * @note   Each time the random number data is read the RNG_FLAG_DRDY flag
-  *         is automatically cleared.
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
-  *                the configuration information for RNG.
-  * @param  random32bit: pointer to generated random number variable if successful.
-  * @retval HAL status
-  */
-
-HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit)
-{
-  uint32_t tickstart = 0;
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process Locked */
-  __HAL_LOCK(hrng);
-
-  /* Check RNG peripheral state */
-  if(hrng->State == HAL_RNG_STATE_READY)
-  {
-    /* Change RNG peripheral state */
-    hrng->State = HAL_RNG_STATE_BUSY;
-
-    /* Get tick */
-    tickstart = HAL_GetTick();
-
-    /* Check if data register contains valid random data */
-    while(__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RNG_TIMEOUT_VALUE)
-      {
-        hrng->State = HAL_RNG_STATE_ERROR;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrng);
-
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Get a 32bit Random number */
-    hrng->RandomNumber = hrng->Instance->DR;
-    *random32bit = hrng->RandomNumber;
-
-    hrng->State = HAL_RNG_STATE_READY;
-  }
-  else
-  {
-    status = HAL_ERROR;
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrng);
-
-  return status;
-}
-
-/**
-  * @brief  Generates a 32-bit random number in interrupt mode.
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
-  *                the configuration information for RNG.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process Locked */
-  __HAL_LOCK(hrng);
-
-  /* Check RNG peripheral state */
-  if(hrng->State == HAL_RNG_STATE_READY)
-  {
-    /* Change RNG peripheral state */
-    hrng->State = HAL_RNG_STATE_BUSY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hrng);
-
-    /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */
-    __HAL_RNG_ENABLE_IT(hrng);
-  }
-  else
-  {
-    /* Process Unlocked */
-    __HAL_UNLOCK(hrng);
-
-    status = HAL_ERROR;
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Handles RNG interrupt request.
-  * @note   In the case of a clock error, the RNG is no more able to generate
-  *         random numbers because the PLL48CLK clock is not correct. User has
-  *         to check that the clock controller is correctly configured to provide
-  *         the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT().
-  *         The clock error has no impact on the previously generated
-  *         random numbers, and the RNG_DR register contents can be used.
-  * @note   In the case of a seed error, the generation of random numbers is
-  *         interrupted as long as the SECS bit is '1'. If a number is
-  *         available in the RNG_DR register, it must not be used because it may
-  *         not have enough entropy. In this case, it is recommended to clear the
-  *         SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable
-  *         the RNG peripheral to reinitialize and restart the RNG.
-  * @note   User-written HAL_RNG_ErrorCallback() API is called once whether SEIS
-  *         or CEIS are set.
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
-  *                the configuration information for RNG.
-  * @retval None
-
-  */
-void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
-{
-  /* RNG clock error interrupt occurred */
-  if((__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET) ||  (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET))
-  {
-    /* Change RNG peripheral state */
-    hrng->State = HAL_RNG_STATE_ERROR;
-
-    HAL_RNG_ErrorCallback(hrng);
-
-    /* Clear the clock error flag */
-    __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI|RNG_IT_SEI);
-
-  }
-
-  /* Check RNG data ready interrupt occurred */
-  if(__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET)
-  {
-    /* Generate random number once, so disable the IT */
-    __HAL_RNG_DISABLE_IT(hrng);
-
-    /* Get the 32bit Random number (DRDY flag automatically cleared) */
-    hrng->RandomNumber = hrng->Instance->DR;
-
-    if(hrng->State != HAL_RNG_STATE_ERROR)
-    {
-      /* Change RNG peripheral state */
-      hrng->State = HAL_RNG_STATE_READY;
-
-      /* Data Ready callback */
-      HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber);
-    }
-  }
-}
-
-/**
-  * @brief  Returns generated random number in polling mode (Obsolete)
-  *         Use HAL_RNG_GenerateRandomNumber() API instead.
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
-  *                the configuration information for RNG.
-  * @retval Random value
-  */
-uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng)
-{
-  if(HAL_RNG_GenerateRandomNumber(hrng, &(hrng->RandomNumber)) == HAL_OK)
-  {
-    return hrng->RandomNumber;
-  }
-  else
-  {
-    return 0;
-  }
-}
-
-/**
-  * @brief  Returns a 32-bit random number with interrupt enabled (Obsolete),
-  *         Use HAL_RNG_GenerateRandomNumber_IT() API instead.
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
-  *                the configuration information for RNG.
-  * @retval 32-bit random number
-  */
-uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng)
-{
-  uint32_t random32bit = 0;
-
-  /* Process locked */
-  __HAL_LOCK(hrng);
-
-  /* Change RNG peripheral state */
-  hrng->State = HAL_RNG_STATE_BUSY;
-
-  /* Get a 32bit Random number */
-  random32bit = hrng->Instance->DR;
-
-  /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */
-  __HAL_RNG_ENABLE_IT(hrng);
-
-  /* Return the 32 bit random number */
-  return random32bit;
-}
-
-/**
-  * @brief  Read latest generated random number.
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
-  *                the configuration information for RNG.
-  * @retval random value
-  */
-uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng)
-{
-  return(hrng->RandomNumber);
-}
-
-/**
-  * @brief  Data Ready callback in non-blocking mode.
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
-  *                the configuration information for RNG.
-  * @param  random32bit: generated random number.
-  * @retval None
-  */
-__weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrng);
-
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_RNG_ReadyDataCallback must be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  RNG error callbacks.
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
-  *                the configuration information for RNG.
-  * @retval None
-  */
-__weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrng);
-
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_RNG_ErrorCallback must be implemented in the user file.
-   */
-}
-/**
-  * @}
-  */
-
-
-/** @addtogroup RNG_Exported_Functions_Group3
- *  @brief   Peripheral State functions
- *
-@verbatim
- ===============================================================================
-                      ##### Peripheral State functions #####
- ===============================================================================
-    [..]
-    This subsection permits to get in run-time the status of the peripheral
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Returns the RNG state.
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
-  *                the configuration information for RNG.
-  * @retval HAL state
-  */
-HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
-{
-  return hrng->State;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_rtc.c b/stmhal/hal/f7/src/stm32f7xx_hal_rtc.c
deleted file mode 100644
index af604feb22..0000000000
--- a/stmhal/hal/f7/src/stm32f7xx_hal_rtc.c
+++ /dev/null
@@ -1,1567 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_rtc.c
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   RTC HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Real Time Clock (RTC) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + RTC Time and Date functions
-  *           + RTC Alarm functions
-  *           + Peripheral Control functions
-  *           + Peripheral State functions
-  *
-  @verbatim
-  ==============================================================================
-              ##### Backup Domain Operating Condition #####
-  ==============================================================================
-  [..] The real-time clock (RTC), the RTC backup registers, and the backup
-       SRAM (BKP SRAM) can be powered from the VBAT voltage when the main
-       VDD supply is powered off.
-       To retain the content of the RTC backup registers, backup SRAM, and supply
-       the RTC when VDD is turned off, VBAT pin can be connected to an optional
-       standby voltage supplied by a battery or by another source.
-
-  [..] To allow the RTC operating even when the main digital supply (VDD) is turned
-       off, the VBAT pin powers the following blocks:
-    (#) The RTC
-    (#) The LSE oscillator
-    (#) The backup SRAM when the low power backup regulator is enabled
-    (#) PC13 to PC15 I/Os, plus PI8 I/O (when available)
-
-  [..] When the backup domain is supplied by VDD (analog switch connected to VDD),
-       the following pins are available:
-    (#) PC14 and PC15 can be used as either GPIO or LSE pins
-    (#) PC13 can be used as a GPIO or as the RTC_AF1 pin
-    (#) PI8 can be used as a GPIO or as the RTC_AF2 pin
-
-  [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT
-       because VDD is not present), the following pins are available:
-    (#) PC14 and PC15 can be used as LSE pins only
-    (#) PC13 can be used as the RTC_AF1 pin
-    (#) PI8 can be used as the RTC_AF2 pin
-    (#) PC1 can be used as the RTC_AF3 pin
-
-                   ##### Backup Domain Reset #####
-  ==================================================================
-  [..] The backup domain reset sets all RTC registers and the RCC_BDCR register
-       to their reset values. The BKPSRAM is not affected by this reset. The only
-       way to reset the BKPSRAM is through the Flash interface by requesting
-       a protection level change from 1 to 0.
-  [..] A backup domain reset is generated when one of the following events occurs:
-    (#) Software reset, triggered by setting the BDRST bit in the
-        RCC Backup domain control register (RCC_BDCR).
-    (#) VDD or VBAT power on, if both supplies have previously been powered off.
-
-                   ##### Backup Domain Access #####
-  ==================================================================
-  [..] After reset, the backup domain (RTC registers, RTC backup data
-       registers and backup SRAM) is protected against possible unwanted write
-       accesses.
-  [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
-    (+) Enable the Power Controller (PWR) APB1 interface clock using the
-        __HAL_RCC_PWR_CLK_ENABLE() function.
-    (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
-    (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function.
-    (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function.
-
-
-                  ##### How to use this driver #####
-  ==================================================================
-  [..]
-    (+) Enable the RTC domain access (see description in the section above).
-    (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
-        format using the HAL_RTC_Init() function.
-
-  *** Time and Date configuration ***
-  ===================================
-  [..]
-    (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
-        and HAL_RTC_SetDate() functions.
-    (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.
-
-  *** Alarm configuration ***
-  ===========================
-  [..]
-    (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
-        You can also configure the RTC Alarm with interrupt mode using the HAL_RTC_SetAlarm_IT() function.
-    (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.
-
-                  ##### RTC and low power modes #####
-  ==================================================================
-  [..] The MCU can be woken up from a low power mode by an RTC alternate
-       function.
-  [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
-       RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
-       These RTC alternate functions can wake up the system from the Stop and
-       Standby low power modes.
-  [..] The system can also wake up from low power modes without depending
-       on an external interrupt (Auto-wakeup mode), by using the RTC alarm
-       or the RTC wakeup events.
-  [..] The RTC provides a programmable time base for waking up from the
-       Stop or Standby mode at regular intervals.
-       Wakeup from STOP and STANDBY modes is possible only when the RTC clock source
-       is LSE or LSI.
-
-   @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup RTC RTC
-  * @brief RTC HAL module driver
-  * @{
-  */
-
-#ifdef HAL_RTC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup RTC_Exported_Functions RTC Exported Functions
-  * @{
-  */
-
-/** @defgroup RTC_Group1 Initialization and de-initialization functions
- *  @brief    Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-   [..] This section provides functions allowing to initialize and configure the
-         RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
-         RTC registers Write protection, enter and exit the RTC initialization mode,
-         RTC registers synchronization check and reference clock detection enable.
-         (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
-             It is split into 2 programmable prescalers to minimize power consumption.
-             (++) A 7-bit asynchronous prescaler and a 13-bit synchronous prescaler.
-             (++) When both prescalers are used, it is recommended to configure the
-                 asynchronous prescaler to a high value to minimize power consumption.
-         (#) All RTC registers are Write protected. Writing to the RTC registers
-             is enabled by writing a key into the Write Protection register, RTC_WPR.
-         (#) To configure the RTC Calendar, user application should enter
-             initialization mode. In this mode, the calendar counter is stopped
-             and its value can be updated. When the initialization sequence is
-             complete, the calendar restarts counting after 4 RTCCLK cycles.
-         (#) To read the calendar through the shadow registers after Calendar
-             initialization, calendar update or after wakeup from low power modes
-             the software must first clear the RSF flag. The software must then
-             wait until it is set again before reading the calendar, which means
-             that the calendar registers have been correctly copied into the
-             RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function
-             implements the above software sequence (RSF clear and RSF check).
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the RTC peripheral
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
-{
-  /* Check the RTC peripheral state */
-  if(hrtc == NULL)
-  {
-     return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
-  assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat));
-  assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv));
-  assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv));
-  assert_param (IS_RTC_OUTPUT(hrtc->Init.OutPut));
-  assert_param (IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity));
-  assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType));
-
-  if(hrtc->State == HAL_RTC_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hrtc->Lock = HAL_UNLOCKED;
-    /* Initialize RTC MSP */
-    HAL_RTC_MspInit(hrtc);
-  }
-
-  /* Set RTC state */
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Set Initialization mode */
-  if(RTC_EnterInitMode(hrtc) != HAL_OK)
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-    /* Set RTC state */
-    hrtc->State = HAL_RTC_STATE_ERROR;
-
-    return HAL_ERROR;
-  }
-  else
-  {
-    /* Clear RTC_CR FMT, OSEL and POL Bits */
-    hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));
-    /* Set RTC_CR register */
-    hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
-
-    /* Configure the RTC PRER */
-    hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
-    hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16);
-
-    /* Exit Initialization mode */
-    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
-
-    hrtc->Instance->OR &= (uint32_t)~RTC_OR_ALARMTYPE;
-    hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType);
-
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-    /* Set RTC state */
-    hrtc->State = HAL_RTC_STATE_READY;
-
-    return HAL_OK;
-  }
-}
-
-/**
-  * @brief  DeInitializes the RTC peripheral
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @note   This function doesn't reset the RTC Backup Data registers.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
-{
-  uint32_t tickstart = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
-
-  /* Set RTC state */
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Set Initialization mode */
-  if(RTC_EnterInitMode(hrtc) != HAL_OK)
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-    /* Set RTC state */
-    hrtc->State = HAL_RTC_STATE_ERROR;
-
-    return HAL_ERROR;
-  }
-  else
-  {
-    /* Reset TR, DR and CR registers */
-    hrtc->Instance->TR = (uint32_t)0x00000000;
-    hrtc->Instance->DR = (uint32_t)0x00002101;
-    /* Reset All CR bits except CR[2:0] */
-    hrtc->Instance->CR &= (uint32_t)0x00000007;
-
-    /* Get tick */
-    tickstart = HAL_GetTick();
-
-    /* Wait till WUTWF flag is set and if Time out is reached exit */
-    while(((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        /* Set RTC state */
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Reset all RTC CR register bits */
-    hrtc->Instance->CR &= (uint32_t)0x00000000;
-    hrtc->Instance->WUTR = (uint32_t)0x0000FFFF;
-    hrtc->Instance->PRER = (uint32_t)0x007F00FF;
-    hrtc->Instance->ALRMAR = (uint32_t)0x00000000;
-    hrtc->Instance->ALRMBR = (uint32_t)0x00000000;
-    hrtc->Instance->SHIFTR = (uint32_t)0x00000000;
-    hrtc->Instance->CALR = (uint32_t)0x00000000;
-    hrtc->Instance->ALRMASSR = (uint32_t)0x00000000;
-    hrtc->Instance->ALRMBSSR = (uint32_t)0x00000000;
-
-    /* Reset ISR register and exit initialization mode */
-    hrtc->Instance->ISR = (uint32_t)0x00000000;
-
-    /* Reset Tamper and alternate functions configuration register */
-    hrtc->Instance->TAMPCR = 0x00000000;
-
-    /* Reset Option register */
-    hrtc->Instance->OR = 0x00000000;
-
-    /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
-    if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
-    {
-      if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_ERROR;
-
-        return HAL_ERROR;
-      }
-    }
-  }
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* De-Initialize RTC MSP */
-  HAL_RTC_MspDeInit(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the RTC MSP.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval None
-  */
-__weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_RTC_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes the RTC MSP.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval None
-  */
-__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_RTC_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Group2 RTC Time and Date functions
- *  @brief   RTC Time and Date functions
- *
-@verbatim
- ===============================================================================
-                 ##### RTC Time and Date functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure Time and Date features
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Sets RTC current time.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  sTime: Pointer to Time structure
-  * @param  Format: Specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *            @arg FORMAT_BIN: Binary data format
-  *            @arg FORMAT_BCD: BCD data format
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
-{
-  uint32_t tmpreg = 0;
-
- /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-  assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving));
-  assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  if(Format == RTC_FORMAT_BIN)
-  {
-    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
-    {
-      assert_param(IS_RTC_HOUR12(sTime->Hours));
-      assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
-    }
-    else
-    {
-      sTime->TimeFormat = 0x00;
-      assert_param(IS_RTC_HOUR24(sTime->Hours));
-    }
-    assert_param(IS_RTC_MINUTES(sTime->Minutes));
-    assert_param(IS_RTC_SECONDS(sTime->Seconds));
-
-    tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16) | \
-                        ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8) | \
-                        ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \
-                        (((uint32_t)sTime->TimeFormat) << 16));
-  }
-  else
-  {
-    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
-    {
-      tmpreg = RTC_Bcd2ToByte(sTime->Hours);
-      assert_param(IS_RTC_HOUR12(tmpreg));
-      assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
-    }
-    else
-    {
-      sTime->TimeFormat = 0x00;
-      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours)));
-    }
-    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));
-    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));
-    tmpreg = (((uint32_t)(sTime->Hours) << 16) | \
-              ((uint32_t)(sTime->Minutes) << 8) | \
-              ((uint32_t)sTime->Seconds) | \
-              ((uint32_t)(sTime->TimeFormat) << 16));
-  }
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Set Initialization mode */
-  if(RTC_EnterInitMode(hrtc) != HAL_OK)
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-    /* Set RTC state */
-    hrtc->State = HAL_RTC_STATE_ERROR;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hrtc);
-
-    return HAL_ERROR;
-  }
-  else
-  {
-    /* Set the RTC_TR register */
-    hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
-
-    /* Clear the bits to be configured */
-    hrtc->Instance->CR &= (uint32_t)~RTC_CR_BKP;
-
-    /* Configure the RTC_CR register */
-    hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
-
-    /* Exit Initialization mode */
-    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
-
-    /* If  CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
-    if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
-    {
-      if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_ERROR;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_ERROR;
-      }
-    }
-
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-   hrtc->State = HAL_RTC_STATE_READY;
-
-   __HAL_UNLOCK(hrtc);
-
-   return HAL_OK;
-  }
-}
-
-/**
-  * @brief  Gets RTC current time.
-  * @param  hrtc: RTC handle
-  * @param  sTime: Pointer to Time structure with Hours, Minutes and Seconds fields returned
-  *                with input format (BIN or BCD), also SubSeconds field returning the
-  *                RTC_SSR register content and SecondFraction field the Synchronous pre-scaler
-  *                factor to be used for second fraction ratio computation.
-  * @param  Format: Specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *            @arg RTC_FORMAT_BIN: Binary data format
-  *            @arg RTC_FORMAT_BCD: BCD data format
-  * @note  You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds
-  *        value in second fraction ratio with time unit following generic formula:
-  *        Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
-  *        This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS
-  * @note  You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
-  *        in the higher-order calendar shadow registers to ensure consistency between the time and date values.
-  *        Reading RTC current time locks the values in calendar shadow registers until Current date is read
-  *        to ensure consistency between the time and date values.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-
-  /* Get subseconds values from the correspondent registers*/
-  sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR);
-
-  /* Get SecondFraction structure field from the corresponding register field*/
-  sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S);
-
-  /* Get the TR register */
-  tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK);
-
-  /* Fill the structure fields with the read parameters */
-  sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16);
-  sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8);
-  sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
-  sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16);
-
-  /* Check the input parameters format */
-  if(Format == RTC_FORMAT_BIN)
-  {
-    /* Convert the time structure parameters to Binary format */
-    sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours);
-    sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes);
-    sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds);
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Sets RTC current date.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  sDate: Pointer to date structure
-  * @param  Format: specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *            @arg RTC_FORMAT_BIN: Binary data format
-  *            @arg RTC_FORMAT_BCD: BCD data format
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
-{
-  uint32_t datetmpreg = 0;
-
- /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U))
-  {
-    sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU);
-  }
-
-  assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));
-
-  if(Format == RTC_FORMAT_BIN)
-  {
-    assert_param(IS_RTC_YEAR(sDate->Year));
-    assert_param(IS_RTC_MONTH(sDate->Month));
-    assert_param(IS_RTC_DATE(sDate->Date));
-
-   datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16) | \
-                 ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8) | \
-                 ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \
-                 ((uint32_t)sDate->WeekDay << 13));
-  }
-  else
-  {
-    assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));
-    datetmpreg = RTC_Bcd2ToByte(sDate->Month);
-    assert_param(IS_RTC_MONTH(datetmpreg));
-    datetmpreg = RTC_Bcd2ToByte(sDate->Date);
-    assert_param(IS_RTC_DATE(datetmpreg));
-
-    datetmpreg = ((((uint32_t)sDate->Year) << 16) | \
-                  (((uint32_t)sDate->Month) << 8) | \
-                  ((uint32_t)sDate->Date) | \
-                  (((uint32_t)sDate->WeekDay) << 13));
-  }
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Set Initialization mode */
-  if(RTC_EnterInitMode(hrtc) != HAL_OK)
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-    /* Set RTC state*/
-    hrtc->State = HAL_RTC_STATE_ERROR;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hrtc);
-
-    return HAL_ERROR;
-  }
-  else
-  {
-    /* Set the RTC_DR register */
-    hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK);
-
-    /* Exit Initialization mode */
-    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
-
-    /* If  CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
-    if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
-    {
-      if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_ERROR;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_ERROR;
-      }
-    }
-
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-    hrtc->State = HAL_RTC_STATE_READY ;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hrtc);
-
-    return HAL_OK;
-  }
-}
-
-/**
-  * @brief  Gets RTC current date.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  sDate: Pointer to Date structure
-  * @param  Format: Specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *            @arg RTC_FORMAT_BIN:  Binary data format
-  *            @arg RTC_FORMAT_BCD:  BCD data format
-  * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
-  * in the higher-order calendar shadow registers to ensure consistency between the time and date values.
-  * Reading RTC current time locks the values in calendar shadow registers until Current date is read.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
-{
-  uint32_t datetmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-
-  /* Get the DR register */
-  datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK);
-
-  /* Fill the structure fields with the read parameters */
-  sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16);
-  sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8);
-  sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU));
-  sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13);
-
-  /* Check the input parameters format */
-  if(Format == RTC_FORMAT_BIN)
-  {
-    /* Convert the date structure parameters to Binary format */
-    sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);
-    sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month);
-    sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date);
-  }
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Group3 RTC Alarm functions
- *  @brief   RTC Alarm functions
- *
-@verbatim
- ===============================================================================
-                 ##### RTC Alarm functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure Alarm feature
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Sets the specified RTC Alarm.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  sAlarm: Pointer to Alarm structure
-  * @param  Format: Specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *             @arg FORMAT_BIN: Binary data format
-  *             @arg FORMAT_BCD: BCD data format
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
-{
-  uint32_t tickstart = 0;
-  uint32_t tmpreg = 0, subsecondtmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-  assert_param(IS_RTC_ALARM(sAlarm->Alarm));
-  assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
-  assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
-  assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
-  assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  if(Format == RTC_FORMAT_BIN)
-  {
-    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
-    {
-      assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
-      assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
-    }
-    else
-    {
-      sAlarm->AlarmTime.TimeFormat = 0x00;
-      assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
-    }
-    assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
-    assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
-
-    if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
-    {
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
-    }
-    else
-    {
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
-    }
-
-    tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \
-              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \
-              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
-              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
-              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \
-              ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
-              ((uint32_t)sAlarm->AlarmMask));
-  }
-  else
-  {
-    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
-    {
-      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
-      assert_param(IS_RTC_HOUR12(tmpreg));
-      assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
-    }
-    else
-    {
-      sAlarm->AlarmTime.TimeFormat = 0x00;
-      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
-    }
-
-    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
-    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
-
-    if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
-    {
-      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
-    }
-    else
-    {
-      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
-    }
-
-    tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \
-              ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \
-              ((uint32_t) sAlarm->AlarmTime.Seconds) | \
-              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
-              ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \
-              ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
-              ((uint32_t)sAlarm->AlarmMask));
-  }
-
-  /* Configure the Alarm A or Alarm B Sub Second registers */
-  subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Configure the Alarm register */
-  if(sAlarm->Alarm == RTC_ALARM_A)
-  {
-    /* Disable the Alarm A interrupt */
-    __HAL_RTC_ALARMA_DISABLE(hrtc);
-
-    /* In case of interrupt mode is used, the interrupt source must disabled */
-    __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
-
-    /* Get tick */
-    tickstart = HAL_GetTick();
-
-    /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
-    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-
-    hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
-    /* Configure the Alarm A Sub Second register */
-    hrtc->Instance->ALRMASSR = subsecondtmpreg;
-    /* Configure the Alarm state: Enable Alarm */
-    __HAL_RTC_ALARMA_ENABLE(hrtc);
-  }
-  else
-  {
-    /* Disable the Alarm B interrupt */
-    __HAL_RTC_ALARMB_DISABLE(hrtc);
-
-    /* In case of interrupt mode is used, the interrupt source must disabled */
-    __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB);
-
-    /* Get tick */
-    tickstart = HAL_GetTick();
-
-    /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
-    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-
-    hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
-    /* Configure the Alarm B Sub Second register */
-    hrtc->Instance->ALRMBSSR = subsecondtmpreg;
-    /* Configure the Alarm state: Enable Alarm */
-    __HAL_RTC_ALARMB_ENABLE(hrtc);
-  }
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Sets the specified RTC Alarm with Interrupt
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  sAlarm: Pointer to Alarm structure
-  * @param  Format: Specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *             @arg FORMAT_BIN: Binary data format
-  *             @arg FORMAT_BCD: BCD data format
-  * @note   The Alarm register can only be written when the corresponding Alarm
-  *         is disabled (Use the HAL_RTC_DeactivateAlarm()).
-  * @note   The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
-{
-  uint32_t tickstart = 0;
-  uint32_t tmpreg = 0, subsecondtmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-  assert_param(IS_RTC_ALARM(sAlarm->Alarm));
-  assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
-  assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
-  assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
-  assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  if(Format == RTC_FORMAT_BIN)
-  {
-    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
-    {
-      assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
-      assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
-    }
-    else
-    {
-      sAlarm->AlarmTime.TimeFormat = 0x00;
-      assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
-    }
-    assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
-    assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
-
-    if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
-    {
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
-    }
-    else
-    {
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
-    }
-    tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \
-              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \
-              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
-              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
-              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \
-              ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
-              ((uint32_t)sAlarm->AlarmMask));
-  }
-  else
-  {
-    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
-    {
-      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
-      assert_param(IS_RTC_HOUR12(tmpreg));
-      assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
-    }
-    else
-    {
-      sAlarm->AlarmTime.TimeFormat = 0x00;
-      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
-    }
-
-    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
-    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
-
-    if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
-    {
-      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
-    }
-    else
-    {
-      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
-    }
-    tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \
-              ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \
-              ((uint32_t) sAlarm->AlarmTime.Seconds) | \
-              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
-              ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \
-              ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
-              ((uint32_t)sAlarm->AlarmMask));
-  }
-  /* Configure the Alarm A or Alarm B Sub Second registers */
-  subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Configure the Alarm register */
-  if(sAlarm->Alarm == RTC_ALARM_A)
-  {
-    /* Disable the Alarm A interrupt */
-    __HAL_RTC_ALARMA_DISABLE(hrtc);
-
-    /* Clear flag alarm A */
-    __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
-
-    /* Get tick */
-    tickstart = HAL_GetTick();
-
-    /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
-    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-
-    hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
-    /* Configure the Alarm A Sub Second register */
-    hrtc->Instance->ALRMASSR = subsecondtmpreg;
-    /* Configure the Alarm state: Enable Alarm */
-    __HAL_RTC_ALARMA_ENABLE(hrtc);
-    /* Configure the Alarm interrupt */
-    __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA);
-  }
-  else
-  {
-    /* Disable the Alarm B interrupt */
-    __HAL_RTC_ALARMB_DISABLE(hrtc);
-
-    /* Clear flag alarm B */
-    __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
-
-    /* Get tick */
-    tickstart = HAL_GetTick();
-
-    /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
-    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-
-    hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
-    /* Configure the Alarm B Sub Second register */
-    hrtc->Instance->ALRMBSSR = subsecondtmpreg;
-    /* Configure the Alarm state: Enable Alarm */
-    __HAL_RTC_ALARMB_ENABLE(hrtc);
-    /* Configure the Alarm interrupt */
-    __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB);
-  }
-
-  /* RTC Alarm Interrupt Configuration: EXTI configuration */
-  __HAL_RTC_ALARM_EXTI_ENABLE_IT();
-
-  EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT;
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deactive the specified RTC Alarm
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  Alarm: Specifies the Alarm.
-  *          This parameter can be one of the following values:
-  *            @arg RTC_ALARM_A:  AlarmA
-  *            @arg RTC_ALARM_B:  AlarmB
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
-{
-  uint32_t tickstart = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_ALARM(Alarm));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  if(Alarm == RTC_ALARM_A)
-  {
-    /* AlarmA */
-    __HAL_RTC_ALARMA_DISABLE(hrtc);
-
-    /* In case of interrupt mode is used, the interrupt source must disabled */
-    __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
-
-    /* Get tick */
-    tickstart = HAL_GetTick();
-
-    /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
-    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  else
-  {
-    /* AlarmB */
-    __HAL_RTC_ALARMB_DISABLE(hrtc);
-
-    /* In case of interrupt mode is used, the interrupt source must disabled */
-    __HAL_RTC_ALARM_DISABLE_IT(hrtc,RTC_IT_ALRB);
-
-    /* Get tick */
-    tickstart = HAL_GetTick();
-
-    /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
-    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Gets the RTC Alarm value and masks.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  sAlarm: Pointer to Date structure
-  * @param  Alarm: Specifies the Alarm.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_ALARM_A: AlarmA
-  *             @arg RTC_ALARM_B: AlarmB
-  * @param  Format: Specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_FORMAT_BIN: Binary data format
-  *             @arg RTC_FORMAT_BCD: BCD data format
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
-{
-  uint32_t tmpreg = 0, subsecondtmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-  assert_param(IS_RTC_ALARM(Alarm));
-
-  if(Alarm == RTC_ALARM_A)
-  {
-    /* AlarmA */
-    sAlarm->Alarm = RTC_ALARM_A;
-
-    tmpreg = (uint32_t)(hrtc->Instance->ALRMAR);
-    subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR ) & RTC_ALRMASSR_SS);
-  }
-  else
-  {
-    sAlarm->Alarm = RTC_ALARM_B;
-
-    tmpreg = (uint32_t)(hrtc->Instance->ALRMBR);
-    subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS);
-  }
-
-  /* Fill the structure with the read parameters */
-  sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16);
-  sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8);
-  sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
-  sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16);
-  sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;
-  sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24);
-  sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
-  sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
-
-  if(Format == RTC_FORMAT_BIN)
-  {
-    sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
-    sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes);
-    sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds);
-    sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles Alarm interrupt request.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval None
-  */
-void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
-{
-  if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRA))
-  {
-    /* Get the status of the Interrupt */
-    if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRA) != (uint32_t)RESET)
-    {
-      /* AlarmA callback */
-      HAL_RTC_AlarmAEventCallback(hrtc);
-
-      /* Clear the Alarm interrupt pending bit */
-      __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRAF);
-    }
-  }
-
-  if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRB))
-  {
-    /* Get the status of the Interrupt */
-    if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRB) != (uint32_t)RESET)
-    {
-      /* AlarmB callback */
-      HAL_RTCEx_AlarmBEventCallback(hrtc);
-
-      /* Clear the Alarm interrupt pending bit */
-      __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRBF);
-    }
-  }
-
-  /* Clear the EXTI's line Flag for RTC Alarm */
-  __HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-}
-
-/**
-  * @brief  Alarm A callback.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval None
-  */
-__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_RTC_AlarmAEventCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  This function handles AlarmA Polling request.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
-  uint32_t tickstart = 0;
-
-    /* Get tick */
-    tickstart = HAL_GetTick();
-
-  while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET)
-  {
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Clear the Alarm interrupt pending bit */
-  __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Group4 Peripheral Control functions
- *  @brief   Peripheral Control functions
- *
-@verbatim
- ===============================================================================
-                     ##### Peripheral Control functions #####
- ===============================================================================
-    [..]
-    This subsection provides functions allowing to
-      (+) Wait for RTC Time and Date Synchronization
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are
-  *         synchronized with RTC APB clock.
-  * @note   The RTC Resynchronization mode is write protected, use the
-  *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
-  * @note   To read the calendar through the shadow registers after Calendar
-  *         initialization, calendar update or after wakeup from low power modes
-  *         the software must first clear the RSF flag.
-  *         The software must then wait until it is set again before reading
-  *         the calendar, which means that the calendar registers have been
-  *         correctly copied into the RTC_TR and RTC_DR shadow registers.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
-{
-  uint32_t tickstart = 0;
-
-  /* Clear RSF flag */
-  hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;
-
-    /* Get tick */
-    tickstart = HAL_GetTick();
-
-  /* Wait the registers to be synchronised */
-  while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET)
-  {
-    if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Group5 Peripheral State functions
- *  @brief   Peripheral State functions
- *
-@verbatim
- ===============================================================================
-                     ##### Peripheral State functions #####
- ===============================================================================
-    [..]
-    This subsection provides functions allowing to
-      (+) Get RTC state
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Returns the RTC state.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval HAL state
-  */
-HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)
-{
-  return hrtc->State;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @brief  Enters the RTC Initialization mode.
-  * @note   The RTC Initialization mode is write protected, use the
-  *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)
-{
-  uint32_t tickstart = 0;
-
-  /* Check if the Initialization mode is set */
-  if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
-  {
-    /* Set the Initialization mode */
-    hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
-
-    /* Get tick */
-    tickstart = HAL_GetTick();
-
-    /* Wait till RTC is in INIT state and if Time out is reached exit */
-    while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  Converts a 2 digit decimal to BCD format.
-  * @param  Value: Byte to be converted
-  * @retval Converted byte
-  */
-uint8_t RTC_ByteToBcd2(uint8_t Value)
-{
-  uint32_t bcdhigh = 0;
-
-  while(Value >= 10)
-  {
-    bcdhigh++;
-    Value -= 10;
-  }
-
-  return  ((uint8_t)(bcdhigh << 4) | Value);
-}
-
-/**
-  * @brief  Converts from 2 digit BCD to Binary.
-  * @param  Value: BCD value to be converted
-  * @retval Converted word
-  */
-uint8_t RTC_Bcd2ToByte(uint8_t Value)
-{
-  uint32_t tmp = 0;
-  tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
-  return (tmp + (Value & (uint8_t)0x0F));
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_RTC_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_rtc_ex.c b/stmhal/hal/f7/src/stm32f7xx_hal_rtc_ex.c
deleted file mode 100644
index 3289c24307..0000000000
--- a/stmhal/hal/f7/src/stm32f7xx_hal_rtc_ex.c
+++ /dev/null
@@ -1,1853 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_rtc_ex.c
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   RTC HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Real Time Clock (RTC) Extension peripheral:
-  *           + RTC Time Stamp functions
-  *           + RTC Tamper functions
-  *           + RTC Wake-up functions
-  *           + Extension Control functions
-  *           + Extension RTC features functions
-  *
-  @verbatim
-  ==============================================================================
-                  ##### How to use this driver #####
-  ==============================================================================
-  [..]
-    (+) Enable the RTC domain access.
-    (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
-        format using the HAL_RTC_Init() function.
-
-  *** RTC Wakeup configuration ***
-  ================================
-  [..]
-    (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTC_SetWakeUpTimer()
-        function. You can also configure the RTC Wakeup timer in interrupt mode
-        using the HAL_RTC_SetWakeUpTimer_IT() function.
-    (+) To read the RTC WakeUp Counter register, use the HAL_RTC_GetWakeUpTimer()
-        function.
-
-  *** TimeStamp configuration ***
-  ===============================
-  [..]
-    (+) Enables the RTC TimeStamp using the HAL_RTC_SetTimeStamp() function.
-        You can also configure the RTC TimeStamp with interrupt mode using the
-        HAL_RTC_SetTimeStamp_IT() function.
-    (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTC_GetTimeStamp()
-        function.
-
-  *** Internal TimeStamp configuration ***
-  ===============================
-  [..]
-    (+) Enables the RTC internal TimeStamp using the HAL_RTC_SetInternalTimeStamp() function.
-    (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTC_GetTimeStamp()
-        function.
-
-  *** Tamper configuration ***
-  ============================
-  [..]
-    (+) Enable the RTC Tamper and Configure the Tamper filter count, trigger Edge
-        or Level according to the Tamper filter (if equal to 0 Edge else Level)
-        value, sampling frequency, NoErase, MaskFlag,  precharge or discharge and
-        Pull-UP using the HAL_RTC_SetTamper() function. You can configure RTC Tamper
-        with interrupt mode using HAL_RTC_SetTamper_IT() function.
-    (+) The default configuration of the Tamper erases the backup registers. To avoid
-        erase, enable the NoErase field on the RTC_TAMPCR register.
-
-  *** Backup Data Registers configuration ***
-  ===========================================
-  [..]
-    (+) To write to the RTC Backup Data registers, use the HAL_RTC_BKUPWrite()
-        function.
-    (+) To read the RTC Backup Data registers, use the HAL_RTC_BKUPRead()
-        function.
-
-   @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup RTCEx RTCEx
-  * @brief RTC Extended HAL module driver
-  * @{
-  */
-
-#ifdef HAL_RTC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
-  * @{
-  */
-
-
-/** @defgroup RTCEx_Group1 RTC TimeStamp and Tamper functions
- *  @brief   RTC TimeStamp and Tamper functions
- *
-@verbatim
- ===============================================================================
-                 ##### RTC TimeStamp and Tamper functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure TimeStamp feature
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Sets TimeStamp.
-  * @note   This API must be called before enabling the TimeStamp feature.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  TimeStampEdge: Specifies the pin edge on which the TimeStamp is
-  *         activated.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
-  *                                        rising edge of the related pin.
-  *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
-  *                                         falling edge of the related pin.
-  * @param  RTC_TimeStampPin: specifies the RTC TimeStamp Pin.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin.
-  *             @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin.
-  *             @arg RTC_TIMESTAMPPIN_PC1: PC1 is selected as RTC TimeStamp Pin.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
-  assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Get the RTC_CR register and clear the bits to be configured */
-  tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
-
-  tmpreg|= TimeStampEdge;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  hrtc->Instance->OR &= (uint32_t)~RTC_OR_TSINSEL;
-  hrtc->Instance->OR |= (uint32_t)(RTC_TimeStampPin);
-
-  /* Configure the Time Stamp TSEDGE and Enable bits */
-  hrtc->Instance->CR = (uint32_t)tmpreg;
-
-  __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Sets TimeStamp with Interrupt.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @note   This API must be called before enabling the TimeStamp feature.
-  * @param  TimeStampEdge: Specifies the pin edge on which the TimeStamp is
-  *         activated.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
-  *                                        rising edge of the related pin.
-  *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
-  *                                         falling edge of the related pin.
-  * @param  RTC_TimeStampPin: Specifies the RTC TimeStamp Pin.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin.
-  *             @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin.
-  *             @arg RTC_TIMESTAMPPIN_PC1: PC1 is selected as RTC TimeStamp Pin.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
-  assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Get the RTC_CR register and clear the bits to be configured */
-  tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
-
-  tmpreg |= TimeStampEdge;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Configure the Time Stamp TSEDGE and Enable bits */
-  hrtc->Instance->CR = (uint32_t)tmpreg;
-
-  hrtc->Instance->OR &= (uint32_t)~RTC_OR_TSINSEL;
-  hrtc->Instance->OR |= (uint32_t)(RTC_TimeStampPin);
-
-  /* Clear RTC Timestamp flag */
-  __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
-
-  __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
-
-  /* Enable IT timestamp */
-  __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS);
-
-  /* RTC timestamp Interrupt Configuration: EXTI configuration */
-  __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
-
-  EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT;
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deactivates TimeStamp.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
-{
-  uint32_t tmpreg = 0;
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* In case of interrupt mode is used, the interrupt source must disabled */
-  __HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS);
-
-  /* Get the RTC_CR register and clear the bits to be configured */
-  tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
-
-  /* Configure the Time Stamp TSEDGE and Enable bits */
-  hrtc->Instance->CR = (uint32_t)tmpreg;
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Sets Internal TimeStamp.
-  * @note   This API must be called before enabling the internal TimeStamp feature.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc)
-{
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Configure the internal Time Stamp Enable bits */
-  __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(hrtc);
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deactivates internal TimeStamp.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc)
-{
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Configure the internal Time Stamp Enable bits */
-  __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(hrtc);
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Gets the RTC TimeStamp value.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  sTimeStamp: Pointer to Time structure
-  * @param  sTimeStampDate: Pointer to Date structure
-  * @param  Format: specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *             FORMAT_BIN: Binary data format
-  *             FORMAT_BCD: BCD data format
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format)
-{
-  uint32_t tmptime = 0, tmpdate = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-
-  /* Get the TimeStamp time and date registers values */
-  tmptime = (uint32_t)(hrtc->Instance->TSTR & RTC_TR_RESERVED_MASK);
-  tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK);
-
-  /* Fill the Time structure fields with the read parameters */
-  sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16);
-  sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8);
-  sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));
-  sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16);
-  sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR;
-
-  /* Fill the Date structure fields with the read parameters */
-  sTimeStampDate->Year = 0;
-  sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8);
-  sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
-  sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);
-
-  /* Check the input parameters format */
-  if(Format == RTC_FORMAT_BIN)
-  {
-    /* Convert the TimeStamp structure parameters to Binary format */
-    sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours);
-    sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes);
-    sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds);
-
-    /* Convert the DateTimeStamp structure parameters to Binary format */
-    sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month);
-    sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date);
-    sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay);
-  }
-
-  /* Clear the TIMESTAMP Flag */
-  __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Sets Tamper
-  * @note   By calling this API we disable the tamper interrupt for all tampers.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  sTamper: Pointer to Tamper Structure.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_TAMPER(sTamper->Tamper));
-  assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
-  assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase));
-  assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag));
-  assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
-  assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
-  assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
-  assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
-  assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
-  {
-    sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1);
-  }
-
-  if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
-  {
-    sTamper->NoErase = 0;
-    if((sTamper->Tamper & RTC_TAMPER_1) != 0)
-    {
-      sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE;
-    }
-    if((sTamper->Tamper & RTC_TAMPER_2) != 0)
-    {
-      sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE;
-    }
-    if((sTamper->Tamper & RTC_TAMPER_3) != 0)
-    {
-      sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE;
-    }
-  }
-
-  if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)
-  {
-    sTamper->MaskFlag = 0;
-    if((sTamper->Tamper & RTC_TAMPER_1) != 0)
-    {
-      sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF;
-    }
-    if((sTamper->Tamper & RTC_TAMPER_2) != 0)
-    {
-      sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF;
-    }
-    if((sTamper->Tamper & RTC_TAMPER_3) != 0)
-    {
-      sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF;
-    }
-  }
-
-  tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger  | (uint32_t)sTamper->NoErase |\
-            (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\
-            (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
-
-  hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAMPCR_TAMPTS |\
-                                       (uint32_t)RTC_TAMPCR_TAMPFREQ | (uint32_t)RTC_TAMPCR_TAMPFLT | (uint32_t)RTC_TAMPCR_TAMPPRCH |\
-                                       (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE | (uint32_t)RTC_TAMPCR_TAMP1IE |\
-                                       (uint32_t)RTC_TAMPCR_TAMP2IE | (uint32_t)RTC_TAMPCR_TAMP3IE | (uint32_t)RTC_TAMPCR_TAMP1NOERASE |\
-                                       (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP3NOERASE | (uint32_t)RTC_TAMPCR_TAMP1MF |\
-                                       (uint32_t)RTC_TAMPCR_TAMP2MF | (uint32_t)RTC_TAMPCR_TAMP3MF);
-
-  hrtc->Instance->TAMPCR |= tmpreg;
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Sets Tamper with interrupt.
-  * @note   By calling this API we force the tamper interrupt for all tampers.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  sTamper: Pointer to RTC Tamper.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_TAMPER(sTamper->Tamper));
-  assert_param(IS_RTC_TAMPER_INTERRUPT(sTamper->Interrupt));
-  assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
-  assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase));
-  assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag));
-  assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
-  assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
-  assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
-  assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
-  assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Configure the tamper trigger */
-  if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
-  {
-    sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1);
-  }
-
-  if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
-  {
-    sTamper->NoErase = 0;
-    if((sTamper->Tamper & RTC_TAMPER_1) != 0)
-    {
-      sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE;
-    }
-    if((sTamper->Tamper & RTC_TAMPER_2) != 0)
-    {
-      sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE;
-    }
-    if((sTamper->Tamper & RTC_TAMPER_3) != 0)
-    {
-      sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE;
-    }
-  }
-
-  if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)
-  {
-    sTamper->MaskFlag = 0;
-    if((sTamper->Tamper & RTC_TAMPER_1) != 0)
-    {
-      sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF;
-    }
-    if((sTamper->Tamper & RTC_TAMPER_2) != 0)
-    {
-      sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF;
-    }
-    if((sTamper->Tamper & RTC_TAMPER_3) != 0)
-    {
-      sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF;
-    }
-  }
-
-  tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Interrupt | (uint32_t)sTamper->Trigger  | (uint32_t)sTamper->NoErase |\
-            (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\
-            (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
-
-  hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAMPCR_TAMPTS |\
-                                       (uint32_t)RTC_TAMPCR_TAMPFREQ | (uint32_t)RTC_TAMPCR_TAMPFLT | (uint32_t)RTC_TAMPCR_TAMPPRCH |\
-                                       (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE | (uint32_t)RTC_TAMPCR_TAMP1IE |\
-                                       (uint32_t)RTC_TAMPCR_TAMP2IE | (uint32_t)RTC_TAMPCR_TAMP3IE | (uint32_t)RTC_TAMPCR_TAMP1NOERASE |\
-                                       (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP3NOERASE | (uint32_t)RTC_TAMPCR_TAMP1MF |\
-                                       (uint32_t)RTC_TAMPCR_TAMP2MF | (uint32_t)RTC_TAMPCR_TAMP3MF);
-
-  hrtc->Instance->TAMPCR |= tmpreg;
-
-  if(sTamper->Tamper == RTC_TAMPER_1)
-  {
-    /* Clear RTC Tamper 1 flag */
-    __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
-  }
-  else if(sTamper->Tamper == RTC_TAMPER_2)
-  {
-    /* Clear RTC Tamper 2 flag */
-    __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
-  }
-  else
-  {
-    /* Clear RTC Tamper 3 flag */
-    __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);
-  }
-
-  /* RTC Tamper Interrupt Configuration: EXTI configuration */
-  __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
-
-  EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT;
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deactivates Tamper.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  Tamper: Selected tamper pin.
-  *          This parameter can be RTC_Tamper_1 and/or RTC_TAMPER_2.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)
-{
-  assert_param(IS_RTC_TAMPER(Tamper));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-/* Disable the selected Tamper pin */
-  hrtc->Instance->TAMPCR &= (uint32_t)~Tamper;
-
-  if ((Tamper & RTC_TAMPER_1) != 0)
-  {
-    /* Disable the Tamper1 interrupt */
-    hrtc->Instance->TAMPCR &= (uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP1);
-  }
-  if ((Tamper & RTC_TAMPER_2) != 0)
-  {
-    /* Disable the Tamper2 interrupt */
-    hrtc->Instance->TAMPCR &= (uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP2);
-  }
-  if ((Tamper & RTC_TAMPER_3) != 0)
-  {
-    /* Disable the Tamper2 interrupt */
-    hrtc->Instance->TAMPCR &= (uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP3);
-  }
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles TimeStamp interrupt request.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval None
-  */
-void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
-{
-  if(__HAL_RTC_TIMESTAMP_GET_IT(hrtc, RTC_IT_TS))
-  {
-    /* Get the status of the Interrupt */
-    if((uint32_t)(hrtc->Instance->CR & RTC_IT_TS) != (uint32_t)RESET)
-    {
-       /* TIMESTAMP callback */
-        HAL_RTCEx_TimeStampEventCallback(hrtc);
-
-      /* Clear the TIMESTAMP interrupt pending bit */
-      __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc,RTC_FLAG_TSF);
-    }
-  }
-
-  /* Get the status of the Interrupt */
-  if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== SET)
-  {
-    /* Get the TAMPER Interrupt enable bit and pending bit */
-    if((((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMPIE)) != (uint32_t)RESET) || \
-       (((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMP1IE)) != (uint32_t)RESET))
-    {
-      /* Tamper callback */
-      HAL_RTCEx_Tamper1EventCallback(hrtc);
-
-      /* Clear the Tamper interrupt pending bit */
-      __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
-    }
-  }
-
-  /* Get the status of the Interrupt */
-  if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F)== SET)
-  {
-    /* Get the TAMPER Interrupt enable bit and pending bit */
-    if((((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMPIE)) != (uint32_t)RESET) || \
-       (((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMP2IE)) != (uint32_t)RESET))
-    {
-      /* Tamper callback */
-      HAL_RTCEx_Tamper2EventCallback(hrtc);
-
-      /* Clear the Tamper interrupt pending bit */
-      __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
-    }
-  }
-
-  /* Get the status of the Interrupt */
-  if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F)== SET)
-  {
-    /* Get the TAMPER Interrupt enable bit and pending bit */
-    if((((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMPIE)) != (uint32_t)RESET) || \
-       (((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMP3IE)) != (uint32_t)RESET))
-    {
-      /* Tamper callback */
-      HAL_RTCEx_Tamper3EventCallback(hrtc);
-
-      /* Clear the Tamper interrupt pending bit */
-      __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);
-    }
-  }
-
-  /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */
-  __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-}
-
-/**
-  * @brief  TimeStamp callback.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval None
-  */
-__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_RTC_TimeStampEventCallback could be implemented in the user file
-  */
-}
-
-/**
-  * @brief  Tamper 1 callback.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval None
-  */
-__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_RTC_Tamper1EventCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Tamper 2 callback.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval None
-  */
-__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_RTC_Tamper2EventCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Tamper 3 callback.
-  * @param  hrtc: RTC handle
-  * @retval None
-  */
-__weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  This function handles TimeStamp polling request.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
-  uint32_t tickstart = 0;
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET)
-  {
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET)
-  {
-    /* Clear the TIMESTAMP OverRun Flag */
-    __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
-
-    /* Change TIMESTAMP state */
-    hrtc->State = HAL_RTC_STATE_ERROR;
-
-    return HAL_ERROR;
-   }
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles Tamper1 Polling.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
-  uint32_t tickstart = 0;
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  /* Get the status of the Interrupt */
-  while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== RESET)
-  {
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Clear the Tamper Flag */
-  __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles Tamper2 Polling.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
-  uint32_t tickstart = 0;
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  /* Get the status of the Interrupt */
-  while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == RESET)
-  {
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Clear the Tamper Flag */
-  __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP2F);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles Tamper3 Polling.
-  * @param  hrtc: RTC handle
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
-  uint32_t tickstart = HAL_GetTick();
-
-  /* Get the status of the Interrupt */
-  while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) == RESET)
-  {
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Clear the Tamper Flag */
-  __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP3F);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Group2 RTC Wake-up functions
- *  @brief   RTC Wake-up functions
- *
-@verbatim
- ===============================================================================
-                        ##### RTC Wake-up functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure Wake-up feature
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Sets wake up timer.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  WakeUpCounter: Wake up counter
-  * @param  WakeUpClock: Wake up clock
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
-{
-  uint32_t tickstart = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
-  assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
-  if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)
-  {
-    /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
-    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Clear the Wakeup Timer clock source bits in CR register */
-  hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
-
-  /* Configure the clock source */
-  hrtc->Instance->CR |= (uint32_t)WakeUpClock;
-
-  /* Configure the Wakeup Timer counter */
-  hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
-
-   /* Enable the Wakeup Timer */
-  __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Sets wake up timer with interrupt
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  WakeUpCounter: Wake up counter
-  * @param  WakeUpClock: Wake up clock
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
-{
-  uint32_t tickstart = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
-  assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-    /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
-  if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)
-  {
-    /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
-    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Configure the Wakeup Timer counter */
-  hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
-
-  /* Clear the Wakeup Timer clock source bits in CR register */
-  hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
-
-  /* Configure the clock source */
-  hrtc->Instance->CR |= (uint32_t)WakeUpClock;
-
-  /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
-  __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
-
-  EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT;
-
-  /* Clear RTC Wake Up timer Flag */
-  __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
-
-  /* Configure the Interrupt in the RTC_CR register */
-  __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT);
-
-  /* Enable the Wakeup Timer */
-  __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deactivates wake up timer counter.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval HAL status
-  */
-uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
-{
-  uint32_t tickstart = 0;
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Disable the Wakeup Timer */
-  __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
-
-  /* In case of interrupt mode is used, the interrupt source must disabled */
-  __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT);
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
-  while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
-  {
-    if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-    {
-      /* Enable the write protection for RTC registers */
-      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-      hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hrtc);
-
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Gets wake up timer counter.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval Counter value
-  */
-uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
-{
-  /* Get the counter value */
-  return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT));
-}
-
-/**
-  * @brief  This function handles Wake Up Timer interrupt request.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval None
-  */
-void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
-{
-  if(__HAL_RTC_WAKEUPTIMER_GET_IT(hrtc, RTC_IT_WUT))
-  {
-    /* Get the status of the Interrupt */
-    if((uint32_t)(hrtc->Instance->CR & RTC_IT_WUT) != (uint32_t)RESET)
-    {
-      /* WAKEUPTIMER callback */
-      HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
-
-      /* Clear the WAKEUPTIMER interrupt pending bit */
-      __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
-    }
-  }
-
-  /* Clear the EXTI's line Flag for RTC WakeUpTimer */
-  __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-}
-
-/**
-  * @brief  Wake Up Timer callback.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval None
-  */
-__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_RTC_WakeUpTimerEventCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  This function handles Wake Up Timer Polling.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
-  uint32_t tickstart = 0;
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET)
-  {
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Clear the WAKEUPTIMER Flag */
-  __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-
-/** @defgroup RTCEx_Group3 Extension Peripheral Control functions
- *  @brief   Extension Peripheral Control functions
- *
-@verbatim
- ===============================================================================
-              ##### Extension Peripheral Control functions #####
- ===============================================================================
-    [..]
-    This subsection provides functions allowing to
-      (+) Write a data in a specified RTC Backup data register
-      (+) Read a data in a specified RTC Backup data register
-      (+) Set the Coarse calibration parameters.
-      (+) Deactivate the Coarse calibration parameters
-      (+) Set the Smooth calibration parameters.
-      (+) Configure the Synchronization Shift Control Settings.
-      (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
-      (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
-      (+) Enable the RTC reference clock detection.
-      (+) Disable the RTC reference clock detection.
-      (+) Enable the Bypass Shadow feature.
-      (+) Disable the Bypass Shadow feature.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Writes a data in a specified RTC Backup data register.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  BackupRegister: RTC Backup data Register number.
-  *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
-  *                                 specify the register.
-  * @param  Data: Data to be written in the specified RTC Backup data register.
-  * @retval None
-  */
-void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
-{
-  uint32_t tmp = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_BKP(BackupRegister));
-
-  tmp = (uint32_t)&(hrtc->Instance->BKP0R);
-  tmp += (BackupRegister * 4);
-
-  /* Write the specified register */
-  *(__IO uint32_t *)tmp = (uint32_t)Data;
-}
-
-/**
-  * @brief  Reads data from the specified RTC Backup data Register.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  BackupRegister: RTC Backup data Register number.
-  *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
-  *                                 specify the register.
-  * @retval Read value
-  */
-uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
-{
-  uint32_t tmp = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_BKP(BackupRegister));
-
-  tmp = (uint32_t)&(hrtc->Instance->BKP0R);
-  tmp += (BackupRegister * 4);
-
-  /* Read the specified register */
-  return (*(__IO uint32_t *)tmp);
-}
-
-/**
-  * @brief  Sets the Smooth calibration parameters.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  SmoothCalibPeriod: Select the Smooth Calibration Period.
-  *          This parameter can be can be one of the following values :
-  *             @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
-  *             @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
-  *             @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
-  * @param  SmoothCalibPlusPulses: Select to Set or reset the CALP bit.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulses every 2*11 pulses.
-  *             @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
-  * @param  SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits.
-  *          This parameter can be one any value from 0 to 0x000001FF.
-  * @note   To deactivate the smooth calibration, the field SmoothCalibPlusPulses
-  *         must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field
-  *         SmouthCalibMinusPulsesValue must be equal to 0.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue)
-{
-  uint32_t tickstart = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod));
-  assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses));
-  assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmouthCalibMinusPulsesValue));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* check if a calibration is pending*/
-  if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
-  {
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-    /* check if a calibration is pending*/
-    while((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        /* Change RTC state */
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Configure the Smooth calibration settings */
-  hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmouthCalibMinusPulsesValue);
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the Synchronization Shift Control Settings.
-  * @note   When REFCKON is set, firmware must not write to Shift control register.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  ShiftAdd1S: Select to add or not 1 second to the time calendar.
-  *          This parameter can be one of the following values :
-  *             @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar.
-  *             @arg RTC_SHIFTADD1S_RESET: No effect.
-  * @param  ShiftSubFS: Select the number of Second Fractions to substitute.
-  *          This parameter can be one any value from 0 to 0x7FFF.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
-{
-  uint32_t tickstart = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S));
-  assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-    /* Wait until the shift is completed*/
-    while((hrtc->Instance->ISR & RTC_ISR_SHPF) != RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Check if the reference clock detection is disabled */
-    if((hrtc->Instance->CR & RTC_CR_REFCKON) == RESET)
-    {
-      /* Configure the Shift settings */
-      hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S);
-
-      /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
-      if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
-      {
-        if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
-        {
-          /* Enable the write protection for RTC registers */
-          __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-          hrtc->State = HAL_RTC_STATE_ERROR;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hrtc);
-
-          return HAL_ERROR;
-        }
-      }
-    }
-    else
-    {
-      /* Enable the write protection for RTC registers */
-      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-      /* Change RTC state */
-      hrtc->State = HAL_RTC_STATE_ERROR;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hrtc);
-
-      return HAL_ERROR;
-    }
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  CalibOutput: Select the Calibration output Selection .
-  *          This parameter can be one of the following values:
-  *             @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
-  *             @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32_t CalibOutput)
-{
-  /* Check the parameters */
-  assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Clear flags before config */
-  hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL;
-
-  /* Configure the RTC_CR register */
-  hrtc->Instance->CR |= (uint32_t)CalibOutput;
-
-  __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc);
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc)
-{
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc);
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enables the RTC reference clock detection.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc)
-{
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Set Initialization mode */
-  if(RTC_EnterInitMode(hrtc) != HAL_OK)
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-    /* Set RTC state*/
-    hrtc->State = HAL_RTC_STATE_ERROR;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hrtc);
-
-    return HAL_ERROR;
-  }
-  else
-  {
-    __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc);
-
-    /* Exit Initialization mode */
-    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
-  }
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-   /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disable the RTC reference clock detection.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc)
-{
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Set Initialization mode */
-  if(RTC_EnterInitMode(hrtc) != HAL_OK)
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-    /* Set RTC state*/
-    hrtc->State = HAL_RTC_STATE_ERROR;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hrtc);
-
-    return HAL_ERROR;
-  }
-  else
-  {
-    __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc);
-
-    /* Exit Initialization mode */
-    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
-  }
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enables the Bypass Shadow feature.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @note   When the Bypass Shadow is enabled the calendar value are taken
-  *         directly from the Calendar counter.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc)
-{
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Set the BYPSHAD bit */
-  hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD;
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disables the Bypass Shadow feature.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @note   When the Bypass Shadow is enabled the calendar value are taken
-  *         directly from the Calendar counter.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc)
-{
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Reset the BYPSHAD bit */
-  hrtc->Instance->CR &= (uint8_t)~RTC_CR_BYPSHAD;
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-  /** @defgroup RTCEx_Group4 Extended features functions
- *  @brief    Extended features functions
- *
-@verbatim
- ===============================================================================
-                 ##### Extended features functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) RTC Alram B callback
-      (+) RTC Poll for Alarm B request
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Alarm B callback.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval None
-  */
-__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_RTC_AlarmBEventCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  This function handles AlarmB Polling request.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
-  uint32_t tickstart = 0;
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == RESET)
-  {
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Clear the Alarm Flag */
-  __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_RTC_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_sd.c b/stmhal/hal/f7/src/stm32f7xx_hal_sd.c
deleted file mode 100644
index 4fd6a3f2e9..0000000000
--- a/stmhal/hal/f7/src/stm32f7xx_hal_sd.c
+++ /dev/null
@@ -1,3428 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_sd.c
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   SD card HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Secure Digital (SD) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions
-  *           + Peripheral State functions
-  *
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-  [..]
-    This driver implements a high level communication layer for read and write from/to
-    this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by
-    the user in HAL_SD_MspInit() function (MSP layer).
-    Basically, the MSP layer configuration should be the same as we provide in the
-    examples.
-    You can easily tailor this configuration according to hardware resources.
-
-  [..]
-    This driver is a generic layered driver for SDMMC memories which uses the HAL
-    SDMMC driver functions to interface with SD and uSD cards devices.
-    It is used as follows:
-
-    (#)Initialize the SDMMC low level resources by implement the HAL_SD_MspInit() API:
-        (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE();
-        (##) SDMMC pins configuration for SD card
-            (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
-            (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init()
-                  and according to your pin assignment;
-        (##) DMA Configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA()
-             and HAL_SD_WriteBlocks_DMA() APIs).
-            (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE();
-            (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled.
-        (##) NVIC configuration if you need to use interrupt process when using DMA transfer.
-            (+++) Configure the SDMMC and DMA interrupt priorities using functions
-                  HAL_NVIC_SetPriority(); DMA priority is superior to SDMMC's priority
-            (+++) Enable the NVIC DMA and SDMMC IRQs using function HAL_NVIC_EnableIRQ()
-            (+++) SDMMC interrupts are managed using the macros __HAL_SD_SDMMC_ENABLE_IT()
-                  and __HAL_SD_SDMMC_DISABLE_IT() inside the communication process.
-            (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SD_SDMMC_GET_IT()
-                  and __HAL_SD_SDMMC_CLEAR_IT()
-    (#) At this stage, you can perform SD read/write/erase operations after SD card initialization
-
-
-  *** SD Card Initialization and configuration ***
-  ================================================
-  [..]
-    To initialize the SD Card, use the HAL_SD_Init() function.  It Initializes
-    the SD Card and put it into StandBy State (Ready for data transfer).
-    This function provide the following operations:
-
-    (#) Apply the SD Card initialization process at 400KHz and check the SD Card
-        type (Standard Capacity or High Capacity). You can change or adapt this
-        frequency by adjusting the "ClockDiv" field.
-        The SD Card frequency (SDMMC_CK) is computed as follows:
-
-           SDMMC_CK = SDMMCCLK / (ClockDiv + 2)
-
-        In initialization mode and according to the SD Card standard,
-        make sure that the SDMMC_CK frequency doesn't exceed 400KHz.
-
-    (#) Get the SD CID and CSD data. All these information are managed by the SDCardInfo
-        structure. This structure provide also ready computed SD Card capacity
-        and Block size.
-
-        -@- These information are stored in SD handle structure in case of future use.
-
-    (#) Configure the SD Card Data transfer frequency. By Default, the card transfer
-        frequency is set to 24MHz. You can change or adapt this frequency by adjusting
-        the "ClockDiv" field.
-        In transfer mode and according to the SD Card standard, make sure that the
-        SDMMC_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch.
-        To be able to use a frequency higher than 24MHz, you should use the SDMMC
-        peripheral in bypass mode. Refer to the corresponding reference manual
-        for more details.
-
-    (#) Select the corresponding SD Card according to the address read with the step 2.
-
-    (#) Configure the SD Card in wide bus mode: 4-bits data.
-
-  *** SD Card Read operation ***
-  ==============================
-  [..]
-    (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks().
-        This function support only 512-bytes block length (the block size should be
-        chosen as 512 bytes).
-        You can choose either one block read operation or multiple block read operation
-        by adjusting the "NumberOfBlocks" parameter.
-
-    (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().
-        This function support only 512-bytes block length (the block size should be
-        chosen as 512 bytes).
-        You can choose either one block read operation or multiple block read operation
-        by adjusting the "NumberOfBlocks" parameter.
-        After this, you have to call the function HAL_SD_CheckReadOperation(), to insure
-        that the read transfer is done correctly in both DMA and SD sides.
-
-  *** SD Card Write operation ***
-  ===============================
-  [..]
-    (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks().
-        This function support only 512-bytes block length (the block size should be
-        chosen as 512 bytes).
-        You can choose either one block read operation or multiple block read operation
-        by adjusting the "NumberOfBlocks" parameter.
-
-    (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().
-        This function support only 512-bytes block length (the block size should be
-        chosen as 512 byte).
-        You can choose either one block read operation or multiple block read operation
-        by adjusting the "NumberOfBlocks" parameter.
-        After this, you have to call the function HAL_SD_CheckWriteOperation(), to insure
-        that the write transfer is done correctly in both DMA and SD sides.
-
-  *** SD card status ***
-  ======================
-  [..]
-    (+) At any time, you can check the SD Card status and get the SD card state
-        by using the HAL_SD_GetStatus() function. This function checks first if the
-        SD card is still connected and then get the internal SD Card transfer state.
-    (+) You can also get the SD card SD Status register by using the HAL_SD_SendSDStatus()
-        function.
-
-  *** SD HAL driver macros list ***
-  ==================================
-  [..]
-    Below the list of most used macros in SD HAL driver.
-
-    (+) __HAL_SD_SDMMC_ENABLE : Enable the SD device
-    (+) __HAL_SD_SDMMC_DISABLE : Disable the SD device
-    (+) __HAL_SD_SDMMC_DMA_ENABLE: Enable the SDMMC DMA transfer
-    (+) __HAL_SD_SDMMC_DMA_DISABLE: Disable the SDMMC DMA transfer
-    (+) __HAL_SD_SDMMC_ENABLE_IT: Enable the SD device interrupt
-    (+) __HAL_SD_SDMMC_DISABLE_IT: Disable the SD device interrupt
-    (+) __HAL_SD_SDMMC_GET_FLAG:Check whether the specified SD flag is set or not
-    (+) __HAL_SD_SDMMC_CLEAR_FLAG: Clear the SD's pending flags
-
-    (@) You can refer to the SD HAL driver header file for more useful macros
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup SD
-  * @{
-  */
-
-#ifdef HAL_SD_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup SD_Private_Defines
-  * @{
-  */
-/**
-  * @brief  SDMMC Data block size
-  */
-#define DATA_BLOCK_SIZE                  ((uint32_t)(9 << 4))
-/**
-  * @brief  SDMMC Static flags, Timeout, FIFO Address
-  */
-#define SDMMC_STATIC_FLAGS               ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\
-                                                    SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR  |\
-                                                    SDMMC_FLAG_CMDREND  | SDMMC_FLAG_CMDSENT  | SDMMC_FLAG_DATAEND  |\
-                                                    SDMMC_FLAG_DBCKEND))
-
-#define SDMMC_CMD0TIMEOUT                ((uint32_t)0x00010000U)
-
-/**
-  * @brief  Mask for errors Card Status R1 (OCR Register)
-  */
-#define SD_OCR_ADDR_OUT_OF_RANGE        ((uint32_t)0x80000000U)
-#define SD_OCR_ADDR_MISALIGNED          ((uint32_t)0x40000000U)
-#define SD_OCR_BLOCK_LEN_ERR            ((uint32_t)0x20000000U)
-#define SD_OCR_ERASE_SEQ_ERR            ((uint32_t)0x10000000U)
-#define SD_OCR_BAD_ERASE_PARAM          ((uint32_t)0x08000000U)
-#define SD_OCR_WRITE_PROT_VIOLATION     ((uint32_t)0x04000000U)
-#define SD_OCR_LOCK_UNLOCK_FAILED       ((uint32_t)0x01000000U)
-#define SD_OCR_COM_CRC_FAILED           ((uint32_t)0x00800000U)
-#define SD_OCR_ILLEGAL_CMD              ((uint32_t)0x00400000U)
-#define SD_OCR_CARD_ECC_FAILED          ((uint32_t)0x00200000U)
-#define SD_OCR_CC_ERROR                 ((uint32_t)0x00100000U)
-#define SD_OCR_GENERAL_UNKNOWN_ERROR    ((uint32_t)0x00080000U)
-#define SD_OCR_STREAM_READ_UNDERRUN     ((uint32_t)0x00040000U)
-#define SD_OCR_STREAM_WRITE_OVERRUN     ((uint32_t)0x00020000U)
-#define SD_OCR_CID_CSD_OVERWRITE        ((uint32_t)0x00010000U)
-#define SD_OCR_WP_ERASE_SKIP            ((uint32_t)0x00008000U)
-#define SD_OCR_CARD_ECC_DISABLED        ((uint32_t)0x00004000U)
-#define SD_OCR_ERASE_RESET              ((uint32_t)0x00002000U)
-#define SD_OCR_AKE_SEQ_ERROR            ((uint32_t)0x00000008U)
-#define SD_OCR_ERRORBITS                ((uint32_t)0xFDFFE008U)
-
-/**
-  * @brief  Masks for R6 Response
-  */
-#define SD_R6_GENERAL_UNKNOWN_ERROR     ((uint32_t)0x00002000U)
-#define SD_R6_ILLEGAL_CMD               ((uint32_t)0x00004000U)
-#define SD_R6_COM_CRC_FAILED            ((uint32_t)0x00008000U)
-
-#define SD_VOLTAGE_WINDOW_SD            ((uint32_t)0x80100000U)
-#define SD_HIGH_CAPACITY                ((uint32_t)0x40000000U)
-#define SD_STD_CAPACITY                 ((uint32_t)0x00000000U)
-#define SD_CHECK_PATTERN                ((uint32_t)0x000001AAU)
-
-#define SD_MAX_VOLT_TRIAL               ((uint32_t)0x0000FFFFU)
-#define SD_ALLZERO                      ((uint32_t)0x00000000U)
-
-#define SD_WIDE_BUS_SUPPORT             ((uint32_t)0x00040000U)
-#define SD_SINGLE_BUS_SUPPORT           ((uint32_t)0x00010000U)
-#define SD_CARD_LOCKED                  ((uint32_t)0x02000000U)
-
-#define SD_DATATIMEOUT                  ((uint32_t)0xFFFFFFFFU)
-#define SD_0TO7BITS                     ((uint32_t)0x000000FFU)
-#define SD_8TO15BITS                    ((uint32_t)0x0000FF00U)
-#define SD_16TO23BITS                   ((uint32_t)0x00FF0000U)
-#define SD_24TO31BITS                   ((uint32_t)0xFF000000U)
-#define SD_MAX_DATA_LENGTH              ((uint32_t)0x01FFFFFFU)
-
-#define SD_HALFFIFO                     ((uint32_t)0x00000008U)
-#define SD_HALFFIFOBYTES                ((uint32_t)0x00000020U)
-
-/**
-  * @brief  Command Class Supported
-  */
-#define SD_CCCC_LOCK_UNLOCK             ((uint32_t)0x00000080U)
-#define SD_CCCC_WRITE_PROT              ((uint32_t)0x00000040U)
-#define SD_CCCC_ERASE                   ((uint32_t)0x00000020U)
-
-/**
-  * @brief  Following commands are SD Card Specific commands.
-  *         SDMMC_APP_CMD should be sent before sending these commands.
-  */
-#define SD_SDMMC_SEND_IF_COND            ((uint32_t)SD_CMD_HS_SEND_EXT_CSD)
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup SD_Private_Functions SD Private Functions
-  * @{
-  */
-static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t addr);
-static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_PowerOFF(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus);
-static HAL_SD_CardStateTypedef SD_GetState(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *pStatus);
-static HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD);
-static HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA);
-static HAL_SD_ErrorTypedef SD_WideBus_Enable(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_WideBus_Disable(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR);
-static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma);
-static void SD_DMA_RxError(DMA_HandleTypeDef *hdma);
-static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma);
-static void SD_DMA_TxError(DMA_HandleTypeDef *hdma);
-/**
-  * @}
-  */
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SD_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup SD_Exported_Functions_Group1
- *  @brief   Initialization and de-initialization functions
- *
-@verbatim
-  ==============================================================================
-          ##### Initialization and de-initialization functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to initialize/de-initialize the SD
-    card device to be ready for use.
-
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the SD card according to the specified parameters in the
-            SD_HandleTypeDef and create the associated handle.
-  * @param  hsd: SD handle
-  * @param  SDCardInfo: HAL_SD_CardInfoTypedef structure for SD card information
-  * @retval HAL SD error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo)
-{
-  __IO HAL_SD_ErrorTypedef errorstate = SD_OK;
-  SD_InitTypeDef tmpinit;
-
-  /* Allocate lock resource and initialize it */
-  hsd->Lock = HAL_UNLOCKED;
-
-  /* Initialize the low level hardware (MSP) */
-  HAL_SD_MspInit(hsd);
-
-  /* Default SDMMC peripheral configuration for SD card initialization */
-  tmpinit.ClockEdge           = SDMMC_CLOCK_EDGE_RISING;
-  tmpinit.ClockBypass         = SDMMC_CLOCK_BYPASS_DISABLE;
-  tmpinit.ClockPowerSave      = SDMMC_CLOCK_POWER_SAVE_DISABLE;
-  tmpinit.BusWide             = SDMMC_BUS_WIDE_1B;
-  tmpinit.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
-  tmpinit.ClockDiv            = SDMMC_INIT_CLK_DIV;
-
-  /* Initialize SDMMC peripheral interface with default configuration */
-  SDMMC_Init(hsd->Instance, tmpinit);
-
-  /* Identify card operating voltage */
-  errorstate = SD_PowerON(hsd);
-
-  if(errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-
-  /* Initialize the present SDMMC card(s) and put them in idle state */
-  errorstate = SD_Initialize_Cards(hsd);
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-
-  /* Read CSD/CID MSD registers */
-  errorstate = HAL_SD_Get_CardInfo(hsd, SDCardInfo);
-
-  if (errorstate == SD_OK)
-  {
-    /* Select the Card */
-    errorstate = SD_Select_Deselect(hsd, (uint32_t)(((uint32_t)SDCardInfo->RCA) << 16));
-  }
-
-  /* Configure SDMMC peripheral interface */
-  SDMMC_Init(hsd->Instance, hsd->Init);
-
-  return errorstate;
-}
-
-/**
-  * @brief  De-Initializes the SD card.
-  * @param  hsd: SD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)
-{
-
-  /* Set SD power state to off */
-  SD_PowerOFF(hsd);
-
-  /* De-Initialize the MSP layer */
-  HAL_SD_MspDeInit(hsd);
-
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  Initializes the SD MSP.
-  * @param  hsd: SD handle
-  * @retval None
-  */
-__weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsd);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SD_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  De-Initialize SD MSP.
-  * @param  hsd: SD handle
-  * @retval None
-  */
-__weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsd);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SD_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup SD_Exported_Functions_Group2
- *  @brief   Data transfer functions
- *
-@verbatim
-  ==============================================================================
-                        ##### IO operation functions #####
-  ==============================================================================
-  [..]
-    This subsection provides a set of functions allowing to manage the data
-    transfer from/to SD card.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Reads block(s) from a specified address in a card. The Data transfer
-  *         is managed by polling mode.
-  * @param  hsd: SD handle
-  * @param  pReadBuffer: pointer to the buffer that will contain the received data
-  * @param  BlockNumber: Block number from where data is to be read (byte address = BlockNumber * BlockSize)
-  * @param  BlockSize: SD card Data block size
-  *   @note BlockSize must be 512 bytes.
-  * @param  NumberOfBlocks: Number of SD blocks to read
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_BlockNumber(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint32_t BlockNumber, uint32_t BlockSize, uint32_t NumberOfBlocks)
-{
-  SDMMC_CmdInitTypeDef  sdmmc_cmdinitstructure;
-  SDMMC_DataInitTypeDef sdmmc_datainitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t count = 0, *tempbuff = (uint32_t *)pReadBuffer;
-
-  /* Initialize data control register */
-  hsd->Instance->DCTRL = 0;
-
-  uint32_t ReadAddr;
-  if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
-  {
-    BlockSize = 512;
-    ReadAddr = BlockNumber;
-  }
-  else
-  {
-    // should not overflow for standard-capacity cards
-    ReadAddr = BlockNumber * BlockSize;
-  }
-
-  /* Set Block Size for Card */
-  sdmmc_cmdinitstructure.Argument         = (uint32_t) BlockSize;
-  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
-  sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
-  sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
-  sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
-
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-
-  /* Configure the SD DPSM (Data Path State Machine) */
-  sdmmc_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
-  sdmmc_datainitstructure.DataLength    = NumberOfBlocks * BlockSize;
-  sdmmc_datainitstructure.DataBlockSize = DATA_BLOCK_SIZE;
-  sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
-  sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
-  sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;
-  SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);
-
-  if(NumberOfBlocks > 1)
-  {
-    /* Send CMD18 READ_MULT_BLOCK with argument data address */
-    sdmmc_cmdinitstructure.CmdIndex = SD_CMD_READ_MULT_BLOCK;
-  }
-  else
-  {
-    /* Send CMD17 READ_SINGLE_BLOCK */
-    sdmmc_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK;
-  }
-
-  sdmmc_cmdinitstructure.Argument         = ReadAddr;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-
-  /* Read block(s) in polling mode */
-  if(NumberOfBlocks > 1)
-  {
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK);
-
-    if (errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-
-    /* Poll on SDMMC flags */
-    while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
-    {
-      if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
-      {
-        /* Read data from SDMMC Rx FIFO */
-        for (count = 0; count < 8; count++)
-        {
-          *(tempbuff + count) = SDMMC_ReadFIFO(hsd->Instance);
-        }
-
-        tempbuff += 8;
-      }
-    }
-  }
-  else
-  {
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK);
-
-    if (errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-
-    /* In case of single block transfer, no need of stop transfer at all */
-    while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))
-    {
-      if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
-      {
-        /* Read data from SDMMC Rx FIFO */
-        for (count = 0; count < 8; count++)
-        {
-          *(tempbuff + count) = SDMMC_ReadFIFO(hsd->Instance);
-        }
-
-        tempbuff += 8;
-      }
-    }
-  }
-
-  /* Send stop transmission command in case of multiblock read */
-  if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1))
-  {
-    if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) ||\
-      (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
-        (hsd->CardType == HIGH_CAPACITY_SD_CARD))
-    {
-      /* Send stop transmission command */
-      errorstate = HAL_SD_StopTransfer(hsd);
-    }
-  }
-
-  /* Get error state */
-  if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
-  {
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
-
-    errorstate = SD_DATA_TIMEOUT;
-
-    return errorstate;
-  }
-  else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
-  {
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
-
-    errorstate = SD_DATA_CRC_FAIL;
-
-    return errorstate;
-  }
-  else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
-  {
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
-
-    errorstate = SD_RX_OVERRUN;
-
-    return errorstate;
-  }
-  else
-  {
-    /* No error flag set */
-  }
-
-  count = SD_DATATIMEOUT;
-
-  /* Empty FIFO if there is still any data */
-  while ((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) && (count > 0))
-  {
-    *tempbuff = SDMMC_ReadFIFO(hsd->Instance);
-    tempbuff++;
-    count--;
-  }
-
-  /* Clear all the static flags */
-  __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
-
-  return errorstate;
-}
-
-/**
-  * @brief  Allows to write block(s) to a specified address in a card. The Data
-  *         transfer is managed by polling mode.
-  * @param  hsd: SD handle
-  * @param  pWriteBuffer: pointer to the buffer that will contain the data to transmit
-  * @param  BlockNumber: Block number to where data is to be written (byte address = BlockNumber * BlockSize)
-  * @param  BlockSize: SD card Data block size
-  * @note   BlockSize must be 512 bytes.
-  * @param  NumberOfBlocks: Number of SD blocks to write
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_BlockNumber(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint32_t BlockNumber, uint32_t BlockSize, uint32_t NumberOfBlocks)
-{
-  SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
-  SDMMC_DataInitTypeDef sdmmc_datainitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t totalnumberofbytes = 0, bytestransferred = 0, count = 0, restwords = 0;
-  uint32_t *tempbuff = (uint32_t *)pWriteBuffer;
-  uint8_t cardstate  = 0;
-
-  /* Initialize data control register */
-  hsd->Instance->DCTRL = 0;
-
-  uint32_t WriteAddr;
-  if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
-  {
-    BlockSize = 512;
-    WriteAddr = BlockNumber;
-  }
-  else
-  {
-    // should not overflow for standard-capacity cards
-    WriteAddr = BlockNumber * BlockSize;
-  }
-
-  /* Set Block Size for Card */
-  sdmmc_cmdinitstructure.Argument         = (uint32_t)BlockSize;
-  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
-  sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
-  sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
-  sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
-
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-
-  if(NumberOfBlocks > 1)
-  {
-    /* Send CMD25 WRITE_MULT_BLOCK with argument data address */
-    sdmmc_cmdinitstructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK;
-  }
-  else
-  {
-    /* Send CMD24 WRITE_SINGLE_BLOCK */
-    sdmmc_cmdinitstructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK;
-  }
-
-  sdmmc_cmdinitstructure.Argument         = WriteAddr;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-
-  /* Check for error conditions */
-  if(NumberOfBlocks > 1)
-  {
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK);
-  }
-  else
-  {
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK);
-  }
-
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-
-  /* Set total number of bytes to write */
-  totalnumberofbytes = NumberOfBlocks * BlockSize;
-
-  /* Configure the SD DPSM (Data Path State Machine) */
-  sdmmc_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
-  sdmmc_datainitstructure.DataLength    = NumberOfBlocks * BlockSize;
-  sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
-  sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
-  sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
-  sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;
-  SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);
-
-  /* Write block(s) in polling mode */
-  if(NumberOfBlocks > 1)
-  {
-    while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
-    {
-      if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE))
-      {
-        if ((totalnumberofbytes - bytestransferred) < 32)
-        {
-          restwords = ((totalnumberofbytes - bytestransferred) % 4 == 0) ? ((totalnumberofbytes - bytestransferred) / 4) : (( totalnumberofbytes -  bytestransferred) / 4 + 1);
-
-          /* Write data to SDMMC Tx FIFO */
-          for (count = 0; count < restwords; count++)
-          {
-            SDMMC_WriteFIFO(hsd->Instance, tempbuff);
-            tempbuff++;
-            bytestransferred += 4;
-          }
-        }
-        else
-        {
-          /* Write data to SDMMC Tx FIFO */
-          for (count = 0; count < 8; count++)
-          {
-            SDMMC_WriteFIFO(hsd->Instance, (tempbuff + count));
-          }
-
-          tempbuff += 8;
-          bytestransferred += 32;
-        }
-      }
-    }
-  }
-  else
-  {
-    /* In case of single data block transfer no need of stop command at all */
-    while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))
-    {
-      if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE))
-      {
-        if ((totalnumberofbytes - bytestransferred) < 32)
-        {
-          restwords = ((totalnumberofbytes - bytestransferred) % 4 == 0) ? ((totalnumberofbytes - bytestransferred) / 4) : (( totalnumberofbytes -  bytestransferred) / 4 + 1);
-
-          /* Write data to SDMMC Tx FIFO */
-          for (count = 0; count < restwords; count++)
-          {
-            SDMMC_WriteFIFO(hsd->Instance, tempbuff);
-            tempbuff++;
-            bytestransferred += 4;
-          }
-        }
-        else
-        {
-          /* Write data to SDMMC Tx FIFO */
-          for (count = 0; count < 8; count++)
-          {
-            SDMMC_WriteFIFO(hsd->Instance, (tempbuff + count));
-          }
-
-          tempbuff += 8;
-          bytestransferred += 32;
-        }
-      }
-    }
-  }
-
-  /* Send stop transmission command in case of multiblock write */
-  if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1))
-  {
-    if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
-      (hsd->CardType == HIGH_CAPACITY_SD_CARD))
-    {
-      /* Send stop transmission command */
-      errorstate = HAL_SD_StopTransfer(hsd);
-    }
-  }
-
-  /* Get error state */
-  if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
-  {
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
-
-    errorstate = SD_DATA_TIMEOUT;
-
-    return errorstate;
-  }
-  else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
-  {
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
-
-    errorstate = SD_DATA_CRC_FAIL;
-
-    return errorstate;
-  }
-  else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR))
-  {
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_TXUNDERR);
-
-    errorstate = SD_TX_UNDERRUN;
-
-    return errorstate;
-  }
-  else
-  {
-    /* No error flag set */
-  }
-
-  /* Clear all the static flags */
-  __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
-
-  /* Wait till the card is in programming state */
-  errorstate = SD_IsCardProgramming(hsd, &cardstate);
-
-  while ((errorstate == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING)))
-  {
-    errorstate = SD_IsCardProgramming(hsd, &cardstate);
-  }
-
-  return errorstate;
-}
-
-/**
-  * @brief  Reads block(s) from a specified address in a card. The Data transfer
-  *         is managed by DMA mode.
-  * @note   This API should be followed by the function HAL_SD_CheckReadOperation()
-  *         to check the completion of the read process
-  * @param  hsd: SD handle
-  * @param  pReadBuffer: Pointer to the buffer that will contain the received data
-  * @param  BlockNumber: Block number from where data is to be read (byte address = BlockNumber * BlockSize)
-  * @param  BlockSize: SD card Data block size
-  * @note   BlockSize must be 512 bytes.
-  * @param  NumberOfBlocks: Number of blocks to read.
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_BlockNumber_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint32_t BlockNumber, uint32_t BlockSize, uint32_t NumberOfBlocks)
-{
-  SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
-  SDMMC_DataInitTypeDef sdmmc_datainitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-
-  /* Initialize data control register */
-  hsd->Instance->DCTRL = 0;
-
-  /* Initialize handle flags */
-  hsd->SdTransferCplt  = 0;
-  hsd->DmaTransferCplt = 0;
-  hsd->SdTransferErr   = SD_OK;
-
-  /* Initialize SD Read operation */
-  if(NumberOfBlocks > 1)
-  {
-    hsd->SdOperation = SD_READ_MULTIPLE_BLOCK;
-  }
-  else
-  {
-    hsd->SdOperation = SD_READ_SINGLE_BLOCK;
-  }
-
-  /* Enable transfer interrupts */
-  __HAL_SD_SDMMC_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL |\
-                                 SDMMC_IT_DTIMEOUT |\
-                                 SDMMC_IT_DATAEND  |\
-                                 SDMMC_IT_RXOVERR));
-
-  /* Enable SDMMC DMA transfer */
-  __HAL_SD_SDMMC_DMA_ENABLE(hsd);
-
-  /* Configure DMA user callbacks */
-  hsd->hdmarx->XferCpltCallback  = SD_DMA_RxCplt;
-  hsd->hdmarx->XferErrorCallback = SD_DMA_RxError;
-
-  /* Enable the DMA Channel */
-  HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pReadBuffer, (uint32_t)(BlockSize * NumberOfBlocks)/4);
-
-  uint32_t ReadAddr;
-  if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
-  {
-    BlockSize = 512;
-    ReadAddr = BlockNumber;
-  }
-  else
-  {
-    // should not overflow for standard-capacity cards
-    ReadAddr = BlockNumber * BlockSize;
-
-  }
-
-  /* Set Block Size for Card */
-  sdmmc_cmdinitstructure.Argument         = (uint32_t)BlockSize;
-  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
-  sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
-  sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
-  sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
-
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-
-  /* Configure the SD DPSM (Data Path State Machine) */
-  sdmmc_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
-  sdmmc_datainitstructure.DataLength    = BlockSize * NumberOfBlocks;
-  sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
-  sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
-  sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
-  sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;
-  SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);
-
-  /* Check number of blocks command */
-  if(NumberOfBlocks > 1)
-  {
-    /* Send CMD18 READ_MULT_BLOCK with argument data address */
-    sdmmc_cmdinitstructure.CmdIndex = SD_CMD_READ_MULT_BLOCK;
-  }
-  else
-  {
-    /* Send CMD17 READ_SINGLE_BLOCK */
-    sdmmc_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK;
-  }
-
-  sdmmc_cmdinitstructure.Argument         = ReadAddr;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-
-  /* Check for error conditions */
-  if(NumberOfBlocks > 1)
-  {
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK);
-  }
-  else
-  {
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK);
-  }
-
-  /* Update the SD transfer error in SD handle */
-  hsd->SdTransferErr = errorstate;
-
-  return errorstate;
-}
-
-
-/**
-  * @brief  Writes block(s) to a specified address in a card. The Data transfer
-  *         is managed by DMA mode.
-  * @note   This API should be followed by the function HAL_SD_CheckWriteOperation()
-  *         to check the completion of the write process (by SD current status polling).
-  * @param  hsd: SD handle
-  * @param  pWriteBuffer: pointer to the buffer that will contain the data to transmit
-  * @param  BlockNumber: Block number to where data is to be written (byte address = BlockNumber * BlockSize)
-  * @param  BlockSize: the SD card Data block size
-  * @note   BlockSize must be 512 bytes.
-  * @param  NumberOfBlocks: Number of blocks to write
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_BlockNumber_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint32_t BlockNumber, uint32_t BlockSize, uint32_t NumberOfBlocks)
-{
-  SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
-  SDMMC_DataInitTypeDef sdmmc_datainitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-
-  /* Initialize data control register */
-  hsd->Instance->DCTRL = 0;
-
-  /* Initialize handle flags */
-  hsd->SdTransferCplt  = 0;
-  hsd->DmaTransferCplt = 0;
-  hsd->SdTransferErr   = SD_OK;
-
-  /* Initialize SD Write operation */
-  if(NumberOfBlocks > 1)
-  {
-    hsd->SdOperation = SD_WRITE_MULTIPLE_BLOCK;
-  }
-  else
-  {
-    hsd->SdOperation = SD_WRITE_SINGLE_BLOCK;
-  }
-
-  /* Enable transfer interrupts */
-  __HAL_SD_SDMMC_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL |\
-                                 SDMMC_IT_DTIMEOUT |\
-                                 SDMMC_IT_DATAEND  |\
-                                 SDMMC_IT_TXUNDERR));
-
-  /* Configure DMA user callbacks */
-  hsd->hdmatx->XferCpltCallback  = SD_DMA_TxCplt;
-  hsd->hdmatx->XferErrorCallback = SD_DMA_TxError;
-
-  /* Enable the DMA Channel */
-  HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pWriteBuffer, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BlockSize * NumberOfBlocks)/4);
-
-  /* Enable SDMMC DMA transfer */
-  __HAL_SD_SDMMC_DMA_ENABLE(hsd);
-
-  uint32_t WriteAddr;
-  if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
-  {
-    BlockSize = 512;
-    WriteAddr = BlockNumber;
-  }
-  else
-  {
-    // should not overflow for standard-capacity cards
-    WriteAddr = BlockNumber * BlockSize;
-  }
-
-  /* Set Block Size for Card */
-  sdmmc_cmdinitstructure.Argument         = (uint32_t)BlockSize;
-  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
-  sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
-  sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
-  sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
-
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-
-  /* Check number of blocks command */
-  if(NumberOfBlocks <= 1)
-  {
-    /* Send CMD24 WRITE_SINGLE_BLOCK */
-    sdmmc_cmdinitstructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK;
-  }
-  else
-  {
-    /* Send CMD25 WRITE_MULT_BLOCK with argument data address */
-    sdmmc_cmdinitstructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK;
-  }
-
-  sdmmc_cmdinitstructure.Argument         = (uint32_t)WriteAddr;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-
-  /* Check for error conditions */
-  if(NumberOfBlocks > 1)
-  {
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK);
-  }
-  else
-  {
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK);
-  }
-
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-
-  /* Configure the SD DPSM (Data Path State Machine) */
-  sdmmc_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
-  sdmmc_datainitstructure.DataLength    = BlockSize * NumberOfBlocks;
-  sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
-  sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
-  sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
-  sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;
-  SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);
-
-  hsd->SdTransferErr = errorstate;
-
-  return errorstate;
-}
-
-/**
-  * @brief  This function waits until the SD DMA data read transfer is finished.
-  *         This API should be called after HAL_SD_ReadBlocks_DMA() function
-  *         to insure that all data sent by the card is already transferred by the
-  *         DMA controller.
-  * @param  hsd: SD handle
-  * @param  Timeout: Timeout duration
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t timeout = Timeout;
-  uint32_t tmp1, tmp2;
-  HAL_SD_ErrorTypedef tmp3;
-
-  /* Wait for DMA/SD transfer end or SD error variables to be in SD handle */
-  tmp1 = hsd->DmaTransferCplt;
-  tmp2 = hsd->SdTransferCplt;
-  tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;
-
-  while (((tmp1 & tmp2) == 0) && (tmp3 == SD_OK) && (timeout > 0))
-  {
-    tmp1 = hsd->DmaTransferCplt;
-    tmp2 = hsd->SdTransferCplt;
-    tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;
-    timeout--;
-  }
-
-  timeout = Timeout;
-
-  /* Wait until the Rx transfer is no longer active */
-  while((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXACT)) && (timeout > 0))
-  {
-    timeout--;
-  }
-
-  /* Send stop command in multiblock read */
-  if (hsd->SdOperation == SD_READ_MULTIPLE_BLOCK)
-  {
-    errorstate = HAL_SD_StopTransfer(hsd);
-  }
-
-  if ((timeout == 0) && (errorstate == SD_OK))
-  {
-    errorstate = SD_DATA_TIMEOUT;
-  }
-
-  /* Clear all the static flags */
-  __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
-
-  /* Return error state */
-  if (hsd->SdTransferErr != SD_OK)
-  {
-    return (HAL_SD_ErrorTypedef)(hsd->SdTransferErr);
-  }
-
-  return errorstate;
-}
-
-/**
-  * @brief  This function waits until the SD DMA data write transfer is finished.
-  *         This API should be called after HAL_SD_WriteBlocks_DMA() function
-  *         to insure that all data sent by the card is already transferred by the
-  *         DMA controller.
-  * @param  hsd: SD handle
-  * @param  Timeout: Timeout duration
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t timeout = Timeout;
-  uint32_t tmp1, tmp2;
-  HAL_SD_ErrorTypedef tmp3;
-
-  /* Wait for DMA/SD transfer end or SD error variables to be in SD handle */
-  tmp1 = hsd->DmaTransferCplt;
-  tmp2 = hsd->SdTransferCplt;
-  tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;
-
-  while (((tmp1 & tmp2) == 0) && (tmp3 == SD_OK) && (timeout > 0))
-  {
-    tmp1 = hsd->DmaTransferCplt;
-    tmp2 = hsd->SdTransferCplt;
-    tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;
-    timeout--;
-  }
-
-  timeout = Timeout;
-
-  /* Wait until the Tx transfer is no longer active */
-  while((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXACT))  && (timeout > 0))
-  {
-    timeout--;
-  }
-
-  /* Send stop command in multiblock write */
-  if (hsd->SdOperation == SD_WRITE_MULTIPLE_BLOCK)
-  {
-    errorstate = HAL_SD_StopTransfer(hsd);
-  }
-
-  if ((timeout == 0) && (errorstate == SD_OK))
-  {
-    errorstate = SD_DATA_TIMEOUT;
-  }
-
-  /* Clear all the static flags */
-  __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
-
-  /* Return error state */
-  if (hsd->SdTransferErr != SD_OK)
-  {
-    return (HAL_SD_ErrorTypedef)(hsd->SdTransferErr);
-  }
-
-  /* Wait until write is complete */
-  while(HAL_SD_GetStatus(hsd) != SD_TRANSFER_OK)
-  {
-  }
-
-  return errorstate;
-}
-
-/**
-  * @brief  Erases the specified memory area of the given SD card.
-  * @param  hsd: SD handle
-  * @param  startaddr: Start byte address
-  * @param  endaddr: End byte address
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
-
-  uint32_t delay         = 0;
-  __IO uint32_t maxdelay = 0;
-  uint8_t cardstate      = 0;
-
-  /* Check if the card command class supports erase command */
-  if (((hsd->CSD[1] >> 20) & SD_CCCC_ERASE) == 0)
-  {
-    errorstate = SD_REQUEST_NOT_APPLICABLE;
-
-    return errorstate;
-  }
-
-  /* Get max delay value */
-  maxdelay = 120000 / (((hsd->Instance->CLKCR) & 0xFF) + 2);
-
-  if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
-  {
-    errorstate = SD_LOCK_UNLOCK_FAILED;
-
-    return errorstate;
-  }
-
-  /* Get start and end block for high capacity cards */
-  if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
-  {
-    startaddr /= 512;
-    endaddr   /= 512;
-  }
-
-  /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */
-  if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
-    (hsd->CardType == HIGH_CAPACITY_SD_CARD))
-  {
-    /* Send CMD32 SD_ERASE_GRP_START with argument as addr  */
-    sdmmc_cmdinitstructure.Argument         =(uint32_t)startaddr;
-    sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SD_ERASE_GRP_START;
-    sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
-    sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
-    sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
-    SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_START);
-
-    if (errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-
-    /* Send CMD33 SD_ERASE_GRP_END with argument as addr  */
-    sdmmc_cmdinitstructure.Argument         = (uint32_t)endaddr;
-    sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SD_ERASE_GRP_END;
-    SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_END);
-
-    if (errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-  }
-
-  /* Send CMD38 ERASE */
-  sdmmc_cmdinitstructure.Argument         = 0;
-  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_ERASE;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_ERASE);
-
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-
-  for (; delay < maxdelay; delay++)
-  {
-  }
-
-  /* Wait until the card is in programming state */
-  errorstate = SD_IsCardProgramming(hsd, &cardstate);
-
-  delay = SD_DATATIMEOUT;
-
-  while ((delay > 0) && (errorstate == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING)))
-  {
-    errorstate = SD_IsCardProgramming(hsd, &cardstate);
-    delay--;
-  }
-
-  return errorstate;
-}
-
-/**
-  * @brief  This function handles SD card interrupt request.
-  * @param  hsd: SD handle
-  * @retval None
-  */
-void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
-{
-  /* Check for SDMMC interrupt flags */
-  if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_DATAEND))
-  {
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_IT_DATAEND);
-
-    /* SD transfer is complete */
-    hsd->SdTransferCplt = 1;
-
-    /* No transfer error */
-    hsd->SdTransferErr  = SD_OK;
-
-    HAL_SD_XferCpltCallback(hsd);
-  }
-  else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL))
-  {
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
-
-    hsd->SdTransferErr = SD_DATA_CRC_FAIL;
-
-    HAL_SD_XferErrorCallback(hsd);
-
-  }
-  else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_DTIMEOUT))
-  {
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
-
-    hsd->SdTransferErr = SD_DATA_TIMEOUT;
-
-    HAL_SD_XferErrorCallback(hsd);
-  }
-  else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_RXOVERR))
-  {
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
-
-    hsd->SdTransferErr = SD_RX_OVERRUN;
-
-    HAL_SD_XferErrorCallback(hsd);
-  }
-  else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_TXUNDERR))
-  {
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_TXUNDERR);
-
-    hsd->SdTransferErr = SD_TX_UNDERRUN;
-
-    HAL_SD_XferErrorCallback(hsd);
-  }
-  else
-  {
-    /* No error flag set */
-  }
-
-  /* Disable all SDMMC peripheral interrupt sources */
-  __HAL_SD_SDMMC_DISABLE_IT(hsd, SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_DATAEND  |\
-                                 SDMMC_IT_TXFIFOHE | SDMMC_IT_RXFIFOHF | SDMMC_IT_TXUNDERR |\
-                                 SDMMC_IT_RXOVERR);
-}
-
-
-/**
-  * @brief  SD end of transfer callback.
-  * @param  hsd: SD handle
-  * @retval None
-  */
-__weak void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsd);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SD_XferCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  SD Transfer Error callback.
-  * @param  hsd: SD handle
-  * @retval None
-  */
-__weak void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsd);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SD_XferErrorCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  SD Transfer complete Rx callback in non blocking mode.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-__weak void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdma);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SD_DMA_RxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  SD DMA transfer complete Rx error callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-__weak void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdma);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SD_DMA_RxErrorCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  SD Transfer complete Tx callback in non blocking mode.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-__weak void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdma);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SD_DMA_TxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  SD DMA transfer complete error Tx callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-__weak void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdma);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SD_DMA_TxErrorCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup SD_Exported_Functions_Group3
- *  @brief   management functions
- *
-@verbatim
-  ==============================================================================
-                      ##### Peripheral Control functions #####
-  ==============================================================================
-  [..]
-    This subsection provides a set of functions allowing to control the SD card
-    operations.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Returns information about specific card.
-  * @param  hsd: SD handle
-  * @param  pCardInfo: Pointer to a HAL_SD_CardInfoTypedef structure that
-  *         contains all SD cardinformation
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t tmp = 0;
-
-  pCardInfo->CardType = (uint8_t)(hsd->CardType);
-  pCardInfo->RCA      = (uint16_t)(hsd->RCA);
-
-  /* Byte 0 */
-  tmp = (hsd->CSD[0] & 0xFF000000U) >> 24;
-  pCardInfo->SD_csd.CSDStruct      = (uint8_t)((tmp & 0xC0) >> 6);
-  pCardInfo->SD_csd.SysSpecVersion = (uint8_t)((tmp & 0x3C) >> 2);
-  pCardInfo->SD_csd.Reserved1      = tmp & 0x03;
-
-  /* Byte 1 */
-  tmp = (hsd->CSD[0] & 0x00FF0000) >> 16;
-  pCardInfo->SD_csd.TAAC = (uint8_t)tmp;
-
-  /* Byte 2 */
-  tmp = (hsd->CSD[0] & 0x0000FF00) >> 8;
-  pCardInfo->SD_csd.NSAC = (uint8_t)tmp;
-
-  /* Byte 3 */
-  tmp = hsd->CSD[0] & 0x000000FF;
-  pCardInfo->SD_csd.MaxBusClkFrec = (uint8_t)tmp;
-
-  /* Byte 4 */
-  tmp = (hsd->CSD[1] & 0xFF000000U) >> 24;
-  pCardInfo->SD_csd.CardComdClasses = (uint16_t)(tmp << 4);
-
-  /* Byte 5 */
-  tmp = (hsd->CSD[1] & 0x00FF0000U) >> 16;
-  pCardInfo->SD_csd.CardComdClasses |= (uint16_t)((tmp & 0xF0) >> 4);
-  pCardInfo->SD_csd.RdBlockLen       = (uint8_t)(tmp & 0x0F);
-
-  /* Byte 6 */
-  tmp = (hsd->CSD[1] & 0x0000FF00U) >> 8;
-  pCardInfo->SD_csd.PartBlockRead   = (uint8_t)((tmp & 0x80) >> 7);
-  pCardInfo->SD_csd.WrBlockMisalign = (uint8_t)((tmp & 0x40) >> 6);
-  pCardInfo->SD_csd.RdBlockMisalign = (uint8_t)((tmp & 0x20) >> 5);
-  pCardInfo->SD_csd.DSRImpl         = (uint8_t)((tmp & 0x10) >> 4);
-  pCardInfo->SD_csd.Reserved2       = 0; /*!< Reserved */
-
-  if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0))
-  {
-    pCardInfo->SD_csd.DeviceSize = (tmp & 0x03) << 10;
-
-    /* Byte 7 */
-    tmp = (uint8_t)(hsd->CSD[1] & 0x000000FFU);
-    pCardInfo->SD_csd.DeviceSize |= (tmp) << 2;
-
-    /* Byte 8 */
-    tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000U) >> 24);
-    pCardInfo->SD_csd.DeviceSize |= (tmp & 0xC0) >> 6;
-
-    pCardInfo->SD_csd.MaxRdCurrentVDDMin = (tmp & 0x38) >> 3;
-    pCardInfo->SD_csd.MaxRdCurrentVDDMax = (tmp & 0x07);
-
-    /* Byte 9 */
-    tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000U) >> 16);
-    pCardInfo->SD_csd.MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5;
-    pCardInfo->SD_csd.MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2;
-    pCardInfo->SD_csd.DeviceSizeMul      = (tmp & 0x03) << 1;
-    /* Byte 10 */
-    tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00U) >> 8);
-    pCardInfo->SD_csd.DeviceSizeMul |= (tmp & 0x80) >> 7;
-
-    pCardInfo->CardCapacity  = (pCardInfo->SD_csd.DeviceSize + 1) ;
-    pCardInfo->CardCapacity *= (1 << (pCardInfo->SD_csd.DeviceSizeMul + 2));
-    pCardInfo->CardBlockSize = 1 << (pCardInfo->SD_csd.RdBlockLen);
-    pCardInfo->CardCapacity *= pCardInfo->CardBlockSize;
-  }
-  else if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
-  {
-    /* Byte 7 */
-    tmp = (uint8_t)(hsd->CSD[1] & 0x000000FFU);
-    pCardInfo->SD_csd.DeviceSize = (tmp & 0x3F) << 16;
-
-    /* Byte 8 */
-    tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000U) >> 24);
-
-    pCardInfo->SD_csd.DeviceSize |= (tmp << 8);
-
-    /* Byte 9 */
-    tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000U) >> 16);
-
-    pCardInfo->SD_csd.DeviceSize |= (tmp);
-
-    /* Byte 10 */
-    tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00U) >> 8);
-
-    pCardInfo->CardCapacity = (uint64_t)(((uint64_t)pCardInfo->SD_csd.DeviceSize + 1ULL) * 512 * 1024);
-    pCardInfo->CardBlockSize = 512;
-  }
-  else
-  {
-    /* Not supported card type */
-    errorstate = SD_ERROR;
-  }
-
-  pCardInfo->SD_csd.EraseGrSize = (tmp & 0x40) >> 6;
-  pCardInfo->SD_csd.EraseGrMul  = (tmp & 0x3F) << 1;
-
-  /* Byte 11 */
-  tmp = (uint8_t)(hsd->CSD[2] & 0x000000FF);
-  pCardInfo->SD_csd.EraseGrMul     |= (tmp & 0x80) >> 7;
-  pCardInfo->SD_csd.WrProtectGrSize = (tmp & 0x7F);
-
-  /* Byte 12 */
-  tmp = (uint8_t)((hsd->CSD[3] & 0xFF000000U) >> 24);
-  pCardInfo->SD_csd.WrProtectGrEnable = (tmp & 0x80) >> 7;
-  pCardInfo->SD_csd.ManDeflECC        = (tmp & 0x60) >> 5;
-  pCardInfo->SD_csd.WrSpeedFact       = (tmp & 0x1C) >> 2;
-  pCardInfo->SD_csd.MaxWrBlockLen     = (tmp & 0x03) << 2;
-
-  /* Byte 13 */
-  tmp = (uint8_t)((hsd->CSD[3] & 0x00FF0000) >> 16);
-  pCardInfo->SD_csd.MaxWrBlockLen      |= (tmp & 0xC0) >> 6;
-  pCardInfo->SD_csd.WriteBlockPaPartial = (tmp & 0x20) >> 5;
-  pCardInfo->SD_csd.Reserved3           = 0;
-  pCardInfo->SD_csd.ContentProtectAppli = (tmp & 0x01);
-
-  /* Byte 14 */
-  tmp = (uint8_t)((hsd->CSD[3] & 0x0000FF00) >> 8);
-  pCardInfo->SD_csd.FileFormatGrouop = (tmp & 0x80) >> 7;
-  pCardInfo->SD_csd.CopyFlag         = (tmp & 0x40) >> 6;
-  pCardInfo->SD_csd.PermWrProtect    = (tmp & 0x20) >> 5;
-  pCardInfo->SD_csd.TempWrProtect    = (tmp & 0x10) >> 4;
-  pCardInfo->SD_csd.FileFormat       = (tmp & 0x0C) >> 2;
-  pCardInfo->SD_csd.ECC              = (tmp & 0x03);
-
-  /* Byte 15 */
-  tmp = (uint8_t)(hsd->CSD[3] & 0x000000FF);
-  pCardInfo->SD_csd.CSD_CRC   = (tmp & 0xFE) >> 1;
-  pCardInfo->SD_csd.Reserved4 = 1;
-
-  /* Byte 0 */
-  tmp = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24);
-  pCardInfo->SD_cid.ManufacturerID = tmp;
-
-  /* Byte 1 */
-  tmp = (uint8_t)((hsd->CID[0] & 0x00FF0000) >> 16);
-  pCardInfo->SD_cid.OEM_AppliID = tmp << 8;
-
-  /* Byte 2 */
-  tmp = (uint8_t)((hsd->CID[0] & 0x000000FF00) >> 8);
-  pCardInfo->SD_cid.OEM_AppliID |= tmp;
-
-  /* Byte 3 */
-  tmp = (uint8_t)(hsd->CID[0] & 0x000000FF);
-  pCardInfo->SD_cid.ProdName1 = tmp << 24;
-
-  /* Byte 4 */
-  tmp = (uint8_t)((hsd->CID[1] & 0xFF000000U) >> 24);
-  pCardInfo->SD_cid.ProdName1 |= tmp << 16;
-
-  /* Byte 5 */
-  tmp = (uint8_t)((hsd->CID[1] & 0x00FF0000) >> 16);
-  pCardInfo->SD_cid.ProdName1 |= tmp << 8;
-
-  /* Byte 6 */
-  tmp = (uint8_t)((hsd->CID[1] & 0x0000FF00) >> 8);
-  pCardInfo->SD_cid.ProdName1 |= tmp;
-
-  /* Byte 7 */
-  tmp = (uint8_t)(hsd->CID[1] & 0x000000FF);
-  pCardInfo->SD_cid.ProdName2 = tmp;
-
-  /* Byte 8 */
-  tmp = (uint8_t)((hsd->CID[2] & 0xFF000000U) >> 24);
-  pCardInfo->SD_cid.ProdRev = tmp;
-
-  /* Byte 9 */
-  tmp = (uint8_t)((hsd->CID[2] & 0x00FF0000) >> 16);
-  pCardInfo->SD_cid.ProdSN = tmp << 24;
-
-  /* Byte 10 */
-  tmp = (uint8_t)((hsd->CID[2] & 0x0000FF00) >> 8);
-  pCardInfo->SD_cid.ProdSN |= tmp << 16;
-
-  /* Byte 11 */
-  tmp = (uint8_t)(hsd->CID[2] & 0x000000FF);
-  pCardInfo->SD_cid.ProdSN |= tmp << 8;
-
-  /* Byte 12 */
-  tmp = (uint8_t)((hsd->CID[3] & 0xFF000000U) >> 24);
-  pCardInfo->SD_cid.ProdSN |= tmp;
-
-  /* Byte 13 */
-  tmp = (uint8_t)((hsd->CID[3] & 0x00FF0000) >> 16);
-  pCardInfo->SD_cid.Reserved1   |= (tmp & 0xF0) >> 4;
-  pCardInfo->SD_cid.ManufactDate = (tmp & 0x0F) << 8;
-
-  /* Byte 14 */
-  tmp = (uint8_t)((hsd->CID[3] & 0x0000FF00) >> 8);
-  pCardInfo->SD_cid.ManufactDate |= tmp;
-
-  /* Byte 15 */
-  tmp = (uint8_t)(hsd->CID[3] & 0x000000FF);
-  pCardInfo->SD_cid.CID_CRC   = (tmp & 0xFE) >> 1;
-  pCardInfo->SD_cid.Reserved2 = 1;
-
-  return errorstate;
-}
-
-/**
-  * @brief  Enables wide bus operation for the requested card if supported by
-  *         card.
-  * @param  hsd: SD handle
-  * @param  WideMode: Specifies the SD card wide bus mode
-  *          This parameter can be one of the following values:
-  *            @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer (Only for MMC)
-  *            @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer
-  *            @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  SDMMC_InitTypeDef tmpinit;
-
-  /* MMC Card does not support this feature */
-  if (hsd->CardType == MULTIMEDIA_CARD)
-  {
-    errorstate = SD_UNSUPPORTED_FEATURE;
-
-    return errorstate;
-  }
-  else if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
-    (hsd->CardType == HIGH_CAPACITY_SD_CARD))
-  {
-    if (WideMode == SDMMC_BUS_WIDE_8B)
-    {
-      errorstate = SD_UNSUPPORTED_FEATURE;
-    }
-    else if (WideMode == SDMMC_BUS_WIDE_4B)
-    {
-      errorstate = SD_WideBus_Enable(hsd);
-    }
-    else if (WideMode == SDMMC_BUS_WIDE_1B)
-    {
-      errorstate = SD_WideBus_Disable(hsd);
-    }
-    else
-    {
-      /* WideMode is not a valid argument*/
-      errorstate = SD_INVALID_PARAMETER;
-    }
-
-    if (errorstate == SD_OK)
-    {
-      /* Configure the SDMMC peripheral */
-      tmpinit.ClockEdge           = hsd->Init.ClockEdge;
-      tmpinit.ClockBypass         = hsd->Init.ClockBypass;
-      tmpinit.ClockPowerSave      = hsd->Init.ClockPowerSave;
-      tmpinit.BusWide             = WideMode;
-      tmpinit.HardwareFlowControl = hsd->Init.HardwareFlowControl;
-      tmpinit.ClockDiv            = hsd->Init.ClockDiv;
-      SDMMC_Init(hsd->Instance, tmpinit);
-    }
-  }
-
-  return errorstate;
-}
-
-/**
-  * @brief  Aborts an ongoing data transfer.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd)
-{
-  SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-
-  /* Send CMD12 STOP_TRANSMISSION  */
-  sdmmc_cmdinitstructure.Argument         = 0;
-  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_STOP_TRANSMISSION;
-  sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
-  sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
-  sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_STOP_TRANSMISSION);
-
-  return errorstate;
-}
-
-/**
-  * @brief  Switches the SD card to High Speed mode.
-  *         This API must be used after "Transfer State"
-  * @note   This operation should be followed by the configuration
-  *         of PLL to have SDMMCCK clock between 67 and 75 MHz
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
-  SDMMC_DataInitTypeDef sdmmc_datainitstructure;
-
-  uint8_t SD_hs[64]  = {0};
-  uint32_t SD_scr[2] = {0, 0};
-  uint32_t SD_SPEC   = 0 ;
-  uint32_t count = 0, *tempbuff = (uint32_t *)SD_hs;
-
-  /* Initialize the Data control register */
-  hsd->Instance->DCTRL = 0;
-
-  /* Get SCR Register */
-  errorstate = SD_FindSCR(hsd, SD_scr);
-
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-
-  /* Test the Version supported by the card*/
-  SD_SPEC = (SD_scr[1]  & 0x01000000) | (SD_scr[1]  & 0x02000000);
-
-  if (SD_SPEC != SD_ALLZERO)
-  {
-    /* Set Block Size for Card */
-    sdmmc_cmdinitstructure.Argument         = (uint32_t)64;
-    sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
-    sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
-    sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
-    sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
-    SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
-
-    if (errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-
-    /* Configure the SD DPSM (Data Path State Machine) */
-    sdmmc_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
-    sdmmc_datainitstructure.DataLength    = 64;
-    sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ;
-    sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
-    sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
-    sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;
-    SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);
-
-    /* Send CMD6 switch mode */
-    sdmmc_cmdinitstructure.Argument         = 0x80FFFF01U;
-    sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_HS_SWITCH;
-    SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_HS_SWITCH);
-
-    if (errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-
-    while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))
-    {
-      if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
-      {
-        for (count = 0; count < 8; count++)
-        {
-          *(tempbuff + count) = SDMMC_ReadFIFO(hsd->Instance);
-        }
-
-        tempbuff += 8;
-      }
-    }
-
-    if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
-    {
-      __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
-
-      errorstate = SD_DATA_TIMEOUT;
-
-      return errorstate;
-    }
-    else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
-    {
-      __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
-
-      errorstate = SD_DATA_CRC_FAIL;
-
-      return errorstate;
-    }
-    else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
-    {
-      __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
-
-      errorstate = SD_RX_OVERRUN;
-
-      return errorstate;
-    }
-    else
-    {
-      /* No error flag set */
-    }
-
-    count = SD_DATATIMEOUT;
-
-    while ((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) && (count > 0))
-    {
-      *tempbuff = SDMMC_ReadFIFO(hsd->Instance);
-      tempbuff++;
-      count--;
-    }
-
-    /* Clear all the static flags */
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
-
-    /* Test if the switch mode HS is ok */
-    if ((SD_hs[13]& 2) != 2)
-    {
-      errorstate = SD_UNSUPPORTED_FEATURE;
-    }
-  }
-
-  return errorstate;
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup SD_Exported_Functions_Group4
- *  @brief   Peripheral State functions
- *
-@verbatim
-  ==============================================================================
-                      ##### Peripheral State functions #####
-  ==============================================================================
-  [..]
-    This subsection permits to get in runtime the status of the peripheral
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Returns the current SD card's status.
-  * @param  hsd: SD handle
-  * @param  pSDstatus: Pointer to the buffer that will contain the SD card status
-  *         SD Status register)
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
-{
-  SDMMC_CmdInitTypeDef  sdmmc_cmdinitstructure;
-  SDMMC_DataInitTypeDef sdmmc_datainitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t count = 0;
-
-  /* Check SD response */
-  if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
-  {
-    errorstate = SD_LOCK_UNLOCK_FAILED;
-
-    return errorstate;
-  }
-
-  /* Set block size for card if it is not equal to current block size for card */
-  sdmmc_cmdinitstructure.Argument         = 64;
-  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
-  sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
-  sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
-  sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
-
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-
-  /* Send CMD55 */
-  sdmmc_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16);
-  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
-
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-
-  /* Configure the SD DPSM (Data Path State Machine) */
-  sdmmc_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
-  sdmmc_datainitstructure.DataLength    = 64;
-  sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B;
-  sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
-  sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
-  sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;
-  SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);
-
-  /* Send ACMD13 (SD_APP_STAUS)  with argument as card's RCA */
-  sdmmc_cmdinitstructure.Argument         = 0;
-  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SD_APP_STATUS;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_STATUS);
-
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-
-  /* Get status data */
-  while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))
-  {
-    if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
-    {
-      for (count = 0; count < 8; count++)
-      {
-        *(pSDstatus + count) = SDMMC_ReadFIFO(hsd->Instance);
-      }
-
-      pSDstatus += 8;
-    }
-  }
-
-  if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
-  {
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
-
-    errorstate = SD_DATA_TIMEOUT;
-
-    return errorstate;
-  }
-  else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
-  {
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
-
-    errorstate = SD_DATA_CRC_FAIL;
-
-    return errorstate;
-  }
-  else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
-  {
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
-
-    errorstate = SD_RX_OVERRUN;
-
-    return errorstate;
-  }
-  else
-  {
-    /* No error flag set */
-  }
-
-  count = SD_DATATIMEOUT;
-  while ((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) && (count > 0))
-  {
-    *pSDstatus = SDMMC_ReadFIFO(hsd->Instance);
-    pSDstatus++;
-    count--;
-  }
-
-  /* Clear all the static status flags*/
-  __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
-
-  return errorstate;
-}
-
-/**
-  * @brief  Gets the current sd card data status.
-  * @param  hsd: SD handle
-  * @retval Data Transfer state
-  */
-HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd)
-{
-  HAL_SD_CardStateTypedef cardstate =  SD_CARD_TRANSFER;
-
-  /* Get SD card state */
-  cardstate = SD_GetState(hsd);
-
-  /* Find SD status according to card state*/
-  if (cardstate == SD_CARD_TRANSFER)
-  {
-    return SD_TRANSFER_OK;
-  }
-  else if(cardstate == SD_CARD_ERROR)
-  {
-    return SD_TRANSFER_ERROR;
-  }
-  else
-  {
-    return SD_TRANSFER_BUSY;
-  }
-}
-
-/**
-  * @brief  Gets the SD card status.
-  * @param  hsd: SD handle
-  * @param  pCardStatus: Pointer to the HAL_SD_CardStatusTypedef structure that
-  *         will contain the SD card status information
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t tmp = 0;
-  uint32_t sd_status[16];
-
-  errorstate = HAL_SD_SendSDStatus(hsd, sd_status);
-
-  if (errorstate  != SD_OK)
-  {
-    return errorstate;
-  }
-
-  /* Byte 0 */
-  tmp = (sd_status[0] & 0xC0) >> 6;
-  pCardStatus->DAT_BUS_WIDTH = (uint8_t)tmp;
-
-  /* Byte 0 */
-  tmp = (sd_status[0] & 0x20) >> 5;
-  pCardStatus->SECURED_MODE = (uint8_t)tmp;
-
-  /* Byte 2 */
-  tmp = (sd_status[0] & 0x00FF0000) >> 16;
-  pCardStatus->SD_CARD_TYPE = (uint16_t)(tmp << 8);
-
-  /* Byte 3 */
-  tmp = (sd_status[0] & 0xFF000000) >> 24;
-  pCardStatus->SD_CARD_TYPE |= (uint16_t)tmp;
-
-  /* Byte 4 */
-  tmp = (sd_status[1] & 0xFF);
-  pCardStatus->SIZE_OF_PROTECTED_AREA = (uint32_t)(tmp << 24);
-
-  /* Byte 5 */
-  tmp = (sd_status[1] & 0xFF00) >> 8;
-  pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint32_t)(tmp << 16);
-
-  /* Byte 6 */
-  tmp = (sd_status[1] & 0xFF0000) >> 16;
-  pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint32_t)(tmp << 8);
-
-  /* Byte 7 */
-  tmp = (sd_status[1] & 0xFF000000) >> 24;
-  pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint32_t)tmp;
-
-  /* Byte 8 */
-  tmp = (sd_status[2] & 0xFF);
-  pCardStatus->SPEED_CLASS = (uint8_t)tmp;
-
-  /* Byte 9 */
-  tmp = (sd_status[2] & 0xFF00) >> 8;
-  pCardStatus->PERFORMANCE_MOVE = (uint8_t)tmp;
-
-  /* Byte 10 */
-  tmp = (sd_status[2] & 0xF00000) >> 20;
-  pCardStatus->AU_SIZE = (uint8_t)tmp;
-
-  /* Byte 11 */
-  tmp = (sd_status[2] & 0xFF000000) >> 24;
-  pCardStatus->ERASE_SIZE = (uint16_t)(tmp << 8);
-
-  /* Byte 12 */
-  tmp = (sd_status[3] & 0xFF);
-  pCardStatus->ERASE_SIZE |= (uint16_t)tmp;
-
-  /* Byte 13 */
-  tmp = (sd_status[3] & 0xFC00) >> 10;
-  pCardStatus->ERASE_TIMEOUT = (uint8_t)tmp;
-
-  /* Byte 13 */
-  tmp = (sd_status[3] & 0x0300) >> 8;
-  pCardStatus->ERASE_OFFSET = (uint8_t)tmp;
-
-  return errorstate;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private function ----------------------------------------------------------*/
-/** @addtogroup SD_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  SD DMA transfer complete Rx callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma)
-{
-  SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  /* DMA transfer is complete */
-  hsd->DmaTransferCplt = 1;
-
-  /* Wait until SD transfer is complete */
-  while(hsd->SdTransferCplt == 0)
-  {
-  }
-
-  /* Disable the DMA channel */
-  HAL_DMA_Abort(hdma);
-
-  /* Transfer complete user callback */
-  HAL_SD_DMA_RxCpltCallback(hsd->hdmarx);
-}
-
-/**
-  * @brief  SD DMA transfer Error Rx callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SD_DMA_RxError(DMA_HandleTypeDef *hdma)
-{
-  SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  /* Transfer complete user callback */
-  HAL_SD_DMA_RxErrorCallback(hsd->hdmarx);
-}
-
-/**
-  * @brief  SD DMA transfer complete Tx callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma)
-{
-  SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  /* DMA transfer is complete */
-  hsd->DmaTransferCplt = 1;
-
-  /* Wait until SD transfer is complete */
-  while(hsd->SdTransferCplt == 0)
-  {
-  }
-
-  /* Disable the DMA channel */
-  HAL_DMA_Abort(hdma);
-
-  /* Transfer complete user callback */
-  HAL_SD_DMA_TxCpltCallback(hsd->hdmatx);
-}
-
-/**
-  * @brief  SD DMA transfer Error Tx callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SD_DMA_TxError(DMA_HandleTypeDef *hdma)
-{
-  SD_HandleTypeDef *hsd = ( SD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  /* Transfer complete user callback */
-  HAL_SD_DMA_TxErrorCallback(hsd->hdmatx);
-}
-
-/**
-  * @brief  Returns the SD current state.
-  * @param  hsd: SD handle
-  * @retval SD card current state
-  */
-static HAL_SD_CardStateTypedef SD_GetState(SD_HandleTypeDef *hsd)
-{
-  uint32_t resp1 = 0;
-
-  if (SD_SendStatus(hsd, &resp1) != SD_OK)
-  {
-    return SD_CARD_ERROR;
-  }
-  else
-  {
-    return (HAL_SD_CardStateTypedef)((resp1 >> 9) & 0x0F);
-  }
-}
-
-/**
-  * @brief  Initializes all cards or single card as the case may be Card(s) come
-  *         into standby state.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd)
-{
-  SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint16_t sd_rca = 1;
-
-  if(SDMMC_GetPowerState(hsd->Instance) == 0) /* Power off */
-  {
-    errorstate = SD_REQUEST_NOT_APPLICABLE;
-
-    return errorstate;
-  }
-
-  if(hsd->CardType != SECURE_DIGITAL_IO_CARD)
-  {
-    /* Send CMD2 ALL_SEND_CID */
-    sdmmc_cmdinitstructure.Argument         = 0;
-    sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_ALL_SEND_CID;
-    sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_LONG;
-    sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
-    sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
-    SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-
-    /* Check for error conditions */
-    errorstate = SD_CmdResp2Error(hsd);
-
-    if(errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-
-    /* Get Card identification number data */
-    hsd->CID[0] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
-    hsd->CID[1] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);
-    hsd->CID[2] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);
-    hsd->CID[3] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);
-  }
-
-  if((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1)    || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
-     (hsd->CardType == SECURE_DIGITAL_IO_COMBO_CARD) || (hsd->CardType == HIGH_CAPACITY_SD_CARD))
-  {
-    /* Send CMD3 SET_REL_ADDR with argument 0 */
-    /* SD Card publishes its RCA. */
-    sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SET_REL_ADDR;
-    sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
-    SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-
-    /* Check for error conditions */
-    errorstate = SD_CmdResp6Error(hsd, SD_CMD_SET_REL_ADDR, &sd_rca);
-
-    if(errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-  }
-
-  if (hsd->CardType != SECURE_DIGITAL_IO_CARD)
-  {
-    /* Get the SD card RCA */
-    hsd->RCA = sd_rca;
-
-    /* Send CMD9 SEND_CSD with argument as card's RCA */
-    sdmmc_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16);
-    sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SEND_CSD;
-    sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_LONG;
-    SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-
-    /* Check for error conditions */
-    errorstate = SD_CmdResp2Error(hsd);
-
-    if(errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-
-    /* Get Card Specific Data */
-    hsd->CSD[0] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
-    hsd->CSD[1] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);
-    hsd->CSD[2] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);
-    hsd->CSD[3] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);
-  }
-
-  /* All cards are initialized */
-  return errorstate;
-}
-
-/**
-  * @brief  Selects od Deselects the corresponding card.
-  * @param  hsd: SD handle
-  * @param  addr: Address of the card to be selected
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t addr)
-{
-  SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-
-  /* Send CMD7 SDMMC_SEL_DESEL_CARD */
-  sdmmc_cmdinitstructure.Argument         = (uint32_t)addr;
-  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SEL_DESEL_CARD;
-  sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
-  sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
-  sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SEL_DESEL_CARD);
-
-  return errorstate;
-}
-
-/**
-  * @brief  Enquires cards about their operating voltage and configures clock
-  *         controls and stores SD information that will be needed in future
-  *         in the SD handle.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd)
-{
-  SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
-  __IO HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t response = 0, count = 0, validvoltage = 0;
-  uint32_t sdtype = SD_STD_CAPACITY;
-
-  /* Power ON Sequence -------------------------------------------------------*/
-  /* Disable SDMMC Clock */
-  __HAL_SD_SDMMC_DISABLE(hsd);
-
-  /* Set Power State to ON */
-  SDMMC_PowerState_ON(hsd->Instance);
-
-  /* 1ms: required power up waiting time before starting the SD initialization
-     sequence */
-  HAL_Delay(1);
-
-  /* Enable SDMMC Clock */
-  __HAL_SD_SDMMC_ENABLE(hsd);
-
-  /* CMD0: GO_IDLE_STATE -----------------------------------------------------*/
-  /* No CMD response required */
-  sdmmc_cmdinitstructure.Argument         = 0;
-  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_GO_IDLE_STATE;
-  sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_NO;
-  sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
-  sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-
-  /* Check for error conditions */
-  errorstate = SD_CmdError(hsd);
-
-  if(errorstate != SD_OK)
-  {
-    /* CMD Response Timeout (wait for CMDSENT flag) */
-    return errorstate;
-  }
-
-  /* CMD8: SEND_IF_COND ------------------------------------------------------*/
-  /* Send CMD8 to verify SD card interface operating condition */
-  /* Argument: - [31:12]: Reserved (shall be set to '0')
-  - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V)
-  - [7:0]: Check Pattern (recommended 0xAA) */
-  /* CMD Response: R7 */
-  sdmmc_cmdinitstructure.Argument         = SD_CHECK_PATTERN;
-  sdmmc_cmdinitstructure.CmdIndex         = SD_SDMMC_SEND_IF_COND;
-  sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-
-  /* Check for error conditions */
-  errorstate = SD_CmdResp7Error(hsd);
-
-  if (errorstate == SD_OK)
-  {
-    /* SD Card 2.0 */
-    hsd->CardType = STD_CAPACITY_SD_CARD_V2_0;
-    sdtype        = SD_HIGH_CAPACITY;
-  }
-
-  /* Send CMD55 */
-  sdmmc_cmdinitstructure.Argument         = 0;
-  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
-
-  /* If errorstate is Command Timeout, it is a MMC card */
-  /* If errorstate is SD_OK it is a SD card: SD card 2.0 (voltage range mismatch)
-     or SD card 1.x */
-  if(errorstate == SD_OK)
-  {
-    /* SD CARD */
-    /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
-    while((!validvoltage) && (count < SD_MAX_VOLT_TRIAL))
-    {
-
-      /* SEND CMD55 APP_CMD with RCA as 0 */
-      sdmmc_cmdinitstructure.Argument         = 0;
-      sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
-      sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
-      sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
-      sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
-      SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-
-      /* Check for error conditions */
-      errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
-
-      if(errorstate != SD_OK)
-      {
-        return errorstate;
-      }
-
-      /* Send CMD41 */
-      sdmmc_cmdinitstructure.Argument         = SD_VOLTAGE_WINDOW_SD | sdtype;
-      sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SD_APP_OP_COND;
-      sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
-      sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
-      sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
-      SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-
-      /* Check for error conditions */
-      errorstate = SD_CmdResp3Error(hsd);
-
-      if(errorstate != SD_OK)
-      {
-        return errorstate;
-      }
-
-      /* Get command response */
-      response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
-
-      /* Get operating voltage*/
-      validvoltage = (((response >> 31) == 1) ? 1 : 0);
-
-      count++;
-    }
-
-    if(count >= SD_MAX_VOLT_TRIAL)
-    {
-      errorstate = SD_INVALID_VOLTRANGE;
-
-      return errorstate;
-    }
-
-    if((response & SD_HIGH_CAPACITY) == SD_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */
-    {
-      hsd->CardType = HIGH_CAPACITY_SD_CARD;
-    }
-
-  } /* else MMC Card */
-
-  return errorstate;
-}
-
-/**
-  * @brief  Turns the SDMMC output signals off.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_PowerOFF(SD_HandleTypeDef *hsd)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-
-  /* Set Power State to OFF */
-  SDMMC_PowerState_OFF(hsd->Instance);
-
-  return errorstate;
-}
-
-/**
-  * @brief  Returns the current card's status.
-  * @param  hsd: SD handle
-  * @param  pCardStatus: pointer to the buffer that will contain the SD card
-  *         status (Card Status register)
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
-{
-  SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-
-  if(pCardStatus == NULL)
-  {
-    errorstate = SD_INVALID_PARAMETER;
-
-    return errorstate;
-  }
-
-  /* Send Status command */
-  sdmmc_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16);
-  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SEND_STATUS;
-  sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
-  sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
-  sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SEND_STATUS);
-
-  if(errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-
-  /* Get SD card status */
-  *pCardStatus = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
-
-  return errorstate;
-}
-
-/**
-  * @brief  Checks for error conditions for CMD0.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t timeout, tmp;
-
-  timeout = SDMMC_CMD0TIMEOUT;
-
-  tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CMDSENT);
-
-  while((timeout > 0) && (!tmp))
-  {
-    tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CMDSENT);
-    timeout--;
-  }
-
-  if(timeout == 0)
-  {
-    errorstate = SD_CMD_RSP_TIMEOUT;
-    return errorstate;
-  }
-
-  /* Clear all the static flags */
-  __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
-
-  return errorstate;
-}
-
-/**
-  * @brief  Checks for error conditions for R7 response.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_ERROR;
-  uint32_t timeout = SDMMC_CMD0TIMEOUT, tmp;
-
-  tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT);
-
-  while((!tmp) && (timeout > 0))
-  {
-    tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT);
-    timeout--;
-  }
-
-  tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);
-
-  if((timeout == 0) || tmp)
-  {
-    /* Card is not V2.0 compliant or card does not support the set voltage range */
-    errorstate = SD_CMD_RSP_TIMEOUT;
-
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);
-
-    return errorstate;
-  }
-
-  if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CMDREND))
-  {
-    /* Card is SD V2.0 compliant */
-    errorstate = SD_OK;
-
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CMDREND);
-
-    return errorstate;
-  }
-
-  return errorstate;
-}
-
-/**
-  * @brief  Checks for error conditions for R1 response.
-  * @param  hsd: SD handle
-  * @param  SD_CMD: The sent command index
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t response_r1;
-  while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT))
-  {
-  }
-
-  if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT))
-  {
-    errorstate = SD_CMD_RSP_TIMEOUT;
-
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);
-
-    return errorstate;
-  }
-  else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL))
-  {
-    errorstate = SD_CMD_CRC_FAIL;
-
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CCRCFAIL);
-
-    return errorstate;
-  }
-
-  /* Check response received is of desired command */
-  if(SDMMC_GetCommandResponse(hsd->Instance) != SD_CMD)
-  {
-    errorstate = SD_ILLEGAL_CMD;
-
-    return errorstate;
-  }
-
-  /* Clear all the static flags */
-  __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
-
-  /* We have received response, retrieve it for analysis  */
-  response_r1 = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
-
-  if((response_r1 & SD_OCR_ERRORBITS) == SD_ALLZERO)
-  {
-    return errorstate;
-  }
-
-  if((response_r1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE)
-  {
-    return(SD_ADDR_OUT_OF_RANGE);
-  }
-
-  if((response_r1 & SD_OCR_ADDR_MISALIGNED) == SD_OCR_ADDR_MISALIGNED)
-  {
-    return(SD_ADDR_MISALIGNED);
-  }
-
-  if((response_r1 & SD_OCR_BLOCK_LEN_ERR) == SD_OCR_BLOCK_LEN_ERR)
-  {
-    return(SD_BLOCK_LEN_ERR);
-  }
-
-  if((response_r1 & SD_OCR_ERASE_SEQ_ERR) == SD_OCR_ERASE_SEQ_ERR)
-  {
-    return(SD_ERASE_SEQ_ERR);
-  }
-
-  if((response_r1 & SD_OCR_BAD_ERASE_PARAM) == SD_OCR_BAD_ERASE_PARAM)
-  {
-    return(SD_BAD_ERASE_PARAM);
-  }
-
-  if((response_r1 & SD_OCR_WRITE_PROT_VIOLATION) == SD_OCR_WRITE_PROT_VIOLATION)
-  {
-    return(SD_WRITE_PROT_VIOLATION);
-  }
-
-  if((response_r1 & SD_OCR_LOCK_UNLOCK_FAILED) == SD_OCR_LOCK_UNLOCK_FAILED)
-  {
-    return(SD_LOCK_UNLOCK_FAILED);
-  }
-
-  if((response_r1 & SD_OCR_COM_CRC_FAILED) == SD_OCR_COM_CRC_FAILED)
-  {
-    return(SD_COM_CRC_FAILED);
-  }
-
-  if((response_r1 & SD_OCR_ILLEGAL_CMD) == SD_OCR_ILLEGAL_CMD)
-  {
-    return(SD_ILLEGAL_CMD);
-  }
-
-  if((response_r1 & SD_OCR_CARD_ECC_FAILED) == SD_OCR_CARD_ECC_FAILED)
-  {
-    return(SD_CARD_ECC_FAILED);
-  }
-
-  if((response_r1 & SD_OCR_CC_ERROR) == SD_OCR_CC_ERROR)
-  {
-    return(SD_CC_ERROR);
-  }
-
-  if((response_r1 & SD_OCR_GENERAL_UNKNOWN_ERROR) == SD_OCR_GENERAL_UNKNOWN_ERROR)
-  {
-    return(SD_GENERAL_UNKNOWN_ERROR);
-  }
-
-  if((response_r1 & SD_OCR_STREAM_READ_UNDERRUN) == SD_OCR_STREAM_READ_UNDERRUN)
-  {
-    return(SD_STREAM_READ_UNDERRUN);
-  }
-
-  if((response_r1 & SD_OCR_STREAM_WRITE_OVERRUN) == SD_OCR_STREAM_WRITE_OVERRUN)
-  {
-    return(SD_STREAM_WRITE_OVERRUN);
-  }
-
-  if((response_r1 & SD_OCR_CID_CSD_OVERWRITE) == SD_OCR_CID_CSD_OVERWRITE)
-  {
-    return(SD_CID_CSD_OVERWRITE);
-  }
-
-  if((response_r1 & SD_OCR_WP_ERASE_SKIP) == SD_OCR_WP_ERASE_SKIP)
-  {
-    return(SD_WP_ERASE_SKIP);
-  }
-
-  if((response_r1 & SD_OCR_CARD_ECC_DISABLED) == SD_OCR_CARD_ECC_DISABLED)
-  {
-    return(SD_CARD_ECC_DISABLED);
-  }
-
-  if((response_r1 & SD_OCR_ERASE_RESET) == SD_OCR_ERASE_RESET)
-  {
-    return(SD_ERASE_RESET);
-  }
-
-  if((response_r1 & SD_OCR_AKE_SEQ_ERROR) == SD_OCR_AKE_SEQ_ERROR)
-  {
-    return(SD_AKE_SEQ_ERROR);
-  }
-
-  return errorstate;
-}
-
-/**
-  * @brief  Checks for error conditions for R3 (OCR) response.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-
-  while (!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT))
-  {
-  }
-
-  if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT))
-  {
-    errorstate = SD_CMD_RSP_TIMEOUT;
-
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);
-
-    return errorstate;
-  }
-
-  /* Clear all the static flags */
-  __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
-
-  return errorstate;
-}
-
-/**
-  * @brief  Checks for error conditions for R2 (CID or CSD) response.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-
-  while (!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT))
-  {
-  }
-
-  if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT))
-  {
-    errorstate = SD_CMD_RSP_TIMEOUT;
-
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);
-
-    return errorstate;
-  }
-  else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL))
-  {
-    errorstate = SD_CMD_CRC_FAIL;
-
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CCRCFAIL);
-
-    return errorstate;
-  }
-  else
-  {
-    /* No error flag set */
-  }
-
-  /* Clear all the static flags */
-  __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
-
-  return errorstate;
-}
-
-/**
-  * @brief  Checks for error conditions for R6 (RCA) response.
-  * @param  hsd: SD handle
-  * @param  SD_CMD: The sent command index
-  * @param  pRCA: Pointer to the variable that will contain the SD card relative
-  *         address RCA
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t response_r1;
-
-  while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT))
-  {
-  }
-
-  if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT))
-  {
-    errorstate = SD_CMD_RSP_TIMEOUT;
-
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);
-
-    return errorstate;
-  }
-  else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL))
-  {
-    errorstate = SD_CMD_CRC_FAIL;
-
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CCRCFAIL);
-
-    return errorstate;
-  }
-  else
-  {
-    /* No error flag set */
-  }
-
-  /* Check response received is of desired command */
-  if(SDMMC_GetCommandResponse(hsd->Instance) != SD_CMD)
-  {
-    errorstate = SD_ILLEGAL_CMD;
-
-    return errorstate;
-  }
-
-  /* Clear all the static flags */
-  __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
-
-  /* We have received response, retrieve it.  */
-  response_r1 = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
-
-  if((response_r1 & (SD_R6_GENERAL_UNKNOWN_ERROR | SD_R6_ILLEGAL_CMD | SD_R6_COM_CRC_FAILED)) == SD_ALLZERO)
-  {
-    *pRCA = (uint16_t) (response_r1 >> 16);
-
-    return errorstate;
-  }
-
-  if((response_r1 & SD_R6_GENERAL_UNKNOWN_ERROR) == SD_R6_GENERAL_UNKNOWN_ERROR)
-  {
-    return(SD_GENERAL_UNKNOWN_ERROR);
-  }
-
-  if((response_r1 & SD_R6_ILLEGAL_CMD) == SD_R6_ILLEGAL_CMD)
-  {
-    return(SD_ILLEGAL_CMD);
-  }
-
-  if((response_r1 & SD_R6_COM_CRC_FAILED) == SD_R6_COM_CRC_FAILED)
-  {
-    return(SD_COM_CRC_FAILED);
-  }
-
-  return errorstate;
-}
-
-/**
-  * @brief  Enables the SDMMC wide bus mode.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_WideBus_Enable(SD_HandleTypeDef *hsd)
-{
-  SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-
-  uint32_t scr[2] = {0, 0};
-
-  if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
-  {
-    errorstate = SD_LOCK_UNLOCK_FAILED;
-
-    return errorstate;
-  }
-
-  /* Get SCR Register */
-  errorstate = SD_FindSCR(hsd, scr);
-
-  if(errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-
-  /* If requested card supports wide bus operation */
-  if((scr[1] & SD_WIDE_BUS_SUPPORT) != SD_ALLZERO)
-  {
-    /* Send CMD55 APP_CMD with argument as card's RCA.*/
-    sdmmc_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16);
-    sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
-    sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
-    sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
-    sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
-    SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
-
-    if(errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-
-    /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
-    sdmmc_cmdinitstructure.Argument         = 2;
-    sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_APP_SD_SET_BUSWIDTH;
-    SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH);
-
-    if(errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-
-    return errorstate;
-  }
-  else
-  {
-    errorstate = SD_REQUEST_NOT_APPLICABLE;
-
-    return errorstate;
-  }
-}
-
-/**
-  * @brief  Disables the SDMMC wide bus mode.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_WideBus_Disable(SD_HandleTypeDef *hsd)
-{
-  SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-
-  uint32_t scr[2] = {0, 0};
-
-  if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
-  {
-    errorstate = SD_LOCK_UNLOCK_FAILED;
-
-    return errorstate;
-  }
-
-  /* Get SCR Register */
-  errorstate = SD_FindSCR(hsd, scr);
-
-  if(errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-
-  /* If requested card supports 1 bit mode operation */
-  if((scr[1] & SD_SINGLE_BUS_SUPPORT) != SD_ALLZERO)
-  {
-    /* Send CMD55 APP_CMD with argument as card's RCA */
-    sdmmc_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16);
-    sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
-    sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
-    sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
-    sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
-    SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
-
-    if(errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-
-    /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */
-    sdmmc_cmdinitstructure.Argument         = 0;
-    sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_APP_SD_SET_BUSWIDTH;
-    SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH);
-
-    if(errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-
-    return errorstate;
-  }
-  else
-  {
-    errorstate = SD_REQUEST_NOT_APPLICABLE;
-
-    return errorstate;
-  }
-}
-
-
-/**
-  * @brief  Finds the SD card SCR register value.
-  * @param  hsd: SD handle
-  * @param  pSCR: pointer to the buffer that will contain the SCR value
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
-{
-  SDMMC_CmdInitTypeDef  sdmmc_cmdinitstructure;
-  SDMMC_DataInitTypeDef sdmmc_datainitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t index = 0;
-  uint32_t tempscr[2] = {0, 0};
-
-  /* Set Block Size To 8 Bytes */
-  /* Send CMD55 APP_CMD with argument as card's RCA */
-  sdmmc_cmdinitstructure.Argument         = (uint32_t)8;
-  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
-  sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
-  sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
-  sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
-
-  if(errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-
-  /* Send CMD55 APP_CMD with argument as card's RCA */
-  sdmmc_cmdinitstructure.Argument         = (uint32_t)((hsd->RCA) << 16);
-  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
-
-  if(errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  sdmmc_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
-  sdmmc_datainitstructure.DataLength    = 8;
-  sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_8B;
-  sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
-  sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
-  sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;
-  SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);
-
-  /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */
-  sdmmc_cmdinitstructure.Argument         = 0;
-  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SD_APP_SEND_SCR;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_SEND_SCR);
-
-  if(errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-
-  while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))
-  {
-    if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL))
-    {
-      *(tempscr + index) = SDMMC_ReadFIFO(hsd->Instance);
-      index++;
-    }
-  }
-
-  if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
-  {
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
-
-    errorstate = SD_DATA_TIMEOUT;
-
-    return errorstate;
-  }
-  else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
-  {
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
-
-    errorstate = SD_DATA_CRC_FAIL;
-
-    return errorstate;
-  }
-  else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
-  {
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
-
-    errorstate = SD_RX_OVERRUN;
-
-    return errorstate;
-  }
-  else
-  {
-    /* No error flag set */
-  }
-
-  /* Clear all the static flags */
-  __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
-
-  *(pSCR + 1) = ((tempscr[0] & SD_0TO7BITS) << 24)  | ((tempscr[0] & SD_8TO15BITS) << 8) |\
-    ((tempscr[0] & SD_16TO23BITS) >> 8) | ((tempscr[0] & SD_24TO31BITS) >> 24);
-
-  *(pSCR) = ((tempscr[1] & SD_0TO7BITS) << 24)  | ((tempscr[1] & SD_8TO15BITS) << 8) |\
-    ((tempscr[1] & SD_16TO23BITS) >> 8) | ((tempscr[1] & SD_24TO31BITS) >> 24);
-
-  return errorstate;
-}
-
-/**
-  * @brief  Checks if the SD card is in programming state.
-  * @param  hsd: SD handle
-  * @param  pStatus: pointer to the variable that will contain the SD card state
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *pStatus)
-{
-  SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  __IO uint32_t responseR1 = 0;
-
-  sdmmc_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16);
-  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SEND_STATUS;
-  sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
-  sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
-  sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-
-  while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT))
-  {
-  }
-
-  if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT))
-  {
-    errorstate = SD_CMD_RSP_TIMEOUT;
-
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);
-
-    return errorstate;
-  }
-  else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL))
-  {
-    errorstate = SD_CMD_CRC_FAIL;
-
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CCRCFAIL);
-
-    return errorstate;
-  }
-  else
-  {
-    /* No error flag set */
-  }
-
-  /* Check response received is of desired command */
-  if((uint32_t)SDMMC_GetCommandResponse(hsd->Instance) != SD_CMD_SEND_STATUS)
-  {
-    errorstate = SD_ILLEGAL_CMD;
-
-    return errorstate;
-  }
-
-  /* Clear all the static flags */
-  __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
-
-
-  /* We have received response, retrieve it for analysis */
-  responseR1 = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
-
-  /* Find out card status */
-  *pStatus = (uint8_t)((responseR1 >> 9) & 0x0000000F);
-
-  if((responseR1 & SD_OCR_ERRORBITS) == SD_ALLZERO)
-  {
-    return errorstate;
-  }
-
-  if((responseR1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE)
-  {
-    return(SD_ADDR_OUT_OF_RANGE);
-  }
-
-  if((responseR1 & SD_OCR_ADDR_MISALIGNED) == SD_OCR_ADDR_MISALIGNED)
-  {
-    return(SD_ADDR_MISALIGNED);
-  }
-
-  if((responseR1 & SD_OCR_BLOCK_LEN_ERR) == SD_OCR_BLOCK_LEN_ERR)
-  {
-    return(SD_BLOCK_LEN_ERR);
-  }
-
-  if((responseR1 & SD_OCR_ERASE_SEQ_ERR) == SD_OCR_ERASE_SEQ_ERR)
-  {
-    return(SD_ERASE_SEQ_ERR);
-  }
-
-  if((responseR1 & SD_OCR_BAD_ERASE_PARAM) == SD_OCR_BAD_ERASE_PARAM)
-  {
-    return(SD_BAD_ERASE_PARAM);
-  }
-
-  if((responseR1 & SD_OCR_WRITE_PROT_VIOLATION) == SD_OCR_WRITE_PROT_VIOLATION)
-  {
-    return(SD_WRITE_PROT_VIOLATION);
-  }
-
-  if((responseR1 & SD_OCR_LOCK_UNLOCK_FAILED) == SD_OCR_LOCK_UNLOCK_FAILED)
-  {
-    return(SD_LOCK_UNLOCK_FAILED);
-  }
-
-  if((responseR1 & SD_OCR_COM_CRC_FAILED) == SD_OCR_COM_CRC_FAILED)
-  {
-    return(SD_COM_CRC_FAILED);
-  }
-
-  if((responseR1 & SD_OCR_ILLEGAL_CMD) == SD_OCR_ILLEGAL_CMD)
-  {
-    return(SD_ILLEGAL_CMD);
-  }
-
-  if((responseR1 & SD_OCR_CARD_ECC_FAILED) == SD_OCR_CARD_ECC_FAILED)
-  {
-    return(SD_CARD_ECC_FAILED);
-  }
-
-  if((responseR1 & SD_OCR_CC_ERROR) == SD_OCR_CC_ERROR)
-  {
-    return(SD_CC_ERROR);
-  }
-
-  if((responseR1 & SD_OCR_GENERAL_UNKNOWN_ERROR) == SD_OCR_GENERAL_UNKNOWN_ERROR)
-  {
-    return(SD_GENERAL_UNKNOWN_ERROR);
-  }
-
-  if((responseR1 & SD_OCR_STREAM_READ_UNDERRUN) == SD_OCR_STREAM_READ_UNDERRUN)
-  {
-    return(SD_STREAM_READ_UNDERRUN);
-  }
-
-  if((responseR1 & SD_OCR_STREAM_WRITE_OVERRUN) == SD_OCR_STREAM_WRITE_OVERRUN)
-  {
-    return(SD_STREAM_WRITE_OVERRUN);
-  }
-
-  if((responseR1 & SD_OCR_CID_CSD_OVERWRITE) == SD_OCR_CID_CSD_OVERWRITE)
-  {
-    return(SD_CID_CSD_OVERWRITE);
-  }
-
-  if((responseR1 & SD_OCR_WP_ERASE_SKIP) == SD_OCR_WP_ERASE_SKIP)
-  {
-    return(SD_WP_ERASE_SKIP);
-  }
-
-  if((responseR1 & SD_OCR_CARD_ECC_DISABLED) == SD_OCR_CARD_ECC_DISABLED)
-  {
-    return(SD_CARD_ECC_DISABLED);
-  }
-
-  if((responseR1 & SD_OCR_ERASE_RESET) == SD_OCR_ERASE_RESET)
-  {
-    return(SD_ERASE_RESET);
-  }
-
-  if((responseR1 & SD_OCR_AKE_SEQ_ERROR) == SD_OCR_AKE_SEQ_ERROR)
-  {
-    return(SD_AKE_SEQ_ERROR);
-  }
-
-  return errorstate;
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_SD_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_spi.c b/stmhal/hal/f7/src/stm32f7xx_hal_spi.c
deleted file mode 100644
index 4bb5a48472..0000000000
--- a/stmhal/hal/f7/src/stm32f7xx_hal_spi.c
+++ /dev/null
@@ -1,3694 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_spi.c
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   SPI HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Serial Peripheral Interface (SPI) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions
-  *           + Peripheral State functions
-  *
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-    [..]
-      The SPI HAL driver can be used as follows:
-
-      (#) Declare a SPI_HandleTypeDef handle structure, for example:
-          SPI_HandleTypeDef  hspi;
-
-      (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
-          (##) Enable the SPIx interface clock
-          (##) SPI pins configuration
-              (+++) Enable the clock for the SPI GPIOs
-              (+++) Configure these SPI pins as alternate function push-pull
-          (##) NVIC configuration if you need to use interrupt process
-              (+++) Configure the SPIx interrupt priority
-              (+++) Enable the NVIC SPI IRQ handle
-          (##) DMA Configuration if you need to use DMA process
-              (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
-              (+++) Enable the DMAx clock
-              (+++) Configure the DMA handle parameters
-              (+++) Configure the DMA Tx or Rx Stream/Channel
-              (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
-              (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
-
-      (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
-          management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
-
-      (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
-          (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
-              by calling the customized HAL_SPI_MspInit() API.
-     [..]
-       Circular mode restriction:
-      (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
-          (##) Master 2Lines RxOnly
-          (##) Master 1Line Rx
-      (#) The CRC feature is not managed when the DMA circular mode is enabled
-      (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
-          the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
-     [..]
-       Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,
-       the following table resume the max SPI frequency reached with data size 8bits/16bits,
-       according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance :
-
-       DataSize = SPI_DATASIZE_8BIT:
-       +----------------------------------------------------------------------------------------------+
-       |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |
-       | Process | Tranfert mode  |---------------------|----------------------|----------------------|
-       |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |
-       |==============================================================================================|
-       |    T    |     Polling    | Fpclk/4  | Fpclk/8  |    NA     |    NA    |    NA     |   NA     |
-       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
-       |    /    |     Interrupt  | Fpclk/4  | Fpclk/16 |    NA     |    NA    |    NA     |   NA     |
-       |    R    |----------------|----------|----------|-----------|----------|-----------|----------|
-       |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
-       |=========|================|==========|==========|===========|==========|===========|==========|
-       |         |     Polling    | Fpclk/4  | Fpclk/8  | Fpclk/16  | Fpclk/8  | Fpclk/8   | Fpclk/8  |
-       |         |----------------|----------|----------|-----------|----------|-----------|----------|
-       |    R    |     Interrupt  | Fpclk/8  | Fpclk/16 | Fpclk/8   | Fpclk/8  | Fpclk/8   | Fpclk/4  |
-       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
-       |         |       DMA      | Fpclk/4  | Fpclk/2  | Fpclk/2   | Fpclk/16 | Fpclk/2   | Fpclk/16 |
-       |=========|================|==========|==========|===========|==========|===========|==========|
-       |         |     Polling    | Fpclk/8  | Fpclk/2  |     NA    |    NA    | Fpclk/8   | Fpclk/8  |
-       |         |----------------|----------|----------|-----------|----------|-----------|----------|
-       |    T    |     Interrupt  | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/16  | Fpclk/8  |
-       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
-       |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/8   | Fpclk/16 |
-       +----------------------------------------------------------------------------------------------+
-
-       DataSize = SPI_DATASIZE_16BIT:
-       +----------------------------------------------------------------------------------------------+
-       |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |
-       | Process | Tranfert mode  |---------------------|----------------------|----------------------|
-       |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |
-       |==============================================================================================|
-       |    T    |     Polling    | Fpclk/4  | Fpclk/8  |    NA     |    NA    |    NA     |   NA     |
-       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
-       |    /    |     Interrupt  | Fpclk/4  | Fpclk/16 |    NA     |    NA    |    NA     |   NA     |
-       |    R    |----------------|----------|----------|-----------|----------|-----------|----------|
-       |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
-       |=========|================|==========|==========|===========|==========|===========|==========|
-       |         |     Polling    | Fpclk/4  | Fpclk/8  | Fpclk/16  | Fpclk/8  | Fpclk/8   | Fpclk/8  |
-       |         |----------------|----------|----------|-----------|----------|-----------|----------|
-       |    R    |     Interrupt  | Fpclk/8  | Fpclk/16 | Fpclk/8   | Fpclk/8  | Fpclk/8   | Fpclk/4  |
-       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
-       |         |       DMA      | Fpclk/4  | Fpclk/2  | Fpclk/2   | Fpclk/16 | Fpclk/2   | Fpclk/16 |
-       |=========|================|==========|==========|===========|==========|===========|==========|
-       |         |     Polling    | Fpclk/8  | Fpclk/2  |     NA    |    NA    | Fpclk/8   | Fpclk/8  |
-       |         |----------------|----------|----------|-----------|----------|-----------|----------|
-       |    T    |     Interrupt  | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/16  | Fpclk/8  |
-       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
-       |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/8   | Fpclk/16 |
-       +----------------------------------------------------------------------------------------------+
-       @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
-             SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
-       @note
-            (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
-            (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
-            (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup SPI SPI
-  * @brief SPI HAL module driver
-  * @{
-  */
-#ifdef HAL_SPI_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup SPI_Private_Constants SPI Private Constants
-  * @{
-  */
-#define SPI_DEFAULT_TIMEOUT 100U
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup SPI_Private_Functions SPI Private Functions
-  * @{
-  */
-static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAError(DMA_HandleTypeDef *hdma);
-static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
-static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
-static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State,
-                                                       uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
-                                                       uint32_t Timeout, uint32_t Tickstart);
-static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
-#if (USE_SPI_CRC != 0U)
-static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
-static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
-#endif /* USE_SPI_CRC */
-static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
-static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
-static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
-static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
-static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
-static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup SPI_Exported_Functions SPI Exported Functions
-  * @{
-  */
-
-/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @brief    Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This subsection provides a set of functions allowing to initialize and
-          de-initialize the SPIx peripheral:
-
-      (+) User must implement HAL_SPI_MspInit() function in which he configures
-          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
-
-      (+) Call the function HAL_SPI_Init() to configure the selected device with
-          the selected configuration:
-        (++) Mode
-        (++) Direction
-        (++) Data Size
-        (++) Clock Polarity and Phase
-        (++) NSS Management
-        (++) BaudRate Prescaler
-        (++) FirstBit
-        (++) TIMode
-        (++) CRC Calculation
-        (++) CRC Polynomial if CRC enabled
-        (++) CRC Length, used only with Data8 and Data16
-        (++) FIFO reception threshold
-
-      (+) Call the function HAL_SPI_DeInit() to restore the default configuration
-          of the selected SPIx peripheral.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initialize the SPI according to the specified parameters
-  *         in the SPI_InitTypeDef and initialize the associated handle.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
-{
-  uint32_t frxth;
-
-  /* Check the SPI handle allocation */
-  if (hspi == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
-  assert_param(IS_SPI_MODE(hspi->Init.Mode));
-  assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
-  assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
-  assert_param(IS_SPI_NSS(hspi->Init.NSS));
-  assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
-  assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
-  assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
-  assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
-  if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
-  {
-    assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
-    assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
-  }
-#if (USE_SPI_CRC != 0U)
-  assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
-    assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
-  }
-#else
-  hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
-#endif /* USE_SPI_CRC */
-
-  if (hspi->State == HAL_SPI_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hspi->Lock = HAL_UNLOCKED;
-
-    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
-    HAL_SPI_MspInit(hspi);
-  }
-
-  hspi->State = HAL_SPI_STATE_BUSY;
-
-  /* Disable the selected SPI peripheral */
-  __HAL_SPI_DISABLE(hspi);
-
-  /* Align by default the rs fifo threshold on the data size */
-  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
-  {
-    frxth = SPI_RXFIFO_THRESHOLD_HF;
-  }
-  else
-  {
-    frxth = SPI_RXFIFO_THRESHOLD_QF;
-  }
-
-  /* CRC calculation is valid only for 16Bit and 8 Bit */
-  if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
-  {
-    /* CRC must be disabled */
-    hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
-  }
-
-  /* Align the CRC Length on the data size */
-  if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
-  {
-    /* CRC Length aligned on the data size : value set by default */
-    if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
-    {
-      hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
-    }
-    else
-    {
-      hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
-    }
-  }
-
-  /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
-  /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
-  Communication speed, First bit, CRC calculation state */
-  WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction |
-                                  hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
-                                  hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit  | hspi->Init.CRCCalculation));
-#if (USE_SPI_CRC != 0U)
-  /* Configure : CRC Length */
-  if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
-  {
-    hspi->Instance->CR1 |= SPI_CR1_CRCL;
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Configure : NSS management, TI Mode and Rx Fifo Threshold */
-  WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode |
-                                  hspi->Init.NSSPMode | hspi->Init.DataSize) | frxth);
-
-#if (USE_SPI_CRC != 0U)
-  /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
-  /* Configure : CRC Polynomial */
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
-  }
-#endif /* USE_SPI_CRC */
-
-#if defined(SPI_I2SCFGR_I2SMOD)
-  /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
-  CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
-#endif /* SPI_I2SCFGR_I2SMOD */
-
-  hspi->ErrorCode = HAL_SPI_ERROR_NONE;
-  hspi->State     = HAL_SPI_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  De-Initialize the SPI peripheral.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
-{
-  /* Check the SPI handle allocation */
-  if (hspi == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check SPI Instance parameter */
-  assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
-
-  hspi->State = HAL_SPI_STATE_BUSY;
-
-  /* Disable the SPI Peripheral Clock */
-  __HAL_SPI_DISABLE(hspi);
-
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
-  HAL_SPI_MspDeInit(hspi);
-
-  hspi->ErrorCode = HAL_SPI_ERROR_NONE;
-  hspi->State = HAL_SPI_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hspi);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initialize the SPI MSP.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_MspInit should be implemented in the user file
-   */
-}
-
-/**
-  * @brief  De-Initialize the SPI MSP.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_MspDeInit should be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
- *  @brief   Data transfers functions
- *
-@verbatim
-  ==============================================================================
-                      ##### IO operation functions #####
- ===============================================================================
- [..]
-    This subsection provides a set of functions allowing to manage the SPI
-    data transfers.
-
-    [..] The SPI supports master and slave mode :
-
-    (#) There are two modes of transfer:
-       (++) Blocking mode: The communication is performed in polling mode.
-            The HAL status of all data processing is returned by the same function
-            after finishing transfer.
-       (++) No-Blocking mode: The communication is performed using Interrupts
-            or DMA, These APIs return the HAL status.
-            The end of the data processing will be indicated through the
-            dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
-            using DMA mode.
-            The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
-            will be executed respectively at the end of the transmit or Receive process
-            The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
-
-    (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
-        exist for 1Line (simplex) and 2Lines (full duplex) modes.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Transmit an amount of data in blocking mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pData: pointer to data buffer
-  * @param  Size: amount of data to be sent
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint32_t tickstart = 0U;
-  HAL_StatusTypeDef errorcode = HAL_OK;
-
-  /* Check Direction parameter */
-  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
-
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  /* Init tickstart for timeout management*/
-  tickstart = HAL_GetTick();
-
-  if (hspi->State != HAL_SPI_STATE_READY)
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  if ((pData == NULL) || (Size == 0U))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  /* Set the transaction information */
-  hspi->State       = HAL_SPI_STATE_BUSY_TX;
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pTxBuffPtr  = (uint8_t *)pData;
-  hspi->TxXferSize  = Size;
-  hspi->TxXferCount = Size;
-
-  /*Init field not used in handle to zero */
-  hspi->pRxBuffPtr  = (uint8_t *)NULL;
-  hspi->RxXferSize  = 0U;
-  hspi->RxXferCount = 0U;
-  hspi->TxISR       = NULL;
-  hspi->RxISR       = NULL;
-
-  /* Configure communication direction : 1Line */
-  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
-  {
-    SPI_1LINE_TX(hspi);
-  }
-
-#if (USE_SPI_CRC != 0U)
-  /* Reset CRC Calculation */
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Check if the SPI is already enabled */
-  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-
-  /* Transmit data in 16 Bit mode */
-  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
-  {
-    /* Transmit data in 16 Bit mode */
-    while (hspi->TxXferCount > 0U)
-    {
-      /* Wait until TXE flag is set to send data */
-      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
-      {
-        hspi->Instance->DR = *((uint16_t *)pData);
-        pData += sizeof(uint16_t);
-        hspi->TxXferCount--;
-      }
-      else
-      {
-        /* Timeout management */
-        if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >=  Timeout)))
-        {
-          errorcode = HAL_TIMEOUT;
-          goto error;
-        }
-      }
-    }
-  }
-  /* Transmit data in 8 Bit mode */
-  else
-  {
-    while (hspi->TxXferCount > 0U)
-    {
-      /* Wait until TXE flag is set to send data */
-      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
-      {
-        if (hspi->TxXferCount > 1U)
-        {
-          /* write on the data register in packing mode */
-          hspi->Instance->DR = *((uint16_t *)pData);
-          pData += sizeof(uint16_t);
-          hspi->TxXferCount -= 2U;
-        }
-        else
-        {
-          *((__IO uint8_t *)&hspi->Instance->DR) = (*pData++);
-          hspi->TxXferCount--;
-        }
-      }
-      else
-      {
-        /* Timeout management */
-        if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >=  Timeout)))
-        {
-          errorcode = HAL_TIMEOUT;
-          goto error;
-        }
-      }
-    }
-  }
-#if (USE_SPI_CRC != 0U)
-  /* Enable CRC Transmission */
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Check the end of the transaction */
-  if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
-  {
-    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
-  }
-
-  /* Clear overrun flag in 2 Lines communication mode because received is not read */
-  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
-  {
-    __HAL_SPI_CLEAR_OVRFLAG(hspi);
-  }
-
-  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
-  {
-    errorcode = HAL_ERROR;
-  }
-
-error:
-  hspi->State = HAL_SPI_STATE_READY;
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Receive an amount of data in blocking mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pData: pointer to data buffer
-  * @param  Size: amount of data to be received
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-#if (USE_SPI_CRC != 0U)
-  __IO uint16_t tmpreg = 0U;
-#endif /* USE_SPI_CRC */
-  uint32_t tickstart = 0U;
-  HAL_StatusTypeDef errorcode = HAL_OK;
-
-  if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
-  {
-    hspi->State = HAL_SPI_STATE_BUSY_RX;
-    /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
-    return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
-  }
-
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  /* Init tickstart for timeout management*/
-  tickstart = HAL_GetTick();
-
-  if (hspi->State != HAL_SPI_STATE_READY)
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  if ((pData == NULL) || (Size == 0U))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  /* Set the transaction information */
-  hspi->State       = HAL_SPI_STATE_BUSY_RX;
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pRxBuffPtr  = (uint8_t *)pData;
-  hspi->RxXferSize  = Size;
-  hspi->RxXferCount = Size;
-
-  /*Init field not used in handle to zero */
-  hspi->pTxBuffPtr  = (uint8_t *)NULL;
-  hspi->TxXferSize  = 0U;
-  hspi->TxXferCount = 0U;
-  hspi->RxISR       = NULL;
-  hspi->TxISR       = NULL;
-
-#if (USE_SPI_CRC != 0U)
-  /* Reset CRC Calculation */
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-    /* this is done to handle the CRCNEXT before the latest data */
-    hspi->RxXferCount--;
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Set the Rx Fifo threshold */
-  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
-  {
-    /* set fiforxthreshold according the reception data length: 16bit */
-    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-  }
-  else
-  {
-    /* set fiforxthreshold according the reception data length: 8bit */
-    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-  }
-
-  /* Configure communication direction: 1Line */
-  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
-  {
-    SPI_1LINE_RX(hspi);
-  }
-
-  /* Check if the SPI is already enabled */
-  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-
-  /* Receive data in 8 Bit mode */
-  if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
-  {
-    /* Transfer loop */
-    while (hspi->RxXferCount > 0U)
-    {
-      /* Check the RXNE flag */
-      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
-      {
-        /* read the received data */
-        (*pData) = *(__IO uint8_t *)&hspi->Instance->DR;
-        pData += sizeof(uint8_t);
-        hspi->RxXferCount--;
-      }
-      else
-      {
-        /* Timeout management */
-        if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >=  Timeout)))
-        {
-          errorcode = HAL_TIMEOUT;
-          goto error;
-        }
-      }
-    }
-  }
-  else
-  {
-    /* Transfer loop */
-    while (hspi->RxXferCount > 0U)
-    {
-      /* Check the RXNE flag */
-      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
-      {
-        *((uint16_t *)pData) = hspi->Instance->DR;
-        pData += sizeof(uint16_t);
-        hspi->RxXferCount--;
-      }
-      else
-      {
-        /* Timeout management */
-        if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >=  Timeout)))
-        {
-          errorcode = HAL_TIMEOUT;
-          goto error;
-        }
-      }
-    }
-  }
-
-#if (USE_SPI_CRC != 0U)
-  /* Handle the CRC Transmission */
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    /* freeze the CRC before the latest data */
-    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-
-    /* Read the latest data */
-    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
-    {
-      /* the latest data has not been received */
-      errorcode = HAL_TIMEOUT;
-      goto error;
-    }
-
-    /* Receive last data in 16 Bit mode */
-    if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
-    {
-      *((uint16_t *)pData) = hspi->Instance->DR;
-    }
-    /* Receive last data in 8 Bit mode */
-    else
-    {
-      (*pData) = *(__IO uint8_t *)&hspi->Instance->DR;
-    }
-
-    /* Wait the CRC data */
-    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-      errorcode = HAL_TIMEOUT;
-      goto error;
-    }
-
-    /* Read CRC to Flush DR and RXNE flag */
-    if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
-    {
-      tmpreg = hspi->Instance->DR;
-      /* To avoid GCC warning */
-      UNUSED(tmpreg);
-    }
-    else
-    {
-      tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
-      /* To avoid GCC warning */
-      UNUSED(tmpreg);
-
-      if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
-      {
-        if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout, tickstart) != HAL_OK)
-        {
-          /* Error on the CRC reception */
-          SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-          errorcode = HAL_TIMEOUT;
-          goto error;
-        }
-        tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
-        /* To avoid GCC warning */
-        UNUSED(tmpreg);
-      }
-    }
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Check the end of the transaction */
-  if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
-  {
-    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
-  }
-
-#if (USE_SPI_CRC != 0U)
-  /* Check if CRC error occurred */
-  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
-  {
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-  }
-#endif /* USE_SPI_CRC */
-
-  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
-  {
-    errorcode = HAL_ERROR;
-  }
-
-error :
-  hspi->State = HAL_SPI_STATE_READY;
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Transmit and Receive an amount of data in blocking mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pTxData: pointer to transmission data buffer
-  * @param  pRxData: pointer to reception data buffer
-  * @param  Size: amount of data to be sent and received
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
-                                          uint32_t Timeout)
-{
-  uint32_t tmp = 0U, tmp1 = 0U;
-#if (USE_SPI_CRC != 0U)
-  __IO uint16_t tmpreg = 0U;
-#endif /* USE_SPI_CRC */
-  uint32_t tickstart = 0U;
-  /* Variable used to alternate Rx and Tx during transfer */
-  uint32_t txallowed = 1U;
-  HAL_StatusTypeDef errorcode = HAL_OK;
-
-  /* Check Direction parameter */
-  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
-
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  /* Init tickstart for timeout management*/
-  tickstart = HAL_GetTick();
-
-  tmp  = hspi->State;
-  tmp1 = hspi->Init.Mode;
-
-  if (!((tmp == HAL_SPI_STATE_READY) || \
-        ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
-  if (hspi->State != HAL_SPI_STATE_BUSY_RX)
-  {
-    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
-  }
-
-  /* Set the transaction information */
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pRxBuffPtr  = (uint8_t *)pRxData;
-  hspi->RxXferCount = Size;
-  hspi->RxXferSize  = Size;
-  hspi->pTxBuffPtr  = (uint8_t *)pTxData;
-  hspi->TxXferCount = Size;
-  hspi->TxXferSize  = Size;
-
-  /*Init field not used in handle to zero */
-  hspi->RxISR       = NULL;
-  hspi->TxISR       = NULL;
-
-#if (USE_SPI_CRC != 0U)
-  /* Reset CRC Calculation */
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Set the Rx Fifo threshold */
-  if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1))
-  {
-    /* set fiforxthreshold according the reception data length: 16bit */
-    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-  }
-  else
-  {
-    /* set fiforxthreshold according the reception data length: 8bit */
-    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-  }
-
-  /* Check if the SPI is already enabled */
-  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-
-  /* Transmit and Receive data in 16 Bit mode */
-  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
-  {
-    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01))
-    {
-      hspi->Instance->DR = *((uint16_t *)pTxData);
-      pTxData += sizeof(uint16_t);
-      hspi->TxXferCount--;
-    }
-    while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
-    {
-      /* Check TXE flag */
-      if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
-      {
-        hspi->Instance->DR = *((uint16_t *)pTxData);
-        pTxData += sizeof(uint16_t);
-        hspi->TxXferCount--;
-        /* Next Data is a reception (Rx). Tx not allowed */
-        txallowed = 0U;
-
-#if (USE_SPI_CRC != 0U)
-        /* Enable CRC Transmission */
-        if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
-        {
-          /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
-          if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
-          {
-            SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
-          }
-          SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-        }
-#endif /* USE_SPI_CRC */
-      }
-
-      /* Check RXNE flag */
-      if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
-      {
-        *((uint16_t *)pRxData) = hspi->Instance->DR;
-        pRxData += sizeof(uint16_t);
-        hspi->RxXferCount--;
-        /* Next Data is a Transmission (Tx). Tx is allowed */
-        txallowed = 1U;
-      }
-      if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >=  Timeout))
-      {
-        errorcode = HAL_TIMEOUT;
-        goto error;
-      }
-    }
-  }
-  /* Transmit and Receive data in 8 Bit mode */
-  else
-  {
-    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01))
-    {
-      *((__IO uint8_t *)&hspi->Instance->DR) = (*pTxData);
-      pTxData += sizeof(uint8_t);
-      hspi->TxXferCount--;
-    }
-    while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
-    {
-      /* check TXE flag */
-      if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
-      {
-        if (hspi->TxXferCount > 1U)
-        {
-          hspi->Instance->DR = *((uint16_t *)pTxData);
-          pTxData += sizeof(uint16_t);
-          hspi->TxXferCount -= 2U;
-        }
-        else
-        {
-          *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++);
-          hspi->TxXferCount--;
-        }
-        /* Next Data is a reception (Rx). Tx not allowed */
-        txallowed = 0U;
-
-#if (USE_SPI_CRC != 0U)
-        /* Enable CRC Transmission */
-        if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
-        {
-          /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
-          if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
-          {
-            SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
-          }
-          SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-        }
-#endif /* USE_SPI_CRC */
-      }
-
-      /* Wait until RXNE flag is reset */
-      if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
-      {
-        if (hspi->RxXferCount > 1U)
-        {
-          *((uint16_t *)pRxData) = hspi->Instance->DR;
-          pRxData += sizeof(uint16_t);
-          hspi->RxXferCount -= 2U;
-          if (hspi->RxXferCount <= 1U)
-          {
-            /* set fiforxthreshold before to switch on 8 bit data size */
-            SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-          }
-        }
-        else
-        {
-          (*pRxData++) = *(__IO uint8_t *)&hspi->Instance->DR;
-          hspi->RxXferCount--;
-        }
-        /* Next Data is a Transmission (Tx). Tx is allowed */
-        txallowed = 1U;
-      }
-      if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >=  Timeout))
-      {
-        errorcode = HAL_TIMEOUT;
-        goto error;
-      }
-    }
-  }
-
-#if (USE_SPI_CRC != 0U)
-  /* Read CRC from DR to close CRC calculation process */
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    /* Wait until TXE flag */
-    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
-    {
-      /* Error on the CRC reception */
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-      errorcode = HAL_TIMEOUT;
-      goto error;
-    }
-    /* Read CRC */
-    if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
-    {
-      tmpreg = hspi->Instance->DR;
-      /* To avoid GCC warning */
-      UNUSED(tmpreg);
-    }
-    else
-    {
-      tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
-      /* To avoid GCC warning */
-      UNUSED(tmpreg);
-
-      if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
-      {
-        if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
-        {
-          /* Error on the CRC reception */
-          SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-          errorcode = HAL_TIMEOUT;
-          goto error;
-        }
-        tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
-        /* To avoid GCC warning */
-        UNUSED(tmpreg);
-      }
-    }
-  }
-
-  /* Check if CRC error occurred */
-  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
-  {
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-    /* Clear CRC Flag */
-    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-
-    errorcode = HAL_ERROR;
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Check the end of the transaction */
-  if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
-  {
-    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
-  }
-
-  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
-  {
-    errorcode = HAL_ERROR;
-  }
-
-error :
-  hspi->State = HAL_SPI_STATE_READY;
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Transmit an amount of data in non-blocking mode with Interrupt.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pData: pointer to data buffer
-  * @param  Size: amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
-{
-  HAL_StatusTypeDef errorcode = HAL_OK;
-
-  /* Check Direction parameter */
-  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
-
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  if ((pData == NULL) || (Size == 0U))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  if (hspi->State != HAL_SPI_STATE_READY)
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  /* Set the transaction information */
-  hspi->State       = HAL_SPI_STATE_BUSY_TX;
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pTxBuffPtr  = (uint8_t *)pData;
-  hspi->TxXferSize  = Size;
-  hspi->TxXferCount = Size;
-
-  /* Init field not used in handle to zero */
-  hspi->pRxBuffPtr  = (uint8_t *)NULL;
-  hspi->RxXferSize  = 0U;
-  hspi->RxXferCount = 0U;
-  hspi->RxISR       = NULL;
-
-  /* Set the function for IT treatment */
-  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
-  {
-    hspi->TxISR = SPI_TxISR_16BIT;
-  }
-  else
-  {
-    hspi->TxISR = SPI_TxISR_8BIT;
-  }
-
-  /* Configure communication direction : 1Line */
-  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
-  {
-    SPI_1LINE_TX(hspi);
-  }
-
-#if (USE_SPI_CRC != 0U)
-  /* Reset CRC Calculation */
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Enable TXE and ERR interrupt */
-  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
-
-
-  /* Check if the SPI is already enabled */
-  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-
-error :
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Receive an amount of data in non-blocking mode with Interrupt.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pData: pointer to data buffer
-  * @param  Size: amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
-{
-  HAL_StatusTypeDef errorcode = HAL_OK;
-
-  if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
-  {
-    hspi->State = HAL_SPI_STATE_BUSY_RX;
-    /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
-    return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
-  }
-
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  if (hspi->State != HAL_SPI_STATE_READY)
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  if ((pData == NULL) || (Size == 0U))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  /* Set the transaction information */
-  hspi->State       = HAL_SPI_STATE_BUSY_RX;
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pRxBuffPtr  = (uint8_t *)pData;
-  hspi->RxXferSize  = Size;
-  hspi->RxXferCount = Size;
-
-  /* Init field not used in handle to zero */
-  hspi->pTxBuffPtr  = (uint8_t *)NULL;
-  hspi->TxXferSize  = 0U;
-  hspi->TxXferCount = 0U;
-  hspi->TxISR       = NULL;
-
-  /* check the data size to adapt Rx threshold and the set the function for IT treatment */
-  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
-  {
-    /* set fiforxthreshold according the reception data length: 16 bit */
-    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-    hspi->RxISR = SPI_RxISR_16BIT;
-  }
-  else
-  {
-    /* set fiforxthreshold according the reception data length: 8 bit */
-    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-    hspi->RxISR = SPI_RxISR_8BIT;
-  }
-
-  /* Configure communication direction : 1Line */
-  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
-  {
-    SPI_1LINE_RX(hspi);
-  }
-
-#if (USE_SPI_CRC != 0U)
-  /* Reset CRC Calculation */
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    hspi->CRCSize = 1U;
-    if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
-    {
-      hspi->CRCSize = 2U;
-    }
-    SPI_RESET_CRC(hspi);
-  }
-  else
-  {
-    hspi->CRCSize = 0U;
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Enable TXE and ERR interrupt */
-  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
-  /* Note : The SPI must be enabled after unlocking current process
-            to avoid the risk of SPI interrupt handle execution before current
-            process unlock */
-
-  /* Check if the SPI is already enabled */
-  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-
-error :
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Transmit and Receive an amount of data in non-blocking mode with Interrupt.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pTxData: pointer to transmission data buffer
-  * @param  pRxData: pointer to reception data buffer
-  * @param  Size: amount of data to be sent and received
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
-{
-  uint32_t tmp = 0U, tmp1 = 0U;
-  HAL_StatusTypeDef errorcode = HAL_OK;
-
-  /* Check Direction parameter */
-  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
-
-  /* Process locked */
-  __HAL_LOCK(hspi);
-
-  tmp  = hspi->State;
-  tmp1 = hspi->Init.Mode;
-
-  if (!((tmp == HAL_SPI_STATE_READY) || \
-        ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
-  if (hspi->State != HAL_SPI_STATE_BUSY_RX)
-  {
-    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
-  }
-
-  /* Set the transaction information */
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pTxBuffPtr  = (uint8_t *)pTxData;
-  hspi->TxXferSize  = Size;
-  hspi->TxXferCount = Size;
-  hspi->pRxBuffPtr  = (uint8_t *)pRxData;
-  hspi->RxXferSize  = Size;
-  hspi->RxXferCount = Size;
-
-  /* Set the function for IT treatment */
-  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
-  {
-    hspi->RxISR     = SPI_2linesRxISR_16BIT;
-    hspi->TxISR     = SPI_2linesTxISR_16BIT;
-  }
-  else
-  {
-    hspi->RxISR     = SPI_2linesRxISR_8BIT;
-    hspi->TxISR     = SPI_2linesTxISR_8BIT;
-  }
-
-#if (USE_SPI_CRC != 0U)
-  /* Reset CRC Calculation */
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    hspi->CRCSize = 1U;
-    if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
-    {
-      hspi->CRCSize = 2U;
-    }
-    SPI_RESET_CRC(hspi);
-  }
-  else
-  {
-    hspi->CRCSize = 0U;
-  }
-#endif /* USE_SPI_CRC */
-
-  /* check if packing mode is enabled and if there is more than 2 data to receive */
-  if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2U))
-  {
-    /* set fiforxthreshold according the reception data length: 16 bit */
-    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-  }
-  else
-  {
-    /* set fiforxthreshold according the reception data length: 8 bit */
-    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-  }
-
-  /* Enable TXE, RXNE and ERR interrupt */
-  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
-
-  /* Check if the SPI is already enabled */
-  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-
-error :
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Transmit an amount of data in non-blocking mode with DMA.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pData: pointer to data buffer
-  * @param  Size: amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
-{
-  HAL_StatusTypeDef errorcode = HAL_OK;
-
-  /* Check Direction parameter */
-  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
-
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  if (hspi->State != HAL_SPI_STATE_READY)
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  if ((pData == NULL) || (Size == 0U))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  /* Set the transaction information */
-  hspi->State       = HAL_SPI_STATE_BUSY_TX;
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pTxBuffPtr  = (uint8_t *)pData;
-  hspi->TxXferSize  = Size;
-  hspi->TxXferCount = Size;
-
-  /* Init field not used in handle to zero */
-  hspi->pRxBuffPtr  = (uint8_t *)NULL;
-  hspi->TxISR       = NULL;
-  hspi->RxISR       = NULL;
-  hspi->RxXferSize  = 0U;
-  hspi->RxXferCount = 0U;
-
-  /* Configure communication direction : 1Line */
-  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
-  {
-    SPI_1LINE_TX(hspi);
-  }
-
-#if (USE_SPI_CRC != 0U)
-  /* Reset CRC Calculation */
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Set the SPI TxDMA Half transfer complete callback */
-  hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
-
-  /* Set the SPI TxDMA transfer complete callback */
-  hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
-
-  /* Set the DMA error callback */
-  hspi->hdmatx->XferErrorCallback = SPI_DMAError;
-
-  /* Set the DMA AbortCpltCallback */
-  hspi->hdmatx->XferAbortCallback = NULL;
-
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
-  /* packing mode is enabled only if the DMA setting is HALWORD */
-  if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
-  {
-    /* Check the even/odd of the data size + crc if enabled */
-    if ((hspi->TxXferCount & 0x1U) == 0U)
-    {
-      CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
-      hspi->TxXferCount = (hspi->TxXferCount >> 1U);
-    }
-    else
-    {
-      SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
-      hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
-    }
-  }
-
-  /* Enable the Tx DMA Stream/Channel */
-  HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
-
-  /* Check if the SPI is already enabled */
-  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-
-  /* Enable the SPI Error Interrupt Bit */
-  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
-
-  /* Enable Tx DMA Request */
-  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
-error :
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Receive an amount of data in non-blocking mode with DMA.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pData: pointer to data buffer
-  * @note   When the CRC feature is enabled the pData Length must be Size + 1.
-  * @param  Size: amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
-{
-  HAL_StatusTypeDef errorcode = HAL_OK;
-
-  if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
-  {
-    hspi->State = HAL_SPI_STATE_BUSY_RX;
-    /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
-    return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
-  }
-
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  if (hspi->State != HAL_SPI_STATE_READY)
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  if ((pData == NULL) || (Size == 0U))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  /* Set the transaction information */
-  hspi->State       = HAL_SPI_STATE_BUSY_RX;
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pRxBuffPtr  = (uint8_t *)pData;
-  hspi->RxXferSize  = Size;
-  hspi->RxXferCount = Size;
-
-  /*Init field not used in handle to zero */
-  hspi->RxISR       = NULL;
-  hspi->TxISR       = NULL;
-  hspi->TxXferSize  = 0U;
-  hspi->TxXferCount = 0U;
-
-  /* Configure communication direction : 1Line */
-  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
-  {
-    SPI_1LINE_RX(hspi);
-  }
-
-#if (USE_SPI_CRC != 0U)
-  /* Reset CRC Calculation */
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-  }
-#endif /* USE_SPI_CRC */
-
-  /* packing mode management is enabled by the DMA settings */
-  if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
-  {
-    /* Restriction the DMA data received is not allowed in this mode */
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
-  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
-  {
-    /* set fiforxthreshold according the reception data length: 16bit */
-    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-  }
-  else
-  {
-    /* set fiforxthreshold according the reception data length: 8bit */
-    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-  }
-
-  /* Set the SPI RxDMA Half transfer complete callback */
-  hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
-
-  /* Set the SPI Rx DMA transfer complete callback */
-  hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
-
-  /* Set the DMA error callback */
-  hspi->hdmarx->XferErrorCallback = SPI_DMAError;
-
-  /* Set the DMA AbortCpltCallback */
-  hspi->hdmarx->XferAbortCallback = NULL;
-
-  /* Enable the Rx DMA Stream/Channel  */
-  HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
-
-  /* Check if the SPI is already enabled */
-  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-
-  /* Enable the SPI Error Interrupt Bit */
-  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
-
-  /* Enable Rx DMA Request */
-  SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-
-error:
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Transmit and Receive an amount of data in non-blocking mode with DMA.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pTxData: pointer to transmission data buffer
-  * @param  pRxData: pointer to reception data buffer
-  * @note   When the CRC feature is enabled the pRxData Length must be Size + 1
-  * @param  Size: amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
-                                              uint16_t Size)
-{
-  uint32_t tmp = 0U, tmp1 = 0U;
-  HAL_StatusTypeDef errorcode = HAL_OK;
-
-  /* Check Direction parameter */
-  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
-
-  /* Process locked */
-  __HAL_LOCK(hspi);
-
-  tmp  = hspi->State;
-  tmp1 = hspi->Init.Mode;
-  if (!((tmp == HAL_SPI_STATE_READY) ||
-        ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
-  if (hspi->State != HAL_SPI_STATE_BUSY_RX)
-  {
-    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
-  }
-
-  /* Set the transaction information */
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pTxBuffPtr  = (uint8_t *)pTxData;
-  hspi->TxXferSize  = Size;
-  hspi->TxXferCount = Size;
-  hspi->pRxBuffPtr  = (uint8_t *)pRxData;
-  hspi->RxXferSize  = Size;
-  hspi->RxXferCount = Size;
-
-  /* Init field not used in handle to zero */
-  hspi->RxISR       = NULL;
-  hspi->TxISR       = NULL;
-
-#if (USE_SPI_CRC != 0U)
-  /* Reset CRC Calculation */
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Reset the threshold bit */
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
-
-  /* the packing mode management is enabled by the DMA settings according the spi data size */
-  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
-  {
-    /* set fiforxthreshold according the reception data length: 16bit */
-    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-  }
-  else
-  {
-    /* set fiforxthreshold according the reception data length: 8bit */
-    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-
-    if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
-    {
-      if ((hspi->TxXferSize & 0x1U) == 0x0U)
-      {
-        CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
-        hspi->TxXferCount = hspi->TxXferCount >> 1U;
-      }
-      else
-      {
-        SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
-        hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
-      }
-    }
-
-    if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
-    {
-      /* set fiforxthreshold according the reception data length: 16bit */
-      CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-
-      if ((hspi->RxXferCount & 0x1U) == 0x0U)
-      {
-        CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
-        hspi->RxXferCount = hspi->RxXferCount >> 1U;
-      }
-      else
-      {
-        SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
-        hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
-      }
-    }
-  }
-
-  /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
-  if (hspi->State == HAL_SPI_STATE_BUSY_RX)
-  {
-    /* Set the SPI Rx DMA Half transfer complete callback */
-    hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
-    hspi->hdmarx->XferCpltCallback     = SPI_DMAReceiveCplt;
-  }
-  else
-  {
-    /* Set the SPI Tx/Rx DMA Half transfer complete callback */
-    hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
-    hspi->hdmarx->XferCpltCallback     = SPI_DMATransmitReceiveCplt;
-  }
-
-  /* Set the DMA error callback */
-  hspi->hdmarx->XferErrorCallback = SPI_DMAError;
-
-  /* Set the DMA AbortCpltCallback */
-  hspi->hdmarx->XferAbortCallback = NULL;
-
-  /* Enable the Rx DMA Stream/Channel  */
-  HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
-
-  /* Enable Rx DMA Request */
-  SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-
-  /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
-  is performed in DMA reception complete callback  */
-  hspi->hdmatx->XferHalfCpltCallback = NULL;
-  hspi->hdmatx->XferCpltCallback     = NULL;
-  hspi->hdmatx->XferErrorCallback    = NULL;
-  hspi->hdmatx->XferAbortCallback    = NULL;
-
-  /* Enable the Tx DMA Stream/Channel  */
-  HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
-
-  /* Check if the SPI is already enabled */
-  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-  /* Enable the SPI Error Interrupt Bit */
-  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
-
-  /* Enable Tx DMA Request */
-  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
-error :
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Abort ongoing transfer (blocking mode).
-  * @param  hspi SPI handle.
-  * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),
-  *         started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable SPI Interrupts (depending of transfer direction)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
-{
-  HAL_StatusTypeDef errorcode;
-
-  /* Initialized local variable  */
-  errorcode = HAL_OK;
-
-  /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
-  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
-  {
-    hspi->TxISR = SPI_AbortTx_ISR;
-    while (hspi->State != HAL_SPI_STATE_ABORT);
-  }
-
-  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
-  {
-    hspi->RxISR = SPI_AbortRx_ISR;
-    while (hspi->State != HAL_SPI_STATE_ABORT);
-  }
-
-  /* Clear ERRIE interrupts in case of DMA Mode */
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
-
-  /* Disable the SPI DMA Tx or SPI DMA Rx request if enabled */
-  if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
-  {
-    /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
-    if (hspi->hdmatx != NULL)
-    {
-      /* Set the SPI DMA Abort callback :
-      will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
-      hspi->hdmatx->XferAbortCallback = NULL;
-
-      /* Abort DMA Tx Handle linked to SPI Peripheral */
-      if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
-      {
-        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
-      }
-
-      /* Disable Tx DMA Request */
-      CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
-
-      if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
-      {
-        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
-      }
-
-      /* Disable SPI Peripheral */
-      __HAL_SPI_DISABLE(hspi);
-
-      /* Empty the FRLVL fifo */
-      if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
-      {
-        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
-      }
-    }
-    /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
-    if (hspi->hdmarx != NULL)
-    {
-      /* Set the SPI DMA Abort callback :
-      will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
-      hspi->hdmarx->XferAbortCallback = NULL;
-
-      /* Abort DMA Rx Handle linked to SPI Peripheral */
-      if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
-      {
-        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
-      }
-
-      /* Disable peripheral */
-      __HAL_SPI_DISABLE(hspi);
-
-      /* Control the BSY flag */
-      if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
-      {
-        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
-      }
-
-      /* Empty the FRLVL fifo */
-      if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
-      {
-        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
-      }
-
-      /* Disable Rx DMA Request */
-      CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
-    }
-  }
-  /* Reset Tx and Rx transfer counters */
-  hspi->RxXferCount = 0U;
-  hspi->TxXferCount = 0U;
-
-  /* Check error during Abort procedure */
-  if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
-  {
-    /* return HAL_Error in case of error during Abort procedure */
-    errorcode = HAL_ERROR;
-  }
-  else
-  {
-    /* Reset errorCode */
-    hspi->ErrorCode = HAL_SPI_ERROR_NONE;
-  }
-
-  /* Clear the Error flags in the SR register */
-  __HAL_SPI_CLEAR_OVRFLAG(hspi);
-  __HAL_SPI_CLEAR_FREFLAG(hspi);
-
-  /* Restore hspi->state to ready */
-  hspi->State = HAL_SPI_STATE_READY;
-
-  return errorcode;
-}
-
-/**
-  * @brief  Abort ongoing transfer (Interrupt mode).
-  * @param  hspi SPI handle.
-  * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),
-  *         started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable SPI Interrupts (depending of transfer direction)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  *           - At abort completion, call user abort complete callback
-  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
-  *         considered as completed only when user abort complete callback is executed (not when exiting function).
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
-{
-  HAL_StatusTypeDef errorcode;
-  uint32_t abortcplt ;
-
-  /* Initialized local variable  */
-  errorcode = HAL_OK;
-  abortcplt = 1U;
-
-  /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
-  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
-  {
-    hspi->TxISR = SPI_AbortTx_ISR;
-    while (hspi->State != HAL_SPI_STATE_ABORT);
-  }
-
-  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
-  {
-    hspi->RxISR = SPI_AbortRx_ISR;
-    while (hspi->State != HAL_SPI_STATE_ABORT);
-  }
-
-  /* Clear ERRIE interrupts in case of DMA Mode */
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
-
-  /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
-     before any call to DMA Abort functions */
-  /* DMA Tx Handle is valid */
-  if (hspi->hdmatx != NULL)
-  {
-    /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
-       Otherwise, set it to NULL */
-    if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
-    {
-      hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
-    }
-    else
-    {
-      hspi->hdmatx->XferAbortCallback = NULL;
-    }
-  }
-  /* DMA Rx Handle is valid */
-  if (hspi->hdmarx != NULL)
-  {
-    /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
-       Otherwise, set it to NULL */
-    if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
-    {
-      hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
-    }
-    else
-    {
-      hspi->hdmarx->XferAbortCallback = NULL;
-    }
-  }
-
-  /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
-  if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) && (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
-  {
-    /* Abort the SPI DMA Tx Stream/Channel */
-    if (hspi->hdmatx != NULL)
-    {
-      /* Abort DMA Tx Handle linked to SPI Peripheral */
-      if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
-      {
-        hspi->hdmatx->XferAbortCallback = NULL;
-        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
-      }
-      else
-      {
-        abortcplt = 0U;
-      }
-    }
-    /* Abort the SPI DMA Rx Stream/Channel */
-    if (hspi->hdmarx != NULL)
-    {
-      /* Abort DMA Rx Handle linked to SPI Peripheral */
-      if (HAL_DMA_Abort_IT(hspi->hdmarx) !=  HAL_OK)
-      {
-        hspi->hdmarx->XferAbortCallback = NULL;
-        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
-        abortcplt = 1U;
-      }
-      else
-      {
-        abortcplt = 0U;
-      }
-    }
-  }
-
-  /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
-  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
-  {
-    /* Abort the SPI DMA Tx Stream/Channel */
-    if (hspi->hdmatx != NULL)
-    {
-      /* Abort DMA Tx Handle linked to SPI Peripheral */
-      if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
-      {
-        hspi->hdmatx->XferAbortCallback = NULL;
-        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
-      }
-      else
-      {
-        abortcplt = 0U;
-      }
-    }
-  }
-  /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
-  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
-  {
-    /* Abort the SPI DMA Rx Stream/Channel */
-    if (hspi->hdmarx != NULL)
-    {
-      /* Abort DMA Rx Handle linked to SPI Peripheral */
-      if (HAL_DMA_Abort_IT(hspi->hdmarx) !=  HAL_OK)
-      {
-        hspi->hdmarx->XferAbortCallback = NULL;
-        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
-      }
-      else
-      {
-        abortcplt = 0U;
-      }
-    }
-  }
-
-  if (abortcplt == 1U)
-  {
-    /* Reset Tx and Rx transfer counters */
-    hspi->RxXferCount = 0U;
-    hspi->TxXferCount = 0U;
-
-    /* Check error during Abort procedure */
-    if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
-    {
-      /* return HAL_Error in case of error during Abort procedure */
-      errorcode = HAL_ERROR;
-    }
-    else
-    {
-      /* Reset errorCode */
-      hspi->ErrorCode = HAL_SPI_ERROR_NONE;
-    }
-
-    /* Clear the Error flags in the SR register */
-    __HAL_SPI_CLEAR_OVRFLAG(hspi);
-    __HAL_SPI_CLEAR_FREFLAG(hspi);
-
-    /* Restore hspi->State to Ready */
-    hspi->State = HAL_SPI_STATE_READY;
-
-    /* As no DMA to be aborted, call directly user Abort complete callback */
-    HAL_SPI_AbortCpltCallback(hspi);
-  }
-
-  return errorcode;
-}
-
-/**
-  * @brief  Pause the DMA Transfer.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for the specified SPI module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
-{
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  /* Disable the SPI DMA Tx & Rx requests */
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Resume the DMA Transfer.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for the specified SPI module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
-{
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  /* Enable the SPI DMA Tx & Rx requests */
-  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Stop the DMA Transfer.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for the specified SPI module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
-{
-  /* The Lock is not implemented on this API to allow the user application
-     to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
-     when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
-     and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
-     */
-
-  /* Abort the SPI DMA tx Stream/Channel  */
-  if (hspi->hdmatx != NULL)
-  {
-    HAL_DMA_Abort(hspi->hdmatx);
-  }
-  /* Abort the SPI DMA rx Stream/Channel  */
-  if (hspi->hdmarx != NULL)
-  {
-    HAL_DMA_Abort(hspi->hdmarx);
-  }
-
-  /* Disable the SPI DMA Tx & Rx requests */
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-  hspi->State = HAL_SPI_STATE_READY;
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle SPI interrupt request.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for the specified SPI module.
-  * @retval None
-  */
-void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
-{
-  uint32_t itsource = hspi->Instance->CR2;
-  uint32_t itflag   = hspi->Instance->SR;
-
-  /* SPI in mode Receiver ----------------------------------------------------*/
-  if (((itflag & SPI_FLAG_OVR) == RESET) &&
-      ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
-  {
-    hspi->RxISR(hspi);
-    return;
-  }
-
-  /* SPI in mode Transmitter -------------------------------------------------*/
-  if (((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
-  {
-    hspi->TxISR(hspi);
-    return;
-  }
-
-  /* SPI in Error Treatment --------------------------------------------------*/
-  if (((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET) && ((itsource & SPI_IT_ERR) != RESET))
-  {
-    /* SPI Overrun error interrupt occurred ----------------------------------*/
-    if ((itflag & SPI_FLAG_OVR) != RESET)
-    {
-      if (hspi->State != HAL_SPI_STATE_BUSY_TX)
-      {
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
-        __HAL_SPI_CLEAR_OVRFLAG(hspi);
-      }
-      else
-      {
-        __HAL_SPI_CLEAR_OVRFLAG(hspi);
-        return;
-      }
-    }
-
-    /* SPI Mode Fault error interrupt occurred -------------------------------*/
-    if ((itflag & SPI_FLAG_MODF) != RESET)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
-      __HAL_SPI_CLEAR_MODFFLAG(hspi);
-    }
-
-    /* SPI Frame error interrupt occurred ------------------------------------*/
-    if ((itflag & SPI_FLAG_FRE) != RESET)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
-      __HAL_SPI_CLEAR_FREFLAG(hspi);
-    }
-
-    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
-    {
-      /* Disable all interrupts */
-      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
-
-      hspi->State = HAL_SPI_STATE_READY;
-      /* Disable the SPI DMA requests if enabled */
-      if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
-      {
-        CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
-
-        /* Abort the SPI DMA Rx channel */
-        if (hspi->hdmarx != NULL)
-        {
-          /* Set the SPI DMA Abort callback :
-          will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
-          hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
-          HAL_DMA_Abort_IT(hspi->hdmarx);
-        }
-        /* Abort the SPI DMA Tx channel */
-        if (hspi->hdmatx != NULL)
-        {
-          /* Set the SPI DMA Abort callback :
-          will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
-          hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
-          HAL_DMA_Abort_IT(hspi->hdmatx);
-        }
-      }
-      else
-      {
-        /* Call user error callback */
-        HAL_SPI_ErrorCallback(hspi);
-      }
-    }
-    return;
-  }
-}
-
-/**
-  * @brief Tx Transfer completed callback.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_TxCpltCallback should be implemented in the user file
-   */
-}
-
-/**
-  * @brief Rx Transfer completed callback.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_RxCpltCallback should be implemented in the user file
-   */
-}
-
-/**
-  * @brief Tx and Rx Transfer completed callback.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_TxRxCpltCallback should be implemented in the user file
-   */
-}
-
-/**
-  * @brief Tx Half Transfer completed callback.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
-   */
-}
-
-/**
-  * @brief Rx Half Transfer completed callback.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
-   */
-}
-
-/**
-  * @brief Tx and Rx Half Transfer callback.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
-   */
-}
-
-/**
-  * @brief SPI error callback.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_ErrorCallback should be implemented in the user file
-   */
-  /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
-            and user can use HAL_SPI_GetError() API to check the latest error occurred
-   */
-}
-
-/**
-  * @brief  SPI Abort Complete callback.
-  * @param  hspi SPI handle.
-  * @retval None
-  */
-__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_AbortCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
-  * @brief   SPI control functions
-  *
-@verbatim
- ===============================================================================
-                      ##### Peripheral State and Errors functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to control the SPI.
-     (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
-     (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the SPI handle state.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval SPI state
-  */
-HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
-{
-  /* Return SPI handle state */
-  return hspi->State;
-}
-
-/**
-  * @brief  Return the SPI error code.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval SPI error code in bitmap format
-  */
-uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
-{
-  /* Return SPI ErrorCode */
-  return hspi->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup SPI_Private_Functions
-  * @brief   Private functions
-  * @{
-  */
-
-/**
-  * @brief DMA SPI transmit process complete callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-  uint32_t tickstart = 0U;
-
-  /* Init tickstart for timeout managment*/
-  tickstart = HAL_GetTick();
-
-  /* DMA Normal Mode */
-  if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC)
-  {
-    /* Disable ERR interrupt */
-    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
-
-    /* Disable Tx DMA Request */
-    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
-    /* Check the end of the transaction */
-    if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-    }
-
-    /* Clear overrun flag in 2 Lines communication mode because received data is not read */
-    if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
-    {
-      __HAL_SPI_CLEAR_OVRFLAG(hspi);
-    }
-
-    hspi->TxXferCount = 0U;
-    hspi->State = HAL_SPI_STATE_READY;
-
-    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
-    {
-      HAL_SPI_ErrorCallback(hspi);
-      return;
-    }
-  }
-  HAL_SPI_TxCpltCallback(hspi);
-}
-
-/**
-  * @brief DMA SPI receive process complete callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-  uint32_t tickstart = 0U;
-#if (USE_SPI_CRC != 0U)
-  __IO uint16_t tmpreg = 0U;
-#endif /* USE_SPI_CRC */
-
-  /* Init tickstart for timeout management*/
-  tickstart = HAL_GetTick();
-
-  /* DMA Normal Mode */
-  if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC)
-  {
-    /* Disable ERR interrupt */
-    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
-
-#if (USE_SPI_CRC != 0U)
-    /* CRC handling */
-    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      /* Wait until RXNE flag */
-      if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
-      {
-        /* Error on the CRC reception */
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-      }
-      /* Read CRC */
-      if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
-      {
-        tmpreg = hspi->Instance->DR;
-        /* To avoid GCC warning */
-        UNUSED(tmpreg);
-      }
-      else
-      {
-        tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
-        /* To avoid GCC warning */
-        UNUSED(tmpreg);
-
-        if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
-        {
-          if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
-          {
-            /* Error on the CRC reception */
-            SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-          }
-          tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
-          /* To avoid GCC warning */
-          UNUSED(tmpreg);
-        }
-      }
-    }
-#endif /* USE_SPI_CRC */
-
-    /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
-    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
-    /* Check the end of the transaction */
-    if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
-    {
-      hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
-    }
-
-    hspi->RxXferCount = 0U;
-    hspi->State = HAL_SPI_STATE_READY;
-
-#if (USE_SPI_CRC != 0U)
-    /* Check if CRC error occurred */
-    if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-    }
-#endif /* USE_SPI_CRC */
-
-    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
-    {
-      HAL_SPI_ErrorCallback(hspi);
-      return;
-    }
-  }
-  HAL_SPI_RxCpltCallback(hspi);
-}
-
-/**
-  * @brief  DMA SPI transmit receive process complete callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-  uint32_t tickstart = 0U;
-#if (USE_SPI_CRC != 0U)
-  __IO int16_t tmpreg = 0U;
-#endif /* USE_SPI_CRC */
-  /* Init tickstart for timeout management*/
-  tickstart = HAL_GetTick();
-
-  /* DMA Normal Mode */
-  if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC)
-  {
-    /* Disable ERR interrupt */
-    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
-
-#if (USE_SPI_CRC != 0U)
-    /* CRC handling */
-    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
-      {
-        if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT,
-                                          tickstart) != HAL_OK)
-        {
-          /* Error on the CRC reception */
-          SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-        }
-        /* Read CRC to Flush DR and RXNE flag */
-        tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
-        /* To avoid GCC warning */
-        UNUSED(tmpreg);
-      }
-      else
-      {
-        if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
-        {
-          /* Error on the CRC reception */
-          SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-        }
-        /* Read CRC to Flush DR and RXNE flag */
-        tmpreg = hspi->Instance->DR;
-        /* To avoid GCC warning */
-        UNUSED(tmpreg);
-      }
-    }
-#endif /* USE_SPI_CRC */
-
-    /* Check the end of the transaction */
-    if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-    }
-
-    /* Disable Rx/Tx DMA Request */
-    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
-    hspi->TxXferCount = 0U;
-    hspi->RxXferCount = 0U;
-    hspi->State = HAL_SPI_STATE_READY;
-
-#if (USE_SPI_CRC != 0U)
-    /* Check if CRC error occurred */
-    if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-    }
-#endif /* USE_SPI_CRC */
-
-    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
-    {
-      HAL_SPI_ErrorCallback(hspi);
-      return;
-    }
-  }
-  HAL_SPI_TxRxCpltCallback(hspi);
-}
-
-/**
-  * @brief  DMA SPI half transmit process complete callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  HAL_SPI_TxHalfCpltCallback(hspi);
-}
-
-/**
-  * @brief  DMA SPI half receive process complete callback
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  HAL_SPI_RxHalfCpltCallback(hspi);
-}
-
-/**
-  * @brief  DMA SPI half transmit receive process complete callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  HAL_SPI_TxRxHalfCpltCallback(hspi);
-}
-
-/**
-  * @brief  DMA SPI communication error callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SPI_DMAError(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  /* Stop the disable DMA transfer on SPI side */
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
-  SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
-  hspi->State = HAL_SPI_STATE_READY;
-  HAL_SPI_ErrorCallback(hspi);
-}
-
-/**
-  * @brief  DMA SPI communication abort callback, when initiated by HAL services on Error
-  *         (To be called at end of DMA Abort procedure following error occurrence).
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-  hspi->RxXferCount = 0U;
-  hspi->TxXferCount = 0U;
-
-  HAL_SPI_ErrorCallback(hspi);
-}
-
-/**
-  * @brief  DMA SPI Tx communication abort callback, when initiated by user
-  *         (To be called at end of DMA Tx Abort procedure following user abort request).
-  * @note   When this callback is executed, User Abort complete call back is called only if no
-  *         Abort still ongoing for Rx DMA Handle.
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  hspi->hdmatx->XferAbortCallback = NULL;
-
-  /* Disable Tx DMA Request */
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
-  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
-  {
-    hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
-  }
-
-  /* Disable SPI Peripheral */
-  __HAL_SPI_DISABLE(hspi);
-
-  /* Empty the FRLVL fifo */
-  if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
-  {
-    hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
-  }
-
-  /* Check if an Abort process is still ongoing */
-  if (hspi->hdmarx != NULL)
-  {
-    if (hspi->hdmarx->XferAbortCallback != NULL)
-    {
-      return;
-    }
-  }
-
-  /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
-  hspi->RxXferCount = 0U;
-  hspi->TxXferCount = 0U;
-
-  /* Check no error during Abort procedure */
-  if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
-  {
-    /* Reset errorCode */
-    hspi->ErrorCode = HAL_SPI_ERROR_NONE;
-  }
-
-  /* Clear the Error flags in the SR register */
-  __HAL_SPI_CLEAR_OVRFLAG(hspi);
-  __HAL_SPI_CLEAR_FREFLAG(hspi);
-
-  /* Restore hspi->State to Ready */
-  hspi->State  = HAL_SPI_STATE_READY;
-
-  /* Call user Abort complete callback */
-  HAL_SPI_AbortCpltCallback(hspi);
-}
-
-/**
-  * @brief  DMA SPI Rx communication abort callback, when initiated by user
-  *         (To be called at end of DMA Rx Abort procedure following user abort request).
-  * @note   When this callback is executed, User Abort complete call back is called only if no
-  *         Abort still ongoing for Tx DMA Handle.
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  /* Disable SPI Peripheral */
-  __HAL_SPI_DISABLE(hspi);
-
-  hspi->hdmarx->XferAbortCallback = NULL;
-
-  /* Disable Rx DMA Request */
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-
-  /* Control the BSY flag */
-  if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
-  {
-    hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
-  }
-
-  /* Empty the FRLVL fifo */
-  if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
-  {
-    hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
-  }
-
-  /* Check if an Abort process is still ongoing */
-  if (hspi->hdmatx != NULL)
-  {
-    if (hspi->hdmatx->XferAbortCallback != NULL)
-    {
-      return;
-    }
-  }
-
-  /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
-  hspi->RxXferCount = 0U;
-  hspi->TxXferCount = 0U;
-
-  /* Check no error during Abort procedure */
-  if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
-  {
-    /* Reset errorCode */
-    hspi->ErrorCode = HAL_SPI_ERROR_NONE;
-  }
-
-  /* Clear the Error flags in the SR register */
-  __HAL_SPI_CLEAR_OVRFLAG(hspi);
-  __HAL_SPI_CLEAR_FREFLAG(hspi);
-
-  /* Restore hspi->State to Ready */
-  hspi->State  = HAL_SPI_STATE_READY;
-
-  /* Call user Abort complete callback */
-  HAL_SPI_AbortCpltCallback(hspi);
-}
-
-/**
-  * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
-{
-  /* Receive data in packing mode */
-  if (hspi->RxXferCount > 1U)
-  {
-    *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
-    hspi->pRxBuffPtr += sizeof(uint16_t);
-    hspi->RxXferCount -= 2U;
-    if (hspi->RxXferCount == 1U)
-    {
-      /* set fiforxthreshold according the reception data length: 8bit */
-      SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-    }
-  }
-  /* Receive data in 8 Bit mode */
-  else
-  {
-    *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR);
-    hspi->RxXferCount--;
-  }
-
-  /* check end of the reception */
-  if (hspi->RxXferCount == 0U)
-  {
-#if (USE_SPI_CRC != 0U)
-    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-      hspi->RxISR =  SPI_2linesRxISR_8BITCRC;
-      return;
-    }
-#endif /* USE_SPI_CRC */
-
-    /* Disable RXNE  and ERR interrupt */
-    __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
-    if (hspi->TxXferCount == 0U)
-    {
-      SPI_CloseRxTx_ISR(hspi);
-    }
-  }
-}
-
-#if (USE_SPI_CRC != 0U)
-/**
-  * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
-{
-  __IO uint8_t tmpreg = 0U;
-
-  /* Read data register to flush CRC */
-  tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
-
-  /* To avoid GCC warning */
-  UNUSED(tmpreg);
-
-  hspi->CRCSize--;
-
-  /* check end of the reception */
-  if (hspi->CRCSize == 0U)
-  {
-    /* Disable RXNE and ERR interrupt */
-    __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
-    if (hspi->TxXferCount == 0U)
-    {
-      SPI_CloseRxTx_ISR(hspi);
-    }
-  }
-}
-#endif /* USE_SPI_CRC */
-
-/**
-  * @brief  Tx 8-bit handler for Transmit and Receive in Interrupt mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
-{
-  /* Transmit data in packing Bit mode */
-  if (hspi->TxXferCount >= 2U)
-  {
-    hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
-    hspi->pTxBuffPtr += sizeof(uint16_t);
-    hspi->TxXferCount -= 2U;
-  }
-  /* Transmit data in 8 Bit mode */
-  else
-  {
-    *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
-    hspi->TxXferCount--;
-  }
-
-  /* check the end of the transmission */
-  if (hspi->TxXferCount == 0U)
-  {
-#if (USE_SPI_CRC != 0U)
-    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      /* Set CRC Next Bit to send CRC */
-      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-      /* Disable TXE interrupt */
-      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
-      return;
-    }
-#endif /* USE_SPI_CRC */
-
-    /* Disable TXE interrupt */
-    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
-
-    if (hspi->RxXferCount == 0U)
-    {
-      SPI_CloseRxTx_ISR(hspi);
-    }
-  }
-}
-
-/**
-  * @brief  Rx 16-bit handler for Transmit and Receive in Interrupt mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
-{
-  /* Receive data in 16 Bit mode */
-  *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
-  hspi->pRxBuffPtr += sizeof(uint16_t);
-  hspi->RxXferCount--;
-
-  if (hspi->RxXferCount == 0U)
-  {
-#if (USE_SPI_CRC != 0U)
-    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      hspi->RxISR =  SPI_2linesRxISR_16BITCRC;
-      return;
-    }
-#endif /* USE_SPI_CRC */
-
-    /* Disable RXNE interrupt */
-    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
-
-    if (hspi->TxXferCount == 0U)
-    {
-      SPI_CloseRxTx_ISR(hspi);
-    }
-  }
-}
-
-#if (USE_SPI_CRC != 0U)
-/**
-  * @brief  Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
-{
-  /* Receive data in 16 Bit mode */
-  __IO uint16_t tmpreg = 0U;
-
-  /* Read data register to flush CRC */
-  tmpreg = hspi->Instance->DR;
-
-  /* To avoid GCC warning */
-  UNUSED(tmpreg);
-
-  /* Disable RXNE interrupt */
-  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
-
-  SPI_CloseRxTx_ISR(hspi);
-}
-#endif /* USE_SPI_CRC */
-
-/**
-  * @brief  Tx 16-bit handler for Transmit and Receive in Interrupt mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
-{
-  /* Transmit data in 16 Bit mode */
-  hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
-  hspi->pTxBuffPtr += sizeof(uint16_t);
-  hspi->TxXferCount--;
-
-  /* Enable CRC Transmission */
-  if (hspi->TxXferCount == 0U)
-  {
-#if (USE_SPI_CRC != 0U)
-    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      /* Set CRC Next Bit to send CRC */
-      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-      /* Disable TXE interrupt */
-      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
-      return;
-    }
-#endif /* USE_SPI_CRC */
-
-    /* Disable TXE interrupt */
-    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
-
-    if (hspi->RxXferCount == 0U)
-    {
-      SPI_CloseRxTx_ISR(hspi);
-    }
-  }
-}
-
-#if (USE_SPI_CRC != 0U)
-/**
-  * @brief  Manage the CRC 8-bit receive in Interrupt context.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
-{
-  __IO uint8_t tmpreg = 0U;
-
-  /* Read data register to flush CRC */
-  tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
-
-  /* To avoid GCC warning */
-  UNUSED(tmpreg);
-
-  hspi->CRCSize--;
-
-  if (hspi->CRCSize == 0U)
-  {
-    SPI_CloseRx_ISR(hspi);
-  }
-}
-#endif /* USE_SPI_CRC */
-
-/**
-  * @brief  Manage the receive 8-bit in Interrupt context.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
-{
-  *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);
-  hspi->RxXferCount--;
-
-#if (USE_SPI_CRC != 0U)
-  /* Enable CRC Transmission */
-  if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
-  {
-    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-  }
-#endif /* USE_SPI_CRC */
-
-  if (hspi->RxXferCount == 0U)
-  {
-#if (USE_SPI_CRC != 0U)
-    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      hspi->RxISR =  SPI_RxISR_8BITCRC;
-      return;
-    }
-#endif /* USE_SPI_CRC */
-    SPI_CloseRx_ISR(hspi);
-  }
-}
-
-#if (USE_SPI_CRC != 0U)
-/**
-  * @brief  Manage the CRC 16-bit receive in Interrupt context.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
-{
-  __IO uint16_t tmpreg = 0U;
-
-  /* Read data register to flush CRC */
-  tmpreg = hspi->Instance->DR;
-
-  /* To avoid GCC warning */
-  UNUSED(tmpreg);
-
-  /* Disable RXNE and ERR interrupt */
-  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
-  SPI_CloseRx_ISR(hspi);
-}
-#endif /* USE_SPI_CRC */
-
-/**
-  * @brief  Manage the 16-bit receive in Interrupt context.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
-{
-  *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
-  hspi->pRxBuffPtr += sizeof(uint16_t);
-  hspi->RxXferCount--;
-
-#if (USE_SPI_CRC != 0U)
-  /* Enable CRC Transmission */
-  if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
-  {
-    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-  }
-#endif /* USE_SPI_CRC */
-
-  if (hspi->RxXferCount == 0U)
-  {
-#if (USE_SPI_CRC != 0U)
-    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      hspi->RxISR = SPI_RxISR_16BITCRC;
-      return;
-    }
-#endif /* USE_SPI_CRC */
-    SPI_CloseRx_ISR(hspi);
-  }
-}
-
-/**
-  * @brief  Handle the data 8-bit transmit in Interrupt mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
-{
-  *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
-  hspi->TxXferCount--;
-
-  if (hspi->TxXferCount == 0U)
-  {
-#if (USE_SPI_CRC != 0U)
-    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      /* Enable CRC Transmission */
-      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-    }
-#endif /* USE_SPI_CRC */
-    SPI_CloseTx_ISR(hspi);
-  }
-}
-
-/**
-  * @brief  Handle the data 16-bit transmit in Interrupt mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
-{
-  /* Transmit data in 16 Bit mode */
-  hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
-  hspi->pTxBuffPtr += sizeof(uint16_t);
-  hspi->TxXferCount--;
-
-  if (hspi->TxXferCount == 0U)
-  {
-#if (USE_SPI_CRC != 0U)
-    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      /* Enable CRC Transmission */
-      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-    }
-#endif /* USE_SPI_CRC */
-    SPI_CloseTx_ISR(hspi);
-  }
-}
-
-/**
-  * @brief Handle SPI Communication Timeout.
-  * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *              the configuration information for SPI module.
-  * @param Flag: SPI flag to check
-  * @param State: flag state to check
-  * @param Timeout: Timeout duration
-  * @param Tickstart: tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State,
-                                                       uint32_t Timeout, uint32_t Tickstart)
-{
-  while ((hspi->Instance->SR & Flag) != State)
-  {
-    if (Timeout != HAL_MAX_DELAY)
-    {
-      if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) >= Timeout))
-      {
-        /* Disable the SPI and reset the CRC: the CRC value should be cleared
-        on both master and slave sides in order to resynchronize the master
-        and slave for their respective CRC calculation */
-
-        /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
-        __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
-
-        if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
-                                                     || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
-        {
-          /* Disable SPI peripheral */
-          __HAL_SPI_DISABLE(hspi);
-        }
-
-        /* Reset CRC Calculation */
-        if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-        {
-          SPI_RESET_CRC(hspi);
-        }
-
-        hspi->State = HAL_SPI_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hspi);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Handle SPI FIFO Communication Timeout.
-  * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *              the configuration information for SPI module.
-  * @param Fifo: Fifo to check
-  * @param State: Fifo state to check
-  * @param Timeout: Timeout duration
-  * @param Tickstart: tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
-                                                       uint32_t Timeout, uint32_t Tickstart)
-{
-  __IO uint8_t tmpreg;
-
-  while ((hspi->Instance->SR & Fifo) != State)
-  {
-    if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
-    {
-      tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
-      /* To avoid GCC warning */
-      UNUSED(tmpreg);
-    }
-
-    if (Timeout != HAL_MAX_DELAY)
-    {
-      if ((Timeout == 0) || ((HAL_GetTick() - Tickstart) >= Timeout))
-      {
-        /* Disable the SPI and reset the CRC: the CRC value should be cleared
-           on both master and slave sides in order to resynchronize the master
-           and slave for their respective CRC calculation */
-
-        /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
-        __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
-
-        if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
-                                                     || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
-        {
-          /* Disable SPI peripheral */
-          __HAL_SPI_DISABLE(hspi);
-        }
-
-        /* Reset CRC Calculation */
-        if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-        {
-          SPI_RESET_CRC(hspi);
-        }
-
-        hspi->State = HAL_SPI_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hspi);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle the check of the RX transaction complete.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  Timeout: Timeout duration
-  * @param  Tickstart: tick start value
-  * @retval None.
-  */
-static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi,  uint32_t Timeout, uint32_t Tickstart)
-{
-  if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
-                                               || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
-  {
-    /* Disable SPI peripheral */
-    __HAL_SPI_DISABLE(hspi);
-  }
-
-  /* Control the BSY flag */
-  if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
-  {
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-    return HAL_TIMEOUT;
-  }
-
-  if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
-                                               || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
-  {
-    /* Empty the FRLVL fifo */
-    if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-      return HAL_TIMEOUT;
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief Handle the check of the RXTX or TX transaction complete.
-  * @param hspi: SPI handle
-  * @param Timeout: Timeout duration
-  * @param Tickstart: tick start value
-  */
-static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
-{
-  /* Control if the TX fifo is empty */
-  if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
-  {
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-    return HAL_TIMEOUT;
-  }
-  /* Control the BSY flag */
-  if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
-  {
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-    return HAL_TIMEOUT;
-  }
-  /* Control if the RX fifo is empty */
-  if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
-  {
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-    return HAL_TIMEOUT;
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle the end of the RXTX transaction.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
-{
-  uint32_t tickstart = 0U;
-
-  /* Init tickstart for timeout managment*/
-  tickstart = HAL_GetTick();
-
-  /* Disable ERR interrupt */
-  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
-
-  /* Check the end of the transaction */
-  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
-  {
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-  }
-
-#if (USE_SPI_CRC != 0U)
-  /* Check if CRC error occurred */
-  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
-  {
-    hspi->State = HAL_SPI_STATE_READY;
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-    HAL_SPI_ErrorCallback(hspi);
-  }
-  else
-  {
-#endif /* USE_SPI_CRC */
-    if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
-    {
-      if (hspi->State == HAL_SPI_STATE_BUSY_RX)
-      {
-        hspi->State = HAL_SPI_STATE_READY;
-        HAL_SPI_RxCpltCallback(hspi);
-      }
-      else
-      {
-        hspi->State = HAL_SPI_STATE_READY;
-        HAL_SPI_TxRxCpltCallback(hspi);
-      }
-    }
-    else
-    {
-      hspi->State = HAL_SPI_STATE_READY;
-      HAL_SPI_ErrorCallback(hspi);
-    }
-#if (USE_SPI_CRC != 0U)
-  }
-#endif /* USE_SPI_CRC */
-}
-
-/**
-  * @brief  Handle the end of the RX transaction.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
-{
-  /* Disable RXNE and ERR interrupt */
-  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
-  /* Check the end of the transaction */
-  if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
-  {
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-  }
-  hspi->State = HAL_SPI_STATE_READY;
-
-#if (USE_SPI_CRC != 0U)
-  /* Check if CRC error occurred */
-  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
-  {
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-    HAL_SPI_ErrorCallback(hspi);
-  }
-  else
-  {
-#endif /* USE_SPI_CRC */
-    if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
-    {
-      HAL_SPI_RxCpltCallback(hspi);
-    }
-    else
-    {
-      HAL_SPI_ErrorCallback(hspi);
-    }
-#if (USE_SPI_CRC != 0U)
-  }
-#endif /* USE_SPI_CRC */
-}
-
-/**
-  * @brief  Handle the end of the TX transaction.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
-{
-  uint32_t tickstart = 0U;
-
-  /* Init tickstart for timeout management*/
-  tickstart = HAL_GetTick();
-
-  /* Disable TXE and ERR interrupt */
-  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
-
-  /* Check the end of the transaction */
-  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
-  {
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-  }
-
-  /* Clear overrun flag in 2 Lines communication mode because received is not read */
-  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
-  {
-    __HAL_SPI_CLEAR_OVRFLAG(hspi);
-  }
-
-  hspi->State = HAL_SPI_STATE_READY;
-  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
-  {
-    HAL_SPI_ErrorCallback(hspi);
-  }
-  else
-  {
-    HAL_SPI_TxCpltCallback(hspi);
-  }
-}
-
-/**
-  * @brief  Handle abort a Rx transaction.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
-{
-  /* Disable SPI Peripheral */
-  __HAL_SPI_DISABLE(hspi);
-
-  /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
-  CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
-
-  while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
-
-  /* Control the BSY flag */
-  if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
-  {
-    hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
-  }
-
-  /* Empty the FRLVL fifo */
-  if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
-  {
-    hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
-  }
-
-  hspi->State = HAL_SPI_STATE_ABORT;
-}
-
-/**
-  * @brief  Handle abort a Tx or Rx/Tx transaction.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
-{
-  /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
-  CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
-
-  while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
-
-  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
-  {
-    hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
-  }
-
-  /* Disable SPI Peripheral */
-  __HAL_SPI_DISABLE(hspi);
-
-  /* Empty the FRLVL fifo */
-  if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
-  {
-    hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
-  }
-
-  hspi->State = HAL_SPI_STATE_ABORT;
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_tim.c b/stmhal/hal/f7/src/stm32f7xx_hal_tim.c
deleted file mode 100644
index 3a6d7a9c98..0000000000
--- a/stmhal/hal/f7/src/stm32f7xx_hal_tim.c
+++ /dev/null
@@ -1,5521 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_tim.c
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   TIM HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Timer (TIM) peripheral:
-  *           + Time Base Initialization
-  *           + Time Base Start
-  *           + Time Base Start Interruption
-  *           + Time Base Start DMA
-  *           + Time Output Compare/PWM Initialization
-  *           + Time Output Compare/PWM Channel Configuration
-  *           + Time Output Compare/PWM  Start
-  *           + Time Output Compare/PWM  Start Interruption
-  *           + Time Output Compare/PWM Start DMA
-  *           + Time Input Capture Initialization
-  *           + Time Input Capture Channel Configuration
-  *           + Time Input Capture Start
-  *           + Time Input Capture Start Interruption
-  *           + Time Input Capture Start DMA
-  *           + Time One Pulse Initialization
-  *           + Time One Pulse Channel Configuration
-  *           + Time One Pulse Start
-  *           + Time Encoder Interface Initialization
-  *           + Time Encoder Interface Start
-  *           + Time Encoder Interface Start Interruption
-  *           + Time Encoder Interface Start DMA
-  *           + Commutation Event configuration with Interruption and DMA
-  *           + Time OCRef clear configuration
-  *           + Time External Clock configuration
-  @verbatim
-  ==============================================================================
-                      ##### TIMER Generic features #####
-  ==============================================================================
-  [..] The Timer features include:
-       (#) 16-bit up, down, up/down auto-reload counter.
-       (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
-           counter clock frequency either by any factor between 1 and 65536.
-       (#) Up to 4 independent channels for:
-           (++) Input Capture
-           (++) Output Compare
-           (++) PWM generation (Edge and Center-aligned Mode)
-           (++) One-pulse mode output
-
-                        ##### How to use this driver #####
-  ==============================================================================
-    [..]
-     (#) Initialize the TIM low level resources by implementing the following functions
-         depending from feature used :
-           (++) Time Base : HAL_TIM_Base_MspInit()
-           (++) Input Capture : HAL_TIM_IC_MspInit()
-           (++) Output Compare : HAL_TIM_OC_MspInit()
-           (++) PWM generation : HAL_TIM_PWM_MspInit()
-           (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
-           (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
-
-     (#) Initialize the TIM low level resources :
-        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
-        (##) TIM pins configuration
-            (+++) Enable the clock for the TIM GPIOs using the following function:
-                 __HAL_RCC_GPIOx_CLK_ENABLE();
-            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
-
-     (#) The external Clock can be configured, if needed (the default clock is the
-         internal clock from the APBx), using the following function:
-         HAL_TIM_ConfigClockSource, the clock configuration should be done before
-         any start function.
-
-     (#) Configure the TIM in the desired functioning mode using one of the
-         initialization function of this driver:
-         (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
-         (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
-              Output Compare signal.
-         (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
-              PWM signal.
-         (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
-              external signal.
-         (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
-              in One Pulse Mode.
-         (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
-
-     (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
-           (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
-           (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
-           (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
-           (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
-           (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
-           (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
-
-     (#) The DMA Burst is managed with the two following functions:
-         HAL_TIM_DMABurst_WriteStart()
-         HAL_TIM_DMABurst_ReadStart()
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup TIM TIM
-  * @brief TIM HAL module driver
-  * @{
-  */
-
-#ifdef HAL_TIM_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @addtogroup TIM_Private_Functions
-  * @{
-  */
-/* Private function prototypes -----------------------------------------------*/
-static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
-static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                       uint32_t TIM_ICFilter);
-static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
-static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                       uint32_t TIM_ICFilter);
-static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                       uint32_t TIM_ICFilter);
-
-static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t TIM_ITRx);
-static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
-static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
-static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
-                                     TIM_SlaveConfigTypeDef * sSlaveConfig);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup TIM_Exported_Functions TIM Exported Functions
-  * @{
-  */
-
-/** @defgroup TIM_Exported_Functions_Group1 Time Base functions
- *  @brief    Time Base functions
- *
-@verbatim
-  ==============================================================================
-              ##### Time Base functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Initialize and configure the TIM base.
-    (+) De-initialize the TIM base.
-    (+) Start the Time Base.
-    (+) Stop the Time Base.
-    (+) Start the Time Base and enable interrupt.
-    (+) Stop the Time Base and disable interrupt.
-    (+) Start the Time Base and enable DMA transfer.
-    (+) Stop the Time Base and disable DMA transfer.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIM Time base Unit according to the specified
-  *         parameters in the TIM_HandleTypeDef and create the associated handle.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
-{
-  /* Check the TIM handle allocation */
-  if(htim == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-
-  if(htim->State == HAL_TIM_STATE_RESET)
-  {
-    /* Init the low level hardware : GPIO, CLOCK, NVIC */
-    HAL_TIM_Base_MspInit(htim);
-  }
-
-  /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;
-
-  /* Set the Time Base configuration */
-  TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
-  /* Initialize the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the TIM Base peripheral
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Disable the TIM Peripheral Clock */
-  __HAL_TIM_DISABLE(htim);
-
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
-  HAL_TIM_Base_MspDeInit(htim);
-
-  /* Change TIM state */
-  htim->State = HAL_TIM_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM Base MSP.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_Base_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes TIM Base MSP.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_Base_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Starts the TIM Base generation.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Change the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Base generation.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Change the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Base generation in interrupt mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  /* Enable the TIM Update interrupt */
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Base generation in interrupt mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  /* Disable the TIM Update interrupt */
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Base generation in DMA mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  pData: The source Buffer address.
-  * @param  Length: The length of data to be transferred from memory to peripheral.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
-
-  if((htim->State == HAL_TIM_STATE_BUSY))
-  {
-     return HAL_BUSY;
-  }
-  else if((htim->State == HAL_TIM_STATE_READY))
-  {
-    if((pData == 0 ) && (Length > 0))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      htim->State = HAL_TIM_STATE_BUSY;
-    }
-  }
-  /* Set the DMA Period elapsed callback */
-  htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
-
-  /* Set the DMA error callback */
-  htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
-
-  /* Enable the DMA Stream */
-  HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
-
-  /* Enable the TIM Update DMA request */
-  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Base generation in DMA mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
-
-  /* Disable the TIM Update DMA request */
-  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Change the htim state */
-  htim->State = HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
- *  @brief    Time Output Compare functions
- *
-@verbatim
-  ==============================================================================
-                  ##### Time Output Compare functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Initialize and configure the TIM Output Compare.
-    (+) De-initialize the TIM Output Compare.
-    (+) Start the Time Output Compare.
-    (+) Stop the Time Output Compare.
-    (+) Start the Time Output Compare and enable interrupt.
-    (+) Stop the Time Output Compare and disable interrupt.
-    (+) Start the Time Output Compare and enable DMA transfer.
-    (+) Stop the Time Output Compare and disable DMA transfer.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIM Output Compare according to the specified
-  *         parameters in the TIM_HandleTypeDef and create the associated handle.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
-{
-  /* Check the TIM handle allocation */
-  if(htim == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-
-  if(htim->State == HAL_TIM_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    htim->Lock = HAL_UNLOCKED;
-    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
-    HAL_TIM_OC_MspInit(htim);
-  }
-
-  /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;
-
-  /* Init the base time for the Output Compare */
-  TIM_Base_SetConfig(htim->Instance,  &htim->Init);
-
-  /* Initialize the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the TIM peripheral
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-   htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Disable the TIM Peripheral Clock */
-  __HAL_TIM_DISABLE(htim);
-
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
-  HAL_TIM_OC_MspDeInit(htim);
-
-  /* Change TIM state */
-  htim->State = HAL_TIM_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM Output Compare MSP.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_OC_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes TIM Output Compare MSP.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_OC_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Starts the TIM Output Compare signal generation.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  /* Enable the Output compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
-  {
-    /* Enable the main output */
-    __HAL_TIM_MOE_ENABLE(htim);
-  }
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Output Compare signal generation.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be disabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  /* Disable the Output compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
-  {
-    /* Disable the Main Output */
-    __HAL_TIM_MOE_DISABLE(htim);
-  }
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Output Compare signal generation in interrupt mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Enable the TIM Capture/Compare 1 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Enable the TIM Capture/Compare 2 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Enable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Enable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Enable the Output compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
-  {
-    /* Enable the main output */
-    __HAL_TIM_MOE_ENABLE(htim);
-  }
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Output Compare signal generation in interrupt mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be disabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Disable the TIM Capture/Compare 1 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Capture/Compare 2 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Disable the Output compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
-  {
-    /* Disable the Main Output */
-    __HAL_TIM_MOE_DISABLE(htim);
-  }
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Output Compare signal generation in DMA mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  pData: The source Buffer address.
-  * @param  Length: The length of data to be transferred from memory to TIM peripheral
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  if((htim->State == HAL_TIM_STATE_BUSY))
-  {
-     return HAL_BUSY;
-  }
-  else if((htim->State == HAL_TIM_STATE_READY))
-  {
-    if(((uint32_t)pData == 0 ) && (Length > 0))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      htim->State = HAL_TIM_STATE_BUSY;
-    }
-  }
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
-
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
-
-      /* Enable the TIM Capture/Compare 1 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
-
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
-
-      /* Enable the TIM Capture/Compare 2 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
-
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-
-      /* Enable the TIM Capture/Compare 3 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-     /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
-
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-
-      /* Enable the TIM Capture/Compare 4 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Enable the Output compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
-  {
-    /* Enable the main output */
-    __HAL_TIM_MOE_ENABLE(htim);
-  }
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Output Compare signal generation in DMA mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be disabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Disable the TIM Capture/Compare 1 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Capture/Compare 2 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Capture/Compare 3 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Disable the Output compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
-  {
-    /* Disable the Main Output */
-    __HAL_TIM_MOE_DISABLE(htim);
-  }
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Change the htim state */
-  htim->State = HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
- *  @brief    Time PWM functions
- *
-@verbatim
-  ==============================================================================
-                          ##### Time PWM functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Initialize and configure the TIM OPWM.
-    (+) De-initialize the TIM PWM.
-    (+) Start the Time PWM.
-    (+) Stop the Time PWM.
-    (+) Start the Time PWM and enable interrupt.
-    (+) Stop the Time PWM and disable interrupt.
-    (+) Start the Time PWM and enable DMA transfer.
-    (+) Stop the Time PWM and disable DMA transfer.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIM PWM Time Base according to the specified
-  *         parameters in the TIM_HandleTypeDef and create the associated handle.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
-{
-  /* Check the TIM handle allocation */
-  if(htim == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-
-  if(htim->State == HAL_TIM_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    htim->Lock = HAL_UNLOCKED;
-    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
-    HAL_TIM_PWM_MspInit(htim);
-  }
-
-  /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;
-
-  /* Init the base time for the PWM */
-  TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
-  /* Initialize the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the TIM peripheral
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Disable the TIM Peripheral Clock */
-  __HAL_TIM_DISABLE(htim);
-
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
-  HAL_TIM_PWM_MspDeInit(htim);
-
-  /* Change TIM state */
-  htim->State = HAL_TIM_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM PWM MSP.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_PWM_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes TIM PWM MSP.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_PWM_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Starts the PWM signal generation.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  /* Enable the Capture compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
-  {
-    /* Enable the main output */
-    __HAL_TIM_MOE_ENABLE(htim);
-  }
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the PWM signal generation.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be disabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  /* Disable the Capture compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
-  {
-    /* Disable the Main Output */
-    __HAL_TIM_MOE_DISABLE(htim);
-  }
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Change the htim state */
-  htim->State = HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the PWM signal generation in interrupt mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Enable the TIM Capture/Compare 1 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Enable the TIM Capture/Compare 2 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Enable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Enable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Enable the Capture compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
-  {
-    /* Enable the main output */
-    __HAL_TIM_MOE_ENABLE(htim);
-  }
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the PWM signal generation in interrupt mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be disabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Disable the TIM Capture/Compare 1 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Capture/Compare 2 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Disable the Capture compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
-  {
-    /* Disable the Main Output */
-    __HAL_TIM_MOE_DISABLE(htim);
-  }
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM PWM signal generation in DMA mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  pData: The source Buffer address.
-  * @param  Length: The length of data to be transferred from memory to TIM peripheral
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  if((htim->State == HAL_TIM_STATE_BUSY))
-  {
-     return HAL_BUSY;
-  }
-  else if((htim->State == HAL_TIM_STATE_READY))
-  {
-    if(((uint32_t)pData == 0 ) && (Length > 0))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      htim->State = HAL_TIM_STATE_BUSY;
-    }
-  }
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
-
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
-
-      /* Enable the TIM Capture/Compare 1 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
-
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
-
-      /* Enable the TIM Capture/Compare 2 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
-
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-
-      /* Enable the TIM Output Capture/Compare 3 request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-     /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
-
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-
-      /* Enable the TIM Capture/Compare 4 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Enable the Capture compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
-  {
-    /* Enable the main output */
-    __HAL_TIM_MOE_ENABLE(htim);
-  }
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM PWM signal generation in DMA mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be disabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Disable the TIM Capture/Compare 1 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Capture/Compare 2 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Capture/Compare 3 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Disable the Capture compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
-  {
-    /* Disable the Main Output */
-    __HAL_TIM_MOE_DISABLE(htim);
-  }
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Change the htim state */
-  htim->State = HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
- *  @brief    Time Input Capture functions
- *
-@verbatim
-  ==============================================================================
-              ##### Time Input Capture functions #####
-  ==============================================================================
- [..]
-   This section provides functions allowing to:
-   (+) Initialize and configure the TIM Input Capture.
-   (+) De-initialize the TIM Input Capture.
-   (+) Start the Time Input Capture.
-   (+) Stop the Time Input Capture.
-   (+) Start the Time Input Capture and enable interrupt.
-   (+) Stop the Time Input Capture and disable interrupt.
-   (+) Start the Time Input Capture and enable DMA transfer.
-   (+) Stop the Time Input Capture and disable DMA transfer.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIM Input Capture Time base according to the specified
-  *         parameters in the TIM_HandleTypeDef and create the associated handle.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
-{
-  /* Check the TIM handle allocation */
-  if(htim == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-
-  if(htim->State == HAL_TIM_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    htim->Lock = HAL_UNLOCKED;
-    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
-    HAL_TIM_IC_MspInit(htim);
-  }
-
-  /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;
-
-  /* Init the base time for the input capture */
-  TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
-  /* Initialize the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the TIM peripheral
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Disable the TIM Peripheral Clock */
-  __HAL_TIM_DISABLE(htim);
-
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
-  HAL_TIM_IC_MspDeInit(htim);
-
-  /* Change TIM state */
-  htim->State = HAL_TIM_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM INput Capture MSP.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_IC_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes TIM Input Capture MSP.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_IC_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Starts the TIM Input Capture measurement.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  /* Enable the Input Capture channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Input Capture measurement.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be disabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  /* Disable the Input Capture channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Input Capture measurement in interrupt mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Enable the TIM Capture/Compare 1 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Enable the TIM Capture/Compare 2 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Enable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Enable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-  /* Enable the Input Capture channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Input Capture measurement in interrupt mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be disabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Disable the TIM Capture/Compare 1 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Capture/Compare 2 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Disable the Input Capture channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Input Capture measurement on in DMA mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  pData: The destination Buffer address.
-  * @param  Length: The length of data to be transferred from TIM peripheral to memory.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-
-  if((htim->State == HAL_TIM_STATE_BUSY))
-  {
-     return HAL_BUSY;
-  }
-  else if((htim->State == HAL_TIM_STATE_READY))
-  {
-    if((pData == 0 ) && (Length > 0))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      htim->State = HAL_TIM_STATE_BUSY;
-    }
-  }
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
-
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
-
-      /* Enable the TIM Capture/Compare 1 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
-
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
-
-      /* Enable the TIM Capture/Compare 2  DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
-
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
-
-      /* Enable the TIM Capture/Compare 3  DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
-
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
-
-      /* Enable the TIM Capture/Compare 4  DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Enable the Input Capture channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Input Capture measurement on in DMA mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be disabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Disable the TIM Capture/Compare 1 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Capture/Compare 2 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Capture/Compare 3  DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 4  DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Disable the Input Capture channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Change the htim state */
-  htim->State = HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
- *  @brief    Time One Pulse functions
- *
-@verbatim
-  ==============================================================================
-                        ##### Time One Pulse functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Initialize and configure the TIM One Pulse.
-    (+) De-initialize the TIM One Pulse.
-    (+) Start the Time One Pulse.
-    (+) Stop the Time One Pulse.
-    (+) Start the Time One Pulse and enable interrupt.
-    (+) Stop the Time One Pulse and disable interrupt.
-    (+) Start the Time One Pulse and enable DMA transfer.
-    (+) Stop the Time One Pulse and disable DMA transfer.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIM One Pulse Time Base according to the specified
-  *         parameters in the TIM_HandleTypeDef and create the associated handle.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  OnePulseMode: Select the One pulse mode.
-  *         This parameter can be one of the following values:
-  *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
-  *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
-{
-  /* Check the TIM handle allocation */
-  if(htim == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-  assert_param(IS_TIM_OPM_MODE(OnePulseMode));
-
-  if(htim->State == HAL_TIM_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    htim->Lock = HAL_UNLOCKED;
-    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
-    HAL_TIM_OnePulse_MspInit(htim);
-  }
-
-  /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;
-
-  /* Configure the Time base in the One Pulse Mode */
-  TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
-  /* Reset the OPM Bit */
-  htim->Instance->CR1 &= ~TIM_CR1_OPM;
-
-  /* Configure the OPM Mode */
-  htim->Instance->CR1 |= OnePulseMode;
-
-  /* Initialize the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the TIM One Pulse
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Disable the TIM Peripheral Clock */
-  __HAL_TIM_DISABLE(htim);
-
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
-  HAL_TIM_OnePulse_MspDeInit(htim);
-
-  /* Change TIM state */
-  htim->State = HAL_TIM_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM One Pulse MSP.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_OnePulse_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes TIM One Pulse MSP.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Starts the TIM One Pulse signal generation.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  OutputChannel : TIM Channels to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
-  /* Enable the Capture compare and the Input Capture channels
-    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
-    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
-    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
-    in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
-
-    No need to enable the counter, it's enabled automatically by hardware
-    (the counter starts in response to a stimulus and generate a pulse */
-
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
-  {
-    /* Enable the main output */
-    __HAL_TIM_MOE_ENABLE(htim);
-  }
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM One Pulse signal generation.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  OutputChannel : TIM Channels to be disable.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
-  /* Disable the Capture compare and the Input Capture channels
-  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
-  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
-  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
-  in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
-
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
-  {
-    /* Disable the Main Output */
-    __HAL_TIM_MOE_DISABLE(htim);
-  }
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  OutputChannel : TIM Channels to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
-  /* Enable the Capture compare and the Input Capture channels
-    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
-    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
-    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
-    in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
-
-    No need to enable the counter, it's enabled automatically by hardware
-    (the counter starts in response to a stimulus and generate a pulse */
-
-  /* Enable the TIM Capture/Compare 1 interrupt */
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-
-  /* Enable the TIM Capture/Compare 2 interrupt */
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
-  {
-    /* Enable the main output */
-    __HAL_TIM_MOE_ENABLE(htim);
-  }
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  OutputChannel : TIM Channels to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
-  /* Disable the TIM Capture/Compare 1 interrupt */
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-
-  /* Disable the TIM Capture/Compare 2 interrupt */
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-
-  /* Disable the Capture compare and the Input Capture channels
-  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
-  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
-  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
-  in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
-  {
-    /* Disable the Main Output */
-    __HAL_TIM_MOE_DISABLE(htim);
-  }
-
-  /* Disable the Peripheral */
-   __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
- *  @brief    Time Encoder functions
- *
-@verbatim
-  ==============================================================================
-                          ##### Time Encoder functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Initialize and configure the TIM Encoder.
-    (+) De-initialize the TIM Encoder.
-    (+) Start the Time Encoder.
-    (+) Stop the Time Encoder.
-    (+) Start the Time Encoder and enable interrupt.
-    (+) Stop the Time Encoder and disable interrupt.
-    (+) Start the Time Encoder and enable DMA transfer.
-    (+) Stop the Time Encoder and disable DMA transfer.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIM Encoder Interface and create the associated handle.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  sConfig: TIM Encoder Interface configuration structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef* sConfig)
-{
-  uint32_t tmpsmcr = 0;
-  uint32_t tmpccmr1 = 0;
-  uint32_t tmpccer = 0;
-
-  /* Check the TIM handle allocation */
-  if(htim == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
-  assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
-  assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
-  assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
-  assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
-  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
-  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
-  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
-  assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
-
-  if(htim->State == HAL_TIM_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    htim->Lock = HAL_UNLOCKED;
-    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
-    HAL_TIM_Encoder_MspInit(htim);
-  }
-
-  /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;
-
-  /* Reset the SMS bits */
-  htim->Instance->SMCR &= ~TIM_SMCR_SMS;
-
-  /* Configure the Time base in the Encoder Mode */
-  TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
-  /* Get the TIMx SMCR register value */
-  tmpsmcr = htim->Instance->SMCR;
-
-  /* Get the TIMx CCMR1 register value */
-  tmpccmr1 = htim->Instance->CCMR1;
-
-  /* Get the TIMx CCER register value */
-  tmpccer = htim->Instance->CCER;
-
-  /* Set the encoder Mode */
-  tmpsmcr |= sConfig->EncoderMode;
-
-  /* Select the Capture Compare 1 and the Capture Compare 2 as input */
-  tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
-  tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
-
-  /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
-  tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
-  tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
-  tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);
-  tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);
-
-  /* Set the TI1 and the TI2 Polarities */
-  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
-  tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
-  tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);
-
-  /* Write to TIMx SMCR */
-  htim->Instance->SMCR = tmpsmcr;
-
-  /* Write to TIMx CCMR1 */
-  htim->Instance->CCMR1 = tmpccmr1;
-
-  /* Write to TIMx CCER */
-  htim->Instance->CCER = tmpccer;
-
-  /* Initialize the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the TIM Encoder interface
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Disable the TIM Peripheral Clock */
-  __HAL_TIM_DISABLE(htim);
-
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
-  HAL_TIM_Encoder_MspDeInit(htim);
-
-  /* Change TIM state */
-  htim->State = HAL_TIM_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM Encoder Interface MSP.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_Encoder_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes TIM Encoder Interface MSP.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Starts the TIM Encoder Interface.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-  /* Enable the encoder interface channels */
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-      break;
-    }
-    case TIM_CHANNEL_2:
-    {
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-      break;
-    }
-    default :
-    {
-     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-     break;
-    }
-  }
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Encoder Interface.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be disabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-    assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-   /* Disable the Input Capture channels 1 and 2
-    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-      break;
-    }
-    case TIM_CHANNEL_2:
-    {
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-      break;
-    }
-    default :
-    {
-     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-     break;
-    }
-  }
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Encoder Interface in interrupt mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-  /* Enable the encoder interface channels */
-  /* Enable the capture compare Interrupts 1 and/or 2 */
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-      break;
-    }
-    case TIM_CHANNEL_2:
-    {
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-      break;
-    }
-    default :
-    {
-     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-     __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-     __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-     break;
-    }
-  }
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Encoder Interface in interrupt mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be disabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-  /* Disable the Input Capture channels 1 and 2
-    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
-  if(Channel == TIM_CHANNEL_1)
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
-    /* Disable the capture compare Interrupts 1 */
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-  }
-  else if(Channel == TIM_CHANNEL_2)
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
-    /* Disable the capture compare Interrupts 2 */
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-  }
-  else
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
-    /* Disable the capture compare Interrupts 1 and 2 */
-    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-  }
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Change the htim state */
-  htim->State = HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Encoder Interface in DMA mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
-  * @param  pData1: The destination Buffer address for IC1.
-  * @param  pData2: The destination Buffer address for IC2.
-  * @param  Length: The length of data to be transferred from TIM peripheral to memory.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-
-  if((htim->State == HAL_TIM_STATE_BUSY))
-  {
-     return HAL_BUSY;
-  }
-  else if((htim->State == HAL_TIM_STATE_READY))
-  {
-    if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      htim->State = HAL_TIM_STATE_BUSY;
-    }
-  }
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
-
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
-
-      /* Enable the TIM Input Capture DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-
-      /* Enable the Peripheral */
-      __HAL_TIM_ENABLE(htim);
-
-      /* Enable the Capture compare channel */
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError;
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
-
-      /* Enable the TIM Input Capture  DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-
-      /* Enable the Peripheral */
-      __HAL_TIM_ENABLE(htim);
-
-      /* Enable the Capture compare channel */
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-    }
-    break;
-
-    case TIM_CHANNEL_ALL:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
-
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
-
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
-
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
-
-     /* Enable the Peripheral */
-      __HAL_TIM_ENABLE(htim);
-
-      /* Enable the Capture compare channel */
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-
-      /* Enable the TIM Input Capture  DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-      /* Enable the TIM Input Capture  DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-    }
-    break;
-
-    default:
-    break;
-  }
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Encoder Interface in DMA mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-
-  /* Disable the Input Capture channels 1 and 2
-    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
-  if(Channel == TIM_CHANNEL_1)
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
-    /* Disable the capture compare DMA Request 1 */
-    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-  }
-  else if(Channel == TIM_CHANNEL_2)
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
-    /* Disable the capture compare DMA Request 2 */
-    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
-  }
-  else
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
-    /* Disable the capture compare DMA Request 1 and 2 */
-    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
-  }
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Change the htim state */
-  htim->State = HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
- *  @brief    IRQ handler management
- *
-@verbatim
-  ==============================================================================
-                        ##### IRQ handler management #####
-  ==============================================================================
-  [..]
-    This section provides Timer IRQ handler function.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  This function handles TIM interrupts requests.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
-{
-  /* Capture compare 1 event */
-  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
-  {
-    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
-    {
-      {
-        __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
-        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-
-        /* Input capture event */
-        if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
-        {
-          HAL_TIM_IC_CaptureCallback(htim);
-        }
-        /* Output compare event */
-        else
-        {
-          HAL_TIM_OC_DelayElapsedCallback(htim);
-          HAL_TIM_PWM_PulseFinishedCallback(htim);
-        }
-        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-      }
-    }
-  }
-  /* Capture compare 2 event */
-  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
-  {
-    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
-    {
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-      /* Input capture event */
-      if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
-      {
-        HAL_TIM_IC_CaptureCallback(htim);
-      }
-      /* Output compare event */
-      else
-      {
-        HAL_TIM_OC_DelayElapsedCallback(htim);
-        HAL_TIM_PWM_PulseFinishedCallback(htim);
-      }
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-    }
-  }
-  /* Capture compare 3 event */
-  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
-  {
-    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
-    {
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-      /* Input capture event */
-      if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
-      {
-        HAL_TIM_IC_CaptureCallback(htim);
-      }
-      /* Output compare event */
-      else
-      {
-        HAL_TIM_OC_DelayElapsedCallback(htim);
-        HAL_TIM_PWM_PulseFinishedCallback(htim);
-      }
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-    }
-  }
-  /* Capture compare 4 event */
-  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
-  {
-    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
-    {
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-      /* Input capture event */
-      if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
-      {
-        HAL_TIM_IC_CaptureCallback(htim);
-      }
-      /* Output compare event */
-      else
-      {
-        HAL_TIM_OC_DelayElapsedCallback(htim);
-        HAL_TIM_PWM_PulseFinishedCallback(htim);
-      }
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-    }
-  }
-  /* TIM Update event */
-  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
-  {
-    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
-    {
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
-      HAL_TIM_PeriodElapsedCallback(htim);
-    }
-  }
-  /* TIM Break input event */
-  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
-  {
-    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
-    {
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
-      HAL_TIMEx_BreakCallback(htim);
-    }
-  }
-
-    /* TIM Break input event */
-  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
-  {
-    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
-    {
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
-      HAL_TIMEx_BreakCallback(htim);
-    }
-  }
-
-  /* TIM Trigger detection event */
-  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
-  {
-    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
-    {
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
-      HAL_TIM_TriggerCallback(htim);
-    }
-  }
-  /* TIM commutation event */
-  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
-  {
-    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
-    {
-      __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
-      HAL_TIMEx_CommutationCallback(htim);
-    }
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
- *  @brief   	Peripheral Control functions
- *
-@verbatim
-  ==============================================================================
-                   ##### Peripheral Control functions #####
-  ==============================================================================
- [..]
-   This section provides functions allowing to:
-   (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
-   (+) Configure External Clock source.
-   (+) Configure Complementary channels, break features and dead time.
-   (+) Configure Master and the Slave synchronization.
-   (+) Configure the DMA Burst Mode.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the TIM Output Compare Channels according to the specified
-  *         parameters in the TIM_OC_InitTypeDef.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  sConfig: TIM Output Compare configuration structure
-  * @param  Channel: TIM Channels to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-__weak HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CHANNELS(Channel));
-  assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
-  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
-
-  /* Check input state */
-  __HAL_LOCK(htim);
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-      /* Configure the TIM Channel 1 in Output Compare */
-      TIM_OC1_SetConfig(htim->Instance, sConfig);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-      /* Configure the TIM Channel 2 in Output Compare */
-      TIM_OC2_SetConfig(htim->Instance, sConfig);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-      /* Configure the TIM Channel 3 in Output Compare */
-      TIM_OC3_SetConfig(htim->Instance, sConfig);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-      /* Configure the TIM Channel 4 in Output Compare */
-      TIM_OC4_SetConfig(htim->Instance, sConfig);
-    }
-    break;
-
-    default:
-    break;
-  }
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM Input Capture Channels according to the specified
-  *         parameters in the TIM_IC_InitTypeDef.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  sConfig: TIM Input Capture configuration structure
-  * @param  Channel: TIM Channels to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
-  assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
-  assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
-  assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
-
-  __HAL_LOCK(htim);
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  if (Channel == TIM_CHANNEL_1)
-  {
-    /* TI1 Configuration */
-    TIM_TI1_SetConfig(htim->Instance,
-               sConfig->ICPolarity,
-               sConfig->ICSelection,
-               sConfig->ICFilter);
-
-    /* Reset the IC1PSC Bits */
-    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
-
-    /* Set the IC1PSC value */
-    htim->Instance->CCMR1 |= sConfig->ICPrescaler;
-  }
-  else if (Channel == TIM_CHANNEL_2)
-  {
-    /* TI2 Configuration */
-    assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-    TIM_TI2_SetConfig(htim->Instance,
-                      sConfig->ICPolarity,
-                      sConfig->ICSelection,
-                      sConfig->ICFilter);
-
-    /* Reset the IC2PSC Bits */
-    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
-
-    /* Set the IC2PSC value */
-    htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);
-  }
-  else if (Channel == TIM_CHANNEL_3)
-  {
-    /* TI3 Configuration */
-    assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
-    TIM_TI3_SetConfig(htim->Instance,
-               sConfig->ICPolarity,
-               sConfig->ICSelection,
-               sConfig->ICFilter);
-
-    /* Reset the IC3PSC Bits */
-    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
-
-    /* Set the IC3PSC value */
-    htim->Instance->CCMR2 |= sConfig->ICPrescaler;
-  }
-  else
-  {
-    /* TI4 Configuration */
-    assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
-    TIM_TI4_SetConfig(htim->Instance,
-               sConfig->ICPolarity,
-               sConfig->ICSelection,
-               sConfig->ICFilter);
-
-    /* Reset the IC4PSC Bits */
-    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
-
-    /* Set the IC4PSC value */
-    htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);
-  }
-
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM PWM  channels according to the specified
-  *         parameters in the TIM_OC_InitTypeDef.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  sConfig: TIM PWM configuration structure
-  * @param  Channel: TIM Channels to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-__weak HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
-{
-  __HAL_LOCK(htim);
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CHANNELS(Channel));
-  assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
-  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
-  assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-      /* Configure the Channel 1 in PWM mode */
-      TIM_OC1_SetConfig(htim->Instance, sConfig);
-
-      /* Set the Preload enable bit for channel1 */
-      htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
-
-      /* Configure the Output Fast mode */
-      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
-      htim->Instance->CCMR1 |= sConfig->OCFastMode;
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-      /* Configure the Channel 2 in PWM mode */
-      TIM_OC2_SetConfig(htim->Instance, sConfig);
-
-      /* Set the Preload enable bit for channel2 */
-      htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
-
-      /* Configure the Output Fast mode */
-      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
-      htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-      /* Configure the Channel 3 in PWM mode */
-      TIM_OC3_SetConfig(htim->Instance, sConfig);
-
-      /* Set the Preload enable bit for channel3 */
-      htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
-
-     /* Configure the Output Fast mode */
-      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
-      htim->Instance->CCMR2 |= sConfig->OCFastMode;
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-      /* Configure the Channel 4 in PWM mode */
-      TIM_OC4_SetConfig(htim->Instance, sConfig);
-
-      /* Set the Preload enable bit for channel4 */
-      htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
-
-     /* Configure the Output Fast mode */
-      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
-      htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM One Pulse Channels according to the specified
-  *         parameters in the TIM_OnePulse_InitTypeDef.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  sConfig: TIM One Pulse configuration structure
-  * @param  OutputChannel: TIM Channels to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @param  InputChannel: TIM Channels to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel,  uint32_t InputChannel)
-{
-  TIM_OC_InitTypeDef temp1;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
-  assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
-
-  if(OutputChannel != InputChannel)
-  {
-    __HAL_LOCK(htim);
-
-    htim->State = HAL_TIM_STATE_BUSY;
-
-    /* Extract the Output compare configuration from sConfig structure */
-    temp1.OCMode = sConfig->OCMode;
-    temp1.Pulse = sConfig->Pulse;
-    temp1.OCPolarity = sConfig->OCPolarity;
-    temp1.OCNPolarity = sConfig->OCNPolarity;
-    temp1.OCIdleState = sConfig->OCIdleState;
-    temp1.OCNIdleState = sConfig->OCNIdleState;
-
-    switch (OutputChannel)
-    {
-      case TIM_CHANNEL_1:
-      {
-        assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
-        TIM_OC1_SetConfig(htim->Instance, &temp1);
-      }
-      break;
-      case TIM_CHANNEL_2:
-      {
-        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-        TIM_OC2_SetConfig(htim->Instance, &temp1);
-      }
-      break;
-      default:
-      break;
-    }
-    switch (InputChannel)
-    {
-      case TIM_CHANNEL_1:
-      {
-        assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
-        TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
-                        sConfig->ICSelection, sConfig->ICFilter);
-
-        /* Reset the IC1PSC Bits */
-        htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
-
-        /* Select the Trigger source */
-        htim->Instance->SMCR &= ~TIM_SMCR_TS;
-        htim->Instance->SMCR |= TIM_TS_TI1FP1;
-
-        /* Select the Slave Mode */
-        htim->Instance->SMCR &= ~TIM_SMCR_SMS;
-        htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
-      }
-      break;
-      case TIM_CHANNEL_2:
-      {
-        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-        TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
-                 sConfig->ICSelection, sConfig->ICFilter);
-
-        /* Reset the IC2PSC Bits */
-        htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
-
-        /* Select the Trigger source */
-        htim->Instance->SMCR &= ~TIM_SMCR_TS;
-        htim->Instance->SMCR |= TIM_TS_TI2FP2;
-
-        /* Select the Slave Mode */
-        htim->Instance->SMCR &= ~TIM_SMCR_SMS;
-        htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
-      }
-      break;
-
-      default:
-      break;
-    }
-
-    htim->State = HAL_TIM_STATE_READY;
-
-    __HAL_UNLOCK(htim);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  BurstBaseAddress: TIM Base address from when the DMA will starts the Data write.
-  *         This parameters can be on of the following values:
-  *            @arg TIM_DMABASE_CR1
-  *            @arg TIM_DMABASE_CR2
-  *            @arg TIM_DMABASE_SMCR
-  *            @arg TIM_DMABASE_DIER
-  *            @arg TIM_DMABASE_SR
-  *            @arg TIM_DMABASE_EGR
-  *            @arg TIM_DMABASE_CCMR1
-  *            @arg TIM_DMABASE_CCMR2
-  *            @arg TIM_DMABASE_CCER
-  *            @arg TIM_DMABASE_CNT
-  *            @arg TIM_DMABASE_PSC
-  *            @arg TIM_DMABASE_ARR
-  *            @arg TIM_DMABASE_RCR
-  *            @arg TIM_DMABASE_CCR1
-  *            @arg TIM_DMABASE_CCR2
-  *            @arg TIM_DMABASE_CCR3
-  *            @arg TIM_DMABASE_CCR4
-  *            @arg TIM_DMABASE_BDTR
-  *            @arg TIM_DMABASE_DCR
-  * @param  BurstRequestSrc: TIM DMA Request sources.
-  *         This parameters can be on of the following values:
-  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
-  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
-  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
-  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
-  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
-  *            @arg TIM_DMA_COM: TIM Commutation DMA source
-  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
-  * @param  BurstBuffer: The Buffer address.
-  * @param  BurstLength: DMA Burst length. This parameter can be one value
-  *         between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
-                                              uint32_t* BurstBuffer, uint32_t  BurstLength)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
-  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
-  assert_param(IS_TIM_DMA_LENGTH(BurstLength));
-
-  if((htim->State == HAL_TIM_STATE_BUSY))
-  {
-     return HAL_BUSY;
-  }
-  else if((htim->State == HAL_TIM_STATE_READY))
-  {
-    if((BurstBuffer == 0 ) && (BurstLength > 0))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      htim->State = HAL_TIM_STATE_BUSY;
-    }
-  }
-  switch(BurstRequestSrc)
-  {
-    case TIM_DMA_UPDATE:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
-
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
-    }
-    break;
-    case TIM_DMA_CC1:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
-
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
-    }
-    break;
-    case TIM_DMA_CC2:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
-
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
-    }
-    break;
-    case TIM_DMA_CC3:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
-
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
-    }
-    break;
-    case TIM_DMA_CC4:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
-
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
-    }
-    break;
-    case TIM_DMA_COM:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
-
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
-    }
-    break;
-    case TIM_DMA_TRIGGER:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
-
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
-    }
-    break;
-    default:
-    break;
-  }
-   /* configure the DMA Burst Mode */
-   htim->Instance->DCR = BurstBaseAddress | BurstLength;
-
-   /* Enable the TIM DMA Request */
-   __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
-
-   htim->State = HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM DMA Burst mode
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  BurstRequestSrc: TIM DMA Request sources to disable
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
-
-  /* Abort the DMA transfer (at least disable the DMA channel) */
-  switch(BurstRequestSrc)
-  {
-    case TIM_DMA_UPDATE:
-    {
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
-    }
-    break;
-    case TIM_DMA_CC1:
-    {
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
-    }
-    break;
-    case TIM_DMA_CC2:
-    {
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
-    }
-    break;
-    case TIM_DMA_CC3:
-    {
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
-    }
-    break;
-    case TIM_DMA_CC4:
-    {
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
-    }
-    break;
-    case TIM_DMA_COM:
-    {
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
-    }
-    break;
-    case TIM_DMA_TRIGGER:
-    {
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
-    }
-    break;
-    default:
-    break;
-  }
-
-  /* Disable the TIM Update DMA request */
-  __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  BurstBaseAddress: TIM Base address from when the DMA will starts the Data read.
-  *         This parameters can be on of the following values:
-  *            @arg TIM_DMABASE_CR1
-  *            @arg TIM_DMABASE_CR2
-  *            @arg TIM_DMABASE_SMCR
-  *            @arg TIM_DMABASE_DIER
-  *            @arg TIM_DMABASE_SR
-  *            @arg TIM_DMABASE_EGR
-  *            @arg TIM_DMABASE_CCMR1
-  *            @arg TIM_DMABASE_CCMR2
-  *            @arg TIM_DMABASE_CCER
-  *            @arg TIM_DMABASE_CNT
-  *            @arg TIM_DMABASE_PSC
-  *            @arg TIM_DMABASE_ARR
-  *            @arg TIM_DMABASE_RCR
-  *            @arg TIM_DMABASE_CCR1
-  *            @arg TIM_DMABASE_CCR2
-  *            @arg TIM_DMABASE_CCR3
-  *            @arg TIM_DMABASE_CCR4
-  *            @arg TIM_DMABASE_BDTR
-  *            @arg TIM_DMABASE_DCR
-  * @param  BurstRequestSrc: TIM DMA Request sources.
-  *         This parameters can be on of the following values:
-  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
-  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
-  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
-  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
-  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
-  *            @arg TIM_DMA_COM: TIM Commutation DMA source
-  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
-  * @param  BurstBuffer: The Buffer address.
-  * @param  BurstLength: DMA Burst length. This parameter can be one value
-  *         between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
-                                             uint32_t  *BurstBuffer, uint32_t  BurstLength)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
-  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
-  assert_param(IS_TIM_DMA_LENGTH(BurstLength));
-
-  if((htim->State == HAL_TIM_STATE_BUSY))
-  {
-     return HAL_BUSY;
-  }
-  else if((htim->State == HAL_TIM_STATE_READY))
-  {
-    if((BurstBuffer == 0 ) && (BurstLength > 0))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      htim->State = HAL_TIM_STATE_BUSY;
-    }
-  }
-  switch(BurstRequestSrc)
-  {
-    case TIM_DMA_UPDATE:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
-
-      /* Enable the DMA Stream */
-       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
-    }
-    break;
-    case TIM_DMA_CC1:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
-
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
-    }
-    break;
-    case TIM_DMA_CC2:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
-
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
-    }
-    break;
-    case TIM_DMA_CC3:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
-
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
-    }
-    break;
-    case TIM_DMA_CC4:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
-
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
-    }
-    break;
-    case TIM_DMA_COM:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
-
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
-    }
-    break;
-    case TIM_DMA_TRIGGER:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
-
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
-    }
-    break;
-    default:
-    break;
-  }
-
-  /* configure the DMA Burst Mode */
-  htim->Instance->DCR = BurstBaseAddress | BurstLength;
-
-  /* Enable the TIM DMA Request */
-  __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
-
-  htim->State = HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stop the DMA burst reading
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  BurstRequestSrc: TIM DMA Request sources to disable.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
-
-  /* Abort the DMA transfer (at least disable the DMA channel) */
-  switch(BurstRequestSrc)
-  {
-    case TIM_DMA_UPDATE:
-    {
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
-    }
-    break;
-    case TIM_DMA_CC1:
-    {
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
-    }
-    break;
-    case TIM_DMA_CC2:
-    {
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
-    }
-    break;
-    case TIM_DMA_CC3:
-    {
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
-    }
-    break;
-    case TIM_DMA_CC4:
-    {
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
-    }
-    break;
-    case TIM_DMA_COM:
-    {
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
-    }
-    break;
-    case TIM_DMA_TRIGGER:
-    {
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
-    }
-    break;
-    default:
-    break;
-  }
-
-  /* Disable the TIM Update DMA request */
-  __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Generate a software event
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  EventSource: specifies the event source.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
-  *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
-  *            @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
-  *            @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
-  *            @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
-  *            @arg TIM_EVENTSOURCE_COM: Timer COM event source
-  *            @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
-  *            @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
-  *            @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
-  * @note   TIM6 and TIM7 can only generate an update event.
-  * @note   TIM_EVENTSOURCE_COM, TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are used only with TIM1 and TIM8.
-  * @retval HAL status
-  */
-
-HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_EVENT_SOURCE(EventSource));
-
-  /* Process Locked */
-  __HAL_LOCK(htim);
-
-  /* Change the TIM state */
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Set the event sources */
-  htim->Instance->EGR = EventSource;
-
-  /* Change the TIM state */
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the OCRef clear feature
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
-  *         contains the OCREF clear feature and parameters for the TIM peripheral.
-  * @param  Channel: specifies the TIM Channel.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-__weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_CHANNELS(Channel));
-  assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
-
-  /* Process Locked */
-  __HAL_LOCK(htim);
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
-  {
-    assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
-    assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
-    assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
-
-    TIM_ETR_SetConfig(htim->Instance,
-                      sClearInputConfig->ClearInputPrescaler,
-                      sClearInputConfig->ClearInputPolarity,
-                      sClearInputConfig->ClearInputFilter);
-  }
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      if(sClearInputConfig->ClearInputState != RESET)
-      {
-        /* Enable the Ocref clear feature for Channel 1 */
-        htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
-      }
-      else
-      {
-        /* Disable the Ocref clear feature for Channel 1 */
-        htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
-      }
-    }
-    break;
-    case TIM_CHANNEL_2:
-    {
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-      if(sClearInputConfig->ClearInputState != RESET)
-      {
-        /* Enable the Ocref clear feature for Channel 2 */
-        htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
-      }
-      else
-      {
-        /* Disable the Ocref clear feature for Channel 2 */
-        htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
-      }
-    }
-    break;
-    case TIM_CHANNEL_3:
-    {
-      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-      if(sClearInputConfig->ClearInputState != RESET)
-      {
-        /* Enable the Ocref clear feature for Channel 3 */
-        htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
-      }
-      else
-      {
-        /* Disable the Ocref clear feature for Channel 3 */
-        htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
-      }
-    }
-    break;
-    case TIM_CHANNEL_4:
-    {
-      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-      if(sClearInputConfig->ClearInputState != RESET)
-      {
-        /* Enable the Ocref clear feature for Channel 4 */
-        htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
-      }
-      else
-      {
-        /* Disable the Ocref clear feature for Channel 4 */
-        htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
-      }
-    }
-    break;
-    default:
-    break;
-  }
-
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief   Configures the clock source to be used
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
-  *         contains the clock source information for the TIM peripheral.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
-{
-  uint32_t tmpsmcr = 0;
-
-  /* Process Locked */
-  __HAL_LOCK(htim);
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
-
-  /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
-  tmpsmcr = htim->Instance->SMCR;
-  tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
-  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
-  htim->Instance->SMCR = tmpsmcr;
-
-  switch (sClockSourceConfig->ClockSource)
-  {
-    case TIM_CLOCKSOURCE_INTERNAL:
-    {
-      assert_param(IS_TIM_INSTANCE(htim->Instance));
-      /* Disable slave mode to clock the prescaler directly with the internal clock */
-      htim->Instance->SMCR &= ~TIM_SMCR_SMS;
-    }
-    break;
-
-    case TIM_CLOCKSOURCE_ETRMODE1:
-    {
-      assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
-      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
-      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
-      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-      /* Configure the ETR Clock source */
-      TIM_ETR_SetConfig(htim->Instance,
-                        sClockSourceConfig->ClockPrescaler,
-                        sClockSourceConfig->ClockPolarity,
-                        sClockSourceConfig->ClockFilter);
-      /* Get the TIMx SMCR register value */
-      tmpsmcr = htim->Instance->SMCR;
-      /* Reset the SMS and TS Bits */
-      tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
-      /* Select the External clock mode1 and the ETRF trigger */
-      tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
-      /* Write to TIMx SMCR */
-      htim->Instance->SMCR = tmpsmcr;
-    }
-    break;
-
-    case TIM_CLOCKSOURCE_ETRMODE2:
-    {
-      assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
-      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
-      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
-      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
-      /* Configure the ETR Clock source */
-      TIM_ETR_SetConfig(htim->Instance,
-                        sClockSourceConfig->ClockPrescaler,
-                        sClockSourceConfig->ClockPolarity,
-                        sClockSourceConfig->ClockFilter);
-      /* Enable the External clock mode2 */
-      htim->Instance->SMCR |= TIM_SMCR_ECE;
-    }
-    break;
-
-    case TIM_CLOCKSOURCE_TI1:
-    {
-      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
-
-      /* Check TI1 input conditioning related parameters */
-      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
-      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
-      TIM_TI1_ConfigInputStage(htim->Instance,
-                        sClockSourceConfig->ClockPolarity,
-                        sClockSourceConfig->ClockFilter);
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
-    }
-    break;
-    case TIM_CLOCKSOURCE_TI2:
-    {
-      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
-
-      /* Check TI1 input conditioning related parameters */
-      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
-      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
-      TIM_TI2_ConfigInputStage(htim->Instance,
-                        sClockSourceConfig->ClockPolarity,
-                        sClockSourceConfig->ClockFilter);
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
-    }
-    break;
-    case TIM_CLOCKSOURCE_TI1ED:
-    {
-      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
-      /* Check TI1 input conditioning related parameters */
-      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
-      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
-      TIM_TI1_ConfigInputStage(htim->Instance,
-                        sClockSourceConfig->ClockPolarity,
-                        sClockSourceConfig->ClockFilter);
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
-    }
-    break;
-    case TIM_CLOCKSOURCE_ITR0:
-    {
-      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
-    }
-    break;
-    case TIM_CLOCKSOURCE_ITR1:
-    {
-      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
-    }
-    break;
-    case TIM_CLOCKSOURCE_ITR2:
-    {
-      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
-    }
-    break;
-    case TIM_CLOCKSOURCE_ITR3:
-    {
-      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
-    }
-    break;
-
-    default:
-    break;
-  }
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
-  *         or a XOR combination between CH1_input, CH2_input & CH3_input
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  TI1_Selection: Indicate whether or not channel 1 is connected to the
-  *         output of a XOR gate.
-  *         This parameter can be one of the following values:
-  *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
-  *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
-  *            pins are connected to the TI1 input (XOR combination)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
-{
-  uint32_t tmpcr2 = 0;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
-
-  /* Get the TIMx CR2 register value */
-  tmpcr2 = htim->Instance->CR2;
-
-  /* Reset the TI1 selection */
-  tmpcr2 &= ~TIM_CR2_TI1S;
-
-  /* Set the TI1 selection */
-  tmpcr2 |= TI1_Selection;
-
-  /* Write to TIMxCR2 */
-  htim->Instance->CR2 = tmpcr2;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the TIM in Slave mode
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
-  *         contains the selected trigger (internal trigger input, filtered
-  *         timer input or external trigger input) and the ) and the Slave
-  *         mode (Disable, Reset, Gated, Trigger, External clock mode 1).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
-{
-  uint32_t tmpsmcr  = 0;
-  uint32_t tmpccmr1 = 0;
-  uint32_t tmpccer = 0;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
-  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
-
-  __HAL_LOCK(htim);
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Get the TIMx SMCR register value */
-  tmpsmcr = htim->Instance->SMCR;
-
-  /* Reset the Trigger Selection Bits */
-  tmpsmcr &= ~TIM_SMCR_TS;
-  /* Set the Input Trigger source */
-  tmpsmcr |= sSlaveConfig->InputTrigger;
-
-  /* Reset the slave mode Bits */
-  tmpsmcr &= ~TIM_SMCR_SMS;
-  /* Set the slave mode */
-  tmpsmcr |= sSlaveConfig->SlaveMode;
-
-  /* Write to TIMx SMCR */
-  htim->Instance->SMCR = tmpsmcr;
-
-  /* Configure the trigger prescaler, filter, and polarity */
-  switch (sSlaveConfig->InputTrigger)
-  {
-  case TIM_TS_ETRF:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
-      assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
-      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
-      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-      /* Configure the ETR Trigger source */
-      TIM_ETR_SetConfig(htim->Instance,
-                        sSlaveConfig->TriggerPrescaler,
-                        sSlaveConfig->TriggerPolarity,
-                        sSlaveConfig->TriggerFilter);
-    }
-    break;
-
-  case TIM_TS_TI1F_ED:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
-      /* Disable the Channel 1: Reset the CC1E Bit */
-      tmpccer = htim->Instance->CCER;
-      htim->Instance->CCER &= ~TIM_CCER_CC1E;
-      tmpccmr1 = htim->Instance->CCMR1;
-
-      /* Set the filter */
-      tmpccmr1 &= ~TIM_CCMR1_IC1F;
-      tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
-
-      /* Write to TIMx CCMR1 and CCER registers */
-      htim->Instance->CCMR1 = tmpccmr1;
-      htim->Instance->CCER = tmpccer;
-
-    }
-    break;
-
-  case TIM_TS_TI1FP1:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
-      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
-      /* Configure TI1 Filter and Polarity */
-      TIM_TI1_ConfigInputStage(htim->Instance,
-                               sSlaveConfig->TriggerPolarity,
-                               sSlaveConfig->TriggerFilter);
-    }
-    break;
-
-  case TIM_TS_TI2FP2:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
-      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
-      /* Configure TI2 Filter and Polarity */
-      TIM_TI2_ConfigInputStage(htim->Instance,
-                                sSlaveConfig->TriggerPolarity,
-                                sSlaveConfig->TriggerFilter);
-    }
-    break;
-
-  case TIM_TS_ITR0:
-    {
-      /* Check the parameter */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-    }
-    break;
-
-  case TIM_TS_ITR1:
-    {
-      /* Check the parameter */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-    }
-    break;
-
-  case TIM_TS_ITR2:
-    {
-      /* Check the parameter */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-    }
-    break;
-
-  case TIM_TS_ITR3:
-    {
-      /* Check the parameter */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-    }
-    break;
-
-  default:
-    break;
-  }
-
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the TIM in Slave mode in interrupt mode
-  * @param  htim: TIM handle.
-  * @param  sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
-  *         contains the selected trigger (internal trigger input, filtered
-  *         timer input or external trigger input) and the ) and the Slave
-  *         mode (Disable, Reset, Gated, Trigger, External clock mode 1).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
-                                                        TIM_SlaveConfigTypeDef * sSlaveConfig)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
-  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
-
-  __HAL_LOCK(htim);
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
-
-  /* Enable Trigger Interrupt */
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
-
-  /* Disable Trigger DMA request */
-  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
-
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Read the captured value from Capture Compare unit
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval Captured value
-  */
-uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  uint32_t tmpreg = 0;
-
-  __HAL_LOCK(htim);
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
-      /* Return the capture 1 value */
-      tmpreg = htim->Instance->CCR1;
-
-      break;
-    }
-    case TIM_CHANNEL_2:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-      /* Return the capture 2 value */
-      tmpreg = htim->Instance->CCR2;
-
-      break;
-    }
-
-    case TIM_CHANNEL_3:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
-      /* Return the capture 3 value */
-      tmpreg = htim->Instance->CCR3;
-
-      break;
-    }
-
-    case TIM_CHANNEL_4:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
-      /* Return the capture 4 value */
-      tmpreg = htim->Instance->CCR4;
-
-      break;
-    }
-
-    default:
-    break;
-  }
-
-  __HAL_UNLOCK(htim);
-  return tmpreg;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
- *  @brief    TIM Callbacks functions
- *
-@verbatim
-  ==============================================================================
-                        ##### TIM Callbacks functions #####
-  ==============================================================================
- [..]
-   This section provides TIM callback functions:
-   (+) Timer Period elapsed callback
-   (+) Timer Output Compare callback
-   (+) Timer Input capture callback
-   (+) Timer Trigger callback
-   (+) Timer Error callback
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Period elapsed callback in non blocking mode
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
-   */
-
-}
-/**
-  * @brief  Output Compare callback in non blocking mode
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
-   */
-}
-/**
-  * @brief  Input Capture callback in non blocking mode
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  PWM Pulse finished callback in non blocking mode
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Hall Trigger detection callback in non blocking mode
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_TriggerCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Timer error callback in non blocking mode
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_ErrorCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
- *  @brief   Peripheral State functions
- *
-@verbatim
-  ==============================================================================
-                        ##### Peripheral State functions #####
-  ==============================================================================
-  [..]
-    This subsection permits to get in run-time the status of the peripheral
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the TIM Base state
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL state
-  */
-HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
-{
-  return htim->State;
-}
-
-/**
-  * @brief  Return the TIM OC state
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL state
-  */
-HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
-{
-  return htim->State;
-}
-
-/**
-  * @brief  Return the TIM PWM state
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL state
-  */
-HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
-{
-  return htim->State;
-}
-
-/**
-  * @brief  Return the TIM Input Capture state
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL state
-  */
-HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
-{
-  return htim->State;
-}
-
-/**
-  * @brief  Return the TIM One Pulse Mode state
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL state
-  */
-HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
-{
-  return htim->State;
-}
-
-/**
-  * @brief  Return the TIM Encoder Mode state
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL state
-  */
-HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
-{
-  return htim->State;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @brief  TIM DMA error callback
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  htim->State= HAL_TIM_STATE_READY;
-
-  HAL_TIM_ErrorCallback(htim);
-}
-
-/**
-  * @brief  TIM DMA Delay Pulse complete callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  htim->State= HAL_TIM_STATE_READY;
-
-  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-  }
-
-  HAL_TIM_PWM_PulseFinishedCallback(htim);
-
-  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-/**
-  * @brief  TIM DMA Capture complete callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-   htim->State= HAL_TIM_STATE_READY;
-
-  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-  }
-
-  HAL_TIM_IC_CaptureCallback(htim);
-
-  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-
-}
-
-/**
-  * @brief  TIM DMA Period Elapse complete callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  htim->State= HAL_TIM_STATE_READY;
-
-  HAL_TIM_PeriodElapsedCallback(htim);
-}
-
-/**
-  * @brief  TIM DMA Trigger callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  htim->State= HAL_TIM_STATE_READY;
-
-  HAL_TIM_TriggerCallback(htim);
-}
-
-/**
-  * @brief  Time Base configuration
-  * @param  TIMx: TIM peripheral
-  * @param  Structure: pointer on TIM Time Base required parameters
-  * @retval None
-  */
-void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
-{
-  uint32_t tmpcr1 = 0;
-  tmpcr1 = TIMx->CR1;
-
-  /* Set TIM Time Base Unit parameters ---------------------------------------*/
-  if(IS_TIM_CC3_INSTANCE(TIMx) != RESET)
-  {
-    /* Select the Counter Mode */
-    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
-    tmpcr1 |= Structure->CounterMode;
-  }
-
-  if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)
-  {
-    /* Set the clock division */
-    tmpcr1 &= ~TIM_CR1_CKD;
-    tmpcr1 |= (uint32_t)Structure->ClockDivision;
-  }
-
-  TIMx->CR1 = tmpcr1;
-
-  /* Set the Auto-reload value */
-  TIMx->ARR = (uint32_t)Structure->Period ;
-
-  /* Set the Prescaler value */
-  TIMx->PSC = (uint32_t)Structure->Prescaler;
-
-  if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
-  {
-    /* Set the Repetition Counter value */
-    TIMx->RCR = Structure->RepetitionCounter;
-  }
-
-  /* Generate an update event to reload the Prescaler
-     and the repetition counter(only for TIM1 and TIM8) value immediately */
-  TIMx->EGR = TIM_EGR_UG;
-}
-
-/**
-  * @brief  Time Output Compare 1 configuration
-  * @param  TIMx to select the TIM peripheral
-  * @param  OC_Config: The output configuration structure
-  * @retval None
-  */
-void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
-  uint32_t tmpccmrx = 0;
-  uint32_t tmpccer = 0;
-  uint32_t tmpcr2 = 0;
-
-  /* Disable the Channel 1: Reset the CC1E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC1E;
-
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
-  /* Get the TIMx CR2 register value */
-  tmpcr2 = TIMx->CR2;
-
-  /* Get the TIMx CCMR1 register value */
-  tmpccmrx = TIMx->CCMR1;
-
-  /* Reset the Output Compare Mode Bits */
-  tmpccmrx &= ~TIM_CCMR1_OC1M;
-  tmpccmrx &= ~TIM_CCMR1_CC1S;
-  /* Select the Output Compare Mode */
-  tmpccmrx |= OC_Config->OCMode;
-
-  /* Reset the Output Polarity level */
-  tmpccer &= ~TIM_CCER_CC1P;
-  /* Set the Output Compare Polarity */
-  tmpccer |= OC_Config->OCPolarity;
-
-
-  if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
-  {
-    /* Reset the Output N Polarity level */
-    tmpccer &= ~TIM_CCER_CC1NP;
-    /* Set the Output N Polarity */
-    tmpccer |= OC_Config->OCNPolarity;
-    /* Reset the Output N State */
-    tmpccer &= ~TIM_CCER_CC1NE;
-
-    /* Reset the Output Compare and Output Compare N IDLE State */
-    tmpcr2 &= ~TIM_CR2_OIS1;
-    tmpcr2 &= ~TIM_CR2_OIS1N;
-    /* Set the Output Idle state */
-    tmpcr2 |= OC_Config->OCIdleState;
-    /* Set the Output N Idle state */
-    tmpcr2 |= OC_Config->OCNIdleState;
-  }
-  /* Write to TIMx CR2 */
-  TIMx->CR2 = tmpcr2;
-
-  /* Write to TIMx CCMR1 */
-  TIMx->CCMR1 = tmpccmrx;
-
-  /* Set the Capture Compare Register value */
-  TIMx->CCR1 = OC_Config->Pulse;
-
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Time Output Compare 2 configuration
-  * @param  TIMx to select the TIM peripheral
-  * @param  OC_Config: The output configuration structure
-  * @retval None
-  */
-void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
-  uint32_t tmpccmrx = 0;
-  uint32_t tmpccer = 0;
-  uint32_t tmpcr2 = 0;
-
-  /* Disable the Channel 2: Reset the CC2E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC2E;
-
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
-  /* Get the TIMx CR2 register value */
-  tmpcr2 = TIMx->CR2;
-
-  /* Get the TIMx CCMR1 register value */
-  tmpccmrx = TIMx->CCMR1;
-
-  /* Reset the Output Compare mode and Capture/Compare selection Bits */
-  tmpccmrx &= ~TIM_CCMR1_OC2M;
-  tmpccmrx &= ~TIM_CCMR1_CC2S;
-
-  /* Select the Output Compare Mode */
-  tmpccmrx |= (OC_Config->OCMode << 8);
-
-  /* Reset the Output Polarity level */
-  tmpccer &= ~TIM_CCER_CC2P;
-  /* Set the Output Compare Polarity */
-  tmpccer |= (OC_Config->OCPolarity << 4);
-
-  if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
-  {
-    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-
-    /* Reset the Output N Polarity level */
-    tmpccer &= ~TIM_CCER_CC2NP;
-    /* Set the Output N Polarity */
-    tmpccer |= (OC_Config->OCNPolarity << 4);
-    /* Reset the Output N State */
-    tmpccer &= ~TIM_CCER_CC2NE;
-
-    /* Reset the Output Compare and Output Compare N IDLE State */
-    tmpcr2 &= ~TIM_CR2_OIS2;
-    tmpcr2 &= ~TIM_CR2_OIS2N;
-    /* Set the Output Idle state */
-    tmpcr2 |= (OC_Config->OCIdleState << 2);
-    /* Set the Output N Idle state */
-    tmpcr2 |= (OC_Config->OCNIdleState << 2);
-  }
-  /* Write to TIMx CR2 */
-  TIMx->CR2 = tmpcr2;
-
-  /* Write to TIMx CCMR1 */
-  TIMx->CCMR1 = tmpccmrx;
-
-  /* Set the Capture Compare Register value */
-  TIMx->CCR2 = OC_Config->Pulse;
-
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Time Output Compare 3 configuration
-  * @param  TIMx to select the TIM peripheral
-  * @param  OC_Config: The output configuration structure
-  * @retval None
-  */
-void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
-  uint32_t tmpccmrx = 0;
-  uint32_t tmpccer = 0;
-  uint32_t tmpcr2 = 0;
-
-  /* Disable the Channel 3: Reset the CC2E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC3E;
-
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
-  /* Get the TIMx CR2 register value */
-  tmpcr2 = TIMx->CR2;
-
-  /* Get the TIMx CCMR2 register value */
-  tmpccmrx = TIMx->CCMR2;
-
-  /* Reset the Output Compare mode and Capture/Compare selection Bits */
-  tmpccmrx &= ~TIM_CCMR2_OC3M;
-  tmpccmrx &= ~TIM_CCMR2_CC3S;
-  /* Select the Output Compare Mode */
-  tmpccmrx |= OC_Config->OCMode;
-
-  /* Reset the Output Polarity level */
-  tmpccer &= ~TIM_CCER_CC3P;
-  /* Set the Output Compare Polarity */
-  tmpccer |= (OC_Config->OCPolarity << 8);
-
-  if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
-  {
-    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-
-    /* Reset the Output N Polarity level */
-    tmpccer &= ~TIM_CCER_CC3NP;
-    /* Set the Output N Polarity */
-    tmpccer |= (OC_Config->OCNPolarity << 8);
-    /* Reset the Output N State */
-    tmpccer &= ~TIM_CCER_CC3NE;
-
-    /* Reset the Output Compare and Output Compare N IDLE State */
-    tmpcr2 &= ~TIM_CR2_OIS3;
-    tmpcr2 &= ~TIM_CR2_OIS3N;
-    /* Set the Output Idle state */
-    tmpcr2 |= (OC_Config->OCIdleState << 4);
-    /* Set the Output N Idle state */
-    tmpcr2 |= (OC_Config->OCNIdleState << 4);
-  }
-  /* Write to TIMx CR2 */
-  TIMx->CR2 = tmpcr2;
-
-  /* Write to TIMx CCMR2 */
-  TIMx->CCMR2 = tmpccmrx;
-
-  /* Set the Capture Compare Register value */
-  TIMx->CCR3 = OC_Config->Pulse;
-
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Time Output Compare 4 configuration
-  * @param  TIMx to select the TIM peripheral
-  * @param  OC_Config: The output configuration structure
-  * @retval None
-  */
-void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
-  uint32_t tmpccmrx = 0;
-  uint32_t tmpccer = 0;
-  uint32_t tmpcr2 = 0;
-
-  /* Disable the Channel 4: Reset the CC4E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC4E;
-
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
-  /* Get the TIMx CR2 register value */
-  tmpcr2 = TIMx->CR2;
-
-  /* Get the TIMx CCMR2 register value */
-  tmpccmrx = TIMx->CCMR2;
-
-  /* Reset the Output Compare mode and Capture/Compare selection Bits */
-  tmpccmrx &= ~TIM_CCMR2_OC4M;
-  tmpccmrx &= ~TIM_CCMR2_CC4S;
-
-  /* Select the Output Compare Mode */
-  tmpccmrx |= (OC_Config->OCMode << 8);
-
-  /* Reset the Output Polarity level */
-  tmpccer &= ~TIM_CCER_CC4P;
-  /* Set the Output Compare Polarity */
-  tmpccer |= (OC_Config->OCPolarity << 12);
-
-  /*if((TIMx == TIM1) || (TIMx == TIM8))*/
-  if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
-  {
-    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-    /* Reset the Output Compare IDLE State */
-    tmpcr2 &= ~TIM_CR2_OIS4;
-    /* Set the Output Idle state */
-    tmpcr2 |= (OC_Config->OCIdleState << 6);
-  }
-  /* Write to TIMx CR2 */
-  TIMx->CR2 = tmpcr2;
-
-  /* Write to TIMx CCMR2 */
-  TIMx->CCMR2 = tmpccmrx;
-
-  /* Set the Capture Compare Register value */
-  TIMx->CCR4 = OC_Config->Pulse;
-
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Time Output Compare 4 configuration
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  sSlaveConfig: The slave configuration structure
-  * @retval None
-  */
-static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
-                              TIM_SlaveConfigTypeDef * sSlaveConfig)
-{
-  uint32_t tmpsmcr = 0;
-  uint32_t tmpccmr1 = 0;
-  uint32_t tmpccer = 0;
-
- /* Get the TIMx SMCR register value */
-  tmpsmcr = htim->Instance->SMCR;
-
-  /* Reset the Trigger Selection Bits */
-  tmpsmcr &= ~TIM_SMCR_TS;
-  /* Set the Input Trigger source */
-  tmpsmcr |= sSlaveConfig->InputTrigger;
-
-  /* Reset the slave mode Bits */
-  tmpsmcr &= ~TIM_SMCR_SMS;
-  /* Set the slave mode */
-  tmpsmcr |= sSlaveConfig->SlaveMode;
-
-  /* Write to TIMx SMCR */
-  htim->Instance->SMCR = tmpsmcr;
-
-  /* Configure the trigger prescaler, filter, and polarity */
-  switch (sSlaveConfig->InputTrigger)
-  {
-  case TIM_TS_ETRF:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
-      assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
-      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
-      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-      /* Configure the ETR Trigger source */
-      TIM_ETR_SetConfig(htim->Instance,
-                        sSlaveConfig->TriggerPrescaler,
-                        sSlaveConfig->TriggerPolarity,
-                        sSlaveConfig->TriggerFilter);
-    }
-    break;
-
-  case TIM_TS_TI1F_ED:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
-      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
-      /* Disable the Channel 1: Reset the CC1E Bit */
-      tmpccer = htim->Instance->CCER;
-      htim->Instance->CCER &= ~TIM_CCER_CC1E;
-      tmpccmr1 = htim->Instance->CCMR1;
-
-      /* Set the filter */
-      tmpccmr1 &= ~TIM_CCMR1_IC1F;
-      tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
-
-      /* Write to TIMx CCMR1 and CCER registers */
-      htim->Instance->CCMR1 = tmpccmr1;
-      htim->Instance->CCER = tmpccer;
-
-    }
-    break;
-
-  case TIM_TS_TI1FP1:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
-      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
-      /* Configure TI1 Filter and Polarity */
-      TIM_TI1_ConfigInputStage(htim->Instance,
-                               sSlaveConfig->TriggerPolarity,
-                               sSlaveConfig->TriggerFilter);
-    }
-    break;
-
-  case TIM_TS_TI2FP2:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
-      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
-      /* Configure TI2 Filter and Polarity */
-      TIM_TI2_ConfigInputStage(htim->Instance,
-                                sSlaveConfig->TriggerPolarity,
-                                sSlaveConfig->TriggerFilter);
-    }
-    break;
-
-  case TIM_TS_ITR0:
-    {
-      /* Check the parameter */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-    }
-    break;
-
-  case TIM_TS_ITR1:
-    {
-      /* Check the parameter */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-    }
-    break;
-
-  case TIM_TS_ITR2:
-    {
-      /* Check the parameter */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-    }
-    break;
-
-  case TIM_TS_ITR3:
-    {
-      /* Check the parameter */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-    }
-    break;
-
-  default:
-    break;
-  }
-}
-
-/**
-  * @brief  Configure the TI1 as Input.
-  * @param  TIMx to select the TIM peripheral.
-  * @param  TIM_ICPolarity : The Input Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPolarity_Rising
-  *            @arg TIM_ICPolarity_Falling
-  *            @arg TIM_ICPolarity_BothEdge
-  * @param  TIM_ICSelection: specifies the input to be used.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
-  *            @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
-  *            @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
-  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
-  *          This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
-  *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be
-  *        protected against un-initialized filter and polarity values.
-  */
-void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                       uint32_t TIM_ICFilter)
-{
-  uint32_t tmpccmr1 = 0;
-  uint32_t tmpccer = 0;
-
-  /* Disable the Channel 1: Reset the CC1E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC1E;
-  tmpccmr1 = TIMx->CCMR1;
-  tmpccer = TIMx->CCER;
-
-  /* Select the Input */
-  if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
-  {
-    tmpccmr1 &= ~TIM_CCMR1_CC1S;
-    tmpccmr1 |= TIM_ICSelection;
-  }
-  else
-  {
-    tmpccmr1 |= TIM_CCMR1_CC1S_0;
-  }
-
-  /* Set the filter */
-  tmpccmr1 &= ~TIM_CCMR1_IC1F;
-  tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
-
-  /* Select the Polarity and set the CC1E Bit */
-  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
-  tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
-
-  /* Write to TIMx CCMR1 and CCER registers */
-  TIMx->CCMR1 = tmpccmr1;
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configure the Polarity and Filter for TI1.
-  * @param  TIMx to select the TIM peripheral.
-  * @param  TIM_ICPolarity : The Input Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPolarity_Rising
-  *            @arg TIM_ICPolarity_Falling
-  *            @arg TIM_ICPolarity_BothEdge
-  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
-  *          This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  */
-static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
-{
-  uint32_t tmpccmr1 = 0;
-  uint32_t tmpccer = 0;
-
-  /* Disable the Channel 1: Reset the CC1E Bit */
-  tmpccer = TIMx->CCER;
-  TIMx->CCER &= ~TIM_CCER_CC1E;
-  tmpccmr1 = TIMx->CCMR1;
-
-  /* Set the filter */
-  tmpccmr1 &= ~TIM_CCMR1_IC1F;
-  tmpccmr1 |= (TIM_ICFilter << 4);
-
-  /* Select the Polarity and set the CC1E Bit */
-  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
-  tmpccer |= TIM_ICPolarity;
-
-  /* Write to TIMx CCMR1 and CCER registers */
-  TIMx->CCMR1 = tmpccmr1;
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configure the TI2 as Input.
-  * @param  TIMx to select the TIM peripheral
-  * @param  TIM_ICPolarity : The Input Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPolarity_Rising
-  *            @arg TIM_ICPolarity_Falling
-  *            @arg TIM_ICPolarity_BothEdge
-  * @param  TIM_ICSelection: specifies the input to be used.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
-  *            @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
-  *            @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
-  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
-  *          This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
-  *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be
-  *        protected against un-initialized filter and polarity values.
-  */
-static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                       uint32_t TIM_ICFilter)
-{
-  uint32_t tmpccmr1 = 0;
-  uint32_t tmpccer = 0;
-
-  /* Disable the Channel 2: Reset the CC2E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC2E;
-  tmpccmr1 = TIMx->CCMR1;
-  tmpccer = TIMx->CCER;
-
-  /* Select the Input */
-  tmpccmr1 &= ~TIM_CCMR1_CC2S;
-  tmpccmr1 |= (TIM_ICSelection << 8);
-
-  /* Set the filter */
-  tmpccmr1 &= ~TIM_CCMR1_IC2F;
-  tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
-
-  /* Select the Polarity and set the CC2E Bit */
-  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
-  tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
-
-  /* Write to TIMx CCMR1 and CCER registers */
-  TIMx->CCMR1 = tmpccmr1 ;
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configure the Polarity and Filter for TI2.
-  * @param  TIMx to select the TIM peripheral.
-  * @param  TIM_ICPolarity : The Input Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPolarity_Rising
-  *            @arg TIM_ICPolarity_Falling
-  *            @arg TIM_ICPolarity_BothEdge
-  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
-  *          This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  */
-static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
-{
-uint32_t tmpccmr1 = 0;
-  uint32_t tmpccer = 0;
-
-  /* Disable the Channel 2: Reset the CC2E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC2E;
-  tmpccmr1 = TIMx->CCMR1;
-  tmpccer = TIMx->CCER;
-
-  /* Set the filter */
-  tmpccmr1 &= ~TIM_CCMR1_IC2F;
-  tmpccmr1 |= (TIM_ICFilter << 12);
-
-  /* Select the Polarity and set the CC2E Bit */
-  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
-  tmpccer |= (TIM_ICPolarity << 4);
-
-  /* Write to TIMx CCMR1 and CCER registers */
-  TIMx->CCMR1 = tmpccmr1 ;
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configure the TI3 as Input.
-  * @param  TIMx to select the TIM peripheral
-  * @param  TIM_ICPolarity : The Input Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPolarity_Rising
-  *            @arg TIM_ICPolarity_Falling
-  *            @arg TIM_ICPolarity_BothEdge
-  * @param  TIM_ICSelection: specifies the input to be used.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
-  *            @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
-  *            @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
-  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
-  *          This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
-  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
-  *        protected against un-initialized filter and polarity values.
-  */
-static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                       uint32_t TIM_ICFilter)
-{
-  uint32_t tmpccmr2 = 0;
-  uint32_t tmpccer = 0;
-
-  /* Disable the Channel 3: Reset the CC3E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC3E;
-  tmpccmr2 = TIMx->CCMR2;
-  tmpccer = TIMx->CCER;
-
-  /* Select the Input */
-  tmpccmr2 &= ~TIM_CCMR2_CC3S;
-  tmpccmr2 |= TIM_ICSelection;
-
-  /* Set the filter */
-  tmpccmr2 &= ~TIM_CCMR2_IC3F;
-  tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
-
-  /* Select the Polarity and set the CC3E Bit */
-  tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
-  tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
-
-  /* Write to TIMx CCMR2 and CCER registers */
-  TIMx->CCMR2 = tmpccmr2;
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configure the TI4 as Input.
-  * @param  TIMx to select the TIM peripheral
-  * @param  TIM_ICPolarity : The Input Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPolarity_Rising
-  *            @arg TIM_ICPolarity_Falling
-  *            @arg TIM_ICPolarity_BothEdge
-  * @param  TIM_ICSelection: specifies the input to be used.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
-  *            @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
-  *            @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
-  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
-  *          This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
-  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
-  *        protected against un-initialized filter and polarity values.
-  */
-static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                       uint32_t TIM_ICFilter)
-{
-  uint32_t tmpccmr2 = 0;
-  uint32_t tmpccer = 0;
-
-  /* Disable the Channel 4: Reset the CC4E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC4E;
-  tmpccmr2 = TIMx->CCMR2;
-  tmpccer = TIMx->CCER;
-
-  /* Select the Input */
-  tmpccmr2 &= ~TIM_CCMR2_CC4S;
-  tmpccmr2 |= (TIM_ICSelection << 8);
-
-  /* Set the filter */
-  tmpccmr2 &= ~TIM_CCMR2_IC4F;
-  tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
-
-  /* Select the Polarity and set the CC4E Bit */
-  tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
-  tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
-
-  /* Write to TIMx CCMR2 and CCER registers */
-  TIMx->CCMR2 = tmpccmr2;
-  TIMx->CCER = tmpccer ;
-}
-
-/**
-  * @brief  Selects the Input Trigger source
-  * @param  TIMx to select the TIM peripheral
-  * @param  TIM_ITRx: The Input Trigger source.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_TS_ITR0: Internal Trigger 0
-  *            @arg TIM_TS_ITR1: Internal Trigger 1
-  *            @arg TIM_TS_ITR2: Internal Trigger 2
-  *            @arg TIM_TS_ITR3: Internal Trigger 3
-  *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
-  *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
-  *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
-  *            @arg TIM_TS_ETRF: External Trigger input
-  * @retval None
-  */
-static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t TIM_ITRx)
-{
-  uint32_t tmpsmcr = 0;
-
-   /* Get the TIMx SMCR register value */
-   tmpsmcr = TIMx->SMCR;
-   /* Reset the TS Bits */
-   tmpsmcr &= ~TIM_SMCR_TS;
-   /* Set the Input Trigger source and the slave mode*/
-   tmpsmcr |= TIM_ITRx | TIM_SLAVEMODE_EXTERNAL1;
-   /* Write to TIMx SMCR */
-   TIMx->SMCR = tmpsmcr;
-}
-
-/**
-  * @brief  Configures the TIMx External Trigger (ETR).
-  * @param  TIMx to select the TIM peripheral
-  * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ExtTRGPSC_DIV1: ETRP Prescaler OFF.
-  *            @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
-  *            @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
-  *            @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
-  * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
-  *            @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
-  * @param  ExtTRGFilter: External Trigger Filter.
-  *          This parameter must be a value between 0x00 and 0x0F
-  * @retval None
-  */
-void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
-                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
-{
-  uint32_t tmpsmcr = 0;
-
-  tmpsmcr = TIMx->SMCR;
-
-  /* Reset the ETR Bits */
-  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
-
-  /* Set the Prescaler, the Filter value and the Polarity */
-  tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
-
-  /* Write to TIMx SMCR */
-  TIMx->SMCR = tmpsmcr;
-}
-
-/**
-  * @brief  Enables or disables the TIM Capture Compare Channel x.
-  * @param  TIMx to select the TIM peripheral
-  * @param  Channel: specifies the TIM Channel
-  *          This parameter can be one of the following values:
-  *            @arg TIM_Channel_1: TIM Channel 1
-  *            @arg TIM_Channel_2: TIM Channel 2
-  *            @arg TIM_Channel_3: TIM Channel 3
-  *            @arg TIM_Channel_4: TIM Channel 4
-  * @param  ChannelState: specifies the TIM Channel CCxE bit new state.
-  *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
-  * @retval None
-  */
-void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
-{
-  uint32_t tmp = 0;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
-  assert_param(IS_TIM_CHANNELS(Channel));
-
-  tmp = TIM_CCER_CC1E << Channel;
-
-  /* Reset the CCxE Bit */
-  TIMx->CCER &= ~tmp;
-
-  /* Set or reset the CCxE Bit */
-  TIMx->CCER |= (uint32_t)(ChannelState << Channel);
-}
-
-
-/**
-  * @}
-  */
-
-#endif /* HAL_TIM_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_tim_ex.c b/stmhal/hal/f7/src/stm32f7xx_hal_tim_ex.c
deleted file mode 100644
index 131d4a6fe2..0000000000
--- a/stmhal/hal/f7/src/stm32f7xx_hal_tim_ex.c
+++ /dev/null
@@ -1,2574 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_tim_ex.c
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   TIM HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Timer extension peripheral:
-  *           + Time Hall Sensor Interface Initialization
-  *           + Time Hall Sensor Interface Start
-  *           + Time Complementary signal bread and dead time configuration
-  *           + Time Master and Slave synchronization configuration
-  *           + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
-  *           + Time OCRef clear configuration
-  *           + Timer remapping capabilities configuration
-  @verbatim
-  ==============================================================================
-                      ##### TIMER Extended features #####
-  ==============================================================================
-  [..]
-    The Timer Extension features include:
-    (#) Complementary outputs with programmable dead-time for :
-        (++) Input Capture
-        (++) Output Compare
-        (++) PWM generation (Edge and Center-aligned Mode)
-        (++) One-pulse mode output
-    (#) Synchronization circuit to control the timer with external signals and to
-        interconnect several timers together.
-    (#) Break input to put the timer output signals in reset state or in a known state.
-    (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
-        positioning purposes
-
-                        ##### How to use this driver #####
-  ==============================================================================
-  [..]
-     (#) Initialize the TIM low level resources by implementing the following functions
-         depending from feature used :
-           (++) Complementary Output Compare : HAL_TIM_OC_MspInit()
-           (++) Complementary PWM generation : HAL_TIM_PWM_MspInit()
-           (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()
-           (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit()
-
-     (#) Initialize the TIM low level resources :
-        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
-        (##) TIM pins configuration
-            (+++) Enable the clock for the TIM GPIOs using the following function:
-                  __HAL_RCC_GPIOx_CLK_ENABLE();
-            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
-
-     (#) The external Clock can be configured, if needed (the default clock is the
-         internal clock from the APBx), using the following function:
-         HAL_TIM_ConfigClockSource, the clock configuration should be done before
-         any start function.
-
-    (#) Configure the TIM in the desired functioning mode using one of the
-        initialization function of this driver:
-        (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the
-             Timer Hall Sensor Interface and the commutation event with the corresponding
-             Interrupt and DMA request if needed (Note that One Timer is used to interface
-             with the Hall sensor Interface and another Timer should be used to use
-             the commutation event).
-
-    (#) Activate the TIM peripheral using one of the start functions:
-           (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
-           (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
-           (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
-           (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
-
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup TIMEx TIMEx
-  * @brief TIM Extended HAL module driver
-  * @{
-  */
-
-#ifdef HAL_TIM_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define BDTR_BKF_SHIFT  (16)
-#define BDTR_BK2F_SHIFT (20)
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup TIMEx_Private_Functions
-  * @{
-  */
-static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
-static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-/**
-  * @}
-  */
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions
-  * @{
-  */
-
-/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
- *  @brief    Timer Hall Sensor functions
- *
-@verbatim
-  ==============================================================================
-                      ##### Timer Hall Sensor functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Initialize and configure TIM HAL Sensor.
-    (+) De-initialize TIM HAL Sensor.
-    (+) Start the Hall Sensor Interface.
-    (+) Stop the Hall Sensor Interface.
-    (+) Start the Hall Sensor Interface and enable interrupts.
-    (+) Stop the Hall Sensor Interface and disable interrupts.
-    (+) Start the Hall Sensor Interface and enable DMA transfers.
-    (+) Stop the Hall Sensor Interface and disable DMA transfers.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIM Hall Sensor Interface and create the associated handle.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  sConfig: TIM Hall Sensor configuration structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
-{
-  TIM_OC_InitTypeDef OC_Config;
-
-  /* Check the TIM handle allocation */
-  if(htim == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-  assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
-  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
-  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
-
-  /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;
-
-  /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
-  HAL_TIMEx_HallSensor_MspInit(htim);
-
-  /* Configure the Time base in the Encoder Mode */
-  TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
-  /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the  Hall sensor */
-  TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
-
-  /* Reset the IC1PSC Bits */
-  htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
-  /* Set the IC1PSC value */
-  htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
-
-  /* Enable the Hall sensor interface (XOR function of the three inputs) */
-  htim->Instance->CR2 |= TIM_CR2_TI1S;
-
-  /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
-  htim->Instance->SMCR &= ~TIM_SMCR_TS;
-  htim->Instance->SMCR |= TIM_TS_TI1F_ED;
-
-  /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
-  htim->Instance->SMCR &= ~TIM_SMCR_SMS;
-  htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
-
-  /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
-  OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
-  OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
-  OC_Config.OCMode = TIM_OCMODE_PWM2;
-  OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
-  OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
-  OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
-  OC_Config.Pulse = sConfig->Commutation_Delay;
-
-  TIM_OC2_SetConfig(htim->Instance, &OC_Config);
-
-  /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
-    register to 101 */
-  htim->Instance->CR2 &= ~TIM_CR2_MMS;
-  htim->Instance->CR2 |= TIM_TRGO_OC2REF;
-
-  /* Initialize the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the TIM Hall Sensor interface
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Disable the TIM Peripheral Clock */
-  __HAL_TIM_DISABLE(htim);
-
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
-  HAL_TIMEx_HallSensor_MspDeInit(htim);
-
-  /* Change TIM state */
-  htim->State = HAL_TIM_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM Hall Sensor MSP.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes TIM Hall Sensor MSP.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Starts the TIM Hall Sensor Interface.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-
-  /* Enable the Input Capture channels 1
-    (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Hall sensor Interface.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-
-  /* Disable the Input Capture channels 1, 2 and 3
-    (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Hall Sensor Interface in interrupt mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-
-  /* Enable the capture compare Interrupts 1 event */
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-
-  /* Enable the Input Capture channels 1
-    (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Hall Sensor Interface in interrupt mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-
-  /* Disable the Input Capture channels 1
-    (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
-  /* Disable the capture compare Interrupts event */
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Hall Sensor Interface in DMA mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  pData: The destination Buffer address.
-  * @param  Length: The length of data to be transferred from TIM peripheral to memory.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-
-   if((htim->State == HAL_TIM_STATE_BUSY))
-  {
-     return HAL_BUSY;
-  }
-  else if((htim->State == HAL_TIM_STATE_READY))
-  {
-    if(((uint32_t)pData == 0 ) && (Length > 0))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      htim->State = HAL_TIM_STATE_BUSY;
-    }
-  }
-  /* Enable the Input Capture channels 1
-    (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-
-  /* Set the DMA Input Capture 1 Callback */
-  htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-  /* Set the DMA error callback */
-  htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
-
-  /* Enable the DMA Stream for Capture 1*/
-  HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
-
-  /* Enable the capture compare 1 Interrupt */
-  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Hall Sensor Interface in DMA mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-
-  /* Disable the Input Capture channels 1
-    (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
-
-  /* Disable the capture compare Interrupts 1 event */
-  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
- *  @brief    Timer Complementary Output Compare functions
- *
-@verbatim
-  ==============================================================================
-              ##### Timer Complementary Output Compare functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Start the Complementary Output Compare/PWM.
-    (+) Stop the Complementary Output Compare/PWM.
-    (+) Start the Complementary Output Compare/PWM and enable interrupts.
-    (+) Stop the Complementary Output Compare/PWM and disable interrupts.
-    (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
-    (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Starts the TIM Output Compare signal generation on the complementary
-  *         output.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
-     /* Enable the Capture compare channel N */
-     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
-  /* Enable the Main Output */
-    __HAL_TIM_MOE_ENABLE(htim);
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Output Compare signal generation on the complementary
-  *         output.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be disabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
-    /* Disable the Capture compare channel N */
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
-  /* Disable the Main Output */
-    __HAL_TIM_MOE_DISABLE(htim);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Output Compare signal generation in interrupt mode
-  *         on the complementary output.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Enable the TIM Output Compare interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Enable the TIM Output Compare interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Enable the TIM Output Compare interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Enable the TIM Output Compare interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Enable the TIM Break interrupt */
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
-
-  /* Enable the Capture compare channel N */
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
-  /* Enable the Main Output */
- __HAL_TIM_MOE_ENABLE(htim);
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Output Compare signal generation in interrupt mode
-  *         on the complementary output.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be disabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  uint32_t tmpccer = 0;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Disable the TIM Output Compare interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Output Compare interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Output Compare interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Output Compare interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Disable the Capture compare channel N */
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
-  /* Disable the TIM Break interrupt (only if no more channel is active) */
-  tmpccer = htim->Instance->CCER;
-  if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
-  {
-    __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
-  }
-
-  /* Disable the Main Output */
-  __HAL_TIM_MOE_DISABLE(htim);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Output Compare signal generation in DMA mode
-  *         on the complementary output.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  pData: The source Buffer address.
-  * @param  Length: The length of data to be transferred from memory to TIM peripheral
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
-  if((htim->State == HAL_TIM_STATE_BUSY))
-  {
-     return HAL_BUSY;
-  }
-  else if((htim->State == HAL_TIM_STATE_READY))
-  {
-    if(((uint32_t)pData == 0 ) && (Length > 0))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      htim->State = HAL_TIM_STATE_BUSY;
-    }
-  }
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
-
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
-
-      /* Enable the TIM Output Compare DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
-
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
-
-      /* Enable the TIM Output Compare DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-{
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
-
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-
-      /* Enable the TIM Output Compare DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-     /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
-
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-
-      /* Enable the TIM Output Compare DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Enable the Capture compare channel N */
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
-  /* Enable the Main Output */
-  __HAL_TIM_MOE_ENABLE(htim);
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Output Compare signal generation in DMA mode
-  *         on the complementary output.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be disabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Disable the TIM Output Compare DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Output Compare DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Output Compare DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Output Compare interrupt */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Disable the Capture compare channel N */
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
-  /* Disable the Main Output */
-  __HAL_TIM_MOE_DISABLE(htim);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Change the htim state */
-  htim->State = HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
- *  @brief    Timer Complementary PWM functions
- *
-@verbatim
-  ==============================================================================
-                 ##### Timer Complementary PWM functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Start the Complementary PWM.
-    (+) Stop the Complementary PWM.
-    (+) Start the Complementary PWM and enable interrupts.
-    (+) Stop the Complementary PWM and disable interrupts.
-    (+) Start the Complementary PWM and enable DMA transfers.
-    (+) Stop the Complementary PWM and disable DMA transfers.
-    (+) Start the Complementary Input Capture measurement.
-    (+) Stop the Complementary Input Capture.
-    (+) Start the Complementary Input Capture and enable interrupts.
-    (+) Stop the Complementary Input Capture and disable interrupts.
-    (+) Start the Complementary Input Capture and enable DMA transfers.
-    (+) Stop the Complementary Input Capture and disable DMA transfers.
-    (+) Start the Complementary One Pulse generation.
-    (+) Stop the Complementary One Pulse.
-    (+) Start the Complementary One Pulse and enable interrupts.
-    (+) Stop the Complementary One Pulse and disable interrupts.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Starts the PWM signal generation on the complementary output.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
-  /* Enable the complementary PWM output  */
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
-  /* Enable the Main Output */
-  __HAL_TIM_MOE_ENABLE(htim);
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the PWM signal generation on the complementary output.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be disabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
-  /* Disable the complementary PWM output  */
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
-  /* Disable the Main Output */
-  __HAL_TIM_MOE_DISABLE(htim);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the PWM signal generation in interrupt mode on the
-  *         complementary output.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be disabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Enable the TIM Capture/Compare 1 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Enable the TIM Capture/Compare 2 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Enable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Enable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Enable the TIM Break interrupt */
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
-
-  /* Enable the complementary PWM output  */
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
-  /* Enable the Main Output */
-  __HAL_TIM_MOE_ENABLE(htim);
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the PWM signal generation in interrupt mode on the
-  *         complementary output.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be disabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  uint32_t tmpccer = 0;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Disable the TIM Capture/Compare 1 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Capture/Compare 2 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Disable the complementary PWM output  */
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
-  /* Disable the TIM Break interrupt (only if no more channel is active) */
-  tmpccer = htim->Instance->CCER;
-  if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
-  {
-    __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
-  }
-
-  /* Disable the Main Output */
-  __HAL_TIM_MOE_DISABLE(htim);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM PWM signal generation in DMA mode on the
-  *         complementary output
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  pData: The source Buffer address.
-  * @param  Length: The length of data to be transferred from memory to TIM peripheral
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
-  if((htim->State == HAL_TIM_STATE_BUSY))
-  {
-     return HAL_BUSY;
-  }
-  else if((htim->State == HAL_TIM_STATE_READY))
-  {
-    if(((uint32_t)pData == 0 ) && (Length > 0))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      htim->State = HAL_TIM_STATE_BUSY;
-    }
-  }
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
-
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
-
-      /* Enable the TIM Capture/Compare 1 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
-
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
-
-      /* Enable the TIM Capture/Compare 2 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
-
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-
-      /* Enable the TIM Capture/Compare 3 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-     /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
-
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-
-      /* Enable the TIM Capture/Compare 4 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Enable the complementary PWM output  */
-     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
-  /* Enable the Main Output */
-    __HAL_TIM_MOE_ENABLE(htim);
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM PWM signal generation in DMA mode on the complementary
-  *         output
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be disabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Disable the TIM Capture/Compare 1 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Capture/Compare 2 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Capture/Compare 3 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 4 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Disable the complementary PWM output */
-    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
-  /* Disable the Main Output */
-    __HAL_TIM_MOE_DISABLE(htim);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Change the htim state */
-  htim->State = HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
- *  @brief    Timer Complementary One Pulse functions
- *
-@verbatim
-  ==============================================================================
-                ##### Timer Complementary One Pulse functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Start the Complementary One Pulse generation.
-    (+) Stop the Complementary One Pulse.
-    (+) Start the Complementary One Pulse and enable interrupts.
-    (+) Stop the Complementary One Pulse and disable interrupts.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Starts the TIM One Pulse signal generation on the complemetary
-  *         output.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  OutputChannel: TIM Channel to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-  {
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
-
-  /* Enable the complementary One Pulse output */
-  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
-
-  /* Enable the Main Output */
-  __HAL_TIM_MOE_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM One Pulse signal generation on the complementary
-  *         output.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  OutputChannel: TIM Channel to be disabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
-
-  /* Disable the complementary One Pulse output */
-    TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
-
-  /* Disable the Main Output */
-    __HAL_TIM_MOE_DISABLE(htim);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM One Pulse signal generation in interrupt mode on the
-  *         complementary channel.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  OutputChannel: TIM Channel to be enabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
-
-  /* Enable the TIM Capture/Compare 1 interrupt */
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-
-  /* Enable the TIM Capture/Compare 2 interrupt */
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-
-  /* Enable the complementary One Pulse output */
-  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
-
-  /* Enable the Main Output */
-  __HAL_TIM_MOE_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-  }
-
-/**
-  * @brief  Stops the TIM One Pulse signal generation in interrupt mode on the
-  *         complementary channel.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  OutputChannel: TIM Channel to be disabled.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
-
-  /* Disable the TIM Capture/Compare 1 interrupt */
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-
-  /* Disable the TIM Capture/Compare 2 interrupt */
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-
-  /* Disable the complementary One Pulse output */
-  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
-
-  /* Disable the Main Output */
-  __HAL_TIM_MOE_DISABLE(htim);
-
-  /* Disable the Peripheral */
-   __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
- *  @brief   	Peripheral Control functions
- *
-@verbatim
-  ==============================================================================
-                    ##### Peripheral Control functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
-    (+) Configure External Clock source.
-    (+) Configure Complementary channels, break features and dead time.
-    (+) Configure Master and the Slave synchronization.
-    (+) Configure the commutation event in case of use of the Hall sensor interface.
-    (+) Configure the DMA Burst Mode.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Configure the TIM commutation event sequence.
-  * @note  This function is mandatory to use the commutation event in order to
-  *        update the configuration at each commutation detection on the TRGI input of the Timer,
-  *        the typical use of this feature is with the use of another Timer(interface Timer)
-  *        configured in Hall sensor interface, this interface Timer will generate the
-  *        commutation at its TRGO output (connected to Timer used in this function) each time
-  *        the TI1 of the Interface Timer detect a commutation at its input TI1.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_TS_ITR0: Internal trigger 0 selected
-  *            @arg TIM_TS_ITR1: Internal trigger 1 selected
-  *            @arg TIM_TS_ITR2: Internal trigger 2 selected
-  *            @arg TIM_TS_ITR3: Internal trigger 3 selected
-  *            @arg TIM_TS_NONE: No trigger is needed
-  * @param  CommutationSource: the Commutation Event source.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
-  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
-
-  __HAL_LOCK(htim);
-
-  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
-      (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
-  {
-    /* Select the Input trigger */
-    htim->Instance->SMCR &= ~TIM_SMCR_TS;
-    htim->Instance->SMCR |= InputTrigger;
-  }
-
-  /* Select the Capture Compare preload feature */
-  htim->Instance->CR2 |= TIM_CR2_CCPC;
-  /* Select the Commutation event source */
-  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
-  htim->Instance->CR2 |= CommutationSource;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configure the TIM commutation event sequence with interrupt.
-  * @note  This function is mandatory to use the commutation event in order to
-  *        update the configuration at each commutation detection on the TRGI input of the Timer,
-  *        the typical use of this feature is with the use of another Timer(interface Timer)
-  *        configured in Hall sensor interface, this interface Timer will generate the
-  *        commutation at its TRGO output (connected to Timer used in this function) each time
-  *        the TI1 of the Interface Timer detect a commutation at its input TI1.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_TS_ITR0: Internal trigger 0 selected
-  *            @arg TIM_TS_ITR1: Internal trigger 1 selected
-  *            @arg TIM_TS_ITR2: Internal trigger 2 selected
-  *            @arg TIM_TS_ITR3: Internal trigger 3 selected
-  *            @arg TIM_TS_NONE: No trigger is needed
-  * @param  CommutationSource: the Commutation Event source.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
-  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
-
-  __HAL_LOCK(htim);
-
-  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
-      (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
-  {
-    /* Select the Input trigger */
-    htim->Instance->SMCR &= ~TIM_SMCR_TS;
-    htim->Instance->SMCR |= InputTrigger;
-  }
-
-  /* Select the Capture Compare preload feature */
-  htim->Instance->CR2 |= TIM_CR2_CCPC;
-  /* Select the Commutation event source */
-  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
-  htim->Instance->CR2 |= CommutationSource;
-
-  /* Enable the Commutation Interrupt Request */
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configure the TIM commutation event sequence with DMA.
-  * @note  This function is mandatory to use the commutation event in order to
-  *        update the configuration at each commutation detection on the TRGI input of the Timer,
-  *        the typical use of this feature is with the use of another Timer(interface Timer)
-  *        configured in Hall sensor interface, this interface Timer will generate the
-  *        commutation at its TRGO output (connected to Timer used in this function) each time
-  *        the TI1 of the Interface Timer detect a commutation at its input TI1.
-  * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_TS_ITR0: Internal trigger 0 selected
-  *            @arg TIM_TS_ITR1: Internal trigger 1 selected
-  *            @arg TIM_TS_ITR2: Internal trigger 2 selected
-  *            @arg TIM_TS_ITR3: Internal trigger 3 selected
-  *            @arg TIM_TS_NONE: No trigger is needed
-  * @param  CommutationSource: the Commutation Event source.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
-  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
-
-  __HAL_LOCK(htim);
-
-  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
-      (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
-  {
-    /* Select the Input trigger */
-    htim->Instance->SMCR &= ~TIM_SMCR_TS;
-    htim->Instance->SMCR |= InputTrigger;
-  }
-
-  /* Select the Capture Compare preload feature */
-  htim->Instance->CR2 |= TIM_CR2_CCPC;
-  /* Select the Commutation event source */
-  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
-  htim->Instance->CR2 |= CommutationSource;
-
-  /* Enable the Commutation DMA Request */
-  /* Set the DMA Commutation Callback */
-  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
-  /* Set the DMA error callback */
-  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError;
-
-  /* Enable the Commutation DMA Request */
-  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM Output Compare Channels according to the specified
-  *         parameters in the TIM_OC_InitTypeDef.
-  * @param  htim: TIM Output Compare handle
-  * @param  sConfig: TIM Output Compare configuration structure
-  * @param  Channel : TIM Channels to configure
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
-  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CHANNELS(Channel));
-  assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
-  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
-
-  /* Check input state */
-  __HAL_LOCK(htim);
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
-     /* Configure the TIM Channel 1 in Output Compare */
-      TIM_OC1_SetConfig(htim->Instance, sConfig);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-      /* Configure the TIM Channel 2 in Output Compare */
-      TIM_OC2_SetConfig(htim->Instance, sConfig);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
-      /* Configure the TIM Channel 3 in Output Compare */
-      TIM_OC3_SetConfig(htim->Instance, sConfig);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
-       /* Configure the TIM Channel 4 in Output Compare */
-       TIM_OC4_SetConfig(htim->Instance, sConfig);
-    }
-    break;
-
-    case TIM_CHANNEL_5:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
-
-       /* Configure the TIM Channel 5 in Output Compare */
-       TIM_OC5_SetConfig(htim->Instance, sConfig);
-    }
-    break;
-
-    case TIM_CHANNEL_6:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
-
-       /* Configure the TIM Channel 6 in Output Compare */
-       TIM_OC6_SetConfig(htim->Instance, sConfig);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM PWM  channels according to the specified
-  *         parameters in the TIM_OC_InitTypeDef.
-  * @param  htim: TIM PWM handle
-  * @param  sConfig: TIM PWM configuration structure
-  * @param  Channel : TIM Channels to be configured
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
-  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
-                                            TIM_OC_InitTypeDef* sConfig,
-                                            uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CHANNELS(Channel));
-  assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
-  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
-  assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
-
-  /* Check input state */
-  __HAL_LOCK(htim);
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
-      /* Configure the Channel 1 in PWM mode */
-      TIM_OC1_SetConfig(htim->Instance, sConfig);
-
-      /* Set the Preload enable bit for channel1 */
-      htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
-
-      /* Configure the Output Fast mode */
-      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
-      htim->Instance->CCMR1 |= sConfig->OCFastMode;
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-      /* Configure the Channel 2 in PWM mode */
-      TIM_OC2_SetConfig(htim->Instance, sConfig);
-
-      /* Set the Preload enable bit for channel2 */
-      htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
-
-      /* Configure the Output Fast mode */
-      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
-      htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
-      /* Configure the Channel 3 in PWM mode */
-      TIM_OC3_SetConfig(htim->Instance, sConfig);
-
-      /* Set the Preload enable bit for channel3 */
-      htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
-
-     /* Configure the Output Fast mode */
-      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
-      htim->Instance->CCMR2 |= sConfig->OCFastMode;
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
-      /* Configure the Channel 4 in PWM mode */
-      TIM_OC4_SetConfig(htim->Instance, sConfig);
-
-      /* Set the Preload enable bit for channel4 */
-      htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
-
-     /* Configure the Output Fast mode */
-      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
-      htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
-    }
-    break;
-
-    case TIM_CHANNEL_5:
-    {
-       /* Check the parameters */
-      assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
-
-     /* Configure the Channel 5 in PWM mode */
-      TIM_OC5_SetConfig(htim->Instance, sConfig);
-
-      /* Set the Preload enable bit for channel5*/
-      htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
-
-     /* Configure the Output Fast mode */
-      htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
-      htim->Instance->CCMR3 |= sConfig->OCFastMode;
-    }
-    break;
-
-    case TIM_CHANNEL_6:
-    {
-       /* Check the parameters */
-      assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
-
-     /* Configure the Channel 5 in PWM mode */
-      TIM_OC6_SetConfig(htim->Instance, sConfig);
-
-      /* Set the Preload enable bit for channel6 */
-      htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
-
-     /* Configure the Output Fast mode */
-      htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
-      htim->Instance->CCMR3 |= sConfig->OCFastMode << 8;
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the OCRef clear feature
-  * @param  htim: TIM handle
-  * @param  sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
-  *         contains the OCREF clear feature and parameters for the TIM peripheral.
-  * @param  Channel: specifies the TIM Channel
-  *          This parameter can be one of the following values:
-  *            @arg TIM_Channel_1: TIM Channel 1
-  *            @arg TIM_Channel_2: TIM Channel 2
-  *            @arg TIM_Channel_3: TIM Channel 3
-  *            @arg TIM_Channel_4: TIM Channel 4
-  *            @arg TIM_Channel_5: TIM Channel 5
-  *            @arg TIM_Channel_6: TIM Channel 6
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
-                                           TIM_ClearInputConfigTypeDef *sClearInputConfig,
-                                           uint32_t Channel)
-{
-  uint32_t tmpsmcr = 0;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
-
-  /* Check input state */
-  __HAL_LOCK(htim);
-
-  switch (sClearInputConfig->ClearInputSource)
-  {
-    case TIM_CLEARINPUTSOURCE_NONE:
-    {
-      /* Get the TIMx SMCR register value */
-      tmpsmcr = htim->Instance->SMCR;
-
-      /* Clear the OCREF clear selection bit */
-      tmpsmcr &= ~TIM_SMCR_OCCS;
-
-      /* Clear the ETR Bits */
-      tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
-
-      /* Set TIMx_SMCR */
-      htim->Instance->SMCR = tmpsmcr;
-   }
-    break;
-
-    case TIM_CLEARINPUTSOURCE_OCREFCLR:
-    {
-      /* Clear the OCREF clear selection bit */
-      htim->Instance->SMCR &= ~TIM_SMCR_OCCS;
-    }
-    break;
-
-    case TIM_CLEARINPUTSOURCE_ETR:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
-      assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
-      assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
-
-      TIM_ETR_SetConfig(htim->Instance,
-                        sClearInputConfig->ClearInputPrescaler,
-                        sClearInputConfig->ClearInputPolarity,
-                        sClearInputConfig->ClearInputFilter);
-
-      /* Set the OCREF clear selection bit */
-      htim->Instance->SMCR |= TIM_SMCR_OCCS;
-    }
-    break;
-    default:
-    break;
-  }
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-      {
-        if(sClearInputConfig->ClearInputState != RESET)
-        {
-          /* Enable the Ocref clear feature for Channel 1 */
-          htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
-        }
-        else
-        {
-          /* Disable the Ocref clear feature for Channel 1 */
-          htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
-        }
-      }
-      break;
-    case TIM_CHANNEL_2:
-      {
-        if(sClearInputConfig->ClearInputState != RESET)
-        {
-          /* Enable the Ocref clear feature for Channel 2 */
-          htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
-        }
-        else
-        {
-          /* Disable the Ocref clear feature for Channel 2 */
-          htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
-        }
-      }
-    break;
-    case TIM_CHANNEL_3:
-      {
-        if(sClearInputConfig->ClearInputState != RESET)
-        {
-          /* Enable the Ocref clear feature for Channel 3 */
-          htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
-        }
-        else
-        {
-          /* Disable the Ocref clear feature for Channel 3 */
-          htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
-        }
-      }
-    break;
-    case TIM_CHANNEL_4:
-      {
-        if(sClearInputConfig->ClearInputState != RESET)
-        {
-          /* Enable the Ocref clear feature for Channel 4 */
-          htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
-        }
-        else
-        {
-          /* Disable the Ocref clear feature for Channel 4 */
-          htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
-        }
-      }
-    break;
-    case TIM_CHANNEL_5:
-      {
-        if(sClearInputConfig->ClearInputState != RESET)
-        {
-          /* Enable the Ocref clear feature for Channel 1 */
-          htim->Instance->CCMR3 |= TIM_CCMR3_OC5CE;
-        }
-        else
-        {
-          /* Disable the Ocref clear feature for Channel 1 */
-          htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5CE;
-        }
-      }
-    break;
-    case TIM_CHANNEL_6:
-      {
-        if(sClearInputConfig->ClearInputState != RESET)
-        {
-          /* Enable the Ocref clear feature for Channel 1 */
-          htim->Instance->CCMR3 |= TIM_CCMR3_OC6CE;
-        }
-        else
-        {
-          /* Disable the Ocref clear feature for Channel 1 */
-          htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6CE;
-        }
-      }
-    break;
-    default:
-    break;
-  }
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the TIM in master mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that
-  *         contains the selected trigger output (TRGO) and the Master/Slave
-  *         mode.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig)
-{
-  uint32_t tmpcr2;
-  uint32_t tmpsmcr;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
-  assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
-
-  /* Check input state */
-  __HAL_LOCK(htim);
-
- /* Get the TIMx CR2 register value */
-  tmpcr2 = htim->Instance->CR2;
-
-  /* Get the TIMx SMCR register value */
-  tmpsmcr = htim->Instance->SMCR;
-
-  /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
-  if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
-  {
-    /* Check the parameters */
-    assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
-
-    /* Clear the MMS2 bits */
-    tmpcr2 &= ~TIM_CR2_MMS2;
-    /* Select the TRGO2 source*/
-    tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
-  }
-
-  /* Reset the MMS Bits */
-  tmpcr2 &= ~TIM_CR2_MMS;
-  /* Select the TRGO source */
-  tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
-
-  /* Reset the MSM Bit */
-  tmpsmcr &= ~TIM_SMCR_MSM;
-  /* Set master mode */
-  tmpsmcr |= sMasterConfig->MasterSlaveMode;
-
-  /* Update TIMx CR2 */
-  htim->Instance->CR2 = tmpcr2;
-
-  /* Update TIMx SMCR */
-  htim->Instance->SMCR = tmpsmcr;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief   Configures the Break feature, dead time, Lock level, OSSI/OSSR State
-  *         and the AOE(automatic output enable).
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfig_TypeDef structure that
-  *         contains the BDTR Register configuration  information for the TIM peripheral.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
-                                              TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
-{
-  uint32_t tmpbdtr = 0;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
-  assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
-  assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
-  assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
-  assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
-  assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
-  assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
-  assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
-  assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
-  assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
-  assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
-
-  /* Check input state */
-  __HAL_LOCK(htim);
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
-     the OSSI State, the dead time value and the Automatic Output Enable Bit */
-
-  /* Clear the BDTR bits */
-  tmpbdtr &= ~(TIM_BDTR_DTG | TIM_BDTR_LOCK |  TIM_BDTR_OSSI |
-               TIM_BDTR_OSSR | TIM_BDTR_BKE | TIM_BDTR_BKP |
-               TIM_BDTR_AOE | TIM_BDTR_MOE | TIM_BDTR_BKF |
-               TIM_BDTR_BK2F | TIM_BDTR_BK2E | TIM_BDTR_BK2P);
-
-  /* Set the BDTR bits */
-  tmpbdtr |= sBreakDeadTimeConfig->DeadTime;
-  tmpbdtr |= sBreakDeadTimeConfig->LockLevel;
-  tmpbdtr |= sBreakDeadTimeConfig->OffStateIDLEMode;
-  tmpbdtr |= sBreakDeadTimeConfig->OffStateRunMode;
-  tmpbdtr |= sBreakDeadTimeConfig->BreakState;
-  tmpbdtr |= sBreakDeadTimeConfig->BreakPolarity;
-  tmpbdtr |= sBreakDeadTimeConfig->AutomaticOutput;
-  tmpbdtr |= (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT);
-  tmpbdtr |= (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT);
-  tmpbdtr |= sBreakDeadTimeConfig->Break2State;
-  tmpbdtr |= sBreakDeadTimeConfig->Break2Polarity;
-
-  /* Set TIMx_BDTR */
-  htim->Instance->BDTR = tmpbdtr;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
-/**
-  * @brief  Configures the break input source.
-  * @param  htim: TIM handle.
-  * @param  BreakInput: Break input to configure
-  *          This parameter can be one of the following values:
-  *            @arg TIM_BREAKINPUT_BRK: Timer break input
-  *            @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
-  * @param  sBreakInputConfig: Break input source configuration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
-                                             uint32_t BreakInput,
-                                             TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
-
-{
-  uint32_t tmporx = 0;
-  uint32_t bkin_enable_mask = 0;
-  uint32_t bkin_enable_bitpos = 0;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_BREAKINPUT(BreakInput));
-  assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
-  assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
-
-  /* Check input state */
-  __HAL_LOCK(htim);
-
-  switch(sBreakInputConfig->Source)
-  {
-  case TIM_BREAKINPUTSOURCE_BKIN:
-    {
-      bkin_enable_mask = TIM1_AF1_BKINE;
-      bkin_enable_bitpos = 0;
-    }
-    break;
-
-  case TIM_BREAKINPUTSOURCE_DFSDM1:
-    {
-      bkin_enable_mask = TIM1_AF1_BKDF1BKE;
-      bkin_enable_bitpos = 8;
-    }
-    break;
-
-  default:
-    break;
-  }
-
-  switch(BreakInput)
-  {
-    case TIM_BREAKINPUT_BRK:
-      {
-        /* Get the TIMx_AF1 register value */
-        tmporx = htim->Instance->AF1;
-
-        /* Enable the break input */
-        tmporx &= ~bkin_enable_mask;
-        tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
-
-        /* Set TIMx_AF1 */
-        htim->Instance->AF1 = tmporx;
-      }
-        break;
-    case TIM_BREAKINPUT_BRK2:
-      {
-        /* Get the TIMx_AF2 register value */
-        tmporx = htim->Instance->AF2;
-
-        /* Enable the break input */
-        tmporx &= ~bkin_enable_mask;
-        tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
-
-        /* Set TIMx_AF2 */
-        htim->Instance->AF2 = tmporx;
-      }
-      break;
-  default:
-    break;
-  }
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
-/**
-  * @brief  Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Remap: specifies the TIM input remapping source.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default)
-  *            @arg TIM_TIM2_ETH_PTP:   TIM2 ITR1 input is connected to ETH PTP trigger output.
-  *            @arg TIM_TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF.
-  *            @arg TIM_TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF.
-  *            @arg TIM_TIM5_GPIO:      TIM5 CH4 input is connected to dedicated Timer pin(default)
-  *            @arg TIM_TIM5_LSI:       TIM5 CH4 input is connected to LSI clock.
-  *            @arg TIM_TIM5_LSE:       TIM5 CH4 input is connected to LSE clock.
-  *            @arg TIM_TIM5_RTC:       TIM5 CH4 input is connected to RTC Output event.
-  *            @arg TIM_TIM11_GPIO:     TIM11 CH4 input is connected to dedicated Timer pin(default)
-  *            @arg TIM_TIM11_SPDIF:    SPDIF Frame synchronous
-  *            @arg TIM_TIM11_HSE:      TIM11 CH4 input is connected to HSE_RTC clock
-  *                                     (HSE divided by a programmable prescaler)
-  *            @arg TIM_TIM11_MCO1:     TIM11 CH1 input is connected to MCO1
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
-{
-  __HAL_LOCK(htim);
-
-  /* Check parameters */
-  assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_REMAP(Remap));
-
-  /* Set the Timer remapping configuration */
-  htim->Instance->OR = Remap;
-
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Group channel 5 and channel 1, 2 or 3
-  * @param  htim: TIM handle.
-  * @param  OCRef: specifies the reference signal(s) the OC5REF is combined with.
-  *         This parameter can be any combination of the following values:
-  *         TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
-  *         TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
-  *         TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
-  *         TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t OCRef)
-{
-  /* Check parameters */
-  assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_GROUPCH5(OCRef));
-
-  /* Process Locked */
-  __HAL_LOCK(htim);
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Clear GC5Cx bit fields */
-  htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3|TIM_CCR5_GC5C2|TIM_CCR5_GC5C1);
-
-  /* Set GC5Cx bit fields */
-  htim->Instance->CCR5 |= OCRef;
-
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
-  * @brief    Extended Callbacks functions
- *
-@verbatim
-  ==============================================================================
-                    ##### Extension Callbacks functions #####
-  ==============================================================================
-  [..]
-    This section provides Extension TIM callback functions:
-    (+) Timer Commutation callback
-    (+) Timer Break callback
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Hall commutation changed callback in non blocking mode
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIMEx_CommutationCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Hall Break detection callback in non blocking mode
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIMEx_BreakCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
- *  @brief    Extended Peripheral State functions
- *
-@verbatim
-  ==============================================================================
-                ##### Extension Peripheral State functions #####
-  ==============================================================================
-  [..]
-    This subsection permits to get in run-time the status of the peripheral
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the TIM Hall Sensor interface state
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL state
-  */
-HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
-{
-  return htim->State;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @brief  TIM DMA Commutation callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  htim->State= HAL_TIM_STATE_READY;
-
-  HAL_TIMEx_CommutationCallback(htim);
-}
-
-/**
-  * @brief  Enables or disables the TIM Capture Compare Channel xN.
-  * @param  TIMx to select the TIM peripheral
-  * @param  Channel: specifies the TIM Channel
-  *          This parameter can be one of the following values:
-  *            @arg TIM_Channel_1: TIM Channel 1
-  *            @arg TIM_Channel_2: TIM Channel 2
-  *            @arg TIM_Channel_3: TIM Channel 3
-  * @param  ChannelNState: specifies the TIM Channel CCxNE bit new state.
-  *          This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
-  * @retval None
-  */
-static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
-{
-  uint32_t tmp = 0;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_ADVANCED_INSTANCE(TIMx));
-  assert_param(IS_TIM_COMPLEMENTARY_CHANNELS(Channel));
-
-  tmp = TIM_CCER_CC1NE << Channel;
-
-  /* Reset the CCxNE Bit */
-  TIMx->CCER &= ~tmp;
-
-  /* Set or reset the CCxNE Bit */
-  TIMx->CCER |= (uint32_t)(ChannelNState << Channel);
-}
-
-/**
-  * @brief  Timer Output Compare 5 configuration
-  * @param  TIMx to select the TIM peripheral
-  * @param  OC_Config: The output configuration structure
-  * @retval None
-  */
-static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
-  uint32_t tmpccmrx = 0;
-  uint32_t tmpccer = 0;
-  uint32_t tmpcr2 = 0;
-
-  /* Disable the output: Reset the CCxE Bit */
-  TIMx->CCER &= ~TIM_CCER_CC5E;
-
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
-  /* Get the TIMx CR2 register value */
-  tmpcr2 =  TIMx->CR2;
-  /* Get the TIMx CCMR1 register value */
-  tmpccmrx = TIMx->CCMR3;
-
-  /* Reset the Output Compare Mode Bits */
-  tmpccmrx &= ~(TIM_CCMR3_OC5M);
-  /* Select the Output Compare Mode */
-  tmpccmrx |= OC_Config->OCMode;
-
-  /* Reset the Output Polarity level */
-  tmpccer &= ~TIM_CCER_CC5P;
-  /* Set the Output Compare Polarity */
-  tmpccer |= (OC_Config->OCPolarity << 16);
-
-  if(IS_TIM_BREAK_INSTANCE(TIMx))
-  {
-    /* Reset the Output Compare IDLE State */
-    tmpcr2 &= ~TIM_CR2_OIS5;
-    /* Set the Output Idle state */
-    tmpcr2 |= (OC_Config->OCIdleState << 8);
-  }
-  /* Write to TIMx CR2 */
-  TIMx->CR2 = tmpcr2;
-
-  /* Write to TIMx CCMR3 */
-  TIMx->CCMR3 = tmpccmrx;
-
-  /* Set the Capture Compare Register value */
-  TIMx->CCR5 = OC_Config->Pulse;
-
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Timer Output Compare 6 configuration
-  * @param  TIMx to select the TIM peripheral
-  * @param  OC_Config: The output configuration structure
-  * @retval None
-  */
-static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
-  uint32_t tmpccmrx = 0;
-  uint32_t tmpccer = 0;
-  uint32_t tmpcr2 = 0;
-
-  /* Disable the output: Reset the CCxE Bit */
-  TIMx->CCER &= ~TIM_CCER_CC6E;
-
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
-  /* Get the TIMx CR2 register value */
-  tmpcr2 =  TIMx->CR2;
-  /* Get the TIMx CCMR1 register value */
-  tmpccmrx = TIMx->CCMR3;
-
-  /* Reset the Output Compare Mode Bits */
-  tmpccmrx &= ~(TIM_CCMR3_OC6M);
-  /* Select the Output Compare Mode */
-  tmpccmrx |= (OC_Config->OCMode << 8);
-
-  /* Reset the Output Polarity level */
-  tmpccer &= (uint32_t)~TIM_CCER_CC6P;
-  /* Set the Output Compare Polarity */
-  tmpccer |= (OC_Config->OCPolarity << 20);
-
-  if(IS_TIM_BREAK_INSTANCE(TIMx))
-  {
-    /* Reset the Output Compare IDLE State */
-    tmpcr2 &= ~TIM_CR2_OIS6;
-    /* Set the Output Idle state */
-    tmpcr2 |= (OC_Config->OCIdleState << 10);
-  }
-
-  /* Write to TIMx CR2 */
-  TIMx->CR2 = tmpcr2;
-
-  /* Write to TIMx CCMR3 */
-  TIMx->CCMR3 = tmpccmrx;
-
-  /* Set the Capture Compare Register value */
-  TIMx->CCR6 = OC_Config->Pulse;
-
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_TIM_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_uart.c b/stmhal/hal/f7/src/stm32f7xx_hal_uart.c
deleted file mode 100644
index 060659414a..0000000000
--- a/stmhal/hal/f7/src/stm32f7xx_hal_uart.c
+++ /dev/null
@@ -1,2184 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_uart.c
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   UART HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions
-  *           + Peripheral State and Errors functions
-  *
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-  [..]
-    The UART HAL driver can be used as follows:
-
-    (#) Declare a UART_HandleTypeDef handle structure.
-
-    (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
-        (##) Enable the USARTx interface clock.
-        (##) UART pins configuration:
-            (+++) Enable the clock for the UART GPIOs.
-            (+++) Configure these UART pins as alternate function pull-up.
-        (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
-             and HAL_UART_Receive_IT() APIs):
-            (+++) Configure the USARTx interrupt priority.
-            (+++) Enable the NVIC USART IRQ handle.
-        (##) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
-             and HAL_UART_Receive_DMA() APIs):
-            (+++) Declare a DMA handle structure for the Tx/Rx stream.
-            (+++) Enable the DMAx interface clock.
-            (+++) Configure the declared DMA handle structure with the required
-                  Tx/Rx parameters.
-            (+++) Configure the DMA Tx/Rx Stream.
-            (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
-            (+++) Configure the priority and enable the NVIC for the transfer complete
-                  interrupt on the DMA Tx/Rx Stream.
-
-    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
-        flow control and Mode(Receiver/Transmitter) in the Init structure.
-
-    (#) For the UART asynchronous mode, initialize the UART registers by calling
-        the HAL_UART_Init() API.
-
-    (#) For the UART Half duplex mode, initialize the UART registers by calling
-        the HAL_HalfDuplex_Init() API.
-
-    (#) For the LIN mode, initialize the UART registers by calling the HAL_LIN_Init() API.
-
-    (#) For the Multi-Processor mode, initialize the UART registers by calling
-        the HAL_MultiProcessor_Init() API.
-
-     [..]
-       (@) The specific UART interrupts (Transmission complete interrupt,
-            RXNE interrupt and Error Interrupts) will be managed using the macros
-            __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit
-            and receive process.
-
-     [..]
-       (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the
-            low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized
-            HAL_UART_MspInit() API.
-
-     [..]
-        Three operation modes are available within this driver :
-
-     *** Polling mode IO operation ***
-     =================================
-     [..]
-       (+) Send an amount of data in blocking mode using HAL_UART_Transmit()
-       (+) Receive an amount of data in blocking mode using HAL_UART_Receive()
-
-     *** Interrupt mode IO operation ***
-     ===================================
-     [..]
-       (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT()
-       (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
-            add his own code by customization of function pointer HAL_UART_TxCpltCallback
-       (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT()
-       (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
-            add his own code by customization of function pointer HAL_UART_RxCpltCallback
-       (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
-            add his own code by customization of function pointer HAL_UART_ErrorCallback
-
-     *** DMA mode IO operation ***
-     ==============================
-     [..]
-       (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA()
-       (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can
-            add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback
-       (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
-            add his own code by customization of function pointer HAL_UART_TxCpltCallback
-       (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA()
-       (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can
-            add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback
-       (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
-            add his own code by customization of function pointer HAL_UART_RxCpltCallback
-       (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
-            add his own code by customization of function pointer HAL_UART_ErrorCallback
-       (+) Pause the DMA Transfer using HAL_UART_DMAPause()
-       (+) Resume the DMA Transfer using HAL_UART_DMAResume()
-       (+) Stop the DMA Transfer using HAL_UART_DMAStop()
-
-     *** UART HAL driver macros list ***
-     =============================================
-     [..]
-       Below the list of most used macros in UART HAL driver.
-
-      (+) __HAL_UART_ENABLE: Enable the UART peripheral
-      (+) __HAL_UART_DISABLE: Disable the UART peripheral
-      (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not
-      (+) __HAL_UART_CLEAR_IT : Clears the specified UART ISR flag
-      (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt
-      (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt
-      (+) __HAL_UART_GET_IT_SOURCE: Check whether the specified UART interrupt has occurred or not
-
-     [..]
-       (@) You can refer to the UART HAL driver header file for more useful macros
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup UART UART
-  * @brief HAL UART module driver
-  * @{
-  */
-
-#ifdef HAL_UART_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup UART_Private_Constants UART Private Constants
-  * @{
-  */
-#define UART_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
-                                     USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8))
-/**
-  * @}
-  */
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup UART_Private_Functions
-  * @{
-  */
-static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
-static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
-static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMAError(DMA_HandleTypeDef *hdma);
-static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
-static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
-static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup UART_Exported_Functions UART Exported Functions
-  * @{
-  */
-
-/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
-  *  @brief    Initialization and Configuration functions
-  *
-@verbatim
-===============================================================================
-            ##### Initialization and Configuration functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
-    in asynchronous mode.
-      (+) For the asynchronous mode only these parameters can be configured:
-        (++) Baud Rate
-        (++) Word Length
-        (++) Stop Bit
-        (++) Parity: If the parity is enabled, then the MSB bit of the data written
-             in the data register is transmitted but is changed by the parity bit.
-             Depending on the frame length defined by the M bit (8-bits or 9-bits),
-             please refer to Reference manual for possible UART frame formats.
-        (++) Hardware flow control
-        (++) Receiver/transmitter modes
-        (++) Over Sampling Method
-    [..]
-    The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs
-    follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor
-    configuration procedures (details for the procedures are available in reference manual (RM0329)).
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Initializes the UART mode according to the specified
-  *         parameters in the UART_InitTypeDef and creates the associated handle .
-  * @param huart: uart handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
-{
-  /* Check the UART handle allocation */
-  if(huart == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
-  {
-    /* Check the parameters */
-    assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
-  }
-  else
-  {
-    /* Check the parameters */
-    assert_param(IS_UART_INSTANCE(huart->Instance));
-  }
-
-  if(huart->gState == HAL_UART_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    huart->Lock = HAL_UNLOCKED;
-
-    /* Init the low level hardware : GPIO, CLOCK */
-    HAL_UART_MspInit(huart);
-  }
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /* Disable the Peripheral */
-  __HAL_UART_DISABLE(huart);
-
-  /* Set the UART Communication parameters */
-  if (UART_SetConfig(huart) == HAL_ERROR)
-  {
-    return HAL_ERROR;
-  }
-
-  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
-  {
-    UART_AdvFeatureConfig(huart);
-  }
-
-  /* In asynchronous mode, the following bits must be kept cleared:
-  - LINEN and CLKEN bits in the USART_CR2 register,
-  - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
-  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
-  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
-
-  /* Enable the Peripheral */
-  __HAL_UART_ENABLE(huart);
-
-  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
-  return (UART_CheckIdleState(huart));
-}
-
-/**
-  * @brief Initializes the half-duplex mode according to the specified
-  *         parameters in the UART_InitTypeDef and creates the associated handle .
-  * @param huart: UART handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
-{
-  /* Check the UART handle allocation */
-  if(huart == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  if(huart->gState == HAL_UART_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    huart->Lock = HAL_UNLOCKED;
-
-    /* Init the low level hardware : GPIO, CLOCK */
-    HAL_UART_MspInit(huart);
-  }
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /* Disable the Peripheral */
-  __HAL_UART_DISABLE(huart);
-
-  /* Set the UART Communication parameters */
-  if (UART_SetConfig(huart) == HAL_ERROR)
-  {
-    return HAL_ERROR;
-  }
-
-  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
-  {
-    UART_AdvFeatureConfig(huart);
-  }
-
-  /* In half-duplex mode, the following bits must be kept cleared:
-  - LINEN and CLKEN bits in the USART_CR2 register,
-  - SCEN and IREN bits in the USART_CR3 register.*/
-  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
-  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));
-
-  /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
-  SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
-
-  /* Enable the Peripheral */
-  __HAL_UART_ENABLE(huart);
-
-  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
-  return (UART_CheckIdleState(huart));
-}
-
-
-/**
-  * @brief Initialize the LIN mode according to the specified
-  *        parameters in the UART_InitTypeDef and creates the associated handle .
-  * @param huart: UART handle.
-  * @param BreakDetectLength: specifies the LIN break detection length.
-  *        This parameter can be one of the following values:
-  *          @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection
-  *          @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
-{
-  /* Check the UART handle allocation */
-  if(huart == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_UART_INSTANCE(huart->Instance));
-  assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
-  assert_param(IS_LIN_WORD_LENGTH(huart->Init.WordLength));
-
-  if(huart->gState == HAL_UART_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    huart->Lock = HAL_UNLOCKED;
-
-    /* Init the low level hardware : GPIO, CLOCK */
-    HAL_UART_MspInit(huart);
-  }
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /* Disable the Peripheral */
-  __HAL_UART_DISABLE(huart);
-
-  /* Set the UART Communication parameters */
-  if (UART_SetConfig(huart) == HAL_ERROR)
-  {
-    return HAL_ERROR;
-  }
-
-  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
-  {
-    UART_AdvFeatureConfig(huart);
-  }
-
-  /* In LIN mode, the following bits must be kept cleared:
-  - LINEN and CLKEN bits in the USART_CR2 register,
-  - SCEN and IREN bits in the USART_CR3 register.*/
-  CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
-  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));
-
-  /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
-  SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);
-
-  /* Set the USART LIN Break detection length. */
-  MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);
-
-  /* Enable the Peripheral */
-  __HAL_UART_ENABLE(huart);
-
-  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
-  return (UART_CheckIdleState(huart));
-}
-
-
-/**
-  * @brief Initialize the multiprocessor mode according to the specified
-  *        parameters in the UART_InitTypeDef and initialize the associated handle.
-  * @param huart: UART handle.
-  * @param Address: UART node address (4-, 6-, 7- or 8-bit long).
-  * @param WakeUpMethod: specifies the UART wakeup method.
-  *        This parameter can be one of the following values:
-  *          @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection
-  *          @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark
-  * @note  If the user resorts to idle line detection wake up, the Address parameter
-  *        is useless and ignored by the initialization function.
-  * @note  If the user resorts to address mark wake up, the address length detection
-  *        is configured by default to 4 bits only. For the UART to be able to
-  *        manage 6-, 7- or 8-bit long addresses detection
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
-{
-  /* Check the UART handle allocation */
-  if(huart == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the wake up method parameter */
-  assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
-
-  if(huart->gState == HAL_UART_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    huart->Lock = HAL_UNLOCKED;
-
-    /* Init the low level hardware : GPIO, CLOCK */
-    HAL_UART_MspInit(huart);
-  }
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /* Disable the Peripheral */
-  __HAL_UART_DISABLE(huart);
-
-  /* Set the UART Communication parameters */
-  if (UART_SetConfig(huart) == HAL_ERROR)
-  {
-    return HAL_ERROR;
-  }
-
-  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
-  {
-    UART_AdvFeatureConfig(huart);
-  }
-
-  /* In multiprocessor mode, the following bits must be kept cleared:
-  - LINEN and CLKEN bits in the USART_CR2 register,
-  - SCEN, HDSEL and IREN  bits in the USART_CR3 register. */
-  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
-  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
-
-  if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK)
-  {
-    /* If address mark wake up method is chosen, set the USART address node */
-    MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS));
-  }
-
-  /* Set the wake up method by setting the WAKE bit in the CR1 register */
-  MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);
-
-  /* Enable the Peripheral */
-  __HAL_UART_ENABLE(huart);
-
-  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
-  return (UART_CheckIdleState(huart));
-}
-
-
-/**
-  * @brief Initialize the RS485 Driver enable feature according to the specified
-  *         parameters in the UART_InitTypeDef and creates the associated handle.
-  * @param huart: UART handle.
-  * @param Polarity: select the driver enable polarity.
-  *        This parameter can be one of the following values:
-  *          @arg @ref UART_DE_POLARITY_HIGH DE signal is active high
-  *          @arg @ref UART_DE_POLARITY_LOW  DE signal is active low
-  * @param AssertionTime: Driver Enable assertion time:
-  *                         5-bit value defining the time between the activation of the DE (Driver Enable)
-  *                         signal and the beginning of the start bit. It is expressed in sample time
-  *                         units (1/8 or 1/16 bit time, depending on the oversampling rate)
-  * @param DeassertionTime: Driver Enable deassertion time:
-  *                         5-bit value defining the time between the end of the last stop bit, in a
-  *                         transmitted message, and the de-activation of the DE (Driver Enable) signal.
-  *                         It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
-  *                         oversampling rate).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
-{
-  uint32_t temp = 0x0;
-
-  /* Check the UART handle allocation */
-  if(huart == NULL)
-  {
-    return HAL_ERROR;
-  }
-  /* Check the Driver Enable UART instance */
-  assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));
-
-  /* Check the Driver Enable polarity */
-  assert_param(IS_UART_DE_POLARITY(Polarity));
-
-  /* Check the Driver Enable assertion time */
-  assert_param(IS_UART_ASSERTIONTIME(AssertionTime));
-
-  /* Check the Driver Enable deassertion time */
-  assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));
-
-  if(huart->gState == HAL_UART_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    huart->Lock = HAL_UNLOCKED;
-
-    /* Init the low level hardware : GPIO, CLOCK, CORTEX */
-    HAL_UART_MspInit(huart);
-  }
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /* Disable the Peripheral */
-  __HAL_UART_DISABLE(huart);
-
-  /* Set the UART Communication parameters */
-  if (UART_SetConfig(huart) == HAL_ERROR)
-  {
-    return HAL_ERROR;
-  }
-
-  if(huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
-  {
-    UART_AdvFeatureConfig(huart);
-  }
-
-  /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
-  SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
-
-  /* Set the Driver Enable polarity */
-  MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
-
-  /* Set the Driver Enable assertion and deassertion times */
-  temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
-  temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
-  MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT|USART_CR1_DEAT), temp);
-
-  /* Enable the Peripheral */
-  __HAL_UART_ENABLE(huart);
-
-  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
-  return (UART_CheckIdleState(huart));
-}
-
-/**
-  * @brief DeInitializes the UART peripheral
-  * @param huart: uart handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
-{
-  /* Check the UART handle allocation */
-  if(huart == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_UART_INSTANCE(huart->Instance));
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /* Disable the Peripheral */
-  __HAL_UART_DISABLE(huart);
-
-  huart->Instance->CR1 = 0x0U;
-  huart->Instance->CR2 = 0x0U;
-  huart->Instance->CR3 = 0x0U;
-
-  /* DeInit the low level hardware */
-  HAL_UART_MspDeInit(huart);
-
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
-  huart->gState    = HAL_UART_STATE_RESET;
-  huart->RxState   = HAL_UART_STATE_RESET;
-
-  /* Process Unlock */
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief UART MSP Init
-  * @param huart: uart handle
-  * @retval None
-  */
-__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_UART_MspInit can be implemented in the user file
-   */
-}
-
-/**
-  * @brief UART MSP DeInit
-  * @param huart: uart handle
-  * @retval None
-  */
-__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_UART_MspDeInit can be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup UART_Exported_Functions_Group2 IO operation functions
-  * @brief UART Transmit/Receive functions
-  *
-@verbatim
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================
-    This subsection provides a set of functions allowing to manage the UART asynchronous
-    and Half duplex data transfers.
-
-    (#) There are two mode of transfer:
-       (+) Blocking mode: The communication is performed in polling mode.
-           The HAL status of all data processing is returned by the same function
-           after finishing transfer.
-       (+) Non-Blocking mode: The communication is performed using Interrupts
-           or DMA, These API's return the HAL status.
-           The end of the data processing will be indicated through the
-           dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
-           using DMA mode.
-           The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
-           will be executed respectively at the end of the transmit or Receive process
-           The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected
-
-    (#) Blocking mode API's are :
-        (+) HAL_UART_Transmit()
-        (+) HAL_UART_Receive()
-
-    (#) Non-Blocking mode API's with Interrupt are :
-        (+) HAL_UART_Transmit_IT()
-        (+) HAL_UART_Receive_IT()
-        (+) HAL_UART_IRQHandler()
-        (+) UART_Transmit_IT()
-        (+) UART_Receive_IT()
-
-    (#) Non-Blocking mode API's with DMA are :
-        (+) HAL_UART_Transmit_DMA()
-        (+) HAL_UART_Receive_DMA()
-        (+) HAL_UART_DMAPause()
-        (+) HAL_UART_DMAResume()
-        (+) HAL_UART_DMAStop()
-
-    (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
-        (+) HAL_UART_TxHalfCpltCallback()
-        (+) HAL_UART_TxCpltCallback()
-        (+) HAL_UART_RxHalfCpltCallback()
-        (+) HAL_UART_RxCpltCallback()
-        (+) HAL_UART_ErrorCallback()
-
-
-    -@- In the Half duplex communication, it is forbidden to run the transmit
-        and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Send an amount of data in blocking mode.
-  * @param huart: UART handle.
-  * @param pData: Pointer to data buffer.
-  * @param Size: Amount of data to be sent.
-  * @param Timeout: Timeout duration.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint16_t* tmp;
-  uint32_t tickstart = 0U;
-
-  /* Check that a Tx process is not already ongoing */
-  if(huart->gState == HAL_UART_STATE_READY)
-  {
-    if((pData == NULL ) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(huart);
-
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
-    huart->gState = HAL_UART_STATE_BUSY_TX;
-
-    /* Init tickstart for timeout managment*/
-    tickstart = HAL_GetTick();
-
-    huart->TxXferSize = Size;
-    huart->TxXferCount = Size;
-    while(huart->TxXferCount > 0U)
-    {
-      huart->TxXferCount--;
-      if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
-      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
-      {
-        tmp = (uint16_t*) pData;
-        huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
-        pData += 2;
-      }
-      else
-      {
-        huart->Instance->TDR = (*pData++ & (uint8_t)0xFFU);
-      }
-    }
-    if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    /* At end of Tx process, restore huart->gState to Ready */
-    huart->gState = HAL_UART_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(huart);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Receive an amount of data in blocking mode.
-  * @param huart: UART handle.
-  * @param pData: pointer to data buffer.
-  * @param Size: amount of data to be received.
-  * @param Timeout: Timeout duration.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint16_t* tmp;
-  uint16_t uhMask;
-  uint32_t tickstart = 0U;
-
-  /* Check that a Rx process is not already ongoing */
-  if(huart->RxState == HAL_UART_STATE_READY)
-  {
-    if((pData == NULL ) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(huart);
-
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
-    huart->RxState = HAL_UART_STATE_BUSY_RX;
-
-    /* Init tickstart for timeout managment*/
-    tickstart = HAL_GetTick();
-
-    huart->RxXferSize = Size;
-    huart->RxXferCount = Size;
-
-    /* Computation of UART mask to apply to RDR register */
-    UART_MASK_COMPUTATION(huart);
-    uhMask = huart->Mask;
-
-    /* as long as data have to be received */
-    while(huart->RxXferCount > 0U)
-    {
-      huart->RxXferCount--;
-      if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
-      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
-      {
-        tmp = (uint16_t*) pData ;
-        *tmp = (uint16_t)(huart->Instance->RDR & uhMask);
-        pData +=2U;
-      }
-      else
-      {
-        *pData++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
-      }
-    }
-
-    /* At end of Rx process, restore huart->RxState to Ready */
-    huart->RxState = HAL_UART_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(huart);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Send an amount of data in interrupt mode.
-  * @param huart: UART handle.
-  * @param pData: pointer to data buffer.
-  * @param Size: amount of data to be sent.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
-  /* Check that a Tx process is not already ongoing */
-  if(huart->gState == HAL_UART_STATE_READY)
-  {
-    if((pData == NULL ) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(huart);
-
-    huart->pTxBuffPtr = pData;
-    huart->TxXferSize = Size;
-    huart->TxXferCount = Size;
-
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
-    huart->gState = HAL_UART_STATE_BUSY_TX;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(huart);
-
-    /* Enable the UART Transmit Data Register Empty Interrupt */
-    SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Receive an amount of data in interrupt mode.
-  * @param huart: UART handle.
-  * @param pData: pointer to data buffer.
-  * @param Size: amount of data to be received.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
-  /* Check that a Rx process is not already ongoing */
-  if(huart->RxState == HAL_UART_STATE_READY)
-  {
-    if((pData == NULL ) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(huart);
-
-    huart->pRxBuffPtr = pData;
-    huart->RxXferSize = Size;
-    huart->RxXferCount = Size;
-
-    /* Computation of UART mask to apply to RDR register */
-    UART_MASK_COMPUTATION(huart);
-
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
-    huart->RxState = HAL_UART_STATE_BUSY_RX;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(huart);
-
-    /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
-    SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-    /* Enable the UART Parity Error and Data Register not empty Interrupts */
-    SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Send an amount of data in DMA mode.
-  * @param huart: UART handle.
-  * @param pData: pointer to data buffer.
-  * @param Size: amount of data to be sent.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
-  uint32_t *tmp;
-
-  /* Check that a Tx process is not already ongoing */
-  if(huart->gState == HAL_UART_STATE_READY)
-  {
-    if((pData == NULL ) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(huart);
-
-    huart->pTxBuffPtr = pData;
-    huart->TxXferSize = Size;
-    huart->TxXferCount = Size;
-
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
-    huart->gState = HAL_UART_STATE_BUSY_TX;
-
-    /* Set the UART DMA transfer complete callback */
-    huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
-
-    /* Set the UART DMA Half transfer complete callback */
-    huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
-
-    /* Set the DMA error callback */
-    huart->hdmatx->XferErrorCallback = UART_DMAError;
-
-    /* Set the DMA abort callback */
-    huart->hdmatx->XferAbortCallback = NULL;
-
-    /* Enable the UART transmit DMA channel */
-    tmp = (uint32_t*)&pData;
-    HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t*)tmp, (uint32_t)&huart->Instance->TDR, Size);
-
-    /* Clear the TC flag in the SR register by writing 0 to it */
-    __HAL_UART_CLEAR_IT(huart, UART_FLAG_TC);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(huart);
-
-    /* Enable the DMA transfer for transmit request by setting the DMAT bit
-       in the UART CR3 register */
-    SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Receive an amount of data in DMA mode.
-  * @param huart: UART handle.
-  * @param pData: pointer to data buffer.
-  * @param Size: amount of data to be received.
-  * @note   When the UART parity is enabled (PCE = 1), the received data contain
-  *         the parity bit (MSB position).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
-  uint32_t *tmp;
-
-  /* Check that a Rx process is not already ongoing */
-  if(huart->RxState == HAL_UART_STATE_READY)
-  {
-    if((pData == NULL ) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(huart);
-
-    huart->pRxBuffPtr = pData;
-    huart->RxXferSize = Size;
-
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
-    huart->RxState = HAL_UART_STATE_BUSY_RX;
-
-    /* Set the UART DMA transfer complete callback */
-    huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
-
-    /* Set the UART DMA Half transfer complete callback */
-    huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
-
-    /* Set the DMA error callback */
-    huart->hdmarx->XferErrorCallback = UART_DMAError;
-
-    /* Set the DMA abort callback */
-    huart->hdmarx->XferAbortCallback = NULL;
-
-    /* Enable the DMA channel */
-    tmp = (uint32_t*)&pData;
-    HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, *(uint32_t*)tmp, Size);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(huart);
-
-    /* Enable the UART Parity Error Interrupt */
-    SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
-
-    /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
-    SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-    /* Enable the DMA transfer for the receiver request by setting the DMAR bit
-    in the UART CR3 register */
-    SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Pause the DMA Transfer.
-  * @param huart: UART handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
-{
-  /* Process Locked */
-  __HAL_LOCK(huart);
-
-  if ((huart->gState == HAL_UART_STATE_BUSY_TX) &&
-      (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)))
-  {
-    /* Disable the UART DMA Tx request */
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-  }
-  if ((huart->RxState == HAL_UART_STATE_BUSY_RX) &&
-      (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
-  {
-    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
-    CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-    /* Disable the UART DMA Rx request */
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Resume the DMA Transfer.
-  * @param huart: UART handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
-{
-  /* Process Locked */
-  __HAL_LOCK(huart);
-
-  if(huart->gState == HAL_UART_STATE_BUSY_TX)
-  {
-    /* Enable the UART DMA Tx request */
-    SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-  }
-  if(huart->RxState == HAL_UART_STATE_BUSY_RX)
-  {
-    /* Clear the Overrun flag before resuming the Rx transfer*/
-    __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF);
-
-    /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
-    SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
-    SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-    /* Enable the UART DMA Rx request */
-    SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-  }
-
-  /* If the UART peripheral is still not enabled, enable it */
-  if ((huart->Instance->CR1 & USART_CR1_UE) == 0U)
-  {
-    /* Enable UART peripheral */
-    __HAL_UART_ENABLE(huart);
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Stop the DMA Transfer.
-  * @param huart: UART handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
-{
-  /* The Lock is not implemented on this API to allow the user application
-     to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() /
-     HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback:
-     indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
-     interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
-     the stream and the corresponding call back is executed. */
-
-  /* Stop UART DMA Tx request if ongoing */
-  if ((huart->gState == HAL_UART_STATE_BUSY_TX) &&
-      (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)))
-  {
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
-    /* Abort the UART DMA Tx channel */
-    if(huart->hdmatx != NULL)
-    {
-      HAL_DMA_Abort(huart->hdmatx);
-    }
-
-    UART_EndTxTransfer(huart);
-  }
-
-  /* Stop UART DMA Rx request if ongoing */
-  if ((huart->RxState == HAL_UART_STATE_BUSY_RX) &&
-      (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
-  {
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
-    /* Abort the UART DMA Rx channel */
-    if(huart->hdmarx != NULL)
-    {
-      HAL_DMA_Abort(huart->hdmarx);
-    }
-
-    UART_EndRxTransfer(huart);
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief This function handles UART interrupt request.
-  * @param huart: uart handle
-  * @retval None
-  */
-void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
-{
-  uint32_t isrflags   = READ_REG(huart->Instance->ISR);
-  uint32_t cr1its     = READ_REG(huart->Instance->CR1);
-  uint32_t cr3its     = READ_REG(huart->Instance->CR3);
-  uint32_t errorflags;
-
-  /* If no error occurs */
-  errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
-  if (errorflags == RESET)
-  {
-    /* UART in mode Receiver ---------------------------------------------------*/
-    if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
-    {
-      UART_Receive_IT(huart);
-      return;
-    }
-  }
-
-  /* If some errors occur */
-  if(   (errorflags != RESET)
-     && (   ((cr3its & USART_CR3_EIE) != RESET)
-         || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) )
-  {
-
-    /* UART parity error interrupt occurred -------------------------------------*/
-    if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
-    {
-      __HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF);
-
-      huart->ErrorCode |= HAL_UART_ERROR_PE;
-    }
-
-    /* UART frame error interrupt occurred --------------------------------------*/
-    if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
-    {
-      __HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF);
-
-      huart->ErrorCode |= HAL_UART_ERROR_FE;
-    }
-
-    /* UART noise error interrupt occurred --------------------------------------*/
-    if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
-    {
-      __HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF);
-
-      huart->ErrorCode |= HAL_UART_ERROR_NE;
-    }
-
-    /* UART Over-Run interrupt occurred -----------------------------------------*/
-    if(((isrflags & USART_ISR_ORE) != RESET) &&
-       (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
-    {
-      __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF);
-
-      huart->ErrorCode |= HAL_UART_ERROR_ORE;
-    }
-
-    /* Call UART Error Call back function if need be --------------------------*/
-    if(huart->ErrorCode != HAL_UART_ERROR_NONE)
-    {
-      /* UART in mode Receiver ---------------------------------------------------*/
-      if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
-      {
-        UART_Receive_IT(huart);
-      }
-
-      /* If Overrun error occurs, or if any error occurs in DMA mode reception,
-         consider error as blocking */
-      if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) ||
-          (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
-      {
-        /* Blocking error : transfer is aborted
-           Set the UART state ready to be able to start again the process,
-           Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
-        UART_EndRxTransfer(huart);
-
-        /* Disable the UART DMA Rx request if enabled */
-        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
-        {
-          CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
-          /* Abort the UART DMA Rx channel */
-          if(huart->hdmarx != NULL)
-          {
-            /* Set the UART DMA Abort callback :
-            will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
-            huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
-
-            /* Abort DMA RX */
-            if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
-            {
-              /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
-              huart->hdmarx->XferAbortCallback(huart->hdmarx);
-            }
-          }
-          else
-          {
-            /* Call user error callback */
-            HAL_UART_ErrorCallback(huart);
-          }
-        }
-        else
-        {
-          /* Call user error callback */
-          HAL_UART_ErrorCallback(huart);
-        }
-      }
-      else
-      {
-        /* Non Blocking error : transfer could go on.
-           Error is notified to user through user error callback */
-        HAL_UART_ErrorCallback(huart);
-        huart->ErrorCode = HAL_UART_ERROR_NONE;
-      }
-    }
-    return;
-
-  } /* End if some error occurs */
-
-  /* UART in mode Transmitter ------------------------------------------------*/
-  if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
-  {
-    UART_Transmit_IT(huart);
-    return;
-  }
-
-  /* UART in mode Transmitter (transmission end) -----------------------------*/
-  if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
-  {
-    UART_EndTransmit_IT(huart);
-    return;
-  }
-
-}
-
-/**
-  * @brief  This function handles UART Communication Timeout.
-  * @param  huart UART handle
-  * @param  Flag specifies the UART flag to check.
-  * @param  Status The new Flag status (SET or RESET).
-  * @param  Tickstart Tick start value
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
-{
-  /* Wait until flag is set */
-  while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
-  {
-    /* Check for the Timeout */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0U)||((HAL_GetTick()-Tickstart) >=  Timeout))
-      {
-        /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
-        CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
-        CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-        huart->gState = HAL_UART_STATE_READY;
-        huart->RxState = HAL_UART_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(huart);
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief DMA UART transmit process complete callback
-  * @param hdma: DMA handle
-  * @retval None
-  */
-static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  /* DMA Normal mode*/
-  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
-  {
-    huart->TxXferCount = 0U;
-
-    /* Disable the DMA transfer for transmit request by setting the DMAT bit
-       in the UART CR3 register */
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
-    /* Enable the UART Transmit Complete Interrupt */
-    SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
-  }
-  /* DMA Circular mode */
-  else
-  {
-    HAL_UART_TxCpltCallback(huart);
-  }
-}
-
-/**
-  * @brief DMA UART transmit process half complete callback
-  * @param hdma : DMA handle
-  * @retval None
-  */
-static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  HAL_UART_TxHalfCpltCallback(huart);
-}
-
-/**
-  * @brief DMA UART receive process complete callback
-  * @param hdma: DMA handle
-  * @retval None
-  */
-static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  /* DMA Normal mode */
-  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
-  {
-    huart->RxXferCount = 0U;
-
-    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
-    CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-    /* Disable the DMA transfer for the receiver request by setting the DMAR bit
-    in the UART CR3 register */
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
-	/* At end of Rx process, restore huart->RxState to Ready */
-    huart->RxState = HAL_UART_STATE_READY;
-  }
-  HAL_UART_RxCpltCallback(huart);
-}
-
-/**
-  * @brief DMA UART receive process half complete callback
-  * @param hdma : DMA handle
-  * @retval None
-  */
-static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  HAL_UART_RxHalfCpltCallback(huart);
-}
-
-/**
-  * @brief DMA UART communication error callback
-  * @param hdma: DMA handle
-  * @retval None
-  */
-static void UART_DMAError(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  huart->RxXferCount = 0U;
-  huart->TxXferCount = 0U;
-  /* Stop UART DMA Tx request if ongoing */
-  if (  (huart->gState == HAL_UART_STATE_BUSY_TX)
-      &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) )
-  {
-    UART_EndTxTransfer(huart);
-  }
-
-  /* Stop UART DMA Rx request if ongoing */
-  if (  (huart->RxState == HAL_UART_STATE_BUSY_RX)
-      &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) )
-  {
-    UART_EndRxTransfer(huart);
-  }
-  SET_BIT(huart->ErrorCode, HAL_UART_ERROR_DMA);
-  HAL_UART_ErrorCallback(huart);
-}
-
-/**
-  * @brief DMA UART communication abort callback, when call by HAL services on Error
-  *        (To be called at end of DMA Abort procedure following error occurrence).
-  * @param hdma: DMA handle.
-  * @retval None
-  */
-static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
-  huart->RxXferCount = 0U;
-  huart->TxXferCount = 0U;
-
-  HAL_UART_ErrorCallback(huart);
-}
-
-/**
-  * @brief Tx Transfer completed callbacks
-  * @param huart: uart handle
-  * @retval None
-  */
- __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_UART_TxCpltCallback can be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Tx Half Transfer completed callbacks.
-  * @param  huart: UART handle
-  * @retval None
-  */
- __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_UART_TxHalfCpltCallback can be implemented in the user file
-   */
-}
-
-/**
-  * @brief Rx Transfer completed callbacks
-  * @param huart: uart handle
-  * @retval None
-  */
-__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_UART_RxCpltCallback can be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Rx Half Transfer completed callbacks.
-  * @param  huart: UART handle
-  * @retval None
-  */
-__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_UART_RxHalfCpltCallback can be implemented in the user file
-   */
-}
-
-/**
-  * @brief UART error callbacks
-  * @param huart: uart handle
-  * @retval None
-  */
- __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_UART_ErrorCallback can be implemented in the user file
-   */
-}
-
-/**
-  * @brief Send an amount of data in interrupt mode
-  *         Function called under interruption only, once
-  *         interruptions have been enabled by HAL_UART_Transmit_IT()
-  * @param  huart: UART handle
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
-{
-  uint16_t* tmp;
-
-  /* Check that a Tx process is ongoing */
-  if (huart->gState == HAL_UART_STATE_BUSY_TX)
-  {
-
-    if(huart->TxXferCount == 0U)
-    {
-      /* Disable the UART Transmit Data Register Empty Interrupt */
-      CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
-
-      /* Enable the UART Transmit Complete Interrupt */
-      SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
-
-      return HAL_OK;
-    }
-    else
-    {
-      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
-      {
-        tmp = (uint16_t*) huart->pTxBuffPtr;
-        huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
-        huart->pTxBuffPtr += 2U;
-      }
-      else
-      {
-        huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFFU);
-      }
-
-      huart->TxXferCount--;
-
-      return HAL_OK;
-    }
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Wrap up transmission in non-blocking mode.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
-{
-  /* Disable the UART Transmit Complete Interrupt */
-  CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
-
-  /* Tx process is ended, restore huart->gState to Ready */
-  huart->gState = HAL_UART_STATE_READY;
-
-  HAL_UART_TxCpltCallback(huart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Receive an amount of data in interrupt mode
-  *         Function called under interruption only, once
-  *         interruptions have been enabled by HAL_UART_Receive_IT()
-  * @param  huart: UART handle
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
-{
-  uint16_t* tmp;
-  uint16_t uhMask = huart->Mask;
-
-  /* Check that a Rx process is ongoing */
-  if(huart->RxState == HAL_UART_STATE_BUSY_RX)
-  {
-
-    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
-    {
-      tmp = (uint16_t*) huart->pRxBuffPtr ;
-      *tmp = (uint16_t)(huart->Instance->RDR & uhMask);
-      huart->pRxBuffPtr +=2;
-    }
-    else
-    {
-      *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
-    }
-
-    if(--huart->RxXferCount == 0)
-    {
-      /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
-      CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
-
-      /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
-      CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-      /* Rx process is completed, restore huart->RxState to Ready */
-      huart->RxState = HAL_UART_STATE_READY;
-
-      HAL_UART_RxCpltCallback(huart);
-
-      return HAL_OK;
-    }
-
-    return HAL_OK;
-  }
-  else
-  {
-    /* Clear RXNE interrupt flag */
-    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
-
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
-  * @param  huart: UART handle.
-  * @retval None
-  */
-static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
-{
-  /* Disable TXEIE and TCIE interrupts */
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
-  /* At end of Tx process, restore huart->gState to Ready */
-  huart->gState = HAL_UART_STATE_READY;
-}
-
-
-/**
-  * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
-  * @param  huart: UART handle.
-  * @retval None
-  */
-static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
-{
-  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
-  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-  /* At end of Rx process, restore huart->RxState to Ready */
-  huart->RxState = HAL_UART_STATE_READY;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
-  *  @brief   UART control functions
-  *
-@verbatim
- ===============================================================================
-                      ##### Peripheral Control functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to control the UART.
-     (+) HAL_UART_GetState() API is helpful to check in run-time the state of the UART peripheral.
-     (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
-     (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
-     (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
-     (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
-     (+) UART_SetConfig() API configures the UART peripheral
-     (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features
-     (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization
-     (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
-     (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
-     (+) HAL_LIN_SendBreak() API transmits the break characters
-	 (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
-         detection length to more than 4 bits for multiprocessor address mark wake up.
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Enable UART in mute mode (doesn't mean UART enters mute mode;
-  * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called)
-  * @param huart: UART handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
-{
-  /* Process Locked */
-  __HAL_LOCK(huart);
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /* Enable USART mute mode by setting the MME bit in the CR1 register */
-  SET_BIT(huart->Instance->CR1, USART_CR1_MME);
-
-  huart->gState = HAL_UART_STATE_READY;
-
-  return (UART_CheckIdleState(huart));
-}
-
-/**
-  * @brief Disable UART mute mode (doesn't mean it actually wakes up the software,
-  * as it may not have been in mute mode at this very moment).
-  * @param huart: uart handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
-{
-  /* Process Locked */
-  __HAL_LOCK(huart);
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-   /* Disable USART mute mode by clearing the MME bit in the CR1 register */
-  CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);
-
-  huart->gState = HAL_UART_STATE_READY;
-
-  return (UART_CheckIdleState(huart));
-}
-
-/**
-  * @brief Enter UART mute mode (means UART actually enters mute mode).
-  * To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
-  * @param huart: uart handle
-  * @retval HAL status
-  */
-void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
-{
-  __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);
-}
-
-
-
-/**
-  * @brief return the UART state
-  * @param huart: uart handle
-  * @retval HAL state
-  */
-HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
-{
-  uint32_t temp1= 0x00U, temp2 = 0x00U;
-  temp1 = huart->gState;
-  temp2 = huart->RxState;
-
-  return (HAL_UART_StateTypeDef)(temp1 | temp2);
-}
-
-/**
-* @brief  Return the UART error code
-* @param  huart : pointer to a UART_HandleTypeDef structure that contains
-  *              the configuration information for the specified UART.
-* @retval UART Error Code
-*/
-uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
-{
-  return huart->ErrorCode;
-}
-
-/**
-  * @brief Configure the UART peripheral
-  * @param huart: uart handle
-  * @retval None
-  */
-HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
-{
-  uint32_t tmpreg                     = 0x00000000U;
-  UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED;
-  uint16_t brrtemp                    = 0x0000U;
-  uint16_t usartdiv                   = 0x0000U;
-  HAL_StatusTypeDef ret               = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
-  assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
-  assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
-  assert_param(IS_UART_PARITY(huart->Init.Parity));
-  assert_param(IS_UART_MODE(huart->Init.Mode));
-  assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
-  assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
-
-
-  /*-------------------------- USART CR1 Configuration -----------------------*/
-  /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure
-   *  the UART Word Length, Parity, Mode and oversampling:
-   *  set the M bits according to huart->Init.WordLength value
-   *  set PCE and PS bits according to huart->Init.Parity value
-   *  set TE and RE bits according to huart->Init.Mode value
-   *  set OVER8 bit according to huart->Init.OverSampling value */
-  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
-  MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
-
-  /*-------------------------- USART CR2 Configuration -----------------------*/
-  /* Configure the UART Stop Bits: Set STOP[13:12] bits according
-   * to huart->Init.StopBits value */
-  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
-
-  /*-------------------------- USART CR3 Configuration -----------------------*/
-  /* Configure
-   * - UART HardWare Flow Control: set CTSE and RTSE bits according
-   *   to huart->Init.HwFlowCtl value
-   * - one-bit sampling method versus three samples' majority rule according
-   *   to huart->Init.OneBitSampling */
-  tmpreg = (uint32_t)huart->Init.HwFlowCtl | huart->Init.OneBitSampling ;
-  MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT), tmpreg);
-
-  /*-------------------------- USART BRR Configuration -----------------------*/
-  UART_GETCLOCKSOURCE(huart, clocksource);
-
-  /* Check UART Over Sampling to set Baud Rate Register */
-  if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
-  {
-    switch (clocksource)
-    {
-    case UART_CLOCKSOURCE_PCLK1:
-        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
-      break;
-    case UART_CLOCKSOURCE_PCLK2:
-        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
-      break;
-    case UART_CLOCKSOURCE_HSI:
-        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate));
-      break;
-    case UART_CLOCKSOURCE_SYSCLK:
-        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
-      break;
-    case UART_CLOCKSOURCE_LSE:
-        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate));
-      break;
-      case UART_CLOCKSOURCE_UNDEFINED:
-    default:
-        ret = HAL_ERROR;
-      break;
-    }
-
-    brrtemp = usartdiv & 0xFFF0U;
-    brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
-    huart->Instance->BRR = brrtemp;
-  }
-  else
-  {
-    switch (clocksource)
-    {
-    case UART_CLOCKSOURCE_PCLK1:
-        huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
-      break;
-    case UART_CLOCKSOURCE_PCLK2:
-        huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
-      break;
-    case UART_CLOCKSOURCE_HSI:
-        huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));
-      break;
-    case UART_CLOCKSOURCE_SYSCLK:
-        huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
-      break;
-    case UART_CLOCKSOURCE_LSE:
-        huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate));
-      break;
-      case UART_CLOCKSOURCE_UNDEFINED:
-    default:
-        ret = HAL_ERROR;
-      break;
-    }
-  }
-
-  return ret;
-
-}
-
-
-/**
-  * @brief Configure the UART peripheral advanced features
-  * @param huart: uart handle
-  * @retval None
-  */
-void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
-{
-  /* Check whether the set of advanced features to configure is properly set */
-  assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
-
-  /* if required, configure TX pin active level inversion */
-  if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
-  {
-    assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
-    MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
-  }
-
-  /* if required, configure RX pin active level inversion */
-  if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
-  {
-    assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
-    MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
-  }
-
-  /* if required, configure data inversion */
-  if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
-  {
-    assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
-    MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
-  }
-
-  /* if required, configure RX/TX pins swap */
-  if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
-  {
-    assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
-    MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
-  }
-
-  /* if required, configure RX overrun detection disabling */
-  if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
-  {
-    assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
-    MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
-  }
-
-  /* if required, configure DMA disabling on reception error */
-  if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
-  {
-    assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
-    MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
-  }
-
-  /* if required, configure auto Baud rate detection scheme */
-  if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
-  {
-    assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
-    MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
-    /* set auto Baudrate detection parameters if detection is enabled */
-    if(huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
-    {
-      assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
-      MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
-    }
-  }
-
-  /* if required, configure MSB first on communication line */
-  if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
-  {
-    assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
-    MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
-  }
-}
-
-
-
-/**
-  * @brief Check the UART Idle State
-  * @param huart: uart handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
-{
-  uint32_t tickstart = 0U;
-
-  /* Initialize the UART ErrorCode */
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
-
-  /* Init tickstart for timeout managment*/
-  tickstart = HAL_GetTick();
-
-  /* Check if the Transmitter is enabled */
-  if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
-  {
-    /* Wait until TEACK flag is set */
-    if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
-    {
-      /* Timeout Occurred */
-      return HAL_TIMEOUT;
-    }
-  }
-  /* Check if the Receiver is enabled */
-  if((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
-  {
-    /* Wait until REACK flag is set */
-    if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
-    {
-      /* Timeout Occurred */
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Initialize the UART State */
-  huart->gState= HAL_UART_STATE_READY;
-  huart->RxState= HAL_UART_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enables the UART transmitter and disables the UART receiver.
-  * @param  huart: UART handle
-  * @retval HAL status
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
-{
-  /* Process Locked */
-  __HAL_LOCK(huart);
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /* Clear TE and RE bits */
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
-  /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
-  SET_BIT(huart->Instance->CR1, USART_CR1_TE);
-
-  huart->gState= HAL_UART_STATE_READY;
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enables the UART receiver and disables the UART transmitter.
-  * @param  huart: UART handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
-{
-  /* Process Locked */
-  __HAL_LOCK(huart);
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /* Clear TE and RE bits */
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
-  /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
-  SET_BIT(huart->Instance->CR1, USART_CR1_RE);
-
-  huart->gState = HAL_UART_STATE_READY;
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  Transmits break characters.
-  * @param  huart: UART handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
-{
-  /* Check the parameters */
-  assert_param(IS_UART_INSTANCE(huart->Instance));
-
-  /* Process Locked */
-  __HAL_LOCK(huart);
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /* Send break characters */
-  SET_BIT(huart->Instance->RQR, UART_SENDBREAK_REQUEST);
-
-  huart->gState = HAL_UART_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief By default in multiprocessor mode, when the wake up method is set
-  *        to address mark, the UART handles only 4-bit long addresses detection;
-  *        this API allows to enable longer addresses detection (6-, 7- or 8-bit
-  *        long).
-  * @note  Addresses detection lengths are: 6-bit address detection in 7-bit data mode,
-  *        7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
-  * @param huart: UART handle.
-  * @param AddressLength: this parameter can be one of the following values:
-  *          @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address
-  *          @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)
-{
-  /* Check the UART handle allocation */
-  if(huart == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the address length parameter */
-  assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /* Disable the Peripheral */
-  __HAL_UART_DISABLE(huart);
-
-  /* Set the address length */
-  MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
-
-  /* Enable the Peripheral */
-  __HAL_UART_ENABLE(huart);
-
-  /* TEACK and/or REACK to check before moving huart->gState to Ready */
-  return (UART_CheckIdleState(huart));
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_UART_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/src/stm32f7xx_ll_sdmmc.c b/stmhal/hal/f7/src/stm32f7xx_ll_sdmmc.c
deleted file mode 100644
index 2ce4013793..0000000000
--- a/stmhal/hal/f7/src/stm32f7xx_ll_sdmmc.c
+++ /dev/null
@@ -1,509 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_ll_sdmmc.c
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   SDMMC Low Layer HAL module driver.
-  *
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the SDMMC peripheral:
-  *           + Initialization/de-initialization functions
-  *           + I/O operation functions
-  *           + Peripheral Control functions
-  *           + Peripheral State functions
-  *
-  @verbatim
-  ==============================================================================
-                       ##### SDMMC peripheral features #####
-  ==============================================================================
-    [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the APB2
-         peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDMMC cards and CE-ATA
-         devices.
-
-    [..] The SDMMC features include the following:
-         (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support
-             for three different databus modes: 1-bit (default), 4-bit and 8-bit
-         (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility)
-         (+) Full compliance with SD Memory Card Specifications Version 2.0
-         (+) Full compliance with SD I/O Card Specification Version 2.0: card support for two
-             different data bus modes: 1-bit (default) and 4-bit
-         (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol
-             Rev1.1)
-         (+) Data transfer up to 48 MHz for the 8 bit mode
-         (+) Data and command output enable signals to control external bidirectional drivers.
-
-
-                           ##### How to use this driver #####
-  ==============================================================================
-    [..]
-      This driver is a considered as a driver of service for external devices drivers
-      that interfaces with the SDMMC peripheral.
-      According to the device used (SD card/ MMC card / SDMMC card ...), a set of APIs
-      is used in the device's driver to perform SDMMC operations and functionalities.
-
-      This driver is almost transparent for the final user, it is only used to implement other
-      functionalities of the external device.
-
-    [..]
-      (+) The SDMMC clock (SDMMCCLK = 48 MHz) is coming from a specific output of PLL
-          (PLL48CLK). Before start working with SDMMC peripheral make sure that the
-          PLL is well configured.
-          The SDMMC peripheral uses two clock signals:
-          (++) SDMMC adapter clock (SDMMCCLK = 48 MHz)
-          (++) APB2 bus clock (PCLK2)
-
-          -@@- PCLK2 and SDMMC_CK clock frequencies must respect the following condition:
-               Frequency(PCLK2) >= (3 / 8 x Frequency(SDMMC_CK))
-
-      (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDMMC
-          peripheral.
-
-      (+) Enable the Power ON State using the SDMMC_PowerState_ON(SDMMCx)
-          function and disable it using the function SDMMC_PowerState_OFF(SDMMCx).
-
-      (+) Enable/Disable the clock using the __SDMMC_ENABLE()/__SDMMC_DISABLE() macros.
-
-      (+) Enable/Disable the peripheral interrupts using the macros __SDMMC_ENABLE_IT(hSDMMC, IT)
-          and __SDMMC_DISABLE_IT(hSDMMC, IT) if you need to use interrupt mode.
-
-      (+) When using the DMA mode
-          (++) Configure the DMA in the MSP layer of the external device
-          (++) Active the needed channel Request
-          (++) Enable the DMA using __SDMMC_DMA_ENABLE() macro or Disable it using the macro
-               __SDMMC_DMA_DISABLE().
-
-      (+) To control the CPSM (Command Path State Machine) and send
-          commands to the card use the SDMMC_SendCommand(SDMMCx),
-          SDMMC_GetCommandResponse() and SDMMC_GetResponse() functions. First, user has
-          to fill the command structure (pointer to SDMMC_CmdInitTypeDef) according
-          to the selected command to be sent.
-          The parameters that should be filled are:
-           (++) Command Argument
-           (++) Command Index
-           (++) Command Response type
-           (++) Command Wait
-           (++) CPSM Status (Enable or Disable).
-
-          -@@- To check if the command is well received, read the SDMMC_CMDRESP
-              register using the SDMMC_GetCommandResponse().
-              The SDMMC responses registers (SDMMC_RESP1 to SDMMC_RESP2), use the
-              SDMMC_GetResponse() function.
-
-      (+) To control the DPSM (Data Path State Machine) and send/receive
-           data to/from the card use the SDMMC_DataConfig(), SDMMC_GetDataCounter(),
-          SDMMC_ReadFIFO(), DIO_WriteFIFO() and SDMMC_GetFIFOCount() functions.
-
-    *** Read Operations ***
-    =======================
-    [..]
-      (#) First, user has to fill the data structure (pointer to
-          SDMMC_DataInitTypeDef) according to the selected data type to be received.
-          The parameters that should be filled are:
-           (++) Data TimeOut
-           (++) Data Length
-           (++) Data Block size
-           (++) Data Transfer direction: should be from card (To SDMMC)
-           (++) Data Transfer mode
-           (++) DPSM Status (Enable or Disable)
-
-      (#) Configure the SDMMC resources to receive the data from the card
-          according to selected transfer mode (Refer to Step 8, 9 and 10).
-
-      (#) Send the selected Read command (refer to step 11).
-
-      (#) Use the SDMMC flags/interrupts to check the transfer status.
-
-    *** Write Operations ***
-    ========================
-    [..]
-     (#) First, user has to fill the data structure (pointer to
-         SDMMC_DataInitTypeDef) according to the selected data type to be received.
-         The parameters that should be filled are:
-          (++) Data TimeOut
-          (++) Data Length
-          (++) Data Block size
-          (++) Data Transfer direction:  should be to card (To CARD)
-          (++) Data Transfer mode
-          (++) DPSM Status (Enable or Disable)
-
-     (#) Configure the SDMMC resources to send the data to the card according to
-         selected transfer mode.
-
-     (#) Send the selected Write command.
-
-     (#) Use the SDMMC flags/interrupts to check the transfer status.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup SDMMC_LL SDMMC Low Layer
-  * @brief Low layer module for SD
-  * @{
-  */
-
-#if defined (HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED)
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup SDMMC_LL_Exported_Functions SDMMC Low Layer Exported Functions
-  * @{
-  */
-
-/** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions
- *  @brief    Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
-              ##### Initialization/de-initialization functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the SDMMC according to the specified
-  *         parameters in the SDMMC_InitTypeDef and create the associated handle.
-  * @param  SDMMCx: Pointer to SDMMC register base
-  * @param  Init: SDMMC initialization structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_SDMMC_ALL_INSTANCE(SDMMCx));
-  assert_param(IS_SDMMC_CLOCK_EDGE(Init.ClockEdge));
-  assert_param(IS_SDMMC_CLOCK_BYPASS(Init.ClockBypass));
-  assert_param(IS_SDMMC_CLOCK_POWER_SAVE(Init.ClockPowerSave));
-  assert_param(IS_SDMMC_BUS_WIDE(Init.BusWide));
-  assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl));
-  assert_param(IS_SDMMC_CLKDIV(Init.ClockDiv));
-
-  /* Set SDMMC configuration parameters */
-  tmpreg |= (Init.ClockEdge           |\
-             Init.ClockBypass         |\
-             Init.ClockPowerSave      |\
-             Init.BusWide             |\
-             Init.HardwareFlowControl |\
-             Init.ClockDiv
-             );
-
-  /* Write to SDMMC CLKCR */
-  MODIFY_REG(SDMMCx->CLKCR, CLKCR_CLEAR_MASK, tmpreg);
-
-  return HAL_OK;
-}
-
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SDMMC_LL_Group2 IO operation functions
- *  @brief   Data transfers functions
- *
-@verbatim
- ===============================================================================
-                      ##### I/O operation functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to manage the SDMMC data
-    transfers.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Read data (word) from Rx FIFO in blocking mode (polling)
-  * @param  SDMMCx: Pointer to SDMMC register base
-  * @retval HAL status
-  */
-uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx)
-{
-  /* Read data from Rx FIFO */
-  return (SDMMCx->FIFO);
-}
-
-/**
-  * @brief  Write data (word) to Tx FIFO in blocking mode (polling)
-  * @param  SDMMCx: Pointer to SDMMC register base
-  * @param  pWriteData: pointer to data to write
-  * @retval HAL status
-  */
-HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData)
-{
-  /* Write data to FIFO */
-  SDMMCx->FIFO = *pWriteData;
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions
- *  @brief   management functions
- *
-@verbatim
- ===============================================================================
-                      ##### Peripheral Control functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to control the SDMMC data
-    transfers.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Set SDMMC Power state to ON.
-  * @param  SDMMCx: Pointer to SDMMC register base
-  * @retval HAL status
-  */
-HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx)
-{
-  /* Set power state to ON */
-  SDMMCx->POWER = SDMMC_POWER_PWRCTRL;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set SDMMC Power state to OFF.
-  * @param  SDMMCx: Pointer to SDMMC register base
-  * @retval HAL status
-  */
-HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx)
-{
-  /* Set power state to OFF */
-  SDMMCx->POWER = (uint32_t)0x00000000;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Get SDMMC Power state.
-  * @param  SDMMCx: Pointer to SDMMC register base
-  * @retval Power status of the controller. The returned value can be one of the
-  *         following values:
-  *            - 0x00: Power OFF
-  *            - 0x02: Power UP
-  *            - 0x03: Power ON
-  */
-uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx)
-{
-  return (SDMMCx->POWER & SDMMC_POWER_PWRCTRL);
-}
-
-/**
-  * @brief  Configure the SDMMC command path according to the specified parameters in
-  *         SDMMC_CmdInitTypeDef structure and send the command
-  * @param  SDMMCx: Pointer to SDMMC register base
-  * @param  Command: pointer to a SDMMC_CmdInitTypeDef structure that contains
-  *         the configuration information for the SDMMC command
-  * @retval HAL status
-  */
-HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_SDMMC_CMD_INDEX(Command->CmdIndex));
-  assert_param(IS_SDMMC_RESPONSE(Command->Response));
-  assert_param(IS_SDMMC_WAIT(Command->WaitForInterrupt));
-  assert_param(IS_SDMMC_CPSM(Command->CPSM));
-
-  /* Set the SDMMC Argument value */
-  SDMMCx->ARG = Command->Argument;
-
-  /* Set SDMMC command parameters */
-  tmpreg |= (uint32_t)(Command->CmdIndex         |\
-                       Command->Response         |\
-                       Command->WaitForInterrupt |\
-                       Command->CPSM);
-
-  /* Write to SDMMC CMD register */
-  MODIFY_REG(SDMMCx->CMD, CMD_CLEAR_MASK, tmpreg);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Return the command index of last command for which response received
-  * @param  SDMMCx: Pointer to SDMMC register base
-  * @retval Command index of the last command response received
-  */
-uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx)
-{
-  return (uint8_t)(SDMMCx->RESPCMD);
-}
-
-
-/**
-  * @brief  Return the response received from the card for the last command
-  * @param  SDMMCx: Pointer to SDMMC register base
-  * @param  Response: Specifies the SDMMC response register.
-  *          This parameter can be one of the following values:
-  *            @arg SDMMC_RESP1: Response Register 1
-  *            @arg SDMMC_RESP2: Response Register 2
-  *            @arg SDMMC_RESP3: Response Register 3
-  *            @arg SDMMC_RESP4: Response Register 4
-  * @retval The Corresponding response register value
-  */
-uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response)
-{
-  __IO uint32_t tmp = 0;
-
-  /* Check the parameters */
-  assert_param(IS_SDMMC_RESP(Response));
-
-  /* Get the response */
-  tmp = (uint32_t)&(SDMMCx->RESP1) + Response;
-
-  return (*(__IO uint32_t *) tmp);
-}
-
-/**
-  * @brief  Configure the SDMMC data path according to the specified
-  *         parameters in the SDMMC_DataInitTypeDef.
-  * @param  SDMMCx: Pointer to SDMMC register base
-  * @param  Data : pointer to a SDMMC_DataInitTypeDef structure
-  *         that contains the configuration information for the SDMMC data.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef SDMMC_DataConfig(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_SDMMC_DATA_LENGTH(Data->DataLength));
-  assert_param(IS_SDMMC_BLOCK_SIZE(Data->DataBlockSize));
-  assert_param(IS_SDMMC_TRANSFER_DIR(Data->TransferDir));
-  assert_param(IS_SDMMC_TRANSFER_MODE(Data->TransferMode));
-  assert_param(IS_SDMMC_DPSM(Data->DPSM));
-
-  /* Set the SDMMC Data TimeOut value */
-  SDMMCx->DTIMER = Data->DataTimeOut;
-
-  /* Set the SDMMC DataLength value */
-  SDMMCx->DLEN = Data->DataLength;
-
-  /* Set the SDMMC data configuration parameters */
-  tmpreg |= (uint32_t)(Data->DataBlockSize |\
-                       Data->TransferDir   |\
-                       Data->TransferMode  |\
-                       Data->DPSM);
-
-  /* Write to SDMMC DCTRL */
-  MODIFY_REG(SDMMCx->DCTRL, DCTRL_CLEAR_MASK, tmpreg);
-
-  return HAL_OK;
-
-}
-
-/**
-  * @brief  Returns number of remaining data bytes to be transferred.
-  * @param  SDMMCx: Pointer to SDMMC register base
-  * @retval Number of remaining data bytes to be transferred
-  */
-uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx)
-{
-  return (SDMMCx->DCOUNT);
-}
-
-/**
-  * @brief  Get the FIFO data
-  * @param  SDMMCx: Pointer to SDMMC register base
-  * @retval Data received
-  */
-uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx)
-{
-  return (SDMMCx->FIFO);
-}
-
-
-/**
-  * @brief  Sets one of the two options of inserting read wait interval.
-  * @param  SDMMCx: Pointer to SDMMC register base
-  * @param  SDMMC_ReadWaitMode: SDMMC Read Wait operation mode.
-  *          This parameter can be:
-  *            @arg SDMMC_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK
-  *            @arg SDMMC_READ_WAIT_MODE_DATA2: Read Wait control using SDMMC_DATA2
-  * @retval None
-  */
-HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode)
-{
-  /* Check the parameters */
-  assert_param(IS_SDMMC_READWAIT_MODE(SDMMC_ReadWaitMode));
-
-  /* Set SDMMC read wait mode */
-  MODIFY_REG(SDMMCx->DCTRL, SDMMC_DCTRL_RWMOD, SDMMC_ReadWaitMode);
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* (HAL_SD_MODULE_ENABLED) || (HAL_MMC_MODULE_ENABLED) */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/f7/src/stm32f7xx_ll_usb.c b/stmhal/hal/f7/src/stm32f7xx_ll_usb.c
deleted file mode 100644
index 51983557b4..0000000000
--- a/stmhal/hal/f7/src/stm32f7xx_ll_usb.c
+++ /dev/null
@@ -1,1692 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_ll_usb.c
-  * @author  MCD Application Team
-  * @version V1.1.2
-  * @date    23-September-2016
-  * @brief   USB Low Layer HAL module driver.
-  *
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the USB Peripheral Controller:
-  *           + Initialization/de-initialization functions
-  *           + I/O operation functions
-  *           + Peripheral Control functions
-  *           + Peripheral State functions
-  *
-  @verbatim
-  ==============================================================================
-                    ##### How to use this driver #####
-  ==============================================================================
-    [..]
-      (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.
-
-      (#) Call USB_CoreInit() API to initialize the USB Core peripheral.
-
-      (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal.h"
-
-/** @addtogroup STM32F7xx_LL_USB_DRIVER
-  * @{
-  */
-
-#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED)
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx);
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup LL_USB_Exported_Functions USB Low Layer Exported Functions
-  * @{
-  */
-
-/** @defgroup LL_USB_Group1 Initialization/de-initialization functions
- *  @brief    Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
-              ##### Initialization/de-initialization functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the USB Core
-  * @param  USBx: USB Instance
-  * @param  cfg : pointer to a USB_OTG_CfgTypeDef structure that contains
-  *         the configuration information for the specified USBx peripheral.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
-{
-  if (cfg.phy_itface == USB_OTG_ULPI_PHY)
-  {
-
-    USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
-
-    /* Init The ULPI Interface */
-    USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
-
-    /* Select vbus source */
-    USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
-    if(cfg.use_external_vbus == 1)
-    {
-      USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;
-    }
-    /* Reset after a PHY select  */
-    USB_CoreReset(USBx);
-  }
-  else /* FS interface (embedded Phy) */
-  {
-    /* Select FS Embedded PHY */
-    USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
-
-    /* Reset after a PHY select and set Host mode */
-    USB_CoreReset(USBx);
-
-    /* Deactivate the power down*/
-    USBx->GCCFG = USB_OTG_GCCFG_PWRDWN;
-  }
-
-  if(cfg.dma_enable == ENABLE)
-  {
-    USBx->GAHBCFG |= (USB_OTG_GAHBCFG_HBSTLEN_1 | USB_OTG_GAHBCFG_HBSTLEN_2);
-    USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_EnableGlobalInt
-  *         Enables the controller's Global Int in the AHB Config reg
-  * @param  USBx : Selected device
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
-{
-  USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  USB_DisableGlobalInt
-  *         Disable the controller's Global Int in the AHB Config reg
-  * @param  USBx : Selected device
-  * @retval HAL status
-*/
-HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
-{
-  USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_SetCurrentMode : Set functional mode
-  * @param  USBx : Selected device
-  * @param  mode :  current core mode
-  *          This parameter can be one of these values:
-  *            @arg USB_OTG_DEVICE_MODE: Peripheral mode
-  *            @arg USB_OTG_HOST_MODE: Host mode
-  *            @arg USB_OTG_DRD_MODE: Dual Role Device mode
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode)
-{
-  USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
-
-  if ( mode == USB_OTG_HOST_MODE)
-  {
-    USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
-  }
-  else if ( mode == USB_OTG_DEVICE_MODE)
-  {
-    USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
-  }
-  HAL_Delay(50);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_DevInit : Initializes the USB_OTG controller registers
-  *         for device mode
-  * @param  USBx : Selected device
-  * @param  cfg  : pointer to a USB_OTG_CfgTypeDef structure that contains
-  *         the configuration information for the specified USBx peripheral.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
-{
-  uint32_t i = 0;
-
-  /*Activate VBUS Sensing B */
-  USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
-
-  if (cfg.vbus_sensing_enable == 0)
-  {
-    /* Deactivate VBUS Sensing B */
-    USBx->GCCFG &= ~ USB_OTG_GCCFG_VBDEN;
-
-    /* B-peripheral session valid override enable*/
-    USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
-    USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
-  }
-
-  /* Restart the Phy Clock */
-  USBx_PCGCCTL = 0;
-
-  /* Device mode configuration */
-  USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80;
-
-  if(cfg.phy_itface  == USB_OTG_ULPI_PHY)
-  {
-    if(cfg.speed == USB_OTG_SPEED_HIGH)
-    {
-      /* Set High speed phy */
-      USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH);
-    }
-    else
-    {
-      /* set High speed phy in Full speed mode */
-      USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH_IN_FULL);
-    }
-  }
-  else
-  {
-    /* Set Full speed phy */
-    USB_SetDevSpeed (USBx , USB_OTG_SPEED_FULL);
-  }
-
-  /* Flush the FIFOs */
-  USB_FlushTxFifo(USBx , 0x10); /* all Tx FIFOs */
-  USB_FlushRxFifo(USBx);
-
-  /* Clear all pending Device Interrupts */
-  USBx_DEVICE->DIEPMSK = 0;
-  USBx_DEVICE->DOEPMSK = 0;
-  USBx_DEVICE->DAINT = 0xFFFFFFFF;
-  USBx_DEVICE->DAINTMSK = 0;
-
-  for (i = 0; i < cfg.dev_endpoints; i++)
-  {
-    if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
-    {
-      USBx_INEP(i)->DIEPCTL = (USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK);
-    }
-    else
-    {
-      USBx_INEP(i)->DIEPCTL = 0;
-    }
-
-    USBx_INEP(i)->DIEPTSIZ = 0;
-    USBx_INEP(i)->DIEPINT  = 0xFF;
-  }
-
-  for (i = 0; i < cfg.dev_endpoints; i++)
-  {
-    if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
-    {
-      USBx_OUTEP(i)->DOEPCTL = (USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK);
-    }
-    else
-    {
-      USBx_OUTEP(i)->DOEPCTL = 0;
-    }
-
-    USBx_OUTEP(i)->DOEPTSIZ = 0;
-    USBx_OUTEP(i)->DOEPINT  = 0xFF;
-  }
-
-  USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
-
-  if (cfg.dma_enable == 1)
-  {
-    /*Set threshold parameters */
-    USBx_DEVICE->DTHRCTL = (USB_OTG_DTHRCTL_TXTHRLEN_6 | USB_OTG_DTHRCTL_RXTHRLEN_6);
-    USBx_DEVICE->DTHRCTL |= (USB_OTG_DTHRCTL_RXTHREN | USB_OTG_DTHRCTL_ISOTHREN | USB_OTG_DTHRCTL_NONISOTHREN);
-
-    i= USBx_DEVICE->DTHRCTL;
-  }
-
-  /* Disable all interrupts. */
-  USBx->GINTMSK = 0;
-
-  /* Clear any pending interrupts */
-  USBx->GINTSTS = 0xBFFFFFFF;
-
-  /* Enable the common interrupts */
-  if (cfg.dma_enable == DISABLE)
-  {
-    USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
-  }
-
-  /* Enable interrupts matching to the Device mode ONLY */
-  USBx->GINTMSK |= (USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |\
-                    USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |\
-                    USB_OTG_GINTMSK_OEPINT   | USB_OTG_GINTMSK_IISOIXFRM|\
-                    USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM);
-
-  if(cfg.Sof_enable)
-  {
-    USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
-  }
-
-  if (cfg.vbus_sensing_enable == ENABLE)
-  {
-    USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);
-  }
-
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  USB_OTG_FlushTxFifo : Flush a Tx FIFO
-  * @param  USBx : Selected device
-  * @param  num : FIFO number
-  *         This parameter can be a value from 1 to 15
-            15 means Flush all Tx FIFOs
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num )
-{
-  uint32_t count = 0;
-
-  USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)( num << 6));
-
-  do
-  {
-    if (++count > 200000)
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
-
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  USB_FlushRxFifo : Flush Rx FIFO
-  * @param  USBx : Selected device
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
-{
-  uint32_t count = 0;
-
-  USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
-
-  do
-  {
-    if (++count > 200000)
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_SetDevSpeed :Initializes the DevSpd field of DCFG register
-  *         depending the PHY type and the enumeration speed of the device.
-  * @param  USBx : Selected device
-  * @param  speed : device speed
-  *          This parameter can be one of these values:
-  *            @arg USB_OTG_SPEED_HIGH: High speed mode
-  *            @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode
-  *            @arg USB_OTG_SPEED_FULL: Full speed mode
-  *            @arg USB_OTG_SPEED_LOW: Low speed mode
-  * @retval  Hal status
-  */
-HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed)
-{
-  USBx_DEVICE->DCFG |= speed;
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_GetDevSpeed :Return the  Dev Speed
-  * @param  USBx : Selected device
-  * @retval speed : device speed
-  *          This parameter can be one of these values:
-  *            @arg USB_OTG_SPEED_HIGH: High speed mode
-  *            @arg USB_OTG_SPEED_FULL: Full speed mode
-  *            @arg USB_OTG_SPEED_LOW: Low speed mode
-  */
-uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
-{
-  uint8_t speed = 0;
-
-  if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)
-  {
-    speed = USB_OTG_SPEED_HIGH;
-  }
-  else if (((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ)||
-           ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_48MHZ))
-  {
-    speed = USB_OTG_SPEED_FULL;
-  }
-  else if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
-  {
-    speed = USB_OTG_SPEED_LOW;
-  }
-
-  return speed;
-}
-
-/**
-  * @brief  Activate and configure an endpoint
-  * @param  USBx : Selected device
-  * @param  ep: pointer to endpoint structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
-{
-  if (ep->is_in == 1)
-  {
-   USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)));
-
-    if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0)
-    {
-      USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\
-        ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP));
-    }
-
-  }
-  else
-  {
-     USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16);
-
-    if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0)
-    {
-      USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\
-       (USB_OTG_DIEPCTL_SD0PID_SEVNFRM)| (USB_OTG_DOEPCTL_USBAEP));
-    }
-  }
-  return HAL_OK;
-}
-/**
-  * @brief  Activate and configure a dedicated endpoint
-  * @param  USBx : Selected device
-  * @param  ep: pointer to endpoint structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
-{
-  static __IO uint32_t debug = 0;
-
-  /* Read DEPCTLn register */
-  if (ep->is_in == 1)
-  {
-    if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0)
-    {
-      USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\
-        ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP));
-    }
-
-
-    debug  |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\
-        ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP));
-
-   USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)));
-  }
-  else
-  {
-    if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0)
-    {
-      USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\
-        ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP));
-
-      debug = (uint32_t)(((uint32_t )USBx) + USB_OTG_OUT_ENDPOINT_BASE + (0)*USB_OTG_EP_REG_SIZE);
-      debug = (uint32_t )&USBx_OUTEP(ep->num)->DOEPCTL;
-      debug |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\
-        ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP));
-    }
-
-     USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16);
-  }
-
-  return HAL_OK;
-}
-/**
-  * @brief  De-activate and de-initialize an endpoint
-  * @param  USBx : Selected device
-  * @param  ep: pointer to endpoint structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
-{
-  /* Read DEPCTLn register */
-  if (ep->is_in == 1)
-  {
-   USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));
-   USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));
-   USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
-  }
-  else
-  {
-     USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
-     USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
-     USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  De-activate and de-initialize a dedicated endpoint
-  * @param  USBx : Selected device
-  * @param  ep: pointer to endpoint structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
-{
-  /* Read DEPCTLn register */
-  if (ep->is_in == 1)
-  {
-   USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
-   USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));
-  }
-  else
-  {
-     USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
-     USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_EPStartXfer : setup and starts a transfer over an EP
-  * @param  USBx : Selected device
-  * @param  ep: pointer to endpoint structure
-  * @param  dma: USB dma enabled or disabled
-  *          This parameter can be one of these values:
-  *           0 : DMA feature not used
-  *           1 : DMA feature used
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma)
-{
-  uint16_t pktcnt = 0;
-
-  /* IN endpoint */
-  if (ep->is_in == 1)
-  {
-    /* Zero Length Packet? */
-    if (ep->xfer_len == 0)
-    {
-      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
-      USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;
-      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
-    }
-    else
-    {
-      /* Program the transfer size and packet count
-      * as follows: xfersize = N * maxpacket +
-      * short_packet pktcnt = N + (short_packet
-      * exist ? 1 : 0)
-      */
-      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
-      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
-      USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket) << 19)) ;
-      USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
-
-      if (ep->type == EP_TYPE_ISOC)
-      {
-        USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);
-        USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1 << 29));
-      }
-    }
-
-    if (dma == 1)
-    {
-      USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr);
-    }
-    else
-    {
-      if (ep->type != EP_TYPE_ISOC)
-      {
-        /* Enable the Tx FIFO Empty Interrupt for this EP */
-        if (ep->xfer_len > 0)
-        {
-          USBx_DEVICE->DIEPEMPMSK |= 1 << ep->num;
-        }
-      }
-    }
-
-    if (ep->type == EP_TYPE_ISOC)
-    {
-      if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0)
-      {
-        USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
-      }
-      else
-      {
-        USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
-      }
-    }
-
-    /* EP enable, IN data in FIFO */
-    USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
-
-    if (ep->type == EP_TYPE_ISOC)
-    {
-      USB_WritePacket(USBx, ep->xfer_buff, ep->num, ep->xfer_len, dma);
-    }
-  }
-  else /* OUT endpoint */
-  {
-    /* Program the transfer size and packet count as follows:
-    * pktcnt = N
-    * xfersize = N * maxpacket
-    */
-    USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
-    USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
-
-    if (ep->xfer_len == 0)
-    {
-      USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);
-      USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ;
-    }
-    else
-    {
-      pktcnt = (ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket;
-      USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (pktcnt << 19));
-      USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt));
-    }
-
-    if (dma == 1)
-    {
-      USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)ep->xfer_buff;
-    }
-
-    if (ep->type == EP_TYPE_ISOC)
-    {
-      if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0)
-      {
-        USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;
-      }
-      else
-      {
-        USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
-      }
-    }
-    /* EP enable */
-    USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_EP0StartXfer : setup and starts a transfer over the EP  0
-  * @param  USBx : Selected device
-  * @param  ep: pointer to endpoint structure
-  * @param  dma: USB dma enabled or disabled
-  *          This parameter can be one of these values:
-  *           0 : DMA feature not used
-  *           1 : DMA feature used
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma)
-{
-  /* IN endpoint */
-  if (ep->is_in == 1)
-  {
-    /* Zero Length Packet? */
-    if (ep->xfer_len == 0)
-    {
-      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
-      USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;
-      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
-    }
-    else
-    {
-      /* Program the transfer size and packet count
-      * as follows: xfersize = N * maxpacket +
-      * short_packet pktcnt = N + (short_packet
-      * exist ? 1 : 0)
-      */
-      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
-      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
-
-      if(ep->xfer_len > ep->maxpacket)
-      {
-        ep->xfer_len = ep->maxpacket;
-      }
-      USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;
-      USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
-
-    }
-
-    /* EP enable, IN data in FIFO */
-    USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
-
-    if (dma == 1)
-    {
-      USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr);
-    }
-    else
-    {
-      /* Enable the Tx FIFO Empty Interrupt for this EP */
-      if (ep->xfer_len > 0U)
-      {
-        USBx_DEVICE->DIEPEMPMSK |= 1U << (ep->num);
-      }
-    }
-  }
-  else /* OUT endpoint */
-  {
-    /* Program the transfer size and packet count as follows:
-    * pktcnt = N
-    * xfersize = N * maxpacket
-    */
-    USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
-    USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
-
-    if (ep->xfer_len > 0)
-    {
-      ep->xfer_len = ep->maxpacket;
-    }
-
-    USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19));
-    USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket));
-
-
-    if (dma == 1)
-    {
-      USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)(ep->xfer_buff);
-    }
-
-    /* EP enable */
-    USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_WritePacket : Writes a packet into the Tx FIFO associated
-  *         with the EP/channel
-  * @param  USBx : Selected device
-  * @param  src :  pointer to source buffer
-  * @param  ch_ep_num : endpoint or host channel number
-  * @param  len : Number of bytes to write
-  * @param  dma: USB dma enabled or disabled
-  *          This parameter can be one of these values:
-  *           0 : DMA feature not used
-  *           1 : DMA feature used
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma)
-{
-  uint32_t count32b= 0 , i= 0;
-
-  if (dma == 0)
-  {
-    count32b =  (len + 3) / 4;
-    for (i = 0; i < count32b; i++, src += 4)
-    {
-      USBx_DFIFO(ch_ep_num) = *((__packed uint32_t *)src);
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_ReadPacket : read a packet from the Tx FIFO associated
-  *         with the EP/channel
-  * @param  USBx : Selected device
-  * @param  src : source pointer
-  * @param  ch_ep_num : endpoint or host channel number
-  * @param  len : Number of bytes to read
-  * @param  dma: USB dma enabled or disabled
-  *          This parameter can be one of these values:
-  *           0 : DMA feature not used
-  *           1 : DMA feature used
-  * @retval pointer to destination buffer
-  */
-void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
-{
-  uint32_t i=0;
-  uint32_t count32b = (len + 3) / 4;
-
-  for ( i = 0; i < count32b; i++, dest += 4 )
-  {
-    *(__packed uint32_t *)dest = USBx_DFIFO(0);
-
-  }
-  return ((void *)dest);
-}
-
-/**
-  * @brief  USB_EPSetStall : set a stall condition over an EP
-  * @param  USBx : Selected device
-  * @param  ep: pointer to endpoint structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep)
-{
-  if (ep->is_in == 1)
-  {
-    if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == 0)
-    {
-      USBx_INEP(ep->num)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS);
-    }
-    USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;
-  }
-  else
-  {
-    if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == 0)
-    {
-      USBx_OUTEP(ep->num)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS);
-    }
-    USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;
-  }
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  USB_EPClearStall : Clear a stall condition over an EP
-  * @param  USBx : Selected device
-  * @param  ep: pointer to endpoint structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
-{
-  if (ep->is_in == 1)
-  {
-    USBx_INEP(ep->num)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
-    if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)
-    {
-       USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */
-    }
-  }
-  else
-  {
-    USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
-    if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)
-    {
-      USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_StopDevice : Stop the usb device mode
-  * @param  USBx : Selected device
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)
-{
-  uint32_t i;
-
-  /* Clear Pending interrupt */
-  for (i = 0; i < 15 ; i++)
-  {
-    USBx_INEP(i)->DIEPINT  = 0xFF;
-    USBx_OUTEP(i)->DOEPINT  = 0xFF;
-  }
-  USBx_DEVICE->DAINT = 0xFFFFFFFF;
-
-  /* Clear interrupt masks */
-  USBx_DEVICE->DIEPMSK  = 0;
-  USBx_DEVICE->DOEPMSK  = 0;
-  USBx_DEVICE->DAINTMSK = 0;
-
-  /* Flush the FIFO */
-  USB_FlushRxFifo(USBx);
-  USB_FlushTxFifo(USBx ,  0x10 );
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_SetDevAddress : Stop the usb device mode
-  * @param  USBx : Selected device
-  * @param  address : new device address to be assigned
-  *          This parameter can be a value from 0 to 255
-  * @retval HAL status
-  */
-HAL_StatusTypeDef  USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address)
-{
-  USBx_DEVICE->DCFG &= ~ (USB_OTG_DCFG_DAD);
-  USBx_DEVICE->DCFG |= (address << 4) & USB_OTG_DCFG_DAD ;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down
-  * @param  USBx : Selected device
-  * @retval HAL status
-  */
-HAL_StatusTypeDef  USB_DevConnect (USB_OTG_GlobalTypeDef *USBx)
-{
-  USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS ;
-  HAL_Delay(3);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down
-  * @param  USBx : Selected device
-  * @retval HAL status
-  */
-HAL_StatusTypeDef  USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx)
-{
-  USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS ;
-  HAL_Delay(3);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_ReadInterrupts: return the global USB interrupt status
-  * @param  USBx : Selected device
-  * @retval HAL status
-  */
-uint32_t  USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx)
-{
-  uint32_t v = 0;
-
-  v = USBx->GINTSTS;
-  v &= USBx->GINTMSK;
-  return v;
-}
-
-/**
-  * @brief  USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
-  * @param  USBx : Selected device
-  * @retval HAL status
-  */
-uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
-{
-  uint32_t v;
-  v  = USBx_DEVICE->DAINT;
-  v &= USBx_DEVICE->DAINTMSK;
-  return ((v & 0xffff0000) >> 16);
-}
-
-/**
-  * @brief  USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
-  * @param  USBx : Selected device
-  * @retval HAL status
-  */
-uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
-{
-  uint32_t v;
-  v  = USBx_DEVICE->DAINT;
-  v &= USBx_DEVICE->DAINTMSK;
-  return ((v & 0xFFFF));
-}
-
-/**
-  * @brief  Returns Device OUT EP Interrupt register
-  * @param  USBx : Selected device
-  * @param  epnum : endpoint number
-  *          This parameter can be a value from 0 to 15
-  * @retval Device OUT EP Interrupt register
-  */
-uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)
-{
-  uint32_t v;
-  v  = USBx_OUTEP(epnum)->DOEPINT;
-  v &= USBx_DEVICE->DOEPMSK;
-  return v;
-}
-
-/**
-  * @brief  Returns Device IN EP Interrupt register
-  * @param  USBx : Selected device
-  * @param  epnum : endpoint number
-  *          This parameter can be a value from 0 to 15
-  * @retval Device IN EP Interrupt register
-  */
-uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)
-{
-  uint32_t v, msk, emp;
-
-  msk = USBx_DEVICE->DIEPMSK;
-  emp = USBx_DEVICE->DIEPEMPMSK;
-  msk |= ((emp >> epnum) & 0x1) << 7;
-  v = USBx_INEP(epnum)->DIEPINT & msk;
-  return v;
-}
-
-/**
-  * @brief  USB_ClearInterrupts: clear a USB interrupt
-  * @param  USBx : Selected device
-  * @param  interrupt : interrupt flag
-  * @retval None
-  */
-void  USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
-{
-  USBx->GINTSTS |= interrupt;
-}
-
-/**
-  * @brief  Returns USB core mode
-  * @param  USBx : Selected device
-  * @retval return core mode : Host or Device
-  *          This parameter can be one of these values:
-  *           0 : Host
-  *           1 : Device
-  */
-uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)
-{
-  return ((USBx->GINTSTS ) & 0x1);
-}
-
-
-/**
-  * @brief  Activate EP0 for Setup transactions
-  * @param  USBx : Selected device
-  * @retval HAL status
-  */
-HAL_StatusTypeDef  USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx)
-{
-  /* Set the MPS of the IN EP based on the enumeration speed */
-  USBx_INEP(0)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
-
-  if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
-  {
-    USBx_INEP(0)->DIEPCTL |= 3;
-  }
-  USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;
-
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  Prepare the EP0 to start the first control setup
-  * @param  USBx : Selected device
-  * @param  dma: USB dma enabled or disabled
-  *          This parameter can be one of these values:
-  *           0 : DMA feature not used
-  *           1 : DMA feature used
-  * @param  psetup : pointer to setup packet
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup)
-{
-  USBx_OUTEP(0)->DOEPTSIZ = 0;
-  USBx_OUTEP(0)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ;
-  USBx_OUTEP(0)->DOEPTSIZ |= (3 * 8);
-  USBx_OUTEP(0)->DOEPTSIZ |=  USB_OTG_DOEPTSIZ_STUPCNT;
-
-  if (dma == 1)
-  {
-    USBx_OUTEP(0)->DOEPDMA = (uint32_t)psetup;
-    /* EP enable */
-    USBx_OUTEP(0)->DOEPCTL = 0x80008000;
-  }
-
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  Reset the USB Core (needed after USB clock settings change)
-  * @param  USBx : Selected device
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
-{
-  uint32_t count = 0;
-
-  /* Wait for AHB master IDLE state. */
-  do
-  {
-    if (++count > 200000)
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0);
-
-  /* Core Soft Reset */
-  count = 0;
-  USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
-
-  do
-  {
-    if (++count > 200000)
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
-
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  USB_HostInit : Initializes the USB OTG controller registers
-  *         for Host mode
-  * @param  USBx : Selected device
-  * @param  cfg  : pointer to a USB_OTG_CfgTypeDef structure that contains
-  *         the configuration information for the specified USBx peripheral.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
-{
-  uint32_t i;
-
-  /* Restart the Phy Clock */
-  USBx_PCGCCTL = 0;
-
-  /*Activate VBUS Sensing B */
-  USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
-
-  /* Disable the FS/LS support mode only */
-  if((cfg.speed == USB_OTG_SPEED_FULL)&&
-     (USBx != USB_OTG_FS))
-  {
-    USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS;
-  }
-  else
-  {
-    USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);
-  }
-
-  /* Make sure the FIFOs are flushed. */
-  USB_FlushTxFifo(USBx, 0x10 ); /* all Tx FIFOs */
-  USB_FlushRxFifo(USBx);
-
-  /* Clear all pending HC Interrupts */
-  for (i = 0; i < cfg.Host_channels; i++)
-  {
-    USBx_HC(i)->HCINT = 0xFFFFFFFF;
-    USBx_HC(i)->HCINTMSK = 0;
-  }
-
-  /* Enable VBUS driving */
-  USB_DriveVbus(USBx, 1);
-
-  HAL_Delay(200);
-
-  /* Disable all interrupts. */
-  USBx->GINTMSK = 0;
-
-  /* Clear any pending interrupts */
-  USBx->GINTSTS = 0xFFFFFFFF;
-
-  if(USBx == USB_OTG_FS)
-  {
-    /* set Rx FIFO size */
-    USBx->GRXFSIZ  = (uint32_t )0x80;
-    USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x60 << 16)& USB_OTG_NPTXFD) | 0x80);
-    USBx->HPTXFSIZ = (uint32_t )(((0x40 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0);
-  }
-  else
-  {
-    /* set Rx FIFO size */
-    USBx->GRXFSIZ  = (uint32_t )0x200;
-    USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x100 << 16)& USB_OTG_NPTXFD) | 0x200);
-    USBx->HPTXFSIZ = (uint32_t )(((0xE0 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0x300);
-  }
-
-  /* Enable the common interrupts */
-  if (cfg.dma_enable == DISABLE)
-  {
-    USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
-  }
-
-  /* Enable interrupts matching to the Host mode ONLY */
-  USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM            | USB_OTG_GINTMSK_HCIM |\
-                    USB_OTG_GINTMSK_SOFM             |USB_OTG_GINTSTS_DISCINT|\
-                    USB_OTG_GINTMSK_PXFRM_IISOOXFRM  | USB_OTG_GINTMSK_WUIM);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the
-  *         HCFG register on the PHY type and set the right frame interval
-  * @param  USBx : Selected device
-  * @param  freq : clock frequency
-  *          This parameter can be one of these values:
-  *           HCFG_48_MHZ : Full Speed 48 MHz Clock
-  *           HCFG_6_MHZ : Low Speed 6 MHz Clock
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq)
-{
-  USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS);
-  USBx_HOST->HCFG |= (freq & USB_OTG_HCFG_FSLSPCS);
-
-  if (freq ==  HCFG_48_MHZ)
-  {
-    USBx_HOST->HFIR = (uint32_t)48000;
-  }
-  else if (freq ==  HCFG_6_MHZ)
-  {
-    USBx_HOST->HFIR = (uint32_t)6000;
-  }
-  return HAL_OK;
-}
-
-/**
-* @brief  USB_OTG_ResetPort : Reset Host Port
-  * @param  USBx : Selected device
-  * @retval HAL status
-  * @note : (1)The application must wait at least 10 ms
-  *   before clearing the reset bit.
-  */
-HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
-{
-  __IO uint32_t hprt0;
-
-  hprt0 = USBx_HPRT0;
-  hprt0 |= USB_OTG_HPRT_PENA ;
-
-  hprt0 &= ~(USB_OTG_HPRT_PCDET | USB_OTG_HPRT_PENCHNG |\
-             USB_OTG_HPRT_POCCHNG );
-
-  USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0);
-  HAL_Delay (10);                                /* See Note #1 */
-  USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0);
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_DriveVbus : activate or de-activate vbus
-  * @param  state : VBUS state
-  *          This parameter can be one of these values:
-  *           0 : VBUS Active
-  *           1 : VBUS Inactive
-  * @retval HAL status
-*/
-HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state)
-{
-  __IO uint32_t hprt0;
-
-  hprt0 = USBx_HPRT0;
-  hprt0 |= USB_OTG_HPRT_PENA ;
-
-  hprt0 &= ~(USB_OTG_HPRT_PCDET | USB_OTG_HPRT_PENCHNG |\
-             USB_OTG_HPRT_POCCHNG );
-
-  if (((hprt0 & USB_OTG_HPRT_PPWR) == 0 ) && (state == 1 ))
-  {
-    USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0);
-  }
-  if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0 ))
-  {
-    USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0);
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Return Host Core speed
-  * @param  USBx : Selected device
-  * @retval speed : Host speed
-  *          This parameter can be one of these values:
-  *            @arg USB_OTG_SPEED_HIGH: High speed mode
-  *            @arg USB_OTG_SPEED_FULL: Full speed mode
-  *            @arg USB_OTG_SPEED_LOW: Low speed mode
-  */
-uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx)
-{
-  __IO uint32_t hprt0;
-
-  hprt0 = USBx_HPRT0;
-  return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17);
-}
-
-/**
-  * @brief  Return Host Current Frame number
-  * @param  USBx : Selected device
-  * @retval current frame number
-*/
-uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx)
-{
-  return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM);
-}
-
-/**
-  * @brief  Initialize a host channel
-  * @param  USBx : Selected device
-  * @param  ch_num : Channel number
-  *         This parameter can be a value from 1 to 15
-  * @param  epnum : Endpoint number
-  *          This parameter can be a value from 1 to 15
-  * @param  dev_address : Current device address
-  *          This parameter can be a value from 0 to 255
-  * @param  speed : Current device speed
-  *          This parameter can be one of these values:
-  *            @arg USB_OTG_SPEED_HIGH: High speed mode
-  *            @arg USB_OTG_SPEED_FULL: Full speed mode
-  *            @arg USB_OTG_SPEED_LOW: Low speed mode
-  * @param  ep_type : Endpoint Type
-  *          This parameter can be one of these values:
-  *            @arg EP_TYPE_CTRL: Control type
-  *            @arg EP_TYPE_ISOC: Isochronous type
-  *            @arg EP_TYPE_BULK: Bulk type
-  *            @arg EP_TYPE_INTR: Interrupt type
-  * @param  mps : Max Packet Size
-  *          This parameter can be a value from 0 to32K
-  * @retval HAL state
-  */
-HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
-                              uint8_t ch_num,
-                              uint8_t epnum,
-                              uint8_t dev_address,
-                              uint8_t speed,
-                              uint8_t ep_type,
-                              uint16_t mps)
-{
-
-  /* Clear old interrupt conditions for this host channel. */
-  USBx_HC(ch_num)->HCINT = 0xFFFFFFFF;
-
-  /* Enable channel interrupts required for this transfer. */
-  switch (ep_type)
-  {
-  case EP_TYPE_CTRL:
-  case EP_TYPE_BULK:
-
-    USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |\
-                                USB_OTG_HCINTMSK_STALLM |\
-                                USB_OTG_HCINTMSK_TXERRM |\
-                                USB_OTG_HCINTMSK_DTERRM |\
-                                USB_OTG_HCINTMSK_AHBERR |\
-                                USB_OTG_HCINTMSK_NAKM ;
-
-    if (epnum & 0x80)
-    {
-      USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
-    }
-    else
-    {
-      if(USBx != USB_OTG_FS)
-      {
-        USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
-      }
-    }
-    break;
-
-  case EP_TYPE_INTR:
-
-    USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |\
-                                USB_OTG_HCINTMSK_STALLM |\
-                                USB_OTG_HCINTMSK_TXERRM |\
-                                USB_OTG_HCINTMSK_DTERRM |\
-                                USB_OTG_HCINTMSK_NAKM   |\
-                                USB_OTG_HCINTMSK_AHBERR |\
-                                USB_OTG_HCINTMSK_FRMORM ;
-
-    if (epnum & 0x80)
-    {
-      USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
-    }
-
-    break;
-  case EP_TYPE_ISOC:
-
-    USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |\
-                                USB_OTG_HCINTMSK_ACKM   |\
-                                USB_OTG_HCINTMSK_AHBERR |\
-                                USB_OTG_HCINTMSK_FRMORM ;
-
-    if (epnum & 0x80)
-    {
-      USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM);
-    }
-    break;
-  }
-
-  /* Enable the top level host channel interrupt. */
-  USBx_HOST->HAINTMSK |= (1 << ch_num);
-
-  /* Make sure host channel interrupts are enabled. */
-  USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM;
-
-  /* Program the HCCHAR register */
-  USBx_HC(ch_num)->HCCHAR = (((dev_address << 22) & USB_OTG_HCCHAR_DAD)  |\
-                             (((epnum & 0x7F)<< 11) & USB_OTG_HCCHAR_EPNUM)|\
-                             ((((epnum & 0x80) == 0x80)<< 15) & USB_OTG_HCCHAR_EPDIR)|\
-                             (((speed == HPRT0_PRTSPD_LOW_SPEED)<< 17) & USB_OTG_HCCHAR_LSDEV)|\
-                             ((ep_type << 18) & USB_OTG_HCCHAR_EPTYP)|\
-                             (mps & USB_OTG_HCCHAR_MPSIZ));
-
-  if (ep_type == EP_TYPE_INTR)
-  {
-    USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ;
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Start a transfer over a host channel
-  * @param  USBx : Selected device
-  * @param  hc : pointer to host channel structure
-  * @param  dma: USB dma enabled or disabled
-  *          This parameter can be one of these values:
-  *           0 : DMA feature not used
-  *           1 : DMA feature used
-  * @retval HAL state
-  */
-#if defined   (__CC_ARM) /*!< ARM Compiler */
-#pragma O0
-#elif defined (__GNUC__) /*!< GNU Compiler */
-#pragma GCC optimize ("O0")
-#endif /* __CC_ARM */
-HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma)
-{
-  uint8_t  is_oddframe = 0;
-  uint16_t len_words = 0;
-  uint16_t num_packets = 0;
-  uint16_t max_hc_pkt_count = 256;
-  uint32_t tmpreg = 0;
-
-  if((USBx != USB_OTG_FS) && (hc->speed == USB_OTG_SPEED_HIGH))
-  {
-    if((dma == 0) && (hc->do_ping == 1))
-    {
-      USB_DoPing(USBx, hc->ch_num);
-      return HAL_OK;
-    }
-    else if(dma == 1)
-    {
-      USBx_HC(hc->ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
-      hc->do_ping = 0;
-    }
-  }
-
-  /* Compute the expected number of packets associated to the transfer */
-  if (hc->xfer_len > 0)
-  {
-    num_packets = (hc->xfer_len + hc->max_packet - 1) / hc->max_packet;
-
-    if (num_packets > max_hc_pkt_count)
-    {
-      num_packets = max_hc_pkt_count;
-      hc->xfer_len = num_packets * hc->max_packet;
-    }
-  }
-  else
-  {
-    num_packets = 1;
-  }
-  if (hc->ep_is_in)
-  {
-    hc->xfer_len = num_packets * hc->max_packet;
-  }
-
-  /* Initialize the HCTSIZn register */
-  USBx_HC(hc->ch_num)->HCTSIZ = (((hc->xfer_len) & USB_OTG_HCTSIZ_XFRSIZ)) |\
-    ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\
-      (((hc->data_pid) << 29) & USB_OTG_HCTSIZ_DPID);
-
-  if (dma)
-  {
-    /* xfer_buff MUST be 32-bits aligned */
-    USBx_HC(hc->ch_num)->HCDMA = (uint32_t)hc->xfer_buff;
-  }
-
-  is_oddframe = (USBx_HOST->HFNUM & 0x01) ? 0 : 1;
-  USBx_HC(hc->ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;
-  USBx_HC(hc->ch_num)->HCCHAR |= (is_oddframe << 29);
-
-  /* Set host channel enable */
-  tmpreg = USBx_HC(hc->ch_num)->HCCHAR;
-  tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
-  tmpreg |= USB_OTG_HCCHAR_CHENA;
-  USBx_HC(hc->ch_num)->HCCHAR = tmpreg;
-
-  if (dma == 0) /* Slave mode */
-  {
-    if((hc->ep_is_in == 0) && (hc->xfer_len > 0))
-    {
-      switch(hc->ep_type)
-      {
-        /* Non periodic transfer */
-      case EP_TYPE_CTRL:
-      case EP_TYPE_BULK:
-
-        len_words = (hc->xfer_len + 3) / 4;
-
-        /* check if there is enough space in FIFO space */
-        if(len_words > (USBx->HNPTXSTS & 0xFFFF))
-        {
-          /* need to process data in nptxfempty interrupt */
-          USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM;
-        }
-        break;
-        /* Periodic transfer */
-      case EP_TYPE_INTR:
-      case EP_TYPE_ISOC:
-        len_words = (hc->xfer_len + 3) / 4;
-        /* check if there is enough space in FIFO space */
-        if(len_words > (USBx_HOST->HPTXSTS & 0xFFFF)) /* split the transfer */
-        {
-          /* need to process data in ptxfempty interrupt */
-          USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM;
-        }
-        break;
-
-      default:
-        break;
-      }
-
-      /* Write packet into the Tx FIFO. */
-      USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, hc->xfer_len, 0);
-    }
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Read all host channel interrupts status
-  * @param  USBx : Selected device
-  * @retval HAL state
-  */
-uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx)
-{
-  return ((USBx_HOST->HAINT) & 0xFFFF);
-}
-
-/**
-  * @brief  Halt a host channel
-  * @param  USBx : Selected device
-  * @param  hc_num : Host Channel number
-  *         This parameter can be a value from 1 to 15
-  * @retval HAL state
-  */
-HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num)
-{
-  uint32_t count = 0;
-
-  /* Check for space in the request queue to issue the halt. */
-  if (((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_CTRL << 18)) || ((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_BULK << 18)))
-  {
-    USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
-
-    if ((USBx->HNPTXSTS & 0xFFFF) == 0)
-    {
-      USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
-      USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
-      USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
-      do
-      {
-        if (++count > 1000)
-        {
-          break;
-        }
-      }
-      while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
-    }
-    else
-    {
-      USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
-    }
-  }
-  else
-  {
-    USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
-
-    if ((USBx_HOST->HPTXSTS & 0xFFFF) == 0)
-    {
-      USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
-      USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
-      USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
-      do
-      {
-        if (++count > 1000)
-        {
-          break;
-        }
-      }
-      while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
-    }
-    else
-    {
-       USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
-    }
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initiate Do Ping protocol
-  * @param  USBx : Selected device
-  * @param  hc_num : Host Channel number
-  *         This parameter can be a value from 1 to 15
-  * @retval HAL state
-  */
-HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num)
-{
-  uint8_t  num_packets = 1;
-  uint32_t tmpreg = 0;
-
-  USBx_HC(ch_num)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\
-                                USB_OTG_HCTSIZ_DOPING;
-
-  /* Set host channel enable */
-  tmpreg = USBx_HC(ch_num)->HCCHAR;
-  tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
-  tmpreg |= USB_OTG_HCCHAR_CHENA;
-  USBx_HC(ch_num)->HCCHAR = tmpreg;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stop Host Core
-  * @param  USBx : Selected device
-  * @retval HAL state
-  */
-HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
-{
-  uint8_t i;
-  uint32_t count = 0;
-  uint32_t value;
-
-  USB_DisableGlobalInt(USBx);
-
-    /* Flush FIFO */
-  USB_FlushTxFifo(USBx, 0x10);
-  USB_FlushRxFifo(USBx);
-
-  /* Flush out any leftover queued requests. */
-  for (i = 0; i <= 15; i++)
-  {
-
-    value = USBx_HC(i)->HCCHAR ;
-    value |=  USB_OTG_HCCHAR_CHDIS;
-    value &= ~USB_OTG_HCCHAR_CHENA;
-    value &= ~USB_OTG_HCCHAR_EPDIR;
-    USBx_HC(i)->HCCHAR = value;
-  }
-
-  /* Halt all channels to put them into a known state. */
-  for (i = 0; i <= 15; i++)
-  {
-    value = USBx_HC(i)->HCCHAR ;
-
-    value |= USB_OTG_HCCHAR_CHDIS;
-    value |= USB_OTG_HCCHAR_CHENA;
-    value &= ~USB_OTG_HCCHAR_EPDIR;
-
-    USBx_HC(i)->HCCHAR = value;
-    do
-    {
-      if (++count > 1000)
-      {
-        break;
-      }
-    }
-    while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
-  }
-
-  /* Clear any pending Host interrupts */
-  USBx_HOST->HAINT = 0xFFFFFFFF;
-  USBx->GINTSTS = 0xFFFFFFFF;
-  USB_EnableGlobalInt(USBx);
-  return HAL_OK;
-}
-/**
-  * @}
-  */
-
-#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/inc/Legacy/stm32_hal_legacy.h b/stmhal/hal/l4/inc/Legacy/stm32_hal_legacy.h
deleted file mode 100644
index ec26698e77..0000000000
--- a/stmhal/hal/l4/inc/Legacy/stm32_hal_legacy.h
+++ /dev/null
@@ -1,2962 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32_hal_legacy.h
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   This file contains aliases definition for the STM32Cube HAL constants 
-  *          macros and functions maintained for legacy purpose.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32_HAL_LEGACY
-#define __STM32_HAL_LEGACY
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define AES_FLAG_RDERR                  CRYP_FLAG_RDERR
-#define AES_FLAG_WRERR                  CRYP_FLAG_WRERR
-#define AES_CLEARFLAG_CCF               CRYP_CLEARFLAG_CCF
-#define AES_CLEARFLAG_RDERR             CRYP_CLEARFLAG_RDERR
-#define AES_CLEARFLAG_WRERR             CRYP_CLEARFLAG_WRERR
-
-/**
-  * @}
-  */
-  
-/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define ADC_RESOLUTION12b               ADC_RESOLUTION_12B
-#define ADC_RESOLUTION10b               ADC_RESOLUTION_10B
-#define ADC_RESOLUTION8b                ADC_RESOLUTION_8B
-#define ADC_RESOLUTION6b                ADC_RESOLUTION_6B
-#define OVR_DATA_OVERWRITTEN            ADC_OVR_DATA_OVERWRITTEN
-#define OVR_DATA_PRESERVED              ADC_OVR_DATA_PRESERVED
-#define EOC_SINGLE_CONV                 ADC_EOC_SINGLE_CONV
-#define EOC_SEQ_CONV                    ADC_EOC_SEQ_CONV
-#define EOC_SINGLE_SEQ_CONV             ADC_EOC_SINGLE_SEQ_CONV
-#define REGULAR_GROUP                   ADC_REGULAR_GROUP
-#define INJECTED_GROUP                  ADC_INJECTED_GROUP
-#define REGULAR_INJECTED_GROUP          ADC_REGULAR_INJECTED_GROUP
-#define AWD_EVENT                       ADC_AWD_EVENT
-#define AWD1_EVENT                      ADC_AWD1_EVENT
-#define AWD2_EVENT                      ADC_AWD2_EVENT
-#define AWD3_EVENT                      ADC_AWD3_EVENT
-#define OVR_EVENT                       ADC_OVR_EVENT
-#define JQOVF_EVENT                     ADC_JQOVF_EVENT
-#define ALL_CHANNELS                    ADC_ALL_CHANNELS
-#define REGULAR_CHANNELS                ADC_REGULAR_CHANNELS
-#define INJECTED_CHANNELS               ADC_INJECTED_CHANNELS
-#define SYSCFG_FLAG_SENSOR_ADC          ADC_FLAG_SENSOR
-#define SYSCFG_FLAG_VREF_ADC            ADC_FLAG_VREFINT
-#define ADC_CLOCKPRESCALER_PCLK_DIV1    ADC_CLOCK_SYNC_PCLK_DIV1
-#define ADC_CLOCKPRESCALER_PCLK_DIV2    ADC_CLOCK_SYNC_PCLK_DIV2
-#define ADC_CLOCKPRESCALER_PCLK_DIV4    ADC_CLOCK_SYNC_PCLK_DIV4
-#define ADC_CLOCKPRESCALER_PCLK_DIV6    ADC_CLOCK_SYNC_PCLK_DIV6
-#define ADC_CLOCKPRESCALER_PCLK_DIV8    ADC_CLOCK_SYNC_PCLK_DIV8
-#define ADC_EXTERNALTRIG0_T6_TRGO       ADC_EXTERNALTRIGCONV_T6_TRGO 
-#define ADC_EXTERNALTRIG1_T21_CC2       ADC_EXTERNALTRIGCONV_T21_CC2 
-#define ADC_EXTERNALTRIG2_T2_TRGO       ADC_EXTERNALTRIGCONV_T2_TRGO 
-#define ADC_EXTERNALTRIG3_T2_CC4        ADC_EXTERNALTRIGCONV_T2_CC4  
-#define ADC_EXTERNALTRIG4_T22_TRGO      ADC_EXTERNALTRIGCONV_T22_TRGO
-#define ADC_EXTERNALTRIG7_EXT_IT11      ADC_EXTERNALTRIGCONV_EXT_IT11
-#define ADC_CLOCK_ASYNC                 ADC_CLOCK_ASYNC_DIV1
-#define ADC_EXTERNALTRIG_EDGE_NONE      ADC_EXTERNALTRIGCONVEDGE_NONE
-#define ADC_EXTERNALTRIG_EDGE_RISING    ADC_EXTERNALTRIGCONVEDGE_RISING
-#define ADC_EXTERNALTRIG_EDGE_FALLING   ADC_EXTERNALTRIGCONVEDGE_FALLING
-#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
-#define ADC_SAMPLETIME_2CYCLE_5         ADC_SAMPLETIME_2CYCLES_5
-
-#define HAL_ADC_STATE_BUSY_REG          HAL_ADC_STATE_REG_BUSY
-#define HAL_ADC_STATE_BUSY_INJ          HAL_ADC_STATE_INJ_BUSY
-#define HAL_ADC_STATE_EOC_REG           HAL_ADC_STATE_REG_EOC
-#define HAL_ADC_STATE_EOC_INJ           HAL_ADC_STATE_INJ_EOC
-#define HAL_ADC_STATE_ERROR             HAL_ADC_STATE_ERROR_INTERNAL
-#define HAL_ADC_STATE_BUSY              HAL_ADC_STATE_BUSY_INTERNAL
-#define HAL_ADC_STATE_AWD               HAL_ADC_STATE_AWD1 
-/**
-  * @}
-  */
-  
-/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
-  * @{
-  */ 
-  
-#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG 
-
-/**
-  * @}
-  */   
-   
-/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
-  * @{
-  */
-  
-#define COMP_WINDOWMODE_DISABLED       COMP_WINDOWMODE_DISABLE
-#define COMP_WINDOWMODE_ENABLED        COMP_WINDOWMODE_ENABLE
-#define COMP_EXTI_LINE_COMP1_EVENT     COMP_EXTI_LINE_COMP1
-#define COMP_EXTI_LINE_COMP2_EVENT     COMP_EXTI_LINE_COMP2
-#define COMP_EXTI_LINE_COMP3_EVENT     COMP_EXTI_LINE_COMP3
-#define COMP_EXTI_LINE_COMP4_EVENT     COMP_EXTI_LINE_COMP4
-#define COMP_EXTI_LINE_COMP5_EVENT     COMP_EXTI_LINE_COMP5
-#define COMP_EXTI_LINE_COMP6_EVENT     COMP_EXTI_LINE_COMP6
-#define COMP_EXTI_LINE_COMP7_EVENT     COMP_EXTI_LINE_COMP7
-#define COMP_OUTPUT_COMP6TIM2OCREFCLR  COMP_OUTPUT_COMP6_TIM2OCREFCLR
-#if defined(STM32F373xC) || defined(STM32F378xx)
-#define COMP_OUTPUT_TIM3IC1            COMP_OUTPUT_COMP1_TIM3IC1
-#define COMP_OUTPUT_TIM3OCREFCLR       COMP_OUTPUT_COMP1_TIM3OCREFCLR
-#endif /* STM32F373xC || STM32F378xx */
-/**
-  * @}
-  */
-
-/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
-/**
-  * @}
-  */
-
-/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-  
-#define CRC_OUTPUTDATA_INVERSION_DISABLED    CRC_OUTPUTDATA_INVERSION_DISABLE
-#define CRC_OUTPUTDATA_INVERSION_ENABLED     CRC_OUTPUTDATA_INVERSION_ENABLE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define DAC1_CHANNEL_1                                  DAC_CHANNEL_1
-#define DAC1_CHANNEL_2                                  DAC_CHANNEL_2
-#define DAC2_CHANNEL_1                                  DAC_CHANNEL_1
-#define DAC_WAVE_NONE                                   ((uint32_t)0x00000000U)
-#define DAC_WAVE_NOISE                                  ((uint32_t)DAC_CR_WAVE1_0)
-#define DAC_WAVE_TRIANGLE                               ((uint32_t)DAC_CR_WAVE1_1)                           
-#define DAC_WAVEGENERATION_NONE                         DAC_WAVE_NONE
-#define DAC_WAVEGENERATION_NOISE                        DAC_WAVE_NOISE
-#define DAC_WAVEGENERATION_TRIANGLE                     DAC_WAVE_TRIANGLE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define HAL_REMAPDMA_ADC_DMA_CH2                DMA_REMAP_ADC_DMA_CH2       
-#define HAL_REMAPDMA_USART1_TX_DMA_CH4          DMA_REMAP_USART1_TX_DMA_CH4 
-#define HAL_REMAPDMA_USART1_RX_DMA_CH5          DMA_REMAP_USART1_RX_DMA_CH5   
-#define HAL_REMAPDMA_TIM16_DMA_CH4              DMA_REMAP_TIM16_DMA_CH4       
-#define HAL_REMAPDMA_TIM17_DMA_CH2              DMA_REMAP_TIM17_DMA_CH2       
-#define HAL_REMAPDMA_USART3_DMA_CH32            DMA_REMAP_USART3_DMA_CH32
-#define HAL_REMAPDMA_TIM16_DMA_CH6              DMA_REMAP_TIM16_DMA_CH6
-#define HAL_REMAPDMA_TIM17_DMA_CH7              DMA_REMAP_TIM17_DMA_CH7      
-#define HAL_REMAPDMA_SPI2_DMA_CH67              DMA_REMAP_SPI2_DMA_CH67  
-#define HAL_REMAPDMA_USART2_DMA_CH67            DMA_REMAP_USART2_DMA_CH67 
-#define HAL_REMAPDMA_USART3_DMA_CH32            DMA_REMAP_USART3_DMA_CH32  
-#define HAL_REMAPDMA_I2C1_DMA_CH76              DMA_REMAP_I2C1_DMA_CH76   
-#define HAL_REMAPDMA_TIM1_DMA_CH6               DMA_REMAP_TIM1_DMA_CH6     
-#define HAL_REMAPDMA_TIM2_DMA_CH7               DMA_REMAP_TIM2_DMA_CH7      
-#define HAL_REMAPDMA_TIM3_DMA_CH6               DMA_REMAP_TIM3_DMA_CH6    
-  
-#define IS_HAL_REMAPDMA                          IS_DMA_REMAP  
-#define __HAL_REMAPDMA_CHANNEL_ENABLE            __HAL_DMA_REMAP_CHANNEL_ENABLE
-#define __HAL_REMAPDMA_CHANNEL_DISABLE           __HAL_DMA_REMAP_CHANNEL_DISABLE
-  
-  
-  
-/**
-  * @}
-  */
-
-/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
-  * @{
-  */
-  
-#define TYPEPROGRAM_BYTE              FLASH_TYPEPROGRAM_BYTE
-#define TYPEPROGRAM_HALFWORD          FLASH_TYPEPROGRAM_HALFWORD
-#define TYPEPROGRAM_WORD              FLASH_TYPEPROGRAM_WORD
-#define TYPEPROGRAM_DOUBLEWORD        FLASH_TYPEPROGRAM_DOUBLEWORD
-#define TYPEERASE_SECTORS             FLASH_TYPEERASE_SECTORS
-#define TYPEERASE_PAGES               FLASH_TYPEERASE_PAGES
-#define TYPEERASE_PAGEERASE           FLASH_TYPEERASE_PAGES
-#define TYPEERASE_MASSERASE           FLASH_TYPEERASE_MASSERASE
-#define WRPSTATE_DISABLE              OB_WRPSTATE_DISABLE
-#define WRPSTATE_ENABLE               OB_WRPSTATE_ENABLE
-#define HAL_FLASH_TIMEOUT_VALUE       FLASH_TIMEOUT_VALUE
-#define OBEX_PCROP                    OPTIONBYTE_PCROP
-#define OBEX_BOOTCONFIG               OPTIONBYTE_BOOTCONFIG
-#define PCROPSTATE_DISABLE            OB_PCROP_STATE_DISABLE
-#define PCROPSTATE_ENABLE             OB_PCROP_STATE_ENABLE
-#define TYPEERASEDATA_BYTE            FLASH_TYPEERASEDATA_BYTE
-#define TYPEERASEDATA_HALFWORD        FLASH_TYPEERASEDATA_HALFWORD
-#define TYPEERASEDATA_WORD            FLASH_TYPEERASEDATA_WORD
-#define TYPEPROGRAMDATA_BYTE          FLASH_TYPEPROGRAMDATA_BYTE
-#define TYPEPROGRAMDATA_HALFWORD      FLASH_TYPEPROGRAMDATA_HALFWORD
-#define TYPEPROGRAMDATA_WORD          FLASH_TYPEPROGRAMDATA_WORD
-#define TYPEPROGRAMDATA_FASTBYTE      FLASH_TYPEPROGRAMDATA_FASTBYTE
-#define TYPEPROGRAMDATA_FASTHALFWORD  FLASH_TYPEPROGRAMDATA_FASTHALFWORD
-#define TYPEPROGRAMDATA_FASTWORD      FLASH_TYPEPROGRAMDATA_FASTWORD
-#define PAGESIZE                      FLASH_PAGE_SIZE
-#define TYPEPROGRAM_FASTBYTE          FLASH_TYPEPROGRAM_BYTE
-#define TYPEPROGRAM_FASTHALFWORD      FLASH_TYPEPROGRAM_HALFWORD
-#define TYPEPROGRAM_FASTWORD          FLASH_TYPEPROGRAM_WORD
-#define VOLTAGE_RANGE_1               FLASH_VOLTAGE_RANGE_1
-#define VOLTAGE_RANGE_2               FLASH_VOLTAGE_RANGE_2
-#define VOLTAGE_RANGE_3               FLASH_VOLTAGE_RANGE_3
-#define VOLTAGE_RANGE_4               FLASH_VOLTAGE_RANGE_4
-#define TYPEPROGRAM_FAST              FLASH_TYPEPROGRAM_FAST
-#define TYPEPROGRAM_FAST_AND_LAST     FLASH_TYPEPROGRAM_FAST_AND_LAST
-#define WRPAREA_BANK1_AREAA           OB_WRPAREA_BANK1_AREAA
-#define WRPAREA_BANK1_AREAB           OB_WRPAREA_BANK1_AREAB
-#define WRPAREA_BANK2_AREAA           OB_WRPAREA_BANK2_AREAA
-#define WRPAREA_BANK2_AREAB           OB_WRPAREA_BANK2_AREAB
-#define IWDG_STDBY_FREEZE             OB_IWDG_STDBY_FREEZE
-#define IWDG_STDBY_ACTIVE             OB_IWDG_STDBY_RUN
-#define IWDG_STOP_FREEZE              OB_IWDG_STOP_FREEZE
-#define IWDG_STOP_ACTIVE              OB_IWDG_STOP_RUN
-#define FLASH_ERROR_NONE              HAL_FLASH_ERROR_NONE
-#define FLASH_ERROR_RD                HAL_FLASH_ERROR_RD
-#define FLASH_ERROR_PG                HAL_FLASH_ERROR_PROG
-#define FLASH_ERROR_PGP               HAL_FLASH_ERROR_PGS
-#define FLASH_ERROR_WRP               HAL_FLASH_ERROR_WRP
-#define FLASH_ERROR_OPTV              HAL_FLASH_ERROR_OPTV
-#define FLASH_ERROR_OPTVUSR           HAL_FLASH_ERROR_OPTVUSR
-#define FLASH_ERROR_PROG              HAL_FLASH_ERROR_PROG
-#define FLASH_ERROR_OP                HAL_FLASH_ERROR_OPERATION
-#define FLASH_ERROR_PGA               HAL_FLASH_ERROR_PGA
-#define FLASH_ERROR_SIZE              HAL_FLASH_ERROR_SIZE
-#define FLASH_ERROR_SIZ               HAL_FLASH_ERROR_SIZE
-#define FLASH_ERROR_PGS               HAL_FLASH_ERROR_PGS
-#define FLASH_ERROR_MIS               HAL_FLASH_ERROR_MIS
-#define FLASH_ERROR_FAST              HAL_FLASH_ERROR_FAST
-#define FLASH_ERROR_FWWERR            HAL_FLASH_ERROR_FWWERR
-#define FLASH_ERROR_NOTZERO           HAL_FLASH_ERROR_NOTZERO
-#define FLASH_ERROR_OPERATION         HAL_FLASH_ERROR_OPERATION
-#define FLASH_ERROR_ERS               HAL_FLASH_ERROR_ERS
-#define OB_WDG_SW                     OB_IWDG_SW
-#define OB_WDG_HW                     OB_IWDG_HW
-#define OB_SDADC12_VDD_MONITOR_SET    OB_SDACD_VDD_MONITOR_SET
-#define OB_SDADC12_VDD_MONITOR_RESET  OB_SDACD_VDD_MONITOR_RESET
-#define OB_RAM_PARITY_CHECK_SET       OB_SRAM_PARITY_SET
-#define OB_RAM_PARITY_CHECK_RESET     OB_SRAM_PARITY_RESET
-#define IS_OB_SDADC12_VDD_MONITOR     IS_OB_SDACD_VDD_MONITOR
-#define OB_RDP_LEVEL0                 OB_RDP_LEVEL_0
-#define OB_RDP_LEVEL1                 OB_RDP_LEVEL_1
-#define OB_RDP_LEVEL2                 OB_RDP_LEVEL_2
-/**
-  * @}
-  */
-  
-/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
-  * @{
-  */
-  
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9    I2C_FASTMODEPLUS_PA9
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10   I2C_FASTMODEPLUS_PA10
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6    I2C_FASTMODEPLUS_PB6
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7    I2C_FASTMODEPLUS_PB7
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8    I2C_FASTMODEPLUS_PB8
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9    I2C_FASTMODEPLUS_PB9
-#define HAL_SYSCFG_FASTMODEPLUS_I2C1       I2C_FASTMODEPLUS_I2C1
-#define HAL_SYSCFG_FASTMODEPLUS_I2C2       I2C_FASTMODEPLUS_I2C2
-#define HAL_SYSCFG_FASTMODEPLUS_I2C3       I2C_FASTMODEPLUS_I2C3
-/**
-  * @}
-  */
-  
-
-/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
-  * @{
-  */
-#if defined(STM32L4) || defined(STM32F7)
-#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE       FMC_NAND_WAIT_FEATURE_DISABLE
-#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE        FMC_NAND_WAIT_FEATURE_ENABLE
-#define FMC_NAND_PCC_MEM_BUS_WIDTH_8            FMC_NAND_MEM_BUS_WIDTH_8
-#define FMC_NAND_PCC_MEM_BUS_WIDTH_16           FMC_NAND_MEM_BUS_WIDTH_16
-#else
-#define FMC_NAND_WAIT_FEATURE_DISABLE           FMC_NAND_PCC_WAIT_FEATURE_DISABLE
-#define FMC_NAND_WAIT_FEATURE_ENABLE            FMC_NAND_PCC_WAIT_FEATURE_ENABLE
-#define FMC_NAND_MEM_BUS_WIDTH_8                FMC_NAND_PCC_MEM_BUS_WIDTH_8
-#define FMC_NAND_MEM_BUS_WIDTH_16               FMC_NAND_PCC_MEM_BUS_WIDTH_16
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-  
-#define FSMC_NORSRAM_TYPEDEF                      FSMC_NORSRAM_TypeDef
-#define FSMC_NORSRAM_EXTENDED_TYPEDEF             FSMC_NORSRAM_EXTENDED_TypeDef
-/**
-  * @}
-  */
-
-/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define GET_GPIO_SOURCE                           GPIO_GET_INDEX
-#define GET_GPIO_INDEX                            GPIO_GET_INDEX
-
-#if defined(STM32F4)
-#define GPIO_AF12_SDMMC                           GPIO_AF12_SDIO
-#define GPIO_AF12_SDMMC1                          GPIO_AF12_SDIO
-#endif
-
-#if defined(STM32F7)
-#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1
-#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
-#endif
-
-#if defined(STM32L4)
-#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1
-#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
-#endif
-
-#define GPIO_AF0_LPTIM                            GPIO_AF0_LPTIM1
-#define GPIO_AF1_LPTIM                            GPIO_AF1_LPTIM1
-#define GPIO_AF2_LPTIM                            GPIO_AF2_LPTIM1
-
-#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7)
-#define  GPIO_SPEED_LOW                           GPIO_SPEED_FREQ_LOW     
-#define  GPIO_SPEED_MEDIUM                        GPIO_SPEED_FREQ_MEDIUM     
-#define  GPIO_SPEED_FAST                          GPIO_SPEED_FREQ_HIGH     
-#define  GPIO_SPEED_HIGH                          GPIO_SPEED_FREQ_VERY_HIGH       
-#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */
-
-#if defined(STM32L1) 
- #define  GPIO_SPEED_VERY_LOW    GPIO_SPEED_FREQ_LOW     
- #define  GPIO_SPEED_LOW         GPIO_SPEED_FREQ_MEDIUM     
- #define  GPIO_SPEED_MEDIUM      GPIO_SPEED_FREQ_HIGH     
- #define  GPIO_SPEED_HIGH        GPIO_SPEED_FREQ_VERY_HIGH     
-#endif /* STM32L1 */
-
-#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
- #define  GPIO_SPEED_LOW    GPIO_SPEED_FREQ_LOW
- #define  GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
- #define  GPIO_SPEED_HIGH   GPIO_SPEED_FREQ_HIGH
-#endif /* STM32F0 || STM32F3 || STM32F1 */
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define HRTIM_TIMDELAYEDPROTECTION_DISABLED           HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
-#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
-   
-#define __HAL_HRTIM_SetCounter        __HAL_HRTIM_SETCOUNTER
-#define __HAL_HRTIM_GetCounter        __HAL_HRTIM_GETCOUNTER
-#define __HAL_HRTIM_SetPeriod         __HAL_HRTIM_SETPERIOD
-#define __HAL_HRTIM_GetPeriod         __HAL_HRTIM_GETPERIOD
-#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
-#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
-#define __HAL_HRTIM_SetCompare        __HAL_HRTIM_SETCOMPARE
-#define __HAL_HRTIM_GetCompare        __HAL_HRTIM_GETCOMPARE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define I2C_DUALADDRESS_DISABLED                I2C_DUALADDRESS_DISABLE
-#define I2C_DUALADDRESS_ENABLED                 I2C_DUALADDRESS_ENABLE
-#define I2C_GENERALCALL_DISABLED                I2C_GENERALCALL_DISABLE
-#define I2C_GENERALCALL_ENABLED                 I2C_GENERALCALL_ENABLE
-#define I2C_NOSTRETCH_DISABLED                  I2C_NOSTRETCH_DISABLE
-#define I2C_NOSTRETCH_ENABLED                   I2C_NOSTRETCH_ENABLE
-#define I2C_ANALOGFILTER_ENABLED                I2C_ANALOGFILTER_ENABLE
-#define I2C_ANALOGFILTER_DISABLED               I2C_ANALOGFILTER_DISABLE
-#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4)
-#define HAL_I2C_STATE_MEM_BUSY_TX               HAL_I2C_STATE_BUSY_TX
-#define HAL_I2C_STATE_MEM_BUSY_RX               HAL_I2C_STATE_BUSY_RX
-#define HAL_I2C_STATE_MASTER_BUSY_TX            HAL_I2C_STATE_BUSY_TX
-#define HAL_I2C_STATE_MASTER_BUSY_RX            HAL_I2C_STATE_BUSY_RX
-#define HAL_I2C_STATE_SLAVE_BUSY_TX             HAL_I2C_STATE_BUSY_TX
-#define HAL_I2C_STATE_SLAVE_BUSY_RX             HAL_I2C_STATE_BUSY_RX
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define IRDA_ONE_BIT_SAMPLE_DISABLED            IRDA_ONE_BIT_SAMPLE_DISABLE
-#define IRDA_ONE_BIT_SAMPLE_ENABLED             IRDA_ONE_BIT_SAMPLE_ENABLE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define KR_KEY_RELOAD                   IWDG_KEY_RELOAD
-#define KR_KEY_ENABLE                   IWDG_KEY_ENABLE
-#define KR_KEY_EWA                      IWDG_KEY_WRITE_ACCESS_ENABLE
-#define KR_KEY_DWA                      IWDG_KEY_WRITE_ACCESS_DISABLE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
-#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
-#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
-#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
-
-#define LPTIM_CLOCKPOLARITY_RISINGEDGE          LPTIM_CLOCKPOLARITY_RISING
-#define LPTIM_CLOCKPOLARITY_FALLINGEDGE         LPTIM_CLOCKPOLARITY_FALLING
-#define LPTIM_CLOCKPOLARITY_BOTHEDGES           LPTIM_CLOCKPOLARITY_RISING_FALLING
-
-#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION  LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
-#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS      LPTIM_TRIGSAMPLETIME_2TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS      LPTIM_TRIGSAMPLETIME_4TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS      LPTIM_TRIGSAMPLETIME_8TRANSITIONS        
-
-/* The following 3 definition have also been present in a temporary version of lptim.h */
-/* They need to be renamed also to the right name, just in case */
-#define LPTIM_TRIGSAMPLETIME_2TRANSITION        LPTIM_TRIGSAMPLETIME_2TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_4TRANSITION        LPTIM_TRIGSAMPLETIME_4TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_8TRANSITION        LPTIM_TRIGSAMPLETIME_8TRANSITIONS
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define NAND_AddressTypedef             NAND_AddressTypeDef
-
-#define __ARRAY_ADDRESS                 ARRAY_ADDRESS
-#define __ADDR_1st_CYCLE                ADDR_1ST_CYCLE
-#define __ADDR_2nd_CYCLE                ADDR_2ND_CYCLE
-#define __ADDR_3rd_CYCLE                ADDR_3RD_CYCLE
-#define __ADDR_4th_CYCLE                ADDR_4TH_CYCLE
-/**
-  * @}
-  */
-   
-/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define NOR_StatusTypedef              HAL_NOR_StatusTypeDef
-#define NOR_SUCCESS                    HAL_NOR_STATUS_SUCCESS
-#define NOR_ONGOING                    HAL_NOR_STATUS_ONGOING
-#define NOR_ERROR                      HAL_NOR_STATUS_ERROR
-#define NOR_TIMEOUT                    HAL_NOR_STATUS_TIMEOUT
-
-#define __NOR_WRITE                    NOR_WRITE
-#define __NOR_ADDR_SHIFT               NOR_ADDR_SHIFT
-/**
-  * @}
-  */
-
-/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define OPAMP_NONINVERTINGINPUT_VP0           OPAMP_NONINVERTINGINPUT_IO0
-#define OPAMP_NONINVERTINGINPUT_VP1           OPAMP_NONINVERTINGINPUT_IO1
-#define OPAMP_NONINVERTINGINPUT_VP2           OPAMP_NONINVERTINGINPUT_IO2
-#define OPAMP_NONINVERTINGINPUT_VP3           OPAMP_NONINVERTINGINPUT_IO3
-                                              
-#define OPAMP_SEC_NONINVERTINGINPUT_VP0       OPAMP_SEC_NONINVERTINGINPUT_IO0
-#define OPAMP_SEC_NONINVERTINGINPUT_VP1       OPAMP_SEC_NONINVERTINGINPUT_IO1
-#define OPAMP_SEC_NONINVERTINGINPUT_VP2       OPAMP_SEC_NONINVERTINGINPUT_IO2
-#define OPAMP_SEC_NONINVERTINGINPUT_VP3       OPAMP_SEC_NONINVERTINGINPUT_IO3   
-
-#define OPAMP_INVERTINGINPUT_VM0              OPAMP_INVERTINGINPUT_IO0
-#define OPAMP_INVERTINGINPUT_VM1              OPAMP_INVERTINGINPUT_IO1
-
-#define IOPAMP_INVERTINGINPUT_VM0             OPAMP_INVERTINGINPUT_IO0
-#define IOPAMP_INVERTINGINPUT_VM1             OPAMP_INVERTINGINPUT_IO1
-
-#define OPAMP_SEC_INVERTINGINPUT_VM0          OPAMP_SEC_INVERTINGINPUT_IO0
-#define OPAMP_SEC_INVERTINGINPUT_VM1          OPAMP_SEC_INVERTINGINPUT_IO1    
-
-#define OPAMP_INVERTINGINPUT_VINM             OPAMP_SEC_INVERTINGINPUT_IO1
-                                                                      
-#define OPAMP_PGACONNECT_NO                   OPAMP_PGA_CONNECT_INVERTINGINPUT_NO             
-#define OPAMP_PGACONNECT_VM0                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0            
-#define OPAMP_PGACONNECT_VM1                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1          
-                                                        
-/**
-  * @}
-  */
-
-/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define I2S_STANDARD_PHILLIPS      I2S_STANDARD_PHILIPS
-/**
-  * @}
-  */
-
-/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-/* Compact Flash-ATA registers description */
-#define CF_DATA                       ATA_DATA                
-#define CF_SECTOR_COUNT               ATA_SECTOR_COUNT        
-#define CF_SECTOR_NUMBER              ATA_SECTOR_NUMBER       
-#define CF_CYLINDER_LOW               ATA_CYLINDER_LOW        
-#define CF_CYLINDER_HIGH              ATA_CYLINDER_HIGH       
-#define CF_CARD_HEAD                  ATA_CARD_HEAD           
-#define CF_STATUS_CMD                 ATA_STATUS_CMD          
-#define CF_STATUS_CMD_ALTERNATE       ATA_STATUS_CMD_ALTERNATE
-#define CF_COMMON_DATA_AREA           ATA_COMMON_DATA_AREA    
-
-/* Compact Flash-ATA commands */
-#define CF_READ_SECTOR_CMD            ATA_READ_SECTOR_CMD 
-#define CF_WRITE_SECTOR_CMD           ATA_WRITE_SECTOR_CMD
-#define CF_ERASE_SECTOR_CMD           ATA_ERASE_SECTOR_CMD
-#define CF_IDENTIFY_CMD               ATA_IDENTIFY_CMD
-
-#define PCCARD_StatusTypedef          HAL_PCCARD_StatusTypeDef
-#define PCCARD_SUCCESS                HAL_PCCARD_STATUS_SUCCESS
-#define PCCARD_ONGOING                HAL_PCCARD_STATUS_ONGOING
-#define PCCARD_ERROR                  HAL_PCCARD_STATUS_ERROR
-#define PCCARD_TIMEOUT                HAL_PCCARD_STATUS_TIMEOUT
-/**
-  * @}
-  */
-  
-/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-  
-#define FORMAT_BIN                  RTC_FORMAT_BIN
-#define FORMAT_BCD                  RTC_FORMAT_BCD
-
-#define RTC_ALARMSUBSECONDMASK_None     RTC_ALARMSUBSECONDMASK_NONE
-#define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE
-#define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE
-#define RTC_TAMPERMASK_FLAG_DISABLED    RTC_TAMPERMASK_FLAG_DISABLE
-#define RTC_TAMPERMASK_FLAG_ENABLED     RTC_TAMPERMASK_FLAG_ENABLE
-
-#define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE 
-#define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE 
-#define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE
-#define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE 
-#define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE 
-#define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE
-#define RTC_TAMPER1_2_INTERRUPT         RTC_ALL_TAMPER_INTERRUPT 
-#define RTC_TAMPER1_2_3_INTERRUPT       RTC_ALL_TAMPER_INTERRUPT 
-
-#define RTC_TIMESTAMPPIN_PC13  RTC_TIMESTAMPPIN_DEFAULT
-#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 
-#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
-#define RTC_TIMESTAMPPIN_PC1   RTC_TIMESTAMPPIN_POS2
-
-#define RTC_OUTPUT_REMAP_PC13  RTC_OUTPUT_REMAP_NONE
-#define RTC_OUTPUT_REMAP_PB14  RTC_OUTPUT_REMAP_POS1
-#define RTC_OUTPUT_REMAP_PB2   RTC_OUTPUT_REMAP_POS1
-
-#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT 
-#define RTC_TAMPERPIN_PA0  RTC_TAMPERPIN_POS1 
-#define RTC_TAMPERPIN_PI8  RTC_TAMPERPIN_POS1
-
-/**
-  * @}
-  */
-
-  
-/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define SMARTCARD_NACK_ENABLED                  SMARTCARD_NACK_ENABLE
-#define SMARTCARD_NACK_DISABLED                 SMARTCARD_NACK_DISABLE
-
-#define SMARTCARD_ONEBIT_SAMPLING_DISABLED      SMARTCARD_ONE_BIT_SAMPLE_DISABLE
-#define SMARTCARD_ONEBIT_SAMPLING_ENABLED       SMARTCARD_ONE_BIT_SAMPLE_ENABLE
-#define SMARTCARD_ONEBIT_SAMPLING_DISABLE       SMARTCARD_ONE_BIT_SAMPLE_DISABLE
-#define SMARTCARD_ONEBIT_SAMPLING_ENABLE        SMARTCARD_ONE_BIT_SAMPLE_ENABLE
-
-#define SMARTCARD_TIMEOUT_DISABLED              SMARTCARD_TIMEOUT_DISABLE
-#define SMARTCARD_TIMEOUT_ENABLED               SMARTCARD_TIMEOUT_ENABLE
-
-#define SMARTCARD_LASTBIT_DISABLED              SMARTCARD_LASTBIT_DISABLE
-#define SMARTCARD_LASTBIT_ENABLED               SMARTCARD_LASTBIT_ENABLE
-/**
-  * @}
-  */
-
-  
-  /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define SMBUS_DUALADDRESS_DISABLED      SMBUS_DUALADDRESS_DISABLE
-#define SMBUS_DUALADDRESS_ENABLED       SMBUS_DUALADDRESS_ENABLE
-#define SMBUS_GENERALCALL_DISABLED      SMBUS_GENERALCALL_DISABLE
-#define SMBUS_GENERALCALL_ENABLED       SMBUS_GENERALCALL_ENABLE
-#define SMBUS_NOSTRETCH_DISABLED        SMBUS_NOSTRETCH_DISABLE
-#define SMBUS_NOSTRETCH_ENABLED         SMBUS_NOSTRETCH_ENABLE
-#define SMBUS_ANALOGFILTER_ENABLED      SMBUS_ANALOGFILTER_ENABLE
-#define SMBUS_ANALOGFILTER_DISABLED     SMBUS_ANALOGFILTER_DISABLE
-#define SMBUS_PEC_DISABLED              SMBUS_PEC_DISABLE
-#define SMBUS_PEC_ENABLED               SMBUS_PEC_ENABLE
-#define HAL_SMBUS_STATE_SLAVE_LISTEN    HAL_SMBUS_STATE_LISTEN
-/**
-  * @}
-  */
-  
-  /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define SPI_TIMODE_DISABLED             SPI_TIMODE_DISABLE
-#define SPI_TIMODE_ENABLED              SPI_TIMODE_ENABLE
-
-#define SPI_CRCCALCULATION_DISABLED     SPI_CRCCALCULATION_DISABLE
-#define SPI_CRCCALCULATION_ENABLED      SPI_CRCCALCULATION_ENABLE
-
-#define SPI_NSS_PULSE_DISABLED          SPI_NSS_PULSE_DISABLE
-#define SPI_NSS_PULSE_ENABLED           SPI_NSS_PULSE_ENABLE
-
-/**
-  * @}
-  */
-  
-/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define CCER_CCxE_MASK                   TIM_CCER_CCxE_MASK
-#define CCER_CCxNE_MASK                  TIM_CCER_CCxNE_MASK
-  
-#define TIM_DMABase_CR1                  TIM_DMABASE_CR1
-#define TIM_DMABase_CR2                  TIM_DMABASE_CR2
-#define TIM_DMABase_SMCR                 TIM_DMABASE_SMCR
-#define TIM_DMABase_DIER                 TIM_DMABASE_DIER
-#define TIM_DMABase_SR                   TIM_DMABASE_SR
-#define TIM_DMABase_EGR                  TIM_DMABASE_EGR
-#define TIM_DMABase_CCMR1                TIM_DMABASE_CCMR1
-#define TIM_DMABase_CCMR2                TIM_DMABASE_CCMR2
-#define TIM_DMABase_CCER                 TIM_DMABASE_CCER
-#define TIM_DMABase_CNT                  TIM_DMABASE_CNT
-#define TIM_DMABase_PSC                  TIM_DMABASE_PSC
-#define TIM_DMABase_ARR                  TIM_DMABASE_ARR
-#define TIM_DMABase_RCR                  TIM_DMABASE_RCR
-#define TIM_DMABase_CCR1                 TIM_DMABASE_CCR1
-#define TIM_DMABase_CCR2                 TIM_DMABASE_CCR2
-#define TIM_DMABase_CCR3                 TIM_DMABASE_CCR3
-#define TIM_DMABase_CCR4                 TIM_DMABASE_CCR4
-#define TIM_DMABase_BDTR                 TIM_DMABASE_BDTR
-#define TIM_DMABase_DCR                  TIM_DMABASE_DCR
-#define TIM_DMABase_DMAR                 TIM_DMABASE_DMAR
-#define TIM_DMABase_OR1                  TIM_DMABASE_OR1
-#define TIM_DMABase_CCMR3                TIM_DMABASE_CCMR3
-#define TIM_DMABase_CCR5                 TIM_DMABASE_CCR5
-#define TIM_DMABase_CCR6                 TIM_DMABASE_CCR6
-#define TIM_DMABase_OR2                  TIM_DMABASE_OR2
-#define TIM_DMABase_OR3                  TIM_DMABASE_OR3
-#define TIM_DMABase_OR                   TIM_DMABASE_OR
-
-#define TIM_EventSource_Update           TIM_EVENTSOURCE_UPDATE
-#define TIM_EventSource_CC1              TIM_EVENTSOURCE_CC1
-#define TIM_EventSource_CC2              TIM_EVENTSOURCE_CC2
-#define TIM_EventSource_CC3              TIM_EVENTSOURCE_CC3
-#define TIM_EventSource_CC4              TIM_EVENTSOURCE_CC4
-#define TIM_EventSource_COM              TIM_EVENTSOURCE_COM
-#define TIM_EventSource_Trigger          TIM_EVENTSOURCE_TRIGGER
-#define TIM_EventSource_Break            TIM_EVENTSOURCE_BREAK
-#define TIM_EventSource_Break2           TIM_EVENTSOURCE_BREAK2
-
-#define TIM_DMABurstLength_1Transfer     TIM_DMABURSTLENGTH_1TRANSFER
-#define TIM_DMABurstLength_2Transfers    TIM_DMABURSTLENGTH_2TRANSFERS
-#define TIM_DMABurstLength_3Transfers    TIM_DMABURSTLENGTH_3TRANSFERS
-#define TIM_DMABurstLength_4Transfers    TIM_DMABURSTLENGTH_4TRANSFERS
-#define TIM_DMABurstLength_5Transfers    TIM_DMABURSTLENGTH_5TRANSFERS
-#define TIM_DMABurstLength_6Transfers    TIM_DMABURSTLENGTH_6TRANSFERS
-#define TIM_DMABurstLength_7Transfers    TIM_DMABURSTLENGTH_7TRANSFERS
-#define TIM_DMABurstLength_8Transfers    TIM_DMABURSTLENGTH_8TRANSFERS
-#define TIM_DMABurstLength_9Transfers    TIM_DMABURSTLENGTH_9TRANSFERS
-#define TIM_DMABurstLength_10Transfers   TIM_DMABURSTLENGTH_10TRANSFERS
-#define TIM_DMABurstLength_11Transfers   TIM_DMABURSTLENGTH_11TRANSFERS
-#define TIM_DMABurstLength_12Transfers   TIM_DMABURSTLENGTH_12TRANSFERS
-#define TIM_DMABurstLength_13Transfers   TIM_DMABURSTLENGTH_13TRANSFERS
-#define TIM_DMABurstLength_14Transfers   TIM_DMABURSTLENGTH_14TRANSFERS
-#define TIM_DMABurstLength_15Transfers   TIM_DMABURSTLENGTH_15TRANSFERS
-#define TIM_DMABurstLength_16Transfers   TIM_DMABURSTLENGTH_16TRANSFERS
-#define TIM_DMABurstLength_17Transfers   TIM_DMABURSTLENGTH_17TRANSFERS
-#define TIM_DMABurstLength_18Transfers   TIM_DMABURSTLENGTH_18TRANSFERS
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define TSC_SYNC_POL_FALL        TSC_SYNC_POLARITY_FALLING
-#define TSC_SYNC_POL_RISE_HIGH   TSC_SYNC_POLARITY_RISING
-/**
-  * @}
-  */
-
-/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define UART_ONEBIT_SAMPLING_DISABLED   UART_ONE_BIT_SAMPLE_DISABLE
-#define UART_ONEBIT_SAMPLING_ENABLED    UART_ONE_BIT_SAMPLE_ENABLE
-#define UART_ONE_BIT_SAMPLE_DISABLED    UART_ONE_BIT_SAMPLE_DISABLE
-#define UART_ONE_BIT_SAMPLE_ENABLED     UART_ONE_BIT_SAMPLE_ENABLE
-
-#define __HAL_UART_ONEBIT_ENABLE        __HAL_UART_ONE_BIT_SAMPLE_ENABLE
-#define __HAL_UART_ONEBIT_DISABLE       __HAL_UART_ONE_BIT_SAMPLE_DISABLE
-
-#define __DIV_SAMPLING16                UART_DIV_SAMPLING16
-#define __DIVMANT_SAMPLING16            UART_DIVMANT_SAMPLING16
-#define __DIVFRAQ_SAMPLING16            UART_DIVFRAQ_SAMPLING16
-#define __UART_BRR_SAMPLING16           UART_BRR_SAMPLING16
-
-#define __DIV_SAMPLING8                 UART_DIV_SAMPLING8
-#define __DIVMANT_SAMPLING8             UART_DIVMANT_SAMPLING8
-#define __DIVFRAQ_SAMPLING8             UART_DIVFRAQ_SAMPLING8
-#define __UART_BRR_SAMPLING8            UART_BRR_SAMPLING8
-
-#define UART_WAKEUPMETHODE_IDLELINE     UART_WAKEUPMETHOD_IDLELINE
-#define UART_WAKEUPMETHODE_ADDRESSMARK  UART_WAKEUPMETHOD_ADDRESSMARK
-
-/**
-  * @}
-  */
-
-  
-/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define USART_CLOCK_DISABLED            USART_CLOCK_DISABLE
-#define USART_CLOCK_ENABLED             USART_CLOCK_ENABLE
-
-#define USARTNACK_ENABLED               USART_NACK_ENABLE
-#define USARTNACK_DISABLED              USART_NACK_DISABLE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define CFR_BASE                    WWDG_CFR_BASE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define CAN_FilterFIFO0             CAN_FILTER_FIFO0
-#define CAN_FilterFIFO1             CAN_FILTER_FIFO1
-#define CAN_IT_RQCP0                CAN_IT_TME
-#define CAN_IT_RQCP1                CAN_IT_TME
-#define CAN_IT_RQCP2                CAN_IT_TME
-#define INAK_TIMEOUT                CAN_TIMEOUT_VALUE
-#define SLAK_TIMEOUT                CAN_TIMEOUT_VALUE
-#define CAN_TXSTATUS_FAILED         ((uint8_t)0x00U)
-#define CAN_TXSTATUS_OK             ((uint8_t)0x01U)
-#define CAN_TXSTATUS_PENDING        ((uint8_t)0x02U)
-
-/**
-  * @}
-  */
-  
-/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define VLAN_TAG                ETH_VLAN_TAG
-#define MIN_ETH_PAYLOAD         ETH_MIN_ETH_PAYLOAD
-#define MAX_ETH_PAYLOAD         ETH_MAX_ETH_PAYLOAD
-#define JUMBO_FRAME_PAYLOAD     ETH_JUMBO_FRAME_PAYLOAD
-#define MACMIIAR_CR_MASK        ETH_MACMIIAR_CR_MASK
-#define MACCR_CLEAR_MASK        ETH_MACCR_CLEAR_MASK
-#define MACFCR_CLEAR_MASK       ETH_MACFCR_CLEAR_MASK
-#define DMAOMR_CLEAR_MASK       ETH_DMAOMR_CLEAR_MASK
-
-#define ETH_MMCCR              ((uint32_t)0x00000100U)  
-#define ETH_MMCRIR             ((uint32_t)0x00000104U)  
-#define ETH_MMCTIR             ((uint32_t)0x00000108U)  
-#define ETH_MMCRIMR            ((uint32_t)0x0000010CU)  
-#define ETH_MMCTIMR            ((uint32_t)0x00000110U)  
-#define ETH_MMCTGFSCCR         ((uint32_t)0x0000014CU)  
-#define ETH_MMCTGFMSCCR        ((uint32_t)0x00000150U)  
-#define ETH_MMCTGFCR           ((uint32_t)0x00000168U)  
-#define ETH_MMCRFCECR          ((uint32_t)0x00000194U)  
-#define ETH_MMCRFAECR          ((uint32_t)0x00000198U)  
-#define ETH_MMCRGUFCR          ((uint32_t)0x000001C4U)
- 
-#define ETH_MAC_TXFIFO_FULL          ((uint32_t)0x02000000)  /* Tx FIFO full */
-#define ETH_MAC_TXFIFONOT_EMPTY      ((uint32_t)0x01000000)  /* Tx FIFO not empty */
-#define ETH_MAC_TXFIFO_WRITE_ACTIVE  ((uint32_t)0x00400000)  /* Tx FIFO write active */
-#define ETH_MAC_TXFIFO_IDLE     ((uint32_t)0x00000000)  /* Tx FIFO read status: Idle */
-#define ETH_MAC_TXFIFO_READ     ((uint32_t)0x00100000)  /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
-#define ETH_MAC_TXFIFO_WAITING  ((uint32_t)0x00200000)  /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
-#define ETH_MAC_TXFIFO_WRITING  ((uint32_t)0x00300000)  /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
-#define ETH_MAC_TRANSMISSION_PAUSE     ((uint32_t)0x00080000)  /* MAC transmitter in pause */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE            ((uint32_t)0x00000000)  /* MAC transmit frame controller: Idle */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING         ((uint32_t)0x00020000)  /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF   ((uint32_t)0x00040000)  /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING    ((uint32_t)0x00060000)  /* MAC transmit frame controller: Transferring input frame for transmission */
-#define ETH_MAC_MII_TRANSMIT_ACTIVE      ((uint32_t)0x00010000)  /* MAC MII transmit engine active */
-#define ETH_MAC_RXFIFO_EMPTY             ((uint32_t)0x00000000)  /* Rx FIFO fill level: empty */
-#define ETH_MAC_RXFIFO_BELOW_THRESHOLD   ((uint32_t)0x00000100)  /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
-#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD   ((uint32_t)0x00000200)  /* Rx FIFO fill level: fill-level above flow-control activate threshold */
-#define ETH_MAC_RXFIFO_FULL              ((uint32_t)0x00000300)  /* Rx FIFO fill level: full */
-#define ETH_MAC_READCONTROLLER_IDLE               ((uint32_t)0x00000000)  /* Rx FIFO read controller IDLE state */
-#define ETH_MAC_READCONTROLLER_READING_DATA       ((uint32_t)0x00000020)  /* Rx FIFO read controller Reading frame data */
-#define ETH_MAC_READCONTROLLER_READING_STATUS     ((uint32_t)0x00000040)  /* Rx FIFO read controller Reading frame status (or time-stamp) */
-#define ETH_MAC_READCONTROLLER_FLUSHING           ((uint32_t)0x00000060)  /* Rx FIFO read controller Flushing the frame data and status */
-#define ETH_MAC_RXFIFO_WRITE_ACTIVE     ((uint32_t)0x00000010)  /* Rx FIFO write controller active */
-#define ETH_MAC_SMALL_FIFO_NOTACTIVE    ((uint32_t)0x00000000)  /* MAC small FIFO read / write controllers not active */
-#define ETH_MAC_SMALL_FIFO_READ_ACTIVE  ((uint32_t)0x00000002)  /* MAC small FIFO read controller active */
-#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004)  /* MAC small FIFO write controller active */
-#define ETH_MAC_SMALL_FIFO_RW_ACTIVE    ((uint32_t)0x00000006)  /* MAC small FIFO read / write controllers active */
-#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE   ((uint32_t)0x00000001)  /* MAC MII receive protocol engine active */
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
-  * @{
-  */
-  
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_CRYP_ComputationCpltCallback     HAL_CRYPEx_ComputationCpltCallback
-/**
-  * @}
-  */  
-
-/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
-  * @{
-  */ 
-#define HAL_HASH_STATETypeDef        HAL_HASH_StateTypeDef
-#define HAL_HASHPhaseTypeDef         HAL_HASH_PhaseTypeDef
-#define HAL_HMAC_MD5_Finish          HAL_HASH_MD5_Finish
-#define HAL_HMAC_SHA1_Finish         HAL_HASH_SHA1_Finish
-#define HAL_HMAC_SHA224_Finish       HAL_HASH_SHA224_Finish
-#define HAL_HMAC_SHA256_Finish       HAL_HASH_SHA256_Finish
-
-/*HASH Algorithm Selection*/
-
-#define HASH_AlgoSelection_SHA1      HASH_ALGOSELECTION_SHA1 
-#define HASH_AlgoSelection_SHA224    HASH_ALGOSELECTION_SHA224
-#define HASH_AlgoSelection_SHA256    HASH_ALGOSELECTION_SHA256
-#define HASH_AlgoSelection_MD5       HASH_ALGOSELECTION_MD5
-
-#define HASH_AlgoMode_HASH         HASH_ALGOMODE_HASH 
-#define HASH_AlgoMode_HMAC         HASH_ALGOMODE_HMAC
-
-#define HASH_HMACKeyType_ShortKey  HASH_HMAC_KEYTYPE_SHORTKEY
-#define HASH_HMACKeyType_LongKey   HASH_HMAC_KEYTYPE_LONGKEY
-/**
-  * @}
-  */
-  
-/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
-#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
-#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
-#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
-#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
-#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
-#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
-#define HAL_VREFINT_OutputSelect  HAL_SYSCFG_VREFINT_OutputSelect
-#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
-#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
-#define HAL_ADC_EnableBuffer_Cmd(cmd)  (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
-#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
-/**
-  * @}
-  */
-
-/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define FLASH_HalfPageProgram      HAL_FLASHEx_HalfPageProgram
-#define FLASH_EnableRunPowerDown   HAL_FLASHEx_EnableRunPowerDown
-#define FLASH_DisableRunPowerDown  HAL_FLASHEx_DisableRunPowerDown
-#define HAL_DATA_EEPROMEx_Unlock   HAL_FLASHEx_DATAEEPROM_Unlock
-#define HAL_DATA_EEPROMEx_Lock     HAL_FLASHEx_DATAEEPROM_Lock
-#define HAL_DATA_EEPROMEx_Erase    HAL_FLASHEx_DATAEEPROM_Erase
-#define HAL_DATA_EEPROMEx_Program  HAL_FLASHEx_DATAEEPROM_Program
-
- /**
-  * @}
-  */
-
-/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_I2CEx_AnalogFilter_Config         HAL_I2CEx_ConfigAnalogFilter
-#define HAL_I2CEx_DigitalFilter_Config        HAL_I2CEx_ConfigDigitalFilter
-#define HAL_FMPI2CEx_AnalogFilter_Config      HAL_FMPI2CEx_ConfigAnalogFilter
-#define HAL_FMPI2CEx_DigitalFilter_Config     HAL_FMPI2CEx_ConfigDigitalFilter
-
-#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
- /**
-  * @}
-  */
-
-/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
-  * @{
-  */
-#define HAL_PWR_PVDConfig                             HAL_PWR_ConfigPVD
-#define HAL_PWR_DisableBkUpReg                        HAL_PWREx_DisableBkUpReg
-#define HAL_PWR_DisableFlashPowerDown                 HAL_PWREx_DisableFlashPowerDown
-#define HAL_PWR_DisableVddio2Monitor                  HAL_PWREx_DisableVddio2Monitor
-#define HAL_PWR_EnableBkUpReg                         HAL_PWREx_EnableBkUpReg
-#define HAL_PWR_EnableFlashPowerDown                  HAL_PWREx_EnableFlashPowerDown
-#define HAL_PWR_EnableVddio2Monitor                   HAL_PWREx_EnableVddio2Monitor
-#define HAL_PWR_PVD_PVM_IRQHandler                    HAL_PWREx_PVD_PVM_IRQHandler
-#define HAL_PWR_PVDLevelConfig                        HAL_PWR_ConfigPVD
-#define HAL_PWR_Vddio2Monitor_IRQHandler              HAL_PWREx_Vddio2Monitor_IRQHandler
-#define HAL_PWR_Vddio2MonitorCallback                 HAL_PWREx_Vddio2MonitorCallback
-#define HAL_PWREx_ActivateOverDrive                   HAL_PWREx_EnableOverDrive
-#define HAL_PWREx_DeactivateOverDrive                 HAL_PWREx_DisableOverDrive
-#define HAL_PWREx_DisableSDADCAnalog                  HAL_PWREx_DisableSDADC
-#define HAL_PWREx_EnableSDADCAnalog                   HAL_PWREx_EnableSDADC
-#define HAL_PWREx_PVMConfig                           HAL_PWREx_ConfigPVM
-
-#define PWR_MODE_NORMAL                               PWR_PVD_MODE_NORMAL
-#define PWR_MODE_IT_RISING                            PWR_PVD_MODE_IT_RISING
-#define PWR_MODE_IT_FALLING                           PWR_PVD_MODE_IT_FALLING
-#define PWR_MODE_IT_RISING_FALLING                    PWR_PVD_MODE_IT_RISING_FALLING
-#define PWR_MODE_EVENT_RISING                         PWR_PVD_MODE_EVENT_RISING
-#define PWR_MODE_EVENT_FALLING                        PWR_PVD_MODE_EVENT_FALLING
-#define PWR_MODE_EVENT_RISING_FALLING                 PWR_PVD_MODE_EVENT_RISING_FALLING
-
-#define CR_OFFSET_BB                                  PWR_CR_OFFSET_BB
-#define CSR_OFFSET_BB                                 PWR_CSR_OFFSET_BB
-
-#define DBP_BitNumber                                 DBP_BIT_NUMBER
-#define PVDE_BitNumber                                PVDE_BIT_NUMBER
-#define PMODE_BitNumber                               PMODE_BIT_NUMBER
-#define EWUP_BitNumber                                EWUP_BIT_NUMBER
-#define FPDS_BitNumber                                FPDS_BIT_NUMBER
-#define ODEN_BitNumber                                ODEN_BIT_NUMBER
-#define ODSWEN_BitNumber                              ODSWEN_BIT_NUMBER
-#define MRLVDS_BitNumber                              MRLVDS_BIT_NUMBER
-#define LPLVDS_BitNumber                              LPLVDS_BIT_NUMBER
-#define BRE_BitNumber                                 BRE_BIT_NUMBER
-
-#define PWR_MODE_EVT                                  PWR_PVD_MODE_NORMAL
- 
- /**
-  * @}
-  */  
-  
-/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_SMBUS_Slave_Listen_IT          HAL_SMBUS_EnableListen_IT
-#define HAL_SMBUS_SlaveAddrCallback        HAL_SMBUS_AddrCallback         
-#define HAL_SMBUS_SlaveListenCpltCallback  HAL_SMBUS_ListenCpltCallback   
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_SPI_FlushRxFifo                HAL_SPIEx_FlushRxFifo
-/**
-  * @}
-  */  
-
-/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_TIM_DMADelayPulseCplt                       TIM_DMADelayPulseCplt
-#define HAL_TIM_DMAError                                TIM_DMAError
-#define HAL_TIM_DMACaptureCplt                          TIM_DMACaptureCplt
-#define HAL_TIMEx_DMACommutationCplt                    TIMEx_DMACommutationCplt
-/**
-  * @}
-  */
-   
-/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
-  * @{
-  */ 
-#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
-/**
-  * @}
-  */
-  
-/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
-  * @{
-  */ 
-#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
-/**
-  * @}
-  */  
-   
-  
-   /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
-  * @{
-  */
-  
-/**
-  * @}
-  */
-
-/* Exported macros ------------------------------------------------------------*/
-
-/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define AES_IT_CC                      CRYP_IT_CC
-#define AES_IT_ERR                     CRYP_IT_ERR
-#define AES_FLAG_CCF                   CRYP_FLAG_CCF
-/**
-  * @}
-  */  
-  
-/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_GET_BOOT_MODE                   __HAL_SYSCFG_GET_BOOT_MODE
-#define __HAL_REMAPMEMORY_FLASH               __HAL_SYSCFG_REMAPMEMORY_FLASH
-#define __HAL_REMAPMEMORY_SYSTEMFLASH         __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
-#define __HAL_REMAPMEMORY_SRAM                __HAL_SYSCFG_REMAPMEMORY_SRAM
-#define __HAL_REMAPMEMORY_FMC                 __HAL_SYSCFG_REMAPMEMORY_FMC
-#define __HAL_REMAPMEMORY_FMC_SDRAM           __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM 
-#define __HAL_REMAPMEMORY_FSMC                __HAL_SYSCFG_REMAPMEMORY_FSMC
-#define __HAL_REMAPMEMORY_QUADSPI             __HAL_SYSCFG_REMAPMEMORY_QUADSPI
-#define __HAL_FMC_BANK                        __HAL_SYSCFG_FMC_BANK
-#define __HAL_GET_FLAG                        __HAL_SYSCFG_GET_FLAG
-#define __HAL_CLEAR_FLAG                      __HAL_SYSCFG_CLEAR_FLAG
-#define __HAL_VREFINT_OUT_ENABLE              __HAL_SYSCFG_VREFINT_OUT_ENABLE
-#define __HAL_VREFINT_OUT_DISABLE             __HAL_SYSCFG_VREFINT_OUT_DISABLE
-
-#define SYSCFG_FLAG_VREF_READY                SYSCFG_FLAG_VREFINT_READY
-#define SYSCFG_FLAG_RC48                      RCC_FLAG_HSI48
-#define IS_SYSCFG_FASTMODEPLUS_CONFIG         IS_I2C_FASTMODEPLUS
-#define UFB_MODE_BitNumber                    UFB_MODE_BIT_NUMBER
-#define CMP_PD_BitNumber                      CMP_PD_BIT_NUMBER
-
-/**
-  * @}
-  */
-
-   
-/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __ADC_ENABLE                                     __HAL_ADC_ENABLE
-#define __ADC_DISABLE                                    __HAL_ADC_DISABLE
-#define __HAL_ADC_ENABLING_CONDITIONS                    ADC_ENABLING_CONDITIONS
-#define __HAL_ADC_DISABLING_CONDITIONS                   ADC_DISABLING_CONDITIONS
-#define __HAL_ADC_IS_ENABLED                             ADC_IS_ENABLE
-#define __ADC_IS_ENABLED                                 ADC_IS_ENABLE
-#define __HAL_ADC_IS_SOFTWARE_START_REGULAR              ADC_IS_SOFTWARE_START_REGULAR
-#define __HAL_ADC_IS_SOFTWARE_START_INJECTED             ADC_IS_SOFTWARE_START_INJECTED
-#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
-#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR          ADC_IS_CONVERSION_ONGOING_REGULAR
-#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED         ADC_IS_CONVERSION_ONGOING_INJECTED
-#define __HAL_ADC_IS_CONVERSION_ONGOING                  ADC_IS_CONVERSION_ONGOING
-#define __HAL_ADC_CLEAR_ERRORCODE                        ADC_CLEAR_ERRORCODE
-
-#define __HAL_ADC_GET_RESOLUTION                         ADC_GET_RESOLUTION
-#define __HAL_ADC_JSQR_RK                                ADC_JSQR_RK
-#define __HAL_ADC_CFGR_AWD1CH                            ADC_CFGR_AWD1CH_SHIFT
-#define __HAL_ADC_CFGR_AWD23CR                           ADC_CFGR_AWD23CR
-#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION            ADC_CFGR_INJECT_AUTO_CONVERSION
-#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE              ADC_CFGR_INJECT_CONTEXT_QUEUE
-#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS             ADC_CFGR_INJECT_DISCCONTINUOUS
-#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS                ADC_CFGR_REG_DISCCONTINUOUS
-#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM                 ADC_CFGR_DISCONTINUOUS_NUM
-#define __HAL_ADC_CFGR_AUTOWAIT                          ADC_CFGR_AUTOWAIT
-#define __HAL_ADC_CFGR_CONTINUOUS                        ADC_CFGR_CONTINUOUS
-#define __HAL_ADC_CFGR_OVERRUN                           ADC_CFGR_OVERRUN
-#define __HAL_ADC_CFGR_DMACONTREQ                        ADC_CFGR_DMACONTREQ
-#define __HAL_ADC_CFGR_EXTSEL                            ADC_CFGR_EXTSEL_SET
-#define __HAL_ADC_JSQR_JEXTSEL                           ADC_JSQR_JEXTSEL_SET
-#define __HAL_ADC_OFR_CHANNEL                            ADC_OFR_CHANNEL
-#define __HAL_ADC_DIFSEL_CHANNEL                         ADC_DIFSEL_CHANNEL
-#define __HAL_ADC_CALFACT_DIFF_SET                       ADC_CALFACT_DIFF_SET
-#define __HAL_ADC_CALFACT_DIFF_GET                       ADC_CALFACT_DIFF_GET
-#define __HAL_ADC_TRX_HIGHTHRESHOLD                      ADC_TRX_HIGHTHRESHOLD
-
-#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION                ADC_OFFSET_SHIFT_RESOLUTION
-#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION         ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
-#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION        ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
-#define __HAL_ADC_COMMON_REGISTER                        ADC_COMMON_REGISTER
-#define __HAL_ADC_COMMON_CCR_MULTI                       ADC_COMMON_CCR_MULTI
-#define __HAL_ADC_MULTIMODE_IS_ENABLED                   ADC_MULTIMODE_IS_ENABLE
-#define __ADC_MULTIMODE_IS_ENABLED                       ADC_MULTIMODE_IS_ENABLE
-#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER        ADC_NONMULTIMODE_OR_MULTIMODEMASTER
-#define __HAL_ADC_COMMON_ADC_OTHER                       ADC_COMMON_ADC_OTHER
-#define __HAL_ADC_MULTI_SLAVE                            ADC_MULTI_SLAVE
-
-#define __HAL_ADC_SQR1_L                                 ADC_SQR1_L_SHIFT
-#define __HAL_ADC_JSQR_JL                                ADC_JSQR_JL_SHIFT
-#define __HAL_ADC_JSQR_RK_JL                             ADC_JSQR_RK_JL
-#define __HAL_ADC_CR1_DISCONTINUOUS_NUM                  ADC_CR1_DISCONTINUOUS_NUM
-#define __HAL_ADC_CR1_SCAN                               ADC_CR1_SCAN_SET
-#define __HAL_ADC_CONVCYCLES_MAX_RANGE                   ADC_CONVCYCLES_MAX_RANGE
-#define __HAL_ADC_CLOCK_PRESCALER_RANGE                  ADC_CLOCK_PRESCALER_RANGE
-#define __HAL_ADC_GET_CLOCK_PRESCALER                    ADC_GET_CLOCK_PRESCALER
-
-#define __HAL_ADC_SQR1                                   ADC_SQR1
-#define __HAL_ADC_SMPR1                                  ADC_SMPR1
-#define __HAL_ADC_SMPR2                                  ADC_SMPR2
-#define __HAL_ADC_SQR3_RK                                ADC_SQR3_RK
-#define __HAL_ADC_SQR2_RK                                ADC_SQR2_RK
-#define __HAL_ADC_SQR1_RK                                ADC_SQR1_RK
-#define __HAL_ADC_CR2_CONTINUOUS                         ADC_CR2_CONTINUOUS
-#define __HAL_ADC_CR1_DISCONTINUOUS                      ADC_CR1_DISCONTINUOUS
-#define __HAL_ADC_CR1_SCANCONV                           ADC_CR1_SCANCONV
-#define __HAL_ADC_CR2_EOCSelection                       ADC_CR2_EOCSelection
-#define __HAL_ADC_CR2_DMAContReq                         ADC_CR2_DMAContReq
-#define __HAL_ADC_GET_RESOLUTION                         ADC_GET_RESOLUTION
-#define __HAL_ADC_JSQR                                   ADC_JSQR
-
-#define __HAL_ADC_CHSELR_CHANNEL                         ADC_CHSELR_CHANNEL
-#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS               ADC_CFGR1_REG_DISCCONTINUOUS
-#define __HAL_ADC_CFGR1_AUTOOFF                          ADC_CFGR1_AUTOOFF
-#define __HAL_ADC_CFGR1_AUTOWAIT                         ADC_CFGR1_AUTOWAIT
-#define __HAL_ADC_CFGR1_CONTINUOUS                       ADC_CFGR1_CONTINUOUS
-#define __HAL_ADC_CFGR1_OVERRUN                          ADC_CFGR1_OVERRUN
-#define __HAL_ADC_CFGR1_SCANDIR                          ADC_CFGR1_SCANDIR
-#define __HAL_ADC_CFGR1_DMACONTREQ                       ADC_CFGR1_DMACONTREQ
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_DHR12R1_ALIGNEMENT                        DAC_DHR12R1_ALIGNMENT
-#define __HAL_DHR12R2_ALIGNEMENT                        DAC_DHR12R2_ALIGNMENT
-#define __HAL_DHR12RD_ALIGNEMENT                        DAC_DHR12RD_ALIGNMENT
-#define IS_DAC_GENERATE_WAVE                            IS_DAC_WAVE
-
-/**
-  * @}
-  */
-   
-/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
-#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
-#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
-#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
-#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
-#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
-#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
-#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
-#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
-#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
-#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
-#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
-#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
-#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
-#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
-#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
-
-#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
-#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
-#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
-#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
-#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
-#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
-#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
-#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
-#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
-#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
-#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
-#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
-#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
-#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
-
-
-#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
-#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
-#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
-#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
-#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
-#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
-#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
-#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
-#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
-#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
-#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
-#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
-#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
-#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
-#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
-#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
-#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
-#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
-#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
-#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
-#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
-#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
-#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
-#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#if defined(STM32F3)
-#define COMP_START                                       __HAL_COMP_ENABLE
-#define COMP_STOP                                        __HAL_COMP_DISABLE
-#define COMP_LOCK                                        __HAL_COMP_LOCK
-   
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
-                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F302xE) || defined(STM32F302xC)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
-                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
-                                                          __HAL_COMP_COMP7_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
-                                                          __HAL_COMP_COMP7_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
-                                                          __HAL_COMP_COMP7_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F373xC) ||defined(STM32F378xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
-                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
-# endif
-#else
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
-                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
-#endif
-
-#define __HAL_COMP_GET_EXTI_LINE  COMP_GET_EXTI_LINE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
-                          ((WAVE) == DAC_WAVE_NOISE)|| \
-                          ((WAVE) == DAC_WAVE_TRIANGLE))
-  
-/**
-  * @}
-  */
-
-/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define IS_WRPAREA          IS_OB_WRPAREA
-#define IS_TYPEPROGRAM      IS_FLASH_TYPEPROGRAM
-#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
-#define IS_TYPEERASE        IS_FLASH_TYPEERASE
-#define IS_NBSECTORS        IS_FLASH_NBSECTORS
-#define IS_OB_WDG_SOURCE    IS_OB_IWDG_SOURCE
-
-/**
-  * @}
-  */
-  
-/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
-  * @{
-  */
-  
-#define __HAL_I2C_RESET_CR2             I2C_RESET_CR2
-#define __HAL_I2C_GENERATE_START        I2C_GENERATE_START
-#define __HAL_I2C_FREQ_RANGE            I2C_FREQ_RANGE
-#define __HAL_I2C_RISE_TIME             I2C_RISE_TIME
-#define __HAL_I2C_SPEED_STANDARD        I2C_SPEED_STANDARD
-#define __HAL_I2C_SPEED_FAST            I2C_SPEED_FAST
-#define __HAL_I2C_SPEED                 I2C_SPEED
-#define __HAL_I2C_7BIT_ADD_WRITE        I2C_7BIT_ADD_WRITE
-#define __HAL_I2C_7BIT_ADD_READ         I2C_7BIT_ADD_READ
-#define __HAL_I2C_10BIT_ADDRESS         I2C_10BIT_ADDRESS
-#define __HAL_I2C_10BIT_HEADER_WRITE    I2C_10BIT_HEADER_WRITE
-#define __HAL_I2C_10BIT_HEADER_READ     I2C_10BIT_HEADER_READ
-#define __HAL_I2C_MEM_ADD_MSB           I2C_MEM_ADD_MSB
-#define __HAL_I2C_MEM_ADD_LSB           I2C_MEM_ADD_LSB
-#define __HAL_I2C_FREQRANGE             I2C_FREQRANGE
-/**
-  * @}
-  */
-  
-/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
-  * @{
-  */
-  
-#define IS_I2S_INSTANCE                 IS_I2S_ALL_INSTANCE
-#define IS_I2S_INSTANCE_EXT             IS_I2S_ALL_INSTANCE_EXT
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
-  * @{
-  */
-  
-#define __IRDA_DISABLE                  __HAL_IRDA_DISABLE
-#define __IRDA_ENABLE                   __HAL_IRDA_ENABLE
-
-#define __HAL_IRDA_GETCLOCKSOURCE       IRDA_GETCLOCKSOURCE
-#define __HAL_IRDA_MASK_COMPUTATION     IRDA_MASK_COMPUTATION
-#define __IRDA_GETCLOCKSOURCE           IRDA_GETCLOCKSOURCE
-#define __IRDA_MASK_COMPUTATION         IRDA_MASK_COMPUTATION
-
-#define IS_IRDA_ONEBIT_SAMPLE           IS_IRDA_ONE_BIT_SAMPLE                  
-
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_IWDG_ENABLE_WRITE_ACCESS  IWDG_ENABLE_WRITE_ACCESS
-#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __HAL_LPTIM_ENABLE_INTERRUPT    __HAL_LPTIM_ENABLE_IT
-#define __HAL_LPTIM_DISABLE_INTERRUPT   __HAL_LPTIM_DISABLE_IT
-#define __HAL_LPTIM_GET_ITSTATUS        __HAL_LPTIM_GET_IT_SOURCE
-
-/**
-  * @}
-  */
-  
-  
-/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __OPAMP_CSR_OPAXPD                OPAMP_CSR_OPAXPD
-#define __OPAMP_CSR_S3SELX                OPAMP_CSR_S3SELX
-#define __OPAMP_CSR_S4SELX                OPAMP_CSR_S4SELX
-#define __OPAMP_CSR_S5SELX                OPAMP_CSR_S5SELX
-#define __OPAMP_CSR_S6SELX                OPAMP_CSR_S6SELX
-#define __OPAMP_CSR_OPAXCAL_L             OPAMP_CSR_OPAXCAL_L
-#define __OPAMP_CSR_OPAXCAL_H             OPAMP_CSR_OPAXCAL_H
-#define __OPAMP_CSR_OPAXLPM               OPAMP_CSR_OPAXLPM
-#define __OPAMP_CSR_ALL_SWITCHES          OPAMP_CSR_ALL_SWITCHES
-#define __OPAMP_CSR_ANAWSELX              OPAMP_CSR_ANAWSELX
-#define __OPAMP_CSR_OPAXCALOUT            OPAMP_CSR_OPAXCALOUT
-#define __OPAMP_OFFSET_TRIM_BITSPOSITION  OPAMP_OFFSET_TRIM_BITSPOSITION
-#define __OPAMP_OFFSET_TRIM_SET           OPAMP_OFFSET_TRIM_SET
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_PVD_EVENT_DISABLE                                  __HAL_PWR_PVD_EXTI_DISABLE_EVENT
-#define __HAL_PVD_EVENT_ENABLE                                   __HAL_PWR_PVD_EXTI_ENABLE_EVENT
-#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
-#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
-#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PVM_EVENT_DISABLE                                  __HAL_PWR_PVM_EVENT_DISABLE
-#define __HAL_PVM_EVENT_ENABLE                                   __HAL_PWR_PVM_EVENT_ENABLE
-#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
-#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
-#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
-#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
-#define __HAL_PWR_INTERNALWAKEUP_DISABLE                         HAL_PWREx_DisableInternalWakeUpLine
-#define __HAL_PWR_INTERNALWAKEUP_ENABLE                          HAL_PWREx_EnableInternalWakeUpLine
-#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE                    HAL_PWREx_DisablePullUpPullDownConfig
-#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE                     HAL_PWREx_EnablePullUpPullDownConfig
-#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER()                  do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
-#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE                         __HAL_PWR_PVD_EXTI_DISABLE_EVENT
-#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE                          __HAL_PWR_PVD_EXTI_ENABLE_EVENT
-#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE                __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
-#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE                 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE                 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
-#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE                  __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER              __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER               __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PWR_PVM_DISABLE()                                  do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
-#define __HAL_PWR_PVM_ENABLE()                                   do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
-#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE                  HAL_PWREx_DisableSRAM2ContentRetention
-#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE                   HAL_PWREx_EnableSRAM2ContentRetention
-#define __HAL_PWR_VDDIO2_DISABLE                                 HAL_PWREx_DisableVddIO2
-#define __HAL_PWR_VDDIO2_ENABLE                                  HAL_PWREx_EnableVddIO2
-#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER                 __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
-#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER           __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PWR_VDDUSB_DISABLE                                 HAL_PWREx_DisableVddUSB
-#define __HAL_PWR_VDDUSB_ENABLE                                  HAL_PWREx_EnableVddUSB
-
-#if defined (STM32F4)
-#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD)         __HAL_PWR_PVD_EXTI_ENABLE_IT()
-#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_DISABLE_IT()
-#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD)          __HAL_PWR_PVD_EXTI_GET_FLAG()   
-#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
-#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD)     __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
-#else
-#define __HAL_PVD_EXTI_CLEAR_FLAG                                __HAL_PWR_PVD_EXTI_CLEAR_FLAG
-#define __HAL_PVD_EXTI_DISABLE_IT                                __HAL_PWR_PVD_EXTI_DISABLE_IT
-#define __HAL_PVD_EXTI_ENABLE_IT                                 __HAL_PWR_PVD_EXTI_ENABLE_IT
-#define __HAL_PVD_EXTI_GENERATE_SWIT                             __HAL_PWR_PVD_EXTI_GENERATE_SWIT
-#define __HAL_PVD_EXTI_GET_FLAG                                  __HAL_PWR_PVD_EXTI_GET_FLAG 
-#endif /* STM32F4 */
-/**   
-  * @}
-  */  
-  
-  
-/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
-  * @{
-  */
-  
-#define RCC_StopWakeUpClock_MSI     RCC_STOP_WAKEUPCLOCK_MSI
-#define RCC_StopWakeUpClock_HSI     RCC_STOP_WAKEUPCLOCK_HSI
-
-#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
-#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
-
-#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
-#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
-#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
-#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
-#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
-#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
-#define __ADC1_CLK_DISABLE        __HAL_RCC_ADC1_CLK_DISABLE
-#define __ADC1_CLK_ENABLE         __HAL_RCC_ADC1_CLK_ENABLE
-#define __ADC1_FORCE_RESET        __HAL_RCC_ADC1_FORCE_RESET
-#define __ADC1_RELEASE_RESET      __HAL_RCC_ADC1_RELEASE_RESET
-#define __ADC1_CLK_SLEEP_ENABLE   __HAL_RCC_ADC1_CLK_SLEEP_ENABLE  
-#define __ADC1_CLK_SLEEP_DISABLE  __HAL_RCC_ADC1_CLK_SLEEP_DISABLE  
-#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
-#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
-#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
-#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
-#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
-#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
-#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
-#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
-#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
-#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
-#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
-#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
-#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
-#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
-#define __CRYP_CLK_SLEEP_ENABLE      __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
-#define __CRYP_CLK_SLEEP_DISABLE  __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
-#define __CRYP_CLK_ENABLE  __HAL_RCC_CRYP_CLK_ENABLE
-#define __CRYP_CLK_DISABLE  __HAL_RCC_CRYP_CLK_DISABLE
-#define __CRYP_FORCE_RESET  __HAL_RCC_CRYP_FORCE_RESET
-#define __CRYP_RELEASE_RESET  __HAL_RCC_CRYP_RELEASE_RESET
-#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
-#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
-#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
-#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
-#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
-#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
-#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
-#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
-#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
-#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
-#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
-#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
-#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
-#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
-#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
-#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
-#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
-#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
-#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
-#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
-#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
-#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
-#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
-#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
-#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
-#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
-#define __CAN_CLK_DISABLE         __HAL_RCC_CAN1_CLK_DISABLE
-#define __CAN_CLK_ENABLE          __HAL_RCC_CAN1_CLK_ENABLE
-#define __CAN_FORCE_RESET         __HAL_RCC_CAN1_FORCE_RESET
-#define __CAN_RELEASE_RESET       __HAL_RCC_CAN1_RELEASE_RESET
-#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
-#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
-#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
-#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
-#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
-#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
-#define __COMP_CLK_DISABLE        __HAL_RCC_COMP_CLK_DISABLE
-#define __COMP_CLK_ENABLE         __HAL_RCC_COMP_CLK_ENABLE
-#define __COMP_FORCE_RESET        __HAL_RCC_COMP_FORCE_RESET
-#define __COMP_RELEASE_RESET      __HAL_RCC_COMP_RELEASE_RESET
-#define __COMP_CLK_SLEEP_ENABLE   __HAL_RCC_COMP_CLK_SLEEP_ENABLE
-#define __COMP_CLK_SLEEP_DISABLE  __HAL_RCC_COMP_CLK_SLEEP_DISABLE
-#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
-#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
-#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
-#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
-#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
-#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
-#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
-#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
-#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
-#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
-#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
-#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
-#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
-#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
-#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
-#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
-#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
-#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
-#define __DBGMCU_CLK_ENABLE     __HAL_RCC_DBGMCU_CLK_ENABLE
-#define __DBGMCU_CLK_DISABLE     __HAL_RCC_DBGMCU_CLK_DISABLE
-#define __DBGMCU_FORCE_RESET    __HAL_RCC_DBGMCU_FORCE_RESET
-#define __DBGMCU_RELEASE_RESET  __HAL_RCC_DBGMCU_RELEASE_RESET
-#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
-#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
-#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
-#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
-#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
-#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
-#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
-#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
-#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
-#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
-#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
-#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
-#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
-#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
-#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
-#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
-#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
-#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
-#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
-#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
-#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
-#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
-#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
-#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
-#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
-#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
-#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
-#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
-#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
-#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
-#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
-#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
-#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
-#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
-#define __FLITF_CLK_DISABLE       __HAL_RCC_FLITF_CLK_DISABLE
-#define __FLITF_CLK_ENABLE        __HAL_RCC_FLITF_CLK_ENABLE
-#define __FLITF_FORCE_RESET       __HAL_RCC_FLITF_FORCE_RESET
-#define __FLITF_RELEASE_RESET     __HAL_RCC_FLITF_RELEASE_RESET
-#define __FLITF_CLK_SLEEP_ENABLE  __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
-#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
-#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
-#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
-#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
-#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
-#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
-#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
-#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
-#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
-#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
-#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
-#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
-#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
-#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
-#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
-#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
-#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
-#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
-#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
-#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
-#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
-#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
-#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
-#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
-#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
-#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
-#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
-#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
-#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
-#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
-#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
-#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
-#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
-#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
-#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
-#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
-#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
-#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
-#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
-#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
-#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
-#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
-#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
-#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
-#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
-#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
-#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
-#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
-#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
-#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
-#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
-#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
-#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
-#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
-#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
-#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
-#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
-#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
-#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
-#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
-#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
-#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
-#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
-#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
-#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
-#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
-#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
-#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
-#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
-#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
-#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
-#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
-#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
-#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
-#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
-#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
-#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
-#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
-#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
-#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
-#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
-#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
-#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
-#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
-#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
-#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
-#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
-#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
-#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
-#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
-#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
-#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
-#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
-#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
-#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
-#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
-#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
-#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
-#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
-#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
-#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
-#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
-#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
-#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
-#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
-#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
-#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
-#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
-#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
-#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
-#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
-#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
-#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
-#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
-#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
-#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
-#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
-#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
-#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
-#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
-#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
-#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
-#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
-#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
-#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
-#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
-#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
-#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
-#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
-#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
-#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
-#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
-#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
-#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
-#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
-#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
-#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
-#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
-#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
-#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
-#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
-#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
-#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
-#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
-#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
-#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
-#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
-#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
-#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
-#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
-#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
-#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
-#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
-#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
-#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
-#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
-#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
-#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
-#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
-#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
-#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
-#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
-#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
-#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
-#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
-#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
-#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
-#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
-#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
-#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
-#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
-#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
-#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
-#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
-#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
-#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
-#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
-#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
-#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
-#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
-#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
-#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
-#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
-#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
-#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
-#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
-#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
-#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
-#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
-#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
-#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
-#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
-#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
-#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
-#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
-#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
-#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
-#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
-#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
-#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
-#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
-#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
-#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
-#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
-#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
-#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
-#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
-#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
-#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
-#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
-#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
-#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
-#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
-#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
-#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
-#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
-#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
-#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
-#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
-#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
-#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
-#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
-#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
-#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
-#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
-#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
-#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
-#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
-#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
-#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
-#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
-#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
-#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
-#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
-#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
-#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
-#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
-#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
-#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
-#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
-#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
-#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
-#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
-#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
-#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
-#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
-#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
-#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
-#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
-#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
-#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
-#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
-#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
-#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
-#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
-#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
-#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
-#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
-#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
-#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
-#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
-#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
-#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
-#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
-#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
-#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
-#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
-#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
-#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
-#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
-#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
-#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
-#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
-#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
-#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
-#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
-#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
-#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
-#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
-#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
-#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
-#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
-#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
-#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
-#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
-#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
-#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
-#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
-#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
-#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
-#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
-#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
-#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
-#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
-#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
-#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
-#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
-#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
-#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
-#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
-#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
-#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
-#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
-#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
-#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
-#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
-#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
-#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
-#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
-#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
-#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
-#define __USART4_CLK_DISABLE        __HAL_RCC_USART4_CLK_DISABLE
-#define __USART4_CLK_ENABLE         __HAL_RCC_USART4_CLK_ENABLE
-#define __USART4_CLK_SLEEP_ENABLE   __HAL_RCC_USART4_CLK_SLEEP_ENABLE
-#define __USART4_CLK_SLEEP_DISABLE  __HAL_RCC_USART4_CLK_SLEEP_DISABLE 
-#define __USART4_FORCE_RESET        __HAL_RCC_USART4_FORCE_RESET
-#define __USART4_RELEASE_RESET      __HAL_RCC_USART4_RELEASE_RESET
-#define __USART5_CLK_DISABLE        __HAL_RCC_USART5_CLK_DISABLE
-#define __USART5_CLK_ENABLE         __HAL_RCC_USART5_CLK_ENABLE
-#define __USART5_CLK_SLEEP_ENABLE   __HAL_RCC_USART5_CLK_SLEEP_ENABLE
-#define __USART5_CLK_SLEEP_DISABLE  __HAL_RCC_USART5_CLK_SLEEP_DISABLE 
-#define __USART5_FORCE_RESET        __HAL_RCC_USART5_FORCE_RESET
-#define __USART5_RELEASE_RESET      __HAL_RCC_USART5_RELEASE_RESET
-#define __USART7_CLK_DISABLE        __HAL_RCC_USART7_CLK_DISABLE
-#define __USART7_CLK_ENABLE         __HAL_RCC_USART7_CLK_ENABLE
-#define __USART7_FORCE_RESET        __HAL_RCC_USART7_FORCE_RESET
-#define __USART7_RELEASE_RESET      __HAL_RCC_USART7_RELEASE_RESET
-#define __USART8_CLK_DISABLE        __HAL_RCC_USART8_CLK_DISABLE
-#define __USART8_CLK_ENABLE         __HAL_RCC_USART8_CLK_ENABLE
-#define __USART8_FORCE_RESET        __HAL_RCC_USART8_FORCE_RESET
-#define __USART8_RELEASE_RESET      __HAL_RCC_USART8_RELEASE_RESET
-#define __USB_CLK_DISABLE         __HAL_RCC_USB_CLK_DISABLE
-#define __USB_CLK_ENABLE          __HAL_RCC_USB_CLK_ENABLE
-#define __USB_FORCE_RESET         __HAL_RCC_USB_FORCE_RESET
-#define __USB_CLK_SLEEP_ENABLE    __HAL_RCC_USB_CLK_SLEEP_ENABLE
-#define __USB_CLK_SLEEP_DISABLE   __HAL_RCC_USB_CLK_SLEEP_DISABLE
-#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
-#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
-#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
-#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
-#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
-#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
-#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
-#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
-#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
-#define __TIM21_CLK_ENABLE   __HAL_RCC_TIM21_CLK_ENABLE
-#define __TIM21_CLK_DISABLE   __HAL_RCC_TIM21_CLK_DISABLE
-#define __TIM21_FORCE_RESET   __HAL_RCC_TIM21_FORCE_RESET
-#define __TIM21_RELEASE_RESET  __HAL_RCC_TIM21_RELEASE_RESET
-#define __TIM21_CLK_SLEEP_ENABLE   __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
-#define __TIM21_CLK_SLEEP_DISABLE   __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
-#define __TIM22_CLK_ENABLE   __HAL_RCC_TIM22_CLK_ENABLE
-#define __TIM22_CLK_DISABLE   __HAL_RCC_TIM22_CLK_DISABLE
-#define __TIM22_FORCE_RESET   __HAL_RCC_TIM22_FORCE_RESET
-#define __TIM22_RELEASE_RESET  __HAL_RCC_TIM22_RELEASE_RESET
-#define __TIM22_CLK_SLEEP_ENABLE   __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
-#define __TIM22_CLK_SLEEP_DISABLE   __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
-#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
-#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
-#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
-#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
-#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
-#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
-#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
-#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
-
-#define __USB_OTG_FS_FORCE_RESET  __HAL_RCC_USB_OTG_FS_FORCE_RESET
-#define __USB_OTG_FS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
-#define __USB_OTG_FS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
-#define __USB_OTG_FS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
-#define __USB_OTG_HS_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_DISABLE
-#define __USB_OTG_HS_CLK_ENABLE          __HAL_RCC_USB_OTG_HS_CLK_ENABLE
-#define __USB_OTG_HS_ULPI_CLK_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
-#define __USB_OTG_HS_ULPI_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE  
-#define __TIM9_CLK_SLEEP_ENABLE          __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
-#define __TIM9_CLK_SLEEP_DISABLE  __HAL_RCC_TIM9_CLK_SLEEP_DISABLE  
-#define __TIM10_CLK_SLEEP_ENABLE  __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
-#define __TIM10_CLK_SLEEP_DISABLE  __HAL_RCC_TIM10_CLK_SLEEP_DISABLE  
-#define __TIM11_CLK_SLEEP_ENABLE  __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
-#define __TIM11_CLK_SLEEP_DISABLE  __HAL_RCC_TIM11_CLK_SLEEP_DISABLE  
-#define __ETHMACPTP_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
-#define __ETHMACPTP_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
-#define __ETHMACPTP_CLK_ENABLE          __HAL_RCC_ETHMACPTP_CLK_ENABLE
-#define __ETHMACPTP_CLK_DISABLE          __HAL_RCC_ETHMACPTP_CLK_DISABLE  
-#define __HASH_CLK_ENABLE          __HAL_RCC_HASH_CLK_ENABLE
-#define __HASH_FORCE_RESET          __HAL_RCC_HASH_FORCE_RESET
-#define __HASH_RELEASE_RESET          __HAL_RCC_HASH_RELEASE_RESET
-#define __HASH_CLK_SLEEP_ENABLE          __HAL_RCC_HASH_CLK_SLEEP_ENABLE
-#define __HASH_CLK_SLEEP_DISABLE  __HAL_RCC_HASH_CLK_SLEEP_DISABLE
-#define __HASH_CLK_DISABLE            __HAL_RCC_HASH_CLK_DISABLE  
-#define __SPI5_CLK_ENABLE          __HAL_RCC_SPI5_CLK_ENABLE
-#define __SPI5_CLK_DISABLE              __HAL_RCC_SPI5_CLK_DISABLE
-#define __SPI5_FORCE_RESET          __HAL_RCC_SPI5_FORCE_RESET
-#define __SPI5_RELEASE_RESET          __HAL_RCC_SPI5_RELEASE_RESET
-#define __SPI5_CLK_SLEEP_ENABLE          __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
-#define __SPI5_CLK_SLEEP_DISABLE  __HAL_RCC_SPI5_CLK_SLEEP_DISABLE  
-#define __SPI6_CLK_ENABLE          __HAL_RCC_SPI6_CLK_ENABLE
-#define __SPI6_CLK_DISABLE          __HAL_RCC_SPI6_CLK_DISABLE
-#define __SPI6_FORCE_RESET          __HAL_RCC_SPI6_FORCE_RESET
-#define __SPI6_RELEASE_RESET         __HAL_RCC_SPI6_RELEASE_RESET
-#define __SPI6_CLK_SLEEP_ENABLE          __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
-#define __SPI6_CLK_SLEEP_DISABLE  __HAL_RCC_SPI6_CLK_SLEEP_DISABLE  
-#define __LTDC_CLK_ENABLE          __HAL_RCC_LTDC_CLK_ENABLE
-#define __LTDC_CLK_DISABLE          __HAL_RCC_LTDC_CLK_DISABLE
-#define __LTDC_FORCE_RESET          __HAL_RCC_LTDC_FORCE_RESET
-#define __LTDC_RELEASE_RESET          __HAL_RCC_LTDC_RELEASE_RESET
-#define __LTDC_CLK_SLEEP_ENABLE          __HAL_RCC_LTDC_CLK_SLEEP_ENABLE  
-#define __ETHMAC_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
-#define __ETHMAC_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE  
-#define __ETHMACTX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
-#define __ETHMACTX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE  
-#define __ETHMACRX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
-#define __ETHMACRX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE  
-#define __TIM12_CLK_SLEEP_ENABLE  __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
-#define __TIM12_CLK_SLEEP_DISABLE  __HAL_RCC_TIM12_CLK_SLEEP_DISABLE  
-#define __TIM13_CLK_SLEEP_ENABLE  __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
-#define __TIM13_CLK_SLEEP_DISABLE  __HAL_RCC_TIM13_CLK_SLEEP_DISABLE  
-#define __TIM14_CLK_SLEEP_ENABLE  __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
-#define __TIM14_CLK_SLEEP_DISABLE  __HAL_RCC_TIM14_CLK_SLEEP_DISABLE  
-#define __BKPSRAM_CLK_ENABLE          __HAL_RCC_BKPSRAM_CLK_ENABLE
-#define __BKPSRAM_CLK_DISABLE          __HAL_RCC_BKPSRAM_CLK_DISABLE
-#define __BKPSRAM_CLK_SLEEP_ENABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
-#define __BKPSRAM_CLK_SLEEP_DISABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE  
-#define __CCMDATARAMEN_CLK_ENABLE  __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
-#define __CCMDATARAMEN_CLK_DISABLE  __HAL_RCC_CCMDATARAMEN_CLK_DISABLE  
-#define __USART6_CLK_ENABLE          __HAL_RCC_USART6_CLK_ENABLE
-#define __USART6_CLK_DISABLE          __HAL_RCC_USART6_CLK_DISABLE
-#define __USART6_FORCE_RESET        __HAL_RCC_USART6_FORCE_RESET
-#define __USART6_RELEASE_RESET        __HAL_RCC_USART6_RELEASE_RESET
-#define __USART6_CLK_SLEEP_ENABLE  __HAL_RCC_USART6_CLK_SLEEP_ENABLE
-#define __USART6_CLK_SLEEP_DISABLE  __HAL_RCC_USART6_CLK_SLEEP_DISABLE  
-#define __SPI4_CLK_ENABLE          __HAL_RCC_SPI4_CLK_ENABLE
-#define __SPI4_CLK_DISABLE          __HAL_RCC_SPI4_CLK_DISABLE
-#define __SPI4_FORCE_RESET          __HAL_RCC_SPI4_FORCE_RESET
-#define __SPI4_RELEASE_RESET        __HAL_RCC_SPI4_RELEASE_RESET
-#define __SPI4_CLK_SLEEP_ENABLE   __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
-#define __SPI4_CLK_SLEEP_DISABLE  __HAL_RCC_SPI4_CLK_SLEEP_DISABLE  
-#define __GPIOI_CLK_ENABLE          __HAL_RCC_GPIOI_CLK_ENABLE
-#define __GPIOI_CLK_DISABLE          __HAL_RCC_GPIOI_CLK_DISABLE
-#define __GPIOI_FORCE_RESET          __HAL_RCC_GPIOI_FORCE_RESET
-#define __GPIOI_RELEASE_RESET          __HAL_RCC_GPIOI_RELEASE_RESET
-#define __GPIOI_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
-#define __GPIOI_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE  
-#define __GPIOJ_CLK_ENABLE          __HAL_RCC_GPIOJ_CLK_ENABLE
-#define __GPIOJ_CLK_DISABLE          __HAL_RCC_GPIOJ_CLK_DISABLE
-#define __GPIOJ_FORCE_RESET         __HAL_RCC_GPIOJ_FORCE_RESET
-#define __GPIOJ_RELEASE_RESET          __HAL_RCC_GPIOJ_RELEASE_RESET
-#define __GPIOJ_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
-#define __GPIOJ_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE  
-#define __GPIOK_CLK_ENABLE          __HAL_RCC_GPIOK_CLK_ENABLE
-#define __GPIOK_CLK_DISABLE          __HAL_RCC_GPIOK_CLK_DISABLE
-#define __GPIOK_RELEASE_RESET          __HAL_RCC_GPIOK_RELEASE_RESET
-#define __GPIOK_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
-#define __GPIOK_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE  
-#define __ETH_CLK_ENABLE          __HAL_RCC_ETH_CLK_ENABLE
-#define __ETH_CLK_DISABLE          __HAL_RCC_ETH_CLK_DISABLE  
-#define __DCMI_CLK_ENABLE          __HAL_RCC_DCMI_CLK_ENABLE
-#define __DCMI_CLK_DISABLE          __HAL_RCC_DCMI_CLK_DISABLE
-#define __DCMI_FORCE_RESET          __HAL_RCC_DCMI_FORCE_RESET
-#define __DCMI_RELEASE_RESET          __HAL_RCC_DCMI_RELEASE_RESET
-#define __DCMI_CLK_SLEEP_ENABLE   __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
-#define __DCMI_CLK_SLEEP_DISABLE  __HAL_RCC_DCMI_CLK_SLEEP_DISABLE  
-#define __UART7_CLK_ENABLE          __HAL_RCC_UART7_CLK_ENABLE
-#define __UART7_CLK_DISABLE          __HAL_RCC_UART7_CLK_DISABLE
-#define __UART7_RELEASE_RESET       __HAL_RCC_UART7_RELEASE_RESET
-#define __UART7_FORCE_RESET       __HAL_RCC_UART7_FORCE_RESET
-#define __UART7_CLK_SLEEP_ENABLE  __HAL_RCC_UART7_CLK_SLEEP_ENABLE
-#define __UART7_CLK_SLEEP_DISABLE  __HAL_RCC_UART7_CLK_SLEEP_DISABLE  
-#define __UART8_CLK_ENABLE          __HAL_RCC_UART8_CLK_ENABLE
-#define __UART8_CLK_DISABLE          __HAL_RCC_UART8_CLK_DISABLE
-#define __UART8_FORCE_RESET          __HAL_RCC_UART8_FORCE_RESET
-#define __UART8_RELEASE_RESET          __HAL_RCC_UART8_RELEASE_RESET
-#define __UART8_CLK_SLEEP_ENABLE  __HAL_RCC_UART8_CLK_SLEEP_ENABLE
-#define __UART8_CLK_SLEEP_DISABLE  __HAL_RCC_UART8_CLK_SLEEP_DISABLE  
-#define __OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
-#define __OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
-#define __OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
-#define __OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET  
-#define __OTGHSULPI_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
-#define __OTGHSULPI_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
-#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
-#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
-#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
-#define __HAL_RCC_OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
-#define __HAL_RCC_OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET  
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE      __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE     __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE 
-#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED  __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED   
-#define __CRYP_FORCE_RESET             __HAL_RCC_CRYP_FORCE_RESET  
-#define __SRAM3_CLK_SLEEP_ENABLE       __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE  
-#define __CAN2_CLK_SLEEP_ENABLE        __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
-#define __CAN2_CLK_SLEEP_DISABLE       __HAL_RCC_CAN2_CLK_SLEEP_DISABLE  
-#define __DAC_CLK_SLEEP_ENABLE         __HAL_RCC_DAC_CLK_SLEEP_ENABLE
-#define __DAC_CLK_SLEEP_DISABLE        __HAL_RCC_DAC_CLK_SLEEP_DISABLE  
-#define __ADC2_CLK_SLEEP_ENABLE        __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
-#define __ADC2_CLK_SLEEP_DISABLE       __HAL_RCC_ADC2_CLK_SLEEP_DISABLE  
-#define __ADC3_CLK_SLEEP_ENABLE        __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
-#define __ADC3_CLK_SLEEP_DISABLE       __HAL_RCC_ADC3_CLK_SLEEP_DISABLE  
-#define __FSMC_FORCE_RESET             __HAL_RCC_FSMC_FORCE_RESET
-#define __FSMC_RELEASE_RESET           __HAL_RCC_FSMC_RELEASE_RESET
-#define __FSMC_CLK_SLEEP_ENABLE        __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
-#define __FSMC_CLK_SLEEP_DISABLE       __HAL_RCC_FSMC_CLK_SLEEP_DISABLE  
-#define __SDIO_FORCE_RESET             __HAL_RCC_SDIO_FORCE_RESET
-#define __SDIO_RELEASE_RESET           __HAL_RCC_SDIO_RELEASE_RESET
-#define __SDIO_CLK_SLEEP_DISABLE       __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
-#define __SDIO_CLK_SLEEP_ENABLE        __HAL_RCC_SDIO_CLK_SLEEP_ENABLE  
-#define __DMA2D_CLK_ENABLE             __HAL_RCC_DMA2D_CLK_ENABLE
-#define __DMA2D_CLK_DISABLE            __HAL_RCC_DMA2D_CLK_DISABLE
-#define __DMA2D_FORCE_RESET            __HAL_RCC_DMA2D_FORCE_RESET
-#define __DMA2D_RELEASE_RESET          __HAL_RCC_DMA2D_RELEASE_RESET
-#define __DMA2D_CLK_SLEEP_ENABLE       __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
-#define __DMA2D_CLK_SLEEP_DISABLE      __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
-
-/* alias define maintained for legacy */
-#define __HAL_RCC_OTGFS_FORCE_RESET    __HAL_RCC_USB_OTG_FS_FORCE_RESET
-#define __HAL_RCC_OTGFS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
-
-#define __ADC12_CLK_ENABLE          __HAL_RCC_ADC12_CLK_ENABLE
-#define __ADC12_CLK_DISABLE         __HAL_RCC_ADC12_CLK_DISABLE
-#define __ADC34_CLK_ENABLE          __HAL_RCC_ADC34_CLK_ENABLE
-#define __ADC34_CLK_DISABLE         __HAL_RCC_ADC34_CLK_DISABLE
-#define __ADC12_CLK_ENABLE          __HAL_RCC_ADC12_CLK_ENABLE
-#define __ADC12_CLK_DISABLE         __HAL_RCC_ADC12_CLK_DISABLE
-#define __DAC2_CLK_ENABLE           __HAL_RCC_DAC2_CLK_ENABLE
-#define __DAC2_CLK_DISABLE          __HAL_RCC_DAC2_CLK_DISABLE
-#define __TIM18_CLK_ENABLE          __HAL_RCC_TIM18_CLK_ENABLE
-#define __TIM18_CLK_DISABLE         __HAL_RCC_TIM18_CLK_DISABLE
-#define __TIM19_CLK_ENABLE          __HAL_RCC_TIM19_CLK_ENABLE
-#define __TIM19_CLK_DISABLE         __HAL_RCC_TIM19_CLK_DISABLE
-#define __TIM20_CLK_ENABLE          __HAL_RCC_TIM20_CLK_ENABLE
-#define __TIM20_CLK_DISABLE         __HAL_RCC_TIM20_CLK_DISABLE
-#define __HRTIM1_CLK_ENABLE         __HAL_RCC_HRTIM1_CLK_ENABLE
-#define __HRTIM1_CLK_DISABLE        __HAL_RCC_HRTIM1_CLK_DISABLE
-#define __SDADC1_CLK_ENABLE         __HAL_RCC_SDADC1_CLK_ENABLE
-#define __SDADC2_CLK_ENABLE         __HAL_RCC_SDADC2_CLK_ENABLE
-#define __SDADC3_CLK_ENABLE         __HAL_RCC_SDADC3_CLK_ENABLE
-#define __SDADC1_CLK_DISABLE        __HAL_RCC_SDADC1_CLK_DISABLE
-#define __SDADC2_CLK_DISABLE        __HAL_RCC_SDADC2_CLK_DISABLE
-#define __SDADC3_CLK_DISABLE        __HAL_RCC_SDADC3_CLK_DISABLE
-
-#define __ADC12_FORCE_RESET         __HAL_RCC_ADC12_FORCE_RESET
-#define __ADC12_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET
-#define __ADC34_FORCE_RESET         __HAL_RCC_ADC34_FORCE_RESET
-#define __ADC34_RELEASE_RESET       __HAL_RCC_ADC34_RELEASE_RESET
-#define __ADC12_FORCE_RESET         __HAL_RCC_ADC12_FORCE_RESET
-#define __ADC12_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET
-#define __DAC2_FORCE_RESET          __HAL_RCC_DAC2_FORCE_RESET
-#define __DAC2_RELEASE_RESET        __HAL_RCC_DAC2_RELEASE_RESET
-#define __TIM18_FORCE_RESET         __HAL_RCC_TIM18_FORCE_RESET
-#define __TIM18_RELEASE_RESET       __HAL_RCC_TIM18_RELEASE_RESET
-#define __TIM19_FORCE_RESET         __HAL_RCC_TIM19_FORCE_RESET
-#define __TIM19_RELEASE_RESET       __HAL_RCC_TIM19_RELEASE_RESET
-#define __TIM20_FORCE_RESET         __HAL_RCC_TIM20_FORCE_RESET
-#define __TIM20_RELEASE_RESET       __HAL_RCC_TIM20_RELEASE_RESET
-#define __HRTIM1_FORCE_RESET        __HAL_RCC_HRTIM1_FORCE_RESET
-#define __HRTIM1_RELEASE_RESET      __HAL_RCC_HRTIM1_RELEASE_RESET
-#define __SDADC1_FORCE_RESET        __HAL_RCC_SDADC1_FORCE_RESET
-#define __SDADC2_FORCE_RESET        __HAL_RCC_SDADC2_FORCE_RESET
-#define __SDADC3_FORCE_RESET        __HAL_RCC_SDADC3_FORCE_RESET
-#define __SDADC1_RELEASE_RESET      __HAL_RCC_SDADC1_RELEASE_RESET
-#define __SDADC2_RELEASE_RESET      __HAL_RCC_SDADC2_RELEASE_RESET
-#define __SDADC3_RELEASE_RESET      __HAL_RCC_SDADC3_RELEASE_RESET
-
-#define __ADC1_IS_CLK_ENABLED       __HAL_RCC_ADC1_IS_CLK_ENABLED
-#define __ADC1_IS_CLK_DISABLED      __HAL_RCC_ADC1_IS_CLK_DISABLED
-#define __ADC12_IS_CLK_ENABLED      __HAL_RCC_ADC12_IS_CLK_ENABLED
-#define __ADC12_IS_CLK_DISABLED     __HAL_RCC_ADC12_IS_CLK_DISABLED
-#define __ADC34_IS_CLK_ENABLED      __HAL_RCC_ADC34_IS_CLK_ENABLED
-#define __ADC34_IS_CLK_DISABLED     __HAL_RCC_ADC34_IS_CLK_DISABLED
-#define __CEC_IS_CLK_ENABLED        __HAL_RCC_CEC_IS_CLK_ENABLED
-#define __CEC_IS_CLK_DISABLED       __HAL_RCC_CEC_IS_CLK_DISABLED
-#define __CRC_IS_CLK_ENABLED        __HAL_RCC_CRC_IS_CLK_ENABLED
-#define __CRC_IS_CLK_DISABLED       __HAL_RCC_CRC_IS_CLK_DISABLED
-#define __DAC1_IS_CLK_ENABLED       __HAL_RCC_DAC1_IS_CLK_ENABLED
-#define __DAC1_IS_CLK_DISABLED      __HAL_RCC_DAC1_IS_CLK_DISABLED
-#define __DAC2_IS_CLK_ENABLED       __HAL_RCC_DAC2_IS_CLK_ENABLED
-#define __DAC2_IS_CLK_DISABLED      __HAL_RCC_DAC2_IS_CLK_DISABLED
-#define __DMA1_IS_CLK_ENABLED       __HAL_RCC_DMA1_IS_CLK_ENABLED
-#define __DMA1_IS_CLK_DISABLED      __HAL_RCC_DMA1_IS_CLK_DISABLED
-#define __DMA2_IS_CLK_ENABLED       __HAL_RCC_DMA2_IS_CLK_ENABLED
-#define __DMA2_IS_CLK_DISABLED      __HAL_RCC_DMA2_IS_CLK_DISABLED
-#define __FLITF_IS_CLK_ENABLED      __HAL_RCC_FLITF_IS_CLK_ENABLED
-#define __FLITF_IS_CLK_DISABLED     __HAL_RCC_FLITF_IS_CLK_DISABLED
-#define __FMC_IS_CLK_ENABLED        __HAL_RCC_FMC_IS_CLK_ENABLED
-#define __FMC_IS_CLK_DISABLED       __HAL_RCC_FMC_IS_CLK_DISABLED
-#define __GPIOA_IS_CLK_ENABLED      __HAL_RCC_GPIOA_IS_CLK_ENABLED
-#define __GPIOA_IS_CLK_DISABLED     __HAL_RCC_GPIOA_IS_CLK_DISABLED
-#define __GPIOB_IS_CLK_ENABLED      __HAL_RCC_GPIOB_IS_CLK_ENABLED
-#define __GPIOB_IS_CLK_DISABLED     __HAL_RCC_GPIOB_IS_CLK_DISABLED
-#define __GPIOC_IS_CLK_ENABLED      __HAL_RCC_GPIOC_IS_CLK_ENABLED
-#define __GPIOC_IS_CLK_DISABLED     __HAL_RCC_GPIOC_IS_CLK_DISABLED
-#define __GPIOD_IS_CLK_ENABLED      __HAL_RCC_GPIOD_IS_CLK_ENABLED
-#define __GPIOD_IS_CLK_DISABLED     __HAL_RCC_GPIOD_IS_CLK_DISABLED
-#define __GPIOE_IS_CLK_ENABLED      __HAL_RCC_GPIOE_IS_CLK_ENABLED
-#define __GPIOE_IS_CLK_DISABLED     __HAL_RCC_GPIOE_IS_CLK_DISABLED
-#define __GPIOF_IS_CLK_ENABLED      __HAL_RCC_GPIOF_IS_CLK_ENABLED
-#define __GPIOF_IS_CLK_DISABLED     __HAL_RCC_GPIOF_IS_CLK_DISABLED
-#define __GPIOG_IS_CLK_ENABLED      __HAL_RCC_GPIOG_IS_CLK_ENABLED
-#define __GPIOG_IS_CLK_DISABLED     __HAL_RCC_GPIOG_IS_CLK_DISABLED
-#define __GPIOH_IS_CLK_ENABLED      __HAL_RCC_GPIOH_IS_CLK_ENABLED
-#define __GPIOH_IS_CLK_DISABLED     __HAL_RCC_GPIOH_IS_CLK_DISABLED
-#define __HRTIM1_IS_CLK_ENABLED     __HAL_RCC_HRTIM1_IS_CLK_ENABLED
-#define __HRTIM1_IS_CLK_DISABLED    __HAL_RCC_HRTIM1_IS_CLK_DISABLED
-#define __I2C1_IS_CLK_ENABLED       __HAL_RCC_I2C1_IS_CLK_ENABLED
-#define __I2C1_IS_CLK_DISABLED      __HAL_RCC_I2C1_IS_CLK_DISABLED
-#define __I2C2_IS_CLK_ENABLED       __HAL_RCC_I2C2_IS_CLK_ENABLED
-#define __I2C2_IS_CLK_DISABLED      __HAL_RCC_I2C2_IS_CLK_DISABLED
-#define __I2C3_IS_CLK_ENABLED       __HAL_RCC_I2C3_IS_CLK_ENABLED
-#define __I2C3_IS_CLK_DISABLED      __HAL_RCC_I2C3_IS_CLK_DISABLED
-#define __PWR_IS_CLK_ENABLED        __HAL_RCC_PWR_IS_CLK_ENABLED
-#define __PWR_IS_CLK_DISABLED       __HAL_RCC_PWR_IS_CLK_DISABLED
-#define __SYSCFG_IS_CLK_ENABLED     __HAL_RCC_SYSCFG_IS_CLK_ENABLED
-#define __SYSCFG_IS_CLK_DISABLED    __HAL_RCC_SYSCFG_IS_CLK_DISABLED
-#define __SPI1_IS_CLK_ENABLED       __HAL_RCC_SPI1_IS_CLK_ENABLED
-#define __SPI1_IS_CLK_DISABLED      __HAL_RCC_SPI1_IS_CLK_DISABLED
-#define __SPI2_IS_CLK_ENABLED       __HAL_RCC_SPI2_IS_CLK_ENABLED
-#define __SPI2_IS_CLK_DISABLED      __HAL_RCC_SPI2_IS_CLK_DISABLED
-#define __SPI3_IS_CLK_ENABLED       __HAL_RCC_SPI3_IS_CLK_ENABLED
-#define __SPI3_IS_CLK_DISABLED      __HAL_RCC_SPI3_IS_CLK_DISABLED
-#define __SPI4_IS_CLK_ENABLED       __HAL_RCC_SPI4_IS_CLK_ENABLED
-#define __SPI4_IS_CLK_DISABLED      __HAL_RCC_SPI4_IS_CLK_DISABLED
-#define __SDADC1_IS_CLK_ENABLED     __HAL_RCC_SDADC1_IS_CLK_ENABLED
-#define __SDADC1_IS_CLK_DISABLED    __HAL_RCC_SDADC1_IS_CLK_DISABLED
-#define __SDADC2_IS_CLK_ENABLED     __HAL_RCC_SDADC2_IS_CLK_ENABLED
-#define __SDADC2_IS_CLK_DISABLED    __HAL_RCC_SDADC2_IS_CLK_DISABLED
-#define __SDADC3_IS_CLK_ENABLED     __HAL_RCC_SDADC3_IS_CLK_ENABLED
-#define __SDADC3_IS_CLK_DISABLED    __HAL_RCC_SDADC3_IS_CLK_DISABLED
-#define __SRAM_IS_CLK_ENABLED       __HAL_RCC_SRAM_IS_CLK_ENABLED
-#define __SRAM_IS_CLK_DISABLED      __HAL_RCC_SRAM_IS_CLK_DISABLED
-#define __TIM1_IS_CLK_ENABLED       __HAL_RCC_TIM1_IS_CLK_ENABLED
-#define __TIM1_IS_CLK_DISABLED      __HAL_RCC_TIM1_IS_CLK_DISABLED
-#define __TIM2_IS_CLK_ENABLED       __HAL_RCC_TIM2_IS_CLK_ENABLED
-#define __TIM2_IS_CLK_DISABLED      __HAL_RCC_TIM2_IS_CLK_DISABLED
-#define __TIM3_IS_CLK_ENABLED       __HAL_RCC_TIM3_IS_CLK_ENABLED
-#define __TIM3_IS_CLK_DISABLED      __HAL_RCC_TIM3_IS_CLK_DISABLED
-#define __TIM4_IS_CLK_ENABLED       __HAL_RCC_TIM4_IS_CLK_ENABLED
-#define __TIM4_IS_CLK_DISABLED      __HAL_RCC_TIM4_IS_CLK_DISABLED
-#define __TIM5_IS_CLK_ENABLED       __HAL_RCC_TIM5_IS_CLK_ENABLED
-#define __TIM5_IS_CLK_DISABLED      __HAL_RCC_TIM5_IS_CLK_DISABLED
-#define __TIM6_IS_CLK_ENABLED       __HAL_RCC_TIM6_IS_CLK_ENABLED
-#define __TIM6_IS_CLK_DISABLED      __HAL_RCC_TIM6_IS_CLK_DISABLED
-#define __TIM7_IS_CLK_ENABLED       __HAL_RCC_TIM7_IS_CLK_ENABLED
-#define __TIM7_IS_CLK_DISABLED      __HAL_RCC_TIM7_IS_CLK_DISABLED
-#define __TIM8_IS_CLK_ENABLED       __HAL_RCC_TIM8_IS_CLK_ENABLED
-#define __TIM8_IS_CLK_DISABLED      __HAL_RCC_TIM8_IS_CLK_DISABLED
-#define __TIM12_IS_CLK_ENABLED      __HAL_RCC_TIM12_IS_CLK_ENABLED
-#define __TIM12_IS_CLK_DISABLED     __HAL_RCC_TIM12_IS_CLK_DISABLED
-#define __TIM13_IS_CLK_ENABLED      __HAL_RCC_TIM13_IS_CLK_ENABLED
-#define __TIM13_IS_CLK_DISABLED     __HAL_RCC_TIM13_IS_CLK_DISABLED
-#define __TIM14_IS_CLK_ENABLED      __HAL_RCC_TIM14_IS_CLK_ENABLED
-#define __TIM14_IS_CLK_DISABLED     __HAL_RCC_TIM14_IS_CLK_DISABLED
-#define __TIM15_IS_CLK_ENABLED      __HAL_RCC_TIM15_IS_CLK_ENABLED
-#define __TIM15_IS_CLK_DISABLED     __HAL_RCC_TIM15_IS_CLK_DISABLED
-#define __TIM16_IS_CLK_ENABLED      __HAL_RCC_TIM16_IS_CLK_ENABLED
-#define __TIM16_IS_CLK_DISABLED     __HAL_RCC_TIM16_IS_CLK_DISABLED
-#define __TIM17_IS_CLK_ENABLED      __HAL_RCC_TIM17_IS_CLK_ENABLED
-#define __TIM17_IS_CLK_DISABLED     __HAL_RCC_TIM17_IS_CLK_DISABLED
-#define __TIM18_IS_CLK_ENABLED      __HAL_RCC_TIM18_IS_CLK_ENABLED
-#define __TIM18_IS_CLK_DISABLED     __HAL_RCC_TIM18_IS_CLK_DISABLED
-#define __TIM19_IS_CLK_ENABLED      __HAL_RCC_TIM19_IS_CLK_ENABLED
-#define __TIM19_IS_CLK_DISABLED     __HAL_RCC_TIM19_IS_CLK_DISABLED
-#define __TIM20_IS_CLK_ENABLED      __HAL_RCC_TIM20_IS_CLK_ENABLED
-#define __TIM20_IS_CLK_DISABLED     __HAL_RCC_TIM20_IS_CLK_DISABLED
-#define __TSC_IS_CLK_ENABLED        __HAL_RCC_TSC_IS_CLK_ENABLED
-#define __TSC_IS_CLK_DISABLED       __HAL_RCC_TSC_IS_CLK_DISABLED
-#define __UART4_IS_CLK_ENABLED      __HAL_RCC_UART4_IS_CLK_ENABLED
-#define __UART4_IS_CLK_DISABLED     __HAL_RCC_UART4_IS_CLK_DISABLED
-#define __UART5_IS_CLK_ENABLED      __HAL_RCC_UART5_IS_CLK_ENABLED
-#define __UART5_IS_CLK_DISABLED     __HAL_RCC_UART5_IS_CLK_DISABLED
-#define __USART1_IS_CLK_ENABLED     __HAL_RCC_USART1_IS_CLK_ENABLED
-#define __USART1_IS_CLK_DISABLED    __HAL_RCC_USART1_IS_CLK_DISABLED
-#define __USART2_IS_CLK_ENABLED     __HAL_RCC_USART2_IS_CLK_ENABLED
-#define __USART2_IS_CLK_DISABLED    __HAL_RCC_USART2_IS_CLK_DISABLED
-#define __USART3_IS_CLK_ENABLED     __HAL_RCC_USART3_IS_CLK_ENABLED
-#define __USART3_IS_CLK_DISABLED    __HAL_RCC_USART3_IS_CLK_DISABLED
-#define __USB_IS_CLK_ENABLED        __HAL_RCC_USB_IS_CLK_ENABLED
-#define __USB_IS_CLK_DISABLED       __HAL_RCC_USB_IS_CLK_DISABLED
-#define __WWDG_IS_CLK_ENABLED       __HAL_RCC_WWDG_IS_CLK_ENABLED
-#define __WWDG_IS_CLK_DISABLED      __HAL_RCC_WWDG_IS_CLK_DISABLED
-
-#if defined(STM32F4)
-#define __HAL_RCC_SDMMC1_FORCE_RESET       __HAL_RCC_SDIO_FORCE_RESET
-#define __HAL_RCC_SDMMC1_RELEASE_RESET     __HAL_RCC_SDIO_RELEASE_RESET
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE  __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
-#define __HAL_RCC_SDMMC1_CLK_ENABLE        __HAL_RCC_SDIO_CLK_ENABLE
-#define __HAL_RCC_SDMMC1_CLK_DISABLE       __HAL_RCC_SDIO_CLK_DISABLE
-#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED    __HAL_RCC_SDIO_IS_CLK_ENABLED
-#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED   __HAL_RCC_SDIO_IS_CLK_DISABLED
-#define Sdmmc1ClockSelection               SdioClockSelection
-#define RCC_PERIPHCLK_SDMMC1               RCC_PERIPHCLK_SDIO
-#define RCC_SDMMC1CLKSOURCE_CLK48          RCC_SDIOCLKSOURCE_CK48
-#define RCC_SDMMC1CLKSOURCE_SYSCLK         RCC_SDIOCLKSOURCE_SYSCLK
-#define __HAL_RCC_SDMMC1_CONFIG            __HAL_RCC_SDIO_CONFIG
-#define __HAL_RCC_GET_SDMMC1_SOURCE        __HAL_RCC_GET_SDIO_SOURCE
-#endif
-
-#if defined(STM32F7) || defined(STM32L4)
-#define __HAL_RCC_SDIO_FORCE_RESET         __HAL_RCC_SDMMC1_FORCE_RESET
-#define __HAL_RCC_SDIO_RELEASE_RESET       __HAL_RCC_SDMMC1_RELEASE_RESET
-#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE    __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
-#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE   __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
-#define __HAL_RCC_SDIO_CLK_ENABLE          __HAL_RCC_SDMMC1_CLK_ENABLE
-#define __HAL_RCC_SDIO_CLK_DISABLE         __HAL_RCC_SDMMC1_CLK_DISABLE
-#define __HAL_RCC_SDIO_IS_CLK_ENABLED      __HAL_RCC_SDMMC1_IS_CLK_ENABLED
-#define __HAL_RCC_SDIO_IS_CLK_DISABLED     __HAL_RCC_SDMMC1_IS_CLK_DISABLED
-#define SdioClockSelection                 Sdmmc1ClockSelection
-#define RCC_PERIPHCLK_SDIO                 RCC_PERIPHCLK_SDMMC1
-#define __HAL_RCC_SDIO_CONFIG              __HAL_RCC_SDMMC1_CONFIG
-#define __HAL_RCC_GET_SDIO_SOURCE          __HAL_RCC_GET_SDMMC1_SOURCE	
-#endif
-
-#if defined(STM32F7)
-#define RCC_SDIOCLKSOURCE_CK48             RCC_SDMMC1CLKSOURCE_CLK48
-#define RCC_SDIOCLKSOURCE_SYSCLK           RCC_SDMMC1CLKSOURCE_SYSCLK
-#endif
-
-#define __HAL_RCC_I2SCLK            __HAL_RCC_I2S_CONFIG
-#define __HAL_RCC_I2SCLK_CONFIG     __HAL_RCC_I2S_CONFIG
-
-#define __RCC_PLLSRC                RCC_GET_PLL_OSCSOURCE
-
-#define IS_RCC_MSIRANGE             IS_RCC_MSI_CLOCK_RANGE
-#define IS_RCC_RTCCLK_SOURCE        IS_RCC_RTCCLKSOURCE
-#define IS_RCC_SYSCLK_DIV           IS_RCC_HCLK
-#define IS_RCC_HCLK_DIV             IS_RCC_PCLK
-#define IS_RCC_PERIPHCLK            IS_RCC_PERIPHCLOCK
-
-#define RCC_IT_HSI14                RCC_IT_HSI14RDY
-
-#if defined(STM32L0)
-#define RCC_IT_LSECSS              RCC_IT_CSSLSE 
-#define RCC_IT_CSS                 RCC_IT_CSSHSE
-#endif
-
-#define IS_RCC_MCOSOURCE            IS_RCC_MCO1SOURCE
-#define __HAL_RCC_MCO_CONFIG        __HAL_RCC_MCO1_CONFIG
-#define RCC_MCO_NODIV               RCC_MCODIV_1
-#define RCC_MCO_DIV1                RCC_MCODIV_1
-#define RCC_MCO_DIV2                RCC_MCODIV_2
-#define RCC_MCO_DIV4                RCC_MCODIV_4
-#define RCC_MCO_DIV8                RCC_MCODIV_8
-#define RCC_MCO_DIV16               RCC_MCODIV_16
-#define RCC_MCO_DIV32               RCC_MCODIV_32
-#define RCC_MCO_DIV64               RCC_MCODIV_64
-#define RCC_MCO_DIV128              RCC_MCODIV_128
-#define RCC_MCOSOURCE_NONE          RCC_MCO1SOURCE_NOCLOCK
-#define RCC_MCOSOURCE_LSI           RCC_MCO1SOURCE_LSI
-#define RCC_MCOSOURCE_LSE           RCC_MCO1SOURCE_LSE
-#define RCC_MCOSOURCE_SYSCLK        RCC_MCO1SOURCE_SYSCLK
-#define RCC_MCOSOURCE_HSI           RCC_MCO1SOURCE_HSI
-#define RCC_MCOSOURCE_HSI14         RCC_MCO1SOURCE_HSI14
-#define RCC_MCOSOURCE_HSI48         RCC_MCO1SOURCE_HSI48
-#define RCC_MCOSOURCE_HSE           RCC_MCO1SOURCE_HSE
-#define RCC_MCOSOURCE_PLLCLK_DIV1   RCC_MCO1SOURCE_PLLCLK
-#define RCC_MCOSOURCE_PLLCLK_NODIV  RCC_MCO1SOURCE_PLLCLK
-#define RCC_MCOSOURCE_PLLCLK_DIV2   RCC_MCO1SOURCE_PLLCLK_DIV2
-
-#define RCC_RTCCLKSOURCE_NONE       RCC_RTCCLKSOURCE_NO_CLK
-
-#define RCC_USBCLK_PLLSAI1          RCC_USBCLKSOURCE_PLLSAI1
-#define RCC_USBCLK_PLL              RCC_USBCLKSOURCE_PLL
-#define RCC_USBCLK_MSI              RCC_USBCLKSOURCE_MSI
-#define RCC_USBCLKSOURCE_PLLCLK     RCC_USBCLKSOURCE_PLL
-#define RCC_USBPLLCLK_DIV1          RCC_USBCLKSOURCE_PLL
-#define RCC_USBPLLCLK_DIV1_5        RCC_USBCLKSOURCE_PLL_DIV1_5
-#define RCC_USBPLLCLK_DIV2          RCC_USBCLKSOURCE_PLL_DIV2
-#define RCC_USBPLLCLK_DIV3          RCC_USBCLKSOURCE_PLL_DIV3
-
-#define HSION_BitNumber        RCC_HSION_BIT_NUMBER
-#define HSION_BITNUMBER        RCC_HSION_BIT_NUMBER
-#define HSEON_BitNumber        RCC_HSEON_BIT_NUMBER
-#define HSEON_BITNUMBER        RCC_HSEON_BIT_NUMBER
-#define MSION_BITNUMBER        RCC_MSION_BIT_NUMBER
-#define CSSON_BitNumber        RCC_CSSON_BIT_NUMBER
-#define CSSON_BITNUMBER        RCC_CSSON_BIT_NUMBER
-#define PLLON_BitNumber        RCC_PLLON_BIT_NUMBER
-#define PLLON_BITNUMBER        RCC_PLLON_BIT_NUMBER
-#define PLLI2SON_BitNumber     RCC_PLLI2SON_BIT_NUMBER
-#define I2SSRC_BitNumber       RCC_I2SSRC_BIT_NUMBER
-#define RTCEN_BitNumber        RCC_RTCEN_BIT_NUMBER
-#define RTCEN_BITNUMBER        RCC_RTCEN_BIT_NUMBER
-#define BDRST_BitNumber        RCC_BDRST_BIT_NUMBER
-#define BDRST_BITNUMBER        RCC_BDRST_BIT_NUMBER
-#define RTCRST_BITNUMBER       RCC_RTCRST_BIT_NUMBER
-#define LSION_BitNumber        RCC_LSION_BIT_NUMBER
-#define LSION_BITNUMBER        RCC_LSION_BIT_NUMBER
-#define LSEON_BitNumber        RCC_LSEON_BIT_NUMBER
-#define LSEON_BITNUMBER        RCC_LSEON_BIT_NUMBER
-#define LSEBYP_BITNUMBER       RCC_LSEBYP_BIT_NUMBER
-#define PLLSAION_BitNumber     RCC_PLLSAION_BIT_NUMBER
-#define TIMPRE_BitNumber       RCC_TIMPRE_BIT_NUMBER
-#define RMVF_BitNumber         RCC_RMVF_BIT_NUMBER
-#define RMVF_BITNUMBER         RCC_RMVF_BIT_NUMBER
-#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
-#define CR_BYTE2_ADDRESS       RCC_CR_BYTE2_ADDRESS
-#define CIR_BYTE1_ADDRESS      RCC_CIR_BYTE1_ADDRESS
-#define CIR_BYTE2_ADDRESS      RCC_CIR_BYTE2_ADDRESS
-#define BDCR_BYTE0_ADDRESS     RCC_BDCR_BYTE0_ADDRESS
-#define DBP_TIMEOUT_VALUE      RCC_DBP_TIMEOUT_VALUE
-#define LSE_TIMEOUT_VALUE      RCC_LSE_TIMEOUT_VALUE
-
-#define CR_HSION_BB            RCC_CR_HSION_BB
-#define CR_CSSON_BB            RCC_CR_CSSON_BB
-#define CR_PLLON_BB            RCC_CR_PLLON_BB
-#define CR_PLLI2SON_BB         RCC_CR_PLLI2SON_BB
-#define CR_MSION_BB            RCC_CR_MSION_BB
-#define CSR_LSION_BB           RCC_CSR_LSION_BB
-#define CSR_LSEON_BB           RCC_CSR_LSEON_BB
-#define CSR_LSEBYP_BB          RCC_CSR_LSEBYP_BB
-#define CSR_RTCEN_BB           RCC_CSR_RTCEN_BB
-#define CSR_RTCRST_BB          RCC_CSR_RTCRST_BB
-#define CFGR_I2SSRC_BB         RCC_CFGR_I2SSRC_BB
-#define BDCR_RTCEN_BB          RCC_BDCR_RTCEN_BB
-#define BDCR_BDRST_BB          RCC_BDCR_BDRST_BB
-#define CR_HSEON_BB            RCC_CR_HSEON_BB
-#define CSR_RMVF_BB            RCC_CSR_RMVF_BB
-#define CR_PLLSAION_BB         RCC_CR_PLLSAION_BB
-#define DCKCFGR_TIMPRE_BB      RCC_DCKCFGR_TIMPRE_BB
-
-#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER     __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
-#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER    __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
-#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB        __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
-#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB       __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
-#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE         __HAL_RCC_CRS_RELOADVALUE_CALCULATE
-
-#define __HAL_RCC_GET_IT_SOURCE                     __HAL_RCC_GET_IT
-/**
-  * @}
-  */
-
-/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define  HAL_RNG_ReadyCallback(__HANDLE__)  HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)                                       
-
-/**
-  * @}
-  */
-  
-/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-  
-#define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG
-#define __HAL_RTC_DISABLE_IT                      __HAL_RTC_EXTI_DISABLE_IT
-#define __HAL_RTC_ENABLE_IT                       __HAL_RTC_EXTI_ENABLE_IT
-
-#if defined (STM32F1)
-#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
-
-#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_ENABLE_IT()
-
-#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_DISABLE_IT()
-
-#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT)    __HAL_RTC_ALARM_EXTI_GET_FLAG()
-
-#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
-#else
-#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
-                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
-                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
-#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__)   (((__EXTI_LINE__)  == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
-                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
-                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
-#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
-                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
-                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
-#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__)    (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
-                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
-                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
-#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__)   (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
-                                                      (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() :  \
-                                                          __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
-#endif   /* STM32F1 */
-
-#define IS_ALARM                                  IS_RTC_ALARM
-#define IS_ALARM_MASK                             IS_RTC_ALARM_MASK
-#define IS_TAMPER                                 IS_RTC_TAMPER
-#define IS_TAMPER_ERASE_MODE                      IS_RTC_TAMPER_ERASE_MODE
-#define IS_TAMPER_FILTER                          IS_RTC_TAMPER_FILTER 
-#define IS_TAMPER_INTERRUPT                       IS_RTC_TAMPER_INTERRUPT
-#define IS_TAMPER_MASKFLAG_STATE                  IS_RTC_TAMPER_MASKFLAG_STATE
-#define IS_TAMPER_PRECHARGE_DURATION              IS_RTC_TAMPER_PRECHARGE_DURATION
-#define IS_TAMPER_PULLUP_STATE                    IS_RTC_TAMPER_PULLUP_STATE
-#define IS_TAMPER_SAMPLING_FREQ                   IS_RTC_TAMPER_SAMPLING_FREQ
-#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION     IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
-#define IS_TAMPER_TRIGGER                         IS_RTC_TAMPER_TRIGGER
-#define IS_WAKEUP_CLOCK                           IS_RTC_WAKEUP_CLOCK
-#define IS_WAKEUP_COUNTER                         IS_RTC_WAKEUP_COUNTER
-
-#define __RTC_WRITEPROTECTION_ENABLE  __HAL_RTC_WRITEPROTECTION_ENABLE
-#define __RTC_WRITEPROTECTION_DISABLE  __HAL_RTC_WRITEPROTECTION_DISABLE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define SD_OCR_CID_CSD_OVERWRIETE   SD_OCR_CID_CSD_OVERWRITE
-#define SD_CMD_SD_APP_STAUS         SD_CMD_SD_APP_STATUS
-
-#if defined(STM32F4)
-#define  SD_SDMMC_DISABLED          SD_SDIO_DISABLED
-#define  SD_SDMMC_FUNCTION_BUSY     SD_SDIO_FUNCTION_BUSY     
-#define  SD_SDMMC_FUNCTION_FAILED   SD_SDIO_FUNCTION_FAILED   
-#define  SD_SDMMC_UNKNOWN_FUNCTION  SD_SDIO_UNKNOWN_FUNCTION  
-#define  SD_CMD_SDMMC_SEN_OP_COND   SD_CMD_SDIO_SEN_OP_COND   
-#define  SD_CMD_SDMMC_RW_DIRECT     SD_CMD_SDIO_RW_DIRECT     
-#define  SD_CMD_SDMMC_RW_EXTENDED   SD_CMD_SDIO_RW_EXTENDED   
-#define  __HAL_SD_SDMMC_ENABLE      __HAL_SD_SDIO_ENABLE      
-#define  __HAL_SD_SDMMC_DISABLE     __HAL_SD_SDIO_DISABLE     
-#define  __HAL_SD_SDMMC_DMA_ENABLE  __HAL_SD_SDIO_DMA_ENABLE  
-#define  __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL  
-#define  __HAL_SD_SDMMC_ENABLE_IT   __HAL_SD_SDIO_ENABLE_IT   
-#define  __HAL_SD_SDMMC_DISABLE_IT  __HAL_SD_SDIO_DISABLE_IT  
-#define  __HAL_SD_SDMMC_GET_FLAG    __HAL_SD_SDIO_GET_FLAG    
-#define  __HAL_SD_SDMMC_CLEAR_FLAG  __HAL_SD_SDIO_CLEAR_FLAG  
-#define  __HAL_SD_SDMMC_GET_IT      __HAL_SD_SDIO_GET_IT      
-#define  __HAL_SD_SDMMC_CLEAR_IT    __HAL_SD_SDIO_CLEAR_IT    
-#define  SDMMC_STATIC_FLAGS         SDIO_STATIC_FLAGS	       
-#define  SDMMC_CMD0TIMEOUT          SDIO_CMD0TIMEOUT	       
-#define  SD_SDMMC_SEND_IF_COND      SD_SDIO_SEND_IF_COND
-/* alias CMSIS */
-#define  SDMMC1_IRQn                SDIO_IRQn
-#define  SDMMC1_IRQHandler          SDIO_IRQHandler
-#endif
-
-#if defined(STM32F7) || defined(STM32L4)
-#define  SD_SDIO_DISABLED           SD_SDMMC_DISABLED
-#define  SD_SDIO_FUNCTION_BUSY      SD_SDMMC_FUNCTION_BUSY    
-#define  SD_SDIO_FUNCTION_FAILED    SD_SDMMC_FUNCTION_FAILED  
-#define  SD_SDIO_UNKNOWN_FUNCTION   SD_SDMMC_UNKNOWN_FUNCTION
-#define  SD_CMD_SDIO_SEN_OP_COND    SD_CMD_SDMMC_SEN_OP_COND
-#define  SD_CMD_SDIO_RW_DIRECT      SD_CMD_SDMMC_RW_DIRECT
-#define  SD_CMD_SDIO_RW_EXTENDED    SD_CMD_SDMMC_RW_EXTENDED
-#define  __HAL_SD_SDIO_ENABLE       __HAL_SD_SDMMC_ENABLE
-#define  __HAL_SD_SDIO_DISABLE      __HAL_SD_SDMMC_DISABLE
-#define  __HAL_SD_SDIO_DMA_ENABLE   __HAL_SD_SDMMC_DMA_ENABLE
-#define  __HAL_SD_SDIO_DMA_DISABL   __HAL_SD_SDMMC_DMA_DISABLE
-#define  __HAL_SD_SDIO_ENABLE_IT    __HAL_SD_SDMMC_ENABLE_IT
-#define  __HAL_SD_SDIO_DISABLE_IT   __HAL_SD_SDMMC_DISABLE_IT
-#define  __HAL_SD_SDIO_GET_FLAG     __HAL_SD_SDMMC_GET_FLAG
-#define  __HAL_SD_SDIO_CLEAR_FLAG   __HAL_SD_SDMMC_CLEAR_FLAG
-#define  __HAL_SD_SDIO_GET_IT       __HAL_SD_SDMMC_GET_IT
-#define  __HAL_SD_SDIO_CLEAR_IT     __HAL_SD_SDMMC_CLEAR_IT
-#define  SDIO_STATIC_FLAGS	        SDMMC_STATIC_FLAGS
-#define  SDIO_CMD0TIMEOUT	          SDMMC_CMD0TIMEOUT
-#define  SD_SDIO_SEND_IF_COND	      SD_SDMMC_SEND_IF_COND
-/* alias CMSIS for compatibilities */
-#define  SDIO_IRQn                  SDMMC1_IRQn
-#define  SDIO_IRQHandler            SDMMC1_IRQHandler
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __SMARTCARD_ENABLE_IT           __HAL_SMARTCARD_ENABLE_IT
-#define __SMARTCARD_DISABLE_IT          __HAL_SMARTCARD_DISABLE_IT
-#define __SMARTCARD_ENABLE              __HAL_SMARTCARD_ENABLE
-#define __SMARTCARD_DISABLE             __HAL_SMARTCARD_DISABLE
-#define __SMARTCARD_DMA_REQUEST_ENABLE  __HAL_SMARTCARD_DMA_REQUEST_ENABLE
-#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
-
-#define __HAL_SMARTCARD_GETCLOCKSOURCE  SMARTCARD_GETCLOCKSOURCE
-#define __SMARTCARD_GETCLOCKSOURCE      SMARTCARD_GETCLOCKSOURCE
-
-#define IS_SMARTCARD_ONEBIT_SAMPLING    IS_SMARTCARD_ONE_BIT_SAMPLE                  
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_SMBUS_RESET_CR1           SMBUS_RESET_CR1
-#define __HAL_SMBUS_RESET_CR2           SMBUS_RESET_CR2
-#define __HAL_SMBUS_GENERATE_START      SMBUS_GENERATE_START
-#define __HAL_SMBUS_GET_ADDR_MATCH      SMBUS_GET_ADDR_MATCH
-#define __HAL_SMBUS_GET_DIR             SMBUS_GET_DIR
-#define __HAL_SMBUS_GET_STOP_MODE       SMBUS_GET_STOP_MODE
-#define __HAL_SMBUS_GET_PEC_MODE        SMBUS_GET_PEC_MODE
-#define __HAL_SMBUS_GET_ALERT_ENABLED   SMBUS_GET_ALERT_ENABLED
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __HAL_SPI_1LINE_TX              SPI_1LINE_TX
-#define __HAL_SPI_1LINE_RX              SPI_1LINE_RX
-#define __HAL_SPI_RESET_CRC             SPI_RESET_CRC
-
-/**
-  * @}
-  */
-  
-/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __HAL_UART_GETCLOCKSOURCE       UART_GETCLOCKSOURCE
-#define __HAL_UART_MASK_COMPUTATION     UART_MASK_COMPUTATION
-#define __UART_GETCLOCKSOURCE           UART_GETCLOCKSOURCE
-#define __UART_MASK_COMPUTATION         UART_MASK_COMPUTATION
-
-#define IS_UART_WAKEUPMETHODE           IS_UART_WAKEUPMETHOD
-
-#define IS_UART_ONEBIT_SAMPLE           IS_UART_ONE_BIT_SAMPLE                  
-#define IS_UART_ONEBIT_SAMPLING         IS_UART_ONE_BIT_SAMPLE                  
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __USART_ENABLE_IT               __HAL_USART_ENABLE_IT
-#define __USART_DISABLE_IT              __HAL_USART_DISABLE_IT
-#define __USART_ENABLE                  __HAL_USART_ENABLE
-#define __USART_DISABLE                 __HAL_USART_DISABLE
-
-#define __HAL_USART_GETCLOCKSOURCE      USART_GETCLOCKSOURCE
-#define __USART_GETCLOCKSOURCE          USART_GETCLOCKSOURCE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define USB_EXTI_LINE_WAKEUP                               USB_WAKEUP_EXTI_LINE
-
-#define USB_FS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
-#define USB_FS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
-#define USB_FS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
-#define USB_FS_EXTI_LINE_WAKEUP                            USB_OTG_FS_WAKEUP_EXTI_LINE
-
-#define USB_HS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
-#define USB_HS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
-#define USB_HS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
-#define USB_HS_EXTI_LINE_WAKEUP                            USB_OTG_HS_WAKEUP_EXTI_LINE
-
-#define __HAL_USB_EXTI_ENABLE_IT                           __HAL_USB_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_USB_EXTI_DISABLE_IT                          __HAL_USB_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_USB_EXTI_GET_FLAG                            __HAL_USB_WAKEUP_EXTI_GET_FLAG
-#define __HAL_USB_EXTI_CLEAR_FLAG                          __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER             __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
-#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER            __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER           __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
-
-#define __HAL_USB_FS_EXTI_ENABLE_IT                        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_USB_FS_EXTI_DISABLE_IT                       __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_USB_FS_EXTI_GET_FLAG                         __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
-#define __HAL_USB_FS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
-#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
-#define __HAL_USB_FS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
-
-#define __HAL_USB_HS_EXTI_ENABLE_IT                        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_USB_HS_EXTI_DISABLE_IT                       __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_USB_HS_EXTI_GET_FLAG                         __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
-#define __HAL_USB_HS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
-#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
-#define __HAL_USB_HS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
-
-#define HAL_PCD_ActiveRemoteWakeup                         HAL_PCD_ActivateRemoteWakeup
-#define HAL_PCD_DeActiveRemoteWakeup                       HAL_PCD_DeActivateRemoteWakeup
-
-#define HAL_PCD_SetTxFiFo                                  HAL_PCDEx_SetTxFiFo
-#define HAL_PCD_SetRxFiFo                                  HAL_PCDEx_SetRxFiFo
-/**
-  * @}
-  */
-
-/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_TIM_SetICPrescalerValue   TIM_SET_ICPRESCALERVALUE
-#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
-
-#define TIM_GET_ITSTATUS                __HAL_TIM_GET_IT_SOURCE
-#define TIM_GET_CLEAR_IT                __HAL_TIM_CLEAR_IT
-
-#define __HAL_TIM_GET_ITSTATUS          __HAL_TIM_GET_IT_SOURCE
-
-#define __HAL_TIM_DIRECTION_STATUS      __HAL_TIM_IS_TIM_COUNTING_DOWN
-#define __HAL_TIM_PRESCALER             __HAL_TIM_SET_PRESCALER
-#define __HAL_TIM_SetCounter            __HAL_TIM_SET_COUNTER
-#define __HAL_TIM_GetCounter            __HAL_TIM_GET_COUNTER
-#define __HAL_TIM_SetAutoreload         __HAL_TIM_SET_AUTORELOAD
-#define __HAL_TIM_GetAutoreload         __HAL_TIM_GET_AUTORELOAD
-#define __HAL_TIM_SetClockDivision      __HAL_TIM_SET_CLOCKDIVISION
-#define __HAL_TIM_GetClockDivision      __HAL_TIM_GET_CLOCKDIVISION
-#define __HAL_TIM_SetICPrescaler        __HAL_TIM_SET_ICPRESCALER
-#define __HAL_TIM_GetICPrescaler        __HAL_TIM_GET_ICPRESCALER
-#define __HAL_TIM_SetCompare            __HAL_TIM_SET_COMPARE
-#define __HAL_TIM_GetCompare            __HAL_TIM_GET_COMPARE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
-  * @{
-  */
-  
-#define __HAL_ETH_EXTI_ENABLE_IT                   __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_ETH_EXTI_DISABLE_IT                  __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_ETH_EXTI_GET_FLAG                    __HAL_ETH_WAKEUP_EXTI_GET_FLAG
-#define __HAL_ETH_EXTI_CLEAR_FLAG                  __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER     __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
-#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER    __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
-#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER   __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
-
-#define ETH_PROMISCIOUSMODE_ENABLE   ETH_PROMISCUOUS_MODE_ENABLE 
-#define ETH_PROMISCIOUSMODE_DISABLE  ETH_PROMISCUOUS_MODE_DISABLE
-#define IS_ETH_PROMISCIOUS_MODE      IS_ETH_PROMISCUOUS_MODE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_LTDC_LAYER LTDC_LAYER
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define SAI_OUTPUTDRIVE_DISABLED          SAI_OUTPUTDRIVE_DISABLE
-#define SAI_OUTPUTDRIVE_ENABLED           SAI_OUTPUTDRIVE_ENABLE
-#define SAI_MASTERDIVIDER_ENABLED         SAI_MASTERDIVIDER_ENABLE
-#define SAI_MASTERDIVIDER_DISABLED        SAI_MASTERDIVIDER_DISABLE
-#define SAI_STREOMODE                     SAI_STEREOMODE
-#define SAI_FIFOStatus_Empty              SAI_FIFOSTATUS_EMPTY
-#define SAI_FIFOStatus_Less1QuarterFull   SAI_FIFOSTATUS_LESS1QUARTERFULL
-#define SAI_FIFOStatus_1QuarterFull       SAI_FIFOSTATUS_1QUARTERFULL
-#define SAI_FIFOStatus_HalfFull           SAI_FIFOSTATUS_HALFFULL
-#define SAI_FIFOStatus_3QuartersFull      SAI_FIFOSTATUS_3QUARTERFULL
-#define SAI_FIFOStatus_Full               SAI_FIFOSTATUS_FULL
-#define IS_SAI_BLOCK_MONO_STREO_MODE      IS_SAI_BLOCK_MONO_STEREO_MODE
-#define SAI_SYNCHRONOUS_EXT               SAI_SYNCHRONOUS_EXT_SAI1
-#define SAI_SYNCEXT_IN_ENABLE             SAI_SYNCEXT_OUTBLOCKA_ENABLE
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
-  * @{
-  */
-  
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ___STM32_HAL_LEGACY */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/stmhal/hal/l4/inc/stm32l4xx_hal.h b/stmhal/hal/l4/inc/stm32l4xx_hal.h
deleted file mode 100644
index c54034889d..0000000000
--- a/stmhal/hal/l4/inc/stm32l4xx_hal.h
+++ /dev/null
@@ -1,569 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal.h
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   This file contains all the functions prototypes for the HAL
-  *          module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L4xx_HAL_H
-#define __STM32L4xx_HAL_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_conf.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup HAL
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
-  * @{
-  */
-
-/** @defgroup SYSCFG_BootMode Boot Mode
-  * @{
-  */
-#define SYSCFG_BOOT_MAINFLASH          ((uint32_t)0x00000000)
-#define SYSCFG_BOOT_SYSTEMFLASH        SYSCFG_MEMRMP_MEM_MODE_0
-#define SYSCFG_BOOT_FMC                SYSCFG_MEMRMP_MEM_MODE_1
-#define SYSCFG_BOOT_SRAM               (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0)
-#define SYSCFG_BOOT_QUADSPI            (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1)
-
-/**
-  * @}
-  */
-
-/** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts
-  * @{
-  */
-#define SYSCFG_IT_FPU_IOC              SYSCFG_CFGR1_FPU_IE_0  /*!< Floating Point Unit Invalid operation Interrupt */
-#define SYSCFG_IT_FPU_DZC              SYSCFG_CFGR1_FPU_IE_1  /*!< Floating Point Unit Divide-by-zero Interrupt */
-#define SYSCFG_IT_FPU_UFC              SYSCFG_CFGR1_FPU_IE_2  /*!< Floating Point Unit Underflow Interrupt */
-#define SYSCFG_IT_FPU_OFC              SYSCFG_CFGR1_FPU_IE_3  /*!< Floating Point Unit Overflow Interrupt */
-#define SYSCFG_IT_FPU_IDC              SYSCFG_CFGR1_FPU_IE_4  /*!< Floating Point Unit Input denormal Interrupt */
-#define SYSCFG_IT_FPU_IXC              SYSCFG_CFGR1_FPU_IE_5  /*!< Floating Point Unit Inexact Interrupt */
-
-/**
-  * @}
-  */
-
-/** @defgroup SYSCFG_SRAM2WRP SRAM2 Write protection
-  * @{
-  */
-#define SYSCFG_SRAM2WRP_PAGE0          SYSCFG_SWPR_PAGE0 /*!< SRAM2 Write protection page 0 */
-#define SYSCFG_SRAM2WRP_PAGE1          SYSCFG_SWPR_PAGE1 /*!< SRAM2 Write protection page 1 */
-#define SYSCFG_SRAM2WRP_PAGE2          SYSCFG_SWPR_PAGE2 /*!< SRAM2 Write protection page 2 */
-#define SYSCFG_SRAM2WRP_PAGE3          SYSCFG_SWPR_PAGE3 /*!< SRAM2 Write protection page 3 */
-#define SYSCFG_SRAM2WRP_PAGE4          SYSCFG_SWPR_PAGE4 /*!< SRAM2 Write protection page 4 */
-#define SYSCFG_SRAM2WRP_PAGE5          SYSCFG_SWPR_PAGE5 /*!< SRAM2 Write protection page 5 */
-#define SYSCFG_SRAM2WRP_PAGE6          SYSCFG_SWPR_PAGE6 /*!< SRAM2 Write protection page 6 */
-#define SYSCFG_SRAM2WRP_PAGE7          SYSCFG_SWPR_PAGE7 /*!< SRAM2 Write protection page 7 */
-#define SYSCFG_SRAM2WRP_PAGE8          SYSCFG_SWPR_PAGE8 /*!< SRAM2 Write protection page 8 */
-#define SYSCFG_SRAM2WRP_PAGE9          SYSCFG_SWPR_PAGE9 /*!< SRAM2 Write protection page 9 */
-#define SYSCFG_SRAM2WRP_PAGE10         SYSCFG_SWPR_PAGE10 /*!< SRAM2 Write protection page 10 */
-#define SYSCFG_SRAM2WRP_PAGE11         SYSCFG_SWPR_PAGE11 /*!< SRAM2 Write protection page 11 */
-#define SYSCFG_SRAM2WRP_PAGE12         SYSCFG_SWPR_PAGE12 /*!< SRAM2 Write protection page 12 */
-#define SYSCFG_SRAM2WRP_PAGE13         SYSCFG_SWPR_PAGE13 /*!< SRAM2 Write protection page 13 */
-#define SYSCFG_SRAM2WRP_PAGE14         SYSCFG_SWPR_PAGE14 /*!< SRAM2 Write protection page 14 */
-#define SYSCFG_SRAM2WRP_PAGE15         SYSCFG_SWPR_PAGE15 /*!< SRAM2 Write protection page 15 */
-#define SYSCFG_SRAM2WRP_PAGE16         SYSCFG_SWPR_PAGE16 /*!< SRAM2 Write protection page 16 */
-#define SYSCFG_SRAM2WRP_PAGE17         SYSCFG_SWPR_PAGE17 /*!< SRAM2 Write protection page 17 */
-#define SYSCFG_SRAM2WRP_PAGE18         SYSCFG_SWPR_PAGE18 /*!< SRAM2 Write protection page 18 */
-#define SYSCFG_SRAM2WRP_PAGE19         SYSCFG_SWPR_PAGE19 /*!< SRAM2 Write protection page 19 */
-#define SYSCFG_SRAM2WRP_PAGE20         SYSCFG_SWPR_PAGE20 /*!< SRAM2 Write protection page 20 */
-#define SYSCFG_SRAM2WRP_PAGE21         SYSCFG_SWPR_PAGE21 /*!< SRAM2 Write protection page 21 */
-#define SYSCFG_SRAM2WRP_PAGE22         SYSCFG_SWPR_PAGE22 /*!< SRAM2 Write protection page 22 */
-#define SYSCFG_SRAM2WRP_PAGE23         SYSCFG_SWPR_PAGE23 /*!< SRAM2 Write protection page 23 */
-#define SYSCFG_SRAM2WRP_PAGE24         SYSCFG_SWPR_PAGE24 /*!< SRAM2 Write protection page 24 */
-#define SYSCFG_SRAM2WRP_PAGE25         SYSCFG_SWPR_PAGE25 /*!< SRAM2 Write protection page 25 */
-#define SYSCFG_SRAM2WRP_PAGE26         SYSCFG_SWPR_PAGE26 /*!< SRAM2 Write protection page 26 */
-#define SYSCFG_SRAM2WRP_PAGE27         SYSCFG_SWPR_PAGE27 /*!< SRAM2 Write protection page 27 */
-#define SYSCFG_SRAM2WRP_PAGE28         SYSCFG_SWPR_PAGE28 /*!< SRAM2 Write protection page 28 */
-#define SYSCFG_SRAM2WRP_PAGE29         SYSCFG_SWPR_PAGE29 /*!< SRAM2 Write protection page 29 */
-#define SYSCFG_SRAM2WRP_PAGE30         SYSCFG_SWPR_PAGE30 /*!< SRAM2 Write protection page 30 */
-#define SYSCFG_SRAM2WRP_PAGE31         SYSCFG_SWPR_PAGE31 /*!< SRAM2 Write protection page 31 */
-
-/**
-  * @}
-  */
-
-#if defined(VREFBUF)
-/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
-  * @{
-  */
-#define SYSCFG_VREFBUF_VOLTAGE_SCALE0  ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */
-#define SYSCFG_VREFBUF_VOLTAGE_SCALE1  VREFBUF_CSR_VRS        /*!< Voltage reference scale 1 (VREF_OUT2) */
-
-/**
-  * @}
-  */
-
-/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
-  * @{
-  */
-#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE  ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
-#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE   VREFBUF_CSR_HIZ        /*!< VREF_plus pin is high impedance */
-
-/**
-  * @}
-  */
-#endif /* VREFBUF */
-
-/** @defgroup SYSCFG_flags_definition Flags
-  * @{
-  */
-
-#define SYSCFG_FLAG_SRAM2_PE            SYSCFG_CFGR2_SPF       /*!< SRAM2 parity error */
-#define SYSCFG_FLAG_SRAM2_BUSY          SYSCFG_SCSR_SRAM2BSY   /*!< SRAM2 busy by erase operation */
-
-/**
-  * @}
-  */
-
-/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
-  * @{
-  */
-
-/** @brief  Fast-mode Plus driving capability on a specific GPIO
-  */  
-#define SYSCFG_FASTMODEPLUS_PB6        SYSCFG_CFGR1_I2C_PB6_FMP  /*!< Enable Fast-mode Plus on PB6 */
-#define SYSCFG_FASTMODEPLUS_PB7        SYSCFG_CFGR1_I2C_PB7_FMP  /*!< Enable Fast-mode Plus on PB7 */
-#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
-#define SYSCFG_FASTMODEPLUS_PB8        SYSCFG_CFGR1_I2C_PB8_FMP  /*!< Enable Fast-mode Plus on PB8 */
-#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
-#if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
-#define SYSCFG_FASTMODEPLUS_PB9        SYSCFG_CFGR1_I2C_PB9_FMP  /*!< Enable Fast-mode Plus on PB9 */
-#endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
-
-/**
- * @}
- */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-
-/** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros
-  * @{
-  */
-
-/** @brief  Freeze/Unfreeze Peripherals in Debug mode
-  */
-#if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM2()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM2()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
-#endif
-
-#if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM3()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM3()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
-#endif
-
-#if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM4()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM4()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
-#endif
-
-#if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM5()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM5()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
-#endif
-
-#if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM6()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM6()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
-#endif
-
-#if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM7()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM7()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
-#endif
-
-#if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP)
-#define __HAL_DBGMCU_FREEZE_RTC()            SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
-#define __HAL_DBGMCU_UNFREEZE_RTC()          CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
-#endif
-
-#if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP)
-#define __HAL_DBGMCU_FREEZE_WWDG()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
-#define __HAL_DBGMCU_UNFREEZE_WWDG()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
-#endif
-
-#if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP)
-#define __HAL_DBGMCU_FREEZE_IWDG()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
-#define __HAL_DBGMCU_UNFREEZE_IWDG()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
-#endif
-
-#if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP)
-#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
-#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
-#endif
-
-#if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP)
-#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
-#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
-#endif
-
-#if defined(DBGMCU_APB1FZR1_DBG_I2C3_STOP)
-#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
-#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
-#endif
-
-#if defined(DBGMCU_APB1FZR1_DBG_CAN_STOP)
-#define __HAL_DBGMCU_FREEZE_CAN1()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP)
-#define __HAL_DBGMCU_UNFREEZE_CAN1()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP)
-#endif
-
-#if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
-#define __HAL_DBGMCU_FREEZE_LPTIM1()         SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
-#define __HAL_DBGMCU_UNFREEZE_LPTIM1()       CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
-#endif
-
-#if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
-#define __HAL_DBGMCU_FREEZE_LPTIM2()         SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
-#define __HAL_DBGMCU_UNFREEZE_LPTIM2()       CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
-#endif
-
-#if defined(DBGMCU_APB2FZ_DBG_TIM1_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM1()           SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM1()         CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
-#endif
-
-#if defined(DBGMCU_APB2FZ_DBG_TIM8_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM8()           SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM8()         CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
-#endif
-
-#if defined(DBGMCU_APB2FZ_DBG_TIM15_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM15()          SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM15()        CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
-#endif
-
-#if defined(DBGMCU_APB2FZ_DBG_TIM16_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM16()          SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM16()        CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
-#endif
-
-#if defined(DBGMCU_APB2FZ_DBG_TIM17_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM17()          SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM17()        CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
-#endif
-
-/**
-  * @}
-  */
-
-/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
-  * @{
-  */
-
-/** @brief  Main Flash memory mapped at 0x00000000.
-  */
-#define __HAL_SYSCFG_REMAPMEMORY_FLASH()       CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
-
-/** @brief  System Flash memory mapped at 0x00000000.
-  */
-#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0)
-
-/** @brief  Embedded SRAM mapped at 0x00000000.
-  */
-#define __HAL_SYSCFG_REMAPMEMORY_SRAM()        MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0))
-
-/** @brief  FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000.
-  */
-#define __HAL_SYSCFG_REMAPMEMORY_FMC()         MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1)
-
-/** @brief  QUADSPI mapped at 0x00000000.
-  */
-#define __HAL_SYSCFG_REMAPMEMORY_QUADSPI()     MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1))
-
-/**
-  * @brief  Return the boot mode as configured by user.
-  * @retval The boot mode as configured by user. The returned value can be one
-  *         of the following values:
-  *           @arg @ref SYSCFG_BOOT_MAINFLASH
-  *           @arg @ref SYSCFG_BOOT_SYSTEMFLASH
-  *           @arg @ref SYSCFG_BOOT_FMC
-  *           @arg @ref SYSCFG_BOOT_SRAM
-  *           @arg @ref SYSCFG_BOOT_QUADSPI
-  */
-#define __HAL_SYSCFG_GET_BOOT_MODE()           READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
-
-/** @brief  SRAM2 page write protection enable macro
-  * @param __SRAM2WRP__: This parameter can be a value of @ref SYSCFG_SRAM2WRP
-  * @note   write protection can only be disabled by a system reset
-  */
-#define __HAL_SYSCFG_SRAM2_WRP_ENABLE(__SRAM2WRP__)   do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\
-                                                         SET_BIT(SYSCFG->SWPR, (__SRAM2WRP__));\
-                                                        }while(0)
-
-/** @brief  SRAM2 page write protection unlock prior to erase
-  * @note   Writing a wrong key reactivates the write protection
-  */
-#define __HAL_SYSCFG_SRAM2_WRP_UNLOCK()      do {SYSCFG->SKR = 0xCA;\
-                                                 SYSCFG->SKR = 0x53;\
-                                                }while(0)
-
-/** @brief  SRAM2 erase
-  * @note   __SYSCFG_GET_FLAG(SYSCFG_FLAG_SRAM2_BUSY) may be used to check end of erase
-  */
-#define __HAL_SYSCFG_SRAM2_ERASE()           SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER)
-
-/** @brief  Floating Point Unit interrupt enable/disable macros
-  * @param __INTERRUPT__: This parameter can be a value of @ref SYSCFG_FPU_Interrupts
-  */
-#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__)    do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
-                                                                SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
-                                                            }while(0)
-
-#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__)   do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
-                                                                CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
-                                                            }while(0)
-
-/** @brief  SYSCFG Break ECC lock.
-  *         Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input.
-  * @note   The selected configuration is locked and can be unlocked only by system reset.
-  */
-#define __HAL_SYSCFG_BREAK_ECC_LOCK()        SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
-
-/** @brief  SYSCFG Break Cortex-M4 Lockup lock.
-  *         Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input.
-  * @note   The selected configuration is locked and can be unlocked only by system reset.
-  */
-#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK()     SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
-
-/** @brief  SYSCFG Break PVD lock.
-  *         Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register.
-  * @note   The selected configuration is locked and can be unlocked only by system reset.
-  */
-#define __HAL_SYSCFG_BREAK_PVD_LOCK()        SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
-
-/** @brief  SYSCFG Break SRAM2 parity lock.
-  *         Enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17 Break input.
-  * @note   The selected configuration is locked and can be unlocked by system reset.
-  */
-#define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK()  SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL)
-
-/** @brief  Check SYSCFG flag is set or not.
-  * @param  __FLAG__: specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg @ref SYSCFG_FLAG_SRAM2_PE   SRAM2 Parity Error Flag
-  *            @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_SYSCFG_GET_FLAG(__FLAG__)      ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0) ? 1 : 0)
-
-/** @brief  Set the SPF bit to clear the SRAM Parity Error Flag.
-  */
-#define __HAL_SYSCFG_CLEAR_FLAG()            SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
-
-/** @brief  Fast-mode Plus driving capability enable/disable macros
-  * @param __FASTMODEPLUS__: This parameter can be a value of : 
-  *     @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6
-  *     @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 
-  *     @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8
-  *     @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9
-  */
-#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)  do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
-                                                                SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
-                                                               }while(0)
-
-#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
-                                                                CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
-                                                               }while(0)
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros
-  * @{
-  */
-
-#define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \
-                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \
-                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \
-                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \
-                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \
-                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC))
-
-#define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC)           || \
-                                            ((__CONFIG__) == SYSCFG_BREAK_PVD)           || \
-                                            ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY)  || \
-                                            ((__CONFIG__) == SYSCFG_BREAK_LOCKUP))
-
-#define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__)   (((__PAGE__) > 0) && ((__PAGE__) <= 0xFFFFFFFF))
-
-#if defined(VREFBUF)
-#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__)  (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
-                                                     ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1))
-
-#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__)  (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
-                                                      ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
-
-#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__)  (((__VALUE__) > 0) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
-#endif /* VREFBUF */
-
-#if defined(SYSCFG_FASTMODEPLUS_PB8) && defined(SYSCFG_FASTMODEPLUS_PB9)
-#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
-                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
-                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
-                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
-#elif defined(SYSCFG_FASTMODEPLUS_PB8)
-#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
-                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
-                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8))
-#elif defined(SYSCFG_FASTMODEPLUS_PB9)
-#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
-                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
-                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
-#else
-#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
-                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7))
-#endif
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup HAL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup HAL_Exported_Functions_Group1
-  * @{
-  */
-
-/* Initialization and de-initialization functions  ******************************/
-HAL_StatusTypeDef HAL_Init(void);
-HAL_StatusTypeDef HAL_DeInit(void);
-void HAL_MspInit(void);
-void HAL_MspDeInit(void);
-HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
-
-/**
-  * @}
-  */
-
-/** @addtogroup HAL_Exported_Functions_Group2
-  * @{
-  */
-
-/* Peripheral Control functions  ************************************************/
-void HAL_IncTick(void);
-void HAL_Delay(uint32_t Delay);
-uint32_t HAL_GetTick(void);
-void HAL_SuspendTick(void);
-void HAL_ResumeTick(void);
-uint32_t HAL_GetHalVersion(void);
-uint32_t HAL_GetREVID(void);
-uint32_t HAL_GetDEVID(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup HAL_Exported_Functions_Group3
-  * @{
-  */
-
-/* DBGMCU Peripheral Control functions  *****************************************/
-void HAL_DBGMCU_EnableDBGSleepMode(void);
-void HAL_DBGMCU_DisableDBGSleepMode(void);
-void HAL_DBGMCU_EnableDBGStopMode(void);
-void HAL_DBGMCU_DisableDBGStopMode(void);
-void HAL_DBGMCU_EnableDBGStandbyMode(void);
-void HAL_DBGMCU_DisableDBGStandbyMode(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup HAL_Exported_Functions_Group4
-  * @{
-  */
-
-/* SYSCFG Control functions  ****************************************************/
-void HAL_SYSCFG_SRAM2Erase(void);
-void HAL_SYSCFG_EnableMemorySwappingBank(void);
-void HAL_SYSCFG_DisableMemorySwappingBank(void);
-
-#if defined(VREFBUF)
-void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
-void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
-void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
-HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
-void HAL_SYSCFG_DisableVREFBUF(void);
-#endif /* VREFBUF */
-
-void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void);
-void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L4xx_HAL_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/inc/stm32l4xx_hal_adc.h b/stmhal/hal/l4/inc/stm32l4xx_hal_adc.h
deleted file mode 100644
index 892ab36b14..0000000000
--- a/stmhal/hal/l4/inc/stm32l4xx_hal_adc.h
+++ /dev/null
@@ -1,1032 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_adc.h
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   Header file of ADC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L4xx_ADC_H
-#define __STM32L4xx_ADC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-   
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup ADC
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup ADC_Exported_Types ADC Exported Types
-  * @{
-  */ 
-  
-                                                      
-/** 
-  * @brief  ADC Regular Conversion Oversampling structure definition  
-  */
-typedef struct
-{
-  uint32_t Ratio;                         /*!< Configures the oversampling ratio.
-                                               This parameter can be a value of @ref ADCEx_Oversampling_Ratio */
-                                               
-  uint32_t RightBitShift;                 /*!< Configures the division coefficient for the Oversampler.
-                                               This parameter can be a value of @ref ADCEx_Right_Bit_Shift */
-                                               
-  uint32_t TriggeredMode;                 /*!< Selects the regular triggered oversampling mode.
-                                               This parameter can be a value of @ref ADCEx_Triggered_Oversampling_Mode */
-                                               
-  uint32_t OversamplingStopReset;         /*!< Selects the regular oversampling mode.
-                                               The oversampling is either temporary stopped or reset upon an injected
-                                               sequence interruption. 
-                                               If oversampling is enabled on both regular and injected groups, this parameter 
-                                               is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE" 
-                                               (the oversampling buffer is zeroed during injection sequence).   
-                                               This parameter can be a value of @ref ADCEx_Regular_Oversampling_Mode */                                               
-                                        
-}ADC_OversamplingTypeDef;  
-  
-  
-  
-  
-/**
-  * @brief  Structure definition of ADC initialization and regular group  
-  * @note   Parameters of this structure are shared within 2 scopes:
-  *          - Scope entire ADC (affects regular and injected groups): ClockPrescaler and ClockDivider, Resolution, DataAlign, 
-  *            ScanConvMode, EOCSelection, LowPowerAutoWait.
-  *          - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, 
-  *            ExternalTrigConv, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling.
-  * @note   The setting of these parameters by function HAL_ADC_Init() is conditioned by ADC state.
-  *         ADC state can be either:
-  *          - For all parameters: ADC disabled
-  *          - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on going on regular group.
-  *          - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on regular and injected groups.
-  *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
-  *         without error reporting (as it can be the expected behaviour in case of intended action to update another parameter 
-  *         (which fulfills the ADC state condition) on the fly).
-  */
-typedef struct
-{                                                                                                                          
-  uint32_t ClockPrescaler;        /*!< Selects ADC clock source (asynchronous System/PLLSAI1/PLLSAI2 clocks or synchronous AHB clock) as well as
-                                       the division factor applied to the clock.
-                                       This parameter can be a value of @ref ADC_ClockPrescaler.
-                                       Note: The clock is common for all the ADCs.
-                                       Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits, 
-                                             AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits.
-                                       Note: In case of usage of the ADC dedicated PLL clock, this clock must be preliminarily enabled and prescaler set at RCC top level.
-                                       Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only if the AHB clock prescaler is set to 1 
-                                       and if the system clock has a 50% duty cycle.                                       
-                                       Note: This parameter can be modified only if all ADCs are disabled. */
-                                       
-  uint32_t Resolution;            /*!< Configures the ADC resolution. 
-                                       This parameter can be a value of @ref ADC_Resolution */
-
-  uint32_t DataAlign;             /*!< Specifies ADC data alignment (right or left). 
-                                       See reference manual for alignments formats versus resolutions.
-                                       This parameter can be a value of @ref ADC_Data_align */
-
-  uint32_t ScanConvMode;          /*!< Configures the sequencer of regular and injected groups.
-                                       This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
-                                       If disabled: Conversion is performed in single mode (one channel converted, that defined in rank 1).
-                                                    Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
-                                       If enabled:  Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion' or'InjectedNbrOfConversion'). 
-                                                    Scan direction is upward: from rank 1 to rank 'n'.
-                                       This parameter can be a value of @ref ADC_Scan_mode */
-
-  uint32_t EOCSelection;          /*!< Specifies which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
-                                       This parameter can be a value of @ref ADC_EOCSelection. */
-
-  uint32_t LowPowerAutoWait;      /*!< Selects the dynamic low power Auto Delay: new conversion start only when the previous
-                                       conversion (for regular group) or previous sequence (for injected group) has been processed by user software
-                                       (EOC bit cleared or DR read for regular conversions, JEOS cleared for injected conversions).
-                                       This feature automatically adapts the speed of ADC to the speed of the system that reads the data. Moreover, this avoids risk of overrun 
-                                       for low frequency applications. 
-                                       This parameter can be set to ENABLE or DISABLE.
-                                       Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA(), HAL_ADCEx_InjectedStart_IT()) when it is necessary 
-                                       to clear immediately the EOC flag to free the IRQ vector sequencer.
-                                       Do use with polling: 1. Start conversion with HAL_ADC_Start() or HAL_ADCEx_InjectedStart(), 2. When conversion data is available: use 
-                                       HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another 
-                                       conversion. For injected conversion, resort to HAL_ADCEx_InjectedPollForConversion() then HAL_ADCEx_InjectedGetValue() */
-
-  uint32_t ContinuousConvMode;    /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
-                                       after software start or external trigger occurred.
-                                       This parameter can be set to ENABLE or DISABLE. */
-
-  uint32_t NbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
-                                       To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
-                                       This parameter must be a number between Min_Data = 1 and Max_Data = 16.
-                                       Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without 
-                                       continuous mode or external trigger that could launch a conversion). */
-
-  uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence 
-                                       subdivided in successive parts).
-                                       Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
-                                       Discontinuous mode can be enabled only if continuous mode is disabled.
-                                       This parameter can be set to ENABLE or DISABLE. */
-
-  uint32_t NbrOfDiscConversion;   /*!< Specifies the number of discontinuous conversions in which the  main sequence of regular group (parameter NbrOfConversion) will be subdivided.
-                                       If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
-                                       This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
-
-  uint32_t ExternalTrigConv;      /*!< Selects the external event used to trigger the conversion start of regular group.
-                                       If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
-                                       This parameter can be a value of @ref ADC_Regular_External_Trigger_Source.
-                                       Caution: external trigger source is common to ADCs.  */
-                                                                                                        
-  uint32_t ExternalTrigConvEdge;  /*!< Selects the external trigger edge of regular group.
-                                       If set to ADC_EXTERNALTRIGCONVEDGE_NONE, external triggers are disabled and software trigger is used instead.
-                                       This parameter can be a value of @ref ADC_Regular_External_Trigger_Source_Edge */
-
-  uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached)
-                                       or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
-                                       Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
-                                       This parameter can be set to ENABLE or DISABLE.
-                                       Note: This parameter must be modified when no conversion is on going on both regular and injected groups 
-                                       (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */
-
-  uint32_t Overrun;               /*!< Select the behaviour in case of overrun: data overwritten or preserved (default).
-                                       This parameter applies to regular group only.
-                                       This parameter can be a value of @ref ADC_Overrun.
-                                       Note: Case of overrun set to data preserved and usage with end on conversion interruption (HAL_Start_IT()): ADC IRQ handler has to clear 
-                                       end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved by user-developped function 
-                                       HAL_ADC_ConvCpltCallback() (called before end of conversion flags clear).
-                                       Note: Error reporting with respect to the conversion mode:
-                                        - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data 
-                                          overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case.
-                                        - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */
-                                        
-  uint32_t OversamplingMode;               /*!< Specifies whether the oversampling feature is enabled or disabled.
-                                                This parameter can be set to ENABLE or DISABLE.
-                                                Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
-                                              
-  ADC_OversamplingTypeDef  Oversampling;   /*!< Specifies the Oversampling parameters.
-                                                Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled.  
-                                                Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */                                        
-}ADC_InitTypeDef;  
-  
-
-/** @defgroup ADC_States ADC States
-  * @{
-  */ 
-    
-/** 
-  * @brief  HAL ADC state machine: ADC State bitfield definition  
-  */ 
-/* States of ADC global scope */
-#define HAL_ADC_STATE_RESET             ((uint32_t)0x00000000)    /*!< ADC not yet initialized or disabled */
-#define HAL_ADC_STATE_READY             ((uint32_t)0x00000001)    /*!< ADC peripheral ready for use */
-#define HAL_ADC_STATE_BUSY_INTERNAL     ((uint32_t)0x00000002)    /*!< ADC is busy because of an internal process (initialization, calibration) */   
-#define HAL_ADC_STATE_TIMEOUT           ((uint32_t)0x00000004)    /*!< TimeOut occurrence */
-
-/* States of ADC errors */
-#define HAL_ADC_STATE_ERROR_INTERNAL    ((uint32_t)0x00000010)    /*!< Internal error occurrence */
-#define HAL_ADC_STATE_ERROR_CONFIG      ((uint32_t)0x00000020)    /*!< Configuration error occurrence */  
-#define HAL_ADC_STATE_ERROR_DMA         ((uint32_t)0x00000040)    /*!< DMA error occurrence */ 
-
-/* States of ADC regular group */
-#define HAL_ADC_STATE_REG_BUSY          ((uint32_t)0x00000100)    /*!< A regular conversion is ongoing or can occur (either by continuous mode,
-                                                                       external trigger, low power auto power-on, multimode ADC master control) */ 
-#define HAL_ADC_STATE_REG_EOC           ((uint32_t)0x00000200)    /*!< Regular conversion data available */
-#define HAL_ADC_STATE_REG_OVR           ((uint32_t)0x00000400)    /*!< Overrun occurrence  */
-#define HAL_ADC_STATE_REG_EOSMP         ((uint32_t)0x00000800)    /*!< End Of Sampling flag raised  */
-
-/* States of ADC injected group */
-#define HAL_ADC_STATE_INJ_BUSY          ((uint32_t)0x00001000)    /*!< An injected conversion is ongoing or can occur (either by auto-injection mode,
-                                                                       external trigger, low power auto power-on, multimode ADC master control) */ 
-#define HAL_ADC_STATE_INJ_EOC           ((uint32_t)0x00002000)    /*!< Injected conversion data available */
-#define HAL_ADC_STATE_INJ_JQOVF         ((uint32_t)0x00004000)    /*!< Injected queue overflow occurrence */
-
-/* States of ADC analog watchdogs */
-#define HAL_ADC_STATE_AWD1              ((uint32_t)0x00010000)    /*!< Out-of-window occurrence of Analog Watchdog 1 */
-#define HAL_ADC_STATE_AWD2              ((uint32_t)0x00020000)    /*!< Out-of-window occurrence of Analog Watchdog 2 */
-#define HAL_ADC_STATE_AWD3              ((uint32_t)0x00040000)    /*!< Out-of-window occurrence of Analog Watchdog 3 */
-
-/* States of ADC multi-mode */
-#define HAL_ADC_STATE_MULTIMODE_SLAVE   ((uint32_t)0x00100000)    /*!< ADC in multimode slave state, controlled by another ADC master */
-
-/**
-  * @}
-  */
-  
-/** 
-  * @brief  ADC Injection Configuration 
-  */
-typedef struct
-{
-  uint32_t ContextQueue;                 /*!< Injected channel configuration context: build-up over each 
-                                              HAL_ADCEx_InjectedConfigChannel() call to finally initialize
-                                              JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */
-                                               
-  uint32_t ChannelCount;                 /*!< Number of channels in the injected sequence */                                        
-}ADC_InjectionConfigTypeDef;  
-
-
-
-/** 
-  * @brief  ADC handle Structure definition  
-  */ 
-typedef struct
-{
-  ADC_TypeDef                   *Instance;              /*!< Register base address */
-
-  ADC_InitTypeDef               Init;                   /*!< ADC initialization parameters and regular conversions setting */
-
-  DMA_HandleTypeDef             *DMA_Handle;            /*!< Pointer DMA Handler */
-
-  HAL_LockTypeDef               Lock;                   /*!< ADC locking object */
-
-  __IO uint32_t                 State;                  /*!< ADC communication state (bit-map of ADC states) */
-
-  __IO uint32_t                 ErrorCode;              /*!< ADC Error code */
-  
-  ADC_InjectionConfigTypeDef    InjectionConfig ;       /*!< ADC injected channel configuration build-up structure */  
-}ADC_HandleTypeDef;
-
-
-
-/** 
-  * @brief  Structure definition of ADC channel for regular group  
-  * @note   The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned by ADC state.
-  *         ADC state can be either:
-  *          - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff')
-  *          - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group.
-  *          - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups.
-  *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
-  *         without error reporting (as it can be the expected behaviour in case of intended action to update another parameter 
-  *        (which fulfills the ADC state condition) on the fly).
-  */
-typedef struct 
-{
-  uint32_t Channel;                /*!< Specifies the channel to configure into ADC regular group.
-                                        This parameter can be a value of @ref ADC_channels
-                                        Note: Depending on devices and ADC instances, some channels may not be available. Refer to device DataSheet for channels availability. */
-  uint32_t Rank;                   /*!< Specifies the rank in the regular group sequencer.
-                                        This parameter can be a value of @ref ADCEx_regular_rank
-                                        Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by 
-                                        the new channel setting (or parameter number of conversions adjusted) */
-  uint32_t SamplingTime;           /*!< Sampling time value to be set for the selected channel.
-                                        Unit: ADC clock cycles
-                                        Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 
-                                        8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
-                                        This parameter can be a value of @ref ADC_sampling_times
-                                        Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
-                                                 It overwrites the last setting.
-                                        Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
-                                              sampling time constraints must be respected (sampling time can be adjusted with respect to the ADC clock frequency and sampling time setting)
-                                              Refer to device DataSheet for timings values. */
-  uint32_t SingleDiff;             /*!< Selection of single-ended or differential input.
-                                        In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
-                                                              Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
-                                        This parameter must be a value of @ref ADCEx_SingleDifferential
-                                        Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
-                                                 It overwrites the last setting.
-                                        Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.
-                                        Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
-                                        Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
-                                              If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case 
-                                        of another parameter update on the fly) */
-  uint32_t OffsetNumber;           /*!< Selects the offset number
-                                        This parameter can be a value of @ref ADCEx_OffsetNumber
-                                        Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */
-  uint32_t Offset;                 /*!< Defines the offset to be subtracted from the raw converted data.
-                                        Offset value must be a positive number.
-                                        Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 
-                                        0x3FF, 0xFF or 0x3F respectively.
-                                        Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled 
-                                        without continuous mode or external trigger that could launch a conversion). */
-}ADC_ChannelConfTypeDef;
-
-
-/** 
-  * @brief  Structure definition of ADC analog watchdog
-  * @note   The setting of these parameters with function HAL_ADC_AnalogWDGConfig() is conditioned by ADC state.
-  *         ADC state can be either: ADC disabled or ADC enabled without conversion on going on regular and injected groups.
-  */
-typedef struct
-{
-  uint32_t WatchdogNumber;    /*!< Selects which ADC analog watchdog is applied to the selected channel.
-                                   For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode')
-                                   For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel)
-                                   This parameter can be a value of @ref ADCEx_analog_watchdog_number. */
-  uint32_t WatchdogMode;      /*!< For Analog Watchdog 1: Configures the ADC analog watchdog mode: single channel/overall group of channels, regular/injected group.
-                                   For Analog Watchdog 2 and 3: There is no configuration for overall group of channels as AWD1. Set value 'ADC_ANALOGWATCHDOG_NONE' to reset 
-                                   channels group programmed with parameter 'Channel', set any other value to program the channel(s) to be monitored.
-                                   This parameter can be a value of @ref ADCEx_analog_watchdog_mode. */
-  uint32_t Channel;           /*!< Selects which ADC channel to monitor by analog watchdog.
-                                   For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored).
-                                   For Analog Watchdog 2 and 3: Several channels can be monitored (successive calls of HAL_ADC_AnalogWDGConfig() must be done, one for each channel.
-                                   Channels group reset can be done by setting WatchdogMode to 'ADC_ANALOGWATCHDOG_NONE').
-                                   This parameter can be a value of @ref ADC_channels. */
-  uint32_t ITMode;            /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
-                                   This parameter can be set to ENABLE or DISABLE */
-  uint32_t HighThreshold;     /*!< Configures the ADC analog watchdog High threshold value.
-                                   Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 
-                                   0x3FF, 0xFF or 0x3F respectively.
-                                   Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits 
-                                         the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. */
-  uint32_t LowThreshold;      /*!< Configures the ADC analog watchdog Low threshold value.
-                                   Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
-                                   Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits 
-                                         the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. */
-}ADC_AnalogWDGConfTypeDef;
-
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup ADC_Exported_Constants ADC Exported Constants
-  * @{
-  */
-
-/** @defgroup ADC_Error_Code ADC Error Code
-  * @{
-  */
-#define HAL_ADC_ERROR_NONE         ((uint32_t)0x00)   /*!< No error                                 */
-#define HAL_ADC_ERROR_INTERNAL     ((uint32_t)0x01)   /*!< ADC IP internal error: problem of
-                                                          clocking, enable/disable, erroneous state */
-#define HAL_ADC_ERROR_OVR          ((uint32_t)0x02)   /*!< Overrun error                            */
-#define HAL_ADC_ERROR_DMA          ((uint32_t)0x04)   /*!< DMA transfer error                       */
-#define HAL_ADC_ERROR_JQOVF        ((uint32_t)0x08)   /*!< Injected context queue overflow error    */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
-  * @{
-  */
-#define ADC_CLOCK_SYNC_PCLK_DIV1      ((uint32_t)ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock not divided  */
-#define ADC_CLOCK_SYNC_PCLK_DIV2      ((uint32_t)ADC_CCR_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by 2 */
-#define ADC_CLOCK_SYNC_PCLK_DIV4      ((uint32_t)ADC_CCR_CKMODE)   /*!< ADC synchronous clock derived from AHB clock divided by 4 */
-
-#define ADC_CLOCKPRESCALER_PCLK_DIV1   ADC_CLOCK_SYNC_PCLK_DIV1    /*!< Obsolete naming, kept for compatibility with some other devices */
-#define ADC_CLOCKPRESCALER_PCLK_DIV2   ADC_CLOCK_SYNC_PCLK_DIV2    /*!< Obsolete naming, kept for compatibility with some other devices */
-#define ADC_CLOCKPRESCALER_PCLK_DIV4   ADC_CLOCK_SYNC_PCLK_DIV4    /*!< Obsolete naming, kept for compatibility with some other devices */
-
-#define ADC_CLOCK_ASYNC_DIV1       ((uint32_t)0x00000000)                                        /*!< ADC asynchronous clock not divided    */
-#define ADC_CLOCK_ASYNC_DIV2       ((uint32_t)ADC_CCR_PRESC_0)                                   /*!< ADC asynchronous clock divided by 2   */
-#define ADC_CLOCK_ASYNC_DIV4       ((uint32_t)ADC_CCR_PRESC_1)                                   /*!< ADC asynchronous clock divided by 4   */
-#define ADC_CLOCK_ASYNC_DIV6       ((uint32_t)(ADC_CCR_PRESC_1|ADC_CCR_PRESC_0))                 /*!< ADC asynchronous clock divided by 6   */
-#define ADC_CLOCK_ASYNC_DIV8       ((uint32_t)(ADC_CCR_PRESC_2))                                 /*!< ADC asynchronous clock divided by 8   */
-#define ADC_CLOCK_ASYNC_DIV10      ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_0))                 /*!< ADC asynchronous clock divided by 10  */
-#define ADC_CLOCK_ASYNC_DIV12      ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_1))                 /*!< ADC asynchronous clock divided by 12  */
-#define ADC_CLOCK_ASYNC_DIV16      ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_1|ADC_CCR_PRESC_0)) /*!< ADC asynchronous clock divided by 16  */
-#define ADC_CLOCK_ASYNC_DIV32      ((uint32_t)(ADC_CCR_PRESC_3))                                 /*!< ADC asynchronous clock divided by 32  */
-#define ADC_CLOCK_ASYNC_DIV64      ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_0))                 /*!< ADC asynchronous clock divided by 64  */
-#define ADC_CLOCK_ASYNC_DIV128     ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_1))                 /*!< ADC asynchronous clock divided by 128 */
-#define ADC_CLOCK_ASYNC_DIV256     ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_1|ADC_CCR_PRESC_0)) /*!< ADC asynchronous clock divided by 256 */
-/**
-  * @}
-  */
-  
-
-/** @defgroup ADC_Resolution ADC Resolution
-  * @{
-  */
-#define ADC_RESOLUTION_12B      ((uint32_t)0x00000000)          /*!< ADC 12-bit resolution */
-#define ADC_RESOLUTION_10B      ((uint32_t)ADC_CFGR_RES_0)      /*!< ADC 10-bit resolution */
-#define ADC_RESOLUTION_8B       ((uint32_t)ADC_CFGR_RES_1)      /*!< ADC 8-bit resolution  */
-#define ADC_RESOLUTION_6B       ((uint32_t)ADC_CFGR_RES)        /*!< ADC 6-bit resolution  */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Data_align ADC Data Alignment
-  * @{
-  */
-#define ADC_DATAALIGN_RIGHT      ((uint32_t)0x00000000)         /*!< Data right alignment */
-#define ADC_DATAALIGN_LEFT       ((uint32_t)ADC_CFGR_ALIGN)     /*!< Data left alignment  */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Scan_mode ADC Scan Mode
-  * @{
-  */
-#define ADC_SCAN_DISABLE         ((uint32_t)0x00000000)        /*!< Scan mode disabled */
-#define ADC_SCAN_ENABLE          ((uint32_t)0x00000001)        /*!< Scan mode enabled  */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Regular_External_Trigger_Source_Edge ADC External Trigger Source Edge for Regular Group
-  * @{
-  */
-#define ADC_EXTERNALTRIGCONVEDGE_NONE           ((uint32_t)0x00000000)        /*!< Regular conversions hardware trigger detection disabled                             */
-#define ADC_EXTERNALTRIGCONVEDGE_RISING         ((uint32_t)ADC_CFGR_EXTEN_0)  /*!< Regular conversions hardware trigger detection on the rising edge                   */
-#define ADC_EXTERNALTRIGCONVEDGE_FALLING        ((uint32_t)ADC_CFGR_EXTEN_1)  /*!< Regular conversions hardware trigger detection on the falling edge                  */
-#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING  ((uint32_t)ADC_CFGR_EXTEN)    /*!< Regular conversions hardware trigger detection on both the rising and falling edges */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Regular_External_Trigger_Source ADC External Trigger Source for Regular Group
-  * @{
-  */
-
-/* External triggers of ADC regular group */                                                    
-#define ADC_EXTERNALTRIG_T1_CC1           ((uint32_t)0x00000000)                                                  /*!< Event 0 triggers regular group conversion start  */
-#define ADC_EXTERNALTRIG_T1_CC2           ((uint32_t)ADC_CFGR_EXTSEL_0)                                           /*!< Event 1 triggers regular group conversion start  */
-#define ADC_EXTERNALTRIG_T1_CC3           ((uint32_t)ADC_CFGR_EXTSEL_1)                                           /*!< Event 2 triggers regular group conversion start  */
-#define ADC_EXTERNALTRIG_T2_CC2           ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))                     /*!< Event 3 triggers regular group conversion start  */
-#define ADC_EXTERNALTRIG_T3_TRGO          ((uint32_t)ADC_CFGR_EXTSEL_2)                                           /*!< Event 4 triggers regular group conversion start  */
-#define ADC_EXTERNALTRIG_T4_CC4           ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))                     /*!< Event 5 triggers regular group conversion start  */
-#define ADC_EXTERNALTRIG_EXT_IT11         ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))                     /*!< Event 6 triggers regular group conversion start  */
-#define ADC_EXTERNALTRIG_T8_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) /*!< Event 7 triggers regular group conversion start  */
-#define ADC_EXTERNALTRIG_T8_TRGO2         ((uint32_t) ADC_CFGR_EXTSEL_3)                                          /*!< Event 8 triggers regular group conversion start  */
-#define ADC_EXTERNALTRIG_T1_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))                     /*!< Event 9 triggers regular group conversion start  */
-#define ADC_EXTERNALTRIG_T1_TRGO2         ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))                     /*!< Event 10 triggers regular group conversion start */
-#define ADC_EXTERNALTRIG_T2_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) /*!< Event 11 triggers regular group conversion start */
-#define ADC_EXTERNALTRIG_T4_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2))                     /*!< Event 12 triggers regular group conversion start */
-#define ADC_EXTERNALTRIG_T6_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0)) /*!< Event 13 triggers regular group conversion start */
-#define ADC_EXTERNALTRIG_T15_TRGO         ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1)) /*!< Event 14 triggers regular group conversion start */
-#define ADC_EXTERNALTRIG_T3_CC4           ((uint32_t)ADC_CFGR_EXTSEL)                                             /*!< Event 15 triggers regular group conversion start */
-
-#define ADC_SOFTWARE_START                ((uint32_t)0x00000001)                                                  /*!< Software triggers regular group conversion start */
-/**
-  * @}
-  */
-
-
-/** @defgroup ADC_EOCSelection ADC End of Regular Sequence/Conversion 
-  * @{
-  */
-#define ADC_EOC_SINGLE_CONV         ((uint32_t) ADC_ISR_EOC)                 /*!< End of conversion flag  */
-#define ADC_EOC_SEQ_CONV            ((uint32_t) ADC_ISR_EOS)                 /*!< End of sequence flag    */
-#define ADC_EOC_SINGLE_SEQ_CONV     ((uint32_t)(ADC_ISR_EOC | ADC_ISR_EOS))  /*!< Reserved for future use */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Overrun ADC overrun
-  * @{
-  */
-#define ADC_OVR_DATA_PRESERVED             ((uint32_t)0x00000000)           /*!< Data preserved in case of overrun   */
-#define ADC_OVR_DATA_OVERWRITTEN           ((uint32_t)ADC_CFGR_OVRMOD)      /*!< Data overwritten in case of overrun */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_channels ADC Channels
-  * @{
-  */
-#define ADC_CHANNEL_0           ((uint32_t)(0x00000000))                                                            /*!< ADC channel 0  */
-#define ADC_CHANNEL_1           ((uint32_t)(ADC_SQR3_SQ10_0))                                                       /*!< ADC channel 1  */
-#define ADC_CHANNEL_2           ((uint32_t)(ADC_SQR3_SQ10_1))                                                       /*!< ADC channel 2  */
-#define ADC_CHANNEL_3           ((uint32_t)(ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))                                     /*!< ADC channel 3  */
-#define ADC_CHANNEL_4           ((uint32_t)(ADC_SQR3_SQ10_2))                                                       /*!< ADC channel 4  */
-#define ADC_CHANNEL_5           ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0))                                     /*!< ADC channel 5  */
-#define ADC_CHANNEL_6           ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1))                                     /*!< ADC channel 6  */
-#define ADC_CHANNEL_7           ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))                   /*!< ADC channel 7  */
-#define ADC_CHANNEL_8           ((uint32_t)(ADC_SQR3_SQ10_3))                                                       /*!< ADC channel 8  */
-#define ADC_CHANNEL_9           ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_0))                                     /*!< ADC channel 9  */
-#define ADC_CHANNEL_10          ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1))                                     /*!< ADC channel 10 */
-#define ADC_CHANNEL_11          ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))                   /*!< ADC channel 11 */
-#define ADC_CHANNEL_12          ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2))                                     /*!< ADC channel 12 */
-#define ADC_CHANNEL_13          ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0))                   /*!< ADC channel 13 */
-#define ADC_CHANNEL_14          ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1))                   /*!< ADC channel 14 */
-#define ADC_CHANNEL_15          ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0)) /*!< ADC channel 15 */
-#define ADC_CHANNEL_16          ((uint32_t)(ADC_SQR3_SQ10_4))                                                       /*!< ADC channel 16 */
-#define ADC_CHANNEL_17          ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_0))                                     /*!< ADC channel 17 */
-#define ADC_CHANNEL_18          ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_1))                                     /*!< ADC channel 18 */
-
-/* Note: VrefInt, TempSensor and Vbat internal channels are not available on all ADC's
-         (information present in Reference Manual) */ 
-#define ADC_CHANNEL_TEMPSENSOR  ADC_CHANNEL_17                                                                      /*!< ADC temperature sensor channel */
-#define ADC_CHANNEL_VBAT        ADC_CHANNEL_18                                                                      /*!< ADC Vbat channel               */
-#define ADC_CHANNEL_VREFINT     ADC_CHANNEL_0                                                                       /*!< ADC Vrefint channel            */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_sampling_times ADC Sampling Times
-  * @{
-  */
-#define ADC_SAMPLETIME_2CYCLES_5      ((uint32_t)0x00000000)                              /*!< Sampling time 2.5 ADC clock cycle    */
-#define ADC_SAMPLETIME_6CYCLES_5      ((uint32_t)ADC_SMPR2_SMP10_0)                       /*!< Sampling time 6.5 ADC clock cycles   */
-#define ADC_SAMPLETIME_12CYCLES_5     ((uint32_t)ADC_SMPR2_SMP10_1)                       /*!< Sampling time 12.5 ADC clock cycles  */
-#define ADC_SAMPLETIME_24CYCLES_5     ((uint32_t)(ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)) /*!< Sampling time 24.5 ADC clock cycles  */
-#define ADC_SAMPLETIME_47CYCLES_5     ((uint32_t)ADC_SMPR2_SMP10_2)                       /*!< Sampling time 47.5 ADC clock cycles  */
-#define ADC_SAMPLETIME_92CYCLES_5     ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0)) /*!< Sampling time 92.5 ADC clock cycles  */
-#define ADC_SAMPLETIME_247CYCLES_5    ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1)) /*!< Sampling time 247.5 ADC clock cycles */
-#define ADC_SAMPLETIME_640CYCLES_5    ((uint32_t)ADC_SMPR2_SMP10)                         /*!< Sampling time 640.5 ADC clock cycles */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-     
-/** @defgroup ADC_Private_Macro ADC Private Macros
-  * @{
-  */
-
-/**
-  * @brief Test if conversion trigger of regular group is software start
-  *        or external trigger.
-  * @param __HANDLE__: ADC handle.
-  * @retval SET (software start) or RESET (external trigger)
-  */
-#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__)                        \
-       (((__HANDLE__)->Instance->CFGR & ADC_CFGR_EXTEN) == RESET)
-        
-/**
-  * @brief Return resolution bits in CFGR register RES[1:0] field.
-  * @param __HANDLE__: ADC handle.
-  * @retval 2-bit field RES of CFGR register.
-  */
-#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)
-
-/**
-  * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").
-  * @param __HANDLE__: ADC handle.
-  * @retval None
-  */
-#define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) 
-
-/**
-  * @brief Verification of ADC state: enabled or disabled.
-  * @param __HANDLE__: ADC handle.
-  * @retval SET (ADC enabled) or RESET (ADC disabled)
-  */
-#define ADC_IS_ENABLE(__HANDLE__)                                                    \
-       (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
-          ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY)                  \
-        ) ? SET : RESET)
-
-         
-/**
-  * @brief Check if conversion is on going on regular group.
-  * @param __HANDLE__: ADC handle.
-  * @retval SET (conversion is on going) or RESET (no conversion is on going)
-  */
-#define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__)                    \
-       (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET             \
-        ) ? RESET : SET)
-        
-        
-/**
-  * @brief Simultaneously clear and set specific bits of the handle State.
-  * @note  ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
-  *        the first parameter is the ADC handle State, the second parameter is the
-  *        bit field to clear, the third and last parameter is the bit field to set.    
-  * @retval None
-  */
-#define ADC_STATE_CLR_SET MODIFY_REG
-
-/**
-  * @brief Verify that a given value is aligned with the ADC resolution range.
-  * @param __RESOLUTION__: ADC resolution (12, 10, 8 or 6 bits).
-  * @param __ADC_VALUE__: value checked against the resolution.     
-  * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__)
-  */  
-#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__)                                         \
-   ((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_VALUE__) <= ((uint32_t)0x0FFF))) || \
-    (((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_VALUE__) <= ((uint32_t)0x03FF))) || \
-    (((__RESOLUTION__) == ADC_RESOLUTION_8B)  && ((__ADC_VALUE__) <= ((uint32_t)0x00FF))) || \
-    (((__RESOLUTION__) == ADC_RESOLUTION_6B)  && ((__ADC_VALUE__) <= ((uint32_t)0x003F)))   )
-
-
-/**
-  * @brief Verify the length of the scheduled regular conversions group.
-  * @param __LENGTH__: number of programmed conversions.   
-  * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large)
-  */    
-#define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)16)))
-
-
-/**
-  * @brief Verify the number of scheduled regular conversions in discontinuous mode.
-  * @param NUMBER: number of scheduled regular conversions in discontinuous mode.  
-  * @retval SET (NUMBER is within the maximum number of regular conversions in discontinous mode) or RESET (NUMBER is null or too large)
-  */   
-#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
-
-
-/**
-  * @brief Verify the ADC clock setting.
-  * @param __ADC_CLOCK__: programmed ADC clock. 
-  * @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid)
-  */       
-#define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \
-                                              ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
-                                              ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
-                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1)     || \
-                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2)     || \
-                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4)     || \
-                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6)     || \
-                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8)     || \
-                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10)    || \
-                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12)    || \
-                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16)    || \
-                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32)    || \
-                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64)    || \
-                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128)   || \
-                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) )  
-	
-
-/**
-  * @brief Verify the ADC resolution setting.
-  * @param __RESOLUTION__: programmed ADC resolution. 
-  * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)
-  */  	
-#define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
-                                           ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
-                                           ((__RESOLUTION__) == ADC_RESOLUTION_8B)  || \
-                                           ((__RESOLUTION__) == ADC_RESOLUTION_6B)    )
-                             
-/**                          
-  * @brief Verify the ADC resolution setting when limited to 6 or 8 bits.
-  * @param __RESOLUTION__: programmed ADC resolution when limited to 6 or 8 bits. 
-  * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)
-  */ 
-#define IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B) || \
-                                                    ((__RESOLUTION__) == ADC_RESOLUTION_6B)   )
-
-/**
-  * @brief Verify the ADC converted data alignment.
-  * @param __ALIGN__: programmed ADC converted data alignment. 
-  * @retval SET (__ALIGN__ is a valid value) or RESET (__ALIGN__ is invalid)
-  */ 		
-#define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \
-                                      ((__ALIGN__) == ADC_DATAALIGN_LEFT)    )
-	
-
-/**
-  * @brief Verify the ADC scan mode.
-  * @param __SCAN_MODE__: programmed ADC scan mode.
-  * @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid)
-  */ 	
-#define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \
-                                         ((__SCAN_MODE__) == ADC_SCAN_ENABLE)    )	
-									 
-/**
-  * @brief Verify the ADC edge trigger setting for regular group.
-  * @param __EDGE__: programmed ADC edge trigger setting.
-  * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
-  */ 									 
-#define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE)         || \
-                                       ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING)       || \
-                                       ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING)      || \
-                                       ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)  )
-	
-	
-
-/**
-  * @brief Verify the ADC regular conversions external trigger.
-  * @param __REGTRIG__: programmed ADC regular conversions external trigger.
-  * @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid)
-  */ 
-#define IS_ADC_EXTTRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1)   || \
-                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2)   || \
-                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3)   || \
-                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2)   || \
-                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO)  || \
-                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4)   || \
-                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \
-                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO)  || \
-                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \
-                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO)  || \
-                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
-                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO)  || \
-                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO)  || \
-                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO)  || \
-                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \
-                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4)   || \
-                                                                                 \
-                                     ((__REGTRIG__) == ADC_SOFTWARE_START)           )	
-								 
-
-
-/**
-  * @brief Verify the ADC regular conversions check for converted data availability.
-  * @param __EOC_SELECTION__: converted data availability check.
-  * @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid)
-  */ 								 
-#define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV)    || \
-                                                 ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV)       || \
-                                                 ((__EOC_SELECTION__) == ADC_EOC_SINGLE_SEQ_CONV)  )
-	
-/**
-  * @brief Verify the ADC regular conversions overrun handling.
-  * @param __OVR__: ADC regular conversions overrun handling.
-  * @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid)
-  */ 		
-#define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED)  || \
-                                 ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN)  )	                                   
-	
-/**
-  * @brief Verify the ADC conversions sampling time.
-  * @param __TIME__: ADC conversions sampling time.
-  * @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid)
-  */
-#define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_2CYCLE_5)    || \
-                                      ((__TIME__) == ADC_SAMPLETIME_6CYCLES_5)   || \
-                                      ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5)  || \
-                                      ((__TIME__) == ADC_SAMPLETIME_24CYCLES_5)  || \
-                                      ((__TIME__) == ADC_SAMPLETIME_47CYCLES_5)  || \
-                                      ((__TIME__) == ADC_SAMPLETIME_92CYCLES_5)  || \
-                                      ((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \
-                                      ((__TIME__) == ADC_SAMPLETIME_640CYCLES_5)   )	     
-/**
-  * @}
-  */ 
-  
-  
-/* Private constants ---------------------------------------------------------*/  
-  
-/** @defgroup ADC_Private_Constants ADC Private Constants
-  * @{
-  */                         
-   
-/* Fixed timeout values for ADC conversion (including sampling time)        */
-/* Maximum sampling time is 640.5 ADC clock cycle (SMPx[2:0] = 0b111        */
-/* Maximum conversion time is 12.5 + Maximum sampling time                  */
-/*                       or 12.5  + 640.5 = 653 ADC clock cycles            */
-/* Minimum ADC Clock frequency is 0.14 MHz                                  */
-/* Maximum conversion time is                                               */
-/*              653 / 0.14 MHz = 4.66 ms                                    */
-#define ADC_STOP_CONVERSION_TIMEOUT     ((uint32_t) 5)      /*!< ADC stop time-out value */ 
-
-/* Delay for temperature sensor stabilization time.                         */
-/* Maximum delay is 120us (refer device datasheet, parameter tSTART).       */
-/* Unit: us                                                                 */
-#define ADC_TEMPSENSOR_DELAY_US         ((uint32_t) 120)
-
-/**
-  * @}
-  */ 
-
-/* Exported macros -----------------------------------------------------------*/
-         
-/** @defgroup ADC_Exported_Macro ADC Exported Macros
-  * @{
-  */
-      
-/** @brief  Reset ADC handle state.
-  * @param  __HANDLE__: ADC handle.
-  * @retval None
-  */
-#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)                                                                        
-         
-         
-/** @brief  Check whether the specified ADC interrupt source is enabled or not.
-  * @param __HANDLE__: ADC handle.
-  * @param __INTERRUPT__: ADC interrupt source to check
-  *          This parameter can be one of the following values:
-  *            @arg @ref ADC_IT_RDY,    ADC Ready (ADRDY) interrupt source
-  *            @arg @ref ADC_IT_EOSMP,  ADC End of Sampling interrupt source
-  *            @arg @ref ADC_IT_EOC,    ADC End of Regular Conversion interrupt source
-  *            @arg @ref ADC_IT_EOS,    ADC End of Regular sequence of Conversions interrupt source
-  *            @arg @ref ADC_IT_OVR,    ADC overrun interrupt source
-  *            @arg @ref ADC_IT_JEOC,   ADC End of Injected Conversion interrupt source
-  *            @arg @ref ADC_IT_JEOS,   ADC End of Injected sequence of Conversions interrupt source
-  *            @arg @ref ADC_IT_AWD1,   ADC Analog watchdog 1 interrupt source (main analog watchdog)
-  *            @arg @ref ADC_IT_AWD2,   ADC Analog watchdog 2 interrupt source (additional analog watchdog)
-  *            @arg @ref ADC_IT_AWD3,   ADC Analog watchdog 3 interrupt source (additional analog watchdog)
-  *            @arg @ref ADC_IT_JQOVF,  ADC Injected Context Queue Overflow interrupt source.  
-  * @retval State of interruption (SET or RESET)
-  */
-#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)                     \
-    (( ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)      \
-     )? SET : RESET                                                            \
-    )
-
-/**
-  * @brief Enable an ADC interrupt.
-  * @param __HANDLE__: ADC handle.
-  * @param __INTERRUPT__: ADC Interrupt to enable
-   *          This parameter can be one of the following values:
-  *            @arg @ref ADC_IT_RDY,    ADC Ready (ADRDY) interrupt source
-  *            @arg @ref ADC_IT_EOSMP,  ADC End of Sampling interrupt source
-  *            @arg @ref ADC_IT_EOC,    ADC End of Regular Conversion interrupt source
-  *            @arg @ref ADC_IT_EOS,    ADC End of Regular sequence of Conversions interrupt source
-  *            @arg @ref ADC_IT_OVR,    ADC overrun interrupt source
-  *            @arg @ref ADC_IT_JEOC,   ADC End of Injected Conversion interrupt source
-  *            @arg @ref ADC_IT_JEOS,   ADC End of Injected sequence of Conversions interrupt source
-  *            @arg @ref ADC_IT_AWD1,   ADC Analog watchdog 1 interrupt source (main analog watchdog)
-  *            @arg @ref ADC_IT_AWD2,   ADC Analog watchdog 2 interrupt source (additional analog watchdog)
-  *            @arg @ref ADC_IT_AWD3,  ADC Analog watchdog 3 interrupt source (additional analog watchdog)
-  *            @arg @ref ADC_IT_JQOVF,  ADC Injected Context Queue Overflow interrupt source. 
-  * @retval None
-  */
-#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
-
-/**
-  * @brief Disable an ADC interrupt.
-  * @param __HANDLE__: ADC handle.
-  * @param __INTERRUPT__: ADC Interrupt to disable
-  *            @arg @ref ADC_IT_RDY,    ADC Ready (ADRDY) interrupt source
-  *            @arg @ref ADC_IT_EOSMP,  ADC End of Sampling interrupt source
-  *            @arg @ref ADC_IT_EOC,    ADC End of Regular Conversion interrupt source
-  *            @arg @ref ADC_IT_EOS,    ADC End of Regular sequence of Conversions interrupt source
-  *            @arg @ref ADC_IT_OVR,    ADC overrun interrupt source
-  *            @arg @ref ADC_IT_JEOC,   ADC End of Injected Conversion interrupt source
-  *            @arg @ref ADC_IT_JEOS,   ADC End of Injected sequence of Conversions interrupt source
-  *            @arg @ref ADC_IT_AWD1,   ADC Analog watchdog 1 interrupt source (main analog watchdog)
-  *            @arg @ref ADC_IT_AWD2,   ADC Analog watchdog 2 interrupt source (additional analog watchdog)
-  *            @arg @ref ADC_IT_AWD3,   ADC Analog watchdog 3 interrupt source (additional analog watchdog)
-  *            @arg @ref ADC_IT_JQOVF,  ADC Injected Context Queue Overflow interrupt source. 
-  * @retval None
-  */
-#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
-
-/**
-  * @brief Check whether the specified ADC flag is set or not.
-  * @param __HANDLE__: ADC handle.
-  * @param __FLAG__: ADC flag to check
-  *        This parameter can be one of the following values:
-  *            @arg @ref ADC_FLAG_RDY,     ADC Ready (ADRDY) flag                              
-  *            @arg @ref ADC_FLAG_EOSMP,   ADC End of Sampling flag                            
-  *            @arg @ref ADC_FLAG_EOC,     ADC End of Regular Conversion flag                  
-  *            @arg @ref ADC_FLAG_EOS,     ADC End of Regular sequence of Conversions flag     
-  *            @arg @ref ADC_FLAG_OVR,     ADC overrun flag        
-  *            @arg @ref ADC_FLAG_JEOC,    ADC End of Injected Conversion flag                 
-  *            @arg @ref ADC_FLAG_JEOS,    ADC End of Injected sequence of Conversions flag    
-  *            @arg @ref ADC_FLAG_AWD1,    ADC Analog watchdog 1 flag (main analog watchdog)
-  *            @arg @ref ADC_FLAG_AWD2,    ADC Analog watchdog 2 flag (additional analog watchdog)
-  *            @arg @ref ADC_FLAG_AWD3,    ADC Analog watchdog 3 flag (additional analog watchdog)
-  *            @arg @ref ADC_FLAG_JQOVF,   ADC Injected Context Queue Overflow flag.            
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
-
-/**
-  * @brief Clear a specified ADC flag.
-  * @param __HANDLE__: ADC handle.
-  * @param __FLAG__: ADC flag to clear
-  *        This parameter can be one of the following values:
-  *            @arg @ref ADC_FLAG_RDY,     ADC Ready (ADRDY) flag                              
-  *            @arg @ref ADC_FLAG_EOSMP,   ADC End of Sampling flag                            
-  *            @arg @ref ADC_FLAG_EOC,     ADC End of Regular Conversion flag                  
-  *            @arg @ref ADC_FLAG_EOS,     ADC End of Regular sequence of Conversions flag     
-  *            @arg @ref ADC_FLAG_OVR,     ADC overrun flag        
-  *            @arg @ref ADC_FLAG_JEOC,    ADC End of Injected Conversion flag                 
-  *            @arg @ref ADC_FLAG_JEOS,    ADC End of Injected sequence of Conversions flag    
-  *            @arg @ref ADC_FLAG_AWD1,    ADC Analog watchdog 1 flag (main analog watchdog)
-  *            @arg @ref ADC_FLAG_AWD2,    ADC Analog watchdog 2 flag (additional analog watchdog)
-  *            @arg @ref ADC_FLAG_AWD3,    ADC Analog watchdog 3 flag (additional analog watchdog)
-  *            @arg @ref ADC_FLAG_JQOVF,   ADC Injected Context Queue Overflow flag.   
-  * @note  Bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR).
-  * @retval None
-  */
-#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR) = (__FLAG__))
-       
-
-/**
-  * @}
-  */
-
-/* Include ADC HAL Extended module */
-#include "stm32l4xx_hal_adc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup ADC_Exported_Functions ADC Exported Functions
-  * @{
-  */ 
-
-/** @addtogroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions 
- * @{
- */ 
-/* Initialization and de-initialization functions  **********************************/
-HAL_StatusTypeDef       HAL_ADC_Init(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef       HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
-void                    HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
-void                    HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
-/**
-  * @}
-  */
-
-/** @addtogroup ADC_Exported_Functions_Group2 Input and Output operation functions
- *  @brief    IO operation functions 
- * @{
- */ 
-/* Blocking mode: Polling */
-HAL_StatusTypeDef       HAL_ADC_Start(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef       HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef       HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
-HAL_StatusTypeDef       HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
-
-/* Non-blocking mode: Interruption */
-HAL_StatusTypeDef       HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef       HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
-
-/* Non-blocking mode: DMA */
-HAL_StatusTypeDef       HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
-HAL_StatusTypeDef       HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
-
-/* ADC retrieve conversion value intended to be used with polling or interruption */
-uint32_t                HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
-
-/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
-void                    HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
-void                    HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
-void                    HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
-void                    HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
-void                    HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
-/**
-  * @}
-  */
-
-/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
- *  @brief    Peripheral Control functions 
- * @{
- */ 
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef       HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
-HAL_StatusTypeDef       HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
- *  @brief   ADC Peripheral State functions 
- * @{
- */ 
-/* Peripheral State functions *************************************************/
-uint32_t      HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
-uint32_t      HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */   
-
-/* Private functions -----------------------------------------------------------*/
-/** @addtogroup ADC_Private_Functions ADC Private Functions
-  * @{
-  */
- 
-HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup);
-HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc);
-void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
-void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
-void ADC_DMAError(DMA_HandleTypeDef *hdma);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32L4xx_ADC_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/inc/stm32l4xx_hal_adc_ex.h b/stmhal/hal/l4/inc/stm32l4xx_hal_adc_ex.h
deleted file mode 100644
index c64c601c4e..0000000000
--- a/stmhal/hal/l4/inc/stm32l4xx_hal_adc_ex.h
+++ /dev/null
@@ -1,1494 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_adc_ex.h
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   Header file of ADC HAL extended module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L4xx_ADC_EX_H
-#define __STM32L4xx_ADC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-   
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup ADCEx ADCEx
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup ADCEx_Exported_Types ADC Extended Exported Types
-  * @{
-  */
-
-/** 
-  * @brief  ADC Injected Conversion Oversampling structure definition  
-  */
-typedef struct
-{
-  uint32_t Ratio;                         /*!< Configures the oversampling ratio.
-                                               This parameter can be a value of @ref ADCEx_Oversampling_Ratio */
-                                               
-  uint32_t RightBitShift;                 /*!< Configures the division coefficient for the Oversampler.
-                                               This parameter can be a value of @ref ADCEx_Right_Bit_Shift */
-}ADC_InjOversamplingTypeDef;  
-
-
-
-/** 
-  * @brief  Structure definition of ADC injected group and ADC channel for injected group  
-  * @note   Parameters of this structure are shared within 2 scopes:
-  *          - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset
-  *          - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
-  *            AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConvEdge, ExternalTrigInjecConv, InjecOversamplingMode, InjecOversampling.
-  * @note   The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned by ADC state.
-  *         ADC state can be either:
-  *          - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff')
-  *          - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group.
-  *          - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups.
-  *          - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going 
-  *            on regular and injected groups.
-  *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
-  *         without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
-  */
-typedef struct 
-{
-  uint32_t InjectedChannel;               /*!< Configure the ADC injected channel.
-                                               This parameter can be a value of @ref ADC_channels
-                                                Note: Depending on devices and ADC instances, some channels may not be available. Refer to device DataSheet for channels availability. */
-  uint32_t InjectedRank;                  /*!< The rank in the injected group sequencer.
-                                               This parameter must be a value of @ref ADCEx_injected_rank.
-                                               Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by 
-                                               the new channel setting (or parameter number of conversions adjusted). */
-  uint32_t InjectedSamplingTime;          /*!< Sampling time value to be set for the selected channel.
-                                               Unit: ADC clock cycles.
-                                               Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits,
-                                               8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
-                                               This parameter can be a value of @ref ADC_sampling_times.
-                                               Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
-                                                        It overwrites the last setting.
-                                               Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
-                                                     sampling time constraints must be respected (sampling time can be adjusted with respect to the ADC clock frequency and sampling time 
-                                                     setting). Refer to device DataSheet for timings values. */
-  uint32_t InjectedSingleDiff;            /*!< Selection of single-ended or differential input.
-                                               In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
-                                               Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
-                                               This parameter must be a value of @ref ADCEx_SingleDifferential.
-                                               Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
-                                                        It overwrites the last setting.
-                                               Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.
-                                               Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
-                                               Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
-                                               If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case 
-                                               of another parameter update on the fly) */
-  uint32_t InjectedOffsetNumber;          /*!< Selects the offset number.
-                                               This parameter can be a value of @ref ADCEx_OffsetNumber.
-                                               Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */
-  uint32_t InjectedOffset;                /*!< Defines the offset to be subtracted from the raw converted data.
-                                               Offset value must be a positive number.
-                                               Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 
-                                               0x3FF, 0xFF or 0x3F respectively.
-                                               Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled 
-                                               without continuous mode or external trigger that could launch a conversion). */
-  uint32_t InjectedNbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
-                                               To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
-                                               This parameter must be a number between Min_Data = 1 and Max_Data = 4.
-                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 
-                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
-  uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence 
-                                               subdivided in successive parts).
-                                               Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
-                                               Discontinuous mode can be enabled only if continuous mode is disabled. 
-                                               This parameter can be set to ENABLE or DISABLE.
-                                               Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
-                                               Note: For injected group, discontinuous mode converts the sequence channel by channel (only one channel at a time).
-                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 
-                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
-  uint32_t AutoInjectedConv;              /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
-                                               This parameter can be set to ENABLE or DISABLE.      
-                                               Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
-                                               Note: To use Automatic injected conversion, injected group external triggers must be disabled.
-                                               Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
-                                                     To maintain JAUTO always enabled, DMA must be configured in circular mode.
-                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 
-                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
-  uint32_t QueueInjectedContext;          /*!< Specifies whether the context queue feature is enabled.
-                                               This parameter can be set to ENABLE or DISABLE.
-                                               If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a
-                                               new injected context is set when queue is full, error is triggered by interruption and through function 
-                                               'HAL_ADCEx_InjectedQueueOverflowCallback'.
-                                               Caution: This feature request that the sequence is fully configured before injected conversion start.
-                                                        Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter.
-                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 
-                                                        configure a channel on injected group can impact the configuration of other channels previously set.
-                                               Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */
-  uint32_t ExternalTrigInjecConv;         /*!< Selects the external event used to trigger the conversion start of injected group.
-                                               If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
-                                               This parameter can be a value of @ref ADCEx_Injected_External_Trigger_Source.
-                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 
-                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
-  uint32_t ExternalTrigInjecConvEdge;     /*!< Selects the external trigger edge of injected group.
-                                               This parameter can be a value of @ref ADCEx_Injected_External_Trigger_Source_Edge.
-                                               If trigger edge is set to ADC_EXTERNALTRIGINJECCONV_EDGE_NONE, external triggers are disabled and software trigger is used instead.
-                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 
-                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
-                                                                                                
-  uint32_t InjecOversamplingMode;             /*!< Specifies whether the oversampling feature is enabled or disabled.
-                                              This parameter can be set to ENABLE or DISABLE.
-                                              Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
-                                              
-  ADC_InjOversamplingTypeDef  InjecOversampling;   /*!< Specifies the Oversampling parameters.
-                                                   Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled.    
-                                                   Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */                                                          
-}ADC_InjectionConfTypeDef;
-
-
-/** 
-  * @brief  Structure definition of ADC multimode
-  * @note   The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master and Slave ADCs).
-  *         Both Master and Slave ADCs must be disabled.
-  */
-typedef struct
-{
-  uint32_t Mode;              /*!< Configures the ADC to operate in independent or multimode. 
-                                   This parameter can be a value of @ref ADCEx_Common_mode. */
-  uint32_t DMAAccessMode;     /*!< Configures the DMA mode for multimode ADC:
-                                   selection whether 2 DMA channels (each ADC uses its own DMA channel) or 1 DMA channel (one DMA channel for both ADC, DMA of ADC master)
-                                   This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multimode. */
-  uint32_t TwoSamplingDelay;  /*!< Configures the Delay between 2 sampling phases.
-                                   This parameter can be a value of @ref ADCEx_delay_between_2_sampling_phases.
-                                   Delay range depends on selected resolution: 
-                                    from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits,
-                                    from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits.     */
-}ADC_MultiModeTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-  /** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants
-  * @{
-  */
-
-/** @defgroup ADCEx_SingleDifferential ADC Extended Single-ended/Differential input mode
-  * @{
-  */
-#define ADC_SINGLE_ENDED                ((uint32_t)0x00000000)       /*!< ADC channel set in single-ended input mode */
-#define ADC_DIFFERENTIAL_ENDED          ((uint32_t)ADC_CR_ADCALDIF)  /*!< ADC channel set in differential mode       */
-/**
-  * @}
-  */
-
-/** @defgroup ADCEx_OffsetNumber ADC Extended Offset Number
-  * @{
-  */
-#define ADC_OFFSET_NONE               ((uint32_t)0x00)     /*!< No offset correction                           */
-#define ADC_OFFSET_1                  ((uint32_t)0x01)     /*!< Offset correction to apply to a first channel  */
-#define ADC_OFFSET_2                  ((uint32_t)0x02)     /*!< Offset correction to apply to a second channel */
-#define ADC_OFFSET_3                  ((uint32_t)0x03)     /*!< Offset correction to apply to a third channel  */
-#define ADC_OFFSET_4                  ((uint32_t)0x04)     /*!< Offset correction to apply to a fourth channel */
-/**
-  * @}
-  */
-
-/** @defgroup ADCEx_regular_rank ADC Extended Regular Channel Rank
-  * @{
-  */
-#define ADC_REGULAR_RANK_1    ((uint32_t)0x00000001)       /*!< ADC regular conversion rank 1  */
-#define ADC_REGULAR_RANK_2    ((uint32_t)0x00000002)       /*!< ADC regular conversion rank 2  */
-#define ADC_REGULAR_RANK_3    ((uint32_t)0x00000003)       /*!< ADC regular conversion rank 3  */
-#define ADC_REGULAR_RANK_4    ((uint32_t)0x00000004)       /*!< ADC regular conversion rank 4  */
-#define ADC_REGULAR_RANK_5    ((uint32_t)0x00000005)       /*!< ADC regular conversion rank 5  */
-#define ADC_REGULAR_RANK_6    ((uint32_t)0x00000006)       /*!< ADC regular conversion rank 6  */
-#define ADC_REGULAR_RANK_7    ((uint32_t)0x00000007)       /*!< ADC regular conversion rank 7  */
-#define ADC_REGULAR_RANK_8    ((uint32_t)0x00000008)       /*!< ADC regular conversion rank 8  */
-#define ADC_REGULAR_RANK_9    ((uint32_t)0x00000009)       /*!< ADC regular conversion rank 9  */
-#define ADC_REGULAR_RANK_10   ((uint32_t)0x0000000A)       /*!< ADC regular conversion rank 10 */
-#define ADC_REGULAR_RANK_11   ((uint32_t)0x0000000B)       /*!< ADC regular conversion rank 11 */
-#define ADC_REGULAR_RANK_12   ((uint32_t)0x0000000C)       /*!< ADC regular conversion rank 12 */
-#define ADC_REGULAR_RANK_13   ((uint32_t)0x0000000D)       /*!< ADC regular conversion rank 13 */
-#define ADC_REGULAR_RANK_14   ((uint32_t)0x0000000E)       /*!< ADC regular conversion rank 14 */
-#define ADC_REGULAR_RANK_15   ((uint32_t)0x0000000F)       /*!< ADC regular conversion rank 15 */
-#define ADC_REGULAR_RANK_16   ((uint32_t)0x00000010)       /*!< ADC regular conversion rank 16 */
-/**
-  * @}
-  */
-
-/** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank
-  * @{
-  */
-#define ADC_INJECTED_RANK_1    ((uint32_t)0x00000001)      /*!< ADC injected conversion rank 1 */
-#define ADC_INJECTED_RANK_2    ((uint32_t)0x00000002)      /*!< ADC injected conversion rank 2 */
-#define ADC_INJECTED_RANK_3    ((uint32_t)0x00000003)      /*!< ADC injected conversion rank 3 */
-#define ADC_INJECTED_RANK_4    ((uint32_t)0x00000004)      /*!< ADC injected conversion rank 4 */
-/**injected
-  * @}
-  */
-                        
-/** @defgroup ADCEx_Injected_External_Trigger_Source_Edge ADC External Trigger Source Edge for Injected Group
-  * @{
-  */
-#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE           ((uint32_t)0x00000000)          /*!< Injected conversions hardware trigger detection disabled                             */ 
-#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING         ((uint32_t)ADC_JSQR_JEXTEN_0)   /*!< Injected conversions hardware trigger detection on the rising edge                   */ 
-#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING        ((uint32_t)ADC_JSQR_JEXTEN_1)   /*!< Injected conversions hardware trigger detection on the falling edge                  */ 
-#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING  ((uint32_t)ADC_JSQR_JEXTEN)     /*!< Injected conversions hardware trigger detection on both the rising and falling edges */ 
-/**
-  * @}
-  */
-
-/** @defgroup ADCEx_Injected_External_Trigger_Source ADC Extended External Trigger Source for Injected Group
-  * @{
-  */
-#define ADC_EXTERNALTRIGINJEC_T1_TRGO    ((uint32_t)0x00000000)                                                     /*!< Event 0 triggers injected group conversion start  */
-#define ADC_EXTERNALTRIGINJEC_T1_CC4     ((uint32_t)ADC_JSQR_JEXTSEL_0)                                             /*!< Event 1 triggers injected group conversion start  */
-#define ADC_EXTERNALTRIGINJEC_T2_TRGO    ((uint32_t)ADC_JSQR_JEXTSEL_1)                                             /*!< Event 2 triggers injected group conversion start  */
-#define ADC_EXTERNALTRIGINJEC_T2_CC1     ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))                      /*!< Event 3 triggers injected group conversion start  */
-#define ADC_EXTERNALTRIGINJEC_T3_CC4     ((uint32_t)ADC_JSQR_JEXTSEL_2)                                             /*!< Event 4 triggers injected group conversion start  */
-#define ADC_EXTERNALTRIGINJEC_T4_TRGO    ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))                      /*!< Event 5 triggers injected group conversion start  */
-#define ADC_EXTERNALTRIGINJEC_EXT_IT15   ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))                      /*!< Event 6 triggers injected group conversion start  */
-#define ADC_EXTERNALTRIGINJEC_T8_CC4     ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) /*!< Event 7 triggers injected group conversion start  */
-#define ADC_EXTERNALTRIGINJEC_T1_TRGO2   ((uint32_t)ADC_JSQR_JEXTSEL_3)                                             /*!< Event 8 triggers injected group conversion start  */
-#define ADC_EXTERNALTRIGINJEC_T8_TRGO    ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0))                      /*!< Event 9 triggers injected group conversion start  */
-#define ADC_EXTERNALTRIGINJEC_T8_TRGO2   ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1))                      /*!< Event 10 triggers injected group conversion start */
-#define ADC_EXTERNALTRIGINJEC_T3_CC3     ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) /*!< Event 11 triggers injected group conversion start */
-#define ADC_EXTERNALTRIGINJEC_T3_TRGO    ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2))                      /*!< Event 12 triggers injected group conversion start */
-#define ADC_EXTERNALTRIGINJEC_T3_CC1     ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0)) /*!< Event 13 triggers injected group conversion start */
-#define ADC_EXTERNALTRIGINJEC_T6_TRGO    ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1)) /*!< Event 14 triggers injected group conversion start */
-#define ADC_EXTERNALTRIGINJEC_T15_TRGO   ((uint32_t)ADC_JSQR_JEXTSEL)                                               /*!< Event 15 triggers injected group conversion start */
-
-#define ADC_INJECTED_SOFTWARE_START      ((uint32_t)0x00000001)                                                     /*!< Software triggers injected group conversion start */
-/**
-  * @}
-  */
-
-/** @defgroup ADCEx_Common_mode ADC Extended Dual ADC Mode
-  * @{
-  */
-#define ADC_MODE_INDEPENDENT                  ((uint32_t)(0x00000000))                                       /*!< Independent ADC conversions mode                           */
-#define ADC_DUALMODE_REGSIMULT_INJECSIMULT    ((uint32_t)(ADC_CCR_DUAL_0))                                   /*!< Combined regular simultaneous + injected simultaneous mode */
-#define ADC_DUALMODE_REGSIMULT_ALTERTRIG      ((uint32_t)(ADC_CCR_DUAL_1))                                   /*!< Combined regular simultaneous + alternate trigger mode     */
-#define ADC_DUALMODE_REGINTERL_INJECSIMULT    ((uint32_t)(ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0))                  /*!< Combined Interleaved mode + injected simultaneous mode     */
-#define ADC_DUALMODE_INJECSIMULT              ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0))                  /*!< Injected simultaneous mode only                            */
-#define ADC_DUALMODE_REGSIMULT                ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1))                  /*!< Regular simultaneous mode only                             */
-#define ADC_DUALMODE_INTERL                   ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0)) /*!< Interleaved mode only                                      */
-#define ADC_DUALMODE_ALTERTRIG                ((uint32_t)(ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0))                  /*!< Alternate trigger mode only                                */
-/**
-  * @}
-  */
-
-/** @defgroup ADCEx_Direct_memory_access_mode_for_multimode ADC Extended DMA Mode for Dual ADC Mode
-  * @{
-  */
-#define ADC_DMAACCESSMODE_DISABLED      ((uint32_t)0x00000000)       /*!< DMA multimode disabled: each ADC uses its own DMA channel */
-#define ADC_DMAACCESSMODE_12_10_BITS    ((uint32_t)ADC_CCR_MDMA_1)   /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution */
-#define ADC_DMAACCESSMODE_8_6_BITS      ((uint32_t)ADC_CCR_MDMA)     /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution */
-/**
-  * @}
-  */
-
-/** @defgroup ADCEx_delay_between_2_sampling_phases ADC Extended Delay Between 2 Sampling Phases
-  * @{
-  */
-#define ADC_TWOSAMPLINGDELAY_1CYCLE     ((uint32_t)(0x00000000))                                          /*!< 1 ADC clock cycle delay                                     */ 
-#define ADC_TWOSAMPLINGDELAY_2CYCLES    ((uint32_t)(ADC_CCR_DELAY_0))                                     /*!< 2 ADC clock cycles delay                                    */ 
-#define ADC_TWOSAMPLINGDELAY_3CYCLES    ((uint32_t)(ADC_CCR_DELAY_1))                                     /*!< 3 ADC clock cycles delay                                    */ 
-#define ADC_TWOSAMPLINGDELAY_4CYCLES    ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))                   /*!< 4 ADC clock cycles delay                                    */ 
-#define ADC_TWOSAMPLINGDELAY_5CYCLES    ((uint32_t)(ADC_CCR_DELAY_2))                                     /*!< 5 ADC clock cycles delay                                    */ 
-#define ADC_TWOSAMPLINGDELAY_6CYCLES    ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))                   /*!< 6 ADC clock cycles delay                                    */ 
-#define ADC_TWOSAMPLINGDELAY_7CYCLES    ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))                   /*!< 7 ADC clock cycles delay (lower for non 12-bit resolution)  */ 
-#define ADC_TWOSAMPLINGDELAY_8CYCLES    ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) /*!< 8 ADC clock cycles delay (lower for non 12-bit resolution)  */ 
-#define ADC_TWOSAMPLINGDELAY_9CYCLES    ((uint32_t)(ADC_CCR_DELAY_3))                                     /*!< 9 ADC clock cycles delay (lower for non 12-bit resolution)  */ 
-#define ADC_TWOSAMPLINGDELAY_10CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))                   /*!< 10 ADC clock cycles delay (lower for non 12-bit resolution) */ 
-#define ADC_TWOSAMPLINGDELAY_11CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))                   /*!< 11 ADC clock cycles delay (lower for non 12-bit resolution) */ 
-#define ADC_TWOSAMPLINGDELAY_12CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) /*!< 12 ADC clock cycles delay (lower for non 12-bit resolution) */ 
-/**
-  * @}
-  */
-
-/** @defgroup ADCEx_analog_watchdog_number ADC Extended Analog Watchdog Selection
-  * @{
-  */
-#define ADC_ANALOGWATCHDOG_1                    ((uint32_t)0x00000001)   /*!< Analog watchdog 1 selection */ 
-#define ADC_ANALOGWATCHDOG_2                    ((uint32_t)0x00000002)   /*!< Analog watchdog 2 selection */ 
-#define ADC_ANALOGWATCHDOG_3                    ((uint32_t)0x00000003)   /*!< Analog watchdog 3 selection */ 
-/**
-  * @}
-  */
-
-/** @defgroup ADCEx_analog_watchdog_mode ADC Extended Analog Watchdog Mode
-  * @{
-  */
-#define ADC_ANALOGWATCHDOG_NONE                 ((uint32_t) 0x00000000)                                             /*!< No analog watchdog selected                                             */
-#define ADC_ANALOGWATCHDOG_SINGLE_REG           ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN))                    /*!< Analog watchdog applied to a regular group single channel               */
-#define ADC_ANALOGWATCHDOG_SINGLE_INJEC         ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN))                   /*!< Analog watchdog applied to an injected group single channel             */
-#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC      ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)) /*!< Analog watchdog applied to a regular and injected groups single channel */
-#define ADC_ANALOGWATCHDOG_ALL_REG              ((uint32_t) ADC_CFGR_AWD1EN)                                        /*!< Analog watchdog applied to regular group all channels                   */
-#define ADC_ANALOGWATCHDOG_ALL_INJEC            ((uint32_t) ADC_CFGR_JAWD1EN)                                       /*!< Analog watchdog applied to injected group all channels                  */
-#define ADC_ANALOGWATCHDOG_ALL_REGINJEC         ((uint32_t)(ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN))                    /*!< Analog watchdog applied to regular and injected groups all channels     */
-/**
-  * @}
-  */
-
-/** @defgroup ADCEx_conversion_group ADC Extended Conversion Group
-  * @{
-  */                                                                                                            
-#define ADC_REGULAR_GROUP             ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS))                                 /*!< ADC regular group selection               */ 
-#define ADC_INJECTED_GROUP            ((uint32_t)(ADC_FLAG_JEOC | ADC_FLAG_JEOS))                               /*!< ADC injected group selection              */ 
-#define ADC_REGULAR_INJECTED_GROUP    ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS)) /*!< ADC regular and injected groups selection */ 
-/**
-  * @}
-  */
-
-/** @defgroup ADCEx_Event_type ADC Extended Event Type
-  * @{
-  */
-#define ADC_EOSMP_EVENT          ((uint32_t)ADC_FLAG_EOSMP) /*!< ADC End of Sampling event                                */
-#define ADC_AWD1_EVENT           ((uint32_t)ADC_FLAG_AWD1)  /*!< ADC Analog watchdog 1 event (main analog watchdog)       */
-#define ADC_AWD2_EVENT           ((uint32_t)ADC_FLAG_AWD2)  /*!< ADC Analog watchdog 2 event (additional analog watchdog) */
-#define ADC_AWD3_EVENT           ((uint32_t)ADC_FLAG_AWD3)  /*!< ADC Analog watchdog 3 event (additional analog watchdog) */
-#define ADC_OVR_EVENT            ((uint32_t)ADC_FLAG_OVR)   /*!< ADC overrun event                                        */
-#define ADC_JQOVF_EVENT          ((uint32_t)ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event                */
-
-#define ADC_AWD_EVENT            ADC_AWD1_EVENT      /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */
-/**
-  * @}
-  */
-
-/** @defgroup ADCEx_interrupts_definition ADC Extended Interrupts Definition
-  * @{
-  */
-#define ADC_IT_RDY           ADC_IER_ADRDY      /*!< ADC Ready (ADRDY) interrupt source */
-#define ADC_IT_EOSMP         ADC_IER_EOSMP      /*!< ADC End of sampling interrupt source */
-#define ADC_IT_EOC           ADC_IER_EOC        /*!< ADC End of regular conversion interrupt source */
-#define ADC_IT_EOS           ADC_IER_EOS        /*!< ADC End of regular sequence of conversions interrupt source */
-#define ADC_IT_OVR           ADC_IER_OVR        /*!< ADC overrun interrupt source */
-#define ADC_IT_JEOC          ADC_IER_JEOC       /*!< ADC End of injected conversion interrupt source */
-#define ADC_IT_JEOS          ADC_IER_JEOS       /*!< ADC End of injected sequence of conversions interrupt source */
-#define ADC_IT_AWD1          ADC_IER_AWD1       /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */
-#define ADC_IT_AWD2          ADC_IER_AWD2       /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */
-#define ADC_IT_AWD3          ADC_IER_AWD3       /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */
-#define ADC_IT_JQOVF         ADC_IER_JQOVF      /*!< ADC Injected Context Queue Overflow interrupt source */
-
-#define ADC_IT_AWD           ADC_IT_AWD1        /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */
-
-/**
-  * @}
-  */
-
-/** @defgroup ADCEx_flags_definition ADC Extended Flags Definition
-  * @{
-  */
-#define ADC_FLAG_RDY           ADC_ISR_ADRDY    /*!< ADC Ready (ADRDY) flag */
-#define ADC_FLAG_EOSMP         ADC_ISR_EOSMP    /*!< ADC End of Sampling flag */
-#define ADC_FLAG_EOC           ADC_ISR_EOC      /*!< ADC End of Regular Conversion flag */
-#define ADC_FLAG_EOS           ADC_ISR_EOS      /*!< ADC End of Regular sequence of Conversions flag */
-#define ADC_FLAG_OVR           ADC_ISR_OVR      /*!< ADC overrun flag */
-#define ADC_FLAG_JEOC          ADC_ISR_JEOC     /*!< ADC End of Injected Conversion flag */
-#define ADC_FLAG_JEOS          ADC_ISR_JEOS     /*!< ADC End of Injected sequence of Conversions flag */
-#define ADC_FLAG_AWD1          ADC_ISR_AWD1     /*!< ADC Analog watchdog 1 flag (main analog watchdog) */
-#define ADC_FLAG_AWD2          ADC_ISR_AWD2     /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */
-#define ADC_FLAG_AWD3          ADC_ISR_AWD3     /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */
-#define ADC_FLAG_JQOVF         ADC_ISR_JQOVF    /*!< ADC Injected Context Queue Overflow flag */
-
-#define ADC_FLAG_AWD           ADC_FLAG_AWD1    /*!< ADC Analog watchdog 1 flag: Naming for compatibility with other STM32 devices having only one analog watchdog */
-
-#define ADC_FLAG_ALL    (ADC_FLAG_RDY | ADC_FLAG_EOSMP | ADC_FLAG_EOC | ADC_FLAG_EOS |  \
-                         ADC_FLAG_JEOC | ADC_FLAG_JEOS | ADC_FLAG_OVR | ADC_FLAG_AWD1 | \
-                         ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | ADC_FLAG_JQOVF)   /*!< ADC all flags */
-
-/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx, JQOVF */
-#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_EOS  | ADC_FLAG_JEOC | ADC_FLAG_JEOS | \
-                               ADC_FLAG_OVR | ADC_FLAG_AWD1 | ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | \
-                               ADC_FLAG_JQOVF)                             /*!< ADC post-conversion all flags */
-
-/**
-  * @}
-  */
-
-       
-/** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank
-  * @{
-  */
-#define ADC_INJECTED_RANK_1    ((uint32_t)0x00000001)   /*!< ADC injected conversion rank 1 */
-#define ADC_INJECTED_RANK_2    ((uint32_t)0x00000002)   /*!< ADC injected conversion rank 2 */
-#define ADC_INJECTED_RANK_3    ((uint32_t)0x00000003)   /*!< ADC injected conversion rank 3 */
-#define ADC_INJECTED_RANK_4    ((uint32_t)0x00000004)   /*!< ADC injected conversion rank 4 */
-/**
-  * @}
-  */
-
-
-
-/** @defgroup ADCEx_Oversampling_Ratio    ADC Extended Oversampling Ratio
-  * @{
-  */
-
-#define ADC_OVERSAMPLING_RATIO_2      ((uint32_t)0x00000000)                            /*!<  ADC Oversampling ratio 2x   */
-#define ADC_OVERSAMPLING_RATIO_4      ((uint32_t)ADC_CFGR2_OVSR_0)                      /*!<  ADC Oversampling ratio 4x   */
-#define ADC_OVERSAMPLING_RATIO_8      ((uint32_t)ADC_CFGR2_OVSR_1)                      /*!<  ADC Oversampling ratio 8x   */
-#define ADC_OVERSAMPLING_RATIO_16     ((uint32_t)(ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0)) /*!<  ADC Oversampling ratio 16x  */
-#define ADC_OVERSAMPLING_RATIO_32     ((uint32_t)ADC_CFGR2_OVSR_2)                      /*!<  ADC Oversampling ratio 32x  */
-#define ADC_OVERSAMPLING_RATIO_64     ((uint32_t)(ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0)) /*!<  ADC Oversampling ratio 64x  */
-#define ADC_OVERSAMPLING_RATIO_128    ((uint32_t)(ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1)) /*!<  ADC Oversampling ratio 128x */
-#define ADC_OVERSAMPLING_RATIO_256    ((uint32_t)(ADC_CFGR2_OVSR))                      /*!<  ADC Oversampling ratio 256x */
-/**
-  * @}
-  */
-
-/** @defgroup ADCEx_Right_Bit_Shift   ADC Extended Oversampling Right Shift
-  * @{
-  */
-#define ADC_RIGHTBITSHIFT_NONE  ((uint32_t)0x00000000)                                               /*!<  ADC No bit shift for oversampling */
-#define ADC_RIGHTBITSHIFT_1     ((uint32_t)ADC_CFGR2_OVSS_0)                                         /*!<  ADC 1 bit shift for oversampling  */
-#define ADC_RIGHTBITSHIFT_2     ((uint32_t)ADC_CFGR2_OVSS_1)                                         /*!<  ADC 2 bits shift for oversampling */
-#define ADC_RIGHTBITSHIFT_3     ((uint32_t)(ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0))                    /*!<  ADC 3 bits shift for oversampling */
-#define ADC_RIGHTBITSHIFT_4     ((uint32_t)ADC_CFGR2_OVSS_2)                                         /*!<  ADC 4 bits shift for oversampling */
-#define ADC_RIGHTBITSHIFT_5     ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0))                    /*!<  ADC 5 bits shift for oversampling */
-#define ADC_RIGHTBITSHIFT_6     ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1))                    /*!<  ADC 6 bits shift for oversampling */
-#define ADC_RIGHTBITSHIFT_7     ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)) /*!<  ADC 7 bits shift for oversampling */
-#define ADC_RIGHTBITSHIFT_8     ((uint32_t)ADC_CFGR2_OVSS_3)                                         /*!<  ADC 8 bits shift for oversampling */
-/**
-  * @}
-  */
-
-/** @defgroup ADCEx_Triggered_Oversampling_Mode   ADC Extended Triggered Regular Oversampling
-  * @{
-  */
-#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER      ((uint32_t)0x00000000)      /*!<  A single trigger for all channel oversampled conversions */
-#define ADC_TRIGGEREDMODE_MULTI_TRIGGER       ((uint32_t)ADC_CFGR2_TROVS) /*!<  A trigger for each oversampled conversion                */
-/**
-  * @}
-  */
-  
-/** @defgroup ADCEx_Regular_Oversampling_Mode   ADC Extended Regular Oversampling Continued or Resumed Mode
-  * @{
-  */
-#define ADC_REGOVERSAMPLING_CONTINUED_MODE    ((uint32_t)0x00000000)      /*!<  Oversampling buffer maintained during injection sequence */
-#define ADC_REGOVERSAMPLING_RESUMED_MODE      ((uint32_t)ADC_CFGR2_ROVSM) /*!<  Oversampling buffer zeroed during injection sequence     */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_CFGR_fields ADCx CFGR fields
-  * @{
-  */
-#define ADC_CFGR_FIELDS    (ADC_CFGR_AWD1CH  | ADC_CFGR_JAUTO   | ADC_CFGR_JAWD1EN |\
-                            ADC_CFGR_AWD1EN  | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM     |\
-                            ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN  |\
-                            ADC_CFGR_AUTDLY  | ADC_CFGR_CONT    | ADC_CFGR_OVRMOD  |\
-                            ADC_CFGR_EXTEN   | ADC_CFGR_EXTSEL  | ADC_CFGR_ALIGN   |\
-                            ADC_CFGR_RES     | ADC_CFGR_DMACFG  | ADC_CFGR_DMAEN   )
-/**
-  * @}
-  */  
-  
-/** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields
-  * @{
-  */
-#define ADC_SMPR1_FIELDS    (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\
-                             ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\
-                             ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\
-                             ADC_SMPR1_SMP0) 
-/**
-  * @}
-  */ 
-  
-/** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields 
-  * @{
-  */
-/* ADC_CFGR fields of parameters that can be updated when no conversion
-   (neither regular nor injected) is on-going  */  
-#define ADC_CFGR_FIELDS_2  ((uint32_t)(ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY))
-/**
-  * @}
-  */ 
-  
-/**
-  * @}
-  */
-
-
-
-/* Private macros -----------------------------------------------------------*/
-
-/** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros
-  * @{
-  */
-  
-/**
-  * @brief Test if conversion trigger of injected group is software start
-  *        or external trigger.
-  * @param __HANDLE__: ADC handle.
-  * @retval SET (software start) or RESET (external trigger).
-  */
-#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__)                       \
-       (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == RESET)
-
-/**
-  * @brief Check if conversion is on going on regular or injected groups.
-  * @param __HANDLE__: ADC handle.
-  * @retval SET (conversion is on going) or RESET (no conversion is on going).
-  */
-#define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__)                    \
-       (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == RESET  \
-        ) ? RESET : SET)
-        
-
-/**
-  * @brief Check if conversion is on going on injected group.
-  * @param __HANDLE__: ADC handle.
-  * @retval SET (conversion is on going) or RESET (no conversion is on going).
-  */
-#define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__)                   \
-       (( (((__HANDLE__)->Instance->CR) & ADC_CR_JADSTART) == RESET            \
-        ) ? RESET : SET)  
-                      
-
-        
-/**
-  * @brief Check whether or not ADC is independent.
-  * @param __HANDLE__: ADC handle.
-  * @retval SET (ADC is independent) or RESET (ADC is not).
-  */
-#define ADC_IS_INDEPENDENT(__HANDLE__)    \
-  ( ( ( ((__HANDLE__)->Instance) == ADC3) \
-    )?                                    \
-     SET                                  \
-     :                                    \
-     RESET                                \
-  ) 
-      
-
-/**
-  * @brief Set the sample time for Channels numbers between 0 and 9.
-  * @param __SAMPLETIME__: Sample time parameter.
-  * @param __CHANNELNB__: Channel number.  
-  * @retval None
-  */
-#define ADC_SMPR1(__SAMPLETIME__, __CHANNELNB__) ((__SAMPLETIME__) << (POSITION_VAL(ADC_SMPR1_SMP1) * (__CHANNELNB__)))
-    
-/**
-  * @brief Set the sample time for Channels numbers between 10 and 18.
-  * @param __SAMPLETIME__: Sample time parameter.
-  * @param __CHANNELNB__: Channel number.  
-  * @retval None
-  */
-#define ADC_SMPR2(__SAMPLETIME__, __CHANNELNB__) ((__SAMPLETIME__) << ((POSITION_VAL(ADC_SMPR2_SMP11) * ((__CHANNELNB__) - 10))))
-
-/**
-  * @brief Write SMPR1 register.
-  * @param __HANDLE__    : ADC handle.
-  * @param __SAMPLETIME__: Sample time parameter.
-  * @param __CHANNELNB__ : Channel number.  
-  * @retval None
-  */
-#define ADC_SMPR1_SETTING(__HANDLE__, __SAMPLETIME__, __CHANNELNB__)           \
-                    MODIFY_REG((__HANDLE__)->Instance->SMPR1,                  \
-                               ADC_SMPR1(ADC_SMPR1_SMP0, (__CHANNELNB__)),     \
-                               ADC_SMPR1((__SAMPLETIME__), (__CHANNELNB__)))
-
-/**
-  * @brief Write SMPR2 register.
-  * @param __HANDLE__    : ADC handle.
-  * @param __SAMPLETIME__: Sample time parameter.
-  * @param __CHANNELNB__ : Channel number.  
-  * @retval None
-  */
-#define ADC_SMPR2_SETTING(__HANDLE__, __SAMPLETIME__, __CHANNELNB__)           \
-                    MODIFY_REG((__HANDLE__)->Instance->SMPR2,                  \
-                               ADC_SMPR2(ADC_SMPR2_SMP10, (__CHANNELNB__)),    \
-                               ADC_SMPR2((__SAMPLETIME__), (__CHANNELNB__)))
-
-
-/**
-  * @brief Set the selected regular Channel rank for rank between 1 and 4.
-  * @param __CHANNELNB__: Channel number.
-  * @param __RANKNB__: Rank number.    
-  * @retval None
-  */                                                                   
-#define ADC_SQR1_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR1_SQ1) * (__RANKNB__)))
-
-/**
-  * @brief Set the selected regular Channel rank for rank between 5 and 9.
-  * @param __CHANNELNB__: Channel number.
-  * @param __RANKNB__: Rank number.    
-  * @retval None
-  */
-#define ADC_SQR2_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR2_SQ6) * ((__RANKNB__) - 5)))
-
-/**
-  * @brief Set the selected regular Channel rank for rank between 10 and 14.
-  * @param __CHANNELNB__: Channel number.
-  * @param __RANKNB__: Rank number.    
-  * @retval None
-  */
-#define ADC_SQR3_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR3_SQ11) * ((__RANKNB__) - 10)))
-
-/**
-  * @brief Set the selected regular Channel rank for rank between 15 and 16.
-  * @param __CHANNELNB__: Channel number.
-  * @param __RANKNB__: Rank number.    
-  * @retval None
-  */
-#define ADC_SQR4_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR4_SQ16) * ((__RANKNB__) - 15)))
-
-/**
-  * @brief Set the selected injected Channel rank.
-  * @param __CHANNELNB__: Channel number.
-  * @param __RANKNB__: Rank number.   
-  * @retval None
-  */
-#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << ((POSITION_VAL(ADC_JSQR_JSQ1)-2) * (__RANKNB__) +2))
-
-
-/**
-  * @brief Set the Analog Watchdog 1 channel.
-  * @param __CHANNEL__: channel to be monitored by Analog Watchdog 1.
-  * @retval None
-  */
-#define ADC_CFGR_SET_AWD1CH(__CHANNEL__) ((__CHANNEL__) << POSITION_VAL(ADC_CFGR_AWD1CH))
-
-/**
-  * @brief Configure the channel number in Analog Watchdog 2 or 3.
-  * @param __CHANNEL__: ADC Channel
-  * @retval None
-  */
-#define ADC_CFGR_SET_AWD23CR(__CHANNEL__) (1U << (__CHANNEL__)) 
-
-/**
-  * @brief Configure ADC injected context queue
-  * @param __INJECT_CONTEXT_QUEUE_MODE__: Injected context queue mode.
-  * @retval None
-  */                                                                                            
-#define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << POSITION_VAL(ADC_CFGR_JQM))
-
-/**
-  * @brief Configure ADC discontinuous conversion mode for injected group
-  * @param __INJECT_DISCONTINUOUS_MODE__: Injected discontinuous mode.
-  * @retval None
-  */
-#define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) <<  POSITION_VAL(ADC_CFGR_JDISCEN))
-
-/**
-  * @brief Configure ADC discontinuous conversion mode for regular group
-  * @param __REG_DISCONTINUOUS_MODE__: Regular discontinuous mode.
-  * @retval None
-  */                                                                                                  
-#define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_DISCEN))
-/**
-  * @brief Configure the number of discontinuous conversions for regular group.
-  * @param __NBR_DISCONTINUOUS_CONV__: Number of discontinuous conversions.
-  * @retval None
-  */
-#define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1) << POSITION_VAL(ADC_CFGR_DISCNUM))
-
-/**
-  * @brief Configure the ADC auto delay mode.
-  * @param __AUTOWAIT__: Auto delay bit enable or disable.
-  * @retval None
-  */
-#define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << POSITION_VAL(ADC_CFGR_AUTDLY))
-
-/**
-  * @brief Configure ADC continuous conversion mode.
-  * @param __CONTINUOUS_MODE__: Continuous mode.
-  * @retval None
-  */
-#define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_CONT))
-    
-/**
-  * @brief Configure the ADC DMA continuous request.
-  * @param __DMACONTREQ_MODE__: DMA continuous request mode.
-  * @retval None
-  */                                                                              
-#define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) <<  POSITION_VAL(ADC_CFGR_DMACFG))
-
-
-/**
-  * @brief Configure the channel number into offset OFRx register.
-  * @param __CHANNEL__: ADC Channel.
-  * @retval None
-  */
-#define ADC_OFR_CHANNEL(__CHANNEL__) ((__CHANNEL__) << POSITION_VAL(ADC_OFR1_OFFSET1_CH))
-
-/**
-  * @brief Configure the channel number into differential mode selection register.
-  * @param __CHANNEL__: ADC Channel.
-  * @retval None
-  */
-#define ADC_DIFSEL_CHANNEL(__CHANNEL__) (1U << (__CHANNEL__)) 
-
-/**
-  * @brief Configure calibration factor in differential mode to be set into calibration register.
-  * @param __CALIBRATION_FACTOR__: Calibration factor value.
-  * @retval None
-  */
-#define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D >> POSITION_VAL(ADC_CALFACT_CALFACT_D)) ) << POSITION_VAL(ADC_CALFACT_CALFACT_D))
-/**
-  * @brief Calibration factor in differential mode to be retrieved from calibration register.
-  * @param __CALIBRATION_FACTOR__: Calibration factor value.
-  * @retval None
-  */                                                                                
-#define ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) >> POSITION_VAL(ADC_CALFACT_CALFACT_D))
-     
-/**
-  * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
-  * @param __THRESHOLD__: Threshold value.
-  * @retval None
-  */
-#define ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16)
-
-/**
-  * @brief Configure the ADC DMA continuous request for ADC multimode.
-  * @param __DMACONTREQ_MODE__: DMA continuous request mode.
-  * @retval None
-  */                                                                               
-#define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << POSITION_VAL(ADC_CCR_DMACFG))
-
-/**
-  * @brief Enable the ADC peripheral.
-  * @param __HANDLE__: ADC handle.
-  * @retval None
-  */
-#define ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN)
-
-/**
-  * @brief Verification of hardware constraints before ADC can be enabled.
-  * @param __HANDLE__: ADC handle.
-  * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled)
-  */
-#define ADC_ENABLING_CONDITIONS(__HANDLE__)                             \
-       (( ( ((__HANDLE__)->Instance->CR) &                                    \
-            (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART |  \
-             ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN                    ) \
-           ) == RESET                                                         \
-        ) ? SET : RESET)
-         
-/**
-  * @brief Disable the ADC peripheral.
-  * @param __HANDLE__: ADC handle.
-  * @retval None
-  */
-#define ADC_DISABLE(__HANDLE__)                                          \
-  do{                                                                          \
-         (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS;                           \
-          __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \
-  } while(0)
-    
-/**
-  * @brief Verification of hardware constraints before ADC can be disabled.
-  * @param __HANDLE__: ADC handle.
-  * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled)
-  */
-#define ADC_DISABLING_CONDITIONS(__HANDLE__)                             \
-       (( ( ((__HANDLE__)->Instance->CR) &                                     \
-            (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN   \
-        ) ? SET : RESET)
-         
-
-/**
-  * @brief Shift the offset with respect to the selected ADC resolution. 
-  * @note   Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0.
-  *         If resolution 12 bits, no shift.
-  *         If resolution 10 bits, shift of 2 ranks on the left.
-  *         If resolution 8 bits, shift of 4 ranks on the left.
-  *         If resolution 6 bits, shift of 6 ranks on the left.
-  *         Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
-  * @param __HANDLE__: ADC handle
-  * @param __OFFSET__: Value to be shifted
-  * @retval None
-  */
-#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \
-        ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))
-
-
-/**
-  * @brief Shift the AWD1 threshold with respect to the selected ADC resolution.
-  * @note  Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0.
-  *        If resolution 12 bits, no shift.
-  *        If resolution 10 bits, shift of 2 ranks on the left.
-  *        If resolution 8 bits, shift of 4 ranks on the left.
-  *        If resolution 6 bits, shift of 6 ranks on the left.
-  *        Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
-  * @param __HANDLE__: ADC handle
-  * @param __THRESHOLD__: Value to be shifted
-  * @retval None
-  */
-#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
-        ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))
-
-/**
-  * @brief Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution.
-  * @note  Thresholds have to be left-aligned on bit 7.
-  *        If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are discarded).
-  *        If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded).
-  *        If resolution 8 bits, no shift.
-  *        If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0).
-  * @param __HANDLE__: ADC handle
-  * @param __THRESHOLD__: Value to be shifted
-  * @retval None
-  */
-#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
-         ( ((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) ? \
-            ((__THRESHOLD__) >> (4- ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))) : \
-            (__THRESHOLD__) << 2 )
-
-        
-/**
-  * @brief Report ADC common register.
-  * @param __HANDLE__: ADC handle.
-  * @retval Common control register
-  */
-#define ADC_COMMON_REGISTER(__HANDLE__)   (ADC123_COMMON)       
-
-/**
-  * @brief Report Master Instance.
-  * @param __HANDLE__: ADC handle.
-  * @note return same instance if ADC of input handle is independent ADC.  
-  * @retval Master Instance
-  */
-#define ADC_MASTER_REGISTER(__HANDLE__)                                          \
-  ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3)) \
-    )?                                                                           \
-     ((__HANDLE__)->Instance)                                                    \
-     :                                                                           \
-     (ADC1)                                                                      \
-  )
-       
-
-/**
-  * @brief Clear Common Control Register.
-  * @param __HANDLE__: ADC handle.     
-  * @retval None
-  */
-#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(ADC_COMMON_REGISTER(__HANDLE__)->CCR, ADC_CCR_CKMODE | \
-                                                                                                      ADC_CCR_PRESC  | \
-                                                                                                      ADC_CCR_VBATEN | \
-                                                                                                      ADC_CCR_TSEN   | \
-                                                                                                      ADC_CCR_VREFEN | \
-                                                                                                      ADC_CCR_MDMA   | \
-                                                                                                      ADC_CCR_DMACFG | \
-                                                                                                      ADC_CCR_DELAY  | \
-                                                                                                      ADC_CCR_DUAL  )
-                                                      
-                                                      
-/**                                                   
-  * @brief Check whether or not dual conversions are enabled.
-  * @param __HANDLE__: ADC handle.
-  * @note Return RESET if ADC of input handle is independent ADC.   
-  * @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled)
-  */
-#define ADC_IS_DUAL_CONVERSION_ENABLE(__HANDLE__)                                \
-  ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \
-    )?                                                                           \
-     ( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT)  )          \
-     :                                                                           \
-     RESET                                                                       \
-  )
-       
-/**
-  * @brief Check whether or not dual regular conversions are enabled.
-  * @param __HANDLE__: ADC handle.
-  * @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled)
-  */
-#define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__)                        \
-  ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \
-    )?                                                                           \
-     ( (((ADC_COMMON_REGISTER(__HANDLE__))->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT)     &&      \
-       (((ADC_COMMON_REGISTER(__HANDLE__))->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_INJECSIMULT) &&      \
-       (((ADC_COMMON_REGISTER(__HANDLE__))->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_ALTERTRIG) )         \
-     :                                                                           \
-     RESET                                                                       \
-  )
-                        
-
-/**
-  * @brief Verification of condition for ADC start conversion: ADC must be in non-multimode or multimode with handle of ADC master.
-  * @param __HANDLE__: ADC handle.
-  * @retval SET (non-multimode or Master handle) or RESET (handle of Slave ADC in multimode)
-  */
-#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__)                        \
-  ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3)     \
-    )?                                                                         \
-     SET                                                                       \
-     :                                                                         \
-     ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == RESET)                            \
-  )
-  
-/**
-  * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled.
-  * @param __HANDLE__: ADC handle.
-  * @retval SET (Independent or Master, or Slave without dual regular conversions enabled) or RESET (Slave ADC with dual regular conversions enabled)
-  */
-#define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__)            \
-  ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3)  \
-    )?                                                                      \
-     SET                                                                    \
-     :                                                                      \
-     ( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT)     || \
-       ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \
-       ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) ))  
-
-/**
-  * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled.
-  * @param __HANDLE__: ADC handle.
-  * @retval SET (non-multimode or Master, or Slave without dual injected conversions enabled) or RESET (Slave ADC with dual injected conversions enabled)
-  */
-#define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__)          \
-  ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \
-    )?                                                                     \
-     SET                                                                   \
-     :                                                                     \
-     ( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT)    || \
-       ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT)  || \
-       ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) ))
-  
-/**
-  * @brief Verification of ADC state: enabled or disabled, directly checked on instance as input parameter.
-  * @param __INSTANCE__: ADC instance.
-  * @retval SET (ADC enabled) or RESET (ADC disabled)
-  */
-#define ADC_INSTANCE_IS_ENABLED(__INSTANCE__)                                       \
-       (( ((((__INSTANCE__)->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
-          ((((__INSTANCE__)->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY)                  \
-        ) ? SET : RESET)  
-  
-/**
-  * @brief Verification of enabled/disabled status of ADCs other than that associated to the input parameter handle.
-  * @param __HANDLE__: ADC handle.
-  * @retval SET (at least one other ADC is enabled) or RESET (no other ADC is enabled, all other ADCs are disabled)
-  */ 
-#define ADC_ANY_OTHER_ENABLED(__HANDLE__)                                   \
-  ( ( ((__HANDLE__)->Instance == ADC1)                                      \
-    )?                                                                      \
-     (ADC_INSTANCE_IS_ENABLED(ADC2)) || (ADC_INSTANCE_IS_ENABLED(ADC3))     \
-     :                                                                      \
-     ( ( ((__HANDLE__)->Instance == ADC2)                                   \
-       )?                                                                   \
-         (ADC_INSTANCE_IS_ENABLED(ADC1)) || (ADC_INSTANCE_IS_ENABLED(ADC3)) \
-        :                                                                   \
-          ADC_INSTANCE_IS_ENABLED(ADC1)) || (ADC_INSTANCE_IS_ENABLED(ADC2)) \
-     )
-
-
-/**
-  * @brief Set handle instance of the ADC slave associated to the ADC master.
-  * @param __HANDLE_MASTER__: ADC master handle.
-  * @param __HANDLE_SLAVE__: ADC slave handle.
-  * @note if __HANDLE_MASTER__ is the handle of a slave ADC (ADC2) or an independent ADC (ADC3), __HANDLE_SLAVE__ instance is set to NULL.
-  * @retval None
-  */
-#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__)             \
-  ( (((__HANDLE_MASTER__)->Instance == ADC1)) ? ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) ) 
- 
-
-/**
-  * @brief Check whether or not multimode is configured in DMA mode.
-  * @retval SET (multimode is configured in DMA mode) or RESET (DMA multimode is disabled)
-  */ 
-#define ADC_MULTIMODE_DMA_ENABLED()                                     \
-    ((READ_BIT(ADC123_COMMON->CCR, ADC_CCR_MDMA) == ADC_DMAACCESSMODE_12_10_BITS) \
-  || (READ_BIT(ADC123_COMMON->CCR, ADC_CCR_MDMA) == ADC_DMAACCESSMODE_8_6_BITS))  
- 
-
-/**
-  * @brief Verify the ADC instance connected to the temperature sensor.
-  * @param __HANDLE__: ADC handle.
-  * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
-  */  
-/*  The temperature sensor measurement path (channel 17) is available on ADC1 and ADC3 */                        
-#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__)  ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3))
-
-/**
-  * @brief Verify the ADC instance connected to the battery voltage VBAT.
-  * @param __HANDLE__: ADC handle.
-  * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
-  */  
-/*  The battery voltage measurement path (channel 18) is available on ADC1 and ADC3 */                        
-#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__)  ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3))
-
-/**
-  * @brief Verify the ADC instance connected to the internal voltage reference VREFINT.
-  * @param __HANDLE__: ADC handle.
-  * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
-  */  
-/*  The internal voltage reference  VREFINT measurement path (channel 0) is available on ADC1 */  
-#define ADC_VREFINT_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) == ADC1)
-
- 
-/**
-  * @brief Verify the length of scheduled injected conversions group.
-  * @param __LENGTH__: number of programmed conversions.   
-  * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large)
-  */  
-#define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)4)))
-  
-  
-/**
-  * @brief Calibration factor size verification (7 bits maximum).
-  * @param __CALIBRATION_FACTOR__: Calibration factor value.
-  * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)
-  */
-#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= ((uint32_t)0x7F))
-
- 
-/**
-  * @brief Verify the ADC channel setting.
-  * @param __HANDLE__: ADC handle.
-  * @param __CHANNEL__: programmed ADC channel. 
-  * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
-  */
-#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__)  (((((__HANDLE__)->Instance) == ADC1)  && \
-                                                         (((__CHANNEL__) == ADC_CHANNEL_VREFINT)     || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_1)           || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_2)           || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_3)           || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_4)           || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_5)           || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_6)           || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_7)           || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_8)           || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_9)           || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_10)          || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_11)          || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_12)          || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_13)          || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_14)          || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_15)          || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_16)          || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR)  || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_VBAT)))      || \
-                                                        ((((__HANDLE__)->Instance) == ADC2)  && \
-                                                         (((__CHANNEL__) == ADC_CHANNEL_1)           || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_2)           || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_3)           || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_4)           || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_5)           || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_6)           || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_7)           || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_8)           || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_9)           || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_10)          || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_11)          || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_12)          || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_13)          || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_14)          || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_15)          || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_16)          || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_17)          || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_18)))        || \
-                                                        ((((__HANDLE__)->Instance) == ADC3)  && \
-                                                         (((__CHANNEL__) == ADC_CHANNEL_1)           || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_2)           || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_3)           || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_4)           || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_6)           || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_7)           || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_8)           || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_9)           || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_10)          || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_11)          || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_12)          || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_13)          || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_14)          || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_15)          || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR)  || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_VBAT)   ))) 
- 
-/**
-  * @brief Verify the ADC channel setting in differential mode.
-  * @param __HANDLE__: ADC handle.
-  * @param __CHANNEL__: programmed ADC channel. 
-  * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
-  */  
-    /* For ADC1 and ADC2, channels 1 to 15 are available in differential mode, 
-                          channels 0, 16 to 18 can be only used in single-ended mode. 
-       For ADC3, channels 1 to 3 and 6 to 12 are available in differential mode,
-                 channels 4, 5 and 13 to 18 can only be used in single-ended mode.  */                         
-#define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__)  ((((((__HANDLE__)->Instance) == ADC1)   || \
-                                                         (((__HANDLE__)->Instance) == ADC2))  && \
-                                                         (((__CHANNEL__) == ADC_CHANNEL_1)    || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_2)    || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_3)    || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_4)    || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_5)    || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_6)    || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_7)    || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_8)    || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_9)    || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_10)   || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_11)   || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_12)   || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_13)   || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_14)   || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_15))) || \
-                                                        ((((__HANDLE__)->Instance) == ADC3)  && \
-                                                         (((__CHANNEL__) == ADC_CHANNEL_1)   || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_2)   || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_3)   || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_6)   || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_7)   || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_8)   || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_9)   || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_10)  || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_11)  || \
-                                                          ((__CHANNEL__) == ADC_CHANNEL_12)   )))
-                               
-/**                            
-  * @brief Verify the ADC single-ended input or differential mode setting.
-  * @param __SING_DIFF__: programmed channel setting. 
-  * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid)
-  */                           
-#define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED)      || \
-                                                   ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED)  )
-                               
-/**
-  * @brief Verify the ADC offset management setting.
-  * @param __OFFSET_NUMBER__: ADC offset management. 
-  * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid)
-  */ 
-#define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \
-                                                 ((__OFFSET_NUMBER__) == ADC_OFFSET_1)    || \
-                                                 ((__OFFSET_NUMBER__) == ADC_OFFSET_2)    || \
-                                                 ((__OFFSET_NUMBER__) == ADC_OFFSET_3)    || \
-                                                 ((__OFFSET_NUMBER__) == ADC_OFFSET_4)      ) 
-
-/**
-  * @brief Verify the ADC regular channel setting.
-  * @param __CHANNEL__: programmed ADC regular channel. 
-  * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
-  */
-#define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \
-                                          ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \
-                                          ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \
-                                          ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \
-                                          ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \
-                                          ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \
-                                          ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \
-                                          ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \
-                                          ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \
-                                          ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \
-                                          ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \
-                                          ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \
-                                          ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \
-                                          ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \
-                                          ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \
-                                          ((__CHANNEL__) == ADC_REGULAR_RANK_16)   )
-
-
-/**
-  * @brief Verify the ADC injected channel setting.
-  * @param __CHANNEL__: programmed ADC injected channel. 
-  * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
-  */
-#define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \
-                                           ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \
-                                           ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \
-                                           ((__CHANNEL__) == ADC_INJECTED_RANK_4)   ) 
-
-/**
-  * @brief Verify the ADC edge trigger setting for injected group.
-  * @param __EDGE__: programmed ADC edge trigger setting.
-  * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
-  */ 
-#define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)        || \
-                                           ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING)       || \
-                                           ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING)      || \
-                                           ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) 
-
-
-/**
-  * @brief Verify the ADC injected conversions external trigger.
-  * @param __INJTRIG__: programmed ADC injected conversions external trigger.
-  * @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid)
-  */ 
-#define IS_ADC_EXTTRIGINJEC(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO)     || \
-                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4)      || \
-                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO)     || \
-                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1)      || \
-                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4)      || \
-                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO)     || \
-                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15)    || \
-                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4)      || \
-                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2)    || \
-                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO)     || \
-                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2)    || \
-                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3)      || \
-                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO)     || \
-                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1)      || \
-                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO)     || \
-                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO)    || \
-                                                                                                  \
-                                          ((__INJTRIG__) == ADC_SOFTWARE_START)                   )  
-
-
-/**
-  * @brief Verify the ADC multimode setting.
-  * @param __MODE__: programmed ADC multimode setting.
-  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
-  */ 
-#define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT)          || \
-                               ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
-                               ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG)   || \
-                               ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \
-                               ((__MODE__) == ADC_DUALMODE_INJECSIMULT)           || \
-                               ((__MODE__) == ADC_DUALMODE_REGSIMULT)             || \
-                               ((__MODE__) == ADC_DUALMODE_INTERL)                || \
-                               ((__MODE__) == ADC_DUALMODE_ALTERTRIG)               ) 
-
-/**
-  * @brief Verify the ADC multimode DMA access setting.
-  * @param __MODE__: programmed ADC multimode DMA access setting.
-  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
-  */
-#define IS_ADC_DMA_ACCESS_MULTIMODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED)   || \
-                                               ((__MODE__) == ADC_DMAACCESSMODE_12_10_BITS) || \
-                                               ((__MODE__) == ADC_DMAACCESSMODE_8_6_BITS)     ) 
-
-/**
-  * @brief Verify the ADC multimode delay setting.
-  * @param __DELAY__: programmed ADC multimode delay setting.
-  * @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid)
-  */
-#define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE)   || \
-                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES)  || \
-                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES)  || \
-                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES)  || \
-                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES)  || \
-                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES)  || \
-                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES)  || \
-                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES)  || \
-                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES)  || \
-                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
-                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
-                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES)   ) 
-
-/**
-  * @brief Verify the ADC analog watchdog setting.
-  * @param __WATCHDOG__: programmed ADC analog watchdog setting.
-  * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid)
-  */
-#define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \
-                                                     ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \
-                                                     ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3)   ) 
-
-/**
-  * @brief Verify the ADC analog watchdog mode setting.
-  * @param __WATCHDOG_MODE__: programmed ADC analog watchdog mode setting.
-  * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid)
-  */
-#define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE)             || \
-                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG)       || \
-                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC)     || \
-                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)  || \
-                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG)          || \
-                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC)        || \
-                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)       ) 
-
-/**
-  * @brief Verify the ADC conversion (regular or injected or both).
-  * @param __CONVERSION__: ADC conversion group.
-  * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid)
-  */
-#define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP)     || \
-                                             ((__CONVERSION__) == ADC_INJECTED_GROUP)        || \
-                                             ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP)  )
-
-/**
-  * @brief Verify the ADC event type.
-  * @param __EVENT__: ADC event.
-  * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid)
-  */
-#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \
-                                     ((__EVENT__) == ADC_AWD_EVENT)    || \
-                                     ((__EVENT__) == ADC_AWD2_EVENT)   || \
-                                     ((__EVENT__) == ADC_AWD3_EVENT)   || \
-                                     ((__EVENT__) == ADC_OVR_EVENT)    || \
-                                     ((__EVENT__) == ADC_JQOVF_EVENT)  ) 
-
-/**
-  * @brief Verify the ADC oversampling ratio. 
-  * @param __RATIO__: programmed ADC oversampling ratio.
-  * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid)
-  */   
-#define IS_ADC_OVERSAMPLING_RATIO(__RATIO__)      (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2   ) || \
-                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4   ) || \
-                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8   ) || \
-                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16  ) || \
-                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32  ) || \
-                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64  ) || \
-                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \
-                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 ))
-
-/**
-  * @brief Verify the ADC oversampling shift. 
-  * @param __SHIFT__: programmed ADC oversampling shift.
-  * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid)
-  */                 
-#define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__)        (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \
-                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_1   ) || \
-                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_2   ) || \
-                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_3   ) || \
-                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_4   ) || \
-                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_5   ) || \
-                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_6   ) || \
-                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_7   ) || \
-                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_8   ))
-
-/**
-  * @brief Verify the ADC oversampling triggered mode. 
-  * @param __MODE__: programmed ADC oversampling triggered mode. 
-  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
-  */ 
-#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
-                                                      ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) 
-
-/**
-  * @brief Verify the ADC oversampling regular conversion resumed or continued mode. 
-  * @param __MODE__: programmed ADC oversampling regular conversion resumed or continued mode. 
-  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
-  */ 
-#define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \
-                                               ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) )              
-
- 
-
-                                                  
-/**
-  * @}
-  */
-
-
-/* Exported functions --------------------------------------------------------*/  
-/** @addtogroup ADCEx_Exported_Functions ADC Extended Exported Functions
-  * @{
-  */ 
-          
-/* Initialization/de-initialization functions *********************************/
-
-/** @addtogroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions
-  * @brief    Extended IO operation functions
-  * @{
-  */ 
-/* I/O operation functions ****************************************************/
-
-/* ADC calibration */
-
-HAL_StatusTypeDef       HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff);
-uint32_t                HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
-HAL_StatusTypeDef       HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor);
-
-
-
-/* Blocking mode: Polling */
-HAL_StatusTypeDef       HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef       HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef       HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
-
-/* Non-blocking mode: Interruption */
-HAL_StatusTypeDef       HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef       HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
-     
-
-/* ADC multimode */
-HAL_StatusTypeDef       HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
-HAL_StatusTypeDef       HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); 
-uint32_t                HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc);
-
-/* ADC retrieve conversion value intended to be used with polling or interruption */
-uint32_t                HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
-
-/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
-void                    HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
-void                    HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc);
-void                    HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc);
-void                    HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc);
-void                    HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef* hadc);
-
-
-/* ADC Regular conversions stop */
-HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc);
-
-/**
-  * @}
-  */
-     
-/** @addtogroup ADCEx_Exported_Functions_Group2 Extended Peripheral Control functions
-  * @brief    Extended Peripheral Control functions
-  * @{
-  */ 
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef       HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
-HAL_StatusTypeDef       HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);
-HAL_StatusTypeDef       HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef       HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef       HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef       HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef* hadc);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32L4xx_ADC_EX_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/inc/stm32l4xx_hal_can.h b/stmhal/hal/l4/inc/stm32l4xx_hal_can.h
deleted file mode 100644
index 6508069dcc..0000000000
--- a/stmhal/hal/l4/inc/stm32l4xx_hal_can.h
+++ /dev/null
@@ -1,768 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_can.h
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   Header file of CAN HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L4xx_CAN_H
-#define __STM32L4xx_CAN_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup CAN
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup CAN_Exported_Types CAN Exported Types
-  * @{
-  */
-
-/**
-  * @brief  HAL State structures definition
-  */
-typedef enum
-{
-  HAL_CAN_STATE_RESET             = 0x00,  /*!< CAN not yet initialized or disabled */
-  HAL_CAN_STATE_READY             = 0x01,  /*!< CAN initialized and ready for use   */
-  HAL_CAN_STATE_BUSY              = 0x02,  /*!< CAN process is ongoing              */
-  HAL_CAN_STATE_BUSY_TX           = 0x12,  /*!< CAN process is ongoing              */
-  HAL_CAN_STATE_BUSY_RX           = 0x22,  /*!< CAN process is ongoing              */
-  HAL_CAN_STATE_BUSY_TX_RX        = 0x32,  /*!< CAN process is ongoing              */
-  HAL_CAN_STATE_TIMEOUT           = 0x03,  /*!< Timeout state                       */
-  HAL_CAN_STATE_ERROR             = 0x04   /*!< CAN error state                     */
-
-}HAL_CAN_StateTypeDef;
-
-/**
-  * @brief  CAN init structure definition
-  */
-typedef struct
-{
-  uint32_t Prescaler;  /*!< Specifies the length of a time quantum.
-                            This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
-
-  uint32_t Mode;       /*!< Specifies the CAN operating mode.
-                            This parameter can be a value of @ref CAN_operating_mode */
-
-  uint32_t SJW;        /*!< Specifies the maximum number of time quanta
-                            the CAN hardware is allowed to lengthen or
-                            shorten a bit to perform resynchronization.
-                            This parameter can be a value of @ref CAN_synchronisation_jump_width */
-
-  uint32_t BS1;        /*!< Specifies the number of time quanta in Bit Segment 1.
-                            This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
-
-  uint32_t BS2;        /*!< Specifies the number of time quanta in Bit Segment 2.
-                            This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
-
-  uint32_t TTCM;       /*!< Enable or disable the time triggered communication mode.
-                            This parameter can be set to ENABLE or DISABLE. */
-
-  uint32_t ABOM;       /*!< Enable or disable the automatic bus-off management.
-                            This parameter can be set to ENABLE or DISABLE */
-
-  uint32_t AWUM;       /*!< Enable or disable the automatic wake-up mode.
-                            This parameter can be set to ENABLE or DISABLE */
-
-  uint32_t NART;       /*!< Enable or disable the non-automatic retransmission mode.
-                            This parameter can be set to ENABLE or DISABLE */
-
-  uint32_t RFLM;       /*!< Enable or disable the receive FIFO Locked mode.
-                            This parameter can be set to ENABLE or DISABLE */
-
-  uint32_t TXFP;       /*!< Enable or disable the transmit FIFO priority.
-                            This parameter can be set to ENABLE or DISABLE */
-}CAN_InitTypeDef;
-
-/**
-  * @brief  CAN filter configuration structure definition
-  */
-typedef struct
-{
-  uint32_t FilterIdHigh;          /*!< Specifies the filter identification number (MSBs for a 32-bit
-                                       configuration, first one for a 16-bit configuration).
-                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
-  uint32_t FilterIdLow;           /*!< Specifies the filter identification number (LSBs for a 32-bit
-                                       configuration, second one for a 16-bit configuration).
-                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
-  uint32_t FilterMaskIdHigh;      /*!< Specifies the filter mask number or identification number,
-                                       according to the mode (MSBs for a 32-bit configuration,
-                                       first one for a 16-bit configuration).
-                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
-  uint32_t FilterMaskIdLow;       /*!< Specifies the filter mask number or identification number,
-                                       according to the mode (LSBs for a 32-bit configuration,
-                                       second one for a 16-bit configuration).
-                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
-  uint32_t FilterFIFOAssignment;  /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
-                                       This parameter can be a value of @ref CAN_filter_FIFO */
-
-  uint32_t FilterNumber;          /*!< Specifies the filter which will be initialized.
-                                       This parameter must be a number between Min_Data = 0 and Max_Data = 27 */
-
-  uint32_t FilterMode;            /*!< Specifies the filter mode to be initialized.
-                                       This parameter can be a value of @ref CAN_filter_mode */
-
-  uint32_t FilterScale;           /*!< Specifies the filter scale.
-                                       This parameter can be a value of @ref CAN_filter_scale */
-
-  uint32_t FilterActivation;      /*!< Enable or disable the filter.
-                                       This parameter can be set to ENABLE or DISABLE */
-
-  uint32_t BankNumber;            /*!< Select the start slave bank filter.
-                                       This parameter must be a number between Min_Data = 0 and Max_Data = 28 */ 
-
-}CAN_FilterConfTypeDef;
-
-/**
-  * @brief  CAN Tx message structure definition
-  */
-typedef struct
-{
-  uint32_t StdId;    /*!< Specifies the standard identifier.
-                          This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
-
-  uint32_t ExtId;    /*!< Specifies the extended identifier.
-                          This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
-
-  uint32_t IDE;      /*!< Specifies the type of identifier for the message that will be transmitted.
-                          This parameter can be a value of @ref CAN_identifier_type */
-
-  uint32_t RTR;      /*!< Specifies the type of frame for the message that will be transmitted.
-                          This parameter can be a value of @ref CAN_remote_transmission_request */
-
-  uint32_t DLC;      /*!< Specifies the length of the frame that will be transmitted.
-                          This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
-
-  uint8_t Data[8];   /*!< Contains the data to be transmitted.
-                          This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
-
-}CanTxMsgTypeDef;
-
-/**
-  * @brief  CAN Rx message structure definition
-  */
-typedef struct
-{
-  uint32_t StdId;       /*!< Specifies the standard identifier.
-                             This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
-
-  uint32_t ExtId;       /*!< Specifies the extended identifier.
-                             This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
-
-  uint32_t IDE;         /*!< Specifies the type of identifier for the message that will be received.
-                             This parameter can be a value of @ref CAN_identifier_type */
-
-  uint32_t RTR;         /*!< Specifies the type of frame for the received message.
-                             This parameter can be a value of @ref CAN_remote_transmission_request */
-
-  uint32_t DLC;         /*!< Specifies the length of the frame that will be received.
-                             This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
-
-  uint32_t Data[8];     /*!< Contains the data to be received.
-                             This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
-
-  uint32_t FMI;         /*!< Specifies the index of the filter the message stored in the mailbox passes through.
-                             This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
-
-  uint32_t FIFONumber;  /*!< Specifies the receive FIFO number.
-                             This parameter can be CAN_FIFO0 or CAN_FIFO1 */
-
-}CanRxMsgTypeDef;
-
-/**
-  * @brief  CAN handle Structure definition
-  */
-typedef struct
-{
-  CAN_TypeDef                 *Instance;  /*!< Register base address          */
-
-  CAN_InitTypeDef             Init;       /*!< CAN required parameters        */
-
-  CanTxMsgTypeDef*            pTxMsg;     /*!< Pointer to transmit structure  */
-
-  CanRxMsgTypeDef*            pRxMsg;     /*!< Pointer to reception structure */
-
-  __IO HAL_CAN_StateTypeDef   State;      /*!< CAN communication state        */
-
-  HAL_LockTypeDef             Lock;       /*!< CAN locking object             */
-
-  __IO uint32_t               ErrorCode;  /*!< CAN Error code                 */
-
-}CAN_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CAN_Exported_Constants CAN Exported Constants
-  * @{
-  */
-
-/** @defgroup CAN_Error_Code CAN Error Code
-  * @{
-  */
-#define   HAL_CAN_ERROR_NONE        ((uint32_t)0x00000000)    /*!< No error             */
-#define   HAL_CAN_ERROR_EWG         ((uint32_t)0x00000001)    /*!< EWG error            */
-#define   HAL_CAN_ERROR_EPV         ((uint32_t)0x00000002)    /*!< EPV error            */
-#define   HAL_CAN_ERROR_BOF         ((uint32_t)0x00000004)    /*!< BOF error            */
-#define   HAL_CAN_ERROR_STF         ((uint32_t)0x00000008)    /*!< Stuff error          */
-#define   HAL_CAN_ERROR_FOR         ((uint32_t)0x00000010)    /*!< Form error           */
-#define   HAL_CAN_ERROR_ACK         ((uint32_t)0x00000020)    /*!< Acknowledgment error */
-#define   HAL_CAN_ERROR_BR          ((uint32_t)0x00000040)    /*!< Bit recessive        */
-#define   HAL_CAN_ERROR_BD          ((uint32_t)0x00000080)    /*!< LEC dominant         */
-#define   HAL_CAN_ERROR_CRC         ((uint32_t)0x00000100)   /*!< LEC transfer error   */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_InitStatus CAN initialization Status
-  * @{
-  */
-#define CAN_INITSTATUS_FAILED       ((uint32_t)0x00000000)  /*!< CAN initialization failed */
-#define CAN_INITSTATUS_SUCCESS      ((uint32_t)0x00000001)  /*!< CAN initialization OK */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_operating_mode CAN Operating Mode
-  * @{
-  */
-#define CAN_MODE_NORMAL             ((uint32_t)0x00000000)                     /*!< Normal mode   */
-#define CAN_MODE_LOOPBACK           ((uint32_t)CAN_BTR_LBKM)                   /*!< Loopback mode */
-#define CAN_MODE_SILENT             ((uint32_t)CAN_BTR_SILM)                   /*!< Silent mode   */
-#define CAN_MODE_SILENT_LOOPBACK    ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM))  /*!< Loopback combined with silent mode */
-/**
-  * @}
-  */
-
-
-/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
-  * @{
-  */
-#define CAN_SJW_1TQ                 ((uint32_t)0x00000000)     /*!< 1 time quantum */
-#define CAN_SJW_2TQ                 ((uint32_t)CAN_BTR_SJW_0)  /*!< 2 time quantum */
-#define CAN_SJW_3TQ                 ((uint32_t)CAN_BTR_SJW_1)  /*!< 3 time quantum */
-#define CAN_SJW_4TQ                 ((uint32_t)CAN_BTR_SJW)    /*!< 4 time quantum */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
-  * @{
-  */
-#define CAN_BS1_1TQ                 ((uint32_t)0x00000000)                                       /*!< 1 time quantum  */
-#define CAN_BS1_2TQ                 ((uint32_t)CAN_BTR_TS1_0)                                    /*!< 2 time quantum  */
-#define CAN_BS1_3TQ                 ((uint32_t)CAN_BTR_TS1_1)                                    /*!< 3 time quantum  */
-#define CAN_BS1_4TQ                 ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0))                  /*!< 4 time quantum  */
-#define CAN_BS1_5TQ                 ((uint32_t)CAN_BTR_TS1_2)                                    /*!< 5 time quantum  */
-#define CAN_BS1_6TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0))                  /*!< 6 time quantum  */
-#define CAN_BS1_7TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1))                  /*!< 7 time quantum  */
-#define CAN_BS1_8TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))  /*!< 8 time quantum  */
-#define CAN_BS1_9TQ                 ((uint32_t)CAN_BTR_TS1_3)                                    /*!< 9 time quantum  */
-#define CAN_BS1_10TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0))                  /*!< 10 time quantum */
-#define CAN_BS1_11TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1))                  /*!< 11 time quantum */
-#define CAN_BS1_12TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))  /*!< 12 time quantum */
-#define CAN_BS1_13TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2))                  /*!< 13 time quantum */
-#define CAN_BS1_14TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0))  /*!< 14 time quantum */
-#define CAN_BS1_15TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1))  /*!< 15 time quantum */
-#define CAN_BS1_16TQ                ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2
-  * @{
-  */
-#define CAN_BS2_1TQ                 ((uint32_t)0x00000000)                       /*!< 1 time quantum */
-#define CAN_BS2_2TQ                 ((uint32_t)CAN_BTR_TS2_0)                    /*!< 2 time quantum */
-#define CAN_BS2_3TQ                 ((uint32_t)CAN_BTR_TS2_1)                    /*!< 3 time quantum */
-#define CAN_BS2_4TQ                 ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0))  /*!< 4 time quantum */
-#define CAN_BS2_5TQ                 ((uint32_t)CAN_BTR_TS2_2)                    /*!< 5 time quantum */
-#define CAN_BS2_6TQ                 ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0))  /*!< 6 time quantum */
-#define CAN_BS2_7TQ                 ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1))  /*!< 7 time quantum */
-#define CAN_BS2_8TQ                 ((uint32_t)CAN_BTR_TS2)                      /*!< 8 time quantum */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_filter_mode CAN Filter Mode
-  * @{
-  */
-#define CAN_FILTERMODE_IDMASK       ((uint8_t)0x00)  /*!< Identifier mask mode */
-#define CAN_FILTERMODE_IDLIST       ((uint8_t)0x01)  /*!< Identifier list mode */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_filter_scale CAN Filter Scale
-  * @{
-  */
-#define CAN_FILTERSCALE_16BIT       ((uint8_t)0x00)  /*!< Two 16-bit filters */
-#define CAN_FILTERSCALE_32BIT       ((uint8_t)0x01)  /*!< One 32-bit filter  */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_filter_FIFO CAN Filter FIFO
-  * @{
-  */
-#define CAN_FILTER_FIFO0             ((uint8_t)0x00)  /*!< Filter FIFO 0 assignment for filter x */
-#define CAN_FILTER_FIFO1             ((uint8_t)0x01)  /*!< Filter FIFO 1 assignment for filter x */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_identifier_type CAN Identifier Type
-  * @{
-  */
-#define CAN_ID_STD             ((uint32_t)0x00000000)  /*!< Standard Id */
-#define CAN_ID_EXT             ((uint32_t)0x00000004)  /*!< Extended Id */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
-  * @{
-  */
-#define CAN_RTR_DATA                ((uint32_t)0x00000000)  /*!< Data frame */
-#define CAN_RTR_REMOTE              ((uint32_t)0x00000002)  /*!< Remote frame */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number
-  * @{
-  */
-#define CAN_FIFO0                   ((uint8_t)0x00)  /*!< CAN FIFO 0 used to receive */
-#define CAN_FIFO1                   ((uint8_t)0x01)  /*!< CAN FIFO 1 used to receive */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_flags CAN Flags
-  * @{
-  */
-/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
-   and CAN_ClearFlag() functions. */
-/* If the flag is 0x1XXXXXXX, it means that it can only be used with
-   CAN_GetFlagStatus() function.  */
-
-/* Transmit Flags */
-#define CAN_FLAG_RQCP0             ((uint32_t)0x00000500)  /*!< Request MailBox0 flag         */
-#define CAN_FLAG_RQCP1             ((uint32_t)0x00000508)  /*!< Request MailBox1 flag         */
-#define CAN_FLAG_RQCP2             ((uint32_t)0x00000510)  /*!< Request MailBox2 flag         */
-#define CAN_FLAG_TXOK0             ((uint32_t)0x00000501)  /*!< Transmission OK MailBox0 flag */
-#define CAN_FLAG_TXOK1             ((uint32_t)0x00000509)  /*!< Transmission OK MailBox1 flag */
-#define CAN_FLAG_TXOK2             ((uint32_t)0x00000511)  /*!< Transmission OK MailBox2 flag */
-#define CAN_FLAG_TME0              ((uint32_t)0x0000051A)  /*!< Transmit mailbox 0 empty flag */
-#define CAN_FLAG_TME1              ((uint32_t)0x0000051B)  /*!< Transmit mailbox 0 empty flag */
-#define CAN_FLAG_TME2              ((uint32_t)0x0000051C)  /*!< Transmit mailbox 0 empty flag */
-
-/* Receive Flags */
-#define CAN_FLAG_FF0               ((uint32_t)0x00000203)  /*!< FIFO 0 Full flag    */
-#define CAN_FLAG_FOV0              ((uint32_t)0x00000204)  /*!< FIFO 0 Overrun flag */
-
-#define CAN_FLAG_FF1               ((uint32_t)0x00000403)  /*!< FIFO 1 Full flag    */
-#define CAN_FLAG_FOV1              ((uint32_t)0x00000404)  /*!< FIFO 1 Overrun flag */
-
-/* Operating Mode Flags */
-#define CAN_FLAG_WKU               ((uint32_t)0x00000103)  /*!< Wake up flag           */
-#define CAN_FLAG_SLAK              ((uint32_t)0x00000101)  /*!< Sleep acknowledge flag */
-#define CAN_FLAG_SLAKI             ((uint32_t)0x00000104)  /*!< Sleep acknowledge flag */
-/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
-         In this case the SLAK bit can be polled.*/
-
-/* Error Flags */
-#define CAN_FLAG_EWG               ((uint32_t)0x00000300)  /*!< Error warning flag   */
-#define CAN_FLAG_EPV               ((uint32_t)0x00000301)  /*!< Error passive flag   */
-#define CAN_FLAG_BOF               ((uint32_t)0x00000302)  /*!< Bus-Off flag         */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_interrupts CAN Interrupts
-  * @{
-  */
-#define CAN_IT_TME                  ((uint32_t)CAN_IER_TMEIE)   /*!< Transmit mailbox empty interrupt */
-
-/* Receive Interrupts */
-#define CAN_IT_FMP0                 ((uint32_t)CAN_IER_FMPIE0)  /*!< FIFO 0 message pending interrupt */
-#define CAN_IT_FF0                  ((uint32_t)CAN_IER_FFIE0)   /*!< FIFO 0 full interrupt            */
-#define CAN_IT_FOV0                 ((uint32_t)CAN_IER_FOVIE0)  /*!< FIFO 0 overrun interrupt         */
-#define CAN_IT_FMP1                 ((uint32_t)CAN_IER_FMPIE1)  /*!< FIFO 1 message pending interrupt */
-#define CAN_IT_FF1                  ((uint32_t)CAN_IER_FFIE1)   /*!< FIFO 1 full interrupt            */
-#define CAN_IT_FOV1                 ((uint32_t)CAN_IER_FOVIE1)  /*!< FIFO 1 overrun interrupt         */
-
-/* Operating Mode Interrupts */
-#define CAN_IT_WKU                  ((uint32_t)CAN_IER_WKUIE)  /*!< Wake-up interrupt           */
-#define CAN_IT_SLK                  ((uint32_t)CAN_IER_SLKIE)  /*!< Sleep acknowledge interrupt */
-
-/* Error Interrupts */
-#define CAN_IT_EWG                  ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt   */
-#define CAN_IT_EPV                  ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt   */
-#define CAN_IT_BOF                  ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt         */
-#define CAN_IT_LEC                  ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
-#define CAN_IT_ERR                  ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt           */
-
-/**
-  * @}
-  */
-
-/* Mailboxes definition */
-#define CAN_TXMAILBOX_0   ((uint8_t)0x00)
-#define CAN_TXMAILBOX_1   ((uint8_t)0x01)
-#define CAN_TXMAILBOX_2   ((uint8_t)0x02)
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup CAN_Exported_Macro CAN Exported Macros
-  * @{
-  */
-
-/** @brief  Reset CAN handle state.
-  * @param  __HANDLE__: CAN handle.
-  * @retval None
-  */
-#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
-
-/**
-  * @brief  Enable the specified CAN interrupt.
-  * @param  __HANDLE__: CAN handle.
-  * @param  __INTERRUPT__: CAN Interrupt.
-  * @retval None
-  */
-#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the specified CAN interrupt.
-  * @param  __HANDLE__: CAN handle.
-  * @param  __INTERRUPT__: CAN Interrupt.
-  * @retval None
-  */
-#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
-
-/**
-  * @brief  Return the number of pending received messages.
-  * @param  __HANDLE__: CAN handle.
-  * @param  __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
-  * @retval The number of pending message.
-  */
-#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
-((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&(uint32_t)0x03)))
-
-/** @brief  Check whether the specified CAN flag is set or not.
-  * @param  __HANDLE__: specifies the CAN Handle.
-  * @param  __FLAG__: specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg CAN_TSR_RQCP0: Request MailBox0 Flag
-  *            @arg CAN_TSR_RQCP1: Request MailBox1 Flag
-  *            @arg CAN_TSR_RQCP2: Request MailBox2 Flag
-  *            @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
-  *            @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
-  *            @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
-  *            @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
-  *            @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
-  *            @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
-  *            @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
-  *            @arg CAN_FLAG_FF0: FIFO 0 Full Flag
-  *            @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
-  *            @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
-  *            @arg CAN_FLAG_FF1: FIFO 1 Full Flag
-  *            @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
-  *            @arg CAN_FLAG_WKU: Wake up Flag
-  *            @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
-  *            @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
-  *            @arg CAN_FLAG_EWG: Error Warning Flag
-  *            @arg CAN_FLAG_EPV: Error Passive Flag
-  *            @arg CAN_FLAG_BOF: Bus-Off Flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
-((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8) == 4)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8) == 1)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
-
-/** @brief  Clear the specified CAN pending flag.
-  * @param  __HANDLE__: specifies the CAN Handle.
-  * @param  __FLAG__: specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg CAN_TSR_RQCP0: Request MailBox0 Flag
-  *            @arg CAN_TSR_RQCP1: Request MailBox1 Flag
-  *            @arg CAN_TSR_RQCP2: Request MailBox2 Flag
-  *            @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
-  *            @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
-  *            @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
-  *            @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
-  *            @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
-  *            @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
-  *            @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
-  *            @arg CAN_FLAG_FF0: FIFO 0 Full Flag
-  *            @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
-  *            @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
-  *            @arg CAN_FLAG_FF1: FIFO 1 Full Flag
-  *            @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
-  *            @arg CAN_FLAG_WKU: Wake up Flag
-  *            @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
-((((__FLAG__) >> 8U) == 5)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == 2)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == 4)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == 1)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0)
-
-
-/** @brief  Check whether the specified CAN interrupt source is enabled or not.
-  * @param  __HANDLE__: specifies the CAN Handle.
-  * @param  __INTERRUPT__: specifies the CAN interrupt source to check.
-  *         This parameter can be one of the following values:
-  *            @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
-  *            @arg CAN_IT_FMP0: FIFO0 message pending interrupt enable
-  *            @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable
-  * @retval The new state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/**
-  * @brief  Check the transmission status of a CAN Frame.
-  * @param  __HANDLE__: specifies the CAN Handle.
-  * @param  __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
-  * @retval The new status of transmission  (TRUE or FALSE).
-  */
-#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
-(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\
- ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\
- ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))
-
-
-
-/**
-  * @brief  Release the specified receive FIFO.
-  * @param  __HANDLE__: CAN handle.
-  * @param  __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
-  * @retval None
-  */
-#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
-((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1)) 
-
-/**
-  * @brief  Cancel a transmit request.
-  * @param  __HANDLE__: specifies the CAN Handle.
-  * @param  __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
-  * @retval None
-  */
-#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
-(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\
- ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\
- ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2))
-
-/**
-  * @brief  Enable or disable the DBG Freeze for CAN.
-  * @param  __HANDLE__: specifies the CAN Handle.
-  * @param  __NEWSTATE__: new state of the CAN peripheral. 
-  *         This parameter can be: ENABLE (CAN reception/transmission is frozen
-  *         during debug. Reception FIFO can still be accessed/controlled normally) 
-  *         or DISABLE (CAN is working during debug).
-  * @retval None
-  */
-#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
-((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF)) 
-
-/**
- * @}
- */  
- 
-/* Exported functions --------------------------------------------------------*/  
-/** @addtogroup CAN_Exported_Functions CAN Exported Functions
-  * @{
-  */
-  
-/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions 
- * @{
- */
-/* addtogroup and de-initialization functions *****************************/ 
-HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
-HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
-HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
-void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
-void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
-/**
- * @}
- */ 
- 
-/** @addtogroup CAN_Exported_Functions_Group2 Input and Output operation functions
- *  @brief    I/O operation functions 
- * @{
- */
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
-HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
-HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
-HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
-void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
-void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
-void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
-void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
-/**
- * @}
- */ 
- 
-/** @addtogroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
- *  @brief   CAN Peripheral State functions 
- * @{
- */
-/* Peripheral State and Error functions ***************************************/
-uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
-HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
-/**
- * @}
- */ 
-
-/**
- * @}
- */ 
-
-/* Private types -------------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup CAN_Private_Constants CAN Private Constants
-  * @{
-  */
-/** @defgroup CAN_transmit_constants CAN Transmit Constants
-  * @{
-  */
-#define CAN_TXSTATUS_NOMAILBOX      ((uint8_t)0x04)  /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
-/**
-  * @}
-  */
-#define CAN_FLAG_MASK     ((uint32_t)0x000000FF)
-
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup CAN_Private_Macros CAN Private Macros
-  * @{
-  */
-
-#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
-                           ((MODE) == CAN_MODE_LOOPBACK)|| \
-                           ((MODE) == CAN_MODE_SILENT) || \
-                           ((MODE) == CAN_MODE_SILENT_LOOPBACK))
-
-#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
-                         ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
-
-#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
-
-#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
-
-#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
-
-#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
-
-#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
-                                  ((MODE) == CAN_FILTERMODE_IDLIST))
-
-#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
-                                    ((SCALE) == CAN_FILTERSCALE_32BIT))
-
-#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
-                                  ((FIFO) == CAN_FILTER_FIFO1))
-
-#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28)
-
-#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
-
-#define IS_CAN_STDID(STDID)   ((STDID) <= ((uint32_t)0x7FF))
-
-#define IS_CAN_EXTID(EXTID)   ((EXTID) <= ((uint32_t)0x1FFFFFFF))
-
-#define IS_CAN_DLC(DLC)       ((DLC) <= ((uint8_t)0x08))
-
-#define IS_CAN_IDTYPE(IDTYPE)  (((IDTYPE) == CAN_ID_STD) || \
-                                ((IDTYPE) == CAN_ID_EXT))
-
-#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
-
-#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L4xx_CAN_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/inc/stm32l4xx_hal_cortex.h b/stmhal/hal/l4/inc/stm32l4xx_hal_cortex.h
deleted file mode 100644
index 5fc9db9669..0000000000
--- a/stmhal/hal/l4/inc/stm32l4xx_hal_cortex.h
+++ /dev/null
@@ -1,467 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_cortex.h
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   Header file of CORTEX HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L4xx_HAL_CORTEX_H
-#define __STM32L4xx_HAL_CORTEX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup CORTEX CORTEX
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup CORTEX_Exported_Types CORTEX Exported Types
-  * @{
-  */
-
-#if (__MPU_PRESENT == 1)
-/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
-  * @{
-  */
-typedef struct
-{
-  uint8_t                Enable;                /*!< Specifies the status of the region. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */
-  uint8_t                Number;                /*!< Specifies the number of the region to protect. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */
-  uint32_t               BaseAddress;           /*!< Specifies the base address of the region to protect.                           */
-  uint8_t                Size;                  /*!< Specifies the size of the region to protect. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */
-  uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable. 
-                                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */
-  uint8_t                TypeExtField;          /*!< Specifies the TEX field level.
-                                                     This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */
-  uint8_t                AccessPermission;      /*!< Specifies the region access permission type. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */
-  uint8_t                DisableExec;           /*!< Specifies the instruction access status. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */
-  uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */
-  uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */
-  uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */
-}MPU_Region_InitTypeDef;
-/**
-  * @}
-  */
-#endif /* __MPU_PRESENT */
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
-  * @{
-  */
-
-/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
-  * @{
-  */
-#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bit  for pre-emption priority,
-                                                                 4 bits for subpriority */
-#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bit  for pre-emption priority,
-                                                                 3 bits for subpriority */
-#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
-                                                                 2 bits for subpriority */
-#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
-                                                                 1 bit  for subpriority */
-#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
-                                                                 0 bit  for subpriority */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
-  * @{
-  */
-#define SYSTICK_CLKSOURCE_HCLK_DIV8    ((uint32_t)0x00000000)
-#define SYSTICK_CLKSOURCE_HCLK         ((uint32_t)0x00000004)
-/**
-  * @}
-  */
-
-#if (__MPU_PRESENT == 1)
-/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
-  * @{
-  */
-#define  MPU_HFNMI_PRIVDEF_NONE      ((uint32_t)0x00000000)
-#define  MPU_HARDFAULT_NMI           ((uint32_t)0x00000002)
-#define  MPU_PRIVILEGED_DEFAULT      ((uint32_t)0x00000004)
-#define  MPU_HFNMI_PRIVDEF           ((uint32_t)0x00000006)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
-  * @{
-  */
-#define  MPU_REGION_ENABLE           ((uint8_t)0x01)
-#define  MPU_REGION_DISABLE          ((uint8_t)0x00)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
-  * @{
-  */
-#define  MPU_INSTRUCTION_ACCESS_ENABLE      ((uint8_t)0x00)
-#define  MPU_INSTRUCTION_ACCESS_DISABLE     ((uint8_t)0x01)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
-  * @{
-  */
-#define  MPU_ACCESS_SHAREABLE        ((uint8_t)0x01)
-#define  MPU_ACCESS_NOT_SHAREABLE    ((uint8_t)0x00)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
-  * @{
-  */
-#define  MPU_ACCESS_CACHEABLE        ((uint8_t)0x01)
-#define  MPU_ACCESS_NOT_CACHEABLE    ((uint8_t)0x00)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
-  * @{
-  */
-#define  MPU_ACCESS_BUFFERABLE       ((uint8_t)0x01)
-#define  MPU_ACCESS_NOT_BUFFERABLE   ((uint8_t)0x00)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels
-  * @{
-  */
-#define  MPU_TEX_LEVEL0              ((uint8_t)0x00)
-#define  MPU_TEX_LEVEL1              ((uint8_t)0x01)
-#define  MPU_TEX_LEVEL2              ((uint8_t)0x02)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
-  * @{
-  */
-#define   MPU_REGION_SIZE_32B        ((uint8_t)0x04)
-#define   MPU_REGION_SIZE_64B        ((uint8_t)0x05)
-#define   MPU_REGION_SIZE_128B       ((uint8_t)0x06)
-#define   MPU_REGION_SIZE_256B       ((uint8_t)0x07)
-#define   MPU_REGION_SIZE_512B       ((uint8_t)0x08)
-#define   MPU_REGION_SIZE_1KB        ((uint8_t)0x09)
-#define   MPU_REGION_SIZE_2KB        ((uint8_t)0x0A)
-#define   MPU_REGION_SIZE_4KB        ((uint8_t)0x0B)
-#define   MPU_REGION_SIZE_8KB        ((uint8_t)0x0C)
-#define   MPU_REGION_SIZE_16KB       ((uint8_t)0x0D)
-#define   MPU_REGION_SIZE_32KB       ((uint8_t)0x0E)
-#define   MPU_REGION_SIZE_64KB       ((uint8_t)0x0F)
-#define   MPU_REGION_SIZE_128KB      ((uint8_t)0x10)
-#define   MPU_REGION_SIZE_256KB      ((uint8_t)0x11)
-#define   MPU_REGION_SIZE_512KB      ((uint8_t)0x12)
-#define   MPU_REGION_SIZE_1MB        ((uint8_t)0x13)
-#define   MPU_REGION_SIZE_2MB        ((uint8_t)0x14)
-#define   MPU_REGION_SIZE_4MB        ((uint8_t)0x15)
-#define   MPU_REGION_SIZE_8MB        ((uint8_t)0x16)
-#define   MPU_REGION_SIZE_16MB       ((uint8_t)0x17)
-#define   MPU_REGION_SIZE_32MB       ((uint8_t)0x18)
-#define   MPU_REGION_SIZE_64MB       ((uint8_t)0x19)
-#define   MPU_REGION_SIZE_128MB      ((uint8_t)0x1A)
-#define   MPU_REGION_SIZE_256MB      ((uint8_t)0x1B)
-#define   MPU_REGION_SIZE_512MB      ((uint8_t)0x1C)
-#define   MPU_REGION_SIZE_1GB        ((uint8_t)0x1D)
-#define   MPU_REGION_SIZE_2GB        ((uint8_t)0x1E)
-#define   MPU_REGION_SIZE_4GB        ((uint8_t)0x1F)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 
-  * @{
-  */
-#define  MPU_REGION_NO_ACCESS        ((uint8_t)0x00)
-#define  MPU_REGION_PRIV_RW          ((uint8_t)0x01)
-#define  MPU_REGION_PRIV_RW_URO      ((uint8_t)0x02)
-#define  MPU_REGION_FULL_ACCESS      ((uint8_t)0x03)
-#define  MPU_REGION_PRIV_RO          ((uint8_t)0x05)
-#define  MPU_REGION_PRIV_RO_URO      ((uint8_t)0x06)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
-  * @{
-  */
-#define  MPU_REGION_NUMBER0          ((uint8_t)0x00)
-#define  MPU_REGION_NUMBER1          ((uint8_t)0x01)
-#define  MPU_REGION_NUMBER2          ((uint8_t)0x02)
-#define  MPU_REGION_NUMBER3          ((uint8_t)0x03)
-#define  MPU_REGION_NUMBER4          ((uint8_t)0x04)
-#define  MPU_REGION_NUMBER5          ((uint8_t)0x05)
-#define  MPU_REGION_NUMBER6          ((uint8_t)0x06)
-#define  MPU_REGION_NUMBER7          ((uint8_t)0x07)
-/**
-  * @}
-  */
-#endif /* __MPU_PRESENT */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
-  * @{
-  */
-
-/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions 
-  * @brief    Initialization and Configuration functions
-  * @{
-  */
-/* Initialization and Configuration functions *****************************/
-void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
-void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
-void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
-void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
-void HAL_NVIC_SystemReset(void);
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
-
-#if (__MPU_PRESENT == 1)
-/**
-  * @brief  Disable the MPU.
-  * @retval None
-  */
-__STATIC_INLINE void HAL_MPU_Disable(void)
-{
-  /* Disable fault exceptions */
-  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
-  
-  /* Disable the MPU */
-  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
-}
-
-/**
-  * @brief  Enable the MPU.
-  * @param  MPU_Control: Specifies the control mode of the MPU during hard fault, 
-  *          NMI, FAULTMASK and privileged accessto the default memory 
-  *          This parameter can be one of the following values:
-  *            @arg MPU_HFNMI_PRIVDEF_NONE
-  *            @arg MPU_HARDFAULT_NMI
-  *            @arg MPU_PRIVILEGED_DEFAULT
-  *            @arg MPU_HFNMI_PRIVDEF
-  * @retval None
-  */
-__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
-{
-  /* Enable the MPU */
-  MPU->CTRL   = MPU_Control | MPU_CTRL_ENABLE_Msk;
-  
-  /* Enable fault exceptions */
-  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
-}
-#endif /* __MPU_PRESENT */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions 
-  * @brief   Cortex control functions
-  * @{
-  */
-/* Peripheral Control functions ***********************************************/
-uint32_t HAL_NVIC_GetPriorityGrouping(void);
-void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
-uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
-void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
-void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
-uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
-void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
-void HAL_SYSTICK_IRQHandler(void);
-void HAL_SYSTICK_Callback(void);
-
-#if (__MPU_PRESENT == 1)
-void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
-#endif /* __MPU_PRESENT */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/ 
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
-  * @{
-  */
-#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
-                                       ((GROUP) == NVIC_PRIORITYGROUP_1) || \
-                                       ((GROUP) == NVIC_PRIORITYGROUP_2) || \
-                                       ((GROUP) == NVIC_PRIORITYGROUP_3) || \
-                                       ((GROUP) == NVIC_PRIORITYGROUP_4))
-
-#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
-
-#define IS_NVIC_SUB_PRIORITY(PRIORITY)         ((PRIORITY) < 0x10)
-
-#define IS_NVIC_DEVICE_IRQ(IRQ)                ((IRQ) >= 0x00)
-
-#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
-                                       ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
-
-#if (__MPU_PRESENT == 1)
-#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
-                                     ((STATE) == MPU_REGION_DISABLE))
-
-#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
-                                          ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
-
-#define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_SHAREABLE) || \
-                                          ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
-
-#define IS_MPU_ACCESS_CACHEABLE(STATE)   (((STATE) == MPU_ACCESS_CACHEABLE) || \
-                                          ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
-
-#define IS_MPU_ACCESS_BUFFERABLE(STATE)   (((STATE) == MPU_ACCESS_BUFFERABLE) || \
-                                          ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
-
-#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0)  || \
-                                ((TYPE) == MPU_TEX_LEVEL1)  || \
-                                ((TYPE) == MPU_TEX_LEVEL2))
-
-#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS)   || \
-                                                  ((TYPE) == MPU_REGION_PRIV_RW)     || \
-                                                  ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
-                                                  ((TYPE) == MPU_REGION_FULL_ACCESS) || \
-                                                  ((TYPE) == MPU_REGION_PRIV_RO)     || \
-                                                  ((TYPE) == MPU_REGION_PRIV_RO_URO))
-
-#define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER1) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER2) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER3) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER4) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER5) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER6) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER7))
-
-#define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_32B)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_64B)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_128B)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_256B)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_512B)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_1KB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_2KB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_4KB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_8KB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_16KB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_32KB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_64KB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_128KB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_256KB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_512KB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_1MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_2MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_4MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_8MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_16MB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_32MB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_64MB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_128MB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_256MB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_512MB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_1GB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_2GB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_4GB))
-
-#define IS_MPU_SUB_REGION_DISABLE(SUBREGION)  ((SUBREGION) < (uint16_t)0x00FF)
-#endif /* __MPU_PRESENT */
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L4xx_HAL_CORTEX_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/inc/stm32l4xx_hal_dac.h b/stmhal/hal/l4/inc/stm32l4xx_hal_dac.h
deleted file mode 100644
index 30c6b52a37..0000000000
--- a/stmhal/hal/l4/inc/stm32l4xx_hal_dac.h
+++ /dev/null
@@ -1,479 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_dac.h
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   Header file of DAC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L4xx_HAL_DAC_H
-#define __STM32L4xx_HAL_DAC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-   
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup DAC
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Types DAC Exported Types
-  * @{
-  */
-
-/** 
-  * @brief  HAL State structures definition  
-  */ 
-typedef enum
-{
-  HAL_DAC_STATE_RESET             = 0x00,  /*!< DAC not yet initialized or disabled  */
-  HAL_DAC_STATE_READY             = 0x01,  /*!< DAC initialized and ready for use    */
-  HAL_DAC_STATE_BUSY              = 0x02,  /*!< DAC internal processing is ongoing   */
-  HAL_DAC_STATE_TIMEOUT           = 0x03,  /*!< DAC timeout state                    */
-  HAL_DAC_STATE_ERROR             = 0x04   /*!< DAC error state                      */
- 
-}HAL_DAC_StateTypeDef;
- 
-/** 
-  * @brief  DAC handle Structure definition  
-  */ 
-typedef struct
-{
-  DAC_TypeDef                 *Instance;     /*!< Register base address             */
-  
-  __IO HAL_DAC_StateTypeDef   State;         /*!< DAC communication state           */
-
-  HAL_LockTypeDef             Lock;          /*!< DAC locking object                */
-  
-  DMA_HandleTypeDef           *DMA_Handle1;  /*!< Pointer DMA handler for channel 1 */
-  
-  DMA_HandleTypeDef           *DMA_Handle2;  /*!< Pointer DMA handler for channel 2 */ 
-  
-  __IO uint32_t               ErrorCode;     /*!< DAC Error code                    */
-  
-}DAC_HandleTypeDef;
-
-/** 
-  * @brief   DAC Configuration sample and hold Channel structure definition  
-  */ 
-typedef struct
-{
-  uint32_t DAC_SampleTime ;          /*!< Specifies the Sample time for the selected channel.
-                                          This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. 
-                                          This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */  
-
-  uint32_t DAC_HoldTime ;            /*!< Specifies the hold time for the selected channel
-                                          This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. 
-                                          This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */    
-  
-  uint32_t DAC_RefreshTime ;         /*!< Specifies the refresh time for the selected channel
-                                          This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. 
-                                          This parameter must be a number between Min_Data = 0 and Max_Data = 255 */  
-}
-DAC_SampleAndHoldConfTypeDef;
-
-/** 
-  * @brief   DAC Configuration regular Channel structure definition  
-  */ 
-typedef struct
-{
-  uint32_t DAC_SampleAndHold;            /*!< Specifies whether the DAC mode.
-                                              This parameter can be a value of @ref DAC_SampleAndHold */
-  
-  uint32_t DAC_Trigger;                  /*!< Specifies the external trigger for the selected DAC channel.
-                                              This parameter can be a value of @ref DAC_trigger_selection */
-  
-  uint32_t DAC_OutputBuffer;             /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
-                                               This parameter can be a value of @ref DAC_output_buffer */
-
-  uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral .
-                                              This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */
-  
-  uint32_t DAC_UserTrimming;             /*!< Specifies the trimming mode 
-                                              This parameter must be a value of @ref DAC_UserTrimming 
-                                              DAC_UserTrimming is either factory or user trimming */
-                                        
-  uint32_t DAC_TrimmingValue;             /*!< Specifies the offset trimming value 
-                                               i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER. 
-                                               This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
-
-  DAC_SampleAndHoldConfTypeDef  DAC_SampleAndHoldConfig;  /*!< Sample and Hold settings */ 
-      
-}DAC_ChannelConfTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Constants DAC Exported Constants
-  * @{
-  */
-
-/** @defgroup DAC_Error_Code DAC Error Code
-  * @{
-  */
-#define  HAL_DAC_ERROR_NONE              0x00    /*!< No error                          */
-#define  HAL_DAC_ERROR_DMAUNDERRUNCH1    0x01    /*!< DAC channel1 DMA underrun error   */
-#define  HAL_DAC_ERROR_DMAUNDERRUNCH2    0x02    /*!< DAC channel2 DMA underrun error   */
-#define  HAL_DAC_ERROR_DMA               0x04    /*!< DMA error                         */
-#define  HAL_DAC_ERROR_TIMEOUT           0x08    /*!< Timeout error                     */
-/**
-  * @}
-  */
-
-/** @defgroup DAC_trigger_selection DAC trigger selection
-  * @{
-  */
-
-#define DAC_TRIGGER_NONE                   ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register 
-                                                                       has been loaded, and not by external trigger */
-#define DAC_TRIGGER_T2_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T4_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 |DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T5_TRGO                ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T6_TRGO                ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T7_TRGO                ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T8_TRGO                ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_EXT_IT9                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_SOFTWARE               ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
-
-/**
-  * @}
-  */   
-
-/** @defgroup DAC_output_buffer DAC output buffer
-  * @{
-  */
-#define DAC_OUTPUTBUFFER_ENABLE            ((uint32_t)0x00000000)
-#define DAC_OUTPUTBUFFER_DISABLE           ((uint32_t)DAC_MCR_MODE1_1)
-
-/**
-  * @}
-  */
-    
-/** @defgroup DAC_Channel_selection DAC Channel selection
-  * @{
-  */
-#define DAC_CHANNEL_1                      ((uint32_t)0x00000000)
-#define DAC_CHANNEL_2                      ((uint32_t)0x00000010)
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_data_alignment DAC data alignment
-  * @{
-  */
-#define DAC_ALIGN_12B_R                    ((uint32_t)0x00000000)
-#define DAC_ALIGN_12B_L                    ((uint32_t)0x00000004)
-#define DAC_ALIGN_8B_R                     ((uint32_t)0x00000008)
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_flags_definition DAC flags definition
-  * @{
-  */ 
-#define DAC_FLAG_DMAUDR1                   ((uint32_t)DAC_SR_DMAUDR1)
-#define DAC_FLAG_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)   
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_IT_definition  DAC IT definition
-  * @{
-  */ 
-#define DAC_IT_DMAUDR1                   ((uint32_t)DAC_SR_DMAUDR1)
-#define DAC_IT_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)   
-
-/**
-  * @}
-  */
-  
-/** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral
-  * @{
-  */
-#define DAC_CHIPCONNECT_DISABLE  ((uint32_t)0x00000000)
-#define DAC_CHIPCONNECT_ENABLE     ((uint32_t)DAC_MCR_MODE1_0)
-
-/**
-  * @}
-  */
-
-  /** @defgroup DAC_UserTrimming DAC User Trimming
-  * @{
-  */
-
-#define DAC_TRIMMING_FACTORY        ((uint32_t)0x00000000)           /*!< Factory trimming */
-#define DAC_TRIMMING_USER           ((uint32_t)0x00000001)           /*!< User trimming */
-   
-/**
-  * @}
-  */ 
-
-/** @defgroup DAC_SampleAndHold DAC power mode
-  * @{
-  */
-#define DAC_SAMPLEANDHOLD_DISABLE     ((uint32_t)0x00000000)
-#define DAC_SAMPLEANDHOLD_ENABLE      ((uint32_t)DAC_MCR_MODE1_2)
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Macros DAC Exported Macros
-  * @{
-  */
-
-/** @brief Reset DAC handle state.
-  * @param  __HANDLE__: specifies the DAC handle.
-  * @retval None
-  */
-#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
-
-/** @brief Enable the DAC channel.
-  * @param  __HANDLE__: specifies the DAC handle.
-  * @param  __DAC_Channel__: specifies the DAC channel
-  * @retval None
-  */
-#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
-((__HANDLE__)->Instance->CR |=  (DAC_CR_EN1 << (__DAC_Channel__)))
-
-/** @brief Disable the DAC channel.
-  * @param  __HANDLE__: specifies the DAC handle
-  * @param  __DAC_Channel__: specifies the DAC channel.
-  * @retval None
-  */
-#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
-((__HANDLE__)->Instance->CR &=  ~(DAC_CR_EN1 << (__DAC_Channel__)))
- 
-/** @brief Set DHR12R1 alignment.
-  * @param  __ALIGNMENT__: specifies the DAC alignment
-  * @retval None
-  */
-#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008) + (__ALIGNMENT__))
-
-/** @brief  Set DHR12R2 alignment.
-  * @param  __ALIGNMENT__: specifies the DAC alignment
-  * @retval None
-  */
-#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014) + (__ALIGNMENT__))
-
-/** @brief  Set DHR12RD alignment.
-  * @param  __ALIGNMENT__: specifies the DAC alignment
-  * @retval None
-  */
-#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020) + (__ALIGNMENT__))
-
-/** @brief Enable the DAC interrupt.
-  * @param  __HANDLE__: specifies the DAC handle
-  * @param  __INTERRUPT__: specifies the DAC interrupt.
-  *          This parameter can be any combination of the following values:
-  *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
-  *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
-  * @retval None
-  */
-#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
-
-/** @brief Disable the DAC interrupt.
-  * @param  __HANDLE__: specifies the DAC handle
-  * @param  __INTERRUPT__: specifies the DAC interrupt.
-  *          This parameter can be any combination of the following values:
-  *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
-  *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
-  * @retval None
-  */
-#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
-
-/** @brief  Check whether the specified DAC interrupt source is enabled or not.
-  * @param __HANDLE__: DAC handle
-  * @param __INTERRUPT__: DAC interrupt source to check
-  *          This parameter can be any combination of the following values:
-  *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
-  *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
-  * @retval State of interruption (SET or RESET)
-  */
-#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/** @brief  Get the selected DAC's flag status.
-  * @param  __HANDLE__: specifies the DAC handle.
-  * @param  __FLAG__: specifies the DAC flag to get.
-  *          This parameter can be any combination of the following values:
-  *            @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
-  *            @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
-  * @retval None
-  */
-#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Clear the DAC's flag.
-  * @param  __HANDLE__: specifies the DAC handle.
-  * @param  __FLAG__: specifies the DAC flag to clear.
-  *          This parameter can be any combination of the following values:
-  *            @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
-  *            @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
-  * @retval None
-  */
-#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
-
-/**
-  * @}
-  */ 
-
-/* Private macro -------------------------------------------------------------*/
-
-/** @defgroup DAC_Private_Macros DAC Private Macros
-  * @{
-  */
-#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
-                                           ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
-
-#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
-                                ((CHANNEL) == DAC_CHANNEL_2))
-
-#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
-                             ((ALIGN) == DAC_ALIGN_12B_L) || \
-                             ((ALIGN) == DAC_ALIGN_8B_R))
-
-#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
-
-#define IS_DAC_REFRESHTIME(TIME)   ((TIME) <= 0x0000000FF)
-
-/**
-  * @}
-  */
-  
-/* Include DAC HAL Extended module */
-#include "stm32l4xx_hal_dac_ex.h"   
-
-/* Exported functions --------------------------------------------------------*/  
-
-/** @addtogroup DAC_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup DAC_Exported_Functions_Group1
-  * @{
-  */  
-/* Initialization and de-initialization functions *****************************/ 
-HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
-HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
-void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
-void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
-
-/**
-  * @}
-  */
-
-/** @addtogroup DAC_Exported_Functions_Group2
- * @{
- */    
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
-HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
-
-void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
-
-HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
-
-void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
-void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
-void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
-void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
-/**
-  * @}
-  */
-
-/** @addtogroup DAC_Exported_Functions_Group3
-  * @{
-  */ 
-/* Peripheral Control functions ***********************************************/
-uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
-
-HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
-/**
-  * @}
-  */
-
-/** @addtogroup DAC_Exported_Functions_Group4
-  * @{
-  */     
-/* Peripheral State and Error functions ***************************************/
-HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
-uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif 
-  
-
-#endif /*__STM32L4xx_HAL_DAC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/stmhal/hal/l4/inc/stm32l4xx_hal_dac_ex.h b/stmhal/hal/l4/inc/stm32l4xx_hal_dac_ex.h
deleted file mode 100644
index 6368df6e71..0000000000
--- a/stmhal/hal/l4/inc/stm32l4xx_hal_dac_ex.h
+++ /dev/null
@@ -1,245 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_dac_ex.h
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   Header file of DAC HAL Extended module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L4xx_HAL_DAC_EX_H
-#define __STM32L4xx_HAL_DAC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-           
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup DACEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-   
-/** 
-  * @brief  HAL State structures definition  
-  */ 
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DACEx_Exported_Constants DACEx Exported Constants
-  * @{
-  */ 
-    
-/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangleamplitude
-  * @{
-  */
-#define DAC_LFSRUNMASK_BIT0                ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
-#define DAC_LFSRUNMASK_BITS1_0             ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS2_0             ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS3_0             ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS4_0             ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS5_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS6_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS7_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS8_0             ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS9_0             ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS10_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS11_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
-#define DAC_TRIANGLEAMPLITUDE_1            ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
-#define DAC_TRIANGLEAMPLITUDE_3            ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
-#define DAC_TRIANGLEAMPLITUDE_7            ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
-#define DAC_TRIANGLEAMPLITUDE_15           ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
-#define DAC_TRIANGLEAMPLITUDE_31           ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */
-#define DAC_TRIANGLEAMPLITUDE_63           ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
-#define DAC_TRIANGLEAMPLITUDE_127          ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */
-#define DAC_TRIANGLEAMPLITUDE_255          ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
-#define DAC_TRIANGLEAMPLITUDE_511          ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */
-#define DAC_TRIANGLEAMPLITUDE_1023         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
-#define DAC_TRIANGLEAMPLITUDE_2047         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
-#define DAC_TRIANGLEAMPLITUDE_4095         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
-
-/**
-  * @}
-  */       
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-
-/* Private macro -------------------------------------------------------------*/
-
-/** @defgroup DACEx_Private_Macros DACEx Private Macros
-  * @{
-  */
-
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
-                                 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))      
-
-#define IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x0000003FF)
-
-#define IS_DAC_HOLDTIME(TIME)   ((TIME) <= 0x0000003FF)
-
-#define IS_DAC_SAMPLEANDHOLD(MODE) (((MODE) == DAC_SAMPLEANDHOLD_DISABLE) || \
-                                    ((MODE) == DAC_SAMPLEANDHOLD_ENABLE))
-
-
-#define IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1F)
-
-#define IS_DAC_NEWTRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1F)
-
-#define IS_DAC_CHIP_CONNECTION(CONNECT) (((CONNECT) == DAC_CHIPCONNECT_DISABLE) || \
-                                         ((CONNECT) == DAC_CHIPCONNECT_ENABLE))
-
-#define IS_DAC_TRIMMING(TRIMMING) (((TRIMMING) == DAC_TRIMMING_FACTORY) || \
-                                     ((TRIMMING) == DAC_TRIMMING_USER))
-
-#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
-
-
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/  
-/* Extended features functions ***********************************************/
-
-/** @addtogroup DACEx_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup DACEx_Exported_Functions_Group2
- * @{
- */    
-/* IO operation functions *****************************************************/
-  
-HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
-HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
-HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
-
-void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
-
-HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel, uint32_t NewTrimmingValue);
-
-/**
-  * @}
-  */
-
-/** @addtogroup DACEx_Exported_Functions_Group3
-  * @{
-  */ 
-/* Peripheral Control functions ***********************************************/
-
-uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
-uint32_t HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel);
-   
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup DACEx_Private_Functions
-  * @{
-  */
-
-/* DAC_DMAConvCpltCh2 / DAC_DMAErrorCh2 / DAC_DMAHalfConvCpltCh2 */
-/* are called by HAL_DAC_Start_DMA */
-void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
-void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
-void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
-
-/**
- * @}
- */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif   
-
-#endif /*__STM32L4xx_HAL_DAC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/inc/stm32l4xx_hal_def.h b/stmhal/hal/l4/inc/stm32l4xx_hal_def.h
deleted file mode 100644
index 5f0a44c220..0000000000
--- a/stmhal/hal/l4/inc/stm32l4xx_hal_def.h
+++ /dev/null
@@ -1,215 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_def.h
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   This file contains HAL common defines, enumeration, macros and
-  *          structures definitions.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L4xx_HAL_DEF
-#define __STM32L4xx_HAL_DEF
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx.h"
-#include "Legacy/stm32_hal_legacy.h"  /* Aliases file for old names compatibility */
-#include <stdio.h>
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
-  * @brief  HAL Status structures definition
-  */
-typedef enum
-{
-  HAL_OK       = 0x00,
-  HAL_ERROR    = 0x01,
-  HAL_BUSY     = 0x02,
-  HAL_TIMEOUT  = 0x03
-} HAL_StatusTypeDef;
-
-/**
-  * @brief  HAL Lock structures definition
-  */
-typedef enum
-{
-  HAL_UNLOCKED = 0x00,
-  HAL_LOCKED   = 0x01
-} HAL_LockTypeDef;
-
-/* Exported macros -----------------------------------------------------------*/
-
-#define HAL_MAX_DELAY      0xFFFFFFFF
-
-#define HAL_IS_BIT_SET(REG, BIT)         (((REG) & (BIT)) == (BIT))
-#define HAL_IS_BIT_CLR(REG, BIT)         (((REG) & (BIT)) == RESET)
-
-#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__)             \
-                        do{                                                      \
-                            (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
-                            (__DMA_HANDLE__).Parent = (__HANDLE__);              \
-                        } while(0)
-
-#define UNUSED(x) ((void)(x))
-                         
-/** @brief Reset the Handle's State field.
-  * @param __HANDLE__: specifies the Peripheral Handle.
-  * @note  This macro can be used for the following purpose: 
-  *          - When the Handle is declared as local variable; before passing it as parameter
-  *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro 
-  *            to set to 0 the Handle's "State" field.
-  *            Otherwise, "State" field may have any random value and the first time the function 
-  *            HAL_PPP_Init() is called, the low level hardware initialization will be missed
-  *            (i.e. HAL_PPP_MspInit() will not be executed).
-  *          - When there is a need to reconfigure the low level hardware: instead of calling
-  *            HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
-  *            In this later function, when the Handle's "State" field is set to 0, it will execute the function
-  *            HAL_PPP_MspInit() which will reconfigure the low level hardware.
-  * @retval None
-  */
-#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
-
-#if (USE_RTOS == 1)
-  /* Reserved for future use */
-  #error " USE_RTOS should be 0 in the current HAL release "
-#else
-  #define __HAL_LOCK(__HANDLE__)                                           \
-                                do{                                        \
-                                    if((__HANDLE__)->Lock == HAL_LOCKED)   \
-                                    {                                      \
-                                       return HAL_BUSY;                    \
-                                    }                                      \
-                                    else                                   \
-                                    {                                      \
-                                       (__HANDLE__)->Lock = HAL_LOCKED;    \
-                                    }                                      \
-                                  }while (0)
-
-  #define __HAL_UNLOCK(__HANDLE__)                                          \
-                                  do{                                       \
-                                      (__HANDLE__)->Lock = HAL_UNLOCKED;    \
-                                    }while (0)
-#endif /* USE_RTOS */
-
-#if  defined ( __GNUC__ )
-  #ifndef __weak
-    #define __weak   __attribute__((weak))
-  #endif /* __weak */
-  #ifndef __packed
-    #define __packed __attribute__((__packed__))
-  #endif /* __packed */
-#endif /* __GNUC__ */
-
-
-/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
-#if defined   (__GNUC__)        /* GNU Compiler */
-  #ifndef __ALIGN_END
-    #define __ALIGN_END    __attribute__ ((aligned (4)))
-  #endif /* __ALIGN_END */
-  #ifndef __ALIGN_BEGIN
-    #define __ALIGN_BEGIN
-  #endif /* __ALIGN_BEGIN */
-#else
-  #ifndef __ALIGN_END
-    #define __ALIGN_END
-  #endif /* __ALIGN_END */
-  #ifndef __ALIGN_BEGIN
-    #if defined   (__CC_ARM)      /* ARM Compiler */
-      #define __ALIGN_BEGIN    __align(4)
-    #elif defined (__ICCARM__)    /* IAR Compiler */
-      #define __ALIGN_BEGIN
-    #endif /* __CC_ARM */
-  #endif /* __ALIGN_BEGIN */
-#endif /* __GNUC__ */
-
-/**
-  * @brief  __RAM_FUNC definition
-  */
-#if defined ( __CC_ARM   )
-/* ARM Compiler
-   ------------
-   RAM functions are defined using the toolchain options.
-   Functions that are executed in RAM should reside in a separate source module.
-   Using the 'Options for File' dialog you can simply change the 'Code / Const'
-   area of a module to a memory space in physical RAM.
-   Available memory areas are declared in the 'Target' tab of the 'Options for Target'
-   dialog.
-*/
-#define __RAM_FUNC HAL_StatusTypeDef
-
-#elif defined ( __ICCARM__ )
-/* ICCARM Compiler
-   ---------------
-   RAM functions are defined using a specific toolchain keyword "__ramfunc".
-*/
-#define __RAM_FUNC __ramfunc HAL_StatusTypeDef
-
-#elif defined   (  __GNUC__  )
-/* GNU Compiler
-   ------------
-  RAM functions are defined using a specific toolchain attribute
-   "__attribute__((section(".RamFunc")))".
-*/
-#define __RAM_FUNC HAL_StatusTypeDef  __attribute__((section(".RamFunc")))
-
-#endif
-
-/** 
-  * @brief  __NOINLINE definition
-  */ 
-#if defined ( __CC_ARM   ) || defined   (  __GNUC__  )
-/* ARM & GNUCompiler 
-   ---------------- 
-*/
-#define __NOINLINE __attribute__ ( (noinline) )  
-
-#elif defined ( __ICCARM__ )
-/* ICCARM Compiler
-   ---------------
-*/
-#define __NOINLINE _Pragma("optimize = no_inline")
-
-#endif
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ___STM32L4xx_HAL_DEF */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/inc/stm32l4xx_hal_dma.h b/stmhal/hal/l4/inc/stm32l4xx_hal_dma.h
deleted file mode 100644
index bbb1e54aea..0000000000
--- a/stmhal/hal/l4/inc/stm32l4xx_hal_dma.h
+++ /dev/null
@@ -1,588 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_dma.h
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   Header file of DMA HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L4xx_HAL_DMA_H
-#define __STM32L4xx_HAL_DMA_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup DMA
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup DMA_Exported_Types DMA Exported Types
-  * @{
-  */
-
-/**
-  * @brief  DMA Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t Request;                   /*!< Specifies the request selected for the specified channel.
-                                           This parameter can be a value of @ref DMA_request */
-
-  uint32_t Direction;                 /*!< Specifies if the data will be transferred from memory to peripheral,
-                                           from memory to memory or from peripheral to memory.
-                                           This parameter can be a value of @ref DMA_Data_transfer_direction */
-
-  uint32_t PeriphInc;                 /*!< Specifies whether the Peripheral address register should be incremented or not.
-                                           This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
-
-  uint32_t MemInc;                    /*!< Specifies whether the memory address register should be incremented or not.
-                                           This parameter can be a value of @ref DMA_Memory_incremented_mode */
-
-  uint32_t PeriphDataAlignment;       /*!< Specifies the Peripheral data width.
-                                           This parameter can be a value of @ref DMA_Peripheral_data_size */
-
-  uint32_t MemDataAlignment;          /*!< Specifies the Memory data width.
-                                           This parameter can be a value of @ref DMA_Memory_data_size */
-
-  uint32_t Mode;                      /*!< Specifies the operation mode of the DMAy Channelx.
-                                           This parameter can be a value of @ref DMA_mode
-                                           @note The circular buffer mode cannot be used if the memory-to-memory
-                                                 data transfer is configured on the selected Channel */
-
-  uint32_t Priority;                  /*!< Specifies the software priority for the DMAy Channelx.
-                                           This parameter can be a value of @ref DMA_Priority_level */
-} DMA_InitTypeDef;
-
-/**
-  * @brief DMA Configuration enumeration values definition
-  */
-typedef enum
-{
-  DMA_MODE            = 0,      /*!< Control related DMA mode Parameter in DMA_InitTypeDef        */
-  DMA_PRIORITY        = 1       /*!< Control related priority level Parameter in DMA_InitTypeDef  */
-
-} DMA_ControlTypeDef;
-
-/**
-  * @brief  HAL DMA State structures definition
-  */
-typedef enum
-{
-  HAL_DMA_STATE_RESET             = 0x00,  /*!< DMA not yet initialized or disabled    */
-  HAL_DMA_STATE_READY             = 0x01,  /*!< DMA process success and ready for use  */
-  HAL_DMA_STATE_READY_HALF        = 0x11,  /*!< DMA Half process success               */
-  HAL_DMA_STATE_BUSY              = 0x02,  /*!< DMA process is ongoing                 */
-  HAL_DMA_STATE_TIMEOUT           = 0x03,  /*!< DMA timeout state                      */
-  HAL_DMA_STATE_ERROR             = 0x04   /*!< DMA error state                        */
-}HAL_DMA_StateTypeDef;
-
-/**
-  * @brief  HAL DMA Error Code structure definition
-  */
-typedef enum
-{
-  HAL_DMA_FULL_TRANSFER      = 0x00,    /*!< Full transfer     */
-  HAL_DMA_HALF_TRANSFER      = 0x01     /*!< Half Transfer     */
-}HAL_DMA_LevelCompleteTypeDef;
-
-/**
-  * @brief  DMA handle Structure definition
-  */
-typedef struct __DMA_HandleTypeDef
-{
-  DMA_Channel_TypeDef    *Instance;                                                /*!< Register base address                  */
-                                                                                
-  DMA_InitTypeDef       Init;                                                      /*!< DMA communication parameters           */
-                                                                                
-  HAL_LockTypeDef       Lock;                                                      /*!< DMA locking object                     */
-                                                                                
-  __IO HAL_DMA_StateTypeDef  State;                                                /*!< DMA transfer state                     */
-                                                                                
-  void                  *Parent;                                                   /*!< Parent object state                    */
-
-  void                  (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma);     /*!< DMA transfer complete callback       */
-
-  void                  (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback  */
-
-  void                  (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer error callback          */
-
-  __IO uint32_t          ErrorCode;                                                /*!< DMA Error code                         */
-}DMA_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Constants DMA Exported Constants
-  * @{
-  */
-
-/** @defgroup DMA_Error_Code DMA Error Code
-  * @{
-  */
-#define HAL_DMA_ERROR_NONE      ((uint32_t)0x00000000)    /*!< No error             */
-#define HAL_DMA_ERROR_TE        ((uint32_t)0x00000001)    /*!< Transfer error       */
-#define HAL_DMA_ERROR_TIMEOUT   ((uint32_t)0x00000020)    /*!< Timeout error        */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_request DMA request
-  * @{
-  */
-#define DMA_REQUEST_0                     ((uint32_t)0x00000000)
-#define DMA_REQUEST_1                     ((uint32_t)0x00000001)
-#define DMA_REQUEST_2                     ((uint32_t)0x00000002)
-#define DMA_REQUEST_3                     ((uint32_t)0x00000003)
-#define DMA_REQUEST_4                     ((uint32_t)0x00000004)
-#define DMA_REQUEST_5                     ((uint32_t)0x00000005)
-#define DMA_REQUEST_6                     ((uint32_t)0x00000006)
-#define DMA_REQUEST_7                     ((uint32_t)0x00000007)
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
-  * @{
-  */
-#define DMA_PERIPH_TO_MEMORY         ((uint32_t)0x00000000)        /*!< Peripheral to memory direction */
-#define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_CCR_DIR)       /*!< Memory to peripheral direction */
-#define DMA_MEMORY_TO_MEMORY         ((uint32_t)DMA_CCR_MEM2MEM)   /*!< Memory to memory direction     */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
-  * @{
-  */
-#define DMA_PINC_ENABLE        ((uint32_t)DMA_CCR_PINC)  /*!< Peripheral increment mode Enable */
-#define DMA_PINC_DISABLE       ((uint32_t)0x00000000)    /*!< Peripheral increment mode Disable */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
-  * @{
-  */
-#define DMA_MINC_ENABLE         ((uint32_t)DMA_CCR_MINC)  /*!< Memory increment mode Enable  */
-#define DMA_MINC_DISABLE        ((uint32_t)0x00000000)    /*!< Memory increment mode Disable */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
-  * @{
-  */
-#define DMA_PDATAALIGN_BYTE          ((uint32_t)0x00000000)       /*!< Peripheral data alignment : Byte     */
-#define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_PSIZE_0)  /*!< Peripheral data alignment : HalfWord */
-#define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_CCR_PSIZE_1)  /*!< Peripheral data alignment : Word     */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Memory_data_size DMA Memory data size
-  * @{
-  */
-#define DMA_MDATAALIGN_BYTE          ((uint32_t)0x00000000)       /*!< Memory data alignment : Byte     */
-#define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_MSIZE_0)  /*!< Memory data alignment : HalfWord */
-#define DMA_MDATAALIGN_WORD          ((uint32_t)DMA_CCR_MSIZE_1)  /*!< Memory data alignment : Word     */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_mode DMA mode
-  * @{
-  */
-#define DMA_NORMAL         ((uint32_t)0x00000000)       /*!< Normal mode                  */
-#define DMA_CIRCULAR       ((uint32_t)DMA_CCR_CIRC)     /*!< Circular mode                */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Priority_level DMA Priority level
-  * @{
-  */
-#define DMA_PRIORITY_LOW             ((uint32_t)0x00000000)    /*!< Priority level : Low       */
-#define DMA_PRIORITY_MEDIUM          ((uint32_t)DMA_CCR_PL_0)  /*!< Priority level : Medium    */
-#define DMA_PRIORITY_HIGH            ((uint32_t)DMA_CCR_PL_1)  /*!< Priority level : High      */
-#define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_CCR_PL)    /*!< Priority level : Very_High */
-/**
-  * @}
-  */
-
-
-/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
-  * @{
-  */
-#define DMA_IT_TC                         ((uint32_t)DMA_CCR_TCIE)
-#define DMA_IT_HT                         ((uint32_t)DMA_CCR_HTIE)
-#define DMA_IT_TE                         ((uint32_t)DMA_CCR_TEIE)
-/**
-  * @}
-  */
-
-/** @defgroup DMA_flag_definitions DMA flag definitions
-  * @{
-  */
-#define DMA_FLAG_GL1                      ((uint32_t)0x00000001)
-#define DMA_FLAG_TC1                      ((uint32_t)0x00000002)
-#define DMA_FLAG_HT1                      ((uint32_t)0x00000004)
-#define DMA_FLAG_TE1                      ((uint32_t)0x00000008)
-#define DMA_FLAG_GL2                      ((uint32_t)0x00000010)
-#define DMA_FLAG_TC2                      ((uint32_t)0x00000020)
-#define DMA_FLAG_HT2                      ((uint32_t)0x00000040)
-#define DMA_FLAG_TE2                      ((uint32_t)0x00000080)
-#define DMA_FLAG_GL3                      ((uint32_t)0x00000100)
-#define DMA_FLAG_TC3                      ((uint32_t)0x00000200)
-#define DMA_FLAG_HT3                      ((uint32_t)0x00000400)
-#define DMA_FLAG_TE3                      ((uint32_t)0x00000800)
-#define DMA_FLAG_GL4                      ((uint32_t)0x00001000)
-#define DMA_FLAG_TC4                      ((uint32_t)0x00002000)
-#define DMA_FLAG_HT4                      ((uint32_t)0x00004000)
-#define DMA_FLAG_TE4                      ((uint32_t)0x00008000)
-#define DMA_FLAG_GL5                      ((uint32_t)0x00010000)
-#define DMA_FLAG_TC5                      ((uint32_t)0x00020000)
-#define DMA_FLAG_HT5                      ((uint32_t)0x00040000)
-#define DMA_FLAG_TE5                      ((uint32_t)0x00080000)
-#define DMA_FLAG_GL6                      ((uint32_t)0x00100000)
-#define DMA_FLAG_TC6                      ((uint32_t)0x00200000)
-#define DMA_FLAG_HT6                      ((uint32_t)0x00400000)
-#define DMA_FLAG_TE6                      ((uint32_t)0x00800000)
-#define DMA_FLAG_GL7                      ((uint32_t)0x01000000)
-#define DMA_FLAG_TC7                      ((uint32_t)0x02000000)
-#define DMA_FLAG_HT7                      ((uint32_t)0x04000000)
-#define DMA_FLAG_TE7                      ((uint32_t)0x08000000)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup DMA_Exported_Macros DMA Exported Macros
-  * @{
-  */
-
-/** @brief  Reset DMA handle state.
-  * @param  __HANDLE__: DMA handle
-  * @retval None
-  */
-#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
-
-/**
-  * @brief  Enable the specified DMA Channel.
-  * @param  __HANDLE__: DMA handle
-  * @retval None
-  */
-#define __HAL_DMA_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CCR |=  DMA_CCR_EN)
-
-/**
-  * @brief  Disable the specified DMA Channel.
-  * @param  __HANDLE__: DMA handle
-  * @retval None
-  */
-#define __HAL_DMA_DISABLE(__HANDLE__)       ((__HANDLE__)->Instance->CCR &=  ~DMA_CCR_EN)
-
-
-/* Interrupt & Flag management */
-
-/**
-  * @brief  Return the current DMA Channel transfer complete flag.
-  * @param  __HANDLE__: DMA handle
-  * @retval The specified transfer complete flag index.
-  */
-
-#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\
-   DMA_FLAG_TC7)
-
-/**
-  * @brief  Return the current DMA Channel half transfer complete flag.
-  * @param  __HANDLE__: DMA handle
-  * @retval The specified half transfer complete flag index.
-  */
-#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\
-   DMA_FLAG_HT7)
-
-/**
-  * @brief  Return the current DMA Channel transfer error flag.
-  * @param  __HANDLE__: DMA handle
-  * @retval The specified transfer error flag index.
-  */
-#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\
-   DMA_FLAG_TE7)
-
-/**
-  * @brief  Return the current DMA Channel Global interrupt flag.
-  * @param  __HANDLE__: DMA handle
-  * @retval The specified transfer error flag index.
-  */
-#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\
-   DMA_ISR_GIF7)
-
-/**
-  * @brief  Get the DMA Channel pending flags.
-  * @param  __HANDLE__: DMA handle
-  * @param  __FLAG__: Get the specified flag.
-  *          This parameter can be any combination of the following values:
-  *            @arg DMA_FLAG_TCIFx:  Transfer complete flag
-  *            @arg DMA_FLAG_HTIFx:  Half transfer complete flag
-  *            @arg DMA_FLAG_TEIFx:  Transfer error flag
-  *            @arg DMA_ISR_GIFx: Global interrupt flag
-  *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
-  * @retval The state of FLAG (SET or RESET).
-  */
-#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
- (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
-
-/**
-  * @brief  Clear the DMA Channel pending flags.
-  * @param  __HANDLE__: DMA handle
-  * @param  __FLAG__: specifies the flag to clear.
-  *          This parameter can be any combination of the following values:
-  *            @arg DMA_FLAG_TCIFx:  Transfer complete flag
-  *            @arg DMA_FLAG_HTIFx:  Half transfer complete flag
-  *            @arg DMA_FLAG_TEIFx:  Transfer error flag
-  *            @arg DMA_ISR_GIFx: Global interrupt flag
-  *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
-  * @retval None
-  */
-#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
- (DMA2->IFCR |= (__FLAG__)) : (DMA1->IFCR |= (__FLAG__)))
-
-/**
-  * @brief  Enable the specified DMA Channel interrupts.
-  * @param  __HANDLE__: DMA handle
-  * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
-  *          This parameter can be any combination of the following values:
-  *            @arg DMA_IT_TC:  Transfer complete interrupt mask
-  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
-  *            @arg DMA_IT_TE:  Transfer error interrupt mask
-  * @retval None
-  */
-#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the specified DMA Channel interrupts.
-  * @param  __HANDLE__: DMA handle
-  * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
-  *          This parameter can be any combination of the following values:
-  *            @arg DMA_IT_TC:  Transfer complete interrupt mask
-  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
-  *            @arg DMA_IT_TE:  Transfer error interrupt mask
-  * @retval None
-  */
-#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
-
-/**
-  * @brief  Check whether the specified DMA Channel interrupt is enabled or not.
-  * @param  __HANDLE__: DMA handle
-  * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg DMA_IT_TC:  Transfer complete interrupt mask
-  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
-  *            @arg DMA_IT_TE:  Transfer error interrupt mask
-  * @retval The state of DMA_IT (SET or RESET).
-  */
-#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup DMA_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup DMA_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization and de-initialization functions *****************************/
-HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
-/**
-  * @}
-  */
-
-/** @addtogroup DMA_Exported_Functions_Group2
-  * @{
-  */
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
-void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
-/**
-  * @}
-  */
-
-/** @addtogroup DMA_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral State and Error functions ***************************************/
-HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
-uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup DMA_Private_Macros DMA Private Macros
-  * @{
-  */
-
-#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
-                                     ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
-                                     ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
-
-#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
-
-#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
-                                            ((STATE) == DMA_PINC_DISABLE))
-
-#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
-                                        ((STATE) == DMA_MINC_DISABLE))
-
-#define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \
-                                     ((REQUEST) == DMA_REQUEST_1) || \
-                                     ((REQUEST) == DMA_REQUEST_2) || \
-                                     ((REQUEST) == DMA_REQUEST_3) || \
-                                     ((REQUEST) == DMA_REQUEST_4) || \
-                                     ((REQUEST) == DMA_REQUEST_5) || \
-                                     ((REQUEST) == DMA_REQUEST_6) || \
-                                     ((REQUEST) == DMA_REQUEST_7))
-
-#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
-                                           ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
-                                           ((SIZE) == DMA_PDATAALIGN_WORD))
-
-#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
-                                       ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
-                                       ((SIZE) == DMA_MDATAALIGN_WORD ))
-
-#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
-                           ((MODE) == DMA_CIRCULAR))
-
-#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
-                                   ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
-                                   ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
-                                   ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
-
-/**
-  * @}
-  */ 
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L4xx_HAL_DMA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/inc/stm32l4xx_hal_flash.h b/stmhal/hal/l4/inc/stm32l4xx_hal_flash.h
deleted file mode 100644
index 1bf0c52269..0000000000
--- a/stmhal/hal/l4/inc/stm32l4xx_hal_flash.h
+++ /dev/null
@@ -1,829 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_flash.h
-  * @author  MCD Application Team
-  * @version V1.3.0 
-  * @date    29-January-2016
-  * @brief   Header file of FLASH HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L4xx_HAL_FLASH_H
-#define __STM32L4xx_HAL_FLASH_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup FLASH
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Types FLASH Exported Types
-  * @{
-  */
-
-/**
-  * @brief  FLASH Erase structure definition
-  */
-typedef struct
-{ 
-  uint32_t TypeErase;   /*!< Mass erase or page erase.
-                             This parameter can be a value of @ref FLASH_Type_Erase */
-  uint32_t Banks;       /*!< Select bank to erase.
-                             This parameter must be a value of @ref FLASH_Banks 
-                             (FLASH_BANK_BOTH should be used only for mass erase) */        
-  uint32_t Page;        /*!< Initial Flash page to erase when page erase is disabled
-                             This parameter must be a value between 0 and (max number of pages in the bank - 1) 
-                             (eg : 255 for 1MB dual bank) */
-  uint32_t NbPages;     /*!< Number of pages to be erased.
-                             This parameter must be a value between 1 and (max number of pages in the bank - value of initial page)*/           
-} FLASH_EraseInitTypeDef;
-
-/**
-  * @brief  FLASH Option Bytes Program structure definition
-  */
-typedef struct
-{
-  uint32_t OptionType;     /*!< Option byte to be configured.
-                                This parameter can be a combination of the values of @ref FLASH_OB_Type */
-  uint32_t WRPArea;        /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP).
-                                Only one WRP area could be programmed at the same time.
-                                This parameter can be value of @ref FLASH_OB_WRP_Area */
-  uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP).
-                                This parameter must be a value between 0 and (max number of pages in the bank - 1)
-                                (eg : 25 for 1MB dual bank) */
-  uint32_t WRPEndOffset;   /*!< Write protection end offset (used for OPTIONBYTE_WRP).
-                                This parameter must be a value between WRPStartOffset and (max number of pages in the bank - 1) */
-  uint32_t RDPLevel;       /*!< Set the read protection level.. (used for OPTIONBYTE_RDP).
-                                This parameter can be a value of @ref FLASH_OB_Read_Protection */
-  uint32_t USERType;       /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER).
-                                This parameter can be a combination of @ref FLASH_OB_USER_Type */
-  uint32_t USERConfig;     /*!< Value of the user option byte (used for OPTIONBYTE_USER).
-                                This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL,
-                                @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
-                                @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW, 
-                                @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY, 
-                                @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_BFB2, 
-                                @ref FLASH_OB_USER_DUALBANK, @ref FLASH_OB_USER_nBOOT1, 
-                                @ref FLASH_OB_USER_SRAM2_PE and @ref FLASH_OB_USER_SRAM2_RST */
-  uint32_t PCROPConfig;    /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP).
-                                This parameter must be a combination of @ref FLASH_Banks (except FLASH_BANK_BOTH) 
-                                and @ref FLASH_OB_PCROP_RDP */
-  uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP).
-                                This parameter must be a value between begin and end of bank 
-                                => Be careful of the bank swapping for the address */
-  uint32_t PCROPEndAddr;   /*!< PCROP End address (used for OPTIONBYTE_PCROP).
-                                This parameter must be a value between PCROP Start address and end of bank */
-} FLASH_OBProgramInitTypeDef;
-
-/**
-  * @brief  FLASH Procedure structure definition
-  */
-typedef enum 
-{
-  FLASH_PROC_NONE = 0,
-  FLASH_PROC_PAGE_ERASE,
-  FLASH_PROC_MASS_ERASE,
-  FLASH_PROC_PROGRAM,
-  FLASH_PROC_PROGRAM_LAST
-} FLASH_ProcedureTypeDef;
-
-/** 
-  * @brief  FLASH handle Structure definition  
-  */
-typedef struct
-{
-  HAL_LockTypeDef             Lock;              /* FLASH locking object */
-  __IO uint32_t               ErrorCode;         /* FLASH error code */
-  __IO FLASH_ProcedureTypeDef ProcedureOnGoing;  /* Internal variable to indicate which procedure is ongoing or not in IT context */
-  __IO uint32_t               Address;           /* Internal variable to save address selected for program in IT context */
-  __IO uint32_t               Bank;              /* Internal variable to save current bank selected during erase in IT context */
-  __IO uint32_t               Page;              /* Internal variable to define the current page which is erasing in IT context */
-  __IO uint32_t               NbPagesToErase;    /* Internal variable to save the remaining pages to erase in IT context */
-}FLASH_ProcessTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
-  * @{
-  */
-
-/** @defgroup FLASH_Error FLASH Error
-  * @{
-  */ 
-#define HAL_FLASH_ERROR_NONE      ((uint32_t)0x00000000)
-#define HAL_FLASH_ERROR_OP        ((uint32_t)0x00000001)
-#define HAL_FLASH_ERROR_PROG      ((uint32_t)0x00000002)
-#define HAL_FLASH_ERROR_WRP       ((uint32_t)0x00000004)
-#define HAL_FLASH_ERROR_PGA       ((uint32_t)0x00000008)
-#define HAL_FLASH_ERROR_SIZ       ((uint32_t)0x00000010)
-#define HAL_FLASH_ERROR_PGS       ((uint32_t)0x00000020)
-#define HAL_FLASH_ERROR_MIS       ((uint32_t)0x00000040)
-#define HAL_FLASH_ERROR_FAST      ((uint32_t)0x00000080)
-#define HAL_FLASH_ERROR_RD        ((uint32_t)0x00000100)
-#define HAL_FLASH_ERROR_OPTV      ((uint32_t)0x00000200)
-#define HAL_FLASH_ERROR_ECCD      ((uint32_t)0x00000400)
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Type_Erase FLASH Erase Type
-  * @{
-  */ 
-#define FLASH_TYPEERASE_PAGES     ((uint32_t)0x00)  /*!<Pages erase only*/
-#define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01)  /*!<Flash mass erase activation*/
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Banks FLASH Banks
-  * @{
-  */
-#define FLASH_BANK_1              ((uint32_t)0x01)                          /*!< Bank 1   */
-#define FLASH_BANK_2              ((uint32_t)0x02)                          /*!< Bank 2   */
-#define FLASH_BANK_BOTH           ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2)) /*!< Bank1 and Bank2  */
-/**
-  * @}
-  */
-
-
-/** @defgroup FLASH_Type_Program FLASH Program Type
-  * @{
-  */
-#define FLASH_TYPEPROGRAM_DOUBLEWORD    ((uint32_t)0x00)  /*!<Program a double-word (64-bit) at a specified address.*/
-#define FLASH_TYPEPROGRAM_FAST          ((uint32_t)0x01)  /*!<Fast program a 32 row double-word (64-bit) at a specified address.
-                                                                 And another 32 row double-word (64-bit) will be programmed */
-#define FLASH_TYPEPROGRAM_FAST_AND_LAST ((uint32_t)0x02)  /*!<Fast program a 32 row double-word (64-bit) at a specified address.
-                                                                 And this is the last 32 row double-word (64-bit) programmed */
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_OB_Type FLASH Option Bytes Type
-  * @{
-  */
-#define OPTIONBYTE_WRP            ((uint32_t)0x01)  /*!< WRP option byte configuration */
-#define OPTIONBYTE_RDP            ((uint32_t)0x02)  /*!< RDP option byte configuration */
-#define OPTIONBYTE_USER           ((uint32_t)0x04)  /*!< USER option byte configuration */
-#define OPTIONBYTE_PCROP          ((uint32_t)0x08)  /*!< PCROP option byte configuration */
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_OB_WRP_Area FLASH WRP Area
-  * @{
-  */ 
-#define OB_WRPAREA_BANK1_AREAA    ((uint32_t)0x00)  /*!< Flash Bank 1 Area A */
-#define OB_WRPAREA_BANK1_AREAB    ((uint32_t)0x01)  /*!< Flash Bank 1 Area B */
-#define OB_WRPAREA_BANK2_AREAA    ((uint32_t)0x02)  /*!< Flash Bank 2 Area A */
-#define OB_WRPAREA_BANK2_AREAB    ((uint32_t)0x04)  /*!< Flash Bank 2 Area B */
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_OB_Read_Protection FLASH Option Bytes Read Protection
-  * @{
-  */
-#define OB_RDP_LEVEL_0            ((uint32_t)0xAA)
-#define OB_RDP_LEVEL_1            ((uint32_t)0xBB)
-#define OB_RDP_LEVEL_2            ((uint32_t)0xCC) /*!< Warning: When enabling read protection level 2 
-                                                        it's no more possible to go back to level 1 or 0 */
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_OB_USER_Type FLASH Option Bytes User Type
-  * @{
-  */
-#define OB_USER_BOR_LEV           ((uint32_t)0x0001)                   /*!< BOR reset Level */
-#define OB_USER_nRST_STOP         ((uint32_t)0x0002)                   /*!< Reset generated when entering the stop mode */
-#define OB_USER_nRST_STDBY        ((uint32_t)0x0004)                   /*!< Reset generated when entering the standby mode */
-#define OB_USER_IWDG_SW           ((uint32_t)0x0008)                   /*!< Independent watchdog selection */
-#define OB_USER_IWDG_STOP         ((uint32_t)0x0010)                   /*!< Independent watchdog counter freeze in stop mode */
-#define OB_USER_IWDG_STDBY        ((uint32_t)0x0020)                   /*!< Independent watchdog counter freeze in standby mode */
-#define OB_USER_WWDG_SW           ((uint32_t)0x0040)                   /*!< Window watchdog selection */
-#define OB_USER_BFB2              ((uint32_t)0x0080)                   /*!< Dual-bank boot */
-#define OB_USER_DUALBANK          ((uint32_t)0x0100)                   /*!< Dual-Bank on 512KB or 256KB Flash memory devices */
-#define OB_USER_nBOOT1            ((uint32_t)0x0200)                   /*!< Boot configuration */
-#define OB_USER_SRAM2_PE          ((uint32_t)0x0400)                   /*!< SRAM2 parity check enable */
-#define OB_USER_SRAM2_RST         ((uint32_t)0x0800)                   /*!< SRAM2 Erase when system reset */
-#define OB_USER_nRST_SHDW         ((uint32_t)0x1000)                   /*!< Reset generated when entering the shutdown mode */
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level
-  * @{
-  */
-#define OB_BOR_LEVEL_0            ((uint32_t)FLASH_OPTR_BOR_LEV_0)     /*!< Reset level threshold is around 1.7V */
-#define OB_BOR_LEVEL_1            ((uint32_t)FLASH_OPTR_BOR_LEV_1)     /*!< Reset level threshold is around 2.0V */
-#define OB_BOR_LEVEL_2            ((uint32_t)FLASH_OPTR_BOR_LEV_2)     /*!< Reset level threshold is around 2.2V */
-#define OB_BOR_LEVEL_3            ((uint32_t)FLASH_OPTR_BOR_LEV_3)     /*!< Reset level threshold is around 2.5V */
-#define OB_BOR_LEVEL_4            ((uint32_t)FLASH_OPTR_BOR_LEV_4)     /*!< Reset level threshold is around 2.8V */
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop 
-  * @{
-  */
-#define OB_STOP_RST               ((uint32_t)0x0000)                   /*!< Reset generated when entering the stop mode */
-#define OB_STOP_NORST             ((uint32_t)FLASH_OPTR_nRST_STOP)     /*!< No reset generated when entering the stop mode */
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby
-  * @{
-  */
-#define OB_STANDBY_RST            ((uint32_t)0x0000)                   /*!< Reset generated when entering the standby mode */
-#define OB_STANDBY_NORST          ((uint32_t)FLASH_OPTR_nRST_STDBY)    /*!< No reset generated when entering the standby mode */
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown
-  * @{
-  */
-#define OB_SHUTDOWN_RST           ((uint32_t)0x0000)                   /*!< Reset generated when entering the shutdown mode */
-#define OB_SHUTDOWN_NORST         ((uint32_t)FLASH_OPTR_nRST_SHDW)     /*!< No reset generated when entering the shutdown mode */
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type
-  * @{
-  */
-#define OB_IWDG_HW                ((uint32_t)0x00000)                  /*!< Hardware independent watchdog */
-#define OB_IWDG_SW                ((uint32_t)FLASH_OPTR_IWDG_SW)       /*!< Software independent watchdog */
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop
-  * @{
-  */
-#define OB_IWDG_STOP_FREEZE       ((uint32_t)0x00000)                  /*!< Independent watchdog counter is frozen in Stop mode */
-#define OB_IWDG_STOP_RUN          ((uint32_t)FLASH_OPTR_IWDG_STOP)     /*!< Independent watchdog counter is running in Stop mode */
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby
-  * @{
-  */
-#define OB_IWDG_STDBY_FREEZE      ((uint32_t)0x00000)                  /*!< Independent watchdog counter is frozen in Standby mode */
-#define OB_IWDG_STDBY_RUN         ((uint32_t)FLASH_OPTR_IWDG_STDBY)    /*!< Independent watchdog counter is running in Standby mode */
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type
-  * @{
-  */
-#define OB_WWDG_HW                ((uint32_t)0x00000)                  /*!< Hardware window watchdog */
-#define OB_WWDG_SW                ((uint32_t)FLASH_OPTR_WWDG_SW)       /*!< Software window watchdog */
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_OB_USER_BFB2 FLASH Option Bytes User BFB2 Mode
-  * @{
-  */
-#define OB_BFB2_DISABLE           ((uint32_t)0x000000)                 /*!< Dual-bank boot disable */
-#define OB_BFB2_ENABLE            ((uint32_t)FLASH_OPTR_BFB2)          /*!< Dual-bank boot enable */
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_OB_USER_DUALBANK FLASH Option Bytes User Dual-bank Type
-  * @{
-  */
-#define OB_DUALBANK_SINGLE        ((uint32_t)0x000000)                 /*!< 256 KB/512 KB Single-bank Flash */
-#define OB_DUALBANK_DUAL          ((uint32_t)FLASH_OPTR_DUALBANK)      /*!< 256 KB/512 KB Dual-bank Flash */
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type
-  * @{
-  */
-#define OB_BOOT1_SRAM             ((uint32_t)0x000000)                 /*!< Embedded SRAM1 is selected as boot space (if BOOT0=1) */
-#define OB_BOOT1_SYSTEM           ((uint32_t)FLASH_OPTR_nBOOT1)        /*!< System memory is selected as boot space (if BOOT0=1) */
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_OB_USER_SRAM2_PE FLASH Option Bytes User SRAM2 Parity Check Type
-  * @{
-  */
-#define OB_SRAM2_PARITY_ENABLE    ((uint32_t)0x0000000)                /*!< SRAM2 parity check enable */
-#define OB_SRAM2_PARITY_DISABLE   ((uint32_t)FLASH_OPTR_SRAM2_PE)      /*!< SRAM2 parity check disable */
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_OB_USER_SRAM2_RST FLASH Option Bytes User SRAM2 Erase On Reset Type
-  * @{
-  */
-#define OB_SRAM2_RST_ERASE        ((uint32_t)0x0000000)                /*!< SRAM2 erased when a system reset occurs */
-#define OB_SRAM2_RST_NOT_ERASE    ((uint32_t)FLASH_OPTR_SRAM2_RST)     /*!< SRAM2 is not erased when a system reset occurs */
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_OB_PCROP_RDP FLASH Option Bytes PCROP On RDP Level Type
-  * @{
-  */
-#define OB_PCROP_RDP_NOT_ERASE    ((uint32_t)0x00000000)               /*!< PCROP area is not erased when the RDP level 
-                                                                            is decreased from Level 1 to Level 0 */
-#define OB_PCROP_RDP_ERASE        ((uint32_t)FLASH_PCROP1ER_PCROP_RDP) /*!< PCROP area is erased when the RDP level is 
-                                                                            decreased from Level 1 to Level 0 (full mass erase) */
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_Latency FLASH Latency
-  * @{
-  */ 
-#define FLASH_LATENCY_0           FLASH_ACR_LATENCY_0WS                /*!< FLASH Zero wait state */
-#define FLASH_LATENCY_1           FLASH_ACR_LATENCY_1WS                /*!< FLASH One wait state */
-#define FLASH_LATENCY_2           FLASH_ACR_LATENCY_2WS                /*!< FLASH Two wait states */
-#define FLASH_LATENCY_3           FLASH_ACR_LATENCY_3WS                /*!< FLASH Three wait states */
-#define FLASH_LATENCY_4           FLASH_ACR_LATENCY_4WS                /*!< FLASH Four wait states */
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_Keys FLASH Keys
-  * @{
-  */ 
-#define FLASH_KEY1                ((uint32_t)0x45670123U)               /*!< Flash key1 */
-#define FLASH_KEY2                ((uint32_t)0xCDEF89ABU)               /*!< Flash key2: used with FLASH_KEY1 
-                                                                            to unlock the FLASH registers access */
-
-#define FLASH_PDKEY1              ((uint32_t)0x04152637U)               /*!< Flash power down key1 */
-#define FLASH_PDKEY2              ((uint32_t)0xFAFBFCFDU)               /*!< Flash power down key2: used with FLASH_PDKEY1 
-                                                                            to unlock the RUN_PD bit in FLASH_ACR */
-
-#define FLASH_OPTKEY1             ((uint32_t)0x08192A3BU)               /*!< Flash option byte key1 */
-#define FLASH_OPTKEY2             ((uint32_t)0x4C5D6E7FU)               /*!< Flash option byte key2: used with FLASH_OPTKEY1 
-                                                                            to allow option bytes operations */
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Flags FLASH Flags Definition
-  * @{
-  */ 
-#define FLASH_FLAG_EOP            FLASH_SR_EOP                         /*!< FLASH End of operation flag */
-#define FLASH_FLAG_OPERR          FLASH_SR_OPERR                       /*!< FLASH Operation error flag */
-#define FLASH_FLAG_PROGERR        FLASH_SR_PROGERR                     /*!< FLASH Programming error flag */
-#define FLASH_FLAG_WRPERR         FLASH_SR_WRPERR                      /*!< FLASH Write protection error flag */
-#define FLASH_FLAG_PGAERR         FLASH_SR_PGAERR                      /*!< FLASH Programming alignment error flag */
-#define FLASH_FLAG_SIZERR         FLASH_SR_SIZERR                      /*!< FLASH Size error flag  */
-#define FLASH_FLAG_PGSERR         FLASH_SR_PGSERR                      /*!< FLASH Programming sequence error flag */
-#define FLASH_FLAG_MISERR         FLASH_SR_MISERR                      /*!< FLASH Fast programming data miss error flag */
-#define FLASH_FLAG_FASTERR        FLASH_SR_FASTERR                     /*!< FLASH Fast programming error flag */
-#define FLASH_FLAG_RDERR          FLASH_SR_RDERR                       /*!< FLASH PCROP read error flag */
-#define FLASH_FLAG_OPTVERR        FLASH_SR_OPTVERR                     /*!< FLASH Option validity error flag  */
-#define FLASH_FLAG_BSY            FLASH_SR_BSY                         /*!< FLASH Busy flag */
-#define FLASH_FLAG_ECCC           FLASH_ECCR_ECCC                      /*!< FLASH ECC correction */
-#define FLASH_FLAG_ECCD           FLASH_ECCR_ECCD                      /*!< FLASH ECC detection */
-
-#define FLASH_FLAG_ALL_ERRORS     (FLASH_FLAG_OPERR   | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \
-                                   FLASH_FLAG_PGAERR  | FLASH_FLAG_SIZERR  | FLASH_FLAG_PGSERR | \
-                                   FLASH_FLAG_MISERR  | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR  | \
-                                   FLASH_FLAG_OPTVERR | FLASH_FLAG_ECCD)
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition
-  * @brief FLASH Interrupt definition
-  * @{
-  */ 
-#define FLASH_IT_EOP              FLASH_CR_EOPIE                       /*!< End of FLASH Operation Interrupt source */
-#define FLASH_IT_OPERR            FLASH_CR_ERRIE                       /*!< Error Interrupt source */
-#define FLASH_IT_RDERR            FLASH_CR_RDERRIE                     /*!< PCROP Read Error Interrupt source*/
-#define FLASH_IT_ECCC             (FLASH_ECCR_ECCIE >> 24)             /*!< ECC Correction Interrupt source */
-/**
-  * @}
-  */  
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
- *  @brief macros to control FLASH features 
- *  @{
- */
-
-/**
-  * @brief  Set the FLASH Latency.
-  * @param  __LATENCY__: FLASH Latency                   
-  *         This parameter can be one of the following values :
-  *     @arg FLASH_LATENCY_0: FLASH Zero wait state
-  *     @arg FLASH_LATENCY_1: FLASH One wait state    
-  *     @arg FLASH_LATENCY_2: FLASH Two wait states
-  *     @arg FLASH_LATENCY_3: FLASH Three wait states
-  *     @arg FLASH_LATENCY_4: FLASH Four wait states
-  * @retval None
-  */ 
-#define __HAL_FLASH_SET_LATENCY(__LATENCY__)    (MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__)))
-
-/**
-  * @brief  Get the FLASH Latency.
-  * @retval FLASH Latency                   
-  *         This parameter can be one of the following values :
-  *     @arg FLASH_LATENCY_0: FLASH Zero wait state
-  *     @arg FLASH_LATENCY_1: FLASH One wait state    
-  *     @arg FLASH_LATENCY_2: FLASH Two wait states
-  *     @arg FLASH_LATENCY_3: FLASH Three wait states
-  *     @arg FLASH_LATENCY_4: FLASH Four wait states
-  */ 
-#define __HAL_FLASH_GET_LATENCY()               READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)
-
-/**
-  * @brief  Enable the FLASH prefetch buffer.
-  * @retval None
-  */ 
-#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE()    SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
-
-/**
-  * @brief  Disable the FLASH prefetch buffer.
-  * @retval None
-  */
-#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE()   CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
-
-/**
-  * @brief  Enable the FLASH instruction cache.
-  * @retval none
-  */ 
-#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE()  SET_BIT(FLASH->ACR, FLASH_ACR_ICEN)
-
-/**
-  * @brief  Disable the FLASH instruction cache.
-  * @retval none
-  */ 
-#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN)
-
-/**
-  * @brief  Enable the FLASH data cache.
-  * @retval none
-  */ 
-#define __HAL_FLASH_DATA_CACHE_ENABLE()         SET_BIT(FLASH->ACR, FLASH_ACR_DCEN)
-
-/**
-  * @brief  Disable the FLASH data cache.
-  * @retval none
-  */ 
-#define __HAL_FLASH_DATA_CACHE_DISABLE()        CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN)
-
-/**
-  * @brief  Reset the FLASH instruction Cache.
-  * @note   This function must be used only when the Instruction Cache is disabled.  
-  * @retval None
-  */
-#define __HAL_FLASH_INSTRUCTION_CACHE_RESET()   do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);   \
-                                                     CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \
-                                                   } while (0)
-
-/**
-  * @brief  Reset the FLASH data Cache.
-  * @note   This function must be used only when the data Cache is disabled.  
-  * @retval None
-  */
-#define __HAL_FLASH_DATA_CACHE_RESET()          do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);   \
-                                                     CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); \
-                                                   } while (0)
-
-/**
-  * @brief  Enable the FLASH power down during Low-power run mode.
-  * @note   Writing this bit  to 0 this bit, automatically the keys are
-  *         loss and a new unlock sequence is necessary to re-write it to 1.
-  */
-#define __HAL_FLASH_POWER_DOWN_ENABLE()         do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \
-                                                     WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \
-                                                     SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);   \
-                                                   } while (0)
-
-/**
-  * @brief  Disable the FLASH power down during Low-power run mode.
-  * @note   Writing this bit  to 0 this bit, automatically the keys are
-  *         loss and a new unlock sequence is necessary to re-write it to 1.
-  */
-#define __HAL_FLASH_POWER_DOWN_DISABLE()        do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \
-                                                     WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \
-                                                     CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \
-                                                   } while (0)
-
-/**
-  * @brief  Enable the FLASH power down during Low-Power sleep mode
-  * @retval none
-  */ 
-#define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE()    SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
-
-/**
-  * @brief  Disable the FLASH power down during Low-Power sleep mode
-  * @retval none
-  */ 
-#define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE()   CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
-
-/**
-  * @}
-  */  
-
-/** @defgroup FLASH_Interrupt FLASH Interrupts Macros
- *  @brief macros to handle FLASH interrupts
- * @{
- */ 
-
-/**
-  * @brief  Enable the specified FLASH interrupt.
-  * @param  __INTERRUPT__: FLASH interrupt 
-  *         This parameter can be any combination of the following values:
-  *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
-  *     @arg FLASH_IT_OPERR: Error Interrupt    
-  *     @arg FLASH_IT_RDERR: PCROP Read Error Interrupt
-  *     @arg FLASH_IT_ECCC: ECC Correction Interrupt
-  * @retval none
-  */  
-#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)    do { if((__INTERRUPT__) & FLASH_IT_ECCC) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
-                                                     if((__INTERRUPT__) & (~FLASH_IT_ECCC)) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
-                                                   } while(0)
-
-/**
-  * @brief  Disable the specified FLASH interrupt.
-  * @param  __INTERRUPT__: FLASH interrupt 
-  *         This parameter can be any combination of the following values:
-  *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
-  *     @arg FLASH_IT_OPERR: Error Interrupt    
-  *     @arg FLASH_IT_RDERR: PCROP Read Error Interrupt
-  *     @arg FLASH_IT_ECCC: ECC Correction Interrupt
-  * @retval none
-  */  
-#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)   do { if((__INTERRUPT__) & FLASH_IT_ECCC) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
-                                                     if((__INTERRUPT__) & (~FLASH_IT_ECCC)) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
-                                                   } while(0)
-
-/**
-  * @brief  Check whether the specified FLASH flag is set or not.
-  * @param  __FLAG__: specifies the FLASH flag to check.
-  *   This parameter can be one of the following values:
-  *     @arg FLASH_FLAG_EOP: FLASH End of Operation flag
-  *     @arg FLASH_FLAG_OPERR: FLASH Operation error flag
-  *     @arg FLASH_FLAG_PROGERR: FLASH Programming error flag
-  *     @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag 
-  *     @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
-  *     @arg FLASH_FLAG_SIZERR: FLASH Size error flag
-  *     @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
-  *     @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag
-  *     @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag
-  *     @arg FLASH_FLAG_RDERR: FLASH PCROP read  error flag
-  *     @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
-  *     @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag 
-  *     @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected
-  *     @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected
-  * @retval The new state of FLASH_FLAG (SET or RESET).
-  */
-#define __HAL_FLASH_GET_FLAG(__FLAG__)          (((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) ? \
-                                                 (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__))  : \
-                                                 (READ_BIT(FLASH->SR,   (__FLAG__)) == (__FLAG__)))
-
-/**
-  * @brief  Clear the FLASH's pending flags.
-  * @param  __FLAG__: specifies the FLASH flags to clear.
-  *   This parameter can be any combination of the following values:
-  *     @arg FLASH_FLAG_EOP: FLASH End of Operation flag
-  *     @arg FLASH_FLAG_OPERR: FLASH Operation error flag
-  *     @arg FLASH_FLAG_PROGERR: FLASH Programming error flag
-  *     @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag 
-  *     @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
-  *     @arg FLASH_FLAG_SIZERR: FLASH Size error flag
-  *     @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
-  *     @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag
-  *     @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag
-  *     @arg FLASH_FLAG_RDERR: FLASH PCROP read  error flag
-  *     @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
-  *     @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected
-  *     @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected
-  *     @arg FLASH_FLAG_ALL_ERRORS: FLASH All errors flags
-  * @retval None
-  */
-#define __HAL_FLASH_CLEAR_FLAG(__FLAG__)        do { if((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) { SET_BIT(FLASH->ECCR, ((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\
-                                                     if((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\
-                                                   } while(0)
-/**
-  * @}
-  */  
-
-/* Include FLASH HAL Extended module */
-#include "stm32l4xx_hal_flash_ex.h"
-#include "stm32l4xx_hal_flash_ramfunc.h"
-
-/* Exported functions --------------------------------------------------------*/ 
-/** @addtogroup FLASH_Exported_Functions
-  * @{
-  */
-
-/* Program operation functions  ***********************************************/
-/** @addtogroup FLASH_Exported_Functions_Group1
-  * @{
-  */
-HAL_StatusTypeDef  HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
-HAL_StatusTypeDef  HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
-/* FLASH IRQ handler method */
-void               HAL_FLASH_IRQHandler(void);
-/* Callbacks in non blocking modes */ 
-void               HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
-void               HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
-/**
-  * @}
-  */
-
-/* Peripheral Control functions  **********************************************/
-/** @addtogroup FLASH_Exported_Functions_Group2
-  * @{
-  */
-HAL_StatusTypeDef  HAL_FLASH_Unlock(void);
-HAL_StatusTypeDef  HAL_FLASH_Lock(void);
-/* Option bytes control */
-HAL_StatusTypeDef  HAL_FLASH_OB_Unlock(void);
-HAL_StatusTypeDef  HAL_FLASH_OB_Lock(void);
-HAL_StatusTypeDef  HAL_FLASH_OB_Launch(void);
-/**
-  * @}
-  */
-
-/* Peripheral State functions  ************************************************/
-/** @addtogroup FLASH_Exported_Functions_Group3
-  * @{
-  */
-uint32_t HAL_FLASH_GetError(void);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private constants --------------------------------------------------------*/
-/** @defgroup FLASH_Private_Constants FLASH Private Constants
-  * @{
-  */
-#define FLASH_SIZE_DATA_REGISTER           ((uint32_t)0x1FFF75E0)
-    
-#define FLASH_SIZE                         ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x400 << 10) : \
-                                            (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10))
-
-#define FLASH_BANK_SIZE                    (FLASH_SIZE >> 1)
-
-#define FLASH_PAGE_SIZE                    ((uint32_t)0x800)
-
-#define FLASH_TIMEOUT_VALUE                ((uint32_t)50000)/* 50 s */
-/**
-  * @}
-  */
- 
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup FLASH_Private_Macros FLASH Private Macros
- *  @{
- */
-
-#define IS_FLASH_TYPEERASE(VALUE)          (((VALUE) == FLASH_TYPEERASE_PAGES) || \
-                                            ((VALUE) == FLASH_TYPEERASE_MASSERASE))  
-
-#define IS_FLASH_BANK(BANK)                (((BANK) == FLASH_BANK_1)  || \
-                                            ((BANK) == FLASH_BANK_2)  || \
-                                            ((BANK) == FLASH_BANK_BOTH))
-
-#define IS_FLASH_BANK_EXCLUSIVE(BANK)      (((BANK) == FLASH_BANK_1)  || \
-                                            ((BANK) == FLASH_BANK_2))
-
-#define IS_FLASH_TYPEPROGRAM(VALUE)        (((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \
-                                            ((VALUE) == FLASH_TYPEPROGRAM_FAST) || \
-                                            ((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST))  
-
-#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE)        && ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x400) ? \
-                                            ((ADDRESS) <= FLASH_BASE+0xFFFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? \
-                                            ((ADDRESS) <= FLASH_BASE+0x7FFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? \
-                                            ((ADDRESS) <= FLASH_BASE+0x3FFFF) : ((ADDRESS) <= FLASH_BASE+0xFFFFF))))) 
-
-#define IS_FLASH_OTP_ADDRESS(ADDRESS)      (((ADDRESS) >= 0x1FFF7000) && ((ADDRESS) <= 0x1FFF73FF))
-
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS)  (IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) || IS_FLASH_OTP_ADDRESS(ADDRESS))
-
-#define IS_FLASH_PAGE(PAGE)                (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x400) ? ((PAGE) < 256) : \
-                                            ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? ((PAGE) < 128) : \
-                                            ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 64) : \
-                                            ((PAGE) < 256)))))
-
-#define IS_OPTIONBYTE(VALUE)               (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP)))
-
-#define IS_OB_WRPAREA(VALUE)               (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \
-                                            ((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB))
-
-#define IS_OB_RDP_LEVEL(LEVEL)             (((LEVEL) == OB_RDP_LEVEL_0)   ||\
-                                            ((LEVEL) == OB_RDP_LEVEL_1)/* ||\
-                                            ((LEVEL) == OB_RDP_LEVEL_2)*/)
-
-#define IS_OB_USER_TYPE(TYPE)              (((TYPE) <= (uint32_t)0x1FFF) && ((TYPE) != 0))
-
-#define IS_OB_USER_BOR_LEVEL(LEVEL)        (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \
-                                            ((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3) || \
-                                            ((LEVEL) == OB_BOR_LEVEL_4))
-
-#define IS_OB_USER_STOP(VALUE)             (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST))
-
-#define IS_OB_USER_STANDBY(VALUE)          (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST))
-
-#define IS_OB_USER_SHUTDOWN(VALUE)         (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST))
-
-#define IS_OB_USER_IWDG(VALUE)             (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW))
-
-#define IS_OB_USER_IWDG_STOP(VALUE)        (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN))
-
-#define IS_OB_USER_IWDG_STDBY(VALUE)       (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN))
-
-#define IS_OB_USER_WWDG(VALUE)             (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW))
-
-#define IS_OB_USER_BFB2(VALUE)             (((VALUE) == OB_BFB2_DISABLE) || ((VALUE) == OB_BFB2_ENABLE))
-
-#define IS_OB_USER_DUALBANK(VALUE)         (((VALUE) == OB_DUALBANK_SINGLE) || ((VALUE) == OB_DUALBANK_DUAL))
-
-#define IS_OB_USER_BOOT1(VALUE)            (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM))
-
-#define IS_OB_USER_SRAM2_PARITY(VALUE)     (((VALUE) == OB_SRAM2_PARITY_ENABLE) || ((VALUE) == OB_SRAM2_PARITY_DISABLE))
-
-#define IS_OB_USER_SRAM2_RST(VALUE)        (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE))
-
-#define IS_OB_PCROP_RDP(VALUE)             (((VALUE) == OB_PCROP_RDP_NOT_ERASE) || ((VALUE) == OB_PCROP_RDP_ERASE))
-
-#define IS_FLASH_LATENCY(LATENCY)          (((LATENCY) == FLASH_LATENCY_0) || \
-                                            ((LATENCY) == FLASH_LATENCY_1) || \
-                                            ((LATENCY) == FLASH_LATENCY_2) || \
-                                            ((LATENCY) == FLASH_LATENCY_3) || \
-                                            ((LATENCY) == FLASH_LATENCY_4))
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L4xx_HAL_FLASH_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/inc/stm32l4xx_hal_flash_ex.h b/stmhal/hal/l4/inc/stm32l4xx_hal_flash_ex.h
deleted file mode 100644
index be3540d4b7..0000000000
--- a/stmhal/hal/l4/inc/stm32l4xx_hal_flash_ex.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_flash_ex.h
-  * @author  MCD Application Team
-  * @version V1.3.0 
-  * @date    29-January-2016
-  * @brief   Header file of FLASH HAL Extended module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L4xx_HAL_FLASH_EX_H
-#define __STM32L4xx_HAL_FLASH_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup FLASHEx
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-
-/* Exported constants --------------------------------------------------------*/
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/ 
-/** @addtogroup FLASHEx_Exported_Functions
-  * @{
-  */
-
-/* Extended Program operation functions  *************************************/
-/** @addtogroup FLASHEx_Exported_Functions_Group1
-  * @{
-  */
-HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
-HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
-HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
-void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L4xx_HAL_FLASH_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/inc/stm32l4xx_hal_flash_ramfunc.h b/stmhal/hal/l4/inc/stm32l4xx_hal_flash_ramfunc.h
deleted file mode 100644
index c6eb07b725..0000000000
--- a/stmhal/hal/l4/inc/stm32l4xx_hal_flash_ramfunc.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_flash_ramfunc.h
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   Header file of FLASH RAMFUNC driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L4xx_FLASH_RAMFUNC_H
-#define __STM32L4xx_FLASH_RAMFUNC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup FLASH_RAMFUNC
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/* Exported macro ------------------------------------------------------------*/
-/** 
-  * @brief  __RAM_FUNC definition
-  */ 
-#if defined ( __CC_ARM   )
-/* ARM Compiler
-   ------------
-   RAM functions are defined using the toolchain options. 
-   Functions that are executed in RAM should reside in a separate source module.
-   Using the 'Options for File' dialog you can simply change the 'Code / Const' 
-   area of a module to a memory space in physical RAM.
-   Available memory areas are declared in the 'Target' tab of the 'Options for Target'
-   dialog. 
-*/
-#define __RAM_FUNC HAL_StatusTypeDef 
-
-#elif defined ( __ICCARM__ )
-/* ICCARM Compiler
-   ---------------
-   RAM functions are defined using a specific toolchain keyword "__ramfunc". 
-*/
-#define __RAM_FUNC __ramfunc HAL_StatusTypeDef
-
-#elif defined   (  __GNUC__  )
-/* GNU Compiler
-   ------------
-  RAM functions are defined using a specific toolchain attribute 
-   "__attribute__((section(".RamFunc")))".
-*/
-#define __RAM_FUNC HAL_StatusTypeDef  __attribute__((section(".RamFunc")))
-
-#endif
-                                      
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup FLASH_RAMFUNC_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1
-  * @{
-  */
-/* Peripheral Control functions  ************************************************/
-__RAM_FUNC  HAL_FLASHEx_EnableRunPowerDown(void);
-__RAM_FUNC  HAL_FLASHEx_DisableRunPowerDown(void);
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L4xx_FLASH_RAMFUNC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/inc/stm32l4xx_hal_gpio.h b/stmhal/hal/l4/inc/stm32l4xx_hal_gpio.h
deleted file mode 100644
index 20c73ec096..0000000000
--- a/stmhal/hal/l4/inc/stm32l4xx_hal_gpio.h
+++ /dev/null
@@ -1,317 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_gpio.h
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   Header file of GPIO HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L4xx_HAL_GPIO_H
-#define __STM32L4xx_HAL_GPIO_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup GPIO
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup GPIO_Exported_Types GPIO Exported Types
-  * @{
-  */
-/**
-  * @brief   GPIO Init structure definition
-  */
-typedef struct
-{
-  uint32_t Pin;        /*!< Specifies the GPIO pins to be configured.
-                           This parameter can be any value of @ref GPIO_pins */
-
-  uint32_t Mode;       /*!< Specifies the operating mode for the selected pins.
-                           This parameter can be a value of @ref GPIO_mode */
-
-  uint32_t Pull;       /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
-                           This parameter can be a value of @ref GPIO_pull */
-
-  uint32_t Speed;      /*!< Specifies the speed for the selected pins.
-                           This parameter can be a value of @ref GPIO_speed */
-
-  uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins 
-                            This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
-}GPIO_InitTypeDef;
-
-/**
-  * @brief  GPIO Bit SET and Bit RESET enumeration
-  */
-typedef enum
-{
-  GPIO_PIN_RESET = 0,
-  GPIO_PIN_SET
-}GPIO_PinState;
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
-  * @{
-  */
-/** @defgroup GPIO_pins GPIO pins
-  * @{
-  */
-#define GPIO_PIN_0                 ((uint16_t)0x0001)  /* Pin 0 selected    */
-#define GPIO_PIN_1                 ((uint16_t)0x0002)  /* Pin 1 selected    */
-#define GPIO_PIN_2                 ((uint16_t)0x0004)  /* Pin 2 selected    */
-#define GPIO_PIN_3                 ((uint16_t)0x0008)  /* Pin 3 selected    */
-#define GPIO_PIN_4                 ((uint16_t)0x0010)  /* Pin 4 selected    */
-#define GPIO_PIN_5                 ((uint16_t)0x0020)  /* Pin 5 selected    */
-#define GPIO_PIN_6                 ((uint16_t)0x0040)  /* Pin 6 selected    */
-#define GPIO_PIN_7                 ((uint16_t)0x0080)  /* Pin 7 selected    */
-#define GPIO_PIN_8                 ((uint16_t)0x0100)  /* Pin 8 selected    */
-#define GPIO_PIN_9                 ((uint16_t)0x0200)  /* Pin 9 selected    */
-#define GPIO_PIN_10                ((uint16_t)0x0400)  /* Pin 10 selected   */
-#define GPIO_PIN_11                ((uint16_t)0x0800)  /* Pin 11 selected   */
-#define GPIO_PIN_12                ((uint16_t)0x1000)  /* Pin 12 selected   */
-#define GPIO_PIN_13                ((uint16_t)0x2000)  /* Pin 13 selected   */
-#define GPIO_PIN_14                ((uint16_t)0x4000)  /* Pin 14 selected   */
-#define GPIO_PIN_15                ((uint16_t)0x8000)  /* Pin 15 selected   */
-#define GPIO_PIN_All               ((uint16_t)0xFFFF)  /* All pins selected */
-
-#define GPIO_PIN_MASK              ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_mode GPIO mode
-  * @brief GPIO Configuration Mode
-  *        Elements values convention: 0xX0yz00YZ
-  *           - X  : GPIO mode or EXTI Mode
-  *           - y  : External IT or Event trigger detection
-  *           - z  : IO configuration on External IT or Event
-  *           - Y  : Output type (Push Pull or Open Drain)
-  *           - Z  : IO Direction mode (Input, Output, Alternate or Analog)
-  * @{
-  */
-#define  GPIO_MODE_INPUT                        ((uint32_t)0x00000000)   /*!< Input Floating Mode                   */
-#define  GPIO_MODE_OUTPUT_PP                    ((uint32_t)0x00000001)   /*!< Output Push Pull Mode                 */
-#define  GPIO_MODE_OUTPUT_OD                    ((uint32_t)0x00000011)   /*!< Output Open Drain Mode                */
-#define  GPIO_MODE_AF_PP                        ((uint32_t)0x00000002)   /*!< Alternate Function Push Pull Mode     */
-#define  GPIO_MODE_AF_OD                        ((uint32_t)0x00000012)   /*!< Alternate Function Open Drain Mode    */
-#define  GPIO_MODE_ANALOG                       ((uint32_t)0x00000003)   /*!< Analog Mode  */
-#define  GPIO_MODE_ANALOG_ADC_CONTROL           ((uint32_t)0x0000000B)   /*!< Analog Mode for ADC conversion */
-#define  GPIO_MODE_IT_RISING                    ((uint32_t)0x10110000)   /*!< External Interrupt Mode with Rising edge trigger detection          */
-#define  GPIO_MODE_IT_FALLING                   ((uint32_t)0x10210000)   /*!< External Interrupt Mode with Falling edge trigger detection         */
-#define  GPIO_MODE_IT_RISING_FALLING            ((uint32_t)0x10310000)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
-#define  GPIO_MODE_EVT_RISING                   ((uint32_t)0x10120000)   /*!< External Event Mode with Rising edge trigger detection               */
-#define  GPIO_MODE_EVT_FALLING                  ((uint32_t)0x10220000)   /*!< External Event Mode with Falling edge trigger detection              */
-#define  GPIO_MODE_EVT_RISING_FALLING           ((uint32_t)0x10320000)   /*!< External Event Mode with Rising/Falling edge trigger detection       */
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_speed GPIO speed
-  * @brief GPIO Output Maximum frequency
-  * @{
-  */
-#define  GPIO_SPEED_FREQ_LOW        ((uint32_t)0x00000000)   /*!< range up to 5 MHz, please refer to the product datasheet */
-#define  GPIO_SPEED_FREQ_MEDIUM     ((uint32_t)0x00000001)   /*!< range  5 MHz to 25 MHz, please refer to the product datasheet */
-#define  GPIO_SPEED_FREQ_HIGH       ((uint32_t)0x00000002)   /*!< range 25 MHz to 50 MHz, please refer to the product datasheet */
-#define  GPIO_SPEED_FREQ_VERY_HIGH  ((uint32_t)0x00000003)   /*!< range 50 MHz to 80 MHz, please refer to the product datasheet */
-/**
-  * @}
-  */
-
- /** @defgroup GPIO_pull GPIO pull
-   * @brief GPIO Pull-Up or Pull-Down Activation
-   * @{
-   */
-#define  GPIO_NOPULL        ((uint32_t)0x00000000)   /*!< No Pull-up or Pull-down activation  */
-#define  GPIO_PULLUP        ((uint32_t)0x00000001)   /*!< Pull-up activation                  */
-#define  GPIO_PULLDOWN      ((uint32_t)0x00000002)   /*!< Pull-down activation                */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
-  * @{
-  */
-  
-/**
-  * @brief  Check whether the specified EXTI line flag is set or not.
-  * @param  __EXTI_LINE__: specifies the EXTI line flag to check.
-  *         This parameter can be GPIO_PIN_x where x can be(0..15)
-  * @retval The new state of __EXTI_LINE__ (SET or RESET).
-  */
-#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__)       (EXTI->PR1 & (__EXTI_LINE__))
-
-/**
-  * @brief  Clear the EXTI's line pending flags.
-  * @param  __EXTI_LINE__: specifies the EXTI lines flags to clear.
-  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
-  * @retval None
-  */
-#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__)     (EXTI->PR1 = (__EXTI_LINE__))
-
-/**
-  * @brief  Check whether the specified EXTI line is asserted or not.
-  * @param  __EXTI_LINE__: specifies the EXTI line to check.
-  *          This parameter can be GPIO_PIN_x where x can be(0..15)
-  * @retval The new state of __EXTI_LINE__ (SET or RESET).
-  */
-#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__)         (EXTI->PR1 & (__EXTI_LINE__))
-
-/**
-  * @brief  Clear the EXTI's line pending bits.
-  * @param  __EXTI_LINE__: specifies the EXTI lines to clear.
-  *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
-  * @retval None
-  */
-#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__)       (EXTI->PR1 = (__EXTI_LINE__))
-
-/**
-  * @brief  Generate a Software interrupt on selected EXTI line.
-  * @param  __EXTI_LINE__: specifies the EXTI line to check.
-  *          This parameter can be GPIO_PIN_x where x can be(0..15)
-  * @retval None
-  */
-#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__)  (EXTI->SWIER1 |= (__EXTI_LINE__))
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup GPIO_Private_Macros GPIO Private Macros
-  * @{
-  */
-#define IS_GPIO_PIN_ACTION(ACTION)  (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
-
-#define IS_GPIO_PIN(__PIN__)        (((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00)
-
-#define IS_GPIO_MODE(__MODE__)      (((__MODE__) == GPIO_MODE_INPUT)              ||\
-                                     ((__MODE__) == GPIO_MODE_OUTPUT_PP)          ||\
-                                     ((__MODE__) == GPIO_MODE_OUTPUT_OD)          ||\
-                                     ((__MODE__) == GPIO_MODE_AF_PP)              ||\
-                                     ((__MODE__) == GPIO_MODE_AF_OD)              ||\
-                                     ((__MODE__) == GPIO_MODE_IT_RISING)          ||\
-                                     ((__MODE__) == GPIO_MODE_IT_FALLING)         ||\
-                                     ((__MODE__) == GPIO_MODE_IT_RISING_FALLING)  ||\
-                                     ((__MODE__) == GPIO_MODE_EVT_RISING)         ||\
-                                     ((__MODE__) == GPIO_MODE_EVT_FALLING)        ||\
-                                     ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\
-                                     ((__MODE__) == GPIO_MODE_ANALOG)             ||\
-                                     ((__MODE__) == GPIO_MODE_ANALOG_ADC_CONTROL))
-
-#define IS_GPIO_SPEED(__SPEED__)    (((__SPEED__) == GPIO_SPEED_FREQ_LOW)       ||\
-                                     ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM)    ||\
-                                     ((__SPEED__) == GPIO_SPEED_FREQ_HIGH)      ||\
-                                     ((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH))
-
-#define IS_GPIO_PULL(__PULL__)      (((__PULL__) == GPIO_NOPULL)   ||\
-                                     ((__PULL__) == GPIO_PULLUP)   || \
-                                     ((__PULL__) == GPIO_PULLDOWN))
-/**
-  * @}
-  */
-
-/* Include GPIO HAL Extended module */
-#include "stm32l4xx_hal_gpio_ex.h"
-
-/* Exported functions --------------------------------------------------------*/ 
-/** @addtogroup GPIO_Exported_Functions GPIO Exported Functions
-  * @{
-  */
-
-/** @addtogroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions 
- *  @brief    Initialization and Configuration functions
- * @{
- */
-     
-/* Initialization and de-initialization functions *****************************/
-void              HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init);
-void              HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);
-
-/**
-  * @}
-  */
-
-/** @addtogroup GPIO_Exported_Functions_Group2 IO operation functions 
- * @{
- */
-   
-/* IO operation functions *****************************************************/
-GPIO_PinState     HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void              HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
-void              HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void              HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
-void              HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */  
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L4xx_HAL_GPIO_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/inc/stm32l4xx_hal_gpio_ex.h b/stmhal/hal/l4/inc/stm32l4xx_hal_gpio_ex.h
deleted file mode 100644
index 223a7b5e59..0000000000
--- a/stmhal/hal/l4/inc/stm32l4xx_hal_gpio_ex.h
+++ /dev/null
@@ -1,245 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_gpio_ex.h
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   Header file of GPIO HAL Extended module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L4xx_HAL_GPIO_EX_H
-#define __STM32L4xx_HAL_GPIO_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup GPIOEx GPIOEx
-  * @brief GPIO Extended HAL module driver
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
-  * @{
-  */
-
-/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection
-  * @{
-  */
-
-#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
-/*--------------STM32L471xx/STM32L475xx/STM32L476xx/STM32L485xx/STM32L486xx----*/
-/**
-  * @brief   AF 0 selection
-  */
-#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
-#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
-#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
-#if defined(STM32L476xx) || defined(STM32L486xx)
-#define GPIO_AF0_LCDBIAS       ((uint8_t)0x00)  /* LCDBIAS Alternate Function mapping                        */
-#endif /* STM32L476xx || STM32L486xx */
-#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
-
-/**
-  * @brief   AF 1 selection
-  */
-#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
-#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
-#define GPIO_AF1_TIM5          ((uint8_t)0x01)  /* TIM5 Alternate Function mapping */
-#define GPIO_AF1_TIM8          ((uint8_t)0x01)  /* TIM8 Alternate Function mapping */
-#define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /* LPTIM1 Alternate Function mapping */
-#define GPIO_AF1_IR            ((uint8_t)0x01)  /* IR Alternate Function mapping */
-
-/**
-  * @brief   AF 2 selection
-  */
-#define GPIO_AF2_TIM1          ((uint8_t)0x02)  /* TIM1 Alternate Function mapping */
-#define GPIO_AF2_TIM2          ((uint8_t)0x02)  /* TIM2 Alternate Function mapping */
-#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
-
-/**
-  * @brief   AF 3 selection
-  */
-#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */
-#define GPIO_AF3_TIM1_COMP2    ((uint8_t)0x03)  /* TIM1/COMP2 Break in Alternate Function mapping  */
-#define GPIO_AF3_TIM1_COMP1    ((uint8_t)0x03)  /* TIM1/COMP1 Break in Alternate Function mapping  */
-
-/**
-  * @brief   AF 4 selection
-  */
-#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping   */
-#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping   */
-#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping   */
-
-/**
-  * @brief   AF 5 selection
-  */
-#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping   */
-#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2 Alternate Function mapping   */
-
-/**
-  * @brief   AF 6 selection
-  */
-#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3 Alternate Function mapping   */
-#define GPIO_AF6_DFSDM         ((uint8_t)0x06)  /* DFSDM Alternate Function mapping  */
-
-/**
-  * @brief   AF 7 selection
-  */
-#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
-#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
-#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */
-
-/**
-  * @brief   AF 8 selection
-  */
-#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping   */
-#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping   */
-#define GPIO_AF8_LPUART1       ((uint8_t)0x08)  /* LPUART1 Alternate Function mapping */
-
-
-/**
-  * @brief   AF 9 selection
-  */
-#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping  */
-#define GPIO_AF9_TSC           ((uint8_t)0x09)  /* TSC Alternate Function mapping   */
-
-/**
-  * @brief   AF 10 selection
-  */
-#if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
-#define GPIO_AF10_OTG_FS       ((uint8_t)0xA)  /* OTG_FS Alternate Function mapping */
-#endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
-#define GPIO_AF10_QUADSPI      ((uint8_t)0xA)  /* QUADSPI Alternate Function mapping */
-
-#if defined(STM32L476xx) || defined(STM32L486xx)
-/**
-  * @brief   AF 11 selection
-  */
-#define GPIO_AF11_LCD           ((uint8_t)0x0B)  /* LCD Alternate Function mapping */
-#endif /* STM32L476xx || STM32L486xx */
-
-/**
-  * @brief   AF 12 selection
-  */
-#define GPIO_AF12_FMC           ((uint8_t)0xC)  /* FMC Alternate Function mapping     */
-#define GPIO_AF12_SWPMI1        ((uint8_t)0xC)  /* SWPMI1 Alternate Function mapping  */
-#define GPIO_AF12_COMP1         ((uint8_t)0xC)  /* COMP1 Alternate Function mapping   */
-#define GPIO_AF12_COMP2         ((uint8_t)0xC)  /* COMP2 Alternate Function mapping   */
-#define GPIO_AF12_SDMMC1        ((uint8_t)0xC)  /* SDMMC1 Alternate Function mapping  */
-
-/**
-  * @brief   AF 13 selection
-  */
-#define GPIO_AF13_SAI1          ((uint8_t)0x0D)   /* SAI1 Alternate Function mapping */
-#define GPIO_AF13_SAI2          ((uint8_t)0x0D)   /* SAI2 Alternate Function mapping */
-#define GPIO_AF13_TIM8_COMP2    ((uint8_t)0x0D)   /* TIM8/COMP2 Break in Alternate Function mapping  */
-#define GPIO_AF13_TIM8_COMP1    ((uint8_t)0x0D)   /* TIM8/COMP1 Break in Alternate Function mapping  */
-
-/**
-  * @brief   AF 14 selection
-  */
-#define GPIO_AF14_TIM2          ((uint8_t)0x0E)   /* TIM2 Alternate Function mapping */
-#define GPIO_AF14_TIM15         ((uint8_t)0x0E)   /* TIM15 Alternate Function mapping */
-#define GPIO_AF14_TIM16         ((uint8_t)0x0E)   /* TIM16 Alternate Function mapping */
-#define GPIO_AF14_TIM17         ((uint8_t)0x0E)   /* TIM17 Alternate Function mapping */
-#define GPIO_AF14_LPTIM2        ((uint8_t)0x0E)   /* LPTIM2 Alternate Function mapping */
-#define GPIO_AF14_TIM8_COMP1    ((uint8_t)0x0E)   /* TIM8/COMP1 Break in Alternate Function mapping  */
-
-/**
-  * @brief   AF 15 selection
-  */
-#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
-
-#define IS_GPIO_AF(AF)   ((AF) <= (uint8_t)0x0F)
-
-#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros
-  * @{
-  */
-
-/** @defgroup GPIOEx_Get_Port_Index GPIOEx_Get Port Index
-* @{
-  */
-#define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0U :\
-                                      ((__GPIOx__) == (GPIOB))? 1U :\
-                                      ((__GPIOx__) == (GPIOC))? 2U :\
-                                      ((__GPIOx__) == (GPIOD))? 3U :\
-                                      ((__GPIOx__) == (GPIOE))? 4U :\
-                                      ((__GPIOx__) == (GPIOF))? 5U :\
-                                      ((__GPIOx__) == (GPIOG))? 6U : 7U)
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/ 
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L4xx_HAL_GPIO_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/inc/stm32l4xx_hal_i2c.h b/stmhal/hal/l4/inc/stm32l4xx_hal_i2c.h
deleted file mode 100644
index 2f179732e7..0000000000
--- a/stmhal/hal/l4/inc/stm32l4xx_hal_i2c.h
+++ /dev/null
@@ -1,665 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_i2c.h
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   Header file of I2C HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L4xx_HAL_I2C_H
-#define __STM32L4xx_HAL_I2C_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"  
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup I2C
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup I2C_Exported_Types I2C Exported Types
-  * @{
-  */
-
-/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
-  * @brief  I2C Configuration Structure definition  
-  * @{
-  */
-typedef struct
-{
-  uint32_t Timing;              /*!< Specifies the I2C_TIMINGR_register value.
-                                  This parameter calculated by referring to I2C initialization 
-                                         section in Reference manual */
-
-  uint32_t OwnAddress1;         /*!< Specifies the first device own address.
-                                  This parameter can be a 7-bit or 10-bit address. */
-
-  uint32_t AddressingMode;      /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
-                                  This parameter can be a value of @ref I2C_addressing_mode */
-
-  uint32_t DualAddressMode;     /*!< Specifies if dual addressing mode is selected.
-                                  This parameter can be a value of @ref I2C_dual_addressing_mode */
-
-  uint32_t OwnAddress2;         /*!< Specifies the second device own address if dual addressing mode is selected
-                                  This parameter can be a 7-bit address. */
-
-  uint32_t OwnAddress2Masks;    /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
-                                  This parameter can be a value of @ref I2C_own_address2_masks */
-
-  uint32_t GeneralCallMode;     /*!< Specifies if general call mode is selected.
-                                  This parameter can be a value of @ref I2C_general_call_addressing_mode */
-
-  uint32_t NoStretchMode;       /*!< Specifies if nostretch mode is selected.
-                                  This parameter can be a value of @ref I2C_nostretch_mode */
-
-}I2C_InitTypeDef;
-
-/** 
-  * @}
-  */
-
-/** @defgroup HAL_state_structure_definition HAL state structure definition
-  * @brief  HAL State structure definition
-  * @{
-  */ 
-
-typedef enum
-{
-  HAL_I2C_STATE_RESET             = 0x00,   /*!< Peripheral is not yet Initialized         */
-  HAL_I2C_STATE_READY             = 0x20,   /*!< Peripheral Initialized and ready for use  */
-  HAL_I2C_STATE_BUSY              = 0x24,   /*!< An internal process is ongoing            */
-  HAL_I2C_STATE_BUSY_TX           = 0x21,   /*!< Data Transmission process is ongoing      */ 
-  HAL_I2C_STATE_BUSY_RX           = 0x22,   /*!< Data Reception process is ongoing         */
-  HAL_I2C_STATE_LISTEN            = 0x28,   /*!< Address Listen Mode is ongoing            */
-  HAL_I2C_STATE_BUSY_TX_LISTEN    = 0x29,   /*!< Address Listen Mode and Data Transmission
-                                                 process is ongoing                        */
-  HAL_I2C_STATE_BUSY_RX_LISTEN    = 0x2A,   /*!< Address Listen Mode and Data Reception
-                                                 process is ongoing                        */
-  HAL_I2C_STATE_TIMEOUT           = 0xA0,   /*!< Timeout state                             */
-  HAL_I2C_STATE_ERROR             = 0xE0    /*!< Error                                     */ 
-
-}HAL_I2C_StateTypeDef;
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_mode_structure_definition HAL mode structure definition
-  * @brief  HAL Mode structure definition
-  * @{
-  */
-typedef enum
-{
-  HAL_I2C_MODE_NONE               = 0x00,   /*!< No I2C communication on going             */
-  HAL_I2C_MODE_MASTER             = 0x10,   /*!< I2C communication is in Master Mode       */
-  HAL_I2C_MODE_SLAVE              = 0x20,   /*!< I2C communication is in Slave Mode        */
-  HAL_I2C_MODE_MEM                = 0x40    /*!< I2C communication is in Memory Mode       */
-
-}HAL_I2C_ModeTypeDef;
-
-/** 
-  * @}
-  */
-
-/** @defgroup I2C_Error_Code_definition I2C Error Code definition
-  * @brief  I2C Error Code definition  
-  * @{
-  */
-#define HAL_I2C_ERROR_NONE      ((uint32_t)0x00000000)    /*!< No error              */
-#define HAL_I2C_ERROR_BERR      ((uint32_t)0x00000001)    /*!< BERR error            */
-#define HAL_I2C_ERROR_ARLO      ((uint32_t)0x00000002)    /*!< ARLO error            */
-#define HAL_I2C_ERROR_AF        ((uint32_t)0x00000004)    /*!< ACKF error            */
-#define HAL_I2C_ERROR_OVR       ((uint32_t)0x00000008)    /*!< OVR error             */
-#define HAL_I2C_ERROR_DMA       ((uint32_t)0x00000010)    /*!< DMA transfer error    */
-#define HAL_I2C_ERROR_TIMEOUT   ((uint32_t)0x00000020)    /*!< Timeout error         */
-#define HAL_I2C_ERROR_SIZE      ((uint32_t)0x00000040)    /*!< Size Management error */
-/** 
-  * @}
-  */
-
-/** @defgroup I2C_XferOptions_definition  I2C XferOptions definition
-  * @{
-  */
-#define I2C_NO_OPTION_FRAME             ((uint32_t)0xFFFF0000)
-#define I2C_FIRST_FRAME                 ((uint32_t)I2C_SOFTEND_MODE)
-#define I2C_NEXT_FRAME                  ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
-#define I2C_FIRST_AND_LAST_FRAME        ((uint32_t)I2C_AUTOEND_MODE)
-#define I2C_LAST_FRAME                  ((uint32_t)I2C_AUTOEND_MODE)
-/**
-  * @}
-  */
-
-/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
-  * @brief  I2C handle Structure definition  
-  * @{
-  */
-typedef struct
-{
-  I2C_TypeDef                *Instance;        /*!< I2C registers base address       */
-
-  I2C_InitTypeDef            Init;             /*!< I2C communication parameters     */
-
-  uint8_t                    *pBuffPtr;        /*!< Pointer to I2C transfer buffer   */
-
-  uint16_t                   XferSize;         /*!< I2C transfer size                */
-
-  __IO uint16_t              XferCount;        /*!< I2C transfer counter             */
-
-  __IO uint32_t              XferOptions;      /*!< I2C transfer options             */
-
-  __IO uint32_t              PreviousState;    /*!< I2C communication Previous state */
-
-  DMA_HandleTypeDef          *hdmatx;          /*!< I2C Tx DMA handle parameters     */
-
-  DMA_HandleTypeDef          *hdmarx;          /*!< I2C Rx DMA handle parameters     */
-
-  HAL_LockTypeDef            Lock;             /*!< I2C locking object               */
-
-  __IO HAL_I2C_StateTypeDef  State;            /*!< I2C communication state          */
-
-  __IO HAL_I2C_ModeTypeDef   Mode;             /*!< I2C communication mode           */
-
-  __IO uint32_t              ErrorCode;        /*!< I2C Error code                   */
-
-  __IO uint32_t              AddrEventCount;   /*!< I2C Address Event counter        */
-}I2C_HandleTypeDef;
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */  
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup I2C_Exported_Constants I2C Exported Constants
-  * @{
-  */
-
-/** @defgroup I2C_addressing_mode I2C addressing mode
-  * @{
-  */
-#define I2C_ADDRESSINGMODE_7BIT         ((uint32_t)0x00000001)
-#define I2C_ADDRESSINGMODE_10BIT        ((uint32_t)0x00000002)
-/**
-  * @}
-  */
-
-/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode
-  * @{
-  */
-#define I2C_DUALADDRESS_DISABLE         ((uint32_t)0x00000000)
-#define I2C_DUALADDRESS_ENABLE          I2C_OAR2_OA2EN
-/**
-  * @}
-  */
-
-/** @defgroup I2C_own_address2_masks I2C own address2 masks
-  * @{
-  */
-#define I2C_OA2_NOMASK                  ((uint8_t)0x00)
-#define I2C_OA2_MASK01                  ((uint8_t)0x01)
-#define I2C_OA2_MASK02                  ((uint8_t)0x02)
-#define I2C_OA2_MASK03                  ((uint8_t)0x03)
-#define I2C_OA2_MASK04                  ((uint8_t)0x04)
-#define I2C_OA2_MASK05                  ((uint8_t)0x05)
-#define I2C_OA2_MASK06                  ((uint8_t)0x06)
-#define I2C_OA2_MASK07                  ((uint8_t)0x07)
-/**
-  * @}
-  */
-
-/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
-  * @{
-  */
-#define I2C_GENERALCALL_DISABLE         ((uint32_t)0x00000000)
-#define I2C_GENERALCALL_ENABLE          I2C_CR1_GCEN
-/**
-  * @}
-  */
-
-/** @defgroup I2C_nostretch_mode I2C nostretch mode
-  * @{
-  */
-#define I2C_NOSTRETCH_DISABLE           ((uint32_t)0x00000000)
-#define I2C_NOSTRETCH_ENABLE            I2C_CR1_NOSTRETCH
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
-  * @{
-  */
-#define I2C_MEMADD_SIZE_8BIT            ((uint32_t)0x00000001)
-#define I2C_MEMADD_SIZE_16BIT           ((uint32_t)0x00000002)
-/**
-  * @}
-  */
-  
-/** @defgroup I2C_XferDirection_definition I2C XferDirection definition
-  * @{
-  */
-#define I2C_DIRECTION_TRANSMIT          ((uint32_t)0x00000000)
-#define I2C_DIRECTION_RECEIVE           ((uint32_t)0x00000001)
-/**
-  * @}
-  */
-
-/** @defgroup I2C_ReloadEndMode_definition I2C ReloadEndMode definition
-  * @{
-  */
-#define  I2C_RELOAD_MODE                I2C_CR2_RELOAD
-#define  I2C_AUTOEND_MODE               I2C_CR2_AUTOEND
-#define  I2C_SOFTEND_MODE               ((uint32_t)0x00000000)
-/**
-  * @}
-  */
-
-/** @defgroup I2C_StartStopMode_definition I2C StartStopMode definition
-  * @{
-  */
-#define  I2C_NO_STARTSTOP               ((uint32_t)0x00000000)
-#define  I2C_GENERATE_STOP              I2C_CR2_STOP
-#define  I2C_GENERATE_START_READ        (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
-#define  I2C_GENERATE_START_WRITE       I2C_CR2_START
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
-  * @brief I2C Interrupt definition
-  *        Elements values convention: 0xXXXXXXXX
-  *           - XXXXXXXX  : Interrupt control mask
-  * @{
-  */
-#define I2C_IT_ERRI                     I2C_CR1_ERRIE
-#define I2C_IT_TCI                      I2C_CR1_TCIE
-#define I2C_IT_STOPI                    I2C_CR1_STOPIE
-#define I2C_IT_NACKI                    I2C_CR1_NACKIE
-#define I2C_IT_ADDRI                    I2C_CR1_ADDRIE
-#define I2C_IT_RXI                      I2C_CR1_RXIE
-#define I2C_IT_TXI                      I2C_CR1_TXIE
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Flag_definition I2C Flag definition
-  * @{
-  */ 
-#define I2C_FLAG_TXE                    I2C_ISR_TXE
-#define I2C_FLAG_TXIS                   I2C_ISR_TXIS
-#define I2C_FLAG_RXNE                   I2C_ISR_RXNE
-#define I2C_FLAG_ADDR                   I2C_ISR_ADDR
-#define I2C_FLAG_AF                     I2C_ISR_NACKF
-#define I2C_FLAG_STOPF                  I2C_ISR_STOPF
-#define I2C_FLAG_TC                     I2C_ISR_TC
-#define I2C_FLAG_TCR                    I2C_ISR_TCR
-#define I2C_FLAG_BERR                   I2C_ISR_BERR
-#define I2C_FLAG_ARLO                   I2C_ISR_ARLO
-#define I2C_FLAG_OVR                    I2C_ISR_OVR
-#define I2C_FLAG_PECERR                 I2C_ISR_PECERR
-#define I2C_FLAG_TIMEOUT                I2C_ISR_TIMEOUT
-#define I2C_FLAG_ALERT                  I2C_ISR_ALERT
-#define I2C_FLAG_BUSY                   I2C_ISR_BUSY
-#define I2C_FLAG_DIR                    I2C_ISR_DIR
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-  
-/** @defgroup I2C_Exported_Macros I2C Exported Macros
-  * @{
-  */
-
-/** @brief Reset I2C handle state.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @retval None
-  */
-#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
-
-/** @brief  Enable the specified I2C interrupt.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @param  __INTERRUPT__ specifies the interrupt source to enable.
-  *        This parameter can be one of the following values:
-  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
-  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
-  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
-  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
-  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
-  *            @arg @ref I2C_IT_RXI   RX interrupt enable
-  *            @arg @ref I2C_IT_TXI   TX interrupt enable
-  *
-  * @retval None
-  */
-#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)          ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
-
-/** @brief  Disable the specified I2C interrupt.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @param  __INTERRUPT__ specifies the interrupt source to disable.
-  *        This parameter can be one of the following values:
-  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
-  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
-  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
-  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
-  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
-  *            @arg @ref I2C_IT_RXI   RX interrupt enable
-  *            @arg @ref I2C_IT_TXI   TX interrupt enable
-  *   
-  * @retval None
-  */
-#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
- 
-/** @brief  Check whether the specified I2C interrupt source is enabled or not.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @param  __INTERRUPT__ specifies the I2C interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
-  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
-  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
-  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
-  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
-  *            @arg @ref I2C_IT_RXI   RX interrupt enable
-  *            @arg @ref I2C_IT_TXI   TX interrupt enable
-  *
-  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
-  */
-#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)      ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief  Check whether the specified I2C flag is set or not.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @param  __FLAG__ specifies the flag to check.
-  *        This parameter can be one of the following values:
-  *            @arg @ref I2C_FLAG_TXE     Transmit data register empty
-  *            @arg @ref I2C_FLAG_TXIS    Transmit interrupt status
-  *            @arg @ref I2C_FLAG_RXNE    Receive data register not empty
-  *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)
-  *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag
-  *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
-  *            @arg @ref I2C_FLAG_TC      Transfer complete (master mode)
-  *            @arg @ref I2C_FLAG_TCR     Transfer complete reload
-  *            @arg @ref I2C_FLAG_BERR    Bus error
-  *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
-  *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun
-  *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
-  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
-  *            @arg @ref I2C_FLAG_ALERT   SMBus alert
-  *            @arg @ref I2C_FLAG_BUSY    Bus busy
-  *            @arg @ref I2C_FLAG_DIR     Transfer direction (slave mode)
-  *
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @param  __FLAG__ specifies the flag to clear.
-  *          This parameter can be any combination of the following values:
-  *            @arg @ref I2C_FLAG_TXE     Transmit data register empty
-  *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)
-  *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag
-  *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
-  *            @arg @ref I2C_FLAG_BERR    Bus error
-  *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
-  *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun            
-  *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
-  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag 
-  *            @arg @ref I2C_FLAG_ALERT   SMBus alert
-  *
-  * @retval None
-  */
-#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
-                                                                                 : ((__HANDLE__)->Instance->ICR = (__FLAG__)))
- 
-/** @brief  Enable the specified I2C peripheral.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @retval None
-  */
-#define __HAL_I2C_ENABLE(__HANDLE__)                            (SET_BIT((__HANDLE__)->Instance->CR1,  I2C_CR1_PE))
-
-/** @brief  Disable the specified I2C peripheral.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @retval None
-  */
-#define __HAL_I2C_DISABLE(__HANDLE__)                           (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
-
-/**
-  * @}
-  */
-
-/* Include I2C HAL Extended module */
-#include "stm32l4xx_hal_i2c_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2C_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-/* Initialization and de-initialization functions******************************/
-HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
-/**
-  * @}
-  */
-
-/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
-  * @{
-  */
-/* IO operation functions  ****************************************************/
- /******* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
-
- /******* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-
-HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
-
- /******* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-/**
-  * @}
-  */
-
-/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
- * @{
- */
-/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
-void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
-void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
-/**
-  * @}
-  */ 
-
-/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
-  * @{
-  */
-/* Peripheral State, Mode and Error functions  *********************************/
-HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
-HAL_I2C_ModeTypeDef  HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
-uint32_t             HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2C_Private_Constants I2C Private Constants
-  * @{
-  */
-
-/**
-  * @}
-  */ 
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2C_Private_Macro I2C Private Macros
-  * @{
-  */
-
-#define IS_I2C_ADDRESSING_MODE(MODE)    (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
-                                         ((MODE) == I2C_ADDRESSINGMODE_10BIT))
-
-#define IS_I2C_DUAL_ADDRESS(ADDRESS)    (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
-                                         ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
-
-#define IS_I2C_OWN_ADDRESS2_MASK(MASK)  (((MASK) == I2C_OA2_NOMASK)  || \
-                                         ((MASK) == I2C_OA2_MASK01) || \
-                                         ((MASK) == I2C_OA2_MASK02) || \
-                                         ((MASK) == I2C_OA2_MASK03) || \
-                                         ((MASK) == I2C_OA2_MASK04) || \
-                                         ((MASK) == I2C_OA2_MASK05) || \
-                                         ((MASK) == I2C_OA2_MASK06) || \
-                                         ((MASK) == I2C_OA2_MASK07))
-
-#define IS_I2C_GENERAL_CALL(CALL)       (((CALL) == I2C_GENERALCALL_DISABLE) || \
-                                         ((CALL) == I2C_GENERALCALL_ENABLE))
-
-#define IS_I2C_NO_STRETCH(STRETCH)      (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
-                                         ((STRETCH) == I2C_NOSTRETCH_ENABLE))
-
-#define IS_I2C_MEMADD_SIZE(SIZE)        (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
-                                         ((SIZE) == I2C_MEMADD_SIZE_16BIT))
-
-#define IS_TRANSFER_MODE(MODE)          (((MODE) == I2C_RELOAD_MODE)   || \
-                                         ((MODE) == I2C_AUTOEND_MODE) || \
-                                         ((MODE) == I2C_SOFTEND_MODE))
-
-#define IS_TRANSFER_REQUEST(REQUEST)    (((REQUEST) == I2C_GENERATE_STOP)        || \
-                                         ((REQUEST) == I2C_GENERATE_START_READ)  || \
-                                         ((REQUEST) == I2C_GENERATE_START_WRITE) || \
-                                         ((REQUEST) == I2C_NO_STARTSTOP))
-
-#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)  (((REQUEST) == I2C_FIRST_FRAME)          || \
-                                                   ((REQUEST) == I2C_NEXT_FRAME)           || \
-                                                   ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
-                                                   ((REQUEST) == I2C_LAST_FRAME))
-
-#define I2C_RESET_CR2(__HANDLE__)                 ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
-
-#define I2C_GET_ADDR_MATCH(__HANDLE__)            (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16)
-#define I2C_GET_DIR(__HANDLE__)                   (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16)
-#define I2C_GET_STOP_MODE(__HANDLE__)             ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
-#define I2C_GET_ISR_REG(__HANDLE__)               ((__HANDLE__)->Instance->ISR)
-#define I2C_CHECK_FLAG(__ISR__, __FLAG__)         (((__ISR__) & (__FLAG__)) == (__FLAG__))
-#define I2C_GET_OWN_ADDRESS1(__HANDLE__)          ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)
-#define I2C_GET_OWN_ADDRESS2(__HANDLE__)          ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)
-
-#define IS_I2C_OWN_ADDRESS1(ADDRESS1)             ((ADDRESS1) <= (uint32_t)0x000003FF)
-#define IS_I2C_OWN_ADDRESS2(ADDRESS2)             ((ADDRESS2) <= (uint16_t)0x00FF)
-
-#define I2C_MEM_ADD_MSB(__ADDRESS__)              ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))
-#define I2C_MEM_ADD_LSB(__ADDRESS__)              ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
-
-#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
-                                                          (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
-/**
-  * @}
-  */ 
-
-/* Private Functions ---------------------------------------------------------*/
-/** @defgroup I2C_Private_Functions I2C Private Functions
-  * @{
-  */
-/* Private functions are defined in stm32l4xx_hal_i2c.c file */
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32L4xx_HAL_I2C_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/inc/stm32l4xx_hal_i2c_ex.h b/stmhal/hal/l4/inc/stm32l4xx_hal_i2c_ex.h
deleted file mode 100644
index 683eb035de..0000000000
--- a/stmhal/hal/l4/inc/stm32l4xx_hal_i2c_ex.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_i2c_ex.h
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   Header file of I2C HAL Extended module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L4xx_HAL_I2C_EX_H
-#define __STM32L4xx_HAL_I2C_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup I2CEx
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
-  * @{
-  */
-
-/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
-  * @{
-  */
-#define I2C_ANALOGFILTER_ENABLE         ((uint32_t)0x00000000)
-#define I2C_ANALOGFILTER_DISABLE        I2C_CR1_ANFOFF
-/**
-  * @}
-  */
-
-/** @defgroup I2CEx_FastModePlus I2CEx FastModePlus
-  * @{
-  */
-#define I2C_FASTMODEPLUS_PB6            SYSCFG_CFGR1_I2C_PB6_FMP  /*!< Enable Fast Mode Plus on PB6       */
-#define I2C_FASTMODEPLUS_PB7            SYSCFG_CFGR1_I2C_PB7_FMP  /*!< Enable Fast Mode Plus on PB7       */
-#define I2C_FASTMODEPLUS_PB8            SYSCFG_CFGR1_I2C_PB8_FMP  /*!< Enable Fast Mode Plus on PB8       */
-#define I2C_FASTMODEPLUS_PB9            SYSCFG_CFGR1_I2C_PB9_FMP  /*!< Enable Fast Mode Plus on PB9       */
-#define I2C_FASTMODEPLUS_I2C1           SYSCFG_CFGR1_I2C1_FMP     /*!< Enable Fast Mode Plus on I2C1 pins */
-#define I2C_FASTMODEPLUS_I2C2           SYSCFG_CFGR1_I2C2_FMP     /*!< Enable Fast Mode Plus on I2C2 pins */
-#define I2C_FASTMODEPLUS_I2C3           SYSCFG_CFGR1_I2C3_FMP     /*!< Enable Fast Mode Plus on I2C3 pins */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
-  * @{
-  */
-
-/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions
-  * @brief    Extended features functions
-  * @{
-  */
-
-/* Peripheral Control functions  ************************************************/
-HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
-HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
-HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
-void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
-void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2C_Private_Constants I2C Private Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2C_Private_Macro I2C Private Macros
-  * @{
-  */
-#define IS_I2C_ANALOG_FILTER(FILTER)    (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
-                                          ((FILTER) == I2C_ANALOGFILTER_DISABLE))
-
-#define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000F)
-
-#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6)    || \
-                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7)   || \
-                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8)   || \
-                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9)   || \
-                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \
-                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \
-                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3))
-/**
-  * @}
-  */ 
-
-/* Private Functions ---------------------------------------------------------*/
-/** @defgroup I2C_Private_Functions I2C Private Functions
-  * @{
-  */
-/* Private functions are defined in stm32l4xx_hal_i2c_ex.c file */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L4xx_HAL_I2C_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/inc/stm32l4xx_hal_pcd.h b/stmhal/hal/l4/inc/stm32l4xx_hal_pcd.h
deleted file mode 100644
index 1083b29bf8..0000000000
--- a/stmhal/hal/l4/inc/stm32l4xx_hal_pcd.h
+++ /dev/null
@@ -1,312 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_pcd.h
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   Header file of PCD HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L4xx_HAL_PCD_H
-#define __STM32L4xx_HAL_PCD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_ll_usb.h"
-   
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup PCD
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup PCD_Exported_Types PCD Exported Types
-  * @{
-  */
-
-   /** 
-  * @brief  PCD State structure definition  
-  */  
-typedef enum 
-{
-  HAL_PCD_STATE_RESET   = 0x00,
-  HAL_PCD_STATE_READY   = 0x01,
-  HAL_PCD_STATE_ERROR   = 0x02,
-  HAL_PCD_STATE_BUSY    = 0x03,
-  HAL_PCD_STATE_TIMEOUT = 0x04
-} PCD_StateTypeDef;
-
-/* Device LPM suspend state */
-typedef enum  
-{
-  LPM_L0 = 0x00, /* on */
-  LPM_L1 = 0x01, /* LPM L1 sleep */
-  LPM_L2 = 0x02, /* suspend */
-  LPM_L3 = 0x03, /* off */
-}PCD_LPM_StateTypeDef;
-
-typedef USB_OTG_GlobalTypeDef  PCD_TypeDef;
-typedef USB_OTG_CfgTypeDef     PCD_InitTypeDef;
-typedef USB_OTG_EPTypeDef      PCD_EPTypeDef ;                          
-
-/** 
-  * @brief  PCD Handle Structure definition  
-  */ 
-typedef struct
-{
-  PCD_TypeDef             *Instance;   /*!< Register base address              */ 
-  PCD_InitTypeDef         Init;        /*!< PCD required parameters            */
-  PCD_EPTypeDef           IN_ep[15];    /*!< IN endpoint parameters             */
-  PCD_EPTypeDef           OUT_ep[15];   /*!< OUT endpoint parameters            */ 
-  HAL_LockTypeDef         Lock;        /*!< PCD peripheral status              */
-  __IO PCD_StateTypeDef   State;       /*!< PCD communication state            */
-  uint32_t                Setup[12];   /*!< Setup packet buffer                */
-  PCD_LPM_StateTypeDef    LPM_State;    /*!< LPM State                          */
-  uint32_t                BESL;
-  
-  
-  uint32_t lpm_active;                  /*!< Enable or disable the Link Power Management .                                  
-                                        This parameter can be set to ENABLE or DISABLE                      */
-
-  uint32_t battery_charging_active;     /*!< Enable or disable Battery charging.                                  
-                                        This parameter can be set to ENABLE or DISABLE                      */
-  void                    *pData;      /*!< Pointer to upper stack Handler     */    
-  
-} PCD_HandleTypeDef;
-
-/**
-  * @}
-  */
-  
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup PCD_Exported_Constants PCD Exported Constants
-  * @{
-  */
-
-/** @defgroup PCD_Speed PCD Speed
-  * @{
-  */
-#define PCD_SPEED_FULL               1
-/**
-  * @}
-  */
-  
-/** @defgroup PCD_PHY_Module PCD PHY Module
-  * @{
-  */
-#define PCD_PHY_EMBEDDED             1
-/**
-  * @}
-  */
-
-/** @defgroup PCD_Turnaround_Timeout Turnaround Timeout Value
-  * @{
-  */
-#ifndef USBD_FS_TRDT_VALUE
- #define USBD_FS_TRDT_VALUE           5
-#endif /* USBD_FS_TRDT_VALUE */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-  
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup PCD_Exported_Macros PCD Exported Macros
- *  @brief macros to handle interrupts and specific clock configurations
- * @{
- */
-#define __HAL_PCD_ENABLE(__HANDLE__)                       USB_EnableGlobalInt ((__HANDLE__)->Instance)
-#define __HAL_PCD_DISABLE(__HANDLE__)                      USB_DisableGlobalInt ((__HANDLE__)->Instance)
-   
-#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
-#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) &=  (__INTERRUPT__))
-#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
-
-
-#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__)             *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
-                                                          ~(USB_OTG_PCGCCTL_STOPCLK)
-
-#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__)               *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
-                                                      
-#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__)            ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10)
-                                                         
-#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE                ((uint32_t)0x08) 
-#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE               ((uint32_t)0x0C) 
-#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE        ((uint32_t)0x10) 
-
-#define USB_OTG_FS_WAKEUP_EXTI_LINE                       ((uint32_t)0x00020000)  /*!< External interrupt line 17 Connected to the USB FS EXTI Line */
-
-                                                      
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT()    EXTI->IMR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT()   EXTI->IMR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG()     EXTI->PR1 & (USB_OTG_FS_WAKEUP_EXTI_LINE)
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG()   EXTI->PR1 = USB_OTG_FS_WAKEUP_EXTI_LINE
-
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE()  do {\
-                                                             EXTI->FTSR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
-                                                             EXTI->RTSR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
-                                                           } while(0)
-
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() do {\
-                                                             EXTI->FTSR1 |= (USB_OTG_FS_WAKEUP_EXTI_LINE);\
-                                                             EXTI->RTSR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
-                                                           } while(0)
-
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() do {\
-                                                                   EXTI->RTSR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
-                                                                   EXTI->FTSR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
-                                                                   EXTI->RTSR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
-                                                                   EXTI->FTSR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
-                                                                  } while(0)                                                                   
-                                                         
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT()   (EXTI->SWIER1 |= USB_OTG_FS_WAKEUP_EXTI_LINE)                                                          
-
-/**
-  * @}
-  */
-
-/* Include PCD HAL Extended module */
-#include "stm32l4xx_hal_pcd_ex.h"
-
-/** @addtogroup PCD_Exported_Functions PCD Exported Functions
-  * @{
-  */
-
-/* Initialization/de-initialization functions  ********************************/
-/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd);
-void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
-/**
-  * @}
-  */
-
-/* I/O operation functions  ***************************************************/
-/* Non-Blocking mode: Interrupt */
-/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
-  * @{
-  */
- /* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
-
-void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
-/**
-  * @}
-  */
-
-/* Peripheral Control functions  **********************************************/
-/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
-  * @{
-  */
-HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
-HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
-HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
-HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
-uint16_t          HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
-/**
-  * @}
-  */
-
-/* Peripheral State functions  ************************************************/
-/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
-  * @{
-  */
-PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup PCD_Private_Macros PCD Private Macros
- * @{
- */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32L4xx_HAL_PCD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/inc/stm32l4xx_hal_pcd_ex.h b/stmhal/hal/l4/inc/stm32l4xx_hal_pcd_ex.h
deleted file mode 100644
index 8fe16d8209..0000000000
--- a/stmhal/hal/l4/inc/stm32l4xx_hal_pcd_ex.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_pcd_ex.h
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   Header file of PCD HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L4xx_HAL_PCD_EX_H
-#define __STM32L4xx_HAL_PCD_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-   
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup PCDEx
-  * @{
-  */
-/* Exported types ------------------------------------------------------------*/
-typedef enum  
-{
-  PCD_LPM_L0_ACTIVE = 0x00, /* on */
-  PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
-}PCD_LPM_MsgTypeDef;
-
-typedef enum  
-{
-  PCD_BCD_ERROR                     = 0xFF, 
-  PCD_BCD_CONTACT_DETECTION         = 0xFE,
-  PCD_BCD_STD_DOWNSTREAM_PORT       = 0xFD,
-  PCD_BCD_CHARGING_DOWNSTREAM_PORT  = 0xFC,
-  PCD_BCD_DEDICATED_CHARGING_PORT   = 0xFB,
-  PCD_BCD_DISCOVERY_COMPLETED       = 0x00,
-  
-}PCD_BCD_MsgTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-/* Exported macros -----------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
-  * @{
-  */
-/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
-  * @{
-  */
-HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
-HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
-HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);
-void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);
-void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
-void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32L4xx_HAL_PCD_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/inc/stm32l4xx_hal_pwr.h b/stmhal/hal/l4/inc/stm32l4xx_hal_pwr.h
deleted file mode 100644
index 4553bf74c9..0000000000
--- a/stmhal/hal/l4/inc/stm32l4xx_hal_pwr.h
+++ /dev/null
@@ -1,427 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_pwr.h
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   Header file of PWR HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L4xx_HAL_PWR_H
-#define __STM32L4xx_HAL_PWR_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup PWR
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/ 
-
-/** @defgroup PWR_Exported_Types PWR Exported Types
-  * @{
-  */
-
-/**
-  * @brief  PWR PVD configuration structure definition
-  */
-typedef struct
-{
-  uint32_t PVDLevel;   /*!< PVDLevel: Specifies the PVD detection level.
-                            This parameter can be a value of @ref PWR_PVD_detection_level. */
-
-  uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.
-                           This parameter can be a value of @ref PWR_PVD_Mode. */
-}PWR_PVDTypeDef;
-
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup PWR_Exported_Constants PWR Exported Constants
-  * @{
-  */
-
-
-/** @defgroup PWR_PVD_detection_level Programmable Voltage Detection levels
-  * @{
-  */
-#define PWR_PVDLEVEL_0                  PWR_CR2_PLS_LEV0  /*!< PVD threshold around 2.0 V */
-#define PWR_PVDLEVEL_1                  PWR_CR2_PLS_LEV1  /*!< PVD threshold around 2.2 V */
-#define PWR_PVDLEVEL_2                  PWR_CR2_PLS_LEV2  /*!< PVD threshold around 2.4 V */
-#define PWR_PVDLEVEL_3                  PWR_CR2_PLS_LEV3  /*!< PVD threshold around 2.5 V */
-#define PWR_PVDLEVEL_4                  PWR_CR2_PLS_LEV4  /*!< PVD threshold around 2.6 V */
-#define PWR_PVDLEVEL_5                  PWR_CR2_PLS_LEV5  /*!< PVD threshold around 2.8 V */
-#define PWR_PVDLEVEL_6                  PWR_CR2_PLS_LEV6  /*!< PVD threshold around 2.9 V */
-#define PWR_PVDLEVEL_7                  PWR_CR2_PLS_LEV7  /*!< External input analog voltage (compared internally to VREFINT) */
-/**
-  * @}
-  */
-
-/** @defgroup PWR_PVD_Mode  PWR PVD interrupt and event mode
-  * @{
-  */
-#define PWR_PVD_MODE_NORMAL                 ((uint32_t)0x00000000)   /*!< Basic mode is used */
-#define PWR_PVD_MODE_IT_RISING              ((uint32_t)0x00010001)   /*!< External Interrupt Mode with Rising edge trigger detection */
-#define PWR_PVD_MODE_IT_FALLING             ((uint32_t)0x00010002)   /*!< External Interrupt Mode with Falling edge trigger detection */
-#define PWR_PVD_MODE_IT_RISING_FALLING      ((uint32_t)0x00010003)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-#define PWR_PVD_MODE_EVENT_RISING           ((uint32_t)0x00020001)   /*!< Event Mode with Rising edge trigger detection */
-#define PWR_PVD_MODE_EVENT_FALLING          ((uint32_t)0x00020002)   /*!< Event Mode with Falling edge trigger detection */
-#define PWR_PVD_MODE_EVENT_RISING_FALLING   ((uint32_t)0x00020003)   /*!< Event Mode with Rising/Falling edge trigger detection */                               
-/**
-  * @}
-  */
-  
-  
-
-
-/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode  PWR regulator mode
-  * @{
-  */
-#define PWR_MAINREGULATOR_ON            ((uint32_t)0x00000000) /*!< Regulator in main mode      */
-#define PWR_LOWPOWERREGULATOR_ON        PWR_CR1_LPR            /*!< Regulator in low-power mode */
-/**
-  * @}
-  */
-
-/** @defgroup PWR_SLEEP_mode_entry  PWR SLEEP mode entry
-  * @{
-  */
-#define PWR_SLEEPENTRY_WFI              ((uint8_t)0x01)        /*!< Wait For Interruption instruction to enter Sleep mode */
-#define PWR_SLEEPENTRY_WFE              ((uint8_t)0x02)        /*!< Wait For Event instruction to enter Sleep mode        */
-/**
-  * @}
-  */
-
-/** @defgroup PWR_STOP_mode_entry  PWR STOP mode entry
-  * @{
-  */
-#define PWR_STOPENTRY_WFI               ((uint8_t)0x01)       /*!< Wait For Interruption instruction to enter Stop mode */
-#define PWR_STOPENTRY_WFE               ((uint8_t)0x02)       /*!< Wait For Event instruction to enter Stop mode        */
-/**
-  * @}
-  */
-  
-
-/** @defgroup PWR_PVD_EXTI_LINE  PWR PVD external interrupt line
-  * @{
-  */
-#define PWR_EXTI_LINE_PVD  ((uint32_t)0x00010000)   /*!< External interrupt line 16 Connected to the PVD EXTI Line */
-/**
-  * @}
-  */
-
-/** @defgroup PWR_PVD_EVENT_LINE  PWR PVD event line
-  * @{
-  */  
-#define PWR_EVENT_LINE_PVD  ((uint32_t)0x00010000)  /*!< Event line 16 Connected to the PVD Event Line */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup PWR_Exported_Macros  PWR Exported Macros
-  * @{
-  */
-
-/** @brief  Check whether or not a specific PWR flag is set.
-  * @param  __FLAG__: specifies the flag to check.
-  *           This parameter can be one of the following values:
-  *            @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event
-  *                  was received from the WKUP pin 1.
-  *            @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event
-  *                  was received from the WKUP pin 2.
-  *            @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event
-  *                  was received from the WKUP pin 3.
-  *            @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event
-  *                  was received from the WKUP pin 4.
-  *            @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event
-  *                  was received from the WKUP pin 5.          
-  *            @arg @ref PWR_FLAG_SB StandBy Flag. Indicates that the system
-  *                  entered StandBy mode.
-  *            @arg @ref PWR_FLAG_WUFI Wake-Up Flag Internal. Set when a wakeup is detected on
-  *                 the internal wakeup line.
-  *            @arg @ref PWR_FLAG_REGLPS Low Power Regulator Started. Indicates whether or not the 
-  *                 low-power regulator is ready.
-  *            @arg @ref PWR_FLAG_REGLPF Low Power Regulator Flag. Indicates whether the 
-  *                 regulator is ready in main mode or is in low-power mode. 
-  *            @arg @ref PWR_FLAG_VOSF Voltage Scaling Flag. Indicates whether the regulator is ready 
-  *                 in the selected voltage range or is still changing to the required voltage level.
-  *            @arg @ref PWR_FLAG_PVDO Power Voltage Detector Output. Indicates whether VDD voltage is
-  *                  below or above the selected PVD threshold.
-  *            @arg @ref PWR_FLAG_PVMO1 Peripheral Voltage Monitoring Output 1. Indicates whether VDDUSB voltage is
-  *                  is below or above PVM1 threshold (applicable when USB feature is supported).
-  *            @arg @ref PWR_FLAG_PVMO2 Peripheral Voltage Monitoring Output 2. Indicates whether VDDIO2 voltage is
-  *                  is below or above PVM2 threshold (applicable when VDDIO2 is present on device). 
-  *            @arg @ref PWR_FLAG_PVMO3 Peripheral Voltage Monitoring Output 3. Indicates whether VDDA voltage is
-  *                  is below or above PVM3 threshold. 
-  *            @arg @ref PWR_FLAG_PVMO4 Peripheral Voltage Monitoring Output 4. Indicates whether VDDA voltage is
-  *                  is below or above PVM4 threshold.                           
-  *    
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_PWR_GET_FLAG(__FLAG__)  ( ((((uint8_t)(__FLAG__)) >> 5U) == 1)  ?\
-                                      (PWR->SR1 & (1U << ((__FLAG__) & 31U))) :\
-                                      (PWR->SR2 & (1U << ((__FLAG__) & 31U))) )
-
-/** @brief  Clear a specific PWR flag.
-  * @param  __FLAG__: specifies the flag to clear.
-  *          This parameter can be one of the following values:
-  *            @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event
-  *                  was received from the WKUP pin 1.
-  *            @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event
-  *                  was received from the WKUP pin 2.
-  *            @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event
-  *                  was received from the WKUP pin 3.
-  *            @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event
-  *                  was received from the WKUP pin 4.
-  *            @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event
-  *                  was received from the WKUP pin 5.
-  *            @arg @ref PWR_FLAG_WU Encompasses all five Wake Up Flags.
-  *            @arg @ref PWR_FLAG_SB Standby Flag. Indicates that the system
-  *                  entered Standby mode.
-  * @retval None   
-  */
-#define __HAL_PWR_CLEAR_FLAG(__FLAG__)   ( (((uint8_t)(__FLAG__)) == PWR_FLAG_WU) ?\
-                                         (PWR->SCR  = (__FLAG__)) :\
-                                         (PWR->SCR = (1U << ((__FLAG__) & 31U))) )
-/**
-  * @brief Enable the PVD Extended Interrupt Line.
-  * @retval None
-  */
-#define __HAL_PWR_PVD_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
-
-/**
-  * @brief Disable the PVD Extended Interrupt Line.
-  * @retval None
-  */
-#define __HAL_PWR_PVD_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
-
-/**
-  * @brief Enable the PVD Event Line.
-  * @retval None
-  */
-#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
-
-/**
-  * @brief Disable the PVD Event Line.
-  * @retval None
-  */
-#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
-
-/**
-  * @brief Enable the PVD Extended Interrupt Rising Trigger.
-  * @retval None
-  */
-#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
-
-/**
-  * @brief Disable the PVD Extended Interrupt Rising Trigger.
-  * @retval None
-  */
-#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
-
-/**
-  * @brief Enable the PVD Extended Interrupt Falling Trigger.
-  * @retval None
-  */
-#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
-
-
-/**
-  * @brief Disable the PVD Extended Interrupt Falling Trigger.
-  * @retval None
-  */
-#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
-
-
-/**
-  * @brief  Enable the PVD Extended Interrupt Rising & Falling Trigger.
-  * @retval None
-  */
-#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()  \
-  do {                                                   \
-    __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();             \
-    __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();            \
-  } while(0)
-
-/**
-  * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
-  * @retval None
-  */
-#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()  \
-  do {                                                    \
-    __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();             \
-    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();            \
-  } while(0)
-
-/**
-  * @brief  Generate a Software interrupt on selected EXTI line.
-  * @retval None
-  */
-#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
-
-/**
-  * @brief Check whether or not the PVD EXTI interrupt flag is set.
-  * @retval EXTI PVD Line Status.
-  */
-#define __HAL_PWR_PVD_EXTI_GET_FLAG()  (EXTI->PR1 & PWR_EXTI_LINE_PVD)
-
-/**
-  * @brief Clear the PVD EXTI interrupt flag.
-  * @retval None
-  */
-#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR1, PWR_EXTI_LINE_PVD)
-
-/**
-  * @}
-  */
-  
-
-/* Private macros --------------------------------------------------------*/
-/** @addtogroup  PWR_Private_Macros   PWR Private Macros
-  * @{
-  */
-
-#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
-                                 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
-                                 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
-                                 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
-                                 
-#define IS_PWR_PVD_MODE(MODE)  (((MODE) == PWR_PVD_MODE_NORMAL)              ||\
-                                ((MODE) == PWR_PVD_MODE_IT_RISING)           ||\
-                                ((MODE) == PWR_PVD_MODE_IT_FALLING)          ||\
-                                ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING)   ||\
-                                ((MODE) == PWR_PVD_MODE_EVENT_RISING)        ||\
-                                ((MODE) == PWR_PVD_MODE_EVENT_FALLING)       ||\
-                                ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING)) 
-                                
-#define IS_PWR_REGULATOR(REGULATOR)      (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
-                                          ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
-                                          
-#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
-
-#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) )
-                                      
-/**
-  * @}
-  */  
-
-/* Include PWR HAL Extended module */
-#include "stm32l4xx_hal_pwr_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup PWR_Exported_Functions PWR Exported Functions
-  * @{
-  */
-  
-/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 
-  * @{
-  */
-  
-/* Initialization and de-initialization functions *******************************/
-void HAL_PWR_DeInit(void);
-void HAL_PWR_EnableBkUpAccess(void);
-void HAL_PWR_DisableBkUpAccess(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions 
-  * @{
-  */
-
-/* Peripheral Control functions  ************************************************/
-HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
-void HAL_PWR_EnablePVD(void);
-void HAL_PWR_DisablePVD(void);
-
-
-/* WakeUp pins configuration functions ****************************************/
-void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
-void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
-
-/* Low Power modes configuration functions ************************************/
-void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
-void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
-void HAL_PWR_EnterSTANDBYMode(void);
-
-void HAL_PWR_EnableSleepOnExit(void);
-void HAL_PWR_DisableSleepOnExit(void);
-void HAL_PWR_EnableSEVOnPend(void);
-void HAL_PWR_DisableSEVOnPend(void);
-
-void HAL_PWR_PVDCallback(void);
-
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */  
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32L4xx_HAL_PWR_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/inc/stm32l4xx_hal_pwr_ex.h b/stmhal/hal/l4/inc/stm32l4xx_hal_pwr_ex.h
deleted file mode 100644
index 97236f74a4..0000000000
--- a/stmhal/hal/l4/inc/stm32l4xx_hal_pwr_ex.h
+++ /dev/null
@@ -1,825 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_pwr_ex.h
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   Header file of PWR HAL Extended module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L4xx_HAL_PWR_EX_H
-#define __STM32L4xx_HAL_PWR_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup PWREx
-  * @{
-  */
-
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup PWREx_Exported_Types PWR Extended Exported Types
-  * @{
-  */
-
-
-/**
-  * @brief  PWR PVM configuration structure definition
-  */
-typedef struct
-{
-  uint32_t PVMType;   /*!< PVMType: Specifies which voltage is monitored and against which threshold. 
-                           This parameter can be a value of @ref PWREx_PVM_Type. 
-                           @arg @ref PWR_PVM_1 Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported). 
-                           @arg @ref PWR_PVM_2 Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device). 
-                           @arg @ref PWR_PVM_3 Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V. 
-                           @arg @ref PWR_PVM_4 Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V. */
-
-  uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.
-                           This parameter can be a value of @ref PWREx_PVM_Mode. */
-}PWR_PVMTypeDef;
-
-/**
-  * @}
-  */ 
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup PWREx_Exported_Constants  PWR Extended Exported Constants
-  * @{
-  */
-
-/** @defgroup PWREx_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants
-  * @{
-  */
-#define PWR_WUP_POLARITY_SHIFT                  0x05   /*!< Internal constant used to retrieve wakeup pin polariry */
-/**
-  * @}
-  */  
-
-
-/** @defgroup PWREx_WakeUp_Pins  PWR wake-up pins
-  * @{
-  */                                                      
-#define PWR_WAKEUP_PIN1                 PWR_CR3_EWUP1  /*!< Wakeup pin 1 (with high level polarity) */
-#define PWR_WAKEUP_PIN2                 PWR_CR3_EWUP2  /*!< Wakeup pin 2 (with high level polarity) */
-#define PWR_WAKEUP_PIN3                 PWR_CR3_EWUP3  /*!< Wakeup pin 3 (with high level polarity) */
-#define PWR_WAKEUP_PIN4                 PWR_CR3_EWUP4  /*!< Wakeup pin 4 (with high level polarity) */
-#define PWR_WAKEUP_PIN5                 PWR_CR3_EWUP5  /*!< Wakeup pin 5 (with high level polarity) */
-#define PWR_WAKEUP_PIN1_HIGH            PWR_CR3_EWUP1  /*!< Wakeup pin 1 (with high level polarity) */
-#define PWR_WAKEUP_PIN2_HIGH            PWR_CR3_EWUP2  /*!< Wakeup pin 2 (with high level polarity) */
-#define PWR_WAKEUP_PIN3_HIGH            PWR_CR3_EWUP3  /*!< Wakeup pin 3 (with high level polarity) */
-#define PWR_WAKEUP_PIN4_HIGH            PWR_CR3_EWUP4  /*!< Wakeup pin 4 (with high level polarity) */
-#define PWR_WAKEUP_PIN5_HIGH            PWR_CR3_EWUP5  /*!< Wakeup pin 5 (with high level polarity) */
-#define PWR_WAKEUP_PIN1_LOW             (uint32_t)((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level polarity) */
-#define PWR_WAKEUP_PIN2_LOW             (uint32_t)((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level polarity) */
-#define PWR_WAKEUP_PIN3_LOW             (uint32_t)((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level polarity) */
-#define PWR_WAKEUP_PIN4_LOW             (uint32_t)((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level polarity) */
-#define PWR_WAKEUP_PIN5_LOW             (uint32_t)((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level polarity) */
-/**
-  * @}
-  */
-
-/** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type
-  * @{
-  */
-#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
-#define PWR_PVM_1                  PWR_CR2_PVME1  /*!< Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported) */
-#endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
-#define PWR_PVM_2                  PWR_CR2_PVME2  /*!< Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device) */
-#define PWR_PVM_3                  PWR_CR2_PVME3  /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V */
-#define PWR_PVM_4                  PWR_CR2_PVME4  /*!< Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V  */
-/**
-  * @}
-  */  
-  
-/** @defgroup PWREx_PVM_Mode  PWR PVM interrupt and event mode
-  * @{
-  */
-#define PWR_PVM_MODE_NORMAL                 ((uint32_t)0x00000000)   /*!< basic mode is used */
-#define PWR_PVM_MODE_IT_RISING              ((uint32_t)0x00010001)   /*!< External Interrupt Mode with Rising edge trigger detection */
-#define PWR_PVM_MODE_IT_FALLING             ((uint32_t)0x00010002)   /*!< External Interrupt Mode with Falling edge trigger detection */
-#define PWR_PVM_MODE_IT_RISING_FALLING      ((uint32_t)0x00010003)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-#define PWR_PVM_MODE_EVENT_RISING           ((uint32_t)0x00020001)   /*!< Event Mode with Rising edge trigger detection */
-#define PWR_PVM_MODE_EVENT_FALLING          ((uint32_t)0x00020002)   /*!< Event Mode with Falling edge trigger detection */
-#define PWR_PVM_MODE_EVENT_RISING_FALLING   ((uint32_t)0x00020003)   /*!< Event Mode with Rising/Falling edge trigger detection */
-/**
-  * @}
-  */
-  
-  
-
-/** @defgroup PWREx_Regulator_Voltage_Scale  PWR Regulator voltage scale
-  * @{
-  */
-#define PWR_REGULATOR_VOLTAGE_SCALE1       PWR_CR1_VOS_0     /*!< Voltage scaling range 1 */
-#define PWR_REGULATOR_VOLTAGE_SCALE2       PWR_CR1_VOS_1     /*!< Voltage scaling range 2 */
-/**
-  * @}
-  */
-
-  
-/** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection
-  * @{
-  */
-#define PWR_BATTERY_CHARGING_RESISTOR_5          ((uint32_t)0x00000000) /*!< VBAT charging through a 5 kOhms resistor   */
-#define PWR_BATTERY_CHARGING_RESISTOR_1_5         PWR_CR4_VBRS          /*!< VBAT charging through a 1.5 kOhms resistor */
-/**
-  * @}
-  */
-  
-/** @defgroup PWREx_VBAT_Battery_Charging PWR battery charging
-  * @{
-  */
-#define PWR_BATTERY_CHARGING_DISABLE        ((uint32_t)0x00000000)
-#define PWR_BATTERY_CHARGING_ENABLE         PWR_CR4_VBE
-/**
-  * @}
-  */ 
-  
-/** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in standby/shutdown mode
-  * @{
-  */
-#define PWR_GPIO_BIT_0   PWR_PUCRA_PA0    /*!< GPIO port I/O pin 0  */
-#define PWR_GPIO_BIT_1   PWR_PUCRA_PA1    /*!< GPIO port I/O pin 1  */
-#define PWR_GPIO_BIT_2   PWR_PUCRA_PA2    /*!< GPIO port I/O pin 2  */
-#define PWR_GPIO_BIT_3   PWR_PUCRA_PA3    /*!< GPIO port I/O pin 3  */
-#define PWR_GPIO_BIT_4   PWR_PUCRA_PA4    /*!< GPIO port I/O pin 4  */
-#define PWR_GPIO_BIT_5   PWR_PUCRA_PA5    /*!< GPIO port I/O pin 5  */
-#define PWR_GPIO_BIT_6   PWR_PUCRA_PA6    /*!< GPIO port I/O pin 6  */
-#define PWR_GPIO_BIT_7   PWR_PUCRA_PA7    /*!< GPIO port I/O pin 7  */
-#define PWR_GPIO_BIT_8   PWR_PUCRA_PA8    /*!< GPIO port I/O pin 8  */
-#define PWR_GPIO_BIT_9   PWR_PUCRA_PA9    /*!< GPIO port I/O pin 9  */
-#define PWR_GPIO_BIT_10  PWR_PUCRA_PA10   /*!< GPIO port I/O pin 10 */
-#define PWR_GPIO_BIT_11  PWR_PUCRA_PA11   /*!< GPIO port I/O pin 11 */
-#define PWR_GPIO_BIT_12  PWR_PUCRA_PA12   /*!< GPIO port I/O pin 12 */
-#define PWR_GPIO_BIT_13  PWR_PUCRA_PA13   /*!< GPIO port I/O pin 13 */
-#define PWR_GPIO_BIT_14  PWR_PDCRA_PA14   /*!< GPIO port I/O pin 14 */
-#define PWR_GPIO_BIT_15  PWR_PUCRA_PA15   /*!< GPIO port I/O pin 15 */
-/**
-  * @}
-  */ 
-  
-/** @defgroup PWREx_GPIO GPIO port
-  * @{
-  */
-#define PWR_GPIO_A   0x00000000      /*!< GPIO port A */
-#define PWR_GPIO_B   0x00000001      /*!< GPIO port B */
-#define PWR_GPIO_C   0x00000002      /*!< GPIO port C */
-#define PWR_GPIO_D   0x00000003      /*!< GPIO port D */
-#define PWR_GPIO_E   0x00000004      /*!< GPIO port E */
-#define PWR_GPIO_F   0x00000005      /*!< GPIO port F */
-#define PWR_GPIO_G   0x00000006      /*!< GPIO port G */
-#define PWR_GPIO_H   0x00000007      /*!< GPIO port H */
-/**
-  * @}
-  */ 
-  
-/** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines
-  * @{
-  */    
-#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
-#define PWR_EXTI_LINE_PVM1  ((uint32_t)0x00000008)  /*!< External interrupt line 35 Connected to the PVM1 EXTI Line   */
-#endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
-#define PWR_EXTI_LINE_PVM2  ((uint32_t)0x00000010)  /*!< External interrupt line 36 Connected to the PVM2 EXTI Line   */
-#define PWR_EXTI_LINE_PVM3  ((uint32_t)0x00000020)  /*!< External interrupt line 37 Connected to the PVM3 EXTI Line   */
-#define PWR_EXTI_LINE_PVM4  ((uint32_t)0x00000040)  /*!< External interrupt line 38 Connected to the PVM4 EXTI Line   */ 
-/**
-  * @}
-  */ 
-  
-/** @defgroup PWREx_PVM_EVENT_LINE PWR PVM event lines
-  * @{
-  */    
-#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
-#define PWR_EVENT_LINE_PVM1 ((uint32_t)0x00000008)  /*!< Event line 35 Connected to the PVM1 EXTI Line */
-#endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
-#define PWR_EVENT_LINE_PVM2 ((uint32_t)0x00000010)  /*!< Event line 36 Connected to the PVM2 EXTI Line */
-#define PWR_EVENT_LINE_PVM3 ((uint32_t)0x00000020)  /*!< Event line 37 Connected to the PVM3 EXTI Line */
-#define PWR_EVENT_LINE_PVM4 ((uint32_t)0x00000040)  /*!< Event line 38 Connected to the PVM4 EXTI Line */ 
-/**
-  * @}
-  */ 
-  
-/** @defgroup PWREx_Flag  PWR Status Flags
-  *        Elements values convention: 0000 0000 0XXY YYYYb
-  *           - Y YYYY  : Flag position in the XX register (5 bits)
-  *           - XX  : Status register (2 bits)
-  *                 - 01: SR1 register
-  *                 - 10: SR2 register
-  *        The only exception is PWR_FLAG_WU, encompassing all
-  *        wake-up flags and set to PWR_SR1_WUF.    
-  * @{   
-  */  
-#define PWR_FLAG_WUF1                       ((uint32_t)0x0020)   /*!< Wakeup event on wakeup pin 1 */
-#define PWR_FLAG_WUF2                       ((uint32_t)0x0021)   /*!< Wakeup event on wakeup pin 2 */
-#define PWR_FLAG_WUF3                       ((uint32_t)0x0022)   /*!< Wakeup event on wakeup pin 3 */
-#define PWR_FLAG_WUF4                       ((uint32_t)0x0023)   /*!< Wakeup event on wakeup pin 4 */
-#define PWR_FLAG_WUF5                       ((uint32_t)0x0024)   /*!< Wakeup event on wakeup pin 5 */
-#define PWR_FLAG_WU                         PWR_SR1_WUF          /*!< Encompass wakeup event on all wakeup pins */
-#define PWR_FLAG_SB                         ((uint32_t)0x0028)   /*!< Standby flag */
-#define PWR_FLAG_WUFI                       ((uint32_t)0x002F)   /*!< Wakeup on internal wakeup line */
-
-#define PWR_FLAG_REGLPS                     ((uint32_t)0x0048)   /*!< Low-power regulator start flag */
-#define PWR_FLAG_REGLPF                     ((uint32_t)0x0049)   /*!< Low-power regulator flag */
-#define PWR_FLAG_VOSF                       ((uint32_t)0x004A)   /*!< Voltage scaling flag */
-#define PWR_FLAG_PVDO                       ((uint32_t)0x004B)   /*!< Power Voltage Detector output flag */
-#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
-#define PWR_FLAG_PVMO1                      ((uint32_t)0x004C)   /*!< Power Voltage Monitoring 1 output flag */
-#endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
-#define PWR_FLAG_PVMO2                      ((uint32_t)0x004D)   /*!< Power Voltage Monitoring 2 output flag */
-#define PWR_FLAG_PVMO3                      ((uint32_t)0x004E)   /*!< Power Voltage Monitoring 3 output flag */
-#define PWR_FLAG_PVMO4                      ((uint32_t)0x004F)   /*!< Power Voltage Monitoring 4 output flag */
-/**
-  * @}
-  */        
-
-/**
-  * @}
-  */  
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros
- * @{
- */
-
-#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
-/**
-  * @brief Enable the PVM1 Extended Interrupt Line.
-  * @retval None
-  */
-#define __HAL_PWR_PVM1_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
-
-/**
-  * @brief Disable the PVM1 Extended Interrupt Line.
-  * @retval None
-  */
-#define __HAL_PWR_PVM1_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
-
-/**
-  * @brief Enable the PVM1 Event Line.
-  * @retval None
-  */
-#define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
-
-/**
-  * @brief Disable the PVM1 Event Line.
-  * @retval None
-  */
-#define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
-
-/**
-  * @brief Enable the PVM1 Extended Interrupt Rising Trigger.
-  * @retval None
-  */
-#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
-
-/**
-  * @brief Disable the PVM1 Extended Interrupt Rising Trigger.
-  * @retval None
-  */
-#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
-
-/**
-  * @brief Enable the PVM1 Extended Interrupt Falling Trigger.
-  * @retval None
-  */
-#define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
-
-
-/**
-  * @brief Disable the PVM1 Extended Interrupt Falling Trigger.
-  * @retval None
-  */
-#define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
-
-
-/**
-  * @brief  PVM1 EXTI line configuration: set rising & falling edge trigger.
-  * @retval None
-  */
-#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE()  \
-  do {                                                    \
-    __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE();             \
-    __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE();            \
-  } while(0)
-
-/**
-  * @brief Disable the PVM1 Extended Interrupt Rising & Falling Trigger.
-  * @retval None
-  */
-#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE()  \
-  do {                                                     \
-    __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE();             \
-    __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE();            \
-  } while(0)
-
-/**
-  * @brief  Generate a Software interrupt on selected EXTI line.
-  * @retval None
-  */
-#define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1)
-
-/**
-  * @brief Check whether the specified PVM1 EXTI interrupt flag is set or not.
-  * @retval EXTI PVM1 Line Status.
-  */
-#define __HAL_PWR_PVM1_EXTI_GET_FLAG()  (EXTI->PR2 & PWR_EXTI_LINE_PVM1)
-
-/**
-  * @brief Clear the PVM1 EXTI flag.
-  * @retval None
-  */
-#define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM1)
-
-#endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
-
-
-/**
-  * @brief Enable the PVM2 Extended Interrupt Line.
-  * @retval None
-  */
-#define __HAL_PWR_PVM2_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
-
-/**
-  * @brief Disable the PVM2 Extended Interrupt Line.
-  * @retval None
-  */
-#define __HAL_PWR_PVM2_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
-
-/**
-  * @brief Enable the PVM2 Event Line.
-  * @retval None
-  */
-#define __HAL_PWR_PVM2_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
-
-/**
-  * @brief Disable the PVM2 Event Line.
-  * @retval None
-  */
-#define __HAL_PWR_PVM2_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
-
-/**
-  * @brief Enable the PVM2 Extended Interrupt Rising Trigger.
-  * @retval None
-  */
-#define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
-
-/**
-  * @brief Disable the PVM2 Extended Interrupt Rising Trigger.
-  * @retval None
-  */
-#define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
-
-/**
-  * @brief Enable the PVM2 Extended Interrupt Falling Trigger.
-  * @retval None
-  */
-#define __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
-
-
-/**
-  * @brief Disable the PVM2 Extended Interrupt Falling Trigger.
-  * @retval None
-  */
-#define __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
-
-
-/**
-  * @brief  PVM2 EXTI line configuration: set rising & falling edge trigger.
-  * @retval None
-  */
-#define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE()  \
-  do {                                                    \
-    __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE();             \
-    __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE();            \
-  } while(0)
-  
-/**
-  * @brief Disable the PVM2 Extended Interrupt Rising & Falling Trigger.
-  * @retval None
-  */
-#define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE()  \
-  do {                                                     \
-    __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE();             \
-    __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE();            \
-  } while(0)
-
-/**
-  * @brief  Generate a Software interrupt on selected EXTI line.
-  * @retval None
-  */
-#define __HAL_PWR_PVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2)
-
-/**
-  * @brief Check whether the specified PVM2 EXTI interrupt flag is set or not.
-  * @retval EXTI PVM2 Line Status.
-  */
-#define __HAL_PWR_PVM2_EXTI_GET_FLAG()  (EXTI->PR2 & PWR_EXTI_LINE_PVM2)
-
-/**
-  * @brief Clear the PVM2 EXTI flag.
-  * @retval None
-  */
-#define __HAL_PWR_PVM2_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM2)
-
-
-
-/**
-  * @brief Enable the PVM3 Extended Interrupt Line.
-  * @retval None
-  */
-#define __HAL_PWR_PVM3_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
-
-/**
-  * @brief Disable the PVM3 Extended Interrupt Line.
-  * @retval None
-  */
-#define __HAL_PWR_PVM3_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
-
-/**
-  * @brief Enable the PVM3 Event Line.
-  * @retval None
-  */
-#define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
-
-/**
-  * @brief Disable the PVM3 Event Line.
-  * @retval None
-  */
-#define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
-
-/**
-  * @brief Enable the PVM3 Extended Interrupt Rising Trigger.
-  * @retval None
-  */
-#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
-
-/**
-  * @brief Disable the PVM3 Extended Interrupt Rising Trigger.
-  * @retval None
-  */
-#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
-
-/**
-  * @brief Enable the PVM3 Extended Interrupt Falling Trigger.
-  * @retval None
-  */
-#define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
-
-
-/**
-  * @brief Disable the PVM3 Extended Interrupt Falling Trigger.
-  * @retval None
-  */
-#define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
-
-
-/**
-  * @brief  PVM3 EXTI line configuration: set rising & falling edge trigger.
-  * @retval None
-  */
-#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE()  \
-  do {                                                    \
-    __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE();             \
-    __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE();            \
-  } while(0)
-  
-/**
-  * @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger.
-  * @retval None
-  */
-#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE()  \
-  do {                                                     \
-    __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE();             \
-    __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE();            \
-  } while(0)
-
-/**
-  * @brief  Generate a Software interrupt on selected EXTI line.
-  * @retval None
-  */
-#define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM3)
-
-/**
-  * @brief Check whether the specified PVM3 EXTI interrupt flag is set or not.
-  * @retval EXTI PVM3 Line Status.
-  */
-#define __HAL_PWR_PVM3_EXTI_GET_FLAG()  (EXTI->PR2 & PWR_EXTI_LINE_PVM3)
-
-/**
-  * @brief Clear the PVM3 EXTI flag.
-  * @retval None
-  */
-#define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM3)
-
-
-
-
-/**
-  * @brief Enable the PVM4 Extended Interrupt Line.
-  * @retval None
-  */
-#define __HAL_PWR_PVM4_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
-
-/**
-  * @brief Disable the PVM4 Extended Interrupt Line.
-  * @retval None
-  */
-#define __HAL_PWR_PVM4_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
-
-/**
-  * @brief Enable the PVM4 Event Line.
-  * @retval None
-  */
-#define __HAL_PWR_PVM4_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
-
-/**
-  * @brief Disable the PVM4 Event Line.
-  * @retval None
-  */
-#define __HAL_PWR_PVM4_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
-
-/**
-  * @brief Enable the PVM4 Extended Interrupt Rising Trigger.
-  * @retval None
-  */
-#define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
-
-/**
-  * @brief Disable the PVM4 Extended Interrupt Rising Trigger.
-  * @retval None
-  */
-#define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
-
-/**
-  * @brief Enable the PVM4 Extended Interrupt Falling Trigger.
-  * @retval None
-  */
-#define __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
-
-
-/**
-  * @brief Disable the PVM4 Extended Interrupt Falling Trigger.
-  * @retval None
-  */
-#define __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
-
-
-/**
-  * @brief  PVM4 EXTI line configuration: set rising & falling edge trigger.
-  * @retval None
-  */
-#define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE()  \
-  do {                                                    \
-    __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE();             \
-    __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE();            \
-  } while(0)
-  
-/**
-  * @brief Disable the PVM4 Extended Interrupt Rising & Falling Trigger.
-  * @retval None
-  */
-#define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE()  \
-  do {                                                     \
-    __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE();             \
-    __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE();            \
-  } while(0)
-
-/**
-  * @brief  Generate a Software interrupt on selected EXTI line.
-  * @retval None
-  */
-#define __HAL_PWR_PVM4_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM4)
-
-/**
-  * @brief Check whether or not the specified PVM4 EXTI interrupt flag is set.
-  * @retval EXTI PVM4 Line Status.
-  */
-#define __HAL_PWR_PVM4_EXTI_GET_FLAG()  (EXTI->PR2 & PWR_EXTI_LINE_PVM4)
-
-/**
-  * @brief Clear the PVM4 EXTI flag.
-  * @retval None
-  */
-#define __HAL_PWR_PVM4_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM4)
-
-
-/**
-  * @brief Configure the main internal regulator output voltage.
-  * @param  __REGULATOR__: specifies the regulator output voltage to achieve
-  *         a tradeoff between performance and power consumption.
-  *          This parameter can be one of the following values:
-  *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1  Regulator voltage output range 1 mode,
-  *                                                typical output voltage at 1.2 V,  
-  *                                                system frequency up to 80 MHz.
-  *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2  Regulator voltage output range 2 mode,
-  *                                                typical output voltage at 1.0 V,                
-  *                                                system frequency up to 26 MHz.  
-  * @note  This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check
-  *        whether or not VOSF flag is cleared when moving from range 2 to range 1. User
-  *        may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting.   
-  * @retval None
-  */
-#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do {                                                     \
-                                                            __IO uint32_t tmpreg;                               \
-                                                            MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \
-                                                            /* Delay after an RCC peripheral clock enabling */  \
-                                                            tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS);           \
-                                                            UNUSED(tmpreg);                                     \
-                                                          } while(0)
-
-/**
-  * @}
-  */
-  
-/* Private macros --------------------------------------------------------*/
-/** @addtogroup  PWREx_Private_Macros   PWR Extended Private Macros
-  * @{
-  */
-
-#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
-                                ((PIN) == PWR_WAKEUP_PIN2) || \
-                                ((PIN) == PWR_WAKEUP_PIN3) || \
-                                ((PIN) == PWR_WAKEUP_PIN4) || \
-                                ((PIN) == PWR_WAKEUP_PIN5) || \
-                                ((PIN) == PWR_WAKEUP_PIN1_HIGH) || \
-                                ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \
-                                ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \
-                                ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \
-                                ((PIN) == PWR_WAKEUP_PIN5_HIGH) || \
-                                ((PIN) == PWR_WAKEUP_PIN1_LOW) || \
-                                ((PIN) == PWR_WAKEUP_PIN2_LOW) || \
-                                ((PIN) == PWR_WAKEUP_PIN3_LOW) || \
-                                ((PIN) == PWR_WAKEUP_PIN4_LOW) || \
-                                ((PIN) == PWR_WAKEUP_PIN5_LOW))
-                                
-#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
-#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\
-                               ((TYPE) == PWR_PVM_2) ||\
-                               ((TYPE) == PWR_PVM_3) ||\
-                               ((TYPE) == PWR_PVM_4))
-#elif defined (STM32L471xx)
-#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_2) ||\
-                               ((TYPE) == PWR_PVM_3) ||\
-                               ((TYPE) == PWR_PVM_4))
-#endif
-
-#define IS_PWR_PVM_MODE(MODE)  (((MODE) == PWR_PVM_MODE_NORMAL)              ||\
-                                ((MODE) == PWR_PVM_MODE_IT_RISING)           ||\
-                                ((MODE) == PWR_PVM_MODE_IT_FALLING)          ||\
-                                ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING)   ||\
-                                ((MODE) == PWR_PVM_MODE_EVENT_RISING)        ||\
-                                ((MODE) == PWR_PVM_MODE_EVENT_FALLING)       ||\
-                                ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING))  
-                                
-#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
-                                             ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
-                                             
-#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
-                                                  ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))  
-                                                  
-#define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\
-                                           ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE)) 
-                                           
-#define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00)
-                                           
-                             
-#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
-                           ((GPIO) == PWR_GPIO_B) ||\
-                           ((GPIO) == PWR_GPIO_C) ||\
-                           ((GPIO) == PWR_GPIO_D) ||\
-                           ((GPIO) == PWR_GPIO_E) ||\
-                           ((GPIO) == PWR_GPIO_F) ||\
-                           ((GPIO) == PWR_GPIO_G) ||\
-                           ((GPIO) == PWR_GPIO_H))
-
-
-/**
-  * @}
-  */  
-  
-
-/** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions
-  * @{
-  */
-  
-/** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions 
-  * @{
-  */
-
-
-/* Peripheral Control functions  **********************************************/
-uint32_t HAL_PWREx_GetVoltageRange(void);
-HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
-void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection);
-void HAL_PWREx_DisableBatteryCharging(void);
-#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
-void HAL_PWREx_EnableVddUSB(void);
-void HAL_PWREx_DisableVddUSB(void);
-#endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
-void HAL_PWREx_EnableVddIO2(void);
-void HAL_PWREx_DisableVddIO2(void);
-void HAL_PWREx_EnableInternalWakeUpLine(void);
-void HAL_PWREx_DisableInternalWakeUpLine(void);
-HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
-HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
-HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
-HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
-void HAL_PWREx_EnablePullUpPullDownConfig(void);
-void HAL_PWREx_DisablePullUpPullDownConfig(void);
-void HAL_PWREx_EnableSRAM2ContentRetention(void);
-void HAL_PWREx_DisableSRAM2ContentRetention(void);
-#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
-void HAL_PWREx_EnablePVM1(void);
-void HAL_PWREx_DisablePVM1(void);
-#endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
-void HAL_PWREx_EnablePVM2(void);
-void HAL_PWREx_DisablePVM2(void);
-void HAL_PWREx_EnablePVM3(void);
-void HAL_PWREx_DisablePVM3(void);
-void HAL_PWREx_EnablePVM4(void);
-void HAL_PWREx_DisablePVM4(void);
-HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM);
-
-
-/* Low Power modes configuration functions ************************************/
-void HAL_PWREx_EnableLowPowerRunMode(void);
-HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void);
-void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry);
-void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry);
-void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry);
-void HAL_PWREx_EnterSHUTDOWNMode(void);
-
-void HAL_PWREx_PVD_PVM_IRQHandler(void);
-#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
-void HAL_PWREx_PVM1Callback(void);
-#endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
-void HAL_PWREx_PVM2Callback(void);
-void HAL_PWREx_PVM3Callback(void);
-void HAL_PWREx_PVM4Callback(void);
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32L4xx_HAL_PWR_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/inc/stm32l4xx_hal_qspi.h b/stmhal/hal/l4/inc/stm32l4xx_hal_qspi.h
deleted file mode 100644
index 314cfdd603..0000000000
--- a/stmhal/hal/l4/inc/stm32l4xx_hal_qspi.h
+++ /dev/null
@@ -1,648 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_qspi.h
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   Header file of QSPI HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************  
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L4xx_HAL_QSPI_H
-#define __STM32L4xx_HAL_QSPI_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup QSPI
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup QSPI_Exported_Types QSPI Exported Types
-  * @{
-  */
-
-/** 
-  * @brief  QSPI Init structure definition  
-  */
-typedef struct
-{
-  uint32_t ClockPrescaler;     /* Specifies the prescaler factor for generating clock based on the AHB clock.
-                                  This parameter can be a number between 0 and 255 */ 
-  uint32_t FifoThreshold;      /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
-                                  This parameter can be a value between 1 and 16 */
-  uint32_t SampleShifting;     /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to 
-                                  take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
-                                  This parameter can be a value of @ref QSPI_SampleShifting */
-  uint32_t FlashSize;          /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits 
-                                  required to address the flash memory. The flash capacity can be up to 4GB 
-                                  (addressed using 32 bits) in indirect mode, but the addressable space in 
-                                  memory-mapped mode is limited to 256MB
-                                  This parameter can be a number between 0 and 31 */
-  uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number 
-                                  of clock cycles which the chip select must remain high between commands.
-                                  This parameter can be a value of @ref QSPI_ChipSelectHighTime */   
-  uint32_t ClockMode;          /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
-                                  This parameter can be a value of @ref QSPI_ClockMode */
-}QSPI_InitTypeDef;
-
-/** 
-  * @brief HAL QSPI State structures definition  
-  */ 
-typedef enum
-{
-  HAL_QSPI_STATE_RESET             = 0x00,    /*!< Peripheral not initialized                            */
-  HAL_QSPI_STATE_READY             = 0x01,    /*!< Peripheral initialized and ready for use              */
-  HAL_QSPI_STATE_BUSY              = 0x02,    /*!< Peripheral in indirect mode and busy                  */ 
-  HAL_QSPI_STATE_BUSY_INDIRECT_TX  = 0x12,    /*!< Peripheral in indirect mode with transmission ongoing */ 
-  HAL_QSPI_STATE_BUSY_INDIRECT_RX  = 0x22,    /*!< Peripheral in indirect mode with reception ongoing    */
-  HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42,    /*!< Peripheral in auto polling mode ongoing               */
-  HAL_QSPI_STATE_BUSY_MEM_MAPPED   = 0x82,    /*!< Peripheral in memory mapped mode ongoing              */
-  HAL_QSPI_STATE_ERROR             = 0x04     /*!< Peripheral in error                                   */
-}HAL_QSPI_StateTypeDef;
-
-/** 
-  * @brief  QSPI Handle Structure definition  
-  */  
-typedef struct
-{
-  QUADSPI_TypeDef            *Instance;        /* QSPI registers base address        */
-  QSPI_InitTypeDef           Init;             /* QSPI communication parameters      */
-  uint8_t                    *pTxBuffPtr;      /* Pointer to QSPI Tx transfer Buffer */
-  __IO uint16_t              TxXferSize;       /* QSPI Tx Transfer size              */
-  __IO uint16_t              TxXferCount;      /* QSPI Tx Transfer Counter           */
-  uint8_t                    *pRxBuffPtr;      /* Pointer to QSPI Rx transfer Buffer */
-  __IO uint16_t              RxXferSize;       /* QSPI Rx Transfer size              */
-  __IO uint16_t              RxXferCount;      /* QSPI Rx Transfer Counter           */
-  DMA_HandleTypeDef          *hdma;            /* QSPI Rx/Tx DMA Handle parameters   */
-  __IO HAL_LockTypeDef       Lock;             /* Locking object                     */
-  __IO HAL_QSPI_StateTypeDef State;            /* QSPI communication state           */
-  __IO uint32_t              ErrorCode;        /* QSPI Error code                    */
-  uint32_t                   Timeout;          /* Timeout for the QSPI memory access */ 
-}QSPI_HandleTypeDef;
-
-/** 
-  * @brief  QSPI Command structure definition  
-  */
-typedef struct
-{
-  uint32_t Instruction;        /* Specifies the Instruction to be sent
-                                  This parameter can be a value (8-bit) between 0x00 and 0xFF */
-  uint32_t Address;            /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
-                                  This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
-  uint32_t AlternateBytes;     /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
-                                  This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
-  uint32_t AddressSize;        /* Specifies the Address Size
-                                  This parameter can be a value of @ref QSPI_AddressSize */
-  uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
-                                  This parameter can be a value of @ref QSPI_AlternateBytesSize */
-  uint32_t DummyCycles;        /* Specifies the Number of Dummy Cycles.
-                                  This parameter can be a number between 0 and 31 */
-  uint32_t InstructionMode;    /* Specifies the Instruction Mode
-                                  This parameter can be a value of @ref QSPI_InstructionMode */
-  uint32_t AddressMode;        /* Specifies the Address Mode
-                                  This parameter can be a value of @ref QSPI_AddressMode */
-  uint32_t AlternateByteMode;  /* Specifies the Alternate Bytes Mode
-                                  This parameter can be a value of @ref QSPI_AlternateBytesMode */
-  uint32_t DataMode;           /* Specifies the Data Mode (used for dummy cycles and data phases)
-                                  This parameter can be a value of @ref QSPI_DataMode */
-  uint32_t NbData;             /* Specifies the number of data to transfer. 
-                                  This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length 
-                                  until end of memory)*/
-  uint32_t DdrMode;            /* Specifies the double data rate mode for address, alternate byte and data phase
-                                  This parameter can be a value of @ref QSPI_DdrMode */
-  uint32_t DdrHoldHalfCycle;   /* Specifies the DDR hold half cycle. It delays the data output by one half of 
-                                  system clock in DDR mode. Not available on STM32L4x6 devices but in future devices.
-                                  This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
-  uint32_t SIOOMode;           /* Specifies the send instruction only once mode
-                                  This parameter can be a value of @ref QSPI_SIOOMode */
-}QSPI_CommandTypeDef;
-
-/** 
-  * @brief  QSPI Auto Polling mode configuration structure definition  
-  */
-typedef struct
-{
-  uint32_t Match;              /* Specifies the value to be compared with the masked status register to get a match.
-                                  This parameter can be any value between 0 and 0xFFFFFFFF */
-  uint32_t Mask;               /* Specifies the mask to be applied to the status bytes received. 
-                                  This parameter can be any value between 0 and 0xFFFFFFFF */
-  uint32_t Interval;           /* Specifies the number of clock cycles between two read during automatic polling phases.
-                                  This parameter can be any value between 0 and 0xFFFF */
-  uint32_t StatusBytesSize;    /* Specifies the size of the status bytes received.
-                                  This parameter can be any value between 1 and 4 */
-  uint32_t MatchMode;          /* Specifies the method used for determining a match.
-                                  This parameter can be a value of @ref QSPI_MatchMode */
-  uint32_t AutomaticStop;      /* Specifies if automatic polling is stopped after a match.
-                                  This parameter can be a value of @ref QSPI_AutomaticStop */
-}QSPI_AutoPollingTypeDef;
-                           
-/** 
-  * @brief  QSPI Memory Mapped mode configuration structure definition  
-  */
-typedef struct
-{
-  uint32_t TimeOutPeriod;      /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
-                                  This parameter can be any value between 0 and 0xFFFF */
-  uint32_t TimeOutActivation;  /* Specifies if the timeout counter is enabled to release the chip select. 
-                                  This parameter can be a value of @ref QSPI_TimeOutActivation */
-}QSPI_MemoryMappedTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup QSPI_Exported_Constants QSPI Exported Constants
-  * @{
-  */
-
-/** @defgroup QSPI_ErrorCode QSPI Error Code
-  * @{
-  */ 
-#define HAL_QSPI_ERROR_NONE            ((uint32_t)0x00000000) /*!< No error           */
-#define HAL_QSPI_ERROR_TIMEOUT         ((uint32_t)0x00000001) /*!< Timeout error      */
-#define HAL_QSPI_ERROR_TRANSFER        ((uint32_t)0x00000002) /*!< Transfer error     */
-#define HAL_QSPI_ERROR_DMA             ((uint32_t)0x00000004) /*!< DMA transfer error */
-/**
-  * @}
-  */ 
-
-/** @defgroup QSPI_SampleShifting QSPI Sample Shifting
-  * @{
-  */
-#define QSPI_SAMPLE_SHIFTING_NONE      ((uint32_t)0x00000000)        /*!<No clock cycle shift to sample data*/
-#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
-/**
-  * @}
-  */ 
-
-/** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time
-  * @{
-  */
-#define QSPI_CS_HIGH_TIME_1_CYCLE      ((uint32_t)0x00000000)                              /*!<nCS stay high for at least 1 clock cycle between commands*/
-#define QSPI_CS_HIGH_TIME_2_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_0)                      /*!<nCS stay high for at least 2 clock cycles between commands*/
-#define QSPI_CS_HIGH_TIME_3_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_1)                      /*!<nCS stay high for at least 3 clock cycles between commands*/
-#define QSPI_CS_HIGH_TIME_4_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
-#define QSPI_CS_HIGH_TIME_5_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2)                      /*!<nCS stay high for at least 5 clock cycles between commands*/
-#define QSPI_CS_HIGH_TIME_6_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/
-#define QSPI_CS_HIGH_TIME_7_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/
-#define QSPI_CS_HIGH_TIME_8_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT)                        /*!<nCS stay high for at least 8 clock cycles between commands*/
-/**
-  * @}
-  */
-
-/** @defgroup QSPI_ClockMode QSPI Clock Mode
-  * @{
-  */
-#define QSPI_CLOCK_MODE_0              ((uint32_t)0x00000000)         /*!<Clk stays low while nCS is released*/
-#define QSPI_CLOCK_MODE_3              ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
-/**
-  * @}
-  */
-
-/** @defgroup QSPI_AddressSize QSPI Address Size
-  * @{
-  */
-#define QSPI_ADDRESS_8_BITS            ((uint32_t)0x00000000)           /*!<8-bit address*/
-#define QSPI_ADDRESS_16_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/
-#define QSPI_ADDRESS_24_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/
-#define QSPI_ADDRESS_32_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE)   /*!<32-bit address*/
-/**
-  * @}
-  */  
-
-/** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
-  * @{
-  */
-#define QSPI_ALTERNATE_BYTES_8_BITS    ((uint32_t)0x00000000)           /*!<8-bit alternate bytes*/
-#define QSPI_ALTERNATE_BYTES_16_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/
-#define QSPI_ALTERNATE_BYTES_24_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/
-#define QSPI_ALTERNATE_BYTES_32_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE)   /*!<32-bit alternate bytes*/
-/**
-  * @}
-  */
-
-/** @defgroup QSPI_InstructionMode QSPI Instruction Mode
-* @{
-*/
-#define QSPI_INSTRUCTION_NONE          ((uint32_t)0x00000000)          /*!<No instruction*/
-#define QSPI_INSTRUCTION_1_LINE        ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/
-#define QSPI_INSTRUCTION_2_LINES       ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/
-#define QSPI_INSTRUCTION_4_LINES       ((uint32_t)QUADSPI_CCR_IMODE)   /*!<Instruction on four lines*/
-/**
-  * @}
-  */
-
-/** @defgroup QSPI_AddressMode QSPI Address Mode
-* @{
-*/
-#define QSPI_ADDRESS_NONE              ((uint32_t)0x00000000)           /*!<No address*/
-#define QSPI_ADDRESS_1_LINE            ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/
-#define QSPI_ADDRESS_2_LINES           ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/
-#define QSPI_ADDRESS_4_LINES           ((uint32_t)QUADSPI_CCR_ADMODE)   /*!<Address on four lines*/
-/**
-  * @}
-  */  
-
-/** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
-* @{
-*/
-#define QSPI_ALTERNATE_BYTES_NONE      ((uint32_t)0x00000000)           /*!<No alternate bytes*/
-#define QSPI_ALTERNATE_BYTES_1_LINE    ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/
-#define QSPI_ALTERNATE_BYTES_2_LINES   ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/
-#define QSPI_ALTERNATE_BYTES_4_LINES   ((uint32_t)QUADSPI_CCR_ABMODE)   /*!<Alternate bytes on four lines*/
-/**
-  * @}
-  */  
-
-/** @defgroup QSPI_DataMode QSPI Data Mode
-  * @{
-  */
-#define QSPI_DATA_NONE                 ((uint32_t)0X00000000)           /*!<No data*/
-#define QSPI_DATA_1_LINE               ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/
-#define QSPI_DATA_2_LINES              ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/
-#define QSPI_DATA_4_LINES              ((uint32_t)QUADSPI_CCR_DMODE)   /*!<Data on four lines*/
-/**
-  * @}
-  */  
-
-/** @defgroup QSPI_DdrMode QSPI DDR Mode
-  * @{
-  */
-#define QSPI_DDR_MODE_DISABLE          ((uint32_t)0x00000000)       /*!<Double data rate mode disabled*/
-#define QSPI_DDR_MODE_ENABLE           ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
-/**
-  * @}
-  */
-
-/** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay
-  * @{
-  */
-#define QSPI_DDR_HHC_ANALOG_DELAY      ((uint32_t)0x00000000)       /*!<Delay the data output using analog delay in DDR mode*/
-/**
-  * @}
-  */
-
-/** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode
-  * @{
-  */
-#define QSPI_SIOO_INST_EVERY_CMD       ((uint32_t)0x00000000)       /*!<Send instruction on every transaction*/
-#define QSPI_SIOO_INST_ONLY_FIRST_CMD  ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/
-/**
-  * @}
-  */
-
-/** @defgroup QSPI_MatchMode QSPI Match Mode
-  * @{
-  */
-#define QSPI_MATCH_MODE_AND            ((uint32_t)0x00000000)     /*!<AND match mode between unmasked bits*/
-#define QSPI_MATCH_MODE_OR             ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
-/**
-  * @}
-  */  
-
-/** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
-  * @{
-  */
-#define QSPI_AUTOMATIC_STOP_DISABLE    ((uint32_t)0x00000000)      /*!<AutoPolling stops only with abort or QSPI disabling*/
-#define QSPI_AUTOMATIC_STOP_ENABLE     ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
-/**
-  * @}
-  */  
-
-/** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation
-  * @{
-  */
-#define QSPI_TIMEOUT_COUNTER_DISABLE   ((uint32_t)0x00000000)      /*!<Timeout counter disabled, nCS remains active*/
-#define QSPI_TIMEOUT_COUNTER_ENABLE    ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
-/**
-  * @}
-  */  
-
-/** @defgroup QSPI_Flags QSPI Flags
-  * @{
-  */
-#define QSPI_FLAG_BUSY                 QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/
-#define QSPI_FLAG_TO                   QUADSPI_SR_TOF  /*!<Timeout flag: timeout occurs in memory-mapped mode*/
-#define QSPI_FLAG_SM                   QUADSPI_SR_SMF  /*!<Status match flag: received data matches in autopolling mode*/
-#define QSPI_FLAG_FT                   QUADSPI_SR_FTF  /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/
-#define QSPI_FLAG_TC                   QUADSPI_SR_TCF  /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/
-#define QSPI_FLAG_TE                   QUADSPI_SR_TEF  /*!<Transfer error flag: invalid address is being accessed*/
-/**
-  * @}
-  */
-
-/** @defgroup QSPI_Interrupts QSPI Interrupts
-  * @{
-  */  
-#define QSPI_IT_TO                     QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/
-#define QSPI_IT_SM                     QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/
-#define QSPI_IT_FT                     QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/
-#define QSPI_IT_TC                     QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/
-#define QSPI_IT_TE                     QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/
-/**
-  * @}
-  */
-
-/** @defgroup QSPI_Timeout_definition QSPI Timeout definition
-  * @brief QSPI Timeout definition
-  * @{
-  */ 
-#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */
-/**
-  * @}
-  */  
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup QSPI_Exported_Macros QSPI Exported Macros
-  * @{
-  */
-/** @brief Reset QSPI handle state.
-  * @param  __HANDLE__: QSPI handle.
-  * @retval None
-  */
-#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__)           ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
-
-/** @brief  Enable the QSPI peripheral.
-  * @param  __HANDLE__: specifies the QSPI Handle.
-  * @retval None
-  */ 
-#define __HAL_QSPI_ENABLE(__HANDLE__)                       SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
-
-/** @brief  Disable the QSPI peripheral.
-  * @param  __HANDLE__: specifies the QSPI Handle.
-  * @retval None
-  */
-#define __HAL_QSPI_DISABLE(__HANDLE__)                      CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
-
-/** @brief  Enable the specified QSPI interrupt.
-  * @param  __HANDLE__: specifies the QSPI Handle.
-  * @param  __INTERRUPT__: specifies the QSPI interrupt source to enable.
-  *          This parameter can be one of the following values:
-  *            @arg QSPI_IT_TO: QSPI Timeout interrupt
-  *            @arg QSPI_IT_SM: QSPI Status match interrupt
-  *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
-  *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
-  *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
-  * @retval None
-  */
-#define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)     SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
-
-
-/** @brief  Disable the specified QSPI interrupt.
-  * @param  __HANDLE__: specifies the QSPI Handle.
-  * @param  __INTERRUPT__: specifies the QSPI interrupt source to disable.
-  *          This parameter can be one of the following values:
-  *            @arg QSPI_IT_TO: QSPI Timeout interrupt
-  *            @arg QSPI_IT_SM: QSPI Status match interrupt
-  *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
-  *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
-  *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
-  * @retval None
-  */
-#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)    CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
-
-/** @brief  Check whether the specified QSPI interrupt source is enabled or not.
-  * @param  __HANDLE__: specifies the QSPI Handle.
-  * @param  __INTERRUPT__: specifies the QSPI interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg QSPI_IT_TO: QSPI Timeout interrupt
-  *            @arg QSPI_IT_SM: QSPI Status match interrupt
-  *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
-  *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
-  *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
-  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
-  */
-#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) 
-
-/**
-  * @brief  Check whether the selected QSPI flag is set or not.
-  * @param  __HANDLE__: specifies the QSPI Handle.
-  * @param  __FLAG__: specifies the QSPI flag to check.
-  *          This parameter can be one of the following values:
-  *            @arg QSPI_FLAG_BUSY: QSPI Busy flag
-  *            @arg QSPI_FLAG_TO:   QSPI Timeout flag
-  *            @arg QSPI_FLAG_SM:   QSPI Status match flag
-  *            @arg QSPI_FLAG_FT:   QSPI FIFO threshold flag
-  *            @arg QSPI_FLAG_TC:   QSPI Transfer complete flag
-  *            @arg QSPI_FLAG_TE:   QSPI Transfer error flag
-  * @retval None
-  */
-#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__)           (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0)
-
-/** @brief  Clears the specified QSPI's flag status.
-  * @param  __HANDLE__: specifies the QSPI Handle.
-  * @param  __FLAG__: specifies the QSPI clear register flag that needs to be set
-  *          This parameter can be one of the following values:
-  *            @arg QSPI_FLAG_TO: QSPI Timeout flag
-  *            @arg QSPI_FLAG_SM: QSPI Status match flag
-  *            @arg QSPI_FLAG_TC: QSPI Transfer complete flag
-  *            @arg QSPI_FLAG_TE: QSPI Transfer error flag
-  * @retval None
-  */
-#define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__)         WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/  
-/** @addtogroup QSPI_Exported_Functions
-  * @{
-  */
-/* Initialization/de-initialization functions  ********************************/
-HAL_StatusTypeDef     HAL_QSPI_Init     (QSPI_HandleTypeDef *hqspi);
-HAL_StatusTypeDef     HAL_QSPI_DeInit   (QSPI_HandleTypeDef *hqspi);
-void                  HAL_QSPI_MspInit  (QSPI_HandleTypeDef *hqspi);
-void                  HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
-
-/* IO operation functions *****************************************************/
-/* QSPI IRQ handler method */
-void                  HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
-
-/* QSPI indirect mode */
-HAL_StatusTypeDef     HAL_QSPI_Command      (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);
-HAL_StatusTypeDef     HAL_QSPI_Transmit     (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
-HAL_StatusTypeDef     HAL_QSPI_Receive      (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
-HAL_StatusTypeDef     HAL_QSPI_Command_IT   (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);
-HAL_StatusTypeDef     HAL_QSPI_Transmit_IT  (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
-HAL_StatusTypeDef     HAL_QSPI_Receive_IT   (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
-HAL_StatusTypeDef     HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
-HAL_StatusTypeDef     HAL_QSPI_Receive_DMA  (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
-
-/* QSPI status flag polling mode */
-HAL_StatusTypeDef     HAL_QSPI_AutoPolling   (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
-HAL_StatusTypeDef     HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);
-
-/* QSPI memory-mapped mode */
-HAL_StatusTypeDef     HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);
-
-/* Callback functions in non-blocking modes ***********************************/
-void                  HAL_QSPI_ErrorCallback        (QSPI_HandleTypeDef *hqspi);
-void                  HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
-
-/* QSPI indirect mode */
-void                  HAL_QSPI_CmdCpltCallback      (QSPI_HandleTypeDef *hqspi);
-void                  HAL_QSPI_RxCpltCallback       (QSPI_HandleTypeDef *hqspi);
-void                  HAL_QSPI_TxCpltCallback       (QSPI_HandleTypeDef *hqspi);
-void                  HAL_QSPI_RxHalfCpltCallback   (QSPI_HandleTypeDef *hqspi);
-void                  HAL_QSPI_TxHalfCpltCallback   (QSPI_HandleTypeDef *hqspi);
-
-/* QSPI status flag polling mode */
-void                  HAL_QSPI_StatusMatchCallback  (QSPI_HandleTypeDef *hqspi);
-
-/* QSPI memory-mapped mode */
-void                  HAL_QSPI_TimeOutCallback      (QSPI_HandleTypeDef *hqspi);
-
-/* Peripheral Control and State functions  ************************************/
-HAL_QSPI_StateTypeDef HAL_QSPI_GetState  (QSPI_HandleTypeDef *hqspi);
-uint32_t              HAL_QSPI_GetError  (QSPI_HandleTypeDef *hqspi);
-HAL_StatusTypeDef     HAL_QSPI_Abort     (QSPI_HandleTypeDef *hqspi);
-void                  HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
-/**
-  * @}
-  */
-/* End of exported functions -------------------------------------------------*/  
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup QSPI_Private_Macros QSPI Private Macros
-* @{
-*/
-#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFF)
-
-#define IS_QSPI_FIFO_THRESHOLD(THR)        (((THR) > 0) && ((THR) <= 16))
-
-#define IS_QSPI_SSHIFT(SSHIFT)             (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
-                                            ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
-
-#define IS_QSPI_FLASH_SIZE(FSIZE)          (((FSIZE) <= 31))
-
-#define IS_QSPI_CS_HIGH_TIME(CSHTIME)      (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
-                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
-                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
-                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
-                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
-                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
-                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
-                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
-
-#define IS_QSPI_CLOCK_MODE(CLKMODE)        (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
-                                            ((CLKMODE) == QSPI_CLOCK_MODE_3))
-
-#define IS_QSPI_INSTRUCTION(INSTRUCTION)   ((INSTRUCTION) <= 0xFF) 
-
-#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE)    (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS)  || \
-                                            ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
-                                            ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
-                                            ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
-
-#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS)  || \
-                                            ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
-                                            ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
-                                            ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
-
-#define IS_QSPI_DUMMY_CYCLES(DCY)          ((DCY) <= 31) 
-
-#define IS_QSPI_INSTRUCTION_MODE(MODE)     (((MODE) == QSPI_INSTRUCTION_NONE)    || \
-                                            ((MODE) == QSPI_INSTRUCTION_1_LINE)  || \
-                                            ((MODE) == QSPI_INSTRUCTION_2_LINES) || \
-                                            ((MODE) == QSPI_INSTRUCTION_4_LINES))
-
-#define IS_QSPI_ADDRESS_MODE(MODE)         (((MODE) == QSPI_ADDRESS_NONE)    || \
-                                            ((MODE) == QSPI_ADDRESS_1_LINE)  || \
-                                            ((MODE) == QSPI_ADDRESS_2_LINES) || \
-                                            ((MODE) == QSPI_ADDRESS_4_LINES))
-
-#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE)    || \
-                                            ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE)  || \
-                                            ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
-                                            ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
-
-#define IS_QSPI_DATA_MODE(MODE)            (((MODE) == QSPI_DATA_NONE)    || \
-                                            ((MODE) == QSPI_DATA_1_LINE)  || \
-                                            ((MODE) == QSPI_DATA_2_LINES) || \
-                                            ((MODE) == QSPI_DATA_4_LINES))
-
-#define IS_QSPI_DDR_MODE(DDR_MODE)         (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
-                                            ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
-
-#define IS_QSPI_DDR_HHC(DDR_HHC)           (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY))
-
-#define IS_QSPI_SIOO_MODE(SIOO_MODE)       (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
-                                            ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
-
-#define IS_QSPI_INTERVAL(INTERVAL)         ((INTERVAL) <= QUADSPI_PIR_INTERVAL) 
-
-#define IS_QSPI_STATUS_BYTES_SIZE(SIZE)    (((SIZE) >= 1) && ((SIZE) <= 4)) 
-
-#define IS_QSPI_MATCH_MODE(MODE)           (((MODE) == QSPI_MATCH_MODE_AND) || \
-                                            ((MODE) == QSPI_MATCH_MODE_OR)) 
-
-#define IS_QSPI_AUTOMATIC_STOP(APMS)       (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
-                                            ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE)) 
-
-#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN)   (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
-                                            ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE)) 
-
-#define IS_QSPI_TIMEOUT_PERIOD(PERIOD)     ((PERIOD) <= 0xFFFF) 
-/**
-* @}
-*/ 
-/* End of private macros -----------------------------------------------------*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L4xx_HAL_QSPI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/inc/stm32l4xx_hal_rcc.h b/stmhal/hal/l4/inc/stm32l4xx_hal_rcc.h
deleted file mode 100644
index 6afdf8add4..0000000000
--- a/stmhal/hal/l4/inc/stm32l4xx_hal_rcc.h
+++ /dev/null
@@ -1,3208 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_rcc.h
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   Header file of RCC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L4xx_HAL_RCC_H
-#define __STM32L4xx_HAL_RCC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup RCC
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup RCC_Exported_Types RCC Exported Types
-  * @{
-  */
-
-/**
-  * @brief  RCC PLL configuration structure definition
-  */
-typedef struct
-{
-  uint32_t PLLState;   /*!< The new state of the PLL.
-                            This parameter can be a value of @ref RCC_PLL_Config                      */
-
-  uint32_t PLLSource;  /*!< RCC_PLLSource: PLL entry clock source.
-                            This parameter must be a value of @ref RCC_PLL_Clock_Source               */
-
-  uint32_t PLLM;       /*!< PLLM: Division factor for PLL VCO input clock.
-                            This parameter must be a number between Min_Data = 0 and Max_Data = 8     */
-
-  uint32_t PLLN;       /*!< PLLN: Multiplication factor for PLL VCO output clock.
-                            This parameter must be a number between Min_Data = 8 and Max_Data = 86    */
-
-  uint32_t PLLP;       /*!< PLLP: Division factor for SAI clock.
-                            This parameter must be a value of @ref RCC_PLLP_Clock_Divider             */
-
-  uint32_t PLLQ;       /*!< PLLQ: Division factor for SDMMC1, RNG and USB clocks.
-                            This parameter must be a value of @ref RCC_PLLQ_Clock_Divider             */
-
-  uint32_t PLLR;       /*!< PLLR: Division for the main system clock.
-                            User have to set the PLLR parameter correctly to not exceed max frequency 80MHZ.
-                            This parameter must be a value of @ref RCC_PLLR_Clock_Divider             */
-
-}RCC_PLLInitTypeDef;
-
-/**
-  * @brief  RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition
-  */
-typedef struct
-{
-  uint32_t OscillatorType;       /*!< The oscillators to be configured.
-                                      This parameter can be a value of @ref RCC_Oscillator_Type                   */
-
-  uint32_t HSEState;             /*!< The new state of the HSE.
-                                      This parameter can be a value of @ref RCC_HSE_Config                        */
-
-  uint32_t LSEState;             /*!< The new state of the LSE.
-                                      This parameter can be a value of @ref RCC_LSE_Config                        */
-
-  uint32_t HSIState;             /*!< The new state of the HSI.
-                                      This parameter can be a value of @ref RCC_HSI_Config                        */
-
-  uint32_t HSICalibrationValue;  /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
-                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
-
-  uint32_t LSIState;             /*!< The new state of the LSI.
-                                      This parameter can be a value of @ref RCC_LSI_Config                        */
-
-  uint32_t MSIState;             /*!< The new state of the MSI.
-                                      This parameter can be a value of @ref RCC_MSI_Config */
-
-  uint32_t MSICalibrationValue;  /*!< The calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT).
-                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
-
-  uint32_t MSIClockRange;        /*!< The MSI frequency range.
-                                      This parameter can be a value of @ref RCC_MSI_Clock_Range  */
-
-  RCC_PLLInitTypeDef PLL;        /*!< Main PLL structure parameters                                               */
-
-}RCC_OscInitTypeDef;
-
-/**
-  * @brief  RCC System, AHB and APB busses clock configuration structure definition
-  */
-typedef struct
-{
-  uint32_t ClockType;             /*!< The clock to be configured.
-                                       This parameter can be a value of @ref RCC_System_Clock_Type      */
-
-  uint32_t SYSCLKSource;          /*!< The clock source used as system clock (SYSCLK).
-                                       This parameter can be a value of @ref RCC_System_Clock_Source    */
-
-  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
-                                       This parameter can be a value of @ref RCC_AHB_Clock_Source       */
-
-  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
-                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
-
-  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
-                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
-
-}RCC_ClkInitTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RCC_Exported_Constants RCC Exported Constants
-  * @{
-  */
-
-/** @defgroup RCC_Timeout_Value Timeout Values
-  * @{
-  */
-#define RCC_DBP_TIMEOUT_VALUE          ((uint32_t)2U)    /* 2 ms (minimum Tick + 1) */
-#define RCC_LSE_TIMEOUT_VALUE          LSE_STARTUP_TIMEOUT
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Oscillator_Type Oscillator Type
-  * @{
-  */
-#define RCC_OSCILLATORTYPE_NONE        ((uint32_t)0x00000000U)   /*!< Oscillator configuration unchanged */
-#define RCC_OSCILLATORTYPE_HSE         ((uint32_t)0x00000001U)   /*!< HSE to configure */
-#define RCC_OSCILLATORTYPE_HSI         ((uint32_t)0x00000002U)   /*!< HSI to configure */
-#define RCC_OSCILLATORTYPE_LSE         ((uint32_t)0x00000004U)   /*!< LSE to configure */
-#define RCC_OSCILLATORTYPE_LSI         ((uint32_t)0x00000008U)   /*!< LSI to configure */
-#define RCC_OSCILLATORTYPE_MSI         ((uint32_t)0x00000010U)   /*!< MSI to configure */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_HSE_Config HSE Config
-  * @{
-  */
-#define RCC_HSE_OFF                    ((uint32_t)0x00000000U)                     /*!< HSE clock deactivation */
-#define RCC_HSE_ON                     RCC_CR_HSEON                               /*!< HSE clock activation */
-#define RCC_HSE_BYPASS                 ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LSE_Config LSE Config
-  * @{
-  */
-#define RCC_LSE_OFF                    ((uint32_t)0x00000000U)                         /*!< LSE clock deactivation */
-#define RCC_LSE_ON                     RCC_BDCR_LSEON                                 /*!< LSE clock activation */
-#define RCC_LSE_BYPASS                 ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_HSI_Config HSI Config
-  * @{
-  */
-#define RCC_HSI_OFF                    ((uint32_t)0x00000000U) /*!< HSI clock deactivation */
-#define RCC_HSI_ON                     RCC_CR_HSION           /*!< HSI clock activation */
-
-#define RCC_HSICALIBRATION_DEFAULT     ((uint32_t)16)   /*!< Default HSI calibration trimming value */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LSI_Config LSI Config
-  * @{
-  */
-#define RCC_LSI_OFF                    ((uint32_t)0x00000000U) /*!< LSI clock deactivation */
-#define RCC_LSI_ON                     RCC_CSR_LSION          /*!< LSI clock activation */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_MSI_Config MSI Config
-  * @{
-  */
-#define RCC_MSI_OFF                    ((uint32_t)0x00000000U) /*!< MSI clock deactivation */
-#define RCC_MSI_ON                     RCC_CR_MSION           /*!< MSI clock activation */
-
-#define RCC_MSICALIBRATION_DEFAULT     ((uint32_t)0)   /*!< Default MSI calibration trimming value */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PLL_Config PLL Config
-  * @{
-  */
-#define RCC_PLL_NONE                   ((uint32_t)0x00000000U) /*!< PLL configuration unchanged */
-#define RCC_PLL_OFF                    ((uint32_t)0x00000001U) /*!< PLL deactivation */
-#define RCC_PLL_ON                     ((uint32_t)0x00000002U) /*!< PLL activation */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
-  * @{
-  */
-#define RCC_PLLP_DIV7                  ((uint32_t)0x00000007U) /*!< PLLP division factor = 7  */
-#define RCC_PLLP_DIV17                 ((uint32_t)0x00000011U) /*!< PLLP division factor = 17 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider
-  * @{
-  */
-#define RCC_PLLQ_DIV2                  ((uint32_t)0x00000002U) /*!< PLLQ division factor = 2 */
-#define RCC_PLLQ_DIV4                  ((uint32_t)0x00000004U) /*!< PLLQ division factor = 4 */
-#define RCC_PLLQ_DIV6                  ((uint32_t)0x00000006U) /*!< PLLQ division factor = 6 */
-#define RCC_PLLQ_DIV8                  ((uint32_t)0x00000008U) /*!< PLLQ division factor = 8 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider
-  * @{
-  */
-#define RCC_PLLR_DIV2                  ((uint32_t)0x00000002U) /*!< PLLR division factor = 2 */
-#define RCC_PLLR_DIV4                  ((uint32_t)0x00000004U) /*!< PLLR division factor = 4 */
-#define RCC_PLLR_DIV6                  ((uint32_t)0x00000006U) /*!< PLLR division factor = 6 */
-#define RCC_PLLR_DIV8                  ((uint32_t)0x00000008U) /*!< PLLR division factor = 8 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
-  * @{
-  */
-#define RCC_PLLSOURCE_NONE             ((uint32_t)0x00000000U)  /*!< No clock selected as PLL entry clock source  */
-#define RCC_PLLSOURCE_MSI              RCC_PLLCFGR_PLLSRC_MSI  /*!< MSI clock selected as PLL entry clock source */
-#define RCC_PLLSOURCE_HSI              RCC_PLLCFGR_PLLSRC_HSI  /*!< HSI clock selected as PLL entry clock source */
-#define RCC_PLLSOURCE_HSE              RCC_PLLCFGR_PLLSRC_HSE  /*!< HSE clock selected as PLL entry clock source */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PLL_Clock_Output PLL Clock Output
-  * @{
-  */
-#define RCC_PLL_SAI3CLK                RCC_PLLCFGR_PLLPEN      /*!< PLLSAI3CLK selection from main PLL */
-#define RCC_PLL_48M1CLK                RCC_PLLCFGR_PLLQEN      /*!< PLL48M1CLK selection from main PLL */
-#define RCC_PLL_SYSCLK                 RCC_PLLCFGR_PLLREN      /*!< PLLCLK selection from main PLL */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PLLSAI1_Clock_Output PLLSAI1 Clock Output
-  * @{
-  */
-#define RCC_PLLSAI1_SAI1CLK            RCC_PLLSAI1CFGR_PLLSAI1PEN /*!< PLLSAI1CLK selection from PLLSAI1 */
-#define RCC_PLLSAI1_48M2CLK            RCC_PLLSAI1CFGR_PLLSAI1QEN /*!< PLL48M2CLK selection from PLLSAI1 */
-#define RCC_PLLSAI1_ADC1CLK            RCC_PLLSAI1CFGR_PLLSAI1REN /*!< PLLADC1CLK selection from PLLSAI1 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PLLSAI2_Clock_Output PLLSAI2 Clock Output
-  * @{
-  */
-#define RCC_PLLSAI2_SAI2CLK            RCC_PLLSAI2CFGR_PLLSAI2PEN /*!< PLLSAI2CLK selection from PLLSAI2 */
-#define RCC_PLLSAI2_ADC2CLK            RCC_PLLSAI2CFGR_PLLSAI2REN /*!< PLLADC2CLK selection from PLLSAI2 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_MSI_Clock_Range MSI Clock Range
-  * @{
-  */
-#define RCC_MSIRANGE_0                 RCC_CR_MSIRANGE_0  /*!< MSI = 100 KHz  */
-#define RCC_MSIRANGE_1                 RCC_CR_MSIRANGE_1  /*!< MSI = 200 KHz  */
-#define RCC_MSIRANGE_2                 RCC_CR_MSIRANGE_2  /*!< MSI = 400 KHz  */
-#define RCC_MSIRANGE_3                 RCC_CR_MSIRANGE_3  /*!< MSI = 800 KHz  */
-#define RCC_MSIRANGE_4                 RCC_CR_MSIRANGE_4  /*!< MSI = 1 MHz    */
-#define RCC_MSIRANGE_5                 RCC_CR_MSIRANGE_5  /*!< MSI = 2 MHz    */
-#define RCC_MSIRANGE_6                 RCC_CR_MSIRANGE_6  /*!< MSI = 4 MHz    */
-#define RCC_MSIRANGE_7                 RCC_CR_MSIRANGE_7  /*!< MSI = 8 MHz    */
-#define RCC_MSIRANGE_8                 RCC_CR_MSIRANGE_8  /*!< MSI = 16 MHz   */
-#define RCC_MSIRANGE_9                 RCC_CR_MSIRANGE_9  /*!< MSI = 24 MHz   */
-#define RCC_MSIRANGE_10                RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz   */
-#define RCC_MSIRANGE_11                RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz   */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_System_Clock_Type System Clock Type
-  * @{
-  */
-#define RCC_CLOCKTYPE_SYSCLK           ((uint32_t)0x00000001U)  /*!< SYSCLK to configure */
-#define RCC_CLOCKTYPE_HCLK             ((uint32_t)0x00000002U)  /*!< HCLK to configure */
-#define RCC_CLOCKTYPE_PCLK1            ((uint32_t)0x00000004U)  /*!< PCLK1 to configure */
-#define RCC_CLOCKTYPE_PCLK2            ((uint32_t)0x00000008U)  /*!< PCLK2 to configure */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_System_Clock_Source System Clock Source
-  * @{
-  */
-#define RCC_SYSCLKSOURCE_MSI           RCC_CFGR_SW_MSI    /*!< MSI selection as system clock */
-#define RCC_SYSCLKSOURCE_HSI           RCC_CFGR_SW_HSI    /*!< HSI selection as system clock */
-#define RCC_SYSCLKSOURCE_HSE           RCC_CFGR_SW_HSE    /*!< HSE selection as system clock */
-#define RCC_SYSCLKSOURCE_PLLCLK        RCC_CFGR_SW_PLL    /*!< PLL selection as system clock */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
-  * @{
-  */
-#define RCC_SYSCLKSOURCE_STATUS_MSI    RCC_CFGR_SWS_MSI   /*!< MSI used as system clock */
-#define RCC_SYSCLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
-#define RCC_SYSCLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
-#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL   /*!< PLL used as system clock */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
-  * @{
-  */
-#define RCC_SYSCLK_DIV1                RCC_CFGR_HPRE_DIV1   /*!< SYSCLK not divided */
-#define RCC_SYSCLK_DIV2                RCC_CFGR_HPRE_DIV2   /*!< SYSCLK divided by 2 */
-#define RCC_SYSCLK_DIV4                RCC_CFGR_HPRE_DIV4   /*!< SYSCLK divided by 4 */
-#define RCC_SYSCLK_DIV8                RCC_CFGR_HPRE_DIV8   /*!< SYSCLK divided by 8 */
-#define RCC_SYSCLK_DIV16               RCC_CFGR_HPRE_DIV16  /*!< SYSCLK divided by 16 */
-#define RCC_SYSCLK_DIV64               RCC_CFGR_HPRE_DIV64  /*!< SYSCLK divided by 64 */
-#define RCC_SYSCLK_DIV128              RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
-#define RCC_SYSCLK_DIV256              RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
-#define RCC_SYSCLK_DIV512              RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
-  * @{
-  */
-#define RCC_HCLK_DIV1                  RCC_CFGR_PPRE1_DIV1  /*!< HCLK not divided */
-#define RCC_HCLK_DIV2                  RCC_CFGR_PPRE1_DIV2  /*!< HCLK divided by 2 */
-#define RCC_HCLK_DIV4                  RCC_CFGR_PPRE1_DIV4  /*!< HCLK divided by 4 */
-#define RCC_HCLK_DIV8                  RCC_CFGR_PPRE1_DIV8  /*!< HCLK divided by 8 */
-#define RCC_HCLK_DIV16                 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
-  * @{
-  */
-#define RCC_RTCCLKSOURCE_LSE           RCC_BDCR_RTCSEL_0  /*!< LSE oscillator clock used as RTC clock */
-#define RCC_RTCCLKSOURCE_LSI           RCC_BDCR_RTCSEL_1  /*!< LSI oscillator clock used as RTC clock */
-#define RCC_RTCCLKSOURCE_HSE_DIV32     RCC_BDCR_RTCSEL    /*!< HSE oscillator clock divided by 32 used as RTC clock */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_MCO_Index MCO Index
-  * @{
-  */
-#define RCC_MCO1                       ((uint32_t)0x00000000U)
-#define RCC_MCO                        RCC_MCO1               /*!< MCO1 to be compliant with other families with 2 MCOs*/
-/**
-  * @}
-  */
-
-/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
-  * @{
-  */
-#define RCC_MCO1SOURCE_NOCLOCK         ((uint32_t)0x00000000U)                 /*!< MCO1 output disabled, no clock on MCO1 */
-#define RCC_MCO1SOURCE_SYSCLK          RCC_CFGR_MCOSEL_0                      /*!< SYSCLK selection as MCO1 source */
-#define RCC_MCO1SOURCE_MSI             RCC_CFGR_MCOSEL_1                      /*!< MSI selection as MCO1 source */
-#define RCC_MCO1SOURCE_HSI             (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */
-#define RCC_MCO1SOURCE_HSE             RCC_CFGR_MCOSEL_2                      /*!< HSE selection as MCO1 source */
-#define RCC_MCO1SOURCE_PLLCLK          (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2)  /*!< PLLCLK selection as MCO1 source */
-#define RCC_MCO1SOURCE_LSI             (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)  /*!< LSI selection as MCO1 source */
-#define RCC_MCO1SOURCE_LSE             (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler
-  * @{
-  */
-#define RCC_MCODIV_1                   RCC_CFGR_MCOPRE_DIV1     /*!< MCO not divided  */      
-#define RCC_MCODIV_2                   RCC_CFGR_MCOPRE_DIV2     /*!< MCO divided by 2 */
-#define RCC_MCODIV_4                   RCC_CFGR_MCOPRE_DIV4     /*!< MCO divided by 4 */
-#define RCC_MCODIV_8                   RCC_CFGR_MCOPRE_DIV8     /*!< MCO divided by 8 */
-#define RCC_MCODIV_16                  RCC_CFGR_MCOPRE_DIV16    /*!< MCO divided by 16 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Interrupt Interrupts
-  * @{
-  */
-#define RCC_IT_LSIRDY                  RCC_CIFR_LSIRDYF      /*!< LSI Ready Interrupt flag */
-#define RCC_IT_LSERDY                  RCC_CIFR_LSERDYF      /*!< LSE Ready Interrupt flag */
-#define RCC_IT_MSIRDY                  RCC_CIFR_MSIRDYF      /*!< MSI Ready Interrupt flag */
-#define RCC_IT_HSIRDY                  RCC_CIFR_HSIRDYF      /*!< HSI16 Ready Interrupt flag */
-#define RCC_IT_HSERDY                  RCC_CIFR_HSERDYF      /*!< HSE Ready Interrupt flag */
-#define RCC_IT_PLLRDY                  RCC_CIFR_PLLRDYF      /*!< PLL Ready Interrupt flag */
-#define RCC_IT_PLLSAI1RDY              RCC_CIFR_PLLSAI1RDYF  /*!< PLLSAI1 Ready Interrupt flag */
-#define RCC_IT_PLLSAI2RDY              RCC_CIFR_PLLSAI2RDYF  /*!< PLLSAI2 Ready Interrupt flag */
-#define RCC_IT_CSS                     RCC_CIFR_CSSF        /*!< Clock Security System Interrupt flag */
-#define RCC_IT_LSECSS                  RCC_CIFR_LSECSSF     /*!< LSE Clock Security System Interrupt flag */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Flag Flags
-  *        Elements values convention: XXXYYYYYb
-  *           - YYYYY  : Flag position in the register
-  *           - XXX  : Register index
-  *                 - 001: CR register
-  *                 - 010: BDCR register
-  *                 - 011: CSR register
-  * @{
-  */
-/* Flags in the CR register */
-#define RCC_FLAG_MSIRDY                ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_MSIRDY))) /*!< MSI Ready flag */
-#define RCC_FLAG_HSIRDY                ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< HSI Ready flag */
-#define RCC_FLAG_HSERDY                ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSERDY))) /*!< HSE Ready flag */
-#define RCC_FLAG_PLLRDY                ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL Ready flag */
-#define RCC_FLAG_PLLSAI1RDY            ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLSAI1RDY))) /*!< PLLSAI1 Ready flag */
-#define RCC_FLAG_PLLSAI2RDY            ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLSAI2RDY))) /*!< PLLSAI2 Ready flag */
-
-/* Flags in the BDCR register */
-#define RCC_FLAG_LSERDY                ((uint32_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSERDY))) /*!< LSE Ready flag */
-#define RCC_FLAG_LSECSSD               ((uint32_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSECSSD))) /*!< LSE Clock Security System Interrupt flag */
-
-/* Flags in the CSR register */
-#define RCC_FLAG_LSIRDY                ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LSIRDY)))   /*!< LSI Ready flag */
-#define RCC_FLAG_RMVF                  ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_RMVF)))     /*!< Remove reset flag */
-#define RCC_FLAG_FWRST                 ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_FWRSTF)))   /*!< Firewall reset flag */
-#define RCC_FLAG_OBLRST                ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_OBLRSTF)))  /*!< Option Byte Loader reset flag */
-#define RCC_FLAG_PINRST                ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PINRSTF)))  /*!< PIN reset flag */
-#define RCC_FLAG_BORRST                ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_BORRSTF)))  /*!< BOR reset flag */
-#define RCC_FLAG_SFTRST                ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_SFTRSTF)))  /*!< Software Reset flag */
-#define RCC_FLAG_IWDGRST               ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */
-#define RCC_FLAG_WWDGRST               ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */
-#define RCC_FLAG_LPWRRST               ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LSEDrive_Config LSE Drive Config
-  * @{
-  */
-#define RCC_LSEDRIVE_LOW                 ((uint32_t)0x00000000U) /*!< LSE low drive capability */
-#define RCC_LSEDRIVE_MEDIUMLOW           RCC_BDCR_LSEDRV_0      /*!< LSE medium low drive capability */
-#define RCC_LSEDRIVE_MEDIUMHIGH          RCC_BDCR_LSEDRV_1      /*!< LSE medium high drive capability */ 
-#define RCC_LSEDRIVE_HIGH                RCC_BDCR_LSEDRV        /*!< LSE high drive capability */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock 
-  * @{
-  */
-#define RCC_STOP_WAKEUPCLOCK_MSI       ((uint32_t)0x00000000U)  /*!< MSI selection after wake-up from STOP */
-#define RCC_STOP_WAKEUPCLOCK_HSI       RCC_CFGR_STOPWUCK       /*!< HSI selection after wake-up from STOP */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-
-/** @defgroup RCC_Exported_Macros RCC Exported Macros
-  * @{
-  */
-
-/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-
-#define __HAL_RCC_DMA1_CLK_ENABLE()            do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_DMA2_CLK_ENABLE()            do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_FLASH_CLK_ENABLE()           do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_CRC_CLK_ENABLE()             do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_TSC_CLK_ENABLE()             do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_DMA1_CLK_DISABLE()           CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN)
-
-#define __HAL_RCC_DMA2_CLK_DISABLE()           CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN)
-
-#define __HAL_RCC_FLASH_CLK_DISABLE()          CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN)
-
-#define __HAL_RCC_CRC_CLK_DISABLE()            CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN)
-
-#define __HAL_RCC_TSC_CLK_DISABLE()            CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the AHB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-
-#define __HAL_RCC_GPIOA_CLK_ENABLE()           do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_GPIOB_CLK_ENABLE()           do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_GPIOC_CLK_ENABLE()           do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_GPIOD_CLK_ENABLE()           do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_GPIOE_CLK_ENABLE()           do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_GPIOF_CLK_ENABLE()           do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_GPIOG_CLK_ENABLE()           do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_GPIOH_CLK_ENABLE()           do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#if defined(USB_OTG_FS)
-#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()      do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-#endif /* USB_OTG_FS */
-
-#define __HAL_RCC_ADC_CLK_ENABLE()             do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#if defined(AES)
-#define __HAL_RCC_AES_CLK_ENABLE()             do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-#endif /* AES */
-
-#define __HAL_RCC_RNG_CLK_ENABLE()             do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_GPIOA_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN)
-
-#define __HAL_RCC_GPIOB_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN)
-
-#define __HAL_RCC_GPIOC_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN)
-
-#define __HAL_RCC_GPIOD_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN)
-
-#define __HAL_RCC_GPIOE_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN)
-
-#define __HAL_RCC_GPIOF_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN)
-
-#define __HAL_RCC_GPIOG_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN)
-
-#define __HAL_RCC_GPIOH_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN)
-
-#if defined(USB_OTG_FS)
-#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE()     CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);
-#endif /* USB_OTG_FS */
-
-#define __HAL_RCC_ADC_CLK_DISABLE()            CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN)
-
-#if defined(AES)
-#define __HAL_RCC_AES_CLK_DISABLE()            CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);
-#endif /* AES */
-
-#define __HAL_RCC_RNG_CLK_DISABLE()            CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the AHB3 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-
-#define __HAL_RCC_FMC_CLK_ENABLE()             do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_QSPI_CLK_ENABLE()            do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_FMC_CLK_DISABLE()            CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN)
-
-#define __HAL_RCC_QSPI_CLK_DISABLE()           CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the APB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-
-#define __HAL_RCC_TIM2_CLK_ENABLE()            do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_TIM3_CLK_ENABLE()            do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_TIM4_CLK_ENABLE()            do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_TIM5_CLK_ENABLE()            do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_TIM6_CLK_ENABLE()            do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_TIM7_CLK_ENABLE()            do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#if defined(LCD)
-#define __HAL_RCC_LCD_CLK_ENABLE()             do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-#endif /* LCD */
-
-#define __HAL_RCC_WWDG_CLK_ENABLE()            do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_SPI2_CLK_ENABLE()            do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_SPI3_CLK_ENABLE()            do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_USART2_CLK_ENABLE()          do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_USART3_CLK_ENABLE()          do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_UART4_CLK_ENABLE()           do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_UART5_CLK_ENABLE()           do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_I2C1_CLK_ENABLE()            do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_I2C2_CLK_ENABLE()            do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_I2C3_CLK_ENABLE()            do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_CAN1_CLK_ENABLE()            do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_PWR_CLK_ENABLE()             do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_DAC1_CLK_ENABLE()            do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_OPAMP_CLK_ENABLE()           do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_LPTIM1_CLK_ENABLE()          do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_LPUART1_CLK_ENABLE()         do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_SWPMI1_CLK_ENABLE()          do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_LPTIM2_CLK_ENABLE()          do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_TIM2_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN)
-
-#define __HAL_RCC_TIM3_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN)
-
-#define __HAL_RCC_TIM4_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN)
-
-#define __HAL_RCC_TIM5_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN)
-
-#define __HAL_RCC_TIM6_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN)
-
-#define __HAL_RCC_TIM7_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN)
-
-#if defined(LCD)
-#define __HAL_RCC_LCD_CLK_DISABLE()            CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN);
-#endif /* LCD */
-
-#define __HAL_RCC_SPI2_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN)
-
-#define __HAL_RCC_SPI3_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN)
-
-#define __HAL_RCC_USART2_CLK_DISABLE()         CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN)
-
-#define __HAL_RCC_USART3_CLK_DISABLE()         CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN)
-
-#define __HAL_RCC_UART4_CLK_DISABLE()          CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN)
-
-#define __HAL_RCC_UART5_CLK_DISABLE()          CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN)
-
-#define __HAL_RCC_I2C1_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN)
-
-#define __HAL_RCC_I2C2_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN)
-
-#define __HAL_RCC_I2C3_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN)
-
-#define __HAL_RCC_CAN1_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN)
-
-#define __HAL_RCC_PWR_CLK_DISABLE()            CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN)
-
-#define __HAL_RCC_DAC1_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN)
-
-#define __HAL_RCC_OPAMP_CLK_DISABLE()          CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN)
-
-#define __HAL_RCC_LPTIM1_CLK_DISABLE()         CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN)
-
-#define __HAL_RCC_LPUART1_CLK_DISABLE()        CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN)
-
-#define __HAL_RCC_SWPMI1_CLK_DISABLE()         CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN)
-
-#define __HAL_RCC_LPTIM2_CLK_DISABLE()         CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the APB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-
-#define __HAL_RCC_SYSCFG_CLK_ENABLE()          do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_FIREWALL_CLK_ENABLE()        do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_SDMMC1_CLK_ENABLE()          do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_TIM1_CLK_ENABLE()            do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_SPI1_CLK_ENABLE()            do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_TIM8_CLK_ENABLE()            do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_USART1_CLK_ENABLE()          do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-
-#define __HAL_RCC_TIM15_CLK_ENABLE()           do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_TIM16_CLK_ENABLE()           do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_TIM17_CLK_ENABLE()           do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_SAI1_CLK_ENABLE()            do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_SAI2_CLK_ENABLE()            do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_DFSDM_CLK_ENABLE()           do { \
-                                                 __IO uint32_t tmpreg; \
-                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDMEN); \
-                                                 /* Delay after an RCC peripheral clock enabling */ \
-                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDMEN); \
-                                                 UNUSED(tmpreg); \
-                                               } while(0)
-
-#define __HAL_RCC_SYSCFG_CLK_DISABLE()         CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN)
-
-#define __HAL_RCC_SDMMC1_CLK_DISABLE()         CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN)
-
-#define __HAL_RCC_TIM1_CLK_DISABLE()           CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN)
-
-#define __HAL_RCC_SPI1_CLK_DISABLE()           CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN)
-
-#define __HAL_RCC_TIM8_CLK_DISABLE()           CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN)
-
-#define __HAL_RCC_USART1_CLK_DISABLE()         CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN)
-
-#define __HAL_RCC_TIM15_CLK_DISABLE()          CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN)
-
-#define __HAL_RCC_TIM16_CLK_DISABLE()          CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN)
-
-#define __HAL_RCC_TIM17_CLK_DISABLE()          CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN)
-
-#define __HAL_RCC_SAI1_CLK_DISABLE()           CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN)
-
-#define __HAL_RCC_SAI2_CLK_DISABLE()           CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN)
-
-#define __HAL_RCC_DFSDM_CLK_DISABLE()          CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDMEN)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status
-  * @brief  Check whether the AHB1 peripheral clock is enabled or not.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-
-#define __HAL_RCC_DMA1_IS_CLK_ENABLED()        (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != RESET)
-
-#define __HAL_RCC_DMA2_IS_CLK_ENABLED()        (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != RESET)
-
-#define __HAL_RCC_FLASH_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != RESET)
-
-#define __HAL_RCC_CRC_IS_CLK_ENABLED()         (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != RESET)
-
-#define __HAL_RCC_TSC_IS_CLK_ENABLED()         (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != RESET)
-
-#define __HAL_RCC_DMA1_IS_CLK_DISABLED()       (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == RESET)
-
-#define __HAL_RCC_DMA2_IS_CLK_DISABLED()       (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == RESET)
-
-#define __HAL_RCC_FLASH_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == RESET)
-
-#define __HAL_RCC_CRC_IS_CLK_DISABLED()        (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == RESET)
-
-#define __HAL_RCC_TSC_IS_CLK_DISABLED()        (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == RESET)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status
-  * @brief  Check whether the AHB2 peripheral clock is enabled or not.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-
-#define __HAL_RCC_GPIOA_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != RESET)
-
-#define __HAL_RCC_GPIOB_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET)
-
-#define __HAL_RCC_GPIOC_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET)
-
-#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != RESET)
-
-#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != RESET)
-
-#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != RESET)
-
-#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != RESET)
-
-#define __HAL_RCC_GPIOH_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != RESET)
-
-#if defined(USB_OTG_FS)
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) != RESET)
-#endif /* USB_OTG_FS */
-
-#define __HAL_RCC_ADC_IS_CLK_ENABLED()         (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != RESET)
-
-#if defined(AES)
-#define __HAL_RCC_AES_IS_CLK_ENABLED()         (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != RESET)
-#endif /* AES */
-
-#define __HAL_RCC_RNG_IS_CLK_ENABLED()         (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != RESET)
-
-#define __HAL_RCC_GPIOA_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == RESET)
-
-#define __HAL_RCC_GPIOB_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == RESET)
-
-#define __HAL_RCC_GPIOC_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == RESET)
-
-#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == RESET)
-
-#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == RESET)
-
-#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == RESET)
-
-#define __HAL_RCC_GPIOG_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == RESET)
-
-#define __HAL_RCC_GPIOH_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == RESET)
-
-#if defined(USB_OTG_FS)
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) == RESET)
-#endif /* USB_OTG_FS */
-
-#define __HAL_RCC_ADC_IS_CLK_DISABLED()        (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) == RESET)
-
-#if defined(AES)
-#define __HAL_RCC_AES_IS_CLK_DISABLED()        (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == RESET)
-#endif /* AES */
-
-#define __HAL_RCC_RNG_IS_CLK_DISABLED()        (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == RESET)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status
-  * @brief  Check whether the AHB3 peripheral clock is enabled or not.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-
-#define __HAL_RCC_FMC_IS_CLK_ENABLED()         (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != RESET)
-
-#define __HAL_RCC_QSPI_IS_CLK_ENABLED()        (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != RESET)
-
-#define __HAL_RCC_FMC_IS_CLK_DISABLED()        (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == RESET)
-
-#define __HAL_RCC_QSPI_IS_CLK_DISABLED()       (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == RESET)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status
-  * @brief  Check whether the APB1 peripheral clock is enabled or not.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-
-#define __HAL_RCC_TIM2_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != RESET)
-
-#define __HAL_RCC_TIM3_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != RESET)
-
-#define __HAL_RCC_TIM4_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != RESET)
-
-#define __HAL_RCC_TIM5_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != RESET)
-
-#define __HAL_RCC_TIM6_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != RESET)
-
-#define __HAL_RCC_TIM7_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != RESET)
-
-#if defined(LCD)
-#define __HAL_RCC_LCD_IS_CLK_ENABLED()         (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) != RESET)
-#endif /* LCD */
-
-#define __HAL_RCC_WWDG_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != RESET)
-
-#define __HAL_RCC_SPI2_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != RESET)
-
-#define __HAL_RCC_SPI3_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != RESET)
-
-#define __HAL_RCC_USART2_IS_CLK_ENABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != RESET)
-
-#define __HAL_RCC_USART3_IS_CLK_ENABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != RESET)
-
-#define __HAL_RCC_UART4_IS_CLK_ENABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != RESET)
-
-#define __HAL_RCC_UART5_IS_CLK_ENABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != RESET)
-
-#define __HAL_RCC_I2C1_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != RESET)
-
-#define __HAL_RCC_I2C2_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != RESET)
-
-#define __HAL_RCC_I2C3_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != RESET)
-
-#define __HAL_RCC_CAN1_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) != RESET)
-
-#define __HAL_RCC_PWR_IS_CLK_ENABLED()         (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != RESET)
-
-#define __HAL_RCC_DAC1_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) != RESET)
-
-#define __HAL_RCC_OPAMP_IS_CLK_ENABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) != RESET)
-
-#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != RESET)
-
-#define __HAL_RCC_LPUART1_IS_CLK_ENABLED()     (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != RESET)
-
-#define __HAL_RCC_SWPMI1_IS_CLK_ENABLED()      (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) != RESET)
-
-#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED()      (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != RESET)
-
-#define __HAL_RCC_TIM2_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == RESET)
-
-#define __HAL_RCC_TIM3_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == RESET)
-
-#define __HAL_RCC_TIM4_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == RESET)
-
-#define __HAL_RCC_TIM5_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == RESET)
-
-#define __HAL_RCC_TIM6_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == RESET)
-
-#define __HAL_RCC_TIM7_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == RESET)
-
-#if defined(LCD)
-#define __HAL_RCC_LCD_IS_CLK_DISABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) == RESET)
-#endif /* LCD */
-
-#define __HAL_RCC_WWDG_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == RESET)
-
-#define __HAL_RCC_SPI2_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == RESET)
-
-#define __HAL_RCC_SPI3_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == RESET)
-
-#define __HAL_RCC_USART2_IS_CLK_DISABLED()     (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == RESET)
-
-#define __HAL_RCC_USART3_IS_CLK_DISABLED()     (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == RESET)
-
-#define __HAL_RCC_UART4_IS_CLK_DISABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == RESET)
-
-#define __HAL_RCC_UART5_IS_CLK_DISABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == RESET)
-
-#define __HAL_RCC_I2C1_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == RESET)
-
-#define __HAL_RCC_I2C2_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == RESET)
-
-#define __HAL_RCC_I2C3_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == RESET)
-
-#define __HAL_RCC_CAN1_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) == RESET)
-
-#define __HAL_RCC_PWR_IS_CLK_DISABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == RESET)
-
-#define __HAL_RCC_DAC1_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) == RESET)
-
-#define __HAL_RCC_OPAMP_IS_CLK_DISABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) == RESET)
-
-#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED()     (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == RESET)
-
-#define __HAL_RCC_LPUART1_IS_CLK_DISABLED()    (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == RESET)
-
-#define __HAL_RCC_SWPMI1_IS_CLK_DISABLED()     (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) == RESET)
-
-#define __HAL_RCC_LPTIM2_IS_CLK_DISABLED()     (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == RESET)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status
-  * @brief  Check whether the APB2 peripheral clock is enabled or not.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-
-#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != RESET)
-
-#define __HAL_RCC_FIREWALL_IS_CLK_ENABLED()    (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN) != RESET)
-
-#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) != RESET)
-
-#define __HAL_RCC_TIM1_IS_CLK_ENABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != RESET)
-
-#define __HAL_RCC_SPI1_IS_CLK_ENABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != RESET)
-
-#define __HAL_RCC_TIM8_IS_CLK_ENABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != RESET)
-
-#define __HAL_RCC_USART1_IS_CLK_ENABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != RESET)
-
-#define __HAL_RCC_TIM15_IS_CLK_ENABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != RESET)
-
-#define __HAL_RCC_TIM16_IS_CLK_ENABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != RESET)
-
-#define __HAL_RCC_TIM17_IS_CLK_ENABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != RESET)
-
-#define __HAL_RCC_SAI1_IS_CLK_ENABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != RESET)
-
-#define __HAL_RCC_SAI2_IS_CLK_ENABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != RESET)
-
-#define __HAL_RCC_DFSDM_IS_CLK_ENABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDMEN) != RESET)
-
-#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED()     (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == RESET)
-
-#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED()     (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) == RESET)
-
-#define __HAL_RCC_TIM1_IS_CLK_DISABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == RESET)
-
-#define __HAL_RCC_SPI1_IS_CLK_DISABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == RESET)
-
-#define __HAL_RCC_TIM8_IS_CLK_DISABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == RESET)
-
-#define __HAL_RCC_USART1_IS_CLK_DISABLED()     (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == RESET)
-
-#define __HAL_RCC_TIM15_IS_CLK_DISABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == RESET)
-
-#define __HAL_RCC_TIM16_IS_CLK_DISABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == RESET)
-
-#define __HAL_RCC_TIM17_IS_CLK_DISABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == RESET)
-
-#define __HAL_RCC_SAI1_IS_CLK_DISABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == RESET)
-
-#define __HAL_RCC_SAI2_IS_CLK_DISABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == RESET)
-
-#define __HAL_RCC_DFSDM_IS_CLK_DISABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDMEN) == RESET)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset
-  * @brief  Force or release AHB1 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_AHB1_FORCE_RESET()           WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU)
-
-#define __HAL_RCC_DMA1_FORCE_RESET()           SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
-
-#define __HAL_RCC_DMA2_FORCE_RESET()           SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
-
-#define __HAL_RCC_FLASH_FORCE_RESET()          SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
-
-#define __HAL_RCC_CRC_FORCE_RESET()            SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
-
-#define __HAL_RCC_TSC_FORCE_RESET()            SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)
-
-#define __HAL_RCC_AHB1_RELEASE_RESET()         WRITE_REG(RCC->AHB1RSTR, 0x00000000U)
-
-#define __HAL_RCC_DMA1_RELEASE_RESET()         CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
-
-#define __HAL_RCC_DMA2_RELEASE_RESET()         CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
-
-#define __HAL_RCC_FLASH_RELEASE_RESET()        CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
-
-#define __HAL_RCC_CRC_RELEASE_RESET()          CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
-
-#define __HAL_RCC_TSC_RELEASE_RESET()          CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset
-  * @brief  Force or release AHB2 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_AHB2_FORCE_RESET()           WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFU)
-
-#define __HAL_RCC_GPIOA_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
-
-#define __HAL_RCC_GPIOB_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
-
-#define __HAL_RCC_GPIOC_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
-
-#define __HAL_RCC_GPIOD_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
-
-#define __HAL_RCC_GPIOE_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
-
-#define __HAL_RCC_GPIOF_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
-
-#define __HAL_RCC_GPIOG_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
-
-#define __HAL_RCC_GPIOH_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)
-
-#if defined(USB_OTG_FS)
-#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()     SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST)
-#endif /* USB_OTG_FS */
-
-#define __HAL_RCC_ADC_FORCE_RESET()            SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)
-
-#if defined(AES)
-#define __HAL_RCC_AES_FORCE_RESET()            SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
-#endif /* AES */
-
-#define __HAL_RCC_RNG_FORCE_RESET()            SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
-
-#define __HAL_RCC_AHB2_RELEASE_RESET()         WRITE_REG(RCC->AHB2RSTR, 0x00000000U)
-
-#define __HAL_RCC_GPIOA_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
-
-#define __HAL_RCC_GPIOB_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
-
-#define __HAL_RCC_GPIOC_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
-
-#define __HAL_RCC_GPIOD_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
-
-#define __HAL_RCC_GPIOE_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
-
-#define __HAL_RCC_GPIOF_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
-
-#define __HAL_RCC_GPIOG_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
-
-#define __HAL_RCC_GPIOH_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)
-
-#if defined(USB_OTG_FS)
-#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET()   CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST)
-#endif /* USB_OTG_FS */
-
-#define __HAL_RCC_ADC_RELEASE_RESET()          CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)
-
-#if defined(AES)
-#define __HAL_RCC_AES_RELEASE_RESET()          CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
-#endif /* AES */
-
-#define __HAL_RCC_RNG_RELEASE_RESET()          CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset
-  * @brief  Force or release AHB3 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_AHB3_FORCE_RESET()           WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFU)
-
-#define __HAL_RCC_FMC_FORCE_RESET()            SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
-
-#define __HAL_RCC_QSPI_FORCE_RESET()           SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
-
-#define __HAL_RCC_AHB3_RELEASE_RESET()         WRITE_REG(RCC->AHB3RSTR, 0x00000000U)
-
-#define __HAL_RCC_FMC_RELEASE_RESET()          CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
-
-#define __HAL_RCC_QSPI_RELEASE_RESET()         CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
-  * @brief  Force or release APB1 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_APB1_FORCE_RESET()           WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU)
-
-#define __HAL_RCC_TIM2_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
-
-#define __HAL_RCC_TIM3_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
-
-#define __HAL_RCC_TIM4_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
-
-#define __HAL_RCC_TIM5_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
-
-#define __HAL_RCC_TIM6_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
-
-#define __HAL_RCC_TIM7_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
-
-#if defined(LCD)
-#define __HAL_RCC_LCD_FORCE_RESET()            SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)
-#endif /* LCD */
-
-#define __HAL_RCC_SPI2_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
-
-#define __HAL_RCC_SPI3_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
-
-#define __HAL_RCC_USART2_FORCE_RESET()         SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
-
-#define __HAL_RCC_USART3_FORCE_RESET()         SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
-
-#define __HAL_RCC_UART4_FORCE_RESET()          SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
-
-#define __HAL_RCC_UART5_FORCE_RESET()          SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
-
-#define __HAL_RCC_I2C1_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
-
-#define __HAL_RCC_I2C2_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
-
-#define __HAL_RCC_I2C3_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
-
-#define __HAL_RCC_CAN1_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)
-
-#define __HAL_RCC_PWR_FORCE_RESET()            SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
-
-#define __HAL_RCC_DAC1_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)
-
-#define __HAL_RCC_OPAMP_FORCE_RESET()          SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)
-
-#define __HAL_RCC_LPTIM1_FORCE_RESET()         SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
-
-#define __HAL_RCC_LPUART1_FORCE_RESET()        SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
-
-#define __HAL_RCC_SWPMI1_FORCE_RESET()         SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)
-
-#define __HAL_RCC_LPTIM2_FORCE_RESET()         SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)
-
-#define __HAL_RCC_APB1_RELEASE_RESET()         WRITE_REG(RCC->APB1RSTR1, 0x00000000U)
-
-#define __HAL_RCC_TIM2_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
-
-#define __HAL_RCC_TIM3_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
-
-#define __HAL_RCC_TIM4_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
-
-#define __HAL_RCC_TIM5_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
-
-#define __HAL_RCC_TIM6_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
-
-#define __HAL_RCC_TIM7_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
-
-#if defined(LCD)
-#define __HAL_RCC_LCD_RELEASE_RESET()          CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)
-#endif /* LCD */
-
-#define __HAL_RCC_SPI2_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
-
-#define __HAL_RCC_SPI3_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
-
-#define __HAL_RCC_USART2_RELEASE_RESET()       CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
-
-#define __HAL_RCC_USART3_RELEASE_RESET()       CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
-
-#define __HAL_RCC_UART4_RELEASE_RESET()        CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
-
-#define __HAL_RCC_UART5_RELEASE_RESET()        CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
-
-#define __HAL_RCC_I2C1_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
-
-#define __HAL_RCC_I2C2_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
-
-#define __HAL_RCC_I2C3_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
-
-#define __HAL_RCC_CAN1_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)
-
-#define __HAL_RCC_PWR_RELEASE_RESET()          CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
-
-#define __HAL_RCC_DAC1_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)
-
-#define __HAL_RCC_OPAMP_RELEASE_RESET()        CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)
-
-#define __HAL_RCC_LPTIM1_RELEASE_RESET()       CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
-
-#define __HAL_RCC_LPUART1_RELEASE_RESET()      CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
-
-#define __HAL_RCC_SWPMI1_RELEASE_RESET()       CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)
-
-#define __HAL_RCC_LPTIM2_RELEASE_RESET()       CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
-  * @brief  Force or release APB2 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_APB2_FORCE_RESET()           WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU)
-
-#define __HAL_RCC_SYSCFG_FORCE_RESET()         SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
-
-#define __HAL_RCC_SDMMC1_FORCE_RESET()         SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)
-
-#define __HAL_RCC_TIM1_FORCE_RESET()           SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
-
-#define __HAL_RCC_SPI1_FORCE_RESET()           SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
-
-#define __HAL_RCC_TIM8_FORCE_RESET()           SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
-
-#define __HAL_RCC_USART1_FORCE_RESET()         SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
-
-#define __HAL_RCC_TIM15_FORCE_RESET()          SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
-
-#define __HAL_RCC_TIM16_FORCE_RESET()          SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
-
-#define __HAL_RCC_TIM17_FORCE_RESET()          SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
-
-#define __HAL_RCC_SAI1_FORCE_RESET()           SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
-
-#define __HAL_RCC_SAI2_FORCE_RESET()           SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
-
-#define __HAL_RCC_DFSDM_FORCE_RESET()          SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDMRST)
-
-#define __HAL_RCC_APB2_RELEASE_RESET()         WRITE_REG(RCC->APB2RSTR, 0x00000000U)
-
-#define __HAL_RCC_SYSCFG_RELEASE_RESET()       CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
-
-#define __HAL_RCC_SDMMC1_RELEASE_RESET()       CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)
-
-#define __HAL_RCC_TIM1_RELEASE_RESET()         CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
-
-#define __HAL_RCC_SPI1_RELEASE_RESET()         CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
-
-#define __HAL_RCC_TIM8_RELEASE_RESET()         CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
-
-#define __HAL_RCC_USART1_RELEASE_RESET()       CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
-
-#define __HAL_RCC_TIM15_RELEASE_RESET()        CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
-
-#define __HAL_RCC_TIM16_RELEASE_RESET()        CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
-
-#define __HAL_RCC_TIM17_RELEASE_RESET()        CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
-
-#define __HAL_RCC_SAI1_RELEASE_RESET()         CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
-
-#define __HAL_RCC_SAI2_RELEASE_RESET()         CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
-
-#define __HAL_RCC_DFSDM_RELEASE_RESET()        CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDMRST)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable
-  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-
-#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
-
-#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
-
-#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
-
-#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
-
-#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
-
-#define __HAL_RCC_TSC_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
-
-#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
-
-#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
-
-#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
-
-#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
-
-#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
-
-#define __HAL_RCC_TSC_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable
-  * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-
-#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
-
-#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
-
-#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
-
-#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
-
-#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
-
-#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
-
-#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
-
-#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)
-
-#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
-
-#if defined(USB_OTG_FS)
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN)
-#endif /* USB_OTG_FS */
-
-#define __HAL_RCC_ADC_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)
-
-#if defined(AES)
-#define __HAL_RCC_AES_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
-#endif /* AES */
-
-#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
-
-#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
-
-#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
-
-#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
-
-#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
-
-#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
-
-#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
-
-#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
-
-#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)
-
-#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
-
-#if defined(USB_OTG_FS)
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN)
-#endif /* USB_OTG_FS */
-
-#define __HAL_RCC_ADC_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)
-
-#if defined(AES)
-#define __HAL_RCC_AES_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
-#endif /* AES */
-
-#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable
-  * @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-
-#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
-
-#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
-
-#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
-
-#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
-  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-
-#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
-
-#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
-
-#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
-
-#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
-
-#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
-
-#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
-
-#if defined(LCD)
-#define __HAL_RCC_LCD_CLK_SLEEP_ENABLE()       SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)
-#endif /* LCD */
-
-#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
-
-#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
-
-#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
-
-#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
-
-#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
-
-#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
-
-#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
-
-#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
-
-#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
-
-#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
-
-#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)
-
-#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE()       SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
-
-#define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)
-
-#define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)
-
-#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
-
-#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE()   SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
-
-#define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)
-
-#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)
-
-#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
-
-#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
-
-#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
-
-#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
-
-#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
-
-#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
-
-#if defined(LCD)
-#define __HAL_RCC_LCD_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)
-#endif /* LCD */
-
-#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
-
-#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
-
-#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
-
-#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
-
-#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
-
-#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
-
-#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
-
-#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
-
-#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
-
-#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
-
-#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)
-
-#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
-
-#define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)
-
-#define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)
-
-#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
-
-#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
-
-#define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)
-
-#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
-  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-
-#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
-
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)
-
-#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
-
-#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
-
-#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
-
-#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
-
-#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
-
-#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
-
-#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
-
-#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
-
-#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)
-
-#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDMSMEN)
-
-#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
-
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)
-
-#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
-
-#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
-
-#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
-
-#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
-
-#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
-
-#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
-
-#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
-
-#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
-
-#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)
-
-#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDMSMEN)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status
-  * @brief  Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-
-#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != RESET)
-
-#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != RESET)
-
-#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != RESET)
-
-#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != RESET)
-
-#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != RESET)
-
-#define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != RESET)
-
-#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == RESET)
-
-#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == RESET)
-
-#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == RESET)
-
-#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == RESET)
-
-#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == RESET)
-
-#define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == RESET)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status
-  * @brief  Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-
-#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != RESET)
-
-#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != RESET)
-
-#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != RESET)
-
-#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != RESET)
-
-#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != RESET)
-
-#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != RESET)
-
-#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != RESET)
-
-#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != RESET)
-
-#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != RESET)
-
-#if defined(USB_OTG_FS)
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) != RESET)
-#endif /* USB_OTG_FS */
-
-#define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != RESET)
-
-#if defined(AES)
-#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != RESET)
-#endif /* AES */
-
-#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != RESET)
-
-#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == RESET)
-
-#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == RESET)
-
-#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == RESET)
-
-#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == RESET)
-
-#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == RESET)
-
-#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == RESET)
-
-#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == RESET)
-
-#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == RESET)
-
-#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == RESET)
-
-#if defined(USB_OTG_FS)
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) == RESET)
-#endif /* USB_OTG_FS */
-
-#define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == RESET)
-
-#if defined(AES)
-#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == RESET)
-#endif /* AES */
-
-#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == RESET)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status
-  * @brief  Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-
-#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != RESET)
-
-#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != RESET)
-
-#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == RESET)
-
-#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == RESET)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status
-  * @brief  Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-
-#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != RESET)
-
-#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != RESET)
-
-#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != RESET)
-
-#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != RESET)
-
-#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != RESET)
-
-#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != RESET)
-
-#if defined(LCD)
-#define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED()       (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != RESET)
-#endif /* LCD */
-
-#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != RESET)
-
-#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != RESET)
-
-#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != RESET)
-
-#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != RESET)
-
-#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != RESET)
-
-#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != RESET)
-
-#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != RESET)
-
-#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != RESET)
-
-#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != RESET)
-
-#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != RESET)
-
-#define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) != RESET)
-
-#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED()       (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != RESET)
-
-#define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) != RESET)
-
-#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) != RESET)
-
-#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != RESET)
-
-#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != RESET)
-
-#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) != RESET)
-
-#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != RESET)
-
-#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == RESET)
-
-#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == RESET)
-
-#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == RESET)
-
-#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == RESET)
-
-#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == RESET)
-
-#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == RESET)
-
-#if defined(LCD)
-#define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == RESET)
-#endif /* LCD */
-
-#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == RESET)
-
-#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == RESET)
-
-#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == RESET)
-
-#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == RESET)
-
-#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == RESET)
-
-#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == RESET)
-
-#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == RESET)
-
-#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == RESET)
-
-#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == RESET)
-
-#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == RESET)
-
-#define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) == RESET)
-
-#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == RESET)
-
-#define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) == RESET)
-
-#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) == RESET)
-
-#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == RESET)
-
-#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == RESET)
-
-#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) == RESET)
-
-#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == RESET)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status
-  * @brief  Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-
-#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != RESET)
-
-#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) != RESET)
-
-#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != RESET)
-
-#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != RESET)
-
-#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != RESET)
-
-#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != RESET)
-
-#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != RESET)
-
-#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != RESET)
-
-#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != RESET)
-
-#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != RESET)
-
-#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) != RESET)
-
-#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDMSMEN) != RESET)
-
-#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == RESET)
-
-#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) == RESET)
-
-#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == RESET)
-
-#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == RESET)
-
-#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == RESET)
-
-#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == RESET)
-
-#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == RESET)
-
-#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == RESET)
-
-#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == RESET)
-
-#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == RESET)
-
-#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) == RESET)
-
-#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDMSMEN) == RESET)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset
-  * @{   
-  */ 
-
-/** @brief  Macros to force or release the Backup domain reset.
-  * @note   This function resets the RTC peripheral (including the backup registers)
-  *         and the RTC clock source selection in RCC_CSR register.
-  * @note   The BKPSRAM is not affected by this reset.
-  * @retval None
-  */
-#define __HAL_RCC_BACKUPRESET_FORCE()   SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
-
-#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
-  * @{   
-  */ 
-
-/** @brief  Macros to enable or disable the RTC clock.
-  * @note   As the RTC is in the Backup domain and write access is denied to
-  *         this domain after reset, you have to enable write access using
-  *         HAL_PWR_EnableBkUpAccess() function before to configure the RTC
-  *         (to be done once after reset).
-  * @note   These macros must be used after the RTC clock source was selected.
-  * @retval None
-  */
-#define __HAL_RCC_RTC_ENABLE()         SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
-
-#define __HAL_RCC_RTC_DISABLE()        CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
-
-/**
-  * @}
-  */
-
-/** @brief  Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI).
-  * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
-  *         It is used (enabled by hardware) as system clock source after startup
-  *         from Reset, wakeup from STOP and STANDBY mode, or in case of failure
-  *         of the HSE used directly or indirectly as system clock (if the Clock
-  *         Security System CSS is enabled).
-  * @note   HSI can not be stopped if it is used as system clock source. In this case,
-  *         you have to select another source of the system clock then stop the HSI.
-  * @note   After enabling the HSI, the application software should wait on HSIRDY
-  *         flag to be set indicating that HSI clock is stable and can be used as
-  *         system clock source.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
-  *         clock cycles.
-  * @retval None
-  */
-#define __HAL_RCC_HSI_ENABLE()  SET_BIT(RCC->CR, RCC_CR_HSION)
-
-#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
-
-/** @brief  Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value.
-  * @note   The calibration is used to compensate for the variations in voltage
-  *         and temperature that influence the frequency of the internal HSI RC.
-  * @param  __HSICALIBRATIONVALUE__: specifies the calibration trimming value
-  *         (default is RCC_HSICALIBRATION_DEFAULT).
-  *         This parameter must be a number between 0 and 31.
-  * @retval None
-  */
-#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \
-                  MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_ICSCR_HSITRIM))
-
-/**
-  * @brief    Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI)
-  *           in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup.
-  * @note     The enable of this function has not effect on the HSION bit.
-  *           This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-#define __HAL_RCC_HSIAUTOMATIC_START_ENABLE()   SET_BIT(RCC->CR, RCC_CR_HSIASFS)
-
-#define __HAL_RCC_HSIAUTOMATIC_START_DISABLE()  CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS)
-
-/**
-  * @brief    Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
-  *           in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
-  * @note     Keeping the HSI ON in STOP mode allows to avoid slowing down the communication
-  *           speed because of the HSI startup time.
-  * @note     The enable of this function has not effect on the HSION bit.
-  *           This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-#define __HAL_RCC_HSISTOP_ENABLE()     SET_BIT(RCC->CR, RCC_CR_HSIKERON)
-
-#define __HAL_RCC_HSISTOP_DISABLE()    CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
-
-/**
-  * @brief  Macros to enable or disable the Internal Multi Speed oscillator (MSI).
-  * @note     The MSI is stopped by hardware when entering STOP and STANDBY modes.
-  *           It is used (enabled by hardware) as system clock source after
-  *           startup from Reset, wakeup from STOP and STANDBY mode, or in case
-  *           of failure of the HSE used directly or indirectly as system clock
-  *           (if the Clock Security System CSS is enabled).
-  * @note     MSI can not be stopped if it is used as system clock source.
-  *           In this case, you have to select another source of the system
-  *           clock then stop the MSI.
-  * @note     After enabling the MSI, the application software should wait on
-  *           MSIRDY flag to be set indicating that MSI clock is stable and can
-  *           be used as system clock source.
-  * @note   When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
-  *         clock cycles.
-  * @retval None
-  */
-#define __HAL_RCC_MSI_ENABLE()  SET_BIT(RCC->CR, RCC_CR_MSION)
-
-#define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION)
-
-/** @brief  Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
-  * @note   The calibration is used to compensate for the variations in voltage
-  *         and temperature that influence the frequency of the internal MSI RC.
-  *         Refer to the Application Note AN3300 for more details on how to
-  *         calibrate the MSI.
-  * @param  __MSICALIBRATIONVALUE__: specifies the calibration trimming value
-  *         (default is RCC_MSICALIBRATION_DEFAULT).
-  *         This parameter must be a number between 0 and 255.
-  * @retval None
-  */
-#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \
-                  MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(__MSICALIBRATIONVALUE__) << 8)
-
-/**
-  * @brief  Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode
-  * @note     After restart from Reset , the MSI clock is around 4 MHz.
-  *           After stop the startup clock can be MSI (at any of its possible
-  *           frequencies, the one that was used before entering stop mode) or HSI.
-  *          After Standby its frequency can be selected between 4 possible values
-  *          (1, 2, 4 or 8 MHz).
-  * @note     MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready
-  *          (MSIRDY=1).
-  * @note    The MSI clock range after reset can be modified on the fly.
-  * @param  __MSIRANGEVALUE__: specifies the MSI clock range.
-  *         This parameter must be one of the following values:
-  *            @arg @ref RCC_MSIRANGE_0  MSI clock is around 100 KHz
-  *            @arg @ref RCC_MSIRANGE_1  MSI clock is around 200 KHz
-  *            @arg @ref RCC_MSIRANGE_2  MSI clock is around 400 KHz
-  *            @arg @ref RCC_MSIRANGE_3  MSI clock is around 800 KHz
-  *            @arg @ref RCC_MSIRANGE_4  MSI clock is around 1 MHz
-  *            @arg @ref RCC_MSIRANGE_5  MSI clock is around 2MHz
-  *            @arg @ref RCC_MSIRANGE_6  MSI clock is around 4MHz (default after Reset)
-  *            @arg @ref RCC_MSIRANGE_7  MSI clock is around 8  MHz
-  *            @arg @ref RCC_MSIRANGE_8  MSI clock is around 16 MHz
-  *            @arg @ref RCC_MSIRANGE_9  MSI clock is around 24 MHz
-  *            @arg @ref RCC_MSIRANGE_10  MSI clock is around 32 MHz
-  *            @arg @ref RCC_MSIRANGE_11  MSI clock is around 48 MHz
-  * @retval None
-  */
-#define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) \
-                  do {                                                         \
-                    SET_BIT(RCC->CR, RCC_CR_MSIRGSEL);                         \
-                    MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, (__MSIRANGEVALUE__)); \
-                  } while(0)
-
-/**
-  * @brief  Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode
-  *         After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz).
-  * @param  __MSIRANGEVALUE__: specifies the MSI clock range.
-  *         This parameter must be one of the following values:
-  *            @arg @ref RCC_MSIRANGE_4  MSI clock is around 1 MHz
-  *            @arg @ref RCC_MSIRANGE_5  MSI clock is around 2MHz
-  *            @arg @ref RCC_MSIRANGE_6  MSI clock is around 4MHz (default after Reset)
-  *            @arg @ref RCC_MSIRANGE_7  MSI clock is around 8  MHz
-  * @retval None
-  */
-#define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) \
-                  MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U)
-
-/** @brief  Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode
-  * @retval MSI clock range.
-  *         This parameter must be one of the following values:
-  *            @arg @ref RCC_MSIRANGE_0  MSI clock is around 100 KHz
-  *            @arg @ref RCC_MSIRANGE_1  MSI clock is around 200 KHz
-  *            @arg @ref RCC_MSIRANGE_2  MSI clock is around 400 KHz
-  *            @arg @ref RCC_MSIRANGE_3  MSI clock is around 800 KHz
-  *            @arg @ref RCC_MSIRANGE_4  MSI clock is around 1 MHz
-  *            @arg @ref RCC_MSIRANGE_5  MSI clock is around 2MHz
-  *            @arg @ref RCC_MSIRANGE_6  MSI clock is around 4MHz (default after Reset)
-  *            @arg @ref RCC_MSIRANGE_7  MSI clock is around 8  MHz
-  *            @arg @ref RCC_MSIRANGE_8  MSI clock is around 16 MHz
-  *            @arg @ref RCC_MSIRANGE_9  MSI clock is around 24 MHz
-  *            @arg @ref RCC_MSIRANGE_10  MSI clock is around 32 MHz
-  *            @arg @ref RCC_MSIRANGE_11  MSI clock is around 48 MHz
-  */
-#define __HAL_RCC_GET_MSI_RANGE()                                              \
-                  ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != RESET) ?             \
-                   (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE)) :            \
-                   (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4))
-
-/** @brief  Macros to enable or disable the Internal Low Speed oscillator (LSI).
-  * @note   After enabling the LSI, the application software should wait on
-  *         LSIRDY flag to be set indicating that LSI clock is stable and can
-  *         be used to clock the IWDG and/or the RTC.
-  * @note   LSI can not be disabled if the IWDG is running.
-  * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
-  *         clock cycles.
-  * @retval None
-  */
-#define __HAL_RCC_LSI_ENABLE()         SET_BIT(RCC->CSR, RCC_CSR_LSION)
-
-#define __HAL_RCC_LSI_DISABLE()        CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
-
-/**
-  * @brief  Macro to configure the External High Speed oscillator (HSE).
-  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
-  *         supported by this macro. User should request a transition to HSE Off
-  *         first and then HSE On or HSE Bypass.
-  * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
-  *         software should wait on HSERDY flag to be set indicating that HSE clock
-  *         is stable and can be used to clock the PLL and/or system clock.
-  * @note   HSE state can not be changed if it is used directly or through the
-  *         PLL as system clock. In this case, you have to select another source
-  *         of the system clock then change the HSE state (ex. disable it).
-  * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
-  * @note   This function reset the CSSON bit, so if the clock security system(CSS)
-  *         was previously enabled you have to enable it again after calling this
-  *         function.
-  * @param  __STATE__: specifies the new state of the HSE.
-  *         This parameter can be one of the following values:
-  *            @arg @ref RCC_HSE_OFF  Turn OFF the HSE oscillator, HSERDY flag goes low after
-  *                              6 HSE oscillator clock cycles.
-  *            @arg @ref RCC_HSE_ON  Turn ON the HSE oscillator.
-  *            @arg @ref RCC_HSE_BYPASS  HSE oscillator bypassed with external clock.
-  * @retval None
-  */
-#define __HAL_RCC_HSE_CONFIG(__STATE__)                      \
-                    do {                                     \
-                      if((__STATE__) == RCC_HSE_ON)          \
-                      {                                      \
-                        SET_BIT(RCC->CR, RCC_CR_HSEON);      \
-                      }                                      \
-                      else if((__STATE__) == RCC_HSE_BYPASS) \
-                      {                                      \
-                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);    \
-                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);     \
-                        SET_BIT(RCC->CR, RCC_CR_HSEON);      \
-                      }                                      \
-                      else                                   \
-                      {                                      \
-                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);    \
-                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);   \
-                      }                                      \
-                    } while(0)
-
-/**
-  * @brief  Macro to configure the External Low Speed oscillator (LSE).
-  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
-  *         supported by this macro. User should request a transition to LSE Off 
-  *         first and then LSE On or LSE Bypass.  
-  * @note   As the LSE is in the Backup domain and write access is denied to
-  *         this domain after reset, you have to enable write access using
-  *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
-  *         (to be done once after reset).
-  * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
-  *         software should wait on LSERDY flag to be set indicating that LSE clock
-  *         is stable and can be used to clock the RTC.
-  * @param  __STATE__: specifies the new state of the LSE.
-  *         This parameter can be one of the following values:
-  *            @arg @ref RCC_LSE_OFF  Turn OFF the LSE oscillator, LSERDY flag goes low after
-  *                              6 LSE oscillator clock cycles.
-  *            @arg @ref RCC_LSE_ON  Turn ON the LSE oscillator.
-  *            @arg @ref RCC_LSE_BYPASS  LSE oscillator bypassed with external clock.
-  * @retval None
-  */
-#define __HAL_RCC_LSE_CONFIG(__STATE__)                        \
-                    do {                                       \
-                      if((__STATE__) == RCC_LSE_ON)            \
-                      {                                        \
-                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
-                      }                                        \
-                      else if((__STATE__) == RCC_LSE_OFF)      \
-                      {                                        \
-                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \
-                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
-                      }                                        \
-                      else if((__STATE__) == RCC_LSE_BYPASS)   \
-                      {                                        \
-                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \
-                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);   \
-                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
-                      }                                        \
-                      else                                     \
-                      {                                        \
-                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \
-                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
-                      }                                        \
-                    } while(0)
-
-/** @brief  Macros to configure the RTC clock (RTCCLK).
-  * @note   As the RTC clock configuration bits are in the Backup domain and write
-  *         access is denied to this domain after reset, you have to enable write
-  *         access using the Power Backup Access macro before to configure
-  *         the RTC clock source (to be done once after reset).
-  * @note   Once the RTC clock is configured it cannot be changed unless the
-  *         Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by
-  *         a Power On Reset (POR).
-  *
-  * @param  __RTC_CLKSOURCE__: specifies the RTC clock source.
-  *         This parameter can be one of the following values:
-  *            @arg @ref RCC_RTCCLKSOURCE_LSE  LSE selected as RTC clock.
-  *            @arg @ref RCC_RTCCLKSOURCE_LSI  LSI selected as RTC clock.
-  *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32  HSE clock divided by 32 selected
-  *
-  * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
-  *         work in STOP and STANDBY modes, and can be used as wakeup source.
-  *         However, when the HSE clock is used as RTC clock source, the RTC
-  *         cannot be used in STOP and STANDBY modes.
-  * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
-  *         RTC clock source).
-  * @retval None
-  */
-#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__)  \
-                  MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
-
-
-/** @brief  Macro to get the RTC clock source.
-  * @retval The returned value can be one of the following:
-  *            @arg @ref RCC_RTCCLKSOURCE_LSE  LSE selected as RTC clock.
-  *            @arg @ref RCC_RTCCLKSOURCE_LSI  LSI selected as RTC clock.
-  *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32  HSE clock divided by 32 selected
-  */
-#define  __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
-
-/** @brief  Macros to enable or disable the main PLL.
-  * @note   After enabling the main PLL, the application software should wait on
-  *         PLLRDY flag to be set indicating that PLL clock is stable and can
-  *         be used as system clock source.
-  * @note   The main PLL can not be disabled if it is used as system clock source
-  * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
-  * @retval None
-  */
-#define __HAL_RCC_PLL_ENABLE()         SET_BIT(RCC->CR, RCC_CR_PLLON)
-
-#define __HAL_RCC_PLL_DISABLE()        CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
-
-/** @brief  Macro to configure the PLL clock source.
-  * @note   This function must be used only when the main PLL is disabled.
-  * @param  __PLLSOURCE__: specifies the PLL entry clock source.
-  *         This parameter can be one of the following values:
-  *            @arg @ref RCC_PLLSOURCE_NONE  No clock selected as PLL clock entry
-  *            @arg @ref RCC_PLLSOURCE_MSI  MSI oscillator clock selected as PLL clock entry
-  *            @arg @ref RCC_PLLSOURCE_HSI  HSI oscillator clock selected as PLL clock entry
-  *            @arg @ref RCC_PLLSOURCE_HSE  HSE oscillator clock selected as PLL clock entry
-  * @note   This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).
-  * @retval None
-  *      
-  */
-#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \
-                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
-
-/** @brief  Macro to configure the PLL multiplication factor.
-  * @note   This function must be used only when the main PLL is disabled.
-  * @param  __PLLM__: specifies the division factor for PLL VCO input clock
-  *         This parameter must be a number between Min_Data = 1 and Max_Data = 8.
-  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
-  *         frequency ranges from 4 to 16 MHz. It is recommended to select a frequency
-  *         of 16 MHz to limit PLL jitter.
-  * @retval None
-  *      
-  */
-#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \
-                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << 4U)
-
-/**
-  * @brief  Macro to configure the main PLL clock source, multiplication and division factors.
-  * @note   This function must be used only when the main PLL is disabled.
-  *
-  * @param  __PLLSOURCE__: specifies the PLL entry clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_PLLSOURCE_NONE  No clock selected as PLL clock entry
-  *            @arg @ref RCC_PLLSOURCE_MSI  MSI oscillator clock selected as PLL clock entry
-  *            @arg @ref RCC_PLLSOURCE_HSI  HSI oscillator clock selected as PLL clock entry
-  *            @arg @ref RCC_PLLSOURCE_HSE  HSE oscillator clock selected as PLL clock entry
-  * @note   This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).
-  *
-  * @param  __PLLM__: specifies the division factor for PLL VCO input clock.
-  *          This parameter must be a number between 1 and 8.
-  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
-  *         frequency ranges from 4 to 16 MHz. It is recommended to select a frequency
-  *         of 16 MHz to limit PLL jitter.
-  *
-  * @param  __PLLN__: specifies the multiplication factor for PLL VCO output clock.
-  *          This parameter must be a number between 8 and 86.
-  * @note   You have to set the PLLN parameter correctly to ensure that the VCO
-  *         output frequency is between 64 and 344 MHz.
-  *
-  * @param  __PLLP__: specifies the division factor for SAI clock.
-  *          This parameter must be a number in the range (7 or 17).
-  *
-  * @param  __PLLQ__: specifies the division factor for OTG FS, SDMMC1 and RNG clocks.
-  *          This parameter must be in the range (2, 4, 6 or 8).
-  * @note   If the USB OTG FS is used in your application, you have to set the
-  *         PLLQ parameter correctly to have 48 MHz clock for the USB. However,
-  *         the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work
-  *         correctly.
-  * @param  __PLLR__: specifies the division factor for the main system clock.
-  * @note   You have to set the PLLR parameter correctly to not exceed 80MHZ.
-  *          This parameter must be in the range (2, 4, 6 or 8).
-  * @retval None
-  */
-#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
-                  (RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | (uint32_t)(((__PLLP__) >> 4U ) << 17U) | \
-                   (uint32_t)(__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U))
-
-/** @brief  Macro to get the oscillator used as PLL clock source.
-  * @retval The oscillator used as PLL clock source. The returned value can be one
-  *         of the following:
-  *              - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.
-  *              - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source.
-  *              - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
-  *              - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
-  */
-#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
-
-/**
-  * @brief  Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
-  * @note   Enabling/disabling clock outputs RCC_PLL_SAI3CLK and RCC_PLL_48M1CLK can be done at anytime 
-  *         without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot  
-  *         be stopped if used as System Clock.
-  * @param  __PLLCLOCKOUT__: specifies the PLL clock to be output.
-  *          This parameter can be one or a combination of the following values:
-  *            @arg @ref RCC_PLL_SAI3CLK  This clock is used to generate an accurate clock to achieve
-  *                                   high-quality audio performance on SAI interface in case.
-  *            @arg @ref RCC_PLL_48M1CLK  This Clock is used to generate the clock for the USB OTG FS (48 MHz),
-  *                                   the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
-  *            @arg @ref RCC_PLL_SYSCLK  This Clock is used to generate the high speed system clock (up to 80MHz)
-  * @retval None
-  */
-#define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__)   SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
-
-#define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__)  CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
-
-/**
-  * @brief  Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
-  * @param  __PLLCLOCKOUT__: specifies the output PLL clock to be checked.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_PLL_SAI3CLK  This clock is used to generate an accurate clock to achieve
-  *                                   high-quality audio performance on SAI interface in case.
-  *            @arg @ref RCC_PLL_48M1CLK  This Clock is used to generate the clock for the USB OTG FS (48 MHz),
-  *                                   the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
-  *            @arg @ref RCC_PLL_SYSCLK  This Clock is used to generate the high speed system clock (up to 80MHz)
-  * @retval SET / RESET
-  */
-#define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__)  READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
-
-/**
-  * @brief  Macro to configure the system clock source.
-  * @param  __SYSCLKSOURCE__: specifies the system clock source.
-  *          This parameter can be one of the following values:
-  *              - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source.
-  *              - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
-  *              - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
-  *              - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
-  * @retval None
-  */
-#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
-                  MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
-
-/** @brief  Macro to get the clock source used as system clock.
-  * @retval The clock source used as system clock. The returned value can be one
-  *         of the following:
-  *              - RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock.
-  *              - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
-  *              - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
-  *              - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
-  */
-#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
-
-/**
-  * @brief  Macro to configure the External Low Speed oscillator (LSE) drive capability.
-  * @note   As the LSE is in the Backup domain and write access is denied to
-  *         this domain after reset, you have to enable write access using
-  *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
-  *         (to be done once after reset).
-  * @param  __LSEDRIVE__: specifies the new state of the LSE drive capability.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_LSEDRIVE_LOW  LSE oscillator low drive capability.
-  *            @arg @ref RCC_LSEDRIVE_MEDIUMLOW  LSE oscillator medium low drive capability.
-  *            @arg @ref RCC_LSEDRIVE_MEDIUMHIGH  LSE oscillator medium high drive capability.
-  *            @arg @ref RCC_LSEDRIVE_HIGH  LSE oscillator high drive capability.
-  * @retval None
-  */
-#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
-                  MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__))
-
-/**
-  * @brief  Macro to configure the wake up from stop clock.
-  * @param  __STOPWUCLK__: specifies the clock source used after wake up from stop.
-  *         This parameter can be one of the following values:
-  *            @arg @ref RCC_STOP_WAKEUPCLOCK_MSI  MSI selected as system clock source
-  *            @arg @ref RCC_STOP_WAKEUPCLOCK_HSI  HSI selected as system clock source
-  * @retval None
-  */
-#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \
-                  MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__))
-
-
-/** @brief  Macro to configure the MCO clock.
-  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_MCO1SOURCE_NOCLOCK  MCO output disabled
-  *            @arg @ref RCC_MCO1SOURCE_SYSCLK  System  clock selected as MCO source
-  *            @arg @ref RCC_MCO1SOURCE_MSI  MSI clock selected as MCO source
-  *            @arg @ref RCC_MCO1SOURCE_HSI  HSI clock selected as MCO source
-  *            @arg @ref RCC_MCO1SOURCE_HSE  HSE clock selected as MCO sourcee
-  *            @arg @ref RCC_MCO1SOURCE_PLLCLK  Main PLL clock selected as MCO source
-  *            @arg @ref RCC_MCO1SOURCE_LSI  LSI clock selected as MCO source
-  *            @arg @ref RCC_MCO1SOURCE_LSE  LSE clock selected as MCO source
-  * @param  __MCODIV__ specifies the MCO clock prescaler.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_MCODIV_1   MCO clock source is divided by 1
-  *            @arg @ref RCC_MCODIV_2   MCO clock source is divided by 2
-  *            @arg @ref RCC_MCODIV_4   MCO clock source is divided by 4
-  *            @arg @ref RCC_MCODIV_8   MCO clock source is divided by 8
-  *            @arg @ref RCC_MCODIV_16  MCO clock source is divided by 16
-  */
-#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
-                 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
-
-/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
-  * @brief macros to manage the specified RCC Flags and interrupts.
-  * @{
-  */
-
-/** @brief  Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
-  *         the selected interrupts).
-  * @param  __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
-  *         This parameter can be any combination of the following values:
-  *            @arg @ref RCC_IT_LSIRDY  LSI ready interrupt
-  *            @arg @ref RCC_IT_LSERDY  LSE ready interrupt
-  *            @arg @ref RCC_IT_MSIRDY  HSI ready interrupt
-  *            @arg @ref RCC_IT_HSIRDY  HSI ready interrupt
-  *            @arg @ref RCC_IT_HSERDY  HSE ready interrupt
-  *            @arg @ref RCC_IT_PLLRDY  Main PLL ready interrupt
-  *            @arg @ref RCC_IT_PLLSAI1RDY  PLLSAI1 ready interrupt
-  *            @arg @ref RCC_IT_PLLSAI2RDY  PLLSAI2 ready interrupt
-  *            @arg @ref RCC_IT_LSECSS  LSE Clock security system interrupt
-  * @retval None
-  */
-#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
-
-/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
-  *        the selected interrupts).
-  * @param  __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
-  *         This parameter can be any combination of the following values:
-  *            @arg @ref RCC_IT_LSIRDY  LSI ready interrupt
-  *            @arg @ref RCC_IT_LSERDY  LSE ready interrupt
-  *            @arg @ref RCC_IT_MSIRDY  HSI ready interrupt
-  *            @arg @ref RCC_IT_HSIRDY  HSI ready interrupt
-  *            @arg @ref RCC_IT_HSERDY  HSE ready interrupt
-  *            @arg @ref RCC_IT_PLLRDY  Main PLL ready interrupt
-  *            @arg @ref RCC_IT_PLLSAI1RDY  PLLSAI1 ready interrupt
-  *            @arg @ref RCC_IT_PLLSAI2RDY  PLLSAI2 ready interrupt
-  *            @arg @ref RCC_IT_LSECSS  LSE Clock security system interrupt
-  * @retval None
-  */
-#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
-
-/** @brief  Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
-  *         bits to clear the selected interrupt pending bits.
-  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
-  *         This parameter can be any combination of the following values:
-  *            @arg @ref RCC_IT_LSIRDY  LSI ready interrupt
-  *            @arg @ref RCC_IT_LSERDY  LSE ready interrupt
-  *            @arg @ref RCC_IT_MSIRDY  MSI ready interrupt
-  *            @arg @ref RCC_IT_HSIRDY  HSI ready interrupt
-  *            @arg @ref RCC_IT_HSERDY  HSE ready interrupt
-  *            @arg @ref RCC_IT_PLLRDY  Main PLL ready interrupt
-  *            @arg @ref RCC_IT_PLLSAI1RDY  PLLSAI1 ready interrupt
-  *            @arg @ref RCC_IT_PLLSAI2RDY  PLLSAI2 ready interrupt
-  *            @arg @ref RCC_IT_CSS  HSE Clock security system interrupt
-  *            @arg @ref RCC_IT_LSECSS  LSE Clock security system interrupt
-  * @retval None
-  */
-#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
-
-/** @brief  Check whether the RCC interrupt has occurred or not.
-  * @param  __INTERRUPT__: specifies the RCC interrupt source to check.
-  *         This parameter can be one of the following values:
-  *            @arg @ref RCC_IT_LSIRDY  LSI ready interrupt
-  *            @arg @ref RCC_IT_LSERDY  LSE ready interrupt
-  *            @arg @ref RCC_IT_MSIRDY  MSI ready interrupt
-  *            @arg @ref RCC_IT_HSIRDY  HSI ready interrupt
-  *            @arg @ref RCC_IT_HSERDY  HSE ready interrupt
-  *            @arg @ref RCC_IT_PLLRDY  Main PLL ready interrupt
-  *            @arg @ref RCC_IT_PLLSAI1RDY  PLLSAI1 ready interrupt
-  *            @arg @ref RCC_IT_PLLSAI2RDY  PLLSAI2 ready interrupt
-  *            @arg @ref RCC_IT_CSS  HSE Clock security system interrupt
-  *            @arg @ref RCC_IT_LSECSS  LSE Clock security system interrupt
-  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
-  */
-#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/** @brief Set RMVF bit to clear the reset flags.
-  *        The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST,
-  *        RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
-  * @retval None
- */
-#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
-
-/** @brief  Check whether the selected RCC flag is set or not.
-  * @param  __FLAG__: specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg @ref RCC_FLAG_MSIRDY  MSI oscillator clock ready
-  *            @arg @ref RCC_FLAG_HSIRDY  HSI oscillator clock ready
-  *            @arg @ref RCC_FLAG_HSERDY  HSE oscillator clock ready
-  *            @arg @ref RCC_FLAG_PLLRDY  Main PLL clock ready
-  *            @arg @ref RCC_FLAG_PLLSAI1RDY  PLLSAI1 clock ready
-  *            @arg @ref RCC_FLAG_PLLSAI2RDY  PLLSAI2 clock ready
-  *            @arg @ref RCC_FLAG_LSERDY  LSE oscillator clock ready
-  *            @arg @ref RCC_FLAG_LSECSSD  Clock security system failure on LSE oscillator detection
-  *            @arg @ref RCC_FLAG_LSIRDY  LSI oscillator clock ready
-  *            @arg @ref RCC_FLAG_BORRST  BOR reset
-  *            @arg @ref RCC_FLAG_OBLRST  OBLRST reset
-  *            @arg @ref RCC_FLAG_PINRST  Pin reset
-  *            @arg @ref RCC_FLAG_FWRST  FIREWALL reset
-  *            @arg @ref RCC_FLAG_RMVF  Remove reset Flag
-  *            @arg @ref RCC_FLAG_SFTRST  Software reset
-  *            @arg @ref RCC_FLAG_IWDGRST  Independent Watchdog reset
-  *            @arg @ref RCC_FLAG_WWDGRST  Window Watchdog reset
-  *            @arg @ref RCC_FLAG_LPWRRST  Low Power reset
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR :                    \
-                                        ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :                  \
-                                        ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR))) &    \
-                                          ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) \
-                                            ? 1U : 0U)
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RCC_Private_Constants RCC Private Constants
-  * @{
-  */
-/* Defines used for Flags */
-#define CR_REG_INDEX              ((uint32_t)1U)
-#define BDCR_REG_INDEX            ((uint32_t)2U)
-#define CSR_REG_INDEX             ((uint32_t)3U)
-
-#define RCC_FLAG_MASK             ((uint32_t)0x1FU)
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup RCC_Private_Macros
-  * @{
-  */
-
-#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE)                           || \
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
-
-#define IS_RCC_HSE(__HSE__)  (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
-                              ((__HSE__) == RCC_HSE_BYPASS))
-
-#define IS_RCC_LSE(__LSE__)  (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
-                              ((__LSE__) == RCC_LSE_BYPASS))
-
-#define IS_RCC_HSI(__HSI__)  (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
-
-#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)31U)
-
-#define IS_RCC_LSI(__LSI__)  (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
-
-#define IS_RCC_MSI(__MSI__)  (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON))
-
-#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)255U)
-
-#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \
-                             ((__PLL__) == RCC_PLL_ON))
-
-#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \
-                                      ((__SOURCE__) == RCC_PLLSOURCE_MSI)  || \
-                                      ((__SOURCE__) == RCC_PLLSOURCE_HSI)  || \
-                                      ((__SOURCE__) == RCC_PLLSOURCE_HSE))
-
-#define IS_RCC_PLLM_VALUE(__VALUE__) ((__VALUE__) <= 8U)
-
-#define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
-
-#define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U))
-
-#define IS_RCC_PLLQ_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
-                                      ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
-
-#define IS_RCC_PLLR_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
-                                      ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
-
-#define IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK)  || \
-                                                  (((__VALUE__) & RCC_PLLSAI1_48M2CLK) == RCC_PLLSAI1_48M2CLK)  || \
-                                                  (((__VALUE__) & RCC_PLLSAI1_ADC1CLK) == RCC_PLLSAI1_ADC1CLK)) && \
-                                                 (((__VALUE__) & ~(RCC_PLLSAI1_SAI1CLK|RCC_PLLSAI1_48M2CLK|RCC_PLLSAI1_ADC1CLK)) == 0U))
-
-#define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK ) || \
-                                                  (((__VALUE__) & RCC_PLLSAI2_ADC2CLK) == RCC_PLLSAI2_ADC2CLK)) && \
-                                                 (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_ADC2CLK)) == 0U))   
-
-#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0)  || \
-                                           ((__RANGE__) == RCC_MSIRANGE_1)  || \
-                                           ((__RANGE__) == RCC_MSIRANGE_2)  || \
-                                           ((__RANGE__) == RCC_MSIRANGE_3)  || \
-                                           ((__RANGE__) == RCC_MSIRANGE_4)  || \
-                                           ((__RANGE__) == RCC_MSIRANGE_5)  || \
-                                           ((__RANGE__) == RCC_MSIRANGE_6)  || \
-                                           ((__RANGE__) == RCC_MSIRANGE_7)  || \
-                                           ((__RANGE__) == RCC_MSIRANGE_8)  || \
-                                           ((__RANGE__) == RCC_MSIRANGE_9)  || \
-                                           ((__RANGE__) == RCC_MSIRANGE_10) || \
-                                           ((__RANGE__) == RCC_MSIRANGE_11))
-
-#define IS_RCC_MSI_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_4)  || \
-                                                   ((__RANGE__) == RCC_MSIRANGE_5)  || \
-                                                   ((__RANGE__) == RCC_MSIRANGE_6)  || \
-                                                   ((__RANGE__) == RCC_MSIRANGE_7))
-
-#define IS_RCC_CLOCKTYPE(__CLK__)  ((1U <= (__CLK__)) && ((__CLK__) <= 15U))
-
-#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \
-                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
-                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
-                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
-
-#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1)   || ((__HCLK__) == RCC_SYSCLK_DIV2)   || \
-                               ((__HCLK__) == RCC_SYSCLK_DIV4)   || ((__HCLK__) == RCC_SYSCLK_DIV8)   || \
-                               ((__HCLK__) == RCC_SYSCLK_DIV16)  || ((__HCLK__) == RCC_SYSCLK_DIV64)  || \
-                               ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
-                               ((__HCLK__) == RCC_SYSCLK_DIV512))
-
-#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
-                               ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
-                               ((__PCLK__) == RCC_HCLK_DIV16))
-
-#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
-
-#define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1)
-
-#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
-                                       ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
-                                       ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
-                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
-                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
-                                       ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
-                                       ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \
-                                       ((__SOURCE__) == RCC_MCO1SOURCE_LSE))
-
-#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \
-                                ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \
-                                ((__DIV__) == RCC_MCODIV_16))
-
-#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW)        || \
-                                     ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW)  || \
-                                     ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \
-                                     ((__DRIVE__) == RCC_LSEDRIVE_HIGH))
-
-#define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) || \
-                                             ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI))
-/**
-  * @}
-  */
-
-/* Include RCC HAL Extended module */
-#include "stm32l4xx_hal_rcc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RCC_Exported_Functions
-  * @{
-  */
-
-
-/** @addtogroup RCC_Exported_Functions_Group1
-  * @{
-  */
-
-/* Initialization and de-initialization functions  ******************************/
-void              HAL_RCC_DeInit(void);
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
-
-/**
-  * @}
-  */
-
-/** @addtogroup RCC_Exported_Functions_Group2
-  * @{
-  */
-
-/* Peripheral Control functions  ************************************************/
-void              HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
-void              HAL_RCC_EnableCSS(void);
-uint32_t          HAL_RCC_GetSysClockFreq(void);
-uint32_t          HAL_RCC_GetHCLKFreq(void);
-uint32_t          HAL_RCC_GetPCLK1Freq(void);
-uint32_t          HAL_RCC_GetPCLK2Freq(void);
-void              HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
-void              HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
-/* CSS NMI IRQ handler */
-void              HAL_RCC_NMI_IRQHandler(void);
-/* User Callbacks in non blocking mode (IT mode) */
-void              HAL_RCC_CSSCallback(void);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L4xx_HAL_RCC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/inc/stm32l4xx_hal_rcc_ex.h b/stmhal/hal/l4/inc/stm32l4xx_hal_rcc_ex.h
deleted file mode 100644
index b31f6d8d37..0000000000
--- a/stmhal/hal/l4/inc/stm32l4xx_hal_rcc_ex.h
+++ /dev/null
@@ -1,1518 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_rcc_ex.h
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   Header file of RCC HAL Extended module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L4xx_HAL_RCC_EX_H
-#define __STM32L4xx_HAL_RCC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup RCCEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/ 
-
-/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
-  * @{
-  */
-
-/**
-  * @brief  PLLSAI1 Clock structure definition
-  */
-typedef struct
-{
-
-  uint32_t PLLSAI1N;         /*!< PLLSAI1N: specifies the multiplication factor for PLLSAI1 VCO output clock.
-                                  This parameter must be a number between 8 and 86. */
-
-  uint32_t PLLSAI1P;         /*!< PLLSAI1P: specifies the division factor for SAI clock.
-                                  This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
-
-  uint32_t PLLSAI1Q;         /*!< PLLSAI1Q: specifies the division factor for USB/RNG/SDMMC1 clock.
-                                  This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */
-
-  uint32_t PLLSAI1R;         /*!< PLLSAI1R: specifies the division factor for ADC clock.
-                                  This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
-
-  uint32_t PLLSAI1ClockOut;  /*!< PLLSAIClockOut: specifies PLLSAI1 output clock to be enabled.
-                                  This parameter must be a value of @ref RCC_PLLSAI1_Clock_Output */
-}RCC_PLLSAI1InitTypeDef;
-
-/**
-  * @brief  PLLSAI2 Clock structure definition
-  */
-typedef struct
-{
-
-  uint32_t PLLSAI2N;         /*!< PLLSAI2N: specifies the multiplication factor for PLLSAI2 VCO output clock.
-                                  This parameter must be a number between 8 and 86. */
-
-  uint32_t PLLSAI2P;         /*!< PLLSAI2P: specifies the division factor for SAI clock.
-                                  This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
-
-  uint32_t PLLSAI2R;         /*!< PLLSAI2R: specifies the division factor for ADC clock.
-                                  This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
-
-  uint32_t PLLSAI2ClockOut;  /*!< PLLSAIClockOut: specifies PLLSAI2 output clock to be enabled.
-                                  This parameter must be a value of @ref RCC_PLLSAI2_Clock_Output */
-}RCC_PLLSAI2InitTypeDef;
-
-/**
-  * @brief  RCC extended clocks structure definition
-  */
-typedef struct
-{
-  uint32_t PeriphClockSelection;   /*!< The Extended Clock to be configured.
-                                        This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
-
-  RCC_PLLSAI1InitTypeDef PLLSAI1;  /*!< PLLSAI1 structure parameters.
-                                        This parameter will be used only when PLLSAI1 is selected as Clock Source for SAI1, USB/RNG/SDMMC1 or ADC */
-
-  RCC_PLLSAI2InitTypeDef PLLSAI2;  /*!< PLLSAI2 structure parameters.
-                                        This parameter will be used only when PLLSAI2 is selected as Clock Source for SAI2 or ADC */
-
-  uint32_t Usart1ClockSelection;   /*!< Specifies USART1 clock source.
-                                        This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
-
-  uint32_t Usart2ClockSelection;   /*!< Specifies USART2 clock source.
-                                        This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
-
-  uint32_t Usart3ClockSelection;   /*!< Specifies USART3 clock source.
-                                        This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
-
-  uint32_t Uart4ClockSelection;    /*!< Specifies UART4 clock source.
-                                        This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
-
-  uint32_t Uart5ClockSelection;    /*!< Specifies UART5 clock source.
-                                        This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
-
-  uint32_t Lpuart1ClockSelection;  /*!< Specifies LPUART1 clock source.
-                                        This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
-
-  uint32_t I2c1ClockSelection;     /*!< Specifies I2C1 clock source.
-                                        This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
-
-  uint32_t I2c2ClockSelection;     /*!< Specifies I2C2 clock source.
-                                        This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
-
-  uint32_t I2c3ClockSelection;     /*!< Specifies I2C3 clock source.
-                                        This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
-
-  uint32_t Lptim1ClockSelection;   /*!< Specifies LPTIM1 clock source.
-                                        This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
-
-  uint32_t Lptim2ClockSelection;   /*!< Specifies LPTIM2 clock source.
-                                        This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */
-
-  uint32_t Sai1ClockSelection;     /*!< Specifies SAI1 clock source.
-                                        This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
-
-  uint32_t Sai2ClockSelection;     /*!< Specifies SAI2 clock source.
-                                        This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
-
-#if defined(USB_OTG_FS)
-
-  uint32_t UsbClockSelection;      /*!< Specifies USB clock source (warning: same source for SDMMC1 and RNG).
-                                        This parameter can be a value of @ref RCCEx_USB_Clock_Source */
-
-#endif /* USB_OTG_FS */
-
-  uint32_t Sdmmc1ClockSelection;   /*!< Specifies SDMMC1 clock source (warning: same source for USB and RNG).
-                                        This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */
-
-  uint32_t RngClockSelection;      /*!< Specifies RNG clock source (warning: same source for USB and SDMMC1).
-                                        This parameter can be a value of @ref RCCEx_RNG_Clock_Source */
-
-  uint32_t AdcClockSelection;      /*!< Specifies ADC interface clock source.
-                                        This parameter can be a value of @ref RCCEx_ADC_Clock_Source */
-
-  uint32_t Swpmi1ClockSelection;   /*!< Specifies SWPMI1 clock source.
-                                        This parameter can be a value of @ref RCCEx_SWPMI1_Clock_Source */
-
-  uint32_t DfsdmClockSelection;    /*!< Specifies DFSDM clock source.
-                                        This parameter can be a value of @ref RCCEx_DFSDM_Clock_Source */
-
-  uint32_t RTCClockSelection;      /*!< Specifies RTC clock source.
-                                        This parameter can be a value of @ref RCC_RTC_Clock_Source */
-}RCC_PeriphCLKInitTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
-  * @{
-  */
-
-/** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source
-  * @{
-  */
-#define RCC_LSCOSOURCE_LSI             (uint32_t)0x00000000U /*!< LSI selection for low speed clock output */
-#define RCC_LSCOSOURCE_LSE             RCC_BDCR_LSCOSEL      /*!< LSE selection for low speed clock output */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection
-  * @{
-  */
-#define RCC_PERIPHCLK_USART1           ((uint32_t)0x00000001U)
-#define RCC_PERIPHCLK_USART2           ((uint32_t)0x00000002U)
-#define RCC_PERIPHCLK_USART3           ((uint32_t)0x00000004U)
-#define RCC_PERIPHCLK_UART4            ((uint32_t)0x00000008U)
-#define RCC_PERIPHCLK_UART5            ((uint32_t)0x00000010U)
-#define RCC_PERIPHCLK_LPUART1          ((uint32_t)0x00000020U)
-#define RCC_PERIPHCLK_I2C1             ((uint32_t)0x00000040U)
-#define RCC_PERIPHCLK_I2C2             ((uint32_t)0x00000080U)
-#define RCC_PERIPHCLK_I2C3             ((uint32_t)0x00000100U)
-#define RCC_PERIPHCLK_LPTIM1           ((uint32_t)0x00000200U)
-#define RCC_PERIPHCLK_LPTIM2           ((uint32_t)0x00000400U)
-#define RCC_PERIPHCLK_SAI1             ((uint32_t)0x00000800U)
-#define RCC_PERIPHCLK_SAI2             ((uint32_t)0x00001000U)
-#if defined(USB_OTG_FS)
-#define RCC_PERIPHCLK_USB              ((uint32_t)0x00002000U)
-#endif
-#define RCC_PERIPHCLK_ADC              ((uint32_t)0x00004000U)
-#define RCC_PERIPHCLK_SWPMI1           ((uint32_t)0x00008000U)
-#define RCC_PERIPHCLK_DFSDM            ((uint32_t)0x00010000U)
-#define RCC_PERIPHCLK_RTC              ((uint32_t)0x00020000U)
-#define RCC_PERIPHCLK_RNG              ((uint32_t)0x00040000U)
-#define RCC_PERIPHCLK_SDMMC1           ((uint32_t)0x00080000U)
-/**
-  * @}
-  */
-
-
-/** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source
-  * @{
-  */
-#define RCC_USART1CLKSOURCE_PCLK2      ((uint32_t)0x00000000U)
-#define RCC_USART1CLKSOURCE_SYSCLK     RCC_CCIPR_USART1SEL_0
-#define RCC_USART1CLKSOURCE_HSI        RCC_CCIPR_USART1SEL_1
-#define RCC_USART1CLKSOURCE_LSE        (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source
-  * @{
-  */
-#define RCC_USART2CLKSOURCE_PCLK1      ((uint32_t)0x00000000U)
-#define RCC_USART2CLKSOURCE_SYSCLK     RCC_CCIPR_USART2SEL_0
-#define RCC_USART2CLKSOURCE_HSI        RCC_CCIPR_USART2SEL_1
-#define RCC_USART2CLKSOURCE_LSE        (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source
-  * @{
-  */
-#define RCC_USART3CLKSOURCE_PCLK1      ((uint32_t)0x00000000U)
-#define RCC_USART3CLKSOURCE_SYSCLK     RCC_CCIPR_USART3SEL_0
-#define RCC_USART3CLKSOURCE_HSI        RCC_CCIPR_USART3SEL_1
-#define RCC_USART3CLKSOURCE_LSE        (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source
-  * @{
-  */
-#define RCC_UART4CLKSOURCE_PCLK1       ((uint32_t)0x00000000U)
-#define RCC_UART4CLKSOURCE_SYSCLK      RCC_CCIPR_UART4SEL_0
-#define RCC_UART4CLKSOURCE_HSI         RCC_CCIPR_UART4SEL_1
-#define RCC_UART4CLKSOURCE_LSE         (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source
-  * @{
-  */
-#define RCC_UART5CLKSOURCE_PCLK1       ((uint32_t)0x00000000U)
-#define RCC_UART5CLKSOURCE_SYSCLK      RCC_CCIPR_UART5SEL_0
-#define RCC_UART5CLKSOURCE_HSI         RCC_CCIPR_UART5SEL_1
-#define RCC_UART5CLKSOURCE_LSE         (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source
-  * @{
-  */
-#define RCC_LPUART1CLKSOURCE_PCLK1     ((uint32_t)0x00000000U)
-#define RCC_LPUART1CLKSOURCE_SYSCLK    RCC_CCIPR_LPUART1SEL_0
-#define RCC_LPUART1CLKSOURCE_HSI       RCC_CCIPR_LPUART1SEL_1
-#define RCC_LPUART1CLKSOURCE_LSE       (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source
-  * @{
-  */
-#define RCC_I2C1CLKSOURCE_PCLK1        ((uint32_t)0x00000000U)
-#define RCC_I2C1CLKSOURCE_SYSCLK       RCC_CCIPR_I2C1SEL_0
-#define RCC_I2C1CLKSOURCE_HSI          RCC_CCIPR_I2C1SEL_1
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source
-  * @{
-  */
-#define RCC_I2C2CLKSOURCE_PCLK1        ((uint32_t)0x00000000U)
-#define RCC_I2C2CLKSOURCE_SYSCLK       RCC_CCIPR_I2C2SEL_0
-#define RCC_I2C2CLKSOURCE_HSI          RCC_CCIPR_I2C2SEL_1
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source
-  * @{
-  */
-#define RCC_I2C3CLKSOURCE_PCLK1        ((uint32_t)0x00000000U)
-#define RCC_I2C3CLKSOURCE_SYSCLK       RCC_CCIPR_I2C3SEL_0
-#define RCC_I2C3CLKSOURCE_HSI          RCC_CCIPR_I2C3SEL_1
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source
-  * @{
-  */
-#define RCC_SAI1CLKSOURCE_PLLSAI1      ((uint32_t)0x00000000U)
-#define RCC_SAI1CLKSOURCE_PLLSAI2      RCC_CCIPR_SAI1SEL_0
-#define RCC_SAI1CLKSOURCE_PLL          RCC_CCIPR_SAI1SEL_1
-#define RCC_SAI1CLKSOURCE_PIN          RCC_CCIPR_SAI1SEL
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source
-  * @{
-  */
-#define RCC_SAI2CLKSOURCE_PLLSAI1      ((uint32_t)0x00000000U)
-#define RCC_SAI2CLKSOURCE_PLLSAI2      RCC_CCIPR_SAI2SEL_0
-#define RCC_SAI2CLKSOURCE_PLL          RCC_CCIPR_SAI2SEL_1
-#define RCC_SAI2CLKSOURCE_PIN          RCC_CCIPR_SAI2SEL
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source
-  * @{
-  */
-#define RCC_LPTIM1CLKSOURCE_PCLK       ((uint32_t)0x00000000U)
-#define RCC_LPTIM1CLKSOURCE_LSI        RCC_CCIPR_LPTIM1SEL_0
-#define RCC_LPTIM1CLKSOURCE_HSI        RCC_CCIPR_LPTIM1SEL_1
-#define RCC_LPTIM1CLKSOURCE_LSE        RCC_CCIPR_LPTIM1SEL
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source
-  * @{
-  */
-#define RCC_LPTIM2CLKSOURCE_PCLK       ((uint32_t)0x00000000U)
-#define RCC_LPTIM2CLKSOURCE_LSI        RCC_CCIPR_LPTIM2SEL_0
-#define RCC_LPTIM2CLKSOURCE_HSI        RCC_CCIPR_LPTIM2SEL_1
-#define RCC_LPTIM2CLKSOURCE_LSE        RCC_CCIPR_LPTIM2SEL
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_SDMMC1_Clock_Source SDMMC1 Clock Source
-  * @{
-  */
-#define RCC_SDMMC1CLKSOURCE_NONE       ((uint32_t)0x00000000U)
-#define RCC_SDMMC1CLKSOURCE_PLLSAI1    RCC_CCIPR_CLK48SEL_0
-#define RCC_SDMMC1CLKSOURCE_PLL        RCC_CCIPR_CLK48SEL_1
-#define RCC_SDMMC1CLKSOURCE_MSI        RCC_CCIPR_CLK48SEL
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source
-  * @{
-  */
-#define RCC_RNGCLKSOURCE_NONE          ((uint32_t)0x00000000U)
-#define RCC_RNGCLKSOURCE_PLLSAI1       RCC_CCIPR_CLK48SEL_0
-#define RCC_RNGCLKSOURCE_PLL           RCC_CCIPR_CLK48SEL_1
-#define RCC_RNGCLKSOURCE_MSI           RCC_CCIPR_CLK48SEL
-/**
-  * @}
-  */
-
-#if defined(USB_OTG_FS)
-/** @defgroup RCCEx_USB_Clock_Source USB Clock Source
-  * @{
-  */
-#define RCC_USBCLKSOURCE_NONE          ((uint32_t)0x00000000U)
-#define RCC_USBCLKSOURCE_PLLSAI1       RCC_CCIPR_CLK48SEL_0
-#define RCC_USBCLKSOURCE_PLL           RCC_CCIPR_CLK48SEL_1
-#define RCC_USBCLKSOURCE_MSI           RCC_CCIPR_CLK48SEL
-/**
-  * @}
-  */
-#endif /* USB_OTG_FS */
-
-/** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source
-  * @{
-  */
-#define RCC_ADCCLKSOURCE_NONE        ((uint32_t)0x00000000U)
-#define RCC_ADCCLKSOURCE_PLLSAI1      RCC_CCIPR_ADCSEL_0
-#define RCC_ADCCLKSOURCE_PLLSAI2      RCC_CCIPR_ADCSEL_1
-#define RCC_ADCCLKSOURCE_SYSCLK       RCC_CCIPR_ADCSEL
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_SWPMI1_Clock_Source SWPMI1 Clock Source
-  * @{
-  */
-#define RCC_SWPMI1CLKSOURCE_PCLK       ((uint32_t)0x00000000U)
-#define RCC_SWPMI1CLKSOURCE_HSI        RCC_CCIPR_SWPMI1SEL
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_DFSDM_Clock_Source DFSDM Clock Source
-  * @{
-  */
-#define RCC_DFSDMCLKSOURCE_PCLK        ((uint32_t)0x00000000U)
-#define RCC_DFSDMCLKSOURCE_SYSCLK      RCC_CCIPR_DFSDMSEL
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_EXTI_LINE_LSECSS  RCC LSE CSS external interrupt line
-  * @{
-  */
-#define RCC_EXTI_LINE_LSECSS           EXTI_IMR1_IM19        /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
- * @{
- */
-
-
-/**
-  * @brief  Macro to configure the PLLSAI1 clock multiplication and division factors.
-  *
-  * @note   This function must be used only when the PLLSAI1 is disabled.
-  * @note   PLLSAI1 clock source is common with the main PLL (configured through
-  *         __HAL_RCC_PLL_CONFIG() macro)
-  *
-  * @param  __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock.
-  *         This parameter must be a number between 8 and 86.
-  * @note   You have to set the PLLSAI1N parameter correctly to ensure that the VCO
-  *         output frequency is between 64 and 344 MHz.
-  *         PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N
-  *
-  * @param  __PLLSAI1P__ specifies the division factor for SAI clock.
-  *         This parameter must be a number in the range (7 or 17).
-  *         SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P
-  *
-  * @param  __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock.
-  *         This parameter must be in the range (2, 4, 6 or 8).
-  *         USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q
-  *
-  * @param  __PLLSAI1R__ specifies the division factor for SAR ADC clock.
-  *         This parameter must be in the range (2, 4, 6 or 8).
-  *         ADC clock frequency = f(PLLSAI1) / PLLSAI1R
-  *
-  * @retval None
-  */
-#define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \
-                  WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) | \
-                    (((__PLLSAI1P__) >> 4U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P)) | \
-                    ((((__PLLSAI1Q__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)) | \
-                    ((((__PLLSAI1R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)))
-
-/**
-  * @brief  Macro to configure the PLLSAI1 clock multiplication factor N.
-  *
-  * @note   This function must be used only when the PLLSAI1 is disabled.
-  * @note   PLLSAI1 clock source is common with the main PLL (configured through
-  *         __HAL_RCC_PLL_CONFIG() macro)
-  *
-  * @param  __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock.
-  *          This parameter must be a number between 8 and 86.
-  * @note   You have to set the PLLSAI1N parameter correctly to ensure that the VCO
-  *         output frequency is between 64 and 344 MHz.
-  *         Use to set PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N
-  *
-  * @retval None
-  */
-#define __HAL_RCC_PLLSAI1_MULN_CONFIG(__PLLSAI1N__) \
-                  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N))
-
-/** @brief  Macro to configure the PLLSAI1 clock division factor P.
-  *
-  * @note   This function must be used only when the PLLSAI1 is disabled.
-  * @note   PLLSAI1 clock source is common with the main PLL (configured through
-  *         __HAL_RCC_PLL_CONFIG() macro)
-  *
-  * @param  __PLLSAI1P__ specifies the division factor for SAI clock.
-  *         This parameter must be a number in the range (7 or 17).
-  *         Use to set SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P
-  *
-  * @retval None
-  */
-#define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \
-                  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P, ((__PLLSAI1P__) >> 4U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P))
-
-/** @brief  Macro to configure the PLLSAI1 clock division factor Q.
-  *
-  * @note   This function must be used only when the PLLSAI1 is disabled.
-  * @note   PLLSAI1 clock source is common with the main PLL (configured through
-  *         __HAL_RCC_PLL_CONFIG() macro)
-  *
-  * @param  __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock.
-  *         This parameter must be in the range (2, 4, 6 or 8).
-  *         Use to set USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q
-  *
-  * @retval None
-  */
-#define __HAL_RCC_PLLSAI1_DIVQ_CONFIG(__PLLSAI1Q__) \
-                  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q))
-
-/** @brief  Macro to configure the PLLSAI1 clock division factor R.
-  *
-  * @note   This function must be used only when the PLLSAI1 is disabled.
-  * @note   PLLSAI1 clock source is common with the main PLL (configured through
-  *         __HAL_RCC_PLL_CONFIG() macro)
-  *
-  * @param  __PLLSAI1R__ specifies the division factor for ADC clock.
-  *         This parameter must be in the range (2, 4, 6 or 8)
-  *         Use to set ADC clock frequency = f(PLLSAI1) / PLLSAI1R
-  *
-  * @retval None
-  */
-#define __HAL_RCC_PLLSAI1_DIVR_CONFIG(__PLLSAI1R__) \
-                  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R))
-
-/**
-  * @brief  Macros to enable or disable the PLLSAI1.
-  * @note   The PLLSAI1 is disabled by hardware when entering STOP and STANDBY modes.
-  * @retval None
-  */
-
-#define __HAL_RCC_PLLSAI1_ENABLE()  SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON)
-
-#define __HAL_RCC_PLLSAI1_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON)
-
-/**
-  * @brief  Macros to enable or disable each clock output (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1).
-  * @note   Enabling and disabling those clocks can be done without the need to stop the PLL.
-  *         This is mainly used to save Power.
-  * @param  __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output.
-  *         This parameter can be one or a combination of the following values:
-  *            @arg @ref RCC_PLLSAI1_SAI1CLK  This clock is used to generate an accurate clock to achieve
-  *                                   high-quality audio performance on SAI interface in case.
-  *            @arg @ref RCC_PLLSAI1_48M2CLK  This clock is used to generate the clock for the USB OTG FS (48 MHz),
-  *                                   the random number generator (<=48 MHz) and the SDIO (<= 48 MHz).
-  *            @arg @ref RCC_PLLSAI1_ADC1CLK  Clock used to clock ADC peripheral.
-  * @retval None
-  */
-
-#define __HAL_RCC_PLLSAI1CLKOUT_ENABLE(__PLLSAI1_CLOCKOUT__)   SET_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
-
-#define __HAL_RCC_PLLSAI1CLKOUT_DISABLE(__PLLSAI1_CLOCKOUT__)  CLEAR_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
-
-/**
-  * @brief  Macro to get clock output enable status (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1).
-  * @param  __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output.
-  *         This parameter can be one of the following values:
-  *            @arg @ref RCC_PLLSAI1_SAI1CLK  This clock is used to generate an accurate clock to achieve
-  *                                   high-quality audio performance on SAI interface in case.
-  *            @arg @ref RCC_PLLSAI1_48M2CLK  This clock is used to generate the clock for the USB OTG FS (48 MHz),
-  *                                   the random number generator (<=48 MHz) and the SDIO (<= 48 MHz).
-  *            @arg @ref RCC_PLLSAI1_ADC1CLK  Clock used to clock ADC peripheral.
-  * @retval SET / RESET
-  */
-#define __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(__PLLSAI1_CLOCKOUT__)  READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
-
-/**
-  * @brief  Macro to configure the PLLSAI2 clock multiplication and division factors.
-  *
-  * @note   This function must be used only when the PLLSAI2 is disabled.
-  * @note   PLLSAI2 clock source is common with the main PLL (configured through
-  *         __HAL_RCC_PLL_CONFIG() macro)
-  *
-  * @param  __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock.
-  *          This parameter must be a number between 8 and 86.
-  * @note   You have to set the PLLSAI2N parameter correctly to ensure that the VCO
-  *         output frequency is between 64 and 344 MHz.
-  *
-  * @param  __PLLSAI2P__ specifies the division factor for SAI clock.
-  *          This parameter must be a number in the range (7 or 17).
-  *
-  *
-  * @param  __PLLSAI2R__ specifies the division factor for SAR ADC clock.
-  *          This parameter must be in the range (2, 4, 6 or 8)
-  *
-  * @retval None
-  */
-
-#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \
-                  WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)) | \
-                    (((__PLLSAI2P__) >> 4U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P)) | \
-                    ((((__PLLSAI2R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)))
-
-/**
-  * @brief  Macro to configure the PLLSAI2 clock multiplication factor N.
-  *
-  * @note   This function must be used only when the PLLSAI2 is disabled.
-  * @note   PLLSAI2 clock source is common with the main PLL (configured through
-  *         __HAL_RCC_PLL_CONFIG() macro)
-  *
-  * @param  __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock.
-  *          This parameter must be a number between 8 and 86.
-  * @note   You have to set the PLLSAI2N parameter correctly to ensure that the VCO
-  *         output frequency is between 64 and 344 MHz.
-  *         PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI2N
-  *
-  * @retval None
-  */
-#define __HAL_RCC_PLLSAI2_MULN_CONFIG(__PLLSAI2N__) \
-                  MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N))
-
-/** @brief  Macro to configure the PLLSAI2 clock division factor P.
-  *
-  * @note   This function must be used only when the PLLSAI2 is disabled.
-  * @note   PLLSAI2 clock source is common with the main PLL (configured through
-  *         __HAL_RCC_PLL_CONFIG() macro)
-  *
-  * @param  __PLLSAI2P__ specifies the division factor.
-  *         This parameter must be a number in the range (7 or 17).
-  *         Use to set SAI2 clock frequency = f(PLLSAI2) / __PLLSAI2P__
-  *
-  * @retval None
-  */
-#define __HAL_RCC_PLLSAI2_DIVP_CONFIG(__PLLSAI2P__) \
-                  MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P))
-
-/** @brief  Macro to configure the PLLSAI2 clock division factor R.
-  *
-  * @note   This function must be used only when the PLLSAI2 is disabled.
-  * @note   PLLSAI1 clock source is common with the main PLL (configured through
-  *         __HAL_RCC_PLL_CONFIG() macro)
-  *
-  * @param  __PLLSAI2R__ specifies the division factor.
-  *         This parameter must be in the range (2, 4, 6 or 8).
-  *         Use to set ADC clock frequency = f(PLLSAI2) / __PLLSAI2Q__
-  *
-  * @retval None
-  */
-#define __HAL_RCC_PLLSAI2_DIVR_CONFIG(__PLLSAI2R__) \
-                  MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R, (((__PLLSAI2R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R))
-
-/**
-  * @brief  Macros to enable or disable the PLLSAI2.
-  * @note   The PLLSAI2 is disabled by hardware when entering STOP and STANDBY modes.
-  * @retval None
-  */
-
-#define __HAL_RCC_PLLSAI2_ENABLE()  SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON)
-
-#define __HAL_RCC_PLLSAI2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON)
-
-/**
-  * @brief  Macros to enable or disable each clock output (PLLSAI2_SAI2 and PLLSAI2_ADC2).
-  * @note   Enabling and disabling those clocks can be done without the need to stop the PLL.
-  *         This is mainly used to save Power.
-  * @param  __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output.
-  *         This parameter can be one or a combination of the following values:
-  *            @arg @ref RCC_PLLSAI2_SAI2CLK  This clock is used to generate an accurate clock to achieve
-  *                                   high-quality audio performance on SAI interface in case.
-  *            @arg @ref RCC_PLLSAI2_ADC2CLK  Clock used to clock ADC peripheral.
-  * @retval None
-  */
-
-#define __HAL_RCC_PLLSAI2CLKOUT_ENABLE(__PLLSAI2_CLOCKOUT__)  SET_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
-
-#define __HAL_RCC_PLLSAI2CLKOUT_DISABLE(__PLLSAI2_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
-
-/**
-  * @brief  Macro to get clock output enable status (PLLSAI2_SAI2 and PLLSAI2_ADC2).
-  * @param  __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_PLLSAI2_SAI2CLK  This clock is used to generate an accurate clock to achieve
-  *                                   high-quality audio performance on SAI interface in case.
-  *            @arg @ref RCC_PLLSAI2_ADC2CLK  Clock used to clock ADC peripheral.
-  * @retval SET / RESET
-  */
-#define __HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(__PLLSAI2_CLOCKOUT__)  READ_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
-
-/**
-  * @brief  Macro to configure the SAI1 clock source.
-  * @param  __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived
-  *         from the PLLSAI1, system PLL or external clock (through a dedicated pin).
-  *          This parameter can be one of the following values:
-  *             @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1  SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
-  *             @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2  SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK)
-  *             @arg @ref RCC_SAI1CLKSOURCE_PLL  SAI1 clock  = PLL "P" clock (PLLSAI3CLK)
-  *             @arg @ref RCC_SAI1CLKSOURCE_PIN  SAI1 clock = External Clock (SAI1_EXTCLK)
-  *
-  * @retval None
-  */
-#define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (uint32_t)(__SAI1_CLKSOURCE__))
-
-/** @brief  Macro to get the SAI1 clock source.
-  * @retval The clock source can be one of the following values:
-  *             @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1  SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
-  *             @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2  SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK)
-  *             @arg @ref RCC_SAI1CLKSOURCE_PLL  SAI1 clock  = PLL "P" clock (PLLSAI3CLK)
-  *             @arg @ref RCC_SAI1CLKSOURCE_PIN  SAI1 clock = External Clock (SAI1_EXTCLK)
-  */
-#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL)))
-
-/**
-  * @brief  Macro to configure the SAI2 clock source.
-  * @param  __SAI2_CLKSOURCE__ defines the SAI2 clock source. This clock is derived
-  *         from the PLLSAI2, system PLL or external clock (through a dedicated pin).
-  *          This parameter can be one of the following values:
-  *             @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1  SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
-  *             @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2  SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK)
-  *             @arg @ref RCC_SAI2CLKSOURCE_PLL  SAI2 clock  = PLL "P" clock (PLLSAI3CLK)
-  *             @arg @ref RCC_SAI2CLKSOURCE_PIN  SAI2 clock = External Clock (SAI2_EXTCLK)
-  * @retval None
-  */
-#define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI2SEL, (uint32_t)(__SAI2_CLKSOURCE__))
-
-/** @brief  Macro to get the SAI2 clock source.
-  * @retval The clock source can be one of the following values:
-  *             @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1  SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
-  *             @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2  SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK)
-  *             @arg @ref RCC_SAI2CLKSOURCE_PLL  SAI2 clock  = PLL "P" clock (PLLSAI3CLK)
-  *             @arg @ref RCC_SAI2CLKSOURCE_PIN  SAI2 clock = External Clock (SAI2_EXTCLK)
-  */
-#define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI2SEL)))
-
-/** @brief  Macro to configure the I2C1 clock (I2C1CLK).
-  *
-  * @param  __I2C1_CLKSOURCE__ specifies the I2C1 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_I2C1CLKSOURCE_PCLK1  PCLK1 selected as I2C1 clock
-  *            @arg @ref RCC_I2C1CLKSOURCE_HSI  HSI selected as I2C1 clock
-  *            @arg @ref RCC_I2C1CLKSOURCE_SYSCLK  System Clock selected as I2C1 clock
-  * @retval None
-  */
-#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
-
-/** @brief  Macro to get the I2C1 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_I2C1CLKSOURCE_PCLK1  PCLK1 selected as I2C1 clock
-  *            @arg @ref RCC_I2C1CLKSOURCE_HSI  HSI selected as I2C1 clock
-  *            @arg @ref RCC_I2C1CLKSOURCE_SYSCLK  System Clock selected as I2C1 clock
-  */
-#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)))
-
-/** @brief  Macro to configure the I2C2 clock (I2C2CLK).
-  *
-  * @param  __I2C2_CLKSOURCE__ specifies the I2C2 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_I2C2CLKSOURCE_PCLK1  PCLK1 selected as I2C2 clock
-  *            @arg @ref RCC_I2C2CLKSOURCE_HSI  HSI selected as I2C2 clock
-  *            @arg @ref RCC_I2C2CLKSOURCE_SYSCLK  System Clock selected as I2C2 clock
-  * @retval None
-  */
-#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))
-
-/** @brief  Macro to get the I2C2 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_I2C2CLKSOURCE_PCLK1  PCLK1 selected as I2C2 clock
-  *            @arg @ref RCC_I2C2CLKSOURCE_HSI  HSI selected as I2C2 clock
-  *            @arg @ref RCC_I2C2CLKSOURCE_SYSCLK  System Clock selected as I2C2 clock
-  */
-#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL)))
-
-/** @brief  Macro to configure the I2C3 clock (I2C3CLK).
-  *
-  * @param  __I2C3_CLKSOURCE__ specifies the I2C3 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_I2C3CLKSOURCE_PCLK1  PCLK1 selected as I2C3 clock
-  *            @arg @ref RCC_I2C3CLKSOURCE_HSI  HSI selected as I2C3 clock
-  *            @arg @ref RCC_I2C3CLKSOURCE_SYSCLK  System Clock selected as I2C3 clock
-  * @retval None
-  */
-#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
-
-/** @brief  Macro to get the I2C3 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_I2C3CLKSOURCE_PCLK1  PCLK1 selected as I2C3 clock
-  *            @arg @ref RCC_I2C3CLKSOURCE_HSI  HSI selected as I2C3 clock
-  *            @arg @ref RCC_I2C3CLKSOURCE_SYSCLK  System Clock selected as I2C3 clock
-  */
-#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)))
-
-/** @brief  Macro to configure the USART1 clock (USART1CLK).
-  *
-  * @param  __USART1_CLKSOURCE__ specifies the USART1 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_USART1CLKSOURCE_PCLK2  PCLK2 selected as USART1 clock
-  *            @arg @ref RCC_USART1CLKSOURCE_HSI  HSI selected as USART1 clock
-  *            @arg @ref RCC_USART1CLKSOURCE_SYSCLK  System Clock selected as USART1 clock
-  *            @arg @ref RCC_USART1CLKSOURCE_LSE  SE selected as USART1 clock
-  * @retval None
-  */
-#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
-
-/** @brief  Macro to get the USART1 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_USART1CLKSOURCE_PCLK2  PCLK2 selected as USART1 clock
-  *            @arg @ref RCC_USART1CLKSOURCE_HSI  HSI selected as USART1 clock
-  *            @arg @ref RCC_USART1CLKSOURCE_SYSCLK  System Clock selected as USART1 clock
-  *            @arg @ref RCC_USART1CLKSOURCE_LSE  LSE selected as USART1 clock
-  */
-#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)))
-
-/** @brief  Macro to configure the USART2 clock (USART2CLK).
-  *
-  * @param  __USART2_CLKSOURCE__ specifies the USART2 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_USART2CLKSOURCE_PCLK1  PCLK1 selected as USART2 clock
-  *            @arg @ref RCC_USART2CLKSOURCE_HSI  HSI selected as USART2 clock
-  *            @arg @ref RCC_USART2CLKSOURCE_SYSCLK  System Clock selected as USART2 clock
-  *            @arg @ref RCC_USART2CLKSOURCE_LSE  LSE selected as USART2 clock
-  * @retval None
-  */
-#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
-
-/** @brief  Macro to get the USART2 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_USART2CLKSOURCE_PCLK1  PCLK1 selected as USART2 clock
-  *            @arg @ref RCC_USART2CLKSOURCE_HSI  HSI selected as USART2 clock
-  *            @arg @ref RCC_USART2CLKSOURCE_SYSCLK  System Clock selected as USART2 clock
-  *            @arg @ref RCC_USART2CLKSOURCE_LSE  LSE selected as USART2 clock
-  */
-#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)))
-
-/** @brief  Macro to configure the USART3 clock (USART3CLK).
-  *
-  * @param  __USART3_CLKSOURCE__ specifies the USART3 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_USART3CLKSOURCE_PCLK1  PCLK1 selected as USART3 clock
-  *            @arg @ref RCC_USART3CLKSOURCE_HSI  HSI selected as USART3 clock
-  *            @arg @ref RCC_USART3CLKSOURCE_SYSCLK  System Clock selected as USART3 clock
-  *            @arg @ref RCC_USART3CLKSOURCE_LSE  LSE selected as USART3 clock
-  * @retval None
-  */
-#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))
-
-/** @brief  Macro to get the USART3 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_USART3CLKSOURCE_PCLK1  PCLK1 selected as USART3 clock
-  *            @arg @ref RCC_USART3CLKSOURCE_HSI  HSI selected as USART3 clock
-  *            @arg @ref RCC_USART3CLKSOURCE_SYSCLK  System Clock selected as USART3 clock
-  *            @arg @ref RCC_USART3CLKSOURCE_LSE  LSE selected as USART3 clock
-  */
-#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL)))
-
-/** @brief  Macro to configure the UART4 clock (UART4CLK).
-  *
-  * @param  __UART4_CLKSOURCE__ specifies the UART4 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_UART4CLKSOURCE_PCLK1  PCLK1 selected as UART4 clock
-  *            @arg @ref RCC_UART4CLKSOURCE_HSI  HSI selected as UART4 clock
-  *            @arg @ref RCC_UART4CLKSOURCE_SYSCLK  System Clock selected as UART4 clock
-  *            @arg @ref RCC_UART4CLKSOURCE_LSE  LSE selected as UART4 clock
-  * @retval None
-  */
-#define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))
-
-/** @brief  Macro to get the UART4 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_UART4CLKSOURCE_PCLK1  PCLK1 selected as UART4 clock
-  *            @arg @ref RCC_UART4CLKSOURCE_HSI  HSI selected as UART4 clock
-  *            @arg @ref RCC_UART4CLKSOURCE_SYSCLK  System Clock selected as UART4 clock
-  *            @arg @ref RCC_UART4CLKSOURCE_LSE  LSE selected as UART4 clock
-  */
-#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL)))
-
- /** @brief  Macro to configure the UART5 clock (UART5CLK).
-  *
-  * @param  __UART5_CLKSOURCE__ specifies the UART5 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_UART5CLKSOURCE_PCLK1  PCLK1 selected as UART5 clock
-  *            @arg @ref RCC_UART5CLKSOURCE_HSI  HSI selected as UART5 clock
-  *            @arg @ref RCC_UART5CLKSOURCE_SYSCLK  System Clock selected as UART5 clock
-  *            @arg @ref RCC_UART5CLKSOURCE_LSE  LSE selected as UART5 clock
-  * @retval None
-  */
-#define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))
-
-/** @brief  Macro to get the UART5 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_UART5CLKSOURCE_PCLK1  PCLK1 selected as UART5 clock
-  *            @arg @ref RCC_UART5CLKSOURCE_HSI  HSI selected as UART5 clock
-  *            @arg @ref RCC_UART5CLKSOURCE_SYSCLK  System Clock selected as UART5 clock
-  *            @arg @ref RCC_UART5CLKSOURCE_LSE  LSE selected as UART5 clock
-  */
-#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL)))
-
-/** @brief  Macro to configure the LPUART1 clock (LPUART1CLK).
-  *
-  * @param  __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_LPUART1CLKSOURCE_PCLK1  PCLK1 selected as LPUART1 clock
-  *            @arg @ref RCC_LPUART1CLKSOURCE_HSI  HSI selected as LPUART1 clock
-  *            @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK  System Clock selected as LPUART1 clock
-  *            @arg @ref RCC_LPUART1CLKSOURCE_LSE  LSE selected as LPUART1 clock
-  * @retval None
-  */
-#define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__))
-
-/** @brief  Macro to get the LPUART1 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_LPUART1CLKSOURCE_PCLK1  PCLK1 selected as LPUART1 clock
-  *            @arg @ref RCC_LPUART1CLKSOURCE_HSI  HSI selected as LPUART1 clock
-  *            @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK  System Clock selected as LPUART1 clock
-  *            @arg @ref RCC_LPUART1CLKSOURCE_LSE  LSE selected as LPUART1 clock
-  */
-#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)))
-
-/** @brief  Macro to configure the LPTIM1 clock (LPTIM1CLK).
-  *
-  * @param  __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_LPTIM1CLKSOURCE_PCLK  PCLK selected as LPTIM1 clock
-  *            @arg @ref RCC_LPTIM1CLKSOURCE_LSI  HSI selected as LPTIM1 clock
-  *            @arg @ref RCC_LPTIM1CLKSOURCE_HSI  LSI selected as LPTIM1 clock
-  *            @arg @ref RCC_LPTIM1CLKSOURCE_LSE  LSE selected as LPTIM1 clock
-  * @retval None
-  */
-#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
-
-/** @brief  Macro to get the LPTIM1 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_LPTIM1CLKSOURCE_PCLK  PCLK selected as LPUART1 clock
-  *            @arg @ref RCC_LPTIM1CLKSOURCE_LSI  HSI selected as LPUART1 clock
-  *            @arg @ref RCC_LPTIM1CLKSOURCE_HSI  System Clock selected as LPUART1 clock
-  *            @arg @ref RCC_LPTIM1CLKSOURCE_LSE  LSE selected as LPUART1 clock
-  */
-#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)))
-
-/** @brief  Macro to configure the LPTIM2 clock (LPTIM2CLK).
-  *
-  * @param  __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_LPTIM2CLKSOURCE_PCLK  PCLK selected as LPTIM2 clock
-  *            @arg @ref RCC_LPTIM2CLKSOURCE_LSI  HSI selected as LPTIM2 clock
-  *            @arg @ref RCC_LPTIM2CLKSOURCE_HSI  LSI selected as LPTIM2 clock
-  *            @arg @ref RCC_LPTIM2CLKSOURCE_LSE  LSE selected as LPTIM2 clock
-  * @retval None
-  */
-#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__))
-
-/** @brief  Macro to get the LPTIM2 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_LPTIM2CLKSOURCE_PCLK  PCLK selected as LPUART1 clock
-  *            @arg @ref RCC_LPTIM2CLKSOURCE_LSI  HSI selected as LPUART1 clock
-  *            @arg @ref RCC_LPTIM2CLKSOURCE_HSI  System Clock selected as LPUART1 clock
-  *            @arg @ref RCC_LPTIM2CLKSOURCE_LSE  LSE selected as LPUART1 clock
-  */
-#define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL)))
-
-/** @brief  Macro to configure the SDMMC1 clock.
-  *
-  * @note  USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
-  *
-  * @param  __SDMMC1_CLKSOURCE__ specifies the SDMMC1 clock source.
-  *         This parameter can be one of the following values:
-  *            @arg @ref RCC_SDMMC1CLKSOURCE_NONE  No clock selected as SDMMC1 clock
-  *            @arg @ref RCC_SDMMC1CLKSOURCE_MSI  MSI selected as SDMMC1 clock
-  *            @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1  PLLSAI1 Clock selected as SDMMC1 clock
-  *            @arg @ref RCC_SDMMC1CLKSOURCE_PLL  PLL Clock selected as SDMMC1 clock
-  * @retval None
-  */
-#define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__SDMMC1_CLKSOURCE__))
-
-/** @brief  Macro to get the SDMMC1 clock.
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_SDMMC1CLKSOURCE_NONE  No clock selected as SDMMC1 clock
-  *            @arg @ref RCC_SDMMC1CLKSOURCE_MSI  MSI selected as SDMMC1 clock
-  *            @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1  PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock
-  *            @arg @ref RCC_SDMMC1CLKSOURCE_PLL  PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock
-  */
-#define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
-
-/** @brief  Macro to configure the RNG clock.
-  *
-  * @note  USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
-  *
-  * @param  __RNG_CLKSOURCE__ specifies the RNG clock source.
-  *         This parameter can be one of the following values:
-  *            @arg @ref RCC_RNGCLKSOURCE_NONE  No clock selected as RNG clock
-  *            @arg @ref RCC_RNGCLKSOURCE_MSI  MSI selected as RNG clock
-  *            @arg @ref RCC_RNGCLKSOURCE_PLLSAI1  PLLSAI1 Clock selected as RNG clock
-  *            @arg @ref RCC_RNGCLKSOURCE_PLL  PLL Clock selected as RNG clock
-  * @retval None
-  */
-#define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__RNG_CLKSOURCE__))
-
-/** @brief  Macro to get the RNG clock.
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_RNGCLKSOURCE_NONE  No clock selected as RNG clock
-  *            @arg @ref RCC_RNGCLKSOURCE_MSI  MSI selected as RNG clock
-  *            @arg @ref RCC_RNGCLKSOURCE_PLLSAI1  PLLSAI1 "Q" clock (PLL48M2CLK) selected as RNG clock
-  *            @arg @ref RCC_RNGCLKSOURCE_PLL  PLL "Q" clock (PLL48M1CLK) selected as RNG clock
-  */
-#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
-
-#if defined(USB_OTG_FS)
-
-/** @brief  Macro to configure the USB clock (USBCLK).
-  *
-  * @note  USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
-  *
-  * @param  __USB_CLKSOURCE__ specifies the USB clock source.
-  *         This parameter can be one of the following values:
-  *            @arg @ref RCC_USBCLKSOURCE_NONE  No clock selected as 48MHz clock
-  *            @arg @ref RCC_USBCLKSOURCE_MSI  MSI selected as USB clock
-  *            @arg @ref RCC_USBCLKSOURCE_PLLSAI1  PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock
-  *            @arg @ref RCC_USBCLKSOURCE_PLL  PLL "Q" clock (PLL48M1CLK) selected as USB clock
-  * @retval None
-  */
-#define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__USB_CLKSOURCE__))
-
-/** @brief  Macro to get the USB clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_USBCLKSOURCE_NONE  No clock selected as 48MHz clock
-  *            @arg @ref RCC_USBCLKSOURCE_MSI  MSI selected as USB clock
-  *            @arg @ref RCC_USBCLKSOURCE_PLLSAI1  PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock
-  *            @arg @ref RCC_USBCLKSOURCE_PLL  PLL "Q" clock (PLL48M1CLK) selected as USB clock
-  */
-#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
-
-#endif /* USB_OTG_FS */
-
-/** @brief  Macro to configure the ADC interface clock.
-  * @param  __ADC_CLKSOURCE__ specifies the ADC digital interface clock source.
-  *         This parameter can be one of the following values:
-  *            @arg @ref RCC_ADCCLKSOURCE_NONE  No clock selected as ADC clock
-  *            @arg @ref RCC_ADCCLKSOURCE_PLLSAI1  PLLSAI1 Clock selected as ADC clock
-  *            @arg @ref RCC_ADCCLKSOURCE_PLLSAI2  PLLSAI2 Clock selected as ADC clock
-  *            @arg @ref RCC_ADCCLKSOURCE_SYSCLK  System Clock selected as ADC clock
-  * @retval None
-  */
-#define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (uint32_t)(__ADC_CLKSOURCE__))
-
-/** @brief  Macro to get the ADC clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_ADCCLKSOURCE_NONE  No clock selected as ADC clock
-  *            @arg @ref RCC_ADCCLKSOURCE_PLLSAI1  PLLSAI1 Clock selected as ADC clock
-  *            @arg @ref RCC_ADCCLKSOURCE_PLLSAI2  PLLSAI2 Clock selected as ADC clock
-  *            @arg @ref RCC_ADCCLKSOURCE_SYSCLK  System Clock selected as ADC clock
-  */
-#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL)))
-
-/** @brief  Macro to configure the SWPMI1 clock.
-  * @param  __SWPMI1_CLKSOURCE__ specifies the SWPMI1 clock source.
-  *         This parameter can be one of the following values:
-  *            @arg @ref RCC_SWPMI1CLKSOURCE_PCLK  PCLK Clock selected as SWPMI1 clock
-  *            @arg @ref RCC_SWPMI1CLKSOURCE_HSI  HSI Clock selected as SWPMI1 clock
-  * @retval None
-  */
-#define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1_CLKSOURCE__) \
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, (uint32_t)(__SWPMI1_CLKSOURCE__))
-
-/** @brief  Macro to get the SWPMI1 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_SWPMI1CLKSOURCE_PCLK  PCLK Clock selected as SWPMI1 clock
-  *            @arg @ref RCC_SWPMI1CLKSOURCE_HSI  HSI Clock selected as SWPMI1 clock
-  */
-#define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL)))
-
-/** @brief  Macro to configure the DFSDM clock.
-  * @param  __DFSDM_CLKSOURCE__ specifies the DFSDM clock source.
-  *         This parameter can be one of the following values:
-  *            @arg @ref RCC_DFSDMCLKSOURCE_PCLK  PCLK Clock selected as DFSDM clock
-  *            @arg @ref RCC_DFSDMCLKSOURCE_SYSCLK  System Clock selected as DFSDM clock
-  * @retval None
-  */
-#define __HAL_RCC_DFSDM_CONFIG(__DFSDM_CLKSOURCE__) \
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDMSEL, (uint32_t)(__DFSDM_CLKSOURCE__))
-
-/** @brief  Macro to get the DFSDM clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_DFSDMCLKSOURCE_PCLK  PCLK Clock selected as DFSDM clock
-  *            @arg @ref RCC_DFSDMCLKSOURCE_SYSCLK  System Clock selected as DFSDM clock
-  */
-#define __HAL_RCC_GET_DFSDM_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_DFSDMSEL)))
-
-/** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management
-  * @brief macros to manage the specified RCC Flags and interrupts.
-  * @{
-  */
-
-/** @brief Enable PLLSAI1RDY interrupt.
-  * @retval None
-  */
-#define __HAL_RCC_PLLSAI1_ENABLE_IT()  SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE)
-
-/** @brief Disable PLLSAI1RDY interrupt.
-  * @retval None
-  */
-#define __HAL_RCC_PLLSAI1_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE)
-
-/** @brief Clear the PLLSAI1RDY interrupt pending bit.
-  * @retval None
-  */
-#define __HAL_RCC_PLLSAI1_CLEAR_IT()   WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI1RDYC)
-
-/** @brief Check whether PLLSAI1RDY interrupt has occurred or not.
-  * @retval TRUE or FALSE.
-  */
-#define __HAL_RCC_PLLSAI1_GET_IT_SOURCE()     (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == RCC_CIFR_PLLSAI1RDYF)
-
-/** @brief  Check whether the PLLSAI1RDY flag is set or not.
-  * @retval TRUE or FALSE.
-  */
-#define __HAL_RCC_PLLSAI1_GET_FLAG()   (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY))
-
-/** @brief Enable PLLSAI2RDY interrupt.
-  * @retval None
-  */
-#define __HAL_RCC_PLLSAI2_ENABLE_IT()  SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE)
-
-/** @brief Disable PLLSAI2RDY interrupt.
-  * @retval None
-  */
-#define __HAL_RCC_PLLSAI2_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE)
-
-/** @brief Clear the PLLSAI2RDY interrupt pending bit.
-  * @retval None
-  */
-#define __HAL_RCC_PLLSAI2_CLEAR_IT()   WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI2RDYC)
-
-/** @brief Check whether the PLLSAI2RDY interrupt has occurred or not.
-  * @retval TRUE or FALSE.
-  */
-#define __HAL_RCC_PLLSAI2_GET_IT_SOURCE()     (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == RCC_CIFR_PLLSAI2RDYF)
-
-/** @brief  Check whether the PLLSAI2RDY flag is set or not.
-  * @retval TRUE or FALSE.
-  */
-#define __HAL_RCC_PLLSAI2_GET_FLAG()   (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY))
-
-/**
-  * @brief Enable the RCC LSE CSS Extended Interrupt Line.
-  * @retval None
-  */
-#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT()      SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
-
-/**
-  * @brief Disable the RCC LSE CSS Extended Interrupt Line.
-  * @retval None
-  */
-#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT()     CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
-
-/**
-  * @brief Enable the RCC LSE CSS Event Line.
-  * @retval None.
-  */
-#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
-
-/**
-  * @brief Disable the RCC LSE CSS Event Line.
-  * @retval None.
-  */
-#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
-
-
-/**
-  * @brief  Enable the RCC LSE CSS Extended Interrupt Falling Trigger.
-  * @retval None.
-  */
-#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE()  SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
-
-
-/**
-  * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
-  * @retval None.
-  */
-#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
-
-
-/**
-  * @brief  Enable the RCC LSE CSS Extended Interrupt Rising Trigger.
-  * @retval None.
-  */
-#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
-
-/**
-  * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
-  * @retval None.
-  */
-#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
-
-/**
-  * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
-  * @retval None.
-  */
-#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE()  \
-  do {                                                      \
-    __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();             \
-    __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE();            \
-  } while(0)  
-  
-/**
-  * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
-  * @retval None.
-  */
-#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE()  \
-  do {                                                       \
-    __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE();             \
-    __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE();            \
-  } while(0)  
-
-/**
-  * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
-  * @retval EXTI RCC LSE CSS Line Status.
-  */
-#define __HAL_RCC_LSECSS_EXTI_GET_FLAG()       (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
-
-/**
-  * @brief Clear the RCC LSE CSS EXTI flag.
-  * @retval None.
-  */
-#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG()     WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)
-
-/**
-  * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line.
-  * @retval None.
-  */
-#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT()  SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RCCEx_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup RCCEx_Exported_Functions_Group1
-  * @{
-  */
-
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
-void              HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
-uint32_t          HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
-
-/**
-  * @}
-  */
-
-/** @addtogroup RCCEx_Exported_Functions_Group2
-  * @{
-  */
-
-HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef  *PLLSAI1Init);
-HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void);
-
-HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef  *PLLSAI2Init);
-HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void);
-
-void              HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk);
-void              HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange);
-void              HAL_RCCEx_EnableLSECSS(void);
-void              HAL_RCCEx_DisableLSECSS(void);
-void              HAL_RCCEx_EnableLSECSS_IT(void);
-void              HAL_RCCEx_LSECSS_IRQHandler(void);
-void              HAL_RCCEx_LSECSS_Callback(void);
-void              HAL_RCCEx_EnableLSCO(uint32_t LSCOSource);
-void              HAL_RCCEx_DisableLSCO(void);
-void              HAL_RCCEx_EnableMSIPLLMode(void);
-void              HAL_RCCEx_DisableMSIPLLMode(void);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup RCCEx_Private_Macros
-  * @{
-  */
-
-#define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \
-                                       ((__SOURCE__) == RCC_LSCOSOURCE_LSE))
-
-#if defined(STM32L471xx)
-
-#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
-               ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \
-                (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \
-                (((__SELECTION__) & RCC_PERIPHCLK_USART3)  == RCC_PERIPHCLK_USART3)  || \
-                (((__SELECTION__) & RCC_PERIPHCLK_UART4)   == RCC_PERIPHCLK_UART4)   || \
-                (((__SELECTION__) & RCC_PERIPHCLK_UART5)   == RCC_PERIPHCLK_UART5)   || \
-                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C2)    == RCC_PERIPHCLK_I2C2)    || \
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)    == RCC_PERIPHCLK_I2C3)    || \
-                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \
-                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \
-                (((__SELECTION__) & RCC_PERIPHCLK_SAI1)    == RCC_PERIPHCLK_SAI1)    || \
-                (((__SELECTION__) & RCC_PERIPHCLK_SAI2)    == RCC_PERIPHCLK_SAI2)    || \
-                (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \
-                (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1)  == RCC_PERIPHCLK_SWPMI1)  || \
-                (((__SELECTION__) & RCC_PERIPHCLK_DFSDM)   == RCC_PERIPHCLK_DFSDM)   || \
-                (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \
-                (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG)     || \
-                (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1)  == RCC_PERIPHCLK_SDMMC1))
-
-#else
-
-#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
-               ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \
-                (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \
-                (((__SELECTION__) & RCC_PERIPHCLK_USART3)  == RCC_PERIPHCLK_USART3)  || \
-                (((__SELECTION__) & RCC_PERIPHCLK_UART4)   == RCC_PERIPHCLK_UART4)   || \
-                (((__SELECTION__) & RCC_PERIPHCLK_UART5)   == RCC_PERIPHCLK_UART5)   || \
-                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C2)    == RCC_PERIPHCLK_I2C2)    || \
-                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)    == RCC_PERIPHCLK_I2C3)    || \
-                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \
-                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \
-                (((__SELECTION__) & RCC_PERIPHCLK_SAI1)    == RCC_PERIPHCLK_SAI1)    || \
-                (((__SELECTION__) & RCC_PERIPHCLK_SAI2)    == RCC_PERIPHCLK_SAI2)    || \
-                (((__SELECTION__) & RCC_PERIPHCLK_USB)     == RCC_PERIPHCLK_USB)     || \
-                (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \
-                (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1)  == RCC_PERIPHCLK_SWPMI1)  || \
-                (((__SELECTION__) & RCC_PERIPHCLK_DFSDM)   == RCC_PERIPHCLK_DFSDM)   || \
-                (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \
-                (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG)     || \
-                (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1)  == RCC_PERIPHCLK_SDMMC1))
-
-#endif /* STM32L471xx */
-
-#define IS_RCC_USART1CLKSOURCE(__SOURCE__)  \
-               (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2)  || \
-                ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
-                ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE)    || \
-                ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
-
-#define IS_RCC_USART2CLKSOURCE(__SOURCE__)  \
-               (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1)  || \
-                ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
-                ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE)    || \
-                ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
-
-#define IS_RCC_USART3CLKSOURCE(__SOURCE__)  \
-               (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1)  || \
-                ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \
-                ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE)    || \
-                ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI))
-
-#define IS_RCC_UART4CLKSOURCE(__SOURCE__)  \
-               (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1)  || \
-                ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \
-                ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE)    || \
-                ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI))
-
-#define IS_RCC_UART5CLKSOURCE(__SOURCE__)  \
-               (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1)  || \
-                ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \
-                ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE)    || \
-                ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI))
-
-#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__)  \
-               (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1)  || \
-                ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
-                ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE)    || \
-                ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
-
-#define IS_RCC_I2C1CLKSOURCE(__SOURCE__)   \
-               (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
-                ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
-                ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
-
-#define IS_RCC_I2C2CLKSOURCE(__SOURCE__)   \
-               (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \
-                ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \
-                ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI))
-
-#define IS_RCC_I2C3CLKSOURCE(__SOURCE__)   \
-               (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \
-                ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
-                ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
-
-#define IS_RCC_SAI1CLK(__SOURCE__)   \
-               (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \
-                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \
-                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL)     || \
-                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))
-
-#define IS_RCC_SAI2CLK(__SOURCE__)   \
-               (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) || \
-                ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \
-                ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL)     || \
-                ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN))
-
-#define IS_RCC_LPTIM1CLK(__SOURCE__)  \
-               (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK) || \
-                ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI)  || \
-                ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI)  || \
-                ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE))
-
-#define IS_RCC_LPTIM2CLK(__SOURCE__)  \
-               (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK) || \
-                ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI)  || \
-                ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI)  || \
-                ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE))
-
-#define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__)  \
-               (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_NONE)    || \
-                ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \
-                ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL)     || \
-                ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI))
-
-#define IS_RCC_RNGCLKSOURCE(__SOURCE__)  \
-               (((__SOURCE__) == RCC_RNGCLKSOURCE_NONE)    || \
-                ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \
-                ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL)     || \
-                ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI))
-
-#if defined(USB_OTG_FS)
-
-#define IS_RCC_USBCLKSOURCE(__SOURCE__)  \
-               (((__SOURCE__) == RCC_USBCLKSOURCE_NONE)    || \
-                ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \
-                ((__SOURCE__) == RCC_USBCLKSOURCE_PLL)     || \
-                ((__SOURCE__) == RCC_USBCLKSOURCE_MSI))
-
-#endif /* USB_OTG_FS */
-
-#define IS_RCC_ADCCLKSOURCE(__SOURCE__)  \
-               (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE)    || \
-                ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \
-                ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI2) || \
-                ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))
-
-#define IS_RCC_SWPMI1CLKSOURCE(__SOURCE__)  \
-               (((__SOURCE__) == RCC_SWPMI1CLKSOURCE_PCLK) || \
-                ((__SOURCE__) == RCC_SWPMI1CLKSOURCE_HSI))
-
-#define IS_RCC_DFSDMCLKSOURCE(__SOURCE__)  \
-               (((__SOURCE__) == RCC_DFSDMCLKSOURCE_PCLK) || \
-                ((__SOURCE__) == RCC_DFSDMCLKSOURCE_SYSCLK))
-
-#define IS_RCC_PLLSAI1N_VALUE(__VALUE__)   ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
-
-#define IS_RCC_PLLSAI1P_VALUE(__VALUE__)   (((__VALUE__) == 7U) || ((__VALUE__) == 17U))
-
-#define IS_RCC_PLLSAI1Q_VALUE(__VALUE__)   (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
-                                            ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
-
-#define IS_RCC_PLLSAI1R_VALUE(__VALUE__)   (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
-                                            ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
-
-#define IS_RCC_PLLSAI2N_VALUE(__VALUE__)   ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
-
-#define IS_RCC_PLLSAI2P_VALUE(__VALUE__)   (((__VALUE__) == 7U) || ((__VALUE__) == 17U))
-
-#define IS_RCC_PLLSAI2R_VALUE(__VALUE__)   (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
-                                            ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L4xx_HAL_RCC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/inc/stm32l4xx_hal_rng.h b/stmhal/hal/l4/inc/stm32l4xx_hal_rng.h
deleted file mode 100644
index dbaa0dbb71..0000000000
--- a/stmhal/hal/l4/inc/stm32l4xx_hal_rng.h
+++ /dev/null
@@ -1,285 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_rng.h
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   Header file of RNG HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L4xx_HAL_RNG_H
-#define __STM32L4xx_HAL_RNG_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup RNG
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup RNG_Exported_Types RNG Exported Types
-  * @{
-  */
-
-/** 
-  * @brief  RNG HAL State Structure definition  
-  */ 
-typedef enum
-{
-  HAL_RNG_STATE_RESET     = 0x00,  /*!< RNG not yet initialized or disabled */
-  HAL_RNG_STATE_READY     = 0x01,  /*!< RNG initialized and ready for use   */
-  HAL_RNG_STATE_BUSY      = 0x02,  /*!< RNG internal process is ongoing     */ 
-  HAL_RNG_STATE_TIMEOUT   = 0x03,  /*!< RNG timeout state                   */
-  HAL_RNG_STATE_ERROR     = 0x04   /*!< RNG error state                     */
-    
-}HAL_RNG_StateTypeDef;
-
-/** 
-  * @brief  RNG Handle Structure definition  
-  */ 
-typedef struct
-{
-  RNG_TypeDef                 *Instance;  /*!< Register base address   */ 
-  
-  HAL_LockTypeDef             Lock;       /*!< RNG locking object      */
-  
-  __IO HAL_RNG_StateTypeDef   State;      /*!< RNG communication state */
-  
-  uint32_t               RandomNumber;    /*!< Last Generated RNG Data */
-  
-}RNG_HandleTypeDef;
-
-/** 
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RNG_Exported_Constants RNG Exported Constants
-  * @{
-  */
-
-/** @defgroup RNG_Interrupt_definition  RNG Interrupts Definition
-  * @{
-  */
-#define RNG_IT_DRDY  RNG_SR_DRDY  /*!< Data Ready interrupt  */
-#define RNG_IT_CEI   RNG_SR_CEIS  /*!< Clock error interrupt */
-#define RNG_IT_SEI   RNG_SR_SEIS  /*!< Seed error interrupt  */
-/**
-  * @}
-  */
-
-/** @defgroup RNG_Flag_definition  RNG Flags Definition
-  * @{
-  */ 
-#define RNG_FLAG_DRDY   RNG_SR_DRDY  /*!< Data ready                 */
-#define RNG_FLAG_CECS   RNG_SR_CECS  /*!< Clock error current status */
-#define RNG_FLAG_SECS   RNG_SR_SECS  /*!< Seed error current status  */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-  
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup RNG_Exported_Macros RNG Exported Macros
-  * @{
-  */
-
-/** @brief Reset RNG handle state.
-  * @param  __HANDLE__: RNG Handle
-  * @retval None
-  */
-#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
-
-/**
-  * @brief  Enable the RNG peripheral.
-  * @param  __HANDLE__: RNG Handle
-  * @retval None
-  */
-#define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_RNGEN)
-
-/**
-  * @brief  Disable the RNG peripheral.
-  * @param  __HANDLE__: RNG Handle
-  * @retval None
-  */
-#define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
-
-/**
-  * @brief  Check whether the specified RNG flag is set or not.
-  * @param  __HANDLE__: RNG Handle
-  * @param  __FLAG__: RNG flag
-  *          This parameter can be one of the following values:
-  *            @arg RNG_FLAG_DRDY:  Data ready                
-  *            @arg RNG_FLAG_CECS:  Clock error current status
-  *            @arg RNG_FLAG_SECS:  Seed error current status 
-  * @retval The new state of __FLAG__ (SET or RESET).
-  */
-#define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-
-
-/**
-  * @brief  Clear the selected RNG flag status.
-  * @param  __HANDLE__: RNG handle
-  * @param  __FLAG__: RNG flag to clear  
-  * @note   WARNING: This is a dummy macro for HAL code alignment,
-  *         flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
-  * @retval None
-  */
-#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__)                      /* dummy  macro */
-
-
-
-/**
-  * @brief  Enable the RNG interrupt.
-  * @param  __HANDLE__: RNG Handle
-  * @retval None
-  */
-#define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_IE)
-    
-/**
-  * @brief  Disable the RNG interrupt.
-  * @param  __HANDLE__: RNG Handle
-  * @retval None
-  */
-#define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
-
-/**
-  * @brief  Check whether the specified RNG interrupt has occurred or not.
-  * @param  __HANDLE__: RNG Handle
-  * @param  __INTERRUPT__: specifies the RNG interrupt status flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg RNG_IT_DRDY: Data ready interrupt              
-  *            @arg RNG_IT_CEI: Clock error interrupt
-  *            @arg RNG_IT_SEI: Seed error interrupt
-  * @retval The new state of __INTERRUPT__ (SET or RESET).
-  */
-#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))   
-
-/**
-  * @brief  Clear the RNG interrupt status flags.
-  * @param  __HANDLE__: RNG Handle
-  * @param  __INTERRUPT__: specifies the RNG interrupt status flag to clear.
-  *          This parameter can be one of the following values:            
-  *            @arg RNG_IT_CEI: Clock error interrupt
-  *            @arg RNG_IT_SEI: Seed error interrupt
-  * @note   RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.          
-  * @retval None
-  */
-#define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
-
-/**
-  * @}
-  */ 
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup RNG_Exported_Functions RNG Exported Functions
-  * @{
-  */
-
-/* Initialization and de-initialization functions  ******************************/
-/** @defgroup RNG_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */  
-HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);
-HAL_StatusTypeDef HAL_RNG_DeInit (RNG_HandleTypeDef *hrng);
-void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
-void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
-/**
-  * @}
-  */ 
-
-/* Peripheral Control functions  ************************************************/
-/** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions
-  * @{
-  */
-uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng);    /* Obsolete, use HAL_RNG_GenerateRandomNumber() instead    */
-uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber_IT() instead */
-
-HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
-HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
-uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);
-
-void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
-void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
-void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef* hrng, uint32_t random32bit);
-/**
-  * @}
-  */ 
-
-/* Peripheral State functions  **************************************************/
-/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions
-  * @{
-  */
-HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private defines -----------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private functions prototypes ----------------------------------------------*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L4xx_HAL_RNG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/inc/stm32l4xx_hal_rtc.h b/stmhal/hal/l4/inc/stm32l4xx_hal_rtc.h
deleted file mode 100644
index f102007b2c..0000000000
--- a/stmhal/hal/l4/inc/stm32l4xx_hal_rtc.h
+++ /dev/null
@@ -1,863 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_rtc.h
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   Header file of RTC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L4xx_HAL_RTC_H
-#define __STM32L4xx_HAL_RTC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup RTC
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup RTC_Exported_Types RTC Exported Types
-  * @{
-  */
-/** 
-  * @brief  HAL State structures definition  
-  */
-typedef enum
-{
-  HAL_RTC_STATE_RESET             = 0x00,  /*!< RTC not yet initialized or disabled */
-  HAL_RTC_STATE_READY             = 0x01,  /*!< RTC initialized and ready for use   */
-  HAL_RTC_STATE_BUSY              = 0x02,  /*!< RTC process is ongoing              */
-  HAL_RTC_STATE_TIMEOUT           = 0x03,  /*!< RTC timeout state                   */
-  HAL_RTC_STATE_ERROR             = 0x04   /*!< RTC error state                     */
-
-}HAL_RTCStateTypeDef;
-
-/** 
-  * @brief  RTC Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t HourFormat;      /*!< Specifies the RTC Hour Format.
-                                 This parameter can be a value of @ref RTC_Hour_Formats */
-
-  uint32_t AsynchPrediv;    /*!< Specifies the RTC Asynchronous Predivider value.
-                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
-                               
-  uint32_t SynchPrediv;     /*!< Specifies the RTC Synchronous Predivider value.
-                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
-
-  uint32_t OutPut;          /*!< Specifies which signal will be routed to the RTC output.
-                                 This parameter can be a value of @ref RTCEx_Output_selection_Definitions */
-
-  uint32_t OutPutRemap;    /*!< Specifies the remap for RTC output.
-                                 This parameter can be a value of @ref  RTC_Output_ALARM_OUT_Remap */
-
-  uint32_t OutPutPolarity;  /*!< Specifies the polarity of the output signal.  
-                                 This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
-
-  uint32_t OutPutType;      /*!< Specifies the RTC Output Pin mode.
-                                 This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
-}RTC_InitTypeDef;
-
-/** 
-  * @brief  RTC Time structure definition  
-  */
-typedef struct
-{
-  uint8_t Hours;            /*!< Specifies the RTC Time Hour.
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
-
-  uint8_t Minutes;          /*!< Specifies the RTC Time Minutes.
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
-
-  uint8_t Seconds;          /*!< Specifies the RTC Time Seconds.
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
-
-  uint8_t TimeFormat;       /*!< Specifies the RTC AM/PM Time.
-                                 This parameter can be a value of @ref RTC_AM_PM_Definitions */
-  
-  uint32_t SubSeconds;     /*!< Specifies the RTC_SSR RTC Sub Second register content.
-                                 This parameter corresponds to a time unit range between [0-1] Second
-                                 with [1 Sec / SecondFraction +1] granularity */
- 
-  uint32_t SecondFraction;  /*!< Specifies the range or granularity of Sub Second register content
-                                 corresponding to Synchronous pre-scaler factor value (PREDIV_S)
-                                 This parameter corresponds to a time unit range between [0-1] Second
-                                 with [1 Sec / SecondFraction +1] granularity.
-                                 This field will be used only by HAL_RTC_GetTime function */
-  
-  uint32_t DayLightSaving;  /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment.
-                                 This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
-
-  uint32_t StoreOperation;  /*!< Specifies RTC_StoreOperation value to be written in the BCK bit 
-                                 in CR register to store the operation.
-                                 This parameter can be a value of @ref RTC_StoreOperation_Definitions */
-}RTC_TimeTypeDef;
-
-/** 
-  * @brief  RTC Date structure definition
-  */
-typedef struct
-{
-  uint8_t WeekDay;  /*!< Specifies the RTC Date WeekDay.
-                         This parameter can be a value of @ref RTC_WeekDay_Definitions */
-
-  uint8_t Month;    /*!< Specifies the RTC Date Month (in BCD format).
-                         This parameter can be a value of @ref RTC_Month_Date_Definitions */
-
-  uint8_t Date;     /*!< Specifies the RTC Date.
-                         This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
-
-  uint8_t Year;     /*!< Specifies the RTC Date Year.
-                         This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
-
-}RTC_DateTypeDef;
-
-/** 
-  * @brief  RTC Alarm structure definition
-  */
-typedef struct
-{
-  RTC_TimeTypeDef AlarmTime;     /*!< Specifies the RTC Alarm Time members */
-
-  uint32_t AlarmMask;            /*!< Specifies the RTC Alarm Masks.
-                                      This parameter can be a value of @ref RTC_AlarmMask_Definitions */
-  
-  uint32_t AlarmSubSecondMask;   /*!< Specifies the RTC Alarm SubSeconds Masks.
-                                      This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
-
-  uint32_t AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on Date or WeekDay.
-                                     This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
-
-  uint8_t AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Date/WeekDay.
-                                      If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
-                                      If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
-
-  uint32_t Alarm;                /*!< Specifies the alarm .
-                                      This parameter can be a value of @ref RTC_Alarms_Definitions */
-}RTC_AlarmTypeDef;
-
-/** 
-  * @brief  Time Handle Structure definition
-  */
-typedef struct
-{
-  RTC_TypeDef               *Instance;  /*!< Register base address    */
-
-  RTC_InitTypeDef           Init;       /*!< RTC required parameters  */
-
-  HAL_LockTypeDef           Lock;       /*!< RTC locking object       */
-
-  __IO HAL_RTCStateTypeDef  State;      /*!< Time communication state */
-
-}RTC_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RTC_Exported_Constants RTC Exported Constants
-  * @{
-  */
-
-/** @defgroup RTC_Hour_Formats RTC Hour Formats
-  * @{
-  */
-#define RTC_HOURFORMAT_24              ((uint32_t)0x00000000)
-#define RTC_HOURFORMAT_12              ((uint32_t)0x00000040)
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
-  * @{
-  */
-#define RTC_OUTPUT_POLARITY_HIGH       ((uint32_t)0x00000000)
-#define RTC_OUTPUT_POLARITY_LOW        ((uint32_t)0x00100000)
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
-  * @{
-  */
-#define RTC_OUTPUT_TYPE_OPENDRAIN      ((uint32_t)0x00000000)
-#define RTC_OUTPUT_TYPE_PUSHPULL       ((uint32_t)RTC_OR_ALARMOUTTYPE)
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Output_ALARM_OUT_Remap RTC Output ALARM OUT Remap
-  * @{
-  */
-#define RTC_OUTPUT_REMAP_NONE          ((uint32_t)0x00000000)
-#define RTC_OUTPUT_REMAP_POS1          ((uint32_t)RTC_OR_OUT_RMP)
-/**
-  * @}
-  */
-
-/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
-  * @{
-  */
-#define RTC_HOURFORMAT12_AM            ((uint8_t)0x00)
-#define RTC_HOURFORMAT12_PM            ((uint8_t)0x40)
-/**
-  * @}
-  */
-
-/** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions
-  * @{
-  */
-#define RTC_DAYLIGHTSAVING_SUB1H       ((uint32_t)0x00020000)
-#define RTC_DAYLIGHTSAVING_ADD1H       ((uint32_t)0x00010000)
-#define RTC_DAYLIGHTSAVING_NONE        ((uint32_t)0x00000000)
-/**
-  * @}
-  */
-
-/** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions
-  * @{
-  */
-#define RTC_STOREOPERATION_RESET        ((uint32_t)0x00000000)
-#define RTC_STOREOPERATION_SET          ((uint32_t)0x00040000)
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions
-  * @{
-  */
-#define RTC_FORMAT_BIN                  ((uint32_t)0x000000000)
-#define RTC_FORMAT_BCD                  ((uint32_t)0x000000001)
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
-  * @{
-  */
-
-/* Coded in BCD format */
-#define RTC_MONTH_JANUARY              ((uint8_t)0x01)
-#define RTC_MONTH_FEBRUARY             ((uint8_t)0x02)
-#define RTC_MONTH_MARCH                ((uint8_t)0x03)
-#define RTC_MONTH_APRIL                ((uint8_t)0x04)
-#define RTC_MONTH_MAY                  ((uint8_t)0x05)
-#define RTC_MONTH_JUNE                 ((uint8_t)0x06)
-#define RTC_MONTH_JULY                 ((uint8_t)0x07)
-#define RTC_MONTH_AUGUST               ((uint8_t)0x08)
-#define RTC_MONTH_SEPTEMBER            ((uint8_t)0x09)
-#define RTC_MONTH_OCTOBER              ((uint8_t)0x10)
-#define RTC_MONTH_NOVEMBER             ((uint8_t)0x11)
-#define RTC_MONTH_DECEMBER             ((uint8_t)0x12)
-/**
-  * @}
-  */
-
-/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
-  * @{
-  */
-#define RTC_WEEKDAY_MONDAY             ((uint8_t)0x01)
-#define RTC_WEEKDAY_TUESDAY            ((uint8_t)0x02)
-#define RTC_WEEKDAY_WEDNESDAY          ((uint8_t)0x03)
-#define RTC_WEEKDAY_THURSDAY           ((uint8_t)0x04)
-#define RTC_WEEKDAY_FRIDAY             ((uint8_t)0x05)
-#define RTC_WEEKDAY_SATURDAY           ((uint8_t)0x06)
-#define RTC_WEEKDAY_SUNDAY             ((uint8_t)0x07)
-/**
-  * @}
-  */
-
-/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions
-  * @{
-  */
-#define RTC_ALARMDATEWEEKDAYSEL_DATE      ((uint32_t)0x00000000)
-#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY   ((uint32_t)0x40000000)
-/**
-  * @}
-  */
-
-
-/** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions
-  * @{
-  */
-#define RTC_ALARMMASK_NONE                ((uint32_t)0x00000000)
-#define RTC_ALARMMASK_DATEWEEKDAY         RTC_ALRMAR_MSK4
-#define RTC_ALARMMASK_HOURS               RTC_ALRMAR_MSK3
-#define RTC_ALARMMASK_MINUTES             RTC_ALRMAR_MSK2
-#define RTC_ALARMMASK_SECONDS             RTC_ALRMAR_MSK1
-#define RTC_ALARMMASK_ALL                 ((uint32_t)0x80808080)
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
-  * @{
-  */
-#define RTC_ALARM_A                       RTC_CR_ALRAE
-#define RTC_ALARM_B                       RTC_CR_ALRBE
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
-  * @{
-  */
-#define RTC_ALARMSUBSECONDMASK_ALL         ((uint32_t)0x00000000)  /*!< All Alarm SS fields are masked.
-                                                                        There is no comparison on sub seconds
-                                                                        for Alarm */
-#define RTC_ALARMSUBSECONDMASK_SS14_1      ((uint32_t)0x01000000)  /*!< SS[14:1] are don't care in Alarm
-                                                                        comparison. Only SS[0] is compared.    */
-#define RTC_ALARMSUBSECONDMASK_SS14_2      ((uint32_t)0x02000000)  /*!< SS[14:2] are don't care in Alarm
-                                                                        comparison. Only SS[1:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_3      ((uint32_t)0x03000000)  /*!< SS[14:3] are don't care in Alarm
-                                                                        comparison. Only SS[2:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_4      ((uint32_t)0x04000000)  /*!< SS[14:4] are don't care in Alarm
-                                                                        comparison. Only SS[3:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_5      ((uint32_t)0x05000000)  /*!< SS[14:5] are don't care in Alarm
-                                                                        comparison. Only SS[4:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_6      ((uint32_t)0x06000000)  /*!< SS[14:6] are don't care in Alarm
-                                                                        comparison. Only SS[5:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_7      ((uint32_t)0x07000000)  /*!< SS[14:7] are don't care in Alarm
-                                                                        comparison. Only SS[6:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_8      ((uint32_t)0x08000000)  /*!< SS[14:8] are don't care in Alarm
-                                                                        comparison. Only SS[7:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_9      ((uint32_t)0x09000000)  /*!< SS[14:9] are don't care in Alarm
-                                                                        comparison. Only SS[8:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_10     ((uint32_t)0x0A000000)  /*!< SS[14:10] are don't care in Alarm
-                                                                        comparison. Only SS[9:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_11     ((uint32_t)0x0B000000)  /*!< SS[14:11] are don't care in Alarm
-                                                                        comparison. Only SS[10:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_12     ((uint32_t)0x0C000000)  /*!< SS[14:12] are don't care in Alarm
-                                                                        comparison. Only SS[11:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_13     ((uint32_t)0x0D000000)  /*!< SS[14:13] are don't care in Alarm
-                                                                        comparison. Only SS[12:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14        ((uint32_t)0x0E000000)  /*!< SS[14] is don't care in Alarm
-                                                                        comparison. Only SS[13:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_NONE        ((uint32_t)0x0F000000)  /*!< SS[14:0] are compared and must match
-                                                                        to activate alarm. */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
-  * @{
-  */
-#define RTC_IT_TS                         ((uint32_t)RTC_CR_TSIE)        /*!< Enable Timestamp Interrupt    */
-#define RTC_IT_WUT                        ((uint32_t)RTC_CR_WUTIE)       /*!< Enable Wakeup timer Interrupt */
-#define RTC_IT_ALRA                       ((uint32_t)RTC_CR_ALRAIE)      /*!< Enable Alarm A Interrupt      */
-#define RTC_IT_ALRB                       ((uint32_t)RTC_CR_ALRBIE)      /*!< Enable Alarm B Interrupt      */
-#define RTC_IT_TAMP                       ((uint32_t)RTC_TAMPCR_TAMPIE)  /*!< Enable all Tamper Interrupt   */
-#define RTC_IT_TAMP1                      ((uint32_t)RTC_TAMPCR_TAMP1IE) /*!< Enable Tamper 1 Interrupt     */
-#define RTC_IT_TAMP2                      ((uint32_t)RTC_TAMPCR_TAMP2IE) /*!< Enable Tamper 2 Interrupt     */
-#define RTC_IT_TAMP3                      ((uint32_t)RTC_TAMPCR_TAMP3IE) /*!< Enable Tamper 3 Interrupt     */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Flags_Definitions RTC Flags Definitions
-  * @{
-  */
-#define RTC_FLAG_RECALPF                  ((uint32_t)RTC_ISR_RECALPF)
-#define RTC_FLAG_TAMP3F                   ((uint32_t)RTC_ISR_TAMP3F)
-#define RTC_FLAG_TAMP2F                   ((uint32_t)RTC_ISR_TAMP2F)
-#define RTC_FLAG_TAMP1F                   ((uint32_t)RTC_ISR_TAMP1F)
-#define RTC_FLAG_TSOVF                    ((uint32_t)RTC_ISR_TSOVF)
-#define RTC_FLAG_TSF                      ((uint32_t)RTC_ISR_TSF)
-#define RTC_FLAG_ITSF                     ((uint32_t)RTC_ISR_ITSF)
-#define RTC_FLAG_WUTF                     ((uint32_t)RTC_ISR_WUTF)
-#define RTC_FLAG_ALRBF                    ((uint32_t)RTC_ISR_ALRBF)
-#define RTC_FLAG_ALRAF                    ((uint32_t)RTC_ISR_ALRAF)
-#define RTC_FLAG_INITF                    ((uint32_t)RTC_ISR_INITF)
-#define RTC_FLAG_RSF                      ((uint32_t)RTC_ISR_RSF)
-#define RTC_FLAG_INITS                    ((uint32_t)RTC_ISR_INITS)
-#define RTC_FLAG_SHPF                     ((uint32_t)RTC_ISR_SHPF)
-#define RTC_FLAG_WUTWF                    ((uint32_t)RTC_ISR_WUTWF)
-#define RTC_FLAG_ALRBWF                   ((uint32_t)RTC_ISR_ALRBWF)
-#define RTC_FLAG_ALRAWF                   ((uint32_t)RTC_ISR_ALRAWF)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup RTC_Exported_Macros RTC Exported Macros
-  * @{
-  */
-
-/** @brief Reset RTC handle state.
-  * @param  __HANDLE__: RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
-
-/**
-  * @brief  Disable the write protection for RTC registers.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)             \
-                        do{                                       \
-                            (__HANDLE__)->Instance->WPR = 0xCA;   \
-                            (__HANDLE__)->Instance->WPR = 0x53;   \
-                          } while(0)
-
-/**
-  * @brief  Enable the write protection for RTC registers.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)              \
-                        do{                                       \
-                            (__HANDLE__)->Instance->WPR = 0xFF;   \
-                          } while(0)
-
-
-/**
-  * @brief  Enable the RTC ALARMA peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__)                          ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
-
-/**
-  * @brief  Disable the RTC ALARMA peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__)                         ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
-
-/**
-  * @brief  Enable the RTC ALARMB peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__)                          ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
-
-/**
-  * @brief  Disable the RTC ALARMB peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__)                         ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
-
-/**
-  * @brief  Enable the RTC Alarm interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
-  *          This parameter can be any combination of the following values:
-  *             @arg RTC_IT_ALRA: Alarm A interrupt
-  *             @arg RTC_IT_ALRB: Alarm B interrupt
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the RTC Alarm interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
-  *         This parameter can be any combination of the following values:
-  *            @arg RTC_IT_ALRA: Alarm A interrupt
-  *            @arg RTC_IT_ALRB: Alarm B interrupt
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__)        ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
-
-/**
-  * @brief  Check whether the specified RTC Alarm interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to check.
-  *         This parameter can be:
-  *            @arg RTC_IT_ALRA: Alarm A interrupt
-  *            @arg RTC_IT_ALRB: Alarm B interrupt
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__)            (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
-
-/**
-  * @brief  Get the selected RTC Alarm's flag status.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Alarm Flag sources to check.
-  *         This parameter can be:
-  *            @arg RTC_FLAG_ALRAF
-  *            @arg RTC_FLAG_ALRBF
-  *            @arg RTC_FLAG_ALRAWF
-  *            @arg RTC_FLAG_ALRBWF
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__)               (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
-
-/**
-  * @brief  Clear the RTC Alarm's pending flags.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Alarm Flag sources to clear.
-  *          This parameter can be:
-  *             @arg RTC_FLAG_ALRAF
-  *             @arg RTC_FLAG_ALRBF
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)             ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-/**
-  * @brief  Check whether the specified RTC Alarm interrupt is enabled or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to check.
-  *         This parameter can be:
-  *            @arg RTC_IT_ALRA: Alarm A interrupt
-  *            @arg RTC_IT_ALRB: Alarm B interrupt
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
-
-/**
-  * @brief  Enable interrupt on the RTC Alarm associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_IT()            (EXTI->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
-  * @brief  Disable interrupt on the RTC Alarm associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_IT()           (EXTI->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
-
-/**
-  * @brief  Enable event on the RTC Alarm associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT()         (EXTI->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
-  * @brief  Disable event on the RTC Alarm associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT()         (EXTI->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
-
-/**
-  * @brief  Enable falling edge trigger on the RTC Alarm associated Exti line.  
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
-  * @brief  Disable falling edge trigger on the RTC Alarm associated Exti line.  
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
-
-/**
-  * @brief  Enable rising edge trigger on the RTC Alarm associated Exti line.  
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
-  * @brief  Disable rising edge trigger on the RTC Alarm associated Exti line.  
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
-
-/**
-  * @brief  Enable rising & falling edge trigger on the RTC Alarm associated Exti line.  
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE()  do { \
-                                                             __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();  \
-                                                             __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \
-                                                           } while(0)
-
-/**
-  * @brief  Disable rising & falling edge trigger on the RTC Alarm associated Exti line.  
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
-                                                             __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();  \
-                                                             __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \
-                                                           } while(0)
-
-/**
-  * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
-  * @retval Line Status.
-  */
-#define __HAL_RTC_ALARM_EXTI_GET_FLAG()              (EXTI->PR1 & RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
-  * @brief Clear the RTC Alarm associated Exti line flag.
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()            (EXTI->PR1 = RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
-  * @brief Generate a Software interrupt on RTC Alarm associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()         (EXTI->SWIER1 |= RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
-  * @}
-  */
-
-/* Include RTC HAL Extended module */
-#include "stm32l4xx_hal_rtc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RTC_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup RTC_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization and de-initialization functions  ****************************/
-HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
-void              HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
-void              HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
-/**
-  * @}
-  */
-
-/** @addtogroup RTC_Exported_Functions_Group2
-  * @{
-  */
-/* RTC Time and Date functions ************************************************/
-HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
-/**
-  * @}
-  */
-
-/** @addtogroup RTC_Exported_Functions_Group3
-  * @{
-  */
-/* RTC Alarm functions ********************************************************/
-HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
-HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
-void              HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-void              HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
-/**
-  * @}
-  */
-
-/** @addtogroup RTC_Exported_Functions_Group4
-  * @{
-  */
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);
-/**
-  * @}
-  */
-
-/** @addtogroup RTC_Exported_Functions_Group5
-  * @{
-  */
-/* Peripheral State functions *************************************************/
-HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/ 
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RTC_Private_Constants RTC Private Constants
-  * @{
-  */
-/* Masks Definition */
-#define RTC_TR_RESERVED_MASK    ((uint32_t)0x007F7F7F)
-#define RTC_DR_RESERVED_MASK    ((uint32_t)0x00FFFF3F) 
-#define RTC_INIT_MASK           ((uint32_t)0xFFFFFFFFU)  
-#define RTC_RSF_MASK            ((uint32_t)0xFFFFFF5FU)
-
-#define RTC_TIMEOUT_VALUE  1000
-  
-#define RTC_EXTI_LINE_ALARM_EVENT             ((uint32_t)0x00040000)  /*!< External interrupt line 18 Connected to the RTC Alarm event */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup RTC_Private_Macros RTC Private Macros
-  * @{
-  */
-
-/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
-  * @{
-  */ 
-
-#define IS_RTC_HOUR_FORMAT(FORMAT)     (((FORMAT) == RTC_HOURFORMAT_12) || \
-                                        ((FORMAT) == RTC_HOURFORMAT_24))
-
-#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
-                                ((POL) == RTC_OUTPUT_POLARITY_LOW))
-
-#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
-                                  ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
-
-#define IS_RTC_OUTPUT_REMAP(REMAP)   (((REMAP) == RTC_OUTPUT_REMAP_NONE) || \
-                                      ((REMAP) == RTC_OUTPUT_REMAP_POS1))
-
-#define IS_RTC_HOURFORMAT12(PM)  (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))
-
-#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
-                                      ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
-                                      ((SAVE) == RTC_DAYLIGHTSAVING_NONE))
-
-#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
-                                           ((OPERATION) == RTC_STOREOPERATION_SET))
-
-#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
-
-#define IS_RTC_YEAR(YEAR)              ((YEAR) <= (uint32_t)99)
-
-#define IS_RTC_MONTH(MONTH)            (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12))
-
-#define IS_RTC_DATE(DATE)              (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31))
-
-#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
-                                 ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
-                                 ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
-                                 ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
-                                 ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
-                                 ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
-                                 ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
-
-#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31))
-
-#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
-                                                    ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
-                                                    ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
-                                                    ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
-                                                    ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
-                                                    ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
-                                                    ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
-
-#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
-                                            ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
-
-#define IS_RTC_ALARM_MASK(MASK)  (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
-
-#define IS_RTC_ALARM(ALARM)      (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
-
-#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00007FFF)
-
-#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK)   (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_NONE))
-
-#define IS_RTC_ASYNCH_PREDIV(PREDIV)   ((PREDIV) <= (uint32_t)0x7F)
-
-#define IS_RTC_SYNCH_PREDIV(PREDIV)    ((PREDIV) <= (uint32_t)0x7FFF)
-
-#define IS_RTC_HOUR12(HOUR)            (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12))
-
-#define IS_RTC_HOUR24(HOUR)            ((HOUR) <= (uint32_t)23)
-
-#define IS_RTC_MINUTES(MINUTES)        ((MINUTES) <= (uint32_t)59)
-
-#define IS_RTC_SECONDS(SECONDS)        ((SECONDS) <= (uint32_t)59)
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @addtogroup RTC_Private_Functions
-  * @{
-  */
-
-HAL_StatusTypeDef  RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
-uint8_t            RTC_ByteToBcd2(uint8_t Value);
-uint8_t            RTC_Bcd2ToByte(uint8_t Value);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L4xx_HAL_RTC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/inc/stm32l4xx_hal_rtc_ex.h b/stmhal/hal/l4/inc/stm32l4xx_hal_rtc_ex.h
deleted file mode 100644
index 2d0f366f07..0000000000
--- a/stmhal/hal/l4/inc/stm32l4xx_hal_rtc_ex.h
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_rtc_ex.h
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   Header file of RTC HAL Extended module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L4xx_HAL_RTC_EX_H
-#define __STM32L4xx_HAL_RTC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup RTCEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Types RTCEx Exported Types
-  * @{
-  */
-/**
-  * @brief  RTC Tamper structure definition
-  */
-typedef struct
-{
-  uint32_t Tamper;                      /*!< Specifies the Tamper Pin.
-                                             This parameter can be a value of @ref  RTCEx_Tamper_Pins_Definitions */
-
-  uint32_t Interrupt;                   /*!< Specifies the Tamper Interrupt.
-                                             This parameter can be a value of @ref  RTCEx_Tamper_Interrupt_Definitions */
-
-  uint32_t Trigger;                     /*!< Specifies the Tamper Trigger.
-                                             This parameter can be a value of @ref  RTCEx_Tamper_Trigger_Definitions */
-
-  uint32_t NoErase;                     /*!< Specifies the Tamper no erase mode.
-                                             This parameter can be a value of @ref  RTCEx_Tamper_EraseBackUp_Definitions */
-
-  uint32_t MaskFlag;                     /*!< Specifies the Tamper Flag masking.
-                                             This parameter can be a value of @ref RTCEx_Tamper_MaskFlag_Definitions   */
-
-  uint32_t Filter;                      /*!< Specifies the RTC Filter Tamper.
-                                             This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */
-
-  uint32_t SamplingFrequency;           /*!< Specifies the sampling frequency.
-                                             This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies_Definitions */
-
-  uint32_t PrechargeDuration;           /*!< Specifies the Precharge Duration .
-                                             This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */
-
-  uint32_t TamperPullUp;                /*!< Specifies the Tamper PullUp .
-                                             This parameter can be a value of @ref RTCEx_Tamper_Pull_UP_Definitions */
-
-  uint32_t TimeStampOnTamperDetection;  /*!< Specifies the TimeStampOnTamperDetection.
-                                             This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */
-}RTC_TamperTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants
-  * @{
-  */
-
-/** @defgroup RTCEx_Output_selection_Definitions RTC Output Selection Definitions
-  * @{
-  */
-#define RTC_OUTPUT_DISABLE             ((uint32_t)0x00000000)
-#define RTC_OUTPUT_ALARMA              ((uint32_t)0x00200000)
-#define RTC_OUTPUT_ALARMB              ((uint32_t)0x00400000)
-#define RTC_OUTPUT_WAKEUP              ((uint32_t)0x00600000)
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Backup_Registers_Definitions RTC Backup Registers Definitions
-  * @{
-  */
-#define RTC_BKP_DR0                       ((uint32_t)0x00000000)
-#define RTC_BKP_DR1                       ((uint32_t)0x00000001)
-#define RTC_BKP_DR2                       ((uint32_t)0x00000002)
-#define RTC_BKP_DR3                       ((uint32_t)0x00000003)
-#define RTC_BKP_DR4                       ((uint32_t)0x00000004)
-#define RTC_BKP_DR5                       ((uint32_t)0x00000005)
-#define RTC_BKP_DR6                       ((uint32_t)0x00000006)
-#define RTC_BKP_DR7                       ((uint32_t)0x00000007)
-#define RTC_BKP_DR8                       ((uint32_t)0x00000008)
-#define RTC_BKP_DR9                       ((uint32_t)0x00000009)
-#define RTC_BKP_DR10                      ((uint32_t)0x0000000A)
-#define RTC_BKP_DR11                      ((uint32_t)0x0000000B)
-#define RTC_BKP_DR12                      ((uint32_t)0x0000000C)
-#define RTC_BKP_DR13                      ((uint32_t)0x0000000D)
-#define RTC_BKP_DR14                      ((uint32_t)0x0000000E)
-#define RTC_BKP_DR15                      ((uint32_t)0x0000000F)
-#define RTC_BKP_DR16                      ((uint32_t)0x00000010)
-#define RTC_BKP_DR17                      ((uint32_t)0x00000011)
-#define RTC_BKP_DR18                      ((uint32_t)0x00000012)
-#define RTC_BKP_DR19                      ((uint32_t)0x00000013)
-#define RTC_BKP_DR20                      ((uint32_t)0x00000014)
-#define RTC_BKP_DR21                      ((uint32_t)0x00000015)
-#define RTC_BKP_DR22                      ((uint32_t)0x00000016)
-#define RTC_BKP_DR23                      ((uint32_t)0x00000017)
-#define RTC_BKP_DR24                      ((uint32_t)0x00000018)
-#define RTC_BKP_DR25                      ((uint32_t)0x00000019)
-#define RTC_BKP_DR26                      ((uint32_t)0x0000001A)
-#define RTC_BKP_DR27                      ((uint32_t)0x0000001B)
-#define RTC_BKP_DR28                      ((uint32_t)0x0000001C)
-#define RTC_BKP_DR29                      ((uint32_t)0x0000001D)
-#define RTC_BKP_DR30                      ((uint32_t)0x0000001E)
-#define RTC_BKP_DR31                      ((uint32_t)0x0000001F)
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_TimeStamp_Edges_definitions RTC TimeStamp Edges Definitions
-  * @{
-  */ 
-#define RTC_TIMESTAMPEDGE_RISING          ((uint32_t)0x00000000)
-#define RTC_TIMESTAMPEDGE_FALLING         ((uint32_t)0x00000008)
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_TimeStamp_Pin_Selection RTC TimeStamp Pins Selection
-  * @{
-  */
-#define RTC_TIMESTAMPPIN_DEFAULT          ((uint32_t)0x00000000)
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_Pins_Definitions RTC Tamper Pins Definitions
-  * @{
-  */
-#if defined(RTC_TAMPER1_SUPPORT)
-#define RTC_TAMPER_1                       RTC_TAMPCR_TAMP1E
-#endif /* RTC_TAMPER1_SUPPORT */
-#define RTC_TAMPER_2                       RTC_TAMPCR_TAMP2E
-#if defined(RTC_TAMPER3_SUPPORT)
-#define RTC_TAMPER_3                       RTC_TAMPCR_TAMP3E
-#endif /* RTC_TAMPER3_SUPPORT */
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_Interrupt_Definitions RTC Tamper Interrupts Definitions
-  * @{
-  */
-#if defined(RTC_TAMPER1_SUPPORT)
-#define RTC_TAMPER1_INTERRUPT              RTC_TAMPCR_TAMP1IE
-#endif /* RTC_TAMPER1_SUPPORT */
-#define RTC_TAMPER2_INTERRUPT              RTC_TAMPCR_TAMP2IE
-#if defined(RTC_TAMPER3_SUPPORT)
-#define RTC_TAMPER3_INTERRUPT              RTC_TAMPCR_TAMP3IE
-#endif /* RTC_TAMPER3_SUPPORT */
-#define RTC_ALL_TAMPER_INTERRUPT           RTC_TAMPCR_TAMPIE
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_Trigger_Definitions RTC Tamper Triggers Definitions
-  * @{
-  */
-#define RTC_TAMPERTRIGGER_RISINGEDGE       ((uint32_t)0x00000000)
-#define RTC_TAMPERTRIGGER_FALLINGEDGE      ((uint32_t)0x00000002)
-#define RTC_TAMPERTRIGGER_LOWLEVEL         RTC_TAMPERTRIGGER_RISINGEDGE
-#define RTC_TAMPERTRIGGER_HIGHLEVEL        RTC_TAMPERTRIGGER_FALLINGEDGE
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_EraseBackUp_Definitions RTC Tamper EraseBackUp Definitions
-* @{
-*/
-#define RTC_TAMPER_ERASE_BACKUP_ENABLE     ((uint32_t)0x00000000)
-#define RTC_TAMPER_ERASE_BACKUP_DISABLE    ((uint32_t)0x00020000)
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_MaskFlag_Definitions RTC Tamper Mask Flag Definitions
-* @{
-*/
-#define RTC_TAMPERMASK_FLAG_DISABLE        ((uint32_t)0x00000000)
-#define RTC_TAMPERMASK_FLAG_ENABLE         ((uint32_t)0x00040000)
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_Filter_Definitions RTC Tamper Filter Definitions
-  * @{
-  */
-#define RTC_TAMPERFILTER_DISABLE   ((uint32_t)0x00000000)  /*!< Tamper filter is disabled */
-
-#define RTC_TAMPERFILTER_2SAMPLE   ((uint32_t)0x00000800)  /*!< Tamper is activated after 2
-                                                                consecutive samples at the active level */
-#define RTC_TAMPERFILTER_4SAMPLE   ((uint32_t)0x00001000)  /*!< Tamper is activated after 4
-                                                                consecutive samples at the active level */
-#define RTC_TAMPERFILTER_8SAMPLE   ((uint32_t)0x00001800)  /*!< Tamper is activated after 8
-                                                                consecutive samples at the active level. */
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTC Tamper Sampling Frequencies Definitions
-  * @{
-  */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768  ((uint32_t)0x00000000)  /*!< Each of the tamper inputs are sampled
-                                                                             with a frequency =  RTCCLK / 32768 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384  ((uint32_t)0x00000100)  /*!< Each of the tamper inputs are sampled
-                                                                             with a frequency =  RTCCLK / 16384 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192   ((uint32_t)0x00000200)  /*!< Each of the tamper inputs are sampled
-                                                                             with a frequency =  RTCCLK / 8192  */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096   ((uint32_t)0x00000300)  /*!< Each of the tamper inputs are sampled
-                                                                             with a frequency =  RTCCLK / 4096  */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048   ((uint32_t)0x00000400)  /*!< Each of the tamper inputs are sampled
-                                                                             with a frequency =  RTCCLK / 2048  */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024   ((uint32_t)0x00000500)  /*!< Each of the tamper inputs are sampled
-                                                                             with a frequency =  RTCCLK / 1024  */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512    ((uint32_t)0x00000600)  /*!< Each of the tamper inputs are sampled
-                                                                             with a frequency =  RTCCLK / 512   */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256    ((uint32_t)0x00000700)  /*!< Each of the tamper inputs are sampled
-                                                                             with a frequency =  RTCCLK / 256   */
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTC Tamper Pin Precharge Duration Definitions
-  * @{
-  */
-#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000)  /*!< Tamper pins are pre-charged before
-                                                                         sampling during 1 RTCCLK cycle  */
-#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000)  /*!< Tamper pins are pre-charged before
-                                                                         sampling during 2 RTCCLK cycles */
-#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000)  /*!< Tamper pins are pre-charged before
-                                                                         sampling during 4 RTCCLK cycles */
-#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000)  /*!< Tamper pins are pre-charged before
-                                                                         sampling during 8 RTCCLK cycles */
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTC Tamper TimeStamp On Tamper Detection Definitions
-  * @{
-  */
-#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE  ((uint32_t)RTC_TAMPCR_TAMPTS)  /*!< TimeStamp on Tamper Detection event saved        */
-#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000)         /*!< TimeStamp on Tamper Detection event is not saved */
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTC Tamper Pull Up Definitions
-  * @{
-  */
-#define RTC_TAMPER_PULLUP_ENABLE  ((uint32_t)0x00000000)              /*!< TimeStamp on Tamper Detection event saved        */
-#define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAMPCR_TAMPPUDIS)    /*!< TimeStamp on Tamper Detection event is not saved */
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Wakeup_Timer_Definitions RTC Wakeup Timer Definitions
-  * @{
-  */
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV16        ((uint32_t)0x00000000)
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV8         ((uint32_t)0x00000001)
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV4         ((uint32_t)0x00000002)
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV2         ((uint32_t)0x00000003)
-#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS      ((uint32_t)0x00000004)
-#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS      ((uint32_t)0x00000006)
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Smooth_calib_period_Definitions RTC Smooth Calib Period Definitions
-  * @{
-  */
-#define RTC_SMOOTHCALIB_PERIOD_32SEC   ((uint32_t)0x00000000)  /*!< If RTCCLK = 32768 Hz, Smooth calibration
-                                                                    period is 32s,  else 2exp20 RTCCLK seconds */
-#define RTC_SMOOTHCALIB_PERIOD_16SEC   ((uint32_t)0x00002000)  /*!< If RTCCLK = 32768 Hz, Smooth calibration 
-                                                                    period is 16s, else 2exp19 RTCCLK seconds */
-#define RTC_SMOOTHCALIB_PERIOD_8SEC    ((uint32_t)0x00004000)  /*!< If RTCCLK = 32768 Hz, Smooth calibration 
-                                                                    period is 8s, else 2exp18 RTCCLK seconds */
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTC Smooth Calib Plus Pulses Definitions
-  * @{
-  */
-#define RTC_SMOOTHCALIB_PLUSPULSES_SET    ((uint32_t)0x00008000)  /*!< The number of RTCCLK pulses added
-                                                                       during a X -second window = Y - CALM[8:0]
-                                                                       with Y = 512, 256, 128 when X = 32, 16, 8 */
-#define RTC_SMOOTHCALIB_PLUSPULSES_RESET  ((uint32_t)0x00000000)  /*!< The number of RTCCLK pulses subbstited
-                                                                       during a 32-second window = CALM[8:0] */
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Calib_Output_selection_Definitions RTC Calib Output Selection Definitions
-  * @{
-  */
-#define RTC_CALIBOUTPUT_512HZ            ((uint32_t)0x00000000)
-#define RTC_CALIBOUTPUT_1HZ              ((uint32_t)0x00080000)
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Add_1_Second_Parameter_Definitions RTC Add 1 Second Parameter Definitions
-  * @{
-  */
-#define RTC_SHIFTADD1S_RESET      ((uint32_t)0x00000000)
-#define RTC_SHIFTADD1S_SET        ((uint32_t)0x80000000)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros
-  * @{
-  */
-
-/**
-  * @brief  Enable the RTC WakeUp Timer peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__)                     ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
-
-/**
-  * @brief  Disable the RTC WakeUp Timer peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__)                    ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
-
-/**
-  * @brief  Enable the RTC WakeUpTimer interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled.
-  *         This parameter can be:
-  *            @arg RTC_IT_WUT: WakeUpTimer interrupt
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the RTC WakeUpTimer interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be disabled.
-  *         This parameter can be:
-  *            @arg RTC_IT_WUT: WakeUpTimer interrupt
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
-
-/**
-  * @brief  Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to check.
-  *         This parameter can be:
-  *            @arg RTC_IT_WUT:  WakeUpTimer interrupt
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__)       (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
-
-/**
-  * @brief  Check whether the specified RTC Wake Up timer interrupt is enabled or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Wake Up timer interrupt sources to check.
-  *         This parameter can be:
-  *            @arg RTC_IT_WUT:  WakeUpTimer interrupt
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)   (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
-
-/**
-  * @brief  Get the selected RTC WakeUpTimer's flag status.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC WakeUpTimer Flag is pending or not.
-  *          This parameter can be:
-  *             @arg RTC_FLAG_WUTF
-  *             @arg RTC_FLAG_WUTWF
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__)   (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
-
-/**
-  * @brief  Clear the RTC Wake Up timer's pending flags.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC WakeUpTimer Flag to clear.
-  *         This parameter can be:
-  *            @arg RTC_FLAG_WUTF
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) 
-
-/**
-  * @brief  Enable the RTC Tamper1 input detection.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP1E))
-
-/**
-  * @brief  Disable the RTC Tamper1 input detection.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP1E))
-
-/**
-  * @brief  Enable the RTC Tamper2 input detection.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E))
-
-/**
-  * @brief  Disable the RTC Tamper2 input detection.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E))
-
-/**
-  * @brief  Enable the RTC Tamper3 input detection.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP3E))
-
-/**
-  * @brief  Disable the RTC Tamper3 input detection.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP3E))
-
-/**
-  * @brief  Enable the RTC Tamper interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Tamper interrupt sources to be enabled.
-  *          This parameter can be any combination of the following values:
-  *             @arg  RTC_IT_TAMP: All tampers interrupts
-  *             @arg  RTC_IT_TAMP1: Tamper1 interrupt
-  *             @arg  RTC_IT_TAMP2: Tamper2 interrupt
-  *             @arg  RTC_IT_TAMP3: Tamper3 interrupt
-  * @retval None
-  */   
-#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__)        ((__HANDLE__)->Instance->TAMPCR |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the RTC Tamper interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Tamper interrupt sources to be disabled. 
-  *         This parameter can be any combination of the following values:
-  *            @arg  RTC_IT_TAMP: All tampers interrupts
-  *            @arg  RTC_IT_TAMP1: Tamper1 interrupt
-  *            @arg  RTC_IT_TAMP2: Tamper2 interrupt
-  *            @arg  RTC_IT_TAMP3: Tamper3 interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__)       ((__HANDLE__)->Instance->TAMPCR &= ~(__INTERRUPT__))
-
-/**
-  * @brief  Check whether the specified RTC Tamper interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Tamper interrupt to check.
-  *         This parameter can be:
-  *            @arg  RTC_IT_TAMP1: Tamper1 interrupt
-  *            @arg  RTC_IT_TAMP2: Tamper2 interrupt
-  *            @arg  RTC_IT_TAMP3: Tamper3 interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)           (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3)) != RESET) ? SET : RESET) : \
-                                                                      ((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5)) != RESET) ? SET : RESET) : \
-                                                                      (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7)) != RESET) ? SET : RESET))
-
-/**
-  * @brief  Check whether the specified RTC Tamper interrupt is enabled or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Tamper interrupt source to check.
-  *         This parameter can be:
-  *            @arg  RTC_IT_TAMP: All tampers interrupts
-  *            @arg  RTC_IT_TAMP1: Tamper1 interrupt
-  *            @arg  RTC_IT_TAMP2: Tamper2 interrupt
-  *            @arg  RTC_IT_TAMP3: Tamper3 interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)    (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
-
-/**
-  * @brief  Get the selected RTC Tamper's flag status.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Tamper Flag is pending or not.
-  *          This parameter can be:
-  *             @arg RTC_FLAG_TAMP1F: Tamper1 flag
-  *             @arg RTC_FLAG_TAMP2F: Tamper2 flag
-  *             @arg RTC_FLAG_TAMP3F: Tamper3 flag
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__)        (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
-
-/**
-  * @brief  Clear the RTC Tamper's pending flags.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Tamper Flag sources to clear.
-  *          This parameter can be:
-  *             @arg RTC_FLAG_TAMP1F: Tamper1 flag
-  *             @arg RTC_FLAG_TAMP2F: Tamper2 flag
-  *             @arg RTC_FLAG_TAMP3F: Tamper3 flag
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-/**
-  * @brief  Enable the RTC TimeStamp peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__)                       ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
-
-/**
-  * @brief  Disable the RTC TimeStamp peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
-
-/**
-  * @brief  Enable the RTC TimeStamp interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC TimeStamp interrupt source to be enabled.
-  *         This parameter can be:
-  *            @arg RTC_IT_TS: TimeStamp interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the RTC TimeStamp interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC TimeStamp interrupt source to be disabled. 
-  *         This parameter can be:
-  *            @arg RTC_IT_TS: TimeStamp interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
-
-/**
-  * @brief  Check whether the specified RTC TimeStamp interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC TimeStamp interrupt source to check.
-  *         This parameter can be:
-  *            @arg RTC_IT_TS: TimeStamp interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__)        (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
-
-/**
-  * @brief  Check whether the specified RTC Time Stamp interrupt is enabled or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Time Stamp interrupt source to check.
-  *         This parameter can be:
-  *            @arg RTC_IT_TS: TimeStamp interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
-
-/**
-  * @brief  Get the selected RTC TimeStamp's flag status.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC TimeStamp Flag is pending or not.
-  *         This parameter can be:
-  *            @arg RTC_FLAG_TSF
-  *            @arg RTC_FLAG_TSOVF
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)     (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
-
-/**
-  * @brief  Clear the RTC Time Stamp's pending flags.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Alarm Flag sources to clear.
-  *          This parameter can be:
-  *             @arg RTC_FLAG_TSF
-  *             @arg RTC_FLAG_TSOVF
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)   ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-/**
-  * @brief  Enable the RTC internal TimeStamp peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE))
-
-/**
-  * @brief  Disable the RTC internal TimeStamp peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE))
-
-/**
-  * @brief  Get the selected RTC Internal Time Stamp's flag status.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Internal Time Stamp Flag is pending or not.
-  *         This parameter can be:
-  *            @arg RTC_FLAG_ITSF
-  * @retval None
-  */
-#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)    (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
-
-/**
-  * @brief  Clear the RTC Internal Time Stamp's pending flags.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Internal Time Stamp Flag source to clear.
-  *          This parameter can be:
-  *             @arg RTC_FLAG_ITSF
-  * @retval None
-  */
-#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)  ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-/**
-  * @brief  Enable the RTC calibration output.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
-
-/**
-  * @brief  Disable the calibration output.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
-
-/**
-  * @brief  Enable the clock reference detection.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
-
-/**
-  * @brief  Disable the clock reference detection.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
-
-/**
-  * @brief  Get the selected RTC shift operation's flag status.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC shift operation Flag is pending or not.
-  *          This parameter can be:
-  *             @arg RTC_FLAG_SHPF
-  * @retval None
-  */
-#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__)         (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
-
-/**
-  * @brief  Enable interrupt on the RTC WakeUp Timer associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT()       (EXTI->IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
-  * @brief  Disable interrupt on the RTC WakeUp Timer associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT()      (EXTI->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
-
-/**
-  * @brief  Enable event on the RTC WakeUp Timer associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT()    (EXTI->EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
-  * @brief  Disable event on the RTC WakeUp Timer associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT()   (EXTI->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
-
-/**
-  * @brief  Enable falling edge trigger on the RTC WakeUp Timer associated Exti line. 
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
-  * @brief  Disable falling edge trigger on the RTC WakeUp Timer associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
-
-/**
-  * @brief  Enable rising edge trigger on the RTC WakeUp Timer associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
-  * @brief  Disable rising edge trigger on the RTC WakeUp Timer associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
-
-/**
-  * @brief  Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE()  do { \
-                                                                   __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();  \
-                                                                   __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE(); \
-                                                                 } while(0)
-
-/**
-  * @brief  Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
-  * This parameter can be:
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE()  do { \
-                                                                   __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();  \
-                                                                   __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE(); \
-                                                                  } while(0)
-
-/**
-  * @brief Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not.
-  * @retval Line Status.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG()              (EXTI->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
-  * @brief Clear the RTC WakeUp Timer associated Exti line flag.
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG()            (EXTI->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
-  * @brief Generate a Software interrupt on the RTC WakeUp Timer associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT()         (EXTI->SWIER1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
-  * @brief  Enable interrupt on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()        (EXTI->IMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
-  * @brief  Disable interrupt on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()       (EXTI->IMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
-
-/**
-  * @brief  Enable event on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT()    (EXTI->EMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
-  * @brief  Disable event on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT()   (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
-
-/**
-  * @brief  Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line. 
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
-  * @brief  Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
-
-/**
-  * @brief  Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
-  * @brief  Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
-
-/**
-  * @brief  Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE()  do { \
-                                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();  \
-                                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE(); \
-                                                                      } while(0)
-
-/**
-  * @brief  Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
-  * This parameter can be:
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE()  do { \
-                                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();  \
-                                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE(); \
-                                                                       } while(0)
-
-/**
-  * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
-  * @retval Line Status.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()         (EXTI->PR1 & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
-  * @brief Clear the RTC Tamper and Timestamp associated Exti line flag.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()       (EXTI->PR1 = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
-  * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()    (EXTI->SWIER1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RTCEx_Exported_Functions
-  * @{
-  */
-
-/* RTC TimeStamp and Tamper functions *****************************************/
-/** @addtogroup RTCEx_Exported_Functions_Group1
-  * @{
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format);
-
-HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
-HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
-void              HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
-
-#if defined(RTC_TAMPER1_SUPPORT)
-void              HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
-#endif /* RTC_TAMPER1_SUPPORT */
-void              HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
-#if defined(RTC_TAMPER3_SUPPORT)
-void              HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc);
-#endif /* RTC_TAMPER3_SUPPORT */
-void              HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-#if defined(RTC_TAMPER1_SUPPORT)
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-#endif /* RTC_TAMPER1_SUPPORT */
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-#if defined(RTC_TAMPER3_SUPPORT)
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-#endif /* RTC_TAMPER3_SUPPORT */
-/**
-  * @}
-  */
-
-/* RTC Wake-up functions ******************************************************/
-/** @addtogroup RTCEx_Exported_Functions_Group2
-  * @{
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
-HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
-uint32_t          HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
-uint32_t          HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
-void              HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
-void              HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-/**
-  * @}
-  */
-
-/* Extended Control functions ************************************************/
-/** @addtogroup RTCEx_Exported_Functions_Group3
-  * @{
-  */
-void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
-uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
-
-HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue);
-HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS);
-HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);
-/**
-  * @}
-  */
-
-/* Extended RTC features functions *******************************************/
-/** @addtogroup RTCEx_Exported_Functions_Group4
-  * @{
-  */
-void              HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc); 
-HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/ 
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RTCEx_Private_Constants RTCEx Private Constants
-  * @{
-  */
-#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT  ((uint32_t)0x00080000)  /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */
-#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT       ((uint32_t)0x00100000)  /*!< External interrupt line 20 Connected to the RTC Wakeup event */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup RTCEx_Private_Macros RTCEx Private Macros
-  * @{
-  */
-
-/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
-  * @{
-  */ 
-
-#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
-                               ((OUTPUT) == RTC_OUTPUT_ALARMA)  || \
-                               ((OUTPUT) == RTC_OUTPUT_ALARMB)  || \
-                               ((OUTPUT) == RTC_OUTPUT_WAKEUP))
-
-#define IS_RTC_BKP(BKP)                   ((BKP) < (uint32_t) RTC_BKP_NUMBER)
-
-#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
-                                 ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
-
-#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET))
-
-#define IS_RTC_TAMPER_INTERRUPT(INTERRUPT) ((((INTERRUPT) & (uint32_t)0xFFB6FFFB) == 0x00) && ((INTERRUPT) != (uint32_t)RESET))
-
-#define IS_RTC_TIMESTAMP_PIN(PIN)  (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))
-
-#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
-                                        ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
-                                        ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
-                                        ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL)) 
-
-#define IS_RTC_TAMPER_ERASE_MODE(MODE)             (((MODE) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \
-                                                    ((MODE) == RTC_TAMPER_ERASE_BACKUP_DISABLE))
-
-#define IS_RTC_TAMPER_MASKFLAG_STATE(STATE)        (((STATE) == RTC_TAMPERMASK_FLAG_ENABLE) || \
-                                                    ((STATE) == RTC_TAMPERMASK_FLAG_DISABLE))
-
-#define IS_RTC_TAMPER_FILTER(FILTER)  (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \
-                                       ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \
-                                       ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \
-                                       ((FILTER) == RTC_TAMPERFILTER_8SAMPLE))
-
-#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
-                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
-                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
-                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
-                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
-                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
-                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512)  || \
-                                          ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))
-
-#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
-                                                    ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
-                                                    ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
-                                                   ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))
-
-#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
-                                                              ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
-
-#define IS_RTC_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \
-                                           ((STATE) == RTC_TAMPER_PULLUP_DISABLE))
-
-#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16)       || \
-                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8)    || \
-                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4)    || \
-                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2)    || \
-                                    ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
-                                    ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
-
-#define IS_RTC_WAKEUP_COUNTER(COUNTER)  ((COUNTER) <= 0xFFFF)
-
-#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
-                                            ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
-                                            ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))
-
-#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
-                                        ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
-
-#define  IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
-
-#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \
-                                 ((SEL) == RTC_SHIFTADD1S_SET))
-
-#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
-
-#define IS_RTC_CALIB_OUTPUT(OUTPUT)  (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
-                                      ((OUTPUT) == RTC_CALIBOUTPUT_1HZ))
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L4xx_HAL_RTC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/inc/stm32l4xx_hal_sd.h b/stmhal/hal/l4/inc/stm32l4xx_hal_sd.h
deleted file mode 100644
index 1baa66a9d2..0000000000
--- a/stmhal/hal/l4/inc/stm32l4xx_hal_sd.h
+++ /dev/null
@@ -1,776 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_sd.h
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   Header file of SD HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L4xx_HAL_SD_H
-#define __STM32L4xx_HAL_SD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_ll_sdmmc.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup SD SD
-  * @brief SD HAL module driver
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup SD_Exported_Types SD Exported Types
-  * @{
-  */
-
-/** @defgroup SD_Exported_Types_Group1 SD Handle Structure definition   
-  * @{
-  */
-#define SD_InitTypeDef      SDMMC_InitTypeDef 
-#define SD_TypeDef          SDMMC_TypeDef
-
-typedef struct
-{
-  SD_TypeDef                   *Instance;        /*!< SDMMC register base address                     */
-  
-  SD_InitTypeDef               Init;             /*!< SD required parameters                         */
-  
-  HAL_LockTypeDef              Lock;             /*!< SD locking object                              */
-  
-  uint32_t                     CardType;         /*!< SD card type                                   */
-  
-  uint32_t                     RCA;              /*!< SD relative card address                       */
-  
-  uint32_t                     CSD[4];           /*!< SD card specific data table                    */
-  
-  uint32_t                     CID[4];           /*!< SD card identification number table            */
-  
-  __IO uint32_t                SdTransferCplt;   /*!< SD transfer complete flag in non blocking mode */
-  
-  __IO uint32_t                SdTransferErr;    /*!< SD transfer error flag in non blocking mode    */
-  
-  __IO uint32_t                DmaTransferCplt;  /*!< SD DMA transfer complete flag                  */
-  
-  __IO uint32_t                SdOperation;      /*!< SD transfer operation (read/write)             */
-  
-  DMA_HandleTypeDef            *hdmarx;          /*!< SD Rx DMA handle parameters                    */
-  
-  DMA_HandleTypeDef            *hdmatx;          /*!< SD Tx DMA handle parameters                    */
-  
-}SD_HandleTypeDef;
-/** 
-  * @}
-  */
-
-/** @defgroup SD_Exported_Types_Group2 Card Specific Data: CSD Register 
-  * @{
-  */ 
-typedef struct
-{
-  __IO uint8_t  CSDStruct;            /*!< CSD structure                         */
-  __IO uint8_t  SysSpecVersion;       /*!< System specification version          */
-  __IO uint8_t  Reserved1;            /*!< Reserved                              */
-  __IO uint8_t  TAAC;                 /*!< Data read access time 1               */
-  __IO uint8_t  NSAC;                 /*!< Data read access time 2 in CLK cycles */
-  __IO uint8_t  MaxBusClkFrec;        /*!< Max. bus clock frequency              */
-  __IO uint16_t CardComdClasses;      /*!< Card command classes                  */
-  __IO uint8_t  RdBlockLen;           /*!< Max. read data block length           */
-  __IO uint8_t  PartBlockRead;        /*!< Partial blocks for read allowed       */
-  __IO uint8_t  WrBlockMisalign;      /*!< Write block misalignment              */
-  __IO uint8_t  RdBlockMisalign;      /*!< Read block misalignment               */
-  __IO uint8_t  DSRImpl;              /*!< DSR implemented                       */
-  __IO uint8_t  Reserved2;            /*!< Reserved                              */
-  __IO uint32_t DeviceSize;           /*!< Device Size                           */
-  __IO uint8_t  MaxRdCurrentVDDMin;   /*!< Max. read current @ VDD min           */
-  __IO uint8_t  MaxRdCurrentVDDMax;   /*!< Max. read current @ VDD max           */
-  __IO uint8_t  MaxWrCurrentVDDMin;   /*!< Max. write current @ VDD min          */
-  __IO uint8_t  MaxWrCurrentVDDMax;   /*!< Max. write current @ VDD max          */
-  __IO uint8_t  DeviceSizeMul;        /*!< Device size multiplier                */
-  __IO uint8_t  EraseGrSize;          /*!< Erase group size                      */
-  __IO uint8_t  EraseGrMul;           /*!< Erase group size multiplier           */
-  __IO uint8_t  WrProtectGrSize;      /*!< Write protect group size              */
-  __IO uint8_t  WrProtectGrEnable;    /*!< Write protect group enable            */
-  __IO uint8_t  ManDeflECC;           /*!< Manufacturer default ECC              */
-  __IO uint8_t  WrSpeedFact;          /*!< Write speed factor                    */
-  __IO uint8_t  MaxWrBlockLen;        /*!< Max. write data block length          */
-  __IO uint8_t  WriteBlockPaPartial;  /*!< Partial blocks for write allowed      */
-  __IO uint8_t  Reserved3;            /*!< Reserved                              */
-  __IO uint8_t  ContentProtectAppli;  /*!< Content protection application        */
-  __IO uint8_t  FileFormatGrouop;     /*!< File format group                     */
-  __IO uint8_t  CopyFlag;             /*!< Copy flag (OTP)                       */
-  __IO uint8_t  PermWrProtect;        /*!< Permanent write protection            */
-  __IO uint8_t  TempWrProtect;        /*!< Temporary write protection            */
-  __IO uint8_t  FileFormat;           /*!< File format                           */
-  __IO uint8_t  ECC;                  /*!< ECC code                              */
-  __IO uint8_t  CSD_CRC;              /*!< CSD CRC                               */
-  __IO uint8_t  Reserved4;            /*!< Always 1                              */
-
-}HAL_SD_CSDTypedef;
-/** 
-  * @}
-  */
-
-/** @defgroup SD_Exported_Types_Group3 Card Identification Data: CID Register
-  * @{
-  */
-typedef struct
-{
-  __IO uint8_t  ManufacturerID;  /*!< Manufacturer ID       */
-  __IO uint16_t OEM_AppliID;     /*!< OEM/Application ID    */
-  __IO uint32_t ProdName1;       /*!< Product Name part1    */
-  __IO uint8_t  ProdName2;       /*!< Product Name part2    */
-  __IO uint8_t  ProdRev;         /*!< Product Revision      */
-  __IO uint32_t ProdSN;          /*!< Product Serial Number */
-  __IO uint8_t  Reserved1;       /*!< Reserved1             */
-  __IO uint16_t ManufactDate;    /*!< Manufacturing Date    */
-  __IO uint8_t  CID_CRC;         /*!< CID CRC               */
-  __IO uint8_t  Reserved2;       /*!< Always 1              */
-
-}HAL_SD_CIDTypedef;
-/** 
-  * @}
-  */
-
-/** @defgroup SD_Exported_Types_Group4 SD Card Status returned by ACMD13 
-  * @{
-  */
-typedef struct
-{
-  __IO uint8_t  DAT_BUS_WIDTH;           /*!< Shows the currently defined data bus width                 */
-  __IO uint8_t  SECURED_MODE;            /*!< Card is in secured mode of operation                       */
-  __IO uint16_t SD_CARD_TYPE;            /*!< Carries information about card type                        */
-  __IO uint32_t SIZE_OF_PROTECTED_AREA;  /*!< Carries information about the capacity of protected area   */
-  __IO uint8_t  SPEED_CLASS;             /*!< Carries information about the speed class of the card      */
-  __IO uint8_t  PERFORMANCE_MOVE;        /*!< Carries information about the card's performance move      */
-  __IO uint8_t  AU_SIZE;                 /*!< Carries information about the card's allocation unit size  */
-  __IO uint16_t ERASE_SIZE;              /*!< Determines the number of AUs to be erased in one operation */
-  __IO uint8_t  ERASE_TIMEOUT;           /*!< Determines the timeout for any number of AU erase          */
-  __IO uint8_t  ERASE_OFFSET;            /*!< Carries information about the erase offset                 */
-
-}HAL_SD_CardStatusTypedef;
-/** 
-  * @}
-  */
-
-/** @defgroup SD_Exported_Types_Group5 SD Card information structure 
-  * @{
-  */
-typedef struct
-{
-  HAL_SD_CSDTypedef   SD_csd;         /*!< SD card specific data register         */
-  HAL_SD_CIDTypedef   SD_cid;         /*!< SD card identification number register */
-  uint64_t            CardCapacity;   /*!< Card capacity                          */
-  uint32_t            CardBlockSize;  /*!< Card block size                        */
-  uint16_t            RCA;            /*!< SD relative card address               */
-  uint8_t             CardType;       /*!< SD card type                           */
-
-}HAL_SD_CardInfoTypedef;
-/** 
-  * @}
-  */
-
-/** @defgroup SD_Exported_Types_Group6 SD Error status enumeration Structure definition 
-  * @{
-  */
-typedef enum
-{
-/** 
-  * @brief  SD specific error defines  
-  */   
-  SD_CMD_CRC_FAIL                    = (1),   /*!< Command response received (but CRC check failed)              */
-  SD_DATA_CRC_FAIL                   = (2),   /*!< Data block sent/received (CRC check failed)                   */
-  SD_CMD_RSP_TIMEOUT                 = (3),   /*!< Command response timeout                                      */
-  SD_DATA_TIMEOUT                    = (4),   /*!< Data timeout                                                  */
-  SD_TX_UNDERRUN                     = (5),   /*!< Transmit FIFO underrun                                        */
-  SD_RX_OVERRUN                      = (6),   /*!< Receive FIFO overrun                                          */
-  SD_START_BIT_ERR                   = (7),   /*!< Start bit not detected on all data signals in wide bus mode   */
-  SD_CMD_OUT_OF_RANGE                = (8),   /*!< Command's argument was out of range.                          */
-  SD_ADDR_MISALIGNED                 = (9),   /*!< Misaligned address                                            */
-  SD_BLOCK_LEN_ERR                   = (10),  /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */
-  SD_ERASE_SEQ_ERR                   = (11),  /*!< An error in the sequence of erase command occurs.            */
-  SD_BAD_ERASE_PARAM                 = (12),  /*!< An invalid selection for erase groups                        */
-  SD_WRITE_PROT_VIOLATION            = (13),  /*!< Attempt to program a write protect block                     */
-  SD_LOCK_UNLOCK_FAILED              = (14),  /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */
-  SD_COM_CRC_FAILED                  = (15),  /*!< CRC check of the previous command failed                     */
-  SD_ILLEGAL_CMD                     = (16),  /*!< Command is not legal for the card state                      */
-  SD_CARD_ECC_FAILED                 = (17),  /*!< Card internal ECC was applied but failed to correct the data */
-  SD_CC_ERROR                        = (18),  /*!< Internal card controller error                               */
-  SD_GENERAL_UNKNOWN_ERROR           = (19),  /*!< General or unknown error                                     */
-  SD_STREAM_READ_UNDERRUN            = (20),  /*!< The card could not sustain data transfer in stream read operation. */
-  SD_STREAM_WRITE_OVERRUN            = (21),  /*!< The card could not sustain data programming in stream mode   */
-  SD_CID_CSD_OVERWRITE               = (22),  /*!< CID/CSD overwrite error                                      */
-  SD_WP_ERASE_SKIP                   = (23),  /*!< Only partial address space was erased                        */
-  SD_CARD_ECC_DISABLED               = (24),  /*!< Command has been executed without using internal ECC         */
-  SD_ERASE_RESET                     = (25),  /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */
-  SD_AKE_SEQ_ERROR                   = (26),  /*!< Error in sequence of authentication.                         */
-  SD_INVALID_VOLTRANGE               = (27),
-  SD_ADDR_OUT_OF_RANGE               = (28),
-  SD_SWITCH_ERROR                    = (29),
-  SD_SDMMC_DISABLED                  = (30),
-  SD_SDMMC_FUNCTION_BUSY             = (31),
-  SD_SDMMC_FUNCTION_FAILED           = (32),
-  SD_SDMMC_UNKNOWN_FUNCTION          = (33),
-
-/** 
-  * @brief  Standard error defines   
-  */ 
-  SD_INTERNAL_ERROR                  = (34),
-  SD_NOT_CONFIGURED                  = (35),
-  SD_REQUEST_PENDING                 = (36),
-  SD_REQUEST_NOT_APPLICABLE          = (37),
-  SD_INVALID_PARAMETER               = (38),
-  SD_UNSUPPORTED_FEATURE             = (39),
-  SD_UNSUPPORTED_HW                  = (40),
-  SD_ERROR                           = (41),
-  SD_OK                              = (0) 
-
-}HAL_SD_ErrorTypedef;
-/** 
-  * @}
-  */
-
-/** @defgroup SD_Exported_Types_Group7 SD Transfer state enumeration structure
-  * @{
-  */   
-typedef enum
-{
-  SD_TRANSFER_OK    = 0,  /*!< Transfer success      */
-  SD_TRANSFER_BUSY  = 1,  /*!< Transfer is occurring */
-  SD_TRANSFER_ERROR = 2   /*!< Transfer failed       */
-
-}HAL_SD_TransferStateTypedef;
-/** 
-  * @}
-  */
-
-/** @defgroup SD_Exported_Types_Group8 SD Card State enumeration structure
-  * @{
-  */   
-typedef enum
-{
-  SD_CARD_READY                  = ((uint32_t)0x00000001),  /*!< Card state is ready                     */
-  SD_CARD_IDENTIFICATION         = ((uint32_t)0x00000002),  /*!< Card is in identification state         */
-  SD_CARD_STANDBY                = ((uint32_t)0x00000003),  /*!< Card is in standby state                */
-  SD_CARD_TRANSFER               = ((uint32_t)0x00000004),  /*!< Card is in transfer state               */  
-  SD_CARD_SENDING                = ((uint32_t)0x00000005),  /*!< Card is sending an operation            */
-  SD_CARD_RECEIVING              = ((uint32_t)0x00000006),  /*!< Card is receiving operation information */
-  SD_CARD_PROGRAMMING            = ((uint32_t)0x00000007),  /*!< Card is in programming state            */
-  SD_CARD_DISCONNECTED           = ((uint32_t)0x00000008),  /*!< Card is disconnected                    */
-  SD_CARD_ERROR                  = ((uint32_t)0x000000FF)   /*!< Card is in error state                  */
-
-}HAL_SD_CardStateTypedef;
-/** 
-  * @}
-  */
-
-/** @defgroup SD_Exported_Types_Group9 SD Operation enumeration structure
-  * @{
-  */   
-typedef enum
-{
-  SD_READ_SINGLE_BLOCK    = 0,  /*!< Read single block operation      */
-  SD_READ_MULTIPLE_BLOCK  = 1,  /*!< Read multiple blocks operation   */
-  SD_WRITE_SINGLE_BLOCK   = 2,  /*!< Write single block operation     */
-  SD_WRITE_MULTIPLE_BLOCK = 3   /*!< Write multiple blocks operation  */
-
-}HAL_SD_OperationTypedef;
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SD_Exported_Constants SD Exported Constants
-  * @{
-  */
-
-/** 
-  * @brief SD Commands Index 
-  */
-#define SD_CMD_GO_IDLE_STATE                       ((uint8_t)0)   /*!< Resets the SD memory card.                                                               */
-#define SD_CMD_SEND_OP_COND                        ((uint8_t)1)   /*!< Sends host capacity support information and activates the card's initialization process. */
-#define SD_CMD_ALL_SEND_CID                        ((uint8_t)2)   /*!< Asks any card connected to the host to send the CID numbers on the CMD line.             */
-#define SD_CMD_SET_REL_ADDR                        ((uint8_t)3)   /*!< Asks the card to publish a new relative address (RCA).                                   */
-#define SD_CMD_SET_DSR                             ((uint8_t)4)   /*!< Programs the DSR of all cards.                                                           */
-#define SD_CMD_SDMMC_SEN_OP_COND                   ((uint8_t)5)   /*!< Sends host capacity support information (HCS) and asks the accessed card to send its 
-                                                                       operating condition register (OCR) content in the response on the CMD line.              */
-#define SD_CMD_HS_SWITCH                           ((uint8_t)6)   /*!< Checks switchable function (mode 0) and switch card function (mode 1).                   */
-#define SD_CMD_SEL_DESEL_CARD                      ((uint8_t)7)   /*!< Selects the card by its own relative address and gets deselected by any other address    */
-#define SD_CMD_HS_SEND_EXT_CSD                     ((uint8_t)8)   /*!< Sends SD Memory Card interface condition, which includes host supply voltage information 
-                                                                       and asks the card whether card supports voltage.                                         */
-#define SD_CMD_SEND_CSD                            ((uint8_t)9)   /*!< Addressed card sends its card specific data (CSD) on the CMD line.                       */
-#define SD_CMD_SEND_CID                            ((uint8_t)10)  /*!< Addressed card sends its card identification (CID) on the CMD line.                      */
-#define SD_CMD_READ_DAT_UNTIL_STOP                 ((uint8_t)11)  /*!< SD card doesn't support it.                                                              */
-#define SD_CMD_STOP_TRANSMISSION                   ((uint8_t)12)  /*!< Forces the card to stop transmission.                                                    */
-#define SD_CMD_SEND_STATUS                         ((uint8_t)13)  /*!< Addressed card sends its status register.                                                */
-#define SD_CMD_HS_BUSTEST_READ                     ((uint8_t)14) 
-#define SD_CMD_GO_INACTIVE_STATE                   ((uint8_t)15)  /*!< Sends an addressed card into the inactive state.                                         */
-#define SD_CMD_SET_BLOCKLEN                        ((uint8_t)16)  /*!< Sets the block length (in bytes for SDSC) for all following block commands 
-                                                                       (read, write, lock). Default block length is fixed to 512 Bytes. Not effective 
-                                                                       for SDHS and SDXC.                                                                       */
-#define SD_CMD_READ_SINGLE_BLOCK                   ((uint8_t)17)  /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of 
-                                                                       fixed 512 bytes in case of SDHC and SDXC.                                                */
-#define SD_CMD_READ_MULT_BLOCK                     ((uint8_t)18)  /*!< Continuously transfers data blocks from card to host until interrupted by 
-                                                                       STOP_TRANSMISSION command.                                                               */
-#define SD_CMD_HS_BUSTEST_WRITE                    ((uint8_t)19)  /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104.                                    */
-#define SD_CMD_WRITE_DAT_UNTIL_STOP                ((uint8_t)20)  /*!< Speed class control command.                                                             */
-#define SD_CMD_SET_BLOCK_COUNT                     ((uint8_t)23)  /*!< Specify block count for CMD18 and CMD25.                                                 */
-#define SD_CMD_WRITE_SINGLE_BLOCK                  ((uint8_t)24)  /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of 
-                                                                       fixed 512 bytes in case of SDHC and SDXC.                                                */
-#define SD_CMD_WRITE_MULT_BLOCK                    ((uint8_t)25)  /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows.                    */
-#define SD_CMD_PROG_CID                            ((uint8_t)26)  /*!< Reserved for manufacturers.                                                              */
-#define SD_CMD_PROG_CSD                            ((uint8_t)27)  /*!< Programming of the programmable bits of the CSD.                                         */
-#define SD_CMD_SET_WRITE_PROT                      ((uint8_t)28)  /*!< Sets the write protection bit of the addressed group.                                    */
-#define SD_CMD_CLR_WRITE_PROT                      ((uint8_t)29)  /*!< Clears the write protection bit of the addressed group.                                  */
-#define SD_CMD_SEND_WRITE_PROT                     ((uint8_t)30)  /*!< Asks the card to send the status of the write protection bits.                           */
-#define SD_CMD_SD_ERASE_GRP_START                  ((uint8_t)32)  /*!< Sets the address of the first write block to be erased. (For SD card only).              */
-#define SD_CMD_SD_ERASE_GRP_END                    ((uint8_t)33)  /*!< Sets the address of the last write block of the continuous range to be erased.           */
-#define SD_CMD_ERASE_GRP_START                     ((uint8_t)35)  /*!< Sets the address of the first write block to be erased. Reserved for each command 
-                                                                       system set by switch function command (CMD6).                                            */
-#define SD_CMD_ERASE_GRP_END                       ((uint8_t)36)  /*!< Sets the address of the last write block of the continuous range to be erased. 
-                                                                       Reserved for each command system set by switch function command (CMD6).                  */
-#define SD_CMD_ERASE                               ((uint8_t)38)  /*!< Reserved for SD security applications.                                                   */
-#define SD_CMD_FAST_IO                             ((uint8_t)39)  /*!< SD card doesn't support it (Reserved).                                                   */
-#define SD_CMD_GO_IRQ_STATE                        ((uint8_t)40)  /*!< SD card doesn't support it (Reserved).                                                   */
-#define SD_CMD_LOCK_UNLOCK                         ((uint8_t)42)  /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by 
-                                                                       the SET_BLOCK_LEN command.                                                               */
-#define SD_CMD_APP_CMD                             ((uint8_t)55)  /*!< Indicates to the card that the next command is an application specific command rather 
-                                                                       than a standard command.                                                                 */
-#define SD_CMD_GEN_CMD                             ((uint8_t)56)  /*!< Used either to transfer a data block to the card or to get a data block from the card 
-                                                                       for general purpose/application specific commands.                                       */
-#define SD_CMD_NO_CMD                              ((uint8_t)64) 
-
-/** 
-  * @brief Following commands are SD Card Specific commands.
-  *        SDMMC_APP_CMD should be sent before sending these commands. 
-  */
-#define SD_CMD_APP_SD_SET_BUSWIDTH                 ((uint8_t)6)   /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus 
-                                                                       widths are given in SCR register.                                                          */
-#define SD_CMD_SD_APP_STATUS                       ((uint8_t)13)  /*!< (ACMD13) Sends the SD status.                                                              */
-#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS        ((uint8_t)22)  /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 
-                                                                       32bit+CRC data block.                                                                      */
-#define SD_CMD_SD_APP_OP_COND                      ((uint8_t)41)  /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to 
-                                                                       send its operating condition register (OCR) content in the response on the CMD line.       */
-#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT          ((uint8_t)42)  /*!< (ACMD42) Connects/Disconnects the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card. */
-#define SD_CMD_SD_APP_SEND_SCR                     ((uint8_t)51)  /*!< Reads the SD Configuration Register (SCR).                                                 */
-#define SD_CMD_SDMMC_RW_DIRECT                     ((uint8_t)52)  /*!< For SD I/O card only, reserved for security specification.                                 */
-#define SD_CMD_SDMMC_RW_EXTENDED                   ((uint8_t)53)  /*!< For SD I/O card only, reserved for security specification.                                 */
-
-/** 
-  * @brief Following commands are SD Card Specific security commands.
-  *        SD_CMD_APP_CMD should be sent before sending these commands. 
-  */
-#define SD_CMD_SD_APP_GET_MKB                      ((uint8_t)43)  /*!< For SD card only */
-#define SD_CMD_SD_APP_GET_MID                      ((uint8_t)44)  /*!< For SD card only */
-#define SD_CMD_SD_APP_SET_CER_RN1                  ((uint8_t)45)  /*!< For SD card only */
-#define SD_CMD_SD_APP_GET_CER_RN2                  ((uint8_t)46)  /*!< For SD card only */
-#define SD_CMD_SD_APP_SET_CER_RES2                 ((uint8_t)47)  /*!< For SD card only */
-#define SD_CMD_SD_APP_GET_CER_RES1                 ((uint8_t)48)  /*!< For SD card only */
-#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK   ((uint8_t)18)  /*!< For SD card only */
-#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK  ((uint8_t)25)  /*!< For SD card only */
-#define SD_CMD_SD_APP_SECURE_ERASE                 ((uint8_t)38)  /*!< For SD card only */
-#define SD_CMD_SD_APP_CHANGE_SECURE_AREA           ((uint8_t)49)  /*!< For SD card only */
-#define SD_CMD_SD_APP_SECURE_WRITE_MKB             ((uint8_t)48)  /*!< For SD card only */
-
-/** 
-  * @brief Supported SD Memory Cards 
-  */
-#define STD_CAPACITY_SD_CARD_V1_1             ((uint32_t)0x00000000)
-#define STD_CAPACITY_SD_CARD_V2_0             ((uint32_t)0x00000001)
-#define HIGH_CAPACITY_SD_CARD                 ((uint32_t)0x00000002)
-#define MULTIMEDIA_CARD                       ((uint32_t)0x00000003)
-#define SECURE_DIGITAL_IO_CARD                ((uint32_t)0x00000004)
-#define HIGH_SPEED_MULTIMEDIA_CARD            ((uint32_t)0x00000005)
-#define SECURE_DIGITAL_IO_COMBO_CARD          ((uint32_t)0x00000006)
-#define HIGH_CAPACITY_MMC_CARD                ((uint32_t)0x00000007)
-/**
-  * @}
-  */
-  
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup SD_Exported_macros SD Exported Macros
- *  @brief macros to handle interrupts and specific clock configurations
- * @{
- */
- 
-/**
-  * @brief  Enable the SD device.
-  * @retval None
-  */ 
-#define __HAL_SD_SDMMC_ENABLE(__HANDLE__) __SDMMC_ENABLE((__HANDLE__)->Instance)
-
-/**
-  * @brief  Disable the SD device.
-  * @retval None
-  */
-#define __HAL_SD_SDMMC_DISABLE(__HANDLE__) __SDMMC_DISABLE((__HANDLE__)->Instance)
-
-/**
-  * @brief  Enable the SDMMC DMA transfer.
-  * @retval None
-  */ 
-#define __HAL_SD_SDMMC_DMA_ENABLE(__HANDLE__) __SDMMC_DMA_ENABLE((__HANDLE__)->Instance)
-
-/**
-  * @brief  Disable the SDMMC DMA transfer.
-  * @retval None
-  */
-#define __HAL_SD_SDMMC_DMA_DISABLE(__HANDLE__)  __SDMMC_DMA_DISABLE((__HANDLE__)->Instance)
- 
-/**
-  * @brief  Enable the SD device interrupt.
-  * @param  __HANDLE__: SD Handle  
-  * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
-  *         This parameter can be one or a combination of the following values:
-  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
-  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
-  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt
-  *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt
-  *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt
-  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
-  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
-  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt
-  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt
-  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt
-  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt
-  *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt
-  *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt
-  * @retval None
-  */
-#define __HAL_SD_SDMMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
-  * @brief  Disable the SD device interrupt.
-  * @param  __HANDLE__: SD Handle   
-  * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
-  *          This parameter can be one or a combination of the following values:
-  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
-  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
-  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt
-  *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt
-  *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt
-  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
-  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
-  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt
-  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt
-  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt
-  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt
-  *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt
-  *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt   
-  * @retval None
-  */
-#define __HAL_SD_SDMMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
-  * @brief  Check whether the specified SD flag is set or not. 
-  * @param  __HANDLE__: SD Handle   
-  * @param  __FLAG__: specifies the flag to check. 
-  *          This parameter can be one of the following values:
-  *            @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
-  *            @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
-  *            @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
-  *            @arg SDMMC_FLAG_DTIMEOUT: Data timeout
-  *            @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
-  *            @arg SDMMC_FLAG_RXOVERR:  Received FIFO overrun error
-  *            @arg SDMMC_FLAG_CMDREND:  Command response received (CRC check passed)
-  *            @arg SDMMC_FLAG_CMDSENT:  Command sent (no response required)
-  *            @arg SDMMC_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
-  *            @arg SDMMC_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
-  *            @arg SDMMC_FLAG_CMDACT:   Command transfer in progress
-  *            @arg SDMMC_FLAG_TXACT:    Data transmit in progress
-  *            @arg SDMMC_FLAG_RXACT:    Data receive in progress
-  *            @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
-  *            @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
-  *            @arg SDMMC_FLAG_TXFIFOF:  Transmit FIFO full
-  *            @arg SDMMC_FLAG_RXFIFOF:  Receive FIFO full
-  *            @arg SDMMC_FLAG_TXFIFOE:  Transmit FIFO empty
-  *            @arg SDMMC_FLAG_RXFIFOE:  Receive FIFO empty
-  *            @arg SDMMC_FLAG_TXDAVL:   Data available in transmit FIFO
-  *            @arg SDMMC_FLAG_RXDAVL:   Data available in receive FIFO
-  *            @arg SDMMC_FLAG_SDIOIT:   SD I/O interrupt received
-  * @retval The new state of SD FLAG (SET or RESET).
-  */
-#define __HAL_SD_SDMMC_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
-
-/**
-  * @brief  Clear the SD's pending flags.
-  * @param  __HANDLE__: SD Handle  
-  * @param  __FLAG__: specifies the flag to clear.  
-  *          This parameter can be one or a combination of the following values:
-  *            @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
-  *            @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
-  *            @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
-  *            @arg SDMMC_FLAG_DTIMEOUT: Data timeout
-  *            @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
-  *            @arg SDMMC_FLAG_RXOVERR:  Received FIFO overrun error
-  *            @arg SDMMC_FLAG_CMDREND:  Command response received (CRC check passed)
-  *            @arg SDMMC_FLAG_CMDSENT:  Command sent (no response required)
-  *            @arg SDMMC_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
-  *            @arg SDMMC_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
-  *            @arg SDMMC_FLAG_SDIOIT:   SD I/O interrupt received
-  * @retval None
-  */
-#define __HAL_SD_SDMMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
-
-/**
-  * @brief  Check whether the specified SD interrupt has occurred or not.
-  * @param  __HANDLE__: SD Handle   
-  * @param  __INTERRUPT__: specifies the SDMMC interrupt source to check. 
-  *          This parameter can be one of the following values:
-  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
-  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
-  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt
-  *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt
-  *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt
-  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
-  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
-  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt
-  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt
-  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt
-  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt
-  *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt
-  *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt
-  * @retval The new state of SD IT (SET or RESET).
-  */
-#define __HAL_SD_SDMMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
-  * @brief  Clear the SD's interrupt pending bits.
-  * @param  __HANDLE__: SD Handle
-  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. 
-  *          This parameter can be one or a combination of the following values:
-  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
-  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt
-  * @retval None
-  */
-#define __HAL_SD_SDMMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-/**
-  * @}
-  */
-  
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup SD_Exported_Functions SD Exported Functions
-  * @{
-  */
-  
-/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo);
-HAL_StatusTypeDef   HAL_SD_DeInit (SD_HandleTypeDef *hsd);
-void HAL_SD_MspInit(SD_HandleTypeDef *hsd);
-void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
-/**
-  * @}
-  */
-  
-/** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions
-  * @{
-  */
-/* Blocking mode: Polling */
-// dpgeorge: read/write functions renamed to emphasise that address is given by block number
-HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_BlockNumber(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint32_t BlockNumber, uint32_t BlockSize, uint32_t NumberOfBlocks);
-HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_BlockNumber(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint32_t BlockNumber, uint32_t BlockSize, uint32_t NumberOfBlocks);
-HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr);
-
-/* Non-Blocking mode: Interrupt */
-void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
-
-/* Callback in non blocking modes (DMA) */
-void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma);
-void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma);
-void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma);
-void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma);
-void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd);
-void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd);
-
-/* Non-Blocking mode: DMA */
-// dpgeorge: read/write functions renamed to emphasise that address is given by block number
-HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_BlockNumber_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint32_t BlockNumber, uint32_t BlockSize, uint32_t NumberOfBlocks);
-HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_BlockNumber_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint32_t BlockNumber, uint32_t BlockSize, uint32_t NumberOfBlocks);
-HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);
-HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);
-/**
-  * @}
-  */
-  
-/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions
-  * @{
-  */
-HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo);
-HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode);
-HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd);
-HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd);
-/**
-  * @}
-  */
-  
-/* Peripheral State functions  ************************************************/
-/** @defgroup SD_Exported_Functions_Group4 Peripheral State functions
-  * @{
-  */
-HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
-HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus);
-HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd);
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-    
-/* Private types -------------------------------------------------------------*/
-/** @defgroup SD_Private_Types SD Private Types
-  * @{
-  */
-
-/**
-  * @}
-  */ 
-
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup SD_Private_Defines SD Private Defines
-  * @{
-  */
-
-/**
-  * @}
-  */ 
-          
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup SD_Private_Variables SD Private Variables
-  * @{
-  */
-
-/**
-  * @}
-  */ 
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup SD_Private_Constants SD Private Constants
-  * @{
-  */
-
-/**
-  * @}
-  */ 
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SD_Private_Macros SD Private Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup SD_Private_Functions SD Private Functions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32L4xx_HAL_SD_H */ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/inc/stm32l4xx_hal_spi.h b/stmhal/hal/l4/inc/stm32l4xx_hal_spi.h
deleted file mode 100644
index 789aecd4d9..0000000000
--- a/stmhal/hal/l4/inc/stm32l4xx_hal_spi.h
+++ /dev/null
@@ -1,696 +0,0 @@
- /**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_spi.h
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   Header file of SPI HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L4xx_HAL_SPI_H
-#define __STM32L4xx_HAL_SPI_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup SPI
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup SPI_Exported_Types SPI Exported Types
-  * @{
-  */
-
-/**
-  * @brief  SPI Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t Mode;                /*!< Specifies the SPI operating mode.
-                                     This parameter can be a value of @ref SPI_Mode */
-
-  uint32_t Direction;           /*!< Specifies the SPI bidirectional mode state.
-                                     This parameter can be a value of @ref SPI_Direction */
-
-  uint32_t DataSize;            /*!< Specifies the SPI data size.
-                                     This parameter can be a value of @ref SPI_Data_Size */
-
-  uint32_t CLKPolarity;         /*!< Specifies the serial clock steady state.
-                                     This parameter can be a value of @ref SPI_Clock_Polarity */
-
-  uint32_t CLKPhase;            /*!< Specifies the clock active edge for the bit capture.
-                                     This parameter can be a value of @ref SPI_Clock_Phase */
-
-  uint32_t NSS;                 /*!< Specifies whether the NSS signal is managed by
-                                     hardware (NSS pin) or by software using the SSI bit.
-                                     This parameter can be a value of @ref SPI_Slave_Select_management */
-
-  uint32_t BaudRatePrescaler;   /*!< Specifies the Baud Rate prescaler value which will be
-                                     used to configure the transmit and receive SCK clock.
-                                     This parameter can be a value of @ref SPI_BaudRate_Prescaler
-                                     @note The communication clock is derived from the master
-                                     clock. The slave clock does not need to be set. */
-
-  uint32_t FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.
-                                     This parameter can be a value of @ref SPI_MSB_LSB_transmission */
-
-  uint32_t TIMode;              /*!< Specifies if the TI mode is enabled or not .
-                                     This parameter can be a value of @ref SPI_TI_mode */
-
-  uint32_t CRCCalculation;      /*!< Specifies if the CRC calculation is enabled or not.
-                                     This parameter can be a value of @ref SPI_CRC_Calculation */
-
-  uint32_t CRCPolynomial;       /*!< Specifies the polynomial used for the CRC calculation.
-                                     This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
-
-  uint32_t CRCLength;           /*!< Specifies the CRC Length used for the CRC calculation.
-                                     CRC Length is only used with Data8 and Data16, not other data size
-                                     This parameter can be a value of @ref SPI_CRC_length */
-
-  uint32_t NSSPMode;            /*!< Specifies whether the NSSP signal is enabled or not .
-                                     This parameter can be a value of @ref SPI_NSSP_Mode
-                                     This mode is activated by the NSSP bit in the SPIx_CR2 register and
-                                     it takes effect only if the SPI interface is configured as Motorola SPI
-                                     master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,
-                                     CPOL setting is ignored).. */
-} SPI_InitTypeDef;
-
-/**
-  * @brief  HAL State structures definition
-  */
-typedef enum
-{
-  HAL_SPI_STATE_RESET      = 0x00,    /*!< Peripheral not Initialized                         */
-  HAL_SPI_STATE_READY      = 0x01,    /*!< Peripheral Initialized and ready for use           */
-  HAL_SPI_STATE_BUSY       = 0x02,    /*!< an internal process is ongoing                     */
-  HAL_SPI_STATE_BUSY_TX    = 0x03,    /*!< Data Transmission process is ongoing               */
-  HAL_SPI_STATE_BUSY_RX    = 0x04,    /*!< Data Reception process is ongoing                  */
-  HAL_SPI_STATE_BUSY_TX_RX = 0x05,    /*!< Data Transmission and Reception process is ongoing*/
-  HAL_SPI_STATE_ERROR      = 0x06     /*!< SPI error state                                   */
-}HAL_SPI_StateTypeDef;
-
-/**
-  * @brief  SPI handle Structure definition
-  */
-typedef struct __SPI_HandleTypeDef
-{
-  SPI_TypeDef             *Instance;      /* SPI registers base address     */
-
-  SPI_InitTypeDef         Init;           /* SPI communication parameters   */
-
-  uint8_t                 *pTxBuffPtr;    /* Pointer to SPI Tx transfer Buffer */
-
-  uint16_t                TxXferSize;     /* SPI Tx Transfer size */
-
-  uint16_t                TxXferCount;    /* SPI Tx Transfer Counter */
-
-  uint8_t                 *pRxBuffPtr;    /* Pointer to SPI Rx transfer Buffer */
-
-  uint16_t                RxXferSize;     /* SPI Rx Transfer size */
-
-  uint16_t                RxXferCount;    /* SPI Rx Transfer Counter */
-
-  uint32_t                CRCSize;        /* SPI CRC size used for the transfer */
-
-  void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on Rx IRQ handler   */
-
-  void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on Tx IRQ handler   */
-
-  DMA_HandleTypeDef       *hdmatx;        /* SPI Tx DMA Handle parameters   */
-
-  DMA_HandleTypeDef       *hdmarx;        /* SPI Rx DMA Handle parameters   */
-
-  HAL_LockTypeDef         Lock;           /* Locking object                 */
-
-  HAL_SPI_StateTypeDef    State;          /* SPI communication state        */
-
-  uint32_t                ErrorCode;      /* SPI Error code                 */
-
-}SPI_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup SPI_Exported_Constants SPI Exported Constants
-  * @{
-  */
-
-/** @defgroup SPI_Error_Code SPI Error Code
-  * @{
-  */
-#define HAL_SPI_ERROR_NONE   (uint32_t)0x00000000  /*!< No error                          */
-#define HAL_SPI_ERROR_MODF   (uint32_t)0x00000001  /*!< MODF error                        */
-#define HAL_SPI_ERROR_CRC    (uint32_t)0x00000002  /*!< CRC error                         */
-#define HAL_SPI_ERROR_OVR    (uint32_t)0x00000004  /*!< OVR error                         */
-#define HAL_SPI_ERROR_FRE    (uint32_t)0x00000008  /*!< FRE error                         */
-#define HAL_SPI_ERROR_DMA    (uint32_t)0x00000010  /*!< DMA transfer error                */
-#define HAL_SPI_ERROR_FLAG   (uint32_t)0x00000020  /*!< Error on BSY/TXE/FTLVL/FRLVL Flag */
-#define HAL_SPI_ERROR_UNKNOW (uint32_t)0x00000040  /*!< Unknown error                     */
-/**
-  * @}
-  */
-
-
-/** @defgroup SPI_Mode SPI Mode
-  * @{
-  */
-#define SPI_MODE_SLAVE                  ((uint32_t)0x00000000)
-#define SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Direction SPI Direction Mode
-  * @{
-  */
-#define SPI_DIRECTION_2LINES            ((uint32_t)0x00000000)
-#define SPI_DIRECTION_2LINES_RXONLY     SPI_CR1_RXONLY
-#define SPI_DIRECTION_1LINE             SPI_CR1_BIDIMODE
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Data_Size SPI Data Size
-  * @{
-  */
-#define SPI_DATASIZE_4BIT               ((uint32_t)0x0300)
-#define SPI_DATASIZE_5BIT               ((uint32_t)0x0400)
-#define SPI_DATASIZE_6BIT               ((uint32_t)0x0500)
-#define SPI_DATASIZE_7BIT               ((uint32_t)0x0600)
-#define SPI_DATASIZE_8BIT               ((uint32_t)0x0700)
-#define SPI_DATASIZE_9BIT               ((uint32_t)0x0800)
-#define SPI_DATASIZE_10BIT              ((uint32_t)0x0900)
-#define SPI_DATASIZE_11BIT              ((uint32_t)0x0A00)
-#define SPI_DATASIZE_12BIT              ((uint32_t)0x0B00)
-#define SPI_DATASIZE_13BIT              ((uint32_t)0x0C00)
-#define SPI_DATASIZE_14BIT              ((uint32_t)0x0D00)
-#define SPI_DATASIZE_15BIT              ((uint32_t)0x0E00)
-#define SPI_DATASIZE_16BIT              ((uint32_t)0x0F00)
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
-  * @{
-  */
-#define SPI_POLARITY_LOW                ((uint32_t)0x00000000)
-#define SPI_POLARITY_HIGH               SPI_CR1_CPOL
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Clock_Phase SPI Clock Phase
-  * @{
-  */
-#define SPI_PHASE_1EDGE                 ((uint32_t)0x00000000)
-#define SPI_PHASE_2EDGE                 SPI_CR1_CPHA
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Slave_Select_management SPI Slave Select management
-  * @{
-  */
-#define SPI_NSS_SOFT                    SPI_CR1_SSM
-#define SPI_NSS_HARD_INPUT              ((uint32_t)0x00000000)
-#define SPI_NSS_HARD_OUTPUT             ((uint32_t)0x00040000)
-/**
-  * @}
-  */
-
-/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
-  * @{
-  */
-#define SPI_NSS_PULSE_ENABLE            SPI_CR2_NSSP
-#define SPI_NSS_PULSE_DISABLE           ((uint32_t)0x00000000)
-/**
-  * @}
-  */
-
-/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
-  * @{
-  */
-#define SPI_BAUDRATEPRESCALER_2         ((uint32_t)0x00000000)
-#define SPI_BAUDRATEPRESCALER_4         ((uint32_t)0x00000008)
-#define SPI_BAUDRATEPRESCALER_8         ((uint32_t)0x00000010)
-#define SPI_BAUDRATEPRESCALER_16        ((uint32_t)0x00000018)
-#define SPI_BAUDRATEPRESCALER_32        ((uint32_t)0x00000020)
-#define SPI_BAUDRATEPRESCALER_64        ((uint32_t)0x00000028)
-#define SPI_BAUDRATEPRESCALER_128       ((uint32_t)0x00000030)
-#define SPI_BAUDRATEPRESCALER_256       ((uint32_t)0x00000038)
-/**
-  * @}
-  */
-
-/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission
-  * @{
-  */
-#define SPI_FIRSTBIT_MSB                ((uint32_t)0x00000000)
-#define SPI_FIRSTBIT_LSB                SPI_CR1_LSBFIRST
-/**
-  * @}
-  */
-
-/** @defgroup SPI_TI_mode SPI TI mode
-  * @{
-  */
-#define SPI_TIMODE_DISABLE              ((uint32_t)0x00000000)
-#define SPI_TIMODE_ENABLE               SPI_CR2_FRF
-/**
-  * @}
-  */
-
-/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
-  * @{
-  */
-#define SPI_CRCCALCULATION_DISABLE      ((uint32_t)0x00000000)
-#define SPI_CRCCALCULATION_ENABLE       SPI_CR1_CRCEN
-/**
-  * @}
-  */
-
-/** @defgroup SPI_CRC_length SPI CRC Length
-  * @{
-  * This parameter can be one of the following values:
-  *     SPI_CRC_LENGTH_DATASIZE: aligned with the data size
-  *     SPI_CRC_LENGTH_8BIT    : CRC 8bit
-  *     SPI_CRC_LENGTH_16BIT   : CRC 16bit
-  */
-#define SPI_CRC_LENGTH_DATASIZE         ((uint32_t)0x00000000)
-#define SPI_CRC_LENGTH_8BIT             ((uint32_t)0x00000001)
-#define SPI_CRC_LENGTH_16BIT            ((uint32_t)0x00000002)
-/**
-  * @}
-  */
-
-/** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold
-  * @{
-  * This parameter can be one of the following values:
-  *     SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :
-  *          RXNE event is generated if the FIFO
-  *          level is greater or equal to 1/2(16-bits).
-  *     SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO
-  *          level is greater or equal to 1/4(8 bits). */
-#define SPI_RXFIFO_THRESHOLD            SPI_CR2_FRXTH
-#define SPI_RXFIFO_THRESHOLD_QF         SPI_CR2_FRXTH
-#define SPI_RXFIFO_THRESHOLD_HF         ((uint32_t)0x00000000)
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition
-  * @brief SPI Interrupt definition
-  *        Elements values convention: 0xXXXXXXXX
-  *           - XXXXXXXX  : Interrupt control mask
-  * @{
-  */
-#define SPI_IT_TXE                      SPI_CR2_TXEIE
-#define SPI_IT_RXNE                     SPI_CR2_RXNEIE
-#define SPI_IT_ERR                      SPI_CR2_ERRIE
-/**
-  * @}
-  */
-
-
-/** @defgroup SPI_Flag_definition SPI Flag definition
-  * @brief Flag definition
-  *        Elements values convention: 0xXXXXYYYY
-  *           - XXXX  : Flag register Index
-  *           - YYYY  : Flag mask
-  * @{
-  */
-#define SPI_FLAG_RXNE                   SPI_SR_RXNE   /* SPI status flag: Rx buffer not empty flag */
-#define SPI_FLAG_TXE                    SPI_SR_TXE    /* SPI status flag: Tx buffer empty flag */
-#define SPI_FLAG_BSY                    SPI_SR_BSY    /* SPI status flag: Busy flag */
-#define SPI_FLAG_CRCERR                 SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
-#define SPI_FLAG_MODF                   SPI_SR_MODF   /* SPI Error flag: Mode fault flag */
-#define SPI_FLAG_OVR                    SPI_SR_OVR    /* SPI Error flag: Overrun flag */
-#define SPI_FLAG_FRE                    SPI_SR_FRE    /* SPI Error flag: TI mode frame format error flag */
-#define SPI_FLAG_FTLVL                  SPI_SR_FTLVL  /* SPI fifo transmission level */
-#define SPI_FLAG_FRLVL                  SPI_SR_FRLVL  /* SPI fifo reception level */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level
-  * @{
-  */
-#define SPI_FTLVL_EMPTY           ((uint32_t)0x0000)
-#define SPI_FTLVL_QUARTER_FULL    ((uint32_t)0x0800)
-#define SPI_FTLVL_HALF_FULL       ((uint32_t)0x1000)
-#define SPI_FTLVL_FULL            ((uint32_t)0x1800)
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
-  * @{
-  */
-#define SPI_FRLVL_EMPTY           ((uint32_t)0x0000)
-#define SPI_FRLVL_QUARTER_FULL    ((uint32_t)0x0200)
-#define SPI_FRLVL_HALF_FULL       ((uint32_t)0x0400)
-#define SPI_FRLVL_FULL            ((uint32_t)0x0600)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros ------------------------------------------------------------*/
-/** @defgroup SPI_Exported_Macros SPI Exported Macros
-  * @{
-  */
-
-/** @brief  Reset SPI handle state.
-  * @param  __HANDLE__: SPI handle.
-  * @retval None
-  */
-#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
-
-/** @brief  Enable or disable the specified SPI interrupts.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
-  *        This parameter can be one of the following values:
-  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg SPI_IT_ERR: Error interrupt enable
-  * @retval None
-  */
-#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
-#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
-
-/** @brief  Check whether the specified SPI interrupt source is enabled or not.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @param  __INTERRUPT__: specifies the SPI interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg SPI_IT_ERR: Error interrupt enable
-  * @retval The new state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief  Check whether the specified SPI flag is set or not.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @param  __FLAG__: specifies the flag to check.
-  *        This parameter can be one of the following values:
-  *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag
-  *            @arg SPI_FLAG_TXE: Transmit buffer empty flag
-  *            @arg SPI_FLAG_CRCERR: CRC error flag
-  *            @arg SPI_FLAG_MODF: Mode fault flag
-  *            @arg SPI_FLAG_OVR: Overrun flag
-  *            @arg SPI_FLAG_BSY: Busy flag
-  *            @arg SPI_FLAG_FRE: Frame format error flag
-  *            @arg SPI_FLAG_FTLVL: SPI fifo transmission level
-  *            @arg SPI_FLAG_FRLVL: SPI fifo reception level
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Clear the SPI CRCERR pending flag.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
-
-/** @brief  Clear the SPI MODF pending flag.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  *
-  * @retval None
-  */
-#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)        \
-   do{                                              \
-     __IO uint32_t tmpreg;                          \
-     tmpreg = (__HANDLE__)->Instance->SR;           \
-     (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
-     UNUSED(tmpreg);                                \
-   } while(0)
-
-/** @brief  Clear the SPI OVR pending flag.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  *
-  * @retval None
-  */
-#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)         \
-   do{                                              \
-     __IO uint32_t tmpreg;                          \
-     tmpreg = (__HANDLE__)->Instance->DR;           \
-     tmpreg = (__HANDLE__)->Instance->SR;           \
-     UNUSED(tmpreg);                                \
-   } while(0)
-
-/** @brief  Clear the SPI FRE pending flag.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  *
-  * @retval None
-  */
-#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)         \
-   do{                                              \
-     __IO uint32_t tmpreg;                          \
-     tmpreg = (__HANDLE__)->Instance->SR;           \
-     UNUSED(tmpreg);                                \
-   } while(0)
-
-/** @brief  Enable the SPI peripheral.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |=  SPI_CR1_SPE)
-
-/** @brief  Disable the SPI peripheral.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
-
-/**
-  * @}
-  */
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup SPI_Private_Macros   SPI Private Macros
-  * @{
-  */
-
-/** @brief  Set the SPI transmit-only mode.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
-
-/** @brief  Set the SPI receive-only mode.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
-
-/** @brief  Reset the CRC calculation of the SPI.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
-                                     (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
-
-#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
-                           ((MODE) == SPI_MODE_MASTER))
-
-#define IS_SPI_DIRECTION(MODE)   (((MODE) == SPI_DIRECTION_2LINES) || \
-                                  ((MODE) == SPI_DIRECTION_2LINES_RXONLY) ||\
-                                  ((MODE) == SPI_DIRECTION_1LINE))
-
-#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
-
-#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \
-                                                 ((MODE) == SPI_DIRECTION_1LINE))
-
-#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
-                                   ((DATASIZE) == SPI_DATASIZE_15BIT) || \
-                                   ((DATASIZE) == SPI_DATASIZE_14BIT) || \
-                                   ((DATASIZE) == SPI_DATASIZE_13BIT) || \
-                                   ((DATASIZE) == SPI_DATASIZE_12BIT) || \
-                                   ((DATASIZE) == SPI_DATASIZE_11BIT) || \
-                                   ((DATASIZE) == SPI_DATASIZE_10BIT) || \
-                                   ((DATASIZE) == SPI_DATASIZE_9BIT)  || \
-                                   ((DATASIZE) == SPI_DATASIZE_8BIT)  || \
-                                   ((DATASIZE) == SPI_DATASIZE_7BIT)  || \
-                                   ((DATASIZE) == SPI_DATASIZE_6BIT)  || \
-                                   ((DATASIZE) == SPI_DATASIZE_5BIT)  || \
-                                   ((DATASIZE) == SPI_DATASIZE_4BIT))
-
-#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
-                           ((CPOL) == SPI_POLARITY_HIGH))
-
-#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
-                           ((CPHA) == SPI_PHASE_2EDGE))
-
-#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
-                         ((NSS) == SPI_NSS_HARD_INPUT) || \
-                         ((NSS) == SPI_NSS_HARD_OUTPUT))
-
-#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \
-                           ((NSSP) == SPI_NSS_PULSE_DISABLE))
-
-#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
-                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
-                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
-                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
-                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
-                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
-                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
-                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
-
-#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
-                               ((BIT) == SPI_FIRSTBIT_LSB))
-
-#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
-                             ((MODE) == SPI_TIMODE_ENABLE))
-
-#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
-                                             ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
-
-#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\
-                                   ((LENGTH) == SPI_CRC_LENGTH_8BIT)  ||   \
-                                   ((LENGTH) == SPI_CRC_LENGTH_16BIT))
-
-#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))
-
-
-/**
-  * @}
-  */
-
-/* Include SPI HAL Extended module */
-#include "stm32l4xx_hal_spi_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SPI_Exported_Functions
-  * @{
-  */
-
-/* Initialization and de-initialization functions  ****************************/
-/** @addtogroup SPI_Exported_Functions_Group1
-  * @{
-  */
-HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
-void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
-void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
-/**
-  * @}
-  */
-
-/* IO operation functions *****************************************************/
-/** @addtogroup SPI_Exported_Functions_Group2
-  * @{
-  */
-HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
-
-void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
-/**
-  * @}
-  */
-
-/* Peripheral State and Error functions ***************************************/
-/** @addtogroup SPI_Exported_Functions_Group3
-  * @{
-  */
-HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
-uint32_t             HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L4xx_HAL_SPI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/inc/stm32l4xx_hal_spi_ex.h b/stmhal/hal/l4/inc/stm32l4xx_hal_spi_ex.h
deleted file mode 100644
index db1f6571f9..0000000000
--- a/stmhal/hal/l4/inc/stm32l4xx_hal_spi_ex.h
+++ /dev/null
@@ -1,93 +0,0 @@
- /**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_spi_ex.h
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   Header file of SPI HAL Extended module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L4xx_HAL_SPI_EX_H
-#define __STM32L4xx_HAL_SPI_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup SPIEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macros ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SPIEx_Exported_Functions
-  * @{
-  */
-
-/* Initialization and de-initialization functions  ****************************/
-/* IO operation functions *****************************************************/
-/** @addtogroup SPIEx_Exported_Functions_Group1
-  * @{
-  */
-HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L4xx_HAL_SPI_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/inc/stm32l4xx_hal_tim.h b/stmhal/hal/l4/inc/stm32l4xx_hal_tim.h
deleted file mode 100644
index 931b03294f..0000000000
--- a/stmhal/hal/l4/inc/stm32l4xx_hal_tim.h
+++ /dev/null
@@ -1,1978 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_tim.h
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   Header file of TIM HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L4xx_HAL_TIM_H
-#define __STM32L4xx_HAL_TIM_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup TIM
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup TIM_Exported_Types TIM Exported Types
-  * @{
-  */
-
-/**
-  * @brief  TIM Time base Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
-                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
-  uint32_t CounterMode;       /*!< Specifies the counter mode.
-                                   This parameter can be a value of @ref TIM_Counter_Mode */
-
-  uint32_t Period;            /*!< Specifies the period value to be loaded into the active
-                                   Auto-Reload Register at the next update event.
-                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.  */
-
-  uint32_t ClockDivision;     /*!< Specifies the clock division.
-                                   This parameter can be a value of @ref TIM_ClockDivision */
-
-  uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
-                                    reaches zero, an update event is generated and counting restarts
-                                    from the RCR value (N).
-                                    This means in PWM mode that (N+1) corresponds to:
-                                        - the number of PWM periods in edge-aligned mode
-                                        - the number of half PWM period in center-aligned mode
-                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
-                                     @note This parameter is valid only for TIM1 and TIM8. */
-} TIM_Base_InitTypeDef;
-
-/**
-  * @brief  TIM Output Compare Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t OCMode;        /*!< Specifies the TIM mode.
-                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
-
-  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
-                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
-  uint32_t OCPolarity;    /*!< Specifies the output polarity.
-                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */
-
-  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
-                               This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
-                               @note This parameter is valid only for TIM1 and TIM8. */
-
-  uint32_t OCFastMode;   /*!< Specifies the Fast mode state.
-                               This parameter can be a value of @ref TIM_Output_Fast_State
-                               @note This parameter is valid only in PWM1 and PWM2 mode. */
-
-
-  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
-                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State
-                               @note This parameter is valid only for TIM1 and TIM8. */
-
-  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
-                               This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
-                               @note This parameter is valid only for TIM1 and TIM8. */
-} TIM_OC_InitTypeDef;
-
-/**
-  * @brief  TIM One Pulse Mode Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t OCMode;        /*!< Specifies the TIM mode.
-                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
-
-  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
-                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
-  uint32_t OCPolarity;    /*!< Specifies the output polarity.
-                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */
-
-  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
-                               This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
-                               @note This parameter is valid only for TIM1 and TIM8. */
-
-  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
-                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State
-                               @note This parameter is valid only for TIM1 and TIM8. */
-
-  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
-                               This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
-                               @note This parameter is valid only for TIM1 and TIM8. */
-
-  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
-                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
-  uint32_t ICSelection;   /*!< Specifies the input.
-                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
-  uint32_t ICFilter;      /*!< Specifies the input capture filter.
-                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_OnePulse_InitTypeDef;
-
-
-/**
-  * @brief  TIM Input Capture Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t  ICPolarity;   /*!< Specifies the active edge of the input signal.
-                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
-  uint32_t ICSelection;  /*!< Specifies the input.
-                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
-  uint32_t ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
-                              This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
-  uint32_t ICFilter;     /*!< Specifies the input capture filter.
-                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_IC_InitTypeDef;
-
-/**
-  * @brief  TIM Encoder Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t EncoderMode;   /*!< Specifies the active edge of the input signal.
-                               This parameter can be a value of @ref TIM_Encoder_Mode */
-
-  uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.
-                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
-  uint32_t IC1Selection;  /*!< Specifies the input.
-                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
-  uint32_t IC1Prescaler;  /*!< Specifies the Input Capture Prescaler.
-                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
-  uint32_t IC1Filter;     /*!< Specifies the input capture filter.
-                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-
-  uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.
-                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
-  uint32_t IC2Selection;  /*!< Specifies the input.
-                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
-  uint32_t IC2Prescaler;  /*!< Specifies the Input Capture Prescaler.
-                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
-  uint32_t IC2Filter;     /*!< Specifies the input capture filter.
-                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_Encoder_InitTypeDef;
-
-
-/**
-  * @brief  Clock Configuration Handle Structure definition
-  */
-typedef struct
-{
-  uint32_t ClockSource;     /*!< TIM clock sources
-                                 This parameter can be a value of @ref TIM_Clock_Source */
-  uint32_t ClockPolarity;   /*!< TIM clock polarity
-                                 This parameter can be a value of @ref TIM_Clock_Polarity */
-  uint32_t ClockPrescaler;  /*!< TIM clock prescaler
-                                 This parameter can be a value of @ref TIM_Clock_Prescaler */
-  uint32_t ClockFilter;    /*!< TIM clock filter
-                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-}TIM_ClockConfigTypeDef;
-
-/**
-  * @brief  Clear Input Configuration Handle Structure definition
-  */
-typedef struct
-{
-  uint32_t ClearInputState;      /*!< TIM clear Input state
-                                      This parameter can be ENABLE or DISABLE */
-  uint32_t ClearInputSource;     /*!< TIM clear Input sources
-                                      This parameter can be a value of @ref TIM_ClearInput_Source */
-  uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity
-                                      This parameter can be a value of @ref TIM_ClearInput_Polarity */
-  uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler
-                                      This parameter can be a value of @ref TIM_ClearInput_Prescaler */
-  uint32_t ClearInputFilter;    /*!< TIM Clear Input filter
-                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-}TIM_ClearInputConfigTypeDef;
-
-/**
-  * @brief  TIM Master configuration Structure definition
-  * @note   Advanced timers provide TRGO2 internal line which is redirected
-  *         to the ADC
-  */
-typedef struct {
-  uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection
-                                      This parameter can be a value of @ref TIM_Master_Mode_Selection */
-  uint32_t  MasterOutputTrigger2;  /*!< Trigger output2 (TRGO2) selection
-                                      This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */
-  uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection
-                                      This parameter can be a value of @ref TIM_Master_Slave_Mode */
-}TIM_MasterConfigTypeDef;
-
-/**
-  * @brief  TIM Slave configuration Structure definition
-  */
-typedef struct {
-  uint32_t  SlaveMode;      /*!< Slave mode selection
-                               This parameter can be a value of @ref TIM_Slave_Mode */
-  uint32_t  InputTrigger;      /*!< Input Trigger source
-                                  This parameter can be a value of @ref TIM_Trigger_Selection */
-  uint32_t  TriggerPolarity;   /*!< Input Trigger polarity
-                                  This parameter can be a value of @ref TIM_Trigger_Polarity */
-  uint32_t  TriggerPrescaler;  /*!< Input trigger prescaler
-                                  This parameter can be a value of @ref TIM_Trigger_Prescaler */
-  uint32_t  TriggerFilter;     /*!< Input trigger filter
-                                  This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF  */
-
-}TIM_SlaveConfigTypeDef;
-
-/**
-  * @brief  TIM Break input(s) and Dead time configuration Structure definition
-  * @note   2 break inputs can be configured (BKIN and BKIN2) with configurable
-  *        filter and polarity.
-  */
-typedef struct
-{
-  uint32_t OffStateRunMode;	      /*!< TIM off state in run mode
-                                         This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
-  uint32_t OffStateIDLEMode;	      /*!< TIM off state in IDLE mode
-                                         This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
-  uint32_t LockLevel;	 	      /*!< TIM Lock level
-                                         This parameter can be a value of @ref TIM_Lock_level */
-  uint32_t DeadTime;	 	      /*!< TIM dead Time
-                                         This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
-  uint32_t BreakState;	 	      /*!< TIM Break State
-                                         This parameter can be a value of @ref TIM_Break_Input_enable_disable */
-  uint32_t BreakPolarity;             /*!< TIM Break input polarity
-                                         This parameter can be a value of @ref TIM_Break_Polarity */
-  uint32_t BreakFilter;               /*!< Specifies the break input filter.
-                                         This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-  uint32_t Break2State;	 	      /*!< TIM Break2 State
-                                         This parameter can be a value of @ref TIM_Break2_Input_enable_disable */
-  uint32_t Break2Polarity;            /*!< TIM Break2 input polarity
-                                         This parameter can be a value of @ref TIM_Break2_Polarity */
-  uint32_t Break2Filter;              /*!< TIM break2 input filter.
-                                         This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-  uint32_t AutomaticOutput;           /*!< TIM Automatic Output Enable state
-                                         This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
-} TIM_BreakDeadTimeConfigTypeDef;
-
-/**
-  * @brief  HAL State structures definition
-  */
-typedef enum
-{
-  HAL_TIM_STATE_RESET             = 0x00,    /*!< Peripheral not yet initialized or disabled  */
-  HAL_TIM_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use    */
-  HAL_TIM_STATE_BUSY              = 0x02,    /*!< An internal process is ongoing              */
-  HAL_TIM_STATE_TIMEOUT           = 0x03,    /*!< Timeout state                               */
-  HAL_TIM_STATE_ERROR             = 0x04     /*!< Reception process is ongoing                */
-}HAL_TIM_StateTypeDef;
-
-/**
-  * @brief  HAL Active channel structures definition
-  */
-typedef enum
-{
-  HAL_TIM_ACTIVE_CHANNEL_1        = 0x01,    /*!< The active channel is 1     */
-  HAL_TIM_ACTIVE_CHANNEL_2        = 0x02,    /*!< The active channel is 2     */
-  HAL_TIM_ACTIVE_CHANNEL_3        = 0x04,    /*!< The active channel is 3     */
-  HAL_TIM_ACTIVE_CHANNEL_4        = 0x08,    /*!< The active channel is 4     */
-  HAL_TIM_ACTIVE_CHANNEL_5        = 0x10,    /*!< The active channel is 5     */
-  HAL_TIM_ACTIVE_CHANNEL_6        = 0x20,    /*!< The active channel is 6     */
-  HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00    /*!< All active channels cleared */
-}HAL_TIM_ActiveChannel;
-
-/**
-  * @brief  TIM Time Base Handle Structure definition
-  */
-typedef struct
-{
-  TIM_TypeDef              *Instance;     /*!< Register base address             */
-  TIM_Base_InitTypeDef     Init;          /*!< TIM Time Base required parameters */
-  HAL_TIM_ActiveChannel    Channel;       /*!< Active channel                    */
-  DMA_HandleTypeDef        *hdma[7];      /*!< DMA Handlers array
-                                             This array is accessed by a @ref DMA_Handle_index */
-  HAL_LockTypeDef          Lock;          /*!< Locking object                    */
-  __IO HAL_TIM_StateTypeDef   State;         /*!< TIM operation state               */
-}TIM_HandleTypeDef;
-
-/**
-  * @}
-  */
-/* End of exported types -----------------------------------------------------*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIM_Exported_Constants TIM Exported Constants
-  * @{
-  */
-
-/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
-  * @{
-  */
-#define TIM_CLEARINPUTSOURCE_ETR            ((uint32_t)0x0001)
-#define TIM_CLEARINPUTSOURCE_OCREFCLR       ((uint32_t)0x0002)
-#define TIM_CLEARINPUTSOURCE_NONE           ((uint32_t)0x0000)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
-  * @{
-  */
-#define TIM_DMABASE_CR1                    (0x00000000)
-#define TIM_DMABASE_CR2                    (0x00000001)
-#define TIM_DMABASE_SMCR                   (0x00000002)
-#define TIM_DMABASE_DIER                   (0x00000003)
-#define TIM_DMABASE_SR                     (0x00000004)
-#define TIM_DMABASE_EGR                    (0x00000005)
-#define TIM_DMABASE_CCMR1                  (0x00000006)
-#define TIM_DMABASE_CCMR2                  (0x00000007)
-#define TIM_DMABASE_CCER                   (0x00000008)
-#define TIM_DMABASE_CNT                    (0x00000009)
-#define TIM_DMABASE_PSC                    (0x0000000A)
-#define TIM_DMABASE_ARR                    (0x0000000B)
-#define TIM_DMABASE_RCR                    (0x0000000C)
-#define TIM_DMABASE_CCR1                   (0x0000000D)
-#define TIM_DMABASE_CCR2                   (0x0000000E)
-#define TIM_DMABASE_CCR3                   (0x0000000F)
-#define TIM_DMABASE_CCR4                   (0x00000010)
-#define TIM_DMABASE_BDTR                   (0x00000011)
-#define TIM_DMABASE_DCR                    (0x00000012)
-#define TIM_DMABASE_DMAR                   (0x00000013)
-#define TIM_DMABASE_OR1                    (0x00000014)
-#define TIM_DMABASE_CCMR3                  (0x00000015)
-#define TIM_DMABASE_CCR5                   (0x00000016)
-#define TIM_DMABASE_CCR6                   (0x00000017)
-#define TIM_DMABASE_OR2                    (0x00000018)
-#define TIM_DMABASE_OR3                    (0x00000019)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Event_Source TIM  Extended Event Source
-  * @{
-  */
-#define TIM_EVENTSOURCE_UPDATE              TIM_EGR_UG     /*!< Reinitialize the counter and generates an update of the registers */
-#define TIM_EVENTSOURCE_CC1                 TIM_EGR_CC1G   /*!< A capture/compare event is generated on channel 1 */
-#define TIM_EVENTSOURCE_CC2                 TIM_EGR_CC2G   /*!< A capture/compare event is generated on channel 2 */
-#define TIM_EVENTSOURCE_CC3                 TIM_EGR_CC3G   /*!< A capture/compare event is generated on channel 3 */
-#define TIM_EVENTSOURCE_CC4                 TIM_EGR_CC4G   /*!< A capture/compare event is generated on channel 4 */
-#define TIM_EVENTSOURCE_COM                 TIM_EGR_COMG   /*!< A commutation event is generated */
-#define TIM_EVENTSOURCE_TRIGGER             TIM_EGR_TG     /*!< A trigger event is generated */
-#define TIM_EVENTSOURCE_BREAK               TIM_EGR_BG     /*!< A break event is generated */
-#define TIM_EVENTSOURCE_BREAK2              TIM_EGR_B2G    /*!< A break 2 event is generated */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
-  * @{
-  */
-#define  TIM_INPUTCHANNELPOLARITY_RISING      ((uint32_t)0x00000000)            /*!< Polarity for TIx source */
-#define  TIM_INPUTCHANNELPOLARITY_FALLING     (TIM_CCER_CC1P)                   /*!< Polarity for TIx source */
-#define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
-  * @{
-  */
-#define TIM_ETRPOLARITY_INVERTED              (TIM_SMCR_ETP)                    /*!< Polarity for ETR source */
-#define TIM_ETRPOLARITY_NONINVERTED           ((uint32_t)0x0000)                /*!< Polarity for ETR source */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
-  * @{
-  */
-#define TIM_ETRPRESCALER_DIV1                 ((uint32_t)0x0000)                /*!< No prescaler is used */
-#define TIM_ETRPRESCALER_DIV2                 (TIM_SMCR_ETPS_0)                 /*!< ETR input source is divided by 2 */
-#define TIM_ETRPRESCALER_DIV4                 (TIM_SMCR_ETPS_1)                 /*!< ETR input source is divided by 4 */
-#define TIM_ETRPRESCALER_DIV8                 (TIM_SMCR_ETPS)                   /*!< ETR input source is divided by 8 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Counter_Mode TIM Counter Mode
-  * @{
-  */
-#define TIM_COUNTERMODE_UP                 ((uint32_t)0x0000)
-#define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR
-#define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0
-#define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1
-#define TIM_COUNTERMODE_CENTERALIGNED3     TIM_CR1_CMS
-/**
-  * @}
-  */
-
-/** @defgroup TIM_ClockDivision TIM Clock Division
-  * @{
-  */
-#define TIM_CLOCKDIVISION_DIV1             ((uint32_t)0x0000)
-#define TIM_CLOCKDIVISION_DIV2             (TIM_CR1_CKD_0)
-#define TIM_CLOCKDIVISION_DIV4             (TIM_CR1_CKD_1)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Compare_State TIM Output Compare State
-  * @{
-  */
-#define TIM_OUTPUTSTATE_DISABLE            ((uint32_t)0x0000)
-#define TIM_OUTPUTSTATE_ENABLE             (TIM_CCER_CC1E)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Fast_State TIM Output Fast State
-  * @{
-  */
-#define TIM_OCFAST_DISABLE                 ((uint32_t)0x0000)
-#define TIM_OCFAST_ENABLE                  (TIM_CCMR1_OC1FE)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
-  * @{
-  */
-#define TIM_OUTPUTNSTATE_DISABLE           ((uint32_t)0x0000)
-#define TIM_OUTPUTNSTATE_ENABLE            (TIM_CCER_CC1NE)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
-  * @{
-  */
-#define TIM_OCPOLARITY_HIGH                ((uint32_t)0x0000)
-#define TIM_OCPOLARITY_LOW                 (TIM_CCER_CC1P)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
-  * @{
-  */
-#define TIM_OCNPOLARITY_HIGH               ((uint32_t)0x0000)
-#define TIM_OCNPOLARITY_LOW                (TIM_CCER_CC1NP)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
-  * @{
-  */
-#define TIM_OCIDLESTATE_SET                (TIM_CR2_OIS1)
-#define TIM_OCIDLESTATE_RESET              ((uint32_t)0x0000)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
-  * @{
-  */
-#define TIM_OCNIDLESTATE_SET               (TIM_CR2_OIS1N)
-#define TIM_OCNIDLESTATE_RESET             ((uint32_t)0x0000)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
-  * @{
-  */
-#define  TIM_ICPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING
-#define  TIM_ICPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING
-#define  TIM_ICPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
-  * @{
-  */
-#define TIM_ICSELECTION_DIRECTTI           (TIM_CCMR1_CC1S_0)   /*!< TIM Input 1, 2, 3 or 4 is selected to be
-                                                                               connected to IC1, IC2, IC3 or IC4, respectively */
-#define TIM_ICSELECTION_INDIRECTTI         (TIM_CCMR1_CC1S_1)   /*!< TIM Input 1, 2, 3 or 4 is selected to be
-                                                                               connected to IC2, IC1, IC4 or IC3, respectively */
-#define TIM_ICSELECTION_TRC                (TIM_CCMR1_CC1S)     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
-  * @{
-  */
-#define TIM_ICPSC_DIV1                     ((uint32_t)0x0000)                 /*!< Capture performed each time an edge is detected on the capture input */
-#define TIM_ICPSC_DIV2                     (TIM_CCMR1_IC1PSC_0)     /*!< Capture performed once every 2 events */
-#define TIM_ICPSC_DIV4                     (TIM_CCMR1_IC1PSC_1)     /*!< Capture performed once every 4 events */
-#define TIM_ICPSC_DIV8                     (TIM_CCMR1_IC1PSC)       /*!< Capture performed once every 8 events */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
-  * @{
-  */
-#define TIM_OPMODE_SINGLE                  (TIM_CR1_OPM)
-#define TIM_OPMODE_REPETITIVE              ((uint32_t)0x0000)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
-  * @{
-  */
-#define TIM_ENCODERMODE_TI1                (TIM_SMCR_SMS_0)
-#define TIM_ENCODERMODE_TI2                (TIM_SMCR_SMS_1)
-#define TIM_ENCODERMODE_TI12               (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
-  * @{
-  */
-#define TIM_IT_UPDATE                      (TIM_DIER_UIE)
-#define TIM_IT_CC1                         (TIM_DIER_CC1IE)
-#define TIM_IT_CC2                         (TIM_DIER_CC2IE)
-#define TIM_IT_CC3                         (TIM_DIER_CC3IE)
-#define TIM_IT_CC4                         (TIM_DIER_CC4IE)
-#define TIM_IT_COM                         (TIM_DIER_COMIE)
-#define TIM_IT_TRIGGER                     (TIM_DIER_TIE)
-#define TIM_IT_BREAK                       (TIM_DIER_BIE)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Commutation_Source  TIM Commutation Source 
-  * @{
-  */  
-#define TIM_COMMUTATION_TRGI              (TIM_CR2_CCUS)
-#define TIM_COMMUTATION_SOFTWARE          ((uint32_t)0x0000)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_DMA_sources TIM DMA Sources
-  * @{
-  */
-#define TIM_DMA_UPDATE                     (TIM_DIER_UDE)
-#define TIM_DMA_CC1                        (TIM_DIER_CC1DE)
-#define TIM_DMA_CC2                        (TIM_DIER_CC2DE)
-#define TIM_DMA_CC3                        (TIM_DIER_CC3DE)
-#define TIM_DMA_CC4                        (TIM_DIER_CC4DE)
-#define TIM_DMA_COM                        (TIM_DIER_COMDE)
-#define TIM_DMA_TRIGGER                    (TIM_DIER_TDE)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Flag_definition TIM Flag Definition
-  * @{
-  */
-#define TIM_FLAG_UPDATE                    (TIM_SR_UIF)
-#define TIM_FLAG_CC1                       (TIM_SR_CC1IF)
-#define TIM_FLAG_CC2                       (TIM_SR_CC2IF)
-#define TIM_FLAG_CC3                       (TIM_SR_CC3IF)
-#define TIM_FLAG_CC4                       (TIM_SR_CC4IF)
-#define TIM_FLAG_CC5                       (TIM_SR_CC5IF)
-#define TIM_FLAG_CC6                       (TIM_SR_CC6IF)
-#define TIM_FLAG_COM                       (TIM_SR_COMIF)
-#define TIM_FLAG_TRIGGER                   (TIM_SR_TIF)
-#define TIM_FLAG_BREAK                     (TIM_SR_BIF)
-#define TIM_FLAG_BREAK2                    (TIM_SR_B2IF)
-#define TIM_FLAG_SYSTEM_BREAK              (TIM_SR_SBIF)
-#define TIM_FLAG_CC1OF                     (TIM_SR_CC1OF)
-#define TIM_FLAG_CC2OF                     (TIM_SR_CC2OF)
-#define TIM_FLAG_CC3OF                     (TIM_SR_CC3OF)
-#define TIM_FLAG_CC4OF                     (TIM_SR_CC4OF)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Channel TIM Channel
-  * @{
-  */
-#define TIM_CHANNEL_1                      ((uint32_t)0x0000)
-#define TIM_CHANNEL_2                      ((uint32_t)0x0004)
-#define TIM_CHANNEL_3                      ((uint32_t)0x0008)
-#define TIM_CHANNEL_4                      ((uint32_t)0x000C)
-#define TIM_CHANNEL_5                      ((uint32_t)0x0010)
-#define TIM_CHANNEL_6                      ((uint32_t)0x0014)
-#define TIM_CHANNEL_ALL                    ((uint32_t)0x003C)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Clock_Source TIM Clock Source
-  * @{
-  */
-#define	TIM_CLOCKSOURCE_ETRMODE2    (TIM_SMCR_ETPS_1)
-#define	TIM_CLOCKSOURCE_INTERNAL    (TIM_SMCR_ETPS_0)
-#define	TIM_CLOCKSOURCE_ITR0        ((uint32_t)0x0000)
-#define	TIM_CLOCKSOURCE_ITR1        (TIM_SMCR_TS_0)
-#define	TIM_CLOCKSOURCE_ITR2        (TIM_SMCR_TS_1)
-#define	TIM_CLOCKSOURCE_ITR3        (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
-#define	TIM_CLOCKSOURCE_TI1ED       (TIM_SMCR_TS_2)
-#define	TIM_CLOCKSOURCE_TI1         (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
-#define	TIM_CLOCKSOURCE_TI2         (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
-#define	TIM_CLOCKSOURCE_ETRMODE1    (TIM_SMCR_TS)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
-  * @{
-  */
-#define TIM_CLOCKPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED          /*!< Polarity for ETRx clock sources */
-#define TIM_CLOCKPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED       /*!< Polarity for ETRx clock sources */
-#define TIM_CLOCKPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING   /*!< Polarity for TIx clock sources */
-#define TIM_CLOCKPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING   /*!< Polarity for TIx clock sources */
-#define TIM_CLOCKPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE  /*!< Polarity for TIx clock sources */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
-  * @{
-  */
-#define TIM_CLOCKPRESCALER_DIV1                 TIM_ETRPRESCALER_DIV1     /*!< No prescaler is used */
-#define TIM_CLOCKPRESCALER_DIV2                 TIM_ETRPRESCALER_DIV2     /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
-#define TIM_CLOCKPRESCALER_DIV4                 TIM_ETRPRESCALER_DIV4     /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
-#define TIM_CLOCKPRESCALER_DIV8                 TIM_ETRPRESCALER_DIV8     /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
-  * @{
-  */
-#define TIM_CLEARINPUTPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED                    /*!< Polarity for ETRx pin */
-#define TIM_CLEARINPUTPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED                          /*!< Polarity for ETRx pin */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
-  * @{
-  */
-#define TIM_CLEARINPUTPRESCALER_DIV1              TIM_ETRPRESCALER_DIV1      /*!< No prescaler is used */
-#define TIM_CLEARINPUTPRESCALER_DIV2              TIM_ETRPRESCALER_DIV2      /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
-#define TIM_CLEARINPUTPRESCALER_DIV4              TIM_ETRPRESCALER_DIV4      /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
-#define TIM_CLEARINPUTPRESCALER_DIV8              TIM_ETRPRESCALER_DIV8        /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
-  * @{
-  */
-#define TIM_OSSR_ENABLE 	                 (TIM_BDTR_OSSR)
-#define TIM_OSSR_DISABLE                   ((uint32_t)0x0000)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
-  * @{
-  */
-#define TIM_OSSI_ENABLE	 	                 (TIM_BDTR_OSSI)
-#define TIM_OSSI_DISABLE                   ((uint32_t)0x0000)
-/**
-  * @}
-  */
-/** @defgroup TIM_Lock_level  TIM Lock level
-  * @{
-  */
-#define TIM_LOCKLEVEL_OFF	                 ((uint32_t)0x0000)
-#define TIM_LOCKLEVEL_1                    (TIM_BDTR_LOCK_0)
-#define TIM_LOCKLEVEL_2                    (TIM_BDTR_LOCK_1)
-#define TIM_LOCKLEVEL_3                    (TIM_BDTR_LOCK)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
-  * @{
-  */
-#define TIM_BREAK_ENABLE                   (TIM_BDTR_BKE)
-#define TIM_BREAK_DISABLE                  ((uint32_t)0x0000)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
-  * @{
-  */
-#define TIM_BREAKPOLARITY_LOW              ((uint32_t)0x0000)
-#define TIM_BREAKPOLARITY_HIGH             (TIM_BDTR_BKP)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable
-  * @{
-  */
-#define TIM_BREAK2_DISABLE                 ((uint32_t)0x00000000)
-#define TIM_BREAK2_ENABLE                  ((uint32_t)TIM_BDTR_BK2E)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity
-  * @{
-  */
-#define TIM_BREAK2POLARITY_LOW             ((uint32_t)0x00000000)
-#define TIM_BREAK2POLARITY_HIGH            ((uint32_t)TIM_BDTR_BK2P)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
-  * @{
-  */
-#define TIM_AUTOMATICOUTPUT_ENABLE         (TIM_BDTR_AOE)
-#define	TIM_AUTOMATICOUTPUT_DISABLE        ((uint32_t)0x0000)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3
-  * @{
-  */
-#define TIM_GROUPCH5_NONE       (uint32_t)0x00000000  /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
-#define TIM_GROUPCH5_OC1REFC    (TIM_CCR5_GC5C1)      /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
-#define TIM_GROUPCH5_OC2REFC    (TIM_CCR5_GC5C2)      /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
-#define TIM_GROUPCH5_OC3REFC    (TIM_CCR5_GC5C3)      /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
-  * @{
-  */
-#define	TIM_TRGO_RESET            ((uint32_t)0x0000)
-#define	TIM_TRGO_ENABLE           (TIM_CR2_MMS_0)
-#define	TIM_TRGO_UPDATE           (TIM_CR2_MMS_1)
-#define	TIM_TRGO_OC1              ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
-#define	TIM_TRGO_OC1REF           (TIM_CR2_MMS_2)
-#define	TIM_TRGO_OC2REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
-#define	TIM_TRGO_OC3REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
-#define	TIM_TRGO_OC4REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2)
-  * @{
-  */
-#define	TIM_TRGO2_RESET                          ((uint32_t)0x00000000)
-#define	TIM_TRGO2_ENABLE                         ((uint32_t)(TIM_CR2_MMS2_0))
-#define	TIM_TRGO2_UPDATE                         ((uint32_t)(TIM_CR2_MMS2_1))
-#define	TIM_TRGO2_OC1                            ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
-#define	TIM_TRGO2_OC1REF                         ((uint32_t)(TIM_CR2_MMS2_2))
-#define	TIM_TRGO2_OC2REF                         ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
-#define	TIM_TRGO2_OC3REF                         ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1))
-#define	TIM_TRGO2_OC4REF                         ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
-#define	TIM_TRGO2_OC5REF                         ((uint32_t)(TIM_CR2_MMS2_3))
-#define	TIM_TRGO2_OC6REF                         ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0))
-#define	TIM_TRGO2_OC4REF_RISINGFALLING           ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1))
-#define	TIM_TRGO2_OC6REF_RISINGFALLING           ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
-#define	TIM_TRGO2_OC4REF_RISING_OC6REF_RISING    ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2))
-#define	TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING   ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
-#define	TIM_TRGO2_OC5REF_RISING_OC6REF_RISING    ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1))
-#define	TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING   ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
-  * @{
-  */
-#define TIM_MASTERSLAVEMODE_ENABLE         ((uint32_t)0x0080)
-#define TIM_MASTERSLAVEMODE_DISABLE        ((uint32_t)0x0000)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Slave_Mode TIM Slave mode
-  * @{
-  */
-#define TIM_SLAVEMODE_DISABLE                ((uint32_t)0x0000)
-#define TIM_SLAVEMODE_RESET                  ((uint32_t)(TIM_SMCR_SMS_2))
-#define TIM_SLAVEMODE_GATED                  ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))
-#define TIM_SLAVEMODE_TRIGGER                ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))
-#define TIM_SLAVEMODE_EXTERNAL1              ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))
-#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER  ((uint32_t)(TIM_SMCR_SMS_3))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
-  * @{
-  */
-#define TIM_OCMODE_TIMING                   ((uint32_t)0x0000)
-#define TIM_OCMODE_ACTIVE                   ((uint32_t)TIM_CCMR1_OC1M_0)
-#define TIM_OCMODE_INACTIVE                 ((uint32_t)TIM_CCMR1_OC1M_1)
-#define TIM_OCMODE_TOGGLE                   ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
-#define TIM_OCMODE_PWM1                     ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
-#define TIM_OCMODE_PWM2                     ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
-#define TIM_OCMODE_FORCED_ACTIVE            ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
-#define TIM_OCMODE_FORCED_INACTIVE          ((uint32_t)TIM_CCMR1_OC1M_2)
-
-#define TIM_OCMODE_RETRIGERRABLE_OPM1      ((uint32_t)TIM_CCMR1_OC1M_3)
-#define TIM_OCMODE_RETRIGERRABLE_OPM2      ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
-#define TIM_OCMODE_COMBINED_PWM1           ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
-#define TIM_OCMODE_COMBINED_PWM2           ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
-#define TIM_OCMODE_ASSYMETRIC_PWM1         ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
-#define TIM_OCMODE_ASSYMETRIC_PWM2         ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
-  * @{
-  */
-#define TIM_TS_ITR0                        ((uint32_t)0x0000)
-#define TIM_TS_ITR1                        ((uint32_t)0x0010)
-#define TIM_TS_ITR2                        ((uint32_t)0x0020)
-#define TIM_TS_ITR3                        ((uint32_t)0x0030)
-#define TIM_TS_TI1F_ED                     ((uint32_t)0x0040)
-#define TIM_TS_TI1FP1                      ((uint32_t)0x0050)
-#define TIM_TS_TI2FP2                      ((uint32_t)0x0060)
-#define TIM_TS_ETRF                        ((uint32_t)0x0070)
-#define TIM_TS_NONE                        ((uint32_t)0xFFFF)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
-  * @{
-  */
-#define TIM_TRIGGERPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx trigger sources */
-#define TIM_TRIGGERPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx trigger sources */
-#define TIM_TRIGGERPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING        /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-#define TIM_TRIGGERPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING       /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-#define TIM_TRIGGERPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE      /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
-  * @{
-  */
-#define TIM_TRIGGERPRESCALER_DIV1             TIM_ETRPRESCALER_DIV1     /*!< No prescaler is used */
-#define TIM_TRIGGERPRESCALER_DIV2             TIM_ETRPRESCALER_DIV2     /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
-#define TIM_TRIGGERPRESCALER_DIV4             TIM_ETRPRESCALER_DIV4     /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
-#define TIM_TRIGGERPRESCALER_DIV8             TIM_ETRPRESCALER_DIV8     /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
-  * @{
-  */
-#define TIM_TI1SELECTION_CH1               ((uint32_t)0x0000)
-#define TIM_TI1SELECTION_XORCOMBINATION    (TIM_CR2_TI1S)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
-  * @{
-  */
-#define TIM_DMABURSTLENGTH_1TRANSFER       (0x00000000)
-#define TIM_DMABURSTLENGTH_2TRANSFERS      (0x00000100)
-#define TIM_DMABURSTLENGTH_3TRANSFERS      (0x00000200)
-#define TIM_DMABURSTLENGTH_4TRANSFERS      (0x00000300)
-#define TIM_DMABURSTLENGTH_5TRANSFERS      (0x00000400)
-#define TIM_DMABURSTLENGTH_6TRANSFERS      (0x00000500)
-#define TIM_DMABURSTLENGTH_7TRANSFERS      (0x00000600)
-#define TIM_DMABURSTLENGTH_8TRANSFERS      (0x00000700)
-#define TIM_DMABURSTLENGTH_9TRANSFERS      (0x00000800)
-#define TIM_DMABURSTLENGTH_10TRANSFERS     (0x00000900)
-#define TIM_DMABURSTLENGTH_11TRANSFERS     (0x00000A00)
-#define TIM_DMABURSTLENGTH_12TRANSFERS     (0x00000B00)
-#define TIM_DMABURSTLENGTH_13TRANSFERS     (0x00000C00)
-#define TIM_DMABURSTLENGTH_14TRANSFERS     (0x00000D00)
-#define TIM_DMABURSTLENGTH_15TRANSFERS     (0x00000E00)
-#define TIM_DMABURSTLENGTH_16TRANSFERS     (0x00000F00)
-#define TIM_DMABURSTLENGTH_17TRANSFERS     (0x00001000)
-#define TIM_DMABURSTLENGTH_18TRANSFERS     (0x00001100)
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Handle_index TIM DMA Handle Index
-  * @{
-  */
-#define TIM_DMA_ID_UPDATE                ((uint16_t) 0x0)       /*!< Index of the DMA handle used for Update DMA requests */
-#define TIM_DMA_ID_CC1                   ((uint16_t) 0x1)       /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
-#define TIM_DMA_ID_CC2                   ((uint16_t) 0x2)       /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
-#define TIM_DMA_ID_CC3                   ((uint16_t) 0x3)       /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
-#define TIM_DMA_ID_CC4                   ((uint16_t) 0x4)       /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
-#define TIM_DMA_ID_COMMUTATION           ((uint16_t) 0x5)       /*!< Index of the DMA handle used for Commutation DMA requests */
-#define TIM_DMA_ID_TRIGGER               ((uint16_t) 0x6)       /*!< Index of the DMA handle used for Trigger DMA requests */
-/**
-  * @}
-  */
-
-/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
-  * @{
-  */
-#define TIM_CCx_ENABLE                   ((uint32_t)0x0001)
-#define TIM_CCx_DISABLE                  ((uint32_t)0x0000)
-#define TIM_CCxN_ENABLE                  ((uint32_t)0x0004)
-#define TIM_CCxN_DISABLE                 ((uint32_t)0x0000)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Break_System TIM Break System
-  * @{
-  */
-#define TIM_BREAK_SYSTEM_ECC                 SYSCFG_CFGR2_ECCL  /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */
-#define TIM_BREAK_SYSTEM_PVD                 SYSCFG_CFGR2_PVDL  /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */
-#define TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR  SYSCFG_CFGR2_SPL   /*!< Enables and locks the SRAM2_PARITY error signal with Break Input of TIM1/8/15/16/17 */
-#define TIM_BREAK_SYSTEM_LOCKUP              SYSCFG_CFGR2_CLL   /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/15/16/17 */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* End of exported constants -------------------------------------------------*/
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup TIM_Exported_Macros TIM Exported Macros
-  * @{
-  */
-
-/** @brief  Reset TIM handle state.
-  * @param  __HANDLE__: TIM handle.
-  * @retval None
-  */
-#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
-
-/**
-  * @brief  Enable the TIM peripheral.
-  * @param  __HANDLE__: TIM handle
-  * @retval None
- */
-#define __HAL_TIM_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
-
-/**
-  * @brief  Enable the TIM main Output.
-  * @param  __HANDLE__: TIM handle
-  * @retval None
-  */
-#define __HAL_TIM_MOE_ENABLE(__HANDLE__)             ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
-
-/**
-  * @brief  Disable the TIM peripheral.
-  * @param  __HANDLE__: TIM handle
-  * @retval None
-  */
-#define __HAL_TIM_DISABLE(__HANDLE__) \
-                        do { \
-                          if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
-                            { \
-                            if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
-                            { \
-                              (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
-                            } \
-                          } \
-                        } while(0)
-
-/**
-  * @brief  Disable the TIM main Output.
-  * @param  __HANDLE__: TIM handle
-  * @retval None
-  * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
-  */
-#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
-                        do { \
-                          if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
-                          { \
-                            if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
-                            { \
-                              (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
-                            } \
-                            } \
-                        } while(0)
-
-/** @brief  Enable the specified TIM interrupt.
-  * @param  __HANDLE__: specifies the TIM Handle.
-  * @param  __INTERRUPT__: specifies the TIM interrupt source to enable.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_IT_UPDATE: Update interrupt
-  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
-  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
-  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
-  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
-  *            @arg TIM_IT_COM:   Commutation interrupt
-  *            @arg TIM_IT_TRIGGER: Trigger interrupt
-  *            @arg TIM_IT_BREAK: Break interrupt
-  * @retval None
-  */
-#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
-
-
-/** @brief  Disable the specified TIM interrupt.
-  * @param  __HANDLE__: specifies the TIM Handle.
-  * @param  __INTERRUPT__: specifies the TIM interrupt source to disable.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_IT_UPDATE: Update interrupt
-  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
-  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
-  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
-  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
-  *            @arg TIM_IT_COM:   Commutation interrupt
-  *            @arg TIM_IT_TRIGGER: Trigger interrupt
-  *            @arg TIM_IT_BREAK: Break interrupt
-  * @retval None
-  */
-#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
-
-/** @brief  Enable the specified DMA request.
-  * @param  __HANDLE__: specifies the TIM Handle.
-  * @param  __DMA__: specifies the TIM DMA request to enable.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_DMA_UPDATE: Update DMA request
-  *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
-  *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
-  *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
-  *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
-  *            @arg TIM_DMA_COM:   Commutation DMA request
-  *            @arg TIM_DMA_TRIGGER: Trigger DMA request
-  *            @arg TIM_DMA_BREAK: Break DMA request
-  * @retval None
-  */
-#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)         ((__HANDLE__)->Instance->DIER |= (__DMA__))
-
-/** @brief  Disable the specified DMA request.
-  * @param  __HANDLE__: specifies the TIM Handle.
-  * @param  __DMA__: specifies the TIM DMA request to disable.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_DMA_UPDATE: Update DMA request
-  *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
-  *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
-  *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
-  *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
-  *            @arg TIM_DMA_COM:   Commutation DMA request
-  *            @arg TIM_DMA_TRIGGER: Trigger DMA request
-  *            @arg TIM_DMA_BREAK: Break DMA request
-  * @retval None
-  */
-#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)        ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
-
-/** @brief  Check whether the specified TIM interrupt flag is set or not.
-  * @param  __HANDLE__: specifies the TIM Handle.
-  * @param  __FLAG__: specifies the TIM interrupt flag to check.
-  *        This parameter can be one of the following values:
-  *            @arg TIM_FLAG_UPDATE: Update interrupt flag
-  *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
-  *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
-  *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
-  *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
-  *            @arg TIM_FLAG_CC5: Compare 5 interrupt flag
-  *            @arg TIM_FLAG_CC6: Compare 5 interrupt flag
-  *            @arg TIM_FLAG_COM:  Commutation interrupt flag
-  *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
-  *            @arg TIM_FLAG_BREAK: Break interrupt flag   
-  *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag                     
-  *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
-  *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
-  *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
-  *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
-  *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
-
-/** @brief  Clear the specified TIM interrupt flag.
-  * @param  __HANDLE__: specifies the TIM Handle.
-  * @param  __FLAG__: specifies the TIM interrupt flag to clear.
-  *        This parameter can be one of the following values:
-  *            @arg TIM_FLAG_UPDATE: Update interrupt flag
-  *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
-  *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
-  *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
-  *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
-  *            @arg TIM_FLAG_CC5: Compare 5 interrupt flag
-  *            @arg TIM_FLAG_CC6: Compare 5 interrupt flag
-  *            @arg TIM_FLAG_COM:  Commutation interrupt flag
-  *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
-  *            @arg TIM_FLAG_BREAK: Break interrupt flag   
-  *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag                     
-  *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
-  *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
-  *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
-  *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
-  *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-
-/**
-  * @brief  Check whether the specified TIM interrupt source is enabled or not.
-  * @param  __HANDLE__: TIM handle
-  * @param  __INTERRUPT__: specifies the TIM interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_IT_UPDATE: Update interrupt
-  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
-  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
-  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
-  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
-  *            @arg TIM_IT_COM:   Commutation interrupt
-  *            @arg TIM_IT_TRIGGER: Trigger interrupt
-  *            @arg TIM_IT_BREAK: Break interrupt
-  * @retval The state of TIM_IT (SET or RESET).
-  */
-#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief Clear the TIM interrupt pending bits.
-  * @param  __HANDLE__: TIM handle
-  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_IT_UPDATE: Update interrupt
-  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
-  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
-  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
-  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
-  *            @arg TIM_IT_COM:   Commutation interrupt
-  *            @arg TIM_IT_TRIGGER: Trigger interrupt
-  *            @arg TIM_IT_BREAK: Break interrupt
-  * @retval None
-  */
-#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
-
-/**
-  * @brief  Indicates whether or not the TIM Counter is used as downcounter.
-  * @param  __HANDLE__: TIM handle.
-  * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
-  * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
-mode.
-  */
-#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
-
-
-/**
-  * @brief  Set the TIM Prescaler on runtime.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __PRESC__: specifies the Prescaler new value.
-  * @retval None
-  */
-#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__)       ((__HANDLE__)->Instance->PSC = (__PRESC__))
-
-/**
-  * @brief  Set the TIM Counter Register value on runtime.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __COUNTER__: specifies the Counter register new value.
-  * @retval None
-  */
-#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__)  ((__HANDLE__)->Instance->CNT = (__COUNTER__))
-
-/**
-  * @brief  Get the TIM Counter Register value on runtime.
-  * @param  __HANDLE__: TIM handle.
-  * @retval None
-  */
-#define __HAL_TIM_GET_COUNTER(__HANDLE__) \
-   ((__HANDLE__)->Instance->CNT)
-
-/**
-  * @brief  Set the TIM Autoreload Register value on runtime without calling another time any Init function.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __AUTORELOAD__: specifies the Counter register new value.
-  * @retval None
-  */
-#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
-                        do{                                                    \
-                              (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
-                              (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
-                          } while(0)
-
-/**
-  * @brief  Get the TIM Autoreload Register value on runtime.
-  * @param  __HANDLE__: TIM handle.
-  * @retval None
-  */
-#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
-   ((__HANDLE__)->Instance->ARR)
-
-/**
-  * @brief  Set the TIM Clock Division value on runtime without calling another time any Init function.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CKD__: specifies the clock division value.
-  *          This parameter can be one of the following value:
-  *            @arg TIM_CLOCKDIVISION_DIV1
-  *            @arg TIM_CLOCKDIVISION_DIV2
-  *            @arg TIM_CLOCKDIVISION_DIV4
-  * @retval None
-  */
-#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
-                        do{                                                    \
-                              (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD);  \
-                              (__HANDLE__)->Instance->CR1 |= (__CKD__);                   \
-                              (__HANDLE__)->Init.ClockDivision = (__CKD__);             \
-                          } while(0)
-
-/**
-  * @brief  Get the TIM Clock Division value on runtime.
-  * @param  __HANDLE__: TIM handle.
-  * @retval None
-  */
-#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__)  \
-   ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
-
-/**
-  * @brief  Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CHANNEL__: TIM Channels to be configured.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  __ICPSC__: specifies the Input Capture4 prescaler new value.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPSC_DIV1: no prescaler
-  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
-  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
-  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
-  * @retval None
-  */
-#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
-                        do{                                                    \
-                              TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
-                              TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
-                          } while(0)
-
-/**
-  * @brief  Get the TIM Input Capture prescaler on runtime.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CHANNEL__: TIM Channels to be configured.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value
-  *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value
-  *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value
-  *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value
-  * @retval None
-  */
-#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)  \
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
-   (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
-
-/**
-  * @brief  Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CHANNEL__: TIM Channels to be configured.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
-  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
-  * @param  __COMPARE__: specifies the Capture Compare register new value.
-  * @retval None
-  */
-#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
- ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
-
-/**
-  * @brief  Get the TIM Capture Compare Register value on runtime.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CHANNEL__: TIM Channel associated with the capture compare register
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: get capture/compare 1 register value
-  *            @arg TIM_CHANNEL_2: get capture/compare 2 register value
-  *            @arg TIM_CHANNEL_3: get capture/compare 3 register value
-  *            @arg TIM_CHANNEL_4: get capture/compare 4 register value
-  *            @arg TIM_CHANNEL_5: get capture/compare 5 register value
-  *            @arg TIM_CHANNEL_6: get capture/compare 6 register value
-  * @retval None
-  */
-#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
- ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
- ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
- ((__HANDLE__)->Instance->CCR6))
-
-/**
-  * @brief  Set the Update Request Source (URS) bit of the TIMx_CR1 register.
-  * @param  __HANDLE__: TIM handle.
-  * @note  When the USR bit of the TIMx_CR1 register is set, only counter 
-  *        overflow/underflow generates an update interrupt or DMA request (if
-  *        enabled)
-  * @retval None
-  */
-#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
-    ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
-
-/**
-  * @brief  Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
-  * @param  __HANDLE__: TIM handle.
-  * @note  When the USR bit of the TIMx_CR1 register is reset, any of the 
-  *        following events generate an update interrupt or DMA request (if 
-  *        enabled):
-  *           _ Counter overflow underflow
-  *           _ Setting the UG bit
-  *           _ Update generation through the slave mode controller
-  * @retval None
-  */
-#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
-      ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
-        
-/**
-  * @brief  Set the TIM Capture x input polarity on runtime.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CHANNEL__: TIM Channels to be configured.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  __POLARITY__: Polarity for TIx source   
-  *            @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
-  *            @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
-  *            @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
-  * @retval None
-  */
-#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)    \
-        do{                                                                     \
-          TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
-          TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
-        }while(0)
-          
-/**
-  * @}
-  */
-/* End of exported macros ----------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup TIM_Private_Constants TIM Private Constants
-  * @{
-  */
-/* The counter of a timer instance is disabled only if all the CCx and CCxN
-   channels have been disabled */
-#define TIM_CCER_CCxE_MASK  ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
-#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
-/**
-  * @}
-  */
-/* End of private constants --------------------------------------------------*/
-  
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup TIM_Private_Macros TIM Private Macros
-  * @{
-  */
-
-#define IS_TIM_CLEARINPUT_SOURCE(__MODE__)  (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)      || \
-                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \
-                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))
-
-#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1)   || \
-                                   ((__BASE__) == TIM_DMABASE_CR2)   || \
-                                   ((__BASE__) == TIM_DMABASE_SMCR)  || \
-                                   ((__BASE__) == TIM_DMABASE_DIER)  || \
-                                   ((__BASE__) == TIM_DMABASE_SR)    || \
-                                   ((__BASE__) == TIM_DMABASE_EGR)   || \
-                                   ((__BASE__) == TIM_DMABASE_CCMR1) || \
-                                   ((__BASE__) == TIM_DMABASE_CCMR2) || \
-                                   ((__BASE__) == TIM_DMABASE_CCER)  || \
-                                   ((__BASE__) == TIM_DMABASE_CNT)   || \
-                                   ((__BASE__) == TIM_DMABASE_PSC)   || \
-                                   ((__BASE__) == TIM_DMABASE_ARR)   || \
-                                   ((__BASE__) == TIM_DMABASE_RCR)   || \
-                                   ((__BASE__) == TIM_DMABASE_CCR1)  || \
-                                   ((__BASE__) == TIM_DMABASE_CCR2)  || \
-                                   ((__BASE__) == TIM_DMABASE_CCR3)  || \
-                                   ((__BASE__) == TIM_DMABASE_CCR4)  || \
-                                   ((__BASE__) == TIM_DMABASE_BDTR)  || \
-                                   ((__BASE__) == TIM_DMABASE_CCMR3) || \
-                                   ((__BASE__) == TIM_DMABASE_CCR5)  || \
-                                   ((__BASE__) == TIM_DMABASE_CCR6)  || \
-                                   ((__BASE__) == TIM_DMABASE_OR1)   || \
-                                   ((__BASE__) == TIM_DMABASE_OR2)   || \
-                                   ((__BASE__) == TIM_DMABASE_OR3))
-
-
-#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00) == 0x00000000) && ((__SOURCE__) != 0x00000000))
-
-
-#define IS_TIM_COUNTER_MODE(__MODE__)      (((__MODE__) == TIM_COUNTERMODE_UP)              || \
-                                            ((__MODE__) == TIM_COUNTERMODE_DOWN)            || \
-                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
-                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
-                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
-
-#define IS_TIM_CLOCKDIVISION_DIV(__DIV__)  (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
-                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
-                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
-
-#define IS_TIM_FAST_STATE(__STATE__)       (((__STATE__) == TIM_OCFAST_DISABLE) || \
-                                            ((__STATE__) == TIM_OCFAST_ENABLE))
-
-#define IS_TIM_OC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
-                                            ((__POLARITY__) == TIM_OCPOLARITY_LOW))
-
-#define IS_TIM_OCN_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
-                                            ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
-
-#define IS_TIM_OCIDLE_STATE(__STATE__)     (((__STATE__) == TIM_OCIDLESTATE_SET) || \
-                                            ((__STATE__) == TIM_OCIDLESTATE_RESET))
-
-#define IS_TIM_OCNIDLE_STATE(__STATE__)    (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
-                                            ((__STATE__) == TIM_OCNIDLESTATE_RESET))
-
-#define IS_TIM_IC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \
-                                            ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \
-                                            ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
-
-#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
-                                            ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
-                                            ((__SELECTION__) == TIM_ICSELECTION_TRC))
-
-#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
-                                            ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
-                                            ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
-                                            ((__PRESCALER__) == TIM_ICPSC_DIV8))
-
-#define IS_TIM_OPM_MODE(__MODE__)          (((__MODE__) == TIM_OPMODE_SINGLE) || \
-                                            ((__MODE__) == TIM_OPMODE_REPETITIVE))
-
-#define IS_TIM_ENCODER_MODE(__MODE__)      (((__MODE__) == TIM_ENCODERMODE_TI1) || \
-                                            ((__MODE__) == TIM_ENCODERMODE_TI2) || \
-                                            ((__MODE__) == TIM_ENCODERMODE_TI12))
-
-#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FF) == 0x00000000) && ((__SOURCE__) != 0x00000000))
-
-#define IS_TIM_CHANNELS(__CHANNEL__)       (((__CHANNEL__) == TIM_CHANNEL_1) || \
-                                            ((__CHANNEL__) == TIM_CHANNEL_2) || \
-                                            ((__CHANNEL__) == TIM_CHANNEL_3) || \
-                                            ((__CHANNEL__) == TIM_CHANNEL_4) || \
-                                            ((__CHANNEL__) == TIM_CHANNEL_5) || \
-                                            ((__CHANNEL__) == TIM_CHANNEL_6) || \
-                                            ((__CHANNEL__) == TIM_CHANNEL_ALL))
-
-#define IS_TIM_OPM_CHANNELS(__CHANNEL__)   (((__CHANNEL__) == TIM_CHANNEL_1) || \
-                                            ((__CHANNEL__) == TIM_CHANNEL_2))
-
-#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
-                                                    ((__CHANNEL__) == TIM_CHANNEL_2) || \
-                                                    ((__CHANNEL__) == TIM_CHANNEL_3))
-
-#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)     || \
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
-
-#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED)    || \
-                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
-                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING)      || \
-                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING)     || \
-                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
-
-#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
-                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
-                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
-                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
-
-#define IS_TIM_CLOCKFILTER(ICFILTER)      ((ICFILTER) <= 0xF)
-
-#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
-                                                  ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
-
-#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
-                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
-                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
-                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
-
-#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
-
-
-#define IS_TIM_OSSR_STATE(__STATE__)       (((__STATE__) == TIM_OSSR_ENABLE) || \
-                                            ((__STATE__) == TIM_OSSR_DISABLE))
-
-#define IS_TIM_OSSI_STATE(__STATE__)       (((__STATE__) == TIM_OSSI_ENABLE) || \
-                                            ((__STATE__) == TIM_OSSI_DISABLE))
-
-#define IS_TIM_LOCK_LEVEL(__LEVEL__)       (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
-                                            ((__LEVEL__) == TIM_LOCKLEVEL_1)   || \
-                                            ((__LEVEL__) == TIM_LOCKLEVEL_2)   || \
-                                            ((__LEVEL__) == TIM_LOCKLEVEL_3))
-
-#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xF)
-
-
-#define IS_TIM_BREAK_STATE(__STATE__)      (((__STATE__) == TIM_BREAK_ENABLE) || \
-                                            ((__STATE__) == TIM_BREAK_DISABLE))
-
-#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
-                                             ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
-
-#define IS_TIM_BREAK2_STATE(__STATE__)     (((__STATE__) == TIM_BREAK2_ENABLE) || \
-                                            ((__STATE__) == TIM_BREAK2_DISABLE))
-
-#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
-                                              ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
-
-#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
-                                                  ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
-
-#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFF) == 0x00000000))
-
-#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET)  || \
-                                        ((__SOURCE__) == TIM_TRGO_ENABLE) || \
-                                        ((__SOURCE__) == TIM_TRGO_UPDATE) || \
-                                        ((__SOURCE__) == TIM_TRGO_OC1)    || \
-                                        ((__SOURCE__) == TIM_TRGO_OC1REF) || \
-                                        ((__SOURCE__) == TIM_TRGO_OC2REF) || \
-                                        ((__SOURCE__) == TIM_TRGO_OC3REF) || \
-                                        ((__SOURCE__) == TIM_TRGO_OC4REF))
-
-#define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET)                        || \
-                                         ((__SOURCE__) == TIM_TRGO2_ENABLE)                       || \
-                                         ((__SOURCE__) == TIM_TRGO2_UPDATE)                       || \
-                                         ((__SOURCE__) == TIM_TRGO2_OC1)                          || \
-                                         ((__SOURCE__) == TIM_TRGO2_OC1REF)                       || \
-                                         ((__SOURCE__) == TIM_TRGO2_OC2REF)                       || \
-                                         ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
-                                         ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
-                                         ((__SOURCE__) == TIM_TRGO2_OC4REF)                       || \
-                                         ((__SOURCE__) == TIM_TRGO2_OC5REF)                       || \
-                                         ((__SOURCE__) == TIM_TRGO2_OC6REF)                       || \
-                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING)         || \
-                                         ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING)         || \
-                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING)  || \
-                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
-                                         ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING)  || \
-                                         ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
-
-#define IS_TIM_MSM_STATE(__STATE__)      (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
-                                          ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
-
-#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE)   || \
-                                     ((__MODE__) == TIM_SLAVEMODE_RESET)     || \
-                                     ((__MODE__) == TIM_SLAVEMODE_GATED)     || \
-                                     ((__MODE__) == TIM_SLAVEMODE_TRIGGER)   || \
-                                     ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \
-                                     ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
-
-#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1)               || \
-	                                 ((__MODE__) == TIM_OCMODE_PWM2)               || \
-                                   ((__MODE__) == TIM_OCMODE_COMBINED_PWM1)      || \
-                                   ((__MODE__) == TIM_OCMODE_COMBINED_PWM2)      || \
-                                   ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1)    || \
-                                   ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))
-
-#define IS_TIM_OC_MODE(__MODE__)  (((__MODE__) == TIM_OCMODE_TIMING)             || \
-                                   ((__MODE__) == TIM_OCMODE_ACTIVE)             || \
-                                   ((__MODE__) == TIM_OCMODE_INACTIVE)           || \
-                                   ((__MODE__) == TIM_OCMODE_TOGGLE)             || \
-                                   ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE)      || \
-                                   ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)    || \
-                                   ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
-                                   ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))
-
-#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
-                                                 ((__SELECTION__) == TIM_TS_ITR1) || \
-                                                 ((__SELECTION__) == TIM_TS_ITR2) || \
-                                                 ((__SELECTION__) == TIM_TS_ITR3) || \
-                                                 ((__SELECTION__) == TIM_TS_TI1F_ED) || \
-                                                 ((__SELECTION__) == TIM_TS_TI1FP1) || \
-                                                 ((__SELECTION__) == TIM_TS_TI2FP2) || \
-                                                 ((__SELECTION__) == TIM_TS_ETRF))
-
-#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
-                                                               ((__SELECTION__) == TIM_TS_ITR1) || \
-                                                               ((__SELECTION__) == TIM_TS_ITR2) || \
-                                                               ((__SELECTION__) == TIM_TS_ITR3) || \
-                                                               ((__SELECTION__) == TIM_TS_NONE))
-
-
-#define IS_TIM_TRIGGERPOLARITY(__POLARITY__)   (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
-                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
-                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING     ) || \
-                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING    ) || \
-                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))
-
-#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
-                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
-                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
-                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
-
-#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
-
-#define IS_TIM_TI1SELECTION(__TI1SELECTION__)  (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
-                                                ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
-
-#define IS_TIM_DMA_LENGTH(__LENGTH__)      (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
-
-#define IS_TIM_IC_FILTER(__ICFILTER__)   ((__ICFILTER__) <= 0xF)
-
-#define IS_TIM_DEADTIME(__DEADTIME__)    ((__DEADTIME__) <= 0xFF)
-
-#define IS_TIM_BREAK_SYSTEM(__CONFIG__)    (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC)                 || \
-                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD)                 || \
-                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR)  || \
-                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
-
-#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
- ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
-
-#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
- ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
-
-#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\
- ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12))))
-
-#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
- ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
-
-/**
-  * @}
-  */
-/* End of private macros -----------------------------------------------------*/
-
-/* Include TIM HAL Extended module */
-#include "stm32l4xx_hal_tim_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIM_Exported_Functions TIM Exported Functions
-  * @{
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group1 Time Base functions
- *  @brief    Time Base functions
- * @{
- */
-/* Time Base functions ********************************************************/
-HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group2 Time Output Compare functions
- *  @brief    Time Output Compare functions
- * @{
- */
-/* Timer Output Compare functions *********************************************/
-HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group3 Time PWM functions
- *  @brief    Time PWM functions
- * @{
- */
-/* Timer PWM functions ********************************************************/
-HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group4 Time Input Capture functions
- *  @brief    Time Input Capture functions
- * @{
- */
-/* Timer Input Capture functions **********************************************/
-HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group5 Time One Pulse functions
- *  @brief    Time One Pulse functions
- * @{
- */
-/* Timer One Pulse functions **************************************************/
-HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
-HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group6 Time Encoder functions
- *  @brief    Time Encoder functions
- * @{
- */
-/* Timer Encoder functions ****************************************************/
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef* sConfig);
-HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
- /* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
- *  @brief    IRQ handler management
-  * @{
-  */
-/* Interrupt Handler functions  ***********************************************/
-void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
- *  @brief   	Peripheral Control functions
-  * @{
-  */
-/* Control functions  *********************************************************/
-HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel,  uint32_t InputChannel);
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
-HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
-                                              uint32_t  *BurstBuffer, uint32_t  BurstLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
-                                              uint32_t  *BurstBuffer, uint32_t  BurstLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
-HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
-uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
- *  @brief    TIM Callbacks functions
-  * @{
-  */
-/* Callback in non blocking modes (Interrupt and DMA) *************************/
-void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
- *  @brief   Peripheral State functions
- * @{
- */
-/* Peripheral State functions  ************************************************/
-HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* End of exported functions -------------------------------------------------*/
-
-/* Private functions----------------------------------------------------------*/
-/** @defgroup TIM_Private_Functions TIM Private Functions
-* @{
-*/
-void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
-void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
-void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
-                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
-
-void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
-void TIM_DMAError(DMA_HandleTypeDef *hdma);
-void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
-void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
-/**
-* @}
-*/ 
-/* End of private functions --------------------------------------------------*/
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L4xx_HAL_TIM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/inc/stm32l4xx_hal_tim_ex.h b/stmhal/hal/l4/inc/stm32l4xx_hal_tim_ex.h
deleted file mode 100644
index d4fcfdfcb8..0000000000
--- a/stmhal/hal/l4/inc/stm32l4xx_hal_tim_ex.h
+++ /dev/null
@@ -1,396 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_tim_ex.h
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   Header file of TIM HAL Extended module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L4xx_HAL_TIM_EX_H
-#define __STM32L4xx_HAL_TIM_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup TIMEx
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
-  * @{
-  */
-
-/** 
-  * @brief  TIM Hall sensor Configuration Structure definition  
-  */
-
-typedef struct
-{
-                                  
-  uint32_t IC1Polarity;         /*!< Specifies the active edge of the input signal.
-                                     This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-                                                                   
-  uint32_t IC1Prescaler;        /*!< Specifies the Input Capture Prescaler.
-                                     This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-                                  
-  uint32_t IC1Filter;           /*!< Specifies the input capture filter.
-                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */  
-
-  uint32_t Commutation_Delay;   /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 
-                                     This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */                              
-} TIM_HallSensor_InitTypeDef;
-
-/** 
-  * @brief  TIM Break/Break2 input configuration   
-  */
-typedef struct {
-  uint32_t Source;         /*!< Specifies the source of the timer break input.
-                                This parameter can be a value of @ref TIMEx_Break_Input_Source */
-  uint32_t Enable;         /*!< Specifies whether or not the break input source is enabled.
-                                This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */
-  uint32_t Polarity;       /*!< Specifies the break input source polarity.
-                                This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity
-                                Not relevant when analog watchdog output of the DFSDM used as break input source */
-} TIMEx_BreakInputConfigTypeDef;
-
-/**
-  * @}
-  */
-/* End of exported types -----------------------------------------------------*/ 
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
-  * @{
-  */
-
-/** @defgroup TIMEx_Remap TIM  Extended Remapping
-  * @{
-  */
-#define TIM_TIM1_ETR_ADC1_NONE      ((uint32_t)(0x00000000))                              /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
-#define TIM_TIM1_ETR_ADC1_AWD1      (TIM1_OR1_ETR_ADC1_RMP_0)                             /* !< TIM1_ETR is connected to ADC1 AWD1 */
-#define TIM_TIM1_ETR_ADC1_AWD2      (TIM1_OR1_ETR_ADC1_RMP_1)                             /* !< TIM1_ETR is connected to ADC1 AWD2 */
-#define TIM_TIM1_ETR_ADC1_AWD3      (TIM1_OR1_ETR_ADC1_RMP_1 | TIM1_OR1_ETR_ADC1_RMP_0)   /* !< TIM1_ETR is connected to ADC1 AWD3 */
-#define TIM_TIM1_ETR_ADC3_NONE      ((uint32_t)(0x00000000))                              /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
-#define TIM_TIM1_ETR_ADC3_AWD1      (TIM1_OR1_ETR_ADC3_RMP_0)                             /* !< TIM1_ETR is connected to ADC3 AWD1 */
-#define TIM_TIM1_ETR_ADC3_AWD2      (TIM1_OR1_ETR_ADC3_RMP_1)                             /* !< TIM1_ETR is connected to ADC3 AWD2 */
-#define TIM_TIM1_ETR_ADC3_AWD3      (TIM1_OR1_ETR_ADC3_RMP_1 | TIM1_OR1_ETR_ADC3_RMP_0)   /* !< TIM1_ETR is connected to ADC3 AWD3 */
-#define TIM_TIM1_TI1_GPIO           ((uint32_t)(0x00000000))                              /* !< TIM1 TI1 is connected to GPIO */
-#define TIM_TIM1_TI1_COMP1          (TIM1_OR1_TI1_RMP)                                    /* !< TIM1 TI1 is connected to COMP1 */
-#define TIM_TIM1_ETR_COMP1          (TIM1_OR2_ETRSEL_0)                                   /* !< TIM1_ETR is connected to COMP1 output */
-#define TIM_TIM1_ETR_COMP2          (TIM1_OR2_ETRSEL_1)                                   /* !< TIM1_ETR is connected to COMP2 output */
-#define TIM_TIM2_ITR1_TIM8_TRGO     ((uint32_t)(0x00000000))                              /* !< TIM2_ITR1 is connected to TIM8_TRGO */
-#define TIM_TIM2_ITR1_OTG_FS_SOF    (TIM2_OR1_ITR1_RMP)                                   /* !< TIM2_ITR1 is connected to OTG_FS SOF */
-#define TIM_TIM2_ETR_GPIO           ((uint32_t)(0x00000000))                              /* !< TIM2_ETR is connected to GPIO */
-#define TIM_TIM2_ETR_LSE            (TIM2_OR1_ETR1_RMP)                                   /* !< TIM2_ETR is connected to LSE */
-#define TIM_TIM2_ETR_COMP1          (TIM2_OR2_ETRSEL_0)                                   /* !< TIM2_ETR is connected to COMP1 output */
-#define TIM_TIM2_ETR_COMP2          (TIM2_OR2_ETRSEL_1)                                   /* !< TIM2_ETR is connected to COMP2 output */
-#define TIM_TIM2_TI4_GPIO           ((uint32_t)(0x00000000))                              /* !< TIM2 TI4 is connected to GPIO */
-#define TIM_TIM2_TI4_COMP1          (TIM2_OR1_TI4_RMP_0)                                  /* !< TIM2 TI4 is connected to COMP1 output */
-#define TIM_TIM2_TI4_COMP2          (TIM2_OR1_TI4_RMP_1)                                  /* !< TIM2 TI4 is connected to COMP2 output */
-#define TIM_TIM2_TI4_COMP1_COMP2    (TIM2_OR1_TI4_RMP_1| TIM2_OR1_TI4_RMP_0)              /* !< TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output2 */
-#define TIM_TIM3_TI1_GPIO           ((uint32_t)(0x00000000))                              /* !< TIM3 TI1 is connected to GPIO */
-#define TIM_TIM3_TI1_COMP1          (TIM3_OR1_TI1_RMP_0)                                  /* !< TIM3 TI1 is connected to COMP1 output */
-#define TIM_TIM3_TI1_COMP2          (TIM3_OR1_TI1_RMP_1)                                  /* !< TIM3 TI1 is connected to COMP2 output */
-#define TIM_TIM3_TI1_COMP1_COMP2    (TIM3_OR1_TI1_RMP_1 | TIM3_OR1_TI1_RMP_0)             /* !< TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output2 */
-#define TIM_TIM3_ETR_GPIO           ((uint32_t)(0x00000000))                              /* !< TIM3_ETR is connected to GPIO */
-#define TIM_TIM3_ETR_COMP1          (TIM3_OR2_ETRSEL_0)                                   /* !< TIM3_ETR is connected to COMP1 output */
-#define TIM_TIM8_ETR_ADC2_NONE      ((uint32_t)(0x00000000))                              /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/
-#define TIM_TIM8_ETR_ADC2_AWD1      (TIM8_OR1_ETR_ADC2_RMP_0)                             /* !< TIM8_ETR is connected to ADC2 AWD1 */
-#define TIM_TIM8_ETR_ADC2_AWD2      (TIM8_OR1_ETR_ADC2_RMP_1)                             /* !< TIM8_ETR is connected to ADC2 AWD2 */
-#define TIM_TIM8_ETR_ADC2_AWD3      (TIM8_OR1_ETR_ADC2_RMP_1 | TIM8_OR1_ETR_ADC2_RMP_0)   /* !< TIM8_ETR is connected to ADC2 AWD3 */
-#define TIM_TIM8_ETR_ADC3_NONE      ((uint32_t)(0x00000000))                              /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/
-#define TIM_TIM8_ETR_ADC3_AWD1      (TIM8_OR1_ETR_ADC3_RMP_0)                             /* !< TIM8_ETR is connected to ADC3 AWD1 */
-#define TIM_TIM8_ETR_ADC3_AWD2      (TIM8_OR1_ETR_ADC3_RMP_1)                             /* !< TIM8_ETR is connected to ADC3 AWD2 */
-#define TIM_TIM8_ETR_ADC3_AWD3      (TIM8_OR1_ETR_ADC3_RMP_1 | TIM8_OR1_ETR_ADC3_RMP_0)   /* !< TIM8_ETR is connected to ADC3 AWD3 */
-#define TIM_TIM8_TI1_GPIO           ((uint32_t)(0x00000000))                              /* !< TIM8 TI1 is connected to GPIO */
-#define TIM_TIM8_TI1_COMP2          (TIM8_OR1_TI1_RMP)                                    /* !< TIM8 TI1 is connected to COMP1 */
-#define TIM_TIM8_ETR_COMP1          (TIM8_OR2_ETRSEL_0)                                   /* !< TIM8_ETR is connected to COMP1 output */
-#define TIM_TIM8_ETR_COMP2          (TIM8_OR2_ETRSEL_1)                                   /* !< TIM8_ETR is connected to COMP2 output */
-#define TIM_TIM15_TI1_GPIO          ((uint32_t)(0x00000000))                              /* !< TIM15 TI1 is connected to GPIO */
-#define TIM_TIM15_TI1_LSE           (TIM15_OR1_TI1_RMP)                                   /* !< TIM15 TI1 is connected to LSE */
-#define TIM_TIM15_ENCODERMODE_NONE  ((uint32_t)(0x00000000))                              /* !< No redirection */
-#define TIM_TIM15_ENCODERMODE_TIM2  (TIM15_OR1_ENCODER_MODE_0)                            /* !< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
-#define TIM_TIM15_ENCODERMODE_TIM3  (TIM15_OR1_ENCODER_MODE_1)                            /* !< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
-#define TIM_TIM15_ENCODERMODE_TIM4  (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_ENCODER_MODE_0) /* !< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
-#define TIM_TIM16_TI1_GPIO          ((uint32_t)(0x00000000))                              /* !< TIM16 TI1 is connected to GPIO */
-#define TIM_TIM16_TI1_LSI           (TIM16_OR1_TI1_RMP_0)                                 /* !< TIM16 TI1 is connected to LSI */
-#define TIM_TIM16_TI1_LSE           (TIM16_OR1_TI1_RMP_1)                                 /* !< TIM16 TI1 is connected to LSE */
-#define TIM_TIM16_TI1_RTC           (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_TI1_RMP_0)           /* !< TIM16 TI1 is connected to RTC wakeup interrupt */
-#define TIM_TIM17_TI1_GPIO          ((uint32_t)(0x00000000))                              /* !< TIM17 TI1 is connected to GPIO */
-#define TIM_TIM17_TI1_MSI           (TIM17_OR1_TI1_RMP_0)                                 /* !< TIM17 TI1 is connected to MSI */
-#define TIM_TIM17_TI1_HSE_32        (TIM17_OR1_TI1_RMP_1)                                 /* !< TIM17 TI1 is connected to HSE div 32 */
-#define TIM_TIM17_TI1_MCO           (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_TI1_RMP_0)           /* !< TIM17 TI1 is connected to MCO */
-/**
-  * @}
-  */ 
-
-/** @defgroup TIMEx_Break_Input TIM  Extended Break input
-  * @{
-  */
-#define TIM_BREAKINPUT_BRK     ((uint32_t)(0x00000001)) /* !< Timer break input  */
-#define TIM_BREAKINPUT_BRK2    ((uint32_t)(0x00000002)) /* !< Timer break2 input */
-/**
-  * @}
-  */ 
-
-/** @defgroup TIMEx_Break_Input_Source TIM  Extended Break input source
-  * @{
-  */
-#define TIM_BREAKINPUTSOURCE_BKIN     ((uint32_t)(0x00000001)) /* !< An external source (GPIO) is connected to the BKIN pin  */
-#define TIM_BREAKINPUTSOURCE_COMP1    ((uint32_t)(0x00000002)) /* !< The COMP1 output is connected to the break input */
-#define TIM_BREAKINPUTSOURCE_COMP2    ((uint32_t)(0x00000004)) /* !< The COMP2 output is connected to the break input */
-#define TIM_BREAKINPUTSOURCE_DFSDM    ((uint32_t)(0x00000008)) /* !< The analog watchdog output of the DFSDM peripheral is connected to the break input */
-/**
-  * @}
-  */ 
-
-/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling
-  * @{
-  */
-#define TIM_BREAKINPUTSOURCE_DISABLE     ((uint32_t)(0x00000000)) /* !< Break input source is disabled */
-#define TIM_BREAKINPUTSOURCE_ENABLE      ((uint32_t)(0x00000001)) /* !< Break input source is enabled */
-/**
-  * @}
-  */ 
-
-/** @defgroup TIMEx_Break_Input_Source_Polarity TIM  Extended Break input polarity
-  * @{
-  */
-#define TIM_BREAKINPUTSOURCE_POLARITY_LOW     ((uint32_t)(0x00000001)) /* !< Break input source is active low */
-#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH    ((uint32_t)(0x00000000)) /* !< Break input source is active_high */
-/**
-  * @}
-  */ 
-   
-/**
-  * @}
-  */ 
-/* End of exported constants -------------------------------------------------*/
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
-  * @{
-  */  
-
-/**
-  * @}
-  */ 
-/* End of exported macro -----------------------------------------------------*/
-
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
-  * @{
-  */  
-#define IS_TIM_REMAP(__REMAP__)    (((__REMAP__) <= (uint32_t)0x0001C01F))
-
-#define IS_TIM_BREAKINPUT(__BREAKINPUT__)  (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK)  || \
-                                            ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
-
-#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__)  (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)  || \
-                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
-                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
-                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM))
-
-#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__)  (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE)  || \
-                                                   ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
-
-#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW)  || \
-                                                         ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
-/**
-  * @}
-  */ 
-/* End of private macro ------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
-  * @{
-  */
-
-/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions 
- *  @brief    Timer Hall Sensor functions
- * @{
- */
-/*  Timer Hall Sensor functions  **********************************************/
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
-
-void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
-
- /* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
-/**
-  * @}
-  */
-
-/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
- *  @brief   Timer Complementary Output Compare functions
- * @{
- */
-/*  Timer Complementary Output Compare functions  *****************************/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
-  * @}
-  */
-
-/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
- *  @brief    Timer Complementary PWM functions
- * @{
- */
-/*  Timer Complementary PWM functions  ****************************************/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
-  * @}
-  */
-
-/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
- *  @brief    Timer Complementary One Pulse functions
- * @{
- */
-/*  Timer Complementary One Pulse functions  **********************************/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-/**
-  * @}
-  */
-
-/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
- *  @brief    Peripheral Control functions
- * @{
- */
-/* Extended Control functions  ************************************************/
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig);
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
-HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
-HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
-
-/**
-  * @}
-  */
-
-/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions 
-  * @brief    Extended Callbacks functions
-  * @{
-  */
-/* Extended Callback **********************************************************/
-void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim);
-void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
-/**
-  * @}
-  */
-
-/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions 
-  * @brief    Extended Peripheral State functions
-  * @{
-  */
-/* Extended Peripheral State functions  ***************************************/
-HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-/* End of exported functions -------------------------------------------------*/
-
-/* Private functions----------------------------------------------------------*/
-/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
-* @{
-*/
-void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
-/**
-* @}
-*/ 
-/* End of private functions --------------------------------------------------*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32L4xx_HAL_TIM_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/inc/stm32l4xx_hal_uart.h b/stmhal/hal/l4/inc/stm32l4xx_hal_uart.h
deleted file mode 100644
index 52ca6406bc..0000000000
--- a/stmhal/hal/l4/inc/stm32l4xx_hal_uart.h
+++ /dev/null
@@ -1,1382 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_uart.h
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   Header file of UART HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L4xx_HAL_UART_H
-#define __STM32L4xx_HAL_UART_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup UART
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup UART_Exported_Types UART Exported Types
-  * @{
-  */
-
-/**
-  * @brief UART Init Structure definition
-  */
-typedef struct
-{
-  uint32_t BaudRate;                  /*!< This member configures the UART communication baud rate.
-                                           The baud rate register is computed using the following formula:
-                                           - If oversampling is 16 or in LIN mode,
-                                              Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate)))
-                                           - If oversampling is 8,
-                                           - -  Baud Rate Register[15:4] = ((2 * PCLKx) / ((huart->Init.BaudRate)))[15:4]
-                                           - -  Baud Rate Register[3] =  0
-                                           - -  Baud Rate Register[2:0] =  (((2 * PCLKx) / ((huart->Init.BaudRate)))[3:0]) >> 1      */
-
-  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
-                                           This parameter can be a value of @ref UARTEx_Word_Length. */
-
-  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
-                                           This parameter can be a value of @ref UART_Stop_Bits. */
-
-  uint32_t Parity;                    /*!< Specifies the parity mode.
-                                           This parameter can be a value of @ref UART_Parity
-                                           @note When parity is enabled, the computed parity is inserted
-                                                 at the MSB position of the transmitted data (9th bit when
-                                                 the word length is set to 9 data bits; 8th bit when the
-                                                 word length is set to 8 data bits). */
-
-  uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
-                                           This parameter can be a value of @ref UART_Mode. */
-
-  uint32_t HwFlowCtl;                 /*!< Specifies whether the hardware flow control mode is enabled
-                                           or disabled.
-                                           This parameter can be a value of @ref UART_Hardware_Flow_Control. */
-
-  uint32_t OverSampling;              /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8).
-                                           This parameter can be a value of @ref UART_Over_Sampling. */
-
-  uint32_t OneBitSampling;            /*!< Specifies whether a single sample or three samples' majority vote is selected.
-                                           Selecting the single sample method increases the receiver tolerance to clock
-                                           deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */
-}UART_InitTypeDef;
-
-/**
-  * @brief  UART Advanced Features initalization structure definition
-  */
-typedef struct
-{
-  uint32_t AdvFeatureInit;        /*!< Specifies which advanced UART features is initialized. Several
-                                       Advanced Features may be initialized at the same time .
-                                       This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type. */
-
-  uint32_t TxPinLevelInvert;      /*!< Specifies whether the TX pin active level is inverted.
-                                       This parameter can be a value of @ref UART_Tx_Inv.  */
-
-  uint32_t RxPinLevelInvert;      /*!< Specifies whether the RX pin active level is inverted.
-                                       This parameter can be a value of @ref UART_Rx_Inv.  */
-
-  uint32_t DataInvert;            /*!< Specifies whether data are inverted (positive/direct logic
-                                       vs negative/inverted logic).
-                                       This parameter can be a value of @ref UART_Data_Inv. */
-
-  uint32_t Swap;                  /*!< Specifies whether TX and RX pins are swapped.
-                                       This parameter can be a value of @ref UART_Rx_Tx_Swap. */
-
-  uint32_t OverrunDisable;        /*!< Specifies whether the reception overrun detection is disabled.
-                                       This parameter can be a value of @ref UART_Overrun_Disable. */
-
-  uint32_t DMADisableonRxError;   /*!< Specifies whether the DMA is disabled in case of reception error.
-                                       This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */
-
-  uint32_t AutoBaudRateEnable;    /*!< Specifies whether auto Baud rate detection is enabled.
-                                       This parameter can be a value of @ref UART_AutoBaudRate_Enable */
-
-  uint32_t AutoBaudRateMode;      /*!< If auto Baud rate detection is enabled, specifies how the rate
-                                       detection is carried out.
-                                       This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */
-
-  uint32_t MSBFirst;              /*!< Specifies whether MSB is sent first on UART line.
-                                       This parameter can be a value of @ref UART_MSB_First. */
-} UART_AdvFeatureInitTypeDef;
-
-
-
-/**
-  * @brief HAL UART State structures definition
-  */
-typedef enum
-{
-  HAL_UART_STATE_RESET             = 0x00,    /*!< Peripheral is not initialized                      */
-  HAL_UART_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use           */
-  HAL_UART_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing                     */
-  HAL_UART_STATE_BUSY_TX           = 0x12,    /*!< Data Transmission process is ongoing               */
-  HAL_UART_STATE_BUSY_RX           = 0x22,    /*!< Data Reception process is ongoing                  */
-  HAL_UART_STATE_BUSY_TX_RX        = 0x32,    /*!< Data Transmission and Reception process is ongoing */
-  HAL_UART_STATE_TIMEOUT           = 0x03,    /*!< Timeout state                                      */
-  HAL_UART_STATE_ERROR             = 0x04     /*!< Error                                              */
-}HAL_UART_StateTypeDef;
-
-/**
-  * @brief  HAL UART Error Code structure definition
-  */
-typedef enum
-{
-  HAL_UART_ERROR_NONE      = 0x00,    /*!< No error            */
-  HAL_UART_ERROR_PE        = 0x01,    /*!< Parity error        */
-  HAL_UART_ERROR_NE        = 0x02,    /*!< Noise error         */
-  HAL_UART_ERROR_FE        = 0x04,    /*!< frame error         */
-  HAL_UART_ERROR_ORE       = 0x08,    /*!< Overrun error       */
-  HAL_UART_ERROR_DMA       = 0x10     /*!< DMA transfer error  */
-}HAL_UART_ErrorTypeDef;
-
-/**
-  * @brief UART clock sources definition
-  */
-typedef enum
-{
-  UART_CLOCKSOURCE_PCLK1      = 0x00,    /*!< PCLK1 clock source  */
-  UART_CLOCKSOURCE_PCLK2      = 0x01,    /*!< PCLK2 clock source  */
-  UART_CLOCKSOURCE_HSI        = 0x02,    /*!< HSI clock source    */
-  UART_CLOCKSOURCE_SYSCLK     = 0x04,    /*!< SYSCLK clock source */
-  UART_CLOCKSOURCE_LSE        = 0x08,    /*!< LSE clock source       */
-  UART_CLOCKSOURCE_UNDEFINED  = 0x10     /*!< Undefined clock source */
-}UART_ClockSourceTypeDef;
-
-/**
-  * @brief  UART handle Structure definition
-  */
-typedef struct
-{
-  USART_TypeDef            *Instance;        /*!< UART registers base address        */
-
-  UART_InitTypeDef         Init;             /*!< UART communication parameters      */
-
-  UART_AdvFeatureInitTypeDef AdvancedInit;   /*!< UART Advanced Features initialization parameters */
-
-  uint8_t                  *pTxBuffPtr;      /*!< Pointer to UART Tx transfer Buffer */
-
-  uint16_t                 TxXferSize;       /*!< UART Tx Transfer size              */
-
-  uint16_t                 TxXferCount;      /*!< UART Tx Transfer Counter           */
-
-  uint8_t                  *pRxBuffPtr;      /*!< Pointer to UART Rx transfer Buffer */
-
-  uint16_t                 RxXferSize;       /*!< UART Rx Transfer size              */
-
-  uint16_t                 RxXferCount;      /*!< UART Rx Transfer Counter           */
-
-  uint16_t                 Mask;             /*!< UART Rx RDR register mask          */
-
-  DMA_HandleTypeDef        *hdmatx;          /*!< UART Tx DMA Handle parameters      */
-
-  DMA_HandleTypeDef        *hdmarx;          /*!< UART Rx DMA Handle parameters      */
-
-  HAL_LockTypeDef           Lock;            /*!< Locking object                     */
-
-  __IO HAL_UART_StateTypeDef    State;       /*!< UART communication state           */
-
-  __IO uint32_t             ErrorCode;       /*!< UART Error code                    */
-
-}UART_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup UART_Exported_Constants UART Exported Constants
-  * @{
-  */
-
-/** @defgroup UART_Stop_Bits   UART Number of Stop Bits
-  * @{
-  */
-#define UART_STOPBITS_0_5                    USART_CR2_STOP_0                     /*!< UART frame with 0.5 stop bit  */
-#define UART_STOPBITS_1                     ((uint32_t)0x00000000)                /*!< UART frame with 1 stop bit    */
-#define UART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */
-#define UART_STOPBITS_2                      USART_CR2_STOP_1                     /*!< UART frame with 2 stop bits   */
-/**
-  * @}
-  */
-
-/** @defgroup UART_Parity  UART Parity
-  * @{
-  */
-#define UART_PARITY_NONE                    ((uint32_t)0x00000000)                         /*!< No parity   */
-#define UART_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)                      /*!< Even parity */
-#define UART_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))     /*!< Odd parity  */
-/**
-  * @}
-  */
-
-/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
-  * @{
-  */
-#define UART_HWCONTROL_NONE                  ((uint32_t)0x00000000)                           /*!< No hardware control       */
-#define UART_HWCONTROL_RTS                   ((uint32_t)USART_CR3_RTSE)                       /*!< Request To Send           */
-#define UART_HWCONTROL_CTS                   ((uint32_t)USART_CR3_CTSE)                       /*!< Clear To Send             */
-#define UART_HWCONTROL_RTS_CTS               ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))    /*!< Request and Clear To Send */
-/**
-  * @}
-  */
-
-/** @defgroup UART_Mode UART Transfer Mode
-  * @{
-  */
-#define UART_MODE_RX                        ((uint32_t)USART_CR1_RE)                    /*!< RX mode        */ 
-#define UART_MODE_TX                        ((uint32_t)USART_CR1_TE)                    /*!< TX mode        */ 
-#define UART_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))    /*!< RX and TX mode */ 
-/**
-  * @}
-  */
-
- /** @defgroup UART_State  UART State
-  * @{
-  */
-#define UART_STATE_DISABLE                  ((uint32_t)0x00000000)          /*!< UART disabled  */
-#define UART_STATE_ENABLE                   ((uint32_t)USART_CR1_UE)        /*!< UART enabled   */
-/**
-  * @}
-  */
-
-/** @defgroup UART_Over_Sampling UART Over Sampling
-  * @{
-  */
-#define UART_OVERSAMPLING_16                ((uint32_t)0x00000000)          /*!< Oversampling by 16 */
-#define UART_OVERSAMPLING_8                 ((uint32_t)USART_CR1_OVER8)     /*!< Oversampling by 8  */
-/**
-  * @}
-  */
-
-/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method
-  * @{
-  */
-#define UART_ONE_BIT_SAMPLE_DISABLE         ((uint32_t)0x00000000)          /*!< One-bit sampling disable */
-#define UART_ONE_BIT_SAMPLE_ENABLE          ((uint32_t)USART_CR3_ONEBIT)    /*!< One-bit sampling enable  */
-/**
-  * @}
-  */
-
-/** @defgroup UART_AutoBaud_Rate_Mode    UART Advanced Feature AutoBaud Rate Mode
-  * @{
-  */
-#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT    ((uint32_t)0x0000)                /*!< Auto Baud rate detection on start bit            */
-#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0)   /*!< Auto Baud rate detection on falling edge         */
-#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME   ((uint32_t)USART_CR2_ABRMODE_1)   /*!< Auto Baud rate detection on 0x7F frame detection */    
-#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME   ((uint32_t)USART_CR2_ABRMODE)     /*!< Auto Baud rate detection on 0x55 frame detection */
-/**
-  * @}
-  */
-
-/** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut
-  * @{
-  */
-#define UART_RECEIVER_TIMEOUT_DISABLE       ((uint32_t)0x00000000)                  /*!< UART receiver timeout disable */
-#define UART_RECEIVER_TIMEOUT_ENABLE        ((uint32_t)USART_CR2_RTOEN)             /*!< UART receiver timeout enable  */
-/**
-  * @}
-  */
-
-/** @defgroup UART_LIN    UART Local Interconnection Network mode
-  * @{
-  */
-#define UART_LIN_DISABLE                    ((uint32_t)0x00000000)                 /*!< Local Interconnect Network disable */
-#define UART_LIN_ENABLE                     ((uint32_t)USART_CR2_LINEN)            /*!< Local Interconnect Network enable  */
-/**
-  * @}
-  */
-
-/** @defgroup UART_LIN_Break_Detection  UART LIN Break Detection
-  * @{
-  */
-#define UART_LINBREAKDETECTLENGTH_10B       ((uint32_t)0x00000000)                /*!< LIN 10-bit break detection length */
-#define UART_LINBREAKDETECTLENGTH_11B       ((uint32_t)USART_CR2_LBDL)            /*!< LIN 11-bit break detection length  */
-/**
-  * @}
-  */
-
-/** @defgroup UART_DMA_Tx    UART DMA Tx
-  * @{
-  */
-#define UART_DMA_TX_DISABLE                 ((uint32_t)0x00000000)                /*!< UART DMA TX disabled */
-#define UART_DMA_TX_ENABLE                  ((uint32_t)USART_CR3_DMAT)            /*!< UART DMA TX enabled  */
-/**
-  * @}
-  */
-
-/** @defgroup UART_DMA_Rx   UART DMA Rx
-  * @{
-  */
-#define UART_DMA_RX_DISABLE                 ((uint32_t)0x0000)                      /*!< UART DMA RX disabled */
-#define UART_DMA_RX_ENABLE                  ((uint32_t)USART_CR3_DMAR)              /*!< UART DMA RX enabled  */
-/**
-  * @}
-  */
-
-/** @defgroup UART_Half_Duplex_Selection  UART Half Duplex Selection
-  * @{
-  */
-#define UART_HALF_DUPLEX_DISABLE            ((uint32_t)0x0000)                      /*!< UART half-duplex disabled */
-#define UART_HALF_DUPLEX_ENABLE             ((uint32_t)USART_CR3_HDSEL)             /*!< UART half-duplex enabled  */
-/**
-  * @}
-  */
-
-/** @defgroup UART_WakeUp_Methods   UART WakeUp Methods
-  * @{
-  */
-#define UART_WAKEUPMETHOD_IDLELINE          ((uint32_t)0x00000000)                  /*!< UART wake-up on idle line    */
-#define UART_WAKEUPMETHOD_ADDRESSMARK       ((uint32_t)USART_CR1_WAKE)              /*!< UART wake-up on address mark */
-/**
-  * @}
-  */
-
-/** @defgroup UART_Request_Parameters UART Request Parameters
-  * @{
-  */
-#define UART_AUTOBAUD_REQUEST               ((uint32_t)USART_RQR_ABRRQ)        /*!< Auto-Baud Rate Request      */
-#define UART_SENDBREAK_REQUEST              ((uint32_t)USART_RQR_SBKRQ)        /*!< Send Break Request          */
-#define UART_MUTE_MODE_REQUEST              ((uint32_t)USART_RQR_MMRQ)         /*!< Mute Mode Request           */
-#define UART_RXDATA_FLUSH_REQUEST           ((uint32_t)USART_RQR_RXFRQ)        /*!< Receive Data flush Request  */
-#define UART_TXDATA_FLUSH_REQUEST           ((uint32_t)USART_RQR_TXFRQ)        /*!< Transmit data flush Request */
-/**
-  * @}
-  */
-
-/** @defgroup UART_Advanced_Features_Initialization_Type  UART Advanced Feature Initialization Type
-  * @{
-  */
-#define UART_ADVFEATURE_NO_INIT                 ((uint32_t)0x00000000)          /*!< No advanced feature initialization       */
-#define UART_ADVFEATURE_TXINVERT_INIT           ((uint32_t)0x00000001)          /*!< TX pin active level inversion            */
-#define UART_ADVFEATURE_RXINVERT_INIT           ((uint32_t)0x00000002)          /*!< RX pin active level inversion            */
-#define UART_ADVFEATURE_DATAINVERT_INIT         ((uint32_t)0x00000004)          /*!< Binary data inversion                    */
-#define UART_ADVFEATURE_SWAP_INIT               ((uint32_t)0x00000008)          /*!< TX/RX pins swap                          */
-#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT   ((uint32_t)0x00000010)          /*!< RX overrun disable                       */
-#define UART_ADVFEATURE_DMADISABLEONERROR_INIT  ((uint32_t)0x00000020)          /*!< DMA disable on Reception Error           */
-#define UART_ADVFEATURE_AUTOBAUDRATE_INIT       ((uint32_t)0x00000040)          /*!< Auto Baud rate detection initialization  */
-#define UART_ADVFEATURE_MSBFIRST_INIT           ((uint32_t)0x00000080)          /*!< Most significant bit sent/received first */
-/**
-  * @}
-  */
-
-/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion
-  * @{
-  */
-#define UART_ADVFEATURE_TXINV_DISABLE       ((uint32_t)0x00000000)              /*!< TX pin active level inversion disable */
-#define UART_ADVFEATURE_TXINV_ENABLE        ((uint32_t)USART_CR2_TXINV)         /*!< TX pin active level inversion enable  */
-/**
-  * @}
-  */
-
-/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion
-  * @{
-  */
-#define UART_ADVFEATURE_RXINV_DISABLE       ((uint32_t)0x00000000)              /*!< RX pin active level inversion disable */ 
-#define UART_ADVFEATURE_RXINV_ENABLE        ((uint32_t)USART_CR2_RXINV)         /*!< RX pin active level inversion enable  */ 
-/**
-  * @}
-  */
-
-/** @defgroup UART_Data_Inv  UART Advanced Feature Binary Data Inversion
-  * @{
-  */
-#define UART_ADVFEATURE_DATAINV_DISABLE     ((uint32_t)0x00000000)              /*!< Binary data inversion disable */
-#define UART_ADVFEATURE_DATAINV_ENABLE      ((uint32_t)USART_CR2_DATAINV)       /*!< Binary data inversion enable  */
-/**
-  * @}
-  */
-
-/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap
-  * @{
-  */
-#define UART_ADVFEATURE_SWAP_DISABLE        ((uint32_t)0x00000000)              /*!< TX/RX pins swap disable */
-#define UART_ADVFEATURE_SWAP_ENABLE         ((uint32_t)USART_CR2_SWAP)          /*!< TX/RX pins swap enable  */
-/**
-  * @}
-  */
-
-/** @defgroup UART_Overrun_Disable  UART Advanced Feature Overrun Disable
-  * @{
-  */
-#define UART_ADVFEATURE_OVERRUN_ENABLE      ((uint32_t)0x00000000)              /*!< RX overrun enable  */ 
-#define UART_ADVFEATURE_OVERRUN_DISABLE     ((uint32_t)USART_CR3_OVRDIS)        /*!< RX overrun disable */ 
-/**
-  * @}
-  */
-
-/** @defgroup UART_AutoBaudRate_Enable  UART Advanced Feature Auto BaudRate Enable
-  * @{
-  */
-#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE   ((uint32_t)0x00000000)           /*!< RX Auto Baud rate detection enable  */ 
-#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE    ((uint32_t)USART_CR2_ABREN)      /*!< RX Auto Baud rate detection disable */ 
-/**
-  * @}
-  */
-
-/** @defgroup UART_DMA_Disable_on_Rx_Error   UART Advanced Feature DMA Disable On Rx Error
-  * @{
-  */
-#define UART_ADVFEATURE_DMA_ENABLEONRXERROR    ((uint32_t)0x00000000)           /*!< DMA enable on Reception Error  */
-#define UART_ADVFEATURE_DMA_DISABLEONRXERROR   ((uint32_t)USART_CR3_DDRE)       /*!< DMA disable on Reception Error */
-/**
-  * @}
-  */
-
-/** @defgroup UART_MSB_First   UART Advanced Feature MSB First
-  * @{
-  */
-#define UART_ADVFEATURE_MSBFIRST_DISABLE    ((uint32_t)0x00000000)              /*!< Most significant bit sent/received first disable */
-#define UART_ADVFEATURE_MSBFIRST_ENABLE     ((uint32_t)USART_CR2_MSBFIRST)      /*!< Most significant bit sent/received first enable  */
-/**
-  * @}
-  */
-
-/** @defgroup UART_Stop_Mode_Enable   UART Advanced Feature Stop Mode Enable
-  * @{
-  */
-#define UART_ADVFEATURE_STOPMODE_DISABLE    ((uint32_t)0x00000000)              /*!< UART stop mode disable */
-#define UART_ADVFEATURE_STOPMODE_ENABLE     ((uint32_t)USART_CR1_UESM)          /*!< UART stop mode enable  */
-/**
-  * @}
-  */
-
-/** @defgroup UART_Mute_Mode   UART Advanced Feature Mute Mode Enable
-  * @{
-  */
-#define UART_ADVFEATURE_MUTEMODE_DISABLE    ((uint32_t)0x00000000)              /*!< UART mute mode disable */
-#define UART_ADVFEATURE_MUTEMODE_ENABLE     ((uint32_t)USART_CR1_MME)           /*!< UART mute mode enable  */
-/**
-  * @}
-  */
-
-/** @defgroup UART_CR2_ADDRESS_LSB_POS    UART Address-matching LSB Position In CR2 Register
-  * @{
-  */
-#define UART_CR2_ADDRESS_LSB_POS            ((uint32_t) 24)                     /*!< UART address-matching LSB position in CR2 register */
-/**
-  * @}
-  */
-
-/** @defgroup UART_WakeUp_from_Stop_Selection   UART WakeUp From Stop Selection
-  * @{
-  */
-#define UART_WAKEUP_ON_ADDRESS              ((uint32_t)0x00000000)              /*!< UART wake-up on address                         */
-#define UART_WAKEUP_ON_STARTBIT             ((uint32_t)USART_CR3_WUS_1)         /*!< UART wake-up on start bit                       */
-#define UART_WAKEUP_ON_READDATA_NONEMPTY    ((uint32_t)USART_CR3_WUS)           /*!< UART wake-up on receive data register not empty */
-/**
-  * @}
-  */
-
-/** @defgroup UART_DriverEnable_Polarity      UART DriverEnable Polarity
-  * @{
-  */
-#define UART_DE_POLARITY_HIGH               ((uint32_t)0x00000000)              /*!< Driver enable signal is active high */
-#define UART_DE_POLARITY_LOW                ((uint32_t)USART_CR3_DEP)           /*!< Driver enable signal is active low  */
-/**
-  * @}
-  */
-
-/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS    UART Driver Enable Assertion Time LSB Position In CR1 Register
-  * @{
-  */
-#define UART_CR1_DEAT_ADDRESS_LSB_POS       ((uint32_t) 21)                     /*!< UART Driver Enable assertion time LSB position in CR1 register */
-/**
-  * @}
-  */
-
-/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS    UART Driver Enable DeAssertion Time LSB Position In CR1 Register
-  * @{
-  */
-#define UART_CR1_DEDT_ADDRESS_LSB_POS       ((uint32_t) 16)                     /*!< UART Driver Enable de-assertion time LSB position in CR1 register */
-/**
-  * @}
-  */
-
-/** @defgroup UART_Interruption_Mask    UART Interruptions Flag Mask
-  * @{
-  */
-#define UART_IT_MASK                        ((uint32_t)0x001F)                  /*!< UART interruptions flags mask */
-/**
-  * @}
-  */
-
-/** @defgroup UART_TimeOut_Value    UART polling-based communications time-out value
-  * @{
-  */
-#define HAL_UART_TIMEOUT_VALUE              0x1FFFFFF                           /*!< UART polling-based communications time-out value */
-/**
-  * @}
-  */
-
-/** @defgroup UART_Flags     UART Status Flags
-  *        Elements values convention: 0xXXXX
-  *           - 0xXXXX  : Flag mask in the ISR register
-  * @{
-  */
-#define UART_FLAG_REACK                     ((uint32_t)0x00400000)              /*!< UART receive enable acknowledge flag      */
-#define UART_FLAG_TEACK                     ((uint32_t)0x00200000)              /*!< UART transmit enable acknowledge flag     */
-#define UART_FLAG_WUF                       ((uint32_t)0x00100000)              /*!< UART wake-up from stop mode flag          */
-#define UART_FLAG_RWU                       ((uint32_t)0x00080000)              /*!< UART receiver wake-up from mute mode flag */
-#define UART_FLAG_SBKF                      ((uint32_t)0x00040000)              /*!< UART send break flag                      */
-#define UART_FLAG_CMF                       ((uint32_t)0x00020000)              /*!< UART character match flag                 */
-#define UART_FLAG_BUSY                      ((uint32_t)0x00010000)              /*!< UART busy flag                            */
-#define UART_FLAG_ABRF                      ((uint32_t)0x00008000)              /*!< UART auto Baud rate flag                  */
-#define UART_FLAG_ABRE                      ((uint32_t)0x00004000)              /*!< UART uto Baud rate error                  */
-#define UART_FLAG_EOBF                      ((uint32_t)0x00001000)              /*!< UART end of block flag                    */
-#define UART_FLAG_RTOF                      ((uint32_t)0x00000800)              /*!< UART receiver timeout flag                */
-#define UART_FLAG_CTS                       ((uint32_t)0x00000400)              /*!< UART clear to send flag                   */
-#define UART_FLAG_CTSIF                     ((uint32_t)0x00000200)              /*!< UART clear to send interrupt flag         */
-#define UART_FLAG_LBDF                      ((uint32_t)0x00000100)              /*!< UART LIN break detection flag             */
-#define UART_FLAG_TXE                       ((uint32_t)0x00000080)              /*!< UART transmit data register empty         */
-#define UART_FLAG_TC                        ((uint32_t)0x00000040)              /*!< UART transmission complete                */
-#define UART_FLAG_RXNE                      ((uint32_t)0x00000020)              /*!< UART read data register not empty         */
-#define UART_FLAG_IDLE                      ((uint32_t)0x00000010)              /*!< UART idle flag                            */
-#define UART_FLAG_ORE                       ((uint32_t)0x00000008)              /*!< UART overrun error                        */
-#define UART_FLAG_NE                        ((uint32_t)0x00000004)              /*!< UART noise error                          */
-#define UART_FLAG_FE                        ((uint32_t)0x00000002)              /*!< UART frame error                          */
-#define UART_FLAG_PE                        ((uint32_t)0x00000001)              /*!< UART parity error                         */
-/**
-  * @}
-  */
-
-/** @defgroup UART_Interrupt_definition   UART Interrupts Definition
-  *        Elements values convention: 000ZZZZZ0XXYYYYYb
-  *           - YYYYY  : Interrupt source position in the XX register (5bits)
-  *           - XX  : Interrupt source register (2bits)
-  *                 - 01: CR1 register
-  *                 - 10: CR2 register
-  *                 - 11: CR3 register
-  *           - ZZZZZ  : Flag position in the ISR register(5bits)
-  * @{
-  */
-#define UART_IT_PE                          ((uint32_t)0x0028)                  /*!< UART parity error interruption                 */    
-#define UART_IT_TXE                         ((uint32_t)0x0727)                  /*!< UART transmit data register empty interruption */    
-#define UART_IT_TC                          ((uint32_t)0x0626)                  /*!< UART transmission complete interruption        */    
-#define UART_IT_RXNE                        ((uint32_t)0x0525)                  /*!< UART read data register not empty interruption */    
-#define UART_IT_IDLE                        ((uint32_t)0x0424)                  /*!< UART idle interruption                         */                                                               
-#define UART_IT_LBD                         ((uint32_t)0x0846)                  /*!< UART LIN break detection interruption          */                
-#define UART_IT_CTS                         ((uint32_t)0x096A)                  /*!< UART CTS interruption                          */                
-#define UART_IT_CM                          ((uint32_t)0x112E)                  /*!< UART character match interruption              */                
-#define UART_IT_WUF                         ((uint32_t)0x1476)                  /*!< UART wake-up from stop mode interruption       */                
-                                                                                                     
-/*        Elements values convention: 000000000XXYYYYYb                                         
-              - YYYYY  : Interrupt source position in the XX register (5bits)                   
-              - XX  : Interrupt source register (2bits)
-                    - 01: CR1 register
-                    - 10: CR2 register
-                    - 11: CR3 register */
-#define UART_IT_ERR                         ((uint32_t)0x0060)                  /*!< UART error interruption         */   
-                                                                                  
-/*       Elements values convention: 0000ZZZZ00000000b                            
-             - ZZZZ  : Flag position in the ISR register(4bits) */                
-#define UART_IT_ORE                         ((uint32_t)0x0300)                  /*!< UART overrun error interruption */ 
-#define UART_IT_NE                          ((uint32_t)0x0200)                  /*!< UART noise error interruption   */ 
-#define UART_IT_FE                          ((uint32_t)0x0100)                  /*!< UART frame error interruption   */ 
-/**
-  * @}
-  */
-
-/** @defgroup UART_IT_CLEAR_Flags  UART Interruption Clear Flags
-  * @{
-  */
-#define UART_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag           */
-#define UART_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag          */
-#define UART_CLEAR_NEF                       USART_ICR_NCF             /*!< Noise detected Clear Flag         */
-#define UART_CLEAR_OREF                      USART_ICR_ORECF           /*!< Overrun Error Clear Flag          */
-#define UART_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag     */
-#define UART_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag  */
-#define UART_CLEAR_LBDF                      USART_ICR_LBDCF           /*!< LIN Break Detection Clear Flag    */
-#define UART_CLEAR_CTSF                      USART_ICR_CTSCF           /*!< CTS Interrupt Clear Flag          */
-#define UART_CLEAR_RTOF                      USART_ICR_RTOCF           /*!< Receiver Time Out Clear Flag      */
-#define UART_CLEAR_EOBF                      USART_ICR_EOBCF           /*!< End Of Block Clear Flag           */
-#define UART_CLEAR_CMF                       USART_ICR_CMCF            /*!< Character Match Clear Flag        */
-#define UART_CLEAR_WUF                       USART_ICR_WUCF            /*!< Wake Up from stop mode Clear Flag */
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup UART_Exported_Macros UART Exported Macros
-  * @{
-  */
-
-/** @brief Reset UART handle state.
-  * @param  __HANDLE__: UART handle.
-  * @retval None
-  */
-#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_UART_STATE_RESET)
-
-/** @brief  Flush the UART Data registers.
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @retval None  
-  */
-#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__)  \
-  do{                \
-      SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
-      SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
-    }  while(0)
-
-/** @brief  Clear the specified UART pending flag.
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @param  __FLAG__: specifies the flag to check.
-  *          This parameter can be any combination of the following values:
-  *            @arg @ref UART_CLEAR_PEF      Parity Error Clear Flag           
-  *            @arg @ref UART_CLEAR_FEF      Framing Error Clear Flag          
-  *            @arg @ref UART_CLEAR_NEF      Noise detected Clear Flag         
-  *            @arg @ref UART_CLEAR_OREF     Overrun Error Clear Flag          
-  *            @arg @ref UART_CLEAR_IDLEF    IDLE line detected Clear Flag     
-  *            @arg @ref UART_CLEAR_TCF      Transmission Complete Clear Flag  
-  *            @arg @ref UART_CLEAR_LBDF     LIN Break Detection Clear Flag    
-  *            @arg @ref UART_CLEAR_CTSF     CTS Interrupt Clear Flag          
-  *            @arg @ref UART_CLEAR_RTOF     Receiver Time Out Clear Flag      
-  *            @arg @ref UART_CLEAR_EOBF     End Of Block Clear Flag           
-  *            @arg @ref UART_CLEAR_CMF      Character Match Clear Flag        
-  *            @arg @ref UART_CLEAR_WUF      Wake Up from stop mode Clear Flag 
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
-
-/** @brief  Clear the UART PE pending flag.
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
-
-/** @brief  Clear the UART FE pending flag.
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
-
-/** @brief  Clear the UART NE pending flag.
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__)  __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
-
-/** @brief  Clear the UART ORE pending flag.
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
-
-/** @brief  Clear the UART IDLE pending flag.
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
-
-/** @brief  Check whether the specified UART flag is set or not.
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @param  __FLAG__: specifies the flag to check.
-  *        This parameter can be one of the following values:
-  *            @arg @ref UART_FLAG_REACK Receive enable acknowledge flag
-  *            @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag
-  *            @arg @ref UART_FLAG_WUF   Wake up from stop mode flag
-  *            @arg @ref UART_FLAG_RWU   Receiver wake up flag (if the UART in mute mode)
-  *            @arg @ref UART_FLAG_SBKF  Send Break flag
-  *            @arg @ref UART_FLAG_CMF   Character match flag
-  *            @arg @ref UART_FLAG_BUSY  Busy flag
-  *            @arg @ref UART_FLAG_ABRF  Auto Baud rate detection flag
-  *            @arg @ref UART_FLAG_ABRE  Auto Baud rate detection error flag
-  *            @arg @ref UART_FLAG_EOBF  End of block flag
-  *            @arg @ref UART_FLAG_RTOF  Receiver timeout flag
-  *            @arg @ref UART_FLAG_CTS   CTS Change flag
-  *            @arg @ref UART_FLAG_LBDF  LIN Break detection flag
-  *            @arg @ref UART_FLAG_TXE   Transmit data register empty flag
-  *            @arg @ref UART_FLAG_TC    Transmission Complete flag
-  *            @arg @ref UART_FLAG_RXNE  Receive data register not empty flag
-  *            @arg @ref UART_FLAG_IDLE  Idle Line detection flag
-  *            @arg @ref UART_FLAG_ORE   Overrun Error flag
-  *            @arg @ref UART_FLAG_NE    Noise Error flag
-  *            @arg @ref UART_FLAG_FE    Framing Error flag
-  *            @arg @ref UART_FLAG_PE    Parity Error flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Enable the specified UART interrupt.
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @param  __INTERRUPT__: specifies the UART interrupt source to enable.
-  *          This parameter can be one of the following values:
-  *            @arg @ref UART_IT_WUF  Wakeup from stop mode interrupt
-  *            @arg @ref UART_IT_CM   Character match interrupt
-  *            @arg @ref UART_IT_CTS  CTS change interrupt
-  *            @arg @ref UART_IT_LBD  LIN Break detection interrupt
-  *            @arg @ref UART_IT_TXE  Transmit Data Register empty interrupt
-  *            @arg @ref UART_IT_TC   Transmission complete interrupt
-  *            @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
-  *            @arg @ref UART_IT_IDLE Idle line detection interrupt
-  *            @arg @ref UART_IT_PE   Parity Error interrupt
-  *            @arg @ref UART_IT_ERR  Error interrupt (Frame error, noise error, overrun error)
-  * @retval None
-  */
-#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
-                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
-                                                           ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))))
-
-
-/** @brief  Disable the specified UART interrupt.
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @param  __INTERRUPT__: specifies the UART interrupt source to disable.
-  *          This parameter can be one of the following values:
-  *            @arg @ref UART_IT_WUF  Wakeup from stop mode interrupt
-  *            @arg @ref UART_IT_CM   Character match interrupt
-  *            @arg @ref UART_IT_CTS  CTS change interrupt
-  *            @arg @ref UART_IT_LBD  LIN Break detection interrupt
-  *            @arg @ref UART_IT_TXE  Transmit Data Register empty interrupt
-  *            @arg @ref UART_IT_TC   Transmission complete interrupt
-  *            @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
-  *            @arg @ref UART_IT_IDLE Idle line detection interrupt
-  *            @arg @ref UART_IT_PE   Parity Error interrupt
-  *            @arg @ref UART_IT_ERR  Error interrupt (Frame error, noise error, overrun error)
-  * @retval None
-  */
-#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
-                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
-                                                           ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))
-
-/** @brief  Check whether the specified UART interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @param  __IT__: specifies the UART interrupt to check.
-  *          This parameter can be one of the following values:
-  *            @arg @ref UART_IT_WUF  Wakeup from stop mode interrupt
-  *            @arg @ref UART_IT_CM   Character match interrupt
-  *            @arg @ref UART_IT_CTS  CTS change interrupt
-  *            @arg @ref UART_IT_LBD  LIN Break detection interrupt
-  *            @arg @ref UART_IT_TXE  Transmit Data Register empty interrupt
-  *            @arg @ref UART_IT_TC   Transmission complete interrupt
-  *            @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
-  *            @arg @ref UART_IT_IDLE Idle line detection interrupt
-  *            @arg @ref UART_IT_ORE  Overrun Error interrupt
-  *            @arg @ref UART_IT_NE   Noise Error interrupt   
-  *            @arg @ref UART_IT_FE   Framing Error interrupt   
-  *            @arg @ref UART_IT_PE   Parity Error interrupt
-  * @retval The new state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
-
-/** @brief  Check whether the specified UART interrupt source is enabled or not.
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @param  __IT__: specifies the UART interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg @ref UART_IT_WUF  Wakeup from stop mode interrupt
-  *            @arg @ref UART_IT_CM   Character match interrupt  
-  *            @arg @ref UART_IT_CTS  CTS change interrupt
-  *            @arg @ref UART_IT_LBD  LIN Break detection interrupt
-  *            @arg @ref UART_IT_TXE  Transmit Data Register empty interrupt
-  *            @arg @ref UART_IT_TC   Transmission complete interrupt
-  *            @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
-  *            @arg @ref UART_IT_IDLE Idle line detection interrupt
-  *            @arg @ref UART_IT_ERR  Error interrupt (Frame error, noise error, overrun error)
-  *            @arg @ref UART_IT_PE   Parity Error interrupt
-  * @retval The new state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \
-                                                       (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & UART_IT_MASK)))
-
-/** @brief  Clear the specified UART ISR flag, in setting the proper ICR register flag.
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @param  __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
-  *                       to clear the corresponding interrupt
-  *          This parameter can be one of the following values:
-  *            @arg @ref UART_CLEAR_PEF Parity Error Clear Flag
-  *            @arg @ref UART_CLEAR_FEF Framing Error Clear Flag
-  *            @arg @ref UART_CLEAR_NEF Noise detected Clear Flag
-  *            @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag
-  *            @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag
-  *            @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag
-  *            @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag
-  *            @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag
-  *            @arg @ref UART_CLEAR_CMF Character Match Clear Flag
-  *            @arg @ref UART_CLEAR_WUF  Wake Up from stop mode Clear Flag
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
-
-/** @brief  Set a specific UART request flag.
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @param  __REQ__: specifies the request flag to set
-  *          This parameter can be one of the following values:
-  *            @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request
-  *            @arg @ref UART_SENDBREAK_REQUEST Send Break Request
-  *            @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request
-  *            @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request
-  *            @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request
-  * @retval None
-  */
-#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__))
-
-/** @brief  Enable the UART one bit sample method.
-  * @param  __HANDLE__: specifies the UART Handle.  
-  * @retval None
-  */     
-#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
-
-/** @brief  Disable the UART one bit sample method.
-  * @param  __HANDLE__: specifies the UART Handle.  
-  * @retval None
-  */      
-#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
-
-/** @brief  Enable UART.
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @retval None
-  */
-#define __HAL_UART_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
-
-/** @brief  Disable UART.
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @retval None
-  */
-#define __HAL_UART_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
-
-/** @brief  Enable CTS flow control.
-  * @note   This macro allows to enable CTS hardware flow control for a given UART instance, 
-  *         without need to call HAL_UART_Init() function.
-  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
-  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
-  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
-  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
-  *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
-  *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).                                                                                                                  
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @retval None
-  */
-#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)        \
-  do{                                                      \
-    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \
-    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;        \
-  } while(0)
-
-/** @brief  Disable CTS flow control.
-  * @note   This macro allows to disable CTS hardware flow control for a given UART instance, 
-  *         without need to call HAL_UART_Init() function.
-  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
-  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
-  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
-  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
-  *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
-  *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). 
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @retval None
-  */
-#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)        \
-  do{                                                       \
-    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
-    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);      \
-  } while(0)
-
-/** @brief  Enable RTS flow control.
-  * @note   This macro allows to enable RTS hardware flow control for a given UART instance, 
-  *         without need to call HAL_UART_Init() function.
-  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
-  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
-  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
-  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
-  *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
-  *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). 
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @retval None
-  */
-#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)       \
-  do{                                                     \
-    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
-    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;       \
-  } while(0)
-
-/** @brief  Disable RTS flow control.
-  * @note   This macro allows to disable RTS hardware flow control for a given UART instance, 
-  *         without need to call HAL_UART_Init() function.
-  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
-  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
-  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
-  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
-  *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
-  *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). 
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @retval None
-  */
-#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)       \
-  do{                                                      \
-    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
-    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);     \
-  } while(0)
-
-/**
-  * @}
-  */
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup UART_Private_Macros   UART Private Macros
-  * @{
-  */
-/** @brief  BRR division operation to set BRR register with LPUART.
-  * @param  __PCLK__: LPUART clock.
-  * @param  __BAUD__: Baud rate set by the user.
-  * @retval Division result
-  */
-/* FIXME tobbad Adapted to avoid 64 bit division. */
-#define UART_DIV_LPUART(__PCLK__, __BAUD__)                HAL_UART_CalcBrr((__PCLK__), (__BAUD__))
-
-/** @brief  BRR division operation to set BRR register in 8-bit oversampling mode.
-  * @param  __PCLK__: UART clock.
-  * @param  __BAUD__: Baud rate set by the user.
-  * @retval Division result
-  */
-#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__)             (((__PCLK__)*2)/((__BAUD__)))
-
-/** @brief  BRR division operation to set BRR register in 16-bit oversampling mode.
-  * @param  __PCLK__: UART clock.
-  * @param  __BAUD__: Baud rate set by the user.
-  * @retval Division result
-  */
-#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__)             (((__PCLK__))/((__BAUD__)))
-
-/** @brief  Check whether or not UART instance is Low Power UART.
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @retval SET (instance is LPUART) or RESET (instance isn't LPUART)
-  */
-#define UART_INSTANCE_LOWPOWER(__HANDLE__) (((__HANDLE__)->Instance == LPUART1) ? SET : RESET )
-
-/** @brief  Check UART Baud rate.
-  * @param  __BAUDRATE__: Baudrate specified by the user.
-  *         The maximum Baud Rate is derived from the maximum clock on L4 (i.e. 80 MHz)
-  *         divided by the smallest oversampling used on the USART (i.e. 8)
-  * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)
-  */
-#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 10000001)
-
-/** @brief  Check UART assertion time.
-  * @param  __TIME__: 5-bit value assertion time.
-  * @retval Test result (TRUE or FALSE).
-  */
-#define IS_UART_ASSERTIONTIME(__TIME__)    ((__TIME__) <= 0x1F)
-
-/** @brief  Check UART deassertion time.
-  * @param  __TIME__: 5-bit value deassertion time.
-  * @retval Test result (TRUE or FALSE).
-  */
-#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1F)
-
-/**
-  * @brief Ensure that UART frame number of stop bits is valid.
-  * @param __STOPBITS__: UART frame number of stop bits. 
-  * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)  UART_STOPBITS_1_5
-  */
-#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \
-                                        ((__STOPBITS__) == UART_STOPBITS_1)   || \
-                                        ((__STOPBITS__) == UART_STOPBITS_1_5) || \
-                                        ((__STOPBITS__) == UART_STOPBITS_2))
-
-/**
-  * @brief Ensure that LPUART frame number of stop bits is valid.
-  * @param __STOPBITS__: LPUART frame number of stop bits. 
-  * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
-  */ 
-#define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \
-                                          ((__STOPBITS__) == UART_STOPBITS_2))
-
-/**
-  * @brief Ensure that UART frame parity is valid.
-  * @param __PARITY__: UART frame parity. 
-  * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
-  */ 
-#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \
-                                    ((__PARITY__) == UART_PARITY_EVEN) || \
-                                    ((__PARITY__) == UART_PARITY_ODD))
-
-/**
-  * @brief Ensure that UART hardware flow control is valid.
-  * @param __CONTROL__: UART hardware flow control. 
-  * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)
-  */ 
-#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\
-                                   (((__CONTROL__) == UART_HWCONTROL_NONE) || \
-                                    ((__CONTROL__) == UART_HWCONTROL_RTS)  || \
-                                    ((__CONTROL__) == UART_HWCONTROL_CTS)  || \
-                                    ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
-
-/**
-  * @brief Ensure that UART communication mode is valid.
-  * @param __MODE__: UART communication mode. 
-  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
-  */ 
-#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00))
-
-/**
-  * @brief Ensure that UART state is valid.
-  * @param __STATE__: UART state. 
-  * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
-  */ 
-#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \
-                                  ((__STATE__) == UART_STATE_ENABLE))
-
-/**
-  * @brief Ensure that UART oversampling is valid.
-  * @param __SAMPLING__: UART oversampling. 
-  * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
-  */ 
-#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \
-                                            ((__SAMPLING__) == UART_OVERSAMPLING_8))
-
-/**
-  * @brief Ensure that UART frame sampling is valid.
-  * @param __ONEBIT__: UART frame sampling. 
-  * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
-  */
-#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \
-                                            ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))
-
-/**
-  * @brief Ensure that UART auto Baud rate detection mode is valid.
-  * @param __MODE__: UART auto Baud rate detection mode. 
-  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
-  */
-#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__)  (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT)    || \
-                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
-                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME)   || \
-                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
-
-/**
-  * @brief Ensure that UART receiver timeout setting is valid.
-  * @param __TIMEOUT__: UART receiver timeout setting. 
-  * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
-  */
-#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
-                                               ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))
-
-/**
-  * @brief Ensure that UART LIN state is valid.
-  * @param __LIN__: UART LIN state. 
-  * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid)
-  */
-#define IS_UART_LIN(__LIN__)        (((__LIN__) == UART_LIN_DISABLE) || \
-                                     ((__LIN__) == UART_LIN_ENABLE))
-
-/**
-  * @brief Ensure that UART LIN break detection length is valid.
-  * @param __LENGTH__: UART LIN break detection length. 
-  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
-  */
-#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \
-                                                     ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))
-
-/**
-  * @brief Ensure that UART DMA TX state is valid.
-  * @param __DMATX__: UART DMA TX state. 
-  * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
-  */
-#define IS_UART_DMA_TX(__DMATX__)     (((__DMATX__) == UART_DMA_TX_DISABLE) || \
-                                       ((__DMATX__) == UART_DMA_TX_ENABLE))
-
-/**
-  * @brief Ensure that UART DMA RX state is valid.
-  * @param __DMARX__: UART DMA RX state. 
-  * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
-  */
-#define IS_UART_DMA_RX(__DMARX__)     (((__DMARX__) == UART_DMA_RX_DISABLE) || \
-                                       ((__DMARX__) == UART_DMA_RX_ENABLE))
-
-/**
-  * @brief Ensure that UART half-duplex state is valid.
-  * @param __HDSEL__: UART half-duplex state. 
-  * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)
-  */
-#define IS_UART_HALF_DUPLEX(__HDSEL__)     (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \
-                                            ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))
-
-/**
-  * @brief Ensure that UART wake-up method is valid.
-  * @param __WAKEUP__: UART wake-up method . 
-  * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)
-  */
-#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \
-                                          ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))
-
-/**
-  * @brief Ensure that UART request parameter is valid.
-  * @param __PARAM__: UART request parameter. 
-  * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
-  */
-#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST)     || \
-                                              ((__PARAM__) == UART_SENDBREAK_REQUEST)    || \
-                                              ((__PARAM__) == UART_MUTE_MODE_REQUEST)    || \
-                                              ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \
-                                              ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))
-
-/**
-  * @brief Ensure that UART advanced features initialization is valid.
-  * @param __INIT__: UART advanced features initialization. 
-  * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
-  */
-#define IS_UART_ADVFEATURE_INIT(__INIT__)   ((__INIT__) <= (UART_ADVFEATURE_NO_INIT                | \
-                                                            UART_ADVFEATURE_TXINVERT_INIT          | \
-                                                            UART_ADVFEATURE_RXINVERT_INIT          | \
-                                                            UART_ADVFEATURE_DATAINVERT_INIT        | \
-                                                            UART_ADVFEATURE_SWAP_INIT              | \
-                                                            UART_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
-                                                            UART_ADVFEATURE_DMADISABLEONERROR_INIT | \
-                                                            UART_ADVFEATURE_AUTOBAUDRATE_INIT      | \
-                                                            UART_ADVFEATURE_MSBFIRST_INIT))
-
-/**
-  * @brief Ensure that UART frame TX inversion setting is valid.
-  * @param __TXINV__: UART frame TX inversion setting. 
-  * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
-  */
-#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \
-                                             ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))
-
-/**
-  * @brief Ensure that UART frame RX inversion setting is valid.
-  * @param __RXINV__: UART frame RX inversion setting. 
-  * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
-  */
-#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \
-                                             ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))
-
-/**
-  * @brief Ensure that UART frame data inversion setting is valid.
-  * @param __DATAINV__: UART frame data inversion setting. 
-  * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
-  */
-#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \
-                                                 ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))
-
-/**
-  * @brief Ensure that UART frame RX/TX pins swap setting is valid.
-  * @param __SWAP__: UART frame RX/TX pins swap setting. 
-  * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
-  */
-#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \
-                                           ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))
-
-/**
-  * @brief Ensure that UART frame overrun setting is valid.
-  * @param __OVERRUN__: UART frame overrun setting. 
-  * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
-  */
-#define IS_UART_OVERRUN(__OVERRUN__)     (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
-                                          ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))
-
-/**
-  * @brief Ensure that UART auto Baud rate state is valid.
-  * @param __AUTOBAUDRATE__: UART auto Baud rate state. 
-  * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)
-  */
-#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__)  (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
-                                                            ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
-
-/**
-  * @brief Ensure that UART DMA enabling or disabling on error setting is valid.
-  * @param __DMA__: UART DMA enabling or disabling on error setting. 
-  * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
-  */
-#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__)  (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
-                                                   ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))
-
-/**
-  * @brief Ensure that UART frame MSB first setting is valid.
-  * @param __MSBFIRST__: UART frame MSB first setting. 
-  * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
-  */
-#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
-                                                   ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))
-
-/**
-  * @brief Ensure that UART stop mode state is valid.
-  * @param __STOPMODE__: UART stop mode state. 
-  * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)
-  */
-#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \
-                                                   ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))
-
-/**
-  * @brief Ensure that UART mute mode state is valid.
-  * @param __MUTE__: UART mute mode state. 
-  * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)
-  */
-#define IS_UART_MUTE_MODE(__MUTE__)       (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
-                                           ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))
-
-/**
-  * @brief Ensure that UART wake-up selection is valid.
-  * @param __WAKE__: UART wake-up selection. 
-  * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)
-  */
-#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \
-                                            ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \
-                                            ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))
-
-/**
-  * @brief Ensure that UART driver enable polarity is valid.
-  * @param __POLARITY__: UART driver enable polarity. 
-  * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)
-  */
-#define IS_UART_DE_POLARITY(__POLARITY__)    (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \
-                                              ((__POLARITY__) == UART_DE_POLARITY_LOW))
-
-/**
-  * @}
-  */
-
-/* Include UART HAL Extended module */
-#include "stm32l4xx_hal_uart_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup UART_Exported_Functions UART Exported Functions
-  * @{
-  */
-
-/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-
-/* Initialization and de-initialization functions  ****************************/
-HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
-HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
-HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);
-void HAL_UART_MspInit(UART_HandleTypeDef *huart);
-void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
-
-/**
-  * @}
-  */
-
-/** @addtogroup UART_Exported_Functions_Group2 IO operation functions
-  * @{
-  */
-
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
-void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
-void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
-
-/**
-  * @}
-  */
-
-/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions
-  * @{
-  */
-
-/* Peripheral Control functions  ************************************************/
-HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);
-void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
-
-/**
-  * @}
-  */
-
-/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions
-  * @{
-  */
-
-/* Peripheral State and Errors functions  **************************************************/
-HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
-uint32_t              HAL_UART_GetError(UART_HandleTypeDef *huart);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions -----------------------------------------------------------*/
-/** @addtogroup UART_Private_Functions UART Private Functions
-  * @{
-  */
-
-HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
-void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Functions added by MicroPython */
-uint32_t HAL_UART_CalcBrr(uint32_t fck, uint32_t baud);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L4xx_HAL_UART_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/inc/stm32l4xx_hal_uart_ex.h b/stmhal/hal/l4/inc/stm32l4xx_hal_uart_ex.h
deleted file mode 100644
index 24fc34f7c1..0000000000
--- a/stmhal/hal/l4/inc/stm32l4xx_hal_uart_ex.h
+++ /dev/null
@@ -1,372 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_uart_ex.h
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   Header file of UART HAL Extended module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L4xx_HAL_UART_EX_H
-#define __STM32L4xx_HAL_UART_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup UARTEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup UARTEx_Exported_Types UARTEx Exported Types
-  * @{
-  */
-
-/**
-  * @brief  UART wake up from stop mode parameters
-  */
-typedef struct
-{
-  uint32_t WakeUpEvent;        /*!< Specifies which event will activat the Wakeup from Stop mode flag (WUF).
-                                    This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
-                                    If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
-                                    be filled up. */
-
-  uint16_t AddressLength;      /*!< Specifies whether the address is 4 or 7-bit long.
-                                    This parameter can be a value of @ref UARTEx_WakeUp_Address_Length.  */
-
-  uint8_t Address;             /*!< UART/USART node address (7-bit long max). */
-} UART_WakeUpTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
-  * @{
-  */
-
-/** @defgroup UARTEx_Word_Length UART Word Length
-  * @{
-  */
-#define UART_WORDLENGTH_7B                  ((uint32_t)USART_CR1_M1)   /*!< 7-bit long UART frame */
-#define UART_WORDLENGTH_8B                  ((uint32_t)0x00000000)     /*!< 8-bit long UART frame */
-#define UART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M0)   /*!< 9-bit long UART frame */
-/**
-  * @}
-  */
-
-/** @defgroup UARTEx_WakeUp_Address_Length UART Extended WakeUp Address Length
-  * @{
-  */
-#define UART_ADDRESS_DETECT_4B              ((uint32_t)0x00000000)       /*!< 4-bit long wake-up address */
-#define UART_ADDRESS_DETECT_7B              ((uint32_t)USART_CR2_ADDM7)  /*!< 7-bit long wake-up address */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup UARTEx_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup UARTEx_Exported_Functions_Group1
-  * @{
-  */
-
-/* Initialization and de-initialization functions  ****************************/
-HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime);
-
-/**
-  * @}
-  */
-
-/* IO operation functions *****************************************************/
-
-/** @addtogroup UARTEx_Exported_Functions_Group3
-  * @{
-  */
-
-/* Peripheral Control functions  **********************************************/
-HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
-HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
-void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup UARTEx_Private_Macros UARTEx Private Macros
-  * @{
-  */
-
-/** @brief  Report the UART clock source.
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @param  __CLOCKSOURCE__: output variable.
-  * @retval UART clocking source, written in __CLOCKSOURCE__.
-  */
-#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
-  do {                                                        \
-    if((__HANDLE__)->Instance == USART1)                      \
-    {                                                         \
-       switch(__HAL_RCC_GET_USART1_SOURCE())                  \
-       {                                                      \
-        case RCC_USART1CLKSOURCE_PCLK2:                       \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \
-          break;                                              \
-        case RCC_USART1CLKSOURCE_HSI:                         \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
-          break;                                              \
-        case RCC_USART1CLKSOURCE_SYSCLK:                      \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
-          break;                                              \
-        case RCC_USART1CLKSOURCE_LSE:                         \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
-          break;                                              \
-        default:                                              \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
-          break;                                              \
-       }                                                      \
-    }                                                         \
-    else if((__HANDLE__)->Instance == USART2)                 \
-    {                                                         \
-       switch(__HAL_RCC_GET_USART2_SOURCE())                  \
-       {                                                      \
-        case RCC_USART2CLKSOURCE_PCLK1:                       \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
-          break;                                              \
-        case RCC_USART2CLKSOURCE_HSI:                         \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
-          break;                                              \
-        case RCC_USART2CLKSOURCE_SYSCLK:                      \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
-          break;                                              \
-        case RCC_USART2CLKSOURCE_LSE:                         \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
-          break;                                              \
-        default:                                              \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
-          break;                                              \
-       }                                                      \
-    }                                                         \
-    else if((__HANDLE__)->Instance == USART3)                 \
-    {                                                         \
-       switch(__HAL_RCC_GET_USART3_SOURCE())                  \
-       {                                                      \
-        case RCC_USART3CLKSOURCE_PCLK1:                       \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
-          break;                                              \
-        case RCC_USART3CLKSOURCE_HSI:                         \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
-          break;                                              \
-        case RCC_USART3CLKSOURCE_SYSCLK:                      \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
-          break;                                              \
-        case RCC_USART3CLKSOURCE_LSE:                         \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
-          break;                                              \
-        default:                                              \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
-          break;                                              \
-       }                                                      \
-    }                                                         \
-    else if((__HANDLE__)->Instance == UART4)                  \
-    {                                                         \
-       switch(__HAL_RCC_GET_UART4_SOURCE())                   \
-       {                                                      \
-        case RCC_UART4CLKSOURCE_PCLK1:                        \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
-          break;                                              \
-        case RCC_UART4CLKSOURCE_HSI:                          \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
-          break;                                              \
-        case RCC_UART4CLKSOURCE_SYSCLK:                       \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
-          break;                                              \
-        case RCC_UART4CLKSOURCE_LSE:                          \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
-          break;                                              \
-        default:                                              \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
-          break;                                              \
-       }                                                      \
-    }                                                         \
-    else if ((__HANDLE__)->Instance == UART5)                 \
-    {                                                         \
-       switch(__HAL_RCC_GET_UART5_SOURCE())                   \
-       {                                                      \
-        case RCC_UART5CLKSOURCE_PCLK1:                        \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
-          break;                                              \
-        case RCC_UART5CLKSOURCE_HSI:                          \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
-          break;                                              \
-        case RCC_UART5CLKSOURCE_SYSCLK:                       \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
-          break;                                              \
-        case RCC_UART5CLKSOURCE_LSE:                          \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
-          break;                                              \
-        default:                                              \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
-          break;                                              \
-       }                                                      \
-    }                                                         \
-    else if((__HANDLE__)->Instance == LPUART1)                \
-    {                                                         \
-       switch(__HAL_RCC_GET_LPUART1_SOURCE())                 \
-       {                                                      \
-        case RCC_LPUART1CLKSOURCE_PCLK1:                      \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
-          break;                                              \
-        case RCC_LPUART1CLKSOURCE_HSI:                        \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
-          break;                                              \
-        case RCC_LPUART1CLKSOURCE_SYSCLK:                     \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
-          break;                                              \
-        case RCC_LPUART1CLKSOURCE_LSE:                        \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
-          break;                                              \
-        default:                                              \
-          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
-          break;                                              \
-       }                                                      \
-    }                                                         \
-  } while(0)
-
-/** @brief  Report the UART mask to apply to retrieve the received data
-  *         according to the word length and to the parity bits activation.
-  * @note   If PCE = 1, the parity bit is not included in the data extracted
-  *         by the reception API().
-  *         This masking operation is not carried out in the case of
-  *         DMA transfers.
-  * @param  __HANDLE__: specifies the UART Handle.
-  * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.
-  */
-#define UART_MASK_COMPUTATION(__HANDLE__)                             \
-  do {                                                                \
-  if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B)            \
-  {                                                                   \
-     if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)               \
-     {                                                                \
-        (__HANDLE__)->Mask = 0x01FF ;                                 \
-     }                                                                \
-     else                                                             \
-     {                                                                \
-        (__HANDLE__)->Mask = 0x00FF ;                                 \
-     }                                                                \
-  }                                                                   \
-  else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B)       \
-  {                                                                   \
-     if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)               \
-     {                                                                \
-        (__HANDLE__)->Mask = 0x00FF ;                                 \
-     }                                                                \
-     else                                                             \
-     {                                                                \
-        (__HANDLE__)->Mask = 0x007F ;                                 \
-     }                                                                \
-  }                                                                   \
-  else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B)       \
-  {                                                                   \
-     if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)               \
-     {                                                                \
-        (__HANDLE__)->Mask = 0x007F ;                                 \
-     }                                                                \
-     else                                                             \
-     {                                                                \
-        (__HANDLE__)->Mask = 0x003F ;                                 \
-     }                                                                \
-  }                                                                   \
-} while(0)
-
-
-/**
-  * @brief Ensure that UART frame length is valid.
-  * @param __LENGTH__: UART frame length. 
-  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
-  */
-#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
-                                         ((__LENGTH__) == UART_WORDLENGTH_8B) || \
-                                         ((__LENGTH__) == UART_WORDLENGTH_9B))
-
-/**
-  * @brief Ensure that UART wake-up address length is valid.
-  * @param __ADDRESS__: UART wake-up address length. 
-  * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
-  */
-#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
-                                                   ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L4xx_HAL_UART_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/inc/stm32l4xx_ll_sdmmc.h b/stmhal/hal/l4/inc/stm32l4xx_ll_sdmmc.h
deleted file mode 100644
index cc9ad48f78..0000000000
--- a/stmhal/hal/l4/inc/stm32l4xx_ll_sdmmc.h
+++ /dev/null
@@ -1,804 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_ll_sdmmc.h
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   Header file of low layer SDMMC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L4xx_LL_SDMMC_H
-#define __STM32L4xx_LL_SDMMC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-
-/** @addtogroup STM32L4xx_Driver
-  * @{
-  */
-
-/** @addtogroup SDMMC_LL
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
-  * @{
-  */
-  
-/** 
-  * @brief  SDMMC Configuration Structure definition  
-  */
-typedef struct
-{
-  uint32_t ClockEdge;            /*!< Specifies the clock transition on which the bit capture is made.
-                                      This parameter can be a value of @ref SDMMC_LL_Clock_Edge                 */
-
-  uint32_t ClockBypass;          /*!< Specifies whether the SDMMC Clock divider bypass is
-                                      enabled or disabled.
-                                      This parameter can be a value of @ref SDMMC_LL_Clock_Bypass               */
-
-  uint32_t ClockPowerSave;       /*!< Specifies whether SDMMC Clock output is enabled or
-                                      disabled when the bus is idle.
-                                      This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save           */
-
-  uint32_t BusWide;              /*!< Specifies the SDMMC bus width.
-                                      This parameter can be a value of @ref SDMMC_LL_Bus_Wide                   */
-
-  uint32_t HardwareFlowControl;  /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.
-                                      This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control      */
-
-  uint32_t ClockDiv;             /*!< Specifies the clock frequency of the SDMMC controller.
-                                      This parameter can be a value between Min_Data = 0 and Max_Data = 255 */  
-  
-}SDMMC_InitTypeDef;
-  
-
-/** 
-  * @brief  SDMMC Command Control structure 
-  */
-typedef struct                                                                                            
-{
-  uint32_t Argument;            /*!< Specifies the SDMMC command argument which is sent
-                                     to a card as part of a command message. If a command
-                                     contains an argument, it must be loaded into this register
-                                     before writing the command to the command register.              */
-
-  uint32_t CmdIndex;            /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and 
-                                     Max_Data = 64                                                    */
-
-  uint32_t Response;            /*!< Specifies the SDMMC response type.
-                                     This parameter can be a value of @ref SDMMC_LL_Response_Type         */
-
-  uint32_t WaitForInterrupt;    /*!< Specifies whether SDMMC wait for interrupt request is 
-                                     enabled or disabled.
-                                     This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State  */
-
-  uint32_t CPSM;                /*!< Specifies whether SDMMC Command path state machine (CPSM)
-                                     is enabled or disabled.
-                                     This parameter can be a value of @ref SDMMC_LL_CPSM_State            */
-}SDMMC_CmdInitTypeDef;
-
-
-/** 
-  * @brief  SDMMC Data Control structure 
-  */
-typedef struct
-{
-  uint32_t DataTimeOut;         /*!< Specifies the data timeout period in card bus clock periods.  */
-
-  uint32_t DataLength;          /*!< Specifies the number of data bytes to be transferred.         */
- 
-  uint32_t DataBlockSize;       /*!< Specifies the data block size for block transfer.
-                                     This parameter can be a value of @ref SDMMC_LL_Data_Block_Size    */
- 
-  uint32_t TransferDir;         /*!< Specifies the data transfer direction, whether the transfer
-                                     is a read or write.
-                                     This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
- 
-  uint32_t TransferMode;        /*!< Specifies whether data transfer is in stream or block mode.
-                                     This parameter can be a value of @ref SDMMC_LL_Transfer_Type      */
- 
-  uint32_t DPSM;                /*!< Specifies whether SDMMC Data path state machine (DPSM)
-                                     is enabled or disabled.
-                                     This parameter can be a value of @ref SDMMC_LL_DPSM_State         */
-}SDMMC_DataInitTypeDef;
-
-/**
-  * @}
-  */
-  
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
-  * @{
-  */
-
-/** @defgroup SDMMC_LL_Clock_Edge Clock Edge
-  * @{
-  */
-#define SDMMC_CLOCK_EDGE_RISING               ((uint32_t)0x00000000)
-#define SDMMC_CLOCK_EDGE_FALLING              SDMMC_CLKCR_NEGEDGE
-
-#define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \
-                                  ((EDGE) == SDMMC_CLOCK_EDGE_FALLING))
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass
-  * @{
-  */
-#define SDMMC_CLOCK_BYPASS_DISABLE             ((uint32_t)0x00000000)
-#define SDMMC_CLOCK_BYPASS_ENABLE              SDMMC_CLKCR_BYPASS   
-
-#define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) || \
-                                      ((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE))
-/**
-  * @}
-  */ 
-
-/** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving
-  * @{
-  */
-#define SDMMC_CLOCK_POWER_SAVE_DISABLE         ((uint32_t)0x00000000)
-#define SDMMC_CLOCK_POWER_SAVE_ENABLE          SDMMC_CLKCR_PWRSAV
-
-#define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \
-                                        ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE))
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Bus_Wide Bus Width
-  * @{
-  */
-#define SDMMC_BUS_WIDE_1B                      ((uint32_t)0x00000000)
-#define SDMMC_BUS_WIDE_4B                      SDMMC_CLKCR_WIDBUS_0
-#define SDMMC_BUS_WIDE_8B                      SDMMC_CLKCR_WIDBUS_1
-
-#define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \
-                                ((WIDE) == SDMMC_BUS_WIDE_4B) || \
-                                ((WIDE) == SDMMC_BUS_WIDE_8B))
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control
-  * @{
-  */
-#define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE    ((uint32_t)0x00000000)
-#define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE     SDMMC_CLKCR_HWFC_EN
-
-#define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \
-                                                ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE))
-/**
-  * @}
-  */
-  
-/** @defgroup SDMMC_LL_Clock_Division Clock Division
-  * @{
-  */
-#define IS_SDMMC_CLKDIV(DIV)   ((DIV) <= 0xFF)
-/**
-  * @}
-  */  
-    
-/** @defgroup SDMMC_LL_Command_Index Command Index
-  * @{
-  */
-#define IS_SDMMC_CMD_INDEX(INDEX)            ((INDEX) < 0x40)
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Response_Type Response Type
-  * @{
-  */
-#define SDMMC_RESPONSE_NO                    ((uint32_t)0x00000000)
-#define SDMMC_RESPONSE_SHORT                 SDMMC_CMD_WAITRESP_0
-#define SDMMC_RESPONSE_LONG                  SDMMC_CMD_WAITRESP
-
-#define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO)    || \
-                                    ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \
-                                    ((RESPONSE) == SDMMC_RESPONSE_LONG))
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt
-  * @{
-  */
-#define SDMMC_WAIT_NO                        ((uint32_t)0x00000000)
-#define SDMMC_WAIT_IT                        SDMMC_CMD_WAITINT 
-#define SDMMC_WAIT_PEND                      SDMMC_CMD_WAITPEND
-
-#define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \
-                            ((WAIT) == SDMMC_WAIT_IT) || \
-                            ((WAIT) == SDMMC_WAIT_PEND))
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_CPSM_State CPSM State
-  * @{
-  */
-#define SDMMC_CPSM_DISABLE                   ((uint32_t)0x00000000)
-#define SDMMC_CPSM_ENABLE                    SDMMC_CMD_CPSMEN
-
-#define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \
-                            ((CPSM) == SDMMC_CPSM_ENABLE))
-/**
-  * @}
-  */  
-
-/** @defgroup SDMMC_LL_Response_Registers Response Register
-  * @{
-  */
-#define SDMMC_RESP1                          ((uint32_t)0x00000000)
-#define SDMMC_RESP2                          ((uint32_t)0x00000004)
-#define SDMMC_RESP3                          ((uint32_t)0x00000008)
-#define SDMMC_RESP4                          ((uint32_t)0x0000000C)
-
-#define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \
-                            ((RESP) == SDMMC_RESP2) || \
-                            ((RESP) == SDMMC_RESP3) || \
-                            ((RESP) == SDMMC_RESP4))
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Data_Length Data Lenght
-  * @{
-  */
-#define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Data_Block_Size  Data Block Size
-  * @{
-  */
-#define SDMMC_DATABLOCK_SIZE_1B               ((uint32_t)0x00000000)
-#define SDMMC_DATABLOCK_SIZE_2B               SDMMC_DCTRL_DBLOCKSIZE_0
-#define SDMMC_DATABLOCK_SIZE_4B               SDMMC_DCTRL_DBLOCKSIZE_1
-#define SDMMC_DATABLOCK_SIZE_8B               (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1)
-#define SDMMC_DATABLOCK_SIZE_16B              SDMMC_DCTRL_DBLOCKSIZE_2
-#define SDMMC_DATABLOCK_SIZE_32B              (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2)
-#define SDMMC_DATABLOCK_SIZE_64B              (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
-#define SDMMC_DATABLOCK_SIZE_128B             (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
-#define SDMMC_DATABLOCK_SIZE_256B             SDMMC_DCTRL_DBLOCKSIZE_3
-#define SDMMC_DATABLOCK_SIZE_512B             (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3)
-#define SDMMC_DATABLOCK_SIZE_1024B            (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
-#define SDMMC_DATABLOCK_SIZE_2048B            (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) 
-#define SDMMC_DATABLOCK_SIZE_4096B            (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
-#define SDMMC_DATABLOCK_SIZE_8192B            (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
-#define SDMMC_DATABLOCK_SIZE_16384B           (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
-
-#define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B)    || \
-                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_2B)    || \
-                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_4B)    || \
-                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_8B)    || \
-                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_16B)   || \
-                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_32B)   || \
-                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_64B)   || \
-                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_128B)  || \
-                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_256B)  || \
-                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_512B)  || \
-                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \
-                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \
-                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \
-                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \
-                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B)) 
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction
-  * @{
-  */
-#define SDMMC_TRANSFER_DIR_TO_CARD            ((uint32_t)0x00000000)
-#define SDMMC_TRANSFER_DIR_TO_SDMMC            SDMMC_DCTRL_DTDIR
-
-#define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \
-                                   ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC))
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Transfer_Type Transfer Type
-  * @{
-  */
-#define SDMMC_TRANSFER_MODE_BLOCK             ((uint32_t)0x00000000)
-#define SDMMC_TRANSFER_MODE_STREAM            SDMMC_DCTRL_DTMODE
-
-#define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \
-                                     ((MODE) == SDMMC_TRANSFER_MODE_STREAM))
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_DPSM_State DPSM State
-  * @{
-  */
-#define SDMMC_DPSM_DISABLE                    ((uint32_t)0x00000000)
-#define SDMMC_DPSM_ENABLE                     SDMMC_DCTRL_DTEN
-
-#define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\
-                            ((DPSM) == SDMMC_DPSM_ENABLE))
-/**
-  * @}
-  */
-  
-/** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode
-  * @{
-  */
-#define SDMMC_READ_WAIT_MODE_DATA2                ((uint32_t)0x00000000)
-#define SDMMC_READ_WAIT_MODE_CLK                  (SDMMC_DCTRL_RWMOD)
-
-#define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \
-                                     ((MODE) == SDMMC_READ_WAIT_MODE_DATA2))
-/**
-  * @}
-  */  
-
-/** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources
-  * @{
-  */
-#define SDMMC_IT_CCRCFAIL                    SDMMC_STA_CCRCFAIL
-#define SDMMC_IT_DCRCFAIL                    SDMMC_STA_DCRCFAIL
-#define SDMMC_IT_CTIMEOUT                    SDMMC_STA_CTIMEOUT
-#define SDMMC_IT_DTIMEOUT                    SDMMC_STA_DTIMEOUT
-#define SDMMC_IT_TXUNDERR                    SDMMC_STA_TXUNDERR
-#define SDMMC_IT_RXOVERR                     SDMMC_STA_RXOVERR
-#define SDMMC_IT_CMDREND                     SDMMC_STA_CMDREND
-#define SDMMC_IT_CMDSENT                     SDMMC_STA_CMDSENT
-#define SDMMC_IT_DATAEND                     SDMMC_STA_DATAEND
-#define SDMMC_IT_DBCKEND                     SDMMC_STA_DBCKEND
-#define SDMMC_IT_CMDACT                      SDMMC_STA_CMDACT
-#define SDMMC_IT_TXACT                       SDMMC_STA_TXACT
-#define SDMMC_IT_RXACT                       SDMMC_STA_RXACT
-#define SDMMC_IT_TXFIFOHE                    SDMMC_STA_TXFIFOHE
-#define SDMMC_IT_RXFIFOHF                    SDMMC_STA_RXFIFOHF
-#define SDMMC_IT_TXFIFOF                     SDMMC_STA_TXFIFOF
-#define SDMMC_IT_RXFIFOF                     SDMMC_STA_RXFIFOF
-#define SDMMC_IT_TXFIFOE                     SDMMC_STA_TXFIFOE
-#define SDMMC_IT_RXFIFOE                     SDMMC_STA_RXFIFOE
-#define SDMMC_IT_TXDAVL                      SDMMC_STA_TXDAVL
-#define SDMMC_IT_RXDAVL                      SDMMC_STA_RXDAVL
-#define SDMMC_IT_SDIOIT                      SDMMC_STA_SDIOIT
-/**
-  * @}
-  */ 
-
-/** @defgroup SDMMC_LL_Flags Flags
-  * @{
-  */
-#define SDMMC_FLAG_CCRCFAIL                  SDMMC_STA_CCRCFAIL
-#define SDMMC_FLAG_DCRCFAIL                  SDMMC_STA_DCRCFAIL
-#define SDMMC_FLAG_CTIMEOUT                  SDMMC_STA_CTIMEOUT
-#define SDMMC_FLAG_DTIMEOUT                  SDMMC_STA_DTIMEOUT
-#define SDMMC_FLAG_TXUNDERR                  SDMMC_STA_TXUNDERR
-#define SDMMC_FLAG_RXOVERR                   SDMMC_STA_RXOVERR
-#define SDMMC_FLAG_CMDREND                   SDMMC_STA_CMDREND
-#define SDMMC_FLAG_CMDSENT                   SDMMC_STA_CMDSENT
-#define SDMMC_FLAG_DATAEND                   SDMMC_STA_DATAEND
-#define SDMMC_FLAG_DBCKEND                   SDMMC_STA_DBCKEND
-#define SDMMC_FLAG_CMDACT                    SDMMC_STA_CMDACT
-#define SDMMC_FLAG_TXACT                     SDMMC_STA_TXACT
-#define SDMMC_FLAG_RXACT                     SDMMC_STA_RXACT
-#define SDMMC_FLAG_TXFIFOHE                  SDMMC_STA_TXFIFOHE
-#define SDMMC_FLAG_RXFIFOHF                  SDMMC_STA_RXFIFOHF
-#define SDMMC_FLAG_TXFIFOF                   SDMMC_STA_TXFIFOF
-#define SDMMC_FLAG_RXFIFOF                   SDMMC_STA_RXFIFOF
-#define SDMMC_FLAG_TXFIFOE                   SDMMC_STA_TXFIFOE
-#define SDMMC_FLAG_RXFIFOE                   SDMMC_STA_RXFIFOE
-#define SDMMC_FLAG_TXDAVL                    SDMMC_STA_TXDAVL
-#define SDMMC_FLAG_RXDAVL                    SDMMC_STA_RXDAVL
-#define SDMMC_FLAG_SDIOIT                    SDMMC_STA_SDIOIT
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
-  * @{
-  */
-  
-/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
-  * @brief SDMMC_LL registers bit address in the alias region
-  * @{
-  */
-/* ---------------------- SDMMC registers bit mask --------------------------- */
-/* --- CLKCR Register ---*/
-/* CLKCR register clear mask */ 
-#define CLKCR_CLEAR_MASK         ((uint32_t)(SDMMC_CLKCR_CLKDIV  | SDMMC_CLKCR_PWRSAV |\
-                                             SDMMC_CLKCR_BYPASS  | SDMMC_CLKCR_WIDBUS |\
-                                             SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN))
-
-/* --- DCTRL Register ---*/
-/* SDMMC DCTRL Clear Mask */
-#define DCTRL_CLEAR_MASK         ((uint32_t)(SDMMC_DCTRL_DTEN    | SDMMC_DCTRL_DTDIR |\
-                                             SDMMC_DCTRL_DTMODE  | SDMMC_DCTRL_DBLOCKSIZE))
-
-/* --- CMD Register ---*/
-/* CMD Register clear mask */
-#define CMD_CLEAR_MASK           ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\
-                                             SDMMC_CMD_WAITINT  | SDMMC_CMD_WAITPEND |\
-                                             SDMMC_CMD_CPSMEN   | SDMMC_CMD_SDIOSUSPEND))
-
-/* SDMMC Intialization Frequency (400KHz max) */
-#define SDMMC_INIT_CLK_DIV ((uint8_t)0x76)
-
-/* SDMMC Data Transfer Frequency (25MHz max) */
-#define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0)
-
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
- *  @brief macros to handle interrupts and specific clock configurations
- * @{
- */
- 
-/**
-  * @brief  Enable the SDMMC device.
-  * @param  __INSTANCE__: SDMMC Instance  
-  * @retval None
-  */ 
-#define __SDMMC_ENABLE(__INSTANCE__)  ((__INSTANCE__)->CLKCR |= SDMMC_CLKCR_CLKEN)
-
-/**
-  * @brief  Disable the SDMMC device.
-  * @param  __INSTANCE__: SDMMC Instance  
-  * @retval None
-  */
-#define __SDMMC_DISABLE(__INSTANCE__)  ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN)
-
-/**
-  * @brief  Enable the SDMMC DMA transfer.
-  * @param  None  
-  * @retval None
-  */ 
-#define __SDMMC_DMA_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_DMAEN)
-/**
-  * @brief  Disable the SDMMC DMA transfer.
-  * @param  None   
-  * @retval None
-  */
-#define __SDMMC_DMA_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN)
- 
-/**
-  * @brief  Enable the SDMMC device interrupt.
-  * @param  __INSTANCE__: Pointer to SDMMC register base  
-  * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
-  *         This parameter can be one or a combination of the following values:
-  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
-  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
-  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt
-  *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt
-  *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt
-  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
-  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
-  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt
-  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt
-  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt
-  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt
-  *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt
-  *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt   
-  * @retval None
-  */
-#define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the SDMMC device interrupt.
-  * @param  __INSTANCE__: Pointer to SDMMC register base   
-  * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
-  *          This parameter can be one or a combination of the following values:
-  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
-  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
-  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt
-  *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt
-  *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt
-  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
-  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
-  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt
-  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt
-  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt
-  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt
-  *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt
-  *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt   
-  * @retval None
-  */
-#define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
-
-/**
-  * @brief  Checks whether the specified SDMMC flag is set or not. 
-  * @param  __INSTANCE__: Pointer to SDMMC register base   
-  * @param  __FLAG__: specifies the flag to check. 
-  *          This parameter can be one of the following values:
-  *            @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
-  *            @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
-  *            @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
-  *            @arg SDMMC_FLAG_DTIMEOUT: Data timeout
-  *            @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
-  *            @arg SDMMC_FLAG_RXOVERR:  Received FIFO overrun error
-  *            @arg SDMMC_FLAG_CMDREND:  Command response received (CRC check passed)
-  *            @arg SDMMC_FLAG_CMDSENT:  Command sent (no response required)
-  *            @arg SDMMC_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
-  *            @arg SDMMC_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
-  *            @arg SDMMC_FLAG_CMDACT:   Command transfer in progress
-  *            @arg SDMMC_FLAG_TXACT:    Data transmit in progress
-  *            @arg SDMMC_FLAG_RXACT:    Data receive in progress
-  *            @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
-  *            @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
-  *            @arg SDMMC_FLAG_TXFIFOF:  Transmit FIFO full
-  *            @arg SDMMC_FLAG_RXFIFOF:  Receive FIFO full
-  *            @arg SDMMC_FLAG_TXFIFOE:  Transmit FIFO empty
-  *            @arg SDMMC_FLAG_RXFIFOE:  Receive FIFO empty
-  *            @arg SDMMC_FLAG_TXDAVL:   Data available in transmit FIFO
-  *            @arg SDMMC_FLAG_RXDAVL:   Data available in receive FIFO
-  *            @arg SDMMC_FLAG_SDMMCIT:   SD I/O interrupt received
-  * @retval The new state of SDMMC_FLAG (SET or RESET).
-  */
-#define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__)  (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
-
-
-/**
-  * @brief  Clears the SDMMC pending flags.
-  * @param  __INSTANCE__: Pointer to SDMMC register base  
-  * @param  __FLAG__: specifies the flag to clear.  
-  *          This parameter can be one or a combination of the following values:
-  *            @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
-  *            @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
-  *            @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
-  *            @arg SDMMC_FLAG_DTIMEOUT: Data timeout
-  *            @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
-  *            @arg SDMMC_FLAG_RXOVERR:  Received FIFO overrun error
-  *            @arg SDMMC_FLAG_CMDREND:  Command response received (CRC check passed)
-  *            @arg SDMMC_FLAG_CMDSENT:  Command sent (no response required)
-  *            @arg SDMMC_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
-  *            @arg SDMMC_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
-  *            @arg SDMMC_FLAG_SDMMCIT:   SD I/O interrupt received
-  * @retval None
-  */
-#define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__)  ((__INSTANCE__)->ICR = (__FLAG__))
-
-/**
-  * @brief  Checks whether the specified SDMMC interrupt has occurred or not.
-  * @param  __INSTANCE__: Pointer to SDMMC register base   
-  * @param  __INTERRUPT__: specifies the SDMMC interrupt source to check. 
-  *          This parameter can be one of the following values:
-  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
-  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
-  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt
-  *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt
-  *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt
-  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
-  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
-  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt
-  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt
-  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt
-  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt
-  *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt
-  *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt
-  * @retval The new state of SDMMC_IT (SET or RESET).
-  */
-#define __SDMMC_GET_IT(__INSTANCE__, __INTERRUPT__)  (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
-
-/**
-  * @brief  Clears the SDMMC's interrupt pending bits.
-  * @param  __INSTANCE__: Pointer to SDMMC register base 
-  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. 
-  *          This parameter can be one or a combination of the following values:
-  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
-  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt
-  * @retval None
-  */
-#define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->ICR = (__INTERRUPT__))
-
-/**
-  * @brief  Enable Start the SD I/O Read Wait operation.
-  * @param  __INSTANCE__: Pointer to SDMMC register base  
-  * @retval None
-  */  
-#define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART)
-
-/**
-  * @brief  Disable Start the SD I/O Read Wait operations.
-  * @param  __INSTANCE__: Pointer to SDMMC register base   
-  * @retval None
-  */  
-#define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART)
-
-/**
-  * @brief  Enable Start the SD I/O Read Wait operation.
-  * @param  __INSTANCE__: Pointer to SDMMC register base   
-  * @retval None
-  */  
-#define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP)
-
-/**
-  * @brief  Disable Stop the SD I/O Read Wait operations.
-  * @param  __INSTANCE__: Pointer to SDMMC register base  
-  * @retval None
-  */  
-#define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP)
-
-/**
-  * @brief  Enable the SD I/O Mode Operation.
-  * @param  __INSTANCE__: Pointer to SDMMC register base   
-  * @retval None
-  */  
-#define __SDMMC_OPERATION_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN) 
-
-/**
-  * @brief  Disable the SD I/O Mode Operation.
-  * @param  __INSTANCE__: Pointer to SDMMC register base 
-  * @retval None
-  */  
-#define __SDMMC_OPERATION_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN) 
-
-/**
-  * @brief  Enable the SD I/O Suspend command sending.
-  * @param  __INSTANCE__: Pointer to SDMMC register base  
-  * @retval None
-  */  
-#define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__)  ((__INSTANCE__)->CMD |= SDMMC_CMD_SDIOSUSPEND) 
-
-/**
-  * @brief  Disable the SD I/O Suspend command sending.
-  * @param  __INSTANCE__: Pointer to SDMMC register base  
-  * @retval None
-  */  
-#define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__)  ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND) 
-      
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */  
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SDMMC_LL_Exported_Functions
-  * @{
-  */
-  
-/* Initialization/de-initialization functions  **********************************/
-/** @addtogroup HAL_SDMMC_LL_Group1
-  * @{
-  */
-HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init);
-/**
-  * @}
-  */
-  
-/* I/O operation functions  *****************************************************/
-/** @addtogroup HAL_SDMMC_LL_Group2
-  * @{
-  */
-/* Blocking mode: Polling */
-uint32_t          SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx);
-HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData);
-/**
-  * @}
-  */
-  
-/* Peripheral Control functions  ************************************************/
-/** @addtogroup HAL_SDMMC_LL_Group3
-  * @{
-  */
-HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx);
-HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx);
-uint32_t          SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx);
-
-/* Command path state machine (CPSM) management functions */
-HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command);
-uint8_t           SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx);
-uint32_t          SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response);
-
-/* Data path state machine (DPSM) management functions */
-HAL_StatusTypeDef SDMMC_DataConfig(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data);
-uint32_t          SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx);
-uint32_t          SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx);
-
-/* SDMMC Cards mode management functions */
-HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode);
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L4xx_LL_SDMMC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/inc/stm32l4xx_ll_usb.h b/stmhal/hal/l4/inc/stm32l4xx_ll_usb.h
deleted file mode 100644
index 16e5efc125..0000000000
--- a/stmhal/hal/l4/inc/stm32l4xx_ll_usb.h
+++ /dev/null
@@ -1,468 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_ll_usb.h
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   Header file of USB Core HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L4xx_LL_USB_H
-#define __STM32L4xx_LL_USB_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-
-/** @addtogroup STM32L4xx_HAL
-  * @{
-  */
-
-/** @addtogroup USB_Core
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-
-/** 
-  * @brief  USB Mode definition  
-  */  
-typedef enum 
-{
-   USB_OTG_DEVICE_MODE  = 0,
-   USB_OTG_HOST_MODE    = 1,
-   USB_OTG_DRD_MODE     = 2
-   
-}USB_OTG_ModeTypeDef;
-
-/** 
-  * @brief  URB States definition  
-  */ 
-typedef enum {
-  URB_IDLE = 0,
-  URB_DONE,
-  URB_NOTREADY,
-  URB_NYET,
-  URB_ERROR,
-  URB_STALL
-    
-}USB_OTG_URBStateTypeDef;
-
-/** 
-  * @brief  Host channel States  definition  
-  */ 
-typedef enum {
-  HC_IDLE = 0,
-  HC_XFRC,
-  HC_HALTED,
-  HC_NAK,
-  HC_NYET,
-  HC_STALL,
-  HC_XACTERR,  
-  HC_BBLERR,   
-  HC_DATATGLERR
-    
-}USB_OTG_HCStateTypeDef;
-
-/** 
-  * @brief  PCD Initialization Structure definition  
-  */
-typedef struct
-{
-  uint32_t dev_endpoints;        /*!< Device Endpoints number.
-                                      This parameter depends on the used USB core.   
-                                      This parameter must be a number between Min_Data = 1 and Max_Data = 15 */    
-  
-  uint32_t Host_channels;        /*!< Host Channels number.
-                                      This parameter Depends on the used USB core.   
-                                      This parameter must be a number between Min_Data = 1 and Max_Data = 15 */       
-
-  uint32_t speed;                /*!< USB Core speed.
-                                      This parameter can be any value of @ref USB_Core_Speed_                */        
-                               
-  uint32_t dma_enable;           /*!< Enable or disable of the USB embedded DMA.                             */            
-
-  uint32_t ep0_mps;              /*!< Set the Endpoint 0 Max Packet size. 
-                                      This parameter can be any value of @ref USB_EP0_MPS_                   */              
-                       
-  uint32_t phy_itface;           /*!< Select the used PHY interface.
-                                      This parameter can be any value of @ref USB_Core_PHY_                  */ 
-                                
-  uint32_t Sof_enable;           /*!< Enable or disable the output of the SOF signal.                        */     
-                               
-  uint32_t low_power_enable;     /*!< Enable or disable the low power mode.                                  */     
-                          
-  uint32_t lpm_enable;           /*!< Enable or disable Battery charging.                                    */    
-
-  uint32_t battery_charging_enable; /*!< Enable or disable Battery charging.                                 */   
-  
-  uint32_t vbus_sensing_enable;  /*!< Enable or disable the VBUS Sensing feature.                            */ 
-
-  uint32_t use_dedicated_ep1;    /*!< Enable or disable the use of the dedicated EP1 interrupt.              */      
-  
-  uint32_t use_external_vbus;    /*!< Enable or disable the use of the external VBUS.                        */   
-  
-}USB_OTG_CfgTypeDef;
-
-typedef struct
-{
-  uint8_t   num;            /*!< Endpoint number
-                                This parameter must be a number between Min_Data = 1 and Max_Data = 15    */ 
-                                
-  uint8_t   is_in;          /*!< Endpoint direction
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 1     */ 
-  
-  uint8_t   is_stall;       /*!< Endpoint stall condition
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 1     */ 
-  
-  uint8_t   type;           /*!< Endpoint type
-                                 This parameter can be any value of @ref USB_EP_Type_                     */ 
-                                
-  uint8_t   data_pid_start; /*!< Initial data PID
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 1     */
-                                
-  uint8_t   even_odd_frame; /*!< IFrame parity
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 1    */
-                                
-  uint16_t  tx_fifo_num;    /*!< Transmission FIFO number
-                                 This parameter must be a number between Min_Data = 1 and Max_Data = 15   */
-                                
-  uint32_t  maxpacket;      /*!< Endpoint Max packet size
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
-
-  uint8_t   *xfer_buff;     /*!< Pointer to transfer buffer                                               */
-                                
-  uint32_t  dma_addr;       /*!< 32 bits aligned transfer buffer address                                  */
-  
-  uint32_t  xfer_len;       /*!< Current transfer length                                                  */
-  
-  uint32_t  xfer_count;     /*!< Partial transfer length in case of multi packet transfer                 */
-
-}USB_OTG_EPTypeDef;
-
-typedef struct
-{
-  uint8_t   dev_addr ;     /*!< USB device address.
-                                This parameter must be a number between Min_Data = 1 and Max_Data = 255    */ 
-
-  uint8_t   ch_num;        /*!< Host channel number.
-                                This parameter must be a number between Min_Data = 1 and Max_Data = 15     */ 
-                                
-  uint8_t   ep_num;        /*!< Endpoint number.
-                                This parameter must be a number between Min_Data = 1 and Max_Data = 15     */ 
-                                
-  uint8_t   ep_is_in;      /*!< Endpoint direction
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */ 
-                                
-  uint8_t   speed;         /*!< USB Host speed.
-                                This parameter can be any value of @ref USB_Core_Speed_                    */
-                                
-  uint8_t   do_ping;       /*!< Enable or disable the use of the PING protocol for HS mode.                */
-  
-  uint8_t   process_ping;  /*!< Execute the PING protocol for HS mode.                                     */
-
-  uint8_t   ep_type;       /*!< Endpoint Type.
-                                This parameter can be any value of @ref USB_EP_Type_                       */
-                                
-  uint16_t  max_packet;    /*!< Endpoint Max packet size.
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 64KB   */
-                                
-  uint8_t   data_pid;      /*!< Initial data PID.
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
-                                
-  uint8_t   *xfer_buff;    /*!< Pointer to transfer buffer.                                                */
-  
-  uint32_t  xfer_len;      /*!< Current transfer length.                                                   */
-  
-  uint32_t  xfer_count;    /*!< Partial transfer length in case of multi packet transfer.                  */
-  
-  uint8_t   toggle_in;     /*!< IN transfer current toggle flag.
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
-                                
-  uint8_t   toggle_out;    /*!< OUT transfer current toggle flag
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
-  
-  uint32_t  dma_addr;      /*!< 32 bits aligned transfer buffer address.                                   */
-  
-  uint32_t  ErrCnt;        /*!< Host channel error count.*/
-  
-  USB_OTG_URBStateTypeDef  urb_state;  /*!< URB state. 
-                                           This parameter can be any value of @ref USB_OTG_URBStateTypeDef */ 
-  
-  USB_OTG_HCStateTypeDef   state;     /*!< Host Channel state. 
-                                           This parameter can be any value of @ref USB_OTG_HCStateTypeDef  */ 
-                                             
-}USB_OTG_HCTypeDef;
-  
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup PCD_Exported_Constants PCD Exported Constants
-  * @{
-  */
-
-/** @defgroup USB_Core_Mode_ USB Core Mode
-  * @{
-  */
-#define USB_OTG_MODE_DEVICE                    0
-#define USB_OTG_MODE_HOST                      1
-#define USB_OTG_MODE_DRD                       2
-/**
-  * @}
-  */
-
-/** @defgroup USB_Core_Speed_   USB Core Speed
-  * @{
-  */  
-#define USB_OTG_SPEED_HIGH                     0
-#define USB_OTG_SPEED_HIGH_IN_FULL             1
-#define USB_OTG_SPEED_LOW                      2  
-#define USB_OTG_SPEED_FULL                     3
-/**
-  * @}
-  */
-  
-/** @defgroup USB_Core_PHY_   USB Core PHY
-  * @{
-  */   
-#define USB_OTG_EMBEDDED_PHY                   1
-/**
-  * @}
-  */
-  
-/** @defgroup USB_Core_MPS_   USB Core MPS
-  * @{
-  */
-#define USB_OTG_FS_MAX_PACKET_SIZE           64
-#define USB_OTG_MAX_EP0_SIZE                 64
-/**
-  * @}
-  */
-
-/** @defgroup USB_Core_Phy_Frequency_   USB Core Phy Frequency
-  * @{
-  */
-#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ     (0 << 1)
-#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ     (1 << 1)
-#define DSTS_ENUMSPD_LS_PHY_6MHZ               (2 << 1)
-#define DSTS_ENUMSPD_FS_PHY_48MHZ              (3 << 1)
-/**
-  * @}
-  */
-  
-/** @defgroup USB_CORE_Frame_Interval_   USB CORE Frame Interval
-  * @{
-  */  
-#define DCFG_FRAME_INTERVAL_80                 0
-#define DCFG_FRAME_INTERVAL_85                 1
-#define DCFG_FRAME_INTERVAL_90                 2
-#define DCFG_FRAME_INTERVAL_95                 3
-/**
-  * @}
-  */
-
-/** @defgroup USB_EP0_MPS_  USB EP0 MPS
-  * @{
-  */
-#define DEP0CTL_MPS_64                         0
-#define DEP0CTL_MPS_32                         1
-#define DEP0CTL_MPS_16                         2
-#define DEP0CTL_MPS_8                          3
-/**
-  * @}
-  */
-
-/** @defgroup USB_EP_Speed_  USB EP Speed
-  * @{
-  */
-#define EP_SPEED_LOW                           0
-#define EP_SPEED_FULL                          1
-#define EP_SPEED_HIGH                          2
-/**
-  * @}
-  */
-
-/** @defgroup USB_EP_Type_  USB EP Type
-  * @{
-  */
-#define EP_TYPE_CTRL                           0
-#define EP_TYPE_ISOC                           1
-#define EP_TYPE_BULK                           2
-#define EP_TYPE_INTR                           3
-#define EP_TYPE_MSK                            3
-/**
-  * @}
-  */
-
-/** @defgroup USB_STS_Defines_   USB STS Defines
-  * @{
-  */
-#define STS_GOUT_NAK                           1
-#define STS_DATA_UPDT                          2
-#define STS_XFER_COMP                          3
-#define STS_SETUP_COMP                         4
-#define STS_SETUP_UPDT                         6
-/**
-  * @}
-  */
-
-/** @defgroup HCFG_SPEED_Defines_   HCFG SPEED Defines
-  * @{
-  */  
-#define HCFG_30_60_MHZ                         0
-#define HCFG_48_MHZ                            1
-#define HCFG_6_MHZ                             2
-/**
-  * @}
-  */
-    
-/** @defgroup HPRT0_PRTSPD_SPEED_Defines_  HPRT0 PRTSPD SPEED Defines
-  * @{
-  */    
-#define HPRT0_PRTSPD_HIGH_SPEED                0
-#define HPRT0_PRTSPD_FULL_SPEED                1
-#define HPRT0_PRTSPD_LOW_SPEED                 2
-/**
-  * @}
-  */  
-   
-#define HCCHAR_CTRL                            0
-#define HCCHAR_ISOC                            1
-#define HCCHAR_BULK                            2
-#define HCCHAR_INTR                            3
-       
-#define HC_PID_DATA0                           0
-#define HC_PID_DATA2                           1
-#define HC_PID_DATA1                           2
-#define HC_PID_SETUP                           3
-
-#define GRXSTS_PKTSTS_IN                       2
-#define GRXSTS_PKTSTS_IN_XFER_COMP             3
-#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR          5
-#define GRXSTS_PKTSTS_CH_HALTED                7
-    
-#define USBx_PCGCCTL    *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_PCGCCTL_BASE)
-#define USBx_HPRT0      *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_HOST_PORT_BASE)
-
-#define USBx_DEVICE     ((USB_OTG_DeviceTypeDef *)((uint32_t )USBx + USB_OTG_DEVICE_BASE)) 
-#define USBx_INEP(i)    ((USB_OTG_INEndpointTypeDef *)((uint32_t)USBx + USB_OTG_IN_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE))        
-#define USBx_OUTEP(i)   ((USB_OTG_OUTEndpointTypeDef *)((uint32_t)USBx + USB_OTG_OUT_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE))        
-#define USBx_DFIFO(i)   *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_FIFO_BASE + (i) * USB_OTG_FIFO_SIZE)
-
-#define USBx_HOST       ((USB_OTG_HostTypeDef *)((uint32_t )USBx + USB_OTG_HOST_BASE))  
-#define USBx_HC(i)      ((USB_OTG_HostChannelTypeDef *)((uint32_t)USBx + USB_OTG_HOST_CHANNEL_BASE + (i)*USB_OTG_HOST_CHANNEL_SIZE))
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__)     ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))
-#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__)   ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))
-    
-#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__)          (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))
-#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__)         (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))  
-
-/* Exported functions --------------------------------------------------------*/
-HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
-HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
-HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode);
-HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed);
-HAL_StatusTypeDef USB_FlushRxFifo (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num );
-HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma);
-HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma);
-HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma);
-void *            USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
-HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address);
-HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup);
-uint8_t           USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);
-uint32_t          USB_GetMode(USB_OTG_GlobalTypeDef *USBx);
-uint32_t          USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx);
-uint32_t          USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx);
-uint32_t          USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);
-uint32_t          USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx);
-uint32_t          USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);
-void              USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
-
-HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
-HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq);
-HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state);
-uint32_t          USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx);
-uint32_t          USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,  
-                                  uint8_t ch_num,
-                                  uint8_t epnum,
-                                  uint8_t dev_address,
-                                  uint8_t speed,
-                                  uint8_t ep_type,
-                                  uint16_t mps);
-HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma);
-uint32_t          USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num);
-HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num);
-HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
-  
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32L4xx_LL_USB_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/src/stm32l4xx_hal.c b/stmhal/hal/l4/src/stm32l4xx_hal.c
deleted file mode 100644
index c8a4a44aef..0000000000
--- a/stmhal/hal/l4/src/stm32l4xx_hal.c
+++ /dev/null
@@ -1,660 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal.c
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   HAL module driver.
-  *          This is the common part of the HAL initialization
-  *
-  @verbatim
-  ==============================================================================
-                     ##### How to use this driver #####
-  ==============================================================================
-    [..]
-    The common HAL driver contains a set of generic and common APIs that can be
-    used by the PPP peripheral drivers and the user to start using the HAL.
-    [..]
-    The HAL contains two APIs' categories:
-         (+) Common HAL APIs
-         (+) Services HAL APIs
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup HAL HAL
-  * @brief HAL module driver
-  * @{
-  */
-
-#ifdef HAL_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/**
- * @brief STM32L4xx HAL Driver version number V1.3.0
-   */
-#define __STM32L4xx_HAL_VERSION_MAIN   (0x01) /*!< [31:24] main version */
-#define __STM32L4xx_HAL_VERSION_SUB1   (0x03) /*!< [23:16] sub1 version */
-#define __STM32L4xx_HAL_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
-#define __STM32L4xx_HAL_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
-#define __STM32L4xx_HAL_VERSION         ((__STM32L4xx_HAL_VERSION_MAIN << 24)\
-                                        |(__STM32L4xx_HAL_VERSION_SUB1 << 16)\
-                                        |(__STM32L4xx_HAL_VERSION_SUB2 << 8 )\
-                                        |(__STM32L4xx_HAL_VERSION_RC))
-
-#if defined(VREFBUF)
-#define VREFBUF_TIMEOUT_VALUE     (uint32_t)10   /* 10 ms (to be confirmed) */
-#endif /* VREFBUF */
-
-/* ------------ SYSCFG registers bit address in the alias region ------------ */
-#define SYSCFG_OFFSET             (SYSCFG_BASE - PERIPH_BASE)
-/* ---  MEMRMP Register ---*/
-/* Alias word address of FB_MODE bit */
-#define MEMRMP_OFFSET             SYSCFG_OFFSET
-#define FB_MODE_BitNumber         ((uint8_t)0x8)
-#define FB_MODE_BB                (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (FB_MODE_BitNumber * 4))
-
-/* --- SCSR Register ---*/
-/* Alias word address of SRAM2ER bit */
-#define SCSR_OFFSET              (SYSCFG_OFFSET + 0x18)
-#define BRER_BitNumber           ((uint8_t)0x0)
-#define SCSR_SRAM2ER_BB          (PERIPH_BB_BASE + (SCSR_OFFSET * 32) + (BRER_BitNumber * 4))
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-__IO uint32_t uwTick;
-
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup HAL_Exported_Functions HAL Exported Functions
-  * @{
-  */
-
-/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
- *  @brief    Initialization and de-initialization functions
- *
-@verbatim
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Initialize the Flash interface the NVIC allocation and initial time base
-          clock configuration.
-      (+) De-initialize common part of the HAL.
-      (+) Configure the time base source to have 1ms time base with a dedicated
-          Tick interrupt priority.
-        (++) SysTick timer is used by default as source of time base, but user
-             can eventually implement his proper time base source (a general purpose
-             timer for example or other time source), keeping in mind that Time base
-             duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
-             handled in milliseconds basis.
-        (++) Time base configuration function (HAL_InitTick ()) is called automatically
-             at the beginning of the program after reset by HAL_Init() or at any time
-             when clock is configured, by HAL_RCC_ClockConfig().
-        (++) Source of time base is configured  to generate interrupts at regular
-             time intervals. Care must be taken if HAL_Delay() is called from a
-             peripheral ISR process, the Tick interrupt line must have higher priority
-            (numerically lower) than the peripheral interrupt. Otherwise the caller
-            ISR process will be blocked.
-       (++) functions affecting time base configurations are declared as __weak
-             to make  override possible  in case of other  implementations in user file.
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configure the Flash prefetch, the Instruction and Data caches,
-  *         the time base source, NVIC and any required global low level hardware 
-  *         by calling the HAL_MspInit() callback function to be optionally defined in user file 
-  *         stm32l4xx_hal_msp.c.
-  *
-  * @note   HAL_Init() function is called at the beginning of program after reset and before 
-  *         the clock configuration.
-  *             
-  * @note   In the default implementation the System Timer (Systick) is used as source of time base.
-  *         The Systick configuration is based on MSI clock, as MSI is the clock
-  *         used after a system Reset and the NVIC configuration is set to Priority group 4.
-  *         Once done, time base tick starts incrementing: the tick variable counter is incremented 
-  *         each 1ms in the SysTick_Handler() interrupt handler.
-  *
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_Init(void)
-{
-  /* Configure Flash prefetch, Instruction cache, Data cache */
-  /* Default configuration at reset is:                      */
-  /* - Prefetch disabled                                     */
-  /* - Instruction cache enabled                             */
-  /* - Data cache enabled                                    */
-#if (INSTRUCTION_CACHE_ENABLE == 0)
-   __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
-#endif /* INSTRUCTION_CACHE_ENABLE */
-
-#if (DATA_CACHE_ENABLE == 0)
-   __HAL_FLASH_DATA_CACHE_DISABLE();
-#endif /* DATA_CACHE_ENABLE */
-
-#if (PREFETCH_ENABLE != 0)
-  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
-#endif /* PREFETCH_ENABLE */
-
-  /* Set Interrupt Group Priority */
-  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
-
-  /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */
-  HAL_InitTick(TICK_INT_PRIORITY);
-
-  /* Init the low level hardware */
-  HAL_MspInit();
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief De-initialize common part of the HAL and stop the source of time base.
-  * @note This function is optional.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DeInit(void)
-{
-  /* Reset of all peripherals */
-  __HAL_RCC_APB1_FORCE_RESET();
-  __HAL_RCC_APB1_RELEASE_RESET();
-
-  __HAL_RCC_APB2_FORCE_RESET();
-  __HAL_RCC_APB2_RELEASE_RESET();
-
-  __HAL_RCC_AHB1_FORCE_RESET();
-  __HAL_RCC_AHB1_RELEASE_RESET();
-
-  __HAL_RCC_AHB2_FORCE_RESET();
-  __HAL_RCC_AHB2_RELEASE_RESET();
-
-  __HAL_RCC_AHB3_FORCE_RESET();
-  __HAL_RCC_AHB3_RELEASE_RESET();
-
-  /* De-Init the low level hardware */
-  HAL_MspDeInit();
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initialize the MSP.
-  * @retval None
-  */
-__weak void HAL_MspInit(void)
-{
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitialize the MSP.
-  * @retval None
-  */
-__weak void HAL_MspDeInit(void)
-{
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief This function configures the source of the time base:
-  *        The time source is configured to have 1ms time base with a dedicated
-  *        Tick interrupt priority.
-  * @note This function is called  automatically at the beginning of program after
-  *       reset by HAL_Init() or at any time when clock is reconfigured  by HAL_RCC_ClockConfig().
-  * @note In the default implementation, SysTick timer is the source of time base.
-  *       It is used to generate interrupts at regular time intervals.
-  *       Care must be taken if HAL_Delay() is called from a peripheral ISR process,
-  *       The SysTick interrupt must have higher priority (numerically lower)
-  *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
-  *       The function is declared as __weak  to be overwritten  in case of other
-  *       implementation  in user file.
-  * @param TickPriority: Tick interrupt priority.
-  * @retval HAL status
-  */
-__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
-{
-  /*Configure the SysTick to have interrupt in 1ms time basis*/
-  HAL_SYSTICK_Config(SystemCoreClock/1000);
-
-  /*Configure the SysTick IRQ priority */
-  HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
- *  @brief    HAL Control functions
- *
-@verbatim
- ===============================================================================
-                      ##### HAL Control functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Provide a tick value in millisecond
-      (+) Provide a blocking delay in millisecond
-      (+) Suspend the time base source interrupt
-      (+) Resume the time base source interrupt
-      (+) Get the HAL API driver version
-      (+) Get the device identifier
-      (+) Get the device revision identifier
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief This function is called to increment a global variable "uwTick"
-  *        used as application time base.
-  * @note In the default implementation, this variable is incremented each 1ms
-  *       in SysTick ISR.
- * @note This function is declared as __weak to be overwritten in case of other
-  *      implementations in user file.
-  * @retval None
-  */
-__weak void HAL_IncTick(void)
-{
-  uwTick++;
-}
-
-/**
-  * @brief Provide a tick value in millisecond.
-  * @note This function is declared as __weak to be overwritten in case of other
-  *       implementations in user file.
-  * @retval tick value
-  */
-__weak uint32_t HAL_GetTick(void)
-{
-  return uwTick;
-}
-
-/**
-  * @brief Provide accurate delay (in milliseconds) based on variable incremented.
-  * @note In the default implementation , SysTick timer is the source of time base.
-  *       It is used to generate interrupts at regular time intervals where uwTick
-  *       is incremented.
-  * @note This function is declared as __weak to be overwritten in case of other
-  *       implementations in user file.
-  * @param Delay: specifies the delay time length, in milliseconds.
-  * @retval None
-  */
-__weak void HAL_Delay(uint32_t Delay)
-{
-  uint32_t tickstart = 0;
-  tickstart = HAL_GetTick();
-  while((HAL_GetTick() - tickstart) < Delay)
-  {
-  }
-}
-
-/**
-  * @brief Suspend Tick increment.
-  * @note In the default implementation , SysTick timer is the source of time base. It is
-  *       used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
-  *       is called, the SysTick interrupt will be disabled and so Tick increment
-  *       is suspended.
-  * @note This function is declared as __weak to be overwritten in case of other
-  *       implementations in user file.
-  * @retval None
-  */
-__weak void HAL_SuspendTick(void)
-{
-  /* Disable SysTick Interrupt */
-  SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
-}
-
-/**
-  * @brief Resume Tick increment.
-  * @note In the default implementation , SysTick timer is the source of time base. It is
-  *       used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
-  *       is called, the SysTick interrupt will be enabled and so Tick increment
-  *       is resumed.
-  * @note This function is declared as __weak to be overwritten in case of other
-  *       implementations in user file.
-  * @retval None
-  */
-__weak void HAL_ResumeTick(void)
-{
-  /* Enable SysTick Interrupt */
-  SysTick->CTRL  |= SysTick_CTRL_TICKINT_Msk;
-}
-
-/**
-  * @brief  Return the HAL revision.
-  * @retval version : 0xXYZR (8bits for each decimal, R for RC)
-  */
-uint32_t HAL_GetHalVersion(void)
-{
- return __STM32L4xx_HAL_VERSION;
-}
-
-/**
-  * @brief  Return the device revision identifier.
-  * @retval Device revision identifier
-  */
-uint32_t HAL_GetREVID(void)
-{
-   return((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> 16);
-}
-
-/**
-  * @brief  Return the device identifier.
-  * @retval Device identifier
-  */
-uint32_t HAL_GetDEVID(void)
-{
-   return(DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions
- *  @brief    HAL Debug functions
- *
-@verbatim
- ===============================================================================
-                      ##### HAL Debug functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Enable/Disable Debug module during SLEEP mode
-      (+) Enable/Disable Debug module during STOP0/STOP1/STOP2 modes
-      (+) Enable/Disable Debug module during STANDBY mode
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enable the Debug Module during SLEEP mode.
-  * @retval None
-  */
-void HAL_DBGMCU_EnableDBGSleepMode(void)
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
-  * @brief  Disable the Debug Module during SLEEP mode.
-  * @retval None
-  */
-void HAL_DBGMCU_DisableDBGSleepMode(void)
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
-  * @brief  Enable the Debug Module during STOP0/STOP1/STOP2 modes.
-  * @retval None
-  */
-void HAL_DBGMCU_EnableDBGStopMode(void)
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
-}
-
-/**
-  * @brief  Disable the Debug Module during STOP0/STOP1/STOP2 modes.
-  * @retval None
-  */
-void HAL_DBGMCU_DisableDBGStopMode(void)
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
-}
-
-/**
-  * @brief  Enable the Debug Module during STANDBY mode.
-  * @retval None
-  */
-void HAL_DBGMCU_EnableDBGStandbyMode(void)
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
-}
-
-/**
-  * @brief  Disable the Debug Module during STANDBY mode.
-  * @retval None
-  */
-void HAL_DBGMCU_DisableDBGStandbyMode(void)
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_Exported_Functions_Group4 HAL SYSCFG configuration functions
- *  @brief    HAL SYSCFG configuration functions
- *
-@verbatim
- ===============================================================================
-                      ##### HAL SYSCFG configuration functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Start a hardware SRAM2 erase operation
-      (+) Enable/Disable the Internal FLASH Bank Swapping
-      (+) Configure the Voltage reference buffer
-      (+) Enable/Disable the Voltage reference buffer
-      (+) Enable/Disable the I/O analog switch voltage booster
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Start a hardware SRAM2 erase operation.
-  * @note   As long as SRAM2 is not erased the SRAM2ER bit will be set.
-  *         This bit is automatically reset at the end of the SRAM2 erase operation.
-  * @retval None
-  */
-void HAL_SYSCFG_SRAM2Erase(void)
-{
-  /* unlock the write protection of the SRAM2ER bit */
-  SYSCFG->SKR = 0xCA;
-  SYSCFG->SKR = 0x53;
-  /* Starts a hardware SRAM2 erase operation*/
-  *(__IO uint32_t *) SCSR_SRAM2ER_BB = (uint8_t)0x00000001;
-}
-
-/**
-  * @brief  Enable the Internal FLASH Bank Swapping.
-  *
-  * @note   This function can be used only for STM32L4xx devices.
-  *
-  * @note   Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000)
-  *         and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000)
-  *
-  * @retval None
-  */
-void HAL_SYSCFG_EnableMemorySwappingBank(void)
-{
-  *(__IO uint32_t *)FB_MODE_BB = (uint32_t)ENABLE;
-}
-
-/**
-  * @brief  Disable the Internal FLASH Bank Swapping.
-  *
-  * @note   This function can be used only for STM32L4xx devices.
-  *
-  * @note   The default state : Flash Bank1 mapped at 0x08000000 (and aliased @0x0000 0000)
-  *         and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000)
-  *
-  * @retval None
-  */
-void HAL_SYSCFG_DisableMemorySwappingBank(void)
-{
-
-  *(__IO uint32_t *)FB_MODE_BB = (uint32_t)DISABLE;
-}
-
-#if defined(VREFBUF)
-/**
-  * @brief Configure the internal voltage reference buffer voltage scale.
-  * @param  VoltageScaling: specifies the output voltage to achieve
-  *          This parameter can be one of the following values:
-  *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.048 V. 
-  *                                                This requires VDDA equal to or higher than 2.4 V.
-  *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT1 around 2.5 V. 
-  *                                                This requires VDDA equal to or higher than 2.8 V.
-  * @retval None
-  */
-void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling)
-{
-  /* Check the parameters */
-  assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling));
-  
-  MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling);
-}
-
-/**
-  * @brief Configure the internal voltage reference buffer high impedance mode.
-  * @param  Mode: specifies the high impedance mode
-  *          This parameter can be one of the following values:
-  *            @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output.
-  *            @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance.
-  * @retval None
-  */
-void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode)
-{
-  /* Check the parameters */
-  assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode));
-  
-  MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode);
-}
-
-/**
-  * @brief  Tune the Internal Voltage Reference buffer (VREFBUF).
-  * @retval None
-  */
-void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue)
-{
-  /* Check the parameters */
-  assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue));
-  
-  MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue);
-}
-
-/**
-  * @brief  Enable the Internal Voltage Reference buffer (VREFBUF).
-  * @retval HAL_OK/HAL_TIMEOUT
-  */
-HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void)
-{
-  uint32_t  tickstart = 0;
-  
-  SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
-  
-  /* Get Start Tick*/
-  tickstart = HAL_GetTick();
-
-  /* Wait for VRR bit  */
-  while(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == RESET)
-  {
-    if((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE)
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disable the Internal Voltage Reference buffer (VREFBUF).
-  *
-  * @retval None
-  */
-void HAL_SYSCFG_DisableVREFBUF(void)
-{
-  CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
-}
-#endif /* VREFBUF */
-
-/**
-  * @brief  Enable the I/O analog switch voltage booster
-  *
-  * @retval None
-  */
-void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void)
-{
-  SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
-}
-
-/**
-  * @brief  Disable the I/O analog switch voltage booster
-  *
-  * @retval None
-  */
-void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void)
-{
-  CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/src/stm32l4xx_hal_adc.c b/stmhal/hal/l4/src/stm32l4xx_hal_adc.c
deleted file mode 100644
index 0d2f29ff69..0000000000
--- a/stmhal/hal/l4/src/stm32l4xx_hal_adc.c
+++ /dev/null
@@ -1,2992 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_adc.c
-  * @author  MCD Application conversion
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   This file provides firmware functions to manage the following 
-  *          functionalities of the Analog to Digital Convertor (ADC)
-  *          peripheral:
-  *           + Initialization and de-initialization functions
-  *             ++ Configuration of ADC
-  *           + Operation functions
-  *             ++ Start, stop, get result of regular conversions of regular 
-  *                using 3 possible modes: polling, interruption or DMA.
-  *           + Control functions
-  *             ++ Analog Watchdog configuration
-  *             ++ Channels configuration on regular group
-  *           + State functions
-  *             ++ ADC state machine management
-  *             ++ Interrupts and flags management
-  *     
-   @verbatim      
-  ==============================================================================
-                    ##### ADC specific features #####
-  ==============================================================================
-  [..] 
-  (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
-
-  (#) Interrupt generation at the end of regular conversion and in case of 
-      analog watchdog and overrun events.
-  
-  (#) Single and continuous conversion modes.
-  
-  (#) Scan mode for automatic conversion of channel 0 to channel 'n'.
-  
-  (#) Data alignment with in-built data coherency.
-  
-  (#) Channel-wise programmable sampling time.
-
-  (#) External trigger (timer or EXTI) with configurable polarity for  
-      regular groups.
-
-  (#) DMA request generation for transfer of regular group converted data.
-  
-  (#) Configurable delay between conversions in Dual interleaved mode.
-
-  (#) ADC channels selectable single/differential input.
-
-  (#) ADC offset on regular groups.
-
-  (#) ADC supply requirements: 1.62 V to 3.6 V.
-  
-  (#) ADC input range: from Vref_ (connected to Vssa) to Vref+ (connected to 
-      Vdda or to an external voltage reference).
-      
-
-
-                     ##### How to use this driver #####
-  ==============================================================================
-    [..]
-
-    (#) Enable the ADC interface 
-        As prerequisite, in HAL_ADC_MspInit(), ADC clock source must be  
-        configured at RCC top level.
-
-        Two different clock sources are available:
-        (++) - the ADC clock can be a specific clock source, coming from the system 
-        clock, the PLLSAI1 or the PLLSAI2 running up to 80MHz.
-        (++) - or the ADC clock can be derived from the AHB clock of the ADC bus 
-       interface, divided by a programmable factor
-
-
-        (++) For example, in case of PLLSAI2:
-            (+++) __HAL_RCC_ADC_CLK_ENABLE();
-            (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
-            (+++) where
-              (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC
-              (+++) PeriphClkInit.AdcClockSelection    = RCC_ADCCLKSOURCE_PLLSAI2
-
-                      
-    (#) ADC pins configuration
-         (++) Enable the clock for the ADC GPIOs using the following function:
-             __HAL_RCC_GPIOx_CLK_ENABLE();   
-         (++) Configure these ADC pins in analog mode using HAL_GPIO_Init();  
-  
-    (#) Configure the ADC parameters (conversion resolution, data alignment,  
-         continuous mode, ...) using the HAL_ADC_Init() function.
-         
-    (#) Optionally, perform an automatic ADC calibration to improve the
-        conversion accuracy using function HAL_ADCEx_Calibration_Start().
-
-    (#) Activate the ADC peripheral using one of the start functions: 
-        HAL_ADC_Start(), HAL_ADC_Start_IT(), HAL_ADC_Start_DMA(),
-        HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT() or 
-        HAL_ADCEx_MultiModeStart_DMA() when multimode feature is available.
-  
-   *** Channels to regular group configuration ***
-     ============================================
-     [..]    
-       (+) To configure the ADC regular group features, use 
-           HAL_ADC_Init() and HAL_ADC_ConfigChannel() functions.
-       (+) To activate the continuous mode, use the HAL_ADC_Init() function.   
-       (+) To read the ADC converted values, use the HAL_ADC_GetValue() function.
-  
-     *** DMA for regular configuration ***
-     ============================================================= 
-     [..]
-       (+) To enable the DMA mode for regular group, use the  
-           HAL_ADC_Start_DMA() function.
-       (+) To enable the generation of DMA requests continuously at the end of 
-           the last DMA transfer, resort to DMAContinuousRequests parameter of 
-           ADC handle initialization structure.
-  
-
-  
-    @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************  
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup ADC ADC
-  * @brief ADC HAL module driver
-  * @{
-  */ 
-
-#ifdef HAL_ADC_MODULE_ENABLED
-    
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/** @defgroup ADC_Private_Constants ADC Private Constants
-  * @{                                                         
-  */
-  
-#define ADC_CFGR_FIELDS_1  ((uint32_t)(ADC_CFGR_RES    | ADC_CFGR_ALIGN   |\
-                                       ADC_CFGR_CONT   | ADC_CFGR_OVRMOD  |\
-                                       ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\
-                                       ADC_CFGR_EXTEN  | ADC_CFGR_EXTSEL))   /*!< ADC_CFGR fields of parameters that can be updated 
-                                                                                  when no regular conversion is on-going */
-                                      
-#define ADC_CFGR2_FIELDS  ((uint32_t)(ADC_CFGR2_ROVSE | ADC_CFGR2_OVSR  |\
-                                       ADC_CFGR2_OVSS | ADC_CFGR2_TROVS |\
-                                       ADC_CFGR2_ROVSM))                     /*!< ADC_CFGR2 fields of parameters that can be updated when no conversion
-                                                                                 (neither regular nor injected) is on-going  */
-
-#define ADC_CFGR_WD_FIELDS  ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN | \
-                                        ADC_CFGR_AWD1EN | ADC_CFGR_AWD1CH))  /*!< ADC_CFGR fields of Analog Watchdog parameters that can be updated when no
-                                                                                  conversion (neither regular nor injected) is on-going  */
-  
-#define ADC_OFR_FIELDS  ((uint32_t)(ADC_OFR1_OFFSET1 | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1_EN)) /*!< ADC_OFR fields of parameters that can be updated when no conversion
-                                                                                                        (neither regular nor injected) is on-going */
-
-
-  
-/* Delay to wait before setting ADEN once ADCAL has been reset
-   must be at least 4 ADC clock cycles.
-   Assuming lowest ADC clock (140 KHz according to DS), this
-   4 ADC clock cycles duration is equal to
-   4 / 140,000 = 0.028 ms.
-   ADC_ENABLE_TIMEOUT set to 2 is a margin large enough to ensure
-   the 4 ADC clock cycles have elapsed while waiting for ADRDY
-   to become 1 */        
-  #define ADC_ENABLE_TIMEOUT              ((uint32_t)  2)    /*!< ADC enable time-out value  */
-  #define ADC_DISABLE_TIMEOUT             ((uint32_t)  2)    /*!< ADC disable time-out value */
-   
-    
-                                                                            
-/* Delay for ADC voltage regulator startup time                               */
-/*  Maximum delay is 10 microseconds                                          */
-/* (refer device RM, parameter Tadcvreg_stup).                                */
-#define ADC_STAB_DELAY_US               ((uint32_t) 10)     /*!< ADC voltage regulator startup time */
-  
-  
-/* Timeout to wait for current conversion on going to be completed.           */
-/* Timeout fixed to worst case, for 1 channel.                                */
-/*   - maximum sampling time (640.5 adc_clk)                                  */
-/*   - ADC resolution (Tsar 12 bits= 12.5 adc_clk)                            */
-/*   - ADC clock with prescaler 256                                           */
-/*     653 * 256 = 167168 clock cycles max                                    */
-/* Unit: cycles of CPU clock.                                                 */
-#define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 167168)  /*!< ADC conversion completion time-out value */
-  
-  
-
-  
-/**
-  * @}
-  */  
-  
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup ADC_Exported_Functions ADC Exported Functions
-  * @{
-  */ 
-
-/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @brief    Initialization and Configuration functions 
- *
-@verbatim    
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Initialize and configure the ADC. 
-      (+) De-initialize the ADC. 
-         
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initialize the ADC peripheral and regular group according to  
-  *         parameters specified in structure "ADC_InitTypeDef".
-  * @note   As prerequisite, ADC clock must be configured at RCC top level
-  *         depending on possible clock sources: System/PLLSAI1/PLLSAI2 clocks 
-  *         or AHB clock.
-  * @note   Possibility to update parameters on the fly:
-  *         this function initializes the ADC MSP (HAL_ADC_MspInit()) only when
-  *         coming from ADC state reset. Following calls to this function can
-  *         be used to reconfigure some parameters of ADC_InitTypeDef  
-  *         structure on the fly, without modifying MSP configuration. If ADC  
-  *         MSP has to be modified again, HAL_ADC_DeInit() must be called
-  *         before HAL_ADC_Init().
-  *         The setting of these parameters is conditioned by ADC state.
-  *         For parameters constraints, see comments of structure 
-  *         "ADC_InitTypeDef".
-  * @note   This function configures the ADC within 2 scopes: scope of entire 
-  *         ADC and scope of regular group. For parameters details, see comments 
-  *         of structure "ADC_InitTypeDef".
-  * @note   Parameters related to common ADC registers (ADC clock mode) are set 
-  *         only if all ADCs are disabled.
-  *         If this is not the case, these common parameters setting are  
-  *         bypassed without error reporting: it can be the intended behaviour in
-  *         case of update of a parameter of ADC_InitTypeDef on the fly,
-  *         without  disabling the other ADCs.
-  * @param  hadc: ADC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmp_status = HAL_OK;
-
-  ADC_Common_TypeDef *tmpADC_Common;
-  uint32_t tmpCFGR = 0;
-  uint32_t wait_loop_index = 0;
-  
-  /* Check ADC handle */
-  if(hadc == NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); 
-  assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
-  assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); 
-  assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
-  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
-  assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
-  assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
-  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
-  assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
-  assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
-  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
-  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
-  
-  if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
-  {
-    assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
-    assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
-    
-    if (hadc->Init.DiscontinuousConvMode == ENABLE)
-    { 
-      assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
-    }
-  }
-
-  
-  /* DISCEN and CONT bits can't be set at the same time */
-  assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
- 
-  
-  /* Actions performed only if ADC is coming from state reset:                */
-  /* - Initialization of ADC MSP                                              */
-  if (hadc->State == HAL_ADC_STATE_RESET)
-  {
-    /* Init the low level hardware */
-    HAL_ADC_MspInit(hadc);
-    
-    /* Set ADC error code to none */
-    ADC_CLEAR_ERRORCODE(hadc);
-    
-    /* Initialize Lock */
-    hadc->Lock = HAL_UNLOCKED;
-  }
-    
-    
-  /* - Exit from deep-power-down mode and ADC voltage regulator enable        */    
-  /*  Exit deep power down mode if still in that state */
-  if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_DEEPPWD))
-  {
-    /* Exit deep power down mode */ 
-    CLEAR_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
-    
-    /* System was in deep power down mode, calibration must
-     be relaunched or a previously saved calibration factor 
-     re-applied once the ADC voltage regulator is enabled */    
-  }
-  
-
-  if  (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
-  {  
-    /* Enable ADC internal voltage regulator  then 
-     wait for start-up time */
-    SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN);
-    wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
-    while(wait_loop_index != 0)
-    {
-      wait_loop_index--;
-    }    
-  }
-
-
- 
-  
-  /* Verification that ADC voltage regulator is correctly enabled, whether    */
-  /* or not ADC is coming from state reset (if any potential problem of       */
-  /* clocking, voltage regulator would not be enabled).                       */
-  if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))  
-  {
-    /* Update ADC state machine to error */
-    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-    
-    /* Set ADC error code to ADC IP internal error */
-    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-    
-    tmp_status = HAL_ERROR;
-  }
- 
-
-  /* Configuration of ADC parameters if previous preliminary actions are      */ 
-  /* correctly completed and if there is no conversion on going on regular    */
-  /* group (ADC may already be enabled at this point if HAL_ADC_Init() is     */
-  /* called to update a parameter on the fly).                                */
-  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
-      (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)  )
-  {
-    
-    /* Initialize the ADC state */
-    SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
-    
-    /* Configuration of common ADC parameters                                 */
-    
-    /* Pointer to the common control register                                 */
-    tmpADC_Common = ADC_COMMON_REGISTER(hadc);
-    
-  
-    /* Parameters update conditioned to ADC state:                            */
-    /* Parameters that can be updated only when ADC is disabled:              */
-    /*  - clock configuration                                                 */
-    if ((ADC_IS_ENABLE(hadc) == RESET)   &&
-         (ADC_ANY_OTHER_ENABLED(hadc) == RESET) )         
-    {
-      /* Reset configuration of ADC common register CCR:                      */
-      /*                                                                      */
-      /*   - ADC clock mode and ACC prescaler (CKMODE and PRESC bits)are set  */
-      /*     according to adc->Init.ClockPrescaler. It selects the clock      */
-      /*    source and sets the clock division factor.                        */
-      /*                                                                      */
-      /* Some parameters of this register are not reset, since they are set   */
-      /* by other functions and must be kept in case of usage of this         */
-      /* function on the fly (update of a parameter of ADC_InitTypeDef        */
-      /* without needing to reconfigure all other ADC groups/channels         */
-      /* parameters):                                                         */
-      /*   - when multimode feature is available, multimode-related           */
-      /*     parameters: MDMA, DMACFG, DELAY, DUAL (set by API                */
-      /*     HAL_ADCEx_MultiModeConfigChannel() )                             */
-      /*   - internal measurement paths: Vbat, temperature sensor, Vref       */
-      /*     (set into HAL_ADC_ConfigChannel() or                             */
-      /*     HAL_ADCEx_InjectedConfigChannel() )                              */
-           
-      MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_PRESC|ADC_CCR_CKMODE, hadc->Init.ClockPrescaler);
-    }
-      
-      
-    /* Configuration of ADC:                                                  */
-    /*  - resolution                               Init.Resolution            */
-    /*  - data alignment                           Init.DataAlign             */
-    /*  - external trigger to start conversion     Init.ExternalTrigConv      */
-    /*  - external trigger polarity                Init.ExternalTrigConvEdge  */
-    /*  - continuous conversion mode               Init.ContinuousConvMode    */
-    /*  - overrun                                  Init.Overrun               */
-    /*  - discontinuous mode                       Init.DiscontinuousConvMode */
-    /*  - discontinuous mode channel count         Init.NbrOfDiscConversion   */    
-    tmpCFGR  = ( ADC_CFGR_CONTINUOUS(hadc->Init.ContinuousConvMode)          |
-                 hadc->Init.Overrun                                          |
-                 hadc->Init.DataAlign                                        |
-                 hadc->Init.Resolution                                       |
-                ADC_CFGR_REG_DISCONTINUOUS(hadc->Init.DiscontinuousConvMode) |
-                ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion) );
-      
-    /* Enable external trigger if trigger selection is different of software  */
-    /* start.                                                                 */
-    /*  - external trigger to start conversion     Init.ExternalTrigConv      */
-    /*  - external trigger polarity                Init.ExternalTrigConvEdge  */    
-    /* Note:  parameter ExternalTrigConvEdge set to "trigger edge none" is    */
-    /*        equivalent to software start.                                   */
-    if ((hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
-    &&  (hadc->Init.ExternalTrigConvEdge != ADC_EXTERNALTRIGCONVEDGE_NONE))
-    {
-      tmpCFGR |= ( hadc->Init.ExternalTrigConv |  hadc->Init.ExternalTrigConvEdge);
-    }
-    
-     /* Update Configuration Register CFGR */
-     MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR); 
-     
-
-    /* Parameters update conditioned to ADC state:                            */
-    /* Parameters that can be updated when ADC is disabled or enabled without */
-    /* conversion on going on regular and injected groups:                    */
-    /*  - DMA continuous request          Init.DMAContinuousRequests          */
-    /*  - LowPowerAutoWait feature        Init.LowPowerAutoWait               */
-    /*  - Oversampling parameters         Init.Oversampling                     */    
-    if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
-    {
-      tmpCFGR = ( ADC_CFGR_AUTOWAIT(hadc->Init.LowPowerAutoWait)       |
-                  ADC_CFGR_DMACONTREQ(hadc->Init.DMAContinuousRequests) );
-               
-      MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR);                    
-    
- 
-      if (hadc->Init.OversamplingMode == ENABLE)
-      {
-        assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio));
-        assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift));
-        assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode));
-        assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset));
-        
-        if ((hadc->Init.ExternalTrigConv == ADC_SOFTWARE_START)
-        ||  (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE))
-        {
-            /* Multi trigger is not applicable to software-triggered conversions */
-            assert_param((hadc->Init.Oversampling.TriggeredMode == ADC_TRIGGEREDMODE_SINGLE_TRIGGER));
-        }    
-    
-    
-       /* Configuration of Oversampler:                                       */
-       /*  - Oversampling Ratio                                               */
-       /*  - Right bit shift                                                  */
-       /*  - Triggered mode                                                   */
-       /*  - Oversampling mode (continued/resumed)                            */    
-       MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS, 
-                               ADC_CFGR2_ROVSE                     | 
-                               hadc->Init.Oversampling.Ratio         |
-                               hadc->Init.Oversampling.RightBitShift |
-                               hadc->Init.Oversampling.TriggeredMode |
-                               hadc->Init.Oversampling.OversamplingStopReset);
-      }  
-      else
-      {
-        /* Disable Regular OverSampling */
-        CLEAR_BIT( hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
-      }    
- 
-    
-    }   /*  if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) */
-    
-
-    
-    
-    /* Configuration of regular group sequencer:                              */
-    /* - if scan mode is disabled, regular channels sequence length is set to */
-    /*   0x00: 1 channel converted (channel on regular rank 1)                */
-    /*   Parameter "NbrOfConversion" is discarded.                            */
-    /*   Note: Scan mode is not present by hardware on this device, but       */
-    /*   emulated by software for alignment over all STM32 devices.           */
-    /* - if scan mode is enabled, regular channels sequence length is set to  */
-    /*   parameter "NbrOfConversion"                                          */
-
-    if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
-    {
-      /* Set number of ranks in regular group sequencer */     
-      MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));  
-    } 
-    else
-    {
-      CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
-    }
-    
-    
-    /* Initialize the ADC state */
-    /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
-    ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
-  }
-  else
-  {
-    /* Update ADC state machine to error */
-    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-        
-    tmp_status = HAL_ERROR;
-  }  /*  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)  && (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)  ) */
-  
-  
-  /* Return function status */
-  return tmp_status;
-
-}
-
-/**
-  * @brief  Deinitialize the ADC peripheral registers to their default reset
-  *         values, with deinitialization of the ADC MSP.           
-  * @note   Keep in mind that all ADCs use the same clock: disabling
-  *         the clock will reset all ADCs.
-  * @note   By default, HAL_ADC_DeInit() sets DEEPPWD: this saves more power by
-  *         reducing the leakage currents and is particularly interesting before
-  *         entering STOP 1 or STOP 2 modes.         
-  * @param  hadc: ADC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
-{  
-  /* Check ADC handle */
-  if(hadc == NULL)
-  {
-     return HAL_ERROR;
-  }
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  /* Change ADC state */
-  SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
-  
-  /* Stop potential conversion on going, on regular and injected groups */
-  /* No check on ADC_ConversionStop() return status, if the conversion
-    stop failed, it is up to HAL_ADC_MspDeInit() to reset the ADC IP */
-  ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
-
-  
-  /* Disable ADC peripheral if conversions are effectively stopped            */
-  /* Flush register JSQR: reset the queue sequencer when injected             */
-  /* queue sequencer is enabled and ADC disabled.                             */
-  /* The software and hardware triggers of the injected sequence are both     */
-  /* internally disabled just after the completion of the last valid          */
-  /* injected sequence.                                                       */
-  SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM);
-    
-  /* Disable the ADC peripheral */
-  /* No check on ADC_Disable() return status, if the ADC disabling process
-    failed, it is up to HAL_ADC_MspDeInit() to reset the ADC IP */  
-  ADC_Disable(hadc);
-
-
-  /* ========== Reset ADC registers ========== */
-  /* Reset register IER */
-  __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3  | ADC_IT_AWD2 | ADC_IT_AWD1 |
-                              ADC_IT_JQOVF | ADC_IT_OVR  |
-                              ADC_IT_JEOS  | ADC_IT_JEOC |
-                              ADC_IT_EOS   | ADC_IT_EOC  |
-                              ADC_IT_EOSMP | ADC_IT_RDY                 ) );
-      
-  /* Reset register ISR */
-  __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3  | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 |
-                              ADC_FLAG_JQOVF | ADC_FLAG_OVR  |
-                              ADC_FLAG_JEOS  | ADC_FLAG_JEOC |
-                              ADC_FLAG_EOS   | ADC_FLAG_EOC  |
-                              ADC_FLAG_EOSMP | ADC_FLAG_RDY                   ) );
-  
-  /* Reset register CR */
- /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, 
-    ADC_CR_ADCAL, ADC_CR_ADDIS and ADC_CR_ADEN are in access mode "read-set": 
-    no direct reset applicable. 
-    Update CR register to reset value where doable by software */
-  CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
-  SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);    
-      
-  /* Reset register CFGR */
-  CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_FIELDS);
-  SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);  
-  
-  /* Reset register CFGR2 */
-  CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSM  | ADC_CFGR2_TROVS   | ADC_CFGR2_OVSS |   
-                                  ADC_CFGR2_OVSR  | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE    );                                 
-  
-  /* Reset register SMPR1 */
-  CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_FIELDS);                                 
-  
-  /* Reset register SMPR2 */
-  CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 | 
-                             ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 | 
-                             ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10    );                                 
-  
-  /* Reset register TR1 */
-  CLEAR_BIT(hadc->Instance->TR1, ADC_TR1_HT1 | ADC_TR1_LT1);
-  
-  /* Reset register TR2 */
-  CLEAR_BIT(hadc->Instance->TR2, ADC_TR2_HT2 | ADC_TR2_LT2);    
-  
-  /* Reset register TR3 */
-  CLEAR_BIT(hadc->Instance->TR3, ADC_TR3_HT3 | ADC_TR3_LT3);      
-  
-  /* Reset register SQR1 */
-  CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 | 
-                            ADC_SQR1_SQ1 | ADC_SQR1_L);                              
-  
-  /* Reset register SQR2 */
-  CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 | 
-                            ADC_SQR2_SQ6 | ADC_SQR2_SQ5);                                
-  
-  /* Reset register SQR3 */
-  CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 | 
-                            ADC_SQR3_SQ11 | ADC_SQR3_SQ10);                                 
-  
-  /* Reset register SQR4 */
-  CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15); 
-  
-  /* Register JSQR was reset when the ADC was disabled */
-  
-  /* Reset register DR */
-  /* bits in access mode read only, no direct reset applicable*/
-    
-  /* Reset register OFR1 */
-  CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1); 
-  /* Reset register OFR2 */
-  CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2); 
-  /* Reset register OFR3 */
-  CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3); 
-  /* Reset register OFR4 */
-  CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
-  
-  /* Reset registers JDR1, JDR2, JDR3, JDR4 */
-  /* bits in access mode read only, no direct reset applicable*/
-  
-  /* Reset register AWD2CR */
-  CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
-  
-  /* Reset register AWD3CR */
-  CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
-  
-  /* Reset register DIFSEL */
-  CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL);
-  
-  /* Reset register CALFACT */
-  CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
-
-  
-  
-  
-  
-  
-  /* ========== Reset common ADC registers ========== */
-        
-  /* Software is allowed to change common parameters only when all the other
-     ADCs are disabled.   */
-  if ((ADC_IS_ENABLE(hadc) == RESET)   &&
-       (ADC_ANY_OTHER_ENABLED(hadc) == RESET) )
-  {
-    /* Reset configuration of ADC common register CCR:
-      - clock mode: CKMODE, PRESCEN
-      - multimode related parameters (when this feature is available): MDMA, 
-        DMACFG, DELAY, DUAL (set by HAL_ADCEx_MultiModeConfigChannel() API)
-      - internal measurement paths: Vbat, temperature sensor, Vref (set into
-        HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() )
-    */
-    ADC_CLEAR_COMMON_CONTROL_REGISTER(hadc);
-  }
-
-  /* DeInit the low level hardware. 
-  
-     For example:
-    __HAL_RCC_ADC_FORCE_RESET();
-    __HAL_RCC_ADC_RELEASE_RESET();
-    __HAL_RCC_ADC_CLK_DISABLE();
-    
-    Keep in mind that all ADCs use the same clock: disabling
-    the clock will reset all ADCs. 
-    
-  */ 
-  HAL_ADC_MspDeInit(hadc);
-    
-  /* Set ADC error code to none */
-  ADC_CLEAR_ERRORCODE(hadc);
-    
-  /* Reset injected channel configuration parameters */
-  hadc->InjectionConfig.ContextQueue = 0;
-  hadc->InjectionConfig.ChannelCount = 0; 
-    
-  /* Change ADC state */
-  hadc->State = HAL_ADC_STATE_RESET;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-
-  
-  /* Return function status */
-  return HAL_OK;
-
-}
-    
-/**
-  * @brief  Initialize the ADC MSP.
-  * @param  hadc: ADC handle
-  * @retval None
-  */
-__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
-
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_ADC_MspInit must be implemented in the user file.
-   */ 
-}
-
-/**
-  * @brief  DeInitialize the ADC MSP.
-  * @param  hadc: ADC handle
-  * @note   All ADCs use the same clock: disabling the clock will reset all ADCs.  
-  * @retval None
-  */
-__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
-
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_ADC_MspDeInit must be implemented in the user file.
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Exported_Functions_Group2 Input and Output operation functions
- *  @brief    IO operation functions 
- *
-@verbatim   
- ===============================================================================
-             ##### IO operation functions #####
- ===============================================================================  
-    [..]  This section provides functions allowing to:
-      (+) Start conversion of regular group.
-      (+) Stop conversion of regular group.
-      (+) Poll for conversion complete on regular group.
-      (+) Poll for conversion event.
-      (+) Get result of regular channel conversion.
-      (+) Start conversion of regular group and enable interruptions.
-      (+) Stop conversion of regular group and disable interruptions.
-      (+) Handle ADC interrupt request
-      (+) Start conversion of regular group and enable DMA transfer.
-      (+) Stop conversion of regular group and disable ADC DMA transfer.
-               
-@endverbatim
-  * @{
-  */
-  
-/**
-  * @brief  Enable ADC, start conversion of regular group.
-  * @note   Interruptions enabled in this function: None.
-  * @note   Case of multimode enabled (when multimode feature is available): 
-  *           if ADC is Slave, ADC is enabled but conversion is not started, 
-  *           if ADC is master, ADC is enabled and multimode conversion is started.
-  * @param  hadc: ADC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
-{
-  ADC_TypeDef        *tmpADC_Master;
-  HAL_StatusTypeDef tmp_status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-   
-  
-  /* if a regular conversion is already on-going (i.e. ADSTART is set),
-     don't restart the conversion. */
-  if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc))
-  {
-    return HAL_BUSY;
-  }
-  else
-  {
-    /* Process locked */
-    __HAL_LOCK(hadc);
-    
-    /* Enable the ADC peripheral */
-    tmp_status = ADC_Enable(hadc);
-  
-    /* Start conversion if ADC is effectively enabled */
-    if (tmp_status == HAL_OK)
-    {
-      /* State machine update: Check if an injected conversion is ongoing */
-      if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
-      {
-        /* Reset ADC error code fields related to regular conversions only */
-        CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR|HAL_ADC_ERROR_DMA));         
-      }
-      else
-      {  
-        /* Set ADC error code to none */
-        ADC_CLEAR_ERRORCODE(hadc); 
-      }
-      /* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */
-      ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_REG_EOC|HAL_ADC_STATE_REG_OVR|HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY);
-
-      /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
-        - by default if ADC is Master or Independent or if multimode feature is not available
-        - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */
-      if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
-      {
-        CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
-      }
-    
-      /* Clear regular group conversion flag and overrun flag                   */
-      /* (To ensure of no unknown state from potential previous ADC operations) */
-      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
-    
-      /* Enable conversion of regular group.                                  */
-      /* If software start has been selected, conversion starts immediately.  */
-      /* If external trigger has been selected, conversion starts at next     */
-      /* trigger event.                                                       */
-      /* Case of multimode enabled (when multimode feature is available):     */ 
-      /*  - if ADC is slave and dual regular conversions are enabled, ADC is  */
-      /*    enabled only (conversion is not started),                         */
-      /*  - if ADC is master, ADC is enabled and conversion is started.       */
-      if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
-      {
-        /* Multimode feature is not available or ADC Instance is Independent or Master, 
-           or is not Slave ADC with dual regular conversions enabled. 
-           Then, set HAL_ADC_STATE_INJ_BUSY bit and reset HAL_ADC_STATE_INJ_EOC bit if JAUTO is set. */
-        if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
-        {
-          ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  
-        }
-        /* Process unlocked */
-        __HAL_UNLOCK(hadc);
-        /* Start ADC */
-        SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
-      }
-      else
-      {
-        SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
-        /* if Master ADC JAUTO bit is set, update Slave State in setting 
-           HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */
-        tmpADC_Master = ADC_MASTER_REGISTER(hadc); 
-        if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET)
-        {
-          ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
-           
-        }  /* if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET) */
-        /* Process unlocked */
-        __HAL_UNLOCK(hadc);      
-      } /* if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)) */
-    }
-    else
-    {
-      /* Process unlocked */
-      __HAL_UNLOCK(hadc);    
-    }    
-  
-  /* Return function status */
-  return tmp_status;
-  }
-}
-
-/**  
-  * @brief  Stop ADC conversion of regular and injected groups, disable ADC peripheral.
-  * @param  hadc: ADC handle
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
-{ 
-  HAL_StatusTypeDef tmp_status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  /* 1. Stop potential regular and injected on-going conversions */
-  tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
-  
-  /* Disable ADC peripheral if conversions are effectively stopped */
-  if (tmp_status == HAL_OK)
-  {
-    /* 2. Disable the ADC peripheral */
-    tmp_status = ADC_Disable(hadc);
-    
-    /* Check if ADC is effectively disabled */
-    if (tmp_status == HAL_OK)
-    {
-      /* Change ADC state */
-      /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
-      ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);
-    }
-  }
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmp_status;
-}
-
-
-
-/**
-  * @brief  Wait for regular group conversion to be completed.
-  * @param  hadc: ADC handle
-  * @param  Timeout: Timeout value in millisecond.
-  * @note   Depending on hadc->Init.EOCSelection, EOS or EOC is 
-  *         checked and cleared depending on AUTDLY bit status. 
-  * @note   HAL_ADC_PollForConversion() returns HAL_ERROR if EOC is polled in a
-  *         DMA-managed conversions configuration: indeed, EOC is immediately 
-  *         reset by the DMA reading the DR register when the converted data is
-  *         available. Therefore, EOC is set for a too short period to be 
-  *         reliably polled.                    
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
-{
-  uint32_t           tickstart;
-  uint32_t           tmp_Flag_End   = 0x00;
-  ADC_TypeDef        *tmpADC_Master;
-  uint32_t           tmp_cfgr       = 0x00;
-  uint32_t           tmp_eos_raised = 0x01; /* by default, assume that EOS is set, 
-                                               tmp_eos_raised will be corrected
-                                               accordingly during API execution */ 
- 
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
-  /* If end of sequence selected */
-  if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
-  {
-    tmp_Flag_End = ADC_FLAG_EOS;
-  }
-  else /* end of conversion selected */
-  {
-    /* Check that the ADC is not in a DMA-based configuration. Otherwise,
-       returns an error.  */
-       
-    /* Check whether dual regular conversions are disabled or unavailable. */
-    if (ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(hadc) == RESET)  
-    {
-      /* Check DMAEN bit in handle ADC CFGR register */
-      if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != RESET)
-      {
-        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-        return HAL_ERROR;
-      } 
-    }
-    else
-    {
-      /* Else need to check Common register CCR MDMA bit field. */
-      if (ADC_MULTIMODE_DMA_ENABLED())
-      {
-        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 
-        return HAL_ERROR;          
-      }
-    }  
-    
-    /* no DMA transfer detected, polling ADC_FLAG_EOC is possible */         
-    tmp_Flag_End = ADC_FLAG_EOC;
-  }
-    
-  /* Get timeout */
-  tickstart = HAL_GetTick();  
-     
-  /* Wait until End of Conversion or Sequence flag is raised */
-  while (HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_End))
-  {
-    /* Check if timeout is disabled (set to infinite wait) */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
-      { 
-        SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);       
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  
-  /* Next, to clear the polled flag as well as to update the handle State,
-     EOS is checked and the relevant configuration register is retrieved. */
-  /*   1. Check whether or not EOS is set */
-  if (HAL_IS_BIT_CLR(hadc->Instance->ISR, ADC_FLAG_EOS))
-  {
-    tmp_eos_raised = 0;   
-  }
-  /*  2. Check whether or not hadc is the handle of a Slave ADC with dual
-   regular conversions enabled. */
-   if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)) 
-  {
-    /* Retrieve handle ADC CFGR register */
-    tmp_cfgr = READ_REG(hadc->Instance->CFGR);  
-  }
-  else
-  {
-    /* Retrieve Master ADC CFGR register */
-    tmpADC_Master = ADC_MASTER_REGISTER(hadc);
-    tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
-  }        
-
-  /* Clear polled flag */                         
-  if (tmp_Flag_End == ADC_FLAG_EOS)
-  {
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS);  
-  }
-  else
-  {               
-
-    /* Clear end of conversion EOC flag of regular group if low power feature */
-    /* "LowPowerAutoWait " is disabled, to not interfere with this feature    */
-    /* until data register is read using function HAL_ADC_GetValue().         */
-    /* For regular groups, no new conversion will start before EOC is cleared.*/
-    /* Note that 1. reading DR clears EOC.                                    */ 
-    /*           2. in multimode with dual regular conversions enabled (when  */
-    /*              multimode feature is available), Master AUTDLY bit is     */
-    /*              checked.                                                  */
-    if (READ_BIT (tmp_cfgr, ADC_CFGR_AUTDLY) == RESET)
-    {
-      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
-    }
-  }
-
-  
-  /* Update ADC state machine */
-  SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
-  /* If 1. EOS is set
-        2. conversions are software-triggered
-        3. CONT bit is reset (that of handle ADC or Master ADC if applicable)          
-     Then regular conversions are over and HAL_ADC_STATE_REG_BUSY can be reset.
-        4. additionally, if no injected conversions are on-going, HAL_ADC_STATE_READY
-          can be set */
-  if ((tmp_eos_raised)
-   && (ADC_IS_SOFTWARE_START_REGULAR(hadc))
-   && (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET))
-   {
-     CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);   
-     /* If no injected conversion on-going, set HAL_ADC_STATE_READY bit */
-     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
-     { 
-       SET_BIT(hadc->State, HAL_ADC_STATE_READY);
-     }
-   }                       
-
-  
-  /* Return API HAL status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Poll for ADC event.
-  * @param  hadc: ADC handle
-  * @param  EventType: the ADC event type.
-  *          This parameter can be one of the following values:
-  *            @arg @ref ADC_EOSMP_EVENT  ADC End of Sampling event            
-  *            @arg @ref ADC_AWD_EVENT    ADC Analog watchdog 1 event
-  *            @arg @ref ADC_AWD2_EVENT   ADC Analog watchdog 2 event
-  *            @arg @ref ADC_AWD3_EVENT   ADC Analog watchdog 3 event
-  *            @arg @ref ADC_OVR_EVENT    ADC Overrun event
-  *            @arg @ref ADC_JQOVF_EVENT  ADC Injected context queue overflow event
-  * @param  Timeout: Timeout value in millisecond.
-  * @note   The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR.
-  *         Indeed, the latter is reset only if hadc->Init.Overrun field is set  
-  *         to ADC_OVR_DATA_OVERWRITTEN. Otherwise, DR may be potentially overwritten 
-  *         by a new converted data as soon as OVR is cleared.
-  *         To reset OVR flag once the preserved data is retrieved, the user can resort
-  *         to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); 
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
-{
-  uint32_t tickstart; 
-
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  assert_param(IS_ADC_EVENT_TYPE(EventType));
-  
-  tickstart = HAL_GetTick();   
-      
-  /* Check selected event flag */
-  while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
-  {
-    /* Check if timeout is disabled (set to infinite wait) */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
-      {
-        /* Update ADC state machine to timeout */
-        SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
-        
-        /* Process unlocked */
-        __HAL_UNLOCK(hadc);
-        
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  
-  switch(EventType)
-  {
-  /* End Of Sampling event */
-  case ADC_EOSMP_EVENT:
-    /* Change ADC state */
-    SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
-     
-    /* Clear the End Of Sampling flag */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
-       
-    break;  
-  
-  /* Analog watchdog (level out of window) event                              */
-  /* Note: In case of several analog watchdog enabled, if needed to know      */
-  /* which one triggered and on which ADCx, test ADC state of Analog Watchdog */
-  /* flags HAL_ADC_STATE_AWD/2/3 function.                                    */
-  /* For example: "if (HAL_ADC_GetState(hadc1) == HAL_ADC_STATE_AWD) "        */
-  /*              "if (HAL_ADC_GetState(hadc1) == HAL_ADC_STATE_AWD2)"        */
-  /*              "if (HAL_ADC_GetState(hadc1) == HAL_ADC_STATE_AWD3)"        */
-  case ADC_AWD_EVENT:
-    /* Change ADC state */
-    SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
-     
-    /* Clear ADC analog watchdog flag */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
-       
-    break;
-  
-  /* Check analog watchdog 2 flag */
-  case ADC_AWD2_EVENT:
-    /* Change ADC state */
-    SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
-      
-    /* Clear ADC analog watchdog flag */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
-      
-    break;
-  
-  /* Check analog watchdog 3 flag */
-  case ADC_AWD3_EVENT:
-    /* Change ADC state */
-    SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
-      
-    /* Clear ADC analog watchdog flag */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
-      
-    break;
-  
-  /* Injected context queue overflow event */
-  case ADC_JQOVF_EVENT:
-    /* Change ADC state */
-    SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
-      
-    /* Set ADC error code to Injected context queue overflow */
-    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
-    
-    /* Clear ADC Injected context queue overflow flag */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
-    
-    break;
-     
-  /* Overrun event */
-  default: /* Case ADC_OVR_EVENT */
-    /* If overrun is set to overwrite previous data, overrun event is not     */
-    /* considered as an error.                                                */
-    /* (cf ref manual "Managing conversions without using the DMA and without */
-    /* overrun ")                                                             */
-    if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
-    {
-      /* Change ADC state */
-      SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
-        
-      /* Set ADC error code to overrun */
-      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
-    }
-    else
-    {
-      /* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN
-         otherwise, DR is potentially overwritten by new converted data as soon
-         as OVR is cleared. */
-      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
-    }
-    break;
-  }
-  
-  /* Return API HAL status */
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  Enable ADC, start conversion of regular group with interruption.
-  * @note   Interruptions enabled in this function according to initialization
-  *         setting : EOC (end of conversion), EOS (end of sequence), 
-  *         OVR overrun.
-  *         Each of these interruptions has its dedicated callback function.
-  * @note   Case of multimode enabled (when multimode feature is available): 
-  *         HAL_ADC_Start_IT() must be called for ADC Slave first, then for
-  *         ADC Master. 
-  *         For ADC Slave, ADC is enabled only (conversion is not started).  
-  *         For ADC Master, ADC is enabled and multimode conversion is started.
-  * @note   To guarantee a proper reset of all interruptions once all the needed
-  *         conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure 
-  *         a correct stop of the IT-based conversions.  
-  * @note   By default, HAL_ADC_Start_IT() doesn't enable the End Of Sampling 
-  *         interruption. If required (e.g. in case of oversampling with trigger
-  *         mode), the user must    
-  *          1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP)             
-  *          2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP)     
-  *          before calling HAL_ADC_Start_IT().    
-  * @param  hadc: ADC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmp_status = HAL_OK;
-  ADC_TypeDef        *tmpADC_Master;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  /* if a regular conversion is already on-going (i.e. ADSTART is set),
-     don't restart the conversion. */
-  if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc))
-  {
-    return HAL_BUSY;
-  }
-  else
-  {  
-    /* Process locked */
-    __HAL_LOCK(hadc);
- 
-    /* Enable the ADC peripheral */
-    tmp_status = ADC_Enable(hadc);
- 
-    /* Start conversion if ADC is effectively enabled */
-    if (tmp_status == HAL_OK)
-    {
-      /* State machine update: Check if an injected conversion is ongoing */
-      if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
-      {
-        /* Reset ADC error code fields related to regular conversions only */
-        CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR|HAL_ADC_ERROR_DMA));         
-      }
-      else
-      {
-        /* Set ADC error code to none */
-        ADC_CLEAR_ERRORCODE(hadc); 
-      } 
-      /* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */
-      ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_REG_EOC|HAL_ADC_STATE_REG_OVR|HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY);
-      
-      /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
-        - by default if ADC is Master or Independent or if multimode feature is not available
-        - if MultiMode setting is set to independent mode (no dual regular or injected conversions are configured) */
-      if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
-      {
-        CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
-      }      
-  
-      /* Clear regular group conversion flag and overrun flag */
-      /* (To ensure of no unknown state from potential previous ADC operations) */
-      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
-   
-      /* By default, disable all interruptions before enabling the desired ones */
-      __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
-  
-      /* Enable required interruptions */  
-      switch(hadc->Init.EOCSelection)
-      {
-        case ADC_EOC_SEQ_CONV: 
-          __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS);
-         break;
-        /* case ADC_EOC_SINGLE_CONV */
-        default:
-         __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
-         break;
-      }
-   
-      /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is
-         ADC_IT_OVR enabled; otherwise data overwrite is considered as normal
-         behavior and no CPU time is lost for a non-processed interruption */
-      if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
-      {
-        __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);  
-      }   
-      
-      /* Enable conversion of regular group.                                  */
-      /* If software start has been selected, conversion starts immediately.  */
-      /* If external trigger has been selected, conversion starts at next     */
-      /* trigger event.                                                       */
-      /* Case of multimode enabled (when multimode feature is available):     */ 
-      /*  - if ADC is slave and dual regular conversions are enabled, ADC is  */
-      /*    enabled only (conversion is not started),                         */
-      /*  - if ADC is master, ADC is enabled and conversion is started.       */
-      if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)   )
-      {
-        /* Multimode feature is not available or ADC Instance is Independent or Master, 
-           or is not Slave ADC with dual regular conversions enabled.         
-           Then set HAL_ADC_STATE_INJ_BUSY and reset HAL_ADC_STATE_INJ_EOC if JAUTO is set. */
-        if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
-        {
-          ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
-          
-          /* Enable as well injected interruptions in case 
-           HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
-           allows to start regular and injected conversions when JAUTO is
-           set with a single call to HAL_ADC_Start_IT() */
-          switch(hadc->Init.EOCSelection)
-          {
-            case ADC_EOC_SEQ_CONV: 
-              __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
-              __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
-            break;
-            /* case ADC_EOC_SINGLE_CONV */
-            default:
-              __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);      
-              __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
-            break;
-          }  
-        } /*  if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET) */
-        /* Process unlocked */
-        __HAL_UNLOCK(hadc);           
-        /* Start ADC */     
-        SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
-      }
-      else
-      {
-        /* hadc is the handle of a Slave ADC with dual regular conversions
-           enabled. Therefore, ADC_CR_ADSTART is NOT set */
-        SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
-        /* if Master ADC JAUTO bit is set, Slave injected interruptions
-           are enabled nevertheless (for same reason as above) */
-        tmpADC_Master = ADC_MASTER_REGISTER(hadc); 
-        if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET)
-        {
-          /* First, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit 
-             and in resetting HAL_ADC_STATE_INJ_EOC bit */
-          ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
-          /* Next, set Slave injected interruptions */
-          switch(hadc->Init.EOCSelection)
-          {
-            case ADC_EOC_SEQ_CONV: 
-              __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
-              __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
-            break;
-            /* case ADC_EOC_SINGLE_CONV */
-            default:
-              __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);      
-              __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
-            break;
-          }         
-        }  /* if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET) */
-        /* Process unlocked */
-        __HAL_UNLOCK(hadc);         
-      } /*  if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)   ) */     
-    }  /*  if (tmp_status == HAL_OK) */
-    else
-    {
-      /* Process unlocked */
-      __HAL_UNLOCK(hadc);    
-    }
- 
-    /* Return function status */
-    return tmp_status;
- 
-  }  
-}
-
-
-
-/**  
-  * @brief  Stop ADC conversion of regular groups when interruptions are enabled.
-  * @note   Stop as well injected conversions and disable ADC peripheral.
-  * @param  hadc: ADC handle
-  * @retval HAL status.
-  */  
-HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmp_status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  /* 1. Stop potential regular and injected on-going conversions */
-  tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
-  
-  /* Disable ADC peripheral if conversions are effectively stopped */
-  if (tmp_status == HAL_OK)
-  {
-    /* Disable all interrupts */
-    __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
-    
-    /* 2. Disable the ADC peripheral */
-    tmp_status = ADC_Disable(hadc);
-    
-    /* Check if ADC is effectively disabled */
-    if (tmp_status == HAL_OK)
-    {
-      /* Change ADC state */
-      /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
-      ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY); 
-    }
-  }
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmp_status;
-}
-
-
-/**
-  * @brief  Enable ADC, start conversion of regular group and transfer result through DMA.
-  * @note   Interruptions enabled in this function:
-  *         overrun (if applicable), DMA half transfer, DMA transfer complete. 
-  *         Each of these interruptions has its dedicated callback function.
-  * @note   Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_DMA() 
-  *         is designed for single-ADC mode only. For multimode, the dedicated 
-  *         HAL_ADCEx_MultiModeStart_DMA() function must be used.
-  * @param  hadc: ADC handle
-  * @param  pData: Destination Buffer address.
-  * @param  Length: Length of data to be transferred from ADC peripheral to memory (in bytes)
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
-{
-  HAL_StatusTypeDef tmp_status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc))
-  {
-    return HAL_BUSY;
-  }
-  else
-  {
-    
-    /* Process locked */
-    __HAL_LOCK(hadc);
-  
-    /* Ensure that dual regular conversions are not enabled or unavailable.   */
-    /* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used.  */
-    if (ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(hadc) == RESET)
-    {
-      /* Enable the ADC peripheral */
-      tmp_status = ADC_Enable(hadc);
-    
-      /* Start conversion if ADC is effectively enabled */
-      if (tmp_status == HAL_OK)
-      {
-        /* State machine update: Check if an injected conversion is ongoing */
-        if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
-        {
-          /* Reset ADC error code fields related to regular conversions only */
-          CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR|HAL_ADC_ERROR_DMA));             
-        }
-        else
-        {
-          /* Set ADC error code to none */
-          ADC_CLEAR_ERRORCODE(hadc);          
-        }
-        /* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */
-        ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_REG_EOC|HAL_ADC_STATE_REG_OVR|HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY);
-
-       /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
-        - by default if ADC is Master or Independent or if multimode feature is not available
-        - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */
-        if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
-        {
-          CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
-        }
-      
-        /* Set the DMA transfer complete callback */
-        hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
-
-        /* Set the DMA half transfer complete callback */
-        hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
-      
-        /* Set the DMA error callback */
-        hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
-
-            
-        /* Manage ADC and DMA start: ADC overrun interruption, DMA start,     */
-        /* ADC start (in case of SW start):                                   */
-      
-        /* Clear regular group conversion flag and overrun flag               */
-        /* (To ensure of no unknown state from potential previous ADC         */
-        /* operations)                                                        */
-        __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
-      
-        /* With DMA, overrun event is always considered as an error even if 
-           hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore,  
-           ADC_IT_OVR is enabled.  */         
-        __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);  
-     
-      
-        /* Enable ADC DMA mode */
-        SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
-      
-        /* Start the DMA channel */
-        HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
-               
-        /* Enable conversion of regular group.                                  */
-        /* Process unlocked */
-        __HAL_UNLOCK(hadc);          
-        /* If software start has been selected, conversion starts immediately.  */
-        /* If external trigger has been selected, conversion will start at next */
-        /* trigger event.                                                       */
-        SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
-      
-      }  
-      else
-      {
-        /* Process unlocked */
-        __HAL_UNLOCK(hadc);      
-      }  /* if (tmp_status == HAL_OK) */
-    }
-    else
-    {
-      tmp_status = HAL_ERROR;
-      /* Process unlocked */
-      __HAL_UNLOCK(hadc);      
-    } /* if (ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(hadc) == RESET) */
-  
-
-  
-  /* Return function status */
-  return tmp_status;
-  } /* if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc)) */
-}
-
-
-/**
-  * @brief  Stop ADC conversion of regular groups and disable ADC DMA transfer. 
-  * @note   Stop as well injected conversions and disable ADC peripheral.
-  * @note   Case of multimode enabled (when multimode feature is available): 
-  *         HAL_ADC_Stop_DMA() function is dedicated to single-ADC mode only. 
-  *         For multimode, the dedicated HAL_ADCEx_MultiModeStop_DMA() API must be used.
-  * @param  hadc: ADC handle
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
-{  
-  HAL_StatusTypeDef tmp_status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  /* 1. Stop potential regular conversion on going */
-  tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
-  
-  /* Disable ADC peripheral if conversions are effectively stopped */
-  if (tmp_status == HAL_OK)
-  {
-    /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
-    CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); 
-    
-    /* Disable the DMA channel (in case of DMA in circular mode or stop while */
-    /* while DMA transfer is on going)                                        */
-    tmp_status = HAL_DMA_Abort(hadc->DMA_Handle);   
-    
-    /* Check if DMA channel effectively disabled */
-    if (tmp_status != HAL_OK)
-    {
-      /* Update ADC state machine to error */
-      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);  
-    }
-    
-    /* Disable ADC overrun interrupt */
-    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
-    
-    /* 2. Disable the ADC peripheral */
-    /* Update "tmp_status" only if DMA channel disabling passed, to keep in */
-    /* memory a potential failing status.                                     */
-    if (tmp_status == HAL_OK)
-    {
-      tmp_status = ADC_Disable(hadc);
-    }
-    else
-    {
-      ADC_Disable(hadc);
-    }
-
-    /* Check if ADC is effectively disabled */
-    if (tmp_status == HAL_OK)
-    {
-      /* Change ADC state */
-      /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
-      ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);     
-    }
-    
-  }
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmp_status;
-}
-
-
-/**
-  * @brief  Get ADC regular group conversion result.
-  * @param  hadc: ADC handle
-  * @note   Reading DR register automatically clears EOC flag. To reset EOS flag, 
-  *         the user must resort to the macro 
-  *         __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS)  
-  * @retval Converted value
-  */
-uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  /* Return ADC converted value */ 
-  return hadc->Instance->DR;
-}
-
-
-/**
-  * @brief  Handle ADC interrupt request.  
-  * @param  hadc: ADC handle
-  * @retval None
-  */
-void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
-{
-  uint32_t overrun_error = 0; /* flag set if overrun occurrence has to be considered as an error */
-  ADC_TypeDef        *tmpADC_Master;  
-  uint32_t tmp_isr      = hadc->Instance->ISR;
-  uint32_t tmp_ier      = hadc->Instance->IER;
-  uint32_t tmp_cfgr     = 0x0;
-  uint32_t tmp_cfgr_jqm = 0x0;       
-  
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
-  
-  
-  /* ====== Check End of Sampling flag for regular group ===== */
-  if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP))
-  {
-    /* Update state machine on end of sampling status if not in error state */
-    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
-    {
-      /* Change ADC state */
-      SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
-    }
-        
-    /* End Of Sampling callback */
-      HAL_ADCEx_EndOfSamplingCallback(hadc);
-    
-    /* Clear regular group conversion flag */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP );
-  }  
-  
-  /* ====== Check End of Conversion or Sequence flags for regular group ===== */
-  if( (((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
-      (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS))  )
-  {
-    /* Update state machine on conversion status if not in error state */
-    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
-    {
-      /* Change ADC state */    
-      SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 
-    }
-    
-    /* Disable interruption if no further conversion upcoming by regular      */
-    /* external trigger or by continuous mode,                                */
-    /* and if scan sequence if completed.                                     */
-    if(ADC_IS_SOFTWARE_START_REGULAR(hadc))
-    {
-      if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
-      {
-        /* check CONT bit directly in handle ADC CFGR register */
-        tmp_cfgr = READ_REG(hadc->Instance->CFGR); 
-      }
-      else
-      {
-        /* else need to check Master ADC CONT bit */
-        tmpADC_Master = ADC_MASTER_REGISTER(hadc);
-        tmp_cfgr = READ_REG(tmpADC_Master->CFGR); 
-      }
-      
-      /* Carry on if continuous mode is disabled */
-      if (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT)
-      {
-        /* If End of Sequence is reached, disable interrupts */
-        if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
-        {
-          /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit           */
-          /* ADSTART==0 (no conversion on going)                                */
-          if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
-          {
-            /* Disable ADC end of sequence conversion interrupt */
-            /* Note: if Overrun interrupt was enabled with EOC or EOS interrupt */
-            /* in HAL_Start_IT(), it isn't disabled here because it can be used */
-            /* by overrun IRQ process below.                                    */
-            __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
-            /* Clear HAL_ADC_STATE_REG_BUSY bit */
-             CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 
-             /* If no injected conversion on-going, set HAL_ADC_STATE_READY bit */
-             if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
-             { 
-               SET_BIT(hadc->State, HAL_ADC_STATE_READY);
-             }           
-          }
-          else
-          {
-            /* Change ADC state to error state */
-            SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-            
-            /* Set ADC error code to ADC IP internal error */
-            SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-          }
-        }
-      } /* if (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT) */
-    }   /* if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   */
-    
-    /* Conversion complete callback */
-    /* Note:  HAL_ADC_ConvCpltCallback can resort to 
-              if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) or
-              if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOC)) to determine whether 
-              interruption has been triggered by end of conversion or end of 
-              sequence.    */
-      HAL_ADC_ConvCpltCallback(hadc);
-
-    
-    /* Clear regular group conversion flag */
-    __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) );
-  }
-  
-  
-  /* ========== Check End of Conversion flag for injected group ========== */
-  if( (((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) ||
-      (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS))  )      
-  {
-    /* Update state machine on conversion status if not in error state */
-    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
-    {
-      /* Change ADC state */
-      SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
-    }
-    
-
-    /* Check whether interruptions can be disabled only if
-        - injected conversions are software-triggered when injected queue management is disabled
-        OR
-        - auto-injection is enabled, continuous mode is disabled (CONT = 0)
-          and regular conversions are software-triggered */
-          /* If End of Sequence is reached, disable interrupts */
-    if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
-    {
-          
-      /* First, retrieve proper registers to check */
-      /* 1a. Are injected conversions that of a dual Slave ? */      
-      if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc))
-      {
-        /* hadc is not the handle of a Slave ADC with dual injected conversions enabled:
-           check JQM bit directly in ADC CFGR register */
-        tmp_cfgr_jqm = READ_REG(hadc->Instance->CFGR); 
-      }
-      else
-      {
-        /* hadc is the handle of a Slave ADC with dual injected conversions enabled:
-           need to check JQM bit of Master ADC CFGR register */
-          tmpADC_Master = ADC_MASTER_REGISTER(hadc);
-          tmp_cfgr_jqm = READ_REG(tmpADC_Master->CFGR); 
-      }
-      /* 1b. Is hadc the handle of a Slave ADC with regular conversions enabled? */ 
-      if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
-      {
-        /* hadc is not the handle of a Slave ADC with dual regular conversions enabled:
-           check JAUTO and CONT bits directly in ADC CFGR register */        
-          tmp_cfgr = READ_REG(hadc->Instance->CFGR); 
-      }
-      else
-      {
-        /* hadc is not the handle of a Slave ADC with dual regular conversions enabled:
-           check JAUTO and CONT bits of Master ADC CFGR register */  
-        tmpADC_Master = ADC_MASTER_REGISTER(hadc);
-        tmp_cfgr = READ_REG(tmpADC_Master->CFGR); 
-      }
-      
-      /* Secondly, check whether JEOC and JEOS interruptions can be disabled */                                                 
-      if ((ADC_IS_SOFTWARE_START_INJECTED(hadc) && (READ_BIT(tmp_cfgr_jqm, ADC_CFGR_JQM) != ADC_CFGR_JQM))  
-         && (!((READ_BIT(tmp_cfgr, (ADC_CFGR_JAUTO|ADC_CFGR_CONT)) == (ADC_CFGR_JAUTO|ADC_CFGR_CONT)) &&    
-             (ADC_IS_SOFTWARE_START_REGULAR(hadc))))    )
-      {
-        /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit         */
-        /* JADSTART==0 (no conversion on going)                               */
-        if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
-        {
-          /* Disable ADC end of sequence conversion interrupt  */
-          __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
-          /* Clear HAL_ADC_STATE_INJ_BUSY bit */
-           CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);   
-           /* If no regular conversion on-going, set HAL_ADC_STATE_READY bit */                   
-          if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
-          { 
-            SET_BIT(hadc->State, HAL_ADC_STATE_READY);
-          }           
-        }
-        else
-        {
-          /* Change ADC state to error state */
-          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-          
-          /* Set ADC error code to ADC IP internal error */
-          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-        }
-      }
-    } /* if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) */
-    
-    /* Injected Conversion complete callback */
-    /* Note:  HAL_ADCEx_InjectedConvCpltCallback can resort to 
-              if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or
-              if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether 
-              interruption has been triggered by end of conversion or end of 
-              sequence.    */    
-    HAL_ADCEx_InjectedConvCpltCallback(hadc);
-    
-    /* Clear injected group conversion flag */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS);
-  }
-  
-   
-  /* ========== Check Analog watchdog flags =================================================== */
-  
-  /* ========== Check Analog watchdog 1 flags ========== */
-  if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1))      
-  {
-    /* Change ADC state */
-    SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
-    
-    /* Level out of window 1 callback */
-    HAL_ADC_LevelOutOfWindowCallback(hadc);
-    /* Clear ADC Analog watchdog flag */ 
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
-  }
-  
-  /* ========== Check Analog watchdog 2 flags ========== */
-  if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2))      
-  {
-    /* Change ADC state */
-    SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
-    
-    /* Level out of window 2 callback */
-    HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
-    /* Clear ADC Analog watchdog flag */ 
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
-  } 
-  
-  /* ========== Check Analog watchdog 3 flags ========== */
-  if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3))      
-  {
-    /* Change ADC state */
-    SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
-    
-    /* Level out of window 3 callback */
-    HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
-    /* Clear ADC Analog watchdog flag */ 
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
-  } 
-  
-  
-  /* ========== Check Overrun flag ========== */
-  if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR)) 
-  {
-    /* If overrun is set to overwrite previous data (default setting),        */
-    /* overrun event is not considered as an error.                           */
-    /* (cf ref manual "Managing conversions without using the DMA and without */
-    /* overrun ")                                                             */
-    /* Exception for usage with DMA overrun event always considered as an     */
-    /* error.                                                                 */
-    
-    if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
-    {
-      overrun_error = 1;
-    }
-    else
-    {
-      /* check DMA configuration, depending on multimode set or not,
-        or whether or not multimode feature is available */
-      if (ADC_IS_DUAL_CONVERSION_ENABLE(hadc) == RESET)
-      {
-        /* Multimode not set or feature not available or ADC independent */
-        if (HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_DMAEN))
-        {
-          overrun_error = 1;  
-        }      
-      }
-      else
-      {
-        /* Multimode (when feature is available) is enabled, 
-           Common Control Register MDMA bits must be checked. */
-        if (ADC_MULTIMODE_DMA_ENABLED())
-        {
-          overrun_error = 1;  
-        }
-      }
-    }
-        
-    if (overrun_error == 1)
-    {
-      /* Change ADC state to error state */
-      SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
-      
-      /* Set ADC error code to overrun */
-      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
-      
-      /* Error callback */ 
-      HAL_ADC_ErrorCallback(hadc);
-    }
-
-    /* Clear the Overrun flag, to be done AFTER HAL_ADC_ErrorCallback() since
-       old data is preserved until OVR is reset */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);  
-
-  }
-  
-  
-  /* ========== Check Injected context queue overflow flag ========== */
-  if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF)) 
-  {
-    /* Change ADC state to overrun state */
-    SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
-        
-    /* Set ADC error code to Injected context queue overflow */
-    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
-    
-    /* Clear the Injected context queue overflow flag */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
-    
-    /* Error callback */ 
-    HAL_ADCEx_InjectedQueueOverflowCallback(hadc);
-  }
-  
-}
-
-/**
-  * @brief  Conversion complete callback in non-blocking mode.
-  * @param  hadc: ADC handle
-  * @retval None
-  */
-__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
-
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_ADC_ConvCpltCallback must be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  Conversion DMA half-transfer callback in non-blocking mode.
-  * @param  hadc: ADC handle
-  * @retval None
-  */
-__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
-
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
-  */
-}
-
-/**
-  * @brief  Analog watchdog 1 callback in non-blocking mode.        
-  * @param  hadc: ADC handle
-  * @retval None
-  */
-__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
-
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
-  */
-}
-
-/**
-  * @brief  ADC error callback in non-blocking mode
-  *        (ADC conversion with interruption or transfer by DMA).
-  * @param  hadc: ADC handle
-  * @retval None
-  */
-__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
-
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_ADC_ErrorCallback must be implemented in the user file.
-  */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
- *  @brief    Peripheral Control functions 
- *
-@verbatim   
- ===============================================================================
-             ##### Peripheral Control functions #####
- ===============================================================================  
-    [..]  This section provides functions allowing to:
-      (+) Configure channels on regular group
-      (+) Configure the analog watchdog
-      
-@endverbatim
-  * @{
-  */
-
-
-/**
-  * @brief  Configure the selected channel to be linked to the regular group.
-  * @note   In case of usage of internal measurement channels (Vbat / VrefInt /
-  *         TempSensor), the recommended sampling time is provided by the
-  *         datasheet.  
-  *         These internal paths can be disabled using function 
-  *         HAL_ADC_DeInit().
-  * @note   Possibility to update parameters on the fly:
-  *         HAL_ADC_ConfigChannel() initializes channel into regular group, 
-  *         consecutive calls to this function can be used to reconfigure some 
-  *         parameters of structure "ADC_ChannelConfTypeDef" on the fly, without 
-  *         resetting the ADC.
-  *         The setting of these parameters is conditioned to ADC state.
-  *         For parameters constraints, see comments of structure 
-  *         "ADC_ChannelConfTypeDef".
-  * @param  hadc: ADC handle
-  * @param  sConfig: Structure ADC channel for regular group.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
-{
-  HAL_StatusTypeDef tmp_status = HAL_OK;
-                                                                                                                     
-  ADC_Common_TypeDef *tmpADC_Common;
-  uint32_t tmpOffsetShifted;
-  __IO uint32_t wait_loop_index = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
-  assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
-  assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfig->SingleDiff));
-  assert_param(IS_ADC_OFFSET_NUMBER(sConfig->OffsetNumber));
-  assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset));
-
-  /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is  
-     ignored (considered as reset) */
-  assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE)));  
-  
-  /* Verification of channel number */
-  if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
-  {
-     assert_param(IS_ADC_CHANNEL(hadc, sConfig->Channel));
-  }
-  else
-  {
-    assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfig->Channel));
-  }
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-
-  /* Parameters update conditioned to ADC state:                              */
-  /* Parameters that can be updated when ADC is disabled or enabled without   */
-  /* conversion on going on regular group:                                    */
-  /*  - Channel number                                                        */
-  /*  - Channel rank                                                          */
-  if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
-  {
-    
-      /* Regular sequence configuration */
-      /* Clear the old SQx bits then set the new ones for the selected rank */
-      /* For Rank 1 to 4 */
-      if (sConfig->Rank < 5)
-      {      
-        MODIFY_REG(hadc->Instance->SQR1, 
-                  ADC_SQR1_RK(ADC_SQR2_SQ5, sConfig->Rank), 
-                  ADC_SQR1_RK(sConfig->Channel, sConfig->Rank));      
-      }
-      /* For Rank 5 to 9 */
-      else if (sConfig->Rank < 10)
-      {
-        MODIFY_REG(hadc->Instance->SQR2, 
-                  ADC_SQR2_RK(ADC_SQR2_SQ5, sConfig->Rank), 
-                  ADC_SQR2_RK(sConfig->Channel, sConfig->Rank));       
-      }
-      /* For Rank 10 to 14 */
-      else if (sConfig->Rank < 15)
-      {
-        MODIFY_REG(hadc->Instance->SQR3, 
-                  ADC_SQR3_RK(ADC_SQR3_SQ10, sConfig->Rank), 
-                  ADC_SQR3_RK(sConfig->Channel, sConfig->Rank));        
-      }
-      /* For Rank 15 to 16 */
-      else
-      {   
-        MODIFY_REG(hadc->Instance->SQR4, 
-                  ADC_SQR4_RK(ADC_SQR4_SQ15, sConfig->Rank), 
-                  ADC_SQR4_RK(sConfig->Channel, sConfig->Rank));         
-      }
-      
-      
-      /* Parameters update conditioned to ADC state:                              */
-      /* Parameters that can be updated when ADC is disabled or enabled without   */
-      /* conversion on going on regular group:                                    */
-      /*  - Channel sampling time                                                 */
-      /*  - Channel offset                                                        */
-      if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
-      {
-       
-        /* Channel sampling time configuration */
-        /* Clear the old sample time then set the new one for the selected channel */    
-        /* For channels 10 to 18 */
-        if (sConfig->Channel >= ADC_CHANNEL_10)
-        {
-          ADC_SMPR2_SETTING(hadc, sConfig->SamplingTime, sConfig->Channel);                
-        }
-        else /* For channels 0 to 9 */
-        {
-          ADC_SMPR1_SETTING(hadc, sConfig->SamplingTime, sConfig->Channel);                       
-        }
-      
-  
-       /* Configure the offset: offset enable/disable, channel, offset value */
-  
-       /* Shift the offset with respect to the selected ADC resolution. */
-       /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
-       tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfig->Offset);
-      
-       switch (sConfig->OffsetNumber)
-       {
-        /* Configure offset register i when applicable:                         */
-        /* - Enable offset                                                      */
-        /* - Set channel number                                                 */
-        /* - Set offset value                                                   */    
-       case ADC_OFFSET_1:                                
-          MODIFY_REG(hadc->Instance->OFR1, 
-                  ADC_OFR_FIELDS, 
-                  ADC_OFR1_OFFSET1_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted);                                   
-         break;
-      
-       case ADC_OFFSET_2:
-         MODIFY_REG(hadc->Instance->OFR2, 
-                  ADC_OFR_FIELDS, 
-                  ADC_OFR2_OFFSET2_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted);                                  
-         break;
-          
-       case ADC_OFFSET_3:
-         MODIFY_REG(hadc->Instance->OFR3, 
-                  ADC_OFR_FIELDS, 
-                  ADC_OFR3_OFFSET3_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted);                                  
-         break;
-      
-       case ADC_OFFSET_4:
-         MODIFY_REG(hadc->Instance->OFR4, 
-                  ADC_OFR_FIELDS, 
-                  ADC_OFR4_OFFSET4_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted);                                  
-         break;
-      
-       /* Case ADC_OFFSET_NONE */
-       default :
-       /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is enabled. 
-          If this is the case, offset OFRx is disabled since 
-          sConfig->OffsetNumber = ADC_OFFSET_NONE. */
-         if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
-         {
-           CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN);
-         }
-         if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
-         {
-           CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN); 
-         }
-         if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
-         {
-           CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN); 
-         }
-         if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
-         {
-           CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN);
-         }
-         break;
-      }  /*  switch (sConfig->OffsetNumber) */
-  
-    }  /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) */
-   
-  
-  
-    /* Parameters update conditioned to ADC state:                              */
-    /* Parameters that can be updated only when ADC is disabled:                */
-    /*  - Single or differential mode                                           */
-    /*  - Internal measurement channels: Vbat/VrefInt/TempSensor                */
-    if (ADC_IS_ENABLE(hadc) == RESET)
-    {
-      /* Configuration of differential mode */
-      if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
-      {
-        /* Disable differential mode (default mode: single-ended) */
-        CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel));
-      }
-      else
-      {
-        /* Enable differential mode */
-        SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel));
-        
-        /* Sampling time configuration of channel ADC_IN+1 (negative input)     */
-        /* Clear the old sample time then set the new one for the selected      */
-        /* channel.                                                             */        
-        /* Starting from channel 9, SMPR2 register must be configured           */
-        if (sConfig->Channel >= ADC_CHANNEL_9)
-        {
-          ADC_SMPR2_SETTING(hadc, sConfig->SamplingTime, sConfig->Channel+1);                                
-        }
-        else /* For channels 0 to 8, SMPR1 must be configured */
-        {
-          ADC_SMPR1_SETTING(hadc, sConfig->SamplingTime, sConfig->Channel+1);      
-        }
-      }
-    
-    
-      
-      /* Management of internal measurement channels: Vbat/VrefInt/TempSensor.  */
-      /* If internal channel selected, enable dedicated internal buffers and    */
-      /*  paths.                                                                */
-      /* Note: these internal measurement paths can be disabled using           */
-      /* HAL_ADC_DeInit().                                                      */
-         
-      /* Configuration of common ADC parameters                                 */
-      tmpADC_Common = ADC_COMMON_REGISTER(hadc);
-    
-  
-      /* If the requested internal measurement path has already been enabled,   */
-      /* bypass the configuration processing.                                   */
-      if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
-            (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN))            ) ||
-          ( (sConfig->Channel == ADC_CHANNEL_VBAT)       &&
-            (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN))          ) ||
-          ( (sConfig->Channel == ADC_CHANNEL_VREFINT)    &&
-            (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN)))
-         )
-      {
-        /* Configuration of common ADC parameters (continuation)                */
-  
-        /* Software is allowed to change common parameters only when all ADCs   */
-        /* of the common group are disabled.                                    */
-        if ((ADC_IS_ENABLE(hadc) == RESET)   &&
-           (ADC_ANY_OTHER_ENABLED(hadc) == RESET) )              
-        {
-          if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
-          {
-            if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) 
-            {
-              SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN);
-            
-              /* Delay for temperature sensor stabilization time */
-              /* Compute number of CPU cycles to wait for */
-              wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
-              while(wait_loop_index != 0)
-              {
-                wait_loop_index--;
-              }
-            }
-          }
-          else if (sConfig->Channel == ADC_CHANNEL_VBAT)
-          {
-            if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
-            {
-              SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN);
-            }
-          }
-          else if (sConfig->Channel == ADC_CHANNEL_VREFINT)
-          { 
-            if (ADC_VREFINT_INSTANCE(hadc))
-            {
-              SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN);
-            }        
-          }
-        }
-        /* If the requested internal measurement path has already been          */
-        /* enabled and other ADC of the common group are enabled, internal      */
-        /* measurement paths cannot be enabled.                                 */
-        else  
-        {
-          /* Update ADC state machine to error */
-          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-          
-          tmp_status = HAL_ERROR;
-        }
-      }
-  
-    } /* if (ADC_IS_ENABLE(hadc) == RESET) */
-
-  } /* if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) */
-  
-  /* If a conversion is on going on regular group, no update on regular       */
-  /* channel could be done on neither of the channel configuration structure  */
-  /* parameters.                                                              */
-  else
-  {
-    /* Update ADC state machine to error */
-    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-    
-    tmp_status = HAL_ERROR;
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-
-  /* Return function status */
-  return tmp_status;
-}
-  
-
-
-/**
-  * @brief  Configure the analog watchdog.
-  * @note   Possibility to update parameters on the fly:
-  *         This function initializes the selected analog watchdog, successive  
-  *         calls to this function can be used to reconfigure some parameters 
-  *         of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting 
-  *         the ADC, e.g. to set several channels to monitor simultaneously. 
-  *         The setting of these parameters is conditioned to ADC state.
-  *         For parameters constraints, see comments of structure 
-  *         "ADC_AnalogWDGConfTypeDef".
-  * @param  hadc: ADC handle
-  * @param  AnalogWDGConfig: Structure of ADC analog watchdog configuration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
-{
-  HAL_StatusTypeDef tmp_status = HAL_OK;
-
-  
-  uint32_t tmpAWDHighThresholdShifted;
-  uint32_t tmpAWDLowThresholdShifted;
-  
-  uint32_t tmpADCFlagAWD2orAWD3;
-  uint32_t tmpADCITAWD2orAWD3;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber));
-  assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
-  assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
-  
-  if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG)     ||
-     (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC)   ||
-     (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)  )
-  {
-    assert_param(IS_ADC_CHANNEL(hadc, AnalogWDGConfig->Channel));
-  }
-  
-
-  /* Verify if threshold is within the selected ADC resolution */
-  assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
-  assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
-
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  /* Parameters update conditioned to ADC state:                              */
-  /* Parameters that can be updated when ADC is disabled or enabled without   */
-  /* conversion on going on regular and injected groups:                      */
-  /*  - Analog watchdog channels                                              */
-  /*  - Analog watchdog thresholds                                            */
-  if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
-  {
-  
-    /* Analog watchdogs configuration */
-    if(AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
-    {
-      /* Configuration of analog watchdog:                                    */
-      /*  - Set the analog watchdog enable mode: regular and/or injected      */
-      /*    groups, one or overall group of channels.                         */
-      /*  - Set the Analog watchdog channel (is not used if watchdog          */
-      /*    mode "all channels": ADC_CFGR_AWD1SGL=0).                         */
-                                
-        MODIFY_REG(hadc->Instance->CFGR,  ADC_CFGR_WD_FIELDS, 
-              AnalogWDGConfig->WatchdogMode | ADC_CFGR_SET_AWD1CH(AnalogWDGConfig->Channel) );                                  
-
-      /* Shift the offset with respect to the selected ADC resolution:         */
-      /* Thresholds have to be left-aligned on bit 11, the LSB (right bits)   */
-      /* are set to 0                                                         */ 
-      tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
-      tmpAWDLowThresholdShifted  = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
-      
-      /* Set the high and low thresholds */                                
-      MODIFY_REG(hadc->Instance->TR1,  ADC_TR1_HT1 | ADC_TR1_LT1, 
-              ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) | tmpAWDLowThresholdShifted );                                  
-      
-      /* Clear the ADC Analog watchdog flag (in case left enabled by          */
-      /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */
-      /* or HAL_ADC_PollForEvent().                                           */
-      __HAL_ADC_CLEAR_FLAG(hadc, ADC_IT_AWD1);
-      
-      /* Configure ADC Analog watchdog interrupt */
-      if(AnalogWDGConfig->ITMode == ENABLE)
-      {
-        /* Enable the ADC Analog watchdog interrupt */
-        __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD1);
-      }
-      else
-      {
-        /* Disable the ADC Analog watchdog interrupt */
-        __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD1);
-      }
-      
-      /* Update state, clear previous result related to AWD1 */
-      CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1);
-    }
-    /* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */
-    else
-    {
-    /* Shift the threshold with respect to the selected ADC resolution         */
-    /* have to be left-aligned on bit 7, the LSB (right bits) are set to 0    */
-      tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
-      tmpAWDLowThresholdShifted  = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
-
-      if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
-      {
-        /* Set the Analog watchdog channel or group of channels. This also    */
-        /* enables the watchdog.                                              */
-        /* Note: Conditional register reset, because several channels can be */
-        /*       set by successive calls of this function.                    */
-        if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE) 
-        {
-          SET_BIT(hadc->Instance->AWD2CR, ADC_CFGR_SET_AWD23CR(AnalogWDGConfig->Channel));
-        }
-        else
-        {
-          CLEAR_BIT(hadc->Instance->AWD2CR,  ADC_AWD2CR_AWD2CH);
-        }
-        
-        /* Set the high and low thresholds */
-        MODIFY_REG(hadc->Instance->TR2,  ADC_TR2_HT2 | ADC_TR2_LT2, 
-              ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) | tmpAWDLowThresholdShifted );                                      
-        
-        /* Set temporary variable to flag and IT of AWD2 or AWD3 for further  */
-        /* settings.                                                          */
-        tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD2;
-        tmpADCITAWD2orAWD3 = ADC_IT_AWD2;
-        
-        /* Update state, clear previous result related to AWD2 */
-        CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2);
-      }
-      /* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
-      else
-      {
-        /* Set the Analog watchdog channel or group of channels. This also    */
-        /* enables the watchdog.                                              */
-        /* Note: Conditional register reset, because several channels can be */
-        /*       set by successive calls of this function.                    */
-        if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE) 
-        {
-          SET_BIT(hadc->Instance->AWD3CR, ADC_CFGR_SET_AWD23CR(AnalogWDGConfig->Channel));
-        }
-        else
-        {
-          CLEAR_BIT(hadc->Instance->AWD3CR,  ADC_AWD3CR_AWD3CH);
-        }
-        
-        /* Set the high and low thresholds */
-        MODIFY_REG(hadc->Instance->TR3,  ADC_TR3_HT3 | ADC_TR3_LT3, 
-              ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) | tmpAWDLowThresholdShifted );                                    
-        
-        /* Set temporary variable to flag and IT of AWD2 or AWD3 for further  */
-        /* settings.                                                          */
-        tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD3;
-        tmpADCITAWD2orAWD3 = ADC_IT_AWD3;
-        
-        /* Update state, clear previous result related to AWD3 */
-        CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3);
-      }
-
-      /* Clear the ADC Analog watchdog flag (in case left enabled by          */
-      /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */
-      /* or HAL_ADC_PollForEvent().                                           */
-      __HAL_ADC_CLEAR_FLAG(hadc, tmpADCFlagAWD2orAWD3);
-
-      /* Configure ADC Analog watchdog interrupt */
-      if(AnalogWDGConfig->ITMode == ENABLE)
-      {
-        __HAL_ADC_ENABLE_IT(hadc, tmpADCITAWD2orAWD3);
-      }
-      else
-      {
-        __HAL_ADC_DISABLE_IT(hadc, tmpADCITAWD2orAWD3);
-      }
-    }
-  
-  }
-  /* If a conversion is on going on regular or injected groups, no update     */
-  /* could be done on neither of the AWD configuration structure parameters.  */
-  else
-  {
-    /* Update ADC state machine to error */
-    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-    
-    tmp_status = HAL_ERROR;
-  }
-  
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-
-  /* Return function status */
-  return tmp_status;
-}
-
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
- *  @brief   ADC Peripheral State functions 
- *
-@verbatim   
- ===============================================================================
-            ##### Peripheral state and errors functions #####
- ===============================================================================
-    [..]
-    This subsection provides functions to get in run-time the status of the  
-    peripheral.
-      (+) Check the ADC state
-      (+) Check the ADC error code
-         
-@endverbatim
-  * @{
-  */
-  
-/**
-  * @brief  Return the ADC handle state.
-  * @param  hadc: ADC handle
-  * @retval HAL state  (uint32_t bit-map)
-  */
-uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  /* Return ADC handle state */
-  return hadc->State;
-}
-
-
-/**
-  * @brief  Return the ADC error code.
-  * @param  hadc: ADC handle
-  * @retval ADC Error Code (uint32_t bit-map)
-  */
-uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  return hadc->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-
-/** @defgroup ADC_Private_Functions ADC Private Functions
-  * @{
-  */
-
-/**
-  * @brief  Stop ADC conversion.
-  * @param  hadc: ADC handle
-  * @param  ConversionGroup: ADC group regular and/or injected.
-  *          This parameter can be one of the following values:
-  *            @arg @ref ADC_REGULAR_GROUP           ADC regular conversion type.
-  *            @arg @ref ADC_INJECTED_GROUP          ADC injected conversion type.
-  *            @arg @ref ADC_REGULAR_INJECTED_GROUP  ADC regular and injected conversion type.
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup)
-{
-  uint32_t tmp_ADC_CR_ADSTART_JADSTART = 0;
-  uint32_t tickstart = 0;
-  uint32_t Conversion_Timeout_CPU_cycles = 0;
-
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
-    
-  /* Verification if ADC is not already stopped (on regular and injected      */
-  /* groups) to bypass this function if not needed.                           */
-  if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc))
-  {
-    /* Particular case of continuous auto-injection mode combined with        */
-    /* auto-delay mode.                                                       */
-    /* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not   */
-    /* injected group stop ADC_CR_JADSTP).                                    */
-    /* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1   */
-    /* (see reference manual).                                                */
-    if ((HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_JAUTO)) 
-         && (hadc->Init.ContinuousConvMode==ENABLE) 
-         && (hadc->Init.LowPowerAutoWait==ENABLE))
-    {
-      /* Use stop of regular group */
-      ConversionGroup = ADC_REGULAR_GROUP;
-      
-      /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */
-      while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == RESET)
-      {
-        if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES *4))
-        {
-          /* Update ADC state machine to error */
-          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-          
-          /* Set ADC error code to ADC IP internal error */
-          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-          
-          return HAL_ERROR;
-        }
-        Conversion_Timeout_CPU_cycles ++;
-      }
-
-      /* Clear JEOS */
-      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS);
-    }
-    
-    /* Stop potential conversion on going on regular group */
-    if (ConversionGroup != ADC_INJECTED_GROUP)
-    {
-      /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
-      if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) && 
-          HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS)     )
-      {
-        /* Stop conversions on regular group */
-        SET_BIT(hadc->Instance->CR, ADC_CR_ADSTP);
-      }
-    }
-
-    /* Stop potential conversion on going on injected group */
-    if (ConversionGroup != ADC_REGULAR_GROUP)
-    {
-      /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */
-      if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_JADSTART) && 
-          HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS)      )
-      {
-        /* Stop conversions on injected group */
-        SET_BIT(hadc->Instance->CR, ADC_CR_JADSTP);
-      }   
-    }
-
-    /* Selection of start and stop bits with respect to the regular or injected group */
-    switch(ConversionGroup)
-    {
-    case ADC_REGULAR_INJECTED_GROUP:
-        tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART);
-        break;
-    case ADC_INJECTED_GROUP:
-        tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART;
-        break;
-    /* Case ADC_REGULAR_GROUP only*/
-    default:
-        tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART;
-        break;
-    }
-    
-    /* Wait for conversion effectively stopped */
-
-    
-    tickstart = HAL_GetTick();
-      
-    while((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != RESET)
-    {
-      if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
-      {
-        /* Update ADC state machine to error */
-        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-        
-        /* Set ADC error code to ADC IP internal error */
-        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-        
-        return HAL_ERROR;
-      }
-    }
-    
-  } /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc)) */
-   
-  /* Return HAL status */
-  return HAL_OK;
-}
-
-
-
-/**
-  * @brief  Enable the selected ADC.
-  * @note   Prerequisite condition to use this function: ADC must be disabled
-  *         and voltage regulator must be enabled (done into HAL_ADC_Init()).
-  * @param  hadc: ADC handle
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
-{
-  uint32_t tickstart = 0;
-  
-  /* ADC enable and wait for ADC ready (in case of ADC is disabled or         */
-  /* enabling phase not yet completed: flag ADC ready not set yet).           */
-  /* Timeout implemented not to be stuck if ADC cannot be enabled (possible   */
-  /* causes: ADC clock not running, ...).                                     */
-  if (ADC_IS_ENABLE(hadc) == RESET)
-  {
-    /* Check if conditions to enable the ADC are fulfilled */
-    if (ADC_ENABLING_CONDITIONS(hadc) == RESET)
-    {
-      /* Update ADC state machine to error */
-      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-      
-      /* Set ADC error code to ADC IP internal error */
-      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-      
-      return HAL_ERROR;
-    }
-    
-    /* Enable the ADC peripheral */
-    ADC_ENABLE(hadc);
-    
-    
-    /* Wait for ADC effectively enabled */
-    tickstart = HAL_GetTick();  
-    
-    while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET)
-    {
-      /*  If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit 
-          has been cleared (after a calibration), ADEN bit is reset by the 
-          calibration logic.
-			    The workaround is to continue setting ADEN until ADRDY is becomes 1.
-          Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
-          4 ADC clock cycle duration */
-      ADC_ENABLE(hadc);
-
-      if((HAL_GetTick()-tickstart) > ADC_ENABLE_TIMEOUT)
-      {  
-        /* Update ADC state machine to error */
-        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-        
-        /* Set ADC error code to ADC IP internal error */
-       SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-      
-        return HAL_ERROR;
-      }
-    } 
-  }
-   
-  /* Return HAL status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disable the selected ADC.
-  * @note   Prerequisite condition to use this function: ADC conversions must be
-  *         stopped.
-  * @param  hadc: ADC handle
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
-{
-  uint32_t tickstart = 0;
-  
-  /* Verification if ADC is not already disabled:                             */
-  /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already  */
-  /* disabled.                                                                */
-  if (ADC_IS_ENABLE(hadc) != RESET )
-  {
-    /* Check if conditions to disable the ADC are fulfilled */
-    if (ADC_DISABLING_CONDITIONS(hadc) != RESET)
-    {
-      /* Disable the ADC peripheral */
-      ADC_DISABLE(hadc);
-    }
-    else
-    {
-      /* Update ADC state machine to error */
-      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-      
-      /* Set ADC error code to ADC IP internal error */
-      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-      
-      return HAL_ERROR;
-    }
-     
-    /* Wait for ADC effectively disabled */
-    tickstart = HAL_GetTick();
-    
-    while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
-    {
-      if((HAL_GetTick()-tickstart) > ADC_DISABLE_TIMEOUT)
-      { 
-        /* Update ADC state machine to error */
-        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-        
-        /* Set ADC error code to ADC IP internal error */
-        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-        
-        return HAL_ERROR;
-      }
-    }
-  }
-  
-  /* Return HAL status */
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  DMA transfer complete callback. 
-  * @param  hdma: pointer to DMA handle.
-  * @retval None
-  */
-void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
-{
-  /* Retrieve ADC handle corresponding to current DMA handle */
-  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- 
-  /* Update state machine on conversion status if not in error state */
-  if (HAL_IS_BIT_CLR(hadc->State, (HAL_ADC_STATE_ERROR_INTERNAL|HAL_ADC_STATE_ERROR_DMA)))
-  {
-    /* Update ADC state machine */
-    SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
-    /* Is it the end of the regular sequence ? */
-    if (HAL_IS_BIT_SET(hadc->Instance->ISR, ADC_FLAG_EOS))
-    {
-      /* Are conversions software-triggered ? */
-      if(ADC_IS_SOFTWARE_START_REGULAR(hadc))
-      {
-        /* Is CONT bit set ? */
-        if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == RESET)
-        {
-          /* CONT bit is not set, no more conversions expected */
-          CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
-          if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
-          { 
-            SET_BIT(hadc->State, HAL_ADC_STATE_READY);
-          }
-        }
-      }
-    }
-    else
-    {
-      /* DMA End of Transfer interrupt was triggered but conversions sequence
-         is not over. If DMACFG is set to 0, conversions are stopped. */
-      if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMACFG) == RESET)
-      {
-        /* DMACFG bit is not set, conversions are stopped. */
-        CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
-        if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
-        { 
-          SET_BIT(hadc->State, HAL_ADC_STATE_READY);
-        }
-      }
-    }
-    
-    /* Conversion complete callback */
-    HAL_ADC_ConvCpltCallback(hadc);   
-  }
-  else /* DMA or internal error occurred (or both) */
-  {
-    /* In case of internal error, */
-    if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
-    {
-      /* call Error Callback function */
-      HAL_ADC_ErrorCallback(hadc);
-    }
-  
-  }
-  
-
-}
-
-/**
-  * @brief  DMA half transfer complete callback. 
-  * @param  hdma: pointer to DMA handle.
-  * @retval None
-  */
-void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)   
-{
-  /* Retrieve ADC handle corresponding to current DMA handle */
-  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  /* Half conversion callback */
-  HAL_ADC_ConvHalfCpltCallback(hadc); 
-}
-
-/**
-  * @brief  DMA error callback.
-  * @param  hdma: pointer to DMA handle.
-  * @retval None
-  */
-void ADC_DMAError(DMA_HandleTypeDef *hdma)   
-{
-  /* Retrieve ADC handle corresponding to current DMA handle */
-  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  /* Change ADC state */
-  SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
-  
-  /* Set ADC error code to DMA error */
-  SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
-  
-  /* Error callback */
-  HAL_ADC_ErrorCallback(hadc); 
-}
-
-
-/**
-  * @}
-  */
-
-
-#endif /* HAL_ADC_MODULE_ENABLED */
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/src/stm32l4xx_hal_adc_ex.c b/stmhal/hal/l4/src/stm32l4xx_hal_adc_ex.c
deleted file mode 100644
index 96c8b517a7..0000000000
--- a/stmhal/hal/l4/src/stm32l4xx_hal_adc_ex.c
+++ /dev/null
@@ -1,2382 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_adc_ex.c
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   This file provides firmware functions to manage the following 
-  *          functionalities of the Analog to Digital Convertor (ADC)
-  *          peripheral:
-  *           + Calibration functions
-  *             ++ Calibration start-up
-  *             ++ Calibration value reading or setting 
-  *           + Operation functions
-  *             ++ Start, stop, get result of conversions of injected
-  *             groups, using 3 possible modes: polling or interruption.
-  *             ++ Multimode feature when available
-  *           + Control functions
-  *             ++ Configure channels on injected group
-  *           + State functions
-  *             ++ Injected group queues management
-  *  
-   @verbatim           
-  ==============================================================================
-                    ##### ADC specific features #####
-  ==============================================================================
-  [..] 
-  (#) Interrupt generation at the end of injected conversion and in case of 
-      injected queues overflow.
-  
-  (#) External trigger (timer or EXTI) with configurable polarity for  
-      injected groups.
-
-  (#) Multimode Dual mode when multimode feature is available.
-  
-  (#) Configurable DMA data storage in Multimode Dual mode.
-  
-  (#) Configurable delay between conversions in Dual interleaved mode.
-  
-  (#) ADC calibration.
-
-  (#) ADC channels selectable single/differential input.
-
-  (#) ADC Injected sequencer&channels configuration context queue.
-
-  (#) ADC offset on injected groups.
-  
-  (#) ADC oversampling.
-
-
-                     ##### How to use this driver #####
-  ==============================================================================
-    [..]
-  
-     (#) Configure the ADC parameters (conversion resolution, data alignment,  
-         continuous mode, ...) using the HAL_ADC_Init() function.
-
-     (#) Activate the ADC peripheral using one of the start functions: 
-         HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT() for injected conversions
-         or 
-         HAL_ADC_MultiModeStart_DMA() for multimode conversions when multimode
-         feature is available.
-  
-  
-     *** Channels to injected group configuration ***
-     =============================================    
-     [..]
-       (+) To configure the ADC Injected channels group features, use 
-           HAL_ADCEx_InjectedConfigChannel() functions.
-       (+) To read the ADC converted values, use the HAL_ADCEx_InjectedGetValue() 
-           function.  
-            
-            
-     *** Multimode ADCs configuration (when  multimode feature is available) ***
-     ========================================================================
-     [..]
-       (+) Multimode feature is available and applicable to Master and
-           Slave ADCs.
-       (+) Refer to "Channels to regular group configuration" description to  
-           configure the Master and Slave regular groups.        
-       (+) Select the Multi mode ADC  features (dual mode
-           simultaneous, interleaved, ...) and configure the DMA mode using 
-           HAL_ADCEx_MultiModeConfigChannel() functions. 
-       (+) Read the ADCs converted values using the HAL_ADCEx_MultiModeGetValue()
-           function.
-
-  
-    @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************  
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup ADCEx ADCEx
-  * @brief ADC Extended HAL module driver
-  * @{
-  */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-    
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/** @defgroup ADCEx_Private_Constants ADC Extended Private Constants
-  * @{
-  */
-
-#define ADC_JSQR_FIELDS  ((uint32_t)(ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\
-                                     ADC_JSQR_JSQ1  | ADC_JSQR_JSQ2 |\
-                                      ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 ))  /*!< ADC_JSQR fields of parameters that can be updated anytime
-                                                                             once the ADC is enabled */
-                                      
-#define ADC_CFGR2_INJ_FIELDS  ((uint32_t)(ADC_CFGR2_JOVSE | ADC_CFGR2_OVSR  |\
-                                       ADC_CFGR2_OVSS ))     /*!< ADC_CFGR2 injected oversampling parameters that can be updated
-                                                                  when no conversion is on-going (neither regular nor injected) */
-                                       
-/* Fixed timeout value for ADC calibration.                                   */
-/* Values defined to be higher than worst cases: low clock frequency,         */
-/* maximum prescalers.                                                        */
-/* Ex of profile low frequency : f_ADC at 0.14 MHz (minimum value             */
-/* according to Data sheet), calibration_time MAX = 112 / f_ADC               */
-/*           112 / 140,000 = 0.8 ms                                           */
-/* At maximum CPU speed (80 MHz), this means                                  */
-/*    0.8 ms * 80 MHz = 64000 CPU cycles                                      */  
-#define ADC_CALIBRATION_TIMEOUT         ((uint32_t) 64000)    /*!< ADC calibration time-out value */ 
-                                    
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions
-  * @{
-  */ 
-
-
-
-/** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions
-  * @brief    Extended IO operation functions
-  *
-@verbatim   
- ===============================================================================
-             ##### IO operation functions #####
- ===============================================================================  
-    [..]  This section provides functions allowing to:
-    
-      (+) Perform the ADC self-calibration for single or differential ending.
-      (+) Get calibration factors for single or differential ending.
-      (+) Set calibration factors for single or differential ending.
-          
-      (+) Start conversion of injected group.
-      (+) Stop conversion of injected group.
-      (+) Poll for conversion complete on injected group.
-      (+) Get result of injected channel conversion.
-      (+) Start conversion of injected group and enable interruptions.
-      (+) Stop conversion of injected group and disable interruptions.
-
-      (+) When multimode feature is available, start multimode and enable DMA transfer.
-      (+) Stop multimode and disable ADC DMA transfer.
-      (+) Get result of multimode conversion.
-
-
-
-@endverbatim
-  * @{
-  */
-  
-
-
-/**
-  * @brief  Perform an ADC automatic self-calibration
-  *         Calibration prerequisite: ADC must be disabled (execute this
-  *         function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
-  * @param  hadc: ADC handle.
-  * @param  SingleDiff: Selection of single-ended or differential input
-  *          This parameter can be one of the following values:
-  *            @arg @ref ADC_SINGLE_ENDED       Channel in mode input single ended
-  *            @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff)
-{
-  HAL_StatusTypeDef tmp_status = HAL_OK;
-  uint32_t WaitLoopIndex = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
-
-  /* Process locked */
-  __HAL_LOCK(hadc);
-   
-  /* Calibration prerequisite: ADC must be disabled. */
-   
-  /* Disable the ADC (if not already disabled) */
-  tmp_status = ADC_Disable(hadc);
-  
-  /* Check if ADC is effectively disabled */
-  if (tmp_status == HAL_OK)
-  {
-    /* Change ADC state */
-    /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_BUSY_INTERNAL bit */
-    ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_BUSY_INTERNAL);
-    
-    /* Select calibration mode single ended or differential ended */
-    MODIFY_REG(hadc->Instance->CR, ADC_CR_ADCALDIF, SingleDiff);
-
-    /* Start ADC calibration */
-    SET_BIT(hadc->Instance->CR, ADC_CR_ADCAL);
-
-
-    /* Wait for calibration completion */
-    while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADCAL))
-    {
-      WaitLoopIndex++;
-      if (WaitLoopIndex >= ADC_CALIBRATION_TIMEOUT)
-      {
-        /* Update ADC state machine to error */
-        /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_ERROR_INTERNAL bit */
-        ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL);
-        
-        /* Process unlocked */
-        __HAL_UNLOCK(hadc);
-        
-        return HAL_ERROR;
-      }
-    }
-    
-    /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
-    ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
-  }
-  else
-  {
-    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-    
-    /* Update ADC state machine to error */
-    tmp_status = HAL_ERROR; 
-  }
-  
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmp_status;
-}
-
-
-
-
-/**
-  * @brief  Get the calibration factor from automatic conversion result.
-  * @param  hadc: ADC handle.
-  * @param  SingleDiff: Selection of single-ended or differential input
-  *          This parameter can be one of the following values:
-  *            @arg @ref ADC_SINGLE_ENDED       Channel in mode input single ended
-  *            @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
-  * @retval Converted value
-  */
-uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); 
-  
-  /* Return the selected ADC calibration value */ 
-  if (SingleDiff == ADC_DIFFERENTIAL_ENDED)
-  {
-    return ADC_CALFACT_DIFF_GET(hadc->Instance->CALFACT);
-  }
-  else
-  {
-    return ((hadc->Instance->CALFACT) & ADC_CALFACT_CALFACT_S);
-  }
-}
-
-
-
-/**
-  * @brief  Set the calibration factor to overwrite automatic conversion result. ADC must be enabled and no conversion on going.
-  * @param  hadc: ADC handle.
-  * @param  SingleDiff: Selection of single-ended or differential input.
-  *          This parameter can be one of the following values:
-  *            @arg @ref ADC_SINGLE_ENDED       Channel in mode input single ended
-  *            @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
-  * @param  CalibrationFactor: Calibration factor (coded on 7 bits maximum)
-  * @retval HAL state
-  */
-HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
-{
-  HAL_StatusTypeDef tmp_status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); 
-  assert_param(IS_ADC_CALFACT(CalibrationFactor)); 
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  /* Verification of hardware constraints before modifying the calibration    */
-  /* factors register: ADC must be enabled, no conversion on going.           */
-  if ( (ADC_IS_ENABLE(hadc) != RESET)                            &&
-       (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)  )
-  {
-    /* Set the selected ADC calibration value */ 
-    if (SingleDiff == ADC_DIFFERENTIAL_ENDED)
-    {
-      MODIFY_REG(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D, ADC_CALFACT_DIFF_SET(CalibrationFactor));
-    }
-    else
-    {
-      MODIFY_REG(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_S, CalibrationFactor);
-    }
-  }
-  else
-  {
-    /* Update ADC state machine */
-    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-    
-    /* Update ADC state machine to error */
-    tmp_status = HAL_ERROR;
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmp_status;
-}
-
-
-
-/**
-  * @brief  Enable ADC, start conversion of injected group.
-  * @note   Interruptions enabled in this function: None.
-  * @note   Case of multimode enabled when multimode feature is available: 
-  *         HAL_ADCEx_InjectedStart() API must be called for ADC slave first, 
-  *         then for ADC master. 
-  *         For ADC slave, ADC is enabled only (conversion is not started).  
-  *         For ADC master, ADC is enabled and multimode conversion is started.
-  * @param  hadc: ADC handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmp_status = HAL_OK;  
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc))
-  {
-    return HAL_BUSY;
-  }
-  else
-  {
-  
-    /* In case of software trigger detection enabled, JQDIS must be set 
-      (which can be done only if ADSTART and JADSTART are both cleared).
-       If JQDIS is not set at that point, returns an error
-       - since software trigger detection is disabled. User needs to
-       resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.  
-       - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means 
-         the queue is empty */
-    if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == RESET)   
-    && (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS) == RESET))  
-    {
-      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 
-      return HAL_ERROR;
-    }
-
-      
-    /* Process locked */
-    __HAL_LOCK(hadc);
-      
-    /* Enable the ADC peripheral */
-    tmp_status = ADC_Enable(hadc);
-    
-    /* Start conversion if ADC is effectively enabled */
-    if (tmp_status == HAL_OK)
-    {
-      /* Check if a regular conversion is ongoing */
-      if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_REG_BUSY)) 
-      {
-        /* Reset ADC error code field related to injected conversions only */
-        CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);             
-      }
-      else
-      {
-        /* Set ADC error code to none */
-        ADC_CLEAR_ERRORCODE(hadc);        
-      }
-      /* Update ADC state */
-      /* Clear HAL_ADC_STATE_READY and HAL_ADC_STATE_INJ_EOC bits, set HAL_ADC_STATE_INJ_BUSY bit */
-      ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_INJ_EOC), HAL_ADC_STATE_INJ_BUSY);
-      
-      /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
-        - by default if ADC is Master or Independent or if multimode feature is not available
-        - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */
-      if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
-      {
-        CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
-      }      
-
-      
-      /* Clear injected group conversion flag */
-      /* (To ensure of no unknown state from potential previous ADC operations) */
-      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
-      
-      /* Enable conversion of injected group, if automatic injected conversion  */
-      /* is disabled.                                                           */
-      /* If software start has been selected, conversion starts immediately.    */
-      /* If external trigger has been selected, conversion will start at next   */
-      /* trigger event.                                                         */
-      /* Case of multimode enabled (when multimode feature is available):       */
-      /* if ADC is slave,                                                       */
-      /*    - ADC is enabled only (conversion is not started).                  */
-      /*    - if multimode only concerns regular conversion, ADC is enabled     */
-      /*     and conversion is started.                                         */
-      /* If ADC is master or independent,                                       */
-      /*    - ADC is enabled and conversion is started.                         */
-
-      /* Are injected conversions that of a dual Slave ? */      
-      if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc))
-      {
-        /* hadc is not the handle of a Slave ADC with dual injected conversions enabled:
-           set ADSTART only if JAUTO is cleared */
-        /* Process unlocked */
-        __HAL_UNLOCK(hadc);            
-        if (HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO))
-        {
-          SET_BIT(hadc->Instance->CR, ADC_CR_JADSTART) ;
-        }
-      }
-      else
-      {
-        /* hadc is the handle of a Slave ADC with dual injected conversions enabled:
-           ADSTART is not set */
-          SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
-        /* Process unlocked */
-        __HAL_UNLOCK(hadc);            
-      }
-    } 
-    else
-    {
-      /* Process unlocked */
-      __HAL_UNLOCK(hadc);    
-    } /* if (tmp_status == HAL_OK) */
-  
-  
-    /* Return function status */
-    return tmp_status;
-  } /*  if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc)) */
-}
-
-
-
-/**
-  * @brief  Stop conversion of injected channels, disable ADC peripheral if no regular conversion is on going.
-  * @note   If ADC must be disabled and if regular conversion
-  *         is on going, function HAL_ADC_Stop() must be used.
-  * @note   In case of auto-injection mode, HAL_ADC_Stop() must be used.
-  * @note   In case of multimode enabled (when multimode feature is available), 
-  *         HAL_ADCEx_InjectedStop() must be called for ADC master first, then for ADC slave.
-  *         For ADC master, conversion is stopped and ADC is disabled. 
-  *         For ADC slave, ADC is disabled only (conversion stop of ADC master
-  *         has already stopped conversion of ADC slave).
-  * @param  hadc: ADC handle.
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
-{  
-  HAL_StatusTypeDef tmp_status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  /* 1. Stop potential conversion on going on injected group only. */
-  tmp_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
-  
-  /* Disable ADC peripheral if injected conversions are effectively stopped   */
-  /* and if no conversion on regular group is on-going                       */
-  if (tmp_status == HAL_OK)
-  {
-    if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
-    {
-      /* 2. Disable the ADC peripheral */
-      tmp_status = ADC_Disable(hadc);
-      
-      /* Check if ADC is effectively disabled */
-      if (tmp_status == HAL_OK)
-      {
-        /* Change ADC state */
-      /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
-      ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);
-      }
-    }
-    /* Conversion on injected group is stopped, but ADC not disabled since    */
-    /* conversion on regular group is still running.                          */
-    else
-    {
-      /* Clear HAL_ADC_STATE_INJ_BUSY bit */
-      CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); 
-    }
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmp_status;
-}
-
-
-
-/**
-  * @brief  Wait for injected group conversion to be completed.
-  * @param  hadc: ADC handle
-  * @param  Timeout: Timeout value in millisecond.
-  * @note   Depending on hadc->Init.EOCSelection, JEOS or JEOC is 
-  *         checked and cleared depending on AUTDLY bit status.    
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
-{
-  uint32_t           tickstart;
-  uint32_t           tmp_Flag_End        = 0x00;
-  ADC_TypeDef        *tmpADC_Master;
-  uint32_t           tmp_cfgr            = 0x00;
-  uint32_t           tmp_cfgr_jqm_autdly = 0x00;   
-  uint32_t           tmp_jeos_raised     = 0x01; /* by default, assume that JEOS is set, 
-                                                    tmp_jeos_raised will be corrected
-                                                    accordingly during API execution */       
- 
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
-  /* If end of sequence selected */
-  if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
-  {
-    tmp_Flag_End = ADC_FLAG_JEOS;
-  }
-  else /* end of conversion selected */
-  {
-    tmp_Flag_End = ADC_FLAG_JEOC;
-  }
-  
-  /* Get timeout */
-  tickstart = HAL_GetTick();  
-     
-   /* Wait until End of Conversion or Sequence flag is raised */
-  while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_End))
-  {
-    /* Check if timeout is disabled (set to infinite wait) */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
-      {
-        /* Update ADC state machine to timeout */
-        SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
-        
-        /* Process unlocked */
-        __HAL_UNLOCK(hadc);
-        
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  
-  /* Next, to clear the polled flag as well as to update the handle State,
-     JEOS is checked and the relevant configuration registers are retrieved. 
-     JQM, JAUTO and CONT bits will have to be read for the State update,
-     AUTDLY for JEOS clearing. */
-  /*   1. Check whether or not JEOS is set */
-  if (HAL_IS_BIT_CLR(hadc->Instance->ISR, ADC_FLAG_JEOS))
-  {
-    tmp_jeos_raised = 0;   
-  }
-  /*  2. Check whether or not hadc is the handle of a Slave ADC with dual
-        injected conversions enabled. */
-  if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc) == RESET)  
-  {
-    /* hadc is not the handle of a Slave ADC with dual injected conversions enabled:
-        check JQM and AUTDLY bits directly in ADC CFGR register */     
-    tmp_cfgr_jqm_autdly = READ_REG(hadc->Instance->CFGR);  
-  }
-  else
-  {
-    /* hadc is the handle of a Slave ADC with dual injected conversions enabled:
-        need to check JQM and AUTDLY bits of Master ADC CFGR register */    
-    tmpADC_Master = ADC_MASTER_REGISTER(hadc);
-    tmp_cfgr_jqm_autdly = READ_REG(tmpADC_Master->CFGR);
-  }  
-  /* 3. Check whether or not hadc is the handle of a Slave ADC with dual
-        regular conversions enabled. */ 
-  if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
-  {
-    /* hadc is not the handle of a Slave ADC with dual regular conversions enabled:
-       check JAUTO and CONT bits directly in ADC CFGR register */        
-    tmp_cfgr = READ_REG(hadc->Instance->CFGR); 
-  }
-  else
-  {
-    /* hadc is not the handle of a Slave ADC with dual regular conversions enabled:
-      check JAUTO and CONT bits of Master ADC CFGR register */  
-    tmpADC_Master = ADC_MASTER_REGISTER(hadc);
-    tmp_cfgr = READ_REG(tmpADC_Master->CFGR); 
-  }        
-  
-  
-  
-  /* Clear polled flag */                         
-  if (tmp_Flag_End == ADC_FLAG_JEOS)
-  {
-    /* Clear end of sequence JEOS flag of injected group if low power feature */
-    /* "LowPowerAutoWait " is disabled, to not interfere with this feature.   */
-    /* For injected groups, no new conversion will start before JEOS is       */
-    /* cleared.                                                               */
-    /* Note that 1. reading ADCx_JDRy clears JEOC.                            */ 
-    /*           2. in multimode with dual injected conversions enabled (when */
-    /*              multimode feature is available), Master AUTDLY bit is     */
-    /*              checked.                                                  */        
-    if (READ_BIT (tmp_cfgr_jqm_autdly, ADC_CFGR_AUTDLY) == RESET)
-    {
-      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
-    }
-  }
-  else
-  {
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);    
-  }  
-  
-  
-  /* Update ADC state machine */
-  SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); 
-  /* Are injected conversions over ? This is the case if JEOS is set AND
-        - injected conversions are software-triggered when injected queue management is disabled
-        OR
-        - auto-injection is enabled, continuous mode is disabled,
-          and regular conversions are software-triggered */
-          
-  if (tmp_jeos_raised)
-  {  
-    if ((ADC_IS_SOFTWARE_START_INJECTED(hadc) && (READ_BIT(tmp_cfgr_jqm_autdly, ADC_CFGR_JQM) != ADC_CFGR_JQM))  
-       && (!((READ_BIT(tmp_cfgr, (ADC_CFGR_JAUTO|ADC_CFGR_CONT)) == (ADC_CFGR_JAUTO|ADC_CFGR_CONT)) &&    
-           (ADC_IS_SOFTWARE_START_REGULAR(hadc)))    ))           
-    {
-      /* Clear HAL_ADC_STATE_INJ_BUSY bit */
-      CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); 
-      /* If no regular conversion on-going, set HAL_ADC_STATE_READY bit */                   
-      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
-      { 
-        SET_BIT(hadc->State, HAL_ADC_STATE_READY); 
-      }           
-    }      
-  }
-
-
-    
-  /* Return API HAL status */
-  return HAL_OK;
-}
-
-
-
-/**
-  * @brief  Enable ADC, start conversion of injected group with interruption.
-  * @note   Interruptions enabled in this function according to initialization
-  *         setting : JEOC (end of conversion) or JEOS (end of sequence) 
-  * @note   Case of multimode enabled (when multimode feature is enabled): 
-  *         HAL_ADCEx_InjectedStart_IT() API must be called for ADC slave first, 
-  *         then for ADC master. 
-  *         For ADC slave, ADC is enabled only (conversion is not started).  
-  *         For ADC master, ADC is enabled and multimode conversion is started.
-  * @param  hadc: ADC handle.
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmp_status = HAL_OK;  
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc))
-  {
-    return HAL_BUSY;
-  }
-  else
-  {
-
-    /* In case of software trigger detection enabled, JQDIS must be set 
-      (which can be done only if ADSTART and JADSTART are both cleared).
-       If JQDIS is not set at that point, returns an error
-       - since software trigger detection is disabled. User needs to
-       resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.  
-       - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means 
-         the queue is empty */
-    if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == RESET)   
-    && (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS) == RESET))  
-    {
-      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 
-      return HAL_ERROR;
-    }
-
-    /* Process locked */
-    __HAL_LOCK(hadc);
-      
-    /* Enable the ADC peripheral */
-    tmp_status = ADC_Enable(hadc);
-    
-    /* Start conversion if ADC is effectively enabled */
-    if (tmp_status == HAL_OK)
-    {
-      /* Check if a regular conversion is ongoing */
-      if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_REG_BUSY))
-      {
-        /* Reset ADC error code field related to injected conversions only */
-        CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);            
-      }
-      else
-      {
-        /* Set ADC error code to none */
-        ADC_CLEAR_ERRORCODE(hadc);
-      }
-      /* Clear HAL_ADC_STATE_READY and HAL_ADC_STATE_INJ_EOC bits, set HAL_ADC_STATE_INJ_BUSY bit */
-      ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_INJ_EOC), HAL_ADC_STATE_INJ_BUSY);
-      
-      /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
-        - by default if ADC is Master or Independent or if multimode feature is not available
-        - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */
-      if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
-      {
-        CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
-      }      
-    
-      /* Clear injected group conversion flag */
-      /* (To ensure of no unknown state from potential previous ADC operations) */
-      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
-      
-      /* Enable ADC Injected context queue overflow interrupt if this feature   */
-      /* is enabled.                                                            */
-      if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != RESET)
-      {
-        __HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF);
-      }
-      
-      /* Enable ADC end of conversion interrupt */
-      switch(hadc->Init.EOCSelection)
-      {
-        case ADC_EOC_SEQ_CONV: 
-          __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
-          __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
-          break;
-        /* case ADC_EOC_SINGLE_CONV */
-        default:
-          __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);      
-          __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
-          break;
-      }
-      
-      /* Enable conversion of injected group, if automatic injected conversion  */
-      /* is disabled.                                                           */
-      /* If software start has been selected, conversion starts immediately.    */
-      /* If external trigger has been selected, conversion will start at next   */
-      /* trigger event.                                                         */
-      /* Case of multimode enabled (when multimode feature is available):       */
-      /* if ADC is slave,                                                       */
-      /*    - ADC is enabled only (conversion is not started),                  */
-      /*    - if multimode only concerns regular conversion, ADC is enabled     */
-      /*     and conversion is started.                                         */
-      /* If ADC is master or independent,                                       */
-      /*    - ADC is enabled and conversion is started.                         */
-
-      /* Are injected conversions that of a dual Slave ? */      
-      if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc))
-      {
-        /* hadc is not the handle of a Slave ADC with dual injected conversions enabled:
-           set ADSTART only if JAUTO is cleared */
-        /* Process unlocked */
-        __HAL_UNLOCK(hadc);            
-        if (HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO))
-        {
-          SET_BIT(hadc->Instance->CR, ADC_CR_JADSTART) ;
-        }
-      }
-      else
-      {
-        /* hadc is the handle of a Slave ADC with dual injected conversions enabled:
-           ADSTART is not set */
-          SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
-        /* Process unlocked */
-        __HAL_UNLOCK(hadc);          
-      }
-    }
-    else
-    {
-      /* Process unlocked */
-      __HAL_UNLOCK(hadc);
-    }
-    
-    /* Return function status */
-    return tmp_status;
-}
-}
-
-
-
-/**
-  * @brief  Stop conversion of injected channels, disable interruption of end-of-conversion. 
-  * @note   Disable ADC peripheral if no regular conversion
-  *         is on going.
-  * @note   If ADC must be disabled and if regular conversion
-  *         is on going, function HAL_ADC_Stop must be used first.
-  * @note   Case of multimode enabled (when multimode feature is available): 
-  *         HAL_ADCEx_InjectedStop_IT() API must be called for ADC master first, 
-  *         then for ADC slave.
-  *         For ADC master, conversion is stopped and ADC is disabled. 
-  *         For ADC slave, ADC is disabled only (conversion stop of ADC master
-  *         has already stopped conversion of ADC slave).
-  * @note   In case of auto-injection mode, HAL_ADC_Stop() must be used.
-  * @param  hadc: ADC handle
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
-{ 
-  HAL_StatusTypeDef tmp_status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  /* 1. Stop potential conversion on going on injected group only. */
-  tmp_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
-  
-  /* Disable ADC peripheral if injected conversions are effectively stopped   */
-  /* and if no conversion on the other group (regular group) is intended to   */
-  /* continue.                                                                */
-  if (tmp_status == HAL_OK)
-  {
-    /* Disable ADC end of conversion interrupt for injected channels */
-    __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_FLAG_JQOVF));
-    
-    if ((ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET))
-    {
-      /* 2. Disable the ADC peripheral */
-      tmp_status = ADC_Disable(hadc);
-      
-      /* Check if ADC is effectively disabled */
-      if (tmp_status == HAL_OK)
-      {
-        /* Change ADC state */
-        /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
-        ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);
-      }
-    }
-    /* Conversion on injected group is stopped, but ADC not disabled since    */
-    /* conversion on regular group is still running.                          */
-    else
-    {
-      /* Clear HAL_ADC_STATE_INJ_BUSY bit */
-      CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); 
-    }
-  }
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmp_status;
-}
-
-
-/**
-  * @brief  Enable ADC, start MultiMode conversion and transfer regular results through DMA.
-  * @note   Multimode must have been previously configured using 
-  *         HAL_ADCEx_MultiModeConfigChannel() function.
-  *         Interruptions enabled in this function:
-  *          overrun, DMA half transfer, DMA transfer complete. 
-  *         Each of these interruptions has its dedicated callback function.
-  * @note   State field of Slave ADC handle is not updated in this configuration: 
-  *          user should not rely on it for information related to Slave regular 
-  *         conversions.                                                                          
-  * @param  hadc: ADC handle of ADC master (handle of ADC slave must not be used)
-  * @param  pData: Destination Buffer address.
-  * @param  Length: Length of data to be transferred from ADC peripheral to memory (in bytes).
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
-{
-  HAL_StatusTypeDef tmp_status = HAL_OK;
-  ADC_HandleTypeDef tmphadcSlave;
-  ADC_Common_TypeDef *tmpADC_Common;
-
-  /* Check the parameters */
-  assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
-  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
-  assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
-  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
-  
-  if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc))
-  {
-    return HAL_BUSY;
-  }
-  else
-  {
-    /* Process locked */
-    __HAL_LOCK(hadc);
-
-    /* Set a temporary handle of the ADC slave associated to the ADC master   */
-    ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
-  
-    if (tmphadcSlave.Instance == NULL)
-    {
-      /* Update ADC state machine to error */
-      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-    
-      /* Process unlocked */
-      __HAL_UNLOCK(hadc);
-    
-      return HAL_ERROR;
-    }
-    
-  
-    /* Enable the ADC peripherals: master and slave (in case if not already   */
-    /* enabled previously)                                                    */
-    tmp_status = ADC_Enable(hadc);
-    if (tmp_status == HAL_OK)
-    {
-      tmp_status = ADC_Enable(&tmphadcSlave);
-    }
-  
-    /* Start multimode conversion of ADCs pair */
-    if (tmp_status == HAL_OK)
-    {
-      /* Update Master State */
-      /* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */
-      ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_REG_EOC|HAL_ADC_STATE_REG_OVR|HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY);
-
-       
-      /* Set ADC error code to none */
-      ADC_CLEAR_ERRORCODE(hadc);
-      
-      
-      /* Set the DMA transfer complete callback */
-      hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
-         
-      /* Set the DMA half transfer complete callback */
-      hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
-      
-      /* Set the DMA error callback */
-      hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
-      
-      /* Pointer to the common control register  */
-      tmpADC_Common = ADC_COMMON_REGISTER(hadc);
-      
-      
-      /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */
-      /* start (in case of SW start):                                           */
-  
-      /* Clear regular group conversion flag and overrun flag */
-      /* (To ensure of no unknown state from potential previous ADC operations) */
-      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
-      
-      /* Enable ADC overrun interrupt */
-      __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
-  
-      /* Start the DMA channel */
-      HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length);
-          
-      /* Enable conversion of regular group.                                    */
-      /* Process unlocked */
-      __HAL_UNLOCK(hadc);      
-      /* If software start has been selected, conversion starts immediately.    */
-      /* If external trigger has been selected, conversion will start at next   */
-      /* trigger event.                                                         */
-      SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
-
-    }
-    else
-    {
-      /* Process unlocked */
-      __HAL_UNLOCK(hadc);
-    }
-  
-    /* Return function status */
-    return tmp_status;
-  }
-}
-
-/**
-  * @brief  Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral.
-  * @note   Multimode is kept enabled after this function. MultiMode DMA bits
-  *         (MDMA and DMACFG bits of common CCR register) are maintained. To disable 
-  *         Multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be 
-  *         reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
-  *         resort to HAL_ADCEx_DisableMultiMode() API.
-  * @note   In case of DMA configured in circular mode, function 
-  *         HAL_ADC_Stop_DMA() must be called after this function with handle of
-  *         ADC slave, to properly disable the DMA channel.
-  * @param  hadc: ADC handle of ADC master (handle of ADC slave must not be used)
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmp_status = HAL_OK;
-  uint32_t tickstart;
-  ADC_HandleTypeDef tmphadcSlave;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
- 
-  /* 1. Stop potential multimode conversion on going, on regular and injected groups */
-  tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
-
-  /* Disable ADC peripheral if conversions are effectively stopped */
-  if (tmp_status == HAL_OK)
-  {                                      
-    /* Set a temporary handle of the ADC slave associated to the ADC master   */
-    ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
-    
-    if (tmphadcSlave.Instance == NULL)
-    {
-      /* Update ADC state machine to error */
-      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-      
-      /* Process unlocked */
-      __HAL_UNLOCK(hadc);
-      
-      return HAL_ERROR;
-    }
-    
-    /* Procedure to disable the ADC peripheral: wait for conversions          */
-    /* effectively stopped (ADC master and ADC slave), then disable ADC       */
-    
-    /* 1. Wait until ADSTP=0 for ADC master and ADC slave*/
-    tickstart = HAL_GetTick();  
-
-    while(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc)          || 
-          ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave)   )
-    {
-      if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
-      {
-        /* Update ADC state machine to error */
-        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-        
-        /* Process unlocked */
-        __HAL_UNLOCK(hadc);
-        
-        return HAL_ERROR;
-      }
-    }
-    
-    /* Disable the DMA channel (in case of DMA in circular mode or stop       */
-    /* while DMA transfer is on going)                                        */
-    /* Note: DMA channel of ADC slave should be stopped after this function   */
-    /*       with HAL_ADC_Stop_DMA() API.                                     */
-    tmp_status = HAL_DMA_Abort(hadc->DMA_Handle);
-    
-    /* Check if DMA channel effectively disabled */
-    if (tmp_status == HAL_ERROR)
-    {
-      /* Update ADC state machine to error */
-      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); 
-    }
-    
-    /* Disable ADC overrun interrupt */
-    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
-    
-    
-    
-    /* 2. Disable the ADC peripherals: master and slave */
-    /* Update "tmp_status" only if DMA channel disabling passed, to keep in */
-    /* memory a potential failing status.                                     */
-    if (tmp_status == HAL_OK)
-    {
-      /* Check if ADC are effectively disabled */
-      if ((ADC_Disable(hadc) == HAL_OK)         &&
-          (ADC_Disable(&tmphadcSlave) == HAL_OK)   )
-      {
-        tmp_status = HAL_OK;
-      }
-    }
-    else
-    {
-      ADC_Disable(hadc);
-      ADC_Disable(&tmphadcSlave);
-    }
-    /* Change ADC state (ADC master) */
-    /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
-    ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);
-    
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmp_status;
-}
-
-
-/**
-  * @brief  Return the last ADC Master and Slave regular conversions results when in multimode configuration.
-  * @param  hadc: ADC handle of ADC Master (handle of ADC Slave must not be used)
-  * @retval The converted data values.
-  */
-uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
-{
-  ADC_Common_TypeDef *tmpADC_Common;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
-  
-  /* Pointer to the common control register  */
-  tmpADC_Common = ADC_COMMON_REGISTER(hadc);
-  
-  /* Return the multi mode conversion value */
-  return tmpADC_Common->CDR;
-}
-
-
-/**
-  * @brief  Get ADC injected group conversion result.
-  * @param  hadc: ADC handle
-  * @param  InjectedRank: the converted ADC injected rank.
-  *          This parameter can be one of the following values:
-  *            @arg @ref ADC_INJECTED_RANK_1 Injected Channel1 selected
-  *            @arg @ref ADC_INJECTED_RANK_2 Injected Channel2 selected
-  *            @arg @ref ADC_INJECTED_RANK_3 Injected Channel3 selected
-  *            @arg @ref ADC_INJECTED_RANK_4 Injected Channel4 selected
-  * @note   Reading JDRy register automatically clears JEOC flag. To reset JEOS 
-  *         flag the user must resort to the macro 
-  *         __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS).    
-  * @retval None
-  */
-uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
-{
-  uint32_t tmp_jdr = 0;
-
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
-  
-  
-  /* Get ADC converted value */ 
-  switch(InjectedRank)
-  {  
-    case ADC_INJECTED_RANK_4: 
-      tmp_jdr = hadc->Instance->JDR4;
-      break;
-    case ADC_INJECTED_RANK_3: 
-      tmp_jdr = hadc->Instance->JDR3;
-      break;
-    case ADC_INJECTED_RANK_2: 
-      tmp_jdr = hadc->Instance->JDR2;
-      break;
-    case ADC_INJECTED_RANK_1:
-    default:
-      tmp_jdr = hadc->Instance->JDR1;
-      break;
-  }
-  
-  /* Return ADC converted value */ 
-  return tmp_jdr;
-}
-
-/**
-  * @brief  Injected conversion complete callback in non-blocking mode. 
-  * @param  hadc: ADC handle
-  * @retval None
-  */
-__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
-
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_ADCEx_InjectedConvCpltCallback must be implemented in the user file.
-  */
-}
-
-
-/**
-  * @brief  Injected context queue overflow callback. 
-  * @note   This callback is called if injected context queue is enabled
-            (parameter "QueueInjectedContext" in injected channel configuration)
-            and if a new injected context is set when queue is full (maximum 2
-            contexts).
-  * @param  hadc: ADC handle
-  * @retval None
-  */
-__weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
-
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file.
-  */
-}
-
-/**
-  * @brief  Analog watchdog 2 callback in non-blocking mode.        
-  * @param  hadc: ADC handle
-  * @retval None
-  */
-__weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
-
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file.
-  */
-}
-
-/**
-  * @brief  Analog watchdog 3 callback in non-blocking mode.        
-  * @param  hadc: ADC handle
-  * @retval None
-  */
-__weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
-
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file.
-  */
-}
-
-
-/**
-  * @brief  End Of Sampling callback in non-blocking mode.        
-  * @param  hadc: ADC handle
-  * @retval None
-  */
-__weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef* hadc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
-
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file.
-  */
-}
-
-
-
-/**  
-  * @brief  Stop ADC conversion of regular groups, disable ADC peripheral if no injected conversion is on-going.
-  * @param  hadc: ADC handle
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc)
-{ 
-  HAL_StatusTypeDef tmp_status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  /* 1. Stop potential regular conversion on going */
-  tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
-  
-  /* Disable ADC peripheral if regular conversions are effectively stopped 
-     and if no injected conversions are on-going */
-  if (tmp_status == HAL_OK)
-  {
-    /* Clear HAL_ADC_STATE_REG_BUSY bit */ 
-    CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 
-     
-    if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
-    {
-      /* 2. Disable the ADC peripheral */
-      tmp_status = ADC_Disable(hadc);
-      
-      /* Check if ADC is effectively disabled */
-      if (tmp_status == HAL_OK)
-      {
-        /* Change ADC state */
-        /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
-        ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
-      }
-    }
-    /* Conversion on injected group is stopped, but ADC not disabled since    */
-    /* conversion on regular group is still running.                          */
-    else
-    {
-      SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
-    }
-  }
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmp_status;
-}
-
-
-/**  
-  * @brief  Stop ADC conversion of regular groups when interruptions are enabled, disable ADC peripheral if no injected conversion is on-going.
-  * @param  hadc: ADC handle
-  * @retval HAL status.
-  */  
-HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmp_status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  /* 1. Stop potential regular conversion on going */
-  tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
-  
-  /* Disable ADC peripheral if conversions are effectively stopped
-    and if no injected conversion is on-going */
-  if (tmp_status == HAL_OK)
-  {
-    /* Clear HAL_ADC_STATE_REG_BUSY bit */ 
-    CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);  
-     
-    /* Disable all regular-related interrupts */
-    __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
-    
-    /* 2. Disable ADC peripheral if no injected conversions are on-going */
-    if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
-    {     
-      tmp_status = ADC_Disable(hadc);
-      /* if no issue reported */
-      if (tmp_status == HAL_OK)
-      {
-        /* Change ADC state */
-        /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
-        ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
-      }
-    }
-    else
-    {
-      SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
-    }
-  }
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmp_status;
-}
-
-
-/**
-  * @brief  Stop ADC conversion of regular groups and disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.
-  * @note   HAL_ADCEx_RegularStop_DMA() function is dedicated to single-ADC mode only. 
-  *         For multimode (when multimode feature is available), 
-  *         HAL_ADCEx_RegularMultiModeStop_DMA() API must be used.
-  * @param  hadc: ADC handle
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc)
-{  
-  HAL_StatusTypeDef tmp_status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  /* 1. Stop potential regular conversion on going */
-  tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
-  
-  /* Disable ADC peripheral if conversions are effectively stopped 
-     and if no injected conversion is on-going */
-  if (tmp_status == HAL_OK)
-  {
-    /* Clear HAL_ADC_STATE_REG_BUSY bit */ 
-    CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
-    
-    /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
-    CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); 
-    
-    /* Disable the DMA channel (in case of DMA in circular mode or stop while */
-    /* while DMA transfer is on going)                                        */
-    tmp_status = HAL_DMA_Abort(hadc->DMA_Handle);   
-    
-    /* Check if DMA channel effectively disabled */
-    if (tmp_status != HAL_OK)
-    {
-      /* Update ADC state machine to error */
-      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);   
-    }
-    
-    /* Disable ADC overrun interrupt */
-    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
-    
-    /* 2. Disable the ADC peripheral */
-    /* Update "tmp_status" only if DMA channel disabling passed, to keep in */
-    /* memory a potential failing status.                                     */
-    if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
-    {    
-      if (tmp_status == HAL_OK)
-      {
-        tmp_status = ADC_Disable(hadc);
-      }
-      else
-      {
-        ADC_Disable(hadc);
-      }
-
-      /* Check if ADC is effectively disabled */
-      if (tmp_status == HAL_OK)
-      {
-        /* Change ADC state */
-        /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
-        ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);      
-      }
-    }
-    else
-    {
-      SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);  
-    }
-  }
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmp_status;
-}
-
-
-/**
-  * @brief  Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.
-  * @note   Multimode is kept enabled after this function. Multimode DMA bits
-  *         (MDMA and DMACFG bits of common CCR register) are maintained. To disable 
-  *         multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be 
-  *         reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
-  *         resort to HAL_ADCEx_DisableMultiMode() API.  
-  * @note   In case of DMA configured in circular mode, function 
-  *         HAL_ADCEx_RegularStop_DMA() must be called after this function with handle of
-  *         ADC slave, to properly disable the DMA channel.
-  * @param  hadc: ADC handle of ADC master (handle of ADC slave must not be used)
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmp_status = HAL_OK;
-  uint32_t tickstart;
-  ADC_HandleTypeDef tmphadcSlave;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
- 
-  /* 1. Stop potential multimode conversion on going, on regular groups */
-  tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
-
-  /* Disable ADC peripheral if conversions are effectively stopped */
-  if (tmp_status == HAL_OK)
-  { 
-    /* Clear HAL_ADC_STATE_REG_BUSY bit */                                     
-    CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
-    
-    /* Set a temporary handle of the ADC slave associated to the ADC master   */
-    ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
-    
-    if (tmphadcSlave.Instance == NULL)
-    {
-      /* Update ADC state machine to error */
-      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-      
-      /* Process unlocked */
-      __HAL_UNLOCK(hadc);
-      
-      return HAL_ERROR;
-    }
-    
-    /* Procedure to disable the ADC peripheral: wait for conversions          */
-    /* effectively stopped (ADC master and ADC slave), then disable ADC       */
-    
-    /* 1. Wait until ADSTP=0 for ADC master and ADC slave*/
-    tickstart = HAL_GetTick();  
-
-    while(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc)          || 
-          ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave)   )
-    {
-      if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
-      {
-        /* Update ADC state machine to error */
-        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-        
-        /* Process unlocked */
-        __HAL_UNLOCK(hadc);
-        
-        return HAL_ERROR;
-      }
-    }
-    
-    /* Disable the DMA channel (in case of DMA in circular mode or stop       */
-    /* while DMA transfer is on going)                                        */
-    /* Note: DMA channel of ADC slave should be stopped after this function   */
-    /* with HAL_ADCEx_RegularStop_DMA() API.                                  */
-    tmp_status = HAL_DMA_Abort(hadc->DMA_Handle);
-    
-    /* Check if DMA channel effectively disabled */
-    if (tmp_status != HAL_OK)
-    {
-      /* Update ADC state machine to error */
-      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);  
-    }
-    
-    /* Disable ADC overrun interrupt */
-    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
-    
-    
-    
-    /* 2. Disable the ADC peripherals: master and slave if no injected        */
-    /*   conversion is on-going.                                              */
-    /* Update "tmp_status" only if DMA channel disabling passed, to keep in */
-    /* memory a potential failing status.                                     */
-    if (tmp_status == HAL_OK)
-    {
-       if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
-       {  
-         tmp_status =  ADC_Disable(hadc);
-         if (tmp_status == HAL_OK)
-         {
-           if (ADC_IS_CONVERSION_ONGOING_INJECTED(&tmphadcSlave) == RESET)
-           {
-             tmp_status =  ADC_Disable(&tmphadcSlave);
-           }
-         }
-       }
-       
-       if (tmp_status == HAL_OK)
-       {
-         /* Both Master and Slave ADC's could be disabled. Update Master State */
-         /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
-         ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
-       }
-       else
-       {
-         /* injected (Master or Slave) conversions are still on-going,
-            no Master State change */
-       }
-          
-
-    }
-
-    
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmp_status;
-}
-
-
-/**
-  * @}
-  */
-
-/** @defgroup ADCEx_Exported_Functions_Group2 Extended Peripheral Control functions
-  * @brief    Extended Peripheral Control functions
-  *
-@verbatim   
- ===============================================================================
-             ##### Peripheral Control functions #####
- ===============================================================================  
-    [..]  This section provides functions allowing to:
-      (+) Configure channels on injected group
-      (+) Configure multimode when multimode feature is available
-      (+) Enable or Disable Injected Queue
-      (+) Disable ADC voltage regulator
-      (+) Enter ADC deep-power-down mode      
-      
-      
-@endverbatim
-  * @{
-  */
-
-/**  
-  * @brief  Configure the ADC injected group and the selected channel to be linked to the injected group.
-  * @note   Possibility to update parameters on the fly:
-  *         This function initializes injected group, consecutive calls to this 
-  *         function can be used to reconfigure some parameters of structure
-  *         "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC.
-  *         The setting of these parameters is conditioned to ADC state.
-  *         For parameters constraints, see comments of structure 
-  *         "ADC_InjectionConfTypeDef".
-  * @note   In case of usage of internal measurement channels (Vbat/VrefInt/TempSensor),
-  *         The internal paths can be disabled using function HAL_ADC_DeInit().
-  * @note   To reset injected sequencer, function HAL_ADCEx_InjectedStop() can
-  *         be used.
-  * @note   Caution: For Injected Context Queue use, a context must be fully 
-  *         defined before start of injected conversion. All channels are configured 
-  *         consecutively for the same ADC instance. Therefore, the number of calls to 
-  *         HAL_ADCEx_InjectedConfigChannel() must be equal to the value of parameter 
-  *         InjectedNbrOfConversion for each context.
-  *  - Example 1: If 1 context is intended to be used (or if there is no use of the 
-  *    Injected Queue Context feature) and if the context contains 3 injected ranks 
-  *    (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be  
-  *    called once for each channel (i.e. 3 times) before starting a conversion.   
-  *    This function must not be called to configure a 4th injected channel:   
-  *    it would start a new context into context queue.
-  *  - Example 2: If 2 contexts are intended to be used and each of them contains 
-  *    3 injected ranks (InjectedNbrOfConversion = 3),  
-  *    HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and  
-  *    for each context (3 channels x 2 contexts = 6 calls). Conversion can  
-  *    start once the 1st context is set, that is after the first three 
-  *    HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly.
-  * @param  hadc: ADC handle
-  * @param  sConfigInjected: Structure of ADC injected group and ADC channel for
-  *         injected group.
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
-{
-  HAL_StatusTypeDef tmp_status = HAL_OK;
-  ADC_Common_TypeDef *tmpADC_Common;
-  uint32_t tmpOffsetShifted;
-  uint32_t wait_loop_index = 0;
-  
-
-  uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
-  assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfigInjected->InjectedSingleDiff));
-  assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
-  assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->QueueInjectedContext));
-  assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
-  assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv));
-  assert_param(IS_ADC_OFFSET_NUMBER(sConfigInjected->InjectedOffsetNumber));
-  assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset));
-  assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjecOversamplingMode));
-  
-  if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
-  {
-    assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
-    assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
-    assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
-  }
-  
-  
-  /* if JOVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is  
-     ignored (considered as reset) */
-  assert_param(!((sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) && (sConfigInjected->InjecOversamplingMode == ENABLE))); 
-    
-  /* JDISCEN and JAUTO bits can't be set at the same time  */
-  assert_param(!((sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE))); 
-
-  /*  DISCEN and JAUTO bits can't be set at the same time */
-  assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE)));  
-
-  /* Verification of channel number */
-  if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
-  {
-     assert_param(IS_ADC_CHANNEL(hadc, sConfigInjected->InjectedChannel));
-  }
-  else
-  {
-    assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfigInjected->InjectedChannel));
-  }                
- 
-    
-  /* Process locked */
-  __HAL_LOCK(hadc);
-
-
-
-  /* Configuration of Injected group sequencer.                               */
-  /* Hardware constraint: Must fully define injected context register JSQR    */
-  /* before make it entering into injected sequencer queue.                   */
-  /*                                                                          */
-  /* - if scan mode is disabled:                                              */
-  /*    * Injected channels sequence length is set to 0x00: 1 channel         */
-  /*      converted (channel on injected rank 1)                              */
-  /*      Parameter "InjectedNbrOfConversion" is discarded.                   */
-  /*    * Injected context register JSQR setting is simple: register is fully */
-  /*      defined on one call of this function (for injected rank 1) and can  */
-  /*      be entered into queue directly.                                     */
-  /* - if scan mode is enabled:                                               */
-  /*    * Injected channels sequence length is set to parameter               */
-  /*      "InjectedNbrOfConversion".                                          */
-  /*    * Injected context register JSQR setting more complex: register is    */
-  /*      fully defined over successive calls of this function, for each      */
-  /*      injected channel rank. It is entered into queue only when all       */
-  /*      injected ranks have been set.                                       */
-  /*   Note: Scan mode is not present by hardware on this device, but used    */
-  /*   by software for alignment over all STM32 devices.                      */
-
-  if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)  ||
-      (sConfigInjected->InjectedNbrOfConversion == 1)  )
-  {
-    /* Configuration of context register JSQR:                                */
-    /*  - number of ranks in injected group sequencer: fixed to 1st rank      */
-    /*    (scan mode disabled, only rank 1 used)                              */
-    /*  - external trigger to start conversion                                */
-    /*  - external trigger polarity                                           */
-    /*  - channel set to rank 1 (scan mode disabled, only rank 1 can be used) */
-    
-    if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
-    {
-      /* Enable external trigger if trigger selection is different of         */
-      /* software start.                                                      */
-      /* Note: This configuration keeps the hardware feature of parameter     */
-      /*       ExternalTrigInjecConvEdge "trigger edge none" equivalent to    */
-      /*       software start.                                                */
-      if ((sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
-         && (sConfigInjected->ExternalTrigInjecConvEdge != ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
-      {
-        tmp_JSQR_ContextQueueBeingBuilt = ( ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) |
-                                             sConfigInjected->ExternalTrigInjecConv     |
-                                             sConfigInjected->ExternalTrigInjecConvEdge                                );                                              
-      }
-      else
-      {
-        tmp_JSQR_ContextQueueBeingBuilt = ( ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) );
-      }
-      
-
-      MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_JSQR_ContextQueueBeingBuilt); 
-      /* For debug and informative reasons, hadc handle saves JSQR setting */
-      hadc->InjectionConfig.ContextQueue = tmp_JSQR_ContextQueueBeingBuilt;
-    
-    }
-  }
-  else
-  {
-    /* Case of scan mode enabled, several channels to set into injected group */
-    /* sequencer.                                                             */
-    /*                                                                        */
-    /* Procedure to define injected context register JSQR over successive     */
-    /* calls of this function, for each injected channel rank:                */
-    /* 1. Start new context and set parameters related to all injected        */
-    /*    channels: injected sequence length and trigger.                     */
-    
-    /* if hadc->InjectionConfig.ChannelCount is equal to 0, this is the first */
-    /*   call of the context under setting                                    */
-    if (hadc->InjectionConfig.ChannelCount == 0) 
-    {
-      /* Initialize number of channels that will be configured on the context */
-      /*  being built                                                         */
-      hadc->InjectionConfig.ChannelCount = sConfigInjected->InjectedNbrOfConversion;
-      /* Handle hadc saves the context under build up over each HAL_ADCEx_InjectedConfigChannel()
-         call, this context will be written in JSQR register at the last call.
-         At this point, the context is merely reset  */
-       hadc->InjectionConfig.ContextQueue = (uint32_t)0x00000000;
-
-      /* Configuration of context register JSQR:                              */
-      /*  - number of ranks in injected group sequencer                       */
-      /*  - external trigger to start conversion                              */
-      /*  - external trigger polarity                                         */
-        
-      /* Enable external trigger if trigger selection is different of         */
-      /* software start.                                                      */
-      /* Note: This configuration keeps the hardware feature of parameter     */
-      /*       ExternalTrigInjecConvEdge "trigger edge none" equivalent to    */
-      /*       software start.                                                */
-      if ((sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
-         && (sConfigInjected->ExternalTrigInjecConvEdge != ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
-      {      
-        tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - (uint32_t)1)              |
-                                             sConfigInjected->ExternalTrigInjecConv |
-                                             sConfigInjected->ExternalTrigInjecConvEdge                            );        
-      }
-      else
-      {
-        tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - (uint32_t)1) );
-      }
-     
-      
-    } /* if (hadc->InjectionConfig.ChannelCount == 0) */  
-    
-
-    /* 2. Continue setting of context under definition with parameter       */
-    /*    related to each channel: channel rank sequence                    */ 
-    /* Clear the old JSQx bits for the selected rank */
-    tmp_JSQR_ContextQueueBeingBuilt &= ~ADC_JSQR_RK(ADC_SQR3_SQ10, sConfigInjected->InjectedRank);
-    
-    /* Set the JSQx bits for the selected rank */
-    tmp_JSQR_ContextQueueBeingBuilt |= ADC_JSQR_RK(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank);
-
-    /* Decrease channel count  */
-    hadc->InjectionConfig.ChannelCount--;
-    
-    
-    /* 3. tmp_JSQR_ContextQueueBeingBuilt is fully built for this HAL_ADCEx_InjectedConfigChannel()
-          call, aggregate the setting to those already built during the previous  
-          HAL_ADCEx_InjectedConfigChannel() calls (for the same context of course)  */
-    hadc->InjectionConfig.ContextQueue |= tmp_JSQR_ContextQueueBeingBuilt;
-          
-    /* 4. End of context setting: if this is the last channel set, then write context
-        into register JSQR and make it enter into queue                   */
-    if (hadc->InjectionConfig.ChannelCount == 0)
-    {
-      MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, hadc->InjectionConfig.ContextQueue); 
-    }
-
-    
-  } 
-
-  /* Parameters update conditioned to ADC state:                              */
-  /* Parameters that can be updated when ADC is disabled or enabled without   */
-  /* conversion on going on injected group:                                   */
-  /*  - Injected context queue: Queue disable (active context is kept) or     */
-  /*    enable (context decremented, up to 2 contexts queued)                 */
-  /*  - Injected discontinuous mode: can be enabled only if auto-injected     */
-  /*    mode is disabled.                                                     */
-  if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
-  {
-     
-    /* If auto-injected mode is disabled: no constraint                       */
-    if (sConfigInjected->AutoInjectedConv == DISABLE)
-    {                               
-      MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_JQM | ADC_CFGR_JDISCEN, 
-                               ADC_CFGR_INJECT_CONTEXT_QUEUE(sConfigInjected->QueueInjectedContext)          | 
-                               ADC_CFGR_INJECT_DISCCONTINUOUS(sConfigInjected->InjectedDiscontinuousConvMode) );                          
-    }
-    /* If auto-injected mode is enabled: Injected discontinuous setting is   */
-    /* discarded.                                                             */
-    else
-    {
-            MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_JQM | ADC_CFGR_JDISCEN, 
-                               ADC_CFGR_INJECT_CONTEXT_QUEUE(sConfigInjected->QueueInjectedContext) );  
-    }
-
-  }
-  
-  
-  /* Parameters update conditioned to ADC state:                              */
-  /* Parameters that can be updated when ADC is disabled or enabled without   */
-  /* conversion on going on regular and injected groups:                      */
-  /*  - Automatic injected conversion: can be enabled if injected group       */
-  /*    external triggers are disabled.                                       */
-  /*  - Channel sampling time                                                 */
-  /*  - Channel offset                                                        */
-  if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
-  {    
-    /* If injected group external triggers are disabled (set to injected      */
-    /* software start): no constraint                                         */
-    if ((sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
-       || (sConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
-    {
-         if (sConfigInjected->AutoInjectedConv == ENABLE)
-         {
-           SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);    
-         }
-         else
-         {
-           CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);    
-         }                                                                                  
-    }
-    /* If Automatic injected conversion was intended to be set and could not  */
-    /* due to injected group external triggers enabled, error is reported.    */
-    else
-    {
-      if (sConfigInjected->AutoInjectedConv == ENABLE)
-      {
-        /* Update ADC state machine to error */
-        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-        
-        tmp_status = HAL_ERROR;
-      }
-      else
-      {
-        CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO); 
-      }
-    }
-    
-    
-    
-    if (sConfigInjected->InjecOversamplingMode == ENABLE)
-    {
-      assert_param(IS_ADC_OVERSAMPLING_RATIO(sConfigInjected->InjecOversampling.Ratio));
-      assert_param(IS_ADC_RIGHT_BIT_SHIFT(sConfigInjected->InjecOversampling.RightBitShift));
-      
-      /*  JOVSE must be reset in case of triggered regular mode  */
-      assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE|ADC_CFGR2_TROVS) == (ADC_CFGR2_ROVSE|ADC_CFGR2_TROVS)));
-
-      /* Configuration of Injected Oversampler:                                 */
-      /*  - Oversampling Ratio                                                  */
-      /*  - Right bit shift                                                     */
-      
-      /* Enable OverSampling mode */
-  
-       MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_INJ_FIELDS, 
-                                 ADC_CFGR2_JOVSE                     | 
-                                 sConfigInjected->InjecOversampling.Ratio         |
-                                 sConfigInjected->InjecOversampling.RightBitShift );
-    }  
-    else
-    {
-      /* Disable Regular OverSampling */
-       CLEAR_BIT( hadc->Instance->CFGR2, ADC_CFGR2_JOVSE);
-    }    
-        
-  
-    /* Sampling time configuration of the selected channel */
-    /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
-    if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10)
-    {
-      /* Clear the old sample time and set the new one */
-      ADC_SMPR2_SETTING(hadc, sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);                
-    }
-    else /* if ADC_Channel_0 ... ADC_Channel_9 is selected */
-    {
-     /* Clear the old sample time and set the new one */
-      ADC_SMPR1_SETTING(hadc, sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);             
-    }
-    
-        
-    /* Configure the offset: offset enable/disable, channel, offset value */
-  
-    /* Shift the offset with respect to the selected ADC resolution. */
-    /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
-    tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset);
-    
-    switch (sConfigInjected->InjectedOffsetNumber)
-    {
-    case ADC_OFFSET_1:
-      /* Configure offset register 1:                                         */
-      /* - Enable offset                                                      */
-      /* - Set channel number                                                 */
-      /* - Set offset value                                                   */
-      MODIFY_REG(hadc->Instance->OFR1, 
-                ADC_OFR1_OFFSET1 | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1_EN, 
-                ADC_OFR1_OFFSET1_EN | ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted);                                    
-      break;
-    
-    case ADC_OFFSET_2:
-      /* Configure offset register 2:                                         */
-      /* - Enable offset                                                      */
-      /* - Set channel number                                                 */
-      /* - Set offset value                                                   */
-      MODIFY_REG(hadc->Instance->OFR2, 
-                ADC_OFR2_OFFSET2 | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2_EN, 
-                ADC_OFR2_OFFSET2_EN | ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted);                                     
-      break;
-        
-    case ADC_OFFSET_3:
-      /* Configure offset register 3:                                         */
-      /* - Enable offset                                                      */
-      /* - Set channel number                                                 */
-      /* - Set offset value                                                   */
-      MODIFY_REG(hadc->Instance->OFR3, 
-                ADC_OFR3_OFFSET3 | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3_EN, 
-                ADC_OFR3_OFFSET3_EN | ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted);                                   
-      break;
-    
-    case ADC_OFFSET_4:
-      /* Configure offset register 1:                                         */
-      /* - Enable offset                                                      */
-      /* - Set channel number                                                 */
-      /* - Set offset value                                                   */
-      MODIFY_REG(hadc->Instance->OFR4, 
-                ADC_OFR4_OFFSET4 | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4_EN, 
-                ADC_OFR4_OFFSET4_EN | ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted);                                  
-      break;
-    
-    /* Case ADC_OFFSET_NONE */
-    default :
-    /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is enabled. If this is the case, offset OFRx is disabled. */
-      if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
-      {
-        /* Disable offset OFR1*/
-        CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN);
-      }
-      if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
-      {
-        /* Disable offset OFR2*/
-        CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN); 
-      }
-      if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
-      {
-        /* Disable offset OFR3*/
-        CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN); 
-      }
-      if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
-      {
-        /* Disable offset OFR4*/
-        CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN); 
-      }
-      break;
-    }
-
-  } /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) */
-  
-  
-  /* Parameters update conditioned to ADC state:                              */
-  /* Parameters that can be updated only when ADC is disabled:                */
-  /*  - Single or differential mode                                           */
-  /*  - Internal measurement channels: Vbat/VrefInt/TempSensor                */
-  if (ADC_IS_ENABLE(hadc) == RESET)
-  {
-    /* Configuration of differential mode */
-    if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
-    {
-      /* Disable differential mode (default mode: single-ended) */
-      CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfigInjected->InjectedChannel));
-    }
-    else
-    {
-      /* Enable differential mode */
-      SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfigInjected->InjectedChannel));
-      
-      /* Sampling time configuration of channel ADC_IN+1 (negative input).
-         Starting from channel 9, SMPR2 register must be configured.      */
-      if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_9)
-      {
-        /* Clear the old sample time and set the new one */
-        ADC_SMPR2_SETTING(hadc, sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel+1);                     
-      }
-      else /* For channels 0 to 8 */
-      {
-         /* Clear the old sample time and set the new one */
-        ADC_SMPR1_SETTING(hadc, sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel+1);                 
-      }
-    }
-    
-
-    /* Management of internal measurement channels: Vbat/VrefInt/TempSensor   */
-    /* internal measurement paths enable: If internal channel selected,       */
-    /* enable dedicated internal buffers and path.                            */
-    /* Note: these internal measurement paths can be disabled using           */
-    /* HAL_ADC_DeInit().                                                      */
-
-    /* Configuration of common ADC parameters                                 */
-
-    tmpADC_Common = ADC_COMMON_REGISTER(hadc);
-  
-    /* If the requested internal measurement path has already been enabled,   */
-    /* bypass the configuration processing.                                   */
-    if (( (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) &&
-          (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN))            ) ||
-        ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)       &&
-          (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN))          ) ||
-        ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)    &&
-          (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN)))
-       )
-    {
-      /* Configuration of common ADC parameters (continuation)                */
-      /* Software is allowed to change common parameters only when all ADCs   */
-      /* of the common group are disabled.                                    */
-      if ((ADC_IS_ENABLE(hadc) == RESET)   &&
-         (ADC_ANY_OTHER_ENABLED(hadc) == RESET) )              
-      {
-        if (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR)
-        {
-          if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) 
-          {
-            SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN);
-          
-            /* Delay for temperature sensor stabilization time */
-            /* Compute number of CPU cycles to wait for */
-            wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
-            while(wait_loop_index != 0)
-            {
-              wait_loop_index--;
-            }
-          }
-        }
-        else if (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)
-        { 
-          if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
-          {
-            SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN);
-          }
-        }
-        else if (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)
-        { 
-          if (ADC_VREFINT_INSTANCE(hadc))
-          {
-            SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN);
-          }                       
-        }       
-      }
-      /* If the requested internal measurement path has already been enabled  */
-      /* and other ADC of the common group are enabled, internal              */
-      /* measurement paths cannot be enabled.                                 */
-      else  
-      {
-        /* Update ADC state machine to error */
-        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-        
-        tmp_status = HAL_ERROR;
-      }
-    }
-    
-  } /* if (ADC_IS_ENABLE(hadc) == RESET) */
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-
-  /* Return function status */
-  return tmp_status;
-}
-
-
-
-
-/**
-  * @brief  Enable ADC multimode and configure multimode parameters
-  * @note   Possibility to update parameters on the fly:
-  *         This function initializes multimode parameters, following  
-  *         calls to this function can be used to reconfigure some parameters 
-  *         of structure "ADC_MultiModeTypeDef" on the fly, without resetting 
-  *         the ADCs.
-  *         The setting of these parameters is conditioned to ADC state.
-  *         For parameters constraints, see comments of structure 
-  *         "ADC_MultiModeTypeDef".
-  * @note   To move back configuration from multimode to single mode, ADC must
-  *         be reset (using function HAL_ADC_Init() ).
-  * @param  hadc: Master ADC handle
-  * @param  multimode : Structure of ADC multimode configuration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)
-{
-  HAL_StatusTypeDef  tmp_status = HAL_OK;
-  ADC_Common_TypeDef *tmpADC_Common;
-  ADC_HandleTypeDef  tmphadcSlave;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
-  assert_param(IS_ADC_MULTIMODE(multimode->Mode));
-  assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(multimode->DMAAccessMode));
-  assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-
-  ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
-  
-  /* Parameters update conditioned to ADC state:                              */
-  /* Parameters that can be updated when ADC is disabled or enabled without   */
-  /* conversion on going on regular group:                                    */
-  /*  - Multimode DMA configuration                                           */
-  /*  - Multimode DMA mode                                                    */
-  if ( (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) 
-    && (ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave) == RESET) )
-  {
-    
-    /* Pointer to the common control register */
-    tmpADC_Common = ADC_COMMON_REGISTER(hadc);
-    
-    MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, 
-               multimode->DMAAccessMode |
-               ADC_CCR_MULTI_DMACONTREQ(hadc->Init.DMAContinuousRequests));
-               
-    /* Parameters that can be updated only when ADC is disabled:                */
-    /*  - Multimode mode selection                                              */
-    /*  - Multimode delay                                                       */
-    if ((ADC_IS_ENABLE(hadc) == RESET)                             &&
-        (ADC_IS_ENABLE(&tmphadcSlave) == RESET)  )
-    {
-      /* Configuration of ADC common group ADC1&ADC2                            */
-      /*  - set the selected multimode                                          */
-      /*  - Set delay between two sampling phases                               */
-      /*    Note: Delay range depends on selected resolution:                   */
-      /*      from 1 to 12 clock cycles for 12 bits                             */
-      /*      from 1 to 10 clock cycles for 10 bits,                            */
-      /*      from 1 to 8 clock cycles for 8 bits                               */
-      /*      from 1 to 6 clock cycles for 6 bits                               */
-      /*    If a higher delay is selected, it will be clipped to maximum delay  */
-      /*    range                                                               */
-  
-        MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY, 
-               multimode->Mode | multimode->TwoSamplingDelay );
-    }                              
-                            
-                            
-  }
-  /* If one of the ADC sharing the same common group is enabled, no update    */
-  /* could be done on neither of the multimode structure parameters.          */
-  else
-  {
-    /* Update ADC state machine to error */
-    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-    
-    tmp_status = HAL_ERROR;
-  }
-    
-    
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmp_status;
-} 
-
-
-/**
-  * @brief  Enable Injected Queue
-  * @note   This function resets CFGR register JQDIS bit in order to enable the
-  *         Injected Queue. JQDIS can be written only when ADSTART and JDSTART
-  *         are both equal to 0 to ensure that no regular nor injected 
-  *         conversion is ongoing. 
-  * @param  hadc: ADC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef* hadc)
-{
-
-  /* Parameter can be set only if no conversion is on-going                   */
-  if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
-  {
-    CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
-    
-    /* Update state, clear previous result related to injected queue overflow */
-    CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
-    
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-
-}
-
-/**
-  * @brief  Disable Injected Queue
-  * @note   This function sets CFGR register JQDIS bit in order to disable the
-  *         Injected Queue. JQDIS can be written only when ADSTART and JDSTART
-  *         are both equal to 0 to ensure that no regular nor injected 
-  *         conversion is ongoing. 
-  * @param  hadc: ADC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef* hadc)
-{
-
-  /* Parameter can be set only if no conversion is on-going                   */
-  if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
-  {
-    SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
-    return HAL_OK;    
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-
-}
-
-
-/**
-  * @brief  Disable ADC voltage regulator.
-  * @note   Disabling voltage regulator allows to save power. This operation can
-  *         be carried out only when ADC is disabled.
-  * @note   To enable again the voltage regulator, the user is expected to 
-  *         resort to HAL_ADC_Init() API.           
-  * @param  hadc: ADC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc)
-{
-
-  /* ADVREGEN can be written only when the ADC is disabled  */
-  if (ADC_IS_ENABLE(hadc) == RESET)
-  {
-    CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN);
-    return HAL_OK;    
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Enter ADC deep-power-down mode
-  * @note   This mode is achieved in setting DEEPPWD bit and allows to save power 
-  *         in reducing leakage currents. It is particularly interesting before 
-  *         entering stop modes.
-  * @note   Setting DEEPPWD automatically clears ADVREGEN bit and disables the
-  *         ADC voltage regulator. This means that this API encompasses
-  *         HAL_ADCEx_DisableVoltageRegulator(). Additionally, the internal
-  *         calibration is lost.    
-  * @note   To exit the ADC deep-power-down mode, the user is expected to 
-  *         resort to HAL_ADC_Init() API as well as to relaunch a calibration
-  *         with HAL_ADCEx_Calibration_Start() API or to re-apply a previously
-  *         saved calibration factor.
-  * @param  hadc: ADC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef* hadc)
-{
-
-  /* DEEPPWD can be written only when the ADC is disabled  */
-  if (ADC_IS_ENABLE(hadc) == RESET)
-  {
-    SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
-    return HAL_OK;    
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-
-  
-#endif /* HAL_ADC_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/src/stm32l4xx_hal_can.c b/stmhal/hal/l4/src/stm32l4xx_hal_can.c
deleted file mode 100644
index 455664ba3b..0000000000
--- a/stmhal/hal/l4/src/stm32l4xx_hal_can.c
+++ /dev/null
@@ -1,1404 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_can.c
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   CAN HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the Controller Area Network (CAN) peripheral:           
-  *           + Initialization and de-initialization functions 
-  *           + IO operation functions
-  *           + Peripheral Control functions
-  *           + Peripheral State and Error functions
-  *
-  @verbatim
-  ==============================================================================    
-                        ##### How to use this driver #####
-  ==============================================================================
-    [..]            
-      (#) Enable the CAN controller interface clock using 
-          __HAL_RCC_CAN1_CLK_ENABLE() for CAN1.
-       
-      (#) CAN pins configuration
-        (++) Enable the clock for the CAN GPIOs using the following function:
-             __HAL_RCC_GPIOx_CLK_ENABLE();   
-        (++) Connect and configure the involved CAN pins using the 
-              following function HAL_GPIO_Init(); 
-              
-      (#) Initialize and configure the CAN using HAL_CAN_Init() function.   
-                 
-      (#) Transmit the desired CAN frame using HAL_CAN_Transmit() or 
-          HAL_CAN_Transmit_IT() function.
-           
-      (#) Receive a CAN frame using HAL_CAN_Receive() or HAL_CAN_Receive_IT() function.
-
-     *** Polling mode IO operation ***
-     =================================
-     [..]    
-       (+) Start the CAN peripheral transmission and wait the end of this operation 
-           using HAL_CAN_Transmit(), at this stage user can specify the value of timeout
-           according to his end application
-       (+) Start the CAN peripheral reception and wait the end of this operation 
-           using HAL_CAN_Receive(), at this stage user can specify the value of timeout
-           according to his end application 
-       
-     *** Interrupt mode IO operation ***    
-     ===================================
-     [..]    
-       (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()
-       (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT()         
-       (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine
-       (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can 
-            add his own code by customization of function pointer HAL_CAN_TxCpltCallback 
-       (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can 
-            add his own code by customization of function pointer HAL_CAN_ErrorCallback
- 
-     *** CAN HAL driver macros list ***
-     ============================================= 
-     [..]
-       Below the list of most used macros in CAN HAL driver.
-       
-      (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts
-      (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts
-      (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled
-      (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags
-      (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status
-      
-     [..] 
-      (@) You can refer to the CAN HAL driver header file for more useful macros 
-                
-  @endverbatim
-           
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup CAN CAN
-  * @brief CAN driver modules
-  * @{
-  */ 
-  
-#ifdef HAL_CAN_MODULE_ENABLED  
-  
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup CAN_Private_Constants CAN Private Constants
-  * @{
-  */
-#define CAN_TIMEOUT_VALUE  10
-/**
-  * @}
-  */
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup CAN_Private_Functions CAN Private Functions
- * @{
- */
-static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);
-static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup CAN_Exported_Functions CAN Exported Functions
-  * @{
-  */
-
-/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions 
- *
-@verbatim    
-  ==============================================================================
-              ##### Initialization and de-initialization functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Initialize and configure the CAN. 
-      (+) De-initialize the CAN. 
-         
-@endverbatim
-  * @{
-  */
-  
-/**
-  * @brief  Initialize the CAN peripheral according to the specified parameters 
-  *         in the CAN_InitStruct structure and initialize the associated handle.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
-{
-  uint32_t status = CAN_INITSTATUS_FAILED;  /* Default init status */
-  uint32_t tickstart = 0;
-  
-  /* Check CAN handle */
-  if(hcan == NULL)
-  {
-     return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
-  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM));
-  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM));
-  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM));
-  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART));
-  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM));
-  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP));
-  assert_param(IS_CAN_MODE(hcan->Init.Mode));
-  assert_param(IS_CAN_SJW(hcan->Init.SJW));
-  assert_param(IS_CAN_BS1(hcan->Init.BS1));
-  assert_param(IS_CAN_BS2(hcan->Init.BS2));
-  assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
-  
-  if(hcan->State == HAL_CAN_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hcan->Lock = HAL_UNLOCKED;
-
-    /* Init the low level hardware */
-    HAL_CAN_MspInit(hcan);
-  }
-  
-  /* Initialize the CAN state*/
-  hcan->State = HAL_CAN_STATE_BUSY;
-  
-  /* Exit from sleep mode */
-  hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
-
-  /* Request initialisation */
-  hcan->Instance->MCR |= CAN_MCR_INRQ ;
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  /* Wait the acknowledge */
-  while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
-  {
-    if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
-    {
-      hcan->State= HAL_CAN_STATE_TIMEOUT;
-      /* Process unlocked */
-      __HAL_UNLOCK(hcan);
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Check acknowledge */
-  if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
-  {
-    /* Set the time triggered communication mode */
-    if (hcan->Init.TTCM == ENABLE)
-    {
-      hcan->Instance->MCR |= CAN_MCR_TTCM;
-    }
-    else
-    {
-      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM;
-    }
-
-    /* Set the automatic bus-off management */
-    if (hcan->Init.ABOM == ENABLE)
-    {
-      hcan->Instance->MCR |= CAN_MCR_ABOM;
-    }
-    else
-    {
-      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM;
-    }
-
-    /* Set the automatic wake-up mode */
-    if (hcan->Init.AWUM == ENABLE)
-    {
-      hcan->Instance->MCR |= CAN_MCR_AWUM;
-    }
-    else
-    {
-      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM;
-    }
-
-    /* Set the no automatic retransmission */
-    if (hcan->Init.NART == ENABLE)
-    {
-      hcan->Instance->MCR |= CAN_MCR_NART;
-    }
-    else
-    {
-      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART;
-    }
-
-    /* Set the receive FIFO locked mode */
-    if (hcan->Init.RFLM == ENABLE)
-    {
-      hcan->Instance->MCR |= CAN_MCR_RFLM;
-    }
-    else
-    {
-      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM;
-    }
-
-    /* Set the transmit FIFO priority */
-    if (hcan->Init.TXFP == ENABLE)
-    {
-      hcan->Instance->MCR |= CAN_MCR_TXFP;
-    }
-    else
-    {
-      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP;
-    }
-
-    /* Set the bit timing register */
-    hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \
-                ((uint32_t)hcan->Init.SJW) | \
-                ((uint32_t)hcan->Init.BS1) | \
-                ((uint32_t)hcan->Init.BS2) | \
-               ((uint32_t)hcan->Init.Prescaler - 1);
-
-    /* Request leave initialisation */
-    hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ;
-
-    /* Get tick */
-    tickstart = HAL_GetTick();
-   
-    /* Wait the acknowledge */
-    while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
-    {
-      if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
-      {
-         hcan->State= HAL_CAN_STATE_TIMEOUT;
-         /* Process unlocked */
-         __HAL_UNLOCK(hcan);
-         return HAL_TIMEOUT;
-      }
-    }
-
-    /* Check acknowledged */
-    if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
-    {
-      status = CAN_INITSTATUS_SUCCESS;
-    }
-  }
- 
-  if(status == CAN_INITSTATUS_SUCCESS)
-  {
-    /* Set CAN error code to none */
-    hcan->ErrorCode = HAL_CAN_ERROR_NONE;
-    
-    /* Initialize the CAN state */
-    hcan->State = HAL_CAN_STATE_READY;
-  
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Initialize the CAN state */
-    hcan->State = HAL_CAN_STATE_ERROR;
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Configure the CAN reception filter according to the specified
-  *         parameters in the CAN_FilterInitStruct.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @param  sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that
-  *         contains the filter configuration information.
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)
-{
-  uint32_t filternbrbitpos = 0;
-  
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcan);
-
-  /* Check the parameters */
-  assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
-  assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
-  assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
-  assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
-  assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
-  assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber));
-
-  filternbrbitpos = ((uint32_t)1) << sFilterConfig->FilterNumber;
-
-  /* Initialisation mode for the filter */
-  CAN1->FMR |= (uint32_t)CAN_FMR_FINIT;
-  
-  /* Filter Deactivation */
-  CAN1->FA1R &= ~(uint32_t)filternbrbitpos;
-
-  /* Filter Scale */
-  if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
-  {
-    /* 16-bit scale for the filter */
-    CAN1->FS1R &= ~(uint32_t)filternbrbitpos;
-
-    /* First 16-bit identifier and First 16-bit mask */
-    /* Or First 16-bit identifier and Second 16-bit identifier */
-    CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 = 
-       ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16) |
-        (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
-
-    /* Second 16-bit identifier and Second 16-bit mask */
-    /* Or Third 16-bit identifier and Fourth 16-bit identifier */
-    CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 = 
-       ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |
-        (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh);
-  }
-
-  if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
-  {
-    /* 32-bit scale for the filter */
-    CAN1->FS1R |= filternbrbitpos;
-    /* 32-bit identifier or First 32-bit identifier */
-    CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 = 
-       ((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16) |
-        (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
-    /* 32-bit mask or Second 32-bit identifier */
-    CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 = 
-       ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |
-        (0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow);
-  }
-
-  /* Filter Mode */
-  if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
-  {
-    /*Id/Mask mode for the filter*/
-    CAN1->FM1R &= ~(uint32_t)filternbrbitpos;
-  }
-  else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
-  {
-    /*Identifier list mode for the filter*/
-    CAN1->FM1R |= (uint32_t)filternbrbitpos;
-  }
-
-  /* Filter FIFO assignment */
-  if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
-  {
-    /* FIFO 0 assignation for the filter */
-    CAN1->FFA1R &= ~(uint32_t)filternbrbitpos;
-  }
-
-  if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1)
-  {
-    /* FIFO 1 assignation for the filter */
-    CAN1->FFA1R |= (uint32_t)filternbrbitpos;
-  }
-  
-  /* Filter activation */
-  if (sFilterConfig->FilterActivation == ENABLE)
-  {
-    CAN1->FA1R |= filternbrbitpos;
-  }
-
-  /* Leave the initialisation mode for the filter */
-  CAN1->FMR &= ~((uint32_t)CAN_FMR_FINIT);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitialize the CAN peripheral registers to their default reset values. 
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)
-{
-  /* Check CAN handle */
-  if(hcan == NULL)
-  {
-     return HAL_ERROR;
-  }
-  
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
-  
-  /* Change CAN state */
-  hcan->State = HAL_CAN_STATE_BUSY;
-  
-  /* DeInit the low level hardware */
-  HAL_CAN_MspDeInit(hcan);
-  
-  /* Change CAN state */
-  hcan->State = HAL_CAN_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hcan);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initialize the CAN MSP.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.  
-  * @retval None
-  */
-__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcan);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_CAN_MspInit could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  DeInitialize the CAN MSP.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.  
-  * @retval None
-  */
-__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcan);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_CAN_MspDeInit could be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_Exported_Functions_Group2 Input and Output operation functions
- *  @brief    I/O operation functions 
- *
-@verbatim   
-  ==============================================================================
-                      ##### IO operation functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Transmit a CAN frame message.
-      (+) Receive a CAN frame message.
-      (+) Enter CAN peripheral in sleep mode. 
-      (+) Wake up the CAN peripheral from sleep mode.
-               
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initiate and transmit a CAN frame message.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.  
-  * @param  Timeout: Timeout duration.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
-{
-  uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
-  uint32_t tickstart = 0;
-
-  /* Check the parameters */
-  assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
-  assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
-  assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
-  
-  /* Process locked */
-  __HAL_LOCK(hcan);
-  
-  if(hcan->State == HAL_CAN_STATE_BUSY_RX) 
-  {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
-  }
-  else
-  {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_BUSY_TX;
-  }
-  
-  /* Select one empty transmit mailbox */
-  if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
-  {
-    transmitmailbox = 0;
-  }
-  else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
-  {
-    transmitmailbox = 1;
-  }
-  else if ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
-  {
-    transmitmailbox = 2;
-  }
-
-  if (transmitmailbox != CAN_TXSTATUS_NOMAILBOX)
-  {
-    /* Set up the Id */
-    hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
-    if (hcan->pTxMsg->IDE == CAN_ID_STD)
-    {
-      assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));  
-      hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \
-                                                  hcan->pTxMsg->RTR);
-    }
-    else
-    {
-      assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
-      hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \
-                                                  hcan->pTxMsg->IDE | \
-                                                  hcan->pTxMsg->RTR);
-    }
-    
-    /* Set up the DLC */
-    hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
-    hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0;
-    hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
-
-    /* Set up the data field */
-    hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) | 
-                                             ((uint32_t)hcan->pTxMsg->Data[2] << 16) |
-                                             ((uint32_t)hcan->pTxMsg->Data[1] << 8) | 
-                                             ((uint32_t)hcan->pTxMsg->Data[0]));
-    hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) | 
-                                             ((uint32_t)hcan->pTxMsg->Data[6] << 16) |
-                                             ((uint32_t)hcan->pTxMsg->Data[5] << 8) |
-                                             ((uint32_t)hcan->pTxMsg->Data[4]));
-    /* Request transmission */
-    hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
-  
-    /* Get tick */
-    tickstart = HAL_GetTick();
-  
-    /* Check End of transmission flag */
-    while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))
-    {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
-        {
-          hcan->State = HAL_CAN_STATE_TIMEOUT;
-          /* Process unlocked */
-          __HAL_UNLOCK(hcan);
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-    if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) 
-    {
-      /* Change CAN state */
-      hcan->State = HAL_CAN_STATE_BUSY_RX;
-    }
-    else
-    {
-      /* Change CAN state */
-      hcan->State = HAL_CAN_STATE_READY;
-    }
-    
-    /* Process unlocked */
-    __HAL_UNLOCK(hcan);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_ERROR; 
-    
-    /* Process unlocked */
-    __HAL_UNLOCK(hcan);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Initiate and transmit a CAN frame message in Interrupt mode.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
-{
-  uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
-
-  /* Check the parameters */
-  assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
-  assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
-  assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
-  
-  if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_RX))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcan);
-    
-    /* Select one empty transmit mailbox */
-    if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
-    {
-      transmitmailbox = 0;
-    }
-    else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
-    {
-      transmitmailbox = 1;
-    }
-    else if((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
-    {
-      transmitmailbox = 2;
-    }
-
-    if(transmitmailbox != CAN_TXSTATUS_NOMAILBOX)
-    {
-      /* Set up the Id */
-      hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
-      if(hcan->pTxMsg->IDE == CAN_ID_STD)
-      {
-        assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));  
-        hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \
-                                                  hcan->pTxMsg->RTR);
-      }
-      else
-      {
-        assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
-        hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \
-                                                  hcan->pTxMsg->IDE | \
-                                                  hcan->pTxMsg->RTR);
-      }
-    
-      /* Set up the DLC */
-      hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
-      hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0;
-      hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
-
-      /* Set up the data field */
-      hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) | 
-                                             ((uint32_t)hcan->pTxMsg->Data[2] << 16) |
-                                             ((uint32_t)hcan->pTxMsg->Data[1] << 8) | 
-                                             ((uint32_t)hcan->pTxMsg->Data[0]));
-      hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) | 
-                                             ((uint32_t)hcan->pTxMsg->Data[6] << 16) |
-                                             ((uint32_t)hcan->pTxMsg->Data[5] << 8) |
-                                             ((uint32_t)hcan->pTxMsg->Data[4]));
-    
-      if(hcan->State == HAL_CAN_STATE_BUSY_RX) 
-      {
-        /* Change CAN state */
-        hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
-      }
-      else
-      {
-        /* Change CAN state */
-        hcan->State = HAL_CAN_STATE_BUSY_TX;
-      }
-      
-      /* Set CAN error code to none */
-      hcan->ErrorCode = HAL_CAN_ERROR_NONE;
-      
-      /* Process Unlocked */
-      __HAL_UNLOCK(hcan);
-      
-      /* Enable interrupts: */
-      /*  - Enable Error warning Interrupt */
-      /*  - Enable Error passive Interrupt */
-      /*  - Enable Bus-off Interrupt */
-      /*  - Enable Last error code Interrupt */
-      /*  - Enable Error Interrupt */
-      /*  - Enable Transmit mailbox empty Interrupt */
-      __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
-                                CAN_IT_EPV |
-                                CAN_IT_BOF |
-                                CAN_IT_LEC |
-                                CAN_IT_ERR |
-                                CAN_IT_TME  );
-      
-      /* Request transmission */
-      hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
-    }
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Receive a correct CAN frame.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.  
-  * @param  FIFONumber:    FIFO number.
-  * @param  Timeout:       Timeout duration.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
-{
-  uint32_t tickstart = 0;
-   
-  /* Check the parameters */
-  assert_param(IS_CAN_FIFO(FIFONumber));
-  
-  /* Process locked */
-  __HAL_LOCK(hcan);
-  
-  if(hcan->State == HAL_CAN_STATE_BUSY_TX) 
-  {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
-  }
-  else
-  {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_BUSY_RX;
-  }
-    
-  /* Get tick */
-  tickstart = HAL_GetTick();
-  
-  /* Check pending message */
-  while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0)
-  {
-    /* Check for the Timeout */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
-      {
-        hcan->State = HAL_CAN_STATE_TIMEOUT;
-        /* Process unlocked */
-        __HAL_UNLOCK(hcan);
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  
-  /* Get the Id */
-  hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
-  if (hcan->pRxMsg->IDE == CAN_ID_STD)
-  {
-    hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21);
-  }
-  else
-  {
-    hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3);
-  }
-  
-  hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
-  /* Get the DLC */
-  hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
-  /* Get the FMI */
-  hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8);
-  /* Get the data field */
-  hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
-  hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8);
-  hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16);
-  hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24);
-  hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
-  hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8);
-  hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16);
-  hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24);
-  
-  /* Release the FIFO */
-  if(FIFONumber == CAN_FIFO0)
-  {
-    /* Release FIFO0 */
-    __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
-  }
-  else /* FIFONumber == CAN_FIFO1 */
-  {
-    /* Release FIFO1 */
-    __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
-  }
-  
-  if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) 
-  {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_BUSY_TX;
-  }
-  else
-  {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_READY;
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hcan);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Receive a correct CAN frame in Interrupt mode.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.  
-  * @param  FIFONumber:    FIFO number.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
-{
-  /* Check the parameters */
-  assert_param(IS_CAN_FIFO(FIFONumber));
-  
-  if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_TX))
-  {
-    /* Process locked */
-    __HAL_LOCK(hcan);
-  
-    if(hcan->State == HAL_CAN_STATE_BUSY_TX) 
-    {
-      /* Change CAN state */
-      hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      /* Change CAN state */
-      hcan->State = HAL_CAN_STATE_BUSY_RX;
-    }
-    
-    /* Set CAN error code to none */
-    hcan->ErrorCode = HAL_CAN_ERROR_NONE;
-    
-    /* Enable interrupts: */
-    /*  - Enable Error warning Interrupt */
-    /*  - Enable Error passive Interrupt */
-    /*  - Enable Bus-off Interrupt */
-    /*  - Enable Last error code Interrupt */
-    /*  - Enable Error Interrupt */
-    __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
-                              CAN_IT_EPV |
-                              CAN_IT_BOF |
-                              CAN_IT_LEC |
-                              CAN_IT_ERR );
-
-    /* Process unlocked */
-    __HAL_UNLOCK(hcan);
-
-    if(FIFONumber == CAN_FIFO0)
-    {
-      /* Enable FIFO 0 message pending Interrupt */
-      __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP0);
-    }
-    else
-    {
-      /* Enable FIFO 1 message pending Interrupt */
-      __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP1);
-    }
-    
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enter the Sleep (low power) mode.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
-{
-  uint32_t tickstart = 0;
-   
-  /* Process locked */
-  __HAL_LOCK(hcan);
-  
-  /* Change CAN state */
-  hcan->State = HAL_CAN_STATE_BUSY; 
-    
-  /* Request Sleep mode */
-   hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
-   
-  /* Sleep mode status */
-  if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
-  {
-    /* Process unlocked */
-    __HAL_UNLOCK(hcan);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  /* Get tick */
-  tickstart = HAL_GetTick();
-  
-  /* Wait the acknowledge */
-  while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
-  {
-    if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
-    {
-      hcan->State = HAL_CAN_STATE_TIMEOUT;
-      /* Process unlocked */
-      __HAL_UNLOCK(hcan);
-      return HAL_TIMEOUT;
-    }
-  }
-  
-  /* Change CAN state */
-  hcan->State = HAL_CAN_STATE_READY;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hcan);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Wake up the CAN peripheral from sleep mode (after that the CAN peripheral
-  *         is in the normal mode).
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
-{
-  uint32_t tickstart = 0;
-    
-  /* Process locked */
-  __HAL_LOCK(hcan);
-  
-  /* Change CAN state */
-  hcan->State = HAL_CAN_STATE_BUSY;  
- 
-  /* Wake up request */
-  hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  /* Sleep mode status */
-  while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
-  {
-    if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
-    {
-      hcan->State= HAL_CAN_STATE_TIMEOUT;
-      /* Process unlocked */
-      __HAL_UNLOCK(hcan);
-      return HAL_TIMEOUT;
-    }
-  }
-  if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
-  {
-    /* Process unlocked */
-    __HAL_UNLOCK(hcan);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  /* Change CAN state */
-  hcan->State = HAL_CAN_STATE_READY; 
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hcan);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle CAN interrupt request.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval None
-  */
-void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
-{
-  /* Check End of transmission flag */
-  if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))
-  {
-    if((__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0)) ||
-       (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1)) ||
-       (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2)))
-    {
-      /* Call transmit function */
-      CAN_Transmit_IT(hcan);
-    }
-  }
-  
-  /* Check End of reception flag for FIFO0 */
-  if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0)) &&
-     (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0) != 0))
-  {
-    /* Call receive function */
-    CAN_Receive_IT(hcan, CAN_FIFO0);
-  }
-  
-  /* Check End of reception flag for FIFO1 */
-  if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1)) &&
-     (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1) != 0))
-  {
-    /* Call receive function */
-    CAN_Receive_IT(hcan, CAN_FIFO1);
-  }
-  
-  /* Check Error Warning Flag */
-  if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG))    &&
-     (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG)) &&
-     (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
-  {
-    /* Set CAN error code to EWG error */
-    hcan->ErrorCode |= HAL_CAN_ERROR_EWG;
-    /* No need for clear of Error Warning Flag as read-only */
-  }
-  
-  /* Check Error Passive Flag */
-  if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV))    &&
-     (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV)) &&
-     (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
-  {
-    /* Set CAN error code to EPV error */
-    hcan->ErrorCode |= HAL_CAN_ERROR_EPV;
-    /* No need for clear of Error Passive Flag as read-only */ 
-  }
-  
-  /* Check Bus-Off Flag */
-  if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF))    &&
-     (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF)) &&
-     (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
-  {
-    /* Set CAN error code to BOF error */
-    hcan->ErrorCode |= HAL_CAN_ERROR_BOF;
-    /* No need for clear of Bus-Off Flag as read-only */
-  }
-  
-  /* Check Last error code Flag */
-  if((!HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC)) &&
-     (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC))         &&
-     (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
-  {
-    switch(hcan->Instance->ESR & CAN_ESR_LEC)
-    {
-      case(CAN_ESR_LEC_0):
-          /* Set CAN error code to STF error */
-          hcan->ErrorCode |= HAL_CAN_ERROR_STF;
-          break;
-      case(CAN_ESR_LEC_1):
-          /* Set CAN error code to FOR error */
-          hcan->ErrorCode |= HAL_CAN_ERROR_FOR;
-          break;
-      case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
-          /* Set CAN error code to ACK error */
-          hcan->ErrorCode |= HAL_CAN_ERROR_ACK;
-          break;
-      case(CAN_ESR_LEC_2):
-          /* Set CAN error code to BR error */
-          hcan->ErrorCode |= HAL_CAN_ERROR_BR;
-          break;
-      case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
-          /* Set CAN error code to BD error */
-          hcan->ErrorCode |= HAL_CAN_ERROR_BD;
-          break;
-      case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
-          /* Set CAN error code to CRC error */
-          hcan->ErrorCode |= HAL_CAN_ERROR_CRC;
-          break;
-      default:
-          break;
-    }
-
-    /* Clear Last error code Flag */ 
-    hcan->Instance->ESR &= ~(CAN_ESR_LEC);
-  }
-
-  /* Call the Error call Back in case of Errors */
-  if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)
-  {
-    /* Clear ERRI bit */
-    SET_BIT(hcan->Instance->MSR, CAN_MSR_ERRI);
-    /* Set the CAN state ready to be able to start again the process */
-    hcan->State = HAL_CAN_STATE_READY;
-    /* Call Error callback function */
-    HAL_CAN_ErrorCallback(hcan);
-  }  
-}
-
-/**
-  * @brief  Transmission complete callback in non-blocking mode.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval None
-  */
-__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcan);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_CAN_TxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Reception complete callback in non-blocking mode.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval None
-  */
-__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcan);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_CAN_RxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Error CAN callback.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval None
-  */
-__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcan);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_CAN_ErrorCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
- *  @brief   CAN Peripheral State functions 
- *
-@verbatim   
-  ==============================================================================
-            ##### Peripheral State and Error functions #####
-  ==============================================================================
-    [..]
-    This subsection provides functions allowing to :
-      (+) Check the CAN state.
-      (+) Check CAN Errors detected during interrupt process.
-         
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the CAN handle state.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval HAL state
-  */
-HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan)
-{
-  /* Return CAN handle state */
-  return hcan->State;
-}
-
-/**
-  * @brief  Return the CAN error code.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval CAN Error Code
-  */
-uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
-{
-  return hcan->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_Private_Functions CAN Private Functions
- * @{
- */
-/**
-  * @brief  Initiate and transmit a CAN frame message.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.  
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
-{
-  /* Disable Transmit mailbox empty Interrupt */
-  __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME);
-  
-  if(hcan->State == HAL_CAN_STATE_BUSY_TX)
-  {   
-    /* Disable interrupts: */
-    /*  - Disable Error warning Interrupt */
-    /*  - Disable Error passive Interrupt */
-    /*  - Disable Bus-off Interrupt */
-    /*  - Disable Last error code Interrupt */
-    /*  - Disable Error Interrupt */
-    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
-                               CAN_IT_EPV |
-                               CAN_IT_BOF |
-                               CAN_IT_LEC |
-                               CAN_IT_ERR  );
-  }
-  
-  if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) 
-  {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_BUSY_RX;
-  }
-  else
-  {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_READY;
-  }
-  
-  /* Transmission complete callback */ 
-  HAL_CAN_TxCpltCallback(hcan);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Receive a correct CAN frame.
-  * @param  hcan:       Pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.  
-  * @param  FIFONumber: Specify the FIFO number    
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
-{
-  /* Get the Id */
-  hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
-  if (hcan->pRxMsg->IDE == CAN_ID_STD)
-  {
-    hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21);
-  }
-  else
-  {
-    hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3);
-  }
-  
-  hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
-  /* Get the DLC */
-  hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
-  /* Get the FMI */
-  hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8);
-  /* Get the data field */
-  hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
-  hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8);
-  hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16);
-  hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24);
-  hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
-  hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8);
-  hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16);
-  hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24);
-  /* Release the FIFO */
-  /* Release FIFO0 */
-  if (FIFONumber == CAN_FIFO0)
-  {
-    __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
-    
-    /* Disable FIFO 0 message pending Interrupt */
-    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP0);
-  }
-  /* Release FIFO1 */
-  else /* FIFONumber == CAN_FIFO1 */
-  {
-    __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
-    
-    /* Disable FIFO 1 message pending Interrupt */
-    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP1);
-  }
-  
-  if(hcan->State == HAL_CAN_STATE_BUSY_RX)
-  {
-    /* Disable interrupts: */
-    /*  - Disable Error warning Interrupt */
-    /*  - Disable Error passive Interrupt */
-    /*  - Disable Bus-off Interrupt */
-    /*  - Disable Last error code Interrupt */
-    /*  - Disable Error Interrupt */
-    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
-                               CAN_IT_EPV |
-                               CAN_IT_BOF |
-                               CAN_IT_LEC |
-                               CAN_IT_ERR  );
-  }
-  
-  if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) 
-  {
-    /* Disable CAN state */
-    hcan->State = HAL_CAN_STATE_BUSY_TX;
-  }
-  else
-  {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_READY;
-  }
-
-  /* Receive complete callback */ 
-  HAL_CAN_RxCpltCallback(hcan);
-
-  /* Return function status */
-  return HAL_OK;
-}
-/**
- * @}
- */
-
-#endif /* HAL_CAN_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/src/stm32l4xx_hal_cortex.c b/stmhal/hal/l4/src/stm32l4xx_hal_cortex.c
deleted file mode 100644
index 7ff673dc52..0000000000
--- a/stmhal/hal/l4/src/stm32l4xx_hal_cortex.c
+++ /dev/null
@@ -1,492 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_cortex.c
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   CORTEX HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the CORTEX:
-  *           + Initialization and Configuration functions
-  *           + Peripheral Control functions
-  *
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-
-    [..]
-    *** How to configure Interrupts using CORTEX HAL driver ***
-    ===========================================================
-    [..]
-    This section provides functions allowing to configure the NVIC interrupts (IRQ).
-    The Cortex-M4 exceptions are managed by CMSIS functions.
-
-    (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function.
-    (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
-    (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
-
-     -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
-         The pending IRQ priority will be managed only by the sub priority.
-
-     -@- IRQ priority order (sorted by highest to lowest priority):
-        (+@) Lowest pre-emption priority
-        (+@) Lowest sub priority
-        (+@) Lowest hardware priority (IRQ number)
-
-    [..]
-    *** How to configure SysTick using CORTEX HAL driver ***
-    ========================================================
-    [..]
-    Setup SysTick Timer for time base.
-
-   (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
-       is a CMSIS function that:
-        (++) Configures the SysTick Reload register with value passed as function parameter.
-        (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
-        (++) Resets the SysTick Counter register.
-        (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
-        (++) Enables the SysTick Interrupt.
-        (++) Starts the SysTick Counter.
-
-   (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
-       __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
-       HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
-       inside the stm32l4xx_hal_cortex.h file.
-
-   (+) You can change the SysTick IRQ priority by calling the
-       HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
-       call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
-
-   (+) To adjust the SysTick time base, use the following formula:
-
-       Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
-       (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
-       (++) Reload Value should not exceed 0xFFFFFF
-
-  @endverbatim
-  ******************************************************************************
-
-  The table below gives the allowed values of the pre-emption priority and subpriority according
-  to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
-  
-    ==========================================================================================================================
-      NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  |       Description
-    ==========================================================================================================================
-     NVIC_PRIORITYGROUP_0  |                0                  |            0-15             | 0 bit for pre-emption priority
-                           |                                   |                             | 4 bits for subpriority
-    --------------------------------------------------------------------------------------------------------------------------
-     NVIC_PRIORITYGROUP_1  |                0-1                |            0-7              | 1 bit for pre-emption priority
-                           |                                   |                             | 3 bits for subpriority
-    --------------------------------------------------------------------------------------------------------------------------    
-     NVIC_PRIORITYGROUP_2  |                0-3                |            0-3              | 2 bits for pre-emption priority
-                           |                                   |                             | 2 bits for subpriority
-    --------------------------------------------------------------------------------------------------------------------------    
-     NVIC_PRIORITYGROUP_3  |                0-7                |            0-1              | 3 bits for pre-emption priority
-                           |                                   |                             | 1 bit for subpriority
-    --------------------------------------------------------------------------------------------------------------------------    
-     NVIC_PRIORITYGROUP_4  |                0-15               |            0                | 4 bits for pre-emption priority
-                           |                                   |                             | 0 bit for subpriority                       
-    ==========================================================================================================================
-
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup CORTEX
-  * @{
-  */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup CORTEX_Exported_Functions
-  * @{
-  */
-
-
-/** @addtogroup CORTEX_Exported_Functions_Group1
- *  @brief    Initialization and Configuration functions
- *
-@verbatim
-  ==============================================================================
-              ##### Initialization and Configuration functions #####
-  ==============================================================================
-    [..]
-      This section provides the CORTEX HAL driver functions allowing to configure Interrupts
-      SysTick functionalities
-
-@endverbatim
-  * @{
-  */
-
-
-/**
-  * @brief  Set the priority grouping field (pre-emption priority and subpriority)
-  *         using the required unlock sequence.
-  * @param  PriorityGroup: The priority grouping bits length.
-  *         This parameter can be one of the following values:
-  *         @arg NVIC_PRIORITYGROUP_0: 0 bit  for pre-emption priority,
-  *                                    4 bits for subpriority
-  *         @arg NVIC_PRIORITYGROUP_1: 1 bit  for pre-emption priority,
-  *                                    3 bits for subpriority
-  *         @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
-  *                                    2 bits for subpriority
-  *         @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
-  *                                    1 bit  for subpriority
-  *         @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
-  *                                    0 bit  for subpriority
-  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
-  *         The pending IRQ priority will be managed only by the subpriority.
-  * @retval None
-  */
-void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
-
-  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
-  NVIC_SetPriorityGrouping(PriorityGroup);
-}
-
-/**
-  * @brief  Set the priority of an interrupt.
-  * @param  IRQn: External interrupt number.
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
-  * @param  PreemptPriority: The pre-emption priority for the IRQn channel.
-  *         This parameter can be a value between 0 and 15
-  *         A lower priority value indicates a higher priority
-  * @param  SubPriority: the subpriority level for the IRQ channel.
-  *         This parameter can be a value between 0 and 15
-  *         A lower priority value indicates a higher priority.
-  * @retval None
-  */
-void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t prioritygroup = 0x00;
-
-  /* Check the parameters */
-  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
-  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
-
-  prioritygroup = NVIC_GetPriorityGrouping();
-
-  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
-}
-
-/**
-  * @brief  Enable a device specific interrupt in the NVIC interrupt controller.
-  * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
-  *         function should be called before.
-  * @param  IRQn External interrupt number.
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
-  * @retval None
-  */
-void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-  
-  /* Enable interrupt */
-  NVIC_EnableIRQ(IRQn);
-}
-
-/**
-  * @brief  Disable a device specific interrupt in the NVIC interrupt controller.
-  * @param  IRQn External interrupt number.
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
-  * @retval None
-  */
-void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-  
-  /* Disable interrupt */
-  NVIC_DisableIRQ(IRQn);
-}
-
-/**
-  * @brief  Initiate a system reset request to reset the MCU.
-  * @retval None
-  */
-void HAL_NVIC_SystemReset(void)
-{
-  /* System Reset */
-  NVIC_SystemReset();
-}
-
-/**
-  * @brief  Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick): 
-  *         Counter is in free running mode to generate periodic interrupts.
-  * @param  TicksNumb: Specifies the ticks Number of ticks between two interrupts.
-  * @retval status:  - 0  Function succeeded.
-  *                  - 1  Function failed.
-  */
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
-{
-   return SysTick_Config(TicksNumb);
-}
-/**
-  * @}
-  */
-
-/** @addtogroup CORTEX_Exported_Functions_Group2
- *  @brief   Cortex control functions
- *
-@verbatim
-  ==============================================================================
-                      ##### Peripheral Control functions #####
-  ==============================================================================
-    [..]
-      This subsection provides a set of functions allowing to control the CORTEX
-      (NVIC, SYSTICK, MPU) functionalities.
-
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Get the priority grouping field from the NVIC Interrupt Controller.
-  * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
-  */
-uint32_t HAL_NVIC_GetPriorityGrouping(void)
-{
-  /* Get the PRIGROUP[10:8] field value */
-  return NVIC_GetPriorityGrouping();
-}
-
-/**
-  * @brief  Get the priority of an interrupt.
-  * @param  IRQn: External interrupt number.
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
-  * @param   PriorityGroup: the priority grouping bits length.
-  *         This parameter can be one of the following values:
-  *           @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
-  *                                      4 bits for subpriority
-  *           @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
-  *                                      3 bits for subpriority
-  *           @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
-  *                                      2 bits for subpriority
-  *           @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
-  *                                      1 bit for subpriority
-  *           @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
-  *                                      0 bit for subpriority
-  * @param  pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
-  * @param  pSubPriority: Pointer on the Subpriority value (starting from 0).
-  * @retval None
-  */
-void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
- /* Get priority for Cortex-M system or device specific interrupts */
-  NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
-}
-
-/**
-  * @brief  Set Pending bit of an external interrupt.
-  * @param  IRQn External interrupt number
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
-  * @retval None
-  */
-void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  /* Set interrupt pending */
-  NVIC_SetPendingIRQ(IRQn);
-}
-
-/**
-  * @brief  Get Pending Interrupt (read the pending register in the NVIC
-  *         and return the pending bit for the specified interrupt).
-  * @param  IRQn External interrupt number.
-  *          This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
-  * @retval status: - 0  Interrupt status is not pending.
-  *                 - 1  Interrupt status is pending.
-  */
-uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  /* Return 1 if pending else 0 */
-  return NVIC_GetPendingIRQ(IRQn);
-}
-
-/**
-  * @brief  Clear the pending bit of an external interrupt.
-  * @param  IRQn External interrupt number.
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
-  * @retval None
-  */
-void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  /* Clear pending interrupt */
-  NVIC_ClearPendingIRQ(IRQn);
-}
-
-/**
-  * @brief Get active interrupt (read the active register in NVIC and return the active bit).
-  * @param IRQn External interrupt number
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
-  * @retval status: - 0  Interrupt status is not pending.
-  *                 - 1  Interrupt status is pending.
-  */
-uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
-{
-  /* Return 1 if active else 0 */
-  return NVIC_GetActive(IRQn);
-}
-
-/**
-  * @brief  Configure the SysTick clock source.
-  * @param  CLKSource: specifies the SysTick clock source.
-  *          This parameter can be one of the following values:
-  *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
-  *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
-  * @retval None
-  */
-void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
-{
-  /* Check the parameters */
-  assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
-  if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
-  {
-    SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
-  }
-  else
-  {
-    SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
-  }
-}
-
-/**
-  * @brief  Handle SYSTICK interrupt request.
-  * @retval None
-  */
-void HAL_SYSTICK_IRQHandler(void)
-{
-  HAL_SYSTICK_Callback();
-}
-
-/**
-  * @brief  SYSTICK callback.
-  * @retval None
-  */
-__weak void HAL_SYSTICK_Callback(void)
-{
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SYSTICK_Callback could be implemented in the user file
-   */
-}
-
-#if (__MPU_PRESENT == 1)
-/**
-  * @brief  Initialize and configure the Region and the memory to be protected.
-  * @param  MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
-  *                the initialization and configuration information.
-  * @retval None
-  */
-void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
-{
-  /* Check the parameters */
-  assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
-  assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
-
-  /* Set the Region number */
-  MPU->RNR = MPU_Init->Number;
-
-  if ((MPU_Init->Enable) != RESET)
-  {
-    /* Check the parameters */
-    assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
-    assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
-    assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
-    assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
-    assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
-    assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
-    assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
-    assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
-
-    MPU->RBAR = MPU_Init->BaseAddress;
-    MPU->RASR = ((uint32_t)MPU_Init->DisableExec        << MPU_RASR_XN_Pos)   |
-                ((uint32_t)MPU_Init->AccessPermission   << MPU_RASR_AP_Pos)   |
-                ((uint32_t)MPU_Init->TypeExtField       << MPU_RASR_TEX_Pos)  |
-                ((uint32_t)MPU_Init->IsShareable        << MPU_RASR_S_Pos)    |
-                ((uint32_t)MPU_Init->IsCacheable        << MPU_RASR_C_Pos)    |
-                ((uint32_t)MPU_Init->IsBufferable       << MPU_RASR_B_Pos)    |
-                ((uint32_t)MPU_Init->SubRegionDisable   << MPU_RASR_SRD_Pos)  |
-                ((uint32_t)MPU_Init->Size               << MPU_RASR_SIZE_Pos) |
-                ((uint32_t)MPU_Init->Enable             << MPU_RASR_ENABLE_Pos);
-  }
-  else
-  {
-    MPU->RBAR = 0x00;
-    MPU->RASR = 0x00;
-  }
-}
-#endif /* __MPU_PRESENT */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/src/stm32l4xx_hal_dac.c b/stmhal/hal/l4/src/stm32l4xx_hal_dac.c
deleted file mode 100644
index d797a232c1..0000000000
--- a/stmhal/hal/l4/src/stm32l4xx_hal_dac.c
+++ /dev/null
@@ -1,1183 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_dac.c
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   DAC HAL module driver.
-  *         This file provides firmware functions to manage the following 
-  *         functionalities of the Digital to Analog Converter (DAC) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions
-  *           + Peripheral State and Errors functions      
-  *     
-  *
-  @verbatim      
-  ==============================================================================
-                      ##### DAC Peripheral features #####
-  ==============================================================================
-    [..]        
-      *** DAC Channels ***
-      ====================  
-    [..]  
-    STM32L4 devices integrate two 12-bit Digital Analog Converters
-
-    The 2 converters (i.e. channel1 & channel2)
-    can be used independently or simultaneously (dual mode):
-      (#) DAC channel1 with DAC_OUT1 (PA4) as output or connected to on-chip 
-          peripherals (ex. OPAMPs, comparators).
-      (#) DAC channel2 with DAC_OUT2 (PA5) as output or connected to on-chip 
-          peripherals (ex. OPAMPs, comparators).
-      
-      *** DAC Triggers ***
-      ====================
-    [..]
-    Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
-    and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register. 
-    [..] 
-    Digital to Analog conversion can be triggered by:
-      (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9.
-          The used pin (GPIOx_PIN_9) must be configured in input mode.
-  
-      (#) Timers TRGO: TIM2, TIM3, TIM4, TIM5, TIM6 and TIM7 
-          (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T3_TRGO...)
-  
-      (#) Software using DAC_TRIGGER_SOFTWARE
-  
-      *** DAC Buffer mode feature ***
-      =============================== 
-      [..] 
-      Each DAC channel integrates an output buffer that can be used to 
-      reduce the output impedance, and to drive external loads directly
-      without having to add an external operational amplifier.
-      To enable, the output buffer use  
-      sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
-      [..]           
-      (@) Refer to the device datasheet for more details about output 
-          impedance value with and without output buffer.
-
-      *** DAC connect feature ***
-      =============================== 
-      [..] 
-      Each DAC channel can be connected internally. 
-      To connect, use
-      sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_ENABLE;
-                                               
-      *** GPIO configurations guidelines ***
-      =====================
-      [..] 
-      When a DAC channel is used (ex channel1 on PA4) and the other is not 
-      (ex channel2 on PA5 is configured in Analog and disabled).
-      Channel1 may disturb channel2 as coupling effect.
-      Note that there is no coupling on channel2 as soon as channel2 is turned on.
-      Coupling on adjacent channel could be avoided as follows:
-      when unused PA5 is configured as INPUT PULL-UP or DOWN. 
-      PA5 is configured in ANALOG just before it is turned on.     
-                                               
-      *** DAC Sample and Hold feature ***
-      ========================
-      [..] 
-      For each converter, 2 modes are supported: normal mode and 
-      "sample and hold" mode (i.e. low power mode).
-      In the sample and hold mode, the DAC core converts data, then holds the 
-      converted voltage on a capacitor. When not converting, the DAC cores and 
-      buffer are completely turned off between samples and the DAC output is 
-      tri-stated, therefore  reducing the overall power consumption. A new 
-      stabilization period is needed before each new conversion.
-
-      The sample and hold allow setting internal or external voltage @
-      low power consumption cost (output value can be at any given rate either 
-      by CPU or DMA).
-
-      The Sample and hold block and registers uses either LSI & run in 
-      several power modes: run mode, sleep mode, low power run, low power sleep 
-      mode & stop1 mode.
-          
-      Low power stop1 mode allows only static conversion.
-          
-      To enable Sample and Hold mode 
-      Enable LSI using HAL_RCC_OscConfig with RCC_OSCILLATORTYPE_LSI &
-      RCC_LSI_ON parameters.
-
-      Use DAC_InitStructure.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_ENABLE;
-         & DAC_ChannelConfTypeDef.DAC_SampleAndHoldConfig.DAC_SampleTime,
-           DAC_HoldTime & DAC_RefreshTime;
-    
-
-
-       *** DAC calibration feature ***
-       =================================== 
-      [..] 
-       (#)  The 2 converters (channel1 & channel2) provide calibration capabilities.  
-       (++) Calibration aims at correcting some offset of output buffer.
-       (++) The DAC uses either factory calibration settings OR user defined 
-           calibration (trimming) settings (i.e. trimming mode).
-       (++) The user defined settings can be figured out using self calibration 
-           handled by HAL_DACEx_SelfCalibrate.
-       (++) HAL_DACEx_SelfCalibrate:
-       (+++) Runs automatically the calibration.
-       (+++) Enables the user trimming mode
-       (+++) Updates a structure with trimming values with fresh calibration 
-            results. 
-            The user may store the calibration results for larger 
-            (ex monitoring the trimming as a function of temperature 
-            for instance)
-
-       *** DAC wave generation feature ***
-       =================================== 
-       [..]     
-       Both DAC channels can be used to generate
-         (#) Noise wave 
-         (#) Triangle wave
-            
-       *** DAC data format ***
-       =======================
-       [..]   
-       The DAC data format can be:
-         (#) 8-bit right alignment using DAC_ALIGN_8B_R
-         (#) 12-bit left alignment using DAC_ALIGN_12B_L
-         (#) 12-bit right alignment using DAC_ALIGN_12B_R
-  
-       *** DAC data value to voltage correspondence ***  
-       ================================================ 
-       [..] 
-       The analog output voltage on each DAC channel pin is determined
-       by the following equation:
-       [..]
-       DAC_OUTx = VREF+ * DOR / 4095
-       (+) with  DOR is the Data Output Register
-       [..]
-          VEF+ is the input voltage reference (refer to the device datasheet)
-       [..]
-        e.g. To set DAC_OUT1 to 0.7V, use
-       (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
-  
-       *** DMA requests ***
-       =====================
-       [..]
-       A DMA1 request can be generated when an external trigger (but not a software trigger) 
-       occurs if DMA1 requests are enabled using HAL_DAC_Start_DMA(). 
-       DMA requests are mapped as following:          
-      (#) DAC channel1: mapped either on
-      (++) DMA1 request 6 channel3 
-      (++) or DMA2 request channel4 which must be already configured
-      (#) DAC channel2: mapped either on
-      (++) DMA1 request 5 channel4 
-      (++) or DMA2 request 3 channel5 which must be already configured 
-     [..]
-    (@) For Dual mode and specific signal (Triangle and noise) generation please 
-        refer to Extended Features Driver description        
-      
-                      ##### How to use this driver #####
-  ==============================================================================
-    [..]          
-      (+) DAC APB clock must be enabled to get write access to DAC
-          registers using HAL_DAC_Init()
-      (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
-      (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
-      (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA() functions.
-
-     *** Calibration mode IO operation ***
-     ======================================
-     [..]    
-       (+) Retrieve the factory trimming (calibration settings) using HAL_DACEx_GetTrimOffset()
-       (+) Run the calibration using HAL_DACEx_SelfCalibrate() 
-       (+) Update the trimming while DAC running using HAL_DACEx_SetUserTrimming()
-
-     *** Polling mode IO operation ***
-     =================================
-     [..]    
-       (+) Start the DAC peripheral using HAL_DAC_Start() 
-       (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
-       (+) Stop the DAC peripheral using HAL_DAC_Stop()
-       
-     *** DMA mode IO operation ***    
-     ==============================
-     [..]    
-       (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length 
-           of data to be transferred at each end of conversion
-       (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()  
-           function is executed and user can add his own code by customization of function pointer 
-           HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
-       (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()  
-           function is executed and user can add his own code by customization of function pointer 
-           HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
-       (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can 
-            add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
-       (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
-           HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2()  
-           function is executed and user can add his own code by customization of function pointer 
-           HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() and
-           add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1()
-       (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
-                    
-     *** DAC HAL driver macros list ***
-     ============================================= 
-     [..]
-       Below the list of most used macros in DAC HAL driver.
-       
-      (+) __HAL_DAC_ENABLE : Enable the DAC peripheral
-      (+) __HAL_DAC_DISABLE : Disable the DAC peripheral
-      (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
-      (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
-      
-     [..]
-      (@) You can refer to the DAC HAL driver header file for more useful macros  
-   
- @endverbatim    
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-  /** @defgroup DAC DAC
-  * @brief DAC driver modules  
-  * @{
-  */ 
-
-#ifdef HAL_DAC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @addtogroup DAC_Private_Constants DAC Private Constants
-  * @{
-  */
-#define TIMEOUT_DAC_CALIBCONFIG    ((uint32_t)1)  /* 1ms                  */
-/**
-  * @}
-  */ 
-
-/* Private macro -------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup DAC_Private_Functions DAC Private Functions
-  * @{
-  */
-static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
-static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
-static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); 
-/**
-  * @}
-  */
-/* Exported functions -------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Functions DAC Exported Functions
-  * @{
-  */
-
-/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions 
- *
-@verbatim    
-  ==============================================================================
-              ##### Initialization and de-initialization functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Initialize and configure the DAC. 
-      (+) De-initialize the DAC. 
-         
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initialize the DAC peripheral according to the specified parameters
-  *         in the DAC_InitStruct and initialize the associated handle.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
-{ 
-  /* Check DAC handle */
-  if(hdac == NULL)
-  {
-     return HAL_ERROR;
-  }
-  /* Check the parameters */
-  assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
-  
-  if(hdac->State == HAL_DAC_STATE_RESET)
-  {  
-    /* Allocate lock resource and initialize it */
-    hdac->Lock = HAL_UNLOCKED;
-
-    /* Init the low level hardware */
-    HAL_DAC_MspInit(hdac);
-  }
-  
-  /* Initialize the DAC state*/
-  hdac->State = HAL_DAC_STATE_BUSY;
-  
-  /* Set DAC error code to none */
-  hdac->ErrorCode = HAL_DAC_ERROR_NONE;
-  
-  /* Initialize the DAC state*/
-  hdac->State = HAL_DAC_STATE_READY;
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deinitialize the DAC peripheral registers to their default reset values.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
-{
-  /* Check DAC handle */
-  if(hdac == NULL)
-  {
-     return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_BUSY;
-
-  /* DeInit the low level hardware */
-  HAL_DAC_MspDeInit(hdac);
-
-  /* Set DAC error code to none */
-  hdac->ErrorCode = HAL_DAC_ERROR_NONE;
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hdac);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initialize the DAC MSP.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
-{ 
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_DAC_MspInit could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  DeInitialize the DAC MSP.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.  
-  * @retval None
-  */
-__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_DAC_MspDeInit could be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_Exported_Functions_Group2 IO operation functions
- *  @brief    IO operation functions 
- *
-@verbatim   
-  ==============================================================================
-             ##### IO operation functions #####
-  ==============================================================================  
-    [..]  This section provides functions allowing to:
-      (+) Start conversion.
-      (+) Stop conversion.
-      (+) Start conversion and enable DMA transfer.
-      (+) Stop conversion and disable DMA transfer.
-      (+) Get result of conversion.
-                     
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables DAC and starts conversion of channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  
-  /* Process locked */
-  __HAL_LOCK(hdac);
-  
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_BUSY;
-  
-  /* Enable the Peripheral */
-  __HAL_DAC_ENABLE(hdac, Channel);
-
-  if(Channel == DAC_CHANNEL_1)
-  {
-    /* Check if software trigger enabled */
-    if((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == (DAC_CR_TEN1 | DAC_CR_TSEL1))
-    {
-      /* Enable the selected DAC software conversion */
-      SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
-    }
-  }
-  else
-  {
-    /* Check if software trigger enabled */
-    if((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_CR_TEN2 | DAC_CR_TSEL2))
-    {
-      /* Enable the selected DAC software conversion*/
-      SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
-    }
-  }
-  
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_READY;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hdac);
-    
-  /* Return function status */
-  return HAL_OK;
-}
-  
-/**
-  * @brief  Disables DAC and stop conversion of channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  
-  /* Disable the Peripheral */
-  __HAL_DAC_DISABLE(hdac, Channel);
-  
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_READY;
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enables DAC and starts conversion of channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @param  pData: The destination peripheral Buffer address.
-  * @param  Length: The length of data to be transferred from memory to DAC peripheral
-  * @param  Alignment: Specifies the data alignment for DAC channel.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
-  *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
-  *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
-{
-  uint32_t tmpreg = 0;
-    
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  assert_param(IS_DAC_ALIGN(Alignment));
-  
-  /* Process locked */
-  __HAL_LOCK(hdac);
-  
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_BUSY;
-  
-  if(Channel == DAC_CHANNEL_1)
-  {
-    /* Set the DMA transfer complete callback for channel1 */
-    hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
-    
-    /* Set the DMA half transfer complete callback for channel1 */
-    hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
-       
-    /* Set the DMA error callback for channel1 */
-    hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
-    
-    /* Enable the selected DAC channel1 DMA request */
-    SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
-    
-    /* Case of use of channel 1 */
-    switch(Alignment)
-    {
-      case DAC_ALIGN_12B_R:
-        /* Get DHR12R1 address */
-        tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
-        break;
-      case DAC_ALIGN_12B_L:
-        /* Get DHR12L1 address */
-        tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
-        break;
-      case DAC_ALIGN_8B_R:
-        /* Get DHR8R1 address */
-        tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
-        break;
-      default:
-        break;
-    }
-  }
-  else
-  {
-    /* Set the DMA transfer complete callback for channel2 */
-    hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
-    
-    /* Set the DMA half transfer complete callback for channel2 */
-    hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
-       
-    /* Set the DMA error callback for channel2 */
-    hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
-    
-    /* Enable the selected DAC channel2 DMA request */
-    SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
-    
-    /* Case of use of channel 2 */
-    switch(Alignment)
-    {
-      case DAC_ALIGN_12B_R:
-        /* Get DHR12R2 address */
-        tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
-        break;
-      case DAC_ALIGN_12B_L:
-        /* Get DHR12L2 address */
-        tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
-        break;
-      case DAC_ALIGN_8B_R:
-        /* Get DHR8R2 address */
-        tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
-        break;
-      default:
-        break;
-    }
-  }
-  
-  /* Enable the DMA channel */
-  if(Channel == DAC_CHANNEL_1)
-  {
-    /* Enable the DAC DMA underrun interrupt */
-    __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
-    
-    /* Enable the DMA channel */
-    HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
-  } 
-  else
-  {
-    /* Enable the DAC DMA underrun interrupt */
-    __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
-    
-    /* Enable the DMA channel */
-    HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
-  }
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hdac);
-
-  /* Enable the Peripheral */
-  __HAL_DAC_ENABLE(hdac, Channel);
-  
-  /* Return function status */
-  return HAL_OK;
-}
- 
-/**
-  * @brief  Disables DAC and stop conversion of channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected   
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
-   HAL_StatusTypeDef status = HAL_OK;
-    
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  
-  /* Disable the selected DAC channel DMA request */
-    hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel);
-    
-  /* Disable the Peripheral */
-  __HAL_DAC_DISABLE(hdac, Channel);
-  
-  /* Disable the DMA channel */
-  /* Channel1 is used */
-  if (Channel == DAC_CHANNEL_1)
-  {
-    /* Disable the DMA channel */
-    status = HAL_DMA_Abort(hdac->DMA_Handle1);
-    
-    /* Disable the DAC DMA underrun interrupt */
-    __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
-  }
-  else /* Channel2 is used for */
-  {
-    /* Disable the DMA channel */
-    status = HAL_DMA_Abort(hdac->DMA_Handle2);
-    
-    /* Disable the DAC DMA underrun interrupt */
-    __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
-  }
-  
-  /* Check if DMA Channel effectively disabled */
-  if (status != HAL_OK)
-  {
-    /* Update DAC state machine to error */
-    hdac->State = HAL_DAC_STATE_ERROR;
-  }
-  else
-  {
-    /* Change DAC state */
-    hdac->State = HAL_DAC_STATE_READY;
-  }
-  
-  /* Return function status */
-  return status;
-}
-
-/* DAC channel 2 is available on top of DAC channel 1 */
-
-/**
-  * @brief  Handles DAC interrupt request
-  *         This function uses the interruption of DMA
-  *         underrun.  
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
-{
-  if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
-  { 
-    /* Check underrun flag of DAC channel 1 */
-    if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
-    {
-      /* Change DAC state to error state */
-      hdac->State = HAL_DAC_STATE_ERROR;
-      
-      /* Set DAC error code to chanel1 DMA underrun error */
-      SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
-      
-      /* Clear the underrun flag */
-      __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
-      
-      /* Disable the selected DAC channel1 DMA request */
-      CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
-      
-      /* Error callback */ 
-      HAL_DAC_DMAUnderrunCallbackCh1(hdac);
-    }
-  }
-  if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
-  {
-    /* Check underrun flag of DAC channel 1 */
-    if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
-    {
-      /* Change DAC state to error state */
-      hdac->State = HAL_DAC_STATE_ERROR;
-      
-      /* Set DAC error code to channel2 DMA underrun error */
-      SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2);
-      
-      /* Clear the underrun flag */
-      __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
-      
-      /* Disable the selected DAC channel1 DMA request */
-      CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
-      
-      /* Error callback */ 
-      HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
-    }
-  }
-}
-
-/**
-  * @brief  Set the specified data holding register value for DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected  
-  * @param  Alignment: Specifies the data alignment.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
-  *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
-  *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
-  * @param  Data: Data to be loaded in the selected data holding register.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
-{  
-  __IO uint32_t tmp = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  assert_param(IS_DAC_ALIGN(Alignment));
-  assert_param(IS_DAC_DATA(Data));
-  
-  tmp = (uint32_t)hdac->Instance; 
-  if(Channel == DAC_CHANNEL_1)
-  {
-    tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
-  }
-  else
-  {
-    tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
-  }
-
-  /* Set the DAC channel selected data holding register */
-  *(__IO uint32_t *) tmp = Data;
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Conversion complete callback in non-blocking mode for Channel1 
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Conversion half DMA transfer callback in non-blocking mode for Channel1 
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Error DAC callback for Channel1.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DMA underrun DAC callback for channel1.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-  
-/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
- *  @brief    Peripheral Control functions 
- *
-@verbatim   
-  ==============================================================================
-             ##### Peripheral Control functions #####
-  ==============================================================================  
-    [..]  This section provides functions allowing to:
-      (+) Configure channels. 
-      (+) Set the specified data holding register value for DAC channel.
-      
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Returns the last data output value of the selected DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @retval The selected DAC channel data output value.
-  */
-uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  
-  /* Returns the DAC channel data output register value */
-  if(Channel == DAC_CHANNEL_1)
-  {
-    return hdac->Instance->DOR1;
-  }
-  else
-  {
-    return hdac->Instance->DOR2;
-  }
-}
-
-/**
-  * @brief  Configures the selected DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  sConfig: DAC configuration structure.
-  * @param  Channel: The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
-{
-  uint32_t tmpreg1 = 0, tmpreg2 = 0;
-  uint32_t tickstart = 0;
-   
-  /* Check the DAC parameters */
-  assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
-  assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
-  assert_param(IS_DAC_CHIP_CONNECTION(sConfig->DAC_ConnectOnChipPeripheral));
-  assert_param(IS_DAC_TRIMMING(sConfig->DAC_UserTrimming));
-  if ((sConfig->DAC_UserTrimming) == DAC_TRIMMING_USER)
-  {
-    assert_param(IS_DAC_TRIMMINGVALUE(sConfig->DAC_TrimmingValue));               
-  }
-  assert_param(IS_DAC_SAMPLEANDHOLD(sConfig->DAC_SampleAndHold));
-  if ((sConfig->DAC_SampleAndHold) == DAC_SAMPLEANDHOLD_ENABLE)
-  {
-    assert_param(IS_DAC_SAMPLETIME(sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime));
-    assert_param(IS_DAC_HOLDTIME(sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime));
-    assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)); 
-  }
-  assert_param(IS_DAC_CHANNEL(Channel));
- 
-  /* Process locked */
-  __HAL_LOCK(hdac);
-  
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_BUSY;
-  
-  if(sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE)
-  /* Sample on old configuration */ 
-  {
-    /* SampleTime */
-    if (Channel == DAC_CHANNEL_1)
-    {
-      /* Get timeout */
-      tickstart = HAL_GetTick();
-      
-      /* SHSR1 can be written when BWST1  equals RESET */
-      while (((hdac->Instance->SR) & DAC_SR_BWST1)!= RESET)
-      {
-        /* Check for the Timeout */
-        if((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
-        {
-          /* Update error code */
-          SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
-
-          /* Change the DMA state */
-          hdac->State = HAL_DAC_STATE_TIMEOUT;
-
-          return HAL_TIMEOUT;
-        }
-      }
-      HAL_Delay(1);
-      hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
-    }
-    else /* Channel 2 */
-    {
-      /* SHSR2 can be written when BWST2 equals RESET */
-
-      while (((hdac->Instance->SR) & DAC_SR_BWST2)!= RESET)
-      {
-        /* Check for the Timeout */
-        if((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
-        {
-          /* Update error code */
-          SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
-
-          /* Change the DMA state */
-          hdac->State = HAL_DAC_STATE_TIMEOUT;
-
-          return HAL_TIMEOUT;
-        }
-      }
-      HAL_Delay(1);
-      hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
-    }
-    /* HoldTime */
-    hdac->Instance->SHHR = (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime)<<Channel;
-    /* RefreshTime */
-    hdac->Instance->SHRR = (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)<<Channel;
-  }
-    
-  if(sConfig->DAC_UserTrimming == DAC_TRIMMING_USER)
-  /* USER TRIMMING */
-  {
-  /* Get the DAC CCR value */
-  tmpreg1 = hdac->Instance->CCR;
-  /* Clear trimming value */
-  tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << Channel);
-  /* Configure for the selected trimming offset */
-  tmpreg2 = sConfig->DAC_TrimmingValue;
-  /* Calculate CCR register value depending on DAC_Channel */
-  tmpreg1 |= tmpreg2 << Channel;
-  /* Write to DAC CCR */
-  hdac->Instance->CCR = tmpreg1;
-  }
-  /* else factory trimming is used (factory setting are available at reset)*/
-  /* SW Nothing has nothing to do */
-  
-  /* Get the DAC MCR value */
-  tmpreg1 = hdac->Instance->MCR;
-  /* Clear DAC_MCR_MODE2_0, DAC_MCR_MODE2_1 and DAC_MCR_MODE2_2 bits */
-  tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << Channel); 
-  /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */
-  tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | sConfig->DAC_ConnectOnChipPeripheral);
-  /* Calculate MCR register value depending on DAC_Channel */
-  tmpreg1 |= tmpreg2 << Channel;
-  /* Write to DAC MCR */
-  hdac->Instance->MCR = tmpreg1;
-  
-  /* DAC in normal operating mode hence clear DAC_CR_CENx bit */
-  CLEAR_BIT (hdac->Instance->CR, DAC_CR_CEN1 << Channel);
-  
-  /* Get the DAC CR value */
-  tmpreg1 = hdac->Instance->CR;
-  /* Clear TENx, TSELx, WAVEx and MAMPx bits */
-  tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << Channel); 
-  /* Configure for the selected DAC channel: trigger */
-  /* Set TSELx and TENx bits according to DAC_Trigger value */
-  tmpreg2 = (sConfig->DAC_Trigger);
-  /* Calculate CR register value depending on DAC_Channel */
-  tmpreg1 |= tmpreg2 << Channel;
-  /* Write to DAC CR */
-  hdac->Instance->CR = tmpreg1;
-      
-  /* Disable wave generation */
-  hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel);
-  
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_READY;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hdac);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
- *  @brief   Peripheral State and Errors functions 
- *
-@verbatim   
-  ==============================================================================
-            ##### Peripheral State and Errors functions #####
-  ==============================================================================  
-    [..]
-    This subsection provides functions allowing to
-      (+) Check the DAC state.
-      (+) Check the DAC Errors.
-        
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  return the DAC handle state
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval HAL state
-  */
-HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)
-{
-  /* Return DAC handle state */
-  return hdac->State;
-}
-
-
-/**
-  * @brief  Return the DAC error code
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval DAC Error Code
-  */
-uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
-{
-  return hdac->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup DAC_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  DMA conversion complete callback. 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)   
-{
-  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  HAL_DAC_ConvCpltCallbackCh1(hdac); 
-  
-  hdac->State= HAL_DAC_STATE_READY;
-}
-
-/**
-  * @brief  DMA half transfer complete callback. 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)   
-{
-    DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-    /* Conversion complete callback */
-    HAL_DAC_ConvHalfCpltCallbackCh1(hdac); 
-}
-
-/**
-  * @brief  DMA error callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)   
-{
-  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-    
-  /* Set DAC error code to DMA error */
-  hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
-    
-  HAL_DAC_ErrorCallbackCh1(hdac); 
-    
-  hdac->State= HAL_DAC_STATE_READY;
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/src/stm32l4xx_hal_dac_ex.c b/stmhal/hal/l4/src/stm32l4xx_hal_dac_ex.c
deleted file mode 100644
index c3446257bd..0000000000
--- a/stmhal/hal/l4/src/stm32l4xx_hal_dac_ex.c
+++ /dev/null
@@ -1,620 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_dac_ex.c
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   DAC HAL module driver.
-  *          This file provides firmware functions to manage the extended 
-  *          functionalities of the DAC peripheral.  
-  *     
-  *
-  @verbatim      
-  ==============================================================================
-                      ##### How to use this driver #####
-  ==============================================================================
-    [..]          
-      (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) :
-          Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
-          HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.  
-      (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
-      (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
-
-      (+) HAL_DACEx_SelfCalibrate to calibrate one DAC channel.
-      (+) HAL_DACEx_SetUserTrimming to set user trimming value.
-      (+) HAL_DACEx_GetTrimOffset to retrieve trimming value (factory setting 
-          after reset, user setting if HAL_DACEx_SetUserTrimming have been used 
-          at least one time after reset).
-
- @endverbatim    
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup DACEx DACEx
-  * @brief DAC Extended HAL module driver
-  * @{
-  */ 
-
-#ifdef HAL_DAC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-  
-/** @defgroup DACEx_Exported_Functions DACEx Exported Functions
-  * @{
-  */
-
-/** @defgroup DACEx_Exported_Functions_Group2 IO operation functions
- *  @brief    Extended IO operation functions 
- *
-@verbatim   
-  ==============================================================================
-                 ##### Extended features functions #####
-  ==============================================================================  
-    [..]  This section provides functions allowing to:
-      (+) Start conversion.
-      (+) Stop conversion.
-      (+) Start conversion and enable DMA transfer.
-      (+) Stop conversion and disable DMA transfer.
-      (+) Get result of conversion.
-      (+) Get result of dual mode conversion.
-                     
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enable or disable the selected DAC channel wave generation.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            DAC_CHANNEL_1 / DAC_CHANNEL_2
-  * @param  Amplitude: Select max triangle amplitude. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
-  *            @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
-  *            @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
-  *            @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
-  *            @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
-  *            @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
-  *            @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
-  *            @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
-  *            @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
-  *            @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
-  *            @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
-  *            @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095                               
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
-{  
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
-  
-  /* Process locked */
-  __HAL_LOCK(hdac);
-  
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_BUSY;
-  
-  /* Enable the triangle wave generation for the selected DAC channel */
-  MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_1 | Amplitude) << Channel);
-  
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_READY;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hdac);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enable or disable the selected DAC channel wave generation.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC. 
-  * @param  Channel: The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            DAC_CHANNEL_1 / DAC_CHANNEL_2
-  * @param  Amplitude: Unmask DAC channel LFSR for noise wave generation. 
-  *          This parameter can be one of the following values: 
-  *            @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation  
-  *            @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation 
-  *            @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation 
-  *            @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation 
-  *            @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation 
-  *            @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation 
-  *            @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation 
-  *            @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation 
-  *            @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation 
-  *            @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation 
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
-{   
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
-  
-  /* Process locked */
-  __HAL_LOCK(hdac);
-  
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_BUSY;
-     
-  /* Enable the noise wave generation for the selected DAC channel */
-  MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel);
-  
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_READY;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hdac);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-
-
-/**
-  * @brief  Set the specified data holding register value for dual DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *               the configuration information for the specified DAC.
-  * @param  Alignment: Specifies the data alignment for dual channel DAC.
-  *          This parameter can be one of the following values:
-  *            DAC_ALIGN_8B_R: 8bit right data alignment selected
-  *            DAC_ALIGN_12B_L: 12bit left data alignment selected
-  *            DAC_ALIGN_12B_R: 12bit right data alignment selected
-  * @param  Data1: Data for DAC Channel2 to be loaded in the selected data holding register.
-  * @param  Data2: Data for DAC Channel1 to be loaded in the selected data  holding register.
-  * @note   In dual mode, a unique register access is required to write in both
-  *          DAC channels at the same time.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
-{  
-  uint32_t data = 0, tmp = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_DAC_ALIGN(Alignment));
-  assert_param(IS_DAC_DATA(Data1));
-  assert_param(IS_DAC_DATA(Data2));
-  
-  /* Calculate and set dual DAC data holding register value */
-  if (Alignment == DAC_ALIGN_8B_R)
-  {
-    data = ((uint32_t)Data2 << 8) | Data1; 
-  }
-  else
-  {
-    data = ((uint32_t)Data2 << 16) | Data1;
-  }
-  
-  tmp = (uint32_t)hdac->Instance;
-  tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
-
-  /* Set the dual DAC selected data holding register */
-  *(__IO uint32_t *)tmp = data;
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Conversion complete callback in non-blocking mode for Channel2.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Conversion half DMA transfer callback in non-blocking mode for Channel2. 
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Error DAC callback for Channel2.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DMA underrun DAC callback for Channel2.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Run the self calibration of one DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  sConfig: DAC channel configuration structure.
-  * @param  Channel: The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @retval Updates DAC_TrimmingValue. , DAC_UserTrimming set to DAC_UserTrimming
-  * @retval HAL status
-  * @note   Calibration runs about 7 ms.
-  */
-
-HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
-{ 
-  HAL_StatusTypeDef status = HAL_OK;
-   
-  __IO uint32_t tmp = 0;
-  uint32_t trimmingvalue = 0;
-  uint32_t delta;
-  
-  /* store/restore channel configuration structure purpose */
-  uint32_t oldmodeconfiguration = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-    
- /* Check the DAC handle allocation */
- /* Check if DAC running */
-  if((hdac == NULL) || (hdac->State == HAL_DAC_STATE_BUSY))
-  {
-    status = HAL_ERROR;
-  }
-  
-  /* Process locked */
-  __HAL_LOCK(hdac);
-  
-  /* Store configuration */
-  oldmodeconfiguration = (hdac->Instance->MCR & (DAC_MCR_MODE1 << Channel));
-  
-  /* Disable the selected DAC channel */
-  CLEAR_BIT ((hdac->Instance->CR), (DAC_CR_EN1 << Channel));
-  
-  /* Set mode in MCR  for calibration */
-   MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << Channel), 0);
-   
-  /* Set DAC Channel1 DHR register to the middle value */
-  /* HAL_DAC_SetValue(hdac, Channel, DAC_ALIGN_12B_R, 0x0800); */
-  tmp = (uint32_t)hdac->Instance; 
-  if(Channel == DAC_CHANNEL_1)
-  {
-    tmp += DAC_DHR12R1_ALIGNMENT(DAC_ALIGN_12B_R);
-  }
-  else
-  {
-    tmp += DAC_DHR12R2_ALIGNMENT(DAC_ALIGN_12B_R);
-  }
-  *(__IO uint32_t *) tmp = 0x0800;
-     
-  /* Enable the selected DAC channel calibration */
-  /* i.e. set DAC_CR_CENx bit */
-  SET_BIT ((hdac->Instance->CR), (DAC_CR_CEN1 << Channel));
-  
-  /* Init trimming counter */    
-  /* Medium value */
-  trimmingvalue = 16; 
-  delta = 8;
-  while (delta != 0) 
-    {
-    /* Set candidate trimming */
-    MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<<Channel), (trimmingvalue<<Channel));
-  
-    /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */ 
-    /* i.e. minimum time needed between two calibration steps */
-    HAL_Delay(1);
-  
-    if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1<<Channel)) == RESET)
-      { 
-        /* DAC_SR_CAL_FLAGx is HIGH try higher trimming */
-        trimmingvalue += delta;
-      }
-      else
-      {
-        /* DAC_SR_CAL_FLAGx is LOW try lower trimming */
-        trimmingvalue -= delta;
-       }                   
-     delta >>= 1;
-    }
-  
-    /* Still need to check if right calibration is current value or one step below */
-    /* Indeed the first value that causes the DAC_SR_CAL_FLAGx bit to change from 0 to 1  */
-    /* Set candidate trimming */
-    MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<<Channel), (trimmingvalue<<Channel));
-  
-    /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */ 
-    /* i.e. minimum time needed between two calibration steps */
-    HAL_Delay(1);
-    
-    if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1<<Channel)) == RESET)
-      { 
-      /* OPAMP_CSR_OUTCAL is actually one value more */
-      trimmingvalue++;
-      /* Set right trimming */
-        MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<<Channel), (trimmingvalue<<Channel));
-      }
-    
-  /* Disable the selected DAC channel calibration */
-  /* i.e. clear DAC_CR_CENx bit */
-  CLEAR_BIT ((hdac->Instance->CR), (DAC_CR_CEN1 << Channel));
-  
-  sConfig->DAC_TrimmingValue = trimmingvalue;
-  sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
-  
-  /* Restore configuration */
-  MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << Channel), oldmodeconfiguration);
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hdac);
-  
-  return status;
-}
-
-/**
-  * @brief  Set the trimming mode and trimming value (user trimming mode applied).
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  sConfig: DAC configuration structure updated with new DAC trimming value.
-  * @param  Channel: The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @param  NewTrimmingValue: DAC new trimming value
-  * @retval HAL status
-  */
-
-HAL_StatusTypeDef HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel, uint32_t NewTrimmingValue)
-{ 
-  HAL_StatusTypeDef status = HAL_OK;
-     
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  assert_param(IS_DAC_NEWTRIMMINGVALUE(NewTrimmingValue));
-  
- /* Check the DAC handle allocation */
-  if(hdac == NULL)
-  {
-    status = HAL_ERROR;
-  }
-  
-  /* Process locked */
-  __HAL_LOCK(hdac);
-  
-  /* Set new trimming */
-  MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<<Channel), (NewTrimmingValue<<Channel));
-  
-  /* Update trimming mode */
-  sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
-  sConfig->DAC_TrimmingValue = NewTrimmingValue;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hdac);
-    
-  return status;
-}
-
-/**
-  * @brief  Return the DAC trimming value.
-  * @param  hdac : DAC handle
-  * @param  Channel: The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @retval Trimming value : range: 0->31
-  *         
- */
-
-uint32_t HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel)
-{
-  uint32_t trimmingvalue = 0;
-  
-  /* Check the DAC handle allocation */
-  /* And not in Reset state */
-  if((hdac == NULL) || (hdac->State == HAL_DAC_STATE_RESET))
-  {
-    return HAL_ERROR;
-  }
-  else
-  {
-    /* Check the parameter */
-    assert_param(IS_DAC_CHANNEL(Channel));
-
-    /* Retrieve trimming  */
-    trimmingvalue = ((hdac->Instance->CCR & (DAC_CCR_OTRIM1 << Channel)) >> Channel);
-  }  
-  return trimmingvalue;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup DACEx_Exported_Functions_Group3 Peripheral Control functions
- *  @brief    Extended Peripheral Control functions 
- *
-@verbatim   
-  ==============================================================================
-             ##### Peripheral Control functions #####
-  ==============================================================================  
-    [..]  This section provides functions allowing to:
-      (+) Configure channels. 
-      (+) Set the specified data holding register value for DAC channel.
-      
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the last data output value of the selected DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval The selected DAC channel data output value.
-  */
-uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
-{
-  uint32_t tmp = 0;
-  
-  tmp |= hdac->Instance->DOR1;
-
-  tmp |= hdac->Instance->DOR2 << 16;
-  
-  /* Returns the DAC channel data output register value */
-  return tmp;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup DACEx_Private_Functions DACEx private functions
- *  @brief    Extended private functions
-   * @{
-  */
-
-/**
-  * @brief  DMA conversion complete callback. 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)   
-{
-  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  HAL_DACEx_ConvCpltCallbackCh2(hdac); 
-  
-  hdac->State= HAL_DAC_STATE_READY;
-}
-
-/**
-  * @brief  DMA half transfer complete callback. 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)   
-{
-    DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-    /* Conversion complete callback */
-    HAL_DACEx_ConvHalfCpltCallbackCh2(hdac); 
-}
-
-/**
-  * @brief  DMA error callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)   
-{
-  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-    
-  /* Set DAC error code to DMA error */
-  hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
-    
-  HAL_DACEx_ErrorCallbackCh2(hdac); 
-    
-  hdac->State= HAL_DAC_STATE_READY;
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/src/stm32l4xx_hal_dma.c b/stmhal/hal/l4/src/stm32l4xx_hal_dma.c
deleted file mode 100644
index 81ed8eabc7..0000000000
--- a/stmhal/hal/l4/src/stm32l4xx_hal_dma.c
+++ /dev/null
@@ -1,899 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_dma.c
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   DMA HAL module driver.
-  *    
-  *         This file provides firmware functions to manage the following
-  *         functionalities of the Direct Memory Access (DMA) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral State and errors functions
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-  [..]
-   (#) Enable and configure the peripheral to be connected to the DMA Channel
-       (except for internal SRAM / FLASH memories: no initialization is 
-       necessary). Please refer to the Reference manual for connection between peripherals
-       and DMA requests.
-
-   (#) For a given Channel, program the required configuration through the following parameters:
-       Channel request, Transfer Direction, Source and Destination data formats,
-       Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
-       using HAL_DMA_Init() function.
-
-   (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error 
-       detection.
-                    
-   (#) Use HAL_DMA_Abort() function to abort the current transfer
-                   
-     -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.
-     *** Polling mode IO operation ***
-     =================================
-    [..]
-          (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
-              address and destination address and the Length of data to be transferred
-          (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
-              case a fixed Timeout can be configured by User depending from his application.
-
-     *** Interrupt mode IO operation ***
-     ===================================
-    [..]
-          (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
-          (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
-          (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
-              Source address and destination address and the Length of data to be transferred.
-              In this case the DMA interrupt is configured
-          (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
-          (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
-              add his own function by customization of function pointer XferCpltCallback and
-              XferErrorCallback (i.e. a member of DMA handle structure).
-
-     *** DMA HAL driver macros list ***
-     ============================================= 
-      [..]
-       Below the list of most used macros in DMA HAL driver.
-
-       (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
-       (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
-       (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
-       (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
-       (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
-       (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
-       (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not. 
-
-     [..] 
-      (@) You can refer to the DMA HAL driver header file for more useful macros  
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup DMA DMA
-  * @brief DMA HAL module driver
-  * @{
-  */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup DMA_Private_Constants DMA Private Constants
-  * @{
-  */
-#define HAL_TIMEOUT_DMA_ABORT    ((uint32_t)1000)  /* 1s  */
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup DMA_Private_Functions DMA Private Functions
-  * @{
-  */
-static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-/**
-  * @}
-  */
-
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Functions DMA Exported Functions
-  * @{
-  */
-
-/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @brief   Initialization and de-initialization functions 
- *
-@verbatim
- ===============================================================================
-             ##### Initialization and de-initialization functions  #####
- ===============================================================================
-    [..]
-    This section provides functions allowing to initialize the DMA Channel source
-    and destination addresses, incrementation and data sizes, transfer direction, 
-    circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
-    [..]
-    The HAL_DMA_Init() function follows the DMA configuration procedures as described in
-    reference manual.  
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initialize the DMA according to the specified
-  *         parameters in the DMA_InitTypeDef and initialize the associated handle.
-  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Channel.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
-{
-  uint32_t tmp = 0;
-
-  /* Check the DMA handle allocation */
-  if(hdma == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
-  assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
-  assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
-  assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
-  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
-  assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
-  assert_param(IS_DMA_MODE(hdma->Init.Mode));
-  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
-  if(hdma->Init.Direction != DMA_MEMORY_TO_MEMORY)
-  {
-    assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request));
-  }
-  
-  if(hdma->State == HAL_DMA_STATE_RESET)
-  {  
-    /* Allocate lock resource and initialize it */
-    hdma->Lock = HAL_UNLOCKED;
-  }
-
-  /* Change DMA peripheral state */
-  hdma->State = HAL_DMA_STATE_BUSY;
-
-  /* Get the CR register value */
-  tmp = hdma->Instance->CCR;
-
-  /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */
-  tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  | \
-                      DMA_CCR_MINC  | DMA_CCR_PINC   | DMA_CCR_CIRC   | \
-                      DMA_CCR_DIR));
-
-  /* Prepare the DMA Channel configuration */
-  tmp |=  hdma->Init.Direction        |
-          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
-          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
-          hdma->Init.Mode                | hdma->Init.Priority;
-
-  /* Write to DMA Channel CR register */
-  hdma->Instance->CCR = tmp;
-
-  /* Set request selection */
-  if(hdma->Init.Direction != DMA_MEMORY_TO_MEMORY)
-  {
-    /* Write to DMA channel selection register */
-    if (hdma->Instance == DMA1_Channel1)
-    {
-      /*Reset request selection for DMA1 Channel1*/
-      DMA1_CSELR->CSELR &= ~DMA_CSELR_C1S;
-
-      /* Configure request selection for DMA1 Channel1 */
-      DMA1_CSELR->CSELR |= hdma->Init.Request;
-    }
-    else if (hdma->Instance == DMA1_Channel2)
-    {
-      /*Reset request selection for DMA1 Channel2*/
-      DMA1_CSELR->CSELR &= ~DMA_CSELR_C2S;
-
-      /* Configure request selection for DMA1 Channel2 */
-      DMA1_CSELR->CSELR |= (uint32_t)(hdma->Init.Request << 4);
-    }
-    else if (hdma->Instance == DMA1_Channel3)
-    {
-      /*Reset request selection for DMA1 Channel3*/
-      DMA1_CSELR->CSELR &= ~DMA_CSELR_C3S;
-
-      /* Configure request selection for DMA1 Channel3 */
-      DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 8);
-    }
-    else if (hdma->Instance == DMA1_Channel4)
-    {
-      /*Reset request selection for DMA1 Channel4*/
-      DMA1_CSELR->CSELR &= ~DMA_CSELR_C4S;
-
-      /* Configure request selection for DMA1 Channel4 */
-      DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 12);
-    }
-    else if (hdma->Instance == DMA1_Channel5)
-    {
-      /*Reset request selection for DMA1 Channel5*/
-      DMA1_CSELR->CSELR &= ~DMA_CSELR_C5S;
-
-      /* Configure request selection for DMA1 Channel5 */
-      DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 16);
-    }
-    else if (hdma->Instance == DMA1_Channel6)
-    {
-      /*Reset request selection for DMA1 Channel6*/
-      DMA1_CSELR->CSELR &= ~DMA_CSELR_C6S;
-
-      /* Configure request selection for DMA1 Channel6 */
-      DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 20);
-    }
-    else if (hdma->Instance == DMA1_Channel7)
-    {
-      /*Reset request selection for DMA1 Channel7*/
-      DMA1_CSELR->CSELR &= ~DMA_CSELR_C7S;
-
-      /* Configure request selection for DMA1 Channel7 */
-      DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 24);
-    }
-    else if (hdma->Instance == DMA2_Channel1)
-    {
-      /*Reset request selection for DMA2 Channel1*/
-      DMA2_CSELR->CSELR &= ~DMA_CSELR_C1S;
-
-      /* Configure request selection for DMA2 Channel1 */
-      DMA2_CSELR->CSELR |= hdma->Init.Request;
-    }
-    else if (hdma->Instance == DMA2_Channel2)
-    {
-      /*Reset request selection for DMA2 Channel2*/
-      DMA2_CSELR->CSELR &= ~DMA_CSELR_C2S;
-
-      /* Configure request selection for DMA2 Channel2 */
-      DMA2_CSELR->CSELR |= (uint32_t)(hdma->Init.Request << 4);
-    }
-    else if (hdma->Instance == DMA2_Channel3)
-    {
-      /*Reset request selection for DMA2 Channel3*/
-      DMA2_CSELR->CSELR &= ~DMA_CSELR_C3S;
-
-      /* Configure request selection for DMA2 Channel3 */
-      DMA2_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 8);
-    }
-    else if (hdma->Instance == DMA2_Channel4)
-    {
-      /*Reset request selection for DMA2 Channel4*/
-      DMA2_CSELR->CSELR &= ~DMA_CSELR_C4S;
-
-      /* Configure request selection for DMA2 Channel4 */
-      DMA2_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 12);
-    }
-    else if (hdma->Instance == DMA2_Channel5)
-    {
-      /*Reset request selection for DMA2 Channel5*/
-      DMA2_CSELR->CSELR &= ~DMA_CSELR_C5S;
-
-      /* Configure request selection for DMA2 Channel5 */
-      DMA2_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 16);
-    }
-    else if (hdma->Instance == DMA2_Channel6)
-    {
-      /*Reset request selection for DMA2 Channel6*/
-      DMA2_CSELR->CSELR &= ~DMA_CSELR_C6S;
-
-      /* Configure request selection for DMA2 Channel6 */
-      DMA2_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 20);
-    }
-    else if (hdma->Instance == DMA2_Channel7)
-    {
-      /*Reset request selection for DMA2 Channel7*/
-      DMA2_CSELR->CSELR &= ~DMA_CSELR_C7S;
-
-      /* Configure request selection for DMA2 Channel7 */
-      DMA2_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 24);
-    }
-  }
-
-  /* Initialize the error code */
-  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
-  /* Initialize the DMA state*/
-  hdma->State  = HAL_DMA_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitialize the DMA peripheral.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Channel.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
-{
-  /* Check the DMA handle allocation */
-  if(hdma == NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  /* Check the parameters */
-  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
-
-  /* Check the DMA peripheral state */
-  if(hdma->State == HAL_DMA_STATE_BUSY)
-  {
-     return HAL_ERROR;
-  }
-
-  /* Disable the selected DMA Channelx */
-  __HAL_DMA_DISABLE(hdma);
-
-  /* Reset DMA Channel control register */
-  hdma->Instance->CCR  = 0;
-
-  /* Reset DMA Channel Number of Data to Transfer register */
-  hdma->Instance->CNDTR = 0;
-
-  /* Reset DMA Channel peripheral address register */
-  hdma->Instance->CPAR  = 0;
-
-  /* Reset DMA Channel memory address register */
-  hdma->Instance->CMAR = 0;
-
-  /* Clear all flags */
-  __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
-  __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
-  __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
-  __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
-
-  /* Reset DMA channel selection register */
-  if (hdma->Instance == DMA1_Channel1)
-  {
-    /*Reset DMA request*/
-    DMA1_CSELR->CSELR &= ~DMA_CSELR_C1S;
-  }
-  else if (hdma->Instance == DMA1_Channel2)
-  {
-    /*Reset DMA request*/
-    DMA1_CSELR->CSELR &= ~DMA_CSELR_C2S;
-  }
-  else if (hdma->Instance == DMA1_Channel3)
-  {
-    /*Reset DMA request*/
-    DMA1_CSELR->CSELR &= ~DMA_CSELR_C3S;
-  }
-  else if (hdma->Instance == DMA1_Channel4)
-  {
-    /*Reset DMA request*/
-    DMA1_CSELR->CSELR &= ~DMA_CSELR_C4S;
-  }
-  else if (hdma->Instance == DMA1_Channel5)
-  {
-    /*Reset DMA request*/
-    DMA1_CSELR->CSELR &= ~DMA_CSELR_C5S;
-  }
-  else if (hdma->Instance == DMA1_Channel6)
-  {
-    /*Reset DMA request*/
-    DMA1_CSELR->CSELR &= ~DMA_CSELR_C6S;
-  }
-  else if (hdma->Instance == DMA1_Channel7)
-  {
-    /*Reset DMA request*/
-    DMA1_CSELR->CSELR &= ~DMA_CSELR_C7S;
-  }
-  else if (hdma->Instance == DMA2_Channel1)
-  {
-    /*Reset DMA request*/
-    DMA2_CSELR->CSELR &= ~DMA_CSELR_C1S;
-  }
-  else if (hdma->Instance == DMA2_Channel2)
-  {
-    /*Reset DMA request*/
-    DMA2_CSELR->CSELR &= ~DMA_CSELR_C2S;
-  }
-  else if (hdma->Instance == DMA2_Channel3)
-  {
-    /*Reset DMA request*/
-    DMA2_CSELR->CSELR &= ~DMA_CSELR_C3S;
-  }
-  else if (hdma->Instance == DMA2_Channel4)
-  {
-    /*Reset DMA request*/
-    DMA2_CSELR->CSELR &= ~DMA_CSELR_C4S;
-  }
-  else if (hdma->Instance == DMA2_Channel5)
-  {
-    /*Reset DMA request*/
-    DMA2_CSELR->CSELR &= ~DMA_CSELR_C5S;
-  }
-  else if (hdma->Instance == DMA2_Channel6)
-  {
-    /*Reset DMA request*/
-    DMA2_CSELR->CSELR &= ~DMA_CSELR_C6S;
-  }
-  else if (hdma->Instance == DMA2_Channel7)
-  {
-    /*Reset DMA request*/
-    DMA2_CSELR->CSELR &= ~DMA_CSELR_C7S;
-  }
-
-  /* Initialize the error code */
-  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
-  /* Initialize the DMA state */
-  hdma->State = HAL_DMA_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hdma);
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
- *  @brief   Input and Output operation functions
- *
-@verbatim
- ===============================================================================
-                      #####  IO operation functions  #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Configure the source, destination address and data length and Start DMA transfer
-      (+) Configure the source, destination address and data length and
-          Start DMA transfer with interrupt
-      (+) Abort DMA transfer
-      (+) Poll for transfer complete
-      (+) Handle DMA interrupt request
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Start the DMA Transfer.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Channel.
-  * @param  SrcAddress: The source memory Buffer address
-  * @param  DstAddress: The destination memory Buffer address
-  * @param  DataLength: The length of data to be transferred from source to destination
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{
-  /* Process locked */
-  __HAL_LOCK(hdma);
-
-  /* Change DMA peripheral state */
-  hdma->State = HAL_DMA_STATE_BUSY;
-
-   /* Check the parameters */
-  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-
-  /* Disable the peripheral */
-  __HAL_DMA_DISABLE(hdma);
-
-  /* Configure the source, destination address and the data length */
-  DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
-
-  /* Enable the Peripheral */
-  __HAL_DMA_ENABLE(hdma);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Start the DMA Transfer with interrupt enabled.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Channel.
-  * @param  SrcAddress: The source memory Buffer address
-  * @param  DstAddress: The destination memory Buffer address
-  * @param  DataLength: The length of data to be transferred from source to destination
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{
-  /* Process locked */
-  __HAL_LOCK(hdma);
-
-  /* Change DMA peripheral state */
-  hdma->State = HAL_DMA_STATE_BUSY;
-
-   /* Check the parameters */
-  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-
-  /* Disable the peripheral */
-  __HAL_DMA_DISABLE(hdma);
-
-  /* Configure the source, destination address and the data length */
-  DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
-
-  /* Enable the transfer complete interrupt */
-  /* Enable the Half transfer complete interrupt */
-  /* Enable the transfer Error interrupt */
-  __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
-
-   /* Enable the Peripheral */
-  __HAL_DMA_ENABLE(hdma);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort the DMA Transfer.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Channel.
-  *                   
-  * @note  After disabling a DMA Channel, a check for wait until the DMA Channel is 
-  *        effectively disabled is added. If a Channel is disabled 
-  *        while a data transfer is ongoing, the current data will be transferred
-  *        and the Channel will be effectively disabled only after the transfer of
-  *        this single data is finished.  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
-{
-  uint32_t tickstart = 0;
-
-  /* Disable the channel */
-  __HAL_DMA_DISABLE(hdma);
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  /* Check if the DMA Channel is effectively disabled */
-  while((hdma->Instance->CCR & DMA_CCR_EN) != 0)
-  {
-    /* Check for the Timeout */
-    if((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT)
-    {
-      /* Update error code */
-      hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
-
-      /* Change the DMA state */
-      hdma->State = HAL_DMA_STATE_TIMEOUT;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hdma);
-
-      return HAL_TIMEOUT;
-    }
-  }
-  /* Change the DMA state */
-  hdma->State = HAL_DMA_STATE_READY;
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hdma);
-  
-  return HAL_OK; 
-}
-
-/**
-  * @brief  Polling for transfer complete.
-  * @param  hdma:    pointer to a DMA_HandleTypeDef structure that contains
-  *                  the configuration information for the specified DMA Channel.
-  * @param  CompleteLevel: Specifies the DMA level complete.
-  * @param  Timeout:       Timeout duration.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
-{
-  uint32_t temp;
-  uint32_t tickstart = 0;
-
-  /* Get the level transfer complete flag */
-  if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
-  {
-    /* Transfer Complete flag */
-    temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma);
-  }
-  else
-  {
-    /* Half Transfer Complete flag */
-    temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma);
-  }
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET)
-  {
-    if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET))
-    {
-      /* Clear the transfer error flags */
-      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
-
-      /* Update error code */
-      SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE);
-
-      /* Change the DMA state */
-      hdma->State= HAL_DMA_STATE_ERROR;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hdma);
-
-      return HAL_ERROR;
-    }
-    /* Check for the Timeout */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
-      {
-        /* Update error code */
-        hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
-
-        /* Change the DMA state */
-        hdma->State = HAL_DMA_STATE_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hdma);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
-  {
-    /* Clear the transfer complete flag */
-    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
-
-    /* The selected Channelx EN bit is cleared (DMA is disabled and
-    all transfers are complete) */
-    hdma->State = HAL_DMA_STATE_READY;
-
-  }
-  else
-  {
-    /* Clear the half transfer complete flag */
-    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
-
-    hdma->State = HAL_DMA_STATE_READY_HALF;
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hdma);  
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle DMA interrupt request.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Channel.
-  * @retval None
-  */
-void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
-{
-  /* Transfer Error Interrupt management ***************************************/
-  if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)
-  {
-    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
-    {
-      /* Disable the transfer error interrupt */
-      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE);
-
-      /* Clear the transfer error flag */
-      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
-
-      /* Update error code */
-      hdma->ErrorCode |= HAL_DMA_ERROR_TE;
-
-      /* Change the DMA state */
-      hdma->State = HAL_DMA_STATE_READY;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hdma);
-
-      if (hdma->XferErrorCallback != NULL)
-      {
-        /* Transfer error callback */
-        hdma->XferErrorCallback(hdma);
-      }
-    }
-  }
-
-  /* Half Transfer Complete Interrupt management ******************************/
-  if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET)
-  {
-    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
-    {
-      /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
-      if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
-      {
-        /* Disable the half transfer interrupt */
-        __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
-      }
-      /* Clear the half transfer complete flag */
-      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
-
-      /* Change DMA peripheral state */
-      hdma->State = HAL_DMA_STATE_READY_HALF;
-
-      if(hdma->XferHalfCpltCallback != NULL)
-      {
-        /* Half transfer callback */
-        hdma->XferHalfCpltCallback(hdma);
-      }
-    }
-  }
-
-  /* Transfer Complete Interrupt management ***********************************/
-  if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET)
-  {
-    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
-    {
-      if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
-      {
-        /* Disable the transfer complete interrupt */
-        __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC);
-      }
-      /* Clear the transfer complete flag */
-      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
-
-      /* Update error code */
-      hdma->ErrorCode |= HAL_DMA_ERROR_NONE;
-
-      /* Change the DMA state */
-      hdma->State = HAL_DMA_STATE_READY;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hdma);
-
-      if(hdma->XferCpltCallback != NULL)
-      {
-        /* Transfer complete callback */
-        hdma->XferCpltCallback(hdma);
-      }
-    }
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
- *  @brief    Peripheral State and Errors functions
- *
-@verbatim
- ===============================================================================
-            ##### Peripheral State and Errors functions #####
- ===============================================================================  
-    [..]
-    This subsection provides functions allowing to
-      (+) Check the DMA state
-      (+) Get error code
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the DMA hande state.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Channel.
-  * @retval HAL state
-  */
-HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
-{
-  /* Return DMA handle state */
-  return hdma->State;
-}
-
-/**
-  * @brief  Return the DMA error code.
-  * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains
-  *              the configuration information for the specified DMA Channel.
-  * @retval DMA Error Code
-  */
-uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
-{
-  return hdma->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup DMA_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Sets the DMA Transfer parameter.
-  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
-  *                     the configuration information for the specified DMA Channel.
-  * @param  SrcAddress: The source memory Buffer address
-  * @param  DstAddress: The destination memory Buffer address
-  * @param  DataLength: The length of data to be transferred from source to destination
-  * @retval HAL status
-  */
-static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{
-  /* Configure DMA Channel data length */
-  hdma->Instance->CNDTR = DataLength;
-
-  /* Peripheral to Memory */
-  if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
-  {
-    /* Configure DMA Channel destination address */
-    hdma->Instance->CPAR = DstAddress;
-
-    /* Configure DMA Channel source address */
-    hdma->Instance->CMAR = SrcAddress;
-  }
-  /* Memory to Peripheral */
-  else
-  {
-    /* Configure DMA Channel source address */
-    hdma->Instance->CPAR = SrcAddress;
-
-    /* Configure DMA Channel destination address */
-    hdma->Instance->CMAR = DstAddress;
-  }
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_DMA_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/src/stm32l4xx_hal_flash.c b/stmhal/hal/l4/src/stm32l4xx_hal_flash.c
deleted file mode 100644
index d7c837b26b..0000000000
--- a/stmhal/hal/l4/src/stm32l4xx_hal_flash.c
+++ /dev/null
@@ -1,773 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_flash.c
-  * @author  MCD Application Team
-  * @version V1.3.0 
-  * @date    29-January-2016
-  * @brief   FLASH HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the internal FLASH memory:
-  *           + Program operations functions
-  *           + Memory Control functions 
-  *           + Peripheral Errors functions
-  *  
- @verbatim    
-  ==============================================================================
-                        ##### FLASH peripheral features #####
-  ==============================================================================
-           
-  [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses 
-       to the Flash memory. It implements the erase and program Flash memory operations 
-       and the read and write protection mechanisms.
-      
-  [..] The Flash memory interface accelerates code execution with a system of instruction
-       prefetch and cache lines. 
-
-  [..] The FLASH main features are:
-      (+) Flash memory read operations
-      (+) Flash memory program/erase operations
-      (+) Read / write protections
-      (+) Option bytes programming
-      (+) Prefetch on I-Code
-      (+) 32 cache lines of 4*64 bits on I-Code
-      (+) 8 cache lines of 4*64 bits on D-Code
-      (+) Error code correction (ECC) : Data in flash are 72-bits word
-          (8 bits added per double word)
-      
-      
-                        ##### How to use this driver #####
- ==============================================================================
-    [..]                             
-      This driver provides functions and macros to configure and program the FLASH  
-      memory of all STM32L4xx devices. 
-   
-      (#) Flash Memory IO Programming functions: 
-           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and 
-                HAL_FLASH_Lock() functions
-           (++) Program functions: double word and fast program (full row programming)
-           (++) There Two modes of programming :
-            (+++) Polling mode using HAL_FLASH_Program() function
-            (+++) Interrupt mode using HAL_FLASH_Program_IT() function
-    
-      (#) Interrupts and flags management functions : 
-           (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
-           (++) Callback functions are called when the flash operations are finished :
-                HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise
-                HAL_FLASH_OperationErrorCallback()
-           (++) Get error flag status by calling HAL_GetError()    
-           
-      (#) Option bytes management functions :
-           (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and
-                HAL_FLASH_OB_Lock() functions
-           (++) Launch the reload of the option bytes using HAL_FLASH_Launch() function.
-                In this case, a reset is generated
-                         
-    [..] 
-      In addition to these functions, this driver includes a set of macros allowing
-      to handle the following operations:
-       (+) Set the latency
-       (+) Enable/Disable the prefetch buffer
-       (+) Enable/Disable the Instruction cache and the Data cache
-       (+) Reset the Instruction cache and the Data cache
-       (+) Enable/Disable the Flash power-down during low-power run and sleep modes
-       (+) Enable/Disable the Flash interrupts
-       (+) Monitor the Flash flags status
-    
- @endverbatim                      
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup FLASH FLASH
-  * @brief FLASH HAL module driver
-  * @{
-  */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private defines -----------------------------------------------------------*/ 
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup FLASH_Private_Variables FLASH Private Variables
- * @{
- */
-/**
-  * @brief  Variable used for Program/Erase sectors under interruption 
-  */
-FLASH_ProcessTypeDef pFlash;
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup FLASH_Private_Functions FLASH Private Functions
- * @{
- */
-HAL_StatusTypeDef    FLASH_WaitForLastOperation(uint32_t Timeout);
-extern void          FLASH_PageErase(uint32_t Page, uint32_t Banks);
-extern void          FLASH_FlushCaches(void);
-static void          FLASH_SetErrorCode(void);
-static void          FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);
-static void          FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
-  * @{
-  */
-
-/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions 
- *  @brief   Programming operation functions 
- *
-@verbatim   
- ===============================================================================
-                  ##### Programming operation functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to manage the FLASH 
-    program operations.
- 
-@endverbatim
-  * @{
-  */
- 
-/**
-  * @brief  Program double word or fast program of a row at a specified address.
-  * @param  TypeProgram:  Indicate the way to program at a specified address.
-  *                           This parameter can be a value of @ref FLASH_Type_Program
-  * @param  Address:  specifies the address to be programmed.
-  * @param  Data: specifies the data to be programmed
-  *                This parameter is the data for the double word program and the address where 
-  *                are stored the data for the row fast program
-  * 
-  * @retval HAL_StatusTypeDef HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
-{
-  HAL_StatusTypeDef status = HAL_ERROR;
-  uint32_t prog_bit = 0;
-  
-  /* Process Locked */
-  __HAL_LOCK(&pFlash);
-
-  /* Check the parameters */
-  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-  
-  if(status == HAL_OK)
-  {
-    pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
-    if(TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD)
-    {
-      /* Program double-word (64-bit) at a specified address */
-      FLASH_Program_DoubleWord(Address, Data);
-      prog_bit = FLASH_CR_PG;
-    }
-    else if((TypeProgram == FLASH_TYPEPROGRAM_FAST) || (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST))
-    {
-      /* Fast program a 32 row double-word (64-bit) at a specified address */
-      FLASH_Program_Fast(Address, (uint32_t)Data);
-      
-      /* If it is the last row, the bit will be cleared at the end of the operation */
-      if(TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST)
-      {
-        prog_bit = FLASH_CR_FSTPG;
-      }
-    }
-
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-    
-    /* If the program operation is completed, disable the PG or FSTPG Bit */
-    if (prog_bit != 0)
-    {
-      CLEAR_BIT(FLASH->CR, prog_bit);
-    }
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(&pFlash);
-
-  return status;  
-}
-
-/**
-  * @brief  Program double word or fast program of a row at a specified address with interrupt enabled.
-  * @param  TypeProgram:  Indicate the way to program at a specified address.
-  *                           This parameter can be a value of @ref FLASH_Type_Program
-  * @param  Address:  specifies the address to be programmed.
-  * @param  Data: specifies the data to be programmed
-  *                This parameter is the data for the double word program and the address where 
-  *                are stored the data for the row fast program
-  * 
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
-
-  /* Process Locked */
-  __HAL_LOCK(&pFlash);
-
-  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
-  /* Set internal variables used by the IRQ handler */
-  if(TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST)
-  {
-    pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_LAST;
-  }
-  else
-  {
-    pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;
-  }
-  pFlash.Address = Address;
-    
-  /* Enable End of Operation and Error interrupts */
-  __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
-
-  if(TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD)
-  {
-    /* Program double-word (64-bit) at a specified address */
-    FLASH_Program_DoubleWord(Address, Data);
-  }
-    else if((TypeProgram == FLASH_TYPEPROGRAM_FAST) || (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST))
-  {
-    /* Fast program a 32 row double-word (64-bit) at a specified address */
-    FLASH_Program_Fast(Address, (uint32_t)Data);
-  }
-
-  return status;  
-}
-
-/**
-  * @brief Handle FLASH interrupt request.
-  * @retval None
-  */
-void HAL_FLASH_IRQHandler(void)
-{
-  uint32_t tmp_page;
-
-  /* If the operation is completed, disable the PG, PNB, MER1, MER2 and PER Bit */
-  CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_MER1 | FLASH_CR_PER | FLASH_CR_PNB));
-  CLEAR_BIT(FLASH->CR, FLASH_CR_MER2);
-  
-  /* Disable the FSTPG Bit only if it is the last row programmed */
-  if(pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM_LAST)
-  {
-    CLEAR_BIT(FLASH->CR, FLASH_CR_FSTPG);
-  }
-
-  /* Check FLASH operation error flags */
-  if((__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR))  || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PROGERR)) || 
-     (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR))  || 
-     (__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR))  ||
-     (__HAL_FLASH_GET_FLAG(FLASH_FLAG_MISERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_FASTERR)) || 
-     (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR))  || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) ||
-     (__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD)))
-  {
-    /*Save the error code*/
-    FLASH_SetErrorCode();
-    
-    /* FLASH error interrupt user callback */
-    if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGE_ERASE)
-    {
-       HAL_FLASH_EndOfOperationCallback(pFlash.Page);
-    }
-    else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASS_ERASE)
-    {
-        HAL_FLASH_EndOfOperationCallback(pFlash.Bank);
-    }
-    else if((pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM) || 
-            (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM_LAST))
-    {
-       HAL_FLASH_OperationErrorCallback(pFlash.Address);
-    }
-
-    HAL_FLASH_OperationErrorCallback(pFlash.Address);
-
-    /*Stop the procedure ongoing*/
-    pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
-  }
-
-  /* Check FLASH End of Operation flag  */
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
-  {
-    /* Clear FLASH End of Operation pending bit */
-    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
-
-    if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGE_ERASE)
-    {
-      /* Nb of pages to erased can be decreased */
-      pFlash.NbPagesToErase--;
-
-      /* Check if there are still pages to erase*/
-      if(pFlash.NbPagesToErase != 0)
-      {
-        /* Indicate user which page has been erased*/
-        HAL_FLASH_EndOfOperationCallback(pFlash.Page);
-
-        /* Increment page number */
-        pFlash.Page++;
-        tmp_page = pFlash.Page;
-        FLASH_PageErase(tmp_page, pFlash.Bank);
-      }
-      else
-      {
-        /* No more pages to Erase */
-        /* Reset Address and stop Erase pages procedure */
-        pFlash.Page = 0xFFFFFFFF;
-        pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
-
-        /* Flush the caches to be sure of the data consistency */
-        FLASH_FlushCaches() ;
-        
-        /* FLASH EOP interrupt user callback */
-        HAL_FLASH_EndOfOperationCallback(pFlash.Page);
-      }
-    }
-    else
-    {
-      if(pFlash.ProcedureOnGoing == FLASH_PROC_MASS_ERASE)
-      {
-        /* MassErase ended. Return the selected bank */
-        /* Flush the caches to be sure of the data consistency */
-        FLASH_FlushCaches() ;
-
-        /* FLASH EOP interrupt user callback */
-        HAL_FLASH_EndOfOperationCallback(pFlash.Bank);
-      }
-      else if((pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM) || 
-              (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM_LAST))
-      {
-        /* Program ended. Return the selected address */
-        /* FLASH EOP interrupt user callback */
-        HAL_FLASH_EndOfOperationCallback(pFlash.Address);
-      }
-
-      /*Clear the procedure ongoing*/
-      pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
-    }
-  }
-
-  if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
-  {
-    /* Disable End of Operation and Error interrupts */
-    __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(&pFlash);
-  }
-}
-
-/**
-  * @brief  FLASH end of operation interrupt callback.
-  * @param  ReturnValue: The value saved in this parameter depends on the ongoing procedure
-  *                  Mass Erase: Bank number which has been requested to erase
-  *                  Page Erase: Page which has been erased 
-  *                    (if 0xFFFFFFFF, it means that all the selected pages have been erased)
-  *                  Program: Address which was selected for data program
-  * @retval None
-  */
-__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(ReturnValue);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  FLASH operation error interrupt callback.
-  * @param  ReturnValue: The value saved in this parameter depends on the ongoing procedure
-  *                 Mass Erase: Bank number which has been requested to erase
-  *                 Page Erase: Page number which returned an error
-  *                 Program: Address which was selected for data program
-  * @retval None
-  */
-__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(ReturnValue);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_FLASH_OperationErrorCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions 
- *  @brief   Management functions 
- *
-@verbatim   
- ===============================================================================
-                      ##### Peripheral Control functions #####
- ===============================================================================  
-    [..]
-    This subsection provides a set of functions allowing to control the FLASH 
-    memory operations.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Unlock the FLASH control register access.
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_Unlock(void)
-{
-  if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
-  {
-    /* Authorize the FLASH Registers access */
-    WRITE_REG(FLASH->KEYR, FLASH_KEY1);
-    WRITE_REG(FLASH->KEYR, FLASH_KEY2);
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Lock the FLASH control register access.
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_Lock(void)
-{
-  /* Set the LOCK Bit to lock the FLASH Registers access */
-  SET_BIT(FLASH->CR, FLASH_CR_LOCK);
-  
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Unlock the FLASH Option Bytes Registers access.
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
-{
-  if(READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != RESET)
-  {
-    /* Authorizes the Option Byte register programming */
-    WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
-    WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
-  }
-  else
-  {
-    return HAL_ERROR;
-  }  
-  
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Lock the FLASH Option Bytes Registers access.
-  * @retval HAL Status 
-  */
-HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
-{
-  /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
-  SET_BIT(FLASH->CR, FLASH_CR_OPTLOCK);
-  
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Launch the option byte loading.
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
-{
-  /* Set the bit to force the option byte reloading */
-  SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH); 
-
-  /* Wait for last operation to be completed */
-  return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE)); 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions 
- *  @brief   Peripheral Errors functions 
- *
-@verbatim   
- ===============================================================================
-                ##### Peripheral Errors functions #####
- ===============================================================================  
-    [..]
-    This subsection permits to get in run-time Errors of the FLASH peripheral.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Get the specific FLASH error flag.
-  * @retval FLASH_ErrorCode: The returned value can be:
-  *            @arg HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP)
-  *            @arg HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag 
-  *            @arg HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag  
-  *            @arg HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag
-  *            @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag
-  *            @arg HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag 
-  *            @arg HAL_FLASH_ERROR_NONE: No error set 
-  *            @arg HAL_FLASH_ERROR_OP: FLASH Operation error
-  *            @arg HAL_FLASH_ERROR_PROG: FLASH Programming error
-  *            @arg HAL_FLASH_ERROR_WRP: FLASH Write protection error
-  *            @arg HAL_FLASH_ERROR_PGA: FLASH Programming alignment error
-  *            @arg HAL_FLASH_ERROR_SIZ: FLASH Size error
-  *            @arg HAL_FLASH_ERROR_PGS: FLASH Programming sequence error
-  *            @arg HAL_FLASH_ERROR_MIS: FLASH Fast programming data miss error
-  *            @arg HAL_FLASH_ERROR_FAST: FLASH Fast programming error
-  *            @arg HAL_FLASH_ERROR_RD: FLASH PCROP read error
-  *            @arg HAL_FLASH_ERROR_OPTV: FLASH Option validity error
-  *            @arg HAL_FLASH_ERROR_ECCD: FLASH two ECC errors have been detected
-  */
-uint32_t HAL_FLASH_GetError(void)
-{ 
-   return pFlash.ErrorCode;
-}
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-
-/** @addtogroup FLASH_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Wait for a FLASH operation to complete.
-  * @param  Timeout: maximum flash operation timeout
-  * @retval HAL_StatusTypeDef HAL Status
-  */
-HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
-{
-  /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
-     Even if the FLASH operation fails, the BUSY flag will be reset and an error
-     flag will be set */
-    
-  uint32_t timeout = HAL_GetTick() + Timeout;
-     
-  while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) 
-  { 
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if(HAL_GetTick() >= timeout)
-      {
-        return HAL_TIMEOUT;
-      }
-    } 
-  }
-  
-  if((__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR))  || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PROGERR)) || 
-     (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR))  || 
-     (__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR))  ||
-     (__HAL_FLASH_GET_FLAG(FLASH_FLAG_MISERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_FASTERR)) || 
-     (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR))  || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) ||
-     (__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD)))
-  {
-    /*Save the error code*/
-    FLASH_SetErrorCode();
-    
-    return HAL_ERROR;
-  }
-
-  /* Check FLASH End of Operation flag  */
-  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
-  {
-    /* Clear FLASH End of Operation pending bit */
-    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
-  }
-  
-  /* If there is an error flag set */
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Set the specific FLASH error flag.
-  * @retval None
-  */
-static void FLASH_SetErrorCode(void)
-{  
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR))
-  {
-    pFlash.ErrorCode |= HAL_FLASH_ERROR_OP;
-  }
-
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PROGERR))
-  { 
-    pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG;
-  }
-
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
-  { 
-    pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
-  }
-
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR))
-  { 
-    pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;
-  }
-
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR))
-  { 
-    pFlash.ErrorCode |= HAL_FLASH_ERROR_SIZ;
-  }
-
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR))
-  { 
-    pFlash.ErrorCode |= HAL_FLASH_ERROR_PGS;
-  }
-
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_MISERR))
-  { 
-   pFlash.ErrorCode |= HAL_FLASH_ERROR_MIS;
-  }
-
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_FASTERR))
-  { 
-   pFlash.ErrorCode |= HAL_FLASH_ERROR_FAST;
-  }
-
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR))
-  { 
-   pFlash.ErrorCode |= HAL_FLASH_ERROR_RD;
-  }
-
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))
-  { 
-   pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
-  }
-
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD))
-  { 
-   pFlash.ErrorCode |= HAL_FLASH_ERROR_ECCD;
-  }
-
-  /* Clear error programming flags */
-  __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS);
-} 
-
-/**
-  * @brief  Program double-word (64-bit) at a specified address.
-  * @param  Address: specifies the address to be programmed.
-  * @param  Data: specifies the data to be programmed.
-  * @retval None
-  */
-static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
-{
-  /* Check the parameters */
-  assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
-
-  /* Set PG bit */
-  SET_BIT(FLASH->CR, FLASH_CR_PG);
-  
-  /* Program the double word */
-  *(__IO uint32_t*)Address = (uint32_t)Data;
-  *(__IO uint32_t*)(Address+4) = (uint32_t)(Data >> 32);
-}
-
-/**
-  * @brief  Fast program a 32 row double-word (64-bit) at a specified address.
-  * @param  Address: specifies the address to be programmed.
-  * @param  DataAddress: specifies the address where the data are stored.
-  * @retval None
-  */
-static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress)
-{
-  uint8_t row_index = 32;
-  __IO uint64_t *dest_addr = (__IO uint64_t*)Address;
-  __IO uint64_t *src_addr = (__IO uint64_t*)DataAddress;
-
-  /* Check the parameters */
-  assert_param(IS_FLASH_MAIN_MEM_ADDRESS(Address));
-
-  /* Set FSTPG bit */
-  SET_BIT(FLASH->CR, FLASH_CR_FSTPG);
-  
-  /* Disable interrupts to avoid any interruption during the loop */
-  __disable_irq();
-  
-  /* Program the 32 double word */
-  do
-  {
-    *dest_addr++ = *src_addr++;
-  } while (--row_index != 0);
-
-  /* Re-enable the interrupts */
-  __enable_irq();
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/src/stm32l4xx_hal_flash_ex.c b/stmhal/hal/l4/src/stm32l4xx_hal_flash_ex.c
deleted file mode 100644
index b9c5215bda..0000000000
--- a/stmhal/hal/l4/src/stm32l4xx_hal_flash_ex.c
+++ /dev/null
@@ -1,980 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_flash_ex.c
-  * @author  MCD Application Team
-  * @version V1.3.0 
-  * @date    29-January-2016
-  * @brief   Extended FLASH HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the FLASH extended peripheral:
-  *           + Extended programming operations functions
-  *  
- @verbatim    
- ==============================================================================
-                   ##### Flash Extended features #####
-  ==============================================================================
-           
-  [..] Comparing to other previous devices, the FLASH interface for STM32L4xx 
-       devices contains the following additional features 
-       
-       (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
-           capability (RWW)
-       (+) Dual bank memory organization       
-       (+) PCROP protection for all banks
-   
-                        ##### How to use this driver #####
- ==============================================================================
-  [..] This driver provides functions to configure and program the FLASH memory 
-       of all STM32L4xx devices. It includes
-      (#) Flash Memory Erase functions: 
-           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and 
-                HAL_FLASH_Lock() functions
-           (++) Erase function: Erase page, erase all sectors
-           (++) There are two modes of erase :
-             (+++) Polling Mode using HAL_FLASHEx_Erase()
-             (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
-                         
-      (#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to :
-        (++) Set/Reset the write protection
-        (++) Set the Read protection Level
-        (++) Program the user Option Bytes
-        (++) Configure the PCROP protection
-        
-      (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to :
-        (++) Get the value of a write protection area
-        (++) Know if the read protection is activated
-        (++) Get the value of the user Option Bytes
-        (++) Get the value of a PCROP area
-    
- @endverbatim                      
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup FLASHEx FLASHEx
-  * @brief FALSH Extended HAL module driver
-  * @{
-  */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/ 
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup FLASHEx_Private_Variables FLASHEx Private Variables
- * @{
- */
-extern FLASH_ProcessTypeDef pFlash;
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
- * @{
- */
-extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
-void                     FLASH_PageErase(uint32_t Page, uint32_t Banks);
-static void              FLASH_MassErase(uint32_t Banks);
-void                     FLASH_FlushCaches(void);
-static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset);
-static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel);
-static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig);
-static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr);
-static void              FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t * WRPStartOffset, uint32_t * WRDPEndOffset);
-static uint32_t          FLASH_OB_GetRDP(void);
-static uint32_t          FLASH_OB_GetUser(void);
-static void              FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, uint32_t * PCROPEndAddr);
-/**
-  * @}
-  */
-
-/* Exported functions -------------------------------------------------------*/
-/** @defgroup FLASHEx_Exported_Functions FLASH Extended Exported Functions
-  * @{
-  */ 
-
-/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
- *  @brief   Extended IO operation functions 
- *
-@verbatim   
- ===============================================================================
-                ##### Extended programming operation functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to manage the Extended FLASH 
-    programming operations Operations.
- 
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Perform a mass erase or erase the specified FLASH memory pages.
-  * @param[in]  pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
-  *         contains the configuration information for the erasing.
-  * 
-  * @param[out]  PageError  : pointer to variable that contains the configuration 
-  *         information on faulty page in case of error (0xFFFFFFFF means that all 
-  *         the pages have been correctly erased)
-  * 
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
-{
-  HAL_StatusTypeDef status = HAL_ERROR;
-  uint32_t page_index = 0;
-
-  /* Process Locked */
-  __HAL_LOCK(&pFlash);
-
-  /* Check the parameters */
-  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-  if (status == HAL_OK)
-  {
-    pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
-    if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
-    {
-      /* Mass erase to be done */
-      FLASH_MassErase(pEraseInit->Banks);
-
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-      /* If the erase operation is completed, disable the MER1 and MER2 Bits */
-      CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2));
-    }
-    else
-    {
-      /*Initialization of PageError variable*/
-      *PageError = 0xFFFFFFFF;
-      
-      for(page_index = pEraseInit->Page; page_index < (pEraseInit->Page + pEraseInit->NbPages); page_index++)
-      {
-        FLASH_PageErase(page_index, pEraseInit->Banks);
-
-        /* Wait for last operation to be completed */
-        status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-        /* If the erase operation is completed, disable the PER Bit */
-        CLEAR_BIT(FLASH->CR, (FLASH_CR_PER | FLASH_CR_PNB));
-
-        if (status != HAL_OK)
-        {
-          /* In case of error, stop erase procedure and return the faulty address */
-          *PageError = page_index;
-          break;
-        }
-      }
-    }
-    
-    /* Flush the caches to be sure of the data consistency */
-    FLASH_FlushCaches();
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(&pFlash);
-
-  return status;
-}
-
-/**
-  * @brief  Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.
-  * @param  pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
-  *         contains the configuration information for the erasing.
-  * 
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process Locked */
-  __HAL_LOCK(&pFlash);
-
-  /* Check the parameters */
-  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
-
-  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
-  /* Enable End of Operation and Error interrupts */
-  __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
-
-  pFlash.Bank = pEraseInit->Banks;
-
-  if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
-  {
-    /* Mass erase to be done */
-    pFlash.ProcedureOnGoing = FLASH_PROC_MASS_ERASE;
-    FLASH_MassErase(pEraseInit->Banks);
-  }
-  else
-  {
-    /* Erase by page to be done */
-    pFlash.ProcedureOnGoing = FLASH_PROC_PAGE_ERASE;
-    pFlash.NbPagesToErase = pEraseInit->NbPages;
-    pFlash.Page = pEraseInit->Page;
-
-    /*Erase 1st page and wait for IT */
-    FLASH_PageErase(pEraseInit->Page, pEraseInit->Banks);
-  }
-  
-  return status;
-}
-
-/**
-  * @brief  Program Option bytes.
-  * @param  pOBInit: pointer to an FLASH_OBInitStruct structure that
-  *         contains the configuration information for the programming.
-  * 
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
-{
-  HAL_StatusTypeDef status = HAL_ERROR;
-  
-  /* Process Locked */
-  __HAL_LOCK(&pFlash);
-
-  /* Check the parameters */
-  assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
-  
-  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
-  /* Write protection configuration */
-  if((pOBInit->OptionType & OPTIONBYTE_WRP) != RESET)
-  {
-    /* Configure of Write protection on the selected area */
-    status = FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset);
-  }
-  
-  /* Read protection configuration */
-  if((pOBInit->OptionType & OPTIONBYTE_RDP) != RESET)
-  {
-    /* Configure the Read protection level */
-    status = FLASH_OB_RDPConfig(pOBInit->RDPLevel);
-  }
-  
-  /* User Configuration */
-  if((pOBInit->OptionType & OPTIONBYTE_USER) != RESET)
-  {
-    /* Configure the user option bytes */
-    status = FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig);
-  }
-  
-  /* PCROP Configuration */
-  if((pOBInit->OptionType & OPTIONBYTE_PCROP) != RESET)
-  {
-    /* Configure the Proprietary code readout protection */
-    status = FLASH_OB_PCROPConfig(pOBInit->PCROPConfig, pOBInit->PCROPStartAddr, pOBInit->PCROPEndAddr);
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(&pFlash);
-
-  return status;
-}
-
-/**
-  * @brief  Get the Option bytes configuration.
-  * @param  pOBInit: pointer to an FLASH_OBInitStruct structure that contains the 
-  *                  configuration information. The fields pOBInit->WRPArea and 
-  *                  pOBInit->PCROPConfig should indicate which area is requested
-  *                  for the WRP and PCROP 
-  * 
-  * @retval None
-  */
-void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
-{
-  pOBInit->OptionType = (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP);
-
-  /* Get write protection on the selected area */
-  FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset), &(pOBInit->WRPEndOffset));
-  
-  /* Get Read protection level */
-  pOBInit->RDPLevel = FLASH_OB_GetRDP();
-  
-  /* Get the user option bytes */
-  pOBInit->USERConfig = FLASH_OB_GetUser();
-  
-  /* Get the Proprietary code readout protection */
-  FLASH_OB_GetPCROP(&(pOBInit->PCROPConfig), &(pOBInit->PCROPStartAddr), &(pOBInit->PCROPEndAddr));
-  
-}
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/* Private functions ---------------------------------------------------------*/
-
-/** @addtogroup FLASHEx_Private_Functions
-  * @{
-  */
-/**
-  * @brief  Mass erase of FLASH memory.
-  * @param  Banks: Banks to be erased
-  *          This parameter can be one of the following values:
-  *            @arg FLASH_BANK_1: Bank1 to be erased
-  *            @arg FLASH_BANK_2: Bank2 to be erased
-  *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
-  * @retval None
-  */
-static void FLASH_MassErase(uint32_t Banks)
-{
-  /* Check the parameters */
-  assert_param(IS_FLASH_BANK(Banks));
-
-  /* Set the Mass Erase Bit for the bank 1 if requested */
-  if((Banks & FLASH_BANK_1) != RESET)
-  {
-    SET_BIT(FLASH->CR, FLASH_CR_MER1);
-  }
-  
-  /* Set the Mass Erase Bit for the bank 2 if requested */
-  if((Banks & FLASH_BANK_2) != RESET)
-  {
-    SET_BIT(FLASH->CR, FLASH_CR_MER2);
-  }
-
-  /* Proceed to erase all sectors */
-  SET_BIT(FLASH->CR, FLASH_CR_STRT);
-}
-
-/**
-  * @brief  Erase the specified FLASH memory page.
-  * @param  Page: FLASH page to erase
-  *         This parameter must be a value between 0 and (max number of pages in the bank - 1)      
-  * @param  Banks: Bank(s) where the page will be erased
-  *          This parameter can be one or a combination of the following values:
-  *            @arg FLASH_BANK_1: Page in bank 1 to be erased
-  *            @arg FLASH_BANK_2: Page in bank 2 to be erased
-  * @retval None
-  */
-void FLASH_PageErase(uint32_t Page, uint32_t Banks)
-{
-  /* Check the parameters */
-  assert_param(IS_FLASH_PAGE(Page));
-  assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks));
-
-  if((Banks & FLASH_BANK_1) != RESET)
-  {
-    CLEAR_BIT(FLASH->CR, FLASH_CR_BKER);
-  }
-  else
-  {
-    SET_BIT(FLASH->CR, FLASH_CR_BKER);
-  }
-
-  /* Proceed to erase the page */
-  MODIFY_REG(FLASH->CR, FLASH_CR_PNB, (Page << 3));
-  SET_BIT(FLASH->CR, FLASH_CR_PER);
-  SET_BIT(FLASH->CR, FLASH_CR_STRT);
-}
-
-/**
-  * @brief  Flush the instruction and data caches.
-  * @retval None
-  */
-void FLASH_FlushCaches(void)
-{
-  /* Flush instruction cache  */
-  if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != RESET)
-  {
-    /* Disable instruction cache  */
-    __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
-    /* Reset instruction cache */
-    __HAL_FLASH_INSTRUCTION_CACHE_RESET();
-    /* Enable instruction cache */
-    __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
-  }
-  
-  /* Flush data cache */
-  if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET)
-  {
-    /* Disable data cache  */
-    __HAL_FLASH_DATA_CACHE_DISABLE();
-    /* Reset data cache */
-    __HAL_FLASH_DATA_CACHE_RESET();
-    /* Enable data cache */
-    __HAL_FLASH_DATA_CACHE_ENABLE();
-  }
-}
-
-/**
-  * @brief  Configure the write protection of the desired pages.
-  *
-  * @note   When the memory read protection level is selected (RDP level = 1), 
-  *         it is not possible to program or erase Flash memory if the CPU debug 
-  *         features are connected (JTAG or single wire) or boot code is being 
-  *         executed from RAM or System flash, even if WRP is not activated. 
-  * @note   To configure the WRP options, the option lock bit OPTLOCK must be 
-  *         cleared with the call of the HAL_FLASH_OB_Unlock() function.
-  * @note   To validate the WRP options, the option bytes must be reloaded 
-  *         through the call of the HAL_FLASH_OB_Launch() function.
-  *
-  * @param  WRPArea: specifies the area to be configured.
-  *          This parameter can be one of the following values:
-  *            @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A                      
-  *            @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B                      
-  *            @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A                      
-  *            @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B                      
-  *
-  * @param  WRPStartOffset: specifies the start page of the write protected area
-  *          This parameter can be page number between 0 and (max number of pages in the bank - 1) 
-  *
-  * @param  WRDPEndOffset: specifies the end page of the write protected area
-  *          This parameter can be page number between WRPStartOffset and (max number of pages in the bank - 1) 
-  *
-  * @retval HAL Status
-  */
-static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_OB_WRPAREA(WRPArea));
-  assert_param(IS_FLASH_PAGE(WRPStartOffset));
-  assert_param(IS_FLASH_PAGE(WRDPEndOffset));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-  if(status == HAL_OK)
-  {
-    /* Configure the write protected area */
-    if(WRPArea == OB_WRPAREA_BANK1_AREAA)
-    {
-      MODIFY_REG(FLASH->WRP1AR, (FLASH_WRP1AR_WRP1A_STRT | FLASH_WRP1AR_WRP1A_END), 
-                 (WRPStartOffset | (WRDPEndOffset << 16)));
-    }
-    else if(WRPArea == OB_WRPAREA_BANK1_AREAB)
-    {
-      MODIFY_REG(FLASH->WRP1BR, (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END), 
-                 (WRPStartOffset | (WRDPEndOffset << 16)));
-    }
-    else if(WRPArea == OB_WRPAREA_BANK2_AREAA)
-    {
-      MODIFY_REG(FLASH->WRP2AR, (FLASH_WRP2AR_WRP2A_STRT | FLASH_WRP2AR_WRP2A_END), 
-                 (WRPStartOffset | (WRDPEndOffset << 16)));
-    }
-    else if(WRPArea == OB_WRPAREA_BANK2_AREAB)
-    {
-      MODIFY_REG(FLASH->WRP2BR, (FLASH_WRP2BR_WRP2B_STRT | FLASH_WRP2BR_WRP2B_END), 
-                 (WRPStartOffset | (WRDPEndOffset << 16)));
-    }
-    
-    /* Set OPTSTRT Bit */
-    SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
-    
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-    /* If the option byte program operation is completed, disable the OPTSTRT Bit */
-    CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
-  }
-  
-  return status;
-}
-
-/**
-  * @brief  Set the read protection level.
-  *    
-  * @note   To configure the RDP level, the option lock bit OPTLOCK must be 
-  *         cleared with the call of the HAL_FLASH_OB_Unlock() function.
-  * @note   To validate the RDP level, the option bytes must be reloaded 
-  *         through the call of the HAL_FLASH_OB_Launch() function.
-  * @note   !!! Warning : When enabling OB_RDP level 2 it's no more possible 
-  *         to go back to level 1 or 0 !!!
-  *    
-  * @param  RDPLevel: specifies the read protection level.
-  *         This parameter can be one of the following values:
-  *            @arg OB_RDP_LEVEL_0: No protection
-  *            @arg OB_RDP_LEVEL_1: Read protection of the memory
-  *            @arg OB_RDP_LEVEL_2: Full chip protection
-  *   
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_OB_RDP_LEVEL(RDPLevel));
-    
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-  if(status == HAL_OK)
-  { 
-    /* Configure the RDP level in the option bytes register */
-    MODIFY_REG(FLASH->OPTR, FLASH_OPTR_RDP, RDPLevel);
-    
-    /* Set OPTSTRT Bit */
-    SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
-    
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-    /* If the option byte program operation is completed, disable the OPTSTRT Bit */
-    CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
-  }
-
-  return status;            
-}
-
-/**
-  * @brief  Program the FLASH User Option Byte.    
-  *   
-  * @note   To configure the user option bytes, the option lock bit OPTLOCK must
-  *         be cleared with the call of the HAL_FLASH_OB_Unlock() function.
-  * @note   To validate the user option bytes, the option bytes must be reloaded 
-  *         through the call of the HAL_FLASH_OB_Launch() function.
-  *   
-  * @param  UserType: The FLASH User Option Bytes to be modified 
-  * @param  UserConfig: The FLASH User Option Bytes values: 
-  *         BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), IWDG_SW(Bit16),
-  *         IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19), BFB2(Bit20), 
-  *         DUALBANK(Bit21), nBOOT1(Bit23), SRAM2_PE(Bit24) and SRAM2_RST(Bit25). 
-  *   
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig)
-{
-  uint32_t optr_reg_val = 0;
-  uint32_t optr_reg_mask = 0;
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_OB_USER_TYPE(UserType));
-  
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-  if(status == HAL_OK)
-  { 
-    if((UserType & OB_USER_BOR_LEV) != RESET)
-    {
-      /* BOR level option byte should be modified */
-      assert_param(IS_OB_USER_BOR_LEVEL(UserConfig & FLASH_OPTR_BOR_LEV));
-    
-      /* Set value and mask for BOR level option byte */
-      optr_reg_val |= (UserConfig & FLASH_OPTR_BOR_LEV);
-      optr_reg_mask |= FLASH_OPTR_BOR_LEV;
-    }
-
-    if((UserType & OB_USER_nRST_STOP) != RESET)
-    {
-      /* nRST_STOP option byte should be modified */
-      assert_param(IS_OB_USER_STOP(UserConfig & FLASH_OPTR_nRST_STOP));
-    
-      /* Set value and mask for nRST_STOP option byte */
-      optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STOP);
-      optr_reg_mask |= FLASH_OPTR_nRST_STOP;
-    }
-
-    if((UserType & OB_USER_nRST_STDBY) != RESET)
-    {
-      /* nRST_STDBY option byte should be modified */
-      assert_param(IS_OB_USER_STANDBY(UserConfig & FLASH_OPTR_nRST_STDBY));
-    
-      /* Set value and mask for nRST_STDBY option byte */
-      optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STDBY);
-      optr_reg_mask |= FLASH_OPTR_nRST_STDBY;
-    }
-
-    if((UserType & OB_USER_nRST_SHDW) != RESET)
-    {
-      /* nRST_SHDW option byte should be modified */
-      assert_param(IS_OB_USER_SHUTDOWN(UserConfig & FLASH_OPTR_nRST_SHDW));
-    
-      /* Set value and mask for nRST_SHDW option byte */
-      optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_SHDW);
-      optr_reg_mask |= FLASH_OPTR_nRST_SHDW;
-    }
-
-    if((UserType & OB_USER_IWDG_SW) != RESET)
-    {
-      /* IWDG_SW option byte should be modified */
-      assert_param(IS_OB_USER_IWDG(UserConfig & FLASH_OPTR_IWDG_SW));
-    
-      /* Set value and mask for IWDG_SW option byte */
-      optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_SW);
-      optr_reg_mask |= FLASH_OPTR_IWDG_SW;
-    }
-
-    if((UserType & OB_USER_IWDG_STOP) != RESET)
-    {
-      /* IWDG_STOP option byte should be modified */
-      assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTR_IWDG_STOP));
-    
-      /* Set value and mask for IWDG_STOP option byte */
-      optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STOP);
-      optr_reg_mask |= FLASH_OPTR_IWDG_STOP;
-    }
-
-    if((UserType & OB_USER_IWDG_STDBY) != RESET)
-    {
-      /* IWDG_STDBY option byte should be modified */
-      assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTR_IWDG_STDBY));
-    
-      /* Set value and mask for IWDG_STDBY option byte */
-      optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STDBY);
-      optr_reg_mask |= FLASH_OPTR_IWDG_STDBY;
-    }
-
-    if((UserType & OB_USER_WWDG_SW) != RESET)
-    {
-      /* WWDG_SW option byte should be modified */
-      assert_param(IS_OB_USER_WWDG(UserConfig & FLASH_OPTR_WWDG_SW));
-    
-      /* Set value and mask for WWDG_SW option byte */
-      optr_reg_val |= (UserConfig & FLASH_OPTR_WWDG_SW);
-      optr_reg_mask |= FLASH_OPTR_WWDG_SW;
-    }
-
-    if((UserType & OB_USER_BFB2) != RESET)
-    {
-      /* BFB2 option byte should be modified */
-      assert_param(IS_OB_USER_BFB2(UserConfig & FLASH_OPTR_BFB2));
-    
-      /* Set value and mask for BFB2 option byte */
-      optr_reg_val |= (UserConfig & FLASH_OPTR_BFB2);
-      optr_reg_mask |= FLASH_OPTR_BFB2;
-    }
-
-    if((UserType & OB_USER_DUALBANK) != RESET)
-    {
-      /* DUALBANK option byte should be modified */
-      assert_param(IS_OB_USER_DUALBANK(UserConfig & FLASH_OPTR_DUALBANK));
-    
-      /* Set value and mask for DUALBANK option byte */
-      optr_reg_val |= (UserConfig & FLASH_OPTR_DUALBANK);
-      optr_reg_mask |= FLASH_OPTR_DUALBANK;
-    }
-
-    if((UserType & OB_USER_nBOOT1) != RESET)
-    {
-      /* nBOOT1 option byte should be modified */
-      assert_param(IS_OB_USER_BOOT1(UserConfig & FLASH_OPTR_nBOOT1));
-    
-      /* Set value and mask for nBOOT1 option byte */
-      optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT1);
-      optr_reg_mask |= FLASH_OPTR_nBOOT1;
-    }
-
-    if((UserType & OB_USER_SRAM2_PE) != RESET)
-    {
-      /* SRAM2_PE option byte should be modified */
-      assert_param(IS_OB_USER_SRAM2_PARITY(UserConfig & FLASH_OPTR_SRAM2_PE));
-    
-      /* Set value and mask for SRAM2_PE option byte */
-      optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_PE);
-      optr_reg_mask |= FLASH_OPTR_SRAM2_PE;
-    }
-
-    if((UserType & OB_USER_SRAM2_RST) != RESET)
-    {
-      /* SRAM2_RST option byte should be modified */
-      assert_param(IS_OB_USER_SRAM2_RST(UserConfig & FLASH_OPTR_SRAM2_RST));
-    
-      /* Set value and mask for SRAM2_RST option byte */
-      optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_RST);
-      optr_reg_mask |= FLASH_OPTR_SRAM2_RST;
-    }
-
-    /* Configure the option bytes register */
-    MODIFY_REG(FLASH->OPTR, optr_reg_mask, optr_reg_val);
-    
-    /* Set OPTSTRT Bit */
-    SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
-    
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-    /* If the option byte program operation is completed, disable the OPTSTRT Bit */
-    CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
-  }
-
-  return status;            
-}
-
-/**
-  * @brief  Configure the Proprietary code readout protection of the desired addresses.
-  *
-  * @note   To configure the PCROP options, the option lock bit OPTLOCK must be 
-  *         cleared with the call of the HAL_FLASH_OB_Unlock() function.
-  * @note   To validate the PCROP options, the option bytes must be reloaded 
-  *         through the call of the HAL_FLASH_OB_Launch() function.
-  *
-  * @param  PCROPConfig: specifies the configuration (Bank to be configured and PCROP_RDP option).
-  *          This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2 
-  *          with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE
-  *
-  * @param  PCROPStartAddr: specifies the start address of the Proprietary code readout protection
-  *          This parameter can be an address between begin and end of the bank 
-  *
-  * @param  PCROPEndAddr: specifies the end address of the Proprietary code readout protection
-  *          This parameter can be an address between PCROPStartAddr and end of the bank 
-  *
-  * @retval HAL Status
-  */
-static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  uint32_t reg_value = 0;
-  uint32_t bank1_addr, bank2_addr;
-
-  /* Check the parameters */
-  assert_param(IS_FLASH_BANK_EXCLUSIVE(PCROPConfig & FLASH_BANK_BOTH));
-  assert_param(IS_OB_PCROP_RDP(PCROPConfig & FLASH_PCROP1ER_PCROP_RDP));
-  assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPStartAddr));
-  assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPEndAddr));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-  if(status == HAL_OK)
-  {
-    /* Get the information about the bank swapping */
-    if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0)
-    {
-      bank1_addr = FLASH_BASE;
-      bank2_addr = FLASH_BASE + FLASH_BANK_SIZE;
-    }
-    else
-    {
-      bank1_addr = FLASH_BASE + FLASH_BANK_SIZE;
-      bank2_addr = FLASH_BASE;
-    }
-  
-    /* Configure the Proprietary code readout protection */
-    if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1)
-    {
-      reg_value = ((PCROPStartAddr - bank1_addr) >> 3);
-      MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value);
-
-      reg_value = ((PCROPEndAddr - bank1_addr) >> 3);
-      MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value);
-    }
-    else if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_2)
-    {
-      reg_value = ((PCROPStartAddr - bank2_addr) >> 3);
-      MODIFY_REG(FLASH->PCROP2SR, FLASH_PCROP2SR_PCROP2_STRT, reg_value);
-
-      reg_value = ((PCROPEndAddr - bank2_addr) >> 3);
-      MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value);
-    }
-
-    MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP_RDP, (PCROPConfig & FLASH_PCROP1ER_PCROP_RDP));
-    
-    /* Set OPTSTRT Bit */
-    SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
-    
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-    /* If the option byte program operation is completed, disable the OPTSTRT Bit */
-    CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
-  }
-  
-  return status;
-}
-
-/**
-  * @brief  Return the FLASH Write Protection Option Bytes value.
-  *
-  * @param[in]  WRPArea: specifies the area to be returned.
-  *          This parameter can be one of the following values:
-  *            @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A                      
-  *            @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B                      
-  *            @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A                      
-  *            @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B                      
-  *
-  * @param[out]  WRPStartOffset: specifies the address where to copied the start page 
-  *                         of the write protected area
-  *
-  * @param[out]  WRDPEndOffset: specifies the address where to copied the end page of 
-  *                        the write protected area
-  *
-  * @retval None
-  */
-static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t * WRPStartOffset, uint32_t * WRDPEndOffset)
-{
-  /* Check the parameters */
-  assert_param(IS_OB_WRPAREA(WRPArea));
-
-  /* Get the configuration of the write protected area */
-  if(WRPArea == OB_WRPAREA_BANK1_AREAA)
-  {
-    *WRPStartOffset = READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_STRT);
-    *WRDPEndOffset = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_END) >> 16);
-  }
-  else if(WRPArea == OB_WRPAREA_BANK1_AREAB)
-  {
-    *WRPStartOffset = READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_STRT);
-    *WRDPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_END) >> 16);
-  }
-  else if(WRPArea == OB_WRPAREA_BANK2_AREAA)
-  {
-    *WRPStartOffset = READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_STRT);
-    *WRDPEndOffset = (READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_END) >> 16);
-  }
-  else if(WRPArea == OB_WRPAREA_BANK2_AREAB)
-  {
-    *WRPStartOffset = READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_STRT);
-    *WRDPEndOffset = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_END) >> 16);
-  }
-}
-
-/**
-  * @brief  Return the FLASH Read Protection level.
-  * @retval FLASH ReadOut Protection Status:
-  *         This return value can be one of the following values:
-  *            @arg OB_RDP_LEVEL_0: No protection
-  *            @arg OB_RDP_LEVEL_1: Read protection of the memory
-  *            @arg OB_RDP_LEVEL_2: Full chip protection
-  */
-static uint32_t FLASH_OB_GetRDP(void)
-{
-  if ((READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP) != OB_RDP_LEVEL_0) && 
-      (READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP) != OB_RDP_LEVEL_2))
-  {
-    return (OB_RDP_LEVEL_1);
-  }
-  else
-  {
-    return (READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP));
-  }
-}
-
-/**
-  * @brief  Return the FLASH User Option Byte value.
-  * @retval The FLASH User Option Bytes values: 
-  *         BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), nRST_SHDW(Bit14), 
-  *         IWDG_SW(Bit16), IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19),  
-  *         BFB2(Bit20), DUALBANK(Bit21), nBOOT1(Bit23), SRAM2_PE(Bit24) and SRAM2_RST(Bit25). 
-  */
-static uint32_t FLASH_OB_GetUser(void)
-{
-  uint32_t user_config = READ_REG(FLASH->OPTR);
-  CLEAR_BIT(user_config, FLASH_OPTR_RDP);
-  
-  return user_config;
-}
-
-/**
-  * @brief  Return the FLASH Write Protection Option Bytes value.
-  *
-  * @param PCROPConfig [inout]: specifies the configuration (Bank to be configured and PCROP_RDP option).
-  *          This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2 
-  *          with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE
-  *
-  * @param PCROPStartAddr [out]: specifies the address where to copied the start address 
-  *                         of the Proprietary code readout protection
-  *
-  * @param PCROPEndAddr [out]: specifies the address where to copied the end address of 
-  *                       the Proprietary code readout protection
-  *
-  * @retval None
-  */
-static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, uint32_t * PCROPEndAddr)
-{
-  uint32_t reg_value = 0;
-  uint32_t bank1_addr, bank2_addr;
-  
-  /* Check the parameters */
-  assert_param(IS_FLASH_BANK_EXCLUSIVE((*PCROPConfig) & FLASH_BANK_BOTH));
-
-  /* Get the information about the bank swapping */
-  if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0)
-  {
-    bank1_addr = FLASH_BASE;
-    bank2_addr = FLASH_BASE + FLASH_BANK_SIZE;
-  }
-  else
-  {
-    bank1_addr = FLASH_BASE + FLASH_BANK_SIZE;
-    bank2_addr = FLASH_BASE;
-  }
-
-  if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1)
-  {
-    reg_value       = (READ_REG(FLASH->PCROP1SR) & FLASH_PCROP1SR_PCROP1_STRT);
-    *PCROPStartAddr = (reg_value << 3) + bank1_addr;
-    
-    reg_value     = (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP1_END);
-    *PCROPEndAddr = (reg_value << 3) + bank1_addr;
-  }
-  else if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2)
-  {
-    reg_value       = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT);
-    *PCROPStartAddr = (reg_value << 3) + bank2_addr;
-
-    reg_value     = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END);
-    *PCROPEndAddr = (reg_value << 3) + bank2_addr;
-  }
-
-  *PCROPConfig |= (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP_RDP);
-}
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/src/stm32l4xx_hal_flash_ramfunc.c b/stmhal/hal/l4/src/stm32l4xx_hal_flash_ramfunc.c
deleted file mode 100644
index 1e08b9ccf1..0000000000
--- a/stmhal/hal/l4/src/stm32l4xx_hal_flash_ramfunc.c
+++ /dev/null
@@ -1,155 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_flash_ramfunc.c
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   FLASH RAMFUNC driver.
-  *          This file provides a Flash firmware functions which should be 
-  *          executed from internal SRAM
-  *            + FLASH HalfPage Programming
-  *            + FLASH Power Down in Run mode
-  *
-  *  @verbatim
-  ==============================================================================
-                   ##### Flash RAM functions #####
-  ==============================================================================    
-
-    *** ARM Compiler ***
-    --------------------
-    [..] RAM functions are defined using the toolchain options. 
-         Functions that are executed in RAM should reside in a separate
-         source module. Using the 'Options for File' dialog you can simply change
-         the 'Code / Const' area of a module to a memory space in physical RAM.
-         Available memory areas are declared in the 'Target' tab of the 
-         Options for Target' dialog.
-
-    *** ICCARM Compiler ***
-    -----------------------
-    [..] RAM functions are defined using a specific toolchain keyword "__ramfunc".
-
-    *** GNU Compiler ***
-    --------------------
-    [..] RAM functions are defined using a specific toolchain attribute
-         "__attribute__((section(".RamFunc")))".
-  
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup FLASH_RAMFUNC FLASH_RAMFUNC
-  * @brief FLASH functions executed from RAM
-  * @{
-  */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions -------------------------------------------------------*/
-
-/** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH in RAM function Exported Functions
-  * @{
-  */
-
-/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions 
- *  @brief   Data transfers functions 
- *
-@verbatim   
- ===============================================================================
-                      ##### ramfunc functions #####
- ===============================================================================  
-    [..]
-    This subsection provides a set of functions that should be executed from RAM.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief   Enable the Power down in Run Mode
-  * @note    This function should be called and executed from SRAM memory
-  * @retval None
-  */
-__RAM_FUNC HAL_FLASHEx_EnableRunPowerDown(void)
-{
-  /* Enable the Power Down in Run mode*/
-  __HAL_FLASH_POWER_DOWN_ENABLE();
-  
-  return HAL_OK;
-  
-}
-
-/**
-  * @brief   Disable the Power down in Run Mode
-  * @note    This function should be called and executed from SRAM memory
-  * @retval None
-  */
-__RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void)
-{
-  /* Disable the Power Down in Run mode*/
-  __HAL_FLASH_POWER_DOWN_DISABLE();
-
-  return HAL_OK;  
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */   
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-
-  
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-     
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
-
diff --git a/stmhal/hal/l4/src/stm32l4xx_hal_gpio.c b/stmhal/hal/l4/src/stm32l4xx_hal_gpio.c
deleted file mode 100644
index 5c61d5fc25..0000000000
--- a/stmhal/hal/l4/src/stm32l4xx_hal_gpio.c
+++ /dev/null
@@ -1,562 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_gpio.c
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   GPIO HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *
-  @verbatim
-  ==============================================================================
-                    ##### GPIO Peripheral features #####
-  ==============================================================================
-  [..]
-    (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
-        configured by software in several modes:
-        (++) Input mode
-        (++) Analog mode
-        (++) Output mode
-        (++) Alternate function mode
-        (++) External interrupt/event lines
-
-    (+) During and just after reset, the alternate functions and external interrupt
-        lines are not active and the I/O ports are configured in input floating mode.
-
-    (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
-        activated or not.
-
-    (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
-        type and the IO speed can be selected depending on the VDD value.
-
-    (+) The microcontroller IO pins are connected to onboard peripherals/modules through a
-        multiplexer that allows only one peripheral alternate function (AF) connected
-       to an IO pin at a time. In this way, there can be no conflict between peripherals
-       sharing the same IO pin.
-
-    (+) All ports have external interrupt/event capability. To use external interrupt
-        lines, the port must be configured in input mode. All available GPIO pins are
-        connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
-
-    (+) The external interrupt/event controller consists of up to 39 edge detectors
-        (16 lines are connected to GPIO) for generating event/interrupt requests (each
-        input line can be independently configured to select the type (interrupt or event)
-        and the corresponding trigger event (rising or falling or both). Each line can
-        also be masked independently.
-
-                     ##### How to use this driver #####
-  ==============================================================================
-  [..]
-    (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
-
-    (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
-        (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
-        (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
-             structure.
-        (++) In case of Output or alternate function mode selection: the speed is
-             configured through "Speed" member from GPIO_InitTypeDef structure.
-        (++) In alternate mode is selection, the alternate function connected to the IO
-             is configured through "Alternate" member from GPIO_InitTypeDef structure.
-        (++) Analog mode is required when a pin is to be used as ADC channel
-             or DAC output.
-        (++) In case of external interrupt/event selection the "Mode" member from
-             GPIO_InitTypeDef structure select the type (interrupt or event) and
-             the corresponding trigger event (rising or falling or both).
-
-    (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
-        mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
-        HAL_NVIC_EnableIRQ().
-
-    (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
-
-    (#) To set/reset the level of a pin configured in output mode use
-        HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
-
-   (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
-  
-    (#) During and just after reset, the alternate functions are not
-        active and the GPIO pins are configured in input floating mode (except JTAG
-        pins).
-
-    (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
-        (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
-        priority over the GPIO function.
-
-    (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
-        general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
-        The HSE has priority over the GPIO function.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup GPIO GPIO
-  * @brief GPIO HAL module driver
-  * @{
-  */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup GPIO_Private_Defines GPIO Private Defines
-  * @{
-  */
-#define GPIO_MODE             ((uint32_t)0x00000003)
-#define ANALOG_MODE           ((uint32_t)0x00000008)
-#define EXTI_MODE             ((uint32_t)0x10000000)
-#define GPIO_MODE_IT          ((uint32_t)0x00010000)
-#define GPIO_MODE_EVT         ((uint32_t)0x00020000)
-#define RISING_EDGE           ((uint32_t)0x00100000)
-#define FALLING_EDGE          ((uint32_t)0x00200000)
-#define GPIO_OUTPUT_TYPE      ((uint32_t)0x00000010)
-
-#define GPIO_NUMBER           ((uint32_t)16)
-/**
-  * @}
-  */
-  
-/* Private macros ------------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup GPIO_Private_Macros GPIO Private Macros
-  * @{
-  */
-/**
-  * @}
-  */
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
-  * @{
-  */
-
-/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions 
- *  @brief    Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
-  * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family
-  * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
-  *         the configuration information for the specified GPIO peripheral.
-  * @retval None
-  */
-void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
-{
-  uint32_t position = 0x00;
-  uint32_t iocurrent = 0x00;
-  uint32_t temp = 0x00;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
-  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
-  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
-  assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
-
-  /* Configure the port pins */
-  while (((GPIO_Init->Pin) >> position) != RESET)
-  {
-    /* Get current io position */
-    iocurrent = (GPIO_Init->Pin) & (1U << position);
-
-    if(iocurrent)
-    {
-      /*--------------------- GPIO Mode Configuration ------------------------*/
-      /* In case of Alternate function mode selection */
-      if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
-      {
-        /* Check the Alternate function parameters */
-        assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
-        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
-        
-        /* Configure Alternate function mapped with the current IO */
-        temp = GPIOx->AFR[position >> 3];
-        temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
-        temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
-        GPIOx->AFR[position >> 3] = temp;
-      }
-
-      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
-      temp = GPIOx->MODER;
-      temp &= ~(GPIO_MODER_MODE0 << (position * 2));
-      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
-      GPIOx->MODER = temp;
-
-      /* In case of Output or Alternate function mode selection */
-      if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
-         (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
-      {
-        /* Check the Speed parameter */
-        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
-        /* Configure the IO Speed */
-        temp = GPIOx->OSPEEDR;
-        temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2));
-        temp |= (GPIO_Init->Speed << (position * 2));
-        GPIOx->OSPEEDR = temp;
-
-        /* Configure the IO Output Type */
-        temp = GPIOx->OTYPER;
-        temp &= ~(GPIO_OTYPER_OT0 << position) ;
-        temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
-        GPIOx->OTYPER = temp;
-      }
-
-      /* In case of Analog mode, check if ADC control mode is selected */
-      if((GPIO_Init->Mode & GPIO_MODE_ANALOG) == GPIO_MODE_ANALOG)
-      {
-        /* Configure the IO Output Type */
-        temp = GPIOx->ASCR;
-        temp &= ~(GPIO_ASCR_ASC0 << position) ;
-        temp |= (((GPIO_Init->Mode & ANALOG_MODE) >> 3) << position);
-        GPIOx->ASCR = temp;
-      }
-
-      /* Activate the Pull-up or Pull down resistor for the current IO */
-      temp = GPIOx->PUPDR;
-      temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2));
-      temp |= ((GPIO_Init->Pull) << (position * 2));
-      GPIOx->PUPDR = temp;
-
-      /*--------------------- EXTI Mode Configuration ------------------------*/
-      /* Configure the External Interrupt or event for the current IO */
-      if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
-      {
-        /* Enable SYSCFG Clock */
-        __HAL_RCC_SYSCFG_CLK_ENABLE();
-
-        temp = SYSCFG->EXTICR[position >> 2];
-        temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
-        temp |= (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03)));
-        SYSCFG->EXTICR[position >> 2] = temp;
-
-        /* Clear EXTI line configuration */
-        temp = EXTI->IMR1;
-        temp &= ~((uint32_t)iocurrent);
-        if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
-        {
-          temp |= iocurrent;
-        }
-        EXTI->IMR1 = temp;
-
-        temp = EXTI->EMR1;
-        temp &= ~((uint32_t)iocurrent);
-        if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
-        {
-          temp |= iocurrent;
-        }
-        EXTI->EMR1 = temp;
-
-        /* Clear Rising Falling edge configuration */
-        temp = EXTI->RTSR1;
-        temp &= ~((uint32_t)iocurrent);
-        if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
-        {
-          temp |= iocurrent;
-        }
-        EXTI->RTSR1 = temp;
-
-        temp = EXTI->FTSR1;
-        temp &= ~((uint32_t)iocurrent);
-        if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
-        {
-          temp |= iocurrent;
-        }
-        EXTI->FTSR1 = temp;
-      }
-    }
-    
-    position++;
-  }
-}
-
-/**
-  * @brief  De-initialize the GPIOx peripheral registers to their default reset values.
-  * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family
-  * @param  GPIO_Pin: specifies the port bit to be written.
-  *         This parameter can be one of GPIO_PIN_x where x can be (0..15).
-  * @retval None
-  */
-void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
-{
-  uint32_t position = 0x00;
-  uint32_t iocurrent = 0x00;
-  uint32_t tmp = 0x00;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-
-  /* Configure the port pins */
-  while ((GPIO_Pin >> position) != RESET)
-  {
-    /* Get current io position */
-    iocurrent = (GPIO_Pin) & (1U << position);
-
-    if (iocurrent)
-    {
-      /*------------------------- GPIO Mode Configuration --------------------*/
-      /* Configure IO in Analog Mode */
-      GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2));
-
-      /* Configure the default Alternate Function in current IO */
-      GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
-
-      /* Configure the default value for IO Speed */
-      GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2));
-
-      /* Configure the default value IO Output Type */
-      GPIOx->OTYPER  &= ~(GPIO_OTYPER_OT0 << position) ;
-
-      /* Deactivate the Pull-up and Pull-down resistor for the current IO */
-      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2));
-
-      /* Deactivate the Control bit of Analog mode for the current IO */
-      GPIOx->ASCR &= ~(GPIO_ASCR_ASC0<< position);
-
-      /*------------------------- EXTI Mode Configuration --------------------*/
-      /* Clear the External Interrupt or Event for the current IO */
-      
-      tmp = SYSCFG->EXTICR[position >> 2];
-      tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
-      if(tmp == (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03))))
-      {
-        tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
-        SYSCFG->EXTICR[position >> 2] &= ~tmp;
-
-        /* Clear EXTI line configuration */
-        EXTI->IMR1 &= ~((uint32_t)iocurrent);
-        EXTI->EMR1 &= ~((uint32_t)iocurrent);
-
-        /* Clear Rising Falling edge configuration */
-        EXTI->RTSR1 &= ~((uint32_t)iocurrent);
-        EXTI->FTSR1 &= ~((uint32_t)iocurrent);
-      }
-    }
-    
-    position++;
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions 
- *  @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
- *
-@verbatim
- ===============================================================================
-                       ##### IO operation functions #####
- ===============================================================================
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Read the specified input port pin.
-  * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family
-  * @param  GPIO_Pin: specifies the port bit to read.
-  *         This parameter can be GPIO_PIN_x where x can be (0..15).
-  * @retval The input port pin value.
-  */
-GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
-  GPIO_PinState bitstatus;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-
-  if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
-  {
-    bitstatus = GPIO_PIN_SET;
-  }
-  else
-  {
-    bitstatus = GPIO_PIN_RESET;
-  }
-  return bitstatus;
-}
-
-/**
-  * @brief  Set or clear the selected data port bit.
-  *
-  * @note   This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify
-  *         accesses. In this way, there is no risk of an IRQ occurring between
-  *         the read and the modify access.
-  *
-  * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family
-  * @param  GPIO_Pin: specifies the port bit to be written.
-  *         This parameter can be one of GPIO_PIN_x where x can be (0..15).
-  * @param  PinState: specifies the value to be written to the selected bit.
-  *         This parameter can be one of the GPIO_PinState enum values:
-  *            @arg GPIO_PIN_RESET: to clear the port pin
-  *            @arg GPIO_PIN_SET: to set the port pin
-  * @retval None
-  */
-void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
-{
-  /* Check the parameters */
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-  assert_param(IS_GPIO_PIN_ACTION(PinState));
-
-  if(PinState != GPIO_PIN_RESET)
-  {
-    GPIOx->BSRR = (uint32_t)GPIO_Pin;
-  }
-  else
-  {
-    GPIOx->BRR = (uint32_t)GPIO_Pin;
-  }
-}
-
-/**
-  * @brief  Toggle the specified GPIO pin.
-  * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family
-  * @param  GPIO_Pin: specifies the pin to be toggled.
-  * @retval None
-  */
-void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
-  /* Check the parameters */
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-
-  GPIOx->ODR ^= GPIO_Pin;
-}
-
-/**
-* @brief  Lock GPIO Pins configuration registers.
-  * @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
-  *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
-  * @note   The configuration of the locked GPIO pins can no longer be modified
-  *         until the next reset.
-  * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family
-  * @param  GPIO_Pin: specifies the port bits to be locked.
-  *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
-  __IO uint32_t tmp = GPIO_LCKR_LCKK;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-
-  /* Apply lock key write sequence */
-  tmp |= GPIO_Pin;
-  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
-  GPIOx->LCKR = tmp;
-  /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
-  GPIOx->LCKR = GPIO_Pin;
-  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
-  GPIOx->LCKR = tmp;
-  /* Read LCKK bit*/
-  tmp = GPIOx->LCKR;
-
-  if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
-  {
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Handle EXTI interrupt request.
-  * @param  GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
-  * @retval None
-  */
-void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
-{
-  /* EXTI line interrupt detected */
-  if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
-  {
-    __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
-    HAL_GPIO_EXTI_Callback(GPIO_Pin);
-  }
-}
-
-/**
-  * @brief  EXTI line detection callback.
-  * @param  GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
-  * @retval None
-  */
-__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(GPIO_Pin);
-
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_GPIO_EXTI_Callback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-#endif /* HAL_GPIO_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/src/stm32l4xx_hal_i2c.c b/stmhal/hal/l4/src/stm32l4xx_hal_i2c.c
deleted file mode 100644
index 7d683a4e54..0000000000
--- a/stmhal/hal/l4/src/stm32l4xx_hal_i2c.c
+++ /dev/null
@@ -1,5227 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_i2c.c
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   I2C HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Inter Integrated Circuit (I2C) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral State and Errors functions
-  *
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-    [..]
-    The I2C HAL driver can be used as follows:
-
-    (#) Declare a I2C_HandleTypeDef handle structure, for example:
-        I2C_HandleTypeDef  hi2c;
-
-    (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
-        (##) Enable the I2Cx interface clock
-        (##) I2C pins configuration
-            (+++) Enable the clock for the I2C GPIOs
-            (+++) Configure I2C pins as alternate function open-drain
-        (##) NVIC configuration if you need to use interrupt process
-            (+++) Configure the I2Cx interrupt priority
-            (+++) Enable the NVIC I2C IRQ Channel
-        (##) DMA Configuration if you need to use DMA process
-            (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
-            (+++) Enable the DMAx interface clock using
-            (+++) Configure the DMA handle parameters
-            (+++) Configure the DMA Tx or Rx channel
-            (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
-            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
-                  the DMA Tx or Rx channel
-
-    (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
-        Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
-
-    (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
-        (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
-
-    (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
-
-    (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
-
-    *** Polling mode IO operation ***
-    =================================
-    [..]
-      (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
-      (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
-      (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
-      (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
-
-    *** Polling mode IO MEM operation ***
-    =====================================
-    [..]
-      (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
-      (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
-
-
-    *** Interrupt mode IO operation ***
-    ===================================
-    [..]
-      (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
-      (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
-      (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
-      (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
-      (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
-      (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
-      (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
-      (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
-      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
-           add his own code by customization of function pointer HAL_I2C_ErrorCallback()
-      (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
-
-    *** Interrupt mode IO sequential operation ***
-    ===================================
-    [..]
-      (@) These interfaces allow to manage a sequential transfer with a repeated start condition
-          when a direction change during transfer
-    [..]
-      (+) A specific option field manage the different steps of a sequential transfer
-      (+) Option field values are defined through I2C_XferOptions_definition and are listed below:
-      (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
-      (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
-                            and data to transfer without a final stop condition
-      (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
-                            and with new data to transfer if the direction change or manage only the new data to transfer
-                            if no direction change and without a final stop condition in both cases
-      (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
-                            and with new data to transfer if the direction change or manage only the new data to transfer
-                            if no direction change and with a final stop condition in both cases
-
-      (+) Differents sequential I2C interfaces are listed below:
-      (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT()
-      (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
-      (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT()
-      (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
-      (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
-      (+++) The associated previous transfer callback is called at the end of abort process
-      (+++) mean HAL_I2C_MasterTxCpltCallback() in case of previous state was master transmit
-      (+++) mean HAL_I2c_MasterRxCpltCallback() in case of previous state was master receive
-      (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
-      (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
-           add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
-      (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
-      (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT()
-      (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
-      (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT()
-      (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
-
-    *** Interrupt mode IO MEM operation ***
-    =======================================
-    [..]
-      (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
-          HAL_I2C_Mem_Write_IT()
-      (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
-      (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
-          HAL_I2C_Mem_Read_IT()
-      (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
-      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
-           add his own code by customization of function pointer HAL_I2C_ErrorCallback()
-
-    *** DMA mode IO operation ***
-    ==============================
-    [..]
-      (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
-          HAL_I2C_Master_Transmit_DMA()
-      (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
-      (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
-          HAL_I2C_Master_Receive_DMA()
-      (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
-      (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
-          HAL_I2C_Slave_Transmit_DMA()
-      (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
-      (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
-          HAL_I2C_Slave_Receive_DMA()
-      (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
-      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
-           add his own code by customization of function pointer HAL_I2C_ErrorCallback()
-
-    *** DMA mode IO MEM operation ***
-    =================================
-    [..]
-      (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
-          HAL_I2C_Mem_Write_DMA()
-      (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
-      (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
-          HAL_I2C_Mem_Read_DMA()
-      (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
-      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
-           add his own code by customization of function pointer HAL_I2C_ErrorCallback()
-
-
-     *** I2C HAL driver macros list ***
-     ==================================
-     [..]
-       Below the list of most used macros in I2C HAL driver.
-
-      (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
-      (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
-      (+) __HAL_I2C_GET_FLAG:    Check whether the specified I2C flag is set or not
-      (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
-      (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
-      (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
-
-     [..]
-       (@) You can refer to the I2C HAL driver header file for more useful macros
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup I2C I2C
-  * @brief I2C HAL module driver
-  * @{
-  */
-
-#ifdef HAL_I2C_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/** @defgroup I2C_Private_Define I2C Private Define
-  * @{
-  */
-#define TIMING_CLEAR_MASK   ((uint32_t)0xF0FFFFFF)  /*!<  I2C TIMING clear register Mask */
-#define I2C_TIMEOUT_ADDR    ((uint32_t)10000)       /*!< 10 s  */
-#define I2C_TIMEOUT_BUSY    ((uint32_t)25)          /*!< 25 ms */
-#define I2C_TIMEOUT_DIR     ((uint32_t)25)          /*!< 25 ms */
-#define I2C_TIMEOUT_RXNE    ((uint32_t)25)          /*!< 25 ms */
-#define I2C_TIMEOUT_STOPF   ((uint32_t)25)          /*!< 25 ms */
-#define I2C_TIMEOUT_TC      ((uint32_t)25)          /*!< 25 ms */
-#define I2C_TIMEOUT_TCR     ((uint32_t)25)          /*!< 25 ms */
-#define I2C_TIMEOUT_TXIS    ((uint32_t)25)          /*!< 25 ms */
-#define I2C_TIMEOUT_FLAG    ((uint32_t)25)          /*!< 25 ms */
-
-#define SlaveAddr_SHIFT     7
-#define SlaveAddr_MSK       0x06
-
-/* Private define for @ref PreviousState usage */
-#define I2C_STATE_MSK             ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~HAL_I2C_STATE_READY))) /*!< Mask State define, keep only RX and TX bits            */
-#define I2C_STATE_NONE            ((uint32_t)(HAL_I2C_MODE_NONE))                                                        /*!< Default Value                                          */
-#define I2C_STATE_MASTER_BUSY_TX  ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))            /*!< Master Busy TX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_MASTER_BUSY_RX  ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))            /*!< Master Busy RX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_SLAVE_BUSY_TX   ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))             /*!< Slave Busy TX, combinaison of State LSB and Mode enum  */
-#define I2C_STATE_SLAVE_BUSY_RX   ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))             /*!< Slave Busy RX, combinaison of State LSB and Mode enum  */
-#define I2C_STATE_MEM_BUSY_TX     ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM))               /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_MEM_BUSY_RX     ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM))               /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
-
-
-/* Private define to centralize the enable/disable of Interrupts */
-#define I2C_XFER_TX_IT                       ((uint32_t)0x00000001)
-#define I2C_XFER_RX_IT                       ((uint32_t)0x00000002)
-#define I2C_XFER_LISTEN_IT                   ((uint32_t)0x00000004)
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
-/** @defgroup I2C_Private_Functions I2C Private Functions
-  * @{
-  */
-static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMAError(DMA_HandleTypeDef *hdma);
-
-static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
-
-static HAL_StatusTypeDef I2C_Master_ISR(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_Slave_ISR(I2C_HandleTypeDef *hi2c);
-
-static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
-static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
-
-static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c,  uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup I2C_Exported_Functions I2C Exported Functions
-  * @{
-  */
-
-/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @brief    Initialization and Configuration functions 
- *
-@verbatim
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This subsection provides a set of functions allowing to initialize and
-          deinitialize the I2Cx peripheral:
-
-      (+) User must Implement HAL_I2C_MspInit() function in which he configures
-          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
-
-      (+) Call the function HAL_I2C_Init() to configure the selected device with
-          the selected configuration:
-        (++) Clock Timing
-        (++) Own Address 1
-        (++) Addressing mode (Master, Slave)
-        (++) Dual Addressing mode
-        (++) Own Address 2
-        (++) Own Address 2 Mask
-        (++) General call mode
-        (++) Nostretch mode
-
-      (+) Call the function HAL_I2C_DeInit() to restore the default configuration
-          of the selected I2Cx peripheral.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the I2C according to the specified parameters
-  *         in the I2C_InitTypeDef and initialize the associated handle.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
-{ 
-  /* Check the I2C handle allocation */
-  if(hi2c == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
-  assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
-  assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
-  assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
-  assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
-  assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
-  assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
-  assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
-
-  if(hi2c->State == HAL_I2C_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hi2c->Lock = HAL_UNLOCKED;
-
-    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
-    HAL_I2C_MspInit(hi2c);
-  }
-
-  hi2c->State = HAL_I2C_STATE_BUSY;
-
-  /* Disable the selected I2C peripheral */
-  __HAL_I2C_DISABLE(hi2c);
-
-  /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
-  /* Configure I2Cx: Frequency range */
-  hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
-
-  /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
-  /* Configure I2Cx: Own Address1 and ack own address1 mode */
-  hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
-  if(hi2c->Init.OwnAddress1 != 0)
-  {
-    if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
-    {
-      hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
-    }
-    else /* I2C_ADDRESSINGMODE_10BIT */
-    {
-      hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
-    }
-  }
-
-  /*---------------------------- I2Cx CR2 Configuration ----------------------*/
-  /* Configure I2Cx: Addressing Master mode */
-  if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
-  {
-    hi2c->Instance->CR2 = (I2C_CR2_ADD10);
-  }
-  /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
-  hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
-
-  /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
-  /* Configure I2Cx: Dual mode and Own Address2 */
-  hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));
-
-  /*---------------------------- I2Cx CR1 Configuration ----------------------*/
-  /* Configure I2Cx: Generalcall and NoStretch mode */
-  hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
-
-  /* Enable the selected I2C peripheral */
-  __HAL_I2C_ENABLE(hi2c);
-
-  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-  hi2c->State = HAL_I2C_STATE_READY;
-  hi2c->PreviousState = I2C_STATE_NONE;
-  hi2c->Mode = HAL_I2C_MODE_NONE;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitialize the I2C peripheral.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
-{
-  /* Check the I2C handle allocation */
-  if(hi2c == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
-
-  hi2c->State = HAL_I2C_STATE_BUSY;
-
-  /* Disable the I2C Peripheral Clock */
-  __HAL_I2C_DISABLE(hi2c);
-
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
-  HAL_I2C_MspDeInit(hi2c);
-
-  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-  hi2c->State = HAL_I2C_STATE_RESET;
-  hi2c->PreviousState = I2C_STATE_NONE;
-  hi2c->Mode = HAL_I2C_MODE_NONE;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hi2c);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Initialize the I2C MSP.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief DeInitialize the I2C MSP.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
- *  @brief   Data transfers functions 
- *
-@verbatim
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to manage the I2C data
-    transfers.
-
-    (#) There are two modes of transfer:
-       (++) Blocking mode : The communication is performed in the polling mode.
-            The status of all data processing is returned by the same function 
-            after finishing transfer.
-       (++) No-Blocking mode : The communication is performed using Interrupts
-            or DMA. These functions return the status of the transfer startup.
-            The end of the data processing will be indicated through the
-            dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
-            using DMA mode.
-
-    (#) Blocking mode functions are :
-        (++) HAL_I2C_Master_Transmit()
-        (++) HAL_I2C_Master_Receive()
-        (++) HAL_I2C_Slave_Transmit()
-        (++) HAL_I2C_Slave_Receive()
-        (++) HAL_I2C_Mem_Write()
-        (++) HAL_I2C_Mem_Read()
-        (++) HAL_I2C_IsDeviceReady()
-
-    (#) No-Blocking mode functions with Interrupt are :
-        (++) HAL_I2C_Master_Transmit_IT()
-        (++) HAL_I2C_Master_Receive_IT()
-        (++) HAL_I2C_Slave_Transmit_IT()
-        (++) HAL_I2C_Slave_Receive_IT()
-        (++) HAL_I2C_Mem_Write_IT()
-        (++) HAL_I2C_Mem_Read_IT()
-
-    (#) No-Blocking mode functions with DMA are :
-        (++) HAL_I2C_Master_Transmit_DMA()
-        (++) HAL_I2C_Master_Receive_DMA()
-        (++) HAL_I2C_Slave_Transmit_DMA()
-        (++) HAL_I2C_Slave_Receive_DMA()
-        (++) HAL_I2C_Mem_Write_DMA()
-        (++) HAL_I2C_Mem_Read_DMA()
-
-    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
-        (++) HAL_I2C_MemTxCpltCallback()
-        (++) HAL_I2C_MemRxCpltCallback()
-        (++) HAL_I2C_MasterTxCpltCallback()
-        (++) HAL_I2C_MasterRxCpltCallback()
-        (++) HAL_I2C_SlaveTxCpltCallback()
-        (++) HAL_I2C_SlaveRxCpltCallback()
-        (++) HAL_I2C_ErrorCallback()
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Transmits in master mode an amount of data in blocking mode.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint32_t tickstart = 0;
-  uint32_t sizetmp = 0;
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {    
-    if((pData == NULL ) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Init tickstart for timeout management*/
-    tickstart = HAL_GetTick();
-
-    hi2c->State = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-
-    /* Send Slave Address */
-    /* Set NBYTES to write and reload if size > 255 and generate RESTART */
-    /* Size > 255, need to set RELOAD bit */
-    if(Size > 255)
-    {
-      I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
-      sizetmp = 255;
-    }
-    else
-    {
-      I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
-      sizetmp = Size;
-    }
-
-    do
-    {
-      /* Wait until TXIS flag is set */
-      if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-      {
-        if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-        {
-          return HAL_ERROR;
-        }
-        else
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-      /* Write data to TXDR */
-      hi2c->Instance->TXDR = (*pData++);
-      sizetmp--;
-      Size--;
-
-      if((sizetmp == 0)&&(Size!=0))
-      {
-        /* Wait until TCR flag is set */
-        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-
-        if(Size > 255)
-        {
-          I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
-          sizetmp = 255;
-        }
-        else
-        {
-          I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
-          sizetmp = Size;
-        }
-      }
-
-    }while(Size > 0);
-
-    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
-    /* Wait until STOPF flag is set */
-    if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Clear STOP Flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-    /* Clear Configuration Register 2 */
-    I2C_RESET_CR2(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode = HAL_I2C_MODE_NONE;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receives in master mode an amount of data in blocking mode.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint32_t tickstart = 0;
-  uint32_t sizetmp = 0;
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {    
-    if((pData == NULL ) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Init tickstart for timeout management*/
-    tickstart = HAL_GetTick();
-
-    hi2c->State = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-
-    /* Send Slave Address */
-    /* Set NBYTES to write and reload if size > 255 and generate RESTART */
-    /* Size > 255, need to set RELOAD bit */
-    if(Size > 255)
-    {
-      I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
-      sizetmp = 255;
-    }
-    else
-    {
-      I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
-      sizetmp = Size;
-    }
-
-    do
-    {
-      /* Wait until RXNE flag is set */
-      if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-      {
-        if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-        {
-          return HAL_ERROR;
-        }
-        else
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-
-      /* Write data to RXDR */
-      (*pData++) =hi2c->Instance->RXDR;
-      sizetmp--;
-      Size--;
-
-      if((sizetmp == 0)&&(Size!=0))
-      {
-        /* Wait until TCR flag is set */
-        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-
-        if(Size > 255)
-        {
-          I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
-          sizetmp = 255;
-        }
-        else
-        {
-          I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
-          sizetmp = Size;
-        }
-      }
-
-    }while(Size > 0);
-
-    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
-    /* Wait until STOPF flag is set */
-    if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-    
-    /* Clear STOP Flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-    /* Clear Configuration Register 2 */
-    I2C_RESET_CR2(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode = HAL_I2C_MODE_NONE;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Transmits in slave mode an amount of data in blocking mode. 
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint32_t tickstart = 0;
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == NULL ) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-    
-    /* Init tickstart for timeout management*/
-    tickstart = HAL_GetTick();
-
-    hi2c->State = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-
-    /* Enable Address Acknowledge */
-    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
-    /* Wait until ADDR flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
-    {
-      /* Disable Address Acknowledge */
-      hi2c->Instance->CR2 |= I2C_CR2_NACK;
-      return HAL_TIMEOUT;
-    }
-
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
-
-    /* If 10bit addressing mode is selected */
-    if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
-    {
-      /* Wait until ADDR flag is set */
-      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
-      {
-        /* Disable Address Acknowledge */
-        hi2c->Instance->CR2 |= I2C_CR2_NACK;
-        return HAL_TIMEOUT;
-      }
-
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
-    }
-
-    /* Wait until DIR flag is set Transmitter mode */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
-    {
-      /* Disable Address Acknowledge */
-      hi2c->Instance->CR2 |= I2C_CR2_NACK;
-      return HAL_TIMEOUT;
-    }
-
-    do
-    {
-      /* Wait until TXIS flag is set */
-      if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-      {
-        /* Disable Address Acknowledge */
-        hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
-        if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-        {
-          return HAL_ERROR;
-        }
-        else
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-
-      /* Write data to TXDR */
-      hi2c->Instance->TXDR = (*pData++);
-      Size--;
-    }while(Size > 0);
-
-    /* Wait until STOP flag is set */
-    if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-    {
-      /* Disable Address Acknowledge */
-      hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-	/* Normal use case for Transmitter mode */
-	/* A NACK is generated to confirm the end of transfer */
-	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Clear STOP flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
-
-    /* Wait until BUSY flag is reset */ 
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
-    {
-      /* Disable Address Acknowledge */
-      hi2c->Instance->CR2 |= I2C_CR2_NACK;
-      return HAL_TIMEOUT;
-    }
-
-    /* Disable Address Acknowledge */
-    hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode = HAL_I2C_MODE_NONE;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receive in slave mode an amount of data in blocking mode
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint32_t tickstart = 0;
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {  
-    if((pData == NULL ) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Init tickstart for timeout management*/
-    tickstart = HAL_GetTick();
-
-    hi2c->State = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-    
-    /* Enable Address Acknowledge */
-    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
-    /* Wait until ADDR flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
-    {
-      /* Disable Address Acknowledge */
-      hi2c->Instance->CR2 |= I2C_CR2_NACK;
-      return HAL_TIMEOUT;
-    }
-
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
-
-    /* Wait until DIR flag is reset Receiver mode */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
-    {
-      /* Disable Address Acknowledge */
-      hi2c->Instance->CR2 |= I2C_CR2_NACK;
-      return HAL_TIMEOUT;
-    }
-
-    while(Size > 0)
-    {
-      /* Wait until RXNE flag is set */
-      if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-      {
-        /* Disable Address Acknowledge */
-        hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
-        /* Store Last receive data if any */
-        if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
-        {
-          /* Read data from RXDR */
-          (*pData++) = hi2c->Instance->RXDR;
-        }
-
-        if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
-        {
-          return HAL_TIMEOUT;
-        }
-        else
-        {
-          return HAL_ERROR;
-        }
-      }
-
-      /* Read data from RXDR */
-      (*pData++) = hi2c->Instance->RXDR;
-      Size--;
-    }
-
-    /* Wait until STOP flag is set */
-    if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-    {
-      /* Disable Address Acknowledge */
-      hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Clear STOP flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
-
-    /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
-    {
-      /* Disable Address Acknowledge */
-      hi2c->Instance->CR2 |= I2C_CR2_NACK;
-      return HAL_TIMEOUT;
-    }
-
-    /* Disable Address Acknowledge */
-    hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode = HAL_I2C_MODE_NONE;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Transmit in master mode an amount of data in non-blocking mode with Interrupt
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
-{
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-
-    hi2c->pBuffPtr = pData;
-    hi2c->XferCount = Size;
-    if(Size > 255)
-    {
-      hi2c->XferSize = 255;
-    }
-    else
-    {
-      hi2c->XferSize = Size;
-    }
-
-    /* Send Slave Address */
-    /* Set NBYTES to write and reload if size > 255 and generate RESTART */
-    if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
-    {
-      I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
-    }
-    else
-    {
-      I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c); 
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-
-    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
-    /* possible to enable all of these */
-    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receive in master mode an amount of data in non-blocking mode with Interrupt
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
-{
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-
-    hi2c->pBuffPtr = pData;
-    hi2c->XferCount = Size;
-    if(Size > 255)
-    {
-      hi2c->XferSize = 255;
-    }
-    else
-    {
-      hi2c->XferSize = Size;
-    }
-
-    /* Send Slave Address */
-    /* Set NBYTES to write and reload if size > 255 and generate RESTART */
-    if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
-    {
-      I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
-    }
-    else
-    {
-      I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
-    }
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-
-    /* Enable ERR, TC, STOP, NACK, RXI interrupt */
-    /* possible to enable all of these */
-    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Transmit in slave mode an amount of data in non-blocking mode with Interrupt
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
-{
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-
-    /* Enable Address Acknowledge */
-    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
-    hi2c->pBuffPtr = pData;
-    hi2c->XferSize = Size;
-    hi2c->XferCount = Size;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-
-    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
-    /* possible to enable all of these */
-    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receive in slave mode an amount of data in non-blocking mode with Interrupt 
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
-{
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-
-    /* Enable Address Acknowledge */
-    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
-    hi2c->pBuffPtr = pData;
-    hi2c->XferSize = Size;
-    hi2c->XferCount = Size;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-
-    /* Enable ERR, TC, STOP, NACK, RXI interrupt */
-    /* possible to enable all of these */
-    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Transmit in master mode an amount of data in non-blocking mode with DMA
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
-{
-  uint32_t tickstart = 0;
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Init tickstart for timeout management*/
-    tickstart = HAL_GetTick();
-
-    hi2c->State = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-
-    hi2c->pBuffPtr = pData;
-    hi2c->XferCount = Size;
-    if(Size > 255)
-    {
-      hi2c->XferSize = 255;
-    }
-    else
-    {
-      hi2c->XferSize = Size;
-    }
-
-    /* Set the I2C DMA transfer complete callback */
-    hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
-
-    /* Set the DMA error callback */
-    hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
-
-    /* Enable the DMA channel */
-    HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
-
-    /* Send Slave Address */
-    /* Set NBYTES to write and reload if size > 255 and generate RESTART */
-    if((hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount))
-    {
-      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
-    }
-    else
-    {
-      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
-    }
-
-    /* Wait until TXIS flag is set */
-    if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS, tickstart) != HAL_OK)
-    {
-      /* Disable Address Acknowledge */
-      hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
-      /* Abort DMA */
-      HAL_DMA_Abort(hi2c->hdmatx);
-
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Enable DMA Request */
-    hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receive in master mode an amount of data in non-blocking mode with DMA
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
-{
-  uint32_t tickstart = 0;
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }  
-
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Init tickstart for timeout management*/
-    tickstart = HAL_GetTick();
-
-    hi2c->State = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-
-    hi2c->pBuffPtr = pData;
-    hi2c->XferCount = Size;
-    if(Size > 255)
-    {
-      hi2c->XferSize = 255;
-    }
-    else
-    {
-      hi2c->XferSize = Size;
-    }
-
-    /* Set the I2C DMA transfer complete callback */
-    hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
-
-    /* Set the DMA error callback */
-    hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-
-    /* Enable the DMA channel */
-    HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
-
-    /* Send Slave Address */
-    /* Set NBYTES to write and reload if size > 255 and generate RESTART */
-    if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
-    {
-      I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
-    }
-    else
-    {
-      I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
-    }
-
-    /* Wait until RXNE flag is set */
-    if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, tickstart) != HAL_OK)
-    {
-      /* Abort DMA */
-      HAL_DMA_Abort(hi2c->hdmarx);
-
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Enable DMA Request */
-    hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Transmit in slave mode an amount of data in non-blocking mode with DMA
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
-{
-  uint32_t tickstart = 0;
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }   
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Init tickstart for timeout management*/
-    tickstart = HAL_GetTick();
-
-    hi2c->State = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-
-    hi2c->pBuffPtr = pData;
-    hi2c->XferCount = Size;
-    hi2c->XferSize = Size;
-
-    /* Set the I2C DMA transfer complete callback */
-    hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
-
-    /* Set the DMA error callback */
-    hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
-
-    /* Enable the DMA channel */
-    HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
-
-    /* Enable Address Acknowledge */
-    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
-    /* Wait until ADDR flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR, tickstart) != HAL_OK)
-    {
-      /* Disable Address Acknowledge */
-      hi2c->Instance->CR2 |= I2C_CR2_NACK;
-      return HAL_TIMEOUT;
-    }
-
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
-    
-    /* If 10bits addressing mode is selected */
-    if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
-    {
-      /* Wait until ADDR flag is set */
-      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR, tickstart) != HAL_OK)
-      {
-        /* Disable Address Acknowledge */
-        hi2c->Instance->CR2 |= I2C_CR2_NACK;
-        return HAL_TIMEOUT;
-      }
-
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
-    }
-    
-    /* Wait until DIR flag is set Transmitter mode */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
-    {
-      /* Disable Address Acknowledge */
-      hi2c->Instance->CR2 |= I2C_CR2_NACK;
-      return HAL_TIMEOUT;
-    }
-
-    /* Enable DMA Request */
-    hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; 
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receive in slave mode an amount of data in non-blocking mode with DMA
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
-{
-  uint32_t tickstart = 0;
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }   
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Init tickstart for timeout management*/
-    tickstart = HAL_GetTick();
-
-    hi2c->State = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-
-    hi2c->pBuffPtr = pData;
-    hi2c->XferSize = Size;
-    hi2c->XferCount = Size;
-
-    /* Set the I2C DMA transfer complete callback */
-    hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
-
-    /* Set the DMA error callback */
-    hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-
-    /* Enable the DMA channel */
-    HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, Size);
-
-    /* Enable Address Acknowledge */
-    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
-    /* Wait until ADDR flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR, tickstart) != HAL_OK)
-    {
-      /* Disable Address Acknowledge */
-      hi2c->Instance->CR2 |= I2C_CR2_NACK;
-      return HAL_TIMEOUT;
-    }
-
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
-
-    /* Wait until DIR flag is set Receiver mode */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, I2C_TIMEOUT_DIR, tickstart) != HAL_OK)
-    {
-      /* Disable Address Acknowledge */
-      hi2c->Instance->CR2 |= I2C_CR2_NACK;
-      return HAL_TIMEOUT;
-    }
- 
-    /* Enable DMA Request */
-    hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-/**
-  * @brief  Write an amount of data in blocking mode to a specific memory address
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address
-  * @param  MemAddress Internal memory address
-  * @param  MemAddSize Size of internal memory address
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint32_t tickstart = 0;
-  uint32_t Sizetmp = 0;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Init tickstart for timeout management*/
-    tickstart = HAL_GetTick();
-
-    hi2c->State = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode = HAL_I2C_MODE_MEM;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Send Slave Address and Memory Address */
-    if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_ERROR;
-      }
-      else
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Set NBYTES to write and reload if size > 255 */
-    /* Size > 255, need to set RELOAD bit */
-    if(Size > 255)
-    {
-      I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
-      Sizetmp = 255;
-    }
-    else
-    {
-      I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
-      Sizetmp = Size;
-    }
-
-    do
-    {
-      /* Wait until TXIS flag is set */
-      if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-      {
-        if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-        {
-          return HAL_ERROR;
-        }
-        else
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-
-      /* Write data to DR */
-      hi2c->Instance->TXDR = (*pData++);
-      Sizetmp--;
-      Size--;
-
-      if((Sizetmp == 0)&&(Size!=0))
-      {
-        /* Wait until TCR flag is set */
-        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-
-        if(Size > 255)
-        {
-          I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
-          Sizetmp = 255;
-        }
-        else
-        {
-          I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
-          Sizetmp = Size;
-        }
-      }
-
-    }while(Size > 0);
-
-    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
-    /* Wait until STOPF flag is reset */ 
-    if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Clear STOP Flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-    /* Clear Configuration Register 2 */
-    I2C_RESET_CR2(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode = HAL_I2C_MODE_NONE;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Read an amount of data in blocking mode from a specific memory address
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address
-  * @param  MemAddress Internal memory address
-  * @param  MemAddSize Size of internal memory address
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint32_t tickstart = 0;
-  uint32_t Sizetmp = 0;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Init tickstart for timeout management*/
-    tickstart = HAL_GetTick();
-
-    hi2c->State = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode = HAL_I2C_MODE_MEM;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Send Slave Address and Memory Address */
-    if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_ERROR;
-      }
-      else
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Send Slave Address */
-    /* Set NBYTES to write and reload if size > 255 and generate RESTART */
-    /* Size > 255, need to set RELOAD bit */
-    if(Size > 255)
-    {
-      I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
-      Sizetmp = 255;
-    }
-    else
-    {
-      I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
-      Sizetmp = Size;
-    }
-
-    do
-    {
-      /* Wait until RXNE flag is set */
-      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
-
-      /* Read data from RXDR */
-      (*pData++) = hi2c->Instance->RXDR;
-
-      /* Decrement the Size counter */
-      Sizetmp--;
-      Size--;
-
-      if((Sizetmp == 0)&&(Size!=0))
-      {
-        /* Wait until TCR flag is set */
-        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-
-        if(Size > 255)
-        {
-          I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
-          Sizetmp = 255;
-        }
-        else
-        {
-          I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
-          Sizetmp = Size;
-        }
-      }
-
-    }while(Size > 0);
-
-    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
-    /* Wait until STOPF flag is reset */ 
-    if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Clear STOP Flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-    /* Clear Configuration Register 2 */
-    I2C_RESET_CR2(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode = HAL_I2C_MODE_NONE;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-/**
-  * @brief  Write an amount of data in non-blocking mode with Interrupt to a specific memory address
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address
-  * @param  MemAddress Internal memory address
-  * @param  MemAddSize Size of internal memory address
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
-{
-  uint32_t tickstart = 0;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-    
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Init tickstart for timeout management*/
-    tickstart = HAL_GetTick();
-
-    hi2c->State = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode = HAL_I2C_MODE_MEM;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-
-    hi2c->pBuffPtr = pData;
-    hi2c->XferCount = Size;
-    if(Size > 255)
-    {
-      hi2c->XferSize = 255;
-    }
-    else
-    {
-      hi2c->XferSize = Size;
-    }
-
-    /* Send Slave Address and Memory Address */
-    if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_ERROR;
-      }
-      else
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Set NBYTES to write and reload if size > 255 */
-    /* Size > 255, need to set RELOAD bit */
-    if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
-    {
-      I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
-    }
-    else
-    {
-      I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
-    }  
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c); 
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process 
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-
-    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
-    /* possible to enable all of these */
-    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Read an amount of data in non-blocking mode with Interrupt from a specific memory address
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address
-  * @param  MemAddress Internal memory address
-  * @param  MemAddSize Size of internal memory address
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
-{
-  uint32_t tickstart = 0;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-    
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Init tickstart for timeout management*/
-    tickstart = HAL_GetTick();
-
-    hi2c->State = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode = HAL_I2C_MODE_MEM;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-
-    hi2c->pBuffPtr = pData;
-    hi2c->XferCount = Size;
-    if(Size > 255)
-    {
-      hi2c->XferSize = 255;
-    }
-    else
-    {
-      hi2c->XferSize = Size;
-    }
-
-    /* Send Slave Address and Memory Address */
-    if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_ERROR;
-      }
-      else
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Set NBYTES to write and reload if size > 255 and generate RESTART */
-    /* Size > 255, need to set RELOAD bit */
-    if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
-    {
-      I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
-    }
-    else
-    {
-      I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-
-    /* Enable ERR, TC, STOP, NACK, RXI interrupt */
-    /* possible to enable all of these */
-    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }   
-}
-/**
-  * @brief  Write an amount of data in non-blocking mode with DMA to a specific memory address
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address
-  * @param  MemAddress Internal memory address
-  * @param  MemAddSize Size of internal memory address
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
-{
-  uint32_t tickstart = 0;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Init tickstart for timeout management*/
-    tickstart = HAL_GetTick();
-
-    hi2c->State = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode = HAL_I2C_MODE_MEM;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    hi2c->pBuffPtr = pData;
-    hi2c->XferCount = Size;
-    if(Size > 255)
-    {
-      hi2c->XferSize = 255;
-    }
-    else
-    {
-      hi2c->XferSize = Size;
-    }
-
-    /* Set the I2C DMA transfer complete callback */
-    hi2c->hdmatx->XferCpltCallback = I2C_DMAMemTransmitCplt;
-
-    /* Set the DMA error callback */
-    hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
-
-    /* Enable the DMA channel */
-    HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
-
-    /* Send Slave Address and Memory Address */
-    if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_ERROR;
-      }
-      else
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Send Slave Address */
-    /* Set NBYTES to write and reload if size > 255 */
-    if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
-    {
-      I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
-    }
-    else
-    {
-      I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
-    }
-
-    /* Wait until TXIS flag is set */
-    if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS, tickstart) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Enable DMA Request */
-    hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Reads an amount of data in non-blocking mode with DMA from a specific memory address.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address
-  * @param  MemAddress Internal memory address
-  * @param  MemAddSize Size of internal memory address
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be read
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
-{
-  uint32_t tickstart = 0;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-  
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Init tickstart for timeout management*/
-    tickstart = HAL_GetTick();
-
-    hi2c->State = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode = HAL_I2C_MODE_MEM;
-
-    hi2c->pBuffPtr = pData;
-    hi2c->XferCount = Size;
-    if(Size > 255)
-    {
-      hi2c->XferSize = 255;
-    }
-    else
-    {
-      hi2c->XferSize = Size;
-    }
-
-    /* Set the I2C DMA transfer complete callback */
-    hi2c->hdmarx->XferCpltCallback = I2C_DMAMemReceiveCplt;
-
-    /* Set the DMA error callback */
-    hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-
-    /* Enable the DMA channel */
-    HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
-
-    /* Send Slave Address and Memory Address */
-    if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_ERROR;
-      }
-      else
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Set NBYTES to write and reload if size > 255 and generate RESTART */
-    if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
-    {
-      I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
-    }
-    else
-    {
-      I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
-    }
-
-    /* Wait until RXNE flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE, tickstart) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    /* Enable DMA Request */
-    hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Checks if target device is ready for communication.
-  * @note   This function is used with Memory devices
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address
-  * @param  Trials Number of trials
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
-{  
-  uint32_t tickstart = 0;
-
-  __IO uint32_t I2C_Trials = 0;
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_BUSY;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    do
-    {
-      /* Generate Start */
-      hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode,DevAddress);
-      
-      /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
-      /* Wait until STOPF flag is set or a NACK flag is set*/
-      tickstart = HAL_GetTick();
-      while((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT))
-      {
-      	if(Timeout != HAL_MAX_DELAY)
-      	{
-          if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-          {
-            /* Device is ready */
-            hi2c->State = HAL_I2C_STATE_READY;
-            /* Process Unlocked */
-            __HAL_UNLOCK(hi2c);
-            return HAL_TIMEOUT;
-          }
-        } 
-      }
-
-      /* Check if the NACKF flag has not been set */
-      if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
-      {
-        /* Wait until STOPF flag is reset */ 
-        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-
-        /* Clear STOP Flag */
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-        /* Device is ready */
-        hi2c->State = HAL_I2C_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_OK;
-      }
-      else
-      {
-        /* Wait until STOPF flag is reset */ 
-        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-
-        /* Clear NACK Flag */
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-        /* Clear STOP Flag, auto generated with autoend*/
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-      }
-
-      /* Check if the maximum allowed number of trials has been reached */
-      if (I2C_Trials++ == Trials)
-      {
-        /* Generate Stop */
-        hi2c->Instance->CR2 |= I2C_CR2_STOP;
-        
-        /* Wait until STOPF flag is reset */ 
-        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-
-        /* Clear STOP Flag */
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-      }
-    }while(I2C_Trials < Trials);
-
-    hi2c->State = HAL_I2C_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_TIMEOUT;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
-  * @note   This interface allow to manage repeated start condition when a direction change during transfer
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr = pData;
-    hi2c->XferCount = Size;
-    hi2c->XferOptions = XferOptions;
-
-    if(Size > 255)
-    {
-      hi2c->XferSize = 255;
-    }
-    else
-    {
-      hi2c->XferSize = Size;
-    }
-
-    /* Send Slave Address */
-    /* Set NBYTES to write and reload if size > 255 and generate RESTART */
-    if((hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount))
-    {
-      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
-    }
-    else
-    {
-      /* If transfer direction not change, do not generate Restart Condition */
-      /* Mean Previous state is same as current state */
-      if(hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_TX)
-      {
-        I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP);
-      }
-      /* Else transfer direction change, so generate Restart with new transfer direction */
-      else
-      {
-        I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, hi2c->XferOptions, I2C_GENERATE_START_WRITE);
-      }
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c); 
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
-  * @note   This interface allow to manage repeated start condition when a direction change during transfer
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr = pData;
-    hi2c->XferCount = Size;
-    hi2c->XferOptions = XferOptions;
-
-    if(Size > 255)
-    {
-      hi2c->XferSize = 255;
-    }
-    else
-    {
-      hi2c->XferSize = Size;
-    }
-
-    /* Send Slave Address */
-    /* Set NBYTES to write and reload if size > 255 and generate RESTART */
-    if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
-    {
-      I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
-    }
-    else
-    {
-      /* If transfer direction not change, do not generate Restart Condition */
-      /* Mean Previous state is same as current state */
-      if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
-      {
-        I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP);
-      }
-      /* Else transfer direction change, so generate Restart with new transfer direction */
-      else
-      {
-        I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, hi2c->XferOptions, I2C_GENERATE_START_READ);
-      }
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c); 
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
-  * @note   This interface allow to manage repeated start condition when a direction change during transfer
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
-  if(hi2c->State == HAL_I2C_STATE_LISTEN)
-  {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
-    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
-    hi2c->Mode = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Enable Address Acknowledge */
-    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr = pData;
-    hi2c->XferSize = Size;
-    hi2c->XferCount = Size;
-    hi2c->XferOptions = XferOptions;
-
-    if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
-    {
-      /* Clear ADDR flag after prepare the transfer parameters */
-      /* This action will generate an acknowledge to the Master */
-      __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c); 
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-    to avoid the risk of I2C interrupt handle execution before current
-    process unlock */
-    /* REnable ADDR interrupt */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
-  * @note   This interface allow to manage repeated start condition when a direction change during transfer
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
-  if(hi2c->State == HAL_I2C_STATE_LISTEN)
-  {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
-    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
-    hi2c->Mode = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Enable Address Acknowledge */
-    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr = pData;
-    hi2c->XferSize = Size;
-    hi2c->XferCount = Size;
-    hi2c->XferOptions = XferOptions;
-
-    if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
-    {
-      /* Clear ADDR flag after prepare the transfer parameters */
-      /* This action will generate an acknowledge to the Master */
-      __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-    to avoid the risk of I2C interrupt handle execution before current
-    process unlock */
-    /* REnable ADDR interrupt */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Enable the Address listen mode with Interrupt.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
-{
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    hi2c->State = HAL_I2C_STATE_LISTEN;
-
-    /* Enable the Address Match interrupt */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Disable the Address listen mode with Interrupt.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
-{
-  /* Declaration of tmp to prevent undefined behavior of volatile usage */
-  uint32_t tmp;
-
-  /* Disable Address listen mode only if a transfer is not ongoing */
-  if(hi2c->State == HAL_I2C_STATE_LISTEN)
-  {
-    tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
-    hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode = HAL_I2C_MODE_NONE;
-
-    /* Disable the Address Match interrupt */
-    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Abort a master/host I2C process communication with Interrupt.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
-{
-  if((hi2c->Mode == HAL_I2C_MODE_MASTER) || \
-     ((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) && (hi2c->Mode == HAL_I2C_MODE_MASTER)))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Keep the same state as previous */
-    /* to perform as well the call of the corresponding end of transfer callback */
-    if((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (hi2c->ErrorCode != HAL_I2C_ERROR_NONE))
-    {
-      hi2c->State = HAL_I2C_STATE_BUSY_TX;
-      hi2c->Mode = HAL_I2C_MODE_MASTER;
-    }
-    else if((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (hi2c->ErrorCode != HAL_I2C_ERROR_NONE))
-    {
-      hi2c->State = HAL_I2C_STATE_BUSY_RX;
-      hi2c->Mode = HAL_I2C_MODE_MASTER;
-    }
-
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
-    /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
-    I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process 
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-    if((hi2c->State == HAL_I2C_STATE_BUSY_TX) && (hi2c->Mode == HAL_I2C_MODE_MASTER))
-    {
-      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
-    }
-    if((hi2c->State == HAL_I2C_STATE_BUSY_RX) && (hi2c->Mode == HAL_I2C_MODE_MASTER))
-    {
-      I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
-    }
-    
-    return HAL_OK;
-  }
-  else
-  {
-    /* Wrong usage of abort function */
-    /* This function should be used only in case of abort monitored by master device */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
- * @{
- */   
-
-/**
-  * @brief  This function handles I2C event interrupt request.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
-{
-  uint32_t tmpisrvalue = 0;
-  
-  /* Use a local variable to store the current ISR flags */
-  /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */
-  tmpisrvalue = I2C_GET_ISR_REG(hi2c);
-    
-  /* I2C in mode Transmitter ---------------------------------------------------*/
-  if (((I2C_CHECK_FLAG(tmpisrvalue, I2C_FLAG_TXIS) != RESET) || (I2C_CHECK_FLAG(tmpisrvalue, I2C_FLAG_TCR) != RESET) || (I2C_CHECK_FLAG(tmpisrvalue, I2C_FLAG_TC) != RESET) || (I2C_CHECK_FLAG(tmpisrvalue, I2C_FLAG_STOPF) != RESET) || (I2C_CHECK_FLAG(tmpisrvalue, I2C_FLAG_AF) != RESET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_TXI)) != RESET))
-  {
-    /* Slave mode selected */
-    if (hi2c->Mode  == HAL_I2C_MODE_SLAVE)
-    {
-      I2C_Slave_ISR(hi2c);
-    }
-    /* Master or Memory mode selected */
-    else if ((hi2c->Mode == HAL_I2C_MODE_MASTER) || (hi2c->Mode == HAL_I2C_MODE_MEM))
-    {
-      I2C_Master_ISR(hi2c);
-    }
-  }
-
-  /* I2C in mode Receiver ----------------------------------------------------*/
-  if (((I2C_CHECK_FLAG(tmpisrvalue, I2C_FLAG_RXNE) != RESET) || (I2C_CHECK_FLAG(tmpisrvalue, I2C_FLAG_TCR) != RESET) || (I2C_CHECK_FLAG(tmpisrvalue, I2C_FLAG_TC) != RESET) || (I2C_CHECK_FLAG(tmpisrvalue, I2C_FLAG_STOPF) != RESET) || (I2C_CHECK_FLAG(tmpisrvalue, I2C_FLAG_AF) != RESET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_RXI)) != RESET))
-  {
-    /* Slave mode selected */
-    if (hi2c->Mode  == HAL_I2C_MODE_SLAVE)
-    {
-      I2C_Slave_ISR(hi2c);
-    }
-    /* Master or Memory mode selected */
-    else if ((hi2c->Mode == HAL_I2C_MODE_MASTER) || (hi2c->Mode == HAL_I2C_MODE_MEM))
-    {
-      I2C_Master_ISR(hi2c);
-    }
-  } 
-
-  /* I2C in mode Listener Only --------------------------------------------------*/
-  if (((I2C_CHECK_FLAG(tmpisrvalue, I2C_FLAG_ADDR) != RESET) || (I2C_CHECK_FLAG(tmpisrvalue, I2C_FLAG_STOPF) != RESET) || (I2C_CHECK_FLAG(tmpisrvalue, I2C_FLAG_AF) != RESET)) && ((__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ADDRI) != RESET) || (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_STOPI) != RESET) || (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_NACKI) != RESET)))
-  {
-    if(hi2c->XferOptions != I2C_NO_OPTION_FRAME)
-    {    
-      if((hi2c->State == HAL_I2C_STATE_LISTEN) || (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) || (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))
-      {
-        I2C_Slave_ISR(hi2c);
-      }
-    }
-    else
-    {
-      if(hi2c->Mode == HAL_I2C_MODE_SLAVE)
-      {
-        I2C_Slave_ISR(hi2c);
-      }
-    }
-  }
-}
-
-/**
-  * @brief  This function handles I2C error interrupt request.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
-{
-  /* I2C Bus error interrupt occurred ------------------------------------*/
-  if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BERR) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERRI) == SET))
-  {
-    hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
-
-    /* Clear BERR flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
-  }
-
-  /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
-  if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_OVR) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERRI) == SET))
-  {
-    hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
-
-    /* Clear OVR flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
-  }
-
-  /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
-  if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ARLO) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERRI) == SET))
-  {
-    hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
-
-    /* Clear ARLO flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
-  }
-
-  /* Call the Error Callback in case of Error detected */
-  if((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) !=  HAL_I2C_ERROR_NONE)
-  {
-    if(((hi2c->State == HAL_I2C_STATE_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_BUSY_RX)) && (hi2c->Mode == HAL_I2C_MODE_SLAVE))
-    {
-      /* Reset only HAL_I2C_STATE_SLAVE_BUSY_XX */
-      /* keep HAL_I2C_STATE_LISTEN if set */
-      hi2c->PreviousState = I2C_STATE_NONE;
-      hi2c->State = HAL_I2C_STATE_LISTEN;
-    }
-    else
-    {
-      hi2c->PreviousState = I2C_STATE_NONE;
-      hi2c->State = HAL_I2C_STATE_READY;
-    }
-
-    HAL_I2C_ErrorCallback(hi2c);
-  }
-}
-
-/**
-  * @brief  Master Tx Transfer completed callback.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Master Rx Transfer completed callback.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
-   */
-}
-
-/** @brief  Slave Tx Transfer completed callback.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Slave Rx Transfer completed callback.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Slave Address Match callback.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  TransferDirection: Master request Transfer Direction (Write/Read), value of @ref I2C_XferOptions_definition
-  * @param  AddrMatchCode: Address Match Code
-  * @retval None
-  */
-__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-  UNUSED(TransferDirection);
-  UNUSED(AddrMatchCode);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_AddrCallback() could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Listen Complete callback.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_ListenCpltCallback() could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Memory Tx Transfer completed callback.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_MemTxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Memory Rx Transfer completed callback.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_MemRxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  I2C error callback.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_ErrorCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
- *  @brief   Peripheral State, Mode and Error functions
- *
-@verbatim
- ===============================================================================
-            ##### Peripheral State, Mode and Error functions #####
- ===============================================================================
-    [..]
-    This subsection permit to get in run-time the status of the peripheral
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the I2C handle state.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval HAL state
-  */
-HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
-{
-  /* Return I2C handle state */
-  return hi2c->State;
-}
-
-/**
-  * @brief  Returns the I2C Master, Slave, Memory or no mode.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL mode
-  */
-HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
-{
-  return hi2c->Mode;
-}
-
-/**
-* @brief  Return the I2C error code.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *              the configuration information for the specified I2C.
-* @retval I2C Error Code
-*/
-uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
-{
-  return hi2c->ErrorCode;
-}
-
-/**
-  * @}
-  */  
-
-/**
-  * @}
-  */
-
-/** @addtogroup I2C_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_Master_ISR(I2C_HandleTypeDef *hi2c) 
-{
-  uint16_t DevAddress;
-
-  /* Process Locked */
-  __HAL_LOCK(hi2c);
-
-  if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) != RESET)
-  {
-    /* Clear NACK Flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-    /* Set corresponding Error Code */
-    /* No need to generate STOP, it is automatically done */
-    /* Error callback will be send during stop flag treatment */
-    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-
-    /* If a pending TXIS flag is set */
-    /* Write a dummy data in TXDR */
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
-    {
-       hi2c->Instance->TXDR = 0x00;
-    }
-  }
-  else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) != RESET)
-  {
-    /* Read data from RXDR */
-    (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
-    hi2c->XferSize--;
-    hi2c->XferCount--;
-  }
-  else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
-  {
-    /* Write data to TXDR */
-    hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
-    hi2c->XferSize--;
-    hi2c->XferCount--;	
-  }
-  else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) != RESET)
-  {
-    if((hi2c->XferSize == 0)&&(hi2c->XferCount!=0))
-    {
-      DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
-      
-      if(hi2c->XferCount > 255)
-      {
-        I2C_TransferConfig(hi2c, DevAddress, 255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
-        hi2c->XferSize = 255;
-      }
-      else
-      {
-        hi2c->XferSize = hi2c->XferCount;
-        if(hi2c->XferOptions != I2C_NO_OPTION_FRAME)
-        {
-          I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP);
-        }
-        else
-        {
-          I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
-        }
-      }
-    }
-    else
-    {
-      /* Call TxCpltCallback() if no stop mode is set */
-      if((I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)&&(hi2c->Mode == HAL_I2C_MODE_MASTER))
-      {
-        hi2c->Mode = HAL_I2C_MODE_NONE;
-
-        if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
-        {
-          hi2c->State = HAL_I2C_STATE_READY;
-          hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
-
-          /* Disable Interrupts */
-          I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2c);
-
-          /* Call the corresponding callback to inform upper layer of End of Transfer */
-            HAL_I2C_MasterTxCpltCallback(hi2c);
-        }
-        /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
-        else
-        {
-          hi2c->State = HAL_I2C_STATE_READY;
-          hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
-
-          /* Disable Interrupts */
-          I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2c);
-
-          /* Call the corresponding callback to inform upper layer of End of Transfer */
-          HAL_I2C_MasterRxCpltCallback(hi2c);
-        }
-      }
-      else
-      {
-        hi2c->PreviousState = I2C_STATE_NONE;
-        hi2c->State = HAL_I2C_STATE_READY;
-        hi2c->Mode = HAL_I2C_MODE_NONE;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        /* Wrong size Status regarding TCR flag event */
-        hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE;
-        HAL_I2C_ErrorCallback(hi2c);
-      }
-    }
-  }
-  else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET)
-  {
-    if(hi2c->XferCount == 0)
-    {
-      if((I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)&&(hi2c->Mode == HAL_I2C_MODE_MASTER))
-      {
-        hi2c->Mode = HAL_I2C_MODE_NONE;
-
-        /* No Generate Stop, to permit restart mode */
-        /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
-        if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
-        {
-          hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
-          hi2c->State = HAL_I2C_STATE_READY;
-
-          /* Disable Interrupts */
-          I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2c);
-
-          /* Call the corresponding callback to inform upper layer of End of Transfer */
-          HAL_I2C_MasterTxCpltCallback(hi2c);
-        }
-        /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
-        else
-        {
-          hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
-          hi2c->State = HAL_I2C_STATE_READY;
-
-          /* Disable Interrupts */
-          I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2c);
-
-          /* Call the corresponding callback to inform upper layer of End of Transfer */
-          HAL_I2C_MasterRxCpltCallback(hi2c);
-        }
-      }
-    }
-    else
-    {
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-      
-      /* Wrong size Status regarding TC flag event */
-      hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      /* Call the corresponding callback to inform upper layer of End of Transfer */
-      HAL_I2C_ErrorCallback(hi2c);
-    }
-  }
-
-  if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) != RESET)
-  {
-    if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
-    {
-      if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
-      {
-        /* Clear NACK Flag */
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-        hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-
-        /* If a pending TXIS flag is set */
-        /* Write a dummy data in TXDR to clear it */
-        if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
-        {
-           hi2c->Instance->TXDR = 0x00;
-        }
-      }
-
-      /* Disable Interrupts */
-      I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
-
-      /* Clear STOP Flag */
-      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-      /* Clear Configuration Register 2 */
-      I2C_RESET_CR2(hi2c);
-
-      /* Flush TX register if not empty */
-      if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
-      {
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
-      }
-
-      /* Call the corresponding callback to inform upper layer of End of Transfer */
-      if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
-      {
-        hi2c->PreviousState = I2C_STATE_NONE;
-        hi2c->State = HAL_I2C_STATE_READY;
-        hi2c->Mode = HAL_I2C_MODE_NONE;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        /* Call the corresponding callback to inform upper layer of End of Transfer */
-        HAL_I2C_ErrorCallback(hi2c);
-      }
-      else
-      {
-        if (hi2c->Mode == HAL_I2C_MODE_MEM)
-        {
-          hi2c->PreviousState = I2C_STATE_NONE;
-          hi2c->State = HAL_I2C_STATE_READY;
-          hi2c->Mode = HAL_I2C_MODE_NONE;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2c);
-
-          /* Call the corresponding callback to inform upper layer of End of Transfer */
-          HAL_I2C_MemTxCpltCallback(hi2c);
-        }
-        else
-        {
-          hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
-          hi2c->State = HAL_I2C_STATE_READY;
-          hi2c->Mode = HAL_I2C_MODE_NONE;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2c);
-
-          /* Call the corresponding callback to inform upper layer of End of Transfer */
-          HAL_I2C_MasterTxCpltCallback(hi2c);
-        }
-      }
-    }
-    else if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
-    {
-      if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
-      {
-        /* Clear NACK Flag */
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-        hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-      }
-
-      /* Disable Interrupts */
-      I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
-
-      /* Clear STOP Flag */
-      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-      /* Clear Configuration Register 2 */
-      I2C_RESET_CR2(hi2c);
-
-      /* Call the corresponding callback to inform upper layer of End of Transfer */
-      if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
-      {
-        hi2c->PreviousState = I2C_STATE_NONE;
-        hi2c->State = HAL_I2C_STATE_READY;
-        hi2c->Mode = HAL_I2C_MODE_NONE;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        HAL_I2C_ErrorCallback(hi2c);
-      }
-      else
-      {
-        if (hi2c->Mode == HAL_I2C_MODE_MEM)
-        {
-          hi2c->PreviousState = I2C_STATE_NONE;
-          hi2c->State = HAL_I2C_STATE_READY;
-          hi2c->Mode = HAL_I2C_MODE_NONE;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2c);
-      
-          HAL_I2C_MemRxCpltCallback(hi2c);
-        }
-        else
-        {
-          hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
-          hi2c->State = HAL_I2C_STATE_READY;
-          hi2c->Mode = HAL_I2C_MODE_NONE;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2c);
-
-          HAL_I2C_MasterRxCpltCallback(hi2c);
-        }
-      }
-    }
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hi2c);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_Slave_ISR(I2C_HandleTypeDef *hi2c) 
-{
-  uint8_t TransferDirection = 0;
-  uint16_t SlaveAddrCode = 0;
-  uint16_t OwnAdd1Code = 0;
-  uint16_t OwnAdd2Code = 0;
-
-  /* Process locked */
-  __HAL_LOCK(hi2c);
-  
-  if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) != RESET)
-  {
-    /* Check that I2C transfer finished */
-    /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
-    /* Mean XferCount == 0*/
-    /* So clear Flag NACKF only */
-    if(hi2c->XferCount == 0)
-    {
-      if(((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \
-        (hi2c->State == HAL_I2C_STATE_LISTEN))
-      {
-        hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-
-        hi2c->PreviousState = I2C_STATE_NONE;
-        hi2c->State = HAL_I2C_STATE_READY;
-        hi2c->Mode = HAL_I2C_MODE_NONE;
-
-        /* Store Last receive data if any */
-        if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
-        {
-          /* Read data from RXDR */
-          (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
-          hi2c->XferSize--;
-          hi2c->XferCount--;
-        }
-
-        /* Disable all Interrupts*/
-        I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
-
-        /* Clear NACK Flag */
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
-        HAL_I2C_ListenCpltCallback(hi2c);
-      }
-      else if((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN))
-      {
-        /* Last Byte is Transmitted */
-        /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
-        hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
-        hi2c->State = HAL_I2C_STATE_LISTEN;
-        hi2c->Mode = HAL_I2C_MODE_NONE;
-
-        /* Disable all Interrupts*/
-        I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
-
-        /* Clear NACK Flag */
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-        /* Check if TXIS flag is SET */
-        if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
-        {
-          /* Send a dummy data, to clear TXIS event */
-          hi2c->Instance->TXDR = 0x00;
-
-          /* Flush TX register if not empty */
-          if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
-          {
-            __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
-          }
-        }
-        
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        /* Call the Tx complete callback to inform upper layer of the end of transmit process */
-        HAL_I2C_SlaveTxCpltCallback(hi2c);
-      }
-      else
-      {
-        /* Clear NACK Flag */
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-      }
-    }
-    else
-    {
-      /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
-      /* Clear NACK Flag */
-      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-      if(hi2c->XferOptions != I2C_NO_OPTION_FRAME)
-      { 
-        /* Set HAL State to "Idle" State, mean to LISTEN state */
-        /* So reset Slave Busy state */
-        hi2c->PreviousState = I2C_STATE_NONE;
-        hi2c->State = HAL_I2C_STATE_LISTEN;
-        hi2c->Mode = HAL_I2C_MODE_NONE;
-
-        /* Disable RX/TX Interrupts, keep only ADDR Interrupt */
-        I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
-      }
-
-      /* Set ErrorCode corresponding to a Non-Acknowledge */
-      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      /* Call the Error callback to prevent upper layer */
-      HAL_I2C_ErrorCallback(hi2c);
-    }
-  }
-  else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) != RESET)
-  {
-    /* Read data from RXDR */
-    (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
-    hi2c->XferSize--;
-    hi2c->XferCount--;
-
-    if((hi2c->XferCount == 0)&&(hi2c->XferOptions != I2C_NO_OPTION_FRAME))
-    {
-        /* Last Byte is received, disable Interrupt */
-        I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
-
-        /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
-        hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
-        hi2c->State = HAL_I2C_STATE_LISTEN;
-        hi2c->Mode = HAL_I2C_MODE_NONE;
-          
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        /* Call the Rx complete callback to inform upper layer of the end of receive process */
-        HAL_I2C_SlaveRxCpltCallback(hi2c);
-    }
-
-    if((hi2c->XferCount == 0)                     && \
-       (hi2c->XferOptions != I2C_NO_OPTION_FRAME) && \
-       (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))
-    {
-      /* Last Byte is received, disable Interrupt */
-      I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
-
-      /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
-      hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
-      hi2c->State = HAL_I2C_STATE_LISTEN;
-      hi2c->Mode = HAL_I2C_MODE_NONE;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-    }
-  }
-  else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) != RESET)
-  {
-    /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/
-    /* Other ADDRInterrupt will be treat in next Listen usecase */
-    if(hi2c->XferOptions != I2C_NO_OPTION_FRAME)
-    {
-      TransferDirection = I2C_GET_DIR(hi2c);
-      SlaveAddrCode = I2C_GET_ADDR_MATCH(hi2c);
-      OwnAdd1Code = I2C_GET_OWN_ADDRESS1(hi2c);
-      OwnAdd2Code = I2C_GET_OWN_ADDRESS2(hi2c);
-
-      /* If 10bits addressing mode is selected */
-      if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
-      {
-        if((SlaveAddrCode & SlaveAddr_MSK) == ((OwnAdd1Code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))
-        {
-          SlaveAddrCode = OwnAdd1Code;
-          hi2c->AddrEventCount++;
-          if(hi2c->AddrEventCount == 2)
-          {
-            /* Reset Address Event counter  */
-            hi2c->AddrEventCount = 0;
-
-            /* Clear ADDR flag */
-            __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
-
-            /* Process Unlocked */
-            __HAL_UNLOCK(hi2c);
-
-            /* Call Slave Addr callback */
-            HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode);
-          }
-        }
-        else
-        {
-          SlaveAddrCode = OwnAdd2Code;
-
-          /* Disable ADDR Interrupts */
-          I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2c);
-
-          /* Call Slave Addr callback */
-          HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode);
-        }
-      }
-      /* else 7 bits addressing mode is selected */
-      else
-      {
-        /* Disable ADDR Interrupts */
-        I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        /* Call Slave Addr callback */
-        HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode);
-      }
-    }
-    else
-    {
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-    }
-  }
-  else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
-  {
-    /* Write data to TXDR only if XferCount not reach "0" */
-    /* A TXIS flag can be set, during STOP treatment      */
-    /* Check if all Datas have already been sent */
-    /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
-    if(hi2c->XferCount > 0)
-    {
-      /* Write data to TXDR */
-      hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
-      hi2c->XferCount--;
-      hi2c->XferSize--;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-    }
-    else
-    {
-      if(((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME)) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN))
-      {
-        /* Last Byte is Transmitted */
-        /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
-        I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
-        hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
-        hi2c->State = HAL_I2C_STATE_LISTEN;
-        hi2c->Mode = HAL_I2C_MODE_NONE;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        /* Call the Tx complete callback to inform upper layer of the end of transmit process */
-        HAL_I2C_SlaveTxCpltCallback(hi2c);
-      }
-    }
-  }
-
-  /* Check if STOPF is set */
-  if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) != RESET)
-  {
-    /* Disable all interrupts */
-    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
-
-    /* Disable Address Acknowledge */
-    hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
-    /* Clear Configuration Register 2 */
-    I2C_RESET_CR2(hi2c);
-
-    /* Flush TX register if not empty */
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
-    {
-      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
-    }
-
-    /* Store Last receive data if any */
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
-    {
-      /* Read data from RXDR */
-      (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
-      hi2c->XferSize--;
-      hi2c->XferCount--;
-    }
-
-    /* Clear STOP Flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
-
-    hi2c->PreviousState = I2C_STATE_NONE;
-    hi2c->Mode = HAL_I2C_MODE_NONE;
-
-    if(hi2c->XferOptions != I2C_NO_OPTION_FRAME)
-    {
-      hi2c->XferOptions = 0;
-      hi2c->State = HAL_I2C_STATE_READY;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      /* Call the Listen Complete callback, to prevent upper layer of the end of Listen usecase */
-      HAL_I2C_ListenCpltCallback(hi2c);
-    }
-    else
-    {
-      if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
-      {
-        hi2c->State = HAL_I2C_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        /* Call the Slave Rx Complete callback */
-        HAL_I2C_SlaveRxCpltCallback(hi2c);
-      }
-      else
-      {
-        hi2c->State = HAL_I2C_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        /* Call the Slave Tx Complete callback */
-        HAL_I2C_SlaveTxCpltCallback(hi2c);
-      }
-    }
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hi2c);
-
-  return HAL_OK;
-}  
-
-/**
-  * @brief  Master sends target device address followed by internal memory address for write request.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address
-  * @param  MemAddress Internal memory address
-  * @param  MemAddSize Size of internal memory address
-  * @param  Timeout Timeout duration
-  * @param  Tickstart Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
-{
-  I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
-
-  /* Wait until TXIS flag is set */
-  if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
-  {
-    if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* If Memory address size is 8Bit */
-  if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
-  {
-    /* Send Memory Address */
-    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
-  }
-  /* If Memory address size is 16Bit */
-  else
-  {
-    /* Send MSB of Memory Address */
-    hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
-
-    /* Wait until TXIS flag is set */
-    if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-    
-    /* Send LSB of Memory Address */
-    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
-  }
-
-  /* Wait until TCR flag is set */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
-  {
-    return HAL_TIMEOUT;
-  }
-
-return HAL_OK;
-}
-
-/**
-  * @brief  Master sends target device address followed by internal memory address for read request.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address
-  * @param  MemAddress Internal memory address
-  * @param  MemAddSize Size of internal memory address
-  * @param  Timeout Timeout duration
-  * @param  Tickstart Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
-{
-  I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
-
-  /* Wait until TXIS flag is set */
-  if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
-  {
-    if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* If Memory address size is 8Bit */
-  if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
-  {
-    /* Send Memory Address */
-    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
-  }
-  /* If Memory address size is 16Bit */
-  else
-  {
-    /* Send MSB of Memory Address */
-    hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
-
-    /* Wait until TXIS flag is set */
-    if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-    
-    /* Send LSB of Memory Address */
-    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
-  }
-
-  /* Wait until TC flag is set */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
-  {
-    return HAL_TIMEOUT;
-  }
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  DMA I2C master transmit process complete callback.
-  * @param  hdma DMA handle
-  * @retval None
-  */
-static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
-{
-  uint32_t tickstart = 0;
-  uint16_t DevAddress;
-  I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  /* Init tickstart for timeout managment*/
-  tickstart = HAL_GetTick();
-
-  /* Check if last DMA request was done with RELOAD */
-  /* Set NBYTES to write and reload if size > 255 */
-  if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
-  {
-    /* Wait until TCR flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR, tickstart) != HAL_OK)
-    {
-      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-    }
-
-    /* Disable DMA Request */
-    hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
-
-    /* Check if Errors has been detected during transfer */
-    if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
-    {
-      /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
-      /* Wait until STOPF flag is reset */
-      if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF, tickstart) != HAL_OK)
-      {
-        if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-        {
-          hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-        }
-        else
-        {
-          hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-        }
-      }
-
-      /* Clear STOP Flag */
-      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-          
-      /* Clear Configuration Register 2 */
-      I2C_RESET_CR2(hi2c);
-
-      hi2c->XferCount = 0;
-
-      hi2c->State = HAL_I2C_STATE_READY;
-      hi2c->Mode = HAL_I2C_MODE_NONE;
-
-      HAL_I2C_ErrorCallback(hi2c);
-    }
-    else
-    {
-      hi2c->pBuffPtr += hi2c->XferSize;
-      hi2c->XferCount -= hi2c->XferSize;
-      if(hi2c->XferCount > 255)
-      {
-        hi2c->XferSize = 255;
-      }
-      else
-      {
-        hi2c->XferSize = hi2c->XferCount;
-      }
-
-      DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
-
-      /* Send Slave Address */
-      /* Set NBYTES to write and reload if size > 255 */
-      if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
-      {
-        I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
-      }
-      else
-      {
-        I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
-      }
-
-      /* Wait until TXIS flag is set */
-      if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS, tickstart) != HAL_OK)
-      {
-        /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
-        /* Wait until STOPF flag is reset */ 
-        if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF, tickstart) != HAL_OK)
-        {
-          if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-          {
-            hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-          }
-          else
-          {
-            hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-          }
-        }
-
-        /* Clear STOP Flag */
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-        /* Clear Configuration Register 2 */
-        I2C_RESET_CR2(hi2c);
-
-        hi2c->XferCount = 0;
-
-        hi2c->State = HAL_I2C_STATE_READY;
-        hi2c->Mode = HAL_I2C_MODE_NONE;
-
-        HAL_I2C_ErrorCallback(hi2c);
-      }
-      else
-      {
-        /* Enable DMA Request */
-        hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
-      }
-    }
-  }
-  else
-  {
-    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
-    /* Wait until STOPF flag is reset */ 
-    if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF, tickstart) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-      }
-      else
-      {
-        hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-      }
-    }
-
-    /* Clear STOP Flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-    /* Clear Configuration Register 2 */
-    I2C_RESET_CR2(hi2c);
-
-    /* Disable DMA Request */
-    hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; 
-
-    hi2c->XferCount = 0;
-
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode = HAL_I2C_MODE_NONE;
-
-   /* Check if Errors has been detected during transfer */
-    if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
-    {
-      HAL_I2C_ErrorCallback(hi2c);
-    }
-    else
-    {
-      HAL_I2C_MasterTxCpltCallback(hi2c);
-    }
-  }
-}
-
-/**
-  * @brief  DMA I2C slave transmit process complete callback.
-  * @param  hdma DMA handle
-  * @retval None
-  */
-static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
-{
-  uint32_t tickstart = 0;
-  I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  /* Init tickstart for timeout managment*/
-  tickstart = HAL_GetTick();
-
-  /* Wait until STOP flag is set */
-  if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF, tickstart) != HAL_OK)
-  {
-    if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-    {
-      /* Normal Use case, a AF is generated by master */
-      /* to inform slave the end of transfer */
-      hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-    }
-    else
-    {
-      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-    }
-  }
-
-  /* Clear STOP flag */
-  __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
-
-  /* Wait until BUSY flag is reset */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
-  {
-    hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-  }
-
-  /* Disable DMA Request */
-  hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
-
-  hi2c->XferCount = 0;
-
-  hi2c->State = HAL_I2C_STATE_READY;
-  hi2c->Mode = HAL_I2C_MODE_NONE;
-
-  /* Check if Errors has been detected during transfer */
-  if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
-  {
-    HAL_I2C_ErrorCallback(hi2c);
-  }
-  else
-  {
-    HAL_I2C_SlaveTxCpltCallback(hi2c);
-  }
-}
-
-/**
-  * @brief DMA I2C master receive process complete callback.
-  * @param  hdma DMA handle
-  * @retval None
-  */
-static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  uint32_t tickstart = 0;
-  I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-  uint16_t DevAddress;
-
-  /* Init tickstart for timeout managment*/
-  tickstart = HAL_GetTick();
-
-  /* Check if last DMA request was done with RELOAD */
-  /* Set NBYTES to write and reload if size > 255 */
-  if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
-  {
-    /* Wait until TCR flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR, tickstart) != HAL_OK)
-    {
-      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-    }
-
-    /* Disable DMA Request */
-    hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
-
-    /* Check if Errors has been detected during transfer */
-    if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
-    {
-      /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
-      /* Wait until STOPF flag is reset */
-      if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF, tickstart) != HAL_OK)
-      {
-        if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-        {
-          hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-        }
-        else
-        {
-          hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-        }
-      }
-
-      /* Clear STOP Flag */
-      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-      /* Clear Configuration Register 2 */
-      I2C_RESET_CR2(hi2c);
-
-      hi2c->XferCount = 0;
-
-      hi2c->State = HAL_I2C_STATE_READY;
-      hi2c->Mode = HAL_I2C_MODE_NONE;
-
-      HAL_I2C_ErrorCallback(hi2c);
-    }
-    else
-    {
-      hi2c->pBuffPtr += hi2c->XferSize;
-      hi2c->XferCount -= hi2c->XferSize;
-      if(hi2c->XferCount > 255)
-      {
-        hi2c->XferSize = 255;
-      }
-      else
-      {
-        hi2c->XferSize = hi2c->XferCount;
-      }
-
-      DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
-
-      /* Send Slave Address */
-      /* Set NBYTES to write and reload if size > 255 */
-      if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
-      {
-        I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
-      }
-      else
-      {
-        I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
-      }
-
-      /* Wait until RXNE flag is set */
-      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE, tickstart) != HAL_OK)
-      {
-        hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-      }
-
-      /* Check if Errors has been detected during transfer */
-      if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
-      {
-        /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
-        /* Wait until STOPF flag is reset */ 
-        if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF, tickstart) != HAL_OK)
-        {
-          if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-          {
-            hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-          }
-          else
-          {
-            hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-          }
-        }
-
-        /* Clear STOP Flag */
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-        /* Clear Configuration Register 2 */
-        I2C_RESET_CR2(hi2c);
-
-        hi2c->XferCount = 0;
-
-        hi2c->State = HAL_I2C_STATE_READY;
-        hi2c->Mode = HAL_I2C_MODE_NONE;
-
-        HAL_I2C_ErrorCallback(hi2c);
-      }
-      else
-      {
-        /* Enable DMA Request */
-        hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
-      }
-    }
-  }
-  else
-  {
-    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
-    /* Wait until STOPF flag is reset */
-    if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF, tickstart) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-      }
-      else
-      {
-        hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-      }
-    }
-
-    /* Clear STOP Flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-    /* Clear Configuration Register 2 */
-    I2C_RESET_CR2(hi2c);
-
-    /* Disable DMA Request */
-    hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; 
-
-    hi2c->XferCount = 0;
-
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode = HAL_I2C_MODE_NONE;
-
-    /* Check if Errors has been detected during transfer */
-    if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
-    {
-      HAL_I2C_ErrorCallback(hi2c);
-    }
-    else
-    {
-      HAL_I2C_MasterRxCpltCallback(hi2c);
-    }
-  }
-}
-
-/**
-  * @brief  DMA I2C slave receive process complete callback.
-  * @param  hdma DMA handle
-  * @retval None
-  */
-static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  uint32_t tickstart = 0;
-  I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  /* Init tickstart for timeout managment*/
-  tickstart = HAL_GetTick();
-
-  /* Wait until STOPF flag is reset */ 
-  if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF, tickstart) != HAL_OK)
-  {
-    if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-    {
-      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-    }
-    else
-    {
-      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-    }
-  }
-
-  /* Clear STOPF flag */
-  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-  /* Wait until BUSY flag is reset */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
-  {
-    hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-  }
-
-  /* Disable DMA Request */
-  hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
-
-  /* Disable Address Acknowledge */
-  hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
-  hi2c->XferCount = 0;
-
-  hi2c->State = HAL_I2C_STATE_READY;
-  hi2c->Mode = HAL_I2C_MODE_NONE;
-
-  /* Check if Errors has been detected during transfer */
-  if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
-  {
-    HAL_I2C_ErrorCallback(hi2c);
-  }
-  else
-  {
-    HAL_I2C_SlaveRxCpltCallback(hi2c);
-  }
-}
-
-/**
-  * @brief DMA I2C Memory Write process complete callback.
-  * @param hdma DMA handle
-  * @retval None
-  */
-static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma)   
-{
-  uint32_t tickstart = 0;
-  uint16_t DevAddress;
-  I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  /* Init tickstart for timeout managment*/
-  tickstart = HAL_GetTick();
-
-  /* Check if last DMA request was done with RELOAD */
-  /* Set NBYTES to write and reload if size > 255 */
-  if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
-  {
-    /* Wait until TCR flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR, tickstart) != HAL_OK)
-    {
-      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-    }
-
-    /* Disable DMA Request */
-    hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; 
-
-    /* Check if Errors has been detected during transfer */
-    if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
-    {
-      /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
-      /* Wait until STOPF flag is reset */
-      if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF, tickstart) != HAL_OK)
-      {
-        if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-        {
-          hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-        }
-        else
-        {
-          hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-        }
-      }
-
-      /* Clear STOP Flag */
-      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-      /* Clear Configuration Register 2 */
-      I2C_RESET_CR2(hi2c);
-
-      hi2c->XferCount = 0;
-
-      hi2c->State = HAL_I2C_STATE_READY;
-      hi2c->Mode = HAL_I2C_MODE_NONE;
-      HAL_I2C_ErrorCallback(hi2c);
-    }
-    else
-    {
-      hi2c->pBuffPtr += hi2c->XferSize;
-      hi2c->XferCount -= hi2c->XferSize;
-      if(hi2c->XferCount > 255)
-      {
-        hi2c->XferSize = 255;
-      }
-      else
-      {
-        hi2c->XferSize = hi2c->XferCount;
-      }
-
-      DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
-
-      /* Send Slave Address */
-      /* Set NBYTES to write and reload if size > 255 */
-      if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
-      {
-        I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
-      }
-      else
-      {
-        I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
-      }
-
-      /* Wait until TXIS flag is set */
-      if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS, tickstart) != HAL_OK)
-      {
-        /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
-        /* Wait until STOPF flag is reset */
-        if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF, tickstart) != HAL_OK)
-        {
-          if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-          {
-            hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-          }
-          else
-          {
-            hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-          }
-        }
-
-        /* Clear STOP Flag */
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-        /* Clear Configuration Register 2 */
-        I2C_RESET_CR2(hi2c);
-
-        hi2c->XferCount = 0;
-
-        hi2c->State = HAL_I2C_STATE_READY;
-        hi2c->Mode = HAL_I2C_MODE_NONE;
-
-        HAL_I2C_ErrorCallback(hi2c);
-      }
-      else
-      {
-        /* Enable DMA Request */
-        hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
-      }
-    }
-  }
-  else
-  {
-    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
-    /* Wait until STOPF flag is reset */
-    if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF, tickstart) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-      }
-      else
-      {
-        hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-      }
-    }
-
-    /* Clear STOP Flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-    /* Clear Configuration Register 2 */
-    I2C_RESET_CR2(hi2c);
-
-    /* Disable DMA Request */
-    hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
-
-    hi2c->XferCount = 0;
-
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode = HAL_I2C_MODE_NONE;
-
-    /* Check if Errors has been detected during transfer */
-    if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
-    {
-      HAL_I2C_ErrorCallback(hi2c);
-    }
-    else
-    {
-      HAL_I2C_MemTxCpltCallback(hi2c);
-    }
-  }
-}
-
-/**
-  * @brief  DMA I2C Memory Read process complete callback.
-  * @param  hdma DMA handle
-  * @retval None
-  */
-static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  uint32_t tickstart = 0;
-  I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  uint16_t DevAddress;
-
-  /* Init tickstart for timeout managment*/
-  tickstart = HAL_GetTick();
-
-  /* Check if last DMA request was done with RELOAD */
-  /* Set NBYTES to write and reload if size > 255 */
-  if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
-  {
-    /* Wait until TCR flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR, tickstart) != HAL_OK)
-    {
-      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-    }
-
-    /* Disable DMA Request */
-    hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; 
-
-    /* Check if Errors has been detected during transfer */
-    if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
-    {
-      /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
-      /* Wait until STOPF flag is reset */ 
-      if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF, tickstart) != HAL_OK)
-      {
-        if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-        {
-          hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-        }
-        else
-        {
-          hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-        }
-      }
-
-      /* Clear STOP Flag */
-      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-      /* Clear Configuration Register 2 */
-      I2C_RESET_CR2(hi2c);
-
-      hi2c->XferCount = 0;
-
-      hi2c->State = HAL_I2C_STATE_READY;
-      hi2c->Mode = HAL_I2C_MODE_NONE;
-
-      HAL_I2C_ErrorCallback(hi2c);
-    }
-    else
-    {
-      hi2c->pBuffPtr += hi2c->XferSize;
-      hi2c->XferCount -= hi2c->XferSize;
-      if(hi2c->XferCount > 255)
-      {
-        hi2c->XferSize = 255;
-      }
-      else
-      {
-        hi2c->XferSize = hi2c->XferCount;
-      }
-
-      DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
-
-      /* Send Slave Address */
-      /* Set NBYTES to write and reload if size > 255 */
-      if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
-      {
-        I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
-      }
-      else
-      {
-        I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
-      }
-
-      /* Wait until RXNE flag is set */
-      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE, tickstart) != HAL_OK)
-      {
-        hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-      }
-
-      /* Check if Errors has been detected during transfer */
-      if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
-      {
-        /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
-        /* Wait until STOPF flag is reset */
-        if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF, tickstart) != HAL_OK)
-        {
-          if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-          {
-            hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-          }
-          else
-          {
-            hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-          }
-        }
-
-        /* Clear STOP Flag */
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-        /* Clear Configuration Register 2 */
-        I2C_RESET_CR2(hi2c);
-
-        hi2c->XferCount = 0;
-
-        hi2c->State = HAL_I2C_STATE_READY;
-        hi2c->Mode = HAL_I2C_MODE_NONE;
-
-        HAL_I2C_ErrorCallback(hi2c);
-      }
-      else
-      {
-        /* Enable DMA Request */
-        hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
-      }
-    }
-  }
-  else
-  {
-    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
-    /* Wait until STOPF flag is reset */
-    if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF, tickstart) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-      }
-      else
-      {
-        hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-      }
-    }
-  
-    /* Clear STOP Flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-    /* Clear Configuration Register 2 */
-    I2C_RESET_CR2(hi2c);
-
-    /* Disable DMA Request */
-    hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
-
-    hi2c->XferCount = 0;
-
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode = HAL_I2C_MODE_NONE;
-
-    /* Check if Errors has been detected during transfer */
-    if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
-    {
-      HAL_I2C_ErrorCallback(hi2c);
-    }
-    else
-    {
-      HAL_I2C_MemRxCpltCallback(hi2c);
-    }
-  }
-}
-
-/**
-  * @brief  DMA I2C communication error callback.
-  * @param hdma DMA handle
-  * @retval None
-  */
-static void I2C_DMAError(DMA_HandleTypeDef *hdma)
-{
-  I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  /* Disable Acknowledge */
-  hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
-  hi2c->XferCount = 0;
-
-  hi2c->State = HAL_I2C_STATE_READY;
-  hi2c->Mode = HAL_I2C_MODE_NONE;
-
-  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
-
-  HAL_I2C_ErrorCallback(hi2c);
-}
-
-/**
-  * @brief  This function handles I2C Communication Timeout.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  Flag Specifies the I2C flag to check.
-  * @param  Status The new Flag status (SET or RESET).
-  * @param  Timeout Timeout duration
-  * @param  Tickstart Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
-{
-  /* Wait until flag is set */
-  if(Status == RESET)
-  {
-    while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
-    {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0)||((HAL_GetTick() - Tickstart ) > Timeout))
-        {
-          hi2c->State= HAL_I2C_STATE_READY;
-          hi2c->Mode = HAL_I2C_MODE_NONE;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2c);
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  else
-  {
-    while(__HAL_I2C_GET_FLAG(hi2c, Flag) != RESET)
-    {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0)||((HAL_GetTick() - Tickstart ) > Timeout))
-        {
-          hi2c->State= HAL_I2C_STATE_READY;
-          hi2c->Mode = HAL_I2C_MODE_NONE;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2c);
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles I2C Communication Timeout for specific usage of TXIS flag.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  Timeout Timeout duration
-  * @param  Tickstart Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
-{
-  while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
-  {
-    /* Check if a NACK is detected */
-    if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
-    {
-      return HAL_ERROR;
-    }
-
-    /* Check for the Timeout */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout))
-      {
-        hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-        hi2c->State= HAL_I2C_STATE_READY;
-        hi2c->Mode = HAL_I2C_MODE_NONE;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles I2C Communication Timeout for specific usage of STOP flag.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  Timeout Timeout duration
-  * @param  Tickstart Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
-{
-  while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
-  {
-    /* Check if a NACK is detected */
-    if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
-    {
-      return HAL_ERROR;
-    }
-
-    /* Check for the Timeout */
-    if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout))
-    {
-      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-      hi2c->State= HAL_I2C_STATE_READY;
-      hi2c->Mode = HAL_I2C_MODE_NONE;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      return HAL_TIMEOUT;
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles I2C Communication Timeout for specific usage of RXNE flag.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  Timeout Timeout duration
-  * @param  Tickstart Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
-{
-  while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
-  {
-    /* Check if a NACK is detected */
-    if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
-    {
-      return HAL_ERROR;
-    }
-
-    /* Check if a STOPF is detected */
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
-    {
-      /* Clear STOP Flag */
-      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-      /* Clear Configuration Register 2 */
-      I2C_RESET_CR2(hi2c);
-
-      hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-      hi2c->State= HAL_I2C_STATE_READY;
-      hi2c->Mode = HAL_I2C_MODE_NONE;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      return HAL_ERROR;
-    }
-
-    /* Check for the Timeout */
-    if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout))
-    {
-      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-      hi2c->State= HAL_I2C_STATE_READY;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      return HAL_TIMEOUT;
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles Acknowledge failed detection during an I2C Communication.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  Timeout Timeout duration
-  * @param  Tickstart Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
-{
-  if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
-  {
-    /* Wait until STOP Flag is reset */
-    /* AutoEnd should be initiate after AF */
-    while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
-    {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-      if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout))
-        {
-          hi2c->State= HAL_I2C_STATE_READY;
-          hi2c->Mode = HAL_I2C_MODE_NONE;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2c);
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-
-    /* Clear NACKF Flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-    /* Clear STOP Flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-    /* Flush TX register if not empty */
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
-    {
-      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
-    }
-
-    /* Clear Configuration Register 2 */
-    I2C_RESET_CR2(hi2c);
-
-    hi2c->ErrorCode = HAL_I2C_ERROR_AF;
-    hi2c->State= HAL_I2C_STATE_READY;
-    hi2c->Mode = HAL_I2C_MODE_NONE;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_ERROR;
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
-  * @param  hi2c I2C handle.
-  * @param  DevAddress Specifies the slave address to be programmed.
-  * @param  Size Specifies the number of bytes to be programmed.
-  *   This parameter must be a value between 0 and 255.
-  * @param  Mode New state of the I2C START condition generation.
-  *   This parameter can be one of the following values:
-  *     @arg @ref I2C_RELOAD_MODE Enable Reload mode .
-  *     @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.
-  *     @arg @ref I2C_SOFTEND_MODE Enable Software end mode.
-  * @param  Request New state of the I2C START condition generation.
-  *   This parameter can be one of the following values:
-  *     @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.
-  *     @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
-  *     @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
-  *     @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
-  * @retval None
-  */
-static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c,  uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
-  assert_param(IS_TRANSFER_MODE(Mode));
-  assert_param(IS_TRANSFER_REQUEST(Request));
-
-  /* Get the CR2 register value */
-  tmpreg = hi2c->Instance->CR2;
-
-  /* clear tmpreg specific bits */
-  tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP));
-
-  /* update tmpreg */
-  tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \
-            (uint32_t)Mode | (uint32_t)Request);
-
-  /* update CR2 register */
-  hi2c->Instance->CR2 = tmpreg;
-}
-
-/**
-  * @brief  Manage the enabling of Interrupts.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
-{
-  uint32_t tmpisr = 0;
-
-  if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
-  {
-    /* Enable ADDR and STOP interrupt */
-    tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
-  }
-
-  if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
-  {
-    /* Enable ERR, TC, STOP, NACK and RXI interrupt */
-    tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
-  }
-
-  if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
-  {
-    /* Enable ERR, TC, STOP, NACK and TXI interrupt */
-    tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
-  }
-
-  /* Enable interrupts only at the end */
-  /* to avoid the risk of I2C interrupt handle execution before */
-  /* all interrupts requested done */
-  __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Manage the disabling of Interrupts.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
-{
-  uint32_t tmpisr = 0;
-
-  if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
-  {
-    /* Disable TC and TXI interrupts */
-    tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
-
-    if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
-    {
-      /* Disable NACK and STOP interrupts */
-      tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
-    }
-  }
-
-  if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
-  {
-    /* Disable TC and RXI interrupts */
-    tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
-
-    if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
-    {
-      /* Disable NACK and STOP interrupts */
-      tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
-    }
-  }
-
-  if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
-  {
-    /* Disable ADDR, NACK and STOP interrupts */
-    tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
-  }
-
-  /* Disable interrupts only at the end */
-  /* to avoid a breaking situation like at "t" time */
-  /* all disable interrupts request are not done */
-  __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_I2C_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/src/stm32l4xx_hal_i2c_ex.c b/stmhal/hal/l4/src/stm32l4xx_hal_i2c_ex.c
deleted file mode 100644
index c3f9156d3e..0000000000
--- a/stmhal/hal/l4/src/stm32l4xx_hal_i2c_ex.c
+++ /dev/null
@@ -1,350 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_i2c_ex.c
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   I2C Extended HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of I2C Extended peripheral:
-  *           + Extended features functions
-  *
-  @verbatim
-  ==============================================================================
-               ##### I2C peripheral Extended features  #####
-  ==============================================================================
-
-  [..] Comparing to other previous devices, the I2C interface for STM32L4xx
-       devices contains the following additional features
-
-       (+) Possibility to disable or enable Analog Noise Filter
-       (+) Use of a configured Digital Noise Filter
-       (+) Disable or enable wakeup from Stop modes
-
-                     ##### How to use this driver #####
-  ==============================================================================
-  [..] This driver provides functions to configure Noise Filter and Wake Up Feature
-    (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
-    (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
-    (#) Configure the enable or disable of I2C Wake Up Mode using the functions :
-          (++) HAL_I2CEx_EnableWakeUp()
-          (++) HAL_I2CEx_DisableWakeUp()
-    (#) Configure the enable or disable of fast mode plus driving capability using the functions :
-          (++) HAL_I2CEx_EnableFastModePlus()
-          (++) HAL_I2CEx_DisbleFastModePlus()
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup I2CEx I2CEx
-  * @brief I2C Extended HAL module driver
-  * @{
-  */
-
-#ifdef HAL_I2C_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
-  * @{
-  */
-
-/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions
-  * @brief    Extended features functions
- *
-@verbatim
- ===============================================================================
-                      ##### Extended features functions #####
- ===============================================================================
-    [..] This section provides functions allowing to:
-      (+) Configure Noise Filters 
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configure I2C Analog noise filter.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2Cx peripheral.
-  * @param  AnalogFilter New state of the Analog filter.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
-  assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_BUSY;
-
-    /* Disable the selected I2C peripheral */
-    __HAL_I2C_DISABLE(hi2c);
-
-    /* Reset I2Cx ANOFF bit */
-    hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
-
-    /* Set analog filter bit*/
-    hi2c->Instance->CR1 |= AnalogFilter;
-
-    __HAL_I2C_ENABLE(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Configure I2C Digital noise filter.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2Cx peripheral.
-  * @param  DigitalFilter Coefficient of digital noise filter between 0x00 and 0x0F.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
-  assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_BUSY;
-
-    /* Disable the selected I2C peripheral */
-    __HAL_I2C_DISABLE(hi2c);
-
-    /* Get the old register value */
-    tmpreg = hi2c->Instance->CR1;
-
-    /* Reset I2Cx DNF bits [11:8] */
-    tmpreg &= ~(I2C_CR1_DNF);
-
-    /* Set I2Cx DNF coefficient */
-    tmpreg |= DigitalFilter << 8;
-
-    /* Store the new register value */
-    hi2c->Instance->CR1 = tmpreg;
-
-    __HAL_I2C_ENABLE(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-/**
-  * @brief  Enable I2C wakeup from stop mode.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2Cx peripheral.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_BUSY;
-
-    /* Disable the selected I2C peripheral */
-    __HAL_I2C_DISABLE(hi2c);
-
-    /* Enable wakeup from stop mode */
-    hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
-
-    __HAL_I2C_ENABLE(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-
-/**
-  * @brief  Disable I2C wakeup from stop mode.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2Cx peripheral.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_BUSY;
-
-    /* Disable the selected I2C peripheral */
-    __HAL_I2C_DISABLE(hi2c);
-
-    /* Enable wakeup from stop mode */
-    hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
-
-    __HAL_I2C_ENABLE(hi2c); 
-
-    hi2c->State = HAL_I2C_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Enable the I2C fast mode plus driving capability.
-  * @param ConfigFastModePlus Selects the pin.
-  *   This parameter can be one of the @ref I2CEx_FastModePlus values
-  * @note  For I2C1, fast mode plus driving capability can be enabled on all selected
-  *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
-  *        on each one of the following pins PB6, PB7, PB8 and PB9.
-  * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
-  *        can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
-  * @note  For all I2C2 pins fast mode plus driving capability can be enabled
-  *        only by using I2C_FASTMODEPLUS_I2C2 parameter.
-  * @note  For all I2C3 pins fast mode plus driving capability can be enabled
-  *        only by using I2C_FASTMODEPLUS_I2C3 parameter.
-  * @retval None
-  */
-void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
-{
-  /* Check the parameter */
-  assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
-
-  /* Enable SYSCFG clock */
-  __HAL_RCC_SYSCFG_CLK_ENABLE();
-
-  /* Enable fast mode plus driving capability for selected pin */
-  SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
-}
-
-/**
-  * @brief Disable the I2C fast mode plus driving capability.
-  * @param ConfigFastModePlus Selects the pin.
-  *   This parameter can be one of the @ref I2CEx_FastModePlus values
-  * @note  For I2C1, fast mode plus driving capability can be disabled on all selected
-  *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
-  *        on each one of the following pins PB6, PB7, PB8 and PB9.
-  * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
-  *        can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
-  * @note  For all I2C2 pins fast mode plus driving capability can be disabled
-  *        only by using I2C_FASTMODEPLUS_I2C2 parameter.
-  * @note  For all I2C3 pins fast mode plus driving capability can be disabled
-  *        only by using I2C_FASTMODEPLUS_I2C3 parameter.
-  * @retval None
-  */
-void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
-{
-  /* Check the parameter */
-  assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
-
-  /* Enable SYSCFG clock */
-  __HAL_RCC_SYSCFG_CLK_ENABLE();
-
-  /* Disable fast mode plus driving capability for selected pin */
-  CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_I2C_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/src/stm32l4xx_hal_pcd.c b/stmhal/hal/l4/src/stm32l4xx_hal_pcd.c
deleted file mode 100644
index f39dfe38ee..0000000000
--- a/stmhal/hal/l4/src/stm32l4xx_hal_pcd.c
+++ /dev/null
@@ -1,1255 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_pcd.c
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   PCD HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the USB Peripheral Controller:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions 
-  *           + Peripheral State functions
-  *         
-  @verbatim
-  ==============================================================================
-                    ##### How to use this driver #####
-  ==============================================================================
-    [..]
-      The PCD HAL driver can be used as follows:
-
-     (#) Declare a PCD_HandleTypeDef handle structure, for example:
-         PCD_HandleTypeDef  hpcd;
-        
-     (#) Fill parameters of Init structure in HCD handle
-  
-     (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...) 
-
-     (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
-         (##) Enable the PCD/USB Low Level interface clock using 
-              (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
-         (##) Initialize the related GPIO clocks
-         (##) Configure PCD pin-out
-         (##) Configure PCD NVIC interrupt
-    
-     (#)Associate the Upper USB device stack to the HAL PCD Driver:
-         (##) hpcd.pData = pdev;
-
-     (#)Enable PCD transmission and reception:
-         (##) HAL_PCD_Start();
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-#if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup PCD PCD
-  * @brief PCD HAL module driver
-  * @{
-  */
-
-#ifdef HAL_PCD_MODULE_ENABLED
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup PCD_Private_Macros PCD Private Macros
-  * @{
-  */
-#define PCD_MIN(a, b)  (((a) < (b)) ? (a) : (b))
-#define PCD_MAX(a, b)  (((a) > (b)) ? (a) : (b))
-/**
-  * @}
-  */
-
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup PCD_Private_Functions PCD Private Functions
-  * @{
-  */
-static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup PCD_Exported_Functions PCD Exported Functions
-  * @{
-  */
-
-/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions 
- *
-@verbatim
- ===============================================================================
-            ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-     
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the PCD according to the specified
-  *         parameters in the PCD_InitTypeDef and initialize the associated handle.
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
-{ 
-  uint32_t i = 0;
-  
-  /* Check the PCD handle allocation */
-  if(hpcd == NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  /* Check the parameters */
-  assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
-  
-  if(hpcd->State == HAL_PCD_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hpcd->Lock = HAL_UNLOCKED;
-
-    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
-    HAL_PCD_MspInit(hpcd);
-  }
-
-  hpcd->State = HAL_PCD_STATE_BUSY;
-
-  /* Disable the Interrupts */
-  __HAL_PCD_DISABLE(hpcd);
-
-  /*Init the Core (common init.) */
-  USB_CoreInit(hpcd->Instance, hpcd->Init);
-
-  /* Force Device Mode*/
-  USB_SetCurrentMode(hpcd->Instance , USB_OTG_DEVICE_MODE);
-
-  /* Init endpoints structures */
-  for (i = 0; i < hpcd->Init.dev_endpoints ; i++)
-  {
-    /* Init ep structure */
-    hpcd->IN_ep[i].is_in = 1;
-    hpcd->IN_ep[i].num = i;
-    hpcd->IN_ep[i].tx_fifo_num = i;
-    /* Control until ep is activated */
-    hpcd->IN_ep[i].type = EP_TYPE_CTRL;
-    hpcd->IN_ep[i].maxpacket =  0;
-    hpcd->IN_ep[i].xfer_buff = 0;
-    hpcd->IN_ep[i].xfer_len = 0;
-  }
- 
-  for (i = 0; i < hpcd->Init.dev_endpoints ; i++)
-  {
-    hpcd->OUT_ep[i].is_in = 0;
-    hpcd->OUT_ep[i].num = i;
-    hpcd->IN_ep[i].tx_fifo_num = i;
-    /* Control until ep is activated */
-    hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
-    hpcd->OUT_ep[i].maxpacket = 0;
-    hpcd->OUT_ep[i].xfer_buff = 0;
-    hpcd->OUT_ep[i].xfer_len = 0;
-
-    hpcd->Instance->DIEPTXF[i] = 0;
-  }
-
-  /* Init Device */
-  USB_DevInit(hpcd->Instance, hpcd->Init);
-
-  hpcd->State= HAL_PCD_STATE_READY;
-  
-   /* Activate LPM */
-  if (hpcd->Init.lpm_enable ==1)
-  {
-    HAL_PCDEx_ActivateLPM(hpcd);
-  }  
-  /* Activate Battery charging */
-  if (hpcd->Init.battery_charging_enable ==1)
-  {
-    HAL_PCDEx_ActivateBCD(hpcd);
-  }
-  USB_DevDisconnect (hpcd->Instance);  
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the PCD peripheral.
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
-{
-  /* Check the PCD handle allocation */
-  if(hpcd == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  hpcd->State = HAL_PCD_STATE_BUSY;
-  
-  /* Stop Device */
-  HAL_PCD_Stop(hpcd);
-    
-  /* DeInit the low level hardware */
-  HAL_PCD_MspDeInit(hpcd);
-  
-  hpcd->State = HAL_PCD_STATE_RESET; 
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the PCD MSP.
-  * @param  hpcd: PCD handle
-  * @retval None
-  */
-__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCD_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes PCD MSP.
-  * @param  hpcd: PCD handle
-  * @retval None
-  */
-__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCD_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions 
- *  @brief   Data transfers functions 
- *
-@verbatim   
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================  
-    [..]
-    This subsection provides a set of functions allowing to manage the PCD data 
-    transfers.
-
-@endverbatim
-  * @{
-  */
-  
-/**
-  * @brief  Start The USB OTG Device.
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
-{ 
-  __HAL_LOCK(hpcd); 
-  USB_DevConnect (hpcd->Instance);  
-  __HAL_PCD_ENABLE(hpcd);
-  __HAL_UNLOCK(hpcd); 
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stop The USB OTG Device.
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
-{ 
-  __HAL_LOCK(hpcd); 
-  __HAL_PCD_DISABLE(hpcd);
-  USB_StopDevice(hpcd->Instance);
-  USB_DevDisconnect (hpcd->Instance);
-  __HAL_UNLOCK(hpcd); 
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handles PCD interrupt request.
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
-{
-  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
-  uint32_t i = 0, ep_intr = 0, epint = 0, epnum = 0;
-  uint32_t fifoemptymsk = 0, temp = 0;
-  USB_OTG_EPTypeDef *ep;
-  
-  /* ensure that we are in device mode */
-  if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
-  {
-    /* avoid spurious interrupt */
-    if(__HAL_PCD_IS_INVALID_INTERRUPT(hpcd)) 
-    {
-      return;
-    }
-    
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))
-    {
-      /* incorrect mode, acknowledge the interrupt */
-      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);
-    }
-    
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
-    {
-      epnum = 0;
-      
-      /* Read in the device interrupt bits */
-      ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance);
-      
-      while ( ep_intr )
-      {
-        if (ep_intr & 0x1)
-        {
-          epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, epnum);
-          
-          if(( epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)
-          {
-            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC);
-            
-            if ((( (USBx_OUTEP(0)->DOEPINT & 0x8000) == 0)) )
-            {
-              
-              if(hpcd->Init.dma_enable == 1)
-              {
-                hpcd->OUT_ep[epnum].xfer_count = hpcd->OUT_ep[epnum].maxpacket- (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); 
-                hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket;            
-              }
-              
-              HAL_PCD_DataOutStageCallback(hpcd, epnum);
-              
-              if(hpcd->Init.dma_enable == 1)
-              {
-                if((epnum == 0) && (hpcd->OUT_ep[epnum].xfer_len == 0))
-                {
-                  /* this is ZLP, so prepare EP0 for next setup */
-                  USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup);
-                }              
-              }
-            }
-            /* Clear the SetPktRcvd flag*/ 
-            USBx_OUTEP(0)->DOEPINT |= 0x8020;
-          }
-          
-          if(( epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
-          {
-            /* Inform the upper layer that a setup packet is available */
-            HAL_PCD_SetupStageCallback(hpcd);
-            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
-          }
-          
-          if(( epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)
-          {
-            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);
-          }
-        }
-        epnum++;
-        ep_intr >>= 1;
-      }
-    }
-    
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))
-    {
-      /* Read in the device interrupt bits */
-      ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance);
-      
-      epnum = 0;
-      
-      while ( ep_intr )
-      {
-        if (ep_intr & 0x1) /* In ITR */
-        {
-          epint = USB_ReadDevInEPInterrupt(hpcd->Instance, epnum);
-          
-          if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)
-          {
-            fifoemptymsk = 0x1 << epnum;
-            USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
-            
-            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);
-            
-            if (hpcd->Init.dma_enable == 1)
-            {
-              hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket; 
-            }
-            
-            HAL_PCD_DataInStageCallback(hpcd, epnum);
-            
-            if (hpcd->Init.dma_enable == 1)
-            {
-              /* this is ZLP, so prepare EP0 for next setup */
-              if((epnum == 0) && (hpcd->IN_ep[epnum].xfer_len == 0))
-              {
-                /* prepare to rx more setup packets */
-                USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup);
-              }
-            }           
-          }
-          if(( epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)
-          {
-            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC);
-          }
-          if(( epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE)
-          {
-            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE);
-          }
-          if(( epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE)
-          {
-            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE);
-          }
-          if(( epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)
-          {
-            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);
-          }       
-          if(( epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)
-          {
-            PCD_WriteEmptyTxFifo(hpcd , epnum);
-          }
-        }
-        epnum++;
-        ep_intr >>= 1;
-      }
-    }
-    
-    /* Handle Resume Interrupt */
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))
-    {    
-      /* Clear the Remote Wake-up Signaling */
-      USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
-      
-      if(hpcd->LPM_State == LPM_L1)
-      {
-        hpcd->LPM_State = LPM_L0;
-        HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);
-      }
-      else
-      {
-        HAL_PCD_ResumeCallback(hpcd);
-      }
-      
-      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);
-    }
-    
-    /* Handle Suspend Interrupt */
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
-    {
-      if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
-      {
-        
-        HAL_PCD_SuspendCallback(hpcd);
-      }
-      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
-    }
-    
-    /* Handle LPM Interrupt */ 
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT))
-    {
-      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT);      
-      if( hpcd->LPM_State == LPM_L0)
-      {   
-        hpcd->LPM_State = LPM_L1;
-        hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >>2 ;  
-        HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
-      }
-      else
-      {
-        HAL_PCD_SuspendCallback(hpcd);
-      }
-    }
-    
-    /* Handle Reset Interrupt */
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
-    {
-      USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; 
-      USB_FlushTxFifo(hpcd->Instance ,  0 );
-      
-      for (i = 0; i < hpcd->Init.dev_endpoints ; i++)
-      {
-        USBx_INEP(i)->DIEPINT = 0xFF;
-        USBx_OUTEP(i)->DOEPINT = 0xFF;
-      }
-      USBx_DEVICE->DAINT = 0xFFFFFFFF;
-      USBx_DEVICE->DAINTMSK |= 0x10001;
-      
-      if(hpcd->Init.use_dedicated_ep1)
-      {
-        USBx_DEVICE->DOUTEP1MSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM); 
-        USBx_DEVICE->DINEP1MSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);  
-      }
-      else
-      {
-        USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM);
-        USBx_DEVICE->DIEPMSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);
-      }
-      
-      /* Set Default Address to 0 */
-      USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD;
-      
-      /* setup EP0 to receive SETUP packets */
-      USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
-      
-      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);
-    }
-    
-    /* Handle Enumeration done Interrupt */
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))
-    {
-      USB_ActivateSetup(hpcd->Instance);
-      hpcd->Instance->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
-      
-      hpcd->Init.speed            = USB_OTG_SPEED_FULL;
-      hpcd->Init.ep0_mps          = USB_OTG_FS_MAX_PACKET_SIZE ;  
-      hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_FS_TRDT_VALUE << 10) & USB_OTG_GUSBCFG_TRDT);
-      
-      HAL_PCD_ResetCallback(hpcd);
-      
-      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
-    }
-    
-    /* Handle RxQLevel Interrupt */
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
-    {
-      USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
-      
-      temp = USBx->GRXSTSP;
-      
-      ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];
-      
-      if(((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) ==  STS_DATA_UPDT)
-      {
-        if((temp & USB_OTG_GRXSTSP_BCNT) != 0)
-        {
-          USB_ReadPacket(USBx, ep->xfer_buff, (temp & USB_OTG_GRXSTSP_BCNT) >> 4);
-          ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
-          ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
-        }
-      }
-      else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) ==  STS_SETUP_UPDT)
-      {
-        USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8);
-        ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
-      }
-      USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
-    }
-    
-    /* Handle SOF Interrupt */
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
-    {
-      HAL_PCD_SOFCallback(hpcd);
-      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);
-    }
-    
-    /* Handle Incomplete ISO IN Interrupt */
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
-    {
-      HAL_PCD_ISOINIncompleteCallback(hpcd, epnum);
-      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);
-    } 
-    
-    /* Handle Incomplete ISO OUT Interrupt */
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
-    {
-      HAL_PCD_ISOOUTIncompleteCallback(hpcd, epnum);
-      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
-    } 
-    
-    /* Handle Connection event Interrupt */
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))
-    {
-      HAL_PCD_ConnectCallback(hpcd);
-      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT);
-    } 
-    
-    /* Handle Disconnection event Interrupt */
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))
-    {
-      temp = hpcd->Instance->GOTGINT;
-      
-      if((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)
-      {
-        HAL_PCD_DisconnectCallback(hpcd);
-      }
-      hpcd->Instance->GOTGINT |= temp;
-    }
-  }
-}
-
-/**
-  * @brief  Data OUT stage callback.
-  * @param  hpcd: PCD handle
-  * @param  epnum: endpoint number
-  * @retval None
-  */
-__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-  UNUSED(epnum);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCD_DataOutStageCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  Data IN stage callback.
-  * @param  hpcd: PCD handle
-  * @param  epnum: endpoint number
-  * @retval None
-  */
-__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-  UNUSED(epnum);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCD_DataInStageCallback could be implemented in the user file
-   */ 
-}
-/**
-  * @brief  Setup stage callback.
-  * @param  hpcd: PCD handle
-  * @retval None
-  */
-__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCD_SetupStageCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  USB Start Of Frame callback.
-  * @param  hpcd: PCD handle
-  * @retval None
-  */
-__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCD_SOFCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  USB Reset callback.
-  * @param  hpcd: PCD handle
-  * @retval None
-  */
-__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCD_ResetCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  Suspend event callback.
-  * @param  hpcd: PCD handle
-  * @retval None
-  */
-__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCD_SuspendCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  Resume event callback.
-  * @param  hpcd: PCD handle
-  * @retval None
-  */
-__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCD_ResumeCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  Incomplete ISO OUT callback.
-  * @param  hpcd: PCD handle
-  * @param  epnum: endpoint number
-  * @retval None
-  */
-__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-  UNUSED(epnum);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  Incomplete ISO IN callback.
-  * @param  hpcd: PCD handle
-  * @param  epnum: endpoint number
-  * @retval None
-  */
-__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-  UNUSED(epnum);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  Connection event callback.
-  * @param  hpcd: PCD handle
-  * @retval None
-  */
-__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCD_ConnectCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  Disconnection event callback.
-  * @param  hpcd: PCD handle
-  * @retval None
-  */
-__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCD_DisconnectCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-  
-/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions 
- *  @brief   management functions 
- *
-@verbatim   
- ===============================================================================
-                      ##### Peripheral Control functions #####
- ===============================================================================  
-    [..]
-    This subsection provides a set of functions allowing to control the PCD data 
-    transfers.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Connect the USB device.
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
-{
-  __HAL_LOCK(hpcd); 
-  USB_DevConnect(hpcd->Instance);
-  __HAL_UNLOCK(hpcd); 
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disconnect the USB device.
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
-{
-  __HAL_LOCK(hpcd); 
-  USB_DevDisconnect(hpcd->Instance);
-  __HAL_UNLOCK(hpcd); 
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set the USB Device address.
-  * @param  hpcd: PCD handle
-  * @param  address: new device address
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
-{
-  __HAL_LOCK(hpcd); 
-  USB_SetDevAddress(hpcd->Instance, address);
-  __HAL_UNLOCK(hpcd);   
-  return HAL_OK;
-}
-/**
-  * @brief  Open and configure an endpoint.
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
-  * @param  ep_mps: endpoint max packet size
-  * @param  ep_type: endpoint type   
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
-{
-  HAL_StatusTypeDef  ret = HAL_OK;
-  USB_OTG_EPTypeDef *ep;
-  
-  if ((ep_addr & 0x80) == 0x80)
-  {
-    ep = &hpcd->IN_ep[ep_addr & 0x7F];
-  }
-  else
-  {
-    ep = &hpcd->OUT_ep[ep_addr & 0x7F];
-  }
-  ep->num   = ep_addr & 0x7F;
-  
-  ep->is_in = (0x80 & ep_addr) != 0;
-  ep->maxpacket = ep_mps;
-  ep->type = ep_type;
-  if (ep->is_in)
-  {
-    /* Assign a Tx FIFO */
-    ep->tx_fifo_num = ep->num;
-  }
-  /* Set initial data PID. */
-  if (ep_type == EP_TYPE_BULK )
-  {
-    ep->data_pid_start = 0;
-  }
-  
-  __HAL_LOCK(hpcd); 
-  USB_ActivateEndpoint(hpcd->Instance , ep);
-  __HAL_UNLOCK(hpcd);   
-  return ret;
-}
-
-
-/**
-  * @brief  Deactivate an endpoint.
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{  
-  USB_OTG_EPTypeDef *ep;
-  
-  if ((ep_addr & 0x80) == 0x80)
-  {
-    ep = &hpcd->IN_ep[ep_addr & 0x7F];
-  }
-  else
-  {
-    ep = &hpcd->OUT_ep[ep_addr & 0x7F];
-  }
-  ep->num   = ep_addr & 0x7F;
-  
-  ep->is_in = (0x80 & ep_addr) != 0;
-  
-  __HAL_LOCK(hpcd); 
-  USB_DeactivateEndpoint(hpcd->Instance , ep);
-  __HAL_UNLOCK(hpcd);   
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  Receive an amount of data.
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
-  * @param  pBuf: pointer to the reception buffer   
-  * @param  len: amount of data to be received
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
-{
-  USB_OTG_EPTypeDef *ep;
-  
-  ep = &hpcd->OUT_ep[ep_addr & 0x7F];
-  
-  /*setup and start the Xfer */
-  ep->xfer_buff = pBuf;  
-  ep->xfer_len = len;
-  ep->xfer_count = 0;
-  ep->is_in = 0;
-  ep->num = ep_addr & 0x7F;
-  
-  if (hpcd->Init.dma_enable == 1)
-  {
-    ep->dma_addr = (uint32_t)pBuf;  
-  }
-  
-  __HAL_LOCK(hpcd); 
-  
-  if ((ep_addr & 0x7F) == 0 )
-  {
-    USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
-  }
-  else
-  {
-    USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
-  }
-  __HAL_UNLOCK(hpcd); 
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Get Received Data Size.
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
-  * @retval Data Size
-  */
-uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
-  return hpcd->OUT_ep[ep_addr & 0x7F].xfer_count;
-}
-/**
-  * @brief  Send an amount of data.
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
-  * @param  pBuf: pointer to the transmission buffer   
-  * @param  len: amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
-{
-  USB_OTG_EPTypeDef *ep;
-  
-  ep = &hpcd->IN_ep[ep_addr & 0x7F];
-  
-  /*setup and start the Xfer */
-  ep->xfer_buff = pBuf;  
-  ep->xfer_len = len;
-  ep->xfer_count = 0;
-  ep->is_in = 1;
-  ep->num = ep_addr & 0x7F;
-  
-  if (hpcd->Init.dma_enable == 1)
-  {
-    ep->dma_addr = (uint32_t)pBuf;  
-  }
-  
-  __HAL_LOCK(hpcd); 
-  
-  if ((ep_addr & 0x7F) == 0 )
-  {
-    USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
-  }
-  else
-  {
-    USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
-  }
-  
-  __HAL_UNLOCK(hpcd);
-     
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set a STALL condition over an endpoint.
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
-  USB_OTG_EPTypeDef *ep;
-  
-  if ((0x80 & ep_addr) == 0x80)
-  {
-    ep = &hpcd->IN_ep[ep_addr & 0x7F];
-  }
-  else
-  {
-    ep = &hpcd->OUT_ep[ep_addr];
-  }
-  
-  ep->is_stall = 1;
-  ep->num   = ep_addr & 0x7F;
-  ep->is_in = ((ep_addr & 0x80) == 0x80);
-  
-  
-  __HAL_LOCK(hpcd); 
-  USB_EPSetStall(hpcd->Instance , ep);
-  if((ep_addr & 0x7F) == 0)
-  {
-    USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
-  }
-  __HAL_UNLOCK(hpcd); 
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Clear a STALL condition over in an endpoint.
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
-  USB_OTG_EPTypeDef *ep;
-  
-  if ((0x80 & ep_addr) == 0x80)
-  {
-    ep = &hpcd->IN_ep[ep_addr & 0x7F];
-  }
-  else
-  {
-    ep = &hpcd->OUT_ep[ep_addr];
-  }
-  
-  ep->is_stall = 0;
-  ep->num   = ep_addr & 0x7F;
-  ep->is_in = ((ep_addr & 0x80) == 0x80);
-  
-  __HAL_LOCK(hpcd); 
-  USB_EPClearStall(hpcd->Instance , ep);
-  __HAL_UNLOCK(hpcd); 
-    
-  return HAL_OK;
-}
-
-/**
-  * @brief  Flush an endpoint.
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
-  __HAL_LOCK(hpcd); 
-  
-  if ((ep_addr & 0x80) == 0x80)
-  {
-    USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7F);
-  }
-  else
-  {
-    USB_FlushRxFifo(hpcd->Instance);
-  }
-  
-  __HAL_UNLOCK(hpcd); 
-    
-  return HAL_OK;
-}
-
-/**
-  * @brief  Activate remote wakeup signalling.
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
-{
-  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;  
-    
-  if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
-  {
-    /* Activate Remote wakeup signaling */
-    USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;
-  }
-  return HAL_OK;  
-}
-
-/**
-  * @brief  De-activate remote wakeup signalling.
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
-{
-  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;  
-  
-  /* De-activate Remote wakeup signaling */
-   USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);
-  return HAL_OK;  
-}
-/**
-  * @}
-  */
-  
-/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions 
- *  @brief   Peripheral State functions 
- *
-@verbatim   
- ===============================================================================
-                      ##### Peripheral State functions #####
- ===============================================================================  
-    [..]
-    This subsection permits to get in run-time the status of the peripheral 
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the PCD handle state.
-  * @param  hpcd: PCD handle
-  * @retval HAL state
-  */
-PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
-{
-  return hpcd->State;
-}
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @addtogroup PCD_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Check FIFO for the next packet to be loaded.
-  * @param  hpcd: PCD handle
-  * @param  epnum: endpoint number
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)
-{
-  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;  
-  USB_OTG_EPTypeDef *ep;
-  int32_t len = 0;
-  uint32_t len32b;
-  uint32_t fifoemptymsk = 0;
-
-  ep = &hpcd->IN_ep[epnum];
-  len = ep->xfer_len - ep->xfer_count;
-  
-  if (len > ep->maxpacket)
-  {
-    len = ep->maxpacket;
-  }
-  
-  
-  len32b = (len + 3) / 4;
- 
-  while  ( (USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b &&
-          ep->xfer_count < ep->xfer_len &&
-            ep->xfer_len != 0)
-  {
-    /* Write the FIFO */
-    len = ep->xfer_len - ep->xfer_count;
-    
-    if (len > ep->maxpacket)
-    {
-      len = ep->maxpacket;
-    }
-    len32b = (len + 3) / 4;
-    
-    USB_WritePacket(USBx, ep->xfer_buff, epnum, len, hpcd->Init.dma_enable); 
-    
-    ep->xfer_buff  += len;
-    ep->xfer_count += len;
-  }
-  
-  if(len <= 0)
-  {
-    fifoemptymsk = 0x1 << epnum;
-    USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
-    
-  }
-  
-  return HAL_OK;  
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_PCD_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/src/stm32l4xx_hal_pcd_ex.c b/stmhal/hal/l4/src/stm32l4xx_hal_pcd_ex.c
deleted file mode 100644
index 29a85da6a4..0000000000
--- a/stmhal/hal/l4/src/stm32l4xx_hal_pcd_ex.c
+++ /dev/null
@@ -1,323 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_pcd_ex.c
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   PCD Extended HAL module driver.  
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the USB Peripheral Controller:
-  *           + Extended features functions
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-#if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup PCDEx PCDEx
-  * @brief PCD Extended HAL module driver
-  * @{
-  */
-#ifdef HAL_PCD_MODULE_ENABLED
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
-  * @{
-  */
-  
-/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
-  * @brief    PCDEx control functions 
- *
-@verbatim   
- ===============================================================================
-                 ##### Extended features functions #####
- ===============================================================================  
-    [..]  This section provides functions allowing to:
-      (+) Update FIFO configuration
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Set Tx FIFO
-  * @param  hpcd: PCD handle
-  * @param  fifo: The number of Tx fifo
-  * @param  size: Fifo size
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
-{
-  uint8_t i = 0;
-  uint32_t Tx_Offset = 0;
-
-  /*  TXn min size = 16 words. (n  : Transmit FIFO index)
-      When a TxFIFO is not used, the Configuration should be as follows: 
-          case 1 :  n > m    and Txn is not used    (n,m  : Transmit FIFO indexes)
-         --> Txm can use the space allocated for Txn.
-         case2  :  n < m    and Txn is not used    (n,m  : Transmit FIFO indexes)
-         --> Txn should be configured with the minimum space of 16 words
-     The FIFO is used optimally when used TxFIFOs are allocated in the top 
-         of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
-     When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
-  
-  Tx_Offset = hpcd->Instance->GRXFSIZ;
-  
-  if(fifo == 0)
-  {
-    hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (size << 16) | Tx_Offset;
-  }
-  else
-  {
-    Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;
-    for (i = 0; i < (fifo - 1); i++)
-    {
-      Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);
-    }
-    
-    /* Multiply Tx_Size by 2 to get higher performance */
-    hpcd->Instance->DIEPTXF[fifo - 1] = (size << 16) | Tx_Offset;
-  }
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set Rx FIFO
-  * @param  hpcd: PCD handle
-  * @param  size: Size of Rx fifo
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
-{
-  hpcd->Instance->GRXFSIZ = size;
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Activate LPM feature.
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
-{
-  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;  
-  
-  hpcd->lpm_active = ENABLE;
-  hpcd->LPM_State = LPM_L0;
-  USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
-  USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
-
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Deactivate LPM feature.
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
-{
-  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;  
-  
-  hpcd->lpm_active = DISABLE;
-  USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM;
-  USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
-  
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Handle BatteryCharging Process.
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
-{
-  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;  
-  uint32_t tickstart = HAL_GetTick();
-  
-  /* Start BCD When device is connected */
-  if (USBx_DEVICE->DCTL & USB_OTG_DCTL_SDIS)
-  { 
-    /* Enable DCD : Data Contact Detect */
-    USBx->GCCFG |= USB_OTG_GCCFG_DCDEN;
-    
-    /* Wait Detect flag or a timeout is happen*/
-    while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0)
-    {
-      /* Check for the Timeout */
-      if((HAL_GetTick() - tickstart ) > 1000)
-      {
-        HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
-        return;
-      }
-    }
-    
-    /* Right response got */
-    HAL_Delay(100); 
-    
-    /* Check Detect flag*/
-    if (USBx->GCCFG & USB_OTG_GCCFG_DCDET)
-    {
-      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
-    }
-    
-    /*Primary detection: checks if connected to Standard Downstream Port  
-    (without charging capability) */
-    USBx->GCCFG &=~ USB_OTG_GCCFG_DCDEN;
-    USBx->GCCFG |=  USB_OTG_GCCFG_PDEN;
-    HAL_Delay(100); 
-    
-    if (!(USBx->GCCFG & USB_OTG_GCCFG_PDET))
-    {
-      /* Case of Standard Downstream Port */
-      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
-    }
-    else  
-    {
-      /* start secondary detection to check connection to Charging Downstream 
-      Port or Dedicated Charging Port */
-      USBx->GCCFG &=~ USB_OTG_GCCFG_PDEN;
-      USBx->GCCFG |=  USB_OTG_GCCFG_SDEN;
-      HAL_Delay(100); 
-      
-      if ((USBx->GCCFG) & USB_OTG_GCCFG_SDET)
-      { 
-        /* case Dedicated Charging Port  */
-        HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
-      }
-      else
-      {
-        /* case Charging Downstream Port  */
-        HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
-      }
-    }
-    /* Battery Charging capability discovery finished */
-    HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
-  }
-}
-
-/**
-  * @brief  Activate BatteryCharging feature.
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
-{
-  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;  
-
-  hpcd->battery_charging_active = ENABLE; 
-  USBx->GCCFG |= (USB_OTG_GCCFG_BCDEN);
-  
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Deactivate BatteryCharging feature.
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
-{
-  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;  
-  hpcd->battery_charging_active = DISABLE; 
-  USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Send LPM message to user layer callback.
-  * @param  hpcd: PCD handle
-  * @param  msg: LPM message
-  * @retval HAL status
-  */
-__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
-{ 
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-  UNUSED(msg);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCDEx_LPM_Callback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  Send BatteryCharging message to user layer callback.
-  * @param  hpcd: PCD handle
-  * @param  msg: LPM message
-  * @retval HAL status
-  */
-__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-  UNUSED(msg);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCDEx_BCD_Callback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_PCD_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/src/stm32l4xx_hal_pwr.c b/stmhal/hal/l4/src/stm32l4xx_hal_pwr.c
deleted file mode 100644
index 68e6fe7dd0..0000000000
--- a/stmhal/hal/l4/src/stm32l4xx_hal_pwr.c
+++ /dev/null
@@ -1,676 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_pwr.c
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   PWR HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Power Controller (PWR) peripheral:
-  *           + Initialization/de-initialization functions
-  *           + Peripheral Control functions
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup PWR PWR
-  * @brief PWR HAL module driver
-  * @{
-  */
-
-#ifdef HAL_PWR_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/ 
-
-/** @defgroup PWR_Private_Defines PWR Private Defines
-  * @{
-  */
-  
-/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
-  * @{
-  */ 
-#define PVD_MODE_IT               ((uint32_t)0x00010000)  /*!< Mask for interruption yielded by PVD threshold crossing */ 
-#define PVD_MODE_EVT              ((uint32_t)0x00020000)  /*!< Mask for event yielded by PVD threshold crossing        */ 
-#define PVD_RISING_EDGE           ((uint32_t)0x00000001)  /*!< Mask for rising edge set as PVD trigger                 */ 
-#define PVD_FALLING_EDGE          ((uint32_t)0x00000002)  /*!< Mask for falling edge set as PVD trigger                */ 
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup PWR_Exported_Functions PWR Exported Functions
-  * @{
-  */
-
-/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 
-  *  @brief    Initialization and de-initialization functions
-  *
-@verbatim
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Deinitialize the HAL PWR peripheral registers to their default reset values.
-  * @retval None
-  */
-void HAL_PWR_DeInit(void)
-{
-  __HAL_RCC_PWR_FORCE_RESET();
-  __HAL_RCC_PWR_RELEASE_RESET();
-}
-
-/**
-  * @brief Enable access to the backup domain 
-  *        (RTC registers, RTC backup data registers).
-  * @note  After reset, the backup domain is protected against 
-  *        possible unwanted write accesses.
-  * @note  RTCSEL that sets the RTC clock source selection is in the RTC back-up domain.
-  *        In order to set or modify the RTC clock, the backup domain access must be
-  *        disabled. 
-  * @note  LSEON bit that switches on and off the LSE crystal belongs as well to the
-  *        back-up domain.                
-  * @retval None
-  */
-void HAL_PWR_EnableBkUpAccess(void)
-{
-  SET_BIT(PWR->CR1, PWR_CR1_DBP);    
-}
-
-/**
-  * @brief Disable access to the backup domain
-  *        (RTC registers, RTC backup data registers).    
-  * @retval None
-  */
-void HAL_PWR_DisableBkUpAccess(void)
-{
-  CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);   
-}
-
-
-
-
-/**
-  * @}
-  */
-
-
-
-/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
-  *  @brief Low Power modes configuration functions
-  *
-@verbatim
-
- ===============================================================================
-                 ##### Peripheral Control functions #####
- ===============================================================================
- 
-     [..]
-     *** PVD configuration ***
-    =========================
-    [..]
-      (+) The PVD is used to monitor the VDD power supply by comparing it to a
-          threshold selected by the PVD Level (PLS[2:0] bits in PWR_CR2 register).
-
-      (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower
-          than the PVD threshold. This event is internally connected to the EXTI
-          line16 and can generate an interrupt if enabled. This is done through
-          __HAL_PVD_EXTI_ENABLE_IT() macro.
-      (+) The PVD is stopped in Standby mode.
- 
-    
-    *** WakeUp pin configuration ***
-    ================================
-    [..]
-      (+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode. 
-          The polarity of these pins can be set to configure event detection on high 
-          level (rising edge) or low level (falling edge).
-
-
-   
-    *** Low Power modes configuration ***
-    =====================================
-    [..]
-      The devices feature 8 low-power modes:
-      (+) Low-power Run mode: core and peripherals are running, main regulator off, low power regulator on.
-      (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running, main and low power regulators on.
-      (+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept running, main regulator off, low power regulator on.
-      (+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low power regulators on.
-      (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on.
-      (+) Stop 2 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on, reduced set of waking up IPs compared to Stop 1 mode.      
-      (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved, main regulator off, low power regulator on. 
-      (+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power regulators off.
-      (+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off.
-
-
-   *** Low-power run mode ***
-   ==========================
-    [..]
-      (+) Entry: (from main run mode)
-        (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the system clock below 2 MHz. 
-     
-      (+) Exit:
-        (++) clear LPR bit then wait for REGLP bit to be reset with HAL_PWREx_DisableLowPowerRunMode() API. Only
-             then can the system clock frequency be increased above 2 MHz.
-
-
-   *** Sleep mode / Low-power sleep mode ***
-   =========================================
-    [..]
-      (+) Entry:                                                         
-          The Sleep mode / Low-power Sleep mode is entered thru HAL_PWR_EnterSLEEPMode() API
-          in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered. 
-          (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).              
-          (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode).
-          In the latter case, the system clock frequency must have been decreased below 2 MHz beforehand.           
-          (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
-          (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
-     
-      (+) WFI Exit:
-        (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
-             controller (NVIC) or any wake-up event.
-             
-      (+) WFE Exit:
-        (++) Any wake-up event such as an EXTI line configured in event mode.             
-             
-         [..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event, 
-             the MCU is in Low-power Run mode. 
-
-   *** Stop 0, Stop 1 and Stop 2 modes ***
-   ===============================
-    [..]
-      (+) Entry:                                                 
-          The Stop 0, Stop 1 or Stop 2 modes are entered thru the following API's:
-          (++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or for porting reasons HAL_PWR_EnterSTOPMode().
-          (++) HAL_PWREx_EnterSTOP2Mode() for mode 2.  
-      (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):
-          (++) PWR_MAINREGULATOR_ON
-          (++) PWR_LOWPOWERREGULATOR_ON
-      (+) Exit (interrupt or event-triggered, specified when entering STOP mode):
-          (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction
-          (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction
-          
-      (+) WFI Exit:
-          (++) Any EXTI Line (Internal or External) configured in Interrupt mode.
-          (++) Some specific communication peripherals (USART, LPUART, I2C) interrupts 
-               when programmed in wakeup mode. 
-      (+) WFE Exit:  
-          (++) Any EXTI Line (Internal or External) configured in Event mode.
-       
-       [..]                      
-          When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or in Low-power Run mode
-          depending on the LPR bit setting. 
-          When exiting Stop 2 mode, the MCU is in Run mode. 
-
-   *** Standby mode ***
-   ====================
-     [..]
-      The Standby mode offers two options: 
-      (+) option a) all clocks off except LSI and LSE, RRS bit set (keeps voltage regulator in low power mode).
-        SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC backup registers 
-        and Standby circuitry.      
-      (+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage regulator then disabled).
-        SRAM and register contents are lost except for the RTC registers, RTC backup registers 
-        and Standby circuitry.
-
-      (++) Entry:                                    
-          (+++) The Standby mode is entered thru HAL_PWR_EnterSTANDBYMode() API. 
-                SRAM1 and register contents are lost except for registers in the Backup domain and 
-                Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register. 
-                To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API 
-                to set RRS bit.   
-          
-      (++) Exit:
-          (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event, 
-                external reset in NRST pin, IWDG reset.
-                
-      [..]    After waking up from Standby mode, program execution restarts in the same way as after a Reset.
-          
-
-    *** Shutdown mode ***
-   ======================
-     [..]
-      In Shutdown mode, 
-        voltage regulator is disabled, all clocks are off except LSE, RRS bit is cleared.
-        SRAM and registers contents are lost except for backup domain registers.
-
-      (+) Entry:                                    
-          The Shutdown mode is entered thru HAL_PWREx_EnterSHUTDOWNMode() API.
-          
-      (+) Exit:
-          (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event, 
-               external reset in NRST pin.
-               
-         [..] After waking up from Shutdown mode, program execution restarts in the same way as after a Reset.
-
-
-   *** Auto-wakeup (AWU) from low-power mode ***
-   =============================================
-    [..]
-      The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
-      Wakeup event, a tamper event or a time-stamp event, without depending on
-      an external interrupt (Auto-wakeup mode).
-
-      (+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes
-  
-
-        (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
-             configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
-
-        (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
-             is necessary to configure the RTC to detect the tamper or time stamp event using the
-             HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
-
-        (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
-              configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
-
-@endverbatim
-  * @{
-  */
-
-
-
-/**
-  * @brief Configure the voltage threshold detected by the Power Voltage Detector (PVD).
-  * @param sConfigPVD: pointer to a PWR_PVDTypeDef structure that contains the PVD 
-  *        configuration information.
-  * @note Refer to the electrical characteristics of your device datasheet for
-  *         more details about the voltage thresholds corresponding to each
-  *         detection level.
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
-{
-  /* Check the parameters */
-  assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
-  assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
-
-  /* Set PLS bits according to PVDLevel value */
-  MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel);
-  
-  /* Clear any previous config. Keep it clear if no event or IT mode is selected */
-  __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
-  __HAL_PWR_PVD_EXTI_DISABLE_IT();
-  __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); 
-  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
-
-  /* Configure interrupt mode */
-  if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
-  {
-    __HAL_PWR_PVD_EXTI_ENABLE_IT();
-  }
-  
-  /* Configure event mode */
-  if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
-  {
-    __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
-  }
-  
-  /* Configure the edge */
-  if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
-  {
-    __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
-  }
-  
-  if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
-  {
-    __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
-  }
-  
-  return HAL_OK;
-}
-
-
-/**
-  * @brief Enable the Power Voltage Detector (PVD).
-  * @retval None
-  */
-void HAL_PWR_EnablePVD(void)
-{
-  SET_BIT(PWR->CR2, PWR_CR2_PVDE);  
-}
-
-/**
-  * @brief Disable the Power Voltage Detector (PVD).
-  * @retval None
-  */
-void HAL_PWR_DisablePVD(void)
-{
-  CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);   
-}
-
-
-
-
-/**
-  * @brief Enable the WakeUp PINx functionality.
-  * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable.
-  *         This parameter can be one of the following legacy values which set the default polarity 
-  *         i.e. detection on high level (rising edge):
-  *           @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
-  *             
-  *         or one of the following value where the user can explicitly specify the enabled pin and
-  *         the chosen polarity:  
-  *           @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW 
-  *           @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW 
-  *           @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW 
-  *           @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
-  *           @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW 
-  * @note  PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.               
-  * @retval None
-  */
-void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
-{
-  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity)); 
-  
-  /* Specifies the Wake-Up pin polarity for the event detection 
-    (rising or falling edge) */
-  MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT)); 
-    
-  /* Enable wake-up pin */
-  SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity));
-
-    
-}
-
-/**
-  * @brief Disable the WakeUp PINx functionality.
-  * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
-  *         This parameter can be one of the following values:
-  *           @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5 
-  * @retval None
-  */
-void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
-{
-  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
-
-  CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx)); 
-}
-
-
-/**
-  * @brief Enter Sleep or Low-power Sleep mode.
-  * @note  In Sleep/Low-power Sleep mode, all I/O pins keep the same state as in Run mode.
-  * @param Regulator: Specifies the regulator state in Sleep/Low-power Sleep mode.
-  *          This parameter can be one of the following values:
-  *            @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode)
-  *            @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode) 
-  * @note  Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet 
-  *        in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set 
-  *        to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the    
-  *        Flash in power-down monde in setting the SLEEP_PD bit in FLASH_ACR register.
-  *        Additionally, the clock frequency must be reduced below 2 MHz.
-  *        Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must 
-  *        be done before calling HAL_PWR_EnterSLEEPMode() API. 
-  * @note  When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in 
-  *        Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API.       
-  * @param SLEEPEntry: Specifies if Sleep mode is entered with WFI or WFE instruction.
-  *           This parameter can be one of the following values:
-  *            @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instruction
-  *            @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instruction
-  * @note  When WFI entry is used, tick interrupt have to be disabled if not desired as 
-  *        the interrupt wake up source.   
-  * @retval None
-  */
-void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
-{
-  /* Check the parameters */
-  assert_param(IS_PWR_REGULATOR(Regulator));
-  assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
-
-  /* Set Regulator parameter */
-  if (Regulator == PWR_MAINREGULATOR_ON)
-  {
-    /* If in low-power run mode at this point, exit it */
-    if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
-    {
-      HAL_PWREx_DisableLowPowerRunMode();  
-    } 
-    /* Regulator now in main mode. */
-  }
-  else
-  {
-    /* If in run mode, first move to low-power run mode.
-       The system clock frequency must be below 2 MHz at this point. */
-    if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == RESET)
-    {
-      HAL_PWREx_EnableLowPowerRunMode();  
-    } 
-  } 
-    
-  /* Clear SLEEPDEEP bit of Cortex System Control Register */
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-  
-  /* Select SLEEP mode entry -------------------------------------------------*/
-  if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
-  {
-    /* Request Wait For Interrupt */
-    __WFI();
-  }
-  else
-  {
-    /* Request Wait For Event */
-    __SEV();
-    __WFE();
-    __WFE();
-  }
-
-}
-
-
-/**
-  * @brief Enter Stop mode
-  * @note  This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy code running
-  *        on devices where only "Stop mode" is mentioned with main or low power regulator ON.
-  * @note  In Stop mode, all I/O pins keep the same state as in Run mode.          
-  * @note  All clocks in the VCORE domain are stopped; the PLL, the MSI, 
-  *        the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability 
-  *        (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI 
-  *        after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated 
-  *        only to the peripheral requesting it.
-  *        SRAM1, SRAM2 and register contents are preserved.
-  *        The BOR is available.
-  *        The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1).  
-  * @note  When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event,
-  *         the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
-  *         is set; the MSI oscillator is selected if STOPWUCK is cleared.  
-  * @note  When the voltage regulator operates in low power mode (Stop 1), an additional
-  *         startup delay is incurred when waking up.
-  *         By keeping the internal regulator ON during Stop mode (Stop 0), the consumption
-  *         is higher although the startup time is reduced.
-  * @param Regulator: Specifies the regulator state in Stop mode.
-  *          This parameter can be one of the following values:
-  *            @arg @ref PWR_MAINREGULATOR_ON  Stop 0 mode (main regulator ON)
-  *            @arg @ref PWR_LOWPOWERREGULATOR_ON  Stop 1 mode (low power regulator ON) 
-  * @param STOPEntry: Specifies Stop 0 or Stop 1 mode is entered with WFI or WFE instruction.
-  *          This parameter can be one of the following values:
-  *            @arg @ref PWR_STOPENTRY_WFI  Enter Stop 0 or Stop 1 mode with WFI instruction.
-  *            @arg @ref PWR_STOPENTRY_WFE  Enter Stop 0 or Stop 1 mode with WFE instruction.
-  * @retval None
-  */
-void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
-{
-  /* Check the parameters */
-  assert_param(IS_PWR_REGULATOR(Regulator));
-  
-  if(Regulator == PWR_LOWPOWERREGULATOR_ON)
-  {
-    HAL_PWREx_EnterSTOP1Mode(STOPEntry);
-  }
-  else
-  {
-    HAL_PWREx_EnterSTOP0Mode(STOPEntry);
-  }
-}
-
-/**
-  * @brief Enter Standby mode.
-  * @note  In Standby mode, the PLL, the HSI, the MSI and the HSE oscillators are switched 
-  *        off. The voltage regulator is disabled, except when SRAM2 content is preserved
-  *        in which case the regulator is in low-power mode. 
-  *        SRAM1 and register contents are lost except for registers in the Backup domain and 
-  *        Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register. 
-  *        To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API 
-  *        to set RRS bit.   
-  *        The BOR is available.  
-  * @note  The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
-  *        HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and
-  *        Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disable the
-  *        same.
-  *        These states are effective in Standby mode only if APC bit is set through
-  *        HAL_PWREx_EnablePullUpPullDownConfig() API.        
-  * @retval None
-  */
-void HAL_PWR_EnterSTANDBYMode(void)
-{
-  /* Set Stand-by mode */
-  MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STANDBY);
-
-  /* Set SLEEPDEEP bit of Cortex System Control Register */
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-
-/* This option is used to ensure that store operations are completed */
-#if defined ( __CC_ARM)
-  __force_stores();
-#endif
-  /* Request Wait For Interrupt */
-  __WFI();
-}
-
-
-
-/**
-  * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode. 
-  * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor 
-  *       re-enters SLEEP mode when an interruption handling is over.
-  *       Setting this bit is useful when the processor is expected to run only on
-  *       interruptions handling.         
-  * @retval None
-  */
-void HAL_PWR_EnableSleepOnExit(void)
-{
-  /* Set SLEEPONEXIT bit of Cortex System Control Register */
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
-}
-
-
-/**
-  * @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode. 
-  * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor 
-  *       re-enters SLEEP mode when an interruption handling is over.          
-  * @retval None
-  */
-void HAL_PWR_DisableSleepOnExit(void)
-{
-  /* Clear SLEEPONEXIT bit of Cortex System Control Register */
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
-}
-
-
-
-/**
-  * @brief Enable CORTEX M4 SEVONPEND bit. 
-  * @note Set SEVONPEND bit of SCR register. When this bit is set, this causes 
-  *       WFE to wake up when an interrupt moves from inactive to pended.
-  * @retval None
-  */
-void HAL_PWR_EnableSEVOnPend(void)
-{
-  /* Set SEVONPEND bit of Cortex System Control Register */
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
-}
-
-
-/**
-  * @brief Disable CORTEX M4 SEVONPEND bit. 
-  * @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes 
-  *       WFE to wake up when an interrupt moves from inactive to pended.         
-  * @retval None
-  */
-void HAL_PWR_DisableSEVOnPend(void)
-{
-  /* Clear SEVONPEND bit of Cortex System Control Register */
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
-}
-
-
-
-
-
-/**
-  * @brief PWR PVD interrupt callback
-  * @retval None
-  */
-__weak void HAL_PWR_PVDCallback(void)
-{
-  /* NOTE : This function should not be modified; when the callback is needed,
-            the HAL_PWR_PVDCallback can be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_PWR_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/src/stm32l4xx_hal_pwr_ex.c b/stmhal/hal/l4/src/stm32l4xx_hal_pwr_ex.c
deleted file mode 100644
index c4e9e53387..0000000000
--- a/stmhal/hal/l4/src/stm32l4xx_hal_pwr_ex.c
+++ /dev/null
@@ -1,1176 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_pwr_ex.c
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   Extended PWR HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Power Controller (PWR) peripheral:
-  *           + Extended Initialization and de-initialization functions
-  *           + Extended Peripheral Control functions
-  *         
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup PWREx PWREx
-  * @brief PWR Extended HAL module driver
-  * @{
-  */
-
-#ifdef HAL_PWR_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-#define PWR_PORTH_AVAILABLE_PINS   (PWR_GPIO_BIT_0|PWR_GPIO_BIT_1)    
-
-/** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines
-  * @{
-  */
-  
-/** @defgroup PWREx_PVM_Mode_Mask PWR PVM Mode Mask
-  * @{
-  */ 
-#define PVM_MODE_IT               ((uint32_t)0x00010000)  /*!< Mask for interruption yielded by PVM threshold crossing */
-#define PVM_MODE_EVT              ((uint32_t)0x00020000)  /*!< Mask for event yielded by PVM threshold crossing        */
-#define PVM_RISING_EDGE           ((uint32_t)0x00000001)  /*!< Mask for rising edge set as PVM trigger                 */
-#define PVM_FALLING_EDGE          ((uint32_t)0x00000002)  /*!< Mask for falling edge set as PVM trigger                */
-/**
-  * @}
-  */
-  
-/** @defgroup PWREx_TimeOut_Value PWR Extended Flag Setting Time Out Value
-  * @{
-  */ 
-#define PWR_FLAG_SETTING_DELAY_US                      50   /*!< Time out value for REGLPF and VOSF flags setting */
-/**
-  * @}
-  */
-    
-  
-
-/**
-  * @}
-  */
-
-
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-  
-/** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions
-  * @{
-  */
-
-/** @defgroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions
-  *  @brief   Extended Peripheral Control functions
-  *
-@verbatim
- ===============================================================================
-              ##### Extended Peripheral Initialization and de-initialization functions #####
- ===============================================================================
-    [..]
-
-@endverbatim
-  * @{
-  */
-  
-
-/**
-  * @brief Return Voltage Scaling Range.
-  * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_RANGE1 or PWR_REGULATOR_VOLTAGE_RANGE2)
-  */  
-uint32_t HAL_PWREx_GetVoltageRange(void)
-{
-  return  (PWR->CR1 & PWR_CR1_VOS);
-}
-
-  
-
-/**
-  * @brief Configure the main internal regulator output voltage.
-  * @param  VoltageScaling: specifies the regulator output voltage to achieve
-  *         a tradeoff between performance and power consumption.
-  *          This parameter can be one of the following values:
-  *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode,
-  *                                                typical output voltage at 1.2 V,  
-  *                                                system frequency up to 80 MHz.
-  *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode,
-  *                                                typical output voltage at 1.0 V,                
-  *                                                system frequency up to 26 MHz.
-  * @note  When moving from Range 1 to Range 2, the system frequency must be decreased to
-  *        a value below 26 MHz before calling HAL_PWREx_ControlVoltageScaling() API.
-  *        When moving from Range 2 to Range 1, the system frequency can be increased to
-  *        a value up to 80 MHz after calling HAL_PWREx_ControlVoltageScaling() API.
-  * @note  When moving from Range 2 to Range 1, the API waits for VOSF flag to be
-  *        cleared before returning the status. If the flag is not cleared within
-  *        50 microseconds, HAL_TIMEOUT status is reported.                    
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
-{
-  uint32_t wait_loop_index = 0;  
-
-  assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
-  
-  /* If Set Range 1 */
-  if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
-  {
-    if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1)
-    {
-      /* Set Range 1 */
-      MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
-      
-      /* Wait until VOSF is cleared */      
-      wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000));
-      while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)))
-      {
-        wait_loop_index--;
-      }
-      if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  else
-  {
-    if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2)
-    {
-      /* Set Range 2 */
-      MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
-      /* No need to wait for VOSF to be cleared for this transition */
-    }
-  }
-  
-  return HAL_OK;
-}  
-
-
-/**
-  * @brief Enable battery charging.
-  *        When VDD is present, charge the external battery on VBAT thru an internal resistor.  
-  * @param  ResistorSelection: specifies the resistor impedance.
-  *          This parameter can be one of the following values:
-  *            @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5     5 kOhms resistor
-  *            @arg @ref PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor 
-  * @retval None
-  */
-void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection)
-{
-  assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection));
-  
-  /* Specify resistor selection */
-  MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, ResistorSelection);
-  
-  /* Enable battery charging */
-  SET_BIT(PWR->CR4, PWR_CR4_VBE);
-}
-
-
-/**
-  * @brief Disable battery charging.  
-  * @retval None
-  */
-void HAL_PWREx_DisableBatteryCharging(void)
-{
-  CLEAR_BIT(PWR->CR4, PWR_CR4_VBE); 
-}  
-
-
-#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
-/**
-  * @brief Enable VDDUSB supply. 
-  * @note  Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present.  
-  * @retval None
-  */
-void HAL_PWREx_EnableVddUSB(void)
-{
-  SET_BIT(PWR->CR2, PWR_CR2_USV);
-}
-
-
-/**
-  * @brief Disable VDDUSB supply. 
-  * @retval None
-  */
-void HAL_PWREx_DisableVddUSB(void)
-{
-  CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
-}
-#endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
-
-/**
-  * @brief Enable VDDIO2 supply. 
-  * @note  Remove VDDIO2 electrical and logical isolation, once VDDIO2 supply is present. 
-  * @retval None
-  */
-void HAL_PWREx_EnableVddIO2(void)
-{
-  SET_BIT(PWR->CR2, PWR_CR2_IOSV);
-}
-
-
-/**
-  * @brief Disable VDDIO2 supply. 
-  * @retval None
-  */
-void HAL_PWREx_DisableVddIO2(void)
-{
-  CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV);
-}
-
-
-/**
-  * @brief Enable Internal Wake-up Line. 
-  * @retval None
-  */
-void HAL_PWREx_EnableInternalWakeUpLine(void)
-{
-  SET_BIT(PWR->CR3, PWR_CR3_EIWF);
-}
-
-
-/**
-  * @brief Disable Internal Wake-up Line. 
-  * @retval None
-  */
-void HAL_PWREx_DisableInternalWakeUpLine(void)
-{
-  CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF);
-}
-
-
-
-/**
-  * @brief Enable GPIO pull-up state in Standby and Shutdown modes.
-  * @note  Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in 
-  *        pull-up state in Standby and Shutdown modes. 
-  * @note  This state is effective in Standby and Shutdown modes only if APC bit 
-  *        is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
-  * @note  The configuration is lost when exiting the Shutdown mode due to the 
-  *        power-on reset, maintained when exiting the Standby mode. 
-  * @note  To avoid any conflict at Standby and Shutdown modes exits, the corresponding
-  *        PDy bit of PWR_PDCRx register is cleared unless it is reserved. 
-  * @note  Even if a PUy bit to set is reserved, the other PUy bits entered as input 
-  *        parameter at the same time are set.     
-  * @param  GPIO: Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H 
-  *         to select the GPIO peripheral.
-  * @param  GPIONumber: Specify the I/O pins numbers.
-  *         This parameter can be one of the following values:
-  *         PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less  
-  *         I/O pins are available) or the logical OR of several of them to set 
-  *         several bits for a given port in a single API call.    
-  * @retval HAL Status
-  */   
-HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
-{  
-  assert_param(IS_PWR_GPIO(GPIO));
-  assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
-
-  switch (GPIO)
-  {
-    case PWR_GPIO_A:
-       SET_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
-       CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));                       
-       break;
-    case PWR_GPIO_B:
-       SET_BIT(PWR->PUCRB, GPIONumber);
-       CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));                  
-       break; 
-    case PWR_GPIO_C:
-       SET_BIT(PWR->PUCRC, GPIONumber);
-       CLEAR_BIT(PWR->PDCRC, GPIONumber);         
-       break; 
-    case PWR_GPIO_D:
-       SET_BIT(PWR->PUCRD, GPIONumber);
-       CLEAR_BIT(PWR->PDCRD, GPIONumber);         
-       break;
-    case PWR_GPIO_E:
-       SET_BIT(PWR->PUCRE, GPIONumber);
-       CLEAR_BIT(PWR->PDCRE, GPIONumber);         
-       break;
-    case PWR_GPIO_F:
-       SET_BIT(PWR->PUCRF, GPIONumber);
-       CLEAR_BIT(PWR->PDCRF, GPIONumber);         
-       break;
-    case PWR_GPIO_G:
-       SET_BIT(PWR->PUCRG, GPIONumber);
-       CLEAR_BIT(PWR->PDCRG, GPIONumber);         
-       break;
-    case PWR_GPIO_H:
-       SET_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
-       CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));           
-       break;                                                   
-    default:
-        return HAL_ERROR;
-  }
-       
-  return HAL_OK;
-}
-
-
-/**
-  * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes.
-  * @note  Reset the relevant PUy bits of PWR_PUCRx register used to configure the I/O
-  *        in pull-up state in Standby and Shutdown modes.
-  * @note  Even if a PUy bit to reset is reserved, the other PUy bits entered as input 
-  *        parameter at the same time are reset.      
-  * @param  GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H 
-  *         to select the GPIO peripheral.
-  * @param  GPIONumber: Specify the I/O pins numbers.
-  *         This parameter can be one of the following values:
-  *         PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less  
-  *         I/O pins are available) or the logical OR of several of them to reset 
-  *         several bits for a given port in a single API call. 
-  * @retval HAL Status
-  */   
-HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
-{  
-  assert_param(IS_PWR_GPIO(GPIO));
-  assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
-  
-  switch (GPIO)
-  {
-    case PWR_GPIO_A:
-       CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));         
-       break;
-    case PWR_GPIO_B:
-       CLEAR_BIT(PWR->PUCRB, GPIONumber);
-       break; 
-    case PWR_GPIO_C:
-       CLEAR_BIT(PWR->PUCRC, GPIONumber);
-       break; 
-    case PWR_GPIO_D:
-       CLEAR_BIT(PWR->PUCRD, GPIONumber);
-       break;
-    case PWR_GPIO_E:
-       CLEAR_BIT(PWR->PUCRE, GPIONumber);
-       break;
-    case PWR_GPIO_F:
-       CLEAR_BIT(PWR->PUCRF, GPIONumber);
-       break;
-    case PWR_GPIO_G:
-       CLEAR_BIT(PWR->PUCRG, GPIONumber);
-       break;
-    case PWR_GPIO_H:
-       CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
-       break;                                                   
-    default:
-        return HAL_ERROR;
-  }
-       
-  return HAL_OK;
-}
-
-
-
-/**
-  * @brief Enable GPIO pull-down state in Standby and Shutdown modes.
-  * @note  Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in 
-  *        pull-down state in Standby and Shutdown modes. 
-  * @note  This state is effective in Standby and Shutdown modes only if APC bit
-  *        is set through HAL_PWREx_EnablePullUpPullDownConfig() API. 
-  * @note  The configuration is lost when exiting the Shutdown mode due to the 
-  *        power-on reset, maintained when exiting the Standby mode. 
-  * @note  To avoid any conflict at Standby and Shutdown modes exits, the corresponding
-  *        PUy bit of PWR_PUCRx register is cleared unless it is reserved. 
-  * @note  Even if a PDy bit to set is reserved, the other PDy bits entered as input 
-  *        parameter at the same time are set.         
-  * @param  GPIO: Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H 
-  *         to select the GPIO peripheral.
-  * @param  GPIONumber: Specify the I/O pins numbers.
-  *         This parameter can be one of the following values:
-  *         PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less  
-  *         I/O pins are available) or the logical OR of several of them to set 
-  *         several bits for a given port in a single API call. 
-  * @retval HAL Status
-  */   
-HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
-{
-  assert_param(IS_PWR_GPIO(GPIO));
-  assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
-  
-  switch (GPIO)
-  { 
-    case PWR_GPIO_A:
-       SET_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));        
-       CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));           
-       break;
-    case PWR_GPIO_B:
-       SET_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
-       CLEAR_BIT(PWR->PUCRB, GPIONumber);                    
-       break; 
-    case PWR_GPIO_C:
-       SET_BIT(PWR->PDCRC, GPIONumber);
-       CLEAR_BIT(PWR->PUCRC, GPIONumber);        
-       break; 
-    case PWR_GPIO_D:
-       SET_BIT(PWR->PDCRD, GPIONumber);
-       CLEAR_BIT(PWR->PUCRD, GPIONumber);        
-       break;
-    case PWR_GPIO_E:
-       SET_BIT(PWR->PDCRE, GPIONumber);
-       CLEAR_BIT(PWR->PUCRE, GPIONumber);        
-       break;
-    case PWR_GPIO_F:
-       SET_BIT(PWR->PDCRF, GPIONumber);
-       CLEAR_BIT(PWR->PUCRF, GPIONumber);        
-       break;
-    case PWR_GPIO_G:
-       SET_BIT(PWR->PDCRG, GPIONumber);
-       CLEAR_BIT(PWR->PUCRG, GPIONumber);        
-       break;
-    case PWR_GPIO_H:
-       SET_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
-       CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));          
-       break;                                                   
-    default:
-        return HAL_ERROR;
-  }
-       
-  return HAL_OK;
-}
-
-
-/**
-  * @brief Disable GPIO pull-down state in Standby and Shutdown modes.
-  * @note  Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O
-  *        in pull-down state in Standby and Shutdown modes. 
-  * @note  Even if a PDy bit to reset is reserved, the other PDy bits entered as input 
-  *        parameter at the same time are reset.   
-  * @param  GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H 
-  *         to select the GPIO peripheral.
-  * @param  GPIONumber: Specify the I/O pins numbers.
-  *         This parameter can be one of the following values:
-  *         PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less  
-  *         I/O pins are available) or the logical OR of several of them to reset 
-  *         several bits for a given port in a single API call. 
-  * @retval HAL Status
-  */   
-HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
-{
-  assert_param(IS_PWR_GPIO(GPIO));
-  assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
-   
-  switch (GPIO)
-  {
-    case PWR_GPIO_A:
-       CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));                        
-       break;
-    case PWR_GPIO_B:
-       CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));           
-       break; 
-    case PWR_GPIO_C:
-       CLEAR_BIT(PWR->PDCRC, GPIONumber);
-       break; 
-    case PWR_GPIO_D:
-       CLEAR_BIT(PWR->PDCRD, GPIONumber);
-       break;
-    case PWR_GPIO_E:
-       CLEAR_BIT(PWR->PDCRE, GPIONumber);
-       break;
-    case PWR_GPIO_F:
-       CLEAR_BIT(PWR->PDCRF, GPIONumber);
-       break;
-    case PWR_GPIO_G:
-       CLEAR_BIT(PWR->PDCRG, GPIONumber);
-       break;
-    case PWR_GPIO_H:
-      CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
-       break;                                                   
-    default:
-        return HAL_ERROR;
-  }
-       
-  return HAL_OK;
-}
-
-
-
-/**
-  * @brief Enable pull-up and pull-down configuration.
-  * @note  When APC bit is set, the I/O pull-up and pull-down configurations defined in 
-  *        PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes.    
-  * @note  Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding
-  *        PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher). 
-  *        HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there 
-  *        is no conflict when setting PUy or PDy bit.         
-  * @retval None
-  */
-void HAL_PWREx_EnablePullUpPullDownConfig(void)
-{
-  SET_BIT(PWR->CR3, PWR_CR3_APC);
-}
-
-
-/**
-  * @brief Disable pull-up and pull-down configuration.
-  * @note  When APC bit is cleared, the I/O pull-up and pull-down configurations defined in 
-  *        PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes.     
-  * @retval None
-  */
-void HAL_PWREx_DisablePullUpPullDownConfig(void)
-{
-  CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
-}
-
-
-
-/**
-  * @brief Enable SRAM2 content retention in Standby mode.
-  * @note  When RRS bit is set, SRAM2 is powered by the low-power regulator in 
-  *         Standby mode and its content is kept.    
-  * @retval None
-  */
-void HAL_PWREx_EnableSRAM2ContentRetention(void)
-{
-  SET_BIT(PWR->CR3, PWR_CR3_RRS);
-}
-
-
-/**
-  * @brief Disable SRAM2 content retention in Standby mode.
-  * @note  When RRS bit is reset, SRAM2 is powered off in Standby mode 
-  *        and its content is lost.      
-  * @retval None
-  */
-void HAL_PWREx_DisableSRAM2ContentRetention(void)
-{
-  CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
-}
-
-
-
-
-#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
-/**
-  * @brief Enable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.
-  * @retval None
-  */
-void HAL_PWREx_EnablePVM1(void)
-{
-  SET_BIT(PWR->CR2, PWR_PVM_1);    
-}
-
-/**
-  * @brief Disable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.
-  * @retval None
-  */
-void HAL_PWREx_DisablePVM1(void)
-{
-  CLEAR_BIT(PWR->CR2, PWR_PVM_1);    
-}
-#endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
-
-
-/**
-  * @brief Enable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V.
-  * @retval None
-  */
-void HAL_PWREx_EnablePVM2(void)
-{
-  SET_BIT(PWR->CR2, PWR_PVM_2);    
-}
-
-/**
-  * @brief Disable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V.
-  * @retval None
-  */
-void HAL_PWREx_DisablePVM2(void)
-{
-  CLEAR_BIT(PWR->CR2, PWR_PVM_2);    
-}
-
-
-/**
-  * @brief Enable the Power Voltage Monitoring 3: VDDA versus 1.62V.
-  * @retval None
-  */
-void HAL_PWREx_EnablePVM3(void)
-{
-  SET_BIT(PWR->CR2, PWR_PVM_3);    
-}
-
-/**
-  * @brief Disable the Power Voltage Monitoring 3: VDDA versus 1.62V.
-  * @retval None
-  */
-void HAL_PWREx_DisablePVM3(void)
-{
-  CLEAR_BIT(PWR->CR2, PWR_PVM_3);    
-}
-
-
-/**
-  * @brief Enable the Power Voltage Monitoring 4:  VDDA versus 2.2V.
-  * @retval None
-  */
-void HAL_PWREx_EnablePVM4(void)
-{
-  SET_BIT(PWR->CR2, PWR_PVM_4);    
-}
-
-/**
-  * @brief Disable the Power Voltage Monitoring 4:  VDDA versus 2.2V.
-  * @retval None
-  */
-void HAL_PWREx_DisablePVM4(void)
-{
-  CLEAR_BIT(PWR->CR2, PWR_PVM_4);    
-}
-
-
-
-
-/**
-  * @brief Configure the Peripheral Voltage Monitoring (PVM).
-  * @param sConfigPVM: pointer to a PWR_PVMTypeDef structure that contains the
-  *        PVM configuration information.
-  * @note The API configures a single PVM according to the information contained 
-  *       in the input structure. To configure several PVMs, the API must be singly 
-  *       called for each PVM used.
-  * @note Refer to the electrical characteristics of your device datasheet for
-  *         more details about the voltage thresholds corresponding to each
-  *         detection level and to each monitored supply.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM)
-{  
-  /* Check the parameters */
-  assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType));
-  assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode));
-
-
-  /* Configure EXTI 35 to 38 interrupts if so required:
-     scan thru PVMType to detect which PVMx is set and
-     configure the corresponding EXTI line accordingly. */
-  switch (sConfigPVM->PVMType)
-  {
-#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
-    case PWR_PVM_1:
-      /* Clear any previous config. Keep it clear if no event or IT mode is selected */
-      __HAL_PWR_PVM1_EXTI_DISABLE_EVENT();
-      __HAL_PWR_PVM1_EXTI_DISABLE_IT();
-      __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); 
-      __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE();
-
-      /* Configure interrupt mode */
-      if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
-      {
-        __HAL_PWR_PVM1_EXTI_ENABLE_IT();
-      }
-  
-      /* Configure event mode */
-      if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
-      {
-        __HAL_PWR_PVM1_EXTI_ENABLE_EVENT();
-      }
-  
-      /* Configure the edge */
-      if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
-      {
-        __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE();
-      }
-  
-      if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
-      {
-        __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE();
-      }
-      break; 
-#endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */        
-    
-    case PWR_PVM_2:
-      /* Clear any previous config. Keep it clear if no event or IT mode is selected */
-      __HAL_PWR_PVM2_EXTI_DISABLE_EVENT();
-      __HAL_PWR_PVM2_EXTI_DISABLE_IT();
-      __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE(); 
-      __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE();
-
-      /* Configure interrupt mode */
-      if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
-      {
-        __HAL_PWR_PVM2_EXTI_ENABLE_IT();
-      }
-  
-      /* Configure event mode */
-      if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
-      {
-        __HAL_PWR_PVM2_EXTI_ENABLE_EVENT();
-      }
-  
-      /* Configure the edge */
-      if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
-      {
-        __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE();
-      }
-  
-      if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
-      {
-        __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE();
-      }
-      break;
-      
-    case PWR_PVM_3:
-      /* Clear any previous config. Keep it clear if no event or IT mode is selected */
-      __HAL_PWR_PVM3_EXTI_DISABLE_EVENT();
-      __HAL_PWR_PVM3_EXTI_DISABLE_IT();
-      __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); 
-      __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE();
-
-      /* Configure interrupt mode */
-      if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
-      {
-        __HAL_PWR_PVM3_EXTI_ENABLE_IT();
-      }
-  
-      /* Configure event mode */
-      if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
-      {
-        __HAL_PWR_PVM3_EXTI_ENABLE_EVENT();
-      }
-  
-      /* Configure the edge */
-      if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
-      {
-        __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE();
-      }
-  
-      if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
-      {
-        __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE();
-      }
-      break;
-      
-    case PWR_PVM_4:
-      /* Clear any previous config. Keep it clear if no event or IT mode is selected */
-      __HAL_PWR_PVM4_EXTI_DISABLE_EVENT();
-      __HAL_PWR_PVM4_EXTI_DISABLE_IT();
-      __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE(); 
-      __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE();
-
-      /* Configure interrupt mode */
-      if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
-      {
-        __HAL_PWR_PVM4_EXTI_ENABLE_IT();
-      }
-  
-      /* Configure event mode */
-      if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
-      {
-        __HAL_PWR_PVM4_EXTI_ENABLE_EVENT();
-      }
-  
-      /* Configure the edge */
-      if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
-      {
-        __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE();
-      }
-  
-      if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
-      {
-        __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE();
-      }
-      break;  
-      
-    default:
-      return HAL_ERROR;                      
-    
-  }   
-
-  
-  return HAL_OK;
-}
-
-
-
-/**
-  * @brief Enter Low-power Run mode
-  * @note  In Low-power Run mode, all I/O pins keep the same state as in Run mode.  
-  * @note  When Regulator is set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the 
-  *        Flash in power-down monde in setting the RUN_PD bit in FLASH_ACR register.
-  *        Additionally, the clock frequency must be reduced below 2 MHz.
-  *        Setting RUN_PD in FLASH_ACR then appropriately reducing the clock frequency must 
-  *        be done before calling HAL_PWREx_EnableLowPowerRunMode() API.     
-  * @retval None
-  */
-void HAL_PWREx_EnableLowPowerRunMode(void)
-{
-  /* Set Regulator parameter */
-  SET_BIT(PWR->CR1, PWR_CR1_LPR); 
-}
-
-
-/**
-  * @brief Exit Low-power Run mode.
-  * @note  Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that 
-  *        REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode 
-  *        returns HAL_TIMEOUT status). The system clock frequency can then be
-  *        increased above 2 MHz.   
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void)
-{
-  uint32_t wait_loop_index = 0;
-  
-  /* Clear LPR bit */
-  CLEAR_BIT(PWR->CR1, PWR_CR1_LPR); 
-
-  /* Wait until REGLPF is reset */
-  wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000));
-  while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)))
-  {
-    wait_loop_index--;
-  }
-  if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
-  {
-    return HAL_TIMEOUT;
-  }
-  
-  return HAL_OK;
-}
-
-
-/**
-  * @brief Enter Stop 0 mode.
-  * @note  In Stop 0 mode, main and low voltage regulators are ON.
-  * @note  In Stop 0 mode, all I/O pins keep the same state as in Run mode.
-  * @note  All clocks in the VCORE domain are stopped; the PLL, the MSI, 
-  *        the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability 
-  *        (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI 
-  *        after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated 
-  *        only to the peripheral requesting it.
-  *        SRAM1, SRAM2 and register contents are preserved.
-  *        The BOR is available.
-  * @note  When exiting Stop 0 mode by issuing an interrupt or a wakeup event,
-  *         the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
-  *         is set; the MSI oscillator is selected if STOPWUCK is cleared.  
-  * @note  By keeping the internal regulator ON during Stop 0 mode, the consumption
-  *         is higher although the startup time is reduced.
-  * @param STOPEntry  specifies if Stop mode in entered with WFI or WFE instruction.
-  *          This parameter can be one of the following values:
-  *            @arg @ref PWR_STOPENTRY_WFI  Enter Stop mode with WFI instruction
-  *            @arg @ref PWR_STOPENTRY_WFE  Enter Stop mode with WFE instruction
-  * @retval None
-  */
-void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry)
-{
-  /* Check the parameters */
-  assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
-    
-  /* Stop 0 mode with Main Regulator */
-  MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP0);
-
-  /* Set SLEEPDEEP bit of Cortex System Control Register */
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-
-  /* Select Stop mode entry --------------------------------------------------*/
-  if(STOPEntry == PWR_STOPENTRY_WFI)
-  {
-    /* Request Wait For Interrupt */
-    __WFI();
-  }
-  else
-  {
-    /* Request Wait For Event */
-    __SEV();
-    __WFE();
-    __WFE();
-  }
-
-  /* Reset SLEEPDEEP bit of Cortex System Control Register */
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-}
-
-
-/**
-  * @brief Enter Stop 1 mode.
-  * @note  In Stop 1 mode, only low power voltage regulator is ON.
-  * @note  In Stop 1 mode, all I/O pins keep the same state as in Run mode.
-  * @note  All clocks in the VCORE domain are stopped; the PLL, the MSI, 
-  *        the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability 
-  *        (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI 
-  *        after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated 
-  *        only to the peripheral requesting it.
-  *        SRAM1, SRAM2 and register contents are preserved.
-  *        The BOR is available.
-  * @note  When exiting Stop 1 mode by issuing an interrupt or a wakeup event,
-  *         the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
-  *         is set; the MSI oscillator is selected if STOPWUCK is cleared.  
-  * @note  Due to low power mode, an additional startup delay is incurred when waking up from Stop 1 mode.
-  * @param STOPEntry  specifies if Stop mode in entered with WFI or WFE instruction.
-  *          This parameter can be one of the following values:
-  *            @arg @ref PWR_STOPENTRY_WFI  Enter Stop mode with WFI instruction
-  *            @arg @ref PWR_STOPENTRY_WFE  Enter Stop mode with WFE instruction
-  * @retval None
-  */
-void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)
-{
-  /* Check the parameters */
-  assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
-    
-  /* Stop 1 mode with Low-Power Regulator */
-  MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP1);
-
-  /* Set SLEEPDEEP bit of Cortex System Control Register */
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-
-  /* Select Stop mode entry --------------------------------------------------*/
-  if(STOPEntry == PWR_STOPENTRY_WFI)
-  {
-    /* Request Wait For Interrupt */
-    __WFI();
-  }
-  else
-  {
-    /* Request Wait For Event */
-    __SEV();
-    __WFE();
-    __WFE();
-  }
-
-  /* Reset SLEEPDEEP bit of Cortex System Control Register */
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-}
-
-
-/**
-  * @brief Enter Stop 2 mode.
-  * @note  In Stop 2 mode, only low power voltage regulator is ON.
-  * @note  In Stop 2 mode, all I/O pins keep the same state as in Run mode.
-  * @note  All clocks in the VCORE domain are stopped, the PLL, the MSI, 
-  *        the HSI and the HSE oscillators are disabled. Some peripherals with wakeup capability 
-  *        (LCD, LPTIM1, I2C3 and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after 
-  *        receiving the frame if it is not a wakeup frame. In this case the HSI clock is propagated only 
-  *        to the peripheral requesting it.
-  *        SRAM1, SRAM2 and register contents are preserved.
-  *        The BOR is available.   
-  *        The voltage regulator is set in low-power mode but LPR bit must be cleared to enter stop 2 mode.
-  *        Otherwise, Stop 1 mode is entered.  
-  * @note  When exiting Stop 2 mode by issuing an interrupt or a wakeup event,
-  *         the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
-  *         is set; the MSI oscillator is selected if STOPWUCK is cleared.     
-  * @param STOPEntry  specifies if Stop mode in entered with WFI or WFE instruction.
-  *          This parameter can be one of the following values:
-  *            @arg @ref PWR_STOPENTRY_WFI  Enter Stop mode with WFI instruction
-  *            @arg @ref PWR_STOPENTRY_WFE  Enter Stop mode with WFE instruction
-  * @retval None
-  */
-void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry)
-{
-  /* Check the parameter */
-  assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
-
-  /* Set Stop mode 2 */
-  MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP2);
-
-  /* Set SLEEPDEEP bit of Cortex System Control Register */
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-
-  /* Select Stop mode entry --------------------------------------------------*/
-  if(STOPEntry == PWR_STOPENTRY_WFI)
-  {
-    /* Request Wait For Interrupt */
-    __WFI();
-  }
-  else
-  {
-    /* Request Wait For Event */
-    __SEV();
-    __WFE();
-    __WFE();
-  }
-
-  /* Reset SLEEPDEEP bit of Cortex System Control Register */
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-}
-
-
-
-
-
-/**
-  * @brief Enter Shutdown mode. 
-  * @note  In Shutdown mode, the PLL, the HSI, the MSI, the LSI and the HSE oscillators are switched 
-  *        off. The voltage regulator is disabled and Vcore domain is powered off. 
-  *        SRAM1, SRAM2 and registers contents are lost except for registers in the Backup domain.
-  *        The BOR is not available.  
-  * @note  The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.  
-  * @retval None
-  */
-void HAL_PWREx_EnterSHUTDOWNMode(void)
-{
-  
-  /* Set Shutdown mode */
-  MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_SHUTDOWN);
-  
-  /* Set SLEEPDEEP bit of Cortex System Control Register */
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-
-/* This option is used to ensure that store operations are completed */
-#if defined ( __CC_ARM)
-  __force_stores();
-#endif
-  /* Request Wait For Interrupt */
-  __WFI();
-}
-
-
-
-
-/**
-  * @brief This function handles the PWR PVD/PVMx interrupt request.
-  * @note This API should be called under the PVD_PVM_IRQHandler().  
-  * @retval None
-  */
-void HAL_PWREx_PVD_PVM_IRQHandler(void)
-{
-  /* Check PWR exti flag */
-  if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
-  {
-    /* PWR PVD interrupt user callback */
-    HAL_PWR_PVDCallback();
-
-    /* Clear PVD exti pending bit */
-    __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
-  }
-  /* Next, successively check PVMx exti flags */
-#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
-  if(__HAL_PWR_PVM1_EXTI_GET_FLAG() != RESET) 
-  {
-    /* PWR PVM1 interrupt user callback */
-    HAL_PWREx_PVM1Callback();
-   
-    /* Clear PVM1 exti pending bit */
-    __HAL_PWR_PVM1_EXTI_CLEAR_FLAG();
-  }
-#endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
-  if(__HAL_PWR_PVM2_EXTI_GET_FLAG() != RESET) 
-  {
-    /* PWR PVM2 interrupt user callback */
-    HAL_PWREx_PVM2Callback();
-   
-    /* Clear PVM2 exti pending bit */
-    __HAL_PWR_PVM2_EXTI_CLEAR_FLAG();
-  }
-  if(__HAL_PWR_PVM3_EXTI_GET_FLAG() != RESET) 
-  {
-    /* PWR PVM3 interrupt user callback */
-    HAL_PWREx_PVM3Callback();
-   
-    /* Clear PVM3 exti pending bit */
-    __HAL_PWR_PVM3_EXTI_CLEAR_FLAG();
-  }
-  if(__HAL_PWR_PVM4_EXTI_GET_FLAG() != RESET) 
-  {
-    /* PWR PVM4 interrupt user callback */
-    HAL_PWREx_PVM4Callback();
-   
-    /* Clear PVM4 exti pending bit */
-    __HAL_PWR_PVM4_EXTI_CLEAR_FLAG();
-  }      
-}
-
-
-#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
-/**
-  * @brief PWR PVM1 interrupt callback
-  * @retval None
-  */
-__weak void HAL_PWREx_PVM1Callback(void)
-{
-  /* NOTE : This function should not be modified; when the callback is needed,
-            HAL_PWREx_PVM1Callback() API can be implemented in the user file
-   */
-}
-#endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
-
-/**
-  * @brief PWR PVM2 interrupt callback
-  * @retval None
-  */
-__weak void HAL_PWREx_PVM2Callback(void)
-{
-  /* NOTE : This function should not be modified; when the callback is needed,
-            HAL_PWREx_PVM2Callback() API can be implemented in the user file
-   */
-}
-
-/**
-  * @brief PWR PVM3 interrupt callback
-  * @retval None
-  */
-__weak void HAL_PWREx_PVM3Callback(void)
-{
-  /* NOTE : This function should not be modified; when the callback is needed,
-            HAL_PWREx_PVM3Callback() API can be implemented in the user file
-   */
-}
-
-/**
-  * @brief PWR PVM4 interrupt callback
-  * @retval None
-  */
-__weak void HAL_PWREx_PVM4Callback(void)
-{
-  /* NOTE : This function should not be modified; when the callback is needed,
-            HAL_PWREx_PVM4Callback() API can be implemented in the user file
-   */
-}
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_PWR_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/src/stm32l4xx_hal_qspi.c b/stmhal/hal/l4/src/stm32l4xx_hal_qspi.c
deleted file mode 100644
index eeadc482b9..0000000000
--- a/stmhal/hal/l4/src/stm32l4xx_hal_qspi.c
+++ /dev/null
@@ -1,1981 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_qspi.c
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   QSPI HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the QuadSPI interface (QSPI).
-  *           + Initialization and de-initialization functions
-  *           + Indirect functional mode management
-  *           + Memory-mapped functional mode management
-  *           + Auto-polling functional mode management
-  *           + Interrupts and flags management
-  *           + DMA channel configuration for indirect functional mode
-  *           + Errors management and abort functionality
-  *
-  *
-  @verbatim
- ===============================================================================
-                        ##### How to use this driver #####
- ===============================================================================
-  [..]
-    *** Initialization ***
-    ======================
-    [..]
-      (#) As prerequisite, fill in the HAL_QSPI_MspInit() :
-        (++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
-        (++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
-        (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
-        (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
-        (++) If interrupt mode is used, enable and configure QuadSPI global
-            interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
-        (++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel 
-            with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(), 
-            link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure 
-            DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
-      (#) Configure the flash size, the clock prescaler, the fifo threshold, the
-          clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.
-
-    *** Indirect functional mode ***
-    ================================
-    [..]
-      (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT() 
-          functions :
-         (++) Instruction phase : the mode used and if present the instruction opcode.
-         (++) Address phase : the mode used and if present the size and the address value.
-         (++) Alternate-bytes phase : the mode used and if present the size and the alternate 
-             bytes values.
-         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
-         (++) Data phase : the mode used and if present the number of bytes.
-         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay 
-             if activated.
-         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
-      (#) If no data is required for the command, it is sent directly to the memory :
-         (++) In polling mode, the output of the function is done when the transfer is complete.
-         (++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
-      (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or 
-          HAL_QSPI_Transmit_IT() after the command configuration :
-         (++) In polling mode, the output of the function is done when the transfer is complete.
-         (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold 
-             is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
-         (++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and 
-             HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
-      (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or 
-          HAL_QSPI_Receive_IT() after the command configuration :
-         (++) In polling mode, the output of the function is done when the transfer is complete.
-         (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold 
-             is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
-         (++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and 
-             HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
-
-    *** Auto-polling functional mode ***
-    ====================================
-    [..]
-      (#) Configure the command sequence and the auto-polling functional mode using the 
-          HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
-         (++) Instruction phase : the mode used and if present the instruction opcode.
-         (++) Address phase : the mode used and if present the size and the address value.
-         (++) Alternate-bytes phase : the mode used and if present the size and the alternate 
-             bytes values.
-         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
-         (++) Data phase : the mode used.
-         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay 
-             if activated.
-         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
-         (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
-             the polling interval and the automatic stop activation.
-      (#) After the configuration :
-         (++) In polling mode, the output of the function is done when the status match is reached. The
-             automatic stop is activated to avoid an infinite loop.
-         (++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.
-
-    *** Memory-mapped functional mode ***
-    =====================================
-    [..]
-      (#) Configure the command sequence and the memory-mapped functional mode using the 
-          HAL_QSPI_MemoryMapped() functions :
-         (++) Instruction phase : the mode used and if present the instruction opcode.
-         (++) Address phase : the mode used and the size.
-         (++) Alternate-bytes phase : the mode used and if present the size and the alternate 
-             bytes values.
-         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
-         (++) Data phase : the mode used.
-         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay 
-             if activated.
-         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
-         (++) The timeout activation and the timeout period.
-      (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on 
-          the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.
-
-    *** Errors management and abort functionality ***
-    ==================================================
-    [..]
-      (#) HAL_QSPI_GetError() function gives the error raised during the last operation.
-      (#) HAL_QSPI_Abort() function aborts any on-going operation and flushes the fifo.
-      (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.
-
-    *** Workarounds linked to Silicon Limitation ***
-    ====================================================
-    [..]
-      (#) Workarounds Implemented inside HAL Driver
-         (++) Extra data written in the FIFO at the end of a read transfer
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************  
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup QSPI QSPI
-  * @brief QSPI HAL module driver
-  * @{
-  */
-#ifdef HAL_QSPI_MODULE_ENABLED
-    
-/* Private typedef -----------------------------------------------------------*/
-
-/* Private define ------------------------------------------------------------*/
-/** @defgroup QSPI_Private_Constants QSPI Private Constants
-  * @{
-  */
-#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000)          /*!<Indirect write mode*/
-#define QSPI_FUNCTIONAL_MODE_INDIRECT_READ  ((uint32_t)QUADSPI_CCR_FMODE_0) /*!<Indirect read mode*/
-#define QSPI_FUNCTIONAL_MODE_AUTO_POLLING   ((uint32_t)QUADSPI_CCR_FMODE_1) /*!<Automatic polling mode*/
-#define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED  ((uint32_t)QUADSPI_CCR_FMODE)   /*!<Memory-mapped mode*/
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup QSPI_Private_Macros QSPI Private Macros
-  * @{
-  */
-#define IS_QSPI_FUNCTIONAL_MODE(MODE) (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \
-                                       ((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ)  || \
-                                       ((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING)   || \
-                                       ((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
-/**
-  * @}
-  */
-
-/* Private variables ---------------------------------------------------------*/
-
-/* Private function prototypes -----------------------------------------------*/
-static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma);
-static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma);
-static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
-static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
-static void QSPI_DMAError(DMA_HandleTypeDef *hdma); 
-static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Timeout);
-static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode);
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup QSPI_Exported_Functions QSPI Exported Functions
-  * @{
-  */
-
-/** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions 
-  *  @brief    Initialization and Configuration functions 
-  *
-@verbatim    
-===============================================================================
-            ##### Initialization and Configuration functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to :
-      (+) Initialize the QuadSPI.
-      (+) De-initialize the QuadSPI.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Initialize the QSPI mode according to the specified parameters
-  *        in the QSPI_InitTypeDef and initialize the associated handle.
-  * @param hqspi: QSPI handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
-{
-  HAL_StatusTypeDef status = HAL_ERROR;
-  
-  /* Check the QSPI handle allocation */
-  if(hqspi == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance));
-  assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler));
-  assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold));
-  assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting));
-  assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));
-  assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));
-  assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));
-
-  /* Process locked */
-  __HAL_LOCK(hqspi);
-  
-  if(hqspi->State == HAL_QSPI_STATE_RESET)
-  {  
-    /* Allocate lock resource and initialize it */
-    hqspi->Lock = HAL_UNLOCKED;
-
-    /* Init the low level hardware : GPIO, CLOCK */
-    HAL_QSPI_MspInit(hqspi);
-    
-    /* Configure the default timeout for the QSPI memory access */
-    HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);
-  }
-  
-  /* Configure QSPI FIFO Threshold */
-  MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, 
-             ((hqspi->Init.FifoThreshold - 1) << POSITION_VAL(QUADSPI_CR_FTHRES)));
-
-  /* Wait till BUSY flag reset */
-  status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
-
-  if(status == HAL_OK)
-  {
-    /* Configure QSPI Clock Prescaler and Sample Shift */
-    MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT), 
-               ((hqspi->Init.ClockPrescaler << POSITION_VAL(QUADSPI_CR_PRESCALER)) | 
-                hqspi->Init.SampleShifting));
-
-    /* Configure QSPI Flash Size, CS High Time and Clock Mode */
-    MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE), 
-               ((hqspi->Init.FlashSize << POSITION_VAL(QUADSPI_DCR_FSIZE)) | 
-                hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));
-
-    /* Enable the QSPI peripheral */
-    __HAL_QSPI_ENABLE(hqspi);
-  
-    /* Set QSPI error code to none */
-    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;  
-
-    /* Initialize the QSPI state */
-    hqspi->State = HAL_QSPI_STATE_READY;
-  }
-  
-  /* Release Lock */
-  __HAL_UNLOCK(hqspi);
-
-  /* Return function status */
-  return status;
-}
-
-/**
-  * @brief De-Initialize the QSPI peripheral. 
-  * @param hqspi: QSPI handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
-{
-  /* Check the QSPI handle allocation */
-  if(hqspi == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Process locked */
-  __HAL_LOCK(hqspi);
-
-  /* Disable the QSPI Peripheral Clock */
-  __HAL_QSPI_DISABLE(hqspi);
-
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
-  HAL_QSPI_MspDeInit(hqspi);
-
-  /* Set QSPI error code to none */
-  hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
-  /* Initialize the QSPI state */
-  hqspi->State = HAL_QSPI_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hqspi);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Initialize the QSPI MSP.
-  * @param hqspi: QSPI handle
-  * @retval None
-  */
-__weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hqspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_QSPI_MspInit can be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief DeInitialize the QSPI MSP.
-  * @param hqspi: QSPI handle
-  * @retval None
-  */
-__weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hqspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_QSPI_MspDeInit can be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup QSPI_Exported_Functions_Group2 Input and Output operation functions 
-  *  @brief QSPI Transmit/Receive functions 
-  *
-@verbatim   
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to :
-      (+) Handle the interrupts.
-      (+) Handle the command sequence.
-      (+) Transmit data in blocking, interrupt or DMA mode.
-      (+) Receive data in blocking, interrupt or DMA mode.
-      (+) Manage the auto-polling functional mode.
-      (+) Manage the memory-mapped functional mode.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Handle QSPI interrupt request.
-  * @param hqspi: QSPI handle
-  * @retval None
-  */
-void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
-{
-  __IO uint32_t *data_reg;
-  uint32_t flag = 0, itsource = 0;
-
-  /* QSPI Fifo Threshold interrupt occurred ----------------------------------*/
-  flag     = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT);
-  itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_FT);
-  
-  if((flag != RESET) && (itsource != RESET))
-  {
-    data_reg = &hqspi->Instance->DR;
-
-    if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
-    {
-      /* Transmission process */
-      while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
-      {
-        if (hqspi->TxXferCount > 0)
-        {
-          /* Fill the FIFO until the threshold is reached */
-          *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
-          hqspi->TxXferCount--;
-        }
-        else
-        {
-          /* No more data available for the transfer */
-          /* Disable the QSPI FIFO Threshold Interrupt */
-          __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
-          break;
-        }
-      }
-    }
-    else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
-    {
-      /* Receiving Process */
-      while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
-      {
-        if (hqspi->RxXferCount > 0)
-        {
-          /* Read the FIFO until the threshold is reached */
-          *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
-          hqspi->RxXferCount--;
-        }
-        else
-        {
-          /* All data have been received for the transfer */
-          /* Disable the QSPI FIFO Threshold Interrupt */
-          __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
-          break;
-        }
-      }
-    }
-    
-    /* FIFO Threshold callback */
-    HAL_QSPI_FifoThresholdCallback(hqspi);
-  }
-
-  /* QSPI Transfer Complete interrupt occurred -------------------------------*/
-  flag     = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TC);
-  itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TC);
-  
-  if((flag != RESET) && (itsource != RESET))
-  {
-    /* Clear interrupt */
-    __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
-
-    /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */
-    __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
-    
-    /* Transfer complete callback */
-    if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
-    {
-      /* Clear Busy bit */
-      HAL_QSPI_Abort(hqspi);
-      
-      /* TX Complete callback */
-      HAL_QSPI_TxCpltCallback(hqspi);
-    }
-    else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
-    {
-      data_reg = &hqspi->Instance->DR;
-      while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0)
-      {
-        if (hqspi->RxXferCount > 0)
-        {
-          /* Read the last data received in the FIFO until it is empty */
-          *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
-          hqspi->RxXferCount--;
-        }
-        else
-        {
-          /* All data have been received for the transfer */
-          break;
-        }
-      }
-
-      /* Workaround - Extra data written in the FIFO at the end of a read transfer */
-      HAL_QSPI_Abort(hqspi);
-
-      /* RX Complete callback */
-      HAL_QSPI_RxCpltCallback(hqspi);
-    }
-    else if(hqspi->State == HAL_QSPI_STATE_BUSY)
-    {
-      /* Command Complete callback */
-      HAL_QSPI_CmdCpltCallback(hqspi);
-    }
-
-    /* Change state of QSPI */
-    hqspi->State = HAL_QSPI_STATE_READY;
-  }
-
-  /* QSPI Status Match interrupt occurred ------------------------------------*/
-  flag     = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_SM);
-  itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_SM);
-  
-  if((flag != RESET) && (itsource != RESET))
-  {
-    /* Clear interrupt */
-    __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
-   
-    /* Check if the automatic poll mode stop is activated */
-    if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0)
-    {
-      /* Disable the QSPI Transfer Error and Status Match Interrupts */
-      __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
-
-      /* Change state of QSPI */
-      hqspi->State = HAL_QSPI_STATE_READY;
-    }
-
-    /* Status match callback */
-    HAL_QSPI_StatusMatchCallback(hqspi);
-  }
-
-  /* QSPI Transfer Error interrupt occurred ----------------------------------*/
-  flag     = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TE);
-  itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TE);
-  
-  if((flag != RESET) && (itsource != RESET))
-  {
-    /* Clear interrupt */
-    __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE);
-    
-    /* Disable all the QSPI Interrupts */
-    __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
-
-    /* Set error code */
-    hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER;
-    
-    /* Change state of QSPI */
-    hqspi->State = HAL_QSPI_STATE_ERROR;
-
-    /* Error callback */
-    HAL_QSPI_ErrorCallback(hqspi);
-  }
-
-  /* QSPI Timeout interrupt occurred -----------------------------------------*/
-  flag     = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TO);
-  itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TO);
-  
-  if((flag != RESET) && (itsource != RESET))
-  {
-    /* Clear interrupt */
-    __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
-    
-    /* Timeout callback */
-    HAL_QSPI_TimeOutCallback(hqspi);
-  }
-}
-
-/**
-  * @brief Set the command configuration. 
-  * @param hqspi: QSPI handle
-  * @param cmd : structure that contains the command configuration information
-  * @param Timeout : Timeout duration
-  * @note   This function is used only in Indirect Read or Write Modes
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
-{
-  HAL_StatusTypeDef status = HAL_ERROR;
-  
-  /* Check the parameters */
-  assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
-  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
-  {
-    assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
-  }
-
-  assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
-  if (cmd->AddressMode != QSPI_ADDRESS_NONE)
-  {
-    assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
-  }
-
-  assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
-  if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
-  {
-    assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
-  }
-
-  assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
-  assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
-
-  assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
-  assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
-  assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
-  
-  /* Process locked */
-  __HAL_LOCK(hqspi);
-
-  if(hqspi->State == HAL_QSPI_STATE_READY)
-  {
-    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-    
-    /* Update QSPI state */
-    hqspi->State = HAL_QSPI_STATE_BUSY;   
-    
-    /* Wait till BUSY flag reset */
-    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, Timeout);
-    
-    if (status == HAL_OK)
-    {
-      /* Call the configuration function */
-      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
-      
-      if (cmd->DataMode == QSPI_DATA_NONE)
-      {
-        /* When there is no data phase, the transfer start as soon as the configuration is done 
-        so wait until TC flag is set to go back in idle state */
-        if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)
-        { 
-          status = HAL_TIMEOUT;
-        }
-        else
-        {
-          __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
-          
-          /* Update QSPI state */
-          hqspi->State = HAL_QSPI_STATE_READY;   
-        }
-        
-      }
-      else
-      {
-        /* Update QSPI state */
-        hqspi->State = HAL_QSPI_STATE_READY;   
-      }
-    }
-  }
-  else
-  {
-    status = HAL_BUSY;   
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hqspi);
-
-  /* Return function status */
-  return status;
-}
-
-/**
-  * @brief Set the command configuration in interrupt mode. 
-  * @param hqspi: QSPI handle
-  * @param cmd : structure that contains the command configuration information
-  * @note   This function is used only in Indirect Read or Write Modes
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
-{
-  HAL_StatusTypeDef status = HAL_ERROR;
-  
-  /* Check the parameters */
-  assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
-  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
-  {
-    assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
-  }
-
-  assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
-  if (cmd->AddressMode != QSPI_ADDRESS_NONE)
-  {
-    assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
-  }
-
-  assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
-  if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
-  {
-    assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
-  }
-
-  assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
-  assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
-
-  assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
-  assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
-  assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
-  
-  /* Process locked */
-  __HAL_LOCK(hqspi);
-
-  if(hqspi->State == HAL_QSPI_STATE_READY)
-  {
-    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-    
-    /* Update QSPI state */
-    hqspi->State = HAL_QSPI_STATE_BUSY;   
-    
-    /* Wait till BUSY flag reset */
-    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
-    
-    if (status == HAL_OK)
-    {
-      if (cmd->DataMode == QSPI_DATA_NONE)
-      {
-        /* When there is no data phase, the transfer start as soon as the configuration is done 
-        so activate TC and TE interrupts */
-        /* Clear interrupt */
-        __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
-
-        /* Enable the QSPI Transfer Error Interrupt */
-        __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC);
-      }
-      
-      /* Call the configuration function */
-      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
-      
-      if (cmd->DataMode != QSPI_DATA_NONE)
-      {
-        /* Update QSPI state */
-        hqspi->State = HAL_QSPI_STATE_READY;   
-      }
-    }
-  }
-  else
-  {
-    status = HAL_BUSY;   
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hqspi);
-
-  /* Return function status */
-  return status;
-}
-
-/**
-  * @brief Transmit an amount of data in blocking mode. 
-  * @param hqspi: QSPI handle
-  * @param pData: pointer to data buffer
-  * @param Timeout : Timeout duration
-  * @note   This function is used only in Indirect Write Mode
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  __IO uint32_t *data_reg = &hqspi->Instance->DR;
-
-  /* Process locked */
-  __HAL_LOCK(hqspi);
-
-  if(hqspi->State == HAL_QSPI_STATE_READY)
-  {
-    if(pData != NULL )
-    {
-      hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-    
-      /* Update state */
-      hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
-      
-      /* Configure counters and size of the handle */
-      hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
-      hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
-      hqspi->pTxBuffPtr = pData;
-    
-      /* Configure QSPI: CCR register with functional as indirect write */
-      MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
-
-      while(hqspi->TxXferCount > 0)
-      {
-        /* Wait until FT flag is set to send data */
-        if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, Timeout) != HAL_OK)
-        { 
-          status = HAL_TIMEOUT;
-          break;
-        }
-
-        *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
-        hqspi->TxXferCount--;
-      }
-    
-      if (status == HAL_OK)
-      {
-        /* Wait until TC flag is set to go back in idle state */
-        if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)
-        { 
-          status = HAL_TIMEOUT;
-        }
-        else
-        {
-          /* Clear Transfer Complete bit */
-          __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
-          
-          /* Clear Busy bit */
-          status = HAL_QSPI_Abort(hqspi);
-        }
-      }
-    
-      /* Update QSPI state */
-      hqspi->State = HAL_QSPI_STATE_READY;    
-    }
-    else
-    {
-      status = HAL_ERROR;
-    }
-  }
-  else
-  {
-    status = HAL_BUSY;
-  }
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hqspi);
-
-  return status;
-}
-
-
-/**
-  * @brief Receive an amount of data in blocking mode.
-  * @param hqspi: QSPI handle
-  * @param pData: pointer to data buffer
-  * @param Timeout : Timeout duration
-  * @note   This function is used only in Indirect Read Mode
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
-  __IO uint32_t *data_reg = &hqspi->Instance->DR;
-
-  /* Process locked */
-  __HAL_LOCK(hqspi);
-
-  if(hqspi->State == HAL_QSPI_STATE_READY)
-  {
-    if(pData != NULL )
-    {
-      hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-    
-      /* Update state */
-      hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
-    
-      /* Configure counters and size of the handle */
-      hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
-      hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
-      hqspi->pRxBuffPtr = pData;
-
-      /* Configure QSPI: CCR register with functional as indirect read */
-      MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
-
-      /* Start the transfer by re-writing the address in AR register */
-      WRITE_REG(hqspi->Instance->AR, addr_reg);
-      
-      while(hqspi->RxXferCount > 0)
-      {
-        /* Wait until FT or TC flag is set to read received data */
-        if(QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, Timeout) != HAL_OK)
-        { 
-          status = HAL_TIMEOUT;
-          break;
-        }
-
-        *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
-        hqspi->RxXferCount--;
-      }
-    
-      if (status == HAL_OK)
-      {
-        /* Wait until TC flag is set to go back in idle state */
-        if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)
-        { 
-          status = HAL_TIMEOUT;
-        }
-        else
-        {
-          /* Clear Transfer Complete bit */
-          __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
-
-          /* Workaround - Extra data written in the FIFO at the end of a read transfer */
-          status = HAL_QSPI_Abort(hqspi);
-        }
-      }
-
-      /* Update QSPI state */
-      hqspi->State = HAL_QSPI_STATE_READY;    
-    }
-    else
-    {
-      status = HAL_ERROR;
-    }
-  }
-  else
-  {
-    status = HAL_BUSY;
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hqspi);
-
-  return status;
-}
-
-/**
-  * @brief  Send an amount of data in non-blocking mode with interrupt.
-  * @param  hqspi: QSPI handle
-  * @param  pData: pointer to data buffer
-  * @note   This function is used only in Indirect Write Mode
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
-{  
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hqspi);
-
-  if(hqspi->State == HAL_QSPI_STATE_READY)
-  {
-    if(pData != NULL )
-    {
-      hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
-      /* Update state */
-      hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
-
-      /* Configure counters and size of the handle */
-      hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
-      hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
-      hqspi->pTxBuffPtr = pData;
-    
-      /* Configure QSPI: CCR register with functional as indirect write */
-      MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
-    
-      /* Clear interrupt */
-      __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
-
-      /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
-      __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
-    }
-    else
-    {
-      status = HAL_ERROR;
-    }
-  }
-  else
-  {
-    status = HAL_BUSY;
-  }
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hqspi);
-
-  return status;
-}
-
-/**
-  * @brief  Receive an amount of data in non-blocking mode with interrupt.
-  * @param  hqspi: QSPI handle
-  * @param  pData: pointer to data buffer
-  * @note   This function is used only in Indirect Read Mode
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
-
-  /* Process locked */
-  __HAL_LOCK(hqspi);
-
-  if(hqspi->State == HAL_QSPI_STATE_READY)
-  {
-    if(pData != NULL )
-    {
-      hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-    
-      /* Update state */
-      hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
-    
-      /* Configure counters and size of the handle */
-      hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
-      hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
-      hqspi->pRxBuffPtr = pData;
-
-      /* Configure QSPI: CCR register with functional as indirect read */
-      MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
-
-      /* Start the transfer by re-writing the address in AR register */
-      WRITE_REG(hqspi->Instance->AR, addr_reg);
-
-      /* Clear interrupt */
-      __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
-
-      /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
-      __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
-    }
-    else
-    {
-      status = HAL_ERROR;
-    }
-  }
-  else
-  {
-    status = HAL_BUSY;   
-  }
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hqspi);
-
-  return status;
-}
-
-/**
-  * @brief  Send an amount of data in non-blocking mode with DMA. 
-  * @param  hqspi: QSPI handle
-  * @param  pData: pointer to data buffer
-  * @note   This function is used only in Indirect Write Mode
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  uint32_t *tmp;
-  
-  /* Process locked */
-  __HAL_LOCK(hqspi);
-
-  if(hqspi->State == HAL_QSPI_STATE_READY)
-  {
-    if(pData != NULL ) 
-    {
-      hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
-      /* Update state */
-      hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
-
-      /* Configure counters and size of the handle */
-      hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
-      hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
-      hqspi->pTxBuffPtr = pData;
-    
-      /* Configure QSPI: CCR register with functional mode as indirect write */
-      MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
-    
-      /* Set the QSPI DMA transfer complete callback */
-      hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt;
-    
-      /* Set the QSPI DMA Half transfer complete callback */
-      hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt;
-    
-      /* Set the DMA error callback */
-      hqspi->hdma->XferErrorCallback = QSPI_DMAError;
-      
-      /* Configure the direction of the DMA */
-      hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
-      MODIFY_REG(hqspi->hdma->Instance->CCR, DMA_CCR_DIR, hqspi->hdma->Init.Direction);
-
-      /* Enable the QSPI transmit DMA Channel */
-      tmp = (uint32_t*)&pData;
-      HAL_DMA_Start_IT(hqspi->hdma, *(uint32_t*)tmp, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize);
-    
-      /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
-      SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
-    }
-    else
-    {
-      status = HAL_ERROR;
-    }
-  }
-  else
-  {
-    status = HAL_BUSY;   
-  }
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hqspi);
-
-  return status;
-}
-
-/**
-  * @brief  Receive an amount of data in non-blocking mode with DMA. 
-  * @param  hqspi: QSPI handle
-  * @param  pData: pointer to data buffer.
-  * @note   This function is used only in Indirect Read Mode
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  uint32_t *tmp;
-  uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
-  
-  /* Process locked */
-  __HAL_LOCK(hqspi);
-
-  if(hqspi->State == HAL_QSPI_STATE_READY)
-  {
-    if(pData != NULL ) 
-    {
-      hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-    
-      /* Update state */
-      hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
-    
-      /* Configure counters and size of the handle */
-      hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
-      hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
-      hqspi->pRxBuffPtr = pData;
-
-      /* Set the QSPI DMA transfer complete callback */
-      hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt;
-    
-      /* Set the QSPI DMA Half transfer complete callback */
-      hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt;
-    
-      /* Set the DMA error callback */
-      hqspi->hdma->XferErrorCallback = QSPI_DMAError;
-      
-      /* Configure the direction of the DMA */
-      hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
-      MODIFY_REG(hqspi->hdma->Instance->CCR, DMA_CCR_DIR, hqspi->hdma->Init.Direction);
-
-      /* Enable the DMA Channel */
-      tmp = (uint32_t*)&pData;
-      HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, *(uint32_t*)tmp, hqspi->RxXferSize);
-    
-      /* Configure QSPI: CCR register with functional as indirect read */
-      MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
-
-      /* Start the transfer by re-writing the address in AR register */
-      WRITE_REG(hqspi->Instance->AR, addr_reg);
-
-      /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
-      SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
-    }
-    else
-    {
-      status = HAL_ERROR;
-    }
-  }
-  else
-  {
-    status = HAL_BUSY; 
-  }
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hqspi);
-
-  return status;
-}
-
-/**
-  * @brief  Configure the QSPI Automatic Polling Mode in blocking mode. 
-  * @param  hqspi: QSPI handle
-  * @param  cmd: structure that contains the command configuration information.
-  * @param  cfg: structure that contains the polling configuration information.
-  * @param  Timeout : Timeout duration
-  * @note   This function is used only in Automatic Polling Mode
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
-{
-  HAL_StatusTypeDef status = HAL_ERROR;
-  
-  /* Check the parameters */
-  assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
-  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
-  {
-    assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
-  }
-
-  assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
-  if (cmd->AddressMode != QSPI_ADDRESS_NONE)
-  {
-    assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
-  }
-
-  assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
-  if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
-  {
-    assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
-  }
-
-  assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
-  assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
-
-  assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
-  assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
-  assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
-
-  assert_param(IS_QSPI_INTERVAL(cfg->Interval));
-  assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
-  assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
-  
-  /* Process locked */
-  __HAL_LOCK(hqspi);
-  
-  if(hqspi->State == HAL_QSPI_STATE_READY)
-  {
-    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-    
-    /* Update state */
-    hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
-    
-    /* Wait till BUSY flag reset */
-    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, Timeout);
-    
-    if (status == HAL_OK)
-    {
-      /* Configure QSPI: PSMAR register with the status match value */
-      WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
-      
-      /* Configure QSPI: PSMKR register with the status mask value */
-      WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
-      
-      /* Configure QSPI: PIR register with the interval value */
-      WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
-      
-      /* Configure QSPI: CR register with Match mode and Automatic stop enabled 
-      (otherwise there will be an infinite loop in blocking mode) */
-      MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), 
-               (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE));
-      
-      /* Call the configuration function */
-      cmd->NbData = cfg->StatusBytesSize;
-      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
-      
-      /* Wait until SM flag is set to go back in idle state */
-      if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, Timeout) != HAL_OK)
-      { 
-        status = HAL_TIMEOUT;
-      }
-      else
-      {
-        __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
-        
-        /* Update state */
-        hqspi->State = HAL_QSPI_STATE_READY;
-      }
-    }
-  }
-  else
-  {
-    status = HAL_BUSY;   
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hqspi);
-  
-  /* Return function status */
-  return status;  
-}
-
-/**
-  * @brief  Configure the QSPI Automatic Polling Mode in non-blocking mode. 
-  * @param  hqspi: QSPI handle
-  * @param  cmd: structure that contains the command configuration information.
-  * @param  cfg: structure that contains the polling configuration information.
-  * @note   This function is used only in Automatic Polling Mode
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
-{
-  HAL_StatusTypeDef status = HAL_ERROR;
-  
-  /* Check the parameters */
-  assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
-  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
-  {
-    assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
-  }
-
-  assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
-  if (cmd->AddressMode != QSPI_ADDRESS_NONE)
-  {
-    assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
-  }
-
-  assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
-  if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
-  {
-    assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
-  }
-
-  assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
-  assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
-
-  assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
-  assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
-  assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
-
-  assert_param(IS_QSPI_INTERVAL(cfg->Interval));
-  assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
-  assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
-  assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
-  
-  /* Process locked */
-  __HAL_LOCK(hqspi);
-  
-  if(hqspi->State == HAL_QSPI_STATE_READY)
-  {
-    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-    
-    /* Update state */
-    hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
-    
-    /* Wait till BUSY flag reset */
-    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
-    
-    if (status == HAL_OK)
-    {
-      /* Configure QSPI: PSMAR register with the status match value */
-      WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
-      
-      /* Configure QSPI: PSMKR register with the status mask value */
-      WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
-      
-      /* Configure QSPI: PIR register with the interval value */
-      WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
-      
-      /* Configure QSPI: CR register with Match mode and Automatic stop mode */
-      MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), 
-               (cfg->MatchMode | cfg->AutomaticStop));
-      
-      /* Clear interrupt */
-      __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM);
-
-      /* Enable the QSPI Transfer Error and status match Interrupt */
-      __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
-
-      /* Call the configuration function */
-      cmd->NbData = cfg->StatusBytesSize;
-      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
-    }
-  }
-  else
-  {
-    status = HAL_BUSY;   
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hqspi);
-  
-  /* Return function status */
-  return status;  
-}
-
-/**
-  * @brief  Configure the Memory Mapped mode. 
-  * @param  hqspi: QSPI handle
-  * @param  cmd: structure that contains the command configuration information.
-  * @param  cfg: structure that contains the memory mapped configuration information.
-  * @note   This function is used only in Memory mapped Mode
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
-{
-  HAL_StatusTypeDef status = HAL_ERROR;
-  
-  /* Check the parameters */
-  assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
-  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
-  {
-  assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
-  }
-
-  assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
-  if (cmd->AddressMode != QSPI_ADDRESS_NONE)
-  {
-    assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
-  }
-
-  assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
-  if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
-  {
-    assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
-  }
-
-  assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
-  assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
-
-  assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
-  assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
-  assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
-
-  assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));
-  
-  /* Process locked */
-  __HAL_LOCK(hqspi);
-  
-  if(hqspi->State == HAL_QSPI_STATE_READY)
-  {
-    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-    
-    /* Update state */
-    hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;
-    
-    /* Wait till BUSY flag reset */
-    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
-    
-    if (status == HAL_OK)
-    {
-      /* Configure QSPI: CR register with timeout counter enable */
-    MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
-      
-    if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
-      {
-        assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
-        
-        /* Configure QSPI: LPTR register with the low-power timeout value */
-        WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);
-        
-        /* Clear interrupt */
-        __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
-
-        /* Enable the QSPI TimeOut Interrupt */
-        __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);
-      }
-      
-      /* Call the configuration function */
-      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);
-    }
-  }
-  else
-  {
-    status = HAL_BUSY;   
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hqspi);
-  
-  /* Return function status */
-  return status;  
-}
-
-/**
-  * @brief  Transfer Error callback.
-  * @param  hqspi: QSPI handle
-  * @retval None
-  */
-__weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hqspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_QSPI_ErrorCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Command completed callback.
-  * @param  hqspi: QSPI handle
-  * @retval None
-  */
-__weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hqspi);
-
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_QSPI_CmdCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Rx Transfer completed callback.
-  * @param  hqspi: QSPI handle
-  * @retval None
-  */
-__weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hqspi);
-
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_QSPI_RxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Tx Transfer completed callback.
-  * @param  hqspi: QSPI handle
-  * @retval None
-  */
- __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hqspi);
-
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_QSPI_TxCpltCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  Rx Half Transfer completed callback.
-  * @param  hqspi: QSPI handle
-  * @retval None
-  */
-__weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hqspi);
-
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Tx Half Transfer completed callback.
-  * @param  hqspi: QSPI handle
-  * @retval None
-  */
-__weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hqspi);
-
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  FIFO Threshold callback.
-  * @param  hqspi: QSPI handle
-  * @retval None
-  */
-__weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hqspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Status Match callback.
-  * @param  hqspi: QSPI handle
-  * @retval None
-  */
-__weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hqspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_QSPI_StatusMatchCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Timeout callback.
-  * @param  hqspi: QSPI handle
-  * @retval None
-  */
-__weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hqspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_QSPI_TimeOutCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions 
-  *  @brief   QSPI control and State functions 
-  *
-@verbatim   
- ===============================================================================
-                  ##### Peripheral Control and State functions #####
- ===============================================================================  
-    [..]
-    This subsection provides a set of functions allowing to :
-      (+) Check in run-time the state of the driver. 
-      (+) Check the error code set during last operation.
-      (+) Abort any operation.
-
-  
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the QSPI handle state.
-  * @param  hqspi: QSPI handle
-  * @retval HAL state
-  */
-HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
-{
-  /* Return QSPI handle state */
-  return hqspi->State;
-}
-
-/**
-* @brief  Return the QSPI error code.
-* @param  hqspi: QSPI handle
-* @retval QSPI Error Code
-*/
-uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
-{
-  return hqspi->ErrorCode;
-}
-
-/**
-* @brief  Abort the current transmission.
-* @param  hqspi: QSPI handle
-* @retval HAL status
-*/
-HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
-{
-  HAL_StatusTypeDef status = HAL_ERROR;
-  
-  /* Configure QSPI: CR register with Abort request */
-  SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
-
-  /* Wait until TC flag is set to go back in idle state */
-  if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)
-  { 
-    status = HAL_TIMEOUT;
-  }
-  else
-  {
-    __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
-    
-    /* Wait until BUSY flag is reset */
-    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
-
-    /* Update state */
-    hqspi->State = HAL_QSPI_STATE_READY;
-  }
-
-  return status;
-}
-
-/** @brief Set QSPI timeout.
-  * @param  hqspi: QSPI handle.
-  * @param  Timeout: Timeout for the QSPI memory access.
-  * @retval None
-  */
-void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
-{
-  hqspi->Timeout = Timeout;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @brief  DMA QSPI receive process complete callback. 
-  * @param  hdma: DMA handle
-  * @retval None
-  */
-static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)  
-{
-  QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  hqspi->RxXferCount = 0;
-  
-  /* Wait for QSPI TC Flag */
-  if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)
-  {
-    /* Timeout occurred */ 
-    HAL_QSPI_ErrorCallback(hqspi);
-  }
-  else
-  {
-    /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
-    CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
-
-    /* Disable the DMA channel */
-    HAL_DMA_Abort(hdma);
-
-    /* Clear Transfer Complete bit */
-    __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
-
-    /* Workaround - Extra data written in the FIFO at the end of a read transfer */
-    HAL_QSPI_Abort(hqspi);
-
-    /* Update state */
-    hqspi->State = HAL_QSPI_STATE_READY;
-    
-    HAL_QSPI_RxCpltCallback(hqspi);
-  }
-}
-
-/**
-  * @brief  DMA QSPI transmit process complete callback. 
-  * @param  hdma: DMA handle
-  * @retval None
-  */
-static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)     
-{
-  QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  hqspi->TxXferCount = 0;
-  
-  /* Wait for QSPI TC Flag */
-  if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)
-  {
-    /* Timeout occurred */ 
-    HAL_QSPI_ErrorCallback(hqspi);
-  }
-  else
-  {
-    /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
-    CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
-  
-    /* Disable the DMA channel */
-    HAL_DMA_Abort(hdma);
-
-    /* Clear Transfer Complete bit */
-    __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
-
-    /* Clear Busy bit */
-    HAL_QSPI_Abort(hqspi);
-
-    /* Update state */
-    hqspi->State = HAL_QSPI_STATE_READY;
-    
-    HAL_QSPI_TxCpltCallback(hqspi);
-  }
-}
-
-/**
-  * @brief  DMA QSPI receive process half complete callback. 
-  * @param  hdma : DMA handle
-  * @retval None
-  */
-static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  HAL_QSPI_RxHalfCpltCallback(hqspi); 
-}
-
-/**
-  * @brief  DMA QSPI transmit process half complete callback.
-  * @param  hdma : DMA handle
-  * @retval None
-  */
-static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  HAL_QSPI_TxHalfCpltCallback(hqspi);
-}
-
-/**
-  * @brief  DMA QSPI communication error callback.
-  * @param  hdma: DMA handle
-  * @retval None
-  */
-static void QSPI_DMAError(DMA_HandleTypeDef *hdma)   
-{
-  QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  hqspi->RxXferCount = 0;
-  hqspi->TxXferCount = 0;
-  hqspi->State       = HAL_QSPI_STATE_ERROR;
-  hqspi->ErrorCode   |= HAL_QSPI_ERROR_DMA;
-
-  HAL_QSPI_ErrorCallback(hqspi);
-}
-
-/**
-  * @brief  Wait for a flag state until timeout.
-  * @param  hqspi: QSPI handle
-  * @param  Flag: Flag checked
-  * @param  State: Value of the flag expected
-  * @param  Timeout: Duration of the timeout
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
-                                                        FlagStatus State, uint32_t Timeout)
-{
-  uint32_t tickstart = HAL_GetTick();
-  
-  /* Wait until flag is in expected state */    
-  while((FlagStatus)(__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
-  {
-    /* Check for the Timeout */
-    if (Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
-      {
-        hqspi->State     = HAL_QSPI_STATE_ERROR;
-        hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
-        
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configure the communication registers.
-  * @param  hqspi: QSPI handle
-  * @param  cmd: structure that contains the command configuration information
-  * @param  FunctionalMode: functional mode to configured
-  *           This parameter can be one of the following values:
-  *            @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
-  *            @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
-  *            @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode
-  *            @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode
-  * @retval None
-  */
-static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode)
-{
-  assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode));
-
-  if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
-  {
-    /* Configure QSPI: DLR register with the number of data to read or write */
-    WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1));
-  }
-
-  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
-  {
-    if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
-    {
-      /* Configure QSPI: ABR register with alternate bytes value */
-      WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
-
-      if (cmd->AddressMode != QSPI_ADDRESS_NONE)
-      {
-        /*---- Command with instruction, address and alternate bytes ----*/
-        /* Configure QSPI: CCR register with all communications parameters */
-        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | 
-                                         cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) | 
-                                         cmd->AlternateBytesSize | cmd->AlternateByteMode | 
-                                         cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode | 
-                                         cmd->Instruction | FunctionalMode));
-
-        if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
-        {
-          /* Configure QSPI: AR register with address value */
-          WRITE_REG(hqspi->Instance->AR, cmd->Address);
-        }
-      }
-      else
-      {
-        /*---- Command with instruction and alternate bytes ----*/
-        /* Configure QSPI: CCR register with all communications parameters */
-        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | 
-                                         cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) | 
-                                         cmd->AlternateBytesSize | cmd->AlternateByteMode | 
-                                         cmd->AddressMode | cmd->InstructionMode | 
-                                         cmd->Instruction | FunctionalMode));
-      }
-    }
-    else
-    {
-      if (cmd->AddressMode != QSPI_ADDRESS_NONE)
-      {
-        /*---- Command with instruction and address ----*/
-        /* Configure QSPI: CCR register with all communications parameters */
-        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | 
-                                         cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) | 
-                                         cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode | 
-                                         cmd->InstructionMode | cmd->Instruction | FunctionalMode));
-
-        if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
-        {
-          /* Configure QSPI: AR register with address value */
-          WRITE_REG(hqspi->Instance->AR, cmd->Address);
-        }
-      }
-      else
-      {
-        /*---- Command with only instruction ----*/
-        /* Configure QSPI: CCR register with all communications parameters */
-        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | 
-                                         cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) | 
-                                         cmd->AlternateByteMode | cmd->AddressMode | 
-                                         cmd->InstructionMode | cmd->Instruction | FunctionalMode));
-      }
-    }
-  }
-  else
-  {
-    if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
-    {
-      /* Configure QSPI: ABR register with alternate bytes value */
-      WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
-
-      if (cmd->AddressMode != QSPI_ADDRESS_NONE)
-      {
-        /*---- Command with address and alternate bytes ----*/
-        /* Configure QSPI: CCR register with all communications parameters */
-        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | 
-                                         cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) | 
-                                         cmd->AlternateBytesSize | cmd->AlternateByteMode | 
-                                         cmd->AddressSize | cmd->AddressMode | 
-                                         cmd->InstructionMode | FunctionalMode));
-
-        if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
-        {
-          /* Configure QSPI: AR register with address value */
-          WRITE_REG(hqspi->Instance->AR, cmd->Address);
-        }
-      }
-      else
-      {
-        /*---- Command with only alternate bytes ----*/
-        /* Configure QSPI: CCR register with all communications parameters */
-        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | 
-                                         cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) | 
-                                         cmd->AlternateBytesSize | cmd->AlternateByteMode | 
-                                         cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
-      }
-    }
-    else
-    {
-      if (cmd->AddressMode != QSPI_ADDRESS_NONE)
-      {
-        /*---- Command with only address ----*/
-        /* Configure QSPI: CCR register with all communications parameters */
-        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | 
-                                         cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) | 
-                                         cmd->AlternateByteMode | cmd->AddressSize | 
-                                         cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
-
-        if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
-        {
-          /* Configure QSPI: AR register with address value */
-          WRITE_REG(hqspi->Instance->AR, cmd->Address);
-        }
-      }
-      else
-      {
-        /*---- Command with only data phase ----*/
-        if (cmd->DataMode != QSPI_DATA_NONE)
-        {
-          /* Configure QSPI: CCR register with all communications parameters */
-          WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | 
-                                           cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) | 
-                                           cmd->AlternateByteMode | cmd->AddressMode | 
-                                           cmd->InstructionMode | FunctionalMode));
-        }
-      }
-    }
-  }
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_QSPI_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/src/stm32l4xx_hal_rcc.c b/stmhal/hal/l4/src/stm32l4xx_hal_rcc.c
deleted file mode 100644
index 5144428511..0000000000
--- a/stmhal/hal/l4/src/stm32l4xx_hal_rcc.c
+++ /dev/null
@@ -1,1439 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_rcc.c
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   RCC HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Reset and Clock Control (RCC) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + Peripheral Control functions
-  *
-  @verbatim
-  ==============================================================================
-                      ##### RCC specific features #####
-  ==============================================================================
-    [..]
-      After reset the device is running from Multiple Speed Internal oscillator
-      (4 MHz) with Flash 0 wait state. Flash prefetch buffer, D-Cache
-      and I-Cache are disabled, and all peripherals are off except internal
-      SRAM, Flash and JTAG.
-
-      (+) There is no prescaler on High speed (AHBs) and Low speed (APBs) busses:
-          all peripherals mapped on these busses are running at MSI speed.
-      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
-      (+) All GPIOs are in analog mode, except the JTAG pins which
-          are assigned to be used for debug purpose.
-
-    [..]
-      Once the device started from reset, the user application has to:
-      (+) Configure the clock source to be used to drive the System clock
-          (if the application needs higher frequency/performance)
-      (+) Configure the System clock frequency and Flash settings
-      (+) Configure the AHB and APB busses prescalers
-      (+) Enable the clock for the peripheral(s) to be used
-      (+) Configure the clock source(s) for peripherals which clocks are not
-          derived from the System clock (SAIx, RTC, ADC, USB OTG FS/SDMMC1/RNG)
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup RCC RCC
-  * @brief RCC HAL module driver
-  * @{
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup RCC_Private_Constants RCC Private Constants
- * @{
- */
-#define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT
-#define HSI_TIMEOUT_VALUE          ((uint32_t)2U)    /* 2 ms (minimum Tick + 1) */
-#define MSI_TIMEOUT_VALUE          ((uint32_t)2U)    /* 2 ms (minimum Tick + 1) */  
-#define LSI_TIMEOUT_VALUE          ((uint32_t)2U)    /* 2 ms (minimum Tick + 1) */
-#define PLL_TIMEOUT_VALUE          ((uint32_t)2U)    /* 2 ms (minimum Tick + 1) */
-#define CLOCKSWITCH_TIMEOUT_VALUE  ((uint32_t)5000U) /* 5 s    */
-
-#define PLLSOURCE_NONE             ((uint32_t)0U)
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup RCC_Private_Macros RCC Private Macros
-  * @{
-  */
-#define __MCO1_CLK_ENABLE()   __HAL_RCC_GPIOA_CLK_ENABLE()
-#define MCO1_GPIO_PORT        GPIOA
-#define MCO1_PIN              GPIO_PIN_8
-
-#define RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) \
-            (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (uint32_t)(__HAL_RCC_PLLSOURCE__)))
-/**
-  * @}
-  */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup RCC_Private_Variables RCC Private Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup RCC_Private_Functions RCC Private Functions
-  * @{
-  */
-static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup RCC_Exported_Functions RCC Exported Functions
-  * @{
-  */
-
-/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
-  *  @brief    Initialization and Configuration functions
-  *
-  @verbatim
- ===============================================================================
-           ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]
-      This section provides functions allowing to configure the internal and external oscillators
-      (HSE, HSI, LSE, MSI, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
-       and APB2).
-
-    [..] Internal/external clock and PLL configuration
-         (+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly or through
-             the PLL as System clock source.
-             
-         (+) MSI (Mutiple Speed Internal): Its frequency is software trimmable from 100KHZ to 48MHZ.
-             It can be used to generate the clock for the USB OTG FS (48 MHz).
-             The number of flash wait states is automatically adjusted when MSI range is updated with 
-             HAL_RCC_OscConfig() and the MSI is used as System clock source. 
-
-         (+) LSI (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC
-             clock source.
-
-         (+) HSE (high-speed external): 4 to 48 MHz crystal oscillator used directly or
-             through the PLL as System clock source. Can be used also optionally as RTC clock source.
-
-         (+) LSE (low-speed external): 32.768 KHz oscillator used optionally as RTC clock source.
-
-         (+) PLL (clocked by HSI, HSE or MSI) providing up to three independent output clocks:
-           (++) The first output is used to generate the high speed system clock (up to 80MHz).
-           (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
-                the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
-           (++) The third output is used to generate an accurate clock to achieve
-                high-quality audio performance on SAI interface.
-
-         (+) PLLSAI1 (clocked by HSI, HSE or MSI) providing up to three independent output clocks:
-           (++) The first output is used to generate SAR ADC1 clock.
-           (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
-                the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
-           (++) The Third output is used to generate an accurate clock to achieve
-                high-quality audio performance on SAI interface.
-
-         (+) PLLSAI2 (clocked by HSI , HSE or MSI) providing up to two independent output clocks:
-           (++) The first output is used to generate SAR ADC2 clock.
-           (++) The second  output is used to generate an accurate clock to achieve
-                high-quality audio performance on SAI interface.
-
-         (+) CSS (Clock security system): once enabled, if a HSE clock failure occurs
-            (HSE used directly or through PLL as System clock source), the System clock
-             is automatically switched to HSI and an interrupt is generated if enabled.
-             The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt)
-             exception vector.
-
-         (+) MCO (microcontroller clock output): used to output MSI, LSI, HSI, LSE, HSE or
-             main PLL clock (through a configurable prescaler) on PA8 pin.
-
-    [..] System, AHB and APB busses clocks configuration
-         (+) Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI,
-             HSE and main PLL.
-             The AHB clock (HCLK) is derived from System clock through configurable
-             prescaler and used to clock the CPU, memory and peripherals mapped
-             on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
-             from AHB clock through configurable prescalers and used to clock
-             the peripherals mapped on these busses. You can use
-             "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
-
-         -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
-
-           (+@) SAI: the SAI clock can be derived either from a specific PLL (PLLSAI1) or (PLLSAI2) or
-                from an external clock mapped on the SAI_CKIN pin.
-                You have to use HAL_RCCEx_PeriphCLKConfig() function to configure this clock.
-           (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
-                divided by 2 to 31.
-                You have to use __HAL_RCC_RTC_ENABLE() and HAL_RCCEx_PeriphCLKConfig() function
-                to configure this clock.
-           (+@) USB OTG FS, SDMMC1 and RNG: USB OTG FS requires a frequency equal to 48 MHz
-                to work correctly, while the SDMMC1 and RNG peripherals require a frequency 
-                equal or lower than to 48 MHz. This clock is derived of the main PLL or PLLSAI1
-                through PLLQ divider. You have to enable the peripheral clock and use 
-                HAL_RCCEx_PeriphCLKConfig() function to configure this clock.
-           (+@) IWDG clock which is always the LSI clock.
-
-
-         (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 80 MHz. 
-             The clock source frequency should be adapted depending on the device voltage range
-             as listed in the Reference Manual "Clock source frequency versus voltage scaling" chapter.
-
-  @endverbatim
-             
-           Table 1. HCLK clock frequency.             
-           +-------------------------------------------------------+     
-           | Latency         |    HCLK clock frequency (MHz)       |
-           |                 |-------------------------------------|     
-           |                 | voltage range 1  | voltage range 2  |
-           |                 |      1.2 V       |     1.0 V        |
-           |-----------------|------------------|------------------|          
-           |0WS(1 CPU cycles)|  0 < HCLK <= 16  |  0 < HCLK <= 6   |
-           |-----------------|------------------|------------------|
-           |1WS(2 CPU cycles)| 16 < HCLK <= 32  |  6 < HCLK <= 12  |
-           |-----------------|------------------|------------------|
-           |2WS(3 CPU cycles)| 32 < HCLK <= 48  | 12 < HCLK <= 18  |
-           |-----------------|------------------|------------------|
-           |3WS(4 CPU cycles)| 48 < HCLK <= 64  | 18 < HCLK <= 26  |
-           |-----------------|------------------|------------------|
-           |4WS(5 CPU cycles)| 64 < HCLK <= 80  | 18 < HCLK <= 26  |
-           +-------------------------------------------------------+   
-  * @{
-  */
-
-/**
-  * @brief  Reset the RCC clock configuration to the default reset state.
-  * @note   The default reset state of the clock configuration is given below:
-  *            - MSI ON and used as system clock source
-  *            - HSE, HSI, PLL, PLLSAI1 and PLLISAI2 OFF
-  *            - AHB, APB1 and APB2 prescaler set to 1.
-  *            - CSS, MCO1 OFF
-  *            - All interrupts disabled
-  * @note   This function doesn't modify the configuration of the
-  *            - Peripheral clocks
-  *            - LSI, LSE and RTC clocks
-  * @retval None
-  */
-void HAL_RCC_DeInit(void)
-{
-  /* Set MSION bit */
-  SET_BIT(RCC->CR, RCC_CR_MSION);
-
-  /* Insure MSIRDY bit is set before writing default MSIRANGE value */
-  while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RESET) { __NOP(); }
-  
-  /* Set MSIRANGE default value */
-  MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, RCC_MSIRANGE_6);
-  
-  /* Reset CFGR register (MSI is selected as system clock source) */
-  CLEAR_REG(RCC->CFGR);
-
-  /* Reset HSION, HSIKERON, HSIASFS, HSEON, HSECSSON, PLLON, PLLSAIxON bits */
-  CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_HSIKERON| RCC_CR_HSIASFS | RCC_CR_PLLON | RCC_CR_PLLSAI1ON | RCC_CR_PLLSAI2ON);
-  
-  /* Reset PLLCFGR register */
-  CLEAR_REG(RCC->PLLCFGR);
-  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN_4 );
-
-  /* Reset PLLSAI1CFGR register */
-  CLEAR_REG(RCC->PLLSAI1CFGR);
-  SET_BIT(RCC->PLLSAI1CFGR,  RCC_PLLSAI1CFGR_PLLSAI1N_4 );
-
-  /* Reset PLLSAI2CFGR register */
-  CLEAR_REG(RCC->PLLSAI2CFGR);
-  SET_BIT(RCC->PLLSAI2CFGR,  RCC_PLLSAI2CFGR_PLLSAI2N_4 );
-
-  /* Reset HSEBYP bit */
-  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
-
-  /* Disable all interrupts */
-  CLEAR_REG(RCC->CIER);
-
-  /* Update the SystemCoreClock global variable */
-  SystemCoreClock = MSI_VALUE;
-}
-
-/**
-  * @brief  Initialize the RCC Oscillators according to the specified parameters in the
-  *         RCC_OscInitTypeDef.
-  * @param  RCC_OscInitStruct  pointer to an RCC_OscInitTypeDef structure that
-  *         contains the configuration information for the RCC Oscillators.
-  * @note   The PLL is not disabled when used as system clock.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
-{
-  uint32_t tickstart = 0;
-
-  /* Check the parameters */
-  assert_param(RCC_OscInitStruct != NULL);
-  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
-
-  /*----------------------------- MSI Configuration --------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
-    assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
-    assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
-
-    /* When the MSI is used as system clock it will not be disabled */
-    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI) )
-    {
-      if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != RESET) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
-      {
-        return HAL_ERROR;
-      }
-
-       /* Otherwise, just the calibration and MSI range change are allowed */
-      else
-      {
-        /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
-           must be correctly programmed according to the frequency of the CPU clock
-           (HCLK) and the supply voltage of the device. */
-        if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
-        {
-          /* First increase number of wait states update if necessary */
-          if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
-          {
-            return HAL_ERROR;
-          }
-
-          /* Selects the Multiple Speed oscillator (MSI) clock range .*/
-          __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
-          /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
-          __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
-        }
-        else
-        {
-          /* Else, keep current flash latency while decreasing applies */
-          /* Selects the Multiple Speed oscillator (MSI) clock range .*/
-          __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
-          /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
-          __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
-
-          /* Decrease number of wait states update if necessary */
-          if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
-          {
-            return HAL_ERROR;
-          }          
-        }
-
-        /* Update the SystemCoreClock global variable */
-        SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
-        
-        /* Configure the source of time base considering new system clocks settings*/
-        HAL_InitTick (TICK_INT_PRIORITY);
-      }
-    }
-    else
-    {
-      /* Check the MSI State */
-      if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
-      {
-        /* Enable the Internal High Speed oscillator (MSI). */
-        __HAL_RCC_MSI_ENABLE();
-
-        /* Get timeout */
-        tickstart = HAL_GetTick();
-
-        /* Wait till MSI is ready */
-        while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RESET)
-        {
-          if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-         /* Selects the Multiple Speed oscillator (MSI) clock range .*/
-        __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
-         /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
-        __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
-
-      }
-      else
-      {
-        /* Disable the Internal High Speed oscillator (MSI). */
-        __HAL_RCC_MSI_DISABLE();
-
-        /* Get timeout */
-        tickstart = HAL_GetTick();
-
-        /* Wait till MSI is ready */
-        while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != RESET)
-        {
-          if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }
-  }
-  /*------------------------------- HSE Configuration ------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
-
-    /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
-    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || 
-       ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
-    {
-      if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
-      {
-        return HAL_ERROR;
-      }
-    }
-    else
-    {
-      /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
-      __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
-
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
-
-      /* Wait till HSE is disabled */
-      while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET)
-      {
-        if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-
-      /* Set the new HSE configuration ---------------------------------------*/
-      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
-
-      /* Check the HSE State */
-      if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
-      {
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-
-        /* Wait till HSE is ready */
-        while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == RESET)
-        {
-          if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-      else
-      {
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-
-        /* Wait till HSE is disabled */
-        while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET)
-        {
-          if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }
-  }
-  /*----------------------------- HSI Configuration --------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
-    assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
-
-    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ 
-    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||
-       ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
-    {
-      /* When HSI is used as system clock it will not be disabled */
-      if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
-      {
-        return HAL_ERROR;
-      }
-      /* Otherwise, just the calibration is allowed */
-      else
-      {
-        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
-        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
-      }
-    }
-    else
-    {
-      /* Check the HSI State */
-      if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
-      {
-        /* Enable the Internal High Speed oscillator (HSI). */
-        __HAL_RCC_HSI_ENABLE();
-
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-
-        /* Wait till HSI is ready */
-        while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET)
-        {
-          if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-
-        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
-        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
-      }
-      else
-      {
-        /* Disable the Internal High Speed oscillator (HSI). */
-        __HAL_RCC_HSI_DISABLE();
-
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-
-        /* Wait till HSI is disabled */
-        while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != RESET)
-        {
-          if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }
-  }
-  /*------------------------------ LSI Configuration -------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
-
-    /* Check the LSI State */
-    if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
-    {
-      /* Enable the Internal Low Speed oscillator (LSI). */
-      __HAL_RCC_LSI_ENABLE();
-
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
-
-      /* Wait till LSI is ready */
-      while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == RESET)
-      {
-        if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-    else
-    {
-      /* Disable the Internal Low Speed oscillator (LSI). */
-      __HAL_RCC_LSI_DISABLE();
-
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
-
-      /* Wait till LSI is disabled */
-      while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != RESET)
-      {
-        if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  /*------------------------------ LSE Configuration -------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
-  {
-    FlagStatus       pwrclkchanged = RESET;
-    
-    /* Check the parameters */
-    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
-
-    /* Update LSE configuration in Backup Domain control register    */
-    /* Requires to enable write access to Backup Domain of necessary */
-    if(HAL_IS_BIT_CLR(RCC->APB1ENR1, RCC_APB1ENR1_PWREN))
-    {
-      __HAL_RCC_PWR_CLK_ENABLE();
-      pwrclkchanged = SET;
-    }
-    
-    if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
-    {
-      /* Enable write access to Backup domain */
-      SET_BIT(PWR->CR1, PWR_CR1_DBP);
-      
-      /* Wait for Backup domain Write protection disable */
-      tickstart = HAL_GetTick();
-
-      while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
-      {
-        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-
-    /* Set the new LSE configuration -----------------------------------------*/
-    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
-
-    /* Check the LSE State */
-    if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
-    {
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
-
-      /* Wait till LSE is ready */
-      while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RESET)
-      {
-        if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-    else
-    {
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
-
-      /* Wait till LSE is disabled */
-      while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != RESET)
-      {
-        if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-
-    /* Restore clock configuration if changed */
-    if(pwrclkchanged == SET)
-    {
-      __HAL_RCC_PWR_CLK_DISABLE();
-    }
-  }
-  /*-------------------------------- PLL Configuration -----------------------*/
-  /* Check the parameters */
-  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
-
-  if(RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
-  {
-    /* Check if the PLL is used as system clock or not */
-    if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
-    {
-      if(RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
-      {
-        /* Check the parameters */
-        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
-        assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
-        assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
-        assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
-        assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
-        assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
-
-        /* Disable the main PLL. */
-        __HAL_RCC_PLL_DISABLE();
-
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-
-        /* Wait till PLL is ready */
-        while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET)
-        {
-          if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-
-        /* Configure the main PLL clock source, multiplication and division factors. */
-        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
-                             RCC_OscInitStruct->PLL.PLLM,
-                             RCC_OscInitStruct->PLL.PLLN,
-                             RCC_OscInitStruct->PLL.PLLP,
-                             RCC_OscInitStruct->PLL.PLLQ,
-                             RCC_OscInitStruct->PLL.PLLR);
-
-        /* Enable the main PLL. */
-        __HAL_RCC_PLL_ENABLE();
-
-        /* Enable PLL System Clock output. */
-         __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
-
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-
-        /* Wait till PLL is ready */
-        while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET)
-        {
-          if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-      else
-      {
-        /* Disable the main PLL. */
-        __HAL_RCC_PLL_DISABLE();
-
-        /* Disable all PLL outputs to save power */
-        MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSOURCE_NONE);
-        __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI3CLK);
-
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-
-        /* Wait till PLL is disabled */
-        while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET)
-        {
-          if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }
-    else
-    {
-      return HAL_ERROR;
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initialize the CPU, AHB and APB busses clocks according to the specified
-  *         parameters in the RCC_ClkInitStruct.
-  * @param  RCC_ClkInitStruct  pointer to an RCC_OscInitTypeDef structure that
-  *         contains the configuration information for the RCC peripheral.
-  * @param  FLatency  FLASH Latency
-  *          This parameter can be one of the following values:
-  *            @arg FLASH_LATENCY_0   FLASH 0 Latency cycle
-  *            @arg FLASH_LATENCY_1   FLASH 1 Latency cycle
-  *            @arg FLASH_LATENCY_2   FLASH 2 Latency cycle
-  *            @arg FLASH_LATENCY_3   FLASH 3 Latency cycle
-  *            @arg FLASH_LATENCY_4   FLASH 4 Latency cycle
-  *
-  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
-  *         and updated by HAL_RCC_GetHCLKFreq() function called within this function
-  *
-  * @note   The MSI is used by default as system clock source after
-  *         startup from Reset, wake-up from STANDBY mode. After restart from Reset,
-  *         the MSI frequency is set to its default value 4 MHz.
-  *
-  * @note   The HSI can be selected as system clock source after
-  *         from STOP modes or in case of failure of the HSE used directly or indirectly 
-  *         as system clock (if the Clock Security System CSS is enabled).
-  *
-  * @note   A switch from one clock source to another occurs only if the target
-  *         clock source is ready (clock stable after startup delay or PLL locked).
-  *         If a clock source which is not yet ready is selected, the switch will
-  *         occur when the clock source is ready.
-  *
-  * @note   You can use HAL_RCC_GetClockConfig() function to know which clock is
-  *         currently used as system clock source.
-  *
-  * @note   Depending on the device voltage range, the software has to set correctly
-  *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
-  *         (for more details refer to section above "Initialization/de-initialization functions")
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
-{
-  uint32_t tickstart = 0;
-
-  /* Check the parameters */
-  assert_param(RCC_ClkInitStruct != NULL);
-  assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
-  assert_param(IS_FLASH_LATENCY(FLatency));
-
-  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
-    must be correctly programmed according to the frequency of the CPU clock
-    (HCLK) and the supply voltage of the device. */
-
-  /* Increasing the number of wait states because of higher CPU frequency */
-  if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
-  {
-    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
-    __HAL_FLASH_SET_LATENCY(FLatency);
-
-    /* Check that the new number of wait states is taken into account to access the Flash
-    memory by reading the FLASH_ACR register */
-    if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
-    {
-      return HAL_ERROR;
-    }
-  }
-
-  /*-------------------------- HCLK Configuration --------------------------*/
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
-  {
-    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
-  }
-
-  /*------------------------- SYSCLK Configuration ---------------------------*/
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
-  {
-    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
-
-    /* HSE is selected as System Clock Source */
-    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
-    {
-      /* Check the HSE ready flag */
-      if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == RESET)
-      {
-        return HAL_ERROR;
-      }
-    }
-    /* PLL is selected as System Clock Source */
-    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
-    {
-      /* Check the PLL ready flag */
-      if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET)
-      {
-        return HAL_ERROR;
-      }
-    }
-    /* MSI is selected as System Clock Source */
-    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
-    {
-      /* Check the MSI ready flag */
-      if(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RESET)
-      {
-        return HAL_ERROR;
-      }
-    }
-    /* HSI is selected as System Clock Source */
-    else
-    {
-      /* Check the HSI ready flag */
-      if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET)
-      {
-        return HAL_ERROR;
-      }
-    }
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
-
-    /* Get Start Tick*/
-    tickstart = HAL_GetTick();
-
-    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
-    {
-      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE)
-      {
-        if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
-    {
-      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
-      {
-        if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
-    {
-      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_MSI)
-      {
-        if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-    else
-    {
-      while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI)
-      {
-        if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  
-  /* Decreasing the number of wait states because of lower CPU frequency */
-  if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
-  {
-    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
-    __HAL_FLASH_SET_LATENCY(FLatency);
-
-    /* Check that the new number of wait states is taken into account to access the Flash
-    memory by reading the FLASH_ACR register */
-    if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
-    {
-      return HAL_ERROR;
-    }
-  }
-  
-  /*-------------------------- PCLK1 Configuration ---------------------------*/
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
-  {
-    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
-  }
-
-  /*-------------------------- PCLK2 Configuration ---------------------------*/
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
-  {
-    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
-  }
-
-  /* Update the SystemCoreClock global variable */
-  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
-
-  /* Configure the source of time base considering new system clocks settings*/
-  HAL_InitTick (TICK_INT_PRIORITY);
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions 
- *  @brief   RCC clocks control functions
- *
-@verbatim
- ===============================================================================
-                      ##### Peripheral Control functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to:
-    
-    (+) Ouput clock to MCO pin.
-    (+) Retrieve current clock frequencies.
-    (+) Enable the Clock Security System.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Select the clock source to output on MCO pin(PA8).
-  * @note   PA8 should be configured in alternate function mode.
-  * @param  RCC_MCOx  specifies the output direction for the clock source.
-  *          For STM32L4xx family this parameter can have only one value:
-  *            @arg @ref RCC_MCO1  Clock source to output on MCO1 pin(PA8).
-  * @param  RCC_MCOSource  specifies the clock source to output.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_MCO1SOURCE_NOCLOCK  MCO output disabled, no clock on MCO
-  *            @arg @ref RCC_MCO1SOURCE_SYSCLK  system  clock selected as MCO source
-  *            @arg @ref RCC_MCO1SOURCE_MSI  MSI clock selected as MCO source
-  *            @arg @ref RCC_MCO1SOURCE_HSI  HSI clock selected as MCO source
-  *            @arg @ref RCC_MCO1SOURCE_HSE  HSE clock selected as MCO sourcee
-  *            @arg @ref RCC_MCO1SOURCE_PLLCLK  main PLL clock selected as MCO source
-  *            @arg @ref RCC_MCO1SOURCE_LSI  LSI clock selected as MCO source
-  *            @arg @ref RCC_MCO1SOURCE_LSE  LSE clock selected as MCO source
-  * @param  RCC_MCODiv  specifies the MCO prescaler.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_MCODIV_1  no division applied to MCO clock
-  *            @arg @ref RCC_MCODIV_2  division by 2 applied to MCO clock
-  *            @arg @ref RCC_MCODIV_4  division by 4 applied to MCO clock
-  *            @arg @ref RCC_MCODIV_8  division by 8 applied to MCO clock
-  *            @arg @ref RCC_MCODIV_16  division by 16 applied to MCO clock
-  * @retval None
-  */
-void HAL_RCC_MCOConfig( uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
-{
-  GPIO_InitTypeDef GPIO_InitStruct;
-  /* Check the parameters */
-  assert_param(IS_RCC_MCO(RCC_MCOx));
-  assert_param(IS_RCC_MCODIV(RCC_MCODiv));
-  assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
-
-  /* MCO Clock Enable */
-  __MCO1_CLK_ENABLE();
-
-  /* Configue the MCO1 pin in alternate function mode */
-  GPIO_InitStruct.Pin = MCO1_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
-  HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
-
-  /* Mask MCOSEL[] and MCOPRE[] bits then set MCO1 clock source and prescaler */
-  MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), (RCC_MCOSource | RCC_MCODiv ));
-}
-
-/**
-  * @brief  Return the SYSCLK frequency.
-  *
-  * @note   The system frequency computed by this function is not the real
-  *         frequency in the chip. It is calculated based on the predefined
-  *         constant and the selected clock source:
-  * @note     If SYSCLK source is MSI, function returns values based on MSI
-  *             Value as defined by the MSI range.
-  * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
-  * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
-  * @note     If SYSCLK source is PLL, function returns values based on HSE_VALUE(**),
-  *           HSI_VALUE(*) or MSI Value multiplied/divided by the PLL factors.
-  * @note     (*) HSI_VALUE is a constant defined in stm32l4xx_hal_conf.h file (default value
-  *               16 MHz) but the real value may vary depending on the variations
-  *               in voltage and temperature.
-  * @note     (**) HSE_VALUE is a constant defined in stm32l4xx_hal_conf.h file (default value
-  *                8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *                frequency of the crystal used. Otherwise, this function may
-  *                have wrong result.
-  *
-  * @note   The result of this function could be not correct when using fractional
-  *         value for HSE crystal.
-  *
-  * @note   This function can be used by the user application to compute the
-  *         baudrate for the communication peripherals or configure other parameters.
-  *
-  * @note   Each time SYSCLK changes, this function must be called to update the
-  *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
-  *
-  *
-  * @retval SYSCLK frequency
-  */
-uint32_t HAL_RCC_GetSysClockFreq(void)
-{
-  uint32_t msirange = 0U, pllvco = 0U, pllsource = 0U, pllr = 2U, pllm = 2U;
-  uint32_t sysclockfreq = 0U;
-
-  if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI) ||
-     ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_MSI)))
-  {
-    /* MSI or PLL with MSI source used as system clock source */
-
-    /* Get SYSCLK source */
-    if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == RESET)
-    { /* MSISRANGE from RCC_CSR applies */
-      msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> POSITION_VAL(RCC_CSR_MSISRANGE);
-    }
-    else
-    { /* MSIRANGE from RCC_CR applies */
-      msirange = (RCC->CR & RCC_CR_MSIRANGE) >> POSITION_VAL(RCC_CR_MSIRANGE);
-    }
-    /*MSI frequency range in HZ*/
-    msirange = MSIRangeTable[msirange];
-
-    if(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI)
-    {
-      /* MSI used as system clock source */
-      sysclockfreq = msirange;
-    }
-  }
-  else if(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)
-  {
-    /* HSI used as system clock source */
-    sysclockfreq = HSI_VALUE;
-  }
-  else if(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)
-  {
-    /* HSE used as system clock source */
-    sysclockfreq = HSE_VALUE;
-  }
-
-  if(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL)
-  {
-    /* PLL used as system clock  source */
-
-    /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
-    SYSCLK = PLL_VCO / PLLR
-    */
-    pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
-    pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U ;
-
-    switch (pllsource)
-    {
-    case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
-      pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
-      break;
-
-    case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
-      pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
-      break;
-
-    case RCC_PLLSOURCE_MSI:  /* MSI used as PLL clock source */
-    default:
-      pllvco = (msirange / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
-      break;
-    }
-    pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR)) + 1U ) * 2U;
-    sysclockfreq = pllvco/pllr;
-  }
-
-  return sysclockfreq;
-}
-
-/**
-  * @brief  Return the HCLK frequency.
-  * @note   Each time HCLK changes, this function must be called to update the
-  *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.
-  *
-  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
-  * @retval HCLK frequency in Hz
-  */
-uint32_t HAL_RCC_GetHCLKFreq(void)
-{
-  return SystemCoreClock;
-}
-
-/**
-  * @brief  Return the PCLK1 frequency.
-  * @note   Each time PCLK1 changes, this function must be called to update the
-  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
-  * @retval PCLK1 frequency in Hz
-  */
-uint32_t HAL_RCC_GetPCLK1Freq(void)
-{
-  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
-  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
-}
-
-/**
-  * @brief  Return the PCLK2 frequency.
-  * @note   Each time PCLK2 changes, this function must be called to update the
-  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
-  * @retval PCLK2 frequency in Hz
-  */
-uint32_t HAL_RCC_GetPCLK2Freq(void)
-{
-  /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
-  return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
-}
-
-/**
-  * @brief  Configure the RCC_OscInitStruct according to the internal
-  *         RCC configuration registers.
-  * @param  RCC_OscInitStruct  pointer to an RCC_OscInitTypeDef structure that
-  *         will be configured.
-  * @retval None
-  */
-void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
-{
-  /* Check the parameters */
-  assert_param(RCC_OscInitStruct != NULL);
-
-  /* Set all possible values for the Oscillator type parameter ---------------*/
-  RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \
-                                      RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
-
-  /* Get the HSE configuration -----------------------------------------------*/
-  if((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
-  {
-    RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
-  }
-  else if((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
-  {
-    RCC_OscInitStruct->HSEState = RCC_HSE_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
-  }
-
-   /* Get the MSI configuration -----------------------------------------------*/
-  if((RCC->CR & RCC_CR_MSION) == RCC_CR_MSION)
-  {
-    RCC_OscInitStruct->MSIState = RCC_MSI_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->MSIState = RCC_MSI_OFF;
-  }
-
-  RCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->CR & RCC_ICSCR_MSITRIM) >> POSITION_VAL(RCC_ICSCR_MSITRIM));
-  RCC_OscInitStruct->MSIClockRange = (uint32_t)((RCC->CR & RCC_CR_MSIRANGE) );
-
-  /* Get the HSI configuration -----------------------------------------------*/
-  if((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION)
-  {
-    RCC_OscInitStruct->HSIState = RCC_HSI_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
-  }
-
-  RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->ICSCR & RCC_ICSCR_HSITRIM) >> POSITION_VAL(RCC_ICSCR_HSITRIM));
-
-  /* Get the LSE configuration -----------------------------------------------*/
-  if((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
-  {
-    RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
-  }
-  else if((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
-  {
-    RCC_OscInitStruct->LSEState = RCC_LSE_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
-  }
-
-  /* Get the LSI configuration -----------------------------------------------*/
-  if((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION)
-  {
-    RCC_OscInitStruct->LSIState = RCC_LSI_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
-  }
-
-  /* Get the PLL configuration -----------------------------------------------*/
-  if((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON)
-  {
-    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
-  }
-  RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
-  RCC_OscInitStruct->PLL.PLLM = (uint32_t)(((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U);
-  RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
-  RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ)) + 1U) << 1U);
-  RCC_OscInitStruct->PLL.PLLR = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR)) + 1U) << 1U);
-  if((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) != RESET)
-  {
-    RCC_OscInitStruct->PLL.PLLP = RCC_PLLP_DIV17;
-  }
-  else
-  {
-    RCC_OscInitStruct->PLL.PLLP = RCC_PLLP_DIV7;
-  }
-}
-
-/**
-  * @brief  Configure the RCC_ClkInitStruct according to the internal
-  *         RCC configuration registers.
-  * @param  RCC_ClkInitStruct  pointer to an RCC_ClkInitTypeDef structure that
-  *         will be configured.
-  * @param  pFLatency  Pointer on the Flash Latency.
-  * @retval None
-  */
-void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
-{
-  /* Check the parameters */
-  assert_param(RCC_ClkInitStruct != NULL);
-  assert_param(pFLatency != NULL);
-
-  /* Set all possible values for the Clock type parameter --------------------*/
-  RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
-
-  /* Get the SYSCLK configuration --------------------------------------------*/
-  RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
-
-  /* Get the HCLK configuration ----------------------------------------------*/
-  RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
-
-  /* Get the APB1 configuration ----------------------------------------------*/
-  RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
-
-  /* Get the APB2 configuration ----------------------------------------------*/
-  RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U);
-
-  /* Get the Flash Wait State (Latency) configuration ------------------------*/
-  *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
-}
-
-/**
-  * @brief  Enable the Clock Security System.
-  * @note   If a failure is detected on the HSE oscillator clock, this oscillator
-  *         is automatically disabled and an interrupt is generated to inform the
-  *         software about the failure (Clock Security System Interrupt, CSSI),
-  *         allowing the MCU to perform rescue operations. The CSSI is linked to
-  *         the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
-  * @note   The Clock Security System can only be cleared by reset.
-  * @retval None
-  */
-void HAL_RCC_EnableCSS(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_CSSON) ;
-}
-
-/**
-  * @brief Handle the RCC Clock Security System interrupt request.
-  * @note This API should be called under the NMI_Handler().
-  * @retval None
-  */
-void HAL_RCC_NMI_IRQHandler(void)
-{
-  /* Check RCC CSSF interrupt flag  */
-  if(__HAL_RCC_GET_IT(RCC_IT_CSS))
-  {
-    /* RCC Clock Security System interrupt user callback */
-    HAL_RCC_CSSCallback();
-
-    /* Clear RCC CSS pending bit */
-    __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
-  }
-}
-
-/**
-  * @brief  RCC Clock Security System interrupt callback.
-  * @retval none
-  */
-__weak void HAL_RCC_CSSCallback(void)
-{
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_RCC_CSSCallback should be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup RCC_Private_Functions
-  * @{
-  */
-/**
-  * @brief  Update number of Flash wait states in line with MSI range and current 
-            voltage range.
-  * @param  msirange  MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_11
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange)
-{
-  uint32_t vos = 0;
-  uint32_t latency = FLASH_LATENCY_0;  /* default value 0WS */
-  
-  if(__HAL_RCC_PWR_IS_CLK_ENABLED())
-  {
-    vos = HAL_PWREx_GetVoltageRange();
-  }
-  else
-  {
-    __HAL_RCC_PWR_CLK_ENABLE();
-    vos = HAL_PWREx_GetVoltageRange();
-    __HAL_RCC_PWR_CLK_DISABLE();
-  }
-  
-  if(vos == PWR_REGULATOR_VOLTAGE_SCALE1)
-  {
-    if(msirange > RCC_MSIRANGE_8)
-    {
-      /* MSI > 16Mhz */
-      if(msirange > RCC_MSIRANGE_10)
-      {
-        /* MSI 48Mhz */
-        latency = FLASH_LATENCY_2; /* 2WS */
-      }
-      else
-      {
-        /* MSI 24Mhz or 32Mhz */
-        latency = FLASH_LATENCY_1; /* 1WS */
-      }
-    }
-    /* else MSI <= 16Mhz default FLASH_LATENCY_0 0WS */
-  }
-  else
-  {
-    if(msirange > RCC_MSIRANGE_8)
-    {
-      /* MSI > 16Mhz */
-      latency = FLASH_LATENCY_3; /* 3WS */
-    }
-    else
-    {
-      if(msirange == RCC_MSIRANGE_8)
-      {
-        /* MSI 16Mhz */
-        latency = FLASH_LATENCY_2; /* 2WS */
-      }
-      else if(msirange == RCC_MSIRANGE_7) 
-      {
-        /* MSI 8Mhz */
-        latency = FLASH_LATENCY_1; /* 1WS */
-      }
-      /* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */
-    }
-  }
-       
-  __HAL_FLASH_SET_LATENCY(latency);
-  
-  /* Check that the new number of wait states is taken into account to access the Flash
-     memory by reading the FLASH_ACR register */
-  if((FLASH->ACR & FLASH_ACR_LATENCY) != latency)
-  {
-    return HAL_ERROR;
-  }
-  
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_RCC_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/src/stm32l4xx_hal_rcc_ex.c b/stmhal/hal/l4/src/stm32l4xx_hal_rcc_ex.c
deleted file mode 100644
index 4c32c0a179..0000000000
--- a/stmhal/hal/l4/src/stm32l4xx_hal_rcc_ex.c
+++ /dev/null
@@ -1,2009 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_rcc_ex.c
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   Extended RCC HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities RCC extended peripheral:
-  *           + Extended Peripheral Control functions
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup RCCEx RCCEx
-  * @brief RCC Extended HAL module driver
-  * @{
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
- * @{
- */
-#define PLLSAI1_TIMEOUT_VALUE    ((uint32_t)2U)    /* 2 ms (minimum Tick + 1) */
-#define PLLSAI2_TIMEOUT_VALUE    ((uint32_t)2U)    /* 2 ms (minimum Tick + 1) */
-#define PLL_TIMEOUT_VALUE        ((uint32_t)2U)    /* 2 ms (minimum Tick + 1) */
-
-#define __LSCO_CLK_ENABLE()   __HAL_RCC_GPIOA_CLK_ENABLE()
-#define LSCO_GPIO_PORT        GPIOA
-#define LSCO_PIN              GPIO_PIN_2
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup RCCEx_Private_Functions RCCEx Private Functions
- * @{
- */
-static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNP(RCC_PLLSAI1InitTypeDef *PllSai1);
-static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNQ(RCC_PLLSAI1InitTypeDef *PllSai1);
-static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNR(RCC_PLLSAI1InitTypeDef *PllSai1);
-static HAL_StatusTypeDef RCCEx_PLLSAI2_ConfigNP(RCC_PLLSAI2InitTypeDef *PllSai2);
-static HAL_StatusTypeDef RCCEx_PLLSAI2_ConfigNR(RCC_PLLSAI2InitTypeDef *PllSai2);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
-  * @{
-  */
-
-/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions 
- *  @brief  Extended Peripheral Control functions
- *
-@verbatim
- ===============================================================================
-                ##### Extended Peripheral Control functions  #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to control the RCC Clocks
-    frequencies.
-    [..]
-    (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
-        select the RTC clock source; in this case the Backup domain will be reset in
-        order to modify the RTC Clock source, as consequence RTC registers (including
-        the backup registers) and RCC_BDCR register are set to their reset values.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Initialize the RCC extended peripherals clocks according to the specified
-  *         parameters in the RCC_PeriphCLKInitTypeDef.
-  * @param  PeriphClkInit  pointer to an RCC_PeriphCLKInitTypeDef structure that
-  *         contains a field PeriphClockSelection which can be a combination of the following values:
-  *            @arg @ref RCC_PERIPHCLK_RTC  RTC peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_ADC  ADC peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_DFSDM  DFSDM peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_I2C1  I2C1 peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_I2C2  I2C2 peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_I2C3  I2C3 peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_LPTIM1  LPTIM1 peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_LPTIM2  LPTIM2 peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_LPUART1  LPUART1 peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_RNG  RNG peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_SAI1  SAI1 peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_SAI2  SAI2 peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_SDMMC1  SDMMC1 peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_SWPMI1  SWPMI1 peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_USART1  USART1 peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_USART2  USART1 peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_USART3  USART1 peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_UART4  USART1 peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_UART5  USART1 peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock (only for devices with USB)
-  *
-  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
-  *         the RTC clock source: in this case the access to Backup domain is enabled.
-  *
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
-{
-  uint32_t tmpregister = 0;
-  uint32_t tickstart = 0U;
-  HAL_StatusTypeDef ret = HAL_OK;      /* Intermediate status */
-  HAL_StatusTypeDef status = HAL_OK;   /* Final status */
-
-  /* Check the parameters */
-  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
-
-  /*-------------------------- SAI1 clock source configuration ---------------------*/
-  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1))
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_SAI1CLK(PeriphClkInit->Sai1ClockSelection));
-
-    switch(PeriphClkInit->Sai1ClockSelection)
-    {
-    case RCC_SAI1CLKSOURCE_PLL:      /* PLL is used as clock source for SAI1*/
-      /* Enable SAI Clock output generated form System PLL . */
-      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
-      /* SAI1 clock source config set later after clock selection check */
-      break;
-
-    case RCC_SAI1CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI1*/
-      /* PLLSAI1 parameters N & P configuration and clock output (PLLSAI1ClockOut) */
-      ret = RCCEx_PLLSAI1_ConfigNP(&(PeriphClkInit->PLLSAI1));
-      /* SAI1 clock source config set later after clock selection check */
-      break;
-
-    case RCC_SAI1CLKSOURCE_PLLSAI2:  /* PLLSAI2 is used as clock source for SAI1*/
-      /* PLLSAI2 parameters N & P configuration and clock output (PLLSAI2ClockOut) */
-      ret = RCCEx_PLLSAI2_ConfigNP(&(PeriphClkInit->PLLSAI2));
-      /* SAI1 clock source config set later after clock selection check */
-      break;
-
-    case RCC_SAI1CLKSOURCE_PIN:      /* External clock is used as source of SAI1 clock*/
-      /* SAI1 clock source config set later after clock selection check */
-      break;
-
-    default:
-      ret = HAL_ERROR;
-      break;
-    }
-
-    if(ret == HAL_OK)
-    {
-      /* Set the source of SAI1 clock*/
-      __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
-    }
-    else
-    {
-      /* set overall return value */
-      status = ret;
-    }
-  }
-
-  /*-------------------------- SAI2 clock source configuration ---------------------*/
-  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2))
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_SAI2CLK(PeriphClkInit->Sai2ClockSelection));
-
-    switch(PeriphClkInit->Sai2ClockSelection)
-    {
-    case RCC_SAI2CLKSOURCE_PLL:      /* PLL is used as clock source for SAI2*/
-      /* Enable SAI Clock output generated form System PLL . */
-      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
-      /* SAI2 clock source config set later after clock selection check */
-      break;
-
-    case RCC_SAI2CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI2*/
-      /* PLLSAI1 parameters N & P configuration and clock output (PLLSAI1ClockOut) */
-      ret = RCCEx_PLLSAI1_ConfigNP(&(PeriphClkInit->PLLSAI1));
-      /* SAI2 clock source config set later after clock selection check */
-      break;
-
-    case RCC_SAI2CLKSOURCE_PLLSAI2:  /* PLLSAI2 is used as clock source for SAI2*/
-      /* PLLSAI2 parameters N & P configuration and clock output (PLLSAI2ClockOut) */
-      ret = RCCEx_PLLSAI2_ConfigNP(&(PeriphClkInit->PLLSAI2));
-      /* SAI2 clock source config set later after clock selection check */
-      break;
-
-    case RCC_SAI2CLKSOURCE_PIN:      /* External clock is used as source of SAI2 clock*/
-      /* SAI2 clock source config set later after clock selection check */
-      break;
-
-    default:
-      ret = HAL_ERROR;
-      break;
-    }
-
-    if(ret == HAL_OK)
-    {
-      /* Set the source of SAI2 clock*/
-      __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
-    }
-    else
-    {
-      /* set overall return value */
-      status = ret;
-    }
-  }
-
-  /*-------------------------- RTC clock source configuration ----------------------*/
-  if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
-  {
-    FlagStatus       pwrclkchanged = RESET;
-    
-    /* Check for RTC Parameters used to output RTCCLK */
-    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
-
-    /* Enable Power Clock */
-    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
-    {
-      __HAL_RCC_PWR_CLK_ENABLE();
-      pwrclkchanged = SET;
-    }
-      
-    /* Enable write access to Backup domain */
-    SET_BIT(PWR->CR1, PWR_CR1_DBP);
-
-    /* Wait for Backup domain Write protection disable */
-    tickstart = HAL_GetTick();
-
-    while((PWR->CR1 & PWR_CR1_DBP) == RESET)
-    {
-      if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
-      {
-        ret = HAL_TIMEOUT;
-        break;
-      }
-    }
-
-    if(ret == HAL_OK)
-    { 
-      /* Reset the Backup domain only if the RTC Clock source selection is modified */
-      if(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL) != PeriphClkInit->RTCClockSelection)
-      {
-        /* Store the content of BDCR register before the reset of Backup Domain */
-        tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
-        /* RTC Clock selection can be changed only if the Backup Domain is reset */
-        __HAL_RCC_BACKUPRESET_FORCE();
-        __HAL_RCC_BACKUPRESET_RELEASE();
-        /* Restore the Content of BDCR register */
-        RCC->BDCR = tmpregister;
-      }
-
-      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
-      if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSERDY))
-      {
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-
-        /* Wait till LSE is ready */
-        while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RESET)
-        {
-          if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
-          {
-            ret = HAL_TIMEOUT;
-            break;
-          }
-        }
-      }
-      
-      if(ret == HAL_OK)
-      {
-        /* Apply new RTC clock source selection */
-        __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
-      }
-      else
-      {
-        /* set overall return value */
-        status = ret;
-      }
-    }
-    else
-    {
-      /* set overall return value */
-      status = ret;
-    }
-
-    /* Restore clock configuration if changed */
-    if(pwrclkchanged == SET)
-    {
-      __HAL_RCC_PWR_CLK_DISABLE();
-    }
-  }
-
-  /*-------------------------- USART1 clock source configuration -------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
-
-    /* Configure the USART1 clock source */
-    __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
-  }
-
-  /*-------------------------- USART2 clock source configuration -------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
-
-    /* Configure the USART2 clock source */
-    __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
-  }
-
-  /*-------------------------- USART3 clock source configuration -------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
-
-    /* Configure the USART3 clock source */
-    __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
-  }
-
-  /*-------------------------- UART4 clock source configuration --------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
-
-    /* Configure the UART4 clock source */
-    __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
-  }
-
-  /*-------------------------- UART5 clock source configuration --------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
-
-    /* Configure the UART5 clock source */
-    __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
-  }
-
-  /*-------------------------- LPUART1 clock source configuration ------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
-
-    /* Configure the LPUAR1 clock source */
-    __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
-  }
-
-  /*-------------------------- LPTIM1 clock source configuration -------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
-  {
-    assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
-    __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
-  }
-
-  /*-------------------------- LPTIM2 clock source configuration -------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))
-  {
-    assert_param(IS_RCC_LPTIM2CLK(PeriphClkInit->Lptim2ClockSelection));
-    __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
-  }
-
-  /*-------------------------- I2C1 clock source configuration ---------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
-
-    /* Configure the I2C1 clock source */
-    __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
-  }
-
-  /*-------------------------- I2C2 clock source configuration ---------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
-
-    /* Configure the I2C2 clock source */
-    __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
-  }
-
-  /*-------------------------- I2C3 clock source configuration ---------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
-
-    /* Configure the I2C3 clock source */
-    __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
-  }
-
-#if defined(USB_OTG_FS)
-
-  /*-------------------------- USB clock source configuration ----------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
-  {
-    assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
-    __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
-
-    if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL)
-    {
-      /* Enable PLL48M1CLK output */
-      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
-    }
-    else if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1)
-    {
-      /* PLLSAI1 parameters N & Q configuration and clock output (PLLSAI1ClockOut) */
-      ret = RCCEx_PLLSAI1_ConfigNQ(&(PeriphClkInit->PLLSAI1));
-      
-      if(ret != HAL_OK)
-      {
-        /* set overall return value */
-        status = ret;
-      }
-    }
-  }
-
-#endif /* USB_OTG_FS */
-
-  /*-------------------------- SDMMC1 clock source configuration -------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == (RCC_PERIPHCLK_SDMMC1))
-  {
-    assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
-    __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
-    
-    if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLL)
-    {
-      /* Enable PLL48M1CLK output */
-      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
-    }
-    else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLSAI1)
-    {
-      /* PLLSAI1 parameters N & Q configuration and clock output (PLLSAI1ClockOut) */
-      ret = RCCEx_PLLSAI1_ConfigNQ(&(PeriphClkInit->PLLSAI1));
-      
-      if(ret != HAL_OK)
-      {
-        /* set overall return value */
-        status = ret;
-      }
-    }
-  }
-
-  /*-------------------------- RNG clock source configuration ----------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
-  {
-    assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
-    __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
-
-    if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
-    {
-      /* Enable PLL48M1CLK output */
-      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
-    }
-    else if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLLSAI1)
-    {
-      /* PLLSAI1 parameters N & Q configuration and clock output (PLLSAI1ClockOut) */
-      ret = RCCEx_PLLSAI1_ConfigNQ(&(PeriphClkInit->PLLSAI1));
-      
-      if(ret != HAL_OK)
-      {
-        /* set overall return value */
-        status = ret;
-      }
-    }
-  }
-
-  /*-------------------------- ADC clock source configuration ----------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
-
-    /* Configure the ADC interface clock source */
-    __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
-    
-    if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1)
-    {
-      /* PLLSAI1 parameters N & R configuration and clock output (PLLSAI1ClockOut) */
-      ret = RCCEx_PLLSAI1_ConfigNR(&(PeriphClkInit->PLLSAI1));
-
-      if(ret != HAL_OK)
-      {
-        /* set overall return value */
-        status = ret;
-      }
-    }
-    else if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI2)
-    {
-      /* PLLSAI2 parameters N & R configuration and clock output (PLLSAI2ClockOut) */
-      ret = RCCEx_PLLSAI2_ConfigNR(&(PeriphClkInit->PLLSAI2));
-      
-      if(ret != HAL_OK)
-      {
-        /* set overall return value */
-        status = ret;
-      }
-    }
-  }
-
-  /*-------------------------- SWPMI1 clock source configuration -------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));
-
-    /* Configure the SWPMI1 clock source */
-    __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
-  }
-
-  /*-------------------------- DFSDM clock source configuration --------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM) == RCC_PERIPHCLK_DFSDM)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_DFSDMCLKSOURCE(PeriphClkInit->DfsdmClockSelection));
-
-    /* Configure the DFSDM interface clock source */
-    __HAL_RCC_DFSDM_CONFIG(PeriphClkInit->DfsdmClockSelection);
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
-  * @param  PeriphClkInit  pointer to an RCC_PeriphCLKInitTypeDef structure that
-  *         returns the configuration information for the Extended Peripherals
-  *         clocks(SAI1, SAI2, LPTIM1, LPTIM2, I2C1, I2C2, I2C3, LPUART,
-  *         USART1, USART2, USART3, UART4, UART5, RTC, ADCx, DFSDMx, SWPMI1, USB, SDMMC1 and RNG).
-  * @retval None
-  */
-void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
-{
-  /* Set all possible values for the extended clock type parameter------------*/
-
-#if defined(STM32L471xx)
-
-  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4  | RCC_PERIPHCLK_UART5  | \
-                                        RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3                          | \
-                                        RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1   | RCC_PERIPHCLK_SAI2                          | \
-                                        RCC_PERIPHCLK_SDMMC1  | RCC_PERIPHCLK_RNG    | RCC_PERIPHCLK_ADC    | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM  | \
-                                        RCC_PERIPHCLK_RTC ;
-  
-#else
-
-  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4  | RCC_PERIPHCLK_UART5  | \
-                                        RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3   |                        \
-                                        RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1   | RCC_PERIPHCLK_SAI2   | RCC_PERIPHCLK_USB    | \
-                                        RCC_PERIPHCLK_SDMMC1  | RCC_PERIPHCLK_RNG    | RCC_PERIPHCLK_ADC    | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM  | \
-                                        RCC_PERIPHCLK_RTC ;
-
-#endif /* STM32L471xx */
-
-  /* Get the PLLSAI1 Clock configuration -----------------------------------------------*/
-  PeriphClkInit->PLLSAI1.PLLSAI1N = (uint32_t)((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1N) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N));
-  PeriphClkInit->PLLSAI1.PLLSAI1P = (uint32_t)(((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1P) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P)) << 4U) + 7U;
-  PeriphClkInit->PLLSAI1.PLLSAI1R = (uint32_t)(((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1R) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R))+1U) * 2U;
-  PeriphClkInit->PLLSAI1.PLLSAI1Q = (uint32_t)(((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1Q) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q))+1U) * 2U;
-
-  /* Get the PLLSAI2 Clock configuration -----------------------------------------------*/
-  PeriphClkInit->PLLSAI2.PLLSAI2N = (uint32_t)((RCC->PLLSAI2CFGR & RCC_PLLSAI2CFGR_PLLSAI2N) >> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N));
-  PeriphClkInit->PLLSAI2.PLLSAI2P = (uint32_t)(((RCC->PLLSAI2CFGR & RCC_PLLSAI2CFGR_PLLSAI2P) >> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P)) << 4U) + 7U;
-  PeriphClkInit->PLLSAI2.PLLSAI2R = (uint32_t)(((RCC->PLLSAI2CFGR & RCC_PLLSAI2CFGR_PLLSAI2R)>> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R))+1U) * 2U;
-
-  /* Get the USART1 clock source ---------------------------------------------*/
-  PeriphClkInit->Usart1ClockSelection  = __HAL_RCC_GET_USART1_SOURCE();
-  /* Get the USART2 clock source ---------------------------------------------*/
-  PeriphClkInit->Usart2ClockSelection  = __HAL_RCC_GET_USART2_SOURCE();
-  /* Get the USART3 clock source ---------------------------------------------*/
-  PeriphClkInit->Usart3ClockSelection  = __HAL_RCC_GET_USART3_SOURCE();
-  /* Get the UART4 clock source ----------------------------------------------*/
-  PeriphClkInit->Uart4ClockSelection   = __HAL_RCC_GET_UART4_SOURCE();
-  /* Get the UART5 clock source ----------------------------------------------*/
-  PeriphClkInit->Uart5ClockSelection   = __HAL_RCC_GET_UART5_SOURCE();
-  /* Get the LPUART1 clock source --------------------------------------------*/
-  PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();
-  /* Get the I2C1 clock source -----------------------------------------------*/
-  PeriphClkInit->I2c1ClockSelection    = __HAL_RCC_GET_I2C1_SOURCE();
-   /* Get the I2C2 clock source ----------------------------------------------*/
-  PeriphClkInit->I2c2ClockSelection    = __HAL_RCC_GET_I2C2_SOURCE();
-  /* Get the I2C3 clock source -----------------------------------------------*/
-  PeriphClkInit->I2c3ClockSelection    = __HAL_RCC_GET_I2C3_SOURCE();
-  /* Get the LPTIM1 clock source ---------------------------------------------*/
-  PeriphClkInit->Lptim1ClockSelection  = __HAL_RCC_GET_LPTIM1_SOURCE();
-  /* Get the LPTIM2 clock source ---------------------------------------------*/
-  PeriphClkInit->Lptim2ClockSelection  = __HAL_RCC_GET_LPTIM2_SOURCE();
-  /* Get the SAI1 clock source -----------------------------------------------*/
-  PeriphClkInit->Sai1ClockSelection    = __HAL_RCC_GET_SAI1_SOURCE();
-  /* Get the SAI2 clock source -----------------------------------------------*/
-  PeriphClkInit->Sai2ClockSelection    = __HAL_RCC_GET_SAI2_SOURCE();
-  /* Get the RTC clock source ------------------------------------------------*/
-  PeriphClkInit->RTCClockSelection     = __HAL_RCC_GET_RTC_SOURCE();
-
-#if defined(USB_OTG_FS)
-  /* Get the USB clock source ------------------------------------------------*/
-  PeriphClkInit->UsbClockSelection   = __HAL_RCC_GET_USB_SOURCE();
-#endif /* USB_OTG_FS */
-
-  /* Get the SDMMC1 clock source ---------------------------------------------*/
-  PeriphClkInit->Sdmmc1ClockSelection   = __HAL_RCC_GET_SDMMC1_SOURCE();
-  /* Get the RNG clock source ------------------------------------------------*/
-  PeriphClkInit->RngClockSelection   = __HAL_RCC_GET_RNG_SOURCE();
-  /* Get the ADC clock source -----------------------------------------------*/
-  PeriphClkInit->AdcClockSelection     = __HAL_RCC_GET_ADC_SOURCE();
-  /* Get the SWPMI1 clock source ----------------------------------------------*/
-  PeriphClkInit->Swpmi1ClockSelection  = __HAL_RCC_GET_SWPMI1_SOURCE();
-  /* Get the DFSDM clock source -------------------------------------------*/
-  PeriphClkInit->DfsdmClockSelection   = __HAL_RCC_GET_DFSDM_SOURCE();
-}
-
-/**
-  * @brief  Return the peripheral clock frequency for peripherals with clock source from PLLSAIs 
-  * @note   Return 0 if peripheral clock identifier not managed by this API
-  * @param  PeriphClk  Peripheral clock identifier
-  *         This parameter can be one of the following values:
-  *            @arg @ref RCC_PERIPHCLK_RTC  RTC peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_ADC  ADC peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_DFSDM  DFSDM peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_I2C1  I2C1 peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_I2C2  I2C2 peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_I2C3  I2C3 peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_LPTIM1  LPTIM1 peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_LPTIM2  LPTIM2 peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_LPUART1  LPUART1 peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_RNG  RNG peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_SAI1  SAI1 peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_SAI2  SAI2 peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_SDMMC1  SDMMC1 peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_SWPMI1  SWPMI1 peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_USART1  USART1 peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_USART2  USART1 peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_USART3  USART1 peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_UART4  USART1 peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_UART5  USART1 peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock (only for devices with USB)
-  * @retval Frequency in Hz
-  */
-uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
-{
-  uint32_t frequency = 0U;
-  uint32_t srcclk = 0;
-  uint32_t pllvco = 0, plln = 0, pllp = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
-
-  if(PeriphClk == RCC_PERIPHCLK_RTC)
-  {
-    /* Get the current RTC source */
-    srcclk = __HAL_RCC_GET_RTC_SOURCE();
-
-    /* Check if LSE is ready and if RTC clock selection is LSE */
-    if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
-    {
-      frequency = LSE_VALUE;
-    }
-    /* Check if LSI is ready and if RTC clock selection is LSI */
-    else if ((srcclk == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
-    {
-      frequency = LSI_VALUE;
-    }
-    /* Check if HSE is ready  and if RTC clock selection is HSI_DIV32*/
-    else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIV32) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
-    {
-      frequency = HSE_VALUE / 32;
-    }
-    /* Clock not enabled for RTC*/
-    else
-    {
-      frequency = 0U;
-    }
-  }
-  else
-  {
-    /* Other external peripheral clock source than RTC */
-    
-    /* Compute PLL clock input */
-    if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_MSI)        /* MSI ? */
-    {
-      pllvco = (1U << ((__HAL_RCC_GET_MSI_RANGE() >> 4U) - 4U)) * 1000000U;
-    }
-    else if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)   /* HSI ? */
-    {
-      pllvco = HSI_VALUE;
-    }
-    else if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)   /* HSE ? */
-    {
-      pllvco = HSE_VALUE;
-    }
-    else /* No source */
-    {
-      pllvco = 0;
-    }
-
-    /* f(PLL Source) / PLLM */
-    pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U));
-
-    switch(PeriphClk)
-    {
-    case RCC_PERIPHCLK_SAI1:
-    case RCC_PERIPHCLK_SAI2:
-
-      if(PeriphClk == RCC_PERIPHCLK_SAI1)
-      {
-        srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL);
-          
-        if(srcclk == RCC_SAI1CLKSOURCE_PIN)
-        {
-          frequency = EXTERNAL_SAI1_CLOCK_VALUE;
-        }
-        /* Else, PLL clock output to check below */
-      }
-      else /* RCC_PERIPHCLK_SAI2 */
-      {
-        srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI2SEL);
-          
-        if(srcclk == RCC_SAI2CLKSOURCE_PIN)
-        {
-          frequency = EXTERNAL_SAI2_CLOCK_VALUE;
-        }
-        /* Else, PLL clock output to check below */
-      }
-
-      if(frequency == 0U)
-      {
-        if((srcclk == RCC_SAI1CLKSOURCE_PLL) || (srcclk == RCC_SAI2CLKSOURCE_PLL))
-        {
-          if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI3CLK) != RESET)
-          {
-            /* f(PLLSAI3CLK) = f(VCO input) * PLLN / PLLP */
-            plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN);
-            if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != RESET)
-            {
-              pllp = 17U;
-            }
-            else
-            {
-              pllp = 7U;
-            }
-            frequency = (pllvco * plln) / pllp;
-          }
-        }
-        else if(srcclk == 0U)  /* RCC_SAI1CLKSOURCE_PLLSAI1 || RCC_SAI2CLKSOURCE_PLLSAI1 */
-        {
-          if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != RESET)
-          {
-            /* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */
-            plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N);
-            if(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) != RESET)
-            {
-              pllp = 17U;
-            }
-            else
-            {
-              pllp = 7U;
-            }
-            frequency = (pllvco * plln) / pllp;
-          }
-        }
-        else if((srcclk == RCC_SAI1CLKSOURCE_PLLSAI2) || (srcclk == RCC_SAI2CLKSOURCE_PLLSAI2))
-        {
-          if(__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_SAI2CLK) != RESET)
-          {
-            /* f(PLLSAI2CLK) = f(VCOSAI2 input) * PLLSAI2N / PLLSAI2P */
-            plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N);
-            if(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P) != RESET)
-            {
-              pllp = 17U;
-            }
-            else
-            {
-              pllp = 7U;
-            }
-            frequency = (pllvco * plln) / pllp;
-          }
-        }
-        else
-        {
-          /* No clock source */
-          frequency = 0U;
-        }
-      }
-      break;
-    
-#if defined(USB_OTG_FS)
-    
-    case RCC_PERIPHCLK_USB:
-
-#endif /* USB_OTG_FS */
-
-    case RCC_PERIPHCLK_RNG:
-    case RCC_PERIPHCLK_SDMMC1:
-
-      srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL);
-      
-      if(srcclk == RCC_CCIPR_CLK48SEL)   /* MSI ? */
-      {
-        frequency = (1U << ((__HAL_RCC_GET_MSI_RANGE() >> 4U) - 4U)) * 1000000U;
-      }
-      else if(srcclk == RCC_CCIPR_CLK48SEL_1)  /* PLL ? */
-      {
-        /* f(PLL48M1CLK) = f(VCO input) * PLLN / PLLQ */
-        plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN);
-        frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ)) + 1U) << 1U);
-      }
-      else if(srcclk == RCC_CCIPR_CLK48SEL_0)  /* PLLSAI1 ? */
-      {
-        /* f(PLL48M2CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1Q */
-        plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N);
-        frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)) + 1U) << 1U);
-      }
-      else /* No clock source */
-      {
-        frequency = 0U;
-      }
-      break;
-      
-    case RCC_PERIPHCLK_USART1:
-      /* Get the current USART1 source */
-      srcclk = __HAL_RCC_GET_USART1_SOURCE();
-      
-      if(srcclk == RCC_USART1CLKSOURCE_PCLK2)
-      {
-        frequency = HAL_RCC_GetPCLK2Freq();
-      }
-      else if(srcclk == RCC_USART1CLKSOURCE_SYSCLK)
-      {
-        frequency = HAL_RCC_GetSysClockFreq();
-      }
-      else if((srcclk == RCC_USART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
-      {
-        frequency = HSI_VALUE;
-      }
-      else if((srcclk == RCC_USART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
-      {
-        frequency = LSE_VALUE;
-      }
-      /* Clock not enabled for USART1 */
-      else
-      {
-        frequency = 0U;
-      }
-      break;
-
-    case RCC_PERIPHCLK_USART2:
-      /* Get the current USART2 source */
-      srcclk = __HAL_RCC_GET_USART2_SOURCE();
-      
-      if(srcclk == RCC_USART2CLKSOURCE_PCLK1)
-      {
-        frequency = HAL_RCC_GetPCLK1Freq();
-      }
-      else if(srcclk == RCC_USART2CLKSOURCE_SYSCLK)
-      {
-        frequency = HAL_RCC_GetSysClockFreq();
-      }
-      else if((srcclk == RCC_USART2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
-      {
-        frequency = HSI_VALUE;
-      }
-      else if((srcclk == RCC_USART2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
-      {
-        frequency = LSE_VALUE;
-      }
-      /* Clock not enabled for USART2 */
-      else
-      {
-        frequency = 0U;
-      }
-      break;
-
-    case RCC_PERIPHCLK_USART3:
-      /* Get the current USART3 source */
-      srcclk = __HAL_RCC_GET_USART3_SOURCE();
-      
-      if(srcclk == RCC_USART3CLKSOURCE_PCLK1)
-      {
-        frequency = HAL_RCC_GetPCLK1Freq();
-      }
-      else if(srcclk == RCC_USART3CLKSOURCE_SYSCLK)
-      {
-        frequency = HAL_RCC_GetSysClockFreq();
-      }
-      else if((srcclk == RCC_USART3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
-      {
-        frequency = HSI_VALUE;
-      }
-      else if((srcclk == RCC_USART3CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
-      {
-        frequency = LSE_VALUE;
-      }
-      /* Clock not enabled for USART3 */
-      else
-      {
-        frequency = 0U;
-      }
-      break;
-
-    case RCC_PERIPHCLK_UART4:
-      /* Get the current UART4 source */
-      srcclk = __HAL_RCC_GET_UART4_SOURCE();
-      
-      if(srcclk == RCC_UART4CLKSOURCE_PCLK1)
-      {
-        frequency = HAL_RCC_GetPCLK1Freq();
-      }
-      else if(srcclk == RCC_UART4CLKSOURCE_SYSCLK)
-      {
-        frequency = HAL_RCC_GetSysClockFreq();
-      }
-      else if((srcclk == RCC_UART4CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
-      {
-        frequency = HSI_VALUE;
-      }
-      else if((srcclk == RCC_UART4CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
-      {
-        frequency = LSE_VALUE;
-      }
-      /* Clock not enabled for UART4 */
-      else
-      {
-        frequency = 0U;
-      }
-      break;
-
-    case RCC_PERIPHCLK_UART5:
-      /* Get the current UART5 source */
-      srcclk = __HAL_RCC_GET_UART5_SOURCE();
-      
-      if(srcclk == RCC_UART5CLKSOURCE_PCLK1)
-      {
-        frequency = HAL_RCC_GetPCLK1Freq();
-      }
-      else if(srcclk == RCC_UART5CLKSOURCE_SYSCLK)
-      {
-        frequency = HAL_RCC_GetSysClockFreq();
-      }
-      else if((srcclk == RCC_UART5CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
-      {
-        frequency = HSI_VALUE;
-      }
-      else if((srcclk == RCC_UART5CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
-      {
-        frequency = LSE_VALUE;
-      }
-      /* Clock not enabled for UART5 */
-      else
-      {
-        frequency = 0U;
-      }
-      break;
-
-    case RCC_PERIPHCLK_LPUART1:
-      /* Get the current LPUART1 source */
-      srcclk = __HAL_RCC_GET_LPUART1_SOURCE();
-      
-      if(srcclk == RCC_LPUART1CLKSOURCE_PCLK1)
-      {
-        frequency = HAL_RCC_GetPCLK1Freq();
-      }
-      else if(srcclk == RCC_LPUART1CLKSOURCE_SYSCLK)
-      {
-        frequency = HAL_RCC_GetSysClockFreq();
-      }
-      else if((srcclk == RCC_LPUART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
-      {
-        frequency = HSI_VALUE;
-      }
-      else if((srcclk == RCC_LPUART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
-      {
-        frequency = LSE_VALUE;
-      }
-      /* Clock not enabled for LPUART1 */
-      else
-      {
-        frequency = 0U;
-      }
-      break;
-
-    case RCC_PERIPHCLK_ADC:
-    
-      srcclk = __HAL_RCC_GET_ADC_SOURCE();
-      
-      if(srcclk == RCC_ADCCLKSOURCE_SYSCLK)
-      {
-        frequency = HAL_RCC_GetSysClockFreq();
-      }
-      else if(srcclk == RCC_ADCCLKSOURCE_PLLSAI1)
-      {
-        if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_ADC1CLK) != RESET)
-        {
-          /* f(PLLADC1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1R */
-          plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N);
-          frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)) + 1U) << 1U);
-        }
-      }
-      else if(srcclk == RCC_ADCCLKSOURCE_PLLSAI2)
-      {
-        if(__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_ADC2CLK) != RESET)
-        {
-          /* f(PLLADC2CLK) = f(VCOSAI2 input) * PLLSAI2N / PLLSAI2R */
-          plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N);
-          frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R) >> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)) + 1U) << 1U);
-        }
-      }
-      /* Clock not enabled for ADC */
-      else
-      {
-        frequency = 0U;
-      }
-      break;
-
-    case RCC_PERIPHCLK_DFSDM:
-      /* Get the current DFSDM source */
-      srcclk = __HAL_RCC_GET_DFSDM_SOURCE();
-      
-      if(srcclk == RCC_DFSDMCLKSOURCE_PCLK)
-      {
-        frequency = HAL_RCC_GetPCLK1Freq();
-      }
-      else
-      {
-        frequency = HAL_RCC_GetSysClockFreq();
-      }
-      break;
-
-    case RCC_PERIPHCLK_I2C1:
-      /* Get the current I2C1 source */
-      srcclk = __HAL_RCC_GET_I2C1_SOURCE();
-      
-      if(srcclk == RCC_I2C1CLKSOURCE_PCLK1)
-      {
-        frequency = HAL_RCC_GetPCLK1Freq();
-      }
-      else if(srcclk == RCC_I2C1CLKSOURCE_SYSCLK)
-      {
-        frequency = HAL_RCC_GetSysClockFreq();
-      }
-      else if((srcclk == RCC_I2C1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
-      {
-        frequency = HSI_VALUE;
-      }
-      /* Clock not enabled for I2C1 */
-      else
-      {
-        frequency = 0U;
-      }
-      break;
-
-    case RCC_PERIPHCLK_I2C2:
-      /* Get the current I2C2 source */
-      srcclk = __HAL_RCC_GET_I2C2_SOURCE();
-      
-      if(srcclk == RCC_I2C2CLKSOURCE_PCLK1)
-      {
-        frequency = HAL_RCC_GetPCLK1Freq();
-      }
-      else if(srcclk == RCC_I2C2CLKSOURCE_SYSCLK)
-      {
-        frequency = HAL_RCC_GetSysClockFreq();
-      }
-      else if((srcclk == RCC_I2C2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
-      {
-        frequency = HSI_VALUE;
-      }
-      /* Clock not enabled for I2C2 */
-      else
-      {
-        frequency = 0U;
-      }
-      break;
-
-    case RCC_PERIPHCLK_I2C3:
-      /* Get the current I2C3 source */
-      srcclk = __HAL_RCC_GET_I2C3_SOURCE();
-      
-      if(srcclk == RCC_I2C3CLKSOURCE_PCLK1)
-      {
-        frequency = HAL_RCC_GetPCLK1Freq();
-      }
-      else if(srcclk == RCC_I2C3CLKSOURCE_SYSCLK)
-      {
-        frequency = HAL_RCC_GetSysClockFreq();
-      }
-      else if((srcclk == RCC_I2C3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
-      {
-        frequency = HSI_VALUE;
-      }
-      /* Clock not enabled for I2C3 */
-      else
-      {
-        frequency = 0U;
-      }
-      break;
-
-    case RCC_PERIPHCLK_LPTIM1:
-      /* Get the current LPTIM1 source */
-      srcclk = __HAL_RCC_GET_LPTIM1_SOURCE();
-      
-      if(srcclk == RCC_LPTIM1CLKSOURCE_PCLK)
-      {
-        frequency = HAL_RCC_GetPCLK1Freq();
-      }
-      else if((srcclk == RCC_LPTIM1CLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
-      {
-        frequency = LSI_VALUE;
-      }
-      else if((srcclk == RCC_LPTIM1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
-      {
-        frequency = HSI_VALUE;
-      }
-      else if ((srcclk == RCC_LPTIM1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
-      {
-        frequency = LSE_VALUE;
-      }
-      /* Clock not enabled for LPTIM1 */
-      else
-      {
-        frequency = 0U;
-      }
-      break;
-
-    case RCC_PERIPHCLK_LPTIM2:
-      /* Get the current LPTIM2 source */
-      srcclk = __HAL_RCC_GET_LPTIM2_SOURCE();
-      
-      if(srcclk == RCC_LPTIM2CLKSOURCE_PCLK)
-      {
-        frequency = HAL_RCC_GetPCLK1Freq();
-      }
-      else if((srcclk == RCC_LPTIM2CLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
-      {
-        frequency = LSI_VALUE;
-      }
-      else if((srcclk == RCC_LPTIM2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
-      {
-        frequency = HSI_VALUE;
-      }
-      else if ((srcclk == RCC_LPTIM2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
-      {
-        frequency = LSE_VALUE;
-      }
-      /* Clock not enabled for LPTIM2 */
-      else
-      {
-        frequency = 0U;
-      }
-      break;
-
-    case RCC_PERIPHCLK_SWPMI1:
-      /* Get the current SWPMI1 source */
-      srcclk = __HAL_RCC_GET_SWPMI1_SOURCE();
-      
-      if(srcclk == RCC_SWPMI1CLKSOURCE_PCLK)
-      {
-        frequency = HAL_RCC_GetPCLK1Freq();
-      }
-      else if((srcclk == RCC_SWPMI1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
-      {
-        frequency = HSI_VALUE;
-      }
-      /* Clock not enabled for SWPMI1 */
-      else
-      {
-        frequency = 0U;
-      }
-      break;
-
-    default:
-      break;
-    }
-  }
-
-  return(frequency);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_Exported_Functions_Group2 Extended clock management functions
- *  @brief  Extended clock management functions
- *
-@verbatim   
- ===============================================================================
-                ##### Extended clock management functions  #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to control the 
-    activation or deactivation of MSI PLL-mode, PLLSAI1, PLLSAI2, LSE CSS,
-    Low speed clock output and clock after wake-up from STOP mode.
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enable PLLSAI1.
-  * @param  PLLSAI1Init  pointer to an RCC_PLLSAI1InitTypeDef structure that
-  *         contains the configuration information for the PLLSAI1
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef  *PLLSAI1Init)
-{
-  uint32_t tickstart = 0U;
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* check for PLLSAI1 Parameters used to output PLLSAI1CLK */
-  assert_param(IS_RCC_PLLSAI1N_VALUE(PLLSAI1Init->PLLSAI1N));
-  assert_param(IS_RCC_PLLSAI1P_VALUE(PLLSAI1Init->PLLSAI1P));
-  assert_param(IS_RCC_PLLSAI1Q_VALUE(PLLSAI1Init->PLLSAI1Q));
-  assert_param(IS_RCC_PLLSAI1R_VALUE(PLLSAI1Init->PLLSAI1R));
-  assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PLLSAI1Init->PLLSAI1ClockOut));
-
-  /* Disable the PLLSAI1 */
-  __HAL_RCC_PLLSAI1_DISABLE();
-
-  /* Get Start Tick*/
-  tickstart = HAL_GetTick();
-
-  /* Wait till PLLSAI1 is ready to be updated */
-  while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != RESET)
-  {
-    if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
-    {
-      status = HAL_TIMEOUT;
-      break;
-    }
-  }
-
-  if(status == HAL_OK)    
-  {
-    /* Configure the PLLSAI1 Multiplication factor N */
-    /* Configure the PLLSAI1 Division factors P, Q and R */
-    __HAL_RCC_PLLSAI1_CONFIG(PLLSAI1Init->PLLSAI1N, PLLSAI1Init->PLLSAI1P, PLLSAI1Init->PLLSAI1Q, PLLSAI1Init->PLLSAI1R);
-    /* Configure the PLLSAI1 Clock output(s) */    
-    __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PLLSAI1Init->PLLSAI1ClockOut);
-
-    /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
-    __HAL_RCC_PLLSAI1_ENABLE();
-
-    /* Get Start Tick*/
-    tickstart = HAL_GetTick();
-
-    /* Wait till PLLSAI1 is ready */
-    while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET)
-    {
-      if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
-      {
-        status = HAL_TIMEOUT;
-        break;
-      }
-    }
-  }
-  
-  return status;
-}
-
-/**
-  * @brief  Disable PLLSAI1.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void)
-{
-  uint32_t tickstart = 0U;
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Disable the PLLSAI1 */
-  __HAL_RCC_PLLSAI1_DISABLE();
-
-  /* Get Start Tick*/
-  tickstart = HAL_GetTick();
-
-  /* Wait till PLLSAI1 is ready */
-  while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != RESET)
-  {
-    if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
-    {
-      status = HAL_TIMEOUT;
-      break;
-    }
-  }
-  
-  /* Disable the PLLSAI1 Clock outputs */    
-  __HAL_RCC_PLLSAI1CLKOUT_DISABLE(RCC_PLLSAI1_SAI1CLK|RCC_PLLSAI1_48M2CLK|RCC_PLLSAI1_ADC1CLK);
-
-  return status;
-}
-
-/**
-  * @brief  Enable PLLSAI2.
-  * @param  PLLSAI2Init  pointer to an RCC_PLLSAI2InitTypeDef structure that
-  *         contains the configuration information for the PLLSAI2
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef  *PLLSAI2Init)
-{
-  uint32_t tickstart = 0U;
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* check for PLLSAI2 Parameters used to output PLLSAI2CLK */
-  assert_param(IS_RCC_PLLSAI2N_VALUE(PLLSAI2Init->PLLSAI2N));
-  assert_param(IS_RCC_PLLSAI2P_VALUE(PLLSAI2Init->PLLSAI2P));
-  assert_param(IS_RCC_PLLSAI2R_VALUE(PLLSAI2Init->PLLSAI2R));
-  assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PLLSAI2Init->PLLSAI2ClockOut));
-
-  /* Disable the PLLSAI2 */
-  __HAL_RCC_PLLSAI2_DISABLE();
-
-  /* Get Start Tick*/
-  tickstart = HAL_GetTick();
-
-  /* Wait till PLLSAI2 is ready to be updated */
-  while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != RESET)
-  {
-    if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
-    {
-      status = HAL_TIMEOUT;
-      break;
-    }
-  }
-
-  if(status == HAL_OK)    
-  {
-    /* Configure the PLLSAI2 Multiplication factor N */
-    /* Configure the PLLSAI2 Division factors P and R */
-    __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2R);
-    /* Configure the PLLSAI2 Clock output(s) */    
-    __HAL_RCC_PLLSAI2CLKOUT_ENABLE(PLLSAI2Init->PLLSAI2ClockOut);
-
-    /* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/
-    __HAL_RCC_PLLSAI2_ENABLE();
-
-    /* Get Start Tick*/
-    tickstart = HAL_GetTick();
-
-    /* Wait till PLLSAI2 is ready */
-    while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RESET)
-    {
-      if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
-      {
-        status = HAL_TIMEOUT;
-        break;
-      }
-    }
-  }
-  
-  return status;
-}
-
-/**
-  * @brief  Disable PLLISAI2.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void)
-{
-  uint32_t tickstart = 0U;
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Disable the PLLSAI2 */
-  __HAL_RCC_PLLSAI2_DISABLE();
-
-  /* Get Start Tick*/
-  tickstart = HAL_GetTick();
-
-  /* Wait till PLLSAI2 is ready */
-  while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != RESET)
-  {
-    if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
-    {
-      status = HAL_TIMEOUT;
-      break;
-    }
-  }
-  
-  /* Disable the PLLSAI2 Clock outputs */    
-  __HAL_RCC_PLLSAI2CLKOUT_DISABLE(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_ADC2CLK);
-
-  return status;
-}
-
-/**
-  * @brief  Configure the oscillator clock source for wakeup from Stop and CSS backup clock.
-  * @param  WakeUpClk  Wakeup clock 
-  *         This parameter can be one of the following values:
-  *            @arg @ref RCC_STOP_WAKEUPCLOCK_MSI  MSI oscillator selection
-  *            @arg @ref RCC_STOP_WAKEUPCLOCK_HSI  HSI oscillator selection
-  * @note   This function shall not be called after the Clock Security System on HSE has been
-  *         enabled.
-  * @retval None
-  */
-void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)
-{
-  assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk));
-  
-  __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk);
-}
-
-/**
-  * @brief  Configure the MSI range after standby mode.
-  * @note   After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz).
-  * @param  MSIRange  MSI range 
-  *         This parameter can be one of the following values:
-  *            @arg @ref RCC_MSIRANGE_4  Range 4 around 1 MHz
-  *            @arg @ref RCC_MSIRANGE_5  Range 5 around 2 MHz
-  *            @arg @ref RCC_MSIRANGE_6  Range 6 around 4 MHz (reset value)
-  *            @arg @ref RCC_MSIRANGE_7  Range 7 around 8 MHz
-  * @retval None
-  */
-void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange)
-{
-  assert_param(IS_RCC_MSI_STANDBY_CLOCK_RANGE(MSIRange));
-  
-  __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(MSIRange);
-}
-
-/**
-  * @brief  Enable the LSE Clock Security System.
-  * @note   Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled
-  *         with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC
-  *         clock with HAL_RCCEx_PeriphCLKConfig().
-  * @retval None
-  */
-void HAL_RCCEx_EnableLSECSS(void)
-{
-  SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
-}
-
-/**
-  * @brief  Disable the LSE Clock Security System.
-  * @note   LSE Clock Security System can only be disabled after a LSE failure detection.
-  * @retval None
-  */
-void HAL_RCCEx_DisableLSECSS(void)
-{
-  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
-  
-  /* Disable LSE CSS IT if any */
-  __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS);
-}
-
-/**
-  * @brief  Enable the LSE Clock Security System Interrupt & corresponding EXTI line.
-  * @note   LSE Clock Security System Interrupt is mapped on RTC EXTI line 19
-  * @retval None
-  */
-void HAL_RCCEx_EnableLSECSS_IT(void)
-{
-  /* Enable LSE CSS */
-  SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
-
-  /* Enable LSE CSS IT */
-  __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS);
-  
-  /* Enable IT on EXTI Line 19 */
-  __HAL_RCC_LSECSS_EXTI_ENABLE_IT();
-  __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();
-}
-
-/**
-  * @brief Handle the RCC LSE Clock Security System interrupt request.
-  * @retval None
-  */
-void HAL_RCCEx_LSECSS_IRQHandler(void)
-{
-  /* Check RCC LSE CSSF flag  */
-  if(__HAL_RCC_GET_IT(RCC_IT_LSECSS))
-  {
-    /* RCC LSE Clock Security System interrupt user callback */
-    HAL_RCCEx_LSECSS_Callback();
-
-    /* Clear RCC LSE CSS pending bit */
-    __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS);
-  }
-}                                                                            
-
-/**
-  * @brief  RCCEx LSE Clock Security System interrupt callback.
-  * @retval none
-  */
-__weak void HAL_RCCEx_LSECSS_Callback(void)
-{
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Select the Low Speed clock source to output on LSCO pin (PA2).
-  * @param  LSCOSource  specifies the Low Speed clock source to output.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_LSCOSOURCE_LSI  LSI clock selected as LSCO source
-  *            @arg @ref RCC_LSCOSOURCE_LSE  LSE clock selected as LSCO source
-  * @retval None
-  */
-void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)
-{
-  GPIO_InitTypeDef GPIO_InitStruct;
-  FlagStatus       pwrclkchanged = RESET;
-  FlagStatus       backupchanged = RESET;
-  
-  /* Check the parameters */
-  assert_param(IS_RCC_LSCOSOURCE(LSCOSource));
-
-  /* LSCO Pin Clock Enable */
-  __LSCO_CLK_ENABLE();
-
-  /* Configue the LSCO pin in analog mode */
-  GPIO_InitStruct.Pin = LSCO_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  HAL_GPIO_Init(LSCO_GPIO_PORT, &GPIO_InitStruct);
-
-  /* Update LSCOSEL clock source in Backup Domain control register */
-  if(__HAL_RCC_PWR_IS_CLK_DISABLED())
-  {
-    __HAL_RCC_PWR_CLK_ENABLE();
-    pwrclkchanged = SET;
-  }
-  if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
-  {
-    HAL_PWR_EnableBkUpAccess();
-    backupchanged = SET;
-  }
-  
-  MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, LSCOSource | RCC_BDCR_LSCOEN);
-  
-  if(backupchanged == SET)
-  {
-    HAL_PWR_DisableBkUpAccess();
-  }
-  if(pwrclkchanged == SET)
-  {
-    __HAL_RCC_PWR_CLK_DISABLE();
-  }
-}
-
-/**
-  * @brief  Disable the Low Speed clock output.
-  * @retval None
-  */
-void HAL_RCCEx_DisableLSCO(void)
-{
-  FlagStatus       pwrclkchanged = RESET;
-  FlagStatus       backupchanged = RESET;
-  
-  /* Update LSCOEN bit in Backup Domain control register */
-  if(__HAL_RCC_PWR_IS_CLK_DISABLED())
-  {
-    __HAL_RCC_PWR_CLK_ENABLE();
-    pwrclkchanged = SET;
-  }
-  if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
-  {
-    /* Enable access to the backup domain */
-    HAL_PWR_EnableBkUpAccess();
-    backupchanged = SET;
-  }
-  
-  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
-  
-  /* Restore previous configuration */
-  if(backupchanged == SET)
-  {
-    /* Disable access to the backup domain */
-    HAL_PWR_DisableBkUpAccess();
-  }
-  if(pwrclkchanged == SET)
-  {
-    __HAL_RCC_PWR_CLK_DISABLE();
-  }
-}
-
-/**
-  * @brief  Enable the PLL-mode of the MSI.
-  * @note   Prior to enable the PLL-mode of the MSI for automatic hardware
-  *         calibration LSE oscillator is to be enabled with HAL_RCC_OscConfig().
-  * @retval None
-  */
-void HAL_RCCEx_EnableMSIPLLMode(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_MSIPLLEN) ;
-}
-
-/**
-  * @brief  Disable the PLL-mode of the MSI.
-  * @note   PLL-mode of the MSI is automatically reset when LSE oscillator is disabled.
-  * @retval None
-  */
-void HAL_RCCEx_DisableMSIPLLMode(void)
-{
-  CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN) ;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup RCCEx_Private_Functions
- * @{
- */
-
-/**
-  * @brief  Configure the parameters N & P of PLLSAI1 and enable PLLSAI1 output clock(s).
-  * @param  PllSai1  pointer to an RCC_PLLSAI1InitTypeDef structure that
-  *         contains the configuration parameters N & P as well as PLLSAI1 output clock(s)
-  *
-  * @note   PLLSAI1 is temporary disable to apply new parameters
-  *
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNP(RCC_PLLSAI1InitTypeDef *PllSai1)
-{
-  uint32_t tickstart = 0U;
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* check for PLLSAI1 Parameters used to output PLLSAI1CLK */
-  assert_param(IS_RCC_PLLSAI1N_VALUE(PllSai1->PLLSAI1N));
-  assert_param(IS_RCC_PLLSAI1P_VALUE(PllSai1->PLLSAI1P));
-  assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PllSai1->PLLSAI1ClockOut));
-
-  /* Disable the PLLSAI1 */
-  __HAL_RCC_PLLSAI1_DISABLE();
-
-  /* Get Start Tick*/
-  tickstart = HAL_GetTick();
-
-  /* Wait till PLLSAI1 is ready to be updated */
-  while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != RESET)
-  {
-    if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
-    {
-      status = HAL_TIMEOUT;
-      break;
-    }
-  }
-
-  if(status == HAL_OK)    
-  {
-    /* Configure the PLLSAI1 Multiplication factor N */
-    __HAL_RCC_PLLSAI1_MULN_CONFIG(PllSai1->PLLSAI1N);
-    /* Configure the PLLSAI1 Division factor P */
-    __HAL_RCC_PLLSAI1_DIVP_CONFIG(PllSai1->PLLSAI1P);
-
-    /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
-    __HAL_RCC_PLLSAI1_ENABLE();
-
-    /* Get Start Tick*/
-    tickstart = HAL_GetTick();
-
-    /* Wait till PLLSAI1 is ready */
-    while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET)
-    {
-      if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
-      {
-        status = HAL_TIMEOUT;
-        break;
-      }
-    }
-
-    if(status == HAL_OK)    
-    {
-      /* Configure the PLLSAI1 Clock output(s) */
-      __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PllSai1->PLLSAI1ClockOut);
-    }
-  }
-  
-  return status;
-}
-
-/**
-  * @brief  Configure the parameters N & Q of PLLSAI1 and enable PLLSAI1 output clock(s).
-  * @param  PllSai1  pointer to an RCC_PLLSAI1InitTypeDef structure that
-  *         contains the configuration parameters N & Q as well as PLLSAI1 output clock(s)
-  *
-  * @note   PLLSAI1 is temporary disable to apply new parameters
-  *
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNQ(RCC_PLLSAI1InitTypeDef *PllSai1)
-{
-  uint32_t tickstart = 0U;
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* check for PLLSAI1 Parameters used to output PLLSAI1CLK */
-  assert_param(IS_RCC_PLLSAI1N_VALUE(PllSai1->PLLSAI1N));
-  assert_param(IS_RCC_PLLSAI1Q_VALUE(PllSai1->PLLSAI1Q));
-  assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PllSai1->PLLSAI1ClockOut));
-
-  /* Disable the PLLSAI1 */
-  __HAL_RCC_PLLSAI1_DISABLE();
-
-  /* Get Start Tick*/
-  tickstart = HAL_GetTick();
-
-  /* Wait till PLLSAI1 is ready to be updated */
-  while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != RESET)
-  {
-    if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
-    {
-      status = HAL_TIMEOUT;
-      break;
-    }
-  }
-
-  if(status == HAL_OK)    
-  {
-    /* Configure the PLLSAI1 Multiplication factor N */
-    __HAL_RCC_PLLSAI1_MULN_CONFIG(PllSai1->PLLSAI1N);
-    /* Configure the PLLSAI1 Division factor Q */
-    __HAL_RCC_PLLSAI1_DIVQ_CONFIG(PllSai1->PLLSAI1Q);
-
-    /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
-    __HAL_RCC_PLLSAI1_ENABLE();
-
-    /* Get Start Tick*/
-    tickstart = HAL_GetTick();
-
-    /* Wait till PLLSAI1 is ready */
-    while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET)
-    {
-      if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
-      {
-        status = HAL_TIMEOUT;
-        break;
-      }
-    }
-
-    if(status == HAL_OK)
-    {
-      /* Configure the PLLSAI1 Clock output(s) */
-      __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PllSai1->PLLSAI1ClockOut);
-    }
-  }
-  
-  return status;
-}
-
-/**
-  * @brief  Configure the parameters N & R of PLLSAI1 and enable PLLSAI1 output clock(s).
-  * @param  PllSai1  pointer to an RCC_PLLSAI1InitTypeDef structure that
-  *         contains the configuration parameters N & R as well as PLLSAI1 output clock(s)
-  *
-  * @note   PLLSAI1 is temporary disable to apply new parameters
-  *
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNR(RCC_PLLSAI1InitTypeDef *PllSai1)
-{
-  uint32_t tickstart = 0U;
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* check for PLLSAI1 Parameters used to output PLLSAI1CLK */
-  assert_param(IS_RCC_PLLSAI1N_VALUE(PllSai1->PLLSAI1N));
-  assert_param(IS_RCC_PLLSAI1R_VALUE(PllSai1->PLLSAI1R));
-  assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PllSai1->PLLSAI1ClockOut));
-
-  /* Disable the PLLSAI1 */
-  __HAL_RCC_PLLSAI1_DISABLE();
-
-  /* Get Start Tick*/
-  tickstart = HAL_GetTick();
-
-  /* Wait till PLLSAI1 is ready to be updated */
-  while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != RESET)
-  {
-    if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
-    {
-      status = HAL_TIMEOUT;
-      break;
-    }
-  }
-
-  if(status == HAL_OK)    
-  {
-    /* Configure the PLLSAI1 Multiplication factor N */
-    __HAL_RCC_PLLSAI1_MULN_CONFIG(PllSai1->PLLSAI1N);
-    /* Configure the PLLSAI1 Division factor R */
-    __HAL_RCC_PLLSAI1_DIVR_CONFIG(PllSai1->PLLSAI1R);
-
-    /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
-    __HAL_RCC_PLLSAI1_ENABLE();
-
-    /* Get Start Tick*/
-    tickstart = HAL_GetTick();
-
-    /* Wait till PLLSAI1 is ready */
-    while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET)
-    {
-      if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
-      {
-        status = HAL_TIMEOUT;
-        break;
-      }
-    }
-    
-    if(status == HAL_OK)
-    {
-      /* Configure the PLLSAI1 Clock output(s) */
-      __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PllSai1->PLLSAI1ClockOut);
-    }
-  }
-  
-  return status;
-}
-
-/**
-  * @brief  Configure the parameters N & P of PLLSAI2 and enable PLLSAI2 output clock(s).
-  * @param  PllSai2  pointer to an RCC_PLLSAI2InitTypeDef structure that
-  *         contains the configuration parameters N & P as well as PLLSAI2 output clock(s)
-  *
-  * @note   PLLSAI2 is temporary disable to apply new parameters
-  *
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef RCCEx_PLLSAI2_ConfigNP(RCC_PLLSAI2InitTypeDef *PllSai2)
-{
-  uint32_t tickstart = 0U;
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* check for PLLSAI2 Parameters */
-  assert_param(IS_RCC_PLLSAI2N_VALUE(PllSai2->PLLSAI2N));
-  assert_param(IS_RCC_PLLSAI2P_VALUE(PllSai2->PLLSAI2P));
-  assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PllSai2->PLLSAI2ClockOut));
-
-  /* Disable the PLLSAI2 */
-  __HAL_RCC_PLLSAI2_DISABLE();
-
-  /* Get Start Tick*/
-  tickstart = HAL_GetTick();
-
-  /* Wait till PLLSAI2 is ready */
-  while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != RESET)
-  {
-    if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
-    {
-      status = HAL_TIMEOUT;
-      break;
-    }
-  }
-
-  if(status == HAL_OK)    
-  {
-    /* Configure the PLLSAI2 Multiplication factor N */
-    __HAL_RCC_PLLSAI2_MULN_CONFIG(PllSai2->PLLSAI2N);
-    /* Configure the PLLSAI2 Division factor P */
-    __HAL_RCC_PLLSAI2_DIVP_CONFIG(PllSai2->PLLSAI2P);
-
-    /* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/
-    __HAL_RCC_PLLSAI2_ENABLE();
-
-    /* Get Start Tick*/
-    tickstart = HAL_GetTick();
-
-    /* Wait till PLLSAI2 is ready */
-    while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RESET)
-    {
-      if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
-      {
-        status = HAL_TIMEOUT;
-        break;
-      }
-    }
-    
-    if(status == HAL_OK)
-    {
-      /* Configure the PLLSAI2 Clock output(s) */
-      __HAL_RCC_PLLSAI2CLKOUT_ENABLE(PllSai2->PLLSAI2ClockOut);
-    }
-  }
-  
-  return status;
-}
-
-/**
-  * @brief  Configure the parameters N & R of PLLSAI2 and enable PLLSAI2 output clock(s).
-  * @param  PllSai2  pointer to an RCC_PLLSAI2InitTypeDef structure that
-  *         contains the configuration parameters N & R as well as PLLSAI2 output clock(s)
-  *
-  * @note   PLLSAI2 is temporary disable to apply new parameters
-  *
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef RCCEx_PLLSAI2_ConfigNR(RCC_PLLSAI2InitTypeDef *PllSai2)
-{
-  uint32_t tickstart = 0U;
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* check for PLLSAI2 Parameters */
-  assert_param(IS_RCC_PLLSAI2N_VALUE(PllSai2->PLLSAI2N));
-  assert_param(IS_RCC_PLLSAI2R_VALUE(PllSai2->PLLSAI2R));
-  assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PllSai2->PLLSAI2ClockOut));
-
-  /* Disable the PLLSAI2 */
-  __HAL_RCC_PLLSAI2_DISABLE();
-
-  /* Get Start Tick*/
-  tickstart = HAL_GetTick();
-
-  /* Wait till PLLSAI2 is ready */
-  while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != RESET)
-  {
-    if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
-    {
-      status = HAL_TIMEOUT;
-      break;
-    }
-  }
-
-  if(status == HAL_OK)    
-  {
-    /* Configure the PLLSAI2 Multiplication factor N */
-    __HAL_RCC_PLLSAI2_MULN_CONFIG(PllSai2->PLLSAI2N);
-    /* Configure the PLLSAI2 Division factor R */
-    __HAL_RCC_PLLSAI2_DIVR_CONFIG(PllSai2->PLLSAI2R);
-
-    /* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/
-    __HAL_RCC_PLLSAI2_ENABLE();
-
-    /* Get Start Tick*/
-    tickstart = HAL_GetTick();
-
-    /* Wait till PLLSAI2 is ready */
-    while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RESET)
-    {
-      if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
-      {
-        status = HAL_TIMEOUT;
-        break;
-      }
-    }
-    
-    if(status == HAL_OK)
-    {
-      /* Configure the PLLSAI2 Clock output(s) */
-      __HAL_RCC_PLLSAI2CLKOUT_ENABLE(PllSai2->PLLSAI2ClockOut);
-    }
-  }
-  
-  return status;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_RCC_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/stmhal/hal/l4/src/stm32l4xx_hal_rng.c b/stmhal/hal/l4/src/stm32l4xx_hal_rng.c
deleted file mode 100644
index 8dd1fc3b6d..0000000000
--- a/stmhal/hal/l4/src/stm32l4xx_hal_rng.c
+++ /dev/null
@@ -1,519 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_rng.c
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   RNG HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the Random Number Generator (RNG) peripheral:
-  *           + Initialization/de-initialization functions
-  *           + Peripheral Control functions 
-  *           + Peripheral State functions
-  *         
-  @verbatim
-  ==============================================================================
-                     ##### How to use this driver #####
-  ==============================================================================
-  [..]
-      The RNG HAL driver can be used as follows:
-
-      (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro 
-          in HAL_RNG_MspInit().
-      (#) Activate the RNG peripheral using HAL_RNG_Init() function.
-      (#) Wait until the 32-bit Random Number Generator contains a valid 
-          random data using (polling/interrupt) mode.   
-      (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function.
-  
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup RNG RNG
-  * @brief RNG HAL module driver.
-  * @{
-  */
-
-#ifdef HAL_RNG_MODULE_ENABLED
-
-
-
-/* Private types -------------------------------------------------------------*/
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup RNG_Private_Constants RNG_Private_Constants
-  * @{
-  */
-#define RNG_TIMEOUT_VALUE     2
-/**
-  * @}
-  */ 
-
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup RNG_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup RNG_Exported_Functions_Group1
- *  @brief   Initialization and de-initialization functions
- *
-@verbatim
- ===============================================================================
-          ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Initialize the RNG according to the specified parameters 
-          in the RNG_InitTypeDef and create the associated handle
-      (+) DeInitialize the RNG peripheral
-      (+) Initialize the RNG MSP (MCU Specific Package)
-      (+) DeInitialize the RNG MSP 
- 
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initialize the RNG peripheral and initialize the associated handle.
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
-{ 
-  /* Check the RNG handle allocation */
-  if(hrng == NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  assert_param(IS_RNG_ALL_INSTANCE(hrng->Instance)); 
-  
-  __HAL_LOCK(hrng);
-  
-  if(hrng->State == HAL_RNG_STATE_RESET)
-  {  
-    /* Allocate lock resource and initialize it */
-    hrng->Lock = HAL_UNLOCKED;
-
-    /* Init the low level hardware */
-    HAL_RNG_MspInit(hrng);
-  }
-  
-  /* Change RNG peripheral state */
-  hrng->State = HAL_RNG_STATE_BUSY;
-
-  /* Enable the RNG Peripheral */
-  __HAL_RNG_ENABLE(hrng);
-
-  /* Initialize the RNG state */
-  hrng->State = HAL_RNG_STATE_READY;
-  
-  __HAL_UNLOCK(hrng);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitialize the RNG peripheral. 
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)
-{ 
-  /* Check the RNG handle allocation */
-  if(hrng == NULL)
-  {
-    return HAL_ERROR;
-  }
-  /* Disable the RNG Peripheral */
-  CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN);
-  
-  /* Clear RNG interrupt status flags */
-  CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS);
-  
-  /* DeInit the low level hardware */
-  HAL_RNG_MspDeInit(hrng);
-  
-  /* Update the RNG state */
-  hrng->State = HAL_RNG_STATE_RESET; 
-
-  /* Release Lock */
-  __HAL_UNLOCK(hrng);
-  
-  /* Return the function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initialize the RNG MSP.
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
-  * @retval None
-  */
-__weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrng);
-
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_RNG_MspInit must be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  DeInitialize the RNG MSP.
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
-  * @retval None
-  */
-__weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrng);
-
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_RNG_MspDeInit must be implemented in the user file.
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup RNG_Exported_Functions_Group2
- *  @brief    Management functions. 
- *
-@verbatim   
- ===============================================================================
-                      ##### Peripheral Control functions #####
- ===============================================================================  
-    [..]  This section provides functions allowing to:
-      (+) Get the 32 bit Random number
-      (+) Get the 32 bit Random number with interrupt enabled
-      (+) Handle RNG interrupt request 
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Generate a 32-bit random number.
-  * @note   Each time the random number data is read the RNG_FLAG_DRDY flag 
-  *         is automatically cleared.
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
-  * @param  random32bit: pointer to generated random number variable if successful.
-  * @retval HAL status
-  */
-
-HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit)
-{
-  uint32_t tickstart = 0;    
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process Locked */
-  __HAL_LOCK(hrng); 
-  
-  /* Check RNS peripheral state */
-  if(hrng->State == HAL_RNG_STATE_READY)
-  {
-    /* Change RNG peripheral state */  
-    hrng->State = HAL_RNG_STATE_BUSY;  
-
-    /* Get tick */
-    tickstart = HAL_GetTick();
-  
-    /* Check if data register contains valid random data */
-    while(__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RNG_TIMEOUT_VALUE)
-      {    
-        hrng->State = HAL_RNG_STATE_ERROR;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrng);
-      
-        return HAL_TIMEOUT;
-      } 
-    }
-  
-    /* Get a 32bit Random number */
-    hrng->RandomNumber = hrng->Instance->DR;
-    *random32bit = hrng->RandomNumber;
-  
-    hrng->State = HAL_RNG_STATE_READY;
-  }
-  else
-  {
-    status = HAL_ERROR;
-  }
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrng);
-
-  return status;
-}
-
-/**
-  * @brief  Generate a 32-bit random number in interrupt mode.
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Process Locked */
-  __HAL_LOCK(hrng);
-  
-  /* Check RNG peripheral state */
-  if(hrng->State == HAL_RNG_STATE_READY)
-  {
-    /* Change RNG peripheral state */  
-    hrng->State = HAL_RNG_STATE_BUSY;  
-  
-    /* Process Unlocked */
-    __HAL_UNLOCK(hrng);
-    
-    /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */ 
-    __HAL_RNG_ENABLE_IT(hrng);
-  }
-  else
-  {
-    /* Process Unlocked */
-    __HAL_UNLOCK(hrng);
-    
-    status = HAL_ERROR;
-  }
-  
-  return status;
-}
-
-/**
-  * @brief  Handle RNG interrupt request.
-  * @note   In the case of a clock error, the RNG is no more able to generate 
-  *         random numbers because the PLL48CLK clock is not correct. User has 
-  *         to check that the clock controller is correctly configured to provide
-  *         the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT(). 
-  *         The clock error has no impact on the previously generated 
-  *         random numbers, and the RNG_DR register contents can be used.
-  * @note   In the case of a seed error, the generation of random numbers is 
-  *         interrupted as long as the SECS bit is '1'. If a number is 
-  *         available in the RNG_DR register, it must not be used because it may 
-  *         not have enough entropy. In this case, it is recommended to clear the 
-  *         SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable 
-  *         the RNG peripheral to reinitialize and restart the RNG.
-  * @note   User-written HAL_RNG_ErrorCallback() API is called once whether SEIS
-  *         or CEIS are set.  
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
-  * @retval None
-
-  */
-void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
-{
-  /* RNG clock error interrupt occurred */
-  if((__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET) ||  (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET))
-  { 
-    /* Change RNG peripheral state */
-    hrng->State = HAL_RNG_STATE_ERROR;
-  
-    HAL_RNG_ErrorCallback(hrng);
-    
-    /* Clear the clock error flag */
-    __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI|RNG_IT_SEI);
-    
-  }
-  
-  /* Check RNG data ready interrupt occurred */    
-  if(__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET)
-  {
-    /* Generate random number once, so disable the IT */
-    __HAL_RNG_DISABLE_IT(hrng);
-    
-    /* Get the 32bit Random number (DRDY flag automatically cleared) */ 
-    hrng->RandomNumber = hrng->Instance->DR;
-    
-    if(hrng->State != HAL_RNG_STATE_ERROR)
-    {
-      /* Change RNG peripheral state */
-      hrng->State = HAL_RNG_STATE_READY; 
-      
-      /* Data Ready callback */ 
-      HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber);
-    } 
-  }
-} 
-
-/**
-  * @brief  Return generated random number in polling mode (Obsolete).
-  * @note   Use HAL_RNG_GenerateRandomNumber() API instead.
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
-  *                the configuration information for RNG.
-  * @retval random value
-  */
-uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng)
-{
-  if(HAL_RNG_GenerateRandomNumber(hrng, &(hrng->RandomNumber)) == HAL_OK)
-  {
-    return hrng->RandomNumber; 
-  }
-  else
-  {
-    return 0;
-  }
-}
-
-
-/**
-  * @brief  Return a 32-bit random number with interrupt enabled (Obsolete).
-  * @note   Use HAL_RNG_GenerateRandomNumber_IT() API instead.
-  * @param  hrng: RNG handle
-  * @retval 32-bit random number
-  */
-uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng)
-{
-  uint32_t random32bit = 0;
-  
-  /* Process locked */
-  __HAL_LOCK(hrng);
-  
-  /* Change RNG peripheral state */  
-  hrng->State = HAL_RNG_STATE_BUSY;  
-  
-  /* Get a 32bit Random number */ 
-  random32bit = hrng->Instance->DR;
-  
-  /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */ 
-  __HAL_RNG_ENABLE_IT(hrng); 
-  
-  /* Return the 32 bit random number */   
-  return random32bit;
-}
-
-
-
-/**
-  * @brief  Read latest generated random number. 
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
-  * @retval random value
-  */
-uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng)
-{
-  return(hrng->RandomNumber);
-}
-
-/**
-  * @brief  Data Ready callback in non-blocking mode. 
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
-  * @param  random32bit: generated random value
-  * @retval None
-  */
-__weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrng);
-  UNUSED(random32bit);
-
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_RNG_ReadyDataCallback must be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  RNG error callback.
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
-  * @retval None
-  */
-__weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrng);
-
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_RNG_ErrorCallback must be implemented in the user file.
-   */
-}
- 
-/**
-  * @}
-  */
-
-/** @addtogroup RNG_Exported_Functions_Group3
- *  @brief    Peripheral State functions. 
- *
-@verbatim   
- ===============================================================================
-                      ##### Peripheral State functions #####
- ===============================================================================  
-    [..]
-    This subsection permits to get in run-time the status of the peripheral.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the RNG handle state.
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
-  * @retval HAL state
-  */
-HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
-{
-  /* Return RNG handle state */
-  return hrng->State;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-#endif /* HAL_RNG_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/src/stm32l4xx_hal_rtc.c b/stmhal/hal/l4/src/stm32l4xx_hal_rtc.c
deleted file mode 100644
index d261163428..0000000000
--- a/stmhal/hal/l4/src/stm32l4xx_hal_rtc.c
+++ /dev/null
@@ -1,1530 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_rtc.c
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   RTC HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Real-Time Clock (RTC) peripheral:
-  *           + Initialization
-  *           + Calendar (Time and Date) configuration
-  *           + Alarms (Alarm A and Alarm B) configuration
-  *           + WakeUp Timer configuration
-  *           + TimeStamp configuration
-  *           + Tampers configuration
-  *           + Backup Data Registers configuration  
-  *           + RTC Tamper and TimeStamp Pins Selection 
-  *           + Interrupts and flags management
-  *         
-  @verbatim
- ===============================================================================   
-                          ##### RTC Operating Condition #####
- ===============================================================================
-  [..] The real-time clock (RTC) and the RTC backup registers can be powered
-       from the VBAT voltage when the main VDD supply is powered off.
-       To retain the content of the RTC backup registers and supply the RTC 
-       when VDD is turned off, VBAT pin can be connected to an optional
-       standby voltage supplied by a battery or by another source.
-
-                   ##### Backup Domain Reset #####
- ===============================================================================
-  [..] The backup domain reset sets all RTC registers and the RCC_BDCR register
-       to their reset values. 
-       A backup domain reset is generated when one of the following events occurs:
-    (#) Software reset, triggered by setting the BDRST bit in the 
-        RCC Backup domain control register (RCC_BDCR).
-    (#) VDD or VBAT power on, if both supplies have previously been powered off.
-    (#) Tamper detection event resets all data backup registers.
-
-                   ##### Backup Domain Access #####
- ===================================================================
-  [..] After reset, the backup domain (RTC registers, RTC backup data 
-       registers and backup SRAM) is protected against possible unwanted write 
-       accesses.
-
-  [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
-    (#) Call the function HAL_RCCEx_PeriphCLKConfig with RCC_PERIPHCLK_RTC for
-        PeriphClockSelection and select RTCClockSelection (LSE, LSI or HSEdiv32)
-    (#) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() macro.
-
-                  ##### How to use RTC Driver #####
- ===================================================================
-  [..]
-    (#) Enable the RTC domain access (see description in the section above).
-    (#) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
-        format using the HAL_RTC_Init() function.
-
-  *** Time and Date configuration ***
-  ===================================
-  [..] 
-    (#) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
-        and HAL_RTC_SetDate() functions.
-    (#) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.
-
-  *** Alarm configuration ***
-  ===========================
-  [..]
-    (#) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
-            You can also configure the RTC Alarm with interrupt mode using the 
-            HAL_RTC_SetAlarm_IT() function.
-    (#) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.
-
-                  ##### RTC and low power modes #####
- ===================================================================
-  [..] The MCU can be woken up from a low power mode by an RTC alternate
-       function.
-  [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
-       RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
-       These RTC alternate functions can wake up the system from the Stop and 
-       Standby low power modes.
-  [..] The system can also wake up from low power modes without depending
-       on an external interrupt (Auto-wakeup mode), by using the RTC alarm
-       or the RTC wakeup events.
-  [..] The RTC provides a programmable time base for waking up from the
-       Stop or Standby mode at regular intervals.
-       Wakeup from STOP and Standby modes is possible only when the RTC clock source
-       is LSE or LSI.
-
-   @endverbatim
-
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************  
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup RTC RTC
-  * @brief RTC HAL module driver
-  * @{
-  */
-
-#ifdef HAL_RTC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup RTC_Exported_Functions RTC Exported Functions
-  * @{
-  */
-
-/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions 
- *
-@verbatim
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-   [..] This section provide functions allowing to initialize and configure the 
-         RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable 
-         RTC registers Write protection, enter and exit the RTC initialization mode,
-         RTC registers synchronization check and reference clock detection enable.
-         (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
-             It is split into 2 programmable prescalers to minimize power consumption.
-             (++) A 7-bit asynchronous prescaler and a 15-bit synchronous prescaler.
-             (++) When both prescalers are used, it is recommended to configure the 
-                 asynchronous prescaler to a high value to minimize power consumption.
-         (#) All RTC registers are Write protected. Writing to the RTC registers
-             is enabled by writing a key into the Write Protection register, RTC_WPR.
-         (#) To configure the RTC Calendar, user application should enter 
-             initialization mode. In this mode, the calendar counter is stopped
-             and its value can be updated. When the initialization sequence is 
-             complete, the calendar restarts counting after 4 RTCCLK cycles.
-         (#) To read the calendar through the shadow registers after Calendar 
-             initialization, calendar update or after wakeup from low power modes
-             the software must first clear the RSF flag. The software must then
-             wait until it is set again before reading the calendar, which means
-             that the calendar registers have been correctly copied into the
-             RTC_TR and RTC_DR shadow registers. The HAL_RTC_WaitForSynchro() function 
-             implements the above software sequence (RSF clear and RSF check).
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initialize the RTC according to the specified parameters 
-  *         in the RTC_InitTypeDef structure and initialize the associated handle.
-  * @param  hrtc: RTC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
-{
-  /* Check the RTC peripheral state */
-  if(hrtc == NULL)
-  {
-     return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
-  assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat));
-  assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv));
-  assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv));
-  assert_param(IS_RTC_OUTPUT(hrtc->Init.OutPut));
-  assert_param(IS_RTC_OUTPUT_REMAP(hrtc->Init.OutPutRemap));
-  assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity));
-  assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType));
-  
-  if(hrtc->State == HAL_RTC_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hrtc->Lock = HAL_UNLOCKED;
-
-    /* Initialize RTC MSP */
-    HAL_RTC_MspInit(hrtc);
-  }
-
-  /* Set RTC state */
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Set Initialization mode */
-  if(RTC_EnterInitMode(hrtc) != HAL_OK)
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-    /* Set RTC state */
-    hrtc->State = HAL_RTC_STATE_ERROR;
-
-    return HAL_ERROR;
-  }
-  else
-  {
-    /* Clear RTC_CR FMT, OSEL and POL Bits */
-    hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));
-    /* Set RTC_CR register */
-    hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
-
-    /* Configure the RTC PRER */
-    hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
-    hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16);
-
-    /* Exit Initialization mode */
-    hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
-
-    hrtc->Instance->OR &= (uint32_t)~(RTC_OR_ALARMOUTTYPE | RTC_OR_OUT_RMP);
-    hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType | hrtc->Init.OutPutRemap);
-
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-    /* Set RTC state */
-    hrtc->State = HAL_RTC_STATE_READY;
-
-    return HAL_OK;
-  }
-}
-
-/**
-  * @brief  DeInitialize the RTC peripheral.
-  * @param  hrtc: RTC handle
-  * @note   This function doesn't reset the RTC Backup Data registers.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
-{
-  uint32_t tickstart = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
-
-  /* Set RTC state */
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Set Initialization mode */
-  if(RTC_EnterInitMode(hrtc) != HAL_OK)
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-    /* Set RTC state */
-    hrtc->State = HAL_RTC_STATE_ERROR;
-
-    return HAL_ERROR;
-  }
-  else
-  {
-    /* Reset TR, DR and CR registers */
-    hrtc->Instance->TR = (uint32_t)0x00000000;
-    hrtc->Instance->DR = ((uint32_t)(RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0));
-    /* Reset All CR bits except CR[2:0] */
-    hrtc->Instance->CR &= RTC_CR_WUCKSEL;
-
-    tickstart = HAL_GetTick();
-
-    /* Wait till WUTWF flag is set and if Time out is reached exit */
-    while(((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        /* Set RTC state */
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Reset all RTC CR register bits */
-    hrtc->Instance->CR &= (uint32_t)0x00000000;
-    hrtc->Instance->WUTR = RTC_WUTR_WUT;
-    hrtc->Instance->PRER = ((uint32_t)(RTC_PRER_PREDIV_A | 0x000000FF));
-    hrtc->Instance->ALRMAR = (uint32_t)0x00000000;
-    hrtc->Instance->ALRMBR = (uint32_t)0x00000000;
-    hrtc->Instance->SHIFTR = (uint32_t)0x00000000;
-    hrtc->Instance->CALR = (uint32_t)0x00000000;
-    hrtc->Instance->ALRMASSR = (uint32_t)0x00000000;
-    hrtc->Instance->ALRMBSSR = (uint32_t)0x00000000;
-
-    /* Reset ISR register and exit initialization mode */
-    hrtc->Instance->ISR = (uint32_t)0x00000000;
-
-    /* Reset Tamper configuration register */
-    hrtc->Instance->TAMPCR = 0x00000000;
-
-    /* Reset Option register */
-    hrtc->Instance->OR = 0x00000000;
-
-    /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
-    if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
-    {
-      if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  
-
-        hrtc->State = HAL_RTC_STATE_ERROR;
-
-        return HAL_ERROR;
-      }
-    }
-  }
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* De-Initialize RTC MSP */
-  HAL_RTC_MspDeInit(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_RESET;
-  
-  /* Release Lock */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initialize the RTC MSP.
-  * @param  hrtc: RTC handle  
-  * @retval None
-  */
-__weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_RTC_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitialize the RTC MSP.
-  * @param  hrtc: RTC handle 
-  * @retval None
-  */
-__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_RTC_MspDeInit could be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions
- *  @brief   RTC Time and Date functions
- *
-@verbatim
- ===============================================================================
-                 ##### RTC Time and Date functions #####
- ===============================================================================
- 
- [..] This section provides functions allowing to configure Time and Date features
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Set RTC current time.
-  * @param  hrtc: RTC handle
-  * @param  sTime: Pointer to Time structure
-  * @param  Format: Specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *            @arg RTC_FORMAT_BIN: Binary data format 
-  *            @arg RTC_FORMAT_BCD: BCD data format
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
-{
-  uint32_t tmpreg = 0;
-
- /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-  assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving));
-  assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation));
-
-  /* Process Locked */ 
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  if(Format == RTC_FORMAT_BIN)
-  {
-    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
-    {
-      assert_param(IS_RTC_HOUR12(sTime->Hours));
-      assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
-    }
-    else
-    {
-      sTime->TimeFormat = 0x00;
-      assert_param(IS_RTC_HOUR24(sTime->Hours));
-    }
-    assert_param(IS_RTC_MINUTES(sTime->Minutes));
-    assert_param(IS_RTC_SECONDS(sTime->Seconds));
-
-    tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16) | \
-                        ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8) | \
-                        ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \
-                        (((uint32_t)sTime->TimeFormat) << 16));
-  }
-  else
-  {
-    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
-    {
-      tmpreg = RTC_Bcd2ToByte(sTime->Hours);
-      assert_param(IS_RTC_HOUR12(tmpreg));
-      assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
-    }
-    else
-    {
-      sTime->TimeFormat = 0x00;
-      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours)));
-    }
-    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));
-    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));
-    tmpreg = (((uint32_t)(sTime->Hours) << 16) | \
-              ((uint32_t)(sTime->Minutes) << 8) | \
-              ((uint32_t)sTime->Seconds) | \
-              ((uint32_t)(sTime->TimeFormat) << 16));
-  }
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Set Initialization mode */
-  if(RTC_EnterInitMode(hrtc) != HAL_OK)
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-    /* Set RTC state */
-    hrtc->State = HAL_RTC_STATE_ERROR;
-
-    /* Process Unlocked */ 
-    __HAL_UNLOCK(hrtc);
-
-    return HAL_ERROR;
-  }
-  else
-  {
-    /* Set the RTC_TR register */
-    hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
-
-    /* Clear the bits to be configured */
-    hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BCK);
-
-    /* Configure the RTC_CR register */
-    hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
-
-    /* Exit Initialization mode */
-    hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
-
-    /* If  CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
-    if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
-    {
-      if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_ERROR;
-
-        /* Process Unlocked */ 
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_ERROR;
-      }
-    }
-
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-    
-   hrtc->State = HAL_RTC_STATE_READY;
-
-   __HAL_UNLOCK(hrtc); 
-
-   return HAL_OK;
-  }
-}
-
-/**
-  * @brief  Get RTC current time.
-  * @param  hrtc: RTC handle
-  * @param  sTime: Pointer to Time structure with Hours, Minutes and Seconds fields returned 
-  *                with input format (BIN or BCD), also SubSeconds field returning the
-  *                RTC_SSR register content and SecondFraction field the Synchronous pre-scaler
-  *                factor to be used for second fraction ratio computation.
-  * @param  Format: Specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *            @arg RTC_FORMAT_BIN: Binary data format 
-  *            @arg RTC_FORMAT_BCD: BCD data format
-  * @note  You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds
-  *        value in second fraction ratio with time unit following generic formula:
-  *        Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
-  *        This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS
-  * @note  You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values 
-  *        in the higher-order calendar shadow registers to ensure consistency between the time and date values.
-  *        Reading RTC current time locks the values in calendar shadow registers until Current date is read
-  *        to ensure consistency between the time and date values.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-
-  /* Get subseconds structure field from the corresponding register*/
-  sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR);
-
-  /* Get SecondFraction structure field from the corresponding register field*/
-  sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S);
-  
-  /* Get the TR register */
-  tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK);
-
-  /* Fill the structure fields with the read parameters */
-  sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16);
-  sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8);
-  sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
-  sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16);
-
-  /* Check the input parameters format */
-  if(Format == RTC_FORMAT_BIN)
-  {
-    /* Convert the time structure parameters to Binary format */
-    sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours);
-    sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes);
-    sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds);
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set RTC current date.
-  * @param  hrtc: RTC handle
-  * @param  sDate: Pointer to date structure
-  * @param  Format: specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *            @arg RTC_FORMAT_BIN: Binary data format 
-  *            @arg RTC_FORMAT_BCD: BCD data format
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
-{
-  uint32_t datetmpreg = 0;
-
- /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10) == 0x10))
-  {
-    sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10)) + (uint8_t)0x0A);
-  }
-
-  assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));
-
-  if(Format == RTC_FORMAT_BIN)
-  {
-    assert_param(IS_RTC_YEAR(sDate->Year));
-    assert_param(IS_RTC_MONTH(sDate->Month));
-    assert_param(IS_RTC_DATE(sDate->Date));
-
-   datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16) | \
-                 ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8) | \
-                 ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \
-                 ((uint32_t)sDate->WeekDay << 13));
-  }
-  else
-  {
-    assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));
-    datetmpreg = RTC_Bcd2ToByte(sDate->Month);
-    assert_param(IS_RTC_MONTH(datetmpreg));
-    datetmpreg = RTC_Bcd2ToByte(sDate->Date);
-    assert_param(IS_RTC_DATE(datetmpreg));
-
-    datetmpreg = ((((uint32_t)sDate->Year) << 16) | \
-                  (((uint32_t)sDate->Month) << 8) | \
-                  ((uint32_t)sDate->Date) | \
-                  (((uint32_t)sDate->WeekDay) << 13));
-  }
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Set Initialization mode */
-  if(RTC_EnterInitMode(hrtc) != HAL_OK)
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-    /* Set RTC state*/
-    hrtc->State = HAL_RTC_STATE_ERROR;
-
-    /* Process Unlocked */ 
-    __HAL_UNLOCK(hrtc);
-
-    return HAL_ERROR;
-  }
-  else
-  {
-    /* Set the RTC_DR register */
-    hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK);
-
-    /* Exit Initialization mode */
-    hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
-
-    /* If  CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
-    if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
-    {
-      if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  
-
-        hrtc->State = HAL_RTC_STATE_ERROR;
-
-        /* Process Unlocked */ 
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_ERROR;
-      }
-    }
-
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-    hrtc->State = HAL_RTC_STATE_READY ;
-
-    /* Process Unlocked */ 
-    __HAL_UNLOCK(hrtc);
-
-    return HAL_OK;
-  }
-}
-
-/**
-  * @brief  Get RTC current date.
-  * @param  hrtc: RTC handle
-  * @param  sDate: Pointer to Date structure
-  * @param  Format: Specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *            @arg RTC_FORMAT_BIN:  Binary data format 
-  *            @arg RTC_FORMAT_BCD:  BCD data format
-  * @note  You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values 
-  *        in the higher-order calendar shadow registers to ensure consistency between the time and date values.
-  *        Reading RTC current time locks the values in calendar shadow registers until Current date is read.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
-{
-  uint32_t datetmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-
-  /* Get the DR register */
-  datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK);
-
-  /* Fill the structure fields with the read parameters */
-  sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16);
-  sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8);
-  sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU));
-  sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13); 
-
-  /* Check the input parameters format */
-  if(Format == RTC_FORMAT_BIN)
-  {
-    /* Convert the date structure parameters to Binary format */
-    sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);
-    sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month);
-    sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date);
-  }
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions
- *  @brief   RTC Alarm functions
- *
-@verbatim   
- ===============================================================================
-                 ##### RTC Alarm functions #####
- ===============================================================================  
- 
- [..] This section provides functions allowing to configure Alarm feature
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Set the specified RTC Alarm.
-  * @param  hrtc: RTC handle
-  * @param  sAlarm: Pointer to Alarm structure
-  * @param  Format: Specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_FORMAT_BIN: Binary data format 
-  *             @arg RTC_FORMAT_BCD: BCD data format
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
-{
-  uint32_t tickstart = 0;
-  uint32_t tmpreg = 0, subsecondtmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-  assert_param(IS_RTC_ALARM(sAlarm->Alarm));
-  assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
-  assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
-  assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
-  assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  if(Format == RTC_FORMAT_BIN)
-  {
-    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
-    {
-      assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
-      assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
-    }
-    else
-    {
-      sAlarm->AlarmTime.TimeFormat = 0x00;
-      assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
-    }
-    assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
-    assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
-
-    if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
-    {
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
-    }
-    else
-    {
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
-    }
-
-    tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \
-              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \
-              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
-              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
-              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \
-              ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
-              ((uint32_t)sAlarm->AlarmMask));
-  }
-  else
-  {
-    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
-    {
-      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
-      assert_param(IS_RTC_HOUR12(tmpreg));
-      assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
-    }
-    else
-    {
-      sAlarm->AlarmTime.TimeFormat = 0x00;
-      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
-    }
-
-    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
-    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
-
-    if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
-    {
-      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
-    }
-    else
-    {
-      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
-    }
-
-    tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \
-              ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \
-              ((uint32_t) sAlarm->AlarmTime.Seconds) | \
-              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
-              ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \
-              ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
-              ((uint32_t)sAlarm->AlarmMask));   
-  }
-
-  /* Configure the Alarm A or Alarm B Sub Second registers */
-  subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Configure the Alarm register */
-  if(sAlarm->Alarm == RTC_ALARM_A)
-  {
-    /* Disable the Alarm A interrupt */
-    __HAL_RTC_ALARMA_DISABLE(hrtc);
-
-    /* In case of interrupt mode is used, the interrupt source must disabled */
-    __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
-
-    tickstart = HAL_GetTick();
-    /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
-    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-        
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        /* Process Unlocked */ 
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-
-    hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
-    /* Configure the Alarm A Sub Second register */
-    hrtc->Instance->ALRMASSR = subsecondtmpreg;
-    /* Configure the Alarm state: Enable Alarm */
-    __HAL_RTC_ALARMA_ENABLE(hrtc);
-  }
-  else
-  {
-    /* Disable the Alarm B interrupt */
-    __HAL_RTC_ALARMB_DISABLE(hrtc);
-
-    /* In case of interrupt mode is used, the interrupt source must disabled */
-    __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB);
-
-    tickstart = HAL_GetTick();
-    /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
-    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-
-    hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
-    /* Configure the Alarm B Sub Second register */
-    hrtc->Instance->ALRMBSSR = subsecondtmpreg;
-    /* Configure the Alarm state: Enable Alarm */
-    __HAL_RTC_ALARMB_ENABLE(hrtc);
-  }
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set the specified RTC Alarm with Interrupt.
-  * @param  hrtc: RTC handle
-  * @param  sAlarm: Pointer to Alarm structure
-  * @param  Format: Specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_FORMAT_BIN: Binary data format 
-  *             @arg RTC_FORMAT_BCD: BCD data format
-  * @note   The Alarm register can only be written when the corresponding Alarm
-  *         is disabled (Use the HAL_RTC_DeactivateAlarm()).   
-  * @note   The HAL_RTC_SetTime() must be called before enabling the Alarm feature.   
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
-{
-  uint32_t tickstart = 0;
-  uint32_t tmpreg = 0, subsecondtmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-  assert_param(IS_RTC_ALARM(sAlarm->Alarm));
-  assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
-  assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
-  assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
-  assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
-
-  /* Process Locked */ 
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  if(Format == RTC_FORMAT_BIN)
-  {
-    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
-    {
-      assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
-      assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
-    }
-    else
-    {
-      sAlarm->AlarmTime.TimeFormat = 0x00;
-      assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
-    }
-    assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
-    assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
-
-    if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
-    {
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
-    }
-    else
-    {
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
-    }
-    tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \
-              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \
-              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
-              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
-              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \
-              ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
-              ((uint32_t)sAlarm->AlarmMask));
-  }
-  else
-  {
-    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
-    {
-      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
-      assert_param(IS_RTC_HOUR12(tmpreg));
-      assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
-    } 
-    else
-    {
-      sAlarm->AlarmTime.TimeFormat = 0x00;
-      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
-    }
-
-    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
-    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
-    
-    if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
-    {
-      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
-    }
-    else
-    {
-      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
-    }
-    tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \
-              ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \
-              ((uint32_t) sAlarm->AlarmTime.Seconds) | \
-              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
-              ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \
-              ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
-              ((uint32_t)sAlarm->AlarmMask));     
-  }
-  /* Configure the Alarm A or Alarm B Sub Second registers */
-  subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Configure the Alarm register */
-  if(sAlarm->Alarm == RTC_ALARM_A)
-  {
-    /* Disable the Alarm A interrupt */
-    __HAL_RTC_ALARMA_DISABLE(hrtc);
-    
-    /* Clear flag alarm A */
-    __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
-
-    tickstart = HAL_GetTick();
-    /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
-    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_TIMEOUT; 
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-
-    hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
-    /* Configure the Alarm A Sub Second register */
-    hrtc->Instance->ALRMASSR = subsecondtmpreg;
-    /* Configure the Alarm state: Enable Alarm */
-    __HAL_RTC_ALARMA_ENABLE(hrtc);
-    /* Configure the Alarm interrupt */
-    __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA);
-  }
-  else
-  {
-    /* Disable the Alarm B interrupt */
-    __HAL_RTC_ALARMB_DISABLE(hrtc);
-    
-    /* Clear flag alarm B */
-    __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
-
-    tickstart = HAL_GetTick();
-    /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
-    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-
-    hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
-    /* Configure the Alarm B Sub Second register */
-    hrtc->Instance->ALRMBSSR = subsecondtmpreg;
-    /* Configure the Alarm state: Enable Alarm */
-    __HAL_RTC_ALARMB_ENABLE(hrtc);
-    /* Configure the Alarm interrupt */
-    __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB);
-  }
-
-  /* RTC Alarm Interrupt Configuration: EXTI configuration */
-  __HAL_RTC_ALARM_EXTI_ENABLE_IT();
-
-  __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_READY; 
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deactivate the specified RTC Alarm.
-  * @param  hrtc: RTC handle
-  * @param  Alarm: Specifies the Alarm.
-  *          This parameter can be one of the following values:
-  *            @arg RTC_ALARM_A:  AlarmA
-  *            @arg RTC_ALARM_B:  AlarmB
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
-{
-  uint32_t tickstart = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_ALARM(Alarm));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  if(Alarm == RTC_ALARM_A)
-  {
-    /* AlarmA */
-    __HAL_RTC_ALARMA_DISABLE(hrtc);
-
-    /* In case of interrupt mode is used, the interrupt source must disabled */
-    __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
-
-    tickstart = HAL_GetTick();
-
-    /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
-    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
-    {
-      if( (HAL_GetTick()  - tickstart ) > RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  else
-  {
-    /* AlarmB */
-    __HAL_RTC_ALARMB_DISABLE(hrtc);
-
-    /* In case of interrupt mode is used, the interrupt source must disabled */
-    __HAL_RTC_ALARM_DISABLE_IT(hrtc,RTC_IT_ALRB);
-
-    tickstart = HAL_GetTick();
-
-    /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
-    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK; 
-}
-
-/**
-  * @brief  Get the RTC Alarm value and masks.
-  * @param  hrtc: RTC handle
-  * @param  sAlarm: Pointer to Date structure
-  * @param  Alarm: Specifies the Alarm.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_ALARM_A: AlarmA
-  *             @arg RTC_ALARM_B: AlarmB  
-  * @param  Format: Specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_FORMAT_BIN: Binary data format 
-  *             @arg RTC_FORMAT_BCD: BCD data format
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
-{
-  uint32_t tmpreg = 0, subsecondtmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-  assert_param(IS_RTC_ALARM(Alarm));
-
-  if(Alarm == RTC_ALARM_A)
-  {
-    /* AlarmA */
-    sAlarm->Alarm = RTC_ALARM_A;
-
-    tmpreg = (uint32_t)(hrtc->Instance->ALRMAR);
-    subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR ) & RTC_ALRMASSR_SS);
-  }
-  else
-  {
-    sAlarm->Alarm = RTC_ALARM_B;
-
-    tmpreg = (uint32_t)(hrtc->Instance->ALRMBR);
-    subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS);
-  }
-
-  /* Fill the structure with the read parameters */
-  /* ALRMAR/ALRMBR registers have same mapping)  */
-  sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16);
-  sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8);
-  sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
-  sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16);
-  sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;
-  sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24);
-  sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
-  sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
-
-  if(Format == RTC_FORMAT_BIN)
-  {
-    sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
-    sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes);
-    sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds);
-    sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle Alarm interrupt request.
-  * @param  hrtc: RTC handle
-  * @retval None
-  */
-void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
-{
-  /* Get the AlarmA interrupt source enable status */
-  if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != RESET)
-  {
-    /* Get the pending status of the AlarmA Interrupt */
-    if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != RESET)
-    {
-      /* AlarmA callback */
-      HAL_RTC_AlarmAEventCallback(hrtc);
-
-      /* Clear the AlarmA interrupt pending bit */
-      __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
-    }
-  }
-
-  /* Get the AlarmB interrupt source enable status */
-  if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != RESET)
-  {
-    /* Get the pending status of the AlarmB Interrupt */
-    if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != RESET)
-    {
-      /* AlarmB callback */
-      HAL_RTCEx_AlarmBEventCallback(hrtc);
-
-      /* Clear the AlarmB interrupt pending bit */
-      __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
-    }
-  }
-
-  /* Clear the EXTI's line Flag for RTC Alarm */
-  __HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-}
-
-/**
-  * @brief  Alarm A callback.
-  * @param  hrtc: RTC handle
-  * @retval None
-  */
-__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_RTC_AlarmAEventCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Handle AlarmA Polling request.
-  * @param  hrtc: RTC handle
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
-
-  uint32_t tickstart = HAL_GetTick();   
-  
-  while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET)
-  {
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Clear the Alarm interrupt pending bit */
-  __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions 
- *  @brief   Peripheral Control functions 
- *
-@verbatim
- ===============================================================================
-                     ##### Peripheral Control functions #####
- ===============================================================================
-    [..]
-    This subsection provides functions allowing to
-      (+) Wait for RTC Time and Date Synchronization
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are
-  *         synchronized with RTC APB clock.
-  * @note   The RTC Resynchronization mode is write protected, use the 
-  *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
-  * @note   To read the calendar through the shadow registers after Calendar 
-  *         initialization, calendar update or after wakeup from low power modes
-  *         the software must first clear the RSF flag.
-  *         The software must then wait until it is set again before reading
-  *         the calendar, which means that the calendar registers have been
-  *         correctly copied into the RTC_TR and RTC_DR shadow registers.
-  * @param  hrtc: RTC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
-{
-  uint32_t tickstart = 0;
-
-  /* Clear RSF flag */
-  hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;
-
-  tickstart = HAL_GetTick();
-
-  /* Wait the registers to be synchronised */
-  while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET)
-  {
-    if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions 
- *  @brief   Peripheral State functions 
- *
-@verbatim   
- ===============================================================================
-                     ##### Peripheral State functions #####
- ===============================================================================  
-    [..]
-    This subsection provides functions allowing to
-      (+) Get RTC state
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Return the RTC handle state.
-  * @param  hrtc: RTC handle
-  * @retval HAL state
-  */
-HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)
-{
-  /* Return RTC handle state */
-  return hrtc->State;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Private_Functions RTC Private functions
-  * @{
-  */
-/**
-  * @brief  Enter the RTC Initialization mode.
-  * @note   The RTC Initialization mode is write protected, use the
-  *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
-  * @param  hrtc: RTC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)
-{
-  uint32_t tickstart = 0;
-
-  /* Check if the Initialization mode is set */
-  if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
-  {
-    /* Set the Initialization mode */
-    hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
-
-    tickstart = HAL_GetTick();
-    /* Wait till RTC is in INIT state and if Time out is reached exit */
-    while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
-    {
-      if((HAL_GetTick()  - tickstart ) > RTC_TIMEOUT_VALUE)
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  Convert a 2 digit decimal to BCD format.
-  * @param  Value: Byte to be converted
-  * @retval Converted byte
-  */
-uint8_t RTC_ByteToBcd2(uint8_t Value)
-{
-  uint32_t bcdhigh = 0;
-
-  while(Value >= 10)
-  {
-    bcdhigh++;
-    Value -= 10;
-  }
-
-  return  ((uint8_t)(bcdhigh << 4) | Value);
-}
-
-/**
-  * @brief  Convert from 2 digit BCD to Binary.
-  * @param  Value: BCD value to be converted
-  * @retval Converted word
-  */
-uint8_t RTC_Bcd2ToByte(uint8_t Value)
-{
-  uint32_t tmp = 0;
-  tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
-  return (tmp + (Value & (uint8_t)0x0F));
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_RTC_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/src/stm32l4xx_hal_rtc_ex.c b/stmhal/hal/l4/src/stm32l4xx_hal_rtc_ex.c
deleted file mode 100644
index 510f9e2a70..0000000000
--- a/stmhal/hal/l4/src/stm32l4xx_hal_rtc_ex.c
+++ /dev/null
@@ -1,1876 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_rtc_ex.c
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   Extended RTC HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the Real Time Clock (RTC) Extended peripheral:
-  *           + RTC Time Stamp functions
-  *           + RTC Tamper functions 
-  *           + RTC Wake-up functions
-  *           + Extended Control functions
-  *           + Extended RTC features functions    
-  *
-  @verbatim
-  ==============================================================================
-                  ##### How to use this driver #####
-  ==============================================================================
-  [..]
-    (+) Enable the RTC domain access.
-    (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
-        format using the HAL_RTC_Init() function.
-
-  *** RTC Wakeup configuration ***
-  ================================
-  [..] 
-    (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer()
-        function. You can also configure the RTC Wakeup timer with interrupt mode 
-        using the HAL_RTCEx_SetWakeUpTimer_IT() function.
-    (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer()
-        function.
-        
-  *** Outputs configuration ***
-  =============================
-  [..]  The RTC has 2 different outputs:
-    (+) RTC_ALARM: this output is used to manage the RTC Alarm A, Alarm B
-        and WaKeUp signals.
-        To output the selected RTC signal, use the HAL_RTC_Init() function.             
-    (+) RTC_CALIB: this output is 512Hz signal or 1Hz.
-        To enable the RTC_CALIB, use the HAL_RTCEx_SetCalibrationOutPut() function.
-    (+) Two pins can be used as RTC_ALARM or RTC_CALIB (PC13, PB2) managed on 
-        the RTC_OR register.
-    (+) When the RTC_CALIB or RTC_ALARM output is selected, the RTC_OUT pin is
-        automatically configured in output alternate function. 
-
-  *** Smooth digital Calibration configuration ***
-  ================================================
-  [..]
-    (+) Configure the RTC Original Digital Calibration Value and the corresponding
-        calibration cycle period (32s,16s and 8s) using the HAL_RTCEx_SetSmoothCalib() 
-        function.
-
-  *** TimeStamp configuration ***
-  ===============================
-  [..]
-    (+) Enable the RTC TimeStamp using the HAL_RTCEx_SetTimeStamp() function.
-        You can also configure the RTC TimeStamp with interrupt mode using the
-        HAL_RTCEx_SetTimeStamp_IT() function.
-    (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
-        function.
-
-  *** Internal TimeStamp configuration ***
-  ===============================
-  [..]
-    (+) Enable the RTC internal TimeStamp using the HAL_RTCEx_SetInternalTimeStamp() function.
-        User has to check internal timestamp occurrence using __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG.
-    (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
-        function.
-
-  *** Tamper configuration ***
-  ============================
-  [..]
-    (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge 
-        or Level according to the Tamper filter (if equal to 0 Edge else Level) 
-        value, sampling frequency, NoErase, MaskFlag,  precharge or discharge and
-        Pull-UP using the HAL_RTCEx_SetTamper() function. You can configure RTC Tamper
-        with interrupt mode using HAL_RTCEx_SetTamper_IT() function.
-    (+) The default configuration of the Tamper erases the backup registers. To avoid
-        erase, enable the NoErase field on the RTC_TAMPCR register.
-
-  *** Backup Data Registers configuration ***
-  ===========================================
-  [..]
-    (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite()
-        function.
-    (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead()
-        function.
-
-   @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************  
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup RTCEx RTCEx
-  * @brief RTC Extended HAL module driver
-  * @{
-  */
-
-#ifdef HAL_RTC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#if defined(RTC_TAMPER1_SUPPORT) && defined(RTC_TAMPER3_SUPPORT)
-#define RTC_TAMPCR_MASK               ((uint32_t)RTC_TAMPCR_TAMPTS    |\
-                                       (uint32_t)RTC_TAMPCR_TAMPFREQ  | (uint32_t)RTC_TAMPCR_TAMPFLT      | (uint32_t)RTC_TAMPCR_TAMPPRCH |\
-                                       (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE                                       |\
-                                       (uint32_t)RTC_TAMPCR_TAMP1IE   | (uint32_t)RTC_TAMPCR_TAMP1NOERASE | (uint32_t)RTC_TAMPCR_TAMP1MF  |\
-                                       (uint32_t)RTC_TAMPCR_TAMP2IE   | (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP2MF  |\
-                                       (uint32_t)RTC_TAMPCR_TAMP3IE   | (uint32_t)RTC_TAMPCR_TAMP3NOERASE | (uint32_t)RTC_TAMPCR_TAMP3MF)
-#elif defined(RTC_TAMPER1_SUPPORT)
-#define RTC_TAMPCR_MASK               ((uint32_t)RTC_TAMPCR_TAMPTS    |\
-                                       (uint32_t)RTC_TAMPCR_TAMPFREQ  | (uint32_t)RTC_TAMPCR_TAMPFLT      | (uint32_t)RTC_TAMPCR_TAMPPRCH |\
-                                       (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE                                       |\
-                                       (uint32_t)RTC_TAMPCR_TAMP1IE   | (uint32_t)RTC_TAMPCR_TAMP1NOERASE | (uint32_t)RTC_TAMPCR_TAMP1MF  |\
-                                       (uint32_t)RTC_TAMPCR_TAMP2IE   | (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP2MF)
-#elif defined(RTC_TAMPER3_SUPPORT)
-#define RTC_TAMPCR_MASK               ((uint32_t)RTC_TAMPCR_TAMPTS    |\
-                                       (uint32_t)RTC_TAMPCR_TAMPFREQ  | (uint32_t)RTC_TAMPCR_TAMPFLT      | (uint32_t)RTC_TAMPCR_TAMPPRCH |\
-                                       (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE                                       |\
-                                       (uint32_t)RTC_TAMPCR_TAMP2IE   | (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP2MF  |\
-                                       (uint32_t)RTC_TAMPCR_TAMP3IE   | (uint32_t)RTC_TAMPCR_TAMP3NOERASE | (uint32_t)RTC_TAMPCR_TAMP3MF)
-#else
-#define RTC_TAMPCR_MASK               ((uint32_t)RTC_TAMPCR_TAMPTS    |\
-                                       (uint32_t)RTC_TAMPCR_TAMPFREQ  | (uint32_t)RTC_TAMPCR_TAMPFLT      | (uint32_t)RTC_TAMPCR_TAMPPRCH |\
-                                       (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE                                       |\
-                                       (uint32_t)RTC_TAMPCR_TAMP2IE   | (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP2MF)
-#endif /* RTC_TAMPER1_SUPPORT && RTC_TAMPER3_SUPPORT */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
-  * @{
-  */
-
-
-/** @defgroup RTCEx_Exported_Functions_Group1 RTC TimeStamp and Tamper functions
- *  @brief   RTC TimeStamp and Tamper functions
-  *
-@verbatim
- ===============================================================================
-                 ##### RTC TimeStamp and Tamper functions #####
- ===============================================================================
- 
- [..] This section provide functions allowing to configure TimeStamp feature
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Set TimeStamp.
-  * @note   This API must be called before enabling the TimeStamp feature.
-  * @param  hrtc: RTC handle
-  * @param  TimeStampEdge: Specifies the pin edge on which the TimeStamp is
-  *         activated.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the  
-  *                                        rising edge of the related pin.
-  *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the 
-  *                                         falling edge of the related pin.
-  * @param  RTC_TimeStampPin: specifies the RTC TimeStamp Pin.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
-  *               The RTC TimeStamp Pin is per default PC13, but for reasons of
-  *               compatibility, this parameter is required.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
-  assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Get the RTC_CR register and clear the bits to be configured */
-  tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
-
-  tmpreg|= TimeStampEdge;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Configure the Time Stamp TSEDGE and Enable bits */
-  hrtc->Instance->CR = (uint32_t)tmpreg;
-
-  __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY; 
-
-  /* Process Unlocked */ 
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set TimeStamp with Interrupt.
-  * @param  hrtc: RTC handle
-  * @note   This API must be called before enabling the TimeStamp feature.
-  * @param  TimeStampEdge: Specifies the pin edge on which the TimeStamp is
-  *         activated.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the  
-  *                                        rising edge of the related pin.
-  *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the 
-  *                                         falling edge of the related pin.
-  * @param  RTC_TimeStampPin: Specifies the RTC TimeStamp Pin.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
-  *               The RTC TimeStamp Pin is per default PC13, but for reasons of
-  *               compatibility, this parameter is required.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
-  assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
-
-  /* Process Locked */ 
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Get the RTC_CR register and clear the bits to be configured */
-  tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
-
-  tmpreg |= TimeStampEdge;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Configure the Time Stamp TSEDGE and Enable bits */
-  hrtc->Instance->CR = (uint32_t)tmpreg;
-
-  __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
-
-  /* Enable IT timestamp */
-  __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS);
-
-  /* RTC timestamp Interrupt Configuration: EXTI configuration */
-  __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
-
-  __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deactivate TimeStamp.
-  * @param  hrtc: RTC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
-{
-  uint32_t tmpreg = 0;
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* In case of interrupt mode is used, the interrupt source must disabled */
-  __HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS);
-
-  /* Get the RTC_CR register and clear the bits to be configured */
-  tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
-
-  /* Configure the Time Stamp TSEDGE and Enable bits */
-  hrtc->Instance->CR = (uint32_t)tmpreg;
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set Internal TimeStamp.
-  * @note   This API must be called before enabling the internal TimeStamp feature.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc)
-{
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Configure the internal Time Stamp Enable bits */
-  __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(hrtc);
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */ 
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deactivate Internal TimeStamp.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc)
-{
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Configure the internal Time Stamp Enable bits */
-  __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(hrtc);
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Get the RTC TimeStamp value.
-  * @param  hrtc: RTC handle
-  * @param  sTimeStamp: Pointer to Time structure
-  * @param  sTimeStampDate: Pointer to Date structure
-  * @param  Format: specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_FORMAT_BIN: Binary data format 
-  *             @arg RTC_FORMAT_BCD: BCD data format
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format)
-{
-  uint32_t tmptime = 0, tmpdate = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-
-  /* Get the TimeStamp time and date registers values */
-  tmptime = (uint32_t)(hrtc->Instance->TSTR & RTC_TR_RESERVED_MASK);
-  tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK);
-
-  /* Fill the Time structure fields with the read parameters */
-  sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16);
-  sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8);
-  sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));
-  sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16);
-  sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR;
-
-  /* Fill the Date structure fields with the read parameters */
-  sTimeStampDate->Year = 0;
-  sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8);
-  sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
-  sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);
-
-  /* Check the input parameters format */
-  if(Format == RTC_FORMAT_BIN)
-  {
-    /* Convert the TimeStamp structure parameters to Binary format */
-    sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours);
-    sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes);
-    sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds);
-
-    /* Convert the DateTimeStamp structure parameters to Binary format */
-    sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month);
-    sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date);
-    sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay);
-  }
-
-  /* Clear the TIMESTAMP Flags */
-  __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_ITSF);
-  __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set Tamper.
-  * @note   By calling this API we disable the tamper interrupt for all tampers.
-  * @param  hrtc: RTC handle
-  * @param  sTamper: Pointer to Tamper Structure.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_TAMPER(sTamper->Tamper));
-  assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
-  assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase));
-  assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag));
-  assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
-  assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
-  assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
-  assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
-  assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Configure the tamper trigger */
-  if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
-  { 
-    sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1); 
-  }
-
-  if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
-  { 
-    sTamper->NoErase = 0;
-#if defined(RTC_TAMPER1_SUPPORT)
-    if((sTamper->Tamper & RTC_TAMPER_1) != 0)
-    {
-      sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE;
-    }
-#endif /* RTC_TAMPER1_SUPPORT */
-    if((sTamper->Tamper & RTC_TAMPER_2) != 0)
-    {
-      sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE;
-    }
-#if defined(RTC_TAMPER3_SUPPORT)
-    if((sTamper->Tamper & RTC_TAMPER_3) != 0)
-    {
-      sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE;
-    }
-#endif /* RTC_TAMPER3_SUPPORT */
-  }
-
-  if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)
-  {
-    sTamper->MaskFlag = 0;
-#if defined(RTC_TAMPER1_SUPPORT)
-    if((sTamper->Tamper & RTC_TAMPER_1) != 0)
-    {
-      sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF;
-    }
-#endif /* RTC_TAMPER1_SUPPORT */
-    if((sTamper->Tamper & RTC_TAMPER_2) != 0)
-    {
-      sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF;
-    }
-#if defined(RTC_TAMPER3_SUPPORT)
-    if((sTamper->Tamper & RTC_TAMPER_3) != 0)
-    {
-      sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF;
-    }
-#endif /* RTC_TAMPER3_SUPPORT */
-  }
-
-  tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger  | (uint32_t)sTamper->NoErase |\
-            (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\
-            (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
-
-  hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_MASK);
-
-  hrtc->Instance->TAMPCR |= tmpreg;
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set Tamper with interrupt.
-  * @note   By calling this API we force the tamper interrupt for all tampers.
-  * @param  hrtc: RTC handle
-  * @param  sTamper: Pointer to RTC Tamper.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_TAMPER(sTamper->Tamper));
-  assert_param(IS_RTC_TAMPER_INTERRUPT(sTamper->Interrupt));
-  assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
-  assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase));
-  assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag));
-  assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
-  assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
-  assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
-  assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
-  assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Configure the tamper trigger */
-  if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
-  {
-    sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1);
-  }
-
-  if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
-  { 
-    sTamper->NoErase = 0;
-#if defined(RTC_TAMPER1_SUPPORT)
-    if((sTamper->Tamper & RTC_TAMPER_1) != 0)
-    {
-      sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE;
-    }
-#endif /* RTC_TAMPER1_SUPPORT */
-    if((sTamper->Tamper & RTC_TAMPER_2) != 0)
-    {
-      sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE;
-    }
-#if defined(RTC_TAMPER3_SUPPORT)
-    if((sTamper->Tamper & RTC_TAMPER_3) != 0)
-    {
-      sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE;
-    }
-#endif /* RTC_TAMPER3_SUPPORT */
-  }
-
-  if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)
-  {
-    sTamper->MaskFlag = 0;
-#if defined(RTC_TAMPER1_SUPPORT)
-    if((sTamper->Tamper & RTC_TAMPER_1) != 0)
-    {
-      sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF;
-    }
-#endif /* RTC_TAMPER1_SUPPORT */
-    if((sTamper->Tamper & RTC_TAMPER_2) != 0)
-    {
-      sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF;
-    }
-#if defined(RTC_TAMPER3_SUPPORT)
-    if((sTamper->Tamper & RTC_TAMPER_3) != 0)
-    {
-      sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF;
-    }
-#endif /* RTC_TAMPER3_SUPPORT */
-  }
-
-  tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Interrupt | (uint32_t)sTamper->Trigger  | (uint32_t)sTamper->NoErase |\
-            (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\
-            (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
-
-  hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_MASK);
-  
-  hrtc->Instance->TAMPCR |= tmpreg;
-
-  /* RTC Tamper Interrupt Configuration: EXTI configuration */
-  __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
-
-  __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deactivate Tamper.
-  * @param  hrtc: RTC handle
-  * @param  Tamper: Selected tamper pin.
-  *          This parameter can be any combination of RTC_TAMPER_1, RTC_TAMPER_2 and RTC_TAMPER_3.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)
-{
-  assert_param(IS_RTC_TAMPER(Tamper));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the selected Tamper pin */
-  hrtc->Instance->TAMPCR &= ((uint32_t)~Tamper);
-
-#if defined(RTC_TAMPER1_SUPPORT)
-  if ((Tamper & RTC_TAMPER_1) != 0)
-  {
-    /* Disable the Tamper1 interrupt */
-    hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP1));
-  }
-#endif /* RTC_TAMPER1_SUPPORT */
-  if ((Tamper & RTC_TAMPER_2) != 0)
-  {
-    /* Disable the Tamper2 interrupt */
-    hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP2));
-  }
-#if defined(RTC_TAMPER3_SUPPORT)
-  if ((Tamper & RTC_TAMPER_3) != 0)
-  {
-    /* Disable the Tamper3 interrupt */
-    hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP3));
-  }
-#endif /* RTC_TAMPER3_SUPPORT */
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle TimeStamp interrupt request.
-  * @param  hrtc: RTC handle
-  * @retval None
-  */
-void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
-{ 
-  /* Get the TimeStamp interrupt source enable status */
-  if(__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != RESET)
-  {
-    /* Get the pending status of the TIMESTAMP Interrupt */
-    if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != RESET)
-    {
-      /* TIMESTAMP callback */ 
-      HAL_RTCEx_TimeStampEventCallback(hrtc);
-      
-      /* Clear the TIMESTAMP interrupt pending bit */
-      __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
-    }
-  }
-
-#if defined(RTC_TAMPER1_SUPPORT)
-  /* Get the Tamper1 interrupts source enable status */
-  if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP1) != RESET)
-  {
-    /* Get the pending status of the Tamper1 Interrupt */
-    if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != RESET)
-    {
-      /* Tamper1 callback */
-      HAL_RTCEx_Tamper1EventCallback(hrtc);
-
-      /* Clear the Tamper1 interrupt pending bit */
-      __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
-    }
-  }
-#endif /* RTC_TAMPER1_SUPPORT */
-    
-  /* Get the Tamper2 interrupts source enable status */
-  if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP2) != RESET)
-  {
-    /* Get the pending status of the Tamper2 Interrupt */
-    if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != RESET)
-    {
-      /* Tamper2 callback */
-      HAL_RTCEx_Tamper2EventCallback(hrtc);
-
-      /* Clear the Tamper2 interrupt pending bit */
-      __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
-    }
-  }
-
-#if defined(RTC_TAMPER3_SUPPORT)
-  /* Get the Tamper3 interrupts source enable status */
-  if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP3) != RESET)
-  {
-    /* Get the pending status of the Tamper3 Interrupt */
-    if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != RESET)
-    {
-      /* Tamper3 callback */
-      HAL_RTCEx_Tamper3EventCallback(hrtc);
-
-      /* Clear the Tamper3 interrupt pending bit */
-      __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);
-    }
-  }
-#endif /* RTC_TAMPER3_SUPPORT */
-  
-  /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */
-  __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-}
-
-/**
-  * @brief  TimeStamp callback. 
-  * @param  hrtc: RTC handle
-  * @retval None
-  */
-__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file
-  */
-}
-
-#if defined(RTC_TAMPER1_SUPPORT)
-/**
-  * @brief  Tamper 1 callback.
-  * @param  hrtc: RTC handle
-  * @retval None
-  */
-__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file
-   */
-}
-#endif /* RTC_TAMPER1_SUPPORT */
-
-/**
-  * @brief  Tamper 2 callback. 
-  * @param  hrtc: RTC handle
-  * @retval None
-  */
-__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file
-   */
-}
-
-#if defined(RTC_TAMPER3_SUPPORT)
-/**
-  * @brief  Tamper 3 callback. 
-  * @param  hrtc: RTC handle
-  * @retval None
-  */
-__weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file
-   */
-}
-#endif /* RTC_TAMPER3_SUPPORT */
-
-/**
-  * @brief  Handle TimeStamp polling request.
-  * @param  hrtc: RTC handle
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{ 
-  uint32_t tickstart = HAL_GetTick();
-
-  while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET)
-  {
-    if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET)
-    {
-      /* Clear the TIMESTAMP OverRun Flag */
-      __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
-
-      /* Change TIMESTAMP state */
-      hrtc->State = HAL_RTC_STATE_ERROR; 
-
-      return HAL_ERROR; 
-    }
-
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-  
-  return HAL_OK;
-}
-
-#if defined(RTC_TAMPER1_SUPPORT)
-/**
-  * @brief  Handle Tamper 1 Polling.
-  * @param  hrtc: RTC handle
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
-  uint32_t tickstart = HAL_GetTick();
-
-  /* Get the status of the Interrupt */
-  while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== RESET)
-  {
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Clear the Tamper Flag */
-  __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
-  
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-  
-  return HAL_OK; 
-}
-#endif /* RTC_TAMPER1_SUPPORT */
-
-/**
-  * @brief  Handle Tamper 2 Polling.
-  * @param  hrtc: RTC handle
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
-  uint32_t tickstart = HAL_GetTick();
-
-  /* Get the status of the Interrupt */
-  while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == RESET)
-  {
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Clear the Tamper Flag */
-  __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  return HAL_OK;
-}
-
-#if defined(RTC_TAMPER3_SUPPORT)
-/**
-  * @brief  Handle Tamper 3 Polling.
-  * @param  hrtc: RTC handle
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
-  uint32_t tickstart = HAL_GetTick();
-
-  /* Get the status of the Interrupt */
-  while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) == RESET)
-  {
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Clear the Tamper Flag */
-  __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  return HAL_OK;
-}
-#endif /* RTC_TAMPER3_SUPPORT */
-
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Exported_Functions_Group2 RTC Wake-up functions
-  * @brief    RTC Wake-up functions
-  *
-@verbatim   
- ===============================================================================
-                        ##### RTC Wake-up functions #####
- ===============================================================================  
-
- [..] This section provide functions allowing to configure Wake-up feature
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Set wake up timer.
-  * @param  hrtc: RTC handle
-  * @param  WakeUpCounter: Wake up counter
-  * @param  WakeUpClock: Wake up clock
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
-{
-  uint32_t tickstart = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
-  assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
-
-  /* Process Locked */ 
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
-  if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)
-  {
-    tickstart = HAL_GetTick();
-
-    /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
-    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET)
-    {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        /* Process Unlocked */ 
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
-
-  tickstart = HAL_GetTick();
-
-  /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
-  while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
-  {
-    if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-    {
-      /* Enable the write protection for RTC registers */
-      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-      hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-      /* Process Unlocked */ 
-      __HAL_UNLOCK(hrtc);
-
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Clear the Wakeup Timer clock source bits in CR register */
-  hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
-
-  /* Configure the clock source */
-  hrtc->Instance->CR |= (uint32_t)WakeUpClock;
-
-  /* Configure the Wakeup Timer counter */
-  hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
-
-   /* Enable the Wakeup Timer */
-  __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set wake up timer with interrupt.
-  * @param  hrtc: RTC handle
-  * @param  WakeUpCounter: Wake up counter
-  * @param  WakeUpClock: Wake up clock  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
-{
-  uint32_t tickstart = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
-  assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
-
-  /* Process Locked */ 
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
-  if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)
-  {
-    tickstart = HAL_GetTick();
-
-    /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
-    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET)
-    {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        /* Process Unlocked */ 
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
-
-  tickstart = HAL_GetTick();
-
-  /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
-  while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
-  {
-    if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-    {
-      /* Enable the write protection for RTC registers */
-      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-      hrtc->State = HAL_RTC_STATE_TIMEOUT; 
-
-      /* Process Unlocked */ 
-      __HAL_UNLOCK(hrtc);
-
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Configure the Wakeup Timer counter */
-  hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
-
-  /* Clear the Wakeup Timer clock source bits in CR register */
-  hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
-
-  /* Configure the clock source */
-  hrtc->Instance->CR |= (uint32_t)WakeUpClock;
-
-  /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
-  __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
-
-  __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
-
-  /* Configure the Interrupt in the RTC_CR register */
-  __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT);
-  
-  /* Enable the Wakeup Timer */
-  __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_READY; 
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deactivate wake up timer counter.
-  * @param  hrtc: RTC handle 
-  * @retval HAL status
-  */
-uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
-{
-  uint32_t tickstart = 0;
-
-  /* Process Locked */ 
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Disable the Wakeup Timer */
-  __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
-
-  /* In case of interrupt mode is used, the interrupt source must disabled */
-  __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT);
-
-  tickstart = HAL_GetTick();
-  /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
-  while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
-  {
-    if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-    {
-      /* Enable the write protection for RTC registers */
-      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-      hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hrtc);
-
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Get wake up timer counter.
-  * @param  hrtc: RTC handle 
-  * @retval Counter value
-  */
-uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
-{
-  /* Get the counter value */
-  return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT));
-}
-
-/**
-  * @brief  Handle Wake Up Timer interrupt request.
-  * @param  hrtc: RTC handle
-  * @retval None
-  */
-void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
-{
-  /* Get the pending status of the WAKEUPTIMER Interrupt */
-  if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != RESET)
-  {
-    /* WAKEUPTIMER callback */ 
-    HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
-      
-    /* Clear the WAKEUPTIMER interrupt pending bit */
-    __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
-  }
-
-
-  /* Clear the EXTI's line Flag for RTC WakeUpTimer */
-  __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
-  
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-}
-
-/**
-  * @brief  Wake Up Timer callback.
-  * @param  hrtc: RTC handle
-  * @retval None
-  */
-__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Handle Wake Up Timer Polling.
-  * @param  hrtc: RTC handle
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
-  uint32_t tickstart = HAL_GetTick();
-
-  while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET)
-  {
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-      
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Clear the WAKEUPTIMER Flag */
-  __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
-  
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-
-/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions
-  * @brief    Extended Peripheral Control functions
-  *
-@verbatim   
- ===============================================================================
-              ##### Extended Peripheral Control functions #####
- ===============================================================================  
-    [..]
-    This subsection provides functions allowing to
-      (+) Write a data in a specified RTC Backup data register
-      (+) Read a data in a specified RTC Backup data register
-      (+) Set the Coarse calibration parameters.
-      (+) Deactivate the Coarse calibration parameters
-      (+) Set the Smooth calibration parameters.
-      (+) Configure the Synchronization Shift Control Settings.
-      (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
-      (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
-      (+) Enable the RTC reference clock detection.
-      (+) Disable the RTC reference clock detection.
-      (+) Enable the Bypass Shadow feature.
-      (+) Disable the Bypass Shadow feature.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Write a data in a specified RTC Backup data register.
-  * @param  hrtc: RTC handle 
-  * @param  BackupRegister: RTC Backup data Register number.
-  *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to 
-  *                                 specify the register.
-  * @param  Data: Data to be written in the specified RTC Backup data register.
-  * @retval None
-  */
-void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
-{
-  uint32_t tmp = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_BKP(BackupRegister));
-
-  tmp = (uint32_t)&(hrtc->Instance->BKP0R);
-  tmp += (BackupRegister * 4);
-
-  /* Write the specified register */
-  *(__IO uint32_t *)tmp = (uint32_t)Data;
-}
-
-/**
-  * @brief  Read data from the specified RTC Backup data Register.
-  * @param  hrtc: RTC handle 
-  * @param  BackupRegister: RTC Backup data Register number.
-  *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to 
-  *                                 specify the register.
-  * @retval Read value
-  */
-uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
-{
-  uint32_t tmp = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_BKP(BackupRegister));
-
-  tmp = (uint32_t)&(hrtc->Instance->BKP0R);
-  tmp += (BackupRegister * 4);
-  
-  /* Read the specified register */
-  return (*(__IO uint32_t *)tmp);
-}
-
-/**
-  * @brief  Set the Smooth calibration parameters.
-  * @param  hrtc: RTC handle  
-  * @param  SmoothCalibPeriod: Select the Smooth Calibration Period.
-  *          This parameter can be can be one of the following values :
-  *             @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
-  *             @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
-  *             @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
-  * @param  SmoothCalibPlusPulses: Select to Set or reset the CALP bit.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses.
-  *             @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
-  * @param  SmoothCalibMinusPulsesValue: Select the value of CALM[8:0] bits.
-  *          This parameter can be one any value from 0 to 0x000001FF.
-  * @note   To deactivate the smooth calibration, the field SmoothCalibPlusPulses 
-  *         must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field
-  *         SmoothCalibMinusPulsesValue must be equal to 0.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
-{
-  uint32_t tickstart = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod));
-  assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses));
-  assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmoothCalibMinusPulsesValue));
-
-  /* Process Locked */ 
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* check if a calibration is pending*/
-  if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
-  {
-    tickstart = HAL_GetTick();
-
-    /* check if a calibration is pending*/
-    while((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        /* Change RTC state */
-        hrtc->State = HAL_RTC_STATE_TIMEOUT; 
-        
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Configure the Smooth calibration settings */
-  hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmoothCalibMinusPulsesValue);
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY; 
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configure the Synchronization Shift Control Settings.
-  * @note   When REFCKON is set, firmware must not write to Shift control register. 
-  * @param  hrtc: RTC handle    
-  * @param  ShiftAdd1S: Select to add or not 1 second to the time calendar.
-  *          This parameter can be one of the following values :
-  *             @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar. 
-  *             @arg RTC_SHIFTADD1S_RESET: No effect.
-  * @param  ShiftSubFS: Select the number of Second Fractions to substitute.
-  *          This parameter can be one any value from 0 to 0x7FFF.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
-{
-  uint32_t tickstart = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S));
-  assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS));
-
-  /* Process Locked */ 
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-    tickstart = HAL_GetTick();
-
-    /* Wait until the shift is completed*/
-    while((hrtc->Instance->ISR & RTC_ISR_SHPF) != RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        /* Process Unlocked */ 
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Check if the reference clock detection is disabled */
-    if((hrtc->Instance->CR & RTC_CR_REFCKON) == RESET)
-    {
-      /* Configure the Shift settings */
-      hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S);
-
-      /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
-      if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
-      {
-        if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
-        {
-          /* Enable the write protection for RTC registers */
-          __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-          hrtc->State = HAL_RTC_STATE_ERROR;
-
-          /* Process Unlocked */ 
-          __HAL_UNLOCK(hrtc);
-
-          return HAL_ERROR;
-        }
-      }
-    }
-    else
-    {
-      /* Enable the write protection for RTC registers */
-      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-      
-      /* Change RTC state */
-      hrtc->State = HAL_RTC_STATE_ERROR;
-      
-      /* Process Unlocked */ 
-      __HAL_UNLOCK(hrtc);
-
-      return HAL_ERROR;
-    }
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
-  * @param  hrtc: RTC handle
-  * @param  CalibOutput : Select the Calibration output Selection .
-  *          This parameter can be one of the following values:
-  *             @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
-  *             @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32_t CalibOutput)
-{
-  /* Check the parameters */
-  assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Clear flags before config */
-  hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL;
-
-  /* Configure the RTC_CR register */
-  hrtc->Instance->CR |= (uint32_t)CalibOutput;
-
-  __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc);
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
-  * @param  hrtc: RTC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc)
-{
-  /* Process Locked */ 
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc);
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enable the RTC reference clock detection.
-  * @param  hrtc: RTC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc)
-{
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Set Initialization mode */
-  if(RTC_EnterInitMode(hrtc) != HAL_OK)
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-    /* Set RTC state*/
-    hrtc->State = HAL_RTC_STATE_ERROR;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hrtc);
-
-    return HAL_ERROR;
-  }
-  else
-  {
-    __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc);
-
-    /* Exit Initialization mode */
-    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
-  }
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-   /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disable the RTC reference clock detection.
-  * @param  hrtc: RTC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc)
-{
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  
-  /* Set Initialization mode */
-  if(RTC_EnterInitMode(hrtc) != HAL_OK)
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-    /* Set RTC state*/
-    hrtc->State = HAL_RTC_STATE_ERROR;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hrtc);
-
-    return HAL_ERROR;
-  }
-  else
-  {
-    __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc);
-
-    /* Exit Initialization mode */
-    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
-  }
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enable the Bypass Shadow feature.
-  * @param  hrtc: RTC handle
-  * @note   When the Bypass Shadow is enabled the calendar value are taken
-  *         directly from the Calendar counter.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc)
-{
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Set the BYPSHAD bit */
-  hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD;
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disable the Bypass Shadow feature.
-  * @param  hrtc: RTC handle
-  * @note   When the Bypass Shadow is enabled the calendar value are taken
-  *         directly from the Calendar counter.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc)
-{
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Reset the BYPSHAD bit */
-  hrtc->Instance->CR &= ((uint8_t)~RTC_CR_BYPSHAD);
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions
-  * @brief    Extended features functions
-  *
-@verbatim   
- ===============================================================================
-                 ##### Extended features functions #####
- ===============================================================================  
-    [..]  This section provides functions allowing to:
-      (+) RTC Alarm B callback
-      (+) RTC Poll for Alarm B request
-               
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Alarm B callback.
-  * @param  hrtc: RTC handle
-  * @retval None
-  */
-__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_RTCEx_AlarmBEventCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Handle Alarm B Polling request.
-  * @param  hrtc: RTC handle
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{ 
-  uint32_t tickstart = HAL_GetTick();
-  
-  while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == RESET)
-  {
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Clear the Alarm Flag */
-  __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_RTC_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/src/stm32l4xx_hal_sd.c b/stmhal/hal/l4/src/stm32l4xx_hal_sd.c
deleted file mode 100644
index 10d4e8b0e5..0000000000
--- a/stmhal/hal/l4/src/stm32l4xx_hal_sd.c
+++ /dev/null
@@ -1,3436 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_sd.c
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   SD card HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the Secure Digital (SD) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions 
-  *           + Peripheral State functions
-  *         
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-  [..]
-    This driver implements a high level communication layer for read and write from/to 
-    this memory. The needed STM32 hardware resources (SDMMC1 and GPIO) are performed by 
-    the user in HAL_SD_MspInit() function (MSP layer).                             
-    Basically, the MSP layer configuration should be the same as we provide in the 
-    examples.
-    You can easily tailor this configuration according to hardware resources.
-
-  [..]
-    This driver is a generic layered driver for SDMMC memories which uses the HAL 
-    SDMMC driver functions to interface with SD and uSD cards devices. 
-    It is used as follows:
- 
-    (#)Initialize the SDMMC1 low level resources by implementing the HAL_SD_MspInit() API:
-        (##) Call the function HAL_RCCEx_PeriphCLKConfig with RCC_PERIPHCLK_SDMMC1 for
-        PeriphClockSelection and select SDMMC1 clock source (MSI, main PLL or PLLSAI1)
-        (##) Enable the SDMMC1 interface clock using __HAL_RCC_SDMMC1_CLK_ENABLE(); 
-        (##) SDMMC pins configuration for SD card
-            (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();   
-            (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init()
-                  and according to your pin assignment;
-        (##) DMA Configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA()
-             and HAL_SD_WriteBlocks_DMA() APIs).
-            (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE(); 
-            (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled. 
-        (##) NVIC configuration if you need to use interrupt process when using DMA transfer.
-            (+++) Configure the SDMMC and DMA interrupt priorities using functions
-                  HAL_NVIC_SetPriority(); DMA priority is superior to SDMMC's priority
-            (+++) Enable the NVIC DMA and SDMMC IRQs using function HAL_NVIC_EnableIRQ()
-            (+++) SDMMC interrupts are managed using the macros __HAL_SD_SDMMC_ENABLE_IT() 
-                  and __HAL_SD_SDMMC_DISABLE_IT() inside the communication process.
-            (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SD_SDMMC_GET_IT()
-                  and __HAL_SD_SDMMC_CLEAR_IT()
-    (#) At this stage, you can perform SD read/write/erase operations after SD card initialization  
-
-         
-  *** SD Card Initialization and configuration ***
-  ================================================    
-  [..]
-    To initialize the SD Card, use the HAL_SD_Init() function.  It Initializes 
-    the SD Card and put it into StandBy State (Ready for data transfer). 
-    This function provide the following operations:
-  
-    (#) Apply the SD Card initialization process at 400KHz and check the SD Card 
-        type (Standard Capacity or High Capacity). You can change or adapt this 
-        frequency by adjusting the "ClockDiv" field. 
-        The SD Card frequency (SDMMC_CK) is computed as follows:
-     (++)
-
-           SDMMC_CK = SDMMCCLK / (ClockDiv + 2)
-
-     -@@-  In initialization mode and according to the SD Card standard, 
-          make sure that the SDMMC_CK frequency doesn't exceed 400KHz.
-  
-    (#) Get the SD CID and CSD data. All these information are managed by the SDCardInfo 
-        structure. This structure provide also ready computed SD Card capacity 
-        and Block size.
-        
-        -@- These information are stored in SD handle structure in case of future use.  
-  
-    (#) Configure the SD Card Data transfer frequency. By Default, the card transfer 
-        frequency is set to 24MHz. You can change or adapt this frequency by adjusting 
-        the "ClockDiv" field.
-        In transfer mode and according to the SD Card standard, make sure that the 
-        SDMMC_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch.
-        To be able to use a frequency higher than 24MHz, you should use the SDMMC 
-        peripheral in bypass mode. Refer to the corresponding reference manual 
-        for more details.
-  
-    (#) Select the corresponding SD Card according to the address read with the step 2.
-    
-    (#) Configure the SD Card in wide bus mode: 4-bits data.
-  
-  *** SD Card Read operation ***
-  ==============================
-  [..] 
-    (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks(). 
-        This function support only 512-bytes block length (the block size should be 
-        chosen as 512 bytes).
-        You can choose either one block read operation or multiple block read operation 
-        by adjusting the "NumberOfBlocks" parameter.
-
-    (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().
-        This function support only 512-bytes block length (the block size should be 
-        chosen as 512 bytes).
-        You can choose either one block read operation or multiple block read operation 
-        by adjusting the "NumberOfBlocks" parameter.
-        After this, you have to call the function HAL_SD_CheckReadOperation(), to insure
-        that the read transfer is done correctly in both DMA and SD sides.
-  
-  *** SD Card Write operation ***
-  =============================== 
-  [..] 
-    (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks(). 
-        This function support only 512-bytes block length (the block size should be 
-        chosen as 512 bytes).
-        You can choose either one block read operation or multiple block read operation 
-        by adjusting the "NumberOfBlocks" parameter.
-
-    (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().
-        This function support only 512-bytes block length (the block size should be 
-        chosen as 512 byte).
-        You can choose either one block read operation or multiple block read operation 
-        by adjusting the "NumberOfBlocks" parameter.
-        After this, you have to call the function HAL_SD_CheckWriteOperation(), to insure
-        that the write transfer is done correctly in both DMA and SD sides.  
-  
-  *** SD card status ***
-  ====================== 
-  [..]
-    (+) At any time, you can check the SD Card status and get the SD card state 
-        by using the HAL_SD_GetStatus() function. This function checks first if the 
-        SD card is still connected and then get the internal SD Card transfer state.     
-    (+) You can also get the SD card SD Status register by using the HAL_SD_SendSDStatus() 
-        function.    
-
-  *** SD HAL driver macros list ***
-  ==================================
-  [..]
-    Below the list of most used macros in SD HAL driver.
-       
-    (+) __HAL_SD_SDMMC_ENABLE : Enable the SD device
-    (+) __HAL_SD_SDMMC_DISABLE : Disable the SD device
-    (+) __HAL_SD_SDMMC_DMA_ENABLE: Enable the SDMMC DMA transfer
-    (+) __HAL_SD_SDMMC_DMA_DISABLE: Disable the SDMMC DMA transfer
-    (+) __HAL_SD_SDMMC_ENABLE_IT: Enable the SD device interrupt
-    (+) __HAL_SD_SDMMC_DISABLE_IT: Disable the SD device interrupt
-    (+) __HAL_SD_SDMMC_GET_FLAG:Check whether the specified SD flag is set or not
-    (+) __HAL_SD_SDMMC_CLEAR_FLAG: Clear the SD's pending flags
-    [..]  
-    (@) You can refer to the SD HAL driver header file for more useful macros 
-      
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup SD 
-  * @{
-  */
-
-#ifdef HAL_SD_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup SD_Private_Defines
-  * @{
-  */
-/** 
-  * @brief  SDMMC Data block size 
-  */ 
-#define DATA_BLOCK_SIZE                  ((uint32_t)(9 << 4))
-/** 
-  * @brief  SDMMC Static flags, Timeout, FIFO Address  
-  */
-#define SDMMC_STATIC_FLAGS               ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\
-                                                    SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR  |\
-                                                    SDMMC_FLAG_CMDREND  | SDMMC_FLAG_CMDSENT  | SDMMC_FLAG_DATAEND  |\
-                                                    SDMMC_FLAG_DBCKEND))  
-
-#define SDMMC_CMD0TIMEOUT                ((uint32_t)0x00010000)
-
-/** 
-  * @brief  Mask for errors Card Status R1 (OCR Register) 
-  */
-#define SD_OCR_ADDR_OUT_OF_RANGE        ((uint32_t)0x80000000)
-#define SD_OCR_ADDR_MISALIGNED          ((uint32_t)0x40000000)
-#define SD_OCR_BLOCK_LEN_ERR            ((uint32_t)0x20000000)
-#define SD_OCR_ERASE_SEQ_ERR            ((uint32_t)0x10000000)
-#define SD_OCR_BAD_ERASE_PARAM          ((uint32_t)0x08000000)
-#define SD_OCR_WRITE_PROT_VIOLATION     ((uint32_t)0x04000000)
-#define SD_OCR_LOCK_UNLOCK_FAILED       ((uint32_t)0x01000000)
-#define SD_OCR_COM_CRC_FAILED           ((uint32_t)0x00800000)
-#define SD_OCR_ILLEGAL_CMD              ((uint32_t)0x00400000)
-#define SD_OCR_CARD_ECC_FAILED          ((uint32_t)0x00200000)
-#define SD_OCR_CC_ERROR                 ((uint32_t)0x00100000)
-#define SD_OCR_GENERAL_UNKNOWN_ERROR    ((uint32_t)0x00080000)
-#define SD_OCR_STREAM_READ_UNDERRUN     ((uint32_t)0x00040000)
-#define SD_OCR_STREAM_WRITE_OVERRUN     ((uint32_t)0x00020000)
-#define SD_OCR_CID_CSD_OVERWRITE        ((uint32_t)0x00010000)
-#define SD_OCR_WP_ERASE_SKIP            ((uint32_t)0x00008000)
-#define SD_OCR_CARD_ECC_DISABLED        ((uint32_t)0x00004000)
-#define SD_OCR_ERASE_RESET              ((uint32_t)0x00002000)
-#define SD_OCR_AKE_SEQ_ERROR            ((uint32_t)0x00000008)
-#define SD_OCR_ERRORBITS                ((uint32_t)0xFDFFE008)
-
-/** 
-  * @brief  Masks for R6 Response 
-  */
-#define SD_R6_GENERAL_UNKNOWN_ERROR     ((uint32_t)0x00002000)
-#define SD_R6_ILLEGAL_CMD               ((uint32_t)0x00004000)
-#define SD_R6_COM_CRC_FAILED            ((uint32_t)0x00008000)
-
-#define SD_VOLTAGE_WINDOW_SD            ((uint32_t)0x80100000)
-#define SD_HIGH_CAPACITY                ((uint32_t)0x40000000)
-#define SD_STD_CAPACITY                 ((uint32_t)0x00000000)
-#define SD_CHECK_PATTERN                ((uint32_t)0x000001AA)
-
-#define SD_MAX_VOLT_TRIAL               ((uint32_t)0x0000FFFF)
-#define SD_ALLZERO                      ((uint32_t)0x00000000)
-
-#define SD_WIDE_BUS_SUPPORT             ((uint32_t)0x00040000)
-#define SD_SINGLE_BUS_SUPPORT           ((uint32_t)0x00010000)
-#define SD_CARD_LOCKED                  ((uint32_t)0x02000000)
-
-#define SD_DATATIMEOUT                  ((uint32_t)0xFFFFFFFF)
-#define SD_0TO7BITS                     ((uint32_t)0x000000FF)
-#define SD_8TO15BITS                    ((uint32_t)0x0000FF00)
-#define SD_16TO23BITS                   ((uint32_t)0x00FF0000)
-#define SD_24TO31BITS                   ((uint32_t)0xFF000000)
-#define SD_MAX_DATA_LENGTH              ((uint32_t)0x01FFFFFF)
-
-#define SD_HALFFIFO                     ((uint32_t)0x00000008)
-#define SD_HALFFIFOBYTES                ((uint32_t)0x00000020)
-
-/** 
-  * @brief  Command Class Supported 
-  */
-#define SD_CCCC_LOCK_UNLOCK             ((uint32_t)0x00000080)
-#define SD_CCCC_WRITE_PROT              ((uint32_t)0x00000040)
-#define SD_CCCC_ERASE                   ((uint32_t)0x00000020)
-
-/** 
-  * @brief  Following commands are SD Card Specific commands.
-  *         SDMMC_APP_CMD should be sent before sending these commands. 
-  */
-#define SD_SDMMC_SEND_IF_COND            ((uint32_t)SD_CMD_HS_SEND_EXT_CSD)
-/**
-  * @}
-  */
-  
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup SD_Private_Functions_Prototypes
-  * @{
-  */
-static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t addr);
-static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd); 
-static HAL_SD_ErrorTypedef SD_PowerOFF(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus);
-static HAL_SD_CardStateTypedef SD_GetState(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *pStatus);
-static HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD);
-static HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA);
-static HAL_SD_ErrorTypedef SD_WideBus_Enable(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_WideBus_Disable(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR);  
-static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma);
-static void SD_DMA_RxError(DMA_HandleTypeDef *hdma);
-static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma);
-static void SD_DMA_TxError(DMA_HandleTypeDef *hdma);
-/**
-  * @}
-  */
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SD_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup SD_Exported_Functions_Group1
- *  @brief   Initialization and de-initialization functions 
- *
-@verbatim    
-  ==============================================================================
-          ##### Initialization and de-initialization functions #####
-  ==============================================================================
-  [..]  
-    This section provides functions allowing to initialize/de-initialize the SD
-    card device to be ready for use.
-      
- 
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the SD card according to the specified parameters in the 
-            SD_HandleTypeDef and initialize the associated handle.
-  * @param  hsd: SD handle
-  * @param  SDCardInfo: HAL_SD_CardInfoTypedef structure for SD card information   
-  * @retval HAL SD error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo)
-{ 
-  __IO HAL_SD_ErrorTypedef errorstate = SD_OK;
-  SD_InitTypeDef tmpinit;
-  
-  /* Initialize the low level hardware (MSP) */
-  HAL_SD_MspInit(hsd);
-  
-  /* Default SDMMC peripheral configuration for SD card initialization */
-  tmpinit.ClockEdge           = SDMMC_CLOCK_EDGE_RISING;
-  tmpinit.ClockBypass         = SDMMC_CLOCK_BYPASS_DISABLE;
-  tmpinit.ClockPowerSave      = SDMMC_CLOCK_POWER_SAVE_DISABLE;
-  tmpinit.BusWide             = SDMMC_BUS_WIDE_1B;
-  tmpinit.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
-  tmpinit.ClockDiv            = SDMMC_INIT_CLK_DIV;
-  
-  /* Initialize SDMMC peripheral interface with default configuration */
-  SDMMC_Init(hsd->Instance, tmpinit);
-  
-  /* Identify card operating voltage */
-  errorstate = SD_PowerON(hsd); 
-  
-  if(errorstate != SD_OK)     
-  {
-    return errorstate;
-  }
-  
-  /* Initialize the present SDMMC card(s) and put them in idle state */
-  errorstate = SD_Initialize_Cards(hsd);
-  
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Read CSD/CID MSD registers */
-  errorstate = HAL_SD_Get_CardInfo(hsd, SDCardInfo);
-  
-  if (errorstate == SD_OK)
-  {
-    /* Select the Card */
-    errorstate = SD_Select_Deselect(hsd, (uint32_t)(((uint32_t)SDCardInfo->RCA) << 16));
-  }
-  
-  /* Configure SDMMC peripheral interface */
-  SDMMC_Init(hsd->Instance, hsd->Init);   
-  
-  return errorstate;
-}
-
-/**
-  * @brief  De-Initializes the SD card.
-  * @param  hsd: SD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)
-{
-  
-  /* Set SD power state to off */ 
-  SD_PowerOFF(hsd);
-  
-  /* De-Initialize the MSP layer */
-  HAL_SD_MspDeInit(hsd);
-  
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  Initializes the SD MSP.
-  * @param  hsd: SD handle
-  * @retval None
-  */
-__weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsd);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SD_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  De-Initialize SD MSP.
-  * @param  hsd: SD handle
-  * @retval None
-  */
-__weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsd);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SD_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup SD_Exported_Functions_Group2
- *  @brief   Data transfer functions 
- *
-@verbatim   
-  ==============================================================================
-                        ##### IO operation functions #####
-  ==============================================================================  
-  [..]
-    This subsection provides a set of functions allowing to manage the data 
-    transfer from/to SD card.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Reads block(s) from a specified address in a card. The Data transfer 
-  *         is managed by polling mode.  
-  * @param  hsd: SD handle
-  * @param  pReadBuffer: pointer to the buffer that will contain the received data
-  * @param  BlockNumber: Block number from where data is to be read (byte address = BlockNumber * BlockSize)
-  * @param  BlockSize: SD card Data block size 
-  *   @note BlockSize must be 512 bytes.
-  * @param  NumberOfBlocks: Number of SD blocks to read   
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_BlockNumber(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint32_t BlockNumber, uint32_t BlockSize, uint32_t NumberOfBlocks)
-{
-  SDMMC_CmdInitTypeDef  sdmmc_cmdinitstructure;
-  SDMMC_DataInitTypeDef sdmmc_datainitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t count = 0, *tempbuff = (uint32_t *)pReadBuffer;
-  
-  /* Initialize data control register */
-  hsd->Instance->DCTRL = 0;
-  
-  uint32_t ReadAddr;
-  if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
-  {
-    BlockSize = 512;
-    ReadAddr = BlockNumber;
-  }
-  else
-  {
-    // should not overflow for standard-capacity cards
-    ReadAddr = BlockNumber * BlockSize;
-  }
-  
-  /* Set Block Size for Card */ 
-  sdmmc_cmdinitstructure.Argument         = (uint32_t) BlockSize;
-  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
-  sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
-  sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
-  sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
-  
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Configure the SD DPSM (Data Path State Machine) */
-  sdmmc_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
-  sdmmc_datainitstructure.DataLength    = NumberOfBlocks * BlockSize;
-  sdmmc_datainitstructure.DataBlockSize = DATA_BLOCK_SIZE;
-  sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
-  sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
-  sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;
-  SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);
-  
-  if(NumberOfBlocks > 1)
-  {
-    /* Send CMD18 READ_MULT_BLOCK with argument data address */
-    sdmmc_cmdinitstructure.CmdIndex = SD_CMD_READ_MULT_BLOCK;
-  }
-  else
-  {
-    /* Send CMD17 READ_SINGLE_BLOCK */
-    sdmmc_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK;    
-  }
-  
-  sdmmc_cmdinitstructure.Argument         = ReadAddr;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-  
-  /* Read block(s) in polling mode */
-  if(NumberOfBlocks > 1)
-  {
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK);
-    
-    if (errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-    
-    /* Poll on SDMMC flags */
-    while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
-    {
-      if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
-      {
-        /* Read data from SDMMC Rx FIFO */
-        for (count = 0; count < 8; count++)
-        {
-          *(tempbuff + count) = SDMMC_ReadFIFO(hsd->Instance);
-        }
-        
-        tempbuff += 8;
-      }
-    }      
-  }
-  else
-  {
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK); 
-    
-    if (errorstate != SD_OK)
-    {
-      return errorstate;
-    }    
-    
-    /* In case of single block transfer, no need of stop transfer at all */
-    while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))
-    {
-      if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
-      {
-        /* Read data from SDMMC Rx FIFO */
-        for (count = 0; count < 8; count++)
-        {
-          *(tempbuff + count) = SDMMC_ReadFIFO(hsd->Instance);
-        }
-        
-        tempbuff += 8;
-      }
-    }   
-  }
-  
-  /* Send stop transmission command in case of multiblock read */
-  if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1))
-  {    
-    if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) ||\
-      (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
-        (hsd->CardType == HIGH_CAPACITY_SD_CARD))
-    {
-      /* Send stop transmission command */
-      errorstate = HAL_SD_StopTransfer(hsd);
-    }
-  }
-  
-  /* Get error state */
-  if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
-  {
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
-    
-    errorstate = SD_DATA_TIMEOUT;
-    
-    return errorstate;
-  }
-  else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
-  {
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
-    
-    errorstate = SD_DATA_CRC_FAIL;
-    
-    return errorstate;
-  }
-  else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
-  {
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
-    
-    errorstate = SD_RX_OVERRUN;
-    
-    return errorstate;
-  }
-  else
-  {
-    /* No error flag set */
-  }
-  
-  count = SD_DATATIMEOUT;
-  
-  /* Empty FIFO if there is still any data */
-  while ((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) && (count > 0))
-  {
-    *tempbuff = SDMMC_ReadFIFO(hsd->Instance);
-    tempbuff++;
-    count--;
-  }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Allows to write block(s) to a specified address in a card. The Data
-  *         transfer is managed by polling mode.  
-  * @param  hsd: SD handle
-  * @param  pWriteBuffer: pointer to the buffer that will contain the data to transmit
-  * @param  BlockNumber: Block number to where data is to be written (byte address = BlockNumber * BlockSize) 
-  * @param  BlockSize: SD card Data block size 
-  * @note   BlockSize must be 512 bytes.
-  * @param  NumberOfBlocks: Number of SD blocks to write 
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_BlockNumber(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint32_t BlockNumber, uint32_t BlockSize, uint32_t NumberOfBlocks)
-{
-  SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
-  SDMMC_DataInitTypeDef sdmmc_datainitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t totalnumberofbytes = 0, bytestransferred = 0, count = 0, restwords = 0;
-  uint32_t *tempbuff = (uint32_t *)pWriteBuffer;
-  uint8_t cardstate  = 0;
-  
-  /* Initialize data control register */
-  hsd->Instance->DCTRL = 0;
-  
-  uint32_t WriteAddr;
-  if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
-  {
-    BlockSize = 512;
-    WriteAddr = BlockNumber;
-  }
-  else
-  {
-    // should not overflow for standard-capacity cards
-    WriteAddr = BlockNumber * BlockSize;
-  }
-  
-  /* Set Block Size for Card */ 
-  sdmmc_cmdinitstructure.Argument         = (uint32_t)BlockSize;
-  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
-  sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
-  sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
-  sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
-  
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  if(NumberOfBlocks > 1)
-  {
-    /* Send CMD25 WRITE_MULT_BLOCK with argument data address */
-    sdmmc_cmdinitstructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK;
-  }
-  else
-  {
-    /* Send CMD24 WRITE_SINGLE_BLOCK */
-    sdmmc_cmdinitstructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK;
-  }
-  
-  sdmmc_cmdinitstructure.Argument         = WriteAddr;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-  
-  /* Check for error conditions */
-  if(NumberOfBlocks > 1)
-  {
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK);
-  }
-  else
-  {
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK);
-  }  
-  
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Set total number of bytes to write */
-  totalnumberofbytes = NumberOfBlocks * BlockSize;
-  
-  /* Configure the SD DPSM (Data Path State Machine) */ 
-  sdmmc_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
-  sdmmc_datainitstructure.DataLength    = NumberOfBlocks * BlockSize;
-  sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
-  sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
-  sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
-  sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;
-  SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);
-  
-  /* Write block(s) in polling mode */
-  if(NumberOfBlocks > 1)
-  {
-    while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
-    {
-      if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE))
-      {
-        if ((totalnumberofbytes - bytestransferred) < 32)
-        {
-          restwords = ((totalnumberofbytes - bytestransferred) % 4 == 0) ? ((totalnumberofbytes - bytestransferred) / 4) : (( totalnumberofbytes -  bytestransferred) / 4 + 1);
-          
-          /* Write data to SDMMC Tx FIFO */
-          for (count = 0; count < restwords; count++)
-          {
-            SDMMC_WriteFIFO(hsd->Instance, tempbuff);
-            tempbuff++;
-            bytestransferred += 4;
-          }
-        }
-        else
-        {
-          /* Write data to SDMMC Tx FIFO */
-          for (count = 0; count < 8; count++)
-          {
-            SDMMC_WriteFIFO(hsd->Instance, (tempbuff + count));
-          }
-          
-          tempbuff += 8;
-          bytestransferred += 32;
-        }
-      }
-    }   
-  }
-  else
-  {
-    /* In case of single data block transfer no need of stop command at all */ 
-    while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))
-    {
-      if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE))
-      {
-        if ((totalnumberofbytes - bytestransferred) < 32)
-        {
-          restwords = ((totalnumberofbytes - bytestransferred) % 4 == 0) ? ((totalnumberofbytes - bytestransferred) / 4) : (( totalnumberofbytes -  bytestransferred) / 4 + 1);
-          
-          /* Write data to SDMMC Tx FIFO */
-          for (count = 0; count < restwords; count++)
-          {
-            SDMMC_WriteFIFO(hsd->Instance, tempbuff);
-            tempbuff++; 
-            bytestransferred += 4;
-          }
-        }
-        else
-        {
-          /* Write data to SDMMC Tx FIFO */
-          for (count = 0; count < 8; count++)
-          {
-            SDMMC_WriteFIFO(hsd->Instance, (tempbuff + count));
-          }
-          
-          tempbuff += 8;
-          bytestransferred += 32;
-        }
-      }
-    }  
-  }
-  
-  /* Send stop transmission command in case of multiblock write */
-  if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1))
-  {    
-    if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
-      (hsd->CardType == HIGH_CAPACITY_SD_CARD))
-    {
-      /* Send stop transmission command */
-      errorstate = HAL_SD_StopTransfer(hsd);
-    }
-  }
-  
-  /* Get error state */
-  if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
-  {
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
-    
-    errorstate = SD_DATA_TIMEOUT;
-    
-    return errorstate;
-  }
-  else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
-  {
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
-    
-    errorstate = SD_DATA_CRC_FAIL;
-    
-    return errorstate;
-  }
-  else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR))
-  {
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_TXUNDERR);
-    
-    errorstate = SD_TX_UNDERRUN;
-    
-    return errorstate;
-  }
-  else
-  {
-    /* No error flag set */
-  }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
-  
-  /* Wait till the card is in programming state */
-  errorstate = SD_IsCardProgramming(hsd, &cardstate);
-  
-  while ((errorstate == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING)))
-  {
-    errorstate = SD_IsCardProgramming(hsd, &cardstate);
-  }
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Reads block(s) from a specified address in a card. The Data transfer 
-  *         is managed by DMA mode. 
-  * @note   This API should be followed by the function HAL_SD_CheckReadOperation()
-  *         to check the completion of the read process   
-  * @param  hsd: SD handle                 
-  * @param  pReadBuffer: Pointer to the buffer that will contain the received data
-  * @param  BlockNumber: Block number from where data is to be read (byte address = BlockNumber * BlockSize)
-  * @param  BlockSize: SD card Data block size 
-  * @note   BlockSize must be 512 bytes.
-  * @param  NumberOfBlocks: Number of blocks to read.
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_BlockNumber_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint32_t BlockNumber, uint32_t BlockSize, uint32_t NumberOfBlocks)
-{
-  SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
-  SDMMC_DataInitTypeDef sdmmc_datainitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  
-  /* Initialize data control register */
-  hsd->Instance->DCTRL = 0;
-  
-  /* Initialize handle flags */
-  hsd->SdTransferCplt  = 0;
-  hsd->DmaTransferCplt = 0;
-  hsd->SdTransferErr   = SD_OK; 
-  
-  /* Initialize SD Read operation */
-  if(NumberOfBlocks > 1)
-  {
-    hsd->SdOperation = SD_READ_MULTIPLE_BLOCK;
-  }
-  else
-  {
-    hsd->SdOperation = SD_READ_SINGLE_BLOCK;
-  }
-  
-  /* Enable transfer interrupts */
-  __HAL_SD_SDMMC_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL |\
-                                 SDMMC_IT_DTIMEOUT |\
-                                 SDMMC_IT_DATAEND  |\
-                                 SDMMC_IT_RXOVERR));
-  
-  /* Enable SDMMC DMA transfer */
-  __HAL_SD_SDMMC_DMA_ENABLE(hsd);
-  
-  /* Configure DMA user callbacks */
-  hsd->hdmarx->XferCpltCallback  = SD_DMA_RxCplt;
-  hsd->hdmarx->XferErrorCallback = SD_DMA_RxError;
-
-  /* Change DMA direction Periph to Memory */
-  hsd->hdmarx->Init.Direction = DMA_PERIPH_TO_MEMORY;
-  hsd->hdmarx->Instance->CCR &= ~DMA_MEMORY_TO_PERIPH;
-  
-  /* Enable the DMA Channel */
-  HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pReadBuffer, (uint32_t)(BlockSize * NumberOfBlocks)/4);
-  
-  uint32_t ReadAddr;
-  if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
-  {
-    BlockSize = 512;
-    ReadAddr = BlockNumber;
-  }
-  else
-  {
-    // should not overflow for standard-capacity cards
-    ReadAddr = BlockNumber * BlockSize;
-  }
-  
-  /* Set Block Size for Card */ 
-  sdmmc_cmdinitstructure.Argument         = (uint32_t)BlockSize;
-  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
-  sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
-  sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
-  sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
-  
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Configure the SD DPSM (Data Path State Machine) */ 
-  sdmmc_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
-  sdmmc_datainitstructure.DataLength    = BlockSize * NumberOfBlocks;
-  sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
-  sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
-  sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
-  sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;
-  SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);
-  
-  /* Check number of blocks command */
-  if(NumberOfBlocks > 1)
-  {
-    /* Send CMD18 READ_MULT_BLOCK with argument data address */
-    sdmmc_cmdinitstructure.CmdIndex = SD_CMD_READ_MULT_BLOCK;
-  }
-  else
-  {
-    /* Send CMD17 READ_SINGLE_BLOCK */
-    sdmmc_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK;
-  }
-  
-  sdmmc_cmdinitstructure.Argument         = ReadAddr;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-  
-  /* Check for error conditions */
-  if(NumberOfBlocks > 1)
-  {
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK);
-  }
-  else
-  {
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK);
-  }
-  
-  /* Update the SD transfer error in SD handle */
-  hsd->SdTransferErr = errorstate;
-  
-  return errorstate;
-}
-
-
-/**
-  * @brief  Writes block(s) to a specified address in a card. The Data transfer 
-  *         is managed by DMA mode. 
-  * @note   This API should be followed by the function HAL_SD_CheckWriteOperation()
-  *         to check the completion of the write process (by SD current status polling).  
-  * @param  hsd: SD handle
-  * @param  pWriteBuffer: pointer to the buffer that will contain the data to transmit
-  * @param  @param  BlockNumber: Block number to where data is to be written (byte address = BlockNumber * BlockSize)
-  * @param  BlockSize: the SD card Data block size 
-  * @note   BlockSize must be 512 bytes.
-  * @param  NumberOfBlocks: Number of blocks to write
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_BlockNumber_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint32_t BlockNumber, uint32_t BlockSize, uint32_t NumberOfBlocks)
-{
-  SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
-  SDMMC_DataInitTypeDef sdmmc_datainitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  
-  /* Initialize data control register */
-  hsd->Instance->DCTRL = 0;
-  
-  /* Initialize handle flags */
-  hsd->SdTransferCplt  = 0;
-  hsd->DmaTransferCplt = 0;
-  hsd->SdTransferErr   = SD_OK;
-  
-  /* Initialize SD Write operation */
-  if(NumberOfBlocks > 1)
-  {
-    hsd->SdOperation = SD_WRITE_MULTIPLE_BLOCK;
-  }
-  else
-  {
-    hsd->SdOperation = SD_WRITE_SINGLE_BLOCK;
-  }  
-  
-  /* Enable transfer interrupts */
-  __HAL_SD_SDMMC_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL |\
-                                 SDMMC_IT_DTIMEOUT |\
-                                 SDMMC_IT_DATAEND  |\
-                                 SDMMC_IT_TXUNDERR)); 
-  
-  /* Configure DMA user callbacks */
-  hsd->hdmatx->XferCpltCallback  = SD_DMA_TxCplt;
-  hsd->hdmatx->XferErrorCallback = SD_DMA_TxError;
-
-  /* Change DMA direction Memory to Periph */
-  hsd->hdmatx->Init.Direction = DMA_MEMORY_TO_PERIPH;
-  hsd->hdmatx->Instance->CCR |= DMA_MEMORY_TO_PERIPH;
-  
-  /* Enable the DMA Channel */
-  HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pWriteBuffer, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BlockSize * NumberOfBlocks)/4);
-
-  /* Enable SDMMC DMA transfer */
-  __HAL_SD_SDMMC_DMA_ENABLE(hsd);
-  
-  uint32_t WriteAddr;
-  if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
-  {
-    BlockSize = 512;
-    WriteAddr = BlockNumber;
-  }
-  else
-  {
-    // should not overflow for standard-capacity cards
-    WriteAddr = BlockNumber * BlockSize;
-  }
-
-  /* Set Block Size for Card */ 
-  sdmmc_cmdinitstructure.Argument         = (uint32_t)BlockSize;
-  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
-  sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
-  sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
-  sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
-
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Check number of blocks command */
-  if(NumberOfBlocks <= 1)
-  {
-    /* Send CMD24 WRITE_SINGLE_BLOCK */
-    sdmmc_cmdinitstructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK;
-  }
-  else
-  {
-    /* Send CMD25 WRITE_MULT_BLOCK with argument data address */
-    sdmmc_cmdinitstructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK;
-  }
-  
-  sdmmc_cmdinitstructure.Argument         = (uint32_t)WriteAddr;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-
-  /* Check for error conditions */
-  if(NumberOfBlocks > 1)
-  {
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK);
-  }
-  else
-  {
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK);
-  }
-  
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Configure the SD DPSM (Data Path State Machine) */ 
-  sdmmc_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
-  sdmmc_datainitstructure.DataLength    = BlockSize * NumberOfBlocks;
-  sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
-  sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
-  sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
-  sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;
-  SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);
-  
-  hsd->SdTransferErr = errorstate;
-  
-  return errorstate;
-}
-
-/**
-  * @brief  This function waits until the SD DMA data read transfer is finished. 
-  *         This API should be called after HAL_SD_ReadBlocks_DMA() function
-  *         to insure that all data sent by the card is already transferred by the 
-  *         DMA controller.
-  * @param  hsd: SD handle
-  * @param  Timeout: Timeout duration  
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t timeout = Timeout;
-  uint32_t tmp1, tmp2;
-  HAL_SD_ErrorTypedef tmp3;
-  
-  /* Wait for DMA/SD transfer end or SD error variables to be in SD handle */
-  tmp1 = hsd->DmaTransferCplt; 
-  tmp2 = hsd->SdTransferCplt;
-  tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;
-    
-  while (((tmp1 & tmp2) == 0) && (tmp3 == SD_OK) && (timeout > 0))
-  {
-    tmp1 = hsd->DmaTransferCplt; 
-    tmp2 = hsd->SdTransferCplt;
-    tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;    
-    timeout--;
-  }
-
-  timeout = Timeout;
-  
-  /* Wait until the Rx transfer is no longer active */
-  while((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXACT)) && (timeout > 0))
-  {
-    timeout--;  
-  }
-  
-  /* Send stop command in multiblock read */
-  if (hsd->SdOperation == SD_READ_MULTIPLE_BLOCK)
-  {
-    errorstate = HAL_SD_StopTransfer(hsd);
-  }
-  
-  if ((timeout == 0) && (errorstate == SD_OK))
-  {
-    errorstate = SD_DATA_TIMEOUT;
-  }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
-  
-  /* Return error state */
-  if (hsd->SdTransferErr != SD_OK)
-  {
-    return (HAL_SD_ErrorTypedef)(hsd->SdTransferErr);
-  }
-  
-  return errorstate;
-}
-
-/**
-  * @brief  This function waits until the SD DMA data write transfer is finished. 
-  *         This API should be called after HAL_SD_WriteBlocks_DMA() function
-  *         to insure that all data sent by the card is already transferred by the 
-  *         DMA controller.
-  * @param  hsd: SD handle
-  * @param  Timeout: Timeout duration  
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t timeout = Timeout;
-  uint32_t tmp1, tmp2;
-  HAL_SD_ErrorTypedef tmp3;
-
-  /* Wait for DMA/SD transfer end or SD error variables to be in SD handle */
-  tmp1 = hsd->DmaTransferCplt; 
-  tmp2 = hsd->SdTransferCplt;
-  tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;
-    
-  while (((tmp1 & tmp2) == 0) && (tmp3 == SD_OK) && (timeout > 0))
-  {
-    tmp1 = hsd->DmaTransferCplt; 
-    tmp2 = hsd->SdTransferCplt;
-    tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;
-    timeout--;
-  }
-  
-  timeout = Timeout;
-  
-  /* Wait until the Tx transfer is no longer active */
-  while((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXACT))  && (timeout > 0))
-  {
-    timeout--;  
-  }
-
-  /* Send stop command in multiblock write */
-  if (hsd->SdOperation == SD_WRITE_MULTIPLE_BLOCK)
-  {
-    errorstate = HAL_SD_StopTransfer(hsd);
-  }
-  
-  if ((timeout == 0) && (errorstate == SD_OK))
-  {
-    errorstate = SD_DATA_TIMEOUT;
-  }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
-  
-  /* Return error state */
-  if (hsd->SdTransferErr != SD_OK)
-  {
-    return (HAL_SD_ErrorTypedef)(hsd->SdTransferErr);
-  }
-  
-  /* Wait until write is complete */
-  while(HAL_SD_GetStatus(hsd) != SD_TRANSFER_OK)
-  {    
-  }
-
-  return errorstate; 
-}
-
-/**
-  * @brief  Erases the specified memory area of the given SD card.
-  * @param  hsd: SD handle 
-  * @param  startaddr: Start byte address
-  * @param  endaddr: End byte address
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
-  
-  uint32_t delay         = 0;
-  __IO uint32_t maxdelay = 0;
-  uint8_t cardstate      = 0;
-  
-  /* Check if the card command class supports erase command */
-  if (((hsd->CSD[1] >> 20) & SD_CCCC_ERASE) == 0)
-  {
-    errorstate = SD_REQUEST_NOT_APPLICABLE;
-    
-    return errorstate;
-  }
-  
-  /* Get max delay value */
-  maxdelay = 120000 / (((hsd->Instance->CLKCR) & 0xFF) + 2);
-  
-  if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
-  {
-    errorstate = SD_LOCK_UNLOCK_FAILED;
-    
-    return errorstate;
-  }
-  
-  /* Get start and end block for high capacity cards */
-  if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
-  {
-    startaddr /= 512;
-    endaddr   /= 512;
-  }
-  
-  /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */
-  if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
-    (hsd->CardType == HIGH_CAPACITY_SD_CARD))
-  {
-    /* Send CMD32 SD_ERASE_GRP_START with argument as addr  */
-    sdmmc_cmdinitstructure.Argument         =(uint32_t)startaddr;
-    sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SD_ERASE_GRP_START;
-    sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
-    sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
-    sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
-    SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_START);
-    
-    if (errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-    
-    /* Send CMD33 SD_ERASE_GRP_END with argument as addr  */
-    sdmmc_cmdinitstructure.Argument         = (uint32_t)endaddr;
-    sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SD_ERASE_GRP_END;
-    SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_END);
-    
-    if (errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-  }
-  
-  /* Send CMD38 ERASE */
-  sdmmc_cmdinitstructure.Argument         = 0;
-  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_ERASE;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_ERASE);
-  
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  for (; delay < maxdelay; delay++)
-  {
-  }
-  
-  /* Wait until the card is in programming state */
-  errorstate = SD_IsCardProgramming(hsd, &cardstate);
-  
-  delay = SD_DATATIMEOUT;
-  
-  while ((delay > 0) && (errorstate == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING)))
-  {
-    errorstate = SD_IsCardProgramming(hsd, &cardstate);
-    delay--;
-  }
-  
-  return errorstate;
-}
-
-/**
-  * @brief  This function handles SD card interrupt request.
-  * @param  hsd: SD handle
-  * @retval None
-  */
-void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
-{  
-  /* Check for SDMMC interrupt flags */
-  if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_DATAEND))
-  {
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_IT_DATAEND);  
-      
-    /* SD transfer is complete */
-    hsd->SdTransferCplt = 1;
-
-    /* No transfer error */ 
-    hsd->SdTransferErr  = SD_OK;
-
-    HAL_SD_XferCpltCallback(hsd);  
-  }  
-  else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL))
-  {
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
-    
-    hsd->SdTransferErr = SD_DATA_CRC_FAIL;
-    
-    HAL_SD_XferErrorCallback(hsd);
-    
-  }
-  else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_DTIMEOUT))
-  {
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
-    
-    hsd->SdTransferErr = SD_DATA_TIMEOUT;
-    
-    HAL_SD_XferErrorCallback(hsd);
-  }
-  else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_RXOVERR))
-  {
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
-    
-    hsd->SdTransferErr = SD_RX_OVERRUN;
-    
-    HAL_SD_XferErrorCallback(hsd);
-  }
-  else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_TXUNDERR))
-  {
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_TXUNDERR);
-    
-    hsd->SdTransferErr = SD_TX_UNDERRUN;
-    
-    HAL_SD_XferErrorCallback(hsd);
-  }
-  else
-  {
-    /* No error flag set */
-  }  
-
-  /* Disable all SDMMC peripheral interrupt sources */
-  __HAL_SD_SDMMC_DISABLE_IT(hsd, SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_DATAEND  |\
-                                 SDMMC_IT_TXFIFOHE | SDMMC_IT_RXFIFOHF | SDMMC_IT_TXUNDERR |\
-                                 SDMMC_IT_RXOVERR);                               
-}
-
-
-/**
-  * @brief  SD end of transfer callback.
-  * @param  hsd: SD handle 
-  * @retval None
-  */
-__weak void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsd);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SD_XferCpltCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  SD Transfer Error callback.
-  * @param  hsd: SD handle
-  * @retval None
-  */
-__weak void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsd);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SD_XferErrorCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  SD Transfer complete Rx callback in non-blocking mode.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-__weak void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdma);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SD_DMA_RxCpltCallback could be implemented in the user file
-   */ 
-}  
-
-/**
-  * @brief  SD DMA transfer complete Rx error callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-__weak void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdma);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SD_DMA_RxErrorCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  SD Transfer complete Tx callback in non-blocking mode.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-__weak void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdma);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SD_DMA_TxCpltCallback could be implemented in the user file
-   */ 
-}  
-
-/**
-  * @brief  SD DMA transfer complete error Tx callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-__weak void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdma);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SD_DMA_TxErrorCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup SD_Exported_Functions_Group3
- *  @brief   management functions 
- *
-@verbatim   
-  ==============================================================================
-                      ##### Peripheral Control functions #####
-  ==============================================================================  
-  [..]
-    This subsection provides a set of functions allowing to control the SD card 
-    operations.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Returns information about specific card.
-  * @param  hsd: SD handle
-  * @param  pCardInfo: Pointer to a HAL_SD_CardInfoTypedef structure that  
-  *         contains all SD cardinformation  
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t tmp = 0;
-  
-  pCardInfo->CardType = (uint8_t)(hsd->CardType);
-  pCardInfo->RCA      = (uint16_t)(hsd->RCA);
-  
-  /* Byte 0 */
-  tmp = (hsd->CSD[0] & 0xFF000000) >> 24;
-  pCardInfo->SD_csd.CSDStruct      = (uint8_t)((tmp & 0xC0) >> 6);
-  pCardInfo->SD_csd.SysSpecVersion = (uint8_t)((tmp & 0x3C) >> 2);
-  pCardInfo->SD_csd.Reserved1      = tmp & 0x03;
-  
-  /* Byte 1 */
-  tmp = (hsd->CSD[0] & 0x00FF0000) >> 16;
-  pCardInfo->SD_csd.TAAC = (uint8_t)tmp;
-  
-  /* Byte 2 */
-  tmp = (hsd->CSD[0] & 0x0000FF00) >> 8;
-  pCardInfo->SD_csd.NSAC = (uint8_t)tmp;
-  
-  /* Byte 3 */
-  tmp = hsd->CSD[0] & 0x000000FF;
-  pCardInfo->SD_csd.MaxBusClkFrec = (uint8_t)tmp;
-  
-  /* Byte 4 */
-  tmp = (hsd->CSD[1] & 0xFF000000) >> 24;
-  pCardInfo->SD_csd.CardComdClasses = (uint16_t)(tmp << 4);
-  
-  /* Byte 5 */
-  tmp = (hsd->CSD[1] & 0x00FF0000) >> 16;
-  pCardInfo->SD_csd.CardComdClasses |= (uint16_t)((tmp & 0xF0) >> 4);
-  pCardInfo->SD_csd.RdBlockLen       = (uint8_t)(tmp & 0x0F);
-  
-  /* Byte 6 */
-  tmp = (hsd->CSD[1] & 0x0000FF00) >> 8;
-  pCardInfo->SD_csd.PartBlockRead   = (uint8_t)((tmp & 0x80) >> 7);
-  pCardInfo->SD_csd.WrBlockMisalign = (uint8_t)((tmp & 0x40) >> 6);
-  pCardInfo->SD_csd.RdBlockMisalign = (uint8_t)((tmp & 0x20) >> 5);
-  pCardInfo->SD_csd.DSRImpl         = (uint8_t)((tmp & 0x10) >> 4);
-  pCardInfo->SD_csd.Reserved2       = 0; /*!< Reserved */
-  
-  if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0))
-  {
-    pCardInfo->SD_csd.DeviceSize = (tmp & 0x03) << 10;
-    
-    /* Byte 7 */
-    tmp = (uint8_t)(hsd->CSD[1] & 0x000000FF);
-    pCardInfo->SD_csd.DeviceSize |= (tmp) << 2;
-    
-    /* Byte 8 */
-    tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000) >> 24);
-    pCardInfo->SD_csd.DeviceSize |= (tmp & 0xC0) >> 6;
-    
-    pCardInfo->SD_csd.MaxRdCurrentVDDMin = (tmp & 0x38) >> 3;
-    pCardInfo->SD_csd.MaxRdCurrentVDDMax = (tmp & 0x07);
-    
-    /* Byte 9 */
-    tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000) >> 16);
-    pCardInfo->SD_csd.MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5;
-    pCardInfo->SD_csd.MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2;
-    pCardInfo->SD_csd.DeviceSizeMul      = (tmp & 0x03) << 1;
-    /* Byte 10 */
-    tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00) >> 8);
-    pCardInfo->SD_csd.DeviceSizeMul |= (tmp & 0x80) >> 7;
-    
-    pCardInfo->CardCapacity  = (pCardInfo->SD_csd.DeviceSize + 1) ;
-    pCardInfo->CardCapacity *= (1 << (pCardInfo->SD_csd.DeviceSizeMul + 2));
-    pCardInfo->CardBlockSize = 1 << (pCardInfo->SD_csd.RdBlockLen);
-    pCardInfo->CardCapacity *= pCardInfo->CardBlockSize;
-  }
-  else if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
-  {
-    /* Byte 7 */
-    tmp = (uint8_t)(hsd->CSD[1] & 0x000000FF);
-    pCardInfo->SD_csd.DeviceSize = (tmp & 0x3F) << 16;
-    
-    /* Byte 8 */
-    tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000) >> 24);
-    
-    pCardInfo->SD_csd.DeviceSize |= (tmp << 8);
-    
-    /* Byte 9 */
-    tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000) >> 16);
-    
-    pCardInfo->SD_csd.DeviceSize |= (tmp);
-    
-    /* Byte 10 */
-    tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00) >> 8);
-    
-    pCardInfo->CardCapacity = (uint64_t)(((uint64_t)pCardInfo->SD_csd.DeviceSize + 1) * 512 * 1024);
-    pCardInfo->CardBlockSize = 512;    
-  }
-  else
-  {
-    /* Not supported card type */
-    errorstate = SD_ERROR;
-  }
-      
-  pCardInfo->SD_csd.EraseGrSize = (tmp & 0x40) >> 6;
-  pCardInfo->SD_csd.EraseGrMul  = (tmp & 0x3F) << 1;
-  
-  /* Byte 11 */
-  tmp = (uint8_t)(hsd->CSD[2] & 0x000000FF);
-  pCardInfo->SD_csd.EraseGrMul     |= (tmp & 0x80) >> 7;
-  pCardInfo->SD_csd.WrProtectGrSize = (tmp & 0x7F);
-  
-  /* Byte 12 */
-  tmp = (uint8_t)((hsd->CSD[3] & 0xFF000000) >> 24);
-  pCardInfo->SD_csd.WrProtectGrEnable = (tmp & 0x80) >> 7;
-  pCardInfo->SD_csd.ManDeflECC        = (tmp & 0x60) >> 5;
-  pCardInfo->SD_csd.WrSpeedFact       = (tmp & 0x1C) >> 2;
-  pCardInfo->SD_csd.MaxWrBlockLen     = (tmp & 0x03) << 2;
-  
-  /* Byte 13 */
-  tmp = (uint8_t)((hsd->CSD[3] & 0x00FF0000) >> 16);
-  pCardInfo->SD_csd.MaxWrBlockLen      |= (tmp & 0xC0) >> 6;
-  pCardInfo->SD_csd.WriteBlockPaPartial = (tmp & 0x20) >> 5;
-  pCardInfo->SD_csd.Reserved3           = 0;
-  pCardInfo->SD_csd.ContentProtectAppli = (tmp & 0x01);
-  
-  /* Byte 14 */
-  tmp = (uint8_t)((hsd->CSD[3] & 0x0000FF00) >> 8);
-  pCardInfo->SD_csd.FileFormatGrouop = (tmp & 0x80) >> 7;
-  pCardInfo->SD_csd.CopyFlag         = (tmp & 0x40) >> 6;
-  pCardInfo->SD_csd.PermWrProtect    = (tmp & 0x20) >> 5;
-  pCardInfo->SD_csd.TempWrProtect    = (tmp & 0x10) >> 4;
-  pCardInfo->SD_csd.FileFormat       = (tmp & 0x0C) >> 2;
-  pCardInfo->SD_csd.ECC              = (tmp & 0x03);
-  
-  /* Byte 15 */
-  tmp = (uint8_t)(hsd->CSD[3] & 0x000000FF);
-  pCardInfo->SD_csd.CSD_CRC   = (tmp & 0xFE) >> 1;
-  pCardInfo->SD_csd.Reserved4 = 1;
-  
-  /* Byte 0 */
-  tmp = (uint8_t)((hsd->CID[0] & 0xFF000000) >> 24);
-  pCardInfo->SD_cid.ManufacturerID = tmp;
-  
-  /* Byte 1 */
-  tmp = (uint8_t)((hsd->CID[0] & 0x00FF0000) >> 16);
-  pCardInfo->SD_cid.OEM_AppliID = tmp << 8;
-  
-  /* Byte 2 */
-  tmp = (uint8_t)((hsd->CID[0] & 0x000000FF00) >> 8);
-  pCardInfo->SD_cid.OEM_AppliID |= tmp;
-  
-  /* Byte 3 */
-  tmp = (uint8_t)(hsd->CID[0] & 0x000000FF);
-  pCardInfo->SD_cid.ProdName1 = tmp << 24;
-  
-  /* Byte 4 */
-  tmp = (uint8_t)((hsd->CID[1] & 0xFF000000) >> 24);
-  pCardInfo->SD_cid.ProdName1 |= tmp << 16;
-  
-  /* Byte 5 */
-  tmp = (uint8_t)((hsd->CID[1] & 0x00FF0000) >> 16);
-  pCardInfo->SD_cid.ProdName1 |= tmp << 8;
-  
-  /* Byte 6 */
-  tmp = (uint8_t)((hsd->CID[1] & 0x0000FF00) >> 8);
-  pCardInfo->SD_cid.ProdName1 |= tmp;
-  
-  /* Byte 7 */
-  tmp = (uint8_t)(hsd->CID[1] & 0x000000FF);
-  pCardInfo->SD_cid.ProdName2 = tmp;
-  
-  /* Byte 8 */
-  tmp = (uint8_t)((hsd->CID[2] & 0xFF000000) >> 24);
-  pCardInfo->SD_cid.ProdRev = tmp;
-  
-  /* Byte 9 */
-  tmp = (uint8_t)((hsd->CID[2] & 0x00FF0000) >> 16);
-  pCardInfo->SD_cid.ProdSN = tmp << 24;
-  
-  /* Byte 10 */
-  tmp = (uint8_t)((hsd->CID[2] & 0x0000FF00) >> 8);
-  pCardInfo->SD_cid.ProdSN |= tmp << 16;
-  
-  /* Byte 11 */
-  tmp = (uint8_t)(hsd->CID[2] & 0x000000FF);
-  pCardInfo->SD_cid.ProdSN |= tmp << 8;
-  
-  /* Byte 12 */
-  tmp = (uint8_t)((hsd->CID[3] & 0xFF000000) >> 24);
-  pCardInfo->SD_cid.ProdSN |= tmp;
-  
-  /* Byte 13 */
-  tmp = (uint8_t)((hsd->CID[3] & 0x00FF0000) >> 16);
-  pCardInfo->SD_cid.Reserved1   |= (tmp & 0xF0) >> 4;
-  pCardInfo->SD_cid.ManufactDate = (tmp & 0x0F) << 8;
-  
-  /* Byte 14 */
-  tmp = (uint8_t)((hsd->CID[3] & 0x0000FF00) >> 8);
-  pCardInfo->SD_cid.ManufactDate |= tmp;
-  
-  /* Byte 15 */
-  tmp = (uint8_t)(hsd->CID[3] & 0x000000FF);
-  pCardInfo->SD_cid.CID_CRC   = (tmp & 0xFE) >> 1;
-  pCardInfo->SD_cid.Reserved2 = 1;
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Enables wide bus operation for the requested card if supported by 
-  *         card.
-  * @param  hsd: SD handle       
-  * @param  WideMode: Specifies the SD card wide bus mode 
-  *          This parameter can be one of the following values:
-  *            @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer (Only for MMC)
-  *            @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer
-  *            @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  SDMMC_InitTypeDef tmpinit;
-  
-  /* MMC Card does not support this feature */
-  if (hsd->CardType == MULTIMEDIA_CARD)
-  {
-    errorstate = SD_UNSUPPORTED_FEATURE;
-    
-    return errorstate;
-  }
-  else if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
-    (hsd->CardType == HIGH_CAPACITY_SD_CARD))
-  {
-    if (WideMode == SDMMC_BUS_WIDE_8B)
-    {
-      errorstate = SD_UNSUPPORTED_FEATURE;
-    }
-    else if (WideMode == SDMMC_BUS_WIDE_4B)
-    {
-      errorstate = SD_WideBus_Enable(hsd);
-    }
-    else if (WideMode == SDMMC_BUS_WIDE_1B)
-    {
-      errorstate = SD_WideBus_Disable(hsd);
-    }
-    else
-    {
-      /* WideMode is not a valid argument*/
-      errorstate = SD_INVALID_PARAMETER;
-    }
-      
-    if (errorstate == SD_OK)
-    {
-      /* Configure the SDMMC peripheral */
-      tmpinit.ClockEdge           = hsd->Init.ClockEdge;
-      tmpinit.ClockBypass         = hsd->Init.ClockBypass;
-      tmpinit.ClockPowerSave      = hsd->Init.ClockPowerSave;
-      tmpinit.BusWide             = WideMode;
-      tmpinit.HardwareFlowControl = hsd->Init.HardwareFlowControl;
-      tmpinit.ClockDiv            = hsd->Init.ClockDiv;
-      SDMMC_Init(hsd->Instance, tmpinit);
-    }
-  }
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Aborts an ongoing data transfer.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd)
-{
-  SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  
-  /* Send CMD12 STOP_TRANSMISSION  */
-  sdmmc_cmdinitstructure.Argument         = 0;
-  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_STOP_TRANSMISSION;
-  sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
-  sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
-  sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_STOP_TRANSMISSION);
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Switches the SD card to High Speed mode.
-  *         This API must be used after "Transfer State"
-  * @note   This operation should be followed by the configuration 
-  *         of PLL to have SDMMCCK clock between 67 and 75 MHz
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
-  SDMMC_DataInitTypeDef sdmmc_datainitstructure;
-  
-  uint8_t SD_hs[64]  = {0};
-  uint32_t SD_scr[2] = {0, 0};
-  uint32_t SD_SPEC   = 0 ;
-  uint32_t count = 0, *tempbuff = (uint32_t *)SD_hs;
-  
-  /* Initialize the Data control register */
-  hsd->Instance->DCTRL = 0;
-  
-  /* Get SCR Register */
-  errorstate = SD_FindSCR(hsd, SD_scr);
-  
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Test the Version supported by the card*/ 
-  SD_SPEC = (SD_scr[1]  & 0x01000000) | (SD_scr[1]  & 0x02000000);
-  
-  if (SD_SPEC != SD_ALLZERO)
-  {
-    /* Set Block Size for Card */
-    sdmmc_cmdinitstructure.Argument         = (uint32_t)64;
-    sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
-    sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
-    sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
-    sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
-    SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
-    
-    if (errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-    
-    /* Configure the SD DPSM (Data Path State Machine) */
-    sdmmc_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
-    sdmmc_datainitstructure.DataLength    = 64;
-    sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ;
-    sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
-    sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
-    sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;
-    SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);
-    
-    /* Send CMD6 switch mode */
-    sdmmc_cmdinitstructure.Argument         = 0x80FFFF01;
-    sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_HS_SWITCH;
-    SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); 
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_HS_SWITCH);
-    
-    if (errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-        
-    while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))
-    {
-      if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
-      {
-        for (count = 0; count < 8; count++)
-        {
-          *(tempbuff + count) = SDMMC_ReadFIFO(hsd->Instance);
-        }
-        
-        tempbuff += 8;
-      }
-    }
-    
-    if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
-    {
-      __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
-      
-      errorstate = SD_DATA_TIMEOUT;
-      
-      return errorstate;
-    }
-    else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
-    {
-      __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
-      
-      errorstate = SD_DATA_CRC_FAIL;
-      
-      return errorstate;
-    }
-    else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
-    {
-      __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
-      
-      errorstate = SD_RX_OVERRUN;
-      
-      return errorstate;
-    }
-    else
-    {
-      /* No error flag set */
-    }
-        
-    count = SD_DATATIMEOUT;
-    
-    while ((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) && (count > 0))
-    {
-      *tempbuff = SDMMC_ReadFIFO(hsd->Instance);
-      tempbuff++;
-      count--;
-    }
-    
-    /* Clear all the static flags */
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
-    
-    /* Test if the switch mode HS is ok */
-    if ((SD_hs[13]& 2) != 2)
-    {
-      errorstate = SD_UNSUPPORTED_FEATURE;
-    } 
-  }
-  
-  return errorstate;
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup SD_Exported_Functions_Group4
- *  @brief   Peripheral State functions 
- *
-@verbatim   
-  ==============================================================================
-                      ##### Peripheral State functions #####
-  ==============================================================================  
-  [..]
-    This subsection permits to get in runtime the status of the peripheral 
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Returns the current SD card's status.
-  * @param  hsd: SD handle
-  * @param  pSDstatus: Pointer to the buffer that will contain the SD card status 
-  *         SD Status register)
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
-{
-  SDMMC_CmdInitTypeDef  sdmmc_cmdinitstructure;
-  SDMMC_DataInitTypeDef sdmmc_datainitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t count = 0;
-  
-  /* Check SD response */
-  if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
-  {
-    errorstate = SD_LOCK_UNLOCK_FAILED;
-    
-    return errorstate;
-  }
-  
-  /* Set block size for card if it is not equal to current block size for card */
-  sdmmc_cmdinitstructure.Argument         = 64;
-  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
-  sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
-  sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
-  sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
-  
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Send CMD55 */
-  sdmmc_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16);
-  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
-  
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Configure the SD DPSM (Data Path State Machine) */ 
-  sdmmc_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
-  sdmmc_datainitstructure.DataLength    = 64;
-  sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B;
-  sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
-  sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
-  sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;
-  SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);
-  
-  /* Send ACMD13 (SD_APP_STAUS)  with argument as card's RCA */
-  sdmmc_cmdinitstructure.Argument         = 0;
-  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SD_APP_STATUS;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_STATUS);
-  
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Get status data */
-  while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))
-  {
-    if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
-    {
-      for (count = 0; count < 8; count++)
-      {
-        *(pSDstatus + count) = SDMMC_ReadFIFO(hsd->Instance);
-      }
-      
-      pSDstatus += 8;
-    }
-  }
-  
-  if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
-  {
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
-    
-    errorstate = SD_DATA_TIMEOUT;
-    
-    return errorstate;
-  }
-  else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
-  {
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
-    
-    errorstate = SD_DATA_CRC_FAIL;
-    
-    return errorstate;
-  }
-  else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
-  {
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
-    
-    errorstate = SD_RX_OVERRUN;
-    
-    return errorstate;
-  }
-  else
-  {
-    /* No error flag set */
-  }  
-  
-  count = SD_DATATIMEOUT;
-  while ((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) && (count > 0))
-  {
-    *pSDstatus = SDMMC_ReadFIFO(hsd->Instance);
-    pSDstatus++;
-    count--;
-  }
-  
-  /* Clear all the static status flags*/
-  __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Gets the current sd card data status.
-  * @param  hsd: SD handle
-  * @retval Data Transfer state
-  */
-HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd)
-{
-  HAL_SD_CardStateTypedef cardstate =  SD_CARD_TRANSFER;
-
-  /* Get SD card state */
-  cardstate = SD_GetState(hsd);
-  
-  /* Find SD status according to card state*/
-  if (cardstate == SD_CARD_TRANSFER)
-  {
-    return SD_TRANSFER_OK;
-  }
-  else if(cardstate == SD_CARD_ERROR)
-  {
-    return SD_TRANSFER_ERROR;
-  }
-  else
-  {
-    return SD_TRANSFER_BUSY;
-  }
-}
-
-/**
-  * @brief  Gets the SD card status.
-  * @param  hsd: SD handle      
-  * @param  pCardStatus: Pointer to the HAL_SD_CardStatusTypedef structure that 
-  *         will contain the SD card status information 
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t tmp = 0;
-  uint32_t sd_status[16];
-  
-  errorstate = HAL_SD_SendSDStatus(hsd, sd_status);
-  
-  if (errorstate  != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Byte 0 */
-  tmp = (sd_status[0] & 0xC0) >> 6;
-  pCardStatus->DAT_BUS_WIDTH = (uint8_t)tmp;
-  
-  /* Byte 0 */
-  tmp = (sd_status[0] & 0x20) >> 5;
-  pCardStatus->SECURED_MODE = (uint8_t)tmp;
-  
-  /* Byte 2 */
-  tmp = (sd_status[2] & 0xFF);
-  pCardStatus->SD_CARD_TYPE = (uint8_t)(tmp << 8);
-  
-  /* Byte 3 */
-  tmp = (sd_status[3] & 0xFF);
-  pCardStatus->SD_CARD_TYPE |= (uint8_t)tmp;
-  
-  /* Byte 4 */
-  tmp = (sd_status[4] & 0xFF);
-  pCardStatus->SIZE_OF_PROTECTED_AREA = (uint8_t)(tmp << 24);
-  
-  /* Byte 5 */
-  tmp = (sd_status[5] & 0xFF);
-  pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)(tmp << 16);
-  
-  /* Byte 6 */
-  tmp = (sd_status[6] & 0xFF);
-  pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)(tmp << 8);
-  
-  /* Byte 7 */
-  tmp = (sd_status[7] & 0xFF);
-  pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)tmp;
-  
-  /* Byte 8 */
-  tmp = (sd_status[8] & 0xFF);
-  pCardStatus->SPEED_CLASS = (uint8_t)tmp;
-  
-  /* Byte 9 */
-  tmp = (sd_status[9] & 0xFF);
-  pCardStatus->PERFORMANCE_MOVE = (uint8_t)tmp;
-  
-  /* Byte 10 */
-  tmp = (sd_status[10] & 0xF0) >> 4;
-  pCardStatus->AU_SIZE = (uint8_t)tmp;
-  
-  /* Byte 11 */
-  tmp = (sd_status[11] & 0xFF);
-  pCardStatus->ERASE_SIZE = (uint8_t)(tmp << 8);
-  
-  /* Byte 12 */
-  tmp = (sd_status[12] & 0xFF);
-  pCardStatus->ERASE_SIZE |= (uint8_t)tmp;
-  
-  /* Byte 13 */
-  tmp = (sd_status[13] & 0xFC) >> 2;
-  pCardStatus->ERASE_TIMEOUT = (uint8_t)tmp;
-  
-  /* Byte 13 */
-  tmp = (sd_status[13] & 0x3);
-  pCardStatus->ERASE_OFFSET = (uint8_t)tmp;
-  
-  return errorstate;
-}
-         
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-  
-/* Private function ----------------------------------------------------------*/  
-/** @addtogroup SD_Private_Functions
-  * @{
-  */
-  
-/**
-  * @brief  SD DMA transfer complete Rx callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma)
-{
-  SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-  
-  /* DMA transfer is complete */
-  hsd->DmaTransferCplt = 1;
-  
-  /* Wait until SD transfer is complete */
-  while(hsd->SdTransferCplt == 0)
-  {
-  }
-  
-  /* Disable the DMA channel */
-  HAL_DMA_Abort(hdma);
-
-  /* Transfer complete user callback */
-  HAL_SD_DMA_RxCpltCallback(hsd->hdmarx);   
-}
-
-/**
-  * @brief  SD DMA transfer Error Rx callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SD_DMA_RxError(DMA_HandleTypeDef *hdma)
-{
-  SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-  
-  /* Transfer complete user callback */
-  HAL_SD_DMA_RxErrorCallback(hsd->hdmarx);
-}
-
-/**
-  * @brief  SD DMA transfer complete Tx callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma)
-{
-  SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-  
-  /* DMA transfer is complete */
-  hsd->DmaTransferCplt = 1;
-  
-  /* Wait until SD transfer is complete */
-  while(hsd->SdTransferCplt == 0)
-  {
-  }
-  
-  /* Disable the DMA channel */
-  HAL_DMA_Abort(hdma);
-
-  /* Transfer complete user callback */
-  HAL_SD_DMA_TxCpltCallback(hsd->hdmatx);  
-}
-
-/**
-  * @brief  SD DMA transfer Error Tx callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SD_DMA_TxError(DMA_HandleTypeDef *hdma)
-{
-  SD_HandleTypeDef *hsd = ( SD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  /* Transfer complete user callback */
-  HAL_SD_DMA_TxErrorCallback(hsd->hdmatx);
-}
-
-/**
-  * @brief  Returns the SD current state.
-  * @param  hsd: SD handle
-  * @retval SD card current state
-  */
-static HAL_SD_CardStateTypedef SD_GetState(SD_HandleTypeDef *hsd)
-{
-  uint32_t resp1 = 0;
-  
-  if (SD_SendStatus(hsd, &resp1) != SD_OK)
-  {
-    return SD_CARD_ERROR;
-  }
-  else
-  {
-    return (HAL_SD_CardStateTypedef)((resp1 >> 9) & 0x0F);
-  }
-}
-
-/**
-  * @brief  Initializes all cards or single card as the case may be Card(s) come 
-  *         into standby state.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd)
-{
-  SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; 
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint16_t sd_rca = 1;
-  
-  if(SDMMC_GetPowerState(hsd->Instance) == 0) /* Power off */
-  {
-    errorstate = SD_REQUEST_NOT_APPLICABLE;
-    
-    return errorstate;
-  }
-  
-  if(hsd->CardType != SECURE_DIGITAL_IO_CARD)
-  {
-    /* Send CMD2 ALL_SEND_CID */
-    sdmmc_cmdinitstructure.Argument         = 0;
-    sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_ALL_SEND_CID;
-    sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_LONG;
-    sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
-    sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
-    SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp2Error(hsd);
-    
-    if(errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-    
-    /* Get Card identification number data */
-    hsd->CID[0] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
-    hsd->CID[1] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);
-    hsd->CID[2] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);
-    hsd->CID[3] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);
-  }
-  
-  if((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1)    || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
-     (hsd->CardType == SECURE_DIGITAL_IO_COMBO_CARD) || (hsd->CardType == HIGH_CAPACITY_SD_CARD))
-  {
-    /* Send CMD3 SET_REL_ADDR with argument 0 */
-    /* SD Card publishes its RCA. */
-    sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SET_REL_ADDR;
-    sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
-    SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp6Error(hsd, SD_CMD_SET_REL_ADDR, &sd_rca);
-    
-    if(errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-  }
-  
-  if (hsd->CardType != SECURE_DIGITAL_IO_CARD)
-  {
-    /* Get the SD card RCA */
-    hsd->RCA = sd_rca;
-    
-    /* Send CMD9 SEND_CSD with argument as card's RCA */
-    sdmmc_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16);
-    sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SEND_CSD;
-    sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_LONG;
-    SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp2Error(hsd);
-    
-    if(errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-    
-    /* Get Card Specific Data */
-    hsd->CSD[0] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
-    hsd->CSD[1] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);
-    hsd->CSD[2] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);
-    hsd->CSD[3] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);
-  }
-  
-  /* All cards are initialized */
-  return errorstate;
-}
-
-/**
-  * @brief  Selects or Deselects the corresponding card.
-  * @param  hsd: SD handle
-  * @param  addr: Address of the card to be selected  
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t addr)
-{
-  SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  
-  /* Send CMD7 SDMMC_SEL_DESEL_CARD */
-  sdmmc_cmdinitstructure.Argument         = (uint32_t)addr;
-  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SEL_DESEL_CARD;
-  sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
-  sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
-  sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SEL_DESEL_CARD);
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Enquires cards about their operating voltage and configures clock
-  *         controls and stores SD information that will be needed in future
-  *         in the SD handle.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd)
-{
-  SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; 
-  __IO HAL_SD_ErrorTypedef errorstate = SD_OK; 
-  uint32_t response = 0, count = 0, validvoltage = 0;
-  uint32_t sdtype = SD_STD_CAPACITY;
-  
-  /* Power ON Sequence -------------------------------------------------------*/
-  /* Disable SDMMC Clock */
-  __HAL_SD_SDMMC_DISABLE(hsd); 
-  
-  /* Set Power State to ON */
-  SDMMC_PowerState_ON(hsd->Instance);
-  
-  /* 1ms: required power up waiting time before starting the SD initialization 
-     sequence */
-  HAL_Delay(1);
-  
-  /* Enable SDMMC Clock */
-  __HAL_SD_SDMMC_ENABLE(hsd);
-  
-  /* CMD0: GO_IDLE_STATE -----------------------------------------------------*/
-  /* No CMD response required */
-  sdmmc_cmdinitstructure.Argument         = 0;
-  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_GO_IDLE_STATE;
-  sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_NO;
-  sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
-  sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdError(hsd);
-  
-  if(errorstate != SD_OK)
-  {
-    /* CMD Response Timeout (wait for CMDSENT flag) */
-    return errorstate;
-  }
-  
-  /* CMD8: SEND_IF_COND ------------------------------------------------------*/
-  /* Send CMD8 to verify SD card interface operating condition */
-  /* Argument: - [31:12]: Reserved (shall be set to '0')
-  - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V)
-  - [7:0]: Check Pattern (recommended 0xAA) */
-  /* CMD Response: R7 */
-  sdmmc_cmdinitstructure.Argument         = SD_CHECK_PATTERN;
-  sdmmc_cmdinitstructure.CmdIndex         = SD_SDMMC_SEND_IF_COND;
-  sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-  
-  /* Check for error conditions */ 
-  errorstate = SD_CmdResp7Error(hsd);
-  
-  if (errorstate == SD_OK)
-  {
-    /* SD Card 2.0 */
-    hsd->CardType = STD_CAPACITY_SD_CARD_V2_0; 
-    sdtype        = SD_HIGH_CAPACITY;
-  }
-  
-  /* Send CMD55 */
-  sdmmc_cmdinitstructure.Argument         = 0;
-  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
-  
-  /* If errorstate is Command Timeout, it is a MMC card */
-  /* If errorstate is SD_OK it is a SD card: SD card 2.0 (voltage range mismatch)
-     or SD card 1.x */
-  if(errorstate == SD_OK)
-  {
-    /* SD CARD */
-    /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
-    while((!validvoltage) && (count < SD_MAX_VOLT_TRIAL))
-    {
-      
-      /* SEND CMD55 APP_CMD with RCA as 0 */
-      sdmmc_cmdinitstructure.Argument         = 0;
-      sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
-      sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
-      sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
-      sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
-      SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-      
-      /* Check for error conditions */
-      errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
-      
-      if(errorstate != SD_OK)
-      {
-        return errorstate;
-      }
-      
-      /* Send CMD41 */
-      sdmmc_cmdinitstructure.Argument         = SD_VOLTAGE_WINDOW_SD | sdtype;
-      sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SD_APP_OP_COND;
-      sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
-      sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
-      sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
-      SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-      
-      /* Check for error conditions */
-      errorstate = SD_CmdResp3Error(hsd);
-      
-      if(errorstate != SD_OK)
-      {
-        return errorstate;
-      }
-      
-      /* Get command response */
-      response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
-      
-      /* Get operating voltage*/
-      validvoltage = (((response >> 31) == 1) ? 1 : 0);
-      
-      count++;
-    }
-    
-    if(count >= SD_MAX_VOLT_TRIAL)
-    {
-      errorstate = SD_INVALID_VOLTRANGE;
-      
-      return errorstate;
-    }
-    
-    if((response & SD_HIGH_CAPACITY) == SD_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */
-    {
-      hsd->CardType = HIGH_CAPACITY_SD_CARD;
-    }
-    
-  } /* else MMC Card */
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Turns the SDMMC output signals off.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_PowerOFF(SD_HandleTypeDef *hsd)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  
-  /* Set Power State to OFF */
-  SDMMC_PowerState_OFF(hsd->Instance);
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Returns the current card's status.
-  * @param  hsd: SD handle
-  * @param  pCardStatus: pointer to the buffer that will contain the SD card 
-  *         status (Card Status register)  
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
-{
-  SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  
-  if(pCardStatus == NULL)
-  {
-    errorstate = SD_INVALID_PARAMETER;
-    
-    return errorstate;
-  }
-  
-  /* Send Status command */
-  sdmmc_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16);
-  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SEND_STATUS;
-  sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
-  sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
-  sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SEND_STATUS);
-  
-  if(errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Get SD card status */
-  *pCardStatus = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Checks for error conditions for CMD0.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t timeout, tmp;
-  
-  timeout = SDMMC_CMD0TIMEOUT;
-  
-  tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CMDSENT);
-    
-  while((timeout > 0) && (!tmp))
-  {
-    tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CMDSENT);
-    timeout--;
-  }
-  
-  if(timeout == 0)
-  {
-    errorstate = SD_CMD_RSP_TIMEOUT;
-    return errorstate;
-  }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Checks for error conditions for R7 response.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_ERROR;
-  uint32_t timeout = SDMMC_CMD0TIMEOUT, tmp;
-  
-  tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT); 
-  
-  while((!tmp) && (timeout > 0))
-  {
-    tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT);
-    timeout--;
-  }
-  
-  tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT); 
-  
-  if((timeout == 0) || tmp)
-  {
-    /* Card is not V2.0 compliant or card does not support the set voltage range */
-    errorstate = SD_CMD_RSP_TIMEOUT;
-    
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);
-    
-    return errorstate;
-  }
-  
-  if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CMDREND))
-  {
-    /* Card is SD V2.0 compliant */
-    errorstate = SD_OK;
-    
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CMDREND);
-    
-    return errorstate;
-  }
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Checks for error conditions for R1 response.
-  * @param  hsd: SD handle
-  * @param  SD_CMD: The sent command index  
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t response_r1;
-  
-  while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT))
-  {
-  }
-  
-  if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT))
-  {
-    errorstate = SD_CMD_RSP_TIMEOUT;
-    
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);
-    
-    return errorstate;
-  }
-  else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL))
-  {
-    errorstate = SD_CMD_CRC_FAIL;
-    
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CCRCFAIL);
-    
-    return errorstate;
-  }
-  
-  /* Check response received is of desired command */
-  if(SDMMC_GetCommandResponse(hsd->Instance) != SD_CMD)
-  {
-    errorstate = SD_ILLEGAL_CMD;
-    
-    return errorstate;
-  }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
-  
-  /* We have received response, retrieve it for analysis  */
-  response_r1 = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
-  
-  if((response_r1 & SD_OCR_ERRORBITS) == SD_ALLZERO)
-  {
-    return errorstate;
-  }
-  
-  if((response_r1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE)
-  {
-    return(SD_ADDR_OUT_OF_RANGE);
-  }
-  
-  if((response_r1 & SD_OCR_ADDR_MISALIGNED) == SD_OCR_ADDR_MISALIGNED)
-  {
-    return(SD_ADDR_MISALIGNED);
-  }
-  
-  if((response_r1 & SD_OCR_BLOCK_LEN_ERR) == SD_OCR_BLOCK_LEN_ERR)
-  {
-    return(SD_BLOCK_LEN_ERR);
-  }
-  
-  if((response_r1 & SD_OCR_ERASE_SEQ_ERR) == SD_OCR_ERASE_SEQ_ERR)
-  {
-    return(SD_ERASE_SEQ_ERR);
-  }
-  
-  if((response_r1 & SD_OCR_BAD_ERASE_PARAM) == SD_OCR_BAD_ERASE_PARAM)
-  {
-    return(SD_BAD_ERASE_PARAM);
-  }
-  
-  if((response_r1 & SD_OCR_WRITE_PROT_VIOLATION) == SD_OCR_WRITE_PROT_VIOLATION)
-  {
-    return(SD_WRITE_PROT_VIOLATION);
-  }
-  
-  if((response_r1 & SD_OCR_LOCK_UNLOCK_FAILED) == SD_OCR_LOCK_UNLOCK_FAILED)
-  {
-    return(SD_LOCK_UNLOCK_FAILED);
-  }
-  
-  if((response_r1 & SD_OCR_COM_CRC_FAILED) == SD_OCR_COM_CRC_FAILED)
-  {
-    return(SD_COM_CRC_FAILED);
-  }
-  
-  if((response_r1 & SD_OCR_ILLEGAL_CMD) == SD_OCR_ILLEGAL_CMD)
-  {
-    return(SD_ILLEGAL_CMD);
-  }
-  
-  if((response_r1 & SD_OCR_CARD_ECC_FAILED) == SD_OCR_CARD_ECC_FAILED)
-  {
-    return(SD_CARD_ECC_FAILED);
-  }
-  
-  if((response_r1 & SD_OCR_CC_ERROR) == SD_OCR_CC_ERROR)
-  {
-    return(SD_CC_ERROR);
-  }
-  
-  if((response_r1 & SD_OCR_GENERAL_UNKNOWN_ERROR) == SD_OCR_GENERAL_UNKNOWN_ERROR)
-  {
-    return(SD_GENERAL_UNKNOWN_ERROR);
-  }
-  
-  if((response_r1 & SD_OCR_STREAM_READ_UNDERRUN) == SD_OCR_STREAM_READ_UNDERRUN)
-  {
-    return(SD_STREAM_READ_UNDERRUN);
-  }
-  
-  if((response_r1 & SD_OCR_STREAM_WRITE_OVERRUN) == SD_OCR_STREAM_WRITE_OVERRUN)
-  {
-    return(SD_STREAM_WRITE_OVERRUN);
-  }
-  
-  if((response_r1 & SD_OCR_CID_CSD_OVERWRITE) == SD_OCR_CID_CSD_OVERWRITE)
-  {
-    return(SD_CID_CSD_OVERWRITE);
-  }
-  
-  if((response_r1 & SD_OCR_WP_ERASE_SKIP) == SD_OCR_WP_ERASE_SKIP)
-  {
-    return(SD_WP_ERASE_SKIP);
-  }
-  
-  if((response_r1 & SD_OCR_CARD_ECC_DISABLED) == SD_OCR_CARD_ECC_DISABLED)
-  {
-    return(SD_CARD_ECC_DISABLED);
-  }
-  
-  if((response_r1 & SD_OCR_ERASE_RESET) == SD_OCR_ERASE_RESET)
-  {
-    return(SD_ERASE_RESET);
-  }
-  
-  if((response_r1 & SD_OCR_AKE_SEQ_ERROR) == SD_OCR_AKE_SEQ_ERROR)
-  {
-    return(SD_AKE_SEQ_ERROR);
-  }
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Checks for error conditions for R3 (OCR) response.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  
-  while (!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT))
-  {
-  }
-  
-  if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT))
-  {
-    errorstate = SD_CMD_RSP_TIMEOUT;
-    
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);
-    
-    return errorstate;
-  }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Checks for error conditions for R2 (CID or CSD) response.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  
-  while (!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT))
-  {
-  }
-    
-  if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT))
-  {
-    errorstate = SD_CMD_RSP_TIMEOUT;
-    
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);
-    
-    return errorstate;
-  }
-  else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL))
-  {
-    errorstate = SD_CMD_CRC_FAIL;
-    
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CCRCFAIL);
-    
-    return errorstate;
-  }
-  else
-  {
-    /* No error flag set */
-  }  
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Checks for error conditions for R6 (RCA) response.
-  * @param  hsd: SD handle
-  * @param  SD_CMD: The sent command index
-  * @param  pRCA: Pointer to the variable that will contain the SD card relative 
-  *         address RCA   
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t response_r1;
-  
-  while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT))
-  {
-  }
-  
-  if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT))
-  {
-    errorstate = SD_CMD_RSP_TIMEOUT;
-    
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);
-    
-    return errorstate;
-  }
-  else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL))
-  {
-    errorstate = SD_CMD_CRC_FAIL;
-    
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CCRCFAIL);
-    
-    return errorstate;
-  }
-  else
-  {
-    /* No error flag set */
-  }  
-  
-  /* Check response received is of desired command */
-  if(SDMMC_GetCommandResponse(hsd->Instance) != SD_CMD)
-  {
-    errorstate = SD_ILLEGAL_CMD;
-    
-    return errorstate;
-  }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
-  
-  /* We have received response, retrieve it.  */
-  response_r1 = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
-  
-  if((response_r1 & (SD_R6_GENERAL_UNKNOWN_ERROR | SD_R6_ILLEGAL_CMD | SD_R6_COM_CRC_FAILED)) == SD_ALLZERO)
-  {
-    *pRCA = (uint16_t) (response_r1 >> 16);
-    
-    return errorstate;
-  }
-  
-  if((response_r1 & SD_R6_GENERAL_UNKNOWN_ERROR) == SD_R6_GENERAL_UNKNOWN_ERROR)
-  {
-    return(SD_GENERAL_UNKNOWN_ERROR);
-  }
-  
-  if((response_r1 & SD_R6_ILLEGAL_CMD) == SD_R6_ILLEGAL_CMD)
-  {
-    return(SD_ILLEGAL_CMD);
-  }
-  
-  if((response_r1 & SD_R6_COM_CRC_FAILED) == SD_R6_COM_CRC_FAILED)
-  {
-    return(SD_COM_CRC_FAILED);
-  }
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Enables the SDMMC wide bus mode.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_WideBus_Enable(SD_HandleTypeDef *hsd)
-{
-  SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  
-  uint32_t scr[2] = {0, 0};
-  
-  if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
-  {
-    errorstate = SD_LOCK_UNLOCK_FAILED;
-    
-    return errorstate;
-  }
-  
-  /* Get SCR Register */
-  errorstate = SD_FindSCR(hsd, scr);
-  
-  if(errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* If requested card supports wide bus operation */
-  if((scr[1] & SD_WIDE_BUS_SUPPORT) != SD_ALLZERO)
-  {
-    /* Send CMD55 APP_CMD with argument as card's RCA.*/
-    sdmmc_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16);
-    sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
-    sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
-    sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
-    sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
-    SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
-    
-    if(errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-    
-    /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
-    sdmmc_cmdinitstructure.Argument         = 2;
-    sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_APP_SD_SET_BUSWIDTH;
-    SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH);
-    
-    if(errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-    
-    return errorstate;
-  }
-  else
-  {
-    errorstate = SD_REQUEST_NOT_APPLICABLE;
-    
-    return errorstate;
-  }
-}   
-
-/**
-  * @brief  Disables the SDMMC wide bus mode.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_WideBus_Disable(SD_HandleTypeDef *hsd)
-{
-  SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  
-  uint32_t scr[2] = {0, 0};
-  
-  if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
-  {
-    errorstate = SD_LOCK_UNLOCK_FAILED;
-    
-    return errorstate;
-  }
-  
-  /* Get SCR Register */
-  errorstate = SD_FindSCR(hsd, scr);
-  
-  if(errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* If requested card supports 1 bit mode operation */
-  if((scr[1] & SD_SINGLE_BUS_SUPPORT) != SD_ALLZERO)
-  {
-    /* Send CMD55 APP_CMD with argument as card's RCA */
-    sdmmc_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16);
-    sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
-    sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
-    sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
-    sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
-    SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
-    
-    if(errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-    
-    /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */
-    sdmmc_cmdinitstructure.Argument         = 0;
-    sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_APP_SD_SET_BUSWIDTH;
-    SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH);
-    
-    if(errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-    
-    return errorstate;
-  }
-  else
-  {
-    errorstate = SD_REQUEST_NOT_APPLICABLE;
-    
-    return errorstate;
-  }
-}
-  
-  
-/**
-  * @brief  Finds the SD card SCR register value.
-  * @param  hsd: SD handle
-  * @param  pSCR: pointer to the buffer that will contain the SCR value  
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
-{
-  SDMMC_CmdInitTypeDef  sdmmc_cmdinitstructure;
-  SDMMC_DataInitTypeDef sdmmc_datainitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t index = 0;
-  uint32_t tempscr[2] = {0, 0};
-  
-  /* Set Block Size To 8 Bytes */
-  /* Send CMD55 APP_CMD with argument as card's RCA */
-  sdmmc_cmdinitstructure.Argument         = (uint32_t)8;
-  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
-  sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
-  sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
-  sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
-  
-  if(errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Send CMD55 APP_CMD with argument as card's RCA */
-  sdmmc_cmdinitstructure.Argument         = (uint32_t)((hsd->RCA) << 16);
-  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
-  
-  if(errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  sdmmc_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
-  sdmmc_datainitstructure.DataLength    = 8;
-  sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_8B;
-  sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
-  sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
-  sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;
-  SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);
-  
-  /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */
-  sdmmc_cmdinitstructure.Argument         = 0;
-  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SD_APP_SEND_SCR;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_SEND_SCR);
-  
-  if(errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))
-  {
-    if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL))
-    {
-      *(tempscr + index) = SDMMC_ReadFIFO(hsd->Instance);
-      index++;
-    }
-  }
-  
-  if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
-  {
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
-    
-    errorstate = SD_DATA_TIMEOUT;
-    
-    return errorstate;
-  }
-  else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
-  {
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
-    
-    errorstate = SD_DATA_CRC_FAIL;
-    
-    return errorstate;
-  }
-  else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
-  {
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
-    
-    errorstate = SD_RX_OVERRUN;
-    
-    return errorstate;
-  }
-  else
-  {
-    /* No error flag set */
-  }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
-  
-  *(pSCR + 1) = ((tempscr[0] & SD_0TO7BITS) << 24)  | ((tempscr[0] & SD_8TO15BITS) << 8) |\
-    ((tempscr[0] & SD_16TO23BITS) >> 8) | ((tempscr[0] & SD_24TO31BITS) >> 24);
-  
-  *(pSCR) = ((tempscr[1] & SD_0TO7BITS) << 24)  | ((tempscr[1] & SD_8TO15BITS) << 8) |\
-    ((tempscr[1] & SD_16TO23BITS) >> 8) | ((tempscr[1] & SD_24TO31BITS) >> 24);
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Checks if the SD card is in programming state.
-  * @param  hsd: SD handle
-  * @param  pStatus: pointer to the variable that will contain the SD card state  
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *pStatus)
-{
-  SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  __IO uint32_t responseR1 = 0;
-  
-  sdmmc_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16);
-  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SEND_STATUS;
-  sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
-  sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
-  sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
-  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
-  
-  while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT))
-  {
-  }
-  
-  if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT))
-  {
-    errorstate = SD_CMD_RSP_TIMEOUT;
-    
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);
-    
-    return errorstate;
-  }
-  else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL))
-  {
-    errorstate = SD_CMD_CRC_FAIL;
-    
-    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CCRCFAIL);
-    
-    return errorstate;
-  }
-  else
-  {
-    /* No error flag set */
-  }
-  
-  /* Check response received is of desired command */
-  if((uint32_t)SDMMC_GetCommandResponse(hsd->Instance) != SD_CMD_SEND_STATUS)
-  {
-    errorstate = SD_ILLEGAL_CMD;
-    
-    return errorstate;
-  }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
-  
-  
-  /* We have received response, retrieve it for analysis */
-  responseR1 = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
-  
-  /* Find out card status */
-  *pStatus = (uint8_t)((responseR1 >> 9) & 0x0000000F);
-  
-  if((responseR1 & SD_OCR_ERRORBITS) == SD_ALLZERO)
-  {
-    return errorstate;
-  }
-  
-  if((responseR1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE)
-  {
-    return(SD_ADDR_OUT_OF_RANGE);
-  }
-  
-  if((responseR1 & SD_OCR_ADDR_MISALIGNED) == SD_OCR_ADDR_MISALIGNED)
-  {
-    return(SD_ADDR_MISALIGNED);
-  }
-  
-  if((responseR1 & SD_OCR_BLOCK_LEN_ERR) == SD_OCR_BLOCK_LEN_ERR)
-  {
-    return(SD_BLOCK_LEN_ERR);
-  }
-  
-  if((responseR1 & SD_OCR_ERASE_SEQ_ERR) == SD_OCR_ERASE_SEQ_ERR)
-  {
-    return(SD_ERASE_SEQ_ERR);
-  }
-  
-  if((responseR1 & SD_OCR_BAD_ERASE_PARAM) == SD_OCR_BAD_ERASE_PARAM)
-  {
-    return(SD_BAD_ERASE_PARAM);
-  }
-  
-  if((responseR1 & SD_OCR_WRITE_PROT_VIOLATION) == SD_OCR_WRITE_PROT_VIOLATION)
-  {
-    return(SD_WRITE_PROT_VIOLATION);
-  }
-  
-  if((responseR1 & SD_OCR_LOCK_UNLOCK_FAILED) == SD_OCR_LOCK_UNLOCK_FAILED)
-  {
-    return(SD_LOCK_UNLOCK_FAILED);
-  }
-  
-  if((responseR1 & SD_OCR_COM_CRC_FAILED) == SD_OCR_COM_CRC_FAILED)
-  {
-    return(SD_COM_CRC_FAILED);
-  }
-  
-  if((responseR1 & SD_OCR_ILLEGAL_CMD) == SD_OCR_ILLEGAL_CMD)
-  {
-    return(SD_ILLEGAL_CMD);
-  }
-  
-  if((responseR1 & SD_OCR_CARD_ECC_FAILED) == SD_OCR_CARD_ECC_FAILED)
-  {
-    return(SD_CARD_ECC_FAILED);
-  }
-  
-  if((responseR1 & SD_OCR_CC_ERROR) == SD_OCR_CC_ERROR)
-  {
-    return(SD_CC_ERROR);
-  }
-  
-  if((responseR1 & SD_OCR_GENERAL_UNKNOWN_ERROR) == SD_OCR_GENERAL_UNKNOWN_ERROR)
-  {
-    return(SD_GENERAL_UNKNOWN_ERROR);
-  }
-  
-  if((responseR1 & SD_OCR_STREAM_READ_UNDERRUN) == SD_OCR_STREAM_READ_UNDERRUN)
-  {
-    return(SD_STREAM_READ_UNDERRUN);
-  }
-  
-  if((responseR1 & SD_OCR_STREAM_WRITE_OVERRUN) == SD_OCR_STREAM_WRITE_OVERRUN)
-  {
-    return(SD_STREAM_WRITE_OVERRUN);
-  }
-  
-  if((responseR1 & SD_OCR_CID_CSD_OVERWRITE) == SD_OCR_CID_CSD_OVERWRITE)
-  {
-    return(SD_CID_CSD_OVERWRITE);
-  }
-  
-  if((responseR1 & SD_OCR_WP_ERASE_SKIP) == SD_OCR_WP_ERASE_SKIP)
-  {
-    return(SD_WP_ERASE_SKIP);
-  }
-  
-  if((responseR1 & SD_OCR_CARD_ECC_DISABLED) == SD_OCR_CARD_ECC_DISABLED)
-  {
-    return(SD_CARD_ECC_DISABLED);
-  }
-  
-  if((responseR1 & SD_OCR_ERASE_RESET) == SD_OCR_ERASE_RESET)
-  {
-    return(SD_ERASE_RESET);
-  }
-  
-  if((responseR1 & SD_OCR_AKE_SEQ_ERROR) == SD_OCR_AKE_SEQ_ERROR)
-  {
-    return(SD_AKE_SEQ_ERROR);
-  }
-  
-  return errorstate;
-}   
-
-/**
-  * @}
-  */
-
-#endif /* HAL_SD_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/src/stm32l4xx_hal_spi.c b/stmhal/hal/l4/src/stm32l4xx_hal_spi.c
deleted file mode 100644
index 828b7e0ee7..0000000000
--- a/stmhal/hal/l4/src/stm32l4xx_hal_spi.c
+++ /dev/null
@@ -1,2769 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_spi.c
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   SPI HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Serial Peripheral Interface (SPI) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions
-  *           + Peripheral State functions
-  *
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-    [..]
-      The SPI HAL driver can be used as follows:
-
-      (#) Declare a SPI_HandleTypeDef handle structure, for example:
-          SPI_HandleTypeDef  hspi;
-
-      (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
-          (##) Enable the SPIx interface clock
-          (##) SPI pins configuration
-              (+++) Enable the clock for the SPI GPIOs
-              (+++) Configure these SPI pins as alternate function push-pull
-          (##) NVIC configuration if you need to use interrupt process
-              (+++) Configure the SPIx interrupt priority
-              (+++) Enable the NVIC SPI IRQ handle
-          (##) DMA Configuration if you need to use DMA process
-              (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
-              (+++) Enable the DMAx clock
-              (+++) Configure the DMA handle parameters
-              (+++) Configure the DMA Tx or Rx channel
-              (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
-              (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel
-
-      (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
-          management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
-
-      (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
-          (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
-              by calling the customized HAL_SPI_MspInit() API.
-     [..]
-       Circular mode restriction:
-      (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
-          (##) Master 2Lines RxOnly
-          (##) Master 1Line Rx
-      (#) The CRC feature is not managed when the DMA circular mode is enabled
-      (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
-          the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup SPI SPI
-  * @brief SPI HAL module driver
-  * @{
-  */
-#ifdef HAL_SPI_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup SPI_Private_Constants SPI Private Constants
-  * @{
-  */
-#define SPI_DEFAULT_TIMEOUT 50
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup SPI_Private_Functions SPI Private Functions
-  * @{
-  */
-static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAError(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout);
-static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout);
-static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
-static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
-static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
-static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
-static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
-static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
-static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
-/**
-  * @}
-  */
-
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup SPI_Exported_Functions SPI Exported Functions
-  * @{
-  */
-
-/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @brief    Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This subsection provides a set of functions allowing to initialize and
-          de-initialize the SPIx peripheral:
-
-      (+) User must implement HAL_SPI_MspInit() function in which he configures
-          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
-
-      (+) Call the function HAL_SPI_Init() to configure the selected device with
-          the selected configuration:
-        (++) Mode
-        (++) Direction
-        (++) Data Size
-        (++) Clock Polarity and Phase
-        (++) NSS Management
-        (++) BaudRate Prescaler
-        (++) FirstBit
-        (++) TIMode
-        (++) CRC Calculation
-        (++) CRC Polynomial if CRC enabled
-        (++) CRC Length, used only with Data8 and Data16
-        (++) FIFO reception threshold
-
-      (+) Call the function HAL_SPI_DeInit() to restore the default configuration
-          of the selected SPIx peripheral.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initialize the SPI according to the specified parameters
-  *         in the SPI_InitTypeDef and initialize the associated handle.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
-{
-  uint32_t frxth;
-
-  /* Check the SPI handle allocation */
-  if(hspi == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
-  assert_param(IS_SPI_MODE(hspi->Init.Mode));
-  assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
-  assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
-  assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
-  assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
-  assert_param(IS_SPI_NSS(hspi->Init.NSS));
-  assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
-  assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
-  assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
-  assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
-  assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
-  assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
-  assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
-
-  if(hspi->State == HAL_SPI_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hspi->Lock = HAL_UNLOCKED;
-
-    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
-    HAL_SPI_MspInit(hspi);
-  }
-
-  hspi->State = HAL_SPI_STATE_BUSY;
-
-  /* Disable the selected SPI peripheral */
-  __HAL_SPI_DISABLE(hspi);
-
-  /* Align by default the rs fifo threshold on the data size */
-  if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
-  {
-    frxth = SPI_RXFIFO_THRESHOLD_HF;
-  }
-  else
-  {
-    frxth = SPI_RXFIFO_THRESHOLD_QF;
-  }
-
-  /* CRC calculation is valid only for 16Bit and 8 Bit */
-  if(( hspi->Init.DataSize != SPI_DATASIZE_16BIT ) && ( hspi->Init.DataSize != SPI_DATASIZE_8BIT ))
-  {
-    /* CRC must be disabled */
-    hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
-  }
-
-  /* Align the CRC Length on the data size */
-  if( hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
-  {
-    /* CRC Length aligned on the data size : value set by default */
-    if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
-    {
-      hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
-    }
-    else
-    {
-      hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
-    }
-  }
-
-  /*---------------------------- SPIx CR1 & CR2 Configuration ------------------------*/
-  /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
-  Communication speed, First bit, CRC calculation state, CRC Length */
-  hspi->Instance->CR1 = (hspi->Init.Mode | hspi->Init.Direction |
-                         hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
-                         hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit  | hspi->Init.CRCCalculation);
-
-  if( hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
-  {
-    hspi->Instance->CR1|= SPI_CR1_CRCL;
-  }
-
-  /* Configure : NSS management */
-  /* Configure : Rx Fifo Threshold */
-  hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode | hspi->Init.NSSPMode |
-                         hspi->Init.DataSize ) | frxth;
-
-  /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
-  /* Configure : CRC Polynomial */
-  hspi->Instance->CRCPR = hspi->Init.CRCPolynomial;
-
-  hspi->ErrorCode = HAL_SPI_ERROR_NONE;
-  hspi->State= HAL_SPI_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitialize the SPI peripheral.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
-{
-  /* Check the SPI handle allocation */
-  if(hspi == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
-  hspi->State = HAL_SPI_STATE_BUSY;
-
-  /* Disable the SPI Peripheral Clock */
-  __HAL_SPI_DISABLE(hspi);
-
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
-  HAL_SPI_MspDeInit(hspi);
-
-  hspi->ErrorCode = HAL_SPI_ERROR_NONE;
-  hspi->State = HAL_SPI_STATE_RESET;
-
-  __HAL_UNLOCK(hspi);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Initialize the SPI MSP.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_MspInit should be implemented in the user file
-   */
-}
-
-/**
-  * @brief DeInitialize the SPI MSP.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_MspDeInit should be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
- *  @brief   Data transfers functions
- *
-@verbatim
-  ==============================================================================
-                      ##### IO operation functions #####
- ===============================================================================
- [..]
-    This subsection provides a set of functions allowing to manage the SPI
-    data transfers.
-
-    [..] The SPI supports master and slave mode :
-
-    (#) There are two modes of transfer:
-       (++) Blocking mode: The communication is performed in polling mode.
-            The HAL status of all data processing is returned by the same function
-            after finishing transfer.
-       (++) No-Blocking mode: The communication is performed using Interrupts
-           or DMA, These APIs return the HAL status.
-           The end of the data processing will be indicated through the
-           dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
-           using DMA mode.
-           The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
-           will be executed respectively at the end of the transmit or Receive process
-           The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
-
-    (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
-        exist for 1Line (simplex) and 2Lines (full duplex) modes.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Transmit an amount of data in blocking mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pData: pointer to data buffer
-  * @param  Size: amount of data to be sent
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint32_t tickstart = HAL_GetTick();
-  HAL_StatusTypeDef errorcode = HAL_OK;
-
-  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
-
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  if(hspi->State != HAL_SPI_STATE_READY)
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  if((pData == NULL ) || (Size == 0))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  /* Set the transaction information */
-  hspi->State       = HAL_SPI_STATE_BUSY_TX;
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pTxBuffPtr  = pData;
-  hspi->TxXferSize  = Size;
-  hspi->TxXferCount = Size;
-  hspi->pRxBuffPtr  = (uint8_t *)NULL;
-  hspi->RxXferSize  = 0;
-  hspi->RxXferCount = 0;
-
-  /* Configure communication direction : 1Line */
-  if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
-  {
-    SPI_1LINE_TX(hspi);
-  }
-
-  /* Reset CRC Calculation */
-  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-  }
-
-  /* Check if the SPI is already enabled */
-  if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-
-  /* Transmit data in 16 Bit mode */
-  if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
-  {
-    /* Transmit data in 16 Bit mode */
-    while (hspi->TxXferCount > 0)
-    {
-      /* Wait until TXE flag is set to send data */
-      if((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)
-      {
-          hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
-          hspi->pTxBuffPtr += sizeof(uint16_t);
-          hspi->TxXferCount--;
-      }
-      else
-      {
-        /* Timeout management */
-        if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout)))
-        {
-          errorcode = HAL_TIMEOUT;
-          goto error;
-        }
-      }
-    }
-  }
-  /* Transmit data in 8 Bit mode */
-  else
-  {
-    while (hspi->TxXferCount > 0)
-    {
-      /* Wait until TXE flag is set to send data */
-      if((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)
-      {
-        if(hspi->TxXferCount > 1)
-        {
-          /* write on the data register in packing mode */
-          hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
-          hspi->pTxBuffPtr += sizeof(uint16_t);
-          hspi->TxXferCount -= 2;
-        }
-        else
-        {
-          *((__IO uint8_t*)&hspi->Instance->DR) = (*hspi->pTxBuffPtr++);
-          hspi->TxXferCount--;
-        }
-      }
-      else
-      {
-        /* Timeout management */
-        if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout)))
-        {
-          errorcode = HAL_TIMEOUT;
-          goto error;
-        }
-      }
-    }
-  }
-
-  /* Enable CRC Transmission */
-  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-     hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
-  }
-
-  /* Check the end of the transaction */
-  if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
-  {
-    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
-  }
-  
-  /* Clear overrun flag in 2 Lines communication mode because received is not read */
-  if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
-  {
-    __HAL_SPI_CLEAR_OVRFLAG(hspi);
-  }
-
-  if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
-  {
-    errorcode = HAL_ERROR;
-  }
-
-error:
-  hspi->State = HAL_SPI_STATE_READY;
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Receive an amount of data in blocking mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pData: pointer to data buffer
-  * @param  Size: amount of data to be received
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  __IO uint16_t tmpreg;
-  uint32_t tickstart = HAL_GetTick();
-  HAL_StatusTypeDef errorcode = HAL_OK;
-
-  if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
-  {
-    /* the receive process is not supported in 2Lines direction master mode */
-    /* in this case we call the TransmitReceive process                     */
-    /* Process Locked */
-    return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout);
-  }
-
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  if(hspi->State != HAL_SPI_STATE_READY)
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  if((pData == NULL ) || (Size == 0))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  hspi->State       = HAL_SPI_STATE_BUSY_RX;
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pRxBuffPtr  = pData;
-  hspi->RxXferSize  = Size;
-  hspi->RxXferCount = Size;
-  hspi->pTxBuffPtr  = (uint8_t *)NULL;
-  hspi->TxXferSize  = 0;
-  hspi->TxXferCount = 0;
-
-  /* Reset CRC Calculation */
-  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-    /* this is done to handle the CRCNEXT before the latest data */
-    hspi->RxXferCount--;
-  }
-
-  /* Set the Rx Fido threshold */
-  if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
-  {
-    /* set fiforxthresold according the reception data length: 16bit */
-    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-  }
-  else
-  {
-    /* set fiforxthresold according the reception data length: 8bit */
-    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-  }
-
-  /* Configure communication direction 1Line and enabled SPI if needed */
-  if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
-  {
-    SPI_1LINE_RX(hspi);
-  }
-
-  /* Check if the SPI is already enabled */
-  if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-
-  if(hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
-  {
-    /* Transfer loop */
-    while(hspi->RxXferCount > 0)
-    {
-      /* Check the RXNE flag */
-      if((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)
-      {
-        /* read the received data */
-        (*hspi->pRxBuffPtr++)= *(__IO uint8_t *)&hspi->Instance->DR;
-        hspi->RxXferCount--;
-      }
-      else
-      {
-        /* Timeout management */
-        if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout)))
-        {
-          errorcode = HAL_TIMEOUT;
-          goto error;
-        }
-      }
-    }
-  }
-  else
-  {
-    /* Transfer loop */
-    while(hspi->RxXferCount > 0)
-    {
-      /* Check the RXNE flag */
-      if((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)
-      {
-        *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
-        hspi->pRxBuffPtr += sizeof(uint16_t);
-        hspi->RxXferCount--;
-      }
-      else
-      {
-        /* Timeout management */
-        if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout)))
-        {
-          errorcode = HAL_TIMEOUT;
-          goto error;
-        }
-      }
-    }
-  }
-
-  /* Handle the CRC Transmission */
-  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    /* freeze the CRC before the latest data */
-    hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
-
-    /* Read the latest data */
-    if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
-    {
-      /* the latest data has not been received */
-      errorcode = HAL_TIMEOUT;
-      goto error;
-    }
-
-    /* Receive last data in 16 Bit mode */
-    if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
-    {
-      *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
-    }
-    /* Receive last data in 8 Bit mode */
-    else
-    {
-      *hspi->pRxBuffPtr = *(__IO uint8_t *)&hspi->Instance->DR;
-    }
-
-    /* Wait until TXE flag */
-    if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
-    {
-      /* Flag Error*/
-      hspi->ErrorCode = HAL_SPI_ERROR_CRC;
-      errorcode = HAL_TIMEOUT;
-      goto error;
-    }
-
-    if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
-    {
-      tmpreg = hspi->Instance->DR;
-      UNUSED(tmpreg); /* To avoid GCC warning */
-    }
-    else
-    {
-      tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
-      UNUSED(tmpreg); /* To avoid GCC warning */
-
-      if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
-      {
-        if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
-        {
-          /* Error on the CRC reception */
-          hspi->ErrorCode = HAL_SPI_ERROR_CRC;
-          errorcode = HAL_TIMEOUT;
-          goto error;
-        }
-        tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
-        UNUSED(tmpreg); /* To avoid GCC warning */
-      }
-    }
-  }
-  
-  /* Check the end of the transaction */
-  if(SPI_EndRxTransaction(hspi,Timeout) != HAL_OK)
-  {
-    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
-  }
-
-  /* Check if CRC error occurred */
-  if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
-  {
-    hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
-    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-  }
-
-  if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
-  {
-    errorcode = HAL_ERROR;
-  }
-
-error :
-  hspi->State = HAL_SPI_STATE_READY;
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Transmit and Receive an amount of data in blocking mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pTxData: pointer to transmission data buffer
-  * @param  pRxData: pointer to reception data buffer
-  * @param  Size: amount of data to be sent and received
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
-{
-__IO uint16_t tmpreg;
-  uint32_t tickstart = HAL_GetTick();
-  HAL_StatusTypeDef errorcode = HAL_OK;
-
-  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
-
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  if(hspi->State != HAL_SPI_STATE_READY)
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  hspi->State       = HAL_SPI_STATE_BUSY_TX_RX;
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pRxBuffPtr  = pRxData;
-  hspi->RxXferCount = Size;
-  hspi->RxXferSize  = Size;
-  hspi->pTxBuffPtr  = pTxData;
-  hspi->TxXferCount = Size;
-  hspi->TxXferSize  = Size;
-
-  /* Reset CRC Calculation */
-  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-  }
-
-  /* Set the Rx Fido threshold */
-  if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1))
-  {
-    /* set fiforxthreshold according the reception data length: 16bit */
-    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-  }
-  else
-  {
-    /* set fiforxthreshold according the reception data length: 8bit */
-    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-  }
-
-  /* Check if the SPI is already enabled */
-  if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-
-  /* Transmit and Receive data in 16 Bit mode */
-  if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
-  {
-    while ((hspi->TxXferCount > 0 ) || (hspi->RxXferCount > 0))
-    {
-      /* Check TXE flag */
-      if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
-      {
-        hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
-        hspi->pTxBuffPtr += sizeof(uint16_t);
-        hspi->TxXferCount--;
-
-        /* Enable CRC Transmission */
-        if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
-        {
-          hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
-        }
-      }
-
-      /* Check RXNE flag */
-      if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
-      {
-        *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
-        hspi->pRxBuffPtr += sizeof(uint16_t);
-        hspi->RxXferCount--;
-      }
-      if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout))
-      {
-        errorcode = HAL_TIMEOUT;
-        goto error;
-      }
-    }
-  }
-  /* Transmit and Receive data in 8 Bit mode */
-  else
-  {
-    while((hspi->TxXferCount > 0) || (hspi->RxXferCount > 0))
-    {
-      /* check TXE flag */
-      if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
-      {
-        if(hspi->TxXferCount > 1)
-        {
-          hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
-          hspi->pTxBuffPtr += sizeof(uint16_t);
-          hspi->TxXferCount -= 2;
-        }
-        else
-        {
-          *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
-          hspi->TxXferCount--;
-        }
-
-        /* Enable CRC Transmission */
-        if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
-        {
-          hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
-        }
-      }
-
-      /* Wait until RXNE flag is reset */
-      if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
-      {
-        if(hspi->RxXferCount > 1)
-        {
-          *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
-          hspi->pRxBuffPtr += sizeof(uint16_t);
-          hspi->RxXferCount -= 2;
-          if(hspi->RxXferCount <= 1)
-          {
-            /* set fiforxthresold before to switch on 8 bit data size */
-            SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-          }
-        }
-        else
-        {
-          (*hspi->pRxBuffPtr++) =  *(__IO uint8_t *)&hspi->Instance->DR;
-          hspi->RxXferCount--;
-        }
-      }
-      if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout))
-      {
-        errorcode = HAL_TIMEOUT;
-        goto error;
-      }
-    }
-  }
-
-  /* Read CRC from DR to close CRC calculation process */
-  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    /* Wait until TXE flag */
-    if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
-    {
-      /* Error on the CRC reception */
-      hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
-      errorcode = HAL_TIMEOUT;
-      goto error;
-    }
-
-    if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
-    {
-      tmpreg = hspi->Instance->DR;
-      UNUSED(tmpreg); /* To avoid GCC warning */
-    }
-    else
-    {
-      tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
-      UNUSED(tmpreg); /* To avoid GCC warning */
-
-      if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
-      {
-        if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
-        {
-          /* Error on the CRC reception */
-          hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
-          errorcode = HAL_TIMEOUT;
-          goto error;
-        }
-        tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
-        UNUSED(tmpreg); /* To avoid GCC warning */
-      }
-    }
-  }
-
-  /* Check if CRC error occurred */
-  if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
-  {
-    hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
-    /* Clear CRC Flag */
-    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-
-    errorcode = HAL_ERROR;
-  }
-
-  /* Check the end of the transaction */
-  if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
-  {
-    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
-  }
-
-  if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
-  {
-    errorcode = HAL_ERROR;
-  }
-
-error :
-  hspi->State = HAL_SPI_STATE_READY;
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Transmit an amount of data in non-blocking mode with Interrupt.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pData: pointer to data buffer
-  * @param  Size: amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
-{
-  HAL_StatusTypeDef errorcode = HAL_OK;
-  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
-
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  if((pData == NULL) || (Size == 0))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  if(hspi->State != HAL_SPI_STATE_READY)
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  /* prepare the transfer */
-  hspi->State       = HAL_SPI_STATE_BUSY_TX;
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pTxBuffPtr  = pData;
-  hspi->TxXferSize  = Size;
-  hspi->TxXferCount = Size;
-  hspi->pRxBuffPtr  = (uint8_t *)NULL;
-  hspi->RxXferSize  = 0;
-  hspi->RxXferCount = 0;
-  hspi->RxISR = NULL;
-
-  /* Set the function for IT treatment */
-  if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
-  {
-    hspi->TxISR = SPI_TxISR_16BIT;
-  }
-  else
-  {
-    hspi->TxISR = SPI_TxISR_8BIT;
-  }
-
-  /* Configure communication direction : 1Line */
-  if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
-  {
-    SPI_1LINE_TX(hspi);
-  }
-
-  /* Reset CRC Calculation */
-  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-  }
-
-  /* Enable TXE and ERR interrupt */
-  __HAL_SPI_ENABLE_IT(hspi,(SPI_IT_TXE));
-
-
-  /* Check if the SPI is already enabled */
-  if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-
-error :
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Receive an amount of data in non-blocking mode with Interrupt.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pData: pointer to data buffer
-  * @param  Size: amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
-{
-  HAL_StatusTypeDef errorcode = HAL_OK;
-
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  if(hspi->State != HAL_SPI_STATE_READY)
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-  if((pData == NULL) || (Size == 0))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  /* Configure communication */
-  hspi->State       = HAL_SPI_STATE_BUSY_RX;
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pRxBuffPtr  = pData;
-  hspi->RxXferSize  = Size;
-  hspi->RxXferCount = Size;
-  hspi->pTxBuffPtr  = (uint8_t *)NULL;
-  hspi->TxXferSize  = 0;
-  hspi->TxXferCount = 0;
-
-  if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
-  {
-    /* Process Unlocked */
-    __HAL_UNLOCK(hspi);
-    /* the receive process is not supported in 2Lines direction master mode */
-    /* in this we call the TransmitReceive process          */
-    return HAL_SPI_TransmitReceive_IT(hspi,pData,pData,Size);
-  }
-
-  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    hspi->CRCSize = 1;
-    if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
-    {
-      hspi->CRCSize = 2;
-    }
-  }
-  else
-  {
-    hspi->CRCSize = 0;
-  }
-
-  hspi->TxISR = NULL;
-  /* check the data size to adapt Rx threshold and the set the function for IT treatment */
-  if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
-  {
-    /* set fiforxthresold according the reception data length: 16 bit */
-    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-    hspi->RxISR = SPI_RxISR_16BIT;
-  }
-  else
-  {
-    /* set fiforxthresold according the reception data length: 8 bit */
-    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-    hspi->RxISR = SPI_RxISR_8BIT;
-  }
-
-  /* Configure communication direction : 1Line */
-  if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
-  {
-    SPI_1LINE_RX(hspi);
-  }
-
-  /* Reset CRC Calculation */
-  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-  }
-
-  /* Enable TXE and ERR interrupt */
-  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
-  /* Check if the SPI is already enabled */
-  if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-
-error :
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Transmit and Receive an amount of data in non-blocking mode with Interrupt.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pTxData: pointer to transmission data buffer
-  * @param  pRxData: pointer to reception data buffer
-  * @param  Size: amount of data to be sent and received
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
-{
-  HAL_StatusTypeDef errorcode = HAL_OK;
-  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
-
-  /* Process locked */
-  __HAL_LOCK(hspi);
-
-  if(!((hspi->State == HAL_SPI_STATE_READY) || \
-    ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  hspi->CRCSize = 0;
-  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    hspi->CRCSize = 1;
-    if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
-    {
-      hspi->CRCSize = 2;
-    }
-  }
-
-  if(hspi->State != HAL_SPI_STATE_BUSY_RX)
-  {
-    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
-  }
-
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pTxBuffPtr  = pTxData;
-  hspi->TxXferSize  = Size;
-  hspi->TxXferCount = Size;
-  hspi->pRxBuffPtr  = pRxData;
-  hspi->RxXferSize  = Size;
-  hspi->RxXferCount = Size;
-
-  /* Set the function for IT treatment */
-  if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
-  {
-    hspi->RxISR = SPI_2linesRxISR_16BIT;
-    hspi->TxISR = SPI_2linesTxISR_16BIT;
-  }
-  else
-  {
-    hspi->RxISR = SPI_2linesRxISR_8BIT;
-    hspi->TxISR = SPI_2linesTxISR_8BIT;
-  }
-
-  /* Reset CRC Calculation */
-  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-  }
-
-  /* check if packing mode is enabled and if there is more than 2 data to receive */
-  if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2))
-  {
-    /* set fiforxthresold according the reception data length: 16 bit */
-    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-  }
-  else
-  {
-    /* set fiforxthresold according the reception data length: 8 bit */
-    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-  }
-
-  /* Enable TXE, RXNE and ERR interrupt */
-  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
-
-  /* Check if the SPI is already enabled */
-  if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-
-error :
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Transmit an amount of data in non-blocking mode with DMA.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pData: pointer to data buffer
-  * @param  Size: amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
-{
-  HAL_StatusTypeDef errorcode = HAL_OK;
-  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
-
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  if(hspi->State != HAL_SPI_STATE_READY)
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  if((pData == NULL) || (Size == 0))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  hspi->State       = HAL_SPI_STATE_BUSY_TX;
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pTxBuffPtr  = pData;
-  hspi->TxXferSize  = Size;
-  hspi->TxXferCount = Size;
-  hspi->pRxBuffPtr  = (uint8_t *)NULL;
-  hspi->RxXferSize  = 0;
-  hspi->RxXferCount = 0;
-
-  /* Configure communication direction : 1Line */
-  if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
-  {
-    SPI_1LINE_TX(hspi);
-  }
-
-  /* Reset CRC Calculation */
-  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-  }
-
-  /* Set the SPI TxDMA Half transfer complete callback */
-  hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
-
-  /* Set the SPI TxDMA transfer complete callback */
-  hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
-
-  /* Set the DMA error callback */
-  hspi->hdmatx->XferErrorCallback = SPI_DMAError;
-
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
-  /* packing mode is enabled only if the DMA setting is HALWORD */
-  if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
-  {
-    /* Check the even/odd of the data size + crc if enabled */
-    if((hspi->TxXferCount & 0x1) == 0)
-    {
-      CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
-      hspi->TxXferCount = (hspi->TxXferCount >> 1);
-    }
-    else
-    {
-      SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
-      hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
-    }
-  }
-
-  /* Enable the Tx DMA channel */
-  HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
-
-  /* Check if the SPI is already enabled */
-  if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-
-  /* Enable Tx DMA Request */
-  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
-error :
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Receive an amount of data in non-blocking mode with DMA.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pData: pointer to data buffer
-  * @note  When the CRC feature is enabled the pData Length must be Size + 1.
-  * @param  Size: amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
-{
-  HAL_StatusTypeDef errorcode = HAL_OK;
-
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  if(hspi->State != HAL_SPI_STATE_READY)
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  if((pData == NULL) || (Size == 0))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  hspi->State       = HAL_SPI_STATE_BUSY_RX;
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pRxBuffPtr  = pData;
-  hspi->RxXferSize  = Size;
-  hspi->RxXferCount = Size;
-  hspi->pTxBuffPtr  = (uint8_t *)NULL;
-  hspi->TxXferSize  = 0;
-  hspi->TxXferCount = 0;
-
-  if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
-  {
-    /* Process Unlocked */
-    __HAL_UNLOCK(hspi);
-    /* the receive process is not supported in 2Lines direction master mode */
-    /* in this case we call the TransmitReceive process                     */
-    return HAL_SPI_TransmitReceive_DMA(hspi,pData,pData,Size);
-  }
-
-  /* Configure communication direction : 1Line */
-  if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
-  {
-    SPI_1LINE_RX(hspi);
-  }
-
-  /* Reset CRC Calculation */
-  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-  }
-
-  /* packing mode management is enabled by the DMA settings */
-  if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
-  {
-    /* Restriction the DMA data received is not allowed in this mode */
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
-  if( hspi->Init.DataSize > SPI_DATASIZE_8BIT)
-  {
-    /* set fiforxthresold according the reception data length: 16bit */
-    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-  }
-  else
-  {
-    /* set fiforxthresold according the reception data length: 8bit */
-    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-  }
-
-  /* Set the SPI RxDMA Half transfer complete callback */
-  hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
-
-  /* Set the SPI Rx DMA transfer complete callback */
-  hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
-
-  /* Set the DMA error callback */
-  hspi->hdmarx->XferErrorCallback = SPI_DMAError;
-
-  /* Enable Rx DMA Request */
-  SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-
-  /* Enable the Rx DMA channel */
-  HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
-
-  /* Check if the SPI is already enabled */
-  if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-
-error:
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Transmit and Receive an amount of data in non-blocking mode with DMA.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pTxData: pointer to transmission data buffer
-  * @param  pRxData: pointer to reception data buffer
-  * @note  When the CRC feature is enabled the pRxData Length must be Size + 1
-  * @param  Size: amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
-{
-  HAL_StatusTypeDef errorcode = HAL_OK;
-  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
-
-  /* Process locked */
-  __HAL_LOCK(hspi);
-
-  if(!((hspi->State == HAL_SPI_STATE_READY) ||
-      ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  /* check if the transmit Receive function is not called by a receive master */
-  if(hspi->State != HAL_SPI_STATE_BUSY_RX)
-  {
-    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
-  }
-
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pTxBuffPtr  = (uint8_t *)pTxData;
-  hspi->TxXferSize  = Size;
-  hspi->TxXferCount = Size;
-  hspi->pRxBuffPtr  = (uint8_t *)pRxData;
-  hspi->RxXferSize  = Size;
-  hspi->RxXferCount = Size;
-
-  /* Reset CRC Calculation + increase the rxsize */
-  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-  }
-
-  /* Reset the threshold bit */
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
-
-  /* the packing mode management is enabled by the DMA settings according the spi data size */
-  if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
-  {
-    /* set fiforxthreshold according the reception data length: 16bit */
-    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-  }
-  else
-  {
-    /* set fiforxthresold according the reception data length: 8bit */
-    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-
-    if(hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
-    {
-      if((hspi->TxXferSize & 0x1) == 0x0)
-      {
-        CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
-        hspi->TxXferCount = hspi->TxXferCount >> 1;
-      }
-      else
-      {
-        SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
-        hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
-      }
-    }
-
-    if(hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
-    {
-      /* set fiforxthresold according the reception data length: 16bit */
-      CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-
-      if((hspi->RxXferCount & 0x1) == 0x0 )
-      {
-        CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
-        hspi->RxXferCount = hspi->RxXferCount >> 1;
-      }
-      else
-      {
-        SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
-        hspi->RxXferCount = (hspi->RxXferCount >> 1) + 1;
-      }
-    }
-  }
-
-  /* Set the SPI Rx DMA transfer complete callback if the transfer request is a
-     reception request (RXNE) */
-  if(hspi->State == HAL_SPI_STATE_BUSY_RX)
-  {
-    /* Set the SPI Rx DMA Half transfer complete callback */
-    hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
-    hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
-  }
-  else
-  {
-    /* Set the SPI Rx DMA Half transfer complete callback */
-    hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
-    hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
-  }
-
-  /* Set the DMA error callback */
-  hspi->hdmarx->XferErrorCallback = SPI_DMAError;
-
-  /* Enable Rx DMA Request */
-  SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-
-  /* Enable the Rx DMA channel */
-  HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t) hspi->pRxBuffPtr, hspi->RxXferCount);
-
-  /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
-  is performed in DMA reception complete callback  */
-  hspi->hdmatx->XferHalfCpltCallback = NULL;
-  hspi->hdmatx->XferCpltCallback = NULL;
-
-  /* Set the DMA error callback */
-  hspi->hdmatx->XferErrorCallback = SPI_DMAError;
-
-  /* Enable the Tx DMA channel */
-  HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
-
-  /* Check if the SPI is already enabled */
-  if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-
-  /* Enable Tx DMA Request */
-  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
-error :
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief Pause the DMA Transfer.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for the specified SPI module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
-{
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  /* Disable the SPI DMA Tx & Rx requests */
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Resume the DMA Transfer.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for the specified SPI module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
-{
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  /* Enable the SPI DMA Tx & Rx requests */
-  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Stop the DMA Transfer.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for the specified SPI module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
-{
-  /* The Lock is not implemented on this API to allow the user application
-     to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
-     when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
-     and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
-     */
-
-  /* Abort the SPI DMA tx channel */
-  if(hspi->hdmatx != NULL)
-  {
-    HAL_DMA_Abort(hspi->hdmatx);
-  }
-  /* Abort the SPI DMA rx channel */
-  if(hspi->hdmarx != NULL)
-  {
-    HAL_DMA_Abort(hspi->hdmarx);
-  }
-
-  /* Disable the SPI DMA Tx & Rx requests */
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-  hspi->State = HAL_SPI_STATE_READY;
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle SPI interrupt request.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for the specified SPI module.
-  * @retval None
-  */
-void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
-{
-  uint32_t itsource = hspi->Instance->CR2;
-  uint32_t itflag   = hspi->Instance->SR;
-
-  /* SPI in mode Receiver ----------------------------------------------------*/
-  if(((itflag & SPI_FLAG_OVR) == RESET) &&
-     ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
-  {
-    hspi->RxISR(hspi);
-    return;
-  }
-
-  /* SPI in mode Transmitter ---------------------------------------------------*/
-  if(((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
-  {
-    hspi->TxISR(hspi);
-    return;
-  }
-
-  /* SPI in Error Treatment ---------------------------------------------------*/
-  if((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET)
-  {
-    /* SPI Overrun error interrupt occurred -------------------------------------*/
-    if((itflag & SPI_FLAG_OVR) != RESET)
-    {
-      if(hspi->State != HAL_SPI_STATE_BUSY_TX)
-      {
-        hspi->ErrorCode |= HAL_SPI_ERROR_OVR;
-        __HAL_SPI_CLEAR_OVRFLAG(hspi);
-      }
-      else
-      {
-        return;
-      }
-    }
-
-    /* SPI Mode Fault error interrupt occurred -------------------------------------*/
-    if((itflag & SPI_FLAG_MODF) != RESET)
-    {
-      hspi->ErrorCode |= HAL_SPI_ERROR_MODF;
-      __HAL_SPI_CLEAR_MODFFLAG(hspi);
-    }
-
-    /* SPI Frame error interrupt occurred ----------------------------------------*/
-    if((itflag & SPI_FLAG_FRE) != RESET)
-    {
-      hspi->ErrorCode |= HAL_SPI_ERROR_FRE;
-      __HAL_SPI_CLEAR_FREFLAG(hspi);
-    }
-
-    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
-    hspi->State = HAL_SPI_STATE_READY;
-    HAL_SPI_ErrorCallback(hspi);
-    return;
-  }
-}
-
-/**
-  * @brief Tx Transfer completed callback.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_TxCpltCallback should be implemented in the user file
-   */
-}
-
-/**
-  * @brief Rx Transfer completed callback.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_RxCpltCallback should be implemented in the user file
-   */
-}
-
-/**
-  * @brief Tx and Rx Transfer completed callback.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_TxRxCpltCallback should be implemented in the user file
-   */
-}
-
-/**
-  * @brief Tx Half Transfer completed callback.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
-   */
-}
-
-/**
-  * @brief Rx Half Transfer completed callback.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
-   */
-}
-
-/**
-  * @brief Tx and Rx Half Transfer callback.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
-   */
-}
-
-/**
-  * @brief SPI error callback.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_ErrorCallback should be implemented in the user file
-   */
-  /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
-            and user can use HAL_SPI_GetError() API to check the latest error occurred
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
-  *  @brief   SPI control functions
-  *
-@verbatim
- ===============================================================================
-                      ##### Peripheral State and Errors functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to control the SPI.
-     (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
-     (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the SPI handle state.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval SPI state
-  */
-HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
-{
-  /* Return SPI handle state */
-  return hspi->State;
-}
-
-/**
-  * @brief  Return the SPI error code.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval SPI error code in bitmap format
-  */
-uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
-{
-  return hspi->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup SPI_Private_Functions
- *  @brief   Private functions
-  * @{
-  */
-
-/**
-  * @brief DMA SPI transmit process complete callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
-  {
-    /* Disable Tx DMA Request */
-    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
-    /* Check the end of the transaction */
-    if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT) != HAL_OK)
-    {
-      hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
-    }
-
-    /* Clear overrun flag in 2 Lines communication mode because received data is not read */
-    if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
-    {
-      __HAL_SPI_CLEAR_OVRFLAG(hspi);
-    }
-
-    hspi->TxXferCount = 0;
-    hspi->State = HAL_SPI_STATE_READY;
-
-    if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
-    {
-      HAL_SPI_ErrorCallback(hspi);
-      return;
-    }
-  }
-  HAL_SPI_TxCpltCallback(hspi);
-}
-
-/**
-  * @brief DMA SPI receive process complete callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
-  {
-    __IO uint16_t tmpreg;
-
-    /* CRC handling */
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      /* Wait until TXE flag */
-      if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
-      {
-        /* Error on the CRC reception */
-        hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
-      }
-      if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
-      {
-        tmpreg = hspi->Instance->DR;
-        UNUSED(tmpreg); /* To avoid GCC warning */
-      }
-      else
-      {
-        tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
-        UNUSED(tmpreg); /* To avoid GCC warning */
-
-        if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
-        {
-          if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
-          {
-            /* Error on the CRC reception */
-            hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
-          }
-          tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
-          UNUSED(tmpreg); /* To avoid GCC warning */
-        }
-      }
-    }
-
-    /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
-    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
-    /* Check the end of the transaction */
-    if(SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
-    {
-      hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
-    }
-
-    hspi->RxXferCount = 0;
-    hspi->State = HAL_SPI_STATE_READY;
-
-    /* Check if CRC error occurred */
-    if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
-    {
-      hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
-      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-    }
-
-    if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
-    {
-      HAL_SPI_ErrorCallback(hspi);
-      return;
-    }
-  }
-  HAL_SPI_RxCpltCallback(hspi);
-}
-
-/**
-  * @brief DMA SPI transmit receive process complete callback.
-  * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
-  {
-    __IO int16_t tmpreg;
-    /* CRC handling */
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
-      {
-        if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
-        {
-          /* Error on the CRC reception */
-          hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
-        }
-        tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
-        UNUSED(tmpreg); /* To avoid GCC warning */  
-      }
-      else
-      {
-        if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
-        {
-          /* Error on the CRC reception */
-          hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
-        }
-        tmpreg = hspi->Instance->DR;
-        UNUSED(tmpreg); /* To avoid GCC warning */  
-      }
-    }
-
-    /* Check the end of the transaction */
-    if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT) != HAL_OK)
-    {
-      hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
-    }
-  
-    /* Disable Rx/Tx DMA Request */
-    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
-    hspi->TxXferCount = 0;
-    hspi->RxXferCount = 0;
-    hspi->State = HAL_SPI_STATE_READY;
-
-    /* Check if CRC error occurred */
-    if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
-    {
-      hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
-      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-    }
-
-    if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
-    {
-      HAL_SPI_ErrorCallback(hspi);
-      return;
-    }
-  }
-  HAL_SPI_TxRxCpltCallback(hspi);
-}
-
-/**
-  * @brief DMA SPI half transmit process complete callback.
-  * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  HAL_SPI_TxHalfCpltCallback(hspi);
-}
-
-/**
-  * @brief DMA SPI half receive process complete callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  HAL_SPI_RxHalfCpltCallback(hspi);
-}
-
-/**
-  * @brief DMA SPI half transmit receive process complete callback.
-  * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  HAL_SPI_TxRxHalfCpltCallback(hspi);
-}
-
-/**
-  * @brief DMA SPI communication error callback.
-  * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SPI_DMAError(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  /* Stop the disable DMA transfer on SPI side */
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
-  hspi->ErrorCode|= HAL_SPI_ERROR_DMA;
-  hspi->State = HAL_SPI_STATE_READY;
-  HAL_SPI_ErrorCallback(hspi);
-}
-
-/**
-  * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
-{
-  /* Receive data in packing mode */
-  if(hspi->RxXferCount > 1)
-  {
-    *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
-    hspi->pRxBuffPtr += sizeof(uint16_t);
-    hspi->RxXferCount -= 2;
-    if(hspi->RxXferCount == 1) 
-    {
-      /* set fiforxthresold according the reception data length: 8bit */
-      SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-    }
-  }
-  /* Receive data in 8 Bit mode */
-  else
-  {
-    *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR);
-    hspi->RxXferCount--;
-  }
-
-  /* check end of the reception */
-  if(hspi->RxXferCount == 0)
-  {
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-      hspi->RxISR =  SPI_2linesRxISR_8BITCRC;
-      return;
-    }
-
-    /* Disable RXNE interrupt */
-    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
-
-    if(hspi->TxXferCount == 0)
-    {
-      SPI_CloseRxTx_ISR(hspi);
-    }
-  }
-}
-
-/**
-  * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
-{
-  __IO uint8_t tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
-  UNUSED(tmpreg); /* To avoid GCC warning */
-
-  hspi->CRCSize--;
-
-  /* check end of the reception */
-  if(hspi->CRCSize == 0)
-  {
-    /* Disable RXNE interrupt */
-    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
-
-    if(hspi->TxXferCount == 0)
-    {
-      SPI_CloseRxTx_ISR(hspi);
-    }
-  }
-}
-
-/**
-  * @brief  Tx 8-bit handler for Transmit and Receive in Interrupt mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
-{
-  /* Transmit data in packing Bit mode */
-  if(hspi->TxXferCount >= 2)
-  {
-    hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
-    hspi->pTxBuffPtr += sizeof(uint16_t);
-    hspi->TxXferCount -= 2;
-  }
-  /* Transmit data in 8 Bit mode */
-  else
-  {
-    *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
-    hspi->TxXferCount--;
-  }
-
-  /* check the end of the transmission */
-  if(hspi->TxXferCount == 0)
-  {
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
-    }
-    /* Disable TXE interrupt */
-    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
-
-    if(hspi->RxXferCount == 0)
-    {
-      SPI_CloseRxTx_ISR(hspi);
-    }
-  }
-}
-
-/**
-  * @brief  Rx 16-bit handler for Transmit and Receive in Interrupt mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
-{
-  /* Receive data in 16 Bit mode */
-  *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
-  hspi->pRxBuffPtr += sizeof(uint16_t);
-  hspi->RxXferCount--;
-
-  if(hspi->RxXferCount == 0)
-  {
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      hspi->RxISR =  SPI_2linesRxISR_16BITCRC;
-      return;
-    }
-
-    /* Disable RXNE interrupt */
-    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
-
-    if(hspi->TxXferCount == 0)
-    {
-      SPI_CloseRxTx_ISR(hspi);
-    }
-  }
-}
-
-/**
-  * @brief  Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
-{
-  /* Receive data in 16 Bit mode */
-  __IO uint16_t tmpreg = hspi->Instance->DR;
-  UNUSED(tmpreg); /* To avoid GCC warning */
-
-  /* Disable RXNE interrupt */
-  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
-
-  SPI_CloseRxTx_ISR(hspi);
-}
-
-/**
-  * @brief  Tx 16-bit handler for Transmit and Receive in Interrupt mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
-{
-  /* Transmit data in 16 Bit mode */
-  hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
-  hspi->pTxBuffPtr += sizeof(uint16_t);
-  hspi->TxXferCount--;
-
-  /* Enable CRC Transmission */
-  if(hspi->TxXferCount == 0)
-  {
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
-    }
-    /* Disable TXE interrupt */
-    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
-
-    if(hspi->RxXferCount == 0)
-    {
-      SPI_CloseRxTx_ISR(hspi);
-    }
-  }
-}
-
-/**
-  * @brief  Manage the CRC 8-bit receive in Interrupt context.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
-{
-  __IO uint8_t tmpreg = *((uint8_t*)&hspi->Instance->DR);
-  UNUSED(tmpreg); /* To avoid GCC warning */
-
-  hspi->CRCSize--;
-
-  if(hspi->CRCSize == 0)
-  {
-    SPI_CloseRx_ISR(hspi);
-  }
-}
-
-/**
-  * @brief  Manage the receive 8-bit in Interrupt context.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
-{
-  *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);
-  hspi->RxXferCount--;
-
-  /* Enable CRC Transmission */
-  if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
-  {
-    hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
-  }
-
-  if(hspi->RxXferCount == 0)
-  {
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      hspi->RxISR =  SPI_RxISR_8BITCRC;
-      return;
-    }
-    SPI_CloseRx_ISR(hspi);
-  }
-}
-
-/**
-  * @brief  Manage the CRC 16-bit receive in Interrupt context.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
-{
-  __IO uint16_t tmpreg;
-
-  tmpreg = hspi->Instance->DR;
-  UNUSED(tmpreg); /* To avoid GCC warning */
-
-  /* Disable RXNE and ERR interrupt */
-  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
-  SPI_CloseRx_ISR(hspi);
-}
-
-/**
-  * @brief  Manage the 16-bit receive in Interrupt context.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
-{
-  *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
-  hspi->pRxBuffPtr += sizeof(uint16_t);
-  hspi->RxXferCount--;
-
-  /* Enable CRC Transmission */
-  if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
-  {
-    hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
-  }
-
-  if(hspi->RxXferCount == 0)
-  {
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      hspi->RxISR = SPI_RxISR_16BITCRC;
-      return;
-    }
-    SPI_CloseRx_ISR(hspi);
-  }
-}
-
-/**
-  * @brief  Handle the data 8-bit transmit in Interrupt mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
-{
-  *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
-  hspi->TxXferCount--;
-
-  if(hspi->TxXferCount == 0)
-  {
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      /* Enable CRC Transmission */
-      hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
-    }
-
-    SPI_CloseTx_ISR(hspi);
-  }
-}
-
-/**
-  * @brief  Handle the data 16-bit transmit in Interrupt mode.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
-{
-  /* Transmit data in 16 Bit mode */
-  hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
-  hspi->pTxBuffPtr += sizeof(uint16_t);
-  hspi->TxXferCount--;
-
-  if(hspi->TxXferCount == 0)
-  {
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      /* Enable CRC Transmission */
-      hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
-    }
-    SPI_CloseTx_ISR(hspi);
-  }
-}
-
-/**
-  * @brief Handle SPI Communication Timeout.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param Flag : SPI flag to check
-  * @param State : flag state to check
-  * @param Timeout : Timeout duration
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout)
-{
-  uint32_t tickstart = HAL_GetTick();
-
-  while((hspi->Instance->SR & Flag) != State)
-  {
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout))
-      {
-        /* Disable the SPI and reset the CRC: the CRC value should be cleared
-        on both master and slave sides in order to resynchronize the master
-        and slave for their respective CRC calculation */
-
-        /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
-        __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
-
-        if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
-        {
-          /* Disable SPI peripheral */
-          __HAL_SPI_DISABLE(hspi);
-        }
-
-        /* Reset CRC Calculation */
-        if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-        {
-          SPI_RESET_CRC(hspi);
-        }
-
-        hspi->State= HAL_SPI_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hspi);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Handle SPI FIFO Communication Timeout.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param Fifo : Fifo to check
-  * @param State : Fifo state to check
-  * @param Timeout : Timeout duration
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout)
-{
-  __IO uint8_t tmpreg;
-  uint32_t tickstart = HAL_GetTick();
-
-  while((hspi->Instance->SR & Fifo) != State)
-  {
-    if((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
-    {
-      tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
-      UNUSED(tmpreg); /* To avoid GCC warning */
-    }
-
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout))
-      {
-        /* Disable the SPI and reset the CRC: the CRC value should be cleared
-                  on both master and slave sides in order to resynchronize the master
-                 and slave for their respective CRC calculation */
-
-        /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
-        __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
-
-        if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
-        {
-          /* Disable SPI peripheral */
-          __HAL_SPI_DISABLE(hspi);
-        }
-
-        /* Reset CRC Calculation */
-        if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-        {
-          SPI_RESET_CRC(hspi);
-        }
-
-        hspi->State = HAL_SPI_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hspi);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Handle the check of the RX transaction complete.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param Timeout : Timeout duration
-  * @retval None
-  */
-static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi,  uint32_t Timeout)
-{
-  if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
-  {
-    /* Disable SPI peripheral */
-    __HAL_SPI_DISABLE(hspi);
-  }
-  
-  /* Control the BSY flag */
-  if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
-  {
-    hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
-    return HAL_TIMEOUT;
-  }
-
-  if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
-  {
-    /* Empty the FRLVL fifo */
-    if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
-    {
-      hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
-      return HAL_TIMEOUT;
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief Handle the check of the RXTX or TX transaction complete.
-  * @param hspi: SPI handle
-  * @param Timeout : Timeout duration
-  */
-static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
-{
-  /* Control if the TX fifo is empty */
-  if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout) != HAL_OK)
-  {
-    hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
-    return HAL_TIMEOUT;
-  }
-  /* Control the BSY flag */
-  if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
-  {
-    hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
-    return HAL_TIMEOUT;
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief Handle the end of the RXTX transaction.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
-{
-  /* Disable ERR interrupt */
-  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
-
-  /* Check the end of the transaction */
-  if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
-  {
-    hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
-  }
-
-  /* Check if CRC error occurred */
-  if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
-  {
-    hspi->State = HAL_SPI_STATE_READY;
-    hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
-    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-    HAL_SPI_ErrorCallback(hspi);
-  }
-  else
-  {
-    if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
-    {
-      if(hspi->State == HAL_SPI_STATE_BUSY_RX)
-      {
-      	hspi->State = HAL_SPI_STATE_READY;
-        HAL_SPI_RxCpltCallback(hspi);
-      }
-      else
-      {
-      	hspi->State = HAL_SPI_STATE_READY;
-        HAL_SPI_TxRxCpltCallback(hspi);
-      }
-    }
-    else
-    {
-      hspi->State = HAL_SPI_STATE_READY;
-      HAL_SPI_ErrorCallback(hspi);
-    }
-  }
-}
-
-/**
-  * @brief Handle the end of the RX transaction.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
-{
-    /* Disable RXNE and ERR interrupt */
-    __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
-    /* Check the end of the transaction */
-    if(SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
-    {
-      hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
-    }
-    hspi->State = HAL_SPI_STATE_READY;
-
-    /* Check if CRC error occurred */
-    if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
-    {
-      hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
-      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-      HAL_SPI_ErrorCallback(hspi);
-    }
-    else
-    {
-      if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
-      {
-        HAL_SPI_RxCpltCallback(hspi);
-      }
-      else
-      {
-        HAL_SPI_ErrorCallback(hspi);
-      }
-    }
-}
-
-/**
-  * @brief Handle the end of the TX transaction.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
-{
-  /* Disable TXE and ERR interrupt */
-  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
-
-  /* Check the end of the transaction */
-  if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
-  {
-    hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
-  }
-
-  /* Clear overrun flag in 2 Lines communication mode because received is not read */
-  if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
-  {
-    __HAL_SPI_CLEAR_OVRFLAG(hspi);
-  }
-
-  hspi->State = HAL_SPI_STATE_READY;
-  if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
-  {
-    HAL_SPI_ErrorCallback(hspi);
-  }
-  else
-  {
-    HAL_SPI_TxCpltCallback(hspi);
-  }
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/src/stm32l4xx_hal_spi_ex.c b/stmhal/hal/l4/src/stm32l4xx_hal_spi_ex.c
deleted file mode 100644
index 18224c859e..0000000000
--- a/stmhal/hal/l4/src/stm32l4xx_hal_spi_ex.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_spi_ex.c
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   Extended SPI HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          SPI peripheral extended functionalities :
-  *           + IO operation functions
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup SPIEx SPIEx
-  * @brief SPI Extended HAL module driver
-  * @{
-  */
-#ifdef HAL_SPI_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup SPIEx_Private_Constants SPIEx Private Constants
-  * @{
-  */
-#define SPI_FIFO_SIZE       4
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions
-  * @{
-  */
-
-/** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions
- *  @brief   Data transfers functions
- *
-@verbatim
-  ==============================================================================
-                      ##### IO operation functions #####
- ===============================================================================
- [..]
-    This subsection provides a set of extended functions to manage the SPI
-    data transfers.
-
-    (#) Rx data flush function:
-        (++) HAL_SPIEx_FlushRxFifo()
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Flush the RX fifo.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for the specified SPI module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi)
-{
-  __IO uint32_t tmpreg;
-  uint8_t  count = 0;
-  while((hspi->Instance->SR & SPI_FLAG_FRLVL) !=  SPI_FRLVL_EMPTY)
-  {
-    count++;
-    tmpreg = hspi->Instance->DR;
-    UNUSED(tmpreg); /* To avoid GCC warning */
-    if(count == SPI_FIFO_SIZE)
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/src/stm32l4xx_hal_tim.c b/stmhal/hal/l4/src/stm32l4xx_hal_tim.c
deleted file mode 100644
index 73567062e1..0000000000
--- a/stmhal/hal/l4/src/stm32l4xx_hal_tim.c
+++ /dev/null
@@ -1,5383 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_tim.c
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   TIM HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Timer (TIM) peripheral:
-  *           + Time Base Initialization
-  *           + Time Base Start
-  *           + Time Base Start Interruption
-  *           + Time Base Start DMA
-  *           + Time Output Compare/PWM Initialization
-  *           + Time Output Compare/PWM Channel Configuration
-  *           + Time Output Compare/PWM  Start
-  *           + Time Output Compare/PWM  Start Interruption
-  *           + Time Output Compare/PWM Start DMA
-  *           + Time Input Capture Initialization
-  *           + Time Input Capture Channel Configuration
-  *           + Time Input Capture Start
-  *           + Time Input Capture Start Interruption
-  *           + Time Input Capture Start DMA
-  *           + Time One Pulse Initialization
-  *           + Time One Pulse Channel Configuration
-  *           + Time One Pulse Start
-  *           + Time Encoder Interface Initialization
-  *           + Time Encoder Interface Start
-  *           + Time Encoder Interface Start Interruption
-  *           + Time Encoder Interface Start DMA
-  *           + Commutation Event configuration with Interruption and DMA
-  *           + Time OCRef clear configuration
-  *           + Time External Clock configuration
-  @verbatim
-  ==============================================================================
-                      ##### TIMER Generic features #####
-  ==============================================================================
-  [..] The Timer features include:
-       (#) 16-bit up, down, up/down auto-reload counter.
-       (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
-           counter clock frequency either by any factor between 1 and 65536.
-       (#) Up to 4 independent channels for:
-           (++) Input Capture
-           (++) Output Compare
-           (++) PWM generation (Edge and Center-aligned Mode)
-           (++) One-pulse mode output
-
-            ##### How to use this driver #####
-  ==============================================================================
-    [..]
-     (#) Initialize the TIM low level resources by implementing the following functions
-         depending on the selected feature:
-           (++) Time Base : HAL_TIM_Base_MspInit()
-           (++) Input Capture : HAL_TIM_IC_MspInit()
-           (++) Output Compare : HAL_TIM_OC_MspInit()
-           (++) PWM generation : HAL_TIM_PWM_MspInit()
-           (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
-           (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
-
-     (#) Initialize the TIM low level resources :
-        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
-        (##) TIM pins configuration
-            (+++) Enable the clock for the TIM GPIOs using the following function:
-             __HAL_RCC_GPIOx_CLK_ENABLE();
-            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
-
-     (#) The external Clock can be configured, if needed (the default clock is the
-         internal clock from the APBx), using the following function:
-         HAL_TIM_ConfigClockSource, the clock configuration should be done before
-         any start function.
-
-     (#) Configure the TIM in the desired functioning mode using one of the
-       Initialization function of this driver:
-       (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
-       (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
-            Output Compare signal.
-       (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
-            PWM signal.
-       (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
-            external signal.
-         (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
-              in One Pulse Mode.
-       (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
-
-     (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
-           (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
-           (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
-           (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
-           (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
-           (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
-           (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
-
-     (#) The DMA Burst is managed with the two following functions:
-         HAL_TIM_DMABurst_WriteStart()
-         HAL_TIM_DMABurst_ReadStart()
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup TIM TIM
-  * @brief TIM HAL module driver
-  * @{
-  */
-
-#ifdef HAL_TIM_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
-static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                       uint32_t TIM_ICFilter);
-static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
-static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                       uint32_t TIM_ICFilter);
-static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                       uint32_t TIM_ICFilter);
-static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
-static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
-static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
-static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
-                                     TIM_SlaveConfigTypeDef * sSlaveConfig);
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup TIM_Exported_Functions TIM Exported Functions
-  * @{
-  */
-
-/** @defgroup TIM_Exported_Functions_Group1 Time Base functions
- *  @brief    Time Base functions
- *
-@verbatim
-  ==============================================================================
-              ##### Time Base functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Initialize and configure the TIM base.
-    (+) De-initialize the TIM base.
-    (+) Start the Time Base.
-    (+) Stop the Time Base.
-    (+) Start the Time Base and enable interrupt.
-    (+) Stop the Time Base and disable interrupt.
-    (+) Start the Time Base and enable DMA transfer.
-    (+) Stop the Time Base and disable DMA transfer.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIM Time base Unit according to the specified
-  *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
-  * @param  htim: TIM Base handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
-{
-  /* Check the TIM handle allocation */
-  if(htim == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-
-  if(htim->State == HAL_TIM_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    htim->Lock = HAL_UNLOCKED;
-
-    /* Init the low level hardware : GPIO, CLOCK, NVIC */
-    HAL_TIM_Base_MspInit(htim);
-  }
-
-  /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;
-
-  /* Set the Time Base configuration */
-  TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
-  /* Initialize the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitialize the TIM Base peripheral
-  * @param  htim: TIM Base handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Disable the TIM Peripheral Clock */
-  __HAL_TIM_DISABLE(htim);
-
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
-  HAL_TIM_Base_MspDeInit(htim);
-
-  /* Change TIM state */
-  htim->State = HAL_TIM_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM Base MSP.
-  * @param  htim: TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_Base_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitialize TIM Base MSP.
-  * @param  htim: TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_Base_MspDeInit could be implemented in the user file
-   */
-}
-
-
-/**
-  * @brief  Starts the TIM Base generation.
-  * @param  htim : TIM handle
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Change the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Base generation.
-  * @param  htim : TIM handle
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Change the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Base generation in interrupt mode.
-  * @param  htim : TIM handle
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-   /* Enable the TIM Update interrupt */
-   __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
-
-   /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Base generation in interrupt mode.
-  * @param  htim : TIM handle
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  /* Disable the TIM Update interrupt */
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Base generation in DMA mode.
-  * @param  htim : TIM handle
-  * @param  pData: The source Buffer address.
-  * @param  Length: The length of data to be transferred from memory to peripheral.
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
-
-  if((htim->State == HAL_TIM_STATE_BUSY))
-  {
-     return HAL_BUSY;
-  }
-  else if((htim->State == HAL_TIM_STATE_READY))
-  {
-    if((pData == 0 ) && (Length > 0))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      htim->State = HAL_TIM_STATE_BUSY;
-    }
-  }
-  /* Set the DMA Period elapsed callback */
-  htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
-
-  /* Set the DMA error callback */
-  htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
-
-  /* Enable the DMA channel */
-  HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
-
-  /* Enable the TIM Update DMA request */
-  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Base generation in DMA mode.
-  * @param  htim : TIM handle
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
-
-  /* Disable the TIM Update DMA request */
-  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Change the htim state */
-  htim->State = HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
- *  @brief    Time Output Compare functions
- *
-@verbatim
-  ==============================================================================
-                  ##### Time Output Compare functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Initialize and configure the TIM Output Compare.
-    (+) De-initialize the TIM Output Compare.
-    (+) Start the Time Output Compare.
-    (+) Stop the Time Output Compare.
-    (+) Start the Time Output Compare and enable interrupt.
-    (+) Stop the Time Output Compare and disable interrupt.
-    (+) Start the Time Output Compare and enable DMA transfer.
-    (+) Stop the Time Output Compare and disable DMA transfer.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIM Output Compare according to the specified
-  *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
-  * @param  htim: TIM Output Compare handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
-{
-  /* Check the TIM handle allocation */
-  if(htim == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-
-  if(htim->State == HAL_TIM_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    htim->Lock = HAL_UNLOCKED;
-
-    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
-    HAL_TIM_OC_MspInit(htim);
-  }
-
-  /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;
-
-  /* Init the base time for the Output Compare */
-  TIM_Base_SetConfig(htim->Instance,  &htim->Init);
-
-  /* Initialize the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitialize the TIM peripheral
-  * @param  htim: TIM Output Compare handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-   htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Disable the TIM Peripheral Clock */
-  __HAL_TIM_DISABLE(htim);
-
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
-  HAL_TIM_OC_MspDeInit(htim);
-
-  /* Change TIM state */
-  htim->State = HAL_TIM_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM Output Compare MSP.
-  * @param  htim: TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_OC_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitialize TIM Output Compare MSP.
-  * @param  htim: TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_OC_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Starts the TIM Output Compare signal generation.
-  * @param  htim : TIM Output Compare handle
-  * @param  Channel : TIM Channel to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
-  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  /* Enable the Output compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
-  {
-    /* Enable the main output */
-    __HAL_TIM_MOE_ENABLE(htim);
-  }
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Output Compare signal generation.
-  * @param  htim : TIM handle
-  * @param  Channel : TIM Channel to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
-  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  /* Disable the Output compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
-  {
-    /* Disable the Main Ouput */
-    __HAL_TIM_MOE_DISABLE(htim);
-  }
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Output Compare signal generation in interrupt mode.
-  * @param  htim : TIM OC handle
-  * @param  Channel : TIM Channel to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
-  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Enable the TIM Capture/Compare 1 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Enable the TIM Capture/Compare 2 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Enable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Enable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Enable the Output compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
-  {
-    /* Enable the main output */
-    __HAL_TIM_MOE_ENABLE(htim);
-  }
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Output Compare signal generation in interrupt mode.
-  * @param  htim : TIM Output Compare handle
-  * @param  Channel : TIM Channel to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
-  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Disable the TIM Capture/Compare 1 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Capture/Compare 2 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Disable the Output compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
-  {
-    /* Disable the Main Ouput */
-    __HAL_TIM_MOE_DISABLE(htim);
-  }
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Output Compare signal generation in DMA mode.
-  * @param  htim : TIM Output Compare handle
-  * @param  Channel : TIM Channel to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
-  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
-  * @param  pData: The source Buffer address.
-  * @param  Length: The length of data to be transferred from memory to TIM peripheral
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  if((htim->State == HAL_TIM_STATE_BUSY))
-  {
-     return HAL_BUSY;
-  }
-  else if((htim->State == HAL_TIM_STATE_READY))
-  {
-    if(((uint32_t)pData == 0 ) && (Length > 0))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      htim->State = HAL_TIM_STATE_BUSY;
-    }
-  }
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
-
-      /* Enable the TIM Capture/Compare 1 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
-
-      /* Enable the TIM Capture/Compare 2 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-
-      /* Enable the TIM Capture/Compare 3 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-     /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-
-      /* Enable the TIM Capture/Compare 4 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
-    }
-    break;
-
-  default:
-    break;
-  }
-
-  /* Enable the Output compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
-  {
-    /* Enable the main output */
-    __HAL_TIM_MOE_ENABLE(htim);
-  }
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Output Compare signal generation in DMA mode.
-  * @param  htim : TIM Output Compare handle
-  * @param  Channel : TIM Channel to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
-  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Disable the TIM Capture/Compare 1 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Capture/Compare 2 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Capture/Compare 3 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Disable the Output compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
-  {
-    /* Disable the Main Ouput */
-    __HAL_TIM_MOE_DISABLE(htim);
-  }
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Change the htim state */
-  htim->State = HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
- *  @brief    Time PWM functions
- *
-@verbatim
-  ==============================================================================
-                          ##### Time PWM functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Initialize and configure the TIM OPWM.
-    (+) De-initialize the TIM PWM.
-    (+) Start the Time PWM.
-    (+) Stop the Time PWM.
-    (+) Start the Time PWM and enable interrupt.
-    (+) Stop the Time PWM and disable interrupt.
-    (+) Start the Time PWM and enable DMA transfer.
-    (+) Stop the Time PWM and disable DMA transfer.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIM PWM Time Base according to the specified
-  *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
-  * @param  htim: TIM handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
-{
-  /* Check the TIM handle allocation */
-  if(htim == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-
-  if(htim->State == HAL_TIM_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    htim->Lock = HAL_UNLOCKED;
-
-    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
-    HAL_TIM_PWM_MspInit(htim);
-  }
-
-  /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;
-
-  /* Init the base time for the PWM */
-  TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
-  /* Initialize the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitialize the TIM peripheral
-  * @param  htim: TIM handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Disable the TIM Peripheral Clock */
-  __HAL_TIM_DISABLE(htim);
-
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
-  HAL_TIM_PWM_MspDeInit(htim);
-
-  /* Change TIM state */
-  htim->State = HAL_TIM_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM PWM MSP.
-  * @param  htim: TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_PWM_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitialize TIM PWM MSP.
-  * @param  htim: TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_PWM_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Starts the PWM signal generation.
-  * @param  htim : TIM handle
-  * @param  Channel : TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
-  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  /* Enable the Capture compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
-  {
-    /* Enable the main output */
-    __HAL_TIM_MOE_ENABLE(htim);
-  }
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the PWM signal generation.
-  * @param  htim : TIM handle
-  * @param  Channel : TIM Channels to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
-  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  /* Disable the Capture compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
-  {
-    /* Disable the Main Ouput */
-    __HAL_TIM_MOE_DISABLE(htim);
-  }
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Change the htim state */
-  htim->State = HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the PWM signal generation in interrupt mode.
-  * @param  htim : TIM handle
-  * @param  Channel : TIM Channel to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Enable the TIM Capture/Compare 1 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Enable the TIM Capture/Compare 2 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Enable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Enable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Enable the Capture compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
-  {
-    /* Enable the main output */
-    __HAL_TIM_MOE_ENABLE(htim);
-  }
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the PWM signal generation in interrupt mode.
-  * @param  htim : TIM handle
-  * @param  Channel : TIM Channels to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Disable the TIM Capture/Compare 1 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Capture/Compare 2 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Disable the Capture compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
-  {
-    /* Disable the Main Ouput */
-    __HAL_TIM_MOE_DISABLE(htim);
-  }
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM PWM signal generation in DMA mode.
-  * @param  htim : TIM handle
-  * @param  Channel : TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  pData: The source Buffer address.
-  * @param  Length: The length of data to be transferred from memory to TIM peripheral
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  if((htim->State == HAL_TIM_STATE_BUSY))
-  {
-     return HAL_BUSY;
-  }
-  else if((htim->State == HAL_TIM_STATE_READY))
-  {
-    if(((uint32_t)pData == 0 ) && (Length > 0))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      htim->State = HAL_TIM_STATE_BUSY;
-    }
-  }
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
-
-      /* Enable the TIM Capture/Compare 1 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
-
-      /* Enable the TIM Capture/Compare 2 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-
-      /* Enable the TIM Output Capture/Compare 3 request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-     /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-
-      /* Enable the TIM Capture/Compare 4 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Enable the Capture compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
-  {
-    /* Enable the main output */
-    __HAL_TIM_MOE_ENABLE(htim);
-  }
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM PWM signal generation in DMA mode.
-  * @param  htim : TIM handle
-  * @param  Channel : TIM Channels to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Disable the TIM Capture/Compare 1 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Capture/Compare 2 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Capture/Compare 3 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Disable the Capture compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
-  {
-    /* Disable the Main Ouput */
-    __HAL_TIM_MOE_DISABLE(htim);
-  }
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Change the htim state */
-  htim->State = HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
- *  @brief    Time Input Capture functions
- *
-@verbatim
-  ==============================================================================
-              ##### Time Input Capture functions #####
-  ==============================================================================
- [..]
-   This section provides functions allowing to:
-   (+) Initialize and configure the TIM Input Capture.
-   (+) De-initialize the TIM Input Capture.
-   (+) Start the Time Input Capture.
-   (+) Stop the Time Input Capture.
-   (+) Start the Time Input Capture and enable interrupt.
-   (+) Stop the Time Input Capture and disable interrupt.
-   (+) Start the Time Input Capture and enable DMA transfer.
-   (+) Stop the Time Input Capture and disable DMA transfer.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIM Input Capture Time base according to the specified
-  *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
-  * @param  htim: TIM Input Capture handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
-{
-  /* Check the TIM handle allocation */
-  if(htim == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-
-  if(htim->State == HAL_TIM_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    htim->Lock = HAL_UNLOCKED;
-
-    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
-    HAL_TIM_IC_MspInit(htim);
-  }
-
-  /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;
-
-  /* Init the base time for the input capture */
-  TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
-  /* Initialize the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitialize the TIM peripheral
-  * @param  htim: TIM Input Capture handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Disable the TIM Peripheral Clock */
-  __HAL_TIM_DISABLE(htim);
-
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
-  HAL_TIM_IC_MspDeInit(htim);
-
-  /* Change TIM state */
-  htim->State = HAL_TIM_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM INput Capture MSP.
-  * @param  htim: TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_IC_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitialize TIM Input Capture MSP.
-  * @param  htim: TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_IC_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Starts the TIM Input Capture measurement.
-  * @param  htim : TIM Input Capture handle
-  * @param  Channel : TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  /* Enable the Input Capture channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Input Capture measurement.
-  * @param  htim : TIM handle
-  * @param  Channel : TIM Channels to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  /* Disable the Input Capture channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Input Capture measurement in interrupt mode.
-  * @param  htim : TIM Input Capture handle
-  * @param  Channel : TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Enable the TIM Capture/Compare 1 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Enable the TIM Capture/Compare 2 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Enable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Enable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-  /* Enable the Input Capture channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Input Capture measurement in interrupt mode.
-  * @param  htim : TIM handle
-  * @param  Channel : TIM Channels to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Disable the TIM Capture/Compare 1 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Capture/Compare 2 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Disable the Input Capture channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Input Capture measurement on in DMA mode.
-  * @param  htim : TIM Input Capture handle
-  * @param  Channel : TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  pData: The destination Buffer address.
-  * @param  Length: The length of data to be transferred from TIM peripheral to memory.
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-
-  if((htim->State == HAL_TIM_STATE_BUSY))
-  {
-     return HAL_BUSY;
-  }
-  else if((htim->State == HAL_TIM_STATE_READY))
-  {
-    if((pData == 0 ) && (Length > 0))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      htim->State = HAL_TIM_STATE_BUSY;
-    }
-  }
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
-
-      /* Enable the TIM Capture/Compare 1 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
-
-      /* Enable the TIM Capture/Compare 2  DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
-
-      /* Enable the TIM Capture/Compare 3  DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
-
-      /* Enable the TIM Capture/Compare 4  DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Enable the Input Capture channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Input Capture measurement on in DMA mode.
-  * @param  htim : TIM Input Capture handle
-  * @param  Channel : TIM Channels to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Disable the TIM Capture/Compare 1 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Capture/Compare 2 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Capture/Compare 3  DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 4  DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Disable the Input Capture channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Change the htim state */
-  htim->State = HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
- *  @brief    Time One Pulse functions
- *
-@verbatim
-  ==============================================================================
-                        ##### Time One Pulse functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Initialize and configure the TIM One Pulse.
-    (+) De-initialize the TIM One Pulse.
-    (+) Start the Time One Pulse.
-    (+) Stop the Time One Pulse.
-    (+) Start the Time One Pulse and enable interrupt.
-    (+) Stop the Time One Pulse and disable interrupt.
-    (+) Start the Time One Pulse and enable DMA transfer.
-    (+) Stop the Time One Pulse and disable DMA transfer.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIM One Pulse Time Base according to the specified
-  *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
-  * @param  htim: TIM OnePulse handle
-  * @param  OnePulseMode: Select the One pulse mode.
-  *         This parameter can be one of the following values:
-  *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
-  *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
-{
-  /* Check the TIM handle allocation */
-  if(htim == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-  assert_param(IS_TIM_OPM_MODE(OnePulseMode));
-
-  if(htim->State == HAL_TIM_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    htim->Lock = HAL_UNLOCKED;
-
-    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
-    HAL_TIM_OnePulse_MspInit(htim);
-  }
-
-  /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;
-
-  /* Configure the Time base in the One Pulse Mode */
-  TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
-  /* Reset the OPM Bit */
-  htim->Instance->CR1 &= ~TIM_CR1_OPM;
-
-  /* Configure the OPM Mode */
-  htim->Instance->CR1 |= OnePulseMode;
-
-  /* Initialize the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitialize the TIM One Pulse
-  * @param  htim: TIM One Pulse handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Disable the TIM Peripheral Clock */
-  __HAL_TIM_DISABLE(htim);
-
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
-  HAL_TIM_OnePulse_MspDeInit(htim);
-
-  /* Change TIM state */
-  htim->State = HAL_TIM_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM One Pulse MSP.
-  * @param  htim: TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_OnePulse_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitialize TIM One Pulse MSP.
-  * @param  htim: TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Starts the TIM One Pulse signal generation.
-  * @param  htim : TIM One Pulse handle
-  * @param  OutputChannel : TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(OutputChannel);
-
-  /* Enable the Capture compare and the Input Capture channels
-    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
-    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
-    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
-    in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
-
-    No need to enable the counter, it's enabled automatically by hardware
-    (the counter starts in response to a stimulus and generate a pulse */
-
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-
-  if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
-  {
-    /* Enable the main output */
-    __HAL_TIM_MOE_ENABLE(htim);
-  }
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM One Pulse signal generation.
-  * @param  htim : TIM One Pulse handle
-  * @param  OutputChannel : TIM Channels to be disable
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(OutputChannel);
-
-  /* Disable the Capture compare and the Input Capture channels
-  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
-  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
-  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
-  in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
-
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
-  if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
-  {
-    /* Disable the Main Ouput */
-    __HAL_TIM_MOE_DISABLE(htim);
-  }
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
-  * @param  htim : TIM One Pulse handle
-  * @param  OutputChannel : TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(OutputChannel);
-
-  /* Enable the Capture compare and the Input Capture channels
-    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
-    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
-    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
-    in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
-
-    No need to enable the counter, it's enabled automatically by hardware
-    (the counter starts in response to a stimulus and generate a pulse */
-
-  /* Enable the TIM Capture/Compare 1 interrupt */
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-
-  /* Enable the TIM Capture/Compare 2 interrupt */
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-
-  if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
-  {
-    /* Enable the main output */
-    __HAL_TIM_MOE_ENABLE(htim);
-  }
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
-  * @param  htim : TIM One Pulse handle
-  * @param  OutputChannel : TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(OutputChannel);
-
-  /* Disable the TIM Capture/Compare 1 interrupt */
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-
-  /* Disable the TIM Capture/Compare 2 interrupt */
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-
-  /* Disable the Capture compare and the Input Capture channels
-  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
-  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
-  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
-  in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
-  if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
-  {
-    /* Disable the Main Ouput */
-    __HAL_TIM_MOE_DISABLE(htim);
-  }
-
-  /* Disable the Peripheral */
-   __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
- *  @brief    Time Encoder functions
- *
-@verbatim
-  ==============================================================================
-                          ##### Time Encoder functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Initialize and configure the TIM Encoder.
-    (+) De-initialize the TIM Encoder.
-    (+) Start the Time Encoder.
-    (+) Stop the Time Encoder.
-    (+) Start the Time Encoder and enable interrupt.
-    (+) Stop the Time Encoder and disable interrupt.
-    (+) Start the Time Encoder and enable DMA transfer.
-    (+) Stop the Time Encoder and disable DMA transfer.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIM Encoder Interface and initialize the associated handle.
-  * @param  htim: TIM Encoder Interface handle
-  * @param  sConfig: TIM Encoder Interface configuration structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef* sConfig)
-{
-  uint32_t tmpsmcr = 0;
-  uint32_t tmpccmr1 = 0;
-  uint32_t tmpccer = 0;
-
-  /* Check the TIM handle allocation */
-  if(htim == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
-  assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
-  assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
-  assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
-  assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
-  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
-  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
-  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
-  assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
-
-  if(htim->State == HAL_TIM_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    htim->Lock = HAL_UNLOCKED;
-
-    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
-    HAL_TIM_Encoder_MspInit(htim);
-  }
-
-  /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;
-
-  /* Reset the SMS bits */
-  htim->Instance->SMCR &= ~TIM_SMCR_SMS;
-
-  /* Configure the Time base in the Encoder Mode */
-  TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
-  /* Get the TIMx SMCR register value */
-  tmpsmcr = htim->Instance->SMCR;
-
-  /* Get the TIMx CCMR1 register value */
-  tmpccmr1 = htim->Instance->CCMR1;
-
-  /* Get the TIMx CCER register value */
-  tmpccer = htim->Instance->CCER;
-
-  /* Set the encoder Mode */
-  tmpsmcr |= sConfig->EncoderMode;
-
-  /* Select the Capture Compare 1 and the Capture Compare 2 as input */
-  tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
-  tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
-
-  /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
-  tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
-  tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
-  tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);
-  tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);
-
-  /* Set the TI1 and the TI2 Polarities */
-  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
-  tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
-  tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);
-
-  /* Write to TIMx SMCR */
-  htim->Instance->SMCR = tmpsmcr;
-
-  /* Write to TIMx CCMR1 */
-  htim->Instance->CCMR1 = tmpccmr1;
-
-  /* Write to TIMx CCER */
-  htim->Instance->CCER = tmpccer;
-
-  /* Initialize the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  DeInitialize the TIM Encoder interface
-  * @param  htim: TIM Encoder handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Disable the TIM Peripheral Clock */
-  __HAL_TIM_DISABLE(htim);
-
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
-  HAL_TIM_Encoder_MspDeInit(htim);
-
-  /* Change TIM state */
-  htim->State = HAL_TIM_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM Encoder Interface MSP.
-  * @param  htim: TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_Encoder_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitialize TIM Encoder Interface MSP.
-  * @param  htim: TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Starts the TIM Encoder Interface.
-  * @param  htim : TIM Encoder Interface handle
-  * @param  Channel : TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-  /* Enable the encoder interface channels */
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-      break;
-  }
-    case TIM_CHANNEL_2:
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-      break;
-  }
-    default :
-  {
-     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-     break;
-    }
-  }
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Encoder Interface.
-  * @param  htim : TIM Encoder Interface handle
-  * @param  Channel : TIM Channels to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-    assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-   /* Disable the Input Capture channels 1 and 2
-    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-  {
-     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-      break;
-  }
-    case TIM_CHANNEL_2:
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-      break;
-  }
-    default :
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-     break;
-    }
-  }
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Encoder Interface in interrupt mode.
-  * @param  htim : TIM Encoder Interface handle
-  * @param  Channel : TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-  /* Enable the encoder interface channels */
-  /* Enable the capture compare Interrupts 1 and/or 2 */
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-    __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-      break;
-  }
-    case TIM_CHANNEL_2:
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-    __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-      break;
-  }
-    default :
-  {
-     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-     __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-     __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-     break;
-    }
-  }
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Encoder Interface in interrupt mode.
-  * @param  htim : TIM Encoder Interface handle
-  * @param  Channel : TIM Channels to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-  /* Disable the Input Capture channels 1 and 2
-    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
-  if(Channel == TIM_CHANNEL_1)
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
-    /* Disable the capture compare Interrupts 1 */
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-  }
-  else if(Channel == TIM_CHANNEL_2)
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
-    /* Disable the capture compare Interrupts 2 */
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-  }
-  else
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
-    /* Disable the capture compare Interrupts 1 and 2 */
-    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-  }
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Change the htim state */
-  htim->State = HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Encoder Interface in DMA mode.
-  * @param  htim : TIM Encoder Interface handle
-  * @param  Channel : TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
-  * @param  pData1: The destination Buffer address for IC1.
-  * @param  pData2: The destination Buffer address for IC2.
-  * @param  Length: The length of data to be transferred from TIM peripheral to memory.
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-
-  if((htim->State == HAL_TIM_STATE_BUSY))
-  {
-     return HAL_BUSY;
-  }
-  else if((htim->State == HAL_TIM_STATE_READY))
-  {
-    if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      htim->State = HAL_TIM_STATE_BUSY;
-    }
-  }
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
-
-      /* Enable the TIM Input Capture DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-
-      /* Enable the Peripheral */
-      __HAL_TIM_ENABLE(htim);
-
-      /* Enable the Capture compare channel */
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
-
-      /* Enable the TIM Input Capture  DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-
-      /* Enable the Peripheral */
-      __HAL_TIM_ENABLE(htim);
-
-      /* Enable the Capture compare channel */
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-    }
-    break;
-
-    case TIM_CHANNEL_ALL:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
-
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
-
-     /* Enable the Peripheral */
-      __HAL_TIM_ENABLE(htim);
-
-      /* Enable the Capture compare channel */
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-
-      /* Enable the TIM Input Capture  DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-      /* Enable the TIM Input Capture  DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-    }
-    break;
-
-    default:
-    break;
-  }
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Encoder Interface in DMA mode.
-  * @param  htim : TIM Encoder Interface handle
-  * @param  Channel : TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-
-  /* Disable the Input Capture channels 1 and 2
-    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
-  if(Channel == TIM_CHANNEL_1)
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
-    /* Disable the capture compare DMA Request 1 */
-    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-  }
-  else if(Channel == TIM_CHANNEL_2)
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
-    /* Disable the capture compare DMA Request 2 */
-    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
-  }
-  else
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
-    /* Disable the capture compare DMA Request 1 and 2 */
-    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
-  }
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Change the htim state */
-  htim->State = HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
- *  @brief    IRQ handler management
- *
-@verbatim
-  ==============================================================================
-                        ##### IRQ handler management #####
-  ==============================================================================
-  [..]
-    This section provides Timer IRQ handler function.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  This function handles TIM interrupts requests.
-  * @param  htim: TIM  handle
-  * @retval None
-  */
-void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
-{
-  /* Capture compare 1 event */
-  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
-  {
-    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
-    {
-      {
-        __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
-        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-
-        /* Input capture event */
-        if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
-        {
-          HAL_TIM_IC_CaptureCallback(htim);
-        }
-        /* Output compare event */
-        else
-        {
-          HAL_TIM_OC_DelayElapsedCallback(htim);
-          HAL_TIM_PWM_PulseFinishedCallback(htim);
-        }
-        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-      }
-    }
-  }
-  /* Capture compare 2 event */
-  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
-  {
-    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
-    {
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-      /* Input capture event */
-      if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
-      {
-        HAL_TIM_IC_CaptureCallback(htim);
-      }
-      /* Output compare event */
-      else
-      {
-        HAL_TIM_OC_DelayElapsedCallback(htim);
-        HAL_TIM_PWM_PulseFinishedCallback(htim);
-      }
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-    }
-  }
-  /* Capture compare 3 event */
-  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
-  {
-    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
-    {
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-      /* Input capture event */
-      if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
-      {
-        HAL_TIM_IC_CaptureCallback(htim);
-      }
-      /* Output compare event */
-      else
-      {
-        HAL_TIM_OC_DelayElapsedCallback(htim);
-        HAL_TIM_PWM_PulseFinishedCallback(htim);
-      }
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-    }
-  }
-  /* Capture compare 4 event */
-  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
-  {
-    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
-    {
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-      /* Input capture event */
-      if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
-      {
-        HAL_TIM_IC_CaptureCallback(htim);
-      }
-      /* Output compare event */
-      else
-      {
-        HAL_TIM_OC_DelayElapsedCallback(htim);
-        HAL_TIM_PWM_PulseFinishedCallback(htim);
-      }
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-    }
-  }
-  /* TIM Update event */
-  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
-  {
-    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
-    {
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
-      HAL_TIM_PeriodElapsedCallback(htim);
-    }
-  }
-  /* TIM Break input event */
-  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
-  {
-    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
-    {
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
-      HAL_TIMEx_BreakCallback(htim);
-    }
-  }
-  /* TIM Trigger detection event */
-  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
-  {
-    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
-    {
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
-      HAL_TIM_TriggerCallback(htim);
-    }
-  }
-  /* TIM commutation event */
-  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
-  {
-    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
-    {
-      __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
-      HAL_TIMEx_CommutationCallback(htim);
-    }
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
- *  @brief   	Peripheral Control functions
- *
-@verbatim
-  ==============================================================================
-                   ##### Peripheral Control functions #####
-  ==============================================================================
- [..]
-   This section provides functions allowing to:
-      (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
-      (+) Configure External Clock source.
-      (+) Configure Complementary channels, break features and dead time.
-      (+) Configure Master and the Slave synchronization.
-      (+) Configure the DMA Burst Mode.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the TIM Output Compare Channels according to the specified
-  *         parameters in the TIM_OC_InitTypeDef.
-  * @param  htim: TIM Output Compare handle
-  * @param  sConfig: TIM Output Compare configuration structure
-  * @param  Channel : TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
-  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
-  * @retval HAL status
-  */
-__weak HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CHANNELS(Channel));
-  assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
-  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
-
-  /* Check input state */
-  __HAL_LOCK(htim);
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-      /* Configure the TIM Channel 1 in Output Compare */
-      TIM_OC1_SetConfig(htim->Instance, sConfig);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-      /* Configure the TIM Channel 2 in Output Compare */
-      TIM_OC2_SetConfig(htim->Instance, sConfig);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-      /* Configure the TIM Channel 3 in Output Compare */
-      TIM_OC3_SetConfig(htim->Instance, sConfig);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-       /* Configure the TIM Channel 4 in Output Compare */
-       TIM_OC4_SetConfig(htim->Instance, sConfig);
-    }
-    break;
-
-    default:
-    break;
-  }
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM Input Capture Channels according to the specified
-  *         parameters in the TIM_IC_InitTypeDef.
-  * @param  htim: TIM IC handle
-  * @param  sConfig: TIM Input Capture configuration structure
-  * @param  Channel : TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
-  assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
-  assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
-  assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
-
-  __HAL_LOCK(htim);
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  if (Channel == TIM_CHANNEL_1)
-  {
-    /* TI1 Configuration */
-    TIM_TI1_SetConfig(htim->Instance,
-               sConfig->ICPolarity,
-               sConfig->ICSelection,
-               sConfig->ICFilter);
-
-    /* Reset the IC1PSC Bits */
-    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
-
-    /* Set the IC1PSC value */
-    htim->Instance->CCMR1 |= sConfig->ICPrescaler;
-  }
-  else if (Channel == TIM_CHANNEL_2)
-  {
-    /* TI2 Configuration */
-    assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-    TIM_TI2_SetConfig(htim->Instance,
-                      sConfig->ICPolarity,
-                      sConfig->ICSelection,
-                      sConfig->ICFilter);
-
-    /* Reset the IC2PSC Bits */
-    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
-
-    /* Set the IC2PSC value */
-    htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);
-  }
-  else if (Channel == TIM_CHANNEL_3)
-  {
-    /* TI3 Configuration */
-    assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
-    TIM_TI3_SetConfig(htim->Instance,
-               sConfig->ICPolarity,
-               sConfig->ICSelection,
-               sConfig->ICFilter);
-
-    /* Reset the IC3PSC Bits */
-    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
-
-    /* Set the IC3PSC value */
-    htim->Instance->CCMR2 |= sConfig->ICPrescaler;
-  }
-  else
-  {
-    /* TI4 Configuration */
-    assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
-    TIM_TI4_SetConfig(htim->Instance,
-               sConfig->ICPolarity,
-               sConfig->ICSelection,
-               sConfig->ICFilter);
-
-    /* Reset the IC4PSC Bits */
-    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
-
-    /* Set the IC4PSC value */
-    htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);
-  }
-
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM PWM  channels according to the specified
-  *         parameters in the TIM_OC_InitTypeDef.
-  * @param  htim: TIM handle
-  * @param  sConfig: TIM PWM configuration structure
-  * @param  Channel : TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-__weak HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
-{
-  __HAL_LOCK(htim);
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CHANNELS(Channel));
-  assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
-  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
-  assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-      /* Configure the Channel 1 in PWM mode */
-      TIM_OC1_SetConfig(htim->Instance, sConfig);
-
-      /* Set the Preload enable bit for channel1 */
-      htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
-
-      /* Configure the Output Fast mode */
-      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
-      htim->Instance->CCMR1 |= sConfig->OCFastMode;
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-      /* Configure the Channel 2 in PWM mode */
-      TIM_OC2_SetConfig(htim->Instance, sConfig);
-
-      /* Set the Preload enable bit for channel2 */
-      htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
-
-      /* Configure the Output Fast mode */
-      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
-      htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-      /* Configure the Channel 3 in PWM mode */
-      TIM_OC3_SetConfig(htim->Instance, sConfig);
-
-      /* Set the Preload enable bit for channel3 */
-      htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
-
-     /* Configure the Output Fast mode */
-      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
-      htim->Instance->CCMR2 |= sConfig->OCFastMode;
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-      /* Configure the Channel 4 in PWM mode */
-      TIM_OC4_SetConfig(htim->Instance, sConfig);
-
-      /* Set the Preload enable bit for channel4 */
-      htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
-
-     /* Configure the Output Fast mode */
-      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
-      htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM One Pulse Channels according to the specified
-  *         parameters in the TIM_OnePulse_InitTypeDef.
-  * @param  htim: TIM One Pulse handle
-  * @param  sConfig: TIM One Pulse configuration structure
-  * @param  OutputChannel : TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @param  InputChannel : TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel,  uint32_t InputChannel)
-{
-  TIM_OC_InitTypeDef temp1;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
-  assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
-
-  if(OutputChannel != InputChannel)
-  {
-  __HAL_LOCK(htim);
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Extract the Ouput compare configuration from sConfig structure */
-  temp1.OCMode = sConfig->OCMode;
-  temp1.Pulse = sConfig->Pulse;
-  temp1.OCPolarity = sConfig->OCPolarity;
-  temp1.OCNPolarity = sConfig->OCNPolarity;
-  temp1.OCIdleState = sConfig->OCIdleState;
-  temp1.OCNIdleState = sConfig->OCNIdleState;
-
-    switch (OutputChannel)
-  {
-    case TIM_CHANNEL_1:
-    {
-        assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
-      TIM_OC1_SetConfig(htim->Instance, &temp1);
-    }
-    break;
-    case TIM_CHANNEL_2:
-    {
-        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-      TIM_OC2_SetConfig(htim->Instance, &temp1);
-    }
-    break;
-    default:
-    break;
-  }
-    switch (InputChannel)
-  {
-    case TIM_CHANNEL_1:
-    {
-        assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
-      TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
-                        sConfig->ICSelection, sConfig->ICFilter);
-
-    /* Reset the IC1PSC Bits */
-    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
-
-    /* Select the Trigger source */
-        htim->Instance->SMCR &= ~TIM_SMCR_TS;
-    htim->Instance->SMCR |= TIM_TS_TI1FP1;
-
-    /* Select the Slave Mode */
-        htim->Instance->SMCR &= ~TIM_SMCR_SMS;
-    htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
-    }
-    break;
-    case TIM_CHANNEL_2:
-    {
-        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-      TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
-                 sConfig->ICSelection, sConfig->ICFilter);
-
-      /* Reset the IC2PSC Bits */
-        htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
-
-      /* Select the Trigger source */
-        htim->Instance->SMCR &= ~TIM_SMCR_TS;
-      htim->Instance->SMCR |= TIM_TS_TI2FP2;
-
-      /* Select the Slave Mode */
-        htim->Instance->SMCR &= ~TIM_SMCR_SMS;
-      htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-  else
-  {
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
-  * @param  htim: TIM handle
-  * @param  BurstBaseAddress: TIM Base address from when the DMA will starts the Data write
-  *         This parameters can be on of the following values:
-  *            @arg TIM_DMABASE_CR1
-  *            @arg TIM_DMABASE_CR2
-  *            @arg TIM_DMABASE_SMCR
-  *            @arg TIM_DMABASE_DIER
-  *            @arg TIM_DMABASE_SR
-  *            @arg TIM_DMABASE_EGR
-  *            @arg TIM_DMABASE_CCMR1
-  *            @arg TIM_DMABASE_CCMR2
-  *            @arg TIM_DMABASE_CCER
-  *            @arg TIM_DMABASE_CNT
-  *            @arg TIM_DMABASE_PSC
-  *            @arg TIM_DMABASE_ARR
-  *            @arg TIM_DMABASE_RCR
-  *            @arg TIM_DMABASE_CCR1
-  *            @arg TIM_DMABASE_CCR2
-  *            @arg TIM_DMABASE_CCR3
-  *            @arg TIM_DMABASE_CCR4
-  *            @arg TIM_DMABASE_BDTR
-  *            @arg TIM_DMABASE_DCR
-  * @param  BurstRequestSrc: TIM DMA Request sources
-  *         This parameters can be on of the following values:
-  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
-  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
-  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
-  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
-  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
-  *            @arg TIM_DMA_COM: TIM Commutation DMA source
-  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
-  * @param  BurstBuffer: The Buffer address.
-  * @param  BurstLength: DMA Burst length. This parameter can be one value
-  *         between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
-                                              uint32_t* BurstBuffer, uint32_t  BurstLength)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
-  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
-  assert_param(IS_TIM_DMA_LENGTH(BurstLength));
-
-  if((htim->State == HAL_TIM_STATE_BUSY))
-  {
-     return HAL_BUSY;
-  }
-  else if((htim->State == HAL_TIM_STATE_READY))
-  {
-    if((BurstBuffer == 0 ) && (BurstLength > 0))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      htim->State = HAL_TIM_STATE_BUSY;
-    }
-  }
-  switch(BurstRequestSrc)
-  {
-    case TIM_DMA_UPDATE:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
-    }
-    break;
-    case TIM_DMA_CC1:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback =  TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
-    }
-    break;
-    case TIM_DMA_CC2:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback =  TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
-    }
-    break;
-    case TIM_DMA_CC3:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback =  TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
-    }
-    break;
-    case TIM_DMA_CC4:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback =  TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
-    }
-    break;
-    case TIM_DMA_COM:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
-    }
-    break;
-    case TIM_DMA_TRIGGER:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
-    }
-    break;
-    default:
-    break;
-  }
-   /* configure the DMA Burst Mode */
-   htim->Instance->DCR = BurstBaseAddress | BurstLength;
-
-   /* Enable the TIM DMA Request */
-   __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
-
-   htim->State = HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM DMA Burst mode
-  * @param  htim: TIM handle
-  * @param  BurstRequestSrc: TIM DMA Request sources to disable
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
-
-  /* Abort the DMA transfer (at least disable the DMA channel) */
-  switch(BurstRequestSrc)
-  {
-    case TIM_DMA_UPDATE:
-    {
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
-    }
-    break;
-    case TIM_DMA_CC1:
-    {
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
-    }
-    break;
-    case TIM_DMA_CC2:
-    {
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
-    }
-    break;
-    case TIM_DMA_CC3:
-    {
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
-    }
-    break;
-    case TIM_DMA_CC4:
-    {
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
-    }
-    break;
-    case TIM_DMA_COM:
-    {
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
-    }
-    break;
-    case TIM_DMA_TRIGGER:
-    {
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
-    }
-    break;
-    default:
-    break;
-  }
-
-  /* Disable the TIM Update DMA request */
-  __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
-  * @param  htim: TIM handle
-  * @param  BurstBaseAddress: TIM Base address from when the DMA will starts the Data read
-  *         This parameters can be on of the following values:
-  *            @arg TIM_DMABASE_CR1
-  *            @arg TIM_DMABASE_CR2
-  *            @arg TIM_DMABASE_SMCR
-  *            @arg TIM_DMABASE_DIER
-  *            @arg TIM_DMABASE_SR
-  *            @arg TIM_DMABASE_EGR
-  *            @arg TIM_DMABASE_CCMR1
-  *            @arg TIM_DMABASE_CCMR2
-  *            @arg TIM_DMABASE_CCER
-  *            @arg TIM_DMABASE_CNT
-  *            @arg TIM_DMABASE_PSC
-  *            @arg TIM_DMABASE_ARR
-  *            @arg TIM_DMABASE_RCR
-  *            @arg TIM_DMABASE_CCR1
-  *            @arg TIM_DMABASE_CCR2
-  *            @arg TIM_DMABASE_CCR3
-  *            @arg TIM_DMABASE_CCR4
-  *            @arg TIM_DMABASE_BDTR
-  *            @arg TIM_DMABASE_DCR
-  * @param  BurstRequestSrc: TIM DMA Request sources
-  *         This parameters can be on of the following values:
-  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
-  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
-  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
-  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
-  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
-  *            @arg TIM_DMA_COM: TIM Commutation DMA source
-  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
-  * @param  BurstBuffer: The Buffer address.
-  * @param  BurstLength: DMA Burst length. This parameter can be one value
-  *         between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
-                                             uint32_t  *BurstBuffer, uint32_t  BurstLength)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
-  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
-  assert_param(IS_TIM_DMA_LENGTH(BurstLength));
-
-  if((htim->State == HAL_TIM_STATE_BUSY))
-  {
-     return HAL_BUSY;
-  }
-  else if((htim->State == HAL_TIM_STATE_READY))
-  {
-    if((BurstBuffer == 0 ) && (BurstLength > 0))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      htim->State = HAL_TIM_STATE_BUSY;
-    }
-  }
-  switch(BurstRequestSrc)
-  {
-    case TIM_DMA_UPDATE:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
-    }
-    break;
-    case TIM_DMA_CC1:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback =  TIM_DMACaptureCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
-    }
-    break;
-    case TIM_DMA_CC2:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback =  TIM_DMACaptureCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
-    }
-    break;
-    case TIM_DMA_CC3:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback =  TIM_DMACaptureCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
-    }
-    break;
-    case TIM_DMA_CC4:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback =  TIM_DMACaptureCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
-    }
-    break;
-    case TIM_DMA_COM:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
-    }
-    break;
-    case TIM_DMA_TRIGGER:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
-    }
-    break;
-    default:
-    break;
-  }
-
-  /* configure the DMA Burst Mode */
-  htim->Instance->DCR = BurstBaseAddress | BurstLength;
-
-  /* Enable the TIM DMA Request */
-  __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
-
-  htim->State = HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stop the DMA burst reading
-  * @param  htim: TIM handle
-  * @param  BurstRequestSrc: TIM DMA Request sources to disable.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
-
-  /* Abort the DMA transfer (at least disable the DMA channel) */
-  switch(BurstRequestSrc)
-  {
-    case TIM_DMA_UPDATE:
-    {
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
-    }
-    break;
-    case TIM_DMA_CC1:
-    {
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
-    }
-    break;
-    case TIM_DMA_CC2:
-    {
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
-    }
-    break;
-    case TIM_DMA_CC3:
-    {
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
-    }
-    break;
-    case TIM_DMA_CC4:
-    {
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
-    }
-    break;
-    case TIM_DMA_COM:
-    {
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
-    }
-    break;
-    case TIM_DMA_TRIGGER:
-    {
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
-    }
-    break;
-    default:
-    break;
-  }
-
-  /* Disable the TIM Update DMA request */
-  __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Generate a software event
-  * @param  htim: TIM handle
-  * @param  EventSource: specifies the event source.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
-  *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
-  *            @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
-  *            @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
-  *            @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
-  *            @arg TIM_EVENTSOURCE_COM: Timer COM event source
-  *            @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
-  *            @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
-  *            @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
-  * @retval None
-  */
-
-HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_EVENT_SOURCE(EventSource));
-
-  /* Process Locked */
-  __HAL_LOCK(htim);
-
-  /* Change the TIM state */
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Set the event sources */
-  htim->Instance->EGR = EventSource;
-
-  /* Change the TIM state */
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the OCRef clear feature
-  * @param  htim: TIM handle
-  * @param  sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
-  *         contains the OCREF clear feature and parameters for the TIM peripheral.
-  * @param  Channel: specifies the TIM Channel
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1
-  *            @arg TIM_CHANNEL_2: TIM Channel 2
-  *            @arg TIM_CHANNEL_3: TIM Channel 3
-  *            @arg TIM_CHANNEL_4: TIM Channel 4
-  * @retval HAL status
-  */
-__weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_CHANNELS(Channel));
-  assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
-
-  /* Process Locked */
-  __HAL_LOCK(htim);
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
-  {
-    /* Check the parameters */
-    assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
-    assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
-    assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
-
-    TIM_ETR_SetConfig(htim->Instance,
-                      sClearInputConfig->ClearInputPrescaler,
-                      sClearInputConfig->ClearInputPolarity,
-                      sClearInputConfig->ClearInputFilter);
-  }
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      if(sClearInputConfig->ClearInputState != RESET)
-      {
-      /* Enable the OCREF clear feature for Channel 1 */
-      htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
-      }
-      else
-      {
-        /* Disable the OCREF clear feature for Channel 1 */
-        htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
-      }
-    }
-    break;
-    case TIM_CHANNEL_2:
-    {
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-      if(sClearInputConfig->ClearInputState != RESET)
-      {
-      /* Enable the OCREF clear feature for Channel 2 */
-      htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
-      }
-      else
-      {
-        /* Disable the OCREF clear feature for Channel 2 */
-        htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
-      }
-    }
-    break;
-    case TIM_CHANNEL_3:
-    {
-      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-      if(sClearInputConfig->ClearInputState != RESET)
-      {
-      /* Enable the OCREF clear feature for Channel 3 */
-      htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
-      }
-      else
-      {
-        /* Disable the OCREF clear feature for Channel 3 */
-        htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
-      }
-    }
-    break;
-    case TIM_CHANNEL_4:
-    {
-      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-      if(sClearInputConfig->ClearInputState != RESET)
-      {
-      /* Enable the OCREF clear feature for Channel 4 */
-      htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
-      }
-      else
-      {
-        /* Disable the OCREF clear feature for Channel 4 */
-        htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
-      }
-    }
-    break;
-    default:
-    break;
-  }
-
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief   Configures the clock source to be used
-  * @param  htim: TIM handle
-  * @param  sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
-  *         contains the clock source information for the TIM peripheral.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
-{
-  uint32_t tmpsmcr = 0;
-
-  /* Process Locked */
-  __HAL_LOCK(htim);
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
-
-  /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
-  tmpsmcr = htim->Instance->SMCR;
-  tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
-  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
-  htim->Instance->SMCR = tmpsmcr;
-
-  switch (sClockSourceConfig->ClockSource)
-  {
-  case TIM_CLOCKSOURCE_INTERNAL:
-    {
-      assert_param(IS_TIM_INSTANCE(htim->Instance));
-      /* Disable slave mode to clock the prescaler directly with the internal clock */
-      htim->Instance->SMCR &= ~TIM_SMCR_SMS;
-    }
-    break;
-
-  case TIM_CLOCKSOURCE_ETRMODE1:
-    {
-      /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
-      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
-
-      /* Check ETR input conditioning related parameters */
-      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
-      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
-      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-      
-      /* Configure the ETR Clock source */
-      TIM_ETR_SetConfig(htim->Instance,
-                        sClockSourceConfig->ClockPrescaler,
-                        sClockSourceConfig->ClockPolarity,
-                        sClockSourceConfig->ClockFilter);
-      /* Get the TIMx SMCR register value */
-      tmpsmcr = htim->Instance->SMCR;
-      /* Reset the SMS and TS Bits */
-      tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
-      /* Select the External clock mode1 and the ETRF trigger */
-      tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
-      /* Write to TIMx SMCR */
-      htim->Instance->SMCR = tmpsmcr;
-    }
-    break;
-
-  case TIM_CLOCKSOURCE_ETRMODE2:
-    {
-      /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
-      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
-
-      /* Check ETR input conditioning related parameters */
-      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
-      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
-      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-      
-      /* Configure the ETR Clock source */
-      TIM_ETR_SetConfig(htim->Instance,
-                        sClockSourceConfig->ClockPrescaler,
-                        sClockSourceConfig->ClockPolarity,
-                        sClockSourceConfig->ClockFilter);
-      /* Enable the External clock mode2 */
-      htim->Instance->SMCR |= TIM_SMCR_ECE;
-    }
-    break;
-
-  case TIM_CLOCKSOURCE_TI1:
-    {
-      /* Check whether or not the timer instance supports external clock mode 1 */
-      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
-
-      /* Check TI1 input conditioning related parameters */
-      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
-      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-      
-      TIM_TI1_ConfigInputStage(htim->Instance,
-                               sClockSourceConfig->ClockPolarity,
-                               sClockSourceConfig->ClockFilter);
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
-    }
-    break;
-    
-  case TIM_CLOCKSOURCE_TI2:
-    {
-      /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
-      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
-
-       /* Check TI2 input conditioning related parameters */
-      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
-      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
-      TIM_TI2_ConfigInputStage(htim->Instance,
-                               sClockSourceConfig->ClockPolarity,
-                               sClockSourceConfig->ClockFilter);
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
-    }
-    break;
-
-  case TIM_CLOCKSOURCE_TI1ED:
-    {
-      /* Check whether or not the timer instance supports external clock mode 1 */
-      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
-
-      /* Check TI1 input conditioning related parameters */
-      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
-      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
-      TIM_TI1_ConfigInputStage(htim->Instance,
-                               sClockSourceConfig->ClockPolarity,
-                               sClockSourceConfig->ClockFilter);
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
-    }
-    break;
-    
-  case TIM_CLOCKSOURCE_ITR0:
-    {
-      /* Check whether or not the timer instance supports internal trigger input */
-      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
-
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
-    }
-    break;
-    
-  case TIM_CLOCKSOURCE_ITR1:
-    {
-      /* Check whether or not the timer instance supports internal trigger input */
-      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
-
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
-    }
-    break;
-    
-  case TIM_CLOCKSOURCE_ITR2:
-    {
-      /* Check whether or not the timer instance supports internal trigger input */
-      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
-
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
-    }
-    break;
-    
-  case TIM_CLOCKSOURCE_ITR3:
-    {
-      /* Check whether or not the timer instance supports internal trigger input */
-      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
-
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
-    }
-    break;
-
-  default:
-    break;
-  }
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
-  *         or a XOR combination between CH1_input, CH2_input & CH3_input
-  * @param  htim: TIM handle.
-  * @param  TI1_Selection: Indicate whether or not channel 1 is connected to the
-  *         output of a XOR gate.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
-  *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
-  *            pins are connected to the TI1 input (XOR combination)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
-{
-  uint32_t tmpcr2 = 0;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
-
-  /* Get the TIMx CR2 register value */
-  tmpcr2 = htim->Instance->CR2;
-
-  /* Reset the TI1 selection */
-  tmpcr2 &= ~TIM_CR2_TI1S;
-
-  /* Set the TI1 selection */
-  tmpcr2 |= TI1_Selection;
-
-  /* Write to TIMxCR2 */
-  htim->Instance->CR2 = tmpcr2;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the TIM in Slave mode
-  * @param  htim: TIM handle.
-  * @param  sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
-  *         contains the selected trigger (internal trigger input, filtered
-  *         timer input or external trigger input) and the ) and the Slave
-  *         mode (Disable, Reset, Gated, Trigger, External clock mode 1).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
-  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
-
-  __HAL_LOCK(htim);
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
-  
-  /* Disable Trigger Interrupt */
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
-
-  /* Disable Trigger DMA request */
-  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
-
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);  
-
-  return HAL_OK;
-    }
-
-/**
-  * @brief  Configures the TIM in Slave mode in interrupt mode
-  * @param  htim: TIM handle.
-  * @param  sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
-  *         contains the selected trigger (internal trigger input, filtered
-  *         timer input or external trigger input) and the ) and the Slave 
-  *         mode (Disable, Reset, Gated, Trigger, External clock mode 1). 
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, 
-                                                        TIM_SlaveConfigTypeDef * sSlaveConfig)
-    {
-      /* Check the parameters */
-  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
-  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
-  
-  __HAL_LOCK(htim);
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
-
-  /* Enable Trigger Interrupt */
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
-
-  /* Disable Trigger DMA request */
-  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
-
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);  
-
-  return HAL_OK;
-    }
-
-/**
-  * @brief  Read the captured value from Capture Compare unit
-  * @param  htim: TIM handle.
-  * @param  Channel : TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval Captured value
-  */
-uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  uint32_t tmpreg = 0;
-
-  __HAL_LOCK(htim);
-
-  switch (Channel)
-  {
-  case TIM_CHANNEL_1:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
-      /* Return the capture 1 value */
-      tmpreg =  htim->Instance->CCR1;
-
-      break;
-    }
-  case TIM_CHANNEL_2:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-      /* Return the capture 2 value */
-      tmpreg =   htim->Instance->CCR2;
-
-      break;
-    }
-
-  case TIM_CHANNEL_3:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
-      /* Return the capture 3 value */
-      tmpreg =   htim->Instance->CCR3;
-
-      break;
-    }
-
-  case TIM_CHANNEL_4:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
-      /* Return the capture 4 value */
-      tmpreg =   htim->Instance->CCR4;
-
-      break;
-    }
-
-  default:
-    break;
-  }
-
-  __HAL_UNLOCK(htim);
-  return tmpreg;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
- *  @brief    TIM Callbacks functions
- *
-@verbatim
-  ==============================================================================
-                        ##### TIM Callbacks functions #####
-  ==============================================================================
- [..]
-   This section provides TIM callback functions:
-   (+) Timer Period elapsed callback
-   (+) Timer Output Compare callback
-   (+) Timer Input capture callback
-   (+) Timer Trigger callback
-   (+) Timer Error callback
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Period elapsed callback in non-blocking mode
-  * @param  htim : TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
-   */
-
-}
-/**
-  * @brief  Output Compare callback in non-blocking mode
-  * @param  htim : TIM OC handle
-  * @retval None
-  */
-__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
-   */
-}
-/**
-  * @brief  Input Capture callback in non-blocking mode
-  * @param  htim : TIM IC handle
-  * @retval None
-  */
-__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  PWM Pulse finished callback in non-blocking mode
-  * @param  htim : TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Hall Trigger detection callback in non-blocking mode
-  * @param  htim : TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_TriggerCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Timer error callback in non-blocking mode
-  * @param  htim : TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_ErrorCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
- *  @brief   Peripheral State functions
- *
-@verbatim
-  ==============================================================================
-                        ##### Peripheral State functions #####
-  ==============================================================================
-    [..]
-    This subsection permits to get in run-time the status of the peripheral
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the TIM Base handle state.
-  * @param  htim: TIM Base handle
-  * @retval HAL state
-  */
-HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
-{
-  return htim->State;
-}
-
-/**
-  * @brief  Return the TIM OC handle state.
-  * @param  htim: TIM Ouput Compare handle
-  * @retval HAL state
-  */
-HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
-{
-  return htim->State;
-}
-
-/**
-  * @brief  Return the TIM PWM handle state.
-  * @param  htim: TIM handle
-  * @retval HAL state
-  */
-HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
-{
-  return htim->State;
-}
-
-/**
-  * @brief  Return the TIM Input Capture handle state.
-  * @param  htim: TIM IC handle
-  * @retval HAL state
-  */
-HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
-{
-  return htim->State;
-}
-
-/**
-  * @brief  Return the TIM One Pulse Mode handle state.
-  * @param  htim: TIM OPM handle
-  * @retval HAL state
-  */
-HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
-{
-  return htim->State;
-}
-
-/**
-  * @brief  Return the TIM Encoder Mode handle state.
-  * @param  htim: TIM Encoder handle
-  * @retval HAL state
-  */
-HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
-{
-  return htim->State;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @brief  TIM DMA error callback
-  * @param  hdma : pointer to DMA handle.
-  * @retval None
-  */
-void TIM_DMAError(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  htim->State= HAL_TIM_STATE_READY;
-
-  HAL_TIM_ErrorCallback(htim);
-}
-
-/**
-  * @brief  TIM DMA Delay Pulse complete callback.
-  * @param  hdma : pointer to DMA handle.
-  * @retval None
-  */
-void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  htim->State= HAL_TIM_STATE_READY;
-
-  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-  }
-
-  HAL_TIM_PWM_PulseFinishedCallback(htim);
-
-  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-/**
-  * @brief  TIM DMA Capture complete callback.
-  * @param  hdma : pointer to DMA handle.
-  * @retval None
-  */
-void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  htim->State= HAL_TIM_STATE_READY;
-
-  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-  }
-
-  HAL_TIM_IC_CaptureCallback(htim);
-
-  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-
-/**
-  * @brief  TIM DMA Period Elapse complete callback.
-  * @param  hdma : pointer to DMA handle.
-  * @retval None
-  */
-static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  htim->State= HAL_TIM_STATE_READY;
-
-  HAL_TIM_PeriodElapsedCallback(htim);
-}
-
-/**
-  * @brief  TIM DMA Trigger callback.
-  * @param  hdma : pointer to DMA handle.
-  * @retval None
-  */
-static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  htim->State= HAL_TIM_STATE_READY;
-
-  HAL_TIM_TriggerCallback(htim);
-}
-
-/**
-  * @brief  Time Base configuration
-  * @param  TIMx: TIM peripheral
-  * @param  Structure: TIM Base configuration structure
-  * @retval None
-  */
-void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
-{
-  uint32_t tmpcr1 = 0;
-  tmpcr1 = TIMx->CR1;
-
-  /* Set TIM Time Base Unit parameters ---------------------------------------*/
-  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
-  {
-    /* Select the Counter Mode */
-    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
-    tmpcr1 |= Structure->CounterMode;
-  }
-
-  if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
-  {
-    /* Set the clock division */
-    tmpcr1 &= ~TIM_CR1_CKD;
-    tmpcr1 |= (uint32_t)Structure->ClockDivision;
-  }
-
-  TIMx->CR1 = tmpcr1;
-
-  /* Set the Autoreload value */
-  TIMx->ARR = (uint32_t)Structure->Period ;
-
-  /* Set the Prescaler value */
-  TIMx->PSC = (uint32_t)Structure->Prescaler;
-
-  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
-  {
-    /* Set the Repetition Counter value */
-    TIMx->RCR = Structure->RepetitionCounter;
-  }
-
-  /* Generate an update event to reload the Prescaler
-     and the repetition counter(only for TIM1 and TIM8) value immediately */
-  TIMx->EGR = TIM_EGR_UG;
-}
-
-/**
-  * @brief  Time Ouput Compare 1 configuration
-  * @param  TIMx to select the TIM peripheral
-  * @param  OC_Config: The ouput configuration structure
-  * @retval None
-  */
-void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
-  uint32_t tmpccmrx = 0;
-  uint32_t tmpccer = 0;
-  uint32_t tmpcr2 = 0;
-
-   /* Disable the Channel 1: Reset the CC1E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC1E;
-
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
-  /* Get the TIMx CR2 register value */
-  tmpcr2 =  TIMx->CR2;
-
-  /* Get the TIMx CCMR1 register value */
-  tmpccmrx = TIMx->CCMR1;
-
-  /* Reset the Output Compare Mode Bits */
-  tmpccmrx &= ~TIM_CCMR1_OC1M;
-  tmpccmrx &= ~TIM_CCMR1_CC1S;
-  /* Select the Output Compare Mode */
-  tmpccmrx |= OC_Config->OCMode;
-
-  /* Reset the Output Polarity level */
-  tmpccer &= ~TIM_CCER_CC1P;
-  /* Set the Output Compare Polarity */
-  tmpccer |= OC_Config->OCPolarity;
-
-  if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
-  {
-    /* Check parameters */
-    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-
-    /* Reset the Output N Polarity level */
-    tmpccer &= ~TIM_CCER_CC1NP;
-    /* Set the Output N Polarity */
-    tmpccer |= OC_Config->OCNPolarity;
-    /* Reset the Output N State */
-    tmpccer &= ~TIM_CCER_CC1NE;
-  }
-
-  if(IS_TIM_BREAK_INSTANCE(TIMx))
-  {
-    /* Check parameters */
-    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
-    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
-    /* Reset the Output Compare and Output Compare N IDLE State */
-    tmpcr2 &= ~TIM_CR2_OIS1;
-    tmpcr2 &= ~TIM_CR2_OIS1N;
-    /* Set the Output Idle state */
-    tmpcr2 |= OC_Config->OCIdleState;
-    /* Set the Output N Idle state */
-    tmpcr2 |= OC_Config->OCNIdleState;
-  }
-  /* Write to TIMx CR2 */
-  TIMx->CR2 = tmpcr2;
-
-  /* Write to TIMx CCMR1 */
-  TIMx->CCMR1 = tmpccmrx;
-
-  /* Set the Capture Compare Register value */
-  TIMx->CCR1 = OC_Config->Pulse;
-
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Time Ouput Compare 2 configuration
-  * @param  TIMx to select the TIM peripheral
-  * @param  OC_Config: The ouput configuration structure
-  * @retval None
-  */
-void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
-  uint32_t tmpccmrx = 0;
-  uint32_t tmpccer = 0;
-  uint32_t tmpcr2 = 0;
-
-  /* Disable the Channel 2: Reset the CC2E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC2E;
-
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
-  /* Get the TIMx CR2 register value */
-  tmpcr2 =  TIMx->CR2;
-
-  /* Get the TIMx CCMR1 register value */
-  tmpccmrx = TIMx->CCMR1;
-
-  /* Reset the Output Compare mode and Capture/Compare selection Bits */
-  tmpccmrx &= ~TIM_CCMR1_OC2M;
-  tmpccmrx &= ~TIM_CCMR1_CC2S;
-
-  /* Select the Output Compare Mode */
-  tmpccmrx |= (OC_Config->OCMode << 8);
-
-  /* Reset the Output Polarity level */
-  tmpccer &= ~TIM_CCER_CC2P;
-  /* Set the Output Compare Polarity */
-  tmpccer |= (OC_Config->OCPolarity << 4);
-
-  if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
-  {
-    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-
-    /* Reset the Output N Polarity level */
-    tmpccer &= ~TIM_CCER_CC2NP;
-    /* Set the Output N Polarity */
-    tmpccer |= (OC_Config->OCNPolarity << 4);
-    /* Reset the Output N State */
-    tmpccer &= ~TIM_CCER_CC2NE;
-
-  }
-
-  if(IS_TIM_BREAK_INSTANCE(TIMx))
-  {
-    /* Check parameters */
-    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
-    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
-    /* Reset the Output Compare and Output Compare N IDLE State */
-    tmpcr2 &= ~TIM_CR2_OIS2;
-    tmpcr2 &= ~TIM_CR2_OIS2N;
-    /* Set the Output Idle state */
-    tmpcr2 |= (OC_Config->OCIdleState << 2);
-    /* Set the Output N Idle state */
-    tmpcr2 |= (OC_Config->OCNIdleState << 2);
-  }
-
-  /* Write to TIMx CR2 */
-  TIMx->CR2 = tmpcr2;
-
-  /* Write to TIMx CCMR1 */
-  TIMx->CCMR1 = tmpccmrx;
-
-  /* Set the Capture Compare Register value */
-  TIMx->CCR2 = OC_Config->Pulse;
-
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Time Ouput Compare 3 configuration
-  * @param  TIMx to select the TIM peripheral
-  * @param  OC_Config: The ouput configuration structure
-  * @retval None
-  */
-void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
-  uint32_t tmpccmrx = 0;
-  uint32_t tmpccer = 0;
-  uint32_t tmpcr2 = 0;
-
-  /* Disable the Channel 3: Reset the CC2E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC3E;
-
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
-  /* Get the TIMx CR2 register value */
-  tmpcr2 =  TIMx->CR2;
-
-  /* Get the TIMx CCMR2 register value */
-  tmpccmrx = TIMx->CCMR2;
-
-  /* Reset the Output Compare mode and Capture/Compare selection Bits */
-  tmpccmrx &= ~TIM_CCMR2_OC3M;
-  tmpccmrx &= ~TIM_CCMR2_CC3S;
-  /* Select the Output Compare Mode */
-  tmpccmrx |= OC_Config->OCMode;
-
-  /* Reset the Output Polarity level */
-  tmpccer &= ~TIM_CCER_CC3P;
-  /* Set the Output Compare Polarity */
-  tmpccer |= (OC_Config->OCPolarity << 8);
-
-  if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
-  {
-    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-
-    /* Reset the Output N Polarity level */
-    tmpccer &= ~TIM_CCER_CC3NP;
-    /* Set the Output N Polarity */
-    tmpccer |= (OC_Config->OCNPolarity << 8);
-    /* Reset the Output N State */
-    tmpccer &= ~TIM_CCER_CC3NE;
-  }
-
-  if(IS_TIM_BREAK_INSTANCE(TIMx))
-  {
-    /* Check parameters */
-    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
-    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
-    /* Reset the Output Compare and Output Compare N IDLE State */
-    tmpcr2 &= ~TIM_CR2_OIS3;
-    tmpcr2 &= ~TIM_CR2_OIS3N;
-    /* Set the Output Idle state */
-    tmpcr2 |= (OC_Config->OCIdleState << 4);
-    /* Set the Output N Idle state */
-    tmpcr2 |= (OC_Config->OCNIdleState << 4);
-  }
-
-  /* Write to TIMx CR2 */
-  TIMx->CR2 = tmpcr2;
-
-  /* Write to TIMx CCMR2 */
-  TIMx->CCMR2 = tmpccmrx;
-
-  /* Set the Capture Compare Register value */
-  TIMx->CCR3 = OC_Config->Pulse;
-
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Time Ouput Compare 4 configuration
-  * @param  TIMx to select the TIM peripheral
-  * @param  OC_Config: The ouput configuration structure
-  * @retval None
-  */
-void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
-  uint32_t tmpccmrx = 0;
-  uint32_t tmpccer = 0;
-  uint32_t tmpcr2 = 0;
-
-  /* Disable the Channel 4: Reset the CC4E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC4E;
-
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
-  /* Get the TIMx CR2 register value */
-  tmpcr2 =  TIMx->CR2;
-
-  /* Get the TIMx CCMR2 register value */
-  tmpccmrx = TIMx->CCMR2;
-
-  /* Reset the Output Compare mode and Capture/Compare selection Bits */
-  tmpccmrx &= ~TIM_CCMR2_OC4M;
-  tmpccmrx &= ~TIM_CCMR2_CC4S;
-
-  /* Select the Output Compare Mode */
-  tmpccmrx |= (OC_Config->OCMode << 8);
-
-  /* Reset the Output Polarity level */
-  tmpccer &= ~TIM_CCER_CC4P;
-  /* Set the Output Compare Polarity */
-  tmpccer |= (OC_Config->OCPolarity << 12);
-
-  if(IS_TIM_BREAK_INSTANCE(TIMx))
-  {
-    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
-   /* Reset the Output Compare IDLE State */
-    tmpcr2 &= ~TIM_CR2_OIS4;
-    /* Set the Output Idle state */
-    tmpcr2 |= (OC_Config->OCIdleState << 6);
-  }
-
-  /* Write to TIMx CR2 */
-  TIMx->CR2 = tmpcr2;
-
-  /* Write to TIMx CCMR2 */
-  TIMx->CCMR2 = tmpccmrx;
-
-  /* Set the Capture Compare Register value */
-  TIMx->CCR4 = OC_Config->Pulse;
-
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
-}
-
-static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
-                                     TIM_SlaveConfigTypeDef * sSlaveConfig)
-{
-  uint32_t tmpsmcr = 0;
-  uint32_t tmpccmr1 = 0;
-  uint32_t tmpccer = 0;
-
-  /* Get the TIMx SMCR register value */
-  tmpsmcr = htim->Instance->SMCR;
-
-  /* Reset the Trigger Selection Bits */
-  tmpsmcr &= ~TIM_SMCR_TS;
-  /* Set the Input Trigger source */
-  tmpsmcr |= sSlaveConfig->InputTrigger;
-
-  /* Reset the slave mode Bits */
-  tmpsmcr &= ~TIM_SMCR_SMS;
-  /* Set the slave mode */
-  tmpsmcr |= sSlaveConfig->SlaveMode;
-
-  /* Write to TIMx SMCR */
-  htim->Instance->SMCR = tmpsmcr;
- 
-  /* Configure the trigger prescaler, filter, and polarity */
-  switch (sSlaveConfig->InputTrigger)
-  {
-  case TIM_TS_ETRF:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
-      assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
-      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
-      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-      /* Configure the ETR Trigger source */
-      TIM_ETR_SetConfig(htim->Instance, 
-                        sSlaveConfig->TriggerPrescaler, 
-                        sSlaveConfig->TriggerPolarity, 
-                        sSlaveConfig->TriggerFilter);
-    }
-    break;
-    
-  case TIM_TS_TI1F_ED:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-  
-      /* Disable the Channel 1: Reset the CC1E Bit */
-      tmpccer = htim->Instance->CCER;
-      htim->Instance->CCER &= ~TIM_CCER_CC1E;
-      tmpccmr1 = htim->Instance->CCMR1;    
-      
-      /* Set the filter */
-      tmpccmr1 &= ~TIM_CCMR1_IC1F;
-      tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
-      
-      /* Write to TIMx CCMR1 and CCER registers */
-      htim->Instance->CCMR1 = tmpccmr1;
-      htim->Instance->CCER = tmpccer;                               
-                               
-    }
-    break;
-    
-  case TIM_TS_TI1FP1:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
-      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-  
-      /* Configure TI1 Filter and Polarity */
-      TIM_TI1_ConfigInputStage(htim->Instance,
-                               sSlaveConfig->TriggerPolarity,
-                               sSlaveConfig->TriggerFilter);
-    }
-    break;
-    
-  case TIM_TS_TI2FP2:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
-      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-  
-      /* Configure TI2 Filter and Polarity */
-      TIM_TI2_ConfigInputStage(htim->Instance,
-                                sSlaveConfig->TriggerPolarity,
-                                sSlaveConfig->TriggerFilter);
-    }
-    break;
-    
-  case TIM_TS_ITR0:
-    {
-      /* Check the parameter */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-    }
-    break;
-    
-  case TIM_TS_ITR1:
-    {
-      /* Check the parameter */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-    }
-    break;
-    
-  case TIM_TS_ITR2:
-    {
-      /* Check the parameter */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-    }
-    break;
-    
-  case TIM_TS_ITR3:
-    {
-      /* Check the parameter */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-    }
-    break;
-       
-  default:
-    break;
-  }
-}
-
-/**
-  * @brief  Configure the TI1 as Input.
-  * @param  TIMx to select the TIM peripheral.
-  * @param  TIM_ICPolarity : The Input Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPolarity_Rising
-  *            @arg TIM_ICPolarity_Falling
-  *            @arg TIM_ICPolarity_BothEdge
-  * @param  TIM_ICSelection: specifies the input to be used.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
-  *            @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
-  *            @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
-  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
-  *          This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
-  *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be
-  *        protected against un-initialized filter and polarity values.
-  */
-void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                       uint32_t TIM_ICFilter)
-{
-  uint32_t tmpccmr1 = 0;
-  uint32_t tmpccer = 0;
-
-  /* Disable the Channel 1: Reset the CC1E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC1E;
-  tmpccmr1 = TIMx->CCMR1;
-  tmpccer = TIMx->CCER;
-
-  /* Select the Input */
-  if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
-  {
-    tmpccmr1 &= ~TIM_CCMR1_CC1S;
-    tmpccmr1 |= TIM_ICSelection;
-  }
-  else
-  {
-    tmpccmr1 |= TIM_CCMR1_CC1S_0;
-  }
-
-  /* Set the filter */
-  tmpccmr1 &= ~TIM_CCMR1_IC1F;
-  tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
-
-  /* Select the Polarity and set the CC1E Bit */
-  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
-  tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
-
-  /* Write to TIMx CCMR1 and CCER registers */
-  TIMx->CCMR1 = tmpccmr1;
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configure the Polarity and Filter for TI1.
-  * @param  TIMx to select the TIM peripheral.
-  * @param  TIM_ICPolarity : The Input Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPolarity_Rising
-  *            @arg TIM_ICPolarity_Falling
-  *            @arg TIM_ICPolarity_BothEdge
-  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
-  *          This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  */
-static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
-{
-  uint32_t tmpccmr1 = 0;
-  uint32_t tmpccer = 0;
-
-  /* Disable the Channel 1: Reset the CC1E Bit */
-  tmpccer = TIMx->CCER;
-  TIMx->CCER &= ~TIM_CCER_CC1E;
-  tmpccmr1 = TIMx->CCMR1;
-
-  /* Set the filter */
-  tmpccmr1 &= ~TIM_CCMR1_IC1F;
-  tmpccmr1 |= (TIM_ICFilter << 4);
-
-  /* Select the Polarity and set the CC1E Bit */
-  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
-  tmpccer |= TIM_ICPolarity;
-
-  /* Write to TIMx CCMR1 and CCER registers */
-  TIMx->CCMR1 = tmpccmr1;
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configure the TI2 as Input.
-  * @param  TIMx to select the TIM peripheral
-  * @param  TIM_ICPolarity : The Input Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPolarity_Rising
-  *            @arg TIM_ICPolarity_Falling
-  *            @arg TIM_ICPolarity_BothEdge
-  * @param  TIM_ICSelection: specifies the input to be used.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
-  *            @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
-  *            @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
-  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
-  *          This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
-  *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be
-  *        protected against un-initialized filter and polarity values.
-  */
-static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                       uint32_t TIM_ICFilter)
-{
-  uint32_t tmpccmr1 = 0;
-  uint32_t tmpccer = 0;
-
-  /* Disable the Channel 2: Reset the CC2E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC2E;
-  tmpccmr1 = TIMx->CCMR1;
-  tmpccer = TIMx->CCER;
-
-  /* Select the Input */
-  tmpccmr1 &= ~TIM_CCMR1_CC2S;
-  tmpccmr1 |= (TIM_ICSelection << 8);
-
-  /* Set the filter */
-  tmpccmr1 &= ~TIM_CCMR1_IC2F;
-  tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
-
-  /* Select the Polarity and set the CC2E Bit */
-  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
-  tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
-
-  /* Write to TIMx CCMR1 and CCER registers */
-  TIMx->CCMR1 = tmpccmr1 ;
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configure the Polarity and Filter for TI2.
-  * @param  TIMx to select the TIM peripheral.
-  * @param  TIM_ICPolarity : The Input Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPolarity_Rising
-  *            @arg TIM_ICPolarity_Falling
-  *            @arg TIM_ICPolarity_BothEdge
-  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
-  *          This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  */
-static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
-{
-  uint32_t tmpccmr1 = 0;
-  uint32_t tmpccer = 0;
-
-  /* Disable the Channel 2: Reset the CC2E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC2E;
-  tmpccmr1 = TIMx->CCMR1;
-  tmpccer = TIMx->CCER;
-
-  /* Set the filter */
-  tmpccmr1 &= ~TIM_CCMR1_IC2F;
-  tmpccmr1 |= (TIM_ICFilter << 12);
-
-  /* Select the Polarity and set the CC2E Bit */
-  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
-  tmpccer |= (TIM_ICPolarity << 4);
-
-  /* Write to TIMx CCMR1 and CCER registers */
-  TIMx->CCMR1 = tmpccmr1 ;
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configure the TI3 as Input.
-  * @param  TIMx to select the TIM peripheral
-  * @param  TIM_ICPolarity : The Input Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPolarity_Rising
-  *            @arg TIM_ICPolarity_Falling
-  *            @arg TIM_ICPolarity_BothEdge
-  * @param  TIM_ICSelection: specifies the input to be used.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
-  *            @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
-  *            @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
-  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
-  *          This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
-  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
-  *        protected against un-initialized filter and polarity values.
-  */
-static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                       uint32_t TIM_ICFilter)
-{
-  uint32_t tmpccmr2 = 0;
-  uint32_t tmpccer = 0;
-
-  /* Disable the Channel 3: Reset the CC3E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC3E;
-  tmpccmr2 = TIMx->CCMR2;
-  tmpccer = TIMx->CCER;
-
-  /* Select the Input */
-  tmpccmr2 &= ~TIM_CCMR2_CC3S;
-  tmpccmr2 |= TIM_ICSelection;
-
-  /* Set the filter */
-  tmpccmr2 &= ~TIM_CCMR2_IC3F;
-  tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
-
-  /* Select the Polarity and set the CC3E Bit */
-  tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
-  tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
-
-  /* Write to TIMx CCMR2 and CCER registers */
-  TIMx->CCMR2 = tmpccmr2;
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configure the TI4 as Input.
-  * @param  TIMx to select the TIM peripheral
-  * @param  TIM_ICPolarity : The Input Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPolarity_Rising
-  *            @arg TIM_ICPolarity_Falling
-  *            @arg TIM_ICPolarity_BothEdge
-  * @param  TIM_ICSelection: specifies the input to be used.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
-  *            @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
-  *            @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
-  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
-  *          This parameter must be a value between 0x00 and 0x0F.
-  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
-  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
-  *        protected against un-initialized filter and polarity values.
-  * @retval None
-  */
-static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                       uint32_t TIM_ICFilter)
-{
-  uint32_t tmpccmr2 = 0;
-  uint32_t tmpccer = 0;
-
-  /* Disable the Channel 4: Reset the CC4E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC4E;
-  tmpccmr2 = TIMx->CCMR2;
-  tmpccer = TIMx->CCER;
-
-  /* Select the Input */
-  tmpccmr2 &= ~TIM_CCMR2_CC4S;
-  tmpccmr2 |= (TIM_ICSelection << 8);
-
-  /* Set the filter */
-  tmpccmr2 &= ~TIM_CCMR2_IC4F;
-  tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
-
-  /* Select the Polarity and set the CC4E Bit */
-  tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
-  tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
-
-  /* Write to TIMx CCMR2 and CCER registers */
-  TIMx->CCMR2 = tmpccmr2;
-  TIMx->CCER = tmpccer ;
-}
-
-/**
-  * @brief  Selects the Input Trigger source
-  * @param  TIMx to select the TIM peripheral
-  * @param  InputTriggerSource: The Input Trigger source.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_TS_ITR0: Internal Trigger 0
-  *            @arg TIM_TS_ITR1: Internal Trigger 1
-  *            @arg TIM_TS_ITR2: Internal Trigger 2
-  *            @arg TIM_TS_ITR3: Internal Trigger 3
-  *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
-  *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
-  *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
-  *            @arg TIM_TS_ETRF: External Trigger input
-  * @retval None
-  */
-static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
-{
-  uint32_t tmpsmcr = 0;
-
-   /* Get the TIMx SMCR register value */
-   tmpsmcr = TIMx->SMCR;
-   /* Reset the TS Bits */
-   tmpsmcr &= ~TIM_SMCR_TS;
-   /* Set the Input Trigger source and the slave mode*/
-   tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1;
-   /* Write to TIMx SMCR */
-   TIMx->SMCR = tmpsmcr;
-}
-/**
-  * @brief  Configures the TIMx External Trigger (ETR).
-  * @param  TIMx to select the TIM peripheral
-  * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF.
-  *            @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2.
-  *            @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4.
-  *            @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8.
-  * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active.
-  *            @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active.
-  * @param  ExtTRGFilter: External Trigger Filter.
-  *          This parameter must be a value between 0x00 and 0x0F
-  * @retval None
-  */
-void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
-                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
-{
-  uint32_t tmpsmcr = 0;
-
-  tmpsmcr = TIMx->SMCR;
-
-  /* Reset the ETR Bits */
-  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
-
-  /* Set the Prescaler, the Filter value and the Polarity */
-  tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
-
-  /* Write to TIMx SMCR */
-  TIMx->SMCR = tmpsmcr;
-}
-
-/**
-  * @brief  Enables or disables the TIM Capture Compare Channel x.
-  * @param  TIMx to select the TIM peripheral
-  * @param  Channel: specifies the TIM Channel
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1
-  *            @arg TIM_CHANNEL_2: TIM Channel 2
-  *            @arg TIM_CHANNEL_3: TIM Channel 3
-  *            @arg TIM_CHANNEL_4: TIM Channel 4
-  * @param  ChannelState: specifies the TIM Channel CCxE bit new state.
-  *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
-  * @retval None
-  */
-void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
-{
-  uint32_t tmp = 0;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
-  assert_param(IS_TIM_CHANNELS(Channel));
-
-  tmp = TIM_CCER_CC1E << Channel;
-
-  /* Reset the CCxE Bit */
-  TIMx->CCER &= ~tmp;
-
-  /* Set or reset the CCxE Bit */
-  TIMx->CCER |=  (uint32_t)(ChannelState << Channel);
-}
-
-
-/**
-  * @}
-  */
-
-#endif /* HAL_TIM_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/src/stm32l4xx_hal_tim_ex.c b/stmhal/hal/l4/src/stm32l4xx_hal_tim_ex.c
deleted file mode 100644
index 4c63f2cfbb..0000000000
--- a/stmhal/hal/l4/src/stm32l4xx_hal_tim_ex.c
+++ /dev/null
@@ -1,2711 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_tim_ex.c
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   TIM HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Timer Extended peripheral:
-  *           + Time Hall Sensor Interface Initialization
-  *           + Time Hall Sensor Interface Start
-  *           + Time Complementary signal break and dead time configuration
-  *           + Time Master and Slave synchronization configuration
-  *           + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
-  *           + Time OCRef clear configuration
-  *           + Timer remapping capabilities configuration
-  @verbatim
-  ==============================================================================
-                      ##### TIMER Extended features #####
-  ==============================================================================
-  [..]
-    The Timer Extended features include:
-    (#) Complementary outputs with programmable dead-time for :
-        (++) Output Compare
-        (++) PWM generation (Edge and Center-aligned Mode)
-        (++) One-pulse mode output
-    (#) Synchronization circuit to control the timer with external signals and to
-        interconnect several timers together.
-    (#) Break input to put the timer output signals in reset state or in a known state.
-    (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
-        positioning purposes
-
-            ##### How to use this driver #####
-  ==============================================================================
-    [..]
-     (#) Initialize the TIM low level resources by implementing the following functions
-         depending on the selected feature:
-           (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
-
-     (#) Initialize the TIM low level resources :
-        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
-        (##) TIM pins configuration
-            (+++) Enable the clock for the TIM GPIOs using the following function:
-              __HAL_RCC_GPIOx_CLK_ENABLE();
-            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
-
-     (#) The external Clock can be configured, if needed (the default clock is the
-         internal clock from the APBx), using the following function:
-         HAL_TIM_ConfigClockSource, the clock configuration should be done before
-         any start function.
-
-     (#) Configure the TIM in the desired functioning mode using one of the
-         initialization function of this driver:
-          (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutationEvent(): to use the
-              Timer Hall Sensor Interface and the commutation event with the corresponding
-              Interrupt and DMA request if needed (Note that One Timer is used to interface
-             with the Hall sensor Interface and another Timer should be used to use
-             the commutation event).
-
-     (#) Activate the TIM peripheral using one of the start functions:
-           (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
-           (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
-           (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
-           (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
-
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-*/
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup TIMEx TIMEx
-  * @brief TIM Extended HAL module driver
-  * @{
-  */
-
-#ifdef HAL_TIM_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define BDTR_BKF_SHIFT (16)
-#define BDTR_BK2F_SHIFT (20)
-#define TIMx_ETRSEL_MASK ((uint32_t)0x0001C000) 
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
-                              TIM_OC_InitTypeDef *OC_Config);
-
-static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
-                              TIM_OC_InitTypeDef *OC_Config);
-
-static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
-
-/* Private functions ---------------------------------------------------------*/
-/**
-  * @brief  Timer Ouput Compare 5 configuration
-  * @param  TIMx to select the TIM peripheral
-  * @param  OC_Config: The ouput configuration structure
-  * @retval None
-  */
-static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
-                              TIM_OC_InitTypeDef *OC_Config)
-{
-  uint32_t tmpccmrx = 0;
-  uint32_t tmpccer = 0;
-  uint32_t tmpcr2 = 0;
-
-  /* Disable the output: Reset the CCxE Bit */
-  TIMx->CCER &= ~TIM_CCER_CC5E;
-
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
-  /* Get the TIMx CR2 register value */
-  tmpcr2 =  TIMx->CR2;
-  /* Get the TIMx CCMR1 register value */
-  tmpccmrx = TIMx->CCMR3;
-
-  /* Reset the Output Compare Mode Bits */
-  tmpccmrx &= ~(TIM_CCMR3_OC5M);
-  /* Select the Output Compare Mode */
-  tmpccmrx |= OC_Config->OCMode;
-
-  /* Reset the Output Polarity level */
-  tmpccer &= ~TIM_CCER_CC5P;
-  /* Set the Output Compare Polarity */
-  tmpccer |= (OC_Config->OCPolarity << 16);
-
-  if(IS_TIM_BREAK_INSTANCE(TIMx))
-  {
-    /* Reset the Output Compare IDLE State */
-    tmpcr2 &= ~TIM_CR2_OIS5;
-    /* Set the Output Idle state */
-    tmpcr2 |= (OC_Config->OCIdleState << 8);
-  }
-  /* Write to TIMx CR2 */
-  TIMx->CR2 = tmpcr2;
-
-  /* Write to TIMx CCMR3 */
-  TIMx->CCMR3 = tmpccmrx;
-
-  /* Set the Capture Compare Register value */
-  TIMx->CCR5 = OC_Config->Pulse;
-
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Timer Ouput Compare 6 configuration
-  * @param  TIMx to select the TIM peripheral
-  * @param  OC_Config: The ouput configuration structure
-  * @retval None
-  */
-static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
-                              TIM_OC_InitTypeDef *OC_Config)
-{
-  uint32_t tmpccmrx = 0;
-  uint32_t tmpccer = 0;
-  uint32_t tmpcr2 = 0;
-
-  /* Disable the output: Reset the CCxE Bit */
-  TIMx->CCER &= ~TIM_CCER_CC6E;
-
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
-  /* Get the TIMx CR2 register value */
-  tmpcr2 =  TIMx->CR2;
-  /* Get the TIMx CCMR1 register value */
-  tmpccmrx = TIMx->CCMR3;
-
-  /* Reset the Output Compare Mode Bits */
-  tmpccmrx &= ~(TIM_CCMR3_OC6M);
-  /* Select the Output Compare Mode */
-  tmpccmrx |= (OC_Config->OCMode << 8);
-
-  /* Reset the Output Polarity level */
-  tmpccer &= (uint32_t)~TIM_CCER_CC6P;
-  /* Set the Output Compare Polarity */
-  tmpccer |= (OC_Config->OCPolarity << 20);
-
-  if(IS_TIM_BREAK_INSTANCE(TIMx))
-  {
-    /* Reset the Output Compare IDLE State */
-    tmpcr2 &= ~TIM_CR2_OIS6;
-    /* Set the Output Idle state */
-    tmpcr2 |= (OC_Config->OCIdleState << 10);
-  }
-
-  /* Write to TIMx CR2 */
-  TIMx->CR2 = tmpcr2;
-
-  /* Write to TIMx CCMR3 */
-  TIMx->CCMR3 = tmpccmrx;
-
-  /* Set the Capture Compare Register value */
-  TIMx->CCR6 = OC_Config->Pulse;
-
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
-}
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
-  * @{
-  */
-
-/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
-  * @brief    Timer Hall Sensor functions
-  *
-@verbatim
-  ==============================================================================
-                      ##### Timer Hall Sensor functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Initialize and configure TIM HAL Sensor.
-    (+) De-initialize TIM HAL Sensor.
-    (+) Start the Hall Sensor Interface.
-    (+) Stop the Hall Sensor Interface.
-    (+) Start the Hall Sensor Interface and enable interrupts.
-    (+) Stop the Hall Sensor Interface and disable interrupts.
-    (+) Start the Hall Sensor Interface and enable DMA transfers.
-    (+) Stop the Hall Sensor Interface and disable DMA transfers.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIM Hall Sensor Interface and initialize the associated handle.
-  * @param  htim: TIM Encoder Interface handle
-  * @param  sConfig: TIM Hall Sensor configuration structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
-{
-  TIM_OC_InitTypeDef OC_Config;
-
-  /* Check the TIM handle allocation */
-  if(htim == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-  assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
-  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
-  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
-
-  if(htim->State == HAL_TIM_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    htim->Lock = HAL_UNLOCKED;
-
-    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
-    HAL_TIMEx_HallSensor_MspInit(htim);
-  }
-
-  /* Set the TIM state */
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Configure the Time base in the Encoder Mode */
-  TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
-  /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the  Hall sensor */
-  TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
-
-  /* Reset the IC1PSC Bits */
-  htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
-  /* Set the IC1PSC value */
-  htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
-
-  /* Enable the Hall sensor interface (XOR function of the three inputs) */
-  htim->Instance->CR2 |= TIM_CR2_TI1S;
-
-  /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
-  htim->Instance->SMCR &= ~TIM_SMCR_TS;
-  htim->Instance->SMCR |= TIM_TS_TI1F_ED;
-
-  /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
-  htim->Instance->SMCR &= ~TIM_SMCR_SMS;
-  htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
-
-  /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
-  OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
-  OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
-  OC_Config.OCMode = TIM_OCMODE_PWM2;
-  OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
-  OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
-  OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
-  OC_Config.Pulse = sConfig->Commutation_Delay;
-
-  TIM_OC2_SetConfig(htim->Instance, &OC_Config);
-
-  /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
-    register to 101 */
-  htim->Instance->CR2 &= ~TIM_CR2_MMS;
-  htim->Instance->CR2 |= TIM_TRGO_OC2REF;
-
-  /* Initialize the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitialize the TIM Hall Sensor interface
-  * @param  htim: TIM Hall Sensor handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Disable the TIM Peripheral Clock */
-  __HAL_TIM_DISABLE(htim);
-
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
-  HAL_TIMEx_HallSensor_MspDeInit(htim);
-
-  /* Change TIM state */
-  htim->State = HAL_TIM_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM Hall Sensor MSP.
-  * @param  htim: TIM handle
-  * @retval None
-  */
-__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitialize TIM Hall Sensor MSP.
-  * @param  htim: TIM handle
-  * @retval None
-  */
-__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Starts the TIM Hall Sensor Interface.
-  * @param  htim : TIM Hall Sensor handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-
-  /* Enable the Input Capture channels 1
-    (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Hall sensor Interface.
-  * @param  htim : TIM Hall Sensor handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-
-  /* Disable the Input Capture channels 1, 2 and 3
-    (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Hall Sensor Interface in interrupt mode.
-  * @param  htim : TIM Hall Sensor handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-
-  /* Enable the capture compare Interrupts 1 event */
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-
-  /* Enable the Input Capture channels 1
-    (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Hall Sensor Interface in interrupt mode.
-  * @param  htim : TIM handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-
-  /* Disable the Input Capture channels 1
-    (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
-  /* Disable the capture compare Interrupts event */
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Hall Sensor Interface in DMA mode.
-  * @param  htim : TIM Hall Sensor handle
-  * @param  pData: The destination Buffer address.
-  * @param  Length: The length of data to be transferred from TIM peripheral to memory.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-
-   if((htim->State == HAL_TIM_STATE_BUSY))
-  {
-     return HAL_BUSY;
-  }
-  else if((htim->State == HAL_TIM_STATE_READY))
-  {
-    if(((uint32_t)pData == 0 ) && (Length > 0))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      htim->State = HAL_TIM_STATE_BUSY;
-    }
-  }
-  /* Enable the Input Capture channels 1
-    (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-
-  /* Set the DMA Input Capture 1 Callback */
-  htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
-  /* Set the DMA error callback */
-  htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
-  /* Enable the DMA channel for Capture 1*/
-  HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
-
-  /* Enable the capture compare 1 Interrupt */
-  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Hall Sensor Interface in DMA mode.
-  * @param  htim : TIM handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-
-  /* Disable the Input Capture channels 1
-    (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
-
-  /* Disable the capture compare Interrupts 1 event */
-  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
-  *  @brief   Timer Complementary Output Compare functions
-  *
-@verbatim
-  ==============================================================================
-              ##### Timer Complementary Output Compare functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Start the Complementary Output Compare/PWM.
-    (+) Stop the Complementary Output Compare/PWM.
-    (+) Start the Complementary Output Compare/PWM and enable interrupts.
-    (+) Stop the Complementary Output Compare/PWM and disable interrupts.
-    (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
-    (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Starts the TIM Output Compare signal generation on the complementary
-  *         output.
-  * @param  htim : TIM Output Compare handle
-  * @param  Channel : TIM Channel to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
-  /* Enable the Capture compare channel N */
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
-  /* Enable the Main Ouput */
-  __HAL_TIM_MOE_ENABLE(htim);
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Output Compare signal generation on the complementary
-  *         output.
-  * @param  htim : TIM handle
-  * @param  Channel : TIM Channel to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
-  /* Disable the Capture compare channel N */
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
-  /* Disable the Main Ouput */
-  __HAL_TIM_MOE_DISABLE(htim);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Output Compare signal generation in interrupt mode
-  *         on the complementary output.
-  * @param  htim : TIM OC handle
-  * @param  Channel : TIM Channel to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Enable the TIM Output Compare interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Enable the TIM Output Compare interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Enable the TIM Output Compare interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Enable the TIM Output Compare interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Enable the TIM Break interrupt */
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
-  
-  /* Enable the Capture compare channel N */
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
-  /* Enable the Main Ouput */
-  __HAL_TIM_MOE_ENABLE(htim);
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Output Compare signal generation in interrupt mode
-  *         on the complementary output.
-  * @param  htim : TIM Output Compare handle
-  * @param  Channel : TIM Channel to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  uint32_t tmpccer = 0;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Disable the TIM Output Compare interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Output Compare interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Output Compare interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Output Compare interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Disable the Capture compare channel N */
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
-  /* Disable the TIM Break interrupt (only if no more channel is active) */
-  tmpccer = htim->Instance->CCER;
-  if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
-  {
-    __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
-  }
-
-  /* Disable the Main Ouput */
-  __HAL_TIM_MOE_DISABLE(htim);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Output Compare signal generation in DMA mode
-  *         on the complementary output.
-  * @param  htim : TIM Output Compare handle
-  * @param  Channel : TIM Channel to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  pData: The source Buffer address.
-  * @param  Length: The length of data to be transferred from memory to TIM peripheral
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
-  if((htim->State == HAL_TIM_STATE_BUSY))
-  {
-     return HAL_BUSY;
-  }
-  else if((htim->State == HAL_TIM_STATE_READY))
-  {
-    if(((uint32_t)pData == 0 ) && (Length > 0))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      htim->State = HAL_TIM_STATE_BUSY;
-    }
-  }
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
-
-      /* Enable the TIM Output Compare DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
-
-      /* Enable the TIM Output Compare DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-{
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-
-      /* Enable the TIM Output Compare DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-     /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-
-      /* Enable the TIM Output Compare DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Enable the Capture compare channel N */
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
-  /* Enable the Main Ouput */
-  __HAL_TIM_MOE_ENABLE(htim);
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Output Compare signal generation in DMA mode
-  *         on the complementary output.
-  * @param  htim : TIM Output Compare handle
-  * @param  Channel : TIM Channel to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Disable the TIM Output Compare DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Output Compare DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Output Compare DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Output Compare interrupt */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Disable the Capture compare channel N */
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
-  /* Disable the Main Ouput */
-  __HAL_TIM_MOE_DISABLE(htim);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Change the htim state */
-  htim->State = HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
-  * @brief    Timer Complementary PWM functions
-  *
-@verbatim
-  ==============================================================================
-                 ##### Timer Complementary PWM functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Start the Complementary PWM.
-    (+) Stop the Complementary PWM.
-    (+) Start the Complementary PWM and enable interrupts.
-    (+) Stop the Complementary PWM and disable interrupts.
-    (+) Start the Complementary PWM and enable DMA transfers.
-    (+) Stop the Complementary PWM and disable DMA transfers.
-    (+) Start the Complementary Input Capture measurement.
-    (+) Stop the Complementary Input Capture.
-    (+) Start the Complementary Input Capture and enable interrupts.
-    (+) Stop the Complementary Input Capture and disable interrupts.
-    (+) Start the Complementary Input Capture and enable DMA transfers.
-    (+) Stop the Complementary Input Capture and disable DMA transfers.
-    (+) Start the Complementary One Pulse generation.
-    (+) Stop the Complementary One Pulse.
-    (+) Start the Complementary One Pulse and enable interrupts.
-    (+) Stop the Complementary One Pulse and disable interrupts.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Starts the PWM signal generation on the complementary output.
-  * @param  htim : TIM handle
-  * @param  Channel : TIM Channel to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
-  /* Enable the complementary PWM output  */
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
-  /* Enable the Main Ouput */
-  __HAL_TIM_MOE_ENABLE(htim);
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the PWM signal generation on the complementary output.
-  * @param  htim : TIM handle
-  * @param  Channel : TIM Channel to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
-  /* Disable the complementary PWM output  */
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
-  /* Disable the Main Ouput */
-  __HAL_TIM_MOE_DISABLE(htim);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the PWM signal generation in interrupt mode on the
-  *         complementary output.
-  * @param  htim : TIM handle
-  * @param  Channel : TIM Channel to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Enable the TIM Capture/Compare 1 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Enable the TIM Capture/Compare 2 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Enable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Enable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Enable the TIM Break interrupt */
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
-
-  /* Enable the complementary PWM output  */
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
-  /* Enable the Main Ouput */
-  __HAL_TIM_MOE_ENABLE(htim);
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the PWM signal generation in interrupt mode on the
-  *         complementary output.
-  * @param  htim : TIM handle
-  * @param  Channel : TIM Channel to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  uint32_t tmpccer = 0;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Disable the TIM Capture/Compare 1 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Capture/Compare 2 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Disable the complementary PWM output  */
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
-  
-  /* Disable the TIM Break interrupt (only if no more channel is active) */
-  tmpccer = htim->Instance->CCER;
-  if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
-  {
-    __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
-  }
-
-  /* Disable the Main Ouput */
-  __HAL_TIM_MOE_DISABLE(htim);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM PWM signal generation in DMA mode on the
-  *         complementary output
-  * @param  htim : TIM handle
-  * @param  Channel : TIM Channel to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  pData: The source Buffer address.
-  * @param  Length: The length of data to be transferred from memory to TIM peripheral
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
-  if((htim->State == HAL_TIM_STATE_BUSY))
-  {
-     return HAL_BUSY;
-  }
-  else if((htim->State == HAL_TIM_STATE_READY))
-  {
-    if(((uint32_t)pData == 0 ) && (Length > 0))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      htim->State = HAL_TIM_STATE_BUSY;
-    }
-  }
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
-
-      /* Enable the TIM Capture/Compare 1 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
-
-      /* Enable the TIM Capture/Compare 2 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-
-      /* Enable the TIM Capture/Compare 3 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-     /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-
-      /* Enable the TIM Capture/Compare 4 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Enable the complementary PWM output  */
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
-  /* Enable the Main Ouput */
-  __HAL_TIM_MOE_ENABLE(htim);
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM PWM signal generation in DMA mode on the complementary
-  *         output
-  * @param  htim : TIM handle
-  * @param  Channel : TIM Channel to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Disable the TIM Capture/Compare 1 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Capture/Compare 2 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Capture/Compare 3 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 4 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Disable the complementary PWM output */
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
-  /* Disable the Main Ouput */
-  __HAL_TIM_MOE_DISABLE(htim);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Change the htim state */
-  htim->State = HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
-  * @brief    Timer Complementary One Pulse functions
-  *
-@verbatim
-  ==============================================================================
-                ##### Timer Complementary One Pulse functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Start the Complementary One Pulse generation.
-    (+) Stop the Complementary One Pulse.
-    (+) Start the Complementary One Pulse and enable interrupts.
-    (+) Stop the Complementary One Pulse and disable interrupts.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Starts the TIM One Pulse signal generation on the complementary
-  *         output.
-  * @param  htim : TIM One Pulse handle
-  * @param  OutputChannel : TIM Channel to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-  {
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
-
-  /* Enable the complementary One Pulse output */
-  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
-
-  /* Enable the Main Ouput */
-  __HAL_TIM_MOE_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM One Pulse signal generation on the complementary
-  *         output.
-  * @param  htim : TIM One Pulse handle
-  * @param  OutputChannel : TIM Channel to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
-
-  /* Disable the complementary One Pulse output */
-  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
-
-  /* Disable the Main Ouput */
-  __HAL_TIM_MOE_DISABLE(htim);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM One Pulse signal generation in interrupt mode on the
-  *         complementary channel.
-  * @param  htim : TIM One Pulse handle
-  * @param  OutputChannel : TIM Channel to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
-
-  /* Enable the TIM Capture/Compare 1 interrupt */
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-
-  /* Enable the TIM Capture/Compare 2 interrupt */
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-
-  /* Enable the complementary One Pulse output */
-  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
-
-  /* Enable the Main Ouput */
-  __HAL_TIM_MOE_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM One Pulse signal generation in interrupt mode on the
-  *         complementary channel.
-  * @param  htim : TIM One Pulse handle
-  * @param  OutputChannel : TIM Channel to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
-
-  /* Disable the TIM Capture/Compare 1 interrupt */
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-
-  /* Disable the TIM Capture/Compare 2 interrupt */
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-
-  /* Disable the complementary One Pulse output */
-  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
-
-  /* Disable the Main Ouput */
-  __HAL_TIM_MOE_DISABLE(htim);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
-  * @brief    Peripheral Control functions
-  *
-@verbatim
-  ==============================================================================
-                    ##### Peripheral Control functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Configure the commutation event in case of use of the Hall sensor interface.
-      (+) Configure Output channels for OC and PWM mode.
-
-      (+) Configure Complementary channels, break features and dead time.
-      (+) Configure Master synchronization.
-      (+) Configure timer remapping capabilities.
-      (+) Enable or disable channel grouping
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configure the TIM commutation event sequence.
-  * @note  This function is mandatory to use the commutation event in order to
-  *        update the configuration at each commutation detection on the TRGI input of the Timer,
-  *        the typical use of this feature is with the use of another Timer(interface Timer)
-  *        configured in Hall sensor interface, this interface Timer will generate the
-  *        commutation at its TRGO output (connected to Timer used in this function) each time
-  *        the TI1 of the Interface Timer detect a commutation at its input TI1.
-  * @param  htim: TIM handle
-  * @param  InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
-  *          This parameter can be one of the following values:
-  *            @arg TIM_TS_ITR0: Internal trigger 0 selected
-  *            @arg TIM_TS_ITR1: Internal trigger 1 selected
-  *            @arg TIM_TS_ITR2: Internal trigger 2 selected
-  *            @arg TIM_TS_ITR3: Internal trigger 3 selected
-  *            @arg TIM_TS_NONE: No trigger is needed
-  * @param  CommutationSource : the Commutation Event source
-  *          This parameter can be one of the following values:
-  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
-  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
-
-  __HAL_LOCK(htim);
-
-  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
-      (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
-  {
-    /* Select the Input trigger */
-    htim->Instance->SMCR &= ~TIM_SMCR_TS;
-    htim->Instance->SMCR |= InputTrigger;
-  }
-
-  /* Select the Capture Compare preload feature */
-  htim->Instance->CR2 |= TIM_CR2_CCPC;
-  /* Select the Commutation event source */
-  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
-  htim->Instance->CR2 |= CommutationSource;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configure the TIM commutation event sequence with interrupt.
-  * @note  This function is mandatory to use the commutation event in order to
-  *        update the configuration at each commutation detection on the TRGI input of the Timer,
-  *        the typical use of this feature is with the use of another Timer(interface Timer)
-  *        configured in Hall sensor interface, this interface Timer will generate the
-  *        commutation at its TRGO output (connected to Timer used in this function) each time
-  *        the TI1 of the Interface Timer detect a commutation at its input TI1.
-  * @param  htim: TIM handle
-  * @param  InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
-  *          This parameter can be one of the following values:
-  *            @arg TIM_TS_ITR0: Internal trigger 0 selected
-  *            @arg TIM_TS_ITR1: Internal trigger 1 selected
-  *            @arg TIM_TS_ITR2: Internal trigger 2 selected
-  *            @arg TIM_TS_ITR3: Internal trigger 3 selected
-  *            @arg TIM_TS_NONE: No trigger is needed
-  * @param  CommutationSource : the Commutation Event source
-  *          This parameter can be one of the following values:
-  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
-  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
-
-  __HAL_LOCK(htim);
-
-  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
-      (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
-  {
-    /* Select the Input trigger */
-    htim->Instance->SMCR &= ~TIM_SMCR_TS;
-    htim->Instance->SMCR |= InputTrigger;
-  }
-
-  /* Select the Capture Compare preload feature */
-  htim->Instance->CR2 |= TIM_CR2_CCPC;
-  /* Select the Commutation event source */
-  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
-  htim->Instance->CR2 |= CommutationSource;
-
-  /* Enable the Commutation Interrupt Request */
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configure the TIM commutation event sequence with DMA.
-  * @note  This function is mandatory to use the commutation event in order to
-  *        update the configuration at each commutation detection on the TRGI input of the Timer,
-  *        the typical use of this feature is with the use of another Timer(interface Timer)
-  *        configured in Hall sensor interface, this interface Timer will generate the
-  *        commutation at its TRGO output (connected to Timer used in this function) each time
-  *        the TI1 of the Interface Timer detect a commutation at its input TI1.
-  * @note  The user should configure the DMA in his own software, in This function only the COMDE bit is set
-  * @param  htim: TIM handle
-  * @param  InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
-  *          This parameter can be one of the following values:
-  *            @arg TIM_TS_ITR0: Internal trigger 0 selected
-  *            @arg TIM_TS_ITR1: Internal trigger 1 selected
-  *            @arg TIM_TS_ITR2: Internal trigger 2 selected
-  *            @arg TIM_TS_ITR3: Internal trigger 3 selected
-  *            @arg TIM_TS_NONE: No trigger is needed
-  * @param  CommutationSource : the Commutation Event source
-  *          This parameter can be one of the following values:
-  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
-  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
-
-  __HAL_LOCK(htim);
-
-  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
-      (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
-  {
-    /* Select the Input trigger */
-    htim->Instance->SMCR &= ~TIM_SMCR_TS;
-    htim->Instance->SMCR |= InputTrigger;
-  }
-
-  /* Select the Capture Compare preload feature */
-  htim->Instance->CR2 |= TIM_CR2_CCPC;
-  /* Select the Commutation event source */
-  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
-  htim->Instance->CR2 |= CommutationSource;
-
-  /* Enable the Commutation DMA Request */
-  /* Set the DMA Commutation Callback */
-  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
-  /* Set the DMA error callback */
-  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
-
-  /* Enable the Commutation DMA Request */
-  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM Output Compare Channels according to the specified
-  *         parameters in the TIM_OC_InitTypeDef.
-  * @param  htim: TIM Output Compare handle
-  * @param  sConfig: TIM Output Compare configuration structure
-  * @param  Channel : TIM Channels to configure
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
-  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
-  *            @arg TIM_CHANNEL_ALL: all output channels supported by the timer instance selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
-                                           TIM_OC_InitTypeDef* sConfig,
-                                           uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CHANNELS(Channel));
-  assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
-  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
-
-  /* Check input state */
-  __HAL_LOCK(htim);
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
-     /* Configure the TIM Channel 1 in Output Compare */
-      TIM_OC1_SetConfig(htim->Instance, sConfig);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-      /* Configure the TIM Channel 2 in Output Compare */
-      TIM_OC2_SetConfig(htim->Instance, sConfig);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
-      /* Configure the TIM Channel 3 in Output Compare */
-      TIM_OC3_SetConfig(htim->Instance, sConfig);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
-       /* Configure the TIM Channel 4 in Output Compare */
-       TIM_OC4_SetConfig(htim->Instance, sConfig);
-    }
-    break;
-
-    case TIM_CHANNEL_5:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
-
-       /* Configure the TIM Channel 5 in Output Compare */
-       TIM_OC5_SetConfig(htim->Instance, sConfig);
-    }
-    break;
-
-    case TIM_CHANNEL_6:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
-
-       /* Configure the TIM Channel 6 in Output Compare */
-       TIM_OC6_SetConfig(htim->Instance, sConfig);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM PWM  channels according to the specified
-  *         parameters in the TIM_OC_InitTypeDef.
-  * @param  htim: TIM PWM handle
-  * @param  sConfig: TIM PWM configuration structure
-  * @param  Channel : TIM Channels to be configured
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
-  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
-  *            @arg TIM_CHANNEL_ALL: all PWM channels supported by the timer instance selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
-                                            TIM_OC_InitTypeDef* sConfig,
-                                            uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CHANNELS(Channel));
-  assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
-  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
-  assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
-
-  /* Check input state */
-  __HAL_LOCK(htim);
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
-      /* Configure the Channel 1 in PWM mode */
-      TIM_OC1_SetConfig(htim->Instance, sConfig);
-
-      /* Set the Preload enable bit for channel1 */
-      htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
-
-      /* Configure the Output Fast mode */
-      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
-      htim->Instance->CCMR1 |= sConfig->OCFastMode;
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-      /* Configure the Channel 2 in PWM mode */
-      TIM_OC2_SetConfig(htim->Instance, sConfig);
-
-      /* Set the Preload enable bit for channel2 */
-      htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
-
-      /* Configure the Output Fast mode */
-      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
-      htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
-      /* Configure the Channel 3 in PWM mode */
-      TIM_OC3_SetConfig(htim->Instance, sConfig);
-
-      /* Set the Preload enable bit for channel3 */
-      htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
-
-     /* Configure the Output Fast mode */
-      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
-      htim->Instance->CCMR2 |= sConfig->OCFastMode;
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
-      /* Configure the Channel 4 in PWM mode */
-      TIM_OC4_SetConfig(htim->Instance, sConfig);
-
-      /* Set the Preload enable bit for channel4 */
-      htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
-
-     /* Configure the Output Fast mode */
-      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
-      htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
-    }
-    break;
-
-    case TIM_CHANNEL_5:
-    {
-       /* Check the parameters */
-      assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
-
-     /* Configure the Channel 5 in PWM mode */
-      TIM_OC5_SetConfig(htim->Instance, sConfig);
-
-      /* Set the Preload enable bit for channel5*/
-      htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
-
-     /* Configure the Output Fast mode */
-      htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
-      htim->Instance->CCMR3 |= sConfig->OCFastMode;
-    }
-    break;
-
-    case TIM_CHANNEL_6:
-    {
-       /* Check the parameters */
-      assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
-
-     /* Configure the Channel 5 in PWM mode */
-      TIM_OC6_SetConfig(htim->Instance, sConfig);
-
-      /* Set the Preload enable bit for channel6 */
-      htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
-
-     /* Configure the Output Fast mode */
-      htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
-      htim->Instance->CCMR3 |= sConfig->OCFastMode << 8;
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the OCRef clear feature
-  * @param  htim: TIM handle
-  * @param  sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
-  *         contains the OCREF clear feature and parameters for the TIM peripheral.
-  * @param  Channel: specifies the TIM Channel
-  *          This parameter can be one of the following values:
-  *            @arg TIM_Channel_1: TIM Channel 1
-  *            @arg TIM_Channel_2: TIM Channel 2
-  *            @arg TIM_Channel_3: TIM Channel 3
-  *            @arg TIM_Channel_4: TIM Channel 4
-  *            @arg TIM_Channel_5: TIM Channel 5
-  *            @arg TIM_Channel_6: TIM Channel 6
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
-                                           TIM_ClearInputConfigTypeDef *sClearInputConfig,
-                                           uint32_t Channel)
-{
-  uint32_t tmpsmcr = 0;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
-
-  /* Check input state */
-  __HAL_LOCK(htim);
-
-  switch (sClearInputConfig->ClearInputSource)
-  {
-    case TIM_CLEARINPUTSOURCE_NONE:
-    {
-      /* Get the TIMx SMCR register value */
-      tmpsmcr = htim->Instance->SMCR;
-      
-      /* Clear the OCREF clear selection bit */
-      tmpsmcr &= ~TIM_SMCR_OCCS;
-
-      /* Clear the ETR Bits */
-      tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
-
-      /* Set TIMx_SMCR */
-      htim->Instance->SMCR = tmpsmcr;
-   }
-    break;
-
-    case TIM_CLEARINPUTSOURCE_OCREFCLR:
-    {
-      /* Clear the OCREF clear selection bit */
-      htim->Instance->SMCR &= ~TIM_SMCR_OCCS;
-    }
-    break;
-
-    case TIM_CLEARINPUTSOURCE_ETR:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
-      assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
-      assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
-
-      TIM_ETR_SetConfig(htim->Instance,
-                        sClearInputConfig->ClearInputPrescaler,
-                        sClearInputConfig->ClearInputPolarity,
-                        sClearInputConfig->ClearInputFilter);
-
-      /* Set the OCREF clear selection bit */
-      htim->Instance->SMCR |= TIM_SMCR_OCCS;
-    }
-    break;
-    
-  default:
-    break;
-  }
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-      {
-        if(sClearInputConfig->ClearInputState != RESET)
-        {
-          /* Enable the OCREF clear feature for Channel 1 */
-          htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
-        }
-        else
-        {
-          /* Disable the OCREF clear feature for Channel 1 */
-          htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
-        }
-      }
-      break;
-    case TIM_CHANNEL_2:
-      {
-        if(sClearInputConfig->ClearInputState != RESET)
-        {
-          /* Enable the OCREF clear feature for Channel 2 */
-          htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
-        }
-        else
-        {
-          /* Disable the OCREF clear feature for Channel 2 */
-          htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
-        }
-      }
-    break;
-    case TIM_CHANNEL_3:
-      {
-        if(sClearInputConfig->ClearInputState != RESET)
-        {
-          /* Enable the OCREF clear feature for Channel 3 */
-          htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
-        }
-        else
-        {
-          /* Disable the OCREF clear feature for Channel 3 */
-          htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
-        }
-      }
-    break;
-    case TIM_CHANNEL_4:
-      {
-        if(sClearInputConfig->ClearInputState != RESET)
-        {
-          /* Enable the OCREF clear feature for Channel 4 */
-          htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
-        }
-        else
-        {
-          /* Disable the OCREF clear feature for Channel 4 */
-          htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
-        }
-      }
-    break;
-    case TIM_CHANNEL_5:
-      {
-        if(sClearInputConfig->ClearInputState != RESET)
-        {
-          /* Enable the OCREF clear feature for Channel 1 */
-          htim->Instance->CCMR3 |= TIM_CCMR3_OC5CE;
-        }
-        else
-        {
-          /* Disable the OCREF clear feature for Channel 1 */
-          htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5CE;
-        }
-      }
-    break;
-    case TIM_CHANNEL_6:
-      {
-        if(sClearInputConfig->ClearInputState != RESET)
-        {
-          /* Enable the OCREF clear feature for Channel 1 */
-          htim->Instance->CCMR3 |= TIM_CCMR3_OC6CE;
-        }
-        else
-        {
-          /* Disable the OCREF clear feature for Channel 1 */
-          htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6CE;
-        }
-      }
-    break;
-    default:
-    break;
-  }
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the TIM in master mode.
-  * @param  htim: TIM handle.
-  * @param  sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that
-  *         contains the selected trigger output (TRGO) and the Master/Slave
-  *         mode.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
-                                                      TIM_MasterConfigTypeDef * sMasterConfig)
-{
-  uint32_t tmpcr2;
-  uint32_t tmpsmcr;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
-  assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
-
-  /* Check input state */
-  __HAL_LOCK(htim);
-
- /* Get the TIMx CR2 register value */
-  tmpcr2 = htim->Instance->CR2;
-
-  /* Get the TIMx SMCR register value */
-  tmpsmcr = htim->Instance->SMCR;
-
-  /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
-  if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
-  {
-    /* Check the parameters */
-    assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
-
-    /* Clear the MMS2 bits */
-    tmpcr2 &= ~TIM_CR2_MMS2;
-    /* Select the TRGO2 source*/
-    tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
-  }
-
-  /* Reset the MMS Bits */
-  tmpcr2 &= ~TIM_CR2_MMS;
-  /* Select the TRGO source */
-  tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
-
-  /* Reset the MSM Bit */
-  tmpsmcr &= ~TIM_SMCR_MSM;
-  /* Set master mode */
-  tmpsmcr |= sMasterConfig->MasterSlaveMode;
-
-  /* Update TIMx CR2 */
-  htim->Instance->CR2 = tmpcr2;
-
-  /* Update TIMx SMCR */
-  htim->Instance->SMCR = tmpsmcr;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief   Configures the Break feature, dead time, Lock level, OSSI/OSSR State
-  *         and the AOE(automatic output enable).
-  * @param  htim: TIM handle
-  * @param  sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
-  *         contains the BDTR Register configuration  information for the TIM peripheral.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
-                                                TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
-{
-  uint32_t tmpbdtr = 0;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
-  assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
-  assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
-  assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
-  assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
-  assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
-  assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
-  assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
-
-  /* Check input state */
-  __HAL_LOCK(htim);
-
-  /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
-     the OSSI State, the dead time value and the Automatic Output Enable Bit */
-  if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
-  {
-    assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
-    assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
-    assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
-
-    /* Clear the BDTR bits */
-    tmpbdtr &= ~(TIM_BDTR_DTG | TIM_BDTR_LOCK |  TIM_BDTR_OSSI |
-                 TIM_BDTR_OSSR | TIM_BDTR_BKE | TIM_BDTR_BKP |
-                 TIM_BDTR_AOE | TIM_BDTR_MOE | TIM_BDTR_BKF |
-                 TIM_BDTR_BK2F | TIM_BDTR_BK2E | TIM_BDTR_BK2P);
-
-    /* Set the BDTR bits */
-    tmpbdtr |= sBreakDeadTimeConfig->DeadTime;
-    tmpbdtr |= sBreakDeadTimeConfig->LockLevel;
-    tmpbdtr |= sBreakDeadTimeConfig->OffStateIDLEMode;
-    tmpbdtr |= sBreakDeadTimeConfig->OffStateRunMode;
-    tmpbdtr |= sBreakDeadTimeConfig->BreakState;
-    tmpbdtr |= sBreakDeadTimeConfig->BreakPolarity;
-    tmpbdtr |= sBreakDeadTimeConfig->AutomaticOutput;
-    tmpbdtr |= (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT);
-    tmpbdtr |= (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT);
-    tmpbdtr |= sBreakDeadTimeConfig->Break2State;
-    tmpbdtr |= sBreakDeadTimeConfig->Break2Polarity;
-  }
-  else
-  {
-    /* Clear the BDTR bits */
-    tmpbdtr &= ~(TIM_BDTR_DTG | TIM_BDTR_LOCK |  TIM_BDTR_OSSI |
-                 TIM_BDTR_OSSR | TIM_BDTR_BKE | TIM_BDTR_BKP |
-                 TIM_BDTR_AOE | TIM_BDTR_MOE | TIM_BDTR_BKF);
-
-    /* Set the BDTR bits */
-    tmpbdtr |= sBreakDeadTimeConfig->DeadTime;
-    tmpbdtr |= sBreakDeadTimeConfig->LockLevel;
-    tmpbdtr |= sBreakDeadTimeConfig->OffStateIDLEMode;
-    tmpbdtr |= sBreakDeadTimeConfig->OffStateRunMode;
-    tmpbdtr |= sBreakDeadTimeConfig->BreakState;
-    tmpbdtr |= sBreakDeadTimeConfig->BreakPolarity;
-    tmpbdtr |= sBreakDeadTimeConfig->AutomaticOutput;
-    tmpbdtr |= (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT);
-  }
-
-  /* Set TIMx_BDTR */
-  htim->Instance->BDTR = tmpbdtr;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the break input source.
-  * @param  htim: TIM handle.
-  * @param  BreakInput: Break input to configure
-  *          This parameter can be one of the following values:
-  *            @arg TIM_BREAKINPUT_BRK: Timer break input
-  *            @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
-  * @param  sBreakInputConfig: Break input source configuration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
-                                             uint32_t BreakInput,
-                                             TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
-
-{
-  uint32_t tmporx = 0;
-  uint32_t bkin_enable_mask = 0;
-  uint32_t bkin_polarity_mask = 0;
-  uint32_t bkin_enable_bitpos = 0;
-  uint32_t bkin_polarity_bitpos = 0;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_BREAKINPUT(BreakInput));
-  assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
-  assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
-
-  if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM)
-  {
-    assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
-  }
-  
-  /* Check input state */
-  __HAL_LOCK(htim);
-  
-  switch(sBreakInputConfig->Source)
-  {
-  case TIM_BREAKINPUTSOURCE_BKIN:
-    {
-      bkin_enable_mask = TIM1_OR2_BKINE;
-      bkin_enable_bitpos = 0;
-      bkin_polarity_mask = TIM1_OR2_BKINP;
-      bkin_polarity_bitpos = 9;
-    }
-    break;
-  case TIM_BREAKINPUTSOURCE_COMP1:
-    {
-      bkin_enable_mask = TIM1_OR2_BKCMP1E;
-      bkin_enable_bitpos = 1;
-      bkin_polarity_mask = TIM1_OR2_BKCMP1P;
-      bkin_polarity_bitpos = 10;
-    }
-    break;
-  case TIM_BREAKINPUTSOURCE_COMP2:
-    {
-      bkin_enable_mask = TIM1_OR2_BKCMP2E;
-      bkin_enable_bitpos = 2;
-      bkin_polarity_mask = TIM1_OR2_BKCMP2P;
-      bkin_polarity_bitpos = 11;
-    }
-    break;
-  case TIM_BREAKINPUTSOURCE_DFSDM:
-    {
-      bkin_enable_mask = TIM1_OR2_BKDFBK0E;
-      bkin_enable_bitpos = 8;
-    }
-    break;    
-  default:
-    break;
-  }
-  
-  switch(BreakInput)
-  {
-    case TIM_BREAKINPUT_BRK:
-      {
-        /* Get the TIMx_OR2 register value */
-        tmporx = htim->Instance->OR2;
-        
-        /* Enable the break input */
-        tmporx &= ~bkin_enable_mask;
-        tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
-        
-        /* Set the break input polarity */
-        if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM)
-        {
-          tmporx &= ~bkin_polarity_mask;
-          tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
-        }
-        
-        /* Set TIMx_OR2 */
-        htim->Instance->OR2 = tmporx;        
-      }
-        break;
-    case TIM_BREAKINPUT_BRK2:
-      {
-        /* Get the TIMx_OR3 register value */
-        tmporx = htim->Instance->OR3;
-        
-        /* Enable the break input */
-        tmporx &= ~bkin_enable_mask;
-        tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
-        
-        /* Set the break input polarity */
-        if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM)
-        {
-          tmporx &= ~bkin_polarity_mask;
-          tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
-        }
-        
-        /* Set TIMx_OR3 */
-        htim->Instance->OR3 = tmporx;        
-      }
-      break;    
-  default:
-    break;
-  }
-  
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the TIMx Remapping input capabilities.
-  * @param  htim: TIM handle.
-  * @param  Remap: specifies the TIM remapping source.
-  *
-  *         For TIM1, the parameter is a combination of 4 fields (field1 | field2 | field3 | field4):
-  *
-  *                   field1 can have the following values:
-  *            @arg TIM_TIM1_ETR_ADC1_NONE:           TIM1_ETR is not connected to any ADC1 AWD (analog watchdog)
-  *            @arg TIM_TIM1_ETR_ADC1_AWD1:           TIM1_ETR is connected to ADC1 AWD1
-  *            @arg TIM_TIM1_ETR_ADC1_AWD2:           TIM1_ETR is connected to ADC1 AWD2
-  *            @arg TIM_TIM1_ETR_ADC1_AWD3:           TIM1_ETR is connected to ADC1 AWD3
-  *
-  *                   field2 can have the following values:
-  *            @arg TIM_TIM1_ETR_ADC3_NONE:           TIM1_ETR is not connected to any ADC3 AWD (analog watchdog)
-  *            @arg TIM_TIM1_ETR_ADC3_AWD1:           TIM1_ETR is connected to ADC3 AWD1
-  *            @arg TIM_TIM1_ETR_ADC3_AWD2:           TIM1_ETR is connected to ADC3 AWD2
-  *            @arg TIM_TIM1_ETR_ADC3_AWD3:           TIM1_ETR is connected to ADC3 AWD3
-  *
-  *                   field3 can have the following values:
-  *            @arg TIM_TIM1_TI1_GPIO:                TIM1 TI1 is connected to GPIO
-  *            @arg TIM_TIM1_TI1_COMP1:               TIM1 TI1 is connected to COMP1 output
-  *
-  *                   field4 can have the following values:
-  *            @arg TIM_TIM1_ETR_COMP1:               TIM1_ETR is connected to COMP1 output
-  *            @arg TIM_TIM1_ETR_COMP2:               TIM1_ETR is connected to COMP2 output
-  *            @note  When field4 is set to TIM_TIM1_ETR_COMP1 or TIM_TIM1_ETR_COMP2 field1 and field2 values are not significant 
-  *
-  *         For TIM2, the parameter is a combination of 3 fields (field1 | field2 | field3):
-  *
-  *                   field1 can have the following values:
-  *            @arg TIM_TIM2_ITR1_TIM8_TRGO:          TIM2_ITR1 is connected to TIM8_TRGO
-  *            @arg TIM_TIM2_ITR1_OTG_FS_SOF:         TIM2_ITR1 is connected to OTG_FS SOF
-  *
-  *                   field2 can have the following values:
-  *            @arg TIM_TIM2_ETR_GPIO:                TIM2_ETR is connected to GPIO
-  *            @arg TIM_TIM2_ETR_LSE:                 TIM2_ETR is connected to LSE
-  *            @arg TIM_TIM2_ETR_COMP1:               TIM2_ETR is connected to COMP1 output
-  *            @arg TIM_TIM2_ETR_COMP2:               TIM2_ETR is connected to COMP2 output
-  *
-  *                   field3 can have the following values:
-  *            @arg TIM_TIM2_TI4_GPIO:                TIM2 TI4 is connected to GPIO
-  *            @arg TIM_TIM2_TI4_COMP1:               TIM2 TI4 is connected to COMP1 output
-  *            @arg TIM_TIM2_TI4_COMP2:               TIM2 TI4 is connected to COMP2 output
-  *            @arg TIM_TIM2_TI4_COMP1_COMP2:         TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output
-  *
-  *         For TIM3, the parameter is a combination 2 fields(field1 | field2):
-  *
-  *                   field1 can have the following values:
-  *            @arg TIM_TIM3_TI1_GPIO:                TIM3 TI1 is connected to GPIO
-  *            @arg TIM_TIM3_TI1_COMP1:               TIM3 TI1 is connected to COMP1 output
-  *            @arg TIM_TIM3_TI1_COMP2:               TIM3 TI1 is connected to COMP2 output
-  *            @arg TIM_TIM3_TI1_COMP1_COMP2:         TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output
-  *
-  *                   field2 can have the following values:
-  *            @arg TIM_TIM3_ETR_GPIO:                TIM3_ETR is connected to GPIO
-  *            @arg TIM_TIM3_ETR_COMP1:               TIM3_ETR is connected to COMP1 output
-  *
-  *         For TIM8, the parameter is a combination of 3 fields (field1 | field2 | field3):
-  *
-  *                   field1 can have the following values:
-  *            @arg TIM_TIM8_ETR_ADC2_NONE:          TIM8_ETR is not connected to any ADC2 AWD (analog watchdog)
-  *            @arg TIM_TIM8_ETR_ADC2_AWD1:          TIM8_ETR is connected to ADC2 AWD1
-  *            @arg TIM_TIM8_ETR_ADC2_AWD2:          TIM8_ETR is connected to ADC2 AWD2
-  *            @arg TIM_TIM8_ETR_ADC2_AWD3:          TIM8_ETR is connected to ADC2 AWD3
-  *
-  *                   field2 can have the following values:
-  *            @arg TIM_TIM8_ETR_ADC3_NONE:          TIM8_ETR is not connected to any ADC3 AWD (analog watchdog)
-  *            @arg TIM_TIM8_ETR_ADC3_AWD1:          TIM8_ETR is connected to ADC3 AWD1
-  *            @arg TIM_TIM8_ETR_ADC3_AWD2:          TIM8_ETR is connected to ADC3 AWD2
-  *            @arg TIM_TIM8_ETR_ADC3_AWD3:          TIM8_ETR is connected to ADC3 AWD3
-  *
-  *                   field3 can have the following values:
-  *            @arg TIM_TIM8_TI1_GPIO:               TIM8 TI1 is connected to GPIO
-  *            @arg TIM_TIM8_TI1_COMP2:              TIM8 TI1 is connected to COMP2 output
-  *
-  *                   field4 can have the following values:
-  *            @arg TIM_TIM8_ETR_COMP1:               TIM8_ETR is connected to COMP1 output
-  *            @arg TIM_TIM8_ETR_COMP2:               TIM8_ETR is connected to COMP2 output
-  *            @note  When field4 is set to TIM_TIM8_ETR_COMP1 or TIM_TIM8_ETR_COMP2 field1 and field2 values are not significant 
-  *
-  *         For TIM15, the parameter is a combination of 3 fields (field1 | field2):
-  *
-  *                   field1 can have the following values:
-  *            @arg TIM_TIM15_TI1_GPIO:              TIM15 TI1 is connected to GPIO
-  *            @arg TIM_TIM15_TI1_LSE:               TIM15 TI1 is connected to LSE
-  *
-  *                   field2 can have the following values:
-  *            @arg TIM_TIM15_ENCODERMODE_NONE:      No redirection 
-  *            @arg TIM_TIM15_ENCODERMODE_TIM2:      TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
-  *            @arg TIM_TIM15_ENCODERMODE_TIM3:      TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
-  *            @arg TIM_TIM15_ENCODERMODE_TIM4:      TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
-  *
-  *         For TIM16, the parameter can have the following values:
-  *            @arg TIM_TIM16_TI1_GPIO:              TIM16 TI1 is connected to GPIO
-  *            @arg TIM_TIM16_TI1_LSI:               TIM16 TI1 is connected to LSI
-  *            @arg TIM_TIM16_TI1_LSE:               TIM16 TI1 is connected to LSE
-  *            @arg TIM_TIM16_TI1_RTC:               TIM16 TI1 is connected to RTC wakeup interrupt
-  *
-  *         For TIM17, the parameter can have the following values:
-  *            @arg TIM_TIM17_TI1_GPIO:              TIM17 TI1 is connected to GPIO
-  *            @arg TIM_TIM17_TI1_MSI:               TIM17 TI1 is connected to MSI  (contraints: MSI clock < 1/4 TIM APB clock)
-  *            @arg TIM_TIM17_TI1_HSE_32:            TIM17 TI1 is connected to HSE div 32
-  *            @arg TIM_TIM17_TI1_MCO:               TIM17 TI1 is connected to MCO
-  *
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
-{
-  uint32_t tmpor1 = 0;
-  uint32_t tmpor2 = 0;
-  
-  __HAL_LOCK(htim);
-
-  /* Check parameters */
-  assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_REMAP(Remap));
-  
-  /* Set ETR_SEL bit field (if required) */
-  if (IS_TIM_ETRSEL_INSTANCE(htim->Instance))
-  {
-    tmpor2 = htim->Instance->OR2;
-    tmpor2 &= ~TIMx_ETRSEL_MASK;
-    tmpor2 |= (Remap & TIMx_ETRSEL_MASK);
-    
-    /* Set TIMx_OR2 */
-    htim->Instance->OR2 = tmpor2;        
-  }
-  
-  /* Set other remapping capabilities */
-  tmpor1 = Remap;
-  tmpor1 &= ~TIMx_ETRSEL_MASK;
-
-  /* Set TIMx_OR1 */
-  htim->Instance->OR1 = Remap;
-  
-  /* Set TIMx_OR1 */
-  htim->Instance->OR1 = tmpor1;        
-  
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Group channel 5 and channel 1, 2 or 3
-  * @param  htim: TIM handle.
-  * @param  Channels: specifies the reference signal(s) the OC5REF is combined with.
-  *         This parameter can be any combination of the following values:
-  *         TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
-  *         TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
-  *         TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
-  *         TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
-{
-  /* Check parameters */
-  assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_GROUPCH5(Channels));
-
-  /* Process Locked */
-  __HAL_LOCK(htim);
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Clear GC5Cx bit fields */
-  htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3|TIM_CCR5_GC5C2|TIM_CCR5_GC5C1);
-
-  /* Set GC5Cx bit fields */
-  htim->Instance->CCR5 |= Channels;
-
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
-  * @brief    Extended Callbacks functions
-  *
-@verbatim
-  ==============================================================================
-                    ##### Extended Callbacks functions #####
-  ==============================================================================
-  [..]
-    This section provides Extended TIM callback functions:
-    (+) Timer Commutation callback
-    (+) Timer Break callback
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Hall commutation changed callback in non-blocking mode
-  * @param  htim : TIM handle
-  * @retval None
-  */
-__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIMEx_CommutationCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Hall Break detection callback in non-blocking mode
-  * @param  htim : TIM handle
-  * @retval None
-  */
-__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIMEx_BreakCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
-  * @brief    Extended Peripheral State functions
-  *
-@verbatim
-  ==============================================================================
-                ##### Extended Peripheral State functions #####
-  ==============================================================================
-  [..]
-    This subsection permits to get in run-time the status of the peripheral
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the TIM Hall Sensor interface handle state.
-  * @param  htim: TIM Hall Sensor handle
-  * @retval HAL state
-  */
-HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
-{
-  return htim->State;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @brief  TIM DMA Commutation callback.
-  * @param  hdma : pointer to DMA handle.
-  * @retval None
-  */
-void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  htim->State= HAL_TIM_STATE_READY;
-
-  HAL_TIMEx_CommutationCallback(htim);
-}
-
-/**
-  * @brief  Enables or disables the TIM Capture Compare Channel xN.
-  * @param  TIMx to select the TIM peripheral
-  * @param  Channel: specifies the TIM Channel
-  *          This parameter can be one of the following values:
-  *            @arg TIM_Channel_1: TIM Channel 1
-  *            @arg TIM_Channel_2: TIM Channel 2
-  *            @arg TIM_Channel_3: TIM Channel 3
-  * @param  ChannelNState: specifies the TIM Channel CCxNE bit new state.
-  *          This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
-  * @retval None
-  */
-static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
-{
-  uint32_t tmp = 0;
-
-  tmp = TIM_CCER_CC1NE << Channel;
-
-  /* Reset the CCxNE Bit */
-  TIMx->CCER &=  ~tmp;
-
-  /* Set or reset the CCxNE Bit */
-  TIMx->CCER |=  (uint32_t)(ChannelNState << Channel);
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_TIM_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/src/stm32l4xx_hal_uart.c b/stmhal/hal/l4/src/stm32l4xx_hal_uart.c
deleted file mode 100644
index adb3d79ab7..0000000000
--- a/stmhal/hal/l4/src/stm32l4xx_hal_uart.c
+++ /dev/null
@@ -1,2155 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_uart.c
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   UART HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions
-  *
-  *
-  @verbatim
- ===============================================================================
-                        ##### How to use this driver #####
- ===============================================================================
-  [..]
-    The UART HAL driver can be used as follows:
-
-    (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).
-    (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
-        (++) Enable the USARTx interface clock.
-        (++) UART pins configuration:
-            (+++) Enable the clock for the UART GPIOs.
-            (+++) Configure these UART pins as alternate function pull-up.
-        (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
-             and HAL_UART_Receive_IT() APIs):
-            (+++) Configure the USARTx interrupt priority.
-            (+++) Enable the NVIC USART IRQ handle.
-            (++) UART interrupts handling:
-              -@@-  The specific UART interrupts (Transmission complete interrupt,
-                RXNE interrupt and Error Interrupts) are managed using the macros
-                __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit and receive processes.
-        (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
-             and HAL_UART_Receive_DMA() APIs):
-            (+++) Declare a DMA handle structure for the Tx/Rx channel.
-            (+++) Enable the DMAx interface clock.
-            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
-            (+++) Configure the DMA Tx/Rx channel.
-            (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
-            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
-
-    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
-        flow control and Mode (Receiver/Transmitter) in the huart handle Init structure.
-
-    (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...)
-        in the huart handle AdvancedInit structure.
-
-    (#) For the UART asynchronous mode, initialize the UART registers by calling
-        the HAL_UART_Init() API.
-
-    (#) For the UART Half duplex mode, initialize the UART registers by calling
-        the HAL_HalfDuplex_Init() API.
-
-    (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers
-        by calling the HAL_LIN_Init() API.
-
-    (#) For the UART Multiprocessor mode, initialize the UART registers
-        by calling the HAL_MultiProcessor_Init() API.
-
-    (#) For the UART RS485 Driver Enabled mode, initialize the UART registers
-        by calling the HAL_RS485Ex_Init() API.
-
-    [..]
-    (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(),
-        also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by
-        calling the customized HAL_UART_MspInit() API.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup UART UART
-  * @brief HAL UART module driver
-  * @{
-  */
-
-#ifdef HAL_UART_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup UART_Private_Constants UART Private Constants
-  * @{
-  */
-#define UART_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
-                                     USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
-
-#define UART_LPUART_BRR_MIN           ((uint32_t)0x00000300)  /* LPUART BRR minimum authorized value */
-#define UART_LPUART_BRR_MAX           ((uint32_t)0x000FFFFF)  /* LPUART BRR maximum authorized value */                                                                      
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup UART_Private_Functions
-  * @{
-  */
-static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMAError(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
-static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
-static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup UART_Exported_Functions UART Exported Functions
-  * @{
-  */
-
-/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
-  *  @brief    Initialization and Configuration functions
-  *
-@verbatim
-===============================================================================
-            ##### Initialization and Configuration functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
-    in asynchronous mode.
-      (+) For the asynchronous mode the parameters below can be configured:
-        (++) Baud Rate
-        (++) Word Length
-        (++) Stop Bit
-        (++) Parity: If the parity is enabled, then the MSB bit of the data written
-             in the data register is transmitted but is changed by the parity bit.
-        (++) Hardware flow control
-        (++) Receiver/transmitter modes
-        (++) Over Sampling Method
-        (++) One-Bit Sampling Method
-      (+) For the asynchronous mode, the following advanced features can be configured as well:
-        (++) TX and/or RX pin level inversion
-        (++) data logical level inversion
-        (++) RX and TX pins swap
-        (++) RX overrun detection disabling
-        (++) DMA disabling on RX error
-        (++) MSB first on communication line
-        (++) auto Baud rate detection
-    [..]
-    The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API
-    follow respectively the UART asynchronous, UART Half duplex, UART LIN mode
-    and UART multiprocessor mode configuration procedures (details for the procedures
-    are available in reference manual).
-
-@endverbatim
-
-  Depending on the frame length defined by the M1 and M0 bits (7-bit, 
-  8-bit or 9-bit), the possible UART formats are listed in the 
-  following table.
-  
-  Table 1. UART frame format.
-    +-----------------------------------------------------------------------+
-    |  M1 bit |  M0 bit |  PCE bit  |             UART frame                |
-    |---------|---------|-----------|---------------------------------------|
-    |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
-    |---------|---------|-----------|---------------------------------------|
-    |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
-    |---------|---------|-----------|---------------------------------------|
-    |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
-    |---------|---------|-----------|---------------------------------------|
-    |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
-    |---------|---------|-----------|---------------------------------------|
-    |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
-    |---------|---------|-----------|---------------------------------------|
-    |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
-    +-----------------------------------------------------------------------+
-
-  * @{
-  */
-
-/**
-  * @brief Initialize the UART mode according to the specified
-  *         parameters in the UART_InitTypeDef and initialize the associated handle.
-  * @param huart: UART handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
-{
-  /* Check the UART handle allocation */
-  if(huart == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
-  {
-    /* Check the parameters */
-    assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
-  }
-  else
-  {
-    /* Check the parameters */
-    assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
-  }
-
-  if(huart->State == HAL_UART_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    huart->Lock = HAL_UNLOCKED;
-
-    /* Init the low level hardware : GPIO, CLOCK */
-    HAL_UART_MspInit(huart);
-  }
-
-  huart->State = HAL_UART_STATE_BUSY;
-
-  /* Disable the Peripheral */
-  __HAL_UART_DISABLE(huart);
-
-  /* Set the UART Communication parameters */
-  if (UART_SetConfig(huart) == HAL_ERROR)
-  {
-    return HAL_ERROR;
-  }
-
-  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
-  {
-    UART_AdvFeatureConfig(huart);
-  }
-
-  /* In asynchronous mode, the following bits must be kept cleared:
-  - LINEN and CLKEN bits in the USART_CR2 register,
-  - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
-  huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
-  huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
-
-  /* Enable the Peripheral */
-  __HAL_UART_ENABLE(huart);
-
-  /* TEACK and/or REACK to check before moving huart->State to Ready */
-  return (UART_CheckIdleState(huart));
-}
-
-/**
-  * @brief Initialize the half-duplex mode according to the specified
-  *         parameters in the UART_InitTypeDef and creates the associated handle.
-  * @param huart: UART handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
-{
-  /* Check the UART handle allocation */
-  if(huart == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check UART instance */
-  assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
-
-  if(huart->State == HAL_UART_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    huart->Lock = HAL_UNLOCKED;
-  
-    /* Init the low level hardware : GPIO, CLOCK */
-    HAL_UART_MspInit(huart);
-  }
-
-  huart->State = HAL_UART_STATE_BUSY;
-
-  /* Disable the Peripheral */
-  __HAL_UART_DISABLE(huart);
-
-  /* Set the UART Communication parameters */
-  if (UART_SetConfig(huart) == HAL_ERROR)
-  {
-    return HAL_ERROR;
-  }
-
-  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
-  {
-    UART_AdvFeatureConfig(huart);
-  }
-
-  /* In half-duplex mode, the following bits must be kept cleared:
-  - LINEN and CLKEN bits in the USART_CR2 register,
-  - SCEN and IREN bits in the USART_CR3 register.*/
-  huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
-  huart->Instance->CR3 &= ~(USART_CR3_IREN | USART_CR3_SCEN);
-
-  /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
-  huart->Instance->CR3 |= USART_CR3_HDSEL;
-
-  /* Enable the Peripheral */
-  __HAL_UART_ENABLE(huart);
-
-  /* TEACK and/or REACK to check before moving huart->State to Ready */
-  return (UART_CheckIdleState(huart));
-}
-
-
-/**
-  * @brief Initialize the LIN mode according to the specified
-  *         parameters in the UART_InitTypeDef and creates the associated handle .
-  * @param huart: UART handle.
-  * @param BreakDetectLength: specifies the LIN break detection length.
-  *        This parameter can be one of the following values:
-  *          @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection
-  *          @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
-{
-  /* Check the UART handle allocation */
-  if(huart == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the LIN UART instance */
-  assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
-  /* Check the Break detection length parameter */
-  assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
-
-  /* LIN mode limited to 16-bit oversampling only */
-  if(huart->Init.OverSampling == UART_OVERSAMPLING_8)
-  {
-    return HAL_ERROR;
-  }
-  /* LIN mode limited to 8-bit data length */
-  if(huart->Init.WordLength != UART_WORDLENGTH_8B)
-  {
-    return HAL_ERROR;
-  }
-
-  if(huart->State == HAL_UART_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    huart->Lock = HAL_UNLOCKED;
-  
-    /* Init the low level hardware : GPIO, CLOCK */
-    HAL_UART_MspInit(huart);
-  }
-
-  huart->State = HAL_UART_STATE_BUSY;
-
-  /* Disable the Peripheral */
-  __HAL_UART_DISABLE(huart);
-
-  /* Set the UART Communication parameters */
-  if (UART_SetConfig(huart) == HAL_ERROR)
-  {
-    return HAL_ERROR;
-  }
-
-  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
-  {
-    UART_AdvFeatureConfig(huart);
-  }
-
-  /* In LIN mode, the following bits must be kept cleared:
-  - LINEN and CLKEN bits in the USART_CR2 register,
-  - SCEN and IREN bits in the USART_CR3 register.*/
-  huart->Instance->CR2 &= ~(USART_CR2_CLKEN);
-  huart->Instance->CR3 &= ~(USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN);
-
-  /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
-  huart->Instance->CR2 |= USART_CR2_LINEN;
-
-  /* Set the USART LIN Break detection length. */
-  MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);
-
-    /* Enable the Peripheral */
-  __HAL_UART_ENABLE(huart);
-
-  /* TEACK and/or REACK to check before moving huart->State to Ready */
-  return (UART_CheckIdleState(huart));
-}
-
-
-
-/**
-  * @brief Initialize the multiprocessor mode according to the specified
-  *         parameters in the UART_InitTypeDef and initialize the associated handle.
-  * @param huart: UART handle.
-  * @param Address: UART node address (4-, 6-, 7- or 8-bit long).
-  * @param WakeUpMethod: specifies the UART wakeup method.
-  *        This parameter can be one of the following values:
-  *          @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection
-  *          @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark
-  * @note  If the user resorts to idle line detection wake up, the Address parameter
-  *        is useless and ignored by the initialization function.
-  * @note  If the user resorts to address mark wake up, the address length detection
-  *        is configured by default to 4 bits only. For the UART to be able to
-  *        manage 6-, 7- or 8-bit long addresses detection, the API
-  *        HAL_MultiProcessorEx_AddressLength_Set() must be called after
-  *        HAL_MultiProcessor_Init().
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
-{
-  /* Check the UART handle allocation */
-  if(huart == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the wake up method parameter */
-  assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
-
-  if(huart->State == HAL_UART_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    huart->Lock = HAL_UNLOCKED;
-  
-    /* Init the low level hardware : GPIO, CLOCK */
-    HAL_UART_MspInit(huart);
-  }
-
-  huart->State = HAL_UART_STATE_BUSY;
-
-  /* Disable the Peripheral */
-  __HAL_UART_DISABLE(huart);
-
-  /* Set the UART Communication parameters */
-  if (UART_SetConfig(huart) == HAL_ERROR)
-  {
-    return HAL_ERROR;
-  }
-
-  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
-  {
-    UART_AdvFeatureConfig(huart);
-  }
-
-  /* In multiprocessor mode, the following bits must be kept cleared:
-  - LINEN and CLKEN bits in the USART_CR2 register,
-  - SCEN, HDSEL and IREN  bits in the USART_CR3 register. */
-  huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
-  huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
-
-  if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK)
-  {
-    /* If address mark wake up method is chosen, set the USART address node */
-    MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS));
-  }
-
-  /* Set the wake up method by setting the WAKE bit in the CR1 register */
-  MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);
-
-  /* Enable the Peripheral */
-  __HAL_UART_ENABLE(huart);
-
-  /* TEACK and/or REACK to check before moving huart->State to Ready */
-  return (UART_CheckIdleState(huart));
-}
-
-
-
-
-/**
-  * @brief DeInitialize the UART peripheral.
-  * @param huart: UART handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
-{
-  /* Check the UART handle allocation */
-  if(huart == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
-
-  huart->State = HAL_UART_STATE_BUSY;
-
-  /* Disable the Peripheral */
-  __HAL_UART_DISABLE(huart);
-
-  huart->Instance->CR1 = 0x0;
-  huart->Instance->CR2 = 0x0;
-  huart->Instance->CR3 = 0x0;
-
-  /* DeInit the low level hardware */
-  HAL_UART_MspDeInit(huart);
-
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
-  huart->State = HAL_UART_STATE_RESET;
-
-  /* Process Unlock */
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Initialize the UART MSP.
-  * @param huart: UART handle.
-  * @retval None
-  */
-__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_UART_MspInit can be implemented in the user file
-   */
-}
-
-/**
-  * @brief DeInitialize the UART MSP.
-  * @param huart: UART handle.
-  * @retval None
-  */
-__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_UART_MspDeInit can be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup UART_Exported_Functions_Group2 IO operation functions
-  *  @brief UART Transmit/Receive functions
-  *
-@verbatim
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================
-    This subsection provides a set of functions allowing to manage the UART asynchronous
-    and Half duplex data transfers.
-
-    (#) There are two mode of transfer:
-       (+) Blocking mode: The communication is performed in polling mode.
-            The HAL status of all data processing is returned by the same function
-            after finishing transfer.
-       (+) No-Blocking mode: The communication is performed using Interrupts
-           or DMA, These API's return the HAL status.
-           The end of the data processing will be indicated through the
-           dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
-           using DMA mode.
-           The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
-           will be executed respectively at the end of the transmit or Receive process
-           The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected
-
-    (#) Blocking mode API's are :
-        (+) HAL_UART_Transmit()
-        (+) HAL_UART_Receive()
-
-    (#) Non-Blocking mode API's with Interrupt are :
-        (+) HAL_UART_Transmit_IT()
-        (+) HAL_UART_Receive_IT()
-        (+) HAL_UART_IRQHandler()
-
-    (#) No-Blocking mode API's with DMA are :
-        (+) HAL_UART_Transmit_DMA()
-        (+) HAL_UART_Receive_DMA()
-        (+) HAL_UART_DMAPause()
-        (+) HAL_UART_DMAResume()
-        (+) HAL_UART_DMAStop()
-
-    (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
-        (+) HAL_UART_TxHalfCpltCallback()
-        (+) HAL_UART_TxCpltCallback()
-        (+) HAL_UART_RxHalfCpltCallback()
-        (+) HAL_UART_RxCpltCallback()
-        (+) HAL_UART_ErrorCallback()
-
-
-    -@- In the Half duplex communication, it is forbidden to run the transmit
-        and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Send an amount of data in blocking mode.
-  * @param huart: UART handle.
-  * @param pData: Pointer to data buffer.
-  * @param Size: Amount of data to be sent.
-  * @param Timeout: Timeout duration.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-   uint16_t* tmp;
-
-  if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX))
-  {
-    if((pData == NULL ) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(huart);
-
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
-    /* Check if a non-blocking receive process is ongoing or not */
-    if(huart->State == HAL_UART_STATE_BUSY_RX)
-    {
-      huart->State = HAL_UART_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      huart->State = HAL_UART_STATE_BUSY_TX;
-    }
-
-    huart->TxXferSize = Size;
-    huart->TxXferCount = Size;
-    while(huart->TxXferCount > 0)
-    {
-      huart->TxXferCount--;
-        if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, Timeout) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
-      {
-        tmp = (uint16_t*) pData;
-        huart->Instance->TDR = (*tmp & (uint16_t)0x01FF);
-        pData += 2;
-      }
-      else
-      {
-        huart->Instance->TDR = (*pData++ & (uint8_t)0xFF);
-      }
-    }
-    if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-    /* Check if a non-blocking receive Process is ongoing or not */
-    if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
-    {
-      huart->State = HAL_UART_STATE_BUSY_RX;
-    }
-    else
-    {
-      huart->State = HAL_UART_STATE_READY;
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(huart);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Receive an amount of data in blocking mode.
-  * @param huart: UART handle.
-  * @param pData: pointer to data buffer.
-  * @param Size: amount of data to be received.
-  * @param Timeout: Timeout duration.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint16_t* tmp;
-  uint16_t uhMask;
-
-  if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX))
-  {
-    if((pData == NULL ) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(huart);
-
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
-    /* Check if a non-blocking transmit process is ongoing or not */
-    if(huart->State == HAL_UART_STATE_BUSY_TX)
-    {
-      huart->State = HAL_UART_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      huart->State = HAL_UART_STATE_BUSY_RX;
-    }
-
-    huart->RxXferSize = Size;
-    huart->RxXferCount = Size;
-
-    /* Computation of UART mask to apply to RDR register */
-    UART_MASK_COMPUTATION(huart);
-    uhMask = huart->Mask;
-
-    /* as long as data have to be received */
-    while(huart->RxXferCount > 0)
-    {
-      huart->RxXferCount--;
-        if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
-      {
-        tmp = (uint16_t*) pData ;
-        *tmp = (uint16_t)(huart->Instance->RDR & uhMask);
-        pData +=2;
-      }
-      else
-      {
-        *pData++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
-      }
-    }
-
-    /* Check if a non-blocking transmit Process is ongoing or not */
-    if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
-    {
-      huart->State = HAL_UART_STATE_BUSY_TX;
-    }
-    else
-    {
-      huart->State = HAL_UART_STATE_READY;
-    }
-    /* Process Unlocked */
-    __HAL_UNLOCK(huart);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Send an amount of data in interrupt mode.
-  * @param huart: UART handle.
-  * @param pData: pointer to data buffer.
-  * @param Size: amount of data to be sent.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
-  if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX))
-  {
-    if((pData == NULL ) || (Size == 0))
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(huart);
-
-    huart->pTxBuffPtr = pData;
-    huart->TxXferSize = Size;
-    huart->TxXferCount = Size;
-
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
-    /* Check if a receive process is ongoing or not */
-    if(huart->State == HAL_UART_STATE_BUSY_RX)
-    {
-      huart->State = HAL_UART_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      huart->State = HAL_UART_STATE_BUSY_TX;
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(huart);
-
-    /* Enable the UART Transmit Data Register Empty Interrupt */
-    __HAL_UART_ENABLE_IT(huart, UART_IT_TXE);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Receive an amount of data in interrupt mode.
-  * @param huart: UART handle.
-  * @param pData: pointer to data buffer.
-  * @param Size: amount of data to be received.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
-  if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX))
-  {
-    if((pData == NULL ) || (Size == 0))
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(huart);
-
-    huart->pRxBuffPtr = pData;
-    huart->RxXferSize = Size;
-    huart->RxXferCount = Size;
-
-    /* Computation of UART mask to apply to RDR register */
-    UART_MASK_COMPUTATION(huart);
-
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
-    /* Check if a transmit process is ongoing or not */
-    if(huart->State == HAL_UART_STATE_BUSY_TX)
-    {
-      huart->State = HAL_UART_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      huart->State = HAL_UART_STATE_BUSY_RX;
-    }
-
-    /* Enable the UART Parity Error Interrupt */
-    __HAL_UART_ENABLE_IT(huart, UART_IT_PE);
-
-    /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
-    __HAL_UART_ENABLE_IT(huart, UART_IT_ERR);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(huart);
-
-    /* Enable the UART Data Register not empty Interrupt */
-    __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Send an amount of data in DMA mode.
-  * @param huart: UART handle.
-  * @param pData: pointer to data buffer.
-  * @param Size: amount of data to be sent.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
-  uint32_t *tmp;
-
-  if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX))
-  {
-    if((pData == NULL ) || (Size == 0))
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(huart);
-
-    huart->pTxBuffPtr = pData;
-    huart->TxXferSize = Size;
-    huart->TxXferCount = Size;
-
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
-    /* Check if a receive process is ongoing or not */
-    if(huart->State == HAL_UART_STATE_BUSY_RX)
-    {
-      huart->State = HAL_UART_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      huart->State = HAL_UART_STATE_BUSY_TX;
-    }
-
-    /* Set the UART DMA transfer complete callback */
-    huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
-
-    /* Set the UART DMA Half transfer complete callback */
-    huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
-
-    /* Set the DMA error callback */
-    huart->hdmatx->XferErrorCallback = UART_DMAError;
-
-    /* Enable the UART transmit DMA channel */
-    tmp = (uint32_t*)&pData;
-    HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t*)tmp, (uint32_t)&huart->Instance->TDR, Size);
-
-    /* Clear the TC flag in the ICR register */
-    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
-
-    /* Enable the DMA transfer for transmit request by setting the DMAT bit
-       in the UART CR3 register */
-    huart->Instance->CR3 |= USART_CR3_DMAT;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(huart);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Receive an amount of data in DMA mode.
-  * @param huart: UART handle.
-  * @param pData: pointer to data buffer.
-  * @param Size: amount of data to be received.
-  * @note   When the UART parity is enabled (PCE = 1), the received data contain
-  *         the parity bit (MSB position).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
-  uint32_t *tmp;
-
-  if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX))
-  {
-    if((pData == NULL ) || (Size == 0))
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(huart);
-
-    huart->pRxBuffPtr = pData;
-    huart->RxXferSize = Size;
-
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
-    /* Check if a transmit process is ongoing or not */
-    if(huart->State == HAL_UART_STATE_BUSY_TX)
-    {
-      huart->State = HAL_UART_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      huart->State = HAL_UART_STATE_BUSY_RX;
-    }
-
-    /* Set the UART DMA transfer complete callback */
-    huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
-
-    /* Set the UART DMA Half transfer complete callback */
-    huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
-
-    /* Set the DMA error callback */
-    huart->hdmarx->XferErrorCallback = UART_DMAError;
-
-    /* Enable the DMA channel */
-    tmp = (uint32_t*)&pData;
-    HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, *(uint32_t*)tmp, Size);
-
-    /* Enable the DMA transfer for the receiver request by setting the DMAR bit
-       in the UART CR3 register */
-     huart->Instance->CR3 |= USART_CR3_DMAR;
-
-     /* Process Unlocked */
-     __HAL_UNLOCK(huart);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Pause the DMA Transfer.
-  * @param huart: UART handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
-{
-  /* Process Locked */
-  __HAL_LOCK(huart);
-
-  if(huart->State == HAL_UART_STATE_BUSY_TX)
-  {
-    /* Disable the UART DMA Tx request */
-    huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
-  }
-  else if(huart->State == HAL_UART_STATE_BUSY_RX)
-  {
-    /* Disable the UART DMA Rx request */
-    huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
-  }
-  else if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
-  {
-    /* Disable the UART DMA Tx request */
-    huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
-    /* Disable the UART DMA Rx request */
-    huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Resume the DMA Transfer.
-  * @param huart: UART handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
-{
-  /* Process Locked */
-  __HAL_LOCK(huart);
-
-  if(huart->State == HAL_UART_STATE_BUSY_TX)
-  {
-    /* Enable the UART DMA Tx request */
-    huart->Instance->CR3 |= USART_CR3_DMAT;
-  }
-  else if(huart->State == HAL_UART_STATE_BUSY_RX)
-  {
-    /* Clear the Overrun flag before resuming the Rx transfer */
-    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
-
-    /* Enable the UART DMA Rx request */
-    huart->Instance->CR3 |= USART_CR3_DMAR;
-  }
-  else if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
-  {
-    /* Clear the Overrun flag before resuming the Rx transfer */
-    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
-
-    /* Enable the UART DMA Rx request  before the DMA Tx request */
-    huart->Instance->CR3 |= USART_CR3_DMAR;
-
-    /* Enable the UART DMA Tx request */
-    huart->Instance->CR3 |= USART_CR3_DMAT;
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Stop the DMA Transfer.
-  * @param huart: UART handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
-{
-  /* The Lock is not implemented on this API to allow the user application
-     to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() /
-     HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback: 
-     indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete  
-     interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of 
-     the stream and the corresponding call back is executed. */
-
-  /* Disable the UART Tx/Rx DMA requests */
-  huart->Instance->CR3 &= ~USART_CR3_DMAT;
-  huart->Instance->CR3 &= ~USART_CR3_DMAR;
-
-  /* Abort the UART DMA tx channel */
-  if(huart->hdmatx != NULL)
-  {
-    HAL_DMA_Abort(huart->hdmatx);
-  }
-  /* Abort the UART DMA rx channel */
-  if(huart->hdmarx != NULL)
-  {
-    HAL_DMA_Abort(huart->hdmarx);
-  }
-
-  huart->State = HAL_UART_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Handle UART interrupt request.
-  * @param huart: UART handle.
-  * @retval None
-  */
-void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
-{
-  /* UART parity error interrupt occurred -------------------------------------*/
-  if((__HAL_UART_GET_IT(huart, UART_IT_PE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_PE) != RESET))
-  {
-    __HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF);
-
-    huart->ErrorCode |= HAL_UART_ERROR_PE;
-    /* Set the UART state ready to be able to start again the process */
-    huart->State = HAL_UART_STATE_READY;
-  }
-
-  /* UART frame error interrupt occurred --------------------------------------*/
-  if((__HAL_UART_GET_IT(huart, UART_IT_FE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET))
-  {
-    __HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF);
-
-    huart->ErrorCode |= HAL_UART_ERROR_FE;
-    /* Set the UART state ready to be able to start again the process */
-    huart->State = HAL_UART_STATE_READY;
-  }
-
-  /* UART noise error interrupt occurred --------------------------------------*/
-  if((__HAL_UART_GET_IT(huart, UART_IT_NE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET))
-  {
-    __HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF);
-
-    huart->ErrorCode |= HAL_UART_ERROR_NE;
-    /* Set the UART state ready to be able to start again the process */
-    huart->State = HAL_UART_STATE_READY;
-  }
-
-  /* UART Over-Run interrupt occurred -----------------------------------------*/
-  if((__HAL_UART_GET_IT(huart, UART_IT_ORE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET))
-  {
-    __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF);
-
-    huart->ErrorCode |= HAL_UART_ERROR_ORE;
-    /* Set the UART state ready to be able to start again the process */
-    huart->State = HAL_UART_STATE_READY;
-  }
-
-   /* Call UART Error Call back function if need be --------------------------*/
-  if(huart->ErrorCode != HAL_UART_ERROR_NONE)
-  {
-    HAL_UART_ErrorCallback(huart);
-  }
-
-  /* UART wakeup from Stop mode interrupt occurred -------------------------------------*/
-  if((__HAL_UART_GET_IT(huart, UART_IT_WUF) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_WUF) != RESET))
-  {
-    __HAL_UART_CLEAR_IT(huart, UART_CLEAR_WUF);
-    /* Set the UART state ready to be able to start again the process */
-    huart->State = HAL_UART_STATE_READY;
-    HAL_UARTEx_WakeupCallback(huart);
-  }
-
-  /* UART in mode Receiver ---------------------------------------------------*/
-  if((__HAL_UART_GET_IT(huart, UART_IT_RXNE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE) != RESET))
-  {
-    UART_Receive_IT(huart);
-  }
-
-
-  /* UART in mode Transmitter ------------------------------------------------*/
- if((__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET) &&(__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE) != RESET))
-  {
-    UART_Transmit_IT(huart);
-  }
-
-  /* UART in mode Transmitter (transmission end) -----------------------------*/
- if((__HAL_UART_GET_IT(huart, UART_IT_TC) != RESET) &&(__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET))
-  {
-    UART_EndTransmit_IT(huart);
-  }
-
-}
-
-/**
-  * @brief Tx Transfer completed callback.
-  * @param huart: UART handle.
-  * @retval None
-  */
-__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_UART_TxCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  Tx Half Transfer completed callback.
-  * @param  huart: UART handle.
-  * @retval None
-  */
-__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_UART_TxHalfCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief Rx Transfer completed callback.
-  * @param huart: UART handle.
-  * @retval None
-  */
-__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_UART_RxCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  Rx Half Transfer completed callback.
-  * @param  huart: UART handle.
-  * @retval None
-  */
-__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_UART_RxHalfCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief UART error callback.
-  * @param huart: UART handle.
-  * @retval None
-  */
-__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_UART_ErrorCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
-  *  @brief   UART control functions
-  *
-@verbatim
- ===============================================================================
-                      ##### Peripheral Control functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to control the UART.
-     (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
-     (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
-     (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
-     (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
-     (+) UART_SetConfig() API configures the UART peripheral
-     (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features
-     (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization
-     (+) UART_Wakeup_AddressConfig() API configures the wake-up from stop mode parameters
-     (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
-     (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
-     (+) HAL_LIN_SendBreak() API transmits the break characters
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Enable UART in mute mode (does not mean UART enters mute mode;
-  * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
-  * @param huart: UART handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
-{
-  /* Process Locked */
-  __HAL_LOCK(huart);
-
-  huart->State = HAL_UART_STATE_BUSY;
-
-  /* Enable USART mute mode by setting the MME bit in the CR1 register */
-  huart->Instance->CR1 |= USART_CR1_MME;
-
-  huart->State = HAL_UART_STATE_READY;
-
-  return (UART_CheckIdleState(huart));
-}
-
-/**
-  * @brief Disable UART mute mode (does not mean the UART actually exits mute mode
-  * as it may not have been in mute mode at this very moment).
-  * @param huart: UART handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
-{
-  /* Process Locked */
-  __HAL_LOCK(huart);
-
-  huart->State = HAL_UART_STATE_BUSY;
-
-   /* Disable USART mute mode by clearing the MME bit in the CR1 register */
-  huart->Instance->CR1 &= ~(USART_CR1_MME);
-
-  huart->State = HAL_UART_STATE_READY;
-
-  return (UART_CheckIdleState(huart));
-}
-
-/**
-  * @brief Enter UART mute mode (means UART actually enters mute mode).
-  * @note  To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
-  * @param huart: UART handle.
-  * @retval None
-  */
-void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
-{
-  __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);
-}
-
-/**
-  * @brief  Enable the UART transmitter and disable the UART receiver.
-  * @param  huart: UART handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
-{
-  /* Process Locked */
-  __HAL_LOCK(huart);
-  huart->State = HAL_UART_STATE_BUSY;
-
-  /* Clear TE and RE bits */
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
-  /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
-  SET_BIT(huart->Instance->CR1, USART_CR1_TE);
-
-  huart->State= HAL_UART_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enable the UART receiver and disable the UART transmitter.
-  * @param  huart: UART handle.
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
-{
-  /* Process Locked */
-  __HAL_LOCK(huart);
-  huart->State = HAL_UART_STATE_BUSY;
-
-  /* Clear TE and RE bits */
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
-  /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
-  SET_BIT(huart->Instance->CR1, USART_CR1_RE);
-
-  huart->State = HAL_UART_STATE_READY;
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  Transmit break characters.
-  * @param  huart: UART handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
-{
-  /* Check the parameters */
-  assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
-
-  /* Process Locked */
-  __HAL_LOCK(huart);
-
-  huart->State = HAL_UART_STATE_BUSY;
-
-  /* Send break characters */
-  huart->Instance->RQR |= UART_SENDBREAK_REQUEST;
-
-  huart->State = HAL_UART_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-
-/**
-  * @}
-  */
-
-/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions
- *  @brief   UART Peripheral State functions
- *
-@verbatim
-  ==============================================================================
-            ##### Peripheral State and Error functions #####
-  ==============================================================================
-    [..]
-    This subsection provides functions allowing to :
-      (+) Return the UART handle state.
-      (+) Return the UART handle error code
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Return the UART handle state.
-  * @param  huart : pointer to a UART_HandleTypeDef structure that contains
-  *              the configuration information for the specified UART.
-  * @retval HAL state
-  */
-HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
-{
-  return huart->State;
-}
-
-/**
-* @brief  Return the UART handle error code.
-* @param  huart : pointer to a UART_HandleTypeDef structure that contains
-  *              the configuration information for the specified UART.
-* @retval UART Error Code
-*/
-uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
-{
-  return huart->ErrorCode;
-}
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup UART_Private_Functions UART Private Functions
-  * @{
-  */
-
-/**
-  * @brief Configure the UART peripheral.
-  * @param huart: UART handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
-{
-  uint32_t tmpreg                     = 0x00000000;
-  UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED;
-  uint16_t brrtemp                    = 0x0000;
-  uint16_t usartdiv                   = 0x0000;
-  HAL_StatusTypeDef ret               = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
-  assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
-  if(UART_INSTANCE_LOWPOWER(huart))
-  {
-    assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits));  
-  }
-  else
-  {
-    assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
-    assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
-  }
-
-  assert_param(IS_UART_PARITY(huart->Init.Parity));
-  assert_param(IS_UART_MODE(huart->Init.Mode));
-  assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
-  assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
-
-
-  /*-------------------------- USART CR1 Configuration -----------------------*/
-  /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure
-   *  the UART Word Length, Parity, Mode and oversampling:
-   *  set the M bits according to huart->Init.WordLength value
-   *  set PCE and PS bits according to huart->Init.Parity value
-   *  set TE and RE bits according to huart->Init.Mode value
-   *  set OVER8 bit according to huart->Init.OverSampling value */
-  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
-  MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
-
-  /*-------------------------- USART CR2 Configuration -----------------------*/
-  /* Configure the UART Stop Bits: Set STOP[13:12] bits according
-   * to huart->Init.StopBits value */
-  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
-
-  /*-------------------------- USART CR3 Configuration -----------------------*/
-  /* Configure
-   * - UART HardWare Flow Control: set CTSE and RTSE bits according
-   *   to huart->Init.HwFlowCtl value
-   * - one-bit sampling method versus three samples' majority rule according
-   *   to huart->Init.OneBitSampling (not applicable to LPUART) */
-  tmpreg = (uint32_t)huart->Init.HwFlowCtl;
-  if (!(UART_INSTANCE_LOWPOWER(huart)))
-  {
-    tmpreg |= huart->Init.OneBitSampling;
-  }
-  MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT), tmpreg);
-
-  /*-------------------------- USART BRR Configuration -----------------------*/
-  UART_GETCLOCKSOURCE(huart, clocksource);
-
-  /* Check LPUART instance */
-  if(UART_INSTANCE_LOWPOWER(huart))
-  {
-    /* Retrieve frequency clock */
-    tmpreg = 0;
-
-    switch (clocksource)
-    {
-    case UART_CLOCKSOURCE_PCLK1:
-      tmpreg = HAL_RCC_GetPCLK1Freq();
-      break;
-    case UART_CLOCKSOURCE_HSI:
-      tmpreg = (uint32_t) HSI_VALUE;
-      break;
-    case UART_CLOCKSOURCE_SYSCLK:
-      tmpreg = HAL_RCC_GetSysClockFreq();
-      break;
-    case UART_CLOCKSOURCE_LSE:
-      tmpreg = (uint32_t) LSE_VALUE;
-      break;
-    case UART_CLOCKSOURCE_UNDEFINED:
-    default:
-        ret = HAL_ERROR;
-      break;
-    }
-
-    /* if proper clock source reported */
-    if (tmpreg != 0)
-    {
-      /* ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
-      if ( (tmpreg < (3 * huart->Init.BaudRate) ) ||
-           (tmpreg > (4096 * huart->Init.BaudRate) ))
-      {
-        ret = HAL_ERROR;
-      }
-      else
-      {
-        switch (clocksource)
-        {
-        case UART_CLOCKSOURCE_PCLK1:
-            tmpreg = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
-          break;
-        case UART_CLOCKSOURCE_HSI:
-            tmpreg = (uint32_t)(UART_DIV_LPUART(HSI_VALUE, huart->Init.BaudRate));
-          break;
-        case UART_CLOCKSOURCE_SYSCLK:
-            tmpreg = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
-          break;
-        case UART_CLOCKSOURCE_LSE:
-            tmpreg = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate));
-          break;
-        case UART_CLOCKSOURCE_UNDEFINED:
-        default:
-            ret = HAL_ERROR;
-          break;
-        }
-   
-        if ((tmpreg >= UART_LPUART_BRR_MIN) && (tmpreg <= UART_LPUART_BRR_MAX))
-        {
-           huart->Instance->BRR = tmpreg;
-        }
-        else
-        {
-          ret = HAL_ERROR;
-        }
-      }  /*   if ( (tmpreg < (3 * huart->Init.BaudRate) ) || (tmpreg > (4096 * huart->Init.BaudRate) )) */
-    } /* if (tmpreg != 0) */
-  }
-  /* Check UART Over Sampling to set Baud Rate Register */
-  else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
-  {
-    switch (clocksource)
-    {
-    case UART_CLOCKSOURCE_PCLK1:
-        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
-      break;
-    case UART_CLOCKSOURCE_PCLK2:
-        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
-      break;
-    case UART_CLOCKSOURCE_HSI:
-        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate));
-      break;
-    case UART_CLOCKSOURCE_SYSCLK:
-        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
-      break;
-    case UART_CLOCKSOURCE_LSE:
-        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate));
-      break;
-    case UART_CLOCKSOURCE_UNDEFINED:
-    default:
-        ret = HAL_ERROR;
-      break;
-    }
-
-    brrtemp = usartdiv & 0xFFF0;
-    brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000F) >> 1U);
-    huart->Instance->BRR = brrtemp;
-  }
-  else
-  {
-    switch (clocksource)
-    {
-    case UART_CLOCKSOURCE_PCLK1:
-        huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
-      break;
-    case UART_CLOCKSOURCE_PCLK2:
-        huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
-      break;
-    case UART_CLOCKSOURCE_HSI:
-        huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));
-      break;
-    case UART_CLOCKSOURCE_SYSCLK:
-        huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
-      break;
-    case UART_CLOCKSOURCE_LSE:
-        huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate));
-      break;
-    case UART_CLOCKSOURCE_UNDEFINED:
-    default:
-        ret = HAL_ERROR;
-      break;
-    }
-  }
-
-  return ret;
-
-}
-
-/**
-  * @brief Configure the UART peripheral advanced features.
-  * @param huart: UART handle.
-  * @retval None
-  */
-void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
-{
-  /* Check whether the set of advanced features to configure is properly set */
-  assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
-
-  /* if required, configure TX pin active level inversion */
-  if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
-  {
-    assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
-    MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
-  }
-
-  /* if required, configure RX pin active level inversion */
-  if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
-  {
-    assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
-    MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
-  }
-
-  /* if required, configure data inversion */
-  if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
-  {
-    assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
-    MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
-  }
-
-  /* if required, configure RX/TX pins swap */
-  if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
-  {
-    assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
-    MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
-  }
-
-  /* if required, configure RX overrun detection disabling */
-  if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
-  {
-    assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
-    MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
-  }
-
-  /* if required, configure DMA disabling on reception error */
-  if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
-  {
-    assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
-    MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
-  }
-
-  /* if required, configure auto Baud rate detection scheme */
-  if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
-  {
-    assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
-    assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
-    MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
-    /* set auto Baudrate detection parameters if detection is enabled */
-    if(huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
-    {
-      assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
-      MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
-    }
-  }
-
-  /* if required, configure MSB first on communication line */
-  if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
-  {
-    assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
-    MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
-  }
-}
-
-/**
-  * @brief Check the UART Idle State.
-  * @param huart: UART handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
-{
-  /* Initialize the UART ErrorCode */
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
-
-  /* Check if the Transmitter is enabled */
-  if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
-  {
-    /* Wait until TEACK flag is set */
-    if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
-    {
-      /* Timeout occurred */
-      return HAL_TIMEOUT;
-    }
-  }
-  /* Check if the Receiver is enabled */
-  if((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
-  {
-    /* Wait until REACK flag is set */
-    if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET,  HAL_UART_TIMEOUT_VALUE) != HAL_OK)
-    {
-      /* Timeout occurred */
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Initialize the UART State */
-  huart->State= HAL_UART_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief DMA UART transmit process complete callback.
-  * @param hdma: DMA handle.
-  * @retval None
-  */
-static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  /* DMA Normal mode */
-  if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
-  {  
-    huart->TxXferCount = 0;
-  
-    /* Disable the DMA transfer for transmit request by resetting the DMAT bit
-    in the UART CR3 register */
-    huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT);
-
-    /* Enable the UART Transmit Complete Interrupt */
-    __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
-  }
-  /* DMA Circular mode */
-  else
-  {
-    HAL_UART_TxCpltCallback(huart);
-  }
-
-}
-
-/**
-  * @brief DMA UART transmit process half complete callback.
-  * @param hdma : DMA handle.
-  * @retval None
-  */
-static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  HAL_UART_TxHalfCpltCallback(huart);
-}
-
-/**
-  * @brief DMA UART receive process complete callback.
-  * @param hdma: DMA handle.
-  * @retval None
-  */
-static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  /* DMA Normal mode */
-  if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
-  {
-    huart->RxXferCount = 0;
-
-    /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
-       in the UART CR3 register */
-    huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR);
-
-    /* Check if a transmit Process is ongoing or not */
-    if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
-    {
-      huart->State = HAL_UART_STATE_BUSY_TX;
-    }
-    else
-    {
-      huart->State = HAL_UART_STATE_READY;
-    }
-  }
-  
-  HAL_UART_RxCpltCallback(huart);
-}
-
-/**
-  * @brief  Handle UART Communication Timeout.
-  * @param  huart: UART handle.
-  * @param  Flag: specifies the UART flag to check.
-  * @param  Status: the Flag status (SET or RESET).
-  * @param  Timeout: Timeout duration.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
-{
-  uint32_t tickstart = HAL_GetTick();
-
-  /* Wait until flag is set */
-  if(Status == RESET)
-  {
-    while(__HAL_UART_GET_FLAG(huart, Flag) == RESET)
-    {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
-        {
-          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
-          __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
-          __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
-          __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
-          __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
-
-          huart->State= HAL_UART_STATE_READY;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(huart);
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  else
-  {
-    while(__HAL_UART_GET_FLAG(huart, Flag) != RESET)
-    {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
-        {
-          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
-          __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
-          __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
-          __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
-          __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
-
-          huart->State= HAL_UART_STATE_READY;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(huart);
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief DMA UART receive process half complete callback.
-  * @param hdma : DMA handle.
-  * @retval None
-  */
-static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  HAL_UART_RxHalfCpltCallback(huart);
-}
-
-/**
-  * @brief DMA UART communication error callback.
-  * @param hdma: DMA handle.
-  * @retval None
-  */
-static void UART_DMAError(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  huart->RxXferCount = 0;
-  huart->TxXferCount = 0;
-  huart->State= HAL_UART_STATE_READY;
-  huart->ErrorCode |= HAL_UART_ERROR_DMA;
-  HAL_UART_ErrorCallback(huart);
-}
-
-/**
-  * @brief Send an amount of data in interrupt mode.
-  * @note   Function is called under interruption only, once
-  *         interruptions have been enabled by HAL_UART_Transmit_IT().
-  * @param  huart: UART handle.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
-{
-  uint16_t* tmp;
-
-  if ((huart->State == HAL_UART_STATE_BUSY_TX) || (huart->State == HAL_UART_STATE_BUSY_TX_RX))
-  {
-
-    if(huart->TxXferCount == 0)
-    {
-      /* Disable the UART Transmit Data Register Empty Interrupt */
-      __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
-
-      /* Enable the UART Transmit Complete Interrupt */
-      __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
-
-      return HAL_OK;
-    }
-    else
-    {
-      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
-      {
-        tmp = (uint16_t*) huart->pTxBuffPtr;
-        huart->Instance->TDR = (*tmp & (uint16_t)0x01FF);
-        huart->pTxBuffPtr += 2;
-      }
-      else
-      {
-        huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFF);
-      }
-
-      huart->TxXferCount--;
-
-      return HAL_OK;
-    }
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-
-/**
-  * @brief  Wrap up transmission in non-blocking mode.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
-{
-  /* Disable the UART Transmit Complete Interrupt */
-  __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
-
-  /* Check if a receive process is ongoing or not */
-  if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
-  {
-    huart->State = HAL_UART_STATE_BUSY_RX;
-  }
-  else
-  {
-    /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
-    __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
-
-    huart->State = HAL_UART_STATE_READY;
-  }
-
-  HAL_UART_TxCpltCallback(huart);
-
-  return HAL_OK;
-}
-
-
-/**
-  * @brief Receive an amount of data in interrupt mode.
-  * @note   Function is called under interruption only, once
-  *         interruptions have been enabled by HAL_UART_Receive_IT()
-  * @param  huart: UART handle.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
-{
-  uint16_t* tmp;
-  uint16_t uhMask = huart->Mask;
-
-  if((huart->State == HAL_UART_STATE_BUSY_RX) || (huart->State == HAL_UART_STATE_BUSY_TX_RX))
-  {
-
-    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
-    {
-      tmp = (uint16_t*) huart->pRxBuffPtr ;
-      *tmp = (uint16_t)(huart->Instance->RDR & uhMask);
-      huart->pRxBuffPtr +=2;
-    }
-    else
-    {
-      *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
-    }
-
-    if(--huart->RxXferCount == 0)
-    {
-      __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
-
-      /* Check if a transmit Process is ongoing or not */
-      if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
-      {
-        huart->State = HAL_UART_STATE_BUSY_TX;
-      }
-      else
-      {
-        /* Disable the UART Parity Error Interrupt */
-        __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
-
-        /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
-        __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
-
-        huart->State = HAL_UART_STATE_READY;
-      }
-
-      HAL_UART_RxCpltCallback(huart);
-
-      return HAL_OK;
-    }
-
-    return HAL_OK;
-  }
-  else
-  {
-    /* Clear RXNE interrupt flag */
-    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
-
-    return HAL_BUSY;
-  }
-}
-
-
-/**
-  * @brief Calculate register BRR value without using uint64.
-  * @note   This function is added by the MicroPython project.
-  * @param  fck: Input clock frequency to the uart block in Hz.
-  * @param  baud: baud rate should be one of {300, 600, 1200, 2400, 4800, 9600, 19200, 57600, 115200}.
-  * @retval BRR value
-  */
-uint32_t HAL_UART_CalcBrr(uint32_t fck, uint32_t baud)
-{
-    const struct
-    {
-        uint32_t limit;
-        uint32_t div;
-    } comDiv[]= {
-        {1<<31, 300 }, /* must be >= 256 */
-        {1<<30, 150 }, /* must be >= 128 */
-        {1<<29,  75 }, /* must be >= 64 */
-        {1<<28,  50 }, /* must be >= 32 */
-        {1<<27,  20 }, /* must be >= 16 */
-        {1<<26,  10 }, /* must be >= 8 */
-        {1<<25,   5 }, /* must be >= 4 */
-        {1<<24,   2 }  /* must be >= 2 */
-    };
-    const uint32_t comDivCnt = sizeof(comDiv)/sizeof(comDiv[0]);
-    uint8_t i;
-    for (i=0; i<comDivCnt ;i++)
-    {
-        if (fck >= comDiv[i].limit)
-        {
-            fck  /= comDiv[i].div;
-            baud /= comDiv[i].div;
-            break;
-        }
-    }
-    return (fck<<8)/baud;
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_UART_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/src/stm32l4xx_hal_uart_ex.c b/stmhal/hal/l4/src/stm32l4xx_hal_uart_ex.c
deleted file mode 100644
index 933f50c1c3..0000000000
--- a/stmhal/hal/l4/src/stm32l4xx_hal_uart_ex.c
+++ /dev/null
@@ -1,462 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_uart_ex.c
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   Extended UART HAL module driver.
-  *          This file provides firmware functions to manage the following extended
-  *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
-  *           + Initialization and de-initialization functions
-  *           + Peripheral Control functions
-  *
-  *
-  @verbatim
-  ==============================================================================
-               ##### UART peripheral extended features  #####
-  ==============================================================================
-
-    (#) Declare a UART_HandleTypeDef handle structure.
-
-    (#) For the UART RS485 Driver Enable mode, initialize the UART registers
-        by calling the HAL_RS485Ex_Init() API.
-
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup UARTEx UARTEx
-  * @brief UART Extended HAL module driver
-  * @{
-  */
-
-#ifdef HAL_UART_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup UARTEx_Private_Functions UARTEx Private Functions
-  * @{
-  */
-static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup UARTEx_Exported_Functions  UARTEx Exported Functions
-  * @{
-  */
-
-/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @brief    Extended Initialization and Configuration Functions
-  *
-@verbatim
-===============================================================================
-            ##### Initialization and Configuration functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
-    in asynchronous mode.
-      (+) For the asynchronous mode the parameters below can be configured:
-        (++) Baud Rate
-        (++) Word Length
-        (++) Stop Bit
-        (++) Parity: If the parity is enabled, then the MSB bit of the data written
-             in the data register is transmitted but is changed by the parity bit.
-        (++) Hardware flow control
-        (++) Receiver/transmitter modes
-        (++) Over Sampling Method
-        (++) One-Bit Sampling Method
-      (+) For the asynchronous mode, the following advanced features can be configured as well:
-        (++) TX and/or RX pin level inversion
-        (++) data logical level inversion
-        (++) RX and TX pins swap
-        (++) RX overrun detection disabling
-        (++) DMA disabling on RX error
-        (++) MSB first on communication line
-        (++) auto Baud rate detection
-    [..]
-    The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration
-     procedures (details for the procedures are available in reference manual).
-
-@endverbatim
-
-  Depending on the frame length defined by the M1 and M0 bits (7-bit, 
-  8-bit or 9-bit), the possible UART formats are listed in the 
-  following table.
-  
-    Table 1. UART frame format.
-    +-----------------------------------------------------------------------+
-    |  M1 bit |  M0 bit |  PCE bit  |             UART frame                |
-    |---------|---------|-----------|---------------------------------------|
-    |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
-    |---------|---------|-----------|---------------------------------------|
-    |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
-    |---------|---------|-----------|---------------------------------------|
-    |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
-    |---------|---------|-----------|---------------------------------------|
-    |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
-    |---------|---------|-----------|---------------------------------------|
-    |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
-    |---------|---------|-----------|---------------------------------------|
-    |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
-    +-----------------------------------------------------------------------+
-
-  * @{
-  */
-
-/**
-  * @brief Initialize the RS485 Driver enable feature according to the specified
-  *         parameters in the UART_InitTypeDef and creates the associated handle.
-  * @param huart: UART handle.
-  * @param Polarity: select the driver enable polarity.
-  *        This parameter can be one of the following values:
-  *          @arg @ref UART_DE_POLARITY_HIGH DE signal is active high
-  *          @arg @ref UART_DE_POLARITY_LOW  DE signal is active low
-  * @param AssertionTime: Driver Enable assertion time:
-  *                         5-bit value defining the time between the activation of the DE (Driver Enable)
-  *                         signal and the beginning of the start bit. It is expressed in sample time
-  *                         units (1/8 or 1/16 bit time, depending on the oversampling rate)
-  * @param DeassertionTime: Driver Enable deassertion time:
-  *                         5-bit value defining the time between the end of the last stop bit, in a
-  *                         transmitted message, and the de-activation of the DE (Driver Enable) signal.
-  *                         It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
-  *                         oversampling rate).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
-{
-  uint32_t temp = 0x0;
-
-  /* Check the UART handle allocation */
-  if(huart == NULL)
-  {
-    return HAL_ERROR;
-  }
-  /* Check the Driver Enable UART instance */
-  assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));
-
-  /* Check the Driver Enable polarity */
-  assert_param(IS_UART_DE_POLARITY(Polarity));
-
-  /* Check the Driver Enable assertion time */
-  assert_param(IS_UART_ASSERTIONTIME(AssertionTime));
-
-  /* Check the Driver Enable deassertion time */
-  assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));
-
-  if(huart->State == HAL_UART_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    huart->Lock = HAL_UNLOCKED;
-
-    /* Init the low level hardware : GPIO, CLOCK, CORTEX */
-    HAL_UART_MspInit(huart);
-  }
-
-  huart->State = HAL_UART_STATE_BUSY;
-
-  /* Disable the Peripheral */
-  __HAL_UART_DISABLE(huart);
-
-  /* Set the UART Communication parameters */
-  if (UART_SetConfig(huart) == HAL_ERROR)
-  {
-    return HAL_ERROR;
-  }
-
-  if(huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
-  {
-    UART_AdvFeatureConfig(huart);
-  }
-
-  /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
-  SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
-
-  /* Set the Driver Enable polarity */
-  MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
-
-  /* Set the Driver Enable assertion and deassertion times */
-  temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
-  temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
-  MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT|USART_CR1_DEAT), temp);
-
-  /* Enable the Peripheral */
-  __HAL_UART_ENABLE(huart);
-
-  /* TEACK and/or REACK to check before moving huart->State to Ready */
-  return (UART_CheckIdleState(huart));
-}
-
-
-/**
-  * @}
-  */
-
-/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions
-  * @brief    Extended Peripheral Control functions
- *
-@verbatim
- ===============================================================================
-                      ##### Peripheral Control functions #####
- ===============================================================================
-    [..] This section provides the following functions:
-     (+) HAL_UARTEx_EnableClockStopMode() API enables the UART clock (HSI or LSE only) during stop mode
-     (+) HAL_UARTEx_DisableClockStopMode() API disables the above functionality
-     (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
-         detection length to more than 4 bits for multiprocessor address mark wake up.
-     (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode
-         trigger: address match, Start Bit detection or RXNE bit status.
-     (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode
-     (+) HAL_UARTEx_DisableStopMode() API disables the above functionality
-     (+) HAL_UARTEx_WakeupCallback() called upon UART wakeup interrupt
-
-
-@endverbatim
-  * @{
-  */
-
-
-
-
-/**
-  * @brief By default in multiprocessor mode, when the wake up method is set
-  *        to address mark, the UART handles only 4-bit long addresses detection;
-  *        this API allows to enable longer addresses detection (6-, 7- or 8-bit
-  *        long).
-  * @note  Addresses detection lengths are: 6-bit address detection in 7-bit data mode, 
-  *        7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
-  * @param huart: UART handle.
-  * @param AddressLength: this parameter can be one of the following values:
-  *          @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address
-  *          @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)
-{
-  /* Check the UART handle allocation */
-  if(huart == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the address length parameter */
-  assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
-
-  huart->State = HAL_UART_STATE_BUSY;
-
-  /* Disable the Peripheral */
-  __HAL_UART_DISABLE(huart);
-
-  /* Set the address length */
-  MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
-
-  /* Enable the Peripheral */
-  __HAL_UART_ENABLE(huart);
-
-  /* TEACK and/or REACK to check before moving huart->State to Ready */
-  return (UART_CheckIdleState(huart));
-}
-
-
-/**
-  * @brief Set Wakeup from Stop mode interrupt flag selection.
-  * @param huart: UART handle.
-  * @param WakeUpSelection: address match, Start Bit detection or RXNE bit status.
-  * This parameter can be one of the following values:
-  *      @arg @ref UART_WAKEUP_ON_ADDRESS
-  *      @arg @ref UART_WAKEUP_ON_STARTBIT
-  *      @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* check the wake-up from stop mode UART instance */
-  assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
-  /* check the wake-up selection parameter */
-  assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent));
-
-  /* Process Locked */
-  __HAL_LOCK(huart);
-
-  huart->State = HAL_UART_STATE_BUSY;
-
-  /* Disable the Peripheral */
-  __HAL_UART_DISABLE(huart);
-
-  /* Set the wake-up selection scheme */
-  MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent);
-
-  if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS)
-  {
-    UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection);
-  }
-
-  /* Enable the Peripheral */
-  __HAL_UART_ENABLE(huart);
-
-  /* Wait until REACK flag is set */
-  if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
-  {
-    status = HAL_TIMEOUT;
-  }
-  else
-  {
-    /* Initialize the UART State */
-    huart->State = HAL_UART_STATE_READY;
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-
-  return status;
-}
-
-
-/**
-  * @brief Enable UART Stop Mode.
-  * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE.
-  * @param huart: UART handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
-{
-  /* Process Locked */
-  __HAL_LOCK(huart);
-
-  huart->State = HAL_UART_STATE_BUSY;
-
-  /* Set UESM bit */
-  SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
-
-  huart->State = HAL_UART_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Disable UART Stop Mode.
-  * @param huart: UART handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
-{
-  /* Process Locked */
-  __HAL_LOCK(huart);
-
-  huart->State = HAL_UART_STATE_BUSY;
-
-  /* Clear UESM bit */
-  CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
-
-  huart->State = HAL_UART_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief UART wakeup from Stop mode callback.
-  * @param huart: UART handle.
-  * @retval None
-  */
-__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_UARTEx_WakeupCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup UARTEx_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection.
-  * @param huart: UART handle.
-  * @param WakeUpSelection: UART wake up from stop mode parameters.
-  * @retval None
-  */
-static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
-{
-  assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));
-
-  /* Set the USART address length */
-  MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength);
-
-  /* Set the USART address node */
-  MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_UART_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/src/stm32l4xx_ll_sdmmc.c b/stmhal/hal/l4/src/stm32l4xx_ll_sdmmc.c
deleted file mode 100644
index 42e5ed7af8..0000000000
--- a/stmhal/hal/l4/src/stm32l4xx_ll_sdmmc.c
+++ /dev/null
@@ -1,496 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_ll_sdmmc.c
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   SDMMC Low Layer HAL module driver.  
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the SDMMC peripheral:
-  *           + Initialization/de-initialization functions
-  *           + I/O operation functions
-  *           + Peripheral Control functions 
-  *           + Peripheral State functions
-  *         
-  @verbatim
-  ==============================================================================
-                       ##### SDMMC peripheral features #####
-  ==============================================================================        
-    [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the APB2
-         peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDMMC cards and CE-ATA
-         devices.
-    
-    [..] The SDMMC features include the following:
-         (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support
-             for three different data bus modes: 1-bit (default), 4-bit and 8-bit
-         (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility)
-         (+) Full compliance with SD Memory Card Specifications Version 2.0
-         (+) Full compliance with SD I/O Card Specification Version 2.0: card support for two
-             different data bus modes: 1-bit (default) and 4-bit
-         (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol
-             Rev1.1)
-         (+) Data transfer up to 48 MHz for the 8 bit mode
-         (+) Data and command output enable signals to control external bidirectional drivers.
-                 
-   
-                           ##### How to use this driver #####
-  ==============================================================================
-    [..]
-      This driver is a considered as a driver of service for external devices drivers 
-      that interfaces with the SDMMC peripheral.
-      According to the device used (SD card/ MMC card / SDMMC card ...), a set of APIs 
-      is used in the device's driver to perform SDMMC operations and functionalities.
-   
-      This driver is almost transparent for the final user, it is only used to implement other
-      functionalities of the external device.
-   
-    [..]
-      (+) The SDMMC clock (SDMMCCLK = 48 MHz) is coming from a specific output (MSI, PLLUSB1CLK,
-          PLLUSB2CLK). Before start working with SDMMC peripheral make sure that the
-          PLL is well configured.
-          The SDMMC peripheral uses two clock signals:
-          (++) SDMMC adapter clock (SDMMCCLK = 48 MHz)
-          (++) APB2 bus clock (PCLK2)
-       
-          -@@- PCLK2 and SDMMC_CK clock frequencies must respect the following condition:
-               Frequency(PCLK2) >= (3 / 8 x Frequency(SDMMC_CK))
-  
-      (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDMMC
-          peripheral.
-
-      (+) Enable the Power ON State using the SDMMC_PowerState_ON(SDMMCx) 
-          function and disable it using the function SDMMC_PowerState_OFF(SDMMCx).
-                
-      (+) Enable/Disable the clock using the __SDMMC_ENABLE()/__SDMMC_DISABLE() macros.
-  
-      (+) Enable/Disable the peripheral interrupts using the macros __SDMMC_ENABLE_IT(hSDMMC, IT) 
-          and __SDMMC_DISABLE_IT(hSDMMC, IT) if you need to use interrupt mode. 
-  
-      (+) When using the DMA mode 
-          (++) Configure the DMA in the MSP layer of the external device
-          (++) Active the needed channel Request 
-          (++) Enable the DMA using __SDMMC_DMA_ENABLE() macro or Disable it using the macro
-               __SDMMC_DMA_DISABLE().
-  
-      (+) To control the CPSM (Command Path State Machine) and send 
-          commands to the card use the SDMMC_SendCommand(SDMMCx), 
-          SDMMC_GetCommandResponse() and SDMMC_GetResponse() functions. First, user has
-          to fill the command structure (pointer to SDMMC_CmdInitTypeDef) according 
-          to the selected command to be sent.
-          The parameters that should be filled are:
-           (++) Command Argument
-           (++) Command Index
-           (++) Command Response type
-           (++) Command Wait
-           (++) CPSM Status (Enable or Disable).
-  
-          -@@- To check if the command is well received, read the SDMMC_CMDRESP
-              register using the SDMMC_GetCommandResponse().
-              The SDMMC responses registers (SDMMC_RESP1 to SDMMC_RESP2), use the
-              SDMMC_GetResponse() function.
-  
-      (+) To control the DPSM (Data Path State Machine) and send/receive 
-           data to/from the card use the SDMMC_DataConfig(), SDMMC_GetDataCounter(), 
-          SDMMC_ReadFIFO(), SDMMC_WriteFIFO() and SDMMC_GetFIFOCount() functions.
-  
-    *** Read Operations ***
-    =======================
-    [..]
-      (#) First, user has to fill the data structure (pointer to
-          SDMMC_DataInitTypeDef) according to the selected data type to be received.
-          The parameters that should be filled are:
-           (++) Data TimeOut
-           (++) Data Length
-           (++) Data Block size
-           (++) Data Transfer direction: should be from card (To SDMMC)
-           (++) Data Transfer mode
-           (++) DPSM Status (Enable or Disable)
-                                     
-      (#) Configure the SDMMC resources to receive the data from the card
-          according to selected transfer mode (Refer to Step 8, 9 and 10).
-  
-      (#) Send the selected Read command (refer to step 11).
-                    
-      (#) Use the SDMMC flags/interrupts to check the transfer status.
-  
-    *** Write Operations ***
-    ========================
-    [..]
-     (#) First, user has to fill the data structure (pointer to
-         SDMMC_DataInitTypeDef) according to the selected data type to be received.
-         The parameters that should be filled are:
-          (++) Data TimeOut
-          (++) Data Length
-          (++) Data Block size
-          (++) Data Transfer direction:  should be to card (To CARD)
-          (++) Data Transfer mode
-          (++) DPSM Status (Enable or Disable)
-  
-     (#) Configure the SDMMC resources to send the data to the card according to 
-         selected transfer mode.
-                     
-     (#) Send the selected Write command.
-                    
-     (#) Use the SDMMC flags/interrupts to check the transfer status.
-  
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup SDMMC_LL SDMMC Low Layer
-  * @brief Low layer module for SD
-  * @{
-  */
-
-#if defined (HAL_SD_MODULE_ENABLED)
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup SDMMC_LL_Exported_Functions SDMMC Low Layer Exported Functions
-  * @{
-  */
-
-/** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions 
- *  @brief    Initialization and Configuration functions 
- *
-@verbatim    
- ===============================================================================
-              ##### Initialization/de-initialization functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
- 
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the SDMMC according to the specified
-  *         parameters in the SDMMC_InitTypeDef and initialize the associated handle.
-  * @param  SDMMCx: Pointer to SDMMC register base
-  * @param  Init: SDMMC initialization structure   
-  * @retval HAL status
-  */
-HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init)
-{
-  /* Check the parameters */
-  assert_param(IS_SDMMC_ALL_INSTANCE(SDMMCx));
-  assert_param(IS_SDMMC_CLOCK_EDGE(Init.ClockEdge)); 
-  assert_param(IS_SDMMC_CLOCK_BYPASS(Init.ClockBypass));
-  assert_param(IS_SDMMC_CLOCK_POWER_SAVE(Init.ClockPowerSave));
-  assert_param(IS_SDMMC_BUS_WIDE(Init.BusWide));
-  assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl));
-  assert_param(IS_SDMMC_CLKDIV(Init.ClockDiv));
-  
-  /* Set SDMMC configuration parameters */
-  /* Write to SDMMC CLKCR */
-  MODIFY_REG(SDMMCx->CLKCR, CLKCR_CLEAR_MASK, Init.ClockEdge           |\
-                                              Init.ClockBypass         |\
-                                              Init.ClockPowerSave      |\
-                                              Init.BusWide             |\
-                                              Init.HardwareFlowControl |\
-                                              Init.ClockDiv);  
-
-  return HAL_OK;
-}
-
-
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SDMMC_LL_Group2 IO operation functions 
- *  @brief   Data transfers functions 
- *
-@verbatim   
- ===============================================================================
-                      ##### I/O operation functions #####
- ===============================================================================  
-    [..]
-    This subsection provides a set of functions allowing to manage the SDMMC data 
-    transfers.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Read data (word) from Rx FIFO in blocking mode (polling) 
-  * @param  SDMMCx: Pointer to SDMMC register base
-  * @retval HAL status
-  */
-uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx)
-{
-  /* Read data from Rx FIFO */ 
-  return (SDMMCx->FIFO);
-}
-
-/**
-  * @brief  Write data (word) to Tx FIFO in blocking mode (polling) 
-  * @param  SDMMCx: Pointer to SDMMC register base
-  * @param  pWriteData: pointer to data to write
-  * @retval HAL status
-  */
-HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData)
-{ 
-  /* Write data to FIFO */ 
-  SDMMCx->FIFO = *pWriteData;
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions 
- *  @brief   management functions 
- *
-@verbatim   
- ===============================================================================
-                      ##### Peripheral Control functions #####
- ===============================================================================  
-    [..]
-    This subsection provides a set of functions allowing to control the SDMMC data 
-    transfers.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Set SDMMC Power state to ON. 
-  * @param  SDMMCx: Pointer to SDMMC register base
-  * @retval HAL status
-  */
-HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx)
-{  
-  /* Set power state to ON */ 
-  SDMMCx->POWER = SDMMC_POWER_PWRCTRL;
-  
-  return HAL_OK; 
-}
-
-/**
-  * @brief  Set SDMMC Power state to OFF. 
-  * @param  SDMMCx: Pointer to SDMMC register base
-  * @retval HAL status
-  */
-HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx)
-{
-  /* Set power state to OFF */
-  SDMMCx->POWER = (uint32_t)0x00000000;
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Get SDMMC Power state. 
-  * @param  SDMMCx: Pointer to SDMMC register base
-  * @retval Power status of the controller. The returned value can be one of the 
-  *         following values:
-  *            - 0x00: Power OFF
-  *            - 0x02: Power UP
-  *            - 0x03: Power ON 
-  */
-uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx)  
-{
-  return (SDMMCx->POWER & SDMMC_POWER_PWRCTRL);
-}
-
-/**
-  * @brief  Configure the SDMMC command path according to the specified parameters in
-  *         SDMMC_CmdInitTypeDef structure and send the command 
-  * @param  SDMMCx: Pointer to SDMMC register base
-  * @param  Command: pointer to a SDMMC_CmdInitTypeDef structure that contains 
-  *         the configuration information for the SDMMC command
-  * @retval HAL status
-  */
-HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command)
-{
-  /* Check the parameters */
-  assert_param(IS_SDMMC_CMD_INDEX(Command->CmdIndex));
-  assert_param(IS_SDMMC_RESPONSE(Command->Response));
-  assert_param(IS_SDMMC_WAIT(Command->WaitForInterrupt));
-  assert_param(IS_SDMMC_CPSM(Command->CPSM));
-
-  /* Set the SDMMC Argument value */
-  SDMMCx->ARG = Command->Argument;
-
-  /* Set SDMMC command parameters */
-  /* Write to SDMMC CMD register */
-  MODIFY_REG(SDMMCx->CMD, CMD_CLEAR_MASK, Command->CmdIndex         |\
-                                          Command->Response         |\
-                                          Command->WaitForInterrupt |\
-                                          Command->CPSM); 
-  
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Return the command index of last command for which response received
-  * @param  SDMMCx: Pointer to SDMMC register base
-  * @retval Command index of the last command response received
-  */
-uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx)
-{
-  return (uint8_t)(SDMMCx->RESPCMD);
-}
-
-
-/**
-  * @brief  Return the response received from the card for the last command
-  * @param  SDMMCx: Pointer to SDMMC register base    
-  * @param  Response: Specifies the SDMMC response register. 
-  *          This parameter can be one of the following values:
-  *            @arg SDMMC_RESP1: Response Register 1
-  *            @arg SDMMC_RESP2: Response Register 2
-  *            @arg SDMMC_RESP3: Response Register 3
-  *            @arg SDMMC_RESP4: Response Register 4  
-  * @retval The Corresponding response register value
-  */
-uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response)
-{
-  __IO uint32_t tmp = 0;
-
-  /* Check the parameters */
-  assert_param(IS_SDMMC_RESP(Response));
-  
-  /* Get the response */
-  tmp = (uint32_t)&(SDMMCx->RESP1) + Response;
-  
-  return (*(__IO uint32_t *) tmp);
-}  
-
-/**
-  * @brief  Configure the SDMMC data path according to the specified 
-  *         parameters in the SDMMC_DataInitTypeDef.
-  * @param  SDMMCx: Pointer to SDMMC register base  
-  * @param  Data : pointer to a SDMMC_DataInitTypeDef structure 
-  *         that contains the configuration information for the SDMMC data.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef SDMMC_DataConfig(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data)
-{
-  /* Check the parameters */
-  assert_param(IS_SDMMC_DATA_LENGTH(Data->DataLength));
-  assert_param(IS_SDMMC_BLOCK_SIZE(Data->DataBlockSize));
-  assert_param(IS_SDMMC_TRANSFER_DIR(Data->TransferDir));
-  assert_param(IS_SDMMC_TRANSFER_MODE(Data->TransferMode));
-  assert_param(IS_SDMMC_DPSM(Data->DPSM));
-
-  /* Set the SDMMC Data TimeOut value */
-  SDMMCx->DTIMER = Data->DataTimeOut;
-
-  /* Set the SDMMC DataLength value */
-  SDMMCx->DLEN = Data->DataLength;
-
-  /* Set the SDMMC data configuration parameters */
-  /* Write to SDMMC DCTRL */
-  MODIFY_REG(SDMMCx->DCTRL, DCTRL_CLEAR_MASK, Data->DataBlockSize |\
-                                              Data->TransferDir   |\
-                                              Data->TransferMode  |\
-                                              Data->DPSM);
-
-  return HAL_OK;
-
-}
-
-/**
-  * @brief  Returns number of remaining data bytes to be transferred.
-  * @param  SDMMCx: Pointer to SDMMC register base
-  * @retval Number of remaining data bytes to be transferred
-  */
-uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx)
-{
-  return (SDMMCx->DCOUNT);
-}
-
-/**
-  * @brief  Get the FIFO data
-  * @param  SDMMCx: Pointer to SDMMC register base 
-  * @retval Data received
-  */
-uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx)
-{
-  return (SDMMCx->FIFO);
-}
-
-
-/**
-  * @brief  Sets one of the two options of inserting read wait interval.
-  * @param  SDMMCx: Pointer to SDMMC register base   
-  * @param  SDMMC_ReadWaitMode: SDMMC Read Wait operation mode.
-  *          This parameter can be:
-  *            @arg SDMMC_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK
-  *            @arg SDMMC_READ_WAIT_MODE_DATA2: Read Wait control using SDMMC_DATA2
-  * @retval None
-  */
-HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode)
-{
-  /* Check the parameters */
-  assert_param(IS_SDMMC_READWAIT_MODE(SDMMC_ReadWaitMode));
-  
-  /* Set SDMMC read wait mode */
-  MODIFY_REG(SDMMCx->DCTRL, SDMMC_DCTRL_RWMOD, SDMMC_ReadWaitMode); 
-  
-  return HAL_OK;  
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* (HAL_SD_MODULE_ENABLED) */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/hal/l4/src/stm32l4xx_ll_usb.c b/stmhal/hal/l4/src/stm32l4xx_ll_usb.c
deleted file mode 100644
index db49163a7e..0000000000
--- a/stmhal/hal/l4/src/stm32l4xx_ll_usb.c
+++ /dev/null
@@ -1,1630 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_ll_usb.c
-  * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
-  * @brief   USB Low Layer HAL module driver.
-  *   
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the USB Peripheral Controller:
-  *           + Initialization/de-initialization functions
-  *           + I/O operation functions
-  *           + Peripheral Control functions 
-  *           + Peripheral State functions
-  *         
-  @verbatim
-  ==============================================================================
-                    ##### How to use this driver #####
-  ==============================================================================
-    [..]
-      (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.
-  
-      (#) Call USB_CoreInit() API to initialize the USB Core peripheral.
-
-      (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-#if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
-
-/** @addtogroup STM32L4xx_LL_USB_DRIVER
-  * @{
-  */
-
-#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED)
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx);
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup LL_USB_Exported_Functions USB Low Layer Exported Functions
-  * @{
-  */
-
-/** @defgroup LL_USB_Group1 Initialization/de-initialization functions 
- *  @brief    Initialization and Configuration functions 
- *
-@verbatim    
- ===============================================================================
-              ##### Initialization/de-initialization functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
- 
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the USB Core
-  * @param  USBx: USB Instance
-  * @param  cfg: pointer to a USB_OTG_CfgTypeDef structure that contains
-  *         the configuration information for the specified USBx peripheral.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(cfg);
-
-  /* Select FS Embedded PHY */
-  USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
-  
-  /* Reset after a PHY select and set Host mode */
-  USB_CoreReset(USBx);
-  
-  /* Deactivate the power down*/
-  USBx->GCCFG = USB_OTG_GCCFG_PWRDWN;
-  
-  /* Enable srpcap*/
-  USBx->GUSBCFG |= USB_OTG_GUSBCFG_SRPCAP;
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_EnableGlobalInt
-  *         Enables the controller's Global Int in the AHB Config reg
-  * @param  USBx: Selected device
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
-{
-  USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  USB_DisableGlobalInt
-  *         Disable the controller's Global Int in the AHB Config reg
-  * @param  USBx: Selected device
-  * @retval HAL status
-*/
-HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
-{
-  USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
-  return HAL_OK;
-}
-   
-/**
-  * @brief  USB_SetCurrentMode : Set functional mode
-  * @param  USBx: Selected device
-  * @param  mode:  current core mode
-  *          This parameter can be one of these values:
-  *            @arg USB_OTG_DEVICE_MODE: Peripheral mode
-  *            @arg USB_OTG_HOST_MODE: Host mode
-  *            @arg USB_OTG_DRD_MODE: Dual Role Device mode  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode)
-{
-  USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); 
-  
-  if ( mode == USB_OTG_HOST_MODE)
-  {
-    USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; 
-  }
-  else if ( mode == USB_OTG_DEVICE_MODE)
-  {
-    USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; 
-  }
-  HAL_Delay(50);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_DevInit : Initializes the USB_OTG controller registers 
-  *         for device mode
-  * @param  USBx: Selected device
-  * @param  cfg: pointer to a USB_OTG_CfgTypeDef structure that contains
-  *         the configuration information for the specified USBx peripheral.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
-{
-  uint32_t i = 0;
-
-  /*Activate VBUS Sensing B */
-  USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
-  
-  if (cfg.vbus_sensing_enable == 0)
-  {
-    /* Deactivate VBUS Sensing B */
-    USBx->GCCFG &= ~ USB_OTG_GCCFG_VBDEN;
-    
-    /* B-peripheral session valid override enable*/ 
-    USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
-    USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
-  }
-   
-  /* Restart the Phy Clock */
-  USBx_PCGCCTL = 0;
-
-  /* Device mode configuration */
-  USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80;
-  
-  /* Set Full speed phy */
-  USB_SetDevSpeed (USBx , USB_OTG_SPEED_FULL);
-
-  /* Flush the FIFOs */
-  USB_FlushTxFifo(USBx , 0x10); /* all Tx FIFOs */
-  USB_FlushRxFifo(USBx);
-  
-  /* Clear all pending Device Interrupts */
-  USBx_DEVICE->DIEPMSK = 0;
-  USBx_DEVICE->DOEPMSK = 0;
-  USBx_DEVICE->DAINT = 0xFFFFFFFF;
-  USBx_DEVICE->DAINTMSK = 0;
-  
-  for (i = 0; i < cfg.dev_endpoints; i++)
-  {
-    if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
-    {
-      USBx_INEP(i)->DIEPCTL = (USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK);
-    }
-    else
-    {
-      USBx_INEP(i)->DIEPCTL = 0;
-    }
-    
-    USBx_INEP(i)->DIEPTSIZ = 0;
-    USBx_INEP(i)->DIEPINT  = 0xFF;
-  }
-  
-  for (i = 0; i < cfg.dev_endpoints; i++)
-  {
-    if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
-    {
-      USBx_OUTEP(i)->DOEPCTL = (USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK);
-    }
-    else
-    {
-      USBx_OUTEP(i)->DOEPCTL = 0;
-    }
-    
-    USBx_OUTEP(i)->DOEPTSIZ = 0;
-    USBx_OUTEP(i)->DOEPINT  = 0xFF;
-  }
-  
-  USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
-  
-  if (cfg.dma_enable == 1)
-  {
-    /*Set threshold parameters */
-    USBx_DEVICE->DTHRCTL = (USB_OTG_DTHRCTL_TXTHRLEN_6 | USB_OTG_DTHRCTL_RXTHRLEN_6);
-    USBx_DEVICE->DTHRCTL |= (USB_OTG_DTHRCTL_RXTHREN | USB_OTG_DTHRCTL_ISOTHREN | USB_OTG_DTHRCTL_NONISOTHREN);
-    
-    i= USBx_DEVICE->DTHRCTL;
-  }
-  
-  /* Disable all interrupts. */
-  USBx->GINTMSK = 0;
-  
-  /* Clear any pending interrupts */
-  USBx->GINTSTS = 0xBFFFFFFF;
-
-  /* Enable the common interrupts */
-  if (cfg.dma_enable == DISABLE)
-  {
-    USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; 
-  }
-
-    /* Enable interrupts matching to the Device mode ONLY */
-  USBx->GINTMSK |= (USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |\
-                    USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |\
-                    USB_OTG_GINTMSK_OEPINT   | USB_OTG_GINTMSK_IISOIXFRM|\
-                    USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM);
-
-  if(cfg.Sof_enable)
-  {
-    USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
-  }
-
-  if (cfg.vbus_sensing_enable == ENABLE)
-  {
-    USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); 
-  }
-  
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  USB_OTG_FlushTxFifo : Flush a Tx FIFO
-  * @param  USBx: Selected device
-  * @param  num: FIFO number
-  *         This parameter can be a value from 1 to 15
-            15 means Flush all Tx FIFOs
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num )
-{
-  uint32_t count = 0;
- 
-  USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)( num << 6)); 
- 
-  do
-  {
-    if (++count > 200000)
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
-  
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  USB_FlushRxFifo : Flush Rx FIFO
-  * @param  USBx: Selected device
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
-{
-  uint32_t count = 0;
-  
-  USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
-  
-  do
-  {
-    if (++count > 200000)
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_SetDevSpeed :Initializes the DevSpd field of DCFG register 
-  *         depending the PHY type and the enumeration speed of the device.
-  * @param  USBx: Selected device
-  * @param  speed: device speed
-  *          This parameter can be one of these values:
-  *            @arg USB_OTG_SPEED_HIGH: High speed mode
-  *            @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode
-  *            @arg USB_OTG_SPEED_FULL: Full speed mode
-  *            @arg USB_OTG_SPEED_LOW: Low speed mode
-  * @retval  Hal status
-  */
-HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed)
-{
-  USBx_DEVICE->DCFG |= speed;
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_GetDevSpeed :Return the  Dev Speed 
-  * @param  USBx: Selected device
-  * @retval speed : device speed
-  *          This parameter can be one of these values:
-  *            @arg USB_OTG_SPEED_HIGH: High speed mode
-  *            @arg USB_OTG_SPEED_FULL: Full speed mode
-  *            @arg USB_OTG_SPEED_LOW: Low speed mode
-  */
-uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
-{
-  uint8_t speed = 0;
-  
-  if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)
-  {
-    speed = USB_OTG_SPEED_HIGH;
-  }
-  else if (((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ)||
-           ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_48MHZ))
-  {
-    speed = USB_OTG_SPEED_FULL;
-  }
-  else if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
-  {
-    speed = USB_OTG_SPEED_LOW;
-  }
-  
-  return speed;
-}
-
-/**
-  * @brief  Activate and configure an endpoint
-  * @param  USBx: Selected device
-  * @param  ep: pointer to endpoint structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
-{
-  if (ep->is_in == 1)
-  {
-   USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)));
-   
-    if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0)
-    {
-      USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\
-        ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); 
-    } 
-
-  }
-  else
-  {
-     USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16);
-     
-    if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0)
-    {
-      USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\
-       (USB_OTG_DIEPCTL_SD0PID_SEVNFRM)| (USB_OTG_DOEPCTL_USBAEP));
-    } 
-  }
-  return HAL_OK;
-}
-/**
-  * @brief  Activate and configure a dedicated endpoint
-  * @param  USBx: Selected device
-  * @param  ep: pointer to endpoint structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
-{
-  static __IO uint32_t debug = 0;
-  
-  /* Read DEPCTLn register */
-  if (ep->is_in == 1)
-  {
-    if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0)
-    {
-      USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\
-        ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); 
-    } 
-    
-    
-    debug  |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\
-        ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); 
-    
-   USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)));
-  }
-  else
-  {
-    if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0)
-    {
-      USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\
-        ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP));
-      
-      debug = (uint32_t)(((uint32_t )USBx) + USB_OTG_OUT_ENDPOINT_BASE + (0)*USB_OTG_EP_REG_SIZE);
-      debug = (uint32_t )&USBx_OUTEP(ep->num)->DOEPCTL;
-      debug |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\
-        ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP)); 
-    } 
-    
-     USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16);
-  }
-
-  return HAL_OK;
-}
-/**
-  * @brief  De-activate and de-initialize an endpoint
-  * @param  USBx: Selected device
-  * @param  ep: pointer to endpoint structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
-{
-  /* Read DEPCTLn register */
-  if (ep->is_in == 1)
-  {
-   USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));
-   USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));   
-   USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;   
-  }
-  else
-  {
-     USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
-     USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));     
-     USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;      
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  De-activate and de-initialize a dedicated endpoint
-  * @param  USBx: Selected device
-  * @param  ep: pointer to endpoint structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
-{
-  /* Read DEPCTLn register */
-  if (ep->is_in == 1)
-  {
-   USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
-   USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));
-  }
-  else
-  {
-     USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; 
-     USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_EPStartXfer : setup and starts a transfer over an EP
-  * @param  USBx: Selected device
-  * @param  ep: pointer to endpoint structure
-  * @param  dma: USB dma enabled or disabled 
-  *          This parameter can be one of these values:
-  *           0 : DMA feature not used 
-  *           1 : DMA feature used  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma)
-{
-  uint16_t pktcnt = 0;
-  
-  /* IN endpoint */
-  if (ep->is_in == 1)
-  {
-    /* Zero Length Packet? */
-    if (ep->xfer_len == 0)
-    {
-      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 
-      USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;
-      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 
-    }
-    else
-    {
-      /* Program the transfer size and packet count
-      * as follows: xfersize = N * maxpacket +
-      * short_packet pktcnt = N + (short_packet
-      * exist ? 1 : 0)
-      */
-      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
-      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 
-      USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket) << 19)) ;
-      USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); 
-      
-      if (ep->type == EP_TYPE_ISOC)
-      {
-        USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); 
-        USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1 << 29)); 
-      }       
-    }
-
-    if (dma == 1)
-    {
-      USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr);
-    }
-    else
-    {
-      if (ep->type != EP_TYPE_ISOC)
-      {
-        /* Enable the Tx FIFO Empty Interrupt for this EP */
-        if (ep->xfer_len > 0)
-        {
-          USBx_DEVICE->DIEPEMPMSK |= 1 << ep->num;
-        }
-      }
-    }
-
-    if (ep->type == EP_TYPE_ISOC)
-    {
-      if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0)
-      {
-        USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
-      }
-      else
-      {
-        USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
-      }
-    } 
-    
-    /* EP enable, IN data in FIFO */
-    USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
-    
-    if (ep->type == EP_TYPE_ISOC)
-    {
-      USB_WritePacket(USBx, ep->xfer_buff, ep->num, ep->xfer_len, dma);   
-    }    
-  }
-  else /* OUT endpoint */
-  {
-    /* Program the transfer size and packet count as follows:
-    * pktcnt = N
-    * xfersize = N * maxpacket
-    */  
-    USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); 
-    USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); 
-      
-    if (ep->xfer_len == 0)
-    {
-      USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);
-      USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ;      
-    }
-    else
-    {
-      pktcnt = (ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket; 
-      USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (pktcnt << 19)); ;
-      USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt)); 
-    }
-
-    if (dma == 1)
-    {
-      USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)ep->xfer_buff;
-    }
-    
-    if (ep->type == EP_TYPE_ISOC)
-    {
-      if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0)
-      {
-        USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;
-      }
-      else
-      {
-        USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
-      }
-    }
-    /* EP enable */
-    USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_EP0StartXfer : setup and starts a transfer over the EP  0
-  * @param  USBx: Selected device
-  * @param  ep: pointer to endpoint structure
-  * @param  dma: USB dma enabled or disabled 
-  *          This parameter can be one of these values:
-  *           0 : DMA feature not used 
-  *           1 : DMA feature used  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma)
-{
-  /* IN endpoint */
-  if (ep->is_in == 1)
-  {
-    /* Zero Length Packet? */
-    if (ep->xfer_len == 0)
-    {
-      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 
-      USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;
-      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 
-    }
-    else
-    {
-      /* Program the transfer size and packet count
-      * as follows: xfersize = N * maxpacket +
-      * short_packet pktcnt = N + (short_packet
-      * exist ? 1 : 0)
-      */
-      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
-      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 
-      
-      if(ep->xfer_len > ep->maxpacket)
-      {
-        ep->xfer_len = ep->maxpacket;
-      }
-      USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;
-      USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); 
-    
-    }
-    
-    if (dma == 1)
-    {
-      USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr);
-    }
-    else
-    {
-      /* Enable the Tx FIFO Empty Interrupt for this EP */
-      if (ep->xfer_len > 0)
-      {
-        USBx_DEVICE->DIEPEMPMSK |= 1 << (ep->num);
-      }
-    }
-    
-    /* EP enable, IN data in FIFO */
-    USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);   
-  }
-  else /* OUT endpoint */
-  {
-    /* Program the transfer size and packet count as follows:
-    * pktcnt = N
-    * xfersize = N * maxpacket
-    */
-    USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); 
-    USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); 
-      
-    if (ep->xfer_len > 0)
-    {
-      ep->xfer_len = ep->maxpacket;
-    }
-    
-    USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19));
-    USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket)); 
-    
-
-    if (dma == 1)
-    {
-      USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)(ep->xfer_buff);
-    }
-    
-    /* EP enable */
-    USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);    
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_WritePacket : Writes a packet into the Tx FIFO associated 
-  *         with the EP/channel
-  * @param  USBx: Selected device           
-  * @param  src:  pointer to source buffer
-  * @param  ch_ep_num: endpoint or host channel number
-  * @param  len: Number of bytes to write
-  * @param  dma: USB dma enabled or disabled 
-  *          This parameter can be one of these values:
-  *           0 : DMA feature not used 
-  *           1 : DMA feature used  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma)
-{
-  uint32_t count32b= 0 , i= 0;
-  
-  if (dma == 0)
-  {
-    count32b =  (len + 3) / 4;
-    for (i = 0; i < count32b; i++, src += 4)
-    {
-      USBx_DFIFO(ch_ep_num) = *((__packed uint32_t *)src);
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_ReadPacket : read a packet from the Tx FIFO associated 
-  *         with the EP/channel
-  * @param  USBx: Selected device  
-  * @param  src: source pointer
-  * @param  ch_ep_num: endpoint or host channel number
-  * @param  len: Number of bytes to read
-  * @param  dma: USB dma enabled or disabled 
-  *          This parameter can be one of these values:
-  *           0 : DMA feature not used 
-  *           1 : DMA feature used  
-  * @retval pointer to destination buffer
-  */
-void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
-{
-  uint32_t i=0;
-  uint32_t count32b = (len + 3) / 4;
-  
-  for ( i = 0; i < count32b; i++, dest += 4 )
-  {
-    *(__packed uint32_t *)dest = USBx_DFIFO(0);
-    
-  }
-  return ((void *)dest);
-}
-
-/**
-  * @brief  USB_EPSetStall : set a stall condition over an EP
-  * @param  USBx: Selected device
-  * @param  ep: pointer to endpoint structure   
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep)
-{
-  if (ep->is_in == 1)
-  {
-    if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == 0)
-    {
-      USBx_INEP(ep->num)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); 
-    } 
-    USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;
-  }
-  else
-  {
-    if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == 0)
-    {
-      USBx_OUTEP(ep->num)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); 
-    } 
-    USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;
-  }
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  USB_EPClearStall : Clear a stall condition over an EP
-  * @param  USBx: Selected device
-  * @param  ep: pointer to endpoint structure   
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
-{
-  if (ep->is_in == 1)
-  {
-    USBx_INEP(ep->num)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
-    if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)
-    {
-       USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */
-    }    
-  }
-  else
-  {
-    USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
-    if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)
-    {
-      USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */
-    }    
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_StopDevice : Stop the USB device mode
-  * @param  USBx: Selected device
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)
-{
-  uint32_t i;
-  
-  /* Clear Pending interrupt */
-  for (i = 0; i < 15 ; i++)
-  {
-    USBx_INEP(i)->DIEPINT  = 0xFF;
-    USBx_OUTEP(i)->DOEPINT  = 0xFF;
-  }
-  USBx_DEVICE->DAINT = 0xFFFFFFFF;
-  
-  /* Clear interrupt masks */
-  USBx_DEVICE->DIEPMSK  = 0;
-  USBx_DEVICE->DOEPMSK  = 0;
-  USBx_DEVICE->DAINTMSK = 0;
-  
-  /* Flush the FIFO */
-  USB_FlushRxFifo(USBx);
-  USB_FlushTxFifo(USBx ,  0x10 );  
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_SetDevAddress : Stop the USB device mode
-  * @param  USBx: Selected device
-  * @param  address: new device address to be assigned
-  *          This parameter can be a value from 0 to 255
-  * @retval HAL status
-  */
-HAL_StatusTypeDef  USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address)
-{
-  USBx_DEVICE->DCFG &= ~ (USB_OTG_DCFG_DAD);
-  USBx_DEVICE->DCFG |= (address << 4) & USB_OTG_DCFG_DAD ;
-  
-  return HAL_OK;  
-}
-
-/**
-  * @brief  USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down
-  * @param  USBx: Selected device
-  * @retval HAL status
-  */
-HAL_StatusTypeDef  USB_DevConnect (USB_OTG_GlobalTypeDef *USBx)
-{
-  USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS ; 
-  HAL_Delay(3);
-  
-  return HAL_OK;  
-}
-
-/**
-  * @brief  USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down
-  * @param  USBx: Selected device
-  * @retval HAL status
-  */
-HAL_StatusTypeDef  USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx)
-{
-  USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS ; 
-  HAL_Delay(3);
-  
-  return HAL_OK;  
-}
-
-/**
-  * @brief  USB_ReadInterrupts: return the global USB interrupt status
-  * @param  USBx: Selected device
-  * @retval HAL status
-  */
-uint32_t  USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx)
-{
-  uint32_t v = 0;
-  
-  v = USBx->GINTSTS;
-  v &= USBx->GINTMSK;
-  return v;  
-}
-
-/**
-  * @brief  USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
-  * @param  USBx: Selected device
-  * @retval HAL status
-  */
-uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
-{
-  uint32_t v;
-  v  = USBx_DEVICE->DAINT;
-  v &= USBx_DEVICE->DAINTMSK;
-  return ((v & 0xffff0000) >> 16);
-}
-
-/**
-  * @brief  USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
-  * @param  USBx: Selected device
-  * @retval HAL status
-  */
-uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
-{
-  uint32_t v;
-  v  = USBx_DEVICE->DAINT;
-  v &= USBx_DEVICE->DAINTMSK;
-  return ((v & 0xFFFF));
-}
-
-/**
-  * @brief  Returns Device OUT EP Interrupt register
-  * @param  USBx: Selected device
-  * @param  epnum: endpoint number
-  *          This parameter can be a value from 0 to 15
-  * @retval Device OUT EP Interrupt register
-  */
-uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)
-{
-  uint32_t v;
-  v  = USBx_OUTEP(epnum)->DOEPINT;
-  v &= USBx_DEVICE->DOEPMSK;
-  return v;
-}
-
-/**
-  * @brief  Returns Device IN EP Interrupt register
-  * @param  USBx: Selected device
-  * @param  epnum: endpoint number
-  *          This parameter can be a value from 0 to 15
-  * @retval Device IN EP Interrupt register
-  */
-uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)
-{
-  uint32_t v, msk, emp;
-  
-  msk = USBx_DEVICE->DIEPMSK;
-  emp = USBx_DEVICE->DIEPEMPMSK;
-  msk |= ((emp >> epnum) & 0x1) << 7;
-  v = USBx_INEP(epnum)->DIEPINT & msk;
-  return v;
-}
-
-/**
-  * @brief  USB_ClearInterrupts: clear a USB interrupt
-  * @param  USBx: Selected device
-  * @param  interrupt: interrupt flag
-  * @retval None
-  */
-void  USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
-{
-  USBx->GINTSTS |= interrupt; 
-}
-
-/**
-  * @brief  Returns USB core mode
-  * @param  USBx: Selected device
-  * @retval return core mode : Host or Device
-  *          This parameter can be one of these values:
-  *           0 : Host 
-  *           1 : Device
-  */
-uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)
-{
-  return ((USBx->GINTSTS ) & 0x1);
-}
-
-
-/**
-  * @brief  Activate EP0 for Setup transactions
-  * @param  USBx: Selected device
-  * @retval HAL status
-  */
-HAL_StatusTypeDef  USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx)
-{
-  /* Set the MPS of the IN EP based on the enumeration speed */
-  USBx_INEP(0)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
-  
-  if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
-  {
-    USBx_INEP(0)->DIEPCTL |= 3;
-  }
-  USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;
-
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  Prepare the EP0 to start the first control setup
-  * @param  USBx: Selected device
-  * @param  dma: USB dma enabled or disabled 
-  *          This parameter can be one of these values:
-  *           0 : DMA feature not used 
-  *           1 : DMA feature used  
-  * @param  psetup: pointer to setup packet
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(psetup);
-
-  USBx_OUTEP(0)->DOEPTSIZ = 0;
-  USBx_OUTEP(0)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ;
-  USBx_OUTEP(0)->DOEPTSIZ |= (3 * 8);
-  USBx_OUTEP(0)->DOEPTSIZ |=  USB_OTG_DOEPTSIZ_STUPCNT;  
-  
-  if (dma == 1)
-  {
-    USBx_OUTEP(0)->DOEPDMA = (uint32_t)psetup;
-    /* EP enable */
-    USBx_OUTEP(0)->DOEPCTL = 0x80008000;
-  }
-  
-  return HAL_OK;  
-}
-
-
-/**
-  * @brief  Reset the USB Core (needed after USB clock settings change)
-  * @param  USBx: Selected device
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
-{
-  uint32_t count = 0;
-
-  /* Wait for AHB master IDLE state. */
-  do
-  {
-    if (++count > 200000)
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0);
-  
-  /* Core Soft Reset */
-  count = 0;
-  USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
-
-  do
-  {
-    if (++count > 200000)
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
-  
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  USB_HostInit : Initializes the USB OTG controller registers 
-  *         for Host mode 
-  * @param  USBx: Selected device
-  * @param  cfg: pointer to a USB_OTG_CfgTypeDef structure that contains
-  *         the configuration information for the specified USBx peripheral.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
-{
-  uint32_t i;
-  
-  /* Restart the Phy Clock */
-  USBx_PCGCCTL = 0;
-    
-  /*Activate VBUS Sensing B */
-  USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
-  
-  /* Disable the FS/LS support mode only */
-  if((cfg.speed == USB_OTG_SPEED_FULL)&&
-     (USBx != USB_OTG_FS))
-  {
-    USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS; 
-  }
-  else
-  {
-    USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);  
-  }
-
-  /* Make sure the FIFOs are flushed. */
-  USB_FlushTxFifo(USBx, 0x10 ); /* all Tx FIFOs */
-  USB_FlushRxFifo(USBx);
-
-  /* Clear all pending HC Interrupts */
-  for (i = 0; i < cfg.Host_channels; i++)
-  {
-    USBx_HC(i)->HCINT = 0xFFFFFFFF;
-    USBx_HC(i)->HCINTMSK = 0;
-  }
-  
-  /* Enable VBUS driving */
-  USB_DriveVbus(USBx, 1);
-  
-  HAL_Delay(200);
-  
-  /* Disable all interrupts. */
-  USBx->GINTMSK = 0;
-  
-  /* Clear any pending interrupts */
-  USBx->GINTSTS = 0xFFFFFFFF;
-  
-  /* set Rx FIFO size */
-  USBx->GRXFSIZ  = (uint32_t )0x80; 
-  USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x60 << 16)& USB_OTG_NPTXFD) | 0x80);
-  USBx->HPTXFSIZ = (uint32_t )(((0x40 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0);
-  
-  /* Enable the common interrupts */
-  if (cfg.dma_enable == DISABLE)
-  {
-    USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; 
-  }
-
-    /* Enable interrupts matching to the Host mode ONLY */
-  USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM            | USB_OTG_GINTMSK_HCIM |\
-                    USB_OTG_GINTMSK_SOFM             |USB_OTG_GINTSTS_DISCINT|\
-                    USB_OTG_GINTMSK_PXFRM_IISOOXFRM  | USB_OTG_GINTMSK_WUIM);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the 
-  *         HCFG register on the PHY type and set the right frame interval
-  * @param  USBx: Selected device
-  * @param  freq: clock frequency
-  *          This parameter can be one of these values:
-  *           HCFG_48_MHZ : Full Speed 48 MHz Clock 
-  *           HCFG_6_MHZ : Low Speed 6 MHz Clock 
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq)
-{
-  USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS);
-  USBx_HOST->HCFG |= (freq & USB_OTG_HCFG_FSLSPCS);
-  
-  if (freq ==  HCFG_48_MHZ)
-  {
-    USBx_HOST->HFIR = (uint32_t)48000;
-  }
-  else if (freq ==  HCFG_6_MHZ)
-  {
-    USBx_HOST->HFIR = (uint32_t)6000;
-  } 
-  return HAL_OK;  
-}
-
-/**
-* @brief  USB_OTG_ResetPort : Reset Host Port
-  * @param  USBx: Selected device
-  * @retval HAL status
-  * @note   (1)The application must wait at least 10 ms
-  *   before clearing the reset bit.
-  */
-HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
-{
-  __IO uint32_t hprt0;
-  
-  hprt0 = USBx_HPRT0;
-  
-  hprt0 &= ~(USB_OTG_HPRT_PENA    | USB_OTG_HPRT_PCDET |\
-    USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
-  
-  USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0);  
-  HAL_Delay (10);                                /* See Note #1 */
-  USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0); 
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_DriveVbus : activate or de-activate vbus
-  * @param  state: VBUS state
-  *          This parameter can be one of these values:
-  *           0 : VBUS Active 
-  *           1 : VBUS Inactive
-  * @retval HAL status
-*/
-HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state)
-{
-  __IO uint32_t hprt0;
-
-  hprt0 = USBx_HPRT0;
-  hprt0 &= ~(USB_OTG_HPRT_PENA    | USB_OTG_HPRT_PCDET |\
-                         USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
-  
-  if (((hprt0 & USB_OTG_HPRT_PPWR) == 0 ) && (state == 1 ))
-  {
-    USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0); 
-  }
-  if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0 ))
-  {
-    USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0); 
-  }
-  return HAL_OK; 
-}
-
-/**
-  * @brief  Return Host Core speed
-  * @param  USBx: Selected device
-  * @retval speed : Host speed
-  *          This parameter can be one of these values:
-  *            @arg USB_OTG_SPEED_HIGH: High speed mode
-  *            @arg USB_OTG_SPEED_FULL: Full speed mode
-  *            @arg USB_OTG_SPEED_LOW: Low speed mode
-  */
-uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx)
-{
-  __IO uint32_t hprt0;
-  
-  hprt0 = USBx_HPRT0;
-  return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17);
-}
-
-/**
-  * @brief  Return Host Current Frame number
-  * @param  USBx: Selected device
-  * @retval current frame number
-*/
-uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx)
-{
-  return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM);
-}
-
-/**
-  * @brief  Initialize a host channel
-  * @param  USBx: Selected device
-  * @param  ch_num : Channel number
-  *         This parameter can be a value from 1 to 15
-  * @param  epnum: Endpoint number
-  *          This parameter can be a value from 1 to 15
-  * @param  dev_address: Current device address
-  *          This parameter can be a value from 0 to 255
-  * @param  speed: Current device speed
-  *          This parameter can be one of these values:
-  *            @arg USB_OTG_SPEED_HIGH: High speed mode
-  *            @arg USB_OTG_SPEED_FULL: Full speed mode
-  *            @arg USB_OTG_SPEED_LOW: Low speed mode
-  * @param  ep_type: Endpoint Type
-  *          This parameter can be one of these values:
-  *            @arg EP_TYPE_CTRL: Control type
-  *            @arg EP_TYPE_ISOC: Isochronous type
-  *            @arg EP_TYPE_BULK: Bulk type
-  *            @arg EP_TYPE_INTR: Interrupt type
-  * @param  mps: Max Packet Size
-  *          This parameter can be a value from 0 to32K
-  * @retval HAL state
-  */
-HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,  
-                              uint8_t ch_num,
-                              uint8_t epnum,
-                              uint8_t dev_address,
-                              uint8_t speed,
-                              uint8_t ep_type,
-                              uint16_t mps)
-{
-    
-  /* Clear old interrupt conditions for this host channel. */
-  USBx_HC(ch_num)->HCINT = 0xFFFFFFFF;
-  
-  /* Enable channel interrupts required for this transfer. */
-  switch (ep_type) 
-  {
-  case EP_TYPE_CTRL:
-  case EP_TYPE_BULK:
-    
-    USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |\
-                                USB_OTG_HCINTMSK_STALLM |\
-                                USB_OTG_HCINTMSK_TXERRM |\
-                                USB_OTG_HCINTMSK_DTERRM |\
-                                USB_OTG_HCINTMSK_AHBERR |\
-                                USB_OTG_HCINTMSK_NAKM ;
- 
-    if (epnum & 0x80) 
-    {
-      USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
-    }
-    break;
-    
-  case EP_TYPE_INTR:
-    
-    USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |\
-                                USB_OTG_HCINTMSK_STALLM |\
-                                USB_OTG_HCINTMSK_TXERRM |\
-                                USB_OTG_HCINTMSK_DTERRM |\
-                                USB_OTG_HCINTMSK_NAKM   |\
-                                USB_OTG_HCINTMSK_AHBERR |\
-                                USB_OTG_HCINTMSK_FRMORM ;    
-    
-    if (epnum & 0x80) 
-    {
-      USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
-    }
-    
-    break;
-  case EP_TYPE_ISOC:
-    
-    USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |\
-                                USB_OTG_HCINTMSK_ACKM   |\
-                                USB_OTG_HCINTMSK_AHBERR |\
-                                USB_OTG_HCINTMSK_FRMORM ;   
-    
-    if (epnum & 0x80) 
-    {
-      USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM);      
-    }
-    break;
-  }
-  
-  /* Enable the top level host channel interrupt. */
-  USBx_HOST->HAINTMSK |= (1 << ch_num);
-  
-  /* Make sure host channel interrupts are enabled. */
-  USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM;
-  
-  /* Program the HCCHAR register */
-  USBx_HC(ch_num)->HCCHAR = (((dev_address << 22) & USB_OTG_HCCHAR_DAD)  |\
-                             (((epnum & 0x7F)<< 11) & USB_OTG_HCCHAR_EPNUM)|\
-                             ((((epnum & 0x80) == 0x80)<< 15) & USB_OTG_HCCHAR_EPDIR)|\
-                             (((speed == HPRT0_PRTSPD_LOW_SPEED)<< 17) & USB_OTG_HCCHAR_LSDEV)|\
-                             ((ep_type << 18) & USB_OTG_HCCHAR_EPTYP)|\
-                             (mps & USB_OTG_HCCHAR_MPSIZ));
-    
-  if (ep_type == EP_TYPE_INTR)
-  {
-    USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ;
-  }
-
-  return HAL_OK; 
-}
-
-/**
-  * @brief  Start a transfer over a host channel
-  * @param  USBx: Selected device
-  * @param  hc: pointer to host channel structure
-  * @param  dma: USB dma enabled or disabled 
-  *          This parameter can be one of these values:
-  *           0 : DMA feature not used 
-  *           1 : DMA feature used  
-  * @retval HAL state
-  */
-#if defined   (__CC_ARM) /*!< ARM Compiler */
-#pragma O0
-#elif defined (__GNUC__) /*!< GNU Compiler */
-#pragma GCC optimize ("O0")
-#endif /* __CC_ARM */
-HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma)
-{
-  uint8_t  is_oddframe = 0; 
-  uint16_t len_words = 0;   
-  uint16_t num_packets = 0;
-  uint16_t max_hc_pkt_count = 256;
-  uint32_t tmpreg = 0;
-    
-  /* Compute the expected number of packets associated to the transfer */
-  if (hc->xfer_len > 0)
-  {
-    num_packets = (hc->xfer_len + hc->max_packet - 1) / hc->max_packet;
-    
-    if (num_packets > max_hc_pkt_count)
-    {
-      num_packets = max_hc_pkt_count;
-      hc->xfer_len = num_packets * hc->max_packet;
-    }
-  }
-  else
-  {
-    num_packets = 1;
-  }
-  if (hc->ep_is_in)
-  {
-    hc->xfer_len = num_packets * hc->max_packet;
-  }
-  
-  /* Initialize the HCTSIZn register */
-  USBx_HC(hc->ch_num)->HCTSIZ = (((hc->xfer_len) & USB_OTG_HCTSIZ_XFRSIZ)) |\
-    ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\
-      (((hc->data_pid) << 29) & USB_OTG_HCTSIZ_DPID);
-  
-  if (dma)
-  {
-    /* xfer_buff MUST be 32-bits aligned */
-    USBx_HC(hc->ch_num)->HCDMA = (uint32_t)hc->xfer_buff;
-  }
-  
-  is_oddframe = (USBx_HOST->HFNUM & 0x01) ? 0 : 1;
-  USBx_HC(hc->ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;
-  USBx_HC(hc->ch_num)->HCCHAR |= (is_oddframe << 29);
-  
-  /* Set host channel enable */
-  tmpreg = USBx_HC(hc->ch_num)->HCCHAR;
-  tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
-  tmpreg |= USB_OTG_HCCHAR_CHENA;
-  USBx_HC(hc->ch_num)->HCCHAR = tmpreg;
-  
-  if (dma == 0) /* Slave mode */
-  {  
-    if((hc->ep_is_in == 0) && (hc->xfer_len > 0))
-    {
-      switch(hc->ep_type) 
-      {
-        /* Non periodic transfer */
-      case EP_TYPE_CTRL:
-      case EP_TYPE_BULK:
-        
-        len_words = (hc->xfer_len + 3) / 4;
-        
-        /* check if there is enough space in FIFO space */
-        if(len_words > (USBx->HNPTXSTS & 0xFFFF))
-        {
-          /* need to process data in nptxfempty interrupt */
-          USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM;
-        }
-        break;
-        /* Periodic transfer */
-      case EP_TYPE_INTR:
-      case EP_TYPE_ISOC:
-        len_words = (hc->xfer_len + 3) / 4;
-        /* check if there is enough space in FIFO space */
-        if(len_words > (USBx_HOST->HPTXSTS & 0xFFFF)) /* split the transfer */
-        {
-          /* need to process data in ptxfempty interrupt */
-          USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM;          
-        }
-        break;
-        
-      default:
-        break;
-      }
-      
-      /* Write packet into the Tx FIFO. */
-      USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, hc->xfer_len, 0);
-    }
-  }
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief Read all host channel interrupts status
-  * @param  USBx: Selected device
-  * @retval HAL state
-  */
-uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx)
-{
-  return ((USBx_HOST->HAINT) & 0xFFFF);
-}
-
-/**
-  * @brief  Halt a host channel
-  * @param  USBx: Selected device
-  * @param  hc_num: Host Channel number
-  *         This parameter can be a value from 1 to 15
-  * @retval HAL state
-  */
-HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num)
-{
-  uint32_t count = 0;
-  
-  /* Check for space in the request queue to issue the halt. */
-  if (((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_CTRL << 18)) || ((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_BULK << 18)))
-  {
-    USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
-    
-    if ((USBx->HNPTXSTS & 0xFFFF) == 0)
-    {
-      USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
-      USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;  
-      USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
-      do 
-      {
-        if (++count > 1000) 
-        {
-          break;
-        }
-      } 
-      while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);     
-    }
-    else
-    {
-      USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; 
-    }
-  }
-  else
-  {
-    USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
-    
-    if ((USBx_HOST->HPTXSTS & 0xFFFF) == 0)
-    {
-      USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
-      USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;  
-      USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
-      do 
-      {
-        if (++count > 1000) 
-        {
-          break;
-        }
-      } 
-      while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);     
-    }
-    else
-    {
-       USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; 
-    }
-  }
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initiate Do Ping protocol
-  * @param  USBx: Selected device
-  * @param  hc_num: Host Channel number
-  *         This parameter can be a value from 1 to 15
-  * @retval HAL state
-  */
-HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num)
-{
-  uint8_t  num_packets = 1;
-  uint32_t tmpreg = 0;
-  
-  USBx_HC(ch_num)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\
-                                USB_OTG_HCTSIZ_DOPING;
-  
-  /* Set host channel enable */
-  tmpreg = USBx_HC(ch_num)->HCCHAR;
-  tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
-  tmpreg |= USB_OTG_HCCHAR_CHENA;
-  USBx_HC(ch_num)->HCCHAR = tmpreg;
-  
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Stop Host Core
-  * @param  USBx: Selected device
-  * @retval HAL state
-  */
-HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
-{
-  uint8_t i;
-  uint32_t count = 0;
-  uint32_t value;
-  
-  USB_DisableGlobalInt(USBx);
-  
-    /* Flush FIFO */
-  USB_FlushTxFifo(USBx, 0x10);
-  USB_FlushRxFifo(USBx);
-  
-  /* Flush out any leftover queued requests. */
-  for (i = 0; i <= 15; i++)
-  {   
-
-    value = USBx_HC(i)->HCCHAR ;
-    value |=  USB_OTG_HCCHAR_CHDIS;
-    value &= ~USB_OTG_HCCHAR_CHENA;  
-    value &= ~USB_OTG_HCCHAR_EPDIR;
-    USBx_HC(i)->HCCHAR = value;
-  }
-  
-  /* Halt all channels to put them into a known state. */  
-  for (i = 0; i <= 15; i++)
-  {   
-    value = USBx_HC(i)->HCCHAR ;
-    
-    value |= USB_OTG_HCCHAR_CHDIS;
-    value |= USB_OTG_HCCHAR_CHENA;  
-    value &= ~USB_OTG_HCCHAR_EPDIR;
-    
-    USBx_HC(i)->HCCHAR = value;
-    do 
-    {
-      if (++count > 1000) 
-      {
-        break;
-      }
-    } 
-    while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
-  }
-
-  /* Clear any pending Host interrupts */  
-  USBx_HOST->HAINT = 0xFFFFFFFF;
-  USBx->GINTSTS = 0xFFFFFFFF;
-  USB_EnableGlobalInt(USBx);
-  return HAL_OK;  
-}
-/**
-  * @}
-  */
-
-#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */
-
-/**
-  * @}
-  */
-
-#endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stmhal/modules/lcd160cr.py b/stmhal/modules/lcd160cr.py
deleted file mode 120000
index c0e180714d..0000000000
--- a/stmhal/modules/lcd160cr.py
+++ /dev/null
@@ -1 +0,0 @@
-../../drivers/display/lcd160cr.py
\ No newline at end of file
diff --git a/stmhal/modules/lcd160cr_test.py b/stmhal/modules/lcd160cr_test.py
deleted file mode 120000
index 56f091351b..0000000000
--- a/stmhal/modules/lcd160cr_test.py
+++ /dev/null
@@ -1 +0,0 @@
-../../drivers/display/lcd160cr_test.py
\ No newline at end of file
diff --git a/stmhal/modules/onewire.py b/stmhal/modules/onewire.py
deleted file mode 120000
index f6ec745e85..0000000000
--- a/stmhal/modules/onewire.py
+++ /dev/null
@@ -1 +0,0 @@
-../../drivers/onewire/onewire.py
\ No newline at end of file
diff --git a/stmhal/usbd_cdc_interface.h b/stmhal/usbd_cdc_interface.h
deleted file mode 100644
index 811a289280..0000000000
--- a/stmhal/usbd_cdc_interface.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * This file is part of the MicroPython project, http://micropython.org/
- */
-#ifndef MICROPY_INCLUDED_STMHAL_USBD_CDC_INTERFACE_H
-#define MICROPY_INCLUDED_STMHAL_USBD_CDC_INTERFACE_H
-
-/**
-  ******************************************************************************
-  * @file    USB_Device/CDC_Standalone/Inc/usbd_cdc_interface.h
-  * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    26-February-2014
-  * @brief   Header for usbd_cdc_interface.c file.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an "AS IS" BASIS,
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-extern const USBD_CDC_ItfTypeDef USBD_CDC_fops;
-
-int USBD_CDC_IsConnected(void);
-
-int USBD_CDC_TxHalfEmpty(void);
-int USBD_CDC_Tx(const uint8_t *buf, uint32_t len, uint32_t timeout);
-void USBD_CDC_TxAlways(const uint8_t *buf, uint32_t len);
-
-int USBD_CDC_RxNum(void);
-int USBD_CDC_Rx(uint8_t *buf, uint32_t len, uint32_t timeout);
-
-#endif // MICROPY_INCLUDED_STMHAL_USBD_CDC_INTERFACE_H
diff --git a/stmhal/usbd_hid_interface.h b/stmhal/usbd_hid_interface.h
deleted file mode 100644
index b2ff75fa13..0000000000
--- a/stmhal/usbd_hid_interface.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * This file is part of the MicroPython project, http://micropython.org/
- */
-#ifndef MICROPY_INCLUDED_STMHAL_USBD_HID_INTERFACE_H
-#define MICROPY_INCLUDED_STMHAL_USBD_HID_INTERFACE_H
-
-#include "usbd_cdc_msc_hid.h"
-
-extern const USBD_HID_ItfTypeDef USBD_HID_fops;
-
-int USBD_HID_RxNum(void);
-int USBD_HID_Rx(USBD_HandleTypeDef *pdev, uint8_t *buf, uint32_t len, uint32_t timeout);
-
-#endif // MICROPY_INCLUDED_STMHAL_USBD_HID_INTERFACE_H
diff --git a/stmhal/usbdev/class/src/usbd_msc.c b/stmhal/usbdev/class/src/usbd_msc.c
deleted file mode 100644
index 7817c98b1c..0000000000
--- a/stmhal/usbdev/class/src/usbd_msc.c
+++ /dev/null
@@ -1,609 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    usbd_msc_core.c
-  * @author  MCD Application Team
-  * @version V2.0.0
-  * @date    18-February-2014
-  * @brief   This file provides all the MSC core functions.
-  *
-  * @verbatim
-  *      
-  *          ===================================================================      
-  *                                MSC Class  Description
-  *          =================================================================== 
-  *           This module manages the MSC class V1.0 following the "Universal 
-  *           Serial Bus Mass Storage Class (MSC) Bulk-Only Transport (BOT) Version 1.0
-  *           Sep. 31, 1999".
-  *           This driver implements the following aspects of the specification:
-  *             - Bulk-Only Transport protocol
-  *             - Subclass : SCSI transparent command set (ref. SCSI Primary Commands - 3 (SPC-3))
-  *      
-  *  @endverbatim
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_msc.h"
-
-
-/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
-  * @{
-  */
-
-
-/** @defgroup MSC_CORE 
-  * @brief Mass storage core module
-  * @{
-  */ 
-
-/** @defgroup MSC_CORE_Private_TypesDefinitions
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup MSC_CORE_Private_Defines
-  * @{
-  */ 
-
-/**
-  * @}
-  */ 
-
-
-/** @defgroup MSC_CORE_Private_Macros
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup MSC_CORE_Private_FunctionPrototypes
-  * @{
-  */ 
-uint8_t  USBD_MSC_Init (USBD_HandleTypeDef *pdev, 
-                            uint8_t cfgidx);
-
-uint8_t  USBD_MSC_DeInit (USBD_HandleTypeDef *pdev, 
-                              uint8_t cfgidx);
-
-uint8_t  USBD_MSC_Setup (USBD_HandleTypeDef *pdev, 
-                             USBD_SetupReqTypedef *req);
-
-uint8_t  USBD_MSC_DataIn (USBD_HandleTypeDef *pdev, 
-                              uint8_t epnum);
-
-
-uint8_t  USBD_MSC_DataOut (USBD_HandleTypeDef *pdev, 
-                               uint8_t epnum);
-
-uint8_t  *USBD_MSC_GetHSCfgDesc (uint16_t *length);
-
-uint8_t  *USBD_MSC_GetFSCfgDesc (uint16_t *length);
-
-uint8_t  *USBD_MSC_GetOtherSpeedCfgDesc (uint16_t *length);
-
-uint8_t  *USBD_MSC_GetDeviceQualifierDescriptor (uint16_t *length);
-
-
-/**
-  * @}
-  */ 
-
-
-/** @defgroup MSC_CORE_Private_Variables
-  * @{
-  */ 
-
-
-USBD_ClassTypeDef  USBD_MSC = 
-{
-  USBD_MSC_Init,
-  USBD_MSC_DeInit,
-  USBD_MSC_Setup,
-  NULL, /*EP0_TxSent*/  
-  NULL, /*EP0_RxReady*/
-  USBD_MSC_DataIn,
-  USBD_MSC_DataOut,
-  NULL, /*SOF */ 
-  NULL,  
-  NULL,     
-  USBD_MSC_GetHSCfgDesc,
-  USBD_MSC_GetFSCfgDesc,  
-  USBD_MSC_GetOtherSpeedCfgDesc,
-  USBD_MSC_GetDeviceQualifierDescriptor,
-};
-
-/* USB Mass storage device Configuration Descriptor */
-/*   All Descriptors (Configuration, Interface, Endpoint, Class, Vendor */
-__ALIGN_BEGIN uint8_t USBD_MSC_CfgHSDesc[USB_MSC_CONFIG_DESC_SIZ]  __ALIGN_END =
-{
-  
-  0x09,   /* bLength: Configuation Descriptor size */
-  USB_DESC_TYPE_CONFIGURATION,   /* bDescriptorType: Configuration */
-  USB_MSC_CONFIG_DESC_SIZ,
-  
-  0x00,
-  0x01,   /* bNumInterfaces: 1 interface */
-  0x01,   /* bConfigurationValue: */
-  0x04,   /* iConfiguration: */
-  0xC0,   /* bmAttributes: */
-  0x32,   /* MaxPower 100 mA */
-  
-  /********************  Mass Storage interface ********************/
-  0x09,   /* bLength: Interface Descriptor size */
-  0x04,   /* bDescriptorType: */
-  0x00,   /* bInterfaceNumber: Number of Interface */
-  0x00,   /* bAlternateSetting: Alternate setting */
-  0x02,   /* bNumEndpoints*/
-  0x08,   /* bInterfaceClass: MSC Class */
-  0x06,   /* bInterfaceSubClass : SCSI transparent*/
-  0x50,   /* nInterfaceProtocol */
-  0x05,          /* iInterface: */
-  /********************  Mass Storage Endpoints ********************/
-  0x07,   /*Endpoint descriptor length = 7*/
-  0x05,   /*Endpoint descriptor type */
-  MSC_EPIN_ADDR,   /*Endpoint address (IN, address 1) */
-  0x02,   /*Bulk endpoint type */
-  LOBYTE(MSC_MAX_HS_PACKET),
-  HIBYTE(MSC_MAX_HS_PACKET),
-  0x00,   /*Polling interval in milliseconds */
-  
-  0x07,   /*Endpoint descriptor length = 7 */
-  0x05,   /*Endpoint descriptor type */
-  MSC_EPOUT_ADDR,   /*Endpoint address (OUT, address 1) */
-  0x02,   /*Bulk endpoint type */
-  LOBYTE(MSC_MAX_HS_PACKET),
-  HIBYTE(MSC_MAX_HS_PACKET),
-  0x00     /*Polling interval in milliseconds*/
-};
-
-/* USB Mass storage device Configuration Descriptor */
-/*   All Descriptors (Configuration, Interface, Endpoint, Class, Vendor */
-uint8_t USBD_MSC_CfgFSDesc[USB_MSC_CONFIG_DESC_SIZ]  __ALIGN_END =
-{
-  
-  0x09,   /* bLength: Configuation Descriptor size */
-  USB_DESC_TYPE_CONFIGURATION,   /* bDescriptorType: Configuration */
-  USB_MSC_CONFIG_DESC_SIZ,
-  
-  0x00,
-  0x01,   /* bNumInterfaces: 1 interface */
-  0x01,   /* bConfigurationValue: */
-  0x04,   /* iConfiguration: */
-  0xC0,   /* bmAttributes: */
-  0x32,   /* MaxPower 100 mA */
-  
-  /********************  Mass Storage interface ********************/
-  0x09,   /* bLength: Interface Descriptor size */
-  0x04,   /* bDescriptorType: */
-  0x00,   /* bInterfaceNumber: Number of Interface */
-  0x00,   /* bAlternateSetting: Alternate setting */
-  0x02,   /* bNumEndpoints*/
-  0x08,   /* bInterfaceClass: MSC Class */
-  0x06,   /* bInterfaceSubClass : SCSI transparent*/
-  0x50,   /* nInterfaceProtocol */
-  0x05,          /* iInterface: */
-  /********************  Mass Storage Endpoints ********************/
-  0x07,   /*Endpoint descriptor length = 7*/
-  0x05,   /*Endpoint descriptor type */
-  MSC_EPIN_ADDR,   /*Endpoint address (IN, address 1) */
-  0x02,   /*Bulk endpoint type */
-  LOBYTE(MSC_MAX_FS_PACKET),
-  HIBYTE(MSC_MAX_FS_PACKET),
-  0x00,   /*Polling interval in milliseconds */
-  
-  0x07,   /*Endpoint descriptor length = 7 */
-  0x05,   /*Endpoint descriptor type */
-  MSC_EPOUT_ADDR,   /*Endpoint address (OUT, address 1) */
-  0x02,   /*Bulk endpoint type */
-  LOBYTE(MSC_MAX_FS_PACKET),
-  HIBYTE(MSC_MAX_FS_PACKET),
-  0x00     /*Polling interval in milliseconds*/
-};
-
-__ALIGN_BEGIN uint8_t USBD_MSC_OtherSpeedCfgDesc[USB_MSC_CONFIG_DESC_SIZ]   __ALIGN_END  =
-{
-  
-  0x09,   /* bLength: Configuation Descriptor size */
-  USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION,   
-  USB_MSC_CONFIG_DESC_SIZ,
-  
-  0x00,
-  0x01,   /* bNumInterfaces: 1 interface */
-  0x01,   /* bConfigurationValue: */
-  0x04,   /* iConfiguration: */
-  0xC0,   /* bmAttributes: */
-  0x32,   /* MaxPower 100 mA */
-  
-  /********************  Mass Storage interface ********************/
-  0x09,   /* bLength: Interface Descriptor size */
-  0x04,   /* bDescriptorType: */
-  0x00,   /* bInterfaceNumber: Number of Interface */
-  0x00,   /* bAlternateSetting: Alternate setting */
-  0x02,   /* bNumEndpoints*/
-  0x08,   /* bInterfaceClass: MSC Class */
-  0x06,   /* bInterfaceSubClass : SCSI transparent command set*/
-  0x50,   /* nInterfaceProtocol */
-  0x05,          /* iInterface: */
-  /********************  Mass Storage Endpoints ********************/
-  0x07,   /*Endpoint descriptor length = 7*/
-  0x05,   /*Endpoint descriptor type */
-  MSC_EPIN_ADDR,   /*Endpoint address (IN, address 1) */
-  0x02,   /*Bulk endpoint type */
-  0x40,
-  0x00,
-  0x00,   /*Polling interval in milliseconds */
-  
-  0x07,   /*Endpoint descriptor length = 7 */
-  0x05,   /*Endpoint descriptor type */
-  MSC_EPOUT_ADDR,   /*Endpoint address (OUT, address 1) */
-  0x02,   /*Bulk endpoint type */
-  0x40,
-  0x00,
-  0x00     /*Polling interval in milliseconds*/
-};
-
-/* USB Standard Device Descriptor */
-__ALIGN_BEGIN  uint8_t USBD_MSC_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC]  __ALIGN_END =
-{
-  USB_LEN_DEV_QUALIFIER_DESC,
-  USB_DESC_TYPE_DEVICE_QUALIFIER,
-  0x00,
-  0x02,
-  0x00,
-  0x00,
-  0x00,
-  MSC_MAX_FS_PACKET,
-  0x01,
-  0x00,
-};
-/**
-  * @}
-  */ 
-
-
-/** @defgroup MSC_CORE_Private_Functions
-  * @{
-  */ 
-
-/**
-  * @brief  USBD_MSC_Init
-  *         Initialize  the mass storage configuration
-  * @param  pdev: device instance
-  * @param  cfgidx: configuration index
-  * @retval status
-  */
-uint8_t  USBD_MSC_Init (USBD_HandleTypeDef *pdev, 
-                            uint8_t cfgidx)
-{
-  int16_t ret = 0;
-   
-  if(pdev->dev_speed == USBD_SPEED_HIGH  ) 
-  {
-    /* Open EP OUT */
-    USBD_LL_OpenEP(pdev,
-                   MSC_EPOUT_ADDR,
-                   USBD_EP_TYPE_BULK,
-                   MSC_MAX_HS_PACKET);
-    
-    /* Open EP IN */
-    USBD_LL_OpenEP(pdev,
-                   MSC_EPIN_ADDR,
-                   USBD_EP_TYPE_BULK,
-                   MSC_MAX_HS_PACKET);  
-  }
-  else
-  {
-    /* Open EP OUT */
-    USBD_LL_OpenEP(pdev,
-                   MSC_EPOUT_ADDR,
-                   USBD_EP_TYPE_BULK,
-                   MSC_MAX_FS_PACKET);
-    
-    /* Open EP IN */
-    USBD_LL_OpenEP(pdev,
-                   MSC_EPIN_ADDR,
-                   USBD_EP_TYPE_BULK,
-                   MSC_MAX_FS_PACKET);  
-  }
-  pdev->pClassData = USBD_malloc(sizeof (USBD_MSC_BOT_HandleTypeDef));
-  
-  if(pdev->pClassData == NULL)
-  {
-    ret = 1; 
-  }
-  else
-  {
-    /* Init the BOT  layer */
-    MSC_BOT_Init(pdev); 
-    ret = 0;
-  }
-  
-  return ret;
-}
-
-/**
-  * @brief  USBD_MSC_DeInit
-  *         DeInitilaize  the mass storage configuration
-  * @param  pdev: device instance
-  * @param  cfgidx: configuration index
-  * @retval status
-  */
-uint8_t  USBD_MSC_DeInit (USBD_HandleTypeDef *pdev, 
-                              uint8_t cfgidx)
-{
-  /* Close MSC EPs */
-  USBD_LL_CloseEP(pdev,
-                  MSC_EPOUT_ADDR);
-  
-  /* Open EP IN */
-  USBD_LL_CloseEP(pdev,
-                  MSC_EPIN_ADDR);
-  
-  
-    /* D-Init the BOT layer */
-  MSC_BOT_DeInit(pdev);
-  
-  /* Free MSC Class Resources */
-  if(pdev->pClassData != NULL)
-  {
-    USBD_free(pdev->pClassData);
-    pdev->pClassData  = NULL; 
-  }
-  return 0;
-}
-/**
-* @brief  USBD_MSC_Setup
-*         Handle the MSC specific requests
-* @param  pdev: device instance
-* @param  req: USB request
-* @retval status
-*/
-uint8_t  USBD_MSC_Setup (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
-{
-  USBD_MSC_BOT_HandleTypeDef     *hmsc = pdev->pClassData;
-  
-  switch (req->bmRequest & USB_REQ_TYPE_MASK)
-  {
-
-  /* Class request */
-  case USB_REQ_TYPE_CLASS :
-    switch (req->bRequest)
-    {
-    case BOT_GET_MAX_LUN :
-
-      if((req->wValue  == 0) && 
-         (req->wLength == 1) &&
-         ((req->bmRequest & 0x80) == 0x80))
-      {
-        hmsc->max_lun = ((USBD_StorageTypeDef *)pdev->pUserData)->GetMaxLun();
-        USBD_CtlSendData (pdev,
-                          (uint8_t *)&hmsc->max_lun,
-                          1);
-      }
-      else
-      {
-         USBD_CtlError(pdev , req);
-         return USBD_FAIL; 
-      }
-      break;
-      
-    case BOT_RESET :
-      if((req->wValue  == 0) && 
-         (req->wLength == 0) &&
-        ((req->bmRequest & 0x80) != 0x80))
-      {      
-         MSC_BOT_Reset(pdev);
-      }
-      else
-      {
-         USBD_CtlError(pdev , req);
-         return USBD_FAIL; 
-      }
-      break;
-
-    default:
-       USBD_CtlError(pdev , req);
-       return USBD_FAIL; 
-    }
-    break;
-  /* Interface & Endpoint request */
-  case USB_REQ_TYPE_STANDARD:
-    switch (req->bRequest)
-    {
-    case USB_REQ_GET_INTERFACE :
-      USBD_CtlSendData (pdev,
-                        (uint8_t *)&hmsc->interface,
-                        1);
-      break;
-      
-    case USB_REQ_SET_INTERFACE :
-      hmsc->interface = (uint8_t)(req->wValue);
-      break;
-    
-    case USB_REQ_CLEAR_FEATURE:  
-      
-      /* Flush the FIFO and Clear the stall status */    
-      USBD_LL_FlushEP(pdev, (uint8_t)req->wIndex);
-      
-      /* Re-activate the EP */      
-      USBD_LL_CloseEP (pdev , (uint8_t)req->wIndex);
-      if((((uint8_t)req->wIndex) & 0x80) == 0x80)
-      {
-        if(pdev->dev_speed == USBD_SPEED_HIGH  ) 
-        {
-          /* Open EP IN */
-          USBD_LL_OpenEP(pdev,
-                         MSC_EPIN_ADDR,
-                         USBD_EP_TYPE_BULK,
-                         MSC_MAX_HS_PACKET);  
-        }
-        else
-        {   
-          /* Open EP IN */
-          USBD_LL_OpenEP(pdev,
-                         MSC_EPIN_ADDR,
-                         USBD_EP_TYPE_BULK,
-                         MSC_MAX_FS_PACKET);  
-        }
-      }
-      else
-      {
-        if(pdev->dev_speed == USBD_SPEED_HIGH  ) 
-        {
-          /* Open EP IN */
-          USBD_LL_OpenEP(pdev,
-                         MSC_EPOUT_ADDR,
-                         USBD_EP_TYPE_BULK,
-                         MSC_MAX_HS_PACKET);  
-        }
-        else
-        {   
-          /* Open EP IN */
-          USBD_LL_OpenEP(pdev,
-                         MSC_EPOUT_ADDR,
-                         USBD_EP_TYPE_BULK,
-                         MSC_MAX_FS_PACKET);  
-        }
-      }
-      
-      /* Handle BOT error */
-      MSC_BOT_CplClrFeature(pdev, (uint8_t)req->wIndex);
-      break;
-      
-    }  
-    break;
-   
-  default:
-    break;
-  }
-  return 0;
-}
-
-/**
-* @brief  USBD_MSC_DataIn
-*         handle data IN Stage
-* @param  pdev: device instance
-* @param  epnum: endpoint index
-* @retval status
-*/
-uint8_t  USBD_MSC_DataIn (USBD_HandleTypeDef *pdev, 
-                              uint8_t epnum)
-{
-  MSC_BOT_DataIn(pdev , epnum);
-  return 0;
-}
-
-/**
-* @brief  USBD_MSC_DataOut
-*         handle data OUT Stage
-* @param  pdev: device instance
-* @param  epnum: endpoint index
-* @retval status
-*/
-uint8_t  USBD_MSC_DataOut (USBD_HandleTypeDef *pdev, 
-                               uint8_t epnum)
-{
-  MSC_BOT_DataOut(pdev , epnum);
-  return 0;
-}
-
-/**
-* @brief  USBD_MSC_GetHSCfgDesc 
-*         return configuration descriptor
-* @param  length : pointer data length
-* @retval pointer to descriptor buffer
-*/
-uint8_t  *USBD_MSC_GetHSCfgDesc (uint16_t *length)
-{
-  *length = sizeof (USBD_MSC_CfgHSDesc);
-  return USBD_MSC_CfgHSDesc;
-}
-
-/**
-* @brief  USBD_MSC_GetFSCfgDesc 
-*         return configuration descriptor
-* @param  length : pointer data length
-* @retval pointer to descriptor buffer
-*/
-uint8_t  *USBD_MSC_GetFSCfgDesc (uint16_t *length)
-{
-  *length = sizeof (USBD_MSC_CfgFSDesc);
-  return USBD_MSC_CfgFSDesc;
-}
-
-/**
-* @brief  USBD_MSC_GetOtherSpeedCfgDesc 
-*         return other speed configuration descriptor
-* @param  length : pointer data length
-* @retval pointer to descriptor buffer
-*/
-uint8_t  *USBD_MSC_GetOtherSpeedCfgDesc (uint16_t *length)
-{
-  *length = sizeof (USBD_MSC_OtherSpeedCfgDesc);
-  return USBD_MSC_OtherSpeedCfgDesc;
-}
-/**
-* @brief  DeviceQualifierDescriptor 
-*         return Device Qualifier descriptor
-* @param  length : pointer data length
-* @retval pointer to descriptor buffer
-*/
-uint8_t  *USBD_MSC_GetDeviceQualifierDescriptor (uint16_t *length)
-{
-  *length = sizeof (USBD_MSC_DeviceQualifierDesc);
-  return USBD_MSC_DeviceQualifierDesc;
-}
-
-/**
-* @brief  USBD_MSC_RegisterStorage
-* @param  fops: storage callback
-* @retval status
-*/
-uint8_t  USBD_MSC_RegisterStorage  (USBD_HandleTypeDef   *pdev, 
-                                    USBD_StorageTypeDef *fops)
-{
-  if(fops != NULL)
-  {
-    pdev->pUserData= fops;
-  }
-  return 0;
-}
-
-/**
-  * @}
-  */ 
-
-
-/**
-  * @}
-  */ 
-
-
-/**
-  * @}
-  */ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tests/basics/bytes.py b/tests/basics/bytes.py
index d3da15c8e9..1d97e6b16f 100644
--- a/tests/basics/bytes.py
+++ b/tests/basics/bytes.py
@@ -8,6 +8,9 @@ print(b'\u1234')
 print(bytes())
 print(bytes(b'abc'))
 
+# make sure empty bytes is converted correctly
+print(str(bytes(), 'utf-8'))
+
 a = b"123"
 print(a)
 print(str(a))
diff --git a/tests/basics/class_inplace_op.py b/tests/basics/class_inplace_op.py
new file mode 100644
index 0000000000..62aad8c7cf
--- /dev/null
+++ b/tests/basics/class_inplace_op.py
@@ -0,0 +1,47 @@
+# Case 1: Immutable object (e.g. number-like)
+# __iadd__ should not be defined, will be emulated using __add__
+
+class A:
+
+    def __init__(self, v):
+        self.v = v
+
+    def __add__(self, o):
+        return A(self.v + o.v)
+
+    def __repr__(self):
+        return "A(%s)" % self.v
+
+a = A(5)
+b = a
+a += A(3)
+print(a)
+# Should be original a's value, i.e. A(5)
+print(b)
+
+# Case 2: Mutable object (e.g. list-like)
+# __iadd__ should be defined
+
+class L:
+
+    def __init__(self, v):
+        self.v = v
+
+    def __add__(self, o):
+        # Should not be caled in this test
+        print("L.__add__")
+        return L(self.v + o.v)
+
+    def __iadd__(self, o):
+        self.v += o.v
+        return self
+
+    def __repr__(self):
+        return "L(%s)" % self.v
+
+c = L([1, 2])
+d = c
+c += L([3, 4])
+print(c)
+# Should be updated c's value, i.e. L([1, 2, 3, 4])
+print(d)
diff --git a/tests/basics/class_new.py b/tests/basics/class_new.py
index 9a7072ad03..1f6a86c648 100644
--- a/tests/basics/class_new.py
+++ b/tests/basics/class_new.py
@@ -5,13 +5,14 @@ try:
 except AttributeError:
     print("SKIP")
     raise SystemExit
+
 class A:
     def __new__(cls):
         print("A.__new__")
         return super(cls, A).__new__(cls)
 
     def __init__(self):
-        pass
+        print("A.__init__")
 
     def meth(self):
         print('A.meth')
@@ -33,7 +34,33 @@ a.meth()
 a = a.__new__(A)
 a.meth()
 
+# __new__ returns not an instance of the class (None here), __init__
+# should not be called
+
 class B:
     def __new__(self, v1, v2):
-        None
-B(1, 2)
+        print("B.__new__", v1, v2)
+
+    def __init__(self, v1, v2):
+        # Should not be called in this test
+        print("B.__init__", v1, v2)
+
+print("B inst:", B(1, 2))
+
+
+# Variation of the above, __new__ returns an instance of another class,
+# __init__ should not be called
+
+class Dummy: pass
+
+class C:
+    def __new__(cls):
+        print("C.__new__")
+        return Dummy()
+
+    def __init__(self):
+        # Should not be called in this test
+        print("C.__init__")
+
+c = C()
+print(isinstance(c, Dummy))
diff --git a/tests/basics/class_notimpl.py b/tests/basics/class_notimpl.py
new file mode 100644
index 0000000000..7fd8166f90
--- /dev/null
+++ b/tests/basics/class_notimpl.py
@@ -0,0 +1,50 @@
+# Test that returning of NotImplemented from binary op methods leads to
+# TypeError.
+try:
+    NotImplemented
+except NameError:
+    print("SKIP")
+    raise SystemExit
+
+class C:
+    def __init__(self, value):
+        self.value = value
+
+    def __str__(self):
+        return "C(%s)" % self.value
+
+    def __add__(self, rhs):
+        print(self, '+', rhs)
+        return NotImplemented
+
+    def __sub__(self, rhs):
+        print(self, '-', rhs)
+        return NotImplemented
+
+    def __lt__(self, rhs):
+        print(self, '<', rhs)
+        return NotImplemented
+
+    def __neg__(self):
+        print('-', self)
+        return NotImplemented
+
+c = C(0)
+
+try:
+    c + 1
+except TypeError:
+    print("TypeError")
+
+try:
+    c - 2
+except TypeError:
+    print("TypeError")
+
+try:
+    c < 1
+except TypeError:
+    print("TypeError")
+
+# NotImplemented isn't handled specially in unary methods
+print(-c)
diff --git a/tests/basics/class_reverse_op.py b/tests/basics/class_reverse_op.py
new file mode 100644
index 0000000000..d41c55c9d7
--- /dev/null
+++ b/tests/basics/class_reverse_op.py
@@ -0,0 +1,18 @@
+class A:
+
+    def __init__(self, v):
+        self.v = v
+
+    def __add__(self, o):
+        if isinstance(o, A):
+            return A(self.v + o.v)
+        return A(self.v + o)
+
+    def __radd__(self, o):
+        return A(self.v + o)
+
+    def __repr__(self):
+        return "A(%s)" % self.v
+
+print(A(3) + 1)
+print(2 + A(5))
diff --git a/tests/basics/int_big_zeroone.py b/tests/basics/int_big_zeroone.py
index 131d96c76b..81636724a5 100644
--- a/tests/basics/int_big_zeroone.py
+++ b/tests/basics/int_big_zeroone.py
@@ -1,15 +1,7 @@
 # test [0,-0,1,-1] edge cases of bignum
 
-# Skip if long ints are not supported.
-try:
-    # We have to use variables because 1 << 40 causes an exception on parse and
-    # cannot be caught.
-    x = 40
-    x = 1 << x
-except OverflowError:
-    print("SKIP")
-    import sys
-    sys.exit(1)
+import skip_if
+skip_if.no_bigint()
 
 long_zero = (2**64) >> 65
 long_neg_zero = -long_zero
diff --git a/tests/basics/int_longint_bytes.py b/tests/basics/int_longint_bytes.py
index 31510d75ad..42e445f539 100644
--- a/tests/basics/int_longint_bytes.py
+++ b/tests/basics/int_longint_bytes.py
@@ -1,13 +1,6 @@
 # Skip if long ints are not supported.
-try:
-    # We have to use variables because 1 << 40 causes an exception on parse and
-    # cannot be caught.
-    x = 40
-    x = 1 << x
-except OverflowError:
-    print("SKIP")
-    import sys
-    sys.exit(1)
+import skip_if
+skip_if.no_bigint()
 
 print((2**64).to_bytes(9, "little"))
 print(int.from_bytes(b"\x00\x01\0\0\0\0\0\0", "little"))
diff --git a/tests/basics/list_compare.py b/tests/basics/list_compare.py
index eea8814247..fd656c7f15 100644
--- a/tests/basics/list_compare.py
+++ b/tests/basics/list_compare.py
@@ -48,3 +48,13 @@ print([1] <= [1, 0])
 print([1] <= [1, -1])
 print([1, 0] <= [1])
 print([1, -1] <= [1])
+
+
+print([] == {})
+print([] != {})
+print([1] == (1,))
+
+try:
+    print([] < {})
+except TypeError:
+    print("TypeError")
diff --git a/tests/basics/object_new.py b/tests/basics/object_new.py
index a9c9482cbb..1bf7bc0ecb 100644
--- a/tests/basics/object_new.py
+++ b/tests/basics/object_new.py
@@ -12,6 +12,11 @@ except AttributeError:
 
 class Foo:
 
+    def __new__(cls):
+        # Should not be called in this test
+        print("in __new__")
+        raise RuntimeError
+
     def __init__(self):
         print("in __init__")
         self.attr = "something"
@@ -19,12 +24,13 @@ class Foo:
 
 o = object.__new__(Foo)
 #print(o)
-print(hasattr(o, "attr"))
-print(isinstance(o, Foo))
+print("Result of __new__ has .attr:", hasattr(o, "attr"))
+print("Result of __new__ is already a Foo:", isinstance(o, Foo))
+
 o.__init__()
 #print(dir(o))
-print(hasattr(o, "attr"))
-print(o.attr)
+print("After __init__ has .attr:", hasattr(o, "attr"))
+print(".attr:", o.attr)
 
 # should only be able to call __new__ on user types
 try:
diff --git a/tests/basics/set_binop.py b/tests/basics/set_binop.py
index 7848920b6a..bc76533b1f 100644
--- a/tests/basics/set_binop.py
+++ b/tests/basics/set_binop.py
@@ -47,6 +47,18 @@ s1 = s2 = set('abc')
 s1 -= set('ad')
 print(s1 is s2, len(s1))
 
+# RHS must be a set
+try:
+    print(set('12') >= '1')
+except TypeError:
+    print('TypeError')
+
+# RHS must be a set
+try:
+    print(set('12') <= '123')
+except TypeError:
+    print('TypeError')
+
 # unsupported operator
 try:
     set('abc') * 2
diff --git a/tests/basics/set_remove.py b/tests/basics/set_remove.py
index 5627516c43..0727239118 100644
--- a/tests/basics/set_remove.py
+++ b/tests/basics/set_remove.py
@@ -4,8 +4,8 @@ print(s.remove(1))
 print(list(s))
 try:
     print(s.remove(1), "!!!")
-except KeyError:
-    pass
+except KeyError as er:
+    print('KeyError', er.args[0])
 else:
     print("failed to raise KeyError")
 
diff --git a/tests/basics/string_endswith.py b/tests/basics/string_endswith.py
index 3e8fba925d..683562d10c 100644
--- a/tests/basics/string_endswith.py
+++ b/tests/basics/string_endswith.py
@@ -10,3 +10,8 @@ print("foobar".endswith("foobarbaz"))
 #print("1foo".startswith("1foo", 1))
 #print("1fo".startswith("foo", 1))
 #print("1fo".startswith("foo", 10))
+
+try:
+    "foobar".endswith(1)
+except TypeError:
+    print("TypeError")
diff --git a/tests/basics/string_endswith_upy.py b/tests/basics/string_endswith_upy.py
new file mode 100644
index 0000000000..06a4e71d2c
--- /dev/null
+++ b/tests/basics/string_endswith_upy.py
@@ -0,0 +1,6 @@
+# MicroPython doesn't support tuple argument
+
+try:
+    "foobar".endswith(("bar", "sth"))
+except TypeError:
+    print("TypeError")
diff --git a/tests/basics/string_endswith_upy.py.exp b/tests/basics/string_endswith_upy.py.exp
new file mode 100644
index 0000000000..6002b71c56
--- /dev/null
+++ b/tests/basics/string_endswith_upy.py.exp
@@ -0,0 +1 @@
+TypeError
diff --git a/tests/basics/string_startswith.py b/tests/basics/string_startswith.py
index 5cf730c03c..e63ae3c186 100644
--- a/tests/basics/string_startswith.py
+++ b/tests/basics/string_startswith.py
@@ -9,3 +9,8 @@ print("1foo".startswith("foo", 1))
 print("1foo".startswith("1foo", 1))
 print("1fo".startswith("foo", 1))
 print("1fo".startswith("foo", 10))
+
+try:
+    "foobar".startswith(1)
+except TypeError:
+    print("TypeError")
diff --git a/tests/basics/string_startswith_upy.py b/tests/basics/string_startswith_upy.py
new file mode 100644
index 0000000000..9ea1796c21
--- /dev/null
+++ b/tests/basics/string_startswith_upy.py
@@ -0,0 +1,6 @@
+# MicroPython doesn't support tuple argument
+
+try:
+    "foobar".startswith(("foo", "sth"))
+except TypeError:
+    print("TypeError")
diff --git a/tests/basics/string_startswith_upy.py.exp b/tests/basics/string_startswith_upy.py.exp
new file mode 100644
index 0000000000..6002b71c56
--- /dev/null
+++ b/tests/basics/string_startswith_upy.py.exp
@@ -0,0 +1 @@
+TypeError
diff --git a/tests/basics/string_strip.py b/tests/basics/string_strip.py
index 5d99a78e51..971a4aae53 100644
--- a/tests/basics/string_strip.py
+++ b/tests/basics/string_strip.py
@@ -32,6 +32,13 @@ print("a ".strip())
 print("a ".lstrip())
 print("a ".rstrip())
 
+# \0 used to give a problem
+
+print("\0abc\0".strip())
+print("\0abc\0".lstrip())
+print("\0abc\0".rstrip())
+print("\0abc\0".strip("\0"))
+
 # Test that stripping unstrippable string returns original object
 s = "abc"
 print(id(s.strip()) == id(s))
diff --git a/tests/basics/struct1.py b/tests/basics/struct1.py
index a442beb1e5..db34342a17 100644
--- a/tests/basics/struct1.py
+++ b/tests/basics/struct1.py
@@ -39,6 +39,12 @@ print(v == (10, 100, 200, 300))
 # network byte order
 print(struct.pack('!i', 123))
 
+# check that we get an error if the buffer is too small
+try:
+    struct.unpack('I', b'\x00\x00\x00')
+except:
+    print('struct.error')
+
 # first arg must be a string
 try:
     struct.pack(1, 2)
@@ -63,6 +69,12 @@ print(buf)
 struct.pack_into('<bbb', buf, -6, 0x44, 0x45, 0x46)
 print(buf)
 
+# check that we get an error if the buffer is too small
+try:
+    struct.pack_into('I', bytearray(1), 0, 0)
+except:
+    print('struct.error')
+
 try:
     struct.pack_into('<bbb', buf, 7, 0x41, 0x42, 0x43)
 except:
diff --git a/tests/basics/struct2.py b/tests/basics/struct2.py
index 3b9dd5c1f6..ceb0677769 100644
--- a/tests/basics/struct2.py
+++ b/tests/basics/struct2.py
@@ -25,6 +25,16 @@ print(struct.calcsize('0s1s0H2H'))
 print(struct.unpack('<0s1s0H2H', b'01234'))
 print(struct.pack('<0s1s0H2H', b'abc', b'abc', 258, 515))
 
+# check that we get an error if the buffer is too small
+try:
+    struct.unpack('2H', b'\x00\x00')
+except:
+    print('Exception')
+try:
+    struct.pack_into('2I', bytearray(4), 0, 0)
+except:
+    print('Exception')
+
 # check that unknown types raise an exception
 try:
     struct.unpack('z', b'1')
diff --git a/tests/basics/struct_micropython.py b/tests/basics/struct_micropython.py
index 4b9dfe1378..f203a4666f 100644
--- a/tests/basics/struct_micropython.py
+++ b/tests/basics/struct_micropython.py
@@ -18,6 +18,9 @@ s = struct.pack("<O", o)
 o2 = struct.unpack("<O", s)
 print(o is o2[0])
 
+# pack can accept less arguments than required for the format spec
+print(struct.pack('<2I', 1))
+
 # pack and unpack pointer to a string
 # This requires uctypes to get the address of the string and instead of
 # putting this in a dedicated test that can be skipped we simply pass
diff --git a/tests/basics/struct_micropython.py.exp b/tests/basics/struct_micropython.py.exp
index 0ca95142bb..55b7b6623f 100644
--- a/tests/basics/struct_micropython.py.exp
+++ b/tests/basics/struct_micropython.py.exp
@@ -1 +1,2 @@
 True
+b'\x01\x00\x00\x00\x00\x00\x00\x00'
diff --git a/tests/basics/tuple_compare.py b/tests/basics/tuple_compare.py
index ad813f7029..9558eb1db4 100644
--- a/tests/basics/tuple_compare.py
+++ b/tests/basics/tuple_compare.py
@@ -53,3 +53,13 @@ print((10, 0) > (1, 1))
 print((10, 0) < (1, 1))
 print((0, 0, 10, 0) > (0, 0, 1, 1))
 print((0, 0, 10, 0) < (0, 0, 1, 1))
+
+
+print(() == {})
+print(() != {})
+print((1,) == [1])
+
+try:
+    print(() < {})
+except TypeError:
+    print("TypeError")
diff --git a/tests/cmdline/cmd_showbc.py.exp b/tests/cmdline/cmd_showbc.py.exp
index 1e015eb03c..09fbff6fad 100644
--- a/tests/cmdline/cmd_showbc.py.exp
+++ b/tests/cmdline/cmd_showbc.py.exp
@@ -43,9 +43,9 @@ Raw bytecode (code_info_size=\\d\+, bytecode_size=\\d\+):
   bc=\\d\+ line=126
 00 LOAD_CONST_NONE
 01 LOAD_CONST_FALSE
-02 BINARY_OP 5 __add__
+02 BINARY_OP 28 __add__
 03 LOAD_CONST_TRUE
-04 BINARY_OP 5 __add__
+04 BINARY_OP 28 __add__
 05 STORE_FAST 0
 06 LOAD_CONST_SMALL_INT 0
 07 STORE_FAST 0
@@ -84,34 +84,34 @@ Raw bytecode (code_info_size=\\d\+, bytecode_size=\\d\+):
 \\d\+ STORE_FAST 7
 \\d\+ LOAD_FAST 0
 \\d\+ LOAD_DEREF 14
-\\d\+ BINARY_OP 5 __add__
+\\d\+ BINARY_OP 28 __add__
 \\d\+ STORE_FAST 8
 \\d\+ LOAD_FAST 0
-\\d\+ UNARY_OP 4
+\\d\+ UNARY_OP 1
 \\d\+ STORE_FAST 9
 \\d\+ LOAD_FAST 0
-\\d\+ UNARY_OP 6
+\\d\+ UNARY_OP 3
 \\d\+ STORE_FAST 10
 \\d\+ LOAD_FAST 0
 \\d\+ LOAD_DEREF 14
 \\d\+ DUP_TOP
 \\d\+ ROT_THREE
-\\d\+ BINARY_OP 27 __eq__
+\\d\+ BINARY_OP 2 __eq__
 \\d\+ JUMP_IF_FALSE_OR_POP \\d\+
 \\d\+ LOAD_FAST 1
-\\d\+ BINARY_OP 27 __eq__
+\\d\+ BINARY_OP 2 __eq__
 \\d\+ JUMP \\d\+
 \\d\+ ROT_TWO
 \\d\+ POP_TOP
 \\d\+ STORE_FAST 10
 \\d\+ LOAD_FAST 0
 \\d\+ LOAD_DEREF 14
-\\d\+ BINARY_OP 27 __eq__
+\\d\+ BINARY_OP 2 __eq__
 \\d\+ JUMP_IF_FALSE_OR_POP \\d\+
 \\d\+ LOAD_DEREF 14
 \\d\+ LOAD_FAST 1
-\\d\+ BINARY_OP 27 __eq__
-\\d\+ UNARY_OP 6
+\\d\+ BINARY_OP 2 __eq__
+\\d\+ UNARY_OP 3
 \\d\+ STORE_FAST 10
 \\d\+ LOAD_DEREF 14
 \\d\+ LOAD_ATTR c (cache=0)
@@ -132,7 +132,7 @@ Raw bytecode (code_info_size=\\d\+, bytecode_size=\\d\+):
 \\d\+ DUP_TOP_TWO
 \\d\+ LOAD_SUBSCR
 \\d\+ LOAD_FAST 12
-\\d\+ BINARY_OP 18 __iadd__
+\\d\+ BINARY_OP 16 __iadd__
 \\d\+ ROT_THREE
 \\d\+ STORE_SUBSCR
 \\d\+ LOAD_DEREF 14
@@ -369,7 +369,7 @@ Raw bytecode (code_info_size=\\d\+, bytecode_size=\\d\+):
 42 STORE_FAST_N 19
 44 LOAD_FAST 9
 45 LOAD_FAST_N 19
-47 BINARY_OP 5 __add__
+47 BINARY_OP 28 __add__
 48 POP_TOP
 49 LOAD_CONST_NONE
 50 RETURN_VALUE
@@ -521,7 +521,7 @@ arg names: *
   bc=\\d\+ line=113
 00 LOAD_DEREF 0
 02 LOAD_CONST_SMALL_INT 1
-03 BINARY_OP 5 __add__
+03 BINARY_OP 28 __add__
 04 STORE_FAST 1
 05 LOAD_CONST_SMALL_INT 1
 06 STORE_DEREF 0
@@ -540,7 +540,7 @@ arg names: * b
   bc=\\d\+ line=139
 00 LOAD_FAST 1
 01 LOAD_DEREF 0
-03 BINARY_OP 5 __add__
+03 BINARY_OP 28 __add__
 04 RETURN_VALUE
 mem: total=\\d\+, current=\\d\+, peak=\\d\+
 stack: \\d\+ out of \\d\+
diff --git a/tests/cpydiff/core_locals.py b/tests/cpydiff/core_locals.py
new file mode 100644
index 0000000000..0240e5a1a9
--- /dev/null
+++ b/tests/cpydiff/core_locals.py
@@ -0,0 +1,11 @@
+"""
+categories: Core,Runtime
+description: Local variables aren't included in locals() result
+cause: MicroPython doesn't maintain symbolic local environment, it is optimized to an array of slots. Thus, local variables can't be accessed by a name.
+workaround: Unknown
+"""
+def test():
+    val = 2
+    print(locals())
+
+test()
diff --git a/tests/cpydiff/core_locals_eval.py b/tests/cpydiff/core_locals_eval.py
new file mode 100644
index 0000000000..8416e3b069
--- /dev/null
+++ b/tests/cpydiff/core_locals_eval.py
@@ -0,0 +1,14 @@
+"""
+categories: Core,Runtime
+description: Code running in eval() function doesn't have access to local variables
+cause: MicroPython doesn't maintain symbolic local environment, it is optimized to an array of slots. Thus, local variables can't be accessed by a name. Effectively, ``eval(expr)`` in MicroPython is equivalent to ``eval(expr, globals(), globals())``.
+workaround: Unknown
+"""
+val = 1
+
+def test():
+    val = 2
+    print(val)
+    eval("print(val)")
+
+test()
diff --git a/tests/extmod/ure_stack_overflow.py b/tests/extmod/ure_stack_overflow.py
new file mode 100644
index 0000000000..d3ce0c5a7b
--- /dev/null
+++ b/tests/extmod/ure_stack_overflow.py
@@ -0,0 +1,13 @@
+try:
+    import ure as re
+except ImportError:
+    try:
+        import re
+    except ImportError:
+        print("SKIP")
+        raise SystemExit
+
+try:
+    re.match("(a*)*", "aaa")
+except RuntimeError:
+    print("RuntimeError")
diff --git a/tests/extmod/ure_stack_overflow.py.exp b/tests/extmod/ure_stack_overflow.py.exp
new file mode 100644
index 0000000000..8a2b9bfdda
--- /dev/null
+++ b/tests/extmod/ure_stack_overflow.py.exp
@@ -0,0 +1 @@
+RuntimeError
diff --git a/tests/feature_check/reverse_ops.py b/tests/feature_check/reverse_ops.py
new file mode 100644
index 0000000000..668748bc57
--- /dev/null
+++ b/tests/feature_check/reverse_ops.py
@@ -0,0 +1,9 @@
+class Foo:
+
+    def __radd__(self, other):
+        pass
+
+try:
+    5 + Foo()
+except TypeError:
+    print("TypeError")
diff --git a/tests/feature_check/reverse_ops.py.exp b/tests/feature_check/reverse_ops.py.exp
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/tests/float/complex1.py b/tests/float/complex1.py
index a6038de04a..8544105453 100644
--- a/tests/float/complex1.py
+++ b/tests/float/complex1.py
@@ -37,6 +37,11 @@ ans = 1j ** 2.5j; print("%.5g %.5g" % (ans.real, ans.imag))
 print(1j == 1)
 print(1j == 1j)
 
+# comparison of nan is special
+nan = float('nan') * 1j
+print(nan == 1j)
+print(nan == nan)
+
 # builtin abs
 print(abs(1j))
 print("%.5g" % abs(1j + 2))
@@ -48,6 +53,10 @@ print(type(hash(1j)))
 # float on lhs should delegate to complex
 print(1.2 + 3j)
 
+# negative base and fractional power should create a complex
+ans = (-1) ** 2.3; print("%.5g %.5g" % (ans.real, ans.imag))
+ans = (-1.2) ** -3.4; print("%.5g %.5g" % (ans.real, ans.imag))
+
 # check printing of inf/nan
 print(float('nan') * 1j)
 print(float('inf') * (1 + 1j))
diff --git a/tests/float/float1.py b/tests/float/float1.py
index 93f6f014c4..137dacc233 100644
--- a/tests/float/float1.py
+++ b/tests/float/float1.py
@@ -60,6 +60,11 @@ print(1.2 <= -3.4)
 print(1.2 >= 3.4)
 print(1.2 >= -3.4)
 
+# comparison of nan is special
+nan = float('nan')
+print(nan == 1.2)
+print(nan == nan)
+
 try:
     1.0 / 0
 except ZeroDivisionError:
diff --git a/tests/float/float_compare.py b/tests/float/float_compare.py
new file mode 100644
index 0000000000..105923ac73
--- /dev/null
+++ b/tests/float/float_compare.py
@@ -0,0 +1,22 @@
+# Extended float comparisons
+
+class Foo:
+    pass
+
+foo = Foo()
+
+print(foo == 1.0)
+print(1.0 == foo)
+print(1.0 == Foo)
+print(1.0 == [])
+print(1.0 == {})
+
+try:
+    print(foo < 1.0)
+except TypeError:
+    print("TypeError")
+
+try:
+    print(1.0 < foo)
+except TypeError:
+    print("TypeError")
diff --git a/tests/micropython/emg_exc.py b/tests/micropython/emg_exc.py
index d228e6faab..4a9fa18bc1 100644
--- a/tests/micropython/emg_exc.py
+++ b/tests/micropython/emg_exc.py
@@ -2,6 +2,11 @@
 
 import micropython
 import sys
+try:
+    import uio
+except ImportError:
+    print("SKIP")
+    raise SystemExit
 
 # some ports need to allocate heap for the emg exc
 try:
@@ -14,7 +19,16 @@ def f():
     try:
         raise ValueError(1)
     except ValueError as er:
-        sys.print_exception(er)
+        exc = er
     micropython.heap_unlock()
 
+    # print the exception
+    buf = uio.StringIO()
+    sys.print_exception(exc, buf)
+    for l in buf.getvalue().split("\n"):
+        if l.startswith("  File "):
+            print(l.split('"')[2])
+        else:
+            print(l)
+
 f()
diff --git a/tests/micropython/emg_exc.py.exp b/tests/micropython/emg_exc.py.exp
index 82b10b5f54..fd2cfb2722 100644
--- a/tests/micropython/emg_exc.py.exp
+++ b/tests/micropython/emg_exc.py.exp
@@ -1 +1,4 @@
-ValueError: 
+Traceback (most recent call last):
+, line 20, in f
+ValueError: 1
+
diff --git a/tests/misc/non_compliant.py b/tests/misc/non_compliant.py
index e1ea66e69e..8c2f4184b1 100644
--- a/tests/misc/non_compliant.py
+++ b/tests/misc/non_compliant.py
@@ -39,18 +39,6 @@ try:
 except NotImplementedError:
     print('NotImplementedError')
 
-# should raise type error
-try:
-    print(set('12') >= '1')
-except TypeError:
-    print('TypeError')
-
-# should raise type error
-try:
-    print(set('12') <= '123')
-except TypeError:
-    print('TypeError')
-
 # uPy raises TypeError, shold be ValueError
 try:
     '%c' % b'\x01\x02'
diff --git a/tests/misc/non_compliant.py.exp b/tests/misc/non_compliant.py.exp
index ba5590acc0..9c157fd5bd 100644
--- a/tests/misc/non_compliant.py.exp
+++ b/tests/misc/non_compliant.py.exp
@@ -3,8 +3,6 @@ AttributeError
 TypeError
 NotImplementedError
 NotImplementedError
-True
-True
 TypeError, ValueError
 NotImplementedError
 NotImplementedError
diff --git a/tests/run-bench-tests b/tests/run-bench-tests
index d48b4b7ec5..f4a6776cbc 100755
--- a/tests/run-bench-tests
+++ b/tests/run-bench-tests
@@ -13,10 +13,10 @@ from collections import defaultdict
 # to the correct executable.
 if os.name == 'nt':
     CPYTHON3 = os.getenv('MICROPY_CPYTHON3', 'python3.exe')
-    MICROPYTHON = os.getenv('MICROPY_MICROPYTHON', '../windows/micropython.exe')
+    MICROPYTHON = os.getenv('MICROPY_MICROPYTHON', '../ports/windows/micropython.exe')
 else:
     CPYTHON3 = os.getenv('MICROPY_CPYTHON3', 'python3')
-    MICROPYTHON = os.getenv('MICROPY_MICROPYTHON', '../unix/micropython')
+    MICROPYTHON = os.getenv('MICROPY_MICROPYTHON', '../ports/unix/micropython')
 
 def run_tests(pyb, test_dict):
     test_count = 0
diff --git a/tests/run-tests b/tests/run-tests
index 304c5e21a3..4024d61df3 100755
--- a/tests/run-tests
+++ b/tests/run-tests
@@ -13,10 +13,10 @@ from glob import glob
 # to the correct executable.
 if os.name == 'nt':
     CPYTHON3 = os.getenv('MICROPY_CPYTHON3', 'python3.exe')
-    MICROPYTHON = os.getenv('MICROPY_MICROPYTHON', '../windows/micropython.exe')
+    MICROPYTHON = os.getenv('MICROPY_MICROPYTHON', '../ports/windows/micropython.exe')
 else:
     CPYTHON3 = os.getenv('MICROPY_CPYTHON3', 'python3')
-    MICROPYTHON = os.getenv('MICROPY_MICROPYTHON', '../unix/micropython')
+    MICROPYTHON = os.getenv('MICROPY_MICROPYTHON', '../ports/unix/micropython')
 
 # mpy-cross is only needed if --via-mpy command-line arg is passed
 MPYCROSS = os.getenv('MICROPY_MPYCROSS', '../mpy-cross/mpy-cross')
@@ -103,7 +103,7 @@ def run_micropython(pyb, args, test_file, is_special=False):
                         os.close(master)
                         os.close(slave)
                 else:
-                    output_mupy = subprocess.check_output(args + [test_file])
+                    output_mupy = subprocess.check_output(args + [test_file], stderr=subprocess.STDOUT)
             except subprocess.CalledProcessError:
                 return b'CRASH'
 
@@ -124,7 +124,7 @@ def run_micropython(pyb, args, test_file, is_special=False):
 
             # run the actual test
             e = {"MICROPYPATH": os.getcwd() + ":", "LANG": "en_US.UTF-8"}
-            p = subprocess.Popen(cmdlist, env=e, stdout=subprocess.PIPE)
+            p = subprocess.Popen(cmdlist, env=e, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
             output_mupy = b''
             while p.poll() is None:
                 output_mupy += p.stdout.read()
@@ -211,32 +211,38 @@ def run_tests(pyb, tests, args, base_path="."):
     skip_set_type = False
     skip_async = False
     skip_const = False
+    skip_revops = False
 
     # Check if micropython.native is supported, and skip such tests if it's not
-    native = run_feature_check(pyb, args, base_path, 'native_check.py')
-    if native == b'CRASH':
+    output = run_feature_check(pyb, args, base_path, 'native_check.py')
+    if output == b'CRASH':
         skip_native = True
 
     # Check if arbitrary-precision integers are supported, and skip such tests if it's not
-    native = run_feature_check(pyb, args, base_path, 'int_big.py')
-    if native != b'1000000000000000000000000000000000000000000000\n':
+    output = run_feature_check(pyb, args, base_path, 'int_big.py')
+    if output != b'1000000000000000000000000000000000000000000000\n':
         skip_int_big = True
 
     # Check if set type (and set literals) is supported, and skip such tests if it's not
-    native = run_feature_check(pyb, args, base_path, 'set_check.py')
-    if native == b'CRASH':
+    output = run_feature_check(pyb, args, base_path, 'set_check.py')
+    if output == b'CRASH':
         skip_set_type = True
 
     # Check if async/await keywords are supported, and skip such tests if it's not
-    native = run_feature_check(pyb, args, base_path, 'async_check.py')
-    if native == b'CRASH':
+    output = run_feature_check(pyb, args, base_path, 'async_check.py')
+    if output == b'CRASH':
         skip_async = True
 
     # Check if const keyword (MicroPython extension) is supported, and skip such tests if it's not
-    native = run_feature_check(pyb, args, base_path, 'const.py')
-    if native == b'CRASH':
+    output = run_feature_check(pyb, args, base_path, 'const.py')
+    if output == b'CRASH':
         skip_const = True
 
+    # Check if __rOP__ special methods are supported, and skip such tests if it's not
+    output = run_feature_check(pyb, args, base_path, 'reverse_ops.py')
+    if output == b'TypeError\n':
+        skip_revops = True
+
     # Check if emacs repl is supported, and skip such tests if it's not
     t = run_feature_check(pyb, args, base_path, 'repl_emacs_check.py')
     if not 'True' in str(t, 'ascii'):
@@ -306,6 +312,7 @@ def run_tests(pyb, tests, args, base_path="."):
         elif args.target == 'esp8266':
             skip_tests.add('misc/rge_sm.py')                # too large
         elif args.target == 'minimal':
+            skip_tests.add('basics/class_inplace_op.py')    # all special methods not supported
             skip_tests.add('misc/rge_sm.py')                # too large
             skip_tests.add('micropython/opt_level.py')      # don't assume line numbers are stored
 
@@ -342,6 +349,7 @@ def run_tests(pyb, tests, args, base_path="."):
         skip_tests.add('misc/rge_sm.py') # requires yield
         skip_tests.add('misc/print_exception.py') # because native doesn't have proper traceback info
         skip_tests.add('misc/sys_exc_info.py') # sys.exc_info() is not supported for native
+        skip_tests.add('micropython/emg_exc.py') # because native doesn't have proper traceback info
         skip_tests.add('micropython/heapalloc_traceback.py') # because native doesn't have proper traceback info
         skip_tests.add('micropython/heapalloc_iter.py') # requires generators
         skip_tests.add('micropython/schedule.py') # native code doesn't check pending events
@@ -364,6 +372,7 @@ def run_tests(pyb, tests, args, base_path="."):
         skip_it |= skip_set_type and is_set_type
         skip_it |= skip_async and is_async
         skip_it |= skip_const and is_const
+        skip_it |= skip_revops and test_name.startswith("class_reverse_op")
 
         if skip_it:
             print("skip ", test_file)
diff --git a/tests/unicode/unicode.py b/tests/unicode/unicode.py
index 5f29bc1c95..3a35ce8948 100644
--- a/tests/unicode/unicode.py
+++ b/tests/unicode/unicode.py
@@ -33,3 +33,17 @@ try:
     int('\u0200')
 except ValueError:
     print('ValueError')
+
+# test invalid UTF-8 string
+try:
+    str(b'ab\xa1', 'utf8')
+except UnicodeError:
+    print('UnicodeError')
+try:
+    str(b'ab\xf8', 'utf8')
+except UnicodeError:
+    print('UnicodeError')
+try:
+    str(bytearray(b'ab\xc0a'), 'utf8')
+except UnicodeError:
+    print('UnicodeError')
diff --git a/tests/unix/extra_coverage.py.exp b/tests/unix/extra_coverage.py.exp
index ab638a632d..4c4f666639 100644
--- a/tests/unix/extra_coverage.py.exp
+++ b/tests/unix/extra_coverage.py.exp
@@ -18,7 +18,8 @@ sts
 
 test
 tes
-larg
+RuntimeError: 
+RuntimeError: 
 # repl
 ame__
 
@@ -38,7 +39,7 @@ ementation
 0
 0
 # runtime utils
-TypeError: can't convert str to int
+TypeError: unsupported type for : 'str'
 TypeError: unsupported types for : 'str', 'str'
 Warning: test
 # format float
diff --git a/tools/build_adafruit_bins.sh b/tools/build_adafruit_bins.sh
index e075b5f69c..c7488f28a9 100755
--- a/tools/build_adafruit_bins.sh
+++ b/tools/build_adafruit_bins.sh
@@ -1,15 +1,20 @@
-rm -rf atmel-samd/build*
-rm -rf esp8266/build*
+rm -rf ports/atmel-samd/build*
+rm -rf ports/esp8266/build*
 
 ATMEL_BOARDS="arduino_zero circuitplayground_express feather_m0_basic feather_m0_adalogger feather_m0_express metro_m0_express metro_m4_express trinket_m0 gemma_m0"
 ROSIE_SETUPS="rosie-ci"
 
+PARALLEL="-j 5"
+if [ "$TRAVIS" == "true" ]; then
+    PARALLEL="-j 2"
+fi
+
 for board in $ATMEL_BOARDS; do
-    make -C atmel-samd BOARD=$board
+    make $PARALLEL -C ports/atmel-samd BOARD=$board
     (( exit_status = exit_status || $? ))
 done
 if [ -z "$TRAVIS" ]; then
-    make -C esp8266 BOARD=feather_huzzah
+    make $PARALLEL -C ports/esp8266 BOARD=feather_huzzah
     (( exit_status = exit_status || $? ))
 fi
 
@@ -29,9 +34,9 @@ fi
 
 for board in $ATMEL_BOARDS; do
     mkdir -p bin/$board/
-    cp atmel-samd/build-$board/firmware.bin bin/$board/adafruit-circuitpython-$board-$version.bin
+    cp ports/atmel-samd/build-$board/firmware.bin bin/$board/adafruit-circuitpython-$board-$version.bin
     (( exit_status = exit_status || $? ))
-    cp atmel-samd/build-$board/firmware.uf2 bin/$board/adafruit-circuitpython-$board-$version.uf2
+    cp ports/atmel-samd/build-$board/firmware.uf2 bin/$board/adafruit-circuitpython-$board-$version.uf2
     (( exit_status = exit_status || $? ))
     # Only upload to Rosie if its a pull request.
     if [ "$TRAVIS" == "true" ]; then
@@ -45,7 +50,7 @@ done
 # Skip ESP8266 on Travis
 if [ -z "$TRAVIS" ]; then
     mkdir -p bin/esp8266/
-    cp esp8266/build/firmware-combined.bin bin/esp8266/adafruit-circuitpython-feather_huzzah-$version.bin
+    cp ports/esp8266/build/firmware-combined.bin bin/esp8266/adafruit-circuitpython-feather_huzzah-$version.bin
     (( exit_status = exit_status || $? ))
 fi
 
diff --git a/tools/check_code_size.sh b/tools/check_code_size.sh
index c5f0c6ffdd..2925ff1689 100755
--- a/tools/check_code_size.sh
+++ b/tools/check_code_size.sh
@@ -10,7 +10,7 @@ REFERENCE=$HOME/persist/firmware.bin
 
 if [ -f $REFERENCE ]; then
     size_old=$(stat -c%s $REFERENCE)
-    size_new=$(stat -c%s minimal/build/firmware.bin)
+    size_new=$(stat -c%s ports/minimal/build/firmware.bin)
     echo "Old size: $size_old new size: $size_new"
     if [ $size_new -gt $size_old ]; then
         echo "Validation failure: Core code size increased"
diff --git a/tools/codestats.sh b/tools/codestats.sh
index 5272f3e9c1..09284a30de 100755
--- a/tools/codestats.sh
+++ b/tools/codestats.sh
@@ -9,7 +9,7 @@
 # executing because it does not exist in old revisions of the repository.
 
 # check that we are in the root directory of the repository
-if [ ! -d py -o ! -d unix -o ! -d stmhal ]; then
+if [ ! -d py -o ! -d ports/unix -o ! -d ports/stm32 ]; then
     echo "script must be run from root of the repository"
     exit 1
 fi
@@ -23,18 +23,18 @@ AWK=awk
 MAKE="make -j2"
 
 # these are the binaries that are built; some have 2 or 3 depending on version
-bin_unix=unix/micropython
-bin_stmhal=stmhal/build-PYBV10/firmware.elf
-bin_barearm_1=bare-arm/build/flash.elf
-bin_barearm_2=bare-arm/build/firmware.elf
-bin_minimal=minimal/build/firmware.elf
-bin_cc3200_1=cc3200/build/LAUNCHXL/application.axf
-bin_cc3200_2=cc3200/build/LAUNCHXL/release/application.axf
-bin_cc3200_3=cc3200/build/WIPY/release/application.axf
+bin_unix=ports/unix/micropython
+bin_stm32=ports/stm32/build-PYBV10/firmware.elf
+bin_barearm_1=ports/bare-arm/build/flash.elf
+bin_barearm_2=ports/bare-arm/build/firmware.elf
+bin_minimal=ports/minimal/build/firmware.elf
+bin_cc3200_1=ports/cc3200/build/LAUNCHXL/application.axf
+bin_cc3200_2=ports/cc3200/build/LAUNCHXL/release/application.axf
+bin_cc3200_3=ports/cc3200/build/WIPY/release/application.axf
 
 # start at zero size; if build fails reuse previous valid size
 size_unix="0"
-size_stmhal="0"
+size_stm32="0"
 size_barearm="0"
 size_minimal="0"
 size_cc3200="0"
@@ -86,7 +86,7 @@ function get_size3() {
 if [ -r $output ]; then
     last_rev=$(tail -n1 $output | $AWK '{print $1}')
 else
-    echo "# hash size_unix size_stmhal size_barearm size_minimal size_cc3200 pystones" > $output
+    echo "# hash size_unix size_stm32 size_barearm size_minimal size_cc3200 pystones" > $output
     last_rev="v1.0"
 fi
 
@@ -132,37 +132,37 @@ EOF
     #### unix ####
 
     $RM $bin_unix
-    $MAKE -C unix CFLAGS_EXTRA=-DNDEBUG
+    $MAKE -C ports/unix CFLAGS_EXTRA=-DNDEBUG
     size_unix=$(get_size $size_unix $bin_unix)
 
     # undo patch if it was applied
     git checkout unix/modtime.c
 
-    #### stmhal ####
+    #### stm32 ####
 
-    $RM $bin_stmhal
-    $MAKE -C stmhal board=PYBV10
-    size_stmhal=$(get_size $size_stmhal $bin_stmhal)
+    $RM $bin_stm32
+    $MAKE -C ports/stm32 board=PYBV10
+    size_stm32=$(get_size $size_stm32 $bin_stm32)
 
     #### bare-arm ####
 
     $RM $bin_barearm_1 $bin_barearm_2
-    $MAKE -C bare-arm
+    $MAKE -C ports/bare-arm
     size_barearm=$(get_size2 $size_barearm $bin_barearm_1 $bin_barearm_2)
 
     #### minimal ####
 
-    if [ -r minimal/Makefile ]; then
+    if [ -r ports/minimal/Makefile ]; then
         $RM $bin_minimal
-        $MAKE -C minimal CROSS=1
+        $MAKE -C ports/minimal CROSS=1
         size_minimal=$(get_size $size_minimal $bin_minimal)
     fi
 
     #### cc3200 ####
 
-    if [ -r cc3200/Makefile ]; then
+    if [ -r ports/cc3200/Makefile ]; then
         $RM $bin_cc3200_1 $bin_cc3200_2 $bin_cc3200_3
-        $MAKE -C cc3200 BTARGET=application
+        $MAKE -C ports/cc3200 BTARGET=application
         size_cc3200=$(get_size3 $size_cc3200 $bin_cc3200_1 $bin_cc3200_2 $bin_cc3200_3)
     fi
 
@@ -178,7 +178,7 @@ EOF
 
     #### output data for this commit ####
 
-    echo "$hash $size_unix $size_stmhal $size_barearm $size_minimal $size_cc3200 $pystones" >> $output
+    echo "$hash $size_unix $size_stm32 $size_barearm $size_minimal $size_cc3200 $pystones" >> $output
 
 done
 
diff --git a/tools/upip.py b/tools/upip.py
index 7b85c718f2..411da49e8c 100644
--- a/tools/upip.py
+++ b/tools/upip.py
@@ -122,7 +122,7 @@ def url_open(url):
         s.connect(addr)
 
         if proto == "https:":
-            s = ussl.wrap_socket(s)
+            s = ussl.wrap_socket(s, server_hostname=host)
             if warn_ussl:
                 print("Warning: %s SSL certificate is not validated" % host)
                 warn_ussl = False
diff --git a/tools/upip_utarfile.py b/tools/upip_utarfile.py
index 65ce0bdca8..460ca2cd44 100644
--- a/tools/upip_utarfile.py
+++ b/tools/upip_utarfile.py
@@ -3,7 +3,7 @@ import uctypes
 # http://www.gnu.org/software/tar/manual/html_node/Standard.html
 TAR_HEADER = {
     "name": (uctypes.ARRAY | 0, uctypes.UINT8 | 100),
-    "size": (uctypes.ARRAY | 124, uctypes.UINT8 | 12),
+    "size": (uctypes.ARRAY | 124, uctypes.UINT8 | 11),
 }
 
 DIRTYPE = "dir"
@@ -75,8 +75,8 @@ class TarFile:
                 return None
 
             d = TarInfo()
-            d.name = str(h.name, "utf-8").rstrip()
-            d.size = int(bytes(h.size).rstrip(), 8)
+            d.name = str(h.name, "utf-8").rstrip("\0")
+            d.size = int(bytes(h.size), 8)
             d.type = [REGTYPE, DIRTYPE][d.name[-1] == "/"]
             self.subf = d.subf = FileSection(self.f, d.size, roundup(d.size, 512))
             return d
diff --git a/unix/modules/upip.py b/unix/modules/upip.py
deleted file mode 120000
index 20d52a4ab7..0000000000
--- a/unix/modules/upip.py
+++ /dev/null
@@ -1 +0,0 @@
-../../tools/upip.py
\ No newline at end of file
diff --git a/unix/modules/upip_utarfile.py b/unix/modules/upip_utarfile.py
deleted file mode 120000
index 1498862916..0000000000
--- a/unix/modules/upip_utarfile.py
+++ /dev/null
@@ -1 +0,0 @@
-../../tools/upip_utarfile.py
\ No newline at end of file